diff --git a/.bazelignore b/.bazelignore new file mode 100644 index 0000000000..7bfdcf03d8 --- /dev/null +++ b/.bazelignore @@ -0,0 +1,8 @@ +tools/ +dependencies/ +docker/ +etc/ +jenkins/ +docs/ + + diff --git a/flow/.bazelrc b/.bazelrc similarity index 51% rename from flow/.bazelrc rename to .bazelrc index 3e07f6a46f..b1d0bd32db 100644 --- a/flow/.bazelrc +++ b/.bazelrc @@ -1,2 +1,2 @@ build --incompatible_strict_action_env -try-import %workspace%/.user-bazelrc +try-import %workspace%/user.bazelrc diff --git a/.bazelversion b/.bazelversion new file mode 100644 index 0000000000..93c8ddab9f --- /dev/null +++ b/.bazelversion @@ -0,0 +1 @@ +7.6.0 diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json deleted file mode 100644 index f7582bb9eb..0000000000 --- a/.devcontainer/devcontainer.json +++ /dev/null @@ -1,13 +0,0 @@ -// Copyright (c) 2024 Antmicro -// SPDX-License-Identifier: Apache-2.0 - -{ - "image": "docker.io/openroad/orfs-lxqt:latest", - "forwardPorts": [6080], - "portsAttributes": { - "6080": { - "label": "desktop" - } - }, - "postAttachCommand": "bash /usr/local/share/desktop-init.sh" -} diff --git a/.dockerignore b/.dockerignore index 76a64bc3c1..971b76fa27 100644 --- a/.dockerignore +++ b/.dockerignore @@ -10,6 +10,11 @@ flow/reports flow/objects flow/tech +bazel-bin/ +bazel-obj/ +bazel-OpenROAD-flow-scripts/ +bazel-testlogs/ + # Tar archives flow/*tar.gz flow/run-me*.sh diff --git a/.github/workflows/black.yaml b/.github/workflows/black.yaml index d14d043183..117bbab072 100644 --- a/.github/workflows/black.yaml +++ b/.github/workflows/black.yaml @@ -1,11 +1,9 @@ name: Lint Python on: [push, pull_request] - jobs: lint: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - uses: actions/checkout@v3 - uses: psf/black@stable - diff --git a/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml b/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml index 6d5f57424c..e91e0633cc 100644 --- a/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml +++ b/.github/workflows/github-actions-cron-sync-fork-from-upstream.yml @@ -14,7 +14,7 @@ on: jobs: Sync-Branch-From-Upstream: name: Automatic sync 'master' from The-OpenROAD-Project/OpenROAD-flow-scripts - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} # Only allow one action to run at a time. concurrency: sync-branch-from-upstream diff --git a/.github/workflows/github-actions-cron-test-installer.yml b/.github/workflows/github-actions-cron-test-installer.yml index b2564f5db2..2a53fde91a 100644 --- a/.github/workflows/github-actions-cron-test-installer.yml +++ b/.github/workflows/github-actions-cron-test-installer.yml @@ -27,7 +27,7 @@ jobs: fail-fast: false matrix: os: ["ubuntu20.04", "ubuntu22.04"] - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v3 diff --git a/.github/workflows/github-actions-cron-update-OR.yml b/.github/workflows/github-actions-cron-update-OR.yml index 9704798a13..695bd621f0 100644 --- a/.github/workflows/github-actions-cron-update-OR.yml +++ b/.github/workflows/github-actions-cron-update-OR.yml @@ -7,7 +7,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code recursively uses: actions/checkout@v3 @@ -24,12 +24,16 @@ jobs: git pull - if: "steps.remote-update.outputs.has_update != ''" name: Create Draft PR - uses: peter-evans/create-pull-request@v6 + uses: peter-evans/create-pull-request@v7 with: token: ${{ github.token }} signoff: true delete-branch: true title: 'Update OpenROAD submodule' + body: | + Automated action to update tools/OpenROAD submodule and tighten CI rule checking. + [ci:rules-tighten] + labels: UpdateRules reviewers: | vvbandeira maliberty diff --git a/.github/workflows/github-actions-cron-update-yosys.yml b/.github/workflows/github-actions-cron-update-yosys.yml index b88a39c721..f19a27ebe5 100644 --- a/.github/workflows/github-actions-cron-update-yosys.yml +++ b/.github/workflows/github-actions-cron-update-yosys.yml @@ -8,7 +8,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code recursively uses: actions/checkout@v3 diff --git a/.github/workflows/github-actions-cron-util-test.yml b/.github/workflows/github-actions-cron-util-test.yml index b57089329b..dcfda4c78b 100644 --- a/.github/workflows/github-actions-cron-util-test.yml +++ b/.github/workflows/github-actions-cron-util-test.yml @@ -13,11 +13,11 @@ on: # Allows you to run this workflow manually from the Actions tab workflow_dispatch: -jobs: +jobs: testUtilScripts: strategy: fail-fast: false - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v3 @@ -33,4 +33,4 @@ jobs: cd flow/test for file in *.py; do python "$file" - done \ No newline at end of file + done diff --git a/.github/workflows/github-actions-lint-tcl.yml b/.github/workflows/github-actions-lint-tcl.yml new file mode 100644 index 0000000000..0399b50831 --- /dev/null +++ b/.github/workflows/github-actions-lint-tcl.yml @@ -0,0 +1,29 @@ +name: Lint Tcl code + +on: + push: + branches: + - master + pull_request: + branches: + - master + +jobs: + build: + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Install Dependencies + run: | + python3 -m venv venv + venv/bin/pip install tclint==0.4.2 + + - name: Lint + run: | + source venv/bin/activate + tclfmt --version + tclfmt --in-place . + git diff --exit-code + tclint --no-check-style . diff --git a/.github/workflows/github-actions-manual-update-rules.yml b/.github/workflows/github-actions-manual-update-rules.yml index fc10dae30d..cdcf2744e2 100644 --- a/.github/workflows/github-actions-manual-update-rules.yml +++ b/.github/workflows/github-actions-manual-update-rules.yml @@ -9,7 +9,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} strategy: fail-fast: false steps: @@ -22,15 +22,17 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source venv/bin/activate if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite - else + else python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) fi - name: Push updated rules diff --git a/.github/workflows/github-actions-on-delete-cleanup.yml b/.github/workflows/github-actions-on-delete-cleanup.yml index 7596854aad..5dc97769ad 100644 --- a/.github/workflows/github-actions-on-delete-cleanup.yml +++ b/.github/workflows/github-actions-on-delete-cleanup.yml @@ -12,7 +12,7 @@ jobs: Delete-From-Staging: name: Delete branch from staging - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} permissions: # Read-only access so we don't accidentally try to push to *this* repository. diff --git a/.github/workflows/github-actions-on-label-create.yml b/.github/workflows/github-actions-on-label-create.yml index 0befd29908..4e083dac8a 100644 --- a/.github/workflows/github-actions-on-label-create.yml +++ b/.github/workflows/github-actions-on-label-create.yml @@ -12,7 +12,7 @@ env: jobs: Push-To-Staging: name: Push to staging - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} permissions: # Read-only access so we don't accidentally try to push to *this* repository. diff --git a/.github/workflows/github-actions-on-push.yml b/.github/workflows/github-actions-on-push.yml index d95abd04bc..579beea403 100644 --- a/.github/workflows/github-actions-on-push.yml +++ b/.github/workflows/github-actions-on-push.yml @@ -8,12 +8,9 @@ on: jobs: scan: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v2 - name: run security_scan_on_push uses: The-OpenROAD-Project/actions/security_scan_on_push@main - - - diff --git a/.github/workflows/github-actions-publish-docker-images.yml b/.github/workflows/github-actions-publish-docker-images.yml index bf32946e50..476ec3220d 100644 --- a/.github/workflows/github-actions-publish-docker-images.yml +++ b/.github/workflows/github-actions-publish-docker-images.yml @@ -27,7 +27,7 @@ on: jobs: buildCodespaceImage: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} timeout-minutes: 600 steps: - uses: actions/checkout@v4 @@ -61,7 +61,7 @@ jobs: fail-fast: false matrix: os: [["ubuntu20.04", "ubuntu:20.04"], ["ubuntu22.04", "ubuntu:22.04"]] - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} steps: - name: Check out repository code uses: actions/checkout@v4 diff --git a/.github/workflows/github-actions-update-rules.yml b/.github/workflows/github-actions-update-rules.yml index c728f90df9..3355612ba5 100644 --- a/.github/workflows/github-actions-update-rules.yml +++ b/.github/workflows/github-actions-update-rules.yml @@ -6,7 +6,7 @@ on: jobs: update: - runs-on: ubuntu-latest + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} strategy: fail-fast: false steps: @@ -24,12 +24,14 @@ jobs: python-version: "3.10" - name: Install Python Packages run: | - pip install firebase-admin + python3 -m venv venv + venv/bin/pip install firebase-admin - name: Execute Python Script Update env: CREDS_FILE: ${{ secrets.CREDS_FILE }} API_BASE_URL: ${{ secrets.API_BASE_URL }} run: | + source ./venv/bin/activate echo ${{ github.event_name }} echo ${{ github.event.client_payload.type }} if [[ "${{ github.event_name }}" == "repository_dispatch" && "${{ github.event.client_payload.type }}" == "overwrite" ]]; then diff --git a/.github/workflows/github-actions-yaml-test.yml b/.github/workflows/github-actions-yaml-test.yml new file mode 100644 index 0000000000..704f34ab78 --- /dev/null +++ b/.github/workflows/github-actions-yaml-test.yml @@ -0,0 +1,36 @@ +name: ORFS variables.yaml tester and linter + +on: + pull_request: + +jobs: + docs-test-job: + name: 'Tests for variables.yaml' + if: github.event_name == 'pull_request' || github.event_name == 'push' + runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }} + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + fetch-depth: 1 + sparse-checkout: | + flow/scripts/generate-variables-docs.py + docs/user/FlowVariables.md + yamlfix.toml + - name: Run generate-variables-docs.py + run: | + python3 flow/scripts/generate-variables-docs.py + - name: Check if FlowVariables.md is up to date + run: | + git diff --exit-code docs/user/FlowVariables.md + - name: Install dependencies + run: | + python3 -m venv venv + venv/bin/pip install --quiet yamlfix==1.17.0 + - name: Run yamlfix check + run: | + source venv/bin/activate + yamlfix --version + set -x + yamlfix -c yamlfix.toml flow/scripts/variables.yaml + git diff flow/scripts/variables.yaml diff --git a/.gitignore b/.gitignore index 6f62f5c003..37ebf3fa79 100644 --- a/.gitignore +++ b/.gitignore @@ -29,7 +29,6 @@ flow/rc_model.bin flow/*.tif.gz flow/*.def.v - # RePlAce deps *PORT9.dat *POST9.dat @@ -87,7 +86,6 @@ perf.data.old # documentation specific docs/main docs/build -GitGuide.md SupportedOS.md index2.md Manpage.md @@ -98,3 +96,12 @@ build # autotuner artifacts metadata-base-at.json + +user.bazelrc +bazel-bin +bazel-out +bazel-OpenROAD-flow-scripts +bazel-testlogs + +# python venv +venv/ diff --git a/.gitmodules b/.gitmodules index bcda953424..ec90369ba8 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "tools/OpenROAD"] path = tools/OpenROAD url = ../OpenROAD.git +[submodule "tools/yosys-slang"] + path = tools/yosys-slang + url = https://github.com/povik/yosys-slang.git diff --git a/MODULE.bazel b/MODULE.bazel new file mode 100644 index 0000000000..574d678f5d --- /dev/null +++ b/MODULE.bazel @@ -0,0 +1,46 @@ +"""ORFS bazel setup.""" + +module( + name = "orfs", + version = "0.0.1", + compatibility_level = 1, +) + +bazel_dep(name = "bazel-orfs") + +# To bump version, run: bazelisk run @bazel-orfs//:bump +git_override( + module_name = "bazel-orfs", + commit = "f8a4b694b37c8f5322323eba9a9ae37f9541ee17", + remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", +) + +bazel_dep(name = "rules_python", version = "1.2.0") + +python = use_extension("@rules_python//python/extensions:python.bzl", "python") +python.toolchain( + ignore_root_user_error = True, + python_version = "3.13", +) + +pip = use_extension("@rules_python//python/extensions:pip.bzl", "pip") +pip.parse( + hub_name = "orfs-pip", + python_version = "3.13", + requirements_lock = "//flow:util/requirements_lock.txt", +) +use_repo(pip, "orfs-pip") + +orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") + +# To bump version, run: bazelisk run @bazel-orfs//:bump +orfs.default( + image = "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", + # Use local files instead of docker image + makefile = "//flow:makefile", + makefile_yosys = "//flow:makefile_yosys", + pdk = "//flow:asap7", + sha256 = "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", +) +use_repo(orfs, "com_github_nixos_patchelf_download") +use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock new file mode 100644 index 0000000000..45ece7112e --- /dev/null +++ b/MODULE.bazel.lock @@ -0,0 +1,4158 @@ +{ + "lockFileVersion": 13, + "registryFileHashes": { + "https://bcr.bazel.build/bazel_registry.json": "8a28e4aff06ee60aed2a8c281907fb8bcbf3b753c91fb5a5c57da3215d5b3497", + "https://bcr.bazel.build/modules/abseil-cpp/20210324.2/MODULE.bazel": "7cd0312e064fde87c8d1cd79ba06c876bd23630c83466e9500321be55c96ace2", + "https://bcr.bazel.build/modules/abseil-cpp/20211102.0/MODULE.bazel": "70390338f7a5106231d20620712f7cccb659cd0e9d073d1991c038eb9fc57589", + "https://bcr.bazel.build/modules/abseil-cpp/20230125.1/MODULE.bazel": "89047429cb0207707b2dface14ba7f8df85273d484c2572755be4bab7ce9c3a0", + "https://bcr.bazel.build/modules/abseil-cpp/20230802.0.bcr.1/MODULE.bazel": "1c8cec495288dccd14fdae6e3f95f772c1c91857047a098fad772034264cc8cb", + "https://bcr.bazel.build/modules/abseil-cpp/20230802.0/MODULE.bazel": "d253ae36a8bd9ee3c5955384096ccb6baf16a1b1e93e858370da0a3b94f77c16", + "https://bcr.bazel.build/modules/abseil-cpp/20230802.1/MODULE.bazel": "fa92e2eb41a04df73cdabeec37107316f7e5272650f81d6cc096418fe647b915", + "https://bcr.bazel.build/modules/abseil-cpp/20240116.1/MODULE.bazel": "37bcdb4440fbb61df6a1c296ae01b327f19e9bb521f9b8e26ec854b6f97309ed", + "https://bcr.bazel.build/modules/abseil-cpp/20240116.1/source.json": "9be551b8d4e3ef76875c0d744b5d6a504a27e3ae67bc6b28f46415fd2d2957da", + "https://bcr.bazel.build/modules/apple_support/1.5.0/MODULE.bazel": "50341a62efbc483e8a2a6aec30994a58749bd7b885e18dd96aa8c33031e558ef", + "https://bcr.bazel.build/modules/apple_support/1.5.0/source.json": "eb98a7627c0bc486b57f598ad8da50f6625d974c8f723e9ea71bd39f709c9862", + "https://bcr.bazel.build/modules/aspect_bazel_lib/2.8.1/MODULE.bazel": "812d2dd42f65dca362152101fbec418029cc8fd34cbad1a2fde905383d705838", + "https://bcr.bazel.build/modules/aspect_bazel_lib/2.8.1/source.json": "95a6b56904e2d8bfea164dc6c98ccafe8cb75cb0623cb6ef5b3cfb15fdddabd6", + "https://bcr.bazel.build/modules/aspect_rules_js/2.1.3/MODULE.bazel": "47cc48eec374d69dced3cf9b9e5926beac2f927441acfb1a3568bbb709b25666", + "https://bcr.bazel.build/modules/aspect_rules_js/2.1.3/source.json": "6b0fe67780c101430be087381b7a79d75eeebe1a1eae6a2cee937713603634ac", + "https://bcr.bazel.build/modules/bazel_features/1.1.1/MODULE.bazel": "27b8c79ef57efe08efccbd9dd6ef70d61b4798320b8d3c134fd571f78963dbcd", + "https://bcr.bazel.build/modules/bazel_features/1.11.0/MODULE.bazel": "f9382337dd5a474c3b7d334c2f83e50b6eaedc284253334cf823044a26de03e8", + "https://bcr.bazel.build/modules/bazel_features/1.15.0/MODULE.bazel": "d38ff6e517149dc509406aca0db3ad1efdd890a85e049585b7234d04238e2a4d", + "https://bcr.bazel.build/modules/bazel_features/1.17.0/MODULE.bazel": "039de32d21b816b47bd42c778e0454217e9c9caac4a3cf8e15c7231ee3ddee4d", + "https://bcr.bazel.build/modules/bazel_features/1.18.0/MODULE.bazel": "1be0ae2557ab3a72a57aeb31b29be347bcdc5d2b1eb1e70f39e3851a7e97041a", + "https://bcr.bazel.build/modules/bazel_features/1.19.0/MODULE.bazel": "59adcdf28230d220f0067b1f435b8537dd033bfff8db21335ef9217919c7fb58", + "https://bcr.bazel.build/modules/bazel_features/1.21.0/MODULE.bazel": "675642261665d8eea09989aa3b8afb5c37627f1be178382c320d1b46afba5e3b", + "https://bcr.bazel.build/modules/bazel_features/1.21.0/source.json": "3e8379efaaef53ce35b7b8ba419df829315a880cb0a030e5bb45c96d6d5ecb5f", + "https://bcr.bazel.build/modules/bazel_features/1.4.1/MODULE.bazel": "e45b6bb2350aff3e442ae1111c555e27eac1d915e77775f6fdc4b351b758b5d7", + "https://bcr.bazel.build/modules/bazel_features/1.9.0/MODULE.bazel": "885151d58d90d8d9c811eb75e3288c11f850e1d6b481a8c9f766adee4712358b", + "https://bcr.bazel.build/modules/bazel_skylib/1.0.3/MODULE.bazel": "bcb0fd896384802d1ad283b4e4eb4d718eebd8cb820b0a2c3a347fb971afd9d8", + "https://bcr.bazel.build/modules/bazel_skylib/1.1.1/MODULE.bazel": "1add3e7d93ff2e6998f9e118022c84d163917d912f5afafb3058e3d2f1545b5e", + "https://bcr.bazel.build/modules/bazel_skylib/1.2.0/MODULE.bazel": "44fe84260e454ed94ad326352a698422dbe372b21a1ac9f3eab76eb531223686", + "https://bcr.bazel.build/modules/bazel_skylib/1.2.1/MODULE.bazel": "f35baf9da0efe45fa3da1696ae906eea3d615ad41e2e3def4aeb4e8bc0ef9a7a", + "https://bcr.bazel.build/modules/bazel_skylib/1.3.0/MODULE.bazel": "20228b92868bf5cfc41bda7afc8a8ba2a543201851de39d990ec957b513579c5", + "https://bcr.bazel.build/modules/bazel_skylib/1.4.1/MODULE.bazel": "a0dcb779424be33100dcae821e9e27e4f2901d9dfd5333efe5ac6a8d7ab75e1d", + "https://bcr.bazel.build/modules/bazel_skylib/1.4.2/MODULE.bazel": "3bd40978e7a1fac911d5989e6b09d8f64921865a45822d8b09e815eaa726a651", + "https://bcr.bazel.build/modules/bazel_skylib/1.5.0/MODULE.bazel": "32880f5e2945ce6a03d1fbd588e9198c0a959bb42297b2cfaf1685b7bc32e138", + "https://bcr.bazel.build/modules/bazel_skylib/1.6.1/MODULE.bazel": "8fdee2dbaace6c252131c00e1de4b165dc65af02ea278476187765e1a617b917", + "https://bcr.bazel.build/modules/bazel_skylib/1.7.0/MODULE.bazel": "0db596f4563de7938de764cc8deeabec291f55e8ec15299718b93c4423e9796d", + "https://bcr.bazel.build/modules/bazel_skylib/1.7.1/MODULE.bazel": "3120d80c5861aa616222ec015332e5f8d3171e062e3e804a2a0253e1be26e59b", + "https://bcr.bazel.build/modules/bazel_skylib/1.7.1/source.json": "f121b43eeefc7c29efbd51b83d08631e2347297c95aac9764a701f2a6a2bb953", + "https://bcr.bazel.build/modules/buildozer/7.1.2/MODULE.bazel": "2e8dd40ede9c454042645fd8d8d0cd1527966aa5c919de86661e62953cd73d84", + "https://bcr.bazel.build/modules/buildozer/7.1.2/source.json": "c9028a501d2db85793a6996205c8de120944f50a0d570438fcae0457a5f9d1f8", + "https://bcr.bazel.build/modules/google_benchmark/1.8.2/MODULE.bazel": "a70cf1bba851000ba93b58ae2f6d76490a9feb74192e57ab8e8ff13c34ec50cb", + "https://bcr.bazel.build/modules/googletest/1.11.0/MODULE.bazel": "3a83f095183f66345ca86aa13c58b59f9f94a2f81999c093d4eeaa2d262d12f4", + "https://bcr.bazel.build/modules/googletest/1.14.0.bcr.1/MODULE.bazel": "22c31a561553727960057361aa33bf20fb2e98584bc4fec007906e27053f80c6", + "https://bcr.bazel.build/modules/googletest/1.14.0.bcr.1/source.json": "41e9e129f80d8c8bf103a7acc337b76e54fad1214ac0a7084bf24f4cd924b8b4", + "https://bcr.bazel.build/modules/googletest/1.14.0/MODULE.bazel": "cfbcbf3e6eac06ef9d85900f64424708cc08687d1b527f0ef65aa7517af8118f", + "https://bcr.bazel.build/modules/jsoncpp/1.9.5/MODULE.bazel": "31271aedc59e815656f5736f282bb7509a97c7ecb43e927ac1a37966e0578075", + "https://bcr.bazel.build/modules/jsoncpp/1.9.5/source.json": "4108ee5085dd2885a341c7fab149429db457b3169b86eb081fa245eadf69169d", + "https://bcr.bazel.build/modules/libpfm/4.11.0/MODULE.bazel": "45061ff025b301940f1e30d2c16bea596c25b176c8b6b3087e92615adbd52902", + "https://bcr.bazel.build/modules/platforms/0.0.10/MODULE.bazel": "8cb8efaf200bdeb2150d93e162c40f388529a25852b332cec879373771e48ed5", + "https://bcr.bazel.build/modules/platforms/0.0.10/source.json": "f22828ff4cf021a6b577f1bf6341cb9dcd7965092a439f64fc1bb3b7a5ae4bd5", + "https://bcr.bazel.build/modules/platforms/0.0.4/MODULE.bazel": "9b328e31ee156f53f3c416a64f8491f7eb731742655a47c9eec4703a71644aee", + "https://bcr.bazel.build/modules/platforms/0.0.5/MODULE.bazel": "5733b54ea419d5eaf7997054bb55f6a1d0b5ff8aedf0176fef9eea44f3acda37", + "https://bcr.bazel.build/modules/platforms/0.0.6/MODULE.bazel": "ad6eeef431dc52aefd2d77ed20a4b353f8ebf0f4ecdd26a807d2da5aa8cd0615", + "https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel": "72fd4a0ede9ee5c021f6a8dd92b503e089f46c227ba2813ff183b71616034814", + "https://bcr.bazel.build/modules/platforms/0.0.8/MODULE.bazel": "9f142c03e348f6d263719f5074b21ef3adf0b139ee4c5133e2aa35664da9eb2d", + "https://bcr.bazel.build/modules/platforms/0.0.9/MODULE.bazel": "4a87a60c927b56ddd67db50c89acaa62f4ce2a1d2149ccb63ffd871d5ce29ebc", + "https://bcr.bazel.build/modules/protobuf/21.7/MODULE.bazel": "a5a29bb89544f9b97edce05642fac225a808b5b7be74038ea3640fae2f8e66a7", + "https://bcr.bazel.build/modules/protobuf/27.0/MODULE.bazel": "7873b60be88844a0a1d8f80b9d5d20cfbd8495a689b8763e76c6372998d3f64c", + "https://bcr.bazel.build/modules/protobuf/29.0-rc2/MODULE.bazel": "6241d35983510143049943fc0d57937937122baf1b287862f9dc8590fc4c37df", + "https://bcr.bazel.build/modules/protobuf/29.0-rc3/MODULE.bazel": "33c2dfa286578573afc55a7acaea3cada4122b9631007c594bf0729f41c8de92", + "https://bcr.bazel.build/modules/protobuf/29.0-rc3/source.json": "c16a6488fb279ef578da7098e605082d72ed85fc8d843eaae81e7d27d0f4625d", + "https://bcr.bazel.build/modules/protobuf/3.19.0/MODULE.bazel": "6b5fbb433f760a99a22b18b6850ed5784ef0e9928a72668b66e4d7ccd47db9b0", + "https://bcr.bazel.build/modules/protobuf/3.19.6/MODULE.bazel": "9233edc5e1f2ee276a60de3eaa47ac4132302ef9643238f23128fea53ea12858", + "https://bcr.bazel.build/modules/pybind11_bazel/2.11.1/MODULE.bazel": "88af1c246226d87e65be78ed49ecd1e6f5e98648558c14ce99176da041dc378e", + "https://bcr.bazel.build/modules/pybind11_bazel/2.11.1/source.json": "be4789e951dd5301282729fe3d4938995dc4c1a81c2ff150afc9f1b0504c6022", + "https://bcr.bazel.build/modules/re2/2023-09-01/MODULE.bazel": "cb3d511531b16cfc78a225a9e2136007a48cf8a677e4264baeab57fe78a80206", + "https://bcr.bazel.build/modules/re2/2023-09-01/source.json": "e044ce89c2883cd957a2969a43e79f7752f9656f6b20050b62f90ede21ec6eb4", + "https://bcr.bazel.build/modules/rules_android/0.1.1/MODULE.bazel": "48809ab0091b07ad0182defb787c4c5328bd3a278938415c00a7b69b50c4d3a8", + "https://bcr.bazel.build/modules/rules_android/0.1.1/source.json": "e6986b41626ee10bdc864937ffb6d6bf275bb5b9c65120e6137d56e6331f089e", + "https://bcr.bazel.build/modules/rules_cc/0.0.1/MODULE.bazel": "cb2aa0747f84c6c3a78dad4e2049c154f08ab9d166b1273835a8174940365647", + "https://bcr.bazel.build/modules/rules_cc/0.0.10/MODULE.bazel": "ec1705118f7eaedd6e118508d3d26deba2a4e76476ada7e0e3965211be012002", + "https://bcr.bazel.build/modules/rules_cc/0.0.13/MODULE.bazel": "0e8529ed7b323dad0775ff924d2ae5af7640b23553dfcd4d34344c7e7a867191", + "https://bcr.bazel.build/modules/rules_cc/0.0.15/MODULE.bazel": "6704c35f7b4a72502ee81f61bf88706b54f06b3cbe5558ac17e2e14666cd5dcc", + "https://bcr.bazel.build/modules/rules_cc/0.0.16/MODULE.bazel": "7661303b8fc1b4d7f532e54e9d6565771fea666fbdf839e0a86affcd02defe87", + "https://bcr.bazel.build/modules/rules_cc/0.0.16/source.json": "227e83737046aa4f50015da48e98e0d8ab42fd0ec74d8d653b6cc9f9a357f200", + "https://bcr.bazel.build/modules/rules_cc/0.0.2/MODULE.bazel": "6915987c90970493ab97393024c156ea8fb9f3bea953b2f3ec05c34f19b5695c", + "https://bcr.bazel.build/modules/rules_cc/0.0.6/MODULE.bazel": "abf360251023dfe3efcef65ab9d56beefa8394d4176dd29529750e1c57eaa33f", + "https://bcr.bazel.build/modules/rules_cc/0.0.8/MODULE.bazel": "964c85c82cfeb6f3855e6a07054fdb159aced38e99a5eecf7bce9d53990afa3e", + "https://bcr.bazel.build/modules/rules_cc/0.0.9/MODULE.bazel": "836e76439f354b89afe6a911a7adf59a6b2518fafb174483ad78a2a2fde7b1c5", + "https://bcr.bazel.build/modules/rules_foreign_cc/0.9.0/MODULE.bazel": "c9e8c682bf75b0e7c704166d79b599f93b72cfca5ad7477df596947891feeef6", + "https://bcr.bazel.build/modules/rules_fuzzing/0.5.2/MODULE.bazel": "40c97d1144356f52905566c55811f13b299453a14ac7769dfba2ac38192337a8", + "https://bcr.bazel.build/modules/rules_fuzzing/0.5.2/source.json": "c8b1e2c717646f1702290959a3302a178fb639d987ab61d548105019f11e527e", + "https://bcr.bazel.build/modules/rules_java/4.0.0/MODULE.bazel": "5a78a7ae82cd1a33cef56dc578c7d2a46ed0dca12643ee45edbb8417899e6f74", + "https://bcr.bazel.build/modules/rules_java/5.3.5/MODULE.bazel": "a4ec4f2db570171e3e5eb753276ee4b389bae16b96207e9d3230895c99644b86", + "https://bcr.bazel.build/modules/rules_java/6.3.0/MODULE.bazel": "a97c7678c19f236a956ad260d59c86e10a463badb7eb2eda787490f4c969b963", + "https://bcr.bazel.build/modules/rules_java/6.5.2/MODULE.bazel": "1d440d262d0e08453fa0c4d8f699ba81609ed0e9a9a0f02cd10b3e7942e61e31", + "https://bcr.bazel.build/modules/rules_java/7.10.0/MODULE.bazel": "530c3beb3067e870561739f1144329a21c851ff771cd752a49e06e3dc9c2e71a", + "https://bcr.bazel.build/modules/rules_java/7.12.2/MODULE.bazel": "579c505165ee757a4280ef83cda0150eea193eed3bef50b1004ba88b99da6de6", + "https://bcr.bazel.build/modules/rules_java/7.2.0/MODULE.bazel": "06c0334c9be61e6cef2c8c84a7800cef502063269a5af25ceb100b192453d4ab", + "https://bcr.bazel.build/modules/rules_java/7.6.1/MODULE.bazel": "2f14b7e8a1aa2f67ae92bc69d1ec0fa8d9f827c4e17ff5e5f02e91caa3b2d0fe", + "https://bcr.bazel.build/modules/rules_java/7.6.5/MODULE.bazel": "481164be5e02e4cab6e77a36927683263be56b7e36fef918b458d7a8a1ebadb1", + "https://bcr.bazel.build/modules/rules_java/8.3.2/MODULE.bazel": "7336d5511ad5af0b8615fdc7477535a2e4e723a357b6713af439fe8cf0195017", + "https://bcr.bazel.build/modules/rules_java/8.5.1/MODULE.bazel": "d8a9e38cc5228881f7055a6079f6f7821a073df3744d441978e7a43e20226939", + "https://bcr.bazel.build/modules/rules_java/8.5.1/source.json": "db1a77d81b059e0f84985db67a22f3f579a529a86b7997605be3d214a0abe38e", + "https://bcr.bazel.build/modules/rules_jvm_external/4.4.2/MODULE.bazel": "a56b85e418c83eb1839819f0b515c431010160383306d13ec21959ac412d2fe7", + "https://bcr.bazel.build/modules/rules_jvm_external/5.1/MODULE.bazel": "33f6f999e03183f7d088c9be518a63467dfd0be94a11d0055fe2d210f89aa909", + "https://bcr.bazel.build/modules/rules_jvm_external/5.2/MODULE.bazel": "d9351ba35217ad0de03816ef3ed63f89d411349353077348a45348b096615036", + "https://bcr.bazel.build/modules/rules_jvm_external/6.3/MODULE.bazel": "c998e060b85f71e00de5ec552019347c8bca255062c990ac02d051bb80a38df0", + "https://bcr.bazel.build/modules/rules_jvm_external/6.3/source.json": "6f5f5a5a4419ae4e37c35a5bb0a6ae657ed40b7abc5a5189111b47fcebe43197", + "https://bcr.bazel.build/modules/rules_kotlin/1.9.6/MODULE.bazel": "d269a01a18ee74d0335450b10f62c9ed81f2321d7958a2934e44272fe82dcef3", + "https://bcr.bazel.build/modules/rules_kotlin/1.9.6/source.json": "2faa4794364282db7c06600b7e5e34867a564ae91bda7cae7c29c64e9466b7d5", + "https://bcr.bazel.build/modules/rules_license/0.0.3/MODULE.bazel": "627e9ab0247f7d1e05736b59dbb1b6871373de5ad31c3011880b4133cafd4bd0", + "https://bcr.bazel.build/modules/rules_license/0.0.7/MODULE.bazel": "088fbeb0b6a419005b89cf93fe62d9517c0a2b8bb56af3244af65ecfe37e7d5d", + "https://bcr.bazel.build/modules/rules_license/1.0.0/MODULE.bazel": "a7fda60eefdf3d8c827262ba499957e4df06f659330bbe6cdbdb975b768bb65c", + "https://bcr.bazel.build/modules/rules_license/1.0.0/source.json": "a52c89e54cc311196e478f8382df91c15f7a2bfdf4c6cd0e2675cc2ff0b56efb", + "https://bcr.bazel.build/modules/rules_nodejs/6.3.0/MODULE.bazel": "45345e4aba35dd6e4701c1eebf5a4e67af4ed708def9ebcdc6027585b34ee52d", + "https://bcr.bazel.build/modules/rules_nodejs/6.3.0/source.json": "1254ffd8d0d908a19c67add7fb5e2a1f604df133bc5d206425264293e2e537fc", + "https://bcr.bazel.build/modules/rules_pkg/0.7.0/MODULE.bazel": "df99f03fc7934a4737122518bb87e667e62d780b610910f0447665a7e2be62dc", + "https://bcr.bazel.build/modules/rules_pkg/1.0.1/MODULE.bazel": "5b1df97dbc29623bccdf2b0dcd0f5cb08e2f2c9050aab1092fd39a41e82686ff", + "https://bcr.bazel.build/modules/rules_pkg/1.0.1/source.json": "bd82e5d7b9ce2d31e380dd9f50c111d678c3bdaca190cb76b0e1c71b05e1ba8a", + "https://bcr.bazel.build/modules/rules_proto/4.0.0/MODULE.bazel": "a7a7b6ce9bee418c1a760b3d84f83a299ad6952f9903c67f19e4edd964894e06", + "https://bcr.bazel.build/modules/rules_proto/5.3.0-21.7/MODULE.bazel": "e8dff86b0971688790ae75528fe1813f71809b5afd57facb44dad9e8eca631b7", + "https://bcr.bazel.build/modules/rules_proto/6.0.2/MODULE.bazel": "ce916b775a62b90b61888052a416ccdda405212b6aaeb39522f7dc53431a5e73", + "https://bcr.bazel.build/modules/rules_proto/6.0.2/source.json": "17a2e195f56cb28d6bbf763e49973d13890487c6945311ed141e196fb660426d", + "https://bcr.bazel.build/modules/rules_python/0.10.2/MODULE.bazel": "cc82bc96f2997baa545ab3ce73f196d040ffb8756fd2d66125a530031cd90e5f", + "https://bcr.bazel.build/modules/rules_python/0.22.1/MODULE.bazel": "26114f0c0b5e93018c0c066d6673f1a2c3737c7e90af95eff30cfee38d0bbac7", + "https://bcr.bazel.build/modules/rules_python/0.23.1/MODULE.bazel": "49ffccf0511cb8414de28321f5fcf2a31312b47c40cc21577144b7447f2bf300", + "https://bcr.bazel.build/modules/rules_python/0.25.0/MODULE.bazel": "72f1506841c920a1afec76975b35312410eea3aa7b63267436bfb1dd91d2d382", + "https://bcr.bazel.build/modules/rules_python/0.28.0/MODULE.bazel": "cba2573d870babc976664a912539b320cbaa7114cd3e8f053c720171cde331ed", + "https://bcr.bazel.build/modules/rules_python/0.31.0/MODULE.bazel": "93a43dc47ee570e6ec9f5779b2e64c1476a6ce921c48cc9a1678a91dd5f8fd58", + "https://bcr.bazel.build/modules/rules_python/0.4.0/MODULE.bazel": "9208ee05fd48bf09ac60ed269791cf17fb343db56c8226a720fbb1cdf467166c", + "https://bcr.bazel.build/modules/rules_python/1.2.0/MODULE.bazel": "5aeeb48b2a6c19d668b48adf2b8a2b209a6310c230db0ce77450f148a89846e4", + "https://bcr.bazel.build/modules/rules_python/1.2.0/source.json": "5b7892685c9a843526fd5a31e7d7a93eb819c59fd7b7fc444b5b143558e1b073", + "https://bcr.bazel.build/modules/rules_shell/0.2.0/MODULE.bazel": "fda8a652ab3c7d8fee214de05e7a9916d8b28082234e8d2c0094505c5268ed3c", + "https://bcr.bazel.build/modules/rules_shell/0.2.0/source.json": "7f27af3c28037d9701487c4744b5448d26537cc66cdef0d8df7ae85411f8de95", + "https://bcr.bazel.build/modules/stardoc/0.5.1/MODULE.bazel": "1a05d92974d0c122f5ccf09291442580317cdd859f07a8655f1db9a60374f9f8", + "https://bcr.bazel.build/modules/stardoc/0.5.3/MODULE.bazel": "c7f6948dae6999bf0db32c1858ae345f112cacf98f174c7a8bb707e41b974f1c", + "https://bcr.bazel.build/modules/stardoc/0.6.2/MODULE.bazel": "7060193196395f5dd668eda046ccbeacebfd98efc77fed418dbe2b82ffaa39fd", + "https://bcr.bazel.build/modules/stardoc/0.7.0/MODULE.bazel": "05e3d6d30c099b6770e97da986c53bd31844d7f13d41412480ea265ac9e8079c", + "https://bcr.bazel.build/modules/stardoc/0.7.2/MODULE.bazel": "fc152419aa2ea0f51c29583fab1e8c99ddefd5b3778421845606ee628629e0e5", + "https://bcr.bazel.build/modules/stardoc/0.7.2/source.json": "58b029e5e901d6802967754adf0a9056747e8176f017cfe3607c0851f4d42216", + "https://bcr.bazel.build/modules/upb/0.0.0-20220923-a547704/MODULE.bazel": "7298990c00040a0e2f121f6c32544bab27d4452f80d9ce51349b1a28f3005c43", + "https://bcr.bazel.build/modules/zlib/1.2.11/MODULE.bazel": "07b389abc85fdbca459b69e2ec656ae5622873af3f845e1c9d80fe179f3effa0", + "https://bcr.bazel.build/modules/zlib/1.2.12/MODULE.bazel": "3b1a8834ada2a883674be8cbd36ede1b6ec481477ada359cd2d3ddc562340b27", + "https://bcr.bazel.build/modules/zlib/1.3.1.bcr.3/MODULE.bazel": "af322bc08976524477c79d1e45e241b6efbeb918c497e8840b8ab116802dda79", + "https://bcr.bazel.build/modules/zlib/1.3.1.bcr.3/source.json": "2be409ac3c7601245958cd4fcdff4288be79ed23bd690b4b951f500d54ee6e7d", + "https://bcr.bazel.build/modules/zlib/1.3.1/MODULE.bazel": "751c9940dcfe869f5f7274e1295422a34623555916eb98c174c1e945594bf198" + }, + "selectedYankedVersions": {}, + "moduleExtensions": { + "@@apple_support~//crosstool:setup.bzl%apple_cc_configure_extension": { + "general": { + "bzlTransitiveDigest": "PjIds3feoYE8SGbbIq2SFTZy3zmxeO2tQevJZNDo7iY=", + "usagesDigest": "+hz7IHWN6A1oVJJWNDB6yZRG+RYhF76wAYItpAeIUIg=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "local_config_apple_cc_toolchains": { + "bzlFile": "@@apple_support~//crosstool:setup.bzl", + "ruleClassName": "_apple_cc_autoconf_toolchains", + "attributes": {} + }, + "local_config_apple_cc": { + "bzlFile": "@@apple_support~//crosstool:setup.bzl", + "ruleClassName": "_apple_cc_autoconf", + "attributes": {} + } + }, + "recordedRepoMappingEntries": [ + [ + "apple_support~", + "bazel_tools", + "bazel_tools" + ] + ] + } + }, + "@@aspect_bazel_lib~//lib:extensions.bzl%toolchains": { + "general": { + "bzlTransitiveDigest": "7dUTNg3iBL3n4jGiBJEkQIvlejRjH/FAR+4XLx1N6Ug=", + "usagesDigest": "G7+soeEmZ7LLgLaiMnIUSm/lpOSfIJkTK5CMBT/YMl4=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "copy_directory_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "darwin_amd64" + } + }, + "copy_directory_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "darwin_arm64" + } + }, + "copy_directory_freebsd_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "freebsd_amd64" + } + }, + "copy_directory_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "linux_amd64" + } + }, + "copy_directory_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "linux_arm64" + } + }, + "copy_directory_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_platform_repo", + "attributes": { + "platform": "windows_amd64" + } + }, + "copy_directory_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_directory_toolchain.bzl", + "ruleClassName": "copy_directory_toolchains_repo", + "attributes": { + "user_repository_name": "copy_directory" + } + }, + "copy_to_directory_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "darwin_amd64" + } + }, + "copy_to_directory_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "darwin_arm64" + } + }, + "copy_to_directory_freebsd_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "freebsd_amd64" + } + }, + "copy_to_directory_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "linux_amd64" + } + }, + "copy_to_directory_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "linux_arm64" + } + }, + "copy_to_directory_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_platform_repo", + "attributes": { + "platform": "windows_amd64" + } + }, + "copy_to_directory_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:copy_to_directory_toolchain.bzl", + "ruleClassName": "copy_to_directory_toolchains_repo", + "attributes": { + "user_repository_name": "copy_to_directory" + } + }, + "jq_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_platform_repo", + "attributes": { + "platform": "darwin_amd64", + "version": "1.7" + } + }, + "jq_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_platform_repo", + "attributes": { + "platform": "darwin_arm64", + "version": "1.7" + } + }, + "jq_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_platform_repo", + "attributes": { + "platform": "linux_amd64", + "version": "1.7" + } + }, + "jq_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_platform_repo", + "attributes": { + "platform": "linux_arm64", + "version": "1.7" + } + }, + "jq_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_platform_repo", + "attributes": { + "platform": "windows_amd64", + "version": "1.7" + } + }, + "jq": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_host_alias_repo", + "attributes": {} + }, + "jq_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:jq_toolchain.bzl", + "ruleClassName": "jq_toolchains_repo", + "attributes": { + "user_repository_name": "jq" + } + }, + "yq_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "darwin_amd64", + "version": "4.25.2" + } + }, + "yq_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "darwin_arm64", + "version": "4.25.2" + } + }, + "yq_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "linux_amd64", + "version": "4.25.2" + } + }, + "yq_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "linux_arm64", + "version": "4.25.2" + } + }, + "yq_linux_s390x": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "linux_s390x", + "version": "4.25.2" + } + }, + "yq_linux_ppc64le": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "linux_ppc64le", + "version": "4.25.2" + } + }, + "yq_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_platform_repo", + "attributes": { + "platform": "windows_amd64", + "version": "4.25.2" + } + }, + "yq": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_host_alias_repo", + "attributes": {} + }, + "yq_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:yq_toolchain.bzl", + "ruleClassName": "yq_toolchains_repo", + "attributes": { + "user_repository_name": "yq" + } + }, + "coreutils_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_platform_repo", + "attributes": { + "platform": "darwin_amd64", + "version": "0.0.26" + } + }, + "coreutils_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_platform_repo", + "attributes": { + "platform": "darwin_arm64", + "version": "0.0.26" + } + }, + "coreutils_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_platform_repo", + "attributes": { + "platform": "linux_amd64", + "version": "0.0.26" + } + }, + "coreutils_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_platform_repo", + "attributes": { + "platform": "linux_arm64", + "version": "0.0.26" + } + }, + "coreutils_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_platform_repo", + "attributes": { + "platform": "windows_amd64", + "version": "0.0.26" + } + }, + "coreutils_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:coreutils_toolchain.bzl", + "ruleClassName": "coreutils_toolchains_repo", + "attributes": { + "user_repository_name": "coreutils" + } + }, + "bsd_tar_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "bsdtar_binary_repo", + "attributes": { + "platform": "darwin_amd64" + } + }, + "bsd_tar_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "bsdtar_binary_repo", + "attributes": { + "platform": "darwin_arm64" + } + }, + "bsd_tar_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "bsdtar_binary_repo", + "attributes": { + "platform": "linux_amd64" + } + }, + "bsd_tar_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "bsdtar_binary_repo", + "attributes": { + "platform": "linux_arm64" + } + }, + "bsd_tar_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "bsdtar_binary_repo", + "attributes": { + "platform": "windows_amd64" + } + }, + "bsd_tar_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:tar_toolchain.bzl", + "ruleClassName": "tar_toolchains_repo", + "attributes": { + "user_repository_name": "bsd_tar" + } + }, + "zstd_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:zstd_toolchain.bzl", + "ruleClassName": "zstd_binary_repo", + "attributes": { + "platform": "darwin_amd64" + } + }, + "zstd_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:zstd_toolchain.bzl", + "ruleClassName": "zstd_binary_repo", + "attributes": { + "platform": "darwin_arm64" + } + }, + "zstd_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:zstd_toolchain.bzl", + "ruleClassName": "zstd_binary_repo", + "attributes": { + "platform": "linux_amd64" + } + }, + "zstd_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:zstd_toolchain.bzl", + "ruleClassName": "zstd_binary_repo", + "attributes": { + "platform": "linux_arm64" + } + }, + "zstd_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:zstd_toolchain.bzl", + "ruleClassName": "zstd_toolchains_repo", + "attributes": { + "user_repository_name": "zstd" + } + }, + "expand_template_darwin_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "darwin_amd64" + } + }, + "expand_template_darwin_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "darwin_arm64" + } + }, + "expand_template_freebsd_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "freebsd_amd64" + } + }, + "expand_template_linux_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "linux_amd64" + } + }, + "expand_template_linux_arm64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "linux_arm64" + } + }, + "expand_template_windows_amd64": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_platform_repo", + "attributes": { + "platform": "windows_amd64" + } + }, + "expand_template_toolchains": { + "bzlFile": "@@aspect_bazel_lib~//lib/private:expand_template_toolchain.bzl", + "ruleClassName": "expand_template_toolchains_repo", + "attributes": { + "user_repository_name": "expand_template" + } + }, + "bats_support": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "sha256": "7815237aafeb42ddcc1b8c698fc5808026d33317d8701d5ec2396e9634e2918f", + "urls": [ + "https://github.com/bats-core/bats-support/archive/v0.3.0.tar.gz" + ], + "strip_prefix": "bats-support-0.3.0", + "build_file_content": "load(\"@aspect_bazel_lib//lib:copy_to_directory.bzl\", \"copy_to_directory\")\n\ncopy_to_directory(\n name = \"support\",\n hardlink = \"on\",\n srcs = glob([\n \"src/**\",\n \"load.bash\",\n ]),\n out = \"bats-support\",\n visibility = [\"//visibility:public\"]\n)\n" + } + }, + "bats_assert": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "sha256": "98ca3b685f8b8993e48ec057565e6e2abcc541034ed5b0e81f191505682037fd", + "urls": [ + "https://github.com/bats-core/bats-assert/archive/v2.1.0.tar.gz" + ], + "strip_prefix": "bats-assert-2.1.0", + "build_file_content": "load(\"@aspect_bazel_lib//lib:copy_to_directory.bzl\", \"copy_to_directory\")\n\ncopy_to_directory(\n name = \"assert\",\n hardlink = \"on\",\n srcs = glob([\n \"src/**\",\n \"load.bash\",\n ]),\n out = \"bats-assert\",\n visibility = [\"//visibility:public\"]\n)\n" + } + }, + "bats_file": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "sha256": "9b69043241f3af1c2d251f89b4fcafa5df3f05e97b89db18d7c9bdf5731bb27a", + "urls": [ + "https://github.com/bats-core/bats-file/archive/v0.4.0.tar.gz" + ], + "strip_prefix": "bats-file-0.4.0", + "build_file_content": "load(\"@aspect_bazel_lib//lib:copy_to_directory.bzl\", \"copy_to_directory\")\n\ncopy_to_directory(\n name = \"file\",\n hardlink = \"on\",\n srcs = glob([\n \"src/**\",\n \"load.bash\",\n ]),\n out = \"bats-file\",\n visibility = [\"//visibility:public\"]\n)\n" + } + }, + "bats_toolchains": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "sha256": "a1a9f7875aa4b6a9480ca384d5865f1ccf1b0b1faead6b47aa47d79709a5c5fd", + "urls": [ + "https://github.com/bats-core/bats-core/archive/v1.10.0.tar.gz" + ], + "strip_prefix": "bats-core-1.10.0", + "build_file_content": "load(\"@local_config_platform//:constraints.bzl\", \"HOST_CONSTRAINTS\")\nload(\"@aspect_bazel_lib//lib/private:bats_toolchain.bzl\", \"bats_toolchain\")\nload(\"@aspect_bazel_lib//lib:copy_to_directory.bzl\", \"copy_to_directory\")\n\ncopy_to_directory(\n name = \"core\",\n hardlink = \"on\",\n srcs = glob([\n \"lib/**\",\n \"libexec/**\"\n ]) + [\"bin/bats\"],\n out = \"bats-core\",\n)\n\nbats_toolchain(\n name = \"toolchain\",\n core = \":core\",\n libraries = [\"@bats_support//:support\", \"@bats_assert//:assert\", \"@bats_file//:file\"]\n)\n\ntoolchain(\n name = \"bats_toolchain\",\n exec_compatible_with = HOST_CONSTRAINTS,\n toolchain = \":toolchain\",\n toolchain_type = \"@aspect_bazel_lib//lib:bats_toolchain_type\",\n)\n" + } + } + }, + "recordedRepoMappingEntries": [ + [ + "aspect_bazel_lib~", + "aspect_bazel_lib", + "aspect_bazel_lib~" + ], + [ + "aspect_bazel_lib~", + "bazel_skylib", + "bazel_skylib~" + ], + [ + "aspect_bazel_lib~", + "bazel_tools", + "bazel_tools" + ] + ] + } + }, + "@@bazel-orfs~//:extension.bzl%orfs_repositories": { + "general": { + "bzlTransitiveDigest": "opZMguyG+UPmDQ6vhzXe/u0WnKyao2m9IAQt+JWkhcA=", + "usagesDigest": "ZjAOFUXNXojx6a5mgorvg9pXsDXOsJv7KzaZaxOrWXU=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "com_github_nixos_patchelf_download": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "build_file_content": "\n export_files(\n [\"bin/patchelf\"],\n visibility = [\"//visibility:public\"],\n )\n ", + "sha256": "ce84f2447fb7a8679e58bc54a20dc2b01b37b5802e12c57eece772a6f14bf3f0", + "urls": [ + "https://github.com/NixOS/patchelf/releases/download/0.18.0/patchelf-0.18.0-x86_64.tar.gz" + ] + } + }, + "docker_orfs": { + "bzlFile": "@@bazel-orfs~//:docker.bzl", + "ruleClassName": "docker_pkg", + "attributes": { + "image": "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", + "sha256": "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", + "build_file": "@@bazel-orfs~//:docker.BUILD.bazel", + "timeout": 3600, + "patch_cmds": [ + "find . -name BUILD.bazel -delete" + ] + } + }, + "config": { + "bzlFile": "@@bazel-orfs~//:config.bzl", + "ruleClassName": "global_config", + "attributes": { + "makefile": "@@//flow:makefile", + "pdk": "@@//flow:asap7", + "makefile_yosys": "@@//flow:makefile_yosys", + "openroad": "@@bazel-orfs~~orfs_repositories~docker_orfs//:openroad", + "yosys": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys", + "yosys_abc": "@@bazel-orfs~~orfs_repositories~docker_orfs//:yosys-abc" + } + } + }, + "recordedRepoMappingEntries": [ + [ + "bazel-orfs~", + "bazel_tools", + "bazel_tools" + ], + [ + "bazel-orfs~", + "com_github_nixos_patchelf_download", + "bazel-orfs~~orfs_repositories~com_github_nixos_patchelf_download" + ], + [ + "bazel-orfs~", + "docker_orfs", + "bazel-orfs~~orfs_repositories~docker_orfs" + ] + ] + } + }, + "@@platforms//host:extension.bzl%host_platform": { + "general": { + "bzlTransitiveDigest": "xelQcPZH8+tmuOHVjL9vDxMnnQNMlwj0SlvgoqBkm4U=", + "usagesDigest": "hgylFkgWSg0ulUwWZzEM1aIftlUnbmw2ynWLdEfHnZc=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "host_platform": { + "bzlFile": "@@platforms//host:extension.bzl", + "ruleClassName": "host_platform_repo", + "attributes": {} + } + }, + "recordedRepoMappingEntries": [] + } + }, + "@@rules_java~//java:rules_java_deps.bzl%compatibility_proxy": { + "general": { + "bzlTransitiveDigest": "KIX40nDfygEWbU+rq3nYpt3tVgTK/iO8PKh5VMBlN7M=", + "usagesDigest": "pwHZ+26iLgQdwvdZeA5wnAjKnNI3y6XO2VbhOTeo5h8=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "compatibility_proxy": { + "bzlFile": "@@rules_java~//java:rules_java_deps.bzl", + "ruleClassName": "_compatibility_proxy_repo_rule", + "attributes": {} + } + }, + "recordedRepoMappingEntries": [ + [ + "rules_java~", + "bazel_tools", + "bazel_tools" + ] + ] + } + }, + "@@rules_kotlin~//src/main/starlark/core/repositories:bzlmod_setup.bzl%rules_kotlin_extensions": { + "general": { + "bzlTransitiveDigest": "fus14IFJ/1LGWWGKPH/U18VnJCoMjfDt1ckahqCnM0A=", + "usagesDigest": "aJF6fLy82rR95Ff5CZPAqxNoFgOMLMN5ImfBS0nhnkg=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "com_github_jetbrains_kotlin_git": { + "bzlFile": "@@rules_kotlin~//src/main/starlark/core/repositories:compiler.bzl", + "ruleClassName": "kotlin_compiler_git_repository", + "attributes": { + "urls": [ + "https://github.com/JetBrains/kotlin/releases/download/v1.9.23/kotlin-compiler-1.9.23.zip" + ], + "sha256": "93137d3aab9afa9b27cb06a824c2324195c6b6f6179d8a8653f440f5bd58be88" + } + }, + "com_github_jetbrains_kotlin": { + "bzlFile": "@@rules_kotlin~//src/main/starlark/core/repositories:compiler.bzl", + "ruleClassName": "kotlin_capabilities_repository", + "attributes": { + "git_repository_name": "com_github_jetbrains_kotlin_git", + "compiler_version": "1.9.23" + } + }, + "com_github_google_ksp": { + "bzlFile": "@@rules_kotlin~//src/main/starlark/core/repositories:ksp.bzl", + "ruleClassName": "ksp_compiler_plugin_repository", + "attributes": { + "urls": [ + "https://github.com/google/ksp/releases/download/1.9.23-1.0.20/artifacts.zip" + ], + "sha256": "ee0618755913ef7fd6511288a232e8fad24838b9af6ea73972a76e81053c8c2d", + "strip_version": "1.9.23-1.0.20" + } + }, + "com_github_pinterest_ktlint": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_file", + "attributes": { + "sha256": "01b2e0ef893383a50dbeb13970fe7fa3be36ca3e83259e01649945b09d736985", + "urls": [ + "https://github.com/pinterest/ktlint/releases/download/1.3.0/ktlint" + ], + "executable": true + } + }, + "rules_android": { + "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", + "ruleClassName": "http_archive", + "attributes": { + "sha256": "cd06d15dd8bb59926e4d65f9003bfc20f9da4b2519985c27e190cddc8b7a7806", + "strip_prefix": "rules_android-0.1.1", + "urls": [ + "https://github.com/bazelbuild/rules_android/archive/v0.1.1.zip" + ] + } + } + }, + "recordedRepoMappingEntries": [ + [ + "rules_kotlin~", + "bazel_tools", + "bazel_tools" + ] + ] + } + }, + "@@rules_nodejs~//nodejs:extensions.bzl%node": { + "general": { + "bzlTransitiveDigest": "SqbzUarOVzAfK28Ca5+NIU3LUwnW/b3h0xXBUS97oyI=", + "usagesDigest": "vmfHywZCXchJqbQW4G6223xyz/u2CXNbv8BoImtyMPo=", + "recordedFileInputs": {}, + "recordedDirentsInputs": {}, + "envVariables": {}, + "generatedRepoSpecs": { + "nodejs_linux_amd64": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "linux_amd64" + } + }, + "nodejs_linux_arm64": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "linux_arm64" + } + }, + "nodejs_linux_s390x": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "linux_s390x" + } + }, + "nodejs_linux_ppc64le": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "linux_ppc64le" + } + }, + "nodejs_darwin_amd64": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "darwin_amd64" + } + }, + "nodejs_darwin_arm64": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "darwin_arm64" + } + }, + "nodejs_windows_amd64": { + "bzlFile": "@@rules_nodejs~//nodejs:repositories.bzl", + "ruleClassName": "_nodejs_repositories", + "attributes": { + "node_download_auth": {}, + "node_repositories": {}, + "node_urls": [ + "https://nodejs.org/dist/v{version}/{filename}" + ], + "node_version": "16.14.2", + "include_headers": false, + "platform": "windows_amd64" + } + }, + "nodejs": { + "bzlFile": "@@rules_nodejs~//nodejs/private:nodejs_repo_host_os_alias.bzl", + "ruleClassName": "nodejs_repo_host_os_alias", + "attributes": { + "user_node_repository_name": "nodejs" + } + }, + "nodejs_host": { + "bzlFile": "@@rules_nodejs~//nodejs/private:nodejs_repo_host_os_alias.bzl", + "ruleClassName": "nodejs_repo_host_os_alias", + "attributes": { + "user_node_repository_name": "nodejs" + } + }, + "nodejs_toolchains": { + "bzlFile": "@@rules_nodejs~//nodejs/private:nodejs_toolchains_repo.bzl", + "ruleClassName": "nodejs_toolchains_repo", + "attributes": { + "user_node_repository_name": "nodejs" + } + } + }, + "recordedRepoMappingEntries": [] + } + }, + "@@rules_python~//python/extensions:pip.bzl%pip": { + "general": { + "bzlTransitiveDigest": "wDKx+PsqgAb8Kll8JbxI6+g8BUNJT48gxqvlHp+uPaM=", + "usagesDigest": "Pmo+R+aERo0wl9TIu+O0dXTNmE8JG2ElzftJqGKKsXk=", + "recordedFileInputs": { + "@@rules_python~//tools/publish/requirements_linux.txt": "d576e0d8542df61396a9b38deeaa183c24135ed5e8e73bb9622f298f2671811e", + "@@bazel-orfs~//requirements_lock_3_13.txt": "6d409e2c9f81ceee67c23e6f26b6742b4ee6c32826c7d0591c5c57df72a6a16b", + "@@//flow/util/requirements_lock.txt": "21d4a2f4b126820247f3f9b3554210fc78861c0a367c2b52d87771900b40520c", + "@@rules_fuzzing~//fuzzing/requirements.txt": "ab04664be026b632a0d2a2446c4f65982b7654f5b6851d2f9d399a19b7242a5b", + "@@rules_python~//tools/publish/requirements_windows.txt": "d18538a3982beab378fd5687f4db33162ee1ece69801f9a451661b1b64286b76", + "@@protobuf~//python/requirements.txt": "983be60d3cec4b319dcab6d48aeb3f5b2f7c3350f26b3a9e97486c37967c73c5", + "@@rules_python~//tools/publish/requirements_darwin.txt": "095d4a4f3d639dce831cd493367631cd51b53665292ab20194bac2c0c6458fa8" + }, + "recordedDirentsInputs": {}, + "envVariables": { + "RULES_PYTHON_REPO_DEBUG": null, + "RULES_PYTHON_REPO_DEBUG_VERBOSITY": null + }, + "generatedRepoSpecs": { + "bazel-orfs-pip_313_contourpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "contourpy==1.3.1 --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 --hash=sha256:05e806338bfeaa006acbdeba0ad681a10be63b26e1b17317bfac3c5d98f36cda --hash=sha256:08d9d449a61cf53033612cb368f3a1b26cd7835d9b8cd326647efe43bca7568d --hash=sha256:0ffa84be8e0bd33410b17189f7164c3589c229ce5db85798076a3fa136d0e509 --hash=sha256:113231fe3825ebf6f15eaa8bc1f5b0ddc19d42b733345eae0934cb291beb88b6 --hash=sha256:14c102b0eab282427b662cb590f2e9340a9d91a1c297f48729431f2dcd16e14f --hash=sha256:174e758c66bbc1c8576992cec9599ce8b6672b741b5d336b5c74e35ac382b18e --hash=sha256:19c1555a6801c2f084c7ddc1c6e11f02eb6a6016ca1318dd5452ba3f613a1751 --hash=sha256:19d40d37c1c3a4961b4619dd9d77b12124a453cc3d02bb31a07d58ef684d3d86 --hash=sha256:1bf98051f1045b15c87868dbaea84f92408337d4f81d0e449ee41920ea121d3b --hash=sha256:20914c8c973f41456337652a6eeca26d2148aa96dd7ac323b74516988bea89fc --hash=sha256:287ccc248c9e0d0566934e7d606201abd74761b5703d804ff3df8935f523d546 --hash=sha256:2ba94a401342fc0f8b948e57d977557fbf4d515f03c67682dd5c6191cb2d16ec --hash=sha256:31c1b55c1f34f80557d3830d3dd93ba722ce7e33a0b472cba0ec3b6535684d8f --hash=sha256:36987a15e8ace5f58d4d5da9dca82d498c2bbb28dff6e5d04fbfcc35a9cb3a82 --hash=sha256:3a04ecd68acbd77fa2d39723ceca4c3197cb2969633836ced1bea14e219d077c --hash=sha256:3e8b974d8db2c5610fb4e76307e265de0edb655ae8169e8b21f41807ccbeec4b --hash=sha256:3ea9924d28fc5586bf0b42d15f590b10c224117e74409dd7a0be3b62b74a501c --hash=sha256:4318af1c925fb9a4fb190559ef3eec206845f63e80fb603d47f2d6d67683901c --hash=sha256:44a29502ca9c7b5ba389e620d44f2fbe792b1fb5734e8b931ad307071ec58c53 --hash=sha256:47734d7073fb4590b4a40122b35917cd77be5722d80683b249dac1de266aac80 --hash=sha256:4d76d5993a34ef3df5181ba3c92fabb93f1eaa5729504fb03423fcd9f3177242 --hash=sha256:4dbbc03a40f916a8420e420d63e96a1258d3d1b58cbdfd8d1f07b49fcbd38e85 --hash=sha256:500360b77259914f7805af7462e41f9cb7ca92ad38e9f94d6c8641b089338124 --hash=sha256:523a8ee12edfa36f6d2a49407f705a6ef4c5098de4f498619787e272de93f2d5 --hash=sha256:573abb30e0e05bf31ed067d2f82500ecfdaec15627a59d63ea2d95714790f5c2 --hash=sha256:5b75aa69cb4d6f137b36f7eb2ace9280cfb60c55dc5f61c731fdf6f037f958a3 --hash=sha256:61332c87493b00091423e747ea78200659dc09bdf7fd69edd5e98cef5d3e9a8d --hash=sha256:805617228ba7e2cbbfb6c503858e626ab528ac2a32a04a2fe88ffaf6b02c32bc --hash=sha256:841ad858cff65c2c04bf93875e384ccb82b654574a6d7f30453a04f04af71342 --hash=sha256:89785bb2a1980c1bd87f0cb1517a71cde374776a5f150936b82580ae6ead44a1 --hash=sha256:8eb96e79b9f3dcadbad2a3891672f81cdcab7f95b27f28f1c67d75f045b6b4f1 --hash=sha256:974d8145f8ca354498005b5b981165b74a195abfae9a8129df3e56771961d595 --hash=sha256:9ddeb796389dadcd884c7eb07bd14ef12408aaae358f0e2ae24114d797eede30 --hash=sha256:a045f341a77b77e1c5de31e74e966537bba9f3c4099b35bf4c2e3939dd54cdab --hash=sha256:a0cffcbede75c059f535725c1680dfb17b6ba8753f0c74b14e6a9c68c29d7ea3 --hash=sha256:a761d9ccfc5e2ecd1bf05534eda382aa14c3e4f9205ba5b1684ecfe400716ef2 --hash=sha256:a7895f46d47671fa7ceec40f31fae721da51ad34bdca0bee83e38870b1f47ffd --hash=sha256:a9fa36448e6a3a1a9a2ba23c02012c43ed88905ec80163f2ffe2421c7192a5d7 --hash=sha256:ab29962927945d89d9b293eabd0d59aea28d887d4f3be6c22deaefbb938a7277 --hash=sha256:abbb49fb7dac584e5abc6636b7b2a7227111c4f771005853e7d25176daaf8453 --hash=sha256:ac4578ac281983f63b400f7fe6c101bedc10651650eef012be1ccffcbacf3697 --hash=sha256:adce39d67c0edf383647a3a007de0a45fd1b08dedaa5318404f1a73059c2512b --hash=sha256:ade08d343436a94e633db932e7e8407fe7de8083967962b46bdfc1b0ced39454 --hash=sha256:b2bdca22a27e35f16794cf585832e542123296b4687f9fd96822db6bae17bfc9 --hash=sha256:b2f926efda994cdf3c8d3fdb40b9962f86edbc4457e739277b961eced3d0b4c1 --hash=sha256:b457d6430833cee8e4b8e9b6f07aa1c161e5e0d52e118dc102c8f9bd7dd060d6 --hash=sha256:c414fc1ed8ee1dbd5da626cf3710c6013d3d27456651d156711fa24f24bd1291 --hash=sha256:cb76c1a154b83991a3cbbf0dfeb26ec2833ad56f95540b442c73950af2013750 --hash=sha256:dfd97abd83335045a913e3bcc4a09c0ceadbe66580cf573fe961f4a825efa699 --hash=sha256:e914a8cb05ce5c809dd0fe350cfbb4e881bde5e2a38dc04e3afe1b3e58bd158e --hash=sha256:ece6df05e2c41bd46776fbc712e0996f7c94e0d0543af1656956d150c4ca7c81 --hash=sha256:efa874e87e4a647fd2e4f514d5e91c7d493697127beb95e77d2f7561f6905bd9 --hash=sha256:f611e628ef06670df83fce17805c344710ca5cde01edfdc72751311da8585375" + } + }, + "bazel-orfs-pip_313_cycler": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "cycler==0.12.1 --hash=sha256:85cef7cff222d8644161529808465972e51340599459b8ac3ccbac5a854e0d30 --hash=sha256:88bb128f02ba341da8ef447245a9e138fae777f6a23943da4540077d3601eb1c" + } + }, + "bazel-orfs-pip_313_fonttools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "fonttools==4.55.3 --hash=sha256:07f8288aacf0a38d174445fc78377a97fb0b83cfe352a90c9d9c1400571963c7 --hash=sha256:11e5de1ee0d95af4ae23c1a138b184b7f06e0b6abacabf1d0db41c90b03d834b --hash=sha256:1bc7ad24ff98846282eef1cbeac05d013c2154f977a79886bb943015d2b1b261 --hash=sha256:1dcc07934a2165ccdc3a5a608db56fb3c24b609658a5b340aee4ecf3ba679dc0 --hash=sha256:22f38464daa6cdb7b6aebd14ab06609328fe1e9705bb0fcc7d1e69de7109ee02 --hash=sha256:27e4ae3592e62eba83cd2c4ccd9462dcfa603ff78e09110680a5444c6925d841 --hash=sha256:3983313c2a04d6cc1fe9251f8fc647754cf49a61dac6cb1e7249ae67afaafc45 --hash=sha256:529cef2ce91dc44f8e407cc567fae6e49a1786f2fefefa73a294704c415322a4 --hash=sha256:5323a22eabddf4b24f66d26894f1229261021dacd9d29e89f7872dd8c63f0b8b --hash=sha256:54153c49913f45065c8d9e6d0c101396725c5621c8aee744719300f79771d75a --hash=sha256:546565028e244a701f73df6d8dd6be489d01617863ec0c6a42fa25bf45d43048 --hash=sha256:5480673f599ad410695ca2ddef2dfefe9df779a9a5cda89503881e503c9c7d90 --hash=sha256:5e8d657cd7326eeaba27de2740e847c6b39dde2f8d7cd7cc56f6aad404ddf0bd --hash=sha256:62d65a3022c35e404d19ca14f291c89cc5890032ff04f6c17af0bd1927299674 --hash=sha256:6314bf82c54c53c71805318fcf6786d986461622dd926d92a465199ff54b1b72 --hash=sha256:7a8aa2c5e5b8b3bcb2e4538d929f6589a5c6bdb84fd16e2ed92649fb5454f11c --hash=sha256:827e95fdbbd3e51f8b459af5ea10ecb4e30af50221ca103bea68218e9615de07 --hash=sha256:859c358ebf41db18fb72342d3080bce67c02b39e86b9fbcf1610cca14984841b --hash=sha256:86721fbc389ef5cc1e2f477019e5069e8e4421e8d9576e9c26f840dbb04678de --hash=sha256:89bdc5d88bdeec1b15af790810e267e8332d92561dce4f0748c2b95c9bdf3926 --hash=sha256:8c4491699bad88efe95772543cd49870cf756b019ad56294f6498982408ab03e --hash=sha256:8c5ec45428edaa7022f1c949a632a6f298edc7b481312fc7dc258921e9399628 --hash=sha256:8e75f12c82127486fac2d8bfbf5bf058202f54bf4f158d367e41647b972342ca --hash=sha256:a430178ad3e650e695167cb53242dae3477b35c95bef6525b074d87493c4bf29 --hash=sha256:a8c2794ded89399cc2169c4d0bf7941247b8d5932b2659e09834adfbb01589aa --hash=sha256:aca318b77f23523309eec4475d1fbbb00a6b133eb766a8bdc401faba91261abe --hash=sha256:ae3b6600565b2d80b7c05acb8e24d2b26ac407b27a3f2e078229721ba5698427 --hash=sha256:aedbeb1db64496d098e6be92b2e63b5fac4e53b1b92032dfc6988e1ea9134a4d --hash=sha256:aee3b57643827e237ff6ec6d28d9ff9766bd8b21e08cd13bff479e13d4b14765 --hash=sha256:b54baf65c52952db65df39fcd4820668d0ef4766c0ccdf32879b77f7c804d5c5 --hash=sha256:b586ab5b15b6097f2fb71cafa3c98edfd0dba1ad8027229e7b1e204a58b0e09d --hash=sha256:b8d5e8916c0970fbc0f6f1bece0063363bb5857a7f170121a4493e31c3db3314 --hash=sha256:bc5dbb4685e51235ef487e4bd501ddfc49be5aede5e40f4cefcccabc6e60fb4b --hash=sha256:bdcc9f04b36c6c20978d3f060e5323a43f6222accc4e7fcbef3f428e216d96af --hash=sha256:c3ca99e0d460eff46e033cd3992a969658c3169ffcd533e0a39c63a38beb6831 --hash=sha256:caf8230f3e10f8f5d7593eb6d252a37caf58c480b19a17e250a63dad63834cf3 --hash=sha256:cd70de1a52a8ee2d1877b6293af8a2484ac82514f10b1c67c1c5762d38073e56 --hash=sha256:cf4fe7c124aa3f4e4c1940880156e13f2f4d98170d35c749e6b4f119a872551e --hash=sha256:d342e88764fb201286d185093781bf6628bbe380a913c24adf772d901baa8276 --hash=sha256:da9da6d65cd7aa6b0f806556f4985bcbf603bf0c5c590e61b43aa3e5a0f822d0 --hash=sha256:dc5294a3d5c84226e3dbba1b6f61d7ad813a8c0238fceea4e09aa04848c3d851 --hash=sha256:dd68c87a2bfe37c5b33bcda0fba39b65a353876d3b9006fde3adae31f97b3ef5 --hash=sha256:e6e8766eeeb2de759e862004aa11a9ea3d6f6d5ec710551a88b476192b64fd54 --hash=sha256:e894b5bd60d9f473bed7a8f506515549cc194de08064d829464088d23097331b --hash=sha256:eb6ca911c4c17eb51853143624d8dc87cdcdf12a711fc38bf5bd21521e79715f --hash=sha256:ed63959d00b61959b035c7d47f9313c2c1ece090ff63afea702fe86de00dbed4 --hash=sha256:f412604ccbeee81b091b420272841e5ec5ef68967a9790e80bffd0e30b8e2977 --hash=sha256:f7d66c15ba875432a2d2fb419523f5d3d347f91f48f57b8b08a2dfc3c39b8a3f --hash=sha256:f9e736f60f4911061235603a6119e72053073a12c6d7904011df2d8fad2c0e35 --hash=sha256:fb594b5a99943042c702c550d5494bdd7577f6ef19b0bc73877c948a63184a32" + } + }, + "bazel-orfs-pip_313_kiwisolver": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "kiwisolver==1.4.7 --hash=sha256:073a36c8273647592ea332e816e75ef8da5c303236ec0167196793eb1e34657a --hash=sha256:08471d4d86cbaec61f86b217dd938a83d85e03785f51121e791a6e6689a3be95 --hash=sha256:0c18ec74c0472de033e1bebb2911c3c310eef5649133dd0bedf2a169a1b269e5 --hash=sha256:0c6c43471bc764fad4bc99c5c2d6d16a676b1abf844ca7c8702bdae92df01ee0 --hash=sha256:10849fb2c1ecbfae45a693c070e0320a91b35dd4bcf58172c023b994283a124d --hash=sha256:18077b53dc3bb490e330669a99920c5e6a496889ae8c63b58fbc57c3d7f33a18 --hash=sha256:18e0cca3e008e17fe9b164b55735a325140a5a35faad8de92dd80265cd5eb80b --hash=sha256:22f499f6157236c19f4bbbd472fa55b063db77a16cd74d49afe28992dff8c258 --hash=sha256:2a8781ac3edc42ea4b90bc23e7d37b665d89423818e26eb6df90698aa2287c95 --hash=sha256:2e6039dcbe79a8e0f044f1c39db1986a1b8071051efba3ee4d74f5b365f5226e --hash=sha256:34ea1de54beef1c104422d210c47c7d2a4999bdecf42c7b5718fbe59a4cac383 --hash=sha256:3ab58c12a2cd0fc769089e6d38466c46d7f76aced0a1f54c77652446733d2d02 --hash=sha256:3abc5b19d24af4b77d1598a585b8a719beb8569a71568b66f4ebe1fb0449460b --hash=sha256:3bf1ed55088f214ba6427484c59553123fdd9b218a42bbc8c6496d6754b1e523 --hash=sha256:3ce6b2b0231bda412463e152fc18335ba32faf4e8c23a754ad50ffa70e4091ee --hash=sha256:3da53da805b71e41053dc670f9a820d1157aae77b6b944e08024d17bcd51ef88 --hash=sha256:3f9362ecfca44c863569d3d3c033dbe8ba452ff8eed6f6b5806382741a1334bd --hash=sha256:409afdfe1e2e90e6ee7fc896f3df9a7fec8e793e58bfa0d052c8a82f99c37abb --hash=sha256:40fa14dbd66b8b8f470d5fc79c089a66185619d31645f9b0773b88b19f7223c4 --hash=sha256:4322872d5772cae7369f8351da1edf255a604ea7087fe295411397d0cfd9655e --hash=sha256:44756f9fd339de0fb6ee4f8c1696cfd19b2422e0d70b4cefc1cc7f1f64045a8c --hash=sha256:46707a10836894b559e04b0fd143e343945c97fd170d69a2d26d640b4e297935 --hash=sha256:48b571ecd8bae15702e4f22d3ff6a0f13e54d3d00cd25216d5e7f658242065ee --hash=sha256:48be928f59a1f5c8207154f935334d374e79f2b5d212826307d072595ad76a2e --hash=sha256:4bfa75a048c056a411f9705856abfc872558e33c055d80af6a380e3658766038 --hash=sha256:4c00336b9dd5ad96d0a558fd18a8b6f711b7449acce4c157e7343ba92dd0cf3d --hash=sha256:4c26ed10c4f6fa6ddb329a5120ba3b6db349ca192ae211e882970bfc9d91420b --hash=sha256:4d05d81ecb47d11e7f8932bd8b61b720bf0b41199358f3f5e36d38e28f0532c5 --hash=sha256:4e77f2126c3e0b0d055f44513ed349038ac180371ed9b52fe96a32aa071a5107 --hash=sha256:5337ec7809bcd0f424c6b705ecf97941c46279cf5ed92311782c7c9c2026f07f --hash=sha256:5360cc32706dab3931f738d3079652d20982511f7c0ac5711483e6eab08efff2 --hash=sha256:58370b1ffbd35407444d57057b57da5d6549d2d854fa30249771775c63b5fe17 --hash=sha256:58cb20602b18f86f83a5c87d3ee1c766a79c0d452f8def86d925e6c60fbf7bfb --hash=sha256:599b5c873c63a1f6ed7eead644a8a380cfbdf5db91dcb6f85707aaab213b1674 --hash=sha256:5b7dfa3b546da08a9f622bb6becdb14b3e24aaa30adba66749d38f3cc7ea9706 --hash=sha256:5b9c3f4ee0b9a439d2415012bd1b1cc2df59e4d6a9939f4d669241d30b414327 --hash=sha256:5d34eb8494bea691a1a450141ebb5385e4b69d38bb8403b5146ad279f4b30fa3 --hash=sha256:5d5abf8f8ec1f4e22882273c423e16cae834c36856cac348cfbfa68e01c40f3a --hash=sha256:5e3bc157fed2a4c02ec468de4ecd12a6e22818d4f09cde2c31ee3226ffbefab2 --hash=sha256:612a10bdae23404a72941a0fc8fa2660c6ea1217c4ce0dbcab8a8f6543ea9e7f --hash=sha256:657a05857bda581c3656bfc3b20e353c232e9193eb167766ad2dc58b56504948 --hash=sha256:65e720d2ab2b53f1f72fb5da5fb477455905ce2c88aaa671ff0a447c2c80e8e3 --hash=sha256:693902d433cf585133699972b6d7c42a8b9f8f826ebcaf0132ff55200afc599e --hash=sha256:6af936f79086a89b3680a280c47ea90b4df7047b5bdf3aa5c524bbedddb9e545 --hash=sha256:71bb308552200fb2c195e35ef05de12f0c878c07fc91c270eb3d6e41698c3bcc --hash=sha256:764202cc7e70f767dab49e8df52c7455e8de0df5d858fa801a11aa0d882ccf3f --hash=sha256:76c8094ac20ec259471ac53e774623eb62e6e1f56cd8690c67ce6ce4fcb05650 --hash=sha256:78a42513018c41c2ffd262eb676442315cbfe3c44eed82385c2ed043bc63210a --hash=sha256:79849239c39b5e1fd906556c474d9b0439ea6792b637511f3fe3a41158d89ca8 --hash=sha256:7ab9ccab2b5bd5702ab0803676a580fffa2aa178c2badc5557a84cc943fcf750 --hash=sha256:7bbfcb7165ce3d54a3dfbe731e470f65739c4c1f85bb1018ee912bae139e263b --hash=sha256:7c06a4c7cf15ec739ce0e5971b26c93638730090add60e183530d70848ebdd34 --hash=sha256:801fa7802e5cfabe3ab0c81a34c323a319b097dfb5004be950482d882f3d7225 --hash=sha256:803b8e1459341c1bb56d1c5c010406d5edec8a0713a0945851290a7930679b51 --hash=sha256:82a5c2f4b87c26bb1a0ef3d16b5c4753434633b83d365cc0ddf2770c93829e3c --hash=sha256:84ec80df401cfee1457063732d90022f93951944b5b58975d34ab56bb150dfb3 --hash=sha256:8705f17dfeb43139a692298cb6637ee2e59c0194538153e83e9ee0c75c2eddde --hash=sha256:88a9ca9c710d598fd75ee5de59d5bda2684d9db36a9f50b6125eaea3969c2599 --hash=sha256:88f17c5ffa8e9462fb79f62746428dd57b46eb931698e42e990ad63103f35e6c --hash=sha256:8a3ec5aa8e38fc4c8af308917ce12c536f1c88452ce554027e55b22cbbfbff76 --hash=sha256:8a9c83f75223d5e48b0bc9cb1bf2776cf01563e00ade8775ffe13b0b6e1af3a6 --hash=sha256:8b01aac285f91ca889c800042c35ad3b239e704b150cfd3382adfc9dcc780e39 --hash=sha256:8d53103597a252fb3ab8b5845af04c7a26d5e7ea8122303dd7a021176a87e8b9 --hash=sha256:8e045731a5416357638d1700927529e2b8ab304811671f665b225f8bf8d8f933 --hash=sha256:8f0ea6da6d393d8b2e187e6a5e3fb81f5862010a40c3945e2c6d12ae45cfb2ad --hash=sha256:90da3b5f694b85231cf93586dad5e90e2d71b9428f9aad96952c99055582f520 --hash=sha256:913983ad2deb14e66d83c28b632fd35ba2b825031f2fa4ca29675e665dfecbe1 --hash=sha256:9242795d174daa40105c1d86aba618e8eab7bf96ba8c3ee614da8302a9f95503 --hash=sha256:929e294c1ac1e9f615c62a4e4313ca1823ba37326c164ec720a803287c4c499b --hash=sha256:933d4de052939d90afbe6e9d5273ae05fb836cc86c15b686edd4b3560cc0ee36 --hash=sha256:942216596dc64ddb25adb215c3c783215b23626f8d84e8eff8d6d45c3f29f75a --hash=sha256:94252291e3fe68001b1dd747b4c0b3be12582839b95ad4d1b641924d68fd4643 --hash=sha256:9893ff81bd7107f7b685d3017cc6583daadb4fc26e4a888350df530e41980a60 --hash=sha256:9e838bba3a3bac0fe06d849d29772eb1afb9745a59710762e4ba3f4cb8424483 --hash=sha256:a0f64a48bb81af7450e641e3fe0b0394d7381e342805479178b3d335d60ca7cf --hash=sha256:a17f6a29cf8935e587cc8a4dbfc8368c55edc645283db0ce9801016f83526c2d --hash=sha256:a1ecf0ac1c518487d9d23b1cd7139a6a65bc460cd101ab01f1be82ecf09794b6 --hash=sha256:a79ae34384df2b615eefca647a2873842ac3b596418032bef9a7283675962644 --hash=sha256:a91b5f9f1205845d488c928e8570dcb62b893372f63b8b6e98b863ebd2368ff2 --hash=sha256:aa0abdf853e09aff551db11fce173e2177d00786c688203f52c87ad7fcd91ef9 --hash=sha256:ac542bf38a8a4be2dc6b15248d36315ccc65f0743f7b1a76688ffb6b5129a5c2 --hash=sha256:ad42ba922c67c5f219097b28fae965e10045ddf145d2928bfac2eb2e17673640 --hash=sha256:aeb3531b196ef6f11776c21674dba836aeea9d5bd1cf630f869e3d90b16cfade --hash=sha256:b38ac83d5f04b15e515fd86f312479d950d05ce2368d5413d46c088dda7de90a --hash=sha256:b7d755065e4e866a8086c9bdada157133ff466476a2ad7861828e17b6026e22c --hash=sha256:bd3de6481f4ed8b734da5df134cd5a6a64fe32124fe83dde1e5b5f29fe30b1e6 --hash=sha256:bfa1acfa0c54932d5607e19a2c24646fb4c1ae2694437789129cf099789a3b00 --hash=sha256:c619b101e6de2222c1fcb0531e1b17bbffbe54294bfba43ea0d411d428618c27 --hash=sha256:ce8be0466f4c0d585cdb6c1e2ed07232221df101a4c6f28821d2aa754ca2d9e2 --hash=sha256:cf0438b42121a66a3a667de17e779330fc0f20b0d97d59d2f2121e182b0505e4 --hash=sha256:cf8bcc23ceb5a1b624572a1623b9f79d2c3b337c8c455405ef231933a10da379 --hash=sha256:d2b0e12a42fb4e72d509fc994713d099cbb15ebf1103545e8a45f14da2dfca54 --hash=sha256:d83db7cde68459fc803052a55ace60bea2bae361fc3b7a6d5da07e11954e4b09 --hash=sha256:dda56c24d869b1193fcc763f1284b9126550eaf84b88bbc7256e15028f19188a --hash=sha256:dea0bf229319828467d7fca8c7c189780aa9ff679c94539eed7532ebe33ed37c --hash=sha256:e1631290ee9271dffe3062d2634c3ecac02c83890ada077d225e081aca8aab89 --hash=sha256:e28c7fea2196bf4c2f8d46a0415c77a1c480cc0724722f23d7410ffe9842c407 --hash=sha256:e2e6c39bd7b9372b0be21456caab138e8e69cc0fc1190a9dfa92bd45a1e6e904 --hash=sha256:e33e8fbd440c917106b237ef1a2f1449dfbb9b6f6e1ce17c94cd6a1e0d438376 --hash=sha256:e8df2eb9b2bac43ef8b082e06f750350fbbaf2887534a5be97f6cf07b19d9583 --hash=sha256:e968b84db54f9d42046cf154e02911e39c0435c9801681e3fc9ce8a3c4130278 --hash=sha256:eb542fe7933aa09d8d8f9d9097ef37532a7df6497819d16efe4359890a2f417a --hash=sha256:edcfc407e4eb17e037bca59be0e85a2031a2ac87e4fed26d3e9df88b4165f92d --hash=sha256:eee3ea935c3d227d49b4eb85660ff631556841f6e567f0f7bda972df6c2c9935 --hash=sha256:ef97b8df011141c9b0f6caf23b29379f87dd13183c978a30a3c546d2c47314cb --hash=sha256:f106407dda69ae456dd1227966bf445b157ccc80ba0dff3802bb63f30b74e895 --hash=sha256:f3160309af4396e0ed04db259c3ccbfdc3621b5559b5453075e5de555e1f3a1b --hash=sha256:f32d6edbc638cde7652bd690c3e728b25332acbadd7cad670cc4a02558d9c417 --hash=sha256:f37cfe618a117e50d8c240555331160d73d0411422b59b5ee217843d7b693608 --hash=sha256:f4c9aee212bc89d4e13f58be11a56cc8036cabad119259d12ace14b34476fd07 --hash=sha256:f4d742cb7af1c28303a51b7a27aaee540e71bb8e24f68c736f6f2ffc82f2bf05 --hash=sha256:f5a8b53bdc0b3961f8b6125e198617c40aeed638b387913bf1ce78afb1b0be2a --hash=sha256:f816dd2277f8d63d79f9c8473a79fe54047bc0467754962840782c575522224d --hash=sha256:f9a9e8a507420fe35992ee9ecb302dab68550dedc0da9e2880dd88071c5fb052" + } + }, + "bazel-orfs-pip_313_matplotlib": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "matplotlib==3.10.0 --hash=sha256:01d2b19f13aeec2e759414d3bfe19ddfb16b13a1250add08d46d5ff6f9be83c6 --hash=sha256:12eaf48463b472c3c0f8dbacdbf906e573013df81a0ab82f0616ea4b11281908 --hash=sha256:2c5829a5a1dd5a71f0e31e6e8bb449bc0ee9dbfb05ad28fc0c6b55101b3a4be6 --hash=sha256:2fbbabc82fde51391c4da5006f965e36d86d95f6ee83fb594b279564a4c5d0d2 --hash=sha256:3547d153d70233a8496859097ef0312212e2689cdf8d7ed764441c77604095ae --hash=sha256:359f87baedb1f836ce307f0e850d12bb5f1936f70d035561f90d41d305fdacea --hash=sha256:3b427392354d10975c1d0f4ee18aa5844640b512d5311ef32efd4dd7db106ede --hash=sha256:4659665bc7c9b58f8c00317c3c2a299f7f258eeae5a5d56b4c64226fca2f7c59 --hash=sha256:4673ff67a36152c48ddeaf1135e74ce0d4bce1bbf836ae40ed39c29edf7e2765 --hash=sha256:503feb23bd8c8acc75541548a1d709c059b7184cde26314896e10a9f14df5f12 --hash=sha256:5439f4c5a3e2e8eab18e2f8c3ef929772fd5641876db71f08127eed95ab64683 --hash=sha256:5cdbaf909887373c3e094b0318d7ff230b2ad9dcb64da7ade654182872ab2593 --hash=sha256:5e6c6461e1fc63df30bf6f80f0b93f5b6784299f721bc28530477acd51bfc3d1 --hash=sha256:5fd41b0ec7ee45cd960a8e71aea7c946a28a0b8a4dcee47d2856b2af051f334c --hash=sha256:607b16c8a73943df110f99ee2e940b8a1cbf9714b65307c040d422558397dac5 --hash=sha256:7e8632baebb058555ac0cde75db885c61f1212e47723d63921879806b40bec6a --hash=sha256:81713dd0d103b379de4516b861d964b1d789a144103277769238c732229d7f03 --hash=sha256:845d96568ec873be63f25fa80e9e7fae4be854a66a7e2f0c8ccc99e94a8bd4ef --hash=sha256:95b710fea129c76d30be72c3b38f330269363fbc6e570a5dd43580487380b5ff --hash=sha256:96f2886f5c1e466f21cc41b70c5a0cd47bfa0015eb2d5793c88ebce658600e25 --hash=sha256:994c07b9d9fe8d25951e3202a68c17900679274dadfc1248738dcfa1bd40d7f3 --hash=sha256:9ade1003376731a971e398cc4ef38bb83ee8caf0aee46ac6daa4b0506db1fd06 --hash=sha256:9b0558bae37f154fffda54d779a592bc97ca8b4701f1c710055b609a3bac44c8 --hash=sha256:a2a43cbefe22d653ab34bb55d42384ed30f611bcbdea1f8d7f431011a2e1c62e --hash=sha256:a994f29e968ca002b50982b27168addfd65f0105610b6be7fa515ca4b5307c95 --hash=sha256:ad2e15300530c1a94c63cfa546e3b7864bd18ea2901317bae8bbf06a5ade6dcf --hash=sha256:ae80dc3a4add4665cf2faa90138384a7ffe2a4e37c58d83e115b54287c4f06ef --hash=sha256:b886d02a581b96704c9d1ffe55709e49b4d2d52709ccebc4be42db856e511278 --hash=sha256:c40ba2eb08b3f5de88152c2333c58cee7edcead0a2a0d60fcafa116b17117adc --hash=sha256:c55b20591ced744aa04e8c3e4b7543ea4d650b6c3c4b208c08a05b4010e8b442 --hash=sha256:c58a9622d5dbeb668f407f35f4e6bfac34bb9ecdcc81680c04d0258169747997 --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363" + } + }, + "bazel-orfs-pip_313_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "numpy==2.2.0 --hash=sha256:0557eebc699c1c34cccdd8c3778c9294e8196df27d713706895edc6f57d29608 --hash=sha256:0798b138c291d792f8ea40fe3768610f3c7dd2574389e37c3f26573757c8f7ef --hash=sha256:0da8495970f6b101ddd0c38ace92edea30e7e12b9a926b57f5fabb1ecc25bb90 --hash=sha256:0f0986e917aca18f7a567b812ef7ca9391288e2acb7a4308aa9d265bd724bdae --hash=sha256:122fd2fcfafdefc889c64ad99c228d5a1f9692c3a83f56c292618a59aa60ae83 --hash=sha256:140dd80ff8981a583a60980be1a655068f8adebf7a45a06a6858c873fcdcd4a0 --hash=sha256:16757cf28621e43e252c560d25b15f18a2f11da94fea344bf26c599b9cf54b73 --hash=sha256:18142b497d70a34b01642b9feabb70156311b326fdddd875a9981f34a369b671 --hash=sha256:1c92113619f7b272838b8d6702a7f8ebe5edea0df48166c47929611d0b4dea69 --hash=sha256:1e25507d85da11ff5066269d0bd25d06e0a0f2e908415534f3e603d2a78e4ffa --hash=sha256:30bf971c12e4365153afb31fc73f441d4da157153f3400b82db32d04de1e4066 --hash=sha256:3579eaeb5e07f3ded59298ce22b65f877a86ba8e9fe701f5576c99bb17c283da --hash=sha256:36b2b43146f646642b425dd2027730f99bac962618ec2052932157e213a040e9 --hash=sha256:3905a5fffcc23e597ee4d9fb3fcd209bd658c352657548db7316e810ca80458e --hash=sha256:3a4199f519e57d517ebd48cb76b36c82da0360781c6a0353e64c0cac30ecaad3 --hash=sha256:3f2f5cddeaa4424a0a118924b988746db6ffa8565e5829b1841a8a3bd73eb59a --hash=sha256:40deb10198bbaa531509aad0cd2f9fadb26c8b94070831e2208e7df543562b74 --hash=sha256:440cfb3db4c5029775803794f8638fbdbf71ec702caf32735f53b008e1eaece3 --hash=sha256:4723a50e1523e1de4fccd1b9a6dcea750c2102461e9a02b2ac55ffeae09a4410 --hash=sha256:4bddbaa30d78c86329b26bd6aaaea06b1e47444da99eddac7bf1e2fab717bd72 --hash=sha256:4e58666988605e251d42c2818c7d3d8991555381be26399303053b58a5bbf30d --hash=sha256:54dc1d6d66f8d37843ed281773c7174f03bf7ad826523f73435deb88ba60d2d4 --hash=sha256:57fcc997ffc0bef234b8875a54d4058afa92b0b0c4223fc1f62f24b3b5e86038 --hash=sha256:58b92a5828bd4d9aa0952492b7de803135038de47343b2aa3cc23f3b71a3dc4e --hash=sha256:5a145e956b374e72ad1dff82779177d4a3c62bc8248f41b80cb5122e68f22d13 --hash=sha256:6ab153263a7c5ccaf6dfe7e53447b74f77789f28ecb278c3b5d49db7ece10d6d --hash=sha256:7832f9e8eb00be32f15fdfb9a981d6955ea9adc8574c521d48710171b6c55e95 --hash=sha256:7fe4bb0695fe986a9e4deec3b6857003b4cfe5c5e4aac0b95f6a658c14635e31 --hash=sha256:7fe8f3583e0607ad4e43a954e35c1748b553bfe9fdac8635c02058023277d1b3 --hash=sha256:85ad7d11b309bd132d74397fcf2920933c9d1dc865487128f5c03d580f2c3d03 --hash=sha256:9874bc2ff574c40ab7a5cbb7464bf9b045d617e36754a7bc93f933d52bd9ffc6 --hash=sha256:a184288538e6ad699cbe6b24859206e38ce5fba28f3bcfa51c90d0502c1582b2 --hash=sha256:a222d764352c773aa5ebde02dd84dba3279c81c6db2e482d62a3fa54e5ece69b --hash=sha256:a50aeff71d0f97b6450d33940c7181b08be1441c6c193e678211bff11aa725e7 --hash=sha256:a55dc7a7f0b6198b07ec0cd445fbb98b05234e8b00c5ac4874a63372ba98d4ab --hash=sha256:a62eb442011776e4036af5c8b1a00b706c5bc02dc15eb5344b0c750428c94219 --hash=sha256:a7d41d1612c1a82b64697e894b75db6758d4f21c3ec069d841e60ebe54b5b571 --hash=sha256:a98f6f20465e7618c83252c02041517bd2f7ea29be5378f09667a8f654a5918d --hash=sha256:afe8fb968743d40435c3827632fd36c5fbde633b0423da7692e426529b1759b1 --hash=sha256:b0b227dcff8cdc3efbce66d4e50891f04d0a387cce282fe1e66199146a6a8fca --hash=sha256:b30042fe92dbd79f1ba7f6898fada10bdaad1847c44f2dff9a16147e00a93661 --hash=sha256:b606b1aaf802e6468c2608c65ff7ece53eae1a6874b3765f69b8ceb20c5fa78e --hash=sha256:b6207dc8fb3c8cb5668e885cef9ec7f70189bec4e276f0ff70d5aa078d32c88e --hash=sha256:c2aed8fcf8abc3020d6a9ccb31dbc9e7d7819c56a348cc88fd44be269b37427e --hash=sha256:cb24cca1968b21355cc6f3da1a20cd1cebd8a023e3c5b09b432444617949085a --hash=sha256:cff210198bb4cae3f3c100444c5eaa573a823f05c253e7188e1362a5555235b3 --hash=sha256:d35717333b39d1b6bb8433fa758a55f1081543de527171543a2b710551d40881 --hash=sha256:df12a1f99b99f569a7c2ae59aa2d31724e8d835fc7f33e14f4792e3071d11221 --hash=sha256:e09d40edfdb4e260cb1567d8ae770ccf3b8b7e9f0d9b5c2a9992696b30ce2742 --hash=sha256:e12c6c1ce84628c52d6367863773f7c8c8241be554e8b79686e91a43f1733773 --hash=sha256:e2b8cd48a9942ed3f85b95ca4105c45758438c7ed28fff1e4ce3e57c3b589d8e --hash=sha256:e500aba968a48e9019e42c0c199b7ec0696a97fa69037bea163b55398e390529 --hash=sha256:ebe5e59545401fbb1b24da76f006ab19734ae71e703cdb4a8b347e84a0cece67 --hash=sha256:f0dd071b95bbca244f4cb7f70b77d2ff3aaaba7fa16dc41f58d14854a6204e6c --hash=sha256:f8c8b141ef9699ae777c6278b52c706b653bf15d135d302754f6b2e90eb30367" + } + }, + "bazel-orfs-pip_313_packaging": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f" + } + }, + "bazel-orfs-pip_313_pandas": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pandas==2.3.0 --hash=sha256:034abd6f3db8b9880aaee98f4f5d4dbec7c4829938463ec046517220b2f8574e --hash=sha256:094e271a15b579650ebf4c5155c05dcd2a14fd4fdd72cf4854b2f7ad31ea30be --hash=sha256:14a0cc77b0f089d2d2ffe3007db58f170dae9b9f54e569b299db871a3ab5bf46 --hash=sha256:1a881bc1309f3fce34696d07b00f13335c41f5f5a8770a33b09ebe23261cfc67 --hash=sha256:1d2b33e68d0ce64e26a4acc2e72d747292084f4e8db4c847c6f5f6cbe56ed6d8 --hash=sha256:213cd63c43263dbb522c1f8a7c9d072e25900f6975596f883f4bebd77295d4f3 --hash=sha256:23c2b2dc5213810208ca0b80b8666670eb4660bbfd9d45f58592cc4ddcfd62e1 --hash=sha256:2c7e2fc25f89a49a11599ec1e76821322439d90820108309bf42130d2f36c983 --hash=sha256:2eb4728a18dcd2908c7fccf74a982e241b467d178724545a48d0caf534b38ebf --hash=sha256:34600ab34ebf1131a7613a260a61dbe8b62c188ec0ea4c296da7c9a06b004133 --hash=sha256:39ff73ec07be5e90330cc6ff5705c651ace83374189dcdcb46e6ff54b4a72cd6 --hash=sha256:404d681c698e3c8a40a61d0cd9412cc7364ab9a9cc6e144ae2992e11a2e77a20 --hash=sha256:40cecc4ea5abd2921682b57532baea5588cc5f80f0231c624056b146887274d2 --hash=sha256:430a63bae10b5086995db1b02694996336e5a8ac9a96b4200572b413dfdfccb9 --hash=sha256:4930255e28ff5545e2ca404637bcc56f031893142773b3468dc021c6c32a1390 --hash=sha256:6021910b086b3ca756755e86ddc64e0ddafd5e58e076c72cb1585162e5ad259b --hash=sha256:625466edd01d43b75b1883a64d859168e4556261a5035b32f9d743b67ef44634 --hash=sha256:75651c14fde635e680496148a8526b328e09fe0572d9ae9b638648c46a544ba3 --hash=sha256:84141f722d45d0c2a89544dd29d35b3abfc13d2250ed7e68394eda7564bd6324 --hash=sha256:8adff9f138fc614347ff33812046787f7d43b3cef7c0f0171b3340cae333f6ca --hash=sha256:951805d146922aed8357e4cc5671b8b0b9be1027f0619cea132a9f3f65f2f09c --hash=sha256:9efc0acbbffb5236fbdf0409c04edce96bec4bdaa649d49985427bd1ec73e085 --hash=sha256:9ff730713d4c4f2f1c860e36c005c7cefc1c7c80c21c0688fd605aa43c9fcf09 --hash=sha256:a6872d695c896f00df46b71648eea332279ef4077a409e2fe94220208b6bb675 --hash=sha256:b198687ca9c8529662213538a9bb1e60fa0bf0f6af89292eb68fea28743fcd5a --hash=sha256:b9d8c3187be7479ea5c3d30c32a5d73d62a621166675063b2edd21bc47614027 --hash=sha256:ba24af48643b12ffe49b27065d3babd52702d95ab70f50e1b34f71ca703e2c0d --hash=sha256:bb32dc743b52467d488e7a7c8039b821da2826a9ba4f85b89ea95274f863280f --hash=sha256:bb3be958022198531eb7ec2008cfc78c5b1eed51af8600c6c5d9160d89d8d249 --hash=sha256:bf5be867a0541a9fb47a4be0c5790a4bccd5b77b92f0a59eeec9375fafc2aa14 --hash=sha256:c06f6f144ad0a1bf84699aeea7eff6068ca5c63ceb404798198af7eb86082e33 --hash=sha256:c6da97aeb6a6d233fb6b17986234cc723b396b50a3c6804776351994f2a658fd --hash=sha256:e0f51973ba93a9f97185049326d75b942b9aeb472bec616a129806facb129ebb --hash=sha256:e1991bbb96f4050b09b5f811253c4f3cf05ee89a589379aa36cd623f21a31d6f --hash=sha256:e5f08eb9a445d07720776df6e641975665c9ea12c9d8a331e0f6890f2dcd76ef --hash=sha256:e78ad363ddb873a631e92a3c063ade1ecfb34cae71e9a2be6ad100f875ac1042 --hash=sha256:ed16339bc354a73e0a609df36d256672c7d296f3f767ac07257801aa064ff73c --hash=sha256:f4dd97c19bd06bc557ad787a15b6489d2614ddaab5d104a0310eb314c724b2d2 --hash=sha256:f925f1ef673b4bd0271b1809b72b3270384f2b7d9d14a189b12b7fc02574d575 --hash=sha256:f95a2aef32614ed86216d3c450ab12a4e82084e8102e355707a1d96e33d51c34 --hash=sha256:fa07e138b3f6c04addfeaf56cc7fdb96c3b68a3fe5e5401251f231fce40a0d7a --hash=sha256:fa35c266c8cd1a67d75971a1912b185b492d257092bdd2709bbdebe574ed228d" + } + }, + "bazel-orfs-pip_313_pillow": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pillow==11.0.0 --hash=sha256:00177a63030d612148e659b55ba99527803288cea7c75fb05766ab7981a8c1b7 --hash=sha256:006bcdd307cc47ba43e924099a038cbf9591062e6c50e570819743f5607404f5 --hash=sha256:084a07ef0821cfe4858fe86652fffac8e187b6ae677e9906e192aafcc1b69903 --hash=sha256:0ae08bd8ffc41aebf578c2af2f9d8749d91f448b3bfd41d7d9ff573d74f2a6b2 --hash=sha256:0e038b0745997c7dcaae350d35859c9715c71e92ffb7e0f4a8e8a16732150f38 --hash=sha256:1187739620f2b365de756ce086fdb3604573337cc28a0d3ac4a01ab6b2d2a6d2 --hash=sha256:16095692a253047fe3ec028e951fa4221a1f3ed3d80c397e83541a3037ff67c9 --hash=sha256:1a61b54f87ab5786b8479f81c4b11f4d61702830354520837f8cc791ebba0f5f --hash=sha256:1c1d72714f429a521d8d2d018badc42414c3077eb187a59579f28e4270b4b0fc --hash=sha256:1e2688958a840c822279fda0086fec1fdab2f95bf2b717b66871c4ad9859d7e8 --hash=sha256:20ec184af98a121fb2da42642dea8a29ec80fc3efbaefb86d8fdd2606619045d --hash=sha256:21a0d3b115009ebb8ac3d2ebec5c2982cc693da935f4ab7bb5c8ebe2f47d36f2 --hash=sha256:224aaa38177597bb179f3ec87eeefcce8e4f85e608025e9cfac60de237ba6316 --hash=sha256:2679d2258b7f1192b378e2893a8a0a0ca472234d4c2c0e6bdd3380e8dfa21b6a --hash=sha256:27a7860107500d813fcd203b4ea19b04babe79448268403172782754870dac25 --hash=sha256:290f2cc809f9da7d6d622550bbf4c1e57518212da51b6a30fe8e0a270a5b78bd --hash=sha256:2e46773dc9f35a1dd28bd6981332fd7f27bec001a918a72a79b4133cf5291dba --hash=sha256:3107c66e43bda25359d5ef446f59c497de2b5ed4c7fdba0894f8d6cf3822dafc --hash=sha256:375b8dd15a1f5d2feafff536d47e22f69625c1aa92f12b339ec0b2ca40263273 --hash=sha256:45c566eb10b8967d71bf1ab8e4a525e5a93519e29ea071459ce517f6b903d7fa --hash=sha256:499c3a1b0d6fc8213519e193796eb1a86a1be4b1877d678b30f83fd979811d1a --hash=sha256:4ad70c4214f67d7466bea6a08061eba35c01b1b89eaa098040a35272a8efb22b --hash=sha256:4b60c9520f7207aaf2e1d94de026682fc227806c6e1f55bba7606d1c94dd623a --hash=sha256:5178952973e588b3f1360868847334e9e3bf49d19e169bbbdfaf8398002419ae --hash=sha256:52a2d8323a465f84faaba5236567d212c3668f2ab53e1c74c15583cf507a0291 --hash=sha256:598b4e238f13276e0008299bd2482003f48158e2b11826862b1eb2ad7c768b97 --hash=sha256:5bd2d3bdb846d757055910f0a59792d33b555800813c3b39ada1829c372ccb06 --hash=sha256:5c39ed17edea3bc69c743a8dd3e9853b7509625c2462532e62baa0732163a904 --hash=sha256:5d203af30149ae339ad1b4f710d9844ed8796e97fda23ffbc4cc472968a47d0b --hash=sha256:5ddbfd761ee00c12ee1be86c9c0683ecf5bb14c9772ddbd782085779a63dd55b --hash=sha256:607bbe123c74e272e381a8d1957083a9463401f7bd01287f50521ecb05a313f8 --hash=sha256:61b887f9ddba63ddf62fd02a3ba7add935d053b6dd7d58998c630e6dbade8527 --hash=sha256:6619654954dc4936fcff82db8eb6401d3159ec6be81e33c6000dfd76ae189947 --hash=sha256:674629ff60030d144b7bca2b8330225a9b11c482ed408813924619c6f302fdbb --hash=sha256:6ec0d5af64f2e3d64a165f490d96368bb5dea8b8f9ad04487f9ab60dc4bb6003 --hash=sha256:6f4dba50cfa56f910241eb7f883c20f1e7b1d8f7d91c750cd0b318bad443f4d5 --hash=sha256:70fbbdacd1d271b77b7721fe3cdd2d537bbbd75d29e6300c672ec6bb38d9672f --hash=sha256:72bacbaf24ac003fea9bff9837d1eedb6088758d41e100c1552930151f677739 --hash=sha256:7326a1787e3c7b0429659e0a944725e1b03eeaa10edd945a86dead1913383944 --hash=sha256:73853108f56df97baf2bb8b522f3578221e56f646ba345a372c78326710d3830 --hash=sha256:73e3a0200cdda995c7e43dd47436c1548f87a30bb27fb871f352a22ab8dcf45f --hash=sha256:75acbbeb05b86bc53cbe7b7e6fe00fbcf82ad7c684b3ad82e3d711da9ba287d3 --hash=sha256:8069c5179902dcdce0be9bfc8235347fdbac249d23bd90514b7a47a72d9fecf4 --hash=sha256:846e193e103b41e984ac921b335df59195356ce3f71dcfd155aa79c603873b84 --hash=sha256:8594f42df584e5b4bb9281799698403f7af489fba84c34d53d1c4bfb71b7c4e7 --hash=sha256:86510e3f5eca0ab87429dd77fafc04693195eec7fd6a137c389c3eeb4cfb77c6 --hash=sha256:8853a3bf12afddfdf15f57c4b02d7ded92c7a75a5d7331d19f4f9572a89c17e6 --hash=sha256:88a58d8ac0cc0e7f3a014509f0455248a76629ca9b604eca7dc5927cc593c5e9 --hash=sha256:8ba470552b48e5835f1d23ecb936bb7f71d206f9dfeee64245f30c3270b994de --hash=sha256:8c676b587da5673d3c75bd67dd2a8cdfeb282ca38a30f37950511766b26858c4 --hash=sha256:8ec4a89295cd6cd4d1058a5e6aec6bf51e0eaaf9714774e1bfac7cfc9051db47 --hash=sha256:94f3e1780abb45062287b4614a5bc0874519c86a777d4a7ad34978e86428b8dd --hash=sha256:9a0f748eaa434a41fccf8e1ee7a3eed68af1b690e75328fd7a60af123c193b50 --hash=sha256:a5629742881bcbc1f42e840af185fd4d83a5edeb96475a575f4da50d6ede337c --hash=sha256:a65149d8ada1055029fcb665452b2814fe7d7082fcb0c5bed6db851cb69b2086 --hash=sha256:b3c5ac4bed7519088103d9450a1107f76308ecf91d6dabc8a33a2fcfb18d0fba --hash=sha256:b4fd7bd29610a83a8c9b564d457cf5bd92b4e11e79a4ee4716a63c959699b306 --hash=sha256:bcd1fb5bb7b07f64c15618c89efcc2cfa3e95f0e3bcdbaf4642509de1942a699 --hash=sha256:c12b5ae868897c7338519c03049a806af85b9b8c237b7d675b8c5e089e4a618e --hash=sha256:c26845094b1af3c91852745ae78e3ea47abf3dbcd1cf962f16b9a5fbe3ee8488 --hash=sha256:c6a660307ca9d4867caa8d9ca2c2658ab685de83792d1876274991adec7b93fa --hash=sha256:c809a70e43c7977c4a42aefd62f0131823ebf7dd73556fa5d5950f5b354087e2 --hash=sha256:c8b2351c85d855293a299038e1f89db92a2f35e8d2f783489c6f0b2b5f3fe8a3 --hash=sha256:cb929ca942d0ec4fac404cbf520ee6cac37bf35be479b970c4ffadf2b6a1cad9 --hash=sha256:d2c0a187a92a1cb5ef2c8ed5412dd8d4334272617f532d4ad4de31e0495bd923 --hash=sha256:d69bfd8ec3219ae71bcde1f942b728903cad25fafe3100ba2258b973bd2bc1b2 --hash=sha256:daffdf51ee5db69a82dd127eabecce20729e21f7a3680cf7cbb23f0829189790 --hash=sha256:e58876c91f97b0952eb766123bfef372792ab3f4e3e1f1a2267834c2ab131734 --hash=sha256:eda2616eb2313cbb3eebbe51f19362eb434b18e3bb599466a1ffa76a033fb916 --hash=sha256:ee217c198f2e41f184f3869f3e485557296d505b5195c513b2bfe0062dc537f1 --hash=sha256:f02541ef64077f22bf4924f225c0fd1248c168f86e4b7abdedd87d6ebaceab0f --hash=sha256:f1b82c27e89fffc6da125d5eb0ca6e68017faf5efc078128cfaa42cf5cb38798 --hash=sha256:fba162b8872d30fea8c52b258a542c5dfd7b235fb5cb352240c8d63b414013eb --hash=sha256:fbbcb7b57dc9c794843e3d1258c0fbf0f48656d46ffe9e09b63bbd6e8cd5d0a2 --hash=sha256:fcb4621042ac4b7865c179bb972ed0da0218a076dc1820ffc48b1d74c1e37fe9" + } + }, + "bazel-orfs-pip_313_pyparsing": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pyparsing==3.2.0 --hash=sha256:93d9577b88da0bbea8cc8334ee8b918ed014968fd2ec383e868fb8afb1ccef84 --hash=sha256:cbf74e27246d595d9a74b186b810f6fbb86726dbf3b9532efb343f6d7294fe9c" + } + }, + "bazel-orfs-pip_313_python_dateutil": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "python-dateutil==2.9.0.post0 --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427" + } + }, + "bazel-orfs-pip_313_pytz": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pytz==2025.2 --hash=sha256:360b9e3dbb49a209c21ad61809c7fb453643e048b38924c765813546746e81c3 --hash=sha256:5ddf76296dd8c44c26eb8f4b6f35488f3ccbf6fbbd7adee0b7262d43f0ec2f00" + } + }, + "bazel-orfs-pip_313_pyyaml": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "pyyaml==6.0.2 --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4" + } + }, + "bazel-orfs-pip_313_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81" + } + }, + "bazel-orfs-pip_313_tzdata": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@bazel-orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "bazel-orfs-pip_313", + "requirement": "tzdata==2025.2 --hash=sha256:1a403fada01ff9221ca8044d701868fa132215d84beb92242d9acd2147f667a8 --hash=sha256:b60a638fcc0daffadf82fe0f57e53d06bdec2f36c4df66280ae79bce6bd6f2b9" + } + }, + "orfs-pip_313_contourpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "contourpy==1.3.1 --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 --hash=sha256:05e806338bfeaa006acbdeba0ad681a10be63b26e1b17317bfac3c5d98f36cda --hash=sha256:08d9d449a61cf53033612cb368f3a1b26cd7835d9b8cd326647efe43bca7568d --hash=sha256:0ffa84be8e0bd33410b17189f7164c3589c229ce5db85798076a3fa136d0e509 --hash=sha256:113231fe3825ebf6f15eaa8bc1f5b0ddc19d42b733345eae0934cb291beb88b6 --hash=sha256:14c102b0eab282427b662cb590f2e9340a9d91a1c297f48729431f2dcd16e14f --hash=sha256:174e758c66bbc1c8576992cec9599ce8b6672b741b5d336b5c74e35ac382b18e --hash=sha256:19c1555a6801c2f084c7ddc1c6e11f02eb6a6016ca1318dd5452ba3f613a1751 --hash=sha256:19d40d37c1c3a4961b4619dd9d77b12124a453cc3d02bb31a07d58ef684d3d86 --hash=sha256:1bf98051f1045b15c87868dbaea84f92408337d4f81d0e449ee41920ea121d3b --hash=sha256:20914c8c973f41456337652a6eeca26d2148aa96dd7ac323b74516988bea89fc --hash=sha256:287ccc248c9e0d0566934e7d606201abd74761b5703d804ff3df8935f523d546 --hash=sha256:2ba94a401342fc0f8b948e57d977557fbf4d515f03c67682dd5c6191cb2d16ec --hash=sha256:31c1b55c1f34f80557d3830d3dd93ba722ce7e33a0b472cba0ec3b6535684d8f --hash=sha256:36987a15e8ace5f58d4d5da9dca82d498c2bbb28dff6e5d04fbfcc35a9cb3a82 --hash=sha256:3a04ecd68acbd77fa2d39723ceca4c3197cb2969633836ced1bea14e219d077c --hash=sha256:3e8b974d8db2c5610fb4e76307e265de0edb655ae8169e8b21f41807ccbeec4b --hash=sha256:3ea9924d28fc5586bf0b42d15f590b10c224117e74409dd7a0be3b62b74a501c --hash=sha256:4318af1c925fb9a4fb190559ef3eec206845f63e80fb603d47f2d6d67683901c --hash=sha256:44a29502ca9c7b5ba389e620d44f2fbe792b1fb5734e8b931ad307071ec58c53 --hash=sha256:47734d7073fb4590b4a40122b35917cd77be5722d80683b249dac1de266aac80 --hash=sha256:4d76d5993a34ef3df5181ba3c92fabb93f1eaa5729504fb03423fcd9f3177242 --hash=sha256:4dbbc03a40f916a8420e420d63e96a1258d3d1b58cbdfd8d1f07b49fcbd38e85 --hash=sha256:500360b77259914f7805af7462e41f9cb7ca92ad38e9f94d6c8641b089338124 --hash=sha256:523a8ee12edfa36f6d2a49407f705a6ef4c5098de4f498619787e272de93f2d5 --hash=sha256:573abb30e0e05bf31ed067d2f82500ecfdaec15627a59d63ea2d95714790f5c2 --hash=sha256:5b75aa69cb4d6f137b36f7eb2ace9280cfb60c55dc5f61c731fdf6f037f958a3 --hash=sha256:61332c87493b00091423e747ea78200659dc09bdf7fd69edd5e98cef5d3e9a8d --hash=sha256:805617228ba7e2cbbfb6c503858e626ab528ac2a32a04a2fe88ffaf6b02c32bc --hash=sha256:841ad858cff65c2c04bf93875e384ccb82b654574a6d7f30453a04f04af71342 --hash=sha256:89785bb2a1980c1bd87f0cb1517a71cde374776a5f150936b82580ae6ead44a1 --hash=sha256:8eb96e79b9f3dcadbad2a3891672f81cdcab7f95b27f28f1c67d75f045b6b4f1 --hash=sha256:974d8145f8ca354498005b5b981165b74a195abfae9a8129df3e56771961d595 --hash=sha256:9ddeb796389dadcd884c7eb07bd14ef12408aaae358f0e2ae24114d797eede30 --hash=sha256:a045f341a77b77e1c5de31e74e966537bba9f3c4099b35bf4c2e3939dd54cdab --hash=sha256:a0cffcbede75c059f535725c1680dfb17b6ba8753f0c74b14e6a9c68c29d7ea3 --hash=sha256:a761d9ccfc5e2ecd1bf05534eda382aa14c3e4f9205ba5b1684ecfe400716ef2 --hash=sha256:a7895f46d47671fa7ceec40f31fae721da51ad34bdca0bee83e38870b1f47ffd --hash=sha256:a9fa36448e6a3a1a9a2ba23c02012c43ed88905ec80163f2ffe2421c7192a5d7 --hash=sha256:ab29962927945d89d9b293eabd0d59aea28d887d4f3be6c22deaefbb938a7277 --hash=sha256:abbb49fb7dac584e5abc6636b7b2a7227111c4f771005853e7d25176daaf8453 --hash=sha256:ac4578ac281983f63b400f7fe6c101bedc10651650eef012be1ccffcbacf3697 --hash=sha256:adce39d67c0edf383647a3a007de0a45fd1b08dedaa5318404f1a73059c2512b --hash=sha256:ade08d343436a94e633db932e7e8407fe7de8083967962b46bdfc1b0ced39454 --hash=sha256:b2bdca22a27e35f16794cf585832e542123296b4687f9fd96822db6bae17bfc9 --hash=sha256:b2f926efda994cdf3c8d3fdb40b9962f86edbc4457e739277b961eced3d0b4c1 --hash=sha256:b457d6430833cee8e4b8e9b6f07aa1c161e5e0d52e118dc102c8f9bd7dd060d6 --hash=sha256:c414fc1ed8ee1dbd5da626cf3710c6013d3d27456651d156711fa24f24bd1291 --hash=sha256:cb76c1a154b83991a3cbbf0dfeb26ec2833ad56f95540b442c73950af2013750 --hash=sha256:dfd97abd83335045a913e3bcc4a09c0ceadbe66580cf573fe961f4a825efa699 --hash=sha256:e914a8cb05ce5c809dd0fe350cfbb4e881bde5e2a38dc04e3afe1b3e58bd158e --hash=sha256:ece6df05e2c41bd46776fbc712e0996f7c94e0d0543af1656956d150c4ca7c81 --hash=sha256:efa874e87e4a647fd2e4f514d5e91c7d493697127beb95e77d2f7561f6905bd9 --hash=sha256:f611e628ef06670df83fce17805c344710ca5cde01edfdc72751311da8585375" + } + }, + "orfs-pip_313_cycler": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "cycler==0.12.1 --hash=sha256:85cef7cff222d8644161529808465972e51340599459b8ac3ccbac5a854e0d30 --hash=sha256:88bb128f02ba341da8ef447245a9e138fae777f6a23943da4540077d3601eb1c" + } + }, + "orfs-pip_313_fonttools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "fonttools==4.55.7 --hash=sha256:05568a66b090ed9d79aefdce2ceb180bb64fc856961deaedc29f5ad51355ce2c --hash=sha256:087ace2d06894ccdb03e6975d05da6bb9cec0c689b2a9983c059880e33a1464a --hash=sha256:09740feed51f9ed816aebf5d82071b7fecf693ac3a7e0fc8ea433f5dc3bd92f5 --hash=sha256:0ed25d7b5fa4ae6a805c2a9cc0e5307d45cbb3b8e155584fe932d0f3b6a997bf --hash=sha256:1101976c703ff4008a928fc3fef42caf06d035bfc4614230d7e797cbe356feb0 --hash=sha256:12e81d44f762156d28b5c93a6b65d98ed73678be45b22546de8ed29736c3cb96 --hash=sha256:1d4be8354c245c00aecfc90f5d3da8606226f0ac22e1cb0837b39139e4c2df85 --hash=sha256:23df0f1003abaf8a435543f59583fc247e7ae1b047ee2263510e0654a5f207e0 --hash=sha256:2dbc08e227fbeb716776905a7bd3c4fc62c8e37c8ef7d481acd10cb5fde12222 --hash=sha256:2e6dffe9cbcd163ef617fab1f81682e4d1629b7a5b9c5e598274dc2d03e88bcd --hash=sha256:3098355e7a7b5ac48d5dc29684a65271187b865b85675033958b57c40364ee34 --hash=sha256:30c3501328363b73a90acc8a722dd199c993f2c4369ea16886128d94e91897ec --hash=sha256:3304dfcf9ca204dd0ef691a287bd851ddd8e8250108658c0677c3fdfec853a20 --hash=sha256:371197de1283cc99f5f10eb91496520eb0e2d079312d014fd6cef9e802174c6a --hash=sha256:3976db357484bf4cb533dfd0d1a444b38ad06062458715ebf21e38c71aff325d --hash=sha256:418ece624fbc04e199f58398ffef3eaad645baba65434871b09eb7350a3a346b --hash=sha256:5ff0daf8b2e0612e5761fed2e4a2f54eff9d9ec0aeb4091c9f3666f9a118325e --hash=sha256:6899e3d97225a8218f525e9754da0376e1c62953a0d57a76c5abaada51e0d140 --hash=sha256:69ed0660750993150f7c4d966c0c1ffaa0385f23ccef85c2ff108062d80dd7ea --hash=sha256:6eb93cbba484a463b5ee83f7dd3211905f27a3871d20d90fb72de84c6c5056e3 --hash=sha256:775ed0700ee6f781436641f18a0c61b1846a8c1aecae6da6b395c4417e2cb567 --hash=sha256:77e5115a425d53be6e31cd0fe9210f62a488bccf81eb113ab5dd7f4fa88e4d81 --hash=sha256:7858dc6823296a053d85b831fa8428781c6c6f06fca44582bf7b6b2ff32a9089 --hash=sha256:7ff8e606f905048dc91a55a06d994b68065bf35752ae199df54a9bf30013dcaa --hash=sha256:82163d58b43eff6e2025a25c32905fdb9042a163cc1ff82dab393e7ffc77a7d5 --hash=sha256:833927d089e6585019f2c85e3f8f7d87733e3fe81cd704ebaca7afa27e2e7113 --hash=sha256:8ef5ee98fc320c158e4e459a5ee40d1ac3728d4ce11c3c8dfd854aa0aa5c042f --hash=sha256:9074a2848ea5b607377e16998dfcf90cf5eb614d0c388541b9782d5cc038e149 --hash=sha256:916e1d926823b4b3b3815c59fc79f4ed670696fdd5fd9a5e690a0503eef38f79 --hash=sha256:9ec71d0cc0242899f87e4c230ed0b22c7b8681f288fb80e3d81c2c54c5bd2c79 --hash=sha256:a3d19ea483b3cd8833e9e2ee8115f3d2044d55d3743d84f9c23b48b52d7516d8 --hash=sha256:a7831d16c95b60866772a15fdcc03772625c4bb6d858e0ad8ef3d6e48709b2ef --hash=sha256:b89da448e0073408d7b2c44935f9fdae4fdc93644899f99f6102ef883ecf083c --hash=sha256:bee4920ebeb540849bc3555d871e2a8487e39ce8263c281f74d5b6d44d2bf1df --hash=sha256:c135c91d47351b84893fb6fcbb8f178eba14f7cb195850264c0675c85e4238b6 --hash=sha256:c26445a7be689f8b70df7d5d2e2c85ec4407bdb769902a23dd45ac44f767575d --hash=sha256:c2680a3e6e2e2d104a7ea81fb89323e1a9122c23b03d6569d0768887d0d76e69 --hash=sha256:c665df9c9d99937a5bf807bace1c0c95bd13f55de8c82aaf9856b868dcbfe5d9 --hash=sha256:d4b1c5939c0521525f45522823508e6fad21175bca978583688ea3b3736e6625 --hash=sha256:d4bd27f0fa5120aaa39f76de5768959bc97300e0f59a3160d466b51436a38aea --hash=sha256:e10c7fb80cdfdc32244514cbea0906e9f53e3cc80d64d3389da09502fd999b55 --hash=sha256:e2cbafedb9462be7cf68c66b6ca1d8309842fe36b729f1b1969595f5d660e5c2 --hash=sha256:e4bde87985012adbd7559bc363d802fb335e92a07ff86a76cf02bebb0b8566d1 --hash=sha256:e696d6e2baf4cc57ded34bb87e5d3a9e4da9732f3d9e8e2c6db0746e57a6dc0b --hash=sha256:ee7aa8bb716318e3d835ef473978e22b7a39c0f1b3b08cc0b0ee1bba6f73bc1e --hash=sha256:f0899cd23967950e7b902ea75af06cfe5f59ac71eb38e98a774c9e596790e6aa --hash=sha256:f0c45eae32d090763820756b18322a70571dada3f1cbe003debc37a9c35bc260 --hash=sha256:f3b63648600dd0081bdd6856a86d014a7f1d2d11c3c974542f866478d832e103 --hash=sha256:f669910b64d27750398f6c56c651367d4954b05c86ff067af1c9949e109cf1e2 --hash=sha256:fd4ebc475d43f3de2b26e0cf551eff92c24e22d1aee03dc1b33adb52fc2e6cb2" + } + }, + "orfs-pip_313_kiwisolver": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "kiwisolver==1.4.8 --hash=sha256:01c3d31902c7db5fb6182832713d3b4122ad9317c2c5877d0539227d96bb2e50 --hash=sha256:034d2c891f76bd3edbdb3ea11140d8510dca675443da7304205a2eaa45d8334c --hash=sha256:085940635c62697391baafaaeabdf3dd7a6c3643577dde337f4d66eba021b2b8 --hash=sha256:08e77738ed7538f036cd1170cbed942ef749137b1311fa2bbe2a7fda2f6bf3cc --hash=sha256:111793b232842991be367ed828076b03d96202c19221b5ebab421ce8bcad016f --hash=sha256:11e1022b524bd48ae56c9b4f9296bce77e15a2e42a502cceba602f804b32bb79 --hash=sha256:151dffc4865e5fe6dafce5480fab84f950d14566c480c08a53c663a0020504b6 --hash=sha256:16523b40aab60426ffdebe33ac374457cf62863e330a90a0383639ce14bf44b2 --hash=sha256:1732e065704b47c9afca7ffa272f845300a4eb959276bf6970dc07265e73b605 --hash=sha256:1c8ceb754339793c24aee1c9fb2485b5b1f5bb1c2c214ff13368431e51fc9a09 --hash=sha256:23454ff084b07ac54ca8be535f4174170c1094a4cff78fbae4f73a4bcc0d4dab --hash=sha256:23d5f023bdc8c7e54eb65f03ca5d5bb25b601eac4d7f1a042888a1f45237987e --hash=sha256:257af1622860e51b1a9d0ce387bf5c2c4f36a90594cb9514f55b074bcc787cfc --hash=sha256:286b18e86682fd2217a48fc6be6b0f20c1d0ed10958d8dc53453ad58d7be0bf8 --hash=sha256:291331973c64bb9cce50bbe871fb2e675c4331dab4f31abe89f175ad7679a4d7 --hash=sha256:2f0121b07b356a22fb0414cec4666bbe36fd6d0d759db3d37228f496ed67c880 --hash=sha256:3452046c37c7692bd52b0e752b87954ef86ee2224e624ef7ce6cb21e8c41cc1b --hash=sha256:34d142fba9c464bc3bbfeff15c96eab0e7310343d6aefb62a79d51421fcc5f1b --hash=sha256:369b75d40abedc1da2c1f4de13f3482cb99e3237b38726710f4a793432b1c5ff --hash=sha256:36dbbfd34838500a31f52c9786990d00150860e46cd5041386f217101350f0d3 --hash=sha256:370fd2df41660ed4e26b8c9d6bbcad668fbe2560462cba151a721d49e5b6628c --hash=sha256:3a96c0e790ee875d65e340ab383700e2b4891677b7fcd30a699146f9384a2bb0 --hash=sha256:3b9b4d2892fefc886f30301cdd80debd8bb01ecdf165a449eb6e78f79f0fabd6 --hash=sha256:3cd3bc628b25f74aedc6d374d5babf0166a92ff1317f46267f12d2ed54bc1d30 --hash=sha256:3ddc373e0eef45b59197de815b1b28ef89ae3955e7722cc9710fb91cd77b7f47 --hash=sha256:4191ee8dfd0be1c3666ccbac178c5a05d5f8d689bbe3fc92f3c4abec817f8fe0 --hash=sha256:54a62808ac74b5e55a04a408cda6156f986cefbcf0ada13572696b507cc92fa1 --hash=sha256:577facaa411c10421314598b50413aa1ebcf5126f704f1e5d72d7e4e9f020d90 --hash=sha256:641f2ddf9358c80faa22e22eb4c9f54bd3f0e442e038728f500e3b978d00aa7d --hash=sha256:65ea09a5a3faadd59c2ce96dc7bf0f364986a315949dc6374f04396b0d60e09b --hash=sha256:68269e60ee4929893aad82666821aaacbd455284124817af45c11e50a4b42e3c --hash=sha256:69b5637c3f316cab1ec1c9a12b8c5f4750a4c4b71af9157645bf32830e39c03a --hash=sha256:7506488470f41169b86d8c9aeff587293f530a23a23a49d6bc64dab66bedc71e --hash=sha256:768cade2c2df13db52475bd28d3a3fac8c9eff04b0e9e2fda0f3760f20b3f7fc --hash=sha256:77e6f57a20b9bd4e1e2cedda4d0b986ebd0216236f0106e55c28aea3d3d69b16 --hash=sha256:782bb86f245ec18009890e7cb8d13a5ef54dcf2ebe18ed65f795e635a96a1c6a --hash=sha256:7a3ad337add5148cf51ce0b55642dc551c0b9d6248458a757f98796ca7348712 --hash=sha256:7cd2785b9391f2873ad46088ed7599a6a71e762e1ea33e87514b1a441ed1da1c --hash=sha256:7e9a60b50fe8b2ec6f448fe8d81b07e40141bfced7f896309df271a0b92f80f3 --hash=sha256:84a2f830d42707de1d191b9490ac186bf7997a9495d4e9072210a1296345f7dc --hash=sha256:856b269c4d28a5c0d5e6c1955ec36ebfd1651ac00e1ce0afa3e28da95293b561 --hash=sha256:858416b7fb777a53f0c59ca08190ce24e9abbd3cffa18886a5781b8e3e26f65d --hash=sha256:87b287251ad6488e95b4f0b4a79a6d04d3ea35fde6340eb38fbd1ca9cd35bbbc --hash=sha256:88c6f252f6816a73b1f8c904f7bbe02fd67c09a69f7cb8a0eecdbf5ce78e63db --hash=sha256:893f5525bb92d3d735878ec00f781b2de998333659507d29ea4466208df37bed --hash=sha256:89c107041f7b27844179ea9c85d6da275aa55ecf28413e87624d033cf1f6b751 --hash=sha256:918139571133f366e8362fa4a297aeba86c7816b7ecf0bc79168080e2bd79957 --hash=sha256:99cea8b9dd34ff80c521aef46a1dddb0dcc0283cf18bde6d756f1e6f31772165 --hash=sha256:a17b7c4f5b2c51bb68ed379defd608a03954a1845dfed7cc0117f1cc8a9b7fd2 --hash=sha256:a3c44cb68861de93f0c4a8175fbaa691f0aa22550c331fefef02b618a9dcb476 --hash=sha256:a4d3601908c560bdf880f07d94f31d734afd1bb71e96585cace0e38ef44c6d84 --hash=sha256:a5ce1e481a74b44dd5e92ff03ea0cb371ae7a0268318e202be06c8f04f4f1246 --hash=sha256:a66f60f8d0c87ab7f59b6fb80e642ebb29fec354a4dfad687ca4092ae69d04f4 --hash=sha256:b21dbe165081142b1232a240fc6383fd32cdd877ca6cc89eab93e5f5883e1c25 --hash=sha256:b47a465040146981dc9db8647981b8cb96366fbc8d452b031e4f8fdffec3f26d --hash=sha256:b5773efa2be9eb9fcf5415ea3ab70fc785d598729fd6057bea38d539ead28271 --hash=sha256:b83dc6769ddbc57613280118fb4ce3cd08899cc3369f7d0e0fab518a7cf37fdb --hash=sha256:bade438f86e21d91e0cf5dd7c0ed00cda0f77c8c1616bd83f9fc157fa6760d31 --hash=sha256:bcb1ebc3547619c3b58a39e2448af089ea2ef44b37988caf432447374941574e --hash=sha256:be4816dc51c8a471749d664161b434912eee82f2ea66bd7628bd14583a833e85 --hash=sha256:c07b29089b7ba090b6f1a669f1411f27221c3662b3a1b7010e67b59bb5a6f10b --hash=sha256:c2b9a96e0f326205af81a15718a9073328df1173a2619a68553decb7097fd5d7 --hash=sha256:c5020c83e8553f770cb3b5fc13faac40f17e0b205bd237aebd21d53d733adb03 --hash=sha256:c72941acb7b67138f35b879bbe85be0f6c6a70cab78fe3ef6db9c024d9223e5b --hash=sha256:c8bf637892dc6e6aad2bc6d4d69d08764166e5e3f69d469e55427b6ac001b19d --hash=sha256:cc978a80a0db3a66d25767b03688f1147a69e6237175c0f4ffffaaedf744055a --hash=sha256:ce2cf1e5688edcb727fdf7cd1bbd0b6416758996826a8be1d958f91880d0809d --hash=sha256:d47b28d1dfe0793d5e96bce90835e17edf9a499b53969b03c6c47ea5985844c3 --hash=sha256:d47cfb2650f0e103d4bf68b0b5804c68da97272c84bb12850d877a95c056bd67 --hash=sha256:d5536185fce131780ebd809f8e623bf4030ce1b161353166c49a3c74c287897f --hash=sha256:d561d2d8883e0819445cfe58d7ddd673e4015c3c57261d7bdcd3710d0d14005c --hash=sha256:d6af5e8815fd02997cb6ad9bbed0ee1e60014438ee1a5c2444c96f87b8843502 --hash=sha256:d6d6bd87df62c27d4185de7c511c6248040afae67028a8a22012b010bc7ad062 --hash=sha256:dace81d28c787956bfbfbbfd72fdcef014f37d9b48830829e488fdb32b49d954 --hash=sha256:e063ef9f89885a1d68dd8b2e18f5ead48653176d10a0e324e3b0030e3a69adeb --hash=sha256:e7a019419b7b510f0f7c9dceff8c5eae2392037eae483a7f9162625233802b0a --hash=sha256:eaa973f1e05131de5ff3569bbba7f5fd07ea0595d3870ed4a526d486fe57fa1b --hash=sha256:eb158fe28ca0c29f2260cca8c43005329ad58452c36f0edf298204de32a9a3ed --hash=sha256:ed33ca2002a779a2e20eeb06aea7721b6e47f2d4b8a8ece979d8ba9e2a167e34 --hash=sha256:fc2ace710ba7c1dfd1a3b42530b62b9ceed115f19a1656adefce7b1782a37794" + } + }, + "orfs-pip_313_matplotlib": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "matplotlib==3.10.0 --hash=sha256:01d2b19f13aeec2e759414d3bfe19ddfb16b13a1250add08d46d5ff6f9be83c6 --hash=sha256:12eaf48463b472c3c0f8dbacdbf906e573013df81a0ab82f0616ea4b11281908 --hash=sha256:2c5829a5a1dd5a71f0e31e6e8bb449bc0ee9dbfb05ad28fc0c6b55101b3a4be6 --hash=sha256:2fbbabc82fde51391c4da5006f965e36d86d95f6ee83fb594b279564a4c5d0d2 --hash=sha256:3547d153d70233a8496859097ef0312212e2689cdf8d7ed764441c77604095ae --hash=sha256:359f87baedb1f836ce307f0e850d12bb5f1936f70d035561f90d41d305fdacea --hash=sha256:3b427392354d10975c1d0f4ee18aa5844640b512d5311ef32efd4dd7db106ede --hash=sha256:4659665bc7c9b58f8c00317c3c2a299f7f258eeae5a5d56b4c64226fca2f7c59 --hash=sha256:4673ff67a36152c48ddeaf1135e74ce0d4bce1bbf836ae40ed39c29edf7e2765 --hash=sha256:503feb23bd8c8acc75541548a1d709c059b7184cde26314896e10a9f14df5f12 --hash=sha256:5439f4c5a3e2e8eab18e2f8c3ef929772fd5641876db71f08127eed95ab64683 --hash=sha256:5cdbaf909887373c3e094b0318d7ff230b2ad9dcb64da7ade654182872ab2593 --hash=sha256:5e6c6461e1fc63df30bf6f80f0b93f5b6784299f721bc28530477acd51bfc3d1 --hash=sha256:5fd41b0ec7ee45cd960a8e71aea7c946a28a0b8a4dcee47d2856b2af051f334c --hash=sha256:607b16c8a73943df110f99ee2e940b8a1cbf9714b65307c040d422558397dac5 --hash=sha256:7e8632baebb058555ac0cde75db885c61f1212e47723d63921879806b40bec6a --hash=sha256:81713dd0d103b379de4516b861d964b1d789a144103277769238c732229d7f03 --hash=sha256:845d96568ec873be63f25fa80e9e7fae4be854a66a7e2f0c8ccc99e94a8bd4ef --hash=sha256:95b710fea129c76d30be72c3b38f330269363fbc6e570a5dd43580487380b5ff --hash=sha256:96f2886f5c1e466f21cc41b70c5a0cd47bfa0015eb2d5793c88ebce658600e25 --hash=sha256:994c07b9d9fe8d25951e3202a68c17900679274dadfc1248738dcfa1bd40d7f3 --hash=sha256:9ade1003376731a971e398cc4ef38bb83ee8caf0aee46ac6daa4b0506db1fd06 --hash=sha256:9b0558bae37f154fffda54d779a592bc97ca8b4701f1c710055b609a3bac44c8 --hash=sha256:a2a43cbefe22d653ab34bb55d42384ed30f611bcbdea1f8d7f431011a2e1c62e --hash=sha256:a994f29e968ca002b50982b27168addfd65f0105610b6be7fa515ca4b5307c95 --hash=sha256:ad2e15300530c1a94c63cfa546e3b7864bd18ea2901317bae8bbf06a5ade6dcf --hash=sha256:ae80dc3a4add4665cf2faa90138384a7ffe2a4e37c58d83e115b54287c4f06ef --hash=sha256:b886d02a581b96704c9d1ffe55709e49b4d2d52709ccebc4be42db856e511278 --hash=sha256:c40ba2eb08b3f5de88152c2333c58cee7edcead0a2a0d60fcafa116b17117adc --hash=sha256:c55b20591ced744aa04e8c3e4b7543ea4d650b6c3c4b208c08a05b4010e8b442 --hash=sha256:c58a9622d5dbeb668f407f35f4e6bfac34bb9ecdcc81680c04d0258169747997 --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363" + } + }, + "orfs-pip_313_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "numpy==2.2.2 --hash=sha256:02935e2c3c0c6cbe9c7955a8efa8908dd4221d7755644c59d1bba28b94fd334f --hash=sha256:0349b025e15ea9d05c3d63f9657707a4e1d471128a3b1d876c095f328f8ff7f0 --hash=sha256:09d6a2032faf25e8d0cadde7fd6145118ac55d2740132c1d845f98721b5ebcfd --hash=sha256:0bc61b307655d1a7f9f4b043628b9f2b721e80839914ede634e3d485913e1fb2 --hash=sha256:0eec19f8af947a61e968d5429f0bd92fec46d92b0008d0a6685b40d6adf8a4f4 --hash=sha256:106397dbbb1896f99e044efc90360d098b3335060375c26aa89c0d8a97c5f648 --hash=sha256:128c41c085cab8a85dc29e66ed88c05613dccf6bc28b3866cd16050a2f5448be --hash=sha256:149d1113ac15005652e8d0d3f6fd599360e1a708a4f98e43c9c77834a28238cb --hash=sha256:159ff6ee4c4a36a23fe01b7c3d07bd8c14cc433d9720f977fcd52c13c0098160 --hash=sha256:22ea3bb552ade325530e72a0c557cdf2dea8914d3a5e1fecf58fa5dbcc6f43cd --hash=sha256:23ae9f0c2d889b7b2d88a3791f6c09e2ef827c2446f1c4a3e3e76328ee4afd9a --hash=sha256:250c16b277e3b809ac20d1f590716597481061b514223c7badb7a0f9993c7f84 --hash=sha256:2ec6c689c61df613b783aeb21f945c4cbe6c51c28cb70aae8430577ab39f163e --hash=sha256:2ffbb1acd69fdf8e89dd60ef6182ca90a743620957afb7066385a7bbe88dc748 --hash=sha256:3074634ea4d6df66be04f6728ee1d173cfded75d002c75fac79503a880bf3825 --hash=sha256:356ca982c188acbfa6af0d694284d8cf20e95b1c3d0aefa8929376fea9146f60 --hash=sha256:3fbe72d347fbc59f94124125e73fc4976a06927ebc503ec5afbfb35f193cd957 --hash=sha256:40c7ff5da22cd391944a28c6a9c638a5eef77fcf71d6e3a79e1d9d9e82752715 --hash=sha256:41184c416143defa34cc8eb9d070b0a5ba4f13a0fa96a709e20584638254b317 --hash=sha256:451e854cfae0febe723077bd0cf0a4302a5d84ff25f0bfece8f29206c7bed02e --hash=sha256:4525b88c11906d5ab1b0ec1f290996c0020dd318af8b49acaa46f198b1ffc283 --hash=sha256:463247edcee4a5537841d5350bc87fe8e92d7dd0e8c71c995d2c6eecb8208278 --hash=sha256:4dbd80e453bd34bd003b16bd802fac70ad76bd463f81f0c518d1245b1c55e3d9 --hash=sha256:57b4012e04cc12b78590a334907e01b3a85efb2107df2b8733ff1ed05fce71de --hash=sha256:5a8c863ceacae696aff37d1fd636121f1a512117652e5dfb86031c8d84836369 --hash=sha256:5acea83b801e98541619af398cc0109ff48016955cc0818f478ee9ef1c5c3dcb --hash=sha256:642199e98af1bd2b6aeb8ecf726972d238c9877b0f6e8221ee5ab945ec8a2189 --hash=sha256:64bd6e1762cd7f0986a740fee4dff927b9ec2c5e4d9a28d056eb17d332158014 --hash=sha256:6d9fc9d812c81e6168b6d405bf00b8d6739a7f72ef22a9214c4241e0dc70b323 --hash=sha256:7079129b64cb78bdc8d611d1fd7e8002c0a2565da6a47c4df8062349fee90e3e --hash=sha256:7dca87ca328f5ea7dafc907c5ec100d187911f94825f8700caac0b3f4c384b49 --hash=sha256:860fd59990c37c3ef913c3ae390b3929d005243acca1a86facb0773e2d8d9e50 --hash=sha256:8e6da5cffbbe571f93588f562ed130ea63ee206d12851b60819512dd3e1ba50d --hash=sha256:8ec0636d3f7d68520afc6ac2dc4b8341ddb725039de042faf0e311599f54eb37 --hash=sha256:9491100aba630910489c1d0158034e1c9a6546f0b1340f716d522dc103788e39 --hash=sha256:97b974d3ba0fb4612b77ed35d7627490e8e3dff56ab41454d9e8b23448940576 --hash=sha256:995f9e8181723852ca458e22de5d9b7d3ba4da3f11cc1cb113f093b271d7965a --hash=sha256:9dd47ff0cb2a656ad69c38da850df3454da88ee9a6fde0ba79acceee0e79daba --hash=sha256:9fad446ad0bc886855ddf5909cbf8cb5d0faa637aaa6277fb4b19ade134ab3c7 --hash=sha256:a972cec723e0563aa0823ee2ab1df0cb196ed0778f173b381c871a03719d4826 --hash=sha256:ac9bea18d6d58a995fac1b2cb4488e17eceeac413af014b1dd26170b766d8467 --hash=sha256:b0531f0b0e07643eb089df4c509d30d72c9ef40defa53e41363eca8a8cc61495 --hash=sha256:b208cfd4f5fe34e1535c08983a1a6803fdbc7a1e86cf13dd0c61de0b51a0aadc --hash=sha256:b3482cb7b3325faa5f6bc179649406058253d91ceda359c104dac0ad320e1391 --hash=sha256:b6fb9c32a91ec32a689ec6410def76443e3c750e7cfc3fb2206b985ffb2b85f0 --hash=sha256:b78ea78450fd96a498f50ee096f69c75379af5138f7881a51355ab0e11286c97 --hash=sha256:bd249bc894af67cbd8bad2c22e7cbcd46cf87ddfca1f1289d1e7e54868cc785c --hash=sha256:c7d1fd447e33ee20c1f33f2c8e6634211124a9aabde3c617687d8b739aa69eac --hash=sha256:d0bbe7dd86dca64854f4b6ce2ea5c60b51e36dfd597300057cf473d3615f2369 --hash=sha256:d6d6a0910c3b4368d89dde073e630882cdb266755565155bc33520283b2d9df8 --hash=sha256:da1eeb460ecce8d5b8608826595c777728cdf28ce7b5a5a8c8ac8d949beadcf2 --hash=sha256:e0c8854b09bc4de7b041148d8550d3bd712b5c21ff6a8ed308085f190235d7ff --hash=sha256:e0d4142eb40ca6f94539e4db929410f2a46052a0fe7a2c1c59f6179c39938d2a --hash=sha256:e9e82dcb3f2ebbc8cb5ce1102d5f1c5ed236bf8a11730fb45ba82e2841ec21df --hash=sha256:ed6906f61834d687738d25988ae117683705636936cc605be0bb208b23df4d8f" + } + }, + "orfs-pip_313_packaging": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "packaging==24.2 --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f" + } + }, + "orfs-pip_313_pillow": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "pillow==11.1.0 --hash=sha256:015c6e863faa4779251436db398ae75051469f7c903b043a48f078e437656f83 --hash=sha256:0a2f91f8a8b367e7a57c6e91cd25af510168091fb89ec5146003e424e1558a96 --hash=sha256:11633d58b6ee5733bde153a8dafd25e505ea3d32e261accd388827ee987baf65 --hash=sha256:2062ffb1d36544d42fcaa277b069c88b01bb7298f4efa06731a7fd6cc290b81a --hash=sha256:31eba6bbdd27dde97b0174ddf0297d7a9c3a507a8a1480e1e60ef914fe23d352 --hash=sha256:3362c6ca227e65c54bf71a5f88b3d4565ff1bcbc63ae72c34b07bbb1cc59a43f --hash=sha256:368da70808b36d73b4b390a8ffac11069f8a5c85f29eff1f1b01bcf3ef5b2a20 --hash=sha256:36ba10b9cb413e7c7dfa3e189aba252deee0602c86c309799da5a74009ac7a1c --hash=sha256:3764d53e09cdedd91bee65c2527815d315c6b90d7b8b79759cc48d7bf5d4f114 --hash=sha256:3a5fe20a7b66e8135d7fd617b13272626a28278d0e578c98720d9ba4b2439d49 --hash=sha256:3cdcdb0b896e981678eee140d882b70092dac83ac1cdf6b3a60e2216a73f2b91 --hash=sha256:4637b88343166249fe8aa94e7c4a62a180c4b3898283bb5d3d2fd5fe10d8e4e0 --hash=sha256:4db853948ce4e718f2fc775b75c37ba2efb6aaea41a1a5fc57f0af59eee774b2 --hash=sha256:4dd43a78897793f60766563969442020e90eb7847463eca901e41ba186a7d4a5 --hash=sha256:54251ef02a2309b5eec99d151ebf5c9904b77976c8abdcbce7891ed22df53884 --hash=sha256:54ce1c9a16a9561b6d6d8cb30089ab1e5eb66918cb47d457bd996ef34182922e --hash=sha256:593c5fd6be85da83656b93ffcccc2312d2d149d251e98588b14fbc288fd8909c --hash=sha256:5bb94705aea800051a743aa4874bb1397d4695fb0583ba5e425ee0328757f196 --hash=sha256:67cd427c68926108778a9005f2a04adbd5e67c442ed21d95389fe1d595458756 --hash=sha256:70ca5ef3b3b1c4a0812b5c63c57c23b63e53bc38e758b37a951e5bc466449861 --hash=sha256:73ddde795ee9b06257dac5ad42fcb07f3b9b813f8c1f7f870f402f4dc54b5269 --hash=sha256:758e9d4ef15d3560214cddbc97b8ef3ef86ce04d62ddac17ad39ba87e89bd3b1 --hash=sha256:7d33d2fae0e8b170b6a6c57400e077412240f6f5bb2a342cf1ee512a787942bb --hash=sha256:7fdadc077553621911f27ce206ffcbec7d3f8d7b50e0da39f10997e8e2bb7f6a --hash=sha256:8000376f139d4d38d6851eb149b321a52bb8893a88dae8ee7d95840431977081 --hash=sha256:837060a8599b8f5d402e97197d4924f05a2e0d68756998345c829c33186217b1 --hash=sha256:89dbdb3e6e9594d512780a5a1c42801879628b38e3efc7038094430844e271d8 --hash=sha256:8c730dc3a83e5ac137fbc92dfcfe1511ce3b2b5d7578315b63dbbb76f7f51d90 --hash=sha256:8e275ee4cb11c262bd108ab2081f750db2a1c0b8c12c1897f27b160c8bd57bbc --hash=sha256:9044b5e4f7083f209c4e35aa5dd54b1dd5b112b108648f5c902ad586d4f945c5 --hash=sha256:93a18841d09bcdd774dcdc308e4537e1f867b3dec059c131fde0327899734aa1 --hash=sha256:9409c080586d1f683df3f184f20e36fb647f2e0bc3988094d4fd8c9f4eb1b3b3 --hash=sha256:96f82000e12f23e4f29346e42702b6ed9a2f2fea34a740dd5ffffcc8c539eb35 --hash=sha256:9aa9aeddeed452b2f616ff5507459e7bab436916ccb10961c4a382cd3e03f47f --hash=sha256:9ee85f0696a17dd28fbcfceb59f9510aa71934b483d1f5601d1030c3c8304f3c --hash=sha256:a07dba04c5e22824816b2615ad7a7484432d7f540e6fa86af60d2de57b0fcee2 --hash=sha256:a3cd561ded2cf2bbae44d4605837221b987c216cff94f49dfeed63488bb228d2 --hash=sha256:a697cd8ba0383bba3d2d3ada02b34ed268cb548b369943cd349007730c92bddf --hash=sha256:a76da0a31da6fcae4210aa94fd779c65c75786bc9af06289cd1c184451ef7a65 --hash=sha256:a85b653980faad27e88b141348707ceeef8a1186f75ecc600c395dcac19f385b --hash=sha256:a8d65b38173085f24bc07f8b6c505cbb7418009fa1a1fcb111b1f4961814a442 --hash=sha256:aa8dd43daa836b9a8128dbe7d923423e5ad86f50a7a14dc688194b7be5c0dea2 --hash=sha256:ab8a209b8485d3db694fa97a896d96dd6533d63c22829043fd9de627060beade --hash=sha256:abc56501c3fd148d60659aae0af6ddc149660469082859fa7b066a298bde9482 --hash=sha256:ad5db5781c774ab9a9b2c4302bbf0c1014960a0a7be63278d13ae6fdf88126fe --hash=sha256:ae98e14432d458fc3de11a77ccb3ae65ddce70f730e7c76140653048c71bfcbc --hash=sha256:b20be51b37a75cc54c2c55def3fa2c65bb94ba859dde241cd0a4fd302de5ae0a --hash=sha256:b523466b1a31d0dcef7c5be1f20b942919b62fd6e9a9be199d035509cbefc0ec --hash=sha256:b5d658fbd9f0d6eea113aea286b21d3cd4d3fd978157cbf2447a6035916506d3 --hash=sha256:b6123aa4a59d75f06e9dd3dac5bf8bc9aa383121bb3dd9a7a612e05eabc9961a --hash=sha256:bd165131fd51697e22421d0e467997ad31621b74bfc0b75956608cb2906dda07 --hash=sha256:bf902d7413c82a1bfa08b06a070876132a5ae6b2388e2712aab3a7cbc02205c6 --hash=sha256:c12fc111ef090845de2bb15009372175d76ac99969bdf31e2ce9b42e4b8cd88f --hash=sha256:c1eec9d950b6fe688edee07138993e54ee4ae634c51443cfb7c1e7613322718e --hash=sha256:c640e5a06869c75994624551f45e5506e4256562ead981cce820d5ab39ae2192 --hash=sha256:cc1331b6d5a6e144aeb5e626f4375f5b7ae9934ba620c0ac6b3e43d5e683a0f0 --hash=sha256:cfd5cd998c2e36a862d0e27b2df63237e67273f2fc78f47445b14e73a810e7e6 --hash=sha256:d3d8da4a631471dfaf94c10c85f5277b1f8e42ac42bade1ac67da4b4a7359b73 --hash=sha256:d44ff19eea13ae4acdaaab0179fa68c0c6f2f45d66a4d8ec1eda7d6cecbcc15f --hash=sha256:dd0052e9db3474df30433f83a71b9b23bd9e4ef1de13d92df21a52c0303b8ab6 --hash=sha256:dd0e081319328928531df7a0e63621caf67652c8464303fd102141b785ef9547 --hash=sha256:dda60aa465b861324e65a78c9f5cf0f4bc713e4309f83bc387be158b077963d9 --hash=sha256:e06695e0326d05b06833b40b7ef477e475d0b1ba3a6d27da1bb48c23209bf457 --hash=sha256:e1abe69aca89514737465752b4bcaf8016de61b3be1397a8fc260ba33321b3a8 --hash=sha256:e267b0ed063341f3e60acd25c05200df4193e15a4a5807075cd71225a2386e26 --hash=sha256:e5449ca63da169a2e6068dd0e2fcc8d91f9558aba89ff6d02121ca8ab11e79e5 --hash=sha256:e63e4e5081de46517099dc30abe418122f54531a6ae2ebc8680bcd7096860eab --hash=sha256:f189805c8be5ca5add39e6f899e6ce2ed824e65fb45f3c28cb2841911da19070 --hash=sha256:f7955ecf5609dee9442cbface754f2c6e541d9e6eda87fad7f7a989b0bdb9d71 --hash=sha256:f86d3a7a9af5d826744fabf4afd15b9dfef44fe69a98541f666f66fbb8d3fef9 --hash=sha256:fbd43429d0d7ed6533b25fc993861b8fd512c42d04514a0dd6337fb3ccf22761" + } + }, + "orfs-pip_313_pyparsing": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "pyparsing==3.2.1 --hash=sha256:506ff4f4386c4cec0590ec19e6302d3aedb992fdc02c761e90416f158dacf8e1 --hash=sha256:61980854fd66de3a90028d679a954d5f2623e83144b5afe5ee86f43d762e5f0a" + } + }, + "orfs-pip_313_python_dateutil": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "python-dateutil==2.9.0.post0 --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427" + } + }, + "orfs-pip_313_pyyaml": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "pyyaml==6.0.2 --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4" + } + }, + "orfs-pip_313_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@orfs-pip//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_13_host//:python", + "repo": "orfs-pip_313", + "requirement": "six==1.17.0 --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81" + } + }, + "pip_deps_310_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_10_host//:python", + "repo": "pip_deps_310", + "requirement": "numpy<=1.26.1" + } + }, + "pip_deps_310_setuptools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_10_host//:python", + "repo": "pip_deps_310", + "requirement": "setuptools<=70.3.0" + } + }, + "pip_deps_311_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "pip_deps_311", + "requirement": "numpy<=1.26.1" + } + }, + "pip_deps_311_setuptools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "pip_deps_311", + "requirement": "setuptools<=70.3.0" + } + }, + "pip_deps_312_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python", + "repo": "pip_deps_312", + "requirement": "numpy<=1.26.1" + } + }, + "pip_deps_312_setuptools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python", + "repo": "pip_deps_312", + "requirement": "setuptools<=70.3.0" + } + }, + "pip_deps_38_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_8_host//:python", + "repo": "pip_deps_38", + "requirement": "numpy<=1.26.1" + } + }, + "pip_deps_38_setuptools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_8_host//:python", + "repo": "pip_deps_38", + "requirement": "setuptools<=70.3.0" + } + }, + "pip_deps_39_numpy": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_9_host//:python", + "repo": "pip_deps_39", + "requirement": "numpy<=1.26.1" + } + }, + "pip_deps_39_setuptools": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@pip_deps//{name}:{target}", + "python_interpreter_target": "@@rules_python~~python~python_3_9_host//:python", + "repo": "pip_deps_39", + "requirement": "setuptools<=70.3.0" + } + }, + "rules_fuzzing_py_deps_310_absl_py": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_10_host//:python", + "repo": "rules_fuzzing_py_deps_310", + "requirement": "absl-py==2.0.0 --hash=sha256:9a28abb62774ae4e8edbe2dd4c49ffcd45a6a848952a5eccc6a49f3f0fc1e2f3" + } + }, + "rules_fuzzing_py_deps_310_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_10_host//:python", + "repo": "rules_fuzzing_py_deps_310", + "requirement": "six==1.16.0 --hash=sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254" + } + }, + "rules_fuzzing_py_deps_311_absl_py": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_fuzzing_py_deps_311", + "requirement": "absl-py==2.0.0 --hash=sha256:9a28abb62774ae4e8edbe2dd4c49ffcd45a6a848952a5eccc6a49f3f0fc1e2f3" + } + }, + "rules_fuzzing_py_deps_311_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_fuzzing_py_deps_311", + "requirement": "six==1.16.0 --hash=sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254" + } + }, + "rules_fuzzing_py_deps_312_absl_py": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python", + "repo": "rules_fuzzing_py_deps_312", + "requirement": "absl-py==2.0.0 --hash=sha256:9a28abb62774ae4e8edbe2dd4c49ffcd45a6a848952a5eccc6a49f3f0fc1e2f3" + } + }, + "rules_fuzzing_py_deps_312_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_12_host//:python", + "repo": "rules_fuzzing_py_deps_312", + "requirement": "six==1.16.0 --hash=sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254" + } + }, + "rules_fuzzing_py_deps_38_absl_py": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_8_host//:python", + "repo": "rules_fuzzing_py_deps_38", + "requirement": "absl-py==2.0.0 --hash=sha256:9a28abb62774ae4e8edbe2dd4c49ffcd45a6a848952a5eccc6a49f3f0fc1e2f3" + } + }, + "rules_fuzzing_py_deps_38_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_8_host//:python", + "repo": "rules_fuzzing_py_deps_38", + "requirement": "six==1.16.0 --hash=sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254" + } + }, + "rules_fuzzing_py_deps_39_absl_py": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_9_host//:python", + "repo": "rules_fuzzing_py_deps_39", + "requirement": "absl-py==2.0.0 --hash=sha256:9a28abb62774ae4e8edbe2dd4c49ffcd45a6a848952a5eccc6a49f3f0fc1e2f3" + } + }, + "rules_fuzzing_py_deps_39_six": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_fuzzing_py_deps//{name}:{target}", + "extra_pip_args": [ + "--require-hashes" + ], + "python_interpreter_target": "@@rules_python~~python~python_3_9_host//:python", + "repo": "rules_fuzzing_py_deps_39", + "requirement": "six==1.16.0 --hash=sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254" + } + }, + "rules_python_publish_deps_311_backports_tarfile_py3_none_any_77e284d7": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "backports.tarfile-1.2.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "backports-tarfile==1.2.0", + "sha256": "77e284d754527b01fb1e6fa8a1afe577858ebe4e9dad8919e34c862cb399bc34", + "urls": [ + "https://files.pythonhosted.org/packages/b9/fa/123043af240e49752f1c4bd24da5053b6bd00cad78c2be53c0d1e8b975bc/backports.tarfile-1.2.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_backports_tarfile_sdist_d75e02c2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "backports_tarfile-1.2.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "backports-tarfile==1.2.0", + "sha256": "d75e02c268746e1b8144c278978b6e98e85de6ad16f8e4b0844a154557eca991", + "urls": [ + "https://files.pythonhosted.org/packages/86/72/cd9b395f25e290e633655a100af28cb253e4393396264a98bd5f5951d50f/backports_tarfile-1.2.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_certifi_py3_none_any_922820b5": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "certifi-2024.8.30-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "certifi==2024.8.30", + "sha256": "922820b53db7a7257ffbda3f597266d435245903d80737e34f8a45ff3e3230d8", + "urls": [ + "https://files.pythonhosted.org/packages/12/90/3c9ff0512038035f59d279fddeb79f5f1eccd8859f06d6163c58798b9487/certifi-2024.8.30-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_certifi_sdist_bec941d2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "certifi-2024.8.30.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "certifi==2024.8.30", + "sha256": "bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9", + "urls": [ + "https://files.pythonhosted.org/packages/b0/ee/9b19140fe824b367c04c5e1b369942dd754c4c5462d5674002f75c4dedc1/certifi-2024.8.30.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_aarch64_a1ed2dd2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "a1ed2dd2972641495a3ec98445e09766f077aee98a1c896dcb4ad0d303628e41", + "urls": [ + "https://files.pythonhosted.org/packages/2e/ea/70ce63780f096e16ce8588efe039d3c4f91deb1dc01e9c73a287939c79a6/cffi-1.17.1-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_ppc64le_46bf4316": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "46bf43160c1a35f7ec506d254e5c890f3c03648a4dbac12d624e4490a7046cd1", + "urls": [ + "https://files.pythonhosted.org/packages/1c/a0/a4fa9f4f781bda074c3ddd57a572b060fa0df7655d2a4247bbe277200146/cffi-1.17.1-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_s390x_a24ed04c": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "a24ed04c8ffd54b0729c07cee15a81d964e6fee0e3d4d342a27b020d22959dc6", + "urls": [ + "https://files.pythonhosted.org/packages/62/12/ce8710b5b8affbcdd5c6e367217c242524ad17a02fe5beec3ee339f69f85/cffi-1.17.1-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_x86_64_610faea7": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "610faea79c43e44c71e1ec53a554553fa22321b65fae24889706c0a84d4ad86d", + "urls": [ + "https://files.pythonhosted.org/packages/ff/6b/d45873c5e0242196f042d555526f92aa9e0c32355a1be1ff8c27f077fd37/cffi-1.17.1-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_musllinux_1_1_aarch64_a9b15d49": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-musllinux_1_1_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "a9b15d491f3ad5d692e11f6b71f7857e7835eb677955c00cc0aefcd0669adaf6", + "urls": [ + "https://files.pythonhosted.org/packages/1a/52/d9a0e523a572fbccf2955f5abe883cfa8bcc570d7faeee06336fbd50c9fc/cffi-1.17.1-cp311-cp311-musllinux_1_1_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_cp311_cp311_musllinux_1_1_x86_64_fc48c783": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cffi-1.17.1-cp311-cp311-musllinux_1_1_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "fc48c783f9c87e60831201f2cce7f3b2e4846bf4d8728eabe54d60700b318a0b", + "urls": [ + "https://files.pythonhosted.org/packages/f8/4a/34599cac7dfcd888ff54e801afe06a19c17787dfd94495ab0c8d35fe99fb/cffi-1.17.1-cp311-cp311-musllinux_1_1_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_cffi_sdist_1c39c601": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "cffi-1.17.1.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cffi==1.17.1", + "sha256": "1c39c6016c32bc48dd54561950ebd6836e1670f2ae46128f67cf49e789c52824", + "urls": [ + "https://files.pythonhosted.org/packages/fc/97/c783634659c2920c3fc70419e3af40972dbaf758daa229a7d6ea6135c90d/cffi-1.17.1.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_10_9_universal2_0d99dd8f": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_universal2.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "0d99dd8ff461990f12d6e42c7347fd9ab2532fb70e9621ba520f9e8637161d7c", + "urls": [ + "https://files.pythonhosted.org/packages/9c/61/73589dcc7a719582bf56aae309b6103d2762b526bffe189d635a7fcfd998/charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_universal2.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_10_9_x86_64_c57516e5": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "c57516e58fd17d03ebe67e181a4e4e2ccab1168f8c2976c6a334d4f819fe5944", + "urls": [ + "https://files.pythonhosted.org/packages/77/d5/8c982d58144de49f59571f940e329ad6e8615e1e82ef84584c5eeb5e1d72/charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_11_0_arm64_6dba5d19": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-macosx_11_0_arm64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "6dba5d19c4dfab08e58d5b36304b3f92f3bd5d42c1a3fa37b5ba5cdf6dfcbcee", + "urls": [ + "https://files.pythonhosted.org/packages/bf/19/411a64f01ee971bed3231111b69eb56f9331a769072de479eae7de52296d/charset_normalizer-3.4.0-cp311-cp311-macosx_11_0_arm64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_aarch64_bf4475b8": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "bf4475b82be41b07cc5e5ff94810e6a01f276e37c2d55571e3fe175e467a1a1c", + "urls": [ + "https://files.pythonhosted.org/packages/4c/92/97509850f0d00e9f14a46bc751daabd0ad7765cff29cdfb66c68b6dad57f/charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_ppc64le_ce031db0": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "ce031db0408e487fd2775d745ce30a7cd2923667cf3b69d48d219f1d8f5ddeb6", + "urls": [ + "https://files.pythonhosted.org/packages/e2/29/d227805bff72ed6d6cb1ce08eec707f7cfbd9868044893617eb331f16295/charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_s390x_8ff4e7cd": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "8ff4e7cdfdb1ab5698e675ca622e72d58a6fa2a8aa58195de0c0061288e6e3ea", + "urls": [ + "https://files.pythonhosted.org/packages/13/bc/87c2c9f2c144bedfa62f894c3007cd4530ba4b5351acb10dc786428a50f0/charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_x86_64_3710a975": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "3710a9751938947e6327ea9f3ea6332a09bf0ba0c09cae9cb1f250bd1f1549bc", + "urls": [ + "https://files.pythonhosted.org/packages/eb/5b/6f10bad0f6461fa272bfbbdf5d0023b5fb9bc6217c92bf068fa5a99820f5/charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_aarch64_47334db7": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "47334db71978b23ebcf3c0f9f5ee98b8d65992b65c9c4f2d34c2eaf5bcaf0594", + "urls": [ + "https://files.pythonhosted.org/packages/d7/a1/493919799446464ed0299c8eef3c3fad0daf1c3cd48bff9263c731b0d9e2/charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_ppc64le_f1a2f519": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_ppc64le.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "f1a2f519ae173b5b6a2c9d5fa3116ce16e48b3462c8b96dfdded11055e3d6365", + "urls": [ + "https://files.pythonhosted.org/packages/75/d2/0ab54463d3410709c09266dfb416d032a08f97fd7d60e94b8c6ef54ae14b/charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_ppc64le.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_s390x_63bc5c4a": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_s390x.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "63bc5c4ae26e4bc6be6469943b8253c0fd4e4186c43ad46e713ea61a0ba49129", + "urls": [ + "https://files.pythonhosted.org/packages/8d/c9/27e41d481557be53d51e60750b85aa40eaf52b841946b3cdeff363105737/charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_s390x.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_x86_64_bcb4f8ea": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "bcb4f8ea87d03bc51ad04add8ceaf9b0f085ac045ab4d74e73bbc2dc033f0236", + "urls": [ + "https://files.pythonhosted.org/packages/ee/44/4f62042ca8cdc0cabf87c0fc00ae27cd8b53ab68be3605ba6d071f742ad3/charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_cp311_cp311_win_amd64_cee4373f": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-cp311-cp311-win_amd64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "cee4373f4d3ad28f1ab6290684d8e2ebdb9e7a1b74fdc39e4c211995f77bec27", + "urls": [ + "https://files.pythonhosted.org/packages/0b/6e/b13bd47fa9023b3699e94abf565b5a2f0b0be6e9ddac9812182596ee62e4/charset_normalizer-3.4.0-cp311-cp311-win_amd64.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_py3_none_any_fe9f97fe": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "charset_normalizer-3.4.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "fe9f97feb71aa9896b81973a7bbada8c49501dc73e58a10fcef6663af95e5079", + "urls": [ + "https://files.pythonhosted.org/packages/bf/9b/08c0432272d77b04803958a4598a51e2a4b51c06640af8b8f0f908c18bf2/charset_normalizer-3.4.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_charset_normalizer_sdist_223217c3": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "charset_normalizer-3.4.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "charset-normalizer==3.4.0", + "sha256": "223217c3d4f82c3ac5e29032b3f1c2eb0fb591b72161f86d93f5719079dae93e", + "urls": [ + "https://files.pythonhosted.org/packages/f2/4f/e1808dc01273379acc506d18f1504eb2d299bd4131743b9fc54d7be4df1e/charset_normalizer-3.4.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_17_aarch64_846da004": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "846da004a5804145a5f441b8530b4bf35afbf7da70f82409f151695b127213d5", + "urls": [ + "https://files.pythonhosted.org/packages/2f/78/55356eb9075d0be6e81b59f45c7b48df87f76a20e73893872170471f3ee8/cryptography-43.0.3-cp39-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_17_x86_64_0f996e72": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "0f996e7268af62598f2fc1204afa98a3b5712313a55c4c9d434aef49cadc91d4", + "urls": [ + "https://files.pythonhosted.org/packages/2a/2c/488776a3dc843f95f86d2f957ca0fc3407d0242b50bede7fad1e339be03f/cryptography-43.0.3-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_28_aarch64_f7b178f1": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-manylinux_2_28_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "f7b178f11ed3664fd0e995a47ed2b5ff0a12d893e41dd0494f406d1cf555cab7", + "urls": [ + "https://files.pythonhosted.org/packages/7c/04/2345ca92f7a22f601a9c62961741ef7dd0127c39f7310dffa0041c80f16f/cryptography-43.0.3-cp39-abi3-manylinux_2_28_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_28_x86_64_c2e6fc39": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-manylinux_2_28_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "c2e6fc39c4ab499049df3bdf567f768a723a5e8464816e8f009f121a5a9f4405", + "urls": [ + "https://files.pythonhosted.org/packages/ac/25/e715fa0bc24ac2114ed69da33adf451a38abb6f3f24ec207908112e9ba53/cryptography-43.0.3-cp39-abi3-manylinux_2_28_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_musllinux_1_2_aarch64_e1be4655": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-musllinux_1_2_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "e1be4655c7ef6e1bbe6b5d0403526601323420bcf414598955968c9ef3eb7d16", + "urls": [ + "https://files.pythonhosted.org/packages/21/ce/b9c9ff56c7164d8e2edfb6c9305045fbc0df4508ccfdb13ee66eb8c95b0e/cryptography-43.0.3-cp39-abi3-musllinux_1_2_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_cp39_abi3_musllinux_1_2_x86_64_df6b6c6d": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "cryptography-43.0.3-cp39-abi3-musllinux_1_2_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "df6b6c6d742395dd77a23ea3728ab62f98379eff8fb61be2744d4679ab678f73", + "urls": [ + "https://files.pythonhosted.org/packages/2a/33/b3682992ab2e9476b9c81fff22f02c8b0a1e6e1d49ee1750a67d85fd7ed2/cryptography-43.0.3-cp39-abi3-musllinux_1_2_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_cryptography_sdist_315b9001": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "cryptography-43.0.3.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "cryptography==43.0.3", + "sha256": "315b9001266a492a6ff443b61238f956b214dbec9910a081ba5b6646a055a805", + "urls": [ + "https://files.pythonhosted.org/packages/0d/05/07b55d1fa21ac18c3a8c79f764e2514e6f6a9698f1be44994f5adf0d29db/cryptography-43.0.3.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_docutils_py3_none_any_dafca5b9": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "docutils-0.21.2-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "docutils==0.21.2", + "sha256": "dafca5b9e384f0e419294eb4d2ff9fa826435bf15f15b7bd45723e8ad76811b2", + "urls": [ + "https://files.pythonhosted.org/packages/8f/d7/9322c609343d929e75e7e5e6255e614fcc67572cfd083959cdef3b7aad79/docutils-0.21.2-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_docutils_sdist_3a6b1873": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "docutils-0.21.2.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "docutils==0.21.2", + "sha256": "3a6b18732edf182daa3cd12775bbb338cf5691468f91eeeb109deff6ebfa986f", + "urls": [ + "https://files.pythonhosted.org/packages/ae/ed/aefcc8cd0ba62a0560c3c18c33925362d46c6075480bfa4df87b28e169a9/docutils-0.21.2.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_idna_py3_none_any_946d195a": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "idna-3.10-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "idna==3.10", + "sha256": "946d195a0d259cbba61165e88e65941f16e9b36ea6ddb97f00452bae8b1287d3", + "urls": [ + "https://files.pythonhosted.org/packages/76/c6/c88e154df9c4e1a2a66ccf0005a88dfb2650c1dffb6f5ce603dfbd452ce3/idna-3.10-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_idna_sdist_12f65c9b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "idna-3.10.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "idna==3.10", + "sha256": "12f65c9b470abda6dc35cf8e63cc574b1c52b11df2c86030af0ac09b01b13ea9", + "urls": [ + "https://files.pythonhosted.org/packages/f1/70/7703c29685631f5a7590aa73f1f1d3fa9a380e654b86af429e0934a32f7d/idna-3.10.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_importlib_metadata_py3_none_any_45e54197": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "importlib_metadata-8.5.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "importlib-metadata==8.5.0", + "sha256": "45e54197d28b7a7f1559e60b95e7c567032b602131fbd588f1497f47880aa68b", + "urls": [ + "https://files.pythonhosted.org/packages/a0/d9/a1e041c5e7caa9a05c925f4bdbdfb7f006d1f74996af53467bc394c97be7/importlib_metadata-8.5.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_importlib_metadata_sdist_71522656": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "importlib_metadata-8.5.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "importlib-metadata==8.5.0", + "sha256": "71522656f0abace1d072b9e5481a48f07c138e00f079c38c8f883823f9c26bd7", + "urls": [ + "https://files.pythonhosted.org/packages/cd/12/33e59336dca5be0c398a7482335911a33aa0e20776128f038019f1a95f1b/importlib_metadata-8.5.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_jaraco_classes_py3_none_any_f662826b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "jaraco.classes-3.4.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-classes==3.4.0", + "sha256": "f662826b6bed8cace05e7ff873ce0f9283b5c924470fe664fff1c2f00f581790", + "urls": [ + "https://files.pythonhosted.org/packages/7f/66/b15ce62552d84bbfcec9a4873ab79d993a1dd4edb922cbfccae192bd5b5f/jaraco.classes-3.4.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_jaraco_classes_sdist_47a024b5": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "jaraco.classes-3.4.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-classes==3.4.0", + "sha256": "47a024b51d0239c0dd8c8540c6c7f484be3b8fcf0b2d85c13825780d3b3f3acd", + "urls": [ + "https://files.pythonhosted.org/packages/06/c0/ed4a27bc5571b99e3cff68f8a9fa5b56ff7df1c2251cc715a652ddd26402/jaraco.classes-3.4.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_jaraco_context_py3_none_any_f797fc48": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "jaraco.context-6.0.1-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-context==6.0.1", + "sha256": "f797fc481b490edb305122c9181830a3a5b76d84ef6d1aef2fb9b47ab956f9e4", + "urls": [ + "https://files.pythonhosted.org/packages/ff/db/0c52c4cf5e4bd9f5d7135ec7669a3a767af21b3a308e1ed3674881e52b62/jaraco.context-6.0.1-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_jaraco_context_sdist_9bae4ea5": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "jaraco_context-6.0.1.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-context==6.0.1", + "sha256": "9bae4ea555cf0b14938dc0aee7c9f32ed303aa20a3b73e7dc80111628792d1b3", + "urls": [ + "https://files.pythonhosted.org/packages/df/ad/f3777b81bf0b6e7bc7514a1656d3e637b2e8e15fab2ce3235730b3e7a4e6/jaraco_context-6.0.1.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_jaraco_functools_py3_none_any_ad159f13": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "jaraco.functools-4.1.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-functools==4.1.0", + "sha256": "ad159f13428bc4acbf5541ad6dec511f91573b90fba04df61dafa2a1231cf649", + "urls": [ + "https://files.pythonhosted.org/packages/9f/4f/24b319316142c44283d7540e76c7b5a6dbd5db623abd86bb7b3491c21018/jaraco.functools-4.1.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_jaraco_functools_sdist_70f7e0e2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "jaraco_functools-4.1.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jaraco-functools==4.1.0", + "sha256": "70f7e0e2ae076498e212562325e805204fc092d7b4c17e0e86c959e249701a9d", + "urls": [ + "https://files.pythonhosted.org/packages/ab/23/9894b3df5d0a6eb44611c36aec777823fc2e07740dabbd0b810e19594013/jaraco_functools-4.1.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_jeepney_py3_none_any_c0a454ad": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "jeepney-0.8.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jeepney==0.8.0", + "sha256": "c0a454ad016ca575060802ee4d590dd912e35c122fa04e70306de3d076cce755", + "urls": [ + "https://files.pythonhosted.org/packages/ae/72/2a1e2290f1ab1e06f71f3d0f1646c9e4634e70e1d37491535e19266e8dc9/jeepney-0.8.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_jeepney_sdist_5efe48d2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "jeepney-0.8.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "jeepney==0.8.0", + "sha256": "5efe48d255973902f6badc3ce55e2aa6c5c3b3bc642059ef3a91247bcfcc5806", + "urls": [ + "https://files.pythonhosted.org/packages/d6/f4/154cf374c2daf2020e05c3c6a03c91348d59b23c5366e968feb198306fdf/jeepney-0.8.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_keyring_py3_none_any_5426f817": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "keyring-25.4.1-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "keyring==25.4.1", + "sha256": "5426f817cf7f6f007ba5ec722b1bcad95a75b27d780343772ad76b17cb47b0bf", + "urls": [ + "https://files.pythonhosted.org/packages/83/25/e6d59e5f0a0508d0dca8bb98c7f7fd3772fc943ac3f53d5ab18a218d32c0/keyring-25.4.1-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_keyring_sdist_b07ebc55": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "keyring-25.4.1.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "keyring==25.4.1", + "sha256": "b07ebc55f3e8ed86ac81dd31ef14e81ace9dd9c3d4b5d77a6e9a2016d0d71a1b", + "urls": [ + "https://files.pythonhosted.org/packages/a5/1c/2bdbcfd5d59dc6274ffb175bc29aa07ecbfab196830e0cfbde7bd861a2ea/keyring-25.4.1.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_markdown_it_py_py3_none_any_35521684": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "markdown_it_py-3.0.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "markdown-it-py==3.0.0", + "sha256": "355216845c60bd96232cd8d8c40e8f9765cc86f46880e43a8fd22dc1a1a8cab1", + "urls": [ + "https://files.pythonhosted.org/packages/42/d7/1ec15b46af6af88f19b8e5ffea08fa375d433c998b8a7639e76935c14f1f/markdown_it_py-3.0.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_markdown_it_py_sdist_e3f60a94": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "markdown-it-py-3.0.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "markdown-it-py==3.0.0", + "sha256": "e3f60a94fa066dc52ec76661e37c851cb232d92f9886b15cb560aaada2df8feb", + "urls": [ + "https://files.pythonhosted.org/packages/38/71/3b932df36c1a044d397a1f92d1cf91ee0a503d91e470cbd670aa66b07ed0/markdown-it-py-3.0.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_mdurl_py3_none_any_84008a41": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "mdurl-0.1.2-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "mdurl==0.1.2", + "sha256": "84008a41e51615a49fc9966191ff91509e3c40b939176e643fd50a5c2196b8f8", + "urls": [ + "https://files.pythonhosted.org/packages/b3/38/89ba8ad64ae25be8de66a6d463314cf1eb366222074cfda9ee839c56a4b4/mdurl-0.1.2-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_mdurl_sdist_bb413d29": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "mdurl-0.1.2.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "mdurl==0.1.2", + "sha256": "bb413d29f5eea38f31dd4754dd7377d4465116fb207585f97bf925588687c1ba", + "urls": [ + "https://files.pythonhosted.org/packages/d6/54/cfe61301667036ec958cb99bd3efefba235e65cdeb9c84d24a8293ba1d90/mdurl-0.1.2.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_more_itertools_py3_none_any_037b0d32": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "more_itertools-10.5.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "more-itertools==10.5.0", + "sha256": "037b0d3203ce90cca8ab1defbbdac29d5f993fc20131f3664dc8d6acfa872aef", + "urls": [ + "https://files.pythonhosted.org/packages/48/7e/3a64597054a70f7c86eb0a7d4fc315b8c1ab932f64883a297bdffeb5f967/more_itertools-10.5.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_more_itertools_sdist_5482bfef": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "more-itertools-10.5.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "more-itertools==10.5.0", + "sha256": "5482bfef7849c25dc3c6dd53a6173ae4795da2a41a80faea6700d9f5846c5da6", + "urls": [ + "https://files.pythonhosted.org/packages/51/78/65922308c4248e0eb08ebcbe67c95d48615cc6f27854b6f2e57143e9178f/more-itertools-10.5.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_macosx_10_12_x86_64_14c5a72e": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.macosx_11_0_arm64.macosx_10_12_universal2.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "14c5a72e9fe82aea5fe3072116ad4661af5cf8e8ff8fc5ad3450f123e4925e86", + "urls": [ + "https://files.pythonhosted.org/packages/b3/89/1daff5d9ba5a95a157c092c7c5f39b8dd2b1ddb4559966f808d31cfb67e0/nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.macosx_11_0_arm64.macosx_10_12_universal2.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_macosx_10_12_x86_64_7b7c2a3c": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "7b7c2a3c9eb1a827d42539aa64091640bd275b81e097cd1d8d82ef91ffa2e811", + "urls": [ + "https://files.pythonhosted.org/packages/2c/b6/42fc3c69cabf86b6b81e4c051a9b6e249c5ba9f8155590222c2622961f58/nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_aarch64_42c64511": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "42c64511469005058cd17cc1537578eac40ae9f7200bedcfd1fc1a05f4f8c200", + "urls": [ + "https://files.pythonhosted.org/packages/45/b9/833f385403abaf0023c6547389ec7a7acf141ddd9d1f21573723a6eab39a/nh3-0.2.18-cp37-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_armv7l_0411beb0": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_armv7l.manylinux2014_armv7l.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "0411beb0589eacb6734f28d5497ca2ed379eafab8ad8c84b31bb5c34072b7164", + "urls": [ + "https://files.pythonhosted.org/packages/05/2b/85977d9e11713b5747595ee61f381bc820749daf83f07b90b6c9964cf932/nh3-0.2.18-cp37-abi3-manylinux_2_17_armv7l.manylinux2014_armv7l.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_ppc64_5f36b271": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64.manylinux2014_ppc64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "5f36b271dae35c465ef5e9090e1fdaba4a60a56f0bb0ba03e0932a66f28b9189", + "urls": [ + "https://files.pythonhosted.org/packages/72/f2/5c894d5265ab80a97c68ca36f25c8f6f0308abac649aaf152b74e7e854a8/nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64.manylinux2014_ppc64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_ppc64le_34c03fa7": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "34c03fa78e328c691f982b7c03d4423bdfd7da69cd707fe572f544cf74ac23ad", + "urls": [ + "https://files.pythonhosted.org/packages/ab/a7/375afcc710dbe2d64cfbd69e31f82f3e423d43737258af01f6a56d844085/nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_s390x_19aaba96": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_s390x.manylinux2014_s390x.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "19aaba96e0f795bd0a6c56291495ff59364f4300d4a39b29a0abc9cb3774a84b", + "urls": [ + "https://files.pythonhosted.org/packages/c2/a8/3bb02d0c60a03ad3a112b76c46971e9480efa98a8946677b5a59f60130ca/nh3-0.2.18-cp37-abi3-manylinux_2_17_s390x.manylinux2014_s390x.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_x86_64_de3ceed6": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "de3ceed6e661954871d6cd78b410213bdcb136f79aafe22aa7182e028b8c7307", + "urls": [ + "https://files.pythonhosted.org/packages/1b/63/6ab90d0e5225ab9780f6c9fb52254fa36b52bb7c188df9201d05b647e5e1/nh3-0.2.18-cp37-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_aarch64_f0eca9ca": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-musllinux_1_2_aarch64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "f0eca9ca8628dbb4e916ae2491d72957fdd35f7a5d326b7032a345f111ac07fe", + "urls": [ + "https://files.pythonhosted.org/packages/a3/da/0c4e282bc3cff4a0adf37005fa1fb42257673fbc1bbf7d1ff639ec3d255a/nh3-0.2.18-cp37-abi3-musllinux_1_2_aarch64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_armv7l_3a157ab1": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-musllinux_1_2_armv7l.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "3a157ab149e591bb638a55c8c6bcb8cdb559c8b12c13a8affaba6cedfe51713a", + "urls": [ + "https://files.pythonhosted.org/packages/de/81/c291231463d21da5f8bba82c8167a6d6893cc5419b0639801ee5d3aeb8a9/nh3-0.2.18-cp37-abi3-musllinux_1_2_armv7l.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_x86_64_36c95d4b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-musllinux_1_2_x86_64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "36c95d4b70530b320b365659bb5034341316e6a9b30f0b25fa9c9eff4c27a204", + "urls": [ + "https://files.pythonhosted.org/packages/eb/61/73a007c74c37895fdf66e0edcd881f5eaa17a348ff02f4bb4bc906d61085/nh3-0.2.18-cp37-abi3-musllinux_1_2_x86_64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_cp37_abi3_win_amd64_8ce0f819": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "nh3-0.2.18-cp37-abi3-win_amd64.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "8ce0f819d2f1933953fca255db2471ad58184a60508f03e6285e5114b6254844", + "urls": [ + "https://files.pythonhosted.org/packages/26/8d/53c5b19c4999bdc6ba95f246f4ef35ca83d7d7423e5e38be43ad66544e5d/nh3-0.2.18-cp37-abi3-win_amd64.whl" + ] + } + }, + "rules_python_publish_deps_311_nh3_sdist_94a16692": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "nh3-0.2.18.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "nh3==0.2.18", + "sha256": "94a166927e53972a9698af9542ace4e38b9de50c34352b962f4d9a7d4c927af4", + "urls": [ + "https://files.pythonhosted.org/packages/62/73/10df50b42ddb547a907deeb2f3c9823022580a7a47281e8eae8e003a9639/nh3-0.2.18.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_pkginfo_py3_none_any_889a6da2": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "pkginfo-1.10.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pkginfo==1.10.0", + "sha256": "889a6da2ed7ffc58ab5b900d888ddce90bce912f2d2de1dc1c26f4cb9fe65097", + "urls": [ + "https://files.pythonhosted.org/packages/56/09/054aea9b7534a15ad38a363a2bd974c20646ab1582a387a95b8df1bfea1c/pkginfo-1.10.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_pkginfo_sdist_5df73835": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "pkginfo-1.10.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pkginfo==1.10.0", + "sha256": "5df73835398d10db79f8eecd5cd86b1f6d29317589ea70796994d49399af6297", + "urls": [ + "https://files.pythonhosted.org/packages/2f/72/347ec5be4adc85c182ed2823d8d1c7b51e13b9a6b0c1aae59582eca652df/pkginfo-1.10.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_pycparser_py3_none_any_c3702b6d": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "pycparser-2.22-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pycparser==2.22", + "sha256": "c3702b6d3dd8c7abc1afa565d7e63d53a1d0bd86cdc24edd75470f4de499cfcc", + "urls": [ + "https://files.pythonhosted.org/packages/13/a3/a812df4e2dd5696d1f351d58b8fe16a405b234ad2886a0dab9183fb78109/pycparser-2.22-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_pycparser_sdist_491c8be9": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "pycparser-2.22.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pycparser==2.22", + "sha256": "491c8be9c040f5390f5bf44a5b07752bd07f56edf992381b05c701439eec10f6", + "urls": [ + "https://files.pythonhosted.org/packages/1d/b2/31537cf4b1ca988837256c910a668b553fceb8f069bedc4b1c826024b52c/pycparser-2.22.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_pygments_py3_none_any_b8e6aca0": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "pygments-2.18.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pygments==2.18.0", + "sha256": "b8e6aca0523f3ab76fee51799c488e38782ac06eafcf95e7ba832985c8e7b13a", + "urls": [ + "https://files.pythonhosted.org/packages/f7/3f/01c8b82017c199075f8f788d0d906b9ffbbc5a47dc9918a945e13d5a2bda/pygments-2.18.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_pygments_sdist_786ff802": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "pygments-2.18.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pygments==2.18.0", + "sha256": "786ff802f32e91311bff3889f6e9a86e81505fe99f2735bb6d60ae0c5004f199", + "urls": [ + "https://files.pythonhosted.org/packages/8e/62/8336eff65bcbc8e4cb5d05b55faf041285951b6e80f33e2bff2024788f31/pygments-2.18.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_pywin32_ctypes_py3_none_any_8a151337": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_windows_x86_64" + ], + "filename": "pywin32_ctypes-0.2.3-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pywin32-ctypes==0.2.3", + "sha256": "8a1513379d709975552d202d942d9837758905c8d01eb82b8bcc30918929e7b8", + "urls": [ + "https://files.pythonhosted.org/packages/de/3d/8161f7711c017e01ac9f008dfddd9410dff3674334c233bde66e7ba65bbf/pywin32_ctypes-0.2.3-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_pywin32_ctypes_sdist_d162dc04": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "pywin32-ctypes-0.2.3.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "pywin32-ctypes==0.2.3", + "sha256": "d162dc04946d704503b2edc4d55f3dba5c1d539ead017afa00142c38b9885755", + "urls": [ + "https://files.pythonhosted.org/packages/85/9f/01a1a99704853cb63f253eea009390c88e7131c67e66a0a02099a8c917cb/pywin32-ctypes-0.2.3.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_readme_renderer_py3_none_any_2fbca89b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "readme_renderer-44.0-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "readme-renderer==44.0", + "sha256": "2fbca89b81a08526aadf1357a8c2ae889ec05fb03f5da67f9769c9a592166151", + "urls": [ + "https://files.pythonhosted.org/packages/e1/67/921ec3024056483db83953ae8e48079ad62b92db7880013ca77632921dd0/readme_renderer-44.0-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_readme_renderer_sdist_8712034e": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "readme_renderer-44.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "readme-renderer==44.0", + "sha256": "8712034eabbfa6805cacf1402b4eeb2a73028f72d1166d6f5cb7f9c047c5d1e1", + "urls": [ + "https://files.pythonhosted.org/packages/5a/a9/104ec9234c8448c4379768221ea6df01260cd6c2ce13182d4eac531c8342/readme_renderer-44.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_requests_py3_none_any_70761cfe": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "requests-2.32.3-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "requests==2.32.3", + "sha256": "70761cfe03c773ceb22aa2f671b4757976145175cdfca038c02654d061d6dcc6", + "urls": [ + "https://files.pythonhosted.org/packages/f9/9b/335f9764261e915ed497fcdeb11df5dfd6f7bf257d4a6a2a686d80da4d54/requests-2.32.3-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_requests_sdist_55365417": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "requests-2.32.3.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "requests==2.32.3", + "sha256": "55365417734eb18255590a9ff9eb97e9e1da868d4ccd6402399eaf68af20a760", + "urls": [ + "https://files.pythonhosted.org/packages/63/70/2bf7780ad2d390a8d301ad0b550f1581eadbd9a20f896afe06353c2a2913/requests-2.32.3.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_requests_toolbelt_py2_none_any_cccfdd66": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "requests_toolbelt-1.0.0-py2.py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "requests-toolbelt==1.0.0", + "sha256": "cccfdd665f0a24fcf4726e690f65639d272bb0637b9b92dfd91a5568ccf6bd06", + "urls": [ + "https://files.pythonhosted.org/packages/3f/51/d4db610ef29373b879047326cbf6fa98b6c1969d6f6dc423279de2b1be2c/requests_toolbelt-1.0.0-py2.py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_requests_toolbelt_sdist_7681a0a3": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "requests-toolbelt-1.0.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "requests-toolbelt==1.0.0", + "sha256": "7681a0a3d047012b5bdc0ee37d7f8f07ebe76ab08caeccfc3921ce23c88d5bc6", + "urls": [ + "https://files.pythonhosted.org/packages/f3/61/d7545dafb7ac2230c70d38d31cbfe4cc64f7144dc41f6e4e4b78ecd9f5bb/requests-toolbelt-1.0.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_rfc3986_py2_none_any_50b1502b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "rfc3986-2.0.0-py2.py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "rfc3986==2.0.0", + "sha256": "50b1502b60e289cb37883f3dfd34532b8873c7de9f49bb546641ce9cbd256ebd", + "urls": [ + "https://files.pythonhosted.org/packages/ff/9a/9afaade874b2fa6c752c36f1548f718b5b83af81ed9b76628329dab81c1b/rfc3986-2.0.0-py2.py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_rfc3986_sdist_97aacf9d": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "rfc3986-2.0.0.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "rfc3986==2.0.0", + "sha256": "97aacf9dbd4bfd829baad6e6309fa6573aaf1be3f6fa735c8ab05e46cecb261c", + "urls": [ + "https://files.pythonhosted.org/packages/85/40/1520d68bfa07ab5a6f065a186815fb6610c86fe957bc065754e47f7b0840/rfc3986-2.0.0.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_rich_py3_none_any_6049d5e6": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "rich-13.9.4-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "rich==13.9.4", + "sha256": "6049d5e6ec054bf2779ab3358186963bac2ea89175919d699e378b99738c2a90", + "urls": [ + "https://files.pythonhosted.org/packages/19/71/39c7c0d87f8d4e6c020a393182060eaefeeae6c01dab6a84ec346f2567df/rich-13.9.4-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_rich_sdist_43959497": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "rich-13.9.4.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "rich==13.9.4", + "sha256": "439594978a49a09530cff7ebc4b5c7103ef57baf48d5ea3184f21d9a2befa098", + "urls": [ + "https://files.pythonhosted.org/packages/ab/3a/0316b28d0761c6734d6bc14e770d85506c986c85ffb239e688eeaab2c2bc/rich-13.9.4.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_secretstorage_py3_none_any_f356e662": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "filename": "SecretStorage-3.3.3-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "secretstorage==3.3.3", + "sha256": "f356e6628222568e3af06f2eba8df495efa13b3b63081dafd4f7d9a7b7bc9f99", + "urls": [ + "https://files.pythonhosted.org/packages/54/24/b4293291fa1dd830f353d2cb163295742fa87f179fcc8a20a306a81978b7/SecretStorage-3.3.3-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_secretstorage_sdist_2403533e": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "SecretStorage-3.3.3.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "secretstorage==3.3.3", + "sha256": "2403533ef369eca6d2ba81718576c5e0f564d5cca1b58f73a8b23e7d4eeebd77", + "urls": [ + "https://files.pythonhosted.org/packages/53/a4/f48c9d79cb507ed1373477dbceaba7401fd8a23af63b837fa61f1dcd3691/SecretStorage-3.3.3.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_twine_py3_none_any_215dbe7b": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "twine-5.1.1-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "twine==5.1.1", + "sha256": "215dbe7b4b94c2c50a7315c0275d2258399280fbb7d04182c7e55e24b5f93997", + "urls": [ + "https://files.pythonhosted.org/packages/5d/ec/00f9d5fd040ae29867355e559a94e9a8429225a0284a3f5f091a3878bfc0/twine-5.1.1-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_twine_sdist_9aa08251": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "twine-5.1.1.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "twine==5.1.1", + "sha256": "9aa0825139c02b3434d913545c7b847a21c835e11597f5255842d457da2322db", + "urls": [ + "https://files.pythonhosted.org/packages/77/68/bd982e5e949ef8334e6f7dcf76ae40922a8750aa2e347291ae1477a4782b/twine-5.1.1.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_urllib3_py3_none_any_ca899ca0": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "urllib3-2.2.3-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "urllib3==2.2.3", + "sha256": "ca899ca043dcb1bafa3e262d73aa25c465bfb49e0bd9dd5d59f1d0acba2f8fac", + "urls": [ + "https://files.pythonhosted.org/packages/ce/d9/5f4c13cecde62396b0d3fe530a50ccea91e7dfc1ccf0e09c228841bb5ba8/urllib3-2.2.3-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_urllib3_sdist_e7d814a8": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "urllib3-2.2.3.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "urllib3==2.2.3", + "sha256": "e7d814a81dad81e6caf2ec9fdedb284ecc9c73076b62654547cc64ccdcae26e9", + "urls": [ + "https://files.pythonhosted.org/packages/ed/63/22ba4ebfe7430b76388e7cd448d5478814d3032121827c12a2cc287e2260/urllib3-2.2.3.tar.gz" + ] + } + }, + "rules_python_publish_deps_311_zipp_py3_none_any_a817ac80": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "filename": "zipp-3.20.2-py3-none-any.whl", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "zipp==3.20.2", + "sha256": "a817ac80d6cf4b23bf7f2828b7cabf326f15a001bea8b1f9b49631780ba28350", + "urls": [ + "https://files.pythonhosted.org/packages/62/8b/5ba542fa83c90e09eac972fc9baca7a88e7e7ca4b221a89251954019308b/zipp-3.20.2-py3-none-any.whl" + ] + } + }, + "rules_python_publish_deps_311_zipp_sdist_bc9eb26f": { + "bzlFile": "@@rules_python~//python/private/pypi:whl_library.bzl", + "ruleClassName": "whl_library", + "attributes": { + "dep_template": "@rules_python_publish_deps//{name}:{target}", + "experimental_target_platforms": [ + "cp311_linux_aarch64", + "cp311_linux_arm", + "cp311_linux_ppc", + "cp311_linux_s390x", + "cp311_linux_x86_64", + "cp311_osx_aarch64", + "cp311_osx_x86_64", + "cp311_windows_x86_64" + ], + "extra_pip_args": [ + "--index-url", + "https://pypi.org/simple" + ], + "filename": "zipp-3.20.2.tar.gz", + "python_interpreter_target": "@@rules_python~~python~python_3_11_host//:python", + "repo": "rules_python_publish_deps_311", + "requirement": "zipp==3.20.2", + "sha256": "bc9eb26f4506fda01b81bcde0ca78103b6e62f991b381fec825435c836edbc29", + "urls": [ + "https://files.pythonhosted.org/packages/54/bf/5c0000c44ebc80123ecbdddba1f5dcd94a5ada602a9c225d84b5aaa55e86/zipp-3.20.2.tar.gz" + ] + } + }, + "bazel-orfs-pip": { + "bzlFile": "@@rules_python~//python/private/pypi:hub_repository.bzl", + "ruleClassName": "hub_repository", + "attributes": { + "repo_name": "bazel-orfs-pip", + "extra_hub_aliases": {}, + "whl_map": { + "contourpy": "{\"bazel-orfs-pip_313_contourpy\":[{\"version\":\"3.13\"}]}", + "cycler": "{\"bazel-orfs-pip_313_cycler\":[{\"version\":\"3.13\"}]}", + "fonttools": "{\"bazel-orfs-pip_313_fonttools\":[{\"version\":\"3.13\"}]}", + "kiwisolver": "{\"bazel-orfs-pip_313_kiwisolver\":[{\"version\":\"3.13\"}]}", + "matplotlib": "{\"bazel-orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", + "numpy": "{\"bazel-orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", + "packaging": "{\"bazel-orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pandas": "{\"bazel-orfs-pip_313_pandas\":[{\"version\":\"3.13\"}]}", + "pillow": "{\"bazel-orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", + "pyparsing": "{\"bazel-orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", + "python_dateutil": "{\"bazel-orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pytz": "{\"bazel-orfs-pip_313_pytz\":[{\"version\":\"3.13\"}]}", + "pyyaml": "{\"bazel-orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", + "six": "{\"bazel-orfs-pip_313_six\":[{\"version\":\"3.13\"}]}", + "tzdata": "{\"bazel-orfs-pip_313_tzdata\":[{\"version\":\"3.13\"}]}" + }, + "packages": [ + "contourpy", + "cycler", + "fonttools", + "kiwisolver", + "matplotlib", + "numpy", + "packaging", + "pandas", + "pillow", + "pyparsing", + "python_dateutil", + "pytz", + "pyyaml", + "six", + "tzdata" + ], + "groups": {} + } + }, + "orfs-pip": { + "bzlFile": "@@rules_python~//python/private/pypi:hub_repository.bzl", + "ruleClassName": "hub_repository", + "attributes": { + "repo_name": "orfs-pip", + "extra_hub_aliases": {}, + "whl_map": { + "contourpy": "{\"orfs-pip_313_contourpy\":[{\"version\":\"3.13\"}]}", + "cycler": "{\"orfs-pip_313_cycler\":[{\"version\":\"3.13\"}]}", + "fonttools": "{\"orfs-pip_313_fonttools\":[{\"version\":\"3.13\"}]}", + "kiwisolver": "{\"orfs-pip_313_kiwisolver\":[{\"version\":\"3.13\"}]}", + "matplotlib": "{\"orfs-pip_313_matplotlib\":[{\"version\":\"3.13\"}]}", + "numpy": "{\"orfs-pip_313_numpy\":[{\"version\":\"3.13\"}]}", + "packaging": "{\"orfs-pip_313_packaging\":[{\"version\":\"3.13\"}]}", + "pillow": "{\"orfs-pip_313_pillow\":[{\"version\":\"3.13\"}]}", + "pyparsing": "{\"orfs-pip_313_pyparsing\":[{\"version\":\"3.13\"}]}", + "python_dateutil": "{\"orfs-pip_313_python_dateutil\":[{\"version\":\"3.13\"}]}", + "pyyaml": "{\"orfs-pip_313_pyyaml\":[{\"version\":\"3.13\"}]}", + "six": "{\"orfs-pip_313_six\":[{\"version\":\"3.13\"}]}" + }, + "packages": [ + "contourpy", + "cycler", + "fonttools", + "kiwisolver", + "matplotlib", + "numpy", + "packaging", + "pillow", + "pyparsing", + "python_dateutil", + "pyyaml", + "six" + ], + "groups": {} + } + }, + "pip_deps": { + "bzlFile": "@@rules_python~//python/private/pypi:hub_repository.bzl", + "ruleClassName": "hub_repository", + "attributes": { + "repo_name": "pip_deps", + "extra_hub_aliases": {}, + "whl_map": { + "numpy": "{\"pip_deps_310_numpy\":[{\"version\":\"3.10\"}],\"pip_deps_311_numpy\":[{\"version\":\"3.11\"}],\"pip_deps_312_numpy\":[{\"version\":\"3.12\"}],\"pip_deps_38_numpy\":[{\"version\":\"3.8\"}],\"pip_deps_39_numpy\":[{\"version\":\"3.9\"}]}", + "setuptools": "{\"pip_deps_310_setuptools\":[{\"version\":\"3.10\"}],\"pip_deps_311_setuptools\":[{\"version\":\"3.11\"}],\"pip_deps_312_setuptools\":[{\"version\":\"3.12\"}],\"pip_deps_38_setuptools\":[{\"version\":\"3.8\"}],\"pip_deps_39_setuptools\":[{\"version\":\"3.9\"}]}" + }, + "packages": [ + "numpy", + "setuptools" + ], + "groups": {} + } + }, + "rules_fuzzing_py_deps": { + "bzlFile": "@@rules_python~//python/private/pypi:hub_repository.bzl", + "ruleClassName": "hub_repository", + "attributes": { + "repo_name": "rules_fuzzing_py_deps", + "extra_hub_aliases": {}, + "whl_map": { + "absl_py": "{\"rules_fuzzing_py_deps_310_absl_py\":[{\"version\":\"3.10\"}],\"rules_fuzzing_py_deps_311_absl_py\":[{\"version\":\"3.11\"}],\"rules_fuzzing_py_deps_312_absl_py\":[{\"version\":\"3.12\"}],\"rules_fuzzing_py_deps_38_absl_py\":[{\"version\":\"3.8\"}],\"rules_fuzzing_py_deps_39_absl_py\":[{\"version\":\"3.9\"}]}", + "six": "{\"rules_fuzzing_py_deps_310_six\":[{\"version\":\"3.10\"}],\"rules_fuzzing_py_deps_311_six\":[{\"version\":\"3.11\"}],\"rules_fuzzing_py_deps_312_six\":[{\"version\":\"3.12\"}],\"rules_fuzzing_py_deps_38_six\":[{\"version\":\"3.8\"}],\"rules_fuzzing_py_deps_39_six\":[{\"version\":\"3.9\"}]}" + }, + "packages": [ + "absl_py", + "six" + ], + "groups": {} + } + }, + "rules_python_publish_deps": { + "bzlFile": "@@rules_python~//python/private/pypi:hub_repository.bzl", + "ruleClassName": "hub_repository", + "attributes": { + "repo_name": "rules_python_publish_deps", + "extra_hub_aliases": {}, + "whl_map": { + "backports_tarfile": "{\"rules_python_publish_deps_311_backports_tarfile_py3_none_any_77e284d7\":[{\"filename\":\"backports.tarfile-1.2.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_backports_tarfile_sdist_d75e02c2\":[{\"filename\":\"backports_tarfile-1.2.0.tar.gz\",\"version\":\"3.11\"}]}", + "certifi": "{\"rules_python_publish_deps_311_certifi_py3_none_any_922820b5\":[{\"filename\":\"certifi-2024.8.30-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_certifi_sdist_bec941d2\":[{\"filename\":\"certifi-2024.8.30.tar.gz\",\"version\":\"3.11\"}]}", + "cffi": "{\"rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_aarch64_a1ed2dd2\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_ppc64le_46bf4316\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_s390x_a24ed04c\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_cp311_cp311_manylinux_2_17_x86_64_610faea7\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_cp311_cp311_musllinux_1_1_aarch64_a9b15d49\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-musllinux_1_1_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_cp311_cp311_musllinux_1_1_x86_64_fc48c783\":[{\"filename\":\"cffi-1.17.1-cp311-cp311-musllinux_1_1_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cffi_sdist_1c39c601\":[{\"filename\":\"cffi-1.17.1.tar.gz\",\"version\":\"3.11\"}]}", + "charset_normalizer": "{\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_10_9_universal2_0d99dd8f\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_universal2.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_10_9_x86_64_c57516e5\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-macosx_10_9_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_macosx_11_0_arm64_6dba5d19\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-macosx_11_0_arm64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_aarch64_bf4475b8\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_ppc64le_ce031db0\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_s390x_8ff4e7cd\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_manylinux_2_17_x86_64_3710a975\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_aarch64_47334db7\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_ppc64le_f1a2f519\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_ppc64le.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_s390x_63bc5c4a\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_s390x.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_musllinux_1_2_x86_64_bcb4f8ea\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-musllinux_1_2_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_cp311_cp311_win_amd64_cee4373f\":[{\"filename\":\"charset_normalizer-3.4.0-cp311-cp311-win_amd64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_py3_none_any_fe9f97fe\":[{\"filename\":\"charset_normalizer-3.4.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_charset_normalizer_sdist_223217c3\":[{\"filename\":\"charset_normalizer-3.4.0.tar.gz\",\"version\":\"3.11\"}]}", + "cryptography": "{\"rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_17_aarch64_846da004\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_17_x86_64_0f996e72\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_28_aarch64_f7b178f1\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-manylinux_2_28_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_cp39_abi3_manylinux_2_28_x86_64_c2e6fc39\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-manylinux_2_28_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_cp39_abi3_musllinux_1_2_aarch64_e1be4655\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-musllinux_1_2_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_cp39_abi3_musllinux_1_2_x86_64_df6b6c6d\":[{\"filename\":\"cryptography-43.0.3-cp39-abi3-musllinux_1_2_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_cryptography_sdist_315b9001\":[{\"filename\":\"cryptography-43.0.3.tar.gz\",\"version\":\"3.11\"}]}", + "docutils": "{\"rules_python_publish_deps_311_docutils_py3_none_any_dafca5b9\":[{\"filename\":\"docutils-0.21.2-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_docutils_sdist_3a6b1873\":[{\"filename\":\"docutils-0.21.2.tar.gz\",\"version\":\"3.11\"}]}", + "idna": "{\"rules_python_publish_deps_311_idna_py3_none_any_946d195a\":[{\"filename\":\"idna-3.10-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_idna_sdist_12f65c9b\":[{\"filename\":\"idna-3.10.tar.gz\",\"version\":\"3.11\"}]}", + "importlib_metadata": "{\"rules_python_publish_deps_311_importlib_metadata_py3_none_any_45e54197\":[{\"filename\":\"importlib_metadata-8.5.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_importlib_metadata_sdist_71522656\":[{\"filename\":\"importlib_metadata-8.5.0.tar.gz\",\"version\":\"3.11\"}]}", + "jaraco_classes": "{\"rules_python_publish_deps_311_jaraco_classes_py3_none_any_f662826b\":[{\"filename\":\"jaraco.classes-3.4.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_jaraco_classes_sdist_47a024b5\":[{\"filename\":\"jaraco.classes-3.4.0.tar.gz\",\"version\":\"3.11\"}]}", + "jaraco_context": "{\"rules_python_publish_deps_311_jaraco_context_py3_none_any_f797fc48\":[{\"filename\":\"jaraco.context-6.0.1-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_jaraco_context_sdist_9bae4ea5\":[{\"filename\":\"jaraco_context-6.0.1.tar.gz\",\"version\":\"3.11\"}]}", + "jaraco_functools": "{\"rules_python_publish_deps_311_jaraco_functools_py3_none_any_ad159f13\":[{\"filename\":\"jaraco.functools-4.1.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_jaraco_functools_sdist_70f7e0e2\":[{\"filename\":\"jaraco_functools-4.1.0.tar.gz\",\"version\":\"3.11\"}]}", + "jeepney": "{\"rules_python_publish_deps_311_jeepney_py3_none_any_c0a454ad\":[{\"filename\":\"jeepney-0.8.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_jeepney_sdist_5efe48d2\":[{\"filename\":\"jeepney-0.8.0.tar.gz\",\"version\":\"3.11\"}]}", + "keyring": "{\"rules_python_publish_deps_311_keyring_py3_none_any_5426f817\":[{\"filename\":\"keyring-25.4.1-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_keyring_sdist_b07ebc55\":[{\"filename\":\"keyring-25.4.1.tar.gz\",\"version\":\"3.11\"}]}", + "markdown_it_py": "{\"rules_python_publish_deps_311_markdown_it_py_py3_none_any_35521684\":[{\"filename\":\"markdown_it_py-3.0.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_markdown_it_py_sdist_e3f60a94\":[{\"filename\":\"markdown-it-py-3.0.0.tar.gz\",\"version\":\"3.11\"}]}", + "mdurl": "{\"rules_python_publish_deps_311_mdurl_py3_none_any_84008a41\":[{\"filename\":\"mdurl-0.1.2-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_mdurl_sdist_bb413d29\":[{\"filename\":\"mdurl-0.1.2.tar.gz\",\"version\":\"3.11\"}]}", + "more_itertools": "{\"rules_python_publish_deps_311_more_itertools_py3_none_any_037b0d32\":[{\"filename\":\"more_itertools-10.5.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_more_itertools_sdist_5482bfef\":[{\"filename\":\"more-itertools-10.5.0.tar.gz\",\"version\":\"3.11\"}]}", + "nh3": "{\"rules_python_publish_deps_311_nh3_cp37_abi3_macosx_10_12_x86_64_14c5a72e\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.macosx_11_0_arm64.macosx_10_12_universal2.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_macosx_10_12_x86_64_7b7c2a3c\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-macosx_10_12_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_aarch64_42c64511\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_armv7l_0411beb0\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_armv7l.manylinux2014_armv7l.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_ppc64_5f36b271\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64.manylinux2014_ppc64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_ppc64le_34c03fa7\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_s390x_19aaba96\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_s390x.manylinux2014_s390x.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_manylinux_2_17_x86_64_de3ceed6\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_aarch64_f0eca9ca\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-musllinux_1_2_aarch64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_armv7l_3a157ab1\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-musllinux_1_2_armv7l.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_musllinux_1_2_x86_64_36c95d4b\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-musllinux_1_2_x86_64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_cp37_abi3_win_amd64_8ce0f819\":[{\"filename\":\"nh3-0.2.18-cp37-abi3-win_amd64.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_nh3_sdist_94a16692\":[{\"filename\":\"nh3-0.2.18.tar.gz\",\"version\":\"3.11\"}]}", + "pkginfo": "{\"rules_python_publish_deps_311_pkginfo_py3_none_any_889a6da2\":[{\"filename\":\"pkginfo-1.10.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_pkginfo_sdist_5df73835\":[{\"filename\":\"pkginfo-1.10.0.tar.gz\",\"version\":\"3.11\"}]}", + "pycparser": "{\"rules_python_publish_deps_311_pycparser_py3_none_any_c3702b6d\":[{\"filename\":\"pycparser-2.22-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_pycparser_sdist_491c8be9\":[{\"filename\":\"pycparser-2.22.tar.gz\",\"version\":\"3.11\"}]}", + "pygments": "{\"rules_python_publish_deps_311_pygments_py3_none_any_b8e6aca0\":[{\"filename\":\"pygments-2.18.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_pygments_sdist_786ff802\":[{\"filename\":\"pygments-2.18.0.tar.gz\",\"version\":\"3.11\"}]}", + "pywin32_ctypes": "{\"rules_python_publish_deps_311_pywin32_ctypes_py3_none_any_8a151337\":[{\"filename\":\"pywin32_ctypes-0.2.3-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_pywin32_ctypes_sdist_d162dc04\":[{\"filename\":\"pywin32-ctypes-0.2.3.tar.gz\",\"version\":\"3.11\"}]}", + "readme_renderer": "{\"rules_python_publish_deps_311_readme_renderer_py3_none_any_2fbca89b\":[{\"filename\":\"readme_renderer-44.0-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_readme_renderer_sdist_8712034e\":[{\"filename\":\"readme_renderer-44.0.tar.gz\",\"version\":\"3.11\"}]}", + "requests": "{\"rules_python_publish_deps_311_requests_py3_none_any_70761cfe\":[{\"filename\":\"requests-2.32.3-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_requests_sdist_55365417\":[{\"filename\":\"requests-2.32.3.tar.gz\",\"version\":\"3.11\"}]}", + "requests_toolbelt": "{\"rules_python_publish_deps_311_requests_toolbelt_py2_none_any_cccfdd66\":[{\"filename\":\"requests_toolbelt-1.0.0-py2.py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_requests_toolbelt_sdist_7681a0a3\":[{\"filename\":\"requests-toolbelt-1.0.0.tar.gz\",\"version\":\"3.11\"}]}", + "rfc3986": "{\"rules_python_publish_deps_311_rfc3986_py2_none_any_50b1502b\":[{\"filename\":\"rfc3986-2.0.0-py2.py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_rfc3986_sdist_97aacf9d\":[{\"filename\":\"rfc3986-2.0.0.tar.gz\",\"version\":\"3.11\"}]}", + "rich": "{\"rules_python_publish_deps_311_rich_py3_none_any_6049d5e6\":[{\"filename\":\"rich-13.9.4-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_rich_sdist_43959497\":[{\"filename\":\"rich-13.9.4.tar.gz\",\"version\":\"3.11\"}]}", + "secretstorage": "{\"rules_python_publish_deps_311_secretstorage_py3_none_any_f356e662\":[{\"filename\":\"SecretStorage-3.3.3-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_secretstorage_sdist_2403533e\":[{\"filename\":\"SecretStorage-3.3.3.tar.gz\",\"version\":\"3.11\"}]}", + "twine": "{\"rules_python_publish_deps_311_twine_py3_none_any_215dbe7b\":[{\"filename\":\"twine-5.1.1-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_twine_sdist_9aa08251\":[{\"filename\":\"twine-5.1.1.tar.gz\",\"version\":\"3.11\"}]}", + "urllib3": "{\"rules_python_publish_deps_311_urllib3_py3_none_any_ca899ca0\":[{\"filename\":\"urllib3-2.2.3-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_urllib3_sdist_e7d814a8\":[{\"filename\":\"urllib3-2.2.3.tar.gz\",\"version\":\"3.11\"}]}", + "zipp": "{\"rules_python_publish_deps_311_zipp_py3_none_any_a817ac80\":[{\"filename\":\"zipp-3.20.2-py3-none-any.whl\",\"version\":\"3.11\"}],\"rules_python_publish_deps_311_zipp_sdist_bc9eb26f\":[{\"filename\":\"zipp-3.20.2.tar.gz\",\"version\":\"3.11\"}]}" + }, + "packages": [ + "backports_tarfile", + "certifi", + "charset_normalizer", + "docutils", + "idna", + "importlib_metadata", + "jaraco_classes", + "jaraco_context", + "jaraco_functools", + "keyring", + "markdown_it_py", + "mdurl", + "more_itertools", + "nh3", + "pkginfo", + "pygments", + "readme_renderer", + "requests", + "requests_toolbelt", + "rfc3986", + "rich", + "twine", + "urllib3", + "zipp" + ], + "groups": {} + } + } + }, + "moduleExtensionMetadata": { + "useAllRepos": "NO", + "reproducible": false + }, + "recordedRepoMappingEntries": [ + [ + "bazel_features~", + "bazel_features_globals", + "bazel_features~~version_extension~bazel_features_globals" + ], + [ + "bazel_features~", + "bazel_features_version", + "bazel_features~~version_extension~bazel_features_version" + ], + [ + "rules_python~", + "bazel_features", + "bazel_features~" + ], + [ + "rules_python~", + "bazel_skylib", + "bazel_skylib~" + ], + [ + "rules_python~", + "bazel_tools", + "bazel_tools" + ], + [ + "rules_python~", + "pypi__build", + "rules_python~~internal_deps~pypi__build" + ], + [ + "rules_python~", + "pypi__click", + "rules_python~~internal_deps~pypi__click" + ], + [ + "rules_python~", + "pypi__colorama", + "rules_python~~internal_deps~pypi__colorama" + ], + [ + "rules_python~", + "pypi__importlib_metadata", + "rules_python~~internal_deps~pypi__importlib_metadata" + ], + [ + "rules_python~", + "pypi__installer", + "rules_python~~internal_deps~pypi__installer" + ], + [ + "rules_python~", + "pypi__more_itertools", + "rules_python~~internal_deps~pypi__more_itertools" + ], + [ + "rules_python~", + "pypi__packaging", + "rules_python~~internal_deps~pypi__packaging" + ], + [ + "rules_python~", + "pypi__pep517", + "rules_python~~internal_deps~pypi__pep517" + ], + [ + "rules_python~", + "pypi__pip", + "rules_python~~internal_deps~pypi__pip" + ], + [ + "rules_python~", + "pypi__pip_tools", + "rules_python~~internal_deps~pypi__pip_tools" + ], + [ + "rules_python~", + "pypi__pyproject_hooks", + "rules_python~~internal_deps~pypi__pyproject_hooks" + ], + [ + "rules_python~", + "pypi__setuptools", + "rules_python~~internal_deps~pypi__setuptools" + ], + [ + "rules_python~", + "pypi__tomli", + "rules_python~~internal_deps~pypi__tomli" + ], + [ + "rules_python~", + "pypi__wheel", + "rules_python~~internal_deps~pypi__wheel" + ], + [ + "rules_python~", + "pypi__zipp", + "rules_python~~internal_deps~pypi__zipp" + ], + [ + "rules_python~", + "pythons_hub", + "rules_python~~python~pythons_hub" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_10_host", + "rules_python~~python~python_3_10_host" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_11_host", + "rules_python~~python~python_3_11_host" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_12_host", + "rules_python~~python~python_3_12_host" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_13_host", + "rules_python~~python~python_3_13_host" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_8_host", + "rules_python~~python~python_3_8_host" + ], + [ + "rules_python~~python~pythons_hub", + "python_3_9_host", + "rules_python~~python~python_3_9_host" + ] + ] + } + } + } +} diff --git a/README.md b/README.md index 14df26ed44..515be0b597 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,14 @@ timeline ## Tool Installation +There are different ways to install and develop OpenROAD and ORFS, which is the best fit depends use-case, experience and personal taste. + +### Use Bazel, avoid installing anything at all and adapt the flow to your needs in your own repository + +[bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) provides a seamless, reproducible way to manage dependencies and adapt the flow without requiring manual installations(no Docker images, sudo bash scripts, etc.) + +By leveraging [Bazel](https://bazel.build/)'s robust build system, all dependencies are automatically resolved, versioned, and built in a consistent environment. This eliminates setup complexity, ensures fast incremental builds, and allows for easy customization of the flow, making it an efficient choice for both [beginners](https://github.com/Pinata-Consulting/RegFileStudy) and [advanced](https://github.com/The-OpenROAD-Project/megaboom) users. + ### Docker Based Installation To ease dependency installation issues, ORFS uses docker images. @@ -90,13 +98,30 @@ Document for detailed local build from sources and installation steps found [her individual flows commands, see the documentation [here](https://openroad.readthedocs.io/en/latest/). - For details about automated flow setup, see ORFS docs - [here](https://openroad-flow-scripts.readthedocs.io/en/latest/user/GettingStarted.html). + [here](https://openroad-flow-scripts.readthedocs.io/en/latest/index2.html#getting-started-with-openroad-flow-scripts). - Flow tutorial to run the complete OpenROAD based flow from RTL-GDSII, see the tutorial [here](https://openroad-flow-scripts.readthedocs.io/en/latest/tutorials/FlowTutorial.html). - To watch ORFS flow tutorial videos, check [here](https://theopenroadproject.org/video). +## Building from your own git repository + +ORFS supports hosting projects in your own git repository +without the need to fork ORFS. + +To build from your own git repository: + + cd /home/me/myproject + make --file=~/OpenROAD-flow-scripts/flow/Makefile DESIGN_CONFIG=somefolder/config.mk ... + +## Running a quick smoke-test of ORFS on your own Verilog + +You can [run ORFS on your own Verilog files](./flow/designs/asap7/minimal/README.md) +without setting up a project or moving your Verilog files and even learn +a thing or two about floorplan, placement and routing +before you create an .sdc file and a config.mk file. + ## Citing this Work If you use this software in any published work, we would appreciate a citation! diff --git a/flow/WORKSPACE.bazel b/WORKSPACE.bazel similarity index 100% rename from flow/WORKSPACE.bazel rename to WORKSPACE.bazel diff --git a/build_openroad.sh b/build_openroad.sh index 604985e306..c4967f9b68 100755 --- a/build_openroad.sh +++ b/build_openroad.sh @@ -21,7 +21,7 @@ OPENROAD_APP_BRANCH="master" INSTALL_PATH="$(pwd)/tools/install" YOSYS_USER_ARGS="" -YOSYS_ARGS="CONFIG=clang" +YOSYS_ARGS="" OPENROAD_APP_USER_ARGS="" OPENROAD_APP_ARGS="" @@ -237,6 +237,10 @@ __local_build() set -u fi + echo "[INFO FLW-0018] Compiling OpenROAD." + eval ${NICE} ./tools/OpenROAD/etc/Build.sh -dir="$DIR/tools/OpenROAD/build" -threads=${PROC} -cmake=\'${OPENROAD_APP_ARGS}\' + ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}" + YOSYS_ABC_PATH=tools/yosys/abc if [[ -d "${YOSYS_ABC_PATH}/.git" ]]; then # update indexes to make sure git diff-index uses correct data @@ -246,9 +250,10 @@ __local_build() echo "[INFO FLW-0017] Compiling Yosys." ${NICE} make install -C tools/yosys -j "${PROC}" ${YOSYS_ARGS} - echo "[INFO FLW-0018] Compiling OpenROAD." - eval ${NICE} ./tools/OpenROAD/etc/Build.sh -dir="$DIR/tools/OpenROAD/build" -threads=${PROC} -cmake=\'${OPENROAD_APP_ARGS}\' - ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}" + echo "[INFO FLW-0030] Compiling yosys-slang." + # CMAKE_FLAGS added to work around yosys-slang#141 (unable to build outside of git checkout) + ${NICE} make install -C tools/yosys-slang -j "${PROC}" YOSYS_PREFIX="${INSTALL_PATH}/yosys/bin/" CMAKE_FLAGS="-DYOSYS_SLANG_REVISION=unknown -DSLANG_REVISION=unknown" + } __update_openroad_app_remote() @@ -340,7 +345,7 @@ __common_setup # Choose install method if [ -z "${LOCAL_BUILD+x}" ] && command -v docker &> /dev/null; then - echo -n "[INFO FLW-0000] Using docker build method." + echo "[INFO FLW-0000] Using docker build method." __docker_build else echo -n "[INFO FLW-0001] Using local build method." diff --git a/dev_env.sh b/dev_env.sh index 12f1a933c8..917747caf5 100755 --- a/dev_env.sh +++ b/dev_env.sh @@ -1,9 +1,16 @@ #!/usr/bin/env bash - -function setpaths() { - local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")") +# +# Set developer paths and environment variables here, +# user settings go in ./env.sh +function __setpaths() { + local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")") + [ "$(find $DIR/dependencies -type f -user root)" ] && echo "WARNING! Files set up by sudo found in $DIR" export PATH="$DIR/dependencies/bin:$PATH" export CMAKE_INSTALL_RPATH=$DIR/dependencies/lib:$DIR/dependencies/lib64 -} -setpaths + if [[ "$OSTYPE" == "darwin"* ]]; then + export CMAKE_PREFIX_PATH="$(brew --prefix or-tools)" + fi +} +__setpaths +unset -f __setpaths diff --git a/docker/Dockerfile.builder b/docker/Dockerfile.builder index b7bcb250bd..69d616f6da 100644 --- a/docker/Dockerfile.builder +++ b/docker/Dockerfile.builder @@ -15,12 +15,23 @@ COPY --link build_openroad.sh build_openroad.sh FROM orfs-base AS orfs-builder-base +# Inject compiler wrapper scripts that append the macros +RUN mkdir -p /usr/local/bin/wrapped-cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/gcc && \ + echo 'exec /usr/bin/gcc -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/gcc && \ + chmod +x /usr/local/bin/wrapped-cc/gcc && \ + ln -sf /usr/local/bin/wrapped-cc/gcc /usr/local/bin/wrapped-cc/cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/g++ && \ + echo 'exec /usr/bin/g++ -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/g++ && \ + chmod +x /usr/local/bin/wrapped-cc/g++ + +# Prepend wrapper directory to PATH so they override system compilers +ENV PATH="/usr/local/bin/wrapped-cc:$PATH" + COPY --link tools tools ARG numThreads=$(nproc) RUN echo "" > tools/yosys/abc/.gitcommit && \ - env CFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ - CXXFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ ./build_openroad.sh --no_init --local --threads ${numThreads} FROM orfs-base diff --git a/docker/Dockerfile.dev b/docker/Dockerfile.dev index 26a206bc1c..a2a822b486 100644 --- a/docker/Dockerfile.dev +++ b/docker/Dockerfile.dev @@ -15,10 +15,22 @@ COPY InstallerOpenROAD.sh \ ARG options="" ARG constantBuildDir="-constant-build-dir" -RUN env CFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ - CXXFLAGS="-D__TIME__=0 -D__DATE__=0 -D__TIMESTAMP__=0 -Wno-builtin-macro-redefined" \ - ./DependencyInstaller.sh $options $constantBuildDir \ - && rm -rf /tmp/installer /tmp/* /var/tmp/* /var/lib/apt/lists/* +# add compiler wrapper scripts +# inject the macro definitions during compilation only +RUN mkdir -p /usr/local/bin/wrapped-cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/gcc && \ + echo 'exec /usr/bin/gcc -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/gcc && \ + chmod +x /usr/local/bin/wrapped-cc/gcc && \ + ln -sf /usr/local/bin/wrapped-cc/gcc /usr/local/bin/wrapped-cc/cc && \ + echo '#!/bin/sh' > /usr/local/bin/wrapped-cc/g++ && \ + echo 'exec /usr/bin/g++ -D__TIME__="\"0\"" -D__DATE__="\"0\"" -D__TIMESTAMP__="\"0\"" -Wno-builtin-macro-redefined "$@"' >> /usr/local/bin/wrapped-cc/g++ && \ + chmod +x /usr/local/bin/wrapped-cc/g++ + +ENV PATH="/usr/local/bin/wrapped-cc:$PATH" + +RUN ./DependencyInstaller.sh -base $options $constantBuildDir \ + && ./DependencyInstaller.sh -common $options $constantBuildDir \ + && rm -rf /tmp/installer /tmp/* /var/tmp/* /var/lib/apt/lists/* ARG fromImage diff --git a/docs/contrib/GitGuide.md b/docs/contrib/GitGuide.md new file mode 100644 index 0000000000..add267ee55 --- /dev/null +++ b/docs/contrib/GitGuide.md @@ -0,0 +1,3 @@ +# Git Quickstart + +If you have reached this file on GitHub - please refer to this [link](https://openroad-flow-scripts.readthedocs.io/en/latest/contrib/GitGuide.html) for latest documentation. diff --git a/docs/index.md b/docs/index.md index 04580bef51..fb37dc006e 100644 --- a/docs/index.md +++ b/docs/index.md @@ -111,6 +111,7 @@ You can select a design using either of the following methods: 2. Specify the design using the shell environment. For example: ```shell +# Make sure you are in ./flow make DESIGN_CONFIG=./designs/nangate45/swerv/config.mk # or export DESIGN_CONFIG=./designs/nangate45/swerv/config.mk diff --git a/docs/tutorials/FlowTutorial.md b/docs/tutorials/FlowTutorial.md index a9059e18c6..4f0c6ff9fc 100644 --- a/docs/tutorials/FlowTutorial.md +++ b/docs/tutorials/FlowTutorial.md @@ -187,15 +187,15 @@ minimum required timing constraint. create_clock -name core_clock -period 17.4 [get_ports {clk_i}] ``` -### Design Input Verilog +### Design Input SystemVerilog -The Verilog input files are located in `./designs/src/ibex/` +The SystemVerilog input files are located in `./designs/src/ibex_sv/` -The design is defined in `ibex_core.v` available -[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v). +The design is defined in `ibex_core.sv` available +[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/ibex_core.sv). Refer to the `ibex` design `README.md` -[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md). +[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/README.md). ## Running The Automated RTL-to-GDS Flow @@ -829,7 +829,7 @@ The `gcd` design synthesis results for area and speed optimizations are shown be |-----------------------|--------------------------------------|--------------------------------------| | `Number of wires` | 224 | 224 | | `Number of wire bits` | 270 | 270 | -| `Number of cells` | 234 | 234 | +| `Number of cells` | 234 | 234 | | `Chip area` | 2083.248000 | 2083.248000 | | `Final Design Area` | Design area 4295 u^2 6% utilization. | Design area 4074 u^2 6% utilization. | diff --git a/docs/user/BuildLocally.md b/docs/user/BuildLocally.md index 39e8e3b9f7..857235d288 100644 --- a/docs/user/BuildLocally.md +++ b/docs/user/BuildLocally.md @@ -4,8 +4,7 @@ The `setup.sh` script installs all of the dependencies, including OpenROAD dependencies, if they are not already installed. -Supported configurations are: CentOS 7, Ubuntu 20.04, Ubuntu 22.04, Ubuntu 22.04(aarch64), RHEL 8, -Debian 10 and Debian 11. +Supported configurations are: Ubuntu 20.04, Ubuntu 22.04, Ubuntu 22.04(aarch64), RHEL 8, RockyLinux 9 and Debian 11. ``` shell git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts @@ -33,6 +32,7 @@ up the environment. The `make` command runs from RTL-GDSII generation for defaul ``` shell source ./env.sh yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make @@ -54,3 +54,40 @@ Set up environment variables using `dev_env.sh`, then start Visual Studio Code. . ./dev_env.sh code tools/OpenROAD/ ``` + +## Build OpenROAD and run a few ORFS flows with Bazel + +Local use case: + +- Install Bazelisk and no other dependencies, no need to run `sudo ./setup.sh` +- Modify & build OpenROAD +- Test built OpenROAD with a few ORFS flows + +The Bazel support in OpenROAD and ORFS is work in progress and some Bazel experience is recommended before going spelunking in the Bazel builds. + +Contributions welcome! + +To build `designs/asap7/gcd:gcd_floorplan`: + + cd flow + (cd ../tools/OpenROAD && bazel build :openroad -c opt) && bazelisk build designs/asap7/gcd:gcd_floorplan + +Or to run all flows currently available in Bazel + + cd flow + (cd ../tools/OpenROAD && bazel build :openroad -c opt) && bazelisk build ... + +Note! ORFS uses the OpenROAD Bazel built binary in stop-gap way until OpenROAD has been switched to bzlmod, after which to build all flows becomes simpler as ORFS will build the requisite OpenROAD directly: + + cd flow + bazelisk build ... + +ORFS uses [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) to implement the flow and gets some depedencies, like yosys, from the Docker image. Over time, all dependencies should be built with Bazel and the dependency on the ORFS Docker image will be phased out. + +### Upgrading MODULE.bazel with the latest bazel-orfs and ORFS Docker image + +Run: + + bazelisk run @bazel-orfs//:bump + +Then commit MODULE.bazel and MODULE.bazel.lock. diff --git a/docs/user/BuildWithDocker.md b/docs/user/BuildWithDocker.md index 4825ebd5fd..82d532c567 100644 --- a/docs/user/BuildWithDocker.md +++ b/docs/user/BuildWithDocker.md @@ -79,6 +79,7 @@ Then, inside docker: ``` shell source ./env.sh yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make diff --git a/docs/user/BuildWithPrebuilt.md b/docs/user/BuildWithPrebuilt.md index 6774e81d5c..2fc27fd486 100644 --- a/docs/user/BuildWithPrebuilt.md +++ b/docs/user/BuildWithPrebuilt.md @@ -1,13 +1,13 @@ # Using Pre-built Binaries ## Install Klayout and Yosys -Please ensure the Klayout version (denoted with `klayoutVersion` variable) is consistent with the one used in [DependencyInstaller script](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/etc/DependencyInstaller.sh). +Please ensure the Klayout version (denoted with `klayoutVersion` variable) is consistent with the one used in [DependencyInstaller script](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/etc/DependencyInstaller.sh). Instructions for installing: - [Klayout>=0.28.8](https://www.klayout.de/build.html) - [Yosys>=0.39](https://github.com/YosysHQ/oss-cad-suite-build/blob/master/README.md#installation) -```{tip} Unfortunately KLayout maintainers do not provide Debian 10/11 compatible packages. You can follow the build-from-sources instruction (Version >=0.25) and Ubuntu 22 instructions [here](https://www.klayout.de/build.html#:~:text=Building%20KLayout%20on%20Linux%20(Version%20%3E%3D%200.25)). +```{tip} Unfortunately KLayout maintainers do not provide Debian 11 compatible packages. You can follow the build-from-sources instruction (Version >=0.25) and Ubuntu 22 instructions [here](https://www.klayout.de/build.html#:~:text=Building%20KLayout%20on%20Linux%20(Version%20%3E%3D%200.25)). ``` ## Install OpenROAD @@ -19,7 +19,7 @@ Thanks to [Precision Innovations](https://precisioninno.com/) for hosting and ma The following platforms are supported currently: - Ubuntu 20.04/22.04 -- Debian 10/11 +- Debian 11 Use the following steps to download: @@ -29,24 +29,13 @@ Step 2: Download the artifacts for your distribution. Step 3: Run the install command based on platform use package installer. For example Ubuntu 20.04 use: - + ```shell sudo apt install ./openroad_2.0_amd64-ubuntu20.04.deb ``` -## Install Klayout and Yosys -Please ensure the Klayout version (denoted with `klayoutVersion` variable) is consistent with the one used in [DependencyInstaller script](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/etc/DependencyInstaller.sh). - -Instructions for installing: -- [Klayout>=0.28.8](https://www.klayout.de/build.html) -- [Yosys>=0.39](https://github.com/YosysHQ/oss-cad-suite-build/blob/master/README.md#installation) - -```{tip} Unfortunately KLayout maintainers do not provide Debian 10/11 compatible packages. You can follow the build-from-sources instruction (Version >=0.25) and Ubuntu 22 instructions [here](https://www.klayout.de/build.html#:~:text=Building%20KLayout%20on%20Linux%20(Version%20%3E%3D%200.25)). -``` - - ## Verify Installation -You may clone the OpenROAD-flow-scripts repository non-recursively. +You may clone the OpenROAD-flow-scripts repository non-recursively. ``` git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git @@ -60,9 +49,10 @@ export OPENROAD_EXE=$(command -v openroad) export YOSYS_EXE=$(command -v yosys) # only if KLayout is built from source -export LD_LIBRARY_PATH="/bin:$PATH" +export LD_LIBRARY_PATH="/bin:$PATH" yosys -help +yosys -m slang -p "slang_version" openroad -help cd flow make diff --git a/docs/user/BuildWithWSL.md b/docs/user/BuildWithWSL.md index a8cda8458e..230ab7beba 100644 --- a/docs/user/BuildWithWSL.md +++ b/docs/user/BuildWithWSL.md @@ -2,7 +2,7 @@ Windows Subsystem for Linux, or WSL for short is a way for you to mount a Linux-based OS onto your Windows machine, allowing you to build OpenROAD-flow-scripts both locally and via Docker. ## Install WSL -Instructions to install WSL can be found [here](https://learn.microsoft.com/en-us/windows/wsl/install). You may use any kernel supported, such as: CentOS 7, Ubuntu 20.04, Ubuntu 22.04, RHEL 8, Debian 10 and Debian 11. +Instructions to install WSL can be found [here](https://learn.microsoft.com/en-us/windows/wsl/install). You may use any kernel supported, such as: Ubuntu 20.04, Ubuntu 22.04, RHEL 8, RockyLinux 9, Debian 11. We recommend that users follow the Docker build by continuing onto the guide below. However, if you wish to install locally, you may follow the build locally instructions [here](./BuildLocally.md). diff --git a/docs/user/DockerShell.md b/docs/user/DockerShell.md index f63d418495..1e930f962a 100644 --- a/docs/user/DockerShell.md +++ b/docs/user/DockerShell.md @@ -33,10 +33,10 @@ If you need to use a different Docker image than default, override by using the environment variable: ``` -OR_IMAGE=openroad/flow-centos7-builder:v1234 util/docker_shell make +OR_IMAGE=openroad/flow-ubuntu22.04-builder:v1234 util/docker_shell make ``` -If you have built your OpenROAD Docker image using prebuilt binaries, +If you have built your OpenROAD Docker image using prebuilt binaries, you might want to source custom paths for your modules as follows. ``` diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 5d84f396df..f0d7956f2b 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -1,10 +1,48 @@ -# Environment Variables for the OpenROAD Flow Scripts +# Variables for the OpenROAD Flow Scripts - -Environment variables are used in the OpenROAD flow to define various +Variables are used in the OpenROAD flow to define various platform, design and tool specific variables to allow finer control and -user overrides at various flow stages. These are defined in the -`config.mk` file located in the platform and design specific directories. +user overrides at various flow stages. + +These are normally defined in the `config.mk` file located in the platform and design-specific directories, but can also be defined on the command line or via environment variables. For example: + +- Command line: `make PLACE_DENSITY=0.5` +- Environment variable: `export PLACE_DENSITY=0.5` + +This works provided that `config.mk` has defined it as a default value using the `export PLACE_DENSITY?=0.4` syntax. + +The actual value used is determined by the priority rules set by `make`: + +1. **Makefile Definitions**: Variables defined in the `Makefile` or included files are used when they are defined using the no-override `=` operator, `export PLACE_DENSITY=0.4` syntax. The priority within the included files is the `DESIGN_CONFIG` file, then `Makefile` definitions and finally platform(PDK) defined variables. +2. **Command Line**: Variables defined on the command line take the highest priority in overriding defaults. +3. **Environment Variables**: Variables exported in the shell environment are used if not overridden by the command line. +4. **Default Values**: Variables defined with the `?=` operator in the `Makefile` are used only if the variable is not already defined elsewhere. + +## Effects of variables + +The variables for ORFS are not fully independent and can interact in complex ways. Small changes to a combination of variables can have large consequences, such as on macro placement, which can lead to vastly different quality of results. + +Due to the large number of variables, some of which are continuous and require long runtimes, other discrete, it is not feasible to perform an exhaustive end-to-end search for the best combination of variables. + +Instead, the following approaches are used to determine reasonable values, up to a point of diminishing returns: + +- **Experience**: Leveraging domain expertise to set initial values. +- **AI**: Using machine learning techniques to explore variable combinations. +- **Parameter Sweeps**: Testing a smaller subset of variables to identify optimal ranges. + +These values are then set in configuration files and kept under source control alongside the RTL input. + +## Types of variables + +Variables values are set in ORFS scripts or `config.mk` files and are kept in source control together with configuration files and RTL. + +It is an ongoing effort to move variables upwards in the categories below. + +| Category | Definition | User Involvement | Examples | Automation Potential | Notes | +|--------------------|----------------------------------------------------------------------------|----------------------------------------|-----------------------------------------|-----------------------------|-----------------------------------------------------------------------| +| **Trivial** | Automatically determined by tool with near-optimal results. | None (unless debugging) | Buffer sizing, default layers | **High** – can be hidden | Best if invisible; surfaced only in debug or verbose mode. | +| **Easy** | Requires input, but easy to tune using reports or visuals. | Moderate – copy/edit from reports | `PLACE_DENSITY` | **Medium–High** | Smooth response curves, intuitive tuning. | +| **Complex** | Small changes in values may result in large effects. | High – requires multiple runs/sweeps | `CTS_DISTANCE_BUF`, small changes can have large effects on skew and quality of results. Small changes to independent inputs, such as RTL, can invalidate earlier "good values". | **Low–Medium** | Needs scripted sweeps and statistical evaluation. | ## Platform @@ -20,7 +58,7 @@ variable. For OpenROAD Flow Scripts we have the following public platforms: - `nangate45` - `asap7` -## Platform Specific Environment Variables +## Platform Specific Variables The table below lists the complete set of variables used in each of the @@ -50,145 +88,166 @@ configuration file. ## Variables in alphabetic order -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | -| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| | -| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | | -| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | | -| ABC_LOAD_IN_FF| During synthesis set_load value used.| | | -| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | | -| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | | -| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | | -| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | | -| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | | -| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | | -| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | | -| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | | -| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | | -| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| | -| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| | -| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | | -| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| | | -| CORE_UTILIZATION| The core utilization percentage (0-100).| | | -| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | | -| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | | -| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | | -| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| | -| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| | -| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | | -| DESIGN_NAME| The name of the top-level module of the design.| | | -| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | | -| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| | -| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | | -| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| | -| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | | -| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | | -| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | | -| DONT_USE_LIBS| Set liberty files as `dont_use`.| | | -| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| | -| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| | -| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| | -| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | | -| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | | -| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | | -| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | | -| GDS_FILES| Path to platform GDS files.| | | -| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| | -| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | | -| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| | -| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| | -| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| | -| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| | -| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan. This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at designs target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running times) when exploring different parameter settings.| 0| | -| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | | -| IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| | | -| IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| | | -| IR_DROP_LAYER| Default metal layer to report IR drop.| | | -| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | | -| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | | -| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | | -| MACRO_BLOCKAGE_HALO| Blockage width overridden from default calculation.| | | -| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | -| MACRO_HALO_X| Set macro halo for x-direction. Only available for ASAP7 PDK.| | | -| MACRO_HALO_Y| Set macro halo for y-direction. Only available for ASAP7 PDK.| | | -| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | | -| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | | -| MACRO_PLACE_CHANNEL| Horizontal/vertical channel width between macros (microns). Used by automatic macro placement. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro.| | | -| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | | -| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | | -| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | | -| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| | -| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | -| MAX_UNGROUP_SIZE| For hierarchical synthesis, we ungroup modules of larger area than given by this variable. The default value is > 0 platform specific.| | | -| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | | -| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | | -| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | | -| PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| | | -| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | | -| PLACE_PINS_ARGS| Arguments to place_pins| | | -| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | | -| PLATFORM| Specifies process design kit or technology node to be used.| | | -| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | | -| PRESERVE_CELLS| Mark modules to keep from getting removed in flattening.| | | -| PROCESS| Technology node or process in use.| | | -| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | | -| RCX_RULES| RC Extraction rules file path.| | | -| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| | -| REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1.| | yes| -| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | | -| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | | -| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| | -| RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| 0| | -| RESYNTH_TIMING_RECOVER| Enable re-synthesis for timing optimization.| 0| | -| ROUTING_LAYER_ADJUSTMENT| Default routing layer adjustment| 0.5| | -| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| | -| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | | -| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| | -| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| | -| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| | -| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| | -| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| | -| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| | -| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | | -| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| | -| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| | -| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | | -| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| | -| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| | -| SC_LEF| Path to technology standard cell LEF file.| | | -| SDC_FILE| The path to design constraint (SDC) file.| | | -| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SEAL_GDS| Seal macro to place around the design.| | | -| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack).| 0| | -| SET_RC_TCL| Metal & Via RC definition file path.| | | -| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | | -| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | | -| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| | -| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | | -| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | | -| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | | -| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | | -| SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| | -| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | -| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | -| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | | -| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | | -| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | | -| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | | -| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | | -| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| | -| USE_FILL| Whether to perform metal density filling.| 0| | -| VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | | -| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | -| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | | +| Variable | Description | Default | +| --- | --- | --- | +| ABC_AREA| Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.| 0| +| ABC_CLOCK_PERIOD_IN_PS| Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`.| | +| ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| | +| ABC_LOAD_IN_FF| During synthesis set_load value used.| | +| ABSTRACT_SOURCE| Which .odb file to use to create abstract| | +| ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| | +| ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| | +| ADDITIONAL_GDS| Hardened macro GDS files listed here.| | +| ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| | +| ADDITIONAL_LIBS| Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file.| | +| BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | +| CAP_MARGIN| Specifies a capacitance margin when fixing max capacitance violations. This option allows you to overfix.| | +| CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| | +| CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0| +| CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0| +| CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| | +| CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0| +| CORE_MARGIN| The margin between the core area and die area, specified in microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. This variable is ignored if `CORE_UTILIZATION` is undefined.| 1.0| +| CORE_UTILIZATION| The core utilization percentage (0-100).| | +| CORNER| PVT corner library selection. Only available for ASAP7 and GF180 PDKs.| | +| CTS_ARGS| Override `clock_tree_synthesis` arguments.| | +| CTS_BUF_DISTANCE| Distance (in microns) between buffers.| | +| CTS_BUF_LIST| List of cells used to construct the clock tree. Overrides buffer inference.| | +| CTS_CLUSTER_DIAMETER| Maximum diameter (in microns) of sink cluster.| 20| +| CTS_CLUSTER_SIZE| Maximum number of sinks per cluster.| 50| +| CTS_LIB_NAME| Name of the Liberty library to use in selecting the clock buffers.| | +| CTS_SNAPSHOT| Creates ODB/SDC files prior to clock net and setup/hold repair.| | +| DESIGN_NAME| The name of the top-level module of the design.| | +| DESIGN_NICKNAME| DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design.| | +| DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| +| DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | +| DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| +| DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| | +| DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | +| DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| | +| DONT_USE_LIBS| Set liberty files as `dont_use`.| | +| DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1| +| EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| | +| ENABLE_DPO| Enable detail placement with improve_placement feature.| 1| +| EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0| +| FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | +| FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | +| FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | +| FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | +| FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| +| GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | +| GDS_FILES| Path to platform GDS files.| | +| GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| +| GLOBAL_PLACEMENT_ARGS| Use additional tuning parameters during global placement other than default args defined in global_place.tcl.| | +| GLOBAL_ROUTE_ARGS| Replaces default arguments for global route.| -congestion_iterations 30 -congestion_report_iter_step 5 -verbose| +| GND_NETS_VOLTAGES| Used for IR Drop calculation.| | +| GPL_ROUTABILITY_DRIVEN| Specifies whether the placer should use routability driven placement.| 1| +| GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| 1| +| GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| 1| +| HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. Exiting timing repair early is useful in exploration where the .sdc has a fixed clock period at the design's target clock period and where HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. When an ideal clock is used, that is before CTS, a clock insertion delay of 0 is used in timing paths. This creates a mismatch between macros that have a .lib file from after CTS, when the clock is propagated. To mitigate this, OpenSTA will use subtract the clock insertion delay of macros when calculating timing with ideal clock. Provided that min_clock_tree_path and max_clock_tree_path are in the .lib file, which is the case for macros built with OpenROAD. This is less accurate than if OpenROAD had created a placeholder clock tree for timing estimation purposes prior to CTS. There will inevitably be inaccuracies in the timing calculation prior to CTS. Use a slack margin that is low enough, even negative, to avoid overrepair. Inaccuracies in the timing prior to CTS can also lead to underrepair, but there no obvious and simple way to avoid underrapir in these cases. Overrepair can lead to excessive runtimes in repair or too much buffering being added, which can present itself as congestion of hold cells or buffer cells. Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration when trying to find the minimum clock period for a design. The SDC_FILE for a design can be quite complicated and instead of modifying the clock period in the SDC_FILE, which can be non-trivial, the clock period can be fixed at the target frequency and the SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible current minimum clock period.| 0| +| IO_CONSTRAINTS| File path to the IO constraints .tcl file.| | +| IO_PLACER_H| A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die).| | +| IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| | +| IR_DROP_LAYER| Default metal layer to report IR drop.| | +| KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| | +| LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| | +| LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | +| MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | +| MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | +| MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| | +| MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| | +| MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| | +| MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_ROWS_HALO_Y| Vertical distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| | +| MACRO_WRAPPERS| The wrapper file that replaces existing macros with their wrapped version.| | +| MAKE_TRACKS| Tcl file that defines add routing tracks to a floorplan.| | +| MATCH_CELL_FOOTPRINT| Enforce sizing operations to only swap cells that have the same layout boundary.| 0| +| MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | +| MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | +| MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | +| PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| | +| PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| | +| PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| | +| PLACE_PINS_ARGS| Arguments to place_pins| | +| PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | +| PLATFORM| Specifies process design kit or technology node to be used.| | +| PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| | +| POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | +| PRE_GLOBAL_ROUTE_TCL| Specifies a Tcl script with commands to run before global route.| | +| PROCESS| Technology node or process in use.| | +| PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | +| RCX_RULES| RC Extraction rules file path.| | +| RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| +| REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | +| REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | +| REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | +| REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| +| ROUTING_LAYER_ADJUSTMENT| Adjusts routing layer capacities to manage congestion and improve detailed routing. High values ease detailed routing but risk excessive detours and long global routing times, while low values reduce global routing failure but can complicate detailed routing. The global routing running time normally reduces dramatically (entirely design specific, but going from hours to minutes has been observed) when the value is low (such as 0.10). Sometimes, global routing will succeed with lower values and fail with higher values. Exploring results with different values can help shed light on the problem. Start with a too low value, such as 0.10, and bisect to value that works by doing multiple global routing runs. As a last resort, `make global_route_issue` and using the tools/OpenROAD/etc/deltaDebug.py can be useful to debug global routing errors. If there is something specific that is impossible to route, such as a clock line over a macro, global routing will terminate with DRC errors routes that could have been routed were it not for the specific impossible routes. deltaDebug.py should weed out the possible routes and leave a minimal failing case that pinpoints the problem.| 0.5| +| RTLMP_AREA_WT| Weight for the area of the current floorplan.| 0.1| +| RTLMP_ARGS| Overrides all other RTL macro placer arguments.| | +| RTLMP_BOUNDARY_WT| Weight for the boundary or how far the hard macro clusters are from boundaries.| 50.0| +| RTLMP_DEAD_SPACE| Specifies the target dead space percentage, which influences the utilization of a cluster.| 0.05| +| RTLMP_FENCE_LX| Defines the lower left X coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_LY| Defines the lower left Y coordinate for the global fence bounding box in microns.| 0.0| +| RTLMP_FENCE_UX| Defines the upper right X coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_FENCE_UY| Defines the upper right Y coordinate for the global fence bounding box in microns.| 100000000.0| +| RTLMP_MAX_INST| Maximum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MAX_LEVEL| Maximum depth of the physical hierarchy tree.| 2| +| RTLMP_MAX_MACRO| Maximum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_AR| Specifies the minimum aspect ratio (height/width).| 0.33| +| RTLMP_MIN_INST| Minimum number of standard cells in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_MIN_MACRO| Minimum number of macros in a cluster. If unset, rtl_macro_placer will calculate a value based on the design attributes.| | +| RTLMP_NOTCH_WT| Weight for the notch, or the existence of dead space that cannot be used for placement and routing.| 10.0| +| RTLMP_OUTLINE_WT| Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.| 100.0| +| RTLMP_RPT_DIR| Path to the directory where reports are saved.| | +| RTLMP_SIGNATURE_NET_THRESHOLD| Minimum number of connections between two clusters to be identified as connected.| 50| +| RTLMP_WIRELENGTH_WT| Weight for half-perimiter wirelength.| 100.0| +| RULES_JSON| json files with the metrics baseline regression rules. In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, but ORFS does not mandate the users source directory layout and this can be placed elsewhere when the user sets up an ORFS config.mk or from bazel-orfs.| | +| RUN_LOG_NAME_STEM| Stem of the log file name, the log file will be named `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.| run| +| RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | +| SC_LEF| Path to technology standard cell LEF file.| | +| SDC_FILE| The path to design constraint (SDC) file.| | +| SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SEAL_GDS| Seal macro to place around the design.| | +| SETUP_REPAIR_SEQUENCE| Specifies the sequence of moves to do in repair_timing -setup. This should be a string of move keywords separated by commas such as the default when not used: "unbuffer,sizedown,sizeup,swap,buffer,clone,split".| | +| SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0| +| SET_RC_TCL| Metal & Via RC definition file path.| | +| SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| | +| SKIP_DETAILED_ROUTE| Skips detailed route.| 0| +| SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| | +| SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0| +| SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| | +| SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| | +| SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | +| SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | +| SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| | +| SYNTH_ARGS| Optional synthesis variables for yosys.| | +| SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | +| SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| | +| SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | +| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | +| SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| +| SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| +| SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | +| SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| +| SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| +| SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | +| SYNTH_RETIME_MODULES| List of modules to apply retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. This is an experimental option and may cause adverse effects.| | +| SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | +| TAPCELL_TCL| Path to Endcap and Welltie cells file.| | +| TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | +| TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | +| TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| | +| TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | +| TIE_SEPARATION| Distance separating tie high/low instances from the load.| 0| +| TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| +| USE_FILL| Whether to perform metal density filling.| 0| +| VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | +| VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | +| VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | +| VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | +| YOSYS_FLAGS| Flags to pass to yosys.| -v 3| ## synth variables - [ABC_AREA](#ABC_AREA) @@ -198,19 +257,28 @@ configuration file. - [ADDER_MAP_FILE](#ADDER_MAP_FILE) - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE) - [LATCH_MAP_FILE](#LATCH_MAP_FILE) -- [MAX_UNGROUP_SIZE](#MAX_UNGROUP_SIZE) - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) -- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER) -- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER) - [SDC_FILE](#SDC_FILE) - [SDC_GUT](#SDC_GUT) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) +- [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES) +- [SYNTH_CANONICALIZE_TCL](#SYNTH_CANONICALIZE_TCL) - [SYNTH_GUT](#SYNTH_GUT) +- [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND) - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL) +- [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES) +- [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS) +- [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE) +- [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES) +- [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES) +- [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS) - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [VERILOG_DEFINES](#VERILOG_DEFINES) - [VERILOG_FILES](#VERILOG_FILES) - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) +- [YOSYS_FLAGS](#YOSYS_FLAGS) ## floorplan variables @@ -223,21 +291,18 @@ configuration file. - [FLOORPLAN_DEF](#FLOORPLAN_DEF) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IO_CONSTRAINTS](#IO_CONSTRAINTS) -- [IO_PLACER_H](#IO_PLACER_H) -- [IO_PLACER_V](#IO_PLACER_V) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) -- [MACRO_HALO_X](#MACRO_HALO_X) -- [MACRO_HALO_Y](#MACRO_HALO_Y) - [MACRO_PLACEMENT](#MACRO_PLACEMENT) - [MACRO_PLACEMENT_TCL](#MACRO_PLACEMENT_TCL) -- [MACRO_PLACE_CHANNEL](#MACRO_PLACE_CHANNEL) - [MACRO_PLACE_HALO](#MACRO_PLACE_HALO) +- [MACRO_ROWS_HALO_X](#MACRO_ROWS_HALO_X) +- [MACRO_ROWS_HALO_Y](#MACRO_ROWS_HALO_Y) - [MACRO_WRAPPERS](#MACRO_WRAPPERS) - [MAKE_TRACKS](#MAKE_TRACKS) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [PDN_TCL](#PDN_TCL) - [PLACE_DENSITY](#PLACE_DENSITY) -- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) +- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON) - [PLACE_SITE](#PLACE_SITE) - [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS) - [RTLMP_AREA_WT](#RTLMP_AREA_WT) @@ -259,18 +324,24 @@ configuration file. - [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) - [RTLMP_SIGNATURE_NET_THRESHOLD](#RTLMP_SIGNATURE_NET_THRESHOLD) - [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_LAST_GASP](#SKIP_LAST_GASP) - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) - [TAPCELL_TCL](#TAPCELL_TCL) +- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) +- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [TIE_SEPARATION](#TIE_SEPARATION) - [TNS_END_PERCENT](#TNS_END_PERCENT) ## place variables - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) +- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO) - [FLOORPLAN_DEF](#FLOORPLAN_DEF) - [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN) - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) @@ -281,19 +352,21 @@ configuration file. - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [PLACE_DENSITY](#PLACE_DENSITY) +- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON) - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) -- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT) -- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT) +- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS) ## cts variables - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [CTS_ARGS](#CTS_ARGS) - [CTS_BUF_DISTANCE](#CTS_BUF_DISTANCE) +- [CTS_BUF_LIST](#CTS_BUF_LIST) - [CTS_CLUSTER_DIAMETER](#CTS_CLUSTER_DIAMETER) - [CTS_CLUSTER_SIZE](#CTS_CLUSTER_SIZE) +- [CTS_LIB_NAME](#CTS_LIB_NAME) - [CTS_SNAPSHOT](#CTS_SNAPSHOT) - [DETAILED_METRICS](#DETAILED_METRICS) - [EQUIVALENCE_CHECK](#EQUIVALENCE_CHECK) @@ -302,6 +375,7 @@ configuration file. - [POST_CTS_TCL](#POST_CTS_TCL) - [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) @@ -318,8 +392,10 @@ configuration file. - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) +- [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING) - [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR) @@ -338,23 +414,30 @@ configuration file. - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) ## final variables - [ADDITIONAL_GDS](#ADDITIONAL_GDS) +- [GDS_ALLOW_EMPTY](#GDS_ALLOW_EMPTY) - [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) ## generate_abstract variables - [ABSTRACT_SOURCE](#ABSTRACT_SOURCE) +## test variables + +- [RULES_JSON](#RULES_JSON) + ## All stages variables @@ -377,6 +460,7 @@ configuration file. - [ENABLE_DPO](#ENABLE_DPO) - [FASTROUTE_TCL](#FASTROUTE_TCL) - [FILL_CONFIG](#FILL_CONFIG) +- [FLOW_VARIANT](#FLOW_VARIANT) - [GDS_FILES](#GDS_FILES) - [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE) - [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS) @@ -385,18 +469,20 @@ configuration file. - [KLAYOUT_TECH_FILE](#KLAYOUT_TECH_FILE) - [LIB_FILES](#LIB_FILES) - [MACRO_EXTENSION](#MACRO_EXTENSION) -- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON) - [PLATFORM](#PLATFORM) -- [PRESERVE_CELLS](#PRESERVE_CELLS) +- [PLATFORM_TCL](#PLATFORM_TCL) - [PROCESS](#PROCESS) - [RCX_RULES](#RCX_RULES) - [RECOVER_POWER](#RECOVER_POWER) - [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER) +- [RUN_LOG_NAME_STEM](#RUN_LOG_NAME_STEM) +- [RUN_SCRIPT](#RUN_SCRIPT) - [SC_LEF](#SC_LEF) - [SEAL_GDS](#SEAL_GDS) - [SET_RC_TCL](#SET_RC_TCL) - [SLEW_MARGIN](#SLEW_MARGIN) - [SYNTH_ARGS](#SYNTH_ARGS) +- [SYNTH_HIER_SEPARATOR](#SYNTH_HIER_SEPARATOR) - [TAP_CELL_NAME](#TAP_CELL_NAME) - [TECH_LEF](#TECH_LEF) - [USE_FILL](#USE_FILL) diff --git a/docs/user/InstructionsForAutoTuner.md b/docs/user/InstructionsForAutoTuner.md index 7b43950e05..2cbd5bf339 100644 --- a/docs/user/InstructionsForAutoTuner.md +++ b/docs/user/InstructionsForAutoTuner.md @@ -27,10 +27,6 @@ We have provided two convenience scripts, `./installer.sh` and `./setup.sh` that works in Python3.8 for installation and configuration of AutoTuner, as shown below: -```{note} -Make sure you run the following commands in the ORFS root directory. -``` - ```shell # Install prerequisites ./tools/AutoTuner/installer.sh @@ -104,7 +100,7 @@ For Global Routing parameters that are set on `fastroute.tcl` you can use: ### General Information -The `distributed.py` script located in `./tools/AutoTuner/src/autotuner` uses [Ray's](https://docs.ray.io/en/latest/index.html) job scheduling and management to +The `autotuner.distributed` module uses [Ray's](https://docs.ray.io/en/latest/index.html) job scheduling and management to fully utilize available hardware resources from a single server configuration, on-premise or over the cloud with multiple CPUs. @@ -115,38 +111,53 @@ The two modes of operation: The `sweep` mode is useful when we want to isolate or test a single or very few parameters. On the other hand, `tune` is more suitable for finding the best combination of a complex and large number of flow -parameters. Both modes rely on user-specified search space that is -defined by a `.json` file, they use the same syntax and format, -though some features may not be available for sweeping. +parameters. ```{note} The order of the parameters matter. Arguments `--design`, `--platform` and `--config` are always required and should precede *mode*. ``` +```{note} +The following commands should be run from `./tools/AutoTuner`. +``` + #### Tune only -* AutoTuner: `python3 distributed.py tune -h` +* AutoTuner: `openroad_autotuner tune -h` Example: ```shell -python3 distributed.py --design gcd --platform sky130hd \ - --config ../../../../flow/designs/sky130hd/gcd/autotuner.json \ +openroad_autotuner --design gcd --platform sky130hd \ + --config ../../flow/designs/sky130hd/gcd/autotuner.json \ tune --samples 5 ``` #### Sweep only -* Parameter sweeping: `python3 distributed.py sweep -h` +* Parameter sweeping: `openroad_autotuner sweep -h` Example: ```shell -python3 distributed.py --design gcd --platform sky130hd \ - --config distributed-sweep-example.json \ +openroad_autotuner --design gcd --platform sky130hd \ + --config src/autotuner/distributed-sweep-example.json \ sweep ``` +#### Plot images + +After running an AutoTuner experiment, you can generate a graph to understand the results better. +The graph will show the progression of one metric (see list below) over the execution of the experiment. + +- QoR +- Runtime per trial +- Clock Period +- Worst slack + +```shell +python3 utils/plot.py --results_dir +``` ### Google Cloud Platform (GCP) distribution with Ray diff --git a/env.sh b/env.sh index 3a279ea2f8..563c003a81 100755 --- a/env.sh +++ b/env.sh @@ -1,24 +1,25 @@ -if [[ "$OSTYPE" == "darwin"* ]]; then - DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]}"))" -else - DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]}"))" -fi +#!/usr/bin/env bash +function __setpaths() { + if [[ "$OSTYPE" == "darwin"* ]]; then + DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]:-${(%):-%x}}"))" + else + DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}"))" + fi -if [ -f /opt/rh/rh-python38/enable ]; then - source /opt/rh/rh-python38/enable -fi + export OPENROAD=${DIR}/tools/OpenROAD + echo "OPENROAD: ${OPENROAD}" -export OPENROAD=${DIR}/tools/OpenROAD -echo "OPENROAD: ${OPENROAD}" + # Set user paths and environment variables here, + # developer settings go in ./dev_env.sh + export PATH=${DIR}/tools/install/OpenROAD/bin:$PATH + export PATH=${DIR}/tools/install/yosys/bin:$PATH -export PATH=${DIR}/tools/install/OpenROAD/bin:$PATH -export PATH=${DIR}/tools/install/yosys/bin:$PATH -export PATH=${DIR}/dependencies/bin:$PATH + if [[ "$OSTYPE" == "darwin"* ]]; then + export PATH="/Applications/KLayout/klayout.app/Contents/MacOS:$PATH" + export PATH="$(brew --prefix bison)/bin:$(brew --prefix flex)/bin:$(brew --prefix tcl-tk)/bin:$PATH" + fi -if [[ "$OSTYPE" == "darwin"* ]]; then - export PATH="/Applications/KLayout/klayout.app/Contents/MacOS:$PATH" - export PATH="$(brew --prefix bison)/bin:$(brew --prefix flex)/bin:$(brew --prefix tcl-tk)/bin:$PATH" - export CMAKE_PREFIX_PATH="$(brew --prefix or-tools)" -fi - -export FLOW_HOME=$DIR/flow + export FLOW_HOME=$DIR/flow +} +__setpaths +unset -f __setpaths diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 53a50aba0d..c0927426d7 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -10,7 +10,7 @@ else fi # package versions -klayoutVersion=0.28.8 +klayoutVersion=0.28.17 verilatorVersion=5.026 _versionCompare() { @@ -29,7 +29,7 @@ _installCommon() { source /opt/rh/rh-python38/enable set -u fi - local pkgs="pandas numpy firebase_admin click pyyaml" + local pkgs="pandas numpy firebase_admin click pyyaml yamlfix" if [[ $(id -u) == 0 ]]; then pip3 install --no-cache-dir -U $pkgs else @@ -94,7 +94,7 @@ _installUbuntuCleanUp() { } _installKlayoutDependenciesUbuntuAarch64() { - echo "Installing Klayout dependancies" + echo "Installing Klayout dependencies" export DEBIAN_FRONTEND=noninteractive apt-get -y update apt-get -y install build-essential \ @@ -116,6 +116,7 @@ _installUbuntuPackages() { help2man \ libfl-dev \ libfl2 \ + libgit2-dev \ libgoogle-perftools-dev \ libqt5multimediawidgets5 \ libqt5opengl5 \ @@ -133,6 +134,17 @@ _installUbuntuPackages() { zlib1g \ zlib1g-dev + packages=() + # Choose libstdc++ version + if _versionCompare $1 -ge 25.04; then + packages+=("libstdc++-15-dev") + elif _versionCompare $1 -ge 24.04; then + packages+=("libstdc++-14-dev") + elif _versionCompare $1 -ge 22.10; then + packages+=("libstdc++-12-dev") + fi + apt-get install -y --no-install-recommends ${packages[@]} + # install KLayout if [[ $1 == "rodete" ]]; then apt-get -y install --no-install-recommends klayout python3-pandas @@ -158,9 +170,9 @@ _installUbuntuPackages() { fi else if [[ $1 == 20.04 ]]; then - klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135 + klayoutChecksum=f78d41edf5bcfa5f1990bde1a9307e9e else - klayoutChecksum=db751264399706a23d20455bb7624264 + klayoutChecksum=54748a49e1ab53e14cf5bf95feb2f25a fi wget https://www.klayout.org/downloads/Ubuntu-${1%.*}/klayout_${klayoutVersion}-1_amd64.deb md5sum -c <(echo "${klayoutChecksum} klayout_${klayoutVersion}-1_amd64.deb") || exit 1 @@ -223,7 +235,7 @@ _help() { cat <] # Installs all of OpenROAD's dependencies no # need to run -base or -common. Requires # privileged access. @@ -260,7 +272,7 @@ OR_INSTALLER_ARGS="-eqy" # default prefix PREFIX="" # default option -option="all" +option="none" # default isLocal isLocal="false" constantBuildDir="false" @@ -272,16 +284,20 @@ while [ "$#" -gt 0 ]; do -h|-help) _help 0 ;; + -all) + if [[ "${option}" != "none" ]]; then + echo "WARNING: previous argument -${option} will be overwritten with -all." >&2 + fi + option="all" + ;; -base) - OR_INSTALLER_ARGS="${OR_INSTALLER_ARGS} -base" - if [[ "${option}" != "all" ]]; then + if [[ "${option}" != "none" ]]; then echo "WARNING: previous argument -${option} will be overwritten with -base." >&2 fi option="base" ;; -common) - OR_INSTALLER_ARGS="${OR_INSTALLER_ARGS} -common" - if [[ "${option}" != "all" ]]; then + if [[ "${option}" != "none" ]]; then echo "WARNING: previous argument -${option} will be overwritten with -common." >&2 fi option="common" @@ -309,6 +325,13 @@ while [ "$#" -gt 0 ]; do shift 1 done +if [[ "${option}" == "none" ]]; then + echo "You must use one of: -all|-base|-common" >&2 + _help +fi + +OR_INSTALLER_ARGS="${OR_INSTALLER_ARGS} -${option}" + platform="$(uname -s)" case "${platform}" in "Linux" ) diff --git a/etc/DockerHelper.sh b/etc/DockerHelper.sh index 3eff831853..7d168b2ad0 100755 --- a/etc/DockerHelper.sh +++ b/etc/DockerHelper.sh @@ -33,6 +33,7 @@ usage: $0 [CMD] [OPTIONS] -password=PASSWORD Password to loging at the docker registry. -ci Install CI tools in image -dry-run Do not push images to the repository + -push-latest Push the latest image to the repository -no-constant-build-dir Do not use constant build directory -h -help Show this message and exits @@ -136,10 +137,22 @@ _push() { orfsTag=${org}/orfs:${tag} echo "Renaming docker image: ${builderTag} -> ${orfsTag}" ${DOCKER_CMD} tag ${builderTag} ${orfsTag} + if [[ "${dryRun}" == 1 ]]; then echo "[DRY-RUN] ${DOCKER_CMD} push ${orfsTag}" + if [[ "${pushLatest}" == 1 ]]; then + echo "[DRY-RUN] ${DOCKER_CMD} tag ${orfsTag} \"${org}/orfs:latest\"" + echo "[DRY-RUN] ${DOCKER_CMD} push \"${org}/orfs:latest\"" + fi else ${DOCKER_CMD} push ${orfsTag} + + # Only tag and push as latest if requested + if [[ "${pushLatest}" == 1 ]]; then + ${DOCKER_CMD} tag ${orfsTag} "${org}/orfs:latest" + ${DOCKER_CMD} push "${org}/orfs:latest" + echo "Tagged and pushed ${org}/orfs:latest" + fi fi fi } @@ -174,6 +187,7 @@ numThreads="-1" tag="" options="" dryRun=0 +pushLatest=0 while [ "$#" -gt 0 ]; do case "${1}" in @@ -186,6 +200,9 @@ while [ "$#" -gt 0 ]; do -dry-run ) dryRun=1 ;; + -push-latest ) + pushLatest=1 + ;; -os=* ) os="${1#*=}" ;; diff --git a/flake.lock b/flake.lock new file mode 100644 index 0000000000..05d03ea8bb --- /dev/null +++ b/flake.lock @@ -0,0 +1,171 @@ +{ + "nodes": { + "flake-utils": { + "inputs": { + "systems": "systems" + }, + "locked": { + "lastModified": 1731533236, + "narHash": "sha256-l0KFg5HjrsfsO/JpG+r7fRrqm12kzFHyUHqHCVpMMbI=", + "owner": "numtide", + "repo": "flake-utils", + "rev": "11707dc2f618dd54ca8739b309ec4fc024de578b", + "type": "github" + }, + "original": { + "owner": "numtide", + "repo": "flake-utils", + "type": "github" + } + }, + "flake-utils_2": { + "inputs": { + "systems": "systems_2" + }, + "locked": { + "lastModified": 1705309234, + "narHash": "sha256-uNRRNRKmJyCRC/8y1RqBkqWBLM034y4qN7EprSdmgyA=", + "owner": "numtide", + "repo": "flake-utils", + "rev": "1ef2e671c3b0c19053962c07dbda38332dcebf26", + "type": "github" + }, + "original": { + "owner": "numtide", + "repo": "flake-utils", + "type": "github" + } + }, + "nixpkgs": { + "locked": { + "lastModified": 1741851582, + "narHash": "sha256-cPfs8qMccim2RBgtKGF+x9IBCduRvd/N5F4nYpU0TVE=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "6607cf789e541e7873d40d3a8f7815ea92204f32", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "nixpkgs_2": { + "locked": { + "lastModified": 1724316499, + "narHash": "sha256-Qb9MhKBUTCfWg/wqqaxt89Xfi6qTD3XpTzQ9eXi3JmE=", + "owner": "nixos", + "repo": "nixpkgs", + "rev": "797f7dc49e0bc7fab4b57c021cdf68f595e47841", + "type": "github" + }, + "original": { + "owner": "nixos", + "ref": "nixos-24.05", + "repo": "nixpkgs", + "type": "github" + } + }, + "nixpkgs_3": { + "locked": { + "lastModified": 1708807242, + "narHash": "sha256-sRTRkhMD4delO/hPxxi+XwLqPn8BuUq6nnj4JqLwOu0=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "73de017ef2d18a04ac4bfd0c02650007ccb31c2a", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "openroad": { + "inputs": { + "nixpkgs": "nixpkgs_2" + }, + "locked": { + "lastModified": 1741801451, + "narHash": "sha256-fzWCeq0o6vx8/GoFcOtnaIENes3jXzNk9qfWnIaxtHI=", + "ref": "refs/heads/master", + "rev": "ec1bf1a13902813b722f8341c432cd09714d9e55", + "revCount": 27845, + "submodules": true, + "type": "git", + "url": "https://github.com/The-OpenROAD-Project/OpenROAD" + }, + "original": { + "rev": "ec1bf1a13902813b722f8341c432cd09714d9e55", + "submodules": true, + "type": "git", + "url": "https://github.com/The-OpenROAD-Project/OpenROAD" + } + }, + "root": { + "inputs": { + "flake-utils": "flake-utils", + "nixpkgs": "nixpkgs", + "openroad": "openroad", + "yosys": "yosys" + } + }, + "systems": { + "locked": { + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } + }, + "systems_2": { + "locked": { + "lastModified": 1681028828, + "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", + "owner": "nix-systems", + "repo": "default", + "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "type": "github" + }, + "original": { + "owner": "nix-systems", + "repo": "default", + "type": "github" + } + }, + "yosys": { + "inputs": { + "flake-utils": "flake-utils_2", + "nixpkgs": "nixpkgs_3" + }, + "locked": { + "lastModified": 1741764697, + "narHash": "sha256-5jQ9l0cyRhEI4UFInW3kqw5B+mdLFr66nfG716rO454=", + "ref": "refs/heads/master", + "rev": "c4b5190229616f7ebf8197f43990b4429de3e420", + "revCount": 14791, + "submodules": true, + "type": "git", + "url": "https://github.com/The-OpenROAD-Project/yosys" + }, + "original": { + "rev": "c4b5190229616f7ebf8197f43990b4429de3e420", + "submodules": true, + "type": "git", + "url": "https://github.com/The-OpenROAD-Project/yosys" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/flake.nix b/flake.nix new file mode 100644 index 0000000000..5d95e01629 --- /dev/null +++ b/flake.nix @@ -0,0 +1,42 @@ +{ + inputs = { + nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; + flake-utils.url = "github:numtide/flake-utils"; + openroad = { + type = "git"; + url = "https://github.com/The-OpenROAD-Project/OpenROAD"; + submodules = true; + rev = "ec1bf1a13902813b722f8341c432cd09714d9e55"; + }; + yosys = { + type = "git"; + url = "https://github.com/The-OpenROAD-Project/yosys"; + submodules = true; + rev = "c4b5190229616f7ebf8197f43990b4429de3e420"; + }; + }; + outputs = { self, nixpkgs, flake-utils, openroad, yosys }: flake-utils.lib.eachDefaultSystem ( + system: + let + pkgs = nixpkgs.legacyPackages.${system}; + in { + devShells.default = pkgs.mkShell { + buildInputs = [ + openroad.packages.${system}.default + yosys.packages.${system}.default + pkgs.time + pkgs.klayout + pkgs.verilator + pkgs.perl + pkgs.python3 + pkgs.python3Packages.pandas + pkgs.python3Packages.numpy + pkgs.python3Packages.firebase-admin + pkgs.python3Packages.click + pkgs.python3Packages.pyyaml + pkgs.python3Packages.yamlfix + ]; + }; + } + ); +} diff --git a/flow/.bazelversion b/flow/.bazelversion deleted file mode 100644 index 468c41f93c..0000000000 --- a/flow/.bazelversion +++ /dev/null @@ -1 +0,0 @@ -7.2.1 \ No newline at end of file diff --git a/flow/.gitignore b/flow/.gitignore index 3073067287..a08f9fc5cb 100644 --- a/flow/.gitignore +++ b/flow/.gitignore @@ -2,5 +2,3 @@ settings.mk vars.sh vars.gdb vars.tcl -.user-bazelrc -bazel-* diff --git a/flow/BUILD.bazel b/flow/BUILD.bazel index ed9b9dbc73..bed5d7e257 100644 --- a/flow/BUILD.bazel +++ b/flow/BUILD.bazel @@ -1,263 +1,70 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_flow") - -filegroup( - name = "constraints-gcd", - srcs = [ - "designs/asap7/gcd/constraint.sdc", - ], - visibility = [":__subpackages__"], -) - -orfs_flow( - name = "gcd", - stage_args = { - "synth": { - "SDC_FILE": "$(location :constraints-gcd)", - }, - "floorplan": { - "DIE_AREA": "0 0 16.2 16.2", - "CORE_AREA": "1.08 1.08 15.12 15.12", - }, - "place": { - "PLACE_DENSITY": "0.35", - }, - }, - stage_sources = { - "synth": [":constraints-gcd"], - }, - verilog_files = glob(include=["designs/src/gcd/*.v"]), -) +load("@bazel-orfs//:openroad.bzl", "orfs_pdk") +# files shared between scripts/synth.sh and scripts/flow.sh steps +MAKEFILE_SHARED = [ + "scripts/*.py", + "scripts/*.sh", + "scripts/*.yaml", + "scripts/*.mk", +] +# makefile and scripts used by script/synth.sh steps filegroup( - name = "constraints-swerv", - srcs = [ - "designs/asap7/swerv_wrapper/constraint.sdc", + name = "makefile_yosys", + srcs = ["Makefile"], + data = glob(MAKEFILE_SHARED + [ + "scripts/*.script", + "scripts/util.tcl", + "scripts/synth*.tcl", + "platforms/common/**/*.v", + ]) + [ + "//flow/util:makefile_yosys", ], - visibility = [":__subpackages__"], + visibility = ["//visibility:public"], ) +# makefile and scripts used in the scripts/flow.sh steps filegroup( - name = "swerv-fastroute", - srcs = [ - "designs/asap7/swerv_wrapper/fastroute.tcl", + name = "makefile", + srcs = ["Makefile"], + data = glob(MAKEFILE_SHARED + [ + "scripts/*.tcl", + "platforms/common/**/*.v", + ]) + [ + "//flow/util:makefile", ], - visibility = [":__subpackages__"], -) - -filegroup( - name = "additional_lefs", - srcs = glob(include=["designs/asap7/swerv_wrapper/lef/*.lef"]) -) -filegroup( - name = "additional_libs", - srcs = glob(include=["designs/asap7/swerv_wrapper/lib/*.lib"]) + visibility = ["//visibility:public"], ) -SWERV_ALL = { - "LIB_MODEL":"CCS", - "ADDITIONAL_LEFS": "$(locations :additional_lefs)", - "ADDITIONAL_LIBS": "$(locations :additional_libs)", -} - -all_sources = [":additional_lefs", ":additional_libs"] - -orfs_flow( - name = "swerv_wrapper", - stage_args = { - "synth": SWERV_ALL | { - "SYNTH_HIERARCHICAL": "1", - "SDC_FILE": "$(location :constraints-swerv)", - }, - "floorplan": SWERV_ALL | { - "RTLMP_MAX_INST": "30000", - "RTLMP_MIN_INST": "5000", - "RTLMP_MAX_MACRO": "30", - "RTLMP_MIN_MACRO": "4", - "DIE_AREA": "0 0 550 600", - "CORE_AREA": "5 5 545 595", - "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*" - }, - "place": SWERV_ALL | { - "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*", - "PLACE_DENSITY_LB_ADDON": "0.20", - }, - "cts": SWERV_ALL | { - "TNS_END_PERCENT": "100", - }, - "route": SWERV_ALL | { - "FASTROUTE_TCL": "$(location :swerv-fastroute)", - }, - "final": SWERV_ALL | { - "PWR_NETS_VOLTAGEsS": "", - "GND_NETS_VOLTAGES": "", - } - }, - verilog_files = glob(include=[ - "designs/src/swerv/swerv_wrapper.sv2v.v", - "designs/asap7/swerv_wrapper/macros.v" +[orfs_pdk( + name = pdk, + srcs = glob([ + "platforms/{pdk}/**/*.{ext}".format( + ext = ext, + pdk = pdk, + ) + for ext in [ + "gds", + "lef", + "lib", + "lyt", + "mk", + "rules", + "tcl", + "v", + ] + { + "sky130hd": ["tlef"], + "asap7": [ + "lib.gz", + "sdc", + ], + }.get(pdk, []) + ] + [ + "platforms/common/**/*.v", ]), - stage_sources = { - "synth": all_sources + [":constraints-swerv"], - "floorplan": all_sources, - "place": all_sources, - "cts": all_sources, - "route": all_sources + [":swerv-fastroute"], - "final": all_sources, - }, -) - - -filegroup( - name = "mock-array-constraints", - srcs = [ - "designs/asap7/mock-array/constraints.sdc", - ], - visibility = [":__subpackages__"], -) - -filegroup( - name = "mock-array-io", - srcs = [ - "designs/asap7/mock-array/io.tcl" - ], - data = [ - "designs/src/mock-array/util.tcl", - ], - visibility = [":__subpackages__"], -) - -filegroup( - name = "mock-array-fastroute", - srcs = [ - "designs/asap7/mock-array/fastroute.tcl", - ], - visibility = [":__subpackages__"], -) - -MOCK_ARRAY_FLOORPLAN_PLACE = { - "PLACE_PINS_ARGS": "-annealing", - "IO_CONSTRAINTS": "$(location :mock-array-io)", - "PLACE_DENSITY": "0.30", - "DIE_AREA": "0 0 358.56 388.8", - "CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004", - "MACRO_PLACE_HALO": "0 2.16", - "RTLMP_BOUNDARY_WT": "0", - "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", - "MACRO_HALO_X": "0.5", - "MACRO_HALO_Y": "0.5", - "MACRO_BLOCKAGE_HALO": "0", - "ADDITIONAL_FILES": "$(locations :mock-array-io)", -} - -orfs_flow( - name = "MockArray", - macros = ["Element_generate_abstract"], - stage_args = { - "synth": { - "SDC_FILE": "$(location :mock-array-constraints)", - }, - "floorplan": MOCK_ARRAY_FLOORPLAN_PLACE | { - }, - "place": MOCK_ARRAY_FLOORPLAN_PLACE | { - }, - "cts": { - "CTS_BUF_DISTANCE": "60" - }, - "route": { - "FASTROUTE_TCL": "$(location :mock-array-fastroute)", - # works with 28 or more iterations as of writing, so give it a few more. - "GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose", - # If this design isn't quickly done in detailed routing, something is wrong. - # At time of adding this option, only 12 iterations were needed for 0 - # violations. - "DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15", - # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the - # same information to other stages in the flow. - "MIN_ROUTING_LAYER": "M2", - "MAX_ROUTING_LAYER": "M7", - }, - "final": { - "GDS_ALLOW_EMPTY": "Element", - "PWR_NETS_VOLTAGEsS": "", - "GND_NETS_VOLTAGES": "", - } - }, - verilog_files = glob(include=["designs/src/mock-array/*.v"]), - stage_sources = { - "synth": all_sources + [":mock-array-constraints"] + [":mock-array-io"], - "floorplan": all_sources + [":mock-array-io"], - "place": all_sources + [":mock-array-io"], - "cts": all_sources, - "route": all_sources + [":mock-array-fastroute"], - "final": all_sources, - }, -) - - -filegroup( - name = "mock-array-element-io", - srcs = [ - "designs/asap7/mock-array/Element/io.tcl" - ], - data = [ - "designs/src/mock-array/util.tcl", - ], - visibility = [":__subpackages__"], -) - -MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE = { - "IO_CONSTRAINTS": "$(location :mock-array-element-io)", - "PLACE_DENSITY": "0.50", - "PLACE_PINS_ARGS": "-annealing", -} - -MOCK_ARRAY_ELEMENT_ALL = { -"MOCK_ARRAY_ROWS" : "8", -"MOCK_ARRAY_COLS" : "8", -} - -mock_array_all_sources = ["designs/src/mock-array/util.tcl"] - -orfs_flow( - name = "Element", - abstract_stage = "route", - stage_args = { - "synth": MOCK_ARRAY_ELEMENT_ALL | { - "SDC_FILE": "$(location :mock-array-constraints)", - }, - "floorplan": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | { - "DIE_AREA": "0 0 43.2 43.2", - "CORE_AREA": "1.08 1.08 42.120000000000005 42.120000000000005", - "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl", - }, - "place": MOCK_ARRAY_ELEMENT_ALL | MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE | { - }, - "cts": MOCK_ARRAY_ELEMENT_ALL | { - }, - "route": MOCK_ARRAY_ELEMENT_ALL | { - # If this design isn't quickly done in detailed routing, something is wrong. - # At time of adding this option, only 3 iterations were needed for 0 - # violations. - "DETAILED_ROUTE_ARGS": "-bottom_routing_layer M2 -top_routing_layer M5 -save_guide_updates -verbose 1 -droute_end_iter 10", - # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the - # same information to other stages in the flow. - "MIN_ROUTING_LAYER": "M2", - "MAX_ROUTING_LAYER": "M5", - }, - "final": MOCK_ARRAY_ELEMENT_ALL | { - "PWR_NETS_VOLTAGES": "", - "GND_NETS_VOLTAGES": "", - } - }, - verilog_files = glob(include=["designs/src/mock-array/*.v"]), - stage_sources = { - "synth": mock_array_all_sources + [":mock-array-constraints"], - "floorplan": mock_array_all_sources + [":mock-array-element-io"], - "place": mock_array_all_sources + [":mock-array-element-io"], - "cts": mock_array_all_sources, - "route": mock_array_all_sources + [":mock-array-fastroute"], - "final": mock_array_all_sources, - }, -) - + config = ":platforms/{pdk}/config.mk".format(pdk = pdk), + visibility = ["//visibility:public"], +) for pdk in [ + "asap7", + "sky130hd", +]] diff --git a/flow/MODULE.bazel b/flow/MODULE.bazel deleted file mode 100644 index a508d30f18..0000000000 --- a/flow/MODULE.bazel +++ /dev/null @@ -1,24 +0,0 @@ -module( - name = "orfs", - version = "0.0.1", - compatibility_level = 1, -) - -bazel_dep(name = "bazel-orfs") -git_override( - module_name = "bazel-orfs", - commit = "16eb5dd5b31bdeacc0b3006a71dbce29076e9850", - remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", -) - -# Read: https://github.com/The-OpenROAD-Project/bazel-orfs?tab=readme-ov-file#usage -# -# TL;DR -# -# 1. uncomment below -# 2. comment git_override() above -# -#local_path_override( -# module_name = "bazel-orfs", path = "../bazel-orfs" -#) - diff --git a/flow/MODULE.bazel.lock b/flow/MODULE.bazel.lock deleted file mode 100644 index c1a25987d3..0000000000 --- a/flow/MODULE.bazel.lock +++ /dev/null @@ -1,142 +0,0 @@ -{ - "lockFileVersion": 11, - "registryFileHashes": { - "https://bcr.bazel.build/bazel_registry.json": "8a28e4aff06ee60aed2a8c281907fb8bcbf3b753c91fb5a5c57da3215d5b3497", - "https://bcr.bazel.build/modules/abseil-cpp/20210324.2/MODULE.bazel": "7cd0312e064fde87c8d1cd79ba06c876bd23630c83466e9500321be55c96ace2", - "https://bcr.bazel.build/modules/abseil-cpp/20211102.0/MODULE.bazel": "70390338f7a5106231d20620712f7cccb659cd0e9d073d1991c038eb9fc57589", - "https://bcr.bazel.build/modules/abseil-cpp/20211102.0/source.json": "7e3a9adf473e9af076ae485ed649d5641ad50ec5c11718103f34de03170d94ad", - "https://bcr.bazel.build/modules/apple_support/1.5.0/MODULE.bazel": "50341a62efbc483e8a2a6aec30994a58749bd7b885e18dd96aa8c33031e558ef", - "https://bcr.bazel.build/modules/apple_support/1.5.0/source.json": "eb98a7627c0bc486b57f598ad8da50f6625d974c8f723e9ea71bd39f709c9862", - "https://bcr.bazel.build/modules/bazel_features/1.11.0/MODULE.bazel": "f9382337dd5a474c3b7d334c2f83e50b6eaedc284253334cf823044a26de03e8", - "https://bcr.bazel.build/modules/bazel_features/1.11.0/source.json": "c9320aa53cd1c441d24bd6b716da087ad7e4ff0d9742a9884587596edfe53015", - "https://bcr.bazel.build/modules/bazel_skylib/1.0.3/MODULE.bazel": "bcb0fd896384802d1ad283b4e4eb4d718eebd8cb820b0a2c3a347fb971afd9d8", - "https://bcr.bazel.build/modules/bazel_skylib/1.2.1/MODULE.bazel": "f35baf9da0efe45fa3da1696ae906eea3d615ad41e2e3def4aeb4e8bc0ef9a7a", - "https://bcr.bazel.build/modules/bazel_skylib/1.3.0/MODULE.bazel": "20228b92868bf5cfc41bda7afc8a8ba2a543201851de39d990ec957b513579c5", - "https://bcr.bazel.build/modules/bazel_skylib/1.6.1/MODULE.bazel": "8fdee2dbaace6c252131c00e1de4b165dc65af02ea278476187765e1a617b917", - "https://bcr.bazel.build/modules/bazel_skylib/1.6.1/source.json": "082ed5f9837901fada8c68c2f3ddc958bb22b6d654f71dd73f3df30d45d4b749", - "https://bcr.bazel.build/modules/buildozer/7.1.2/MODULE.bazel": "2e8dd40ede9c454042645fd8d8d0cd1527966aa5c919de86661e62953cd73d84", - "https://bcr.bazel.build/modules/buildozer/7.1.2/source.json": "c9028a501d2db85793a6996205c8de120944f50a0d570438fcae0457a5f9d1f8", - "https://bcr.bazel.build/modules/googletest/1.11.0/MODULE.bazel": "3a83f095183f66345ca86aa13c58b59f9f94a2f81999c093d4eeaa2d262d12f4", - "https://bcr.bazel.build/modules/googletest/1.11.0/source.json": "c73d9ef4268c91bd0c1cd88f1f9dfa08e814b1dbe89b5f594a9f08ba0244d206", - "https://bcr.bazel.build/modules/platforms/0.0.4/MODULE.bazel": "9b328e31ee156f53f3c416a64f8491f7eb731742655a47c9eec4703a71644aee", - "https://bcr.bazel.build/modules/platforms/0.0.5/MODULE.bazel": "5733b54ea419d5eaf7997054bb55f6a1d0b5ff8aedf0176fef9eea44f3acda37", - "https://bcr.bazel.build/modules/platforms/0.0.6/MODULE.bazel": "ad6eeef431dc52aefd2d77ed20a4b353f8ebf0f4ecdd26a807d2da5aa8cd0615", - "https://bcr.bazel.build/modules/platforms/0.0.7/MODULE.bazel": "72fd4a0ede9ee5c021f6a8dd92b503e089f46c227ba2813ff183b71616034814", - "https://bcr.bazel.build/modules/platforms/0.0.9/MODULE.bazel": "4a87a60c927b56ddd67db50c89acaa62f4ce2a1d2149ccb63ffd871d5ce29ebc", - "https://bcr.bazel.build/modules/platforms/0.0.9/source.json": "cd74d854bf16a9e002fb2ca7b1a421f4403cda29f824a765acd3a8c56f8d43e6", - "https://bcr.bazel.build/modules/protobuf/21.7/MODULE.bazel": "a5a29bb89544f9b97edce05642fac225a808b5b7be74038ea3640fae2f8e66a7", - "https://bcr.bazel.build/modules/protobuf/21.7/source.json": "bbe500720421e582ff2d18b0802464205138c06056f443184de39fbb8187b09b", - "https://bcr.bazel.build/modules/protobuf/3.19.0/MODULE.bazel": "6b5fbb433f760a99a22b18b6850ed5784ef0e9928a72668b66e4d7ccd47db9b0", - "https://bcr.bazel.build/modules/protobuf/3.19.6/MODULE.bazel": "9233edc5e1f2ee276a60de3eaa47ac4132302ef9643238f23128fea53ea12858", - "https://bcr.bazel.build/modules/rules_cc/0.0.1/MODULE.bazel": "cb2aa0747f84c6c3a78dad4e2049c154f08ab9d166b1273835a8174940365647", - "https://bcr.bazel.build/modules/rules_cc/0.0.2/MODULE.bazel": "6915987c90970493ab97393024c156ea8fb9f3bea953b2f3ec05c34f19b5695c", - "https://bcr.bazel.build/modules/rules_cc/0.0.8/MODULE.bazel": "964c85c82cfeb6f3855e6a07054fdb159aced38e99a5eecf7bce9d53990afa3e", - "https://bcr.bazel.build/modules/rules_cc/0.0.9/MODULE.bazel": "836e76439f354b89afe6a911a7adf59a6b2518fafb174483ad78a2a2fde7b1c5", - "https://bcr.bazel.build/modules/rules_cc/0.0.9/source.json": "1f1ba6fea244b616de4a554a0f4983c91a9301640c8fe0dd1d410254115c8430", - "https://bcr.bazel.build/modules/rules_java/4.0.0/MODULE.bazel": "5a78a7ae82cd1a33cef56dc578c7d2a46ed0dca12643ee45edbb8417899e6f74", - "https://bcr.bazel.build/modules/rules_java/7.6.1/MODULE.bazel": "2f14b7e8a1aa2f67ae92bc69d1ec0fa8d9f827c4e17ff5e5f02e91caa3b2d0fe", - "https://bcr.bazel.build/modules/rules_java/7.6.1/source.json": "8f3f3076554e1558e8e468b2232991c510ecbcbed9e6f8c06ac31c93bcf38362", - "https://bcr.bazel.build/modules/rules_jvm_external/4.4.2/MODULE.bazel": "a56b85e418c83eb1839819f0b515c431010160383306d13ec21959ac412d2fe7", - "https://bcr.bazel.build/modules/rules_jvm_external/4.4.2/source.json": "a075731e1b46bc8425098512d038d416e966ab19684a10a34f4741295642fc35", - "https://bcr.bazel.build/modules/rules_license/0.0.3/MODULE.bazel": "627e9ab0247f7d1e05736b59dbb1b6871373de5ad31c3011880b4133cafd4bd0", - "https://bcr.bazel.build/modules/rules_license/0.0.7/MODULE.bazel": "088fbeb0b6a419005b89cf93fe62d9517c0a2b8bb56af3244af65ecfe37e7d5d", - "https://bcr.bazel.build/modules/rules_license/0.0.7/source.json": "355cc5737a0f294e560d52b1b7a6492d4fff2caf0bef1a315df5a298fca2d34a", - "https://bcr.bazel.build/modules/rules_pkg/0.7.0/MODULE.bazel": "df99f03fc7934a4737122518bb87e667e62d780b610910f0447665a7e2be62dc", - "https://bcr.bazel.build/modules/rules_pkg/0.7.0/source.json": "c2557066e0c0342223ba592510ad3d812d4963b9024831f7f66fd0584dd8c66c", - "https://bcr.bazel.build/modules/rules_proto/4.0.0/MODULE.bazel": "a7a7b6ce9bee418c1a760b3d84f83a299ad6952f9903c67f19e4edd964894e06", - "https://bcr.bazel.build/modules/rules_proto/5.3.0-21.7/MODULE.bazel": "e8dff86b0971688790ae75528fe1813f71809b5afd57facb44dad9e8eca631b7", - "https://bcr.bazel.build/modules/rules_proto/5.3.0-21.7/source.json": "d57902c052424dfda0e71646cb12668d39c4620ee0544294d9d941e7d12bc3a9", - "https://bcr.bazel.build/modules/rules_python/0.10.2/MODULE.bazel": "cc82bc96f2997baa545ab3ce73f196d040ffb8756fd2d66125a530031cd90e5f", - "https://bcr.bazel.build/modules/rules_python/0.22.1/MODULE.bazel": "26114f0c0b5e93018c0c066d6673f1a2c3737c7e90af95eff30cfee38d0bbac7", - "https://bcr.bazel.build/modules/rules_python/0.22.1/source.json": "57226905e783bae7c37c2dd662be078728e48fa28ee4324a7eabcafb5a43d014", - "https://bcr.bazel.build/modules/rules_python/0.4.0/MODULE.bazel": "9208ee05fd48bf09ac60ed269791cf17fb343db56c8226a720fbb1cdf467166c", - "https://bcr.bazel.build/modules/stardoc/0.5.1/MODULE.bazel": "1a05d92974d0c122f5ccf09291442580317cdd859f07a8655f1db9a60374f9f8", - "https://bcr.bazel.build/modules/stardoc/0.5.1/source.json": "a96f95e02123320aa015b956f29c00cb818fa891ef823d55148e1a362caacf29", - "https://bcr.bazel.build/modules/upb/0.0.0-20220923-a547704/MODULE.bazel": "7298990c00040a0e2f121f6c32544bab27d4452f80d9ce51349b1a28f3005c43", - "https://bcr.bazel.build/modules/upb/0.0.0-20220923-a547704/source.json": "f1ef7d3f9e0e26d4b23d1c39b5f5de71f584dd7d1b4ef83d9bbba6ec7a6a6459", - "https://bcr.bazel.build/modules/zlib/1.2.11/MODULE.bazel": "07b389abc85fdbca459b69e2ec656ae5622873af3f845e1c9d80fe179f3effa0", - "https://bcr.bazel.build/modules/zlib/1.2.12/MODULE.bazel": "3b1a8834ada2a883674be8cbd36ede1b6ec481477ada359cd2d3ddc562340b27", - "https://bcr.bazel.build/modules/zlib/1.3/MODULE.bazel": "6a9c02f19a24dcedb05572b2381446e27c272cd383aed11d41d99da9e3167a72", - "https://bcr.bazel.build/modules/zlib/1.3/source.json": "b6b43d0737af846022636e6e255fd4a96fee0d34f08f3830e6e0bac51465c37c" - }, - "selectedYankedVersions": {}, - "moduleExtensions": { - "@@bazel-orfs~//:extension.bzl%orfs_repositories": { - "general": { - "bzlTransitiveDigest": "42x9Wez2cJ4mcTzytkWEzBr9ilyB80Y3HGoSJdZwb6w=", - "usagesDigest": "Gm0+3Dl8SF2RuxlljVbGIkux4jFOBVAe5f0GmuKYgk4=", - "recordedFileInputs": {}, - "recordedDirentsInputs": {}, - "envVariables": {}, - "generatedRepoSpecs": { - "docker_orfs": { - "bzlFile": "@@bazel-orfs~//:docker.bzl", - "ruleClassName": "docker_pkg", - "attributes": { - "image": "openroad/orfs:v3.0-1114-g46acc762", - "sha256": "ae4df23391c26bcc48a506f8e0d0da73742d1b6cb3b1dc02f4d5ea71170195b5", - "build_file": "@@bazel-orfs~//:docker.BUILD.bazel", - "timeout": 3600 - } - }, - "com_github_nixos_patchelf_download": { - "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", - "ruleClassName": "http_archive", - "attributes": { - "build_file_content": "\n export_files(\n [\"bin/patchelf\"],\n visibility = [\"//visibility:public\"],\n )\n ", - "sha256": "ce84f2447fb7a8679e58bc54a20dc2b01b37b5802e12c57eece772a6f14bf3f0", - "urls": [ - "https://github.com/NixOS/patchelf/releases/download/0.18.0/patchelf-0.18.0-x86_64.tar.gz" - ] - } - }, - "com_github_docker_buildx_file": { - "bzlFile": "@@bazel_tools//tools/build_defs/repo:http.bzl", - "ruleClassName": "http_file", - "attributes": { - "executable": true, - "sha256": "8d486f0088b7407a90ad675525ba4a17d0a537741b9b33fe3391a88cafa2dd0b", - "urls": [ - "https://github.com/docker/buildx/releases/download/v0.15.1/buildx-v0.15.1.linux-amd64" - ] - } - } - }, - "recordedRepoMappingEntries": [ - [ - "bazel-orfs~", - "bazel_tools", - "bazel_tools" - ], - [ - "bazel-orfs~", - "com_github_docker_buildx_file", - "bazel-orfs~~orfs_repositories~com_github_docker_buildx_file" - ], - [ - "bazel-orfs~", - "com_github_nixos_patchelf_download", - "bazel-orfs~~orfs_repositories~com_github_nixos_patchelf_download" - ] - ] - } - }, - "@@platforms//host:extension.bzl%host_platform": { - "general": { - "bzlTransitiveDigest": "xelQcPZH8+tmuOHVjL9vDxMnnQNMlwj0SlvgoqBkm4U=", - "usagesDigest": "meSzxn3DUCcYEhq4HQwExWkWtU4EjriRBQLsZN+Q0SU=", - "recordedFileInputs": {}, - "recordedDirentsInputs": {}, - "envVariables": {}, - "generatedRepoSpecs": { - "host_platform": { - "bzlFile": "@@platforms//host:extension.bzl", - "ruleClassName": "host_platform_repo", - "attributes": {} - } - }, - "recordedRepoMappingEntries": [] - } - } - } -} diff --git a/flow/Makefile b/flow/Makefile index 0118e715af..21a5ea0223 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -23,22 +23,6 @@ # DESIGN_CONFIG=./designs/nangate45/swerv_wrapper/config.mk # DESIGN_CONFIG=./designs/nangate45/tinyRocket/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/aes/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/ariane/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/black_parrot/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/bp_be_top/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/bp_fe_top/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/bp_multi_top/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/coyote/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/dynamic_node/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/gcd/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/ibex/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/jpeg/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/swerv/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/swerv_wrapper/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/tinyRocket/config.mk -# DESIGN_CONFIG=./designs/tsmc65lp/vanilla5/config.mk - # DESIGN_CONFIG=./designs/gf12/aes/config.mk # DESIGN_CONFIG=./designs/gf12/ariane/config.mk # DESIGN_CONFIG=./designs/gf12/ca53/config.mk @@ -56,8 +40,6 @@ # DESIGN_CONFIG=./designs/sky130hd/aes/config.mk # DESIGN_CONFIG=./designs/sky130hd/chameleon/config.mk -# DESIGN_CONFIG=./designs/sky130hd/chameleon_hier/config.mk -# DESIGN_CONFIG=./designs/sky130hd/coyote_tc/config.mk # DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk # DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk # DESIGN_CONFIG=./designs/sky130hd/jpeg/config.mk @@ -84,8 +66,6 @@ # DESIGN_CONFIG=./designs/intel16/aes/config.mk # DESIGN_CONFIG=./designs/intel16/gcd/config.mk -# DESIGN_CONFIG=./designs/intel22/aes/config.mk -# DESIGN_CONFIG=./designs/intel22/gcd/config.mk # DESIGN_CONFIG=./designs/intel22/ibex/config.mk # DESIGN_CONFIG=./designs/intel22/jpeg/config.mk @@ -100,18 +80,41 @@ #DESIGN_CONFIG=./designs/ihp-sg13g2/gcd/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/spi/config.mk #DESIGN_CONFIG=./designs/ihp-sg13g2/riscv32i/config.mk +#DESIGN_CONFIG=./designs/ihp-sg13g2/i2c-gpio-expander/config.mk # Default design DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk - -# Include design and platform configuration before setting default options -# in this file. This allows the DESIGN_CONFIG to set different defaults than -# this file. +export DESIGN_CONFIG include $(DESIGN_CONFIG) -# If we are running headless use offscreen rendering for save_image -ifeq ($(DISPLAY),) -export QT_QPA_PLATFORM ?= offscreen +export DESIGN_DIR ?= $(dir $(DESIGN_CONFIG)) + +# default value "base" for FLOW_VARIANT and "." for WORK_HOME are duplicated +# from variables.yaml and variables.mk because we need it +# earlier in the flow for BLOCKS. BLOCKS is a feature specific to the +# ORFS Makefile. +export FLOW_VARIANT?=base +export WORK_HOME?=. +# BLOCKS is a ORFS make flow specific feature. +ifneq ($(BLOCKS),) + # Normally this comes from variables.yaml, but we need it here to set up these variables + # which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept. + $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) + $(foreach block,$(BLOCKS),$(eval BLOCK_TYP_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_FAST_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_fast.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_SLOW_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_slow.lib)) + $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) + $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) + $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) + export ADDITIONAL_LEFS += $(BLOCK_LEFS) + export ADDITIONAL_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_TYP_LIBS += $(BLOCK_TYP_LIBS) + export ADDITIONAL_FAST_LIBS += $(BLOCK_FAST_LIBS) + export ADDITIONAL_SLOW_LIBS += $(BLOCK_SLOW_LIBS) + export ADDITIONAL_GDS += $(BLOCK_GDS) + ifneq ($(CDL_FILES),) + export CDL_FILES += $(BLOCK_CDL) + endif endif # ============================================================================== @@ -136,174 +139,18 @@ MAKEFLAGS += --no-builtin-rules SHELL := /usr/bin/env bash .SHELLFLAGS := -o pipefail -c + #------------------------------------------------------------------------------- # Setup variables to point to root / head of the OpenROAD directory # - the following settings allowed user to point OpenROAD binaries to different # location # - default is current install / clone directory ifeq ($(origin FLOW_HOME), undefined) -FLOW_HOME := $(shell pwd) + FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST)))) endif export FLOW_HOME -#------------------------------------------------------------------------------- -# Setup variables to point to other location for the following sub directory -# - designs - default is under current directory -# - platforms - default is under current directory -# - work home - default is current directory -# - utils, scripts, test - default is under current directory -export DESIGN_HOME ?= $(FLOW_HOME)/designs -export PLATFORM_HOME ?= $(FLOW_HOME)/platforms -export WORK_HOME ?= . - -export UTILS_DIR ?= $(FLOW_HOME)/util -export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts -export TEST_DIR ?= $(FLOW_HOME)/test - -PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 - -ifneq ($(wildcard $(PLATFORM_HOME)/$(PLATFORM)),) - export PLATFORM_DIR = $(PLATFORM_HOME)/$(PLATFORM) -else ifneq ($(findstring $(PLATFORM),$(PUBLIC)),) - export PLATFORM_DIR = ./platforms/$(PLATFORM) -else ifneq ($(wildcard ../../$(PLATFORM)),) - export PLATFORM_DIR = ../../$(PLATFORM) -else - $(error [ERROR][FLOW] Platform '$(PLATFORM)' not found.) -endif - -include $(PLATFORM_DIR)/config.mk - -# __SPACE__ is a workaround for whitespace hell in "foreach"; there -# is no way to escape space in defaults.py and get "foreach" to work. -$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) - -# Enables hierarchical yosys -export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt -export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl -# If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here -export MAX_UNGROUP_SIZE ?= 0 - -# Not normally adjusted by user -export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v -export SYNTH_FULL_ARGS ?= $(SYNTH_ARGS) $(SYNTH_OPERATIONS_ARGS) - -export FLOW_VARIANT ?= base - -# Setup working directories -export DESIGN_NICKNAME ?= $(DESIGN_NAME) - -export DESIGN_CONFIG -export DESIGN_DIR = $(dir $(DESIGN_CONFIG)) -export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) -export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) -export REPORTS_DIR = $(WORK_HOME)/reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) -export RESULTS_DIR = $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) - -ifneq ($(BLOCKS),) - $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib)) - $(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds)) - $(foreach block,$(BLOCKS),$(eval BLOCK_CDL += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl)) - $(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/)) - export ADDITIONAL_LEFS += $(BLOCK_LEFS) - export ADDITIONAL_LIBS += $(BLOCK_LIBS) - export ADDITIONAL_GDS += $(BLOCK_GDS) - export GDS_FILES += $(BLOCK_GDS) - ifneq ($(CDL_FILES),) - export CDL_FILES += $(BLOCK_CDL) - endif -endif - -export RTLMP_RPT_DIR ?= $(OBJECTS_DIR)/rtlmp -export RTLMP_RPT_FILE ?= partition.txt -export RTLMP_BLOCKAGE_FILE ?= $(OBJECTS_DIR)/rtlmp/partition.txt.blockage - -#------------------------------------------------------------------------------- -ifeq (,$(strip $(NUM_CORES))) - # Linux (utility program) - NUM_CORES := $(shell nproc 2>/dev/null) - - ifeq (,$(strip $(NUM_CORES))) - # Linux (generic) - NUM_CORES := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null) - endif - ifeq (,$(strip $(NUM_CORES))) - # BSD (at least FreeBSD and Mac OSX) - NUM_CORES := $(shell sysctl -n hw.ncpu 2>/dev/null) - endif - ifeq (,$(strip $(NUM_CORES))) - # Fallback - NUM_CORES := 1 - endif -endif -export NUM_CORES - -YOSYS_FLAGS += -v 3 - -#------------------------------------------------------------------------------- -# setup all commands used within this flow -export TIME_BIN ?= env time -TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' -TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null) -ifeq (,$(strip $(TIME_TEST))) - TIME_CMD = $(TIME_BIN) -endif - -# The following determine the executable location for each tool used by this flow. -# Priority is given to -# 1 user explicit set with variable in Makefile or command line, for instance setting OPENROAD_EXE -# 2 ORFS compiled tools: openroad, yosys -export OPENROAD_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/openroad) -export OPENSTA_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/sta) - -OPENROAD_ARGS = -no_init -threads $(NUM_CORES) $(OR_ARGS) -OPENROAD_CMD = $(OPENROAD_EXE) -exit $(OPENROAD_ARGS) -OPENROAD_NO_EXIT_CMD = $(OPENROAD_EXE) $(OPENROAD_ARGS) -OPENROAD_GUI_CMD = $(OPENROAD_EXE) -gui $(OR_ARGS) - -YOSYS_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/yosys/bin/yosys) - -# Use locally installed and built klayout if it exists, otherwise use klayout in path -KLAYOUT_DIR = $(abspath $(FLOW_HOME)/../tools/install/klayout/) -KLAYOUT_BIN_FROM_DIR = $(KLAYOUT_DIR)/klayout - -ifeq ($(wildcard $(KLAYOUT_BIN_FROM_DIR)), $(KLAYOUT_BIN_FROM_DIR)) -KLAYOUT_CMD ?= sh -c 'LD_LIBRARY_PATH=$(dir $(KLAYOUT_BIN_FROM_DIR)) $$0 "$$@"' $(KLAYOUT_BIN_FROM_DIR) -else -ifeq ($(KLAYOUT_CMD),) -KLAYOUT_CMD := $(shell command -v klayout) -endif -endif -KLAYOUT_FOUND = $(if $(KLAYOUT_CMD),,$(error KLayout not found in PATH)) - -ifneq ($(shell command -v stdbuf),) - STDBUF_CMD ?= stdbuf -o L -endif - -#------------------------------------------------------------------------------- -WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.lef=_mod.lef)) -WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib)) -export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS) -export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS) - -export DONT_USE_LIBS = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES)))) -export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS)) - -# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS -STREAM_SYSTEM ?= GDS -ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),) - export STREAM_SYSTEM_EXT := gds - GDSOAS_FILES = $(GDS_FILES) - ADDITIONAL_GDSOAS = $(ADDITIONAL_GDS) - SEAL_GDSOAS = $(SEAL_GDS) -else - export STREAM_SYSTEM_EXT := oas - GDSOAS_FILES = $(OAS_FILES) - ADDITIONAL_GDSOAS = $(ADDITIONAL_OAS) - SEAL_GDSOAS = $(SEAL_OAS) -endif -export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT))) +include $(FLOW_HOME)/scripts/variables.mk define GENERATE_ABSTRACT_RULE ifeq ($(wildcard $(3)),) @@ -327,27 +174,19 @@ endef # Targets to harden Blocks in case of hierarchical flow is triggered .PHONY: build_macros -build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS) +build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS) -$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) -$(foreach block,$(BLOCKS),$(eval ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) +$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk))) +$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef)) # Utility to print tool version information #------------------------------------------------------------------------------- .PHONY: versions.txt versions.txt: mkdir -p $(OBJECTS_DIR) - @if [ -z "$(YOSYS_EXE)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \ - else \ - $(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \ - fi - @echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@ - @if [ -z "$(KLAYOUT_CMD)" ]; then \ - echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \ - else \ - $(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \ - fi + @echo "yosys $(if $(YOSYS_EXE),$(shell $(YOSYS_EXE) -V 2>&1),not available)" > $(OBJECTS_DIR)/$@ + @echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@ + @echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@ # Pre-process libraries # ============================================================================== @@ -357,10 +196,10 @@ versions.txt: .SECONDEXPANSION: $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES)) @mkdir -p $(OBJECTS_DIR)/lib - $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ + $(PYTHON_EXE) $(UTILS_DIR)/preprocessLib.py -i $^ -o $@ -$(OBJECTS_DIR)/lib/merged.lib: - $(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ +$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS) + $(PYTHON_EXE) $(UTILS_DIR)/merge_lib.py $(PLATFORM)_merged $(DONT_USE_LIBS) > $@ # Pre-process KLayout tech # ============================================================================== @@ -372,25 +211,13 @@ do-klayout_tech: @mkdir -p $(OBJECTS_DIR) cp $(TECH_LEF) $(OBJECTS_DIR)/klayout_tech.lef -KLAYOUT_ENV_VAR_IN_PATH_VERSION = 0.28.11 -KLAYOUT_VERSION := $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -v 2>/dev/null | grep 'KLayout' | cut -d ' ' -f2),) - -KLAYOUT_ENV_VAR_IN_PATH = $(shell \ - if [ -z "$(KLAYOUT_VERSION)" ]; then \ - echo "not_found"; \ - elif [ "$$(echo -e "$(KLAYOUT_VERSION)\n$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" | sort -V | head -n1)" = "$(KLAYOUT_VERSION)" ] && [ "$(KLAYOUT_VERSION)" != "$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" ]; then \ - echo "invalid"; \ - else \ - echo "valid"; \ - fi) - $(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef $(UNSET_AND_MAKE) do-klayout .PHONY: do-klayout do-klayout: ifeq ($(KLAYOUT_ENV_VAR_IN_PATH),valid) - SC_LEF_RELATIVE_PATH="$$\(env('FLOW_HOME')\)/$(shell realpath --relative-to=$(FLOW_HOME) $(SC_LEF))"; \ + SC_LEF_RELATIVE_PATH="$(shell realpath --relative-to=$(RESULTS_DIR) $(SC_LEF))"; \ OTHER_LEFS_RELATIVE_PATHS=$$(echo "$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(ADDITIONAL_LEFS),$$(realpath --relative-to=$(RESULTS_DIR) $(file)))"); \ sed 's,.*,'"$$SC_LEF_RELATIVE_PATH"''"$$OTHER_LEFS_RELATIVE_PATHS"',g' $(KLAYOUT_TECH_FILE) > $(OBJECTS_DIR)/klayout.lyt else @@ -405,12 +232,6 @@ $(OBJECTS_DIR)/klayout_wrap.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tec do-klayout_wrap: sed 's,.*,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),$(shell realpath --relative-to=$(OBJECTS_DIR)/def $(file))),g' $(KLAYOUT_TECH_FILE) > $(OBJECTS_DIR)/klayout_wrap.lyt -# Create Macro wrappers (if necessary) -# ============================================================================== -WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg - - -export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH) $(WRAPPED_LEFS): mkdir -p $(OBJECTS_DIR)/lef $(OBJECTS_DIR)/def util/cell-veneer/wrap.tcl -cfg $(WRAP_CFG) -macro $(filter %$(notdir $(@:_mod.lef=.lef)),$(WRAP_LEFS)) @@ -437,14 +258,14 @@ synth-report: synth .PHONY: do-synth-report do-synth-report: - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(LOG_DIR)/1_1_yosys_metrics.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_2_yosys_metrics.log) .PHONY: memory memory: if [ -f $(RESULTS_DIR)/mem_hierarchical.json ]; then \ - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem_hierarchical.json; \ fi - python3 $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json + $(PYTHON_EXE) $(SCRIPTS_DIR)/mem_dump.py $(RESULTS_DIR)/mem.json # ============================================================================== @@ -452,49 +273,33 @@ memory: # Run Synthesis using yosys #------------------------------------------------------------------------------- -export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl -export SYNTH_MEMORY_MAX_BITS ?= 4096 - -.PHONY: do-yosys-stats -do-yosys-stats: - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - (export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \ - $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log) - -export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt - $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE) mkdir -p $(dir $@) echo $(ABC_CLOCK_PERIOD_IN_PS) > $@ -YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD) - .PHONY: yosys-dependencies yosys-dependencies: $(YOSYS_DEPENDENCIES) .PHONY: do-yosys -do-yosys: - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) - (export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \ - $(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys.log) +do-yosys: $(DONT_USE_SC_LIB) + $(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log .PHONY: do-yosys-canonicalize -do-yosys-canonicalize: yosys-dependencies - mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) - ($(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SCRIPTS_DIR)/synth_canonicalize.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_canonicalize.log) +do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB) + $(SCRIPTS_DIR)/synth.sh $(SCRIPTS_DIR)/synth_canonicalize.tcl $(LOG_DIR)/1_1_yosys_canonicalize.log -$(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES) +$(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil: $(YOSYS_DEPENDENCIES) $(UNSET_AND_MAKE) do-yosys-canonicalize -$(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil - $(UNSET_AND_MAKE) do-yosys-stats do-yosys +$(RESULTS_DIR)/1_2_yosys.v: $(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil + $(UNSET_AND_MAKE) do-yosys .PHONY: do-synth do-synth: mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) - cp $(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.v + cp $(RESULTS_DIR)/1_2_yosys.v $(RESULTS_DIR)/1_synth.v -$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v +$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_2_yosys.v $(UNSET_AND_MAKE) do-synth .PHONY: clean_synth @@ -520,12 +325,6 @@ floorplan: $(RESULTS_DIR)/2_floorplan.odb \ # ============================================================================== -ifneq ($(FOOTPRINT),) -IS_CHIP = 1 -else ifneq ($(FOOTPRINT_TCL),) -IS_CHIP = 1 -endif - UNSET_VARS = for var in $(UNSET_VARIABLES_NAMES); do unset $$var; done # FILE_MAKEFILE is needed when ORFS is invoked with @@ -553,7 +352,7 @@ define OPEN_GUI open_$(1): $(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_NO_EXIT_CMD) $(SCRIPTS_DIR)/open.tcl gui_$(1): - $(2)=$(RESULTS_DIR)/$(1) GUI_SHOW=1 $(OPENROAD_GUI_CMD) -minimize $(SCRIPTS_DIR)/open.tcl + $(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_GUI_CMD) $(SCRIPTS_DIR)/open.tcl endef # Separate dependency checking and doing a step. This can @@ -594,13 +393,7 @@ endif .PHONY: do-$(1) do-$(1): $(OBJECTS_DIR)/copyright.txt - @mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) - @echo Running $(3).tcl, stage $(1) - @(set -eo pipefail; \ - trap 'mv $(LOG_DIR)/$(1).tmp.log $(LOG_DIR)/$(1).log' EXIT; \ - $(OPENROAD_EXE) $(OPENROAD_ARGS) -exit $(SCRIPTS_DIR)/noop.tcl 2>&1 >$(LOG_DIR)/$(1).tmp.log; \ - $(TIME_CMD) $(OPENROAD_CMD) -no_splash $(SCRIPTS_DIR)/$(3).tcl -metrics $(LOG_DIR)/$(1).json 2>&1 | \ - tee -a $(abspath $(LOG_DIR)/$(1).tmp.log)) + $(SCRIPTS_DIR)/flow.sh $(1) $(3) endef # generate make rules to copy a file, if a dependency change and @@ -608,7 +401,7 @@ endef # # The file is copied within the $(RESULTS_DIR) # -# $(1) stem of target, e.g. 2_2_floorplan_io +# $(1) stem of target, e.g. 2_1_floorplan # $(2) basename of file to be copied # $(3) further dependencies # $(4) target extension, default .odb @@ -621,36 +414,31 @@ do-$(1)$(if $(4),$(4),): cp $(RESULTS_DIR)/$(2) $(RESULTS_DIR)/$(1)$(if $(4),$(4),.odb) endef +$(eval $(call do-step,1_3_synth,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc,synth_odb)) -# STEP 1: Translate verilog to odb -#------------------------------------------------------------------------------- -$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan)) - -# STEP 2: Random IO placement -#------------------------------------------------------------------------------- -$(eval $(call do-step,2_2_floorplan_io,$(RESULTS_DIR)/2_1_floorplan.odb $(IO_CONSTRAINTS),io_placement_random)) +$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(DONT_USE_SC_LIB),floorplan)) $(eval $(call do-copy,2_floorplan,2_1_floorplan.sdc,,.sdc)) -# STEP 3: Macro Placement +# STEP 2: Macro Placement #------------------------------------------------------------------------------- -$(eval $(call do-step,2_3_floorplan_macro,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) +$(eval $(call do-step,2_2_floorplan_macro,$(RESULTS_DIR)/2_1_floorplan.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place)) -# STEP 4: Tapcell and Welltie insertion +# STEP 3: Tapcell and Welltie insertion #------------------------------------------------------------------------------- -$(eval $(call do-step,2_4_floorplan_tapcell,$(RESULTS_DIR)/2_3_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) +$(eval $(call do-step,2_3_floorplan_tapcell,$(RESULTS_DIR)/2_2_floorplan_macro.odb $(TAPCELL_TCL),tapcell)) -# STEP 5: PDN generation +# STEP 4: PDN generation #------------------------------------------------------------------------------- -$(eval $(call do-step,2_5_floorplan_pdn,$(RESULTS_DIR)/2_4_floorplan_tapcell.odb $(PDN_TCL),pdn)) +$(eval $(call do-step,2_4_floorplan_pdn,$(RESULTS_DIR)/2_3_floorplan_tapcell.odb $(PDN_TCL),pdn)) -$(eval $(call do-copy,2_floorplan,2_5_floorplan_pdn.odb,)) +$(eval $(call do-copy,2_floorplan,2_4_floorplan_pdn.odb,)) $(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.odb .PHONY: do-floorplan do-floorplan: - $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_macro do-2_4_floorplan_tapcell do-2_5_floorplan_pdn do-2_floorplan do-2_floorplan.sdc + $(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_macro do-2_3_floorplan_tapcell do-2_4_floorplan_pdn do-2_floorplan do-2_floorplan.sdc .PHONY: clean_floorplan clean_floorplan: @@ -752,7 +540,8 @@ clean_cts: route: $(RESULTS_DIR)/5_route.odb \ $(RESULTS_DIR)/5_route.sdc -.PHONY: grt +.PHONY: grt globalroute +globalroute: grt grt: $(RESULTS_DIR)/5_1_grt.odb # ============================================================================== @@ -760,7 +549,7 @@ grt: $(RESULTS_DIR)/5_1_grt.odb # STEP 1: Run global route #------------------------------------------------------------------------------- -$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE),global_route)) +$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE_TCL),global_route)) # STEP 2: Run detailed route #------------------------------------------------------------------------------- @@ -813,7 +602,6 @@ klayout_guides: $(RESULTS_DIR)/5_route.def $(OBJECTS_DIR)/klayout.lyt # | _| | || |\ || | ___) | _ || || |\ | |_| | # |_| |___|_| \_|___|____/|_| |_|___|_| \_|\____| # -GDS_FINAL_FILE = $(RESULTS_DIR)/6_final.$(STREAM_SYSTEM_EXT) .PHONY: finish finish: $(LOG_DIR)/6_report.log \ $(RESULTS_DIR)/6_final.v \ @@ -823,12 +611,12 @@ finish: $(LOG_DIR)/6_report.log \ .PHONY: elapsed elapsed: - -@$(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) + -@$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(BLOCK_LOG_FOLDERS) $(LOG_DIR) # Useful when working with macros, see elapsed time for all macros in platform .PHONY: elapsed-all elapsed-all: - @$(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) + @$(PYTHON_EXE) $(UTILS_DIR)/genElapsedTime.py -d $(shell find $(WORK_HOME)/logs/$(PLATFORM)/*/*/ -type d) $(eval $(call do-step,6_1_fill,$(RESULTS_DIR)/5_route.odb $(RESULTS_DIR)/5_route.sdc $(FILL_CONFIG),density_fill)) @@ -860,7 +648,7 @@ generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def $(RESU .PHONY: do-generate_abstract do-generate_abstract: mkdir -p $(LOG_DIR) $(REPORTS_DIR) - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(LOG_DIR)/generate_abstract.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(abspath $(LOG_DIR)/generate_abstract.log) .PHONY: clean_abstract clean_abstract: @@ -878,11 +666,10 @@ $(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS) -rd out_file=$@ \ -rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log) # Merge GDS using Klayout #------------------------------------------------------------------------------- -GDS_MERGED_FILE = $(RESULTS_DIR)/6_1_merged.$(STREAM_SYSTEM_EXT) $(GDS_MERGED_FILE): $(RESULTS_DIR)/6_final.def $(OBJECTS_DIR)/klayout.lyt $(GDSOAS_FILES) $(WRAPPED_GDSOAS) $(SEAL_GDSOAS) $(UNSET_AND_MAKE) do-gds-merged @@ -896,7 +683,7 @@ do-gds-merged: -rd out_file=$(GDS_MERGED_FILE) \ -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \ -rd layer_map=$(GDS_LAYER_MAP) \ - -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log + -r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_1_merge.log) $(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log @@ -916,7 +703,7 @@ ifneq ($(KLAYOUT_DRC_FILE),) $(call KLAYOUT_FOUND) ($(TIME_CMD) $(KLAYOUT_CMD) -zz -rd in_gds="$<" \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log + -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_drc.log) # Hacky way of getting DRV count (don't error on no matches) grep -c "" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]] else @@ -924,7 +711,7 @@ else endif $(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v - ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log + ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/6_cdl.log) $(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE) cat $^ > $@ @@ -938,7 +725,7 @@ ifneq ($(KLAYOUT_LVS_FILE),) ($(TIME_CMD) $(KLAYOUT_CMD) -b -rd in_gds="$<" \ -rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \ -rd report_file=$(abspath $@) \ - -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log + -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_lvs.log) else echo "LVS not supported on this platform" > $@ endif @@ -976,32 +763,18 @@ clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_f .PHONY: nuke nuke: clean_test clean_issues - rm -rf ./results ./logs ./reports ./objects + rm -rf $(WORK_HOME)/results $(WORK_HOME)/logs $(WORK_HOME)/reports $(WORK_HOME)/objects rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log rm -f $(OBJECTS_DIR)/versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide -.PHONY: vars -vars: - $(UTILS_DIR)/generate-vars.sh vars - # DEF/GDS/OAS viewer shortcuts #------------------------------------------------------------------------------- -RESULTS_ODB = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.odb))) -RESULTS_DEF = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.def))) -RESULTS_GDS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.gds))) -RESULTS_OAS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.oas))) .PHONY: $(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)) $(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)): klayout_%: $(OBJECTS_DIR)/klayout.lyt $(KLAYOUT_CMD) -nn $(OBJECTS_DIR)/klayout.lyt $(RESULTS_DIR)/$* -.PHONY: gui_synth -gui_synth: - $(OPENROAD_GUI_CMD) $(SCRIPTS_DIR)/sta-synth.tcl -.PHONY: open_synth -open_synth: - $(OPENROAD_NO_EXIT_CMD) $(SCRIPTS_DIR)/sta-synth.tcl - +$(eval $(call OPEN_GUI_SHORTCUT,synth,1_synth.odb)) $(eval $(call OPEN_GUI_SHORTCUT,floorplan,2_floorplan.odb)) $(eval $(call OPEN_GUI_SHORTCUT,place,3_place.odb)) $(eval $(call OPEN_GUI_SHORTCUT,cts,4_cts.odb)) @@ -1040,10 +813,6 @@ all_verilog : $(foreach file,$(RESULTS_ODB),$(file).v) .PHONY: handoff handoff : all_defs all_verilog -.PHONY: print-% -# Print any variable, for instance: make print-DIE_AREA -print-% : ; @echo "$* = $($*)" - .PHONY: test-unset-and-make-% test-unset-and-make-%: ; $(UNSET_AND_MAKE) $* @@ -1053,7 +822,13 @@ klayout: .phony: run run: - $(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) + @mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR) + ($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/$(RUN_LOG_NAME_STEM).log)) + +export RUN_YOSYS_ARGS ?= -c $(SCRIPTS_DIR)/yosys_keep.tcl +.phony: run-yosys +run-yosys: + $(YOSYS_EXE) $(RUN_YOSYS_ARGS) # Utilities #------------------------------------------------------------------------------- diff --git a/flow/designs/asap7/aes-block/autotuner.json b/flow/designs/asap7/aes-block/autotuner.json index 4225584ff7..28400501b3 100644 --- a/flow/designs/asap7/aes-block/autotuner.json +++ b/flow/designs/asap7/aes-block/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 100, + 300, 600 ], "step": 0 @@ -11,8 +11,8 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 0, - 20 + 20, + 50 ], "step": 1 }, @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk index 9716e7fe9e..7bc1fd2acc 100644 --- a/flow/designs/asap7/aes-block/block.mk +++ b/flow/designs/asap7/aes-block/block.mk @@ -10,4 +10,8 @@ export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.70 +export MAX_ROUTING_LAYER ?= M5 + export PLACE_PINS_ARGS = -annealing + +export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index 79520f6b4c..60a0c336b1 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -8,10 +8,10 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export ABC_AREA = 1 -export CORE_UTILIZATION = 20 +export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 -export PLACE_DENSITY = 0.65 +export PLACE_DENSITY = 0.53 export BLOCKS ?= aes_rcon aes_sbox export SYNTH_HIERARCHICAL = 1 @@ -27,4 +27,6 @@ export GND_NETS_VOLTAGES = export PWR_NETS_VOLTAGES = # The macros are very small so use a smaller halo -export MACRO_PLACE_HALO ?= 5 5 +export MACRO_PLACE_HALO ?= 3 3 + +export ROUTING_LAYER_ADJUSTMENT = 0.3 diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index e45d9100bd..8d7d7c5987 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 475 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-block/metadata-base-ok.json b/flow/designs/asap7/aes-block/metadata-base-ok.json deleted file mode 100644 index 8a7131b813..0000000000 --- a/flow/designs/asap7/aes-block/metadata-base-ok.json +++ /dev/null @@ -1,319 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 400.0000" - ], - "cts__clock__skew__hold": 123.279, - "cts__clock__skew__setup": 108.492, - "cts__cpu__total": 18.49, - "cts__design__core__area": 30460, - "cts__design__die__area": 31942.3, - "cts__design__instance__area": 6490.54, - "cts__design__instance__area__macros": 5577.25, - "cts__design__instance__area__stdcell": 913.291, - "cts__design__instance__count": 11916, - "cts__design__instance__count__hold_buffer": 1147, - "cts__design__instance__count__macros": 21, - "cts__design__instance__count__setup_buffer": 64, - "cts__design__instance__count__stdcell": 11895, - "cts__design__instance__displacement__max": 10.149, - "cts__design__instance__displacement__mean": 0.187, - "cts__design__instance__displacement__total": 2232.3, - "cts__design__instance__utilization": 0.213084, - "cts__design__instance__utilization__stdcell": 0.0367038, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 849512.0, - "cts__power__internal__total": 0.00530655, - "cts__power__leakage__total": 5.614e-07, - "cts__power__switching__total": 0.00407064, - "cts__power__total": 0.00937775, - "cts__route__wirelength__estimated": 68467, - "cts__runtime__total": "0:19.28", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.749818, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.481312, - "cts__timing__drv__setup_violation_count": 277, - "cts__timing__setup__tns": -21670.9, - "cts__timing__setup__ws": -193.302, - "design__io__hpwl": 27463640, - "design__violations": 0, - "detailedplace__cpu__total": 6.64, - "detailedplace__design__core__area": 30460, - "detailedplace__design__die__area": 31942.3, - "detailedplace__design__instance__area": 6375.88, - "detailedplace__design__instance__area__macros": 5577.25, - "detailedplace__design__instance__area__stdcell": 798.634, - "detailedplace__design__instance__count": 10643, - "detailedplace__design__instance__count__macros": 21, - "detailedplace__design__instance__count__stdcell": 10622, - "detailedplace__design__instance__displacement__max": 3.555, - "detailedplace__design__instance__displacement__mean": 0.132, - "detailedplace__design__instance__displacement__total": 1409.55, - "detailedplace__design__instance__utilization": 0.20932, - "detailedplace__design__instance__utilization__stdcell": 0.0320959, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 506776.0, - "detailedplace__power__internal__total": 0.00380856, - "detailedplace__power__leakage__total": 4.81407e-07, - "detailedplace__power__switching__total": 0.00293172, - "detailedplace__power__total": 0.00674076, - "detailedplace__route__wirelength__estimated": 66007.6, - "detailedplace__runtime__total": "0:07.04", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.750346, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.406788, - "detailedplace__timing__drv__setup_violation_count": 267, - "detailedplace__timing__setup__tns": -21476.1, - "detailedplace__timing__setup__ws": -158.362, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 1089, - "detailedroute__route__drc_errors__iter:2": 132, - "detailedroute__route__drc_errors__iter:3": 91, - "detailedroute__route__drc_errors__iter:4": 8, - "detailedroute__route__drc_errors__iter:5": 1, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 6678, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 56449, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 56449, - "detailedroute__route__wirelength": 72639, - "detailedroute__route__wirelength__iter:1": 72757, - "detailedroute__route__wirelength__iter:2": 72681, - "detailedroute__route__wirelength__iter:3": 72626, - "detailedroute__route__wirelength__iter:4": 72634, - "detailedroute__route__wirelength__iter:5": 72639, - "detailedroute__route__wirelength__iter:6": 72639, - "finish__clock__skew__hold": 145.943, - "finish__clock__skew__setup": 127.465, - "finish__cpu__total": 13.31, - "finish__design__core__area": 30460, - "finish__design__die__area": 31942.3, - "finish__design__instance__area": 6505.13, - "finish__design__instance__area__macros": 5577.25, - "finish__design__instance__area__stdcell": 927.886, - "finish__design__instance__count": 12095, - "finish__design__instance__count__class:buffer": 180, - "finish__design__instance__count__class:clock_buffer": 35, - "finish__design__instance__count__class:clock_inverter": 27, - "finish__design__instance__count__class:fill_cell": 73306, - "finish__design__instance__count__class:inverter": 975, - "finish__design__instance__count__class:macro": 21, - "finish__design__instance__count__class:multi_input_combinational_cell": 2696, - "finish__design__instance__count__class:sequential_cell": 518, - "finish__design__instance__count__class:tap_cell": 5820, - "finish__design__instance__count__class:timing_repair_buffer": 1823, - "finish__design__instance__count__macros": 21, - "finish__design__instance__count__stdcell": 12074, - "finish__design__instance__utilization": 0.213563, - "finish__design__instance__utilization__stdcell": 0.0372903, - "finish__design__io": 388, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 11, - "finish__mem__peak": 451564.0, - "finish__power__internal__total": 0.00537871, - "finish__power__leakage__total": 5.70732e-07, - "finish__power__switching__total": 0.00415045, - "finish__power__total": 0.00952973, - "finish__runtime__total": "0:13.74", - "finish__timing__drv__hold_violation_count": 118, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.761079, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.338253, - "finish__timing__drv__setup_violation_count": 275, - "finish__timing__setup__tns": -23305.6, - "finish__timing__setup__ws": -207.715, - "finish__timing__wns_percent_delay": -28.758045, - "finish_merge__cpu__total": 4.77, - "finish_merge__mem__peak": 581808.0, - "finish_merge__runtime__total": "0:05.22", - "floorplan__cpu__total": 6.51, - "floorplan__design__core__area": 30460, - "floorplan__design__die__area": 31942.3, - "floorplan__design__instance__area": 6109.26, - "floorplan__design__instance__area__macros": 5577.25, - "floorplan__design__instance__area__stdcell": 532.01, - "floorplan__design__instance__count": 4398, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 21, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 4377, - "floorplan__design__instance__utilization": 0.200566, - "floorplan__design__instance__utilization__stdcell": 0.0213806, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1398, - "floorplan__mem__peak": 230680.0, - "floorplan__power__internal__total": 0.00333866, - "floorplan__power__leakage__total": 4.01093e-07, - "floorplan__power__switching__total": 0.00101077, - "floorplan__power__total": 0.00434983, - "floorplan__runtime__total": "0:06.68", - "floorplan__timing__setup__tns": -1121.41, - "floorplan__timing__setup__ws": -24.782, - "floorplan_io__cpu__total": 2.03, - "floorplan_io__mem__peak": 217700.0, - "floorplan_io__runtime__total": "0:02.15", - "floorplan_macro__cpu__total": 552.37, - "floorplan_macro__mem__peak": 221020.0, - "floorplan_macro__runtime__total": "0:38.02", - "floorplan_pdn__cpu__total": 6.85, - "floorplan_pdn__mem__peak": 369820.0, - "floorplan_pdn__runtime__total": "0:07.14", - "floorplan_tap__cpu__total": 2.07, - "floorplan_tap__mem__peak": 217852.0, - "floorplan_tap__runtime__total": "0:02.22", - "floorplan_tdms__cpu__total": 0.21, - "floorplan_tdms__mem__peak": 99608.0, - "floorplan_tdms__runtime__total": "0:00.25", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 1084.21, - "globalplace__design__core__area": 30460, - "globalplace__design__die__area": 31942.3, - "globalplace__design__instance__area": 6278.97, - "globalplace__design__instance__area__macros": 5577.25, - "globalplace__design__instance__area__stdcell": 701.721, - "globalplace__design__instance__count": 10218, - "globalplace__design__instance__count__macros": 21, - "globalplace__design__instance__count__stdcell": 10197, - "globalplace__design__instance__utilization": 0.206138, - "globalplace__design__instance__utilization__stdcell": 0.0282011, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 713180.0, - "globalplace__power__internal__total": 0.00337628, - "globalplace__power__leakage__total": 4.01093e-07, - "globalplace__power__switching__total": 0.00238877, - "globalplace__power__total": 0.00576545, - "globalplace__runtime__total": "0:55.18", - "globalplace__timing__setup__tns": -29232.4, - "globalplace__timing__setup__ws": -235.762, - "globalplace_io__cpu__total": 2.22, - "globalplace_io__mem__peak": 233052.0, - "globalplace_io__runtime__total": "0:02.39", - "globalplace_skip_io__cpu__total": 997.77, - "globalplace_skip_io__mem__peak": 259404.0, - "globalplace_skip_io__runtime__total": "0:42.15", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 135.582, - "globalroute__clock__skew__setup": 118.761, - "globalroute__cpu__total": 33.94, - "globalroute__design__core__area": 30460, - "globalroute__design__die__area": 31942.3, - "globalroute__design__instance__area": 6505.13, - "globalroute__design__instance__area__macros": 5577.25, - "globalroute__design__instance__area__stdcell": 927.886, - "globalroute__design__instance__count": 12095, - "globalroute__design__instance__count__hold_buffer": 169, - "globalroute__design__instance__count__macros": 21, - "globalroute__design__instance__count__setup_buffer": 13, - "globalroute__design__instance__count__stdcell": 12074, - "globalroute__design__instance__displacement__max": 4.698, - "globalroute__design__instance__displacement__mean": 0.092, - "globalroute__design__instance__displacement__total": 1115.69, - "globalroute__design__instance__utilization": 0.213563, - "globalroute__design__instance__utilization__stdcell": 0.0372903, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 988096.0, - "globalroute__power__internal__total": 0.00535859, - "globalroute__power__leakage__total": 5.70732e-07, - "globalroute__power__switching__total": 0.00427315, - "globalroute__power__total": 0.00963231, - "globalroute__route__wirelength__estimated": 69448.3, - "globalroute__runtime__total": "0:24.88", - "globalroute__timing__clock__slack": -189.801, - "globalroute__timing__drv__hold_violation_count": 1, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.736509, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.441556, - "globalroute__timing__drv__setup_violation_count": 273, - "globalroute__timing__setup__tns": -22369.5, - "globalroute__timing__setup__ws": -189.801, - "placeopt__cpu__total": 6.21, - "placeopt__design__core__area": 30460, - "placeopt__design__die__area": 31942.3, - "placeopt__design__instance__area": 6375.88, - "placeopt__design__instance__area__macros": 5577.25, - "placeopt__design__instance__area__stdcell": 798.634, - "placeopt__design__instance__count": 10643, - "placeopt__design__instance__count__macros": 21, - "placeopt__design__instance__count__stdcell": 10622, - "placeopt__design__instance__utilization": 0.20932, - "placeopt__design__instance__utilization__stdcell": 0.0320959, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 505492.0, - "placeopt__power__internal__total": 0.00380828, - "placeopt__power__leakage__total": 4.81407e-07, - "placeopt__power__switching__total": 0.00293079, - "placeopt__power__total": 0.00673955, - "placeopt__runtime__total": "0:06.77", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.745261, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.405609, - "placeopt__timing__drv__setup_violation_count": 268, - "placeopt__timing__setup__tns": -21488.2, - "placeopt__timing__setup__ws": -159.186, - "run__flow__design": "aes-block", - "run__flow__generate_date": "2024-10-15 07:36", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16507-gd0e17f1a2", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "d38e365c-f83d-42d5-bf60-e61165d993bb", - "run__flow__variant": "base", - "synth__cpu__total": 5.89, - "synth__design__instance__area__stdcell": 2012.64242, - "synth__design__instance__count__stdcell": 4390.0, - "synth__mem__peak": 144896.0, - "synth__runtime__total": "0:06.25", - "total_time": "0:03:59.360000" -} \ No newline at end of file diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index ab5b4ed959..e0ea045709 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2314.54, + "value": 2130.06, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7332, + "value": 7258, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 12211, + "value": 10666, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1062, + "value": 928, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1262, + "value": 1593, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 82464, + "value": 62330, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -227.71, + "value": -63.56, "compare": ">=" }, "finish__design__instance__area": { - "value": 7468, + "value": 7348, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 531, + "value": 464, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 248, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -44.5, + "value": -17.84, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes-mbff/metadata-base-ok.json b/flow/designs/asap7/aes-mbff/metadata-base-ok.json deleted file mode 100644 index 9b889989f9..0000000000 --- a/flow/designs/asap7/aes-mbff/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 400.0000" - ], - "cts__clock__skew__hold": 16.3525, - "cts__clock__skew__setup": 13.7949, - "cts__cpu__total": 154.36, - "cts__design__core__area": 4255.19, - "cts__design__die__area": 4827.33, - "cts__design__instance__area": 2040.78, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 2040.78, - "cts__design__instance__count": 17628, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 427, - "cts__design__instance__count__stdcell": 17628, - "cts__design__instance__displacement__max": 2.354, - "cts__design__instance__displacement__mean": 0.025, - "cts__design__instance__displacement__total": 449.665, - "cts__design__instance__utilization": 0.479597, - "cts__design__instance__utilization__stdcell": 0.479597, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 673728.0, - "cts__power__internal__total": 0.0596064, - "cts__power__leakage__total": 1.40112e-06, - "cts__power__switching__total": 0.0854016, - "cts__power__total": 0.145009, - "cts__route__wirelength__estimated": 64366.2, - "cts__runtime__total": "2:43.27", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0553465, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.544952, - "cts__timing__drv__setup_violation_count": 84, - "cts__timing__setup__tns": -1076.63, - "cts__timing__setup__ws": -43.6577, - "design__io__hpwl": 10307829, - "design__violations": 0, - "detailedplace__cpu__total": 12.94, - "detailedplace__design__core__area": 4255.19, - "detailedplace__design__die__area": 4827.33, - "detailedplace__design__instance__area": 1976.3, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 1976.3, - "detailedplace__design__instance__count": 17118, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 17118, - "detailedplace__design__instance__displacement__max": 1.944, - "detailedplace__design__instance__displacement__mean": 0.245, - "detailedplace__design__instance__displacement__total": 4194.23, - "detailedplace__design__instance__utilization": 0.464446, - "detailedplace__design__instance__utilization__stdcell": 0.464446, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 301992.0, - "detailedplace__power__internal__total": 0.056128, - "detailedplace__power__leakage__total": 1.34632e-06, - "detailedplace__power__switching__total": 0.083354, - "detailedplace__power__total": 0.139483, - "detailedplace__route__wirelength__estimated": 62112.1, - "detailedplace__runtime__total": "0:13.64", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0555989, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.545498, - "detailedplace__timing__drv__setup_violation_count": 160, - "detailedplace__timing__setup__tns": -9672.05, - "detailedplace__timing__setup__ws": -89.7936, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2630, - "detailedroute__route__drc_errors__iter:2": 223, - "detailedroute__route__drc_errors__iter:3": 120, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 17513, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 172724, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 172724, - "detailedroute__route__wirelength": 77686, - "detailedroute__route__wirelength__iter:1": 78257, - "detailedroute__route__wirelength__iter:2": 77752, - "detailedroute__route__wirelength__iter:3": 77681, - "detailedroute__route__wirelength__iter:4": 77686, - "finish__clock__skew__hold": 20.0986, - "finish__clock__skew__setup": 18.0291, - "finish__cpu__total": 40.0, - "finish__design__core__area": 4255.19, - "finish__design__die__area": 4827.33, - "finish__design__instance__area": 2052.24, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 2052.24, - "finish__design__instance__count": 17734, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 17734, - "finish__design__instance__utilization": 0.482291, - "finish__design__instance__utilization__stdcell": 0.482291, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.764297, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00581264, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.020413, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.024551, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.749587, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.024551, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 747676.0, - "finish__power__internal__total": 0.0602057, - "finish__power__leakage__total": 1.4121e-06, - "finish__power__switching__total": 0.0907213, - "finish__power__total": 0.150928, - "finish__runtime__total": "0:42.34", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0270517, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.513724, - "finish__timing__drv__setup_violation_count": 156, - "finish__timing__setup__tns": -3510.37, - "finish__timing__setup__ws": -63.8732, - "finish__timing__wns_percent_delay": -11.82903, - "finish_merge__cpu__total": 2.6, - "finish_merge__mem__peak": 523188.0, - "finish_merge__runtime__total": "0:02.91", - "floorplan__cpu__total": 45.92, - "floorplan__design__core__area": 4255.19, - "floorplan__design__die__area": 4827.33, - "floorplan__design__instance__area": 1729.89, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 1729.89, - "floorplan__design__instance__count": 16006, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 1, - "floorplan__design__instance__count__stdcell": 16006, - "floorplan__design__instance__utilization": 0.406536, - "floorplan__design__instance__utilization__stdcell": 0.406536, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 8459, - "floorplan__mem__peak": 274468.0, - "floorplan__power__internal__total": 0.0464387, - "floorplan__power__leakage__total": 1.09851e-06, - "floorplan__power__switching__total": 0.064279, - "floorplan__power__total": 0.110719, - "floorplan__runtime__total": "0:46.15", - "floorplan__timing__setup__tns": -1088.1, - "floorplan__timing__setup__ws": -36.4441, - "floorplan_io__cpu__total": 1.3, - "floorplan_io__mem__peak": 235804.0, - "floorplan_io__runtime__total": "0:01.49", - "floorplan_macro__cpu__total": 1.37, - "floorplan_macro__mem__peak": 234792.0, - "floorplan_macro__runtime__total": "0:01.50", - "floorplan_pdn__cpu__total": 1.5, - "floorplan_pdn__mem__peak": 239532.0, - "floorplan_pdn__runtime__total": "0:01.68", - "floorplan_tap__cpu__total": 1.38, - "floorplan_tap__mem__peak": 225448.0, - "floorplan_tap__runtime__total": "0:01.51", - "floorplan_tdms__cpu__total": 1.39, - "floorplan_tdms__mem__peak": 234876.0, - "floorplan_tdms__runtime__total": "0:01.50", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 762.15, - "globalplace__design__core__area": 4255.19, - "globalplace__design__die__area": 4827.33, - "globalplace__design__instance__area": 1751.03, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 1751.03, - "globalplace__design__instance__count": 16731, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16731, - "globalplace__design__instance__utilization": 0.411505, - "globalplace__design__instance__utilization__stdcell": 0.411505, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 670852.0, - "globalplace__power__internal__total": 0.0469766, - "globalplace__power__leakage__total": 1.09851e-06, - "globalplace__power__switching__total": 0.0774282, - "globalplace__power__total": 0.124406, - "globalplace__runtime__total": "2:07.96", - "globalplace__timing__setup__tns": -10021.9, - "globalplace__timing__setup__ws": -92.6619, - "globalplace_io__cpu__total": 1.35, - "globalplace_io__mem__peak": 237656.0, - "globalplace_io__runtime__total": "0:01.54", - "globalplace_skip_io__cpu__total": 471.24, - "globalplace_skip_io__mem__peak": 258168.0, - "globalplace_skip_io__runtime__total": "0:33.78", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 14.6296, - "globalroute__clock__skew__setup": 12.6685, - "globalroute__cpu__total": 131.4, - "globalroute__design__core__area": 4255.19, - "globalroute__design__die__area": 4827.33, - "globalroute__design__instance__area": 2052.24, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 2052.24, - "globalroute__design__instance__count": 17734, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 100, - "globalroute__design__instance__count__stdcell": 17734, - "globalroute__design__instance__displacement__max": 2.862, - "globalroute__design__instance__displacement__mean": 0.01, - "globalroute__design__instance__displacement__total": 190.188, - "globalroute__design__instance__utilization": 0.482291, - "globalroute__design__instance__utilization__stdcell": 0.482291, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 767668.0, - "globalroute__power__internal__total": 0.0601891, - "globalroute__power__leakage__total": 1.4121e-06, - "globalroute__power__switching__total": 0.0896939, - "globalroute__power__total": 0.149884, - "globalroute__route__wirelength__estimated": 64809.6, - "globalroute__runtime__total": "2:00.44", - "globalroute__timing__clock__slack": -54.946, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.04167, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.536757, - "globalroute__timing__drv__setup_violation_count": 142, - "globalroute__timing__setup__tns": -2668.98, - "globalroute__timing__setup__ws": -54.9463, - "placeopt__cpu__total": 16.88, - "placeopt__design__core__area": 4255.19, - "placeopt__design__die__area": 4827.33, - "placeopt__design__instance__area": 1976.3, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 1976.3, - "placeopt__design__instance__count": 17118, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 17118, - "placeopt__design__instance__utilization": 0.464446, - "placeopt__design__instance__utilization__stdcell": 0.464446, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 533708.0, - "placeopt__power__internal__total": 0.056114, - "placeopt__power__leakage__total": 1.34632e-06, - "placeopt__power__switching__total": 0.0827457, - "placeopt__power__total": 0.138861, - "placeopt__runtime__total": "0:18.74", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0527618, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.545123, - "placeopt__timing__drv__setup_violation_count": 160, - "placeopt__timing__setup__tns": -9325.12, - "placeopt__timing__setup__ws": -84.0563, - "run__flow__design": "aes-mbff", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "e7b45a08-8914-4155-be6d-697141133b36", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 17.76, - "synth__design__instance__area__stdcell": 1715.0454, - "synth__design__instance__count__stdcell": 15941.0, - "synth__mem__peak": 336680.0, - "synth__runtime__total": "0:18.31", - "total_time": "0:09:56.760000" -} \ No newline at end of file diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index fb5fd15d09..5b87e6a78e 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 89339, + "value": 76679, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -83.87, + "value": -42.46, "compare": ">=" }, "finish__design__instance__area": { - "value": 2360, + "value": 2272, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -24.19, + "value": -15.57, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes/BUILD.bazel b/flow/designs/asap7/aes/BUILD.bazel new file mode 100644 index 0000000000..2ff325bb42 --- /dev/null +++ b/flow/designs/asap7/aes/BUILD.bazel @@ -0,0 +1,47 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_synth") + +BLACKBOXES = [ + "aes_sbox", + "aes_key_expand_128", + "aes_cipher_top", +] + +[orfs_synth( + name = "{name}_netlist_synth".format(name = name), + arguments = { + "SDC_FILE": "$(location :constraint.sdc)", + "SYNTH_BLACKBOXES": " ".join([b for b in BLACKBOXES if b != name]), + }, + data = [":constraint.sdc"], + module_top = name, + variant = "netlist", + verilog_files = ["//flow/designs/src/aes:verilog"], +) for name in BLACKBOXES] + +[filegroup( + name = "{name}_netlist".format(name = name), + srcs = ["{name}_netlist_synth".format(name = name)], + output_group = "1_synth.v", +) for name in BLACKBOXES] + +filegroup( + name = "netlists", + srcs = [":{}_netlist".format(name) for name in BLACKBOXES], +) + +orfs_flow( + name = "aes_cipher_top", + arguments = { + "ABC_AREA": "1", + "CORE_UTILIZATION": "40", + "CORE_ASPECT_RATIO": "1", + "CORE_MARGIN": "2", + "PLACE_DENSITY": "0.65", + "TNS_END_PERCENT": "100", + }, + sources = { + "SDC_FILE": [":constraint.sdc"], + "SYNTH_NETLIST_FILES": [":netlists"], + }, + top = "aes_cipher_top", +) diff --git a/flow/designs/asap7/aes/README.md b/flow/designs/asap7/aes/README.md new file mode 100644 index 0000000000..7e51fb9d37 --- /dev/null +++ b/flow/designs/asap7/aes/README.md @@ -0,0 +1,28 @@ +# Parallel synthesis with SYNTH_BLACKBOXES + +For large designs, it can be useful to split synthesis for the +major blocks and combine the synthesized result. + +SYNTH_HIERARCHICAL=1 and SYNTH_MINIMUM_KEEP_SIZE can be used to adjust which +modules are flattened and which are kept. + +A module that is not flattened, can be built separately without any +loss in quality of results and combined as shown below. The module +that is built separately be built with and without SYNTH_HIERARCHICAL=1. + +1. Synthesize aes_key_expand_128 module + + make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=blackbox clean_synth synth +2. Synthesize top module, which could happen in parallel to 1 but with aes_key_expand_128 blacklisted: + + make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=top clean_synth synth +3. Combine the synthesis results above: + + make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine clean_synth synth + +4. View final result: + + make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine + make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine gui_final + +![alt text](final.png) \ No newline at end of file diff --git a/flow/designs/asap7/aes/autotuner.json b/flow/designs/asap7/aes/autotuner.json index 8430818c92..17f3ae6309 100644 --- a/flow/designs/asap7/aes/autotuner.json +++ b/flow/designs/asap7/aes/autotuner.json @@ -4,7 +4,7 @@ "type": "float", "minmax": [ 300, - 400 + 600 ], "step": 0 }, @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk index fa660b726e..a8cb544a32 100644 --- a/flow/designs/asap7/aes/config.mk +++ b/flow/designs/asap7/aes/config.mk @@ -15,3 +15,17 @@ export PLACE_DENSITY = 0.65 export TNS_END_PERCENT = 100 export EQUIVALENCE_CHECK ?= 1 export REMOVE_CELLS_FOR_EQY = TAPCELL* + +ifeq ($(FLOW_VARIANT),top) + export DESIGN_NAME = aes_cipher_top + export SYNTH_BLACKBOXES = aes_key_expand_128 +else ifeq ($(FLOW_VARIANT),blackbox) + export DESIGN_NAME = aes_key_expand_128 +else ifeq ($(FLOW_VARIANT),combine) + export EQUIVALENCE_CHECK = 0 +# List blackbox twice to demonstrates that duplicate modules are ignored. + export SYNTH_NETLIST_FILES = \ + $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/top/1_synth.v \ + $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \ + $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v +endif diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes/constraint.sdc +++ b/flow/designs/asap7/aes/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes/final.png b/flow/designs/asap7/aes/final.png new file mode 100644 index 0000000000..1b82a40ae0 Binary files /dev/null and b/flow/designs/asap7/aes/final.png differ diff --git a/flow/designs/asap7/aes/metadata-base-ok.json b/flow/designs/asap7/aes/metadata-base-ok.json deleted file mode 100644 index 1519e5952d..0000000000 --- a/flow/designs/asap7/aes/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 400.0000" - ], - "cts__clock__skew__hold": 12.9806, - "cts__clock__skew__setup": 7.99995, - "cts__cpu__total": 176.9, - "cts__design__core__area": 4255.19, - "cts__design__die__area": 4827.33, - "cts__design__instance__area": 2040.21, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 2040.21, - "cts__design__instance__count": 17629, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 433, - "cts__design__instance__count__stdcell": 17629, - "cts__design__instance__displacement__max": 2.366, - "cts__design__instance__displacement__mean": 0.028, - "cts__design__instance__displacement__total": 505.672, - "cts__design__instance__utilization": 0.479464, - "cts__design__instance__utilization__stdcell": 0.479464, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 663152.0, - "cts__power__internal__total": 0.0597148, - "cts__power__leakage__total": 1.40168e-06, - "cts__power__switching__total": 0.0848525, - "cts__power__total": 0.144569, - "cts__route__wirelength__estimated": 62300.5, - "cts__runtime__total": "2:04.40", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0533113, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.545024, - "cts__timing__drv__setup_violation_count": 92, - "cts__timing__setup__tns": -979.47, - "cts__timing__setup__ws": -32.5157, - "design__io__hpwl": 10307829, - "design__violations": 0, - "detailedplace__cpu__total": 12.78, - "detailedplace__design__core__area": 4255.19, - "detailedplace__design__die__area": 4827.33, - "detailedplace__design__instance__area": 1976.3, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 1976.3, - "detailedplace__design__instance__count": 17118, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 17118, - "detailedplace__design__instance__displacement__max": 1.944, - "detailedplace__design__instance__displacement__mean": 0.245, - "detailedplace__design__instance__displacement__total": 4194.23, - "detailedplace__design__instance__utilization": 0.464446, - "detailedplace__design__instance__utilization__stdcell": 0.464446, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 297972.0, - "detailedplace__power__internal__total": 0.0561199, - "detailedplace__power__leakage__total": 1.34632e-06, - "detailedplace__power__switching__total": 0.0828795, - "detailedplace__power__total": 0.139001, - "detailedplace__route__wirelength__estimated": 62112.1, - "detailedplace__runtime__total": "0:13.00", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0535131, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.54509, - "detailedplace__timing__drv__setup_violation_count": 160, - "detailedplace__timing__setup__tns": -9540.08, - "detailedplace__timing__setup__ws": -87.6338, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2887, - "detailedroute__route__drc_errors__iter:2": 244, - "detailedroute__route__drc_errors__iter:3": 134, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 17472, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 169440, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 169440, - "detailedroute__route__wirelength": 75438, - "detailedroute__route__wirelength__iter:1": 75998, - "detailedroute__route__wirelength__iter:2": 75482, - "detailedroute__route__wirelength__iter:3": 75432, - "detailedroute__route__wirelength__iter:4": 75438, - "finish__clock__skew__hold": 14.1027, - "finish__clock__skew__setup": 10.9521, - "finish__cpu__total": 32.83, - "finish__design__core__area": 4255.19, - "finish__design__die__area": 4827.33, - "finish__design__instance__area": 2046.81, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 2046.81, - "finish__design__instance__count": 17693, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 17693, - "finish__design__instance__utilization": 0.481016, - "finish__design__instance__utilization__stdcell": 0.481016, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.764345, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00576628, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0246168, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0209912, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.745383, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0209912, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 749744.0, - "finish__power__internal__total": 0.0600737, - "finish__power__leakage__total": 1.4081e-06, - "finish__power__switching__total": 0.0898561, - "finish__power__total": 0.149931, - "finish__runtime__total": "0:33.31", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.00606878, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.538025, - "finish__timing__drv__setup_violation_count": 156, - "finish__timing__setup__tns": -3151.53, - "finish__timing__setup__ws": -59.9209, - "finish__timing__wns_percent_delay": -11.441319, - "finish_merge__cpu__total": 2.62, - "finish_merge__mem__peak": 523280.0, - "finish_merge__runtime__total": "0:02.93", - "floorplan__cpu__total": 47.57, - "floorplan__design__core__area": 4255.19, - "floorplan__design__die__area": 4827.33, - "floorplan__design__instance__area": 1729.89, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 1729.89, - "floorplan__design__instance__count": 16006, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 1, - "floorplan__design__instance__count__stdcell": 16006, - "floorplan__design__instance__utilization": 0.406536, - "floorplan__design__instance__utilization__stdcell": 0.406536, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 8459, - "floorplan__mem__peak": 273636.0, - "floorplan__power__internal__total": 0.0464387, - "floorplan__power__leakage__total": 1.09851e-06, - "floorplan__power__switching__total": 0.064279, - "floorplan__power__total": 0.110719, - "floorplan__runtime__total": "0:47.77", - "floorplan__timing__setup__tns": -1088.1, - "floorplan__timing__setup__ws": -36.4441, - "floorplan_io__cpu__total": 1.32, - "floorplan_io__mem__peak": 234548.0, - "floorplan_io__runtime__total": "0:01.47", - "floorplan_macro__cpu__total": 1.35, - "floorplan_macro__mem__peak": 234172.0, - "floorplan_macro__runtime__total": "0:01.50", - "floorplan_pdn__cpu__total": 1.49, - "floorplan_pdn__mem__peak": 237972.0, - "floorplan_pdn__runtime__total": "0:01.65", - "floorplan_tap__cpu__total": 1.37, - "floorplan_tap__mem__peak": 224564.0, - "floorplan_tap__runtime__total": "0:01.50", - "floorplan_tdms__cpu__total": 1.37, - "floorplan_tdms__mem__peak": 234168.0, - "floorplan_tdms__runtime__total": "0:01.50", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 864.68, - "globalplace__design__core__area": 4255.19, - "globalplace__design__die__area": 4827.33, - "globalplace__design__instance__area": 1751.03, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 1751.03, - "globalplace__design__instance__count": 16731, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16731, - "globalplace__design__instance__utilization": 0.411505, - "globalplace__design__instance__utilization__stdcell": 0.411505, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 669520.0, - "globalplace__power__internal__total": 0.0469766, - "globalplace__power__leakage__total": 1.09851e-06, - "globalplace__power__switching__total": 0.0774282, - "globalplace__power__total": 0.124406, - "globalplace__runtime__total": "1:48.49", - "globalplace__timing__setup__tns": -10021.9, - "globalplace__timing__setup__ws": -92.6619, - "globalplace_io__cpu__total": 1.38, - "globalplace_io__mem__peak": 236712.0, - "globalplace_io__runtime__total": "0:01.53", - "globalplace_skip_io__cpu__total": 421.45, - "globalplace_skip_io__mem__peak": 257716.0, - "globalplace_skip_io__runtime__total": "0:30.22", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 11.6357, - "globalroute__clock__skew__setup": 8.94073, - "globalroute__cpu__total": 81.71, - "globalroute__design__core__area": 4255.19, - "globalroute__design__die__area": 4827.33, - "globalroute__design__instance__area": 2046.81, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 2046.81, - "globalroute__design__instance__count": 17693, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 56, - "globalroute__design__instance__count__stdcell": 17693, - "globalroute__design__instance__displacement__max": 1.674, - "globalroute__design__instance__displacement__mean": 0.007, - "globalroute__design__instance__displacement__total": 135.54, - "globalroute__design__instance__utilization": 0.481016, - "globalroute__design__instance__utilization__stdcell": 0.481016, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 760468.0, - "globalroute__power__internal__total": 0.0600603, - "globalroute__power__leakage__total": 1.4081e-06, - "globalroute__power__switching__total": 0.0890287, - "globalroute__power__total": 0.14909, - "globalroute__route__wirelength__estimated": 62601.9, - "globalroute__runtime__total": "1:03.94", - "globalroute__timing__clock__slack": -45.168, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0381674, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.561342, - "globalroute__timing__drv__setup_violation_count": 144, - "globalroute__timing__setup__tns": -2385.53, - "globalroute__timing__setup__ws": -45.1679, - "placeopt__cpu__total": 12.72, - "placeopt__design__core__area": 4255.19, - "placeopt__design__die__area": 4827.33, - "placeopt__design__instance__area": 1976.3, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 1976.3, - "placeopt__design__instance__count": 17118, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 17118, - "placeopt__design__instance__utilization": 0.464446, - "placeopt__design__instance__utilization__stdcell": 0.464446, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 533272.0, - "placeopt__power__internal__total": 0.056114, - "placeopt__power__leakage__total": 1.34632e-06, - "placeopt__power__switching__total": 0.0827457, - "placeopt__power__total": 0.138861, - "placeopt__runtime__total": "0:13.13", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0527618, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.545123, - "placeopt__timing__drv__setup_violation_count": 160, - "placeopt__timing__setup__tns": -9325.12, - "placeopt__timing__setup__ws": -84.0563, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "045b5f2d-92c6-42f4-8156-8eea88882412", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 24.67, - "synth__design__instance__area__stdcell": 1715.0454, - "synth__design__instance__count__stdcell": 15941.0, - "synth__mem__peak": 336416.0, - "synth__runtime__total": "0:26.06", - "total_time": "0:07:52.400000" -} \ No newline at end of file diff --git a/flow/designs/asap7/aes/rules-base.json b/flow/designs/asap7/aes/rules-base.json index aecfbcb273..5dfa3fd7a7 100644 --- a/flow/designs/asap7/aes/rules-base.json +++ b/flow/designs/asap7/aes/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1972.31, + "value": 1928.39, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2273, + "value": 2214, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19686, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1712, + "value": 1704, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 86754, + "value": 74787, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -79.92, + "value": -73.23, "compare": ">=" }, "finish__design__instance__area": { - "value": 2354, + "value": 2278, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 856, + "value": 852, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -23.72, + "value": -13.72, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes_lvt/config.mk b/flow/designs/asap7/aes_lvt/config.mk index e3d1779d9b..43b961430c 100644 --- a/flow/designs/asap7/aes_lvt/config.mk +++ b/flow/designs/asap7/aes_lvt/config.mk @@ -14,14 +14,6 @@ export CORE_MARGIN = 2 export PLACE_DENSITY = 0.65 export TNS_END_PERCENT = 100 -export ASAP7_USELVT = 1 -export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib - -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_R_220121a.gds -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_R_1x_220121a.lef +export ASAP7_USE_VT = LVT export RECOVER_POWER = 100 diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index e45d9100bd..a9b5a65d9c 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 400 +set clk_period 400 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/aes_lvt/metadata-base-ok.json b/flow/designs/asap7/aes_lvt/metadata-base-ok.json deleted file mode 100644 index 1fccae70ba..0000000000 --- a/flow/designs/asap7/aes_lvt/metadata-base-ok.json +++ /dev/null @@ -1,274 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 400.0000" - ], - "cts__clock__skew__hold": 13.0227, - "cts__clock__skew__setup": 8.97402, - "cts__cpu__total": 18.54, - "cts__design__core__area": 4276.37, - "cts__design__die__area": 4837.48, - "cts__design__instance__area": 1970.12, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 1970.12, - "cts__design__instance__count": 17127, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 52, - "cts__design__instance__count__stdcell": 17127, - "cts__design__instance__displacement__max": 1.992, - "cts__design__instance__displacement__mean": 0.003, - "cts__design__instance__displacement__total": 57.962, - "cts__design__instance__utilization": 0.460699, - "cts__design__instance__utilization__stdcell": 0.460699, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 20, - "cts__mem__peak": 991920.0, - "cts__power__internal__total": 0.0620383, - "cts__power__leakage__total": 4.12031e-06, - "cts__power__switching__total": 0.0890563, - "cts__power__total": 0.151099, - "cts__route__wirelength__estimated": 59327.4, - "cts__runtime__total": "0:19.32", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.273282, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.657661, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.385608, - "design__io__hpwl": 10278121, - "design__violations": 0, - "detailedplace__cpu__total": 14.05, - "detailedplace__design__core__area": 4276.37, - "detailedplace__design__die__area": 4837.48, - "detailedplace__design__instance__area": 1942.93, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 1942.93, - "detailedplace__design__instance__count": 17009, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 17009, - "detailedplace__design__instance__displacement__max": 2.274, - "detailedplace__design__instance__displacement__mean": 0.242, - "detailedplace__design__instance__displacement__total": 4127.79, - "detailedplace__design__instance__utilization": 0.454341, - "detailedplace__design__instance__utilization__stdcell": 0.454341, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 20, - "detailedplace__mem__peak": 401496.0, - "detailedplace__power__internal__total": 0.0601808, - "detailedplace__power__leakage__total": 3.95001e-06, - "detailedplace__power__switching__total": 0.0877921, - "detailedplace__power__total": 0.147977, - "detailedplace__route__wirelength__estimated": 60364.4, - "detailedplace__runtime__total": "0:14.31", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.27405, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.595264, - "detailedplace__timing__drv__setup_violation_count": 122, - "detailedplace__timing__setup__tns": -2294.71, - "detailedplace__timing__setup__ws": -50.0204, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 21, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2429, - "detailedroute__route__drc_errors__iter:2": 192, - "detailedroute__route__drc_errors__iter:3": 128, - "detailedroute__route__drc_errors__iter:4": 3, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 16955, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 161350, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 161350, - "detailedroute__route__wirelength": 71429, - "detailedroute__route__wirelength__iter:1": 71974, - "detailedroute__route__wirelength__iter:2": 71466, - "detailedroute__route__wirelength__iter:3": 71427, - "detailedroute__route__wirelength__iter:4": 71429, - "detailedroute__route__wirelength__iter:5": 71429, - "finish__clock__skew__hold": 15.3307, - "finish__clock__skew__setup": 13.243, - "finish__cpu__total": 31.95, - "finish__design__core__area": 4276.37, - "finish__design__die__area": 4837.48, - "finish__design__instance__area": 1969.66, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 1969.66, - "finish__design__instance__count": 17177, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 17177, - "finish__design__instance__utilization": 0.46059, - "finish__design__instance__utilization__stdcell": 0.46059, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.764146, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0058032, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.023122, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0214601, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.746878, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0214601, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 20, - "finish__mem__peak": 848224.0, - "finish__power__internal__total": 0.0623869, - "finish__power__leakage__total": 4.01321e-06, - "finish__power__switching__total": 0.0936544, - "finish__power__total": 0.156045, - "finish__runtime__total": "0:32.73", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.303262, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.628592, - "finish__timing__drv__setup_violation_count": 42, - "finish__timing__setup__tns": -211.248, - "finish__timing__setup__ws": -12.9368, - "finish__timing__wns_percent_delay": -2.751359, - "finish_merge__cpu__total": 2.62, - "finish_merge__mem__peak": 523404.0, - "finish_merge__runtime__total": "0:02.90", - "floorplan__cpu__total": 8.57, - "floorplan__design__core__area": 4276.37, - "floorplan__design__die__area": 4837.48, - "floorplan__design__instance__area": 1719.08, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 1719.08, - "floorplan__design__instance__count": 15894, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 15894, - "floorplan__design__instance__utilization": 0.401996, - "floorplan__design__instance__utilization__stdcell": 0.401996, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 42, - "floorplan__mem__peak": 377364.0, - "floorplan__power__internal__total": 0.0505249, - "floorplan__power__leakage__total": 2.31449e-06, - "floorplan__power__switching__total": 0.0680471, - "floorplan__power__total": 0.118574, - "floorplan__runtime__total": "0:08.78", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.0540679, - "floorplan_io__cpu__total": 2.54, - "floorplan_io__mem__peak": 338840.0, - "floorplan_io__runtime__total": "0:02.74", - "floorplan_macro__cpu__total": 2.51, - "floorplan_macro__mem__peak": 338444.0, - "floorplan_macro__runtime__total": "0:02.77", - "floorplan_pdn__cpu__total": 2.72, - "floorplan_pdn__mem__peak": 342300.0, - "floorplan_pdn__runtime__total": "0:02.94", - "floorplan_tap__cpu__total": 2.57, - "floorplan_tap__mem__peak": 329000.0, - "floorplan_tap__runtime__total": "0:02.77", - "floorplan_tdms__cpu__total": 2.54, - "floorplan_tdms__mem__peak": 338332.0, - "floorplan_tdms__runtime__total": "0:02.75", - "flow__errors__count": 0, - "flow__warnings__count": 20, - "globalplace__cpu__total": 822.68, - "globalplace__design__core__area": 4276.37, - "globalplace__design__die__area": 4837.48, - "globalplace__design__instance__area": 1740.31, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 1740.31, - "globalplace__design__instance__count": 16622, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16622, - "globalplace__design__instance__utilization": 0.40696, - "globalplace__design__instance__utilization__stdcell": 0.40696, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 20, - "globalplace__mem__peak": 1021384.0, - "globalplace__power__internal__total": 0.05123, - "globalplace__power__leakage__total": 2.31449e-06, - "globalplace__power__switching__total": 0.0816172, - "globalplace__power__total": 0.13285, - "globalplace__runtime__total": "1:49.86", - "globalplace__timing__setup__tns": -4855.4, - "globalplace__timing__setup__ws": -60.3972, - "globalplace_io__cpu__total": 2.61, - "globalplace_io__mem__peak": 341020.0, - "globalplace_io__runtime__total": "0:02.80", - "globalplace_skip_io__cpu__total": 466.67, - "globalplace_skip_io__mem__peak": 361280.0, - "globalplace_skip_io__runtime__total": "0:34.61", - "globalroute__cpu__total": 22.4, - "globalroute__mem__peak": 1086112.0, - "globalroute__runtime__total": "0:23.32", - "globalroute__timing__clock__slack": "N/A", - "placeopt__cpu__total": 14.52, - "placeopt__design__core__area": 4276.37, - "placeopt__design__die__area": 4837.48, - "placeopt__design__instance__area": 1942.93, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 1942.93, - "placeopt__design__instance__count": 17009, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 17009, - "placeopt__design__instance__utilization": 0.454341, - "placeopt__design__instance__utilization__stdcell": 0.454341, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 20, - "placeopt__mem__peak": 884468.0, - "placeopt__power__internal__total": 0.0601568, - "placeopt__power__leakage__total": 3.95001e-06, - "placeopt__power__switching__total": 0.0876708, - "placeopt__power__total": 0.147832, - "placeopt__runtime__total": "0:15.20", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.277509, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.636503, - "placeopt__timing__drv__setup_violation_count": 116, - "placeopt__timing__setup__tns": -1974.36, - "placeopt__timing__setup__ws": -44.2044, - "run__flow__design": "aes_lvt", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "76fb84d3-0598-4b88-aece-0611bc3cc79e", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 19.13, - "synth__design__instance__area__stdcell": 1718.85078, - "synth__design__instance__count__stdcell": 15892.0, - "synth__mem__peak": 340056.0, - "synth__runtime__total": "0:19.78", - "total_time": "0:04:57.580000" -} \ No newline at end of file diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 81b9c2ea2b..d531c2e47a 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 77902, + "value": 72549, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -31.87, + "value": -45.99, "compare": ">=" }, "finish__design__instance__area": { - "value": 2142, + "value": 2103, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -13.0, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/cva6/autotuner.json b/flow/designs/asap7/cva6/autotuner.json new file mode 100644 index 0000000000..a7315e9578 --- /dev/null +++ b/flow/designs/asap7/cva6/autotuner.json @@ -0,0 +1,43 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 1000, + 1300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 65, + 75 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.5, + 2 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + } +} diff --git a/flow/designs/asap7/cva6/canonicalize.tcl b/flow/designs/asap7/cva6/canonicalize.tcl new file mode 100644 index 0000000000..c2911a02f8 --- /dev/null +++ b/flow/designs/asap7/cva6/canonicalize.tcl @@ -0,0 +1,4 @@ +# Remove rvfi_probes_o interface since contributes 4k ports and connections +# (many of which are buffers tied to tie cells) + +delete cva6/o:rvfi_probes_o* diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk new file mode 100644 index 0000000000..5144d99aec --- /dev/null +++ b/flow/designs/asap7/cva6/config.mk @@ -0,0 +1,110 @@ +export PLATFORM = asap7 + +export DESIGN_NAME = cva6 + +# Some files are listed specifically vs. sorted wildcard to control the order +# (makes Verific happy) +export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \ + $(SRC_HOME)/core/include/config_pkg.sv \ + $(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \ + $(SRC_HOME)/core/include/riscv_pkg.sv \ + $(SRC_HOME)/core/include/ariane_pkg.sv \ + $(SRC_HOME)/core/include/build_config_pkg.sv \ + $(SRC_HOME)/core/include/std_cache_pkg.sv \ + $(SRC_HOME)/core/include/wt_cache_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \ + $(sort $(wildcard $(SRC_HOME)/core/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ + $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ + $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \ + $(PLATFORM_DIR)/verilog/fakeram7_64x25.sv + +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include + +export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \ + $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \ + $(PLATFORM_DIR)/lef/fakeram7_64x25.lef + +export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +export CORE_UTILIZATION = 70 +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 3 3 +export PLACE_DENSITY = 0.69 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 + +export SYNTH_HDL_FRONTEND = slang + +export ASAP7_USE_VT = RVT LVT SLVT + +export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120 + +# Remove rvfi_probes_o interface +export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc new file mode 100644 index 0000000000..724d7f20ea --- /dev/null +++ b/flow/designs/asap7/cva6/constraint.sdc @@ -0,0 +1,36 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1200 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period + +# #set_dont_touch to keep sram as black boxes +# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[*].i_tag_sram +# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[*].i_data_sram +# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram +# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram +# #constraint the timing to and from the sram black boxes +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] +# set_input_delay -clock main_clk -max $input_delay \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*] + +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] +# set_output_delay $output_delay -max -clock main_clk \ +# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] + + +set_false_path -to [get_ports {rvfi_probes_o}] diff --git a/flow/designs/intel16/gcd/rules-base.json b/flow/designs/asap7/cva6/rules-base.json similarity index 85% rename from flow/designs/intel16/gcd/rules-base.json rename to flow/designs/asap7/cva6/rules-base.json index 1fdd7a9d40..e064d238c2 100644 --- a/flow/designs/intel16/gcd/rules-base.json +++ b/flow/designs/asap7/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 191.22, + "value": 18975.35, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 210, + "value": 19709, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 512, + "value": 123443, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 40, + "value": 10734, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 32, + "value": 10734, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3020, + "value": 716033, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -82.95, "compare": ">=" }, "finish__design__instance__area": { - "value": 360, + "value": 19864, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 16, + "value": 5367, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc index 71e846bd4a..1dd0000a50 100644 --- a/flow/designs/asap7/ethmac/constraint.sdc +++ b/flow/designs/asap7/ethmac/constraint.sdc @@ -3,8 +3,8 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,12 +20,12 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] set_max_fanout 10 [current_design] diff --git a/flow/designs/asap7/ethmac/metadata-base-ok.json b/flow/designs/asap7/ethmac/metadata-base-ok.json deleted file mode 100644 index 9510a2bfc7..0000000000 --- a/flow/designs/asap7/ethmac/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 3, - "constraints__clocks__details": [ - "mrx_clk_pad_i: 300.0000", - "mtx_clk_pad_i: 300.0000", - "wb_clk_i: 1000.0000" - ], - "cts__clock__skew__hold": 165.251, - "cts__clock__skew__setup": 179.068, - "cts__cpu__total": 58.86, - "cts__design__core__area": 18606, - "cts__design__die__area": 19753.7, - "cts__design__instance__area": 8792.85, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 8792.85, - "cts__design__instance__count": 63699, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 91, - "cts__design__instance__count__stdcell": 63699, - "cts__design__instance__displacement__max": 1.991, - "cts__design__instance__displacement__mean": 0.001, - "cts__design__instance__displacement__total": 90.058, - "cts__design__instance__utilization": 0.47258, - "cts__design__instance__utilization__stdcell": 0.47258, - "cts__design__io": 216, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 887232.0, - "cts__power__internal__total": 0.084753, - "cts__power__leakage__total": 7.29233e-06, - "cts__power__switching__total": 0.0254859, - "cts__power__total": 0.110246, - "cts__route__wirelength__estimated": 339560, - "cts__runtime__total": "0:59.81", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.191139, - "cts__timing__drv__max_fanout": 496, - "cts__timing__drv__max_fanout_limit": 10, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.42007, - "cts__timing__drv__setup_violation_count": 58, - "cts__timing__setup__tns": -4753.12, - "cts__timing__setup__ws": -139.831, - "design__io__hpwl": 7520039, - "design__violations": 0, - "detailedplace__cpu__total": 54.69, - "detailedplace__design__core__area": 18606, - "detailedplace__design__die__area": 19753.7, - "detailedplace__design__instance__area": 8480.25, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 8480.25, - "detailedplace__design__instance__count": 62647, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 62647, - "detailedplace__design__instance__displacement__max": 6.575, - "detailedplace__design__instance__displacement__mean": 0.27, - "detailedplace__design__instance__displacement__total": 16926.8, - "detailedplace__design__instance__utilization": 0.455779, - "detailedplace__design__instance__utilization__stdcell": 0.455779, - "detailedplace__design__io": 216, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 538052.0, - "detailedplace__power__internal__total": 0.0580327, - "detailedplace__power__leakage__total": 6.98059e-06, - "detailedplace__power__switching__total": 0.00641996, - "detailedplace__power__total": 0.0644597, - "detailedplace__route__wirelength__estimated": 335843, - "detailedplace__runtime__total": "0:55.20", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.191139, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 10, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.423849, - "detailedplace__timing__drv__setup_violation_count": 113, - "detailedplace__timing__setup__tns": -5420.71, - "detailedplace__timing__setup__ws": -177.915, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 14461, - "detailedroute__route__drc_errors__iter:2": 1111, - "detailedroute__route__drc_errors__iter:3": 610, - "detailedroute__route__drc_errors__iter:4": 15, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 61261, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 666408, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 666408, - "detailedroute__route__wirelength": 486429, - "detailedroute__route__wirelength__iter:1": 487983, - "detailedroute__route__wirelength__iter:2": 486564, - "detailedroute__route__wirelength__iter:3": 486406, - "detailedroute__route__wirelength__iter:4": 486429, - "detailedroute__route__wirelength__iter:5": 486429, - "finish__clock__skew__hold": 174.705, - "finish__clock__skew__setup": 190.033, - "finish__cpu__total": 133.67, - "finish__design__core__area": 18606, - "finish__design__die__area": 19753.7, - "finish__design__instance__area": 8795.56, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 8795.56, - "finish__design__instance__count": 63720, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 63720, - "finish__design__instance__utilization": 0.472726, - "finish__design__instance__utilization__stdcell": 0.472726, - "finish__design__io": 216, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.745581, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.023827, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.094009, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0911129, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.675991, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0911129, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 1981368.0, - "finish__power__internal__total": 0.0848362, - "finish__power__leakage__total": 7.29577e-06, - "finish__power__switching__total": 0.0274942, - "finish__power__total": 0.112338, - "finish__runtime__total": "2:16.32", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0173482, - "finish__timing__drv__max_fanout": 496, - "finish__timing__drv__max_fanout_limit": 10, - "finish__timing__drv__max_slew": 72, - "finish__timing__drv__max_slew_limit": -0.318314, - "finish__timing__drv__setup_violation_count": 84, - "finish__timing__setup__tns": -3979.3, - "finish__timing__setup__ws": -156.115, - "finish__timing__wns_percent_delay": -30.42512, - "finish_merge__cpu__total": 6.74, - "finish_merge__mem__peak": 910576.0, - "finish_merge__runtime__total": "0:07.40", - "floorplan__cpu__total": 27.92, - "floorplan__design__core__area": 18606, - "floorplan__design__die__area": 19753.7, - "floorplan__design__instance__area": 7461.84, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 7461.84, - "floorplan__design__instance__count": 58742, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 1, - "floorplan__design__instance__count__stdcell": 58742, - "floorplan__design__instance__utilization": 0.401044, - "floorplan__design__instance__utilization__stdcell": 0.401044, - "floorplan__design__io": 216, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1824, - "floorplan__mem__peak": 436708.0, - "floorplan__power__internal__total": 0.0566802, - "floorplan__power__leakage__total": 5.62273e-06, - "floorplan__power__switching__total": 0.00389308, - "floorplan__power__total": 0.0605789, - "floorplan__runtime__total": "0:28.19", - "floorplan__timing__setup__tns": -2913.3, - "floorplan__timing__setup__ws": -134.238, - "floorplan_io__cpu__total": 1.97, - "floorplan_io__mem__peak": 299540.0, - "floorplan_io__runtime__total": "0:02.25", - "floorplan_macro__cpu__total": 1.84, - "floorplan_macro__mem__peak": 296684.0, - "floorplan_macro__runtime__total": "0:02.13", - "floorplan_pdn__cpu__total": 2.62, - "floorplan_pdn__mem__peak": 305164.0, - "floorplan_pdn__runtime__total": "0:02.90", - "floorplan_tap__cpu__total": 2.22, - "floorplan_tap__mem__peak": 262292.0, - "floorplan_tap__runtime__total": "0:02.41", - "floorplan_tdms__cpu__total": 1.57, - "floorplan_tdms__mem__peak": 296532.0, - "floorplan_tdms__runtime__total": "0:01.79", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 1345.96, - "globalplace__design__core__area": 18606, - "globalplace__design__die__area": 19753.7, - "globalplace__design__instance__area": 7528.24, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 7528.24, - "globalplace__design__instance__count": 61019, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 61019, - "globalplace__design__instance__utilization": 0.404612, - "globalplace__design__instance__utilization__stdcell": 0.404612, - "globalplace__design__io": 216, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 1067516.0, - "globalplace__power__internal__total": 0.0567726, - "globalplace__power__leakage__total": 5.62273e-06, - "globalplace__power__switching__total": 0.00596853, - "globalplace__power__total": 0.0627467, - "globalplace__runtime__total": "5:41.68", - "globalplace__timing__setup__tns": -23170.5, - "globalplace__timing__setup__ws": -174.859, - "globalplace_io__cpu__total": 2.03, - "globalplace_io__mem__peak": 305204.0, - "globalplace_io__runtime__total": "0:02.35", - "globalplace_skip_io__cpu__total": 355.55, - "globalplace_skip_io__mem__peak": 384528.0, - "globalplace_skip_io__runtime__total": "0:45.66", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 155.452, - "globalroute__clock__skew__setup": 170.069, - "globalroute__cpu__total": 211.6, - "globalroute__design__core__area": 18606, - "globalroute__design__die__area": 19753.7, - "globalroute__design__instance__area": 8795.56, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 8795.56, - "globalroute__design__instance__count": 63720, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 26, - "globalroute__design__instance__count__stdcell": 63720, - "globalroute__design__instance__displacement__max": 1.404, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 31.32, - "globalroute__design__instance__utilization": 0.472726, - "globalroute__design__instance__utilization__stdcell": 0.472726, - "globalroute__design__io": 216, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 13, - "globalroute__mem__peak": 1558048.0, - "globalroute__power__internal__total": 0.084767, - "globalroute__power__leakage__total": 7.29577e-06, - "globalroute__power__switching__total": 0.0267839, - "globalroute__power__total": 0.111558, - "globalroute__route__wirelength__estimated": 339813, - "globalroute__runtime__total": "2:19.76", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.186819, - "globalroute__timing__drv__max_fanout": 496, - "globalroute__timing__drv__max_fanout_limit": 10, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.127416, - "globalroute__timing__drv__setup_violation_count": 76, - "globalroute__timing__setup__tns": -4053.4, - "globalroute__timing__setup__ws": -152.683, - "placeopt__cpu__total": 46.58, - "placeopt__design__core__area": 18606, - "placeopt__design__die__area": 19753.7, - "placeopt__design__instance__area": 8480.25, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 8480.25, - "placeopt__design__instance__count": 62647, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 62647, - "placeopt__design__instance__utilization": 0.455779, - "placeopt__design__instance__utilization__stdcell": 0.455779, - "placeopt__design__io": 216, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 735476.0, - "placeopt__power__internal__total": 0.0580328, - "placeopt__power__leakage__total": 6.98059e-06, - "placeopt__power__switching__total": 0.00640747, - "placeopt__power__total": 0.0644472, - "placeopt__runtime__total": "0:47.44", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.192401, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 10, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.429858, - "placeopt__timing__drv__setup_violation_count": 118, - "placeopt__timing__setup__tns": -5413.15, - "placeopt__timing__setup__ws": -176.615, - "run__flow__design": "ethmac", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "8ec0925e-06d0-43f2-a1ab-e9ee25e4a4e1", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 65.38, - "synth__design__instance__area__stdcell": 7458.20946, - "synth__design__instance__count__stdcell": 58726.0, - "synth__mem__peak": 378876.0, - "synth__runtime__total": "1:20.92", - "total_time": "0:15:56.210000" -} \ No newline at end of file diff --git a/flow/designs/asap7/ethmac/rules-base.json b/flow/designs/asap7/ethmac/rules-base.json index 90d12d4d5e..c6e93e2063 100644 --- a/flow/designs/asap7/ethmac/rules-base.json +++ b/flow/designs/asap7/ethmac/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 8576.95, + "value": 8504.63, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9752, + "value": 9343, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 72044, + "value": 71068, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6265, + "value": 6180, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6265, + "value": 6180, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 559393, + "value": 232938, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -171.11, + "value": -144.87, "compare": ">=" }, "finish__design__instance__area": { - "value": 10115, + "value": 9507, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3132, + "value": 3090, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -46.51, + "value": -42.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ethmac_lvt/BUILD.bazel b/flow/designs/asap7/ethmac_lvt/BUILD.bazel new file mode 100644 index 0000000000..6bc3354348 --- /dev/null +++ b/flow/designs/asap7/ethmac_lvt/BUILD.bazel @@ -0,0 +1,24 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow") + +orfs_flow( + name = "ethmac_lvt", + arguments = { + # Faster builds + "SKIP_INCREMENTAL_REPAIR": "1", + "GPL_TIMING_DRIVEN": "0", + # Various + "SDC_FILE": "$(location :constraint.sdc)", + "ABC_AREA": "1", + "CORE_UTILIZATION": "40", + "CORE_ASPECT_RATIO": "1", + "CORE_MARGIN": "2", + "PLACE_DENSITY": "0.60", + "ASAP7_USE_VT": "LVT", + "RECOVER_POWER": "1", + }, + sources = { + "SDC_FILE": [":constraint.sdc"], + }, + top = "ethmac", + verilog_files = ["//flow/designs/src/ethmac_lvt:verilog"], +) diff --git a/flow/designs/asap7/ethmac_lvt/config.mk b/flow/designs/asap7/ethmac_lvt/config.mk index 21dc689e75..ff4d402a11 100644 --- a/flow/designs/asap7/ethmac_lvt/config.mk +++ b/flow/designs/asap7/ethmac_lvt/config.mk @@ -12,13 +12,6 @@ export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.60 -export ASAP7_USELVT = 1 -export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib +export ASAP7_USE_VT = LVT -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_R_220121a.gds -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_R_1x_220121a.lef export RECOVER_POWER = 1 diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc index c9a876f18f..465d603d0c 100644 --- a/flow/designs/asap7/ethmac_lvt/constraint.sdc +++ b/flow/designs/asap7/ethmac_lvt/constraint.sdc @@ -3,8 +3,8 @@ set clk_period 1000 set clk_io_pct 0.2 set clk_port [get_ports $top_clk_name] create_clock -name $top_clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs] set tx_clk_name mtx_clk_pad_i @@ -12,7 +12,7 @@ set tx_clk_port [get_ports $tx_clk_name] set tx_clk_period 300 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port] -set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs +set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs] set rx_clk_name mrx_clk_pad_i @@ -20,10 +20,10 @@ set rx_clk_port [get_ports $rx_clk_name] set rx_clk_period 300 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port] -set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs +set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs] set_clock_groups -name core_clock -logically_exclusive \ - -group [get_clocks $top_clk_name] \ - -group [get_clocks $tx_clk_name] \ - -group [get_clocks $rx_clk_name] + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] diff --git a/flow/designs/asap7/ethmac_lvt/metadata-base-ok.json b/flow/designs/asap7/ethmac_lvt/metadata-base-ok.json deleted file mode 100644 index 455858e39e..0000000000 --- a/flow/designs/asap7/ethmac_lvt/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 3, - "constraints__clocks__details": [ - "mrx_clk_pad_i: 300.0000", - "mtx_clk_pad_i: 300.0000", - "wb_clk_i: 1000.0000" - ], - "cts__clock__skew__hold": 147.809, - "cts__clock__skew__setup": 158.512, - "cts__cpu__total": 82.51, - "cts__design__core__area": 18327.2, - "cts__design__die__area": 19477.6, - "cts__design__instance__area": 8642.31, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 8642.31, - "cts__design__instance__count": 61508, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 79, - "cts__design__instance__count__stdcell": 61508, - "cts__design__instance__displacement__max": 2.115, - "cts__design__instance__displacement__mean": 0.001, - "cts__design__instance__displacement__total": 76.886, - "cts__design__instance__utilization": 0.471557, - "cts__design__instance__utilization__stdcell": 0.471557, - "cts__design__io": 216, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 21, - "cts__mem__peak": 1232488.0, - "cts__power__internal__total": 0.087936, - "cts__power__leakage__total": 2.75525e-05, - "cts__power__switching__total": 0.0241037, - "cts__power__total": 0.112067, - "cts__route__wirelength__estimated": 368686, - "cts__runtime__total": "1:23.63", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.601505, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.384693, - "cts__timing__drv__setup_violation_count": 17, - "cts__timing__setup__tns": -286.735, - "cts__timing__setup__ws": -19.5119, - "design__io__hpwl": 6624195, - "design__violations": 0, - "detailedplace__cpu__total": 76.64, - "detailedplace__design__core__area": 18327.2, - "detailedplace__design__die__area": 19477.6, - "detailedplace__design__instance__area": 8354.63, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 8354.63, - "detailedplace__design__instance__count": 60492, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 60492, - "detailedplace__design__instance__displacement__max": 5.848, - "detailedplace__design__instance__displacement__mean": 0.259, - "detailedplace__design__instance__displacement__total": 15722.7, - "detailedplace__design__instance__utilization": 0.45586, - "detailedplace__design__instance__utilization__stdcell": 0.45586, - "detailedplace__design__io": 216, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 20, - "detailedplace__mem__peak": 634772.0, - "detailedplace__power__internal__total": 0.0567883, - "detailedplace__power__leakage__total": 2.52735e-05, - "detailedplace__power__switching__total": 0.00478564, - "detailedplace__power__total": 0.0615992, - "detailedplace__route__wirelength__estimated": 364680, - "detailedplace__runtime__total": "1:17.17", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.601505, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.392787, - "detailedplace__timing__drv__setup_violation_count": 336, - "detailedplace__timing__setup__tns": -20429.2, - "detailedplace__timing__setup__ws": -118.99, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 21, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 19614, - "detailedroute__route__drc_errors__iter:2": 1534, - "detailedroute__route__drc_errors__iter:3": 901, - "detailedroute__route__drc_errors__iter:4": 14, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 59137, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 760190, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 760190, - "detailedroute__route__wirelength": 592318, - "detailedroute__route__wirelength__iter:1": 595603, - "detailedroute__route__wirelength__iter:2": 592917, - "detailedroute__route__wirelength__iter:3": 592260, - "detailedroute__route__wirelength__iter:4": 592320, - "detailedroute__route__wirelength__iter:5": 592318, - "finish__clock__skew__hold": 152.26, - "finish__clock__skew__setup": 162.971, - "finish__cpu__total": 199.37, - "finish__design__core__area": 18327.2, - "finish__design__die__area": 19477.6, - "finish__design__instance__area": 8654.1, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 8654.1, - "finish__design__instance__count": 61560, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 61560, - "finish__design__instance__utilization": 0.4722, - "finish__design__instance__utilization__stdcell": 0.4722, - "finish__design__io": 216, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.739145, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0298704, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.101717, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.10073, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.668283, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.10073, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 21, - "finish__mem__peak": 2101912.0, - "finish__power__internal__total": 0.0899285, - "finish__power__leakage__total": 2.75882e-05, - "finish__power__switching__total": 0.0266752, - "finish__power__total": 0.116631, - "finish__runtime__total": "3:21.67", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.204493, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 1536, - "finish__timing__drv__max_slew_limit": -3.83565, - "finish__timing__drv__setup_violation_count": 387, - "finish__timing__setup__tns": -27222.8, - "finish__timing__setup__ws": -193.769, - "finish__timing__wns_percent_delay": -14.532763, - "finish_merge__cpu__total": 10.68, - "finish_merge__mem__peak": 931004.0, - "finish_merge__runtime__total": "0:11.41", - "floorplan__cpu__total": 47.91, - "floorplan__design__core__area": 18327.2, - "floorplan__design__die__area": 19477.6, - "floorplan__design__instance__area": 7352.8, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 7352.8, - "floorplan__design__instance__count": 56745, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 56745, - "floorplan__design__instance__utilization": 0.401196, - "floorplan__design__instance__utilization__stdcell": 0.401196, - "floorplan__design__io": 216, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1383, - "floorplan__mem__peak": 535720.0, - "floorplan__power__internal__total": 0.0548457, - "floorplan__power__leakage__total": 8.26248e-06, - "floorplan__power__switching__total": 0.00252001, - "floorplan__power__total": 0.0573739, - "floorplan__runtime__total": "0:48.28", - "floorplan__timing__setup__tns": -197.701, - "floorplan__timing__setup__ws": -18.48, - "floorplan_io__cpu__total": 4.04, - "floorplan_io__mem__peak": 400752.0, - "floorplan_io__runtime__total": "0:04.31", - "floorplan_macro__cpu__total": 4.0, - "floorplan_macro__mem__peak": 397196.0, - "floorplan_macro__runtime__total": "0:04.35", - "floorplan_pdn__cpu__total": 5.05, - "floorplan_pdn__mem__peak": 406220.0, - "floorplan_pdn__runtime__total": "0:05.40", - "floorplan_tap__cpu__total": 3.94, - "floorplan_tap__mem__peak": 365104.0, - "floorplan_tap__runtime__total": "0:04.19", - "floorplan_tdms__cpu__total": 4.0, - "floorplan_tdms__mem__peak": 397044.0, - "floorplan_tdms__runtime__total": "0:04.36", - "flow__errors__count": 0, - "flow__warnings__count": 20, - "globalplace__cpu__total": 3720.95, - "globalplace__design__core__area": 18327.2, - "globalplace__design__die__area": 19477.6, - "globalplace__design__instance__area": 7418.67, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 7418.67, - "globalplace__design__instance__count": 59004, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 59004, - "globalplace__design__instance__utilization": 0.40479, - "globalplace__design__instance__utilization__stdcell": 0.40479, - "globalplace__design__io": 216, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 20, - "globalplace__mem__peak": 1406672.0, - "globalplace__power__internal__total": 0.0549651, - "globalplace__power__leakage__total": 8.26248e-06, - "globalplace__power__switching__total": 0.00440862, - "globalplace__power__total": 0.059382, - "globalplace__runtime__total": "7:04.48", - "globalplace__timing__setup__tns": -110986, - "globalplace__timing__setup__ws": -434.312, - "globalplace_io__cpu__total": 4.03, - "globalplace_io__mem__peak": 406260.0, - "globalplace_io__runtime__total": "0:04.34", - "globalplace_skip_io__cpu__total": 1348.33, - "globalplace_skip_io__mem__peak": 479928.0, - "globalplace_skip_io__runtime__total": "1:01.22", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 142.527, - "globalroute__clock__skew__setup": 153.536, - "globalroute__cpu__total": 3203.51, - "globalroute__design__core__area": 18327.2, - "globalroute__design__die__area": 19477.6, - "globalroute__design__instance__area": 8654.1, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 8654.1, - "globalroute__design__instance__count": 61560, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 10, - "globalroute__design__instance__count__stdcell": 61560, - "globalroute__design__instance__displacement__max": 1.134, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 16.686, - "globalroute__design__instance__utilization": 0.4722, - "globalroute__design__instance__utilization__stdcell": 0.4722, - "globalroute__design__io": 216, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 23, - "globalroute__mem__peak": 1995808.0, - "globalroute__power__internal__total": 0.0892988, - "globalroute__power__leakage__total": 2.75882e-05, - "globalroute__power__switching__total": 0.0255566, - "globalroute__power__total": 0.114883, - "globalroute__route__wirelength__estimated": 370876, - "globalroute__runtime__total": "49:58.64", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.607418, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 746, - "globalroute__timing__drv__max_slew_limit": -2.32777, - "globalroute__timing__drv__setup_violation_count": 172, - "globalroute__timing__setup__tns": -1878.5, - "globalroute__timing__setup__ws": -29.8616, - "placeopt__cpu__total": 65.27, - "placeopt__design__core__area": 18327.2, - "placeopt__design__die__area": 19477.6, - "placeopt__design__instance__area": 8354.63, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 8354.63, - "placeopt__design__instance__count": 60492, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 60492, - "placeopt__design__instance__utilization": 0.45586, - "placeopt__design__instance__utilization__stdcell": 0.45586, - "placeopt__design__io": 216, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 20, - "placeopt__mem__peak": 1080500.0, - "placeopt__power__internal__total": 0.0567876, - "placeopt__power__leakage__total": 2.52735e-05, - "placeopt__power__switching__total": 0.00478485, - "placeopt__power__total": 0.0615977, - "placeopt__runtime__total": "1:06.18", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.603933, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.404959, - "placeopt__timing__drv__setup_violation_count": 337, - "placeopt__timing__setup__tns": -21249.3, - "placeopt__timing__setup__ws": -124.368, - "run__flow__design": "ethmac_lvt", - "run__flow__generate_date": "2024-09-27 19:04", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "0a95c207-ca96-4206-b29b-d5b2959f60b8", - "run__flow__variant": "base", - "synth__cpu__total": 58.21, - "synth__design__instance__area__stdcell": 7350.84234, - "synth__design__instance__count__stdcell": 56742.0, - "synth__mem__peak": 384992.0, - "synth__runtime__total": "0:59.38", - "total_time": "1:07:39.010000" -} \ No newline at end of file diff --git a/flow/designs/asap7/ethmac_lvt/rules-base.json b/flow/designs/asap7/ethmac_lvt/rules-base.json index e559bfdf3b..36f0d0a851 100644 --- a/flow/designs/asap7/ethmac_lvt/rules-base.json +++ b/flow/designs/asap7/ethmac_lvt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9608, + "value": 8660, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 69566, + "value": 66074, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6049, + "value": 5746, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 593237, + "value": 250591, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -208.76, + "value": -55.18, "compare": ">=" }, "finish__design__instance__area": { - "value": 9952, + "value": 8806, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3025, + "value": 2873, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.43, + "value": -22.5, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/gcd-ccs/metadata-base-ok.json b/flow/designs/asap7/gcd-ccs/metadata-base-ok.json deleted file mode 100644 index 210d47900e..0000000000 --- a/flow/designs/asap7/gcd-ccs/metadata-base-ok.json +++ /dev/null @@ -1,312 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 390.0000" - ], - "cts__clock__skew__hold": 5.79221, - "cts__clock__skew__setup": 2.17651, - "cts__cpu__total": 11.27, - "cts__design__core__area": 197.122, - "cts__design__die__area": 262.44, - "cts__design__instance__area": 51.0008, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 51.0008, - "cts__design__instance__count": 504, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 11, - "cts__design__instance__count__stdcell": 504, - "cts__design__instance__displacement__max": 0.709, - "cts__design__instance__displacement__mean": 0.01, - "cts__design__instance__displacement__total": 5.043, - "cts__design__instance__utilization": 0.258728, - "cts__design__instance__utilization__stdcell": 0.258728, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 18, - "cts__mem__peak": 374528.0, - "cts__power__internal__total": 0.000701415, - "cts__power__leakage__total": 3.11986e-08, - "cts__power__switching__total": 0.000397052, - "cts__power__total": 0.0010985, - "cts__route__wirelength__estimated": 893.541, - "cts__runtime__total": "0:11.41", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.766722, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.65938, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 2.34252, - "design__io__hpwl": 280089, - "detailedplace__cpu__total": 9.09, - "detailedplace__design__core__area": 197.122, - "detailedplace__design__die__area": 262.44, - "detailedplace__design__instance__area": 49.5428, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 49.5428, - "detailedplace__design__instance__count": 485, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 485, - "detailedplace__design__instance__displacement__max": 0.935, - "detailedplace__design__instance__displacement__mean": 0.151, - "detailedplace__design__instance__displacement__total": 73.391, - "detailedplace__design__instance__utilization": 0.251331, - "detailedplace__design__instance__utilization__stdcell": 0.251331, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 18, - "detailedplace__mem__peak": 363484.0, - "detailedplace__power__internal__total": 0.000652664, - "detailedplace__power__leakage__total": 3.0316e-08, - "detailedplace__power__switching__total": 0.000353599, - "detailedplace__power__total": 0.00100629, - "detailedplace__route__wirelength__estimated": 876.914, - "detailedplace__runtime__total": "0:09.21", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.730434, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.65938, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 7.0349, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 57.98, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 23, - "detailedroute__mem__peak": 1740196.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 132, - "detailedroute__route__drc_errors__iter:2": 6, - "detailedroute__route__drc_errors__iter:3": 4, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 465, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3361, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3361, - "detailedroute__route__wirelength": 1094, - "detailedroute__route__wirelength__iter:1": 1103, - "detailedroute__route__wirelength__iter:2": 1094, - "detailedroute__route__wirelength__iter:3": 1094, - "detailedroute__route__wirelength__iter:4": 1094, - "detailedroute__runtime__total": "0:22.44", - "fillcell__cpu__total": 8.87, - "fillcell__mem__peak": 361304.0, - "fillcell__runtime__total": "0:08.99", - "finish__clock__skew__hold": 6.35891, - "finish__clock__skew__setup": 3.72978, - "finish__cpu__total": 13.43, - "finish__design__core__area": 197.122, - "finish__design__die__area": 262.44, - "finish__design__instance__area": 51.0008, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 51.0008, - "finish__design__instance__count": 504, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 504, - "finish__design__instance__utilization": 0.258728, - "finish__design__instance__utilization__stdcell": 0.258728, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.768759, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0015303, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00344425, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0054167, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.766556, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0054167, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 18, - "finish__mem__peak": 427136.0, - "finish__power__internal__total": 0.000702755, - "finish__power__leakage__total": 3.11986e-08, - "finish__power__switching__total": 0.000482744, - "finish__power__total": 0.00118553, - "finish__runtime__total": "0:13.69", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.731314, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.542431, - "finish__timing__drv__setup_violation_count": 40, - "finish__timing__setup__tns": -1332.23, - "finish__timing__setup__ws": -49.2537, - "finish__timing__wns_percent_delay": -10.454899, - "finish_merge__cpu__total": 1.04, - "finish_merge__mem__peak": 251608.0, - "finish_merge__runtime__total": "0:01.34", - "floorplan__cpu__total": 9.01, - "floorplan__design__core__area": 197.122, - "floorplan__design__die__area": 262.44, - "floorplan__design__instance__area": 41.0427, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 41.0427, - "floorplan__design__instance__count": 328, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 328, - "floorplan__design__instance__utilization": 0.20821, - "floorplan__design__instance__utilization__stdcell": 0.20821, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 18, - "floorplan__mem__peak": 363364.0, - "floorplan__power__internal__total": 0.000589964, - "floorplan__power__leakage__total": 2.55777e-08, - "floorplan__power__switching__total": 0.000317496, - "floorplan__power__total": 0.000907486, - "floorplan__runtime__total": "0:09.14", - "floorplan__timing__setup__tns": -414.974, - "floorplan__timing__setup__ws": -31.5234, - "floorplan_io__cpu__total": 8.93, - "floorplan_io__mem__peak": 359708.0, - "floorplan_io__runtime__total": "0:09.05", - "floorplan_macro__cpu__total": 8.89, - "floorplan_macro__mem__peak": 360460.0, - "floorplan_macro__runtime__total": "0:09.01", - "floorplan_pdn__cpu__total": 8.86, - "floorplan_pdn__mem__peak": 361168.0, - "floorplan_pdn__runtime__total": "0:08.99", - "floorplan_tap__cpu__total": 8.87, - "floorplan_tap__mem__peak": 359428.0, - "floorplan_tap__runtime__total": "0:08.99", - "floorplan_tdms__cpu__total": 8.86, - "floorplan_tdms__mem__peak": 359376.0, - "floorplan_tdms__runtime__total": "0:08.99", - "flow__errors__count": 0, - "flow__warnings__count": 18, - "globalplace__cpu__total": 9.5, - "globalplace__design__core__area": 197.122, - "globalplace__design__die__area": 262.44, - "globalplace__design__instance__area": 44.0753, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 44.0753, - "globalplace__design__instance__count": 432, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 432, - "globalplace__design__instance__utilization": 0.223595, - "globalplace__design__instance__utilization__stdcell": 0.223595, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 18, - "globalplace__mem__peak": 379632.0, - "globalplace__power__internal__total": 0.000589964, - "globalplace__power__leakage__total": 2.55777e-08, - "globalplace__power__switching__total": 0.000317496, - "globalplace__power__total": 0.000907486, - "globalplace__runtime__total": "0:09.63", - "globalplace__timing__setup__tns": -414.974, - "globalplace__timing__setup__ws": -31.5234, - "globalplace_io__cpu__total": 8.87, - "globalplace_io__mem__peak": 360264.0, - "globalplace_io__runtime__total": "0:08.99", - "globalplace_skip_io__cpu__total": 8.96, - "globalplace_skip_io__mem__peak": 360564.0, - "globalplace_skip_io__runtime__total": "0:09.07", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 5.79221, - "globalroute__clock__skew__setup": 2.17651, - "globalroute__cpu__total": 11.22, - "globalroute__design__core__area": 197.122, - "globalroute__design__die__area": 262.44, - "globalroute__design__instance__area": 51.0008, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 51.0008, - "globalroute__design__instance__count": 504, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 504, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.258728, - "globalroute__design__instance__utilization__stdcell": 0.258728, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 18, - "globalroute__mem__peak": 448748.0, - "globalroute__power__internal__total": 0.000701415, - "globalroute__power__leakage__total": 3.11986e-08, - "globalroute__power__switching__total": 0.000397052, - "globalroute__power__total": 0.0010985, - "globalroute__route__wirelength__estimated": 893.541, - "globalroute__runtime__total": "0:09.80", - "globalroute__timing__clock__slack": 2.343, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.766722, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.65938, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 2.34252, - "placeopt__cpu__total": 9.14, - "placeopt__design__core__area": 197.122, - "placeopt__design__die__area": 262.44, - "placeopt__design__instance__area": 49.5428, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 49.5428, - "placeopt__design__instance__count": 485, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 485, - "placeopt__design__instance__utilization": 0.251331, - "placeopt__design__instance__utilization__stdcell": 0.251331, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 18, - "placeopt__mem__peak": 369108.0, - "placeopt__power__internal__total": 0.000652664, - "placeopt__power__leakage__total": 3.0316e-08, - "placeopt__power__switching__total": 0.000353599, - "placeopt__power__total": 0.00100629, - "placeopt__runtime__total": "0:09.25", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.730434, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.65938, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 7.0349, - "run__flow__design": "gcd-ccs", - "run__flow__generate_date": "2024-06-20 21:31", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-14264-g08c19394f", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__scripts_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__uuid": "45addd11-ff65-4a39-86ca-a6b979b343ff", - "run__flow__variant": "base", - "synth__cpu__total": 21.04, - "synth__design__instance__area__stdcell": 42.36948, - "synth__design__instance__count__stdcell": 343.0, - "synth__mem__peak": 1134968.0, - "synth__runtime__total": "0:21.84", - "total_time": "0:03:09.830000" -} \ No newline at end of file diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json index 9c3a6c56e9..3b2e302854 100644 --- a/flow/designs/asap7/gcd-ccs/rules-base.json +++ b/flow/designs/asap7/gcd-ccs/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 43.75, + "value": 43.38, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 51, + "value": 53, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 508, + "value": 540, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,15 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 45, + "value": 47, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { "value": 44, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 1251, + "value": 1224, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -39,16 +43,20 @@ "value": 0, "compare": "<=" }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": -64.03, + "value": -94.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 54, + "value": 56, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 41, + "value": 24, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -56,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.54, + "value": -34.7, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/gcd/BUILD b/flow/designs/asap7/gcd/BUILD new file mode 100644 index 0000000000..0736578fe6 --- /dev/null +++ b/flow/designs/asap7/gcd/BUILD @@ -0,0 +1,20 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow") + +orfs_flow( + name = "gcd", + arguments = { + # Faster builds + "SKIP_INCREMENTAL_REPAIR": "1", + "GPL_TIMING_DRIVEN": "0", + "SKIP_LAST_GASP": "1", + # Various + "DIE_AREA": "0 0 16.2 16.2", + "CORE_AREA": "1.08 1.08 15.12 15.12", + "PLACE_DENSITY": "0.35", + }, + sources = { + "RULES_JSON": [":rules-base.json"], + "SDC_FILE": [":constraint.sdc"], + }, + verilog_files = ["//flow/designs/src/gcd:verilog"], +) diff --git a/flow/designs/asap7/gcd/autotuner.json b/flow/designs/asap7/gcd/autotuner.json index 4675593b4b..fcc82fa72d 100644 --- a/flow/designs/asap7/gcd/autotuner.json +++ b/flow/designs/asap7/gcd/autotuner.json @@ -3,32 +3,24 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 300, - 1000 - ], - "step": 0 - }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 + 200, + 500 ], "step": 0 }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -44,7 +36,7 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, diff --git a/flow/designs/asap7/gcd/config.mk b/flow/designs/asap7/gcd/config.mk index 35d247211a..cb572b7986 100644 --- a/flow/designs/asap7/gcd/config.mk +++ b/flow/designs/asap7/gcd/config.mk @@ -7,6 +7,8 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constr export DIE_AREA = 0 0 16.2 16.2 export CORE_AREA = 1.08 1.08 15.12 15.12 +# The goal of this design is to have a smoketest that builds quickly, +# that said, this design will go through grt with a 0.99 placement density. export PLACE_DENSITY = 0.35 # a smoketest for this option, there are a diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc index 7e3d64bb8b..27de11250b 100644 --- a/flow/designs/asap7/gcd/constraint.sdc +++ b/flow/designs/asap7/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 390 +set clk_period 310 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/gcd/metadata-base-ok.json b/flow/designs/asap7/gcd/metadata-base-ok.json deleted file mode 100644 index 89b3af4a88..0000000000 --- a/flow/designs/asap7/gcd/metadata-base-ok.json +++ /dev/null @@ -1,309 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 390.0000" - ], - "cts__clock__skew__hold": 5.70028, - "cts__clock__skew__setup": 3.88663, - "cts__cpu__total": 4.46, - "cts__design__core__area": 197.122, - "cts__design__die__area": 262.44, - "cts__design__instance__area": 60.3758, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 60.3758, - "cts__design__instance__count": 604, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 42, - "cts__design__instance__count__stdcell": 604, - "cts__design__instance__displacement__max": 0.918, - "cts__design__instance__displacement__mean": 0.021, - "cts__design__instance__displacement__total": 13.161, - "cts__design__instance__utilization": 0.306287, - "cts__design__instance__utilization__stdcell": 0.306287, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 578068.0, - "cts__power__internal__total": 0.000480574, - "cts__power__leakage__total": 3.94861e-08, - "cts__power__switching__total": 0.000315762, - "cts__power__total": 0.000796376, - "cts__route__wirelength__estimated": 1201.1, - "cts__runtime__total": "0:04.85", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.830916, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.787038, - "cts__timing__drv__setup_violation_count": 2, - "cts__timing__setup__tns": -17.9406, - "cts__timing__setup__ws": -12.4722, - "design__io__hpwl": 281414, - "design__violations": 0, - "detailedplace__cpu__total": 1.79, - "detailedplace__design__core__area": 197.122, - "detailedplace__design__die__area": 262.44, - "detailedplace__design__instance__area": 56.4975, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 56.4975, - "detailedplace__design__instance__count": 555, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 555, - "detailedplace__design__instance__displacement__max": 1.117, - "detailedplace__design__instance__displacement__mean": 0.172, - "detailedplace__design__instance__displacement__total": 96.002, - "detailedplace__design__instance__utilization": 0.286612, - "detailedplace__design__instance__utilization__stdcell": 0.286612, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 215976.0, - "detailedplace__power__internal__total": 0.00041055, - "detailedplace__power__leakage__total": 3.6904e-08, - "detailedplace__power__switching__total": 0.0002526, - "detailedplace__power__total": 0.000663187, - "detailedplace__route__wirelength__estimated": 1180.44, - "detailedplace__runtime__total": "0:01.93", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.654967, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.506814, - "detailedplace__timing__drv__setup_violation_count": 34, - "detailedplace__timing__setup__tns": -435.34, - "detailedplace__timing__setup__ws": -24.6606, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 72, - "detailedroute__route__drc_errors__iter:2": 15, - "detailedroute__route__drc_errors__iter:3": 0, - "detailedroute__route__net": 566, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 4088, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 4088, - "detailedroute__route__wirelength": 1394, - "detailedroute__route__wirelength__iter:1": 1401, - "detailedroute__route__wirelength__iter:2": 1393, - "detailedroute__route__wirelength__iter:3": 1394, - "finish__clock__skew__hold": 6.15945, - "finish__clock__skew__setup": 4.52083, - "finish__cpu__total": 2.93, - "finish__design__core__area": 197.122, - "finish__design__die__area": 262.44, - "finish__design__instance__area": 60.4778, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 60.4778, - "finish__design__instance__count": 605, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 605, - "finish__design__instance__utilization": 0.306805, - "finish__design__instance__utilization__stdcell": 0.306805, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.76936, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000633076, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00210657, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00215454, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.767893, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00215454, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 362612.0, - "finish__power__internal__total": 0.00048203, - "finish__power__leakage__total": 3.9562e-08, - "finish__power__switching__total": 0.000322139, - "finish__power__total": 0.000804209, - "finish__runtime__total": "0:03.15", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.831454, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.780926, - "finish__timing__drv__setup_violation_count": 3, - "finish__timing__setup__tns": -16.7643, - "finish__timing__setup__ws": -9.05531, - "finish__timing__wns_percent_delay": -2.82048, - "finish_merge__cpu__total": 1.28, - "finish_merge__mem__peak": 396328.0, - "finish_merge__runtime__total": "0:01.44", - "floorplan__cpu__total": 1.79, - "floorplan__design__core__area": 197.122, - "floorplan__design__die__area": 262.44, - "floorplan__design__instance__area": 47.2392, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 47.2392, - "floorplan__design__instance__count": 398, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 398, - "floorplan__design__instance__utilization": 0.239645, - "floorplan__design__instance__utilization__stdcell": 0.239645, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 11, - "floorplan__mem__peak": 215216.0, - "floorplan__power__internal__total": 0.000358457, - "floorplan__power__leakage__total": 3.05344e-08, - "floorplan__power__switching__total": 0.000188012, - "floorplan__power__total": 0.0005465, - "floorplan__runtime__total": "0:01.95", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 30.5282, - "floorplan_io__cpu__total": 1.51, - "floorplan_io__mem__peak": 211204.0, - "floorplan_io__runtime__total": "0:01.68", - "floorplan_macro__cpu__total": 1.24, - "floorplan_macro__mem__peak": 210352.0, - "floorplan_macro__runtime__total": "0:01.36", - "floorplan_pdn__cpu__total": 1.26, - "floorplan_pdn__mem__peak": 213164.0, - "floorplan_pdn__runtime__total": "0:01.38", - "floorplan_tap__cpu__total": 1.25, - "floorplan_tap__mem__peak": 210220.0, - "floorplan_tap__runtime__total": "0:01.35", - "floorplan_tdms__cpu__total": 1.52, - "floorplan_tdms__mem__peak": 210732.0, - "floorplan_tdms__runtime__total": "0:01.68", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 113.66, - "globalplace__design__core__area": 197.122, - "globalplace__design__die__area": 262.44, - "globalplace__design__instance__area": 50.2718, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 50.2718, - "globalplace__design__instance__count": 502, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 502, - "globalplace__design__instance__utilization": 0.25503, - "globalplace__design__instance__utilization__stdcell": 0.25503, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 527644.0, - "globalplace__power__internal__total": 0.000359686, - "globalplace__power__leakage__total": 3.05344e-08, - "globalplace__power__switching__total": 0.00023006, - "globalplace__power__total": 0.000589777, - "globalplace__runtime__total": "0:17.60", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 1.14095, - "globalplace_io__cpu__total": 1.55, - "globalplace_io__mem__peak": 211340.0, - "globalplace_io__runtime__total": "0:01.65", - "globalplace_skip_io__cpu__total": 294.68, - "globalplace_skip_io__mem__peak": 211716.0, - "globalplace_skip_io__runtime__total": "0:24.78", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 6.0372, - "globalroute__clock__skew__setup": 3.99442, - "globalroute__cpu__total": 2.77, - "globalroute__design__core__area": 197.122, - "globalroute__design__die__area": 262.44, - "globalroute__design__instance__area": 60.4778, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 60.4778, - "globalroute__design__instance__count": 605, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 1, - "globalroute__design__instance__count__stdcell": 605, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.306805, - "globalroute__design__instance__utilization__stdcell": 0.306805, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 547680.0, - "globalroute__power__internal__total": 0.000482329, - "globalroute__power__leakage__total": 3.9562e-08, - "globalroute__power__switching__total": 0.000337127, - "globalroute__power__total": 0.000819496, - "globalroute__route__wirelength__estimated": 1201.92, - "globalroute__runtime__total": "0:02.53", - "globalroute__timing__clock__slack": -12.146, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.819057, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.778913, - "globalroute__timing__drv__setup_violation_count": 2, - "globalroute__timing__setup__tns": -23.6444, - "globalroute__timing__setup__ws": -12.1458, - "placeopt__cpu__total": 2.05, - "placeopt__design__core__area": 197.122, - "placeopt__design__die__area": 262.44, - "placeopt__design__instance__area": 56.4975, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 56.4975, - "placeopt__design__instance__count": 555, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 555, - "placeopt__design__instance__utilization": 0.286612, - "placeopt__design__instance__utilization__stdcell": 0.286612, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 480560.0, - "placeopt__power__internal__total": 0.000410499, - "placeopt__power__leakage__total": 3.6904e-08, - "placeopt__power__switching__total": 0.000252624, - "placeopt__power__total": 0.000663161, - "placeopt__runtime__total": "0:02.44", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.659317, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.513085, - "placeopt__timing__drv__setup_violation_count": 34, - "placeopt__timing__setup__tns": -433.923, - "placeopt__timing__setup__ws": -23.0954, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "43428d26-5191-461e-b97b-8a6513bded72", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 2.6, - "synth__design__instance__area__stdcell": 47.2392, - "synth__design__instance__count__stdcell": 398.0, - "synth__mem__peak": 140544.0, - "synth__runtime__total": "0:02.81", - "total_time": "0:01:12.580000" -} \ No newline at end of file diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index d4fa1146e5..b770bcc571 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 54.33, + "value": 43.38, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 65, + "value": 53, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 638, + "value": 543, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 56, + "value": 47, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 56, + "value": 47, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1603, + "value": 1271, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -28.55, + "value": -73.56, "compare": ">=" }, "finish__design__instance__area": { - "value": 70, + "value": 59, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 28, + "value": 27, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -13.38, + "value": -32.76, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/ibex/autotuner.json b/flow/designs/asap7/ibex/autotuner.json index 08d679909b..8561355eec 100644 --- a/flow/designs/asap7/ibex/autotuner.json +++ b/flow/designs/asap7/ibex/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 1800, + 1200, 2000 ], "step": 0 @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 3, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 3, - 5 + 0, + 3 ], "step": 1 }, @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ diff --git a/flow/designs/asap7/ibex/config.mk b/flow/designs/asap7/ibex/config.mk index b49ef0dac7..170af31035 100644 --- a/flow/designs/asap7/ibex/config.mk +++ b/flow/designs/asap7/ibex/config.mk @@ -3,8 +3,21 @@ export PLATFORM = asap7 export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + +# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock +# resulting in positive slack +ifeq ($(FLOW_VARIANT),pos_slack) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_pos_slack.sdc +else export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +endif export CORE_UTILIZATION = 40 export CORE_ASPECT_RATIO = 1 diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc index a58c555b69..30bb0a2292 100644 --- a/flow/designs/asap7/ibex/constraint.sdc +++ b/flow/designs/asap7/ibex/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 1260 set clk_io_pct 0.2 @@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc new file mode 100644 index 0000000000..d605a5aa8e --- /dev/null +++ b/flow/designs/asap7/ibex/constraint_pos_slack.sdc @@ -0,0 +1,13 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 1468 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [all_inputs -no_clocks] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/ibex/metadata-base-ok.json b/flow/designs/asap7/ibex/metadata-base-ok.json deleted file mode 100644 index 9a649f1bc1..0000000000 --- a/flow/designs/asap7/ibex/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1260.0000" - ], - "cts__clock__skew__hold": 130.713, - "cts__clock__skew__setup": 153.191, - "cts__cpu__total": 127.58, - "cts__design__core__area": 5723.52, - "cts__design__die__area": 6363.41, - "cts__design__instance__area": 2722.39, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 2722.39, - "cts__design__instance__count": 21967, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 62, - "cts__design__instance__count__stdcell": 21967, - "cts__design__instance__displacement__max": 1.278, - "cts__design__instance__displacement__mean": 0.002, - "cts__design__instance__displacement__total": 50.71, - "cts__design__instance__utilization": 0.47565, - "cts__design__instance__utilization__stdcell": 0.47565, - "cts__design__io": 264, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 674580.0, - "cts__power__internal__total": 0.0292893, - "cts__power__leakage__total": 2.13718e-06, - "cts__power__switching__total": 0.0298838, - "cts__power__total": 0.0591753, - "cts__route__wirelength__estimated": 95964.6, - "cts__runtime__total": "2:08.05", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.407914, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.410244, - "cts__timing__drv__setup_violation_count": 3, - "cts__timing__setup__tns": -43.6311, - "cts__timing__setup__ws": -26.3496, - "design__io__hpwl": 5014158, - "design__violations": 0, - "detailedplace__cpu__total": 22.73, - "detailedplace__design__core__area": 5723.52, - "detailedplace__design__die__area": 6363.41, - "detailedplace__design__instance__area": 2583.61, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 2583.61, - "detailedplace__design__instance__count": 21562, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 21562, - "detailedplace__design__instance__displacement__max": 2.238, - "detailedplace__design__instance__displacement__mean": 0.223, - "detailedplace__design__instance__displacement__total": 4809.95, - "detailedplace__design__instance__utilization": 0.451401, - "detailedplace__design__instance__utilization__stdcell": 0.451401, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 330276.0, - "detailedplace__power__internal__total": 0.0257104, - "detailedplace__power__leakage__total": 1.99617e-06, - "detailedplace__power__switching__total": 0.0286551, - "detailedplace__power__total": 0.0543675, - "detailedplace__route__wirelength__estimated": 93327.5, - "detailedplace__runtime__total": "0:22.94", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.40852, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.410309, - "detailedplace__timing__drv__setup_violation_count": 187, - "detailedplace__timing__setup__tns": -7989.8, - "detailedplace__timing__setup__ws": -71.1674, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 6031, - "detailedroute__route__drc_errors__iter:2": 656, - "detailedroute__route__drc_errors__iter:3": 501, - "detailedroute__route__drc_errors__iter:4": 8, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 21721, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 220265, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 220265, - "detailedroute__route__wirelength": 117126, - "detailedroute__route__wirelength__iter:1": 117710, - "detailedroute__route__wirelength__iter:2": 117209, - "detailedroute__route__wirelength__iter:3": 117118, - "detailedroute__route__wirelength__iter:4": 117125, - "detailedroute__route__wirelength__iter:5": 117126, - "finish__clock__skew__hold": 140.632, - "finish__clock__skew__setup": 162.401, - "finish__cpu__total": 108.8, - "finish__design__core__area": 5723.52, - "finish__design__die__area": 6363.41, - "finish__design__instance__area": 2730.11, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 2730.11, - "finish__design__instance__count": 22002, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 22002, - "finish__design__instance__utilization": 0.476997, - "finish__design__instance__utilization__stdcell": 0.476997, - "finish__design__io": 264, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.679699, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0900985, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.413346, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.420043, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.356654, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.420043, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 884800.0, - "finish__power__internal__total": 0.0296143, - "finish__power__leakage__total": 2.1448e-06, - "finish__power__switching__total": 0.0322787, - "finish__power__total": 0.0618951, - "finish__runtime__total": "1:49.52", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.274663, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0435411, - "finish__timing__drv__setup_violation_count": 290, - "finish__timing__setup__tns": -6634.59, - "finish__timing__setup__ws": -64.0279, - "finish__timing__wns_percent_delay": -5.972596, - "finish_merge__cpu__total": 3.19, - "finish_merge__mem__peak": 565936.0, - "finish_merge__runtime__total": "0:03.57", - "floorplan__cpu__total": 16.66, - "floorplan__design__core__area": 5723.52, - "floorplan__design__die__area": 6363.41, - "floorplan__design__instance__area": 2296.74, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 2296.74, - "floorplan__design__instance__count": 18640, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 2, - "floorplan__design__instance__count__stdcell": 18640, - "floorplan__design__instance__utilization": 0.401281, - "floorplan__design__instance__utilization__stdcell": 0.401281, - "floorplan__design__io": 264, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 28, - "floorplan__mem__peak": 293076.0, - "floorplan__power__internal__total": 0.0246559, - "floorplan__power__leakage__total": 1.69528e-06, - "floorplan__power__switching__total": 0.0199937, - "floorplan__power__total": 0.0446514, - "floorplan__runtime__total": "0:16.82", - "floorplan__timing__setup__tns": -0.0416334, - "floorplan__timing__setup__ws": 0.0918154, - "floorplan_io__cpu__total": 1.34, - "floorplan_io__mem__peak": 239152.0, - "floorplan_io__runtime__total": "0:01.48", - "floorplan_macro__cpu__total": 1.33, - "floorplan_macro__mem__peak": 238844.0, - "floorplan_macro__runtime__total": "0:01.49", - "floorplan_pdn__cpu__total": 1.58, - "floorplan_pdn__mem__peak": 243040.0, - "floorplan_pdn__runtime__total": "0:01.72", - "floorplan_tap__cpu__total": 1.35, - "floorplan_tap__mem__peak": 227700.0, - "floorplan_tap__runtime__total": "0:01.51", - "floorplan_tdms__cpu__total": 1.32, - "floorplan_tdms__mem__peak": 239020.0, - "floorplan_tdms__runtime__total": "0:01.48", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 916.4, - "globalplace__design__core__area": 5723.52, - "globalplace__design__die__area": 6363.41, - "globalplace__design__instance__area": 2325.41, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 2325.41, - "globalplace__design__instance__count": 19623, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 19623, - "globalplace__design__instance__utilization": 0.406289, - "globalplace__design__instance__utilization__stdcell": 0.406289, - "globalplace__design__io": 264, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 722680.0, - "globalplace__power__internal__total": 0.0250781, - "globalplace__power__leakage__total": 1.69528e-06, - "globalplace__power__switching__total": 0.0272256, - "globalplace__power__total": 0.0523054, - "globalplace__runtime__total": "2:20.98", - "globalplace__timing__setup__tns": -1711570.0, - "globalplace__timing__setup__ws": -1313.13, - "globalplace_io__cpu__total": 1.35, - "globalplace_io__mem__peak": 242340.0, - "globalplace_io__runtime__total": "0:01.52", - "globalplace_skip_io__cpu__total": 508.89, - "globalplace_skip_io__mem__peak": 271872.0, - "globalplace_skip_io__runtime__total": "0:37.27", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 133.653, - "globalroute__clock__skew__setup": 156.423, - "globalroute__cpu__total": 266.27, - "globalroute__design__core__area": 5723.52, - "globalroute__design__die__area": 6363.41, - "globalroute__design__instance__area": 2730.11, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 2730.11, - "globalroute__design__instance__count": 22002, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 6, - "globalroute__design__instance__count__stdcell": 22002, - "globalroute__design__instance__displacement__max": 1.242, - "globalroute__design__instance__displacement__mean": 0.002, - "globalroute__design__instance__displacement__total": 44.604, - "globalroute__design__instance__utilization": 0.476997, - "globalroute__design__instance__utilization__stdcell": 0.476997, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 835984.0, - "globalroute__power__internal__total": 0.0296022, - "globalroute__power__leakage__total": 2.1448e-06, - "globalroute__power__switching__total": 0.0316034, - "globalroute__power__total": 0.0612077, - "globalroute__route__wirelength__estimated": 96657.7, - "globalroute__runtime__total": "4:04.22", - "globalroute__timing__clock__slack": -44.872, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.38421, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.32468, - "globalroute__timing__drv__setup_violation_count": 160, - "globalroute__timing__setup__tns": -2305.88, - "globalroute__timing__setup__ws": -44.8721, - "placeopt__cpu__total": 27.32, - "placeopt__design__core__area": 5723.52, - "placeopt__design__die__area": 6363.41, - "placeopt__design__instance__area": 2583.61, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 2583.61, - "placeopt__design__instance__count": 21562, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 21562, - "placeopt__design__instance__utilization": 0.451401, - "placeopt__design__instance__utilization__stdcell": 0.451401, - "placeopt__design__io": 264, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 562316.0, - "placeopt__power__internal__total": 0.025706, - "placeopt__power__leakage__total": 1.99617e-06, - "placeopt__power__switching__total": 0.0285134, - "placeopt__power__total": 0.0542214, - "placeopt__runtime__total": "0:27.83", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.410516, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.409305, - "placeopt__timing__drv__setup_violation_count": 185, - "placeopt__timing__setup__tns": -7503.72, - "placeopt__timing__setup__ws": -68.2617, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "ed409357-0eea-4e35-aa86-b6400e2b9f6e", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 61.02, - "synth__design__instance__area__stdcell": 2296.52496, - "synth__design__instance__count__stdcell": 18638.0, - "synth__mem__peak": 228820.0, - "synth__runtime__total": "1:01.40", - "total_time": "0:13:21.800000" -} \ No newline at end of file diff --git a/flow/designs/asap7/ibex/rules-base.json b/flow/designs/asap7/ibex/rules-base.json index ab3ba904ba..ab9f3184ac 100644 --- a/flow/designs/asap7/ibex/rules-base.json +++ b/flow/designs/asap7/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2641.01, + "value": 2612.72, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2971, + "value": 2805, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 24796, + "value": 22941, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2156, + "value": 1995, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2156, + "value": 1995, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 134695, + "value": 106483, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -127.02, + "value": -75.22, "compare": ">=" }, "finish__design__instance__area": { - "value": 3140, + "value": 2867, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1078, + "value": 997, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -17.16, + "value": -11.43, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/autotuner.json b/flow/designs/asap7/jpeg/autotuner.json index d9eb088154..1b9ca0761e 100644 --- a/flow/designs/asap7/jpeg/autotuner.json +++ b/flow/designs/asap7/jpeg/autotuner.json @@ -11,19 +11,11 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 0, - 20 + 20, + 50 ], "step": 1 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CORE_ASPECT_RATIO": { "type": "float", "minmax": [ @@ -35,16 +27,16 @@ "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.6 + 0.2 ], "step": 0 }, diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 040a16d721..bd163e05ff 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 1100 +set clk_period 900 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc index d37e20a0ee..46a528441e 100644 --- a/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_postCTS_14nm.sdc @@ -7,7 +7,7 @@ set_units -time 1.0ps current_design jpeg_encoder create_clock -name "tclk" -period 1000.0 -waveform {0.0 500.0} [get_ports clk] -set_propagated_clock [ all_clocks ] +set_propagated_clock [all_clocks] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[5]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[4]}] set_load -pin_load -max 3.0 [get_ports {qnt_cnt[3]}] @@ -36,113 +36,113 @@ set_load -pin_load -max 3.0 [get_ports {amp[1]}] set_load -pin_load -max 3.0 [get_ports {amp[0]}] set_load -pin_load -max 3.0 [get_ports douten] set_max_delay 500 -from [list \ - [get_clocks tclk] ] -to [list \ - [get_ports douten] \ - [get_ports {amp[0]}] \ - [get_ports {amp[1]}] \ - [get_ports {amp[2]}] \ - [get_ports {amp[3]}] \ - [get_ports {amp[4]}] \ - [get_ports {amp[5]}] \ - [get_ports {amp[6]}] \ - [get_ports {amp[7]}] \ - [get_ports {amp[8]}] \ - [get_ports {amp[9]}] \ - [get_ports {amp[10]}] \ - [get_ports {amp[11]}] \ - [get_ports {rlen[0]}] \ - [get_ports {rlen[1]}] \ - [get_ports {rlen[2]}] \ - [get_ports {rlen[3]}] \ - [get_ports {size[0]}] \ - [get_ports {size[1]}] \ - [get_ports {size[2]}] \ - [get_ports {size[3]}] \ - [get_ports {qnt_cnt[0]}] \ - [get_ports {qnt_cnt[1]}] \ - [get_ports {qnt_cnt[2]}] \ - [get_ports {qnt_cnt[3]}] \ - [get_ports {qnt_cnt[4]}] \ - [get_ports {qnt_cnt[5]}] ] + [get_clocks tclk]] -to [list \ + [get_ports douten] \ + [get_ports {amp[0]}] \ + [get_ports {amp[1]}] \ + [get_ports {amp[2]}] \ + [get_ports {amp[3]}] \ + [get_ports {amp[4]}] \ + [get_ports {amp[5]}] \ + [get_ports {amp[6]}] \ + [get_ports {amp[7]}] \ + [get_ports {amp[8]}] \ + [get_ports {amp[9]}] \ + [get_ports {amp[10]}] \ + [get_ports {amp[11]}] \ + [get_ports {rlen[0]}] \ + [get_ports {rlen[1]}] \ + [get_ports {rlen[2]}] \ + [get_ports {rlen[3]}] \ + [get_ports {size[0]}] \ + [get_ports {size[1]}] \ + [get_ports {size[2]}] \ + [get_ports {size[3]}] \ + [get_ports {qnt_cnt[0]}] \ + [get_ports {qnt_cnt[1]}] \ + [get_ports {qnt_cnt[2]}] \ + [get_ports {qnt_cnt[3]}] \ + [get_ports {qnt_cnt[4]}] \ + [get_ports {qnt_cnt[5]}]] set_min_delay 500 \ - -from [list \ - [get_ports ena] \ - [get_ports rst] ] \ - -to [list \ - [get_clocks tclk] ] + -from [list \ + [get_ports ena] \ + [get_ports rst]] \ + -to [list \ + [get_clocks tclk]] group_path -weight 1.000000 -name cg_enable_group_tclk -through [list \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] \ - [get_pins qnr_RC_CG_HIER_INST3/enable] \ - [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ - [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ - [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ - [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ - [get_pins RC_CG_DECLONE_HIER_INST/enable] ] + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable] \ + [get_pins qnr_RC_CG_HIER_INST3/enable] \ + [get_pins rle_rz1_RC_CG_HIER_INST134/enable] \ + [get_pins rle_rz2_RC_CG_HIER_INST136/enable] \ + [get_pins rle_rz3_RC_CG_HIER_INST138/enable] \ + [get_pins rle_rz4_RC_CG_HIER_INST140/enable] \ + [get_pins RC_CG_DECLONE_HIER_INST/enable]] set_clock_gating_check -setup 0.0 -set_input_delay 100 -clock tclk [get_ports ena] -set_input_delay 100 -clock tclk [get_ports rst] +set_input_delay 100 -clock tclk [get_ports ena] +set_input_delay 100 -clock tclk [get_ports rst] -set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] -set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] -set_input_delay 100 -clock tclk [get_ports {din[0]}] -set_input_delay 100 -clock tclk [get_ports {din[1]}] -set_input_delay 100 -clock tclk [get_ports {din[2]}] -set_input_delay 100 -clock tclk [get_ports {din[3]}] -set_input_delay 100 -clock tclk [get_ports {din[4]}] -set_input_delay 100 -clock tclk [get_ports {din[5]}] -set_input_delay 100 -clock tclk [get_ports {din[6]}] -set_input_delay 100 -clock tclk [get_ports {din[7]}] -set_input_delay 100 -clock tclk [get_ports dstrb] -set_output_delay 100 -clock tclk [get_ports douten] -set_output_delay 100 -clock tclk [get_ports {amp[0]}] -set_output_delay 100 -clock tclk [get_ports {amp[1]}] -set_output_delay 100 -clock tclk [get_ports {amp[2]}] -set_output_delay 100 -clock tclk [get_ports {amp[3]}] -set_output_delay 100 -clock tclk [get_ports {amp[4]}] -set_output_delay 100 -clock tclk [get_ports {amp[5]}] -set_output_delay 100 -clock tclk [get_ports {amp[6]}] -set_output_delay 100 -clock tclk [get_ports {amp[7]}] -set_output_delay 100 -clock tclk [get_ports {amp[8]}] -set_output_delay 100 -clock tclk [get_ports {amp[9]}] -set_output_delay 100 -clock tclk [get_ports {amp[10]}] -set_output_delay 100 -clock tclk [get_ports {amp[11]}] -set_output_delay 100 -clock tclk [get_ports {rlen[0]}] -set_output_delay 100 -clock tclk [get_ports {rlen[1]}] -set_output_delay 100 -clock tclk [get_ports {rlen[2]}] -set_output_delay 100 -clock tclk [get_ports {rlen[3]}] -set_output_delay 100 -clock tclk [get_ports {size[0]}] -set_output_delay 100 -clock tclk [get_ports {size[1]}] -set_output_delay 100 -clock tclk [get_ports {size[2]}] -set_output_delay 100 -clock tclk [get_ports {size[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] -set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[0]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[1]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[2]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[3]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[4]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[5]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[6]}] +set_input_delay 100 -clock tclk [get_ports {qnt_val[7]}] +set_input_delay 100 -clock tclk [get_ports {din[0]}] +set_input_delay 100 -clock tclk [get_ports {din[1]}] +set_input_delay 100 -clock tclk [get_ports {din[2]}] +set_input_delay 100 -clock tclk [get_ports {din[3]}] +set_input_delay 100 -clock tclk [get_ports {din[4]}] +set_input_delay 100 -clock tclk [get_ports {din[5]}] +set_input_delay 100 -clock tclk [get_ports {din[6]}] +set_input_delay 100 -clock tclk [get_ports {din[7]}] +set_input_delay 100 -clock tclk [get_ports dstrb] +set_output_delay 100 -clock tclk [get_ports douten] +set_output_delay 100 -clock tclk [get_ports {amp[0]}] +set_output_delay 100 -clock tclk [get_ports {amp[1]}] +set_output_delay 100 -clock tclk [get_ports {amp[2]}] +set_output_delay 100 -clock tclk [get_ports {amp[3]}] +set_output_delay 100 -clock tclk [get_ports {amp[4]}] +set_output_delay 100 -clock tclk [get_ports {amp[5]}] +set_output_delay 100 -clock tclk [get_ports {amp[6]}] +set_output_delay 100 -clock tclk [get_ports {amp[7]}] +set_output_delay 100 -clock tclk [get_ports {amp[8]}] +set_output_delay 100 -clock tclk [get_ports {amp[9]}] +set_output_delay 100 -clock tclk [get_ports {amp[10]}] +set_output_delay 100 -clock tclk [get_ports {amp[11]}] +set_output_delay 100 -clock tclk [get_ports {rlen[0]}] +set_output_delay 100 -clock tclk [get_ports {rlen[1]}] +set_output_delay 100 -clock tclk [get_ports {rlen[2]}] +set_output_delay 100 -clock tclk [get_ports {rlen[3]}] +set_output_delay 100 -clock tclk [get_ports {size[0]}] +set_output_delay 100 -clock tclk [get_ports {size[1]}] +set_output_delay 100 -clock tclk [get_ports {size[2]}] +set_output_delay 100 -clock tclk [get_ports {size[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[0]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[1]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[2]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[3]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[4]}] +set_output_delay 100 -clock tclk [get_ports {qnt_cnt[5]}] set_max_fanout 40.000 [current_design] set_max_transition 80.0 [current_design] set_clock_uncertainty -setup 20.0 [get_clocks tclk] diff --git a/flow/designs/asap7/jpeg/metadata-base-ok.json b/flow/designs/asap7/jpeg/metadata-base-ok.json deleted file mode 100644 index 1d52845b23..0000000000 --- a/flow/designs/asap7/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1100.0000" - ], - "cts__clock__skew__hold": 27.0257, - "cts__clock__skew__setup": 19.1139, - "cts__cpu__total": 331.69, - "cts__design__core__area": 23652, - "cts__design__die__area": 24978.9, - "cts__design__instance__area": 7910.09, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 7910.09, - "cts__design__instance__count": 67298, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 21, - "cts__design__instance__count__stdcell": 67298, - "cts__design__instance__displacement__max": 0.918, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 14.35, - "cts__design__instance__utilization": 0.334437, - "cts__design__instance__utilization__stdcell": 0.334437, - "cts__design__io": 47, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 10, - "cts__mem__peak": 2714436.0, - "cts__power__internal__total": 0.062715, - "cts__power__leakage__total": 5.57221e-06, - "cts__power__switching__total": 0.071118, - "cts__power__total": 0.133839, - "cts__route__wirelength__estimated": 265486, - "cts__runtime__total": "2:57.34", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.295946, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 2, - "cts__timing__drv__max_slew_limit": -0.00229773, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.130118, - "design__io__hpwl": 1768800, - "design__violations": 0, - "detailedplace__cpu__total": 59.99, - "detailedplace__design__core__area": 23652, - "detailedplace__design__die__area": 24978.9, - "detailedplace__design__instance__area": 7756.57, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 7756.57, - "detailedplace__design__instance__count": 66819, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 66819, - "detailedplace__design__instance__displacement__max": 2.003, - "detailedplace__design__instance__displacement__mean": 0.217, - "detailedplace__design__instance__displacement__total": 14557.1, - "detailedplace__design__instance__utilization": 0.327946, - "detailedplace__design__instance__utilization__stdcell": 0.327946, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 575336.0, - "detailedplace__power__internal__total": 0.0592561, - "detailedplace__power__leakage__total": 5.42541e-06, - "detailedplace__power__switching__total": 0.0684827, - "detailedplace__power__total": 0.127744, - "detailedplace__route__wirelength__estimated": 266852, - "detailedplace__runtime__total": "1:00.42", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.29603, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.00299049, - "detailedplace__timing__drv__setup_violation_count": 6, - "detailedplace__timing__setup__tns": -87.2221, - "detailedplace__timing__setup__ws": -62.4738, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 12633, - "detailedroute__route__drc_errors__iter:2": 1621, - "detailedroute__route__drc_errors__iter:3": 1174, - "detailedroute__route__drc_errors__iter:4": 28, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 76018, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 533712, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 533712, - "detailedroute__route__wirelength": 297989, - "detailedroute__route__wirelength__iter:1": 299606, - "detailedroute__route__wirelength__iter:2": 298198, - "detailedroute__route__wirelength__iter:3": 297961, - "detailedroute__route__wirelength__iter:4": 297988, - "detailedroute__route__wirelength__iter:5": 297989, - "finish__clock__skew__hold": 30.3785, - "finish__clock__skew__setup": 30.4063, - "finish__cpu__total": 150.76, - "finish__design__core__area": 23652, - "finish__design__die__area": 24978.9, - "finish__design__instance__area": 7910.23, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 7910.23, - "finish__design__instance__count": 67300, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 67300, - "finish__design__instance__utilization": 0.334443, - "finish__design__instance__utilization__stdcell": 0.334443, - "finish__design__io": 47, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.714507, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0564248, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.218594, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.224463, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.551406, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.224463, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 2123744.0, - "finish__power__internal__total": 0.0628327, - "finish__power__leakage__total": 5.5723e-06, - "finish__power__switching__total": 0.0747136, - "finish__power__total": 0.137552, - "finish__runtime__total": "2:33.23", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0758938, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 24, - "finish__timing__drv__max_slew_limit": -0.43754, - "finish__timing__drv__setup_violation_count": 43, - "finish__timing__setup__tns": -892.501, - "finish__timing__setup__ws": -78.9033, - "finish__timing__wns_percent_delay": -5.947052, - "finish_merge__cpu__total": 6.33, - "finish_merge__mem__peak": 935088.0, - "finish_merge__runtime__total": "0:06.98", - "floorplan__cpu__total": 30.12, - "floorplan__design__core__area": 23652, - "floorplan__design__die__area": 24978.9, - "floorplan__design__instance__area": 7119.2, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 7119.2, - "floorplan__design__instance__count": 63844, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 63844, - "floorplan__design__instance__utilization": 0.300998, - "floorplan__design__instance__utilization__stdcell": 0.300998, - "floorplan__design__io": 47, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 464180.0, - "floorplan__power__internal__total": 0.0578225, - "floorplan__power__leakage__total": 4.6902e-06, - "floorplan__power__switching__total": 0.0517279, - "floorplan__power__total": 0.109555, - "floorplan__runtime__total": "0:30.59", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 189.117, - "floorplan_io__cpu__total": 1.93, - "floorplan_io__mem__peak": 308672.0, - "floorplan_io__runtime__total": "0:02.18", - "floorplan_macro__cpu__total": 1.92, - "floorplan_macro__mem__peak": 306840.0, - "floorplan_macro__runtime__total": "0:02.18", - "floorplan_pdn__cpu__total": 3.01, - "floorplan_pdn__mem__peak": 323964.0, - "floorplan_pdn__runtime__total": "0:03.27", - "floorplan_tap__cpu__total": 2.28, - "floorplan_tap__mem__peak": 269612.0, - "floorplan_tap__runtime__total": "0:02.53", - "floorplan_tdms__cpu__total": 1.94, - "floorplan_tdms__mem__peak": 306188.0, - "floorplan_tdms__runtime__total": "0:02.19", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 1920.51, - "globalplace__design__core__area": 23652, - "globalplace__design__die__area": 24978.9, - "globalplace__design__instance__area": 7202.33, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 7202.33, - "globalplace__design__instance__count": 66695, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 66695, - "globalplace__design__instance__utilization": 0.304513, - "globalplace__design__instance__utilization__stdcell": 0.304513, - "globalplace__design__io": 47, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 1167924.0, - "globalplace__power__internal__total": 0.0584153, - "globalplace__power__leakage__total": 4.6902e-06, - "globalplace__power__switching__total": 0.065679, - "globalplace__power__total": 0.124099, - "globalplace__runtime__total": "7:26.99", - "globalplace__timing__setup__tns": -2830.14, - "globalplace__timing__setup__ws": -98.5856, - "globalplace_io__cpu__total": 2.11, - "globalplace_io__mem__peak": 315084.0, - "globalplace_io__runtime__total": "0:02.37", - "globalplace_skip_io__cpu__total": 439.55, - "globalplace_skip_io__mem__peak": 411928.0, - "globalplace_skip_io__runtime__total": "1:08.10", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 30.3788, - "globalroute__clock__skew__setup": 24.5023, - "globalroute__cpu__total": 153.07, - "globalroute__design__core__area": 23652, - "globalroute__design__die__area": 24978.9, - "globalroute__design__instance__area": 7910.23, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 7910.23, - "globalroute__design__instance__count": 67300, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 2, - "globalroute__design__instance__count__stdcell": 67300, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.334443, - "globalroute__design__instance__utilization__stdcell": 0.334443, - "globalroute__design__io": 47, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 11, - "globalroute__mem__peak": 1341460.0, - "globalroute__power__internal__total": 0.0627962, - "globalroute__power__leakage__total": 5.5723e-06, - "globalroute__power__switching__total": 0.0748223, - "globalroute__power__total": 0.137624, - "globalroute__route__wirelength__estimated": 265488, - "globalroute__runtime__total": "1:38.09", - "globalroute__timing__clock__slack": 0.859, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.279473, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.027861, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.858758, - "placeopt__cpu__total": 58.96, - "placeopt__design__core__area": 23652, - "placeopt__design__die__area": 24978.9, - "placeopt__design__instance__area": 7756.57, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 7756.57, - "placeopt__design__instance__count": 66819, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 66819, - "placeopt__design__instance__utilization": 0.327946, - "placeopt__design__instance__utilization__stdcell": 0.327946, - "placeopt__design__io": 47, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 761180.0, - "placeopt__power__internal__total": 0.059255, - "placeopt__power__leakage__total": 5.42541e-06, - "placeopt__power__switching__total": 0.0683455, - "placeopt__power__total": 0.127606, - "placeopt__runtime__total": "0:59.58", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.294264, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0039844, - "placeopt__timing__drv__setup_violation_count": 5, - "placeopt__timing__setup__tns": -81.4452, - "placeopt__timing__setup__ws": -60.7567, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "b15a4ad1-18a2-409f-b13e-161f53849697", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 151.65, - "synth__design__instance__area__stdcell": 7119.1953, - "synth__design__instance__count__stdcell": 63844.0, - "synth__mem__peak": 959680.0, - "synth__runtime__total": "2:47.23", - "total_time": "0:21:23.270000" -} \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index 1e7e176812..37cf7724de 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 8187.08, + "value": 7008.24, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 8920, + "value": 7287, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 76842, + "value": 63593, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6682, + "value": 5530, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6682, + "value": 5530, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 342687, + "value": 181528, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -133.9, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 9097, + "value": 7375, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3341, + "value": 2765, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -17.13, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg_lvt/config.mk b/flow/designs/asap7/jpeg_lvt/config.mk index 975596c3a4..4b77c09e67 100644 --- a/flow/designs/asap7/jpeg_lvt/config.mk +++ b/flow/designs/asap7/jpeg_lvt/config.mk @@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc export ABC_AREA = 1 -export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib - -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef - export CORE_UTILIZATION = 30 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 @@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60 export TNS_END_PERCENT = 100 export RECOVER_POWER = 100 +export ASAP7_USE_VT = LVT + + diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index a1f1601f12..d1aa7a70f9 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1100 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/jpeg_lvt/metadata-base-ok.json b/flow/designs/asap7/jpeg_lvt/metadata-base-ok.json deleted file mode 100644 index a566567781..0000000000 --- a/flow/designs/asap7/jpeg_lvt/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1100.0000" - ], - "cts__clock__skew__hold": 33.6526, - "cts__clock__skew__setup": 23.8444, - "cts__cpu__total": 62.33, - "cts__design__core__area": 24060.6, - "cts__design__die__area": 25381.3, - "cts__design__instance__area": 8002.55, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 8002.55, - "cts__design__instance__count": 69674, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 3, - "cts__design__instance__count__stdcell": 69674, - "cts__design__instance__displacement__max": 0.531, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 1.437, - "cts__design__instance__utilization": 0.332599, - "cts__design__instance__utilization__stdcell": 0.332599, - "cts__design__io": 47, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 20, - "cts__mem__peak": 1291316.0, - "cts__power__internal__total": 0.0692385, - "cts__power__leakage__total": 1.8709e-05, - "cts__power__switching__total": 0.0770183, - "cts__power__total": 0.146275, - "cts__route__wirelength__estimated": 266755, - "cts__runtime__total": "1:03.39", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.231705, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.103364, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 13.4989, - "design__io__hpwl": 1976040, - "design__violations": 0, - "detailedplace__cpu__total": 67.24, - "detailedplace__design__core__area": 24060.6, - "detailedplace__design__die__area": 25381.3, - "detailedplace__design__instance__area": 7861.33, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 7861.33, - "detailedplace__design__instance__count": 69220, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 69220, - "detailedplace__design__instance__displacement__max": 2.904, - "detailedplace__design__instance__displacement__mean": 0.22, - "detailedplace__design__instance__displacement__total": 15291.9, - "detailedplace__design__instance__utilization": 0.32673, - "detailedplace__design__instance__utilization__stdcell": 0.32673, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 20, - "detailedplace__mem__peak": 689156.0, - "detailedplace__power__internal__total": 0.0658149, - "detailedplace__power__leakage__total": 1.84795e-05, - "detailedplace__power__switching__total": 0.0743483, - "detailedplace__power__total": 0.140182, - "detailedplace__route__wirelength__estimated": 268148, - "detailedplace__runtime__total": "1:07.81", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.231789, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.103815, - "detailedplace__timing__drv__setup_violation_count": 3, - "detailedplace__timing__setup__tns": -25.5687, - "detailedplace__timing__setup__ws": -18.907, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 21, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 13056, - "detailedroute__route__drc_errors__iter:2": 1664, - "detailedroute__route__drc_errors__iter:3": 998, - "detailedroute__route__drc_errors__iter:4": 8, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 78371, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 543540, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 543540, - "detailedroute__route__wirelength": 299077, - "detailedroute__route__wirelength__iter:1": 300687, - "detailedroute__route__wirelength__iter:2": 299145, - "detailedroute__route__wirelength__iter:3": 299047, - "detailedroute__route__wirelength__iter:4": 299075, - "detailedroute__route__wirelength__iter:5": 299077, - "finish__clock__skew__hold": 44.5938, - "finish__clock__skew__setup": 43.9965, - "finish__cpu__total": 174.27, - "finish__design__core__area": 24060.6, - "finish__design__die__area": 25381.3, - "finish__design__instance__area": 7937.16, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 7937.16, - "finish__design__instance__count": 69674, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 69674, - "finish__design__instance__utilization": 0.329882, - "finish__design__instance__utilization__stdcell": 0.329882, - "finish__design__io": 47, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.702061, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0693394, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.247989, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.251199, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.522011, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.251199, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 20, - "finish__mem__peak": 2193432.0, - "finish__power__internal__total": 0.0693086, - "finish__power__leakage__total": 1.79309e-05, - "finish__power__switching__total": 0.0804048, - "finish__power__total": 0.149731, - "finish__runtime__total": "2:56.53", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.219944, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 4, - "finish__timing__drv__max_slew_limit": -0.425299, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 80.2294, - "finish__timing__wns_percent_delay": 6.805113, - "finish_merge__cpu__total": 7.09, - "finish_merge__mem__peak": 951488.0, - "finish_merge__runtime__total": "0:07.78", - "floorplan__cpu__total": 26.64, - "floorplan__design__core__area": 24060.6, - "floorplan__design__die__area": 25381.3, - "floorplan__design__instance__area": 7236.84, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 7236.84, - "floorplan__design__instance__count": 66220, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 66220, - "floorplan__design__instance__utilization": 0.300775, - "floorplan__design__instance__utilization__stdcell": 0.300775, - "floorplan__design__io": 47, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 22, - "floorplan__mem__peak": 575956.0, - "floorplan__power__internal__total": 0.0589987, - "floorplan__power__leakage__total": 1.07509e-05, - "floorplan__power__switching__total": 0.0541253, - "floorplan__power__total": 0.113135, - "floorplan__runtime__total": "0:27.03", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 186.739, - "floorplan_io__cpu__total": 2.77, - "floorplan_io__mem__peak": 415512.0, - "floorplan_io__runtime__total": "0:03.03", - "floorplan_macro__cpu__total": 2.81, - "floorplan_macro__mem__peak": 414392.0, - "floorplan_macro__runtime__total": "0:03.07", - "floorplan_pdn__cpu__total": 3.63, - "floorplan_pdn__mem__peak": 431720.0, - "floorplan_pdn__runtime__total": "0:03.93", - "floorplan_tap__cpu__total": 3.07, - "floorplan_tap__mem__peak": 376612.0, - "floorplan_tap__runtime__total": "0:03.31", - "floorplan_tdms__cpu__total": 2.78, - "floorplan_tdms__mem__peak": 414216.0, - "floorplan_tdms__runtime__total": "0:03.06", - "flow__errors__count": 0, - "flow__warnings__count": 20, - "globalplace__cpu__total": 2375.42, - "globalplace__design__core__area": 24060.6, - "globalplace__design__die__area": 25381.3, - "globalplace__design__instance__area": 7320.71, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 7320.71, - "globalplace__design__instance__count": 69096, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 69096, - "globalplace__design__instance__utilization": 0.304261, - "globalplace__design__instance__utilization__stdcell": 0.304261, - "globalplace__design__io": 47, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 20, - "globalplace__mem__peak": 1545812.0, - "globalplace__power__internal__total": 0.0595603, - "globalplace__power__leakage__total": 1.07509e-05, - "globalplace__power__switching__total": 0.0676731, - "globalplace__power__total": 0.127244, - "globalplace__runtime__total": "9:29.54", - "globalplace__timing__setup__tns": -9965, - "globalplace__timing__setup__ws": -154.843, - "globalplace_io__cpu__total": 2.78, - "globalplace_io__mem__peak": 422200.0, - "globalplace_io__runtime__total": "0:03.14", - "globalplace_skip_io__cpu__total": 545.67, - "globalplace_skip_io__mem__peak": 522160.0, - "globalplace_skip_io__runtime__total": "0:57.06", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 37.4603, - "globalroute__clock__skew__setup": 34.4476, - "globalroute__cpu__total": 729.94, - "globalroute__design__core__area": 24060.6, - "globalroute__design__die__area": 25381.3, - "globalroute__design__instance__area": 7937.16, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 7937.16, - "globalroute__design__instance__count": 69674, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 69674, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.329882, - "globalroute__design__instance__utilization__stdcell": 0.329882, - "globalroute__design__io": 47, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 21, - "globalroute__mem__peak": 1721404.0, - "globalroute__power__internal__total": 0.0693178, - "globalroute__power__leakage__total": 1.79309e-05, - "globalroute__power__switching__total": 0.0810957, - "globalroute__power__total": 0.150431, - "globalroute__route__wirelength__estimated": 266755, - "globalroute__runtime__total": "11:39.59", - "globalroute__timing__clock__slack": 2.756, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.215205, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 1, - "globalroute__timing__drv__max_slew_limit": -0.0125733, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 2.75646, - "placeopt__cpu__total": 79.09, - "placeopt__design__core__area": 24060.6, - "placeopt__design__die__area": 25381.3, - "placeopt__design__instance__area": 7861.33, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 7861.33, - "placeopt__design__instance__count": 69220, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 69220, - "placeopt__design__instance__utilization": 0.32673, - "placeopt__design__instance__utilization__stdcell": 0.32673, - "placeopt__design__io": 47, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 20, - "placeopt__mem__peak": 1121740.0, - "placeopt__power__internal__total": 0.0658253, - "placeopt__power__leakage__total": 1.84795e-05, - "placeopt__power__switching__total": 0.0742225, - "placeopt__power__total": 0.140066, - "placeopt__runtime__total": "1:21.82", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.232003, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.106794, - "placeopt__timing__drv__setup_violation_count": 6, - "placeopt__timing__setup__tns": -101.051, - "placeopt__timing__setup__ws": -37.618, - "run__flow__design": "jpeg_lvt", - "run__flow__generate_date": "2024-09-26 21:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "6c908765-1cac-46b3-bf81-f01a7aa14c64", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 115.47, - "synth__design__instance__area__stdcell": 7236.84132, - "synth__design__instance__count__stdcell": 66220.0, - "synth__mem__peak": 988152.0, - "synth__runtime__total": "1:57.16", - "total_time": "0:31:27.250000" -} \ No newline at end of file diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index 904903d986..8f6bc56ba2 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 8322.37, + "value": 7116.74, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 9041, + "value": 7477, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 79603, + "value": 66675, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6922, + "value": 5798, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6922, + "value": 5798, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 343939, + "value": 187616, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 9128, + "value": 7543, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3461, + "value": 2899, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/asap7/minimal/README.md b/flow/designs/asap7/minimal/README.md new file mode 100644 index 0000000000..fb9e536a26 --- /dev/null +++ b/flow/designs/asap7/minimal/README.md @@ -0,0 +1,117 @@ +# Report on a design prior to setting up a configuration + +This configuration allows running synthesis and floorplan +to extract some basic information useful when setting +up a config.mk file from scratch. + +Below, instructions are given to run synthesis, floorplan, placement and +global route, then examine the results in the GUI to see what a +realistic floorplan and settings might be for your Verilog files. + +The example below uses the designs/src/aes/*.v Verilog files, but +the Verilog files do not have to be located in the OpenROAD-flow-scripts +git repository, adjust the VERILOG_FILES argument to point to your Verilog +files: + +``` +make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_synth synth gui_synth +``` + +Where, the exploratory config.mk file to be replaced +by a design specific config.mk file is: + +``` +DESIGN_CONFIG=designs/asap7/minimal/config.mk +``` + +Verilog files that to be investigated are specified by: + +``` +VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" +``` + +The Verilog top module name is specified by: + +``` +DESIGN_NAME=aes_cipher_top +``` + +Synthesis cleaned and re-run by: + +``` +clean_synth synth +``` + +The GUI is opened by the makefile target: + +``` +gui_synth +``` + +## `make gui_synth` OpenROAD GUI information + +![Alt text](gui_synth.png) + +The module hierarchy can here be examined to give a sense of +area required for the default placement density. + +## `make gui_floorplan` OpenROAD GUI information + +Next to iterate on floorplan settings: + +``` +make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_floorplan floorplan gui_floorplan +``` + +A few more things can be learned from looking at this minimal floorplan: + +- The pins are placed randomly on the edges and at least there + is enough space on the edges to fit the top level pins +- Check that the floorplan size is not completely unreasonable and + at least there is a chance that this design could go through + placement with this density. + +![Alt text](gui_floorplan.png) + +## `make gui_place` OpenROAD GUI information + +Next to iterate on placement settings: + +``` +make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_place place gui_place +``` + +![Alt text](gui_place_heatmap.png) + +![Alt text](gui_place_module.png) + +From placement more information about how to set up the config.mk +file can be learned: + +- Examine estimated routing congestion to get a sense if there + is a chance that the design can be routed. +- Get a sense of size and location of modules + +## CTS(Clock tree Synthesis) + +After placement, CTS (clock tree synthesis is run). However the minimal design does +not have a clock, so CTS runs quickly, but does nothing. + +## `make gui_grt` OpenROAD GUI information + +For non-trivial designs, some more work will need to be done in floorplan and +placement before there is a chance that global routing will complete: + +``` +make DESIGN_CONFIG=designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls designs/src/aes/*.v | xargs)" clean_place place gui_place +``` + +![Alt text](gui_grt.png) + +Global routing congestion heatmap can be examined in the GUI. + +## Next steps + +Start creating a config.mk file for your design, write an .sdc file to +examine timing and find reasonable values for the CORE_UTILIZATION +and PLACE_DENSITY for your design considering routing congestion. diff --git a/flow/designs/asap7/minimal/config.mk b/flow/designs/asap7/minimal/config.mk new file mode 100644 index 0000000000..ce53e6c2aa --- /dev/null +++ b/flow/designs/asap7/minimal/config.mk @@ -0,0 +1,23 @@ +export DESIGN_NICKNAME = minimal +export SDC_FILE = $(FLOW_HOME)/designs/asap7/minimal/empty.sdc +export PLATFORM = asap7 +# Faster build and more information in GUI with hierarchical synthesis +export SYNTH_HIERARCHICAL ?= 1 +# Keep all modules so we can examine the full hierarchy +export SYNTH_MINIMUM_KEEP_SIZE ?= 0 + +# Set the core utilization to 10% for the minimal design to +# maximize chances of getting an initial floorplan. This +# provides a generous area, yet not so big as to make making +# floorplan problematic +export CORE_UTILIZATION ?= 10 +# Low placement density to maximize chances of getting a floorplan +export PLACE_DENSITY ?= 0.20 + +# This won't work with an empty .sdc file +export SKIP_REPORT_METRICS = 1 + +# Faster build, remove these in your own config.mk +export SKIP_CTS_REPAIR_TIMING = 1 +export REMOVE_ABC_BUFFERS = 1 +export SKIP_INCREMENTAL_REPAIR = 1 diff --git a/flow/designs/asap7/minimal/empty.sdc b/flow/designs/asap7/minimal/empty.sdc new file mode 100644 index 0000000000..544afd58e7 --- /dev/null +++ b/flow/designs/asap7/minimal/empty.sdc @@ -0,0 +1,2 @@ +# Creating a basic .sdc file is beyond the scope of +# simple configuration, much as writing Verilog is. diff --git a/flow/designs/asap7/minimal/gui_floorplan.png b/flow/designs/asap7/minimal/gui_floorplan.png new file mode 100644 index 0000000000..59690cf85f Binary files /dev/null and b/flow/designs/asap7/minimal/gui_floorplan.png differ diff --git a/flow/designs/asap7/minimal/gui_grt.png b/flow/designs/asap7/minimal/gui_grt.png new file mode 100644 index 0000000000..1f44d1d657 Binary files /dev/null and b/flow/designs/asap7/minimal/gui_grt.png differ diff --git a/flow/designs/asap7/minimal/gui_place_heatmap.png b/flow/designs/asap7/minimal/gui_place_heatmap.png new file mode 100644 index 0000000000..d4c891ab3d Binary files /dev/null and b/flow/designs/asap7/minimal/gui_place_heatmap.png differ diff --git a/flow/designs/asap7/minimal/gui_place_module.png b/flow/designs/asap7/minimal/gui_place_module.png new file mode 100644 index 0000000000..4ab4242b05 Binary files /dev/null and b/flow/designs/asap7/minimal/gui_place_module.png differ diff --git a/flow/designs/asap7/minimal/gui_synth.png b/flow/designs/asap7/minimal/gui_synth.png new file mode 100644 index 0000000000..54d8e821ef Binary files /dev/null and b/flow/designs/asap7/minimal/gui_synth.png differ diff --git a/flow/designs/asap7/mock-alu/autotuner.json b/flow/designs/asap7/mock-alu/autotuner.json index 4b554b69c6..9be9e3ce62 100644 --- a/flow/designs/asap7/mock-alu/autotuner.json +++ b/flow/designs/asap7/mock-alu/autotuner.json @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 4 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 4 ], "step": 1 }, @@ -64,14 +56,6 @@ ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index ef029372dc..dd93e54e87 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -5,15 +5,15 @@ set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set output_regs [get_cells *io_out_REG*] -if {[llength $output_regs] == 0} { - puts "ERROR: Could not find *io_out_REG*" - exit 1 +if { [llength $output_regs] == 0 } { + puts "Error: Could not find *io_out_REG*" + exit 1 } diff --git a/flow/designs/asap7/mock-alu/metadata-base-ok.json b/flow/designs/asap7/mock-alu/metadata-base-ok.json deleted file mode 100644 index a45e564500..0000000000 --- a/flow/designs/asap7/mock-alu/metadata-base-ok.json +++ /dev/null @@ -1,317 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clock: 100.0000" - ], - "cts__clock__skew__hold": 13.0021, - "cts__clock__skew__setup": 8.89893, - "cts__cpu__total": 184.53, - "cts__design__core__area": 2872.41, - "cts__design__die__area": 3342.11, - "cts__design__instance__area": 1746.29, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 1746.29, - "cts__design__instance__count": 13510, - "cts__design__instance__count__hold_buffer": 189, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 289, - "cts__design__instance__count__stdcell": 13510, - "cts__design__instance__displacement__max": 10.643, - "cts__design__instance__displacement__mean": 0.146, - "cts__design__instance__displacement__total": 1982.43, - "cts__design__instance__utilization": 0.607954, - "cts__design__instance__utilization__stdcell": 0.607954, - "cts__design__io": 200, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 627028.0, - "cts__power__internal__total": 0.0930619, - "cts__power__leakage__total": 1.14282e-06, - "cts__power__switching__total": 0.0865831, - "cts__power__total": 0.179646, - "cts__route__wirelength__estimated": 45778.7, - "cts__runtime__total": "3:05.01", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.748972, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.594594, - "cts__timing__drv__setup_violation_count": 1333, - "cts__timing__setup__tns": -171308, - "cts__timing__setup__ws": -510.648, - "design__io__hpwl": 2972746, - "design__violations": 0, - "detailedplace__cpu__total": 15.32, - "detailedplace__design__core__area": 2872.41, - "detailedplace__design__die__area": 3342.11, - "detailedplace__design__instance__area": 1658.77, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 1658.77, - "detailedplace__design__instance__count": 12866, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 12866, - "detailedplace__design__instance__displacement__max": 3.515, - "detailedplace__design__instance__displacement__mean": 0.267, - "detailedplace__design__instance__displacement__total": 3443.18, - "detailedplace__design__instance__utilization": 0.577483, - "detailedplace__design__instance__utilization__stdcell": 0.577483, - "detailedplace__design__io": 200, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 278112.0, - "detailedplace__power__internal__total": 0.0844703, - "detailedplace__power__leakage__total": 1.06492e-06, - "detailedplace__power__switching__total": 0.0777798, - "detailedplace__power__total": 0.162251, - "detailedplace__route__wirelength__estimated": 42013.8, - "detailedplace__runtime__total": "0:15.52", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.720905, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.52842, - "detailedplace__timing__drv__setup_violation_count": 1267, - "detailedplace__timing__setup__tns": -169594, - "detailedplace__timing__setup__ws": -571.933, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2744, - "detailedroute__route__drc_errors__iter:2": 528, - "detailedroute__route__drc_errors__iter:3": 289, - "detailedroute__route__drc_errors__iter:4": 26, - "detailedroute__route__drc_errors__iter:5": 4, - "detailedroute__route__drc_errors__iter:6": 4, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 14284, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 114236, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 114236, - "detailedroute__route__wirelength": 53387, - "detailedroute__route__wirelength__iter:1": 53738, - "detailedroute__route__wirelength__iter:2": 53380, - "detailedroute__route__wirelength__iter:3": 53376, - "detailedroute__route__wirelength__iter:4": 53387, - "detailedroute__route__wirelength__iter:5": 53387, - "detailedroute__route__wirelength__iter:6": 53388, - "detailedroute__route__wirelength__iter:7": 53387, - "finish__clock__skew__hold": 16.5286, - "finish__clock__skew__setup": 14.8857, - "finish__cpu__total": 30.6, - "finish__design__core__area": 2872.41, - "finish__design__die__area": 3342.11, - "finish__design__instance__area": 1751.79, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 1751.79, - "finish__design__instance__count": 13547, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 13547, - "finish__design__instance__utilization": 0.609868, - "finish__design__instance__utilization__stdcell": 0.609868, - "finish__design__io": 200, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.759246, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0108153, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0911879, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0924941, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.678812, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0924941, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 11, - "finish__mem__peak": 541724.0, - "finish__power__internal__total": 0.0933001, - "finish__power__leakage__total": 1.14886e-06, - "finish__power__switching__total": 0.0909031, - "finish__power__total": 0.184204, - "finish__runtime__total": "0:30.97", - "finish__timing__drv__hold_violation_count": 38, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.732193, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 7, - "finish__timing__drv__max_slew_limit": -0.0135334, - "finish__timing__drv__setup_violation_count": 1334, - "finish__timing__setup__tns": -185996, - "finish__timing__setup__ws": -532.655, - "finish__timing__wns_percent_delay": -74.021395, - "finish_merge__cpu__total": 2.65, - "finish_merge__mem__peak": 487156.0, - "finish_merge__runtime__total": "0:02.99", - "floorplan__cpu__total": 197.58, - "floorplan__design__core__area": 2872.41, - "floorplan__design__die__area": 3342.11, - "floorplan__design__instance__area": 1537.4, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 1537.4, - "floorplan__design__instance__count": 12024, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 20, - "floorplan__design__instance__count__stdcell": 12024, - "floorplan__design__instance__utilization": 0.535232, - "floorplan__design__instance__utilization__stdcell": 0.535232, - "floorplan__design__io": 200, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12895, - "floorplan__mem__peak": 264112.0, - "floorplan__power__internal__total": 0.0804196, - "floorplan__power__leakage__total": 9.54478e-07, - "floorplan__power__switching__total": 0.0624178, - "floorplan__power__total": 0.142838, - "floorplan__runtime__total": "3:17.77", - "floorplan__timing__setup__tns": -133326, - "floorplan__timing__setup__ws": -480.849, - "floorplan_io__cpu__total": 1.78, - "floorplan_io__mem__peak": 228900.0, - "floorplan_io__runtime__total": "0:01.91", - "floorplan_macro__cpu__total": 1.76, - "floorplan_macro__mem__peak": 228124.0, - "floorplan_macro__runtime__total": "0:01.90", - "floorplan_pdn__cpu__total": 1.97, - "floorplan_pdn__mem__peak": 232220.0, - "floorplan_pdn__runtime__total": "0:02.11", - "floorplan_tap__cpu__total": 1.84, - "floorplan_tap__mem__peak": 222496.0, - "floorplan_tap__runtime__total": "0:01.95", - "floorplan_tdms__cpu__total": 1.76, - "floorplan_tdms__mem__peak": 228568.0, - "floorplan_tdms__runtime__total": "0:01.91", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 280.22, - "globalplace__design__core__area": 2872.41, - "globalplace__design__die__area": 3342.11, - "globalplace__design__instance__area": 1554.78, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 1554.78, - "globalplace__design__instance__count": 12620, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 12620, - "globalplace__design__instance__utilization": 0.541282, - "globalplace__design__instance__utilization__stdcell": 0.541282, - "globalplace__design__io": 200, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 636400.0, - "globalplace__power__internal__total": 0.0810216, - "globalplace__power__leakage__total": 9.54478e-07, - "globalplace__power__switching__total": 0.0775077, - "globalplace__power__total": 0.15853, - "globalplace__runtime__total": "1:12.05", - "globalplace__timing__setup__tns": -171637, - "globalplace__timing__setup__ws": -549.436, - "globalplace_io__cpu__total": 1.81, - "globalplace_io__mem__peak": 230364.0, - "globalplace_io__runtime__total": "0:01.98", - "globalplace_skip_io__cpu__total": 193.55, - "globalplace_skip_io__mem__peak": 245196.0, - "globalplace_skip_io__runtime__total": "0:07.95", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 14.5359, - "globalroute__clock__skew__setup": 12.3007, - "globalroute__cpu__total": 116.14, - "globalroute__design__core__area": 2872.41, - "globalroute__design__die__area": 3342.11, - "globalroute__design__instance__area": 1751.79, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 1751.79, - "globalroute__design__instance__count": 13547, - "globalroute__design__instance__count__hold_buffer": 26, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 23, - "globalroute__design__instance__count__stdcell": 13547, - "globalroute__design__instance__displacement__max": 4.428, - "globalroute__design__instance__displacement__mean": 0.042, - "globalroute__design__instance__displacement__total": 569.97, - "globalroute__design__instance__utilization": 0.609868, - "globalroute__design__instance__utilization__stdcell": 0.609868, - "globalroute__design__io": 200, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 696956.0, - "globalroute__power__internal__total": 0.0931304, - "globalroute__power__leakage__total": 1.14886e-06, - "globalroute__power__switching__total": 0.0916432, - "globalroute__power__total": 0.184775, - "globalroute__route__wirelength__estimated": 46377.1, - "globalroute__runtime__total": "1:30.11", - "globalroute__timing__clock__slack": -521.43, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.73941, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.434515, - "globalroute__timing__drv__setup_violation_count": 1333, - "globalroute__timing__setup__tns": -174860, - "globalroute__timing__setup__ws": -521.43, - "placeopt__cpu__total": 16.29, - "placeopt__design__core__area": 2872.41, - "placeopt__design__die__area": 3342.11, - "placeopt__design__instance__area": 1658.77, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 1658.77, - "placeopt__design__instance__count": 12866, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 12866, - "placeopt__design__instance__utilization": 0.577483, - "placeopt__design__instance__utilization__stdcell": 0.577483, - "placeopt__design__io": 200, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 519924.0, - "placeopt__power__internal__total": 0.0845083, - "placeopt__power__leakage__total": 1.06492e-06, - "placeopt__power__switching__total": 0.0776569, - "placeopt__power__total": 0.162166, - "placeopt__runtime__total": "0:16.72", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.720512, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.513893, - "placeopt__timing__drv__setup_violation_count": 1266, - "placeopt__timing__setup__tns": -168415, - "placeopt__timing__setup__ws": -568.971, - "run__flow__design": "mock-alu", - "run__flow__generate_date": "2024-09-27 17:57", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "ec7954e2-a933-4470-8a95-d19baa7f4888", - "run__flow__variant": "base", - "synth__cpu__total": 22.36, - "synth__design__instance__area__stdcell": 1447.85232, - "synth__design__instance__count__stdcell": 11552.0, - "synth__mem__peak": 188528.0, - "synth__runtime__total": "0:22.73", - "total_time": "0:10:53.580000" -} \ No newline at end of file diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index d145792da0..bbec5f551f 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1908, + "value": 1835, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 14796, + "value": 14790, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1287, + "value": 1286, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1287, + "value": 1286, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 61395, + "value": 59049, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -537.65, + "value": -506.14, "compare": ">=" }, "finish__design__instance__area": { - "value": 2015, + "value": 1920, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1401, + "value": 1399, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 148, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -98.82, + "value": -98.1, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-array/BUILD.bazel b/flow/designs/asap7/mock-array/BUILD.bazel new file mode 100644 index 0000000000..e6f26739e5 --- /dev/null +++ b/flow/designs/asap7/mock-array/BUILD.bazel @@ -0,0 +1,186 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow") + +# single source of truth for defaults. +# each number is a unit +# current unit is configured as 2.16 which is on the routing grid for M5 + +# table of Elements - (rows cols width height pitch_x pitch_y) +MOCK_ARRAY_TABLE = [ + 8, + 8, + 20, + 20, + 20, + 22, +] + +# Element'd data width +MOCK_ARRAY_DATAWIDTH = 64 + +# Must be zero for routing by abutment +MACRO_BLOCKAGE_HALO = 0 + +MOCK_ARRAY_SCALE = 45 + +# Routing pitches for relevant metal layers. +# For x, this is M5; for y, this is M4. +# Pitches are specified in OpenROAD-flow-scripts/flow/platforms/asap7/lef/asap7_tech_1x_201209.lef. +# For asap7, x and y pitch is the same. +# +# make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 +# +# the macro needs to be on a multiple of the track pattern +placement_grid_x = 0.048 * MOCK_ARRAY_SCALE + +placement_grid_y = 0.048 * MOCK_ARRAY_SCALE + +# number of Elements in row and column, can be control by user via environment variable +# MOCK_ARRAY_TABLE (rows, cols, width, height, pitch_x, pitch_y) +# rows, cols - number of Element in rows, cols +# width, height - width and height of each Element +# +# When the pitch is equal to the width/height, we have routing by abutment +# https://en.wikipedia.org/wiki/Pitch#Linear_measurement +# +# pitch_x, pitch_y - placement pitch for each Element, in x and y direction +# specification are in unit of placement grid +rows, cols, ce_x, ce_y, pitch_x, pitch_y = MOCK_ARRAY_TABLE + +# Element size is set to multiple of placement grid above +ce_width = ce_x * placement_grid_x + +ce_height = ce_y * placement_grid_y + +# top level core offset +margin_x = placement_grid_x + +margin_y = placement_grid_y + +# Element core margin +ce_margin_x = placement_grid_x * 0.5 + +ce_margin_y = placement_grid_y * 0.5 + +# PDN problems if it is smaller. Not investigated. +array_spacing_x = margin_x * 2 + +array_spacing_y = margin_y * 2 + +array_offset_x = array_spacing_x + margin_x + +array_offset_y = array_spacing_y + margin_y + +# top level core and die size +core_width = ( + 2 * array_spacing_x + ((placement_grid_x * pitch_x) * (cols - 1)) + ce_width +) + +core_height = ( + 2 * array_spacing_y + ((placement_grid_y * pitch_y) * (rows - 1)) + ce_height +) + +die_width = core_width + (margin_x * 2) + +die_height = core_height + (margin_y * 2) + +filegroup( + name = "mock-array-constraints", + srcs = [ + "constraints.sdc", + ], + visibility = [":__subpackages__"], +) + +filegroup( + name = "mock-array-io", + srcs = [ + "io.tcl", + ], + data = [ + "//flow/designs/src/mock-array:util.tcl", + ], + visibility = [":__subpackages__"], +) + +orfs_flow( + name = "MockArray", + arguments = { + "PLACE_PINS_ARGS": "-annealing", + "PLACE_DENSITY": "0.30", + "CORE_AREA": "{} {} {} {}".format( + margin_x, + margin_y, + core_width + margin_x, + core_height + margin_y, + ), + "DIE_AREA": "0 0 {} {}".format( + die_width, + die_height, + ), + "MACRO_PLACE_HALO": "0 2.16", + "RTLMP_BOUNDARY_WT": "0", + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", + "MACRO_ROWS_HALO_X": "0.5", + "MACRO_ROWS_HALO_Y": "0.5", + "MACRO_BLOCKAGE_HALO": "0", + "MAX_ROUTING_LAYER": "M9", + "GDS_ALLOW_EMPTY": "Element", + "PWR_NETS_VOLTAGES": "", + "GND_NETS_VOLTAGES": "", + "IO_PLACER_V": "M5 M7", + "IO_PLACER_H": "M4 M6", + "DETAILED_ROUTE_END_ITERATION": "6", + }, + macros = ["Element_generate_abstract"], + sources = { + "SDC_FILE": [":mock-array-constraints"], + "IO_CONSTRAINTS": [":mock-array-io"], + # "MACRO_PLACEMENT_TCL": [":macro-placement.tcl"], + }, + verilog_files = ["//flow/designs/src/mock-array:verilog"], +) + +filegroup( + name = "mock-array-element-io", + srcs = [ + "Element/io.tcl", + ], + data = [ + "//flow/designs/src/mock-array:util.tcl", + ], + visibility = [":__subpackages__"], +) + +orfs_flow( + name = "Element", + abstract_stage = "route", + arguments = { + "PLACE_DENSITY": "0.82", + "MOCK_ARRAY_ROWS": "8", + "MOCK_ARRAY_COLS": "8", + "DETAILED_ROUTE_END_ITERATION": "6", + "MIN_ROUTING_LAYER": "M2", + "MAX_ROUTING_LAYER": "M5", + "IO_PLACER_H": "M2 M4", + "IO_PLACER_V": "M3 M5", + "PLACE_PINS_ARGS": "-annealing", + "GND_NETS_VOLTAGES": "", + "PWR_NETS_VOLTAGES": "", + "CORE_AREA": "{} {} {} {}".format( + ce_margin_x, + ce_margin_y, + ce_width - ce_margin_x, + ce_height - ce_margin_y, + ), + "DIE_AREA": "0 0 {} {}".format( + ce_width, + ce_height, + ), + "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl", + }, + sources = { + "IO_CONSTRAINTS": [":mock-array-element-io"], + "SDC_FILE": [":mock-array-constraints"], + }, + verilog_files = ["//flow/designs/src/mock-array:verilog"], +) diff --git a/flow/designs/asap7/mock-array/Element/config.mk b/flow/designs/asap7/mock-array/Element/config.mk index 4f4f4c3830..a326e07c32 100644 --- a/flow/designs/asap7/mock-array/Element/config.mk +++ b/flow/designs/asap7/mock-array/Element/config.mk @@ -8,23 +8,23 @@ export SDC_FILE = designs/asap7/mock-array/constraints.sdc export PLATFORM = asap7 -export PLACE_DENSITY = 0.50 +export PLACE_DENSITY = 0.82 export CORE_AREA = $(shell \ export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \ export MOCK_ARRAY_SCALE="$(MOCK_ARRAY_SCALE)" && \ - cd $(dir $(DESIGN_CONFIG))/../ && \ + cd $(DESIGN_DIR)/../ && \ python3 -c "import config; print(f'{config.ce_margin_x} {config.ce_margin_y} {config.ce_width - config.ce_margin_x} {config.ce_height - config.ce_margin_y}')") export DIE_AREA = $(shell \ export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \ export MOCK_ARRAY_SCALE="$(MOCK_ARRAY_SCALE)" && \ - cd $(dir $(DESIGN_CONFIG))/../ && \ + cd $(DESIGN_DIR)/../ && \ python3 -c "import config; print(f'0 0 {config.ce_width} {config.ce_height}')") export IO_CONSTRAINTS = designs/asap7/mock-array/Element/io.tcl -export PDN_TCL = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl # Detailed routing should be easy, limit iterations export DETAILED_ROUTE_END_ITERATION ?= 6 diff --git a/flow/designs/asap7/mock-array/Element/io.tcl b/flow/designs/asap7/mock-array/Element/io.tcl index ebfd7968bb..e0e50243c7 100644 --- a/flow/designs/asap7/mock-array/Element/io.tcl +++ b/flow/designs/asap7/mock-array/Element/io.tcl @@ -1,52 +1,51 @@ -source designs/src/mock-array/util.tcl +# bazel has root of OpenROAD-flow-scripts as working directory +foreach prefix {"" flow/} { + set f ${prefix}designs/src/mock-array/util.tcl + if { [file exists $f] } { + source $f + } +} set assignments [list \ - top bottom \ - [list [ concat \ - {*}[match_pins io_ins_down.*] \ - {*}[match_pins io_outs_up.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_down.*] \ - {*}[match_pins io_ins_up.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_ins_right.*] \ - {*}[match_pins io_outs_left.*] \ - ] \ - [ concat \ - {*}[match_pins io_outs_right.*] \ - {*}[match_pins io_ins_left.*] \ - ]] \ - left right \ - [list [ concat \ - {*}[match_pins io_lsbIns_.*] \ - ] \ - [ concat \ - {*}[match_pins io_lsbOuts_.*] \ - ]] -] + top bottom \ + [list [concat \ + {*}[match_pins io_ins_down.*] \ + {*}[match_pins io_outs_up.*]] \ + [concat \ + {*}[match_pins io_outs_down.*] \ + {*}[match_pins io_ins_up.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_ins_right.*] \ + {*}[match_pins io_outs_left.*]] \ + [concat \ + {*}[match_pins io_outs_right.*] \ + {*}[match_pins io_ins_left.*]]] \ + left right \ + [list [concat \ + {*}[match_pins io_lsbIns_.*]] \ + [concat \ + {*}[match_pins io_lsbOuts_.*]]]] -proc zip {list1 list2} { - set result {} - set length [llength $list1] - set skip [expr [llength $list2] - [llength $list1]] - for {set i 0} {$i < $length} {incr i} { - lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] - } - return $result +proc zip { list1 list2 } { + set result {} + set length [llength $list1] + set skip [expr [llength $list2] - [llength $list1]] + for { set i 0 } { $i < $length } { incr i } { + lappend result [lindex $list2 [expr $skip + $i]] [lindex $list1 $i] + } + return $result } foreach {direction direction2 names} $assignments { - set mirrored [zip {*}$names] - set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] - # Test pins across multiple metal layers; so don't group - # pins as a group of pins must be on a single metal layer. - # - # set_io_pin_constraint -group -order -pin_names [lindex $names 1] - set_io_pin_constraint -mirrored_pins $mirrored + set mirrored [zip {*}$names] + set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1] + # Test pins across multiple metal layers; so don't group + # pins as a group of pins must be on a single metal layer. + # + # set_io_pin_constraint -group -order -pin_names [lindex $names 1] + set_io_pin_constraint -mirrored_pins $mirrored } set_io_pin_constraint -region top:* -pin_names clock diff --git a/flow/designs/asap7/mock-array/README.md b/flow/designs/asap7/mock-array/README.md deleted file mode 100644 index 89f3dd3232..0000000000 --- a/flow/designs/asap7/mock-array/README.md +++ /dev/null @@ -1,46 +0,0 @@ -Mock array big -============== - -A mock array that can be configured in different sizes to generate -interesting test-cases. - -By default, the array is 8x8 elements, has an 8 bit datapath with -Element size of 4x4 unit and Element placement pitch of 6,6 - x,y direction. - -export MOCK_ARRAY_TABLE ?= 8 8 4 4 6 6 - -# Element'd data width -export MOCK_ARRAY_DATAWIDTH ?= 8 - -To create a 4x4 element array with 4 bit datapath with element size of 5x6 and -placement pitch of 8x6, set the user control variable MOCK_ARRAY_TABLE - -``` -export MOCK_ARRAY_TABLE="4 4 5 6 8 6" -export MOCK_ARRAY_DATAWIDTH=4 -export FLOW_VARIANT=small - -export DESIGN_CONFIG=designs/asap7/mock-array/config.mk -``` - -Now run configure, which a custom target in mock-array, that runs Chisel to -regenerate the Verilog code for the above configuration: - -``` -make verilog -``` - -Now build the design as usual: - -``` -make -``` - -CTS ---- - -mock-array and mock-array Element are intended -to be fitted into a higher level module where CTS creates a balanced clock tree -that takes the mock-array and mock-array Element clock insertion -latency into account. This means that the optimization target -for mock-array and mock-array Element have zero skew. diff --git a/flow/designs/asap7/mock-array/config.mk b/flow/designs/asap7/mock-array/config.mk index 52aa1de51e..6b694315ff 100644 --- a/flow/designs/asap7/mock-array/config.mk +++ b/flow/designs/asap7/mock-array/config.mk @@ -14,18 +14,22 @@ export PLACE_DENSITY = 0.30 export CORE_AREA = $(shell \ export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \ export MOCK_ARRAY_SCALE="$(MOCK_ARRAY_SCALE)" && \ - cd $(dir $(DESIGN_CONFIG)) && \ + cd $(DESIGN_DIR) && \ python3 -c "import config ; print(f'{config.margin_x} {config.margin_y} {config.core_width + config.margin_x} {config.core_height + config.margin_y}')") export DIE_AREA = $(shell \ export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \ export MOCK_ARRAY_SCALE="$(MOCK_ARRAY_SCALE)" && \ - cd $(dir $(DESIGN_CONFIG)) && \ + cd $(DESIGN_DIR) && \ python3 -c "import config; print(f'{0} {0} {config.die_width} {config.die_height}')") export MACRO_PLACE_HALO = 0 2.16 export RTLMP_BOUNDARY_WT = 0 export RTLMP_FLOW ?= 1 +export RTLMP_MAX_INST = 250 +export RTLMP_MIN_INST = 50 +export RTLMP_MAX_MACRO = 64 +export RTLMP_MIN_MACRO = 8 export BLOCKS ?= Element @@ -60,13 +64,14 @@ power: export DETAILED_ROUTE_END_ITERATION ?= 6 export MAX_ROUTING_LAYER = M9 -export ROUTING_LAYER_ADJUSTMENT = 0.45 # ensure we have some rows, so we don't get a bad clock skew. -export MACRO_HALO_X = 0.5 -export MACRO_HALO_Y = 0.5 +export MACRO_ROWS_HALO_X = 0.5 +export MACRO_ROWS_HALO_Y = 0.5 -export ADDITIONAL_FILES = designs/src/mock-array/util.tcl +export ADDITIONAL_FILES = \ + designs/src/mock-array/util.tcl \ + designs/asap7/mock-array/macro-placement.tcl export IO_PLACER_V = M5 M7 export IO_PLACER_H = M4 M6 diff --git a/flow/designs/asap7/mock-array/io.tcl b/flow/designs/asap7/mock-array/io.tcl index 37b2d3b874..1bf0ee962b 100644 --- a/flow/designs/asap7/mock-array/io.tcl +++ b/flow/designs/asap7/mock-array/io.tcl @@ -1,29 +1,30 @@ -source designs/src/mock-array/util.tcl +# bazel has root of OpenROAD-flow-scripts as working directory +foreach prefix {"" flow/} { + set f ${prefix}designs/src/mock-array/util.tcl + if { [file exists $f] } { + source $f + } +} set assignments [list \ - top \ - [ concat \ - {*}[match_pins io_ins_down_.*] \ - {*}[match_pins io_outs_up_.*] \ - ] \ - bottom \ - [ concat \ - {*}[match_pins io_ins_up_.*] \ - {*}[match_pins io_outs_down_.*] \ - ] \ - left \ - [ concat \ - {*}[match_pins io_ins_right_.*] \ - {*}[match_pins io_outs_left_.*] \ - ] \ - right \ - [ concat \ - {*}[match_pins io_ins_left_.*] \ - {*}[match_pins io_outs_right_.*] \ - {*}[match_pins io_lsbs_.*] \ - ] \ -] + top \ + [concat \ + {*}[match_pins io_ins_down_.*] \ + {*}[match_pins io_outs_up_.*]] \ + bottom \ + [concat \ + {*}[match_pins io_ins_up_.*] \ + {*}[match_pins io_outs_down_.*]] \ + left \ + [concat \ + {*}[match_pins io_ins_right_.*] \ + {*}[match_pins io_outs_left_.*]] \ + right \ + [concat \ + {*}[match_pins io_ins_left_.*] \ + {*}[match_pins io_outs_right_.*] \ + {*}[match_pins io_lsbs_.*]]] foreach {direction names} $assignments { - set_io_pin_constraint -region $direction:* -pin_names $names + set_io_pin_constraint -region $direction:* -pin_names $names } diff --git a/flow/designs/asap7/mock-array/macro-placement.tcl b/flow/designs/asap7/mock-array/macro-placement.tcl index 18bd768798..6eed9be902 100644 --- a/flow/designs/asap7/mock-array/macro-placement.tcl +++ b/flow/designs/asap7/mock-array/macro-placement.tcl @@ -15,11 +15,14 @@ set x_offset [expr [$core xMin] + ([$core dx] - (7 * $x_pitch) - [$bbox getDX])/ set y_offset [expr [$core yMin] + ([$core dy] - (7 * $y_pitch) - [$bbox getDY])/2] # Loop through the 8x8 array, add the offset, and invoke place_macro -for {set i 0} {$i < 8} {incr i} { - for {set j 0} {$j < 8} {incr j} { - set macro_name [format "ces_%d_%d" $i $j] - set x_location [expr {$j * $x_pitch + $x_offset}] - set y_location [expr {$i * $y_pitch + $y_offset}] - place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0 - } +for { set i 0 } { $i < 8 } { incr i } { + for { set j 0 } { $j < 8 } { incr j } { + set macro_name [format "ces_%d_%d" $i $j] + set x_location [expr { $j * $x_pitch + $x_offset }] + set y_location [expr { $i * $y_pitch + $y_offset }] + place_macro -macro_name $macro_name -location \ + [list [expr [ord::dbu_to_microns 1] * $x_location] \ + [expr [ord::dbu_to_microns 1] * $y_location]] \ + -orientation R0 + } } diff --git a/flow/designs/asap7/mock-array/metadata-base-ok.json b/flow/designs/asap7/mock-array/metadata-base-ok.json deleted file mode 100644 index 40d778a9ba..0000000000 --- a/flow/designs/asap7/mock-array/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clock: 250.0000" - ], - "cts__clock__skew__hold": 108.962, - "cts__clock__skew__setup": 82.901, - "cts__cpu__total": 11.01, - "cts__design__core__area": 136198, - "cts__design__die__area": 139408, - "cts__design__instance__area": 119971, - "cts__design__instance__area__macros": 119439, - "cts__design__instance__area__stdcell": 531.951, - "cts__design__instance__count": 10831, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 64, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 10767, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.880858, - "cts__design__instance__utilization__stdcell": 0.0317415, - "cts__design__io": 4162, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 10, - "cts__mem__peak": 1012528.0, - "cts__power__internal__total": 0.00225967, - "cts__power__leakage__total": 2.62493e-07, - "cts__power__switching__total": 0.00219979, - "cts__power__total": 0.00445973, - "cts__route__wirelength__estimated": 63522.2, - "cts__runtime__total": "0:11.66", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 1, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.585108, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 22.2414, - "design__io__hpwl": 28062723, - "design__violations": 0, - "detailedplace__cpu__total": 9.41, - "detailedplace__design__core__area": 136198, - "detailedplace__design__die__area": 139408, - "detailedplace__design__instance__area": 119955, - "detailedplace__design__instance__area__macros": 119439, - "detailedplace__design__instance__area__stdcell": 516.074, - "detailedplace__design__instance__count": 10790, - "detailedplace__design__instance__count__macros": 64, - "detailedplace__design__instance__count__stdcell": 10726, - "detailedplace__design__instance__displacement__max": 1.396, - "detailedplace__design__instance__displacement__mean": 0.243, - "detailedplace__design__instance__displacement__total": 2629.69, - "detailedplace__design__instance__utilization": 0.880742, - "detailedplace__design__instance__utilization__stdcell": 0.0307941, - "detailedplace__design__io": 4162, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 705024.0, - "detailedplace__power__internal__total": 0.00033438, - "detailedplace__power__leakage__total": 2.46076e-07, - "detailedplace__power__switching__total": 8.23736e-14, - "detailedplace__power__total": 0.000334626, - "detailedplace__route__wirelength__estimated": 62778.2, - "detailedplace__runtime__total": "0:09.83", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.971797, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.937366, - "detailedplace__timing__drv__setup_violation_count": 17, - "detailedplace__timing__setup__tns": -433.868, - "detailedplace__timing__setup__ws": -28.8544, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2453, - "detailedroute__route__drc_errors__iter:2": 60, - "detailedroute__route__drc_errors__iter:3": 10, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 23325, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 53413, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 53413, - "detailedroute__route__wirelength": 63961, - "detailedroute__route__wirelength__iter:1": 64146, - "detailedroute__route__wirelength__iter:2": 63959, - "detailedroute__route__wirelength__iter:3": 63961, - "detailedroute__route__wirelength__iter:4": 63961, - "finish__clock__skew__hold": 119.318, - "finish__clock__skew__setup": 94.8464, - "finish__cpu__total": 136.67, - "finish__design__core__area": 136198, - "finish__design__die__area": 139408, - "finish__design__instance__area": 119971, - "finish__design__instance__area__macros": 119439, - "finish__design__instance__area__stdcell": 531.951, - "finish__design__instance__count": 10831, - "finish__design__instance__count__macros": 64, - "finish__design__instance__count__stdcell": 10767, - "finish__design__instance__utilization": 0.880858, - "finish__design__instance__utilization__stdcell": 0.0317415, - "finish__design__io": 4162, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.766298, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0118914, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0531012, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.660675, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.716899, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.660675, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 2262392.0, - "finish__power__internal__total": 0.00224583, - "finish__power__leakage__total": 2.62493e-07, - "finish__power__switching__total": 0.00187145, - "finish__power__total": 0.00411754, - "finish__runtime__total": "2:23.89", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 1, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.791633, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 25.4451, - "finish__timing__wns_percent_delay": 4.969168, - "finish_merge__cpu__total": 3.02, - "finish_merge__mem__peak": 576524.0, - "finish_merge__runtime__total": "0:03.37", - "floorplan__cpu__total": 2.99, - "floorplan__design__core__area": 136198, - "floorplan__design__die__area": 139408, - "floorplan__design__instance__area": 119463, - "floorplan__design__instance__area__macros": 119439, - "floorplan__design__instance__area__stdcell": 23.3717, - "floorplan__design__instance__count": 193, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 64, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 129, - "floorplan__design__instance__utilization": 0.877124, - "floorplan__design__instance__utilization__stdcell": 0.00139459, - "floorplan__design__io": 4162, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 275384.0, - "floorplan__power__internal__total": 0.000334235, - "floorplan__power__leakage__total": 9.06102e-09, - "floorplan__power__switching__total": 0, - "floorplan__power__total": 0.000334244, - "floorplan__runtime__total": "0:03.14", - "floorplan__timing__setup__tns": -510.322, - "floorplan__timing__setup__ws": -30.98, - "floorplan_io__cpu__total": 2.16, - "floorplan_io__mem__peak": 261392.0, - "floorplan_io__runtime__total": "0:02.36", - "floorplan_macro__cpu__total": 42.06, - "floorplan_macro__mem__peak": 289904.0, - "floorplan_macro__runtime__total": "0:06.08", - "floorplan_pdn__cpu__total": 91.58, - "floorplan_pdn__mem__peak": 4576680.0, - "floorplan_pdn__runtime__total": "1:34.35", - "floorplan_tap__cpu__total": 1.86, - "floorplan_tap__mem__peak": 263024.0, - "floorplan_tap__runtime__total": "0:01.99", - "floorplan_tdms__cpu__total": 0.03, - "floorplan_tdms__mem__peak": 100260.0, - "floorplan_tdms__runtime__total": "0:00.11", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 79.81, - "globalplace__design__core__area": 136198, - "globalplace__design__die__area": 139408, - "globalplace__design__instance__area": 119649, - "globalplace__design__instance__area__macros": 119439, - "globalplace__design__instance__area__stdcell": 209.471, - "globalplace__design__instance__count": 6575, - "globalplace__design__instance__count__macros": 64, - "globalplace__design__instance__count__stdcell": 6511, - "globalplace__design__instance__utilization": 0.878491, - "globalplace__design__instance__utilization__stdcell": 0.0124991, - "globalplace__design__io": 4162, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 1040380.0, - "globalplace__power__internal__total": 0.000334235, - "globalplace__power__leakage__total": 9.06102e-09, - "globalplace__power__switching__total": 0, - "globalplace__power__total": 0.000334244, - "globalplace__runtime__total": "0:12.84", - "globalplace__timing__setup__tns": -522.299, - "globalplace__timing__setup__ws": -32.0597, - "globalplace_io__cpu__total": 3.9, - "globalplace_io__mem__peak": 266104.0, - "globalplace_io__runtime__total": "0:04.08", - "globalplace_skip_io__cpu__total": 223.03, - "globalplace_skip_io__mem__peak": 303524.0, - "globalplace_skip_io__runtime__total": "0:18.39", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 114.614, - "globalroute__clock__skew__setup": 93.7467, - "globalroute__cpu__total": 20.82, - "globalroute__design__core__area": 136198, - "globalroute__design__die__area": 139408, - "globalroute__design__instance__area": 119971, - "globalroute__design__instance__area__macros": 119439, - "globalroute__design__instance__area__stdcell": 531.951, - "globalroute__design__instance__count": 10831, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 64, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 10767, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.880858, - "globalroute__design__instance__utilization__stdcell": 0.0317415, - "globalroute__design__io": 4162, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 11, - "globalroute__mem__peak": 1491060.0, - "globalroute__power__internal__total": 0.00224659, - "globalroute__power__leakage__total": 2.62493e-07, - "globalroute__power__switching__total": 0.00218973, - "globalroute__power__total": 0.00443658, - "globalroute__route__wirelength__estimated": 63522.2, - "globalroute__runtime__total": "0:17.92", - "globalroute__timing__clock__slack": 26.602, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 1, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.798365, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 26.6018, - "placeopt__cpu__total": 8.93, - "placeopt__design__core__area": 136198, - "placeopt__design__die__area": 139408, - "placeopt__design__instance__area": 119955, - "placeopt__design__instance__area__macros": 119439, - "placeopt__design__instance__area__stdcell": 516.074, - "placeopt__design__instance__count": 10790, - "placeopt__design__instance__count__macros": 64, - "placeopt__design__instance__count__stdcell": 10726, - "placeopt__design__instance__utilization": 0.880742, - "placeopt__design__instance__utilization__stdcell": 0.0307941, - "placeopt__design__io": 4162, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 565112.0, - "placeopt__power__internal__total": 0.00033438, - "placeopt__power__leakage__total": 2.46076e-07, - "placeopt__power__switching__total": 9.33265e-14, - "placeopt__power__total": 0.000334626, - "placeopt__runtime__total": "0:09.35", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.972172, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.937747, - "placeopt__timing__drv__setup_violation_count": 17, - "placeopt__timing__setup__tns": -425.139, - "placeopt__timing__setup__ws": -28.5556, - "run__flow__design": "mock-array", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "4fba262e-d115-4f8c-bda4-275d5e50f6b6", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 3.16, - "synth__design__instance__area__stdcell": 17108.10774, - "synth__design__instance__count__stdcell": 193.0, - "synth__mem__peak": 158208.0, - "synth__runtime__total": "0:03.40", - "total_time": "0:05:42.760000" -} \ No newline at end of file diff --git a/flow/designs/asap7/mock-array/power.tcl b/flow/designs/asap7/mock-array/power.tcl index a9265c0aa8..b132101bd8 100644 --- a/flow/designs/asap7/mock-array/power.tcl +++ b/flow/designs/asap7/mock-array/power.tcl @@ -1,34 +1,123 @@ +source $::env(SCRIPTS_DIR)/util.tcl + foreach libFile $::env(LIB_FILES) { - if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} { + if { [lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1 } { read_liberty $libFile } } -read_verilog results/asap7/mock-array_Element/base/6_final.v -read_verilog $::env(RESULTS_DIR)/6_final.v -read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v - -link_design MockArray +log_cmd read_verilog results/asap7/mock-array_Element/base/6_final.v +log_cmd read_verilog $::env(RESULTS_DIR)/6_final.v +log_cmd read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v +log_cmd link_design MockArray -read_sdc $::env(RESULTS_DIR)/6_final.sdc -read_spef $::env(RESULTS_DIR)/6_final.spef -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { +log_cmd read_sdc $::env(RESULTS_DIR)/6_final.sdc +log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef +puts "read_spef for ces_*_* macros" +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef } } -report_parasitic_annotation -report_power -read_power_activities -scope TOP/MockArray -vcd $::env(RESULTS_DIR)/MockArrayTestbench.vcd -report_power +# OpenSTA reports reg2reg paths inside macros, +# whereas these paths are hidden to OpenROAD that +# uses a .lib file for the macros. +log_cmd report_checks + +log_cmd report_power + +set vcd_file $::env(RESULTS_DIR)/MockArrayTestbench.vcd +log_cmd read_vcd -scope TOP/MockArray $vcd_file -# FIXME add an automated test to check that the top-level power is -# smaller than the sum of the individual elements. +set fp [open $::env(RESULTS_DIR)/activity.tcl w] +set pins [get_pins -hierarchical *] +set clock_period [expr [get_property [get_clocks] period] * 1e-12] +foreach pin $pins { + set activity [get_property $pin activity] + set activity_origin [lindex $activity 2] + if { $activity_origin != "vcd" } { + continue + } + puts $fp "set_power_activity \ + -pin \[get_pins \{[get_property $pin full_name]\}\] \ + -activity [expr [lindex $activity 0] * $clock_period] \ + -duty [lindex $activity 1]" +} +close $fp + +puts "Total number of pins: [llength [get_pins -hierarchical *]]" +set no_vcd_activity {} +foreach pin $pins { + set activity [get_property $pin activity] + set activity_origin [lindex $activity 2] + if { $activity_origin == "vcd" } { + continue + } + if { $activity_origin == "constant" } { + continue + } + if { $activity_origin == "unknown" } { + continue + } + if { [get_property $pin is_hierarchical] } { + continue + } + if { $activity_origin == "clock" } { + continue + } + set direction [get_property $pin direction] + if { $direction == "internal" } { + continue + } + lappend no_vcd_activity "[get_full_name $pin] $activity $direction" + if { [llength $no_vcd_activity] >= 10 } { + break + } +} -for {set x 0} {$x < 8} {incr x} { - for {set y 0} {$y < 8} {incr y} { - puts "Power for ces_${x}_${y}" - report_power -instances ces_${x}_${y} +if { [llength $no_vcd_activity] > 0 } { + puts "Error: Listing [llength $no_vcd_activity] pins without activity from $vcd_file:" + foreach pin $no_vcd_activity { + puts $pin } + exit 1 } + +set ces {} +for { set x 0 } { $x < 8 } { incr x } { + for { set y 0 } { $y < 8 } { incr y } { + lappend ces ces_${x}_${y} + } +} + +puts {report_power -instances [get_cells $ces]} +report_power -instances [get_cells $ces] + +proc total_power { } { + return [lindex [sta::design_power [sta::corners]] 3] +} + +set total_power_vcd [total_power] +log_cmd report_power + +source $::env(RESULTS_DIR)/activity.tcl +log_cmd report_power +set total_power_user_activity [total_power] + +puts "Total power from VCD: $total_power_vcd" +puts "Total power from user activity: $total_power_user_activity" + +if { $total_power_vcd == $total_power_user_activity } { + puts "Error: settting user power activity had no effect, expected some loss in accuracy" + exit 1 +} + +if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } { + puts "Error: Total power mismatch between VCD and user activity: \ + $total_power_vcd vs $total_power_user_activity" + exit 1 +} + +log_cmd report_parasitic_annotation +log_cmd report_activity_annotation -report_unannotated diff --git a/flow/designs/asap7/mock-array/rules-base.json b/flow/designs/asap7/mock-array/rules-base.json index 458d092077..3f0451d2cc 100644 --- a/flow/designs/asap7/mock-array/rules-base.json +++ b/flow/designs/asap7/mock-array/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 19674.33, + "value": 34554.19, "compare": "<=" }, "constraints__clocks__count": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -89.95, "compare": ">=" }, "finish__design__instance__area": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -31.9, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-array/simulate.sh b/flow/designs/asap7/mock-array/simulate.sh index 8fb1af516c..5cb8a771b1 100755 --- a/flow/designs/asap7/mock-array/simulate.sh +++ b/flow/designs/asap7/mock-array/simulate.sh @@ -13,29 +13,31 @@ mkdir -p $OBJ_DIR mkdir -p $POST_DIR # Copy Verilog files used for simulation to post dir in the objects area -cp $FLOW_HOME/results/asap7/mock-array/base/6_final.v $POST_DIR/MockArrayFinal.v -cp $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v +cp $RESULTS_DIR/6_final.v $POST_DIR/MockArrayFinal.v +cp $RESULTS_DIR/../../mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v # Run simulation and have Verilator write the output files to the objects area verilator -Wall --cc \ + --timescale 1ps/1ps \ -Wno-DECLFILENAME \ -Wno-UNUSEDSIGNAL \ -Wno-PINMISSING \ --Mdir $OBJ_DIR \ --top-module MockArray \ --trace \ + --trace-underscore \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v \ $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \ $PLATFORM_DIR/verilog/stdcell/dff.v \ $PLATFORM_DIR/verilog/stdcell/empty.v \ - $FLOW_HOME/results/asap7/mock-array/base/6_final.v \ - $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v \ + $RESULTS_DIR/6_final.v \ + $RESULTS_DIR/../../mock-array_Element/base/6_final.v \ --exe \ - $FLOW_HOME/designs/src/mock-array/simulate.cpp + $DESIGN_HOME/src/mock-array/simulate.cpp # Link the generated object files into the VMockArray executable -make -j -C $OBJ_DIR -f VMockArray.mk +make -j16 -C $OBJ_DIR -f VMockArray.mk # Run the simulation $OBJ_DIR/VMockArray diff --git a/flow/designs/asap7/mock-cpu/constraint.sdc b/flow/designs/asap7/mock-cpu/constraint.sdc index 15002f21dd..4648916e35 100644 --- a/flow/designs/asap7/mock-cpu/constraint.sdc +++ b/flow/designs/asap7/mock-cpu/constraint.sdc @@ -10,11 +10,13 @@ set clk_period 333 set clk2_period 1000 set clk1_name clk -create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name] +create_clock -name $clk1_name -period $clk_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk1_name] set_clock_uncertainty 10 [get_clocks $clk1_name] set clk2_name clk_uncore -create_clock -name $clk2_name -period $clk2_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name] +create_clock -name $clk2_name -period $clk2_period -waveform \ + [list 0 [expr $clk_period/2]] [get_ports $clk2_name] set_clock_uncertainty 10 [get_clocks $clk2_name] set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths @@ -31,7 +33,7 @@ set_false_path -to [get_ports *rst_n] set non_clk_inputs {} set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]] foreach input [all_inputs] { - if {[lsearch -exact $clock_ports $input] == -1} { + if { [lsearch -exact $clock_ports $input] == -1 } { lappend non_clk_inputs $input } } diff --git a/flow/designs/asap7/mock-cpu/io.tcl b/flow/designs/asap7/mock-cpu/io.tcl index cb59e8a8e0..ea8b842fc3 100644 --- a/flow/designs/asap7/mock-cpu/io.tcl +++ b/flow/designs/asap7/mock-cpu/io.tcl @@ -1,3 +1,10 @@ -source designs/src/mock-array/util.tcl +# bazel has root of OpenROAD-flow-scripts as working directory +foreach prefix {"" flow/} { + set f ${prefix}designs/src/mock-array/util.tcl + if { [file exists $f] } { + source $f + } +} -set_io_pin_constraint -order -group -region bottom:* -pin_names [concat [match_pins .*] [match_pins clk input 1]] +set_io_pin_constraint -order -group -region bottom:* \ + -pin_names [concat [match_pins .*] [match_pins clk input 1]] diff --git a/flow/designs/asap7/mock-cpu/metadata-base-ok.json b/flow/designs/asap7/mock-cpu/metadata-base-ok.json deleted file mode 100644 index cde9750e96..0000000000 --- a/flow/designs/asap7/mock-cpu/metadata-base-ok.json +++ /dev/null @@ -1,323 +0,0 @@ -{ - "constraints__clocks__count": 2, - "constraints__clocks__details": [ - "clk: 333.0000", - "clk_uncore: 1000.0000" - ], - "cts__clock__skew__hold": 29.0776, - "cts__clock__skew__setup": 28.6476, - "cts__cpu__total": 21.83, - "cts__design__core__area": 15844.3, - "cts__design__die__area": 16904.9, - "cts__design__instance__area": 7431.86, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 7431.86, - "cts__design__instance__count": 41937, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 26, - "cts__design__instance__count__stdcell": 41937, - "cts__design__instance__displacement__max": 3.456, - "cts__design__instance__displacement__mean": 0.004, - "cts__design__instance__displacement__total": 177.62, - "cts__design__instance__utilization": 0.469057, - "cts__design__instance__utilization__stdcell": 0.469057, - "cts__design__io": 72, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 927300.0, - "cts__power__internal__total": 0.127083, - "cts__power__leakage__total": 4.02227e-06, - "cts__power__switching__total": 0.031086, - "cts__power__total": 0.158173, - "cts__route__wirelength__estimated": 42239.1, - "cts__runtime__total": "0:22.49", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.79193, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.698412, - "cts__timing__drv__setup_violation_count": 86, - "cts__timing__setup__tns": -1544.57, - "cts__timing__setup__ws": -80.6827, - "design__io__hpwl": 6806056, - "design__violations": 0, - "detailedplace__cpu__total": 30.11, - "detailedplace__design__core__area": 15844.3, - "detailedplace__design__die__area": 16904.9, - "detailedplace__design__instance__area": 6944.79, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 6944.79, - "detailedplace__design__instance__count": 40372, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 40372, - "detailedplace__design__instance__displacement__max": 2.988, - "detailedplace__design__instance__displacement__mean": 0.265, - "detailedplace__design__instance__displacement__total": 10728.9, - "detailedplace__design__instance__utilization": 0.438316, - "detailedplace__design__instance__utilization__stdcell": 0.438316, - "detailedplace__design__io": 72, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 557088.0, - "detailedplace__power__internal__total": 0.0886011, - "detailedplace__power__leakage__total": 3.53855e-06, - "detailedplace__power__switching__total": 0.00321335, - "detailedplace__power__total": 0.0918179, - "detailedplace__route__wirelength__estimated": 33922.4, - "detailedplace__runtime__total": "0:30.44", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.718119, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.690463, - "detailedplace__timing__drv__setup_violation_count": 100, - "detailedplace__timing__setup__tns": -6279.13, - "detailedplace__timing__setup__ws": -136.709, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 7277, - "detailedroute__route__drc_errors__iter:2": 34, - "detailedroute__route__drc_errors__iter:3": 14, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 39187, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 200876, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 200876, - "detailedroute__route__wirelength": 48305, - "detailedroute__route__wirelength__iter:1": 49054, - "detailedroute__route__wirelength__iter:2": 48306, - "detailedroute__route__wirelength__iter:3": 48305, - "detailedroute__route__wirelength__iter:4": 48305, - "finish__clock__skew__hold": 37.8609, - "finish__clock__skew__setup": 37.8428, - "finish__cpu__total": 56.81, - "finish__design__core__area": 15844.3, - "finish__design__die__area": 16904.9, - "finish__design__instance__area": 7434.01, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 7434.01, - "finish__design__instance__count": 41948, - "finish__design__instance__count__class:buffer": 102, - "finish__design__instance__count__class:clock_buffer": 1193, - "finish__design__instance__count__class:clock_inverter": 344, - "finish__design__instance__count__class:fill_cell": 57805, - "finish__design__instance__count__class:inverter": 18552, - "finish__design__instance__count__class:multi_input_combinational_cell": 806, - "finish__design__instance__count__class:sequential_cell": 18680, - "finish__design__instance__count__class:tap_cell": 2102, - "finish__design__instance__count__class:tie_cell": 63, - "finish__design__instance__count__class:timing_repair_buffer": 104, - "finish__design__instance__count__class:timing_repair_inverter": 2, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 41948, - "finish__design__instance__utilization": 0.469192, - "finish__design__instance__utilization__stdcell": 0.469192, - "finish__design__io": 72, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.725047, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.044901, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.220827, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.219515, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.549173, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.219515, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 1326412.0, - "finish__power__internal__total": 0.127155, - "finish__power__leakage__total": 4.02458e-06, - "finish__power__switching__total": 0.0308056, - "finish__power__total": 0.157965, - "finish__runtime__total": "0:57.97", - "finish__timing__drv__hold_violation_count": 24, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.787359, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.690599, - "finish__timing__drv__setup_violation_count": 93, - "finish__timing__setup__tns": -1736.65, - "finish__timing__setup__ws": -82.0656, - "finish__timing__wns_percent_delay": -45.474222, - "finish_merge__cpu__total": 3.03, - "finish_merge__mem__peak": 646468.0, - "finish_merge__runtime__total": "0:03.41", - "floorplan__cpu__total": 14.64, - "floorplan__design__core__area": 15844.3, - "floorplan__design__die__area": 16904.9, - "floorplan__design__instance__area": 6356.19, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 6356.19, - "floorplan__design__instance__count": 38154, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 1, - "floorplan__design__instance__count__stdcell": 38154, - "floorplan__design__instance__utilization": 0.401167, - "floorplan__design__instance__utilization__stdcell": 0.401167, - "floorplan__design__io": 72, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1004, - "floorplan__mem__peak": 392968.0, - "floorplan__power__internal__total": 0.0840897, - "floorplan__power__leakage__total": 2.79229e-06, - "floorplan__power__switching__total": 0.00275812, - "floorplan__power__total": 0.0868506, - "floorplan__runtime__total": "0:14.91", - "floorplan__timing__setup__tns": -3628.16, - "floorplan__timing__setup__ws": -108.94, - "floorplan_io__cpu__total": 2.08, - "floorplan_io__mem__peak": 338392.0, - "floorplan_io__runtime__total": "0:02.31", - "floorplan_macro__cpu__total": 2.01, - "floorplan_macro__mem__peak": 334428.0, - "floorplan_macro__runtime__total": "0:02.25", - "floorplan_pdn__cpu__total": 2.58, - "floorplan_pdn__mem__peak": 341224.0, - "floorplan_pdn__runtime__total": "0:02.80", - "floorplan_tap__cpu__total": 2.01, - "floorplan_tap__mem__peak": 324980.0, - "floorplan_tap__runtime__total": "0:02.21", - "floorplan_tdms__cpu__total": 0.09, - "floorplan_tdms__mem__peak": 99456.0, - "floorplan_tdms__runtime__total": "0:00.17", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 518.49, - "globalplace__design__core__area": 15844.3, - "globalplace__design__die__area": 16904.9, - "globalplace__design__instance__area": 6417.49, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 6417.49, - "globalplace__design__instance__count": 40256, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 40256, - "globalplace__design__instance__utilization": 0.405036, - "globalplace__design__instance__utilization__stdcell": 0.405036, - "globalplace__design__io": 72, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 906148.0, - "globalplace__power__internal__total": 0.0840973, - "globalplace__power__leakage__total": 2.79229e-06, - "globalplace__power__switching__total": 0.00307201, - "globalplace__power__total": 0.0871721, - "globalplace__runtime__total": "1:08.65", - "globalplace__timing__setup__tns": -4484.52, - "globalplace__timing__setup__ws": -114.948, - "globalplace_io__cpu__total": 2.73, - "globalplace_io__mem__peak": 311304.0, - "globalplace_io__runtime__total": "0:02.95", - "globalplace_skip_io__cpu__total": 445.21, - "globalplace_skip_io__mem__peak": 365696.0, - "globalplace_skip_io__runtime__total": "0:17.97", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 30.3342, - "globalroute__clock__skew__setup": 31.2062, - "globalroute__cpu__total": 59.18, - "globalroute__design__core__area": 15844.3, - "globalroute__design__die__area": 16904.9, - "globalroute__design__instance__area": 7434.01, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 7434.01, - "globalroute__design__instance__count": 41948, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 5, - "globalroute__design__instance__count__stdcell": 41948, - "globalroute__design__instance__displacement__max": 2.97, - "globalroute__design__instance__displacement__mean": 0.002, - "globalroute__design__instance__displacement__total": 85.968, - "globalroute__design__instance__utilization": 0.469192, - "globalroute__design__instance__utilization__stdcell": 0.469192, - "globalroute__design__io": 72, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 13, - "globalroute__mem__peak": 1028144.0, - "globalroute__power__internal__total": 0.127113, - "globalroute__power__leakage__total": 4.02458e-06, - "globalroute__power__switching__total": 0.0328419, - "globalroute__power__total": 0.159959, - "globalroute__route__wirelength__estimated": 42388.9, - "globalroute__runtime__total": "0:26.97", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.77803, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.677649, - "globalroute__timing__drv__setup_violation_count": 95, - "globalroute__timing__setup__tns": -1835.48, - "globalroute__timing__setup__ws": -85.5672, - "placeopt__cpu__total": 17.25, - "placeopt__design__core__area": 15844.3, - "placeopt__design__die__area": 16904.9, - "placeopt__design__instance__area": 6944.79, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 6944.79, - "placeopt__design__instance__count": 40372, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 40372, - "placeopt__design__instance__utilization": 0.438316, - "placeopt__design__instance__utilization__stdcell": 0.438316, - "placeopt__design__io": 72, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 656828.0, - "placeopt__power__internal__total": 0.0885995, - "placeopt__power__leakage__total": 3.53855e-06, - "placeopt__power__switching__total": 0.00315151, - "placeopt__power__total": 0.0917545, - "placeopt__runtime__total": "0:17.73", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.71508, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.699828, - "placeopt__timing__drv__setup_violation_count": 100, - "placeopt__timing__setup__tns": -6306.39, - "placeopt__timing__setup__ws": -137.579, - "run__flow__design": "mock-cpu", - "run__flow__generate_date": "2024-10-15 14:03", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16508-gae6a38a03", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "a7ab3374e86882024ac69fa42065b029a9855e72", - "run__flow__scripts_commit": "a7ab3374e86882024ac69fa42065b029a9855e72", - "run__flow__uuid": "0e9467d7-f832-44b2-b5c0-95605c966586", - "run__flow__variant": "base", - "synth__cpu__total": 8.74, - "synth__design__instance__area__stdcell": 6352.3602, - "synth__design__instance__count__stdcell": 38142.0, - "synth__mem__peak": 208840.0, - "synth__runtime__total": "0:09.04", - "total_time": "0:04:42.270000" -} \ No newline at end of file diff --git a/flow/designs/asap7/mock-cpu/rules-base.json b/flow/designs/asap7/mock-cpu/rules-base.json index fd3e5ff074..4cd178023b 100644 --- a/flow/designs/asap7/mock-cpu/rules-base.json +++ b/flow/designs/asap7/mock-cpu/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7978, + "value": 7389, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 55551, + "value": 52446, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 8127, + "value": 7638, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 109, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -64.56, + "value": -64.53, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk index a029c68794..3c1a32d84c 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk @@ -11,7 +11,9 @@ export PLACE_DENSITY = 0.80 # fakeram7 doesn't block off M5, so limit to M4 here. # However, PDN will use M5, so it is still added to blockages. export MAX_ROUTING_LAYER = M4 +export MIN_CLK_ROUTING_LAYER = M2 -export PLACE_PINS_ARGS = -exclude left:* -exclude bottom:* -exclude top:* -min_distance 6 -min_distance_in_tracks +export PLACE_PINS_ARGS = -min_distance 6 -min_distance_in_tracks +export IO_CONSTRAINTS = $(DESIGN_HOME)/asap7/riscv32i-mock-sram/fakeram7_256x32/io.tcl -export PDN_TCL = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/io.tcl b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/io.tcl new file mode 100644 index 0000000000..d783a5cb83 --- /dev/null +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:* -region bottom:* -region top:* diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/metadata-base-ok.json b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/metadata-base-ok.json deleted file mode 100644 index f681799222..0000000000 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/metadata-base-ok.json +++ /dev/null @@ -1,381 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1660.0000" - ], - "cts__clock__skew__hold": 7.27443, - "cts__clock__skew__hold__post_repair": 7.25267, - "cts__clock__skew__hold__pre_repair": 7.25267, - "cts__clock__skew__setup": 2.56638, - "cts__clock__skew__setup__post_repair": 2.63183, - "cts__clock__skew__setup__pre_repair": 2.63183, - "cts__cpu__total": 2.68, - "cts__design__core__area": 112.674, - "cts__design__core__area__post_repair": 112.674, - "cts__design__core__area__pre_repair": 112.674, - "cts__design__die__area": 187.369, - "cts__design__die__area__post_repair": 187.369, - "cts__design__die__area__pre_repair": 187.369, - "cts__design__instance__area": 72.6813, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 71.5732, - "cts__design__instance__area__pre_repair": 71.5732, - "cts__design__instance__area__stdcell": 72.6813, - "cts__design__instance__area__stdcell__post_repair": 71.5732, - "cts__design__instance__area__stdcell__pre_repair": 71.5732, - "cts__design__instance__count": 712, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 706, - "cts__design__instance__count__pre_repair": 706, - "cts__design__instance__count__setup_buffer": 2, - "cts__design__instance__count__stdcell": 712, - "cts__design__instance__count__stdcell__post_repair": 706, - "cts__design__instance__count__stdcell__pre_repair": 706, - "cts__design__instance__displacement__max": 3.726, - "cts__design__instance__displacement__mean": 0.105, - "cts__design__instance__displacement__total": 75.279, - "cts__design__instance__utilization": 0.645057, - "cts__design__instance__utilization__post_repair": 0.635223, - "cts__design__instance__utilization__pre_repair": 0.635223, - "cts__design__instance__utilization__stdcell": 0.645057, - "cts__design__instance__utilization__stdcell__post_repair": 0.635223, - "cts__design__instance__utilization__stdcell__pre_repair": 0.635223, - "cts__design__io": 75, - "cts__design__io__post_repair": 75, - "cts__design__io__pre_repair": 75, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 204728.0, - "cts__power__internal__total": 0.000243024, - "cts__power__internal__total__post_repair": 0.000243582, - "cts__power__internal__total__pre_repair": 0.000243582, - "cts__power__leakage__total": 4.85077e-08, - "cts__power__leakage__total__post_repair": 4.72173e-08, - "cts__power__leakage__total__pre_repair": 4.72173e-08, - "cts__power__switching__total": 7.47865e-05, - "cts__power__switching__total__post_repair": 7.51709e-05, - "cts__power__switching__total__pre_repair": 7.51709e-05, - "cts__power__total": 0.000317859, - "cts__power__total__post_repair": 0.0003188, - "cts__power__total__pre_repair": 0.0003188, - "cts__route__wirelength__estimated": 1361.1, - "cts__runtime__total": "0:02.75", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.937658, - "cts__timing__drv__max_cap_limit__post_repair": 0.331523, - "cts__timing__drv__max_cap_limit__pre_repair": 0.331523, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.689755, - "cts__timing__drv__max_slew_limit__post_repair": 0.284445, - "cts__timing__drv__max_slew_limit__pre_repair": 0.284445, - "cts__timing__drv__setup_violation_count": 64, - "cts__timing__drv__setup_violation_count__post_repair": 96, - "cts__timing__drv__setup_violation_count__pre_repair": 96, - "cts__timing__setup__tns": -338.146, - "cts__timing__setup__tns__post_repair": -3271.72, - "cts__timing__setup__tns__pre_repair": -3271.72, - "cts__timing__setup__ws": -7.24483, - "cts__timing__setup__ws__post_repair": -66.223, - "cts__timing__setup__ws__pre_repair": -66.223, - "design__io__hpwl": 622235, - "detailedplace__cpu__total": 0.95, - "detailedplace__design__core__area": 112.674, - "detailedplace__design__die__area": 187.369, - "detailedplace__design__instance__area": 68.8322, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 68.8322, - "detailedplace__design__instance__count": 697, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 697, - "detailedplace__design__instance__displacement__max": 3.516, - "detailedplace__design__instance__displacement__mean": 0.482, - "detailedplace__design__instance__displacement__total": 336.175, - "detailedplace__design__instance__utilization": 0.610895, - "detailedplace__design__instance__utilization__stdcell": 0.610895, - "detailedplace__design__io": 75, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 190564.0, - "detailedplace__power__internal__total": 0.000199361, - "detailedplace__power__leakage__total": 4.44558e-08, - "detailedplace__power__switching__total": 4.48736e-05, - "detailedplace__power__total": 0.00024428, - "detailedplace__route__wirelength__estimated": 1133.69, - "detailedplace__runtime__total": "0:01.01", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.331523, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.284445, - "detailedplace__timing__drv__setup_violation_count": 97, - "detailedplace__timing__setup__tns": -7533.44, - "detailedplace__timing__setup__ws": -113.45, - "detailedroute__cpu__total": 32.33, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 1333704.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 175, - "detailedroute__route__drc_errors__iter:2": 2, - "detailedroute__route__drc_errors__iter:3": 2, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 531, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3822, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3822, - "detailedroute__route__wirelength": 1575, - "detailedroute__route__wirelength__iter:1": 1590, - "detailedroute__route__wirelength__iter:2": 1588, - "detailedroute__route__wirelength__iter:3": 1576, - "detailedroute__route__wirelength__iter:4": 1575, - "detailedroute__runtime__total": "0:08.72", - "fillcell__cpu__total": 0.83, - "fillcell__mem__peak": 188084.0, - "fillcell__runtime__total": "0:00.88", - "finish__clock__skew__hold": 7.9035, - "finish__clock__skew__setup": 3.7844, - "finish__cpu__total": 1.46, - "finish__design__core__area": 112.674, - "finish__design__die__area": 187.369, - "finish__design__instance__area": 72.6813, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 72.6813, - "finish__design__instance__count": 712, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 712, - "finish__design__instance__utilization": 0.645057, - "finish__design__instance__utilization__stdcell": 0.645057, - "finish__design__io": 75, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.769756, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000243394, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00107095, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00100154, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.768929, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00100154, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 11, - "finish__mem__peak": 341060.0, - "finish__power__internal__total": 0.000243488, - "finish__power__leakage__total": 4.84935e-08, - "finish__power__switching__total": 7.88543e-05, - "finish__power__total": 0.000322391, - "finish__runtime__total": "0:01.59", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.929257, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.578371, - "finish__timing__drv__setup_violation_count": 96, - "finish__timing__setup__tns": -1635.17, - "finish__timing__setup__ws": -24.6497, - "finish__timing__wns_percent_delay": -17.264778, - "finish_merge__cpu__total": 0.72, - "finish_merge__mem__peak": 373888.0, - "finish_merge__runtime__total": "0:00.83", - "floorplan__cpu__total": 0.8, - "floorplan__design__core__area": 112.674, - "floorplan__design__die__area": 187.369, - "floorplan__design__instance__area": 54.7042, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 54.7042, - "floorplan__design__instance__count": 399, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 399, - "floorplan__design__instance__utilization": 0.485507, - "floorplan__design__instance__utilization__stdcell": 0.485507, - "floorplan__design__io": 75, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 11, - "floorplan__mem__peak": 190164.0, - "floorplan__power__internal__total": 0.000179398, - "floorplan__power__leakage__total": 3.64297e-08, - "floorplan__power__switching__total": 3.50326e-05, - "floorplan__power__total": 0.000214467, - "floorplan__runtime__total": "0:00.87", - "floorplan__timing__setup__tns": -13598.6, - "floorplan__timing__setup__ws": -173.088, - "floorplan_io__cpu__total": 0.74, - "floorplan_io__mem__peak": 187244.0, - "floorplan_io__runtime__total": "0:00.81", - "floorplan_macro__cpu__total": 0.76, - "floorplan_macro__mem__peak": 187516.0, - "floorplan_macro__runtime__total": "0:00.85", - "floorplan_pdn__cpu__total": 0.78, - "floorplan_pdn__mem__peak": 189084.0, - "floorplan_pdn__runtime__total": "0:00.83", - "floorplan_tap__cpu__total": 0.77, - "floorplan_tap__mem__peak": 186208.0, - "floorplan_tap__runtime__total": "0:00.83", - "floorplan_tdms__cpu__total": 0.76, - "floorplan_tdms__mem__peak": 186720.0, - "floorplan_tdms__runtime__total": "0:00.81", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 1.24, - "globalplace__design__core__area": 112.674, - "globalplace__design__die__area": 187.369, - "globalplace__design__instance__area": 61.236, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 61.236, - "globalplace__design__instance__count": 623, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 623, - "globalplace__design__instance__utilization": 0.543478, - "globalplace__design__instance__utilization__stdcell": 0.543478, - "globalplace__design__io": 75, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 215960.0, - "globalplace__power__internal__total": 0.000180129, - "globalplace__power__leakage__total": 3.64297e-08, - "globalplace__power__switching__total": 4.1065e-05, - "globalplace__power__total": 0.00022123, - "globalplace__runtime__total": "0:01.30", - "globalplace__timing__setup__tns": -16014.2, - "globalplace__timing__setup__ws": -207.219, - "globalplace_io__cpu__total": 0.75, - "globalplace_io__mem__peak": 187316.0, - "globalplace_io__runtime__total": "0:00.81", - "globalplace_skip_io__cpu__total": 0.77, - "globalplace_skip_io__mem__peak": 185764.0, - "globalplace_skip_io__runtime__total": "0:00.82", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 7.82121, - "globalroute__clock__skew__setup": 3.47525, - "globalroute__cpu__total": 1.34, - "globalroute__design__core__area": 112.674, - "globalroute__design__die__area": 187.369, - "globalroute__design__instance__area": 72.6813, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 72.6813, - "globalroute__design__instance__count": 712, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 712, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.645057, - "globalroute__design__instance__utilization__stdcell": 0.645057, - "globalroute__design__io": 75, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 10, - "globalroute__mem__peak": 250452.0, - "globalroute__power__internal__total": 0.000243333, - "globalroute__power__leakage__total": 4.84935e-08, - "globalroute__power__switching__total": 8.26631e-05, - "globalroute__power__total": 0.000326045, - "globalroute__route__wirelength__estimated": 1361.1, - "globalroute__runtime__total": "0:01.42", - "globalroute__timing__clock__slack": -21.502, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.918755, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.584319, - "globalroute__timing__drv__setup_violation_count": 96, - "globalroute__timing__setup__tns": -1508.01, - "globalroute__timing__setup__ws": -21.5015, - "placeopt__cpu__total": 0.94, - "placeopt__design__core__area": 112.674, - "placeopt__design__core__area__pre_opt": 112.674, - "placeopt__design__die__area": 187.369, - "placeopt__design__die__area__pre_opt": 187.369, - "placeopt__design__instance__area": 68.8322, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 61.236, - "placeopt__design__instance__area__stdcell": 68.8322, - "placeopt__design__instance__area__stdcell__pre_opt": 61.236, - "placeopt__design__instance__count": 697, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 623, - "placeopt__design__instance__count__stdcell": 697, - "placeopt__design__instance__count__stdcell__pre_opt": 623, - "placeopt__design__instance__utilization": 0.610895, - "placeopt__design__instance__utilization__pre_opt": 0.543478, - "placeopt__design__instance__utilization__stdcell": 0.610895, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.543478, - "placeopt__design__io": 75, - "placeopt__design__io__pre_opt": 75, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 196756.0, - "placeopt__power__internal__total": 0.000192748, - "placeopt__power__internal__total__pre_opt": 0.000180129, - "placeopt__power__leakage__total": 4.60162e-08, - "placeopt__power__leakage__total__pre_opt": 3.64297e-08, - "placeopt__power__switching__total": 4.30114e-05, - "placeopt__power__switching__total__pre_opt": 4.1065e-05, - "placeopt__power__total": 0.000235806, - "placeopt__power__total__pre_opt": 0.00022123, - "placeopt__runtime__total": "0:01.03", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.341695, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.296367, - "placeopt__timing__drv__setup_violation_count": 97, - "placeopt__timing__setup__tns": -7336.59, - "placeopt__timing__setup__tns__pre_opt": -16014.2, - "placeopt__timing__setup__ws": -110.074, - "placeopt__timing__setup__ws__pre_opt": -207.219, - "run__flow__design": "riscv32i-mock-sram_fakeram7_256x32", - "run__flow__generate_date": "2024-04-30 19:28", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-13503-g365f097d1", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "85e2265eb38485db96beaf84260f6e13ad48f05c", - "run__flow__scripts_commit": "85e2265eb38485db96beaf84260f6e13ad48f05c", - "run__flow__uuid": "2e12ef50-6bc0-46a2-9bb6-4e033fd829ac", - "run__flow__variant": "base", - "synth__cpu__total": 1.56, - "synth__design__instance__area__stdcell": 57.56184, - "synth__design__instance__count__stdcell": 425.0, - "synth__mem__peak": 137280.0, - "synth__runtime__total": "0:01.73", - "total_time": "0:00:27.890000" -} \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i-mock-sram/io.tcl b/flow/designs/asap7/riscv32i-mock-sram/io.tcl new file mode 100644 index 0000000000..aee09d1e74 --- /dev/null +++ b/flow/designs/asap7/riscv32i-mock-sram/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* diff --git a/flow/designs/asap7/riscv32i-mock-sram/metadata-base-ok.json b/flow/designs/asap7/riscv32i-mock-sram/metadata-base-ok.json deleted file mode 100644 index 68be089b82..0000000000 --- a/flow/designs/asap7/riscv32i-mock-sram/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1660.0000" - ], - "cts__clock__skew__hold": 60.8587, - "cts__clock__skew__setup": 60.8587, - "cts__cpu__total": 16.99, - "cts__design__core__area": 5569.92, - "cts__design__die__area": 7200, - "cts__design__instance__area": 2025.94, - "cts__design__instance__area__macros": 734.923, - "cts__design__instance__area__stdcell": 1291.02, - "cts__design__instance__count": 10878, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 4, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 10874, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.363728, - "cts__design__instance__utilization__stdcell": 0.267014, - "cts__design__io": 135, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 10, - "cts__mem__peak": 248728.0, - "cts__power__internal__total": 0.00149182, - "cts__power__leakage__total": 1.4483e-06, - "cts__power__switching__total": 0.000378719, - "cts__power__total": 0.00187199, - "cts__route__wirelength__estimated": 46737.6, - "cts__runtime__total": "0:17.09", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.157806, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.015927, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 51.6137, - "design__io__hpwl": 7704179, - "detailedplace__cpu__total": 8.61, - "detailedplace__design__core__area": 5569.92, - "detailedplace__design__die__area": 7200, - "detailedplace__design__instance__area": 1992.45, - "detailedplace__design__instance__area__macros": 734.923, - "detailedplace__design__instance__area__stdcell": 1257.53, - "detailedplace__design__instance__count": 10766, - "detailedplace__design__instance__count__macros": 4, - "detailedplace__design__instance__count__stdcell": 10762, - "detailedplace__design__instance__displacement__max": 9.745, - "detailedplace__design__instance__displacement__mean": 0.292, - "detailedplace__design__instance__displacement__total": 3149.61, - "detailedplace__design__instance__utilization": 0.357715, - "detailedplace__design__instance__utilization__stdcell": 0.260088, - "detailedplace__design__io": 135, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 236384.0, - "detailedplace__power__internal__total": 0.000972956, - "detailedplace__power__leakage__total": 1.41576e-06, - "detailedplace__power__switching__total": 1.82849e-06, - "detailedplace__power__total": 0.0009762, - "detailedplace__route__wirelength__estimated": 47073.2, - "detailedplace__runtime__total": "0:08.70", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.157428, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.015268, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 40.3161, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 1942.4, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 5026356.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 5297, - "detailedroute__route__drc_errors__iter:2": 190, - "detailedroute__route__drc_errors__iter:3": 73, - "detailedroute__route__drc_errors__iter:4": 4, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 10272, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 107573, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 107573, - "detailedroute__route__wirelength": 66695, - "detailedroute__route__wirelength__iter:1": 67009, - "detailedroute__route__wirelength__iter:2": 66739, - "detailedroute__route__wirelength__iter:3": 66693, - "detailedroute__route__wirelength__iter:4": 66695, - "detailedroute__route__wirelength__iter:5": 66695, - "detailedroute__runtime__total": "1:51.72", - "fillcell__cpu__total": 1.53, - "fillcell__mem__peak": 210456.0, - "fillcell__runtime__total": "0:01.60", - "finish__clock__skew__hold": 68.7863, - "finish__clock__skew__setup": 68.7863, - "finish__cpu__total": 35.59, - "finish__design__core__area": 5569.92, - "finish__design__die__area": 7200, - "finish__design__instance__area": 2027.79, - "finish__design__instance__area__macros": 734.923, - "finish__design__instance__area__stdcell": 1292.87, - "finish__design__instance__count": 10888, - "finish__design__instance__count__macros": 4, - "finish__design__instance__count__stdcell": 10884, - "finish__design__instance__utilization": 0.364061, - "finish__design__instance__utilization__stdcell": 0.267397, - "finish__design__io": 135, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.769402, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000593543, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00223595, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00212846, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.767764, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00212846, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 1430644.0, - "finish__power__internal__total": 0.00149176, - "finish__power__leakage__total": 1.45207e-06, - "finish__power__switching__total": 0.000396537, - "finish__power__total": 0.00188975, - "finish__runtime__total": "0:35.80", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.106589, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 219, - "finish__timing__drv__max_slew_limit": -0.148545, - "finish__timing__drv__setup_violation_count": 999, - "finish__timing__setup__tns": -99247.2, - "finish__timing__setup__ws": -164.328, - "finish__timing__wns_percent_delay": -8.573798, - "finish_merge__cpu__total": 2.78, - "finish_merge__mem__peak": 356836.0, - "finish_merge__runtime__total": "0:02.91", - "floorplan__cpu__total": 3.76, - "floorplan__design__core__area": 5569.92, - "floorplan__design__die__area": 7200, - "floorplan__design__instance__area": 1875.12, - "floorplan__design__instance__area__macros": 734.923, - "floorplan__design__instance__area__stdcell": 1140.2, - "floorplan__design__instance__count": 9652, - "floorplan__design__instance__count__macros": 4, - "floorplan__design__instance__count__stdcell": 9648, - "floorplan__design__instance__utilization": 0.336651, - "floorplan__design__instance__utilization__stdcell": 0.235822, - "floorplan__design__io": 135, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 11, - "floorplan__mem__peak": 208080.0, - "floorplan__power__internal__total": 0.00097149, - "floorplan__power__leakage__total": 1.22396e-06, - "floorplan__power__switching__total": 6.65454e-07, - "floorplan__power__total": 0.00097338, - "floorplan__runtime__total": "0:03.82", - "floorplan__timing__setup__tns": -1317260.0, - "floorplan__timing__setup__ws": -1266.07, - "floorplan_io__cpu__total": 1.4, - "floorplan_io__mem__peak": 180416.0, - "floorplan_io__runtime__total": "0:01.46", - "floorplan_macro__cpu__total": 110.38, - "floorplan_macro__mem__peak": 258692.0, - "floorplan_macro__runtime__total": "0:38.85", - "floorplan_pdn__cpu__total": 1.89, - "floorplan_pdn__mem__peak": 210776.0, - "floorplan_pdn__runtime__total": "0:01.96", - "floorplan_tap__cpu__total": 1.42, - "floorplan_tap__mem__peak": 174496.0, - "floorplan_tap__runtime__total": "0:01.47", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 44.78, - "globalplace__design__core__area": 5569.92, - "globalplace__design__die__area": 7200, - "globalplace__design__instance__area": 1899.12, - "globalplace__design__instance__area__macros": 734.923, - "globalplace__design__instance__area__stdcell": 1164.2, - "globalplace__design__instance__count": 10475, - "globalplace__design__instance__count__macros": 4, - "globalplace__design__instance__count__stdcell": 10471, - "globalplace__design__instance__utilization": 0.34096, - "globalplace__design__instance__utilization__stdcell": 0.240786, - "globalplace__design__io": 135, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 304064.0, - "globalplace__power__internal__total": 0.000971491, - "globalplace__power__leakage__total": 1.22396e-06, - "globalplace__power__switching__total": 8.04023e-07, - "globalplace__power__total": 0.000973519, - "globalplace__runtime__total": "0:40.37", - "globalplace__timing__setup__tns": -2687890.0, - "globalplace__timing__setup__ws": -2470.97, - "globalplace_io__cpu__total": 1.41, - "globalplace_io__mem__peak": 185200.0, - "globalplace_io__runtime__total": "0:01.47", - "globalplace_skip_io__cpu__total": 1.39, - "globalplace_skip_io__mem__peak": 177544.0, - "globalplace_skip_io__runtime__total": "0:01.46", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 62.5808, - "globalroute__clock__skew__setup": 62.5808, - "globalroute__cpu__total": 93.12, - "globalroute__design__core__area": 5569.92, - "globalroute__design__die__area": 7200, - "globalroute__design__instance__area": 2027.79, - "globalroute__design__instance__area__macros": 734.923, - "globalroute__design__instance__area__stdcell": 1292.87, - "globalroute__design__instance__count": 10888, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 4, - "globalroute__design__instance__count__setup_buffer": 2, - "globalroute__design__instance__count__stdcell": 10884, - "globalroute__design__instance__displacement__max": 8.316, - "globalroute__design__instance__displacement__mean": 0.001, - "globalroute__design__instance__displacement__total": 12.69, - "globalroute__design__instance__utilization": 0.364061, - "globalroute__design__instance__utilization__stdcell": 0.267397, - "globalroute__design__io": 135, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 10, - "globalroute__mem__peak": 471980.0, - "globalroute__power__internal__total": 0.00149143, - "globalroute__power__leakage__total": 1.45207e-06, - "globalroute__power__switching__total": 0.000395836, - "globalroute__power__total": 0.00188872, - "globalroute__route__wirelength__estimated": 47202.3, - "globalroute__runtime__total": "0:23.21", - "globalroute__timing__clock__slack": 16.798, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.139231, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0444021, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 16.7985, - "placeopt__cpu__total": 8.82, - "placeopt__design__core__area": 5569.92, - "placeopt__design__die__area": 7200, - "placeopt__design__instance__area": 1992.45, - "placeopt__design__instance__area__macros": 734.923, - "placeopt__design__instance__area__stdcell": 1257.53, - "placeopt__design__instance__count": 10766, - "placeopt__design__instance__count__macros": 4, - "placeopt__design__instance__count__stdcell": 10762, - "placeopt__design__instance__utilization": 0.357715, - "placeopt__design__instance__utilization__stdcell": 0.260088, - "placeopt__design__io": 135, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 227768.0, - "placeopt__power__internal__total": 0.000972953, - "placeopt__power__leakage__total": 1.41576e-06, - "placeopt__power__switching__total": 1.76665e-06, - "placeopt__power__total": 0.000976136, - "placeopt__runtime__total": "0:08.90", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.1568, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0269332, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 33.0489, - "run__flow__design": "riscv32i-mock-sram", - "run__flow__generate_date": "2024-06-20 21:35", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-14264-g08c19394f", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__scripts_commit": "6f711638d045b4c662d1d39712c6018e7127f3c9", - "run__flow__uuid": "6f2d7ee1-4f77-421c-a014-9fdeda35fdb9", - "run__flow__variant": "base", - "synth__cpu__total": 22.98, - "synth__design__instance__area__stdcell": 1496.16844, - "synth__design__instance__count__stdcell": 10711.0, - "synth__mem__peak": 169560.0, - "synth__runtime__total": "0:23.20", - "total_time": "0:05:23.990000" -} \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json index 224c8c1c3c..e38e846845 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/rules-base.json +++ b/flow/designs/asap7/riscv32i-mock-sram/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1707.88, + "value": 1659.48, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2269, + "value": 2395, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -27,8 +27,12 @@ "value": 1064, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 76699, + "value": 95161, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -39,16 +43,20 @@ "value": 0, "compare": "<=" }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": -247.32, + "value": -79.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 2307, + "value": 2464, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1049, + "value": 533, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -56,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.28, + "value": -11.73, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk index d129acb64e..60313250f5 100644 --- a/flow/designs/asap7/riscv32i/config.mk +++ b/flow/designs/asap7/riscv32i/config.mk @@ -4,12 +4,7 @@ export PLATFORM = asap7 export SYNTH_HIERARCHICAL ?= 1 -export RTLMP_MIN_INST = 1000 -export RTLMP_MAX_INST = 3500 -export RTLMP_MIN_MACRO = 1 -export RTLMP_MAX_MACRO = 5 - -export MAX_UNGROUP_SIZE ?= 1000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v)) export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i/constraint.sdc @@ -24,8 +19,10 @@ export CORE_AREA = 5 5 75 85 export PLACE_DENSITY_LB_ADDON = 0.10 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -export MACRO_PLACE_HALO = 1 1 -export MACRO_PLACE_CHANNEL = 6 6 -# +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl +export MACRO_PLACE_HALO = 2 2 + export TNS_END_PERCENT = 100 + +export CTS_CLUSTER_SIZE = 10 +export CTS_CLUSTER_DIAMETER = 50 diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc index 74dca22a8f..9868986799 100644 --- a/flow/designs/asap7/riscv32i/constraint.sdc +++ b/flow/designs/asap7/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ current_design riscv_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 1260 set clk_io_pct 0.125 @@ -9,6 +9,6 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/riscv32i/io.tcl b/flow/designs/asap7/riscv32i/io.tcl new file mode 100644 index 0000000000..aee09d1e74 --- /dev/null +++ b/flow/designs/asap7/riscv32i/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* diff --git a/flow/designs/asap7/riscv32i/metadata-base-ok.json b/flow/designs/asap7/riscv32i/metadata-base-ok.json deleted file mode 100644 index dd1ce09cdd..0000000000 --- a/flow/designs/asap7/riscv32i/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1260.0000" - ], - "cts__clock__skew__hold": 47.4088, - "cts__clock__skew__setup": 44.1048, - "cts__cpu__total": 37.67, - "cts__design__core__area": 5569.92, - "cts__design__die__area": 7200, - "cts__design__instance__area": 2847.86, - "cts__design__instance__area__macros": 1404.48, - "cts__design__instance__area__stdcell": 1443.38, - "cts__design__instance__count": 11762, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 4, - "cts__design__instance__count__setup_buffer": 11, - "cts__design__instance__count__stdcell": 11758, - "cts__design__instance__displacement__max": 0.738, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 5.299, - "cts__design__instance__utilization": 0.511292, - "cts__design__instance__utilization__stdcell": 0.346512, - "cts__design__io": 135, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 10, - "cts__mem__peak": 637504.0, - "cts__power__internal__total": 0.0129277, - "cts__power__leakage__total": 0.000516871, - "cts__power__switching__total": 0.002222, - "cts__power__total": 0.0156666, - "cts__route__wirelength__estimated": 82571.3, - "cts__runtime__total": "0:38.29", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.354017, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.519607, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": -0.010103, - "cts__timing__setup__ws": 1.86196, - "design__io__hpwl": 10872826, - "design__violations": 0, - "detailedplace__cpu__total": 20.0, - "detailedplace__design__core__area": 5569.92, - "detailedplace__design__die__area": 7200, - "detailedplace__design__instance__area": 2809.63, - "detailedplace__design__instance__area__macros": 1404.48, - "detailedplace__design__instance__area__stdcell": 1405.15, - "detailedplace__design__instance__count": 11637, - "detailedplace__design__instance__count__macros": 4, - "detailedplace__design__instance__count__stdcell": 11633, - "detailedplace__design__instance__displacement__max": 10.531, - "detailedplace__design__instance__displacement__mean": 0.198, - "detailedplace__design__instance__displacement__total": 2315.41, - "detailedplace__design__instance__utilization": 0.504428, - "detailedplace__design__instance__utilization__stdcell": 0.337334, - "detailedplace__design__io": 135, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 282448.0, - "detailedplace__power__internal__total": 0.0121429, - "detailedplace__power__leakage__total": 0.000516833, - "detailedplace__power__switching__total": 0.0016506, - "detailedplace__power__total": 0.0143103, - "detailedplace__route__wirelength__estimated": 82460.3, - "detailedplace__runtime__total": "0:20.19", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.353007, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.524139, - "detailedplace__timing__drv__setup_violation_count": 256, - "detailedplace__timing__setup__tns": -3218.78, - "detailedplace__timing__setup__ws": -26.5176, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2644, - "detailedroute__route__drc_errors__iter:2": 211, - "detailedroute__route__drc_errors__iter:3": 134, - "detailedroute__route__drc_errors__iter:4": 7, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 11174, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 124675, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 124675, - "detailedroute__route__wirelength": 99200, - "detailedroute__route__wirelength__iter:1": 99410, - "detailedroute__route__wirelength__iter:2": 99215, - "detailedroute__route__wirelength__iter:3": 99197, - "detailedroute__route__wirelength__iter:4": 99201, - "detailedroute__route__wirelength__iter:5": 99200, - "finish__clock__skew__hold": 51.881, - "finish__clock__skew__setup": 49.6891, - "finish__cpu__total": 59.13, - "finish__design__core__area": 5569.92, - "finish__design__die__area": 7200, - "finish__design__instance__area": 2848.32, - "finish__design__instance__area__macros": 1404.48, - "finish__design__instance__area__stdcell": 1443.84, - "finish__design__instance__count": 11767, - "finish__design__instance__count__macros": 4, - "finish__design__instance__count__stdcell": 11763, - "finish__design__instance__utilization": 0.511375, - "finish__design__instance__utilization__stdcell": 0.346624, - "finish__design__io": 135, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.764078, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0059394, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0170905, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0170404, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.75291, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0170404, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 11, - "finish__mem__peak": 584984.0, - "finish__power__internal__total": 0.0129325, - "finish__power__leakage__total": 0.000516871, - "finish__power__switching__total": 0.00241958, - "finish__power__total": 0.0158689, - "finish__runtime__total": "0:59.65", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.224805, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.483512, - "finish__timing__drv__setup_violation_count": 728, - "finish__timing__setup__tns": -20687.7, - "finish__timing__setup__ws": -67.4591, - "finish__timing__wns_percent_delay": -4.757921, - "finish_merge__cpu__total": 3.02, - "finish_merge__mem__peak": 494392.0, - "finish_merge__runtime__total": "0:03.40", - "floorplan__cpu__total": 12.51, - "floorplan__design__core__area": 5569.92, - "floorplan__design__die__area": 7200, - "floorplan__design__instance__area": 2618.89, - "floorplan__design__instance__area__macros": 1404.48, - "floorplan__design__instance__area__stdcell": 1214.41, - "floorplan__design__instance__count": 10636, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 4, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 10632, - "floorplan__design__instance__utilization": 0.470184, - "floorplan__design__instance__utilization__stdcell": 0.291544, - "floorplan__design__io": 135, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 255072.0, - "floorplan__power__internal__total": 0.0118529, - "floorplan__power__leakage__total": 0.000516572, - "floorplan__power__switching__total": 0.00103501, - "floorplan__power__total": 0.0134045, - "floorplan__runtime__total": "0:12.67", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 137.345, - "floorplan_io__cpu__total": 1.85, - "floorplan_io__mem__peak": 226560.0, - "floorplan_io__runtime__total": "0:01.99", - "floorplan_macro__cpu__total": 96.24, - "floorplan_macro__mem__peak": 311888.0, - "floorplan_macro__runtime__total": "0:39.41", - "floorplan_pdn__cpu__total": 2.16, - "floorplan_pdn__mem__peak": 235520.0, - "floorplan_pdn__runtime__total": "0:02.31", - "floorplan_tap__cpu__total": 1.89, - "floorplan_tap__mem__peak": 220000.0, - "floorplan_tap__runtime__total": "0:02.04", - "floorplan_tdms__cpu__total": 0.1, - "floorplan_tdms__mem__peak": 99764.0, - "floorplan_tdms__runtime__total": "0:00.15", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 447.61, - "globalplace__design__core__area": 5569.92, - "globalplace__design__die__area": 7200, - "globalplace__design__instance__area": 2642.31, - "globalplace__design__instance__area__macros": 1404.48, - "globalplace__design__instance__area__stdcell": 1237.83, - "globalplace__design__instance__count": 11439, - "globalplace__design__instance__count__macros": 4, - "globalplace__design__instance__count__stdcell": 11435, - "globalplace__design__instance__utilization": 0.474388, - "globalplace__design__instance__utilization__stdcell": 0.297166, - "globalplace__design__io": 135, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 635024.0, - "globalplace__power__internal__total": 0.0118616, - "globalplace__power__leakage__total": 0.000516572, - "globalplace__power__switching__total": 0.0015824, - "globalplace__power__total": 0.0139606, - "globalplace__runtime__total": "1:14.86", - "globalplace__timing__setup__tns": -87184.7, - "globalplace__timing__setup__ws": -150.939, - "globalplace_io__cpu__total": 1.86, - "globalplace_io__mem__peak": 229368.0, - "globalplace_io__runtime__total": "0:02.04", - "globalplace_skip_io__cpu__total": 712.5, - "globalplace_skip_io__mem__peak": 245768.0, - "globalplace_skip_io__runtime__total": "0:25.55", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 51.648, - "globalroute__clock__skew__setup": 49.6781, - "globalroute__cpu__total": 68.1, - "globalroute__design__core__area": 5569.92, - "globalroute__design__die__area": 7200, - "globalroute__design__instance__area": 2848.32, - "globalroute__design__instance__area__macros": 1404.48, - "globalroute__design__instance__area__stdcell": 1443.84, - "globalroute__design__instance__count": 11767, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 4, - "globalroute__design__instance__count__setup_buffer": 5, - "globalroute__design__instance__count__stdcell": 11763, - "globalroute__design__instance__displacement__max": 0.486, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 1.134, - "globalroute__design__instance__utilization": 0.511375, - "globalroute__design__instance__utilization__stdcell": 0.346624, - "globalroute__design__io": 135, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 11, - "globalroute__mem__peak": 731448.0, - "globalroute__power__internal__total": 0.012929, - "globalroute__power__leakage__total": 0.000516871, - "globalroute__power__switching__total": 0.00231243, - "globalroute__power__total": 0.0157583, - "globalroute__route__wirelength__estimated": 82575.1, - "globalroute__runtime__total": "0:44.23", - "globalroute__timing__clock__slack": 12.137, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.352894, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.535672, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 12.1368, - "placeopt__cpu__total": 20.84, - "placeopt__design__core__area": 5569.92, - "placeopt__design__die__area": 7200, - "placeopt__design__instance__area": 2809.63, - "placeopt__design__instance__area__macros": 1404.48, - "placeopt__design__instance__area__stdcell": 1405.15, - "placeopt__design__instance__count": 11637, - "placeopt__design__instance__count__macros": 4, - "placeopt__design__instance__count__stdcell": 11633, - "placeopt__design__instance__utilization": 0.504428, - "placeopt__design__instance__utilization__stdcell": 0.337334, - "placeopt__design__io": 135, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 515404.0, - "placeopt__power__internal__total": 0.0121428, - "placeopt__power__leakage__total": 0.000516833, - "placeopt__power__switching__total": 0.00165579, - "placeopt__power__total": 0.0143154, - "placeopt__runtime__total": "0:21.20", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.352009, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.519217, - "placeopt__timing__drv__setup_violation_count": 232, - "placeopt__timing__setup__tns": -2468.15, - "placeopt__timing__setup__ws": -23.4794, - "run__flow__design": "riscv32i", - "run__flow__generate_date": "2024-09-27 17:53", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "5f191437-63ce-45c2-ac5c-25dde4b73bdc", - "run__flow__variant": "base", - "synth__cpu__total": 29.72, - "synth__design__instance__area__stdcell": 2590.35194, - "synth__design__instance__count__stdcell": 10636.0, - "synth__mem__peak": 155392.0, - "synth__runtime__total": "0:30.16", - "total_time": "0:06:18.140000" -} \ No newline at end of file diff --git a/flow/designs/asap7/riscv32i/rules-base.json b/flow/designs/asap7/riscv32i/rules-base.json index 041c1a64a8..ce0d33577c 100644 --- a/flow/designs/asap7/riscv32i/rules-base.json +++ b/flow/designs/asap7/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 3191, + "value": 3109, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 13035, + "value": 11777, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1134, + "value": 1024, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1134, + "value": 1024, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 111130, + "value": 83651, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -130.12, + "value": -44.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 3234, + "value": 3180, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 764, + "value": 512, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -15.61, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD.bazel new file mode 100644 index 0000000000..e97eee723b --- /dev/null +++ b/flow/designs/asap7/swerv_wrapper/BUILD.bazel @@ -0,0 +1,118 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_macro", "orfs_synth") + +FAKERAMS = [ + "fakeram7_64x21", + "fakeram7_256x34", + "fakeram7_2048x39", +] + +# BLACKBOXES are those listed in SYNTH_HIERARCHICAL=1 +# +# 33.1. IC_DATA_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_IC_DEPTH8' to `/input.blif'.. + +BLACKBOXES = [ + "IC_TAG_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_TAG_DEPTH64", + "dbg", + "dec_decode_ctl", + "dec_gpr_ctl_GPR_BANKS1_GPR_BANKS_LOG21", + "dec_ib_ctl", + "dec_tlu_ctl", + "dec_trigger", + "dma_ctrl", + "exu_alu_ctl", + "ifu_aln_ctl", + "ifu_bp_ctl", + "ifu_ifc_ctl", + "ifu_mem_ctl", + "lsu_bus_intf", + "lsu_dccm_ctl", + "lsu_ecc", + "lsu_lsc_ctl", + "lsu_stbuf", + "lsu_trigger", + "pic_ctrl", + "ram_256x34", + # When run with SYNTH_HIERARCHICAL=1, which should not be used here, + # the error below is produced. + # + # ERROR: Missing cost information on instanced blackbox lsu_dccm_mem + "lsu_dccm_mem", + "exu_div_ctl", + "lsu_bus_buffer", + "ram_2048x39", + "exu", + "swerv_wrapper", +] + +[orfs_synth( + name = "{name}_netlist_synth".format(name = name), + arguments = { + "SDC_FILE": "$(location :constraint.sdc)", + "SYNTH_BLACKBOXES": " ".join([b for b in BLACKBOXES if b != name]), + "SYNTH_HIERARCHICAL": "0", + }, + data = [":constraint.sdc"], + module_top = name, + variant = "netlist", + verilog_files = [ + "macros.v", + "//flow/designs/src/swerv:verilog", + ], + deps = FAKERAMS, +) for name in BLACKBOXES] + +[filegroup( + name = "{name}_netlist".format(name = name), + srcs = ["{name}_netlist_synth".format(name = name)], + output_group = "1_synth.v", +) for name in BLACKBOXES] + +# ca. 540 seconds for sequential synthesis, vs 90 seconds for netlist synthesis. +filegroup( + name = "netlists", + srcs = [":{}_netlist".format(name) for name in BLACKBOXES], +) + +# Canonicalize the netlists to avoid rebuilds unecessarily. +# +# This is more a demonstration than a practical solution. +# +# Other things could be done here, like get a netlist from git lfs, +# process the netlist in some other way, with Naja, etc. +genrule( + name = "netlists_canonicalized", + srcs = [":netlists"], + outs = ["netlists_canonicalized.v"], + cmd = """ + cat $(locations :netlists) | grep -v -E '\\(\\* src = "|Generated by Yosys' > $@ + """, +) + +[orfs_macro( + name = top, + lef = "lef/{}.lef".format(top), + lib = "lib/{}.lib".format(top), + module_top = top, +) for top in FAKERAMS] + +orfs_flow( + name = "swerv_wrapper", + arguments = { + "LIB_MODEL": "CCS", + "SYNTH_HIERARCHICAL": "1", + "DIE_AREA": "0 0 550 600", + "CORE_AREA": "5 5 545 595", + "PLACE_PINS_ARGS": "-exclude left:* -exclude right:*", + "PLACE_DENSITY_LB_ADDON": "0.20", + "TNS_END_PERCENT": "100", + "PWR_NETS_VOLTAGEsS": "", + "GND_NETS_VOLTAGES": "", + }, + macros = FAKERAMS, + sources = { + "SDC_FILE": [":constraint.sdc"], + "SYNTH_NETLIST_FILES": [":netlists_canonicalized"], + }, + tags = ["manual"], + verilog_files = [], +) diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 2a42119d6d..2a22c2dde9 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -1,12 +1,46 @@ export DESIGN_NAME = swerv_wrapper export PLATFORM = asap7 -export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 30 -export RTLMP_MIN_MACRO = 4 +# SYNTH_KEEP_MODULES below is a captured list of kept modules +# with: +# +# make SYNTH_HIERARCHICAL=1 SYNTH_KEEP_MODULES= clean_synth synth +# +# To list modules with the keep_hiearchy=1 attribute, run: +# +# make run-yosys RUN_YOSYS_ARGS=-C +# +# source scripts/yosys_load.tcl +# ls A:keep_hierarchy=1 +export SYNTH_KEEP_MODULES ?= \ + IC_DATA_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_IC_DEPTH8 \ + IC_TAG_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_TAG_DEPTH64 \ + dbg \ + dec_decode_ctl \ + dec_gpr_ctl_GPR_BANKS1_GPR_BANKS_LOG21 \ + dec_ib_ctl \ + dec_tlu_ctl \ + dec_trigger \ + dma_ctrl \ + exu \ + exu_alu_ctl \ + exu_div_ctl \ + ifu_aln_ctl \ + ifu_bp_ctl \ + ifu_ifc_ctl \ + ifu_mem_ctl \ + lsu_bus_buffer \ + lsu_bus_intf \ + lsu_dccm_ctl \ + lsu_dccm_mem \ + lsu_ecc \ + lsu_lsc_ctl \ + lsu_stbuf \ + lsu_trigger \ + pic_ctrl \ + ram_2048x39 \ + ram_256x34 + export LIB_MODEL = CCS @@ -20,7 +54,7 @@ export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrap export DIE_AREA = 0 0 550 600 export CORE_AREA = 5 5 545 595 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/io.tcl export PLACE_DENSITY_LB_ADDON = 0.20 export ROUTING_LAYER_ADJUSTMENT = 0.2 diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index f679177441..2cae11c882 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -1,15 +1,15 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2500 +set clk_period 2500 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/swerv_wrapper/io.tcl b/flow/designs/asap7/swerv_wrapper/io.tcl new file mode 100644 index 0000000000..90bc38e041 --- /dev/null +++ b/flow/designs/asap7/swerv_wrapper/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:* -region right:* diff --git a/flow/designs/asap7/swerv_wrapper/metadata-base-ok.json b/flow/designs/asap7/swerv_wrapper/metadata-base-ok.json deleted file mode 100644 index 31f06bad9d..0000000000 --- a/flow/designs/asap7/swerv_wrapper/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2500.0000" - ], - "cts__clock__skew__hold": 243.478, - "cts__clock__skew__setup": 254.96, - "cts__cpu__total": 202.98, - "cts__design__core__area": 318395, - "cts__design__die__area": 330000, - "cts__design__instance__area": 50122.1, - "cts__design__instance__area__macros": 33343.6, - "cts__design__instance__area__stdcell": 16778.5, - "cts__design__instance__count": 159778, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 28, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 159750, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.157421, - "cts__design__instance__utilization__stdcell": 0.0588612, - "cts__design__io": 1416, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 18, - "cts__mem__peak": 2195536.0, - "cts__power__internal__total": 0.0519959, - "cts__power__leakage__total": 0.00361985, - "cts__power__switching__total": 0.00839734, - "cts__power__total": 0.0640131, - "cts__route__wirelength__estimated": 1382400.0, - "cts__runtime__total": "3:24.85", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.629151, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0667307, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 1157.69, - "design__io__hpwl": 309895352, - "design__violations": 0, - "detailedplace__cpu__total": 183.72, - "detailedplace__design__core__area": 318395, - "detailedplace__design__die__area": 330000, - "detailedplace__design__instance__area": 49669.9, - "detailedplace__design__instance__area__macros": 33343.6, - "detailedplace__design__instance__area__stdcell": 16326.3, - "detailedplace__design__instance__count": 158386, - "detailedplace__design__instance__count__macros": 28, - "detailedplace__design__instance__count__stdcell": 158358, - "detailedplace__design__instance__displacement__max": 12.577, - "detailedplace__design__instance__displacement__mean": 0.145, - "detailedplace__design__instance__displacement__total": 23050, - "detailedplace__design__instance__utilization": 0.156001, - "detailedplace__design__instance__utilization__stdcell": 0.0572747, - "detailedplace__design__io": 1416, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 18, - "detailedplace__mem__peak": 1826220.0, - "detailedplace__power__internal__total": 0.0472997, - "detailedplace__power__leakage__total": 0.00361942, - "detailedplace__power__switching__total": 0.00596141, - "detailedplace__power__total": 0.0568806, - "detailedplace__route__wirelength__estimated": 1388360.0, - "detailedplace__runtime__total": "3:05.20", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.629151, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0667307, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 1159.72, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 19, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 46452, - "detailedroute__route__drc_errors__iter:2": 9133, - "detailedroute__route__drc_errors__iter:3": 7411, - "detailedroute__route__drc_errors__iter:4": 373, - "detailedroute__route__drc_errors__iter:5": 21, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 125152, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1420474, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1420474, - "detailedroute__route__wirelength": 1572033, - "detailedroute__route__wirelength__iter:1": 1572156, - "detailedroute__route__wirelength__iter:2": 1571130, - "detailedroute__route__wirelength__iter:3": 1571488, - "detailedroute__route__wirelength__iter:4": 1572015, - "detailedroute__route__wirelength__iter:5": 1572035, - "detailedroute__route__wirelength__iter:6": 1572033, - "finish__clock__skew__hold": 425.317, - "finish__clock__skew__setup": 388.853, - "finish__cpu__total": 1830.12, - "finish__design__core__area": 318395, - "finish__design__die__area": 330000, - "finish__design__instance__area": 50123.5, - "finish__design__instance__area__macros": 33343.6, - "finish__design__instance__area__stdcell": 16779.9, - "finish__design__instance__count": 159852, - "finish__design__instance__count__macros": 28, - "finish__design__instance__count__stdcell": 159824, - "finish__design__instance__utilization": 0.157425, - "finish__design__instance__utilization__stdcell": 0.0588661, - "finish__design__io": 1416, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.759181, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0109177, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0576926, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0574897, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.712307, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0574897, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 18, - "finish__mem__peak": 13813716.0, - "finish__power__internal__total": 0.0523183, - "finish__power__leakage__total": 0.00361984, - "finish__power__switching__total": 0.0163237, - "finish__power__total": 0.0722618, - "finish__runtime__total": "31:13.71", - "finish__timing__drv__hold_violation_count": 747, - "finish__timing__drv__max_cap": 6, - "finish__timing__drv__max_cap_limit": -0.0996865, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 160, - "finish__timing__drv__max_slew_limit": -0.404926, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 383.129, - "finish__timing__wns_percent_delay": 14.337594, - "finish_merge__cpu__total": 29.25, - "finish_merge__mem__peak": 3054136.0, - "finish_merge__runtime__total": "0:31.15", - "floorplan__cpu__total": 148.28, - "floorplan__design__core__area": 318395, - "floorplan__design__die__area": 330000, - "floorplan__design__instance__area": 47084, - "floorplan__design__instance__area__macros": 33343.6, - "floorplan__design__instance__area__stdcell": 13740.3, - "floorplan__design__instance__count": 105196, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 28, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 105168, - "floorplan__design__instance__utilization": 0.147879, - "floorplan__design__instance__utilization__stdcell": 0.0482029, - "floorplan__design__io": 1416, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 21, - "floorplan__mem__peak": 899996.0, - "floorplan__power__internal__total": 0.0464306, - "floorplan__power__leakage__total": 0.00361765, - "floorplan__power__switching__total": 0.00540428, - "floorplan__power__total": 0.0554525, - "floorplan__runtime__total": "2:29.37", - "floorplan__timing__setup__tns": -6744030.0, - "floorplan__timing__setup__ws": -682.699, - "floorplan_io__cpu__total": 10.4, - "floorplan_io__mem__peak": 584840.0, - "floorplan_io__runtime__total": "0:10.81", - "floorplan_macro__cpu__total": 213.7, - "floorplan_macro__mem__peak": 1315272.0, - "floorplan_macro__runtime__total": "0:39.63", - "floorplan_pdn__cpu__total": 21.05, - "floorplan_pdn__mem__peak": 758920.0, - "floorplan_pdn__runtime__total": "0:21.73", - "floorplan_tap__cpu__total": 10.51, - "floorplan_tap__mem__peak": 541976.0, - "floorplan_tap__runtime__total": "0:10.91", - "floorplan_tdms__cpu__total": 0.05, - "floorplan_tdms__mem__peak": 109716.0, - "floorplan_tdms__runtime__total": "0:00.17", - "flow__errors__count": 0, - "flow__warnings__count": 18, - "globalplace__cpu__total": 901.27, - "globalplace__design__core__area": 318395, - "globalplace__design__die__area": 330000, - "globalplace__design__instance__area": 48192.5, - "globalplace__design__instance__area__macros": 33343.6, - "globalplace__design__instance__area__stdcell": 14848.9, - "globalplace__design__instance__count": 143212, - "globalplace__design__instance__count__macros": 28, - "globalplace__design__instance__count__stdcell": 143184, - "globalplace__design__instance__utilization": 0.151361, - "globalplace__design__instance__utilization__stdcell": 0.0520918, - "globalplace__design__io": 1416, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 18, - "globalplace__mem__peak": 2684928.0, - "globalplace__power__internal__total": 0.0464306, - "globalplace__power__leakage__total": 0.00361765, - "globalplace__power__switching__total": 0.00540428, - "globalplace__power__total": 0.0554525, - "globalplace__runtime__total": "9:38.53", - "globalplace__timing__setup__tns": -6790540.0, - "globalplace__timing__setup__ws": -682.699, - "globalplace_io__cpu__total": 10.91, - "globalplace_io__mem__peak": 668204.0, - "globalplace_io__runtime__total": "0:11.46", - "globalplace_skip_io__cpu__total": 395.53, - "globalplace_skip_io__mem__peak": 1291016.0, - "globalplace_skip_io__runtime__total": "2:20.85", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 243.478, - "globalroute__clock__skew__setup": 254.96, - "globalroute__cpu__total": 480.03, - "globalroute__design__core__area": 318395, - "globalroute__design__die__area": 330000, - "globalroute__design__instance__area": 50123.5, - "globalroute__design__instance__area__macros": 33343.6, - "globalroute__design__instance__area__stdcell": 16779.9, - "globalroute__design__instance__count": 159852, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 28, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 159824, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.157425, - "globalroute__design__instance__utilization__stdcell": 0.0588661, - "globalroute__design__io": 1416, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 19, - "globalroute__mem__peak": 3851508.0, - "globalroute__power__internal__total": 0.0520128, - "globalroute__power__leakage__total": 0.00361984, - "globalroute__power__switching__total": 0.00840339, - "globalroute__power__total": 0.0640361, - "globalroute__route__wirelength__estimated": 1382410.0, - "globalroute__runtime__total": "4:50.82", - "globalroute__timing__clock__slack": 1157.689, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.629151, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0667307, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 1157.69, - "placeopt__cpu__total": 158.8, - "placeopt__design__core__area": 318395, - "placeopt__design__die__area": 330000, - "placeopt__design__instance__area": 49669.9, - "placeopt__design__instance__area__macros": 33343.6, - "placeopt__design__instance__area__stdcell": 16326.3, - "placeopt__design__instance__count": 158386, - "placeopt__design__instance__count__macros": 28, - "placeopt__design__instance__count__stdcell": 158358, - "placeopt__design__instance__utilization": 0.156001, - "placeopt__design__instance__utilization__stdcell": 0.0572747, - "placeopt__design__io": 1416, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 18, - "placeopt__mem__peak": 1206836.0, - "placeopt__power__internal__total": 0.0472997, - "placeopt__power__leakage__total": 0.00361942, - "placeopt__power__switching__total": 0.00596141, - "placeopt__power__total": 0.0568806, - "placeopt__runtime__total": "2:40.04", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.629151, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0667307, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1159.72, - "run__flow__design": "swerv_wrapper", - "run__flow__generate_date": "2024-10-01 04:08", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16138-g2803c4963", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "594b4339edcd1145b3498ca45cc032969dd7bc09", - "run__flow__scripts_commit": "594b4339edcd1145b3498ca45cc032969dd7bc09", - "run__flow__uuid": "32e81bb1-5d56-40c1-b5c5-face5df482c9", - "run__flow__variant": "base", - "synth__cpu__total": 534.52, - "synth__design__instance__area__stdcell": 46643.84674, - "synth__design__instance__count__stdcell": 105188.0, - "synth__mem__peak": 1179180.0, - "synth__runtime__total": "9:07.89", - "total_time": "1:10:57.120000" -} \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 2c19a13eca..e1ce5d7c25 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1623335, + "value": 1867701, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1034, + "value": 286, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/asap7/uart/config.mk b/flow/designs/asap7/uart/config.mk index 6d980d3f7d..05de91bcbb 100644 --- a/flow/designs/asap7/uart/config.mk +++ b/flow/designs/asap7/uart/config.mk @@ -13,3 +13,4 @@ export TNS_END_PERCENT = 100 export EQUIVALENCE_CHECK ?= 1 export REMOVE_CELLS_FOR_EQY = TAPCELL* export SKIP_GATE_CLONING = 1 +export VERILOG_TOP_PARAMS = DATA_WIDTH 8 diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc index cc49402954..b58ae3408f 100644 --- a/flow/designs/asap7/uart/constraint.sdc +++ b/flow/designs/asap7/uart/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 300 +set clk_period 300 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/asap7/uart/metadata-base-ok.json b/flow/designs/asap7/uart/metadata-base-ok.json deleted file mode 100644 index e7cbc2455f..0000000000 --- a/flow/designs/asap7/uart/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 300.0000" - ], - "cts__clock__skew__hold": 9.76219, - "cts__clock__skew__setup": 4.42842, - "cts__cpu__total": 14.59, - "cts__design__core__area": 221.324, - "cts__design__die__area": 289, - "cts__design__instance__area": 90.5418, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 90.5418, - "cts__design__instance__count": 797, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 47, - "cts__design__instance__count__stdcell": 797, - "cts__design__instance__displacement__max": 2.646, - "cts__design__instance__displacement__mean": 0.072, - "cts__design__instance__displacement__total": 57.87, - "cts__design__instance__utilization": 0.409091, - "cts__design__instance__utilization__stdcell": 0.409091, - "cts__design__io": 44, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 11, - "cts__mem__peak": 578824.0, - "cts__power__internal__total": 0.00143047, - "cts__power__leakage__total": 8.67067e-08, - "cts__power__switching__total": 0.000883171, - "cts__power__total": 0.00231373, - "cts__route__wirelength__estimated": 1300.45, - "cts__runtime__total": "0:10.29", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.836129, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.786209, - "cts__timing__drv__setup_violation_count": 25, - "cts__timing__setup__tns": -267.992, - "cts__timing__setup__ws": -30.4477, - "design__io__hpwl": 254286, - "design__violations": 0, - "detailedplace__cpu__total": 1.94, - "detailedplace__design__core__area": 221.324, - "detailedplace__design__die__area": 289, - "detailedplace__design__instance__area": 83.6455, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 83.6455, - "detailedplace__design__instance__count": 736, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 736, - "detailedplace__design__instance__displacement__max": 1.272, - "detailedplace__design__instance__displacement__mean": 0.212, - "detailedplace__design__instance__displacement__total": 156.485, - "detailedplace__design__instance__utilization": 0.377931, - "detailedplace__design__instance__utilization__stdcell": 0.377931, - "detailedplace__design__io": 44, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 10, - "detailedplace__mem__peak": 215736.0, - "detailedplace__power__internal__total": 0.00126671, - "detailedplace__power__leakage__total": 7.68267e-08, - "detailedplace__power__switching__total": 0.00072061, - "detailedplace__power__total": 0.0019874, - "detailedplace__route__wirelength__estimated": 1180.98, - "detailedplace__runtime__total": "0:02.08", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.715117, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.779233, - "detailedplace__timing__drv__setup_violation_count": 47, - "detailedplace__timing__setup__tns": -1076.67, - "detailedplace__timing__setup__ws": -61.8452, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 11, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 117, - "detailedroute__route__drc_errors__iter:2": 10, - "detailedroute__route__drc_errors__iter:3": 11, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 726, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 5717, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 5717, - "detailedroute__route__wirelength": 1525, - "detailedroute__route__wirelength__iter:1": 1541, - "detailedroute__route__wirelength__iter:2": 1520, - "detailedroute__route__wirelength__iter:3": 1525, - "detailedroute__route__wirelength__iter:4": 1525, - "finish__clock__skew__hold": 10.8344, - "finish__clock__skew__setup": 5.52909, - "finish__cpu__total": 3.56, - "finish__design__core__area": 221.324, - "finish__design__die__area": 289, - "finish__design__instance__area": 91.577, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 91.577, - "finish__design__instance__count": 808, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 808, - "finish__design__instance__utilization": 0.413768, - "finish__design__instance__utilization__stdcell": 0.413768, - "finish__design__io": 44, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.698083, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00197376, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00668648, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00645498, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.693314, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00645498, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 10, - "finish__mem__peak": 365812.0, - "finish__power__internal__total": 0.00145174, - "finish__power__leakage__total": 8.84939e-08, - "finish__power__switching__total": 0.000921705, - "finish__power__total": 0.00237353, - "finish__runtime__total": "0:03.90", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.817854, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.780811, - "finish__timing__drv__setup_violation_count": 29, - "finish__timing__setup__tns": -373.565, - "finish__timing__setup__ws": -33.3799, - "finish__timing__wns_percent_delay": -8.35535, - "finish_merge__cpu__total": 1.44, - "finish_merge__mem__peak": 397220.0, - "finish_merge__runtime__total": "0:01.66", - "floorplan__cpu__total": 3.11, - "floorplan__design__core__area": 221.324, - "floorplan__design__die__area": 289, - "floorplan__design__instance__area": 75.2474, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 75.2474, - "floorplan__design__instance__count": 590, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 6, - "floorplan__design__instance__count__stdcell": 590, - "floorplan__design__instance__utilization": 0.339987, - "floorplan__design__instance__utilization__stdcell": 0.339987, - "floorplan__design__io": 44, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 303, - "floorplan__mem__peak": 216024.0, - "floorplan__power__internal__total": 0.00125668, - "floorplan__power__leakage__total": 6.95279e-08, - "floorplan__power__switching__total": 0.000580854, - "floorplan__power__total": 0.00183761, - "floorplan__runtime__total": "0:03.23", - "floorplan__timing__setup__tns": -162.706, - "floorplan__timing__setup__ws": -16.114, - "floorplan_io__cpu__total": 1.43, - "floorplan_io__mem__peak": 210972.0, - "floorplan_io__runtime__total": "0:01.53", - "floorplan_macro__cpu__total": 1.38, - "floorplan_macro__mem__peak": 210404.0, - "floorplan_macro__runtime__total": "0:01.53", - "floorplan_pdn__cpu__total": 1.44, - "floorplan_pdn__mem__peak": 213104.0, - "floorplan_pdn__runtime__total": "0:01.55", - "floorplan_tap__cpu__total": 1.4, - "floorplan_tap__mem__peak": 210456.0, - "floorplan_tap__runtime__total": "0:01.53", - "floorplan_tdms__cpu__total": 1.39, - "floorplan_tdms__mem__peak": 210576.0, - "floorplan_tdms__runtime__total": "0:01.54", - "flow__errors__count": 0, - "flow__warnings__count": 10, - "globalplace__cpu__total": 303.34, - "globalplace__design__core__area": 221.324, - "globalplace__design__die__area": 289, - "globalplace__design__instance__area": 78.455, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 78.455, - "globalplace__design__instance__count": 700, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 700, - "globalplace__design__instance__utilization": 0.35448, - "globalplace__design__instance__utilization__stdcell": 0.35448, - "globalplace__design__io": 44, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 10, - "globalplace__mem__peak": 528844.0, - "globalplace__power__internal__total": 0.00125729, - "globalplace__power__leakage__total": 6.95279e-08, - "globalplace__power__switching__total": 0.000659305, - "globalplace__power__total": 0.00191666, - "globalplace__runtime__total": "0:34.64", - "globalplace__timing__setup__tns": -640.901, - "globalplace__timing__setup__ws": -28.7106, - "globalplace_io__cpu__total": 1.4, - "globalplace_io__mem__peak": 211532.0, - "globalplace_io__runtime__total": "0:01.53", - "globalplace_skip_io__cpu__total": 330.79, - "globalplace_skip_io__mem__peak": 211740.0, - "globalplace_skip_io__runtime__total": "0:35.38", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 9.83844, - "globalroute__clock__skew__setup": 4.94723, - "globalroute__cpu__total": 4.76, - "globalroute__design__core__area": 221.324, - "globalroute__design__die__area": 289, - "globalroute__design__instance__area": 91.577, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 91.577, - "globalroute__design__instance__count": 808, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 11, - "globalroute__design__instance__count__stdcell": 808, - "globalroute__design__instance__displacement__max": 1.62, - "globalroute__design__instance__displacement__mean": 0.019, - "globalroute__design__instance__displacement__total": 15.714, - "globalroute__design__instance__utilization": 0.413768, - "globalroute__design__instance__utilization__stdcell": 0.413768, - "globalroute__design__io": 44, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 12, - "globalroute__mem__peak": 548656.0, - "globalroute__power__internal__total": 0.00145232, - "globalroute__power__leakage__total": 8.84939e-08, - "globalroute__power__switching__total": 0.000959673, - "globalroute__power__total": 0.00241208, - "globalroute__route__wirelength__estimated": 1332.57, - "globalroute__runtime__total": "0:04.41", - "globalroute__timing__clock__slack": -33.236, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.826772, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.782283, - "globalroute__timing__drv__setup_violation_count": 34, - "globalroute__timing__setup__tns": -424.565, - "globalroute__timing__setup__ws": -33.2361, - "placeopt__cpu__total": 2.03, - "placeopt__design__core__area": 221.324, - "placeopt__design__die__area": 289, - "placeopt__design__instance__area": 83.6455, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 83.6455, - "placeopt__design__instance__count": 736, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 736, - "placeopt__design__instance__utilization": 0.377931, - "placeopt__design__instance__utilization__stdcell": 0.377931, - "placeopt__design__io": 44, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 10, - "placeopt__mem__peak": 481404.0, - "placeopt__power__internal__total": 0.00126656, - "placeopt__power__leakage__total": 7.68267e-08, - "placeopt__power__switching__total": 0.000715871, - "placeopt__power__total": 0.00198251, - "placeopt__runtime__total": "0:02.36", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.718801, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.781285, - "placeopt__timing__drv__setup_violation_count": 46, - "placeopt__timing__setup__tns": -1052.3, - "placeopt__timing__setup__ws": -61.7286, - "run__flow__design": "uart", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "asap7", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "2e7356d8-a9e8-4be3-a0bb-66c6e6b3a63e", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 3.91, - "synth__design__instance__area__stdcell": 74.59128, - "synth__design__instance__count__stdcell": 588.0, - "synth__mem__peak": 141824.0, - "synth__runtime__total": "0:04.14", - "total_time": "0:01:51.300000" -} \ No newline at end of file diff --git a/flow/designs/asap7/uart/rules-base.json b/flow/designs/asap7/uart/rules-base.json index b2fe2ff2e2..80006ed54c 100644 --- a/flow/designs/asap7/uart/rules-base.json +++ b/flow/designs/asap7/uart/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 85.78, + "value": 83.24, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 96, + "value": 95, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 846, + "value": 835, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 74, + "value": 73, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 74, + "value": 73, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -48.37, + "value": -20.24, "compare": ">=" }, "finish__design__instance__area": { - "value": 105, + "value": 103, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 37, + "value": 36, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.02, + "value": -11.75, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc index a930ae4ba7..a820710ab4 100644 --- a/flow/designs/gf12/aes/constraint.sdc +++ b/flow/designs/gf12/aes/constraint.sdc @@ -1,17 +1,17 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 420 +set clk_period 420 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/aes/metadata-base-ok.json b/flow/designs/gf12/aes/metadata-base-ok.json deleted file mode 100644 index 38a30aff70..0000000000 --- a/flow/designs/gf12/aes/metadata-base-ok.json +++ /dev/null @@ -1,374 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 420.0000" - ], - "cts__clock__skew__hold": 13.1912, - "cts__clock__skew__setup": 7.62611, - "cts__cpu__total": 24.04, - "cts__design__core__area": 8039.49, - "cts__design__die__area": 8851.05, - "cts__design__instance__area": 4719.81, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 4719.81, - "cts__design__instance__count": 15401, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 15401, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.587079, - "cts__design__instance__utilization__stdcell": 0.587079, - "cts__design__io": 388, - "cts__design__rows": 155, - "cts__design__rows:sc9mcpp84_12lp": 155, - "cts__design__sites": 166160, - "cts__design__sites:sc9mcpp84_12lp": 166160, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 2, - "cts__mem__peak": 1436616.0, - "cts__power__internal__total": 0.0684388, - "cts__power__leakage__total": 4.96174e-06, - "cts__power__switching__total": 0.109386, - "cts__power__total": 0.17783, - "cts__route__wirelength__estimated": 92933.1, - "cts__runtime__total": "0:25.18", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.918812, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.922072, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 13.0093, - "design__io__hpwl": 24176753, - "design__violations": 0, - "detailedplace__cpu__total": 12.99, - "detailedplace__design__core__area": 8039.49, - "detailedplace__design__die__area": 8851.05, - "detailedplace__design__instance__area": 4658.46, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 4658.46, - "detailedplace__design__instance__count": 15329, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 15329, - "detailedplace__design__instance__displacement__max": 14.2615, - "detailedplace__design__instance__displacement__mean": 0.9035, - "detailedplace__design__instance__displacement__total": 13876.6, - "detailedplace__design__instance__utilization": 0.579448, - "detailedplace__design__instance__utilization__stdcell": 0.579448, - "detailedplace__design__io": 388, - "detailedplace__design__rows": 155, - "detailedplace__design__rows:sc9mcpp84_12lp": 155, - "detailedplace__design__sites": 166160, - "detailedplace__design__sites:sc9mcpp84_12lp": 166160, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 444224.0, - "detailedplace__power__internal__total": 0.0661303, - "detailedplace__power__leakage__total": 2.94005e-06, - "detailedplace__power__switching__total": 0.106752, - "detailedplace__power__total": 0.172885, - "detailedplace__route__wirelength__estimated": 97702.5, - "detailedplace__runtime__total": "0:13.54", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.919918, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.728118, - "detailedplace__timing__drv__setup_violation_count": 5, - "detailedplace__timing__setup__tns": -43.2154, - "detailedplace__timing__setup__ws": -17.93, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 11506, - "detailedroute__route__drc_errors__iter:2": 999, - "detailedroute__route__drc_errors__iter:3": 793, - "detailedroute__route__drc_errors__iter:4": 6, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 15115, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 154020, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 154020, - "detailedroute__route__wirelength": 114535, - "detailedroute__route__wirelength__iter:1": 116314, - "detailedroute__route__wirelength__iter:2": 115037, - "detailedroute__route__wirelength__iter:3": 114571, - "detailedroute__route__wirelength__iter:4": 114544, - "detailedroute__route__wirelength__iter:5": 114535, - "finish__clock__skew__hold": 14.0053, - "finish__clock__skew__setup": 7.71876, - "finish__cpu__total": 15.98, - "finish__design__core__area": 8039.49, - "finish__design__die__area": 8851.05, - "finish__design__instance__area": 4720.39, - "finish__design__instance__area__class:buffer": 829.253, - "finish__design__instance__area__class:clock_buffer": 54.1901, - "finish__design__instance__area__class:clock_inverter": 7.16083, - "finish__design__instance__area__class:inverter": 72.7695, - "finish__design__instance__area__class:multi_input_combinational_cell": 2830.03, - "finish__design__instance__area__class:sequential_cell": 449.584, - "finish__design__instance__area__class:timing_repair_buffer": 159.425, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 4720.39, - "finish__design__instance__count": 15401, - "finish__design__instance__count__class:buffer": 845, - "finish__design__instance__count__class:clock_buffer": 54, - "finish__design__instance__count__class:clock_inverter": 18, - "finish__design__instance__count__class:inverter": 493, - "finish__design__instance__count__class:multi_input_combinational_cell": 12530, - "finish__design__instance__count__class:sequential_cell": 562, - "finish__design__instance__count__class:timing_repair_buffer": 387, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 15401, - "finish__design__instance__utilization": 0.587151, - "finish__design__instance__utilization__stdcell": 0.587151, - "finish__design__io": 388, - "finish__design__rows": 155, - "finish__design__rows:sc9mcpp84_12lp": 155, - "finish__design__sites": 166160, - "finish__design__sites:sc9mcpp84_12lp": 166160, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 660368.0, - "finish__power__internal__total": 0.0684675, - "finish__power__leakage__total": 4.96262e-06, - "finish__power__switching__total": 0.11477, - "finish__power__total": 0.183242, - "finish__runtime__total": "0:17.20", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.90486, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.924909, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 4.28071, - "finish__timing__wns_percent_delay": 0.933062, - "finish_merge__cpu__total": 2.76, - "finish_merge__mem__peak": 552480.0, - "finish_merge__runtime__total": "0:10.86", - "floorplan__cpu__total": 5.92, - "floorplan__design__core__area": 8039.49, - "floorplan__design__die__area": 8851.05, - "floorplan__design__instance__area": 3245.79, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 3245.79, - "floorplan__design__instance__count": 14430, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 14430, - "floorplan__design__instance__utilization": 0.403731, - "floorplan__design__instance__utilization__stdcell": 0.403731, - "floorplan__design__io": 388, - "floorplan__design__rows": 155, - "floorplan__design__rows:sc9mcpp84_12lp": 155, - "floorplan__design__sites": 166160, - "floorplan__design__sites:sc9mcpp84_12lp": 166160, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 417244.0, - "floorplan__power__internal__total": 0.0582528, - "floorplan__power__leakage__total": 2.5086e-06, - "floorplan__power__switching__total": 0.0648317, - "floorplan__power__total": 0.123087, - "floorplan__runtime__total": "0:09.37", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 89.7826, - "floorplan_io__cpu__total": 3.21, - "floorplan_io__mem__peak": 379288.0, - "floorplan_io__runtime__total": "0:03.64", - "floorplan_macro__cpu__total": 3.2, - "floorplan_macro__mem__peak": 379096.0, - "floorplan_macro__runtime__total": "0:03.65", - "floorplan_pdn__cpu__total": 3.42, - "floorplan_pdn__mem__peak": 382772.0, - "floorplan_pdn__runtime__total": "0:04.05", - "floorplan_tap__cpu__total": 3.16, - "floorplan_tap__mem__peak": 370428.0, - "floorplan_tap__runtime__total": "0:03.82", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 569.49, - "globalplace__design__core__area": 8039.49, - "globalplace__design__die__area": 8851.05, - "globalplace__design__instance__area": 4472.04, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 4472.04, - "globalplace__design__instance__count": 14942, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 14942, - "globalplace__design__instance__utilization": 0.556259, - "globalplace__design__instance__utilization__stdcell": 0.556259, - "globalplace__design__io": 388, - "globalplace__design__rows": 155, - "globalplace__design__rows:sc9mcpp84_12lp": 155, - "globalplace__design__sites": 166160, - "globalplace__design__sites:sc9mcpp84_12lp": 166160, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1420412.0, - "globalplace__power__internal__total": 0.0658676, - "globalplace__power__leakage__total": 2.87608e-06, - "globalplace__power__switching__total": 0.104927, - "globalplace__power__total": 0.170797, - "globalplace__runtime__total": "0:50.81", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 31.7307, - "globalplace_io__cpu__total": 3.18, - "globalplace_io__mem__peak": 381656.0, - "globalplace_io__runtime__total": "0:03.66", - "globalplace_skip_io__cpu__total": 106.05, - "globalplace_skip_io__mem__peak": 400820.0, - "globalplace_skip_io__runtime__total": "0:06.92", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 15.7224, - "globalroute__clock__skew__setup": 10.3859, - "globalroute__cpu__total": 56.5, - "globalroute__design__core__area": 8039.49, - "globalroute__design__die__area": 8851.05, - "globalroute__design__instance__area": 4720.39, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 4720.39, - "globalroute__design__instance__count": 15401, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 15401, - "globalroute__design__instance__displacement__max": 1.596, - "globalroute__design__instance__displacement__mean": 0.0005, - "globalroute__design__instance__displacement__total": 14.16, - "globalroute__design__instance__utilization": 0.587151, - "globalroute__design__instance__utilization__stdcell": 0.587151, - "globalroute__design__io": 388, - "globalroute__design__rows": 155, - "globalroute__design__rows:sc9mcpp84_12lp": 155, - "globalroute__design__sites": 166160, - "globalroute__design__sites:sc9mcpp84_12lp": 166160, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 3, - "globalroute__mem__peak": 1631452.0, - "globalroute__power__internal__total": 0.0685886, - "globalroute__power__leakage__total": 4.96262e-06, - "globalroute__power__switching__total": 0.121372, - "globalroute__power__total": 0.189966, - "globalroute__route__wirelength__estimated": 92944.3, - "globalroute__runtime__total": "0:21.01", - "globalroute__timing__clock__slack": -2.879, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.91649, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.873721, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -2.87875, - "globalroute__timing__setup__ws": -2.87875, - "placeopt__cpu__total": 10.4, - "placeopt__design__core__area": 8039.49, - "placeopt__design__die__area": 8851.05, - "placeopt__design__instance__area": 4658.46, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 4658.46, - "placeopt__design__instance__count": 15329, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 15329, - "placeopt__design__instance__utilization": 0.579448, - "placeopt__design__instance__utilization__stdcell": 0.579448, - "placeopt__design__io": 388, - "placeopt__design__rows": 155, - "placeopt__design__rows:sc9mcpp84_12lp": 155, - "placeopt__design__sites": 166160, - "placeopt__design__sites:sc9mcpp84_12lp": 166160, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1265004.0, - "placeopt__power__internal__total": 0.0660972, - "placeopt__power__leakage__total": 2.94005e-06, - "placeopt__power__switching__total": 0.105352, - "placeopt__power__total": 0.171452, - "placeopt__runtime__total": "0:11.58", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.92068, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.721277, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 6.27742, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-11-22 22:32", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "ec7293db19147fc6f53f724975d2e7f587635c34", - "run__flow__uuid": "e49a753b-ce89-4f4f-9b98-17fc48d4a0c8", - "run__flow__variant": "base", - "synth__cpu__total": 16.17, - "synth__design__instance__area__stdcell": 3245.792252, - "synth__design__instance__count__stdcell": 14430.0, - "synth__mem__peak": 424192.0, - "synth__runtime__total": "0:17.08", - "total_time": "0:03:22.370000" -} \ No newline at end of file diff --git a/flow/designs/gf12/aes/rules-base.json b/flow/designs/gf12/aes/rules-base.json index 8203b3070d..750f9f5e3e 100644 --- a/flow/designs/gf12/aes/rules-base.json +++ b/flow/designs/gf12/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5357, + "value": 5349, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 128493, + "value": 148738, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -111.71, "compare": ">=" }, "finish__design__instance__area": { - "value": 5428, + "value": 5418, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -30.22, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index bc3ef63e47..28194633ef 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -2,7 +2,7 @@ export DESIGN_NAME = ariane export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 10000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 # export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ @@ -22,11 +22,9 @@ export CORE_AREA = 5 5 745 595 export PLACE_DENSITY ?= 0.50 -export PLACE_PINS_ARGS = -exclude left:0-150 -exclude left:450-600 -exclude right:* -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 - export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl ifeq ($(USE_FILL),1) diff --git a/flow/designs/gf12/ariane/constraint.sdc b/flow/designs/gf12/ariane/constraint.sdc index 2430c4b71e..d5971e4984 100644 --- a/flow/designs/gf12/ariane/constraint.sdc +++ b/flow/designs/gf12/ariane/constraint.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} -set_input_delay -clock core_clock 1000 [get_ports rst_ni] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1000 [get_ports ipi_i] -set_input_delay -clock core_clock 1000 [get_ports time_irq_i] -set_input_delay -clock core_clock 1000 [get_ports debug_req_i] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3400 -waveform {0 850} +set_input_delay -clock core_clock 1000 [get_ports rst_ni] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1000 [get_ports ipi_i] +set_input_delay -clock core_clock 1000 [get_ports time_irq_i] +set_input_delay -clock core_clock 1000 [get_ports debug_req_i] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1000 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1000 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane/constraint_hier.sdc b/flow/designs/gf12/ariane/constraint_hier.sdc index 89c4ae0115..1a22a7607f 100644 --- a/flow/designs/gf12/ariane/constraint_hier.sdc +++ b/flow/designs/gf12/ariane/constraint_hier.sdc @@ -1,495 +1,495 @@ -create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} -set_input_delay -clock core_clock 1500 [get_ports rst_ni] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1500 [get_ports ipi_i] -set_input_delay -clock core_clock 1500 [get_ports time_irq_i] -set_input_delay -clock core_clock 1500 [get_ports debug_req_i] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 3000 -waveform {0 1500} +set_input_delay -clock core_clock 1500 [get_ports rst_ni] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 1500 [get_ports ipi_i] +set_input_delay -clock core_clock 1500 [get_ports time_irq_i] +set_input_delay -clock core_clock 1500 [get_ports debug_req_i] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 1500 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 1500 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/gf12/ariane/io.tcl b/flow/designs/gf12/ariane/io.tcl new file mode 100644 index 0000000000..b49abf4c20 --- /dev/null +++ b/flow/designs/gf12/ariane/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/ariane/metadata-base-ok.json b/flow/designs/gf12/ariane/metadata-base-ok.json deleted file mode 100644 index 96024f1555..0000000000 --- a/flow/designs/gf12/ariane/metadata-base-ok.json +++ /dev/null @@ -1,462 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 3000.0000" - ], - "cts__clock__skew__hold": 1619.54, - "cts__clock__skew__setup": 1926.55, - "cts__cpu__total": 4018.92, - "cts__design__core__area": 436018, - "cts__design__die__area": 510000, - "cts__design__instance__area": 205252, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 112562, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 92689.8, - "cts__design__instance__count": 205971, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 442, - "cts__design__instance__count__macros": 37, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 2, - "cts__design__instance__count__stdcell": 205934, - "cts__design__instance__displacement__max": 22.0665, - "cts__design__instance__displacement__mean": 0.005, - "cts__design__instance__displacement__total": 1076.51, - "cts__design__instance__utilization": 0.470743, - "cts__design__instance__utilization__stdcell": 0.286561, - "cts__design__io": 495, - "cts__design__rows": 6589, - "cts__design__rows:sc9mcpp84_12lp": 6589, - "cts__design__sites": 6289833, - "cts__design__sites:sc9mcpp84_12lp": 6289833, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 3449004.0, - "cts__power__internal__total": 0.053603, - "cts__power__leakage__total": 0.00132041, - "cts__power__switching__total": 0.0444882, - "cts__power__total": 0.0994117, - "cts__route__wirelength__estimated": 2777170.0, - "cts__runtime__total": "1:07:01", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0930124, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 17, - "cts__timing__drv__max_slew_limit": -0.806155, - "cts__timing__drv__setup_violation_count": 2568, - "cts__timing__setup__tns": -431499, - "cts__timing__setup__ws": -532.016, - "design__io__hpwl": 409275842, - "design__violations": 0, - "detailedplace__cpu__total": 191.88, - "detailedplace__design__core__area": 436018, - "detailedplace__design__die__area": 510000, - "detailedplace__design__instance__area": 202965, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 112562, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 90402.7, - "detailedplace__design__instance__count": 203886, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 37, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 203849, - "detailedplace__design__instance__displacement__max": 22.8585, - "detailedplace__design__instance__displacement__mean": 0.462, - "detailedplace__design__instance__displacement__total": 94330.7, - "detailedplace__design__instance__utilization": 0.465497, - "detailedplace__design__instance__utilization__stdcell": 0.279491, - "detailedplace__design__io": 495, - "detailedplace__design__rows": 6589, - "detailedplace__design__rows:sc9mcpp84_12lp": 6589, - "detailedplace__design__sites": 6289833, - "detailedplace__design__sites:sc9mcpp84_12lp": 6289833, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 2412300.0, - "detailedplace__power__internal__total": 0.0413449, - "detailedplace__power__leakage__total": 0.00124275, - "detailedplace__power__switching__total": 0.035198, - "detailedplace__power__total": 0.0777857, - "detailedplace__route__wirelength__estimated": 2827200.0, - "detailedplace__runtime__total": "3:14.19", - "detailedplace__timing__drv__hold_violation_count": 496, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0933967, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 2, - "detailedplace__timing__drv__max_slew_limit": -0.01959, - "detailedplace__timing__drv__setup_violation_count": 3800, - "detailedplace__timing__setup__tns": -1961110.0, - "detailedplace__timing__setup__ws": -869.238, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 21, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 131656, - "detailedroute__route__drc_errors__iter:10": 2, - "detailedroute__route__drc_errors__iter:11": 2, - "detailedroute__route__drc_errors__iter:12": 2, - "detailedroute__route__drc_errors__iter:13": 2, - "detailedroute__route__drc_errors__iter:14": 2, - "detailedroute__route__drc_errors__iter:15": 2, - "detailedroute__route__drc_errors__iter:16": 2, - "detailedroute__route__drc_errors__iter:17": 2, - "detailedroute__route__drc_errors__iter:18": 2, - "detailedroute__route__drc_errors__iter:19": 2, - "detailedroute__route__drc_errors__iter:2": 9912, - "detailedroute__route__drc_errors__iter:20": 2, - "detailedroute__route__drc_errors__iter:21": 2, - "detailedroute__route__drc_errors__iter:22": 2, - "detailedroute__route__drc_errors__iter:23": 2, - "detailedroute__route__drc_errors__iter:24": 2, - "detailedroute__route__drc_errors__iter:25": 2, - "detailedroute__route__drc_errors__iter:26": 5, - "detailedroute__route__drc_errors__iter:27": 2, - "detailedroute__route__drc_errors__iter:28": 2, - "detailedroute__route__drc_errors__iter:29": 2, - "detailedroute__route__drc_errors__iter:3": 6802, - "detailedroute__route__drc_errors__iter:30": 2, - "detailedroute__route__drc_errors__iter:31": 2, - "detailedroute__route__drc_errors__iter:32": 2, - "detailedroute__route__drc_errors__iter:33": 2, - "detailedroute__route__drc_errors__iter:34": 5, - "detailedroute__route__drc_errors__iter:35": 2, - "detailedroute__route__drc_errors__iter:36": 2, - "detailedroute__route__drc_errors__iter:37": 2, - "detailedroute__route__drc_errors__iter:38": 2, - "detailedroute__route__drc_errors__iter:39": 2, - "detailedroute__route__drc_errors__iter:4": 187, - "detailedroute__route__drc_errors__iter:40": 2, - "detailedroute__route__drc_errors__iter:41": 2, - "detailedroute__route__drc_errors__iter:42": 2, - "detailedroute__route__drc_errors__iter:43": 2, - "detailedroute__route__drc_errors__iter:44": 2, - "detailedroute__route__drc_errors__iter:45": 2, - "detailedroute__route__drc_errors__iter:46": 2, - "detailedroute__route__drc_errors__iter:47": 2, - "detailedroute__route__drc_errors__iter:48": 2, - "detailedroute__route__drc_errors__iter:49": 0, - "detailedroute__route__drc_errors__iter:5": 41, - "detailedroute__route__drc_errors__iter:6": 16, - "detailedroute__route__drc_errors__iter:7": 8, - "detailedroute__route__drc_errors__iter:8": 6, - "detailedroute__route__drc_errors__iter:9": 6, - "detailedroute__route__net": 187241, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2010515, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2010515, - "detailedroute__route__wirelength": 3284456, - "detailedroute__route__wirelength__iter:1": 3300920, - "detailedroute__route__wirelength__iter:10": 3284455, - "detailedroute__route__wirelength__iter:11": 3284455, - "detailedroute__route__wirelength__iter:12": 3284455, - "detailedroute__route__wirelength__iter:13": 3284455, - "detailedroute__route__wirelength__iter:14": 3284455, - "detailedroute__route__wirelength__iter:15": 3284455, - "detailedroute__route__wirelength__iter:16": 3284455, - "detailedroute__route__wirelength__iter:17": 3284455, - "detailedroute__route__wirelength__iter:18": 3284455, - "detailedroute__route__wirelength__iter:19": 3284455, - "detailedroute__route__wirelength__iter:2": 3287523, - "detailedroute__route__wirelength__iter:20": 3284455, - "detailedroute__route__wirelength__iter:21": 3284455, - "detailedroute__route__wirelength__iter:22": 3284455, - "detailedroute__route__wirelength__iter:23": 3284455, - "detailedroute__route__wirelength__iter:24": 3284455, - "detailedroute__route__wirelength__iter:25": 3284455, - "detailedroute__route__wirelength__iter:26": 3284455, - "detailedroute__route__wirelength__iter:27": 3284455, - "detailedroute__route__wirelength__iter:28": 3284455, - "detailedroute__route__wirelength__iter:29": 3284455, - "detailedroute__route__wirelength__iter:3": 3284349, - "detailedroute__route__wirelength__iter:30": 3284455, - "detailedroute__route__wirelength__iter:31": 3284455, - "detailedroute__route__wirelength__iter:32": 3284455, - "detailedroute__route__wirelength__iter:33": 3284455, - "detailedroute__route__wirelength__iter:34": 3284455, - "detailedroute__route__wirelength__iter:35": 3284455, - "detailedroute__route__wirelength__iter:36": 3284455, - "detailedroute__route__wirelength__iter:37": 3284455, - "detailedroute__route__wirelength__iter:38": 3284455, - "detailedroute__route__wirelength__iter:39": 3284455, - "detailedroute__route__wirelength__iter:4": 3284462, - "detailedroute__route__wirelength__iter:40": 3284455, - "detailedroute__route__wirelength__iter:41": 3284455, - "detailedroute__route__wirelength__iter:42": 3284455, - "detailedroute__route__wirelength__iter:43": 3284455, - "detailedroute__route__wirelength__iter:44": 3284455, - "detailedroute__route__wirelength__iter:45": 3284455, - "detailedroute__route__wirelength__iter:46": 3284455, - "detailedroute__route__wirelength__iter:47": 3284455, - "detailedroute__route__wirelength__iter:48": 3284455, - "detailedroute__route__wirelength__iter:49": 3284456, - "detailedroute__route__wirelength__iter:5": 3284458, - "detailedroute__route__wirelength__iter:6": 3284455, - "detailedroute__route__wirelength__iter:7": 3284455, - "detailedroute__route__wirelength__iter:8": 3284456, - "detailedroute__route__wirelength__iter:9": 3284455, - "finish__clock__skew__hold": 1512.12, - "finish__clock__skew__setup": 1803.74, - "finish__cpu__total": 432.38, - "finish__design__core__area": 436018, - "finish__design__die__area": 510000, - "finish__design__instance__area": 205464, - "finish__design__instance__area__class:clock_buffer": 1935.7, - "finish__design__instance__area__class:clock_inverter": 172.247, - "finish__design__instance__area__class:inverter": 578.624, - "finish__design__instance__area__class:macro": 112562, - "finish__design__instance__area__class:multi_input_combinational_cell": 46778.9, - "finish__design__instance__area__class:sequential_cell": 19223.3, - "finish__design__instance__area__class:tie_cell": 1176.89, - "finish__design__instance__area__class:timing_repair_buffer": 10422, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 112562, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 92901.3, - "finish__design__instance__count": 206367, - "finish__design__instance__count__class:clock_buffer": 1140, - "finish__design__instance__count__class:clock_inverter": 410, - "finish__design__instance__count__class:inverter": 2506, - "finish__design__instance__count__class:macro": 37, - "finish__design__instance__count__class:multi_input_combinational_cell": 137941, - "finish__design__instance__count__class:sequential_cell": 20681, - "finish__design__instance__count__class:tie_cell": 6081, - "finish__design__instance__count__class:timing_repair_buffer": 16588, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 37, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 206330, - "finish__design__instance__utilization": 0.471228, - "finish__design__instance__utilization__stdcell": 0.287215, - "finish__design__io": 495, - "finish__design__rows": 6589, - "finish__design__rows:sc9mcpp84_12lp": 6589, - "finish__design__sites": 6289833, - "finish__design__sites:sc9mcpp84_12lp": 6289833, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 3599012.0, - "finish__power__internal__total": 0.0533936, - "finish__power__leakage__total": 0.0013205, - "finish__power__switching__total": 0.0450426, - "finish__power__total": 0.0997567, - "finish__runtime__total": "7:17.24", - "finish__timing__drv__hold_violation_count": 1, - "finish__timing__drv__max_cap": 1, - "finish__timing__drv__max_cap_limit": -0.021764, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0971252, - "finish__timing__drv__setup_violation_count": 2, - "finish__timing__setup__tns": -547.895, - "finish__timing__setup__ws": -296.42, - "finish__timing__wns_percent_delay": -16.500591, - "finish_merge__cpu__total": 29.46, - "finish_merge__mem__peak": 2418800.0, - "finish_merge__runtime__total": "0:39.38", - "floorplan__cpu__total": 88.0, - "floorplan__design__core__area": 436018, - "floorplan__design__die__area": 510000, - "floorplan__design__instance__area": 166258, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 109364, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 56893.7, - "floorplan__design__instance__count": 161128, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__macros": 37, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__stdcell": 161091, - "floorplan__design__instance__utilization": 0.38131, - "floorplan__design__instance__utilization__stdcell": 0.174171, - "floorplan__design__io": 495, - "floorplan__design__rows": 1023, - "floorplan__design__rows:sc9mcpp84_12lp": 1023, - "floorplan__design__sites": 9011607, - "floorplan__design__sites:sc9mcpp84_12lp": 9011607, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 1182360.0, - "floorplan__power__internal__total": 0.0406089, - "floorplan__power__leakage__total": 0.00121688, - "floorplan__power__switching__total": 0.012297, - "floorplan__power__total": 0.0541228, - "floorplan__runtime__total": "1:32.21", - "floorplan__timing__setup__tns": -458981000.0, - "floorplan__timing__setup__ws": -24833.7, - "floorplan_io__cpu__total": 4.17, - "floorplan_io__mem__peak": 678120.0, - "floorplan_io__runtime__total": "0:05.00", - "floorplan_macro__cpu__total": 862.17, - "floorplan_macro__mem__peak": 1291676.0, - "floorplan_macro__runtime__total": "3:44.93", - "floorplan_pdn__cpu__total": 30.74, - "floorplan_pdn__mem__peak": 1133932.0, - "floorplan_pdn__runtime__total": "0:31.96", - "floorplan_tap__cpu__total": 4.31, - "floorplan_tap__mem__peak": 593140.0, - "floorplan_tap__runtime__total": "0:05.28", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1772.48, - "globalplace__design__core__area": 436018, - "globalplace__design__die__area": 510000, - "globalplace__design__instance__area": 199510, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 112562, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 86947.4, - "globalplace__design__instance__count": 194534, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 37, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 194497, - "globalplace__design__instance__utilization": 0.457572, - "globalplace__design__instance__utilization__stdcell": 0.268808, - "globalplace__design__io": 495, - "globalplace__design__rows": 6589, - "globalplace__design__rows:sc9mcpp84_12lp": 6589, - "globalplace__design__sites": 6289833, - "globalplace__design__sites:sc9mcpp84_12lp": 6289833, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 3509580.0, - "globalplace__power__internal__total": 0.0408131, - "globalplace__power__leakage__total": 0.00124047, - "globalplace__power__switching__total": 0.0353542, - "globalplace__power__total": 0.0774078, - "globalplace__runtime__total": "13:34.36", - "globalplace__timing__setup__tns": -4420810.0, - "globalplace__timing__setup__ws": -1804.13, - "globalplace_io__cpu__total": 4.38, - "globalplace_io__mem__peak": 738176.0, - "globalplace_io__runtime__total": "0:05.38", - "globalplace_skip_io__cpu__total": 421.93, - "globalplace_skip_io__mem__peak": 1018392.0, - "globalplace_skip_io__runtime__total": "0:59.79", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 1494.46, - "globalroute__clock__skew__setup": 1798.38, - "globalroute__cpu__total": 1448.69, - "globalroute__design__core__area": 436018, - "globalroute__design__die__area": 510000, - "globalroute__design__instance__area": 205464, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 112562, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 92901.3, - "globalroute__design__instance__count": 206367, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 4, - "globalroute__design__instance__count__macros": 37, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 1, - "globalroute__design__instance__count__stdcell": 206330, - "globalroute__design__instance__displacement__max": 1.164, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 19.716, - "globalroute__design__instance__utilization": 0.471228, - "globalroute__design__instance__utilization__stdcell": 0.287215, - "globalroute__design__io": 495, - "globalroute__design__rows": 6589, - "globalroute__design__rows:sc9mcpp84_12lp": 6589, - "globalroute__design__sites": 6289833, - "globalroute__design__sites:sc9mcpp84_12lp": 6289833, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 6, - "globalroute__mem__peak": 7066420.0, - "globalroute__power__internal__total": 0.0541531, - "globalroute__power__leakage__total": 0.0013205, - "globalroute__power__switching__total": 0.0467218, - "globalroute__power__total": 0.102195, - "globalroute__route__wirelength__estimated": 2779360.0, - "globalroute__runtime__total": "11:42.48", - "globalroute__timing__clock__slack": -331.515, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0743075, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 1, - "globalroute__timing__drv__max_slew_limit": -0.0867818, - "globalroute__timing__drv__setup_violation_count": 219, - "globalroute__timing__setup__tns": -2871.97, - "globalroute__timing__setup__ws": -331.515, - "placeopt__cpu__total": 169.47, - "placeopt__design__core__area": 436018, - "placeopt__design__die__area": 510000, - "placeopt__design__instance__area": 202965, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 112562, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 90402.7, - "placeopt__design__instance__count": 203886, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 37, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 203849, - "placeopt__design__instance__utilization": 0.465497, - "placeopt__design__instance__utilization__stdcell": 0.279491, - "placeopt__design__io": 495, - "placeopt__design__rows": 6589, - "placeopt__design__rows:sc9mcpp84_12lp": 6589, - "placeopt__design__sites": 6289833, - "placeopt__design__sites:sc9mcpp84_12lp": 6289833, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 2147588.0, - "placeopt__power__internal__total": 0.0413542, - "placeopt__power__leakage__total": 0.00124275, - "placeopt__power__switching__total": 0.0356727, - "placeopt__power__total": 0.0782697, - "placeopt__runtime__total": "2:51.13", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 148, - "placeopt__timing__drv__hold_violation_count": 502, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.122765, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 9.86865e-05, - "placeopt__timing__drv__setup_violation_count": 3867, - "placeopt__timing__setup__tns": -1983520.0, - "placeopt__timing__setup__ws": -871.665, - "run__flow__design": "ariane", - "run__flow__generate_date": "2024-11-23 01:01", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "ec7293db19147fc6f53f724975d2e7f587635c34", - "run__flow__uuid": "5445e416-51e4-434c-97c6-325a0960c5f6", - "run__flow__variant": "base", - "synth__cpu__total": 663.58, - "synth__design__instance__area__stdcell": 170170.864322, - "synth__design__instance__count__stdcell": 180817.0, - "synth__mem__peak": 785800.0, - "synth__runtime__total": "11:07.94", - "total_time": "2:04:32.270000" -} \ No newline at end of file diff --git a/flow/designs/gf12/ariane/rules-base.json b/flow/designs/gf12/ariane/rules-base.json index ae13348b97..3c43ec8b2d 100644 --- a/flow/designs/gf12/ariane/rules-base.json +++ b/flow/designs/gf12/ariane/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 226890, + "value": 226083, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3529763, + "value": 3662425, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -446.42, + "value": -212.42, "compare": ">=" }, "finish__design__instance__area": { - "value": 228909, + "value": 228519, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -29.8, + "value": -14.79, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ariane133/ariane.sdc b/flow/designs/gf12/ariane133/ariane.sdc index 254b6d12e9..4ddcb37965 100644 --- a/flow/designs/gf12/ariane133/ariane.sdc +++ b/flow/designs/gf12/ariane133/ariane.sdc @@ -6,6 +6,6 @@ set_units -time 1ps # Set the current design current_design ariane -create_clock -name "core_clock" -period 1800.0 -waveform {0.0 900.0} [get_ports clk_i] -set_clock_gating_check -setup 0.0 +create_clock -name "core_clock" -period 1300.0 -waveform {0.0 900.0} [get_ports clk_i] +set_clock_gating_check -setup 0.0 set_wire_load_mode "top" diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk index fb084b725a..28c9649cd7 100644 --- a/flow/designs/gf12/ariane133/config.mk +++ b/flow/designs/gf12/ariane133/config.mk @@ -3,9 +3,7 @@ export DESIGN_NAME = ariane export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 10000 -# -# RTL_MP Settings +export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v @@ -14,15 +12,15 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2 +export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2 \ + $(PLATFORM_DIR)/gds/gf12_1rw_256x16.gds2 export DIE_AREA = 0 0 900 750 export CORE_AREA = 5 5 895 745 -export PLACE_PINS_ARGS = -exclude left:0-200 -exclude left:500-700 -exclude right:* -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 export PLACE_DENSITY_LB_ADDON = 0.05 @@ -31,3 +29,5 @@ export DESIGN_TYPE = CELL else export DESIGN_TYPE = CELL_NODEN endif + +export REMOVE_ABC_BUFFERS = 1 diff --git a/flow/designs/gf12/ariane133/io.tcl b/flow/designs/gf12/ariane133/io.tcl new file mode 100644 index 0000000000..6ac9789e72 --- /dev/null +++ b/flow/designs/gf12/ariane133/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/ariane133/metadata-base-ok.json b/flow/designs/gf12/ariane133/metadata-base-ok.json deleted file mode 100644 index 42b9d7d312..0000000000 --- a/flow/designs/gf12/ariane133/metadata-base-ok.json +++ /dev/null @@ -1,279 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1800.0000" - ], - "cts__clock__skew__hold": 118.505, - "cts__clock__skew__hold__post_repair": 118.03, - "cts__clock__skew__hold__pre_repair": 123.489, - "cts__clock__skew__setup": 74.8793, - "cts__clock__skew__setup__post_repair": 73.8451, - "cts__clock__skew__setup__pre_repair": 72.5419, - "cts__design__core__area": 658153, - "cts__design__core__area__post_repair": 658153, - "cts__design__core__area__pre_repair": 658153, - "cts__design__die__area": 675000, - "cts__design__die__area__post_repair": 675000, - "cts__design__die__area__pre_repair": 675000, - "cts__design__instance__area": 262439, - "cts__design__instance__area__macros": 183106, - "cts__design__instance__area__macros__post_repair": 183106, - "cts__design__instance__area__macros__pre_repair": 183106, - "cts__design__instance__area__post_repair": 262438, - "cts__design__instance__area__pre_repair": 262427, - "cts__design__instance__area__stdcell": 79332.6, - "cts__design__instance__area__stdcell__post_repair": 79332.2, - "cts__design__instance__area__stdcell__pre_repair": 79320.8, - "cts__design__instance__count": 148353, - "cts__design__instance__count__hold_buffer": 2.0, - "cts__design__instance__count__macros": 133, - "cts__design__instance__count__macros__post_repair": 133, - "cts__design__instance__count__macros__pre_repair": 133, - "cts__design__instance__count__post_repair": 148351, - "cts__design__instance__count__pre_repair": 148333, - "cts__design__instance__count__setup_buffer": 18.0, - "cts__design__instance__count__stdcell": 148220, - "cts__design__instance__count__stdcell__post_repair": 148218, - "cts__design__instance__count__stdcell__pre_repair": 148200, - "cts__design__instance__displacement__max": 0.89, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 1.3155, - "cts__design__instance__utilization": 0.39875, - "cts__design__instance__utilization__post_repair": 0.39875, - "cts__design__instance__utilization__pre_repair": 0.398732, - "cts__design__instance__utilization__stdcell": 0.167, - "cts__design__instance__utilization__stdcell__post_repair": 0.166999, - "cts__design__instance__utilization__stdcell__pre_repair": 0.166975, - "cts__design__io": 495, - "cts__design__io__post_repair": 495, - "cts__design__io__pre_repair": 495, - "cts__design__violations": 0, - "cts__route__wirelength__estimated": 3059250.0, - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 3, - "cts__timing__drv__hold_violation_count__pre_repair": 4, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.00956105, - "cts__timing__drv__max_cap_limit__post_repair": 0.0072233, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0072233, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 24, - "cts__timing__drv__max_slew__post_repair": 42, - "cts__timing__drv__max_slew__pre_repair": 43, - "cts__timing__drv__max_slew_limit": -0.0867308, - "cts__timing__drv__max_slew_limit__post_repair": -0.0616032, - "cts__timing__drv__max_slew_limit__pre_repair": -0.165984, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 13, - "cts__timing__drv__setup_violation_count__pre_repair": 13, - "cts__timing__setup__tns": 0, - "cts__timing__setup__tns__post_repair": -135.707, - "cts__timing__setup__tns__pre_repair": -135.707, - "cts__timing__setup__ws": 0.168532, - "cts__timing__setup__ws__post_repair": -13.2918, - "cts__timing__setup__ws__pre_repair": -13.2918, - "detailedplace__cpu__total": 98.95, - "detailedplace__design__core__area": 658153, - "detailedplace__design__die__area": 675000, - "detailedplace__design__instance__area": 261946, - "detailedplace__design__instance__area__macros": 183106, - "detailedplace__design__instance__area__stdcell": 78839.5, - "detailedplace__design__instance__count": 147504, - "detailedplace__design__instance__count__macros": 133, - "detailedplace__design__instance__count__stdcell": 147371, - "detailedplace__design__instance__displacement__max": 22.5865, - "detailedplace__design__instance__displacement__mean": 0.5275, - "detailedplace__design__instance__displacement__total": 78263.3, - "detailedplace__design__instance__utilization": 0.398001, - "detailedplace__design__instance__utilization__stdcell": 0.165961, - "detailedplace__design__io": 495, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 1654680.0, - "detailedplace__route__wirelength__estimated": 3068260.0, - "detailedplace__runtime__total": "1:41.85", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0072233, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 42, - "detailedplace__timing__drv__max_slew_limit": -0.0616032, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 4.8368, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 166038, - "detailedroute__route__drc_errors__iter:2": 49049, - "detailedroute__route__drc_errors__iter:3": 42723, - "detailedroute__route__drc_errors__iter:4": 687, - "detailedroute__route__drc_errors__iter:5": 52, - "detailedroute__route__drc_errors__iter:6": 14, - "detailedroute__route__drc_errors__iter:7": 4, - "detailedroute__route__drc_errors__iter:8": 0, - "detailedroute__route__net": 114415, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1446527, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1446527, - "detailedroute__route__wirelength": 3473073, - "detailedroute__route__wirelength__iter:1": 3486654, - "detailedroute__route__wirelength__iter:2": 3477645, - "detailedroute__route__wirelength__iter:3": 3473008, - "detailedroute__route__wirelength__iter:4": 3473159, - "detailedroute__route__wirelength__iter:5": 3473084, - "detailedroute__route__wirelength__iter:6": 3473080, - "detailedroute__route__wirelength__iter:7": 3473069, - "detailedroute__route__wirelength__iter:8": 3473073, - "finish__clock__skew__hold": 105.599, - "finish__clock__skew__setup": 78.9035, - "finish__cpu__total": 509.56, - "finish__design__core__area": 658153, - "finish__design__die__area": 675000, - "finish__design__instance__area": 262439, - "finish__design__instance__area__macros": 183106, - "finish__design__instance__area__stdcell": 79332.6, - "finish__design__instance__count": 148353, - "finish__design__instance__count__macros": 133, - "finish__design__instance__count__stdcell": 148220, - "finish__design__instance__utilization": 0.39875, - "finish__design__instance__utilization__stdcell": 0.167, - "finish__design__io": 495, - "finish__mem__peak": 3993488.0, - "finish__runtime__total": "8:37.39", - "finish__timing__drv__hold_violation_count": 1.0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0111176, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0277372, - "finish__timing__drv__setup_violation_count": 0.0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 348.468, - "finish__timing__wns_percent_delay": 19.966873, - "floorplan__cpu__total": 1001.74, - "floorplan__design__core__area": 658153, - "floorplan__design__die__area": 675000, - "floorplan__design__instance__area": 223350, - "floorplan__design__instance__area__macros": 183106, - "floorplan__design__instance__area__stdcell": 40243.9, - "floorplan__design__instance__count": 94347, - "floorplan__design__instance__count__macros": 133, - "floorplan__design__instance__count__stdcell": 94214, - "floorplan__design__instance__utilization": 0.339359, - "floorplan__design__instance__utilization__stdcell": 0.0847156, - "floorplan__design__io": 495, - "floorplan__mem__peak": 1677968.0, - "floorplan__runtime__total": "3:07.78", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 605.561, - "globalplace__cpu__total": 110.97, - "globalplace__design__core__area": 658153, - "globalplace__design__die__area": 675000, - "globalplace__design__instance__area": 246773, - "globalplace__design__instance__area__macros": 183106, - "globalplace__design__instance__area__stdcell": 63667, - "globalplace__design__instance__count": 132010, - "globalplace__design__instance__count__macros": 133, - "globalplace__design__instance__count__stdcell": 131877, - "globalplace__design__instance__utilization": 0.374948, - "globalplace__design__instance__utilization__stdcell": 0.134023, - "globalplace__design__io": 495, - "globalplace__mem__peak": 1319576.0, - "globalplace__runtime__total": "1:53.59", - "globalplace__timing__setup__tns": -5380470.0, - "globalplace__timing__setup__ws": -2856.85, - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 135.709, - "globalroute__clock__skew__setup": 88.1873, - "globalroute__design__core__area": 658153, - "globalroute__design__die__area": 675000, - "globalroute__design__instance__area": 262439, - "globalroute__design__instance__area__macros": 183106, - "globalroute__design__instance__area__stdcell": 79332.6, - "globalroute__design__instance__count": 148353, - "globalroute__design__instance__count__macros": 133, - "globalroute__design__instance__count__stdcell": 148220, - "globalroute__design__instance__utilization": 0.39875, - "globalroute__design__instance__utilization__stdcell": 0.167, - "globalroute__design__io": 495, - "globalroute__timing__clock__slack": 149.998, - "globalroute__timing__drv__hold_violation_count": 1, - "globalroute__timing__drv__max_cap": 1, - "globalroute__timing__drv__max_cap_limit": -0.0317674, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 36, - "globalroute__timing__drv__max_slew_limit": -0.802608, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 149.998, - "placeopt__cpu__total": 110.97, - "placeopt__design__core__area": 658153, - "placeopt__design__core__area__pre_opt": 658153, - "placeopt__design__die__area": 675000, - "placeopt__design__die__area__pre_opt": 675000, - "placeopt__design__instance__area": 261946, - "placeopt__design__instance__area__macros": 183106, - "placeopt__design__instance__area__macros__pre_opt": 183106, - "placeopt__design__instance__area__pre_opt": 246773, - "placeopt__design__instance__area__stdcell": 78839.5, - "placeopt__design__instance__area__stdcell__pre_opt": 63667, - "placeopt__design__instance__count": 147504, - "placeopt__design__instance__count__macros": 133, - "placeopt__design__instance__count__macros__pre_opt": 133, - "placeopt__design__instance__count__pre_opt": 132010, - "placeopt__design__instance__count__stdcell": 147371, - "placeopt__design__instance__count__stdcell__pre_opt": 131877, - "placeopt__design__instance__utilization": 0.398001, - "placeopt__design__instance__utilization__pre_opt": 0.374948, - "placeopt__design__instance__utilization__stdcell": 0.165961, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.134023, - "placeopt__design__io": 495, - "placeopt__design__io__pre_opt": 495, - "placeopt__mem__peak": 1319576.0, - "placeopt__runtime__total": "1:53.59", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0235099, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.00831026, - "placeopt__timing__drv__setup_violation_count": 33, - "placeopt__timing__setup__tns": -1026.21, - "placeopt__timing__setup__tns__pre_opt": -5380470.0, - "placeopt__timing__setup__ws": -62.3841, - "placeopt__timing__setup__ws__pre_opt": -2856.85, - "run__flow__design": "ariane133", - "run__flow__generate_date": "2023-05-18 15:50", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-8159-g4cb463080", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "422575641a0b65fd13a7f96a80d6f51a1749b732", - "run__flow__scripts_commit": "1bb696e8b7a5dc3d22726c9ee1418ce53520ca18", - "run__flow__uuid": "85c2470a-9c65-407f-877b-49834204760e", - "run__flow__variant": "base", - "synth__cpu__total": 172.14, - "synth__design__instance__area__stdcell": 223902.943388, - "synth__design__instance__count__stdcell": 96800.0, - "synth__mem__peak": 1616700.0, - "synth__runtime__total": "2:54.69", - "total_time": "0:20:08.890000" -} \ No newline at end of file diff --git a/flow/designs/gf12/ariane133/rules-base.json b/flow/designs/gf12/ariane133/rules-base.json index 1408a182fa..2f8ee67d4f 100644 --- a/flow/designs/gf12/ariane133/rules-base.json +++ b/flow/designs/gf12/ariane133/rules-base.json @@ -27,16 +27,28 @@ "value": 14737, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 3994034, + "value": 3846017, "compare": "<=" }, "detailedroute__route__drc_errors": { "value": 0, "compare": "<=" }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -112.74, "compare": ">=" }, "finish__design__instance__area": { @@ -48,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 101, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/bp_dual/config.mk b/flow/designs/gf12/bp_dual/config.mk index 4d6b9b04bf..3f3e20af00 100644 --- a/flow/designs/gf12/bp_dual/config.mk +++ b/flow/designs/gf12/bp_dual/config.mk @@ -15,9 +15,9 @@ export RTLMP_FENCE_LY ?= 700 export RTLMP_FENCE_UX ?= 2450 export RTLMP_FENCE_UY ?= 2300 +export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.sv2v.v \ $(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v -export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc @@ -51,20 +51,18 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \ export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds +export FOOTPRINT_TCL = $(PLATFORM_DIR)/bp/footprint.tcl -#Package Strategy for pad placement -export FOOTPRINT = $(PLATFORM_DIR)/bp/bsg_bp_dual.package.strategy -export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap +export DIE_AREA = 0 0 3000 3000 +export CORE_AREA = 200 200 2800 2800 export ABC_CLOCK_PERIOD_IN_PS = 1250 export TNS_END_PERCENT = 0 -export PLACE_DENSITY = 0.55 +export PLACE_DENSITY = 0.50 export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl -# Define macro halo and channel spacings export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 diff --git a/flow/designs/intel22/aes/rules-base.json b/flow/designs/gf12/bp_dual/rules-base.json similarity index 68% rename from flow/designs/intel22/aes/rules-base.json rename to flow/designs/gf12/bp_dual/rules-base.json index 902831e3f2..1162a465ff 100644 --- a/flow/designs/intel22/aes/rules-base.json +++ b/flow/designs/gf12/bp_dual/rules-base.json @@ -1,18 +1,14 @@ { - "synth__design__instance__area__stdcell": { - "value": 9122.16, - "compare": "<=" - }, "constraints__clocks__count": { - "value": 1, + "value": 8, "compare": "==" }, "placeopt__design__instance__area": { - "value": 13961, + "value": 959122, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19022, + "value": 975165, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,31 +16,43 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1808, + "value": 84797, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1654, + "value": 84797, + "compare": "<=" + }, + "globalroute__antenna_diodes_count": { + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 484892, + "value": 14955489, "compare": "<=" }, "detailedroute__route__drc_errors": { "value": 0, "compare": "<=" }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": -76.88, + "value": -280.69, "compare": ">=" }, "finish__design__instance__area": { - "value": 16941, + "value": 977391, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 827, + "value": 42398, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -52,7 +60,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.72, + "value": -20.74, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/bp_quad/config.mk b/flow/designs/gf12/bp_quad/config.mk index 9f756213fc..5846c209b3 100644 --- a/flow/designs/gf12/bp_quad/config.mk +++ b/flow/designs/gf12/bp_quad/config.mk @@ -3,13 +3,25 @@ export DESIGN_NAME = bsg_chip export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 1000 +# +# RTL_MP Settings +export RTLMP_MAX_INST = 30000 +export RTLMP_MIN_INST = 10000 +export RTLMP_MAX_MACRO = 24 +export RTLMP_MIN_MACRO = 4 +# +export RTLMP_FENCE_LX ?= 700 +export RTLMP_FENCE_LY ?= 700 +export RTLMP_FENCE_UX ?= 2450 +export RTLMP_FENCE_UY ?= 2300 -export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/yosys/bp_quad_yosys_netlist.v -export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/rtl/bsg_chip_block.sv2v.v +export SYNTH_MINIMUM_KEEP_SIZE ?= 1000 +export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.sv2v.v \ + $(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v +export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/yosys/bp_quad_hier_yosys_netlist.v -export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/sdc/bsg_chip.sdc +export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.elab.v.sdc export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \ $(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \ @@ -18,6 +30,9 @@ export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \ $(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \ $(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \ + $(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef + export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ $(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ $(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ @@ -25,6 +40,7 @@ export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0 $(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ $(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib +export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \ $(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \ @@ -37,16 +53,18 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \ export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds -export DIE_AREA = 0 0 1800 1800 -export CORE_AREA = 5 5 1795 1795 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-800 -exclude bottom:1200-1800 +export FOOTPRINT_TCL = $(PLATFORM_DIR)/bp/footprint.tcl + +export DIE_AREA = 0 0 3000 3000 +export CORE_AREA = 200 200 2800 2800 + +export ABC_CLOCK_PERIOD_IN_PS = 1250 -export PLACE_DENSITY_LB_ADDON = 0.02 +export TNS_END_PERCENT = 0 +export PLACE_DENSITY = 0.40 export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl -# Define macro halo and channel spacings -export MACRO_PLACE_HALO = 5 5 -export MACRO_PLACE_CHANNEL = 10 10 +export MACRO_PLACE_HALO = 7 7 diff --git a/flow/designs/gf12/bp_quad/rules-base.json b/flow/designs/gf12/bp_quad/rules-base.json new file mode 100644 index 0000000000..4fe8d184e1 --- /dev/null +++ b/flow/designs/gf12/bp_quad/rules-base.json @@ -0,0 +1,66 @@ +{ + "constraints__clocks__count": { + "value": 8, + "compare": "==" + }, + "placeopt__design__instance__area": { + "value": 1579306, + "compare": "<=" + }, + "placeopt__design__instance__count__stdcell": { + "value": 1442363, + "compare": "<=" + }, + "detailedplace__design__violations": { + "value": 0, + "compare": "==" + }, + "cts__design__instance__count__setup_buffer": { + "value": 125423, + "compare": "<=" + }, + "cts__design__instance__count__hold_buffer": { + "value": 125423, + "compare": "<=" + }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, + "detailedroute__route__wirelength": { + "value": 25903866, + "compare": "<=" + }, + "detailedroute__route__drc_errors": { + "value": 3, + "compare": "<=" + }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, + "finish__timing__setup__ws": { + "value": -239.22, + "compare": ">=" + }, + "finish__design__instance__area": { + "value": 1610080, + "compare": "<=" + }, + "finish__timing__drv__setup_violation_count": { + "value": 62711, + "compare": "<=" + }, + "finish__timing__drv__hold_violation_count": { + "value": 170, + "compare": "<=" + }, + "finish__timing__wns_percent_delay": { + "value": -10.96, + "compare": ">=" + } +} \ No newline at end of file diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index 8a9a24d646..53f9f1d165 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -41,24 +41,21 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \ export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds +export FOOTPRINT_TCL = $(PLATFORM_DIR)/bp/footprint.tcl -export FOOTPRINT = $(PLATFORM_DIR)/bp/bsg_bp_single.package.strategy -export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap - -# These values must be multiples of placement site -# export DIE_AREA = -# export CORE_AREA = +export DIE_AREA = 0 0 3000 3000 +export CORE_AREA = 200 200 2800 2800 export ABC_CLOCK_PERIOD_IN_PS = 1250 export PLACE_DENSITY = 0.80 export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl -#export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/bp_single.macro_placment.cfg -#export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/auto_bp_single.macro_placment.cfg -export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/auto_fence2_bp_single.macro_placment.cfg - -export MACRO_BLOCKAGE_HALO = 25 +export RTLMP_FENCE_LX = 606.44 +export RTLMP_FENCE_LY = 896.44 +export RTLMP_FENCE_UX = 2449.96 +export RTLMP_FENCE_UY = 2239.96 +export MACRO_PLACE_HALO = 28.2 28.2 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl diff --git a/flow/designs/gf12/bp_single/config_mpl2.mk b/flow/designs/gf12/bp_single/config_mpl2.mk deleted file mode 100644 index 30139844f7..0000000000 --- a/flow/designs/gf12/bp_single/config_mpl2.mk +++ /dev/null @@ -1,77 +0,0 @@ -export DESIGN_NICKNAME = bp_single -export DESIGN_NAME = bsg_chip -export PLATFORM = gf12 - -export SKIP_GATE_CLONING = 1 -export TNS_END_PERCENT = 5 - -export SYNTH_HIERARCHICAL = 1 -# -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 10000 -export RTLMP_MAX_MACRO = 24 -export RTLMP_MIN_MACRO = 4 -# -export RTLMP_FENCE_LX ?= 900 -export RTLMP_FENCE_LY ?= 1300 -export RTLMP_FENCE_UX ?= 2350 -export RTLMP_FENCE_UY ?= 2500 - -#netlist -export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yosys/bp_single_hier_yosys_netlist.v \ - $(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v -export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yosys/bp_single_hier_yosys_netlist.v - -export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/bsg_chip.elab.v.sdc - -export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \ - $(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \ - $(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \ - $(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \ - $(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \ - $(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \ - $(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef - -export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ - $(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ - $(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ - $(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ - $(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \ - $(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib - -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib - -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \ - $(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \ - $(PLATFORM_DIR)/gds/gf12_1rw_d256_w48_m2.gds2 \ - $(PLATFORM_DIR)/gds/gf12_1rw_d512_w64_m2_byte.gds2 \ - $(PLATFORM_DIR)/gds/gf12_1rw_d64_w124_m2_bit.gds2 \ - $(PLATFORM_DIR)/gds/gf12_1rw_d64_w62_m2_bit.gds2 \ - $(PLATFORM_DIR)/gds/IN12LP_GPIO18_13M9S30P.gds \ - $(PLATFORM_DIR)/gds/GoLd_LN14_CDMM_32xxx.gds.gz - -export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds - - -export FOOTPRINT ?= $(PLATFORM_DIR)/bp/bsg_bp_single.package.strategy -export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap - -export ABC_CLOCK_PERIOD_IN_PS = 1250 - -export PLACE_DENSITY = 0.55 -export TNS_END_PERCENT = 0 - -export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl - -export PDN_TCL ?= $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl - -export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 - -export DESIGN_TYPE = CHIP - -# enable slack margin for setup and hold fix after CTS -export SETUP_SLACK_MARGIN ?= 100 diff --git a/flow/designs/gf12/bp_single/fastroute.tcl b/flow/designs/gf12/bp_single/fastroute.tcl index 91d3b4162f..69e55f9f90 100644 --- a/flow/designs/gf12/bp_single/fastroute.tcl +++ b/flow/designs/gf12/bp_single/fastroute.tcl @@ -3,7 +3,5 @@ set_global_routing_layer_adjustment M3 0.6 set_global_routing_layer_adjustment C4-C5 0.5 set_global_routing_layer_adjustment K1-K4 0.45 -set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) - -set_macro_extension 1 - +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) \ + -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/bp_single/metadata-base-ok.json b/flow/designs/gf12/bp_single/metadata-base-ok.json deleted file mode 100644 index 06332ebd4f..0000000000 --- a/flow/designs/gf12/bp_single/metadata-base-ok.json +++ /dev/null @@ -1,359 +0,0 @@ -{ - "constraints__clocks__count": 8, - "constraints__clocks__details": [ - "bp_clk: 2000.0000", - "io_master_clk: 1666.0000", - "router_clk: 1666.0000", - "sdi_a_clk: 3332.0000", - "sdi_b_clk: 3332.0000", - "sdo_a_tkn_clk: 3332.0000", - "sdo_b_tkn_clk: 3332.0000", - "tag_clk: 6666.0000" - ], - "cts__clock__skew__hold": 487.28, - "cts__clock__skew__setup": 353.905, - "cts__cpu__total": 5469.26, - "cts__design__core__area": 6758590.0, - "cts__design__die__area": 9000000.0, - "cts__design__instance__area": 480784, - "cts__design__instance__area__macros": 192994, - "cts__design__instance__area__stdcell": 287790, - "cts__design__instance__count": 500879, - "cts__design__instance__count__hold_buffer": 31, - "cts__design__instance__count__macros": 53, - "cts__design__instance__count__setup_buffer": 13, - "cts__design__instance__count__stdcell": 499813, - "cts__design__instance__displacement__max": 17.868, - "cts__design__instance__displacement__mean": 0.006, - "cts__design__instance__displacement__total": 3085.85, - "cts__design__instance__utilization": 0.0711368, - "cts__design__instance__utilization__stdcell": 0.0438331, - "cts__design__io": 141, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 24, - "cts__mem__peak": 23852948.0, - "cts__power__internal__total": 0.250471, - "cts__power__leakage__total": 0.000605115, - "cts__power__switching__total": 0.0641791, - "cts__power__total": 0.315255, - "cts__route__wirelength__estimated": 6028260.0, - "cts__runtime__total": "1:31:49", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 30, - "cts__timing__drv__max_slew": 31, - "cts__timing__drv__max_slew_limit": -2.13468, - "cts__timing__drv__setup_violation_count": 2570, - "cts__timing__setup__tns": -523776, - "cts__timing__setup__ws": -600.158, - "design__io__hpwl": 0, - "design__violations": 0, - "detailedplace__cpu__total": 496.46, - "detailedplace__design__core__area": 6758590.0, - "detailedplace__design__die__area": 9000000.0, - "detailedplace__design__instance__area": 472635, - "detailedplace__design__instance__area__macros": 192994, - "detailedplace__design__instance__area__stdcell": 279641, - "detailedplace__design__instance__count": 495160, - "detailedplace__design__instance__count__macros": 53, - "detailedplace__design__instance__count__stdcell": 494094, - "detailedplace__design__instance__displacement__max": 41.0695, - "detailedplace__design__instance__displacement__mean": 0.8175, - "detailedplace__design__instance__displacement__total": 404662, - "detailedplace__design__instance__utilization": 0.069931, - "detailedplace__design__instance__utilization__stdcell": 0.0425919, - "detailedplace__design__io": 141, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 22277300.0, - "detailedplace__power__internal__total": 0.177054, - "detailedplace__power__leakage__total": 0.00031251, - "detailedplace__power__switching__total": 0.0305717, - "detailedplace__power__total": 0.207938, - "detailedplace__route__wirelength__estimated": 5789460.0, - "detailedplace__runtime__total": "8:37.42", - "detailedplace__timing__drv__hold_violation_count": 32, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 30, - "detailedplace__timing__drv__max_slew": 24, - "detailedplace__timing__drv__max_slew_limit": -2.12043, - "detailedplace__timing__drv__setup_violation_count": 2359, - "detailedplace__timing__setup__tns": -246174, - "detailedplace__timing__setup__ws": -926.669, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 146, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 259568, - "detailedroute__route__drc_errors__iter:10": 4, - "detailedroute__route__drc_errors__iter:11": 4, - "detailedroute__route__drc_errors__iter:12": 4, - "detailedroute__route__drc_errors__iter:13": 4, - "detailedroute__route__drc_errors__iter:14": 4, - "detailedroute__route__drc_errors__iter:15": 4, - "detailedroute__route__drc_errors__iter:16": 4, - "detailedroute__route__drc_errors__iter:17": 4, - "detailedroute__route__drc_errors__iter:18": 4, - "detailedroute__route__drc_errors__iter:19": 4, - "detailedroute__route__drc_errors__iter:2": 20674, - "detailedroute__route__drc_errors__iter:20": 0, - "detailedroute__route__drc_errors__iter:3": 14396, - "detailedroute__route__drc_errors__iter:4": 327, - "detailedroute__route__drc_errors__iter:5": 44, - "detailedroute__route__drc_errors__iter:6": 10, - "detailedroute__route__drc_errors__iter:7": 4, - "detailedroute__route__drc_errors__iter:8": 4, - "detailedroute__route__drc_errors__iter:9": 4, - "detailedroute__route__net": 357137, - "detailedroute__route__net__special": 204, - "detailedroute__route__vias": 3829796, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3829796, - "detailedroute__route__wirelength": 6837756, - "detailedroute__route__wirelength__iter:1": 6867064, - "detailedroute__route__wirelength__iter:10": 6837758, - "detailedroute__route__wirelength__iter:11": 6837758, - "detailedroute__route__wirelength__iter:12": 6837758, - "detailedroute__route__wirelength__iter:13": 6837758, - "detailedroute__route__wirelength__iter:14": 6837758, - "detailedroute__route__wirelength__iter:15": 6837758, - "detailedroute__route__wirelength__iter:16": 6837758, - "detailedroute__route__wirelength__iter:17": 6837758, - "detailedroute__route__wirelength__iter:18": 6837756, - "detailedroute__route__wirelength__iter:19": 6837756, - "detailedroute__route__wirelength__iter:2": 6843993, - "detailedroute__route__wirelength__iter:20": 6837756, - "detailedroute__route__wirelength__iter:3": 6837683, - "detailedroute__route__wirelength__iter:4": 6837763, - "detailedroute__route__wirelength__iter:5": 6837758, - "detailedroute__route__wirelength__iter:6": 6837757, - "detailedroute__route__wirelength__iter:7": 6837758, - "detailedroute__route__wirelength__iter:8": 6837758, - "detailedroute__route__wirelength__iter:9": 6837758, - "finish__clock__skew__hold": 390.299, - "finish__clock__skew__setup": 278.229, - "finish__cpu__total": 1169.83, - "finish__design__core__area": 6758590.0, - "finish__design__die__area": 9000000.0, - "finish__design__instance__area": 481160, - "finish__design__instance__area__macros": 192994, - "finish__design__instance__area__stdcell": 288166, - "finish__design__instance__count": 502168, - "finish__design__instance__count__class:buffer": 27455, - "finish__design__instance__count__class:clock_buffer": 4415, - "finish__design__instance__count__class:clock_inverter": 1262, - "finish__design__instance__count__class:cover": 269, - "finish__design__instance__count__class:endcap_cell": 24804, - "finish__design__instance__count__class:fill_cell": 1902738, - "finish__design__instance__count__class:inverter": 716, - "finish__design__instance__count__class:macro": 53, - "finish__design__instance__count__class:multi_input_combinational_cell": 213400, - "finish__design__instance__count__class:pad": 311, - "finish__design__instance__count__class:pad_spacer": 433, - "finish__design__instance__count__class:sequential_cell": 83958, - "finish__design__instance__count__class:tap_cell": 120432, - "finish__design__instance__count__class:tie_cell": 1928, - "finish__design__instance__count__class:timing_repair_buffer": 22732, - "finish__design__instance__count__macros": 53, - "finish__design__instance__count__stdcell": 501102, - "finish__design__instance__utilization": 0.0711924, - "finish__design__instance__utilization__stdcell": 0.0438903, - "finish__design__io": 141, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 10365716.0, - "finish__power__internal__total": 0.250675, - "finish__power__leakage__total": 0.000605402, - "finish__power__switching__total": 0.0636178, - "finish__power__total": 0.314899, - "finish__runtime__total": "19:50.42", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 10, - "finish__timing__drv__max_cap_limit": -0.753223, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 30, - "finish__timing__drv__max_slew": 19, - "finish__timing__drv__max_slew_limit": -0.842267, - "finish__timing__drv__setup_violation_count": 12, - "finish__timing__setup__tns": -1077.03, - "finish__timing__setup__ws": -155.8, - "finish__timing__wns_percent_delay": -7.692963, - "finish_merge__cpu__total": 272.03, - "finish_merge__mem__peak": 8153824.0, - "finish_merge__runtime__total": "4:47.16", - "floorplan__cpu__total": 1770.79, - "floorplan__design__core__area": 6758590.0, - "floorplan__design__die__area": 9000000.0, - "floorplan__design__instance__area": 325203, - "floorplan__design__instance__area__macros": 188565, - "floorplan__design__instance__area__stdcell": 136639, - "floorplan__design__instance__count": 333250, - "floorplan__design__instance__count__hold_buffer": 6651, - "floorplan__design__instance__count__macros": 53, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 332184, - "floorplan__design__instance__utilization": 0.0481171, - "floorplan__design__instance__utilization__stdcell": 0.0207973, - "floorplan__design__io": 0, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 27, - "floorplan__mem__peak": 1894640.0, - "floorplan__power__internal__total": 0.176888, - "floorplan__power__leakage__total": 0.00024962, - "floorplan__power__switching__total": 0.0305742, - "floorplan__power__total": 0.207712, - "floorplan__runtime__total": "29:36.63", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 71.9931, - "floorplan_io__cpu__total": 7.33, - "floorplan_io__mem__peak": 1164824.0, - "floorplan_io__runtime__total": "0:08.91", - "floorplan_macro__cpu__total": 9.2, - "floorplan_macro__mem__peak": 1165920.0, - "floorplan_macro__runtime__total": "0:11.08", - "floorplan_pdn__cpu__total": 1893.31, - "floorplan_pdn__mem__peak": 4187972.0, - "floorplan_pdn__runtime__total": "31:39.95", - "floorplan_tap__cpu__total": 7.76, - "floorplan_tap__mem__peak": 1066324.0, - "floorplan_tap__runtime__total": "0:09.21", - "floorplan_tdms__cpu__total": 0.16, - "floorplan_tdms__mem__peak": 110700.0, - "floorplan_tdms__runtime__total": "0:00.38", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 6461.75, - "globalplace__design__core__area": 6758590.0, - "globalplace__design__die__area": 9000000.0, - "globalplace__design__instance__area": 409940, - "globalplace__design__instance__area__macros": 192994, - "globalplace__design__instance__area__stdcell": 216946, - "globalplace__design__instance__count": 478486, - "globalplace__design__instance__count__macros": 53, - "globalplace__design__instance__count__stdcell": 477420, - "globalplace__design__instance__utilization": 0.0606548, - "globalplace__design__instance__utilization__stdcell": 0.0330429, - "globalplace__design__io": 141, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 14385832.0, - "globalplace__power__internal__total": 0.176888, - "globalplace__power__leakage__total": 0.00024962, - "globalplace__power__switching__total": 0.0305742, - "globalplace__power__total": 0.207712, - "globalplace__runtime__total": "1:26:54", - "globalplace__timing__setup__tns": -46835800.0, - "globalplace__timing__setup__ws": -10622, - "globalplace_io__cpu__total": 11.7, - "globalplace_io__mem__peak": 1775484.0, - "globalplace_io__runtime__total": "0:14.30", - "globalplace_skip_io__cpu__total": 4602.42, - "globalplace_skip_io__mem__peak": 4295616.0, - "globalplace_skip_io__runtime__total": "1:00:06", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 521.375, - "globalroute__clock__skew__setup": 385.917, - "globalroute__cpu__total": 7391.07, - "globalroute__design__core__area": 6758590.0, - "globalroute__design__die__area": 9000000.0, - "globalroute__design__instance__area": 481160, - "globalroute__design__instance__area__macros": 192994, - "globalroute__design__instance__area__stdcell": 288166, - "globalroute__design__instance__count": 502168, - "globalroute__design__instance__count__hold_buffer": 561, - "globalroute__design__instance__count__macros": 53, - "globalroute__design__instance__count__setup_buffer": 4, - "globalroute__design__instance__count__stdcell": 501102, - "globalroute__design__instance__displacement__max": 7.896, - "globalroute__design__instance__displacement__mean": 0.0015, - "globalroute__design__instance__displacement__total": 973.632, - "globalroute__design__instance__utilization": 0.0711924, - "globalroute__design__instance__utilization__stdcell": 0.0438903, - "globalroute__design__io": 141, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 4, - "globalroute__mem__peak": 40507912.0, - "globalroute__power__internal__total": 0.254775, - "globalroute__power__leakage__total": 0.000605402, - "globalroute__power__switching__total": 0.0668992, - "globalroute__power__total": 0.32228, - "globalroute__route__wirelength__estimated": 6043890.0, - "globalroute__runtime__total": "1:51:59", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 3, - "globalroute__timing__drv__max_cap": 7, - "globalroute__timing__drv__max_cap_limit": -0.811832, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 30, - "globalroute__timing__drv__max_slew": 38, - "globalroute__timing__drv__max_slew_limit": -1.5278, - "globalroute__timing__drv__setup_violation_count": 1210, - "globalroute__timing__setup__tns": -155571, - "globalroute__timing__setup__ws": -583.327, - "placeopt__cpu__total": 367.0, - "placeopt__design__core__area": 6758590.0, - "placeopt__design__die__area": 9000000.0, - "placeopt__design__instance__area": 472635, - "placeopt__design__instance__area__macros": 192994, - "placeopt__design__instance__area__stdcell": 279641, - "placeopt__design__instance__count": 495160, - "placeopt__design__instance__count__macros": 53, - "placeopt__design__instance__count__stdcell": 494094, - "placeopt__design__instance__utilization": 0.069931, - "placeopt__design__instance__utilization__stdcell": 0.0425919, - "placeopt__design__io": 141, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 3708300.0, - "placeopt__power__internal__total": 0.177054, - "placeopt__power__leakage__total": 0.00031251, - "placeopt__power__switching__total": 0.0305717, - "placeopt__power__total": 0.207938, - "placeopt__runtime__total": "6:12.83", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 52, - "placeopt__timing__drv__hold_violation_count": 32, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 30, - "placeopt__timing__drv__max_slew": 16, - "placeopt__timing__drv__max_slew_limit": -2.03297, - "placeopt__timing__drv__setup_violation_count": 2163, - "placeopt__timing__setup__tns": -210538, - "placeopt__timing__setup__ws": -928.777, - "run__flow__design": "bp_single", - "run__flow__generate_date": "2024-10-16 16:04", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16507-gd0e17f1a2", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "a1b4fd76ff7096a9ac49a5c403d9de6e238999ac", - "run__flow__uuid": "1c2a342e-ca9b-4a14-9c16-0d3238340db1", - "run__flow__variant": "base", - "synth__cpu__total": 206.21, - "synth__design__instance__area__stdcell": 890888.070911, - "synth__design__instance__count__stdcell": 325717.0, - "synth__mem__peak": 1937244.0, - "synth__runtime__total": "3:30.97", - "total_time": "7:35:47.260000" -} \ No newline at end of file diff --git a/flow/designs/gf12/bp_single/rules-base.json b/flow/designs/gf12/bp_single/rules-base.json index f86b4257e8..791e7fb2f0 100644 --- a/flow/designs/gf12/bp_single/rules-base.json +++ b/flow/designs/gf12/bp_single/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 535113, + "value": 491017, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 546190, + "value": 535708, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 47495, + "value": 46583, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 7863419, + "value": 6200511, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -255.8, + "value": -97.15, "compare": ">=" }, "finish__design__instance__area": { - "value": 538136, + "value": 497627, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 23747, + "value": 23292, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 108, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.6, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf12/ca53/config.mk b/flow/designs/gf12/ca53/config.mk index 01798462da..c867e3c6a5 100644 --- a/flow/designs/gf12/ca53/config.mk +++ b/flow/designs/gf12/ca53/config.mk @@ -3,7 +3,7 @@ export PLATFORM = gf12 export VERILOG_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v -export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v +export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc @@ -48,15 +48,14 @@ export DIE_AREA = 0 0 1400 1400 export CORE_AREA = 10 10 1390 1390 export PLACE_DENSITY_LB_ADDON = 0.05 -export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1350-1400 -exclude right:* -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/ca53/io.tcl export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 -export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl +export MACRO_WRAPPERS = $(DESIGN_DIR)/wrappers.tcl #export MAX_ROUTING_LAYER = H2 -export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl +export FASTROUTE_TCL = $(DESIGN_DIR)/fastroute.tcl # ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf12/ca53/fastroute.tcl b/flow/designs/gf12/ca53/fastroute.tcl index 78b39516da..7b9941dfdb 100644 --- a/flow/designs/gf12/ca53/fastroute.tcl +++ b/flow/designs/gf12/ca53/fastroute.tcl @@ -3,5 +3,4 @@ set_global_routing_layer_adjustment M3 0.5 set_global_routing_layer_adjustment C4-K4 0.5 #set_global_routing_layer_adjustment H1-H2 0.5 -set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) -set_macro_extension 2 +set_routing_layers -signal M2-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/gf12/ca53/io.tcl b/flow/designs/gf12/ca53/io.tcl new file mode 100644 index 0000000000..89e27e2ff6 --- /dev/null +++ b/flow/designs/gf12/ca53/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/gf12/ca53/metadata-base-ok.json b/flow/designs/gf12/ca53/metadata-base-ok.json deleted file mode 100644 index dcb7094abb..0000000000 --- a/flow/designs/gf12/ca53/metadata-base-ok.json +++ /dev/null @@ -1,348 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 2000.0000" - ], - "cts__clock__skew__hold": 687.931, - "cts__clock__skew__setup": 525.727, - "cts__cpu__total": 3551.92, - "cts__design__core__area": 1903560.0, - "cts__design__die__area": 1960000.0, - "cts__design__instance__area": 375864, - "cts__design__instance__area__macros": 132563, - "cts__design__instance__area__stdcell": 243301, - "cts__design__instance__count": 546465, - "cts__design__instance__count__hold_buffer": 6776, - "cts__design__instance__count__macros": 25, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 546440, - "cts__design__instance__displacement__max": 16.184, - "cts__design__instance__displacement__mean": 0.006, - "cts__design__instance__displacement__total": 3327.79, - "cts__design__instance__utilization": 0.197454, - "cts__design__instance__utilization__stdcell": 0.137381, - "cts__design__io": 1352, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 7669288.0, - "cts__power__internal__total": 0.111718, - "cts__power__leakage__total": 0.00129898, - "cts__power__switching__total": 0.194476, - "cts__power__total": 0.307492, - "cts__route__wirelength__estimated": 12743200.0, - "cts__runtime__total": "59:18.38", - "cts__timing__drv__hold_violation_count": 1, - "cts__timing__drv__max_cap": 4, - "cts__timing__drv__max_cap_limit": -0.861673, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 583, - "cts__timing__drv__max_slew_limit": -2.32903, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 142.252, - "design__io__hpwl": 1451716073, - "design__violations": 0, - "detailedplace__cpu__total": 1109.56, - "detailedplace__design__core__area": 1903560.0, - "detailedplace__design__die__area": 1960000.0, - "detailedplace__design__instance__area": 373233, - "detailedplace__design__instance__area__macros": 132563, - "detailedplace__design__instance__area__stdcell": 240670, - "detailedplace__design__instance__count": 537773, - "detailedplace__design__instance__count__macros": 25, - "detailedplace__design__instance__count__stdcell": 537748, - "detailedplace__design__instance__displacement__max": 38.516, - "detailedplace__design__instance__displacement__mean": 0.298, - "detailedplace__design__instance__displacement__total": 160490, - "detailedplace__design__instance__utilization": 0.196071, - "detailedplace__design__instance__utilization__stdcell": 0.135896, - "detailedplace__design__io": 1352, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 5025820.0, - "detailedplace__power__internal__total": 0.105728, - "detailedplace__power__leakage__total": 0.00126501, - "detailedplace__power__switching__total": 0.186542, - "detailedplace__power__total": 0.293536, - "detailedplace__route__wirelength__estimated": 12972400.0, - "detailedplace__runtime__total": "18:34.75", - "detailedplace__timing__drv__hold_violation_count": 2, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0436063, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 68, - "detailedplace__timing__drv__max_slew_limit": -0.207773, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 107.966, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 74, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 376621, - "detailedroute__route__drc_errors__iter:10": 46, - "detailedroute__route__drc_errors__iter:11": 26, - "detailedroute__route__drc_errors__iter:12": 21, - "detailedroute__route__drc_errors__iter:13": 20, - "detailedroute__route__drc_errors__iter:14": 19, - "detailedroute__route__drc_errors__iter:15": 16, - "detailedroute__route__drc_errors__iter:16": 16, - "detailedroute__route__drc_errors__iter:17": 16, - "detailedroute__route__drc_errors__iter:18": 24, - "detailedroute__route__drc_errors__iter:19": 11, - "detailedroute__route__drc_errors__iter:2": 37636, - "detailedroute__route__drc_errors__iter:20": 10, - "detailedroute__route__drc_errors__iter:21": 10, - "detailedroute__route__drc_errors__iter:22": 8, - "detailedroute__route__drc_errors__iter:23": 8, - "detailedroute__route__drc_errors__iter:24": 4, - "detailedroute__route__drc_errors__iter:25": 4, - "detailedroute__route__drc_errors__iter:26": 7, - "detailedroute__route__drc_errors__iter:27": 2, - "detailedroute__route__drc_errors__iter:28": 2, - "detailedroute__route__drc_errors__iter:29": 2, - "detailedroute__route__drc_errors__iter:3": 24083, - "detailedroute__route__drc_errors__iter:30": 0, - "detailedroute__route__drc_errors__iter:4": 1822, - "detailedroute__route__drc_errors__iter:5": 389, - "detailedroute__route__drc_errors__iter:6": 193, - "detailedroute__route__drc_errors__iter:7": 95, - "detailedroute__route__drc_errors__iter:8": 73, - "detailedroute__route__drc_errors__iter:9": 59, - "detailedroute__route__net": 503938, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 6329602, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 6329602, - "detailedroute__route__wirelength": 14726684, - "detailedroute__route__wirelength__iter:1": 14771987, - "detailedroute__route__wirelength__iter:10": 14726683, - "detailedroute__route__wirelength__iter:11": 14726683, - "detailedroute__route__wirelength__iter:12": 14726684, - "detailedroute__route__wirelength__iter:13": 14726683, - "detailedroute__route__wirelength__iter:14": 14726684, - "detailedroute__route__wirelength__iter:15": 14726683, - "detailedroute__route__wirelength__iter:16": 14726683, - "detailedroute__route__wirelength__iter:17": 14726683, - "detailedroute__route__wirelength__iter:18": 14726680, - "detailedroute__route__wirelength__iter:19": 14726685, - "detailedroute__route__wirelength__iter:2": 14733256, - "detailedroute__route__wirelength__iter:20": 14726685, - "detailedroute__route__wirelength__iter:21": 14726684, - "detailedroute__route__wirelength__iter:22": 14726683, - "detailedroute__route__wirelength__iter:23": 14726683, - "detailedroute__route__wirelength__iter:24": 14726684, - "detailedroute__route__wirelength__iter:25": 14726684, - "detailedroute__route__wirelength__iter:26": 14726684, - "detailedroute__route__wirelength__iter:27": 14726684, - "detailedroute__route__wirelength__iter:28": 14726684, - "detailedroute__route__wirelength__iter:29": 14726684, - "detailedroute__route__wirelength__iter:3": 14725629, - "detailedroute__route__wirelength__iter:30": 14726684, - "detailedroute__route__wirelength__iter:4": 14726625, - "detailedroute__route__wirelength__iter:5": 14726647, - "detailedroute__route__wirelength__iter:6": 14726670, - "detailedroute__route__wirelength__iter:7": 14726682, - "detailedroute__route__wirelength__iter:8": 14726682, - "detailedroute__route__wirelength__iter:9": 14726685, - "finish__clock__skew__hold": 625.32, - "finish__clock__skew__setup": 488.232, - "finish__cpu__total": 2207.86, - "finish__design__core__area": 1903560.0, - "finish__design__die__area": 1960000.0, - "finish__design__instance__area": 375864, - "finish__design__instance__area__macros": 132563, - "finish__design__instance__area__stdcell": 243301, - "finish__design__instance__count": 546465, - "finish__design__instance__count__macros": 25, - "finish__design__instance__count__stdcell": 546440, - "finish__design__instance__utilization": 0.197454, - "finish__design__instance__utilization__stdcell": 0.137381, - "finish__design__io": 1352, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 11318240.0, - "finish__power__internal__total": 0.109384, - "finish__power__leakage__total": 0.00129898, - "finish__power__switching__total": 0.18839, - "finish__power__total": 0.299073, - "finish__runtime__total": "37:03.34", - "finish__timing__drv__hold_violation_count": 4088, - "finish__timing__drv__max_cap": 3, - "finish__timing__drv__max_cap_limit": -0.821554, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 389, - "finish__timing__drv__max_slew_limit": -4.07217, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 602.527, - "finish__timing__wns_percent_delay": 35.108091, - "finish_merge__cpu__total": 211.34, - "finish_merge__mem__peak": 7343444.0, - "finish_merge__runtime__total": "3:47.42", - "floorplan__cpu__total": 531.27, - "floorplan__design__core__area": 1903560.0, - "floorplan__design__die__area": 1960000.0, - "floorplan__design__instance__area": 282285, - "floorplan__design__instance__area__macros": 129970, - "floorplan__design__instance__area__stdcell": 152315, - "floorplan__design__instance__count": 449880, - "floorplan__design__instance__count__hold_buffer": 4997, - "floorplan__design__instance__count__macros": 25, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 449855, - "floorplan__design__instance__utilization": 0.148294, - "floorplan__design__instance__utilization__stdcell": 0.0858799, - "floorplan__design__io": 1352, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 21, - "floorplan__mem__peak": 2738692.0, - "floorplan__power__internal__total": 0.074303, - "floorplan__power__leakage__total": 0.000335495, - "floorplan__power__switching__total": 0.0582502, - "floorplan__power__total": 0.132889, - "floorplan__runtime__total": "8:57.82", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 1107.86, - "floorplan_io__cpu__total": 7.57, - "floorplan_io__mem__peak": 1318532.0, - "floorplan_io__runtime__total": "0:09.65", - "floorplan_macro__cpu__total": 916.76, - "floorplan_macro__mem__peak": 3033988.0, - "floorplan_macro__runtime__total": "2:33.07", - "floorplan_pdn__cpu__total": 263.85, - "floorplan_pdn__mem__peak": 2091820.0, - "floorplan_pdn__runtime__total": "4:26.60", - "floorplan_tap__cpu__total": 59.89, - "floorplan_tap__mem__peak": 1102772.0, - "floorplan_tap__runtime__total": "1:01.97", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 5304.01, - "globalplace__design__core__area": 1903560.0, - "globalplace__design__die__area": 1960000.0, - "globalplace__design__instance__area": 311723, - "globalplace__design__instance__area__macros": 132563, - "globalplace__design__instance__area__stdcell": 179160, - "globalplace__design__instance__count": 497241, - "globalplace__design__instance__count__macros": 25, - "globalplace__design__instance__count__stdcell": 497216, - "globalplace__design__instance__utilization": 0.163758, - "globalplace__design__instance__utilization__stdcell": 0.101164, - "globalplace__design__io": 1352, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 9475528.0, - "globalplace__power__internal__total": 0.190752, - "globalplace__power__leakage__total": 0.000335495, - "globalplace__power__switching__total": 0.172082, - "globalplace__power__total": 0.363169, - "globalplace__runtime__total": "1:09:48", - "globalplace__timing__setup__tns": -280339000.0, - "globalplace__timing__setup__ws": -73770.5, - "globalplace_io__cpu__total": 8.61, - "globalplace_io__mem__peak": 1524232.0, - "globalplace_io__runtime__total": "0:10.93", - "globalplace_skip_io__cpu__total": 746.22, - "globalplace_skip_io__mem__peak": 2920388.0, - "globalplace_skip_io__runtime__total": "3:37.60", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 725.486, - "globalroute__clock__skew__setup": 550.531, - "globalroute__cpu__total": 9400.53, - "globalroute__design__core__area": 1903560.0, - "globalroute__design__die__area": 1960000.0, - "globalroute__design__instance__area": 375864, - "globalroute__design__instance__area__macros": 132563, - "globalroute__design__instance__area__stdcell": 243301, - "globalroute__design__instance__count": 546465, - "globalroute__design__instance__count__macros": 25, - "globalroute__design__instance__count__stdcell": 546440, - "globalroute__design__instance__utilization": 0.197454, - "globalroute__design__instance__utilization__stdcell": 0.137381, - "globalroute__design__io": 1352, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 47529988.0, - "globalroute__power__internal__total": 0.111807, - "globalroute__power__leakage__total": 0.00129898, - "globalroute__power__switching__total": 0.201603, - "globalroute__power__total": 0.314709, - "globalroute__runtime__total": "1:15:37", - "globalroute__timing__clock__slack": 244.456, - "globalroute__timing__drv__hold_violation_count": 1461, - "globalroute__timing__drv__max_cap": 4, - "globalroute__timing__drv__max_cap_limit": -0.924885, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 1745, - "globalroute__timing__drv__max_slew_limit": -1.44982, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 244.456, - "placeopt__cpu__total": 921.04, - "placeopt__design__core__area": 1903560.0, - "placeopt__design__die__area": 1960000.0, - "placeopt__design__instance__area": 373233, - "placeopt__design__instance__area__macros": 132563, - "placeopt__design__instance__area__stdcell": 240670, - "placeopt__design__instance__count": 537773, - "placeopt__design__instance__count__macros": 25, - "placeopt__design__instance__count__stdcell": 537748, - "placeopt__design__instance__utilization": 0.196071, - "placeopt__design__instance__utilization__stdcell": 0.135896, - "placeopt__design__io": 1352, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 5391020.0, - "placeopt__power__internal__total": 0.10583, - "placeopt__power__leakage__total": 0.00126501, - "placeopt__power__switching__total": 0.189522, - "placeopt__power__total": 0.296618, - "placeopt__runtime__total": "15:26.40", - "placeopt__timing__drv__floating__nets": 34, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.034224, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 13, - "placeopt__timing__drv__max_slew_limit": -0.250829, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 101.446, - "run__flow__design": "ca53_cpu", - "run__flow__generate_date": "2024-09-19 21:22", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "abe50750-2458-4eac-b250-80786df6d0d6", - "run__flow__variant": "base", - "synth__cpu__total": 0.0, - "synth__design__instance__area__stdcell": "ERR", - "synth__design__instance__count__stdcell": "ERR", - "synth__mem__peak": 12800.0, - "synth__runtime__total": "0:00.25", - "total_time": "5:00:33.180000" -} \ No newline at end of file diff --git a/flow/designs/gf12/ca53/rules-base.json b/flow/designs/gf12/ca53/rules-base.json index 6f1e37e918..15b92b85b6 100644 --- a/flow/designs/gf12/ca53/rules-base.json +++ b/flow/designs/gf12/ca53/rules-base.json @@ -40,7 +40,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk index db5c537c5c..c801e198ec 100644 --- a/flow/designs/gf12/coyote/config.mk +++ b/flow/designs/gf12/coyote/config.mk @@ -29,7 +29,7 @@ export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.t export DIE_AREA = 0 0 752 752 export CORE_AREA = 2 2 750 750 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-20 -exclude bottom:450-750 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc index a27541fdcd..b110ae09d5 100644 --- a/flow/designs/gf12/coyote/constraint.sdc +++ b/flow/designs/gf12/coyote/constraint.sdc @@ -11,813 +11,1616 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T42.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T79.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.data.T9.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem0.macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f.rocket.RocketTile.dcache.meta.tag_arr.mem.macro_mem1.macro_mem0}] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/constraint_hier.sdc b/flow/designs/gf12/coyote/constraint_hier.sdc index 19f548615f..3ca86c77ea 100644 --- a/flow/designs/gf12/coyote/constraint_hier.sdc +++ b/flow/designs/gf12/coyote/constraint_hier.sdc @@ -11,813 +11,1616 @@ set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] +set_input_delay 2000 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] +set_output_delay 200 \ + -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] +set_disable_timing -from {CLKA} -to {CLKB} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_disable_timing -from {CLKB} -to {CLKA} \ + [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] +set_false_path \ + -to [list [get_ports {rocc_ctrl_o_exception_}] \ + [get_ports {rocc_ctrl_o_host_id_}] \ + [get_ports {rocc_ctrl_o_s_}]] ############################################################################### # Environment ############################################################################### diff --git a/flow/designs/gf12/coyote/io.tcl b/flow/designs/gf12/coyote/io.tcl new file mode 100644 index 0000000000..0154d2704c --- /dev/null +++ b/flow/designs/gf12/coyote/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-20 -region bottom:450-750 diff --git a/flow/designs/gf12/coyote/metadata-base-ok.json b/flow/designs/gf12/coyote/metadata-base-ok.json deleted file mode 100644 index 8740fec4a4..0000000000 --- a/flow/designs/gf12/coyote/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clk: 4000.0000" - ], - "cts__clock__skew__hold": 469.675, - "cts__clock__skew__setup": 605.715, - "cts__cpu__total": 376.36, - "cts__design__core__area": 559193, - "cts__design__die__area": 565504, - "cts__design__instance__area": 192706, - "cts__design__instance__area__macros": 68723.7, - "cts__design__instance__area__stdcell": 123983, - "cts__design__instance__count": 338892, - "cts__design__instance__count__hold_buffer": 3254, - "cts__design__instance__count__macros": 15, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 338877, - "cts__design__instance__displacement__max": 24.4215, - "cts__design__instance__displacement__mean": 0.0175, - "cts__design__instance__displacement__total": 5993.46, - "cts__design__instance__utilization": 0.344615, - "cts__design__instance__utilization__stdcell": 0.252784, - "cts__design__io": 784, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 2, - "cts__mem__peak": 3436220.0, - "cts__power__internal__total": 0.0802539, - "cts__power__leakage__total": 0.000299422, - "cts__power__switching__total": 0.0673698, - "cts__power__total": 0.147923, - "cts__route__wirelength__estimated": 4202280.0, - "cts__runtime__total": "6:19.35", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.874429, - "cts__timing__drv__max_fanout": 1684, - "cts__timing__drv__max_fanout_limit": 10, - "cts__timing__drv__max_slew": 473, - "cts__timing__drv__max_slew_limit": -9.63498, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 596.407, - "design__io__hpwl": 327121019, - "design__violations": 0, - "detailedplace__cpu__total": 295.3, - "detailedplace__design__core__area": 559193, - "detailedplace__design__die__area": 565504, - "detailedplace__design__instance__area": 187522, - "detailedplace__design__instance__area__macros": 68723.7, - "detailedplace__design__instance__area__stdcell": 118798, - "detailedplace__design__instance__count": 332291, - "detailedplace__design__instance__count__macros": 15, - "detailedplace__design__instance__count__stdcell": 332276, - "detailedplace__design__instance__displacement__max": 24.7305, - "detailedplace__design__instance__displacement__mean": 0.3765, - "detailedplace__design__instance__displacement__total": 125329, - "detailedplace__design__instance__utilization": 0.335344, - "detailedplace__design__instance__utilization__stdcell": 0.242214, - "detailedplace__design__io": 784, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 2277912.0, - "detailedplace__power__internal__total": 0.0595809, - "detailedplace__power__leakage__total": 0.000136681, - "detailedplace__power__switching__total": 0.0533736, - "detailedplace__power__total": 0.113091, - "detailedplace__route__wirelength__estimated": 4178510.0, - "detailedplace__runtime__total": "4:57.48", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.874429, - "detailedplace__timing__drv__max_fanout": 5, - "detailedplace__timing__drv__max_fanout_limit": 10, - "detailedplace__timing__drv__max_slew": 463, - "detailedplace__timing__drv__max_slew_limit": -4.50904, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 877.297, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 153543, - "detailedroute__route__drc_errors__iter:2": 8020, - "detailedroute__route__drc_errors__iter:3": 3531, - "detailedroute__route__drc_errors__iter:4": 62, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 2, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 320103, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2846386, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2846386, - "detailedroute__route__wirelength": 4680485, - "detailedroute__route__wirelength__iter:1": 4706317, - "detailedroute__route__wirelength__iter:2": 4683207, - "detailedroute__route__wirelength__iter:3": 4680482, - "detailedroute__route__wirelength__iter:4": 4680494, - "detailedroute__route__wirelength__iter:5": 4680486, - "detailedroute__route__wirelength__iter:6": 4680485, - "detailedroute__route__wirelength__iter:7": 4680485, - "detailedroute__route__wirelength__iter:8": 4680485, - "detailedroute__route__wirelength__iter:9": 4680485, - "finish__clock__skew__hold": 145.302, - "finish__clock__skew__setup": 317.062, - "finish__cpu__total": 420.04, - "finish__design__core__area": 559193, - "finish__design__die__area": 565504, - "finish__design__instance__area": 192733, - "finish__design__instance__area__macros": 68723.7, - "finish__design__instance__area__stdcell": 124009, - "finish__design__instance__count": 338994, - "finish__design__instance__count__macros": 15, - "finish__design__instance__count__stdcell": 338979, - "finish__design__instance__utilization": 0.344663, - "finish__design__instance__utilization__stdcell": 0.252838, - "finish__design__io": 784, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 5339536.0, - "finish__power__internal__total": 0.0804869, - "finish__power__leakage__total": 0.000299453, - "finish__power__switching__total": 0.0660109, - "finish__power__total": 0.146797, - "finish__runtime__total": "7:06.99", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.86023, - "finish__timing__drv__max_fanout": 1684, - "finish__timing__drv__max_fanout_limit": 10, - "finish__timing__drv__max_slew": 3, - "finish__timing__drv__max_slew_limit": -0.830192, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 732.015, - "finish__timing__wns_percent_delay": 68.541693, - "finish_merge__cpu__total": 57.65, - "finish_merge__mem__peak": 3725340.0, - "finish_merge__runtime__total": "1:10.87", - "floorplan__cpu__total": 136.46, - "floorplan__design__core__area": 559193, - "floorplan__design__die__area": 565504, - "floorplan__design__instance__area": 150234, - "floorplan__design__instance__area__macros": 67079.7, - "floorplan__design__instance__area__stdcell": 83154.1, - "floorplan__design__instance__count": 300369, - "floorplan__design__instance__count__hold_buffer": 2329, - "floorplan__design__instance__count__macros": 15, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 300354, - "floorplan__design__instance__utilization": 0.268662, - "floorplan__design__instance__utilization__stdcell": 0.168974, - "floorplan__design__io": 784, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 1525532.0, - "floorplan__power__internal__total": 0.0464161, - "floorplan__power__leakage__total": 0.000108175, - "floorplan__power__switching__total": 0.0131406, - "floorplan__power__total": 0.0596649, - "floorplan__runtime__total": "2:21.70", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 1267.85, - "floorplan_io__cpu__total": 4.9, - "floorplan_io__mem__peak": 889552.0, - "floorplan_io__runtime__total": "0:06.14", - "floorplan_macro__cpu__total": 13.19, - "floorplan_macro__mem__peak": 1439868.0, - "floorplan_macro__runtime__total": "0:14.80", - "floorplan_pdn__cpu__total": 43.95, - "floorplan_pdn__mem__peak": 1136512.0, - "floorplan_pdn__runtime__total": "0:45.57", - "floorplan_tap__cpu__total": 21.4, - "floorplan_tap__mem__peak": 705112.0, - "floorplan_tap__runtime__total": "0:22.80", - "floorplan_tdms__cpu__total": 781.37, - "floorplan_tdms__mem__peak": 1482484.0, - "floorplan_tdms__runtime__total": "1:48.98", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1814.51, - "globalplace__design__core__area": 559193, - "globalplace__design__die__area": 565504, - "globalplace__design__instance__area": 162824, - "globalplace__design__instance__area__macros": 68723.7, - "globalplace__design__instance__area__stdcell": 94100.7, - "globalplace__design__instance__count": 319191, - "globalplace__design__instance__count__macros": 15, - "globalplace__design__instance__count__stdcell": 319176, - "globalplace__design__instance__utilization": 0.291178, - "globalplace__design__instance__utilization__stdcell": 0.191859, - "globalplace__design__io": 784, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 4360304.0, - "globalplace__power__internal__total": 0.0471402, - "globalplace__power__leakage__total": 0.000108175, - "globalplace__power__switching__total": 0.0453604, - "globalplace__power__total": 0.0926087, - "globalplace__runtime__total": "15:09.24", - "globalplace__timing__setup__tns": -70297.6, - "globalplace__timing__setup__ws": -1581.18, - "globalplace_io__cpu__total": 5.22, - "globalplace_io__mem__peak": 946648.0, - "globalplace_io__runtime__total": "0:06.59", - "globalplace_skip_io__cpu__total": 411.84, - "globalplace_skip_io__mem__peak": 1299340.0, - "globalplace_skip_io__runtime__total": "1:06.72", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 195.051, - "globalroute__clock__skew__setup": 347.067, - "globalroute__cpu__total": 1226.12, - "globalroute__design__core__area": 559193, - "globalroute__design__die__area": 565504, - "globalroute__design__instance__area": 192733, - "globalroute__design__instance__area__macros": 68723.7, - "globalroute__design__instance__area__stdcell": 124009, - "globalroute__design__instance__count": 338994, - "globalroute__design__instance__count__hold_buffer": 23, - "globalroute__design__instance__count__macros": 15, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 338979, - "globalroute__design__instance__displacement__max": 1.332, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 13.092, - "globalroute__design__instance__utilization": 0.344663, - "globalroute__design__instance__utilization__stdcell": 0.252838, - "globalroute__design__io": 784, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 8027864.0, - "globalroute__power__internal__total": 0.081766, - "globalroute__power__leakage__total": 0.000299453, - "globalroute__power__switching__total": 0.0704805, - "globalroute__power__total": 0.152546, - "globalroute__route__wirelength__estimated": 4203060.0, - "globalroute__runtime__total": "8:50.81", - "globalroute__timing__clock__slack": 620.104, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.867153, - "globalroute__timing__drv__max_fanout": 1684, - "globalroute__timing__drv__max_fanout_limit": 10, - "globalroute__timing__drv__max_slew": 11, - "globalroute__timing__drv__max_slew_limit": -2.0805, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 620.104, - "placeopt__cpu__total": 234.36, - "placeopt__design__core__area": 559193, - "placeopt__design__die__area": 565504, - "placeopt__design__instance__area": 187522, - "placeopt__design__instance__area__macros": 68723.7, - "placeopt__design__instance__area__stdcell": 118798, - "placeopt__design__instance__count": 332291, - "placeopt__design__instance__count__macros": 15, - "placeopt__design__instance__count__stdcell": 332276, - "placeopt__design__instance__utilization": 0.335344, - "placeopt__design__instance__utilization__stdcell": 0.242214, - "placeopt__design__io": 784, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 2665440.0, - "placeopt__power__internal__total": 0.0595781, - "placeopt__power__leakage__total": 0.000136681, - "placeopt__power__switching__total": 0.0534284, - "placeopt__power__total": 0.113143, - "placeopt__runtime__total": "3:56.87", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 30, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.880901, - "placeopt__timing__drv__max_fanout": 5, - "placeopt__timing__drv__max_fanout_limit": 10, - "placeopt__timing__drv__max_slew": 398, - "placeopt__timing__drv__max_slew_limit": -4.5538, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 805.034, - "run__flow__design": "coyote", - "run__flow__generate_date": "2024-09-19 16:06", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "14f51fcc-07d4-4ba9-b10a-1d31f5fa9493", - "run__flow__variant": "base", - "synth__cpu__total": 3066.51, - "synth__design__instance__area__stdcell": 149782.718178, - "synth__design__instance__count__stdcell": 298040.0, - "synth__mem__peak": 5009484.0, - "synth__runtime__total": "51:14.47", - "total_time": "1:45:39.380000" -} \ No newline at end of file diff --git a/flow/designs/gf12/coyote/rules-base.json b/flow/designs/gf12/coyote/rules-base.json index 2740624625..8359e8a556 100644 --- a/flow/designs/gf12/coyote/rules-base.json +++ b/flow/designs/gf12/coyote/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 214239, + "value": 213956, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,11 +32,11 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4929050, + "value": 5678019, "compare": "<=" }, "detailedroute__route__drc_errors": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna__violating__nets": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 266, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc index e1df1eb91a..d7ee23ad0a 100644 --- a/flow/designs/gf12/gcd/constraint.sdc +++ b/flow/designs/gf12/gcd/constraint.sdc @@ -1,17 +1,17 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 280 +set clk_period 280 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] # set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/gcd/metadata-base-ok.json b/flow/designs/gf12/gcd/metadata-base-ok.json deleted file mode 100644 index da398c8f66..0000000000 --- a/flow/designs/gf12/gcd/metadata-base-ok.json +++ /dev/null @@ -1,305 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 280.0000" - ], - "cts__clock__skew__hold": 6.72379, - "cts__clock__skew__setup": 3.09529, - "cts__cpu__total": 22.42, - "cts__design__core__area": 6356.5, - "cts__design__die__area": 10008.8, - "cts__design__instance__area": 522.692, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 522.692, - "cts__design__instance__count": 941, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 46, - "cts__design__instance__count__stdcell": 941, - "cts__design__instance__displacement__max": 2.152, - "cts__design__instance__displacement__mean": 0.05, - "cts__design__instance__displacement__total": 47.493, - "cts__design__instance__utilization": 0.0822296, - "cts__design__instance__utilization__stdcell": 0.0822296, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 1351496.0, - "cts__power__internal__total": 0.00142798, - "cts__power__leakage__total": 2.53364e-07, - "cts__power__switching__total": 0.00095782, - "cts__power__total": 0.00238605, - "cts__route__wirelength__estimated": 3980.3, - "cts__runtime__total": "0:23.54", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.898463, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.932168, - "cts__timing__drv__setup_violation_count": 20, - "cts__timing__setup__tns": -139.327, - "cts__timing__setup__ws": -19.6321, - "design__io__hpwl": 4560466, - "design__violations": 0, - "detailedplace__cpu__total": 3.26, - "detailedplace__design__core__area": 6356.5, - "detailedplace__design__die__area": 10008.8, - "detailedplace__design__instance__area": 494.726, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 494.726, - "detailedplace__design__instance__count": 887, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 887, - "detailedplace__design__instance__displacement__max": 2.424, - "detailedplace__design__instance__displacement__mean": 0.236, - "detailedplace__design__instance__displacement__total": 209.546, - "detailedplace__design__instance__utilization": 0.07783, - "detailedplace__design__instance__utilization__stdcell": 0.07783, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 362692.0, - "detailedplace__power__internal__total": 0.00107742, - "detailedplace__power__leakage__total": 1.34431e-07, - "detailedplace__power__switching__total": 0.000714834, - "detailedplace__power__total": 0.00179238, - "detailedplace__route__wirelength__estimated": 3844.06, - "detailedplace__runtime__total": "0:03.77", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.898463, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.821557, - "detailedplace__timing__drv__setup_violation_count": 30, - "detailedplace__timing__setup__tns": -711.474, - "detailedplace__timing__setup__ws": -59.6715, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 244, - "detailedroute__route__drc_errors__iter:2": 3, - "detailedroute__route__drc_errors__iter:3": 4, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 518, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3793, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3793, - "detailedroute__route__wirelength": 4365, - "detailedroute__route__wirelength__iter:1": 4405, - "detailedroute__route__wirelength__iter:2": 4365, - "detailedroute__route__wirelength__iter:3": 4365, - "detailedroute__route__wirelength__iter:4": 4365, - "finish__clock__skew__hold": 5.98503, - "finish__clock__skew__setup": 2.48435, - "finish__cpu__total": 4.15, - "finish__design__core__area": 6356.5, - "finish__design__die__area": 10008.8, - "finish__design__instance__area": 525.402, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 525.402, - "finish__design__instance__count": 945, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 945, - "finish__design__instance__utilization": 0.0826559, - "finish__design__instance__utilization__stdcell": 0.0826559, - "finish__design__io": 54, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 456236.0, - "finish__power__internal__total": 0.00144964, - "finish__power__leakage__total": 2.57012e-07, - "finish__power__switching__total": 0.000849994, - "finish__power__total": 0.0022999, - "finish__runtime__total": "0:05.28", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.908534, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.942536, - "finish__timing__drv__setup_violation_count": 11, - "finish__timing__setup__tns": -39.6578, - "finish__timing__setup__ws": -7.87764, - "finish__timing__wns_percent_delay": -3.39731, - "finish_merge__cpu__total": 1.52, - "finish_merge__mem__peak": 434976.0, - "finish_merge__runtime__total": "0:10.19", - "floorplan__cpu__total": 3.39, - "floorplan__design__core__area": 6356.5, - "floorplan__design__die__area": 10008.8, - "floorplan__design__instance__area": 126.137, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 126.137, - "floorplan__design__instance__count": 374, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 374, - "floorplan__design__instance__utilization": 0.0198438, - "floorplan__design__instance__utilization__stdcell": 0.0198438, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 362076.0, - "floorplan__power__internal__total": 0.00081178, - "floorplan__power__leakage__total": 9.95802e-08, - "floorplan__power__switching__total": 0.000317475, - "floorplan__power__total": 0.00112935, - "floorplan__runtime__total": "0:07.00", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 20.6404, - "floorplan_io__cpu__total": 2.94, - "floorplan_io__mem__peak": 353372.0, - "floorplan_io__runtime__total": "0:03.45", - "floorplan_macro__cpu__total": 2.98, - "floorplan_macro__mem__peak": 353376.0, - "floorplan_macro__runtime__total": "0:03.49", - "floorplan_pdn__cpu__total": 3.14, - "floorplan_pdn__mem__peak": 359508.0, - "floorplan_pdn__runtime__total": "0:03.82", - "floorplan_tap__cpu__total": 2.96, - "floorplan_tap__mem__peak": 352564.0, - "floorplan_tap__runtime__total": "0:03.64", - "floorplan_tdms__cpu__total": 2.97, - "floorplan_tdms__mem__peak": 353660.0, - "floorplan_tdms__runtime__total": "0:03.46", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 23.03, - "globalplace__design__core__area": 6356.5, - "globalplace__design__die__area": 10008.8, - "globalplace__design__instance__area": 412.377, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 412.377, - "globalplace__design__instance__count": 834, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 834, - "globalplace__design__instance__utilization": 0.0648749, - "globalplace__design__instance__utilization__stdcell": 0.0648749, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1299800.0, - "globalplace__power__internal__total": 0.000812442, - "globalplace__power__leakage__total": 9.95802e-08, - "globalplace__power__switching__total": 0.000587761, - "globalplace__power__total": 0.0014003, - "globalplace__runtime__total": "0:05.43", - "globalplace__timing__setup__tns": -378.149, - "globalplace__timing__setup__ws": -29.9497, - "globalplace_io__cpu__total": 3.03, - "globalplace_io__mem__peak": 354908.0, - "globalplace_io__runtime__total": "0:03.52", - "globalplace_skip_io__cpu__total": 24.74, - "globalplace_skip_io__mem__peak": 356260.0, - "globalplace_skip_io__runtime__total": "0:04.13", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 6.476, - "globalroute__clock__skew__setup": 2.74291, - "globalroute__cpu__total": 9.53, - "globalroute__design__core__area": 6356.5, - "globalroute__design__die__area": 10008.8, - "globalroute__design__instance__area": 525.402, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 525.402, - "globalroute__design__instance__count": 945, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 4, - "globalroute__design__instance__count__stdcell": 945, - "globalroute__design__instance__displacement__max": 1.5, - "globalroute__design__instance__displacement__mean": 0.0115, - "globalroute__design__instance__displacement__total": 11.076, - "globalroute__design__instance__utilization": 0.0826559, - "globalroute__design__instance__utilization__stdcell": 0.0826559, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 3, - "globalroute__mem__peak": 1318964.0, - "globalroute__power__internal__total": 0.00145028, - "globalroute__power__leakage__total": 2.57012e-07, - "globalroute__power__switching__total": 0.00103135, - "globalroute__power__total": 0.00248189, - "globalroute__route__wirelength__estimated": 3993.71, - "globalroute__runtime__total": "0:09.47", - "globalroute__timing__clock__slack": -24.695, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.891238, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.932272, - "globalroute__timing__drv__setup_violation_count": 28, - "globalroute__timing__setup__tns": -369.962, - "globalroute__timing__setup__ws": -24.6953, - "placeopt__cpu__total": 3.48, - "placeopt__design__core__area": 6356.5, - "placeopt__design__die__area": 10008.8, - "placeopt__design__instance__area": 494.726, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 494.726, - "placeopt__design__instance__count": 887, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 887, - "placeopt__design__instance__utilization": 0.07783, - "placeopt__design__instance__utilization__stdcell": 0.07783, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1221624.0, - "placeopt__power__internal__total": 0.00107727, - "placeopt__power__leakage__total": 1.34431e-07, - "placeopt__power__switching__total": 0.000718898, - "placeopt__power__total": 0.0017963, - "placeopt__runtime__total": "0:04.48", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.891841, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.813935, - "placeopt__timing__drv__setup_violation_count": 28, - "placeopt__timing__setup__tns": -678.376, - "placeopt__timing__setup__ws": -59.1232, - "run__flow__design": "gcd_9T_gf", - "run__flow__generate_date": "2024-09-19 14:02", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "cb0bda49-7c12-4deb-9a68-3c949576263e", - "run__flow__variant": "base", - "synth__cpu__total": 5.03, - "synth__design__instance__area__stdcell": 126.137076, - "synth__design__instance__count__stdcell": 374.0, - "synth__mem__peak": 189696.0, - "synth__runtime__total": "0:05.66", - "total_time": "0:01:40.330000" -} \ No newline at end of file diff --git a/flow/designs/gf12/gcd/rules-base.json b/flow/designs/gf12/gcd/rules-base.json index 2ba5993628..e79ab6c325 100644 --- a/flow/designs/gf12/gcd/rules-base.json +++ b/flow/designs/gf12/gcd/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk index c94bfc69e1..78f928de7f 100644 --- a/flow/designs/gf12/ibex/config.mk +++ b/flow/designs/gf12/ibex/config.mk @@ -2,46 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf12 +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc index 1684b897b5..85d691d76e 100644 --- a/flow/designs/gf12/ibex/constraint.sdc +++ b/flow/designs/gf12/ibex/constraint.sdc @@ -1,17 +1,17 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i -set clk_period 1020 +set clk_period 1020 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/ibex/metadata-base-ok.json b/flow/designs/gf12/ibex/metadata-base-ok.json deleted file mode 100644 index cc7fd68771..0000000000 --- a/flow/designs/gf12/ibex/metadata-base-ok.json +++ /dev/null @@ -1,307 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1020.0000" - ], - "cts__clock__skew__hold": 113.576, - "cts__clock__skew__setup": 148.645, - "cts__cpu__total": 1942.34, - "cts__design__core__area": 14025.1, - "cts__design__die__area": 15094.3, - "cts__design__instance__area": 8552.31, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 8552.31, - "cts__design__instance__count": 18291, - "cts__design__instance__count__hold_buffer": 1448, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 162, - "cts__design__instance__count__stdcell": 18291, - "cts__design__instance__displacement__max": 12.432, - "cts__design__instance__displacement__mean": 0.182, - "cts__design__instance__displacement__total": 3342.23, - "cts__design__instance__utilization": 0.609787, - "cts__design__instance__utilization__stdcell": 0.609787, - "cts__design__io": 264, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 1453980.0, - "cts__power__internal__total": 0.110659, - "cts__power__leakage__total": 2.18288e-05, - "cts__power__switching__total": 0.107383, - "cts__power__total": 0.218064, - "cts__route__wirelength__estimated": 148774, - "cts__runtime__total": "32:23.68", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.854424, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.913307, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": -0.0239253, - "cts__timing__setup__ws": 32.1359, - "design__io__hpwl": 14375852, - "design__violations": 0, - "detailedplace__cpu__total": 17.56, - "detailedplace__design__core__area": 14025.1, - "detailedplace__design__die__area": 15094.3, - "detailedplace__design__instance__area": 7710.76, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 7710.76, - "detailedplace__design__instance__count": 16343, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 16343, - "detailedplace__design__instance__displacement__max": 9.1, - "detailedplace__design__instance__displacement__mean": 0.536, - "detailedplace__design__instance__displacement__total": 8780.18, - "detailedplace__design__instance__utilization": 0.549784, - "detailedplace__design__instance__utilization__stdcell": 0.549784, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 450620.0, - "detailedplace__power__internal__total": 0.0972566, - "detailedplace__power__leakage__total": 5.39763e-06, - "detailedplace__power__switching__total": 0.0994482, - "detailedplace__power__total": 0.19671, - "detailedplace__route__wirelength__estimated": 138724, - "detailedplace__runtime__total": "0:18.19", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.86759, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.310081, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 23.1664, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 14125, - "detailedroute__route__drc_errors__iter:2": 895, - "detailedroute__route__drc_errors__iter:3": 704, - "detailedroute__route__drc_errors__iter:4": 33, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 17690, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 188226, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 188226, - "detailedroute__route__wirelength": 183268, - "detailedroute__route__wirelength__iter:1": 185336, - "detailedroute__route__wirelength__iter:2": 183724, - "detailedroute__route__wirelength__iter:3": 183272, - "detailedroute__route__wirelength__iter:4": 183273, - "detailedroute__route__wirelength__iter:5": 183268, - "finish__clock__skew__hold": 103.66, - "finish__clock__skew__setup": 137.848, - "finish__cpu__total": 41.2, - "finish__design__core__area": 14025.1, - "finish__design__die__area": 15094.3, - "finish__design__instance__area": 8626.43, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 8626.43, - "finish__design__instance__count": 18363, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 18363, - "finish__design__instance__utilization": 0.615072, - "finish__design__instance__utilization__stdcell": 0.615072, - "finish__design__io": 264, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 736684.0, - "finish__power__internal__total": 0.114737, - "finish__power__leakage__total": 2.19556e-05, - "finish__power__switching__total": 0.113412, - "finish__power__total": 0.228171, - "finish__runtime__total": "0:42.76", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.853284, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.913159, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 60.3004, - "finish__timing__wns_percent_delay": 7.979414, - "finish_merge__cpu__total": 3.1, - "finish_merge__mem__peak": 590640.0, - "finish_merge__runtime__total": "0:12.18", - "floorplan__cpu__total": 11.48, - "floorplan__design__core__area": 14025.1, - "floorplan__design__die__area": 15094.3, - "floorplan__design__instance__area": 5651.3, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 5651.3, - "floorplan__design__instance__count": 15272, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 15272, - "floorplan__design__instance__utilization": 0.402943, - "floorplan__design__instance__utilization__stdcell": 0.402943, - "floorplan__design__io": 264, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 426840.0, - "floorplan__power__internal__total": 0.07181, - "floorplan__power__leakage__total": 4.23494e-06, - "floorplan__power__switching__total": 0.0544412, - "floorplan__power__total": 0.126255, - "floorplan__runtime__total": "0:15.22", - "floorplan__timing__setup__tns": -384.662, - "floorplan__timing__setup__ws": 182.433, - "floorplan_io__cpu__total": 3.14, - "floorplan_io__mem__peak": 379688.0, - "floorplan_io__runtime__total": "0:03.57", - "floorplan_macro__cpu__total": 3.14, - "floorplan_macro__mem__peak": 378708.0, - "floorplan_macro__runtime__total": "0:03.58", - "floorplan_pdn__cpu__total": 3.56, - "floorplan_pdn__mem__peak": 383608.0, - "floorplan_pdn__runtime__total": "0:04.27", - "floorplan_tap__cpu__total": 3.15, - "floorplan_tap__mem__peak": 370400.0, - "floorplan_tap__runtime__total": "0:03.78", - "floorplan_tdms__cpu__total": 3.09, - "floorplan_tdms__mem__peak": 380016.0, - "floorplan_tdms__runtime__total": "0:03.60", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 229.66, - "globalplace__design__core__area": 14025.1, - "globalplace__design__die__area": 15094.3, - "globalplace__design__instance__area": 6127.45, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 6127.45, - "globalplace__design__instance__count": 16053, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16053, - "globalplace__design__instance__utilization": 0.436892, - "globalplace__design__instance__utilization__stdcell": 0.436892, - "globalplace__design__io": 264, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1436804.0, - "globalplace__power__internal__total": 0.0722237, - "globalplace__power__leakage__total": 4.23494e-06, - "globalplace__power__switching__total": 0.0869787, - "globalplace__power__total": 0.159207, - "globalplace__runtime__total": "1:05.04", - "globalplace__timing__setup__tns": -2206260.0, - "globalplace__timing__setup__ws": -2151.5, - "globalplace_io__cpu__total": 3.12, - "globalplace_io__mem__peak": 381792.0, - "globalplace_io__runtime__total": "0:03.61", - "globalplace_skip_io__cpu__total": 310.87, - "globalplace_skip_io__mem__peak": 401872.0, - "globalplace_skip_io__runtime__total": "0:13.51", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 116.61, - "globalroute__clock__skew__setup": 153.361, - "globalroute__cpu__total": 756.88, - "globalroute__design__core__area": 14025.1, - "globalroute__design__die__area": 15094.3, - "globalroute__design__instance__area": 8626.43, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 8626.43, - "globalroute__design__instance__count": 18363, - "globalroute__design__instance__count__hold_buffer": 1, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 54, - "globalroute__design__instance__count__stdcell": 18363, - "globalroute__design__instance__displacement__max": 9.084, - "globalroute__design__instance__displacement__mean": 0.0425, - "globalroute__design__instance__displacement__total": 789.24, - "globalroute__design__instance__utilization": 0.615072, - "globalroute__design__instance__utilization__stdcell": 0.615072, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 3, - "globalroute__mem__peak": 1689668.0, - "globalroute__power__internal__total": 0.114791, - "globalroute__power__leakage__total": 2.19556e-05, - "globalroute__power__switching__total": 0.12012, - "globalroute__power__total": 0.234933, - "globalroute__route__wirelength__estimated": 150461, - "globalroute__runtime__total": "11:50.42", - "globalroute__timing__clock__slack": 29.108, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.842553, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.863258, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 29.1083, - "placeopt__cpu__total": 19.04, - "placeopt__design__core__area": 14025.1, - "placeopt__design__die__area": 15094.3, - "placeopt__design__instance__area": 7710.76, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 7710.76, - "placeopt__design__instance__count": 16343, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 16343, - "placeopt__design__instance__utilization": 0.549784, - "placeopt__design__instance__utilization__stdcell": 0.549784, - "placeopt__design__io": 264, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1284256.0, - "placeopt__power__internal__total": 0.0972531, - "placeopt__power__leakage__total": 5.39763e-06, - "placeopt__power__switching__total": 0.099166, - "placeopt__power__total": 0.196424, - "placeopt__runtime__total": "0:20.18", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.87397, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.300999, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 28.6765, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-09-19 14:51", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "30d03916-672b-4153-9122-ef38ca7d54ad", - "run__flow__variant": "base", - "synth__cpu__total": 82.61, - "synth__design__instance__area__stdcell": 5651.009208, - "synth__design__instance__count__stdcell": 15272.0, - "synth__mem__peak": 237956.0, - "synth__runtime__total": "1:23.42", - "total_time": "0:49:07.010000" -} \ No newline at end of file diff --git a/flow/designs/gf12/ibex/rules-base.json b/flow/designs/gf12/ibex/rules-base.json index e2f7de9bd6..40e0af92b1 100644 --- a/flow/designs/gf12/ibex/rules-base.json +++ b/flow/designs/gf12/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 8867, + "value": 8018, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18794, + "value": 18384, "compare": "<=" }, "detailedplace__design__violations": { @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1634, + "value": 1796, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 209798, + "value": 207867, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc index 86761946c6..9e32a57bf1 100644 --- a/flow/designs/gf12/jpeg/constraint.sdc +++ b/flow/designs/gf12/jpeg/constraint.sdc @@ -1,17 +1,17 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 770 +set clk_period 770 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 diff --git a/flow/designs/gf12/jpeg/metadata-base-ok.json b/flow/designs/gf12/jpeg/metadata-base-ok.json deleted file mode 100644 index bc07b91e53..0000000000 --- a/flow/designs/gf12/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,319 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 770.0000" - ], - "cts__clock__skew__hold": 27.7769, - "cts__clock__skew__setup": 15.1228, - "cts__cpu__total": 635.41, - "cts__design__core__area": 52419.9, - "cts__design__die__area": 54440.6, - "cts__design__instance__area": 26089.1, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 26089.1, - "cts__design__instance__count": 89046, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 57, - "cts__design__instance__count__stdcell": 89046, - "cts__design__instance__displacement__max": 4.6595, - "cts__design__instance__displacement__mean": 0.0055, - "cts__design__instance__displacement__total": 520.559, - "cts__design__instance__utilization": 0.497695, - "cts__design__instance__utilization__stdcell": 0.497695, - "cts__design__io": 47, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 1776548.0, - "cts__power__internal__total": 0.141625, - "cts__power__leakage__total": 3.74147e-05, - "cts__power__switching__total": 0.148433, - "cts__power__total": 0.290095, - "cts__route__wirelength__estimated": 685422, - "cts__runtime__total": "10:36.90", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.861453, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 4, - "cts__timing__drv__max_slew_limit": -0.0399349, - "cts__timing__drv__setup_violation_count": 311, - "cts__timing__setup__tns": -12856.1, - "cts__timing__setup__ws": -130.962, - "design__io__hpwl": 3316167, - "design__violations": 0, - "detailedplace__cpu__total": 60.3, - "detailedplace__design__core__area": 52419.9, - "detailedplace__design__die__area": 54440.6, - "detailedplace__design__instance__area": 25499.7, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 25499.7, - "detailedplace__design__instance__count": 88653, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 88653, - "detailedplace__design__instance__displacement__max": 5.0545, - "detailedplace__design__instance__displacement__mean": 0.4505, - "detailedplace__design__instance__displacement__total": 39949.6, - "detailedplace__design__instance__utilization": 0.486452, - "detailedplace__design__instance__utilization__stdcell": 0.486452, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 775320.0, - "detailedplace__power__internal__total": 0.129654, - "detailedplace__power__leakage__total": 2.02165e-05, - "detailedplace__power__switching__total": 0.139678, - "detailedplace__power__total": 0.269352, - "detailedplace__route__wirelength__estimated": 691728, - "detailedplace__runtime__total": "1:01.18", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.894494, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.254251, - "detailedplace__timing__drv__setup_violation_count": 373, - "detailedplace__timing__setup__tns": -18630.5, - "detailedplace__timing__setup__ws": -180.333, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 41733, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 2242, - "detailedroute__route__drc_errors__iter:3": 1355, - "detailedroute__route__drc_errors__iter:4": 12, - "detailedroute__route__drc_errors__iter:5": 5, - "detailedroute__route__drc_errors__iter:6": 3, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 87000, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 712174, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 712174, - "detailedroute__route__wirelength": 769838, - "detailedroute__route__wirelength__iter:1": 776691, - "detailedroute__route__wirelength__iter:10": 769839, - "detailedroute__route__wirelength__iter:11": 769838, - "detailedroute__route__wirelength__iter:2": 770836, - "detailedroute__route__wirelength__iter:3": 769853, - "detailedroute__route__wirelength__iter:4": 769839, - "detailedroute__route__wirelength__iter:5": 769840, - "detailedroute__route__wirelength__iter:6": 769839, - "detailedroute__route__wirelength__iter:7": 769839, - "detailedroute__route__wirelength__iter:8": 769839, - "detailedroute__route__wirelength__iter:9": 769839, - "finish__clock__skew__hold": 28.2095, - "finish__clock__skew__setup": 19.3041, - "finish__cpu__total": 76.78, - "finish__design__core__area": 52419.9, - "finish__design__die__area": 54440.6, - "finish__design__instance__area": 26119.5, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 26119.5, - "finish__design__instance__count": 89061, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 89061, - "finish__design__instance__utilization": 0.498275, - "finish__design__instance__utilization__stdcell": 0.498275, - "finish__design__io": 47, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 1563120.0, - "finish__power__internal__total": 0.141896, - "finish__power__leakage__total": 3.74529e-05, - "finish__power__switching__total": 0.152315, - "finish__power__total": 0.294248, - "finish__runtime__total": "1:19.34", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.85815, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.879902, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 32.409, - "finish__timing__wns_percent_delay": 3.966285, - "finish_merge__cpu__total": 8.91, - "finish_merge__mem__peak": 1139268.0, - "finish_merge__runtime__total": "0:17.81", - "floorplan__cpu__total": 22.68, - "floorplan__design__core__area": 52419.9, - "floorplan__design__die__area": 54440.6, - "floorplan__design__instance__area": 21036.1, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 21036.1, - "floorplan__design__instance__count": 85620, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 85620, - "floorplan__design__instance__utilization": 0.401299, - "floorplan__design__instance__utilization__stdcell": 0.401299, - "floorplan__design__io": 47, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 12, - "floorplan__mem__peak": 672668.0, - "floorplan__power__internal__total": 0.108333, - "floorplan__power__leakage__total": 1.65673e-05, - "floorplan__power__switching__total": 0.0742536, - "floorplan__power__total": 0.182603, - "floorplan__runtime__total": "0:26.30", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 274.654, - "floorplan_io__cpu__total": 3.49, - "floorplan_io__mem__peak": 494416.0, - "floorplan_io__runtime__total": "0:04.00", - "floorplan_macro__cpu__total": 3.54, - "floorplan_macro__mem__peak": 492144.0, - "floorplan_macro__runtime__total": "0:04.11", - "floorplan_pdn__cpu__total": 5.23, - "floorplan_pdn__mem__peak": 502236.0, - "floorplan_pdn__runtime__total": "0:06.02", - "floorplan_tap__cpu__total": 3.69, - "floorplan_tap__mem__peak": 443468.0, - "floorplan_tap__runtime__total": "0:04.42", - "floorplan_tdms__cpu__total": 3.56, - "floorplan_tdms__mem__peak": 493640.0, - "floorplan_tdms__runtime__total": "0:04.13", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 2087.28, - "globalplace__design__core__area": 52419.9, - "globalplace__design__die__area": 54440.6, - "globalplace__design__instance__area": 22177.6, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 22177.6, - "globalplace__design__instance__count": 87540, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 87540, - "globalplace__design__instance__utilization": 0.423077, - "globalplace__design__instance__utilization__stdcell": 0.423077, - "globalplace__design__io": 47, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 2007168.0, - "globalplace__power__internal__total": 0.109097, - "globalplace__power__leakage__total": 1.65673e-05, - "globalplace__power__switching__total": 0.13034, - "globalplace__power__total": 0.239453, - "globalplace__runtime__total": "4:44.01", - "globalplace__timing__setup__tns": -183269, - "globalplace__timing__setup__ws": -726.51, - "globalplace_io__cpu__total": 3.48, - "globalplace_io__mem__peak": 500460.0, - "globalplace_io__runtime__total": "0:04.12", - "globalplace_skip_io__cpu__total": 314.84, - "globalplace_skip_io__mem__peak": 599668.0, - "globalplace_skip_io__runtime__total": "0:23.60", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 33.9675, - "globalroute__clock__skew__setup": 25.9143, - "globalroute__cpu__total": 401.62, - "globalroute__design__core__area": 52419.9, - "globalroute__design__die__area": 54440.6, - "globalroute__design__instance__area": 26119.5, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 26119.5, - "globalroute__design__instance__count": 89061, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 4, - "globalroute__design__instance__count__stdcell": 89061, - "globalroute__design__instance__displacement__max": 2.088, - "globalroute__design__instance__displacement__mean": 0.001, - "globalroute__design__instance__displacement__total": 97.656, - "globalroute__design__instance__utilization": 0.498275, - "globalroute__design__instance__utilization__stdcell": 0.498275, - "globalroute__design__io": 47, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 3, - "globalroute__mem__peak": 2795584.0, - "globalroute__power__internal__total": 0.142261, - "globalroute__power__leakage__total": 3.74529e-05, - "globalroute__power__switching__total": 0.161302, - "globalroute__power__total": 0.3036, - "globalroute__route__wirelength__estimated": 685716, - "globalroute__runtime__total": "3:59.66", - "globalroute__timing__clock__slack": -7.856, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.84932, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.263018, - "globalroute__timing__drv__setup_violation_count": 9, - "globalroute__timing__setup__tns": -20.2609, - "globalroute__timing__setup__ws": -7.85577, - "placeopt__cpu__total": 56.31, - "placeopt__design__core__area": 52419.9, - "placeopt__design__die__area": 54440.6, - "placeopt__design__instance__area": 25499.7, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 25499.7, - "placeopt__design__instance__count": 88653, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 88653, - "placeopt__design__instance__utilization": 0.486452, - "placeopt__design__instance__utilization__stdcell": 0.486452, - "placeopt__design__io": 47, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1575200.0, - "placeopt__power__internal__total": 0.129642, - "placeopt__power__leakage__total": 2.02165e-05, - "placeopt__power__switching__total": 0.138035, - "placeopt__power__total": 0.267697, - "placeopt__runtime__total": "0:57.65", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.890017, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.226899, - "placeopt__timing__drv__setup_violation_count": 359, - "placeopt__timing__setup__tns": -18153.8, - "placeopt__timing__setup__ws": -183.903, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-09-23 20:15", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15825-ge21fbdf83", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "d0bcdbaff43e270478f6f7c6651d16e5a2fc70a7", - "run__flow__uuid": "eeb8bfb9-44ce-4ae1-a842-adf2f68bb8f0", - "run__flow__variant": "base", - "synth__cpu__total": 88.67, - "synth__design__instance__area__stdcell": 21036.056742, - "synth__design__instance__count__stdcell": 85620.0, - "synth__mem__peak": 1032672.0, - "synth__runtime__total": "1:30.57", - "total_time": "0:25:43.820000" -} \ No newline at end of file diff --git a/flow/designs/gf12/jpeg/rules-base.json b/flow/designs/gf12/jpeg/rules-base.json index a29f5fe778..cff894b375 100644 --- a/flow/designs/gf12/jpeg/rules-base.json +++ b/flow/designs/gf12/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 23085.37, + "value": 20776.3, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 29325, + "value": 25061, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 92367, + "value": 90181, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 8032, + "value": 7842, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 8032, + "value": 7842, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.06, + "value": -42.35, "compare": ">=" }, "finish__design__instance__area": { - "value": 30037, + "value": 25626, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 4016, + "value": 3921, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk index 56b208a44d..2ed5601613 100644 --- a/flow/designs/gf12/swerv_wrapper/config.mk +++ b/flow/designs/gf12/swerv_wrapper/config.mk @@ -1,15 +1,9 @@ export DESIGN_NAME = swerv_wrapper export PLATFORM = gf12 # -export MAX_UNGROUP_SIZE ?= 10000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 25000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc @@ -29,13 +23,12 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg11_w40_all.gds2 \ export DIE_AREA = 0 0 610 500 export CORE_AREA = 2 2 608 498 # -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-10 -exclude bottom:400-700 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export PLACE_DENSITY_LB_ADDON = 0.05 export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl # export MACRO_PLACE_HALO = 7 7 -export MACRO_PLACE_CHANNEL = 14 14 ifeq ($(USE_FILL),1) export DESIGN_TYPE = CELL diff --git a/flow/designs/gf12/swerv_wrapper/constraint.sdc b/flow/designs/gf12/swerv_wrapper/constraint.sdc index a7296dd71c..186b5121f8 100644 --- a/flow/designs/gf12/swerv_wrapper/constraint.sdc +++ b/flow/designs/gf12/swerv_wrapper/constraint.sdc @@ -8,11 +8,11 @@ current_design swerv_wrapper ############################################################################### create_clock -name core_clock -period 1500.0 -waveform {0.0000 750.0} [get_ports {clk}] set_clock_uncertainty -setup 70.0000 core_clock -set_clock_uncertainty -hold 70.0000 core_clock +set_clock_uncertainty -hold 70.0000 core_clock #set_propagated_clock [get_clocks {core_clock}] create_clock -name jtag_clock -period 1500 -waveform {0.0000 750.0} [get_ports {jtag_tck}] set_clock_uncertainty -setup 70.0000 jtag_clock -set_clock_uncertainty -hold 70.0000 jtag_clock +set_clock_uncertainty -hold 70.0000 jtag_clock #set_propagated_clock [get_clocks {jtag_clock}] # There is sync logic between jtag and core_clock @@ -25,7 +25,7 @@ set_clock_uncertainty -hold 70.0000 jtag_clock # Design Rules ############################################################################### set clock_ports "jtag_tck clk" -set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" +set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" #set input_not_jtag_ports [remove_from_collection [all_inputs] "$jtag_ports $clock_ports"] set input_not_jtag_ports [list] foreach input [all_inputs] { @@ -40,9 +40,9 @@ foreach input [all_inputs] { lappend input_not_jtag_ports $input } } -set_input_delay 375 -clock jtag_clock $jtag_ports +set_input_delay 375 -clock jtag_clock $jtag_ports set_output_delay 375 -clock jtag_clock [get_ports "jtag_tdo"] -set_input_delay 750 -clock core_clock $input_not_jtag_ports +set_input_delay 750 -clock core_clock $input_not_jtag_ports set ports_list [list] foreach output [all_outputs] { set addFlag 1 @@ -63,5 +63,3 @@ set_driving_cell -lib_cell BUFH_X2N_A9PP84TR_C14 [all_inputs] foreach input [all_inputs] { set_load 0 $input } - - diff --git a/flow/designs/gf12/swerv_wrapper/io.tcl b/flow/designs/gf12/swerv_wrapper/io.tcl new file mode 100644 index 0000000000..0545c0cca8 --- /dev/null +++ b/flow/designs/gf12/swerv_wrapper/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-10 -region bottom:400-700 diff --git a/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json b/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json deleted file mode 100644 index 6496b7ded9..0000000000 --- a/flow/designs/gf12/swerv_wrapper/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 2, - "constraints__clocks__details": [ - "core_clock: 1500.0000", - "jtag_clock: 1500.0000" - ], - "cts__clock__skew__hold": 352.327, - "cts__clock__skew__setup": 327.443, - "cts__cpu__total": 1263.09, - "cts__design__core__area": 300176, - "cts__design__die__area": 305000, - "cts__design__instance__area": 160592, - "cts__design__instance__area__macros": 107153, - "cts__design__instance__area__stdcell": 53438.8, - "cts__design__instance__count": 122002, - "cts__design__instance__count__hold_buffer": 12645, - "cts__design__instance__count__macros": 28, - "cts__design__instance__count__setup_buffer": 25, - "cts__design__instance__count__stdcell": 121974, - "cts__design__instance__displacement__max": 4.428, - "cts__design__instance__displacement__mean": 0.075, - "cts__design__instance__displacement__total": 9188.95, - "cts__design__instance__utilization": 0.534992, - "cts__design__instance__utilization__stdcell": 0.276852, - "cts__design__io": 1416, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 8, - "cts__mem__peak": 2205908.0, - "cts__power__internal__total": 0.0509685, - "cts__power__leakage__total": 0.000157902, - "cts__power__switching__total": 0.0275409, - "cts__power__total": 0.0786673, - "cts__route__wirelength__estimated": 1581160.0, - "cts__runtime__total": "21:04.78", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0868509, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 83, - "cts__timing__drv__max_slew_limit": -4.56065, - "cts__timing__drv__setup_violation_count": 52, - "cts__timing__setup__tns": -550.342, - "cts__timing__setup__ws": -28.0082, - "design__io__hpwl": 845400027, - "design__violations": 0, - "detailedplace__cpu__total": 102.63, - "detailedplace__design__core__area": 300176, - "detailedplace__design__die__area": 305000, - "detailedplace__design__instance__area": 156807, - "detailedplace__design__instance__area__macros": 107153, - "detailedplace__design__instance__area__stdcell": 49654.3, - "detailedplace__design__instance__count": 108374, - "detailedplace__design__instance__count__macros": 28, - "detailedplace__design__instance__count__stdcell": 108346, - "detailedplace__design__instance__displacement__max": 31.4695, - "detailedplace__design__instance__displacement__mean": 0.525, - "detailedplace__design__instance__displacement__total": 57122, - "detailedplace__design__instance__utilization": 0.522384, - "detailedplace__design__instance__utilization__stdcell": 0.257245, - "detailedplace__design__io": 1416, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 1138540.0, - "detailedplace__power__internal__total": 0.0361698, - "detailedplace__power__leakage__total": 0.000111365, - "detailedplace__power__switching__total": 0.0164924, - "detailedplace__power__total": 0.0527736, - "detailedplace__route__wirelength__estimated": 1562540.0, - "detailedplace__runtime__total": "1:43.44", - "detailedplace__timing__drv__hold_violation_count": 7032, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0806205, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 49, - "detailedplace__timing__drv__max_slew_limit": -0.0478634, - "detailedplace__timing__drv__setup_violation_count": 7275, - "detailedplace__timing__setup__tns": -1285680.0, - "detailedplace__timing__setup__ws": -413.146, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 80000, - "detailedroute__route__drc_errors__iter:2": 6078, - "detailedroute__route__drc_errors__iter:3": 4191, - "detailedroute__route__drc_errors__iter:4": 112, - "detailedroute__route__drc_errors__iter:5": 35, - "detailedroute__route__drc_errors__iter:6": 3, - "detailedroute__route__drc_errors__iter:7": 3, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 108056, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1146324, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1146324, - "detailedroute__route__wirelength": 1865761, - "detailedroute__route__wirelength__iter:1": 1876051, - "detailedroute__route__wirelength__iter:2": 1867637, - "detailedroute__route__wirelength__iter:3": 1865765, - "detailedroute__route__wirelength__iter:4": 1865767, - "detailedroute__route__wirelength__iter:5": 1865763, - "detailedroute__route__wirelength__iter:6": 1865761, - "detailedroute__route__wirelength__iter:7": 1865761, - "detailedroute__route__wirelength__iter:8": 1865761, - "detailedroute__route__wirelength__iter:9": 1865761, - "finish__clock__skew__hold": 194.544, - "finish__clock__skew__setup": 189.576, - "finish__cpu__total": 168.1, - "finish__design__core__area": 300176, - "finish__design__die__area": 305000, - "finish__design__instance__area": 160800, - "finish__design__instance__area__macros": 107153, - "finish__design__instance__area__stdcell": 53647.3, - "finish__design__instance__count": 122759, - "finish__design__instance__count__macros": 28, - "finish__design__instance__count__stdcell": 122731, - "finish__design__instance__utilization": 0.535686, - "finish__design__instance__utilization__stdcell": 0.277932, - "finish__design__io": 1416, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 2332384.0, - "finish__power__internal__total": 0.0511413, - "finish__power__leakage__total": 0.000158092, - "finish__power__switching__total": 0.0272362, - "finish__power__total": 0.0785356, - "finish__runtime__total": "2:50.96", - "finish__timing__drv__hold_violation_count": 483, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0222554, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 2, - "finish__timing__drv__max_slew_limit": -0.303986, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 74.506, - "finish__timing__wns_percent_delay": 4.800432, - "finish_merge__cpu__total": 22.14, - "finish_merge__mem__peak": 1664624.0, - "finish_merge__runtime__total": "0:25.38", - "floorplan__cpu__total": 46.01, - "floorplan__design__core__area": 300176, - "floorplan__design__die__area": 305000, - "floorplan__design__instance__area": 135124, - "floorplan__design__instance__area__macros": 104693, - "floorplan__design__instance__area__stdcell": 30430.9, - "floorplan__design__instance__count": 86621, - "floorplan__design__instance__count__macros": 28, - "floorplan__design__instance__count__stdcell": 86593, - "floorplan__design__instance__utilization": 0.45015, - "floorplan__design__instance__utilization__stdcell": 0.15567, - "floorplan__design__io": 1416, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 11, - "floorplan__mem__peak": 770200.0, - "floorplan__power__internal__total": 0.0328978, - "floorplan__power__leakage__total": 9.90902e-05, - "floorplan__power__switching__total": 0.00471502, - "floorplan__power__total": 0.0377119, - "floorplan__runtime__total": "0:47.39", - "floorplan__timing__setup__tns": -480089000.0, - "floorplan__timing__setup__ws": -65978.4, - "floorplan_io__cpu__total": 3.62, - "floorplan_io__mem__peak": 527396.0, - "floorplan_io__runtime__total": "0:04.09", - "floorplan_macro__cpu__total": 137.65, - "floorplan_macro__mem__peak": 908552.0, - "floorplan_macro__runtime__total": "0:35.85", - "floorplan_pdn__cpu__total": 20.89, - "floorplan_pdn__mem__peak": 979176.0, - "floorplan_pdn__runtime__total": "0:21.68", - "floorplan_tap__cpu__total": 10.35, - "floorplan_tap__mem__peak": 480608.0, - "floorplan_tap__runtime__total": "0:10.92", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 943.82, - "globalplace__design__core__area": 300176, - "globalplace__design__die__area": 305000, - "globalplace__design__instance__area": 147104, - "globalplace__design__instance__area__macros": 107153, - "globalplace__design__instance__area__stdcell": 39951.1, - "globalplace__design__instance__count": 102380, - "globalplace__design__instance__count__macros": 28, - "globalplace__design__instance__count__stdcell": 102352, - "globalplace__design__instance__utilization": 0.490059, - "globalplace__design__instance__utilization__stdcell": 0.206975, - "globalplace__design__io": 1416, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 2567864.0, - "globalplace__power__internal__total": 0.0344342, - "globalplace__power__leakage__total": 9.90902e-05, - "globalplace__power__switching__total": 0.0141681, - "globalplace__power__total": 0.0487014, - "globalplace__runtime__total": "9:39.25", - "globalplace__timing__setup__tns": -1408980000.0, - "globalplace__timing__setup__ws": -211889, - "globalplace_io__cpu__total": 3.98, - "globalplace_io__mem__peak": 568480.0, - "globalplace_io__runtime__total": "0:04.54", - "globalplace_skip_io__cpu__total": 286.7, - "globalplace_skip_io__mem__peak": 736160.0, - "globalplace_skip_io__runtime__total": "0:28.23", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 220.19, - "globalroute__clock__skew__setup": 211.58, - "globalroute__cpu__total": 724.05, - "globalroute__design__core__area": 300176, - "globalroute__design__die__area": 305000, - "globalroute__design__instance__area": 160800, - "globalroute__design__instance__area__macros": 107153, - "globalroute__design__instance__area__stdcell": 53647.3, - "globalroute__design__instance__count": 122759, - "globalroute__design__instance__count__hold_buffer": 560, - "globalroute__design__instance__count__macros": 28, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 122731, - "globalroute__design__instance__displacement__max": 2.016, - "globalroute__design__instance__displacement__mean": 0.003, - "globalroute__design__instance__displacement__total": 373.02, - "globalroute__design__instance__utilization": 0.535686, - "globalroute__design__instance__utilization__stdcell": 0.277932, - "globalroute__design__io": 1416, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 4, - "globalroute__mem__peak": 4298728.0, - "globalroute__power__internal__total": 0.0521173, - "globalroute__power__leakage__total": 0.000158092, - "globalroute__power__switching__total": 0.028886, - "globalroute__power__total": 0.0811614, - "globalroute__route__wirelength__estimated": 1589420.0, - "globalroute__runtime__total": "5:39.75", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 2, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0509948, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 4, - "globalroute__timing__drv__max_slew_limit": -2.31314, - "globalroute__timing__drv__setup_violation_count": 823, - "globalroute__timing__setup__tns": -18001.4, - "globalroute__timing__setup__ws": -61.4857, - "placeopt__cpu__total": 103.65, - "placeopt__design__core__area": 300176, - "placeopt__design__die__area": 305000, - "placeopt__design__instance__area": 156807, - "placeopt__design__instance__area__macros": 107153, - "placeopt__design__instance__area__stdcell": 49654.3, - "placeopt__design__instance__count": 108374, - "placeopt__design__instance__count__macros": 28, - "placeopt__design__instance__count__stdcell": 108346, - "placeopt__design__instance__utilization": 0.522384, - "placeopt__design__instance__utilization__stdcell": 0.257245, - "placeopt__design__io": 1416, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 1738128.0, - "placeopt__power__internal__total": 0.0361741, - "placeopt__power__leakage__total": 0.000111365, - "placeopt__power__switching__total": 0.0165484, - "placeopt__power__total": 0.0528339, - "placeopt__runtime__total": "1:44.91", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 56, - "placeopt__timing__drv__hold_violation_count": 7037, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0542605, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.000355756, - "placeopt__timing__drv__setup_violation_count": 7344, - "placeopt__timing__setup__tns": -1300270.0, - "placeopt__timing__setup__ws": -430.413, - "run__flow__design": "swerv_wrapper", - "run__flow__generate_date": "2024-09-19 15:24", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "0f83e524-7073-4d84-affb-6fc980c8fd03", - "run__flow__variant": "base", - "synth__cpu__total": 365.41, - "synth__design__instance__area__stdcell": 136814.601002, - "synth__design__instance__count__stdcell": 95238.0, - "synth__mem__peak": 1238052.0, - "synth__runtime__total": "6:08.40", - "total_time": "0:51:49.570000" -} \ No newline at end of file diff --git a/flow/designs/gf12/swerv_wrapper/rules-base.json b/flow/designs/gf12/swerv_wrapper/rules-base.json index ee782b1b4c..eccdad7d0f 100644 --- a/flow/designs/gf12/swerv_wrapper/rules-base.json +++ b/flow/designs/gf12/swerv_wrapper/rules-base.json @@ -24,7 +24,7 @@ "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13650, + "value": 11303, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 2132201, + "value": 2311628, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 660, + "value": 755, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk index 98eeb8da2e..fe6b436ab9 100644 --- a/flow/designs/gf12/tinyRocket/config.mk +++ b/flow/designs/gf12/tinyRocket/config.mk @@ -3,7 +3,7 @@ export DESIGN_NAME = RocketTile export PLATFORM = gf12 export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 1000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 1000 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc index e5604adf91..79e26f0bee 100644 --- a/flow/designs/gf12/tinyRocket/constraint.sdc +++ b/flow/designs/gf12/tinyRocket/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name core_clock +set clk_name core_clock set clk_port_name clock -set clk_period 800 +set clk_period 800 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf12/tinyRocket/metadata-base-ok.json b/flow/designs/gf12/tinyRocket/metadata-base-ok.json deleted file mode 100644 index 9d81409337..0000000000 --- a/flow/designs/gf12/tinyRocket/metadata-base-ok.json +++ /dev/null @@ -1,306 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 800.0000" - ], - "cts__clock__skew__hold": 151.07, - "cts__clock__skew__setup": 149.487, - "cts__cpu__total": 45.51, - "cts__design__core__area": 129609, - "cts__design__die__area": 159939, - "cts__design__instance__area": 18530.7, - "cts__design__instance__area__macros": 2001.45, - "cts__design__instance__area__stdcell": 16529.3, - "cts__design__instance__count": 32203, - "cts__design__instance__count__hold_buffer": 11, - "cts__design__instance__count__macros": 2, - "cts__design__instance__count__setup_buffer": 9, - "cts__design__instance__count__stdcell": 32201, - "cts__design__instance__displacement__max": 2.032, - "cts__design__instance__displacement__mean": 0.0005, - "cts__design__instance__displacement__total": 28.908, - "cts__design__instance__utilization": 0.142974, - "cts__design__instance__utilization__stdcell": 0.129533, - "cts__design__io": 269, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 3, - "cts__mem__peak": 1558892.0, - "cts__power__internal__total": 0.0460059, - "cts__power__leakage__total": 3.25933e-05, - "cts__power__switching__total": 0.0332382, - "cts__power__total": 0.0792766, - "cts__route__wirelength__estimated": 413794, - "cts__runtime__total": "0:46.69", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.400114, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.629141, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__setup__tns": -0.713929, - "cts__timing__setup__ws": -0.712874, - "design__io__hpwl": 46460339, - "design__violations": 0, - "detailedplace__cpu__total": 25.17, - "detailedplace__design__core__area": 129609, - "detailedplace__design__die__area": 159939, - "detailedplace__design__instance__area": 17981.5, - "detailedplace__design__instance__area__macros": 2001.45, - "detailedplace__design__instance__area__stdcell": 15980, - "detailedplace__design__instance__count": 31787, - "detailedplace__design__instance__count__macros": 2, - "detailedplace__design__instance__count__stdcell": 31785, - "detailedplace__design__instance__displacement__max": 14.257, - "detailedplace__design__instance__displacement__mean": 0.3345, - "detailedplace__design__instance__displacement__total": 10658.7, - "detailedplace__design__instance__utilization": 0.138737, - "detailedplace__design__instance__utilization__stdcell": 0.125228, - "detailedplace__design__io": 269, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 1, - "detailedplace__mem__peak": 610988.0, - "detailedplace__power__internal__total": 0.0340713, - "detailedplace__power__leakage__total": 1.25166e-05, - "detailedplace__power__switching__total": 0.0253928, - "detailedplace__power__total": 0.0594766, - "detailedplace__route__wirelength__estimated": 411250, - "detailedplace__runtime__total": "0:25.63", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.400114, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.286454, - "detailedplace__timing__drv__setup_violation_count": 24, - "detailedplace__timing__setup__tns": -56.3136, - "detailedplace__timing__setup__ws": -6.31845, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 19401, - "detailedroute__route__drc_errors__iter:2": 1023, - "detailedroute__route__drc_errors__iter:3": 406, - "detailedroute__route__drc_errors__iter:4": 9, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 28042, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 271539, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 271539, - "detailedroute__route__wirelength": 485108, - "detailedroute__route__wirelength__iter:1": 487761, - "detailedroute__route__wirelength__iter:2": 485321, - "detailedroute__route__wirelength__iter:3": 485110, - "detailedroute__route__wirelength__iter:4": 485108, - "detailedroute__route__wirelength__iter:5": 485108, - "detailedroute__route__wirelength__iter:6": 485108, - "finish__clock__skew__hold": 135.659, - "finish__clock__skew__setup": 135.323, - "finish__cpu__total": 39.51, - "finish__design__core__area": 129609, - "finish__design__die__area": 159939, - "finish__design__instance__area": 18562, - "finish__design__instance__area__macros": 2001.45, - "finish__design__instance__area__stdcell": 16560.6, - "finish__design__instance__count": 32352, - "finish__design__instance__count__macros": 2, - "finish__design__instance__count__stdcell": 32350, - "finish__design__instance__utilization": 0.143216, - "finish__design__instance__utilization__stdcell": 0.129778, - "finish__design__io": 269, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 974572.0, - "finish__power__internal__total": 0.0459853, - "finish__power__leakage__total": 3.26161e-05, - "finish__power__switching__total": 0.0302791, - "finish__power__total": 0.0762971, - "finish__runtime__total": "0:40.75", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.398345, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.879818, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 63.7568, - "finish__timing__wns_percent_delay": 7.191185, - "finish_merge__cpu__total": 6.49, - "finish_merge__mem__peak": 814708.0, - "finish_merge__runtime__total": "0:08.99", - "floorplan__cpu__total": 14.13, - "floorplan__design__core__area": 129609, - "floorplan__design__die__area": 159939, - "floorplan__design__instance__area": 11584, - "floorplan__design__instance__area__macros": 1895.23, - "floorplan__design__instance__area__stdcell": 9688.75, - "floorplan__design__instance__count": 26865, - "floorplan__design__instance__count__hold_buffer": 390, - "floorplan__design__instance__count__macros": 2, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 26863, - "floorplan__design__instance__utilization": 0.0893766, - "floorplan__design__instance__utilization__stdcell": 0.0758632, - "floorplan__design__io": 269, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 11, - "floorplan__mem__peak": 474984.0, - "floorplan__power__internal__total": 0.0285078, - "floorplan__power__leakage__total": 9.13249e-06, - "floorplan__power__switching__total": 0.0078123, - "floorplan__power__total": 0.0363292, - "floorplan__runtime__total": "0:15.18", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 187.577, - "floorplan_io__cpu__total": 3.2, - "floorplan_io__mem__peak": 403384.0, - "floorplan_io__runtime__total": "0:03.50", - "floorplan_macro__cpu__total": 191.46, - "floorplan_macro__mem__peak": 472456.0, - "floorplan_macro__runtime__total": "0:44.37", - "floorplan_pdn__cpu__total": 8.12, - "floorplan_pdn__mem__peak": 449856.0, - "floorplan_pdn__runtime__total": "0:08.56", - "floorplan_tap__cpu__total": 3.4, - "floorplan_tap__mem__peak": 390060.0, - "floorplan_tap__runtime__total": "0:03.83", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 322.84, - "globalplace__design__core__area": 129609, - "globalplace__design__die__area": 159939, - "globalplace__design__instance__area": 14222.5, - "globalplace__design__instance__area__macros": 2001.45, - "globalplace__design__instance__area__stdcell": 12221.1, - "globalplace__design__instance__count": 31203, - "globalplace__design__instance__count__macros": 2, - "globalplace__design__instance__count__stdcell": 31201, - "globalplace__design__instance__utilization": 0.109734, - "globalplace__design__instance__utilization__stdcell": 0.095771, - "globalplace__design__io": 269, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1644088.0, - "globalplace__power__internal__total": 0.0287862, - "globalplace__power__leakage__total": 9.13249e-06, - "globalplace__power__switching__total": 0.0221096, - "globalplace__power__total": 0.0509049, - "globalplace__runtime__total": "1:33.37", - "globalplace__timing__setup__tns": -324306, - "globalplace__timing__setup__ws": -342.832, - "globalplace_io__cpu__total": 3.26, - "globalplace_io__mem__peak": 419756.0, - "globalplace_io__runtime__total": "0:03.61", - "globalplace_skip_io__cpu__total": 178.23, - "globalplace_skip_io__mem__peak": 454752.0, - "globalplace_skip_io__runtime__total": "0:10.91", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 174.201, - "globalroute__clock__skew__setup": 172.984, - "globalroute__cpu__total": 121.15, - "globalroute__design__core__area": 129609, - "globalroute__design__die__area": 159939, - "globalroute__design__instance__area": 18562, - "globalroute__design__instance__area__macros": 2001.45, - "globalroute__design__instance__area__stdcell": 16560.6, - "globalroute__design__instance__count": 32352, - "globalroute__design__instance__count__hold_buffer": 137, - "globalroute__design__instance__count__macros": 2, - "globalroute__design__instance__count__setup_buffer": 10, - "globalroute__design__instance__count__stdcell": 32350, - "globalroute__design__instance__displacement__max": 4.692, - "globalroute__design__instance__displacement__mean": 0.009, - "globalroute__design__instance__displacement__total": 295.464, - "globalroute__design__instance__utilization": 0.143216, - "globalroute__design__instance__utilization__stdcell": 0.129778, - "globalroute__design__io": 269, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 2066844.0, - "globalroute__power__internal__total": 0.0466808, - "globalroute__power__leakage__total": 3.26161e-05, - "globalroute__power__switching__total": 0.0346438, - "globalroute__power__total": 0.0813572, - "globalroute__route__wirelength__estimated": 414084, - "globalroute__runtime__total": "0:51.80", - "globalroute__timing__clock__slack": 0.445, - "globalroute__timing__drv__hold_violation_count": 3, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.385601, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.762043, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.445088, - "placeopt__cpu__total": 26.29, - "placeopt__design__core__area": 129609, - "placeopt__design__die__area": 159939, - "placeopt__design__instance__area": 17981.5, - "placeopt__design__instance__area__macros": 2001.45, - "placeopt__design__instance__area__stdcell": 15980, - "placeopt__design__instance__count": 31787, - "placeopt__design__instance__count__macros": 2, - "placeopt__design__instance__count__stdcell": 31785, - "placeopt__design__instance__utilization": 0.138737, - "placeopt__design__instance__utilization__stdcell": 0.125228, - "placeopt__design__io": 269, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 1350768.0, - "placeopt__power__internal__total": 0.0340733, - "placeopt__power__leakage__total": 1.25166e-05, - "placeopt__power__switching__total": 0.0255398, - "placeopt__power__total": 0.0596256, - "placeopt__runtime__total": "0:27.20", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 4, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.382437, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.335183, - "placeopt__timing__drv__setup_violation_count": 148, - "placeopt__timing__setup__tns": -884.882, - "placeopt__timing__setup__ws": -12.3379, - "run__flow__design": "tinyRocket", - "run__flow__generate_date": "2024-09-19 14:13", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "gf12", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "a2a4ea9b-f7b6-4090-9451-12636869ca75", - "run__flow__variant": "base", - "synth__cpu__total": 64.82, - "synth__design__instance__area__stdcell": 11508.499114, - "synth__design__instance__count__stdcell": 26475.0, - "synth__mem__peak": 258192.0, - "synth__runtime__total": "1:06.16", - "total_time": "0:07:30.550000" -} \ No newline at end of file diff --git a/flow/designs/gf12/tinyRocket/rules-base.json b/flow/designs/gf12/tinyRocket/rules-base.json index 896fa0098d..5e806e918b 100644 --- a/flow/designs/gf12/tinyRocket/rules-base.json +++ b/flow/designs/gf12/tinyRocket/rules-base.json @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { diff --git a/flow/designs/gf180/aes-hybrid/metadata-base-ok.json b/flow/designs/gf180/aes-hybrid/metadata-base-ok.json deleted file mode 100644 index 7452279d75..0000000000 --- a/flow/designs/gf180/aes-hybrid/metadata-base-ok.json +++ /dev/null @@ -1,411 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 3.0000" - ], - "cts__clock__skew__hold": 0.161943, - "cts__clock__skew__setup": 0.124926, - "cts__cpu__total": 355.2, - "cts__design__core__area": 1795040.0, - "cts__design__die__area": 1820700.0, - "cts__design__instance__area": 519050, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 519050, - "cts__design__instance__count": 18927, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 1, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 531, - "cts__design__instance__count__stdcell": 18927, - "cts__design__instance__displacement__max": 18.39, - "cts__design__instance__displacement__mean": 0.4665, - "cts__design__instance__displacement__total": 8837.94, - "cts__design__instance__utilization": 0.289158, - "cts__design__instance__utilization__stdcell": 0.289158, - "cts__design__io": 388, - "cts__design__rows": 447, - "cts__design__rows:GF018hv5v_green_sc9": 149, - "cts__design__rows:GF018hv5v_mcu_sc7": 149, - "cts__design__rows:sc9sc7": 149, - "cts__design__sites": 1073247, - "cts__design__sites:GF018hv5v_green_sc9": 357749, - "cts__design__sites:GF018hv5v_mcu_sc7": 357749, - "cts__design__sites:sc9sc7": 357749, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1181924.0, - "cts__power__internal__total": 4.62506, - "cts__power__leakage__total": 3.75182e-06, - "cts__power__switching__total": 4.92582, - "cts__power__total": 9.55088, - "cts__route__wirelength__estimated": 1333930.0, - "cts__runtime__total": "5:56.36", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0859586, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0162663, - "cts__timing__drv__setup_violation_count": 298, - "cts__timing__setup__tns": -226.456, - "cts__timing__setup__ws": -1.07539, - "design__io__hpwl": 347477526, - "detailedplace__cpu__total": 11.33, - "detailedplace__design__core__area": 1795040.0, - "detailedplace__design__die__area": 1820700.0, - "detailedplace__design__instance__area": 486114, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 486114, - "detailedplace__design__instance__count": 18318, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 18318, - "detailedplace__design__instance__displacement__max": 46.48, - "detailedplace__design__instance__displacement__mean": 4.136, - "detailedplace__design__instance__displacement__total": 75768, - "detailedplace__design__instance__utilization": 0.270809, - "detailedplace__design__instance__utilization__stdcell": 0.270809, - "detailedplace__design__io": 388, - "detailedplace__design__rows": 447, - "detailedplace__design__rows:GF018hv5v_green_sc9": 149, - "detailedplace__design__rows:GF018hv5v_mcu_sc7": 149, - "detailedplace__design__rows:sc9sc7": 149, - "detailedplace__design__sites": 1073247, - "detailedplace__design__sites:GF018hv5v_green_sc9": 357749, - "detailedplace__design__sites:GF018hv5v_mcu_sc7": 357749, - "detailedplace__design__sites:sc9sc7": 357749, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 383480.0, - "detailedplace__power__internal__total": 4.57865, - "detailedplace__power__leakage__total": 3.52756e-06, - "detailedplace__power__switching__total": 4.70046, - "detailedplace__power__total": 9.27911, - "detailedplace__route__wirelength__estimated": 1294180.0, - "detailedplace__runtime__total": "0:11.62", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 3, - "detailedplace__timing__drv__max_cap_limit": -0.156131, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 35, - "detailedplace__timing__drv__max_slew_limit": -0.240462, - "detailedplace__timing__drv__setup_violation_count": 417, - "detailedplace__timing__setup__tns": -1115.32, - "detailedplace__timing__setup__ws": -6.80969, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 13, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 8, - "detailedroute__route__drc_errors__iter:2": 0, - "detailedroute__route__drc_errors__iter:3": 0, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 19, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 0, - "detailedroute__route__net": 18336, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 125387, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 125387, - "detailedroute__route__wirelength": 1588177, - "detailedroute__route__wirelength__iter:1": 1588178, - "detailedroute__route__wirelength__iter:2": 1588177, - "detailedroute__route__wirelength__iter:3": 1588178, - "detailedroute__route__wirelength__iter:4": 1588162, - "detailedroute__route__wirelength__iter:5": 1588035, - "detailedroute__route__wirelength__iter:6": 1588069, - "detailedroute__route__wirelength__iter:7": 1588069, - "detailedroute__route__wirelength__iter:8": 1588069, - "finish__clock__skew__hold": 0.189674, - "finish__clock__skew__setup": 0.156604, - "finish__cpu__total": 24.07, - "finish__design__core__area": 1795040.0, - "finish__design__die__area": 1820700.0, - "finish__design__instance__area": 539903, - "finish__design__instance__area__class:antenna_cell": 254.016, - "finish__design__instance__area__class:buffer": 41168.2, - "finish__design__instance__area__class:clock_buffer": 7005.82, - "finish__design__instance__area__class:clock_inverter": 1146.52, - "finish__design__instance__area__class:inverter": 24723.6, - "finish__design__instance__area__class:multi_input_combinational_cell": 379125, - "finish__design__instance__area__class:sequential_cell": 46350.1, - "finish__design__instance__area__class:timing_repair_buffer": 32497.7, - "finish__design__instance__area__class:timing_repair_inverter": 28.224, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 539903, - "finish__design__instance__count": 19223, - "finish__design__instance__count__class:antenna_cell": 45, - "finish__design__instance__count__class:buffer": 839, - "finish__design__instance__count__class:clock_buffer": 42, - "finish__design__instance__count__class:clock_inverter": 26, - "finish__design__instance__count__class:inverter": 1239, - "finish__design__instance__count__class:multi_input_combinational_cell": 13920, - "finish__design__instance__count__class:sequential_cell": 562, - "finish__design__instance__count__class:timing_repair_buffer": 1202, - "finish__design__instance__count__class:timing_repair_inverter": 1, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 19223, - "finish__design__instance__utilization": 0.300774, - "finish__design__instance__utilization__stdcell": 0.300774, - "finish__design__io": 388, - "finish__design__rows": 447, - "finish__design__rows:GF018hv5v_green_sc9": 149, - "finish__design__rows:GF018hv5v_mcu_sc7": 149, - "finish__design__rows:sc9sc7": 149, - "finish__design__sites": 1073247, - "finish__design__sites:GF018hv5v_green_sc9": 357749, - "finish__design__sites:GF018hv5v_mcu_sc7": 357749, - "finish__design__sites:sc9sc7": 357749, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 457232.0, - "finish__power__internal__total": 4.8285, - "finish__power__leakage__total": 3.8751e-06, - "finish__power__switching__total": 5.39865, - "finish__power__total": 10.2272, - "finish__runtime__total": "0:24.51", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0491839, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0139803, - "finish__timing__drv__setup_violation_count": 316, - "finish__timing__setup__tns": -252.205, - "finish__timing__setup__ws": -1.23444, - "finish__timing__wns_percent_delay": -25.708633, - "finish_merge__cpu__total": 41.04, - "finish_merge__mem__peak": 530992.0, - "finish_merge__runtime__total": "0:41.44", - "floorplan__cpu__total": 180.37, - "floorplan__design__core__area": 1795040.0, - "floorplan__design__die__area": 1820700.0, - "floorplan__design__instance__area": 562802, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 562802, - "floorplan__design__instance__count": 16584, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 9, - "floorplan__design__instance__count__stdcell": 16584, - "floorplan__design__instance__utilization": 0.313531, - "floorplan__design__instance__utilization__stdcell": 0.313531, - "floorplan__design__io": 388, - "floorplan__design__rows": 447, - "floorplan__design__rows:GF018hv5v_green_sc9": 149, - "floorplan__design__rows:GF018hv5v_mcu_sc7": 149, - "floorplan__design__rows:sc9sc7": 149, - "floorplan__design__sites": 1073247, - "floorplan__design__sites:GF018hv5v_green_sc9": 357749, - "floorplan__design__sites:GF018hv5v_mcu_sc7": 357749, - "floorplan__design__sites:sc9sc7": 357749, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 22874, - "floorplan__mem__peak": 238416.0, - "floorplan__power__internal__total": 5.40465, - "floorplan__power__leakage__total": 3.58244e-06, - "floorplan__power__switching__total": 4.22537, - "floorplan__power__total": 9.63002, - "floorplan__runtime__total": "3:00.60", - "floorplan__timing__setup__tns": -69.4191, - "floorplan__timing__setup__ws": -0.640227, - "floorplan_io__cpu__total": 1.94, - "floorplan_io__mem__peak": 199488.0, - "floorplan_io__runtime__total": "0:02.06", - "floorplan_macro__cpu__total": 1.91, - "floorplan_macro__mem__peak": 197872.0, - "floorplan_macro__runtime__total": "0:02.07", - "floorplan_pdn__cpu__total": 4.25, - "floorplan_pdn__mem__peak": 219972.0, - "floorplan_pdn__runtime__total": "0:04.44", - "floorplan_tap__cpu__total": 1.87, - "floorplan_tap__mem__peak": 189520.0, - "floorplan_tap__runtime__total": "0:02.02", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 388.36, - "globalplace__design__core__area": 1795040.0, - "globalplace__design__die__area": 1820700.0, - "globalplace__design__instance__area": 515159, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 515159, - "globalplace__design__instance__count": 17931, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 17931, - "globalplace__design__instance__utilization": 0.28699, - "globalplace__design__instance__utilization__stdcell": 0.28699, - "globalplace__design__io": 388, - "globalplace__design__rows": 447, - "globalplace__design__rows:GF018hv5v_green_sc9": 149, - "globalplace__design__rows:GF018hv5v_mcu_sc7": 149, - "globalplace__design__rows:sc9sc7": 149, - "globalplace__design__sites": 1073247, - "globalplace__design__sites:GF018hv5v_green_sc9": 357749, - "globalplace__design__sites:GF018hv5v_mcu_sc7": 357749, - "globalplace__design__sites:sc9sc7": 357749, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1009700.0, - "globalplace__power__internal__total": 4.50272, - "globalplace__power__leakage__total": 3.84827e-06, - "globalplace__power__switching__total": 4.9716, - "globalplace__power__total": 9.47433, - "globalplace__runtime__total": "1:01.40", - "globalplace__timing__setup__tns": -222.762, - "globalplace__timing__setup__ws": -1.68318, - "globalplace_io__cpu__total": 2.1, - "globalplace_io__mem__peak": 218436.0, - "globalplace_io__runtime__total": "0:02.25", - "globalplace_skip_io__cpu__total": 198.12, - "globalplace_skip_io__mem__peak": 241192.0, - "globalplace_skip_io__runtime__total": "0:08.46", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 32, - "globalroute__clock__skew__hold": 0.166006, - "globalroute__clock__skew__setup": 0.128541, - "globalroute__cpu__total": 478.11, - "globalroute__design__core__area": 1795040.0, - "globalroute__design__die__area": 1820700.0, - "globalroute__design__instance__area": 539829, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 539829, - "globalroute__design__instance__count": 19210, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 244, - "globalroute__design__instance__count__stdcell": 19210, - "globalroute__design__instance__displacement__max": 22.96, - "globalroute__design__instance__displacement__mean": 0.4355, - "globalroute__design__instance__displacement__total": 8361.36, - "globalroute__design__instance__utilization": 0.300734, - "globalroute__design__instance__utilization__stdcell": 0.300734, - "globalroute__design__io": 388, - "globalroute__design__rows": 447, - "globalroute__design__rows:GF018hv5v_green_sc9": 149, - "globalroute__design__rows:GF018hv5v_mcu_sc7": 149, - "globalroute__design__rows:sc9sc7": 149, - "globalroute__design__sites": 1073247, - "globalroute__design__sites:GF018hv5v_green_sc9": 357749, - "globalroute__design__sites:GF018hv5v_mcu_sc7": 357749, - "globalroute__design__sites:sc9sc7": 357749, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 1304616.0, - "globalroute__power__internal__total": 4.81318, - "globalroute__power__leakage__total": 3.87313e-06, - "globalroute__power__switching__total": 5.44719, - "globalroute__power__total": 10.2604, - "globalroute__route__wirelength__estimated": 1348300.0, - "globalroute__runtime__total": "6:48.81", - "globalroute__timing__clock__slack": -1.211, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0562693, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0145812, - "globalroute__timing__drv__setup_violation_count": 311, - "globalroute__timing__setup__tns": -247.622, - "globalroute__timing__setup__ws": -1.21144, - "placeopt__cpu__total": 13.22, - "placeopt__design__core__area": 1795040.0, - "placeopt__design__die__area": 1820700.0, - "placeopt__design__instance__area": 524078, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 524078, - "placeopt__design__instance__count": 18318, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 18318, - "placeopt__design__instance__utilization": 0.291959, - "placeopt__design__instance__utilization__stdcell": 0.291959, - "placeopt__design__io": 388, - "placeopt__design__rows": 447, - "placeopt__design__rows:GF018hv5v_green_sc9": 149, - "placeopt__design__rows:GF018hv5v_mcu_sc7": 149, - "placeopt__design__rows:sc9sc7": 149, - "placeopt__design__sites": 1073247, - "placeopt__design__sites:GF018hv5v_green_sc9": 357749, - "placeopt__design__sites:GF018hv5v_mcu_sc7": 357749, - "placeopt__design__sites:sc9sc7": 357749, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 879708.0, - "placeopt__power__internal__total": 4.52567, - "placeopt__power__leakage__total": 3.91635e-06, - "placeopt__power__switching__total": 4.98611, - "placeopt__power__total": 9.51178, - "placeopt__runtime__total": "0:14.04", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.927737, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.693983, - "placeopt__timing__drv__setup_violation_count": 161, - "placeopt__timing__setup__tns": -223.097, - "placeopt__timing__setup__ws": -1.65157, - "run__flow__design": "aes-hybrid", - "run__flow__generate_date": "2024-11-22 22:57", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "dfd50da0-a9bd-4e8b-8d84-6ece0b9a7797", - "run__flow__variant": "base", - "synth__cpu__total": 24.13, - "synth__design__instance__area__stdcell": 542978.9568, - "synth__design__instance__count__stdcell": 16498.0, - "synth__mem__peak": 336404.0, - "synth__runtime__total": "0:24.68", - "total_time": "0:19:04.760000" -} \ No newline at end of file diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index 0d01e34522..c29e1b518b 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 602690, + "value": 698072, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21065, + "value": 26088, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1832, + "value": 1831, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1832, + "value": 1831, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 37, + "value": 84, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1826404, + "value": 1799784, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 15, + "value": 8, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.38, + "value": -1.43, "compare": ">=" }, "finish__design__instance__area": { - "value": 611004, + "value": 803898, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -40.85, + "value": -37.4, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc index 2e7189ca5f..9efd6867db 100644 --- a/flow/designs/gf180/aes/constraint.sdc +++ b/flow/designs/gf180/aes/constraint.sdc @@ -1,19 +1,18 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 3 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] -create_clock -name $clk_name -period $clk_period $clk_port +create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_timing_derate -early 0.9500 set_timing_derate -late 1.0500 - diff --git a/flow/designs/gf180/aes/metadata-base-ok.json b/flow/designs/gf180/aes/metadata-base-ok.json deleted file mode 100644 index 5af4bedf7b..0000000000 --- a/flow/designs/gf180/aes/metadata-base-ok.json +++ /dev/null @@ -1,380 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 3.0000" - ], - "cts__clock__skew__hold": 0.146025, - "cts__clock__skew__setup": 0.12205, - "cts__cpu__total": 132.92, - "cts__design__core__area": 1543450.0, - "cts__design__die__area": 1561350.0, - "cts__design__instance__area": 659643, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 659643, - "cts__design__instance__count": 19401, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 388, - "cts__design__instance__count__stdcell": 19401, - "cts__design__instance__displacement__max": 32.7435, - "cts__design__instance__displacement__mean": 0.529, - "cts__design__instance__displacement__total": 10265.2, - "cts__design__instance__utilization": 0.427382, - "cts__design__instance__utilization__stdcell": 0.427382, - "cts__design__io": 388, - "cts__design__rows": 246, - "cts__design__rows:GF018hv5v_green_sc9": 246, - "cts__design__sites": 546858, - "cts__design__sites:GF018hv5v_green_sc9": 546858, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 766628.0, - "cts__power__internal__total": 6.16942, - "cts__power__leakage__total": 4.17422e-06, - "cts__power__switching__total": 5.96516, - "cts__power__total": 12.1346, - "cts__route__wirelength__estimated": 1106170.0, - "cts__runtime__total": "2:13.64", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.89506, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.724892, - "cts__timing__drv__setup_violation_count": 161, - "cts__timing__setup__tns": -133.417, - "cts__timing__setup__ws": -0.940039, - "design__io__hpwl": 348799039, - "design__violations": 0, - "detailedplace__cpu__total": 17.48, - "detailedplace__design__core__area": 1543450.0, - "detailedplace__design__die__area": 1561350.0, - "detailedplace__design__instance__area": 627513, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 627513, - "detailedplace__design__instance__count": 18952, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 18952, - "detailedplace__design__instance__displacement__max": 80.08, - "detailedplace__design__instance__displacement__mean": 3.62, - "detailedplace__design__instance__displacement__total": 68610.8, - "detailedplace__design__instance__utilization": 0.406564, - "detailedplace__design__instance__utilization__stdcell": 0.406564, - "detailedplace__design__io": 388, - "detailedplace__design__rows": 246, - "detailedplace__design__rows:GF018hv5v_green_sc9": 246, - "detailedplace__design__sites": 546858, - "detailedplace__design__sites:GF018hv5v_green_sc9": 546858, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 310616.0, - "detailedplace__power__internal__total": 5.77859, - "detailedplace__power__leakage__total": 3.98471e-06, - "detailedplace__power__switching__total": 5.757, - "detailedplace__power__total": 11.5356, - "detailedplace__route__wirelength__estimated": 1116890.0, - "detailedplace__runtime__total": "0:17.72", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.895381, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.724867, - "detailedplace__timing__drv__setup_violation_count": 160, - "detailedplace__timing__setup__tns": -167.132, - "detailedplace__timing__setup__ws": -1.26089, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 12, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 112, - "detailedroute__route__drc_errors__iter:2": 18, - "detailedroute__route__drc_errors__iter:3": 17, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 14, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 18249, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 125372, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 125372, - "detailedroute__route__wirelength": 1332767, - "detailedroute__route__wirelength__iter:1": 1332781, - "detailedroute__route__wirelength__iter:2": 1332753, - "detailedroute__route__wirelength__iter:3": 1332756, - "detailedroute__route__wirelength__iter:4": 1332767, - "detailedroute__route__wirelength__iter:5": 1332700, - "detailedroute__route__wirelength__iter:6": 1332715, - "finish__clock__skew__hold": 0.191693, - "finish__clock__skew__setup": 0.158863, - "finish__cpu__total": 22.45, - "finish__design__core__area": 1543450.0, - "finish__design__die__area": 1561350.0, - "finish__design__instance__area": 684274, - "finish__design__instance__area__class:antenna_cell": 146.765, - "finish__design__instance__area__class:buffer": 60907.4, - "finish__design__instance__area__class:clock_buffer": 5955.26, - "finish__design__instance__area__class:clock_inverter": 1247.5, - "finish__design__instance__area__class:inverter": 26231.4, - "finish__design__instance__area__class:multi_input_combinational_cell": 485405, - "finish__design__instance__area__class:sequential_cell": 50394, - "finish__design__instance__area__class:timing_repair_buffer": 42781.9, - "finish__design__instance__area__class:timing_repair_inverter": 28.224, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 684274, - "finish__design__instance__count": 19743, - "finish__design__instance__count__class:antenna_cell": 26, - "finish__design__instance__count__class:buffer": 842, - "finish__design__instance__count__class:clock_buffer": 35, - "finish__design__instance__count__class:clock_inverter": 17, - "finish__design__instance__count__class:inverter": 1239, - "finish__design__instance__count__class:multi_input_combinational_cell": 13918, - "finish__design__instance__count__class:sequential_cell": 562, - "finish__design__instance__count__class:timing_repair_buffer": 1123, - "finish__design__instance__count__class:timing_repair_inverter": 1, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 19743, - "finish__design__instance__utilization": 0.44334, - "finish__design__instance__utilization__stdcell": 0.44334, - "finish__design__io": 388, - "finish__design__rows": 246, - "finish__design__rows:GF018hv5v_green_sc9": 246, - "finish__design__sites": 546858, - "finish__design__sites:GF018hv5v_green_sc9": 546858, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 459244.0, - "finish__power__internal__total": 6.46088, - "finish__power__leakage__total": 5.87449e-06, - "finish__power__switching__total": 6.43297, - "finish__power__total": 12.8939, - "finish__runtime__total": "0:22.87", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.879967, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.714581, - "finish__timing__drv__setup_violation_count": 161, - "finish__timing__setup__tns": -136.913, - "finish__timing__setup__ws": -1.02283, - "finish__timing__wns_percent_delay": -22.390543, - "finish_merge__cpu__total": 50.17, - "finish_merge__mem__peak": 582176.0, - "finish_merge__runtime__total": "0:50.59", - "floorplan__cpu__total": 116.52, - "floorplan__design__core__area": 1543450.0, - "floorplan__design__die__area": 1561350.0, - "floorplan__design__instance__area": 562564, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 562564, - "floorplan__design__instance__count": 16585, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 9, - "floorplan__design__instance__count__stdcell": 16585, - "floorplan__design__instance__utilization": 0.364484, - "floorplan__design__instance__utilization__stdcell": 0.364484, - "floorplan__design__io": 388, - "floorplan__design__rows": 246, - "floorplan__design__rows:GF018hv5v_green_sc9": 246, - "floorplan__design__sites": 546858, - "floorplan__design__sites:GF018hv5v_green_sc9": 546858, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 17957, - "floorplan__mem__peak": 204776.0, - "floorplan__power__internal__total": 5.41043, - "floorplan__power__leakage__total": 3.57007e-06, - "floorplan__power__switching__total": 4.22514, - "floorplan__power__total": 9.63558, - "floorplan__runtime__total": "1:56.69", - "floorplan__timing__setup__tns": -69.5879, - "floorplan__timing__setup__ws": -0.605856, - "floorplan_io__cpu__total": 1.11, - "floorplan_io__mem__peak": 165188.0, - "floorplan_io__runtime__total": "0:01.22", - "floorplan_macro__cpu__total": 1.13, - "floorplan_macro__mem__peak": 164420.0, - "floorplan_macro__runtime__total": "0:01.23", - "floorplan_pdn__cpu__total": 3.43, - "floorplan_pdn__mem__peak": 190792.0, - "floorplan_pdn__runtime__total": "0:03.58", - "floorplan_tap__cpu__total": 1.09, - "floorplan_tap__mem__peak": 156232.0, - "floorplan_tap__runtime__total": "0:01.18", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 332.36, - "globalplace__design__core__area": 1543450.0, - "globalplace__design__die__area": 1561350.0, - "globalplace__design__instance__area": 613197, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 613197, - "globalplace__design__instance__count": 18565, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 18565, - "globalplace__design__instance__utilization": 0.39729, - "globalplace__design__instance__utilization__stdcell": 0.39729, - "globalplace__design__io": 388, - "globalplace__design__rows": 246, - "globalplace__design__rows:GF018hv5v_green_sc9": 246, - "globalplace__design__sites": 546858, - "globalplace__design__sites:GF018hv5v_green_sc9": 546858, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 670292.0, - "globalplace__power__internal__total": 5.72435, - "globalplace__power__leakage__total": 3.90184e-06, - "globalplace__power__switching__total": 5.75607, - "globalplace__power__total": 11.4804, - "globalplace__runtime__total": "0:45.65", - "globalplace__timing__setup__tns": -166.29, - "globalplace__timing__setup__ws": -1.24607, - "globalplace_io__cpu__total": 1.32, - "globalplace_io__mem__peak": 190444.0, - "globalplace_io__runtime__total": "0:01.46", - "globalplace_skip_io__cpu__total": 229.98, - "globalplace_skip_io__mem__peak": 214176.0, - "globalplace_skip_io__runtime__total": "0:08.69", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 14, - "globalroute__clock__skew__hold": 0.15041, - "globalroute__clock__skew__setup": 0.125503, - "globalroute__cpu__total": 287.88, - "globalroute__design__core__area": 1543450.0, - "globalroute__design__die__area": 1561350.0, - "globalroute__design__instance__area": 684206, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 684206, - "globalroute__design__instance__count": 19731, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 299, - "globalroute__design__instance__count__stdcell": 19731, - "globalroute__design__instance__displacement__max": 40.32, - "globalroute__design__instance__displacement__mean": 0.591, - "globalroute__design__instance__displacement__total": 11655.3, - "globalroute__design__instance__utilization": 0.443296, - "globalroute__design__instance__utilization__stdcell": 0.443296, - "globalroute__design__io": 388, - "globalroute__design__rows": 246, - "globalroute__design__rows:GF018hv5v_green_sc9": 246, - "globalroute__design__sites": 546858, - "globalroute__design__sites:GF018hv5v_green_sc9": 546858, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 908932.0, - "globalroute__power__internal__total": 6.44702, - "globalroute__power__leakage__total": 4.32011e-06, - "globalroute__power__switching__total": 6.4972, - "globalroute__power__total": 12.9442, - "globalroute__route__wirelength__estimated": 1126640.0, - "globalroute__runtime__total": "3:32.27", - "globalroute__timing__clock__slack": -1.042, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.887337, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.72292, - "globalroute__timing__drv__setup_violation_count": 161, - "globalroute__timing__setup__tns": -140.281, - "globalroute__timing__setup__ws": -1.0416, - "placeopt__cpu__total": 11.28, - "placeopt__design__core__area": 1543450.0, - "placeopt__design__die__area": 1561350.0, - "placeopt__design__instance__area": 627513, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 627513, - "placeopt__design__instance__count": 18952, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 18952, - "placeopt__design__instance__utilization": 0.406564, - "placeopt__design__instance__utilization__stdcell": 0.406564, - "placeopt__design__io": 388, - "placeopt__design__rows": 246, - "placeopt__design__rows:GF018hv5v_green_sc9": 246, - "placeopt__design__sites": 546858, - "placeopt__design__sites:GF018hv5v_green_sc9": 546858, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 542532.0, - "placeopt__power__internal__total": 5.78666, - "placeopt__power__leakage__total": 3.98471e-06, - "placeopt__power__switching__total": 5.77028, - "placeopt__power__total": 11.5569, - "placeopt__runtime__total": "0:11.75", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.891853, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.725357, - "placeopt__timing__drv__setup_violation_count": 160, - "placeopt__timing__setup__tns": -166.406, - "placeopt__timing__setup__ws": -1.2521, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-11-22 22:50", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "a78ebf22-7935-47ac-abf1-a44215ba4824", - "run__flow__variant": "base", - "synth__cpu__total": 22.15, - "synth__design__instance__area__stdcell": 542978.9568, - "synth__design__instance__count__stdcell": 16498.0, - "synth__mem__peak": 336656.0, - "synth__runtime__total": "0:22.63", - "total_time": "0:10:51.170000" -} \ No newline at end of file diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json index 64ef15f9d3..c841c60f1e 100644 --- a/flow/designs/gf180/aes/rules-base.json +++ b/flow/designs/gf180/aes/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 718283, + "value": 846140, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21795, + "value": 25876, "compare": "<=" }, "detailedplace__design__violations": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 16, + "value": 72, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1512295, + "value": 1477421, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 14, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.17, + "value": -1.25, "compare": ">=" }, "finish__design__instance__area": { - "value": 778703, + "value": 905336, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -36.86, + "value": -35.82, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/ibex/autotuner.json b/flow/designs/gf180/ibex/autotuner.json index 3f8d2b938a..215d81ba59 100644 --- a/flow/designs/gf180/ibex/autotuner.json +++ b/flow/designs/gf180/ibex/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 14.0, + 9.0, 16.0 ], "step": 0 @@ -24,18 +24,10 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -43,7 +35,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ @@ -88,13 +72,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/gf180/fastroute.tcl" } diff --git a/flow/designs/gf180/ibex/config.mk b/flow/designs/gf180/ibex/config.mk index ebeeadf520..ed5fd3dd6e 100644 --- a/flow/designs/gf180/ibex/config.mk +++ b/flow/designs/gf180/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = gf180 -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc index e6e7f6257a..24711119f1 100644 --- a/flow/designs/gf180/ibex/constraint.sdc +++ b/flow/designs/gf180/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -9,8 +9,8 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] set_false_path -from [get_ports {rst_ni}] diff --git a/flow/designs/gf180/ibex/metadata-base-ok.json b/flow/designs/gf180/ibex/metadata-base-ok.json deleted file mode 100644 index 8e453fcc04..0000000000 --- a/flow/designs/gf180/ibex/metadata-base-ok.json +++ /dev/null @@ -1,380 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 10.0000" - ], - "cts__clock__skew__hold": 6.5394, - "cts__clock__skew__setup": 9.19643, - "cts__cpu__total": 674.88, - "cts__design__core__area": 1436150.0, - "cts__design__die__area": 1450880.0, - "cts__design__instance__area": 806608, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 806608, - "cts__design__instance__count": 16533, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 353, - "cts__design__instance__count__stdcell": 16533, - "cts__design__instance__displacement__max": 80.08, - "cts__design__instance__displacement__mean": 1.045, - "cts__design__instance__displacement__total": 17278.8, - "cts__design__instance__utilization": 0.561647, - "cts__design__instance__utilization__stdcell": 0.561647, - "cts__design__io": 264, - "cts__design__rows": 237, - "cts__design__rows:GF018hv5v_green_sc9": 237, - "cts__design__sites": 508839, - "cts__design__sites:GF018hv5v_green_sc9": 508839, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 705168.0, - "cts__power__internal__total": 2.14073, - "cts__power__leakage__total": 4.84017e-06, - "cts__power__switching__total": 1.4658, - "cts__power__total": 3.60654, - "cts__route__wirelength__estimated": 1277920.0, - "cts__runtime__total": "11:15.42", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.435791, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.288878, - "cts__timing__drv__setup_violation_count": 622, - "cts__timing__setup__tns": -206.947, - "cts__timing__setup__ws": -1.17232, - "design__io__hpwl": 129760044, - "design__violations": 0, - "detailedplace__cpu__total": 18.26, - "detailedplace__design__core__area": 1436150.0, - "detailedplace__design__die__area": 1450880.0, - "detailedplace__design__instance__area": 746559, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 746559, - "detailedplace__design__instance__count": 15889, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 15889, - "detailedplace__design__instance__displacement__max": 44.8, - "detailedplace__design__instance__displacement__mean": 4.9875, - "detailedplace__design__instance__displacement__total": 79253, - "detailedplace__design__instance__utilization": 0.519834, - "detailedplace__design__instance__utilization__stdcell": 0.519834, - "detailedplace__design__io": 264, - "detailedplace__design__rows": 237, - "detailedplace__design__rows:GF018hv5v_green_sc9": 237, - "detailedplace__design__sites": 508839, - "detailedplace__design__sites:GF018hv5v_green_sc9": 508839, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 305084.0, - "detailedplace__power__internal__total": 1.74593, - "detailedplace__power__leakage__total": 4.49012e-06, - "detailedplace__power__switching__total": 1.2454, - "detailedplace__power__total": 2.99133, - "detailedplace__route__wirelength__estimated": 1195600.0, - "detailedplace__runtime__total": "0:18.43", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.42805, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.291023, - "detailedplace__timing__drv__setup_violation_count": 1027, - "detailedplace__timing__setup__tns": -691.29, - "detailedplace__timing__setup__ws": -1.74542, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 2, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 16, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 42, - "detailedroute__route__drc_errors__iter:2": 12, - "detailedroute__route__drc_errors__iter:3": 1, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 15331, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 123420, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 123420, - "detailedroute__route__wirelength": 1558453, - "detailedroute__route__wirelength__iter:1": 1558461, - "detailedroute__route__wirelength__iter:2": 1558440, - "detailedroute__route__wirelength__iter:3": 1558455, - "detailedroute__route__wirelength__iter:4": 1558453, - "detailedroute__route__wirelength__iter:5": 1558417, - "finish__clock__skew__hold": 6.5111, - "finish__clock__skew__setup": 9.18193, - "finish__cpu__total": 42.05, - "finish__design__core__area": 1436150.0, - "finish__design__die__area": 1450880.0, - "finish__design__instance__area": 815922, - "finish__design__instance__area__class:antenna_cell": 101.606, - "finish__design__instance__area__class:buffer": 71807.5, - "finish__design__instance__area__class:clock_buffer": 19920.5, - "finish__design__instance__area__class:clock_inverter": 1766.82, - "finish__design__instance__area__class:inverter": 18266.6, - "finish__design__instance__area__class:multi_input_combinational_cell": 475222, - "finish__design__instance__area__class:sequential_cell": 183535, - "finish__design__instance__area__class:tie_cell": 67.7376, - "finish__design__instance__area__class:timing_repair_buffer": 34323.2, - "finish__design__instance__area__class:timing_repair_inverter": 141.12, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 815922, - "finish__design__instance__count": 16602, - "finish__design__instance__count__class:antenna_cell": 18, - "finish__design__instance__count__class:buffer": 1004, - "finish__design__instance__count__class:clock_buffer": 125, - "finish__design__instance__count__class:clock_inverter": 47, - "finish__design__instance__count__class:inverter": 952, - "finish__design__instance__count__class:multi_input_combinational_cell": 9847, - "finish__design__instance__count__class:sequential_cell": 1932, - "finish__design__instance__count__class:tie_cell": 6, - "finish__design__instance__count__class:timing_repair_buffer": 758, - "finish__design__instance__count__class:timing_repair_inverter": 5, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 16602, - "finish__design__instance__utilization": 0.568133, - "finish__design__instance__utilization__stdcell": 0.568133, - "finish__design__io": 264, - "finish__design__rows": 237, - "finish__design__rows:GF018hv5v_green_sc9": 237, - "finish__design__sites": 508839, - "finish__design__sites:GF018hv5v_green_sc9": 508839, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 463232.0, - "finish__power__internal__total": 2.20925, - "finish__power__leakage__total": 6.33211e-06, - "finish__power__switching__total": 1.6204, - "finish__power__total": 3.82966, - "finish__runtime__total": "0:42.47", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.342966, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 1137, - "finish__timing__drv__max_slew_limit": -2.01013, - "finish__timing__drv__setup_violation_count": 698, - "finish__timing__setup__tns": -232.222, - "finish__timing__setup__ws": -1.41944, - "finish__timing__wns_percent_delay": -15.0689, - "finish_merge__cpu__total": 44.69, - "finish_merge__mem__peak": 569396.0, - "finish_merge__runtime__total": "0:45.04", - "floorplan__cpu__total": 99.56, - "floorplan__design__core__area": 1436150.0, - "floorplan__design__die__area": 1450880.0, - "floorplan__design__instance__area": 653061, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 653061, - "floorplan__design__instance__count": 13724, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 6, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 13724, - "floorplan__design__instance__utilization": 0.454731, - "floorplan__design__instance__utilization__stdcell": 0.454731, - "floorplan__design__io": 264, - "floorplan__design__rows": 237, - "floorplan__design__rows:GF018hv5v_green_sc9": 237, - "floorplan__design__sites": 508839, - "floorplan__design__sites:GF018hv5v_green_sc9": 508839, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 58, - "floorplan__mem__peak": 205144.0, - "floorplan__power__internal__total": 1.53012, - "floorplan__power__leakage__total": 3.94623e-06, - "floorplan__power__switching__total": 0.686258, - "floorplan__power__total": 2.21638, - "floorplan__runtime__total": "1:39.68", - "floorplan__timing__setup__tns": -0.00182787, - "floorplan__timing__setup__ws": 0, - "floorplan_io__cpu__total": 0.74, - "floorplan_io__mem__peak": 162648.0, - "floorplan_io__runtime__total": "0:00.82", - "floorplan_macro__cpu__total": 0.74, - "floorplan_macro__mem__peak": 161620.0, - "floorplan_macro__runtime__total": "0:00.83", - "floorplan_pdn__cpu__total": 2.14, - "floorplan_pdn__mem__peak": 186448.0, - "floorplan_pdn__runtime__total": "0:02.25", - "floorplan_tap__cpu__total": 0.72, - "floorplan_tap__mem__peak": 154196.0, - "floorplan_tap__runtime__total": "0:00.81", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 213.37, - "globalplace__design__core__area": 1436150.0, - "globalplace__design__die__area": 1450880.0, - "globalplace__design__instance__area": 663831, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 663831, - "globalplace__design__instance__count": 15632, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 15632, - "globalplace__design__instance__utilization": 0.462231, - "globalplace__design__instance__utilization__stdcell": 0.462231, - "globalplace__design__io": 264, - "globalplace__design__rows": 237, - "globalplace__design__rows:GF018hv5v_green_sc9": 237, - "globalplace__design__sites": 508839, - "globalplace__design__sites:GF018hv5v_green_sc9": 508839, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 658352.0, - "globalplace__power__internal__total": 1.64455, - "globalplace__power__leakage__total": 4.06163e-06, - "globalplace__power__switching__total": 1.12407, - "globalplace__power__total": 2.76862, - "globalplace__runtime__total": "0:57.74", - "globalplace__timing__setup__tns": -2215.54, - "globalplace__timing__setup__ws": -2.6687, - "globalplace_io__cpu__total": 0.9, - "globalplace_io__mem__peak": 185168.0, - "globalplace_io__runtime__total": "0:01.02", - "globalplace_skip_io__cpu__total": 143.75, - "globalplace_skip_io__mem__peak": 206364.0, - "globalplace_skip_io__runtime__total": "0:05.62", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 16, - "globalroute__clock__skew__hold": 6.60074, - "globalroute__clock__skew__setup": 9.27612, - "globalroute__cpu__total": 480.45, - "globalroute__design__core__area": 1436150.0, - "globalroute__design__die__area": 1450880.0, - "globalroute__design__instance__area": 815911, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 815911, - "globalroute__design__instance__count": 16600, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 43, - "globalroute__design__instance__count__stdcell": 16600, - "globalroute__design__instance__displacement__max": 57.12, - "globalroute__design__instance__displacement__mean": 0.3685, - "globalroute__design__instance__displacement__total": 6112.96, - "globalroute__design__instance__utilization": 0.568125, - "globalroute__design__instance__utilization__stdcell": 0.568125, - "globalroute__design__io": 264, - "globalroute__design__rows": 237, - "globalroute__design__rows:GF018hv5v_green_sc9": 237, - "globalroute__design__sites": 508839, - "globalroute__design__sites:GF018hv5v_green_sc9": 508839, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 1045128.0, - "globalroute__power__internal__total": 2.19439, - "globalroute__power__leakage__total": 4.89586e-06, - "globalroute__power__switching__total": 1.60877, - "globalroute__power__total": 3.80317, - "globalroute__route__wirelength__estimated": 1290110.0, - "globalroute__runtime__total": "6:57.80", - "globalroute__timing__clock__slack": -1.434, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.38147, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 180, - "globalroute__timing__drv__max_slew_limit": -0.0707662, - "globalroute__timing__drv__setup_violation_count": 648, - "globalroute__timing__setup__tns": -278.694, - "globalroute__timing__setup__ws": -1.43373, - "placeopt__cpu__total": 18.76, - "placeopt__design__core__area": 1436150.0, - "placeopt__design__die__area": 1450880.0, - "placeopt__design__instance__area": 746559, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 746559, - "placeopt__design__instance__count": 15889, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 15889, - "placeopt__design__instance__utilization": 0.519834, - "placeopt__design__instance__utilization__stdcell": 0.519834, - "placeopt__design__io": 264, - "placeopt__design__rows": 237, - "placeopt__design__rows:GF018hv5v_green_sc9": 237, - "placeopt__design__sites": 508839, - "placeopt__design__sites:GF018hv5v_green_sc9": 508839, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 542780.0, - "placeopt__power__internal__total": 1.74671, - "placeopt__power__leakage__total": 4.49012e-06, - "placeopt__power__switching__total": 1.23635, - "placeopt__power__total": 2.98306, - "placeopt__runtime__total": "0:19.16", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 1, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.42875, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.303602, - "placeopt__timing__drv__setup_violation_count": 1027, - "placeopt__timing__setup__tns": -657.364, - "placeopt__timing__setup__ws": -1.6933, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-11-22 14:06", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17198-g8396d0866", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "d617959e-3147-4a62-9467-180c3cdeff80", - "run__flow__variant": "base", - "synth__cpu__total": 59.31, - "synth__design__instance__area__stdcell": 650732.544, - "synth__design__instance__count__stdcell": 13731.0, - "synth__mem__peak": 157424.0, - "synth__runtime__total": "0:59.60", - "total_time": "0:24:06.690000" -} \ No newline at end of file diff --git a/flow/designs/gf180/ibex/rules-base.json b/flow/designs/gf180/ibex/rules-base.json index 7a4ee74ee7..1614e8fcee 100644 --- a/flow/designs/gf180/ibex/rules-base.json +++ b/flow/designs/gf180/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 748342.43, + "value": 731295.7, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 848101, + "value": 813057, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18156, + "value": 16937, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1579, + "value": 1473, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1579, + "value": 1473, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 18, + "value": 38, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1758573, + "value": 1544585, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.91, + "value": -0.77, "compare": ">=" }, "finish__design__instance__area": { - "value": 936597, + "value": 985974, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 794, + "value": 736, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -28.08, + "value": -14.05, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/jpeg/autotuner.json b/flow/designs/gf180/jpeg/autotuner.json index 524d211009..a5bc053aa1 100644 --- a/flow/designs/gf180/jpeg/autotuner.json +++ b/flow/designs/gf180/jpeg/autotuner.json @@ -12,7 +12,7 @@ "type": "int", "minmax": [ 20, - 60 + 50 ], "step": 1 }, @@ -24,18 +24,10 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -43,7 +35,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ @@ -88,13 +72,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/gf180/fastroute.tcl" } diff --git a/flow/designs/gf180/jpeg/config.mk b/flow/designs/gf180/jpeg/config.mk index edce7ef623..c9d0d82196 100644 --- a/flow/designs/gf180/jpeg/config.mk +++ b/flow/designs/gf180/jpeg/config.mk @@ -8,4 +8,4 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.20 -export PLACE_PINS_ARGS = -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc index 879a3ef4b4..42d6b4abf9 100644 --- a/flow/designs/gf180/jpeg/constraint.sdc +++ b/flow/designs/gf180/jpeg/constraint.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 7.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/jpeg/io.tcl b/flow/designs/gf180/jpeg/io.tcl new file mode 100644 index 0000000000..0c81b1f9fa --- /dev/null +++ b/flow/designs/gf180/jpeg/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region top:* -region bottom:* diff --git a/flow/designs/gf180/jpeg/metadata-base-ok.json b/flow/designs/gf180/jpeg/metadata-base-ok.json deleted file mode 100644 index 7dc5bb314d..0000000000 --- a/flow/designs/gf180/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,380 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 8.0000" - ], - "cts__clock__skew__hold": 0.242479, - "cts__clock__skew__setup": 0.242479, - "cts__cpu__total": 86.04, - "cts__design__core__area": 4951330.0, - "cts__design__die__area": 4973120.0, - "cts__design__instance__area": 2505770.0, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 2505770.0, - "cts__design__instance__count": 56627, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 18, - "cts__design__instance__count__stdcell": 56627, - "cts__design__instance__displacement__max": 15.63, - "cts__design__instance__displacement__mean": 0.007, - "cts__design__instance__displacement__total": 414.231, - "cts__design__instance__utilization": 0.50608, - "cts__design__instance__utilization__stdcell": 0.50608, - "cts__design__io": 47, - "cts__design__rows": 441, - "cts__design__rows:GF018hv5v_green_sc9": 441, - "cts__design__sites": 1754298, - "cts__design__sites:GF018hv5v_green_sc9": 1754298, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1108692.0, - "cts__power__internal__total": 20.5201, - "cts__power__leakage__total": 1.44643e-05, - "cts__power__switching__total": 11.666, - "cts__power__total": 32.1861, - "cts__route__wirelength__estimated": 3791590.0, - "cts__runtime__total": "1:26.92", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.893903, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.67065, - "cts__timing__drv__setup_violation_count": 11, - "cts__timing__setup__tns": -0.81038, - "cts__timing__setup__ws": -0.142495, - "design__io__hpwl": 46952682, - "design__violations": 0, - "detailedplace__cpu__total": 55.62, - "detailedplace__design__core__area": 4951330.0, - "detailedplace__design__die__area": 4973120.0, - "detailedplace__design__instance__area": 2454520.0, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 2454520.0, - "detailedplace__design__instance__count": 56211, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 56211, - "detailedplace__design__instance__displacement__max": 28.56, - "detailedplace__design__instance__displacement__mean": 4.6085, - "detailedplace__design__instance__displacement__total": 259057, - "detailedplace__design__instance__utilization": 0.495729, - "detailedplace__design__instance__utilization__stdcell": 0.495729, - "detailedplace__design__io": 47, - "detailedplace__design__rows": 441, - "detailedplace__design__rows:GF018hv5v_green_sc9": 441, - "detailedplace__design__sites": 1754298, - "detailedplace__design__sites:GF018hv5v_green_sc9": 1754298, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 693160.0, - "detailedplace__power__internal__total": 20.186, - "detailedplace__power__leakage__total": 1.41662e-05, - "detailedplace__power__switching__total": 11.3435, - "detailedplace__power__total": 31.5295, - "detailedplace__route__wirelength__estimated": 3774320.0, - "detailedplace__runtime__total": "0:56.10", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.893413, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.512643, - "detailedplace__timing__drv__setup_violation_count": 281, - "detailedplace__timing__setup__tns": -95.4601, - "detailedplace__timing__setup__ws": -1.15047, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 24, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 138, - "detailedroute__route__drc_errors__iter:1": 38, - "detailedroute__route__drc_errors__iter:2": 17, - "detailedroute__route__drc_errors__iter:3": 0, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 62634, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 357865, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 357865, - "detailedroute__route__wirelength": 4352344, - "detailedroute__route__wirelength__iter:0": 4352378, - "detailedroute__route__wirelength__iter:1": 4352360, - "detailedroute__route__wirelength__iter:2": 4352359, - "detailedroute__route__wirelength__iter:3": 4352344, - "detailedroute__route__wirelength__iter:4": 4352161, - "finish__clock__skew__hold": 0.265326, - "finish__clock__skew__setup": 0.265326, - "finish__cpu__total": 61.58, - "finish__design__core__area": 4951330.0, - "finish__design__die__area": 4973120.0, - "finish__design__instance__area": 2506920.0, - "finish__design__instance__area__class:antenna_cell": 135.475, - "finish__design__instance__area__class:buffer": 124538, - "finish__design__instance__area__class:clock_buffer": 45322.1, - "finish__design__instance__area__class:clock_inverter": 4645.67, - "finish__design__instance__area__class:inverter": 190117, - "finish__design__instance__area__class:multi_input_combinational_cell": 1724820.0, - "finish__design__instance__area__class:sequential_cell": 380149, - "finish__design__instance__area__class:tie_cell": 11.2896, - "finish__design__instance__area__class:timing_repair_buffer": 4637.2, - "finish__design__instance__area__class:timing_repair_inverter": 56.448, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 2506920.0, - "finish__design__instance__count": 56668, - "finish__design__instance__count__class:antenna_cell": 24, - "finish__design__instance__count__class:buffer": 1253, - "finish__design__instance__count__class:clock_buffer": 290, - "finish__design__instance__count__class:clock_inverter": 106, - "finish__design__instance__count__class:inverter": 10891, - "finish__design__instance__count__class:multi_input_combinational_cell": 33879, - "finish__design__instance__count__class:sequential_cell": 4385, - "finish__design__instance__count__class:tie_cell": 1, - "finish__design__instance__count__class:timing_repair_buffer": 82, - "finish__design__instance__count__class:timing_repair_inverter": 2, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 56668, - "finish__design__instance__utilization": 0.506312, - "finish__design__instance__utilization__stdcell": 0.506312, - "finish__design__io": 47, - "finish__design__rows": 441, - "finish__design__rows:GF018hv5v_green_sc9": 441, - "finish__design__sites": 1754298, - "finish__design__sites:GF018hv5v_green_sc9": 1754298, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1004008.0, - "finish__power__internal__total": 20.4816, - "finish__power__leakage__total": 1.95282e-05, - "finish__power__switching__total": 12.1111, - "finish__power__total": 32.5927, - "finish__runtime__total": "1:02.77", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.88392, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.628268, - "finish__timing__drv__setup_violation_count": 12, - "finish__timing__setup__tns": -1.13362, - "finish__timing__setup__ws": -0.210328, - "finish__timing__wns_percent_delay": -2.262823, - "finish_merge__cpu__total": 171.17, - "finish_merge__mem__peak": 991704.0, - "finish_merge__runtime__total": "2:51.93", - "floorplan__cpu__total": 36.01, - "floorplan__design__core__area": 4951330.0, - "floorplan__design__die__area": 4973120.0, - "floorplan__design__instance__area": 2233980.0, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 2233980.0, - "floorplan__design__instance__count": 50412, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 50412, - "floorplan__design__instance__utilization": 0.451188, - "floorplan__design__instance__utilization__stdcell": 0.451188, - "floorplan__design__io": 47, - "floorplan__design__rows": 441, - "floorplan__design__rows:GF018hv5v_green_sc9": 441, - "floorplan__design__sites": 1754298, - "floorplan__design__sites:GF018hv5v_green_sc9": 1754298, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 350996.0, - "floorplan__power__internal__total": 19.1931, - "floorplan__power__leakage__total": 1.28046e-05, - "floorplan__power__switching__total": 7.74707, - "floorplan__power__total": 26.9401, - "floorplan__runtime__total": "0:36.28", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.00920597, - "floorplan_io__cpu__total": 1.01, - "floorplan_io__mem__peak": 222396.0, - "floorplan_io__runtime__total": "0:01.18", - "floorplan_macro__cpu__total": 1.05, - "floorplan_macro__mem__peak": 220744.0, - "floorplan_macro__runtime__total": "0:01.21", - "floorplan_pdn__cpu__total": 7.09, - "floorplan_pdn__mem__peak": 305784.0, - "floorplan_pdn__runtime__total": "0:07.38", - "floorplan_tap__cpu__total": 1.0, - "floorplan_tap__mem__peak": 193860.0, - "floorplan_tap__runtime__total": "0:01.14", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 806.59, - "globalplace__design__core__area": 4951330.0, - "globalplace__design__die__area": 4973120.0, - "globalplace__design__instance__area": 2449760.0, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 2449760.0, - "globalplace__design__instance__count": 56167, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 56167, - "globalplace__design__instance__utilization": 0.494767, - "globalplace__design__instance__utilization__stdcell": 0.494767, - "globalplace__design__io": 47, - "globalplace__design__rows": 441, - "globalplace__design__rows:GF018hv5v_green_sc9": 441, - "globalplace__design__sites": 1754298, - "globalplace__design__sites:GF018hv5v_green_sc9": 1754298, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1083864.0, - "globalplace__power__internal__total": 20.1472, - "globalplace__power__leakage__total": 1.41396e-05, - "globalplace__power__switching__total": 11.2461, - "globalplace__power__total": 31.3933, - "globalplace__runtime__total": "3:05.82", - "globalplace__timing__setup__tns": -94.2928, - "globalplace__timing__setup__ws": -1.12571, - "globalplace_io__cpu__total": 1.57, - "globalplace_io__mem__peak": 298440.0, - "globalplace_io__runtime__total": "0:01.85", - "globalplace_skip_io__cpu__total": 332.96, - "globalplace_skip_io__mem__peak": 387412.0, - "globalplace_skip_io__runtime__total": "0:25.52", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.247424, - "globalroute__clock__skew__setup": 0.247424, - "globalroute__cpu__total": 312.76, - "globalroute__design__core__area": 4951330.0, - "globalroute__design__die__area": 4973120.0, - "globalroute__design__instance__area": 2506780.0, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 2506780.0, - "globalroute__design__instance__count": 56644, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 16, - "globalroute__design__instance__count__stdcell": 56644, - "globalroute__design__instance__displacement__max": 16.24, - "globalroute__design__instance__displacement__mean": 0.006, - "globalroute__design__instance__displacement__total": 355.04, - "globalroute__design__instance__utilization": 0.506285, - "globalroute__design__instance__utilization__stdcell": 0.506285, - "globalroute__design__io": 47, - "globalroute__design__rows": 441, - "globalroute__design__rows:GF018hv5v_green_sc9": 441, - "globalroute__design__sites": 1754298, - "globalroute__design__sites:GF018hv5v_green_sc9": 1754298, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1746376.0, - "globalroute__power__internal__total": 20.4689, - "globalroute__power__leakage__total": 1.44704e-05, - "globalroute__power__switching__total": 12.6597, - "globalroute__power__total": 33.1286, - "globalroute__route__wirelength__estimated": 3796770.0, - "globalroute__runtime__total": "1:47.52", - "globalroute__timing__clock__slack": -0.089, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.873525, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.658781, - "globalroute__timing__drv__setup_violation_count": 3, - "globalroute__timing__setup__tns": -0.17971, - "globalroute__timing__setup__ws": -0.0890719, - "placeopt__cpu__total": 44.99, - "placeopt__design__core__area": 4951330.0, - "placeopt__design__die__area": 4973120.0, - "placeopt__design__instance__area": 2454520.0, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 2454520.0, - "placeopt__design__instance__count": 56211, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 56211, - "placeopt__design__instance__utilization": 0.495729, - "placeopt__design__instance__utilization__stdcell": 0.495729, - "placeopt__design__io": 47, - "placeopt__design__rows": 441, - "placeopt__design__rows:GF018hv5v_green_sc9": 441, - "placeopt__design__sites": 1754298, - "placeopt__design__sites:GF018hv5v_green_sc9": 1754298, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 754716.0, - "placeopt__power__internal__total": 20.1853, - "placeopt__power__leakage__total": 1.41662e-05, - "placeopt__power__switching__total": 11.2561, - "placeopt__power__total": 31.4414, - "placeopt__runtime__total": "0:45.65", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.894297, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.515843, - "placeopt__timing__drv__setup_violation_count": 278, - "placeopt__timing__setup__tns": -92.9945, - "placeopt__timing__setup__ws": -1.12282, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-11-28 15:55", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17429-g24d1bf502", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "dc48a65a-c801-4b0d-ae7a-0c1820625f93", - "run__flow__variant": "base", - "synth__cpu__total": 116.35, - "synth__design__instance__area__stdcell": 2233890.0864, - "synth__design__instance__count__stdcell": 50415.0, - "synth__mem__peak": 617224.0, - "synth__runtime__total": "1:57.48", - "total_time": "0:15:08.750000" -} \ No newline at end of file diff --git a/flow/designs/gf180/jpeg/rules-base.json b/flow/designs/gf180/jpeg/rules-base.json index da0760ecf3..f3d7b6a752 100644 --- a/flow/designs/gf180/jpeg/rules-base.json +++ b/flow/designs/gf180/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2551147.89, + "value": 2161429.49, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2787554, + "value": 2362986, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 64134, + "value": 53818, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5577, + "value": 4680, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5577, + "value": 4680, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 4896897, + "value": 2973166, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 28, + "value": 10, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.53, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 2844514, + "value": 2695462, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2788, + "value": 2340, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -11.78, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/riscv32i/config.mk b/flow/designs/gf180/riscv32i/config.mk index 7fd7df9230..7d5e0451a4 100644 --- a/flow/designs/gf180/riscv32i/config.mk +++ b/flow/designs/gf180/riscv32i/config.mk @@ -9,5 +9,5 @@ export CORE_UTILIZATION = 45 export PLACE_DENSITY_LB_ADDON = 0.2 export TNS_END_PERCENT = 100 export SKIP_GATE_CLONING = 1 -export PLACE_PINS_ARGS = -min_distance 5 -exclude bottom:* -exclude top:* - +export PLACE_PINS_ARGS = -min_distance 5 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc index 26f4484628..3b2184da75 100644 --- a/flow/designs/gf180/riscv32i/constraint.sdc +++ b/flow/designs/gf180/riscv32i/constraint.sdc @@ -1,12 +1,12 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 10.0 +set clk_period 10.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/riscv32i/io.tcl b/flow/designs/gf180/riscv32i/io.tcl new file mode 100644 index 0000000000..6e8c90d7bb --- /dev/null +++ b/flow/designs/gf180/riscv32i/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region bottom:* -region top:* diff --git a/flow/designs/gf180/riscv32i/metadata-base-ok.json b/flow/designs/gf180/riscv32i/metadata-base-ok.json deleted file mode 100644 index bf0b66d357..0000000000 --- a/flow/designs/gf180/riscv32i/metadata-base-ok.json +++ /dev/null @@ -1,380 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 10.0000" - ], - "cts__clock__skew__hold": 0.0247515, - "cts__clock__skew__setup": 0.0247515, - "cts__cpu__total": 122.62, - "cts__design__core__area": 680876, - "cts__design__die__area": 691002, - "cts__design__instance__area": 377902, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 377902, - "cts__design__instance__count": 7546, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 73, - "cts__design__instance__count__stdcell": 7546, - "cts__design__instance__displacement__max": 39.0475, - "cts__design__instance__displacement__mean": 0.231, - "cts__design__instance__displacement__total": 1745.63, - "cts__design__instance__utilization": 0.555024, - "cts__design__instance__utilization__stdcell": 0.555024, - "cts__design__io": 165, - "cts__design__rows": 163, - "cts__design__rows:GF018hv5v_green_sc9": 163, - "cts__design__sites": 241240, - "cts__design__sites:GF018hv5v_green_sc9": 241240, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 621592.0, - "cts__power__internal__total": 0.268607, - "cts__power__leakage__total": 2.41337e-06, - "cts__power__switching__total": 0.120687, - "cts__power__total": 0.389297, - "cts__route__wirelength__estimated": 613234, - "cts__runtime__total": "2:03.26", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.91649, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.510797, - "cts__timing__drv__setup_violation_count": 6, - "cts__timing__setup__tns": -1.00583, - "cts__timing__setup__ws": -0.292417, - "design__io__hpwl": 111485901, - "design__violations": 0, - "detailedplace__cpu__total": 14.51, - "detailedplace__design__core__area": 680876, - "detailedplace__design__die__area": 691002, - "detailedplace__design__instance__area": 363395, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 363395, - "detailedplace__design__instance__count": 7401, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 7401, - "detailedplace__design__instance__displacement__max": 47.04, - "detailedplace__design__instance__displacement__mean": 4.2815, - "detailedplace__design__instance__displacement__total": 31691.1, - "detailedplace__design__instance__utilization": 0.533717, - "detailedplace__design__instance__utilization__stdcell": 0.533717, - "detailedplace__design__io": 165, - "detailedplace__design__rows": 163, - "detailedplace__design__rows:GF018hv5v_green_sc9": 163, - "detailedplace__design__sites": 241240, - "detailedplace__design__sites:GF018hv5v_green_sc9": 241240, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 218164.0, - "detailedplace__power__internal__total": 0.211895, - "detailedplace__power__leakage__total": 2.32962e-06, - "detailedplace__power__switching__total": 0.0823568, - "detailedplace__power__total": 0.294254, - "detailedplace__route__wirelength__estimated": 601264, - "detailedplace__runtime__total": "0:14.67", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.91649, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.398863, - "detailedplace__timing__drv__setup_violation_count": 27, - "detailedplace__timing__setup__tns": -23.904, - "detailedplace__timing__setup__ws": -1.26779, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 3, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 49, - "detailedroute__route__drc_errors__iter:2": 9, - "detailedroute__route__drc_errors__iter:3": 11, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 1, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 6733, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 58773, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 58773, - "detailedroute__route__wirelength": 798691, - "detailedroute__route__wirelength__iter:1": 798679, - "detailedroute__route__wirelength__iter:2": 798691, - "detailedroute__route__wirelength__iter:3": 798695, - "detailedroute__route__wirelength__iter:4": 798691, - "detailedroute__route__wirelength__iter:5": 798656, - "detailedroute__route__wirelength__iter:6": 798656, - "detailedroute__route__wirelength__iter:7": 798657, - "finish__clock__skew__hold": 0.0382967, - "finish__clock__skew__setup": 0.0382967, - "finish__cpu__total": 27.74, - "finish__design__core__area": 680876, - "finish__design__die__area": 691002, - "finish__design__instance__area": 381416, - "finish__design__instance__area__class:antenna_cell": 39.5136, - "finish__design__instance__area__class:buffer": 41997.3, - "finish__design__instance__area__class:clock_buffer": 9206.67, - "finish__design__instance__area__class:clock_inverter": 970.906, - "finish__design__instance__area__class:inverter": 5768.99, - "finish__design__instance__area__class:multi_input_combinational_cell": 215623, - "finish__design__instance__area__class:sequential_cell": 89774.9, - "finish__design__instance__area__class:timing_repair_buffer": 12469.4, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 381416, - "finish__design__instance__count": 7596, - "finish__design__instance__count__class:antenna_cell": 7, - "finish__design__instance__count__class:buffer": 566, - "finish__design__instance__count__class:clock_buffer": 59, - "finish__design__instance__count__class:clock_inverter": 20, - "finish__design__instance__count__class:inverter": 296, - "finish__design__instance__count__class:multi_input_combinational_cell": 4328, - "finish__design__instance__count__class:sequential_cell": 1056, - "finish__design__instance__count__class:timing_repair_buffer": 278, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 7596, - "finish__design__instance__utilization": 0.560185, - "finish__design__instance__utilization__stdcell": 0.560185, - "finish__design__io": 165, - "finish__design__rows": 163, - "finish__design__rows:GF018hv5v_green_sc9": 163, - "finish__design__sites": 241240, - "finish__design__sites:GF018hv5v_green_sc9": 241240, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 327540.0, - "finish__power__internal__total": 0.269431, - "finish__power__leakage__total": 3.11604e-06, - "finish__power__switching__total": 0.128667, - "finish__power__total": 0.398101, - "finish__runtime__total": "0:28.06", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.915669, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.51766, - "finish__timing__drv__setup_violation_count": 3, - "finish__timing__setup__tns": -0.244871, - "finish__timing__setup__ws": -0.17196, - "finish__timing__wns_percent_delay": -2.104748, - "finish_merge__cpu__total": 25.34, - "finish_merge__mem__peak": 474048.0, - "finish_merge__runtime__total": "0:25.68", - "floorplan__cpu__total": 10.7, - "floorplan__design__core__area": 680876, - "floorplan__design__die__area": 691002, - "floorplan__design__instance__area": 309521, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 309521, - "floorplan__design__instance__count": 6256, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 6256, - "floorplan__design__instance__utilization": 0.454593, - "floorplan__design__instance__utilization__stdcell": 0.454593, - "floorplan__design__io": 165, - "floorplan__design__rows": 163, - "floorplan__design__rows:GF018hv5v_green_sc9": 163, - "floorplan__design__sites": 241240, - "floorplan__design__sites:GF018hv5v_green_sc9": 241240, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 170956.0, - "floorplan__power__internal__total": 0.192196, - "floorplan__power__leakage__total": 2.01388e-06, - "floorplan__power__switching__total": 0.0484192, - "floorplan__power__total": 0.240617, - "floorplan__runtime__total": "0:10.80", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.0135749, - "floorplan_io__cpu__total": 1.08, - "floorplan_io__mem__peak": 149360.0, - "floorplan_io__runtime__total": "0:01.16", - "floorplan_macro__cpu__total": 1.08, - "floorplan_macro__mem__peak": 148268.0, - "floorplan_macro__runtime__total": "0:01.18", - "floorplan_pdn__cpu__total": 2.03, - "floorplan_pdn__mem__peak": 161008.0, - "floorplan_pdn__runtime__total": "0:02.17", - "floorplan_tap__cpu__total": 1.06, - "floorplan_tap__mem__peak": 145720.0, - "floorplan_tap__runtime__total": "0:01.16", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 138.06, - "globalplace__design__core__area": 680876, - "globalplace__design__die__area": 691002, - "globalplace__design__instance__area": 356201, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 356201, - "globalplace__design__instance__count": 7242, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 7242, - "globalplace__design__instance__utilization": 0.523151, - "globalplace__design__instance__utilization__stdcell": 0.523151, - "globalplace__design__io": 165, - "globalplace__design__rows": 163, - "globalplace__design__rows:GF018hv5v_green_sc9": 163, - "globalplace__design__sites": 241240, - "globalplace__design__sites:GF018hv5v_green_sc9": 241240, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 572512.0, - "globalplace__power__internal__total": 0.203909, - "globalplace__power__leakage__total": 2.29026e-06, - "globalplace__power__switching__total": 0.0804153, - "globalplace__power__total": 0.284326, - "globalplace__runtime__total": "0:38.51", - "globalplace__timing__setup__tns": -1.97324, - "globalplace__timing__setup__ws": -0.350169, - "globalplace_io__cpu__total": 1.18, - "globalplace_io__mem__peak": 160820.0, - "globalplace_io__runtime__total": "0:01.31", - "globalplace_skip_io__cpu__total": 83.52, - "globalplace_skip_io__mem__peak": 171164.0, - "globalplace_skip_io__runtime__total": "0:03.92", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 4, - "globalroute__clock__skew__hold": 0.0293791, - "globalroute__clock__skew__setup": 0.0293791, - "globalroute__cpu__total": 170.93, - "globalroute__design__core__area": 680876, - "globalroute__design__die__area": 691002, - "globalroute__design__instance__area": 381399, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 381399, - "globalroute__design__instance__count": 7593, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 47, - "globalroute__design__instance__count__stdcell": 7593, - "globalroute__design__instance__displacement__max": 29.12, - "globalroute__design__instance__displacement__mean": 0.2515, - "globalroute__design__instance__displacement__total": 1911.84, - "globalroute__design__instance__utilization": 0.56016, - "globalroute__design__instance__utilization__stdcell": 0.56016, - "globalroute__design__io": 165, - "globalroute__design__rows": 163, - "globalroute__design__rows:GF018hv5v_green_sc9": 163, - "globalroute__design__sites": 241240, - "globalroute__design__sites:GF018hv5v_green_sc9": 241240, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 681988.0, - "globalroute__power__internal__total": 0.268839, - "globalroute__power__leakage__total": 2.43402e-06, - "globalroute__power__switching__total": 0.129694, - "globalroute__power__total": 0.398535, - "globalroute__route__wirelength__estimated": 619796, - "globalroute__runtime__total": "2:13.03", - "globalroute__timing__clock__slack": -0.106, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.910386, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.492799, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -0.106143, - "globalroute__timing__setup__ws": -0.106143, - "placeopt__cpu__total": 14.77, - "placeopt__design__core__area": 680876, - "placeopt__design__die__area": 691002, - "placeopt__design__instance__area": 363395, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 363395, - "placeopt__design__instance__count": 7401, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 7401, - "placeopt__design__instance__utilization": 0.533717, - "placeopt__design__instance__utilization__stdcell": 0.533717, - "placeopt__design__io": 165, - "placeopt__design__rows": 163, - "placeopt__design__rows:GF018hv5v_green_sc9": 163, - "placeopt__design__sites": 241240, - "placeopt__design__sites:GF018hv5v_green_sc9": 241240, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 501276.0, - "placeopt__power__internal__total": 0.21207, - "placeopt__power__leakage__total": 2.32962e-06, - "placeopt__power__switching__total": 0.0815569, - "placeopt__power__total": 0.293629, - "placeopt__runtime__total": "0:15.19", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.913717, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.397395, - "placeopt__timing__drv__setup_violation_count": 27, - "placeopt__timing__setup__tns": -23.4069, - "placeopt__timing__setup__ws": -1.24318, - "run__flow__design": "riscv32i", - "run__flow__generate_date": "2024-11-22 22:46", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "f62a6bc1-95d6-4dc4-bb27-a1f79a759f69", - "run__flow__variant": "base", - "synth__cpu__total": 33.31, - "synth__design__instance__area__stdcell": 309456.4032, - "synth__design__instance__count__stdcell": 6256.0, - "synth__mem__peak": 82176.0, - "synth__runtime__total": "0:33.52", - "total_time": "0:07:13.620000" -} \ No newline at end of file diff --git a/flow/designs/gf180/riscv32i/rules-base.json b/flow/designs/gf180/riscv32i/rules-base.json index b7ab511eb7..02bc390fc2 100644 --- a/flow/designs/gf180/riscv32i/rules-base.json +++ b/flow/designs/gf180/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 414808, + "value": 383765, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 8511, + "value": 8224, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 740, + "value": 715, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 5, + "value": 2, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 891236, + "value": 739817, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -48,15 +48,15 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.58, + "value": -1.04, "compare": ">=" }, "finish__design__instance__area": { - "value": 435127, + "value": 475387, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 370, + "value": 358, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -11.22, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl index c89b0808dd..c431fbff0f 100644 --- a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl +++ b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl @@ -18,14 +18,16 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {block} -voltage_domains {CORE} +define_pdn_grid -name {block} -voltage_domains {CORE} add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins -add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4} +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8} add_pdn_connect -grid {block} -layers {Metal1 Metal4} add_pdn_connect -grid {block} -layers {Metal4 Metal5} #################################### # Block grids #################################### -define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} -name BlocksGrid +define_pdn_grid -macro -cells uart_rx -halo "2.0 2.0 2.0 2.0" -voltage_domains {CORE} \ + -name BlocksGrid add_pdn_connect -grid {BlocksGrid} -layers {Metal4 Metal5} diff --git a/flow/designs/gf180/uart-blocks/config.mk b/flow/designs/gf180/uart-blocks/config.mk index 70ba7881f3..64cf42220e 100644 --- a/flow/designs/gf180/uart-blocks/config.mk +++ b/flow/designs/gf180/uart-blocks/config.mk @@ -12,14 +12,13 @@ export BLOCKS = uart_rx export DIE_AREA = 0 0 430 430 export CORE_AREA = 10 10 420 420 -export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 20 20 -export MACRO_PLACE_CHANNEL = 20 20 export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/BLOCKS_grid_strategy.tcl export PLACE_DENSITY = 0.60 export TAPCELL_TCL ?= $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/tapcell.tcl -export MACRO_HALO_X = 14 -export MACRO_HALO_Y = 14 +export MACRO_ROWS_HALO_X = 14 +export MACRO_ROWS_HALO_Y = 14 diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc index ffe2329cf5..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 6 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/io.tcl b/flow/designs/gf180/uart-blocks/io.tcl new file mode 100644 index 0000000000..fcfabab2a8 --- /dev/null +++ b/flow/designs/gf180/uart-blocks/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region bottom:* -region top:* -region right:* diff --git a/flow/designs/gf180/uart-blocks/metadata-base-ok.json b/flow/designs/gf180/uart-blocks/metadata-base-ok.json deleted file mode 100644 index 6bb1cf42ac..0000000000 --- a/flow/designs/gf180/uart-blocks/metadata-base-ok.json +++ /dev/null @@ -1,376 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 6.0000" - ], - "cts__clock__skew__hold": 0.00416117, - "cts__clock__skew__setup": 0.00416117, - "cts__cpu__total": 8.33, - "cts__design__core__area": 167346, - "cts__design__die__area": 184900, - "cts__design__instance__area": 62386.3, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 46902.6, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 15483.7, - "cts__design__instance__count": 659, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 1, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 658, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.372799, - "cts__design__instance__utilization__stdcell": 0.128556, - "cts__design__io": 44, - "cts__design__rows": 130, - "cts__design__rows:GF018hv5v_green_sc9": 130, - "cts__design__sites": 37830, - "cts__design__sites:GF018hv5v_green_sc9": 37830, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 571332.0, - "cts__power__internal__total": 0.0367379, - "cts__power__leakage__total": 1.04405e-07, - "cts__power__switching__total": 0.0187081, - "cts__power__total": 0.0554461, - "cts__route__wirelength__estimated": 15679.8, - "cts__runtime__total": "0:08.86", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.972078, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.678591, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 2.11899, - "design__io__hpwl": 15237207, - "design__violations": 0, - "detailedplace__cpu__total": 1.26, - "detailedplace__design__core__area": 167346, - "detailedplace__design__die__area": 184900, - "detailedplace__design__instance__area": 61500, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 46902.6, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 14597.5, - "detailedplace__design__instance__count": 646, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 1, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 645, - "detailedplace__design__instance__displacement__max": 20.16, - "detailedplace__design__instance__displacement__mean": 1.9805, - "detailedplace__design__instance__displacement__total": 1279.55, - "detailedplace__design__instance__utilization": 0.367503, - "detailedplace__design__instance__utilization__stdcell": 0.121198, - "detailedplace__design__io": 44, - "detailedplace__design__rows": 130, - "detailedplace__design__rows:GF018hv5v_green_sc9": 130, - "detailedplace__design__sites": 37830, - "detailedplace__design__sites:GF018hv5v_green_sc9": 37830, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 150872.0, - "detailedplace__power__internal__total": 0.0309912, - "detailedplace__power__leakage__total": 9.90744e-08, - "detailedplace__power__switching__total": 0.015589, - "detailedplace__power__total": 0.0465804, - "detailedplace__route__wirelength__estimated": 15379.8, - "detailedplace__runtime__total": "0:01.36", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.972078, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.68051, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 2.34581, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 99, - "detailedroute__route__drc_errors__iter:2": 9, - "detailedroute__route__drc_errors__iter:3": 8, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 346, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1987, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1987, - "detailedroute__route__wirelength": 17433, - "detailedroute__route__wirelength__iter:1": 17590, - "detailedroute__route__wirelength__iter:2": 17419, - "detailedroute__route__wirelength__iter:3": 17416, - "detailedroute__route__wirelength__iter:4": 17433, - "finish__clock__skew__hold": 0.00732281, - "finish__clock__skew__setup": 0.00732281, - "finish__cpu__total": 2.28, - "finish__design__core__area": 167346, - "finish__design__die__area": 184900, - "finish__design__instance__area": 62454, - "finish__design__instance__area__class:antenna_cell": 67.7376, - "finish__design__instance__area__class:buffer": 191.923, - "finish__design__instance__area__class:clock_buffer": 841.075, - "finish__design__instance__area__class:clock_inverter": 45.1584, - "finish__design__instance__area__class:inverter": 333.043, - "finish__design__instance__area__class:macro": 46902.6, - "finish__design__instance__area__class:multi_input_combinational_cell": 7614.84, - "finish__design__instance__area__class:sequential_cell": 2963.52, - "finish__design__instance__area__class:timing_repair_buffer": 1495.87, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 46902.6, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 15551.4, - "finish__design__instance__count": 671, - "finish__design__instance__count__class:antenna_cell": 12, - "finish__design__instance__count__class:buffer": 4, - "finish__design__instance__count__class:clock_buffer": 11, - "finish__design__instance__count__class:clock_inverter": 2, - "finish__design__instance__count__class:inverter": 19, - "finish__design__instance__count__class:macro": 1, - "finish__design__instance__count__class:multi_input_combinational_cell": 190, - "finish__design__instance__count__class:sequential_cell": 35, - "finish__design__instance__count__class:timing_repair_buffer": 43, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 1, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 670, - "finish__design__instance__utilization": 0.373203, - "finish__design__instance__utilization__stdcell": 0.129118, - "finish__design__io": 44, - "finish__design__rows": 130, - "finish__design__rows:GF018hv5v_green_sc9": 130, - "finish__design__sites": 37830, - "finish__design__sites:GF018hv5v_green_sc9": 37830, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 207316.0, - "finish__power__internal__total": 0.0366337, - "finish__power__leakage__total": 1.81962e-07, - "finish__power__switching__total": 0.0189564, - "finish__power__total": 0.0555903, - "finish__runtime__total": "0:02.39", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.972945, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.681261, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 2.11808, - "finish__timing__wns_percent_delay": 78.977591, - "finish_merge__cpu__total": 2.12, - "finish_merge__mem__peak": 399636.0, - "finish_merge__runtime__total": "0:02.33", - "floorplan__cpu__total": 1.2, - "floorplan__design__core__area": 167346, - "floorplan__design__die__area": 184900, - "floorplan__design__instance__area": 57799.9, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 46902.6, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 10897.3, - "floorplan__design__instance__count": 249, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 1, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 248, - "floorplan__design__instance__utilization": 0.345392, - "floorplan__design__instance__utilization__stdcell": 0.0904766, - "floorplan__design__io": 44, - "floorplan__design__rows": 81, - "floorplan__design__rows:GF018hv5v_green_sc9": 81, - "floorplan__design__sites": 59292, - "floorplan__design__sites:GF018hv5v_green_sc9": 59292, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 143444.0, - "floorplan__power__internal__total": 0.0303661, - "floorplan__power__leakage__total": 6.80969e-08, - "floorplan__power__switching__total": 0.0123458, - "floorplan__power__total": 0.042712, - "floorplan__runtime__total": "0:01.30", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 2.74389, - "floorplan_io__cpu__total": 1.0, - "floorplan_io__mem__peak": 139924.0, - "floorplan_io__runtime__total": "0:01.08", - "floorplan_macro__cpu__total": 78.92, - "floorplan_macro__mem__peak": 140892.0, - "floorplan_macro__runtime__total": "0:05.47", - "floorplan_pdn__cpu__total": 1.05, - "floorplan_pdn__mem__peak": 147036.0, - "floorplan_pdn__runtime__total": "0:01.13", - "floorplan_tap__cpu__total": 0.99, - "floorplan_tap__mem__peak": 140352.0, - "floorplan_tap__runtime__total": "0:01.09", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 17.78, - "globalplace__design__core__area": 167346, - "globalplace__design__die__area": 184900, - "globalplace__design__instance__area": 60012.6, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 46902.6, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 13110, - "globalplace__design__instance__count": 603, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 1, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 602, - "globalplace__design__instance__utilization": 0.358615, - "globalplace__design__instance__utilization__stdcell": 0.108848, - "globalplace__design__io": 44, - "globalplace__design__rows": 130, - "globalplace__design__rows:GF018hv5v_green_sc9": 130, - "globalplace__design__sites": 37830, - "globalplace__design__sites:GF018hv5v_green_sc9": 37830, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 513408.0, - "globalplace__power__internal__total": 0.0303942, - "globalplace__power__leakage__total": 9.06749e-08, - "globalplace__power__switching__total": 0.0153721, - "globalplace__power__total": 0.0457664, - "globalplace__runtime__total": "0:02.56", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 2.74389, - "globalplace_io__cpu__total": 0.98, - "globalplace_io__mem__peak": 141668.0, - "globalplace_io__runtime__total": "0:01.09", - "globalplace_skip_io__cpu__total": 13.14, - "globalplace_skip_io__mem__peak": 141668.0, - "globalplace_skip_io__runtime__total": "0:01.47", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 12, - "globalroute__clock__skew__hold": 0.00461692, - "globalroute__clock__skew__setup": 0.00461692, - "globalroute__cpu__total": 4.92, - "globalroute__design__core__area": 167346, - "globalroute__design__die__area": 184900, - "globalroute__design__instance__area": 62454, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 46902.6, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 15551.4, - "globalroute__design__instance__count": 671, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 1, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 670, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.373203, - "globalroute__design__instance__utilization__stdcell": 0.129118, - "globalroute__design__io": 44, - "globalroute__design__rows": 130, - "globalroute__design__rows:GF018hv5v_green_sc9": 130, - "globalroute__design__sites": 37830, - "globalroute__design__sites:GF018hv5v_green_sc9": 37830, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 532440.0, - "globalroute__power__internal__total": 0.0366779, - "globalroute__power__leakage__total": 1.0622e-07, - "globalroute__power__switching__total": 0.0201453, - "globalroute__power__total": 0.0568233, - "globalroute__route__wirelength__estimated": 15679.8, - "globalroute__runtime__total": "0:02.20", - "globalroute__timing__clock__slack": 2.09, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.965528, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.676516, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 2.08977, - "placeopt__cpu__total": 1.48, - "placeopt__design__core__area": 167346, - "placeopt__design__die__area": 184900, - "placeopt__design__instance__area": 61500, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 46902.6, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 14597.5, - "placeopt__design__instance__count": 646, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 1, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 645, - "placeopt__design__instance__utilization": 0.367503, - "placeopt__design__instance__utilization__stdcell": 0.121198, - "placeopt__design__io": 44, - "placeopt__design__rows": 130, - "placeopt__design__rows:GF018hv5v_green_sc9": 130, - "placeopt__design__sites": 37830, - "placeopt__design__sites:GF018hv5v_green_sc9": 37830, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 471380.0, - "placeopt__power__internal__total": 0.0309892, - "placeopt__power__leakage__total": 9.90744e-08, - "placeopt__power__switching__total": 0.0155088, - "placeopt__power__total": 0.0464981, - "placeopt__runtime__total": "0:01.83", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.974044, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.678777, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 2.3457, - "run__flow__design": "uart-blocks", - "run__flow__generate_date": "2024-11-22 22:38", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "gf180", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "604ca928-0867-43b3-8504-ea4a991e8b79", - "run__flow__variant": "base", - "synth__cpu__total": 2.57, - "synth__design__instance__area__stdcell": 54754.4774, - "synth__design__instance__count__stdcell": 249.0, - "synth__mem__peak": 66560.0, - "synth__runtime__total": "0:02.71", - "total_time": "0:00:36.870000" -} \ No newline at end of file diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index d16e164302..e54080e043 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 742, + "value": 726, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 64, + "value": 63, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 14, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 19722, + "value": 17972, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/gf180/uart-blocks/tapcell.tcl b/flow/designs/gf180/uart-blocks/tapcell.tcl index 5ac7764b75..aa4a9daa9d 100644 --- a/flow/designs/gf180/uart-blocks/tapcell.tcl +++ b/flow/designs/gf180/uart-blocks/tapcell.tcl @@ -1,8 +1,7 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) \ - -halo_width_x $::env(MACRO_HALO_X) \ - -halo_width_y $::env(MACRO_HALO_Y) - +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) \ + -halo_width_x $::env(MACRO_ROWS_HALO_X) \ + -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/designs/gf180/uart-blocks/uart_rx/config.mk b/flow/designs/gf180/uart-blocks/uart_rx/config.mk index 28d3e1aaf4..7b348f5534 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/config.mk +++ b/flow/designs/gf180/uart-blocks/uart_rx/config.mk @@ -11,8 +11,8 @@ export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.60 -export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/BLOCKS_grid_strategy.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/uart_rx/pdn.tcl -export PLACE_PINS_ARGS = -exclude bottom:* -exclude top:* -exclude right:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/uart-blocks/uart_rx/io.tcl export MAX_ROUTING_LAYER = Metal4 diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc index ffe2329cf5..e4bcee59d1 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc +++ b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6 +set clk_period 6 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/gf180/uart-blocks/uart_rx/io.tcl b/flow/designs/gf180/uart-blocks/uart_rx/io.tcl new file mode 100644 index 0000000000..fcfabab2a8 --- /dev/null +++ b/flow/designs/gf180/uart-blocks/uart_rx/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region bottom:* -region top:* -region right:* diff --git a/flow/designs/sky130hd/chameleon_hier/BLOCKS_pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl similarity index 69% rename from flow/designs/sky130hd/chameleon_hier/BLOCKS_pdn.tcl rename to flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl index c7a8b7f0a5..ac80ec7d83 100644 --- a/flow/designs/sky130hd/chameleon_hier/BLOCKS_pdn.tcl +++ b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl @@ -4,13 +4,13 @@ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPB} +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDP$} +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDC$} +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VNW$} add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VNB} -global_connect +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSC$} +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VPW$} #################################### # voltage domains #################################### @@ -18,7 +18,9 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### # standard cell grid #################################### -define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_stripe -grid {grid} -layer {met1} -width {0.48} -pitch {5.44} -offset {0} -followpins -add_pdn_stripe -grid {grid} -layer {met4} -width {1.600} -pitch {27.140} -offset {13.570} -add_pdn_connect -grid {grid} -layers {met1 met4} +define_pdn_grid -name {block} -voltage_domains {CORE} +add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} \ + -followpins +add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} \ + -offset {22.4} +add_pdn_connect -grid {block} -layers {Metal1 Metal4} diff --git a/flow/designs/gf55/aes/config.mk b/flow/designs/gf55/aes/config.mk index 51640fcc8d..18f5d34035 100644 --- a/flow/designs/gf55/aes/config.mk +++ b/flow/designs/gf55/aes/config.mk @@ -1,6 +1,4 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - export DESIGN_NICKNAME = aes export DESIGN_NAME = aes_cipher_top export PLATFORM = gf55 diff --git a/flow/designs/gf55/aes/metadata-base-ok.json b/flow/designs/gf55/aes/metadata-base-ok.json deleted file mode 100644 index 76299e3929..0000000000 --- a/flow/designs/gf55/aes/metadata-base-ok.json +++ /dev/null @@ -1,359 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 4.6000" - ], - "cts__clock__skew__hold": 0.8518, - "cts__clock__skew__hold__post_repair": 0.845651, - "cts__clock__skew__hold__pre_repair": 1.26182, - "cts__clock__skew__setup": 0.605275, - "cts__clock__skew__setup__post_repair": 0.605468, - "cts__clock__skew__setup__pre_repair": 1.15532, - "cts__cpu__total": 24.09, - "cts__design__core__area": 237168, - "cts__design__core__area__post_repair": 237168, - "cts__design__core__area__pre_repair": 237168, - "cts__design__die__area": 246035, - "cts__design__die__area__post_repair": 246035, - "cts__design__die__area__pre_repair": 246035, - "cts__design__instance__area": 134587, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 134132, - "cts__design__instance__area__pre_repair": 133924, - "cts__design__instance__area__stdcell": 134587, - "cts__design__instance__area__stdcell__post_repair": 134132, - "cts__design__instance__area__stdcell__pre_repair": 133924, - "cts__design__instance__count": 19906, - "cts__design__instance__count__hold_buffer": 2, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 19837, - "cts__design__instance__count__pre_repair": 19821, - "cts__design__instance__count__setup_buffer": 67, - "cts__design__instance__count__stdcell": 19906, - "cts__design__instance__count__stdcell__post_repair": 19837, - "cts__design__instance__count__stdcell__pre_repair": 19821, - "cts__design__instance__displacement__max": 10, - "cts__design__instance__displacement__mean": 0.022, - "cts__design__instance__displacement__total": 438.134, - "cts__design__instance__utilization": 0.567477, - "cts__design__instance__utilization__post_repair": 0.565556, - "cts__design__instance__utilization__pre_repair": 0.564681, - "cts__design__instance__utilization__stdcell": 0.567477, - "cts__design__instance__utilization__stdcell__post_repair": 0.565556, - "cts__design__instance__utilization__stdcell__pre_repair": 0.564681, - "cts__design__io": 388, - "cts__design__io__post_repair": 388, - "cts__design__io__pre_repair": 388, - "cts__design__violations": 0, - "cts__mem__peak": 371716.0, - "cts__power__internal__total": 0.0390148, - "cts__power__internal__total__post_repair": 0.0390296, - "cts__power__internal__total__pre_repair": 0.0389341, - "cts__power__leakage__total": 6.46402e-07, - "cts__power__leakage__total__post_repair": 6.52946e-07, - "cts__power__leakage__total__pre_repair": 6.52946e-07, - "cts__power__switching__total": 0.161568, - "cts__power__switching__total__post_repair": 0.15936, - "cts__power__switching__total__pre_repair": 0.159152, - "cts__power__total": 0.200584, - "cts__power__total__post_repair": 0.19839, - "cts__power__total__pre_repair": 0.198087, - "cts__route__wirelength__estimated": 508428, - "cts__runtime__total": "0:24.67", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 2, - "cts__timing__drv__hold_violation_count__pre_repair": 38, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 1, - "cts__timing__drv__max_cap_limit": 0.397585, - "cts__timing__drv__max_cap_limit__post_repair": 0.402033, - "cts__timing__drv__max_cap_limit__pre_repair": -0.0884339, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 56, - "cts__timing__drv__max_slew__post_repair": 52, - "cts__timing__drv__max_slew__pre_repair": 66, - "cts__timing__drv__max_slew_limit": -0.139242, - "cts__timing__drv__max_slew_limit__post_repair": -0.142238, - "cts__timing__drv__max_slew_limit__pre_repair": -1.63661, - "cts__timing__drv__setup_violation_count": 34, - "cts__timing__drv__setup_violation_count__post_repair": 62, - "cts__timing__drv__setup_violation_count__pre_repair": 80, - "cts__timing__setup__tns": -4.27118, - "cts__timing__setup__tns__post_repair": -10.134, - "cts__timing__setup__tns__pre_repair": -22, - "cts__timing__setup__ws": -0.345436, - "cts__timing__setup__ws__post_repair": -0.566456, - "cts__timing__setup__ws__pre_repair": -0.77015, - "design__io__hpwl": 126476626, - "detailedplace__cpu__total": 11.94, - "detailedplace__design__core__area": 237168, - "detailedplace__design__die__area": 246035, - "detailedplace__design__instance__area": 133737, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 133737, - "detailedplace__design__instance__count": 19769, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 19769, - "detailedplace__design__instance__displacement__max": 31.1, - "detailedplace__design__instance__displacement__mean": 1.676, - "detailedplace__design__instance__displacement__total": 33139.3, - "detailedplace__design__instance__utilization": 0.563892, - "detailedplace__design__instance__utilization__stdcell": 0.563892, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 340084.0, - "detailedplace__power__internal__total": 0.0387491, - "detailedplace__power__leakage__total": 6.52946e-07, - "detailedplace__power__switching__total": 0.155686, - "detailedplace__power__total": 0.194436, - "detailedplace__route__wirelength__estimated": 513141, - "detailedplace__runtime__total": "0:12.41", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.402033, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.266369, - "detailedplace__timing__drv__setup_violation_count": 11, - "detailedplace__timing__setup__tns": -0.927102, - "detailedplace__timing__setup__ws": -0.383841, - "detailedroute__cpu__total": 817.12, - "detailedroute__mem__peak": 2008308.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 5661, - "detailedroute__route__drc_errors__iter:2": 336, - "detailedroute__route__drc_errors__iter:3": 170, - "detailedroute__route__drc_errors__iter:4": 1, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 19567, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 126895, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 126895, - "detailedroute__route__wirelength": 619938, - "detailedroute__route__wirelength__iter:1": 625123, - "detailedroute__route__wirelength__iter:2": 620545, - "detailedroute__route__wirelength__iter:3": 619970, - "detailedroute__route__wirelength__iter:4": 619937, - "detailedroute__route__wirelength__iter:5": 619938, - "detailedroute__runtime__total": "0:49.02", - "fillcell__cpu__total": 3.58, - "fillcell__mem__peak": 318180.0, - "fillcell__runtime__total": "0:04.01", - "finish__clock__skew__hold": 0.111351, - "finish__clock__skew__setup": 0.0877822, - "finish__cpu__total": 14.13, - "finish__design__core__area": 237168, - "finish__design__die__area": 246035, - "finish__design__instance__area": 154819, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 154819, - "finish__design__instance__count": 20392, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 20392, - "finish__design__instance__utilization": 0.652784, - "finish__design__instance__utilization__stdcell": 0.652784, - "finish__design__io": 388, - "finish__mem__peak": 1056840.0, - "finish__power__internal__total": 0.0403355, - "finish__power__leakage__total": 6.07401e-07, - "finish__power__switching__total": 0.0267938, - "finish__power__total": 0.06713, - "finish__runtime__total": "0:15.16", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.996363, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.937998, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 2.93028, - "finish__timing__wns_percent_delay": 148.414708, - "finish_merge__cpu__total": 4.02, - "finish_merge__mem__peak": 417940.0, - "finish_merge__runtime__total": "0:04.55", - "floorplan__cpu__total": 6.14, - "floorplan__design__core__area": 237168, - "floorplan__design__die__area": 246035, - "floorplan__design__instance__area": 80461.1, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 80461.1, - "floorplan__design__instance__count": 18008, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 18008, - "floorplan__design__instance__utilization": 0.339258, - "floorplan__design__instance__utilization__stdcell": 0.339258, - "floorplan__design__io": 388, - "floorplan__mem__peak": 306236.0, - "floorplan__power__internal__total": 0.0248393, - "floorplan__power__leakage__total": 1.88808e-07, - "floorplan__power__switching__total": 0.0137784, - "floorplan__power__total": 0.0386178, - "floorplan__runtime__total": "0:06.66", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 2.73017, - "floorplan_io__cpu__total": 3.34, - "floorplan_io__mem__peak": 267620.0, - "floorplan_io__runtime__total": "0:03.61", - "floorplan_macro__cpu__total": 3.38, - "floorplan_macro__mem__peak": 266600.0, - "floorplan_macro__runtime__total": "0:03.71", - "floorplan_pdn__cpu__total": 3.69, - "floorplan_pdn__mem__peak": 270604.0, - "floorplan_pdn__runtime__total": "0:04.05", - "floorplan_tap__cpu__total": 3.46, - "floorplan_tap__mem__peak": 256284.0, - "floorplan_tap__runtime__total": "0:03.78", - "floorplan_tdms__cpu__total": 3.39, - "floorplan_tdms__mem__peak": 266988.0, - "floorplan_tdms__runtime__total": "0:03.69", - "globalplace__cpu__total": 91.57, - "globalplace__design__core__area": 237168, - "globalplace__design__die__area": 246035, - "globalplace__design__instance__area": 81241.6, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 81241.6, - "globalplace__design__instance__count": 19092, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 19092, - "globalplace__design__instance__utilization": 0.342549, - "globalplace__design__instance__utilization__stdcell": 0.342549, - "globalplace__design__io": 388, - "globalplace__mem__peak": 493052.0, - "globalplace__power__internal__total": 0.0316273, - "globalplace__power__leakage__total": 1.88808e-07, - "globalplace__power__switching__total": 0.146016, - "globalplace__power__total": 0.177643, - "globalplace__runtime__total": "0:53.82", - "globalplace__timing__setup__tns": -2333.29, - "globalplace__timing__setup__ws": -29.7251, - "globalplace_io__cpu__total": 3.33, - "globalplace_io__mem__peak": 270192.0, - "globalplace_io__runtime__total": "0:03.67", - "globalplace_skip_io__cpu__total": 8.19, - "globalplace_skip_io__mem__peak": 291996.0, - "globalplace_skip_io__runtime__total": "0:08.59", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.943005, - "globalroute__clock__skew__setup": 0.780381, - "globalroute__cpu__total": 104.27, - "globalroute__design__core__area": 237168, - "globalroute__design__die__area": 246035, - "globalroute__design__instance__area": 154819, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 154819, - "globalroute__design__instance__count": 20392, - "globalroute__design__instance__count__hold_buffer": 2, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 349, - "globalroute__design__instance__count__stdcell": 20392, - "globalroute__design__instance__displacement__max": 27, - "globalroute__design__instance__displacement__mean": 0.2575, - "globalroute__design__instance__displacement__total": 5254, - "globalroute__design__instance__utilization": 0.652784, - "globalroute__design__instance__utilization__stdcell": 0.652784, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 670284.0, - "globalroute__power__internal__total": 0.0410781, - "globalroute__power__leakage__total": 5.61772e-07, - "globalroute__power__switching__total": 0.180537, - "globalroute__power__total": 0.221616, - "globalroute__route__wirelength__estimated": 543458, - "globalroute__runtime__total": "2:12.01", - "globalroute__timing__clock__slack": -0.577, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.252091, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 167, - "globalroute__timing__drv__max_slew_limit": -0.291715, - "globalroute__timing__drv__setup_violation_count": 88, - "globalroute__timing__setup__tns": -15.9499, - "globalroute__timing__setup__ws": -0.576871, - "placeopt__cpu__total": 14.17, - "placeopt__design__core__area": 237168, - "placeopt__design__core__area__pre_opt": 237168, - "placeopt__design__die__area": 246035, - "placeopt__design__die__area__pre_opt": 246035, - "placeopt__design__instance__area": 133737, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 81241.6, - "placeopt__design__instance__area__stdcell": 133737, - "placeopt__design__instance__area__stdcell__pre_opt": 81241.6, - "placeopt__design__instance__count": 19769, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 19092, - "placeopt__design__instance__count__stdcell": 19769, - "placeopt__design__instance__count__stdcell__pre_opt": 19092, - "placeopt__design__instance__utilization": 0.563892, - "placeopt__design__instance__utilization__pre_opt": 0.342549, - "placeopt__design__instance__utilization__stdcell": 0.563892, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.342549, - "placeopt__design__io": 388, - "placeopt__design__io__pre_opt": 388, - "placeopt__mem__peak": 340244.0, - "placeopt__power__internal__total": 0.0357768, - "placeopt__power__internal__total__pre_opt": 0.0316273, - "placeopt__power__leakage__total": 5.82266e-07, - "placeopt__power__leakage__total__pre_opt": 1.88808e-07, - "placeopt__power__switching__total": 0.135408, - "placeopt__power__switching__total__pre_opt": 0.146016, - "placeopt__power__total": 0.171186, - "placeopt__power__total__pre_opt": 0.177643, - "placeopt__runtime__total": "0:14.99", - "placeopt__timing__drv__floating__nets": "0", - "placeopt__timing__drv__floating__pins": "0", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.381888, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.261455, - "placeopt__timing__drv__setup_violation_count": 4, - "placeopt__timing__setup__tns": -0.514838, - "placeopt__timing__setup__tns__pre_opt": -2333.29, - "placeopt__timing__setup__ws": -0.292674, - "placeopt__timing__setup__ws__pre_opt": -29.7251, - "run__flow__design": "aes", - "run__flow__generate_date": "2023-11-01 06:30", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-10894-g3ec4b3a13", - "run__flow__platform": "gf55", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "350fb752f39b45f16d494b2f08031595f61de8ef", - "run__flow__scripts_commit": "0250135ce348668bcd013989edb7f2a6ac1d8f2d", - "run__flow__uuid": "b8c57196-6c9d-48b4-832e-0522f15aebcf", - "run__flow__variant": "base", - "synth__cpu__total": 75.07, - "synth__design__instance__area__stdcell": 83356.92, - "synth__design__instance__count__stdcell": 18710.0, - "synth__mem__peak": 705596.0, - "synth__runtime__total": "1:18.17", - "total_time": "0:07:06.570000" -} \ No newline at end of file diff --git a/flow/designs/harness.mk b/flow/designs/harness.mk deleted file mode 100644 index 39db272b06..0000000000 --- a/flow/designs/harness.mk +++ /dev/null @@ -1,22 +0,0 @@ -export DESIGN_NAME ?= SPECIFY_DESIGN_NAME -export PLATFORM = nangate45 - -export VERILOG_FILES = ./designs/src/harness/*.v -export SDC_FILE = ./designs/src/harness/design.sdc - -export MERGED_LEF = $(PLATFORM_DIR)/NangateOpenCellLibrary.mod.lef -export LIB_FILES = $(PLATFORM_DIR)/NangateOpenCellLibrary_typical.lib -export GDS_FILES = $(sort $(wildcard $(PLATFORM_DIR)/gds/*)) - -# Automatically pick a reasonable area and utilization - -# Core utilization in % -export CORE_UTILIZATION = 10.0 -# Core height / core width -export CORE_ASPECT_RATIO = 1.0 -# Core margin in um -export CORE_MARGIN = 2.0 - -# Start with 250MHz for nangate45, relatively conservative -export CLOCK_PERIOD = 4 -export CLOCK_PORT = clock diff --git a/flow/designs/ihp-sg13g2/aes/autotuner.json b/flow/designs/ihp-sg13g2/aes/autotuner.json index e00ed19ca8..d3fe2ead8f 100644 --- a/flow/designs/ihp-sg13g2/aes/autotuner.json +++ b/flow/designs/ihp-sg13g2/aes/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 5.0, + 4.0, 6.0 ], "step": 0 @@ -11,8 +11,8 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 10, - 20 + 20, + 50 ], "step": 1 }, @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, @@ -88,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl" } diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc index ad041066f1..f0b3b99355 100644 --- a/flow/designs/ihp-sg13g2/aes/constraint.sdc +++ b/flow/designs/ihp-sg13g2/aes/constraint.sdc @@ -1,16 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 5.6 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] - diff --git a/flow/designs/ihp-sg13g2/aes/metadata-base-ok.json b/flow/designs/ihp-sg13g2/aes/metadata-base-ok.json deleted file mode 100644 index 6cdaead97d..0000000000 --- a/flow/designs/ihp-sg13g2/aes/metadata-base-ok.json +++ /dev/null @@ -1,375 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 5.6000" - ], - "cts__clock__skew__hold": 0.158193, - "cts__clock__skew__setup": 0.158193, - "cts__cpu__total": 11.16, - "cts__design__core__area": 946124, - "cts__design__die__area": 1015240.0, - "cts__design__instance__area": 187065, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 187065, - "cts__design__instance__count": 17003, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 17003, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.197717, - "cts__design__instance__utilization__stdcell": 0.197717, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 470348.0, - "cts__power__internal__total": 0.0539133, - "cts__power__leakage__total": 2.47384e-06, - "cts__power__switching__total": 0.0439868, - "cts__power__total": 0.0979026, - "cts__route__wirelength__estimated": 607598, - "cts__runtime__total": "0:11.51", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.830514, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 8, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.858467, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 2.29829, - "design__io__hpwl": 153213141, - "design__violations": 0, - "detailedplace__cpu__total": 12.27, - "detailedplace__design__core__area": 946124, - "detailedplace__design__die__area": 1015240.0, - "detailedplace__design__instance__area": 183679, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 183679, - "detailedplace__design__instance__count": 16849, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 16849, - "detailedplace__design__instance__displacement__max": 25.2, - "detailedplace__design__instance__displacement__mean": 3.799, - "detailedplace__design__instance__displacement__total": 64013.6, - "detailedplace__design__instance__utilization": 0.194138, - "detailedplace__design__instance__utilization__stdcell": 0.194138, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 216716.0, - "detailedplace__power__internal__total": 0.0521654, - "detailedplace__power__leakage__total": 2.37718e-06, - "detailedplace__power__switching__total": 0.0429754, - "detailedplace__power__total": 0.0951432, - "detailedplace__route__wirelength__estimated": 636216, - "detailedplace__runtime__total": "0:12.35", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.830369, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 8, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.858213, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 1.72885, - "detailedroute__antenna__violating__nets": 174, - "detailedroute__antenna__violating__pins": 174, - "detailedroute__cpu__total": 19627.16, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__mem__peak": 5170760.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 27375, - "detailedroute__route__drc_errors__iter:10": 139, - "detailedroute__route__drc_errors__iter:11": 88, - "detailedroute__route__drc_errors__iter:12": 31, - "detailedroute__route__drc_errors__iter:13": 23, - "detailedroute__route__drc_errors__iter:14": 15, - "detailedroute__route__drc_errors__iter:15": 7, - "detailedroute__route__drc_errors__iter:16": 5, - "detailedroute__route__drc_errors__iter:17": 4, - "detailedroute__route__drc_errors__iter:18": 4, - "detailedroute__route__drc_errors__iter:19": 4, - "detailedroute__route__drc_errors__iter:2": 16030, - "detailedroute__route__drc_errors__iter:20": 4, - "detailedroute__route__drc_errors__iter:21": 3, - "detailedroute__route__drc_errors__iter:22": 3, - "detailedroute__route__drc_errors__iter:23": 3, - "detailedroute__route__drc_errors__iter:24": 3, - "detailedroute__route__drc_errors__iter:25": 1, - "detailedroute__route__drc_errors__iter:26": 1, - "detailedroute__route__drc_errors__iter:27": 1, - "detailedroute__route__drc_errors__iter:28": 1, - "detailedroute__route__drc_errors__iter:29": 1, - "detailedroute__route__drc_errors__iter:3": 14513, - "detailedroute__route__drc_errors__iter:30": 1, - "detailedroute__route__drc_errors__iter:31": 1, - "detailedroute__route__drc_errors__iter:32": 1, - "detailedroute__route__drc_errors__iter:33": 1, - "detailedroute__route__drc_errors__iter:34": 1, - "detailedroute__route__drc_errors__iter:35": 0, - "detailedroute__route__drc_errors__iter:4": 4297, - "detailedroute__route__drc_errors__iter:5": 1386, - "detailedroute__route__drc_errors__iter:6": 771, - "detailedroute__route__drc_errors__iter:7": 425, - "detailedroute__route__drc_errors__iter:8": 232, - "detailedroute__route__drc_errors__iter:9": 148, - "detailedroute__route__net": 17781, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 145612, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 145612, - "detailedroute__route__wirelength": 744833, - "detailedroute__route__wirelength__iter:1": 754643, - "detailedroute__route__wirelength__iter:10": 744794, - "detailedroute__route__wirelength__iter:11": 744780, - "detailedroute__route__wirelength__iter:12": 744815, - "detailedroute__route__wirelength__iter:13": 744820, - "detailedroute__route__wirelength__iter:14": 744806, - "detailedroute__route__wirelength__iter:15": 744807, - "detailedroute__route__wirelength__iter:16": 744805, - "detailedroute__route__wirelength__iter:17": 744811, - "detailedroute__route__wirelength__iter:18": 744811, - "detailedroute__route__wirelength__iter:19": 744811, - "detailedroute__route__wirelength__iter:2": 749580, - "detailedroute__route__wirelength__iter:20": 744811, - "detailedroute__route__wirelength__iter:21": 744818, - "detailedroute__route__wirelength__iter:22": 744818, - "detailedroute__route__wirelength__iter:23": 744821, - "detailedroute__route__wirelength__iter:24": 744821, - "detailedroute__route__wirelength__iter:25": 744835, - "detailedroute__route__wirelength__iter:26": 744835, - "detailedroute__route__wirelength__iter:27": 744835, - "detailedroute__route__wirelength__iter:28": 744835, - "detailedroute__route__wirelength__iter:29": 744835, - "detailedroute__route__wirelength__iter:3": 748172, - "detailedroute__route__wirelength__iter:30": 744832, - "detailedroute__route__wirelength__iter:31": 744832, - "detailedroute__route__wirelength__iter:32": 744832, - "detailedroute__route__wirelength__iter:33": 744832, - "detailedroute__route__wirelength__iter:34": 744832, - "detailedroute__route__wirelength__iter:35": 744833, - "detailedroute__route__wirelength__iter:4": 745309, - "detailedroute__route__wirelength__iter:5": 745027, - "detailedroute__route__wirelength__iter:6": 744853, - "detailedroute__route__wirelength__iter:7": 744852, - "detailedroute__route__wirelength__iter:8": 744832, - "detailedroute__route__wirelength__iter:9": 744837, - "detailedroute__runtime__total": "1:06:44", - "fillcell__cpu__total": 0.46, - "fillcell__mem__peak": 199552.0, - "fillcell__runtime__total": "0:00.58", - "finish__clock__skew__hold": 0.181426, - "finish__clock__skew__setup": 0.181426, - "finish__cpu__total": 66.3, - "finish__design__core__area": 946124, - "finish__design__die__area": 1015240.0, - "finish__design__instance__area": 926119, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 926119, - "finish__design__instance__count": 77476, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 77476, - "finish__design__instance__utilization": 0.978855, - "finish__design__instance__utilization__stdcell": 0.978855, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.19867, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00138472, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00331786, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00368408, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.19668, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00368408, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 993324.0, - "finish__power__internal__total": 0.0558489, - "finish__power__leakage__total": 4.73853e-05, - "finish__power__switching__total": 0.0791071, - "finish__power__total": 0.135003, - "finish__runtime__total": "1:07.18", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.299409, - "finish__timing__drv__max_fanout": 242, - "finish__timing__drv__max_fanout_limit": 8, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.598641, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.445279, - "finish__timing__wns_percent_delay": 8.086807, - "finish_merge__cpu__total": 3.43, - "finish_merge__mem__peak": 641540.0, - "finish_merge__runtime__total": "0:03.79", - "floorplan__cpu__total": 3.62, - "floorplan__design__core__area": 946124, - "floorplan__design__die__area": 1015240.0, - "floorplan__design__instance__area": 154641, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 154641, - "floorplan__design__instance__count": 13439, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 13439, - "floorplan__design__instance__utilization": 0.163447, - "floorplan__design__instance__utilization__stdcell": 0.163447, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 179132.0, - "floorplan__power__internal__total": 0.0454503, - "floorplan__power__leakage__total": 1.88077e-06, - "floorplan__power__switching__total": 0.0373477, - "floorplan__power__total": 0.0828, - "floorplan__runtime__total": "0:03.71", - "floorplan__timing__setup__tns": -257.857, - "floorplan__timing__setup__ws": -2.65911, - "floorplan_io__cpu__total": 0.18, - "floorplan_io__mem__peak": 141352.0, - "floorplan_io__runtime__total": "0:00.24", - "floorplan_macro__cpu__total": 0.18, - "floorplan_macro__mem__peak": 140084.0, - "floorplan_macro__runtime__total": "0:00.26", - "floorplan_pdn__cpu__total": 0.32, - "floorplan_pdn__mem__peak": 143916.0, - "floorplan_pdn__runtime__total": "0:00.39", - "floorplan_tap__cpu__total": 0.17, - "floorplan_tap__mem__peak": 132236.0, - "floorplan_tap__runtime__total": "0:00.22", - "floorplan_tdms__cpu__total": 0.17, - "floorplan_tdms__mem__peak": 140464.0, - "floorplan_tdms__runtime__total": "0:00.25", - "flow__errors__count": 0, - "flow__warnings__count": 12, - "globalplace__cpu__total": 253.06, - "globalplace__design__core__area": 946124, - "globalplace__design__die__area": 1015240.0, - "globalplace__design__instance__area": 154641, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 154641, - "globalplace__design__instance__count": 13439, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 13439, - "globalplace__design__instance__utilization": 0.163447, - "globalplace__design__instance__utilization__stdcell": 0.163447, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 465660.0, - "globalplace__power__internal__total": 0.0459291, - "globalplace__power__leakage__total": 1.88077e-06, - "globalplace__power__switching__total": 0.0401261, - "globalplace__power__total": 0.0860571, - "globalplace__runtime__total": "0:48.69", - "globalplace__timing__setup__tns": -320.593, - "globalplace__timing__setup__ws": -3.16762, - "globalplace_io__cpu__total": 0.18, - "globalplace_io__mem__peak": 142680.0, - "globalplace_io__runtime__total": "0:00.26", - "globalplace_skip_io__cpu__total": 205.76, - "globalplace_skip_io__mem__peak": 171708.0, - "globalplace_skip_io__runtime__total": "0:09.09", - "globalroute__antenna__violating__nets": 221, - "globalroute__antenna__violating__pins": 221, - "globalroute__clock__skew__hold": 0.153309, - "globalroute__clock__skew__setup": 0.153309, - "globalroute__cpu__total": 58.3, - "globalroute__design__core__area": 946124, - "globalroute__design__die__area": 1015240.0, - "globalroute__design__instance__area": 203656, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 203656, - "globalroute__design__instance__count": 20051, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 20051, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.215252, - "globalroute__design__instance__utilization__stdcell": 0.215252, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 668452.0, - "globalroute__power__internal__total": 0.0551583, - "globalroute__power__leakage__total": 2.48701e-06, - "globalroute__power__switching__total": 0.0629421, - "globalroute__power__total": 0.118103, - "globalroute__route__wirelength__estimated": 607598, - "globalroute__runtime__total": "0:18.49", - "globalroute__timing__clock__slack": 0.966, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.435889, - "globalroute__timing__drv__max_fanout": 242, - "globalroute__timing__drv__max_fanout_limit": 8, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.629421, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.965843, - "placeopt__cpu__total": 9.11, - "placeopt__design__core__area": 946124, - "placeopt__design__die__area": 1015240.0, - "placeopt__design__instance__area": 183679, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 183679, - "placeopt__design__instance__count": 16849, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 16849, - "placeopt__design__instance__utilization": 0.194138, - "placeopt__design__instance__utilization__stdcell": 0.194138, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 361116.0, - "placeopt__power__internal__total": 0.0521675, - "placeopt__power__leakage__total": 2.37718e-06, - "placeopt__power__switching__total": 0.0429339, - "placeopt__power__total": 0.0951037, - "placeopt__runtime__total": "0:09.28", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.831061, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 8, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.857918, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1.72175, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-08-27 21:57", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15322-gdf361ea88", - "run__flow__platform": "ihp-sg13g2", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__scripts_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__uuid": "8e387424-eb3c-43bb-94fa-a74b81bdb1e0", - "run__flow__variant": "base", - "synth__cpu__total": 36.84, - "synth__design__instance__area__stdcell": 189938.8386, - "synth__design__instance__count__stdcell": 15925.0, - "synth__mem__peak": 134236.0, - "synth__runtime__total": "0:37.01", - "total_time": "1:10:27.300000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/aes/rules-base.json b/flow/designs/ihp-sg13g2/aes/rules-base.json index 6c73d8533c..8d1832de8c 100644 --- a/flow/designs/ihp-sg13g2/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/aes/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 210460, + "value": 229478, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19280, + "value": 18986, "compare": "<=" }, "detailedplace__design__violations": { @@ -27,8 +27,12 @@ "value": 1128, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 6, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 840803, + "value": 782983, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -36,7 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 226, + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 39, "compare": "<=" }, "finish__timing__setup__ws": { @@ -44,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1064943, + "value": 1061886, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 11, + "value": 826, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/gcd/autotuner.json b/flow/designs/ihp-sg13g2/gcd/autotuner.json index cf4af063e3..0684536ecf 100644 --- a/flow/designs/ihp-sg13g2/gcd/autotuner.json +++ b/flow/designs/ihp-sg13g2/gcd/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 7.0, + 2.0, 12.0 ], "step": 0 @@ -11,8 +11,8 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 5, - 30 + 15, + 50 ], "step": 1 }, @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, @@ -68,7 +60,7 @@ "type": "int", "minmax": [ 1, - 1 + 3 ], "step": 1 }, @@ -88,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl" } diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc index 9f9891820b..0c1e6d1d5b 100644 --- a/flow/designs/ihp-sg13g2/gcd/constraint.sdc +++ b/flow/designs/ihp-sg13g2/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 10.4 +set clk_period 2.6 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/gcd/metadata-base-ok.json b/flow/designs/ihp-sg13g2/gcd/metadata-base-ok.json deleted file mode 100644 index 1939755f69..0000000000 --- a/flow/designs/ihp-sg13g2/gcd/metadata-base-ok.json +++ /dev/null @@ -1,317 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 10.4000" - ], - "cts__clock__skew__hold": 0.00203551, - "cts__clock__skew__setup": 0.00203551, - "cts__cpu__total": 2.32, - "cts__design__core__area": 28261.1, - "cts__design__die__area": 41473.3, - "cts__design__instance__area": 6738.68, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 6738.68, - "cts__design__instance__count": 576, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 576, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.238444, - "cts__design__instance__utilization__stdcell": 0.238444, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 397392.0, - "cts__power__internal__total": 0.000303748, - "cts__power__leakage__total": 8.87119e-08, - "cts__power__switching__total": 0.000107427, - "cts__power__total": 0.000411264, - "cts__route__wirelength__estimated": 13026.6, - "cts__runtime__total": "0:02.58", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.82543, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 8, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.91212, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 6.26833, - "design__io__hpwl": 4324018, - "design__violations": 0, - "detailedplace__cpu__total": 0.37, - "detailedplace__design__core__area": 28261.1, - "detailedplace__design__die__area": 41473.3, - "detailedplace__design__instance__area": 6646.15, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 6646.15, - "detailedplace__design__instance__count": 562, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 562, - "detailedplace__design__instance__displacement__max": 22.664, - "detailedplace__design__instance__displacement__mean": 3.882, - "detailedplace__design__instance__displacement__total": 2181.77, - "detailedplace__design__instance__utilization": 0.235169, - "detailedplace__design__instance__utilization__stdcell": 0.235169, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 123344.0, - "detailedplace__power__internal__total": 0.000295437, - "detailedplace__power__leakage__total": 8.74039e-08, - "detailedplace__power__switching__total": 8.29277e-05, - "detailedplace__power__total": 0.000378452, - "detailedplace__route__wirelength__estimated": 13368.6, - "detailedplace__runtime__total": "0:00.41", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.920559, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 8, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.920237, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 6.65327, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 122.71, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__mem__peak": 1143516.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 262, - "detailedroute__route__drc_errors__iter:2": 152, - "detailedroute__route__drc_errors__iter:3": 138, - "detailedroute__route__drc_errors__iter:4": 18, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 642, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3548, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3548, - "detailedroute__route__wirelength": 15014, - "detailedroute__route__wirelength__iter:1": 15287, - "detailedroute__route__wirelength__iter:2": 15174, - "detailedroute__route__wirelength__iter:3": 15098, - "detailedroute__route__wirelength__iter:4": 15019, - "detailedroute__route__wirelength__iter:5": 15014, - "detailedroute__runtime__total": "1:37.95", - "fillcell__cpu__total": 0.12, - "fillcell__mem__peak": 120020.0, - "fillcell__runtime__total": "0:00.16", - "finish__clock__skew__hold": 0.0204803, - "finish__clock__skew__setup": 0.0204803, - "finish__cpu__total": 1.85, - "finish__design__core__area": 28261.1, - "finish__design__die__area": 41473.3, - "finish__design__instance__area": 27624.2, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 27624.2, - "finish__design__instance__count": 2247, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 2247, - "finish__design__instance__utilization": 0.977465, - "finish__design__instance__utilization__stdcell": 0.977465, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.19991, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000200891, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.000104211, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.000221038, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.1999, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.000221038, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 273052.0, - "finish__power__internal__total": 0.000304483, - "finish__power__leakage__total": 1.38625e-06, - "finish__power__switching__total": 0.00015729, - "finish__power__total": 0.000463159, - "finish__runtime__total": "0:01.94", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.808081, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 8, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.890664, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 5.93467, - "finish__timing__wns_percent_delay": 248.803086, - "finish_merge__cpu__total": 1.2, - "finish_merge__mem__peak": 397224.0, - "finish_merge__runtime__total": "0:01.40", - "floorplan__cpu__total": 0.15, - "floorplan__design__core__area": 28261.1, - "floorplan__design__die__area": 41473.3, - "floorplan__design__instance__area": 5824.22, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 5824.22, - "floorplan__design__instance__count": 452, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 452, - "floorplan__design__instance__utilization": 0.206086, - "floorplan__design__instance__utilization__stdcell": 0.206086, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 121520.0, - "floorplan__power__internal__total": 0.000279086, - "floorplan__power__leakage__total": 7.60558e-08, - "floorplan__power__switching__total": 7.2524e-05, - "floorplan__power__total": 0.000351686, - "floorplan__runtime__total": "0:00.24", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 6.88266, - "floorplan_io__cpu__total": 0.08, - "floorplan_io__mem__peak": 118384.0, - "floorplan_io__runtime__total": "0:00.15", - "floorplan_macro__cpu__total": 0.07, - "floorplan_macro__mem__peak": 118856.0, - "floorplan_macro__runtime__total": "0:00.15", - "floorplan_pdn__cpu__total": 0.11, - "floorplan_pdn__mem__peak": 120268.0, - "floorplan_pdn__runtime__total": "0:00.16", - "floorplan_tap__cpu__total": 0.11, - "floorplan_tap__mem__peak": 117424.0, - "floorplan_tap__runtime__total": "0:00.14", - "floorplan_tdms__cpu__total": 0.1, - "floorplan_tdms__mem__peak": 118624.0, - "floorplan_tdms__runtime__total": "0:00.15", - "flow__errors__count": 0, - "flow__warnings__count": 12, - "globalplace__cpu__total": 14.35, - "globalplace__design__core__area": 28261.1, - "globalplace__design__die__area": 41473.3, - "globalplace__design__instance__area": 5824.22, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 5824.22, - "globalplace__design__instance__count": 452, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 452, - "globalplace__design__instance__utilization": 0.206086, - "globalplace__design__instance__utilization__stdcell": 0.206086, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 307924.0, - "globalplace__power__internal__total": 0.000279235, - "globalplace__power__leakage__total": 7.60558e-08, - "globalplace__power__switching__total": 7.67813e-05, - "globalplace__power__total": 0.000356093, - "globalplace__runtime__total": "0:01.36", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 6.85781, - "globalplace_io__cpu__total": 0.1, - "globalplace_io__mem__peak": 119132.0, - "globalplace_io__runtime__total": "0:00.16", - "globalplace_skip_io__cpu__total": 13.01, - "globalplace_skip_io__mem__peak": 120752.0, - "globalplace_skip_io__runtime__total": "0:00.55", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.0202872, - "globalroute__clock__skew__setup": 0.0202872, - "globalroute__cpu__total": 1.69, - "globalroute__design__core__area": 28261.1, - "globalroute__design__die__area": 41473.3, - "globalroute__design__instance__area": 6738.68, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 6738.68, - "globalroute__design__instance__count": 576, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 576, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.238444, - "globalroute__design__instance__utilization__stdcell": 0.238444, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 357188.0, - "globalroute__power__internal__total": 0.000304034, - "globalroute__power__leakage__total": 8.87119e-08, - "globalroute__power__switching__total": 0.00014424, - "globalroute__power__total": 0.000448362, - "globalroute__route__wirelength__estimated": 13026.6, - "globalroute__runtime__total": "0:00.72", - "globalroute__timing__clock__slack": 6.064, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.813771, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 8, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.9077, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 6.06379, - "placeopt__cpu__total": 0.34, - "placeopt__design__core__area": 28261.1, - "placeopt__design__die__area": 41473.3, - "placeopt__design__instance__area": 6646.15, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 6646.15, - "placeopt__design__instance__count": 562, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 562, - "placeopt__design__instance__utilization": 0.235169, - "placeopt__design__instance__utilization__stdcell": 0.235169, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 305868.0, - "placeopt__power__internal__total": 0.000295394, - "placeopt__power__leakage__total": 8.74039e-08, - "placeopt__power__switching__total": 8.2534e-05, - "placeopt__power__total": 0.000378016, - "placeopt__runtime__total": "0:00.51", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.920864, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 8, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.920905, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 6.65299, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-08-27 21:57", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15322-gdf361ea88", - "run__flow__platform": "ihp-sg13g2", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__scripts_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__uuid": "92efb541-db59-415d-ae29-73a585794a7a", - "run__flow__variant": "base", - "synth__cpu__total": 0.71, - "synth__design__instance__area__stdcell": 5823.4302, - "synth__design__instance__count__stdcell": 452.0, - "synth__mem__peak": 32512.0, - "synth__runtime__total": "0:00.76", - "total_time": "0:01:49.490000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/gcd/rules-base.json b/flow/designs/ihp-sg13g2/gcd/rules-base.json index ac5cd9e426..e8f4653148 100644 --- a/flow/designs/ihp-sg13g2/gcd/rules-base.json +++ b/flow/designs/ihp-sg13g2/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 6639.22, + "value": 5719.01, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7149, + "value": 6508, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 646, + "value": 494, "compare": "<=" }, "detailedplace__design__violations": { @@ -27,8 +27,12 @@ "value": 20, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 15911, + "value": 14242, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -39,12 +43,16 @@ "value": 0, "compare": "<=" }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 28317, + "value": 27303, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk new file mode 100644 index 0000000000..68feb648f2 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/config.mk @@ -0,0 +1,20 @@ +export DESIGN_NAME = I2cDeviceCtrl +export TOP_DESIGN_NICKNAME = i2c-gpio-expander +export DESIGN_NICKNAME = ${TOP_DESIGN_NICKNAME}_${DESIGN_NAME} +export PLATFORM = ihp-sg13g2 + +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/${TOP_DESIGN_NICKNAME}/I2cGpioExpander.v \ + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/constraint.sdc + +export DIE_AREA = 0.0 0.0 147.84 147.42 +export CORE_AREA = 18.72 18.9 128.64 128.52 + +export MAX_ROUTING_LAYER = TopMetal2 + +export TNS_END_PERCENT = 100 +export PLACE_DENSITY = 0.75 + +export CORNERS = slow typ fast + +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(TOP_DESIGN_NICKNAME)/${DESIGN_NAME}/pdn.tcl diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc new file mode 100644 index 0000000000..95787b8df0 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/constraint.sdc @@ -0,0 +1,22 @@ +current_design I2cDeviceCtrl/I2cDeviceCtrl +set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA +set_max_fanout 8 [current_design] +set_max_capacitance 0.5 [current_design] +set_max_transition 3 [current_design] +set_max_area 0 + +create_clock [get_ports clock] -name clock -period 20.0 -waveform {0 10.0} +set_ideal_network [get_ports clock] +set_clock_uncertainty 0.15 [get_clocks clock] +set_clock_transition 0.25 [get_clocks clock] +set input_delay_value_clock 4.0 +set output_delay_value_clock 4.0 +set clk_indx_clock [lsearch [all_inputs] [get_port clock]] +set all_inputs_wo_clk_rst_clock [lreplace [all_inputs] $clk_indx_clock $clk_indx_clock ""] +set_input_delay $input_delay_value_clock -clock [get_clocks clock] $all_inputs_wo_clk_rst_clock +set_output_delay $output_delay_value_clock -clock [get_clocks clock] [all_outputs] + +set_load -pin_load 5 [all_inputs] +set_load -pin_load 5 [all_outputs] +set_timing_derate -early 0.95 +set_timing_derate -late 1.05 diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl new file mode 100644 index 0000000000..aa6f2f142a --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl @@ -0,0 +1,38 @@ +# standard cells +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} + +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + +# padframe core power pins +add_global_connection -net {VDD} -pin_pattern {^vdd$} -power +add_global_connection -net {VSS} -pin_pattern {^vss$} -ground + +# padframe io power pins +add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power +add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground + +global_connect + +# core voltage domain +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +# stdcell grid +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_connect -grid {grid} -layers {Metal1 Metal3} +add_pdn_connect -grid {grid} -layers {Metal3 Metal4} diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpander.v b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpander.v new file mode 100644 index 0000000000..237a43223c --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpander.v @@ -0,0 +1,957 @@ +// Generator : SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935 +// Component : SG13G2Top +// Git hash : dbd10e6c9374bd7bc3ffc29e541415e2be16643a + +`timescale 1ns/1ps + +module I2cGpioExpander ( + input wire [2:0] io_address, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire [0:0] io_i2c_interrupts, + input wire [7:0] io_gpio_pins_read, + output wire [7:0] io_gpio_pins_write, + output wire [7:0] io_gpio_pins_writeEnable, + input wire clock, + input wire reset +); + localparam State_IDLE = 3'd0; + localparam State_REG_1 = 3'd1; + localparam State_READ = 3'd2; + localparam State_WRITE = 3'd3; + localparam State_RESPONSE = 3'd4; + + wire [6:0] i2cCtrl_io_config_deviceAddr; + wire [0:0] i2cCtrl_io_interrupts; + reg i2cCtrl_io_cmd_ready; + reg i2cCtrl_io_rsp_valid; + reg [7:0] irq_high_ctrl_io_clears; + reg [7:0] irq_low_ctrl_io_clears; + reg [7:0] irq_rise_ctrl_io_clears; + reg [7:0] irq_fall_ctrl_io_clears; + wire i2cCtrl_io_i2c_scl_write; + wire i2cCtrl_io_i2c_sda_write; + wire [0:0] i2cCtrl_io_i2c_interrupts; + wire i2cCtrl_io_cmd_valid; + wire [7:0] i2cCtrl_io_cmd_payload_data; + wire i2cCtrl_io_cmd_payload_reg; + wire i2cCtrl_io_cmd_payload_read; + wire i2cCtrl_io_rsp_ready; + wire [7:0] gpioCtrl_1_io_gpio_pins_write; + wire [7:0] gpioCtrl_1_io_gpio_pins_writeEnable; + wire [7:0] gpioCtrl_1_io_value; + wire gpioCtrl_1_io_interrupt; + wire [7:0] gpioCtrl_1_io_irqHigh_valid; + wire [7:0] gpioCtrl_1_io_irqLow_valid; + wire [7:0] gpioCtrl_1_io_irqRise_valid; + wire [7:0] gpioCtrl_1_io_irqFall_valid; + wire [7:0] irq_high_ctrl_io_pendings; + wire [7:0] irq_low_ctrl_io_pendings; + wire [7:0] irq_rise_ctrl_io_pendings; + wire [7:0] irq_fall_ctrl_io_pendings; + reg [2:0] i2cConfig_latchedAddress; + reg i2cConfig_latch; + wire when_I2cGpioExpander_l46; + reg [7:0] gpioConfig_write; + reg [7:0] gpioConfig_direction; + reg [7:0] irq_high_masks; + reg [7:0] irq_low_masks; + reg [7:0] irq_rise_masks; + reg [7:0] irq_fall_masks; + reg [7:0] link_regAddr; + reg [2:0] link_state; + reg [7:0] link_data; + reg link_error; + wire [7:0] switch_I2cGpioExpander_l139; + wire [7:0] switch_I2cGpioExpander_l182; + `ifndef SYNTHESIS + reg [63:0] link_state_string; + `endif + + + I2cDeviceCtrl i2cCtrl ( + .io_config_clockDivider (16'h0001 ), //i + .io_config_timeout (16'h1388 ), //i + .io_config_deviceAddr (i2cCtrl_io_config_deviceAddr[6:0]), //i + .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o + .io_i2c_scl_read (io_i2c_scl_read ), //i + .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o + .io_i2c_sda_read (io_i2c_sda_read ), //i + .io_i2c_interrupts (i2cCtrl_io_i2c_interrupts ), //o + .io_interrupts (i2cCtrl_io_interrupts ), //i + .io_cmd_valid (i2cCtrl_io_cmd_valid ), //o + .io_cmd_ready (i2cCtrl_io_cmd_ready ), //i + .io_cmd_payload_data (i2cCtrl_io_cmd_payload_data[7:0] ), //o + .io_cmd_payload_reg (i2cCtrl_io_cmd_payload_reg ), //o + .io_cmd_payload_read (i2cCtrl_io_cmd_payload_read ), //o + .io_rsp_valid (i2cCtrl_io_rsp_valid ), //i + .io_rsp_ready (i2cCtrl_io_rsp_ready ), //o + .io_rsp_payload_data (link_data[7:0] ), //i + .io_rsp_payload_error (link_error ), //i + .clock (clock ), //i + .reset (reset ) //i + ); + GpioCtrl gpioCtrl_1 ( + .io_gpio_pins_read (io_gpio_pins_read[7:0] ), //i + .io_gpio_pins_write (gpioCtrl_1_io_gpio_pins_write[7:0] ), //o + .io_gpio_pins_writeEnable (gpioCtrl_1_io_gpio_pins_writeEnable[7:0]), //o + .io_config_write (gpioConfig_write[7:0] ), //i + .io_config_direction (gpioConfig_direction[7:0] ), //i + .io_value (gpioCtrl_1_io_value[7:0] ), //o + .io_interrupt (gpioCtrl_1_io_interrupt ), //o + .io_irqHigh_valid (gpioCtrl_1_io_irqHigh_valid[7:0] ), //o + .io_irqHigh_pending (irq_high_ctrl_io_pendings[7:0] ), //i + .io_irqLow_valid (gpioCtrl_1_io_irqLow_valid[7:0] ), //o + .io_irqLow_pending (irq_low_ctrl_io_pendings[7:0] ), //i + .io_irqRise_valid (gpioCtrl_1_io_irqRise_valid[7:0] ), //o + .io_irqRise_pending (irq_rise_ctrl_io_pendings[7:0] ), //i + .io_irqFall_valid (gpioCtrl_1_io_irqFall_valid[7:0] ), //o + .io_irqFall_pending (irq_fall_ctrl_io_pendings[7:0] ), //i + .clock (clock ), //i + .reset (reset ) //i + ); + InterruptCtrl irq_high_ctrl ( + .io_inputs (gpioCtrl_1_io_irqHigh_valid[7:0]), //i + .io_clears (irq_high_ctrl_io_clears[7:0] ), //i + .io_masks (irq_high_masks[7:0] ), //i + .io_pendings (irq_high_ctrl_io_pendings[7:0] ), //o + .clock (clock ), //i + .reset (reset ) //i + ); + InterruptCtrl irq_low_ctrl ( + .io_inputs (gpioCtrl_1_io_irqLow_valid[7:0]), //i + .io_clears (irq_low_ctrl_io_clears[7:0] ), //i + .io_masks (irq_low_masks[7:0] ), //i + .io_pendings (irq_low_ctrl_io_pendings[7:0] ), //o + .clock (clock ), //i + .reset (reset ) //i + ); + InterruptCtrl irq_rise_ctrl ( + .io_inputs (gpioCtrl_1_io_irqRise_valid[7:0]), //i + .io_clears (irq_rise_ctrl_io_clears[7:0] ), //i + .io_masks (irq_rise_masks[7:0] ), //i + .io_pendings (irq_rise_ctrl_io_pendings[7:0] ), //o + .clock (clock ), //i + .reset (reset ) //i + ); + InterruptCtrl irq_fall_ctrl ( + .io_inputs (gpioCtrl_1_io_irqFall_valid[7:0]), //i + .io_clears (irq_fall_ctrl_io_clears[7:0] ), //i + .io_masks (irq_fall_masks[7:0] ), //i + .io_pendings (irq_fall_ctrl_io_pendings[7:0] ), //o + .clock (clock ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(link_state) + State_IDLE : link_state_string = "IDLE "; + State_REG_1 : link_state_string = "REG_1 "; + State_READ : link_state_string = "READ "; + State_WRITE : link_state_string = "WRITE "; + State_RESPONSE : link_state_string = "RESPONSE"; + default : link_state_string = "????????"; + endcase + end + `endif + + assign io_i2c_scl_write = i2cCtrl_io_i2c_scl_write; + assign io_i2c_sda_write = i2cCtrl_io_i2c_sda_write; + assign io_i2c_interrupts = i2cCtrl_io_i2c_interrupts; + assign when_I2cGpioExpander_l46 = (! i2cConfig_latch); + assign i2cCtrl_io_config_deviceAddr = {4'b0110,i2cConfig_latchedAddress}; + assign io_gpio_pins_write = gpioCtrl_1_io_gpio_pins_write; + assign io_gpio_pins_writeEnable = gpioCtrl_1_io_gpio_pins_writeEnable; + always @(*) begin + irq_high_ctrl_io_clears = 8'h0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + end + State_READ : begin + end + State_WRITE : begin + case(switch_I2cGpioExpander_l182) + 8'h01 : begin + end + 8'h02 : begin + end + 8'h03 : begin + irq_high_ctrl_io_clears = i2cCtrl_io_cmd_payload_data; + end + 8'h04 : begin + end + 8'h05 : begin + end + 8'h06 : begin + end + 8'h07 : begin + end + 8'h08 : begin + end + 8'h09 : begin + end + 8'h0a : begin + end + default : begin + end + endcase + end + default : begin + end + endcase + end + + always @(*) begin + irq_low_ctrl_io_clears = 8'h0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + end + State_READ : begin + end + State_WRITE : begin + case(switch_I2cGpioExpander_l182) + 8'h01 : begin + end + 8'h02 : begin + end + 8'h03 : begin + end + 8'h04 : begin + irq_low_ctrl_io_clears = i2cCtrl_io_cmd_payload_data; + end + 8'h05 : begin + end + 8'h06 : begin + end + 8'h07 : begin + end + 8'h08 : begin + end + 8'h09 : begin + end + 8'h0a : begin + end + default : begin + end + endcase + end + default : begin + end + endcase + end + + always @(*) begin + irq_rise_ctrl_io_clears = 8'h0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + end + State_READ : begin + end + State_WRITE : begin + case(switch_I2cGpioExpander_l182) + 8'h01 : begin + end + 8'h02 : begin + end + 8'h03 : begin + end + 8'h04 : begin + end + 8'h05 : begin + irq_rise_ctrl_io_clears = i2cCtrl_io_cmd_payload_data; + end + 8'h06 : begin + end + 8'h07 : begin + end + 8'h08 : begin + end + 8'h09 : begin + end + 8'h0a : begin + end + default : begin + end + endcase + end + default : begin + end + endcase + end + + always @(*) begin + irq_fall_ctrl_io_clears = 8'h0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + end + State_READ : begin + end + State_WRITE : begin + case(switch_I2cGpioExpander_l182) + 8'h01 : begin + end + 8'h02 : begin + end + 8'h03 : begin + end + 8'h04 : begin + end + 8'h05 : begin + end + 8'h06 : begin + irq_fall_ctrl_io_clears = i2cCtrl_io_cmd_payload_data; + end + 8'h07 : begin + end + 8'h08 : begin + end + 8'h09 : begin + end + 8'h0a : begin + end + default : begin + end + endcase + end + default : begin + end + endcase + end + + assign i2cCtrl_io_interrupts = (|(((irq_high_ctrl_io_pendings | irq_low_ctrl_io_pendings) | irq_rise_ctrl_io_pendings) | irq_fall_ctrl_io_pendings)); + always @(*) begin + i2cCtrl_io_cmd_ready = 1'b0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + i2cCtrl_io_cmd_ready = 1'b1; + end + State_READ : begin + i2cCtrl_io_cmd_ready = 1'b1; + end + State_WRITE : begin + i2cCtrl_io_cmd_ready = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + i2cCtrl_io_rsp_valid = 1'b0; + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + end + State_READ : begin + end + State_WRITE : begin + end + default : begin + i2cCtrl_io_rsp_valid = 1'b1; + end + endcase + end + + assign switch_I2cGpioExpander_l139 = link_regAddr; + assign switch_I2cGpioExpander_l182 = link_regAddr; + always @(posedge clock) begin + if(!reset) begin + i2cConfig_latch <= 1'b0; + gpioConfig_write <= 8'h0; + gpioConfig_direction <= 8'h0; + irq_high_masks <= 8'h0; + irq_low_masks <= 8'h0; + irq_rise_masks <= 8'h0; + irq_fall_masks <= 8'h0; + link_state <= State_IDLE; + link_data <= 8'h0; + link_error <= 1'b0; + end else begin + if(when_I2cGpioExpander_l46) begin + i2cConfig_latch <= 1'b1; + end + case(link_state) + State_IDLE : begin + if(i2cCtrl_io_cmd_valid) begin + link_error <= 1'b0; + if(i2cCtrl_io_cmd_payload_read) begin + link_state <= State_READ; + end else begin + if(i2cCtrl_io_cmd_payload_reg) begin + link_state <= State_REG_1; + end else begin + link_state <= State_WRITE; + end + end + end + end + State_REG_1 : begin + link_state <= State_RESPONSE; + end + State_READ : begin + case(switch_I2cGpioExpander_l139) + 8'h0 : begin + link_data <= gpioCtrl_1_io_value; + end + 8'h01 : begin + link_data <= gpioConfig_write; + end + 8'h02 : begin + link_data <= gpioConfig_direction; + end + 8'h03 : begin + link_data <= irq_high_ctrl_io_pendings; + end + 8'h04 : begin + link_data <= irq_low_ctrl_io_pendings; + end + 8'h05 : begin + link_data <= irq_rise_ctrl_io_pendings; + end + 8'h06 : begin + link_data <= irq_fall_ctrl_io_pendings; + end + 8'h07 : begin + link_data <= irq_high_masks; + end + 8'h08 : begin + link_data <= irq_low_masks; + end + 8'h09 : begin + link_data <= irq_rise_masks; + end + 8'h0a : begin + link_data <= irq_fall_masks; + end + default : begin + link_error <= 1'b1; + end + endcase + link_state <= State_RESPONSE; + end + State_WRITE : begin + case(switch_I2cGpioExpander_l182) + 8'h01 : begin + gpioConfig_write <= i2cCtrl_io_cmd_payload_data; + end + 8'h02 : begin + gpioConfig_direction <= i2cCtrl_io_cmd_payload_data; + end + 8'h03 : begin + end + 8'h04 : begin + end + 8'h05 : begin + end + 8'h06 : begin + end + 8'h07 : begin + irq_high_masks <= i2cCtrl_io_cmd_payload_data; + end + 8'h08 : begin + irq_low_masks <= i2cCtrl_io_cmd_payload_data; + end + 8'h09 : begin + irq_rise_masks <= i2cCtrl_io_cmd_payload_data; + end + 8'h0a : begin + irq_fall_masks <= i2cCtrl_io_cmd_payload_data; + end + default : begin + link_error <= 1'b1; + end + endcase + link_state <= State_RESPONSE; + end + default : begin + if(i2cCtrl_io_rsp_ready) begin + link_state <= State_IDLE; + end + end + endcase + end + end + + always @(posedge clock) begin + if(when_I2cGpioExpander_l46) begin + i2cConfig_latchedAddress <= io_address; + end + case(link_state) + State_IDLE : begin + end + State_REG_1 : begin + link_regAddr <= i2cCtrl_io_cmd_payload_data; + end + State_READ : begin + link_regAddr <= (link_regAddr + 8'h01); + end + State_WRITE : begin + link_regAddr <= (link_regAddr + 8'h01); + end + default : begin + end + endcase + end + + +endmodule + +//InterruptCtrl_3 replaced by InterruptCtrl + +//InterruptCtrl_2 replaced by InterruptCtrl + +//InterruptCtrl_1 replaced by InterruptCtrl + +module InterruptCtrl ( + input wire [7:0] io_inputs, + input wire [7:0] io_clears, + input wire [7:0] io_masks, + output wire [7:0] io_pendings, + input wire clock, + input wire reset +); + + reg [7:0] pendings; + + assign io_pendings = (pendings & io_masks); + always @(posedge clock) begin + if(!reset) begin + pendings <= 8'h0; + end else begin + pendings <= ((pendings & (~ io_clears)) | io_inputs); + end + end + + +endmodule + +module GpioCtrl ( + input wire [7:0] io_gpio_pins_read, + output wire [7:0] io_gpio_pins_write, + output wire [7:0] io_gpio_pins_writeEnable, + input wire [7:0] io_config_write, + input wire [7:0] io_config_direction, + output wire [7:0] io_value, + output wire io_interrupt, + output wire [7:0] io_irqHigh_valid, + input wire [7:0] io_irqHigh_pending, + output wire [7:0] io_irqLow_valid, + input wire [7:0] io_irqLow_pending, + output wire [7:0] io_irqRise_valid, + input wire [7:0] io_irqRise_pending, + output wire [7:0] io_irqFall_valid, + input wire [7:0] io_irqFall_pending, + input wire clock, + input wire reset +); + + wire [7:0] io_gpio_pins_read_buffercc_io_dataOut; + wire [7:0] synchronized; + reg [7:0] last; + + (* keep_hierarchy = "TRUE" *) BufferCC io_gpio_pins_read_buffercc ( + .io_dataIn (io_gpio_pins_read[7:0] ), //i + .io_dataOut (io_gpio_pins_read_buffercc_io_dataOut[7:0]), //o + .clock (clock ), //i + .reset (reset ) //i + ); + assign io_value = io_gpio_pins_read_buffercc_io_dataOut; + assign synchronized = io_value; + assign io_gpio_pins_write = io_config_write; + assign io_gpio_pins_writeEnable = io_config_direction; + assign io_irqHigh_valid = synchronized; + assign io_irqLow_valid = (~ synchronized); + assign io_irqRise_valid = (synchronized & (~ last)); + assign io_irqFall_valid = ((~ synchronized) & last); + assign io_interrupt = (|(((io_irqHigh_pending | io_irqLow_pending) | io_irqRise_pending) | io_irqFall_pending)); + always @(posedge clock) begin + last <= synchronized; + end + + +endmodule + +module I2cDeviceCtrl ( + input wire [15:0] io_config_clockDivider, + input wire [15:0] io_config_timeout, + input wire [6:0] io_config_deviceAddr, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire [0:0] io_i2c_interrupts, + input wire [0:0] io_interrupts, + output reg io_cmd_valid, + input wire io_cmd_ready, + output wire [7:0] io_cmd_payload_data, + output wire io_cmd_payload_reg, + output wire io_cmd_payload_read, + input wire io_rsp_valid, + output reg io_rsp_ready, + input wire [7:0] io_rsp_payload_data, + input wire io_rsp_payload_error, + input wire clock, + input wire reset +); + localparam State_1_IDLE = 2'd0; + localparam State_1_REQ = 2'd1; + localparam State_1_RSP = 2'd2; + + wire io_i2c_scl_read_buffercc_io_dataOut; + wire io_i2c_sda_read_buffercc_io_dataOut; + wire [7:0] _zz_ctrl_sdaWrite; + wire [2:0] _zz_ctrl_sdaWrite_1; + reg [15:0] filter_timer_counter; + wire filter_timer_tick; + wire filter_sampler_sclSync; + wire filter_sampler_sdaSync; + wire filter_sampler_sclSamples_0; + wire filter_sampler_sclSamples_1; + wire filter_sampler_sclSamples_2; + wire _zz_filter_sampler_sclSamples_0; + reg _zz_filter_sampler_sclSamples_1; + reg _zz_filter_sampler_sclSamples_2; + wire filter_sampler_sdaSamples_0; + wire filter_sampler_sdaSamples_1; + wire filter_sampler_sdaSamples_2; + wire _zz_filter_sampler_sdaSamples_0; + reg _zz_filter_sampler_sdaSamples_1; + reg _zz_filter_sampler_sdaSamples_2; + reg filter_sda; + reg filter_scl; + wire when_I2cDeviceCtrl_l52; + wire when_I2cDeviceCtrl_l55; + wire sclEdge_rise; + wire sclEdge_fall; + wire sclEdge_toggle; + reg filter_scl_regNext; + wire sdaEdge_rise; + wire sdaEdge_fall; + wire sdaEdge_toggle; + reg filter_sda_regNext; + wire detector_start; + wire detector_stop; + reg [15:0] timeout_value; + reg timeout_transmission; + wire when_I2cDeviceCtrl_l86; + wire when_I2cDeviceCtrl_l89; + reg [1:0] ctrl_state; + reg [10:0] ctrl_shiftRegister; + reg [4:0] ctrl_bitCounter; + reg [3:0] ctrl_frameCounter; + reg ctrl_transmission; + reg ctrl_sdaWrite; + wire [6:0] ctrl_address; + wire [7:0] ctrl_data; + reg ctrl_read; + wire ctrl_write; + reg ctrl_response_error; + reg [7:0] ctrl_response_data; + reg ctrl_cmdLock; + wire when_I2cDeviceCtrl_l123; + wire [4:0] _zz_ctrl_bitCounter; + wire when_I2cDeviceCtrl_l137; + wire when_I2cDeviceCtrl_l138; + wire when_I2cDeviceCtrl_l141; + wire when_I2cDeviceCtrl_l145; + wire when_I2cDeviceCtrl_l149; + wire when_I2cDeviceCtrl_l150; + wire when_I2cDeviceCtrl_l152; + wire when_I2cDeviceCtrl_l157; + wire when_I2cDeviceCtrl_l160; + wire when_I2cDeviceCtrl_l175; + wire io_cmd_fire; + `ifndef SYNTHESIS + reg [31:0] ctrl_state_string; + `endif + + + assign _zz_ctrl_sdaWrite = {ctrl_response_data[0],{ctrl_response_data[1],{ctrl_response_data[2],{ctrl_response_data[3],{ctrl_response_data[4],{ctrl_response_data[5],{ctrl_response_data[6],ctrl_response_data[7]}}}}}}}; + assign _zz_ctrl_sdaWrite_1 = ctrl_bitCounter[2:0]; + (* keep_hierarchy = "TRUE" *) BufferCC_1 io_i2c_scl_read_buffercc ( + .io_dataIn (io_i2c_scl_read ), //i + .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o + .clock (clock ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) BufferCC_1 io_i2c_sda_read_buffercc ( + .io_dataIn (io_i2c_sda_read ), //i + .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o + .clock (clock ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(ctrl_state) + State_1_IDLE : ctrl_state_string = "IDLE"; + State_1_REQ : ctrl_state_string = "REQ "; + State_1_RSP : ctrl_state_string = "RSP "; + default : ctrl_state_string = "????"; + endcase + end + `endif + + assign filter_timer_tick = (filter_timer_counter == 16'h0); + assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; + assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; + assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; + assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; + assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; + assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; + assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; + assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; + assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; + assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; + assign when_I2cDeviceCtrl_l52 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); + assign when_I2cDeviceCtrl_l55 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); + assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); + assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); + assign sclEdge_toggle = (filter_scl_regNext != filter_scl); + assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); + assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); + assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); + assign detector_start = (filter_scl && sdaEdge_fall); + assign detector_stop = (filter_scl && sdaEdge_rise); + assign when_I2cDeviceCtrl_l86 = ((detector_start || sclEdge_rise) || sclEdge_fall); + assign when_I2cDeviceCtrl_l89 = (filter_timer_tick && timeout_transmission); + assign ctrl_address = ctrl_shiftRegister[7 : 1]; + assign ctrl_data = ctrl_shiftRegister[7 : 0]; + assign ctrl_write = (! ctrl_read); + assign when_I2cDeviceCtrl_l123 = ((detector_start || detector_stop) || (timeout_value == io_config_timeout)); + assign _zz_ctrl_bitCounter[4 : 0] = 5'h1f; + assign when_I2cDeviceCtrl_l137 = (((ctrl_frameCounter == 4'b0000) || (((ctrl_frameCounter == 4'b0001) || ((! (ctrl_frameCounter == 4'b0000)) && (! (ctrl_frameCounter == 4'b0001)))) && ctrl_write)) && (ctrl_bitCounter == 5'h08)); + assign when_I2cDeviceCtrl_l138 = ((ctrl_frameCounter == 4'b0000) && (ctrl_address == io_config_deviceAddr)); + assign when_I2cDeviceCtrl_l141 = (((ctrl_frameCounter == 4'b0001) || ((! (ctrl_frameCounter == 4'b0000)) && (! (ctrl_frameCounter == 4'b0001)))) && (! ctrl_response_error)); + assign when_I2cDeviceCtrl_l145 = ((ctrl_read && (! (ctrl_frameCounter == 4'b0000))) && (((ctrl_frameCounter == 4'b0000) && (ctrl_bitCounter < 5'h08)) || ((! (ctrl_frameCounter == 4'b0000)) && (ctrl_bitCounter < 5'h08)))); + assign when_I2cDeviceCtrl_l149 = (sclEdge_rise && ctrl_transmission); + assign when_I2cDeviceCtrl_l150 = (((ctrl_frameCounter == 4'b0000) && (ctrl_bitCounter < 5'h08)) || ((! (ctrl_frameCounter == 4'b0000)) && (ctrl_bitCounter < 5'h08))); + assign when_I2cDeviceCtrl_l152 = ((ctrl_frameCounter == 4'b0000) && (ctrl_bitCounter == 5'h07)); + assign when_I2cDeviceCtrl_l157 = (sclEdge_fall && ctrl_transmission); + assign when_I2cDeviceCtrl_l160 = (ctrl_bitCounter == 5'h08); + always @(*) begin + io_cmd_valid = 1'b0; + case(ctrl_state) + State_1_IDLE : begin + end + State_1_REQ : begin + io_cmd_valid = 1'b1; + end + default : begin + end + endcase + end + + assign io_cmd_payload_data = ctrl_data; + assign io_cmd_payload_reg = (ctrl_frameCounter == 4'b0001); + assign io_cmd_payload_read = ctrl_read; + always @(*) begin + io_rsp_ready = 1'b0; + case(ctrl_state) + State_1_IDLE : begin + end + State_1_REQ : begin + end + default : begin + if(io_rsp_valid) begin + io_rsp_ready = 1'b1; + end + end + endcase + end + + assign when_I2cDeviceCtrl_l175 = (((! ctrl_cmdLock) && (ctrl_bitCounter == 5'h08)) && (((ctrl_frameCounter == 4'b0001) || (ctrl_read && (ctrl_frameCounter == 4'b0000))) || (ctrl_write && ((! (ctrl_frameCounter == 4'b0000)) && (! (ctrl_frameCounter == 4'b0001)))))); + assign io_cmd_fire = (io_cmd_valid && io_cmd_ready); + assign io_i2c_scl_write = 1'b0; + assign io_i2c_sda_write = ctrl_sdaWrite; + assign io_i2c_interrupts = io_interrupts; + always @(posedge clock) begin + if(!reset) begin + filter_timer_counter <= 16'h0; + _zz_filter_sampler_sclSamples_1 <= 1'b1; + _zz_filter_sampler_sclSamples_2 <= 1'b1; + _zz_filter_sampler_sdaSamples_1 <= 1'b1; + _zz_filter_sampler_sdaSamples_2 <= 1'b1; + filter_sda <= 1'b1; + filter_scl <= 1'b1; + filter_scl_regNext <= 1'b1; + filter_sda_regNext <= 1'b1; + timeout_value <= 16'h0; + timeout_transmission <= 1'b0; + ctrl_state <= State_1_IDLE; + ctrl_transmission <= 1'b0; + ctrl_sdaWrite <= 1'b0; + end else begin + filter_timer_counter <= (filter_timer_counter - 16'h0001); + if(filter_timer_tick) begin + filter_timer_counter <= io_config_clockDivider; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; + end + if(filter_timer_tick) begin + if(when_I2cDeviceCtrl_l52) begin + filter_sda <= filter_sampler_sdaSamples_2; + end + if(when_I2cDeviceCtrl_l55) begin + filter_scl <= filter_sampler_sclSamples_2; + end + end + filter_scl_regNext <= filter_scl; + filter_sda_regNext <= filter_sda; + if(detector_start) begin + timeout_transmission <= 1'b1; + end + if(detector_stop) begin + timeout_transmission <= 1'b0; + end + if(when_I2cDeviceCtrl_l86) begin + timeout_value <= 16'h0; + end + if(when_I2cDeviceCtrl_l89) begin + timeout_value <= (timeout_value + 16'h0001); + end + if(when_I2cDeviceCtrl_l123) begin + ctrl_state <= State_1_IDLE; + if(detector_start) begin + ctrl_transmission <= 1'b1; + end else begin + ctrl_transmission <= 1'b0; + end + end + ctrl_sdaWrite <= 1'b0; + if(when_I2cDeviceCtrl_l137) begin + if(when_I2cDeviceCtrl_l138) begin + ctrl_sdaWrite <= 1'b1; + end + if(when_I2cDeviceCtrl_l141) begin + ctrl_sdaWrite <= 1'b1; + end + end + if(when_I2cDeviceCtrl_l145) begin + ctrl_sdaWrite <= (! _zz_ctrl_sdaWrite[_zz_ctrl_sdaWrite_1]); + end + case(ctrl_state) + State_1_IDLE : begin + if(when_I2cDeviceCtrl_l175) begin + ctrl_state <= State_1_REQ; + end + end + State_1_REQ : begin + if(io_cmd_fire) begin + ctrl_state <= State_1_RSP; + end + end + default : begin + if(io_rsp_valid) begin + ctrl_state <= State_1_IDLE; + end + end + endcase + end + end + + always @(posedge clock) begin + if(when_I2cDeviceCtrl_l123) begin + ctrl_bitCounter <= _zz_ctrl_bitCounter; + ctrl_frameCounter <= 4'b0000; + ctrl_read <= 1'b0; + ctrl_response_error <= 1'b1; + end + if(when_I2cDeviceCtrl_l149) begin + if(when_I2cDeviceCtrl_l150) begin + ctrl_shiftRegister <= {ctrl_shiftRegister[9 : 0],filter_sda}; + if(when_I2cDeviceCtrl_l152) begin + ctrl_read <= filter_sda; + end + end + end + if(when_I2cDeviceCtrl_l157) begin + ctrl_bitCounter <= (ctrl_bitCounter + 5'h01); + ctrl_cmdLock <= 1'b0; + if(when_I2cDeviceCtrl_l160) begin + ctrl_bitCounter <= 5'h0; + ctrl_frameCounter <= (ctrl_frameCounter + 4'b0001); + end + end + case(ctrl_state) + State_1_IDLE : begin + end + State_1_REQ : begin + end + default : begin + if(io_rsp_valid) begin + ctrl_cmdLock <= 1'b1; + ctrl_response_data <= io_rsp_payload_data; + ctrl_response_error <= io_rsp_payload_error; + end + end + endcase + end + + +endmodule + +module BufferCC ( + input wire [7:0] io_dataIn, + output wire [7:0] io_dataOut, + input wire clock, + input wire reset +); + + (* async_reg = "true" *) reg [7:0] buffers_0; + + assign io_dataOut = buffers_0; + always @(posedge clock) begin + buffers_0 <= io_dataIn; + end + + +endmodule + +//BufferCC_2 replaced by BufferCC_1 + +module BufferCC_1 ( + input wire io_dataIn, + output wire io_dataOut, + input wire clock, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clock) begin + if(!reset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpanderTop.v b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpanderTop.v new file mode 100644 index 0000000000..8192e38f9d --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cGpioExpanderTop.v @@ -0,0 +1,202 @@ +// Generator : SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935 +// Component : SG13G2Top +// Git hash : dbd10e6c9374bd7bc3ffc29e541415e2be16643a + +`timescale 1ns/1ps + +module I2cGpioExpanderTop ( + inout wire io_clock_PAD, + inout wire io_reset_PAD, + inout wire io_i2c_scl_PAD, + inout wire io_i2c_sda_PAD, + inout wire io_i2c_interrupt_PAD, + inout wire io_gpio_0_PAD, + inout wire io_gpio_1_PAD, + inout wire io_gpio_2_PAD, + inout wire io_gpio_3_PAD, + inout wire io_gpio_4_PAD, + inout wire io_gpio_5_PAD, + inout wire io_gpio_6_PAD, + inout wire io_gpio_7_PAD, + inout wire io_address_0_PAD, + inout wire io_address_1_PAD, + inout wire io_address_2_PAD +); + + reg [7:0] system_expander_io_gpio_pins_read; + wire sg13g2_IOPad_io_i2c_interrupt_c2p; + wire sg13g2_IOPad_io_gpio_0_c2p; + wire sg13g2_IOPad_io_gpio_0_c2p_en; + wire sg13g2_IOPad_io_gpio_1_c2p; + wire sg13g2_IOPad_io_gpio_1_c2p_en; + wire sg13g2_IOPad_io_gpio_2_c2p; + wire sg13g2_IOPad_io_gpio_2_c2p_en; + wire sg13g2_IOPad_io_gpio_3_c2p; + wire sg13g2_IOPad_io_gpio_3_c2p_en; + wire sg13g2_IOPad_io_gpio_4_c2p; + wire sg13g2_IOPad_io_gpio_4_c2p_en; + wire sg13g2_IOPad_io_gpio_5_c2p; + wire sg13g2_IOPad_io_gpio_5_c2p_en; + wire sg13g2_IOPad_io_gpio_6_c2p; + wire sg13g2_IOPad_io_gpio_6_c2p_en; + wire sg13g2_IOPad_io_gpio_7_c2p; + wire sg13g2_IOPad_io_gpio_7_c2p_en; + wire sg13g2_IOPad_io_clock_p2c; + wire sg13g2_IOPad_io_reset_p2c; + wire sg13g2_IOPad_io_address_0_p2c; + wire sg13g2_IOPad_io_address_1_p2c; + wire sg13g2_IOPad_io_address_2_p2c; + wire system_expander_io_i2c_scl_write; + wire system_expander_io_i2c_sda_write; + wire [0:0] system_expander_io_i2c_interrupts; + wire [7:0] system_expander_io_gpio_pins_write; + wire [7:0] system_expander_io_gpio_pins_writeEnable; + wire sg13g2_IOPad_io_i2c_scl_p2c; + wire sg13g2_IOPad_io_i2c_sda_p2c; + wire sg13g2_IOPad_io_gpio_0_p2c; + wire sg13g2_IOPad_io_gpio_1_p2c; + wire sg13g2_IOPad_io_gpio_2_p2c; + wire sg13g2_IOPad_io_gpio_3_p2c; + wire sg13g2_IOPad_io_gpio_4_p2c; + wire sg13g2_IOPad_io_gpio_5_p2c; + wire sg13g2_IOPad_io_gpio_6_p2c; + wire sg13g2_IOPad_io_gpio_7_p2c; + wire clock; + wire reset; + reg [2:0] address; + + sg13g2_IOPadIn sg13g2_IOPad_io_clock ( + .p2c (sg13g2_IOPad_io_clock_p2c), //o + .pad (io_clock_PAD ) //~ + ); + sg13g2_IOPadIn sg13g2_IOPad_io_reset ( + .p2c (sg13g2_IOPad_io_reset_p2c), //o + .pad (io_reset_PAD ) //~ + ); + sg13g2_IOPadIn sg13g2_IOPad_io_address_0 ( + .p2c (sg13g2_IOPad_io_address_0_p2c), //o + .pad (io_address_0_PAD ) //~ + ); + sg13g2_IOPadIn sg13g2_IOPad_io_address_1 ( + .p2c (sg13g2_IOPad_io_address_1_p2c), //o + .pad (io_address_1_PAD ) //~ + ); + sg13g2_IOPadIn sg13g2_IOPad_io_address_2 ( + .p2c (sg13g2_IOPad_io_address_2_p2c), //o + .pad (io_address_2_PAD ) //~ + ); + I2cGpioExpander system_expander ( + .io_address (address[2:0] ), //i + .io_i2c_scl_write (system_expander_io_i2c_scl_write ), //o + .io_i2c_scl_read (sg13g2_IOPad_io_i2c_scl_p2c ), //i + .io_i2c_sda_write (system_expander_io_i2c_sda_write ), //o + .io_i2c_sda_read (sg13g2_IOPad_io_i2c_sda_p2c ), //i + .io_i2c_interrupts (system_expander_io_i2c_interrupts ), //o + .io_gpio_pins_read (system_expander_io_gpio_pins_read[7:0] ), //i + .io_gpio_pins_write (system_expander_io_gpio_pins_write[7:0] ), //o + .io_gpio_pins_writeEnable (system_expander_io_gpio_pins_writeEnable[7:0]), //o + .clock (clock ), //i + .reset (reset ) //i + ); + sg13g2_IOPadOut4mA sg13g2_IOPad_io_i2c_interrupt ( + .c2p (sg13g2_IOPad_io_i2c_interrupt_c2p), //i + .pad (io_i2c_interrupt_PAD ) //~ + ); + sg13g2_IOPadInOut4mA sg13g2_IOPad_io_i2c_scl ( + .c2p (1'b0 ), //i + .c2p_en (system_expander_io_i2c_scl_write), //i + .p2c (sg13g2_IOPad_io_i2c_scl_p2c ), //o + .pad (io_i2c_scl_PAD ) //~ + ); + sg13g2_IOPadInOut4mA sg13g2_IOPad_io_i2c_sda ( + .c2p (1'b0 ), //i + .c2p_en (system_expander_io_i2c_sda_write), //i + .p2c (sg13g2_IOPad_io_i2c_sda_p2c ), //o + .pad (io_i2c_sda_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_0 ( + .c2p (sg13g2_IOPad_io_gpio_0_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_0_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_0_p2c ), //o + .pad (io_gpio_0_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_1 ( + .c2p (sg13g2_IOPad_io_gpio_1_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_1_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_1_p2c ), //o + .pad (io_gpio_1_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_2 ( + .c2p (sg13g2_IOPad_io_gpio_2_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_2_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_2_p2c ), //o + .pad (io_gpio_2_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_3 ( + .c2p (sg13g2_IOPad_io_gpio_3_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_3_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_3_p2c ), //o + .pad (io_gpio_3_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_4 ( + .c2p (sg13g2_IOPad_io_gpio_4_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_4_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_4_p2c ), //o + .pad (io_gpio_4_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_5 ( + .c2p (sg13g2_IOPad_io_gpio_5_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_5_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_5_p2c ), //o + .pad (io_gpio_5_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_6 ( + .c2p (sg13g2_IOPad_io_gpio_6_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_6_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_6_p2c ), //o + .pad (io_gpio_6_PAD ) //~ + ); + sg13g2_IOPadInOut16mA sg13g2_IOPad_io_gpio_7 ( + .c2p (sg13g2_IOPad_io_gpio_7_c2p ), //i + .c2p_en (sg13g2_IOPad_io_gpio_7_c2p_en), //i + .p2c (sg13g2_IOPad_io_gpio_7_p2c ), //o + .pad (io_gpio_7_PAD ) //~ + ); + assign clock = sg13g2_IOPad_io_clock_p2c; + assign reset = sg13g2_IOPad_io_reset_p2c; + always @(*) begin + address[0] = sg13g2_IOPad_io_address_0_p2c; + address[1] = sg13g2_IOPad_io_address_1_p2c; + address[2] = sg13g2_IOPad_io_address_2_p2c; + end + + assign sg13g2_IOPad_io_i2c_interrupt_c2p = system_expander_io_i2c_interrupts[0]; + assign sg13g2_IOPad_io_gpio_0_c2p = system_expander_io_gpio_pins_write[0]; + assign sg13g2_IOPad_io_gpio_0_c2p_en = system_expander_io_gpio_pins_writeEnable[0]; + always @(*) begin + system_expander_io_gpio_pins_read[0] = sg13g2_IOPad_io_gpio_0_p2c; + system_expander_io_gpio_pins_read[1] = sg13g2_IOPad_io_gpio_1_p2c; + system_expander_io_gpio_pins_read[2] = sg13g2_IOPad_io_gpio_2_p2c; + system_expander_io_gpio_pins_read[3] = sg13g2_IOPad_io_gpio_3_p2c; + system_expander_io_gpio_pins_read[4] = sg13g2_IOPad_io_gpio_4_p2c; + system_expander_io_gpio_pins_read[5] = sg13g2_IOPad_io_gpio_5_p2c; + system_expander_io_gpio_pins_read[6] = sg13g2_IOPad_io_gpio_6_p2c; + system_expander_io_gpio_pins_read[7] = sg13g2_IOPad_io_gpio_7_p2c; + end + + assign sg13g2_IOPad_io_gpio_1_c2p = system_expander_io_gpio_pins_write[1]; + assign sg13g2_IOPad_io_gpio_1_c2p_en = system_expander_io_gpio_pins_writeEnable[1]; + assign sg13g2_IOPad_io_gpio_2_c2p = system_expander_io_gpio_pins_write[2]; + assign sg13g2_IOPad_io_gpio_2_c2p_en = system_expander_io_gpio_pins_writeEnable[2]; + assign sg13g2_IOPad_io_gpio_3_c2p = system_expander_io_gpio_pins_write[3]; + assign sg13g2_IOPad_io_gpio_3_c2p_en = system_expander_io_gpio_pins_writeEnable[3]; + assign sg13g2_IOPad_io_gpio_4_c2p = system_expander_io_gpio_pins_write[4]; + assign sg13g2_IOPad_io_gpio_4_c2p_en = system_expander_io_gpio_pins_writeEnable[4]; + assign sg13g2_IOPad_io_gpio_5_c2p = system_expander_io_gpio_pins_write[5]; + assign sg13g2_IOPad_io_gpio_5_c2p_en = system_expander_io_gpio_pins_writeEnable[5]; + assign sg13g2_IOPad_io_gpio_6_c2p = system_expander_io_gpio_pins_write[6]; + assign sg13g2_IOPad_io_gpio_6_c2p_en = system_expander_io_gpio_pins_writeEnable[6]; + assign sg13g2_IOPad_io_gpio_7_c2p = system_expander_io_gpio_pins_write[7]; + assign sg13g2_IOPad_io_gpio_7_c2p_en = system_expander_io_gpio_pins_writeEnable[7]; + +endmodule diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk new file mode 100644 index 0000000000..f46620b481 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk @@ -0,0 +1,24 @@ +export DESIGN_NAME = I2cGpioExpanderTop +export DESIGN_NICKNAME = i2c-gpio-expander +export PLATFORM = ihp-sg13g2 + +export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/I2cGpioExpander.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz + +export DIE_AREA = 0.0 0.0 1050.0 1050.0 +export CORE_AREA = 351.36 351.54 699.84 699.3 + +export MAX_ROUTING_LAYER = TopMetal2 + +export TNS_END_PERCENT = 100 +export PLACE_DENSITY = 0.75 + +export CORNERS = slow fast + +export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl +export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl + +export BLOCKS = I2cDeviceCtrl diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc new file mode 100644 index 0000000000..b66bcf5e1c --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc @@ -0,0 +1,56 @@ +current_design SG13G2Top +set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA +set_max_fanout 8 [current_design] +set_max_capacitance 0.5 [current_design] +set_max_transition 3 [current_design] +set_max_area 0 + +set_ideal_network [get_pins sg13g2_IOPad_io_clock/p2c] +create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -waveform {0 10.0} +set_clock_uncertainty 0.15 [get_clocks clk_core] +set_clock_transition 0.25 [get_clocks clk_core] + +set clock_ports [get_ports { + io_clock_PAD +}] +set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clock_ports + +set clk_core_inout_16mA_ports [get_ports { + io_gpio_0_PAD + io_gpio_1_PAD + io_gpio_2_PAD + io_gpio_3_PAD + io_gpio_4_PAD + io_gpio_5_PAD + io_gpio_6_PAD + io_gpio_7_PAD +}] +set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports +set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports +set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports + +set clk_core_inout_4mA_ports [get_ports { + io_i2c_scl_PAD + io_i2c_sda_PAD +}] +set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports +set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports +set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports + +set clk_core_input_ports [get_ports { + io_reset_PAD + io_address_0_PAD + io_address_1_PAD + io_address_2_PAD +}] +set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports +set_input_delay 8 -clock clk_core $clk_core_input_ports + +set clk_core_output_4mA_ports [get_ports { + io_i2c_interrupt_PAD +}] +set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports +set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports + +set_load -pin_load 5 [all_inputs] +set_load -pin_load 5 [all_outputs] diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json new file mode 100644 index 0000000000..0cfab656d7 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/metadata-base-ok.json @@ -0,0 +1,399 @@ +{ + "constraints__clocks__count": 1, + "constraints__clocks__details": [ + "clk_core: 20.0000" + ], + "cts__clock__skew__hold": 0.416925, + "cts__clock__skew__setup": 0.416925, + "cts__cpu__total": 1.74, + "cts__design__core__area": 121187, + "cts__design__die__area": 1102500.0, + "cts__design__instance__area": 36578.3, + "cts__design__instance__area__cover": 98000, + "cts__design__instance__area__macros": 21794.6, + "cts__design__instance__area__padcells": 424800, + "cts__design__instance__area__stdcell": 14783.7, + "cts__design__instance__count": 985, + "cts__design__instance__count__cover": 20, + "cts__design__instance__count__hold_buffer": 0, + "cts__design__instance__count__macros": 1, + "cts__design__instance__count__padcells": 48, + "cts__design__instance__count__setup_buffer": 0, + "cts__design__instance__count__stdcell": 916, + "cts__design__instance__displacement__max": 0, + "cts__design__instance__displacement__mean": 0, + "cts__design__instance__displacement__total": 0, + "cts__design__instance__utilization": 0.301833, + "cts__design__instance__utilization__stdcell": 0.14874, + "cts__design__io": 20, + "cts__design__rows": 133, + "cts__design__rows:CoreSite": 133, + "cts__design__sites": 53754, + "cts__design__sites:CoreSite": 53754, + "cts__design__violations": 0, + "cts__flow__errors__count": 0, + "cts__flow__warnings__count": 1, + "cts__mem__peak": 223804.0, + "cts__power__internal__total": 6.36515e-05, + "cts__power__leakage__total": 6.15849e-07, + "cts__power__switching__total": 1.14976e-05, + "cts__power__total": 7.5765e-05, + "cts__route__wirelength__estimated": 32399.4, + "cts__runtime__total": "0:01.36", + "cts__timing__drv__hold_violation_count": 0, + "cts__timing__drv__max_cap": 27, + "cts__timing__drv__max_cap_limit": -9.58431, + "cts__timing__drv__max_fanout": 0, + "cts__timing__drv__max_fanout_limit": 8, + "cts__timing__drv__max_slew": 25, + "cts__timing__drv__max_slew_limit": -5.32153, + "cts__timing__drv__setup_violation_count": 0, + "cts__timing__hold__tns": 0, + "cts__timing__hold__ws": 0.0665765, + "cts__timing__setup__tns": 0, + "cts__timing__setup__ws": 3.44505, + "design__violations": 0, + "detailedplace__cpu__total": 0.94, + "detailedplace__design__core__area": 121187, + "detailedplace__design__die__area": 1102500.0, + "detailedplace__design__instance__area": 34050.8, + "detailedplace__design__instance__area__cover": 98000, + "detailedplace__design__instance__area__macros": 21794.6, + "detailedplace__design__instance__area__padcells": 424800, + "detailedplace__design__instance__area__stdcell": 12256.3, + "detailedplace__design__instance__count": 924, + "detailedplace__design__instance__count__cover": 20, + "detailedplace__design__instance__count__macros": 1, + "detailedplace__design__instance__count__padcells": 48, + "detailedplace__design__instance__count__stdcell": 855, + "detailedplace__design__instance__displacement__max": 13.101, + "detailedplace__design__instance__displacement__mean": 3.157, + "detailedplace__design__instance__displacement__total": 2702.6, + "detailedplace__design__instance__utilization": 0.280977, + "detailedplace__design__instance__utilization__stdcell": 0.123311, + "detailedplace__design__io": 20, + "detailedplace__design__rows": 133, + "detailedplace__design__rows:CoreSite": 133, + "detailedplace__design__sites": 53754, + "detailedplace__design__sites:CoreSite": 53754, + "detailedplace__design__violations": 0, + "detailedplace__flow__errors__count": 0, + "detailedplace__flow__warnings__count": 1, + "detailedplace__mem__peak": 126980.0, + "detailedplace__power__internal__total": 3.34988e-05, + "detailedplace__power__leakage__total": 3.57528e-07, + "detailedplace__power__switching__total": 6.76419e-06, + "detailedplace__power__total": 4.06205e-05, + "detailedplace__route__wirelength__estimated": 27769.5, + "detailedplace__runtime__total": "0:00.70", + "detailedplace__timing__drv__hold_violation_count": 0, + "detailedplace__timing__drv__max_cap": 27, + "detailedplace__timing__drv__max_cap_limit": -9.58431, + "detailedplace__timing__drv__max_fanout": 0, + "detailedplace__timing__drv__max_fanout_limit": 8, + "detailedplace__timing__drv__max_slew": 25, + "detailedplace__timing__drv__max_slew_limit": -5.32153, + "detailedplace__timing__drv__setup_violation_count": 0, + "detailedplace__timing__hold__tns": 0, + "detailedplace__timing__hold__ws": 0.0614673, + "detailedplace__timing__setup__tns": 0, + "detailedplace__timing__setup__ws": 3.44505, + "detailedroute__antenna__violating__nets": 0, + "detailedroute__antenna__violating__pins": 0, + "detailedroute__antenna_diodes_count": 2, + "detailedroute__flow__errors__count": 0, + "detailedroute__flow__warnings__count": 11, + "detailedroute__route__drc_errors": 0, + "detailedroute__route__drc_errors__iter:0": 6, + "detailedroute__route__drc_errors__iter:1": 1, + "detailedroute__route__drc_errors__iter:2": 0, + "detailedroute__route__drc_errors__iter:3": 27, + "detailedroute__route__drc_errors__iter:4": 3, + "detailedroute__route__drc_errors__iter:5": 0, + "detailedroute__route__net": 1062, + "detailedroute__route__net__special": 24, + "detailedroute__route__vias": 6330, + "detailedroute__route__vias__multicut": 0, + "detailedroute__route__vias__singlecut": 6330, + "detailedroute__route__wirelength": 37033, + "detailedroute__route__wirelength__iter:0": 37038, + "detailedroute__route__wirelength__iter:1": 37035, + "detailedroute__route__wirelength__iter:2": 37033, + "detailedroute__route__wirelength__iter:3": 37018, + "detailedroute__route__wirelength__iter:4": 37007, + "detailedroute__route__wirelength__iter:5": 37012, + "finish__clock__skew__hold": 0.48647, + "finish__clock__skew__setup": 0.462837, + "finish__cpu__total": 4.47, + "finish__design__core__area": 121187, + "finish__design__die__area": 1102500.0, + "finish__design__instance__area": 118272, + "finish__design__instance__area__class:antenna_cell": 576.979, + "finish__design__instance__area__class:clock_buffer": 2494.8, + "finish__design__instance__area__class:clock_inverter": 32.6592, + "finish__design__instance__area__class:cover": 98000, + "finish__design__instance__area__class:input_output_pad": 144000, + "finish__design__instance__area__class:input_pad": 72000, + "finish__design__instance__area__class:inverter": 154.224, + "finish__design__instance__area__class:macro": 21794.6, + "finish__design__instance__area__class:multi_input_combinational_cell": 5889.54, + "finish__design__instance__area__class:output_pad": 14400, + "finish__design__instance__area__class:pad_spacer": 136800, + "finish__design__instance__area__class:power_pad": 57600, + "finish__design__instance__area__class:sequential_cell": 5755.28, + "finish__design__instance__area__class:timing_repair_buffer": 457.229, + "finish__design__instance__area__cover": 98000, + "finish__design__instance__area__macros": 21794.6, + "finish__design__instance__area__padcells": 424800, + "finish__design__instance__area__stdcell": 96477.1, + "finish__design__instance__count": 7518, + "finish__design__instance__count__class:antenna_cell": 106, + "finish__design__instance__count__class:clock_buffer": 55, + "finish__design__instance__count__class:clock_inverter": 6, + "finish__design__instance__count__class:cover": 20, + "finish__design__instance__count__class:input_output_pad": 10, + "finish__design__instance__count__class:input_pad": 5, + "finish__design__instance__count__class:inverter": 28, + "finish__design__instance__count__class:macro": 1, + "finish__design__instance__count__class:multi_input_combinational_cell": 642, + "finish__design__instance__count__class:output_pad": 1, + "finish__design__instance__count__class:pad_spacer": 28, + "finish__design__instance__count__class:power_pad": 4, + "finish__design__instance__count__class:sequential_cell": 122, + "finish__design__instance__count__class:timing_repair_buffer": 63, + "finish__design__instance__count__cover": 20, + "finish__design__instance__count__macros": 1, + "finish__design__instance__count__padcells": 48, + "finish__design__instance__count__stdcell": 7449, + "finish__design__instance__utilization": 0.97594, + "finish__design__instance__utilization__stdcell": 0.970664, + "finish__design__io": 20, + "finish__design__rows": 133, + "finish__design__rows:CoreSite": 133, + "finish__design__sites": 53754, + "finish__design__sites:CoreSite": 53754, + "finish__design_powergrid__drop__average__net:VDD__corner:fast": 1.19999, + "finish__design_powergrid__drop__average__net:VSS__corner:fast": 5.72021e-06, + "finish__design_powergrid__drop__worst__net:VDD__corner:fast": 3.33034e-05, + "finish__design_powergrid__drop__worst__net:VSS__corner:fast": 2.81877e-05, + "finish__design_powergrid__voltage__worst__net:VDD__corner:fast": 1.19997, + "finish__design_powergrid__voltage__worst__net:VSS__corner:fast": 2.81877e-05, + "finish__flow__errors__count": 0, + "finish__flow__warnings__count": 2, + "finish__mem__peak": 266520.0, + "finish__power__internal__total": 5.79117e-05, + "finish__power__leakage__total": 1.87494e-06, + "finish__power__switching__total": 1.32977e-05, + "finish__power__total": 7.30843e-05, + "finish__runtime__total": "0:04.06", + "finish__timing__drv__hold_violation_count": 0, + "finish__timing__drv__max_cap": 27, + "finish__timing__drv__max_cap_limit": -9.58431, + "finish__timing__drv__max_fanout": 3, + "finish__timing__drv__max_fanout_limit": 8, + "finish__timing__drv__max_slew": 25, + "finish__timing__drv__max_slew_limit": -5.32041, + "finish__timing__drv__setup_violation_count": 0, + "finish__timing__hold__tns": 0, + "finish__timing__hold__ws": 0.033864, + "finish__timing__setup__tns": 0, + "finish__timing__setup__ws": 3.88761, + "finish__timing__wns_percent_delay": 48.824475, + "finish_merge__cpu__total": 1.38, + "finish_merge__mem__peak": 473592.0, + "finish_merge__runtime__total": "0:01.53", + "floorplan__cpu__total": 0.63, + "floorplan__design__core__area": 121187, + "floorplan__design__die__area": 1102500.0, + "floorplan__design__instance__area": 33045.7, + "floorplan__design__instance__area__cover": 98000, + "floorplan__design__instance__area__macros": 21794.6, + "floorplan__design__instance__area__padcells": 424800, + "floorplan__design__instance__area__stdcell": 11251.1, + "floorplan__design__instance__count": 754, + "floorplan__design__instance__count__cover": 20, + "floorplan__design__instance__count__hold_buffer": 0, + "floorplan__design__instance__count__macros": 1, + "floorplan__design__instance__count__padcells": 48, + "floorplan__design__instance__count__setup_buffer": 0, + "floorplan__design__instance__count__stdcell": 685, + "floorplan__design__instance__utilization": 0.272682, + "floorplan__design__instance__utilization__stdcell": 0.113198, + "floorplan__design__io": 20, + "floorplan__design__rows": 92, + "floorplan__design__rows:CoreSite": 92, + "floorplan__design__sites": 66792, + "floorplan__design__sites:CoreSite": 66792, + "floorplan__flow__errors__count": 0, + "floorplan__flow__warnings__count": 7, + "floorplan__mem__peak": 116856.0, + "floorplan__power__internal__total": 3.26237e-05, + "floorplan__power__leakage__total": 3.66049e-07, + "floorplan__power__switching__total": 4.05039e-06, + "floorplan__power__total": 3.70401e-05, + "floorplan__runtime__total": "0:00.45", + "floorplan__timing__hold__tns": 0, + "floorplan__timing__hold__ws": 0.0483089, + "floorplan__timing__setup__tns": 0, + "floorplan__timing__setup__ws": 3.57371, + "flow__errors__count": 0, + "flow__warnings__count": 1, + "globalplace__cpu__total": 14.31, + "globalplace__design__core__area": 121187, + "globalplace__design__die__area": 1102500.0, + "globalplace__design__instance__area": 32911.4, + "globalplace__design__instance__area__cover": 98000, + "globalplace__design__instance__area__macros": 21794.6, + "globalplace__design__instance__area__padcells": 424800, + "globalplace__design__instance__area__stdcell": 11116.8, + "globalplace__design__instance__count": 767, + "globalplace__design__instance__count__cover": 20, + "globalplace__design__instance__count__macros": 1, + "globalplace__design__instance__count__padcells": 48, + "globalplace__design__instance__count__stdcell": 698, + "globalplace__design__instance__utilization": 0.271574, + "globalplace__design__instance__utilization__stdcell": 0.111847, + "globalplace__design__io": 20, + "globalplace__design__rows": 133, + "globalplace__design__rows:CoreSite": 133, + "globalplace__design__sites": 53754, + "globalplace__design__sites:CoreSite": 53754, + "globalplace__flow__errors__count": 0, + "globalplace__flow__warnings__count": 1, + "globalplace__mem__peak": 701500.0, + "globalplace__power__internal__total": 3.35075e-05, + "globalplace__power__leakage__total": 3.55326e-07, + "globalplace__power__switching__total": 6.72037e-06, + "globalplace__power__total": 4.05832e-05, + "globalplace__runtime__total": "0:02.59", + "globalplace__timing__hold__tns": 0, + "globalplace__timing__hold__ws": 0.0627901, + "globalplace__timing__setup__tns": 0, + "globalplace__timing__setup__ws": 3.44505, + "globalplace_io__cpu__total": 0.09, + "globalplace_io__mem__peak": 98292.0, + "globalplace_io__runtime__total": "0:00.12", + "globalplace_skip_io__cpu__total": 8.01, + "globalplace_skip_io__mem__peak": 114176.0, + "globalplace_skip_io__runtime__total": "0:00.70", + "globalroute__antenna__violating__nets": 2, + "globalroute__antenna__violating__pins": 4, + "globalroute__antenna_diodes_count": 104, + "globalroute__clock__skew__hold": 0.507695, + "globalroute__clock__skew__setup": 0.471571, + "globalroute__cpu__total": 40.2, + "globalroute__design__core__area": 121187, + "globalroute__design__die__area": 1102500.0, + "globalroute__design__instance__area": 37144.4, + "globalroute__design__instance__area__cover": 98000, + "globalroute__design__instance__area__macros": 21794.6, + "globalroute__design__instance__area__padcells": 424800, + "globalroute__design__instance__area__stdcell": 15349.8, + "globalroute__design__instance__count": 1089, + "globalroute__design__instance__count__cover": 20, + "globalroute__design__instance__count__hold_buffer": 0, + "globalroute__design__instance__count__macros": 1, + "globalroute__design__instance__count__padcells": 48, + "globalroute__design__instance__count__setup_buffer": 0, + "globalroute__design__instance__count__stdcell": 1020, + "globalroute__design__instance__displacement__max": 0, + "globalroute__design__instance__displacement__mean": 0, + "globalroute__design__instance__displacement__total": 0, + "globalroute__design__instance__utilization": 0.306504, + "globalroute__design__instance__utilization__stdcell": 0.154436, + "globalroute__design__io": 20, + "globalroute__design__rows": 133, + "globalroute__design__rows:CoreSite": 133, + "globalroute__design__sites": 53754, + "globalroute__design__sites:CoreSite": 53754, + "globalroute__design__violations": 0, + "globalroute__flow__errors__count": 0, + "globalroute__flow__warnings__count": 11, + "globalroute__mem__peak": 751424.0, + "globalroute__power__internal__total": 5.83437e-05, + "globalroute__power__leakage__total": 6.16393e-07, + "globalroute__power__switching__total": 1.5735e-05, + "globalroute__power__total": 7.46951e-05, + "globalroute__route__net": 1062, + "globalroute__route__net__special": 24, + "globalroute__route__wirelength__estimated": 32399.4, + "globalroute__runtime__total": "0:05.61", + "globalroute__timing__clock__slack": 3.812, + "globalroute__timing__drv__hold_violation_count": 0, + "globalroute__timing__drv__max_cap": 27, + "globalroute__timing__drv__max_cap_limit": -9.58431, + "globalroute__timing__drv__max_fanout": 3, + "globalroute__timing__drv__max_fanout_limit": 8, + "globalroute__timing__drv__max_slew": 25, + "globalroute__timing__drv__max_slew_limit": -5.32154, + "globalroute__timing__drv__setup_violation_count": 0, + "globalroute__timing__hold__tns": 0, + "globalroute__timing__hold__ws": 0.0494376, + "globalroute__timing__setup__tns": 0, + "globalroute__timing__setup__ws": 3.81203, + "placeopt__cpu__total": 1.15, + "placeopt__design__core__area": 121187, + "placeopt__design__die__area": 1102500.0, + "placeopt__design__instance__area": 34050.8, + "placeopt__design__instance__area__cover": 98000, + "placeopt__design__instance__area__macros": 21794.6, + "placeopt__design__instance__area__padcells": 424800, + "placeopt__design__instance__area__stdcell": 12256.3, + "placeopt__design__instance__count": 924, + "placeopt__design__instance__count__cover": 20, + "placeopt__design__instance__count__macros": 1, + "placeopt__design__instance__count__padcells": 48, + "placeopt__design__instance__count__stdcell": 855, + "placeopt__design__instance__utilization": 0.280977, + "placeopt__design__instance__utilization__stdcell": 0.123311, + "placeopt__design__io": 20, + "placeopt__design__rows": 133, + "placeopt__design__rows:CoreSite": 133, + "placeopt__design__sites": 53754, + "placeopt__design__sites:CoreSite": 53754, + "placeopt__flow__errors__count": 0, + "placeopt__flow__warnings__count": 2, + "placeopt__mem__peak": 641056.0, + "placeopt__power__internal__total": 3.35075e-05, + "placeopt__power__leakage__total": 3.57528e-07, + "placeopt__power__switching__total": 1.18703e-05, + "placeopt__power__total": 4.57353e-05, + "placeopt__runtime__total": "0:00.88", + "placeopt__timing__drv__floating__nets": 4, + "placeopt__timing__drv__floating__pins": 0, + "placeopt__timing__drv__hold_violation_count": 0, + "placeopt__timing__drv__max_cap": 27, + "placeopt__timing__drv__max_cap_limit": -9.58431, + "placeopt__timing__drv__max_fanout": 0, + "placeopt__timing__drv__max_fanout_limit": 8, + "placeopt__timing__drv__max_slew": 25, + "placeopt__timing__drv__max_slew_limit": -5.32153, + "placeopt__timing__drv__setup_violation_count": 0, + "placeopt__timing__hold__tns": 0, + "placeopt__timing__hold__ws": 0.0627901, + "placeopt__timing__setup__tns": 0, + "placeopt__timing__setup__ws": 3.44505, + "run__flow__design": "i2c-gpio-expander", + "run__flow__generate_date": "2025-06-27 17:15", + "run__flow__metrics_version": "Metrics_2.1.2", + "run__flow__openroad_commit": "N/A", + "run__flow__openroad_version": "v2.0-18663-g4a7c6dd8f", + "run__flow__platform": "ihp-sg13g2", + "run__flow__platform__capacitance_units": "1pF", + "run__flow__platform__current_units": "1uA", + "run__flow__platform__distance_units": "1um", + "run__flow__platform__power_units": "1pW", + "run__flow__platform__resistance_units": "1kohm", + "run__flow__platform__time_units": "1ns", + "run__flow__platform__voltage_units": "1v", + "run__flow__platform_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1", + "run__flow__scripts_commit": "2b92477257a655e1c3d56c83372e3ea6262fc7e1", + "run__flow__uuid": "a55e4f22-7f3b-48eb-84a6-b10f6fde9a2a", + "run__flow__variant": "base", + "synth__cpu__total": 0.88, + "synth__design__instance__area__stdcell": 253699.051, + "synth__design__instance__count__stdcell": 702.0, + "synth__mem__peak": 26056.0, + "synth__runtime__total": "0:00.90", + "total_time": "0:00:18.900000" +} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl new file mode 100644 index 0000000000..049987ebe2 --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pad.tcl @@ -0,0 +1,200 @@ +set IO_LENGTH 180 +set IO_WIDTH 80 +set BONDPAD_SIZE 70 +set SEALRING_OFFSET 70 +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] + +proc calc_horizontal_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { + set DIE_WIDTH [expr { [lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_WIDTH [expr { $DIE_WIDTH - ($PAD_OFFSET * 2) }] + set HORIZONTAL_PAD_DISTANCE [expr { ($PAD_AREA_WIDTH / $total) - $IO_WIDTH }] + + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + + ($HORIZONTAL_PAD_DISTANCE / 2) + }] +} + +proc calc_vertical_pad_location { index total IO_LENGTH IO_WIDTH BONDPAD_SIZE SEALRING_OFFSET } { + set DIE_HEIGHT [expr { [lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1] }] + set PAD_OFFSET [expr { $IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET }] + set PAD_AREA_HEIGHT [expr { $DIE_HEIGHT - ($PAD_OFFSET * 2) }] + set VERTICAL_PAD_DISTANCE [expr { ($PAD_AREA_HEIGHT / $total) - $IO_WIDTH }] + + return [expr { + $PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + + ($VERTICAL_PAD_DISTANCE / 2) + }] +} + +make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH +make_fake_io_site -name IOLibCSite -width $IO_LENGTH -height $IO_LENGTH + +set IO_OFFSET [expr { $BONDPAD_SIZE + $SEALRING_OFFSET }] +# Create IO Rows +make_io_sites \ + -horizontal_site IOLibSite \ + -vertical_site IOLibSite \ + -corner_site IOLibCSite \ + -offset $IO_OFFSET + +# Place Pads +# IO pin io_clock +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_clock} \ + -master sg13g2_IOPadIn +# IO pin io_reset +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_reset} \ + -master sg13g2_IOPadIn +# IO pin io_i2c_scl +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_scl} \ + -master sg13g2_IOPadInOut4mA +# IO pin io_i2c_sda +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_sda} \ + -master sg13g2_IOPadInOut4mA +# IO pin io_i2c_interrupt +place_pad \ + -row IO_SOUTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_i2c_interrupt} \ + -master sg13g2_IOPadOut4mA +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVdd_east_0} \ + -master sg13g2_IOPadVdd +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadVss_east_1} \ + -master sg13g2_IOPadVss +# IO pin io_address_0 +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_0} \ + -master sg13g2_IOPadIn +# IO pin io_address_1 +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_1} \ + -master sg13g2_IOPadIn +# IO pin io_address_2 +place_pad \ + -row IO_EAST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_address_2} \ + -master sg13g2_IOPadIn +# IO pin io_gpio_0 +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_0} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_1 +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_1} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_2 +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_2} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_3 +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_3} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_4 +place_pad \ + -row IO_NORTH \ + -location [calc_horizontal_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_4} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_5 +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 0 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_5} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_6 +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 1 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_6} \ + -master sg13g2_IOPadInOut16mA +# IO pin io_gpio_7 +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 2 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPad_io_gpio_7} \ + -master sg13g2_IOPadInOut16mA +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 3 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVss_west_3} \ + -master sg13g2_IOPadIOVss +place_pad \ + -row IO_WEST \ + -location [calc_vertical_pad_location \ + 4 5 $IO_LENGTH $IO_WIDTH $BONDPAD_SIZE $SEALRING_OFFSET] \ + {sg13g2_IOPadIOVdd_west_4} \ + -master sg13g2_IOPadIOVdd +# Place Corner Cells and Filler +place_corners sg13g2_Corner + +set iofill { + sg13g2_Filler10000 + sg13g2_Filler4000 + sg13g2_Filler2000 + sg13g2_Filler1000 + sg13g2_Filler400 + sg13g2_Filler200 +} + +place_io_fill -row IO_NORTH {*}$iofill +place_io_fill -row IO_SOUTH {*}$iofill +place_io_fill -row IO_WEST {*}$iofill +place_io_fill -row IO_EAST {*}$iofill + +connect_by_abutment + +place_bondpad -bond bondpad_70x70 sg13g2_IOPad* -offset {5.0 -70.0} + +remove_io_rows diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl new file mode 100644 index 0000000000..6e80d2f55e --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl @@ -0,0 +1,46 @@ +# standard cells +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} + +# macros +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground + +# padframe core power pins +add_global_connection -net {VDD} -pin_pattern {^vdd$} -power +add_global_connection -net {VSS} -pin_pattern {^vss$} -ground + +# padframe io power pins +add_global_connection -net {IOVDD} -pin_pattern {^iovdd$} -power +add_global_connection -net {IOVSS} -pin_pattern {^iovss$} -ground + +global_connect + +# core voltage domain +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +# stdcell grid +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \ + -followpins -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} \ + -extend_to_core_ring +add_pdn_connect -grid {grid} -layers {Metal1 Metal5} +add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} +add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} +add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} + +define_pdn_grid \ + -name {CORE_macro_grid_1} -voltage_domains {CORE} \ + -macro -cells {I2cDeviceCtrl} -grid_over_boundary +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1} +add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1} diff --git a/flow/designs/intel16/aes/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json similarity index 86% rename from flow/designs/intel16/aes/rules-base.json rename to flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index 2b852e947d..aad5ba3347 100644 --- a/flow/designs/intel16/aes/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 5582.34, + "value": 286097.29, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 8840, + "value": 39158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 12985, + "value": 965, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1159, + "value": 84, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1129, + "value": 84, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 135, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 330668, + "value": 39121, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 22, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 9167, + "value": 135775, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 565, + "value": 42, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/sealring.gds.gz b/flow/designs/ihp-sg13g2/i2c-gpio-expander/sealring.gds.gz new file mode 100644 index 0000000000..31bc865e10 Binary files /dev/null and b/flow/designs/ihp-sg13g2/i2c-gpio-expander/sealring.gds.gz differ diff --git a/flow/designs/ihp-sg13g2/ibex/autotuner.json b/flow/designs/ihp-sg13g2/ibex/autotuner.json index 53d12535be..5cecc6b809 100644 --- a/flow/designs/ihp-sg13g2/ibex/autotuner.json +++ b/flow/designs/ihp-sg13g2/ibex/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 15.0, + 10.0, 16.0 ], "step": 0 @@ -12,7 +12,7 @@ "type": "int", "minmax": [ 20, - 45 + 50 ], "step": 1 }, @@ -24,26 +24,18 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, @@ -88,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl" } diff --git a/flow/designs/ihp-sg13g2/ibex/config.mk b/flow/designs/ihp-sg13g2/ibex/config.mk index 8565d7e0b5..2ec1ac66f8 100644 --- a/flow/designs/ihp-sg13g2/ibex/config.mk +++ b/flow/designs/ihp-sg13g2/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = ihp-sg13g2 -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc index 318c8994f5..fed426995f 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint.sdc @@ -1,15 +1,15 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i -set clk_period 15.0 +set clk_period 10.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc +++ b/flow/designs/ihp-sg13g2/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/ihp-sg13g2/ibex/metadata-base-ok.json b/flow/designs/ihp-sg13g2/ibex/metadata-base-ok.json deleted file mode 100644 index e5bb9ec857..0000000000 --- a/flow/designs/ihp-sg13g2/ibex/metadata-base-ok.json +++ /dev/null @@ -1,330 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 15.0000" - ], - "cts__clock__skew__hold": 0.582143, - "cts__clock__skew__setup": 0.58214, - "cts__cpu__total": 58.91, - "cts__design__core__area": 598142, - "cts__design__die__area": 654691, - "cts__design__instance__area": 332607, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 332607, - "cts__design__instance__count": 21954, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 21954, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.556066, - "cts__design__instance__utilization__stdcell": 0.556066, - "cts__design__io": 264, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 480368.0, - "cts__power__internal__total": 0.0322878, - "cts__power__leakage__total": 5.04261e-06, - "cts__power__switching__total": 0.0137908, - "cts__power__total": 0.0460836, - "cts__route__wirelength__estimated": 1021250.0, - "cts__runtime__total": "0:59.24", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.754159, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 8, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.879018, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 5.32197, - "design__io__hpwl": 45573948, - "design__violations": 0, - "detailedplace__cpu__total": 25.19, - "detailedplace__design__core__area": 598142, - "detailedplace__design__die__area": 654691, - "detailedplace__design__instance__area": 289351, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 289351, - "detailedplace__design__instance__count": 20093, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 20093, - "detailedplace__design__instance__displacement__max": 24.84, - "detailedplace__design__instance__displacement__mean": 2.696, - "detailedplace__design__instance__displacement__total": 54176.5, - "detailedplace__design__instance__utilization": 0.48375, - "detailedplace__design__instance__utilization__stdcell": 0.48375, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 215692.0, - "detailedplace__power__internal__total": 0.024169, - "detailedplace__power__leakage__total": 3.7645e-06, - "detailedplace__power__switching__total": 0.0115633, - "detailedplace__power__total": 0.035736, - "detailedplace__route__wirelength__estimated": 993570, - "detailedplace__runtime__total": "0:25.34", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.918698, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 8, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.895901, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 6.13571, - "detailedroute__antenna__violating__nets": 94, - "detailedroute__antenna__violating__pins": 95, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 26748, - "detailedroute__route__drc_errors__iter:10": 26, - "detailedroute__route__drc_errors__iter:11": 6, - "detailedroute__route__drc_errors__iter:12": 3, - "detailedroute__route__drc_errors__iter:13": 3, - "detailedroute__route__drc_errors__iter:14": 0, - "detailedroute__route__drc_errors__iter:2": 14490, - "detailedroute__route__drc_errors__iter:3": 13798, - "detailedroute__route__drc_errors__iter:4": 2579, - "detailedroute__route__drc_errors__iter:5": 587, - "detailedroute__route__drc_errors__iter:6": 173, - "detailedroute__route__drc_errors__iter:7": 80, - "detailedroute__route__drc_errors__iter:8": 55, - "detailedroute__route__drc_errors__iter:9": 42, - "detailedroute__route__net": 23917, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 176438, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 176438, - "detailedroute__route__wirelength": 1203019, - "detailedroute__route__wirelength__iter:1": 1211751, - "detailedroute__route__wirelength__iter:10": 1203003, - "detailedroute__route__wirelength__iter:11": 1203015, - "detailedroute__route__wirelength__iter:12": 1203021, - "detailedroute__route__wirelength__iter:13": 1203021, - "detailedroute__route__wirelength__iter:14": 1203019, - "detailedroute__route__wirelength__iter:2": 1206512, - "detailedroute__route__wirelength__iter:3": 1205327, - "detailedroute__route__wirelength__iter:4": 1203571, - "detailedroute__route__wirelength__iter:5": 1203259, - "detailedroute__route__wirelength__iter:6": 1203118, - "detailedroute__route__wirelength__iter:7": 1203071, - "detailedroute__route__wirelength__iter:8": 1203005, - "detailedroute__route__wirelength__iter:9": 1203006, - "finish__clock__skew__hold": 0.709571, - "finish__clock__skew__setup": 0.709505, - "finish__cpu__total": 134.31, - "finish__design__core__area": 598142, - "finish__design__die__area": 654691, - "finish__design__instance__area": 569379, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 569379, - "finish__design__instance__count": 42802, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 42802, - "finish__design__instance__utilization": 0.951912, - "finish__design__instance__utilization__stdcell": 0.951912, - "finish__design__io": 264, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.19919, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00091077, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00129047, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00140785, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.19871, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00140785, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 704872.0, - "finish__power__internal__total": 0.0328213, - "finish__power__leakage__total": 1.91442e-05, - "finish__power__switching__total": 0.0297934, - "finish__power__total": 0.0626338, - "finish__runtime__total": "2:15.03", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.516758, - "finish__timing__drv__max_fanout": 63, - "finish__timing__drv__max_fanout_limit": 8, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.512753, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 2.271, - "finish__timing__wns_percent_delay": 23.342584, - "finish_merge__cpu__total": 3.88, - "finish_merge__mem__peak": 575956.0, - "finish_merge__runtime__total": "0:04.29", - "floorplan__cpu__total": 10.42, - "floorplan__design__core__area": 598142, - "floorplan__design__die__area": 654691, - "floorplan__design__instance__area": 271070, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 271070, - "floorplan__design__instance__count": 18068, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 18068, - "floorplan__design__instance__utilization": 0.453186, - "floorplan__design__instance__utilization__stdcell": 0.453186, - "floorplan__design__io": 264, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 4, - "floorplan__mem__peak": 181756.0, - "floorplan__power__internal__total": 0.0232222, - "floorplan__power__leakage__total": 3.43367e-06, - "floorplan__power__switching__total": 0.00971129, - "floorplan__power__total": 0.032937, - "floorplan__runtime__total": "0:10.55", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 6.58639, - "floorplan_io__cpu__total": 0.23, - "floorplan_io__mem__peak": 136340.0, - "floorplan_io__runtime__total": "0:00.31", - "floorplan_macro__cpu__total": 0.28, - "floorplan_macro__mem__peak": 135388.0, - "floorplan_macro__runtime__total": "0:00.32", - "floorplan_pdn__cpu__total": 0.43, - "floorplan_pdn__mem__peak": 139776.0, - "floorplan_pdn__runtime__total": "0:00.50", - "floorplan_tap__cpu__total": 0.21, - "floorplan_tap__mem__peak": 124928.0, - "floorplan_tap__runtime__total": "0:00.31", - "floorplan_tdms__cpu__total": 0.24, - "floorplan_tdms__mem__peak": 134936.0, - "floorplan_tdms__runtime__total": "0:00.32", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 475.52, - "globalplace__design__core__area": 598142, - "globalplace__design__die__area": 654691, - "globalplace__design__instance__area": 271070, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 271070, - "globalplace__design__instance__count": 18068, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 18068, - "globalplace__design__instance__utilization": 0.453186, - "globalplace__design__instance__utilization__stdcell": 0.453186, - "globalplace__design__io": 264, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 514440.0, - "globalplace__power__internal__total": 0.0232673, - "globalplace__power__leakage__total": 3.43367e-06, - "globalplace__power__switching__total": 0.0111056, - "globalplace__power__total": 0.0343763, - "globalplace__runtime__total": "1:12.17", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 6.43946, - "globalplace_io__cpu__total": 0.23, - "globalplace_io__mem__peak": 137728.0, - "globalplace_io__runtime__total": "0:00.34", - "globalplace_skip_io__cpu__total": 232.88, - "globalplace_skip_io__mem__peak": 165324.0, - "globalplace_skip_io__runtime__total": "0:07.75", - "globalroute__antenna__violating__nets": 111, - "globalroute__antenna__violating__pins": 111, - "globalroute__antenna_diodes_count": 1376, - "globalroute__clock__skew__hold": 0.571874, - "globalroute__clock__skew__setup": 0.571873, - "globalroute__cpu__total": 150.68, - "globalroute__design__core__area": 598142, - "globalroute__design__die__area": 654691, - "globalroute__design__instance__area": 340097, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 340097, - "globalroute__design__instance__count": 23330, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 23330, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.568588, - "globalroute__design__instance__utilization__stdcell": 0.568588, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 672200.0, - "globalroute__power__internal__total": 0.0325974, - "globalroute__power__leakage__total": 5.04824e-06, - "globalroute__power__switching__total": 0.0244748, - "globalroute__power__total": 0.0570773, - "globalroute__route__wirelength__estimated": 1021250.0, - "globalroute__runtime__total": "1:11.90", - "globalroute__timing__clock__slack": 3.744, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.593391, - "globalroute__timing__drv__max_fanout": 63, - "globalroute__timing__drv__max_fanout_limit": 8, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.58776, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 3.74354, - "placeopt__cpu__total": 20.72, - "placeopt__design__core__area": 598142, - "placeopt__design__die__area": 654691, - "placeopt__design__instance__area": 289351, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 289351, - "placeopt__design__instance__count": 20093, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 20093, - "placeopt__design__instance__utilization": 0.48375, - "placeopt__design__instance__utilization__stdcell": 0.48375, - "placeopt__design__io": 264, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 367392.0, - "placeopt__power__internal__total": 0.024167, - "placeopt__power__leakage__total": 3.7645e-06, - "placeopt__power__switching__total": 0.0115649, - "placeopt__power__total": 0.0357356, - "placeopt__runtime__total": "0:20.99", - "placeopt__timing__drv__floating__nets": 1, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.91885, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 8, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.895789, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 6.1301, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-09-27 18:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "ihp-sg13g2", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "bdc02c31-15ae-4260-bac1-f2a1d2d445d4", - "run__flow__variant": "base", - "synth__cpu__total": 98.84, - "synth__design__instance__area__stdcell": 271042.6698, - "synth__design__instance__count__stdcell": 18069.0, - "synth__mem__peak": 232556.0, - "synth__runtime__total": "1:39.19", - "total_time": "0:08:28.550000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/ibex/rules-base.json b/flow/designs/ihp-sg13g2/ibex/rules-base.json index af9547420f..1532af0351 100644 --- a/flow/designs/ihp-sg13g2/ibex/rules-base.json +++ b/flow/designs/ihp-sg13g2/ibex/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 305593, + "value": 365471, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -27,8 +27,12 @@ "value": 931, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 21, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 1439976, + "value": 1072557, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -36,19 +40,23 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 94, + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 36, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.17, "compare": ">=" }, "finish__design__instance__area": { - "value": 656767, + "value": 645302, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 27, + "value": 906, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -59,4 +67,4 @@ "value": -10.0, "compare": ">=" } -} +} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/jpeg/autotuner.json b/flow/designs/ihp-sg13g2/jpeg/autotuner.json index 7c83eac622..f1092d88e8 100644 --- a/flow/designs/ihp-sg13g2/jpeg/autotuner.json +++ b/flow/designs/ihp-sg13g2/jpeg/autotuner.json @@ -24,27 +24,19 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, @@ -88,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl" } diff --git a/flow/designs/ihp-sg13g2/jpeg/config.mk b/flow/designs/ihp-sg13g2/jpeg/config.mk index 79fe5ed4a4..24bb3852d5 100644 --- a/flow/designs/ihp-sg13g2/jpeg/config.mk +++ b/flow/designs/ihp-sg13g2/jpeg/config.mk @@ -6,7 +6,9 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/* export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export CORE_UTILIZATION = 55 -export PLACE_DENSITY_LB_ADDON = 0.20 +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.15 export TNS_END_PERCENT = 100 +export REMOVE_ABC_BUFFERS = 1 + diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc index 879a3ef4b4..0ca3cc5b3d 100644 --- a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc +++ b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 8.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/jpeg/metadata-base-ok.json b/flow/designs/ihp-sg13g2/jpeg/metadata-base-ok.json deleted file mode 100644 index 6d6d270e7a..0000000000 --- a/flow/designs/ihp-sg13g2/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,362 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 8.0000" - ], - "cts__clock__skew__hold": 0.436991, - "cts__clock__skew__hold__post_repair": 0.431704, - "cts__clock__skew__hold__pre_repair": 0.431704, - "cts__clock__skew__setup": 0.436991, - "cts__clock__skew__setup__post_repair": 0.431704, - "cts__clock__skew__setup__pre_repair": 0.431704, - "cts__cpu__total": 61.54, - "cts__design__core__area": 847080, - "cts__design__core__area__post_repair": 847080, - "cts__design__core__area__pre_repair": 847080, - "cts__design__die__area": 853379, - "cts__design__die__area__post_repair": 853379, - "cts__design__die__area__pre_repair": 853379, - "cts__design__instance__area": 497820, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 497725, - "cts__design__instance__area__pre_repair": 497725, - "cts__design__instance__area__stdcell": 497820, - "cts__design__instance__area__stdcell__post_repair": 497725, - "cts__design__instance__area__stdcell__pre_repair": 497725, - "cts__design__instance__count": 58335, - "cts__design__instance__count__hold_buffer": 6, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 58327, - "cts__design__instance__count__pre_repair": 58327, - "cts__design__instance__count__setup_buffer": 2, - "cts__design__instance__count__stdcell": 58335, - "cts__design__instance__count__stdcell__post_repair": 58327, - "cts__design__instance__count__stdcell__pre_repair": 58327, - "cts__design__instance__displacement__max": 4.56, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 33.788, - "cts__design__instance__utilization": 0.587689, - "cts__design__instance__utilization__post_repair": 0.587577, - "cts__design__instance__utilization__pre_repair": 0.587577, - "cts__design__instance__utilization__stdcell": 0.587689, - "cts__design__instance__utilization__stdcell__post_repair": 0.587577, - "cts__design__instance__utilization__stdcell__pre_repair": 0.587577, - "cts__design__io": 47, - "cts__design__io__post_repair": 47, - "cts__design__io__pre_repair": 47, - "cts__design__violations": 0, - "cts__mem__peak": 355548.0, - "cts__power__internal__total": 0.118885, - "cts__power__internal__total__post_repair": 0.118532, - "cts__power__internal__total__pre_repair": 0.118532, - "cts__power__leakage__total": 2.36109e-07, - "cts__power__leakage__total__post_repair": 2.36067e-07, - "cts__power__leakage__total__pre_repair": 2.36067e-07, - "cts__power__switching__total": 0.119304, - "cts__power__switching__total__post_repair": 0.118026, - "cts__power__switching__total__pre_repair": 0.118026, - "cts__power__total": 0.238189, - "cts__power__total__post_repair": 0.236558, - "cts__power__total__pre_repair": 0.236558, - "cts__route__wirelength__estimated": 981608, - "cts__runtime__total": "1:01.82", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 68, - "cts__timing__drv__hold_violation_count__pre_repair": 68, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.844242, - "cts__timing__drv__max_cap_limit__post_repair": 0.844242, - "cts__timing__drv__max_cap_limit__pre_repair": 0.844242, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.075835, - "cts__timing__drv__max_slew_limit__post_repair": 0.0804819, - "cts__timing__drv__max_slew_limit__pre_repair": 0.0804819, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 0, - "cts__timing__drv__setup_violation_count__pre_repair": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__tns__post_repair": 0, - "cts__timing__setup__tns__pre_repair": 0, - "cts__timing__setup__ws": 0.0412905, - "cts__timing__setup__ws__post_repair": 0.0116183, - "cts__timing__setup__ws__pre_repair": 0.0116183, - "cts_fill__cpu__total": 1.44, - "cts_fill__mem__peak": 208012.0, - "cts_fill__runtime__total": "0:01.61", - "design__io__hpwl": 10413497, - "detailedplace__cpu__total": 48.72, - "detailedplace__design__core__area": 847080, - "detailedplace__design__die__area": 853379, - "detailedplace__design__instance__area": 495780, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 495780, - "detailedplace__design__instance__count": 58068, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 58068, - "detailedplace__design__instance__displacement__max": 20.608, - "detailedplace__design__instance__displacement__mean": 2.297, - "detailedplace__design__instance__displacement__total": 133386, - "detailedplace__design__instance__utilization": 0.585282, - "detailedplace__design__instance__utilization__stdcell": 0.585282, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 304500.0, - "detailedplace__power__internal__total": 0.117701, - "detailedplace__power__leakage__total": 2.34875e-07, - "detailedplace__power__switching__total": 0.111016, - "detailedplace__power__total": 0.228717, - "detailedplace__route__wirelength__estimated": 992460, - "detailedplace__runtime__total": "0:48.96", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.844242, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0836072, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.0659481, - "detailedroute__cpu__total": 10939.31, - "detailedroute__mem__peak": 4667232.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 28894, - "detailedroute__route__drc_errors__iter:2": 12199, - "detailedroute__route__drc_errors__iter:3": 10677, - "detailedroute__route__drc_errors__iter:4": 1641, - "detailedroute__route__drc_errors__iter:5": 221, - "detailedroute__route__drc_errors__iter:6": 46, - "detailedroute__route__drc_errors__iter:7": 24, - "detailedroute__route__drc_errors__iter:8": 0, - "detailedroute__route__net": 59485, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 303589, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 303589, - "detailedroute__route__wirelength": 1130140, - "detailedroute__route__wirelength__iter:1": 1144184, - "detailedroute__route__wirelength__iter:2": 1133861, - "detailedroute__route__wirelength__iter:3": 1130921, - "detailedroute__route__wirelength__iter:4": 1130286, - "detailedroute__route__wirelength__iter:5": 1130124, - "detailedroute__route__wirelength__iter:6": 1130125, - "detailedroute__route__wirelength__iter:7": 1130134, - "detailedroute__route__wirelength__iter:8": 1130140, - "detailedroute__runtime__total": "14:18.83", - "finish__clock__skew__hold": 0.476837, - "finish__clock__skew__setup": 0.476837, - "finish__cpu__total": 95.19, - "finish__design__core__area": 847080, - "finish__design__die__area": 853379, - "finish__design__instance__area": 497820, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 497820, - "finish__design__instance__count": 58335, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 58335, - "finish__design__instance__utilization": 0.587689, - "finish__design__instance__utilization__stdcell": 0.587689, - "finish__design__io": 47, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.0121449, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0119947, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.018054, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0179638, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.78195, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0179638, - "finish__mem__peak": 1639448.0, - "finish__power__internal__total": 0.119678, - "finish__power__leakage__total": 2.36109e-07, - "finish__power__switching__total": 0.125283, - "finish__power__total": 0.244961, - "finish__runtime__total": "1:35.65", - "finish__timing__drv__hold_violation_count": 6, - "finish__timing__drv__max_cap": 2, - "finish__timing__drv__max_cap_limit": -0.044488, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 77, - "finish__timing__drv__max_slew_limit": -0.13451, - "finish__timing__drv__setup_violation_count": 16, - "finish__timing__setup__tns": -1.05202, - "finish__timing__setup__ws": -0.22068, - "finish__timing__wns_percent_delay": -2.209762, - "finish_merge__cpu__total": 10.53, - "finish_merge__mem__peak": 626704.0, - "finish_merge__runtime__total": "0:11.72", - "floorplan__cpu__total": 12.63, - "floorplan__design__core__area": 847080, - "floorplan__design__die__area": 853379, - "floorplan__design__instance__area": 460578, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 460578, - "floorplan__design__instance__count": 46629, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 46629, - "floorplan__design__instance__utilization": 0.543724, - "floorplan__design__instance__utilization__stdcell": 0.543724, - "floorplan__design__io": 47, - "floorplan__mem__peak": 255800.0, - "floorplan__power__internal__total": 0.110307, - "floorplan__power__leakage__total": 2.31445e-07, - "floorplan__power__switching__total": 0.0760191, - "floorplan__power__total": 0.186327, - "floorplan__runtime__total": "0:12.98", - "floorplan__timing__setup__tns": -59926.4, - "floorplan__timing__setup__ws": -56.6505, - "floorplan_io__cpu__total": 0.9, - "floorplan_io__mem__peak": 154864.0, - "floorplan_io__runtime__total": "0:01.02", - "floorplan_macro__cpu__total": 0.94, - "floorplan_macro__mem__peak": 153276.0, - "floorplan_macro__runtime__total": "0:01.05", - "floorplan_pdn__cpu__total": 2.53, - "floorplan_pdn__mem__peak": 193556.0, - "floorplan_pdn__runtime__total": "0:02.68", - "floorplan_tap__cpu__total": 0.84, - "floorplan_tap__mem__peak": 129116.0, - "floorplan_tap__runtime__total": "0:00.94", - "floorplan_tdms__cpu__total": 0.94, - "floorplan_tdms__mem__peak": 153412.0, - "floorplan_tdms__runtime__total": "0:01.05", - "globalplace__cpu__total": 164.63, - "globalplace__design__core__area": 847080, - "globalplace__design__die__area": 853379, - "globalplace__design__instance__area": 474616, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 474616, - "globalplace__design__instance__count": 57849, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 57849, - "globalplace__design__instance__utilization": 0.560297, - "globalplace__design__instance__utilization__stdcell": 0.560297, - "globalplace__design__io": 47, - "globalplace__mem__peak": 530928.0, - "globalplace__power__internal__total": 0.120439, - "globalplace__power__leakage__total": 2.31445e-07, - "globalplace__power__switching__total": 0.103807, - "globalplace__power__total": 0.224246, - "globalplace__runtime__total": "2:45.07", - "globalplace__timing__setup__tns": -118275, - "globalplace__timing__setup__ws": -132.238, - "globalplace_io__cpu__total": 0.99, - "globalplace_io__mem__peak": 167448.0, - "globalplace_io__runtime__total": "0:01.11", - "globalplace_skip_io__cpu__total": 21.0, - "globalplace_skip_io__mem__peak": 234300.0, - "globalplace_skip_io__runtime__total": "0:21.22", - "globalroute__antenna__violating__nets": 15, - "globalroute__antenna__violating__pins": 21, - "globalroute__clock__skew__hold": 0.49546, - "globalroute__clock__skew__setup": 0.49546, - "globalroute__cpu__total": 34.56, - "globalroute__design__core__area": 847080, - "globalroute__design__die__area": 853379, - "globalroute__design__instance__area": 497820, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 497820, - "globalroute__design__instance__count": 58335, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 58335, - "globalroute__design__instance__utilization": 0.587689, - "globalroute__design__instance__utilization__stdcell": 0.587689, - "globalroute__design__io": 47, - "globalroute__mem__peak": 750460.0, - "globalroute__power__internal__total": 0.126032, - "globalroute__power__leakage__total": 2.36109e-07, - "globalroute__power__switching__total": 0.149998, - "globalroute__power__total": 0.276031, - "globalroute__runtime__total": "0:35.06", - "globalroute__timing__clock__slack": -0.503, - "globalroute__timing__drv__hold_violation_count": 5, - "globalroute__timing__drv__max_cap": 2, - "globalroute__timing__drv__max_cap_limit": -0.0505455, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 77, - "globalroute__timing__drv__max_slew_limit": -0.0660371, - "globalroute__timing__drv__setup_violation_count": 83, - "globalroute__timing__setup__tns": -14.1177, - "globalroute__timing__setup__ws": -0.502554, - "placeopt__cpu__total": 36.33, - "placeopt__design__core__area": 847080, - "placeopt__design__core__area__pre_opt": 847080, - "placeopt__design__die__area": 853379, - "placeopt__design__die__area__pre_opt": 853379, - "placeopt__design__instance__area": 495780, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 474616, - "placeopt__design__instance__area__stdcell": 495780, - "placeopt__design__instance__area__stdcell__pre_opt": 474616, - "placeopt__design__instance__count": 58068, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 57849, - "placeopt__design__instance__count__stdcell": 58068, - "placeopt__design__instance__count__stdcell__pre_opt": 57849, - "placeopt__design__instance__utilization": 0.585282, - "placeopt__design__instance__utilization__pre_opt": 0.560297, - "placeopt__design__instance__utilization__stdcell": 0.585282, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.560297, - "placeopt__design__io": 47, - "placeopt__design__io__pre_opt": 47, - "placeopt__mem__peak": 305896.0, - "placeopt__power__internal__total": 0.117256, - "placeopt__power__internal__total__pre_opt": 0.120439, - "placeopt__power__leakage__total": 2.34875e-07, - "placeopt__power__leakage__total__pre_opt": 2.31445e-07, - "placeopt__power__switching__total": 0.108142, - "placeopt__power__switching__total__pre_opt": 0.103807, - "placeopt__power__total": 0.225398, - "placeopt__power__total__pre_opt": 0.224246, - "placeopt__runtime__total": "0:36.59", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.836858, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0862412, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__tns__pre_opt": -118275, - "placeopt__timing__setup__ws": 0.0527356, - "placeopt__timing__setup__ws__pre_opt": -132.238, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2023-07-27 15:04", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9523-g486364f18", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "ec589188ee778f884d4a18de3c3ba924914eac86", - "run__flow__scripts_commit": "ec589188ee778f884d4a18de3c3ba924914eac86", - "run__flow__uuid": "c221e426-dc0c-4145-8a37-1bed198b1bfd", - "run__flow__variant": "base", - "synth__cpu__total": 270.45, - "synth__design__instance__area__stdcell": 467326.9536, - "synth__design__instance__count__stdcell": 48376.0, - "synth__mem__peak": 830820.0, - "synth__runtime__total": "4:34.48", - "total_time": "0:27:11.840000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/jpeg/rules-base.json b/flow/designs/ihp-sg13g2/jpeg/rules-base.json index df944fc741..115f3ccc12 100644 --- a/flow/designs/ihp-sg13g2/jpeg/rules-base.json +++ b/flow/designs/ihp-sg13g2/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 537426, + "value": 1507968.61, "compare": "<=" }, "constraints__clocks__count": { @@ -8,29 +8,17 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 570147, + "value": 1043533, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 66775, + "value": 86736, "compare": "<=" }, "detailedplace__design__violations": { "value": 0, "compare": "==" }, - "cts__timing__setup__ws": { - "value": -1.06, - "compare": ">=" - }, - "cts__timing__setup__ws__pre_repair": { - "value": -1.02, - "compare": ">=" - }, - "cts__timing__setup__ws__post_repair": { - "value": -1.02, - "compare": ">=" - }, "cts__design__instance__count__setup_buffer": { "value": 2903, "compare": "<=" @@ -39,44 +27,36 @@ "value": 2903, "compare": "<=" }, - "globalroute__timing__clock__slack": { - "value": -0.81, - "compare": ">=" - }, - "globalroute__timing__setup__ws": { - "value": -0.81, - "compare": ">=" + "globalroute__antenna_diodes_count": { + "value": 12, + "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1294864, + "value": 3140459, "compare": "<=" }, "detailedroute__route__drc_errors": { "value": 0, "compare": "<=" }, - "finish__timing__setup__ws": { - "value": -0.5, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 572438, + "detailedroute__antenna__violating__nets": { + "value": 0, "compare": "<=" }, - "finish__timing__drv__max_slew_limit": { - "value": -0.27, - "compare": ">=" + "detailedroute__antenna_diodes_count": { + "value": 134, + "compare": "<=" }, - "finish__timing__drv__max_fanout_limit": { - "value": -0.2, + "finish__timing__setup__ws": { + "value": 0.0, "compare": ">=" }, - "finish__timing__drv__max_cap_limit": { - "value": -0.23, - "compare": ">=" + "finish__design__instance__area": { + "value": 2605152, + "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 29, + "value": 3771, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc index 84227b787b..5b0a6f1b4e 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc +++ b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 10.0 +set clk_period 6.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json b/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json deleted file mode 100644 index 567c675914..0000000000 --- a/flow/designs/ihp-sg13g2/riscv32i/metadata-base-ok.json +++ /dev/null @@ -1,356 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 10.0000" - ], - "cts__clock__skew__hold": 0.204393, - "cts__clock__skew__setup": 0.204393, - "cts__cpu__total": 35.59, - "cts__design__core__area": 387723, - "cts__design__die__area": 433998, - "cts__design__instance__area": 156648, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 156648, - "cts__design__instance__count": 10822, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 10822, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.404021, - "cts__design__instance__utilization__stdcell": 0.404021, - "cts__design__io": 165, - "cts__design__rows": 164, - "cts__design__rows:CoreSite": 164, - "cts__design__sites": 213692, - "cts__design__sites:CoreSite": 213692, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 443880.0, - "cts__power__internal__total": 0.0090779, - "cts__power__leakage__total": 2.06259e-06, - "cts__power__switching__total": 0.00198582, - "cts__power__total": 0.0110658, - "cts__route__wirelength__estimated": 603393, - "cts__runtime__total": "0:36.03", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.917789, - "cts__timing__drv__max_fanout": 1, - "cts__timing__drv__max_fanout_limit": 8, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.751527, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 4.20953, - "design__io__hpwl": 29503565, - "design__violations": 0, - "detailedplace__cpu__total": 16.89, - "detailedplace__design__core__area": 387723, - "detailedplace__design__die__area": 433998, - "detailedplace__design__instance__area": 151417, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 151417, - "detailedplace__design__instance__count": 10459, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 10459, - "detailedplace__design__instance__displacement__max": 20.46, - "detailedplace__design__instance__displacement__mean": 3.125, - "detailedplace__design__instance__displacement__total": 32693.3, - "detailedplace__design__instance__utilization": 0.390529, - "detailedplace__design__instance__utilization__stdcell": 0.390529, - "detailedplace__design__io": 165, - "detailedplace__design__rows": 164, - "detailedplace__design__rows:CoreSite": 164, - "detailedplace__design__sites": 213692, - "detailedplace__design__sites:CoreSite": 213692, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 185392.0, - "detailedplace__power__internal__total": 0.0078505, - "detailedplace__power__leakage__total": 1.93593e-06, - "detailedplace__power__switching__total": 0.00105825, - "detailedplace__power__total": 0.00891068, - "detailedplace__route__wirelength__estimated": 609310, - "detailedplace__runtime__total": "0:17.04", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.91789, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 8, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.91171, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 5.27414, - "detailedroute__antenna__violating__nets": 35, - "detailedroute__antenna__violating__pins": 35, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 13045, - "detailedroute__route__drc_errors__iter:2": 7106, - "detailedroute__route__drc_errors__iter:3": 6568, - "detailedroute__route__drc_errors__iter:4": 926, - "detailedroute__route__drc_errors__iter:5": 125, - "detailedroute__route__drc_errors__iter:6": 38, - "detailedroute__route__drc_errors__iter:7": 12, - "detailedroute__route__drc_errors__iter:8": 0, - "detailedroute__route__net": 11812, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 91094, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 91094, - "detailedroute__route__wirelength": 712725, - "detailedroute__route__wirelength__iter:1": 717116, - "detailedroute__route__wirelength__iter:2": 714354, - "detailedroute__route__wirelength__iter:3": 713868, - "detailedroute__route__wirelength__iter:4": 712876, - "detailedroute__route__wirelength__iter:5": 712757, - "detailedroute__route__wirelength__iter:6": 712733, - "detailedroute__route__wirelength__iter:7": 712730, - "detailedroute__route__wirelength__iter:8": 712725, - "finish__clock__skew__hold": 0.187635, - "finish__clock__skew__setup": 0.187635, - "finish__cpu__total": 74.62, - "finish__design__core__area": 387723, - "finish__design__die__area": 433998, - "finish__design__instance__area": 371319, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 371319, - "finish__design__instance__count": 29017, - "finish__design__instance__count__class:antenna_cell": 677, - "finish__design__instance__count__class:buffer": 1184, - "finish__design__instance__count__class:clock_buffer": 285, - "finish__design__instance__count__class:clock_inverter": 78, - "finish__design__instance__count__class:fill_cell": 6156, - "finish__design__instance__count__class:inverter": 371, - "finish__design__instance__count__class:multi_input_combinational_cell": 6982, - "finish__design__instance__count__class:other": 17518, - "finish__design__instance__count__class:sequential_cell": 1056, - "finish__design__instance__count__class:timing_repair_buffer": 866, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 29017, - "finish__design__instance__utilization": 0.957691, - "finish__design__instance__utilization__stdcell": 0.957691, - "finish__design__io": 165, - "finish__design__rows": 164, - "finish__design__rows:CoreSite": 164, - "finish__design__sites": 213692, - "finish__design__sites:CoreSite": 213692, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.19974, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000291865, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.000355652, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.000422252, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.19964, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.000422252, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 468760.0, - "finish__power__internal__total": 0.00921527, - "finish__power__leakage__total": 1.50904e-05, - "finish__power__switching__total": 0.00342931, - "finish__power__total": 0.0126597, - "finish__runtime__total": "1:15.22", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.456466, - "finish__timing__drv__max_fanout": 31, - "finish__timing__drv__max_fanout_limit": 8, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.634221, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 2.4721, - "finish__timing__wns_percent_delay": 44.720418, - "finish_merge__cpu__total": 3.09, - "finish_merge__mem__peak": 495056.0, - "finish_merge__runtime__total": "0:03.42", - "floorplan__cpu__total": 8.24, - "floorplan__design__core__area": 387723, - "floorplan__design__die__area": 433998, - "floorplan__design__instance__area": 137062, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 137062, - "floorplan__design__instance__count": 8570, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 8570, - "floorplan__design__instance__utilization": 0.353504, - "floorplan__design__instance__utilization__stdcell": 0.353504, - "floorplan__design__io": 165, - "floorplan__design__rows": 164, - "floorplan__design__rows:CoreSite": 164, - "floorplan__design__sites": 213692, - "floorplan__design__sites:CoreSite": 213692, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 145392.0, - "floorplan__power__internal__total": 0.00776786, - "floorplan__power__leakage__total": 1.75502e-06, - "floorplan__power__switching__total": 0.000928288, - "floorplan__power__total": 0.0086979, - "floorplan__runtime__total": "0:08.32", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 5.48646, - "floorplan_io__cpu__total": 0.32, - "floorplan_io__mem__peak": 121772.0, - "floorplan_io__runtime__total": "0:00.39", - "floorplan_macro__cpu__total": 0.35, - "floorplan_macro__mem__peak": 120900.0, - "floorplan_macro__runtime__total": "0:00.40", - "floorplan_pdn__cpu__total": 0.43, - "floorplan_pdn__mem__peak": 125012.0, - "floorplan_pdn__runtime__total": "0:00.52", - "floorplan_tap__cpu__total": 0.31, - "floorplan_tap__mem__peak": 115292.0, - "floorplan_tap__runtime__total": "0:00.37", - "floorplan_tdms__cpu__total": 0.19, - "floorplan_tdms__mem__peak": 99728.0, - "floorplan_tdms__runtime__total": "0:00.25", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 856.81, - "globalplace__design__core__area": 387723, - "globalplace__design__die__area": 433998, - "globalplace__design__instance__area": 137062, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 137062, - "globalplace__design__instance__count": 8570, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 8570, - "globalplace__design__instance__utilization": 0.353504, - "globalplace__design__instance__utilization__stdcell": 0.353504, - "globalplace__design__io": 165, - "globalplace__design__rows": 164, - "globalplace__design__rows:CoreSite": 164, - "globalplace__design__sites": 213692, - "globalplace__design__sites:CoreSite": 213692, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 428704.0, - "globalplace__power__internal__total": 0.00778271, - "globalplace__power__leakage__total": 1.75502e-06, - "globalplace__power__switching__total": 0.00102787, - "globalplace__power__total": 0.00881234, - "globalplace__runtime__total": "1:03.70", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 5.40602, - "globalplace_io__cpu__total": 0.31, - "globalplace_io__mem__peak": 122544.0, - "globalplace_io__runtime__total": "0:00.42", - "globalplace_skip_io__cpu__total": 126.95, - "globalplace_skip_io__mem__peak": 137568.0, - "globalplace_skip_io__runtime__total": "0:04.52", - "globalroute__antenna__violating__nets": 24, - "globalroute__antenna__violating__pins": 25, - "globalroute__antenna_diodes_count": 677, - "globalroute__clock__skew__hold": 0.172073, - "globalroute__clock__skew__setup": 0.172073, - "globalroute__cpu__total": 86.01, - "globalroute__design__core__area": 387723, - "globalroute__design__die__area": 433998, - "globalroute__design__instance__area": 160333, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 160333, - "globalroute__design__instance__count": 11499, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 11499, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.413525, - "globalroute__design__instance__utilization__stdcell": 0.413525, - "globalroute__design__io": 165, - "globalroute__design__rows": 164, - "globalroute__design__rows:CoreSite": 164, - "globalroute__design__sites": 213692, - "globalroute__design__sites:CoreSite": 213692, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 533916.0, - "globalroute__power__internal__total": 0.00916959, - "globalroute__power__leakage__total": 2.06551e-06, - "globalroute__power__switching__total": 0.00266551, - "globalroute__power__total": 0.0118372, - "globalroute__route__wirelength__estimated": 603393, - "globalroute__runtime__total": "0:42.85", - "globalroute__timing__clock__slack": 3.753, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.515794, - "globalroute__timing__drv__max_fanout": 31, - "globalroute__timing__drv__max_fanout_limit": 8, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.75803, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 3.75345, - "placeopt__cpu__total": 14.15, - "placeopt__design__core__area": 387723, - "placeopt__design__die__area": 433998, - "placeopt__design__instance__area": 151417, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 151417, - "placeopt__design__instance__count": 10459, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 10459, - "placeopt__design__instance__utilization": 0.390529, - "placeopt__design__instance__utilization__stdcell": 0.390529, - "placeopt__design__io": 165, - "placeopt__design__rows": 164, - "placeopt__design__rows:CoreSite": 164, - "placeopt__design__sites": 213692, - "placeopt__design__sites:CoreSite": 213692, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 321016.0, - "placeopt__power__internal__total": 0.00784952, - "placeopt__power__leakage__total": 1.93593e-06, - "placeopt__power__switching__total": 0.00105681, - "placeopt__power__total": 0.00890826, - "placeopt__runtime__total": "0:14.46", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.915714, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 8, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.911993, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 5.26479, - "run__flow__design": "riscv32i", - "run__flow__generate_date": "2024-10-28 13:44", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16787-gcd519bb5e", - "run__flow__platform": "ihp-sg13g2", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "974b9e27-10ad-4879-ac78-536379f03117", - "run__flow__variant": "base", - "synth__cpu__total": 35.13, - "synth__design__instance__area__stdcell": 137047.3398, - "synth__design__instance__count__stdcell": 8570.0, - "synth__mem__peak": 60160.0, - "synth__runtime__total": "0:35.31", - "total_time": "0:05:03.220000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json index bad6e72d88..1559d3db81 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/rules-base.json +++ b/flow/designs/ihp-sg13g2/riscv32i/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 152901, + "value": 170435, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,11 +28,11 @@ "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 779, + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 819634, + "value": 511850, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,7 +40,11 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 46, + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 12, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 10, + "value": 478, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/ihp-sg13g2/spi/autotuner.json b/flow/designs/ihp-sg13g2/spi/autotuner.json index c657438ba8..f3847e413b 100644 --- a/flow/designs/ihp-sg13g2/spi/autotuner.json +++ b/flow/designs/ihp-sg13g2/spi/autotuner.json @@ -3,16 +3,16 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 1.0, - 4.3647 + 0.8, + 1.1 ], "step": 0 }, "CORE_UTILIZATION": { "type": "int", "minmax": [ - 5, - 30 + 20, + 50 ], "step": 1 }, @@ -20,31 +20,23 @@ "type": "float", "minmax": [ 0.5, - 2.0 - ], - "step": 0 - }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 + 1.5 ], "step": 0 }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -60,7 +52,7 @@ "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, @@ -88,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl" } diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc index e74f093cee..956369e4b8 100644 --- a/flow/designs/ihp-sg13g2/spi/constraint.sdc +++ b/flow/designs/ihp-sg13g2/spi/constraint.sdc @@ -1,15 +1,15 @@ current_design spi -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 10.4 +set clk_period 0.9 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/ihp-sg13g2/spi/metadata-base-ok.json b/flow/designs/ihp-sg13g2/spi/metadata-base-ok.json deleted file mode 100644 index bea7eb0571..0000000000 --- a/flow/designs/ihp-sg13g2/spi/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 10.4000" - ], - "cts__clock__skew__hold": 0.000939693, - "cts__clock__skew__setup": 0.000939693, - "cts__cpu__total": 0.9, - "cts__design__core__area": 9298.8, - "cts__design__die__area": 17455.7, - "cts__design__instance__area": 2382.31, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 2382.31, - "cts__design__instance__count": 168, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 168, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.256195, - "cts__design__instance__utilization__stdcell": 0.256195, - "cts__design__io": 23, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 391132.0, - "cts__power__internal__total": 0.000133779, - "cts__power__leakage__total": 2.73992e-08, - "cts__power__switching__total": 2.06849e-05, - "cts__power__total": 0.000154492, - "cts__route__wirelength__estimated": 2926.11, - "cts__runtime__total": "0:01.12", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.917966, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 8, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.921639, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 7.75541, - "design__io__hpwl": 1245765, - "design__violations": 0, - "detailedplace__cpu__total": 0.18, - "detailedplace__design__core__area": 9298.8, - "detailedplace__design__die__area": 17455.7, - "detailedplace__design__instance__area": 2329.69, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 2329.69, - "detailedplace__design__instance__count": 160, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 160, - "detailedplace__design__instance__displacement__max": 13.976, - "detailedplace__design__instance__displacement__mean": 3.968, - "detailedplace__design__instance__displacement__total": 635.017, - "detailedplace__design__instance__utilization": 0.250537, - "detailedplace__design__instance__utilization__stdcell": 0.250537, - "detailedplace__design__io": 23, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 121280.0, - "detailedplace__power__internal__total": 0.000130222, - "detailedplace__power__leakage__total": 2.66586e-08, - "detailedplace__power__switching__total": 5.40232e-06, - "detailedplace__power__total": 0.000135651, - "detailedplace__route__wirelength__estimated": 2879.41, - "detailedplace__runtime__total": "0:00.22", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.933678, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 8, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.921591, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 7.78096, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 16.41, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__mem__peak": 659180.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 68, - "detailedroute__route__drc_errors__iter:2": 5, - "detailedroute__route__drc_errors__iter:3": 0, - "detailedroute__route__net": 203, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 793, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 793, - "detailedroute__route__wirelength": 3267, - "detailedroute__route__wirelength__iter:1": 3263, - "detailedroute__route__wirelength__iter:2": 3276, - "detailedroute__route__wirelength__iter:3": 3267, - "detailedroute__runtime__total": "0:06.41", - "fillcell__cpu__total": 0.1, - "fillcell__mem__peak": 119344.0, - "fillcell__runtime__total": "0:00.15", - "finish__clock__skew__hold": 0.0088104, - "finish__clock__skew__setup": 0.0088104, - "finish__cpu__total": 1.07, - "finish__design__core__area": 9298.8, - "finish__design__die__area": 17455.7, - "finish__design__instance__area": 9046.6, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 9046.6, - "finish__design__instance__count": 706, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 706, - "finish__design__instance__utilization": 0.972878, - "finish__design__instance__utilization__stdcell": 0.972878, - "finish__design__io": 23, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.19997, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 6.33742e-05, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 3.83726e-05, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 7.43359e-05, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.19996, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 7.43359e-05, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 262076.0, - "finish__power__internal__total": 0.000134196, - "finish__power__leakage__total": 4.40801e-07, - "finish__power__switching__total": 2.67202e-05, - "finish__power__total": 0.000161357, - "finish__runtime__total": "0:01.18", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.900335, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 8, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.898243, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 7.70581, - "finish__timing__wns_percent_delay": 1254.60762, - "finish_merge__cpu__total": 1.18, - "finish_merge__mem__peak": 392112.0, - "finish_merge__runtime__total": "0:01.33", - "floorplan__cpu__total": 0.12, - "floorplan__design__core__area": 9298.8, - "floorplan__design__die__area": 17455.7, - "floorplan__design__instance__area": 1965, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 1965, - "floorplan__design__instance__count": 111, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 111, - "floorplan__design__instance__utilization": 0.211317, - "floorplan__design__instance__utilization__stdcell": 0.211317, - "floorplan__design__io": 23, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 120800.0, - "floorplan__power__internal__total": 0.000129091, - "floorplan__power__leakage__total": 2.21273e-08, - "floorplan__power__switching__total": 4.80816e-06, - "floorplan__power__total": 0.000133921, - "floorplan__runtime__total": "0:00.18", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 7.90016, - "floorplan_io__cpu__total": 0.11, - "floorplan_io__mem__peak": 118640.0, - "floorplan_io__runtime__total": "0:00.15", - "floorplan_macro__cpu__total": 0.1, - "floorplan_macro__mem__peak": 117836.0, - "floorplan_macro__runtime__total": "0:00.15", - "floorplan_pdn__cpu__total": 0.09, - "floorplan_pdn__mem__peak": 119636.0, - "floorplan_pdn__runtime__total": "0:00.15", - "floorplan_tap__cpu__total": 0.11, - "floorplan_tap__mem__peak": 117612.0, - "floorplan_tap__runtime__total": "0:00.15", - "floorplan_tdms__cpu__total": 0.1, - "floorplan_tdms__mem__peak": 118096.0, - "floorplan_tdms__runtime__total": "0:00.15", - "flow__errors__count": 0, - "flow__warnings__count": 12, - "globalplace__cpu__total": 5.4, - "globalplace__design__core__area": 9298.8, - "globalplace__design__die__area": 17455.7, - "globalplace__design__instance__area": 1965, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 1965, - "globalplace__design__instance__count": 111, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 111, - "globalplace__design__instance__utilization": 0.211317, - "globalplace__design__instance__utilization__stdcell": 0.211317, - "globalplace__design__io": 23, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 306336.0, - "globalplace__power__internal__total": 0.000129162, - "globalplace__power__leakage__total": 2.21273e-08, - "globalplace__power__switching__total": 4.96053e-06, - "globalplace__power__total": 0.000134144, - "globalplace__runtime__total": "0:00.54", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 7.89142, - "globalplace_io__cpu__total": 0.11, - "globalplace_io__mem__peak": 117904.0, - "globalplace_io__runtime__total": "0:00.15", - "globalplace_skip_io__cpu__total": 3.53, - "globalplace_skip_io__mem__peak": 119632.0, - "globalplace_skip_io__runtime__total": "0:00.25", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.00398664, - "globalroute__clock__skew__setup": 0.00398664, - "globalroute__cpu__total": 0.87, - "globalroute__design__core__area": 9298.8, - "globalroute__design__die__area": 17455.7, - "globalroute__design__instance__area": 2382.31, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 2382.31, - "globalroute__design__instance__count": 168, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 168, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.256195, - "globalroute__design__instance__utilization__stdcell": 0.256195, - "globalroute__design__io": 23, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 353732.0, - "globalroute__power__internal__total": 0.000133913, - "globalroute__power__leakage__total": 2.73992e-08, - "globalroute__power__switching__total": 2.43654e-05, - "globalroute__power__total": 0.000158306, - "globalroute__route__wirelength__estimated": 2926.11, - "globalroute__runtime__total": "0:00.46", - "globalroute__timing__clock__slack": 7.712, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.908121, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 8, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.909378, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 7.71189, - "placeopt__cpu__total": 0.17, - "placeopt__design__core__area": 9298.8, - "placeopt__design__die__area": 17455.7, - "placeopt__design__instance__area": 2329.69, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 2329.69, - "placeopt__design__instance__count": 160, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 160, - "placeopt__design__instance__utilization": 0.250537, - "placeopt__design__instance__utilization__stdcell": 0.250537, - "placeopt__design__io": 23, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 304472.0, - "placeopt__power__internal__total": 0.000130203, - "placeopt__power__leakage__total": 2.66586e-08, - "placeopt__power__switching__total": 5.35477e-06, - "placeopt__power__total": 0.000135584, - "placeopt__runtime__total": "0:00.36", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.934224, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 8, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.922926, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 7.78543, - "run__flow__design": "spi", - "run__flow__generate_date": "2024-08-27 21:57", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15322-gdf361ea88", - "run__flow__platform": "ihp-sg13g2", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1uA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1pW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__scripts_commit": "53863581bcebf441b313abb65c15059fd79752b8", - "run__flow__uuid": "cbbaa4e4-7e81-4f68-af22-aa77c9f4379b", - "run__flow__variant": "base", - "synth__cpu__total": 0.28, - "synth__design__instance__area__stdcell": 1964.655, - "synth__design__instance__count__stdcell": 111.0, - "synth__mem__peak": 30208.0, - "synth__runtime__total": "0:00.34", - "total_time": "0:00:13.440000" -} \ No newline at end of file diff --git a/flow/designs/ihp-sg13g2/spi/rules-base.json b/flow/designs/ihp-sg13g2/spi/rules-base.json index d6f344c0be..b04f8924a3 100644 --- a/flow/designs/ihp-sg13g2/spi/rules-base.json +++ b/flow/designs/ihp-sg13g2/spi/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2259.36, + "value": 2244.75, "compare": "<=" }, "constraints__clocks__count": { @@ -27,8 +27,12 @@ "value": 13, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 3437, + "value": 4553, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -39,16 +43,20 @@ "value": 0, "compare": "<=" }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.07, "compare": ">=" }, "finish__design__instance__area": { - "value": 10387, + "value": 10376, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 7, + "value": 14, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -56,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.0, + "value": -13.57, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/intel16/aes/config.mk b/flow/designs/intel16/aes/config.mk deleted file mode 100644 index 9549f496bb..0000000000 --- a/flow/designs/intel16/aes/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = aes -export DESIGN_NAME = aes_cipher_top -export PLATFORM = intel16 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -# These values must be multiples of placement site -# x=0.19 y=1.4 -export DIE_AREA = 0 0 250 250 -export CORE_AREA = 1.26 1.89 248 248 - - -export PLACE_DENSITY = uniform -#export SKIP_PIN_SWAP = 1 -export SKIP_GATE_CLONING = 1 diff --git a/flow/designs/intel16/aes/constraint.sdc b/flow/designs/intel16/aes/constraint.sdc deleted file mode 100644 index b90ac2d10e..0000000000 --- a/flow/designs/intel16/aes/constraint.sdc +++ /dev/null @@ -1,8 +0,0 @@ -set clk_name clk -set clk_period 2100 -# -create_clock -name $clk_name -period $clk_period [get_ports clk] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] - diff --git a/flow/designs/intel16/aes/metadata-base-ok.json b/flow/designs/intel16/aes/metadata-base-ok.json deleted file mode 100644 index 901e4c551c..0000000000 --- a/flow/designs/intel16/aes/metadata-base-ok.json +++ /dev/null @@ -1,319 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 2100.0000" - ], - "cts__clock__skew__hold": 92.824, - "cts__clock__skew__setup": 83.1635, - "cts__cpu__total": 12.6, - "cts__design__core__area": 60607.3, - "cts__design__die__area": 62500, - "cts__design__instance__area": 8591.12, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 8591.12, - "cts__design__instance__count": 12976, - "cts__design__instance__count__hold_buffer": 19, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 12976, - "cts__design__instance__displacement__max": 1.62, - "cts__design__instance__displacement__mean": 0.0015, - "cts__design__instance__displacement__total": 25.582, - "cts__design__instance__utilization": 0.141751, - "cts__design__instance__utilization__stdcell": 0.141751, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1503812.0, - "cts__power__internal__total": 0.0142694, - "cts__power__leakage__total": 1.24018e-08, - "cts__power__switching__total": 0.0205312, - "cts__power__total": 0.0348006, - "cts__route__wirelength__estimated": 225853, - "cts__runtime__total": "0:13.74", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.910289, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.763937, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 6.77725, - "design__io__hpwl": 62736584, - "design__violations": 0, - "detailedplace__cpu__total": 12.62, - "detailedplace__design__core__area": 60607.3, - "detailedplace__design__die__area": 62500, - "detailedplace__design__instance__area": 8402.86, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 8402.86, - "detailedplace__design__instance__count": 12798, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 12798, - "detailedplace__design__instance__displacement__max": 2.687, - "detailedplace__design__instance__displacement__mean": 0.2575, - "detailedplace__design__instance__displacement__total": 3708.18, - "detailedplace__design__instance__utilization": 0.138644, - "detailedplace__design__instance__utilization__stdcell": 0.138644, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 344420.0, - "detailedplace__power__internal__total": 0.0137351, - "detailedplace__power__leakage__total": 1.19157e-08, - "detailedplace__power__switching__total": 0.0200905, - "detailedplace__power__total": 0.0338257, - "detailedplace__route__wirelength__estimated": 234354, - "detailedplace__runtime__total": "0:13.17", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.909764, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.763937, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 41.3813, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 8438, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 1880, - "detailedroute__route__drc_errors__iter:3": 1478, - "detailedroute__route__drc_errors__iter:4": 249, - "detailedroute__route__drc_errors__iter:5": 80, - "detailedroute__route__drc_errors__iter:6": 21, - "detailedroute__route__drc_errors__iter:7": 19, - "detailedroute__route__drc_errors__iter:8": 6, - "detailedroute__route__drc_errors__iter:9": 4, - "detailedroute__route__net": 13170, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 154213, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 154213, - "detailedroute__route__wirelength": 287644, - "detailedroute__route__wirelength__iter:1": 287744, - "detailedroute__route__wirelength__iter:10": 287644, - "detailedroute__route__wirelength__iter:11": 287644, - "detailedroute__route__wirelength__iter:2": 287414, - "detailedroute__route__wirelength__iter:3": 287308, - "detailedroute__route__wirelength__iter:4": 287610, - "detailedroute__route__wirelength__iter:5": 287629, - "detailedroute__route__wirelength__iter:6": 287640, - "detailedroute__route__wirelength__iter:7": 287651, - "detailedroute__route__wirelength__iter:8": 287647, - "detailedroute__route__wirelength__iter:9": 287647, - "finish__clock__skew__hold": 51.0846, - "finish__clock__skew__setup": 45.8883, - "finish__cpu__total": 17.51, - "finish__design__core__area": 60607.3, - "finish__design__die__area": 62500, - "finish__design__instance__area": 8595.73, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 8595.73, - "finish__design__instance__count": 12982, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 12982, - "finish__design__instance__utilization": 0.141827, - "finish__design__instance__utilization__stdcell": 0.141827, - "finish__design__io": 388, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 607380.0, - "finish__power__internal__total": 0.0142924, - "finish__power__leakage__total": 1.24089e-08, - "finish__power__switching__total": 0.0181662, - "finish__power__total": 0.0324586, - "finish__runtime__total": "0:18.82", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.944597, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.807653, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 311.701, - "finish__timing__wns_percent_delay": 14.937814, - "finish_merge__cpu__total": 6.27, - "finish_merge__mem__peak": 650620.0, - "finish_merge__runtime__total": "0:11.84", - "floorplan__cpu__total": 5.09, - "floorplan__design__core__area": 60607.3, - "floorplan__design__die__area": 62500, - "floorplan__design__instance__area": 5056.69, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 5056.69, - "floorplan__design__instance__count": 12411, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 12411, - "floorplan__design__instance__utilization": 0.0834337, - "floorplan__design__instance__utilization__stdcell": 0.0834337, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 24, - "floorplan__mem__peak": 276264.0, - "floorplan__power__internal__total": 0.00607069, - "floorplan__power__leakage__total": 4.65404e-09, - "floorplan__power__switching__total": 0.00438541, - "floorplan__power__total": 0.0104561, - "floorplan__runtime__total": "0:07.57", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 578.87, - "floorplan_io__cpu__total": 1.66, - "floorplan_io__mem__peak": 241156.0, - "floorplan_io__runtime__total": "0:01.94", - "floorplan_macro__cpu__total": 1.62, - "floorplan_macro__mem__peak": 240400.0, - "floorplan_macro__runtime__total": "0:01.94", - "floorplan_pdn__cpu__total": 3.44, - "floorplan_pdn__mem__peak": 336060.0, - "floorplan_pdn__runtime__total": "0:03.98", - "floorplan_tap__cpu__total": 1.68, - "floorplan_tap__mem__peak": 233200.0, - "floorplan_tap__runtime__total": "0:02.13", - "floorplan_tdms__cpu__total": 1.6, - "floorplan_tdms__mem__peak": 240116.0, - "floorplan_tdms__runtime__total": "0:01.94", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 162.35, - "globalplace__design__core__area": 60607.3, - "globalplace__design__die__area": 62500, - "globalplace__design__instance__area": 5056.69, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 5056.69, - "globalplace__design__instance__count": 12411, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 12411, - "globalplace__design__instance__utilization": 0.0834337, - "globalplace__design__instance__utilization__stdcell": 0.0834337, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 1, - "globalplace__mem__peak": 1568904.0, - "globalplace__power__internal__total": 0.00596567, - "globalplace__power__leakage__total": 4.65404e-09, - "globalplace__power__switching__total": 0.0167955, - "globalplace__power__total": 0.0227612, - "globalplace__runtime__total": "0:47.31", - "globalplace__timing__setup__tns": -589856, - "globalplace__timing__setup__ws": -3198.01, - "globalplace_io__cpu__total": 1.77, - "globalplace_io__mem__peak": 260108.0, - "globalplace_io__runtime__total": "0:02.09", - "globalplace_skip_io__cpu__total": 253.78, - "globalplace_skip_io__mem__peak": 274688.0, - "globalplace_skip_io__runtime__total": "0:10.25", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 101.091, - "globalroute__clock__skew__setup": 87.3316, - "globalroute__cpu__total": 55.01, - "globalroute__design__core__area": 60607.3, - "globalroute__design__die__area": 62500, - "globalroute__design__instance__area": 8595.73, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 8595.73, - "globalroute__design__instance__count": 12982, - "globalroute__design__instance__count__hold_buffer": 4, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 2, - "globalroute__design__instance__count__stdcell": 12982, - "globalroute__design__instance__displacement__max": 1.404, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 5.94, - "globalroute__design__instance__utilization": 0.141827, - "globalroute__design__instance__utilization__stdcell": 0.141827, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 1633340.0, - "globalroute__power__internal__total": 0.0142632, - "globalroute__power__leakage__total": 1.24089e-08, - "globalroute__power__switching__total": 0.0221313, - "globalroute__power__total": 0.0363945, - "globalroute__route__wirelength__estimated": 225857, - "globalroute__runtime__total": "0:26.12", - "globalroute__timing__clock__slack": -55.496, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.91682, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.75787, - "globalroute__timing__drv__setup_violation_count": 5, - "globalroute__timing__setup__tns": -179.867, - "globalroute__timing__setup__ws": -55.4965, - "placeopt__cpu__total": 12.6, - "placeopt__design__core__area": 60607.3, - "placeopt__design__die__area": 62500, - "placeopt__design__instance__area": 8402.86, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 8402.86, - "placeopt__design__instance__count": 12798, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 12798, - "placeopt__design__instance__utilization": 0.138644, - "placeopt__design__instance__utilization__stdcell": 0.138644, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 1375600.0, - "placeopt__power__internal__total": 0.0137354, - "placeopt__power__leakage__total": 1.19157e-08, - "placeopt__power__switching__total": 0.0209614, - "placeopt__power__total": 0.0346968, - "placeopt__runtime__total": "0:13.75", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.934248, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.761377, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 18.5765, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-09-19 14:04", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15759-g9136ba699", - "run__flow__platform": "intel16", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "dcb6ca0773163b3ff4f04a9a88c8df5f2a1860f4", - "run__flow__uuid": "8cb08658-a5f2-4c12-9036-bbc3a439a323", - "run__flow__variant": "base", - "synth__cpu__total": 38.52, - "synth__design__instance__area__stdcell": 5056.69392, - "synth__design__instance__count__stdcell": 12411.0, - "synth__mem__peak": 134256.0, - "synth__runtime__total": "0:43.10", - "total_time": "0:03:39.690000" -} \ No newline at end of file diff --git a/flow/designs/intel16/gcd/config.mk b/flow/designs/intel16/gcd/config.mk deleted file mode 100644 index 6d857dfbd6..0000000000 --- a/flow/designs/intel16/gcd/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -export DESIGN_NAME = gcd -export PLATFORM = intel16 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export ABC_AREA = 1 - -# Adders degrade GCD -export ADDER_MAP_FILE := - -export CORE_UTILIZATION = 30 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 1 - -export PLACE_DENSITY = uniform diff --git a/flow/designs/intel16/gcd/constraint.sdc b/flow/designs/intel16/gcd/constraint.sdc deleted file mode 100644 index 727b5bffb3..0000000000 --- a/flow/designs/intel16/gcd/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design gcd - -set clk_name core_clock -set clk_port_name clk -set clk_period 1200 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel16/gcd/metadata-base-ok.json b/flow/designs/intel16/gcd/metadata-base-ok.json deleted file mode 100644 index e38171d222..0000000000 --- a/flow/designs/intel16/gcd/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1200.0000" - ], - "cts__clock__skew__hold": 7.62462, - "cts__clock__skew__setup": 6.78575, - "cts__cpu__total": 12.83, - "cts__design__core__area": 544.184, - "cts__design__die__area": 652.394, - "cts__design__instance__area": 298.015, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 298.015, - "cts__design__instance__count": 516, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 24, - "cts__design__instance__count__stdcell": 516, - "cts__design__instance__displacement__max": 3.132, - "cts__design__instance__displacement__mean": 0.2775, - "cts__design__instance__displacement__total": 167.349, - "cts__design__instance__utilization": 0.547637, - "cts__design__instance__utilization__stdcell": 0.547637, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 2, - "cts__mem__peak": 984076.0, - "cts__power__internal__total": 0.000197195, - "cts__power__leakage__total": 3.78513e-10, - "cts__power__switching__total": 9.63564e-05, - "cts__power__total": 0.000293551, - "cts__route__wirelength__estimated": 2158.84, - "cts__runtime__total": "0:13.70", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.95148, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.942792, - "cts__timing__drv__setup_violation_count": 7, - "cts__timing__setup__tns": -54.6246, - "cts__timing__setup__ws": -8.74911, - "design__io__hpwl": 745447, - "design__violations": 0, - "detailedplace__cpu__total": 1.71, - "detailedplace__design__core__area": 544.184, - "detailedplace__design__die__area": 652.394, - "detailedplace__design__instance__area": 200.154, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 200.154, - "detailedplace__design__instance__count": 484, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 484, - "detailedplace__design__instance__displacement__max": 2.034, - "detailedplace__design__instance__displacement__mean": 0.3415, - "detailedplace__design__instance__displacement__total": 194.768, - "detailedplace__design__instance__utilization": 0.367806, - "detailedplace__design__instance__utilization__stdcell": 0.367806, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 227156.0, - "detailedplace__power__internal__total": 0.000104745, - "detailedplace__power__leakage__total": 1.84387e-10, - "detailedplace__power__switching__total": 4.95722e-05, - "detailedplace__power__total": 0.000154318, - "detailedplace__route__wirelength__estimated": 2011, - "detailedplace__runtime__total": "0:01.98", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.951963, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.938851, - "detailedplace__timing__drv__setup_violation_count": 20, - "detailedplace__timing__setup__tns": -938.305, - "detailedplace__timing__setup__ws": -161.045, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 8, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 242, - "detailedroute__route__drc_errors__iter:2": 55, - "detailedroute__route__drc_errors__iter:3": 39, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 550, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3714, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3714, - "detailedroute__route__wirelength": 2626, - "detailedroute__route__wirelength__iter:1": 2677, - "detailedroute__route__wirelength__iter:2": 2651, - "detailedroute__route__wirelength__iter:3": 2620, - "detailedroute__route__wirelength__iter:4": 2626, - "finish__clock__skew__hold": 9.67611, - "finish__clock__skew__setup": 8.85549, - "finish__cpu__total": 2.51, - "finish__design__core__area": 544.184, - "finish__design__die__area": 652.394, - "finish__design__instance__area": 312.654, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 312.654, - "finish__design__instance__count": 517, - "finish__design__instance__count__class:buffer": 11, - "finish__design__instance__count__class:clock_buffer": 6, - "finish__design__instance__count__class:clock_inverter": 2, - "finish__design__instance__count__class:fill_cell": 588, - "finish__design__instance__count__class:inverter": 52, - "finish__design__instance__count__class:multi_input_combinational_cell": 333, - "finish__design__instance__count__class:sequential_cell": 35, - "finish__design__instance__count__class:timing_repair_buffer": 78, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 517, - "finish__design__instance__utilization": 0.574536, - "finish__design__instance__utilization__stdcell": 0.574536, - "finish__design__io": 54, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 310684.0, - "finish__power__internal__total": 0.000208217, - "finish__power__leakage__total": 4.11867e-10, - "finish__power__switching__total": 9.84626e-05, - "finish__power__total": 0.00030668, - "finish__runtime__total": "0:03.20", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.949075, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.942726, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 3.77154, - "finish__timing__wns_percent_delay": 0.394414, - "finish_merge__cpu__total": 1.3, - "finish_merge__mem__peak": 415644.0, - "finish_merge__runtime__total": "0:05.08", - "floorplan__cpu__total": 1.78, - "floorplan__design__core__area": 544.184, - "floorplan__design__die__area": 652.394, - "floorplan__design__instance__area": 166.27, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 166.27, - "floorplan__design__instance__count": 431, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 431, - "floorplan__design__instance__utilization": 0.305541, - "floorplan__design__instance__utilization__stdcell": 0.305541, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 24, - "floorplan__mem__peak": 227932.0, - "floorplan__power__internal__total": 8.35832e-05, - "floorplan__power__leakage__total": 1.57991e-10, - "floorplan__power__switching__total": 3.05477e-05, - "floorplan__power__total": 0.000114131, - "floorplan__runtime__total": "0:03.40", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 225.157, - "floorplan_io__cpu__total": 1.49, - "floorplan_io__mem__peak": 221808.0, - "floorplan_io__runtime__total": "0:01.73", - "floorplan_macro__cpu__total": 1.48, - "floorplan_macro__mem__peak": 221524.0, - "floorplan_macro__runtime__total": "0:01.73", - "floorplan_pdn__cpu__total": 1.52, - "floorplan_pdn__mem__peak": 224344.0, - "floorplan_pdn__runtime__total": "0:01.85", - "floorplan_tap__cpu__total": 1.54, - "floorplan_tap__mem__peak": 221576.0, - "floorplan_tap__runtime__total": "0:01.88", - "floorplan_tdms__cpu__total": 0.11, - "floorplan_tdms__mem__peak": 98716.0, - "floorplan_tdms__runtime__total": "0:00.15", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 7.9, - "globalplace__design__core__area": 544.184, - "globalplace__design__die__area": 652.394, - "globalplace__design__instance__area": 166.27, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 166.27, - "globalplace__design__instance__count": 431, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 431, - "globalplace__design__instance__utilization": 0.305541, - "globalplace__design__instance__utilization__stdcell": 0.305541, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 1, - "globalplace__mem__peak": 942560.0, - "globalplace__power__internal__total": 8.34155e-05, - "globalplace__power__leakage__total": 1.57991e-10, - "globalplace__power__switching__total": 5.0641e-05, - "globalplace__power__total": 0.000134057, - "globalplace__runtime__total": "0:03.49", - "globalplace__timing__setup__tns": -336.639, - "globalplace__timing__setup__ws": -48.7749, - "globalplace_io__cpu__total": 1.51, - "globalplace_io__mem__peak": 222548.0, - "globalplace_io__runtime__total": "0:01.73", - "globalplace_skip_io__cpu__total": 6.43, - "globalplace_skip_io__mem__peak": 224104.0, - "globalplace_skip_io__runtime__total": "0:02.02", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 8.60141, - "globalroute__clock__skew__setup": 7.76408, - "globalroute__cpu__total": 6.96, - "globalroute__design__core__area": 544.184, - "globalroute__design__die__area": 652.394, - "globalroute__design__instance__area": 312.654, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 312.654, - "globalroute__design__instance__count": 517, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 1, - "globalroute__design__instance__count__stdcell": 517, - "globalroute__design__instance__displacement__max": 2.592, - "globalroute__design__instance__displacement__mean": 0.062, - "globalroute__design__instance__displacement__total": 37.584, - "globalroute__design__instance__utilization": 0.574536, - "globalroute__design__instance__utilization__stdcell": 0.574536, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 949780.0, - "globalroute__power__internal__total": 0.000208145, - "globalroute__power__leakage__total": 4.11867e-10, - "globalroute__power__switching__total": 0.000118347, - "globalroute__power__total": 0.000326492, - "globalroute__route__wirelength__estimated": 2203.73, - "globalroute__runtime__total": "0:06.37", - "globalroute__timing__clock__slack": -56.584, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.940014, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.933773, - "globalroute__timing__drv__setup_violation_count": 28, - "globalroute__timing__setup__tns": -712.995, - "globalroute__timing__setup__ws": -56.5835, - "placeopt__cpu__total": 1.85, - "placeopt__design__core__area": 544.184, - "placeopt__design__die__area": 652.394, - "placeopt__design__instance__area": 200.154, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 200.154, - "placeopt__design__instance__count": 484, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 484, - "placeopt__design__instance__utilization": 0.367806, - "placeopt__design__instance__utilization__stdcell": 0.367806, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 884332.0, - "placeopt__power__internal__total": 0.000104732, - "placeopt__power__leakage__total": 1.84387e-10, - "placeopt__power__switching__total": 5.06673e-05, - "placeopt__power__total": 0.0001554, - "placeopt__runtime__total": "0:02.48", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.954291, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.935887, - "placeopt__timing__drv__setup_violation_count": 19, - "placeopt__timing__setup__tns": -607.594, - "placeopt__timing__setup__ws": -168.573, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-10-25 20:35", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16762-g7ff30eabb", - "run__flow__platform": "intel16", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "667e920003c11365066311f2823f79ea4f1ef964", - "run__flow__uuid": "62300412-3533-4a1b-ab7b-4580152bdf90", - "run__flow__variant": "base", - "synth__cpu__total": 2.26, - "synth__design__instance__area__stdcell": 166.27032, - "synth__design__instance__count__stdcell": 431.0, - "synth__mem__peak": 96000.0, - "synth__runtime__total": "0:05.36", - "total_time": "0:00:56.150000" -} \ No newline at end of file diff --git a/flow/designs/intel22/aes/config.mk b/flow/designs/intel22/aes/config.mk deleted file mode 100644 index ec01f5a5e6..0000000000 --- a/flow/designs/intel22/aes/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = aes -export DESIGN_NAME = aes_cipher_top -export PLATFORM = intel22 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -# These values must be multiples of placement site -# x=0.19 y=1.4 -export DIE_AREA = 0 0 250 250 -export CORE_AREA = 1.26 1.89 248 248 - -export PLACE_DENSITY = uniform -export SKIP_PIN_SWAP = 1 -export SKIP_GATE_CLONING = 1 diff --git a/flow/designs/intel22/aes/constraint.sdc b/flow/designs/intel22/aes/constraint.sdc deleted file mode 100644 index be212dcfa9..0000000000 --- a/flow/designs/intel22/aes/constraint.sdc +++ /dev/null @@ -1,8 +0,0 @@ -set clk_name clk -set clk_period 1360 -# -create_clock -name $clk_name -period $clk_period [get_ports clk] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] - diff --git a/flow/designs/intel22/aes/metadata-base-ok.json b/flow/designs/intel22/aes/metadata-base-ok.json deleted file mode 100644 index cce4653096..0000000000 --- a/flow/designs/intel22/aes/metadata-base-ok.json +++ /dev/null @@ -1,382 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1360.0000" - ], - "cts__clock__skew__hold": 133.665, - "cts__clock__skew__hold__post_repair": 130.695, - "cts__clock__skew__hold__pre_repair": 130.695, - "cts__clock__skew__setup": 133.665, - "cts__clock__skew__setup__post_repair": 130.695, - "cts__clock__skew__setup__pre_repair": 130.695, - "cts__cpu__total": 546.21, - "cts__design__core__area": 60607.3, - "cts__design__core__area__post_repair": 60607.3, - "cts__design__core__area__pre_repair": 60607.3, - "cts__design__die__area": 62500, - "cts__design__die__area__post_repair": 62500, - "cts__design__die__area__pre_repair": 62500, - "cts__design__instance__area": 14731.6, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 12155.5, - "cts__design__instance__area__pre_repair": 12155.5, - "cts__design__instance__area__stdcell": 14731.6, - "cts__design__instance__area__stdcell__post_repair": 12155.5, - "cts__design__instance__area__stdcell__pre_repair": 12155.5, - "cts__design__instance__count": 19001, - "cts__design__instance__count__hold_buffer": 587, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 16566, - "cts__design__instance__count__pre_repair": 16566, - "cts__design__instance__count__setup_buffer": 1644, - "cts__design__instance__count__stdcell": 19001, - "cts__design__instance__count__stdcell__post_repair": 16566, - "cts__design__instance__count__stdcell__pre_repair": 16566, - "cts__design__instance__displacement__max": 9.288, - "cts__design__instance__displacement__mean": 0.1965, - "cts__design__instance__displacement__total": 4084.48, - "cts__design__instance__utilization": 0.243067, - "cts__design__instance__utilization__post_repair": 0.200561, - "cts__design__instance__utilization__pre_repair": 0.200561, - "cts__design__instance__utilization__stdcell": 0.243067, - "cts__design__instance__utilization__stdcell__post_repair": 0.200561, - "cts__design__instance__utilization__stdcell__pre_repair": 0.200561, - "cts__design__io": 388, - "cts__design__io__post_repair": 388, - "cts__design__io__pre_repair": 388, - "cts__design__violations": 0, - "cts__mem__peak": 678392.0, - "cts__power__internal__total": 0.0175733, - "cts__power__internal__total__post_repair": 0.0161942, - "cts__power__internal__total__pre_repair": 0.0161942, - "cts__power__leakage__total": 2.38637e-08, - "cts__power__leakage__total__post_repair": 1.71547e-08, - "cts__power__leakage__total__pre_repair": 1.71547e-08, - "cts__power__switching__total": 0.0168935, - "cts__power__switching__total__post_repair": 0.0200671, - "cts__power__switching__total__pre_repair": 0.0200671, - "cts__power__total": 0.0344668, - "cts__power__total__post_repair": 0.0362614, - "cts__power__total__pre_repair": 0.0362614, - "cts__route__wirelength__estimated": 316908, - "cts__runtime__total": "9:17.85", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 273, - "cts__timing__drv__hold_violation_count__pre_repair": 273, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.876955, - "cts__timing__drv__max_cap_limit__post_repair": 0.943608, - "cts__timing__drv__max_cap_limit__pre_repair": 0.943608, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.665165, - "cts__timing__drv__max_slew_limit__post_repair": 0.0604247, - "cts__timing__drv__max_slew_limit__pre_repair": 0.0604247, - "cts__timing__drv__setup_violation_count": 276, - "cts__timing__drv__setup_violation_count__post_repair": 384, - "cts__timing__drv__setup_violation_count__pre_repair": 384, - "cts__timing__setup__tns": -42682.7, - "cts__timing__setup__tns__post_repair": -274372, - "cts__timing__setup__tns__pre_repair": -274372, - "cts__timing__setup__ws": -239.41, - "cts__timing__setup__ws__post_repair": -1537.01, - "cts__timing__setup__ws__pre_repair": -1537.01, - "cts_fill__cpu__total": 3.48, - "cts_fill__mem__peak": 370360.0, - "cts_fill__runtime__total": "0:03.68", - "design__io__hpwl": 65878803, - "detailedplace__cpu__total": 22.48, - "detailedplace__design__core__area": 60607.3, - "detailedplace__design__die__area": 62500, - "detailedplace__design__instance__area": 12140.2, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 12140.2, - "detailedplace__design__instance__count": 16541, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 16541, - "detailedplace__design__instance__displacement__max": 3.474, - "detailedplace__design__instance__displacement__mean": 0.3335, - "detailedplace__design__instance__displacement__total": 6106.17, - "detailedplace__design__instance__utilization": 0.200309, - "detailedplace__design__instance__utilization__stdcell": 0.200309, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 415400.0, - "detailedplace__power__internal__total": 0.0161686, - "detailedplace__power__leakage__total": 1.71219e-08, - "detailedplace__power__switching__total": 0.0197765, - "detailedplace__power__total": 0.0359451, - "detailedplace__route__wirelength__estimated": 246352, - "detailedplace__runtime__total": "0:22.88", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.943608, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0603724, - "detailedplace__timing__drv__setup_violation_count": 383, - "detailedplace__timing__setup__tns": -263622, - "detailedplace__timing__setup__ws": -1458.15, - "detailedroute__cpu__total": 2035.23, - "detailedroute__mem__peak": 6390504.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 22117, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 1, - "detailedroute__route__drc_errors__iter:13": 1, - "detailedroute__route__drc_errors__iter:14": 1, - "detailedroute__route__drc_errors__iter:15": 1, - "detailedroute__route__drc_errors__iter:16": 1, - "detailedroute__route__drc_errors__iter:17": 1, - "detailedroute__route__drc_errors__iter:18": 1, - "detailedroute__route__drc_errors__iter:19": 1, - "detailedroute__route__drc_errors__iter:2": 4843, - "detailedroute__route__drc_errors__iter:20": 1, - "detailedroute__route__drc_errors__iter:21": 0, - "detailedroute__route__drc_errors__iter:3": 5138, - "detailedroute__route__drc_errors__iter:4": 765, - "detailedroute__route__drc_errors__iter:5": 159, - "detailedroute__route__drc_errors__iter:6": 37, - "detailedroute__route__drc_errors__iter:7": 13, - "detailedroute__route__drc_errors__iter:8": 9, - "detailedroute__route__drc_errors__iter:9": 6, - "detailedroute__route__net": 19271, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 219106, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 219106, - "detailedroute__route__wirelength": 421645, - "detailedroute__route__wirelength__iter:1": 422091, - "detailedroute__route__wirelength__iter:10": 421644, - "detailedroute__route__wirelength__iter:11": 421644, - "detailedroute__route__wirelength__iter:12": 421644, - "detailedroute__route__wirelength__iter:13": 421644, - "detailedroute__route__wirelength__iter:14": 421644, - "detailedroute__route__wirelength__iter:15": 421644, - "detailedroute__route__wirelength__iter:16": 421644, - "detailedroute__route__wirelength__iter:17": 421644, - "detailedroute__route__wirelength__iter:18": 421644, - "detailedroute__route__wirelength__iter:19": 421644, - "detailedroute__route__wirelength__iter:2": 421927, - "detailedroute__route__wirelength__iter:20": 421644, - "detailedroute__route__wirelength__iter:21": 421645, - "detailedroute__route__wirelength__iter:3": 421642, - "detailedroute__route__wirelength__iter:4": 421783, - "detailedroute__route__wirelength__iter:5": 421669, - "detailedroute__route__wirelength__iter:6": 421667, - "detailedroute__route__wirelength__iter:7": 421650, - "detailedroute__route__wirelength__iter:8": 421643, - "detailedroute__route__wirelength__iter:9": 421649, - "detailedroute__runtime__total": "3:31.39", - "finish__clock__skew__hold": 25.1679, - "finish__clock__skew__setup": 22.6151, - "finish__cpu__total": 13.28, - "finish__design__core__area": 60607.3, - "finish__design__die__area": 62500, - "finish__design__instance__area": 14731.6, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 14731.6, - "finish__design__instance__count": 19001, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 19001, - "finish__design__instance__utilization": 0.243067, - "finish__design__instance__utilization__stdcell": 0.243067, - "finish__design__io": 388, - "finish__mem__peak": 596948.0, - "finish__power__internal__total": 0.0206811, - "finish__power__leakage__total": 2.38637e-08, - "finish__power__switching__total": 0.0101721, - "finish__power__total": 0.0308532, - "finish__runtime__total": "0:13.55", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.88075, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.85971, - "finish__timing__drv__setup_violation_count": 1, - "finish__timing__setup__tns": -8.887, - "finish__timing__setup__ws": -8.887, - "finish__timing__wns_percent_delay": -0.600344, - "finish_merge__cpu__total": 4.17, - "finish_merge__mem__peak": 629992.0, - "finish_merge__runtime__total": "0:04.52", - "floorplan__cpu__total": 6.97, - "floorplan__design__core__area": 60607.3, - "floorplan__design__die__area": 62500, - "floorplan__design__instance__area": 7248.57, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 7248.57, - "floorplan__design__instance__count": 16147, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 16147, - "floorplan__design__instance__utilization": 0.119599, - "floorplan__design__instance__utilization__stdcell": 0.119599, - "floorplan__design__io": 388, - "floorplan__mem__peak": 356300.0, - "floorplan__power__internal__total": 0.00651519, - "floorplan__power__leakage__total": 6.59896e-09, - "floorplan__power__switching__total": 0.00389821, - "floorplan__power__total": 0.0104134, - "floorplan__runtime__total": "0:07.31", - "floorplan__timing__setup__tns": -137075, - "floorplan__timing__setup__ws": -763.089, - "floorplan_io__cpu__total": 3.17, - "floorplan_io__mem__peak": 310672.0, - "floorplan_io__runtime__total": "0:03.36", - "floorplan_macro__cpu__total": 3.15, - "floorplan_macro__mem__peak": 310140.0, - "floorplan_macro__runtime__total": "0:03.34", - "floorplan_pdn__cpu__total": 3.65, - "floorplan_pdn__mem__peak": 327232.0, - "floorplan_pdn__runtime__total": "0:03.83", - "floorplan_tap__cpu__total": 3.19, - "floorplan_tap__mem__peak": 298948.0, - "floorplan_tap__runtime__total": "0:03.42", - "floorplan_tdms__cpu__total": 3.16, - "floorplan_tdms__mem__peak": 309716.0, - "floorplan_tdms__runtime__total": "0:03.34", - "globalplace__cpu__total": 74.09, - "globalplace__design__core__area": 60607.3, - "globalplace__design__die__area": 62500, - "globalplace__design__instance__area": 7248.57, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 7248.57, - "globalplace__design__instance__count": 16147, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16147, - "globalplace__design__instance__utilization": 0.119599, - "globalplace__design__instance__utilization__stdcell": 0.119599, - "globalplace__design__io": 388, - "globalplace__mem__peak": 601128.0, - "globalplace__power__internal__total": 0.00638753, - "globalplace__power__leakage__total": 6.59896e-09, - "globalplace__power__switching__total": 0.0149962, - "globalplace__power__total": 0.0213837, - "globalplace__runtime__total": "1:14.69", - "globalplace__timing__setup__tns": -1399020.0, - "globalplace__timing__setup__ws": -5230.25, - "globalplace_io__cpu__total": 3.23, - "globalplace_io__mem__peak": 318056.0, - "globalplace_io__runtime__total": "0:03.40", - "globalplace_skip_io__cpu__total": 7.62, - "globalplace_skip_io__mem__peak": 336328.0, - "globalplace_skip_io__runtime__total": "0:07.84", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 135.456, - "globalroute__clock__skew__setup": 135.456, - "globalroute__cpu__total": 24.34, - "globalroute__design__core__area": 60607.3, - "globalroute__design__die__area": 62500, - "globalroute__design__instance__area": 14731.6, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 14731.6, - "globalroute__design__instance__count": 19001, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 19001, - "globalroute__design__instance__utilization": 0.243067, - "globalroute__design__instance__utilization__stdcell": 0.243067, - "globalroute__design__io": 388, - "globalroute__mem__peak": 733136.0, - "globalroute__power__internal__total": 0.0204935, - "globalroute__power__leakage__total": 2.38637e-08, - "globalroute__power__switching__total": 0.0246905, - "globalroute__power__total": 0.045184, - "globalroute__runtime__total": "0:25.75", - "globalroute__timing__clock__slack": -556.38, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.871295, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.663013, - "globalroute__timing__drv__setup_violation_count": 331, - "globalroute__timing__setup__tns": -81412.3, - "globalroute__timing__setup__ws": -556.38, - "placeopt__cpu__total": 17.08, - "placeopt__design__core__area": 60607.3, - "placeopt__design__core__area__pre_opt": 60607.3, - "placeopt__design__die__area": 62500, - "placeopt__design__die__area__pre_opt": 62500, - "placeopt__design__instance__area": 12140.2, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 7248.57, - "placeopt__design__instance__area__stdcell": 12140.2, - "placeopt__design__instance__area__stdcell__pre_opt": 7248.57, - "placeopt__design__instance__count": 16541, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 16147, - "placeopt__design__instance__count__stdcell": 16541, - "placeopt__design__instance__count__stdcell__pre_opt": 16147, - "placeopt__design__instance__utilization": 0.200309, - "placeopt__design__instance__utilization__pre_opt": 0.119599, - "placeopt__design__instance__utilization__stdcell": 0.200309, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.119599, - "placeopt__design__io": 388, - "placeopt__design__io__pre_opt": 388, - "placeopt__mem__peak": 403048.0, - "placeopt__power__internal__total": 0.016146, - "placeopt__power__internal__total__pre_opt": 0.00638753, - "placeopt__power__leakage__total": 1.71219e-08, - "placeopt__power__leakage__total__pre_opt": 6.59896e-09, - "placeopt__power__switching__total": 0.0202381, - "placeopt__power__switching__total__pre_opt": 0.0149962, - "placeopt__power__total": 0.0363841, - "placeopt__power__total__pre_opt": 0.0213837, - "placeopt__runtime__total": "0:17.55", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.952703, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0676234, - "placeopt__timing__drv__setup_violation_count": 384, - "placeopt__timing__setup__tns": -266263, - "placeopt__timing__setup__tns__pre_opt": -1399020.0, - "placeopt__timing__setup__ws": -1368.82, - "placeopt__timing__setup__ws__pre_opt": -5230.25, - "run__flow__design": "aes", - "run__flow__generate_date": "2023-08-09 08:09", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9791-gea56b56a9", - "run__flow__platform": "intel22", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0003c5b3f06a27584094a32eef82bb97f1650981", - "run__flow__scripts_commit": "d9cb46d68a7f018bc85e985b3511d0deb5413ca0", - "run__flow__uuid": "d049e51a-addb-4298-86e0-9bc44e440975", - "run__flow__variant": "base", - "synth__cpu__total": 86.97, - "synth__design__instance__area__stdcell": 7932.30732, - "synth__design__instance__count__stdcell": 18153.0, - "synth__mem__peak": 724344.0, - "synth__runtime__total": "1:29.34", - "total_time": "0:17:37.040000" -} \ No newline at end of file diff --git a/flow/designs/intel22/gcd/config.mk b/flow/designs/intel22/gcd/config.mk deleted file mode 100644 index 79e8596628..0000000000 --- a/flow/designs/intel22/gcd/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NAME = gcd -export DESIGN_NICKNAME = gcd -export DESIGN = gcd - -export PLATFORM = intel22 - -export VERILOG_FILES = $(sort $(wildcard $(abspath $(DESIGN_HOME)/src/$(DESIGN))/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -export PLACE_DENSITY = 0.35 - -export DIE_AREA = 0 0 50 50 -export CORE_AREA = 1.26 1.89 49 49 diff --git a/flow/designs/intel22/gcd/constraint.sdc b/flow/designs/intel22/gcd/constraint.sdc deleted file mode 100644 index 6b11ec3f1a..0000000000 --- a/flow/designs/intel22/gcd/constraint.sdc +++ /dev/null @@ -1,7 +0,0 @@ -set clk_name clk -set clk_period 880 -# -create_clock [get_ports clk] -name $clk_name -period $clk_period -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel22/gcd/metadata-base-ok.json b/flow/designs/intel22/gcd/metadata-base-ok.json deleted file mode 100644 index f20ab5f41d..0000000000 --- a/flow/designs/intel22/gcd/metadata-base-ok.json +++ /dev/null @@ -1,363 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 880.0000" - ], - "cts__clock__skew__hold": 4.98633, - "cts__clock__skew__hold__post_repair": 4.23359, - "cts__clock__skew__hold__pre_repair": 4.23359, - "cts__clock__skew__setup": 4.98633, - "cts__clock__skew__setup__post_repair": 4.23359, - "cts__clock__skew__setup__pre_repair": 4.23359, - "cts__cpu__total": 24.58, - "cts__design__core__area": 2220.42, - "cts__design__core__area__post_repair": 2220.42, - "cts__design__core__area__pre_repair": 2220.42, - "cts__design__die__area": 2500, - "cts__design__die__area__post_repair": 2500, - "cts__design__die__area__pre_repair": 2500, - "cts__design__instance__area": 266.172, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 232.084, - "cts__design__instance__area__pre_repair": 232.084, - "cts__design__instance__area__stdcell": 266.172, - "cts__design__instance__area__stdcell__post_repair": 232.084, - "cts__design__instance__area__stdcell__pre_repair": 232.084, - "cts__design__instance__count": 391, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 337, - "cts__design__instance__count__pre_repair": 337, - "cts__design__instance__count__setup_buffer": 54, - "cts__design__instance__count__stdcell": 391, - "cts__design__instance__count__stdcell__post_repair": 337, - "cts__design__instance__count__stdcell__pre_repair": 337, - "cts__design__instance__displacement__max": 3.132, - "cts__design__instance__displacement__mean": 0.1705, - "cts__design__instance__displacement__total": 85.8635, - "cts__design__instance__utilization": 0.119875, - "cts__design__instance__utilization__post_repair": 0.104523, - "cts__design__instance__utilization__pre_repair": 0.104523, - "cts__design__instance__utilization__stdcell": 0.119875, - "cts__design__instance__utilization__stdcell__post_repair": 0.104523, - "cts__design__instance__utilization__stdcell__pre_repair": 0.104523, - "cts__design__io": 54, - "cts__design__io__post_repair": 54, - "cts__design__io__pre_repair": 54, - "cts__design__violations": 0, - "cts__mem__peak": 297540.0, - "cts__power__internal__total": 0.000187804, - "cts__power__internal__total__post_repair": 0.000168785, - "cts__power__internal__total__pre_repair": 0.000168785, - "cts__power__leakage__total": 3.79461e-10, - "cts__power__leakage__total__post_repair": 3.1415e-10, - "cts__power__leakage__total__pre_repair": 3.1415e-10, - "cts__power__switching__total": 9.46967e-05, - "cts__power__switching__total__post_repair": 9.4739e-05, - "cts__power__switching__total__pre_repair": 9.4739e-05, - "cts__power__total": 0.000282501, - "cts__power__total__post_repair": 0.000263525, - "cts__power__total__pre_repair": 0.000263525, - "cts__route__wirelength__estimated": 2173.04, - "cts__runtime__total": "0:25.35", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.974505, - "cts__timing__drv__max_cap_limit__post_repair": 0.968195, - "cts__timing__drv__max_cap_limit__pre_repair": 0.968195, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.964151, - "cts__timing__drv__max_slew_limit__post_repair": 0.963448, - "cts__timing__drv__max_slew_limit__pre_repair": 0.963448, - "cts__timing__drv__setup_violation_count": 29, - "cts__timing__drv__setup_violation_count__post_repair": 43, - "cts__timing__drv__setup_violation_count__pre_repair": 43, - "cts__timing__setup__tns": -3892.41, - "cts__timing__setup__tns__post_repair": -7414.04, - "cts__timing__setup__tns__pre_repair": -7414.04, - "cts__timing__setup__ws": -215.326, - "cts__timing__setup__ws__post_repair": -344.565, - "cts__timing__setup__ws__pre_repair": -344.565, - "design__io__hpwl": 1629649, - "detailedplace__cpu__total": 3.49, - "detailedplace__design__core__area": 2220.42, - "detailedplace__design__die__area": 2500, - "detailedplace__design__instance__area": 227.798, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 227.798, - "detailedplace__design__instance__count": 330, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 330, - "detailedplace__design__instance__displacement__max": 3.384, - "detailedplace__design__instance__displacement__mean": 0.552, - "detailedplace__design__instance__displacement__total": 244.024, - "detailedplace__design__instance__utilization": 0.102592, - "detailedplace__design__instance__utilization__stdcell": 0.102592, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 257736.0, - "detailedplace__power__internal__total": 0.000148259, - "detailedplace__power__leakage__total": 3.04948e-10, - "detailedplace__power__switching__total": 7.18443e-05, - "detailedplace__power__total": 0.000220103, - "detailedplace__route__wirelength__estimated": 2007.43, - "detailedplace__runtime__total": "0:03.67", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.968195, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.872895, - "detailedplace__timing__drv__setup_violation_count": 40, - "detailedplace__timing__setup__tns": -5737.43, - "detailedplace__timing__setup__ws": -266.837, - "detailedroute__cpu__total": 115.46, - "detailedroute__mem__peak": 953028.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 263, - "detailedroute__route__drc_errors__iter:2": 52, - "detailedroute__route__drc_errors__iter:3": 56, - "detailedroute__route__drc_errors__iter:4": 12, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 432, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2912, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2912, - "detailedroute__route__wirelength": 2618, - "detailedroute__route__wirelength__iter:1": 2642, - "detailedroute__route__wirelength__iter:2": 2627, - "detailedroute__route__wirelength__iter:3": 2615, - "detailedroute__route__wirelength__iter:4": 2621, - "detailedroute__route__wirelength__iter:5": 2617, - "detailedroute__route__wirelength__iter:6": 2617, - "detailedroute__route__wirelength__iter:7": 2618, - "detailedroute__runtime__total": "1:13.92", - "fillcell__cpu__total": 3.47, - "fillcell__mem__peak": 256380.0, - "fillcell__runtime__total": "0:05.27", - "finish__clock__skew__hold": 4.86068, - "finish__clock__skew__setup": 4.43933, - "finish__cpu__total": 4.73, - "finish__design__core__area": 2220.42, - "finish__design__die__area": 2500, - "finish__design__instance__area": 273.725, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 273.725, - "finish__design__instance__count": 396, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 396, - "finish__design__instance__utilization": 0.123276, - "finish__design__instance__utilization__stdcell": 0.123276, - "finish__design__io": 54, - "finish__mem__peak": 303020.0, - "finish__power__internal__total": 0.000198036, - "finish__power__leakage__total": 3.92886e-10, - "finish__power__switching__total": 6.49465e-05, - "finish__power__total": 0.000262983, - "finish__runtime__total": "0:05.03", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.970092, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.93981, - "finish__timing__drv__setup_violation_count": 11, - "finish__timing__setup__tns": -747.328, - "finish__timing__setup__ws": -105.477, - "finish__timing__wns_percent_delay": -13.030233, - "finish_merge__cpu__total": 1.92, - "finish_merge__mem__peak": 279412.0, - "finish_merge__runtime__total": "0:02.22", - "floorplan__cpu__total": 3.63, - "floorplan__design__core__area": 2220.42, - "floorplan__design__die__area": 2500, - "floorplan__design__instance__area": 164.997, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 164.997, - "floorplan__design__instance__count": 277, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 277, - "floorplan__design__instance__utilization": 0.074309, - "floorplan__design__instance__utilization__stdcell": 0.074309, - "floorplan__design__io": 54, - "floorplan__mem__peak": 257708.0, - "floorplan__power__internal__total": 9.70373e-05, - "floorplan__power__leakage__total": 1.78572e-10, - "floorplan__power__switching__total": 2.73913e-05, - "floorplan__power__total": 0.000124429, - "floorplan__runtime__total": "0:03.80", - "floorplan__timing__setup__tns": -3471.07, - "floorplan__timing__setup__ws": -234.601, - "floorplan_io__cpu__total": 3.33, - "floorplan_io__mem__peak": 252868.0, - "floorplan_io__runtime__total": "0:03.54", - "floorplan_macro__cpu__total": 3.21, - "floorplan_macro__mem__peak": 253964.0, - "floorplan_macro__runtime__total": "0:03.39", - "floorplan_pdn__cpu__total": 3.37, - "floorplan_pdn__mem__peak": 254428.0, - "floorplan_pdn__runtime__total": "0:03.57", - "floorplan_tap__cpu__total": 3.35, - "floorplan_tap__mem__peak": 252572.0, - "floorplan_tap__runtime__total": "0:03.59", - "floorplan_tdms__cpu__total": 3.39, - "floorplan_tdms__mem__peak": 252716.0, - "floorplan_tdms__runtime__total": "0:03.61", - "globalplace__cpu__total": 4.54, - "globalplace__design__core__area": 2220.42, - "globalplace__design__die__area": 2500, - "globalplace__design__instance__area": 164.997, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 164.997, - "globalplace__design__instance__count": 277, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 277, - "globalplace__design__instance__utilization": 0.074309, - "globalplace__design__instance__utilization__stdcell": 0.074309, - "globalplace__design__io": 54, - "globalplace__mem__peak": 356664.0, - "globalplace__power__internal__total": 9.67442e-05, - "globalplace__power__leakage__total": 1.78572e-10, - "globalplace__power__switching__total": 5.0677e-05, - "globalplace__power__total": 0.000147421, - "globalplace__runtime__total": "0:04.83", - "globalplace__timing__setup__tns": -27846.6, - "globalplace__timing__setup__ws": -1359.02, - "globalplace_io__cpu__total": 3.31, - "globalplace_io__mem__peak": 253420.0, - "globalplace_io__runtime__total": "0:03.50", - "globalplace_skip_io__cpu__total": 3.4, - "globalplace_skip_io__mem__peak": 253720.0, - "globalplace_skip_io__runtime__total": "0:03.63", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 7.82906, - "globalroute__clock__skew__setup": 7.82906, - "globalroute__cpu__total": 11.18, - "globalroute__design__core__area": 2220.42, - "globalroute__design__die__area": 2500, - "globalroute__design__instance__area": 273.725, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 273.725, - "globalroute__design__instance__count": 396, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 5, - "globalroute__design__instance__count__stdcell": 396, - "globalroute__design__instance__displacement__max": 2.25, - "globalroute__design__instance__displacement__mean": 0.0415, - "globalroute__design__instance__displacement__total": 21.222, - "globalroute__design__instance__utilization": 0.123276, - "globalroute__design__instance__utilization__stdcell": 0.123276, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 360660.0, - "globalroute__power__internal__total": 0.000196254, - "globalroute__power__leakage__total": 3.94914e-10, - "globalroute__power__switching__total": 0.000117216, - "globalroute__power__total": 0.00031347, - "globalroute__route__wirelength__estimated": 2244.41, - "globalroute__runtime__total": "0:27.11", - "globalroute__timing__clock__slack": -231.357, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.957916, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.922127, - "globalroute__timing__drv__setup_violation_count": 41, - "globalroute__timing__setup__tns": -3120, - "globalroute__timing__setup__ws": -231.357, - "placeopt__cpu__total": 3.78, - "placeopt__design__core__area": 2220.42, - "placeopt__design__core__area__pre_opt": 2220.42, - "placeopt__design__die__area": 2500, - "placeopt__design__die__area__pre_opt": 2500, - "placeopt__design__instance__area": 227.798, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 164.997, - "placeopt__design__instance__area__stdcell": 227.798, - "placeopt__design__instance__area__stdcell__pre_opt": 164.997, - "placeopt__design__instance__count": 330, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 277, - "placeopt__design__instance__count__stdcell": 330, - "placeopt__design__instance__count__stdcell__pre_opt": 277, - "placeopt__design__instance__utilization": 0.102592, - "placeopt__design__instance__utilization__pre_opt": 0.074309, - "placeopt__design__instance__utilization__stdcell": 0.102592, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.074309, - "placeopt__design__io": 54, - "placeopt__design__io__pre_opt": 54, - "placeopt__mem__peak": 283292.0, - "placeopt__power__internal__total": 0.000142521, - "placeopt__power__internal__total__pre_opt": 9.67442e-05, - "placeopt__power__leakage__total": 3.05284e-10, - "placeopt__power__leakage__total__pre_opt": 1.78572e-10, - "placeopt__power__switching__total": 6.89701e-05, - "placeopt__power__switching__total__pre_opt": 5.0677e-05, - "placeopt__power__total": 0.000211491, - "placeopt__power__total__pre_opt": 0.000147421, - "placeopt__runtime__total": "0:04.02", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.974173, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.871499, - "placeopt__timing__drv__setup_violation_count": 40, - "placeopt__timing__setup__tns": -5417.37, - "placeopt__timing__setup__tns__pre_opt": -27846.6, - "placeopt__timing__setup__ws": -256.495, - "placeopt__timing__setup__ws__pre_opt": -1359.02, - "run__flow__design": "gcd", - "run__flow__generate_date": "2023-12-18 14:09", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-11538-gbc3306b50", - "run__flow__platform": "intel22", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d3378fd76ca87a25576fe026d9e2ef42c4233e0c", - "run__flow__scripts_commit": "664ad26731368db07b38609491630e59a6ef1fa0", - "run__flow__uuid": "7db9a3d6-e7a6-4169-80f5-badcf0dadbe1", - "run__flow__variant": "base", - "synth__cpu__total": 9.44, - "synth__design__instance__area__stdcell": 170.1, - "synth__design__instance__count__stdcell": 291.0, - "synth__mem__peak": 316332.0, - "synth__runtime__total": "0:10.21", - "total_time": "0:03:10.260000" -} \ No newline at end of file diff --git a/flow/designs/intel22/ibex/config.mk b/flow/designs/intel22/ibex/config.mk deleted file mode 100644 index 8179108aa0..0000000000 --- a/flow/designs/intel22/ibex/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = ibex -export DESIGN_NAME = ibex_core -export PLATFORM = intel22 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -export CORE_UTILIZATION = 30 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 - -export PLACE_DENSITY = uniform -export SKIP_PIN_SWAP = 1 diff --git a/flow/designs/intel22/ibex/constraint.sdc b/flow/designs/intel22/ibex/constraint.sdc deleted file mode 100644 index 51ad46d500..0000000000 --- a/flow/designs/intel22/ibex/constraint.sdc +++ /dev/null @@ -1,8 +0,0 @@ -current_design ibex_core -set clk_name core_clock -set clk_period 3200 -# -create_clock -name $clk_name -period $clk_period [get_ports {clk_i}] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel22/ibex/metadata-base-ok.json b/flow/designs/intel22/ibex/metadata-base-ok.json deleted file mode 100644 index 9bffc3c07c..0000000000 --- a/flow/designs/intel22/ibex/metadata-base-ok.json +++ /dev/null @@ -1,373 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 3200.0000" - ], - "cts__clock__skew__hold": 819.137, - "cts__clock__skew__hold__post_repair": 823.958, - "cts__clock__skew__hold__pre_repair": 823.958, - "cts__clock__skew__setup": 819.137, - "cts__clock__skew__setup__post_repair": 823.958, - "cts__clock__skew__setup__pre_repair": 823.958, - "cts__cpu__total": 3749.59, - "cts__design__core__area": 30384.5, - "cts__design__core__area__post_repair": 30384.5, - "cts__design__core__area__pre_repair": 30384.5, - "cts__design__die__area": 32000.6, - "cts__design__die__area__post_repair": 32000.6, - "cts__design__die__area__pre_repair": 32000.6, - "cts__design__instance__area": 15738.7, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 14214.9, - "cts__design__instance__area__pre_repair": 14214.9, - "cts__design__instance__area__stdcell": 15738.7, - "cts__design__instance__area__stdcell__post_repair": 14214.9, - "cts__design__instance__area__stdcell__pre_repair": 14214.9, - "cts__design__instance__count": 18160, - "cts__design__instance__count__hold_buffer": 701, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 16362, - "cts__design__instance__count__pre_repair": 16362, - "cts__design__instance__count__setup_buffer": 907, - "cts__design__instance__count__stdcell": 18160, - "cts__design__instance__count__stdcell__post_repair": 16362, - "cts__design__instance__count__stdcell__pre_repair": 16362, - "cts__design__instance__displacement__max": 12.186, - "cts__design__instance__displacement__mean": 0.3525, - "cts__design__instance__displacement__total": 6748.05, - "cts__design__instance__utilization": 0.517986, - "cts__design__instance__utilization__post_repair": 0.467835, - "cts__design__instance__utilization__pre_repair": 0.467835, - "cts__design__instance__utilization__stdcell": 0.517986, - "cts__design__instance__utilization__stdcell__post_repair": 0.467835, - "cts__design__instance__utilization__stdcell__pre_repair": 0.467835, - "cts__design__io": 264, - "cts__design__io__post_repair": 264, - "cts__design__io__pre_repair": 264, - "cts__design__violations": 0, - "cts__mem__peak": 388564.0, - "cts__power__internal__total": 0.0145365, - "cts__power__internal__total__post_repair": 0.0139706, - "cts__power__internal__total__pre_repair": 0.0139706, - "cts__power__leakage__total": 2.51461e-08, - "cts__power__leakage__total__post_repair": 2.19657e-08, - "cts__power__leakage__total__pre_repair": 2.19657e-08, - "cts__power__switching__total": 0.0114302, - "cts__power__switching__total__post_repair": 0.0117987, - "cts__power__switching__total__pre_repair": 0.0117987, - "cts__power__total": 0.0259667, - "cts__power__total__post_repair": 0.0257694, - "cts__power__total__pre_repair": 0.0257694, - "cts__route__wirelength__estimated": 210449, - "cts__runtime__total": "1:03:02", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 1519, - "cts__timing__drv__hold_violation_count__pre_repair": 1519, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.948111, - "cts__timing__drv__max_cap_limit__post_repair": 0.950806, - "cts__timing__drv__max_cap_limit__pre_repair": 0.950806, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.174573, - "cts__timing__drv__max_slew_limit__post_repair": 0.099263, - "cts__timing__drv__max_slew_limit__pre_repair": 0.099263, - "cts__timing__drv__setup_violation_count": 1466, - "cts__timing__drv__setup_violation_count__post_repair": 1885, - "cts__timing__drv__setup_violation_count__pre_repair": 1885, - "cts__timing__setup__tns": -1063060.0, - "cts__timing__setup__tns__post_repair": -4370700.0, - "cts__timing__setup__tns__pre_repair": -4370700.0, - "cts__timing__setup__ws": -1222.14, - "cts__timing__setup__ws__post_repair": -3328.7, - "cts__timing__setup__ws__pre_repair": -3328.7, - "design__io__hpwl": 25387346, - "detailedplace__cpu__total": 15.19, - "detailedplace__design__core__area": 30384.5, - "detailedplace__design__die__area": 32000.6, - "detailedplace__design__instance__area": 12814.8, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 12814.8, - "detailedplace__design__instance__count": 15652, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 15652, - "detailedplace__design__instance__displacement__max": 10.7205, - "detailedplace__design__instance__displacement__mean": 0.8515, - "detailedplace__design__instance__displacement__total": 14154.2, - "detailedplace__design__instance__utilization": 0.421754, - "detailedplace__design__instance__utilization__stdcell": 0.421754, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 343232.0, - "detailedplace__power__internal__total": 0.0117098, - "detailedplace__power__leakage__total": 1.71146e-08, - "detailedplace__power__switching__total": 0.0113663, - "detailedplace__power__total": 0.0230761, - "detailedplace__route__wirelength__estimated": 158652, - "detailedplace__runtime__total": "0:17.13", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.950806, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0993076, - "detailedplace__timing__drv__setup_violation_count": 1884, - "detailedplace__timing__setup__tns": -3498730.0, - "detailedplace__timing__setup__ws": -2564.97, - "detailedroute__cpu__total": 4206.37, - "detailedroute__mem__peak": 4193372.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 20850, - "detailedroute__route__drc_errors__iter:10": 3, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 0, - "detailedroute__route__drc_errors__iter:2": 4415, - "detailedroute__route__drc_errors__iter:3": 4441, - "detailedroute__route__drc_errors__iter:4": 749, - "detailedroute__route__drc_errors__iter:5": 192, - "detailedroute__route__drc_errors__iter:6": 56, - "detailedroute__route__drc_errors__iter:7": 33, - "detailedroute__route__drc_errors__iter:8": 11, - "detailedroute__route__drc_errors__iter:9": 6, - "detailedroute__route__net": 18942, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 191014, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 191014, - "detailedroute__route__wirelength": 286864, - "detailedroute__route__wirelength__iter:1": 288019, - "detailedroute__route__wirelength__iter:10": 286868, - "detailedroute__route__wirelength__iter:11": 286871, - "detailedroute__route__wirelength__iter:12": 286864, - "detailedroute__route__wirelength__iter:2": 287508, - "detailedroute__route__wirelength__iter:3": 286987, - "detailedroute__route__wirelength__iter:4": 286904, - "detailedroute__route__wirelength__iter:5": 286860, - "detailedroute__route__wirelength__iter:6": 286885, - "detailedroute__route__wirelength__iter:7": 286897, - "detailedroute__route__wirelength__iter:8": 286878, - "detailedroute__route__wirelength__iter:9": 286873, - "detailedroute__runtime__total": "5:24.80", - "fillcell__cpu__total": 3.89, - "fillcell__mem__peak": 318028.0, - "fillcell__runtime__total": "0:04.40", - "finish__clock__skew__hold": 117.068, - "finish__clock__skew__setup": 114.705, - "finish__cpu__total": 66.77, - "finish__design__core__area": 30384.5, - "finish__design__die__area": 32000.6, - "finish__design__instance__area": 16665.4, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 16665.4, - "finish__design__instance__count": 18783, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 18783, - "finish__design__instance__utilization": 0.548485, - "finish__design__instance__utilization__stdcell": 0.548485, - "finish__design__io": 264, - "finish__mem__peak": 1428472.0, - "finish__power__internal__total": 0.0172813, - "finish__power__leakage__total": 2.7135e-08, - "finish__power__switching__total": 0.00863232, - "finish__power__total": 0.0259137, - "finish__runtime__total": "1:10.41", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.971739, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.854726, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 100.599, - "finish__timing__wns_percent_delay": 4.09039, - "finish_merge__cpu__total": 5.51, - "finish_merge__mem__peak": 446468.0, - "finish_merge__runtime__total": "0:06.37", - "floorplan__cpu__total": 8.21, - "floorplan__design__core__area": 30384.5, - "floorplan__design__die__area": 32000.6, - "floorplan__design__instance__area": 8719.39, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 8719.39, - "floorplan__design__instance__count": 15366, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 15366, - "floorplan__design__instance__utilization": 0.286969, - "floorplan__design__instance__utilization__stdcell": 0.286969, - "floorplan__design__io": 264, - "floorplan__mem__peak": 320160.0, - "floorplan__power__internal__total": 0.00562238, - "floorplan__power__leakage__total": 8.42549e-09, - "floorplan__power__switching__total": 0.00308991, - "floorplan__power__total": 0.0087123, - "floorplan__runtime__total": "0:09.42", - "floorplan__timing__setup__tns": -11524300.0, - "floorplan__timing__setup__ws": -8234.62, - "floorplan_io__cpu__total": 3.08, - "floorplan_io__mem__peak": 276084.0, - "floorplan_io__runtime__total": "0:03.47", - "floorplan_macro__cpu__total": 3.06, - "floorplan_macro__mem__peak": 278640.0, - "floorplan_macro__runtime__total": "0:03.42", - "floorplan_pdn__cpu__total": 3.38, - "floorplan_pdn__mem__peak": 285032.0, - "floorplan_pdn__runtime__total": "0:03.75", - "floorplan_tap__cpu__total": 3.08, - "floorplan_tap__mem__peak": 266208.0, - "floorplan_tap__runtime__total": "0:03.45", - "floorplan_tdms__cpu__total": 3.08, - "floorplan_tdms__mem__peak": 275324.0, - "floorplan_tdms__runtime__total": "0:03.44", - "globalplace__cpu__total": 1050.67, - "globalplace__design__core__area": 30384.5, - "globalplace__design__die__area": 32000.6, - "globalplace__design__instance__area": 8719.39, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 8719.39, - "globalplace__design__instance__count": 15366, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 15366, - "globalplace__design__instance__utilization": 0.286969, - "globalplace__design__instance__utilization__stdcell": 0.286969, - "globalplace__design__io": 264, - "globalplace__mem__peak": 527480.0, - "globalplace__power__internal__total": 0.00556774, - "globalplace__power__leakage__total": 8.42549e-09, - "globalplace__power__switching__total": 0.00746263, - "globalplace__power__total": 0.0130304, - "globalplace__runtime__total": "1:30.80", - "globalplace__timing__setup__tns": -37398800.0, - "globalplace__timing__setup__ws": -21995.9, - "globalplace_io__cpu__total": 3.13, - "globalplace_io__mem__peak": 278896.0, - "globalplace_io__runtime__total": "0:03.55", - "globalplace_skip_io__cpu__total": 6.64, - "globalplace_skip_io__mem__peak": 298180.0, - "globalplace_skip_io__runtime__total": "0:07.05", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 832.826, - "globalroute__clock__skew__setup": 832.826, - "globalroute__cpu__total": 908.37, - "globalroute__design__core__area": 30384.5, - "globalroute__design__die__area": 32000.6, - "globalroute__design__instance__area": 16665.4, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 16665.4, - "globalroute__design__instance__count": 18783, - "globalroute__design__instance__count__hold_buffer": 493, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 102, - "globalroute__design__instance__count__stdcell": 18783, - "globalroute__design__instance__displacement__max": 18.774, - "globalroute__design__instance__displacement__mean": 0.2835, - "globalroute__design__instance__displacement__total": 5605.99, - "globalroute__design__instance__utilization": 0.548485, - "globalroute__design__instance__utilization__stdcell": 0.548485, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 733844.0, - "globalroute__power__internal__total": 0.0164237, - "globalroute__power__leakage__total": 2.71569e-08, - "globalroute__power__switching__total": 0.0153213, - "globalroute__power__total": 0.0317451, - "globalroute__route__wirelength__estimated": 226316, - "globalroute__runtime__total": "16:00.43", - "globalroute__timing__clock__slack": -1505.278, - "globalroute__timing__drv__hold_violation_count": 1, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.934787, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.157349, - "globalroute__timing__drv__setup_violation_count": 1508, - "globalroute__timing__setup__tns": -1388860.0, - "globalroute__timing__setup__ws": -1505.28, - "placeopt__cpu__total": 17.97, - "placeopt__design__core__area": 30384.5, - "placeopt__design__core__area__pre_opt": 30384.5, - "placeopt__design__die__area": 32000.6, - "placeopt__design__die__area__pre_opt": 32000.6, - "placeopt__design__instance__area": 12814.8, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 8719.39, - "placeopt__design__instance__area__stdcell": 12814.8, - "placeopt__design__instance__area__stdcell__pre_opt": 8719.39, - "placeopt__design__instance__count": 15652, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 15366, - "placeopt__design__instance__count__stdcell": 15652, - "placeopt__design__instance__count__stdcell__pre_opt": 15366, - "placeopt__design__instance__utilization": 0.421754, - "placeopt__design__instance__utilization__pre_opt": 0.286969, - "placeopt__design__instance__utilization__stdcell": 0.421754, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.286969, - "placeopt__design__io": 264, - "placeopt__design__io__pre_opt": 264, - "placeopt__mem__peak": 357600.0, - "placeopt__power__internal__total": 0.0116363, - "placeopt__power__internal__total__pre_opt": 0.00556774, - "placeopt__power__leakage__total": 1.71475e-08, - "placeopt__power__leakage__total__pre_opt": 8.42549e-09, - "placeopt__power__switching__total": 0.0109954, - "placeopt__power__switching__total__pre_opt": 0.00746263, - "placeopt__power__total": 0.0226317, - "placeopt__power__total__pre_opt": 0.0130304, - "placeopt__runtime__total": "0:20.48", - "placeopt__timing__drv__floating__nets": 1, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.953357, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.097137, - "placeopt__timing__drv__setup_violation_count": 1881, - "placeopt__timing__setup__tns": -3447090.0, - "placeopt__timing__setup__tns__pre_opt": -37398800.0, - "placeopt__timing__setup__ws": -2548.95, - "placeopt__timing__setup__ws__pre_opt": -21995.9, - "run__flow__design": "ibex", - "run__flow__generate_date": "2023-12-05 19:40", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-11366-g7ca052e63", - "run__flow__platform": "intel22", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "87a252d686593183d85f3be0740a10cd6a6d1f1b", - "run__flow__scripts_commit": "3fb524c891360ae7b02ccd8237dd8764245475ef", - "run__flow__uuid": "b660bfcd-cafa-40e1-8174-0810ae26c453", - "run__flow__variant": "base", - "synth__cpu__total": 112.69, - "synth__design__instance__area__stdcell": 9175.67028, - "synth__design__instance__count__stdcell": 16702.0, - "synth__mem__peak": 374352.0, - "synth__runtime__total": "1:57.06", - "total_time": "1:30:31.430000" -} \ No newline at end of file diff --git a/flow/designs/intel22/ibex/rules-base.json b/flow/designs/intel22/ibex/rules-base.json deleted file mode 100644 index cf16378adc..0000000000 --- a/flow/designs/intel22/ibex/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 10552.03, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 14737, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 18000, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 1565, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 1565, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 310760, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -59.4, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 19165, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 783, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/intel22/jpeg/config.mk b/flow/designs/intel22/jpeg/config.mk deleted file mode 100644 index 246f63bb3f..0000000000 --- a/flow/designs/intel22/jpeg/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -DESIGN_DIR := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -DESIGN_PDK_HOME := $(realpath $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) - -export DESIGN_NICKNAME = jpeg -export DESIGN_NAME = jpeg_encoder -export PLATFORM = intel22 - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = $(DESIGN_DIR)/constraint.sdc - -export CORE_UTILIZATION = 30 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 - -export PLACE_DENSITY = uniform diff --git a/flow/designs/intel22/jpeg/constraint.sdc b/flow/designs/intel22/jpeg/constraint.sdc deleted file mode 100644 index 6200dad94c..0000000000 --- a/flow/designs/intel22/jpeg/constraint.sdc +++ /dev/null @@ -1,10 +0,0 @@ -current_design jpeg_encoder -set clk_name clk -set clk_period 4400 -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name $clk_name -period $clk_period [get_ports {clk}] -# -set_input_delay [expr $clk_period * 0.2] -clock $clk_name [all_inputs] -set_output_delay [expr $clk_period * 0.2] -clock $clk_name [all_outputs] diff --git a/flow/designs/intel22/jpeg/metadata-base-ok.json b/flow/designs/intel22/jpeg/metadata-base-ok.json deleted file mode 100644 index 47e93f0acb..0000000000 --- a/flow/designs/intel22/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,470 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 4400.0000" - ], - "cts__clock__skew__hold": 115.783, - "cts__clock__skew__hold__post_repair": 116.936, - "cts__clock__skew__hold__pre_repair": 116.936, - "cts__clock__skew__setup": 115.783, - "cts__clock__skew__setup__post_repair": 116.936, - "cts__clock__skew__setup__pre_repair": 116.936, - "cts__cpu__total": 191.13, - "cts__design__core__area": 120274, - "cts__design__core__area__post_repair": 120274, - "cts__design__core__area__pre_repair": 120274, - "cts__design__die__area": 123354, - "cts__design__die__area__post_repair": 123354, - "cts__design__die__area__pre_repair": 123354, - "cts__design__instance__area": 58597.6, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 58569.2, - "cts__design__instance__area__pre_repair": 58567.7, - "cts__design__instance__area__stdcell": 58597.6, - "cts__design__instance__area__stdcell__post_repair": 58569.2, - "cts__design__instance__area__stdcell__pre_repair": 58567.7, - "cts__design__instance__count": 68356, - "cts__design__instance__count__hold_buffer": 10, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 68328, - "cts__design__instance__count__pre_repair": 68327, - "cts__design__instance__count__setup_buffer": 18, - "cts__design__instance__count__stdcell": 68356, - "cts__design__instance__count__stdcell__post_repair": 68328, - "cts__design__instance__count__stdcell__pre_repair": 68327, - "cts__design__instance__displacement__max": 4.464, - "cts__design__instance__displacement__mean": 0.0015, - "cts__design__instance__displacement__total": 123.496, - "cts__design__instance__utilization": 0.4872, - "cts__design__instance__utilization__post_repair": 0.486963, - "cts__design__instance__utilization__pre_repair": 0.486951, - "cts__design__instance__utilization__stdcell": 0.4872, - "cts__design__instance__utilization__stdcell__post_repair": 0.486963, - "cts__design__instance__utilization__stdcell__pre_repair": 0.486951, - "cts__design__io": 47, - "cts__design__io__post_repair": 47, - "cts__design__io__pre_repair": 47, - "cts__design__violations": 0, - "cts__mem__peak": 932616.0, - "cts__power__internal__total": 0.0171821, - "cts__power__internal__total__post_repair": 0.0171834, - "cts__power__internal__total__pre_repair": 0.0171814, - "cts__power__leakage__total": 9.47258e-08, - "cts__power__leakage__total__post_repair": 9.46511e-08, - "cts__power__leakage__total__pre_repair": 9.46459e-08, - "cts__power__switching__total": 0.0130616, - "cts__power__switching__total__post_repair": 0.01291, - "cts__power__switching__total__pre_repair": 0.0129054, - "cts__power__total": 0.0302438, - "cts__power__total__post_repair": 0.0300934, - "cts__power__total__pre_repair": 0.0300868, - "cts__route__wirelength__estimated": 620136, - "cts__runtime__total": "3:17.86", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 39, - "cts__timing__drv__hold_violation_count__pre_repair": 43, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.926122, - "cts__timing__drv__max_cap_limit__post_repair": 0.924629, - "cts__timing__drv__max_cap_limit__pre_repair": 0.924629, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.426523, - "cts__timing__drv__max_slew_limit__post_repair": 0.204011, - "cts__timing__drv__max_slew_limit__pre_repair": 0.204011, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__drv__setup_violation_count__post_repair": 14, - "cts__timing__drv__setup_violation_count__pre_repair": 14, - "cts__timing__setup__tns": -0.981437, - "cts__timing__setup__tns__post_repair": -2201.9, - "cts__timing__setup__tns__pre_repair": -2201.9, - "cts__timing__setup__ws": -0.981437, - "cts__timing__setup__ws__post_repair": -325.905, - "cts__timing__setup__ws__pre_repair": -325.905, - "cts_fill__cpu__total": 4.14, - "cts_fill__mem__peak": 495592.0, - "cts_fill__runtime__total": "0:04.46", - "design__io__hpwl": 6071570, - "detailedplace__cpu__total": 60.14, - "detailedplace__design__core__area": 120274, - "detailedplace__design__die__area": 123354, - "detailedplace__design__instance__area": 58463.6, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 58463.6, - "detailedplace__design__instance__count": 68157, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 68157, - "detailedplace__design__instance__displacement__max": 15.006, - "detailedplace__design__instance__displacement__mean": 0.6525, - "detailedplace__design__instance__displacement__total": 46481.9, - "detailedplace__design__instance__utilization": 0.486085, - "detailedplace__design__instance__utilization__stdcell": 0.486085, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 649472.0, - "detailedplace__power__internal__total": 0.0171302, - "detailedplace__power__leakage__total": 9.44223e-08, - "detailedplace__power__switching__total": 0.0123823, - "detailedplace__power__total": 0.0295126, - "detailedplace__route__wirelength__estimated": 620831, - "detailedplace__runtime__total": "1:03.76", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.924629, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.204109, - "detailedplace__timing__drv__setup_violation_count": 22, - "detailedplace__timing__setup__tns": -3048.9, - "detailedplace__timing__setup__ws": -339.573, - "detailedroute__cpu__total": 5974.03, - "detailedroute__mem__peak": 16893832.0, - "detailedroute__route__drc_errors": 1, - "detailedroute__route__drc_errors__iter:1": 62537, - "detailedroute__route__drc_errors__iter:10": 12, - "detailedroute__route__drc_errors__iter:11": 5, - "detailedroute__route__drc_errors__iter:12": 2, - "detailedroute__route__drc_errors__iter:13": 2, - "detailedroute__route__drc_errors__iter:14": 2, - "detailedroute__route__drc_errors__iter:15": 2, - "detailedroute__route__drc_errors__iter:16": 2, - "detailedroute__route__drc_errors__iter:17": 2, - "detailedroute__route__drc_errors__iter:18": 11, - "detailedroute__route__drc_errors__iter:19": 1, - "detailedroute__route__drc_errors__iter:2": 14722, - "detailedroute__route__drc_errors__iter:20": 1, - "detailedroute__route__drc_errors__iter:21": 1, - "detailedroute__route__drc_errors__iter:22": 1, - "detailedroute__route__drc_errors__iter:23": 1, - "detailedroute__route__drc_errors__iter:24": 1, - "detailedroute__route__drc_errors__iter:25": 1, - "detailedroute__route__drc_errors__iter:26": 4, - "detailedroute__route__drc_errors__iter:27": 1, - "detailedroute__route__drc_errors__iter:28": 1, - "detailedroute__route__drc_errors__iter:29": 1, - "detailedroute__route__drc_errors__iter:3": 14347, - "detailedroute__route__drc_errors__iter:30": 1, - "detailedroute__route__drc_errors__iter:31": 1, - "detailedroute__route__drc_errors__iter:32": 1, - "detailedroute__route__drc_errors__iter:33": 1, - "detailedroute__route__drc_errors__iter:34": 3, - "detailedroute__route__drc_errors__iter:35": 1, - "detailedroute__route__drc_errors__iter:36": 1, - "detailedroute__route__drc_errors__iter:37": 1, - "detailedroute__route__drc_errors__iter:38": 1, - "detailedroute__route__drc_errors__iter:39": 1, - "detailedroute__route__drc_errors__iter:4": 2471, - "detailedroute__route__drc_errors__iter:40": 1, - "detailedroute__route__drc_errors__iter:41": 1, - "detailedroute__route__drc_errors__iter:42": 1, - "detailedroute__route__drc_errors__iter:43": 1, - "detailedroute__route__drc_errors__iter:44": 1, - "detailedroute__route__drc_errors__iter:45": 1, - "detailedroute__route__drc_errors__iter:46": 1, - "detailedroute__route__drc_errors__iter:47": 1, - "detailedroute__route__drc_errors__iter:48": 1, - "detailedroute__route__drc_errors__iter:49": 1, - "detailedroute__route__drc_errors__iter:5": 552, - "detailedroute__route__drc_errors__iter:50": 6, - "detailedroute__route__drc_errors__iter:51": 1, - "detailedroute__route__drc_errors__iter:52": 1, - "detailedroute__route__drc_errors__iter:53": 1, - "detailedroute__route__drc_errors__iter:54": 1, - "detailedroute__route__drc_errors__iter:55": 1, - "detailedroute__route__drc_errors__iter:56": 1, - "detailedroute__route__drc_errors__iter:57": 1, - "detailedroute__route__drc_errors__iter:58": 7, - "detailedroute__route__drc_errors__iter:59": 1, - "detailedroute__route__drc_errors__iter:6": 160, - "detailedroute__route__drc_errors__iter:60": 1, - "detailedroute__route__drc_errors__iter:61": 1, - "detailedroute__route__drc_errors__iter:62": 1, - "detailedroute__route__drc_errors__iter:63": 1, - "detailedroute__route__drc_errors__iter:64": 1, - "detailedroute__route__drc_errors__iter:65": 1, - "detailedroute__route__drc_errors__iter:7": 54, - "detailedroute__route__drc_errors__iter:8": 26, - "detailedroute__route__drc_errors__iter:9": 18, - "detailedroute__route__net": 68376, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 618890, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 618890, - "detailedroute__route__wirelength": 766288, - "detailedroute__route__wirelength__iter:1": 770185, - "detailedroute__route__wirelength__iter:10": 766262, - "detailedroute__route__wirelength__iter:11": 766265, - "detailedroute__route__wirelength__iter:12": 766267, - "detailedroute__route__wirelength__iter:13": 766267, - "detailedroute__route__wirelength__iter:14": 766267, - "detailedroute__route__wirelength__iter:15": 766267, - "detailedroute__route__wirelength__iter:16": 766267, - "detailedroute__route__wirelength__iter:17": 766267, - "detailedroute__route__wirelength__iter:18": 766278, - "detailedroute__route__wirelength__iter:19": 766278, - "detailedroute__route__wirelength__iter:2": 768597, - "detailedroute__route__wirelength__iter:20": 766278, - "detailedroute__route__wirelength__iter:21": 766278, - "detailedroute__route__wirelength__iter:22": 766278, - "detailedroute__route__wirelength__iter:23": 766278, - "detailedroute__route__wirelength__iter:24": 766278, - "detailedroute__route__wirelength__iter:25": 766278, - "detailedroute__route__wirelength__iter:26": 766280, - "detailedroute__route__wirelength__iter:27": 766280, - "detailedroute__route__wirelength__iter:28": 766280, - "detailedroute__route__wirelength__iter:29": 766280, - "detailedroute__route__wirelength__iter:3": 766302, - "detailedroute__route__wirelength__iter:30": 766280, - "detailedroute__route__wirelength__iter:31": 766280, - "detailedroute__route__wirelength__iter:32": 766280, - "detailedroute__route__wirelength__iter:33": 766280, - "detailedroute__route__wirelength__iter:34": 766283, - "detailedroute__route__wirelength__iter:35": 766284, - "detailedroute__route__wirelength__iter:36": 766283, - "detailedroute__route__wirelength__iter:37": 766284, - "detailedroute__route__wirelength__iter:38": 766283, - "detailedroute__route__wirelength__iter:39": 766284, - "detailedroute__route__wirelength__iter:4": 766545, - "detailedroute__route__wirelength__iter:40": 766283, - "detailedroute__route__wirelength__iter:41": 766284, - "detailedroute__route__wirelength__iter:42": 766284, - "detailedroute__route__wirelength__iter:43": 766283, - "detailedroute__route__wirelength__iter:44": 766284, - "detailedroute__route__wirelength__iter:45": 766283, - "detailedroute__route__wirelength__iter:46": 766284, - "detailedroute__route__wirelength__iter:47": 766283, - "detailedroute__route__wirelength__iter:48": 766284, - "detailedroute__route__wirelength__iter:49": 766283, - "detailedroute__route__wirelength__iter:5": 766372, - "detailedroute__route__wirelength__iter:50": 766289, - "detailedroute__route__wirelength__iter:51": 766289, - "detailedroute__route__wirelength__iter:52": 766289, - "detailedroute__route__wirelength__iter:53": 766289, - "detailedroute__route__wirelength__iter:54": 766289, - "detailedroute__route__wirelength__iter:55": 766289, - "detailedroute__route__wirelength__iter:56": 766289, - "detailedroute__route__wirelength__iter:57": 766289, - "detailedroute__route__wirelength__iter:58": 766288, - "detailedroute__route__wirelength__iter:59": 766288, - "detailedroute__route__wirelength__iter:6": 766308, - "detailedroute__route__wirelength__iter:60": 766288, - "detailedroute__route__wirelength__iter:61": 766288, - "detailedroute__route__wirelength__iter:62": 766288, - "detailedroute__route__wirelength__iter:63": 766288, - "detailedroute__route__wirelength__iter:64": 766288, - "detailedroute__route__wirelength__iter:65": 766288, - "detailedroute__route__wirelength__iter:7": 766278, - "detailedroute__route__wirelength__iter:8": 766272, - "detailedroute__route__wirelength__iter:9": 766267, - "detailedroute__runtime__total": "7:30.01", - "finish__clock__skew__hold": 28.7374, - "finish__clock__skew__setup": 25.885, - "finish__cpu__total": 38.41, - "finish__design__core__area": 120274, - "finish__design__die__area": 123354, - "finish__design__instance__area": 58597.6, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 58597.6, - "finish__design__instance__count": 68356, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 68356, - "finish__design__instance__utilization": 0.4872, - "finish__design__instance__utilization__stdcell": 0.4872, - "finish__design__io": 47, - "finish__mem__peak": 1088284.0, - "finish__power__internal__total": 0.0172552, - "finish__power__leakage__total": 9.47258e-08, - "finish__power__switching__total": 0.00843592, - "finish__power__total": 0.0256913, - "finish__runtime__total": "0:40.77", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.95523, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.609761, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 1977.91, - "finish__timing__wns_percent_delay": 75.310877, - "finish_merge__cpu__total": 9.63, - "finish_merge__mem__peak": 1057724.0, - "finish_merge__runtime__total": "0:11.07", - "floorplan__cpu__total": 21.31, - "floorplan__design__core__area": 120274, - "floorplan__design__die__area": 123354, - "floorplan__design__instance__area": 34580.3, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 34580.3, - "floorplan__design__instance__count": 67458, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 67458, - "floorplan__design__instance__utilization": 0.287512, - "floorplan__design__instance__utilization__stdcell": 0.287512, - "floorplan__design__io": 47, - "floorplan__mem__peak": 548444.0, - "floorplan__power__internal__total": 0.00859222, - "floorplan__power__leakage__total": 3.59301e-08, - "floorplan__power__switching__total": 0.00415397, - "floorplan__power__total": 0.0127462, - "floorplan__runtime__total": "0:22.29", - "floorplan__timing__setup__tns": -82032600.0, - "floorplan__timing__setup__ws": -36881.6, - "floorplan_io__cpu__total": 3.68, - "floorplan_io__mem__peak": 387152.0, - "floorplan_io__runtime__total": "0:03.92", - "floorplan_macro__cpu__total": 3.57, - "floorplan_macro__mem__peak": 384856.0, - "floorplan_macro__runtime__total": "0:03.81", - "floorplan_pdn__cpu__total": 4.74, - "floorplan_pdn__mem__peak": 412216.0, - "floorplan_pdn__runtime__total": "0:05.00", - "floorplan_tap__cpu__total": 3.55, - "floorplan_tap__mem__peak": 336832.0, - "floorplan_tap__runtime__total": "0:04.12", - "floorplan_tdms__cpu__total": 3.72, - "floorplan_tdms__mem__peak": 385304.0, - "floorplan_tdms__runtime__total": "0:03.94", - "globalplace__cpu__total": 287.92, - "globalplace__design__core__area": 120274, - "globalplace__design__die__area": 123354, - "globalplace__design__instance__area": 34580.3, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 34580.3, - "globalplace__design__instance__count": 67458, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 67458, - "globalplace__design__instance__utilization": 0.287512, - "globalplace__design__instance__utilization__stdcell": 0.287512, - "globalplace__design__io": 47, - "globalplace__mem__peak": 1061428.0, - "globalplace__power__internal__total": 0.00849452, - "globalplace__power__leakage__total": 3.59301e-08, - "globalplace__power__switching__total": 0.00804642, - "globalplace__power__total": 0.016541, - "globalplace__runtime__total": "4:59.59", - "globalplace__timing__setup__tns": -645895000.0, - "globalplace__timing__setup__ws": -253705, - "globalplace_io__cpu__total": 3.64, - "globalplace_io__mem__peak": 397136.0, - "globalplace_io__runtime__total": "0:04.06", - "globalplace_skip_io__cpu__total": 31.88, - "globalplace_skip_io__mem__peak": 479452.0, - "globalplace_skip_io__runtime__total": "0:33.29", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 117.612, - "globalroute__clock__skew__setup": 117.612, - "globalroute__cpu__total": 53.66, - "globalroute__design__core__area": 120274, - "globalroute__design__die__area": 123354, - "globalroute__design__instance__area": 58597.6, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 58597.6, - "globalroute__design__instance__count": 68356, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 68356, - "globalroute__design__instance__utilization": 0.4872, - "globalroute__design__instance__utilization__stdcell": 0.4872, - "globalroute__design__io": 47, - "globalroute__mem__peak": 1470832.0, - "globalroute__power__internal__total": 0.0171648, - "globalroute__power__leakage__total": 9.47258e-08, - "globalroute__power__switching__total": 0.0145297, - "globalroute__power__total": 0.0316946, - "globalroute__runtime__total": "0:54.80", - "globalroute__timing__clock__slack": -354.116, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.918295, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.165189, - "globalroute__timing__drv__setup_violation_count": 28, - "globalroute__timing__setup__tns": -4167.18, - "globalroute__timing__setup__ws": -354.116, - "placeopt__cpu__total": 66.7, - "placeopt__design__core__area": 120274, - "placeopt__design__core__area__pre_opt": 120274, - "placeopt__design__die__area": 123354, - "placeopt__design__die__area__pre_opt": 123354, - "placeopt__design__instance__area": 58463.6, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 34580.3, - "placeopt__design__instance__area__stdcell": 58463.6, - "placeopt__design__instance__area__stdcell__pre_opt": 34580.3, - "placeopt__design__instance__count": 68157, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 67458, - "placeopt__design__instance__count__stdcell": 68157, - "placeopt__design__instance__count__stdcell__pre_opt": 67458, - "placeopt__design__instance__utilization": 0.486085, - "placeopt__design__instance__utilization__pre_opt": 0.287512, - "placeopt__design__instance__utilization__stdcell": 0.486085, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.287512, - "placeopt__design__io": 47, - "placeopt__design__io__pre_opt": 47, - "placeopt__mem__peak": 647936.0, - "placeopt__power__internal__total": 0.0170632, - "placeopt__power__internal__total__pre_opt": 0.00849452, - "placeopt__power__leakage__total": 9.44223e-08, - "placeopt__power__leakage__total__pre_opt": 3.59301e-08, - "placeopt__power__switching__total": 0.0120937, - "placeopt__power__switching__total__pre_opt": 0.00804642, - "placeopt__power__total": 0.0291571, - "placeopt__power__total__pre_opt": 0.016541, - "placeopt__runtime__total": "1:12.46", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.947895, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.426442, - "placeopt__timing__drv__setup_violation_count": 21, - "placeopt__timing__setup__tns": -3443.3, - "placeopt__timing__setup__tns__pre_opt": -645895000.0, - "placeopt__timing__setup__ws": -337.657, - "placeopt__timing__setup__ws__pre_opt": -253705, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2023-07-21 21:04", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9420-ga5589e9a6", - "run__flow__platform": "intel22", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1ohm", - "run__flow__platform__time_units": "1ps", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0003c5b3f06a27584094a32eef82bb97f1650981", - "run__flow__scripts_commit": "9d06582cfb3a4b75ef0d826dfd8a156b73d96f2c", - "run__flow__uuid": "ddc0f323-5667-43c1-96a4-f0b56fb8db29", - "run__flow__variant": "base", - "synth__cpu__total": 305.84, - "synth__design__instance__area__stdcell": 36168.29496, - "synth__design__instance__count__stdcell": 72257.0, - "synth__mem__peak": 891072.0, - "synth__runtime__total": "5:13.81", - "total_time": "0:26:29.020000" -} \ No newline at end of file diff --git a/flow/designs/intel22/jpeg/rules-base.json b/flow/designs/intel22/jpeg/rules-base.json deleted file mode 100644 index 9384dfd273..0000000000 --- a/flow/designs/intel22/jpeg/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 41593.54, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 67233, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 78381, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 6816, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 6816, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 881231, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 1, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 67387, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 3408, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/nangate45/aes/config.mk b/flow/designs/nangate45/aes/config.mk index f653445292..7008a46a9f 100644 --- a/flow/designs/nangate45/aes/config.mk +++ b/flow/designs/nangate45/aes/config.mk @@ -11,3 +11,5 @@ export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 export REMOVE_CELLS_FOR_EQY = TAPCELL* +# workaround for high congestion in post-grt repair +export SKIP_INCREMENTAL_REPAIR = 1 diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc index 6bf0879d5b..95f709e341 100644 --- a/flow/designs/nangate45/aes/constraint.sdc +++ b/flow/designs/nangate45/aes/constraint.sdc @@ -1,15 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 0.82 +set clk_period 0.82 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/aes/metadata-base-ok.json b/flow/designs/nangate45/aes/metadata-base-ok.json deleted file mode 100644 index b585ad571d..0000000000 --- a/flow/designs/nangate45/aes/metadata-base-ok.json +++ /dev/null @@ -1,320 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 0.8200" - ], - "cts__clock__skew__hold": 0.0154092, - "cts__clock__skew__setup": 0.0154092, - "cts__cpu__total": 226.68, - "cts__design__core__area": 52785, - "cts__design__die__area": 62612.4, - "cts__design__instance__area": 25936.6, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 25936.6, - "cts__design__instance__count": 16483, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 373, - "cts__design__instance__count__stdcell": 16483, - "cts__design__instance__displacement__max": 7.03, - "cts__design__instance__displacement__mean": 0.2115, - "cts__design__instance__displacement__total": 3486.54, - "cts__design__instance__utilization": 0.491363, - "cts__design__instance__utilization__stdcell": 0.491363, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 483464.0, - "cts__power__internal__total": 0.219156, - "cts__power__leakage__total": 0.0007031, - "cts__power__switching__total": 0.211961, - "cts__power__total": 0.431819, - "cts__route__wirelength__estimated": 237764, - "cts__runtime__total": "3:48.69", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.318432, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.482368, - "cts__timing__drv__setup_violation_count": 148, - "cts__timing__setup__tns": -6.14391, - "cts__timing__setup__ws": -0.0971889, - "design__violations": 0, - "detailedplace__cpu__total": 14.29, - "detailedplace__design__core__area": 52785, - "detailedplace__design__die__area": 62612.4, - "detailedplace__design__instance__area": 23963.9, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 23963.9, - "detailedplace__design__instance__count": 15860, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 15860, - "detailedplace__design__instance__displacement__max": 5, - "detailedplace__design__instance__displacement__mean": 0.8165, - "detailedplace__design__instance__displacement__total": 12951.3, - "detailedplace__design__instance__utilization": 0.453991, - "detailedplace__design__instance__utilization__stdcell": 0.453991, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 202504.0, - "detailedplace__power__internal__total": 0.194049, - "detailedplace__power__leakage__total": 0.000624549, - "detailedplace__power__switching__total": 0.195929, - "detailedplace__power__total": 0.390603, - "detailedplace__route__wirelength__estimated": 242635, - "detailedplace__runtime__total": "0:14.43", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0693154, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.41122, - "detailedplace__timing__drv__setup_violation_count": 160, - "detailedplace__timing__setup__tns": -18.0158, - "detailedplace__timing__setup__ws": -0.19702, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 6990, - "detailedroute__route__drc_errors__iter:2": 3743, - "detailedroute__route__drc_errors__iter:3": 3311, - "detailedroute__route__drc_errors__iter:4": 506, - "detailedroute__route__drc_errors__iter:5": 33, - "detailedroute__route__drc_errors__iter:6": 26, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 17191, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 151438, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 151438, - "detailedroute__route__wirelength": 305241, - "detailedroute__route__wirelength__iter:1": 307576, - "detailedroute__route__wirelength__iter:2": 305480, - "detailedroute__route__wirelength__iter:3": 304931, - "detailedroute__route__wirelength__iter:4": 305237, - "detailedroute__route__wirelength__iter:5": 305246, - "detailedroute__route__wirelength__iter:6": 305245, - "detailedroute__route__wirelength__iter:7": 305239, - "detailedroute__route__wirelength__iter:8": 305239, - "detailedroute__route__wirelength__iter:9": 305241, - "finish__clock__skew__hold": 0.0233596, - "finish__clock__skew__setup": 0.0233596, - "finish__cpu__total": 27.32, - "finish__design__core__area": 52785, - "finish__design__die__area": 62612.4, - "finish__design__instance__area": 26776.6, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 26776.6, - "finish__design__instance__count": 16599, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 16599, - "finish__design__instance__utilization": 0.507277, - "finish__design__instance__utilization__stdcell": 0.507277, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": -0.0962, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.732419, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 2.34915, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 1.5644, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": -1.24915, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 1.5644, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 624508.0, - "finish__power__internal__total": 0.231183, - "finish__power__leakage__total": 0.000739257, - "finish__power__switching__total": 0.241523, - "finish__power__total": 0.473445, - "finish__runtime__total": "0:27.79", - "finish__timing__drv__hold_violation_count": 11, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.150494, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.411317, - "finish__timing__drv__setup_violation_count": 155, - "finish__timing__setup__tns": -7.37586, - "finish__timing__setup__ws": -0.1092, - "finish__timing__wns_percent_delay": -9.969871, - "finish_merge__cpu__total": 2.38, - "finish_merge__mem__peak": 509396.0, - "finish_merge__runtime__total": "0:02.65", - "floorplan__cpu__total": 85.7, - "floorplan__design__core__area": 52785, - "floorplan__design__die__area": 62612.4, - "floorplan__design__instance__area": 21373.9, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 21373.9, - "floorplan__design__instance__count": 15062, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 16, - "floorplan__design__instance__count__stdcell": 15062, - "floorplan__design__instance__utilization": 0.404923, - "floorplan__design__instance__utilization__stdcell": 0.404923, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 7788, - "floorplan__mem__peak": 183188.0, - "floorplan__power__internal__total": 0.17307, - "floorplan__power__leakage__total": 0.000546212, - "floorplan__power__switching__total": 0.138502, - "floorplan__power__total": 0.312118, - "floorplan__runtime__total": "1:25.79", - "floorplan__timing__setup__tns": -1.66785, - "floorplan__timing__setup__ws": -0.0653671, - "floorplan_io__cpu__total": 0.27, - "floorplan_io__mem__peak": 133172.0, - "floorplan_io__runtime__total": "0:00.35", - "floorplan_macro__cpu__total": 0.32, - "floorplan_macro__mem__peak": 141752.0, - "floorplan_macro__runtime__total": "0:00.38", - "floorplan_pdn__cpu__total": 0.36, - "floorplan_pdn__mem__peak": 145288.0, - "floorplan_pdn__runtime__total": "0:00.45", - "floorplan_tap__cpu__total": 0.29, - "floorplan_tap__mem__peak": 134044.0, - "floorplan_tap__runtime__total": "0:00.37", - "floorplan_tdms__cpu__total": 0.31, - "floorplan_tdms__mem__peak": 142360.0, - "floorplan_tdms__runtime__total": "0:00.38", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1962.15, - "globalplace__design__core__area": 52785, - "globalplace__design__die__area": 62612.4, - "globalplace__design__instance__area": 21483.2, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 21483.2, - "globalplace__design__instance__count": 15473, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 15473, - "globalplace__design__instance__utilization": 0.406995, - "globalplace__design__instance__utilization__stdcell": 0.406995, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 536600.0, - "globalplace__power__internal__total": 0.175289, - "globalplace__power__leakage__total": 0.000546212, - "globalplace__power__switching__total": 0.183911, - "globalplace__power__total": 0.359745, - "globalplace__runtime__total": "3:06.81", - "globalplace__timing__setup__tns": -18.1437, - "globalplace__timing__setup__ws": -0.175039, - "globalplace_io__cpu__total": 0.26, - "globalplace_io__mem__peak": 133916.0, - "globalplace_io__runtime__total": "0:00.36", - "globalplace_skip_io__cpu__total": 0.28, - "globalplace_skip_io__mem__peak": 133536.0, - "globalplace_skip_io__runtime__total": "0:00.37", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.0196884, - "globalroute__clock__skew__setup": 0.0196884, - "globalroute__cpu__total": 237.76, - "globalroute__design__core__area": 52785, - "globalroute__design__die__area": 62612.4, - "globalroute__design__instance__area": 26776.6, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 26776.6, - "globalroute__design__instance__count": 16599, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 112, - "globalroute__design__instance__count__stdcell": 16599, - "globalroute__design__instance__displacement__max": 6.74, - "globalroute__design__instance__displacement__mean": 0.176, - "globalroute__design__instance__displacement__total": 2925.61, - "globalroute__design__instance__utilization": 0.507277, - "globalroute__design__instance__utilization__stdcell": 0.507277, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 658688.0, - "globalroute__power__internal__total": 0.230821, - "globalroute__power__leakage__total": 0.000739257, - "globalroute__power__switching__total": 0.232367, - "globalroute__power__total": 0.463926, - "globalroute__route__wirelength__estimated": 242499, - "globalroute__runtime__total": "3:49.29", - "globalroute__timing__clock__slack": -0.113, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.187502, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.426886, - "globalroute__timing__drv__setup_violation_count": 151, - "globalroute__timing__setup__tns": -6.75298, - "globalroute__timing__setup__ws": -0.113338, - "placeopt__cpu__total": 11.68, - "placeopt__design__core__area": 52785, - "placeopt__design__die__area": 62612.4, - "placeopt__design__instance__area": 23963.9, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 23963.9, - "placeopt__design__instance__count": 15860, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 15860, - "placeopt__design__instance__utilization": 0.453991, - "placeopt__design__instance__utilization__stdcell": 0.453991, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 380764.0, - "placeopt__power__internal__total": 0.194155, - "placeopt__power__leakage__total": 0.000624549, - "placeopt__power__switching__total": 0.198726, - "placeopt__power__total": 0.393506, - "placeopt__runtime__total": "0:11.93", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.063172, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.408261, - "placeopt__timing__drv__setup_violation_count": 160, - "placeopt__timing__setup__tns": -18.3859, - "placeopt__timing__setup__ws": -0.196996, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "9dbfdd6d-e23c-4562-a5f7-cd7dd30a9007", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 34.51, - "synth__design__instance__area__stdcell": 20437.312, - "synth__design__instance__count__stdcell": 15057.0, - "synth__mem__peak": 134492.0, - "synth__runtime__total": "0:34.71", - "total_time": "0:13:44.750000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/aes/rules-base.json b/flow/designs/nangate45/aes/rules-base.json index 66e482bb06..65c5fac049 100644 --- a/flow/designs/nangate45/aes/rules-base.json +++ b/flow/designs/nangate45/aes/rules-base.json @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 27558, + "value": 26514, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 351027, + "value": 298800, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.15, + "value": -0.06, "compare": ">=" }, "finish__design__instance__area": { - "value": 30793, + "value": 27064, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,11 +60,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 114, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.96, + "value": -13.22, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk index 6790881b88..1de1c20457 100644 --- a/flow/designs/nangate45/ariane133/config.mk +++ b/flow/designs/nangate45/ariane133/config.mk @@ -4,12 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 16 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v @@ -21,9 +15,9 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x16.lib export DIE_AREA = 0 0 1500 1500 export CORE_AREA = 10 12 1448 1448 -export PLACE_PINS_ARGS = -exclude left:0-500 -exclude left:1000-1500: -exclude right:* -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 + export TNS_END_PERCENT = 100 export SKIP_GATE_CLONING = 1 diff --git a/flow/designs/nangate45/ariane133/io.tcl b/flow/designs/nangate45/ariane133/io.tcl new file mode 100644 index 0000000000..cf94350a6c --- /dev/null +++ b/flow/designs/nangate45/ariane133/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:0-500 -region left:1000-1500: -region right:* \ + -region top:* -region bottom:* diff --git a/flow/designs/nangate45/ariane133/metadata-base-ok.json b/flow/designs/nangate45/ariane133/metadata-base-ok.json deleted file mode 100644 index c3a3d790e6..0000000000 --- a/flow/designs/nangate45/ariane133/metadata-base-ok.json +++ /dev/null @@ -1,295 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 4.0000" - ], - "cts__clock__skew__hold": 0.183879, - "cts__clock__skew__hold__post_repair": 0.184758, - "cts__clock__skew__hold__pre_repair": 0.184759, - "cts__clock__skew__setup": 2.37032, - "cts__clock__skew__setup__post_repair": 2.3659, - "cts__clock__skew__setup__pre_repair": 2.3659, - "cts__design__core__area": 2063420.0, - "cts__design__core__area__post_repair": 2063420.0, - "cts__design__core__area__pre_repair": 2063420.0, - "cts__design__die__area": 2250000.0, - "cts__design__die__area__post_repair": 2250000.0, - "cts__design__die__area__pre_repair": 2250000.0, - "cts__design__instance__area": 761195, - "cts__design__instance__area__macros": 416463, - "cts__design__instance__area__macros__post_repair": 416463, - "cts__design__instance__area__macros__pre_repair": 416463, - "cts__design__instance__area__post_repair": 760575, - "cts__design__instance__area__pre_repair": 760572, - "cts__design__instance__area__stdcell": 344732, - "cts__design__instance__area__stdcell__post_repair": 344112, - "cts__design__instance__area__stdcell__pre_repair": 344109, - "cts__design__instance__count": 167929, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 132, - "cts__design__instance__count__macros__post_repair": 132, - "cts__design__instance__count__macros__pre_repair": 132, - "cts__design__instance__count__post_repair": 167726, - "cts__design__instance__count__pre_repair": 167725, - "cts__design__instance__count__setup_buffer": 203.0, - "cts__design__instance__count__stdcell": 167797, - "cts__design__instance__count__stdcell__post_repair": 167594, - "cts__design__instance__count__stdcell__pre_repair": 167593, - "cts__design__instance__displacement__max": 8.64, - "cts__design__instance__displacement__mean": 0.0045, - "cts__design__instance__displacement__total": 824.376, - "cts__design__instance__utilization": 0.368901, - "cts__design__instance__utilization__post_repair": 0.3686, - "cts__design__instance__utilization__pre_repair": 0.368599, - "cts__design__instance__utilization__stdcell": 0.209315, - "cts__design__instance__utilization__stdcell__post_repair": 0.208939, - "cts__design__instance__utilization__stdcell__pre_repair": 0.208937, - "cts__design__io": 495, - "cts__design__io__post_repair": 495, - "cts__design__io__pre_repair": 495, - "cts__design__violations": 0, - "cts__route__wirelength__estimated": 5188200.0, - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 16, - "cts__timing__drv__max_cap__post_repair": 13, - "cts__timing__drv__max_cap__pre_repair": 13, - "cts__timing__drv__max_cap_limit": -0.169462, - "cts__timing__drv__max_cap_limit__post_repair": -0.168843, - "cts__timing__drv__max_cap_limit__pre_repair": -0.168843, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 1e+30, - "cts__timing__drv__max_fanout_limit__post_repair": 1e+30, - "cts__timing__drv__max_fanout_limit__pre_repair": 1e+30, - "cts__timing__drv__max_slew": 1, - "cts__timing__drv__max_slew__post_repair": 1, - "cts__timing__drv__max_slew__pre_repair": 1, - "cts__timing__drv__max_slew_limit": -0.0439935, - "cts__timing__drv__max_slew_limit__post_repair": -0.0438745, - "cts__timing__drv__max_slew_limit__pre_repair": -0.0438745, - "cts__timing__drv__setup_violation_count": 2068, - "cts__timing__drv__setup_violation_count__post_repair": 3457, - "cts__timing__drv__setup_violation_count__pre_repair": 3457, - "cts__timing__setup__tns": -422.505, - "cts__timing__setup__tns__post_repair": -3519.76, - "cts__timing__setup__tns__pre_repair": -3519.76, - "cts__timing__setup__ws": -0.308871, - "cts__timing__setup__ws__post_repair": -1.40629, - "cts__timing__setup__ws__pre_repair": -1.40629, - "detailedplace__cpu__total": 102.89, - "detailedplace__design__core__area": 2063420.0, - "detailedplace__design__die__area": 2250000.0, - "detailedplace__design__instance__area": 758900, - "detailedplace__design__instance__area__macros": 416463, - "detailedplace__design__instance__area__stdcell": 342436, - "detailedplace__design__instance__count": 166827, - "detailedplace__design__instance__count__macros": 132, - "detailedplace__design__instance__count__stdcell": 166695, - "detailedplace__design__instance__displacement__max": 30.383, - "detailedplace__design__instance__displacement__mean": 0.846, - "detailedplace__design__instance__displacement__total": 141177, - "detailedplace__design__instance__utilization": 0.367788, - "detailedplace__design__instance__utilization__stdcell": 0.207921, - "detailedplace__design__io": 495, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 1407472.0, - "detailedplace__route__wirelength__estimated": 5154160.0, - "detailedplace__runtime__total": "1:45.35", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 13, - "detailedplace__timing__drv__max_cap_limit": -0.168843, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 1e+30, - "detailedplace__timing__drv__max_slew": 1, - "detailedplace__timing__drv__max_slew_limit": -0.0437961, - "detailedplace__timing__drv__setup_violation_count": 3456, - "detailedplace__timing__setup__tns": -3474.26, - "detailedplace__timing__setup__ws": -1.39689, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 86093, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 1, - "detailedroute__route__drc_errors__iter:13": 1, - "detailedroute__route__drc_errors__iter:14": 1, - "detailedroute__route__drc_errors__iter:15": 1, - "detailedroute__route__drc_errors__iter:16": 0, - "detailedroute__route__drc_errors__iter:2": 7597, - "detailedroute__route__drc_errors__iter:3": 5026, - "detailedroute__route__drc_errors__iter:4": 176, - "detailedroute__route__drc_errors__iter:5": 1, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 184015, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1305689, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1305689, - "detailedroute__route__wirelength": 6466033, - "detailedroute__route__wirelength__iter:1": 6487648, - "detailedroute__route__wirelength__iter:10": 6466030, - "detailedroute__route__wirelength__iter:11": 6466030, - "detailedroute__route__wirelength__iter:12": 6466030, - "detailedroute__route__wirelength__iter:13": 6466030, - "detailedroute__route__wirelength__iter:14": 6466030, - "detailedroute__route__wirelength__iter:15": 6466030, - "detailedroute__route__wirelength__iter:16": 6466033, - "detailedroute__route__wirelength__iter:2": 6468887, - "detailedroute__route__wirelength__iter:3": 6465656, - "detailedroute__route__wirelength__iter:4": 6466015, - "detailedroute__route__wirelength__iter:5": 6466030, - "detailedroute__route__wirelength__iter:6": 6466030, - "detailedroute__route__wirelength__iter:7": 6466030, - "detailedroute__route__wirelength__iter:8": 6466030, - "detailedroute__route__wirelength__iter:9": 6466030, - "finish__clock__skew__hold": 0.179836, - "finish__clock__skew__setup": 2.40185, - "finish__cpu__total": 803.65, - "finish__design__core__area": 2063420.0, - "finish__design__die__area": 2250000.0, - "finish__design__instance__area": 761195, - "finish__design__instance__area__macros": 416463, - "finish__design__instance__area__stdcell": 344732, - "finish__design__instance__count": 167929, - "finish__design__instance__count__macros": 132, - "finish__design__instance__count__stdcell": 167797, - "finish__design__instance__utilization": 0.368901, - "finish__design__instance__utilization__stdcell": 0.209315, - "finish__design__io": 495, - "finish__mem__peak": 4584016.0, - "finish__runtime__total": "13:34.42", - "finish__timing__drv__hold_violation_count": 0.0, - "finish__timing__drv__max_cap": 216, - "finish__timing__drv__max_cap_limit": -0.222952, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 1e+30, - "finish__timing__drv__max_slew": 1, - "finish__timing__drv__max_slew_limit": -0.0867402, - "finish__timing__drv__setup_violation_count": 1.0, - "finish__timing__setup__tns": -737.613, - "finish__timing__setup__ws": -0.492795, - "finish__timing__wns_percent_delay": -10.027062, - "floorplan__cpu__total": 445.94, - "floorplan__design__core__area": 2063420.0, - "floorplan__design__die__area": 2250000.0, - "floorplan__design__instance__area": 703255, - "floorplan__design__instance__area__macros": 416463, - "floorplan__design__instance__area__stdcell": 286792, - "floorplan__design__instance__count": 140101, - "floorplan__design__instance__count__macros": 132, - "floorplan__design__instance__count__stdcell": 139969, - "floorplan__design__instance__utilization": 0.340821, - "floorplan__design__instance__utilization__stdcell": 0.174135, - "floorplan__design__io": 495, - "floorplan__mem__peak": 493092.0, - "floorplan__runtime__total": "1:22.83", - "floorplan__timing__setup__tns": -67591.6, - "floorplan__timing__setup__ws": -11.2326, - "globalplace__cpu__total": 118.23, - "globalplace__design__core__area": 2063420.0, - "globalplace__design__die__area": 2250000.0, - "globalplace__design__instance__area": 707220, - "globalplace__design__instance__area__macros": 416463, - "globalplace__design__instance__area__stdcell": 290757, - "globalplace__design__instance__count": 155006, - "globalplace__design__instance__count__macros": 132, - "globalplace__design__instance__count__stdcell": 154874, - "globalplace__design__instance__utilization": 0.342742, - "globalplace__design__instance__utilization__stdcell": 0.176542, - "globalplace__design__io": 495, - "globalplace__mem__peak": 1215924.0, - "globalplace__runtime__total": "2:00.74", - "globalplace__timing__setup__tns": -176804, - "globalplace__timing__setup__ws": -30.7328, - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.180223, - "globalroute__clock__skew__setup": 2.38305, - "globalroute__design__core__area": 2063420.0, - "globalroute__design__die__area": 2250000.0, - "globalroute__design__instance__area": 761195, - "globalroute__design__instance__area__macros": 416463, - "globalroute__design__instance__area__stdcell": 344732, - "globalroute__design__instance__count": 167929, - "globalroute__design__instance__count__macros": 132, - "globalroute__design__instance__count__stdcell": 167797, - "globalroute__design__instance__utilization": 0.368901, - "globalroute__design__instance__utilization__stdcell": 0.209315, - "globalroute__design__io": 495, - "globalroute__timing__clock__slack": -0.354, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 88, - "globalroute__timing__drv__max_cap_limit": -0.335012, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 1e+30, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0038974, - "globalroute__timing__drv__setup_violation_count": 2103, - "globalroute__timing__setup__tns": -472.164, - "globalroute__timing__setup__ws": -0.354088, - "placeopt__cpu__total": 118.23, - "placeopt__design__core__area": 2063420.0, - "placeopt__design__core__area__pre_opt": 2063420.0, - "placeopt__design__die__area": 2250000.0, - "placeopt__design__die__area__pre_opt": 2250000.0, - "placeopt__design__instance__area": 758900, - "placeopt__design__instance__area__macros": 416463, - "placeopt__design__instance__area__macros__pre_opt": 416463, - "placeopt__design__instance__area__pre_opt": 707220, - "placeopt__design__instance__area__stdcell": 342436, - "placeopt__design__instance__area__stdcell__pre_opt": 290757, - "placeopt__design__instance__count": 166827, - "placeopt__design__instance__count__macros": 132, - "placeopt__design__instance__count__macros__pre_opt": 132, - "placeopt__design__instance__count__pre_opt": 155006, - "placeopt__design__instance__count__stdcell": 166695, - "placeopt__design__instance__count__stdcell__pre_opt": 154874, - "placeopt__design__instance__utilization": 0.367788, - "placeopt__design__instance__utilization__pre_opt": 0.342742, - "placeopt__design__instance__utilization__stdcell": 0.207921, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.176542, - "placeopt__design__io": 495, - "placeopt__design__io__pre_opt": 495, - "placeopt__mem__peak": 1215924.0, - "placeopt__runtime__total": "2:00.74", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 7, - "placeopt__timing__drv__max_cap_limit": -0.177116, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 1e+30, - "placeopt__timing__drv__max_slew": 1, - "placeopt__timing__drv__max_slew_limit": -0.0369146, - "placeopt__timing__drv__setup_violation_count": 3456, - "placeopt__timing__setup__tns": -3438.9, - "placeopt__timing__setup__tns__pre_opt": -176804, - "placeopt__timing__setup__ws": -1.39442, - "placeopt__timing__setup__ws__pre_opt": -30.7328, - "run__flow__design": "ariane133", - "run__flow__generate_date": "2023-04-01 07:48", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-7484-ga8187d5b7", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "6791d5ab557bb4024a97750727053afe477539d5", - "run__flow__scripts_commit": "6791d5ab557bb4024a97750727053afe477539d5", - "run__flow__uuid": "ecac444f-22e6-437b-9c33-f16c4d3d63de", - "run__flow__variant": "base", - "synth__cpu__total": 1015.76, - "synth__design__instance__area__stdcell": 719967.836, - "synth__design__instance__count__stdcell": 158382.0, - "synth__mem__peak": 1494136.0, - "synth__runtime__total": "17:16.23", - "total_time": "0:38:00.310000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/ariane133/rules-base.json b/flow/designs/nangate45/ariane133/rules-base.json index 8854f8a679..00369c0887 100644 --- a/flow/designs/nangate45/ariane133/rules-base.json +++ b/flow/designs/nangate45/ariane133/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 827963.02, + "value": 825864.85, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 872735, + "value": 871517, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -27,16 +27,28 @@ "value": 16670, "compare": "<=" }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, "detailedroute__route__wirelength": { - "value": 7435938, + "value": 8921456, "compare": "<=" }, "detailedroute__route__drc_errors": { "value": 0, "compare": "<=" }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": -0.69, + "value": -0.22, "compare": ">=" }, "finish__design__instance__area": { @@ -52,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.03, + "value": -10.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk index 2a72f8effb..04da1dc265 100644 --- a/flow/designs/nangate45/ariane136/config.mk +++ b/flow/designs/nangate45/ariane136/config.mk @@ -4,13 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 16 -export RTLMP_MIN_MACRO = 4 -export RTLMP_SIGNATURE_NET_THRESHOLD = 30 - export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v @@ -23,9 +16,9 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x16.lib export DIE_AREA = 0 0 1500 1500 export CORE_AREA = 10 12 1448 1448 -export PLACE_PINS_ARGS = -exclude left:0-500 -exclude left:1000-1500: -exclude right:* -exclude top:* -exclude bottom:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 + export TNS_END_PERCENT = 100 export PLACE_DENSITY = 0.35 diff --git a/flow/designs/nangate45/ariane136/constraint.sdc b/flow/designs/nangate45/ariane136/constraint.sdc index e0f4e320df..34dd047647 100644 --- a/flow/designs/nangate45/ariane136/constraint.sdc +++ b/flow/designs/nangate45/ariane136/constraint.sdc @@ -1,496 +1,496 @@ -create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} -set_input_delay -clock core_clock 0 [get_ports clk_i] -set_input_delay -clock core_clock 0 [get_ports rst_ni] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 0 [get_ports ipi_i] -set_input_delay -clock core_clock 0 [get_ports time_irq_i] -set_input_delay -clock core_clock 0 [get_ports debug_req_i] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] +create_clock [get_ports clk_i] -name core_clock -period 6 -waveform {0 3} +set_input_delay -clock core_clock 0 [get_ports clk_i] +set_input_delay -clock core_clock 0 [get_ports rst_ni] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {boot_addr_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {hart_id_i[0]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {irq_i[0]}] +set_input_delay -clock core_clock 0 [get_ports ipi_i] +set_input_delay -clock core_clock 0 [get_ports time_irq_i] +set_input_delay -clock core_clock 0 [get_ports debug_req_i] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[81]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[80]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[79]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[78]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[77]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[76]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[75]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[74]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[73]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[72]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[71]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[70]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[69]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[68]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[67]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[66]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[65]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[64]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[63]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[62]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[61]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[60]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[59]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[58]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[57]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[56]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[55]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[54]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[53]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[52]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[51]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[50]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[49]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[48]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[47]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[46]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[45]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[44]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[43]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[42]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[41]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[40]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[39]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[38]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[37]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[36]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[35]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[34]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[33]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[32]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[31]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[30]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[29]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[28]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[27]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[26]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[25]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[24]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[23]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[22]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[21]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[20]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[19]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[18]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[17]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[16]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[15]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[14]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[13]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[12]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[11]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[10]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[9]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[8]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[7]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[6]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[5]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[4]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[3]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[2]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[1]}] +set_input_delay -clock core_clock 0 [get_ports {axi_resp_i[0]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[277]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[276]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[275]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[274]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[273]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[272]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[271]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[270]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[269]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[268]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[267]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[266]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[265]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[264]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[263]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[262]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[261]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[260]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[259]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[258]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[257]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[256]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[255]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[254]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[253]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[252]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[251]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[250]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[249]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[248]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[247]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[246]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[245]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[244]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[243]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[242]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[241]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[240]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[239]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[238]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[237]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[236]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[235]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[234]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[233]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[232]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[231]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[230]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[229]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[228]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[227]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[226]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[225]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[224]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[223]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[222]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[221]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[220]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[219]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[218]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[217]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[216]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[215]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[214]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[213]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[212]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[211]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[210]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[209]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[208]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[207]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[206]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[205]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[204]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[203]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[202]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[201]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[200]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[199]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[198]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[197]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[196]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[195]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[194]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[193]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[192]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[191]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[190]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[189]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[188]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[187]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[186]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[185]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[184]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[183]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[182]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[181]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[180]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[179]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[178]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[177]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[176]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[175]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[174]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[173]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[172]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[171]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[170]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[169]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[168]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[167]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[166]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[165]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[164]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[163]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[162]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[161]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[160]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[159]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[158]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[157]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[156]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[155]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[154]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[153]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[152]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[151]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[150]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[149]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[148]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[147]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[146]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[145]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[144]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[143]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[142]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[141]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[140]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[139]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[138]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[137]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[136]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[135]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[134]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[133]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[132]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[131]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[130]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[129]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[128]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[127]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[126]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[125]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[124]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[123]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[122]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[121]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[120]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[119]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[118]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[117]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[116]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[115]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[114]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[113]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[112]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[111]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[110]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[109]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[108]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[107]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[106]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[105]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[104]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[103]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[102]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[101]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[100]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[99]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[98]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[97]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[96]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[95]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[94]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[93]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[92]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[91]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[90]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[89]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[88]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[87]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[86]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[85]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[84]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[83]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[82]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[81]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[80]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[79]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[78]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[77]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[76]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[75]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[74]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[73]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[72]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[71]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[70]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[69]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[68]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[67]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[66]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[65]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[64]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[63]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[62]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[61]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[60]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[59]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[58]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[57]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[56]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[55]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[54]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[53]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[52]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[51]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[50]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[49]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[48]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[47]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[46]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[45]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[44]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[43]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[42]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[41]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[40]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[39]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[38]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[37]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[36]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[35]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[34]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[33]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[32]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[31]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[30]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[29]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[28]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[27]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[26]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[25]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[24]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[23]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[22]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[21]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[20]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[19]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[18]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[17]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[16]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[15]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[14]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[13]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[12]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[11]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[10]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[9]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[8]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[7]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[6]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[5]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[4]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[3]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[2]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[1]}] +set_output_delay -clock core_clock 0 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/nangate45/ariane136/io.tcl b/flow/designs/nangate45/ariane136/io.tcl new file mode 100644 index 0000000000..4de8dc3e2a --- /dev/null +++ b/flow/designs/nangate45/ariane136/io.tcl @@ -0,0 +1,6 @@ +exclude_io_pin_region \ + -region left:0-500 \ + -region left:1000-1500: \ + -region right:* \ + -region top:* \ + -region bottom:* diff --git a/flow/designs/nangate45/ariane136/metadata-base-ok.json b/flow/designs/nangate45/ariane136/metadata-base-ok.json deleted file mode 100644 index 7d6b61ebfc..0000000000 --- a/flow/designs/nangate45/ariane136/metadata-base-ok.json +++ /dev/null @@ -1,390 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 6.0000" - ], - "cts__clock__skew__hold": 0.372684, - "cts__clock__skew__setup": 2.26737, - "cts__cpu__total": 715.62, - "cts__design__core__area": 2063420.0, - "cts__design__die__area": 2250000.0, - "cts__design__instance__area": 835794, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 429084, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 406710, - "cts__design__instance__count": 205628, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 3867, - "cts__design__instance__count__macros": 136, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 205492, - "cts__design__instance__displacement__max": 23.3345, - "cts__design__instance__displacement__mean": 0.0365, - "cts__design__instance__displacement__total": 7511.43, - "cts__design__instance__utilization": 0.405053, - "cts__design__instance__utilization__stdcell": 0.248854, - "cts__design__io": 495, - "cts__design__rows": 5489, - "cts__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "cts__design__sites": 5833151, - "cts__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 2262516.0, - "cts__power__internal__total": 0.155137, - "cts__power__leakage__total": 0.0327282, - "cts__power__switching__total": 0.0763917, - "cts__power__total": 0.264257, - "cts__route__wirelength__estimated": 7701030.0, - "cts__runtime__total": "11:58.63", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 2, - "cts__timing__drv__max_cap_limit": -0.0631006, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.326274, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 1.13105, - "design__io__hpwl": 701001009, - "design__violations": 0, - "detailedplace__cpu__total": 177.92, - "detailedplace__design__core__area": 2063420.0, - "detailedplace__design__die__area": 2250000.0, - "detailedplace__design__instance__area": 823716, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 429084, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 394632, - "detailedplace__design__instance__count": 194186, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 136, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 194050, - "detailedplace__design__instance__displacement__max": 26.5205, - "detailedplace__design__instance__displacement__mean": 0.77, - "detailedplace__design__instance__displacement__total": 149552, - "detailedplace__design__instance__utilization": 0.3992, - "detailedplace__design__instance__utilization__stdcell": 0.241464, - "detailedplace__design__io": 495, - "detailedplace__design__rows": 5489, - "detailedplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "detailedplace__design__sites": 5833151, - "detailedplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1979628.0, - "detailedplace__power__internal__total": 0.145266, - "detailedplace__power__leakage__total": 0.0324643, - "detailedplace__power__switching__total": 0.0647131, - "detailedplace__power__total": 0.242443, - "detailedplace__route__wirelength__estimated": 7624540.0, - "detailedplace__runtime__total": "2:59.05", - "detailedplace__timing__drv__hold_violation_count": 1255, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.00805207, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.367871, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 1.11821, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 147, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 50198, - "detailedroute__route__drc_errors__iter:2": 9242, - "detailedroute__route__drc_errors__iter:3": 6075, - "detailedroute__route__drc_errors__iter:4": 325, - "detailedroute__route__drc_errors__iter:5": 26, - "detailedroute__route__drc_errors__iter:6": 18, - "detailedroute__route__drc_errors__iter:7": 9, - "detailedroute__route__drc_errors__iter:8": 9, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 217390, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1587597, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1587597, - "detailedroute__route__wirelength": 8685138, - "detailedroute__route__wirelength__iter:1": 8715452, - "detailedroute__route__wirelength__iter:2": 8687131, - "detailedroute__route__wirelength__iter:3": 8684067, - "detailedroute__route__wirelength__iter:4": 8684994, - "detailedroute__route__wirelength__iter:5": 8685062, - "detailedroute__route__wirelength__iter:6": 8685151, - "detailedroute__route__wirelength__iter:7": 8685135, - "detailedroute__route__wirelength__iter:8": 8685135, - "detailedroute__route__wirelength__iter:9": 8685138, - "finish__clock__skew__hold": 0.406155, - "finish__clock__skew__setup": 2.30649, - "finish__cpu__total": 1282.65, - "finish__design__core__area": 2063420.0, - "finish__design__die__area": 2250000.0, - "finish__design__instance__area": 835977, - "finish__design__instance__area__class:buffer": 36857, - "finish__design__instance__area__class:clock_buffer": 7613.45, - "finish__design__instance__area__class:clock_inverter": 953.344, - "finish__design__instance__area__class:inverter": 6326.54, - "finish__design__instance__area__class:macro": 429084, - "finish__design__instance__area__class:multi_input_combinational_cell": 214765, - "finish__design__instance__area__class:sequential_cell": 116326, - "finish__design__instance__area__class:timing_repair_buffer": 20013, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 429084, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 406894, - "finish__design__instance__count": 205696, - "finish__design__instance__count__class:buffer": 20153, - "finish__design__instance__count__class:clock_buffer": 6490, - "finish__design__instance__count__class:clock_inverter": 1085, - "finish__design__instance__count__class:inverter": 10453, - "finish__design__instance__count__class:macro": 136, - "finish__design__instance__count__class:multi_input_combinational_cell": 123102, - "finish__design__instance__count__class:sequential_cell": 21409, - "finish__design__instance__count__class:timing_repair_buffer": 7683, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 136, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 205560, - "finish__design__instance__utilization": 0.405142, - "finish__design__instance__utilization__stdcell": 0.248966, - "finish__design__io": 495, - "finish__design__rows": 5489, - "finish__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "finish__design__sites": 5833151, - "finish__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.09332, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00534103, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0272603, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0259597, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.07274, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0259597, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 4855108.0, - "finish__power__internal__total": 0.155333, - "finish__power__leakage__total": 0.0327378, - "finish__power__switching__total": 0.0848518, - "finish__power__total": 0.272923, - "finish__runtime__total": "21:28.63", - "finish__timing__drv__hold_violation_count": 127, - "finish__timing__drv__max_cap": 115, - "finish__timing__drv__max_cap_limit": -0.372771, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0765599, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 1.064, - "finish__timing__wns_percent_delay": 19.14151, - "finish_merge__cpu__total": 20.74, - "finish_merge__mem__peak": 2197156.0, - "finish_merge__runtime__total": "0:22.30", - "floorplan__cpu__total": 3669.2, - "floorplan__design__core__area": 2063420.0, - "floorplan__design__die__area": 2250000.0, - "floorplan__design__instance__area": 745788, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 429084, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 316704, - "floorplan__design__instance__count": 171505, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 3, - "floorplan__design__instance__count__macros": 136, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 171369, - "floorplan__design__instance__utilization": 0.361434, - "floorplan__design__instance__utilization__stdcell": 0.193782, - "floorplan__design__io": 495, - "floorplan__design__rows": 1025, - "floorplan__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1025, - "floorplan__design__sites": 7757200, - "floorplan__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 7757200, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 4, - "floorplan__mem__peak": 875680.0, - "floorplan__power__internal__total": 0.12274, - "floorplan__power__leakage__total": 0.0292243, - "floorplan__power__switching__total": 0.0249732, - "floorplan__power__total": 0.176937, - "floorplan__runtime__total": "1:01:10", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 1.75725, - "floorplan_io__cpu__total": 1.89, - "floorplan_io__mem__peak": 420992.0, - "floorplan_io__runtime__total": "0:02.23", - "floorplan_macro__cpu__total": 1498.11, - "floorplan_macro__mem__peak": 1840792.0, - "floorplan_macro__runtime__total": "2:40.18", - "floorplan_pdn__cpu__total": 13.09, - "floorplan_pdn__mem__peak": 584196.0, - "floorplan_pdn__runtime__total": "0:13.56", - "floorplan_tap__cpu__total": 2.35, - "floorplan_tap__mem__peak": 332200.0, - "floorplan_tap__runtime__total": "0:02.64", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1116.99, - "globalplace__design__core__area": 2063420.0, - "globalplace__design__die__area": 2250000.0, - "globalplace__design__instance__area": 814723, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 429084, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 385640, - "globalplace__design__instance__count": 188962, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 136, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 188826, - "globalplace__design__instance__utilization": 0.394842, - "globalplace__design__instance__utilization__stdcell": 0.235962, - "globalplace__design__io": 495, - "globalplace__design__rows": 5489, - "globalplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "globalplace__design__sites": 5833151, - "globalplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 2454552.0, - "globalplace__power__internal__total": 0.144102, - "globalplace__power__leakage__total": 0.0320765, - "globalplace__power__switching__total": 0.0648438, - "globalplace__power__total": 0.241023, - "globalplace__runtime__total": "11:27.07", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 0.856494, - "globalplace_io__cpu__total": 1.41, - "globalplace_io__mem__peak": 455004.0, - "globalplace_io__runtime__total": "0:01.64", - "globalplace_skip_io__cpu__total": 228.08, - "globalplace_skip_io__mem__peak": 767516.0, - "globalplace_skip_io__runtime__total": "0:57.41", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.406797, - "globalroute__clock__skew__setup": 2.27288, - "globalroute__cpu__total": 921.72, - "globalroute__design__core__area": 2063420.0, - "globalroute__design__die__area": 2250000.0, - "globalroute__design__instance__area": 835977, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 429084, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 406894, - "globalroute__design__instance__count": 205696, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 5, - "globalroute__design__instance__count__macros": 136, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 205560, - "globalroute__design__instance__displacement__max": 2.09, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 22.83, - "globalroute__design__instance__utilization": 0.405142, - "globalroute__design__instance__utilization__stdcell": 0.248966, - "globalroute__design__io": 495, - "globalroute__design__rows": 5489, - "globalroute__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "globalroute__design__sites": 5833151, - "globalroute__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 4446032.0, - "globalroute__power__internal__total": 0.155076, - "globalroute__power__leakage__total": 0.0327378, - "globalroute__power__switching__total": 0.0796501, - "globalroute__power__total": 0.267464, - "globalroute__route__wirelength__estimated": 7702140.0, - "globalroute__runtime__total": "8:33.66", - "globalroute__timing__clock__slack": 1.164, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 51, - "globalroute__timing__drv__max_cap_limit": -0.0876539, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.231899, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 1.16442, - "placeopt__cpu__total": 140.35, - "placeopt__design__core__area": 2063420.0, - "placeopt__design__die__area": 2250000.0, - "placeopt__design__instance__area": 823716, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 429084, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 394632, - "placeopt__design__instance__count": 194186, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 136, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 194050, - "placeopt__design__instance__utilization": 0.3992, - "placeopt__design__instance__utilization__stdcell": 0.241464, - "placeopt__design__io": 495, - "placeopt__design__rows": 5489, - "placeopt__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 5489, - "placeopt__design__sites": 5833151, - "placeopt__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 5833151, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1122772.0, - "placeopt__power__internal__total": 0.145284, - "placeopt__power__leakage__total": 0.0324643, - "placeopt__power__switching__total": 0.0650164, - "placeopt__power__total": 0.242765, - "placeopt__runtime__total": "2:20.97", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 1134, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0143768, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.353682, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1.10919, - "run__flow__design": "ariane136", - "run__flow__generate_date": "2024-11-26 16:46", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17322-g75f345819", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "16627131686649bdc0c8ea3bda72c7bdc1544928", - "run__flow__scripts_commit": "16627131686649bdc0c8ea3bda72c7bdc1544928", - "run__flow__uuid": "b407c0e5-fa3b-4ec3-9a5c-898ef6e3b110", - "run__flow__variant": "base", - "synth__cpu__total": 860.17, - "synth__design__instance__area__stdcell": 745785.53, - "synth__design__instance__count__stdcell": 171502.0, - "synth__mem__peak": 786004.0, - "synth__runtime__total": "14:24.54", - "total_time": "2:18:42.510000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index 2835091759..d692880787 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 847095.23, + "value": 845982.06, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 897767, + "value": 889812, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9268350, + "value": 8032745, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 904162, + "value": 902506, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -60,7 +60,7 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 259, + "value": 292, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index 16e60bd058..bdf35d8289 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v @@ -32,10 +27,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_512x64.lib \ export DIE_AREA = 0 0 1350 1300 export CORE_AREA = 10.07 11.2 1340 1290 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-100 -exclude bottom:1200-1350 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export PLACE_DENSITY_LB_ADDON = 0.05 export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 + export TNS_END_PERCENT = 100 diff --git a/flow/designs/nangate45/black_parrot/constraint.sdc b/flow/designs/nangate45/black_parrot/constraint.sdc index d6a53ebbd8..a5514ffe49 100644 --- a/flow/designs/nangate45/black_parrot/constraint.sdc +++ b/flow/designs/nangate45/black_parrot/constraint.sdc @@ -1,4 +1,4 @@ -set clk_name CLK +set clk_name CLK set clk_port_name clk_i set clk_period 6.0 set clk_io_pct 0.2 @@ -9,2397 +9,2397 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set_input_delay -clock CLK -max 3.42 [get_ports reset_i] -set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports reset_i] +set_input_delay -clock CLK -min $min_arrival [get_ports reset_i] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_v_i[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min $min_arrival [get_ports {mem_data_resp_ready_o[0]}] diff --git a/flow/designs/nangate45/black_parrot/io.tcl b/flow/designs/nangate45/black_parrot/io.tcl new file mode 100644 index 0000000000..9df7874f57 --- /dev/null +++ b/flow/designs/nangate45/black_parrot/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-100 -region bottom:1200-1350 diff --git a/flow/designs/nangate45/black_parrot/metadata-base-ok.json b/flow/designs/nangate45/black_parrot/metadata-base-ok.json deleted file mode 100644 index 2ae3d9724f..0000000000 --- a/flow/designs/nangate45/black_parrot/metadata-base-ok.json +++ /dev/null @@ -1,336 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 6.0000" - ], - "cts__clock__skew__hold": 0.10935, - "cts__clock__skew__setup": 0.10935, - "cts__cpu__total": 279.41, - "cts__design__core__area": 1699760.0, - "cts__design__die__area": 1755000.0, - "cts__design__instance__area": 843650, - "cts__design__instance__area__macros": 328372, - "cts__design__instance__area__stdcell": 515278, - "cts__design__instance__count": 336634, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 24, - "cts__design__instance__count__setup_buffer": 15, - "cts__design__instance__count__stdcell": 336610, - "cts__design__instance__displacement__max": 3.37, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 57.934, - "cts__design__instance__utilization": 0.496334, - "cts__design__instance__utilization__stdcell": 0.375734, - "cts__design__io": 1198, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 2178904.0, - "cts__power__internal__total": 0.117039, - "cts__power__leakage__total": 0.0274235, - "cts__power__switching__total": 0.0329894, - "cts__power__total": 0.177452, - "cts__route__wirelength__estimated": 8034710.0, - "cts__runtime__total": "4:41.43", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 7, - "cts__timing__drv__max_cap_limit": -0.0151247, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.377176, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__setup__tns": -0.514343, - "cts__timing__setup__ws": -0.514343, - "design__io__hpwl": 828555319, - "design__violations": 0, - "detailedplace__cpu__total": 292.07, - "detailedplace__design__core__area": 1699760.0, - "detailedplace__design__die__area": 1755000.0, - "detailedplace__design__instance__area": 831125, - "detailedplace__design__instance__area__macros": 328372, - "detailedplace__design__instance__area__stdcell": 502753, - "detailedplace__design__instance__count": 325302, - "detailedplace__design__instance__count__macros": 24, - "detailedplace__design__instance__count__stdcell": 325278, - "detailedplace__design__instance__displacement__max": 60.581, - "detailedplace__design__instance__displacement__mean": 0.884, - "detailedplace__design__instance__displacement__total": 287725, - "detailedplace__design__instance__utilization": 0.488965, - "detailedplace__design__instance__utilization__stdcell": 0.3666, - "detailedplace__design__io": 1198, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1819588.0, - "detailedplace__power__internal__total": 0.103019, - "detailedplace__power__leakage__total": 0.027149, - "detailedplace__power__switching__total": 0.0168442, - "detailedplace__power__total": 0.147012, - "detailedplace__route__wirelength__estimated": 7966090.0, - "detailedplace__runtime__total": "4:53.72", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 7, - "detailedplace__timing__drv__max_cap_limit": -0.0151247, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.377176, - "detailedplace__timing__drv__setup_violation_count": 1, - "detailedplace__timing__setup__tns": -0.637234, - "detailedplace__timing__setup__ws": -0.637234, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__cpu__total": 15569.48, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 0, - "detailedroute__mem__peak": 10969464.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 73683, - "detailedroute__route__drc_errors__iter:10": 69, - "detailedroute__route__drc_errors__iter:11": 32, - "detailedroute__route__drc_errors__iter:12": 22, - "detailedroute__route__drc_errors__iter:13": 3, - "detailedroute__route__drc_errors__iter:14": 1, - "detailedroute__route__drc_errors__iter:15": 1, - "detailedroute__route__drc_errors__iter:16": 0, - "detailedroute__route__drc_errors__iter:2": 13364, - "detailedroute__route__drc_errors__iter:3": 8293, - "detailedroute__route__drc_errors__iter:4": 567, - "detailedroute__route__drc_errors__iter:5": 183, - "detailedroute__route__drc_errors__iter:6": 147, - "detailedroute__route__drc_errors__iter:7": 116, - "detailedroute__route__drc_errors__iter:8": 120, - "detailedroute__route__drc_errors__iter:9": 77, - "detailedroute__route__net": 364010, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2183681, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2183681, - "detailedroute__route__wirelength": 9024533, - "detailedroute__route__wirelength__iter:1": 9054232, - "detailedroute__route__wirelength__iter:10": 9024454, - "detailedroute__route__wirelength__iter:11": 9024483, - "detailedroute__route__wirelength__iter:12": 9024496, - "detailedroute__route__wirelength__iter:13": 9024542, - "detailedroute__route__wirelength__iter:14": 9024524, - "detailedroute__route__wirelength__iter:15": 9024527, - "detailedroute__route__wirelength__iter:16": 9024533, - "detailedroute__route__wirelength__iter:2": 9026874, - "detailedroute__route__wirelength__iter:3": 9022908, - "detailedroute__route__wirelength__iter:4": 9024059, - "detailedroute__route__wirelength__iter:5": 9024212, - "detailedroute__route__wirelength__iter:6": 9024251, - "detailedroute__route__wirelength__iter:7": 9024332, - "detailedroute__route__wirelength__iter:8": 9024371, - "detailedroute__route__wirelength__iter:9": 9024444, - "detailedroute__runtime__total": "15:01.00", - "fillcell__cpu__total": 6.74, - "fillcell__mem__peak": 1126612.0, - "fillcell__runtime__total": "0:07.93", - "finish__clock__skew__hold": 0.132797, - "finish__clock__skew__setup": 0.132797, - "finish__cpu__total": 839.15, - "finish__design__core__area": 1699760.0, - "finish__design__die__area": 1755000.0, - "finish__design__instance__area": 843795, - "finish__design__instance__area__macros": 328372, - "finish__design__instance__area__stdcell": 515423, - "finish__design__instance__count": 336656, - "finish__design__instance__count__macros": 24, - "finish__design__instance__count__stdcell": 336632, - "finish__design__instance__utilization": 0.496419, - "finish__design__instance__utilization__stdcell": 0.37584, - "finish__design__io": 1198, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.0965, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00394438, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0117545, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0265471, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.08825, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0265471, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 6037776.0, - "finish__power__internal__total": 0.117123, - "finish__power__leakage__total": 0.0274306, - "finish__power__switching__total": 0.0357523, - "finish__power__total": 0.180306, - "finish__runtime__total": "14:08.50", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 57, - "finish__timing__drv__max_cap_limit": -0.426262, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0880034, - "finish__timing__drv__setup_violation_count": 1, - "finish__timing__setup__tns": -0.586197, - "finish__timing__setup__ws": -0.586197, - "finish__timing__wns_percent_delay": -8.016739, - "finish_merge__cpu__total": 34.83, - "finish_merge__mem__peak": 3185660.0, - "finish_merge__runtime__total": "0:37.87", - "floorplan__cpu__total": 80.86, - "floorplan__design__core__area": 1699760.0, - "floorplan__design__die__area": 1755000.0, - "floorplan__design__instance__area": 763869, - "floorplan__design__instance__area__macros": 328372, - "floorplan__design__instance__area__stdcell": 435497, - "floorplan__design__instance__count": 306819, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 24, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 306795, - "floorplan__design__instance__utilization": 0.449397, - "floorplan__design__instance__utilization__stdcell": 0.317559, - "floorplan__design__io": 1198, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 17, - "floorplan__mem__peak": 1364012.0, - "floorplan__power__internal__total": 0.0989247, - "floorplan__power__leakage__total": 0.0244019, - "floorplan__power__switching__total": 0.00723678, - "floorplan__power__total": 0.130563, - "floorplan__runtime__total": "1:22.10", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.324622, - "floorplan_io__cpu__total": 2.33, - "floorplan_io__mem__peak": 653020.0, - "floorplan_io__runtime__total": "0:03.09", - "floorplan_macro__cpu__total": 1060.72, - "floorplan_macro__mem__peak": 1375796.0, - "floorplan_macro__runtime__total": "1:21.71", - "floorplan_pdn__cpu__total": 14.55, - "floorplan_pdn__mem__peak": 829484.0, - "floorplan_pdn__runtime__total": "0:15.40", - "floorplan_tap__cpu__total": 16.54, - "floorplan_tap__mem__peak": 475976.0, - "floorplan_tap__runtime__total": "0:17.10", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 6144.47, - "globalplace__design__core__area": 1699760.0, - "globalplace__design__die__area": 1755000.0, - "globalplace__design__instance__area": 766370, - "globalplace__design__instance__area__macros": 328372, - "globalplace__design__instance__area__stdcell": 437998, - "globalplace__design__instance__count": 316221, - "globalplace__design__instance__count__macros": 24, - "globalplace__design__instance__count__stdcell": 316197, - "globalplace__design__instance__utilization": 0.450869, - "globalplace__design__instance__utilization__stdcell": 0.319382, - "globalplace__design__io": 1198, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 2999924.0, - "globalplace__power__internal__total": 0.0991677, - "globalplace__power__leakage__total": 0.0244019, - "globalplace__power__switching__total": 0.0144402, - "globalplace__power__total": 0.13801, - "globalplace__runtime__total": "21:20.23", - "globalplace__timing__setup__tns": -47.3691, - "globalplace__timing__setup__ws": -0.690681, - "globalplace_io__cpu__total": 2.78, - "globalplace_io__mem__peak": 689092.0, - "globalplace_io__runtime__total": "0:03.50", - "globalplace_skip_io__cpu__total": 1005.43, - "globalplace_skip_io__mem__peak": 1285724.0, - "globalplace_skip_io__runtime__total": "1:57.61", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.113665, - "globalroute__clock__skew__setup": 0.113665, - "globalroute__cpu__total": 1000.55, - "globalroute__design__core__area": 1699760.0, - "globalroute__design__die__area": 1755000.0, - "globalroute__design__instance__area": 843795, - "globalroute__design__instance__area__macros": 328372, - "globalroute__design__instance__area__stdcell": 515423, - "globalroute__design__instance__count": 336656, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 24, - "globalroute__design__instance__count__setup_buffer": 9, - "globalroute__design__instance__count__stdcell": 336632, - "globalroute__design__instance__displacement__max": 2.66, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 47.18, - "globalroute__design__instance__utilization": 0.496419, - "globalroute__design__instance__utilization__stdcell": 0.37584, - "globalroute__design__io": 1198, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 4468512.0, - "globalroute__power__internal__total": 0.116999, - "globalroute__power__leakage__total": 0.0274306, - "globalroute__power__switching__total": 0.0339162, - "globalroute__power__total": 0.178345, - "globalroute__route__wirelength__estimated": 8034900.0, - "globalroute__runtime__total": "8:06.78", - "globalroute__timing__clock__slack": -0.595, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 16, - "globalroute__timing__drv__max_cap_limit": -0.242793, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.24884, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -0.594692, - "globalroute__timing__setup__ws": -0.594692, - "placeopt__cpu__total": 206.72, - "placeopt__design__core__area": 1699760.0, - "placeopt__design__die__area": 1755000.0, - "placeopt__design__instance__area": 831125, - "placeopt__design__instance__area__macros": 328372, - "placeopt__design__instance__area__stdcell": 502753, - "placeopt__design__instance__count": 325302, - "placeopt__design__instance__count__macros": 24, - "placeopt__design__instance__count__stdcell": 325278, - "placeopt__design__instance__utilization": 0.488965, - "placeopt__design__instance__utilization__stdcell": 0.3666, - "placeopt__design__io": 1198, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1730540.0, - "placeopt__power__internal__total": 0.103017, - "placeopt__power__leakage__total": 0.027149, - "placeopt__power__switching__total": 0.0168572, - "placeopt__power__total": 0.147023, - "placeopt__runtime__total": "3:28.31", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 7, - "placeopt__timing__drv__max_cap_limit": -0.0160262, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.379057, - "placeopt__timing__drv__setup_violation_count": 1, - "placeopt__timing__setup__tns": -0.733073, - "placeopt__timing__setup__ws": -0.733073, - "run__flow__design": "bp", - "run__flow__generate_date": "2024-08-24 22:19", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15311-g42ba30d73", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "20576ce92a18c95900f45bbf8aff4385defe5527", - "run__flow__scripts_commit": "20576ce92a18c95900f45bbf8aff4385defe5527", - "run__flow__uuid": "bdcea526-879b-4fbf-a6be-69719910d012", - "run__flow__variant": "base", - "synth__cpu__total": 359.91, - "synth__design__instance__area__stdcell": 763869.274, - "synth__design__instance__count__stdcell": 306819.0, - "synth__mem__peak": 812780.0, - "synth__runtime__total": "6:03.99", - "total_time": "1:23:50.270000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/black_parrot/rules-base.json b/flow/designs/nangate45/black_parrot/rules-base.json index da8cb9c170..7b23a5722c 100644 --- a/flow/designs/nangate45/black_parrot/rules-base.json +++ b/flow/designs/nangate45/black_parrot/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 875702.08, + "value": 778242.64, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 928020, + "value": 816555, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 346412, + "value": 280905, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,15 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 30123, + "value": 24426, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 30123, + "value": 24426, + "compare": "<=" + }, + "globalroute__antenna_diodes_count": { + "value": 0, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 9419931, + "value": 7048481, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -39,16 +43,20 @@ "value": 0, "compare": "<=" }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, "finish__timing__setup__ws": { - "value": -0.88, + "value": -4.07, "compare": ">=" }, "finish__design__instance__area": { - "value": 931337, + "value": 832222, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 15061, + "value": 12213, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -56,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.62, + "value": -42.49, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk index 6d21176d60..7f88c0f4c3 100644 --- a/flow/designs/nangate45/bp_be_top/config.mk +++ b/flow/designs/nangate45/bp_be_top/config.mk @@ -3,12 +3,6 @@ export DESIGN_NAME = bp_be_top export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -# -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v @@ -24,10 +18,15 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_512x64.lib \ export DIE_AREA = 0 0 800 700 export CORE_AREA = 10.07 11.2 790 690 -export PLACE_PINS_ARGS = -exclude left:500-800 -exclude right:500-800 -exclude top:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 export PLACE_DENSITY_LB_ADDON = 0.10 export TNS_END_PERCENT = 100 + +export CTS_CLUSTER_SIZE = 30 +export CTS_CLUSTER_DIAMETER = 50 +export SYNTH_MINIMUM_KEEP_SIZE = 3000 + +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl diff --git a/flow/designs/nangate45/bp_be_top/constraint.sdc b/flow/designs/nangate45/bp_be_top/constraint.sdc index 632222055a..3df6fe408f 100644 --- a/flow/designs/nangate45/bp_be_top/constraint.sdc +++ b/flow/designs/nangate45/bp_be_top/constraint.sdc @@ -1,6058 +1,6057 @@ - -create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} -set_input_delay -clock CLK -max 0.6 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 2.6 -waveform {0 1.3} +set_input_delay -clock CLK -max 0.6 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {fe_queue_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_queue_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports fe_cmd_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_req_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[539]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_data_cmd_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[538]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[537]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[536]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[535]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[534]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[533]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[532]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[531]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[530]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[529]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[528]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[527]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[526]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[525]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[524]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[523]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[522]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[521]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[520]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[519]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[518]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[517]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[516]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[515]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[514]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[513]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[512]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[511]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[510]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[509]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[508]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[507]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[506]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[505]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[504]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[503]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[502]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[501]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[500]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[499]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[498]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[497]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[496]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[495]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[494]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[493]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[492]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[491]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[490]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[489]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[488]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[487]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[486]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[485]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[484]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[483]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[482]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[481]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[480]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[479]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[478]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[477]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[476]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[475]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[474]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[473]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[472]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[471]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[470]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[469]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[468]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[467]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[466]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[465]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[464]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[463]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[462]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[461]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[460]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[459]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[458]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[457]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[456]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[455]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[454]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[453]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[452]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[451]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[450]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[449]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[448]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[447]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[446]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[445]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[444]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[443]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[442]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[441]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[440]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[439]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[438]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[437]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[436]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[435]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[434]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[433]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[432]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[431]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[430]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[429]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[428]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[427]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[426]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[425]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[424]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[423]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[422]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[421]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[420]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[419]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[418]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[417]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[416]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[415]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[414]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[413]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[412]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[411]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[410]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[409]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[408]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[407]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[406]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[405]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[404]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[403]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[402]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[401]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[400]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[399]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[398]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[397]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[396]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[395]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[394]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[393]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[392]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[391]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[390]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[389]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[388]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[387]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[386]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[385]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[384]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[383]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[382]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[381]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[380]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[379]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[378]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[377]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[376]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[375]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[374]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[373]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[372]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[371]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[370]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[369]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[368]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[367]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[366]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[365]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[364]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[363]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[362]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[361]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[360]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[359]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[358]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[357]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[356]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[355]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[354]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[353]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[352]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[351]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[350]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[349]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[348]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[347]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[346]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[345]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[344]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[343]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[342]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[341]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[340]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[339]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[338]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[337]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[336]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[335]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[334]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[333]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[332]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[331]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[330]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[329]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[328]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[327]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[326]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[325]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[324]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[323]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[322]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[321]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[320]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[319]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[318]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[317]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[316]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[315]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[314]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[313]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[312]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[311]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[310]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[309]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[308]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[307]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[306]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[305]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[304]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[303]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[302]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[301]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[300]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[299]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[298]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[297]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[296]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[295]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[294]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[293]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[292]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[291]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[290]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[289]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[288]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[287]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[286]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[285]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[284]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[283]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[282]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[281]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[280]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[279]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[278]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[277]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[276]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[275]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[274]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[273]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[272]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[271]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[270]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[269]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[268]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[267]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[266]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[265]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[264]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[263]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[262]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[261]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[260]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[259]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[258]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[257]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[256]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[255]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[254]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[253]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[252]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[251]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[250]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[249]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[248]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[247]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[246]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[245]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[244]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[243]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[242]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[241]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[240]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[239]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[238]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[237]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[236]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[235]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[234]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[233]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[232]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[231]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[230]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[229]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[228]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[227]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[226]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[225]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[224]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[223]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[222]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[221]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[220]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[219]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[218]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[217]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[216]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[215]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[214]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[213]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[212]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[211]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[210]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[209]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[208]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[207]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[206]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[205]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[204]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[203]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[202]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[201]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[200]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[199]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[198]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[197]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[196]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[195]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[194]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[193]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[192]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[191]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[190]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[189]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[188]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[187]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[186]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[185]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[184]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[183]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[182]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[181]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[180]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[179]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[178]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[177]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[176]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[175]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[174]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[173]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[172]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[171]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[170]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[169]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[168]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[167]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[166]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[165]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[164]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[163]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[162]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[161]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[160]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[159]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[158]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[157]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[156]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[155]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[154]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[153]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[152]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[151]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[150]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[149]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[148]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[147]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[146]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[145]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[144]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[143]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[142]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[141]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[140]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[139]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[138]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[137]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[136]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[135]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[134]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[133]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[132]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[131]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[130]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[129]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[128]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[127]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[126]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[125]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[124]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[123]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[122]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[121]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[120]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[119]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[118]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[117]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[116]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[115]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[114]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[113]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[112]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[111]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[110]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[109]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[108]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[107]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[106]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[105]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[104]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[103]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[102]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[101]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[100]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[99]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[98]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[97]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[96]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[95]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[94]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[93]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[92]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[91]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[90]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[89]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[88]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[87]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[86]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[85]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[84]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[83]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[82]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[81]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[80]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[79]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[78]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[77]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[76]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[75]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[74]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[73]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[72]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[71]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[70]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[69]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[68]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[67]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[66]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[65]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[64]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[63]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[62]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[61]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[60]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[59]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[58]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[57]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[56]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[55]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[54]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[53]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[52]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[51]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[50]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[49]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[48]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[47]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[46]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[45]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[44]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[43]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[42]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[41]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[40]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[39]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[38]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[37]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[36]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[35]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[34]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[33]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[32]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[31]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[30]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[29]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[28]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[27]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[26]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[25]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[24]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[23]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[22]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[21]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[20]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[19]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[18]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[17]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[16]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[15]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[14]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[13]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[12]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[11]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[10]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[9]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[8]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[7]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[6]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[5]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[4]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[3]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_i[0]}] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_i] +set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_i] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[2]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[1]}] +set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {proc_cfg_i[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_clr_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_dequeue_o] +set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_queue_rollback_o] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {fe_cmd_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports fe_cmd_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_req_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_req_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_data_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_data_cmd_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_ready_o] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[538]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[537]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[536]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[535]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[534]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[533]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[532]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[531]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[530]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[529]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[528]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[527]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[526]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[525]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[524]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[523]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[522]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[521]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[520]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[519]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[518]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[517]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[516]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[515]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[514]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[513]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[512]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[511]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[510]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[509]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[508]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[507]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[506]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[505]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[504]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[503]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[502]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[501]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[500]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[499]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[498]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[497]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[496]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[495]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[494]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[493]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[492]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[491]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[490]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[489]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[488]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[487]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[486]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[485]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[484]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[483]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[482]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[481]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[480]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[479]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[478]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[477]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[476]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[475]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[474]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[473]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[472]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[471]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[470]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[469]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[468]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[467]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[466]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[465]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[464]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[463]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[462]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[461]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[460]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[459]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[458]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[457]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[456]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[455]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[454]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[453]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[452]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[451]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[450]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[449]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[448]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[447]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[446]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[445]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[444]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[443]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[442]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[441]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[440]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[439]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[438]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[437]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[436]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[435]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[434]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[433]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[432]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[431]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[430]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[429]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[428]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[427]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[426]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[425]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[424]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[423]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[422]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[421]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[420]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[419]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[418]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[417]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[416]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[415]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[414]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[413]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[412]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[411]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[410]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[409]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[408]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[407]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[406]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[405]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[404]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[403]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[402]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[401]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[400]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[399]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[398]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[397]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[396]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[395]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[394]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[393]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[392]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[391]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[390]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[389]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[388]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[387]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[386]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[385]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[384]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[383]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[382]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[381]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[380]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[379]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[378]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {lce_tr_resp_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -min 0.6 [get_ports lce_tr_resp_v_o] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[127]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[126]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[125]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[124]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[123]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[122]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[121]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[120]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[119]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[118]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[117]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[116]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[115]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[114]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[113]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[112]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[111]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[110]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[109]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[108]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[107]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[106]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[105]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[104]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[103]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[102]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[101]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[100]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[99]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[98]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[97]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[96]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[95]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[94]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[93]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[92]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[91]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[90]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[89]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[88]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[87]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[86]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[85]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[84]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[83]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[82]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[81]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[80]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[79]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[78]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[77]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[76]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[75]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[74]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[73]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[72]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[71]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[70]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[69]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[68]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[67]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[66]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[65]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[64]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[63]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[62]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[61]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[60]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[59]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[58]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[57]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[56]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[55]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[54]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[53]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[52]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[51]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[50]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[49]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[48]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[47]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[46]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[45]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[44]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[43]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[42]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[41]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[40]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[39]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[38]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[37]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[36]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[35]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[34]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[33]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[32]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[31]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[30]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[29]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[28]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[27]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[26]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[25]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[24]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[23]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[22]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[21]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[20]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[19]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[18]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[17]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[16]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[15]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[14]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[13]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[12]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[11]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[10]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[9]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[8]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[7]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_result_o[0]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[6]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[5]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[4]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[3]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[2]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[1]}] +set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_trace_exc_o[0]}] diff --git a/flow/designs/nangate45/bp_be_top/fastroute.tcl b/flow/designs/nangate45/bp_be_top/fastroute.tcl new file mode 100644 index 0000000000..c7c32eb6f7 --- /dev/null +++ b/flow/designs/nangate45/bp_be_top/fastroute.tcl @@ -0,0 +1,4 @@ +set_global_routing_layer_adjustment metal2-metal3 0.4 +set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.15 + +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/nangate45/bp_be_top/io.tcl b/flow/designs/nangate45/bp_be_top/io.tcl new file mode 100644 index 0000000000..713f1d0db0 --- /dev/null +++ b/flow/designs/nangate45/bp_be_top/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:500-800 -region right:500-800 -region top:* diff --git a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json b/flow/designs/nangate45/bp_be_top/metadata-base-ok.json deleted file mode 100644 index 518b1b7c86..0000000000 --- a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json +++ /dev/null @@ -1,342 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 2.6000" - ], - "cts__clock__skew__hold": 0.124765, - "cts__clock__skew__setup": 0.124765, - "cts__cpu__total": 361.09, - "cts__design__core__area": 528365, - "cts__design__die__area": 560000, - "cts__design__instance__area": 267430, - "cts__design__instance__area__macros": 143946, - "cts__design__instance__area__stdcell": 123485, - "cts__design__instance__count": 60680, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 10, - "cts__design__instance__count__setup_buffer": 53, - "cts__design__instance__count__stdcell": 60670, - "cts__design__instance__displacement__max": 18.049, - "cts__design__instance__displacement__mean": 0.0075, - "cts__design__instance__displacement__total": 472.134, - "cts__design__instance__utilization": 0.506146, - "cts__design__instance__utilization__stdcell": 0.321223, - "cts__design__io": 3029, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 904116.0, - "cts__power__internal__total": 0.093731, - "cts__power__leakage__total": 0.00982871, - "cts__power__switching__total": 0.0344243, - "cts__power__total": 0.137984, - "cts__route__wirelength__estimated": 2528980.0, - "cts__runtime__total": "6:01.87", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.00193814, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.348226, - "cts__timing__drv__setup_violation_count": 109, - "cts__timing__setup__tns": -24.9773, - "cts__timing__setup__ws": -0.268139, - "design__io__hpwl": 2277424288, - "design__violations": 0, - "detailedplace__cpu__total": 71.4, - "detailedplace__design__core__area": 528365, - "detailedplace__design__die__area": 560000, - "detailedplace__design__instance__area": 264037, - "detailedplace__design__instance__area__macros": 143946, - "detailedplace__design__instance__area__stdcell": 120091, - "detailedplace__design__instance__count": 58071, - "detailedplace__design__instance__count__macros": 10, - "detailedplace__design__instance__count__stdcell": 58061, - "detailedplace__design__instance__displacement__max": 60.62, - "detailedplace__design__instance__displacement__mean": 0.9115, - "detailedplace__design__instance__displacement__total": 52942.5, - "detailedplace__design__instance__utilization": 0.499724, - "detailedplace__design__instance__utilization__stdcell": 0.312396, - "detailedplace__design__io": 3029, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 651688.0, - "detailedplace__power__internal__total": 0.0863632, - "detailedplace__power__leakage__total": 0.00973354, - "detailedplace__power__switching__total": 0.0258172, - "detailedplace__power__total": 0.121914, - "detailedplace__route__wirelength__estimated": 2517150.0, - "detailedplace__runtime__total": "1:11.92", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.00155115, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.348062, - "detailedplace__timing__drv__setup_violation_count": 102, - "detailedplace__timing__setup__tns": -9.63348, - "detailedplace__timing__setup__ws": -0.163148, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 22768, - "detailedroute__route__drc_errors__iter:10": 424, - "detailedroute__route__drc_errors__iter:11": 185, - "detailedroute__route__drc_errors__iter:12": 24, - "detailedroute__route__drc_errors__iter:13": 1, - "detailedroute__route__drc_errors__iter:14": 0, - "detailedroute__route__drc_errors__iter:2": 4718, - "detailedroute__route__drc_errors__iter:3": 3266, - "detailedroute__route__drc_errors__iter:4": 1137, - "detailedroute__route__drc_errors__iter:5": 844, - "detailedroute__route__drc_errors__iter:6": 732, - "detailedroute__route__drc_errors__iter:7": 639, - "detailedroute__route__drc_errors__iter:8": 602, - "detailedroute__route__drc_errors__iter:9": 515, - "detailedroute__route__net": 68477, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 547685, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 547685, - "detailedroute__route__wirelength": 3084898, - "detailedroute__route__wirelength__iter:1": 3096871, - "detailedroute__route__wirelength__iter:10": 3084662, - "detailedroute__route__wirelength__iter:11": 3084812, - "detailedroute__route__wirelength__iter:12": 3084913, - "detailedroute__route__wirelength__iter:13": 3084913, - "detailedroute__route__wirelength__iter:14": 3084898, - "detailedroute__route__wirelength__iter:2": 3086422, - "detailedroute__route__wirelength__iter:3": 3083525, - "detailedroute__route__wirelength__iter:4": 3084199, - "detailedroute__route__wirelength__iter:5": 3084517, - "detailedroute__route__wirelength__iter:6": 3084626, - "detailedroute__route__wirelength__iter:7": 3084600, - "detailedroute__route__wirelength__iter:8": 3084592, - "detailedroute__route__wirelength__iter:9": 3084606, - "finish__clock__skew__hold": 0.513013, - "finish__clock__skew__setup": 0.513013, - "finish__cpu__total": 176.3, - "finish__design__core__area": 528365, - "finish__design__die__area": 560000, - "finish__design__instance__area": 269035, - "finish__design__instance__area__macros": 143946, - "finish__design__instance__area__stdcell": 125089, - "finish__design__instance__count": 62254, - "finish__design__instance__count__class:buffer": 5219, - "finish__design__instance__count__class:clock_buffer": 2042, - "finish__design__instance__count__class:clock_inverter": 513, - "finish__design__instance__count__class:fill_cell": 96056, - "finish__design__instance__count__class:inverter": 3151, - "finish__design__instance__count__class:macro": 10, - "finish__design__instance__count__class:multi_input_combinational_cell": 34448, - "finish__design__instance__count__class:sequential_cell": 8570, - "finish__design__instance__count__class:tap_cell": 3501, - "finish__design__instance__count__class:timing_repair_buffer": 4798, - "finish__design__instance__count__class:timing_repair_inverter": 2, - "finish__design__instance__count__macros": 10, - "finish__design__instance__count__stdcell": 62244, - "finish__design__instance__utilization": 0.509184, - "finish__design__instance__utilization__stdcell": 0.325398, - "finish__design__io": 3029, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.08798, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0118994, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0232615, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0274227, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.07674, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0274227, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1566548.0, - "finish__power__internal__total": 0.0944396, - "finish__power__leakage__total": 0.0098665, - "finish__power__switching__total": 0.04166, - "finish__power__total": 0.145966, - "finish__runtime__total": "2:58.31", - "finish__timing__drv__hold_violation_count": 540, - "finish__timing__drv__max_cap": 206, - "finish__timing__drv__max_cap_limit": -0.784523, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 16, - "finish__timing__drv__max_slew_limit": -0.606029, - "finish__timing__drv__setup_violation_count": 130, - "finish__timing__setup__tns": -89.279, - "finish__timing__setup__ws": -0.863575, - "finish__timing__wns_percent_delay": -30.157843, - "finish_merge__cpu__total": 7.96, - "finish_merge__mem__peak": 928180.0, - "finish_merge__runtime__total": "0:08.61", - "floorplan__cpu__total": 31.09, - "floorplan__design__core__area": 528365, - "floorplan__design__die__area": 560000, - "floorplan__design__instance__area": 236465, - "floorplan__design__instance__area__macros": 143946, - "floorplan__design__instance__area__stdcell": 92519.9, - "floorplan__design__instance__count": 51392, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 10, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 51382, - "floorplan__design__instance__utilization": 0.447542, - "floorplan__design__instance__utilization__stdcell": 0.240674, - "floorplan__design__io": 3029, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 353348.0, - "floorplan__power__internal__total": 0.0776664, - "floorplan__power__leakage__total": 0.00862544, - "floorplan__power__switching__total": 0.00839269, - "floorplan__power__total": 0.0946846, - "floorplan__runtime__total": "0:31.28", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.02525, - "floorplan_io__cpu__total": 1.05, - "floorplan_io__mem__peak": 216368.0, - "floorplan_io__runtime__total": "0:01.22", - "floorplan_macro__cpu__total": 221.36, - "floorplan_macro__mem__peak": 356936.0, - "floorplan_macro__runtime__total": "0:18.89", - "floorplan_pdn__cpu__total": 2.57, - "floorplan_pdn__mem__peak": 256552.0, - "floorplan_pdn__runtime__total": "0:02.73", - "floorplan_tap__cpu__total": 1.04, - "floorplan_tap__mem__peak": 188104.0, - "floorplan_tap__runtime__total": "0:01.17", - "floorplan_tdms__cpu__total": 0.17, - "floorplan_tdms__mem__peak": 99644.0, - "floorplan_tdms__runtime__total": "0:00.25", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1676.78, - "globalplace__design__core__area": 528365, - "globalplace__design__die__area": 560000, - "globalplace__design__instance__area": 237397, - "globalplace__design__instance__area__macros": 143946, - "globalplace__design__instance__area__stdcell": 93451.1, - "globalplace__design__instance__count": 54893, - "globalplace__design__instance__count__macros": 10, - "globalplace__design__instance__count__stdcell": 54883, - "globalplace__design__instance__utilization": 0.449304, - "globalplace__design__instance__utilization__stdcell": 0.243097, - "globalplace__design__io": 3029, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 935336.0, - "globalplace__power__internal__total": 0.0781424, - "globalplace__power__leakage__total": 0.00862544, - "globalplace__power__switching__total": 0.0193044, - "globalplace__power__total": 0.106072, - "globalplace__runtime__total": "5:30.33", - "globalplace__timing__setup__tns": -903.949, - "globalplace__timing__setup__ws": -1.27604, - "globalplace_io__cpu__total": 1.71, - "globalplace_io__mem__peak": 228312.0, - "globalplace_io__runtime__total": "0:01.88", - "globalplace_skip_io__cpu__total": 601.2, - "globalplace_skip_io__mem__peak": 347312.0, - "globalplace_skip_io__runtime__total": "0:25.44", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.425906, - "globalroute__clock__skew__setup": 0.425906, - "globalroute__cpu__total": 964.66, - "globalroute__design__core__area": 528365, - "globalroute__design__die__area": 560000, - "globalroute__design__instance__area": 269035, - "globalroute__design__instance__area__macros": 143946, - "globalroute__design__instance__area__stdcell": 125089, - "globalroute__design__instance__count": 62254, - "globalroute__design__instance__count__hold_buffer": 1540, - "globalroute__design__instance__count__macros": 10, - "globalroute__design__instance__count__setup_buffer": 25, - "globalroute__design__instance__count__stdcell": 62244, - "globalroute__design__instance__displacement__max": 7.12, - "globalroute__design__instance__displacement__mean": 0.0425, - "globalroute__design__instance__displacement__total": 2655.02, - "globalroute__design__instance__utilization": 0.509184, - "globalroute__design__instance__utilization__stdcell": 0.325398, - "globalroute__design__io": 3029, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 1706368.0, - "globalroute__power__internal__total": 0.0942858, - "globalroute__power__leakage__total": 0.0098665, - "globalroute__power__switching__total": 0.0377993, - "globalroute__power__total": 0.141952, - "globalroute__route__wirelength__estimated": 2550000.0, - "globalroute__runtime__total": "14:59.38", - "globalroute__timing__clock__slack": -0.682, - "globalroute__timing__drv__hold_violation_count": 21, - "globalroute__timing__drv__max_cap": 110, - "globalroute__timing__drv__max_cap_limit": -0.546583, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 4, - "globalroute__timing__drv__max_slew_limit": -0.242415, - "globalroute__timing__drv__setup_violation_count": 111, - "globalroute__timing__setup__tns": -68.4425, - "globalroute__timing__setup__ws": -0.681791, - "placeopt__cpu__total": 69.89, - "placeopt__design__core__area": 528365, - "placeopt__design__die__area": 560000, - "placeopt__design__instance__area": 264037, - "placeopt__design__instance__area__macros": 143946, - "placeopt__design__instance__area__stdcell": 120091, - "placeopt__design__instance__count": 58071, - "placeopt__design__instance__count__macros": 10, - "placeopt__design__instance__count__stdcell": 58061, - "placeopt__design__instance__utilization": 0.499724, - "placeopt__design__instance__utilization__stdcell": 0.312396, - "placeopt__design__io": 3029, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 533100.0, - "placeopt__power__internal__total": 0.0863651, - "placeopt__power__leakage__total": 0.00973354, - "placeopt__power__switching__total": 0.0259016, - "placeopt__power__total": 0.122, - "placeopt__runtime__total": "1:10.42", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00738371, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.350494, - "placeopt__timing__drv__setup_violation_count": 105, - "placeopt__timing__setup__tns": -9.54989, - "placeopt__timing__setup__ws": -0.167034, - "run__flow__design": "bp_be", - "run__flow__generate_date": "2024-10-15 22:51", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16535-g199588e84", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "a767acaf-69f2-477d-868f-54dced30b74f", - "run__flow__variant": "base", - "synth__cpu__total": 123.65, - "synth__design__instance__area__stdcell": 236465.222, - "synth__design__instance__count__stdcell": 51393.0, - "synth__mem__peak": 212008.0, - "synth__runtime__total": "2:04.51", - "total_time": "0:35:28.210000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 786ae3b754..f886e74244 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 271352.58, + "value": 268204.56, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 298541, + "value": 288926, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 66169, + "value": 62588, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5754, + "value": 5442, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5754, + "value": 5442, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3494576, + "value": 3302753, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.99, + "value": -0.35, "compare": ">=" }, "finish__design__instance__area": { - "value": 302367, + "value": 290373, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 2877, + "value": 2721, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 775, + "value": 100, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -46.18, + "value": -22.31, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index aa6cc60fe8..249771d43d 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v @@ -24,12 +19,15 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_512x64.lib \ export DIE_AREA = 0 0 800 600 export CORE_AREA = 10 10 790 590 -export PLACE_PINS_ARGS = -exclude left:400-700 -exclude right:400-700 -exclude top:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 -export PLACE_DENSITY_LB_ADDON = 0.10 -export PLACE_DENSITY_MAX_POST_HOLD = 0.12 +export PLACE_DENSITY_LB_ADDON = 0.11 +export PLACE_DENSITY_MAX_POST_HOLD = 0.13 export TNS_END_PERCENT = 100 + +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl + +export GPL_KEEP_OVERFLOW = 0 diff --git a/flow/designs/nangate45/bp_fe_top/constraint.sdc b/flow/designs/nangate45/bp_fe_top/constraint.sdc index b2d5405cf1..7428491fbe 100644 --- a/flow/designs/nangate45/bp_fe_top/constraint.sdc +++ b/flow/designs/nangate45/bp_fe_top/constraint.sdc @@ -1,4 +1,3 @@ - set clk_period 1.8 create_clock [get_ports clk_i] -name CLK -period $clk_period set io_delay [expr $clk_period * .2] diff --git a/flow/designs/nangate45/bp_fe_top/fastroute.tcl b/flow/designs/nangate45/bp_fe_top/fastroute.tcl new file mode 100644 index 0000000000..c7c32eb6f7 --- /dev/null +++ b/flow/designs/nangate45/bp_fe_top/fastroute.tcl @@ -0,0 +1,4 @@ +set_global_routing_layer_adjustment metal2-metal3 0.4 +set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.15 + +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/nangate45/bp_fe_top/io.tcl b/flow/designs/nangate45/bp_fe_top/io.tcl new file mode 100644 index 0000000000..82d99e921d --- /dev/null +++ b/flow/designs/nangate45/bp_fe_top/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:400-700 -region right:400-700 -region top:* diff --git a/flow/designs/nangate45/bp_fe_top/metadata-base-ok.json b/flow/designs/nangate45/bp_fe_top/metadata-base-ok.json deleted file mode 100644 index 1112317661..0000000000 --- a/flow/designs/nangate45/bp_fe_top/metadata-base-ok.json +++ /dev/null @@ -1,400 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 1.8000" - ], - "cts__clock__skew__hold": 0.116357, - "cts__clock__skew__setup": 0.116357, - "cts__cpu__total": 41.02, - "cts__design__core__area": 450857, - "cts__design__die__area": 480000, - "cts__design__instance__area": 234965, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 160975, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 73990, - "cts__design__instance__count": 41316, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 11, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 17, - "cts__design__instance__count__stdcell": 41305, - "cts__design__instance__displacement__max": 21.3975, - "cts__design__instance__displacement__mean": 0.0015, - "cts__design__instance__displacement__total": 69.6045, - "cts__design__instance__utilization": 0.521152, - "cts__design__instance__utilization__stdcell": 0.255242, - "cts__design__io": 2511, - "cts__design__rows": 1274, - "cts__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "cts__design__sites": 1042125, - "cts__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 717688.0, - "cts__power__internal__total": 0.114427, - "cts__power__leakage__total": 0.00953107, - "cts__power__switching__total": 0.0354627, - "cts__power__total": 0.15942, - "cts__route__wirelength__estimated": 2104970.0, - "cts__runtime__total": "0:41.43", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0606032, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.395136, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 2.86438e-05, - "design__io__hpwl": 1931048255, - "design__violations": 0, - "detailedplace__cpu__total": 28.36, - "detailedplace__design__core__area": 450857, - "detailedplace__design__die__area": 480000, - "detailedplace__design__instance__area": 233461, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 160975, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 72486.1, - "detailedplace__design__instance__count": 39972, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 11, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 39961, - "detailedplace__design__instance__displacement__max": 48.42, - "detailedplace__design__instance__displacement__mean": 0.8, - "detailedplace__design__instance__displacement__total": 31982.3, - "detailedplace__design__instance__utilization": 0.517816, - "detailedplace__design__instance__utilization__stdcell": 0.250054, - "detailedplace__design__io": 2511, - "detailedplace__design__rows": 1274, - "detailedplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "detailedplace__design__sites": 1042125, - "detailedplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 497800.0, - "detailedplace__power__internal__total": 0.108891, - "detailedplace__power__leakage__total": 0.00949559, - "detailedplace__power__switching__total": 0.0287823, - "detailedplace__power__total": 0.147169, - "detailedplace__route__wirelength__estimated": 2111040.0, - "detailedplace__runtime__total": "0:28.65", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0588472, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.395136, - "detailedplace__timing__drv__setup_violation_count": 45, - "detailedplace__timing__setup__tns": -2.07489, - "detailedplace__timing__setup__ws": -0.137713, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 22352, - "detailedroute__route__drc_errors__iter:1": 4401, - "detailedroute__route__drc_errors__iter:10": 147, - "detailedroute__route__drc_errors__iter:11": 28, - "detailedroute__route__drc_errors__iter:12": 1, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:2": 2699, - "detailedroute__route__drc_errors__iter:3": 1090, - "detailedroute__route__drc_errors__iter:4": 896, - "detailedroute__route__drc_errors__iter:5": 740, - "detailedroute__route__drc_errors__iter:6": 654, - "detailedroute__route__drc_errors__iter:7": 570, - "detailedroute__route__drc_errors__iter:8": 515, - "detailedroute__route__drc_errors__iter:9": 456, - "detailedroute__route__net": 44120, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 409007, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 409007, - "detailedroute__route__wirelength": 2777961, - "detailedroute__route__wirelength__iter:0": 2794445, - "detailedroute__route__wirelength__iter:1": 2780704, - "detailedroute__route__wirelength__iter:10": 2777847, - "detailedroute__route__wirelength__iter:11": 2777890, - "detailedroute__route__wirelength__iter:12": 2777962, - "detailedroute__route__wirelength__iter:13": 2777961, - "detailedroute__route__wirelength__iter:2": 2776179, - "detailedroute__route__wirelength__iter:3": 2776887, - "detailedroute__route__wirelength__iter:4": 2777062, - "detailedroute__route__wirelength__iter:5": 2777232, - "detailedroute__route__wirelength__iter:6": 2777366, - "detailedroute__route__wirelength__iter:7": 2777464, - "detailedroute__route__wirelength__iter:8": 2777575, - "detailedroute__route__wirelength__iter:9": 2777595, - "finish__clock__skew__hold": 0.198405, - "finish__clock__skew__setup": 0.198405, - "finish__cpu__total": 97.28, - "finish__design__core__area": 450857, - "finish__design__die__area": 480000, - "finish__design__instance__area": 235721, - "finish__design__instance__area__class:buffer": 8941.32, - "finish__design__instance__area__class:clock_buffer": 1279.73, - "finish__design__instance__area__class:clock_inverter": 191.254, - "finish__design__instance__area__class:inverter": 2042.61, - "finish__design__instance__area__class:macro": 160975, - "finish__design__instance__area__class:multi_input_combinational_cell": 36950.3, - "finish__design__instance__area__class:sequential_cell": 19834.3, - "finish__design__instance__area__class:timing_repair_buffer": 4644.89, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 160975, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 74745.7, - "finish__design__instance__count": 41603, - "finish__design__instance__count__class:buffer": 4170, - "finish__design__instance__count__class:clock_buffer": 1089, - "finish__design__instance__count__class:clock_inverter": 238, - "finish__design__instance__count__class:inverter": 3469, - "finish__design__instance__count__class:macro": 11, - "finish__design__instance__count__class:multi_input_combinational_cell": 22314, - "finish__design__instance__count__class:sequential_cell": 4315, - "finish__design__instance__count__class:timing_repair_buffer": 2759, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 11, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 41592, - "finish__design__instance__utilization": 0.522828, - "finish__design__instance__utilization__stdcell": 0.257849, - "finish__design__io": 2511, - "finish__design__rows": 1274, - "finish__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "finish__design__sites": 1042125, - "finish__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.08451, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0173162, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0351444, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0441022, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.06486, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0441022, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1260552.0, - "finish__power__internal__total": 0.114977, - "finish__power__leakage__total": 0.0095518, - "finish__power__switching__total": 0.0455775, - "finish__power__total": 0.170106, - "finish__runtime__total": "1:38.36", - "finish__timing__drv__hold_violation_count": 1603, - "finish__timing__drv__max_cap": 255, - "finish__timing__drv__max_cap_limit": -3.75515, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 37, - "finish__timing__drv__max_slew_limit": -1.51898, - "finish__timing__drv__setup_violation_count": 378, - "finish__timing__setup__tns": -47.4601, - "finish__timing__setup__ws": -0.566634, - "finish__timing__wns_percent_delay": -28.236818, - "finish_merge__cpu__total": 5.13, - "finish_merge__mem__peak": 775340.0, - "finish_merge__runtime__total": "0:05.55", - "floorplan__cpu__total": 9.87, - "floorplan__design__core__area": 450857, - "floorplan__design__die__area": 480000, - "floorplan__design__instance__area": 212666, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 160975, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 51690.4, - "floorplan__design__instance__count": 33199, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 11, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 33188, - "floorplan__design__instance__utilization": 0.471692, - "floorplan__design__instance__utilization__stdcell": 0.178315, - "floorplan__design__io": 2511, - "floorplan__design__rows": 413, - "floorplan__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 413, - "floorplan__design__sites": 1694952, - "floorplan__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1694952, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 3, - "floorplan__mem__peak": 270056.0, - "floorplan__power__internal__total": 0.0985009, - "floorplan__power__leakage__total": 0.00865656, - "floorplan__power__switching__total": 0.00905774, - "floorplan__power__total": 0.116215, - "floorplan__runtime__total": "0:10.07", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.0746403, - "floorplan_io__cpu__total": 0.59, - "floorplan_io__mem__peak": 182184.0, - "floorplan_io__runtime__total": "0:00.70", - "floorplan_macro__cpu__total": 217.89, - "floorplan_macro__mem__peak": 294556.0, - "floorplan_macro__runtime__total": "0:11.66", - "floorplan_pdn__cpu__total": 1.42, - "floorplan_pdn__mem__peak": 211216.0, - "floorplan_pdn__runtime__total": "0:01.55", - "floorplan_tap__cpu__total": 0.58, - "floorplan_tap__mem__peak": 164016.0, - "floorplan_tap__runtime__total": "0:00.69", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 922.54, - "globalplace__design__core__area": 450857, - "globalplace__design__die__area": 480000, - "globalplace__design__instance__area": 230211, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 160975, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 69235.8, - "globalplace__design__instance__count": 36935, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 11, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 36924, - "globalplace__design__instance__utilization": 0.510607, - "globalplace__design__instance__utilization__stdcell": 0.238841, - "globalplace__design__io": 2511, - "globalplace__design__rows": 1274, - "globalplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "globalplace__design__sites": 1042125, - "globalplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 768096.0, - "globalplace__power__internal__total": 0.108478, - "globalplace__power__leakage__total": 0.00938805, - "globalplace__power__switching__total": 0.027892, - "globalplace__power__total": 0.145758, - "globalplace__runtime__total": "2:22.83", - "globalplace__timing__setup__tns": -1.81731, - "globalplace__timing__setup__ws": -0.124353, - "globalplace_io__cpu__total": 1.05, - "globalplace_io__mem__peak": 192164.0, - "globalplace_io__runtime__total": "0:01.17", - "globalplace_skip_io__cpu__total": 280.77, - "globalplace_skip_io__mem__peak": 291880.0, - "globalplace_skip_io__runtime__total": "0:15.26", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.181507, - "globalroute__clock__skew__setup": 0.181507, - "globalroute__cpu__total": 2375.95, - "globalroute__design__core__area": 450857, - "globalroute__design__die__area": 480000, - "globalroute__design__instance__area": 235721, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 160975, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 74745.7, - "globalroute__design__instance__count": 41603, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 314, - "globalroute__design__instance__count__macros": 11, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 32, - "globalroute__design__instance__count__stdcell": 41592, - "globalroute__design__instance__displacement__max": 8.5, - "globalroute__design__instance__displacement__mean": 0.0285, - "globalroute__design__instance__displacement__total": 1202.66, - "globalroute__design__instance__utilization": 0.522828, - "globalroute__design__instance__utilization__stdcell": 0.257849, - "globalroute__design__io": 2511, - "globalroute__design__rows": 1274, - "globalroute__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "globalroute__design__sites": 1042125, - "globalroute__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 1357920.0, - "globalroute__power__internal__total": 0.114778, - "globalroute__power__leakage__total": 0.0095518, - "globalroute__power__switching__total": 0.0401903, - "globalroute__power__total": 0.16452, - "globalroute__route__wirelength__estimated": 2118910.0, - "globalroute__runtime__total": "38:59.51", - "globalroute__timing__clock__slack": -0.375, - "globalroute__timing__drv__hold_violation_count": 8, - "globalroute__timing__drv__max_cap": 131, - "globalroute__timing__drv__max_cap_limit": -2.93082, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 16, - "globalroute__timing__drv__max_slew_limit": -1.12874, - "globalroute__timing__drv__setup_violation_count": 132, - "globalroute__timing__setup__tns": -13.0616, - "globalroute__timing__setup__ws": -0.374922, - "placeopt__cpu__total": 25.52, - "placeopt__design__core__area": 450857, - "placeopt__design__die__area": 480000, - "placeopt__design__instance__area": 233461, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 160975, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 72486.1, - "placeopt__design__instance__count": 39972, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 11, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 39961, - "placeopt__design__instance__utilization": 0.517816, - "placeopt__design__instance__utilization__stdcell": 0.250054, - "placeopt__design__io": 2511, - "placeopt__design__rows": 1274, - "placeopt__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 1274, - "placeopt__design__sites": 1042125, - "placeopt__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1042125, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 422372.0, - "placeopt__power__internal__total": 0.1089, - "placeopt__power__leakage__total": 0.00949559, - "placeopt__power__switching__total": 0.0289618, - "placeopt__power__total": 0.147357, - "placeopt__runtime__total": "0:25.83", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0438253, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.395534, - "placeopt__timing__drv__setup_violation_count": 42, - "placeopt__timing__setup__tns": -1.81031, - "placeopt__timing__setup__ws": -0.124353, - "run__flow__design": "bp_fe", - "run__flow__generate_date": "2024-11-27 01:17", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17353-g10a5df25b", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "1e5c415d-d16c-4631-8f18-24a8ed5b3d7a", - "run__flow__variant": "base", - "synth__cpu__total": 48.91, - "synth__design__instance__area__stdcell": 212665.67, - "synth__design__instance__count__stdcell": 33199.0, - "synth__mem__peak": 116192.0, - "synth__runtime__total": "0:49.41", - "total_time": "0:46:12.670000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index 625c41c336..8ae464c9af 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 244565.53, + "value": 241575.35, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 263557, + "value": 252534, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 45648, + "value": 39729, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 3969, + "value": 3455, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 3969, + "value": 3455, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3194655, + "value": 2081448, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.59, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 265846, + "value": 254470, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1985, + "value": 1727, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 2104, + "value": 860, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -35.7, + "value": -12.16, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk index 71ce929ee1..e05d37d2e5 100644 --- a/flow/designs/nangate45/bp_multi_top/config.mk +++ b/flow/designs/nangate45/bp_multi_top/config.mk @@ -4,11 +4,6 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 # -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v @@ -31,10 +26,9 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_512x64.lib \ export DIE_AREA = 0 0 1100 1100 export CORE_AREA = 10.07 9.8 1090 1090 -export PLACE_PINS_ARGS = -exclude left:100-1100 -exclude right:100-1100 -exclude top:* +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 export PLACE_DENSITY_LB_ADDON = 0.05 export SKIP_GATE_CLONING = 1 diff --git a/flow/designs/nangate45/bp_multi_top/constraint.sdc b/flow/designs/nangate45/bp_multi_top/constraint.sdc index f9be728c02..24d87fe369 100644 --- a/flow/designs/nangate45/bp_multi_top/constraint.sdc +++ b/flow/designs/nangate45/bp_multi_top/constraint.sdc @@ -1,2906 +1,2905 @@ - -create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} -set_input_delay -clock CLK -max 1.8 [get_ports reset_i] -set_input_delay -clock CLK -min 0.6 [get_ports reset_i] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] -set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] +create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} +set_input_delay -clock CLK -max 1.8 [get_ports reset_i] +set_input_delay -clock CLK -min 0.6 [get_ports reset_i] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_data_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[541]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[540]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[539]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[538]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[537]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[536]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[535]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[534]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[533]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[532]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[531]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[530]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[529]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[528]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[527]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[526]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[525]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[524]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[523]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[522]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[521]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[520]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[519]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[518]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[517]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[516]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[515]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[514]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[513]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[512]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[511]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[510]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[509]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[508]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[507]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[506]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[505]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[504]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[503]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[502]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[501]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[500]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[499]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[498]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[497]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[496]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[495]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[494]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[493]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[492]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[491]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[490]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[489]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[488]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[487]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[486]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[485]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[484]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[483]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[482]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[481]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[480]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[479]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[478]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[477]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[476]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[475]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[474]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[473]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[472]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[471]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[470]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[469]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[468]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[467]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[466]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[465]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[464]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[463]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[462]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[461]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[460]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[459]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[458]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[457]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[456]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[455]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[454]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[453]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[452]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[451]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[450]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[449]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[448]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[447]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[446]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[445]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[444]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[443]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[442]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[441]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[440]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[439]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[438]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[437]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[436]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[435]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[434]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[433]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[432]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[431]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[430]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[429]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[428]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[427]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[426]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[425]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[424]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[423]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[422]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[421]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[420]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[419]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[418]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[417]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[416]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[415]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[414]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[413]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[412]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[411]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[410]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[409]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[408]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[407]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[406]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[405]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[404]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[403]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[402]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[401]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[400]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[399]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[398]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[397]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[396]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[395]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[394]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[393]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[392]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[391]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[390]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[389]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[388]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[387]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[386]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[385]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[384]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[383]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[382]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[381]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[380]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[379]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[378]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[377]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[376]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[375]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[374]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[373]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[372]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[371]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[370]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[369]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[368]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[367]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[366]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[365]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[364]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[363]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[362]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[361]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[360]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[359]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[358]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[357]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[356]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[355]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[354]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[353]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[352]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[351]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[350]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[349]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[348]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[347]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[346]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[345]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[344]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[343]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[342]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[341]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[340]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[339]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[338]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[337]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[336]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[335]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[334]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[333]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[332]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[331]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[330]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[329]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[328]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[327]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[326]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[325]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[324]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[323]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[322]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[321]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[320]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[319]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[318]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[317]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[316]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[315]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[314]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[313]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[312]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[311]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[310]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[309]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[308]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[307]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[306]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[305]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[304]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[303]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[302]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[301]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[300]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[299]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[298]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[297]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[296]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[295]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[294]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[293]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[292]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[291]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[290]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[289]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[288]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[287]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[286]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[285]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[284]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[283]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[282]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[281]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[280]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[279]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[278]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[277]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[276]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[275]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[274]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[273]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[272]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[271]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[270]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[269]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[268]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[267]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[266]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[265]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[264]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[263]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[262]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[261]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[260]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[259]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[258]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[257]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[256]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[255]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[254]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[253]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[252]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[251]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[250]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[249]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[248]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[247]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[246]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[245]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[244]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[243]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[242]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[241]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[240]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[239]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[238]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[237]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[236]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[235]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[234]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[233]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[232]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[231]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[230]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[229]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[228]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[227]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[226]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[225]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[224]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[223]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[222]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[221]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[220]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[219]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[218]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[217]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[216]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[215]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[214]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[213]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[212]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[211]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[210]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[209]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[208]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[207]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[206]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[205]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[204]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[203]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[202]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[201]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[200]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[199]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[198]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[197]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[196]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[195]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[194]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[193]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[192]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[191]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[190]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[189]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[188]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[187]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[186]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[185]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[184]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[183]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[182]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[181]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[180]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[179]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[178]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[177]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[176]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[175]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[174]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[173]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[172]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[171]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[170]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[169]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[168]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[167]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[166]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[165]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[164]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[163]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[162]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[161]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[160]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[159]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[158]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[157]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[156]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[155]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[154]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[153]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[152]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[151]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[150]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[149]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[148]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[147]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[146]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[145]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[144]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[143]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[142]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[141]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[140]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[139]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[138]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[137]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[136]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[135]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[134]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[133]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[132]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[131]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[130]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[129]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[128]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[127]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[126]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[125]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[124]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[123]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[122]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[121]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[120]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[119]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[118]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[117]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[116]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[115]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[114]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[113]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[112]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[111]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[110]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[109]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[108]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[107]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[106]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[105]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[104]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[103]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[102]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[101]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[100]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[99]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[98]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[97]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[96]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[95]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[94]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[93]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[92]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[91]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[90]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[89]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[88]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[87]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[86]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[85]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[84]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[83]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[82]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[81]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[80]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[79]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[78]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[77]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[76]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[75]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[74]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[73]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[72]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[71]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[70]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[69]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[68]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[67]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[66]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[65]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[64]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[63]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[62]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[61]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[60]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[59]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[58]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[57]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[56]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[55]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[54]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[53]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[52]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[51]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[50]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[49]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[48]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[47]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[46]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[45]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[44]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[43]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[42]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[41]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[40]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[39]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[38]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[37]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[36]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[35]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[34]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[33]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[32]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[31]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[30]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[29]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[28]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[27]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[26]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[25]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[24]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[23]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[22]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[21]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[20]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[19]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[18]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[17]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[16]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[15]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[14]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[13]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[12]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[11]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[10]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[9]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[8]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[7]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[6]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[5]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[4]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[3]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[2]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[1]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_v_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_cmd_yumi_i[0]}] +set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] +set_input_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_yumi_i[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cce_inst_boot_rom_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_resp_ready_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[569]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[568]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[567]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[566]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[565]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[564]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[563]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[562]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[561]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[560]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[559]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[558]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[557]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[556]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[555]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[554]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[553]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[552]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[551]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[550]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[549]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[548]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[547]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[546]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[545]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[544]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[543]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[542]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[541]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[540]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[539]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[538]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[537]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[536]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[535]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[534]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[533]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[532]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[531]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[530]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[529]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[528]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[527]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[526]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[525]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[524]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[523]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[522]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[521]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[520]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[519]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[518]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[517]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[516]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[515]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[514]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[513]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[512]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[511]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[510]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[509]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[508]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[507]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[506]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[505]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[504]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[503]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[502]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[501]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[500]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[499]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[498]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[497]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[496]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[495]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[494]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[493]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[492]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[491]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[490]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[489]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[488]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[487]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[486]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[485]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[484]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[483]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[482]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[481]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[480]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[479]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[478]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[477]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[476]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[475]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[474]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[473]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[472]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[471]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[470]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[469]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[468]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[467]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[466]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[465]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[464]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[463]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[462]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[461]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[460]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[459]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[458]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[457]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[456]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[455]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[454]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[453]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[452]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[451]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[450]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[449]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[448]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[447]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[446]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[445]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[444]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[443]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[442]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[441]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[440]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[439]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[438]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[437]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[436]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[435]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[434]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[433]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[432]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[431]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[430]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[429]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[428]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[427]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[426]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[425]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[424]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[423]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[422]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[421]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[420]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[419]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[418]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[417]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[416]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[415]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[414]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[413]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[412]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[411]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[410]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[409]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[408]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[407]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[406]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[405]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[404]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[403]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[402]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[401]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[400]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[399]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[398]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[397]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[396]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[395]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[394]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[393]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[392]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[391]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[390]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[389]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[388]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[387]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[386]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[385]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[384]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[383]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[382]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[381]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[380]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[379]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[378]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[377]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[376]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[375]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[374]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[373]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[372]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[371]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[370]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[369]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[368]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[367]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[366]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[365]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[364]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[363]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[362]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[361]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[360]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[359]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[358]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[357]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[356]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[355]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[354]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[353]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[352]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[351]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[350]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[349]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[348]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[347]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[346]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[345]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[344]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[343]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[342]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[341]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[340]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[339]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[338]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[337]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[336]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[335]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[334]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[333]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[332]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[331]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[330]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[329]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[328]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[327]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[326]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[325]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[324]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[323]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[322]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[321]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[320]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[319]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[318]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[317]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[316]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[315]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[314]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[313]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[312]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[311]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[310]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[309]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[308]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[307]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[306]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[305]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[304]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[303]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[302]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[301]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[300]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[299]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[298]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[297]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[296]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[295]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[294]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[293]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[292]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[291]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[290]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[289]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[288]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[287]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[286]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[285]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[284]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[283]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[282]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[281]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[280]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[279]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[278]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[277]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[276]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[275]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[274]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[273]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[272]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[271]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[270]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[269]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[268]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[267]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[266]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[265]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[264]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[263]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[262]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[261]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[260]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[259]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[258]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[257]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[256]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[255]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[254]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[253]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[252]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[251]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[250]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[249]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[248]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[247]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[246]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[245]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[244]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[243]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[242]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[241]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[240]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[239]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[238]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[237]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[236]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[235]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[234]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[233]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[232]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[231]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[230]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[229]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[228]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[227]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[226]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[225]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[224]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[223]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[222]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[221]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[220]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[219]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[218]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[217]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[216]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[215]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[214]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[213]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[212]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[211]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[210]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[209]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[208]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[207]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[206]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[205]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[204]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[203]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[202]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[201]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[200]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[199]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[198]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[197]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[196]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[195]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[194]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[193]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[192]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[191]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[190]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[189]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[188]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[187]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[186]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[185]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[184]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[183]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[182]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[181]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[180]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[179]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[178]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[177]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[176]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[175]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[174]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[173]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[172]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[171]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[170]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[169]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[168]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[167]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[166]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[165]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[164]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[163]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[162]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[161]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[160]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[159]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[158]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[157]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[156]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[155]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[154]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[153]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[152]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[151]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[150]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[149]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[148]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[147]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[146]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[145]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[144]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[143]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[142]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[141]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[140]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[139]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[138]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[137]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[136]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[135]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[134]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[133]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[132]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[131]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[130]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[129]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[128]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[127]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[126]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[125]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[124]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[123]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[122]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[121]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[120]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[119]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[118]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[117]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[116]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[115]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[114]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[113]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[112]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[111]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[110]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[109]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[108]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[107]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[106]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[105]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[104]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[103]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[102]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[101]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[100]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[99]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[98]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[97]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[96]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[95]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[94]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[93]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[92]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[91]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[90]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[89]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[88]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[87]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[86]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[85]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[84]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[83]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[82]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[81]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[80]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[79]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[78]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[77]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[76]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[75]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[74]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[73]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[72]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[71]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[70]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[69]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[68]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[67]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[66]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[65]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[64]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {mem_data_cmd_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_rd_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_w_v_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_addr_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_mem_op_o[0]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[63]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[62]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[61]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[60]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[59]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[58]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[57]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[56]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[55]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[54]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[53]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[52]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[51]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[50]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[49]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[48]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[47]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[46]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[45]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[44]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[43]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[42]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[41]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[40]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[39]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[38]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[37]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[36]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[35]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[34]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[33]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[32]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[31]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[30]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[29]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[28]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[27]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[26]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[25]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[24]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[23]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[22]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[21]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[20]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[19]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[18]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[17]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[16]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[15]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[14]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[13]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[12]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[11]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[10]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[9]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[8]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[7]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[6]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[5]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[4]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[3]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[2]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[1]}] +set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] +set_output_delay -clock CLK -min 0.6 [get_ports {cmt_data_o[0]}] diff --git a/flow/designs/nangate45/bp_multi_top/io.tcl b/flow/designs/nangate45/bp_multi_top/io.tcl new file mode 100644 index 0000000000..46c1375a1d --- /dev/null +++ b/flow/designs/nangate45/bp_multi_top/io.tcl @@ -0,0 +1 @@ +exclude_io_pin_region -region left:100-1100 -region right:100-1100 -region top:* diff --git a/flow/designs/nangate45/bp_multi_top/metadata-base-ok.json b/flow/designs/nangate45/bp_multi_top/metadata-base-ok.json deleted file mode 100644 index 1141b726d4..0000000000 --- a/flow/designs/nangate45/bp_multi_top/metadata-base-ok.json +++ /dev/null @@ -1,327 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 4.8000" - ], - "cts__clock__skew__hold": 0.120627, - "cts__clock__skew__setup": 0.120627, - "cts__cpu__total": 113.7, - "cts__design__core__area": 1165500.0, - "cts__design__die__area": 1210000.0, - "cts__design__instance__area": 583042, - "cts__design__instance__area__macros": 332943, - "cts__design__instance__area__stdcell": 250099, - "cts__design__instance__count": 169032, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 26, - "cts__design__instance__count__setup_buffer": 4, - "cts__design__instance__count__stdcell": 169006, - "cts__design__instance__displacement__max": 1.995, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 23.147, - "cts__design__instance__utilization": 0.500249, - "cts__design__instance__utilization__stdcell": 0.300397, - "cts__design__io": 1453, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1327124.0, - "cts__power__internal__total": 0.0862236, - "cts__power__leakage__total": 0.0212339, - "cts__power__switching__total": 0.0181945, - "cts__power__total": 0.125652, - "cts__route__wirelength__estimated": 4316540.0, - "cts__runtime__total": "1:54.77", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0407312, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.401369, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__setup__tns": -1.76784, - "cts__timing__setup__ws": -1.76784, - "design__io__hpwl": 1146653532, - "design__violations": 0, - "detailedplace__cpu__total": 117.5, - "detailedplace__design__core__area": 1165500.0, - "detailedplace__design__die__area": 1210000.0, - "detailedplace__design__instance__area": 576397, - "detailedplace__design__instance__area__macros": 332943, - "detailedplace__design__instance__area__stdcell": 243454, - "detailedplace__design__instance__count": 163148, - "detailedplace__design__instance__count__macros": 26, - "detailedplace__design__instance__count__stdcell": 163122, - "detailedplace__design__instance__displacement__max": 60.0905, - "detailedplace__design__instance__displacement__mean": 0.7185, - "detailedplace__design__instance__displacement__total": 117253, - "detailedplace__design__instance__utilization": 0.494547, - "detailedplace__design__instance__utilization__stdcell": 0.292415, - "detailedplace__design__io": 1453, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1009288.0, - "detailedplace__power__internal__total": 0.0767285, - "detailedplace__power__leakage__total": 0.0210808, - "detailedplace__power__switching__total": 0.00747716, - "detailedplace__power__total": 0.105286, - "detailedplace__route__wirelength__estimated": 4269230.0, - "detailedplace__runtime__total": "1:58.29", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.036303, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.399099, - "detailedplace__timing__drv__setup_violation_count": 1, - "detailedplace__timing__setup__tns": -1.8443, - "detailedplace__timing__setup__ws": -1.8443, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 35295, - "detailedroute__route__drc_errors__iter:10": 32, - "detailedroute__route__drc_errors__iter:11": 15, - "detailedroute__route__drc_errors__iter:12": 0, - "detailedroute__route__drc_errors__iter:2": 7300, - "detailedroute__route__drc_errors__iter:3": 4789, - "detailedroute__route__drc_errors__iter:4": 257, - "detailedroute__route__drc_errors__iter:5": 88, - "detailedroute__route__drc_errors__iter:6": 72, - "detailedroute__route__drc_errors__iter:7": 62, - "detailedroute__route__drc_errors__iter:8": 45, - "detailedroute__route__drc_errors__iter:9": 39, - "detailedroute__route__net": 180875, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1093776, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1093776, - "detailedroute__route__wirelength": 4798211, - "detailedroute__route__wirelength__iter:1": 4812444, - "detailedroute__route__wirelength__iter:10": 4798133, - "detailedroute__route__wirelength__iter:11": 4798204, - "detailedroute__route__wirelength__iter:12": 4798211, - "detailedroute__route__wirelength__iter:2": 4799479, - "detailedroute__route__wirelength__iter:3": 4797409, - "detailedroute__route__wirelength__iter:4": 4797994, - "detailedroute__route__wirelength__iter:5": 4798053, - "detailedroute__route__wirelength__iter:6": 4798089, - "detailedroute__route__wirelength__iter:7": 4798102, - "detailedroute__route__wirelength__iter:8": 4798106, - "detailedroute__route__wirelength__iter:9": 4798135, - "finish__clock__skew__hold": 0.128682, - "finish__clock__skew__setup": 0.128682, - "finish__cpu__total": 350.2, - "finish__design__core__area": 1165500.0, - "finish__design__die__area": 1210000.0, - "finish__design__instance__area": 583100, - "finish__design__instance__area__macros": 332943, - "finish__design__instance__area__stdcell": 250157, - "finish__design__instance__count": 169038, - "finish__design__instance__count__macros": 26, - "finish__design__instance__count__stdcell": 169012, - "finish__design__instance__utilization": 0.500299, - "finish__design__instance__utilization__stdcell": 0.300467, - "finish__design__io": 1453, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.09635, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00335551, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0113992, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0111108, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.0886, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0111108, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 3197648.0, - "finish__power__internal__total": 0.0862426, - "finish__power__leakage__total": 0.0212366, - "finish__power__switching__total": 0.0191381, - "finish__power__total": 0.126617, - "finish__runtime__total": "5:54.31", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 8, - "finish__timing__drv__max_cap_limit": -0.237704, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.265068, - "finish__timing__drv__setup_violation_count": 1, - "finish__timing__setup__tns": -1.92603, - "finish__timing__setup__ws": -1.92603, - "finish__timing__wns_percent_delay": -26.618755, - "finish_merge__cpu__total": 14.48, - "finish_merge__mem__peak": 1767220.0, - "finish_merge__runtime__total": "0:15.83", - "floorplan__cpu__total": 51.17, - "floorplan__design__core__area": 1165500.0, - "floorplan__design__die__area": 1210000.0, - "floorplan__design__instance__area": 550926, - "floorplan__design__instance__area__macros": 332943, - "floorplan__design__instance__area__stdcell": 217983, - "floorplan__design__instance__count": 152650, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 26, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 152624, - "floorplan__design__instance__utilization": 0.472694, - "floorplan__design__instance__utilization__stdcell": 0.261822, - "floorplan__design__io": 1453, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 314, - "floorplan__mem__peak": 721512.0, - "floorplan__power__internal__total": 0.0756186, - "floorplan__power__leakage__total": 0.0200848, - "floorplan__power__switching__total": 0.00444122, - "floorplan__power__total": 0.100145, - "floorplan__runtime__total": "0:58.23", - "floorplan__timing__setup__tns": -0.812897, - "floorplan__timing__setup__ws": -0.812897, - "floorplan_io__cpu__total": 1.19, - "floorplan_io__mem__peak": 368436.0, - "floorplan_io__runtime__total": "0:01.45", - "floorplan_macro__cpu__total": 461.94, - "floorplan_macro__mem__peak": 774096.0, - "floorplan_macro__runtime__total": "1:30.80", - "floorplan_pdn__cpu__total": 9.51, - "floorplan_pdn__mem__peak": 470352.0, - "floorplan_pdn__runtime__total": "0:11.06", - "floorplan_tap__cpu__total": 9.55, - "floorplan_tap__mem__peak": 285464.0, - "floorplan_tap__runtime__total": "0:11.16", - "floorplan_tdms__cpu__total": 0.05, - "floorplan_tdms__mem__peak": 100592.0, - "floorplan_tdms__runtime__total": "0:00.20", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 4379.2, - "globalplace__design__core__area": 1165500.0, - "globalplace__design__die__area": 1210000.0, - "globalplace__design__instance__area": 552950, - "globalplace__design__instance__area__macros": 332943, - "globalplace__design__instance__area__stdcell": 220007, - "globalplace__design__instance__count": 160259, - "globalplace__design__instance__count__macros": 26, - "globalplace__design__instance__count__stdcell": 160233, - "globalplace__design__instance__utilization": 0.47443, - "globalplace__design__instance__utilization__stdcell": 0.264253, - "globalplace__design__io": 1453, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1884984.0, - "globalplace__power__internal__total": 0.0757207, - "globalplace__power__leakage__total": 0.0200848, - "globalplace__power__switching__total": 0.00695964, - "globalplace__power__total": 0.102765, - "globalplace__runtime__total": "14:21.66", - "globalplace__timing__setup__tns": -1.84063, - "globalplace__timing__setup__ws": -1.84063, - "globalplace_io__cpu__total": 1.64, - "globalplace_io__mem__peak": 390852.0, - "globalplace_io__runtime__total": "0:02.11", - "globalplace_skip_io__cpu__total": 622.76, - "globalplace_skip_io__mem__peak": 681908.0, - "globalplace_skip_io__runtime__total": "2:33.82", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.119135, - "globalroute__clock__skew__setup": 0.119135, - "globalroute__cpu__total": 385.79, - "globalroute__design__core__area": 1165500.0, - "globalroute__design__die__area": 1210000.0, - "globalroute__design__instance__area": 583100, - "globalroute__design__instance__area__macros": 332943, - "globalroute__design__instance__area__stdcell": 250157, - "globalroute__design__instance__count": 169038, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 26, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 169012, - "globalroute__design__instance__displacement__max": 1.59, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 24.91, - "globalroute__design__instance__utilization": 0.500299, - "globalroute__design__instance__utilization__stdcell": 0.300467, - "globalroute__design__io": 1453, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 2554348.0, - "globalroute__power__internal__total": 0.086186, - "globalroute__power__leakage__total": 0.0212366, - "globalroute__power__switching__total": 0.0185078, - "globalroute__power__total": 0.12593, - "globalroute__route__wirelength__estimated": 4316730.0, - "globalroute__runtime__total": "4:19.98", - "globalroute__timing__clock__slack": -1.928, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 4, - "globalroute__timing__drv__max_cap_limit": -0.151877, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.324243, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -1.92797, - "globalroute__timing__setup__ws": -1.92797, - "placeopt__cpu__total": 86.79, - "placeopt__design__core__area": 1165500.0, - "placeopt__design__die__area": 1210000.0, - "placeopt__design__instance__area": 576397, - "placeopt__design__instance__area__macros": 332943, - "placeopt__design__instance__area__stdcell": 243454, - "placeopt__design__instance__count": 163148, - "placeopt__design__instance__count__macros": 26, - "placeopt__design__instance__count__stdcell": 163122, - "placeopt__design__instance__utilization": 0.494547, - "placeopt__design__instance__utilization__stdcell": 0.292415, - "placeopt__design__io": 1453, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1017688.0, - "placeopt__power__internal__total": 0.0767293, - "placeopt__power__leakage__total": 0.0210808, - "placeopt__power__switching__total": 0.00750709, - "placeopt__power__total": 0.105317, - "placeopt__runtime__total": "1:27.59", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0384849, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.4006, - "placeopt__timing__drv__setup_violation_count": 1, - "placeopt__timing__setup__tns": -1.84611, - "placeopt__timing__setup__ws": -1.84611, - "run__flow__design": "bp_multi", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "ae3654ab-272b-4138-b6ed-db38a72a220b", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 220.65, - "synth__design__instance__area__stdcell": 550926.128, - "synth__design__instance__count__stdcell": 152650.0, - "synth__mem__peak": 497232.0, - "synth__runtime__total": "4:21.51", - "total_time": "0:40:02.770000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/bp_multi_top/rules-base.json b/flow/designs/nangate45/bp_multi_top/rules-base.json index 4aa4273f85..0f31b3dbc0 100644 --- a/flow/designs/nangate45/bp_multi_top/rules-base.json +++ b/flow/designs/nangate45/bp_multi_top/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 633565.05, + "value": 586679.15, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 662857, + "value": 607245, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 187590, + "value": 143977, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 16312, + "value": 12520, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 16312, + "value": 12520, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5517943, + "value": 4291357, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -2.16, + "value": -4.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 670565, + "value": 616495, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 8156, + "value": 6260, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -41.94, + "value": -57.81, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_quad/bsg_chip.sdc b/flow/designs/nangate45/bp_quad/bsg_chip.sdc index c7eb8079c0..d89a844195 100644 --- a/flow/designs/nangate45/bp_quad/bsg_chip.sdc +++ b/flow/designs/nangate45/bp_quad/bsg_chip.sdc @@ -1,161 +1,147 @@ +################################################################### + +# Created by write_sdc on Wed Sep 29 06:31:20 2021 + +################################################################### set sdc_version 2.0 +set clk_period 3 +set clk_uncertainty 150 +set bp_clk_hp [expr ${clk_period}/2] +set l_clk_p1 [expr ${clk_period}*2] +set l_clk_p2 [expr ${clk_period}*4] +set wv1 [list 0 $bp_clk_hp] +set wv2 [list 0 $clk_period] +set wv3 [list 0 $l_clk_p1] +set mx_delay1 [expr ${l_clk_p1}*0.28] +set mx_delay2 [expr ${l_clk_p2}*0.28] +set mn_delay1 [expr ${l_clk_p1}*0.02] -# Set the current design -current_design bsg_chip -create_clock -name "tag_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_bsg_tag_clk_i] -create_clock -name "bp_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_clk_A_i] -create_clock -name "io_master_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_clk_B_i] -create_clock -name "router_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_clk_C_i] -create_clock -name "sdi_a_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_ci_clk_i] -create_clock -name "sdo_a_tkn_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_ci2_tkn_i] -create_clock -name "sdi_b_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_co_clk_i] -create_clock -name "sdo_b_tkn_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_co2_tkn_i] -set_false_path -from [list \ - [get_clocks router_clk] \ - [get_clocks tag_clk] ] -to [get_clocks bp_clk] -set_multicycle_path -to [list \ - [get_ports p_ci2_8_o] \ - [get_ports p_ci2_7_o] \ - [get_ports p_ci2_6_o] \ - [get_ports p_ci2_5_o] \ - [get_ports p_ci2_4_o] \ - [get_ports p_ci2_3_o] \ - [get_ports p_ci2_2_o] \ - [get_ports p_ci2_1_o] \ - [get_ports p_ci2_0_o] \ - [get_ports p_ci2_v_o] \ - [get_ports p_ci2_clk_o] \ - [get_ports p_co2_8_o] \ - [get_ports p_co2_7_o] \ - [get_ports p_co2_6_o] \ - [get_ports p_co2_5_o] \ - [get_ports p_co2_4_o] \ - [get_ports p_co2_3_o] \ - [get_ports p_co2_2_o] \ - [get_ports p_co2_1_o] \ - [get_ports p_co2_0_o] \ - [get_ports p_co2_v_o] \ - [get_ports p_co2_clk_o] ] -hold -start 0 -set_multicycle_path -to [list \ - [get_ports p_ci2_8_o] \ - [get_ports p_ci2_7_o] \ - [get_ports p_ci2_6_o] \ - [get_ports p_ci2_5_o] \ - [get_ports p_ci2_4_o] \ - [get_ports p_ci2_3_o] \ - [get_ports p_ci2_2_o] \ - [get_ports p_ci2_1_o] \ - [get_ports p_ci2_0_o] \ - [get_ports p_ci2_v_o] \ - [get_ports p_ci2_clk_o] \ - [get_ports p_co2_8_o] \ - [get_ports p_co2_7_o] \ - [get_ports p_co2_6_o] \ - [get_ports p_co2_5_o] \ - [get_ports p_co2_4_o] \ - [get_ports p_co2_3_o] \ - [get_ports p_co2_2_o] \ - [get_ports p_co2_1_o] \ - [get_ports p_co2_0_o] \ - [get_ports p_co2_v_o] \ - [get_ports p_co2_clk_o] ] -setup -end 1 -set_clock_gating_check -setup 0.0 -set_input_delay -clock [get_clocks tag_clk] -add_delay 1.456 [get_ports p_bsg_tag_data_i] -set_input_delay -clock [get_clocks tag_clk] -add_delay 1.456 [get_ports p_bsg_tag_en_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_v_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_v_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_v_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_v_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_0_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_0_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_0_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_0_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_1_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_1_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_1_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_1_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_2_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_2_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_2_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_2_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_3_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_3_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_3_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_3_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_4_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_4_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_4_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_4_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_5_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_5_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_5_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_5_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_6_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_6_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_6_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_6_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_7_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_7_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_7_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_7_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_8_i] -set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_8_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_8_i] -set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_8_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_v_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_v_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_v_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_v_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_0_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_0_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_0_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_0_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_1_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_1_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_1_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_1_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_2_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_2_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_2_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_2_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_3_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_3_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_3_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_3_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_4_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_4_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_4_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_4_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_5_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_5_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_5_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_5_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_6_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_6_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_6_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_6_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_7_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_7_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_7_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_7_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_8_i] -set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_8_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_8_i] -set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_8_i] -set_wire_load_mode "enclosed" -set_clock_uncertainty -hold 0.15 [get_clocks tag_clk] -set_clock_uncertainty -setup 0.15 [get_clocks bp_clk] -set_clock_uncertainty -hold 0.15 [get_clocks bp_clk] -set_clock_uncertainty -setup 0.15 [get_clocks io_master_clk] -set_clock_uncertainty -hold 0.15 [get_clocks io_master_clk] -set_clock_uncertainty -setup 0.15 [get_clocks router_clk] -set_clock_uncertainty -hold 0.15 [get_clocks router_clk] -set_clock_uncertainty -setup 0.15 [get_clocks sdi_a_clk] -set_clock_uncertainty -hold 0.15 [get_clocks sdi_a_clk] -set_clock_uncertainty -setup 0.15 [get_clocks sdo_a_tkn_clk] -set_clock_uncertainty -hold 0.15 [get_clocks sdo_a_tkn_clk] -set_clock_uncertainty -setup 0.15 [get_clocks sdi_b_clk] -set_clock_uncertainty -hold 0.15 [get_clocks sdi_b_clk] -set_clock_uncertainty -setup 0.15 [get_clocks sdo_b_tkn_clk] -set_clock_uncertainty -hold 0.15 [get_clocks sdo_b_tkn_clk] +set_units -time ps -resistance kOhm -capacitance fF -power mW -voltage V \ + -current uA +create_clock [get_ports p_bsg_tag_clk_i] -name tag_clk -period $l_clk_p2 -waveform $wv3 +set_clock_uncertainty -hold $clk_uncertainty [get_clocks tag_clk] +create_clock [get_ports p_clk_A_i] -name bp_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks bp_clk] +create_clock [get_ports p_clk_B_i] -name io_master_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks io_master_clk] +create_clock [get_ports p_clk_C_i] -name router_clk -period $clk_period -waveform $wv1 +set_clock_uncertainty $clk_uncertainty [get_clocks router_clk] +create_clock [get_ports p_ci_clk_i] -name sdi_a_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_a_clk] +create_clock [get_ports p_ci2_tkn_i] -name sdo_a_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_a_tkn_clk] +create_clock [get_ports p_co_clk_i] -name sdi_b_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdi_b_clk] +create_clock [get_ports p_co2_tkn_i] -name sdo_b_tkn_clk -period $l_clk_p1 -waveform $wv2 +set_clock_uncertainty $clk_uncertainty [get_clocks sdo_b_tkn_clk] +# +set_multicycle_path 0 -hold -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_ci2_clk_o] [get_ports \ + p_ci2_v_o] [get_ports p_ci2_0_o] [get_ports p_ci2_1_o] [get_ports p_ci2_2_o] \ + [get_ports p_ci2_3_o] [get_ports p_ci2_4_o] [get_ports p_ci2_5_o] [get_ports \ + p_ci2_6_o] [get_ports p_ci2_7_o] [get_ports p_ci2_8_o]] +set_multicycle_path 0 -hold -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_multicycle_path 1 -setup -to [list [get_ports p_co2_clk_o] [get_ports \ + p_co2_v_o] [get_ports p_co2_0_o] [get_ports p_co2_1_o] [get_ports p_co2_2_o] \ + [get_ports p_co2_3_o] [get_ports p_co2_4_o] [get_ports p_co2_5_o] [get_ports \ + p_co2_6_o] [get_ports p_co2_7_o] [get_ports p_co2_8_o]] +set_false_path -from [get_clocks router_clk] -to [get_clocks bp_clk] +set_false_path -from [get_clocks tag_clk] -to [get_clocks bp_clk] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_clk_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_clk_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_data_i] +set_input_delay -clock tag_clk $mx_delay2 [get_ports p_bsg_tag_en_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_v_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_0_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_1_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_2_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_3_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_4_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_5_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_6_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_7_i] +set_input_delay -clock sdi_a_clk -max $mx_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -min $mn_delay1 [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_a_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_ci_8_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_v_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_0_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_1_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_2_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_3_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_4_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_5_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_6_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_7_i] +set_input_delay -clock sdi_b_clk -max $mx_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -min $mn_delay1 [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -max $mx_delay1 -add_delay [get_ports p_co_8_i] +set_input_delay -clock sdi_b_clk -clock_fall -min $mn_delay1 -add_delay [get_ports p_co_8_i] +set_timing_derate -early -cell_delay 0.97 [get_cells {bp_processor/cc/y_0__x_0__tile_node/tile/core/fe/mem/icache/tag_mem/macro_bmem/db1_wb_0__bank/macro_mem}] ;# tclint-disable-line line-length diff --git a/flow/designs/nangate45/bp_quad/config.mk b/flow/designs/nangate45/bp_quad/config.mk index 4064f9bb17..fef7ec8e91 100644 --- a/flow/designs/nangate45/bp_quad/config.mk +++ b/flow/designs/nangate45/bp_quad/config.mk @@ -32,7 +32,6 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x48.lib \ export DIE_AREA = 0 0 3600 3600 export CORE_AREA = 10 12 3590 3590 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:2400-3600 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 diff --git a/flow/designs/nangate45/bp_quad/io.tcl b/flow/designs/nangate45/bp_quad/io.tcl new file mode 100644 index 0000000000..41bce8db56 --- /dev/null +++ b/flow/designs/nangate45/bp_quad/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-1000 -region bottom:2400-3600 diff --git a/flow/designs/nangate45/dynamic_node/metadata-base-ok.json b/flow/designs/nangate45/dynamic_node/metadata-base-ok.json deleted file mode 100644 index 4dfa6a8a8e..0000000000 --- a/flow/designs/nangate45/dynamic_node/metadata-base-ok.json +++ /dev/null @@ -1,317 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 6.0000" - ], - "cts__clock__skew__hold": 0.0182687, - "cts__clock__skew__setup": 0.0182687, - "cts__cpu__total": 45.72, - "cts__design__core__area": 55457.8, - "cts__design__die__area": 60557.8, - "cts__design__instance__area": 25694.3, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 25694.3, - "cts__design__instance__count": 12602, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 95, - "cts__design__instance__count__stdcell": 12602, - "cts__design__instance__displacement__max": 7.03, - "cts__design__instance__displacement__mean": 0.06, - "cts__design__instance__displacement__total": 761.178, - "cts__design__instance__utilization": 0.463312, - "cts__design__instance__utilization__stdcell": 0.463312, - "cts__design__io": 693, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 465084.0, - "cts__power__internal__total": 0.0100286, - "cts__power__leakage__total": 0.000557966, - "cts__power__switching__total": 0.00597092, - "cts__power__total": 0.0165575, - "cts__route__wirelength__estimated": 193998, - "cts__runtime__total": "0:46.03", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.370086, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.497823, - "cts__timing__drv__setup_violation_count": 6, - "cts__timing__setup__tns": -0.699923, - "cts__timing__setup__ws": -0.269078, - "design__io__hpwl": 117477507, - "design__violations": 0, - "detailedplace__cpu__total": 9.76, - "detailedplace__design__core__area": 55457.8, - "detailedplace__design__die__area": 60557.8, - "detailedplace__design__instance__area": 24550.2, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 24550.2, - "detailedplace__design__instance__count": 11834, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 11834, - "detailedplace__design__instance__displacement__max": 6.2085, - "detailedplace__design__instance__displacement__mean": 1.3855, - "detailedplace__design__instance__displacement__total": 16398.9, - "detailedplace__design__instance__utilization": 0.442683, - "detailedplace__design__instance__utilization__stdcell": 0.442683, - "detailedplace__design__io": 693, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 186776.0, - "detailedplace__power__internal__total": 0.00905872, - "detailedplace__power__leakage__total": 0.000521616, - "detailedplace__power__switching__total": 0.00500719, - "detailedplace__power__total": 0.0145875, - "detailedplace__route__wirelength__estimated": 189965, - "detailedplace__runtime__total": "0:09.87", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.370384, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.498223, - "detailedplace__timing__drv__setup_violation_count": 2, - "detailedplace__timing__setup__tns": -0.175853, - "detailedplace__timing__setup__ws": -0.146124, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 2997, - "detailedroute__route__drc_errors__iter:2": 1084, - "detailedroute__route__drc_errors__iter:3": 907, - "detailedroute__route__drc_errors__iter:4": 103, - "detailedroute__route__drc_errors__iter:5": 6, - "detailedroute__route__drc_errors__iter:6": 3, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 14695, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 91196, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 91196, - "detailedroute__route__wirelength": 227143, - "detailedroute__route__wirelength__iter:1": 228243, - "detailedroute__route__wirelength__iter:2": 227118, - "detailedroute__route__wirelength__iter:3": 226985, - "detailedroute__route__wirelength__iter:4": 227153, - "detailedroute__route__wirelength__iter:5": 227142, - "detailedroute__route__wirelength__iter:6": 227142, - "detailedroute__route__wirelength__iter:7": 227143, - "finish__clock__skew__hold": 0.0175844, - "finish__clock__skew__setup": 0.0175844, - "finish__cpu__total": 22.31, - "finish__design__core__area": 55457.8, - "finish__design__die__area": 60557.8, - "finish__design__instance__area": 25723.5, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 25723.5, - "finish__design__instance__count": 12611, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 12611, - "finish__design__instance__utilization": 0.46384, - "finish__design__instance__utilization__stdcell": 0.46384, - "finish__design__io": 693, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.05099, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0314814, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0923725, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0625363, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.00763, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0625363, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 540608.0, - "finish__power__internal__total": 0.0100494, - "finish__power__leakage__total": 0.00055922, - "finish__power__switching__total": 0.00639342, - "finish__power__total": 0.017002, - "finish__runtime__total": "0:22.62", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.387852, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.487153, - "finish__timing__drv__setup_violation_count": 11, - "finish__timing__setup__tns": -0.763018, - "finish__timing__setup__ws": -0.272717, - "finish__timing__wns_percent_delay": -23.254029, - "finish_merge__cpu__total": 2.03, - "finish_merge__mem__peak": 481952.0, - "finish_merge__runtime__total": "0:02.28", - "floorplan__cpu__total": 10.76, - "floorplan__design__core__area": 55457.8, - "floorplan__design__die__area": 60557.8, - "floorplan__design__instance__area": 22340.8, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 22340.8, - "floorplan__design__instance__count": 10785, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 10785, - "floorplan__design__instance__utilization": 0.402843, - "floorplan__design__instance__utilization__stdcell": 0.402843, - "floorplan__design__io": 693, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 34, - "floorplan__mem__peak": 168176.0, - "floorplan__power__internal__total": 0.00782668, - "floorplan__power__leakage__total": 0.000438603, - "floorplan__power__switching__total": 0.00267389, - "floorplan__power__total": 0.0109392, - "floorplan__runtime__total": "0:10.85", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.0026818, - "floorplan_io__cpu__total": 0.34, - "floorplan_io__mem__peak": 138028.0, - "floorplan_io__runtime__total": "0:00.41", - "floorplan_macro__cpu__total": 0.35, - "floorplan_macro__mem__peak": 137344.0, - "floorplan_macro__runtime__total": "0:00.41", - "floorplan_pdn__cpu__total": 0.4, - "floorplan_pdn__mem__peak": 141444.0, - "floorplan_pdn__runtime__total": "0:00.49", - "floorplan_tap__cpu__total": 0.35, - "floorplan_tap__mem__peak": 130684.0, - "floorplan_tap__runtime__total": "0:00.41", - "floorplan_tdms__cpu__total": 0.33, - "floorplan_tdms__mem__peak": 136952.0, - "floorplan_tdms__runtime__total": "0:00.41", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 878.05, - "globalplace__design__core__area": 55457.8, - "globalplace__design__die__area": 60557.8, - "globalplace__design__instance__area": 22452.8, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 22452.8, - "globalplace__design__instance__count": 11206, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 11206, - "globalplace__design__instance__utilization": 0.404863, - "globalplace__design__instance__utilization__stdcell": 0.404863, - "globalplace__design__io": 693, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 502188.0, - "globalplace__power__internal__total": 0.00788485, - "globalplace__power__leakage__total": 0.000438603, - "globalplace__power__switching__total": 0.00425155, - "globalplace__power__total": 0.012575, - "globalplace__runtime__total": "1:30.88", - "globalplace__timing__setup__tns": -0.170985, - "globalplace__timing__setup__ws": -0.14774, - "globalplace_io__cpu__total": 0.45, - "globalplace_io__mem__peak": 140684.0, - "globalplace_io__runtime__total": "0:00.54", - "globalplace_skip_io__cpu__total": 499.74, - "globalplace_skip_io__mem__peak": 156976.0, - "globalplace_skip_io__runtime__total": "0:34.29", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.015812, - "globalroute__clock__skew__setup": 0.015812, - "globalroute__cpu__total": 36.75, - "globalroute__design__core__area": 55457.8, - "globalroute__design__die__area": 60557.8, - "globalroute__design__instance__area": 25723.5, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 25723.5, - "globalroute__design__instance__count": 12611, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 12, - "globalroute__design__instance__count__stdcell": 12611, - "globalroute__design__instance__displacement__max": 5.6, - "globalroute__design__instance__displacement__mean": 0.013, - "globalroute__design__instance__displacement__total": 168.02, - "globalroute__design__instance__utilization": 0.46384, - "globalroute__design__instance__utilization__stdcell": 0.46384, - "globalroute__design__io": 693, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 546120.0, - "globalroute__power__internal__total": 0.0100489, - "globalroute__power__leakage__total": 0.00055922, - "globalroute__power__switching__total": 0.00630993, - "globalroute__power__total": 0.016918, - "globalroute__route__wirelength__estimated": 194242, - "globalroute__runtime__total": "0:24.81", - "globalroute__timing__clock__slack": -0.256, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.363072, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.48686, - "globalroute__timing__drv__setup_violation_count": 6, - "globalroute__timing__setup__tns": -0.640226, - "globalroute__timing__setup__ws": -0.25617, - "placeopt__cpu__total": 9.6, - "placeopt__design__core__area": 55457.8, - "placeopt__design__die__area": 60557.8, - "placeopt__design__instance__area": 24550.2, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 24550.2, - "placeopt__design__instance__count": 11834, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 11834, - "placeopt__design__instance__utilization": 0.442683, - "placeopt__design__instance__utilization__stdcell": 0.442683, - "placeopt__design__io": 693, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 366332.0, - "placeopt__power__internal__total": 0.00905443, - "placeopt__power__leakage__total": 0.000521616, - "placeopt__power__switching__total": 0.00494781, - "placeopt__power__total": 0.0145239, - "placeopt__runtime__total": "0:09.85", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.36663, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.502519, - "placeopt__timing__drv__setup_violation_count": 2, - "placeopt__timing__setup__tns": -0.173798, - "placeopt__timing__setup__ws": -0.14315, - "run__flow__design": "dynamic_node", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "59b366ac-a382-44b1-a9ab-64b439656c1c", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 13.16, - "synth__design__instance__area__stdcell": 22294.258, - "synth__design__instance__count__stdcell": 10792.0, - "synth__mem__peak": 82056.0, - "synth__runtime__total": "0:13.33", - "total_time": "0:04:27.480000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/dynamic_node/rules-base.json b/flow/designs/nangate45/dynamic_node/rules-base.json index 6fce3410ce..bdc31d60f5 100644 --- a/flow/designs/nangate45/dynamic_node/rules-base.json +++ b/flow/designs/nangate45/dynamic_node/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 25638.4, + "value": 25515.12, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 28233, + "value": 27551, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 13609, + "value": 12798, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1183, + "value": 1113, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1183, + "value": 1113, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 261214, + "value": 354277, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.57, + "value": -0.49, "compare": ">=" }, "finish__design__instance__area": { - "value": 29582, + "value": 28843, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 592, + "value": 556, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -37.9, + "value": -31.32, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-array/autotuner.json b/flow/designs/nangate45/gcd/autotuner.json similarity index 71% rename from flow/designs/asap7/mock-array/autotuner.json rename to flow/designs/nangate45/gcd/autotuner.json index e6fc11d9cc..3ac6155fe6 100644 --- a/flow/designs/asap7/mock-array/autotuner.json +++ b/flow/designs/nangate45/gcd/autotuner.json @@ -1,42 +1,34 @@ { - "_SDC_FILE_PATH": "constraints.sdc", + "_SDC_FILE_PATH": "constraint.sdc", "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 200, - 400 - ], - "step": 0 - }, - "CORE_ASPECT_RATIO": { - "type": "float", - "minmax": [ - 0.5, - 2.0 + 0.3, + 1.0 ], "step": 0 }, - "CORE_MARGIN": { + "CORE_MARGIN": { "type": "int", "minmax": [ - 2, - 2 + 1, + 3 ], - "step": 0 + "step": 1 }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, - 5 + 0, + 3 ], "step": 1 }, @@ -47,12 +39,12 @@ 0.3 ], "step": 0 - }, + }, "PLACE_DENSITY_LB_ADDON": { "type": "float", "minmax": [ 0.0, - 0.99 + 0.2 ], "step": 0 }, @@ -72,5 +64,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "fastroute.tcl" + "_FR_FILE_PATH": "../../../platforms/nangate45/fastroute.tcl" } diff --git a/flow/designs/nangate45/gcd/config.mk b/flow/designs/nangate45/gcd/config.mk index 1b61b78af4..d7fc7a8bdd 100644 --- a/flow/designs/nangate45/gcd/config.mk +++ b/flow/designs/nangate45/gcd/config.mk @@ -12,3 +12,6 @@ export CORE_UTILIZATION ?= 55 export PLACE_DENSITY_LB_ADDON = 0.20 export TNS_END_PERCENT = 100 export REMOVE_CELLS_FOR_EQY = TAPCELL* + +# This needs a smaller pitch to accomodate a small block +export PDN_TCL ?= $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/grid_strategy-M1-M4-M7.tcl diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc index 57be8eb9c6..c6d4b902be 100644 --- a/flow/designs/nangate45/gcd/constraint.sdc +++ b/flow/designs/nangate45/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 0.46 +set clk_period 0.46 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/gcd/grid_strategy-M1-M4-M7.tcl b/flow/designs/nangate45/gcd/grid_strategy-M1-M4-M7.tcl new file mode 100644 index 0000000000..124e9a32cc --- /dev/null +++ b/flow/designs/nangate45/gcd/grid_strategy-M1-M4-M7.tcl @@ -0,0 +1,22 @@ +#################################### +# global connections +#################################### +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} +global_connect +#################################### +# voltage domains +#################################### +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} +#################################### +# standard cell grid +#################################### +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {metal1} -width {0.17} -pitch {2.4} -offset {0} -followpins +add_pdn_stripe -grid {grid} -layer {metal4} -width {0.48} -pitch {28.0} -offset {2} +add_pdn_stripe -grid {grid} -layer {metal7} -width {1.40} -pitch {15.0} -offset {2} +add_pdn_connect -grid {grid} -layers {metal1 metal4} +add_pdn_connect -grid {grid} -layers {metal4 metal7} diff --git a/flow/designs/nangate45/gcd/metadata-base-ok.json b/flow/designs/nangate45/gcd/metadata-base-ok.json deleted file mode 100644 index 72ec456c29..0000000000 --- a/flow/designs/nangate45/gcd/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 0.4600" - ], - "cts__clock__skew__hold": 0.000795468, - "cts__clock__skew__setup": 0.000795468, - "cts__cpu__total": 7.57, - "cts__design__core__area": 1149.12, - "cts__design__die__area": 1323.5, - "cts__design__instance__area": 813.428, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 813.428, - "cts__design__instance__count": 656, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 44, - "cts__design__instance__count__stdcell": 656, - "cts__design__instance__displacement__max": 7.79, - "cts__design__instance__displacement__mean": 0.7465, - "cts__design__instance__displacement__total": 489.945, - "cts__design__instance__utilization": 0.70787, - "cts__design__instance__utilization__stdcell": 0.70787, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 353208.0, - "cts__power__internal__total": 0.00163151, - "cts__power__leakage__total": 2.11153e-05, - "cts__power__switching__total": 0.00129643, - "cts__power__total": 0.00294906, - "cts__route__wirelength__estimated": 3690.55, - "cts__runtime__total": "0:07.84", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.798485, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.768407, - "cts__timing__drv__setup_violation_count": 26, - "cts__timing__setup__tns": -0.429612, - "cts__timing__setup__ws": -0.0484967, - "design__io__hpwl": 1078643, - "design__violations": 0, - "detailedplace__cpu__total": 0.66, - "detailedplace__design__core__area": 1149.12, - "detailedplace__design__die__area": 1323.5, - "detailedplace__design__instance__area": 659.148, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 659.148, - "detailedplace__design__instance__count": 604, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 604, - "detailedplace__design__instance__displacement__max": 4.0735, - "detailedplace__design__instance__displacement__mean": 0.9115, - "detailedplace__design__instance__displacement__total": 550.819, - "detailedplace__design__instance__utilization": 0.573611, - "detailedplace__design__instance__utilization__stdcell": 0.573611, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 123648.0, - "detailedplace__power__internal__total": 0.00115649, - "detailedplace__power__leakage__total": 1.52789e-05, - "detailedplace__power__switching__total": 0.000825776, - "detailedplace__power__total": 0.00199754, - "detailedplace__route__wirelength__estimated": 3177.48, - "detailedplace__runtime__total": "0:00.75", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.79772, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.76804, - "detailedplace__timing__drv__setup_violation_count": 28, - "detailedplace__timing__setup__tns": -0.368776, - "detailedplace__timing__setup__ws": -0.0206941, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 96, - "detailedroute__route__drc_errors__iter:2": 24, - "detailedroute__route__drc_errors__iter:3": 30, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 688, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3762, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3762, - "detailedroute__route__wirelength": 4800, - "detailedroute__route__wirelength__iter:1": 4851, - "detailedroute__route__wirelength__iter:2": 4806, - "detailedroute__route__wirelength__iter:3": 4798, - "detailedroute__route__wirelength__iter:4": 4800, - "finish__clock__skew__hold": 0.00178986, - "finish__clock__skew__setup": 0.00178986, - "finish__cpu__total": 1.96, - "finish__design__core__area": 1149.12, - "finish__design__die__area": 1323.5, - "finish__design__instance__area": 868.224, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 868.224, - "finish__design__instance__count": 668, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 668, - "finish__design__instance__utilization": 0.755556, - "finish__design__instance__utilization__stdcell": 0.755556, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.09611, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0041941, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0140424, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00990993, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.08596, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00990993, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 209768.0, - "finish__power__internal__total": 0.00175811, - "finish__power__leakage__total": 2.33764e-05, - "finish__power__switching__total": 0.00148702, - "finish__power__total": 0.00326851, - "finish__runtime__total": "0:02.08", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.801032, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.76966, - "finish__timing__drv__setup_violation_count": 44, - "finish__timing__setup__tns": -1.07501, - "finish__timing__setup__ws": -0.0551569, - "finish__timing__wns_percent_delay": -13.043478, - "finish_merge__cpu__total": 1.56, - "finish_merge__mem__peak": 392772.0, - "finish_merge__runtime__total": "0:01.77", - "floorplan__cpu__total": 0.47, - "floorplan__design__core__area": 1149.12, - "floorplan__design__die__area": 1323.5, - "floorplan__design__instance__area": 650.104, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 650.104, - "floorplan__design__instance__count": 503, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 503, - "floorplan__design__instance__utilization": 0.565741, - "floorplan__design__instance__utilization__stdcell": 0.565741, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 123384.0, - "floorplan__power__internal__total": 0.00117917, - "floorplan__power__leakage__total": 1.58666e-05, - "floorplan__power__switching__total": 0.000827966, - "floorplan__power__total": 0.002023, - "floorplan__runtime__total": "0:00.51", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.03906, - "floorplan_io__cpu__total": 0.35, - "floorplan_io__mem__peak": 119036.0, - "floorplan_io__runtime__total": "0:00.39", - "floorplan_macro__cpu__total": 0.33, - "floorplan_macro__mem__peak": 119028.0, - "floorplan_macro__runtime__total": "0:00.39", - "floorplan_pdn__cpu__total": 0.36, - "floorplan_pdn__mem__peak": 122112.0, - "floorplan_pdn__runtime__total": "0:00.40", - "floorplan_tap__cpu__total": 0.32, - "floorplan_tap__mem__peak": 118864.0, - "floorplan_tap__runtime__total": "0:00.39", - "floorplan_tdms__cpu__total": 0.32, - "floorplan_tdms__mem__peak": 119032.0, - "floorplan_tdms__runtime__total": "0:00.39", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 11.82, - "globalplace__design__core__area": 1149.12, - "globalplace__design__die__area": 1323.5, - "globalplace__design__instance__area": 662.872, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 662.872, - "globalplace__design__instance__count": 551, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 551, - "globalplace__design__instance__utilization": 0.576852, - "globalplace__design__instance__utilization__stdcell": 0.576852, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 335728.0, - "globalplace__power__internal__total": 0.00118158, - "globalplace__power__leakage__total": 1.58666e-05, - "globalplace__power__switching__total": 0.000928903, - "globalplace__power__total": 0.00212635, - "globalplace__runtime__total": "0:02.13", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 0.0264975, - "globalplace_io__cpu__total": 0.36, - "globalplace_io__mem__peak": 119616.0, - "globalplace_io__runtime__total": "0:00.40", - "globalplace_skip_io__cpu__total": 5.98, - "globalplace_skip_io__mem__peak": 120540.0, - "globalplace_skip_io__runtime__total": "0:00.57", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.0016853, - "globalroute__clock__skew__setup": 0.0016853, - "globalroute__cpu__total": 8.13, - "globalroute__design__core__area": 1149.12, - "globalroute__design__die__area": 1323.5, - "globalroute__design__instance__area": 868.224, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 868.224, - "globalroute__design__instance__count": 668, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 9, - "globalroute__design__instance__count__stdcell": 668, - "globalroute__design__instance__displacement__max": 9.8, - "globalroute__design__instance__displacement__mean": 0.712, - "globalroute__design__instance__displacement__total": 475.74, - "globalroute__design__instance__utilization": 0.755556, - "globalroute__design__instance__utilization__stdcell": 0.755556, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 356860.0, - "globalroute__power__internal__total": 0.00175908, - "globalroute__power__leakage__total": 2.33764e-05, - "globalroute__power__switching__total": 0.0015095, - "globalroute__power__total": 0.00329195, - "globalroute__route__wirelength__estimated": 4352.21, - "globalroute__runtime__total": "0:06.98", - "globalroute__timing__clock__slack": -0.055, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.783493, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.761205, - "globalroute__timing__drv__setup_violation_count": 44, - "globalroute__timing__setup__tns": -1.09331, - "globalroute__timing__setup__ws": -0.0553322, - "placeopt__cpu__total": 0.7, - "placeopt__design__core__area": 1149.12, - "placeopt__design__die__area": 1323.5, - "placeopt__design__instance__area": 659.148, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 659.148, - "placeopt__design__instance__count": 604, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 604, - "placeopt__design__instance__utilization": 0.573611, - "placeopt__design__instance__utilization__stdcell": 0.573611, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 266456.0, - "placeopt__power__internal__total": 0.00115624, - "placeopt__power__leakage__total": 1.52789e-05, - "placeopt__power__switching__total": 0.000821054, - "placeopt__power__total": 0.00199257, - "placeopt__runtime__total": "0:00.92", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.805204, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.77166, - "placeopt__timing__drv__setup_violation_count": 28, - "placeopt__timing__setup__tns": -0.299658, - "placeopt__timing__setup__ws": -0.017345, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-09-28 19:38", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16113-g7b5c8faf7", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "f1187e72-b9f6-4dcb-8017-1336cb6d64d4", - "run__flow__variant": "base", - "synth__cpu__total": 0.96, - "synth__design__instance__area__stdcell": 650.104, - "synth__design__instance__count__stdcell": 503.0, - "synth__mem__peak": 36864.0, - "synth__runtime__total": "0:01.02", - "total_time": "0:00:26.930000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json index f38ddf5d93..0e91d99a8e 100644 --- a/flow/designs/nangate45/gcd/rules-base.json +++ b/flow/designs/nangate45/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 747.62, + "value": 725.6, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +8,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 747, + "value": 743, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 5520, + "value": 5050, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,15 +44,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.07, + "value": -0.08, "compare": ">=" }, "finish__design__instance__area": { - "value": 907, + "value": 898, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -25.65, + "value": -25.2, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ibex/config.mk b/flow/designs/nangate45/ibex/config.mk index 8d6843f00e..3ead834dba 100644 --- a/flow/designs/nangate45/ibex/config.mk +++ b/flow/designs/nangate45/ibex/config.mk @@ -2,48 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = nangate45 +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc index 625bba41ec..38667319ac 100644 --- a/flow/designs/nangate45/ibex/constraint.sdc +++ b/flow/designs/nangate45/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 2.2 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/ibex/metadata-base-ok.json b/flow/designs/nangate45/ibex/metadata-base-ok.json deleted file mode 100644 index a0ac35c841..0000000000 --- a/flow/designs/nangate45/ibex/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2.2000" - ], - "cts__clock__skew__hold": 0.362404, - "cts__clock__skew__setup": 0.362405, - "cts__cpu__total": 498.42, - "cts__design__core__area": 57494.3, - "cts__design__die__area": 58726.3, - "cts__design__instance__area": 34434, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 34434, - "cts__design__instance__count": 17603, - "cts__design__instance__count__hold_buffer": 6, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 120, - "cts__design__instance__count__stdcell": 17603, - "cts__design__instance__displacement__max": 13.6175, - "cts__design__instance__displacement__mean": 0.1175, - "cts__design__instance__displacement__total": 2071.45, - "cts__design__instance__utilization": 0.598911, - "cts__design__instance__utilization__stdcell": 0.598911, - "cts__design__io": 264, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 493752.0, - "cts__power__internal__total": 0.0521806, - "cts__power__leakage__total": 0.000770296, - "cts__power__switching__total": 0.0429792, - "cts__power__total": 0.0959301, - "cts__route__wirelength__estimated": 262283, - "cts__runtime__total": "8:18.86", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0776869, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.380037, - "cts__timing__drv__setup_violation_count": 764, - "cts__timing__setup__tns": -114.61, - "cts__timing__setup__ws": -0.318472, - "design__io__hpwl": 27832027, - "design__violations": 0, - "detailedplace__cpu__total": 22.16, - "detailedplace__design__core__area": 57494.3, - "detailedplace__design__die__area": 58726.3, - "detailedplace__design__instance__area": 32445.9, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 32445.9, - "detailedplace__design__instance__count": 16394, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 16394, - "detailedplace__design__instance__displacement__max": 9.56, - "detailedplace__design__instance__displacement__mean": 1.0275, - "detailedplace__design__instance__displacement__total": 16848.9, - "detailedplace__design__instance__utilization": 0.564332, - "detailedplace__design__instance__utilization__stdcell": 0.564332, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 211544.0, - "detailedplace__power__internal__total": 0.0454808, - "detailedplace__power__leakage__total": 0.00070901, - "detailedplace__power__switching__total": 0.0391298, - "detailedplace__power__total": 0.0853196, - "detailedplace__route__wirelength__estimated": 251964, - "detailedplace__runtime__total": "0:22.28", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.078101, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.380211, - "detailedplace__timing__drv__setup_violation_count": 531, - "detailedplace__timing__setup__tns": -59.2668, - "detailedplace__timing__setup__ws": -0.198951, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 12, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 4431, - "detailedroute__route__drc_errors__iter:2": 1211, - "detailedroute__route__drc_errors__iter:3": 959, - "detailedroute__route__drc_errors__iter:4": 89, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 19715, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 139667, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 139667, - "detailedroute__route__wirelength": 319271, - "detailedroute__route__wirelength__iter:1": 321308, - "detailedroute__route__wirelength__iter:2": 319507, - "detailedroute__route__wirelength__iter:3": 319211, - "detailedroute__route__wirelength__iter:4": 319278, - "detailedroute__route__wirelength__iter:5": 319271, - "finish__clock__skew__hold": 0.374261, - "finish__clock__skew__setup": 0.374268, - "finish__cpu__total": 87.71, - "finish__design__core__area": 57494.3, - "finish__design__die__area": 58726.3, - "finish__design__instance__area": 34559.5, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 34559.5, - "finish__design__instance__count": 17630, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 17630, - "finish__design__instance__utilization": 0.601095, - "finish__design__instance__utilization__stdcell": 0.601095, - "finish__design__io": 264, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.700633, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.258261, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.835211, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.559293, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.264789, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.559293, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 544872.0, - "finish__power__internal__total": 0.0528286, - "finish__power__leakage__total": 0.000775834, - "finish__power__switching__total": 0.0473018, - "finish__power__total": 0.100906, - "finish__runtime__total": "1:28.42", - "finish__timing__drv__hold_violation_count": 54, - "finish__timing__drv__max_cap": 9, - "finish__timing__drv__max_cap_limit": -0.119975, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.286845, - "finish__timing__drv__setup_violation_count": 865, - "finish__timing__setup__tns": -158.659, - "finish__timing__setup__ws": -0.372315, - "finish__timing__wns_percent_delay": -13.12857, - "finish_merge__cpu__total": 3.31, - "finish_merge__mem__peak": 514620.0, - "finish_merge__runtime__total": "0:03.64", - "floorplan__cpu__total": 92.37, - "floorplan__design__core__area": 57494.3, - "floorplan__design__die__area": 58726.3, - "floorplan__design__instance__area": 29006.2, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 29006.2, - "floorplan__design__instance__count": 15693, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 15693, - "floorplan__design__instance__utilization": 0.504506, - "floorplan__design__instance__utilization__stdcell": 0.504506, - "floorplan__design__io": 264, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 382, - "floorplan__mem__peak": 187896.0, - "floorplan__power__internal__total": 0.0380469, - "floorplan__power__leakage__total": 0.000585633, - "floorplan__power__switching__total": 0.0227191, - "floorplan__power__total": 0.0613517, - "floorplan__runtime__total": "1:32.52", - "floorplan__timing__setup__tns": -0.000212053, - "floorplan__timing__setup__ws": 0.000417666, - "floorplan_io__cpu__total": 0.43, - "floorplan_io__mem__peak": 144128.0, - "floorplan_io__runtime__total": "0:00.52", - "floorplan_macro__cpu__total": 0.47, - "floorplan_macro__mem__peak": 143352.0, - "floorplan_macro__runtime__total": "0:00.53", - "floorplan_pdn__cpu__total": 0.56, - "floorplan_pdn__mem__peak": 147968.0, - "floorplan_pdn__runtime__total": "0:00.65", - "floorplan_tap__cpu__total": 0.34, - "floorplan_tap__mem__peak": 134648.0, - "floorplan_tap__runtime__total": "0:00.48", - "floorplan_tdms__cpu__total": 0.46, - "floorplan_tdms__mem__peak": 143100.0, - "floorplan_tdms__runtime__total": "0:00.52", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 347.27, - "globalplace__design__core__area": 57494.3, - "globalplace__design__die__area": 58726.3, - "globalplace__design__instance__area": 29120.6, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 29120.6, - "globalplace__design__instance__count": 16123, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 16123, - "globalplace__design__instance__utilization": 0.506496, - "globalplace__design__instance__utilization__stdcell": 0.506496, - "globalplace__design__io": 264, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 548300.0, - "globalplace__power__internal__total": 0.0389224, - "globalplace__power__leakage__total": 0.000585633, - "globalplace__power__switching__total": 0.0335494, - "globalplace__power__total": 0.0730574, - "globalplace__runtime__total": "1:25.56", - "globalplace__timing__setup__tns": -311.443, - "globalplace__timing__setup__ws": -0.494181, - "globalplace_io__cpu__total": 0.48, - "globalplace_io__mem__peak": 145664.0, - "globalplace_io__runtime__total": "0:00.53", - "globalplace_skip_io__cpu__total": 221.29, - "globalplace_skip_io__mem__peak": 168796.0, - "globalplace_skip_io__runtime__total": "0:07.56", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.368494, - "globalroute__clock__skew__setup": 0.368494, - "globalroute__cpu__total": 1000.68, - "globalroute__design__core__area": 57494.3, - "globalroute__design__die__area": 58726.3, - "globalroute__design__instance__area": 34559.5, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 34559.5, - "globalroute__design__instance__count": 17630, - "globalroute__design__instance__count__hold_buffer": 2, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 12, - "globalroute__design__instance__count__stdcell": 17630, - "globalroute__design__instance__displacement__max": 5.51, - "globalroute__design__instance__displacement__mean": 0.021, - "globalroute__design__instance__displacement__total": 375.63, - "globalroute__design__instance__utilization": 0.601095, - "globalroute__design__instance__utilization__stdcell": 0.601095, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 684396.0, - "globalroute__power__internal__total": 0.0527871, - "globalroute__power__leakage__total": 0.000775834, - "globalroute__power__switching__total": 0.0459253, - "globalroute__power__total": 0.0994882, - "globalroute__route__wirelength__estimated": 263286, - "globalroute__runtime__total": "15:56.77", - "globalroute__timing__clock__slack": -0.363, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 1, - "globalroute__timing__drv__max_cap_limit": -0.0825659, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.328232, - "globalroute__timing__drv__setup_violation_count": 773, - "globalroute__timing__setup__tns": -143.901, - "globalroute__timing__setup__ws": -0.362631, - "placeopt__cpu__total": 22.83, - "placeopt__design__core__area": 57494.3, - "placeopt__design__die__area": 58726.3, - "placeopt__design__instance__area": 32445.9, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 32445.9, - "placeopt__design__instance__count": 16394, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 16394, - "placeopt__design__instance__utilization": 0.564332, - "placeopt__design__instance__utilization__stdcell": 0.564332, - "placeopt__design__io": 264, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 389184.0, - "placeopt__power__internal__total": 0.0454723, - "placeopt__power__leakage__total": 0.00070901, - "placeopt__power__switching__total": 0.0389762, - "placeopt__power__total": 0.0851575, - "placeopt__runtime__total": "0:23.16", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0926263, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.386745, - "placeopt__timing__drv__setup_violation_count": 531, - "placeopt__timing__setup__tns": -58.378, - "placeopt__timing__setup__ws": -0.194567, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-09-27 18:17", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "f08c6d2f-1bd2-4fe3-9690-dd986cd6d7ff", - "run__flow__variant": "base", - "synth__cpu__total": 83.48, - "synth__design__instance__area__stdcell": 28880.95, - "synth__design__instance__count__stdcell": 15697.0, - "synth__mem__peak": 233324.0, - "synth__runtime__total": "1:23.91", - "total_time": "0:31:05.910000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/ibex/rules-base.json b/flow/designs/nangate45/ibex/rules-base.json index 33978bb075..966130b95e 100644 --- a/flow/designs/nangate45/ibex/rules-base.json +++ b/flow/designs/nangate45/ibex/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 36863, + "value": 35998, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18834, + "value": 17800, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1638, + "value": 1548, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1638, + "value": 1548, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 363762, + "value": 325819, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.48, + "value": -0.14, "compare": ">=" }, "finish__design__instance__area": { - "value": 39536, + "value": 37049, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 908, + "value": 774, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -25.41, + "value": -11.47, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc index 69ef1bc64d..7c97d6490a 100644 --- a/flow/designs/nangate45/jpeg/constraint.sdc +++ b/flow/designs/nangate45/jpeg/constraint.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 1.4 +set clk_period 1.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/jpeg/metadata-base-ok.json b/flow/designs/nangate45/jpeg/metadata-base-ok.json deleted file mode 100644 index a92c915177..0000000000 --- a/flow/designs/nangate45/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,384 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1.4000" - ], - "cts__clock__skew__hold": 0.0252455, - "cts__clock__skew__setup": 0.0252455, - "cts__cpu__total": 624.64, - "cts__design__core__area": 232329, - "cts__design__die__area": 234866, - "cts__design__instance__area": 113934, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 113934, - "cts__design__instance__count": 69849, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 5, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 20, - "cts__design__instance__count__stdcell": 69849, - "cts__design__instance__displacement__max": 3.765, - "cts__design__instance__displacement__mean": 0.005, - "cts__design__instance__displacement__total": 352.686, - "cts__design__instance__utilization": 0.4904, - "cts__design__instance__utilization__stdcell": 0.4904, - "cts__design__io": 47, - "cts__design__rows": 344, - "cts__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "cts__design__sites": 873416, - "cts__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 755364.0, - "cts__power__internal__total": 0.33228, - "cts__power__leakage__total": 0.00260606, - "cts__power__switching__total": 0.324355, - "cts__power__total": 0.659241, - "cts__route__wirelength__estimated": 1021580.0, - "cts__runtime__total": "10:25.61", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0106414, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.374732, - "cts__timing__drv__setup_violation_count": 460, - "cts__timing__setup__tns": -63.8671, - "cts__timing__setup__ws": -0.344834, - "design__io__hpwl": 8940499, - "design__violations": 0, - "detailedplace__cpu__total": 73.79, - "detailedplace__design__core__area": 232329, - "detailedplace__design__die__area": 234866, - "detailedplace__design__instance__area": 112197, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 112197, - "detailedplace__design__instance__count": 68457, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 68457, - "detailedplace__design__instance__displacement__max": 10.96, - "detailedplace__design__instance__displacement__mean": 0.833, - "detailedplace__design__instance__displacement__total": 57032.6, - "detailedplace__design__instance__utilization": 0.482926, - "detailedplace__design__instance__utilization__stdcell": 0.482926, - "detailedplace__design__io": 47, - "detailedplace__design__rows": 344, - "detailedplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "detailedplace__design__sites": 873416, - "detailedplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 530960.0, - "detailedplace__power__internal__total": 0.32221, - "detailedplace__power__leakage__total": 0.00255868, - "detailedplace__power__switching__total": 0.312975, - "detailedplace__power__total": 0.637744, - "detailedplace__route__wirelength__estimated": 1018310.0, - "detailedplace__runtime__total": "1:14.24", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.00909289, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.373888, - "detailedplace__timing__drv__setup_violation_count": 554, - "detailedplace__timing__setup__tns": -117.924, - "detailedplace__timing__setup__ws": -0.460751, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 11270, - "detailedroute__route__drc_errors__iter:2": 2255, - "detailedroute__route__drc_errors__iter:3": 1588, - "detailedroute__route__drc_errors__iter:4": 34, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 84174, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 423632, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 423632, - "detailedroute__route__wirelength": 1159821, - "detailedroute__route__wirelength__iter:1": 1166404, - "detailedroute__route__wirelength__iter:2": 1160330, - "detailedroute__route__wirelength__iter:3": 1159766, - "detailedroute__route__wirelength__iter:4": 1159826, - "detailedroute__route__wirelength__iter:5": 1159821, - "detailedroute__route__wirelength__iter:6": 1159821, - "finish__clock__skew__hold": 0.0386009, - "finish__clock__skew__setup": 0.0386009, - "finish__cpu__total": 169.79, - "finish__design__core__area": 232329, - "finish__design__die__area": 234866, - "finish__design__instance__area": 114322, - "finish__design__instance__area__class:buffer": 5798.8, - "finish__design__instance__area__class:clock_buffer": 1203.38, - "finish__design__instance__area__class:clock_inverter": 266, - "finish__design__instance__area__class:inverter": 10256.4, - "finish__design__instance__area__class:multi_input_combinational_cell": 75491.1, - "finish__design__instance__area__class:sequential_cell": 20548.5, - "finish__design__instance__area__class:timing_repair_buffer": 382.774, - "finish__design__instance__area__class:timing_repair_inverter": 7.98, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 114322, - "finish__design__instance__count": 69883, - "finish__design__instance__count__class:buffer": 3047, - "finish__design__instance__count__class:clock_buffer": 1020, - "finish__design__instance__count__class:clock_inverter": 344, - "finish__design__instance__count__class:inverter": 18467, - "finish__design__instance__count__class:multi_input_combinational_cell": 41066, - "finish__design__instance__count__class:sequential_cell": 4385, - "finish__design__instance__count__class:timing_repair_buffer": 168, - "finish__design__instance__count__class:timing_repair_inverter": 6, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 69883, - "finish__design__instance__utilization": 0.49207, - "finish__design__instance__utilization__stdcell": 0.49207, - "finish__design__io": 47, - "finish__design__rows": 344, - "finish__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "finish__design__sites": 873416, - "finish__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 0.889938, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.20042, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.42091, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.359034, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.67909, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.359034, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1421492.0, - "finish__power__internal__total": 0.336984, - "finish__power__leakage__total": 0.00262401, - "finish__power__switching__total": 0.354536, - "finish__power__total": 0.694144, - "finish__runtime__total": "2:51.81", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 36, - "finish__timing__drv__max_cap_limit": -0.53437, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0755632, - "finish__timing__drv__setup_violation_count": 510, - "finish__timing__setup__tns": -82.3665, - "finish__timing__setup__ws": -0.374966, - "finish__timing__wns_percent_delay": -18.14048, - "finish_merge__cpu__total": 8.1, - "finish_merge__mem__peak": 860772.0, - "finish_merge__runtime__total": "0:08.79", - "floorplan__cpu__total": 218.46, - "floorplan__design__core__area": 232329, - "floorplan__design__die__area": 234866, - "floorplan__design__instance__area": 105056, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 105056, - "floorplan__design__instance__count": 66987, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 66987, - "floorplan__design__instance__utilization": 0.452189, - "floorplan__design__instance__utilization__stdcell": 0.452189, - "floorplan__design__io": 47, - "floorplan__design__rows": 344, - "floorplan__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "floorplan__design__sites": 873416, - "floorplan__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 552, - "floorplan__mem__peak": 380668.0, - "floorplan__power__internal__total": 0.283881, - "floorplan__power__leakage__total": 0.00223463, - "floorplan__power__switching__total": 0.193742, - "floorplan__power__total": 0.479857, - "floorplan__runtime__total": "3:38.83", - "floorplan__timing__setup__tns": -0.068769, - "floorplan__timing__setup__ws": -0.0249631, - "floorplan_io__cpu__total": 0.95, - "floorplan_io__mem__peak": 226816.0, - "floorplan_io__runtime__total": "0:01.16", - "floorplan_macro__cpu__total": 1.03, - "floorplan_macro__mem__peak": 224944.0, - "floorplan_macro__runtime__total": "0:01.23", - "floorplan_pdn__cpu__total": 1.62, - "floorplan_pdn__mem__peak": 239500.0, - "floorplan_pdn__runtime__total": "0:01.82", - "floorplan_tap__cpu__total": 0.86, - "floorplan_tap__mem__peak": 186268.0, - "floorplan_tap__runtime__total": "0:01.04", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1086.85, - "globalplace__design__core__area": 232329, - "globalplace__design__die__area": 234866, - "globalplace__design__instance__area": 112105, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 112105, - "globalplace__design__instance__count": 68409, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 68409, - "globalplace__design__instance__utilization": 0.482527, - "globalplace__design__instance__utilization__stdcell": 0.482527, - "globalplace__design__io": 47, - "globalplace__design__rows": 344, - "globalplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "globalplace__design__sites": 873416, - "globalplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 968004.0, - "globalplace__power__internal__total": 0.32208, - "globalplace__power__leakage__total": 0.00255478, - "globalplace__power__switching__total": 0.31261, - "globalplace__power__total": 0.637244, - "globalplace__runtime__total": "4:41.66", - "globalplace__timing__setup__tns": -116.312, - "globalplace__timing__setup__ws": -0.45554, - "globalplace_io__cpu__total": 1.02, - "globalplace_io__mem__peak": 229200.0, - "globalplace_io__runtime__total": "0:01.22", - "globalplace_skip_io__cpu__total": 725.98, - "globalplace_skip_io__mem__peak": 348448.0, - "globalplace_skip_io__runtime__total": "0:41.71", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.0285738, - "globalroute__clock__skew__setup": 0.0285738, - "globalroute__cpu__total": 380.59, - "globalroute__design__core__area": 232329, - "globalroute__design__die__area": 234866, - "globalroute__design__instance__area": 114322, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 114322, - "globalroute__design__instance__count": 69883, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 39, - "globalroute__design__instance__count__stdcell": 69883, - "globalroute__design__instance__displacement__max": 4.06, - "globalroute__design__instance__displacement__mean": 0.0075, - "globalroute__design__instance__displacement__total": 545.07, - "globalroute__design__instance__utilization": 0.49207, - "globalroute__design__instance__utilization__stdcell": 0.49207, - "globalroute__design__io": 47, - "globalroute__design__rows": 344, - "globalroute__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "globalroute__design__sites": 873416, - "globalroute__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 1117704.0, - "globalroute__power__internal__total": 0.336878, - "globalroute__power__leakage__total": 0.00262401, - "globalroute__power__switching__total": 0.350894, - "globalroute__power__total": 0.690396, - "globalroute__route__wirelength__estimated": 1024010.0, - "globalroute__runtime__total": "4:47.96", - "globalroute__timing__clock__slack": -0.365, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 29, - "globalroute__timing__drv__max_cap_limit": -0.177185, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.264646, - "globalroute__timing__drv__setup_violation_count": 504, - "globalroute__timing__setup__tns": -80.5153, - "globalroute__timing__setup__ws": -0.365443, - "placeopt__cpu__total": 61.29, - "placeopt__design__core__area": 232329, - "placeopt__design__die__area": 234866, - "placeopt__design__instance__area": 112197, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 112197, - "placeopt__design__instance__count": 68457, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 68457, - "placeopt__design__instance__utilization": 0.482926, - "placeopt__design__instance__utilization__stdcell": 0.482926, - "placeopt__design__io": 47, - "placeopt__design__rows": 344, - "placeopt__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 344, - "placeopt__design__sites": 873416, - "placeopt__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 873416, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 533168.0, - "placeopt__power__internal__total": 0.322207, - "placeopt__power__leakage__total": 0.00255868, - "placeopt__power__switching__total": 0.31253, - "placeopt__power__total": 0.637296, - "placeopt__runtime__total": "1:01.80", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0118803, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.375408, - "placeopt__timing__drv__setup_violation_count": 553, - "placeopt__timing__setup__tns": -115.891, - "placeopt__timing__setup__ws": -0.4537, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-11-22 23:13", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "d6242a6c-8db3-468e-92d3-9357c1ef8dbf", - "run__flow__variant": "base", - "synth__cpu__total": 131.13, - "synth__design__instance__area__stdcell": 104819.96, - "synth__design__instance__count__stdcell": 66988.0, - "synth__mem__peak": 614604.0, - "synth__runtime__total": "2:12.69", - "total_time": "0:31:51.570000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json index 233d1dadfd..ffa598e023 100644 --- a/flow/designs/nangate45/jpeg/rules-base.json +++ b/flow/designs/nangate45/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 120537.76, + "value": 103045.48, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 127262, + "value": 104372, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 78697, + "value": 69094, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6843, + "value": 6008, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6843, + "value": 6008, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1313188, + "value": 687679, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.44, + "value": -0.05, "compare": ">=" }, "finish__design__instance__area": { - "value": 130408, + "value": 106338, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3422, + "value": 3004, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.66, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk index 50d4c1ee76..115c2012c5 100644 --- a/flow/designs/nangate45/mempool_group/config.mk +++ b/flow/designs/nangate45/mempool_group/config.mk @@ -5,24 +5,76 @@ export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) -export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/cf_math_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/riscv_instr.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi_hier_interco.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_tile.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_mux.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_remap.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_cc.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_adapter.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/fakeram45_256x32.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/fakeram45_64x64.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_sram.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fall_through_register.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_xbar.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/address_scrambler.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_shim.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_demux.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_axi_adapter.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_cut.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_prepend.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/rr_arb_tree.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fifo_v3.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/lzc.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_ipu.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/isochronous_spill_register.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/onehot_to_bin.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_demux.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/fifo_v2.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register_flushable.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter_flushable.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/latch_scm.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_lsu.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_clk.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch_addr_demux.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_regfile_ff.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_shared_muldiv.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/find_first_one.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_onehot.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_intf.sv \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_group.sv + +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/register_interface/include export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \ - $(PLATFORM_DIR)/lef/fakeram45_64x64.lef \ - $(PLATFORM_DIR)/lef/fakeram45_128x32.lef \ - $(PLATFORM_DIR)/lef/fakeram45_128x256.lef + $(PLATFORM_DIR)/lef/fakeram45_64x64.lef export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x32.lib \ - $(PLATFORM_DIR)/lib/fakeram45_128x32.lib \ - $(PLATFORM_DIR)/lib/fakeram45_64x64.lib \ - $(PLATFORM_DIR)/lib/fakeram45_128x256.lib + $(PLATFORM_DIR)/lib/fakeram45_64x64.lib -export DIE_AREA = 0 0 4400 4400 -export CORE_AREA = 10 12 4390 4390 - -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:3400-4400 +export DIE_AREA = 0 0 1100 1100 +export CORE_AREA = 10 12 1090 1090 export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 + +export SYNTH_HDL_FRONTEND = slang diff --git a/flow/designs/nangate45/mempool_group/mempool_group.sdc b/flow/designs/nangate45/mempool_group/mempool_group.sdc new file mode 100755 index 0000000000..a6efdf815b --- /dev/null +++ b/flow/designs/nangate45/mempool_group/mempool_group.sdc @@ -0,0 +1,68 @@ +set sdc_version 2.0 +set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA + +set clock_cycle 3 +set uncertainty [expr $clock_cycle*0.02] +set io_delay 0 +set maxFanout 16 +set maxTransition [expr $clock_cycle*0.01] +set pre_cts_clock_latency_estimate 0.070 +set clock_port_mempool_tile clk_i + +create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile] +set_clock_uncertainty $uncertainty [all_clocks] +set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==in && is_on_clock_network==false"] +set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay \ + [get_ports * -filter "direction==out && is_on_clock_network==false"] +set_max_transition $maxTransition -clock_path [get_clocks clk_i] +set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i] +#set_propagated_clock [get_clocks clk_i] + + +# Create virtual clock. +create_clock -name "vclk_i" -period $clock_cycle +set_clock_uncertainty $uncertainty [get_clocks vclk_i] +set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i] +set_max_transition $maxTransition -clock_path [get_clocks vclk_i] + + +set_case_analysis 0 [get_ports scan_enable_i] +set_max_fanout $maxFanout [current_design] + + +# False path some of the quasi-static signals. +#set_false_path -from tile_id_i + +# TCDM Master +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_.*req_.*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter { name =~ tcdm_master_*req_*_o}] + +set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_master_*resp_*_o}] + +# TCDM Slave +#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i \ +# [get_ports -filter {name =~ tcdm_slave_*req_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*req_*_o}] + +set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_i}] +set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i \ + [get_ports -filter {name =~ tcdm_slave_*resp_*_o}] + +# Refill port +#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}] +#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}] + +# Reset +set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni + +# Critical range +# Depending on the synthesis tool used, this can be helpful. +#set_critical_range 0.100 [current_design] diff --git a/flow/designs/nangate45/mempool_group/rules-base.json b/flow/designs/nangate45/mempool_group/rules-base.json new file mode 100644 index 0000000000..62e44a2c7e --- /dev/null +++ b/flow/designs/nangate45/mempool_group/rules-base.json @@ -0,0 +1,70 @@ +{ + "synth__design__instance__area__stdcell": { + "value": 271098.37, + "compare": "<=" + }, + "constraints__clocks__count": { + "value": 2, + "compare": "==" + }, + "placeopt__design__instance__area": { + "value": 322046, + "compare": "<=" + }, + "placeopt__design__instance__count__stdcell": { + "value": 163160, + "compare": "<=" + }, + "detailedplace__design__violations": { + "value": 0, + "compare": "==" + }, + "cts__design__instance__count__setup_buffer": { + "value": 11373, + "compare": "<=" + }, + "cts__design__instance__count__hold_buffer": { + "value": 11373, + "compare": "<=" + }, + "globalroute__antenna_diodes_count": { + "value": 0, + "compare": "<=" + }, + "detailedroute__route__wirelength": { + "value": 4942626, + "compare": "<=" + }, + "detailedroute__route__drc_errors": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 5, + "compare": "<=" + }, + "finish__timing__setup__ws": { + "value": -2.34, + "compare": ">=" + }, + "finish__design__instance__area": { + "value": 331160, + "compare": "<=" + }, + "finish__timing__drv__setup_violation_count": { + "value": 7210, + "compare": "<=" + }, + "finish__timing__drv__hold_violation_count": { + "value": 100, + "compare": "<=" + }, + "finish__timing__wns_percent_delay": { + "value": -109.23, + "compare": ">=" + } +} \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc index 9fd406be5e..ccaab11ddf 100644 --- a/flow/designs/nangate45/swerv/constraint.sdc +++ b/flow/designs/nangate45/swerv/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv/metadata-base-ok.json b/flow/designs/nangate45/swerv/metadata-base-ok.json deleted file mode 100644 index 1748668370..0000000000 --- a/flow/designs/nangate45/swerv/metadata-base-ok.json +++ /dev/null @@ -1,384 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2.0000" - ], - "cts__clock__skew__hold": 0.124445, - "cts__clock__skew__setup": 0.124445, - "cts__cpu__total": 376.2, - "cts__design__core__area": 388845, - "cts__design__die__area": 402470, - "cts__design__instance__area": 200076, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 200076, - "cts__design__instance__count": 96194, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 10, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 41, - "cts__design__instance__count__stdcell": 96194, - "cts__design__instance__displacement__max": 5.01, - "cts__design__instance__displacement__mean": 0.006, - "cts__design__instance__displacement__total": 599.824, - "cts__design__instance__utilization": 0.514539, - "cts__design__instance__utilization__stdcell": 0.514539, - "cts__design__io": 2039, - "cts__design__rows": 445, - "cts__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "cts__design__sites": 1461825, - "cts__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1025628.0, - "cts__power__internal__total": 0.0967024, - "cts__power__leakage__total": 0.0047769, - "cts__power__switching__total": 0.0644786, - "cts__power__total": 0.165958, - "cts__route__wirelength__estimated": 2546860.0, - "cts__runtime__total": "6:17.09", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0185031, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.355562, - "cts__timing__drv__setup_violation_count": 932, - "cts__timing__setup__tns": -143.552, - "cts__timing__setup__ws": -0.291811, - "design__io__hpwl": 683773583, - "design__violations": 0, - "detailedplace__cpu__total": 126.31, - "detailedplace__design__core__area": 388845, - "detailedplace__design__die__area": 402470, - "detailedplace__design__instance__area": 196168, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 196168, - "detailedplace__design__instance__count": 92773, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 92773, - "detailedplace__design__instance__displacement__max": 8.375, - "detailedplace__design__instance__displacement__mean": 1.022, - "detailedplace__design__instance__displacement__total": 94818.7, - "detailedplace__design__instance__utilization": 0.504487, - "detailedplace__design__instance__utilization__stdcell": 0.504487, - "detailedplace__design__io": 2039, - "detailedplace__design__rows": 445, - "detailedplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "detailedplace__design__sites": 1461825, - "detailedplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 779968.0, - "detailedplace__power__internal__total": 0.0848958, - "detailedplace__power__leakage__total": 0.00467809, - "detailedplace__power__switching__total": 0.0506916, - "detailedplace__power__total": 0.140265, - "detailedplace__route__wirelength__estimated": 2545280.0, - "detailedplace__runtime__total": "2:06.87", - "detailedplace__timing__drv__hold_violation_count": 209, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0253533, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.358423, - "detailedplace__timing__drv__setup_violation_count": 975, - "detailedplace__timing__setup__tns": -360.793, - "detailedplace__timing__setup__ws": -0.548338, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 3, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 29956, - "detailedroute__route__drc_errors__iter:2": 7900, - "detailedroute__route__drc_errors__iter:3": 6407, - "detailedroute__route__drc_errors__iter:4": 311, - "detailedroute__route__drc_errors__iter:5": 28, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 106985, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 869404, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 869404, - "detailedroute__route__wirelength": 3010603, - "detailedroute__route__wirelength__iter:1": 3027796, - "detailedroute__route__wirelength__iter:2": 3012620, - "detailedroute__route__wirelength__iter:3": 3009782, - "detailedroute__route__wirelength__iter:4": 3010580, - "detailedroute__route__wirelength__iter:5": 3010597, - "detailedroute__route__wirelength__iter:6": 3010603, - "finish__clock__skew__hold": 0.090698, - "finish__clock__skew__setup": 0.090698, - "finish__cpu__total": 340.33, - "finish__design__core__area": 388845, - "finish__design__die__area": 402470, - "finish__design__instance__area": 200559, - "finish__design__instance__area__class:buffer": 16963.1, - "finish__design__instance__area__class:clock_buffer": 3064.32, - "finish__design__instance__area__class:clock_inverter": 507.794, - "finish__design__instance__area__class:inverter": 3355.86, - "finish__design__instance__area__class:multi_input_combinational_cell": 109863, - "finish__design__instance__area__class:sequential_cell": 62030.7, - "finish__design__instance__area__class:timing_repair_buffer": 4238.18, - "finish__design__instance__area__class:timing_repair_inverter": 2.394, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 200559, - "finish__design__instance__count": 96241, - "finish__design__instance__count__class:buffer": 9516, - "finish__design__instance__count__class:clock_buffer": 2600, - "finish__design__instance__count__class:clock_inverter": 756, - "finish__design__instance__count__class:inverter": 5471, - "finish__design__instance__count__class:multi_input_combinational_cell": 62319, - "finish__design__instance__count__class:sequential_cell": 11272, - "finish__design__instance__count__class:timing_repair_buffer": 2299, - "finish__design__instance__count__class:timing_repair_inverter": 1, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 96241, - "finish__design__instance__utilization": 0.515781, - "finish__design__instance__utilization__stdcell": 0.515781, - "finish__design__io": 2039, - "finish__design__rows": 445, - "finish__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "finish__design__sites": 1461825, - "finish__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.07685, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0241072, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0682132, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.080966, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.03179, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.080966, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 2252832.0, - "finish__power__internal__total": 0.0970125, - "finish__power__leakage__total": 0.00480121, - "finish__power__switching__total": 0.0713133, - "finish__power__total": 0.173127, - "finish__runtime__total": "5:43.15", - "finish__timing__drv__hold_violation_count": 362, - "finish__timing__drv__max_cap": 76, - "finish__timing__drv__max_cap_limit": -0.865979, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 1, - "finish__timing__drv__max_slew_limit": -0.0291608, - "finish__timing__drv__setup_violation_count": 938, - "finish__timing__setup__tns": -169.977, - "finish__timing__setup__ws": -0.391331, - "finish__timing__wns_percent_delay": -19.65048, - "finish_merge__cpu__total": 11.68, - "finish_merge__mem__peak": 1122376.0, - "finish_merge__runtime__total": "0:12.50", - "floorplan__cpu__total": 913.58, - "floorplan__design__core__area": 388845, - "floorplan__design__die__area": 402470, - "floorplan__design__instance__area": 156024, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 156024, - "floorplan__design__instance__count": 88304, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 88304, - "floorplan__design__instance__utilization": 0.40125, - "floorplan__design__instance__utilization__stdcell": 0.40125, - "floorplan__design__io": 2039, - "floorplan__design__rows": 445, - "floorplan__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "floorplan__design__sites": 1461825, - "floorplan__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 4, - "floorplan__mem__peak": 507616.0, - "floorplan__power__internal__total": 0.0664338, - "floorplan__power__leakage__total": 0.00303773, - "floorplan__power__switching__total": 0.0212271, - "floorplan__power__total": 0.0906986, - "floorplan__runtime__total": "15:14.81", - "floorplan__timing__setup__tns": -2817.49, - "floorplan__timing__setup__ws": -0.269068, - "floorplan_io__cpu__total": 1.21, - "floorplan_io__mem__peak": 271052.0, - "floorplan_io__runtime__total": "0:01.43", - "floorplan_macro__cpu__total": 1.26, - "floorplan_macro__mem__peak": 266940.0, - "floorplan_macro__runtime__total": "0:01.46", - "floorplan_pdn__cpu__total": 2.0, - "floorplan_pdn__mem__peak": 281044.0, - "floorplan_pdn__runtime__total": "0:02.21", - "floorplan_tap__cpu__total": 1.07, - "floorplan_tap__mem__peak": 216004.0, - "floorplan_tap__runtime__total": "0:01.26", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 5046.49, - "globalplace__design__core__area": 388845, - "globalplace__design__die__area": 402470, - "globalplace__design__instance__area": 194470, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 194470, - "globalplace__design__instance__count": 90769, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 90769, - "globalplace__design__instance__utilization": 0.500122, - "globalplace__design__instance__utilization__stdcell": 0.500122, - "globalplace__design__io": 2039, - "globalplace__design__rows": 445, - "globalplace__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "globalplace__design__sites": 1461825, - "globalplace__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1290028.0, - "globalplace__power__internal__total": 0.0843451, - "globalplace__power__leakage__total": 0.004626, - "globalplace__power__switching__total": 0.0503784, - "globalplace__power__total": 0.139349, - "globalplace__runtime__total": "12:23.09", - "globalplace__timing__setup__tns": -396.321, - "globalplace__timing__setup__ws": -0.589477, - "globalplace_io__cpu__total": 1.78, - "globalplace_io__mem__peak": 275112.0, - "globalplace_io__runtime__total": "0:02.00", - "globalplace_skip_io__cpu__total": 696.76, - "globalplace_skip_io__mem__peak": 452828.0, - "globalplace_skip_io__runtime__total": "0:47.14", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.114484, - "globalroute__clock__skew__setup": 0.114484, - "globalroute__cpu__total": 940.12, - "globalroute__design__core__area": 388845, - "globalroute__design__die__area": 402470, - "globalroute__design__instance__area": 200559, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 200559, - "globalroute__design__instance__count": 96241, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 18, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 12, - "globalroute__design__instance__count__stdcell": 96241, - "globalroute__design__instance__displacement__max": 7.5, - "globalroute__design__instance__displacement__mean": 0.0095, - "globalroute__design__instance__displacement__total": 942.11, - "globalroute__design__instance__utilization": 0.515781, - "globalroute__design__instance__utilization__stdcell": 0.515781, - "globalroute__design__io": 2039, - "globalroute__design__rows": 445, - "globalroute__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "globalroute__design__sites": 1461825, - "globalroute__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 2231992.0, - "globalroute__power__internal__total": 0.0968627, - "globalroute__power__leakage__total": 0.00480121, - "globalroute__power__switching__total": 0.06714, - "globalroute__power__total": 0.168804, - "globalroute__route__wirelength__estimated": 2548990.0, - "globalroute__runtime__total": "11:38.16", - "globalroute__timing__clock__slack": -0.349, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 19, - "globalroute__timing__drv__max_cap_limit": -0.509248, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.133306, - "globalroute__timing__drv__setup_violation_count": 937, - "globalroute__timing__setup__tns": -169.84, - "globalroute__timing__setup__ws": -0.349232, - "placeopt__cpu__total": 115.4, - "placeopt__design__core__area": 388845, - "placeopt__design__die__area": 402470, - "placeopt__design__instance__area": 196168, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 196168, - "placeopt__design__instance__count": 92773, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 92773, - "placeopt__design__instance__utilization": 0.504487, - "placeopt__design__instance__utilization__stdcell": 0.504487, - "placeopt__design__io": 2039, - "placeopt__design__rows": 445, - "placeopt__design__rows:FreePDK45_38x28_10R_NP_162NW_34O": 445, - "placeopt__design__sites": 1461825, - "placeopt__design__sites:FreePDK45_38x28_10R_NP_162NW_34O": 1461825, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 681612.0, - "placeopt__power__internal__total": 0.0848942, - "placeopt__power__leakage__total": 0.00467809, - "placeopt__power__switching__total": 0.0507299, - "placeopt__power__total": 0.140302, - "placeopt__runtime__total": "1:55.99", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 168, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0040475, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.349581, - "placeopt__timing__drv__setup_violation_count": 975, - "placeopt__timing__setup__tns": -359.615, - "placeopt__timing__setup__ws": -0.547864, - "run__flow__design": "swerv", - "run__flow__generate_date": "2024-11-22 23:54", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17258-gc1904e24e", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "2c6f4364-17a6-43b3-a32d-f532c87a0799", - "run__flow__variant": "base", - "synth__cpu__total": 631.56, - "synth__design__instance__area__stdcell": 155952.874, - "synth__design__instance__count__stdcell": 88287.0, - "synth__mem__peak": 1229088.0, - "synth__runtime__total": "10:34.17", - "total_time": "1:07:01.330000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/swerv/rules-base.json b/flow/designs/nangate45/swerv/rules-base.json index f947405e48..26b84e8c90 100644 --- a/flow/designs/nangate45/swerv/rules-base.json +++ b/flow/designs/nangate45/swerv/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 213238, + "value": 201974, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 106074, + "value": 99342, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 9224, + "value": 8638, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 9224, + "value": 8638, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3342843, + "value": 3900533, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.49, + "value": -0.27, "compare": ">=" }, "finish__design__instance__area": { - "value": 218848, + "value": 206802, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 4612, + "value": 4319, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 431, + "value": 1165, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -22.51, + "value": -21.98, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index 0f868c0e54..2ce3c88234 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -1,14 +1,6 @@ export DESIGN_NAME = swerv_wrapper export PLATFORM = nangate45 -export SYNTH_HIERARCHICAL = 1 -# -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/swerv/macros.v export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc @@ -23,13 +15,11 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_2048x39.lib \ export DIE_AREA = 0 0 1100 1000 export CORE_AREA = 10.07 11.2 1090 990 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-200 -exclude bottom:1000-1100 +export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 -export PLACE_DENSITY_LB_ADDON = 0.25 +export PLACE_DENSITY_LB_ADDON = 0.08 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl - diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc index 308fd50a14..f7c9f08b64 100644 --- a/flow/designs/nangate45/swerv_wrapper/constraint.sdc +++ b/flow/designs/nangate45/swerv_wrapper/constraint.sdc @@ -1,6 +1,6 @@ current_design swerv_wrapper -set clk_name core_clock +set clk_name core_clock set clk_port_name clk set clk_period 2.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/nangate45/swerv_wrapper/fastroute.tcl b/flow/designs/nangate45/swerv_wrapper/fastroute.tcl index 8f1d5e070a..1086052539 100644 --- a/flow/designs/nangate45/swerv_wrapper/fastroute.tcl +++ b/flow/designs/nangate45/swerv_wrapper/fastroute.tcl @@ -1,4 +1,4 @@ -set_global_routing_layer_adjustment metal2-metal3 0.25 -set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.15 +set_global_routing_layer_adjustment metal2-metal3 0.20 +set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.10 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/designs/nangate45/swerv_wrapper/io.tcl b/flow/designs/nangate45/swerv_wrapper/io.tcl new file mode 100644 index 0000000000..74f327933a --- /dev/null +++ b/flow/designs/nangate45/swerv_wrapper/io.tcl @@ -0,0 +1,2 @@ +exclude_io_pin_region -region left:* -region right:* -region top:* \ + -region bottom:0-200 -region bottom:1000-1100 diff --git a/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json b/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json deleted file mode 100644 index 43f1b79189..0000000000 --- a/flow/designs/nangate45/swerv_wrapper/metadata-base-ok.json +++ /dev/null @@ -1,333 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2.0000" - ], - "cts__clock__skew__hold": 0.174531, - "cts__clock__skew__setup": 0.174531, - "cts__cpu__total": 2380.32, - "cts__design__core__area": 1056660.0, - "cts__design__die__area": 1100000.0, - "cts__design__instance__area": 697184, - "cts__design__instance__area__macros": 471245, - "cts__design__instance__area__stdcell": 225939, - "cts__design__instance__count": 114754, - "cts__design__instance__count__hold_buffer": 1580, - "cts__design__instance__count__macros": 28, - "cts__design__instance__count__setup_buffer": 134, - "cts__design__instance__count__stdcell": 114726, - "cts__design__instance__displacement__max": 22.51, - "cts__design__instance__displacement__mean": 0.2185, - "cts__design__instance__displacement__total": 25096.4, - "cts__design__instance__utilization": 0.659798, - "cts__design__instance__utilization__stdcell": 0.385945, - "cts__design__io": 1416, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1139752.0, - "cts__power__internal__total": 0.172351, - "cts__power__leakage__total": 0.0262166, - "cts__power__switching__total": 0.037975, - "cts__power__total": 0.236542, - "cts__route__wirelength__estimated": 4863880.0, - "cts__runtime__total": "39:41.59", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 8, - "cts__timing__drv__max_cap_limit": -0.0340501, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.338364, - "cts__timing__drv__setup_violation_count": 1415, - "cts__timing__setup__tns": -493.199, - "cts__timing__setup__ws": -0.540141, - "design__io__hpwl": 1262712732, - "design__violations": 0, - "detailedplace__cpu__total": 132.29, - "detailedplace__design__core__area": 1056660.0, - "detailedplace__design__die__area": 1100000.0, - "detailedplace__design__instance__area": 691638, - "detailedplace__design__instance__area__macros": 471245, - "detailedplace__design__instance__area__stdcell": 220394, - "detailedplace__design__instance__count": 109563, - "detailedplace__design__instance__count__macros": 28, - "detailedplace__design__instance__count__stdcell": 109535, - "detailedplace__design__instance__displacement__max": 103.643, - "detailedplace__design__instance__displacement__mean": 1.0895, - "detailedplace__design__instance__displacement__total": 119409, - "detailedplace__design__instance__utilization": 0.654549, - "detailedplace__design__instance__utilization__stdcell": 0.376472, - "detailedplace__design__io": 1416, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 822876.0, - "detailedplace__power__internal__total": 0.158749, - "detailedplace__power__leakage__total": 0.0260855, - "detailedplace__power__switching__total": 0.0219028, - "detailedplace__power__total": 0.206737, - "detailedplace__route__wirelength__estimated": 4852410.0, - "detailedplace__runtime__total": "2:12.92", - "detailedplace__timing__drv__hold_violation_count": 177, - "detailedplace__timing__drv__max_cap": 8, - "detailedplace__timing__drv__max_cap_limit": -0.0300864, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.338364, - "detailedplace__timing__drv__setup_violation_count": 1364, - "detailedplace__timing__setup__tns": -832.449, - "detailedplace__timing__setup__ws": -0.924484, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 2, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 132401, - "detailedroute__route__drc_errors__iter:10": 2302, - "detailedroute__route__drc_errors__iter:11": 917, - "detailedroute__route__drc_errors__iter:12": 422, - "detailedroute__route__drc_errors__iter:13": 128, - "detailedroute__route__drc_errors__iter:14": 13, - "detailedroute__route__drc_errors__iter:15": 0, - "detailedroute__route__drc_errors__iter:2": 67632, - "detailedroute__route__drc_errors__iter:3": 60281, - "detailedroute__route__drc_errors__iter:4": 15478, - "detailedroute__route__drc_errors__iter:5": 6850, - "detailedroute__route__drc_errors__iter:6": 4375, - "detailedroute__route__drc_errors__iter:7": 3565, - "detailedroute__route__drc_errors__iter:8": 3101, - "detailedroute__route__drc_errors__iter:9": 2711, - "detailedroute__route__net": 121517, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1134488, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1134488, - "detailedroute__route__wirelength": 6157412, - "detailedroute__route__wirelength__iter:1": 6169502, - "detailedroute__route__wirelength__iter:10": 6155563, - "detailedroute__route__wirelength__iter:11": 6156920, - "detailedroute__route__wirelength__iter:12": 6157190, - "detailedroute__route__wirelength__iter:13": 6157487, - "detailedroute__route__wirelength__iter:14": 6157438, - "detailedroute__route__wirelength__iter:15": 6157412, - "detailedroute__route__wirelength__iter:2": 6150972, - "detailedroute__route__wirelength__iter:3": 6145030, - "detailedroute__route__wirelength__iter:4": 6151367, - "detailedroute__route__wirelength__iter:5": 6152947, - "detailedroute__route__wirelength__iter:6": 6153537, - "detailedroute__route__wirelength__iter:7": 6153991, - "detailedroute__route__wirelength__iter:8": 6154368, - "detailedroute__route__wirelength__iter:9": 6154849, - "finish__clock__skew__hold": 0.219758, - "finish__clock__skew__setup": 0.219758, - "finish__cpu__total": 419.27, - "finish__design__core__area": 1056660.0, - "finish__design__die__area": 1100000.0, - "finish__design__instance__area": 698008, - "finish__design__instance__area__macros": 471245, - "finish__design__instance__area__stdcell": 226764, - "finish__design__instance__count": 114915, - "finish__design__instance__count__macros": 28, - "finish__design__instance__count__stdcell": 114887, - "finish__design__instance__utilization": 0.660578, - "finish__design__instance__utilization__stdcell": 0.387354, - "finish__design__io": 1416, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.08861, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0100697, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0368697, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0401713, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.06313, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0401713, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 2800348.0, - "finish__power__internal__total": 0.172629, - "finish__power__leakage__total": 0.0262557, - "finish__power__switching__total": 0.0433627, - "finish__power__total": 0.242248, - "finish__runtime__total": "7:03.21", - "finish__timing__drv__hold_violation_count": 815, - "finish__timing__drv__max_cap": 338, - "finish__timing__drv__max_cap_limit": -3.27373, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 15, - "finish__timing__drv__max_slew_limit": -0.8498, - "finish__timing__drv__setup_violation_count": 1462, - "finish__timing__setup__tns": -582.967, - "finish__timing__setup__ws": -0.691215, - "finish__timing__wns_percent_delay": -21.587857, - "finish_merge__cpu__total": 16.22, - "finish_merge__mem__peak": 1406352.0, - "finish_merge__runtime__total": "0:17.50", - "floorplan__cpu__total": 1408.79, - "floorplan__design__core__area": 1056660.0, - "floorplan__design__die__area": 1100000.0, - "floorplan__design__instance__area": 642430, - "floorplan__design__instance__area__macros": 471245, - "floorplan__design__instance__area__stdcell": 171185, - "floorplan__design__instance__count": 98163, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 28, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 98135, - "floorplan__design__instance__utilization": 0.60798, - "floorplan__design__instance__utilization__stdcell": 0.292415, - "floorplan__design__io": 1416, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 3, - "floorplan__mem__peak": 556196.0, - "floorplan__power__internal__total": 0.153413, - "floorplan__power__leakage__total": 0.0240802, - "floorplan__power__switching__total": 0.0106987, - "floorplan__power__total": 0.188192, - "floorplan__runtime__total": "23:29.47", - "floorplan__timing__setup__tns": -3483.36, - "floorplan__timing__setup__ws": -0.441148, - "floorplan_io__cpu__total": 1.07, - "floorplan_io__mem__peak": 281064.0, - "floorplan_io__runtime__total": "0:01.34", - "floorplan_macro__cpu__total": 336.11, - "floorplan_macro__mem__peak": 859832.0, - "floorplan_macro__runtime__total": "0:38.50", - "floorplan_pdn__cpu__total": 4.59, - "floorplan_pdn__mem__peak": 358228.0, - "floorplan_pdn__runtime__total": "0:04.88", - "floorplan_tap__cpu__total": 1.02, - "floorplan_tap__mem__peak": 229284.0, - "floorplan_tap__runtime__total": "0:01.28", - "floorplan_tdms__cpu__total": 0.08, - "floorplan_tdms__mem__peak": 100116.0, - "floorplan_tdms__runtime__total": "0:00.20", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 4036.45, - "globalplace__design__core__area": 1056660.0, - "globalplace__design__die__area": 1100000.0, - "globalplace__design__instance__area": 644378, - "globalplace__design__instance__area__macros": 471245, - "globalplace__design__instance__area__stdcell": 173134, - "globalplace__design__instance__count": 105488, - "globalplace__design__instance__count__macros": 28, - "globalplace__design__instance__count__stdcell": 105460, - "globalplace__design__instance__utilization": 0.609824, - "globalplace__design__instance__utilization__stdcell": 0.295743, - "globalplace__design__io": 1416, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1590152.0, - "globalplace__power__internal__total": 0.153916, - "globalplace__power__leakage__total": 0.0240802, - "globalplace__power__switching__total": 0.0187383, - "globalplace__power__total": 0.196734, - "globalplace__runtime__total": "14:06.66", - "globalplace__timing__setup__tns": -18370.4, - "globalplace__timing__setup__ws": -3.43387, - "globalplace_io__cpu__total": 1.57, - "globalplace_io__mem__peak": 299428.0, - "globalplace_io__runtime__total": "0:01.83", - "globalplace_skip_io__cpu__total": 1015.12, - "globalplace_skip_io__mem__peak": 495308.0, - "globalplace_skip_io__runtime__total": "1:02.39", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.206788, - "globalroute__clock__skew__setup": 0.206788, - "globalroute__cpu__total": 1532.68, - "globalroute__design__core__area": 1056660.0, - "globalroute__design__die__area": 1100000.0, - "globalroute__design__instance__area": 698008, - "globalroute__design__instance__area__macros": 471245, - "globalroute__design__instance__area__stdcell": 226764, - "globalroute__design__instance__count": 114915, - "globalroute__design__instance__count__hold_buffer": 52, - "globalroute__design__instance__count__macros": 28, - "globalroute__design__instance__count__setup_buffer": 11, - "globalroute__design__instance__count__stdcell": 114887, - "globalroute__design__instance__displacement__max": 12.7, - "globalroute__design__instance__displacement__mean": 0.0435, - "globalroute__design__instance__displacement__total": 5027.9, - "globalroute__design__instance__utilization": 0.660578, - "globalroute__design__instance__utilization__stdcell": 0.387354, - "globalroute__design__io": 1416, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 2652812.0, - "globalroute__power__internal__total": 0.172359, - "globalroute__power__leakage__total": 0.0262557, - "globalroute__power__switching__total": 0.0393215, - "globalroute__power__total": 0.237936, - "globalroute__route__wirelength__estimated": 4872060.0, - "globalroute__runtime__total": "20:50.11", - "globalroute__timing__clock__slack": -0.574, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 114, - "globalroute__timing__drv__max_cap_limit": -2.53479, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 3, - "globalroute__timing__drv__max_slew_limit": -0.505126, - "globalroute__timing__drv__setup_violation_count": 1217, - "globalroute__timing__setup__tns": -453.026, - "globalroute__timing__setup__ws": -0.574133, - "placeopt__cpu__total": 133.27, - "placeopt__design__core__area": 1056660.0, - "placeopt__design__die__area": 1100000.0, - "placeopt__design__instance__area": 691638, - "placeopt__design__instance__area__macros": 471245, - "placeopt__design__instance__area__stdcell": 220394, - "placeopt__design__instance__count": 109563, - "placeopt__design__instance__count__macros": 28, - "placeopt__design__instance__count__stdcell": 109535, - "placeopt__design__instance__utilization": 0.654549, - "placeopt__design__instance__utilization__stdcell": 0.376472, - "placeopt__design__io": 1416, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 854304.0, - "placeopt__power__internal__total": 0.158746, - "placeopt__power__leakage__total": 0.0260855, - "placeopt__power__switching__total": 0.0218914, - "placeopt__power__total": 0.206723, - "placeopt__runtime__total": "2:14.00", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 175, - "placeopt__timing__drv__max_cap": 1, - "placeopt__timing__drv__max_cap_limit": -0.0325834, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.348147, - "placeopt__timing__drv__setup_violation_count": 1364, - "placeopt__timing__setup__tns": -827.018, - "placeopt__timing__setup__ws": -0.920516, - "run__flow__design": "swerv_wrapper", - "run__flow__generate_date": "2024-09-27 20:26", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "6fac9442-fc01-4b30-ba0c-7900b3282062", - "run__flow__variant": "base", - "synth__cpu__total": 519.96, - "synth__design__instance__area__stdcell": 642344.514, - "synth__design__instance__count__stdcell": 98157.0, - "synth__mem__peak": 696440.0, - "synth__runtime__total": "8:43.05", - "total_time": "2:00:28.930000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/swerv_wrapper/rules-base.json b/flow/designs/nangate45/swerv_wrapper/rules-base.json index 76cc3754de..4d68fe18d5 100644 --- a/flow/designs/nangate45/swerv_wrapper/rules-base.json +++ b/flow/designs/nangate45/swerv_wrapper/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 737362.47, + "value": 724516.2, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 783985, + "value": 755158, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 123213, + "value": 113069, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 10714, + "value": 9832, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 10714, + "value": 9832, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 7081024, + "value": 5365759, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,27 +44,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.79, + "value": -0.32, "compare": ">=" }, "finish__design__instance__area": { - "value": 790704, + "value": 762884, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 5357, + "value": 4916, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 1119, + "value": 656, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -35.9, + "value": -19.88, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/config.mk b/flow/designs/nangate45/tinyRocket/config.mk index d06262dd95..02dd38d64c 100644 --- a/flow/designs/nangate45/tinyRocket/config.mk +++ b/flow/designs/nangate45/tinyRocket/config.mk @@ -3,7 +3,7 @@ export DESIGN_NAME = RocketTile export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 5000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 5000 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ diff --git a/flow/designs/nangate45/tinyRocket/metadata-base-ok.json b/flow/designs/nangate45/tinyRocket/metadata-base-ok.json deleted file mode 100644 index ee2f7d513f..0000000000 --- a/flow/designs/nangate45/tinyRocket/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1.2000" - ], - "cts__clock__skew__hold": 0.0743302, - "cts__clock__skew__setup": 0.0743302, - "cts__cpu__total": 301.84, - "cts__design__core__area": 193770, - "cts__design__die__area": 212205, - "cts__design__instance__area": 59170.9, - "cts__design__instance__area__macros": 2481.25, - "cts__design__instance__area__stdcell": 56689.7, - "cts__design__instance__count": 29761, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 2, - "cts__design__instance__count__setup_buffer": 63, - "cts__design__instance__count__stdcell": 29759, - "cts__design__instance__displacement__max": 3.91, - "cts__design__instance__displacement__mean": 0.005, - "cts__design__instance__displacement__total": 152.196, - "cts__design__instance__utilization": 0.305366, - "cts__design__instance__utilization__stdcell": 0.296356, - "cts__design__io": 269, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 566904.0, - "cts__power__internal__total": 0.0749224, - "cts__power__leakage__total": 0.00138554, - "cts__power__switching__total": 0.0498891, - "cts__power__total": 0.126197, - "cts__route__wirelength__estimated": 632759, - "cts__runtime__total": "5:02.30", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.061686, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.374084, - "cts__timing__drv__setup_violation_count": 819, - "cts__timing__setup__tns": -126.286, - "cts__timing__setup__ws": -0.234167, - "design__io__hpwl": 31966700, - "design__violations": 0, - "detailedplace__cpu__total": 22.56, - "detailedplace__design__core__area": 193770, - "detailedplace__design__die__area": 212205, - "detailedplace__design__instance__area": 57553.4, - "detailedplace__design__instance__area__macros": 2481.25, - "detailedplace__design__instance__area__stdcell": 55072.1, - "detailedplace__design__instance__count": 28422, - "detailedplace__design__instance__count__macros": 2, - "detailedplace__design__instance__count__stdcell": 28420, - "detailedplace__design__instance__displacement__max": 7.7295, - "detailedplace__design__instance__displacement__mean": 0.803, - "detailedplace__design__instance__displacement__total": 22831.2, - "detailedplace__design__instance__utilization": 0.297018, - "detailedplace__design__instance__utilization__stdcell": 0.2879, - "detailedplace__design__io": 269, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 282548.0, - "detailedplace__power__internal__total": 0.0665784, - "detailedplace__power__leakage__total": 0.00134438, - "detailedplace__power__switching__total": 0.0403968, - "detailedplace__power__total": 0.10832, - "detailedplace__route__wirelength__estimated": 621491, - "detailedplace__runtime__total": "0:22.76", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 1, - "detailedplace__timing__drv__max_cap_limit": -0.0357498, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.332616, - "detailedplace__timing__drv__setup_violation_count": 802, - "detailedplace__timing__setup__tns": -167.184, - "detailedplace__timing__setup__ws": -0.343823, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 1, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 5239, - "detailedroute__route__drc_errors__iter:2": 985, - "detailedroute__route__drc_errors__iter:3": 702, - "detailedroute__route__drc_errors__iter:4": 36, - "detailedroute__route__drc_errors__iter:5": 1, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 33282, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 212287, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 212287, - "detailedroute__route__wirelength": 735826, - "detailedroute__route__wirelength__iter:1": 738281, - "detailedroute__route__wirelength__iter:2": 735944, - "detailedroute__route__wirelength__iter:3": 735749, - "detailedroute__route__wirelength__iter:4": 735827, - "detailedroute__route__wirelength__iter:5": 735828, - "detailedroute__route__wirelength__iter:6": 735826, - "finish__clock__skew__hold": 0.0801091, - "finish__clock__skew__setup": 0.0801091, - "finish__cpu__total": 57.84, - "finish__design__core__area": 193770, - "finish__design__die__area": 212205, - "finish__design__instance__area": 59514.3, - "finish__design__instance__area__macros": 2481.25, - "finish__design__instance__area__stdcell": 57033.1, - "finish__design__instance__count": 29841, - "finish__design__instance__count__macros": 2, - "finish__design__instance__count__stdcell": 29839, - "finish__design__instance__utilization": 0.307138, - "finish__design__instance__utilization__stdcell": 0.298151, - "finish__design__io": 269, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.0639, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0333067, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0676213, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0656346, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.03238, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0656346, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 898008.0, - "finish__power__internal__total": 0.07523, - "finish__power__leakage__total": 0.00140148, - "finish__power__switching__total": 0.0525837, - "finish__power__total": 0.129215, - "finish__runtime__total": "0:58.63", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 7, - "finish__timing__drv__max_cap_limit": -0.131445, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.228003, - "finish__timing__drv__setup_violation_count": 848, - "finish__timing__setup__tns": -124.44, - "finish__timing__setup__ws": -0.255331, - "finish__timing__wns_percent_delay": -14.684229, - "finish_merge__cpu__total": 3.44, - "finish_merge__mem__peak": 634508.0, - "finish_merge__runtime__total": "0:03.77", - "floorplan__cpu__total": 125.84, - "floorplan__design__core__area": 193770, - "floorplan__design__die__area": 212205, - "floorplan__design__instance__area": 52364.8, - "floorplan__design__instance__area__macros": 2481.25, - "floorplan__design__instance__area__stdcell": 49883.5, - "floorplan__design__instance__count": 26582, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 2, - "floorplan__design__instance__count__setup_buffer": 6, - "floorplan__design__instance__count__stdcell": 26580, - "floorplan__design__instance__utilization": 0.270241, - "floorplan__design__instance__utilization__stdcell": 0.260775, - "floorplan__design__io": 269, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 18045, - "floorplan__mem__peak": 230692.0, - "floorplan__power__internal__total": 0.059014, - "floorplan__power__leakage__total": 0.0011451, - "floorplan__power__switching__total": 0.0218639, - "floorplan__power__total": 0.082023, - "floorplan__runtime__total": "2:06.03", - "floorplan__timing__setup__tns": -51.2311, - "floorplan__timing__setup__ws": -0.122061, - "floorplan_io__cpu__total": 0.37, - "floorplan_io__mem__peak": 161316.0, - "floorplan_io__runtime__total": "0:00.46", - "floorplan_macro__cpu__total": 95.76, - "floorplan_macro__mem__peak": 226712.0, - "floorplan_macro__runtime__total": "0:36.75", - "floorplan_pdn__cpu__total": 0.72, - "floorplan_pdn__mem__peak": 180988.0, - "floorplan_pdn__runtime__total": "0:00.84", - "floorplan_tap__cpu__total": 0.44, - "floorplan_tap__mem__peak": 147556.0, - "floorplan_tap__runtime__total": "0:00.55", - "floorplan_tdms__cpu__total": 0.06, - "floorplan_tdms__mem__peak": 100204.0, - "floorplan_tdms__runtime__total": "0:00.12", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1550.01, - "globalplace__design__core__area": 193770, - "globalplace__design__die__area": 212205, - "globalplace__design__instance__area": 52723.9, - "globalplace__design__instance__area__macros": 2481.25, - "globalplace__design__instance__area__stdcell": 50242.6, - "globalplace__design__instance__count": 27932, - "globalplace__design__instance__count__macros": 2, - "globalplace__design__instance__count__stdcell": 27930, - "globalplace__design__instance__utilization": 0.272095, - "globalplace__design__instance__utilization__stdcell": 0.262653, - "globalplace__design__io": 269, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 660072.0, - "globalplace__power__internal__total": 0.059813, - "globalplace__power__leakage__total": 0.0011451, - "globalplace__power__switching__total": 0.036659, - "globalplace__power__total": 0.0976171, - "globalplace__runtime__total": "3:08.11", - "globalplace__timing__setup__tns": -765.157, - "globalplace__timing__setup__ws": -0.559994, - "globalplace_io__cpu__total": 0.41, - "globalplace_io__mem__peak": 165684.0, - "globalplace_io__runtime__total": "0:00.48", - "globalplace_skip_io__cpu__total": 452.28, - "globalplace_skip_io__mem__peak": 201300.0, - "globalplace_skip_io__runtime__total": "0:32.45", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.0722478, - "globalroute__clock__skew__setup": 0.0722478, - "globalroute__cpu__total": 226.67, - "globalroute__design__core__area": 193770, - "globalroute__design__die__area": 212205, - "globalroute__design__instance__area": 59514.3, - "globalroute__design__instance__area__macros": 2481.25, - "globalroute__design__instance__area__stdcell": 57033.1, - "globalroute__design__instance__count": 29841, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 2, - "globalroute__design__instance__count__setup_buffer": 51, - "globalroute__design__instance__count__stdcell": 29839, - "globalroute__design__instance__displacement__max": 3.04, - "globalroute__design__instance__displacement__mean": 0.0065, - "globalroute__design__instance__displacement__total": 207.28, - "globalroute__design__instance__utilization": 0.307138, - "globalroute__design__instance__utilization__stdcell": 0.298151, - "globalroute__design__io": 269, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 783700.0, - "globalroute__power__internal__total": 0.0751796, - "globalroute__power__leakage__total": 0.00140148, - "globalroute__power__switching__total": 0.0516186, - "globalroute__power__total": 0.1282, - "globalroute__route__wirelength__estimated": 634959, - "globalroute__runtime__total": "3:18.41", - "globalroute__timing__clock__slack": -0.234, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 5, - "globalroute__timing__drv__max_cap_limit": -0.14958, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.284449, - "globalroute__timing__drv__setup_violation_count": 860, - "globalroute__timing__setup__tns": -117.925, - "globalroute__timing__setup__ws": -0.233794, - "placeopt__cpu__total": 23.13, - "placeopt__design__core__area": 193770, - "placeopt__design__die__area": 212205, - "placeopt__design__instance__area": 57553.4, - "placeopt__design__instance__area__macros": 2481.25, - "placeopt__design__instance__area__stdcell": 55072.1, - "placeopt__design__instance__count": 28422, - "placeopt__design__instance__count__macros": 2, - "placeopt__design__instance__count__stdcell": 28420, - "placeopt__design__instance__utilization": 0.297018, - "placeopt__design__instance__utilization__stdcell": 0.2879, - "placeopt__design__io": 269, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 438796.0, - "placeopt__power__internal__total": 0.0665782, - "placeopt__power__leakage__total": 0.00134438, - "placeopt__power__switching__total": 0.0404714, - "placeopt__power__total": 0.108394, - "placeopt__runtime__total": "0:23.48", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0348883, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.362422, - "placeopt__timing__drv__setup_violation_count": 802, - "placeopt__timing__setup__tns": -165.833, - "placeopt__timing__setup__ws": -0.342148, - "run__flow__design": "tinyRocket", - "run__flow__generate_date": "2024-09-26 21:20", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "nangate45", - "run__flow__platform__capacitance_units": "1fF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "670e49be-55ac-4f82-ac51-4a321a4bc665", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 61.92, - "synth__design__instance__area__stdcell": 52201.436, - "synth__design__instance__count__stdcell": 26576.0, - "synth__mem__peak": 256160.0, - "synth__runtime__total": "1:02.43", - "total_time": "0:17:37.570000" -} \ No newline at end of file diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index feee30a245..3dae8034e6 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 60031.66, + "value": 59681.09, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 66186, + "value": 64542, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 32683, + "value": 32493, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2842, + "value": 2826, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2842, + "value": 2826, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 846200, + "value": 763092, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.31, + "value": -0.19, "compare": ">=" }, "finish__design__instance__area": { - "value": 68441, + "value": 66595, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1421, + "value": 1413, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -27.62, + "value": -15.79, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/rapidus2hp/README.md b/flow/designs/rapidus2hp/README.md new file mode 100644 index 0000000000..264a51859a --- /dev/null +++ b/flow/designs/rapidus2hp/README.md @@ -0,0 +1,14 @@ +# Rapidus Environment Setup + +## Clone Rapidus Repo from Private GH + +The ORFS-specific files for the Rapidus platform are stored separately in the private rapidus repo. Clone out the repo into a separate directory and then set PLATFORM_HOME to point to it: + +``` +cd rapidus_platform_dir_goes_here +git clone git@github.com:The-OpenROAD-Project-private/rapidus +export PLATFORM_HOME=`pwd`/rapidus_platform_dir_goes_here +``` + +For more information, check out (http://github.com/The-OpenROAD-Project-private/rapidus) + diff --git a/flow/designs/rapidus2hp/cva6/autotuner.json b/flow/designs/rapidus2hp/cva6/autotuner.json new file mode 100644 index 0000000000..734b7d6808 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/autotuner.json @@ -0,0 +1,51 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 990, + 1250 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "int", + "minmax": [ + 40, + 60 + ], + "step": 1 + }, + "CTS_BUF_DISTANCE": { + "type": "int", + "minmax": [ + 25, + 50 + ], + "step": 1 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 30, + 60 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 15, + 25 + ], + "step": 1 + }, + "CORE_MARGIN": { + "type": "float", + "minmax": [ + 1.8, + 2.1 + ], + "step": 0 + } +} diff --git a/flow/designs/rapidus2hp/cva6/canonicalize.tcl b/flow/designs/rapidus2hp/cva6/canonicalize.tcl new file mode 100644 index 0000000000..d9f81be71f --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/canonicalize.tcl @@ -0,0 +1,4 @@ +# Remove rvfi_probes_o interface since it's not in the baseline and contributes +# 4k ports and connections (many of which are buffers tied to tie cells) + +delete cva6/o:rvfi_probes_o* diff --git a/flow/designs/rapidus2hp/cva6/config.mk b/flow/designs/rapidus2hp/cva6/config.mk new file mode 100644 index 0000000000..7d2fa62b8c --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/config.mk @@ -0,0 +1,130 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = cva6 + +# Some files are listed specifically vs. sorted wilcard to control the order (makes Verific happy) +export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME) +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \ + $(SRC_HOME)/core/include/config_pkg.sv \ + $(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \ + $(SRC_HOME)/core/include/riscv_pkg.sv \ + $(SRC_HOME)/core/include/ariane_pkg.sv \ + $(SRC_HOME)/core/include/build_config_pkg.sv \ + $(SRC_HOME)/core/include/std_cache_pkg.sv \ + $(SRC_HOME)/core/include/wt_cache_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \ + $(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \ + $(sort $(wildcard $(SRC_HOME)/core/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \ + $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \ + $(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \ + $(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \ + $(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \ + $(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \ + $(PLATFORM_DIR)/ram/verilog/fakeram7_64x25_shim.sv \ + $(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv + +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \ + $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include + +export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \ + $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef + +export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \ + $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL = 1 + +ifeq ($(SYNTH_HDL_FRONTEND),verific) + # Reduce utilization for verific since it runs into issues with DPL not being + # able to place instances or with one-site gap/overlap issues + export CORE_UTILIZATION = 45 +else + # Reduce the amount of resizing done between GPL and DPL + export EARLY_SIZING_CAP_RATIO = 6 + ifeq ($(PLACE_SITE),SC6T) + # Decrease the utilization so that the tall macros fit + export CORE_UTILIZATION = 50 + else + export CORE_UTILIZATION = 55 + endif +endif + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 2 2 + +export PLACE_DENSITY = 0.65 + +export ENABLE_DPO = 0 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 + +#export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl + +# Remove rvfi_probes_o interface +export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl diff --git a/flow/designs/rapidus2hp/cva6/constraint.sdc b/flow/designs/rapidus2hp/cva6/constraint.sdc new file mode 100644 index 0000000000..f263502816 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/constraint.sdc @@ -0,0 +1,9 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1380 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/rapidus2hp/cva6/io_constraints.tcl b/flow/designs/rapidus2hp/cva6/io_constraints.tcl new file mode 100644 index 0000000000..44c48e5927 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/io_constraints.tcl @@ -0,0 +1,34 @@ +# left (bottom to top) +set_io_pin_constraint -group -order -region left:4.09-40.70 -pin_names {cvxif_req_o[*]} +set_io_pin_constraint -group -order -region left:40.85-90.13 -pin_names {noc_req_o[*]} + +# right (bottom to top) +# The intervals have been expanded based on pin placer feedback +set_io_pin_constraint -group -order -region right:5.25-45.34 -pin_names {noc_resp_i[*]} +set_io_pin_constraint -group -order -region right:45.62-93.07 -pin_names {cvxif_resp_i[*]} +set_io_pin_constraint -group -order -region right:93.32-93.73 \ + -pin_names { + debug_req_i time_irq_i ipi_i + } +set_io_pin_constraint -group -order -region right:94.01-94.28 -pin_names {irq_i[*]} +set_io_pin_constraint -group -order -region right:94.51-102.01 -pin_names {hart_id_i[*]} +set_io_pin_constraint -group -order -region right:102.25-109.74 -pin_names {boot_addr_i[*]} +set_io_pin_constraint -group -order -region right:109.99-110.25 -pin_names {rst_ni clk_i} + +# The rvfi_probes_o pins don't exist in reference design implementation +# put a third of them on the top, a third on the bottom, and let the placer +# decide where to put the remaining third +set num_rvfi_probes_ports 4295 +set third_rvfi_probes_ports [expr $num_rvfi_probes_ports / 3] +set top_group {} +for { set i 0 } { $i < $third_rvfi_probes_ports } { incr i } { + lappend top_group "rvfi_probes_o\[$i\]" +} +set bottom_group {} +for { } { $i < $third_rvfi_probes_ports * 2 } { incr i } { + lappend bottom_group "rvfi_probes_o\[$i\]" +} + + +set_io_pin_constraint -group -order -region bottom:* -pin_names $top_group +set_io_pin_constraint -group -order -region top:* -pin_names $bottom_group diff --git a/flow/designs/rapidus2hp/cva6/opt_constraint.sdc b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc new file mode 100644 index 0000000000..b0692f6387 --- /dev/null +++ b/flow/designs/rapidus2hp/cva6/opt_constraint.sdc @@ -0,0 +1,9 @@ +# Derived from cva6_synth.tcl and Makefiles + +set clk_name main_clk +set clk_port clk_i +set clk_ports_list [list $clk_port] +set clk_period 1013.87619516354 +set input_delay 0.46 +set output_delay 0.11 +create_clock [get_ports $clk_port] -name $clk_name -period $clk_period diff --git a/flow/designs/tsmc65lp/tinyRocket/rules-base.json b/flow/designs/rapidus2hp/cva6/rules-base.json similarity index 75% rename from flow/designs/tsmc65lp/tinyRocket/rules-base.json rename to flow/designs/rapidus2hp/cva6/rules-base.json index f44ad4763d..753f8242ae 100644 --- a/flow/designs/tsmc65lp/tinyRocket/rules-base.json +++ b/flow/designs/rapidus2hp/cva6/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 202377.17, + "value": 13516.26, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 237278, + "value": 14746, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 31036, + "value": 171414, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,18 +20,14 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2699, + "value": 14906, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2699, + "value": 14906, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 1259007, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, @@ -40,15 +36,15 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 239332, + "value": 15035, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1349, + "value": 7453, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 155, + "value": 795, "compare": "<=" }, "finish__timing__wns_percent_delay": { diff --git a/flow/designs/rapidus2hp/ethmac/config.mk b/flow/designs/rapidus2hp/ethmac/config.mk new file mode 100644 index 0000000000..b3507b64a9 --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/config.mk @@ -0,0 +1,12 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = ethmac + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.70 diff --git a/flow/designs/rapidus2hp/ethmac/constraint.sdc b/flow/designs/rapidus2hp/ethmac/constraint.sdc new file mode 100644 index 0000000000..4a74470ec5 --- /dev/null +++ b/flow/designs/rapidus2hp/ethmac/constraint.sdc @@ -0,0 +1,39 @@ +set top_clk_name wb_clk_i +set clk_period 875 +set clk_io_pct 0.2 +set clk_port [get_ports $top_clk_name] +create_clock -name $top_clk_name -period $clk_period $clk_port +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \ + [all_outputs] + +set tx_clk_name mtx_clk_pad_i +set tx_clk_port [get_ports $tx_clk_name] +set tx_clk_period 300 +create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port +set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $tx_clk_port] +set_input_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + $mtx_non_clock_inputs +set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \ + [all_outputs] + +set rx_clk_name mrx_clk_pad_i +set rx_clk_port [get_ports $rx_clk_name] +set rx_clk_period 200 +create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port +set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \ + $rx_clk_port] +set_input_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + $mrx_non_clock_inputs +set_output_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \ + [all_outputs] + +set_clock_groups -name core_clock -logically_exclusive \ + -group [get_clocks $top_clk_name] \ + -group [get_clocks $tx_clk_name] \ + -group [get_clocks $rx_clk_name] + +set_max_fanout 10 [current_design] diff --git a/flow/designs/tsmc65lp/coyote/rules-hier_rtlmp.json b/flow/designs/rapidus2hp/ethmac/rules-base.json similarity index 75% rename from flow/designs/tsmc65lp/coyote/rules-hier_rtlmp.json rename to flow/designs/rapidus2hp/ethmac/rules-base.json index b15fd7a24d..4bd46bb845 100644 --- a/flow/designs/tsmc65lp/coyote/rules-hier_rtlmp.json +++ b/flow/designs/rapidus2hp/ethmac/rules-base.json @@ -1,18 +1,18 @@ { "synth__design__instance__area__stdcell": { - "value": 17267.12, + "value": 3307.96, "compare": "<=" }, "constraints__clocks__count": { - "value": 1, + "value": 3, "compare": "==" }, "placeopt__design__instance__area": { - "value": 3443931, + "value": 3774, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 472461, + "value": 70864, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,18 +20,14 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 41084, + "value": 6162, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 41084, + "value": 6162, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 17900747, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, @@ -40,11 +36,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 3464597, + "value": 3961, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 20542, + "value": 3081, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/rapidus2hp/gcd/autotuner.json b/flow/designs/rapidus2hp/gcd/autotuner.json new file mode 100644 index 0000000000..e622bbf82d --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/autotuner.json @@ -0,0 +1,35 @@ +{ + "_SDC_FILE_PATH": "constraint.sdc", + "_SDC_CLK_PERIOD": { + "type": "float", + "minmax": [ + 180, + 300 + ], + "step": 0 + }, + "CORE_UTILIZATION": { + "type": "float", + "minmax": [ + 21, + 60 + ], + "step": 0 + }, + "CTS_CLUSTER_SIZE": { + "type": "int", + "minmax": [ + 10, + 200 + ], + "step": 1 + }, + "CTS_CLUSTER_DIAMETER": { + "type": "int", + "minmax": [ + 20, + 400 + ], + "step": 1 + } +} diff --git a/flow/designs/rapidus2hp/gcd/config.mk b/flow/designs/rapidus2hp/gcd/config.mk new file mode 100644 index 0000000000..0dae84d592 --- /dev/null +++ b/flow/designs/rapidus2hp/gcd/config.mk @@ -0,0 +1,10 @@ +export DESIGN_NICKNAME = gcd +export DESIGN_NAME = gcd +export PLATFORM = rapidus2hp + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc + +export CORE_UTILIZATION = 30 +export CORE_MARGIN = .75 +export PLACE_DENSITY = 0.42 diff --git a/flow/designs/sky130hd_fakestack/gcd/constraint.sdc b/flow/designs/rapidus2hp/gcd/constraint.sdc similarity index 52% rename from flow/designs/sky130hd_fakestack/gcd/constraint.sdc rename to flow/designs/rapidus2hp/gcd/constraint.sdc index 6233db67f7..b64f4c437c 100644 --- a/flow/designs/sky130hd_fakestack/gcd/constraint.sdc +++ b/flow/designs/rapidus2hp/gcd/constraint.sdc @@ -1,8 +1,8 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 4.3647 +set clk_period 150 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -11,5 +11,7 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/tsmc65lp/vanilla5/rules-base.json b/flow/designs/rapidus2hp/gcd/rules-base.json similarity index 77% rename from flow/designs/tsmc65lp/vanilla5/rules-base.json rename to flow/designs/rapidus2hp/gcd/rules-base.json index ca04e4fa1d..319a54b30a 100644 --- a/flow/designs/tsmc65lp/vanilla5/rules-base.json +++ b/flow/designs/rapidus2hp/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 160478.75, + "value": 20.89, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 216798, + "value": 31, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21096, + "value": 638, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,18 +20,14 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1834, + "value": 56, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1834, + "value": 56, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 726570, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, @@ -40,11 +36,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 222773, + "value": 33, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 917, + "value": 28, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/rapidus2hp/hercules_idecode/config.mk b/flow/designs/rapidus2hp/hercules_idecode/config.mk new file mode 100644 index 0000000000..ed5476c571 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_idecode/config.mk @@ -0,0 +1,23 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = hercules_idecode + +export SRC_HOME = /platforms/Rapidus/designs/hercules_idecode +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/hercules_idecode/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv)) + +export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_idecode/verilog \ + $(SRC_HOME)/shared/verilog \ + $(SRC_HOME)/models/cells/generic + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc + +export SYNTH_HDL_FRONTEND ?= slang +export CORE_UTILIZATION = 25 +export CORE_MARGIN = 1 +export PLACE_DENSITY = 0.50 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 diff --git a/flow/designs/rapidus2hp/hercules_idecode/prects.sdc b/flow/designs/rapidus2hp/hercules_idecode/prects.sdc new file mode 100755 index 0000000000..81fbee7ddf --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_idecode/prects.sdc @@ -0,0 +1,12 @@ +#set sdc_version 2.1 +set sdc_version 1.4 +current_design hercules_idecode + +set clk_period 250 + +set_max_fanout 32 [current_design] +set_load 10 [all_outputs] +set_max_capacitance 10 [all_inputs] + +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr 0.5*$clk_period]] [get_ports clk] diff --git a/flow/designs/intel22/gcd/rules-base.json b/flow/designs/rapidus2hp/hercules_idecode/rules-base.json similarity index 73% rename from flow/designs/intel22/gcd/rules-base.json rename to flow/designs/rapidus2hp/hercules_idecode/rules-base.json index ce279935e6..35451503fe 100644 --- a/flow/designs/intel22/gcd/rules-base.json +++ b/flow/designs/rapidus2hp/hercules_idecode/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 195.62, + "value": 8741.01, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 241, + "value": 17454, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 379, + "value": 315828, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,39 +20,35 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 59, + "value": 27463, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 33, + "value": 27463, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 3011, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -149.47, + "value": -79.25, "compare": ">=" }, "finish__design__instance__area": { - "value": 294, + "value": 17734, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 16, + "value": 13732, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 149, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -14.8, + "value": -31.7, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/rapidus2hp/hercules_is_int/config.mk b/flow/designs/rapidus2hp/hercules_is_int/config.mk new file mode 100644 index 0000000000..e086fe6907 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/config.mk @@ -0,0 +1,43 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = hercules_is_int + +export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int + +ifeq ($(FLOW_VARIANT), gatelevel) + export SYNTH_NETLIST_FILES = $(SRC_HOME)/ca78_8t_postroute_0707.v +endif + +export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \ + $(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv)) + +export VERILOG_INCLUDE_DIRS = $(SRC_HOME)/hercules_issue/verilog \ + $(SRC_HOME)/shared/verilog \ + $(SRC_HOME)/models/cells/generic + +export VERILOG_DEFINES += + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc + +# Must be defined before the ifeq's +export SYNTH_HDL_FRONTEND = slang +export SYNTH_HIERARCHICAL ?= 0 + +ifeq ($(PLACE_SITE), SC6T) + export CORE_UTILIZATION = 30 +else + export CORE_UTILIZATION = 35 +endif + +export CORE_MARGIN = 2 +export MACRO_PLACE_HALO = 2 2 + +export PLACE_DENSITY = 0.58 + +# a smoketest for this option, there are a +# few last gasp iterations +export SKIP_LAST_GASP ?= 1 + +# For use with SYNTH_HIERARCHICAL +export SYNTH_MINIMUM_KEEP_SIZE ?= 40000 diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc new file mode 100644 index 0000000000..934de6be54 --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/prects.sdc @@ -0,0 +1,12 @@ +#set sdc_version 2.1 +set sdc_version 1.4 +current_design hercules_is_int + +set clk_period 250 + +set_max_fanout 32 [current_design] +set_load 10 [all_outputs] +set_max_capacitance 10 [all_inputs] + +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk] diff --git a/flow/designs/rapidus2hp/hercules_is_int/prects_prop.sdc b/flow/designs/rapidus2hp/hercules_is_int/prects_prop.sdc new file mode 100644 index 0000000000..acdd9ba08c --- /dev/null +++ b/flow/designs/rapidus2hp/hercules_is_int/prects_prop.sdc @@ -0,0 +1,14 @@ +#set sdc_version 2.1 +set sdc_version 1.4 +current_design hercules_is_int + +set clk_period 250 + +set_max_fanout 32 [current_design] +set_load 10 [all_outputs] +set_max_capacitance 10 [all_inputs] + +create_clock -name "clk" -add -period $clk_period \ + -waveform [list 0.0 [expr { 0.5 * $clk_period }]] [get_ports clk] + +set_propagated_clock [all_clocks] diff --git a/flow/designs/tsmc65lp/gcd/rules-base.json b/flow/designs/rapidus2hp/hercules_is_int/rules-base.json similarity index 73% rename from flow/designs/tsmc65lp/gcd/rules-base.json rename to flow/designs/rapidus2hp/hercules_is_int/rules-base.json index 68f7159a15..254e1b0542 100644 --- a/flow/designs/tsmc65lp/gcd/rules-base.json +++ b/flow/designs/rapidus2hp/hercules_is_int/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2493.39, + "value": 26638.13, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2849, + "value": 44052, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 632, + "value": 750846, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,39 +20,35 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 77, + "value": 65291, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 42, + "value": 65291, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 9154, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.12, + "value": -128.59, "compare": ">=" }, "finish__design__instance__area": { - "value": 3457, + "value": 45133, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 28, + "value": 32646, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 100, + "value": 1942, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -15.84, + "value": -31.2, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/rapidus2hp/ibex/config.mk b/flow/designs/rapidus2hp/ibex/config.mk new file mode 100644 index 0000000000..f29c39a686 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/config.mk @@ -0,0 +1,29 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NICKNAME = ibex +export DESIGN_NAME = ibex_core + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + +# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock +# resulting in positive slack +ifeq ($(FLOW_VARIANT),pos_slack) +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_pos_slack.sdc +else +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +endif + +export CORE_UTILIZATION = 45 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY_LB_ADDON = 0.20 + +export ENABLE_DPO = 0 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/ibex/constraint.sdc b/flow/designs/rapidus2hp/ibex/constraint.sdc new file mode 100644 index 0000000000..1465ae6069 --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint.sdc @@ -0,0 +1,15 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 790 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc new file mode 100644 index 0000000000..d714d428ae --- /dev/null +++ b/flow/designs/rapidus2hp/ibex/constraint_pos_slack.sdc @@ -0,0 +1,15 @@ +set clk_name core_clock +set clk_port_name clk_i +set clk_period 1468 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/tsmc65lp/swerv/rules-base.json b/flow/designs/rapidus2hp/ibex/rules-base.json similarity index 77% rename from flow/designs/tsmc65lp/swerv/rules-base.json rename to flow/designs/rapidus2hp/ibex/rules-base.json index 4c7a9073cb..cf8f00b0f4 100644 --- a/flow/designs/tsmc65lp/swerv/rules-base.json +++ b/flow/designs/rapidus2hp/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 558806.72, + "value": 1020.31, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 719763, + "value": 1198, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 92330, + "value": 19647, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,18 +20,14 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 8029, + "value": 1708, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 8029, + "value": 1708, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 5277758, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, @@ -40,11 +36,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 733991, + "value": 1247, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 4014, + "value": 854, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/rapidus2hp/jpeg/config.mk b/flow/designs/rapidus2hp/jpeg/config.mk new file mode 100644 index 0000000000..6996f9da0e --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/config.mk @@ -0,0 +1,16 @@ +export PLATFORM = rapidus2hp + +export DESIGN_NAME = jpeg_encoder +export DESIGN_NICKNAME = jpeg + +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) +export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc +export ABC_AREA = 1 + +export CORE_UTILIZATION = 35 +export CORE_ASPECT_RATIO = 1 +export CORE_MARGIN = 0.75 +export PLACE_DENSITY = 0.62 + +export TNS_END_PERCENT = 100 diff --git a/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc new file mode 100644 index 0000000000..9f0d6c6a9b --- /dev/null +++ b/flow/designs/rapidus2hp/jpeg/jpeg_encoder15_7nm.sdc @@ -0,0 +1,17 @@ +current_design jpeg_encoder + +set clk_name clk +set clk_port_name clk +set clk_period 425 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + $non_clock_inputs +set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \ + [all_outputs] diff --git a/flow/designs/tsmc65lp/bp_fe_top/rules-base.json b/flow/designs/rapidus2hp/jpeg/rules-base.json similarity index 77% rename from flow/designs/tsmc65lp/bp_fe_top/rules-base.json rename to flow/designs/rapidus2hp/jpeg/rules-base.json index 430a465222..4493bd4a0b 100644 --- a/flow/designs/tsmc65lp/bp_fe_top/rules-base.json +++ b/flow/designs/rapidus2hp/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 482012.17, + "value": 3297.12, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 556095, + "value": 3853, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 32013, + "value": 100478, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,18 +20,14 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2784, + "value": 8737, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2784, + "value": 8737, "compare": "<=" }, - "detailedroute__route__wirelength": { - "value": 2536931, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { + "globalroute__antenna_diodes_count": { "value": 0, "compare": "<=" }, @@ -40,11 +36,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 557652, + "value": 3959, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 1392, + "value": 4369, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/aes/autotuner.json b/flow/designs/sky130hd/aes/autotuner.json index e5fd0c8f03..23316d901a 100644 --- a/flow/designs/sky130hd/aes/autotuner.json +++ b/flow/designs/sky130hd/aes/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 5.0, + 3.5, 7.0 ], "step": 0 @@ -11,8 +11,8 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 10, - 20 + 20, + 50 ], "step": 1 }, @@ -24,18 +24,10 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -43,7 +35,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ @@ -88,13 +72,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl" } diff --git a/flow/designs/sky130hd/aes/config.mk b/flow/designs/sky130hd/aes/config.mk index a7fdf67708..85b0da73d6 100644 --- a/flow/designs/sky130hd/aes/config.mk +++ b/flow/designs/sky130hd/aes/config.mk @@ -18,3 +18,5 @@ export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.t export REMOVE_ABC_BUFFERS = 1 +export CTS_CLUSTER_SIZE = 20 +export CTS_CLUSTER_DIAMETER = 50 diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc index 7fa2a489d8..f0b3b99355 100644 --- a/flow/designs/sky130hd/aes/constraint.sdc +++ b/flow/designs/sky130hd/aes/constraint.sdc @@ -1,15 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.5 +set clk_period 4.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/aes/fastroute.tcl b/flow/designs/sky130hd/aes/fastroute.tcl index 66eb939e6f..80e4274ee2 100644 --- a/flow/designs/sky130hd/aes/fastroute.tcl +++ b/flow/designs/sky130hd/aes/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/aes/metadata-base-ok.json b/flow/designs/sky130hd/aes/metadata-base-ok.json deleted file mode 100644 index d707ce9033..0000000000 --- a/flow/designs/sky130hd/aes/metadata-base-ok.json +++ /dev/null @@ -1,332 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 4.5000" - ], - "cts__clock__skew__hold": 0.130923, - "cts__clock__skew__setup": 0.130923, - "cts__cpu__total": 21.38, - "cts__design__core__area": 434504, - "cts__design__die__area": 441873, - "cts__design__instance__area": 120275, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 120275, - "cts__design__instance__count": 18019, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 77, - "cts__design__instance__count__stdcell": 18019, - "cts__design__instance__displacement__max": 16.1, - "cts__design__instance__displacement__mean": 0.055, - "cts__design__instance__displacement__total": 996.969, - "cts__design__instance__utilization": 0.276811, - "cts__design__instance__utilization__stdcell": 0.276811, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 830012.0, - "cts__power__internal__total": 0.136061, - "cts__power__leakage__total": 3.89377e-08, - "cts__power__switching__total": 0.24599, - "cts__power__total": 0.38205, - "cts__route__wirelength__estimated": 428916, - "cts__runtime__total": "0:22.09", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.00768071, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0321478, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": -6.26166e-05, - "cts__timing__setup__ws": 3.06422e-05, - "design__io__hpwl": 121229111, - "design__violations": 0, - "detailedplace__cpu__total": 13.91, - "detailedplace__design__core__area": 434504, - "detailedplace__design__die__area": 441873, - "detailedplace__design__instance__area": 115900, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 115900, - "detailedplace__design__instance__count": 17749, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 17749, - "detailedplace__design__instance__displacement__max": 28.392, - "detailedplace__design__instance__displacement__mean": 1.593, - "detailedplace__design__instance__displacement__total": 28274.9, - "detailedplace__design__instance__utilization": 0.266741, - "detailedplace__design__instance__utilization__stdcell": 0.266741, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 266752.0, - "detailedplace__power__internal__total": 0.129908, - "detailedplace__power__leakage__total": 3.6676e-08, - "detailedplace__power__switching__total": 0.239785, - "detailedplace__power__total": 0.369694, - "detailedplace__route__wirelength__estimated": 435491, - "detailedplace__runtime__total": "0:14.21", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0066375, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0250957, - "detailedplace__timing__drv__setup_violation_count": 146, - "detailedplace__timing__setup__tns": -97.9736, - "detailedplace__timing__setup__ws": -1.52988, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 13, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 215, - "detailedroute__route__drc_errors__iter:10": 7, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 87, - "detailedroute__route__drc_errors__iter:3": 43, - "detailedroute__route__drc_errors__iter:4": 8, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__drc_errors__iter:6": 128, - "detailedroute__route__drc_errors__iter:7": 49, - "detailedroute__route__drc_errors__iter:8": 23, - "detailedroute__route__drc_errors__iter:9": 7, - "detailedroute__route__net": 12876, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 116138, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 116138, - "detailedroute__route__wirelength": 588965, - "detailedroute__route__wirelength__iter:1": 588972, - "detailedroute__route__wirelength__iter:10": 589076, - "detailedroute__route__wirelength__iter:11": 589095, - "detailedroute__route__wirelength__iter:2": 588947, - "detailedroute__route__wirelength__iter:3": 588937, - "detailedroute__route__wirelength__iter:4": 588966, - "detailedroute__route__wirelength__iter:5": 588965, - "detailedroute__route__wirelength__iter:6": 589201, - "detailedroute__route__wirelength__iter:7": 589140, - "detailedroute__route__wirelength__iter:8": 589094, - "detailedroute__route__wirelength__iter:9": 589075, - "finish__clock__skew__hold": 0.133959, - "finish__clock__skew__setup": 0.133959, - "finish__cpu__total": 27.9, - "finish__design__core__area": 434504, - "finish__design__die__area": 441873, - "finish__design__instance__area": 122364, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 122364, - "finish__design__instance__count": 18355, - "finish__design__instance__count__class:antenna_cell": 203, - "finish__design__instance__count__class:clock_buffer": 115, - "finish__design__instance__count__class:clock_inverter": 58, - "finish__design__instance__count__class:fill_cell": 45112, - "finish__design__instance__count__class:inverter": 108, - "finish__design__instance__count__class:multi_input_combinational_cell": 10894, - "finish__design__instance__count__class:sequential_cell": 562, - "finish__design__instance__count__class:tap_cell": 5734, - "finish__design__instance__count__class:timing_repair_buffer": 681, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 18355, - "finish__design__instance__utilization": 0.281617, - "finish__design__instance__utilization__stdcell": 0.281617, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79742, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00248563, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00893128, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00750337, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79107, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00750337, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 509128.0, - "finish__power__internal__total": 0.139919, - "finish__power__leakage__total": 3.98301e-08, - "finish__power__switching__total": 0.270881, - "finish__power__total": 0.4108, - "finish__runtime__total": "0:28.33", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 3, - "finish__timing__drv__max_cap_limit": -0.0177074, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 68, - "finish__timing__drv__max_slew_limit": -0.00870909, - "finish__timing__drv__setup_violation_count": 11, - "finish__timing__setup__tns": -0.891941, - "finish__timing__setup__ws": -0.184144, - "finish__timing__wns_percent_delay": -3.411344, - "finish_merge__cpu__total": 3.4, - "finish_merge__mem__peak": 556040.0, - "finish_merge__runtime__total": "0:03.81", - "floorplan__cpu__total": 5.29, - "floorplan__design__core__area": 434504, - "floorplan__design__die__area": 441873, - "floorplan__design__instance__area": 81369.3, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 81369.3, - "floorplan__design__instance__count": 11526, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 11526, - "floorplan__design__instance__utilization": 0.187269, - "floorplan__design__instance__utilization__stdcell": 0.187269, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 183292.0, - "floorplan__power__internal__total": 0.0890861, - "floorplan__power__leakage__total": 2.93769e-08, - "floorplan__power__switching__total": 0.102184, - "floorplan__power__total": 0.19127, - "floorplan__runtime__total": "0:05.40", - "floorplan__timing__setup__tns": -934.515, - "floorplan__timing__setup__ws": -8.6621, - "floorplan_io__cpu__total": 0.62, - "floorplan_io__mem__peak": 149952.0, - "floorplan_io__runtime__total": "0:00.71", - "floorplan_macro__cpu__total": 0.66, - "floorplan_macro__mem__peak": 149248.0, - "floorplan_macro__runtime__total": "0:00.73", - "floorplan_pdn__cpu__total": 1.27, - "floorplan_pdn__mem__peak": 172352.0, - "floorplan_pdn__runtime__total": "0:01.37", - "floorplan_tap__cpu__total": 0.65, - "floorplan_tap__mem__peak": 144368.0, - "floorplan_tap__runtime__total": "0:00.75", - "floorplan_tdms__cpu__total": 0.17, - "floorplan_tdms__mem__peak": 99912.0, - "floorplan_tdms__runtime__total": "0:00.24", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1015.75, - "globalplace__design__core__area": 434504, - "globalplace__design__die__area": 441873, - "globalplace__design__instance__area": 88543.7, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 88543.7, - "globalplace__design__instance__count": 17260, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 17260, - "globalplace__design__instance__utilization": 0.203781, - "globalplace__design__instance__utilization__stdcell": 0.203781, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 805952.0, - "globalplace__power__internal__total": 0.0937721, - "globalplace__power__leakage__total": 2.93769e-08, - "globalplace__power__switching__total": 0.205267, - "globalplace__power__total": 0.299039, - "globalplace__runtime__total": "1:23.10", - "globalplace__timing__setup__tns": -2455.7, - "globalplace__timing__setup__ws": -19.5528, - "globalplace_io__cpu__total": 0.79, - "globalplace_io__mem__peak": 157976.0, - "globalplace_io__runtime__total": "0:00.88", - "globalplace_skip_io__cpu__total": 317.94, - "globalplace_skip_io__mem__peak": 176536.0, - "globalplace_skip_io__runtime__total": "0:10.82", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 190, - "globalroute__clock__skew__hold": 0.130458, - "globalroute__clock__skew__setup": 0.130458, - "globalroute__cpu__total": 165.43, - "globalroute__design__core__area": 434504, - "globalroute__design__die__area": 441873, - "globalroute__design__instance__area": 122331, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 122331, - "globalroute__design__instance__count": 18342, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 102, - "globalroute__design__instance__count__stdcell": 18342, - "globalroute__design__instance__displacement__max": 18.4, - "globalroute__design__instance__displacement__mean": 0.068, - "globalroute__design__instance__displacement__total": 1246.76, - "globalroute__design__instance__utilization": 0.281542, - "globalroute__design__instance__utilization__stdcell": 0.281542, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1006452.0, - "globalroute__power__internal__total": 0.140191, - "globalroute__power__leakage__total": 3.983e-08, - "globalroute__power__switching__total": 0.284489, - "globalroute__power__total": 0.42468, - "globalroute__route__wirelength__estimated": 437730, - "globalroute__runtime__total": "0:32.93", - "globalroute__timing__clock__slack": -0.238, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.002932, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0107927, - "globalroute__timing__drv__setup_violation_count": 20, - "globalroute__timing__setup__tns": -1.82271, - "globalroute__timing__setup__ws": -0.238229, - "placeopt__cpu__total": 13.39, - "placeopt__design__core__area": 434504, - "placeopt__design__die__area": 441873, - "placeopt__design__instance__area": 115900, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 115900, - "placeopt__design__instance__count": 17749, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 17749, - "placeopt__design__instance__utilization": 0.266741, - "placeopt__design__instance__utilization__stdcell": 0.266741, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 689372.0, - "placeopt__power__internal__total": 0.129978, - "placeopt__power__leakage__total": 3.6676e-08, - "placeopt__power__switching__total": 0.245173, - "placeopt__power__total": 0.375151, - "placeopt__runtime__total": "0:14.04", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0007685, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.00884201, - "placeopt__timing__drv__setup_violation_count": 145, - "placeopt__timing__setup__tns": -97.2784, - "placeopt__timing__setup__ws": -1.53296, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-10-15 22:31", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16535-g199588e84", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "211ea2c6-aacd-442b-9a4e-1bc28f9eefe3", - "run__flow__variant": "base", - "synth__cpu__total": 55.08, - "synth__design__instance__area__stdcell": 87313.7408, - "synth__design__instance__count__stdcell": 12952.0, - "synth__mem__peak": 135008.0, - "synth__runtime__total": "0:55.31", - "total_time": "0:04:34.720000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/aes/rules-base.json b/flow/designs/sky130hd/aes/rules-base.json index 6f6cb542a4..2ed38b5088 100644 --- a/flow/designs/sky130hd/aes/rules-base.json +++ b/flow/designs/sky130hd/aes/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 100410.81, + "value": 99830.94, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 133285, + "value": 152029, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 20411, + "value": 20216, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1775, + "value": 1758, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1775, + "value": 1758, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 218, + "value": 148, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 677310, + "value": 783010, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 15, + "value": 48, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.31, + "value": -0.1, "compare": ">=" }, "finish__design__instance__area": { - "value": 140715, + "value": 157576, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 887, + "value": 879, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -12.11, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc index 6dcc28d927..d3a0d6df47 100644 --- a/flow/designs/sky130hd/chameleon/constraint.sdc +++ b/flow/designs/sky130hd/chameleon/constraint.sdc @@ -1,13 +1,13 @@ -set clk_name core_clock -set clk_port_name HCLK -set clk_period 7.0 +set clk_name core_clock +set clk_port_name HCLK +set clk_period 7.0 set clk_io_pct 0.1 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/chameleon/metadata-base-ok.json b/flow/designs/sky130hd/chameleon/metadata-base-ok.json deleted file mode 100644 index dcd69f6e39..0000000000 --- a/flow/designs/sky130hd/chameleon/metadata-base-ok.json +++ /dev/null @@ -1,444 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 7.0000" - ], - "cts__clock__skew__hold": 0.285719, - "cts__clock__skew__setup": 0.285719, - "cts__cpu__total": 9.19, - "cts__design__core__area": 10010000.0, - "cts__design__die__area": 10278400.0, - "cts__design__instance__area": 5685150.0, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 5574790.0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 110365, - "cts__design__instance__count": 61317, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 6, - "cts__design__instance__count__macros": 6, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 61311, - "cts__design__instance__displacement__max": 3.665, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 7.455, - "cts__design__instance__utilization": 0.56795, - "cts__design__instance__utilization__stdcell": 0.024884, - "cts__design__io": 145, - "cts__design__rows": 3596, - "cts__design__rows:unithd": 3596, - "cts__design__sites": 3499313, - "cts__design__sites:unithd": 3499313, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 1649220.0, - "cts__power__internal__total": 0.00565523, - "cts__power__leakage__total": 1.65434e-08, - "cts__power__switching__total": 0.00374154, - "cts__power__total": 0.00939678, - "cts__route__wirelength__estimated": 692588, - "cts__runtime__total": "0:10.39", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.135671, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0711395, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 1.08036, - "design__io__hpwl": 103884646, - "design__violations": 0, - "detailedplace__cpu__total": 7.74, - "detailedplace__design__core__area": 10010000.0, - "detailedplace__design__die__area": 10278400.0, - "detailedplace__design__instance__area": 5682560.0, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 5574790.0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 107771, - "detailedplace__design__instance__count": 61174, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 6, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 61168, - "detailedplace__design__instance__displacement__max": 210.113, - "detailedplace__design__instance__displacement__mean": 0.186, - "detailedplace__design__instance__displacement__total": 11421.4, - "detailedplace__design__instance__utilization": 0.567691, - "detailedplace__design__instance__utilization__stdcell": 0.0242992, - "detailedplace__design__io": 145, - "detailedplace__design__rows": 3596, - "detailedplace__design__rows:unithd": 3596, - "detailedplace__design__sites": 3499313, - "detailedplace__design__sites:unithd": 3499313, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1122112.0, - "detailedplace__power__internal__total": 0.00340682, - "detailedplace__power__leakage__total": 1.52754e-08, - "detailedplace__power__switching__total": 0.00114223, - "detailedplace__power__total": 0.00454906, - "detailedplace__route__wirelength__estimated": 692465, - "detailedplace__runtime__total": "0:08.85", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.135671, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0711523, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.744913, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 140, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 16, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 59, - "detailedroute__route__drc_errors__iter:1": 1, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:15": 1, - "detailedroute__route__drc_errors__iter:17": 2, - "detailedroute__route__drc_errors__iter:18": 1, - "detailedroute__route__drc_errors__iter:19": 1, - "detailedroute__route__drc_errors__iter:2": 0, - "detailedroute__route__drc_errors__iter:20": 1, - "detailedroute__route__drc_errors__iter:23": 1, - "detailedroute__route__drc_errors__iter:24": 1, - "detailedroute__route__drc_errors__iter:25": 1, - "detailedroute__route__drc_errors__iter:26": 1, - "detailedroute__route__drc_errors__iter:3": 4, - "detailedroute__route__drc_errors__iter:30": 1, - "detailedroute__route__drc_errors__iter:31": 1, - "detailedroute__route__drc_errors__iter:33": 1, - "detailedroute__route__drc_errors__iter:34": 1, - "detailedroute__route__drc_errors__iter:37": 1, - "detailedroute__route__drc_errors__iter:38": 1, - "detailedroute__route__drc_errors__iter:4": 1, - "detailedroute__route__drc_errors__iter:40": 1, - "detailedroute__route__drc_errors__iter:41": 1, - "detailedroute__route__drc_errors__iter:42": 1, - "detailedroute__route__drc_errors__iter:44": 1, - "detailedroute__route__drc_errors__iter:45": 1, - "detailedroute__route__drc_errors__iter:49": 1, - "detailedroute__route__drc_errors__iter:5": 1, - "detailedroute__route__drc_errors__iter:50": 1, - "detailedroute__route__drc_errors__iter:51": 0, - "detailedroute__route__drc_errors__iter:6": 16, - "detailedroute__route__drc_errors__iter:7": 16, - "detailedroute__route__drc_errors__iter:8": 16, - "detailedroute__route__drc_errors__iter:9": 13, - "detailedroute__route__net": 3454, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 27007, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 27007, - "detailedroute__route__wirelength": 734489, - "detailedroute__route__wirelength__iter:0": 734503, - "detailedroute__route__wirelength__iter:1": 734489, - "detailedroute__route__wirelength__iter:10": 734514, - "detailedroute__route__wirelength__iter:11": 734092, - "detailedroute__route__wirelength__iter:15": 734515, - "detailedroute__route__wirelength__iter:17": 734517, - "detailedroute__route__wirelength__iter:18": 734517, - "detailedroute__route__wirelength__iter:19": 734517, - "detailedroute__route__wirelength__iter:2": 734489, - "detailedroute__route__wirelength__iter:20": 734518, - "detailedroute__route__wirelength__iter:23": 734518, - "detailedroute__route__wirelength__iter:24": 734519, - "detailedroute__route__wirelength__iter:25": 734521, - "detailedroute__route__wirelength__iter:26": 734523, - "detailedroute__route__wirelength__iter:3": 734513, - "detailedroute__route__wirelength__iter:30": 734522, - "detailedroute__route__wirelength__iter:31": 734523, - "detailedroute__route__wirelength__iter:33": 734526, - "detailedroute__route__wirelength__iter:34": 734527, - "detailedroute__route__wirelength__iter:37": 734526, - "detailedroute__route__wirelength__iter:38": 734530, - "detailedroute__route__wirelength__iter:4": 734513, - "detailedroute__route__wirelength__iter:40": 734530, - "detailedroute__route__wirelength__iter:41": 734535, - "detailedroute__route__wirelength__iter:42": 734535, - "detailedroute__route__wirelength__iter:44": 734534, - "detailedroute__route__wirelength__iter:45": 734541, - "detailedroute__route__wirelength__iter:49": 734542, - "detailedroute__route__wirelength__iter:5": 734514, - "detailedroute__route__wirelength__iter:50": 734540, - "detailedroute__route__wirelength__iter:51": 734533, - "detailedroute__route__wirelength__iter:6": 734062, - "detailedroute__route__wirelength__iter:7": 734062, - "detailedroute__route__wirelength__iter:8": 734062, - "detailedroute__route__wirelength__iter:9": 734082, - "finish__clock__skew__hold": 0.296763, - "finish__clock__skew__setup": 0.296763, - "finish__cpu__total": 114.79, - "finish__design__core__area": 10010000.0, - "finish__design__die__area": 10278400.0, - "finish__design__instance__area": 5685860.0, - "finish__design__instance__area__class:antenna_cell": 663.136, - "finish__design__instance__area__class:buffer": 2094.51, - "finish__design__instance__area__class:clock_buffer": 2203.36, - "finish__design__instance__area__class:clock_inverter": 312.8, - "finish__design__instance__area__class:inverter": 1702.88, - "finish__design__instance__area__class:macro": 5574790.0, - "finish__design__instance__area__class:multi_input_combinational_cell": 15924, - "finish__design__instance__area__class:sequential_cell": 12844.8, - "finish__design__instance__area__class:timing_repair_buffer": 2538.68, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 5574790.0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 111065, - "finish__design__instance__count": 61584, - "finish__design__instance__count__class:antenna_cell": 265, - "finish__design__instance__count__class:buffer": 175, - "finish__design__instance__count__class:clock_buffer": 104, - "finish__design__instance__count__class:clock_inverter": 33, - "finish__design__instance__count__class:inverter": 242, - "finish__design__instance__count__class:macro": 6, - "finish__design__instance__count__class:multi_input_combinational_cell": 1853, - "finish__design__instance__count__class:sequential_cell": 525, - "finish__design__instance__count__class:timing_repair_buffer": 212, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 6, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 61578, - "finish__design__instance__utilization": 0.56802, - "finish__design__instance__utilization__stdcell": 0.025042, - "finish__design__io": 145, - "finish__design__rows": 3596, - "finish__design__rows:unithd": 3596, - "finish__design__sites": 3499313, - "finish__design__sites:unithd": 3499313, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.8, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 4.71497e-06, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.000400657, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.000849798, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.7996, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.000849798, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1925392.0, - "finish__power__internal__total": 0.0056548, - "finish__power__leakage__total": 1.65621e-08, - "finish__power__switching__total": 0.00339927, - "finish__power__total": 0.00905408, - "finish__runtime__total": "1:57.06", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 2, - "finish__timing__drv__max_cap_limit": -0.187477, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 5, - "finish__timing__drv__max_slew_limit": -0.132889, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.935869, - "finish__timing__wns_percent_delay": 25.293227, - "finish_merge__cpu__total": 24.35, - "finish_merge__mem__peak": 2163652.0, - "finish_merge__runtime__total": "0:26.07", - "floorplan__cpu__total": 1.5, - "floorplan__design__core__area": 10010000.0, - "floorplan__design__die__area": 10278400.0, - "floorplan__design__instance__area": 5598670.0, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 5574790.0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 23875.4, - "floorplan__design__instance__count": 2766, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 6, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 2760, - "floorplan__design__instance__utilization": 0.55931, - "floorplan__design__instance__utilization__stdcell": 0.00538321, - "floorplan__design__io": 145, - "floorplan__design__rows": 1278, - "floorplan__design__rows:unithd": 1278, - "floorplan__design__sites": 8000280, - "floorplan__design__sites:unithd": 8000280, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 10, - "floorplan__mem__peak": 144544.0, - "floorplan__power__internal__total": 0.00322336, - "floorplan__power__leakage__total": 1.15405e-08, - "floorplan__power__switching__total": 6.56166e-05, - "floorplan__power__total": 0.00328899, - "floorplan__runtime__total": "0:01.60", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 2.05254, - "floorplan_io__cpu__total": 0.62, - "floorplan_io__mem__peak": 134052.0, - "floorplan_io__runtime__total": "0:00.69", - "floorplan_macro__cpu__total": 0.61, - "floorplan_macro__mem__peak": 134308.0, - "floorplan_macro__runtime__total": "0:00.70", - "floorplan_pdn__cpu__total": 6.69, - "floorplan_pdn__mem__peak": 359672.0, - "floorplan_pdn__runtime__total": "0:07.00", - "floorplan_tap__cpu__total": 0.8, - "floorplan_tap__mem__peak": 155816.0, - "floorplan_tap__runtime__total": "0:00.90", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 785.84, - "globalplace__design__core__area": 10010000.0, - "globalplace__design__die__area": 10278400.0, - "globalplace__design__instance__area": 5671450.0, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 5574790.0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 96656.5, - "globalplace__design__instance__count": 60935, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 6, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 60929, - "globalplace__design__instance__utilization": 0.566581, - "globalplace__design__instance__utilization__stdcell": 0.0217932, - "globalplace__design__io": 145, - "globalplace__design__rows": 3596, - "globalplace__design__rows:unithd": 3596, - "globalplace__design__sites": 3499313, - "globalplace__design__sites:unithd": 3499313, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 965928.0, - "globalplace__power__internal__total": 0.00322816, - "globalplace__power__leakage__total": 1.15405e-08, - "globalplace__power__switching__total": 0.00101031, - "globalplace__power__total": 0.00423849, - "globalplace__runtime__total": "2:03.88", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 0.173202, - "globalplace_io__cpu__total": 1.01, - "globalplace_io__mem__peak": 213848.0, - "globalplace_io__runtime__total": "0:01.18", - "globalplace_skip_io__cpu__total": 325.03, - "globalplace_skip_io__mem__peak": 269316.0, - "globalplace_skip_io__runtime__total": "1:05.32", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 125, - "globalroute__clock__skew__hold": 0.282403, - "globalroute__clock__skew__setup": 0.282403, - "globalroute__cpu__total": 48.54, - "globalroute__design__core__area": 10010000.0, - "globalroute__design__die__area": 10278400.0, - "globalroute__design__instance__area": 5685510.0, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 5574790.0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 110715, - "globalroute__design__instance__count": 61444, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 1, - "globalroute__design__instance__count__macros": 6, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 61438, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.567985, - "globalroute__design__instance__utilization__stdcell": 0.024963, - "globalroute__design__io": 145, - "globalroute__design__rows": 3596, - "globalroute__design__rows:unithd": 3596, - "globalroute__design__sites": 3499313, - "globalroute__design__sites:unithd": 3499313, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1808772.0, - "globalroute__power__internal__total": 0.00565913, - "globalroute__power__leakage__total": 1.65611e-08, - "globalroute__power__switching__total": 0.00381404, - "globalroute__power__total": 0.00947319, - "globalroute__route__wirelength__estimated": 692661, - "globalroute__runtime__total": "0:22.37", - "globalroute__timing__clock__slack": 1.001, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0628117, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0790285, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 1.0015, - "placeopt__cpu__total": 5.2, - "placeopt__design__core__area": 10010000.0, - "placeopt__design__die__area": 10278400.0, - "placeopt__design__instance__area": 5682560.0, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 5574790.0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 107771, - "placeopt__design__instance__count": 61174, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 6, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 61168, - "placeopt__design__instance__utilization": 0.567691, - "placeopt__design__instance__utilization__stdcell": 0.0242992, - "placeopt__design__io": 145, - "placeopt__design__rows": 3596, - "placeopt__design__rows:unithd": 3596, - "placeopt__design__sites": 3499313, - "placeopt__design__sites:unithd": 3499313, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 35, - "placeopt__mem__peak": 699464.0, - "placeopt__power__internal__total": 0.00340706, - "placeopt__power__leakage__total": 1.52754e-08, - "placeopt__power__switching__total": 0.00115632, - "placeopt__power__total": 0.0045634, - "placeopt__runtime__total": "0:05.79", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.116151, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0719374, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 0.721987, - "run__flow__design": "chameleon", - "run__flow__generate_date": "2024-11-28 15:38", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17429-g24d1bf502", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "c4e5b09e-029c-4f46-9bb2-508a313398cf", - "run__flow__variant": "base", - "synth__cpu__total": 4.66, - "synth__design__instance__area__stdcell": 23875.3984, - "synth__design__instance__count__stdcell": 2766.0, - "synth__mem__peak": 55040.0, - "synth__runtime__total": "0:04.80", - "total_time": "0:06:36.600000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/chameleon/rules-base.json b/flow/designs/sky130hd/chameleon/rules-base.json index c60881643c..de98b6d05b 100644 --- a/flow/designs/sky130hd/chameleon/rules-base.json +++ b/flow/designs/sky130hd/chameleon/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 27456.71, + "value": 27373.26, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 6534944, + "value": 6530712, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 70314, + "value": 69712, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6114, + "value": 6062, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6114, + "value": 6062, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 144, + "value": 196, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 843488, + "value": 798366, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 161, + "value": 174, "compare": "<=" }, "finish__timing__setup__ws": { @@ -52,11 +52,11 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 6538739, + "value": 6534921, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3057, + "value": 3031, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk deleted file mode 100644 index 7a3fe7c767..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -export TOP_NICKNAME = chameleon_hier -export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} - -export DESIGN_NAME = DFFRAM_4K -export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} -export PLATFORM = sky130hd -export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl - -export VERILOG_FILES = \ - ${RTL_DIR}/IPs/DFFRAM_4K.v \ - ${RTL_DIR}/IPs/DFFRAMBB.v - - -export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc - -export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl - -export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 -export ABC_LOAD_IN_FF = 3 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 1925 2450 -export CORE_AREA = 0.46 2.720 1924.54 2447.28 -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met4 diff --git a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/constraint.sdc b/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/constraint.sdc deleted file mode 100644 index a3e059b860..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/constraint.sdc +++ /dev/null @@ -1,7 +0,0 @@ -create_clock [get_ports CLK] -name CLK -period 8 -waveform {0 4} -set_clock_latency -source 0 [get_clocks CLK] -set_clock_uncertainty 0.25 [get_clocks CLK] -set_clock_transition -min -fall 0.15 [get_clocks CLK] -set_clock_transition -min -rise 0.15 [get_clocks CLK] -set_clock_transition -max -fall 0.15 [get_clocks CLK] -set_clock_transition -max -rise 0.15 [get_clocks CLK] diff --git a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk deleted file mode 100644 index c63c632188..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -export TOP_NICKNAME = chameleon_hier -export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} - -export DESIGN_NAME = DMC_32x16HC -export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} -export PLATFORM = sky130hd -export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl - -export VERILOG_FILES = \ - ${RTL_DIR}/IPs/DFFRAMBB.v \ - ${RTL_DIR}/IPs/DMC_32x16HC.v - - -export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc - -export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl - -export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 -export ABC_LOAD_IN_FF = 3 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 600 900 -export CORE_AREA = 0.46 2.720 599.54 897.28 - -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met4 diff --git a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/constraint.sdc b/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/constraint.sdc deleted file mode 100644 index af61872fa0..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/constraint.sdc +++ /dev/null @@ -1,9 +0,0 @@ -create_clock [get_ports clk] -name clk -period 8 -waveform {0 4} -set_clock_latency -source 0 [get_clocks clk] -set_clock_uncertainty 0.25 [get_clocks clk] -set_clock_transition -min -fall 0.15 [get_clocks clk] -set_clock_transition -min -rise 0.15 [get_clocks clk] -set_clock_transition -max -fall 0.15 [get_clocks clk] -set_clock_transition -max -rise 0.15 [get_clocks clk] -set_output_delay -clock clk -max 4.0 [get_ports hit ] -set_output_delay -clock clk -max 4.0 [get_ports Do* ] diff --git a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk deleted file mode 100644 index 9ad85c0488..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -export TOP_NICKNAME = chameleon_hier -export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} - -export DESIGN_NAME = apb_sys_0 -export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} -export PLATFORM = sky130hd -export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl - -export VERILOG_FILES = \ - ${RTL_DIR}/AHB_sys_0/APB_sys_0/*\ - ${RTL_DIR}/IPs/*.v - - -export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc - -export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl - -export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 -export ABC_LOAD_IN_FF = 3 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 675 1050 -export CORE_AREA = 0.46 2.720 674.54 1047.28 - -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met4 diff --git a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/constraint.sdc b/flow/designs/sky130hd/chameleon_hier/apb_sys_0/constraint.sdc deleted file mode 100644 index 5525b9d25c..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/apb_sys_0/constraint.sdc +++ /dev/null @@ -1,7 +0,0 @@ -create_clock [get_ports HCLK] -name HCLK -period 8 -waveform {0 4} -set_clock_latency -source 0 [get_clocks HCLK] -set_clock_uncertainty 0.25 [get_clocks HCLK] -set_clock_transition -min -fall 0.15 [get_clocks HCLK] -set_clock_transition -min -rise 0.15 [get_clocks HCLK] -set_clock_transition -max -fall 0.15 [get_clocks HCLK] -set_clock_transition -max -rise 0.15 [get_clocks HCLK] diff --git a/flow/designs/sky130hd/chameleon_hier/config.mk b/flow/designs/sky130hd/chameleon_hier/config.mk deleted file mode 100644 index cd63d0fa5b..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/config.mk +++ /dev/null @@ -1,51 +0,0 @@ -export DESIGN_NICKNAME = chameleon_hier -export DESIGN_NAME = soc_core -export PLATFORM = sky130hd - -export SKY130_IO_VERSION ?= v0.2.0 -export OPENRAMS_DIR = ./platforms/sky130ram -export IO_DIR = ./platforms/sky130io - - - -export VERILOG_FILES_BLACKBOX = \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/ibex/*.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAM_4K.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/APB_sys_0/*.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DMC_32x16HC.v - -export BLOCKS = \ - DFFRAM_4K \ - DMC_32x16HC \ - apb_sys_0 \ - ibex_wrapper - - -export VERILOG_FILES = \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/acc/AHB_SPM.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/AHBSRAM.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/DFFRAMBB.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/GPIO.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_I2C.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_SPI.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/APB_UART.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/i2c_master.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/PWM32.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/RAM_3Kx32.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/QSPI_XIP_CTRL.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/spi_master.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/TIMER32.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/IPs/WDT32.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/AHB_sys_0/*.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/soc_core.v \ - $(VERILOG_FILES_BLACKBOX) - -export ENABLE_DPO = 0 -export MACRO_PLACE_CHANNEL = 160 160 -export MACRO_PLACE_HALO = 160 160 -export DIE_AREA = 0.0 0.0 6800 6800 -export CORE_AREA = 200 200 6600 6600 -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met5 diff --git a/flow/designs/sky130hd/chameleon_hier/constraint.sdc b/flow/designs/sky130hd/chameleon_hier/constraint.sdc deleted file mode 100644 index bbc60dd567..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/constraint.sdc +++ /dev/null @@ -1,11 +0,0 @@ - - -#set_max_transition 0.5 [current_design] -create_clock [get_ports HCLK] -name HCLK -period 8 -waveform {0 4} -set_clock_latency -source 0 [get_clocks HCLK] -set_clock_uncertainty 0.25 [get_clocks HCLK] -set_clock_transition -min -fall 0.15 [get_clocks HCLK] -set_clock_transition -min -rise 0.15 [get_clocks HCLK] -set_clock_transition -max -fall 0.15 [get_clocks HCLK] -set_clock_transition -max -rise 0.15 [get_clocks HCLK] -#set_max_fanout 100 [current_design] diff --git a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk deleted file mode 100644 index 5a8995057d..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk +++ /dev/null @@ -1,50 +0,0 @@ -export TOP_NICKNAME = chameleon_hier -export TOP_DIR = $(DESIGN_HOME)/$(PLATFORM)/${TOP_NICKNAME} - -export DESIGN_NAME = ibex_wrapper -export DESIGN_NICKNAME = ${TOP_NICKNAME}_${DESIGN_NAME} -export PLATFORM = sky130hd -export RTL_DIR = $(DESIGN_HOME)/src/${TOP_NICKNAME}/rtl - -export VERILOG_FILES = \ - ${RTL_DIR}/ibex/ibex_core.v\ - ${RTL_DIR}/ibex/ibex_pmp.v\ - ${RTL_DIR}/ibex/ibex_controller.v\ - ${RTL_DIR}/ibex/ibex_decoder.v\ - ${RTL_DIR}/ibex/ibex_id_stage.v\ - ${RTL_DIR}/ibex/ibex_wb_stage.v\ - ${RTL_DIR}/ibex/ibex_ex_block.v\ - ${RTL_DIR}/ibex/ibex_branch_predict.v\ - ${RTL_DIR}/ibex/ibex_icache.v\ - ${RTL_DIR}/ibex/ibex_compressed_decoder.v\ - ${RTL_DIR}/ibex/ibex_prefetch_buffer.v\ - ${RTL_DIR}/ibex/ibex_if_stage.v\ - ${RTL_DIR}/ibex/ibex_register_file_latch.v\ - ${RTL_DIR}/ibex/ibex_cs_registers.v\ - ${RTL_DIR}/ibex/ibex_csr.v\ - ${RTL_DIR}/ibex/ibex_register_file_ff.v\ - ${RTL_DIR}/ibex/ibex_load_store_unit.v\ - ${RTL_DIR}/ibex/ibex_alu.v\ - ${RTL_DIR}/ibex/ibex_counter.v\ - ${RTL_DIR}/ibex/ibex_dummy_instr.v\ - ${RTL_DIR}/ibex/ibex_multdiv_fast.v\ - ${RTL_DIR}/ibex/ibex_multdiv_slow.v\ - ${RTL_DIR}/ibex/prim_clock_gating.v\ - ${RTL_DIR}/ibex/ibex_fetch_fifo.v\ - ${RTL_DIR}/ibex/ibex_wrapper.v - -export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc - -export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl - -export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 -export ABC_LOAD_IN_FF = 3 - - - -# These values must be multiples of placement site -export DIE_AREA = 0 0 900 1200 -export CORE_AREA = 0.46 2.720 899.54 1197.28 - -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met4 diff --git a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/constraint.sdc b/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/constraint.sdc deleted file mode 100644 index a0c466bab3..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/ibex_wrapper/constraint.sdc +++ /dev/null @@ -1,7 +0,0 @@ -create_clock [get_ports HCLK] -name HCLK -period 10 -waveform {0 5} -set_clock_latency -source 0 [get_clocks HCLK] -set_clock_uncertainty 0.25 [get_clocks HCLK] -set_clock_transition -min -fall 0.15 [get_clocks HCLK] -set_clock_transition -min -rise 0.15 [get_clocks HCLK] -set_clock_transition -max -fall 0.15 [get_clocks HCLK] -set_clock_transition -max -rise 0.15 [get_clocks HCLK] diff --git a/flow/designs/sky130hd/chameleon_hier/metadata-base-ok.json b/flow/designs/sky130hd/chameleon_hier/metadata-base-ok.json deleted file mode 100644 index d0557f5f80..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/metadata-base-ok.json +++ /dev/null @@ -1,39 +0,0 @@ -{ - "constraints__clocks__count": 0, - "constraints__clocks__details": [], - "cts__design__instance__count__hold_buffer": "ERR", - "cts__design__instance__count__setup_buffer": "ERR", - "detailedplace__cpu__total": "ERR", - "detailedplace__design__violations": "ERR", - "detailedplace__mem__peak": "ERR", - "detailedplace__runtime__total": "ERR", - "finish__cpu__total": "ERR", - "finish__mem__peak": "ERR", - "finish__runtime__total": "ERR", - "finish__timing__drv__hold_violation_count": "ERR", - "finish__timing__drv__setup_violation_count": "ERR", - "finish__timing__wns_percent_delay": "ERR", - "floorplan__cpu__total": "ERR", - "floorplan__mem__peak": "ERR", - "floorplan__runtime__total": "ERR", - "globalroute__timing__clock__slack": "ERR", - "placeopt__cpu__total": "ERR", - "placeopt__mem__peak": "ERR", - "placeopt__runtime__total": "ERR", - "run__flow__design": "chameleon_hier", - "run__flow__generate_date": "2022-09-07 09:29", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-4871-g6fd2fefc4", - "run__flow__platform": "sky130hd", - "run__flow__platform_commit": "8aa9f2dd46129f2c0a670095c93e8c9477cb1ccc", - "run__flow__scripts_commit": "8aa9f2dd46129f2c0a670095c93e8c9477cb1ccc", - "run__flow__uuid": "94b13189-a5bf-4f53-b0a0-de252bcd47a2", - "run__flow__variant": "base", - "synth__cpu__total": 9.45, - "synth__design__instance__area__stdcell": 24429.68, - "synth__design__instance__count__stdcell": 1897.0, - "synth__mem__peak": 69768.0, - "synth__runtime__total": "0:10.31", - "total_time": "ERR" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/chameleon_hier/rules-base.json b/flow/designs/sky130hd/chameleon_hier/rules-base.json deleted file mode 100644 index a805f9e2c8..0000000000 --- a/flow/designs/sky130hd/chameleon_hier/rules-base.json +++ /dev/null @@ -1,86 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 28094, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 19404249, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 377083, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__timing__setup__ws": { - "value": -0.71, - "compare": ">=" - }, - "cts__timing__setup__ws__pre_repair": { - "value": -0.59, - "compare": ">=" - }, - "cts__timing__setup__ws__post_repair": { - "value": -0.7, - "compare": ">=" - }, - "cts__design__instance__count__setup_buffer": { - "value": 11, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 10, - "compare": "<=" - }, - "globalroute__timing__clock__slack": { - "value": 0.0, - "compare": ">=" - }, - "globalroute__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "detailedroute__route__wirelength": { - "value": 2645269, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 19407674, - "compare": "<=" - }, - "finish__timing__drv__max_slew_limit": { - "value": -2.35, - "compare": ">=" - }, - "finish__timing__drv__max_cap_limit": { - "value": -1.23, - "compare": ">=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 10, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 10, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/sky130hd/coyote_tc/config.mk b/flow/designs/sky130hd/coyote_tc/config.mk deleted file mode 100644 index c7ff070a28..0000000000 --- a/flow/designs/sky130hd/coyote_tc/config.mk +++ /dev/null @@ -1,67 +0,0 @@ -export DESIGN_NICKNAME = coyote_tc -export DESIGN_NAME = coyote_tc - -export PLATFORM = sky130hd -# Clone Skywater library: -# git clone git@github.com:google/skywater-pdk.git --recursive -# - -export SYNTH_HIERARCHICAL = 1 - -export SKY130_IO_VERSION ?= v0.2.0 -export OPENRAMS_DIR = ./platforms/sky130ram -export IO_DIR = ./platforms/sky130io - -export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ - $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ - $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ - $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ - $(IO_DIR)/verilog/sky130_io.blackbox.v - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc - -export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pad.tcl - -export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_TT_1p8V_25C.lib \ - $(IO_DIR)/lib/sky130_dummy_io.lib - -export ADDITIONAL_GDS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds - -export ADDITIONAL_LEFS = $(IO_DIR)/lef/sky130_ef_io__gpiov2_pad_wrapped.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_10um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_1um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_20um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_5um.lef \ - $(IO_DIR)/lef/sky130_ef_io__corner_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vccd_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vccd_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vdda_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vdda_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vddio_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vddio_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssa_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssa_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssd_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssd_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssio_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssio_lvc_pad.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef \ - -# These values must be multiples of placement site -export DIE_AREA = 0.0 0.0 5200 4609.14 -export CORE_AREA = 250 250 4950 4349.14 - -# Use custom power grid with core rings offset from the pads -export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.tcl - -# Point to the RC file -export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl diff --git a/flow/designs/sky130hd/coyote_tc/constraint.sdc b/flow/designs/sky130hd/coyote_tc/constraint.sdc deleted file mode 100644 index dba3db69a6..0000000000 --- a/flow/designs/sky130hd/coyote_tc/constraint.sdc +++ /dev/null @@ -1,471 +0,0 @@ - -set_max_fanout 10 [current_design] -set_max_transition 0.5 [current_design] -# set_dont_touch [get_ports *] -set_load -pin_load 3 [get_ports rocc_cmd_v_o] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_15}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_14}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_13}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_12}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_11}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_10}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_9}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_8}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_7}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_6}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_5}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_4}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_3}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_2}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_1}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_0}] -set_load -pin_load 3 [get_ports rocc_resp_ready_o] -set_load -pin_load 3 [get_ports rocc_mem_req_ready_o] -set_load -pin_load 3 [get_ports rocc_mem_resp_v_o] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_63}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_62}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_61}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_60}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_59}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_58}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_57}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_56}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_55}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_54}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_53}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_52}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_51}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_50}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_49}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_48}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_47}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_46}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_45}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_44}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_43}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_42}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_41}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_40}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_39}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_38}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_37}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_36}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_35}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_34}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_33}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_32}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_31}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_30}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_29}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_28}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_27}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_26}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_25}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_24}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_23}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_22}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_21}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_20}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_19}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_18}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_17}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_16}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_15}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_14}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_13}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_12}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_11}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_10}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_9}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_8}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_7}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_6}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_5}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_4}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_3}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_2}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_1}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_0}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_7}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_6}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_5}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_4}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_3}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_2}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_1}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_0}] -set_max_transition 0.069 [get_ports rocc_cmd_v_o] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_15}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_14}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_13}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_12}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_11}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_10}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_9}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_8}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_7}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_6}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_5}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_4}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_3}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_2}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_1}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_0}] -set_max_transition 0.069 [get_ports rocc_resp_ready_o] -set_max_transition 0.069 [get_ports rocc_mem_req_ready_o] -set_max_transition 0.069 [get_ports rocc_mem_resp_v_o] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_63}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_62}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_61}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_60}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_59}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_58}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_57}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_56}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_55}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_54}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_53}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_52}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_51}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_50}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_49}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_48}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_47}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_46}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_45}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_44}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_43}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_42}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_41}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_40}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_39}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_38}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_37}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_36}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_35}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_34}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_33}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_32}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_31}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_30}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_29}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_28}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_27}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_26}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_25}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_24}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_23}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_22}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_21}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_20}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_19}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_18}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_17}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_16}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_15}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_14}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_13}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_12}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_11}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_10}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_9}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_8}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_7}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_6}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_5}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_4}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_3}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_2}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_1}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_0}] -set_max_transition 0.069 [get_ports rocc_ctrl_o_s_] -set_max_transition 0.069 [get_ports rocc_ctrl_o_exception_] -set_max_transition 0.069 [get_ports rocc_ctrl_o_host_id_] -set_max_transition 0.069 [get_ports fsb_node_ready_o] -set_max_transition 0.069 [get_ports fsb_node_v_o] -set_max_transition 0.069 [get_ports {fsb_node_data_o_7}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_6}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_5}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_4}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_3}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_2}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_1}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_0}] -create_clock [get_pins u_clk_i.u_in/IN] -name core_clk -period 50 -waveform {0 2.5} -set_clock_latency -source 0 [get_clocks core_clk] -set_clock_uncertainty 0.03 [get_clocks core_clk] -set_clock_transition -min -fall 0.069 [get_clocks core_clk] -set_clock_transition -min -rise 0.069 [get_clocks core_clk] -set_clock_transition -max -fall 0.069 [get_clocks core_clk] -set_clock_transition -max -rise 0.069 [get_clocks core_clk] -set_false_path -to [list [get_ports rocc_ctrl_o_s_] [get_ports rocc_ctrl_o_exception_] [get_ports rocc_ctrl_o_host_id_]] -set_input_delay -clock core_clk 2.51 [get_ports rocc_cmd_ready_i] -set_input_delay -clock core_clk 2.51 [get_ports rocc_resp_v_i] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[7]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[6]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[5]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[4]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[3]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[2]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[1]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[0]}] -set_input_delay -clock core_clk 3.01 [get_ports rocc_mem_req_v_i] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay -clock core_clk 2.76 [get_ports rocc_ctrl_i_busy_] -set_input_delay -clock core_clk 2.76 [get_ports rocc_ctrl_i_interrupt_] -set_input_delay -clock core_clk 2.51 [get_ports fsb_node_v_i] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[7]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[6]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[5]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[4]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[3]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[2]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[1]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[0]}] -set_input_delay -clock core_clk 3.01 [get_ports fsb_node_yumi_i] -set_input_delay -clock core_clk 2.51 [get_ports reset_i] -set_input_delay -clock core_clk 2.51 [get_ports en_i] -set_output_delay -clock core_clk 2.51 [get_ports rocc_cmd_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_15}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_14}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_13}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_12}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_11}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_10}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_9}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_8}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_0}] -set_output_delay -clock core_clk 2.76 [get_ports rocc_mem_req_ready_o] -set_output_delay -clock core_clk 2.51 [get_ports rocc_mem_resp_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_63}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_62}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_61}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_60}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_59}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_58}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_57}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_56}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_55}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_54}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_53}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_52}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_51}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_50}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_49}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_48}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_47}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_46}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_45}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_44}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_43}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_42}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_41}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_40}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_39}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_38}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_37}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_36}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_35}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_34}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_33}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_32}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_31}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_30}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_29}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_28}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_27}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_26}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_25}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_24}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_23}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_22}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_21}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_20}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_19}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_18}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_17}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_16}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_15}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_14}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_13}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_12}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_11}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_10}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_9}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_8}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_0}] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_s_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_exception_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_host_id_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_resp_ready_o] -set_output_delay -clock core_clk 2.51 [get_ports fsb_node_ready_o] -set_output_delay -clock core_clk 3.01 [get_ports fsb_node_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_0}] -set_input_transition -max 0.069 [get_ports clk_i] -set_input_transition -min 0.069 [get_ports clk_i] -set_input_transition -max 0.069 [get_ports reset_i] -set_input_transition -min 0.069 [get_ports reset_i] -set_input_transition -max 0.069 [get_ports en_i] -set_input_transition -min 0.069 [get_ports en_i] -set_input_transition -max 0.069 [get_ports rocc_cmd_ready_i] -set_input_transition -min 0.069 [get_ports rocc_cmd_ready_i] -set_input_transition -max 0.069 [get_ports rocc_resp_v_i] -set_input_transition -min 0.069 [get_ports rocc_resp_v_i] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[7]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[7]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[6]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[6]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[5]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[5]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[4]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[4]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[3]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[3]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[2]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[2]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[1]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[1]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[0]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[0]}] -set_input_transition -max 0.069 [get_ports rocc_mem_req_v_i] -set_input_transition -min 0.069 [get_ports rocc_mem_req_v_i] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition -max 0.069 [get_ports rocc_ctrl_i_busy_] -set_input_transition -min 0.069 [get_ports rocc_ctrl_i_busy_] -set_input_transition -max 0.069 [get_ports rocc_ctrl_i_interrupt_] -set_input_transition -min 0.069 [get_ports rocc_ctrl_i_interrupt_] -set_input_transition -max 0.069 [get_ports fsb_node_v_i] -set_input_transition -min 0.069 [get_ports fsb_node_v_i] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[7]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[7]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[6]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[6]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[5]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[5]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[4]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[4]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[3]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[3]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[2]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[2]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[1]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[1]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[0]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[0]}] -set_input_transition -max 0.069 [get_ports fsb_node_yumi_i] -set_input_transition -min 0.069 [get_ports fsb_node_yumi_i] diff --git a/flow/designs/sky130hd/coyote_tc/ios.v b/flow/designs/sky130hd/coyote_tc/ios.v deleted file mode 100644 index 211a464d43..0000000000 --- a/flow/designs/sky130hd/coyote_tc/ios.v +++ /dev/null @@ -1,111 +0,0 @@ -`define ABUT .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b) - -`define ABUT_CONNECT .AMUXBUS_A(AMUXBUS_A), .AMUXBUS_B(AMUXBUS_B) - -`define ABUT_PORTS input AMUXBUS_A, input AMUXBUS_B - -`define TIE_CONNECT .HLD_H_N(tie_io), \ - .ENABLE_H(tie_io), \ - .ENABLE_INP_H(tie_lo_esd), \ - .ENABLE_VDDA_H(tie_io), \ - .ENABLE_VSWITCH_H(tie_lo), \ - .ENABLE_VDDIO(tie_io), \ - .INP_DIS(tie_lo), \ - .IB_MODE_SEL(tie_lo), \ - .VTRIP_SEL(tie_lo), \ - .SLOW(tie_lo), \ - .HLD_OVR(tie_lo), \ - .ANALOG_EN(tie_lo), \ - .ANALOG_SEL(tie_lo), \ - .ANALOG_POL(tie_lo), \ - .DM({tie_lo, tie_lo, tie_hi}), \ - .PAD_A_NOESD_H(), \ - .PAD_A_ESD_0_H(), \ - .PAD_A_ESD_1_H(), \ - .TIE_HI_ESD(tie_hi_esd), \ - .TIE_LO_ESD(tie_lo_esd) - -`define INPUT_PAD(PADX,SIGNAL) input_pad u_``PADX (.PAD(PADX), .y(SIGNAL), .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b)) -`define OUTPUT_PAD(PADX,SIGNAL) output_pad u_``PADX (.PAD(PADX), .a(SIGNAL), .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b)) - -module input_pad ( - input PAD, - output y, - `ABUT_PORTS -); - - supply1 VDDIO; - supply1 VDD; - supply0 VSS; - - wire tie_lo_esd; - wire tie_low = VSS; - wire tie_hi = VDD; - wire tie_io = VDDIO; - - sky130_ef_io__gpiov2_pad_wrapped u_in ( - .PAD(PAD), - .IN(y), - .IN_H(), - .OUT(tie_lo), - .OE_N(tie_lo), - `TIE_CONNECT, - `ABUT_CONNECT - ); -endmodule - -module output_pad ( - output PAD, - input a, - `ABUT_PORTS -); - - supply1 VDDIO; - supply1 VDD; - supply0 VSS; - - wire tie_lo_esd; - wire tie_low = VSS; - wire tie_hi = VDD; - wire tie_io = VDDIO; - - sky130_ef_io__gpiov2_pad_wrapped u_io ( - .PAD(PAD), - .IN(), - .IN_H(), - .OUT(a), - .OE_N(tie_hi), - `TIE_CONNECT, - `ABUT_CONNECT - ); -endmodule - -module input_bus #(parameter WIDTH = 1) ( - input [WIDTH-1:0] PAD, - output [WIDTH-1:0] y, - `ABUT_PORTS -); - input_pad u_io [WIDTH-1:0] (.PAD(PAD), .y(y), `ABUT_CONNECT); -endmodule - -module output_bus #(parameter WIDTH = 1) ( - output [WIDTH-1:0] PAD, - input [WIDTH-1:0] a, - `ABUT_PORTS -); - output_pad u_io [WIDTH-1:0] (.PAD(PAD), .a(a), `ABUT_CONNECT); -endmodule - -module core_pg_pads #(parameter NUM_PAIRS = 1) ( - `ABUT_PORTS -); - sky130_ef_io__vccd_hvc_pad vccd [NUM_PAIRS-1:0] (`ABUT_CONNECT); - sky130_ef_io__vssd_hvc_pad vssd [NUM_PAIRS-1:0] (`ABUT_CONNECT); -endmodule - -module io_pg_pads #(parameter NUM_PAIRS = 1) ( - `ABUT_PORTS -); - sky130_ef_io__vddio_hvc_pad vddio [NUM_PAIRS-1:0] (`ABUT_CONNECT); - sky130_ef_io__vssio_hvc_pad vssio [NUM_PAIRS-1:0] (`ABUT_CONNECT); -endmodule diff --git a/flow/designs/sky130hd/coyote_tc/macros.v b/flow/designs/sky130hd/coyote_tc/macros.v deleted file mode 100644 index de508fe0b7..0000000000 --- a/flow/designs/sky130hd/coyote_tc/macros.v +++ /dev/null @@ -1,123 +0,0 @@ -module mem_1rf_lg6_w80_bit (Q, CLK, CEN, WEN, A, D, EMA, EMAW, GWEN, RET1N); - - output [79:0] Q; - input CLK; - input CEN; - input [79:0] WEN; - input [5:0] A; - input [79:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input GWEN; - input RET1N; - - sky130_sram_1rw1r_80x64_8 - macro_mem - ( - .dout0(Q), - .clk0(CLK), - .csb0(CEN), - .wmask0(WEN), - .addr0(A), - .din0(D), - .web0(GWEN), - .addr1(6'b000000), - .csb1(1'b1), - .clk1(1'b0), - ); - -endmodule - -module mem_1rf_lg8_w128_all (Q, CLK, CEN, WEN, A, D, EMA, EMAW, RET1N); - - output [127:0] Q; - input CLK; - input CEN; - input WEN; - input [7:0] A; - input [127:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input RET1N; - - - sky130_sram_1rw1r_128x256_8 - macro_mem - ( - .dout0(Q), - .clk0(CLK), - .csb0(CEN), - .web0(WEN), - .wmask0(16'b1111111111111111), - .addr0(A), - .din0(D), - .clk1(1'b0), - .csb1(1'b1), - .addr1(8'b00000000) - ); - -endmodule - -module mem_2rf_lg6_w44_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [43:0] QA; - input CLKA; - input CENA; - input [5:0] AA; - input CLKB; - input CENB; - input [43:0] WENB; - input [5:0] AB; - input [43:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - sky130_sram_1rw1r_44x64_8 - macro_mem0 - ( - .clk1(CLKA), - .clk0(CLKB), - .addr1(AA), - .csb1(CENA), - .dout1(QA), - .addr0(AB), - .din0(DB), - .csb0(CENB), - .web0(1'b0), - .wmask0(WENB) - ); - -endmodule - -module mem_2rf_lg8_w64_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [63:0] QA; - input CLKA; - input CENA; - input [7:0] AA; - input CLKB; - input CENB; - input [63:0] WENB; - input [7:0] AB; - input [63:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - sky130_sram_1rw1r_64x256_8 - macro_mem0 - ( - .clk1(CLKA), - .clk0(CLKB), - .addr1(AA), - .csb1(CENA), - .dout1(QA), - .addr0(AB), - .din0(DB), - .csb0(CENB), - .wmask0(WENB), - .web0(1'b0) - ); - -endmodule diff --git a/flow/designs/sky130hd/coyote_tc/pad.tcl b/flow/designs/sky130hd/coyote_tc/pad.tcl deleted file mode 100644 index fdae26b1b5..0000000000 --- a/flow/designs/sky130hd/coyote_tc/pad.tcl +++ /dev/null @@ -1,254 +0,0 @@ -make_fake_io_site -name IO_SITE -width 1 -height 200 -make_fake_io_site -name IO_CSITE -width 200 -height 204 - -# Create IO Rows -make_io_sites -horizontal_site IO_SITE \ - -vertical_site IO_SITE \ - -corner_site IO_CSITE \ - -offset 0 \ - -rotation_horizontal R180 \ - -rotation_vertical R180 \ - -rotation_corner R180 - -######## Place Pads ######## -place_pad -row IO_SOUTH -location 240.0 {u_reset_i.u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 320.0 {u_vzz_0} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 400.0 {u_v18_0} -place_pad -row IO_SOUTH -location 560.0 {u_rocc_cmd_v_o.u_io} -place_pad -row IO_SOUTH -location 640.0 {u_rocc_cmd_data_o_0.u_io} -place_pad -row IO_SOUTH -location 720.0 {u_rocc_cmd_data_o_1.u_io} -place_pad -row IO_SOUTH -location 800.0 {u_rocc_cmd_data_o_2.u_io} -place_pad -row IO_SOUTH -location 880.0 {u_rocc_cmd_data_o_3.u_io} -place_pad -row IO_SOUTH -location 960.0 {u_rocc_cmd_data_o_4.u_io} -place_pad -row IO_SOUTH -location 1040.0 {u_rocc_cmd_data_o_5.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 1120.0 {u_vzz_1} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 1200.0 {u_v18_1} -place_pad -row IO_SOUTH -location 1280.0 {u_rocc_cmd_data_o_6.u_io} -place_pad -row IO_SOUTH -location 1360.0 {u_rocc_cmd_data_o_7.u_io} -place_pad -row IO_SOUTH -location 1440.0 {u_rocc_cmd_data_o_8.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_SOUTH -location 1520.0 {u_vss_0} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_SOUTH -location 1600.0 {u_vdd_0} -place_pad -row IO_SOUTH -location 1680.0 {u_rocc_cmd_data_o_9.u_io} -place_pad -row IO_SOUTH -location 1760.0 {u_rocc_cmd_data_o_10.u_io} -place_pad -row IO_SOUTH -location 1840.0 {u_rocc_cmd_data_o_11.u_io} -place_pad -row IO_SOUTH -location 1920.0 {u_rocc_cmd_data_o_12.u_io} -place_pad -row IO_SOUTH -location 2000.0 {u_rocc_cmd_data_o_13.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 2080.0 {u_vzz_2} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 2160.0 {u_v18_2} -place_pad -row IO_SOUTH -location 2240.0 {u_rocc_cmd_data_o_14.u_io} -place_pad -row IO_SOUTH -location 2320.0 {u_rocc_cmd_data_o_15.u_io} -place_pad -row IO_SOUTH -location 2400.0 {u_rocc_cmd_ready_i.u_in} -place_pad -row IO_SOUTH -location 2480.0 {u_rocc_resp_v_i.u_in} -place_pad -row IO_SOUTH -location 2560.0 {u_rocc_resp_data_i.u_io\[0\].u_in} -place_pad -row IO_SOUTH -location 2640.0 {u_rocc_resp_data_i.u_io\[1\].u_in} -place_pad -row IO_SOUTH -location 2720.0 {u_rocc_resp_data_i.u_io\[2\].u_in} -place_pad -row IO_SOUTH -location 2800.0 {u_rocc_resp_data_i.u_io\[3\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 2880.0 {u_vzz_3} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 2960.0 {u_v18_3} -place_pad -row IO_SOUTH -location 3040.0 {u_rocc_resp_data_i.u_io\[4\].u_in} -place_pad -row IO_SOUTH -location 3120.0 {u_rocc_resp_data_i.u_io\[5\].u_in} -place_pad -row IO_SOUTH -location 3200.0 {u_rocc_resp_data_i.u_io\[6\].u_in} -place_pad -row IO_SOUTH -location 3280.0 {u_rocc_resp_data_i.u_io\[7\].u_in} -place_pad -row IO_SOUTH -location 3360.0 {u_rocc_resp_ready_o.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_SOUTH -location 3440.0 {u_vss_1} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_SOUTH -location 3520.0 {u_vdd_1} -place_pad -row IO_SOUTH -location 3600.0 {u_rocc_mem_req_v_i.u_in} -place_pad -row IO_SOUTH -location 3680.0 {u_rocc_mem_req_data_i.u_io\[0\].u_in} -place_pad -row IO_SOUTH -location 3760.0 {u_rocc_mem_req_data_i.u_io\[1\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 3840.0 {u_vzz_4} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 3920.0 {u_v18_4} -place_pad -row IO_SOUTH -location 4000.0 {u_rocc_mem_req_data_i.u_io\[2\].u_in} -place_pad -row IO_SOUTH -location 4080.0 {u_rocc_mem_req_data_i.u_io\[3\].u_in} -place_pad -row IO_SOUTH -location 4160.0 {u_rocc_mem_req_data_i.u_io\[4\].u_in} -place_pad -row IO_SOUTH -location 4240.0 {u_rocc_mem_req_data_i.u_io\[5\].u_in} -place_pad -row IO_SOUTH -location 4320.0 {u_rocc_mem_req_data_i.u_io\[6\].u_in} -place_pad -row IO_SOUTH -location 4400.0 {u_rocc_mem_req_data_i.u_io\[7\].u_in} -place_pad -row IO_SOUTH -location 4480.0 {u_rocc_mem_req_data_i.u_io\[8\].u_in} -place_pad -row IO_SOUTH -location 4560.0 {u_rocc_mem_req_data_i.u_io\[9\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_SOUTH -location 4640.0 {u_vzz_5} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_SOUTH -location 4720.0 {u_v18_5} -place_pad -row IO_SOUTH -location 4800.0 {u_rocc_mem_req_data_i.u_io\[10\].u_in} -place_pad -row IO_SOUTH -location 4880.0 {u_rocc_mem_req_data_i.u_io\[11\].u_in} - -place_pad -row IO_EAST -location 234.0 {u_rocc_mem_req_data_i.u_io\[12\].u_in} -place_pad -row IO_EAST -location 314.0 {u_rocc_mem_req_data_i.u_io\[13\].u_in} -place_pad -row IO_EAST -location 394.0 {u_rocc_mem_req_data_i.u_io\[14\].u_in} -place_pad -row IO_EAST -location 474.0 {u_rocc_mem_req_data_i.u_io\[15\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_EAST -location 554.0 {u_vzz_6} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_EAST -location 634.0 {u_v18_6} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_EAST -location 714.0 {u_vss_2} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_EAST -location 794.0 {u_vdd_2} -place_pad -row IO_EAST -location 874.0 {u_rocc_mem_req_data_i.u_io\[16\].u_in} -place_pad -row IO_EAST -location 954.0 {u_rocc_mem_req_data_i.u_io\[17\].u_in} -place_pad -row IO_EAST -location 1034.0 {u_rocc_mem_req_data_i.u_io\[18\].u_in} -place_pad -row IO_EAST -location 1114.0 {u_rocc_mem_req_data_i.u_io\[19\].u_in} -place_pad -row IO_EAST -location 1194.0 {u_rocc_mem_req_data_i.u_io\[20\].u_in} -place_pad -row IO_EAST -location 1274.0 {u_rocc_mem_req_data_i.u_io\[21\].u_in} -place_pad -row IO_EAST -location 1354.0 {u_rocc_mem_req_data_i.u_io\[22\].u_in} -place_pad -row IO_EAST -location 1434.0 {u_rocc_mem_req_data_i.u_io\[23\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_EAST -location 1514.0 {u_vzz_7} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_EAST -location 1594.0 {u_v18_7} -place_pad -row IO_EAST -location 1674.0 {u_rocc_mem_req_data_i.u_io\[24\].u_in} -place_pad -row IO_EAST -location 1754.0 {u_rocc_mem_req_data_i.u_io\[25\].u_in} -place_pad -row IO_EAST -location 1834.0 {u_rocc_mem_req_data_i.u_io\[26\].u_in} -place_pad -row IO_EAST -location 1914.0 {u_rocc_mem_req_data_i.u_io\[27\].u_in} -place_pad -row IO_EAST -location 1994.0 {u_rocc_mem_req_data_i.u_io\[28\].u_in} -place_pad -row IO_EAST -location 2074.0 {u_rocc_mem_req_data_i.u_io\[29\].u_in} -place_pad -row IO_EAST -location 2154.0 {u_rocc_mem_req_data_i.u_io\[30\].u_in} -place_pad -row IO_EAST -location 2234.0 {u_rocc_mem_req_data_i.u_io\[31\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_EAST -location 2314.0 {u_vzz_8} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_EAST -location 2394.0 {u_v18_8} -place_pad -row IO_EAST -location 2474.0 {u_rocc_mem_req_ready_o.u_io} -place_pad -row IO_EAST -location 2554.0 {u_rocc_mem_resp_v_o.u_io} -place_pad -row IO_EAST -location 2634.0 {u_rocc_mem_resp_data_o_0.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_EAST -location 2714.0 {u_vss_3} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_EAST -location 2794.0 {u_vdd_3} -place_pad -row IO_EAST -location 2874.0 {u_rocc_mem_resp_data_o_1.u_io} -place_pad -row IO_EAST -location 2954.0 {u_rocc_mem_resp_data_o_2.u_io} -place_pad -row IO_EAST -location 3034.0 {u_rocc_mem_resp_data_o_3.u_io} -place_pad -row IO_EAST -location 3114.0 {u_rocc_mem_resp_data_o_4.u_io} -place_pad -row IO_EAST -location 3194.0 {u_rocc_mem_resp_data_o_5.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_EAST -location 3274.0 {u_vzz_9} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_EAST -location 3354.0 {u_v18_9} -place_pad -row IO_EAST -location 3434.0 {u_rocc_mem_resp_data_o_6.u_io} -place_pad -row IO_EAST -location 3514.0 {u_rocc_mem_resp_data_o_7.u_io} -place_pad -row IO_EAST -location 3594.0 {u_rocc_mem_resp_data_o_8.u_io} -place_pad -row IO_EAST -location 3674.0 {u_rocc_mem_resp_data_o_9.u_io} -place_pad -row IO_EAST -location 3754.0 {u_rocc_mem_resp_data_o_10.u_io} -place_pad -row IO_EAST -location 3834.0 {u_rocc_mem_resp_data_o_11.u_io} -place_pad -row IO_EAST -location 3914.0 {u_rocc_mem_resp_data_o_12.u_io} -place_pad -row IO_EAST -location 3994.0 {u_rocc_mem_resp_data_o_13.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_EAST -location 4074.0 {u_vzz_10} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_EAST -location 4154.0 {u_v18_10} -place_pad -row IO_EAST -location 4234.0 {u_rocc_mem_resp_data_o_14.u_io} -place_pad -row IO_EAST -location 4314.0 {u_rocc_mem_resp_data_o_15.u_io} - -place_pad -row IO_NORTH -location 4920.0 {u_rocc_mem_resp_data_o_16.u_io} -place_pad -row IO_NORTH -location 4840.0 {u_rocc_mem_resp_data_o_17.u_io} -place_pad -row IO_NORTH -location 4760.0 {u_rocc_mem_resp_data_o_18.u_io} -place_pad -row IO_NORTH -location 4680.0 {u_rocc_mem_resp_data_o_19.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_NORTH -location 4600.0 {u_vss_4} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_NORTH -location 4520.0 {u_vdd_4} -place_pad -row IO_NORTH -location 4440.0 {u_rocc_mem_resp_data_o_20.u_io} -place_pad -row IO_NORTH -location 4360.0 {u_rocc_mem_resp_data_o_21.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_NORTH -location 4280.0 {u_vzz_11} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_NORTH -location 4200.0 {u_v18_11} -place_pad -row IO_NORTH -location 4120.0 {u_rocc_mem_resp_data_o_22.u_io} -place_pad -row IO_NORTH -location 4040.0 {u_rocc_mem_resp_data_o_23.u_io} -place_pad -row IO_NORTH -location 3960.0 {u_rocc_mem_resp_data_o_24.u_io} -place_pad -row IO_NORTH -location 3880.0 {u_rocc_mem_resp_data_o_25.u_io} -place_pad -row IO_NORTH -location 3800.0 {u_rocc_mem_resp_data_o_26.u_io} -place_pad -row IO_NORTH -location 3720.0 {u_rocc_mem_resp_data_o_27.u_io} -place_pad -row IO_NORTH -location 3640.0 {u_rocc_mem_resp_data_o_28.u_io} -place_pad -row IO_NORTH -location 3560.0 {u_rocc_mem_resp_data_o_29.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_NORTH -location 3480.0 {u_vzz_12} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_NORTH -location 3400.0 {u_v18_12} -place_pad -row IO_NORTH -location 3320.0 {u_rocc_mem_resp_data_o_30.u_io} -place_pad -row IO_NORTH -location 3240.0 {u_rocc_mem_resp_data_o_31.u_io} -place_pad -row IO_NORTH -location 3160.0 {u_rocc_mem_resp_data_o_32.u_io} -place_pad -row IO_NORTH -location 3080.0 {u_rocc_mem_resp_data_o_33.u_io} -place_pad -row IO_NORTH -location 3000.0 {u_rocc_mem_resp_data_o_34.u_io} -place_pad -row IO_NORTH -location 2920.0 {u_rocc_mem_resp_data_o_35.u_io} -place_pad -row IO_NORTH -location 2840.0 {u_rocc_mem_resp_data_o_36.u_io} -place_pad -row IO_NORTH -location 2760.0 {u_rocc_mem_resp_data_o_37.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_NORTH -location 2680.0 {u_vzz_13} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_NORTH -location 2600.0 {u_v18_13} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_NORTH -location 2520.0 {u_vss_5} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_NORTH -location 2440.0 {u_vdd_5} -place_pad -row IO_NORTH -location 2360.0 {u_rocc_mem_resp_data_o_38.u_io} -place_pad -row IO_NORTH -location 2280.0 {u_rocc_mem_resp_data_o_39.u_io} -place_pad -row IO_NORTH -location 2200.0 {u_rocc_mem_resp_data_o_40.u_io} -place_pad -row IO_NORTH -location 2120.0 {u_rocc_mem_resp_data_o_41.u_io} -place_pad -row IO_NORTH -location 2040.0 {u_rocc_mem_resp_data_o_42.u_io} -place_pad -row IO_NORTH -location 1960.0 {u_rocc_mem_resp_data_o_43.u_io} -place_pad -row IO_NORTH -location 1880.0 {u_rocc_mem_resp_data_o_44.u_io} -place_pad -row IO_NORTH -location 1800.0 {u_rocc_mem_resp_data_o_45.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_NORTH -location 1720.0 {u_vzz_14} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_NORTH -location 1640.0 {u_v18_14} -place_pad -row IO_NORTH -location 1560.0 {u_rocc_mem_resp_data_o_46.u_io} -place_pad -row IO_NORTH -location 1480.0 {u_rocc_mem_resp_data_o_47.u_io} -place_pad -row IO_NORTH -location 1400.0 {u_rocc_mem_resp_data_o_48.u_io} -place_pad -row IO_NORTH -location 1320.0 {u_rocc_mem_resp_data_o_49.u_io} -place_pad -row IO_NORTH -location 1240.0 {u_rocc_mem_resp_data_o_50.u_io} -place_pad -row IO_NORTH -location 1160.0 {u_rocc_mem_resp_data_o_51.u_io} -place_pad -row IO_NORTH -location 1080.0 {u_rocc_mem_resp_data_o_52.u_io} -place_pad -row IO_NORTH -location 1000.0 {u_rocc_mem_resp_data_o_53.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_NORTH -location 920.0 {u_vzz_15} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_NORTH -location 840.0 {u_v18_15} -place_pad -row IO_NORTH -location 760.0 {u_rocc_mem_resp_data_o_54.u_io} -place_pad -row IO_NORTH -location 680.0 {u_rocc_mem_resp_data_o_55.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_NORTH -location 600.0 {u_vdd_6} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_NORTH -location 520.0 {u_vss_6} -place_pad -row IO_NORTH -location 440.0 {u_rocc_mem_resp_data_o_56.u_io} -place_pad -row IO_NORTH -location 360.0 {u_rocc_mem_resp_data_o_57.u_io} -place_pad -row IO_NORTH -location 280.0 {u_rocc_mem_resp_data_o_58.u_io} -place_pad -row IO_NORTH -location 200.0 {u_rocc_mem_resp_data_o_59.u_io} - -place_pad -row IO_WEST -location 4300.0 {u_rocc_mem_resp_data_o_60.u_io} -place_pad -row IO_WEST -location 4220.0 {u_rocc_mem_resp_data_o_61.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_WEST -location 4140.0 {u_vzz_16} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_WEST -location 4060.0 {u_v18_16} -place_pad -row IO_WEST -location 3980.0 {u_rocc_mem_resp_data_o_62.u_io} -place_pad -row IO_WEST -location 3900.0 {u_rocc_mem_resp_data_o_63.u_io} -place_pad -row IO_WEST -location 3820.0 {u_fsb_node_v_i.u_in} -place_pad -row IO_WEST -location 3740.0 {u_fsb_node_data_i.u_io\[0\].u_in} -place_pad -row IO_WEST -location 3660.0 {u_fsb_node_data_i.u_io\[1\].u_in} -place_pad -row IO_WEST -location 3580.0 {u_fsb_node_data_i.u_io\[2\].u_in} -place_pad -row IO_WEST -location 3500.0 {u_fsb_node_data_i.u_io\[3\].u_in} -place_pad -row IO_WEST -location 3420.0 {u_fsb_node_data_i.u_io\[4\].u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_WEST -location 3340.0 {u_vzz_17} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_WEST -location 3260.0 {u_v18_17} -place_pad -row IO_WEST -location 3180.0 {u_fsb_node_data_i.u_io\[5\].u_in} -place_pad -row IO_WEST -location 3100.0 {u_fsb_node_data_i.u_io\[6\].u_in} -place_pad -row IO_WEST -location 3020.0 {u_fsb_node_data_i.u_io\[7\].u_in} -place_pad -row IO_WEST -location 2940.0 {u_fsb_node_ready_o.u_io} -place_pad -row IO_WEST -location 2860.0 {u_fsb_node_v_o.u_io} -place_pad -row IO_WEST -location 2780.0 {u_fsb_node_data_o_0.u_io} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_WEST -location 2700.0 {u_vss_7} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_WEST -location 2620.0 {u_vdd_7} -place_pad -row IO_WEST -location 2540.0 {u_fsb_node_data_o_1.u_io} -place_pad -row IO_WEST -location 2460.0 {u_fsb_node_data_o_2.u_io} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_WEST -location 2380.0 {u_vzz_18} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_WEST -location 2300.0 {u_v18_18} -place_pad -row IO_WEST -location 2220.0 {u_fsb_node_data_o_3.u_io} -place_pad -row IO_WEST -location 2140.0 {u_fsb_node_data_o_4.u_io} -place_pad -row IO_WEST -location 2060.0 {u_fsb_node_data_o_5.u_io} -place_pad -row IO_WEST -location 1980.0 {u_fsb_node_data_o_6.u_io} -place_pad -row IO_WEST -location 1900.0 {u_fsb_node_data_o_7.u_io} -place_pad -row IO_WEST -location 1820.0 {u_fsb_node_yumi_i.u_in} -place_pad -row IO_WEST -location 1740.0 {u_rocc_ctrl_i_busy_.u_in} -place_pad -row IO_WEST -location 1660.0 {u_rocc_ctrl_i_interrupt_.u_in} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_WEST -location 1580.0 {u_vzz_19} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_WEST -location 1500.0 {u_v18_19} -place_pad -row IO_WEST -location 1420.0 {u_rocc_ctrl_o_s_.u_io} -place_pad -row IO_WEST -location 1340.0 {u_rocc_ctrl_o_exception_.u_io} -place_pad -row IO_WEST -location 1260.0 {u_rocc_ctrl_o_host_id_.u_io} -place_pad -master sky130_ef_io__vccd_hvc_pad -row IO_WEST -location 780.0 {u_vdd_8} -place_pad -master sky130_ef_io__vssd_hvc_pad -row IO_WEST -location 700.0 {u_vss_8} -place_pad -master sky130_ef_io__vssio_hvc_pad -row IO_WEST -location 620.0 {u_vzz_20} -place_pad -master sky130_ef_io__vddio_hvc_pad -row IO_WEST -location 540.0 {u_v18_20} -place_pad -row IO_WEST -location 220.0 {u_clk_i.u_in} - -# Place corners -place_corners sky130_ef_io__corner_pad - -# Place IO fill -set iofill {sky130_ef_io__com_bus_slice_20um - sky130_ef_io__com_bus_slice_10um - sky130_ef_io__com_bus_slice_5um - sky130_ef_io__com_bus_slice_1um} -place_io_fill -row IO_NORTH {*}$iofill -place_io_fill -row IO_SOUTH {*}$iofill -place_io_fill -row IO_WEST {*}$iofill -place_io_fill -row IO_EAST {*}$iofill - -# Connect ring signals -connect_by_abutment - -# The bond pads are integrated into the IO cell in sky130 so none -# are placed here. We do need to assign the terminals a location -# that aligns to the bond pad. -place_io_terminals *u_io/PAD -place_io_terminals *u_in/PAD - -remove_io_rows diff --git a/flow/designs/sky130hd/coyote_tc/pdn.tcl b/flow/designs/sky130hd/coyote_tc/pdn.tcl deleted file mode 100644 index eb2cfd91e9..0000000000 --- a/flow/designs/sky130hd/coyote_tc/pdn.tcl +++ /dev/null @@ -1,63 +0,0 @@ -#################################### -# global connections -#################################### -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {vdd} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND} - -add_global_connection -net {VDD} -inst_pattern {u_vdd_.*} -pin_pattern {VCCD} -power -add_global_connection -net {VSS} -inst_pattern {u_vss_.*} -pin_pattern {VSSD} -ground -global_connect -#################################### -# voltage domains -#################################### -set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} -#################################### -# standard cell grid -#################################### -define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_stripe -grid {grid} -layer {met1} -width {0.49} -pitch {5.44} -offset {0} -followpins -add_pdn_ring -grid {grid} -layers {met4 met5} -widths {3 3} -spacings {1.6 1.6} -pad_offsets {10 10} -connect_to_pads -starts_with POWER -add_pdn_stripe -grid {grid} -layer {met4} -width {0.96} -pitch {56.0} -offset {2} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {met5} -width {1.60} -pitch {56.0} -offset {2} -extend_to_core_ring -add_pdn_connect -grid {grid} -layers {met1 met4} -add_pdn_connect -grid {grid} -layers {met4 met5} -#################################### -# macro grids -#################################### -#################################### -# grid for: pads -#################################### -define_pdn_grid -name {pads} -voltage_domains {CORE} -macro \ - -halo {0.0 0.0 0.0 0.0} \ - -cells {sky130_ef_io__gpiov2_pad_wrapped - sky130_ef_io__com_bus_slice_10um - sky130_ef_io__com_bus_slice_1um - sky130_ef_io__com_bus_slice_20um - sky130_ef_io__com_bus_slice_5um - sky130_ef_io__corner_pad - sky130_ef_io__vccd_hvc_pad - sky130_ef_io__vccd_lvc_pad - sky130_ef_io__vdda_hvc_pad - sky130_ef_io__vdda_lvc_pad - sky130_ef_io__vddio_hvc_pad - sky130_ef_io__vddio_lvc_pad - sky130_ef_io__vssa_hvc_pad - sky130_ef_io__vssa_lvc_pad - sky130_ef_io__vssd_hvc_pad - sky130_ef_io__vssd_lvc_pad - sky130_ef_io__vssio_hvc_pad - sky130_ef_io__vssio_lvc_pad} \ - -grid_over_boundary -#################################### -# grid for: CORE_macro_grid_1 -#################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {0.0 0.0 0.0 0.0} -default -grid_over_boundary -add_pdn_stripe -grid {CORE_macro_grid_1} -layer {met4} -width {0.93} -pitch {20.0} -offset {2} -add_pdn_connect -grid {CORE_macro_grid_1} -layers {met3 met4} -add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} diff --git a/flow/designs/sky130hd/gcd/autotuner.json b/flow/designs/sky130hd/gcd/autotuner.json index 16a0c04fc9..a39fb2b87c 100644 --- a/flow/designs/sky130hd/gcd/autotuner.json +++ b/flow/designs/sky130hd/gcd/autotuner.json @@ -1,19 +1,18 @@ - { "_SDC_FILE_PATH": "constraint.sdc", "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 7.0, - 12.0 + 0.8, + 5.0 ], "step": 0 }, "CORE_UTILIZATION": { "type": "int", "minmax": [ - 5, - 45 + 20, + 50 ], "step": 1 }, @@ -28,15 +27,15 @@ "CORE_MARGIN": { "type": "int", "minmax": [ - 2, - 2 + 1, + 3 ], - "step": 0 + "step": 1 }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -44,7 +43,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -61,7 +60,7 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, @@ -81,13 +80,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl" } diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc index f7fc57401a..fadfedd028 100644 --- a/flow/designs/sky130hd/gcd/constraint.sdc +++ b/flow/designs/sky130hd/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2.5 +set clk_period 1.1 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/gcd/metadata-base-ok.json b/flow/designs/sky130hd/gcd/metadata-base-ok.json deleted file mode 100644 index 47c8720ee4..0000000000 --- a/flow/designs/sky130hd/gcd/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2.5000" - ], - "cts__clock__skew__hold": 0.0018465, - "cts__clock__skew__setup": 0.0018465, - "cts__cpu__total": 75.67, - "cts__design__core__area": 6944.16, - "cts__design__die__area": 7729.93, - "cts__design__instance__area": 4399.22, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 4399.22, - "cts__design__instance__count": 603, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 54, - "cts__design__instance__count__stdcell": 603, - "cts__design__instance__displacement__max": 27.14, - "cts__design__instance__displacement__mean": 2.577, - "cts__design__instance__displacement__total": 1554.49, - "cts__design__instance__utilization": 0.633514, - "cts__design__instance__utilization__stdcell": 0.633514, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 823260.0, - "cts__power__internal__total": 0.00171189, - "cts__power__leakage__total": 1.9303e-09, - "cts__power__switching__total": 0.00114852, - "cts__power__total": 0.00286041, - "cts__route__wirelength__estimated": 8762.78, - "cts__runtime__total": "0:22.96", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.766235, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.719174, - "cts__timing__drv__setup_violation_count": 24, - "cts__timing__setup__tns": -7.62674, - "cts__timing__setup__ws": -0.7025, - "design__io__hpwl": 1216100, - "design__violations": 0, - "detailedplace__cpu__total": 0.74, - "detailedplace__design__core__area": 6944.16, - "detailedplace__design__die__area": 7729.93, - "detailedplace__design__instance__area": 3484.59, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 3484.59, - "detailedplace__design__instance__count": 540, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 540, - "detailedplace__design__instance__displacement__max": 8.027, - "detailedplace__design__instance__displacement__mean": 1.897, - "detailedplace__design__instance__displacement__total": 1024.51, - "detailedplace__design__instance__utilization": 0.501802, - "detailedplace__design__instance__utilization__stdcell": 0.501802, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 131860.0, - "detailedplace__power__internal__total": 0.0012072, - "detailedplace__power__leakage__total": 1.4158e-09, - "detailedplace__power__switching__total": 0.000768836, - "detailedplace__power__total": 0.00197604, - "detailedplace__route__wirelength__estimated": 6913.14, - "detailedplace__runtime__total": "0:00.81", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.828769, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.709453, - "detailedplace__timing__drv__setup_violation_count": 31, - "detailedplace__timing__setup__tns": -6.0452, - "detailedplace__timing__setup__ws": -0.478817, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 319, - "detailedroute__route__drc_errors__iter:2": 207, - "detailedroute__route__drc_errors__iter:3": 342, - "detailedroute__route__drc_errors__iter:4": 84, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 546, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3659, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3659, - "detailedroute__route__wirelength": 12293, - "detailedroute__route__wirelength__iter:1": 12311, - "detailedroute__route__wirelength__iter:2": 12336, - "detailedroute__route__wirelength__iter:3": 12328, - "detailedroute__route__wirelength__iter:4": 12294, - "detailedroute__route__wirelength__iter:5": 12294, - "detailedroute__route__wirelength__iter:6": 12293, - "finish__clock__skew__hold": 0.00909797, - "finish__clock__skew__setup": 0.00909797, - "finish__cpu__total": 2.04, - "finish__design__core__area": 6944.16, - "finish__design__die__area": 7729.93, - "finish__design__instance__area": 4570.63, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 4570.63, - "finish__design__instance__count": 609, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 609, - "finish__design__instance__utilization": 0.658198, - "finish__design__instance__utilization__stdcell": 0.658198, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79979, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000136618, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.000395085, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00034658, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.7996, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00034658, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 200268.0, - "finish__power__internal__total": 0.0017825, - "finish__power__leakage__total": 2.00114e-09, - "finish__power__switching__total": 0.00134929, - "finish__power__total": 0.00313179, - "finish__runtime__total": "0:02.21", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.669325, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.632417, - "finish__timing__drv__setup_violation_count": 38, - "finish__timing__setup__tns": -9.9381, - "finish__timing__setup__ws": -0.842953, - "finish__timing__wns_percent_delay": -29.651776, - "finish_merge__cpu__total": 1.77, - "finish_merge__mem__peak": 399308.0, - "finish_merge__runtime__total": "0:01.94", - "floorplan__cpu__total": 0.94, - "floorplan__design__core__area": 6944.16, - "floorplan__design__die__area": 7729.93, - "floorplan__design__instance__area": 3004.13, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 3004.13, - "floorplan__design__instance__count": 391, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 391, - "floorplan__design__instance__utilization": 0.432613, - "floorplan__design__instance__utilization__stdcell": 0.432613, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 47, - "floorplan__mem__peak": 132864.0, - "floorplan__power__internal__total": 0.00110851, - "floorplan__power__leakage__total": 1.28065e-09, - "floorplan__power__switching__total": 0.000478548, - "floorplan__power__total": 0.00158706, - "floorplan__runtime__total": "0:00.97", - "floorplan__timing__setup__tns": -0.0409397, - "floorplan__timing__setup__ws": -0.0243929, - "floorplan_io__cpu__total": 0.45, - "floorplan_io__mem__peak": 127736.0, - "floorplan_io__runtime__total": "0:00.50", - "floorplan_macro__cpu__total": 0.44, - "floorplan_macro__mem__peak": 127740.0, - "floorplan_macro__runtime__total": "0:00.50", - "floorplan_pdn__cpu__total": 0.41, - "floorplan_pdn__mem__peak": 129816.0, - "floorplan_pdn__runtime__total": "0:00.53", - "floorplan_tap__cpu__total": 0.45, - "floorplan_tap__mem__peak": 127312.0, - "floorplan_tap__runtime__total": "0:00.51", - "floorplan_tdms__cpu__total": 0.46, - "floorplan_tdms__mem__peak": 127744.0, - "floorplan_tdms__runtime__total": "0:00.51", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 11.46, - "globalplace__design__core__area": 6944.16, - "globalplace__design__die__area": 7729.93, - "globalplace__design__instance__area": 3124.25, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 3124.25, - "globalplace__design__instance__count": 487, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 487, - "globalplace__design__instance__utilization": 0.44991, - "globalplace__design__instance__utilization__stdcell": 0.44991, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 775456.0, - "globalplace__power__internal__total": 0.00111102, - "globalplace__power__leakage__total": 1.28065e-09, - "globalplace__power__switching__total": 0.000696245, - "globalplace__power__total": 0.00180727, - "globalplace__runtime__total": "0:02.77", - "globalplace__timing__setup__tns": -10.8519, - "globalplace__timing__setup__ws": -0.511361, - "globalplace_io__cpu__total": 0.43, - "globalplace_io__mem__peak": 128528.0, - "globalplace_io__runtime__total": "0:00.51", - "globalplace_skip_io__cpu__total": 6.2, - "globalplace_skip_io__mem__peak": 128556.0, - "globalplace_skip_io__runtime__total": "0:00.67", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.00774617, - "globalroute__clock__skew__setup": 0.00774617, - "globalroute__cpu__total": 9.71, - "globalroute__design__core__area": 6944.16, - "globalroute__design__die__area": 7729.93, - "globalroute__design__instance__area": 4570.63, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 4570.63, - "globalroute__design__instance__count": 609, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 11, - "globalroute__design__instance__count__stdcell": 609, - "globalroute__design__instance__displacement__max": 24.48, - "globalroute__design__instance__displacement__mean": 1.765, - "globalroute__design__instance__displacement__total": 1075.12, - "globalroute__design__instance__utilization": 0.658198, - "globalroute__design__instance__utilization__stdcell": 0.658198, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 790844.0, - "globalroute__power__internal__total": 0.00178511, - "globalroute__power__leakage__total": 2.00114e-09, - "globalroute__power__switching__total": 0.00150628, - "globalroute__power__total": 0.0032914, - "globalroute__route__wirelength__estimated": 10194.5, - "globalroute__runtime__total": "0:07.67", - "globalroute__timing__clock__slack": -0.928, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.689006, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.650171, - "globalroute__timing__drv__setup_violation_count": 43, - "globalroute__timing__setup__tns": -13.4763, - "globalroute__timing__setup__ws": -0.927829, - "placeopt__cpu__total": 1.07, - "placeopt__design__core__area": 6944.16, - "placeopt__design__die__area": 7729.93, - "placeopt__design__instance__area": 3484.59, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 3484.59, - "placeopt__design__instance__count": 540, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 540, - "placeopt__design__instance__utilization": 0.501802, - "placeopt__design__instance__utilization__stdcell": 0.501802, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 726788.0, - "placeopt__power__internal__total": 0.00120718, - "placeopt__power__leakage__total": 1.4158e-09, - "placeopt__power__switching__total": 0.000761904, - "placeopt__power__total": 0.00196909, - "placeopt__runtime__total": "0:01.63", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.86293, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.706801, - "placeopt__timing__drv__setup_violation_count": 31, - "placeopt__timing__setup__tns": -4.70054, - "placeopt__timing__setup__ws": -0.454219, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-09-27 17:45", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16089-gd06039e7d", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "361a4900-043b-4c97-a62e-5a650153536a", - "run__flow__variant": "base", - "synth__cpu__total": 1.87, - "synth__design__instance__area__stdcell": 2952.832, - "synth__design__instance__count__stdcell": 391.0, - "synth__mem__peak": 46592.0, - "synth__runtime__total": "0:01.97", - "total_time": "0:00:46.660000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index 29de86a2fd..e3df54dee7 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 3395.76, + "value": 3027.41, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 4007, + "value": 4606, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 621, + "value": 581, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 59, + "value": 62, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 54, + "value": 42, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 14137, + "value": 13998, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.96, + "value": -1.76, "compare": ">=" }, "finish__design__instance__area": { - "value": 5256, + "value": 6219, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 40, + "value": 86, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -45.58, + "value": -79.41, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel new file mode 100644 index 0000000000..08f7adc3e6 --- /dev/null +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -0,0 +1,23 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_flow") + +orfs_flow( + name = "ibex", + arguments = { + "ADDER_MAP_FILE": "", + "CORE_UTILIZATION": "45", + "PLACE_DENSITY_LB_ADDON": "0.25", + "TNS_END_PERCENT": "100", + "REMOVE_ABC_BUFFERS": "1", + "SYNTH_HDL_FRONTEND": "slang", + "VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl", + "CTS_CLUSTER_SIZE": "20", + "CTS_CLUSTER_DIAMETER": "50", + }, + pdk = "@docker_orfs//:sky130hd", + sources = { + "SDC_FILE": [":constraint.sdc"], + "FASTROUTE_TCL": ["fastroute.tcl"], + }, + top = "ibex_core", + verilog_files = ["//flow/designs/src/ibex_sv:verilog"], +) diff --git a/flow/designs/sky130hd/ibex/autotuner.json b/flow/designs/sky130hd/ibex/autotuner.json index f3279ec671..a68e1f0f24 100644 --- a/flow/designs/sky130hd/ibex/autotuner.json +++ b/flow/designs/sky130hd/ibex/autotuner.json @@ -3,7 +3,7 @@ "_SDC_CLK_PERIOD": { "type": "float", "minmax": [ - 14.0, + 9.0, 16.0 ], "step": 0 @@ -11,7 +11,7 @@ "CORE_UTILIZATION": { "type": "int", "minmax": [ - 5, + 20, 50 ], "step": 1 @@ -24,18 +24,10 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -43,7 +35,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ @@ -88,13 +72,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl" } diff --git a/flow/designs/sky130hd/ibex/config.mk b/flow/designs/sky130hd/ibex/config.mk index 1173a088a0..5f03b5aae7 100644 --- a/flow/designs/sky130hd/ibex/config.mk +++ b/flow/designs/sky130hd/ibex/config.mk @@ -2,43 +2,13 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hd -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc @@ -46,9 +16,12 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint. export ADDER_MAP_FILE := export CORE_UTILIZATION = 45 -export PLACE_DENSITY_LB_ADDON = 0.2 +export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 + +export CTS_CLUSTER_SIZE = 20 +export CTS_CLUSTER_DIAMETER = 50 diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc index a4faf836eb..fed426995f 100644 --- a/flow/designs/sky130hd/ibex/constraint.sdc +++ b/flow/designs/sky130hd/ibex/constraint.sdc @@ -1,6 +1,6 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i set clk_period 10.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/ibex/constraint_doe.sdc b/flow/designs/sky130hd/ibex/constraint_doe.sdc index e169d10114..31ddde31d7 100644 --- a/flow/designs/sky130hd/ibex/constraint_doe.sdc +++ b/flow/designs/sky130hd/ibex/constraint_doe.sdc @@ -1,5 +1,5 @@ set uncertainty 1.0 -set io_delay 7.0 +set io_delay 7.0 set clock_port clk_i @@ -11,5 +11,5 @@ create_clock -name core_clock -period 15.0 -waveform {0.0000 7.5} [get_ports {cl set_clock_uncertainty $uncertainty [all_clocks] # -set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] +set_input_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks core_clock] -add_delay -max $io_delay [all_outputs] diff --git a/flow/designs/sky130hd/ibex/fastroute.tcl b/flow/designs/sky130hd/ibex/fastroute.tcl index 80a2ca181e..76f9321967 100644 --- a/flow/designs/sky130hd/ibex/fastroute.tcl +++ b/flow/designs/sky130hd/ibex/fastroute.tcl @@ -1,5 +1,4 @@ -set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.3 +set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2 set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/ibex/metadata-base-ok.json b/flow/designs/sky130hd/ibex/metadata-base-ok.json deleted file mode 100644 index 8eab85dea3..0000000000 --- a/flow/designs/sky130hd/ibex/metadata-base-ok.json +++ /dev/null @@ -1,398 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 10.0000" - ], - "cts__clock__skew__hold": 1.71158, - "cts__clock__skew__setup": 1.71181, - "cts__cpu__total": 308.2, - "cts__design__core__area": 300783, - "cts__design__die__area": 305400, - "cts__design__instance__area": 175433, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 175433, - "cts__design__instance__count": 19772, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 367, - "cts__design__instance__count__stdcell": 19772, - "cts__design__instance__displacement__max": 16.56, - "cts__design__instance__displacement__mean": 0.229, - "cts__design__instance__displacement__total": 4546.05, - "cts__design__instance__utilization": 0.583254, - "cts__design__instance__utilization__stdcell": 0.583254, - "cts__design__io": 264, - "cts__design__rows": 201, - "cts__design__rows:unithd": 201, - "cts__design__sites": 240396, - "cts__design__sites:unithd": 240396, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 832048.0, - "cts__power__internal__total": 0.0572655, - "cts__power__leakage__total": 7.13177e-08, - "cts__power__switching__total": 0.0725254, - "cts__power__total": 0.129791, - "cts__route__wirelength__estimated": 513241, - "cts__runtime__total": "5:08.95", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.011042, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0237972, - "cts__timing__drv__setup_violation_count": 39, - "cts__timing__setup__tns": -6.87877, - "cts__timing__setup__ws": -0.467518, - "design__io__hpwl": 40393807, - "design__violations": 0, - "detailedplace__cpu__total": 23.14, - "detailedplace__design__core__area": 300783, - "detailedplace__design__die__area": 305400, - "detailedplace__design__instance__area": 163340, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 163340, - "detailedplace__design__instance__count": 18953, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 18953, - "detailedplace__design__instance__displacement__max": 16.16, - "detailedplace__design__instance__displacement__mean": 1.857, - "detailedplace__design__instance__displacement__total": 35211, - "detailedplace__design__instance__utilization": 0.54305, - "detailedplace__design__instance__utilization__stdcell": 0.54305, - "detailedplace__design__io": 264, - "detailedplace__design__rows": 201, - "detailedplace__design__rows:unithd": 201, - "detailedplace__design__sites": 240396, - "detailedplace__design__sites:unithd": 240396, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 260428.0, - "detailedplace__power__internal__total": 0.0504562, - "detailedplace__power__leakage__total": 6.46777e-08, - "detailedplace__power__switching__total": 0.0676788, - "detailedplace__power__total": 0.118135, - "detailedplace__route__wirelength__estimated": 466840, - "detailedplace__runtime__total": "0:23.29", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 1, - "detailedplace__timing__drv__max_cap_limit": -0.0330176, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 9, - "detailedplace__timing__drv__max_slew_limit": -0.0119607, - "detailedplace__timing__drv__setup_violation_count": 979, - "detailedplace__timing__setup__tns": -1103.77, - "detailedplace__timing__setup__ws": -2.13483, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 43, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 30, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 1910, - "detailedroute__route__drc_errors__iter:1": 1151, - "detailedroute__route__drc_errors__iter:10": 9, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:12": 11, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:2": 996, - "detailedroute__route__drc_errors__iter:3": 401, - "detailedroute__route__drc_errors__iter:4": 64, - "detailedroute__route__drc_errors__iter:5": 58, - "detailedroute__route__drc_errors__iter:6": 56, - "detailedroute__route__drc_errors__iter:7": 48, - "detailedroute__route__drc_errors__iter:8": 41, - "detailedroute__route__drc_errors__iter:9": 41, - "detailedroute__route__net": 15990, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 142171, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 142171, - "detailedroute__route__wirelength": 708452, - "detailedroute__route__wirelength__iter:0": 708661, - "detailedroute__route__wirelength__iter:1": 708395, - "detailedroute__route__wirelength__iter:10": 708455, - "detailedroute__route__wirelength__iter:11": 708452, - "detailedroute__route__wirelength__iter:12": 708500, - "detailedroute__route__wirelength__iter:13": 708511, - "detailedroute__route__wirelength__iter:2": 708409, - "detailedroute__route__wirelength__iter:3": 708532, - "detailedroute__route__wirelength__iter:4": 708414, - "detailedroute__route__wirelength__iter:5": 708396, - "detailedroute__route__wirelength__iter:6": 708387, - "detailedroute__route__wirelength__iter:7": 708437, - "detailedroute__route__wirelength__iter:8": 708439, - "detailedroute__route__wirelength__iter:9": 708439, - "finish__clock__skew__hold": 1.72264, - "finish__clock__skew__setup": 1.72283, - "finish__cpu__total": 67.61, - "finish__design__core__area": 300783, - "finish__design__die__area": 305400, - "finish__design__instance__area": 178459, - "finish__design__instance__area__class:antenna_cell": 175.168, - "finish__design__instance__area__class:buffer": 37.536, - "finish__design__instance__area__class:clock_buffer": 6094.6, - "finish__design__instance__area__class:clock_inverter": 884.598, - "finish__design__instance__area__class:inverter": 1058.52, - "finish__design__instance__area__class:multi_input_combinational_cell": 107382, - "finish__design__instance__area__class:sequential_cell": 47506.8, - "finish__design__instance__area__class:timing_repair_buffer": 10367.4, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 178459, - "finish__design__instance__count": 20038, - "finish__design__instance__count__class:antenna_cell": 70, - "finish__design__instance__count__class:buffer": 5, - "finish__design__instance__count__class:clock_buffer": 310, - "finish__design__instance__count__class:clock_inverter": 77, - "finish__design__instance__count__class:inverter": 199, - "finish__design__instance__count__class:multi_input_combinational_cell": 12545, - "finish__design__instance__count__class:sequential_cell": 1932, - "finish__design__instance__count__class:timing_repair_buffer": 942, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 20038, - "finish__design__instance__utilization": 0.593313, - "finish__design__instance__utilization__stdcell": 0.593313, - "finish__design__io": 264, - "finish__design__rows": 201, - "finish__design__rows:unithd": 201, - "finish__design__sites": 240396, - "finish__design__sites:unithd": 240396, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79856, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00151126, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00715379, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00826281, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79285, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00826281, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 488156.0, - "finish__power__internal__total": 0.0595607, - "finish__power__leakage__total": 7.29289e-08, - "finish__power__switching__total": 0.0829962, - "finish__power__total": 0.142557, - "finish__runtime__total": "1:08.07", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 5, - "finish__timing__drv__max_cap_limit": -0.27601, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 62, - "finish__timing__drv__max_slew_limit": -0.261538, - "finish__timing__drv__setup_violation_count": 419, - "finish__timing__setup__tns": -97.4269, - "finish__timing__setup__ws": -0.709249, - "finish__timing__wns_percent_delay": -8.143113, - "finish_merge__cpu__total": 3.59, - "finish_merge__mem__peak": 540980.0, - "finish_merge__runtime__total": "0:03.94", - "floorplan__cpu__total": 12.97, - "floorplan__design__core__area": 300783, - "floorplan__design__die__area": 305400, - "floorplan__design__instance__area": 130762, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 130762, - "floorplan__design__instance__count": 14618, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__stdcell": 14618, - "floorplan__design__instance__utilization": 0.434737, - "floorplan__design__instance__utilization__stdcell": 0.434737, - "floorplan__design__io": 264, - "floorplan__design__rows": 201, - "floorplan__design__rows:unithd": 201, - "floorplan__design__sites": 240396, - "floorplan__design__sites:unithd": 240396, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 197800.0, - "floorplan__power__internal__total": 0.0388497, - "floorplan__power__leakage__total": 5.41303e-08, - "floorplan__power__switching__total": 0.0261494, - "floorplan__power__total": 0.0649992, - "floorplan__runtime__total": "0:13.13", - "floorplan__timing__setup__tns": -21843.4, - "floorplan__timing__setup__ws": -14.6993, - "floorplan_io__cpu__total": 0.72, - "floorplan_io__mem__peak": 156160.0, - "floorplan_io__runtime__total": "0:00.81", - "floorplan_macro__cpu__total": 0.73, - "floorplan_macro__mem__peak": 155300.0, - "floorplan_macro__runtime__total": "0:00.82", - "floorplan_pdn__cpu__total": 1.35, - "floorplan_pdn__mem__peak": 171288.0, - "floorplan_pdn__runtime__total": "0:01.43", - "floorplan_tap__cpu__total": 0.69, - "floorplan_tap__mem__peak": 147112.0, - "floorplan_tap__runtime__total": "0:00.79", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1197.72, - "globalplace__design__core__area": 300783, - "globalplace__design__die__area": 305400, - "globalplace__design__instance__area": 161706, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 161706, - "globalplace__design__instance__count": 18699, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 18699, - "globalplace__design__instance__utilization": 0.537617, - "globalplace__design__instance__utilization__stdcell": 0.537617, - "globalplace__design__io": 264, - "globalplace__design__rows": 201, - "globalplace__design__rows:unithd": 201, - "globalplace__design__sites": 240396, - "globalplace__design__sites:unithd": 240396, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 833828.0, - "globalplace__power__internal__total": 0.0500563, - "globalplace__power__leakage__total": 6.37454e-08, - "globalplace__power__switching__total": 0.0669515, - "globalplace__power__total": 0.117008, - "globalplace__runtime__total": "1:42.87", - "globalplace__timing__setup__tns": -1040.01, - "globalplace__timing__setup__ws": -2.03501, - "globalplace_io__cpu__total": 0.74, - "globalplace_io__mem__peak": 161448.0, - "globalplace_io__runtime__total": "0:00.85", - "globalplace_skip_io__cpu__total": 205.22, - "globalplace_skip_io__mem__peak": 186328.0, - "globalplace_skip_io__runtime__total": "0:08.25", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 27, - "globalroute__clock__skew__hold": 1.68922, - "globalroute__clock__skew__setup": 1.68944, - "globalroute__cpu__total": 531.31, - "globalroute__design__core__area": 300783, - "globalroute__design__die__area": 305400, - "globalroute__design__instance__area": 178351, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 178351, - "globalroute__design__instance__count": 19995, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 162, - "globalroute__design__instance__count__stdcell": 19995, - "globalroute__design__instance__displacement__max": 11.04, - "globalroute__design__instance__displacement__mean": 0.127, - "globalroute__design__instance__displacement__total": 2537.18, - "globalroute__design__instance__utilization": 0.592955, - "globalroute__design__instance__utilization__stdcell": 0.592955, - "globalroute__design__io": 264, - "globalroute__design__rows": 201, - "globalroute__design__rows:unithd": 201, - "globalroute__design__sites": 240396, - "globalroute__design__sites:unithd": 240396, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 1102912.0, - "globalroute__power__internal__total": 0.0596081, - "globalroute__power__leakage__total": 7.29287e-08, - "globalroute__power__switching__total": 0.0846369, - "globalroute__power__total": 0.144245, - "globalroute__route__wirelength__estimated": 534138, - "globalroute__runtime__total": "4:43.35", - "globalroute__timing__clock__slack": -0.65, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 1, - "globalroute__timing__drv__max_cap_limit": -0.0949159, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 5, - "globalroute__timing__drv__max_slew_limit": -0.136308, - "globalroute__timing__drv__setup_violation_count": 189, - "globalroute__timing__setup__tns": -24.0751, - "globalroute__timing__setup__ws": -0.650396, - "placeopt__cpu__total": 22.34, - "placeopt__design__core__area": 300783, - "placeopt__design__die__area": 305400, - "placeopt__design__instance__area": 163340, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 163340, - "placeopt__design__instance__count": 18953, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 18953, - "placeopt__design__instance__utilization": 0.54305, - "placeopt__design__instance__utilization__stdcell": 0.54305, - "placeopt__design__io": 264, - "placeopt__design__rows": 201, - "placeopt__design__rows:unithd": 201, - "placeopt__design__sites": 240396, - "placeopt__design__sites:unithd": 240396, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 696828.0, - "placeopt__power__internal__total": 0.0504395, - "placeopt__power__leakage__total": 6.46777e-08, - "placeopt__power__switching__total": 0.06718, - "placeopt__power__total": 0.11762, - "placeopt__runtime__total": "0:22.91", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0186151, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0350381, - "placeopt__timing__drv__setup_violation_count": 971, - "placeopt__timing__setup__tns": -1034.58, - "placeopt__timing__setup__ws": -2.03024, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-11-28 16:24", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17429-g24d1bf502", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "4e29da58-f0b5-44e6-8e92-d2b6cf6f172b", - "run__flow__variant": "base", - "synth__cpu__total": 121.85, - "synth__design__instance__area__stdcell": 136437.104, - "synth__design__instance__count__stdcell": 15954.0, - "synth__mem__peak": 158264.0, - "synth__runtime__total": "2:02.25", - "total_time": "0:16:01.710000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/ibex/rules-base.json b/flow/designs/sky130hd/ibex/rules-base.json index bb527fa90f..c90e9cb8fd 100644 --- a/flow/designs/sky130hd/ibex/rules-base.json +++ b/flow/designs/sky130hd/ibex/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21306, + "value": 20977, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1853, + "value": 1824, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1853, + "value": 1824, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 31, + "value": 128, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 814720, + "value": 801898, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 49, + "value": 64, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.2, + "value": -0.98, "compare": ">=" }, "finish__design__instance__area": { - "value": 205228, + "value": 204569, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 948, + "value": 915, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -19.77, + "value": -16.91, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/jpeg/autotuner.json b/flow/designs/sky130hd/jpeg/autotuner.json index 1210719035..49d4cea07c 100644 --- a/flow/designs/sky130hd/jpeg/autotuner.json +++ b/flow/designs/sky130hd/jpeg/autotuner.json @@ -24,18 +24,10 @@ ], "step": 0 }, - "CORE_MARGIN": { - "type": "int", - "minmax": [ - 2, - 2 - ], - "step": 0 - }, "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -43,7 +35,7 @@ "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": { "type": "int", "minmax": [ - 1, + 0, 3 ], "step": 1 @@ -60,18 +52,10 @@ "type": "float", "minmax": [ 0.0, - 0.1 + 0.2 ], "step": 0 }, - "_PINS_DISTANCE": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 1 - }, "CTS_CLUSTER_SIZE": { "type": "int", "minmax": [ @@ -88,13 +72,5 @@ ], "step": 1 }, - "_FR_FILE_PATH": "fastroute.tcl", - "_FR_GR_OVERFLOW": { - "type": "int", - "minmax": [ - 1, - 1 - ], - "step": 0 - } + "_FR_FILE_PATH": "fastroute.tcl" } diff --git a/flow/designs/sky130hd/jpeg/config.mk b/flow/designs/sky130hd/jpeg/config.mk index dced6f2bca..995fbeda5f 100644 --- a/flow/designs/sky130hd/jpeg/config.mk +++ b/flow/designs/sky130hd/jpeg/config.mk @@ -13,3 +13,6 @@ export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl export REMOVE_ABC_BUFFERS = 1 + +# workaround for density growing to 0.91 from adjustments on TD/RD iterations +export GPL_ROUTABILITY_DRIVEN = 0 diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc index 879a3ef4b4..5d9b007f0e 100644 --- a/flow/designs/sky130hd/jpeg/constraint.sdc +++ b/flow/designs/sky130hd/jpeg/constraint.sdc @@ -1,15 +1,15 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 8.0 +set clk_period 5.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/jpeg/fastroute.tcl b/flow/designs/sky130hd/jpeg/fastroute.tcl index 80a2ca181e..e795f5e820 100644 --- a/flow/designs/sky130hd/jpeg/fastroute.tcl +++ b/flow/designs/sky130hd/jpeg/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/jpeg/metadata-base-ok.json b/flow/designs/sky130hd/jpeg/metadata-base-ok.json deleted file mode 100644 index 19e0e7c67a..0000000000 --- a/flow/designs/sky130hd/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,360 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 8.0000" - ], - "cts__clock__skew__hold": 0.109872, - "cts__clock__skew__setup": 0.109872, - "cts__cpu__total": 58.28, - "cts__design__core__area": 965699, - "cts__design__die__area": 972827, - "cts__design__instance__area": 540354, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 540354, - "cts__design__instance__count": 65378, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 65378, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.559548, - "cts__design__instance__utilization__stdcell": 0.559548, - "cts__design__io": 47, - "cts__design__rows": 361, - "cts__design__rows:unithd": 361, - "cts__design__sites": 771818, - "cts__design__sites:unithd": 771818, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 1061660.0, - "cts__power__internal__total": 0.377681, - "cts__power__leakage__total": 2.48599e-07, - "cts__power__switching__total": 0.436043, - "cts__power__total": 0.813723, - "cts__route__wirelength__estimated": 1199090.0, - "cts__runtime__total": "0:59.17", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.01612, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0391468, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.00157652, - "design__io__hpwl": 8581924, - "design__violations": 0, - "detailedplace__cpu__total": 73.61, - "detailedplace__design__core__area": 965699, - "detailedplace__design__die__area": 972827, - "detailedplace__design__instance__area": 521888, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 521888, - "detailedplace__design__instance__count": 64387, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 64387, - "detailedplace__design__instance__displacement__max": 15.577, - "detailedplace__design__instance__displacement__mean": 2.289, - "detailedplace__design__instance__displacement__total": 147439, - "detailedplace__design__instance__utilization": 0.540425, - "detailedplace__design__instance__utilization__stdcell": 0.540425, - "detailedplace__design__io": 47, - "detailedplace__design__rows": 361, - "detailedplace__design__rows:unithd": 361, - "detailedplace__design__sites": 771818, - "detailedplace__design__sites:unithd": 771818, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 493520.0, - "detailedplace__power__internal__total": 0.361791, - "detailedplace__power__leakage__total": 2.39495e-07, - "detailedplace__power__switching__total": 0.416728, - "detailedplace__power__total": 0.778519, - "detailedplace__route__wirelength__estimated": 1196140.0, - "detailedplace__runtime__total": "1:14.02", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0137956, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0369406, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.0190648, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 49, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 145, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 216, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 53, - "detailedroute__route__drc_errors__iter:3": 27, - "detailedroute__route__drc_errors__iter:4": 10, - "detailedroute__route__drc_errors__iter:5": 10, - "detailedroute__route__drc_errors__iter:6": 10, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 64008, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 354869, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 354869, - "detailedroute__route__wirelength": 1365641, - "detailedroute__route__wirelength__iter:1": 1365671, - "detailedroute__route__wirelength__iter:10": 1364974, - "detailedroute__route__wirelength__iter:11": 1364984, - "detailedroute__route__wirelength__iter:2": 1365676, - "detailedroute__route__wirelength__iter:3": 1365664, - "detailedroute__route__wirelength__iter:4": 1365643, - "detailedroute__route__wirelength__iter:5": 1365643, - "detailedroute__route__wirelength__iter:6": 1365643, - "detailedroute__route__wirelength__iter:7": 1365641, - "detailedroute__route__wirelength__iter:8": 1364974, - "detailedroute__route__wirelength__iter:9": 1364971, - "finish__clock__skew__hold": 0.108251, - "finish__clock__skew__setup": 0.108251, - "finish__cpu__total": 105.85, - "finish__design__core__area": 965699, - "finish__design__die__area": 972827, - "finish__design__instance__area": 541374, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 541374, - "finish__design__instance__count": 65689, - "finish__design__instance__count__class:antenna_cell": 283, - "finish__design__instance__count__class:clock_buffer": 775, - "finish__design__instance__count__class:clock_inverter": 216, - "finish__design__instance__count__class:fill_cell": 79966, - "finish__design__instance__count__class:inverter": 9532, - "finish__design__instance__count__class:multi_input_combinational_cell": 37316, - "finish__design__instance__count__class:sequential_cell": 4385, - "finish__design__instance__count__class:tap_cell": 12886, - "finish__design__instance__count__class:timing_repair_buffer": 296, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 65689, - "finish__design__instance__utilization": 0.560604, - "finish__design__instance__utilization__stdcell": 0.560604, - "finish__design__io": 47, - "finish__design__rows": 361, - "finish__design__rows:unithd": 361, - "finish__design__sites": 771818, - "finish__design__sites:unithd": 771818, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79769, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0024201, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00994306, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0119352, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79006, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0119352, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1025836.0, - "finish__power__internal__total": 0.375959, - "finish__power__leakage__total": 2.48807e-07, - "finish__power__switching__total": 0.434445, - "finish__power__total": 0.810404, - "finish__runtime__total": "1:46.85", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.011789, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0207335, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.282058, - "finish__timing__wns_percent_delay": 3.241076, - "finish_merge__cpu__total": 7.49, - "finish_merge__mem__peak": 838560.0, - "finish_merge__runtime__total": "0:08.08", - "floorplan__cpu__total": 32.17, - "floorplan__design__core__area": 965699, - "floorplan__design__die__area": 972827, - "floorplan__design__instance__area": 477036, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 477036, - "floorplan__design__instance__count": 51233, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 51233, - "floorplan__design__instance__utilization": 0.49398, - "floorplan__design__instance__utilization__stdcell": 0.49398, - "floorplan__design__io": 47, - "floorplan__design__rows": 361, - "floorplan__design__rows:unithd": 361, - "floorplan__design__sites": 771818, - "floorplan__design__sites:unithd": 771818, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 395236.0, - "floorplan__power__internal__total": 0.313698, - "floorplan__power__leakage__total": 2.33901e-07, - "floorplan__power__switching__total": 0.232373, - "floorplan__power__total": 0.546071, - "floorplan__runtime__total": "0:32.47", - "floorplan__timing__setup__tns": -70598.1, - "floorplan__timing__setup__ws": -69.6976, - "floorplan_io__cpu__total": 1.0, - "floorplan_io__mem__peak": 224596.0, - "floorplan_io__runtime__total": "0:01.20", - "floorplan_macro__cpu__total": 1.03, - "floorplan_macro__mem__peak": 222104.0, - "floorplan_macro__runtime__total": "0:01.22", - "floorplan_pdn__cpu__total": 2.89, - "floorplan_pdn__mem__peak": 271968.0, - "floorplan_pdn__runtime__total": "0:03.09", - "floorplan_tap__cpu__total": 0.92, - "floorplan_tap__mem__peak": 195168.0, - "floorplan_tap__runtime__total": "0:01.13", - "floorplan_tdms__cpu__total": 0.18, - "floorplan_tdms__mem__peak": 99928.0, - "floorplan_tdms__runtime__total": "0:00.28", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 991.68, - "globalplace__design__core__area": 965699, - "globalplace__design__die__area": 972827, - "globalplace__design__instance__area": 493159, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 493159, - "globalplace__design__instance__count": 64119, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 64119, - "globalplace__design__instance__utilization": 0.510676, - "globalplace__design__instance__utilization__stdcell": 0.510676, - "globalplace__design__io": 47, - "globalplace__design__rows": 361, - "globalplace__design__rows:unithd": 361, - "globalplace__design__sites": 771818, - "globalplace__design__sites:unithd": 771818, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1193172.0, - "globalplace__power__internal__total": 0.339259, - "globalplace__power__leakage__total": 2.33901e-07, - "globalplace__power__switching__total": 0.38014, - "globalplace__power__total": 0.7194, - "globalplace__runtime__total": "4:10.88", - "globalplace__timing__setup__tns": -209917, - "globalplace__timing__setup__ws": -253.556, - "globalplace_io__cpu__total": 1.11, - "globalplace_io__mem__peak": 240784.0, - "globalplace_io__runtime__total": "0:01.30", - "globalplace_skip_io__cpu__total": 553.81, - "globalplace_skip_io__mem__peak": 316276.0, - "globalplace_skip_io__runtime__total": "0:23.23", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 234, - "globalroute__clock__skew__hold": 0.120395, - "globalroute__clock__skew__setup": 0.120395, - "globalroute__cpu__total": 507.25, - "globalroute__design__core__area": 965699, - "globalroute__design__die__area": 972827, - "globalroute__design__instance__area": 541252, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 541252, - "globalroute__design__instance__count": 65640, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 27, - "globalroute__design__instance__count__stdcell": 65640, - "globalroute__design__instance__displacement__max": 9.2, - "globalroute__design__instance__displacement__mean": 0.002, - "globalroute__design__instance__displacement__total": 162.06, - "globalroute__design__instance__utilization": 0.560477, - "globalroute__design__instance__utilization__stdcell": 0.560477, - "globalroute__design__io": 47, - "globalroute__design__rows": 361, - "globalroute__design__rows:unithd": 361, - "globalroute__design__sites": 771818, - "globalroute__design__sites:unithd": 771818, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1505652.0, - "globalroute__power__internal__total": 0.389931, - "globalroute__power__leakage__total": 2.48807e-07, - "globalroute__power__switching__total": 0.510344, - "globalroute__power__total": 0.900275, - "globalroute__route__wirelength__estimated": 1200890.0, - "globalroute__runtime__total": "1:53.00", - "globalroute__timing__clock__slack": 0.029, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.041982, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0500722, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.0293445, - "placeopt__cpu__total": 60.02, - "placeopt__design__core__area": 965699, - "placeopt__design__die__area": 972827, - "placeopt__design__instance__area": 521888, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 521888, - "placeopt__design__instance__count": 64387, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 64387, - "placeopt__design__instance__utilization": 0.540425, - "placeopt__design__instance__utilization__stdcell": 0.540425, - "placeopt__design__io": 47, - "placeopt__design__rows": 361, - "placeopt__design__rows:unithd": 361, - "placeopt__design__sites": 771818, - "placeopt__design__sites:unithd": 771818, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 863228.0, - "placeopt__power__internal__total": 0.361801, - "placeopt__power__leakage__total": 2.39495e-07, - "placeopt__power__switching__total": 0.413409, - "placeopt__power__total": 0.77521, - "placeopt__runtime__total": "1:00.95", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0072053, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0309118, - "placeopt__timing__drv__setup_violation_count": 2, - "placeopt__timing__setup__tns": -0.168848, - "placeopt__timing__setup__ws": -0.091422, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-10-28 13:59", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16787-gcd519bb5e", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "f61d2ab1-8ce1-4193-8a9d-39ba48c6566c", - "run__flow__variant": "base", - "synth__cpu__total": 146.62, - "synth__design__instance__area__stdcell": 484442.1184, - "synth__design__instance__count__stdcell": 53182.0, - "synth__mem__peak": 740116.0, - "synth__runtime__total": "2:28.12", - "total_time": "0:14:44.990000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index 359f00156d..780a6ec5bd 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 554199.03, + "value": 464771.19, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 598574, + "value": 497902, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 73131, + "value": 55309, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6359, + "value": 4810, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6359, + "value": 4810, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 269, + "value": 220, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 1536290, + "value": 1362963, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 56, + "value": 81, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.11, + "value": -0.25, "compare": ">=" }, "finish__design__instance__area": { - "value": 621399, + "value": 520067, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3180, + "value": 2405, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index c38676da4e..589df7a899 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -8,10 +8,8 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/* export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export DIE_AREA = 0 0 2920 3520 -export CORE_AREA = 10 10 2910 3510 - -export PLACE_DENSITY ?= 0.23 +export DIE_AREA = 0 0 3020 3610 +export CORE_AREA = 10 10 3010 3600 export microwatt_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME) @@ -23,17 +21,33 @@ export ADDITIONAL_LIBS = $(wildcard $(microwatt_DIR)/lib/*.lib) export SYNTH_HIERARCHICAL = 1 -export RTLMP_BOUNDARY_WT = 0 export MACRO_PLACE_HALO = 100 100 -export MACRO_PLACE_CHANNEL = 200 200 + +# We use large placement blockages to try eliminating the channels between +# RAMs in order to make that space inaccessible for GPL. Experiments have +# showed that connections crossing the RAMs vertically can be painful to +# route. +export MACRO_BLOCKAGE_HALO = 151 + +# There's less space due to the adapted blockage halos, so GPL requires a +# higher density in order to run. +export PLACE_DENSITY = 0.2 + +# Extra effort to ease routing: avoid very tall std cell clusters in MPL. +export RTLMP_MIN_AR = 0.40 # CTS tuning export CTS_BUF_DISTANCE = 600 export SKIP_GATE_CLONING = 1 +export CTS_CLUSTER_SIZE = 10 +export CTS_CLUSTER_DIAMETER = 50 export SETUP_SLACK_MARGIN = 0.2 +# GRT non-default config +export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl + # This is high, some SRAMs should probably be converted # to real SRAMs and not instantiated as flops -export SYNTH_MEMORY_MAX_BITS ?= 42000 +export SYNTH_MEMORY_MAX_BITS = 42000 diff --git a/flow/designs/sky130hd/microwatt/constraint.sdc b/flow/designs/sky130hd/microwatt/constraint.sdc index cc9dbbe523..55170d5f75 100644 --- a/flow/designs/sky130hd/microwatt/constraint.sdc +++ b/flow/designs/sky130hd/microwatt/constraint.sdc @@ -49,13 +49,17 @@ set jtag_clk_port [get_ports $jtag_clk_port_name] create_clock -name $jtag_clk_name -period $jtag_clk_period $jtag_clk_port set_clock_groups -name group1 -logically_exclusive \ - -group [get_clocks $jtag_clk_name]\ - -group [get_clocks $clk_name] - -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdi] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tms] -set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_trst] -set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] -clock $jtag_clk_name [get_ports jtag_tdo] + -group [get_clocks $jtag_clk_name] \ + -group [get_clocks $clk_name] + +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdi] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tms] +set_input_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_trst] +set_output_delay [expr $jtag_clk_period * $jtag_clk_io_pct] \ + -clock $jtag_clk_name [get_ports jtag_tdo] set_max_fanout 10 [current_design] diff --git a/flow/platforms/sky130hd_fakestack/fastroute.tcl b/flow/designs/sky130hd/microwatt/fastroute.tcl similarity index 56% rename from flow/platforms/sky130hd_fakestack/fastroute.tcl rename to flow/designs/sky130hd/microwatt/fastroute.tcl index 55f10921ed..e1ea87c701 100644 --- a/flow/platforms/sky130hd_fakestack/fastroute.tcl +++ b/flow/designs/sky130hd/microwatt/fastroute.tcl @@ -1,4 +1,4 @@ -set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.3 +set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.15 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/designs/sky130hd/microwatt/lef/RAM32_1RW1R.lef b/flow/designs/sky130hd/microwatt/lef/RAM32_1RW1R.lef index 99334202f1..aee8437ba8 100644 --- a/flow/designs/sky130hd/microwatt/lef/RAM32_1RW1R.lef +++ b/flow/designs/sky130hd/microwatt/lef/RAM32_1RW1R.lef @@ -2018,18 +2018,18 @@ MACRO RAM32_1RW1R RECT 0.985 0.175 1171.460 5.760 ; LAYER met4 ; RECT 3.055 3.575 5.810 175.945 ; - RECT 9.710 3.575 95.810 175.945 ; - RECT 99.710 3.575 185.810 175.945 ; - RECT 189.710 3.575 275.810 175.945 ; - RECT 279.710 3.575 365.810 175.945 ; - RECT 369.710 3.575 455.810 175.945 ; - RECT 459.710 3.575 545.810 175.945 ; + RECT 26.100 3.575 28.100 175.945 ; + RECT 123.000 3.575 162.100 175.945 ; + RECT 240.000 3.575 275.810 175.945 ; + RECT 279.710 3.575 291.300 175.945 ; + RECT 375.000 3.575 450.000 175.945 ; + RECT 487.000 3.575 545.810 175.945 ; RECT 549.710 3.575 635.810 175.945 ; - RECT 639.710 3.575 725.810 175.945 ; - RECT 729.710 3.575 815.810 175.945 ; - RECT 819.710 3.575 905.810 175.945 ; - RECT 909.710 3.575 995.810 175.945 ; - RECT 999.710 3.575 1077.945 175.945 ; + RECT 639.710 3.575 664.100 175.945 ; + RECT 760.000 3.575 804.870 175.945 ; + RECT 891.600 3.575 905.810 175.945 ; + RECT 909.710 3.575 927.000 175.945 ; + RECT 1015.100 3.575 1078.810 175.945 ; END END RAM32_1RW1R END LIBRARY diff --git a/flow/designs/sky130hd/microwatt/metadata-base-ok.json b/flow/designs/sky130hd/microwatt/metadata-base-ok.json deleted file mode 100644 index 2a9d1ca7c7..0000000000 --- a/flow/designs/sky130hd/microwatt/metadata-base-ok.json +++ /dev/null @@ -1,421 +0,0 @@ -{ - "constraints__clocks__count": 2, - "constraints__clocks__details": [ - "ext_clk: 15.0000", - "jtag_tck: 100.0000" - ], - "cts__clock__skew__hold": 1.68404, - "cts__clock__skew__setup": 1.42715, - "cts__cpu__total": 171.19, - "cts__design__core__area": 10143400.0, - "cts__design__die__area": 10278400.0, - "cts__design__instance__area": 5017530.0, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 3926470.0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 1091050.0, - "cts__design__instance__count": 173898, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 4018, - "cts__design__instance__count__macros": 6, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 60, - "cts__design__instance__count__stdcell": 173892, - "cts__design__instance__displacement__max": 499.074, - "cts__design__instance__displacement__mean": 0.145, - "cts__design__instance__displacement__total": 25343.4, - "cts__design__instance__utilization": 0.494659, - "cts__design__instance__utilization__stdcell": 0.175497, - "cts__design__io": 141, - "cts__design__rows": 2625, - "cts__design__rows:unithd": 2625, - "cts__design__sites": 4927108, - "cts__design__sites:unithd": 4927108, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 16, - "cts__mem__peak": 2267180.0, - "cts__power__internal__total": 0.0575169, - "cts__power__leakage__total": 4.16579e-07, - "cts__power__switching__total": 0.0368404, - "cts__power__total": 0.0943577, - "cts__route__wirelength__estimated": 8015940.0, - "cts__runtime__total": "2:52.64", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 3, - "cts__timing__drv__max_cap_limit": -0.580748, - "cts__timing__drv__max_fanout": 189, - "cts__timing__drv__max_fanout_limit": 10, - "cts__timing__drv__max_slew": 9, - "cts__timing__drv__max_slew_limit": -0.592394, - "cts__timing__drv__setup_violation_count": 337, - "cts__timing__setup__tns": -799.038, - "cts__timing__setup__ws": -3.50235, - "design__io__hpwl": 95041985, - "design__violations": 0, - "detailedplace__cpu__total": 72.33, - "detailedplace__design__core__area": 10143400.0, - "detailedplace__design__die__area": 10278400.0, - "detailedplace__design__instance__area": 4923810.0, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 3926470.0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 997335, - "detailedplace__design__instance__count": 167117, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 6, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 167111, - "detailedplace__design__instance__displacement__max": 489.049, - "detailedplace__design__instance__displacement__mean": 0.859, - "detailedplace__design__instance__displacement__total": 143712, - "detailedplace__design__instance__utilization": 0.48542, - "detailedplace__design__instance__utilization__stdcell": 0.160422, - "detailedplace__design__io": 141, - "detailedplace__design__rows": 2625, - "detailedplace__design__rows:unithd": 2625, - "detailedplace__design__sites": 4927108, - "detailedplace__design__sites:unithd": 4927108, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1582420.0, - "detailedplace__power__internal__total": 0.0356702, - "detailedplace__power__leakage__total": 3.65479e-07, - "detailedplace__power__switching__total": 0.0183213, - "detailedplace__power__total": 0.0539919, - "detailedplace__route__wirelength__estimated": 7908920.0, - "detailedplace__runtime__total": "1:13.21", - "detailedplace__timing__drv__hold_violation_count": 852, - "detailedplace__timing__drv__max_cap": 1, - "detailedplace__timing__drv__max_cap_limit": -0.068057, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 10, - "detailedplace__timing__drv__max_slew": 2, - "detailedplace__timing__drv__max_slew_limit": -0.00765699, - "detailedplace__timing__drv__setup_violation_count": 335, - "detailedplace__timing__setup__tns": -731.268, - "detailedplace__timing__setup__ws": -3.93589, - "detailedroute__antenna__violating__nets": 1, - "detailedroute__antenna__violating__pins": 1, - "detailedroute__antenna_diodes_count": 1910, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 398, - "detailedroute__route__drc_errors__iter:1": 364, - "detailedroute__route__drc_errors__iter:10": 44, - "detailedroute__route__drc_errors__iter:11": 26, - "detailedroute__route__drc_errors__iter:12": 7, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:14": 37, - "detailedroute__route__drc_errors__iter:15": 31, - "detailedroute__route__drc_errors__iter:16": 30, - "detailedroute__route__drc_errors__iter:17": 30, - "detailedroute__route__drc_errors__iter:18": 10, - "detailedroute__route__drc_errors__iter:19": 1, - "detailedroute__route__drc_errors__iter:2": 310, - "detailedroute__route__drc_errors__iter:20": 0, - "detailedroute__route__drc_errors__iter:21": 0, - "detailedroute__route__drc_errors__iter:23": 0, - "detailedroute__route__drc_errors__iter:3": 169, - "detailedroute__route__drc_errors__iter:4": 159, - "detailedroute__route__drc_errors__iter:5": 124, - "detailedroute__route__drc_errors__iter:6": 112, - "detailedroute__route__drc_errors__iter:7": 85, - "detailedroute__route__drc_errors__iter:8": 70, - "detailedroute__route__drc_errors__iter:9": 70, - "detailedroute__route__net": 91828, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 786815, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 786815, - "detailedroute__route__wirelength": 9352317, - "detailedroute__route__wirelength__iter:0": 9352272, - "detailedroute__route__wirelength__iter:1": 9352258, - "detailedroute__route__wirelength__iter:10": 9352354, - "detailedroute__route__wirelength__iter:11": 9352312, - "detailedroute__route__wirelength__iter:12": 9352318, - "detailedroute__route__wirelength__iter:13": 9352317, - "detailedroute__route__wirelength__iter:14": 9352313, - "detailedroute__route__wirelength__iter:15": 9352313, - "detailedroute__route__wirelength__iter:16": 9352313, - "detailedroute__route__wirelength__iter:17": 9352313, - "detailedroute__route__wirelength__iter:18": 9352293, - "detailedroute__route__wirelength__iter:19": 9352316, - "detailedroute__route__wirelength__iter:2": 9352263, - "detailedroute__route__wirelength__iter:20": 9352325, - "detailedroute__route__wirelength__iter:21": 9353095, - "detailedroute__route__wirelength__iter:23": 9353850, - "detailedroute__route__wirelength__iter:3": 9352256, - "detailedroute__route__wirelength__iter:4": 9352243, - "detailedroute__route__wirelength__iter:5": 9352281, - "detailedroute__route__wirelength__iter:6": 9352262, - "detailedroute__route__wirelength__iter:7": 9352271, - "detailedroute__route__wirelength__iter:8": 9352300, - "detailedroute__route__wirelength__iter:9": 9352300, - "finish__clock__skew__hold": 1.31916, - "finish__clock__skew__setup": 1.12024, - "finish__cpu__total": 298.66, - "finish__design__core__area": 10143400.0, - "finish__design__die__area": 10278400.0, - "finish__design__instance__area": 5031920.0, - "finish__design__instance__area__class:antenna_cell": 12056.6, - "finish__design__instance__area__class:buffer": 106875, - "finish__design__instance__area__class:clock_buffer": 43992.2, - "finish__design__instance__area__class:clock_inverter": 6164.66, - "finish__design__instance__area__class:inverter": 9142.52, - "finish__design__instance__area__class:macro": 3926470.0, - "finish__design__instance__area__class:multi_input_combinational_cell": 499154, - "finish__design__instance__area__class:sequential_cell": 216196, - "finish__design__instance__area__class:timing_repair_buffer": 108076, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 3926470.0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 1105450.0, - "finish__design__instance__count": 178777, - "finish__design__instance__count__class:antenna_cell": 4818, - "finish__design__instance__count__class:buffer": 9706, - "finish__design__instance__count__class:clock_buffer": 2174, - "finish__design__instance__count__class:clock_inverter": 543, - "finish__design__instance__count__class:inverter": 1653, - "finish__design__instance__count__class:macro": 6, - "finish__design__instance__count__class:multi_input_combinational_cell": 55828, - "finish__design__instance__count__class:sequential_cell": 10257, - "finish__design__instance__count__class:timing_repair_buffer": 10839, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 6, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 178771, - "finish__design__instance__utilization": 0.496078, - "finish__design__instance__utilization__stdcell": 0.177812, - "finish__design__io": 141, - "finish__design__rows": 2625, - "finish__design__rows:unithd": 2625, - "finish__design__sites": 4927108, - "finish__design__sites:unithd": 4927108, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79996, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 3.77543e-05, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.000277878, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00053695, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79972, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00053695, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 3432928.0, - "finish__power__internal__total": 0.0575509, - "finish__power__leakage__total": 4.17485e-07, - "finish__power__switching__total": 0.0368467, - "finish__power__total": 0.094398, - "finish__runtime__total": "5:02.55", - "finish__timing__drv__hold_violation_count": 58, - "finish__timing__drv__max_cap": 72, - "finish__timing__drv__max_cap_limit": -1.15915, - "finish__timing__drv__max_fanout": 624, - "finish__timing__drv__max_fanout_limit": 10, - "finish__timing__drv__max_slew": 150, - "finish__timing__drv__max_slew_limit": -0.319702, - "finish__timing__drv__setup_violation_count": 338, - "finish__timing__setup__tns": -835.677, - "finish__timing__setup__ws": -3.93259, - "finish__timing__wns_percent_delay": -18.020107, - "finish_merge__cpu__total": 31.01, - "finish_merge__mem__peak": 3091944.0, - "finish_merge__runtime__total": "0:33.13", - "floorplan__cpu__total": 251.61, - "floorplan__design__core__area": 10143400.0, - "floorplan__design__die__area": 10278400.0, - "floorplan__design__instance__area": 4615280.0, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 3926470.0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 688806, - "floorplan__design__instance__count": 81771, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 5167, - "floorplan__design__instance__count__macros": 6, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 20, - "floorplan__design__instance__count__stdcell": 81765, - "floorplan__design__instance__utilization": 0.455003, - "floorplan__design__instance__utilization__stdcell": 0.110795, - "floorplan__design__io": 141, - "floorplan__design__rows": 1286, - "floorplan__design__rows:unithd": 1286, - "floorplan__design__sites": 8106944, - "floorplan__design__sites:unithd": 8106944, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 5263, - "floorplan__mem__peak": 465908.0, - "floorplan__power__internal__total": 0.0329408, - "floorplan__power__leakage__total": 2.9177e-07, - "floorplan__power__switching__total": 0.004552, - "floorplan__power__total": 0.0374931, - "floorplan__runtime__total": "4:11.94", - "floorplan__timing__setup__tns": -2.97492, - "floorplan__timing__setup__ws": -0.14123, - "floorplan_io__cpu__total": 0.9, - "floorplan_io__mem__peak": 283104.0, - "floorplan_io__runtime__total": "0:01.11", - "floorplan_macro__cpu__total": 2613.17, - "floorplan_macro__mem__peak": 474964.0, - "floorplan_macro__runtime__total": "3:02.25", - "floorplan_pdn__cpu__total": 9.24, - "floorplan_pdn__mem__peak": 607160.0, - "floorplan_pdn__runtime__total": "0:09.68", - "floorplan_tap__cpu__total": 1.18, - "floorplan_tap__mem__peak": 272820.0, - "floorplan_tap__runtime__total": "0:01.40", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1475.52, - "globalplace__design__core__area": 10143400.0, - "globalplace__design__die__area": 10278400.0, - "globalplace__design__instance__area": 4920160.0, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 3926470.0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 993688, - "globalplace__design__instance__count": 165986, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 6, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 165980, - "globalplace__design__instance__utilization": 0.48506, - "globalplace__design__instance__utilization__stdcell": 0.159836, - "globalplace__design__io": 141, - "globalplace__design__rows": 2625, - "globalplace__design__rows:unithd": 2625, - "globalplace__design__sites": 4927108, - "globalplace__design__sites:unithd": 4927108, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1701416.0, - "globalplace__power__internal__total": 0.0356271, - "globalplace__power__leakage__total": 3.62449e-07, - "globalplace__power__switching__total": 0.0185519, - "globalplace__power__total": 0.0541793, - "globalplace__runtime__total": "5:29.14", - "globalplace__timing__setup__tns": -797.297, - "globalplace__timing__setup__ws": -4.31887, - "globalplace_io__cpu__total": 1.49, - "globalplace_io__mem__peak": 401768.0, - "globalplace_io__runtime__total": "0:01.79", - "globalplace_skip_io__cpu__total": 320.6, - "globalplace_skip_io__mem__peak": 511928.0, - "globalplace_skip_io__runtime__total": "0:31.54", - "globalroute__antenna__violating__nets": 11, - "globalroute__antenna__violating__pins": 11, - "globalroute__antenna_diodes_count": 2908, - "globalroute__clock__skew__hold": 1.49534, - "globalroute__clock__skew__setup": 1.33074, - "globalroute__cpu__total": 691.1, - "globalroute__design__core__area": 10143400.0, - "globalroute__design__die__area": 10278400.0, - "globalroute__design__instance__area": 5027140.0, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 3926470.0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 1100670.0, - "globalroute__design__instance__count": 176867, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 20, - "globalroute__design__instance__count__macros": 6, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 17, - "globalroute__design__instance__count__stdcell": 176861, - "globalroute__design__instance__displacement__max": 7.28, - "globalroute__design__instance__displacement__mean": 0.002, - "globalroute__design__instance__displacement__total": 487.68, - "globalroute__design__instance__utilization": 0.495607, - "globalroute__design__instance__utilization__stdcell": 0.177044, - "globalroute__design__io": 141, - "globalroute__design__rows": 2625, - "globalroute__design__rows:unithd": 2625, - "globalroute__design__sites": 4927108, - "globalroute__design__sites:unithd": 4927108, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 2, - "globalroute__mem__peak": 3743936.0, - "globalroute__power__internal__total": 0.0575954, - "globalroute__power__leakage__total": 4.17485e-07, - "globalroute__power__switching__total": 0.0383212, - "globalroute__power__total": 0.095917, - "globalroute__route__wirelength__estimated": 8017310.0, - "globalroute__runtime__total": "4:29.51", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 43, - "globalroute__timing__drv__max_cap_limit": -1.2403, - "globalroute__timing__drv__max_fanout": 401, - "globalroute__timing__drv__max_fanout_limit": 10, - "globalroute__timing__drv__max_slew": 14, - "globalroute__timing__drv__max_slew_limit": -0.00833415, - "globalroute__timing__drv__setup_violation_count": 335, - "globalroute__timing__setup__tns": -725.83, - "globalroute__timing__setup__ws": -3.29195, - "placeopt__cpu__total": 56.1, - "placeopt__design__core__area": 10143400.0, - "placeopt__design__die__area": 10278400.0, - "placeopt__design__instance__area": 4923810.0, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 3926470.0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 997335, - "placeopt__design__instance__count": 167117, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 6, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 167111, - "placeopt__design__instance__utilization": 0.48542, - "placeopt__design__instance__utilization__stdcell": 0.160422, - "placeopt__design__io": 141, - "placeopt__design__rows": 2625, - "placeopt__design__rows:unithd": 2625, - "placeopt__design__sites": 4927108, - "placeopt__design__sites:unithd": 4927108, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 1, - "placeopt__mem__peak": 1096276.0, - "placeopt__power__internal__total": 0.0356721, - "placeopt__power__leakage__total": 3.65479e-07, - "placeopt__power__switching__total": 0.0185951, - "placeopt__power__total": 0.0542676, - "placeopt__runtime__total": "0:56.91", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 2, - "placeopt__timing__drv__hold_violation_count": 852, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00938227, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 10, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.00224583, - "placeopt__timing__drv__setup_violation_count": 335, - "placeopt__timing__setup__tns": -740.676, - "placeopt__timing__setup__ws": -3.96828, - "run__flow__design": "microwatt", - "run__flow__generate_date": "2024-11-28 20:03", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17429-g24d1bf502", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "89e3c62a-df40-4018-b6e6-0c5151c6a13f", - "run__flow__variant": "base", - "synth__cpu__total": 199.1, - "synth__design__instance__area__stdcell": 636551.7536, - "synth__design__instance__count__stdcell": 76584.0, - "synth__mem__peak": 412008.0, - "synth__runtime__total": "3:21.63", - "total_time": "0:31:58.430000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/microwatt/rules-base.json b/flow/designs/sky130hd/microwatt/rules-base.json index acbcff11c7..4b1d9fe871 100644 --- a/flow/designs/sky130hd/microwatt/rules-base.json +++ b/flow/designs/sky130hd/microwatt/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5661289, + "value": 5621142, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 191836, + "value": 182480, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 16681, + "value": 15868, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 16681, + "value": 15868, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 3344, + "value": 4257, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 10332428, + "value": 10026505, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,31 +40,31 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 1, + "value": 3, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 2196, + "value": 1618, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -4.68, + "value": -3.13, "compare": ">=" }, "finish__design__instance__area": { - "value": 5775058, + "value": 5740777, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 8341, + "value": 7934, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 122, + "value": 262, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -21.69, + "value": -17.68, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd/mock-alu/config.mk b/flow/designs/sky130hd/mock-alu/config.mk deleted file mode 100644 index 4d097e2891..0000000000 --- a/flow/designs/sky130hd/mock-alu/config.mk +++ /dev/null @@ -1,6 +0,0 @@ -export PLATFORM = sky130hd - -include designs/src/mock-alu/defaults.mk - -export PLACE_DENSITY = 0.50 -export CORE_UTILIZATION = 30 diff --git a/flow/designs/sky130hd/mock-alu/constraints.sdc b/flow/designs/sky130hd/mock-alu/constraints.sdc deleted file mode 100644 index 206b2fda80..0000000000 --- a/flow/designs/sky130hd/mock-alu/constraints.sdc +++ /dev/null @@ -1,13 +0,0 @@ -set clk_name clock -set clk_port_name clock -set clk_period 5 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr 0.2 * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/riscv32i/constraint.sdc b/flow/designs/sky130hd/riscv32i/constraint.sdc index 70a1fcf751..5b0a6f1b4e 100644 --- a/flow/designs/sky130hd/riscv32i/constraint.sdc +++ b/flow/designs/sky130hd/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 6.0 +set clk_period 6.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hd/riscv32i/metadata-base-ok.json b/flow/designs/sky130hd/riscv32i/metadata-base-ok.json deleted file mode 100644 index 4eeea585a0..0000000000 --- a/flow/designs/sky130hd/riscv32i/metadata-base-ok.json +++ /dev/null @@ -1,344 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 6.0000" - ], - "cts__clock__skew__hold": 0.108343, - "cts__clock__skew__setup": 0.108343, - "cts__cpu__total": 118.17, - "cts__design__core__area": 137662, - "cts__design__die__area": 140475, - "cts__design__instance__area": 77091.4, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 77091.4, - "cts__design__instance__count": 8739, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 57, - "cts__design__instance__count__stdcell": 8739, - "cts__design__instance__displacement__max": 13.34, - "cts__design__instance__displacement__mean": 0.129, - "cts__design__instance__displacement__total": 1128.65, - "cts__design__instance__utilization": 0.560005, - "cts__design__instance__utilization__stdcell": 0.560005, - "cts__design__io": 165, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 751892.0, - "cts__power__internal__total": 0.0151707, - "cts__power__leakage__total": 3.04976e-08, - "cts__power__switching__total": 0.00802927, - "cts__power__total": 0.0232, - "cts__route__wirelength__estimated": 191570, - "cts__runtime__total": "1:58.84", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0267308, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.00723976, - "cts__timing__drv__setup_violation_count": 55, - "cts__timing__setup__tns": -24.2689, - "cts__timing__setup__ws": -0.936721, - "design__io__hpwl": 30156592, - "design__violations": 0, - "detailedplace__cpu__total": 11.1, - "detailedplace__design__core__area": 137662, - "detailedplace__design__die__area": 140475, - "detailedplace__design__instance__area": 72379.4, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 72379.4, - "detailedplace__design__instance__count": 8462, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 8462, - "detailedplace__design__instance__displacement__max": 31.51, - "detailedplace__design__instance__displacement__mean": 2.41, - "detailedplace__design__instance__displacement__total": 20398.8, - "detailedplace__design__instance__utilization": 0.525776, - "detailedplace__design__instance__utilization__stdcell": 0.525776, - "detailedplace__design__io": 165, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 181992.0, - "detailedplace__power__internal__total": 0.0109834, - "detailedplace__power__leakage__total": 2.81786e-08, - "detailedplace__power__switching__total": 0.00473308, - "detailedplace__power__total": 0.0157165, - "detailedplace__route__wirelength__estimated": 184860, - "detailedplace__runtime__total": "0:11.27", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0304658, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0233302, - "detailedplace__timing__drv__setup_violation_count": 383, - "detailedplace__timing__setup__tns": -119.874, - "detailedplace__timing__setup__ws": -1.06982, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 11, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 12, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 659, - "detailedroute__route__drc_errors__iter:10": 59, - "detailedroute__route__drc_errors__iter:11": 36, - "detailedroute__route__drc_errors__iter:12": 8, - "detailedroute__route__drc_errors__iter:13": 7, - "detailedroute__route__drc_errors__iter:14": 3, - "detailedroute__route__drc_errors__iter:15": 3, - "detailedroute__route__drc_errors__iter:16": 3, - "detailedroute__route__drc_errors__iter:17": 0, - "detailedroute__route__drc_errors__iter:2": 206, - "detailedroute__route__drc_errors__iter:3": 188, - "detailedroute__route__drc_errors__iter:4": 19, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__drc_errors__iter:6": 357, - "detailedroute__route__drc_errors__iter:7": 173, - "detailedroute__route__drc_errors__iter:8": 149, - "detailedroute__route__drc_errors__iter:9": 72, - "detailedroute__route__net": 7085, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 62707, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 62707, - "detailedroute__route__wirelength": 289869, - "detailedroute__route__wirelength__iter:1": 289950, - "detailedroute__route__wirelength__iter:10": 289472, - "detailedroute__route__wirelength__iter:11": 289440, - "detailedroute__route__wirelength__iter:12": 289473, - "detailedroute__route__wirelength__iter:13": 289473, - "detailedroute__route__wirelength__iter:14": 289466, - "detailedroute__route__wirelength__iter:15": 289466, - "detailedroute__route__wirelength__iter:16": 289466, - "detailedroute__route__wirelength__iter:17": 289489, - "detailedroute__route__wirelength__iter:2": 289839, - "detailedroute__route__wirelength__iter:3": 289832, - "detailedroute__route__wirelength__iter:4": 289847, - "detailedroute__route__wirelength__iter:5": 289869, - "detailedroute__route__wirelength__iter:6": 289528, - "detailedroute__route__wirelength__iter:7": 289484, - "detailedroute__route__wirelength__iter:8": 289457, - "detailedroute__route__wirelength__iter:9": 289481, - "finish__clock__skew__hold": 0.103772, - "finish__clock__skew__setup": 0.103772, - "finish__cpu__total": 25.11, - "finish__design__core__area": 137662, - "finish__design__die__area": 140475, - "finish__design__instance__area": 78446.5, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 78446.5, - "finish__design__instance__count": 8832, - "finish__design__instance__count__class:antenna_cell": 21, - "finish__design__instance__count__class:clock_buffer": 162, - "finish__design__instance__count__class:clock_inverter": 46, - "finish__design__instance__count__class:fill_cell": 10636, - "finish__design__instance__count__class:inverter": 188, - "finish__design__instance__count__class:multi_input_combinational_cell": 5235, - "finish__design__instance__count__class:sequential_cell": 1056, - "finish__design__instance__count__class:tap_cell": 1794, - "finish__design__instance__count__class:timing_repair_buffer": 330, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 8832, - "finish__design__instance__utilization": 0.569848, - "finish__design__instance__utilization__stdcell": 0.569848, - "finish__design__io": 165, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79939, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000448685, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00113951, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.000878824, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79886, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.000878824, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 335404.0, - "finish__power__internal__total": 0.0154163, - "finish__power__leakage__total": 3.09486e-08, - "finish__power__switching__total": 0.00874669, - "finish__power__total": 0.024163, - "finish__runtime__total": "0:25.40", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 4, - "finish__timing__drv__max_cap_limit": -0.0277635, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 187, - "finish__timing__drv__max_slew_limit": -0.0534122, - "finish__timing__drv__setup_violation_count": 102, - "finish__timing__setup__tns": -22.4894, - "finish__timing__setup__ws": -1.01475, - "finish__timing__wns_percent_delay": -17.450599, - "finish_merge__cpu__total": 2.35, - "finish_merge__mem__peak": 461084.0, - "finish_merge__runtime__total": "0:02.63", - "floorplan__cpu__total": 7.43, - "floorplan__design__core__area": 137662, - "floorplan__design__die__area": 140475, - "floorplan__design__instance__area": 59271.8, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 59271.8, - "floorplan__design__instance__count": 6459, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 6459, - "floorplan__design__instance__utilization": 0.430561, - "floorplan__design__instance__utilization__stdcell": 0.430561, - "floorplan__design__io": 165, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 160560.0, - "floorplan__power__internal__total": 0.0103104, - "floorplan__power__leakage__total": 2.24159e-08, - "floorplan__power__switching__total": 0.00224145, - "floorplan__power__total": 0.0125519, - "floorplan__runtime__total": "0:07.53", - "floorplan__timing__setup__tns": -387.266, - "floorplan__timing__setup__ws": -1.61649, - "floorplan_io__cpu__total": 0.58, - "floorplan_io__mem__peak": 140328.0, - "floorplan_io__runtime__total": "0:00.66", - "floorplan_macro__cpu__total": 0.59, - "floorplan_macro__mem__peak": 138744.0, - "floorplan_macro__runtime__total": "0:00.67", - "floorplan_pdn__cpu__total": 0.79, - "floorplan_pdn__mem__peak": 147764.0, - "floorplan_pdn__runtime__total": "0:00.90", - "floorplan_tap__cpu__total": 0.58, - "floorplan_tap__mem__peak": 135988.0, - "floorplan_tap__runtime__total": "0:00.65", - "floorplan_tdms__cpu__total": 0.18, - "floorplan_tdms__mem__peak": 99256.0, - "floorplan_tdms__runtime__total": "0:00.23", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 469.98, - "globalplace__design__core__area": 137662, - "globalplace__design__die__area": 140475, - "globalplace__design__instance__area": 61516.5, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 61516.5, - "globalplace__design__instance__count": 8253, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 8253, - "globalplace__design__instance__utilization": 0.446866, - "globalplace__design__instance__utilization__stdcell": 0.446866, - "globalplace__design__io": 165, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 741292.0, - "globalplace__power__internal__total": 0.0103726, - "globalplace__power__leakage__total": 2.24159e-08, - "globalplace__power__switching__total": 0.00400786, - "globalplace__power__total": 0.0143805, - "globalplace__runtime__total": "0:46.30", - "globalplace__timing__setup__tns": -3378.28, - "globalplace__timing__setup__ws": -5.04973, - "globalplace_io__cpu__total": 0.62, - "globalplace_io__mem__peak": 142392.0, - "globalplace_io__runtime__total": "0:00.69", - "globalplace_skip_io__cpu__total": 636.49, - "globalplace_skip_io__mem__peak": 150552.0, - "globalplace_skip_io__runtime__total": "0:21.24", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 10, - "globalroute__clock__skew__hold": 0.111781, - "globalroute__clock__skew__setup": 0.111781, - "globalroute__cpu__total": 202.13, - "globalroute__design__core__area": 137662, - "globalroute__design__die__area": 140475, - "globalroute__design__instance__area": 78419, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 78419, - "globalroute__design__instance__count": 8821, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 55, - "globalroute__design__instance__count__stdcell": 8821, - "globalroute__design__instance__displacement__max": 19.04, - "globalroute__design__instance__displacement__mean": 0.307, - "globalroute__design__instance__displacement__total": 2713.62, - "globalroute__design__instance__utilization": 0.569648, - "globalroute__design__instance__utilization__stdcell": 0.569648, - "globalroute__design__io": 165, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 1, - "globalroute__mem__peak": 837836.0, - "globalroute__power__internal__total": 0.0154368, - "globalroute__power__leakage__total": 3.09485e-08, - "globalroute__power__switching__total": 0.00940649, - "globalroute__power__total": 0.0248433, - "globalroute__route__wirelength__estimated": 199856, - "globalroute__runtime__total": "2:10.24", - "globalroute__timing__clock__slack": -1.098, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0484976, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0280601, - "globalroute__timing__drv__setup_violation_count": 148, - "globalroute__timing__setup__tns": -21.9826, - "globalroute__timing__setup__ws": -1.09796, - "placeopt__cpu__total": 10.76, - "placeopt__design__core__area": 137662, - "placeopt__design__die__area": 140475, - "placeopt__design__instance__area": 72379.4, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 72379.4, - "placeopt__design__instance__count": 8462, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 8462, - "placeopt__design__instance__utilization": 0.525776, - "placeopt__design__instance__utilization__stdcell": 0.525776, - "placeopt__design__io": 165, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 644416.0, - "placeopt__power__internal__total": 0.0109792, - "placeopt__power__leakage__total": 2.81786e-08, - "placeopt__power__switching__total": 0.0046629, - "placeopt__power__total": 0.0156422, - "placeopt__runtime__total": "0:11.33", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0213696, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0161156, - "placeopt__timing__drv__setup_violation_count": 341, - "placeopt__timing__setup__tns": -96.7205, - "placeopt__timing__setup__ws": -1.04044, - "run__flow__design": "riscv32i", - "run__flow__generate_date": "2024-10-15 22:35", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16535-g199588e84", - "run__flow__platform": "sky130hd", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "1201bf4a-1b77-4921-a099-abae61057141", - "run__flow__variant": "base", - "synth__cpu__total": 32.5, - "synth__design__instance__area__stdcell": 62541.232, - "synth__design__instance__count__stdcell": 7143.0, - "synth__mem__peak": 65464.0, - "synth__runtime__total": "0:32.69", - "total_time": "0:06:51.270000" -} \ No newline at end of file diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index 39f00d6fbd..ac2c4c89f9 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 71922.42, + "value": 70778.51, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 83236, + "value": 81702, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 9731, + "value": 7314, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 846, + "value": 636, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 846, + "value": 636, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 12, + "value": 20, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 333349, + "value": 301382, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 13, + "value": 18, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.31, + "value": -1.17, "compare": ">=" }, "finish__design__instance__area": { - "value": 90213, + "value": 94909, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 423, + "value": 318, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -30.94, + "value": -28.53, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hd_fakestack/aes/config.mk b/flow/designs/sky130hd_fakestack/aes/config.mk deleted file mode 100644 index e4c679faf2..0000000000 --- a/flow/designs/sky130hd_fakestack/aes/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -export DESIGN_NICKNAME = aes -export DESIGN_NAME = aes_cipher_top -export PLATFORM = sky130hd_fakestack - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export CORE_UTILIZATION = 20 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 - -export PLACE_DENSITY = 0.65 diff --git a/flow/designs/sky130hd_fakestack/aes/constraint.sdc b/flow/designs/sky130hd_fakestack/aes/constraint.sdc deleted file mode 100644 index c98e8f1b4a..0000000000 --- a/flow/designs/sky130hd_fakestack/aes/constraint.sdc +++ /dev/null @@ -1,16 +0,0 @@ -current_design aes_cipher_top - -set clk_name clk -set clk_port_name clk -set clk_period 5.9 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] - diff --git a/flow/designs/sky130hd_fakestack/ariane136/ariane.sdc b/flow/designs/sky130hd_fakestack/ariane136/ariane.sdc deleted file mode 100644 index 147d5a884b..0000000000 --- a/flow/designs/sky130hd_fakestack/ariane136/ariane.sdc +++ /dev/null @@ -1,17 +0,0 @@ -# #################################################################### - -# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Fri Jul 01 20:44:40 PDT 2022 - -# #################################################################### - -set sdc_version 2.0 - -set_units -capacitance 1000fF -set_units -time 1000ps - -# Set the current design -current_design ariane - -create_clock -name "core_clock" -period 8.0 -waveform {0.0 4.0} [get_ports clk_i] -set_clock_gating_check -setup 0.0 -set_wire_load_mode "top" diff --git a/flow/designs/sky130hd_fakestack/ariane136/config.mk b/flow/designs/sky130hd_fakestack/ariane136/config.mk deleted file mode 100644 index 8ab5d099ac..0000000000 --- a/flow/designs/sky130hd_fakestack/ariane136/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -export DESIGN_NICKNAME = ariane136 -export DESIGN_NAME = ariane -export PLATFORM = sky130hd_fakestack - -export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE = 10000 - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram130_256x16.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram130_256x16.lib - -# These values must be multiples of placement site -export DIE_AREA = 0.0 0.0 4600 4600 -export CORE_AREA = 10.07 9.94 4590 4590 -export PLACE_PINS_ARGS = -exclude left:0-2000 -exclude left:3200-4600 -exclude right:* -exclude top:* -exclude bottom:* -# -# RTL_MP Settings -export RTLMP_MAX_INST = 5000 -export RTLMP_MIN_INST = 1000 -export RTLMP_MAX_MACRO = 24 -export RTLMP_MIN_MACRO = 4 - -export GPL_TIMING_DRIVEN = 0 -export GPL_ROUTABILITY_DRIVEN = 0 - -export MACRO_PLACE_HALO = 10 10 - -export PLACE_DENSITY_LB_ADDON ?= 0.20 diff --git a/flow/designs/sky130hd_fakestack/ariane136/constraint.sdc b/flow/designs/sky130hd_fakestack/ariane136/constraint.sdc deleted file mode 100644 index e829cd863e..0000000000 --- a/flow/designs/sky130hd_fakestack/ariane136/constraint.sdc +++ /dev/null @@ -1,14 +0,0 @@ -# #################################################################### - -# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Fri Jul 01 20:44:40 PDT 2022 - -# #################################################################### - -set sdc_version 2.0 - -# Set the current design -current_design ariane - -create_clock -name "core_clock" -period 8.0 -waveform {0.0 4.0} [get_ports clk_i] -set_clock_gating_check -setup 0.0 -set_wire_load_mode "top" diff --git a/flow/designs/sky130hd_fakestack/ariane136/macros.v b/flow/designs/sky130hd_fakestack/ariane136/macros.v deleted file mode 100644 index 73eb1a7622..0000000000 --- a/flow/designs/sky130hd_fakestack/ariane136/macros.v +++ /dev/null @@ -1,146 +0,0 @@ -module SyncSpRamBeNx64_00000008_00000100_0_2 - ( - Clk_CI, - Rst_RBI, - CSel_SI, - WrEn_SI, - BEn_SI, - WrData_DI, - Addr_DI, - RdData_DO - ); - - input [7:0] BEn_SI; // byte-enable: ignore or use as needed - input [63:0] WrData_DI; - input [7:0] Addr_DI; - output [63:0] RdData_DO; - input Clk_CI; - input Rst_RBI; // reset: ignore or use as needed - input CSel_SI; - input WrEn_SI; - wire [63:0] RdData_DO; - wire csel_b,wren_b; - wire [15:0] WMaskIn, NotWMaskIn; - - assign NotWMaskIn = 16'b0; - assign WMaskIn = ~NotWMaskIn; - assign wren_b = ~WrEn_SI; // active-low global-write-enable - assign csel_b = ~CSel_SI; // active-low chip-select-enable - - fakeram130_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0])); - fakeram130_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16])); - fakeram130_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32])); - fakeram130_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48])); - -endmodule // SyncSpRamBeNx64_00000008_00000100_0_2 - -// Google made a mistake in their ariane experiment. -// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro -module limping_SyncSpRamBeNx64_00000008_00000100_0_2 - ( - Clk_CI, - Rst_RBI, - CSel_SI, - WrEn_SI, - BEn_SI, - WrData_DI, - Addr_DI, - RdData_DO - ); - - input [7:0] BEn_SI; // byte-enable: ignore or use as needed - input [63:0] WrData_DI; - input [7:0] Addr_DI; - output [63:0] RdData_DO; - input Clk_CI; - input Rst_RBI; // reset: ignore or use as needed - input CSel_SI; - input WrEn_SI; - wire [63:0] RdData_DO; - wire csel_b,wren_b; - wire [15:0] WMaskIn, NotWMaskIn; - - assign NotWMaskIn = 16'b0; - assign WMaskIn = ~NotWMaskIn; - assign wren_b = ~WrEn_SI; // active-low global-write-enable - assign csel_b = ~CSel_SI; // active-low chip-select-enable - - fakeram130_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0])); - fakeram130_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16])); - fakeram130_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32])); - fakeram130_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48])); - -endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2 - -module SyncSpRamBeNx64_00000008_00000100_0_2_d45 - ( - Clk_CI, - Rst_RBI, - CSel_SI, - WrEn_SI, - BEn_SI, - WrData_DI, - Addr_DI, - RdData_DO - ); - - input [7:0] BEn_SI; // byte-enable: ignore or use as needed - input [44:0] WrData_DI; - input [7:0] Addr_DI; - output [44:0] RdData_DO; - input Clk_CI; - input Rst_RBI; // reset: ignore or use as needed - input CSel_SI; - input WrEn_SI; - wire [47:0] RdData_DO_wire; - wire csel_b,wren_b; - wire [15:0] WMaskIn, NotWMaskIn; - - assign NotWMaskIn = 16'b0; - assign WMaskIn = ~NotWMaskIn; - assign wren_b = ~WrEn_SI; // active-low global-write-enable - assign csel_b = ~CSel_SI; // active-low chip-select-enable - assign RdData_DO = RdData_DO_wire[44:0]; - - fakeram130_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0])); - fakeram130_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16])); - fakeram130_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]})); - -endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45 - -module SyncSpRamBeNx64_00000008_00000100_0_2_d44 - ( - Clk_CI, - Rst_RBI, - CSel_SI, - WrEn_SI, - BEn_SI, - WrData_DI, - Addr_DI, - RdData_DO - ); - - input [7:0] BEn_SI; // byte-enable: ignore or use as needed - input [43:0] WrData_DI; - input [7:0] Addr_DI; - output [43:0] RdData_DO; - input Clk_CI; - input Rst_RBI; // reset: ignore or use as needed - input CSel_SI; - input WrEn_SI; - wire [47:0] RdData_DO_wire; - wire csel_b,wren_b; - wire [15:0] WMaskIn, NotWMaskIn; - - assign NotWMaskIn = 16'b0; - assign WMaskIn = ~NotWMaskIn; - assign wren_b = ~WrEn_SI; // active-low global-write-enable - assign csel_b = ~CSel_SI; // active-low chip-select-enable - assign RdData_DO = RdData_DO_wire[43:0]; - - fakeram130_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0])); - fakeram130_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16])); - fakeram130_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]})); - -endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44 - diff --git a/flow/designs/sky130hd_fakestack/gcd/config.mk b/flow/designs/sky130hd_fakestack/gcd/config.mk deleted file mode 100644 index 4ebdfbc698..0000000000 --- a/flow/designs/sky130hd_fakestack/gcd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -export DESIGN_NAME = gcd -export PLATFORM = sky130hd_fakestack - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -# Adders degrade GCD -export ADDER_MAP_FILE := - -# These values must be multiples of placement site -export DIE_AREA = 0 0 279.96 280.128 -export CORE_AREA = 9.996 10.08 269.964 270.048 diff --git a/flow/designs/sky130hs/aes/config.mk b/flow/designs/sky130hs/aes/config.mk index 78dd2e33a6..4bf78ac5ec 100644 --- a/flow/designs/sky130hs/aes/config.mk +++ b/flow/designs/sky130hs/aes/config.mk @@ -13,3 +13,7 @@ export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 export REMOVE_ABC_BUFFERS = 1 + +export CTS_CLUSTER_SIZE = 10 +export CTS_CLUSTER_DIAMETER = 50 + diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc index 7880c8db2a..5878fa7782 100644 --- a/flow/designs/sky130hs/aes/constraint.sdc +++ b/flow/designs/sky130hs/aes/constraint.sdc @@ -1,15 +1,15 @@ current_design aes_cipher_top -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 4.0 +set clk_period 3.1 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/aes/metadata-base-ok.json b/flow/designs/sky130hs/aes/metadata-base-ok.json deleted file mode 100644 index d203ef10f9..0000000000 --- a/flow/designs/sky130hs/aes/metadata-base-ok.json +++ /dev/null @@ -1,371 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 4.0000" - ], - "cts__clock__skew__hold": 0.0225005, - "cts__clock__skew__setup": 0.0225005, - "cts__cpu__total": 16.76, - "cts__design__core__area": 289510, - "cts__design__die__area": 296404, - "cts__design__instance__area": 174277, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 174277, - "cts__design__instance__count": 15191, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 15191, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.601971, - "cts__design__instance__utilization__stdcell": 0.601971, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 584460.0, - "cts__power__internal__total": 0.598288, - "cts__power__leakage__total": 1.06175e-06, - "cts__power__switching__total": 0.31424, - "cts__power__total": 0.91253, - "cts__route__wirelength__estimated": 415036, - "cts__runtime__total": "0:17.33", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 3, - "cts__timing__drv__max_cap_limit": -0.00379792, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.00917089, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.362832, - "design__io__hpwl": 70393863, - "design__violations": 0, - "detailedplace__cpu__total": 16.55, - "detailedplace__design__core__area": 289510, - "detailedplace__design__die__area": 296404, - "detailedplace__design__instance__area": 171272, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 171272, - "detailedplace__design__instance__count": 15064, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 15064, - "detailedplace__design__instance__displacement__max": 43.793, - "detailedplace__design__instance__displacement__mean": 3.591, - "detailedplace__design__instance__displacement__total": 54099, - "detailedplace__design__instance__utilization": 0.591591, - "detailedplace__design__instance__utilization__stdcell": 0.591591, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 229092.0, - "detailedplace__power__internal__total": 0.594501, - "detailedplace__power__leakage__total": 1.04026e-06, - "detailedplace__power__switching__total": 0.307938, - "detailedplace__power__total": 0.902441, - "detailedplace__route__wirelength__estimated": 426697, - "detailedplace__runtime__total": "0:16.71", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 3, - "detailedplace__timing__drv__max_cap_limit": -0.00969209, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.00603662, - "detailedplace__timing__drv__setup_violation_count": 7, - "detailedplace__timing__setup__tns": -0.405146, - "detailedplace__timing__setup__ws": -0.106771, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 4, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 26195, - "detailedroute__route__drc_errors__iter:10": 387, - "detailedroute__route__drc_errors__iter:11": 197, - "detailedroute__route__drc_errors__iter:12": 175, - "detailedroute__route__drc_errors__iter:13": 134, - "detailedroute__route__drc_errors__iter:14": 94, - "detailedroute__route__drc_errors__iter:15": 93, - "detailedroute__route__drc_errors__iter:16": 69, - "detailedroute__route__drc_errors__iter:17": 48, - "detailedroute__route__drc_errors__iter:18": 48, - "detailedroute__route__drc_errors__iter:19": 4, - "detailedroute__route__drc_errors__iter:2": 17004, - "detailedroute__route__drc_errors__iter:20": 4, - "detailedroute__route__drc_errors__iter:21": 4, - "detailedroute__route__drc_errors__iter:22": 4, - "detailedroute__route__drc_errors__iter:23": 4, - "detailedroute__route__drc_errors__iter:24": 4, - "detailedroute__route__drc_errors__iter:25": 4, - "detailedroute__route__drc_errors__iter:26": 4, - "detailedroute__route__drc_errors__iter:27": 4, - "detailedroute__route__drc_errors__iter:28": 4, - "detailedroute__route__drc_errors__iter:29": 4, - "detailedroute__route__drc_errors__iter:3": 16024, - "detailedroute__route__drc_errors__iter:30": 4, - "detailedroute__route__drc_errors__iter:31": 4, - "detailedroute__route__drc_errors__iter:32": 2, - "detailedroute__route__drc_errors__iter:33": 2, - "detailedroute__route__drc_errors__iter:34": 2, - "detailedroute__route__drc_errors__iter:35": 0, - "detailedroute__route__drc_errors__iter:4": 4464, - "detailedroute__route__drc_errors__iter:5": 1688, - "detailedroute__route__drc_errors__iter:6": 899, - "detailedroute__route__drc_errors__iter:7": 621, - "detailedroute__route__drc_errors__iter:8": 507, - "detailedroute__route__drc_errors__iter:9": 397, - "detailedroute__route__net": 12589, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 114165, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 114165, - "detailedroute__route__wirelength": 551840, - "detailedroute__route__wirelength__iter:1": 560812, - "detailedroute__route__wirelength__iter:10": 551704, - "detailedroute__route__wirelength__iter:11": 551760, - "detailedroute__route__wirelength__iter:12": 551745, - "detailedroute__route__wirelength__iter:13": 551796, - "detailedroute__route__wirelength__iter:14": 551822, - "detailedroute__route__wirelength__iter:15": 551823, - "detailedroute__route__wirelength__iter:16": 551812, - "detailedroute__route__wirelength__iter:17": 551803, - "detailedroute__route__wirelength__iter:18": 551803, - "detailedroute__route__wirelength__iter:19": 551806, - "detailedroute__route__wirelength__iter:2": 556055, - "detailedroute__route__wirelength__iter:20": 551817, - "detailedroute__route__wirelength__iter:21": 551817, - "detailedroute__route__wirelength__iter:22": 551817, - "detailedroute__route__wirelength__iter:23": 551817, - "detailedroute__route__wirelength__iter:24": 551817, - "detailedroute__route__wirelength__iter:25": 551817, - "detailedroute__route__wirelength__iter:26": 551817, - "detailedroute__route__wirelength__iter:27": 551817, - "detailedroute__route__wirelength__iter:28": 551816, - "detailedroute__route__wirelength__iter:29": 551816, - "detailedroute__route__wirelength__iter:3": 554441, - "detailedroute__route__wirelength__iter:30": 551817, - "detailedroute__route__wirelength__iter:31": 551817, - "detailedroute__route__wirelength__iter:32": 551841, - "detailedroute__route__wirelength__iter:33": 551841, - "detailedroute__route__wirelength__iter:34": 551841, - "detailedroute__route__wirelength__iter:35": 551840, - "detailedroute__route__wirelength__iter:4": 552590, - "detailedroute__route__wirelength__iter:5": 552064, - "detailedroute__route__wirelength__iter:6": 551886, - "detailedroute__route__wirelength__iter:7": 551828, - "detailedroute__route__wirelength__iter:8": 551721, - "detailedroute__route__wirelength__iter:9": 551712, - "finish__clock__skew__hold": 0.0943552, - "finish__clock__skew__setup": 0.0943552, - "finish__cpu__total": 29.99, - "finish__design__core__area": 289510, - "finish__design__die__area": 296404, - "finish__design__instance__area": 174958, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 174958, - "finish__design__instance__count": 15234, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 15234, - "finish__design__instance__utilization": 0.604323, - "finish__design__instance__utilization__stdcell": 0.604323, - "finish__design__io": 388, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.78929, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00955371, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.0208105, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0198163, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.77919, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0198163, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 492076.0, - "finish__power__internal__total": 0.603359, - "finish__power__leakage__total": 1.06533e-06, - "finish__power__switching__total": 0.357019, - "finish__power__total": 0.960379, - "finish__runtime__total": "0:30.41", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 7, - "finish__timing__drv__max_cap_limit": -0.0225679, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 31, - "finish__timing__drv__max_slew_limit": -0.00420541, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.0724332, - "finish__timing__wns_percent_delay": 1.674221, - "finish_merge__cpu__total": 2.79, - "finish_merge__mem__peak": 504860.0, - "finish_merge__runtime__total": "0:03.13", - "floorplan__cpu__total": 6.5, - "floorplan__design__core__area": 289510, - "floorplan__design__die__area": 296404, - "floorplan__design__instance__area": 107802, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 107802, - "floorplan__design__instance__count": 11335, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 11335, - "floorplan__design__instance__utilization": 0.372362, - "floorplan__design__instance__utilization__stdcell": 0.372362, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 209344.0, - "floorplan__power__internal__total": 0.416622, - "floorplan__power__leakage__total": 9.47355e-07, - "floorplan__power__switching__total": 0.140996, - "floorplan__power__total": 0.557619, - "floorplan__runtime__total": "0:06.69", - "floorplan__timing__setup__tns": -409.243, - "floorplan__timing__setup__ws": -3.76844, - "floorplan_io__cpu__total": 1.71, - "floorplan_io__mem__peak": 175196.0, - "floorplan_io__runtime__total": "0:01.83", - "floorplan_macro__cpu__total": 1.74, - "floorplan_macro__mem__peak": 174768.0, - "floorplan_macro__runtime__total": "0:01.82", - "floorplan_pdn__cpu__total": 2.03, - "floorplan_pdn__mem__peak": 179704.0, - "floorplan_pdn__runtime__total": "0:02.17", - "floorplan_tap__cpu__total": 1.77, - "floorplan_tap__mem__peak": 168572.0, - "floorplan_tap__runtime__total": "0:01.86", - "floorplan_tdms__cpu__total": 1.78, - "floorplan_tdms__mem__peak": 175092.0, - "floorplan_tdms__runtime__total": "0:01.87", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 827.34, - "globalplace__design__core__area": 289510, - "globalplace__design__die__area": 296404, - "globalplace__design__instance__area": 112753, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 112753, - "globalplace__design__instance__count": 14432, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 14432, - "globalplace__design__instance__utilization": 0.38946, - "globalplace__design__instance__utilization__stdcell": 0.38946, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 616380.0, - "globalplace__power__internal__total": 0.471694, - "globalplace__power__leakage__total": 9.47355e-07, - "globalplace__power__switching__total": 0.225203, - "globalplace__power__total": 0.696898, - "globalplace__runtime__total": "1:32.86", - "globalplace__timing__setup__tns": -1043.76, - "globalplace__timing__setup__ws": -8.32616, - "globalplace_io__cpu__total": 1.77, - "globalplace_io__mem__peak": 178688.0, - "globalplace_io__runtime__total": "0:01.86", - "globalplace_skip_io__cpu__total": 172.81, - "globalplace_skip_io__mem__peak": 197980.0, - "globalplace_skip_io__runtime__total": "0:07.32", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 22, - "globalroute__clock__skew__hold": 0.0685167, - "globalroute__clock__skew__setup": 0.0685167, - "globalroute__cpu__total": 140.25, - "globalroute__design__core__area": 289510, - "globalroute__design__die__area": 296404, - "globalroute__design__instance__area": 174945, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 174945, - "globalroute__design__instance__count": 15230, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 15230, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.604279, - "globalroute__design__instance__utilization__stdcell": 0.604279, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 730036.0, - "globalroute__power__internal__total": 0.603023, - "globalroute__power__leakage__total": 1.06533e-06, - "globalroute__power__switching__total": 0.374408, - "globalroute__power__total": 0.977432, - "globalroute__route__wirelength__estimated": 419153, - "globalroute__runtime__total": "0:28.80", - "globalroute__timing__clock__slack": 0.077, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.00192235, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0136364, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.0772635, - "placeopt__cpu__total": 16.82, - "placeopt__design__core__area": 289510, - "placeopt__design__die__area": 296404, - "placeopt__design__instance__area": 171272, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 171272, - "placeopt__design__instance__count": 15064, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 15064, - "placeopt__design__instance__utilization": 0.591591, - "placeopt__design__instance__utilization__stdcell": 0.591591, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 490264.0, - "placeopt__power__internal__total": 0.594195, - "placeopt__power__leakage__total": 1.04026e-06, - "placeopt__power__switching__total": 0.304474, - "placeopt__power__total": 0.89867, - "placeopt__runtime__total": "0:17.22", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0022883, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0118742, - "placeopt__timing__drv__setup_violation_count": 7, - "placeopt__timing__setup__tns": -0.337419, - "placeopt__timing__setup__ws": -0.0819127, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-09-28 20:07", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-16113-g7b5c8faf7", - "run__flow__platform": "sky130hs", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "ada9017a-5f67-4736-98e5-2db65adec284", - "run__flow__variant": "base", - "synth__cpu__total": 55.31, - "synth__design__instance__area__stdcell": 116825.4576, - "synth__design__instance__count__stdcell": 12708.0, - "synth__mem__peak": 142592.0, - "synth__runtime__total": "0:55.68", - "total_time": "0:04:47.560000" -} \ No newline at end of file diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json index 5a72f62cbc..27ade127bb 100644 --- a/flow/designs/sky130hs/aes/rules-base.json +++ b/flow/designs/sky130hs/aes/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 182308, + "value": 176428, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 17278, + "value": 17153, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1502, + "value": 1492, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1502, + "value": 1492, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 25, + "value": 182, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 613182, + "value": 722796, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 54, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.11, + "value": -0.18, "compare": ">=" }, "finish__design__instance__area": { - "value": 186844, + "value": 184400, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 751, + "value": 746, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/coyote_tc/config.mk b/flow/designs/sky130hs/coyote_tc/config.mk deleted file mode 100644 index bb141adccf..0000000000 --- a/flow/designs/sky130hs/coyote_tc/config.mk +++ /dev/null @@ -1,76 +0,0 @@ -export DESIGN_NICKNAME = coyote_tc -export DESIGN_NAME = coyote_tc - -export PLATFORM = sky130hs -# Clone Skywater library: -# git clone git@github.com:google/skywater-pdk.git --recursive -# - -export SKY130_IO_VERSION ?= v0.2.0 -export OPENRAMS_DIR = ./platforms/sky130ram -export IO_DIR = ./platforms/sky130io - -export VERILOG_FILES = $(DESIGN_HOME)/src/coyote_tc/coyote_tc.v \ - $(DESIGN_HOME)/src/coyote/coyote.sv2v.v \ - $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/ios.v \ - $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/macros.v \ - $(IO_DIR)/verilog/sky130_io.blackbox.v - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/constraint.sdc - -export FOOTPRINT_LIBRARY = $(IO_DIR)/library.sky130_fd_io.tcl -export FOOTPRINT = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.package.strategy -export SIG_MAP_FILE = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/coyote_tc.sigmap - -export ADDITIONAL_LIBS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_TT_1p8V_25C.lib \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_TT_1p8V_25C.lib \ - $(IO_DIR)/lib/sky130_dummy_io.lib - -export ADDITIONAL_GDS = $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds - -export ADDITIONAL_LEFS = $(IO_DIR)/lef/sky130_ef_io__gpiov2_pad_wrapped.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_10um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_1um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_20um.lef \ - $(IO_DIR)/lef/sky130_ef_io__com_bus_slice_5um.lef \ - $(IO_DIR)/lef/sky130_ef_io__corner_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vccd_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vccd_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vdda_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vdda_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vddio_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vddio_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssa_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssa_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssd_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssd_lvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssio_hvc_pad.lef \ - $(IO_DIR)/lef/sky130_ef_io__vssio_lvc_pad.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef \ - $(OPENRAMS_DIR)/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef \ - - -# These values must be multiples of placement site -export DIE_AREA = 0.0 0.0 5200 4609.14 -export CORE_AREA = 210 210 4990 4389.14 - -export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1 -export ABC_LOAD_IN_FF = 3 - -export POST_SYNTHESYS_RENAMING = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/post_synthesis_rename.tcl - -# Use custom power grid with core rings offset from the pads -export PDN_CFG = $(DESIGN_HOME)/$(PLATFORM)/coyote_tc/pdn.cfg - -# Point to the RC file -export SETRC_FILE = $(PLATFORM_DIR)/setRC.tcl - -export FASTROUTE_TCL $(PLATFORM_DIR)/fastroute.tcl - diff --git a/flow/designs/sky130hs/coyote_tc/constraint.sdc b/flow/designs/sky130hs/coyote_tc/constraint.sdc deleted file mode 100644 index ba86e07344..0000000000 --- a/flow/designs/sky130hs/coyote_tc/constraint.sdc +++ /dev/null @@ -1,471 +0,0 @@ - -set_max_fanout 10 [current_design] -set_max_transition 0.5 [current_design] -# set_dont_touch [get_ports *] -set_load -pin_load 3 [get_ports rocc_cmd_v_o] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_15}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_14}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_13}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_12}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_11}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_10}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_9}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_8}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_7}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_6}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_5}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_4}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_3}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_2}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_1}] -set_load -pin_load 3 [get_ports {rocc_cmd_data_o_0}] -set_load -pin_load 3 [get_ports rocc_resp_ready_o] -set_load -pin_load 3 [get_ports rocc_mem_req_ready_o] -set_load -pin_load 3 [get_ports rocc_mem_resp_v_o] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_63}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_62}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_61}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_60}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_59}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_58}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_57}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_56}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_55}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_54}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_53}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_52}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_51}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_50}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_49}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_48}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_47}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_46}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_45}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_44}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_43}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_42}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_41}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_40}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_39}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_38}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_37}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_36}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_35}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_34}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_33}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_32}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_31}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_30}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_29}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_28}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_27}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_26}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_25}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_24}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_23}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_22}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_21}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_20}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_19}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_18}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_17}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_16}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_15}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_14}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_13}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_12}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_11}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_10}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_9}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_8}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_7}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_6}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_5}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_4}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_3}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_2}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_1}] -set_load -pin_load 3 [get_ports {rocc_mem_resp_data_o_0}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_7}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_6}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_5}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_4}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_3}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_2}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_1}] -set_load -pin_load 3 [get_ports {fsb_node_data_o_0}] -set_max_transition 0.069 [get_ports rocc_cmd_v_o] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_15}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_14}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_13}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_12}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_11}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_10}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_9}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_8}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_7}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_6}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_5}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_4}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_3}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_2}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_1}] -set_max_transition 0.069 [get_ports {rocc_cmd_data_o_0}] -set_max_transition 0.069 [get_ports rocc_resp_ready_o] -set_max_transition 0.069 [get_ports rocc_mem_req_ready_o] -set_max_transition 0.069 [get_ports rocc_mem_resp_v_o] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_63}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_62}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_61}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_60}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_59}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_58}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_57}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_56}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_55}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_54}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_53}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_52}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_51}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_50}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_49}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_48}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_47}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_46}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_45}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_44}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_43}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_42}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_41}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_40}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_39}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_38}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_37}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_36}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_35}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_34}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_33}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_32}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_31}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_30}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_29}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_28}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_27}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_26}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_25}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_24}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_23}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_22}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_21}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_20}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_19}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_18}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_17}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_16}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_15}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_14}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_13}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_12}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_11}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_10}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_9}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_8}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_7}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_6}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_5}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_4}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_3}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_2}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_1}] -set_max_transition 0.069 [get_ports {rocc_mem_resp_data_o_0}] -set_max_transition 0.069 [get_ports rocc_ctrl_o_s_] -set_max_transition 0.069 [get_ports rocc_ctrl_o_exception_] -set_max_transition 0.069 [get_ports rocc_ctrl_o_host_id_] -set_max_transition 0.069 [get_ports fsb_node_ready_o] -set_max_transition 0.069 [get_ports fsb_node_v_o] -set_max_transition 0.069 [get_ports {fsb_node_data_o_7}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_6}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_5}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_4}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_3}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_2}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_1}] -set_max_transition 0.069 [get_ports {fsb_node_data_o_0}] -create_clock [get_pins u_clk.u_in/IN] -name core_clk -period 50 -waveform {0 2.5} -set_clock_latency -source 0 [get_clocks core_clk] -set_clock_uncertainty 0.03 [get_clocks core_clk] -set_clock_transition -min -fall 0.069 [get_clocks core_clk] -set_clock_transition -min -rise 0.069 [get_clocks core_clk] -set_clock_transition -max -fall 0.069 [get_clocks core_clk] -set_clock_transition -max -rise 0.069 [get_clocks core_clk] -set_false_path -to [list [get_ports rocc_ctrl_o_s_] [get_ports rocc_ctrl_o_exception_] [get_ports rocc_ctrl_o_host_id_]] -set_input_delay -clock core_clk 2.51 [get_ports rocc_cmd_ready_i] -set_input_delay -clock core_clk 2.51 [get_ports rocc_resp_v_i] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[7]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[6]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[5]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[4]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[3]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[2]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[1]}] -set_input_delay -clock core_clk 2.51 [get_ports {rocc_resp_data_i[0]}] -set_input_delay -clock core_clk 3.01 [get_ports rocc_mem_req_v_i] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay -clock core_clk 2.76 [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay -clock core_clk 2.76 [get_ports rocc_ctrl_i_busy_] -set_input_delay -clock core_clk 2.76 [get_ports rocc_ctrl_i_interrupt_] -set_input_delay -clock core_clk 2.51 [get_ports fsb_node_v_i] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[7]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[6]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[5]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[4]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[3]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[2]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[1]}] -set_input_delay -clock core_clk 2.51 [get_ports {fsb_node_data_i[0]}] -set_input_delay -clock core_clk 3.01 [get_ports fsb_node_yumi_i] -set_input_delay -clock core_clk 2.51 [get_ports reset_i] -set_input_delay -clock core_clk 2.51 [get_ports en_i] -set_output_delay -clock core_clk 2.51 [get_ports rocc_cmd_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_15}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_14}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_13}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_12}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_11}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_10}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_9}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_8}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_cmd_data_o_0}] -set_output_delay -clock core_clk 2.76 [get_ports rocc_mem_req_ready_o] -set_output_delay -clock core_clk 2.51 [get_ports rocc_mem_resp_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_63}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_62}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_61}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_60}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_59}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_58}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_57}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_56}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_55}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_54}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_53}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_52}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_51}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_50}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_49}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_48}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_47}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_46}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_45}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_44}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_43}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_42}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_41}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_40}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_39}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_38}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_37}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_36}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_35}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_34}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_33}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_32}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_31}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_30}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_29}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_28}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_27}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_26}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_25}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_24}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_23}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_22}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_21}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_20}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_19}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_18}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_17}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_16}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_15}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_14}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_13}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_12}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_11}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_10}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_9}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_8}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {rocc_mem_resp_data_o_0}] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_s_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_exception_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_ctrl_o_host_id_] -set_output_delay -clock core_clk 2.51 [get_ports rocc_resp_ready_o] -set_output_delay -clock core_clk 2.51 [get_ports fsb_node_ready_o] -set_output_delay -clock core_clk 3.01 [get_ports fsb_node_v_o] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_7}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_6}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_5}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_4}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_3}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_2}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_1}] -set_output_delay -clock core_clk 2.51 [get_ports {fsb_node_data_o_0}] -set_input_transition -max 0.069 [get_ports clk_i] -set_input_transition -min 0.069 [get_ports clk_i] -set_input_transition -max 0.069 [get_ports reset_i] -set_input_transition -min 0.069 [get_ports reset_i] -set_input_transition -max 0.069 [get_ports en_i] -set_input_transition -min 0.069 [get_ports en_i] -set_input_transition -max 0.069 [get_ports rocc_cmd_ready_i] -set_input_transition -min 0.069 [get_ports rocc_cmd_ready_i] -set_input_transition -max 0.069 [get_ports rocc_resp_v_i] -set_input_transition -min 0.069 [get_ports rocc_resp_v_i] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[7]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[7]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[6]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[6]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[5]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[5]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[4]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[4]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[3]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[3]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[2]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[2]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[1]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[1]}] -set_input_transition -max 0.069 [get_ports {rocc_resp_data_i[0]}] -set_input_transition -min 0.069 [get_ports {rocc_resp_data_i[0]}] -set_input_transition -max 0.069 [get_ports rocc_mem_req_v_i] -set_input_transition -min 0.069 [get_ports rocc_mem_req_v_i] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition -max 0.069 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition -min 0.069 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition -max 0.069 [get_ports rocc_ctrl_i_busy_] -set_input_transition -min 0.069 [get_ports rocc_ctrl_i_busy_] -set_input_transition -max 0.069 [get_ports rocc_ctrl_i_interrupt_] -set_input_transition -min 0.069 [get_ports rocc_ctrl_i_interrupt_] -set_input_transition -max 0.069 [get_ports fsb_node_v_i] -set_input_transition -min 0.069 [get_ports fsb_node_v_i] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[7]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[7]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[6]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[6]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[5]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[5]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[4]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[4]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[3]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[3]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[2]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[2]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[1]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[1]}] -set_input_transition -max 0.069 [get_ports {fsb_node_data_i[0]}] -set_input_transition -min 0.069 [get_ports {fsb_node_data_i[0]}] -set_input_transition -max 0.069 [get_ports fsb_node_yumi_i] -set_input_transition -min 0.069 [get_ports fsb_node_yumi_i] diff --git a/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy b/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy deleted file mode 100644 index c62df62d7e..0000000000 --- a/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy +++ /dev/null @@ -1,247 +0,0 @@ -puts "Loading library IO cell meta-data" -source $::env(FOOTPRINT_LIBRARY) - -puts "Loaded library IO cell data" -Footprint definition { - Type Wirebond - - die_area {0 0 5200.000 4599.140} - core_area {210.0 210.00 4990.0 4389.14} - - power_nets "VDD VDDIO" - ground_nets "VSS VSSIO" - - offsets 0 - tracks platforms/sky130/tracks_hs.info - pin_layer met5 - - pad_inst_name "u_%s" - pad_pin_name "%s" - - padcell { - sig0 {type sig cell {origin {x 280.000 y 210.965}}} - sig1 {type sig cell {origin {x 360.000 y 210.965}}} - vzz_0 {type vssio_hvc cell {origin {x 440.000 y 197.965}}} - v18_0 {type vddio_hvc cell {origin {x 520.000 y 197.965}}} - sig2 {type sig cell {origin {x 600.000 y 210.965}}} - sig3 {type sig cell {origin {x 680.000 y 210.965}}} - sig4 {type sig cell {origin {x 760.000 y 210.965}}} - sig5 {type sig cell {origin {x 840.000 y 210.965}}} - sig6 {type sig cell {origin {x 920.000 y 210.965}}} - sig7 {type sig cell {origin {x 1000.000 y 210.965}}} - sig8 {type sig cell {origin {x 1080.000 y 210.965}}} - sig9 {type sig cell {origin {x 1160.000 y 210.965}}} - vzz_1 {type vssio_hvc cell {origin {x 1240.000 y 197.965}}} - v18_1 {type vddio_hvc cell {origin {x 1320.000 y 197.965}}} - sig10 {type sig cell {origin {x 1400.000 y 210.965}}} - sig11 {type sig cell {origin {x 1480.000 y 210.965}}} - sig12 {type sig cell {origin {x 1560.000 y 210.965}}} - vss_0 {type vssd_hvc cell {origin {x 1640.000 y 197.965}}} - vdd_0 {type vccd_hvc cell {origin {x 1720.000 y 197.965}}} - sig13 {type sig cell {origin {x 1800.000 y 210.965}}} - sig14 {type sig cell {origin {x 1880.000 y 210.965}}} - sig15 {type sig cell {origin {x 1960.000 y 210.965}}} - sig16 {type sig cell {origin {x 2040.000 y 210.965}}} - sig17 {type sig cell {origin {x 2120.000 y 210.965}}} - vzz_2 {type vssio_hvc cell {origin {x 2200.000 y 197.965}}} - v18_2 {type vddio_hvc cell {origin {x 2280.000 y 197.965}}} - sig18 {type sig cell {origin {x 2360.000 y 210.965}}} - sig19 {type sig cell {origin {x 2440.000 y 210.965}}} - sig20 {type sig cell {origin {x 2520.000 y 210.965}}} - sig21 {type sig cell {origin {x 2600.000 y 210.965}}} - sig22 {type sig cell {origin {x 2680.000 y 210.965}}} - sig23 {type sig cell {origin {x 2760.000 y 210.965}}} - sig24 {type sig cell {origin {x 2840.000 y 210.965}}} - sig25 {type sig cell {origin {x 2920.000 y 210.965}}} - vzz_3 {type vssio_hvc cell {origin {x 3000.000 y 197.965}}} - v18_3 {type vddio_hvc cell {origin {x 3080.000 y 197.965}}} - sig26 {type sig cell {origin {x 3160.000 y 210.965}}} - sig27 {type sig cell {origin {x 3240.000 y 210.965}}} - sig28 {type sig cell {origin {x 3320.000 y 210.965}}} - sig29 {type sig cell {origin {x 3400.000 y 210.965}}} - sig30 {type sig cell {origin {x 3480.000 y 210.965}}} - vss_1 {type vssd_hvc cell {origin {x 3560.000 y 197.965}}} - vdd_1 {type vccd_hvc cell {origin {x 3640.000 y 197.965}}} - sig31 {type sig cell {origin {x 3720.000 y 210.965}}} - sig32 {type sig cell {origin {x 3800.000 y 210.965}}} - sig33 {type sig cell {origin {x 3880.000 y 210.965}}} - vzz_4 {type vssio_hvc cell {origin {x 3960.000 y 197.965}}} - v18_4 {type vddio_hvc cell {origin {x 4040.000 y 197.965}}} - sig34 {type sig cell {origin {x 4120.000 y 210.965}}} - sig35 {type sig cell {origin {x 4200.000 y 210.965}}} - sig36 {type sig cell {origin {x 4280.000 y 210.965}}} - sig37 {type sig cell {origin {x 4360.000 y 210.965}}} - sig38 {type sig cell {origin {x 4440.000 y 210.965}}} - sig39 {type sig cell {origin {x 4520.000 y 210.965}}} - sig40 {type sig cell {origin {x 4600.000 y 210.965}}} - sig41 {type sig cell {origin {x 4680.000 y 210.965}}} - vzz_5 {type vssio_hvc cell {origin {x 4760.000 y 197.965}}} - v18_5 {type vddio_hvc cell {origin {x 4840.000 y 197.965}}} - sig42 {type sig cell {origin {x 4920.000 y 210.965}}} - sig43 {type sig cell {origin {x 5000.000 y 210.965}} side bottom} - sig44 {type sig cell {origin {x 4989.035 y 294.000}}} - sig45 {type sig cell {origin {x 4989.035 y 374.000}}} - sig46 {type sig cell {origin {x 4989.035 y 454.000}}} - sig47 {type sig cell {origin {x 4989.035 y 534.000}}} - vzz_6 {type vssio_hvc cell {origin {x 5002.035 y 614.000}}} - v18_6 {type vddio_hvc cell {origin {x 5002.035 y 694.000}}} - vss_2 {type vssd_hvc cell {origin {x 5002.035 y 774.000}}} - vdd_2 {type vccd_hvc cell {origin {x 5002.035 y 854.000}}} - sig48 {type sig cell {origin {x 4989.035 y 934.000}}} - sig49 {type sig cell {origin {x 4989.035 y 1014.000}}} - sig50 {type sig cell {origin {x 4989.035 y 1094.000}}} - sig51 {type sig cell {origin {x 4989.035 y 1174.000}}} - sig52 {type sig cell {origin {x 4989.035 y 1254.000}}} - sig53 {type sig cell {origin {x 4989.035 y 1334.000}}} - sig54 {type sig cell {origin {x 4989.035 y 1414.000}}} - sig55 {type sig cell {origin {x 4989.035 y 1494.000}}} - vzz_7 {type vssio_hvc cell {origin {x 5002.035 y 1574.000}}} - v18_7 {type vddio_hvc cell {origin {x 5002.035 y 1654.000}}} - sig56 {type sig cell {origin {x 4989.035 y 1734.000}}} - sig57 {type sig cell {origin {x 4989.035 y 1814.000}}} - sig58 {type sig cell {origin {x 4989.035 y 1894.000}}} - sig59 {type sig cell {origin {x 4989.035 y 1974.000}}} - sig60 {type sig cell {origin {x 4989.035 y 2054.000}}} - sig61 {type sig cell {origin {x 4989.035 y 2134.000}}} - sig62 {type sig cell {origin {x 4989.035 y 2214.000}}} - sig63 {type sig cell {origin {x 4989.035 y 2294.000}}} - vzz_8 {type vssio_hvc cell {origin {x 5002.035 y 2374.000}}} - v18_8 {type vddio_hvc cell {origin {x 5002.035 y 2454.000}}} - sig64 {type sig cell {origin {x 4989.035 y 2534.000}}} - sig65 {type sig cell {origin {x 4989.035 y 2614.000}}} - sig66 {type sig cell {origin {x 4989.035 y 2694.000}}} - vss_3 {type vssd_hvc cell {origin {x 5002.035 y 2774.000}}} - vdd_3 {type vccd_hvc cell {origin {x 5002.035 y 2854.000}}} - sig67 {type sig cell {origin {x 4989.035 y 2934.000}}} - sig68 {type sig cell {origin {x 4989.035 y 3014.000}}} - sig69 {type sig cell {origin {x 4989.035 y 3094.000}}} - sig70 {type sig cell {origin {x 4989.035 y 3174.000}}} - sig71 {type sig cell {origin {x 4989.035 y 3254.000}}} - vzz_9 {type vssio_hvc cell {origin {x 5002.035 y 3334.000}}} - v18_9 {type vddio_hvc cell {origin {x 5002.035 y 3414.000}}} - sig72 {type sig cell {origin {x 4989.035 y 3494.000}}} - sig73 {type sig cell {origin {x 4989.035 y 3574.000}}} - sig74 {type sig cell {origin {x 4989.035 y 3654.000}}} - sig75 {type sig cell {origin {x 4989.035 y 3734.000}}} - sig76 {type sig cell {origin {x 4989.035 y 3814.000}}} - sig77 {type sig cell {origin {x 4989.035 y 3894.000}}} - sig78 {type sig cell {origin {x 4989.035 y 3974.000}}} - sig79 {type sig cell {origin {x 4989.035 y 4054.000}}} - vzz_10 {type vssio_hvc cell {origin {x 5002.035 y 4134.000}}} - v18_10 {type vddio_hvc cell {origin {x 5002.035 y 4214.000}}} - sig80 {type sig cell {origin {x 4989.035 y 4294.000}}} - sig81 {type sig cell {origin {x 4989.035 y 4374.000}}} - sig82 {type sig cell {origin {x 4920.000 y 4388.175}}} - sig83 {type sig cell {origin {x 4840.000 y 4388.175}}} - sig84 {type sig cell {origin {x 4760.000 y 4388.175}}} - sig85 {type sig cell {origin {x 4680.000 y 4388.175}}} - vss_4 {type vssd_hvc cell {origin {x 4600.000 y 4401.175}}} - vdd_4 {type vccd_hvc cell {origin {x 4520.000 y 4401.175}}} - sig86 {type sig cell {origin {x 4440.000 y 4388.175}}} - sig87 {type sig cell {origin {x 4360.000 y 4388.175}}} - vzz_11 {type vssio_hvc cell {origin {x 4280.000 y 4401.175}}} - v18_11 {type vddio_hvc cell {origin {x 4200.000 y 4401.175}}} - sig88 {type sig cell {origin {x 4120.000 y 4388.175}}} - sig89 {type sig cell {origin {x 4040.000 y 4388.175}}} - sig90 {type sig cell {origin {x 3960.000 y 4388.175}}} - sig91 {type sig cell {origin {x 3880.000 y 4388.175}}} - sig92 {type sig cell {origin {x 3800.000 y 4388.175}}} - sig93 {type sig cell {origin {x 3720.000 y 4388.175}}} - sig94 {type sig cell {origin {x 3640.000 y 4388.175}}} - sig95 {type sig cell {origin {x 3560.000 y 4388.175}}} - vzz_12 {type vssio_hvc cell {origin {x 3480.000 y 4401.175}}} - v18_12 {type vddio_hvc cell {origin {x 3400.000 y 4401.175}}} - sig96 {type sig cell {origin {x 3320.000 y 4388.175}}} - sig97 {type sig cell {origin {x 3240.000 y 4388.175}}} - sig98 {type sig cell {origin {x 3160.000 y 4388.175}}} - sig99 {type sig cell {origin {x 3080.000 y 4388.175}}} - sig100 {type sig cell {origin {x 3000.000 y 4388.175}}} - sig101 {type sig cell {origin {x 2920.000 y 4388.175}}} - sig102 {type sig cell {origin {x 2840.000 y 4388.175}}} - sig103 {type sig cell {origin {x 2760.000 y 4388.175}}} - vzz_13 {type vssio_hvc cell {origin {x 2680.000 y 4401.175}}} - v18_13 {type vddio_hvc cell {origin {x 2600.000 y 4401.175}}} - vss_5 {type vssd_hvc cell {origin {x 2520.000 y 4401.175}}} - vdd_5 {type vccd_hvc cell {origin {x 2440.000 y 4401.175}}} - sig104 {type sig cell {origin {x 2360.000 y 4388.175}}} - sig105 {type sig cell {origin {x 2280.000 y 4388.175}}} - sig106 {type sig cell {origin {x 2200.000 y 4388.175}}} - sig107 {type sig cell {origin {x 2120.000 y 4388.175}}} - sig108 {type sig cell {origin {x 2040.000 y 4388.175}}} - sig109 {type sig cell {origin {x 1960.000 y 4388.175}}} - sig110 {type sig cell {origin {x 1880.000 y 4388.175}}} - sig111 {type sig cell {origin {x 1800.000 y 4388.175}}} - vzz_14 {type vssio_hvc cell {origin {x 1720.000 y 4401.175}}} - v18_14 {type vddio_hvc cell {origin {x 1640.000 y 4401.175}}} - sig112 {type sig cell {origin {x 1560.000 y 4388.175}}} - sig113 {type sig cell {origin {x 1480.000 y 4388.175}}} - sig114 {type sig cell {origin {x 1400.000 y 4388.175}}} - sig115 {type sig cell {origin {x 1320.000 y 4388.175}}} - sig116 {type sig cell {origin {x 1240.000 y 4388.175}}} - sig117 {type sig cell {origin {x 1160.000 y 4388.175}}} - sig118 {type sig cell {origin {x 1080.000 y 4388.175}}} - sig119 {type sig cell {origin {x 1000.000 y 4388.175}}} - vzz_15 {type vssio_hvc cell {origin {x 920.000 y 4401.175}}} - v18_15 {type vddio_hvc cell {origin {x 840.000 y 4401.175}}} - sig120 {type sig cell {origin {x 760.000 y 4388.175}}} - sig121 {type sig cell {origin {x 680.000 y 4388.175}}} - vdd_6 {type vssd_hvc cell {origin {x 600.000 y 4401.175}}} - vss_6 {type vccd_hvc cell {origin {x 520.000 y 4401.175}}} - sig122 {type sig cell {origin {x 440.000 y 4388.175}}} - sig123 {type sig cell {origin {x 360.000 y 4388.175}}} - sig124 {type sig cell {origin {x 280.000 y 4388.175}}} - sig125 {type sig cell {origin {x 200.000 y 4388.175}} side top} - sig126 {type sig cell {origin {x 210.965 y 4300.000}}} - sig127 {type sig cell {origin {x 210.965 y 4220.000}}} - vzz_16 {type vssio_hvc cell {origin {x 197.965 y 4140.000}}} - v18_16 {type vddio_hvc cell {origin {x 197.965 y 4060.000}}} - sig128 {type sig cell {origin {x 210.965 y 3980.000}}} - sig129 {type sig cell {origin {x 210.965 y 3900.000}}} - sig130 {type sig cell {origin {x 210.965 y 3820.000}}} - sig131 {type sig cell {origin {x 210.965 y 3740.000}}} - sig132 {type sig cell {origin {x 210.965 y 3660.000}}} - sig133 {type sig cell {origin {x 210.965 y 3580.000}}} - sig134 {type sig cell {origin {x 210.965 y 3500.000}}} - sig135 {type sig cell {origin {x 210.965 y 3420.000}}} - vzz_17 {type vssio_hvc cell {origin {x 197.965 y 3340.000}}} - v18_17 {type vddio_hvc cell {origin {x 197.965 y 3260.000}}} - sig136 {type sig cell {origin {x 210.965 y 3180.000}}} - sig137 {type sig cell {origin {x 210.965 y 3100.000}}} - sig138 {type sig cell {origin {x 210.965 y 3020.000}}} - sig139 {type sig cell {origin {x 210.965 y 2940.000}}} - sig140 {type sig cell {origin {x 210.965 y 2860.000}}} - sig141 {type sig cell {origin {x 210.965 y 2780.000}}} - vss_7 {type vssd_hvc cell {origin {x 197.965 y 2700.000}}} - vdd_7 {type vccd_hvc cell {origin {x 197.965 y 2620.000}}} - sig142 {type sig cell {origin {x 210.965 y 2540.000}}} - sig143 {type sig cell {origin {x 210.965 y 2460.000}}} - vzz_18 {type vssio_hvc cell {origin {x 197.965 y 2380.000}}} - v18_18 {type vddio_hvc cell {origin {x 197.965 y 2300.000}}} - sig144 {type sig cell {origin {x 210.965 y 2220.000}}} - sig145 {type sig cell {origin {x 210.965 y 2140.000}}} - sig146 {type sig cell {origin {x 210.965 y 2060.000}}} - sig147 {type sig cell {origin {x 210.965 y 1980.000}}} - sig148 {type sig cell {origin {x 210.965 y 1900.000}}} - sig149 {type sig cell {origin {x 210.965 y 1820.000}}} - sig150 {type sig cell {origin {x 210.965 y 1740.000}}} - sig151 {type sig cell {origin {x 210.965 y 1660.000}}} - vzz_19 {type vssio_hvc cell {origin {x 197.965 y 1580.000}}} - v18_19 {type vddio_hvc cell {origin {x 197.965 y 1500.000}}} - sig152 {type sig cell {origin {x 210.965 y 1420.000}}} - sig153 {type sig cell {origin {x 210.965 y 1340.000}}} - sig154 {type sig cell {origin {x 210.965 y 1260.000}}} - sig155 {type sig cell {origin {x 210.965 y 1180.000}}} - sig156 {type sig cell {origin {x 210.965 y 1100.000}}} - sig157 {type sig cell {origin {x 210.965 y 1020.000}}} - sig158 {type sig cell {origin {x 210.965 y 940.000}}} - sig159 {type sig cell {origin {x 210.965 y 860.000}}} - vdd_8 {type vccd_hvc cell {origin {x 197.965 y 780.000}}} - vss_8 {type vssd_hvc cell {origin {x 197.965 y 700.000}}} - vzz_20 {type vssio_hvc cell {origin {x 197.965 y 620.000}}} - v18_20 {type vddio_hvc cell {origin {x 197.965 y 540.000}}} - sig160 {type sig cell {origin {x 210.965 y 460.000}}} - sig161 {type sig cell {origin {x 210.965 y 380.000}}} - sig162 {type sig cell {origin {x 210.965 y 300.000}}} - sig163 {type sig cell {origin {x 210.965 y 220.000}}} - } -} diff --git a/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy.orig b/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy.orig deleted file mode 100644 index 0f96397cb3..0000000000 --- a/flow/designs/sky130hs/coyote_tc/coyote_tc.package.strategy.orig +++ /dev/null @@ -1,247 +0,0 @@ -puts "Loading library IO cell meta-data" -source $::env(FOOTPRINT_LIBRARY) - -puts "Loaded library IO cell data" -Footprint definition { - Type Wirebond - - die_area {0 0 5200.000 4599.140} - core_area {210.0 210.00 4990.0 4389.14} - - power_nets "VDD VDDIO" - ground_nets "VSS VSSIO" - - offsets 0 - tracks platforms/sky130/tracks_hs.info - pin_layer met5 - - pad_inst_name "u_%s" - pad_pin_name "%s" - - padcell { - sig0 {type sig cell {centre {x 240.000 y 100.000}}} - sig1 {type sig cell {centre {x 320.000 y 100.000}}} - vzz_0 {type vssio_hvc cell {centre {x 400.000 y 100.000}}} - v18_0 {type vddio_hvc cell {centre {x 480.000 y 100.000}}} - sig2 {type sig cell {centre {x 560.000 y 100.000}}} - sig3 {type sig cell {centre {x 640.000 y 100.000}}} - sig4 {type sig cell {centre {x 720.000 y 100.000}}} - sig5 {type sig cell {centre {x 800.000 y 100.000}}} - sig6 {type sig cell {centre {x 880.000 y 100.000}}} - sig7 {type sig cell {centre {x 960.000 y 100.000}}} - sig8 {type sig cell {centre {x 1040.000 y 100.000}}} - sig9 {type sig cell {centre {x 1120.000 y 100.000}}} - vzz_1 {type vssio_hvc cell {centre {x 1200.000 y 100.000}}} - v18_1 {type vddio_hvc cell {centre {x 1280.000 y 100.000}}} - sig10 {type sig cell {centre {x 1360.000 y 100.000}}} - sig11 {type sig cell {centre {x 1440.000 y 100.000}}} - sig12 {type sig cell {centre {x 1520.000 y 100.000}}} - vss_0 {type vssd_hvc cell {centre {x 1600.000 y 100.000}}} - vdd_0 {type vccd_hvc cell {centre {x 1680.000 y 100.000}}} - sig13 {type sig cell {centre {x 1760.000 y 100.000}}} - sig14 {type sig cell {centre {x 1840.000 y 100.000}}} - sig15 {type sig cell {centre {x 1920.000 y 100.000}}} - sig16 {type sig cell {centre {x 2000.000 y 100.000}}} - sig17 {type sig cell {centre {x 2080.000 y 100.000}}} - vzz_2 {type vssio_hvc cell {centre {x 2160.000 y 100.000}}} - v18_2 {type vddio_hvc cell {centre {x 2240.000 y 100.000}}} - sig18 {type sig cell {centre {x 2320.000 y 100.000}}} - sig19 {type sig cell {centre {x 2400.000 y 100.000}}} - sig20 {type sig cell {centre {x 2480.000 y 100.000}}} - sig21 {type sig cell {centre {x 2560.000 y 100.000}}} - sig22 {type sig cell {centre {x 2640.000 y 100.000}}} - sig23 {type sig cell {centre {x 2720.000 y 100.000}}} - sig24 {type sig cell {centre {x 2800.000 y 100.000}}} - sig25 {type sig cell {centre {x 2880.000 y 100.000}}} - vzz_3 {type vssio_hvc cell {centre {x 2960.000 y 100.000}}} - v18_3 {type vddio_hvc cell {centre {x 3040.000 y 100.000}}} - sig26 {type sig cell {centre {x 3120.000 y 100.000}}} - sig27 {type sig cell {centre {x 3200.000 y 100.000}}} - sig28 {type sig cell {centre {x 3280.000 y 100.000}}} - sig29 {type sig cell {centre {x 3360.000 y 100.000}}} - sig30 {type sig cell {centre {x 3440.000 y 100.000}}} - vss_1 {type vssd_hvc cell {centre {x 3520.000 y 100.000}}} - vdd_1 {type vccd_hvc cell {centre {x 3600.000 y 100.000}}} - sig31 {type sig cell {centre {x 3680.000 y 100.000}}} - sig32 {type sig cell {centre {x 3760.000 y 100.000}}} - sig33 {type sig cell {centre {x 3840.000 y 100.000}}} - vzz_4 {type vssio_hvc cell {centre {x 3920.000 y 100.000}}} - v18_4 {type vddio_hvc cell {centre {x 4000.000 y 100.000}}} - sig34 {type sig cell {centre {x 4080.000 y 100.000}}} - sig35 {type sig cell {centre {x 4160.000 y 100.000}}} - sig36 {type sig cell {centre {x 4240.000 y 100.000}}} - sig37 {type sig cell {centre {x 4320.000 y 100.000}}} - sig38 {type sig cell {centre {x 4400.000 y 100.000}}} - sig39 {type sig cell {centre {x 4480.000 y 100.000}}} - sig40 {type sig cell {centre {x 4560.000 y 100.000}}} - sig41 {type sig cell {centre {x 4640.000 y 100.000}}} - vzz_5 {type vssio_hvc cell {centre {x 4720.000 y 100.000}}} - v18_5 {type vddio_hvc cell {centre {x 4800.000 y 100.000}}} - sig42 {type sig cell {centre {x 4880.000 y 100.000}}} - sig43 {type sig cell {centre {x 4960.000 y 100.000}}} - sig44 {type sig cell {centre {x 5100.000 y 244.000}}} - sig45 {type sig cell {centre {x 5100.000 y 324.000}}} - sig46 {type sig cell {centre {x 5100.000 y 404.000}}} - sig47 {type sig cell {centre {x 5100.000 y 484.000}}} - vzz_6 {type vssio_hvc cell {centre {x 5100.000 y 564.000}}} - v18_6 {type vddio_hvc cell {centre {x 5100.000 y 644.000}}} - vss_2 {type vssd_hvc cell {centre {x 5100.000 y 724.000}}} - vdd_2 {type vccd_hvc cell {centre {x 5100.000 y 804.000}}} - sig48 {type sig cell {centre {x 5100.000 y 884.000}}} - sig49 {type sig cell {centre {x 5100.000 y 964.000}}} - sig50 {type sig cell {centre {x 5100.000 y 1044.000}}} - sig51 {type sig cell {centre {x 5100.000 y 1124.000}}} - sig52 {type sig cell {centre {x 5100.000 y 1204.000}}} - sig53 {type sig cell {centre {x 5100.000 y 1284.000}}} - sig54 {type sig cell {centre {x 5100.000 y 1364.000}}} - sig55 {type sig cell {centre {x 5100.000 y 1444.000}}} - vzz_7 {type vssio_hvc cell {centre {x 5100.000 y 1524.000}}} - v18_7 {type vddio_hvc cell {centre {x 5100.000 y 1604.000}}} - sig56 {type sig cell {centre {x 5100.000 y 1684.000}}} - sig57 {type sig cell {centre {x 5100.000 y 1764.000}}} - sig58 {type sig cell {centre {x 5100.000 y 1844.000}}} - sig59 {type sig cell {centre {x 5100.000 y 1924.000}}} - sig60 {type sig cell {centre {x 5100.000 y 2004.000}}} - sig61 {type sig cell {centre {x 5100.000 y 2084.000}}} - sig62 {type sig cell {centre {x 5100.000 y 2164.000}}} - sig63 {type sig cell {centre {x 5100.000 y 2244.000}}} - vzz_8 {type vssio_hvc cell {centre {x 5100.000 y 2324.000}}} - v18_8 {type vddio_hvc cell {centre {x 5100.000 y 2404.000}}} - sig64 {type sig cell {centre {x 5100.000 y 2484.000}}} - sig65 {type sig cell {centre {x 5100.000 y 2564.000}}} - sig66 {type sig cell {centre {x 5100.000 y 2644.000}}} - vss_3 {type vssd_hvc cell {centre {x 5100.000 y 2724.000}}} - vdd_3 {type vccd_hvc cell {centre {x 5100.000 y 2804.000}}} - sig67 {type sig cell {centre {x 5100.000 y 2884.000}}} - sig68 {type sig cell {centre {x 5100.000 y 2964.000}}} - sig69 {type sig cell {centre {x 5100.000 y 3044.000}}} - sig70 {type sig cell {centre {x 5100.000 y 3124.000}}} - sig71 {type sig cell {centre {x 5100.000 y 3204.000}}} - vzz_9 {type vssio_hvc cell {centre {x 5100.000 y 3284.000}}} - v18_9 {type vddio_hvc cell {centre {x 5100.000 y 3364.000}}} - sig72 {type sig cell {centre {x 5100.000 y 3444.000}}} - sig73 {type sig cell {centre {x 5100.000 y 3524.000}}} - sig74 {type sig cell {centre {x 5100.000 y 3604.000}}} - sig75 {type sig cell {centre {x 5100.000 y 3684.000}}} - sig76 {type sig cell {centre {x 5100.000 y 3764.000}}} - sig77 {type sig cell {centre {x 5100.000 y 3844.000}}} - sig78 {type sig cell {centre {x 5100.000 y 3924.000}}} - sig79 {type sig cell {centre {x 5100.000 y 4004.000}}} - vzz_10 {type vssio_hvc cell {centre {x 5100.000 y 4084.000}}} - v18_10 {type vddio_hvc cell {centre {x 5100.000 y 4164.000}}} - sig80 {type sig cell {centre {x 5100.000 y 4244.000}}} - sig81 {type sig cell {centre {x 5100.000 y 4324.000}}} - sig82 {type sig cell {centre {x 4960.000 y 4499.140}}} - sig83 {type sig cell {centre {x 4880.000 y 4499.140}}} - sig84 {type sig cell {centre {x 4800.000 y 4499.140}}} - sig85 {type sig cell {centre {x 4720.000 y 4499.140}}} - vss_4 {type vssd_hvc cell {centre {x 4640.000 y 4499.140}}} - vdd_4 {type vccd_hvc cell {centre {x 4560.000 y 4499.140}}} - sig86 {type sig cell {centre {x 4480.000 y 4499.140}}} - sig87 {type sig cell {centre {x 4400.000 y 4499.140}}} - vzz_11 {type vssio_hvc cell {centre {x 4320.000 y 4499.140}}} - v18_11 {type vddio_hvc cell {centre {x 4240.000 y 4499.140}}} - sig88 {type sig cell {centre {x 4160.000 y 4499.140}}} - sig89 {type sig cell {centre {x 4080.000 y 4499.140}}} - sig90 {type sig cell {centre {x 4000.000 y 4499.140}}} - sig91 {type sig cell {centre {x 3920.000 y 4499.140}}} - sig92 {type sig cell {centre {x 3840.000 y 4499.140}}} - sig93 {type sig cell {centre {x 3760.000 y 4499.140}}} - sig94 {type sig cell {centre {x 3680.000 y 4499.140}}} - sig95 {type sig cell {centre {x 3600.000 y 4499.140}}} - vzz_12 {type vssio_hvc cell {centre {x 3520.000 y 4499.140}}} - v18_12 {type vddio_hvc cell {centre {x 3440.000 y 4499.140}}} - sig96 {type sig cell {centre {x 3360.000 y 4499.140}}} - sig97 {type sig cell {centre {x 3280.000 y 4499.140}}} - sig98 {type sig cell {centre {x 3200.000 y 4499.140}}} - sig99 {type sig cell {centre {x 3120.000 y 4499.140}}} - sig100 {type sig cell {centre {x 3040.000 y 4499.140}}} - sig101 {type sig cell {centre {x 2960.000 y 4499.140}}} - sig102 {type sig cell {centre {x 2880.000 y 4499.140}}} - sig103 {type sig cell {centre {x 2800.000 y 4499.140}}} - vzz_13 {type vssio_hvc cell {centre {x 2720.000 y 4499.140}}} - v18_13 {type vddio_hvc cell {centre {x 2640.000 y 4499.140}}} - vss_5 {type vssd_hvc cell {centre {x 2560.000 y 4499.140}}} - vdd_5 {type vccd_hvc cell {centre {x 2480.000 y 4499.140}}} - sig104 {type sig cell {centre {x 2400.000 y 4499.140}}} - sig105 {type sig cell {centre {x 2320.000 y 4499.140}}} - sig106 {type sig cell {centre {x 2240.000 y 4499.140}}} - sig107 {type sig cell {centre {x 2160.000 y 4499.140}}} - sig108 {type sig cell {centre {x 2080.000 y 4499.140}}} - sig109 {type sig cell {centre {x 2000.000 y 4499.140}}} - sig110 {type sig cell {centre {x 1920.000 y 4499.140}}} - sig111 {type sig cell {centre {x 1840.000 y 4499.140}}} - vzz_14 {type vssio_hvc cell {centre {x 1760.000 y 4499.140}}} - v18_14 {type vddio_hvc cell {centre {x 1680.000 y 4499.140}}} - sig112 {type sig cell {centre {x 1600.000 y 4499.140}}} - sig113 {type sig cell {centre {x 1520.000 y 4499.140}}} - sig114 {type sig cell {centre {x 1440.000 y 4499.140}}} - sig115 {type sig cell {centre {x 1360.000 y 4499.140}}} - sig116 {type sig cell {centre {x 1280.000 y 4499.140}}} - sig117 {type sig cell {centre {x 1200.000 y 4499.140}}} - sig118 {type sig cell {centre {x 1120.000 y 4499.140}}} - sig119 {type sig cell {centre {x 1040.000 y 4499.140}}} - vzz_15 {type vssio_hvc cell {centre {x 960.000 y 4499.140}}} - v18_15 {type vddio_hvc cell {centre {x 880.000 y 4499.140}}} - sig120 {type sig cell {centre {x 800.000 y 4499.140}}} - sig121 {type sig cell {centre {x 720.000 y 4499.140}}} - vdd_6 {type vssd_hvc cell {centre {x 640.000 y 4499.140}}} - vss_6 {type vccd_hvc cell {centre {x 560.000 y 4499.140}}} - sig122 {type sig cell {centre {x 480.000 y 4499.140}}} - sig123 {type sig cell {centre {x 400.000 y 4499.140}}} - sig124 {type sig cell {centre {x 320.000 y 4499.140}}} - sig125 {type sig cell {centre {x 240.000 y 4499.140}}} - sig126 {type sig cell {centre {x 100.000 y 4324.000}}} - sig127 {type sig cell {centre {x 100.000 y 4244.000}}} - vzz_16 {type vssio_hvc cell {centre {x 100.000 y 4164.000}}} - v18_16 {type vddio_hvc cell {centre {x 100.000 y 4084.000}}} - sig128 {type sig cell {centre {x 100.000 y 4004.000}}} - sig129 {type sig cell {centre {x 100.000 y 3924.000}}} - sig130 {type sig cell {centre {x 100.000 y 3844.000}}} - sig131 {type sig cell {centre {x 100.000 y 3764.000}}} - sig132 {type sig cell {centre {x 100.000 y 3684.000}}} - sig133 {type sig cell {centre {x 100.000 y 3604.000}}} - sig134 {type sig cell {centre {x 100.000 y 3524.000}}} - sig135 {type sig cell {centre {x 100.000 y 3444.000}}} - vzz_17 {type vssio_hvc cell {centre {x 100.000 y 3364.000}}} - v18_17 {type vddio_hvc cell {centre {x 100.000 y 3284.000}}} - sig136 {type sig cell {centre {x 100.000 y 3204.000}}} - sig137 {type sig cell {centre {x 100.000 y 3124.000}}} - sig138 {type sig cell {centre {x 100.000 y 3044.000}}} - sig139 {type sig cell {centre {x 100.000 y 2964.000}}} - sig140 {type sig cell {centre {x 100.000 y 2884.000}}} - sig141 {type sig cell {centre {x 100.000 y 2804.000}}} - vss_7 {type vssd_hvc cell {centre {x 100.000 y 2724.000}}} - vdd_7 {type vccd_hvc cell {centre {x 100.000 y 2644.000}}} - sig142 {type sig cell {centre {x 100.000 y 2564.000}}} - sig143 {type sig cell {centre {x 100.000 y 2484.000}}} - vzz_18 {type vssio_hvc cell {centre {x 100.000 y 2404.000}}} - v18_18 {type vddio_hvc cell {centre {x 100.000 y 2324.000}}} - sig144 {type sig cell {centre {x 100.000 y 2244.000}}} - sig145 {type sig cell {centre {x 100.000 y 2164.000}}} - sig146 {type sig cell {centre {x 100.000 y 2084.000}}} - sig147 {type sig cell {centre {x 100.000 y 2004.000}}} - sig148 {type sig cell {centre {x 100.000 y 1924.000}}} - sig149 {type sig cell {centre {x 100.000 y 1844.000}}} - sig150 {type sig cell {centre {x 100.000 y 1764.000}}} - sig151 {type sig cell {centre {x 100.000 y 1684.000}}} - vzz_19 {type vssio_hvc cell {centre {x 100.000 y 1604.000}}} - v18_19 {type vddio_hvc cell {centre {x 100.000 y 1524.000}}} - sig152 {type sig cell {centre {x 100.000 y 1444.000}}} - sig153 {type sig cell {centre {x 100.000 y 1364.000}}} - sig154 {type sig cell {centre {x 100.000 y 1284.000}}} - sig155 {type sig cell {centre {x 100.000 y 1204.000}}} - sig156 {type sig cell {centre {x 100.000 y 1124.000}}} - sig157 {type sig cell {centre {x 100.000 y 1044.000}}} - sig158 {type sig cell {centre {x 100.000 y 964.000}}} - sig159 {type sig cell {centre {x 100.000 y 884.000}}} - vdd_8 {type vccd_hvc cell {centre {x 100.000 y 804.000}}} - vss_8 {type vssd_hvc cell {centre {x 100.000 y 724.000}}} - vzz_20 {type vssio_hvc cell {centre {x 100.000 y 644.000}}} - v18_20 {type vddio_hvc cell {centre {x 100.000 y 564.000}}} - sig160 {type sig cell {centre {x 100.000 y 484.000}}} - sig161 {type sig cell {centre {x 100.000 y 404.000}}} - sig162 {type sig cell {centre {x 100.000 y 324.000}}} - sig163 {type sig cell {centre {x 100.000 y 244.000}}} - } -} diff --git a/flow/designs/sky130hs/coyote_tc/coyote_tc.sigmap b/flow/designs/sky130hs/coyote_tc/coyote_tc.sigmap deleted file mode 100644 index 13093a3bc4..0000000000 --- a/flow/designs/sky130hs/coyote_tc/coyote_tc.sigmap +++ /dev/null @@ -1,225 +0,0 @@ -sig0 UNASSIGNED -sig1 reset_i -sig2 UNASSIGNED -sig3 rocc_cmd_v_o -sig4 rocc_cmd_data_o_0 -sig5 rocc_cmd_data_o_1 -sig6 rocc_cmd_data_o_2 -sig7 rocc_cmd_data_o_3 -sig8 rocc_cmd_data_o_4 -sig9 rocc_cmd_data_o_5 -sig10 rocc_cmd_data_o_6 -sig11 rocc_cmd_data_o_7 -sig12 rocc_cmd_data_o_8 -sig13 rocc_cmd_data_o_9 -sig14 rocc_cmd_data_o_10 -sig15 rocc_cmd_data_o_11 -sig16 rocc_cmd_data_o_12 -sig17 rocc_cmd_data_o_13 -sig18 rocc_cmd_data_o_14 -sig19 rocc_cmd_data_o_15 -sig20 rocc_cmd_ready_i -sig21 rocc_resp_v_i -sig22 rocc_resp_data_i[0] -sig23 rocc_resp_data_i[1] -sig24 rocc_resp_data_i[2] -sig25 rocc_resp_data_i[3] -sig26 rocc_resp_data_i[4] -sig27 rocc_resp_data_i[5] -sig28 rocc_resp_data_i[6] -sig29 rocc_resp_data_i[7] -sig30 rocc_resp_ready_o -sig31 rocc_mem_req_v_i -sig32 rocc_mem_req_data_i[0] -sig33 rocc_mem_req_data_i[1] -sig34 rocc_mem_req_data_i[2] -sig35 rocc_mem_req_data_i[3] -sig36 rocc_mem_req_data_i[4] -sig37 rocc_mem_req_data_i[5] -sig38 rocc_mem_req_data_i[6] -sig39 rocc_mem_req_data_i[7] -sig40 rocc_mem_req_data_i[8] -sig41 rocc_mem_req_data_i[9] -sig42 rocc_mem_req_data_i[10] -sig43 rocc_mem_req_data_i[11] -sig44 rocc_mem_req_data_i[12] -sig45 rocc_mem_req_data_i[13] -sig46 rocc_mem_req_data_i[14] -sig47 rocc_mem_req_data_i[15] -sig48 rocc_mem_req_data_i[16] -sig49 rocc_mem_req_data_i[17] -sig50 rocc_mem_req_data_i[18] -sig51 rocc_mem_req_data_i[19] -sig52 rocc_mem_req_data_i[20] -sig53 rocc_mem_req_data_i[21] -sig54 rocc_mem_req_data_i[22] -sig55 rocc_mem_req_data_i[23] -sig56 rocc_mem_req_data_i[24] -sig57 rocc_mem_req_data_i[25] -sig58 rocc_mem_req_data_i[26] -sig59 rocc_mem_req_data_i[27] -sig60 rocc_mem_req_data_i[28] -sig61 rocc_mem_req_data_i[29] -sig62 rocc_mem_req_data_i[30] -sig63 rocc_mem_req_data_i[31] -sig64 rocc_mem_req_ready_o -sig65 rocc_mem_resp_v_o -sig66 rocc_mem_resp_data_o_0 -sig67 rocc_mem_resp_data_o_1 -sig68 rocc_mem_resp_data_o_2 -sig69 rocc_mem_resp_data_o_3 -sig70 rocc_mem_resp_data_o_4 -sig71 rocc_mem_resp_data_o_5 -sig72 rocc_mem_resp_data_o_6 -sig73 rocc_mem_resp_data_o_7 -sig74 rocc_mem_resp_data_o_8 -sig75 rocc_mem_resp_data_o_9 -sig76 rocc_mem_resp_data_o_10 -sig77 rocc_mem_resp_data_o_11 -sig78 rocc_mem_resp_data_o_12 -sig79 rocc_mem_resp_data_o_13 -sig80 rocc_mem_resp_data_o_14 -sig81 rocc_mem_resp_data_o_15 -sig82 rocc_mem_resp_data_o_16 -sig83 rocc_mem_resp_data_o_17 -sig84 rocc_mem_resp_data_o_18 -sig85 rocc_mem_resp_data_o_19 -sig86 rocc_mem_resp_data_o_20 -sig87 rocc_mem_resp_data_o_21 -sig88 rocc_mem_resp_data_o_22 -sig89 rocc_mem_resp_data_o_23 -sig90 rocc_mem_resp_data_o_24 -sig91 rocc_mem_resp_data_o_25 -sig92 rocc_mem_resp_data_o_26 -sig93 rocc_mem_resp_data_o_27 -sig94 rocc_mem_resp_data_o_28 -sig95 rocc_mem_resp_data_o_29 -sig96 rocc_mem_resp_data_o_30 -sig97 rocc_mem_resp_data_o_31 -sig98 rocc_mem_resp_data_o_32 -sig99 rocc_mem_resp_data_o_33 -sig100 rocc_mem_resp_data_o_34 -sig101 rocc_mem_resp_data_o_35 -sig102 rocc_mem_resp_data_o_36 -sig103 rocc_mem_resp_data_o_37 -sig104 rocc_mem_resp_data_o_38 -sig105 rocc_mem_resp_data_o_39 -sig106 rocc_mem_resp_data_o_40 -sig107 rocc_mem_resp_data_o_41 -sig108 rocc_mem_resp_data_o_42 -sig109 rocc_mem_resp_data_o_43 -sig110 rocc_mem_resp_data_o_44 -sig111 rocc_mem_resp_data_o_45 -sig112 rocc_mem_resp_data_o_46 -sig113 rocc_mem_resp_data_o_47 -sig114 rocc_mem_resp_data_o_48 -sig115 rocc_mem_resp_data_o_49 -sig116 rocc_mem_resp_data_o_50 -sig117 rocc_mem_resp_data_o_51 -sig118 rocc_mem_resp_data_o_52 -sig119 rocc_mem_resp_data_o_53 -sig120 rocc_mem_resp_data_o_54 -sig121 rocc_mem_resp_data_o_55 -sig122 rocc_mem_resp_data_o_56 -sig123 rocc_mem_resp_data_o_57 -sig124 rocc_mem_resp_data_o_58 -sig125 rocc_mem_resp_data_o_59 -sig126 rocc_mem_resp_data_o_60 -sig127 rocc_mem_resp_data_o_61 -sig128 rocc_mem_resp_data_o_62 -sig129 rocc_mem_resp_data_o_63 -sig130 fsb_node_v_i -sig131 fsb_node_data_i[0] -sig132 fsb_node_data_i[1] -sig133 fsb_node_data_i[2] -sig134 fsb_node_data_i[3] -sig135 fsb_node_data_i[4] -sig136 fsb_node_data_i[5] -sig137 fsb_node_data_i[6] -sig138 fsb_node_data_i[7] -sig139 fsb_node_ready_o -sig140 fsb_node_v_o -sig141 fsb_node_data_o_0 -sig142 fsb_node_data_o_1 -sig143 fsb_node_data_o_2 -sig144 fsb_node_data_o_3 -sig145 fsb_node_data_o_4 -sig146 fsb_node_data_o_5 -sig147 fsb_node_data_o_6 -sig148 fsb_node_data_o_7 -sig149 fsb_node_yumi_i -sig150 rocc_ctrl_i_busy_ -sig151 rocc_ctrl_i_interrupt_ -sig152 rocc_ctrl_o_s_ -sig153 rocc_ctrl_o_exception_ -sig154 rocc_ctrl_o_host_id_ -sig155 TDI -sig156 TDO -sig157 TCK -sig158 TRST -sig159 TMS -sig160 UNASSIGNED -sig161 UNASSIGNED -sig162 UNASSIGNED -sig163 clk_i -vdd_0 VDD -vdd_1 VDD -vdd_2 VDD -vss_3 VDD -vdd_4 VDD -vdd_5 VDD -vdd_6 VDD -vdd_7 VDD -vdd_8 VDD -vss_0 VSS -vss_1 VSS -vdd_2 VSS -vss_3 VSS -vss_4 VSS -vss_5 VSS -vss_6 VSS -vss_7 VSS -vss_8 VSS -v18_0 VDDIO -v18_1 VDDIO -v18_2 VDDIO -v18_3 VDDIO -v18_4 VDDIO -v18_5 VDDIO -v18_6 VDDIO -v18_7 VDDIO -v18_8 VDDIO -v18_9 VDDIO -v18_10 VDDIO -v18_11 VDDIO -v18_12 VDDIO -v18_13 VDDIO -v18_14 VDDIO -v18_15 VDDIO -v18_16 VDDIO -v18_17 VDDIO -v18_18 VDDIO -v18_19 VDDIO -v18_20 VDDIO -vzz_0 VSSIO -vzz_1 VSSIO -vzz_2 VSSIO -vzz_3 VSSIO -vzz_4 VSSIO -vzz_5 VSSIO -vzz_6 VSSIO -vzz_7 VSSIO -vzz_8 VSSIO -vzz_9 VSSIO -vzz_10 VSSIO -vzz_11 VSSIO -vzz_12 VSSIO -vzz_13 VSSIO -vzz_14 VSSIO -vzz_15 VSSIO -vzz_16 VSSIO -vzz_17 VSSIO -vzz_18 VSSIO -vzz_19 VSSIO -vzz_20 VSSIO - diff --git a/flow/designs/sky130hs/coyote_tc/ios.v b/flow/designs/sky130hs/coyote_tc/ios.v deleted file mode 100644 index d9a38cc4be..0000000000 --- a/flow/designs/sky130hs/coyote_tc/ios.v +++ /dev/null @@ -1,111 +0,0 @@ -`define ABUT .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b) - -`define ABUT_CONNECT .AMUXBUS_A(AMUXBUS_A), .AMUXBUS_B(AMUXBUS_B) - -`define ABUT_PORTS input AMUXBUS_A, input AMUXBUS_B - -`define TIE_CONNECT .HLD_H_N(tie_io), \ - .ENABLE_H(tie_io), \ - .ENABLE_INP_H(tie_lo_esd), \ - .ENABLE_VDDA_H(tie_io), \ - .ENABLE_VSWITCH_H(tie_lo), \ - .ENABLE_VDDIO(tie_io), \ - .INP_DIS(tie_lo), \ - .IB_MODE_SEL(tie_lo), \ - .VTRIP_SEL(tie_lo), \ - .SLOW(tie_lo), \ - .HLD_OVR(tie_lo), \ - .ANALOG_EN(tie_lo), \ - .ANALOG_SEL(tie_lo), \ - .ANALOG_POL(tie_lo), \ - .DM({tie_lo, tie_lo, tie_hi}), \ - .PAD_A_NOESD_H(), \ - .PAD_A_ESD_0_H(), \ - .PAD_A_ESD_1_H(), \ - .TIE_HI_ESD(tie_hi_esd), \ - .TIE_LO_ESD(tie_lo_esd) - -`define INPUT_PAD(PAD,SIGNAL) input_pad u_`SIGNAL (.PAD(`PAD), .y(`SIGNAL), .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b)) -`define OUTPUT_PAD(PAD,SIGNAL) output_pad u_`SIGNAL (.PAD(`PAD), .a(`SIGNAL), .AMUXBUS_A(analog_a), .AMUXBUS_B(analog_b)) - -module input_pad ( - input PAD, - output y, - `ABUT_PORTS -); - - supply1 VDDIO; - supply1 VDD; - supply0 VSS; - - wire tie_lo_esd; - wire tie_low = VSS; - wire tie_hi = VDD; - wire tie_io = VDDIO; - - sky130_ef_io__gpiov2_pad_wrapped u_in ( - .PAD(PAD), - .IN(y), - .IN_H(), - .OUT(tie_lo), - .OE_N(tie_lo), - `TIE_CONNECT, - `ABUT_CONNECT - ); -endmodule - -module output_pad ( - output PAD, - input a, - `ABUT_PORTS -); - - supply1 VDDIO; - supply1 VDD; - supply0 VSS; - - wire tie_lo_esd; - wire tie_low = VSS; - wire tie_hi = VDD; - wire tie_io = VDDIO; - - sky130_ef_io__gpiov2_pad_wrapped u_io ( - .PAD(PAD), - .IN(), - .IN_H(), - .OUT(a), - .OE_N(tie_hi), - `TIE_CONNECT, - `ABUT_CONNECT - ); -endmodule - -module input_bus #(parameter WIDTH = 1) ( - input [WIDTH-1:0] PAD, - output [WIDTH-1:0] y, - `ABUT_PORTS -); - input_pad u_io [WIDTH-1:0] (.PAD(PAD), .y(y), `ABUT_CONNECT); -endmodule - -module output_bus #(parameter WIDTH = 1) ( - output [WIDTH-1:0] PAD, - input [WIDTH-1:0] a, - `ABUT_PORTS -); - output_pad u_io [WIDTH-1:0] (.PAD(PAD), .a(a), `ABUT_CONNECT); -endmodule - -module core_pg_pads #(parameter NUM_PAIRS = 1) ( - `ABUT_PORTS -); - sky130_ef_io__vccd_hvc_pad vccd [NUM_PAIRS-1:0] (`ABUT_CONNECT); - sky130_ef_io__vssd_hvc_pad vssd [NUM_PAIRS-1:0] (`ABUT_CONNECT); -endmodule - -module io_pg_pads #(parameter NUM_PAIRS = 1) ( - `ABUT_PORTS -); - sky130_ef_io__vddio_hvc_pad vddio [NUM_PAIRS-1:0] (`ABUT_CONNECT); - sky130_ef_io__vssio_hvc_pad vssio [NUM_PAIRS-1:0] (`ABUT_CONNECT); -endmodule diff --git a/flow/designs/sky130hs/coyote_tc/macros.v b/flow/designs/sky130hs/coyote_tc/macros.v deleted file mode 100644 index de508fe0b7..0000000000 --- a/flow/designs/sky130hs/coyote_tc/macros.v +++ /dev/null @@ -1,123 +0,0 @@ -module mem_1rf_lg6_w80_bit (Q, CLK, CEN, WEN, A, D, EMA, EMAW, GWEN, RET1N); - - output [79:0] Q; - input CLK; - input CEN; - input [79:0] WEN; - input [5:0] A; - input [79:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input GWEN; - input RET1N; - - sky130_sram_1rw1r_80x64_8 - macro_mem - ( - .dout0(Q), - .clk0(CLK), - .csb0(CEN), - .wmask0(WEN), - .addr0(A), - .din0(D), - .web0(GWEN), - .addr1(6'b000000), - .csb1(1'b1), - .clk1(1'b0), - ); - -endmodule - -module mem_1rf_lg8_w128_all (Q, CLK, CEN, WEN, A, D, EMA, EMAW, RET1N); - - output [127:0] Q; - input CLK; - input CEN; - input WEN; - input [7:0] A; - input [127:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input RET1N; - - - sky130_sram_1rw1r_128x256_8 - macro_mem - ( - .dout0(Q), - .clk0(CLK), - .csb0(CEN), - .web0(WEN), - .wmask0(16'b1111111111111111), - .addr0(A), - .din0(D), - .clk1(1'b0), - .csb1(1'b1), - .addr1(8'b00000000) - ); - -endmodule - -module mem_2rf_lg6_w44_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [43:0] QA; - input CLKA; - input CENA; - input [5:0] AA; - input CLKB; - input CENB; - input [43:0] WENB; - input [5:0] AB; - input [43:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - sky130_sram_1rw1r_44x64_8 - macro_mem0 - ( - .clk1(CLKA), - .clk0(CLKB), - .addr1(AA), - .csb1(CENA), - .dout1(QA), - .addr0(AB), - .din0(DB), - .csb0(CENB), - .web0(1'b0), - .wmask0(WENB) - ); - -endmodule - -module mem_2rf_lg8_w64_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [63:0] QA; - input CLKA; - input CENA; - input [7:0] AA; - input CLKB; - input CENB; - input [63:0] WENB; - input [7:0] AB; - input [63:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - sky130_sram_1rw1r_64x256_8 - macro_mem0 - ( - .clk1(CLKA), - .clk0(CLKB), - .addr1(AA), - .csb1(CENA), - .dout1(QA), - .addr0(AB), - .din0(DB), - .csb0(CENB), - .wmask0(WENB), - .web0(1'b0) - ); - -endmodule diff --git a/flow/designs/sky130hs/coyote_tc/pdn.cfg b/flow/designs/sky130hs/coyote_tc/pdn.cfg deleted file mode 100644 index f001d40883..0000000000 --- a/flow/designs/sky130hs/coyote_tc/pdn.cfg +++ /dev/null @@ -1,61 +0,0 @@ -# Floorplan information - core boundary coordinates, std. cell row height, -# minimum track pitch as defined in LEF - -set ::halo 4 - -# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area -set ::rails_start_with "POWER" ; - -# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area -set ::stripes_start_with "POWER" ; - -# Power nets -set ::power_nets "VDD" -set ::ground_nets "VSS" - - -set pdngen::global_connections { - VDD { - {inst_name .* pin_name VPWR} - {inst_name .* pin_name VCCD} - {inst_name .* pin_name vdd} - } - VSS { - {inst_name .* pin_name VGND} - {inst_name .* pin_name VSSD} - {inst_name .* pin_name gnd} - } -} -##===> Power grid strategy -# Ensure pitches and offsets will make the stripes fall on track - -pdngen::specify_grid stdcell { - name grid - - gnd_pads {VSSD {sky130_ef_io__vssd_hvc_pad sky130_ef_io__vssd_lvc_pad}} - pwr_pads {VCCD {sky130_ef_io__vccd_hvc_pad sky130_ef_io__vccd_lvc_pad}} - - core_ring { - met4 {width 3 spacing 1.6 pad_offset 2} - met5 {width 3 spacing 1.6 pad_offset 2} - } - rails { - met1 {width 0.49 offset 0} - } - straps { - met4 {width 0.96 pitch 56.0 offset 2} - met5 {width 1.60 pitch 56.0 offset 2} - } - connect {{met1 met4} {met4 met5}} -} - -pdngen::specify_grid macro { - orient {R0 R180 MX MY} - power_pins "vdd" - ground_pins "gnd" - blockages "met1 met2 met3 met4" - straps { - met4 {width 0.93 pitch 20.0 offset 2} - } - connect {{met3_PIN_hor met4} {met4 met5}} -} diff --git a/flow/designs/sky130hs/coyote_tc/post_synthesis_rename.tcl b/flow/designs/sky130hs/coyote_tc/post_synthesis_rename.tcl deleted file mode 100644 index 8cdd238d42..0000000000 --- a/flow/designs/sky130hs/coyote_tc/post_synthesis_rename.tcl +++ /dev/null @@ -1,3 +0,0 @@ -# renames \u_clk.u_in u_clk_u_in - - diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc index f347111b34..ed93d8a1eb 100644 --- a/flow/designs/sky130hs/gcd/constraint.sdc +++ b/flow/designs/sky130hs/gcd/constraint.sdc @@ -1,15 +1,15 @@ current_design gcd -set clk_name core_clock +set clk_name core_clock set clk_port_name clk -set clk_period 2.2 +set clk_period 2.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/gcd/metadata-base-ok.json b/flow/designs/sky130hs/gcd/metadata-base-ok.json deleted file mode 100644 index a9eaad5ebe..0000000000 --- a/flow/designs/sky130hs/gcd/metadata-base-ok.json +++ /dev/null @@ -1,311 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 2.2000" - ], - "cts__clock__skew__hold": 0.0030648, - "cts__clock__skew__setup": 0.0030648, - "cts__cpu__total": 50.38, - "cts__design__core__area": 9595.2, - "cts__design__die__area": 10393.8, - "cts__design__instance__area": 4852.74, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 4852.74, - "cts__design__instance__count": 648, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 648, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.505747, - "cts__design__instance__utilization__stdcell": 0.505747, - "cts__design__io": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 645304.0, - "cts__power__internal__total": 0.0029582, - "cts__power__leakage__total": 5.809e-08, - "cts__power__switching__total": 0.00156454, - "cts__power__total": 0.0045228, - "cts__route__wirelength__estimated": 8822.42, - "cts__runtime__total": "0:15.70", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.76978, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.703041, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.344411, - "design__io__hpwl": 1483908, - "design__violations": 0, - "detailedplace__cpu__total": 2.13, - "detailedplace__design__core__area": 9595.2, - "detailedplace__design__die__area": 10393.8, - "detailedplace__design__instance__area": 4716.88, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 4716.88, - "detailedplace__design__instance__count": 640, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 640, - "detailedplace__design__instance__displacement__max": 9.27, - "detailedplace__design__instance__displacement__mean": 1.894, - "detailedplace__design__instance__displacement__total": 1212.63, - "detailedplace__design__instance__utilization": 0.491588, - "detailedplace__design__instance__utilization__stdcell": 0.491588, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 159084.0, - "detailedplace__power__internal__total": 0.00268686, - "detailedplace__power__leakage__total": 5.69683e-08, - "detailedplace__power__switching__total": 0.00120917, - "detailedplace__power__total": 0.00389609, - "detailedplace__route__wirelength__estimated": 9054.57, - "detailedplace__runtime__total": "0:02.26", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.773589, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.706342, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.614288, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 0, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 185, - "detailedroute__route__drc_errors__iter:2": 38, - "detailedroute__route__drc_errors__iter:3": 52, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 573, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 3117, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 3117, - "detailedroute__route__wirelength": 10453, - "detailedroute__route__wirelength__iter:1": 10565, - "detailedroute__route__wirelength__iter:2": 10448, - "detailedroute__route__wirelength__iter:3": 10461, - "detailedroute__route__wirelength__iter:4": 10453, - "finish__clock__skew__hold": 0.00656553, - "finish__clock__skew__setup": 0.00656553, - "finish__cpu__total": 2.53, - "finish__design__core__area": 9595.2, - "finish__design__die__area": 10393.8, - "finish__design__instance__area": 4852.74, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 4852.74, - "finish__design__instance__count": 648, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 648, - "finish__design__instance__utilization": 0.505747, - "finish__design__instance__utilization__stdcell": 0.505747, - "finish__design__io": 54, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79972, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000161172, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00055576, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.000396034, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79944, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.000396034, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 311516.0, - "finish__power__internal__total": 0.00295997, - "finish__power__leakage__total": 5.809e-08, - "finish__power__switching__total": 0.00163196, - "finish__power__total": 0.00459199, - "finish__runtime__total": "0:02.70", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.755082, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.690243, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.290475, - "finish__timing__wns_percent_delay": 19.768629, - "finish_merge__cpu__total": 1.27, - "finish_merge__mem__peak": 400500.0, - "finish_merge__runtime__total": "0:01.44", - "floorplan__cpu__total": 1.34, - "floorplan__design__core__area": 9595.2, - "floorplan__design__die__area": 10393.8, - "floorplan__design__instance__area": 3996, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 3996, - "floorplan__design__instance__count": 479, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 479, - "floorplan__design__instance__utilization": 0.416458, - "floorplan__design__instance__utilization__stdcell": 0.416458, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 3, - "floorplan__mem__peak": 159672.0, - "floorplan__power__internal__total": 0.00241133, - "floorplan__power__leakage__total": 4.95009e-08, - "floorplan__power__switching__total": 0.000804936, - "floorplan__power__total": 0.00321631, - "floorplan__runtime__total": "0:01.44", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.810019, - "floorplan_io__cpu__total": 1.18, - "floorplan_io__mem__peak": 154720.0, - "floorplan_io__runtime__total": "0:01.28", - "floorplan_macro__cpu__total": 1.21, - "floorplan_macro__mem__peak": 154472.0, - "floorplan_macro__runtime__total": "0:01.29", - "floorplan_pdn__cpu__total": 1.18, - "floorplan_pdn__mem__peak": 157292.0, - "floorplan_pdn__runtime__total": "0:01.29", - "floorplan_tap__cpu__total": 1.19, - "floorplan_tap__mem__peak": 154856.0, - "floorplan_tap__runtime__total": "0:01.26", - "floorplan_tdms__cpu__total": 1.21, - "floorplan_tdms__mem__peak": 154344.0, - "floorplan_tdms__runtime__total": "0:01.30", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 322.97, - "globalplace__design__core__area": 9595.2, - "globalplace__design__die__area": 10393.8, - "globalplace__design__instance__area": 4168.63, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 4168.63, - "globalplace__design__instance__count": 587, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 587, - "globalplace__design__instance__utilization": 0.434449, - "globalplace__design__instance__utilization__stdcell": 0.434449, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 596528.0, - "globalplace__power__internal__total": 0.00242135, - "globalplace__power__leakage__total": 4.95009e-08, - "globalplace__power__switching__total": 0.00112304, - "globalplace__power__total": 0.00354444, - "globalplace__runtime__total": "0:27.23", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 0.64932, - "globalplace_io__cpu__total": 1.19, - "globalplace_io__mem__peak": 155372.0, - "globalplace_io__runtime__total": "0:01.27", - "globalplace_skip_io__cpu__total": 413.97, - "globalplace_skip_io__mem__peak": 156312.0, - "globalplace_skip_io__runtime__total": "0:33.23", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 0, - "globalroute__clock__skew__hold": 0.00269665, - "globalroute__clock__skew__setup": 0.00269665, - "globalroute__cpu__total": 2.84, - "globalroute__design__core__area": 9595.2, - "globalroute__design__die__area": 10393.8, - "globalroute__design__instance__area": 4852.74, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 4852.74, - "globalroute__design__instance__count": 648, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 648, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.505747, - "globalroute__design__instance__utilization__stdcell": 0.505747, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 606344.0, - "globalroute__power__internal__total": 0.00296415, - "globalroute__power__leakage__total": 5.809e-08, - "globalroute__power__switching__total": 0.00191081, - "globalroute__power__total": 0.00487502, - "globalroute__route__wirelength__estimated": 8822.42, - "globalroute__runtime__total": "0:02.15", - "globalroute__timing__clock__slack": 0.189, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.737041, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.674523, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.188552, - "placeopt__cpu__total": 1.47, - "placeopt__design__core__area": 9595.2, - "placeopt__design__die__area": 10393.8, - "placeopt__design__instance__area": 4716.88, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 4716.88, - "placeopt__design__instance__count": 640, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 640, - "placeopt__design__instance__utilization": 0.491588, - "placeopt__design__instance__utilization__stdcell": 0.491588, - "placeopt__design__io": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 547760.0, - "placeopt__power__internal__total": 0.00268696, - "placeopt__power__leakage__total": 5.69683e-08, - "placeopt__power__switching__total": 0.00120989, - "placeopt__power__total": 0.0038969, - "placeopt__runtime__total": "0:01.85", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.769756, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.703021, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 0.602118, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-09-26 21:32", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "sky130hs", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "42bcfb20-db7d-4d9f-9888-7156cf44d499", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 3.01, - "synth__design__instance__area__stdcell": 3996.0, - "synth__design__instance__count__stdcell": 479.0, - "synth__mem__peak": 113280.0, - "synth__runtime__total": "0:03.21", - "total_time": "0:01:38.900000" -} \ No newline at end of file diff --git a/flow/designs/sky130hs/gcd/rules-base.json b/flow/designs/sky130hs/gcd/rules-base.json index 4370b7cceb..f8939b236d 100644 --- a/flow/designs/sky130hs/gcd/rules-base.json +++ b/flow/designs/sky130hs/gcd/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 4595.4, + "value": 4532.91, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 5424, + "value": 5423, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 736, + "value": 622, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 64, + "value": 54, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 64, + "value": 54, "compare": "<=" }, "globalroute__antenna_diodes_count": { @@ -32,7 +32,7 @@ "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 12021, + "value": 12530, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,7 +44,7 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 0, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 32, + "value": 27, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk index 3235138721..bb2959edd3 100644 --- a/flow/designs/sky130hs/ibex/config.mk +++ b/flow/designs/sky130hs/ibex/config.mk @@ -2,43 +2,14 @@ export DESIGN_NICKNAME = ibex export DESIGN_NAME = ibex_core export PLATFORM = sky130hs -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v +export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \ + $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v + +export VERILOG_INCLUDE_DIRS = \ + $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/ + +export SYNTH_HDL_FRONTEND = slang + export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc export CORE_UTILIZATION = 45 diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc index 8743e4edaa..9927412616 100644 --- a/flow/designs/sky130hs/ibex/constraint.sdc +++ b/flow/designs/sky130hs/ibex/constraint.sdc @@ -1,15 +1,15 @@ current_design ibex_core -set clk_name core_clock +set clk_name core_clock set clk_port_name clk_i -set clk_period 11.8 +set clk_period 9.0 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/ibex/metadata-base-ok.json b/flow/designs/sky130hs/ibex/metadata-base-ok.json deleted file mode 100644 index 389b3dd079..0000000000 --- a/flow/designs/sky130hs/ibex/metadata-base-ok.json +++ /dev/null @@ -1,394 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 11.8000" - ], - "cts__clock__skew__hold": 1.17204, - "cts__clock__skew__setup": 1.17208, - "cts__cpu__total": 36.13, - "cts__design__core__area": 419861, - "cts__design__die__area": 425880, - "cts__design__instance__area": 241788, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 241788, - "cts__design__instance__count": 17706, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 17706, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.575877, - "cts__design__instance__utilization__stdcell": 0.575877, - "cts__design__io": 264, - "cts__design__rows": 194, - "cts__design__rows:unit": 194, - "cts__design__sites": 262676, - "cts__design__sites:unit": 262676, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 627408.0, - "cts__power__internal__total": 0.0884283, - "cts__power__leakage__total": 2.18087e-06, - "cts__power__switching__total": 0.0426084, - "cts__power__total": 0.131039, - "cts__route__wirelength__estimated": 519754, - "cts__runtime__total": "0:36.57", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 6, - "cts__timing__drv__max_cap_limit": -0.037259, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 117, - "cts__timing__drv__max_slew_limit": -0.0142297, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 2.09556, - "design__io__hpwl": 52972496, - "design__violations": 0, - "detailedplace__cpu__total": 17.95, - "detailedplace__design__core__area": 419861, - "detailedplace__design__die__area": 425880, - "detailedplace__design__instance__area": 233661, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 233661, - "detailedplace__design__instance__count": 17361, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 17361, - "detailedplace__design__instance__displacement__max": 40.362, - "detailedplace__design__instance__displacement__mean": 3.702, - "detailedplace__design__instance__displacement__total": 64282.1, - "detailedplace__design__instance__utilization": 0.556518, - "detailedplace__design__instance__utilization__stdcell": 0.556518, - "detailedplace__design__io": 264, - "detailedplace__design__rows": 194, - "detailedplace__design__rows:unit": 194, - "detailedplace__design__sites": 262676, - "detailedplace__design__sites:unit": 262676, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 268516.0, - "detailedplace__power__internal__total": 0.0854693, - "detailedplace__power__leakage__total": 2.12109e-06, - "detailedplace__power__switching__total": 0.0393604, - "detailedplace__power__total": 0.124832, - "detailedplace__route__wirelength__estimated": 518915, - "detailedplace__runtime__total": "0:18.12", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 5, - "detailedplace__timing__drv__max_cap_limit": -0.0265873, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 89, - "detailedplace__timing__drv__max_slew_limit": -0.0083874, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 2.27959, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 12, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 61, - "detailedroute__route__drc_errors__iter:10": 7, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 0, - "detailedroute__route__drc_errors__iter:2": 11, - "detailedroute__route__drc_errors__iter:3": 9, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 179, - "detailedroute__route__drc_errors__iter:6": 96, - "detailedroute__route__drc_errors__iter:7": 52, - "detailedroute__route__drc_errors__iter:8": 32, - "detailedroute__route__drc_errors__iter:9": 8, - "detailedroute__route__net": 13844, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 118307, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 118307, - "detailedroute__route__wirelength": 685091, - "detailedroute__route__wirelength__iter:1": 685114, - "detailedroute__route__wirelength__iter:10": 684949, - "detailedroute__route__wirelength__iter:11": 684954, - "detailedroute__route__wirelength__iter:12": 684966, - "detailedroute__route__wirelength__iter:2": 685103, - "detailedroute__route__wirelength__iter:3": 685104, - "detailedroute__route__wirelength__iter:4": 685091, - "detailedroute__route__wirelength__iter:5": 684945, - "detailedroute__route__wirelength__iter:6": 685011, - "detailedroute__route__wirelength__iter:7": 684988, - "detailedroute__route__wirelength__iter:8": 684968, - "detailedroute__route__wirelength__iter:9": 684953, - "finish__clock__skew__hold": 1.25803, - "finish__clock__skew__setup": 1.25811, - "finish__cpu__total": 60.86, - "finish__design__core__area": 419861, - "finish__design__die__area": 425880, - "finish__design__instance__area": 244082, - "finish__design__instance__area__class:antenna_cell": 137.462, - "finish__design__instance__area__class:buffer": 55.944, - "finish__design__instance__area__class:clock_buffer": 7084.11, - "finish__design__instance__area__class:clock_inverter": 1043.76, - "finish__design__instance__area__class:inverter": 3305.49, - "finish__design__instance__area__class:multi_input_combinational_cell": 145899, - "finish__design__instance__area__class:sequential_cell": 69480.8, - "finish__design__instance__area__class:timing_repair_buffer": 9870.12, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 244082, - "finish__design__instance__count": 17815, - "finish__design__instance__count__class:antenna_cell": 43, - "finish__design__instance__count__class:buffer": 5, - "finish__design__instance__count__class:clock_buffer": 228, - "finish__design__instance__count__class:clock_inverter": 117, - "finish__design__instance__count__class:inverter": 576, - "finish__design__instance__count__class:multi_input_combinational_cell": 9896, - "finish__design__instance__count__class:sequential_cell": 1932, - "finish__design__instance__count__class:timing_repair_buffer": 510, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 17815, - "finish__design__instance__utilization": 0.58134, - "finish__design__instance__utilization__stdcell": 0.58134, - "finish__design__io": 264, - "finish__design__rows": 194, - "finish__design__rows:unit": 194, - "finish__design__sites": 262676, - "finish__design__sites:unit": 262676, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79905, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000968469, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00371806, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.00320292, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.79628, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.00320292, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 583388.0, - "finish__power__internal__total": 0.089062, - "finish__power__leakage__total": 2.19528e-06, - "finish__power__switching__total": 0.0482569, - "finish__power__total": 0.137321, - "finish__runtime__total": "1:01.26", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 9, - "finish__timing__drv__max_cap_limit": -0.0579615, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 21, - "finish__timing__drv__max_slew_limit": -0.0384185, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 1.51462, - "finish__timing__wns_percent_delay": 19.110707, - "finish_merge__cpu__total": 2.34, - "finish_merge__mem__peak": 524572.0, - "finish_merge__runtime__total": "0:02.63", - "floorplan__cpu__total": 9.95, - "floorplan__design__core__area": 419861, - "floorplan__design__die__area": 425880, - "floorplan__design__instance__area": 182063, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 182063, - "floorplan__design__instance__count": 12404, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__stdcell": 12404, - "floorplan__design__instance__utilization": 0.433625, - "floorplan__design__instance__utilization__stdcell": 0.433625, - "floorplan__design__io": 264, - "floorplan__design__rows": 194, - "floorplan__design__rows:unit": 194, - "floorplan__design__sites": 262676, - "floorplan__design__sites:unit": 262676, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 219556.0, - "floorplan__power__internal__total": 0.0926771, - "floorplan__power__leakage__total": 2.13145e-06, - "floorplan__power__switching__total": 0.0160417, - "floorplan__power__total": 0.108721, - "floorplan__runtime__total": "0:10.08", - "floorplan__timing__setup__tns": -7033.14, - "floorplan__timing__setup__ws": -5.66757, - "floorplan_io__cpu__total": 1.37, - "floorplan_io__mem__peak": 178596.0, - "floorplan_io__runtime__total": "0:01.48", - "floorplan_macro__cpu__total": 1.36, - "floorplan_macro__mem__peak": 178084.0, - "floorplan_macro__runtime__total": "0:01.46", - "floorplan_pdn__cpu__total": 1.7, - "floorplan_pdn__mem__peak": 184232.0, - "floorplan_pdn__runtime__total": "0:01.79", - "floorplan_tap__cpu__total": 1.35, - "floorplan_tap__mem__peak": 171684.0, - "floorplan_tap__runtime__total": "0:01.46", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 317.53, - "globalplace__design__core__area": 419861, - "globalplace__design__die__area": 425880, - "globalplace__design__instance__area": 189268, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 189268, - "globalplace__design__instance__count": 16912, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 16912, - "globalplace__design__instance__utilization": 0.450787, - "globalplace__design__instance__utilization__stdcell": 0.450787, - "globalplace__design__io": 264, - "globalplace__design__rows": 194, - "globalplace__design__rows:unit": 194, - "globalplace__design__sites": 262676, - "globalplace__design__sites:unit": 262676, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 636236.0, - "globalplace__power__internal__total": 0.112883, - "globalplace__power__leakage__total": 2.13145e-06, - "globalplace__power__switching__total": 0.0296431, - "globalplace__power__total": 0.142528, - "globalplace__runtime__total": "1:17.81", - "globalplace__timing__setup__tns": -20560.3, - "globalplace__timing__setup__ws": -12.7893, - "globalplace_io__cpu__total": 1.37, - "globalplace_io__mem__peak": 184752.0, - "globalplace_io__runtime__total": "0:01.49", - "globalplace_skip_io__cpu__total": 140.61, - "globalplace_skip_io__mem__peak": 203056.0, - "globalplace_skip_io__runtime__total": "0:05.95", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 31, - "globalroute__clock__skew__hold": 1.29756, - "globalroute__clock__skew__setup": 1.29765, - "globalroute__cpu__total": 120.76, - "globalroute__design__core__area": 419861, - "globalroute__design__die__area": 425880, - "globalroute__design__instance__area": 244044, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 244044, - "globalroute__design__instance__count": 17803, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 17803, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.581248, - "globalroute__design__instance__utilization__stdcell": 0.581248, - "globalroute__design__io": 264, - "globalroute__design__rows": 194, - "globalroute__design__rows:unit": 194, - "globalroute__design__sites": 262676, - "globalroute__design__sites:unit": 262676, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 775468.0, - "globalroute__power__internal__total": 0.0891605, - "globalroute__power__leakage__total": 2.19528e-06, - "globalroute__power__switching__total": 0.0508064, - "globalroute__power__total": 0.139969, - "globalroute__route__wirelength__estimated": 536209, - "globalroute__runtime__total": "0:47.21", - "globalroute__timing__clock__slack": 1.505, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.00227105, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.000628275, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 1.50459, - "placeopt__cpu__total": 19.01, - "placeopt__design__core__area": 419861, - "placeopt__design__die__area": 425880, - "placeopt__design__instance__area": 233661, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 233661, - "placeopt__design__instance__count": 17361, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 17361, - "placeopt__design__instance__utilization": 0.556518, - "placeopt__design__instance__utilization__stdcell": 0.556518, - "placeopt__design__io": 264, - "placeopt__design__rows": 194, - "placeopt__design__rows:unit": 194, - "placeopt__design__sites": 262676, - "placeopt__design__sites:unit": 262676, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 498524.0, - "placeopt__power__internal__total": 0.085377, - "placeopt__power__leakage__total": 2.12109e-06, - "placeopt__power__switching__total": 0.0385279, - "placeopt__power__total": 0.123907, - "placeopt__runtime__total": "0:19.40", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00142253, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0197833, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 2.28649, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-11-22 13:56", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17198-g8396d0866", - "run__flow__platform": "sky130hs", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "b7e804fd-4507-4040-afd2-cccafa69f971", - "run__flow__variant": "base", - "synth__cpu__total": 62.73, - "synth__design__instance__area__stdcell": 190474.9344, - "synth__design__instance__count__stdcell": 13598.0, - "synth__mem__peak": 159808.0, - "synth__runtime__total": "1:03.09", - "total_time": "0:05:49.800000" -} \ No newline at end of file diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json index a2e1eecf6c..87b458d33b 100644 --- a/flow/designs/sky130hs/ibex/rules-base.json +++ b/flow/designs/sky130hs/ibex/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 215689.7, + "value": 214910.32, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 262420, + "value": 261133, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19965, + "value": 19436, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1736, + "value": 1690, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1736, + "value": 1690, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 36, + "value": 130, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 787855, + "value": 908310, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,11 +44,11 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 14, + "value": 33, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.19, "compare": ">=" }, "finish__design__instance__area": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 868, + "value": 845, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/sky130hs/jpeg/config.mk b/flow/designs/sky130hs/jpeg/config.mk index 6e7b62953e..3ae6575637 100644 --- a/flow/designs/sky130hs/jpeg/config.mk +++ b/flow/designs/sky130hs/jpeg/config.mk @@ -14,3 +14,5 @@ export CORE_MARGIN = 2 export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 +export CTS_CLUSTER_SIZE = 30 +export CTS_CLUSTER_DIAMETER = 50 diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index d9420273eb..4c40fe5a3f 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -1,6 +1,6 @@ current_design jpeg_encoder -set clk_name clk +set clk_name clk set clk_port_name clk set clk_period 6.0 set clk_io_pct 0.2 @@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name] create_clock -name $clk_name -period $clk_period $clk_port -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_inputs [all_inputs -no_clocks] -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/jpeg/metadata-base-ok.json b/flow/designs/sky130hs/jpeg/metadata-base-ok.json deleted file mode 100644 index f114f31d48..0000000000 --- a/flow/designs/sky130hs/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,400 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 6.0000" - ], - "cts__clock__skew__hold": 0.0779145, - "cts__clock__skew__setup": 0.0779145, - "cts__cpu__total": 50.94, - "cts__design__core__area": 1352770.0, - "cts__design__die__area": 1366160.0, - "cts__design__instance__area": 853932, - "cts__design__instance__area__cover": 0, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__padcells": 0, - "cts__design__instance__area__stdcell": 853932, - "cts__design__instance__count": 76840, - "cts__design__instance__count__cover": 0, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__padcells": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 76840, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.631249, - "cts__design__instance__utilization__stdcell": 0.631249, - "cts__design__io": 47, - "cts__design__rows": 349, - "cts__design__rows:unit": 349, - "cts__design__sites": 846325, - "cts__design__sites:unit": 846325, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 939380.0, - "cts__power__internal__total": 2.19508, - "cts__power__leakage__total": 8.16087e-06, - "cts__power__switching__total": 1.39415, - "cts__power__total": 3.58924, - "cts__route__wirelength__estimated": 2770520.0, - "cts__runtime__total": "0:51.64", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0216448, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.0328821, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 0.0335545, - "design__io__hpwl": 13921904, - "design__violations": 0, - "detailedplace__cpu__total": 55.29, - "detailedplace__design__core__area": 1352770.0, - "detailedplace__design__die__area": 1366160.0, - "detailedplace__design__instance__area": 833530, - "detailedplace__design__instance__area__cover": 0, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__padcells": 0, - "detailedplace__design__instance__area__stdcell": 833530, - "detailedplace__design__instance__count": 75991, - "detailedplace__design__instance__count__cover": 0, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__padcells": 0, - "detailedplace__design__instance__count__stdcell": 75991, - "detailedplace__design__instance__displacement__max": 35.093, - "detailedplace__design__instance__displacement__mean": 2.354, - "detailedplace__design__instance__displacement__total": 178903, - "detailedplace__design__instance__utilization": 0.616168, - "detailedplace__design__instance__utilization__stdcell": 0.616168, - "detailedplace__design__io": 47, - "detailedplace__design__rows": 349, - "detailedplace__design__rows:unit": 349, - "detailedplace__design__sites": 846325, - "detailedplace__design__sites:unit": 846325, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 575256.0, - "detailedplace__power__internal__total": 2.17529, - "detailedplace__power__leakage__total": 8.01664e-06, - "detailedplace__power__switching__total": 1.36718, - "detailedplace__power__total": 3.54248, - "detailedplace__route__wirelength__estimated": 2766070.0, - "detailedplace__runtime__total": "0:55.65", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0241887, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0352824, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.0987961, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 519, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:0": 103, - "detailedroute__route__drc_errors__iter:1": 25, - "detailedroute__route__drc_errors__iter:10": 4, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:12": 2, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:2": 15, - "detailedroute__route__drc_errors__iter:3": 2, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__drc_errors__iter:6": 111, - "detailedroute__route__drc_errors__iter:7": 111, - "detailedroute__route__drc_errors__iter:8": 78, - "detailedroute__route__drc_errors__iter:9": 33, - "detailedroute__route__net": 73830, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 483974, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 483974, - "detailedroute__route__wirelength": 3244511, - "detailedroute__route__wirelength__iter:0": 3244599, - "detailedroute__route__wirelength__iter:1": 3244527, - "detailedroute__route__wirelength__iter:10": 3244109, - "detailedroute__route__wirelength__iter:11": 3244106, - "detailedroute__route__wirelength__iter:12": 3241152, - "detailedroute__route__wirelength__iter:13": 3241154, - "detailedroute__route__wirelength__iter:2": 3244520, - "detailedroute__route__wirelength__iter:3": 3244511, - "detailedroute__route__wirelength__iter:4": 3244511, - "detailedroute__route__wirelength__iter:5": 3244490, - "detailedroute__route__wirelength__iter:6": 3244109, - "detailedroute__route__wirelength__iter:7": 3244109, - "detailedroute__route__wirelength__iter:8": 3244086, - "detailedroute__route__wirelength__iter:9": 3244063, - "finish__clock__skew__hold": 0.116337, - "finish__clock__skew__setup": 0.116337, - "finish__cpu__total": 138.68, - "finish__design__core__area": 1352770.0, - "finish__design__die__area": 1366160.0, - "finish__design__instance__area": 857895, - "finish__design__instance__area__class:antenna_cell": 3270.33, - "finish__design__instance__area__class:buffer": 42781.2, - "finish__design__instance__area__class:clock_buffer": 16828, - "finish__design__instance__area__class:clock_inverter": 3574.02, - "finish__design__instance__area__class:inverter": 70049.9, - "finish__design__instance__area__class:multi_input_combinational_cell": 574016, - "finish__design__instance__area__class:sequential_cell": 122888, - "finish__design__instance__area__class:timing_repair_buffer": 1205.19, - "finish__design__instance__area__cover": 0, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__padcells": 0, - "finish__design__instance__area__stdcell": 857895, - "finish__design__instance__count": 77898, - "finish__design__instance__count__class:antenna_cell": 1023, - "finish__design__instance__count__class:buffer": 1760, - "finish__design__instance__count__class:clock_buffer": 544, - "finish__design__instance__count__class:clock_inverter": 305, - "finish__design__instance__count__class:inverter": 13091, - "finish__design__instance__count__class:multi_input_combinational_cell": 42142, - "finish__design__instance__count__class:sequential_cell": 4385, - "finish__design__instance__count__class:timing_repair_buffer": 82, - "finish__design__instance__count__cover": 0, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__padcells": 0, - "finish__design__instance__count__stdcell": 77898, - "finish__design__instance__utilization": 0.634178, - "finish__design__instance__utilization__stdcell": 0.634178, - "finish__design__io": 47, - "finish__design__rows": 349, - "finish__design__rows:unit": 349, - "finish__design__sites": 846325, - "finish__design__sites:unit": 846325, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79095, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.00890482, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.043168, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0388129, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.75683, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0388129, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 1, - "finish__mem__peak": 1594088.0, - "finish__power__internal__total": 2.21364, - "finish__power__leakage__total": 8.16892e-06, - "finish__power__switching__total": 1.63975, - "finish__power__total": 3.8534, - "finish__runtime__total": "2:20.25", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 19, - "finish__timing__drv__max_cap_limit": -0.525528, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 91, - "finish__timing__drv__max_slew_limit": -0.48359, - "finish__timing__drv__setup_violation_count": 11, - "finish__timing__setup__tns": -0.936542, - "finish__timing__setup__ws": -0.203602, - "finish__timing__wns_percent_delay": -2.94343, - "finish_merge__cpu__total": 6.35, - "finish_merge__mem__peak": 918912.0, - "finish_merge__runtime__total": "0:06.92", - "floorplan__cpu__total": 21.27, - "floorplan__design__core__area": 1352770.0, - "floorplan__design__die__area": 1366160.0, - "floorplan__design__instance__area": 678414, - "floorplan__design__instance__area__cover": 0, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__padcells": 0, - "floorplan__design__instance__area__stdcell": 678414, - "floorplan__design__instance__count": 61378, - "floorplan__design__instance__count__cover": 0, - "floorplan__design__instance__count__hold_buffer": 0, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__padcells": 0, - "floorplan__design__instance__count__setup_buffer": 0, - "floorplan__design__instance__count__stdcell": 61378, - "floorplan__design__instance__utilization": 0.501501, - "floorplan__design__instance__utilization__stdcell": 0.501501, - "floorplan__design__io": 47, - "floorplan__design__rows": 349, - "floorplan__design__rows:unit": 349, - "floorplan__design__sites": 846325, - "floorplan__design__sites:unit": 846325, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 3, - "floorplan__mem__peak": 410600.0, - "floorplan__power__internal__total": 1.51101, - "floorplan__power__leakage__total": 8.16138e-06, - "floorplan__power__switching__total": 0.558806, - "floorplan__power__total": 2.06982, - "floorplan__runtime__total": "0:21.56", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.613713, - "floorplan_io__cpu__total": 1.63, - "floorplan_io__mem__peak": 265272.0, - "floorplan_io__runtime__total": "0:01.80", - "floorplan_macro__cpu__total": 1.67, - "floorplan_macro__mem__peak": 264364.0, - "floorplan_macro__runtime__total": "0:01.84", - "floorplan_pdn__cpu__total": 2.88, - "floorplan_pdn__mem__peak": 287824.0, - "floorplan_pdn__runtime__total": "0:03.09", - "floorplan_tap__cpu__total": 1.62, - "floorplan_tap__mem__peak": 233908.0, - "floorplan_tap__runtime__total": "0:01.77", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1209.21, - "globalplace__design__core__area": 1352770.0, - "globalplace__design__die__area": 1366160.0, - "globalplace__design__instance__area": 831927, - "globalplace__design__instance__area__cover": 0, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__padcells": 0, - "globalplace__design__instance__area__stdcell": 831927, - "globalplace__design__instance__count": 75947, - "globalplace__design__instance__count__cover": 0, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__padcells": 0, - "globalplace__design__instance__count__stdcell": 75947, - "globalplace__design__instance__utilization": 0.614982, - "globalplace__design__instance__utilization__stdcell": 0.614982, - "globalplace__design__io": 47, - "globalplace__design__rows": 349, - "globalplace__design__rows:unit": 349, - "globalplace__design__sites": 846325, - "globalplace__design__sites:unit": 846325, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 1099236.0, - "globalplace__power__internal__total": 2.17733, - "globalplace__power__leakage__total": 8.01364e-06, - "globalplace__power__switching__total": 1.36062, - "globalplace__power__total": 3.53796, - "globalplace__runtime__total": "4:13.39", - "globalplace__timing__setup__tns": 0, - "globalplace__timing__setup__ws": 0.0726716, - "globalplace_io__cpu__total": 1.72, - "globalplace_io__mem__peak": 284736.0, - "globalplace_io__runtime__total": "0:01.90", - "globalplace_skip_io__cpu__total": 313.11, - "globalplace_skip_io__mem__peak": 387180.0, - "globalplace_skip_io__runtime__total": "0:25.28", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 504, - "globalroute__clock__skew__hold": 0.0931081, - "globalroute__clock__skew__setup": 0.0931081, - "globalroute__cpu__total": 290.08, - "globalroute__design__core__area": 1352770.0, - "globalroute__design__die__area": 1366160.0, - "globalroute__design__instance__area": 856236, - "globalroute__design__instance__area__cover": 0, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__padcells": 0, - "globalroute__design__instance__area__stdcell": 856236, - "globalroute__design__instance__count": 77379, - "globalroute__design__instance__count__cover": 0, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__padcells": 0, - "globalroute__design__instance__count__setup_buffer": 27, - "globalroute__design__instance__count__stdcell": 77379, - "globalroute__design__instance__displacement__max": 21.48, - "globalroute__design__instance__displacement__mean": 0.006, - "globalroute__design__instance__displacement__total": 465.24, - "globalroute__design__instance__utilization": 0.632952, - "globalroute__design__instance__utilization__stdcell": 0.632952, - "globalroute__design__io": 47, - "globalroute__design__rows": 349, - "globalroute__design__rows:unit": 349, - "globalroute__design__sites": 846325, - "globalroute__design__sites:unit": 846325, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1721796.0, - "globalroute__power__internal__total": 2.23959, - "globalroute__power__leakage__total": 8.16892e-06, - "globalroute__power__switching__total": 1.66437, - "globalroute__power__total": 3.90397, - "globalroute__route__wirelength__estimated": 2773180.0, - "globalroute__runtime__total": "1:36.36", - "globalroute__timing__clock__slack": -0.099, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 5, - "globalroute__timing__drv__max_cap_limit": -0.261725, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 10, - "globalroute__timing__drv__max_slew_limit": -0.232695, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -0.0986864, - "globalroute__timing__setup__ws": -0.0986864, - "placeopt__cpu__total": 48.06, - "placeopt__design__core__area": 1352770.0, - "placeopt__design__die__area": 1366160.0, - "placeopt__design__instance__area": 833530, - "placeopt__design__instance__area__cover": 0, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__padcells": 0, - "placeopt__design__instance__area__stdcell": 833530, - "placeopt__design__instance__count": 75991, - "placeopt__design__instance__count__cover": 0, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__padcells": 0, - "placeopt__design__instance__count__stdcell": 75991, - "placeopt__design__instance__utilization": 0.616168, - "placeopt__design__instance__utilization__stdcell": 0.616168, - "placeopt__design__io": 47, - "placeopt__design__rows": 349, - "placeopt__design__rows:unit": 349, - "placeopt__design__sites": 846325, - "placeopt__design__sites:unit": 846325, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 723428.0, - "placeopt__power__internal__total": 2.17445, - "placeopt__power__leakage__total": 8.01664e-06, - "placeopt__power__switching__total": 1.35986, - "placeopt__power__total": 3.53432, - "placeopt__runtime__total": "0:48.56", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0259198, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0369178, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 0.0790936, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2024-11-28 16:27", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-17429-g24d1bf502", - "run__flow__platform": "sky130hs", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "N/A", - "run__flow__scripts_commit": "not a git repo", - "run__flow__uuid": "5f3a5f48-6c8f-4b20-9ed5-68b391d23679", - "run__flow__variant": "base", - "synth__cpu__total": 88.58, - "synth__design__instance__area__stdcell": 678413.7072, - "synth__design__instance__count__stdcell": 61378.0, - "synth__mem__peak": 615940.0, - "synth__runtime__total": "1:29.73", - "total_time": "0:13:19.740000" -} \ No newline at end of file diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index 16d4082dd1..953f199764 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 780175.77, + "value": 653350.08, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 940805, + "value": 723127, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 87390, + "value": 63375, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 7599, + "value": 5511, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 7599, + "value": 5511, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 580, + "value": 87, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 3731188, + "value": 1619030, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -40,23 +40,23 @@ "compare": "<=" }, "detailedroute__antenna__violating__nets": { - "value": 0, + "value": 1, "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 597, + "value": 86, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.5, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 969280, + "value": 760037, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 3800, + "value": 2755, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { @@ -64,7 +64,7 @@ "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -10.04, + "value": -10.0, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc index 71a164e11b..a598e70954 100644 --- a/flow/designs/sky130hs/riscv32i/constraint.sdc +++ b/flow/designs/sky130hs/riscv32i/constraint.sdc @@ -1,6 +1,6 @@ -set clk_name clk +set clk_name clk set clk_port_name clk -set clk_period 7.6 +set clk_period 5.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] @@ -9,10 +9,10 @@ create_clock -name $clk_name -period $clk_period $clk_port set non_clock_inputs [list] foreach input [all_inputs] { - if {$clk_port != $input} { - lappend $non_clock_inputs $input - } + if { $clk_port != $input } { + lappend $non_clock_inputs $input + } } -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/sky130hs/riscv32i/metadata-base-ok.json b/flow/designs/sky130hs/riscv32i/metadata-base-ok.json deleted file mode 100644 index 152d96c73c..0000000000 --- a/flow/designs/sky130hs/riscv32i/metadata-base-ok.json +++ /dev/null @@ -1,313 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 7.6000" - ], - "cts__clock__skew__hold": 0.0217499, - "cts__clock__skew__setup": 0.0217499, - "cts__cpu__total": 15.87, - "cts__design__core__area": 185987, - "cts__design__die__area": 189861, - "cts__design__instance__area": 107406, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 107406, - "cts__design__instance__count": 8808, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 8808, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.577494, - "cts__design__instance__utilization__stdcell": 0.577494, - "cts__design__io": 165, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 0, - "cts__mem__peak": 662512.0, - "cts__power__internal__total": 0.0229574, - "cts__power__leakage__total": 9.33212e-07, - "cts__power__switching__total": 0.00810998, - "cts__power__total": 0.0310683, - "cts__route__wirelength__estimated": 235220, - "cts__runtime__total": "0:16.53", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 2, - "cts__timing__drv__max_cap_limit": -0.0161484, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 154, - "cts__timing__drv__max_slew_limit": -0.0184563, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__ws": 1.20738, - "design__io__hpwl": 38593889, - "design__violations": 0, - "detailedplace__cpu__total": 9.3, - "detailedplace__design__core__area": 185987, - "detailedplace__design__die__area": 189861, - "detailedplace__design__instance__area": 103105, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 103105, - "detailedplace__design__instance__count": 8627, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 8627, - "detailedplace__design__instance__displacement__max": 44.888, - "detailedplace__design__instance__displacement__mean": 3.24, - "detailedplace__design__instance__displacement__total": 27951.9, - "detailedplace__design__instance__utilization": 0.554367, - "detailedplace__design__instance__utilization__stdcell": 0.554367, - "detailedplace__design__io": 165, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 199768.0, - "detailedplace__power__internal__total": 0.0197451, - "detailedplace__power__leakage__total": 9.0169e-07, - "detailedplace__power__switching__total": 0.00518982, - "detailedplace__power__total": 0.0249358, - "detailedplace__route__wirelength__estimated": 232614, - "detailedplace__runtime__total": "0:09.41", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 1, - "detailedplace__timing__drv__max_cap_limit": -0.00205354, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 45, - "detailedplace__timing__drv__max_slew_limit": -0.00652134, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 1.71508, - "detailedroute__antenna__violating__nets": 0, - "detailedroute__antenna__violating__pins": 0, - "detailedroute__antenna_diodes_count": 3, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 10, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 5294, - "detailedroute__route__drc_errors__iter:2": 2628, - "detailedroute__route__drc_errors__iter:3": 2442, - "detailedroute__route__drc_errors__iter:4": 220, - "detailedroute__route__drc_errors__iter:5": 63, - "detailedroute__route__drc_errors__iter:6": 0, - "detailedroute__route__net": 6874, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 58403, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 58403, - "detailedroute__route__wirelength": 335358, - "detailedroute__route__wirelength__iter:1": 339508, - "detailedroute__route__wirelength__iter:2": 336815, - "detailedroute__route__wirelength__iter:3": 335984, - "detailedroute__route__wirelength__iter:4": 335460, - "detailedroute__route__wirelength__iter:5": 335352, - "detailedroute__route__wirelength__iter:6": 335358, - "finish__clock__skew__hold": 0.0589969, - "finish__clock__skew__setup": 0.0589969, - "finish__cpu__total": 28.34, - "finish__design__core__area": 185987, - "finish__design__die__area": 189861, - "finish__design__instance__area": 107906, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 107906, - "finish__design__instance__count": 8846, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 8846, - "finish__design__instance__utilization": 0.580184, - "finish__design__instance__utilization__stdcell": 0.580184, - "finish__design__io": 165, - "finish__design_powergrid__drop__average__net:VDD__corner:default": 1.79935, - "finish__design_powergrid__drop__average__net:VSS__corner:default": 0.000534877, - "finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.00159799, - "finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0011637, - "finish__design_powergrid__voltage__worst__net:VDD__corner:default": 1.7984, - "finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0011637, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 463964.0, - "finish__power__internal__total": 0.0230847, - "finish__power__leakage__total": 9.3606e-07, - "finish__power__switching__total": 0.00894253, - "finish__power__total": 0.0320281, - "finish__runtime__total": "0:28.79", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.0203786, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 65, - "finish__timing__drv__max_slew_limit": -0.0511011, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.615675, - "finish__timing__wns_percent_delay": 11.267683, - "finish_merge__cpu__total": 1.87, - "finish_merge__mem__peak": 460984.0, - "finish_merge__runtime__total": "0:02.11", - "floorplan__cpu__total": 6.0, - "floorplan__design__core__area": 185987, - "floorplan__design__die__area": 189861, - "floorplan__design__instance__area": 79717, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 79717, - "floorplan__design__instance__count": 6294, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 6294, - "floorplan__design__instance__utilization": 0.428617, - "floorplan__design__instance__utilization__stdcell": 0.428617, - "floorplan__design__io": 165, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 2, - "floorplan__mem__peak": 188412.0, - "floorplan__power__internal__total": 0.0173016, - "floorplan__power__leakage__total": 8.8709e-07, - "floorplan__power__switching__total": 0.0025729, - "floorplan__power__total": 0.0198754, - "floorplan__runtime__total": "0:06.16", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 1.1992, - "floorplan_io__cpu__total": 1.22, - "floorplan_io__mem__peak": 166516.0, - "floorplan_io__runtime__total": "0:01.34", - "floorplan_macro__cpu__total": 1.24, - "floorplan_macro__mem__peak": 165752.0, - "floorplan_macro__runtime__total": "0:01.34", - "floorplan_pdn__cpu__total": 1.39, - "floorplan_pdn__mem__peak": 168904.0, - "floorplan_pdn__runtime__total": "0:01.48", - "floorplan_tap__cpu__total": 1.2, - "floorplan_tap__mem__peak": 161656.0, - "floorplan_tap__runtime__total": "0:01.34", - "floorplan_tdms__cpu__total": 1.21, - "floorplan_tdms__mem__peak": 164920.0, - "floorplan_tdms__runtime__total": "0:01.34", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 1300.42, - "globalplace__design__core__area": 185987, - "globalplace__design__die__area": 189861, - "globalplace__design__instance__area": 82961.8, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 82961.8, - "globalplace__design__instance__count": 8324, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 8324, - "globalplace__design__instance__utilization": 0.446063, - "globalplace__design__instance__utilization__stdcell": 0.446063, - "globalplace__design__io": 165, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 673628.0, - "globalplace__power__internal__total": 0.0181382, - "globalplace__power__leakage__total": 8.8709e-07, - "globalplace__power__switching__total": 0.00405829, - "globalplace__power__total": 0.0221973, - "globalplace__runtime__total": "2:02.63", - "globalplace__timing__setup__tns": -337.9, - "globalplace__timing__setup__ws": -1.64425, - "globalplace_io__cpu__total": 1.26, - "globalplace_io__mem__peak": 168952.0, - "globalplace_io__runtime__total": "0:01.37", - "globalplace_skip_io__cpu__total": 482.07, - "globalplace_skip_io__mem__peak": 177076.0, - "globalplace_skip_io__runtime__total": "0:33.95", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__antenna_diodes_count": 22, - "globalroute__clock__skew__hold": 0.0494199, - "globalroute__clock__skew__setup": 0.0494199, - "globalroute__cpu__total": 55.74, - "globalroute__design__core__area": 185987, - "globalroute__design__die__area": 189861, - "globalroute__design__instance__area": 107897, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 107897, - "globalroute__design__instance__count": 8843, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 8843, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.580132, - "globalroute__design__instance__utilization__stdcell": 0.580132, - "globalroute__design__io": 165, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 741024.0, - "globalroute__power__internal__total": 0.0230858, - "globalroute__power__leakage__total": 9.3606e-07, - "globalroute__power__switching__total": 0.00985118, - "globalroute__power__total": 0.0329379, - "globalroute__route__wirelength__estimated": 239832, - "globalroute__runtime__total": "0:24.43", - "globalroute__timing__clock__slack": 0.491, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0131821, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0111365, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 0.490732, - "placeopt__cpu__total": 10.11, - "placeopt__design__core__area": 185987, - "placeopt__design__die__area": 189861, - "placeopt__design__instance__area": 103105, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 103105, - "placeopt__design__instance__count": 8627, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 8627, - "placeopt__design__instance__utilization": 0.554367, - "placeopt__design__instance__utilization__stdcell": 0.554367, - "placeopt__design__io": 165, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 574852.0, - "placeopt__power__internal__total": 0.019735, - "placeopt__power__leakage__total": 9.0169e-07, - "placeopt__power__switching__total": 0.00503518, - "placeopt__power__total": 0.0247711, - "placeopt__runtime__total": "0:10.52", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00649628, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.00156941, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__ws": 1.79723, - "run__flow__design": "riscv32i", - "run__flow__generate_date": "2024-09-26 21:32", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-15807-g036379d64", - "run__flow__platform": "sky130hs", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1nW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__scripts_commit": "d505a82b2c409ec7bd0449ee0cb737219c4c8f2b", - "run__flow__uuid": "593e4535-4988-4811-bd44-843c8fb8a514", - "run__flow__variant": "odb_0925", - "synth__cpu__total": 24.1, - "synth__design__instance__area__stdcell": 84654.4608, - "synth__design__instance__count__stdcell": 6979.0, - "synth__mem__peak": 130120.0, - "synth__runtime__total": "0:24.38", - "total_time": "0:04:47.120000" -} \ No newline at end of file diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json index 8466f6d1c1..60e391e6ae 100644 --- a/flow/designs/sky130hs/riscv32i/rules-base.json +++ b/flow/designs/sky130hs/riscv32i/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 118571, + "value": 116710, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 9921, + "value": 7538, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 863, + "value": 656, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 863, + "value": 656, "compare": "<=" }, "globalroute__antenna_diodes_count": { - "value": 25, + "value": 26, "compare": "<=" }, "detailedroute__route__wirelength": { - "value": 385662, + "value": 369598, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -44,19 +44,19 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 3, + "value": 16, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.21, "compare": ">=" }, "finish__design__instance__area": { - "value": 124092, + "value": 134164, "compare": "<=" }, "finish__timing__drv__setup_violation_count": { - "value": 431, + "value": 328, "compare": "<=" }, "finish__timing__drv__hold_violation_count": { diff --git a/flow/designs/src/aes/BUILD.bazel b/flow/designs/src/aes/BUILD.bazel new file mode 100644 index 0000000000..1639cf0a3b --- /dev/null +++ b/flow/designs/src/aes/BUILD.bazel @@ -0,0 +1,5 @@ +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/.gitignore b/flow/designs/src/cva6/.gitignore new file mode 100644 index 0000000000..de874a6cdd --- /dev/null +++ b/flow/designs/src/cva6/.gitignore @@ -0,0 +1 @@ +!core diff --git a/flow/designs/src/cva6/README.md b/flow/designs/src/cva6/README.md new file mode 100644 index 0000000000..cd27453e1c --- /dev/null +++ b/flow/designs/src/cva6/README.md @@ -0,0 +1,3 @@ +Extracted from https://github.com/openhwgroup/cva6 + +Based on commit 3a389af with some changes for the RAMs diff --git a/flow/designs/src/cva6/common/local/util/sram.sv b/flow/designs/src/cva6/common/local/util/sram.sv new file mode 100644 index 0000000000..8c6c0d34d2 --- /dev/null +++ b/flow/designs/src/cva6/common/local/util/sram.sv @@ -0,0 +1,117 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba , ETH Zurich +// Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: SRAM wrapper for FPGA (requires the fpga-support submodule) +// +// Note: the wrapped module contains two different implementations for +// ALTERA and XILINX tools, since these follow different coding styles for +// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or +// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA) + +module sram #( + parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 1, + parameter USER_EN = 0, + parameter NUM_WORDS = 1024, + parameter SIM_INIT = "none", + parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) +)( + input logic clk_i, + input logic rst_ni, + input logic req_i, + input logic we_i, + input logic [$clog2(NUM_WORDS)-1:0] addr_i, + input logic [USER_WIDTH-1:0] wuser_i, + input logic [DATA_WIDTH-1:0] wdata_i, + input logic [(DATA_WIDTH+7)/8-1:0] be_i, + output logic [USER_WIDTH-1:0] ruser_o, + output logic [DATA_WIDTH-1:0] rdata_o +); + +localparam DATA_WIDTH_ALIGNED = ((DATA_WIDTH+63)/64)*64; +localparam USER_WIDTH_ALIGNED = DATA_WIDTH_ALIGNED; // To be fine tuned to reduce memory size +localparam BE_WIDTH_ALIGNED = (((DATA_WIDTH+7)/8+7)/8)*8; + +logic [DATA_WIDTH_ALIGNED-1:0] wdata_aligned; +logic [USER_WIDTH_ALIGNED-1:0] wuser_aligned; +logic [BE_WIDTH_ALIGNED-1:0] be_aligned; +logic [DATA_WIDTH_ALIGNED-1:0] rdata_aligned; +logic [USER_WIDTH_ALIGNED-1:0] ruser_aligned; + + +// align to 64 bits for inferrable macro below +always_comb begin : p_align + wdata_aligned ='0; + wuser_aligned ='0; + be_aligned ='0; + wdata_aligned[DATA_WIDTH-1:0] = wdata_i; + wuser_aligned[USER_WIDTH-1:0] = wuser_i; + be_aligned[BE_WIDTH_ALIGNED-1:0] = be_i; + + rdata_o = rdata_aligned[DATA_WIDTH-1:0]; + ruser_o = ruser_aligned[USER_WIDTH-1:0]; +end + + for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut + // unused byte-enable segments (8bits) are culled by the tool + tc_sram_wrapper #( + .NumWords(NUM_WORDS), // Number of Words in data array + .DataWidth(64), // Data signal width + .ByteWidth(32'd8), // Width of a data byte + .NumPorts(32'd1), // Number of read and write ports + .Latency(32'd1), // Latency when the read data is available + .SimInit(SIM_INIT), // Simulation initialization + .PrintSimCfg(1'b0) // Print configuration + ) i_tc_sram_wrapper ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .we_i ( we_i ), + .be_i ( be_aligned[k*8 +: 8] ), + .wdata_i ( wdata_aligned[k*64 +: 64] ), + .addr_i ( addr_i ), + .rdata_o ( rdata_aligned[k*64 +: 64] ) + ); + if (USER_EN > 0) begin : gen_mem_user + tc_sram_wrapper #( + .NumWords(NUM_WORDS), // Number of Words in data array + .DataWidth(64), // Data signal width + .ByteWidth(32'd8), // Width of a data byte + .NumPorts(32'd1), // Number of read and write ports + .Latency(32'd1), // Latency when the read data is available + .SimInit(SIM_INIT), // Simulation initialization + .PrintSimCfg(1'b0) // Print configuration + ) i_tc_sram_wrapper_user ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .we_i ( we_i ), + .be_i ( be_aligned[k*8 +: 8] ), + .wdata_i ( wuser_aligned[k*64 +: 64] ), + .addr_i ( addr_i ), + .rdata_o ( ruser_aligned[k*64 +: 64] ) + ); + end else begin : gen_mem_user + assign ruser_aligned[k*64 +: 64] = '0; + // synthesis translate_off + begin: i_tc_sram_wrapper_user + begin: i_tc_sram + localparam type data_t = logic [63:0]; + data_t init_val [0:0]; + data_t sram [NUM_WORDS-1:0] /* verilator public_flat */; + end + end + // synthesis translate_on + end + end +endmodule : sram diff --git a/flow/designs/src/cva6/common/local/util/sram_cache.sv b/flow/designs/src/cva6/common/local/util/sram_cache.sv new file mode 100644 index 0000000000..799c63afcd --- /dev/null +++ b/flow/designs/src/cva6/common/local/util/sram_cache.sv @@ -0,0 +1,144 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba , ETH Zurich +// Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: SRAM wrapper for FPGA (requires the fpga-support submodule) +// +// Note: the wrapped module contains two different implementations for +// ALTERA and XILINX tools, since these follow different coding styles for +// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or +// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA) + +module sram_cache #( + parameter DATA_WIDTH = 64, + parameter USER_WIDTH = 1, + parameter USER_EN = 0, + parameter NUM_WORDS = 1024, + parameter SIM_INIT = "none", + parameter BYTE_ACCESS = 1, + parameter TECHNO_CUT = 0, + parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) +)( + input logic clk_i, + input logic rst_ni, + input logic req_i, + input logic we_i, + input logic [$clog2(NUM_WORDS)-1:0] addr_i, + input logic [USER_WIDTH-1:0] wuser_i, + input logic [DATA_WIDTH-1:0] wdata_i, + input logic [(DATA_WIDTH+7)/8-1:0] be_i, + output logic [USER_WIDTH-1:0] ruser_o, + output logic [DATA_WIDTH-1:0] rdata_o +); + localparam DATA_AND_USER_WIDTH = USER_EN ? DATA_WIDTH + USER_WIDTH : DATA_WIDTH; + if (TECHNO_CUT) begin : gen_techno_cut + if (USER_EN > 0) begin + logic [DATA_WIDTH + USER_WIDTH-1:0] wdata_user; + logic [DATA_WIDTH + USER_WIDTH-1:0] rdata_user; + logic [(DATA_WIDTH+7)/8+(DATA_WIDTH+7)/8-1:0] be; + + always_comb begin + wdata_user = {wdata_i, wuser_i}; + be = {be_i, be_i}; + rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH]; + ruser_o = rdata_user[USER_WIDTH-1:0]; + end + fakeram7_64x256 i_tc_sram_wrapper( + .clk ( clk_i ), + .ce_in ( req_i ), + .we_in ( we_i ), + .wd_in ( wdata_user ), + .addr_in ( addr_i ), + .rd_out ( rdata_user ) + ); + + // tc_sram_wrapper_cache_techno #( + // .NumWords(NUM_WORDS), // Number of Words in data array + // .DataWidth(DATA_AND_USER_WIDTH),// Data signal width + // .ByteWidth(32'd8), // Width of a data byte + // .NumPorts(32'd1), // Number of read and write ports + // .Latency(32'd1), // Latency when the read data is available + // .SimInit(SIM_INIT), // Simulation initialization + // .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word + // .PrintSimCfg(1'b0) // Print configuration + // ) i_tc_sram_wrapper ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_ni ), + // .req_i ( req_i ), + // .we_i ( we_i ), + // .be_i ( be ), + // .wdata_i ( wdata_user ), + // .addr_i ( addr_i ), + // .rdata_o ( rdata_user ) + // ); + end else begin + logic [DATA_WIDTH-1:0] wdata_user; + logic [DATA_WIDTH-1:0] rdata_user; + logic [(DATA_WIDTH+7)/8-1:0] be; + + always_comb begin + wdata_user = wdata_i; + be = be_i; + rdata_o = rdata_user; + ruser_o = '0; + end + fakeram7_64x25 i_tc_sram_wrapper( + .clk ( clk_i ), + .ce_in ( req_i ), + .we_in ( we_i ), + .wd_in ( wdata_user ), + .addr_in ( addr_i ), + .rd_out ( rdata_user ) + ); + + // tc_sram_wrapper_cache_techno #( + // .NumWords(NUM_WORDS), // Number of Words in data array + // .DataWidth(DATA_AND_USER_WIDTH),// Data signal width + // .ByteWidth(32'd8), // Width of a data byte + // .NumPorts(32'd1), // Number of read and write ports + // .Latency(32'd1), // Latency when the read data is available + // .SimInit(SIM_INIT), // Simulation initialization + // .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word + // .PrintSimCfg(1'b0) // Print configuration + // ) i_tc_sram_wrapper ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_ni ), + // .req_i ( req_i ), + // .we_i ( we_i ), + // .be_i ( be ), + // .wdata_i ( wdata_user ), + // .addr_i ( addr_i ), + // .rdata_o ( rdata_user ) + // ); + end + end else begin + sram #( + .USER_WIDTH (USER_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .USER_EN (USER_EN), + .NUM_WORDS (NUM_WORDS) + ) data_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (req_i), + .we_i (we_i), + .addr_i (addr_i), + .wuser_i(wuser_i), + .wdata_i(wdata_i), + .be_i (be_i), + .ruser_o(ruser_o), + .rdata_o(rdata_o) + ); + end + + +endmodule : sram_cache diff --git a/flow/designs/src/cva6/common/local/util/tc_sram_wrapper.sv b/flow/designs/src/cva6/common/local/util/tc_sram_wrapper.sv new file mode 100644 index 0000000000..ae3287d93f --- /dev/null +++ b/flow/designs/src/cva6/common/local/util/tc_sram_wrapper.sv @@ -0,0 +1,60 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +module tc_sram_wrapper #( + parameter int unsigned NumWords = 32'd1024, // Number of Words in data array + parameter int unsigned DataWidth = 32'd128, // Data signal width + parameter int unsigned ByteWidth = 32'd8, // Width of a data byte + parameter int unsigned NumPorts = 32'd2, // Number of read and write ports + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter bit PrintSimCfg = 1'b0, // Print configuration + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type be_t = logic [BeWidth-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable + input addr_t [NumPorts-1:0] addr_i, // request address + input data_t [NumPorts-1:0] wdata_i, // write data + input be_t [NumPorts-1:0] be_i, // write byte enable + // output ports + output data_t [NumPorts-1:0] rdata_o // read data +); + +// synthesis translate_off + + tc_sram #( + .NumWords(NumWords), + .DataWidth(DataWidth), + .ByteWidth(ByteWidth), + .NumPorts(NumPorts), + .Latency(Latency), + .SimInit(SimInit), + .PrintSimCfg(PrintSimCfg) + ) i_tc_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .we_i ( we_i ), + .be_i ( be_i ), + .wdata_i ( wdata_i ), + .addr_i ( addr_i ), + .rdata_o ( rdata_o ) + ); + +// synthesis translate_on + +endmodule diff --git a/flow/designs/src/cva6/common/local/util/tc_sram_wrapper_cache_techno.sv b/flow/designs/src/cva6/common/local/util/tc_sram_wrapper_cache_techno.sv new file mode 100644 index 0000000000..31868b5457 --- /dev/null +++ b/flow/designs/src/cva6/common/local/util/tc_sram_wrapper_cache_techno.sv @@ -0,0 +1,64 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +// Copy of tc_sram_wrapper_cache +// To be replaced by the wrapper of the technology used to avoid having black box at synthesis + +module tc_sram_wrapper_cache_techno #( + parameter int unsigned NumWords = 32'd1024, // Number of Words in data array + parameter int unsigned DataWidth = 32'd128, // Data signal width + parameter int unsigned ByteWidth = 32'd8, // Width of a data byte + parameter int unsigned NumPorts = 32'd2, // Number of read and write ports + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter BYTE_ACCESS = 1, + parameter bit PrintSimCfg = 1'b0, // Print configuration + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type be_t = logic [BeWidth-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable + input addr_t [NumPorts-1:0] addr_i, // request address + input data_t [NumPorts-1:0] wdata_i, // write data + input be_t [NumPorts-1:0] be_i, // write byte enable + // output ports + output data_t [NumPorts-1:0] rdata_o // read data +); + +// synthesis translate_off + + tc_sram #( + .NumWords(NumWords), + .DataWidth(DataWidth), + .ByteWidth(ByteWidth), + .NumPorts(NumPorts), + .Latency(Latency), + .SimInit(SimInit), + .PrintSimCfg(PrintSimCfg) + ) i_tc_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req_i ), + .we_i ( we_i ), + .be_i ( be_i ), + .wdata_i ( wdata_i ), + .addr_i ( addr_i ), + .rdata_o ( rdata_o ) + ); + +// synthesis translate_on + +endmodule diff --git a/flow/designs/src/cva6/core/acc_dispatcher.sv b/flow/designs/src/cva6/core/acc_dispatcher.sv new file mode 100644 index 0000000000..aa526951e6 --- /dev/null +++ b/flow/designs/src/cva6/core/acc_dispatcher.sv @@ -0,0 +1,446 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: Matheus Cavalcante, ETH Zurich +// Nils Wistoff, ETH Zurich +// Date: 20.11.2020 +// Description: Functional unit that dispatches CVA6 instructions to accelerators. + +module acc_dispatcher + import ariane_pkg::*; + import riscv::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type fu_data_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type acc_req_t = logic, + parameter type acc_resp_t = logic, + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + parameter type acc_cfg_t = logic, + parameter acc_cfg_t AccCfg = '0 +) ( + input logic clk_i, + input logic rst_ni, + // Interface with the CSR regfile + input logic acc_cons_en_i, // Accelerator memory consistent mode + output logic acc_fflags_valid_o, + output logic [4:0] acc_fflags_o, + // Interface with the CSRs + input priv_lvl_t ld_st_priv_lvl_i, + input logic sum_i, + input pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [2:0] fcsr_frm_i, + output logic dirty_v_state_o, + input logic acc_mmu_en_i, + // Interface with the issue stage + input scoreboard_entry_t issue_instr_i, + input logic issue_instr_hs_i, + output logic issue_stall_o, + input fu_data_t fu_data_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] acc_trans_id_o, + output logic [CVA6Cfg.XLEN-1:0] acc_result_o, + output logic acc_valid_o, + output exception_t acc_exception_o, + // Interface with the execute stage + output logic acc_valid_ex_o, // FU executed + // Interface with the commit stage + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic commit_st_barrier_i, // A store barrier was commited + // Interface with the load/store unit + output logic acc_stall_st_pending_o, + input logic acc_no_st_pending_i, + input dcache_req_i_t [2:0] dcache_req_ports_i, + // Interface with the MMU + output acc_mmu_req_t acc_mmu_req_o, + input acc_mmu_resp_t acc_mmu_resp_i, + // Interface with the controller + output logic ctrl_halt_o, + input logic [11:0] csr_addr_i, + input logic flush_unissued_instr_i, + input logic flush_ex_i, + output logic flush_pipeline_o, + output logic single_step_o, + // Interface with cache subsystem + output dcache_req_i_t [1:0] acc_dcache_req_ports_o, + input dcache_req_o_t [1:0] acc_dcache_req_ports_i, + input logic inval_ready_i, + output logic inval_valid_o, + output logic [63:0] inval_addr_o, + // Accelerator interface + output acc_req_t acc_req_o, + input acc_resp_t acc_resp_i +); + + `include "common_cells/registers.svh" + + import cf_math_pkg::idx_width; + + /*********************** + * Common signals * + ***********************/ + + logic acc_ready; + logic acc_valid_d, acc_valid_q; + + /************************** + * Accelerator issue * + **************************/ + + // Issue accelerator instructions + `FF(acc_valid_q, acc_valid_d, '0) + + assign acc_valid_ex_o = acc_valid_q; + assign acc_valid_d = ~issue_instr_i.ex.valid & + issue_instr_hs_i & + (issue_instr_i.fu == ACCEL) & + ~flush_unissued_instr_i; + + // Accelerator load/store pending signals + logic acc_no_ld_pending; + logic acc_no_st_pending; + + // Stall issue stage in three cases: + always_comb begin : stall_issue + unique case (issue_instr_i.fu) + ACCEL: + // 1. We're issuing an accelerator instruction but the dispatcher isn't ready yet + issue_stall_o = ~acc_ready; + LOAD: + // 2. We're issuing a scalar load but there is an inflight accelerator store. + issue_stall_o = acc_cons_en_i & ~acc_no_st_pending; + STORE: + // 3. We're issuing a scalar store but there is an inflight accelerator load or store. + issue_stall_o = acc_cons_en_i & (~acc_no_st_pending | ~acc_no_ld_pending); + default: issue_stall_o = 1'b0; + endcase + end + + /*********************** + * Instruction queue * + ***********************/ + + localparam InstructionQueueDepth = 3; + + fu_data_t acc_data; + fu_data_t acc_insn_queue_o; + logic acc_insn_queue_pop; + logic acc_insn_queue_empty; + logic [idx_width(InstructionQueueDepth)-1:0] acc_insn_queue_usage; + logic acc_commit; + logic [ CVA6Cfg.TRANS_ID_BITS-1:0] acc_commit_trans_id; + + assign acc_data = acc_valid_ex_o ? fu_data_i : '0; + + cva6_fifo_v3 #( + .DEPTH (InstructionQueueDepth), + .FALL_THROUGH(1'b1), + .dtype (fu_data_t), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_acc_insn_queue ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_ex_i), + .testmode_i(1'b0), + .data_i (fu_data_i), + .push_i (acc_valid_q), + .full_o ( /* Unused */), + .data_o (acc_insn_queue_o), + .pop_i (acc_insn_queue_pop), + .empty_o (acc_insn_queue_empty), + .usage_o (acc_insn_queue_usage) + ); + + // We are ready if the instruction queue is able to accept at least one more entry. + assign acc_ready = acc_insn_queue_usage < (InstructionQueueDepth - 1); + + /********************************** + * Non-speculative instructions * + **********************************/ + + // Keep track of the instructions that were received by the dispatcher. + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_pending_d, insn_pending_q; + `FF(insn_pending_q, insn_pending_d, '0) + + // Only non-speculative instructions can be issued to the accelerators. + // The following block keeps track of which transaction IDs reached the + // top of the scoreboard, and are therefore no longer speculative. + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_ready_d, insn_ready_q; + `FF(insn_ready_q, insn_ready_d, '0) + + always_comb begin : p_non_speculative_ff + // Maintain state + insn_pending_d = insn_pending_q; + insn_ready_d = insn_ready_q; + + // We received a new instruction + if (acc_valid_q) insn_pending_d[acc_data.trans_id] = 1'b1; + // Flush all received instructions + if (flush_ex_i) insn_pending_d = '0; + + // An accelerator instruction is no longer speculative. + if (acc_commit && insn_pending_q[acc_commit_trans_id]) begin + insn_ready_d[acc_commit_trans_id] = 1'b1; + insn_pending_d[acc_commit_trans_id] = 1'b0; + end + + // An accelerator instruction was issued. + if (acc_req_o.acc_req.req_valid) insn_ready_d[acc_req_o.acc_req.trans_id] = 1'b0; + end : p_non_speculative_ff + + /************************* + * Accelerator request * + *************************/ + + accelerator_req_t acc_req; + logic acc_req_valid; + logic acc_req_ready; + + accelerator_req_t acc_req_int; + spill_register #( + .T(accelerator_req_t) + ) i_accelerator_req_register ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .data_i (acc_req), + .valid_i(acc_req_valid), + .ready_o(acc_req_ready), + .data_o (acc_req_int), + .valid_o(acc_req_o.acc_req.req_valid), + .ready_i(acc_resp_i.acc_resp.req_ready) + ); + + assign acc_req_o.acc_req.insn = acc_req_int.insn; + assign acc_req_o.acc_req.rs1 = acc_req_int.rs1; + assign acc_req_o.acc_req.rs2 = acc_req_int.rs2; + assign acc_req_o.acc_req.frm = acc_req_int.frm; + assign acc_req_o.acc_req.trans_id = acc_req_int.trans_id; + assign acc_req_o.acc_req.store_pending = !acc_no_st_pending_i && acc_cons_en_i; + assign acc_req_o.acc_req.acc_cons_en = acc_cons_en_i; + assign acc_req_o.acc_req.inval_ready = inval_ready_i; + + // MMU interface + assign acc_req_o.acc_mmu_resp = acc_mmu_resp_i; + assign acc_req_o.acc_mmu_en = acc_mmu_en_i; + + always_comb begin : accelerator_req_dispatcher + // Do not fetch from the instruction queue + acc_insn_queue_pop = 1'b0; + + // Default values + acc_req = '0; + acc_req_valid = 1'b0; + + // Unpack fu_data_t into acc_req_t + if (!acc_insn_queue_empty) begin + acc_req = '{ + // Instruction is forwarded from the decoder as an immediate + // - + // frm rounding information is up to date during a valid request to the accelerator + // The scoreboard synchronizes it with previous fcsr writes, and future fcsr writes + // do not take place until the accelerator answers (Ariane commits in-order) + insn : + acc_insn_queue_o.imm[ + 31 + : + 0 + ], + rs1 : acc_insn_queue_o.operand_a, + rs2 : acc_insn_queue_o.operand_b, + frm : fpnew_pkg::roundmode_e'(fcsr_frm_i), + trans_id: acc_insn_queue_o.trans_id, + default: '0 + }; + // Wait until the instruction is no longer speculative. + acc_req_valid = insn_ready_q[acc_insn_queue_o.trans_id] || + (acc_commit && insn_pending_q[acc_commit_trans_id] && !flush_unissued_instr_i); + acc_insn_queue_pop = acc_req_valid && acc_req_ready; + end + end + + /************************** + * Accelerator response * + **************************/ + + logic acc_ld_disp; + logic acc_st_disp; + + assign acc_trans_id_o = acc_resp_i.acc_resp.trans_id; + assign acc_result_o = acc_resp_i.acc_resp.result; + assign acc_valid_o = acc_resp_i.acc_resp.resp_valid; + assign acc_exception_o = acc_resp_i.acc_resp.exception; + // Unpack the accelerator response + assign acc_fflags_valid_o = acc_resp_i.acc_resp.fflags_valid; + assign acc_fflags_o = acc_resp_i.acc_resp.fflags; + + // MMU interface + assign acc_mmu_req_o = acc_resp_i.acc_mmu_req; + + // Always ready to receive responses + assign acc_req_o.acc_req.resp_ready = 1'b1; + + // Signal dispatched load/store to issue stage + assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); + assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); + + // Cache invalidation + assign inval_valid_o = acc_resp_i.acc_resp.inval_valid; + assign inval_addr_o = acc_resp_i.acc_resp.inval_addr; + + /************************** + * Accelerator commit * + **************************/ + + // Instruction can be issued to the (in-order) back-end if + // it reached the top of the scoreboard and it hasn't been + // issued yet + always_comb begin : accelerator_commit + acc_commit = 1'b0; + if (!commit_instr_i[0].valid && commit_instr_i[0].fu == ACCEL) acc_commit = 1'b1; + if (commit_instr_i[0].valid && !commit_instr_i[1].valid && commit_instr_i[1].fu == ACCEL) + acc_commit = 1'b1; + end + + // Dirty the V state if we are committing anything related to the vector accelerator + always_comb begin : dirty_v_state + dirty_v_state_o = 1'b0; + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + dirty_v_state_o |= commit_ack_i[i] & (commit_instr_i[i].fu == ACCEL); + end + end + + assign acc_commit_trans_id = !commit_instr_i[0].valid ? commit_instr_i[0].trans_id + : commit_instr_i[1].trans_id; + + /************************** + * Accelerator barriers * + **************************/ + + // On a store barrier (i.e. any barrier that requires preceeding stores to complete + // before continuing execution), halt execution while there are pending stores in + // the accelerator pipeline. + logic wait_acc_store_d, wait_acc_store_q; + `FF(wait_acc_store_q, wait_acc_store_d, '0) + + // Set on store barrier. Clear when no store is pending. + assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.acc_resp.store_pending; + assign ctrl_halt_o = wait_acc_store_q; + + /************************** + * Load/Store tracking * + **************************/ + + // Loads + logic acc_spec_loads_overflow; + logic [2:0] acc_spec_loads_pending; + logic acc_disp_loads_overflow; + logic [2:0] acc_disp_loads_pending; + + assign acc_no_ld_pending = (acc_spec_loads_pending == 3'b0) && (acc_disp_loads_pending == 3'b0); + + // Count speculative loads. These can still be flushed. + counter #( + .WIDTH (3), + .STICKY_OVERFLOW(0) + ) i_acc_spec_loads ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clear_i (flush_ex_i), + .en_i ((acc_valid_d && issue_instr_i.op == ACCEL_OP_LOAD) ^ acc_ld_disp), + .load_i (1'b0), + .down_i (acc_ld_disp), + .d_i ('0), + .q_o (acc_spec_loads_pending), + .overflow_o(acc_spec_loads_overflow) + ); + + // Count dispatched loads. These cannot be flushed anymore. + counter #( + .WIDTH (3), + .STICKY_OVERFLOW(0) + ) i_acc_disp_loads ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clear_i (1'b0), + .en_i (acc_ld_disp ^ acc_resp_i.acc_resp.load_complete), + .load_i (1'b0), + .down_i (acc_resp_i.acc_resp.load_complete), + .d_i ('0), + .q_o (acc_disp_loads_pending), + .overflow_o(acc_disp_loads_overflow) + ); + + acc_dispatcher_no_load_overflow : + assert property ( + @(posedge clk_i) disable iff (~rst_ni) (acc_spec_loads_overflow == 1'b0) && (acc_disp_loads_overflow == 1'b0) ) + else $error("[acc_dispatcher] Too many pending loads."); + + // Stores + logic acc_spec_stores_overflow; + logic [2:0] acc_spec_stores_pending; + logic acc_disp_stores_overflow; + logic [2:0] acc_disp_stores_pending; + + assign acc_no_st_pending = (acc_spec_stores_pending == 3'b0) && (acc_disp_stores_pending == 3'b0); + + // Count speculative stores. These can still be flushed. + counter #( + .WIDTH (3), + .STICKY_OVERFLOW(0) + ) i_acc_spec_stores ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clear_i (flush_ex_i), + .en_i ((acc_valid_d && issue_instr_i.op == ACCEL_OP_STORE) ^ acc_st_disp), + .load_i (1'b0), + .down_i (acc_st_disp), + .d_i ('0), + .q_o (acc_spec_stores_pending), + .overflow_o(acc_spec_stores_overflow) + ); + + // Count dispatched stores. These cannot be flushed anymore. + counter #( + .WIDTH (3), + .STICKY_OVERFLOW(0) + ) i_acc_disp_stores ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clear_i (1'b0), + .en_i (acc_st_disp ^ acc_resp_i.acc_resp.store_complete), + .load_i (1'b0), + .down_i (acc_resp_i.acc_resp.store_complete), + .d_i ('0), + .q_o (acc_disp_stores_pending), + .overflow_o(acc_disp_stores_overflow) + ); + + acc_dispatcher_no_store_overflow : + assert property ( + @(posedge clk_i) disable iff (~rst_ni) (acc_spec_stores_overflow == 1'b0) && (acc_disp_stores_overflow == 1'b0) ) + else $error("[acc_dispatcher] Too many pending stores."); + + /************************** + * Tie Off Unused Signals * + **************************/ + + assign acc_stall_st_pending_o = 1'b0; + assign flush_pipeline_o = 1'b0; + assign single_step_o = 1'b0; + assign acc_dcache_req_ports_o = '0; + +endmodule : acc_dispatcher diff --git a/flow/designs/src/cva6/core/alu.sv b/flow/designs/src/cva6/core/alu.sv new file mode 100644 index 0000000000..9f69f6ef93 --- /dev/null +++ b/flow/designs/src/cva6/core/alu.sv @@ -0,0 +1,405 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Matthias Baer +// Author: Igor Loi +// Author: Andreas Traber +// Author: Lukas Mueller +// Author: Florian Zaruba +// +// Date: 19.03.2017 +// Description: Ariane ALU based on RI5CY's ALU + + +module alu + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit HasBranch = 1'b1, + parameter type fu_data_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // ALU result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] result_o, + // ALU branch compare result - branch_unit + output logic alu_branch_res_o +); + + logic [CVA6Cfg.XLEN-1:0] operand_a_rev; + logic [ 31:0] operand_a_rev32; + logic [ CVA6Cfg.XLEN:0] operand_b_neg; + logic [CVA6Cfg.XLEN+1:0] adder_result_ext_o; + logic less; // handles both signed and unsigned forms + logic [ 31:0] rolw; // Rotate Left Word + logic [ 31:0] rorw; // Rotate Right Word + logic [31:0] orcbw, rev8w; + logic [ $clog2(CVA6Cfg.XLEN) : 0] cpop; // Count Population + logic [$clog2(CVA6Cfg.XLEN)-1 : 0] lz_tz_count; // Count Leading Zeros + logic [ 4:0] lz_tz_wcount; // Count Leading Zeros Word + logic lz_tz_empty, lz_tz_wempty; + logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result; + + logic [CVA6Cfg.XLEN-1:0] brev8_reversed; + logic [ 31:0] unzip_gen; + logic [ 31:0] zip_gen; + // bit reverse operand_a for left shifts and bit counting + generate + genvar k; + for (k = 0; k < CVA6Cfg.XLEN; k++) + assign operand_a_rev[k] = fu_data_i.operand_a[CVA6Cfg.XLEN-1-k]; + + for (k = 0; k < 32; k++) assign operand_a_rev32[k] = fu_data_i.operand_a[31-k]; + endgenerate + + // ------ + // Adder + // ------ + logic adder_op_b_negate; + logic adder_z_flag; + logic [CVA6Cfg.XLEN:0] adder_in_a, adder_in_b; + logic [CVA6Cfg.XLEN-1:0] adder_result; + logic [CVA6Cfg.XLEN-1:0] operand_a_bitmanip, bit_indx; + + assign adder_op_b_negate = fu_data_i.operation inside {EQ, NE, SUB, SUBW, ANDN, ORN, XNOR}; + + always_comb begin + operand_a_bitmanip = fu_data_i.operand_a; + + if (CVA6Cfg.RVB) begin + if (CVA6Cfg.IS_XLEN64) begin + unique case (fu_data_i.operation) + SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1; + SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2; + SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3; + CTZW: operand_a_bitmanip = operand_a_rev32; + ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0]; + default: ; + endcase + end + unique case (fu_data_i.operation) + SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1; + SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2; + SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3; + CTZ: operand_a_bitmanip = operand_a_rev; + default: ; + endcase + end + end + + // prepare operand a + assign adder_in_a = {operand_a_bitmanip, 1'b1}; + + // prepare operand b + assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {CVA6Cfg.XLEN + 1{adder_op_b_negate}}; + assign adder_in_b = operand_b_neg; + + // actual adder + assign adder_result_ext_o = adder_in_a + adder_in_b; + assign adder_result = adder_result_ext_o[CVA6Cfg.XLEN:1]; + assign adder_z_flag = ~|adder_result; + + // get the right branch comparison result + if (HasBranch) begin + always_comb begin : branch_resolve + // set comparison by default + case (fu_data_i.operation) + EQ: alu_branch_res_o = adder_z_flag; + NE: alu_branch_res_o = ~adder_z_flag; + LTS, LTU: alu_branch_res_o = less; + GES, GEU: alu_branch_res_o = ~less; + default: alu_branch_res_o = 1'b1; + endcase + end + end else begin + assign alu_branch_res_o = 1'b0; + end + + // --------- + // Shifts + // --------- + + // TODO: this can probably optimized significantly + logic shift_left; // should we shift left + logic shift_arithmetic; + + logic [CVA6Cfg.XLEN-1:0] shift_amt; // amount of shift, to the right + logic [CVA6Cfg.XLEN-1:0] shift_op_a; // input of the shifter + logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation + + logic [CVA6Cfg.XLEN-1:0] shift_result; + logic [ 31:0] shift_result32; + + logic [ CVA6Cfg.XLEN:0] shift_right_result; + logic [ 32:0] shift_right_result32; + + logic [CVA6Cfg.XLEN-1:0] shift_left_result; + logic [ 31:0] shift_left_result32; + + assign shift_amt = fu_data_i.operand_b; + + assign shift_left = (fu_data_i.operation == SLL) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SLLW); + + assign shift_arithmetic = (fu_data_i.operation == SRA) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SRAW); + + // right shifts, we let the synthesizer optimize this + logic [CVA6Cfg.XLEN:0] shift_op_a_64; + logic [32:0] shift_op_a_32; + + // choose the bit reversed or the normal input for shift operand a + assign shift_op_a = shift_left ? operand_a_rev : fu_data_i.operand_a; + assign shift_op_a32 = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0]; + + assign shift_op_a_64 = {shift_arithmetic & shift_op_a[CVA6Cfg.XLEN-1], shift_op_a}; + assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a32}; + + assign shift_right_result = $unsigned($signed(shift_op_a_64) >>> shift_amt[5:0]); + + assign shift_right_result32 = $unsigned($signed(shift_op_a_32) >>> shift_amt[4:0]); + // bit reverse the shift_right_result for left shifts + genvar j; + generate + for (j = 0; j < CVA6Cfg.XLEN; j++) + assign shift_left_result[j] = shift_right_result[CVA6Cfg.XLEN-1-j]; + + for (j = 0; j < 32; j++) assign shift_left_result32[j] = shift_right_result32[31-j]; + + endgenerate + + assign shift_result = shift_left ? shift_left_result : shift_right_result[CVA6Cfg.XLEN-1:0]; + assign shift_result32 = shift_left ? shift_left_result32 : shift_right_result32[31:0]; + + // ------------ + // Comparisons + // ------------ + + always_comb begin + logic sgn; + sgn = 1'b0; + + if ((fu_data_i.operation == SLTS) || + (fu_data_i.operation == LTS) || + (fu_data_i.operation == GES) || + (fu_data_i.operation == MAX) || + (fu_data_i.operation == MIN)) + sgn = 1'b1; + + less = ($signed({sgn & fu_data_i.operand_a[CVA6Cfg.XLEN-1], fu_data_i.operand_a}) < + $signed({sgn & fu_data_i.operand_b[CVA6Cfg.XLEN-1], fu_data_i.operand_b})); + end + + if (CVA6Cfg.RVB) begin : gen_bitmanip + // Count Population + Count population Word + + popcount #( + .INPUT_WIDTH(CVA6Cfg.XLEN) + ) i_cpop_count ( + .data_i (operand_a_bitmanip), + .popcount_o(cpop) + ); + + // Count Leading/Trailing Zeros + // 64b + lzc #( + .WIDTH(CVA6Cfg.XLEN), + .MODE (1) + ) i_clz_64b ( + .in_i(operand_a_bitmanip), + .cnt_o(lz_tz_count), + .empty_o(lz_tz_empty) + ); + if (CVA6Cfg.IS_XLEN64) begin + //32b + lzc #( + .WIDTH(32), + .MODE (1) + ) i_clz_32b ( + .in_i(operand_a_bitmanip[31:0]), + .cnt_o(lz_tz_wcount), + .empty_o(lz_tz_wempty) + ); + end + end + + if (CVA6Cfg.RVB) begin : gen_orcbw_rev8w_results + assign orcbw = { + {8{|fu_data_i.operand_a[31:24]}}, + {8{|fu_data_i.operand_a[23:16]}}, + {8{|fu_data_i.operand_a[15:8]}}, + {8{|fu_data_i.operand_a[7:0]}} + }; + assign rev8w = { + {fu_data_i.operand_a[7:0]}, + {fu_data_i.operand_a[15:8]}, + {fu_data_i.operand_a[23:16]}, + {fu_data_i.operand_a[31:24]} + }; + if (CVA6Cfg.IS_XLEN64) begin : gen_64b + assign orcbw_result = { + {8{|fu_data_i.operand_a[63:56]}}, + {8{|fu_data_i.operand_a[55:48]}}, + {8{|fu_data_i.operand_a[47:40]}}, + {8{|fu_data_i.operand_a[39:32]}}, + orcbw + }; + assign rev8w_result = { + rev8w, + {fu_data_i.operand_a[39:32]}, + {fu_data_i.operand_a[47:40]}, + {fu_data_i.operand_a[55:48]}, + {fu_data_i.operand_a[63:56]} + }; + end else begin : gen_32b + assign orcbw_result = orcbw; + assign rev8w_result = rev8w; + end + end + + // ZKN gen block + if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block + genvar i, m, n; + // Generate brev8_reversed by reversing bits within each byte + for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen + for (m = 0; m < 8; m++) begin : reverse_bits + // Reversing the order of bits within a single byte + assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)]; + end + end + // Generate zip and unzip results + if (CVA6Cfg.IS_XLEN32) begin + for (n = 0; n < 16; n++) begin : zip_unzip_gen + // Assigning lower and upper half of operand into the even and odd positions of result + assign zip_gen[n<<1] = fu_data_i.operand_a[n]; + assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16]; + // Assigning even and odd bits of operand into lower and upper halves of result + assign unzip_gen[n] = fu_data_i.operand_a[n<<1]; + assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1]; + end + end + end + + // ----------- + // Result MUX + // ----------- + always_comb begin + result_o = '0; + if (CVA6Cfg.IS_XLEN64) begin + unique case (fu_data_i.operation) + // Add word: Ignore the upper bits and sign extend to 64 bit + ADDW, SUBW: result_o = {{CVA6Cfg.XLEN - 32{adder_result[31]}}, adder_result[31:0]}; + SH1ADDUW, SH2ADDUW, SH3ADDUW: result_o = adder_result; + // Shifts 32 bit + SLLW, SRLW, SRAW: + result_o = {{CVA6Cfg.XLEN - 32{shift_result32[31]}}, shift_result32[31:0]}; + default: ; + endcase + end + unique case (fu_data_i.operation) + // Standard Operations + ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[CVA6Cfg.XLEN:1]; + ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[CVA6Cfg.XLEN:1]; + XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[CVA6Cfg.XLEN:1]; + // Adder Operations + ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result; + // Shift Operations + SLL, SRL, SRA: result_o = (CVA6Cfg.IS_XLEN64) ? shift_result : shift_result32; + // Comparison Operations + SLTS, SLTU: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, less}; + default: ; // default case to suppress unique warning + endcase + + if (CVA6Cfg.RVB) begin + // Index for Bitwise Rotation + bit_indx = 1 << (fu_data_i.operand_b & (CVA6Cfg.XLEN - 1)); + if (CVA6Cfg.IS_XLEN64) begin + // rolw, roriw, rorw + rolw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0])); + rorw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0])); + unique case (fu_data_i.operation) + CLZW, CTZW: + result_o = (lz_tz_wempty) ? 32 : {{CVA6Cfg.XLEN - 5{1'b0}}, lz_tz_wcount}; // change + ROLW: result_o = {{CVA6Cfg.XLEN - 32{rolw[31]}}, rolw}; + RORW, RORIW: result_o = {{CVA6Cfg.XLEN - 32{rorw[31]}}, rorw}; + default: ; + endcase + end + unique case (fu_data_i.operation) + // Integer minimum/maximum + MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; + MAXU: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; + MIN: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a; + MINU: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a; + + // Single bit instructions operations + BCLR, BCLRI: result_o = fu_data_i.operand_a & ~bit_indx; + BEXT, BEXTI: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, |(fu_data_i.operand_a & bit_indx)}; + BINV, BINVI: result_o = fu_data_i.operand_a ^ bit_indx; + BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx; + + // Count Leading/Trailing Zeros + CLZ, CTZ: + result_o = (lz_tz_empty) ? ({{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count} + 1) + : {{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count}; + + // Count population + CPOP, CPOPW: result_o = {{(CVA6Cfg.XLEN - ($clog2(CVA6Cfg.XLEN) + 1)) {1'b0}}, cpop}; + + // Sign and Zero Extend + SEXTB: result_o = {{CVA6Cfg.XLEN - 8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]}; + SEXTH: result_o = {{CVA6Cfg.XLEN - 16{fu_data_i.operand_a[15]}}, fu_data_i.operand_a[15:0]}; + ZEXTH: result_o = {{CVA6Cfg.XLEN - 16{1'b0}}, fu_data_i.operand_a[15:0]}; + + // Bitwise Rotation + ROL: + result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0]))); + + ROR, RORI: + result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0]))); + + ORCB: result_o = orcbw_result; + REV8: result_o = rev8w_result; + + default: + if (fu_data_i.operation == SLLIUW && CVA6Cfg.IS_XLEN64) + result_o = {{CVA6Cfg.XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned + endcase + end + if (CVA6Cfg.RVZiCond) begin + unique case (fu_data_i.operation) + CZERO_EQZ: + result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1 + CZERO_NEZ: + result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1 + default: ; // default case to suppress unique warning + endcase + end + // ZKN instructions + if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin + unique case (fu_data_i.operation) + PACK: + result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]}); + PACK_H: + result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}); + BREV8: result_o = brev8_reversed; + default: ; + endcase + if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) + result_o = { + {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]} + }; + if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen; + if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/amo_buffer.sv b/flow/designs/src/cva6/core/amo_buffer.sv new file mode 100644 index 0000000000..8aca2a13eb --- /dev/null +++ b/flow/designs/src/cva6/core/amo_buffer.sv @@ -0,0 +1,83 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 20.09.2018 +// Description: Buffers AMO requests +// This unit buffers an atomic memory operations for the cache subsyste. +// Furthermore it handles interfacing with the commit stage + +module amo_buffer #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // pipeline flush + + input logic valid_i, // AMO is valid + output logic ready_o, // AMO unit is ready + input ariane_pkg::amo_t amo_op_i, // AMO Operation + input logic [CVA6Cfg.PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue + input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue + input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) + // D$ + output ariane_pkg::amo_req_t amo_req_o, // request to cache subsytem + input ariane_pkg::amo_resp_t amo_resp_i, // response from cache subsystem + // Auxiliary signals + input logic amo_valid_commit_i, // We have a vaild AMO in the commit stage + input logic no_st_pending_i // there is currently no store pending anymore +); + logic flush_amo_buffer; + logic amo_valid; + + typedef struct packed { + ariane_pkg::amo_t op; + logic [CVA6Cfg.PLEN-1:0] paddr; + logic [CVA6Cfg.XLEN-1:0] data; + logic [1:0] size; + } amo_op_t; + + amo_op_t amo_data_in, amo_data_out; + + // validate this request as soon as all stores have drained and the AMO is in the commit stage + assign amo_req_o.req = no_st_pending_i & amo_valid_commit_i & amo_valid; + assign amo_req_o.amo_op = amo_data_out.op; + assign amo_req_o.size = amo_data_out.size; + assign amo_req_o.operand_a = {{64 - CVA6Cfg.PLEN{1'b0}}, amo_data_out.paddr}; + assign amo_req_o.operand_b = {{64 - CVA6Cfg.XLEN{1'b0}}, amo_data_out.data}; + + assign amo_data_in.op = amo_op_i; + assign amo_data_in.data = data_i; + assign amo_data_in.paddr = paddr_i; + assign amo_data_in.size = data_size_i; + + // only flush if we are currently not committing the AMO + // e.g.: it is not speculative anymore + assign flush_amo_buffer = flush_i & !amo_valid_commit_i; + + cva6_fifo_v3 #( + .DEPTH (1), + .dtype (amo_op_t), + .FPGA_EN(CVA6Cfg.FpgaEn) + ) i_amo_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_amo_buffer), + .testmode_i(1'b0), + .full_o (amo_valid), + .empty_o (ready_o), + .usage_o (), // left open + .data_i (amo_data_in), + .push_i (valid_i), + .data_o (amo_data_out), + .pop_i (amo_resp_i.ack) + ); + +endmodule diff --git a/flow/designs/src/cva6/core/ariane_regfile_ff.sv b/flow/designs/src/cva6/core/ariane_regfile_ff.sv new file mode 100644 index 0000000000..ae5cbeb0d7 --- /dev/null +++ b/flow/designs/src/cva6/core/ariane_regfile_ff.sv @@ -0,0 +1,83 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Engineer: Francesco Conti - f.conti@unibo.it +// +// Additional contributions by: +// Markus Wegmann - markus.wegmann@technokrat.ch +// +// Design Name: RISC-V register file +// Project Name: zero-riscy +// Language: SystemVerilog +// +// Description: Register file with 31 or 15x 32 bit wide registers. +// Register 0 is fixed to 0. This register file is based on +// flip flops. +// + +module ariane_regfile #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned NR_READ_PORTS = 2, + parameter bit ZERO_REG_ZERO = 0 +) ( + // clock and reset + input logic clk_i, + input logic rst_ni, + // disable clock gates for testing + input logic test_en_i, + // read port + input logic [ NR_READ_PORTS-1:0][ 4:0] raddr_i, + output logic [ NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + // write port + input logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_i, + input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] we_i +); + + localparam ADDR_WIDTH = 5; + localparam NUM_WORDS = 2 ** ADDR_WIDTH; + + logic [ NUM_WORDS-1:0][DATA_WIDTH-1:0] mem; + logic [CVA6Cfg.NrCommitPorts-1:0][ NUM_WORDS-1:0] we_dec; + + + always_comb begin : we_decoder + for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin + for (int unsigned i = 0; i < NUM_WORDS; i++) begin + if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; + else we_dec[j][i] = 1'b0; + end + end + end + + // loop from 1 to NUM_WORDS-1 as R0 is nil + always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral + if (~rst_ni) begin + mem <= '{default: '0}; + end else begin + for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin + for (int unsigned i = 0; i < NUM_WORDS; i++) begin + if (we_dec[j][i]) begin + mem[i] <= wdata_i[j]; + end + end + if (ZERO_REG_ZERO) begin + mem[0] <= '0; + end + end + end + end + + for (genvar i = 0; i < NR_READ_PORTS; i++) begin + assign rdata_o[i] = mem[raddr_i[i]]; + end + +endmodule diff --git a/flow/designs/src/cva6/core/ariane_regfile_fpga.sv b/flow/designs/src/cva6/core/ariane_regfile_fpga.sv new file mode 100644 index 0000000000..9169482e3a --- /dev/null +++ b/flow/designs/src/cva6/core/ariane_regfile_fpga.sv @@ -0,0 +1,150 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Engineer: Francesco Conti - f.conti@unibo.it +// +// Additional contributions by: +// Markus Wegmann - markus.wegmann@technokrat.ch +// Noam Gallmann - gnoam@live.com +// Felipe Lisboa Malaquias +// Henry Suzukawa +// Angela Gonzalez - PlanV Technologies +// +// Description: This register file is optimized for implementation on +// FPGAs. The register file features one distributed RAM block per implemented +// sync-write port, each with a parametrized number of async-read ports. +// Read-accesses are multiplexed from the relevant block depending on which block +// was last written to. For that purpose an additional array of registers is +// maintained keeping track of write acesses. +// + +module ariane_regfile_fpga #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned NR_READ_PORTS = 2, + parameter bit ZERO_REG_ZERO = 0 +) ( + // clock and reset + input logic clk_i, + input logic rst_ni, + // disable clock gates for testing + input logic test_en_i, + // read port + input logic [ NR_READ_PORTS-1:0][ 4:0] raddr_i, + output logic [ NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + // write port + input logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_i, + input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] we_i +); + + localparam ADDR_WIDTH = 5; + localparam NUM_WORDS = 2 ** ADDR_WIDTH; + localparam LOG_NR_WRITE_PORTS = CVA6Cfg.NrCommitPorts == 1 ? 1 : $clog2(CVA6Cfg.NrCommitPorts); + + // Distributed RAM usually supports one write port per block - duplicate for each write port. + logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem[CVA6Cfg.NrCommitPorts]; + + logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:0] we_dec; + logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel; + logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel_q; + logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_reg; + logic [NR_READ_PORTS-1:0] read_after_write; + + logic [NR_READ_PORTS-1:0][4:0] raddr_q; + logic [NR_READ_PORTS-1:0][4:0] raddr; + + // write adress decoder (for block selector) + always_comb begin + for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin + for (int unsigned i = 0; i < NUM_WORDS; i++) begin + if (waddr_i[j] == i) begin + we_dec[j][i] = we_i[j]; + end else begin + we_dec[j][i] = 1'b0; + end + end + end + end + + // update block selector: + // signal mem_block_sel records where the current valid value is stored. + // if multiple ports try to write to the same address simultaneously, the port with the highest + // index has priority. + always_comb begin + mem_block_sel = mem_block_sel_q; + for (int i = 0; i < NUM_WORDS; i++) begin + for (int j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin + if (we_dec[j][i] == 1'b1) begin + mem_block_sel[i] = LOG_NR_WRITE_PORTS'(j); + end + end + end + end + + // block selector flops + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mem_block_sel_q <= '0; + raddr_q <= '0; + end else begin + mem_block_sel_q <= mem_block_sel; + if (CVA6Cfg.FpgaAlteraEn) raddr_q <= raddr_i; + else raddr_q <= '0; + end + end + + // distributed RAM blocks + logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] mem_read[CVA6Cfg.NrCommitPorts]; + logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] mem_read_sync[CVA6Cfg.NrCommitPorts]; + for (genvar j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin : regfile_ram_block + always_ff @(posedge clk_i) begin + if (we_i[j] && ~waddr_i[j] != 0) begin + mem[j][waddr_i[j]] <= wdata_i[j]; + if (CVA6Cfg.FpgaAlteraEn) + wdata_reg[j] <= wdata_i[j]; // register data written in case is needed to read next cycle + else wdata_reg[j] <= '0; + end + if (CVA6Cfg.FpgaAlteraEn) begin + for (int k = 0; k < NR_READ_PORTS; k++) begin : block_read + mem_read_sync[j][k] = mem[j][raddr_i[k]]; // synchronous RAM + read_after_write[k] <= '0; + if (waddr_i[j] == raddr_i[k]) + read_after_write[k] <= we_i[j] && ~waddr_i[j] != 0; // Identify if we need to read the content that was written + end + end + end + for (genvar k = 0; k < NR_READ_PORTS; k++) begin : block_read + assign mem_read[j][k] = CVA6Cfg.FpgaAlteraEn ? ( read_after_write[k] ? wdata_reg[j]: mem_read_sync[j][k]) : mem[j][raddr_i[k]]; + end + end + //with synchronous ram there is the need to adjust which address is used at the output MUX + assign raddr = CVA6Cfg.FpgaAlteraEn ? raddr_q : raddr_i; + + // output MUX + logic [NR_READ_PORTS-1:0][LOG_NR_WRITE_PORTS-1:0] block_addr; + for (genvar k = 0; k < NR_READ_PORTS; k++) begin : regfile_read_port + assign block_addr[k] = mem_block_sel_q[raddr[k]]; + assign rdata_o[k] = (ZERO_REG_ZERO && raddr[k] == '0) ? '0 : mem_read[block_addr[k]][k]; + end + + // random initialization of the memory to suppress assert warnings on Questa. + initial begin + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + for (int j = 0; j < NUM_WORDS; j++) begin + if (!CVA6Cfg.FpgaAlteraEn) + mem[i][j] = $random(); //quartus does not support this random statement on synthesis + else mem[i][j] = '0; + end + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/axi_shim.sv b/flow/designs/src/cva6/core/axi_shim.sv new file mode 100644 index 0000000000..5511d51851 --- /dev/null +++ b/flow/designs/src/cva6/core/axi_shim.sv @@ -0,0 +1,310 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: axi_shim.sv + * Author: Michael Schaffner + * Florian Zaruba + * Date: 1.8.2018 + * + * Description: Manages communication with the AXI Bus. Note that this unit does not + * buffer requests and register the signals. + * + */ + + +module axi_shim #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2 + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // read channel + // request + input logic rd_req_i, + output logic rd_gnt_o, + input logic [CVA6Cfg.AxiAddrWidth-1:0] rd_addr_i, + input logic [$clog2(AxiNumWords)-1:0] rd_blen_i, // axi convention: LEN-1 + input logic [2:0] rd_size_i, + input logic [CVA6Cfg.AxiIdWidth-1:0] rd_id_i, // use same ID for reads, or make sure you only have one outstanding read tx + input logic rd_lock_i, + // read response (we have to unconditionally sink the response) + input logic rd_rdy_i, + output logic rd_last_o, + output logic rd_valid_o, + output logic [CVA6Cfg.AxiDataWidth-1:0] rd_data_o, + output logic [CVA6Cfg.AxiUserWidth-1:0] rd_user_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] rd_id_o, + output logic rd_exokay_o, // indicates whether exclusive tx succeeded + // write channel + input logic wr_req_i, + output logic wr_gnt_o, + input logic [CVA6Cfg.AxiAddrWidth-1:0] wr_addr_i, + input logic [AxiNumWords-1:0][CVA6Cfg.AxiDataWidth-1:0] wr_data_i, + input logic [AxiNumWords-1:0][CVA6Cfg.AxiUserWidth-1:0] wr_user_i, + input logic [AxiNumWords-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] wr_be_i, + input logic [$clog2(AxiNumWords)-1:0] wr_blen_i, // axi convention: LEN-1 + input logic [2:0] wr_size_i, + input logic [CVA6Cfg.AxiIdWidth-1:0] wr_id_i, + input logic wr_lock_i, + input logic [5:0] wr_atop_i, + // write response + input logic wr_rdy_i, + output logic wr_valid_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] wr_id_o, + output logic wr_exokay_o, // indicates whether exclusive tx succeeded + // AXI port + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i +); + localparam AddrIndex = ($clog2(AxiNumWords) > 0) ? $clog2(AxiNumWords) : 1; + + /////////////////////////////////////////////////////// + // write channel + /////////////////////////////////////////////////////// + + enum logic [3:0] { + IDLE, + WAIT_AW_READY, + WAIT_LAST_W_READY, + WAIT_LAST_W_READY_AW_READY, + WAIT_AW_READY_BURST + } + wr_state_q, wr_state_d; + + // AXI tx counter + logic [AddrIndex-1:0] wr_cnt_d, wr_cnt_q; + logic wr_single_req, wr_cnt_done, wr_cnt_clr, wr_cnt_en; + + assign wr_single_req = (wr_blen_i == 0); + + // address + assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction + assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; + assign axi_req_o.aw.size = wr_size_i; + assign axi_req_o.aw.len = wr_blen_i; + assign axi_req_o.aw.id = wr_id_i; + assign axi_req_o.aw.prot = 3'b0; + assign axi_req_o.aw.region = 4'b0; + assign axi_req_o.aw.lock = wr_lock_i; + assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; + assign axi_req_o.aw.qos = 4'b0; + assign axi_req_o.aw.atop = wr_atop_i; + assign axi_req_o.aw.user = '0; + + // data + assign axi_req_o.w.data = wr_data_i[wr_cnt_q]; + assign axi_req_o.w.user = wr_user_i[wr_cnt_q]; + assign axi_req_o.w.strb = wr_be_i[wr_cnt_q]; + assign axi_req_o.w.last = wr_cnt_done; + + // write response + assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY); + assign axi_req_o.b_ready = wr_rdy_i; + assign wr_valid_o = axi_resp_i.b_valid; + assign wr_id_o = axi_resp_i.b.id; + + // tx counter + assign wr_cnt_done = (wr_cnt_q == wr_blen_i); + assign wr_cnt_d = (wr_cnt_clr) ? '0 : (wr_cnt_en && CVA6Cfg.AxiBurstWriteEn) ? wr_cnt_q + 1 : wr_cnt_q; + + always_comb begin : p_axi_write_fsm + // default + wr_state_d = wr_state_q; + + axi_req_o.aw_valid = 1'b0; + axi_req_o.w_valid = 1'b0; + wr_gnt_o = 1'b0; + + wr_cnt_en = 1'b0; + wr_cnt_clr = 1'b0; + + case (wr_state_q) + /////////////////////////////////// + IDLE: begin + // we have an incoming request + if (wr_req_i) begin + // is this a read or write? + axi_req_o.aw_valid = 1'b1; + axi_req_o.w_valid = 1'b1; + + if (CVA6Cfg.AxiBurstWriteEn && !wr_single_req) begin + wr_cnt_en = axi_resp_i.w_ready; + + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + 2'b11: wr_state_d = WAIT_LAST_W_READY; + 2'b01: wr_state_d = WAIT_LAST_W_READY_AW_READY; + 2'b10: wr_state_d = WAIT_LAST_W_READY; + default: ; + endcase + end else if (wr_single_req) begin // its a single write + wr_cnt_clr = 1'b1; + // single req can be granted here + wr_gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready; + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + 2'b01: wr_state_d = WAIT_AW_READY; + 2'b10: wr_state_d = WAIT_LAST_W_READY; + default: wr_state_d = IDLE; + endcase + // its a request for the whole cache line + end + end + end + /////////////////////////////////// + // ~> from single write + WAIT_AW_READY: begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + end + end + /////////////////////////////////// + // ~> from write, there is an outstanding write + WAIT_LAST_W_READY: begin + axi_req_o.w_valid = 1'b1; + + if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready && !wr_cnt_done) begin + wr_cnt_en = 1'b1; + end else if (wr_cnt_done) begin // this is the last write + if (axi_resp_i.w_ready) begin + wr_state_d = IDLE; + wr_cnt_clr = 1'b1; + wr_gnt_o = 1'b1; + end + end + end + /////////////////////////////////// + default: begin + /////////////////////////////////// + // ~> we need to wait for an aw_ready and there is at least one outstanding write + if (CVA6Cfg.AxiBurstWriteEn) begin + if (wr_state_q == WAIT_LAST_W_READY_AW_READY) begin + axi_req_o.w_valid = 1'b1; + axi_req_o.aw_valid = 1'b1; + // we got an aw_ready + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + // we got an aw ready + 2'b01: begin + // are there any outstanding transactions? + if (wr_cnt_done) begin + wr_state_d = WAIT_AW_READY_BURST; + wr_cnt_clr = 1'b1; + end else begin + // yes, so reduce the count and stay here + wr_cnt_en = 1'b1; + end + end + 2'b10: wr_state_d = WAIT_LAST_W_READY; + 2'b11: begin + // we are finished + if (wr_cnt_done) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + wr_cnt_clr = 1'b1; + // there are outstanding transactions + end else begin + wr_state_d = WAIT_LAST_W_READY; + wr_cnt_en = 1'b1; + end + end + default: ; + endcase + end /////////////////////////////////// + // ~> all data has already been sent, we are only waiting for the aw_ready + else if (wr_state_q == WAIT_AW_READY_BURST) begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + end + end + end else begin + wr_state_d = IDLE; + end + end + endcase + end + + + /////////////////////////////////////////////////////// + // read channel + /////////////////////////////////////////////////////// + + // address + // in case of a wrapping transfer we can simply begin at the address, if we want to request a cache-line + // with an incremental transfer we need to output the corresponding base address of the cache line + assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction + assign axi_req_o.ar.addr = rd_addr_i[CVA6Cfg.AxiAddrWidth-1:0]; + assign axi_req_o.ar.size = rd_size_i; + assign axi_req_o.ar.len = rd_blen_i; + assign axi_req_o.ar.id = rd_id_i; + assign axi_req_o.ar.prot = 3'b0; + assign axi_req_o.ar.region = 4'b0; + assign axi_req_o.ar.lock = rd_lock_i; + assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE; + assign axi_req_o.ar.qos = 4'b0; + assign axi_req_o.ar.user = '0; + + // make the read request + assign axi_req_o.ar_valid = rd_req_i; + assign rd_gnt_o = rd_req_i & axi_resp_i.ar_ready; + + // return path + assign axi_req_o.r_ready = rd_rdy_i; + assign rd_data_o = axi_resp_i.r.data; + if (CVA6Cfg.AXI_USER_EN) begin + assign rd_user_o = axi_resp_i.r.user; + end else begin + assign rd_user_o = '0; + end + assign rd_last_o = axi_resp_i.r.last; + assign rd_valid_o = axi_resp_i.r_valid; + assign rd_id_o = axi_resp_i.r.id; + assign rd_exokay_o = (axi_resp_i.r.resp == axi_pkg::RESP_EXOKAY); + + + // ---------------- + // Registers + // ---------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + // start in flushing state and initialize the memory + wr_state_q <= IDLE; + wr_cnt_q <= '0; + end else begin + wr_state_q <= wr_state_d; + wr_cnt_q <= wr_cnt_d; + end + end + + // ---------------- + // Assertions + // ---------------- + + //pragma translate_off + initial begin + assert (AxiNumWords >= 1) + else $fatal(1, "[axi adapter] AxiNumWords must be >= 1"); + assert (CVA6Cfg.AxiIdWidth >= 2) + else $fatal(1, "[axi adapter] AXI id width must be at least 2 bit wide"); + end + //pragma translate_on + +endmodule // axi_adapter2 diff --git a/flow/designs/src/cva6/core/branch_unit.sv b/flow/designs/src/cva6/core/branch_unit.sv new file mode 100644 index 0000000000..097416756d --- /dev/null +++ b/flow/designs/src/cva6/core/branch_unit.sv @@ -0,0 +1,138 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 09.05.2017 +// Description: Branch target calculation and comparison + +module branch_unit #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, + parameter type fu_data_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Virtualization mode state - CSR_REGFILE + input logic v_i, + // Debug mode state - CSR_REGFILE + input logic debug_mode_i, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // Instruction PC - ISSUE_STAGE + input logic [CVA6Cfg.VLEN-1:0] pc_i, + // Is zcmt instruction - ISSUE_STAGE + input logic is_zcmt_i, + // Instruction is compressed - ISSUE_STAGE + input logic is_compressed_instr_i, + // Branch unit instruction is valid - ISSUE_STAGE + input logic branch_valid_i, + // ALU branch compare result - ALU + input logic branch_comp_res_i, + // Brach unit result - ISSUE_STAGE + output logic [CVA6Cfg.VLEN-1:0] branch_result_o, + // Information of branch prediction - ISSUE_STAGE + input branchpredict_sbe_t branch_predict_i, + // Signaling that we resolved the branch - ISSUE_STAGE + output bp_resolve_t resolved_branch_o, + // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE + output logic resolve_branch_o, + // Branch exception out - TO_BE_COMPLETED + output exception_t branch_exception_o +); + logic [CVA6Cfg.VLEN-1:0] target_address; + logic [CVA6Cfg.VLEN-1:0] next_pc; + + // here we handle the various possibilities of mis-predicts + always_comb begin : mispredict_handler + // set the jump base, for JALR we need to look at the register, for all other control flow instructions we can take the current PC + automatic logic [CVA6Cfg.VLEN-1:0] jump_base; + // TODO(zarubaf): The ALU can be used to calculate the branch target + jump_base = (fu_data_i.operation == ariane_pkg::JALR) ? fu_data_i.operand_a[CVA6Cfg.VLEN-1:0] : pc_i; + + resolve_branch_o = 1'b0; + resolved_branch_o.target_address = {CVA6Cfg.VLEN{1'b0}}; + resolved_branch_o.is_taken = 1'b0; + resolved_branch_o.valid = branch_valid_i; + resolved_branch_o.is_mispredict = 1'b0; + resolved_branch_o.cf_type = branch_predict_i.cf; + // calculate next PC, depending on whether the instruction is compressed or not this may be different + // TODO(zarubaf): We already calculate this a couple of times, maybe re-use? + next_pc = pc_i + ((is_compressed_instr_i) ? {{CVA6Cfg.VLEN-2{1'b0}}, 2'h2} : {{CVA6Cfg.VLEN-3{1'b0}}, 3'h4}); + // calculate target address simple 64 bit addition + target_address = $unsigned($signed(jump_base) + $signed(fu_data_i.imm[CVA6Cfg.VLEN-1:0])); + // on a JALR we are supposed to reset the LSB to 0 (according to the specification) + if (fu_data_i.operation == ariane_pkg::JALR) target_address[0] = 1'b0; + // we need to put the branch target address into rd, this is the result of this unit + branch_result_o = next_pc; + resolved_branch_o.pc = pc_i; + // There are only three sources of mispredicts: + // 1. Branches + // 2. Jumps to register addresses + // 3. Zcmt instructions + if (branch_valid_i) begin + // write target address which goes to PC Gen or select target address if zcmt + resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc; + resolved_branch_o.is_taken = branch_comp_res_i; + if (CVA6Cfg.RVZCMT) begin + if (is_zcmt_i) begin + // Unconditional jump handling + resolved_branch_o.is_mispredict = 1'b1; // miss prediction for ZCMT + resolved_branch_o.cf_type = ariane_pkg::JumpR; + end + end + // check the outcome of the branch speculation + if (ariane_pkg::op_is_branch(fu_data_i.operation)) begin + // Set the `cf_type` of the output as `branch`, this will update the BHT. + resolved_branch_o.cf_type = ariane_pkg::Branch; + // If the ALU comparison does not agree with the BHT prediction set the resolution as mispredicted. + resolved_branch_o.is_mispredict = branch_comp_res_i != (branch_predict_i.cf == ariane_pkg::Branch); + end + if (fu_data_i.operation == ariane_pkg::JALR + // check if the address of the jump register is correct and that we actually predicted + && (branch_predict_i.cf == ariane_pkg::NoCF || target_address != branch_predict_i.predict_address)) begin + resolved_branch_o.is_mispredict = 1'b1; + // update BTB only if this wasn't a return + if (branch_predict_i.cf != ariane_pkg::Return) + resolved_branch_o.cf_type = ariane_pkg::JumpR; + end + // to resolve the branch in ID + resolve_branch_o = 1'b1; + end + end + // use ALU exception signal for storing instruction fetch exceptions if + // the target address is not aligned to a 2 byte boundary + // + logic jump_taken; + always_comb begin : exception_handling + + // Do a jump if it is either unconditional jump (JAL | JALR) or `taken` conditional jump + branch_exception_o.cause = riscv::INSTR_ADDR_MISALIGNED; + branch_exception_o.valid = 1'b0; + if (CVA6Cfg.TvalEn) + branch_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + else branch_exception_o.tval = '0; + branch_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}}; + branch_exception_o.tinst = '0; + branch_exception_o.gva = CVA6Cfg.RVH ? v_i : 1'b0; + // Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or + // an unconditional jump + if (!CVA6Cfg.RVC) begin + jump_taken = !(ariane_pkg::op_is_branch(fu_data_i.operation)) || + ((ariane_pkg::op_is_branch(fu_data_i.operation)) && branch_comp_res_i); + if (branch_valid_i && (target_address[0] || target_address[1]) && jump_taken) begin + branch_exception_o.valid = 1'b1; + end + end + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/axi_adapter.sv b/flow/designs/src/cva6/core/cache_subsystem/axi_adapter.sv new file mode 100644 index 0000000000..3ee65421b7 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/axi_adapter.sv @@ -0,0 +1,520 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: axi_adapter.sv + * Author: Florian Zaruba + * Date: 1.8.2018 + * + * Description: Manages communication with the AXI Bus + */ +//import std_cache_pkg::*; + +module axi_adapter #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned DATA_WIDTH = 256, + parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature + parameter int unsigned CACHELINE_BYTE_OFFSET = 8, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + input logic req_i, + input ariane_pkg::ad_req_t type_i, + input ariane_pkg::amo_t amo_i, + output logic gnt_o, + input logic [CVA6Cfg.XLEN-1:0] addr_i, + input logic we_i, + input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] wdata_i, + input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] be_i, + input logic [1:0] size_i, + input logic [CVA6Cfg.AxiIdWidth-1:0] id_i, + // read port + output logic valid_o, + output logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] rdata_o, + output logic [CVA6Cfg.AxiIdWidth-1:0] id_o, + // critical word - read port + output logic [CVA6Cfg.AxiDataWidth-1:0] critical_word_o, + output logic critical_word_valid_o, + // AXI port + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i +); + localparam BURST_SIZE = (DATA_WIDTH / CVA6Cfg.AxiDataWidth) - 1; + localparam ADDR_INDEX = ($clog2( + DATA_WIDTH / CVA6Cfg.AxiDataWidth + ) > 0) ? $clog2( + DATA_WIDTH / CVA6Cfg.AxiDataWidth + ) : 1; + localparam MAX_OUTSTANDING_AW = CVA6Cfg.MaxOutstandingStores; + localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2( + MAX_OUTSTANDING_AW + 1 + ) > 0 ? $clog2( + MAX_OUTSTANDING_AW + 1 + ) : 1; + + typedef logic [MAX_OUTSTANDING_AW_CNT_WIDTH-1:0] outstanding_aw_cnt_t; + + enum logic [3:0] { + IDLE, + WAIT_B_VALID, + WAIT_AW_READY, + WAIT_LAST_W_READY, + WAIT_LAST_W_READY_AW_READY, + WAIT_AW_READY_BURST, + WAIT_R_VALID, + WAIT_R_VALID_MULTIPLE, + COMPLETE_READ, + WAIT_AMO_R_VALID + } + state_q, state_d; + + // counter for AXI transfers + logic [ADDR_INDEX-1:0] cnt_d, cnt_q; + logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] + cache_line_d, cache_line_q; + // save the address for a read, as we allow for non-cacheline aligned accesses + logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0] addr_offset_d, addr_offset_q; + logic [CVA6Cfg.AxiIdWidth-1:0] id_d, id_q; + logic [ADDR_INDEX-1:0] index; + // save the atomic operation and size + ariane_pkg::amo_t amo_d, amo_q; + logic [1:0] size_d, size_q; + // outstanding write transactions counter + outstanding_aw_cnt_t outstanding_aw_cnt_q, outstanding_aw_cnt_d; + logic any_outstanding_aw; + + assign any_outstanding_aw = outstanding_aw_cnt_q != '0; + + always_comb begin : axi_fsm + // Default assignments + axi_req_o.aw_valid = 1'b0; + // Cast to AXI address width + axi_req_o.aw.addr = addr_i; + axi_req_o.aw.prot = 3'b0; + axi_req_o.aw.region = 4'b0; + axi_req_o.aw.len = 8'b0; + axi_req_o.aw.size = {1'b0, size_i}; // 1, 2, 4 or 8 bytes + axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction + axi_req_o.aw.lock = 1'b0; + axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; + axi_req_o.aw.qos = 4'b0; + axi_req_o.aw.id = id_i; + axi_req_o.aw.atop = atop_from_amo(amo_i); + axi_req_o.aw.user = '0; + + axi_req_o.ar_valid = 1'b0; + // Cast to AXI address width + axi_req_o.ar.addr = addr_i; + // in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line + // with an incremental transfer we need to output the corresponding base address of the cache line + if (!CRITICAL_WORD_FIRST && type_i != ariane_pkg::SINGLE_REQ) begin + axi_req_o.ar.addr[CACHELINE_BYTE_OFFSET-1:0] = '0; + end + axi_req_o.ar.prot = 3'b0; + axi_req_o.ar.region = 4'b0; + axi_req_o.ar.len = 8'b0; + axi_req_o.ar.size = {1'b0, size_i}; // 1, 2, 4 or 8 bytes + axi_req_o.ar.burst = (CRITICAL_WORD_FIRST ? axi_pkg::BURST_WRAP : axi_pkg::BURST_INCR); // wrapping transfer in case of a critical word first strategy + axi_req_o.ar.lock = 1'b0; + axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE; + axi_req_o.ar.qos = 4'b0; + axi_req_o.ar.id = id_i; + axi_req_o.ar.user = '0; + + axi_req_o.w_valid = 1'b0; + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; + axi_req_o.w.last = 1'b0; + axi_req_o.w.user = '0; + + axi_req_o.b_ready = 1'b0; + axi_req_o.r_ready = 1'b0; + + gnt_o = 1'b0; + valid_o = 1'b0; + id_o = axi_resp_i.r.id; + + critical_word_o = axi_resp_i.r.data; + critical_word_valid_o = 1'b0; + rdata_o = cache_line_q; + + state_d = state_q; + cnt_d = cnt_q; + cache_line_d = cache_line_q; + addr_offset_d = addr_offset_q; + id_d = id_q; + amo_d = amo_q; + size_d = size_q; + index = '0; + + outstanding_aw_cnt_d = outstanding_aw_cnt_q; + + case (state_q) + + IDLE: begin + cnt_d = '0; + // we have an incoming request + if (req_i) begin + // is this a read or write? + // write + if (we_i) begin + // multiple outstanding write transactions are only + // allowed if they are guaranteed not to be reordered + // i.e. same ID + if (!any_outstanding_aw || ((id_i == id_q) && (amo_i == ariane_pkg::AMO_NONE))) begin + // the data is valid + axi_req_o.aw_valid = 1'b1; + axi_req_o.w_valid = 1'b1; + // store-conditional requires exclusive access + axi_req_o.aw.lock = amo_i == ariane_pkg::AMO_SC; + // its a single write + if (type_i == ariane_pkg::SINGLE_REQ) begin + // only a single write so the data is already the last one + axi_req_o.w.last = 1'b1; + // single req can be granted here + gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready; + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + 2'b11: state_d = WAIT_B_VALID; + 2'b01: state_d = WAIT_AW_READY; + 2'b10: state_d = WAIT_LAST_W_READY; + default: state_d = IDLE; + endcase + + if (axi_resp_i.aw_ready) begin + id_d = id_i; + amo_d = amo_i; + size_d = size_i; + end + + // its a request for the whole cache line + end else begin + // bursts of AMOs unsupported + assert (amo_i == ariane_pkg::AMO_NONE) + else $fatal(1, "Bursts of atomic operations are not supported"); + + axi_req_o.aw.len = BURST_SIZE[7:0]; // number of bursts to do + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; + + if (axi_resp_i.w_ready) cnt_d = BURST_SIZE[ADDR_INDEX-1:0] - 1; + else cnt_d = BURST_SIZE[ADDR_INDEX-1:0]; + + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + 2'b11: state_d = WAIT_LAST_W_READY; + 2'b01: state_d = WAIT_LAST_W_READY_AW_READY; + 2'b10: state_d = WAIT_LAST_W_READY; + default: ; + endcase + end + end + // read + end else begin + // only multiple outstanding write transactions are allowed + if (!any_outstanding_aw) begin + + axi_req_o.ar_valid = 1'b1; + // load-reserved requires exclusive access + axi_req_o.ar.lock = amo_i == ariane_pkg::AMO_LR; + + gnt_o = axi_resp_i.ar_ready; + if (type_i != ariane_pkg::SINGLE_REQ) begin + assert (amo_i == ariane_pkg::AMO_NONE) + else $fatal(1, "Bursts of atomic operations are not supported"); + + axi_req_o.ar.len = BURST_SIZE[7:0]; + cnt_d = BURST_SIZE[ADDR_INDEX-1:0]; + end + + if (axi_resp_i.ar_ready) begin + state_d = (type_i == ariane_pkg::SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE; + addr_offset_d = addr_i[ADDR_INDEX-1+3:3]; + end + end + end + end + end + + // ~> from single write + WAIT_AW_READY: begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + gnt_o = 1'b1; + state_d = WAIT_B_VALID; + id_d = id_i; + amo_d = amo_i; + size_d = size_i; + end + end + + // ~> we need to wait for an aw_ready and there is at least one outstanding write + WAIT_LAST_W_READY_AW_READY: begin + axi_req_o.w_valid = 1'b1; + axi_req_o.w.last = (cnt_q == '0); + if (type_i == ariane_pkg::SINGLE_REQ) begin + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; + end else begin + axi_req_o.w.data = wdata_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; + axi_req_o.w.strb = be_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; + end + axi_req_o.aw_valid = 1'b1; + // we are here because we want to write a cache line + axi_req_o.aw.len = BURST_SIZE[7:0]; + // we got an aw_ready + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + // we got an aw ready + 2'b01: begin + // are there any outstanding transactions? + if (cnt_q == 0) state_d = WAIT_AW_READY_BURST; + else // yes, so reduce the count and stay here + cnt_d = cnt_q - 1; + end + 2'b10: state_d = WAIT_LAST_W_READY; + 2'b11: begin + // we are finished + if (cnt_q == 0) begin + state_d = WAIT_B_VALID; + gnt_o = 1'b1; + // there are outstanding transactions + end else begin + state_d = WAIT_LAST_W_READY; + cnt_d = cnt_q - 1; + end + end + default: ; + endcase + + end + + // ~> all data has already been sent, we are only waiting for the aw_ready + WAIT_AW_READY_BURST: begin + axi_req_o.aw_valid = 1'b1; + axi_req_o.aw.len = BURST_SIZE[7:0]; + + if (axi_resp_i.aw_ready) begin + state_d = WAIT_B_VALID; + gnt_o = 1'b1; + end + end + + // ~> from write, there is an outstanding write + WAIT_LAST_W_READY: begin + axi_req_o.w_valid = 1'b1; + + if (type_i != ariane_pkg::SINGLE_REQ) begin + axi_req_o.w.data = wdata_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; + axi_req_o.w.strb = be_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q]; + end + + // this is the last write + if (cnt_q == '0) begin + axi_req_o.w.last = 1'b1; + if (axi_resp_i.w_ready) begin + state_d = WAIT_B_VALID; + gnt_o = 1'b1; + end + end else if (axi_resp_i.w_ready) begin + cnt_d = cnt_q - 1; + end + end + + // ~> finish write transaction + WAIT_B_VALID: begin + id_o = axi_resp_i.b.id; + + // Write is valid + if (axi_resp_i.b_valid && !any_outstanding_aw) begin + axi_req_o.b_ready = 1'b1; + + // some atomics must wait for read data + // we only accept it after accepting bvalid + if (amo_returns_data(amo_q)) begin + if (axi_resp_i.r_valid) begin + // return read data if valid + valid_o = 1'b1; + axi_req_o.r_ready = 1'b1; + state_d = IDLE; + rdata_o = axi_resp_i.r.data; + end else begin + // wait otherwise + state_d = WAIT_AMO_R_VALID; + end + end else begin + valid_o = 1'b1; + state_d = IDLE; + + // store-conditional response + if (amo_q == ariane_pkg::AMO_SC) begin + if (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY) begin + // success -> return 0 + rdata_o = 'b0; + end else begin + // failure -> when request is 64-bit, return 1; + // when request is 32-bit place a 1 in both upper + // and lower half words. The right word will be + // realigned/masked externally + rdata_o = size_q == 2'b10 ? (1'b1 << 32) | 64'b1 : 64'b1; + end + end + end + // if the request was not an atomic we can possibly issue + // other requests while waiting for the response + end else begin + if ((amo_q == ariane_pkg::AMO_NONE) && (outstanding_aw_cnt_q != MAX_OUTSTANDING_AW)) begin + state_d = IDLE; + outstanding_aw_cnt_d = outstanding_aw_cnt_q + 1; + end + end + end + + // ~> some atomics wait for read data + WAIT_AMO_R_VALID: begin + // acknowledge data and terminate atomic + if (axi_resp_i.r_valid) begin + axi_req_o.r_ready = 1'b1; + state_d = IDLE; + valid_o = 1'b1; + rdata_o = axi_resp_i.r.data; + end + end + + // ~> cacheline read, single read + WAIT_R_VALID_MULTIPLE, WAIT_R_VALID: begin + if (CRITICAL_WORD_FIRST) index = addr_offset_q + (BURST_SIZE[ADDR_INDEX-1:0] - cnt_q); + else index = BURST_SIZE[ADDR_INDEX-1:0] - cnt_q; + + // reads are always wrapping here + axi_req_o.r_ready = 1'b1; + // this is the first read a.k.a the critical word + if (axi_resp_i.r_valid) begin + if (CRITICAL_WORD_FIRST) begin + // this is the first word of a cacheline read, e.g.: the word which was causing the miss + if (state_q == WAIT_R_VALID_MULTIPLE && cnt_q == BURST_SIZE) begin + critical_word_valid_o = 1'b1; + critical_word_o = axi_resp_i.r.data; + end + end else begin + // check if the address offset matches - then we are getting the critical word + if (index == addr_offset_q) begin + critical_word_valid_o = 1'b1; + critical_word_o = axi_resp_i.r.data; + end + end + + // this is the last read + if (axi_resp_i.r.last) begin + id_d = axi_resp_i.r.id; + state_d = COMPLETE_READ; + end + + // save the word + if (state_q == WAIT_R_VALID_MULTIPLE) begin + cache_line_d[index] = axi_resp_i.r.data; + + end else cache_line_d[0] = axi_resp_i.r.data; + + // Decrease the counter + cnt_d = cnt_q - 1; + end + end + // ~> read is complete + COMPLETE_READ: begin + valid_o = 1'b1; + state_d = IDLE; + id_o = id_q; + end + + default: state_d = IDLE; + endcase + + // This process handles B responses when accepting + // multiple outstanding write transactions + if (any_outstanding_aw && axi_resp_i.b_valid) begin + axi_req_o.b_ready = 1'b1; + valid_o = 1'b1; + // Right hand side contains non-registered signal as we want + // to preserve a possible increment from the WAIT_B_VALID state + outstanding_aw_cnt_d = outstanding_aw_cnt_d - 1; + end + end + + // ---------------- + // Registers + // ---------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + // start in flushing state and initialize the memory + state_q <= IDLE; + cnt_q <= '0; + cache_line_q <= '0; + addr_offset_q <= '0; + id_q <= '0; + amo_q <= ariane_pkg::AMO_NONE; + size_q <= '0; + outstanding_aw_cnt_q <= '0; + end else begin + state_q <= state_d; + cnt_q <= cnt_d; + cache_line_q <= cache_line_d; + addr_offset_q <= addr_offset_d; + id_q <= id_d; + amo_q <= amo_d; + size_q <= size_d; + outstanding_aw_cnt_q <= outstanding_aw_cnt_d; + end + end + + function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo); + axi_pkg::atop_t result = 6'b000000; + + unique case (amo) + ariane_pkg::AMO_NONE: result = {axi_pkg::ATOP_NONE, 4'b0000}; + ariane_pkg::AMO_SWAP: result = {axi_pkg::ATOP_ATOMICSWAP}; + ariane_pkg::AMO_ADD: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; + ariane_pkg::AMO_AND: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; + ariane_pkg::AMO_OR: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; + ariane_pkg::AMO_XOR: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}; + ariane_pkg::AMO_MAX: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}; + ariane_pkg::AMO_MAXU: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}; + ariane_pkg::AMO_MIN: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}; + ariane_pkg::AMO_MINU: + result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}; + ariane_pkg::AMO_CAS1: result = {axi_pkg::ATOP_NONE, 4'b0000}; // Unsupported + ariane_pkg::AMO_CAS2: result = {axi_pkg::ATOP_NONE, 4'b0000}; // Unsupported + default: result = 6'b000000; + endcase + + return result; + endfunction + + function automatic logic amo_returns_data(ariane_pkg::amo_t amo); + axi_pkg::atop_t atop = atop_from_amo(amo); + logic is_load = atop[5:4] == axi_pkg::ATOP_ATOMICLOAD; + logic is_swap_or_cmp = atop[5:4] == axi_pkg::ATOP_ATOMICSWAP[5:4]; + return is_load || is_swap_or_cmp; + endfunction + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/cache_ctrl.sv b/flow/designs/src/cva6/core/cache_subsystem/cache_ctrl.sv new file mode 100644 index 0000000000..8091e6a823 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cache_ctrl.sv @@ -0,0 +1,488 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// File: cache_ctrl.svh +// Author: Florian Zaruba +// Date: 14.10.2017 +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// +// Description: Cache controller + + +module cache_ctrl + import ariane_pkg::*; + import std_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type cache_line_t = logic, + parameter type cl_be_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, + input logic bypass_i, // enable cache + output logic busy_o, + // Core request ports + input dcache_req_i_t req_port_i, + output dcache_req_o_t req_port_o, + // SRAM interface + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] req_o, // req is valid + output logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] addr_o, // address into cache array + input logic gnt_i, + output cache_line_t data_o, + output cl_be_t be_o, + output logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_o, //valid one cycle later + input cache_line_t [CVA6Cfg.DCACHE_SET_ASSOC-1:0] data_i, + output logic we_o, + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way_i, + // Miss handling + output miss_req_t miss_req_o, + // return + input logic miss_gnt_i, + input logic active_serving_i, // the miss unit is currently active for this unit, serving the miss + input logic [63:0] critical_word_i, + input logic critical_word_valid_i, + // bypass ports + input logic bypass_gnt_i, + input logic bypass_valid_i, + input logic [63:0] bypass_data_i, + // check MSHR for aliasing + output logic [55:0] mshr_addr_o, + input logic mshr_addr_matches_i, + input logic mshr_index_matches_i +); + + enum logic [3:0] { + IDLE, // 0 + WAIT_TAG, // 1 + WAIT_TAG_BYPASSED, // 2 + WAIT_GNT, // 3 + WAIT_GNT_SAVED, // 4 + STORE_REQ, // 5 + WAIT_REFILL_VALID, // 6 + WAIT_REFILL_GNT, // 7 + WAIT_TAG_SAVED, // 8 + WAIT_MSHR, // 9 + WAIT_CRITICAL_WORD // 10 + } + state_d, state_q; + + typedef struct packed { + logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] index; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag; + logic [CVA6Cfg.DcacheIdWidth-1:0] id; + logic [(CVA6Cfg.XLEN/8)-1:0] be; + logic [1:0] size; + logic we; + logic [CVA6Cfg.XLEN-1:0] wdata; + logic bypass; + logic killed; + } mem_req_t; + + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way_d, hit_way_q; + + mem_req_t mem_req_d, mem_req_q; + + assign busy_o = (state_q != IDLE); + assign tag_o = mem_req_d.tag; + + logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] cl_i; + + always_comb begin : way_select + cl_i = '0; + for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) + if (hit_way_i[i]) cl_i = data_i[i].data; + + // cl_i = data_i[one_hot_to_bin(hit_way_i)].data; + end + + // -------------- + // Cache FSM + // -------------- + always_comb begin : cache_ctrl_fsm + automatic logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset; + automatic logic [$clog2(CVA6Cfg.AxiDataWidth)-1:0] axi_offset; + // incoming cache-line -> this is needed as synthesis is not supporting +: indexing in a multi-dimensional array + // cache-line offset -> multiple of XLEN + cl_offset = mem_req_q.index[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:$clog2(CVA6Cfg.XLEN/8)] << + $clog2(CVA6Cfg.XLEN); // shift by log2(XLEN) to the left + // XLEN offset within AXI request + axi_offset = (mem_req_q.index >> $clog2(CVA6Cfg.XLEN / 8)) << $clog2(CVA6Cfg.XLEN); + // default assignments + state_d = state_q; + mem_req_d = mem_req_q; + hit_way_d = hit_way_q; + // output assignments + req_port_o.data_gnt = 1'b0; + req_port_o.data_rvalid = 1'b0; + req_port_o.data_rdata = '0; + req_port_o.data_rid = mem_req_q.id; + miss_req_o = '0; + mshr_addr_o = '0; + // Memory array communication + req_o = '0; + addr_o = req_port_i.address_index; + data_o = '0; + be_o = '0; + we_o = '0; + + mem_req_d.killed |= req_port_i.kill_req; + + case (state_q) + + IDLE: begin + // a new request arrived + if (req_port_i.data_req && !flush_i) begin + // request the cache line - we can do this speculatively + req_o = '1; + + // save index, be and we + mem_req_d.index = req_port_i.address_index; + mem_req_d.id = req_port_i.data_id; + mem_req_d.be = req_port_i.data_be; + mem_req_d.size = req_port_i.data_size; + mem_req_d.we = req_port_i.data_we; + mem_req_d.wdata = req_port_i.data_wdata; + mem_req_d.killed = req_port_i.kill_req; + + // Bypass mode, check for uncacheable address here as well + if (bypass_i) begin + state_d = WAIT_TAG_BYPASSED; + // grant this access only if it was a load + req_port_o.data_gnt = (req_port_i.data_we) ? 1'b0 : 1'b1; + mem_req_d.bypass = 1'b1; + // ------------------ + // Cache is enabled + // ------------------ + end else begin + // Wait that we have access on the memory array + if (gnt_i) begin + state_d = WAIT_TAG; + mem_req_d.bypass = 1'b0; + // only for a read + if (!req_port_i.data_we) req_port_o.data_gnt = 1'b1; + end + end + end + end + + // cache enabled and waiting for tag + WAIT_TAG, WAIT_TAG_SAVED: begin + // check that the client really wants to do the request and that we have a valid tag + if (!req_port_i.kill_req && (req_port_i.tag_valid || state_q == WAIT_TAG_SAVED || mem_req_q.we)) begin + // save tag if we didn't already save it + if (state_q != WAIT_TAG_SAVED) begin + mem_req_d.tag = req_port_i.address_tag; + end + // we speculatively request another transfer + if (req_port_i.data_req && !flush_i) begin + req_o = '1; + end + // ------------ + // HIT CASE + // ------------ + if (|hit_way_i) begin + // we can request another cache-line if this was a load + if (req_port_i.data_req && !mem_req_q.we && !flush_i) begin + state_d = WAIT_TAG; // switch back to WAIT_TAG + mem_req_d.index = req_port_i.address_index; + mem_req_d.id = req_port_i.data_id; + mem_req_d.be = req_port_i.data_be; + mem_req_d.size = req_port_i.data_size; + mem_req_d.we = req_port_i.data_we; + mem_req_d.wdata = req_port_i.data_wdata; + mem_req_d.killed = req_port_i.kill_req; + mem_req_d.bypass = 1'b0; + + req_port_o.data_gnt = gnt_i; + + if (!gnt_i) begin + state_d = IDLE; + end + end else begin + state_d = IDLE; + end + + // this is timing critical + req_port_o.data_rdata = cl_i[cl_offset+:CVA6Cfg.XLEN]; + + // report data for a read + if (!mem_req_q.we) begin + req_port_o.data_rvalid = ~mem_req_q.killed; + // else this was a store so we need an extra step to handle it + end else begin + state_d = STORE_REQ; + hit_way_d = hit_way_i; + end + // ------------ + // MISS CASE + // ------------ + end else begin + // make a miss request + state_d = WAIT_REFILL_GNT; + end + // ---------------------------------------------- + // Check MSHR - Miss Status Handling Register + // ---------------------------------------------- + mshr_addr_o = {tag_o, mem_req_q.index}; + // 1. We've got a match on MSHR and while are going down the + // store path. This means that the miss controller is + // currently evicting our cache-line. As the store is + // non-atomic we need to constantly check whether we are + // matching the address the miss handler is serving. + // Furthermore we need to check for the whole index + // because a completely different memory line could alias + // with the cache-line we are evicting. + // 2. The second case is where we are currently loading and + // the address matches the exact CL the miss controller + // is currently serving. That means we need to wait for + // the miss controller to finish its request before we + // can continue to serve this CL. Otherwise we will fetch + // the cache-line again and potentially loosing any + // content we've written so far. This as a consequence + // means we can't have hit on the CL which mean the + // req_port_o.data_rvalid will be de-asserted. + if ((mshr_index_matches_i && mem_req_q.we) || mshr_addr_matches_i) begin + state_d = WAIT_MSHR; + end + + // ------------------------- + // Check for cache-ability + // ------------------------- + if (!config_pkg::is_inside_cacheable_regions( + CVA6Cfg, {{{64 - CVA6Cfg.PLEN} {1'b0}}, tag_o, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}} + )) begin + mem_req_d.bypass = 1'b1; + state_d = WAIT_REFILL_GNT; + end + + // we are still waiting for a valid tag + end else begin + // request cache line for saved index + addr_o = mem_req_q.index; + req_o = '1; + + // check that we still have a memory grant + if (!gnt_i) begin + state_d = WAIT_GNT; + end + end + end + + // ~> we already granted the request but lost the memory grant while waiting for the tag + WAIT_GNT, WAIT_GNT_SAVED: begin + // request cache line for saved index + addr_o = mem_req_q.index; + req_o = '1; + + // if we get a valid tag while waiting for the memory grant, save it + if (req_port_i.tag_valid) begin + mem_req_d.tag = req_port_i.address_tag; + state_d = WAIT_GNT_SAVED; + end + + // we have a memory grant again ~> go back to WAIT_TAG + if (gnt_i) begin + state_d = (state_d == WAIT_GNT) ? WAIT_TAG : WAIT_TAG_SAVED; + end + end + + // ~> we are here as we need a second round of memory access for a store + STORE_REQ: begin + // check if the MSHR still doesn't match + mshr_addr_o = {mem_req_q.tag, mem_req_q.index}; + + // We need to re-check for MSHR aliasing here as the store requires at least + // two memory look-ups on a single-ported SRAM and therefore is non-atomic + if (!mshr_index_matches_i) begin + // store data, write dirty bit + req_o = hit_way_q; + addr_o = mem_req_q.index; + we_o = 1'b1; + + be_o.vldrty = hit_way_q; + + // set the correct byte enable + be_o.data[cl_offset>>3+:CVA6Cfg.XLEN/8] = mem_req_q.be; + data_o.data[cl_offset+:CVA6Cfg.XLEN] = mem_req_q.wdata; + data_o.tag = mem_req_d.tag; + // ~> change the state + data_o.dirty = 1'b1; + data_o.valid = 1'b1; + + // got a grant ~> this is finished now + if (gnt_i) begin + req_port_o.data_gnt = 1'b1; + state_d = IDLE; + end + end else begin + state_d = WAIT_MSHR; + end + end // case: STORE_REQ + + // we've got a match on MSHR ~> miss unit is currently serving a request + WAIT_MSHR: begin + mshr_addr_o = {mem_req_q.tag, mem_req_q.index}; + // we can start a new request + if (!mshr_index_matches_i) begin + req_o = '1; + + addr_o = mem_req_q.index; + + if (gnt_i) state_d = WAIT_TAG_SAVED; + end + end + + // its for sure a miss + WAIT_TAG_BYPASSED: begin + // check that the client really wants to do the request and that we have a valid tag + if (!req_port_i.kill_req && (req_port_i.tag_valid || mem_req_q.we)) begin + // save tag + mem_req_d.tag = req_port_i.address_tag; + state_d = WAIT_REFILL_GNT; + end + end + + // ~> wait for grant from miss unit + WAIT_REFILL_GNT: begin + + mshr_addr_o = {mem_req_q.tag, mem_req_q.index}; + + miss_req_o.valid = 1'b1; + miss_req_o.bypass = mem_req_q.bypass; + miss_req_o.addr = {mem_req_q.tag, mem_req_q.index}; + miss_req_o.be[axi_offset>>3+:CVA6Cfg.XLEN/8] = mem_req_q.be; + miss_req_o.size = mem_req_q.size; + miss_req_o.we = mem_req_q.we; + miss_req_o.wdata[axi_offset+:CVA6Cfg.XLEN] = mem_req_q.wdata; + + // got a grant so go to valid + if (bypass_gnt_i) begin + state_d = WAIT_REFILL_VALID; + // if this was a write we still need to give a grant to the store unit. + // We can also avoid waiting for the response valid, this signal is + // currently not used by the store unit + if (mem_req_q.we) begin + req_port_o.data_gnt = 1'b1; + state_d = IDLE; + end + end + + if (miss_gnt_i && !mem_req_q.we) state_d = WAIT_CRITICAL_WORD; + else if (miss_gnt_i) begin + state_d = IDLE; + req_port_o.data_gnt = 1'b1; + end + + // it can be the case that the miss unit is currently serving a + // request which matches ours + // so we need to check the MSHR for matching continuously + // if the MSHR matches we need to go to a different state -> we should never get a matching MSHR and a high miss_gnt_i + if (mshr_addr_matches_i && !active_serving_i) begin + state_d = WAIT_MSHR; + end + end + + // ~> wait for critical word to arrive + WAIT_CRITICAL_WORD: begin + // speculatively request another word + if (req_port_i.data_req) begin + // request the cache line + req_o = '1; + end + + if (critical_word_valid_i) begin + req_port_o.data_rvalid = ~mem_req_q.killed; + req_port_o.data_rdata = critical_word_i[axi_offset+:CVA6Cfg.XLEN]; + // we can make another request + if (req_port_i.data_req && !flush_i) begin + // save index, be and we + mem_req_d.index = req_port_i.address_index; + mem_req_d.id = req_port_i.data_id; + mem_req_d.be = req_port_i.data_be; + mem_req_d.size = req_port_i.data_size; + mem_req_d.we = req_port_i.data_we; + mem_req_d.wdata = req_port_i.data_wdata; + mem_req_d.killed = req_port_i.kill_req; + + state_d = IDLE; + + // Wait until we have access on the memory array + if (gnt_i) begin + state_d = WAIT_TAG; + mem_req_d.bypass = 1'b0; + req_port_o.data_gnt = 1'b1; + end + end else begin + state_d = IDLE; + end + end + end + // ~> wait until the bypass request is valid + WAIT_REFILL_VALID: begin + // got a valid answer + if (bypass_valid_i) begin + req_port_o.data_rdata = bypass_data_i[axi_offset+:CVA6Cfg.XLEN]; + req_port_o.data_rvalid = ~mem_req_q.killed; + state_d = IDLE; + end + end + + default: ; + + endcase + + if (req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + if (!(state_q inside {WAIT_REFILL_GNT, WAIT_REFILL_VALID, WAIT_CRITICAL_WORD})) begin + state_d = IDLE; + end + end + end + + // -------------- + // Registers + // -------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + mem_req_q <= '0; + hit_way_q <= '0; + end else begin + state_q <= state_d; + mem_req_q <= mem_req_d; + hit_way_q <= hit_way_d; + end + end + + //pragma translate_off +`ifndef VERILATOR + initial begin + assert (CVA6Cfg.DCACHE_LINE_WIDTH == 128) + else + $error( + "Cacheline width has to be 128 for the moment. But only small changes required in data select logic" + ); + end + // if the full MSHR address matches so should also match the partial one + partial_full_mshr_match : + assert property(@(posedge clk_i) disable iff (~rst_ni) mshr_addr_matches_i -> mshr_index_matches_i) + else $fatal(1, "partial mshr index doesn't match"); + // there should never be a valid answer when the MSHR matches and we are not being served + no_valid_on_mshr_match : + assert property(@(posedge clk_i) disable iff (~rst_ni) (mshr_addr_matches_i && !active_serving_i)-> !req_port_o.data_rvalid || req_port_i.kill_req) + else $fatal(1, "rvalid_o should not be set on MSHR match"); +`endif + //pragma translate_on +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv new file mode 100644 index 0000000000..d9e9f23316 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -0,0 +1,352 @@ +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Licensed under the Solderpad Hardware License, Version 2.1 (the “License”); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Authors: Cesar Fuguet +// Date: February, 2023 +// Description: Interface adapter for the CVA6 core +module cva6_hpdcache_if_adapter +// Parameters +// {{{ +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = '0, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter bit InvalidateOnFlush = 1'b0, + parameter bit IsLoadPort = 1'b1 +) +// }}} + +// Ports +// {{{ +( + // Clock and active-low reset pins + input logic clk_i, + input logic rst_ni, + + // Port ID + input hpdcache_req_sid_t hpdcache_req_sid_i, + + // Request/response ports from/to the CVA6 core + input dcache_req_i_t cva6_req_i, + output dcache_req_o_t cva6_req_o, + input ariane_pkg::amo_req_t cva6_amo_req_i, + output ariane_pkg::amo_resp_t cva6_amo_resp_o, + + // Dcache flush signal + input logic cva6_dcache_flush_i, + output logic cva6_dcache_flush_ack_o, + + // Request port to the L1 Dcache + output logic hpdcache_req_valid_o, + input logic hpdcache_req_ready_i, + output hpdcache_req_t hpdcache_req_o, + output logic hpdcache_req_abort_o, + output hpdcache_tag_t hpdcache_req_tag_o, + output hpdcache_pkg::hpdcache_pma_t hpdcache_req_pma_o, + + // Response port from the L1 Dcache + input logic hpdcache_rsp_valid_i, + input hpdcache_rsp_t hpdcache_rsp_i +); + // }}} + + // Internal nets and registers + // {{{ + typedef enum { + FLUSH_IDLE, + FLUSH_PEND + } flush_fsm_t; + + logic hpdcache_req_is_uncacheable; + hpdcache_req_t hpdcache_req; + // }}} + + // Request forwarding + // {{{ + generate + // LOAD request + // {{{ + if (IsLoadPort == 1'b1) begin : load_port_gen + assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions( + CVA6Cfg, + { + {64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}} + , cva6_req_i.address_tag + , {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}} + } + ); + + // Request forwarding + assign hpdcache_req_valid_o = cva6_req_i.data_req; + assign hpdcache_req.addr_offset = cva6_req_i.address_index; + assign hpdcache_req.wdata = '0; + assign hpdcache_req.op = hpdcache_pkg::HPDCACHE_REQ_LOAD; + assign hpdcache_req.be = cva6_req_i.data_be; + assign hpdcache_req.size = cva6_req_i.data_size; + assign hpdcache_req.sid = hpdcache_req_sid_i; + assign hpdcache_req.tid = cva6_req_i.data_id; + assign hpdcache_req.need_rsp = 1'b1; + assign hpdcache_req.phys_indexed = 1'b0; + assign hpdcache_req.addr_tag = '0; // unused on virtually indexed request + assign hpdcache_req.pma.uncacheable = 1'b0; + assign hpdcache_req.pma.io = 1'b0; + assign hpdcache_req.pma.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; + + assign hpdcache_req_abort_o = cva6_req_i.kill_req; + assign hpdcache_req_tag_o = cva6_req_i.address_tag; + assign hpdcache_req_pma_o.uncacheable = hpdcache_req_is_uncacheable; + assign hpdcache_req_pma_o.io = 1'b0; + assign hpdcache_req_pma_o.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; + + // Response forwarding + assign cva6_req_o.data_rvalid = hpdcache_rsp_valid_i; + assign cva6_req_o.data_rdata = hpdcache_rsp_i.rdata; + assign cva6_req_o.data_rid = hpdcache_rsp_i.tid; + assign cva6_req_o.data_gnt = hpdcache_req_ready_i; + + // Assertions + // {{{ + // pragma translate_off + flush_on_load_port_assert : + assert property (@(posedge clk_i) disable iff (rst_ni !== 1'b1) (cva6_dcache_flush_i == 1'b0)) + else $error("Flush unsupported on load adapters"); + // pragma translate_on + // }}} + end // }}} + + // {{{ + else begin : store_amo_gen + // STORE/AMO request + logic [63:0] amo_addr; + hpdcache_req_offset_t amo_addr_offset; + hpdcache_tag_t amo_tag; + logic amo_is_word, amo_is_word_hi; + logic [63:0] amo_data; + logic [ 7:0] amo_data_be; + hpdcache_pkg::hpdcache_req_op_t amo_op; + logic [31:0] amo_resp_word; + logic amo_pending_q; + + hpdcache_req_t hpdcache_req_amo; + hpdcache_req_t hpdcache_req_store; + hpdcache_req_t hpdcache_req_flush; + + flush_fsm_t flush_fsm_q, flush_fsm_d; + + logic forward_store, forward_amo, forward_flush; + + // DCACHE flush request + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) begin : flush_ff + if (!rst_ni) begin + flush_fsm_q <= FLUSH_IDLE; + end else begin + flush_fsm_q <= flush_fsm_d; + end + end + + always_comb begin : flush_comb + forward_flush = 1'b0; + cva6_dcache_flush_ack_o = 1'b0; + + flush_fsm_d = flush_fsm_q; + + case (flush_fsm_q) + FLUSH_IDLE: begin + if (cva6_dcache_flush_i) begin + forward_flush = 1'b1; + if (hpdcache_req_ready_i) begin + flush_fsm_d = FLUSH_PEND; + end + end + end + FLUSH_PEND: begin + if (hpdcache_rsp_valid_i) begin + if (hpdcache_rsp_i.tid == '0) begin + cva6_dcache_flush_ack_o = 1'b1; + flush_fsm_d = FLUSH_IDLE; + end + end + end + default: begin + end + endcase + end + // }}} + + // AMO logic + // {{{ + always_comb begin : amo_op_comb + amo_addr = cva6_amo_req_i.operand_a; + amo_addr_offset = amo_addr[0+:HPDcacheCfg.reqOffsetWidth]; + amo_tag = amo_addr[HPDcacheCfg.reqOffsetWidth+:HPDcacheCfg.tagWidth]; + unique case (cva6_amo_req_i.amo_op) + ariane_pkg::AMO_LR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_LR; + ariane_pkg::AMO_SC: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SC; + ariane_pkg::AMO_SWAP: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SWAP; + ariane_pkg::AMO_ADD: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_ADD; + ariane_pkg::AMO_AND: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_AND; + ariane_pkg::AMO_OR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_OR; + ariane_pkg::AMO_XOR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_XOR; + ariane_pkg::AMO_MAX: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MAX; + ariane_pkg::AMO_MAXU: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MAXU; + ariane_pkg::AMO_MIN: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MIN; + ariane_pkg::AMO_MINU: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MINU; + default: amo_op = hpdcache_pkg::HPDCACHE_REQ_LOAD; + endcase + end + // }}} + + // Request forwarding + // {{{ + assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions( + CVA6Cfg, + { + {64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}} + , hpdcache_req.addr_tag, + {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}} + } + ); + + assign amo_is_word = (cva6_amo_req_i.size == 2'b10); + assign amo_is_word_hi = cva6_amo_req_i.operand_a[2]; + if (CVA6Cfg.XLEN == 64) begin : amo_data_64_gen + assign amo_data = amo_is_word ? {2{cva6_amo_req_i.operand_b[0+:32]}} : cva6_amo_req_i.operand_b; + assign amo_data_be = amo_is_word_hi ? 8'hf0 : amo_is_word ? 8'h0f : 8'hff; + end else begin : amo_data_32_gen + assign amo_data = {32'b0, cva6_amo_req_i.operand_b}; + assign amo_data_be = 8'h0f; + end + + assign hpdcache_req_amo = '{ + addr_offset: amo_addr_offset, + wdata: amo_data, + op: amo_op, + be: amo_data_be, + size: cva6_amo_req_i.size, + sid: hpdcache_req_sid_i, + tid: '1, + need_rsp: 1'b1, + phys_indexed: 1'b1, + addr_tag: amo_tag, + pma: '{ + uncacheable: hpdcache_req_is_uncacheable, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + + assign hpdcache_req_store = '{ + addr_offset: cva6_req_i.address_index, + wdata: cva6_req_i.data_wdata, + op: hpdcache_pkg::HPDCACHE_REQ_STORE, + be: cva6_req_i.data_be, + size: cva6_req_i.data_size, + sid: hpdcache_req_sid_i, + tid: '0, + need_rsp: 1'b0, + phys_indexed: 1'b1, + addr_tag: cva6_req_i.address_tag, + pma: '{ + uncacheable: hpdcache_req_is_uncacheable, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + + assign hpdcache_req_flush = '{ + addr_offset: '0, + addr_tag: '0, + wdata: '0, + op: + InvalidateOnFlush + ? + hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_INVAL_ALL + : + hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_ALL, + be: '0, + size: '0, + sid: hpdcache_req_sid_i, + tid: '0, + need_rsp: 1'b1, + phys_indexed: 1'b0, + pma: '{ + uncacheable: 1'b0, + io: 1'b0, + wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO + } + }; + + assign forward_store = cva6_req_i.data_req; + assign forward_amo = cva6_amo_req_i.req; + + assign hpdcache_req_valid_o = (forward_amo & ~amo_pending_q) | forward_store | forward_flush; + + assign hpdcache_req = forward_amo ? hpdcache_req_amo : + forward_store ? hpdcache_req_store : hpdcache_req_flush; + + assign hpdcache_req_abort_o = 1'b0; // unused on physically indexed requests + assign hpdcache_req_tag_o = '0; // unused on physically indexed requests + assign hpdcache_req_pma_o.uncacheable = 1'b0; + assign hpdcache_req_pma_o.io = 1'b0; + assign hpdcache_req_pma_o.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO; + // }}} + + // Response forwarding + // {{{ + if (CVA6Cfg.XLEN == 64) begin : amo_resp_64_gen + assign amo_resp_word = amo_is_word_hi + ? hpdcache_rsp_i.rdata[0][32 +: 32] + : hpdcache_rsp_i.rdata[0][0 +: 32]; + end else begin : amo_resp_32_gen + assign amo_resp_word = hpdcache_rsp_i.rdata[0]; + end + + assign cva6_req_o.data_rvalid = hpdcache_rsp_valid_i && (hpdcache_rsp_i.tid != '1); + assign cva6_req_o.data_rdata = hpdcache_rsp_i.rdata; + assign cva6_req_o.data_rid = hpdcache_rsp_i.tid; + assign cva6_req_o.data_gnt = hpdcache_req_ready_i; + + assign cva6_amo_resp_o.ack = hpdcache_rsp_valid_i && (hpdcache_rsp_i.tid == '1); + assign cva6_amo_resp_o.result = amo_is_word ? {{32{amo_resp_word[31]}}, amo_resp_word} + : hpdcache_rsp_i.rdata[0]; + // }}} + + always_ff @(posedge clk_i or negedge rst_ni) begin : amo_pending_ff + if (!rst_ni) begin + amo_pending_q <= 1'b0; + end else begin + amo_pending_q <= + ( cva6_amo_req_i.req & hpdcache_req_ready_i & ~amo_pending_q) | + (~cva6_amo_resp_o.ack & amo_pending_q); + end + end + + // Assertions + // {{{ + // pragma translate_off + forward_one_request_assert : + assert property (@(posedge clk_i) disable iff (rst_ni !== 1'b1) ($onehot0( + {forward_store, forward_amo, forward_flush} + ))) + else $error("Only one request shall be forwarded"); + // pragma translate_on + // }}} + end + // }}} + endgenerate + + assign hpdcache_req_o = hpdcache_req; + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv new file mode 100644 index 0000000000..6d13f6517c --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -0,0 +1,469 @@ +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Licensed under the Solderpad Hardware License, Version 2.1 (the “License”); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Authors: Cesar Fuguet +// Date: February, 2023 +// Description: CVA6 cache subsystem integrating standard CVA6's +// instruction cache and the Core-V High-Performance L1 +// data cache (CV-HPDcache). + +module cva6_hpdcache_subsystem +// Parameters +// {{{ +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter int NumPorts = 4, + parameter int NrHwPrefetchers = 4, + // AXI types + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_w_chan_t = logic, + parameter type axi_b_chan_t = logic, + parameter type axi_r_chan_t = logic, + parameter type noc_req_t = logic, + parameter type noc_resp_t = logic, + parameter type cmo_req_t = logic, + parameter type cmo_rsp_t = logic +) +// }}} + +// Ports +// {{{ +( + + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + + // AXI port to upstream memory/peripherals + // {{{ + // noc request, can be AXI or OpenPiton - SUBSYSTEM + output noc_req_t noc_req_o, + // noc response, can be AXI or OpenPiton - SUBSYSTEM + input noc_resp_t noc_resp_i, + // }}} + + // I$ + // {{{ + // Instruction cache enable - CSR_REGFILE + input logic icache_en_i, + // Flush the instruction cache - CONTROLLER + input logic icache_flush_i, + // instructino cache miss - PERF_COUNTERS + output logic icache_miss_o, + // Input address translation request - EX_STAGE + input icache_areq_t icache_areq_i, + // Output address translation request - EX_STAGE + output icache_arsp_t icache_areq_o, + // Input data translation request - FRONTEND + input icache_dreq_t icache_dreq_i, + // Output data translation request - FRONTEND + output icache_drsp_t icache_dreq_o, + // }}} + + // D$ + // {{{ + // Cache management + // Data cache enable - CSR_REGFILE + input logic dcache_enable_i, + // Data cache flush - CONTROLLER + input logic dcache_flush_i, + // Flush acknowledge - CONTROLLER + output logic dcache_flush_ack_o, + // Load or store miss - PERF_COUNTERS + output logic dcache_miss_o, + + // AMO request - EX_STAGE + input ariane_pkg::amo_req_t dcache_amo_req_i, + // AMO response - EX_STAGE + output ariane_pkg::amo_resp_t dcache_amo_resp_o, + // CMO interface request - TO_BE_COMPLETED + input cmo_req_t dcache_cmo_req_i, + // CMO interface response - TO_BE_COMPLETED + output cmo_rsp_t dcache_cmo_resp_o, + // Data cache input request ports - EX_STAGE + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, + // Data cache output request ports - EX_STAGE + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, + // Write buffer status to know if empty - EX_STAGE + output logic wbuffer_empty_o, + // Write buffer status to know if not non idempotent - EX_STAGE + output logic wbuffer_not_ni_o, + + // Hardware memory prefetcher configuration + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0] hwpf_base_set_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0][63:0] hwpf_base_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic [NrHwPrefetchers-1:0][63:0] hwpf_base_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0] hwpf_param_set_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0][63:0] hwpf_param_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic [NrHwPrefetchers-1:0][63:0] hwpf_param_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0] hwpf_throttle_set_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [NrHwPrefetchers-1:0][63:0] hwpf_throttle_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic [NrHwPrefetchers-1:0][63:0] hwpf_throttle_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic [ 63:0] hwpf_status_o + // }}} +); + // }}} + + function int unsigned __minu(int unsigned x, int unsigned y); + return x < y ? x : y; + endfunction + + function int unsigned __maxu(int unsigned x, int unsigned y); + return y < x ? x : y; + endfunction + + // I$ instantiation + // {{{ + logic icache_miss_valid, icache_miss_ready; + icache_req_t icache_miss; + + logic icache_miss_resp_valid; + icache_rtrn_t icache_miss_resp; + + localparam int ICACHE_RDTXID = 1 << (CVA6Cfg.MEM_TID_WIDTH - 1); + + cva6_icache #( + .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .RdTxId(ICACHE_RDTXID) + ) i_cva6_icache ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (icache_flush_i), + .en_i (icache_en_i), + .miss_o (icache_miss_o), + .areq_i (icache_areq_i), + .areq_o (icache_areq_o), + .dreq_i (icache_dreq_i), + .dreq_o (icache_dreq_o), + .mem_rtrn_vld_i(icache_miss_resp_valid), + .mem_rtrn_i (icache_miss_resp), + .mem_data_req_o(icache_miss_valid), + .mem_data_ack_i(icache_miss_ready), + .mem_data_o (icache_miss) + ); + // }}} + + // D$ instantiation + // {{{ + `include "hpdcache_typedef.svh" + + // 0: Page-Table Walk (PTW) + // 1: Load unit + // 2: Accelerator load + // 3: Store/AMO + // . + // . + // . + // NumPorts: CMO + // NumPorts + 1: Hardware Memory Prefetcher (hwpf) + localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; + + function automatic hpdcache_pkg::hpdcache_user_cfg_t hpdcacheSetConfig(); + hpdcache_pkg::hpdcache_user_cfg_t userCfg; + userCfg.nRequesters = HPDCACHE_NREQUESTERS; + userCfg.paWidth = CVA6Cfg.PLEN; + userCfg.wordWidth = CVA6Cfg.XLEN; + userCfg.sets = CVA6Cfg.DCACHE_NUM_WORDS; + userCfg.ways = CVA6Cfg.DCACHE_SET_ASSOC; + userCfg.clWords = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN; + userCfg.reqWords = 1; + userCfg.reqTransIdWidth = CVA6Cfg.DcacheIdWidth; + userCfg.reqSrcIdWidth = 3; // Up to 8 requesters + userCfg.victimSel = hpdcache_pkg::HPDCACHE_VICTIM_RANDOM; + userCfg.dataWaysPerRamWord = __minu(CVA6Cfg.DCACHE_SET_ASSOC, 128 / CVA6Cfg.XLEN); + userCfg.dataSetsPerRam = CVA6Cfg.DCACHE_NUM_WORDS; + userCfg.dataRamByteEnable = 1'b1; + userCfg.accessWords = __maxu(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN, 1 /*reqWords*/); + userCfg.mshrSets = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; + userCfg.mshrWays = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; + userCfg.mshrWaysPerRamWord = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; + userCfg.mshrSetsPerRam = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; + userCfg.mshrRamByteEnable = 1'b1; + userCfg.mshrUseRegbank = (CVA6Cfg.NrLoadBufEntries < 16); + userCfg.refillCoreRspFeedthrough = 1'b1; + userCfg.refillFifoDepth = 2; + userCfg.wbufDirEntries = CVA6Cfg.WtDcacheWbufDepth; + userCfg.wbufDataEntries = CVA6Cfg.WtDcacheWbufDepth; + userCfg.wbufWords = 1; + userCfg.wbufTimecntWidth = 3; + userCfg.rtabEntries = 4; + /*FIXME we should add additional CVA6 config parameters (flushEntries)*/ + userCfg.flushEntries = CVA6Cfg.WtDcacheWbufDepth; + /*FIXME we should add additional CVA6 config parameters (flushFifoDepth)*/ + userCfg.flushFifoDepth = CVA6Cfg.WtDcacheWbufDepth; + userCfg.memAddrWidth = CVA6Cfg.AxiAddrWidth; + userCfg.memIdWidth = CVA6Cfg.MEM_TID_WIDTH; + userCfg.memDataWidth = CVA6Cfg.AxiDataWidth; + userCfg.wtEn = + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT) || + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + userCfg.wbEn = + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB) || + (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + return userCfg; + endfunction + + localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = hpdcacheSetConfig(); + localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcache_pkg::hpdcacheBuildConfig( + HPDcacheUserCfg + ); + + `HPDCACHE_TYPEDEF_MEM_ATTR_T(hpdcache_mem_addr_t, hpdcache_mem_id_t, hpdcache_mem_data_t, + hpdcache_mem_be_t, HPDcacheCfg); + `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t); + `HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t); + `HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t); + `HPDCACHE_TYPEDEF_MEM_RESP_W_T(hpdcache_mem_resp_w_t, hpdcache_mem_id_t); + + `HPDCACHE_TYPEDEF_REQ_ATTR_T(hpdcache_req_offset_t, hpdcache_data_word_t, hpdcache_data_be_t, + hpdcache_req_data_t, hpdcache_req_be_t, hpdcache_req_sid_t, + hpdcache_req_tid_t, hpdcache_tag_t, HPDcacheCfg); + `HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t, + hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t, + hpdcache_tag_t); + `HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t, + hpdcache_req_tid_t); + + typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; + + logic dcache_read_ready; + logic dcache_read_valid; + hpdcache_mem_req_t dcache_read; + + logic dcache_read_resp_ready; + logic dcache_read_resp_valid; + hpdcache_mem_resp_r_t dcache_read_resp; + + logic dcache_write_ready; + logic dcache_write_valid; + hpdcache_mem_req_t dcache_write; + + logic dcache_write_data_ready; + logic dcache_write_data_valid; + hpdcache_mem_req_w_t dcache_write_data; + + logic dcache_write_resp_ready; + logic dcache_write_resp_valid; + hpdcache_mem_resp_w_t dcache_write_resp; + + cva6_hpdcache_wrapper #( + .CVA6Cfg(CVA6Cfg), + .HPDcacheCfg(HPDcacheCfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts(NumPorts), + .NrHwPrefetchers(NrHwPrefetchers), + .cmo_req_t(cmo_req_t), + .cmo_rsp_t(cmo_rsp_t), + .hpdcache_mem_addr_t(hpdcache_mem_addr_t), + .hpdcache_mem_id_t(hpdcache_mem_id_t), + .hpdcache_mem_data_t(hpdcache_mem_data_t), + .hpdcache_mem_be_t(hpdcache_mem_be_t), + .hpdcache_mem_req_t(hpdcache_mem_req_t), + .hpdcache_mem_req_w_t(hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_data_word_t(hpdcache_data_word_t), + .hpdcache_req_data_t(hpdcache_req_data_t), + .hpdcache_req_be_t(hpdcache_req_be_t), + .hpdcache_req_sid_t(hpdcache_req_sid_t), + .hpdcache_req_tid_t(hpdcache_req_tid_t), + .hpdcache_tag_t(hpdcache_tag_t), + .hpdcache_req_t(hpdcache_req_t), + .hpdcache_rsp_t(hpdcache_rsp_t), + .hpdcache_wbuf_timecnt_t(hpdcache_wbuf_timecnt_t), + .hpdcache_data_be_t(hpdcache_data_be_t) + ) i_dcache ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .dcache_enable_i(dcache_enable_i), + .dcache_flush_i(dcache_flush_i), + .dcache_flush_ack_o(dcache_flush_ack_o), + .dcache_miss_o(dcache_miss_o), + .dcache_amo_req_i(dcache_amo_req_i), + .dcache_amo_resp_o(dcache_amo_resp_o), + .dcache_cmo_req_i(dcache_cmo_req_i), + .dcache_cmo_resp_o(dcache_cmo_resp_o), + .dcache_req_ports_i(dcache_req_ports_i), + .dcache_req_ports_o(dcache_req_ports_o), + .wbuffer_empty_o(wbuffer_empty_o), + .wbuffer_not_ni_o(wbuffer_not_ni_o), + .hwpf_base_set_i(hwpf_base_set_i), + .hwpf_base_i(hwpf_base_i), + .hwpf_base_o(hwpf_base_o), + .hwpf_param_set_i(hwpf_param_set_i), + .hwpf_param_i(hwpf_param_i), + .hwpf_param_o(hwpf_param_o), + .hwpf_throttle_set_i(hwpf_throttle_set_i), + .hwpf_throttle_i(hwpf_throttle_i), + .hwpf_throttle_o(hwpf_throttle_o), + .hwpf_status_o(hwpf_status_o), + + .dcache_mem_req_read_ready_i(dcache_read_ready), + .dcache_mem_req_read_valid_o(dcache_read_valid), + .dcache_mem_req_read_o(dcache_read), + + .dcache_mem_resp_read_ready_o(dcache_read_resp_ready), + .dcache_mem_resp_read_valid_i(dcache_read_resp_valid), + .dcache_mem_resp_read_i(dcache_read_resp), + + .dcache_mem_req_write_ready_i(dcache_write_ready), + .dcache_mem_req_write_valid_o(dcache_write_valid), + .dcache_mem_req_write_o(dcache_write), + + .dcache_mem_req_write_data_ready_i(dcache_write_data_ready), + .dcache_mem_req_write_data_valid_o(dcache_write_data_valid), + .dcache_mem_req_write_data_o(dcache_write_data), + + .dcache_mem_resp_write_ready_o(dcache_write_resp_ready), + .dcache_mem_resp_write_valid_i(dcache_write_resp_valid), + .dcache_mem_resp_write_i(dcache_write_resp) + ); + + // AXI arbiter instantiation + // {{{ + cva6_hpdcache_subsystem_axi_arbiter #( + .CVA6Cfg (CVA6Cfg), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), + + .AxiAddrWidth (CVA6Cfg.AxiAddrWidth), + .AxiDataWidth (CVA6Cfg.AxiDataWidth), + .AxiIdWidth (CVA6Cfg.AxiIdWidth), + .AxiUserWidth (CVA6Cfg.AxiUserWidth), + .axi_ar_chan_t(axi_ar_chan_t), + .axi_aw_chan_t(axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_b_chan_t (axi_b_chan_t), + .axi_r_chan_t (axi_r_chan_t), + .axi_req_t (noc_req_t), + .axi_rsp_t (noc_resp_t) + ) i_axi_arbiter ( + .clk_i, + .rst_ni, + + .icache_miss_valid_i(icache_miss_valid), + .icache_miss_ready_o(icache_miss_ready), + .icache_miss_i (icache_miss), + .icache_miss_id_i (hpdcache_mem_id_t'(ICACHE_RDTXID)), + + .icache_miss_resp_valid_o(icache_miss_resp_valid), + .icache_miss_resp_o (icache_miss_resp), + + .dcache_read_ready_o(dcache_read_ready), + .dcache_read_valid_i(dcache_read_valid), + .dcache_read_i (dcache_read), + + .dcache_read_resp_ready_i(dcache_read_resp_ready), + .dcache_read_resp_valid_o(dcache_read_resp_valid), + .dcache_read_resp_o (dcache_read_resp), + + .dcache_write_ready_o(dcache_write_ready), + .dcache_write_valid_i(dcache_write_valid), + .dcache_write_i (dcache_write), + + .dcache_write_data_ready_o(dcache_write_data_ready), + .dcache_write_data_valid_i(dcache_write_data_valid), + .dcache_write_data_i (dcache_write_data), + + .dcache_write_resp_ready_i(dcache_write_resp_ready), + .dcache_write_resp_valid_o(dcache_write_resp_valid), + .dcache_write_resp_o (dcache_write_resp), + + .axi_req_o (noc_req_o), + .axi_resp_i(noc_resp_i) + ); + // }}} + + // Assertions + // {{{ + // pragma translate_off + initial begin : initial_assertions + assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDcacheCfg.u.nRequesters)) + else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough"); + assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth) + else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth"); + assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.mshrSets * HPDcacheCfg.u.mshrWays) + 1)) + else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ and I$ miss requests "); + assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.wbufDirEntries) + 1)) + else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ write requests "); + end + + a_invalid_instruction_fetch : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X", + icache_dreq_o.vaddr, + icache_dreq_o.data + ); + + a_invalid_write_data : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X", + { + dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index + }, + dcache_req_ports_i[2].data_be, + dcache_req_ports_i[2].data_wdata + ); + + for (genvar j = 0; j < 2; j++) begin : gen_assertion + a_invalid_read_data : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_o[j].data_rvalid && ~dcache_req_ports_i[j].kill_req |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid data on port %01d: data=%016X", + j, + dcache_req_ports_o[j].data_rdata + ); + end + // pragma translate_on + // }}} + +endmodule : cva6_hpdcache_subsystem diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv new file mode 100644 index 0000000000..901175f79c --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -0,0 +1,420 @@ +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Licensed under the Solderpad Hardware License, Version 2.1 (the “License”); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Authors: Cesar Fuguet +// Date: February, 2023 +// Description: AXI arbiter for the CVA6 cache subsystem integrating standard +// CVA6's instruction cache and the Core-V High-Performance +// L1 Dcache (CV-HPDcache). + +module cva6_hpdcache_subsystem_axi_arbiter +// Parameters +// {{{ +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + + parameter int unsigned AxiAddrWidth = 1, + parameter int unsigned AxiDataWidth = 1, + parameter int unsigned AxiIdWidth = 1, + parameter int unsigned AxiUserWidth = 1, + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_w_chan_t = logic, + parameter type axi_b_chan_t = logic, + parameter type axi_r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Interfaces from/to I$ + // {{{ + input logic icache_miss_valid_i, + output logic icache_miss_ready_o, + input icache_req_t icache_miss_i, + input hpdcache_mem_id_t icache_miss_id_i, + + output logic icache_miss_resp_valid_o, + output icache_rtrn_t icache_miss_resp_o, + // }}} + + // Interfaces from/to D$ + // {{{ + // Read interface + output logic dcache_read_ready_o, + input logic dcache_read_valid_i, + input hpdcache_mem_req_t dcache_read_i, + + input logic dcache_read_resp_ready_i, + output logic dcache_read_resp_valid_o, + output hpdcache_mem_resp_r_t dcache_read_resp_o, + + // Write interface + output logic dcache_write_ready_o, + input logic dcache_write_valid_i, + input hpdcache_mem_req_t dcache_write_i, + + output logic dcache_write_data_ready_o, + input logic dcache_write_data_valid_i, + input hpdcache_mem_req_w_t dcache_write_data_i, + + input logic dcache_write_resp_ready_i, + output logic dcache_write_resp_valid_o, + output hpdcache_mem_resp_w_t dcache_write_resp_o, + // }}} + + // AXI port to upstream memory/peripherals + // {{{ + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i + // }}} +); + // }}} + + // Internal type definitions + // {{{ + + localparam int MEM_RESP_RT_DEPTH = (1 << CVA6Cfg.MEM_TID_WIDTH); + typedef hpdcache_mem_id_t [MEM_RESP_RT_DEPTH-1:0] mem_resp_rt_t; + typedef logic [CVA6Cfg.ICACHE_LINE_WIDTH-1:0] icache_resp_data_t; + // }}} + + // Adapt the I$ interface to the HPDcache memory interface + // {{{ + localparam int ICACHE_CL_WORDS = CVA6Cfg.ICACHE_LINE_WIDTH / 64; + localparam int ICACHE_CL_WORD_INDEX = $clog2(ICACHE_CL_WORDS); + localparam int ICACHE_CL_SIZE = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8); + localparam int ICACHE_WORD_SIZE = 3; + localparam int ICACHE_MEM_REQ_CL_LEN = + (CVA6Cfg.ICACHE_LINE_WIDTH + CVA6Cfg.AxiDataWidth - 1)/CVA6Cfg.AxiDataWidth; + localparam int ICACHE_MEM_REQ_CL_SIZE = + (CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH) ? + $clog2( + CVA6Cfg.AxiDataWidth / 8 + ) : ICACHE_CL_SIZE; + + // I$ request + hpdcache_mem_req_t icache_miss_req_wdata; + logic icache_miss_req_w, icache_miss_req_wok; + + hpdcache_mem_req_t icache_miss_req_rdata; + logic icache_miss_req_r, icache_miss_req_rok; + + logic icache_miss_pending_q; + + // This FIFO has two functionnalities: + // - Stabilize the ready-valid protocol. The ICACHE can abort a valid + // transaction without receiving the corresponding ready signal. This + // behavior is not supported by AXI. + // - Cut a possible long timing path. + hpdcache_fifo_reg #( + .FIFO_DEPTH (1), + .fifo_data_t(hpdcache_mem_req_t) + ) i_icache_miss_req_fifo ( + .clk_i, + .rst_ni, + + .w_i (icache_miss_req_w), + .wok_o (icache_miss_req_wok), + .wdata_i(icache_miss_req_wdata), + + .r_i (icache_miss_req_r), + .rok_o (icache_miss_req_rok), + .rdata_o(icache_miss_req_rdata) + ); + + assign icache_miss_req_w = icache_miss_valid_i, icache_miss_ready_o = icache_miss_req_wok; + + assign icache_miss_req_wdata.mem_req_addr = icache_miss_i.paddr; + assign icache_miss_req_wdata.mem_req_len = icache_miss_i.nc ? 0 : ICACHE_MEM_REQ_CL_LEN - 1; + assign icache_miss_req_wdata.mem_req_size = icache_miss_i.nc ? ICACHE_WORD_SIZE : ICACHE_MEM_REQ_CL_SIZE; + assign icache_miss_req_wdata.mem_req_id = icache_miss_i.tid; + assign icache_miss_req_wdata.mem_req_command = hpdcache_pkg::HPDCACHE_MEM_READ; + assign icache_miss_req_wdata.mem_req_atomic = hpdcache_pkg::hpdcache_mem_atomic_e'(0); + assign icache_miss_req_wdata.mem_req_cacheable = ~icache_miss_i.nc; + + + // I$ response + logic icache_miss_resp_w, icache_miss_resp_wok; + hpdcache_mem_resp_r_t icache_miss_resp_wdata; + + logic icache_miss_resp_data_w, icache_miss_resp_data_wok; + logic icache_miss_resp_data_r, icache_miss_resp_data_rok; + icache_resp_data_t icache_miss_resp_data_rdata; + + logic icache_miss_resp_meta_w, icache_miss_resp_meta_wok; + logic icache_miss_resp_meta_r, icache_miss_resp_meta_rok; + hpdcache_mem_id_t icache_miss_resp_meta_id; + + icache_resp_data_t icache_miss_rdata; + + generate + if (CVA6Cfg.AxiDataWidth < CVA6Cfg.ICACHE_LINE_WIDTH) begin + hpdcache_fifo_reg #( + .FIFO_DEPTH (1), + .fifo_data_t(hpdcache_mem_id_t) + ) i_icache_refill_meta_fifo ( + .clk_i, + .rst_ni, + + .w_i (icache_miss_resp_meta_w), + .wok_o (icache_miss_resp_meta_wok), + .wdata_i(icache_miss_resp_wdata.mem_resp_r_id), + + .r_i (icache_miss_resp_meta_r), + .rok_o (icache_miss_resp_meta_rok), + .rdata_o(icache_miss_resp_meta_id) + ); + + hpdcache_data_upsize #( + .WR_WIDTH(CVA6Cfg.AxiDataWidth), + .RD_WIDTH(CVA6Cfg.ICACHE_LINE_WIDTH), + .DEPTH (1) + ) i_icache_hpdcache_data_upsize ( + .clk_i, + .rst_ni, + + .w_i (icache_miss_resp_data_w), + .wlast_i(icache_miss_resp_wdata.mem_resp_r_last), + .wok_o (icache_miss_resp_data_wok), + .wdata_i(icache_miss_resp_wdata.mem_resp_r_data), + + .r_i (icache_miss_resp_data_r), + .rok_o (icache_miss_resp_data_rok), + .rdata_o(icache_miss_resp_data_rdata) + ); + + assign icache_miss_resp_meta_r = 1'b1, icache_miss_resp_data_r = 1'b1; + + assign icache_miss_resp_meta_w = icache_miss_resp_w & icache_miss_resp_wdata.mem_resp_r_last; + + assign icache_miss_resp_data_w = icache_miss_resp_w; + + assign icache_miss_resp_wok = icache_miss_resp_data_wok & ( + icache_miss_resp_meta_wok | ~icache_miss_resp_wdata.mem_resp_r_last); + + assign icache_miss_rdata = icache_miss_resp_data_rdata; + + end else begin + assign icache_miss_resp_data_rok = icache_miss_resp_w; + assign icache_miss_resp_meta_rok = icache_miss_resp_w; + assign icache_miss_resp_wok = 1'b1; + assign icache_miss_resp_meta_id = icache_miss_resp_wdata.mem_resp_r_id; + assign icache_miss_resp_data_rdata = icache_miss_resp_wdata.mem_resp_r_data; + + // In the case of uncacheable accesses, the Icache expects the data to be right-aligned + always_comb begin : icache_miss_resp_data_comb + if (!icache_miss_req_rdata.mem_req_cacheable) begin + automatic logic [ICACHE_CL_WORD_INDEX - 1:0] icache_miss_word_index; + automatic logic [63:0] icache_miss_word; + icache_miss_word_index = icache_miss_req_rdata.mem_req_addr[3+:ICACHE_CL_WORD_INDEX]; + icache_miss_word = icache_miss_resp_data_rdata[icache_miss_word_index*64+:64]; + icache_miss_rdata = {{CVA6Cfg.ICACHE_LINE_WIDTH - 64{1'b0}}, icache_miss_word}; + end else begin + icache_miss_rdata = icache_miss_resp_data_rdata; + end + end + end + endgenerate + + assign icache_miss_resp_valid_o = icache_miss_resp_meta_rok; + assign icache_miss_resp_o.rtype = wt_cache_pkg::ICACHE_IFILL_ACK; + assign icache_miss_resp_o.user = '0; + assign icache_miss_resp_o.inv = '0; + assign icache_miss_resp_o.tid = icache_miss_resp_meta_id; + assign icache_miss_resp_o.data = icache_miss_rdata; + + // consume the Icache miss on the arrival of the response. The request + // metadata is decoded to forward the correct word in case of uncacheable + // Icache access + assign icache_miss_req_r = icache_miss_resp_meta_rok; + // }}} + + // Read request arbiter + // {{{ + logic [1:0] mem_req_read_ready; + logic [1:0] mem_req_read_valid; + hpdcache_mem_req_t [1:0] mem_req_read; + + logic mem_req_read_ready_arb; + logic mem_req_read_valid_arb; + hpdcache_mem_req_t mem_req_read_arb; + + assign mem_req_read_valid[0] = icache_miss_req_rok & ~icache_miss_pending_q; + assign mem_req_read[0] = icache_miss_req_rdata; + + assign dcache_read_ready_o = mem_req_read_ready[1]; + assign mem_req_read_valid[1] = dcache_read_valid_i; + assign mem_req_read[1] = dcache_read_i; + + hpdcache_mem_req_read_arbiter #( + .N (2), + .hpdcache_mem_req_t(hpdcache_mem_req_t) + ) i_mem_req_read_arbiter ( + .clk_i, + .rst_ni, + + .mem_req_read_ready_o(mem_req_read_ready), + .mem_req_read_valid_i(mem_req_read_valid), + .mem_req_read_i (mem_req_read), + + .mem_req_read_ready_i(mem_req_read_ready_arb), + .mem_req_read_valid_o(mem_req_read_valid_arb), + .mem_req_read_o (mem_req_read_arb) + ); + // }}} + + // Read response demultiplexor + // {{{ + logic mem_resp_read_ready; + logic mem_resp_read_valid; + hpdcache_mem_resp_r_t mem_resp_read; + + logic mem_resp_read_ready_arb[1:0]; + logic mem_resp_read_valid_arb[1:0]; + hpdcache_mem_resp_r_t mem_resp_read_arb [1:0]; + + mem_resp_rt_t mem_resp_read_rt; + + always_comb begin + for (int i = 0; i < MEM_RESP_RT_DEPTH; i++) begin + mem_resp_read_rt[i] = (i == int'(icache_miss_id_i)) ? 0 : 1; + end + end + + hpdcache_mem_resp_demux #( + .N (2), + .resp_t (hpdcache_mem_resp_r_t), + .resp_id_t(hpdcache_mem_id_t) + ) i_mem_resp_read_demux ( + .clk_i, + .rst_ni, + + .mem_resp_ready_o(mem_resp_read_ready), + .mem_resp_valid_i(mem_resp_read_valid), + .mem_resp_id_i (mem_resp_read.mem_resp_r_id), + .mem_resp_i (mem_resp_read), + + .mem_resp_ready_i(mem_resp_read_ready_arb), + .mem_resp_valid_o(mem_resp_read_valid_arb), + .mem_resp_o (mem_resp_read_arb), + + .mem_resp_rt_i(mem_resp_read_rt) + ); + + assign icache_miss_resp_w = mem_resp_read_valid_arb[0]; + assign icache_miss_resp_wdata = mem_resp_read_arb[0]; + assign mem_resp_read_ready_arb[0] = icache_miss_resp_wok; + + assign dcache_read_resp_valid_o = mem_resp_read_valid_arb[1]; + assign dcache_read_resp_o = mem_resp_read_arb[1]; + assign mem_resp_read_ready_arb[1] = dcache_read_resp_ready_i; + // }}} + + // I$ miss pending + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) begin : icache_miss_pending_ff + if (!rst_ni) begin + icache_miss_pending_q <= 1'b0; + end else begin + icache_miss_pending_q <= ( (icache_miss_req_rok & mem_req_read_ready[0]) & ~icache_miss_pending_q) | + (~(icache_miss_req_r & icache_miss_req_rok) & icache_miss_pending_q); + end + end + // }}} + + // AXI adapters + // {{{ + + hpdcache_mem_to_axi_write #( + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .aw_chan_t (axi_aw_chan_t), + .w_chan_t (axi_w_chan_t), + .b_chan_t (axi_b_chan_t) + ) i_hpdcache_mem_to_axi_write ( + .req_ready_o(dcache_write_ready_o), + .req_valid_i(dcache_write_valid_i), + .req_i (dcache_write_i), + + .req_data_ready_o(dcache_write_data_ready_o), + .req_data_valid_i(dcache_write_data_valid_i), + .req_data_i (dcache_write_data_i), + + .resp_ready_i(dcache_write_resp_ready_i), + .resp_valid_o(dcache_write_resp_valid_o), + .resp_o (dcache_write_resp_o), + + .axi_aw_valid_o(axi_req_o.aw_valid), + .axi_aw_o (axi_req_o.aw), + .axi_aw_ready_i(axi_resp_i.aw_ready), + + .axi_w_valid_o(axi_req_o.w_valid), + .axi_w_o (axi_req_o.w), + .axi_w_ready_i(axi_resp_i.w_ready), + + .axi_b_valid_i(axi_resp_i.b_valid), + .axi_b_i (axi_resp_i.b), + .axi_b_ready_o(axi_req_o.b_ready) + ); + + hpdcache_mem_to_axi_read #( + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .ar_chan_t (axi_ar_chan_t), + .r_chan_t (axi_r_chan_t) + ) i_hpdcache_mem_to_axi_read ( + .req_ready_o(mem_req_read_ready_arb), + .req_valid_i(mem_req_read_valid_arb), + .req_i (mem_req_read_arb), + + .resp_ready_i(mem_resp_read_ready), + .resp_valid_o(mem_resp_read_valid), + .resp_o (mem_resp_read), + + .axi_ar_valid_o(axi_req_o.ar_valid), + .axi_ar_o (axi_req_o.ar), + .axi_ar_ready_i(axi_resp_i.ar_ready), + + .axi_r_valid_i(axi_resp_i.r_valid), + .axi_r_i (axi_resp_i.r), + .axi_r_ready_o(axi_req_o.r_ready) + ); + + // }}} + + // Assertions + // {{{ + // pragma translate_off + initial + assert (CVA6Cfg.MEM_TID_WIDTH <= AxiIdWidth) + else $fatal(1, "MEM_TID_WIDTH shall be less or equal to AxiIdWidth"); + initial + assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH) + else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Icache line"); + initial + assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.DCACHE_LINE_WIDTH) + else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Dcache line"); + // pragma translate_on + // }}} + +endmodule : cva6_hpdcache_subsystem_axi_arbiter diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv new file mode 100644 index 0000000000..7727dc703d --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_hpdcache_wrapper.sv @@ -0,0 +1,426 @@ +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Licensed under the Solderpad Hardware License, Version 2.1 (the “License”); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Authors: Cesar Fuguet +// Date: February, 2023 +// Description: Wrapper for the Core-V High-Performance L1 data cache (CV-HPDcache) + +`include "hpdcache_typedef.svh" + +module cva6_hpdcache_wrapper +// Parameters +// {{{ +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = '0, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter int NumPorts = 4, + parameter int NrHwPrefetchers = 4, + + parameter type cmo_req_t = logic, + parameter type cmo_rsp_t = logic, + parameter type hpdcache_mem_addr_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_data_t = logic, + parameter type hpdcache_mem_be_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + parameter type hpdcache_wbuf_timecnt_t = logic, + parameter type hpdcache_data_be_t = logic +) +// }}} + +// Ports +// {{{ +( + + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + + // D$ + // {{{ + // Cache management + // Data cache enable - CSR_REGFILE + input logic dcache_enable_i, + // Data cache flush - CONTROLLER + input logic dcache_flush_i, + // Flush acknowledge - CONTROLLER + output logic dcache_flush_ack_o, + // Load or store miss - PERF_COUNTERS + output logic dcache_miss_o, + + // AMO request/response - EX_STAGE + input ariane_pkg::amo_req_t dcache_amo_req_i, + output ariane_pkg::amo_resp_t dcache_amo_resp_o, + // CMO interface request/response + input cmo_req_t dcache_cmo_req_i, + output cmo_rsp_t dcache_cmo_resp_o, + // Data cache input request/response ports - EX_STAGE + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, + // Write buffer status - EX_STAGE + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, + + // Hardware memory prefetcher configuration + input logic [NrHwPrefetchers-1:0] hwpf_base_set_i, + input logic [NrHwPrefetchers-1:0][63:0] hwpf_base_i, + output logic [NrHwPrefetchers-1:0][63:0] hwpf_base_o, + input logic [NrHwPrefetchers-1:0] hwpf_param_set_i, + input logic [NrHwPrefetchers-1:0][63:0] hwpf_param_i, + output logic [NrHwPrefetchers-1:0][63:0] hwpf_param_o, + input logic [NrHwPrefetchers-1:0] hwpf_throttle_set_i, + input logic [NrHwPrefetchers-1:0][63:0] hwpf_throttle_i, + output logic [NrHwPrefetchers-1:0][63:0] hwpf_throttle_o, + output logic [ 63:0] hwpf_status_o, + + input logic dcache_mem_req_read_ready_i, + output logic dcache_mem_req_read_valid_o, + output hpdcache_mem_req_t dcache_mem_req_read_o, + + output logic dcache_mem_resp_read_ready_o, + input logic dcache_mem_resp_read_valid_i, + input hpdcache_mem_resp_r_t dcache_mem_resp_read_i, + + input logic dcache_mem_req_write_ready_i, + output logic dcache_mem_req_write_valid_o, + output hpdcache_mem_req_t dcache_mem_req_write_o, + + input logic dcache_mem_req_write_data_ready_i, + output logic dcache_mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t dcache_mem_req_write_data_o, + + output logic dcache_mem_resp_write_ready_o, + input logic dcache_mem_resp_write_valid_i, + input hpdcache_mem_resp_w_t dcache_mem_resp_write_i +); + + localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; + + typedef logic [63:0] hwpf_stride_param_t; + + logic dcache_req_valid[HPDCACHE_NREQUESTERS]; + logic dcache_req_ready[HPDCACHE_NREQUESTERS]; + hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS]; + logic dcache_req_abort[HPDCACHE_NREQUESTERS]; + hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS]; + hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS]; + logic dcache_rsp_valid[HPDCACHE_NREQUESTERS]; + hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS]; + logic dcache_read_miss, dcache_write_miss; + + logic [ 2:0] snoop_valid; + logic [ 2:0] snoop_abort; + hpdcache_req_offset_t [ 2:0] snoop_addr_offset; + hpdcache_tag_t [ 2:0] snoop_addr_tag; + logic [ 2:0] snoop_phys_indexed; + + logic dcache_cmo_req_is_prefetch; + + hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_in; + hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out; + + generate + dcache_req_i_t dcache_req_ports[NumPorts - 1]; + + for (genvar r = 0; r < (NumPorts - 1); r++) begin : gen_cva6_hpdcache_load_if_adapter + assign dcache_req_ports[r] = dcache_req_ports_i[r]; + + cva6_hpdcache_if_adapter #( + .CVA6Cfg (CVA6Cfg), + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), + .InvalidateOnFlush (1'b0), + .IsLoadPort (1'b1) + ) i_cva6_hpdcache_load_if_adapter ( + .clk_i, + .rst_ni, + + .hpdcache_req_sid_i(hpdcache_req_sid_t'(r)), + + .cva6_req_i (dcache_req_ports[r]), + .cva6_req_o (dcache_req_ports_o[r]), + .cva6_amo_req_i ('0), + .cva6_amo_resp_o( /* unused */), + + .cva6_dcache_flush_i (1'b0), + .cva6_dcache_flush_ack_o( /* unused */), + + .hpdcache_req_valid_o(dcache_req_valid[r]), + .hpdcache_req_ready_i(dcache_req_ready[r]), + .hpdcache_req_o (dcache_req[r]), + .hpdcache_req_abort_o(dcache_req_abort[r]), + .hpdcache_req_tag_o (dcache_req_tag[r]), + .hpdcache_req_pma_o (dcache_req_pma[r]), + + .hpdcache_rsp_valid_i(dcache_rsp_valid[r]), + .hpdcache_rsp_i (dcache_rsp[r]) + ); + end + + cva6_hpdcache_if_adapter #( + .CVA6Cfg (CVA6Cfg), + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), + .InvalidateOnFlush (CVA6Cfg.DcacheInvalidateOnFlush), + .IsLoadPort (1'b0) + ) i_cva6_hpdcache_store_if_adapter ( + .clk_i, + .rst_ni, + + .hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts - 1)), + + .cva6_req_i (dcache_req_ports_i[NumPorts-1]), + .cva6_req_o (dcache_req_ports_o[NumPorts-1]), + .cva6_amo_req_i (dcache_amo_req_i), + .cva6_amo_resp_o(dcache_amo_resp_o), + + .cva6_dcache_flush_i (dcache_flush_i), + .cva6_dcache_flush_ack_o(dcache_flush_ack_o), + + .hpdcache_req_valid_o(dcache_req_valid[NumPorts-1]), + .hpdcache_req_ready_i(dcache_req_ready[NumPorts-1]), + .hpdcache_req_o (dcache_req[NumPorts-1]), + .hpdcache_req_abort_o(dcache_req_abort[NumPorts-1]), + .hpdcache_req_tag_o (dcache_req_tag[NumPorts-1]), + .hpdcache_req_pma_o (dcache_req_pma[NumPorts-1]), + + .hpdcache_rsp_valid_i(dcache_rsp_valid[NumPorts-1]), + .hpdcache_rsp_i (dcache_rsp[NumPorts-1]) + ); + +`ifdef HPDCACHE_ENABLE_CMO + cva6_hpdcache_cmo_if_adapter #( + .cmo_req_t(cmo_req_t), + .cmo_rsp_t(cmo_rsp_t) + ) i_cva6_hpdcache_cmo_if_adapter ( + .clk_i, + .rst_ni, + + .dcache_req_sid_i(hpdcache_req_sid_t'(NumPorts)), + + .cva6_cmo_req_i (dcache_cmo_req_i), + .cva6_cmo_resp_o(dcache_cmo_resp_o), + + .dcache_req_valid_o(dcache_req_valid[NumPorts]), + .dcache_req_ready_i(dcache_req_ready[NumPorts]), + .dcache_req_o (dcache_req[NumPorts]), + .dcache_req_abort_o(dcache_req_abort[NumPorts]), + .dcache_req_tag_o (dcache_req_tag[NumPorts]), + .dcache_req_pma_o (dcache_req_pma[NumPorts]), + + .dcache_rsp_valid_i(dcache_rsp_valid[NumPorts]), + .dcache_rsp_i (dcache_rsp[NumPorts]) + ); +`else + assign dcache_req_valid[NumPorts] = 1'b0, + dcache_req[NumPorts] = '0, + dcache_req_abort[NumPorts] = 1'b0, + dcache_req_tag[NumPorts] = '0, + dcache_req_pma[NumPorts] = '0; +`endif + endgenerate + + // Snoop load port + assign snoop_valid[0] = dcache_req_valid[1] & dcache_req_ready[1], + snoop_abort[0] = dcache_req_abort[1], + snoop_addr_offset[0] = dcache_req[1].addr_offset, + snoop_addr_tag[0] = dcache_req_tag[1], + snoop_phys_indexed[0] = dcache_req[1].phys_indexed; + + // Snoop Store/AMO port + assign snoop_valid[1] = dcache_req_valid[NumPorts-1] & dcache_req_ready[NumPorts-1], + snoop_abort[1] = dcache_req_abort[NumPorts-1], + snoop_addr_offset[1] = dcache_req[NumPorts-1].addr_offset, + snoop_addr_tag[1] = dcache_req_tag[NumPorts-1], + snoop_phys_indexed[1] = dcache_req[NumPorts-1].phys_indexed; + +`ifdef HPDCACHE_ENABLE_CMO + // Snoop CMO port (in case of read prefetch accesses) + assign dcache_cmo_req_is_prefetch = hpdcache_pkg::is_cmo_prefetch( + dcache_req[NumPorts].op, dcache_req[NumPorts].size + ); + assign snoop_valid[2] = dcache_req_valid[NumPorts] + & dcache_req_ready[NumPorts] + & dcache_cmo_req_is_prefetch, + snoop_abort[2] = dcache_req_abort[NumPorts], + snoop_addr_offset[2] = dcache_req[NumPorts].addr_offset, + snoop_addr_tag[2] = dcache_req_tag[NumPorts], + snoop_phys_indexed[2] = dcache_req[NumPorts].phys_indexed; +`else + assign snoop_valid[2] = 1'b0, + snoop_abort[2] = 1'b0, + snoop_addr_offset[2] = '0, + snoop_addr_tag[2] = '0, + snoop_phys_indexed[2] = 1'b0; +`endif + + generate + for (genvar h = 0; h < NrHwPrefetchers; h++) begin : gen_hwpf_throttle + assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]); + assign hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]); + end + endgenerate + + hwpf_stride_wrapper #( + .HPDcacheCfg (HPDcacheCfg), + .NUM_HW_PREFETCH (NrHwPrefetchers), + .NUM_SNOOP_PORTS (3), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t) + ) i_hwpf_stride_wrapper ( + .clk_i, + .rst_ni, + + .hwpf_stride_base_set_i (hwpf_base_set_i), + .hwpf_stride_base_i (hwpf_base_i), + .hwpf_stride_base_o (hwpf_base_o), + .hwpf_stride_param_set_i (hwpf_param_set_i), + .hwpf_stride_param_i (hwpf_param_i), + .hwpf_stride_param_o (hwpf_param_o), + .hwpf_stride_throttle_set_i(hwpf_throttle_set_i), + .hwpf_stride_throttle_i (hwpf_throttle_in), + .hwpf_stride_throttle_o (hwpf_throttle_out), + .hwpf_stride_status_o (hwpf_status_o), + + .snoop_valid_i (snoop_valid), + .snoop_abort_i (snoop_abort), + .snoop_addr_offset_i (snoop_addr_offset), + .snoop_addr_tag_i (snoop_addr_tag), + .snoop_phys_indexed_i(snoop_phys_indexed), + + .hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts + 1)), + + .hpdcache_req_valid_o(dcache_req_valid[NumPorts+1]), + .hpdcache_req_ready_i(dcache_req_ready[NumPorts+1]), + .hpdcache_req_o (dcache_req[NumPorts+1]), + .hpdcache_req_abort_o(dcache_req_abort[NumPorts+1]), + .hpdcache_req_tag_o (dcache_req_tag[NumPorts+1]), + .hpdcache_req_pma_o (dcache_req_pma[NumPorts+1]), + .hpdcache_rsp_valid_i(dcache_rsp_valid[NumPorts+1]), + .hpdcache_rsp_i (dcache_rsp[NumPorts+1]) + ); + + hpdcache #( + .HPDcacheCfg (HPDcacheCfg), + .wbuf_timecnt_t (hpdcache_wbuf_timecnt_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_data_be_t (hpdcache_data_be_t), + .hpdcache_req_offset_t(hpdcache_req_offset_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_mem_addr_t (hpdcache_mem_addr_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_data_t (hpdcache_mem_data_t), + .hpdcache_mem_be_t (hpdcache_mem_be_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t) + ) i_hpdcache ( + .clk_i, + .rst_ni, + + .wbuf_flush_i(dcache_flush_i), + + .core_req_valid_i(dcache_req_valid), + .core_req_ready_o(dcache_req_ready), + .core_req_i (dcache_req), + .core_req_abort_i(dcache_req_abort), + .core_req_tag_i (dcache_req_tag), + .core_req_pma_i (dcache_req_pma), + + .core_rsp_valid_o(dcache_rsp_valid), + .core_rsp_o (dcache_rsp), + + .mem_req_read_ready_i(dcache_mem_req_read_ready_i), + .mem_req_read_valid_o(dcache_mem_req_read_valid_o), + .mem_req_read_o (dcache_mem_req_read_o), + + .mem_resp_read_ready_o(dcache_mem_resp_read_ready_o), + .mem_resp_read_valid_i(dcache_mem_resp_read_valid_i), + .mem_resp_read_i (dcache_mem_resp_read_i), + + .mem_req_write_ready_i(dcache_mem_req_write_ready_i), + .mem_req_write_valid_o(dcache_mem_req_write_valid_o), + .mem_req_write_o (dcache_mem_req_write_o), + + .mem_req_write_data_ready_i(dcache_mem_req_write_data_ready_i), + .mem_req_write_data_valid_o(dcache_mem_req_write_data_valid_o), + .mem_req_write_data_o (dcache_mem_req_write_data_o), + + .mem_resp_write_ready_o(dcache_mem_resp_write_ready_o), + .mem_resp_write_valid_i(dcache_mem_resp_write_valid_i), + .mem_resp_write_i (dcache_mem_resp_write_i), + + .evt_cache_write_miss_o(dcache_write_miss), + .evt_cache_read_miss_o (dcache_read_miss), + .evt_uncached_req_o ( /* unused */), + .evt_cmo_req_o ( /* unused */), + .evt_write_req_o ( /* unused */), + .evt_read_req_o ( /* unused */), + .evt_prefetch_req_o ( /* unused */), + .evt_req_on_hold_o ( /* unused */), + .evt_rtab_rollback_o ( /* unused */), + .evt_stall_refill_o ( /* unused */), + .evt_stall_o ( /* unused */), + + .wbuf_empty_o(wbuffer_empty_o), + + .cfg_enable_i (dcache_enable_i), + .cfg_wbuf_threshold_i (3'd2), + .cfg_wbuf_reset_timecnt_on_write_i (1'b1), + .cfg_wbuf_sequential_waw_i (1'b0), + .cfg_wbuf_inhibit_write_coalescing_i(1'b0), + .cfg_prefetch_updt_plru_i (1'b1), + .cfg_error_on_cacheable_amo_i (1'b0), + .cfg_rtab_single_entry_i (1'b0), + .cfg_default_wb_i (1'b0) + ); + + assign dcache_miss_o = dcache_read_miss, wbuffer_not_ni_o = wbuffer_empty_o; + // }}} + +endmodule : cva6_hpdcache_wrapper diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_icache.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_icache.sv new file mode 100644 index 0000000000..be7becb0a0 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_icache.sv @@ -0,0 +1,598 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Instruction cache that is compatible with openpiton. +// +// Some notes: +// +// 1) refills always have the size of one cache line, except for accesses to the I/O region, which is mapped +// to the top half of the physical address space (bit 39 = 1). the data width of the interface has the width +// of one cache line, and hence the ifills can be transferred in a single cycle. note that the ifills must be +// consumed unconditionally. +// +// 2) instruction fetches are always assumed to be aligned to 32bit (lower 2 bits are ignored) +// +// 3) NC accesses to I/O space are expected to return 32bit from memory. +// + + +module cva6_icache + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + /// ID to be used for read transactions + parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 0 +) ( + input logic clk_i, + input logic rst_ni, + + /// flush the icache, flush and kill have to be asserted together + input logic flush_i, + /// enable icache + input logic en_i, + /// to performance counter + output logic miss_o, + // address translation requests + input icache_areq_t areq_i, + output icache_arsp_t areq_o, + // data requests + input icache_dreq_t dreq_i, + output icache_drsp_t dreq_o, + // refill port + input logic mem_rtrn_vld_i, + input icache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output icache_req_t mem_data_o +); + + localparam ICACHE_OFFSET_WIDTH = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8); + localparam ICACHE_NUM_WORDS = 2 ** (CVA6Cfg.ICACHE_INDEX_WIDTH - ICACHE_OFFSET_WIDTH); + localparam ICACHE_CL_IDX_WIDTH = $clog2(ICACHE_NUM_WORDS); // excluding byte offset + + // functions + function automatic logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] icache_way_bin2oh( + input logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] in); + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + // signals + logic cache_en_d, cache_en_q; // cache is enabled + logic [CVA6Cfg.VLEN-1:0] vaddr_d, vaddr_q; + logic paddr_is_nc; // asserted if physical address is non-cacheable + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] cl_hit; // hit from tag compare + logic cache_rden; // triggers cache lookup + logic cache_wren; // triggers write to cacheline + logic + cmp_en_d, + cmp_en_q; // enable tag comparison in next cycle. used to cut long path due to NC signal. + logic flush_d, flush_q; // used to register and signal pending flushes + + // replacement strategy + logic update_lfsr; // shift the LFSR + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] inv_way; // first non-valid encountered + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] rnd_way; // random index for replacement + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] repl_way; // way to replace + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] repl_way_oh_d, repl_way_oh_q; // way to replace (onehot) + logic all_ways_valid; // we need to switch repl strategy since all are valid + + // invalidations / flushing + logic inv_en; // incoming invalidations + logic inv_d, inv_q; // invalidation in progress + logic flush_en, flush_done; // used to flush cache entries + logic [ICACHE_CL_IDX_WIDTH-1:0] flush_cnt_d, flush_cnt_q; // used to flush cache entries + + // mem arrays + logic cl_we; // write enable to memory array + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] cl_req; // request to memory array + logic [ ICACHE_CL_IDX_WIDTH-1:0] cl_index; // this is a cache-line index, to memory array + logic [ICACHE_OFFSET_WIDTH-1:0] cl_offset_d, cl_offset_q; // offset in cache line + logic [CVA6Cfg.ICACHE_TAG_WIDTH-1:0] cl_tag_d, cl_tag_q; // this is the cache tag + logic [CVA6Cfg.ICACHE_TAG_WIDTH-1:0] cl_tag_rdata [CVA6Cfg.ICACHE_SET_ASSOC-1:0]; // these are the tags coming from the tagmem + logic [CVA6Cfg.ICACHE_LINE_WIDTH-1:0] cl_rdata [CVA6Cfg.ICACHE_SET_ASSOC-1:0]; // these are the cachelines coming from the cache + logic [CVA6Cfg.ICACHE_USER_LINE_WIDTH-1:0] cl_ruser[CVA6Cfg.ICACHE_SET_ASSOC-1:0]; // these are the cachelines coming from the user cache + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0][CVA6Cfg.FETCH_WIDTH-1:0] cl_sel; // selected word from each cacheline + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0][CVA6Cfg.FETCH_USER_WIDTH-1:0] cl_user; // selected word from each cacheline + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] vld_req; // bit enable for valid regs + logic vld_we; // valid bits write enable + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] vld_wdata; // valid bits to write + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] vld_rdata; // valid bits coming from valid regs + logic [ICACHE_CL_IDX_WIDTH-1:0] vld_addr; // valid bit + + // cpmtroller FSM + typedef enum logic [2:0] { + FLUSH, + IDLE, + READ, + MISS, + KILL_ATRANS, + KILL_MISS + } state_e; + state_e state_d, state_q; + + /////////////////////////////////////////////////////// + // address -> cl_index mapping, interface plumbing + /////////////////////////////////////////////////////// + + // extract tag from physical address, check if NC + assign cl_tag_d = (areq_i.fetch_valid) ? areq_i.fetch_paddr[CVA6Cfg.ICACHE_TAG_WIDTH+CVA6Cfg.ICACHE_INDEX_WIDTH-1:CVA6Cfg.ICACHE_INDEX_WIDTH] : cl_tag_q; + + // noncacheable if request goes to I/O space, or if cache is disabled + assign paddr_is_nc = (~cache_en_q) | (~config_pkg::is_inside_cacheable_regions( + CVA6Cfg, {{64 - CVA6Cfg.PLEN{1'b0}}, cl_tag_d, {CVA6Cfg.ICACHE_INDEX_WIDTH{1'b0}}} + )); + + // pass exception through + assign dreq_o.ex = areq_i.fetch_exception; + + // latch this in case we have to stall later on + // make sure this is 32bit aligned + assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q; + assign areq_o.fetch_vaddr = (vaddr_q >> CVA6Cfg.FETCH_ALIGN_BITS) << CVA6Cfg.FETCH_ALIGN_BITS; + + // split virtual address into index and offset to address cache arrays + assign cl_index = vaddr_d[CVA6Cfg.ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH]; + + + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset + // if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory + assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? (dreq_i.vaddr >> CVA6Cfg.FETCH_ALIGN_BITS) << CVA6Cfg.FETCH_ALIGN_BITS : + ( paddr_is_nc & mem_data_req_o ) ? {{ICACHE_OFFSET_WIDTH-1{1'b0}}, cl_offset_q[2]}<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case + cl_offset_q; + // request word address instead of cl address in case of NC access + assign mem_data_o.paddr = (paddr_is_nc) ? {cl_tag_d, vaddr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:3], 3'b0} : // align to 64bit + {cl_tag_d, vaddr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH], {ICACHE_OFFSET_WIDTH{1'b0}}}; // align to cl + end else begin : gen_piton_offset + // icache fills are either cachelines or 4byte fills, depending on whether they go to the Piton I/O space or not. + // since the piton cache system replicates the data, we can always index the full CL + assign cl_offset_d = (dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr >> 2, 2'b0} : cl_offset_q; + + // request word address instead of cl address in case of NC access + assign mem_data_o.paddr = (paddr_is_nc) ? {cl_tag_d, vaddr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:2], 2'b0} : // align to 32bit + {cl_tag_d, vaddr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH], {ICACHE_OFFSET_WIDTH{1'b0}}}; // align to cl + end + + + assign mem_data_o.tid = RdTxId; + + assign mem_data_o.nc = paddr_is_nc; + // way that is being replaced + assign mem_data_o.way = repl_way; + assign dreq_o.vaddr = vaddr_q; + + // invalidations take two cycles + assign inv_d = inv_en; + + /////////////////////////////////////////////////////// + // main control logic + /////////////////////////////////////////////////////// + logic addr_ni; + assign addr_ni = config_pkg::is_inside_nonidempotent_regions( + CVA6Cfg, {{64 - CVA6Cfg.PLEN{1'b0}}, areq_i.fetch_paddr} + ); + always_comb begin : p_fsm + // default assignment + state_d = state_q; + cache_en_d = cache_en_q & en_i;// disabling the cache is always possible, enable needs to go via flush + flush_en = 1'b0; + cmp_en_d = 1'b0; + cache_rden = 1'b0; + cache_wren = 1'b0; + inv_en = 1'b0; + flush_d = flush_q | flush_i; // register incoming flush + + // interfaces + dreq_o.ready = 1'b0; + areq_o.fetch_req = 1'b0; + dreq_o.valid = 1'b0; + mem_data_req_o = 1'b0; + // performance counter + miss_o = 1'b0; + + // handle invalidations unconditionally + // note: invald are mutually exclusive with + // ifills, since both arrive over the same IF + // however, we need to make sure below that we + // do not trigger a cache readout at the same time... + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_INV_REQ) begin + inv_en = 1'b1; + end + + unique case (state_q) + ////////////////////////////////// + // this clears all valid bits + FLUSH: begin + flush_en = 1'b1; + if (flush_done) begin + state_d = IDLE; + flush_d = 1'b0; + // if the cache was not enabled set this + cache_en_d = en_i; + end + end + ////////////////////////////////// + // wait for an incoming request + IDLE: begin + // only enable tag comparison if cache is enabled + cmp_en_d = cache_en_q; + + // handle pending flushes, or perform cache clear upon enable + if (flush_d || (en_i && !cache_en_q)) begin + state_d = FLUSH; + // wait for incoming requests + end else begin + // mem requests are for sure invals here + if (!mem_rtrn_vld_i) begin + dreq_o.ready = 1'b1; + // we have a new request + if (dreq_i.req) begin + cache_rden = 1'b1; + state_d = READ; + end + end + if (dreq_i.kill_s1) begin + state_d = IDLE; + end + end + end + ////////////////////////////////// + // check whether we have a hit + // in case the cache is disabled, + // or in case the address is NC, we + // reuse the miss mechanism to handle + // the request + READ: begin + areq_o.fetch_req = '1; + // only enable tag comparison if cache is enabled + cmp_en_d = cache_en_q; + // readout speculatively + cache_rden = cache_en_q; + + if (areq_i.fetch_valid && (!dreq_i.spec || ((CVA6Cfg.NonIdemPotenceEn && !addr_ni) || (!CVA6Cfg.NonIdemPotenceEn)))) begin + // check if we have to flush + if (flush_d) begin + state_d = IDLE; + // we have a hit or an exception output valid result + end else if (((|cl_hit && cache_en_q) || areq_i.fetch_exception.valid) && !inv_q) begin + dreq_o.valid = ~dreq_i.kill_s2; // just don't output in this case + state_d = IDLE; + + // we can accept another request + // and stay here, but only if no inval is coming in + // note: we are not expecting ifill return packets here... + if (!mem_rtrn_vld_i) begin + dreq_o.ready = 1'b1; + if (dreq_i.req) begin + state_d = READ; + end + end + // if a request is being killed at this stage, + // we have to bail out and wait for the address translation to complete + if (dreq_i.kill_s1) begin + state_d = IDLE; + end + // we have a miss / NC transaction + end else if (dreq_i.kill_s2) begin + state_d = IDLE; + end else if (!inv_q) begin + cmp_en_d = 1'b0; + // only count this as a miss if the cache is enabled, and + // the address is cacheable + // send out ifill request + mem_data_req_o = 1'b1; + if (mem_data_ack_i) begin + miss_o = ~paddr_is_nc; + state_d = MISS; + end + end + // bail out if this request is being killed (and we missed on the TLB) + end else if (dreq_i.kill_s2 || flush_d) begin + state_d = KILL_ATRANS; + end + end + ////////////////////////////////// + // wait until the memory transaction + // returns. do not write to memory + // if the nc bit is set. + MISS: begin + // note: this is mutually exclusive with ICACHE_INV_REQ, + // so we do not have to check for invals here + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_IFILL_ACK) begin + state_d = IDLE; + // only return data if request is not being killed + if (!(dreq_i.kill_s2 || flush_d)) begin + dreq_o.valid = 1'b1; + // only write to cache if this address is cacheable + cache_wren = ~paddr_is_nc; + end + // bail out if this request is being killed + end else if (dreq_i.kill_s2 || flush_d) begin + state_d = KILL_MISS; + end + end + ////////////////////////////////// + // killed address translation, + // wait until paddr is valid, and go + // back to idle + KILL_ATRANS: begin + areq_o.fetch_req = '1; + if (areq_i.fetch_valid) begin + state_d = IDLE; + end + end + ////////////////////////////////// + // killed miss, + // wait until memory responds and + // go back to idle + KILL_MISS: begin + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_IFILL_ACK) begin + state_d = IDLE; + end + end + default: begin + // we should never get here + state_d = FLUSH; + end + endcase // state_q + end + + /////////////////////////////////////////////////////// + // valid bit invalidation and replacement strategy + /////////////////////////////////////////////////////// + + // note: it cannot happen that we get an invalidation + a cl replacement + // in the same cycle as these requests arrive via the same interface + // flushes take precedence over invalidations (it is ok if we ignore + // the inval since the cache is cleared anyway) + + assign flush_cnt_d = (flush_done) ? '0 : (flush_en) ? flush_cnt_q + 1 : flush_cnt_q; + + assign flush_done = (flush_cnt_q == (ICACHE_NUM_WORDS - 1)); + + // invalidation/clearing address + // flushing takes precedence over invals + assign vld_addr = (flush_en) ? flush_cnt_q : + (inv_en) ? mem_rtrn_i.inv.idx[CVA6Cfg.ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH] : + cl_index; + + assign vld_req = (flush_en || cache_rden) ? '1 : + (mem_rtrn_i.inv.all && inv_en) ? '1 : + (mem_rtrn_i.inv.vld && inv_en) ? icache_way_bin2oh( + mem_rtrn_i.inv.way + ) : repl_way_oh_q; + + assign vld_wdata = (cache_wren) ? '1 : '0; + + assign vld_we = (cache_wren | inv_en | flush_en); + // assign vld_req = (vld_we | cache_rden); + + + // chose random replacement if all are valid + assign update_lfsr = cache_wren & all_ways_valid; + assign repl_way = (all_ways_valid) ? rnd_way : inv_way; + assign repl_way_oh_d = (cmp_en_q) ? icache_way_bin2oh(repl_way) : repl_way_oh_q; + + // enable signals for memory arrays + assign cl_req = (cache_rden) ? '1 : (cache_wren) ? repl_way_oh_q : '0; + assign cl_we = cache_wren; + + + // find invalid cache line + lzc #( + .WIDTH(CVA6Cfg.ICACHE_SET_ASSOC) + ) i_lzc ( + .in_i (~vld_rdata), + .cnt_o (inv_way), + .empty_o(all_ways_valid) + ); + + // generate random cacheline index + lfsr #( + .LfsrWidth(8), + .OutWidth (CVA6Cfg.ICACHE_SET_ASSOC_WIDTH) + ) i_lfsr ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .en_i (update_lfsr), + .out_o (rnd_way) + ); + + + /////////////////////////////////////////////////////// + // tag comparison, hit generation + /////////////////////////////////////////////////////// + + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] hit_idx; + + for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel + assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i]; + assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; + assign cl_user[i] = CVA6Cfg.FETCH_USER_EN ? cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0; + end + + + lzc #( + .WIDTH(CVA6Cfg.ICACHE_SET_ASSOC) + ) i_lzc_hit ( + .in_i (cl_hit), + .cnt_o (hit_idx), + .empty_o() + ); + + always_comb begin + if (cmp_en_q) begin + dreq_o.data = cl_sel[hit_idx]; + dreq_o.user = CVA6Cfg.FETCH_USER_EN ? cl_user[hit_idx] : '0; + end else begin + dreq_o.data = mem_rtrn_i.data[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; + dreq_o.user = CVA6Cfg.FETCH_USER_EN ? mem_rtrn_i.user[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0; + end + end + + /////////////////////////////////////////////////////// + // memory arrays and regs + /////////////////////////////////////////////////////// + + + logic [CVA6Cfg.ICACHE_TAG_WIDTH:0] cl_tag_valid_rdata[CVA6Cfg.ICACHE_SET_ASSOC-1:0]; + + for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_sram + // Tag RAM + sram_cache #( + // tag + valid bit + .DATA_WIDTH (CVA6Cfg.ICACHE_TAG_WIDTH + 1), + .BYTE_ACCESS(0), + .TECHNO_CUT (CVA6Cfg.TechnoCut), + .NUM_WORDS (ICACHE_NUM_WORDS) + ) tag_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (vld_req[i]), + .we_i (vld_we), + .addr_i (vld_addr), + // we can always use the saved tag here since it takes a + // couple of cycle until we write to the cache upon a miss + .wuser_i('0), + .wdata_i({vld_wdata[i], cl_tag_q}), + .be_i ('1), + .ruser_o(), + .rdata_o(cl_tag_valid_rdata[i]) + ); + + assign cl_tag_rdata[i] = cl_tag_valid_rdata[i][CVA6Cfg.ICACHE_TAG_WIDTH-1:0]; + assign vld_rdata[i] = cl_tag_valid_rdata[i][CVA6Cfg.ICACHE_TAG_WIDTH]; + + // Data RAM + sram_cache #( + .USER_WIDTH (CVA6Cfg.ICACHE_USER_LINE_WIDTH), + .DATA_WIDTH (CVA6Cfg.ICACHE_LINE_WIDTH), + .USER_EN (CVA6Cfg.FETCH_USER_EN), + .BYTE_ACCESS(0), + .TECHNO_CUT (CVA6Cfg.TechnoCut), + .NUM_WORDS (ICACHE_NUM_WORDS) + ) data_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (cl_req[i]), + .we_i (cl_we), + .addr_i (cl_index), + .wuser_i(mem_rtrn_i.user), + .wdata_i(mem_rtrn_i.data), + .be_i ('1), + .ruser_o(cl_ruser[i]), + .rdata_o(cl_rdata[i]) + ); + end + + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + cl_tag_q <= '0; + flush_cnt_q <= '0; + vaddr_q <= '0; + cmp_en_q <= '0; + cache_en_q <= '0; + flush_q <= '0; + state_q <= FLUSH; + cl_offset_q <= '0; + repl_way_oh_q <= '0; + inv_q <= '0; + end else begin + cl_tag_q <= cl_tag_d; + flush_cnt_q <= flush_cnt_d; + vaddr_q <= vaddr_d; + cmp_en_q <= cmp_en_d; + cache_en_q <= cache_en_d; + flush_q <= flush_d; + state_q <= state_d; + cl_offset_q <= cl_offset_d; + repl_way_oh_q <= repl_way_oh_d; + inv_q <= inv_d; + end + end + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + repl_inval0 : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) cache_wren |-> !(mem_rtrn_i.inv.all | mem_rtrn_i.inv.vld)) + else $fatal(1, "[l1 icache] cannot replace cacheline and invalidate cacheline simultaneously"); + + repl_inval1 : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) (mem_rtrn_i.inv.all | mem_rtrn_i.inv.vld) |-> !cache_wren) + else $fatal(1, "[l1 icache] cannot replace cacheline and invalidate cacheline simultaneously"); + + invalid_state : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) (state_q inside {FLUSH, IDLE, READ, MISS, KILL_ATRANS, KILL_MISS})) + else $fatal(1, "[l1 icache] fsm reached an invalid state"); + + hot1 : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) (!inv_en) |-> cache_rden |=> cmp_en_q |-> $onehot0( + cl_hit + )) + else $fatal(1, "[l1 icache] cl_hit signal must be hot1"); + + // this is only used for verification! + logic vld_mirror[ICACHE_NUM_WORDS-1:0][CVA6Cfg.ICACHE_SET_ASSOC-1:0]; + logic [CVA6Cfg.ICACHE_TAG_WIDTH-1:0] tag_mirror[ICACHE_NUM_WORDS-1:0][CVA6Cfg.ICACHE_SET_ASSOC-1:0]; + logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror + if (!rst_ni) begin + vld_mirror <= '{default: '0}; + tag_mirror <= '{default: '0}; + end else begin + for (int i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin + if (vld_req[i] & vld_we) begin + vld_mirror[vld_addr][i] <= vld_wdata[i]; + tag_mirror[vld_addr][i] <= cl_tag_q; + end + end + end + end + + for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_dupl + assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == cl_tag_q) & vld_mirror[vld_addr][i] & (|vld_wdata); + end + + tag_write_duplicate : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) |vld_req |-> vld_we |-> !(|tag_write_duplicate_test)) + else $fatal(1, "[l1 icache] cannot allocate a CL that is already present in the cache"); + + + initial begin + // assert wrong parameterizations + assert (CVA6Cfg.ICACHE_INDEX_WIDTH <= 12) + else $fatal(1, "[l1 icache] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif + //pragma translate_on + +endmodule // cva6_icache diff --git a/flow/designs/src/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/flow/designs/src/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv new file mode 100644 index 0000000000..c16597e8b3 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -0,0 +1,214 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Nils Wistoff , ETH Zurich +// Date: 07.09.2020 +// Description: wrapper module to connect the L1I$ to a 64bit AXI bus. +// + +module cva6_icache_axi_wrapper + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input riscv::priv_lvl_t priv_lvl_i, + + input logic flush_i, // flush the icache, flush and kill have to be asserted together + input logic en_i, // enable icache + output logic miss_o, // to performance counter + // address translation requests + input icache_areq_t areq_i, + output icache_arsp_t areq_o, + // data requests + input icache_dreq_t dreq_i, + output icache_drsp_t dreq_o, + // AXI refill port + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i +); + + localparam AxiNumWords = (CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (CVA6Cfg.ICACHE_LINE_WIDTH > CVA6Cfg.DCACHE_LINE_WIDTH) + + (CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (CVA6Cfg.ICACHE_LINE_WIDTH <= CVA6Cfg.DCACHE_LINE_WIDTH) ; + + logic icache_mem_rtrn_vld; + icache_rtrn_t icache_mem_rtrn; + logic icache_mem_data_req; + logic icache_mem_data_ack; + icache_req_t icache_mem_data; + + logic axi_rd_req; + logic axi_rd_gnt; + logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr; + logic [ $clog2(AxiNumWords)-1:0] axi_rd_blen; + logic [ 2:0] axi_rd_size; + logic [ CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in; + logic axi_rd_rdy; + logic axi_rd_lock; + logic axi_rd_last; + logic axi_rd_valid; + logic [CVA6Cfg.AxiDataWidth-1:0] axi_rd_data; + logic [ CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_out; + logic axi_rd_exokay; + + logic req_valid_d, req_valid_q; + icache_req_t req_data_d, req_data_q; + logic first_d, first_q; + logic [CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] + rd_shift_d, rd_shift_q; + + // Keep read request asserted until we have an AXI grant. This is not guaranteed by icache (but + // required by AXI). + assign req_valid_d = ~axi_rd_gnt & (icache_mem_data_req | req_valid_q); + + // Update read request information on a new request + assign req_data_d = (icache_mem_data_req) ? icache_mem_data : req_data_q; + + // We have a new or pending read request + assign axi_rd_req = icache_mem_data_req | req_valid_q; + assign axi_rd_addr = CVA6Cfg.AxiAddrWidth'(req_data_d.paddr); + + // Fetch a full cache line on a cache miss, or a single word on a bypassed access + assign axi_rd_blen = (req_data_d.nc) ? '0 : CVA6Cfg.ICACHE_LINE_WIDTH / 64 - 1; + assign axi_rd_size = $clog2(CVA6Cfg.AxiDataWidth / 8); // Maximum + assign axi_rd_id_in = req_data_d.tid; + assign axi_rd_rdy = 1'b1; + assign axi_rd_lock = 1'b0; + + // Immediately acknowledge read request. This is an implicit requirement for the icache. + assign icache_mem_data_ack = icache_mem_data_req; + + // Return data as soon as last word arrives + assign icache_mem_rtrn_vld = axi_rd_valid & axi_rd_last; + assign icache_mem_rtrn.data = rd_shift_d; + assign icache_mem_rtrn.tid = req_data_q.tid; + assign icache_mem_rtrn.rtype = wt_cache_pkg::ICACHE_IFILL_ACK; + assign icache_mem_rtrn.inv = '0; + + // ------- + // I-Cache + // ------- + cva6_icache #( + // use ID 0 for icache reads + .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .RdTxId(0) + ) i_cva6_icache ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .en_i (en_i), + .miss_o (miss_o), + .areq_i (areq_i), + .areq_o (areq_o), + .dreq_i (dreq_i), + .dreq_o (dreq_o), + .mem_rtrn_vld_i(icache_mem_rtrn_vld), + .mem_rtrn_i (icache_mem_rtrn), + .mem_data_req_o(icache_mem_data_req), + .mem_data_ack_i(icache_mem_data_ack), + .mem_data_o (icache_mem_data) + ); + + // -------- + // AXI shim + // -------- + axi_shim #( + .CVA6Cfg (CVA6Cfg), + .AxiNumWords(AxiNumWords), + .axi_req_t (axi_req_t), + .axi_rsp_t (axi_rsp_t) + ) i_axi_shim ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rd_req_i (axi_rd_req), + .rd_gnt_o (axi_rd_gnt), + .rd_addr_i (axi_rd_addr), + .rd_blen_i (axi_rd_blen), + .rd_size_i (axi_rd_size), + .rd_id_i (axi_rd_id_in), + .rd_rdy_i (axi_rd_rdy), + .rd_lock_i (axi_rd_lock), + .rd_last_o (axi_rd_last), + .rd_valid_o (axi_rd_valid), + .rd_data_o (axi_rd_data), + .rd_user_o (), + .rd_id_o (axi_rd_id_out), + .rd_exokay_o(axi_rd_exokay), + .wr_req_i ('0), + .wr_gnt_o (), + .wr_addr_i ('0), + .wr_data_i ('0), + .wr_user_i ('0), + .wr_be_i ('0), + .wr_blen_i ('0), + .wr_size_i ('0), + .wr_id_i ('0), + .wr_lock_i ('0), + .wr_atop_i ('0), + .wr_rdy_i ('0), + .wr_valid_o (), + .wr_id_o (), + .wr_exokay_o(), + .axi_req_o (axi_req_o), + .axi_resp_i (axi_resp_i) + ); + + // Buffer burst data in shift register + always_comb begin : p_axi_rtrn_shift + first_d = first_q; + rd_shift_d = rd_shift_q; + + if (axi_rd_valid) begin + first_d = axi_rd_last; + if (CVA6Cfg.ICACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin + rd_shift_d = axi_rd_data; + end else begin + rd_shift_d = {axi_rd_data, rd_shift_q[CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]}; + end + + // If this is a single word transaction, we need to make sure that word is placed at offset 0 + if (first_q) begin + rd_shift_d[0] = axi_rd_data; + end + end + end + + // Registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf + if (!rst_ni) begin + req_valid_q <= 1'b0; + req_data_q <= '0; + first_q <= 1'b1; + rd_shift_q <= '0; + end else begin + req_valid_q <= req_valid_d; + req_data_q <= req_data_d; + first_q <= first_d; + rd_shift_q <= rd_shift_d; + end + end + +endmodule // cva6_icache_axi_wrapper diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/hpdcache_typedef.svh b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/hpdcache_typedef.svh new file mode 100644 index 0000000000..84498bf180 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/hpdcache_typedef.svh @@ -0,0 +1,120 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : February, 2023 + * Description : HPDcache Types' Definition + * History : + */ +`ifndef __HPDCACHE_TYPEDEF_SVH__ +`define __HPDCACHE_TYPEDEF_SVH__ + +`define HPDCACHE_DECL_MEM_REQ_T(__addr_t, __id_t) \ + struct packed { \ + __addr_t mem_req_addr; \ + hpdcache_pkg::hpdcache_mem_len_t mem_req_len; \ + hpdcache_pkg::hpdcache_mem_size_t mem_req_size; \ + __id_t mem_req_id; \ + hpdcache_pkg::hpdcache_mem_command_e mem_req_command; \ + hpdcache_pkg::hpdcache_mem_atomic_e mem_req_atomic; \ + logic mem_req_cacheable; \ + } + +`define HPDCACHE_DECL_MEM_RESP_R_T(__id_t, __data_t) \ + struct packed { \ + hpdcache_pkg::hpdcache_mem_error_e mem_resp_r_error; \ + __id_t mem_resp_r_id; \ + __data_t mem_resp_r_data; \ + logic mem_resp_r_last; \ + } + +`define HPDCACHE_DECL_MEM_REQ_W_T(__data_t, __be_t) \ + struct packed { \ + __data_t mem_req_w_data; \ + __be_t mem_req_w_be; \ + logic mem_req_w_last; \ + } + +`define HPDCACHE_DECL_MEM_RESP_W_T(__id_t) \ + struct packed { \ + logic mem_resp_w_is_atomic; \ + hpdcache_pkg::hpdcache_mem_error_e mem_resp_w_error; \ + __id_t mem_resp_w_id; \ + } + +`define HPDCACHE_TYPEDEF_MEM_ATTR_T(__addr_t, __id_t, __data_t, __be_t, __params) \ + typedef logic [ __params.u.memAddrWidth-1:0] __addr_t; \ + typedef logic [ __params.u.memIdWidth-1:0] __id_t; \ + typedef logic [ __params.u.memDataWidth-1:0] __data_t; \ + typedef logic [__params.u.memDataWidth/8-1:0] __be_t + +`define HPDCACHE_TYPEDEF_MEM_REQ_T(__name__, __addr_t, __id_t) \ + typedef `HPDCACHE_DECL_MEM_REQ_T(__addr_t, __id_t) __name__ + +`define HPDCACHE_TYPEDEF_MEM_RESP_R_T(__name__, __id_t, __data_t) \ + typedef `HPDCACHE_DECL_MEM_RESP_R_T(__id_t, __data_t) __name__ + +`define HPDCACHE_TYPEDEF_MEM_REQ_W_T(__name__, __data_t, __be_t) \ + typedef `HPDCACHE_DECL_MEM_REQ_W_T(__data_t, __be_t) __name__ + +`define HPDCACHE_TYPEDEF_MEM_RESP_W_T(__name__, __id_t) \ + typedef `HPDCACHE_DECL_MEM_RESP_W_T(__id_t) __name__ + +`define HPDCACHE_DECL_REQ_T(__offset_t, __data_t, __be_t, __sid_t, __tid_t, __tag_t) \ + struct packed { \ + __offset_t addr_offset; \ + __data_t wdata; \ + hpdcache_pkg::hpdcache_req_op_t op; \ + __be_t be; \ + hpdcache_pkg::hpdcache_req_size_t size; \ + __sid_t sid; \ + __tid_t tid; \ + logic need_rsp; \ + logic phys_indexed; \ + __tag_t addr_tag; \ + hpdcache_pkg::hpdcache_pma_t pma; \ + } + +`define HPDCACHE_TYPEDEF_REQ_ATTR_T(__offset_t, __word_t, __word_be_t, __data_t, __be_t, __sid_t, __tid_t, __tag_t, __params) \ + typedef logic [ __params.tagWidth-1:0] __tag_t; \ + typedef logic [ __params.u.wordWidth-1:0] __word_t; \ + typedef logic [ __params.u.wordWidth/8-1:0] __word_be_t; \ + typedef logic [ __params.reqOffsetWidth-1:0] __offset_t; \ + typedef __word_t [ __params.u.reqWords-1:0] __data_t; \ + typedef __word_be_t [ __params.u.reqWords-1:0] __be_t; \ + typedef logic [ __params.u.reqSrcIdWidth-1:0] __sid_t; \ + typedef logic [__params.u.reqTransIdWidth-1:0] __tid_t + +`define HPDCACHE_TYPEDEF_REQ_T(__name__, __offset_t, __data_t, __be_t, __sid_t, __tid_t, __tag_t) \ + typedef `HPDCACHE_DECL_REQ_T(__offset_t, __data_t, __be_t, __sid_t, __tid_t, __tag_t) __name__ + +`define HPDCACHE_DECL_RSP_T(__data_t, __sid_t, __tid_t) \ + struct packed { \ + __data_t rdata; \ + __sid_t sid; \ + __tid_t tid; \ + logic error; \ + logic aborted; \ + } + +`define HPDCACHE_TYPEDEF_RSP_T(__name__, __data_t, __sid_t, __tid_t) \ + typedef `HPDCACHE_DECL_RSP_T(__data_t, __sid_t, __tid_t) __name__ + +`endif // __HPDCACHE_TYPEDEF_SVH__ diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv new file mode 100644 index 0000000000..df0d630976 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv @@ -0,0 +1,60 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : One-hot to binary decoder + * History : + */ +module hpdcache_1hot_to_binary + // Parameters + // {{{ +#( + parameter int unsigned N = 0, + localparam int unsigned Log2N = N > 1 ? $clog2(N) : 1, + localparam type in_t = logic unsigned [N-1:0], + localparam type out_t = logic unsigned [Log2N-1:0] +) + // }}} + + // Ports + // {{{ +( + input in_t val_i, + output out_t val_o +); + // }}} + + always_comb + begin : decode_comb + val_o = 0; + for (int unsigned i = 0; i < N; i++) begin + if (val_i[i]) val_o = out_t'(i); + end + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + // FIXME: The final keyword is not supported by the Spyglass linter + // assert final ($onehot0(val_i)) else $error("val_i shall be onehot or zero"); +`endif + // }}} + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv new file mode 100644 index 0000000000..ec6659b52b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv @@ -0,0 +1,184 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : November 22, 2022 + * Description : Refill data downsize + * History : + */ +module hpdcache_data_downsize +// {{{ +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter int WR_WIDTH = 0, + parameter int RD_WIDTH = 0, + parameter int DEPTH = 0, + + localparam type wdata_t = logic [WR_WIDTH-1:0], + localparam type rdata_t = logic [RD_WIDTH-1:0] +) +// }}} +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + input logic w_i, + output logic wok_o, + input wdata_t wdata_i, + + input logic r_i, + output logic rok_o, + output rdata_t rdata_o, + output logic rlast_o +); +// }}} +// Architecture +// {{{ + // Local definitions + // {{{ + localparam int RD_WORDS = WR_WIDTH/RD_WIDTH; + localparam int PTR_WIDTH = $clog2(DEPTH); + localparam int WORDCNT_WIDTH = $clog2(RD_WORDS); + typedef logic [PTR_WIDTH-1:0] bufptr_t; + typedef logic [WORDCNT_WIDTH-1:0] wordptr_t; + typedef logic [PTR_WIDTH:0] occupancy_t; + // }}} + + // Internal registers and signals + // {{{ + rdata_t [DEPTH-1:0][RD_WORDS-1:0] buf_q; + bufptr_t wrptr_q, wrptr_d; + bufptr_t rdptr_q, rdptr_d; + occupancy_t used_q, used_d; + wordptr_t [DEPTH-1:0] words_q, words_d; + logic words_set; + logic full, empty; + // }}} + + // Control-Path + // {{{ + assign full = (hpdcache_uint'(used_q) == DEPTH); + assign empty = (used_q == 0); + assign wok_o = ~full; + assign rok_o = ~empty; + + always_comb + begin : ctrl_comb + automatic logic used_inc, used_dec; + automatic logic words_dec; + + rdptr_d = rdptr_q; + wrptr_d = wrptr_q; + used_dec = 1'b0; + used_inc = 1'b0; + words_dec = 1'b0; + words_set = 1'b0; + + if (w_i && wok_o) begin + used_inc = 1'b1; + words_set = 1'b1; + if (hpdcache_uint'(wrptr_q) == (DEPTH-1)) begin + wrptr_d = 0; + end else begin + wrptr_d = wrptr_q + 1; + end + end + + if (r_i && rok_o) begin + words_dec = (words_q[rdptr_q] > 0); + if (words_q[rdptr_q] == 0) begin + used_dec = 1'b1; + if (hpdcache_uint'(rdptr_q) == (DEPTH-1)) begin + rdptr_d = 0; + end else begin + rdptr_d = rdptr_q + 1; + end + end + end + + case ({used_inc, used_dec}) + 2'b10 : used_d = used_q + 1; + 2'b01 : used_d = used_q - 1; + default: used_d = used_q; + endcase + + words_d = words_q; + if (words_set) begin + words_d[wrptr_q] = wordptr_t'(RD_WORDS - 1); + end + if (words_dec) begin + words_d[rdptr_q] = words_q[rdptr_q] - 1; + end + end + + assign rlast_o = rok_o & (words_q[rdptr_q] == 0); + + always_ff @(posedge clk_i or negedge rst_ni) + begin : ctrl_ff + if (!rst_ni) begin + rdptr_q <= 0; + wrptr_q <= 0; + used_q <= 0; + words_q <= 0; + end else begin + rdptr_q <= rdptr_d; + wrptr_q <= wrptr_d; + used_q <= used_d; + words_q <= words_d; + end + end + // }}} + + // Data-Path + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin : buf_ff + if (!rst_ni) begin + buf_q <= '0; + end else begin + if (words_set) begin + buf_q[wrptr_q] <= wdata_i; + end + end + end + + assign rdata_o = buf_q[rdptr_q][RD_WORDS - hpdcache_uint'(words_q[rdptr_q]) - 1]; + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + initial + begin : initial_assertions + assert (DEPTH > 0) else $error("DEPTH must be greater than 0"); + assert (WR_WIDTH > 0) else $error("WR_WIDTH must be greater than 0"); + assert (RD_WIDTH > 0) else $error("RD_WIDTH must be greater than 0"); + assert (RD_WIDTH < WR_WIDTH) else $error("RD_WIDTH must be less to WR_WIDTH"); + assert ((WR_WIDTH % RD_WIDTH) == 0) else $error("WR_WIDTH must be a multiple RD_WIDTH"); + end +`endif + // }}} +// }}} +endmodule +// }}} diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv new file mode 100644 index 0000000000..769a2d19f8 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv @@ -0,0 +1,129 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : September, 2024 + * Description : Data Resizer + * History : +m*/ +module hpdcache_data_resize +// {{{ +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter int WR_WIDTH = 0, + parameter int RD_WIDTH = 0, + parameter int DEPTH = 0, + + localparam type wdata_t = logic [WR_WIDTH-1:0], + localparam type rdata_t = logic [RD_WIDTH-1:0] +) +// }}} +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + input logic w_i, + output logic wok_o, + input wdata_t wdata_i, + input logic wlast_i, + + input logic r_i, + output logic rok_o, + output rdata_t rdata_o, + output logic rlast_o +); +// }}} + +// Upsizer +// {{{ +if (WR_WIDTH < RD_WIDTH) begin : gen_upsize + hpdcache_data_upsize #( + .WR_WIDTH (WR_WIDTH), + .RD_WIDTH (RD_WIDTH), + .DEPTH (DEPTH) + ) upsizer_i( + .clk_i, + .rst_ni, + + .w_i, + .wlast_i, + .wok_o, + .wdata_i, + + .r_i, + .rok_o, + .rdata_o + ); + + assign rlast_o = 1'b1; +end +// }}} +// Downsizer +// {{{ +else if (WR_WIDTH > RD_WIDTH) begin : gen_downsize + hpdcache_data_downsize #( + .WR_WIDTH (WR_WIDTH), + .RD_WIDTH (RD_WIDTH), + .DEPTH (DEPTH) + ) downsize_i( + .clk_i, + .rst_ni, + + .w_i, + .wok_o, + .wdata_i, + + .r_i, + .rok_o, + .rdata_o, + .rlast_o + ); +end +// }}} +// FIFO +// {{{ +else begin : gen_noresize + hpdcache_fifo_reg #( + .FIFO_DEPTH (DEPTH), + .FEEDTHROUGH (1'b0), + .fifo_data_t (wdata_t) + ) fifo_i( + .clk_i, + .rst_ni, + + .w_i, + .wok_o, + .wdata_i, + + .r_i, + .rok_o, + .rdata_o + ); + + assign rlast_o = 1'b1; +end +// }}} + +endmodule +// }}} diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv new file mode 100644 index 0000000000..357f03d286 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv @@ -0,0 +1,181 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : November 22, 2022 + * Description : Refill data upsize + * History : + */ +module hpdcache_data_upsize +// {{{ +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter int WR_WIDTH = 0, + parameter int RD_WIDTH = 0, + parameter int DEPTH = 0, + + localparam type wdata_t = logic [WR_WIDTH-1:0], + localparam type rdata_t = logic [RD_WIDTH-1:0] +) +// }}} +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + input logic w_i, + output logic wok_o, + input wdata_t wdata_i, + input logic wlast_i, + + input logic r_i, + output logic rok_o, + output rdata_t rdata_o +); +// }}} +// Architecture +// {{{ + // Local definitions + // {{{ + localparam int WR_WORDS = RD_WIDTH/WR_WIDTH; + localparam int PTR_WIDTH = $clog2(DEPTH); + localparam int WORDCNT_WIDTH = $clog2(WR_WORDS); + typedef logic [PTR_WIDTH-1:0] bufptr_t; + typedef logic [WORDCNT_WIDTH-1:0] wordptr_t; + typedef logic [PTR_WIDTH:0] occupancy_t; + // }}} + + // Internal registers and signals + // {{{ + wdata_t [DEPTH-1:0][WR_WORDS-1:0] buf_q; + bufptr_t wrptr_q, wrptr_d; + bufptr_t rdptr_q, rdptr_d; + occupancy_t used_q, used_d; + wordptr_t [DEPTH-1:0] words_q, words_d; + logic full, empty; + logic shift; + // }}} + + // Control-Path + // {{{ + assign full = (hpdcache_uint'(used_q) == DEPTH), + empty = (used_q == 0), + wok_o = ~full, + rok_o = ~empty; + + always_comb + begin : ctrl_comb + automatic logic used_inc, used_dec; + automatic logic words_inc, words_reset; + + wrptr_d = wrptr_q; + rdptr_d = rdptr_q; + words_d = words_q; + used_dec = 1'b0; + used_inc = 1'b0; + words_reset = 1'b0; + words_inc = 1'b0; + shift = 1'b0; + + if (w_i && wok_o) begin + shift = 1'b1; + words_inc = (hpdcache_uint'(words_q[wrptr_q]) < (WR_WORDS-1)); + if (hpdcache_uint'(words_q[wrptr_q]) == (WR_WORDS-1) || wlast_i) begin + used_inc = 1'b1; + if (hpdcache_uint'(wrptr_q) == (DEPTH-1)) begin + wrptr_d = 0; + end else begin + wrptr_d = wrptr_q + 1; + end + end + end + + if (r_i && rok_o) begin + used_dec = 1'b1; + words_reset = 1'b1; + if (hpdcache_uint'(rdptr_q) == (DEPTH-1)) begin + rdptr_d = 0; + end else begin + rdptr_d = rdptr_q + 1; + end + end + + case ({used_inc, used_dec}) + 2'b10 : used_d = used_q + 1; + 2'b01 : used_d = used_q - 1; + default: used_d = used_q; + endcase + + if (words_inc) words_d[wrptr_q] = words_q[wrptr_q] + 1; + if (words_reset) words_d[rdptr_q] = 0; + end + + + always_ff @(posedge clk_i or negedge rst_ni) + begin : ctrl_ff + if (!rst_ni) begin + rdptr_q <= 0; + wrptr_q <= 0; + used_q <= 0; + words_q <= '0; + end else begin + rdptr_q <= rdptr_d; + wrptr_q <= wrptr_d; + used_q <= used_d; + words_q <= words_d; + end + end + // }}} + + // Data-Path + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin : buf_ff + if (!rst_ni) begin + buf_q <= '0; + end else begin + if (shift) begin + buf_q[wrptr_q][words_q[wrptr_q]] <= wdata_i; + end + end + end + + assign rdata_o = buf_q[rdptr_q]; + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + initial + begin : initial_assertions + assert (DEPTH > 0) else $error("DEPTH must be greater than 0"); + assert (WR_WIDTH > 0) else $error("WR_WIDTH must be greater than 0"); + assert (RD_WIDTH > 0) else $error("RD_WIDTH must be greater than 0"); + assert (WR_WIDTH < RD_WIDTH) else $error("WR_WIDTH must be less to RD_WIDTH"); + assert ((RD_WIDTH % WR_WIDTH) == 0) else $error("RD_WIDTH must be a multiple WR_WIDTH"); + end +`endif + // }}} +// }}} +endmodule +// }}} diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv new file mode 100644 index 0000000000..0f7e7322a7 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv @@ -0,0 +1,53 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Decoder + * History : + */ +module hpdcache_decoder + // Parameters + // {{{ +#( + parameter int unsigned N = 0, + localparam int unsigned Pow2N = 2**N, + localparam type in_t = logic unsigned [N-1:0], + localparam type out_t = logic unsigned [Pow2N-1:0] +) + // }}} + + // Ports + // {{{ +( + input logic en_i, + input in_t val_i, + output out_t val_o +); + // }}} + + always_comb + begin : decoder_comb + val_o = 0; + for (int unsigned i = 0; i < Pow2N; i++) begin + if (val_i == in_t'(i)) val_o[i] = en_i; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv new file mode 100644 index 0000000000..3be21e0814 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv @@ -0,0 +1,69 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Simple multiplexor + * History : + */ +module hpdcache_demux +// Parameters +// {{{ +#( + // Number of outputs + parameter int unsigned NOUTPUT = 0, + + // Width in bits of each input + parameter int unsigned DATA_WIDTH = 0, + + // Selector signal is one-hot encoded + parameter bit ONE_HOT_SEL = 0, + + // Compute the width of the selection signal + localparam int unsigned NOUTPUT_LOG2 = $clog2(NOUTPUT), + localparam int unsigned SEL_WIDTH = ONE_HOT_SEL ? NOUTPUT : NOUTPUT_LOG2, + + localparam type data_t = logic [DATA_WIDTH-1:0], + localparam type sel_t = logic [SEL_WIDTH-1:0] +) +// }}} + +// Ports +// {{{ +( + input data_t data_i, + input sel_t sel_i, + output data_t [NOUTPUT-1:0] data_o +); +// }}} + + generate + always_comb + begin : demux_comb + for (int unsigned i = 0; i < NOUTPUT; i++) begin + if (!ONE_HOT_SEL) begin + data_o[i] = (sel_t'(i) == sel_i) ? data_i : '0; + end else begin + data_o[i] = sel_i[i] ? data_i : '0; + end + end + end + endgenerate +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv new file mode 100644 index 0000000000..fecd2b9d13 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv @@ -0,0 +1,176 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : FIFO buffer (using registers) + * History : + */ +module hpdcache_fifo_reg + // Parameters + // {{{ +#( + parameter int unsigned FIFO_DEPTH = 0, + parameter bit FEEDTHROUGH = 1'b0, + parameter type fifo_data_t = logic +) + // }}} + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + input logic w_i, + output logic wok_o, + input fifo_data_t wdata_i, + input logic r_i, + output logic rok_o, + output fifo_data_t rdata_o +); + // }}} + + // Declaration of constants, types and functions + // {{{ + localparam int __FIFO_DEPTH = FIFO_DEPTH > 1 ? FIFO_DEPTH : 2; + typedef logic unsigned [$clog2(__FIFO_DEPTH)-1:0] fifo_addr_t; + // }}} + + /* + * Bypass: no buffering + */ + if (FIFO_DEPTH == 0) begin : gen_bypass + assign wok_o = r_i; + assign rok_o = w_i; + assign rdata_o = wdata_i; + + /* + * Single-entry buffer -> synchronization buffer + */ + end else if (FIFO_DEPTH == 1) begin : gen_buffer + hpdcache_sync_buffer #( + .FEEDTHROUGH (FEEDTHROUGH), + .data_t (fifo_data_t) + ) i_sync_buffer ( + .clk_i, + .rst_ni, + .w_i, + .wok_o, + .wdata_i, + .r_i, + .rok_o, + .rdata_o + ); + + /* + * Multi-entry FIFO buffer + */ + end else if (FIFO_DEPTH > 1) begin : gen_fifo + // Declaration of internal wires and registers + // {{{ + fifo_data_t [FIFO_DEPTH-1:0] fifo_mem_q; + fifo_addr_t rptr_q, rptr_d; // read pointer + fifo_addr_t wptr_q, wptr_d; // write pointer + logic crossover_q, crossover_d; // write pointer has wrap + logic rexec, wexec; + logic rptr_max, wptr_max; + logic match_ptr; + logic empty, full; + // }}} + + // Global control signals + // {{{ + assign match_ptr = (wptr_q == rptr_q); + + assign empty = match_ptr & ~crossover_q, + full = match_ptr & crossover_q; + + assign rok_o = ~empty | (FEEDTHROUGH & w_i), + wok_o = ~full | (FEEDTHROUGH & r_i); + + assign rexec = r_i & ~empty, + wexec = w_i & (( FEEDTHROUGH & ((empty & ~r_i) | (full & r_i) | (~full & ~empty))) | + (~FEEDTHROUGH & ~full)); + + // }}} + + // Control of read and write pointers + // {{{ + assign rptr_max = (rptr_q == fifo_addr_t'(FIFO_DEPTH-1)); + assign wptr_max = (wptr_q == fifo_addr_t'(FIFO_DEPTH-1)); + + always_comb + begin : fifo_ctrl_comb + rptr_d = rptr_q; + wptr_d = wptr_q; + crossover_d = crossover_q; + + if (rexec) begin + rptr_d = rptr_max ? 0 : rptr_q + 1; + end + + if (wexec) begin + wptr_d = wptr_max ? 0 : wptr_q + 1; + end + + if (wexec && wptr_max) begin + crossover_d = 1'b1; + end else if (rexec && rptr_max) begin + crossover_d = 1'b0; + end + end + // }}} + + // FIFO buffer memory management + // {{{ + always_ff @(posedge clk_i) + begin + if (wexec) fifo_mem_q[wptr_q] <= wdata_i; + end + + assign rdata_o = FEEDTHROUGH && empty ? wdata_i : fifo_mem_q[rptr_q]; + // }}} + + // Setting of internal state + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + rptr_q <= 0; + wptr_q <= 0; + crossover_q <= 1'b0; + end else begin + rptr_q <= rptr_d; + wptr_q <= wptr_d; + crossover_q <= crossover_d; + end + end + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + rptr_ahead_wptr_assert: assert property (@(posedge clk_i) disable iff (!rst_ni) + ((rptr_q <= wptr_q) && !crossover_q) || + ((rptr_q >= wptr_q) && crossover_q)) else + $error("fifo: read pointer is ahead of the write pointer"); +`endif + // }}} + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv new file mode 100644 index 0000000000..1b8795444a --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv @@ -0,0 +1,85 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Fixed-Priority Arbiter + * History : + */ +module hpdcache_fxarb + // Parameters + // {{{ +#( + // Number of requesters + parameter int unsigned N = 0 +) + // }}} + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + input logic [N-1:0] req_i, + output logic [N-1:0] gnt_o, + input logic ready_i +); + // }}} + + // Declaration of internal wires and registers + // {{{ + logic [N-1:0] gnt_q, gnt; + logic wait_q; + // }}} + + // Compute the grant vector + // {{{ + hpdcache_prio_1hot_encoder #(.N(N)) prio_msk_i (.val_i(req_i), .val_o(gnt)); + // }}} + + // Compute the output grant vector + // {{{ + assign gnt_o = wait_q ? gnt_q : gnt; + // }}} + + // Setting of internal state + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + wait_q <= 1'b0; + gnt_q <= '0; + end else begin + wait_q <= ~ready_i & (wait_q | (|req_i)); + if (!ready_i && !wait_q && (|req_i)) begin + gnt_q <= gnt; + end + end + end + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + gnt_at_most_one_requester: assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot0(gnt_o)) else $error("arbiter: granting more than one requester"); +`endif + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv new file mode 100644 index 0000000000..48de5f3438 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv @@ -0,0 +1,95 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Author(s) : Cesar Fuguet + * Creation Date : Mars, 2024 + * Description : Galois Linear Feedback Shift Register + * History : + */ +module hpdcache_lfsr +// Parameters +// {{{ +#( + parameter int WIDTH = 8, + + localparam type data_t = logic [WIDTH-1:0] +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + input logic shift_i, + output data_t val_o +); +// }}} + +// Feedback Polynomial +// {{{ +logic [15:0] polynomial; + +assign polynomial = (WIDTH == 8) ? 16'h00E1 : + (WIDTH == 9) ? 16'h01EA : + (WIDTH == 10) ? 16'h02E3 : + (WIDTH == 11) ? 16'h04E3 : + (WIDTH == 12) ? 16'h0AE2 : + (WIDTH == 13) ? 16'h10E3 : + (WIDTH == 14) ? 16'h20EA : + (WIDTH == 15) ? 16'h41E2 : + (WIDTH == 16) ? 16'h81EE : 16'h0BAD; +// }}} + +// Linear Feedback Shift Register +// {{{ +data_t lfsr_q, lfsr_d; +data_t lfsr_shifted; + +assign lfsr_shifted = {1'b0, lfsr_q[WIDTH-1:1]}; + +always_comb +begin : lfsr_comb + if (lfsr_q[0]) lfsr_d = lfsr_shifted ^ polynomial[WIDTH-1:0]; + else lfsr_d = lfsr_shifted; +end + +assign val_o = lfsr_q; + +always_ff @(posedge clk_i or negedge rst_ni) +begin : lfsr_ff + if (!rst_ni) begin + lfsr_q <= '1; + end else begin + if (shift_i) lfsr_q <= lfsr_d; + end +end +// }}} + +// Assertions +// {{{ +`ifndef HPDCACHE_ASSERT_OFF +initial begin : assertions_initials + assert ((WIDTH >= 8) && (WIDTH <= 16)) else $fatal("illegal width"); +end +`endif +// }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv new file mode 100644 index 0000000000..969ef8fc96 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv @@ -0,0 +1,84 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Author(s) : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Simple multiplexor + * History : + */ +module hpdcache_mux + // Parameters + // {{{ +#( + // Number of inputs + parameter int unsigned NINPUT = 0, + + // Width in bits of each input + parameter int unsigned DATA_WIDTH = 0, + + // Selector signal is one-hot encoded + parameter bit ONE_HOT_SEL = 0, + + // Compute the width of the selection signal + localparam int unsigned NINPUT_LOG2 = $clog2(NINPUT), + localparam int unsigned SEL_WIDTH = ONE_HOT_SEL ? NINPUT : NINPUT_LOG2, + + localparam type data_t = logic [DATA_WIDTH-1:0], + localparam type sel_t = logic [SEL_WIDTH-1:0] +) + // }}} + + // Ports + // {{{ +( + input data_t [NINPUT-1:0] data_i, + input sel_t sel_i, + output data_t data_o +); + // }}} + + typedef int unsigned uint32; + + if (NINPUT == 1) begin : gen_single_input + assign data_o = data_i[0]; + + end else begin : gen_multi_input + // Selector is one-hot encoded + if (ONE_HOT_SEL == 1) begin : gen_onehot_sel + always_comb + begin : data_out_mux_comb + data_o = '0; + for (int unsigned i = 0; i < NINPUT; i++) begin + data_o |= sel_i[i] ? data_i[i] : '0; + end + end + + // Selector is binary encoded + end else begin : gen_binary_sel + always_comb + begin : data_out_mux_comb + data_o = '0; + for (int unsigned i = 0; i < NINPUT; i++) begin + data_o |= (i == uint32'(sel_i)) ? data_i[i] : '0; + end + end + end + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv new file mode 100644 index 0000000000..e9a107e288 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv @@ -0,0 +1,42 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Priority One-hot Encoder + * History : + */ +module hpdcache_prio_1hot_encoder + // Parameters +#( + parameter int unsigned N = 0 +) + // Ports +( + input logic [N-1:0] val_i, + output logic [N-1:0] val_o +); + + assign val_o[0] = val_i[0]; + + for (genvar i = 1; i < int'(N); i++) begin : gen_prio + assign val_o[i] = val_i[i] & ~(|val_i[i-1:0]); + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv new file mode 100644 index 0000000000..184e6fbf40 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv @@ -0,0 +1,63 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : 1RW register bank with write byte enable + * History : + */ +module hpdcache_regbank_wbyteenable_1rw +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE/8-1:0] wbyteenable, + output logic [DATA_SIZE-1:0] rdata +); + + /* + * Internal memory array declaration + */ + typedef logic [DATA_SIZE-1:0] mem_t [DEPTH]; + mem_t mem; + + /* + * Process to update or read the memory array + */ + always_ff @(posedge clk) + begin : mem_update_ff + if (cs == 1'b1) begin + if (we == 1'b1) begin + for (int i = 0; i < DATA_SIZE/8; i++) begin + if (wbyteenable[i]) mem[addr][i*8 +: 8] <= wdata[i*8 +: 8]; + end + end + rdata <= mem[addr]; + end + end : mem_update_ff +endmodule : hpdcache_regbank_wbyteenable_1rw diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv new file mode 100644 index 0000000000..e185bc4049 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv @@ -0,0 +1,61 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : 1RW register bank with write bit mask + * History : + */ +module hpdcache_regbank_wmask_1rw +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE-1:0] wmask, + output logic [DATA_SIZE-1:0] rdata +); + + /* + * Internal memory array declaration + */ + typedef logic [DATA_SIZE-1:0] mem_t [DEPTH]; + mem_t mem; + + /* + * Process to update or read the memory array + */ + always_ff @(posedge clk) + begin : mem_update_ff + if (cs == 1'b1) begin + if (we == 1'b1) begin + mem[addr] <= (mem[addr] & ~wmask) | (wdata & wmask); + end + rdata <= mem[addr]; + end + end : mem_update_ff +endmodule : hpdcache_regbank_wmask_1rw diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv new file mode 100644 index 0000000000..81a2ee854d --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv @@ -0,0 +1,122 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/** + * Author(s) : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Round-Robin Arbiter + * Based on design from + * http://www.rtlery.com/articles/how-design-round-robin-arbiter + * History : + */ +module hpdcache_rrarb + // Parameters + // {{{ +#( + // Number of requesters + parameter int unsigned N = 0 +) + // }}} + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + input logic [N-1:0] req_i, + output logic [N-1:0] gnt_o, + input logic ready_i +); + // }}} + + // Declaration of internal wires and registers + // {{{ + logic [N-1:0] gnt_q, gnt; + logic [N-1:0] nxt; + logic wait_q; + logic [N-1:0] mask, gnt_msk, gnt_nomsk; + logic pending; + genvar gen_i; + // }}} + + // Elaboration-time assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + initial + begin : initial_assertions + n_assertion : assert (N > 0) else $fatal("N must be greater than 0"); + end +`endif + // }}} + + // Compute the thermometer mask vector + // {{{ + generate + if (N > 1) begin : gen_nxt_gt_1 + assign nxt = {gnt_q[N-2:0], gnt_q[N-1]}; + end else begin : gen_nxt_1 + assign nxt = gnt_q[0]; + end + + for (gen_i = 0; gen_i < int'(N); gen_i++) begin : gen_mask + assign mask[gen_i] = |nxt[gen_i:0]; + end + endgenerate + // }}} + + // Compute the grant vector + // {{{ + hpdcache_prio_1hot_encoder #(.N(N)) prio_msk_i (.val_i(req_i & mask), .val_o(gnt_msk)); + hpdcache_prio_1hot_encoder #(.N(N)) prio_nomsk_i (.val_i(req_i) , .val_o(gnt_nomsk)); + assign gnt = |gnt_msk ? gnt_msk : gnt_nomsk; + // }}} + + // Compute the output grant vector + // {{{ + assign gnt_o = wait_q ? gnt_q : gnt; + // }}} + + // Setting of internal state + // {{{ + assign pending = |req_i; + + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + wait_q <= 1'b0; + gnt_q <= {1'b1, {N-1{1'b0}}}; + end else begin + wait_q <= ~ready_i & (wait_q | pending); + if (!wait_q && pending) begin + gnt_q <= gnt; + end + end + end + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + gnt_at_most_one_requester: assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot0(gnt)) else $error("arbiter: granting more than one requester"); + gnt_q_exactly_one_requester: assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot(gnt_q)) else $error("arbiter: grant state is not one-hot"); +`endif + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv new file mode 100644 index 0000000000..d078555ac4 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv @@ -0,0 +1,64 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Wrapper for Behavioral SRAM macros + * History : + */ +module hpdcache_sram +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + output logic [DATA_SIZE-1:0] rdata +); + + fakeram7_64x28 ram_i ( + .clk(clk), + .ce_in(cs), + .we_in(we), + .addr_in(addr), + .wd_in(wdata), + .rd_out(rdata) + ); + // hpdcache_sram_1rw #( + // .ADDR_SIZE(ADDR_SIZE), + // .DATA_SIZE(DATA_SIZE), + // .DEPTH(DEPTH) + // ) ram_i ( + // .clk, + // .rst_n, + // .cs, + // .we, + // .addr, + // .wdata, + // .rdata + // ); + +endmodule : hpdcache_sram diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv new file mode 100644 index 0000000000..d0cf76a389 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv @@ -0,0 +1,65 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Wrapper for 1RW SRAM macros implementing a write byte enable + * History : + */ +module hpdcache_sram_wbyteenable +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE/8-1:0] wbyteenable, + output logic [DATA_SIZE-1:0] rdata +); + fakeram7_128x64 ram_i ( + .clk (clk), + .ce_in(cs), + .we_in(we), + .addr_in(addr), + .wd_in(wdata), + .rd_out(rdata) + ); + // hpdcache_sram_wbyteenable_1rw #( + // .ADDR_SIZE(ADDR_SIZE), + // .DATA_SIZE(DATA_SIZE), + // .DEPTH(DEPTH) + // ) ram_i ( + // .clk, + // .rst_n, + // .cs, + // .we, + // .addr, + // .wdata, + // .wbyteenable, + // .rdata + // ); + +endmodule : hpdcache_sram_wbyteenable diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv new file mode 100644 index 0000000000..a4771e3bd5 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv @@ -0,0 +1,58 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Wrapper for 1RW SRAM macros implementing write bit mask + * History : + */ +module hpdcache_sram_wmask +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE-1:0] wmask, + output logic [DATA_SIZE-1:0] rdata +); + + hpdcache_sram_wmask_1rw #( + .ADDR_SIZE(ADDR_SIZE), + .DATA_SIZE(DATA_SIZE), + .DEPTH(DEPTH) + ) ram_i ( + .clk, + .rst_n, + .cs, + .we, + .addr, + .wdata, + .wmask, + .rdata + ); + +endmodule : hpdcache_sram_wmask diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv new file mode 100644 index 0000000000..863c5885ce --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv @@ -0,0 +1,89 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : October, 2023 + * Description : Synchronization buffer + * History : + */ +module hpdcache_sync_buffer + // Parameters + // {{{ +#( + parameter bit FEEDTHROUGH = 1'b0, + parameter type data_t = logic +) + // }}} + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + input logic w_i, + output logic wok_o, + input data_t wdata_i, + input logic r_i, + output logic rok_o, + output data_t rdata_o +); + // }}} + + // Declaration of internal wires and registers + // {{{ + data_t buf_q; + logic buf_we; + logic valid_q, valid_d; + // }}} + + // Global control signals + // {{{ + assign rok_o = valid_q | (FEEDTHROUGH & w_i), + wok_o = ~valid_q | (FEEDTHROUGH & r_i); + + assign buf_we = w_i & ((FEEDTHROUGH & ~(valid_q ^ r_i)) | (~FEEDTHROUGH & ~valid_q)); + // }}} + + // Control of buffer + // {{{ + assign valid_d = buf_we | (valid_q & ~r_i); + // }}} + + // FIFO buffer memory management + // {{{ + always_ff @(posedge clk_i) + begin + if (buf_we) buf_q <= wdata_i; + end + + assign rdata_o = FEEDTHROUGH && !valid_q ? wdata_i : buf_q; + // }}} + + // Setting of internal state + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + valid_q <= 1'b0; + end else begin + valid_q <= valid_d; + end + end + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv new file mode 100644 index 0000000000..c291005ddb --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv @@ -0,0 +1,42 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : SRAM blackbox model + * History : + */ +(* black_box *) module hpdcache_sram_1rw +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + output logic [DATA_SIZE-1:0] rdata +); + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv new file mode 100644 index 0000000000..0082e875c0 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv @@ -0,0 +1,43 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Blackbox model of a 1RW SRAM with write byte enable + * History : + */ +(* black_box *) module hpdcache_sram_wbyteenable_1rw +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE/8-1:0] wbyteenable, + output logic [DATA_SIZE-1:0] rdata +); + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv new file mode 100644 index 0000000000..aa8ec31187 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv @@ -0,0 +1,43 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Blackbox model of a 1RW SRAM with write bit mask + * History : + */ +(* black_box *) module hpdcache_sram_wmask_1rw +#( + parameter int unsigned ADDR_SIZE = 0, + parameter int unsigned DATA_SIZE = 0, + parameter int unsigned DEPTH = 2**ADDR_SIZE +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [DATA_SIZE-1:0] wdata, + input logic [DATA_SIZE-1:0] wmask, + output logic [DATA_SIZE-1:0] rdata +); + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv new file mode 100644 index 0000000000..68d56dfde3 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv @@ -0,0 +1,1291 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache top + * History : + */ +`include "hpdcache_typedef.svh" + +module hpdcache +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type wbuf_timecnt_t = logic, + + // Request Interface Definitions + // {{{ + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_data_be_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + // }}} + + // Memory Interface Definitions + // {{{ + parameter type hpdcache_mem_addr_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_data_t = logic, + parameter type hpdcache_mem_be_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic + // }}} +) + // }}} + + // Ports + // {{{ +( + // Clock and reset signals + input logic clk_i, + input logic rst_ni, + + // Force the write buffer to send all pending writes + input logic wbuf_flush_i, + + // Core request interface + // 1st cycle + input logic core_req_valid_i [HPDcacheCfg.u.nRequesters], + output logic core_req_ready_o [HPDcacheCfg.u.nRequesters], + input hpdcache_req_t core_req_i [HPDcacheCfg.u.nRequesters], + // 2nd cycle + input logic core_req_abort_i [HPDcacheCfg.u.nRequesters], + input hpdcache_tag_t core_req_tag_i [HPDcacheCfg.u.nRequesters], + input hpdcache_pma_t core_req_pma_i [HPDcacheCfg.u.nRequesters], + + // Core response interface + output logic core_rsp_valid_o [HPDcacheCfg.u.nRequesters], + output hpdcache_rsp_t core_rsp_o [HPDcacheCfg.u.nRequesters], + + // Read / Invalidation memory interface + input logic mem_req_read_ready_i, + output logic mem_req_read_valid_o, + output hpdcache_mem_req_t mem_req_read_o, + + output logic mem_resp_read_ready_o, + input logic mem_resp_read_valid_i, + input hpdcache_mem_resp_r_t mem_resp_read_i, +`ifdef HPDCACHE_OPENPITON + input logic mem_resp_read_inval_i, + input hpdcache_nline_t mem_resp_read_inval_nline_i, +`endif + + // Write memory interface + input logic mem_req_write_ready_i, + output logic mem_req_write_valid_o, + output hpdcache_mem_req_t mem_req_write_o, + + input logic mem_req_write_data_ready_i, + output logic mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t mem_req_write_data_o, + + output logic mem_resp_write_ready_o, + input logic mem_resp_write_valid_i, + input hpdcache_mem_resp_w_t mem_resp_write_i, + + // Performance events + output logic evt_cache_write_miss_o, + output logic evt_cache_read_miss_o, + output logic evt_uncached_req_o, + output logic evt_cmo_req_o, + output logic evt_write_req_o, + output logic evt_read_req_o, + output logic evt_prefetch_req_o, + output logic evt_req_on_hold_o, + output logic evt_rtab_rollback_o, + output logic evt_stall_refill_o, + output logic evt_stall_o, + + // Status interface + output logic wbuf_empty_o, + + // Configuration interface + input logic cfg_enable_i, + input wbuf_timecnt_t cfg_wbuf_threshold_i, + input logic cfg_wbuf_reset_timecnt_on_write_i, + input logic cfg_wbuf_sequential_waw_i, + input logic cfg_wbuf_inhibit_write_coalescing_i, + input logic cfg_prefetch_updt_plru_i, + input logic cfg_error_on_cacheable_amo_i, + input logic cfg_rtab_single_entry_i, + input logic cfg_default_wb_i +); + // }}} + + // Declaration of internal types + // {{{ + typedef logic [HPDcacheCfg.u.paWidth-1:0] hpdcache_req_addr_t; + typedef logic [HPDcacheCfg.nlineWidth-1:0] hpdcache_nline_t; + typedef logic [HPDcacheCfg.setWidth-1:0] hpdcache_set_t; + typedef logic [HPDcacheCfg.clOffsetWidth-1:0] hpdcache_offset_t; + typedef logic unsigned [HPDcacheCfg.clWordIdxWidth-1:0] hpdcache_word_t; + typedef logic unsigned [HPDcacheCfg.u.ways-1:0] hpdcache_way_vector_t; + typedef logic unsigned [HPDcacheCfg.wayIndexWidth-1:0] hpdcache_way_t; + + // Cache Directory entry definition + // {{{ + typedef struct packed { + // Cacheline state + // Encoding: {valid, wb, dirty, fetch} + // {0,X,X,0}: Invalid + // {0,X,X,1}: Invalid and Fetching + // {1,X,X,1}: Valid and Fetching (cacheline being replaced is accessible) + // {1,0,0,0}: Write-through + // {1,1,0,0}: Write-back (clean) + // {1,1,1,0}: Write-back (dirty) + // {{{ + logic valid; // valid cacheline + logic wback; // cacheline in write-back mode + logic dirty; // cacheline is locally modified (memory is obsolete) + logic fetch; // cacheline is reserved for a new cacheline being fetched + // }}} + + // Cacheline address tag + // {{{ + hpdcache_tag_t tag; + // }}} + } hpdcache_dir_entry_t; + // }}} + + typedef hpdcache_data_word_t [HPDcacheCfg.u.accessWords-1:0] hpdcache_access_data_t; + typedef hpdcache_data_be_t [HPDcacheCfg.u.accessWords-1:0] hpdcache_access_be_t; + + typedef hpdcache_req_addr_t wbuf_addr_t; + typedef hpdcache_req_data_t wbuf_data_t; + typedef hpdcache_req_be_t wbuf_be_t; + // }}} + + // Declaration of internal signals + // {{{ + logic refill_req_valid; + logic refill_req_ready; + logic refill_is_error; + logic refill_busy; + logic refill_updt_sel_victim; + hpdcache_set_t refill_set; + hpdcache_way_vector_t refill_way; + hpdcache_dir_entry_t refill_dir_entry; + logic refill_write_dir; + logic refill_write_data; + hpdcache_word_t refill_word; + hpdcache_access_data_t refill_data; + logic refill_core_rsp_valid; + hpdcache_rsp_t refill_core_rsp; + hpdcache_nline_t refill_nline; + logic refill_updt_rtab; + + logic inval_check_dir; + logic inval_write_dir; + hpdcache_nline_t inval_nline; + logic inval_hit; + + logic miss_mshr_empty; + logic miss_mshr_check; + hpdcache_req_offset_t miss_mshr_check_offset; + hpdcache_nline_t miss_mshr_check_nline; + logic miss_mshr_hit; + logic miss_mshr_alloc_cs; + logic miss_mshr_alloc; + logic miss_mshr_alloc_ready; + logic miss_mshr_alloc_full; + hpdcache_nline_t miss_mshr_alloc_nline; + hpdcache_req_tid_t miss_mshr_alloc_tid; + hpdcache_req_sid_t miss_mshr_alloc_sid; + hpdcache_word_t miss_mshr_alloc_word; + hpdcache_way_vector_t miss_mshr_alloc_victim_way; + logic miss_mshr_alloc_need_rsp; + logic miss_mshr_alloc_is_prefetch; + logic miss_mshr_alloc_wback; + + logic wbuf_flush_all; + logic wbuf_write; + logic wbuf_write_ready; + wbuf_addr_t wbuf_write_addr; + wbuf_data_t wbuf_write_data; + wbuf_be_t wbuf_write_be; + logic wbuf_write_uncacheable; + logic wbuf_read_hit; + logic wbuf_read_flush_hit; + hpdcache_req_addr_t wbuf_rtab_addr; + logic wbuf_rtab_is_read; + logic wbuf_rtab_hit_open; + logic wbuf_rtab_hit_pend; + logic wbuf_rtab_hit_sent; + logic wbuf_rtab_not_ready; + + logic uc_ready; + logic uc_req_valid; + hpdcache_uc_op_t uc_req_op; + hpdcache_req_addr_t uc_req_addr; + hpdcache_req_size_t uc_req_size; + hpdcache_req_data_t uc_req_data; + hpdcache_req_be_t uc_req_be; + logic uc_req_uncacheable; + hpdcache_req_sid_t uc_req_sid; + hpdcache_req_tid_t uc_req_tid; + logic uc_req_need_rsp; + logic uc_wbuf_flush_all; + logic uc_dir_amo_match; + hpdcache_set_t uc_dir_amo_match_set; + hpdcache_tag_t uc_dir_amo_match_tag; + logic uc_dir_amo_updt_sel_victim; + hpdcache_way_vector_t uc_dir_amo_hit_way; + logic uc_data_amo_write; + logic uc_data_amo_write_enable; + hpdcache_set_t uc_data_amo_write_set; + hpdcache_req_size_t uc_data_amo_write_size; + hpdcache_word_t uc_data_amo_write_word; + hpdcache_req_data_t uc_data_amo_write_data; + hpdcache_req_be_t uc_data_amo_write_be; + logic uc_lrsc_snoop; + hpdcache_req_addr_t uc_lrsc_snoop_addr; + hpdcache_req_size_t uc_lrsc_snoop_size; + logic uc_core_rsp_ready; + logic uc_core_rsp_valid; + hpdcache_rsp_t uc_core_rsp; + + logic cmo_req_valid; + logic cmo_ready; + hpdcache_cmoh_op_t cmo_req_op; + hpdcache_req_addr_t cmo_req_addr; + hpdcache_req_sid_t cmo_req_sid; + hpdcache_req_tid_t cmo_req_tid; + hpdcache_req_data_t cmo_req_wdata; + logic cmo_req_need_rsp; + logic cmo_wbuf_flush_all; + logic cmo_dir_check_nline; + hpdcache_set_t cmo_dir_check_nline_set; + hpdcache_tag_t cmo_dir_check_nline_tag; + hpdcache_way_vector_t cmo_dir_check_nline_hit_way; + logic cmo_dir_check_nline_wback; + logic cmo_dir_check_nline_dirty; + logic cmo_dir_check_entry; + hpdcache_set_t cmo_dir_check_entry_set; + hpdcache_way_vector_t cmo_dir_check_entry_way; + logic cmo_dir_check_entry_valid; + logic cmo_dir_check_entry_wback; + logic cmo_dir_check_entry_dirty; + hpdcache_tag_t cmo_dir_check_entry_tag; + logic cmo_dir_updt; + hpdcache_set_t cmo_dir_updt_set; + hpdcache_way_vector_t cmo_dir_updt_way; + logic cmo_dir_updt_valid; + logic cmo_dir_updt_wback; + logic cmo_dir_updt_dirty; + logic cmo_dir_updt_fetch; + hpdcache_tag_t cmo_dir_updt_tag; + logic cmo_wait; + logic cmo_flush_alloc; + hpdcache_nline_t cmo_flush_alloc_nline; + hpdcache_way_vector_t cmo_flush_alloc_way; + logic cmo_core_rsp_ready; + logic cmo_core_rsp_valid; + hpdcache_rsp_t cmo_core_rsp; + + logic flush_empty; + logic flush_busy; + hpdcache_nline_t flush_check_nline; + logic flush_check_hit; + logic flush_alloc; + logic flush_alloc_ready; + hpdcache_nline_t flush_alloc_nline; + hpdcache_way_vector_t flush_alloc_way; + logic flush_data_read; + hpdcache_set_t flush_data_read_set; + hpdcache_word_t flush_data_read_word; + hpdcache_way_vector_t flush_data_read_way; + hpdcache_access_data_t flush_data_read_data; + logic flush_ack; + hpdcache_nline_t flush_ack_nline; + + logic ctrl_flush_alloc; + hpdcache_nline_t ctrl_flush_alloc_nline; + hpdcache_way_vector_t ctrl_flush_alloc_way; + + logic rtab_empty; + logic ctrl_empty; + + logic core_rsp_valid; + hpdcache_rsp_t core_rsp; + + logic arb_req_valid; + logic arb_req_ready; + hpdcache_req_t arb_req; + logic arb_abort; + hpdcache_tag_t arb_tag; + hpdcache_pma_t arb_pma; + + logic mem_req_read_miss_ready; + logic mem_req_read_miss_valid; + hpdcache_mem_req_t mem_req_read_miss; + + logic mem_resp_read_miss_ready; + logic mem_resp_read_miss_valid; + hpdcache_mem_resp_r_t mem_resp_read_miss; + logic mem_resp_read_miss_inval; + hpdcache_nline_t mem_resp_read_miss_inval_nline; + + logic mem_req_read_uc_ready; + logic mem_req_read_uc_valid; + hpdcache_mem_req_t mem_req_read_uc; + + logic mem_resp_read_uc_ready; + logic mem_resp_read_uc_valid; + hpdcache_mem_resp_r_t mem_resp_read_uc; + + logic mem_req_write_wbuf_ready; + logic mem_req_write_wbuf_valid; + hpdcache_mem_req_t mem_req_write_wbuf; + + logic mem_req_write_wbuf_data_ready; + logic mem_req_write_wbuf_data_valid; + hpdcache_mem_req_w_t mem_req_write_wbuf_data; + + logic mem_resp_write_wbuf_ready; + logic mem_resp_write_wbuf_valid; + hpdcache_mem_resp_w_t mem_resp_write_wbuf; + + logic mem_req_write_flush_ready; + logic mem_req_write_flush_valid; + hpdcache_mem_req_t mem_req_write_flush; + + logic mem_req_write_flush_data_ready; + logic mem_req_write_flush_data_valid; + hpdcache_mem_req_w_t mem_req_write_flush_data; + + logic mem_resp_write_flush_ready; + logic mem_resp_write_flush_valid; + hpdcache_mem_resp_w_t mem_resp_write_flush; + + logic mem_req_write_uc_ready; + logic mem_req_write_uc_valid; + hpdcache_mem_req_t mem_req_write_uc; + + logic mem_req_write_uc_data_ready; + logic mem_req_write_uc_data_valid; + hpdcache_mem_req_w_t mem_req_write_uc_data; + + logic mem_resp_write_uc_ready; + logic mem_resp_write_uc_valid; + hpdcache_mem_resp_w_t mem_resp_write_uc; + + logic cfg_default_wb; + + localparam logic [HPDcacheCfg.u.memIdWidth-1:0] HPDCACHE_UC_READ_ID = + {HPDcacheCfg.u.memIdWidth{1'b1}}; + localparam logic [HPDcacheCfg.u.memIdWidth-1:0] HPDCACHE_UC_WRITE_ID = + {HPDcacheCfg.u.memIdWidth{1'b1}}; + // }}} + + // Requesters arbiter + // {{{ + hpdcache_core_arbiter #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t) + ) core_req_arbiter_i ( + .clk_i, + .rst_ni, + + .core_req_valid_i, + .core_req_ready_o, + .core_req_i, + .core_req_abort_i, + .core_req_tag_i, + .core_req_pma_i, + + .core_rsp_valid_i (core_rsp_valid), + .core_rsp_i (core_rsp), + .core_rsp_valid_o, + .core_rsp_o, + + .arb_req_valid_o (arb_req_valid), + .arb_req_ready_i (arb_req_ready), + .arb_req_o (arb_req), + .arb_abort_o (arb_abort), + .arb_tag_o (arb_tag), + .arb_pma_o (arb_pma) + ); + // }}} + + // HPDcache controller + // {{{ + if (HPDcacheCfg.u.wtEn && HPDcacheCfg.u.wbEn) begin : gen_cfg_default_wt_wb + assign cfg_default_wb = cfg_default_wb_i; + end else if (HPDcacheCfg.u.wtEn) begin : gen_cfg_default_wt + assign cfg_default_wb = 1'b0; + end else if (HPDcacheCfg.u.wbEn) begin : gen_cfg_default_wb + assign cfg_default_wb = 1'b1; + end + + hpdcache_ctrl #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_data_be_t (hpdcache_data_be_t), + .hpdcache_dir_entry_t (hpdcache_dir_entry_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + .hpdcache_way_t (hpdcache_way_t), + .wbuf_addr_t (wbuf_addr_t), + .wbuf_data_t (wbuf_data_t), + .wbuf_be_t (wbuf_be_t), + .hpdcache_access_data_t (hpdcache_access_data_t), + .hpdcache_access_be_t (hpdcache_access_be_t), + .hpdcache_req_addr_t (hpdcache_req_addr_t), + .hpdcache_req_offset_t (hpdcache_req_offset_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t) + ) hpdcache_ctrl_i( + .clk_i, + .rst_ni, + + .core_req_valid_i (arb_req_valid), + .core_req_ready_o (arb_req_ready), + .core_req_i (arb_req), + .core_req_abort_i (arb_abort), + .core_req_tag_i (arb_tag), + .core_req_pma_i (arb_pma), + + .core_rsp_valid_o (core_rsp_valid), + .core_rsp_o (core_rsp), + + .wbuf_flush_i, + + .cachedir_hit_o (/* unused */), + + .st0_mshr_check_o (miss_mshr_check), + .st0_mshr_check_offset_o (miss_mshr_check_offset), + .st1_mshr_check_nline_o (miss_mshr_check_nline), + .st1_mshr_hit_i (miss_mshr_hit), + .st1_mshr_alloc_ready_i (miss_mshr_alloc_ready), + .st1_mshr_alloc_full_i (miss_mshr_alloc_full), + .st2_mshr_alloc_o (miss_mshr_alloc), + .st2_mshr_alloc_cs_o (miss_mshr_alloc_cs), + .st2_mshr_alloc_nline_o (miss_mshr_alloc_nline), + .st2_mshr_alloc_tid_o (miss_mshr_alloc_tid), + .st2_mshr_alloc_sid_o (miss_mshr_alloc_sid), + .st2_mshr_alloc_word_o (miss_mshr_alloc_word), + .st2_mshr_alloc_victim_way_o (miss_mshr_alloc_victim_way), + .st2_mshr_alloc_need_rsp_o (miss_mshr_alloc_need_rsp), + .st2_mshr_alloc_is_prefetch_o (miss_mshr_alloc_is_prefetch), + .st2_mshr_alloc_wback_o (miss_mshr_alloc_wback), + + .refill_req_valid_i (refill_req_valid), + .refill_req_ready_o (refill_req_ready), + .refill_is_error_i (refill_is_error), + .refill_busy_i (refill_busy), + .refill_updt_sel_victim_i (refill_updt_sel_victim), + .refill_set_i (refill_set), + .refill_way_i (refill_way), + .refill_dir_entry_i (refill_dir_entry), + .refill_write_dir_i (refill_write_dir), + .refill_write_data_i (refill_write_data), + .refill_word_i (refill_word), + .refill_data_i (refill_data), + .refill_core_rsp_valid_i (refill_core_rsp_valid), + .refill_core_rsp_i (refill_core_rsp), + .refill_nline_i (refill_nline), + .refill_updt_rtab_i (refill_updt_rtab), + + .flush_busy_i (flush_busy), + .flush_check_nline_o (flush_check_nline), + .flush_check_hit_i (flush_check_hit), + .flush_alloc_o (ctrl_flush_alloc), + .flush_alloc_ready_i (flush_alloc_ready), + .flush_alloc_nline_o (ctrl_flush_alloc_nline), + .flush_alloc_way_o (ctrl_flush_alloc_way), + .flush_data_read_i (flush_data_read), + .flush_data_read_set_i (flush_data_read_set), + .flush_data_read_word_i (flush_data_read_word), + .flush_data_read_way_i (flush_data_read_way), + .flush_data_read_data_o (flush_data_read_data), + .flush_ack_i (flush_ack), + .flush_ack_nline_i (flush_ack_nline), + + .inval_check_dir_i (inval_check_dir), + .inval_write_dir_i (inval_write_dir), + .inval_nline_i (inval_nline), + .inval_hit_o (inval_hit), + + .wbuf_empty_i (wbuf_empty_o), + .wbuf_flush_all_o (wbuf_flush_all), + .wbuf_write_o (wbuf_write), + .wbuf_write_ready_i (wbuf_write_ready), + .wbuf_write_addr_o (wbuf_write_addr), + .wbuf_write_data_o (wbuf_write_data), + .wbuf_write_be_o (wbuf_write_be), + .wbuf_write_uncacheable_o (wbuf_write_uncacheable), + .wbuf_read_hit_i (wbuf_read_hit), + .wbuf_read_flush_hit_o (wbuf_read_flush_hit), + .wbuf_rtab_addr_o (wbuf_rtab_addr), + .wbuf_rtab_is_read_o (wbuf_rtab_is_read), + .wbuf_rtab_hit_open_i (wbuf_rtab_hit_open), + .wbuf_rtab_hit_pend_i (wbuf_rtab_hit_pend), + .wbuf_rtab_hit_sent_i (wbuf_rtab_hit_sent), + .wbuf_rtab_not_ready_i (wbuf_rtab_not_ready), + + .uc_busy_i (~uc_ready), + .uc_lrsc_snoop_o (uc_lrsc_snoop), + .uc_lrsc_snoop_addr_o (uc_lrsc_snoop_addr), + .uc_lrsc_snoop_size_o (uc_lrsc_snoop_size), + .uc_req_valid_o (uc_req_valid), + .uc_req_op_o (uc_req_op), + .uc_req_addr_o (uc_req_addr), + .uc_req_size_o (uc_req_size), + .uc_req_data_o (uc_req_data), + .uc_req_be_o (uc_req_be), + .uc_req_uc_o (uc_req_uncacheable), + .uc_req_sid_o (uc_req_sid), + .uc_req_tid_o (uc_req_tid), + .uc_req_need_rsp_o (uc_req_need_rsp), + .uc_wbuf_flush_all_i (uc_wbuf_flush_all), + .uc_dir_amo_match_i (uc_dir_amo_match), + .uc_dir_amo_match_set_i (uc_dir_amo_match_set), + .uc_dir_amo_match_tag_i (uc_dir_amo_match_tag), + .uc_dir_amo_updt_sel_victim_i (uc_dir_amo_updt_sel_victim), + .uc_dir_amo_hit_way_o (uc_dir_amo_hit_way), + .uc_data_amo_write_i (uc_data_amo_write), + .uc_data_amo_write_enable_i (uc_data_amo_write_enable), + .uc_data_amo_write_set_i (uc_data_amo_write_set), + .uc_data_amo_write_size_i (uc_data_amo_write_size), + .uc_data_amo_write_word_i (uc_data_amo_write_word), + .uc_data_amo_write_data_i (uc_data_amo_write_data), + .uc_data_amo_write_be_i (uc_data_amo_write_be), + .uc_core_rsp_ready_o (uc_core_rsp_ready), + .uc_core_rsp_valid_i (uc_core_rsp_valid), + .uc_core_rsp_i (uc_core_rsp), + + .cmo_busy_i (~cmo_ready), + .cmo_wait_i (cmo_wait), + .cmo_req_valid_o (cmo_req_valid), + .cmo_req_op_o (cmo_req_op), + .cmo_req_addr_o (cmo_req_addr), + .cmo_req_wdata_o (cmo_req_wdata), + .cmo_req_sid_o (cmo_req_sid), + .cmo_req_tid_o (cmo_req_tid), + .cmo_req_need_rsp_o (cmo_req_need_rsp), + .cmo_wbuf_flush_all_i (cmo_wbuf_flush_all), + .cmo_dir_check_nline_i (cmo_dir_check_nline), + .cmo_dir_check_nline_set_i (cmo_dir_check_nline_set), + .cmo_dir_check_nline_tag_i (cmo_dir_check_nline_tag), + .cmo_dir_check_nline_hit_way_o (cmo_dir_check_nline_hit_way), + .cmo_dir_check_nline_wback_o (cmo_dir_check_nline_wback), + .cmo_dir_check_nline_dirty_o (cmo_dir_check_nline_dirty), + .cmo_dir_check_entry_i (cmo_dir_check_entry), + .cmo_dir_check_entry_set_i (cmo_dir_check_entry_set), + .cmo_dir_check_entry_way_i (cmo_dir_check_entry_way), + .cmo_dir_check_entry_valid_o (cmo_dir_check_entry_valid), + .cmo_dir_check_entry_wback_o (cmo_dir_check_entry_wback), + .cmo_dir_check_entry_dirty_o (cmo_dir_check_entry_dirty), + .cmo_dir_check_entry_tag_o (cmo_dir_check_entry_tag), + .cmo_dir_updt_i (cmo_dir_updt), + .cmo_dir_updt_set_i (cmo_dir_updt_set), + .cmo_dir_updt_way_i (cmo_dir_updt_way), + .cmo_dir_updt_valid_i (cmo_dir_updt_valid), + .cmo_dir_updt_wback_i (cmo_dir_updt_wback), + .cmo_dir_updt_dirty_i (cmo_dir_updt_dirty), + .cmo_dir_updt_fetch_i (cmo_dir_updt_fetch), + .cmo_dir_updt_tag_i (cmo_dir_updt_tag), + .cmo_core_rsp_ready_o (cmo_core_rsp_ready), + .cmo_core_rsp_valid_i (cmo_core_rsp_valid), + .cmo_core_rsp_i (cmo_core_rsp), + + .rtab_empty_o (rtab_empty), + .ctrl_empty_o (ctrl_empty), + + .cfg_enable_i, + .cfg_prefetch_updt_plru_i, + .cfg_rtab_single_entry_i, + .cfg_default_wb_i (cfg_default_wb), + + .evt_cache_write_miss_o, + .evt_cache_read_miss_o, + .evt_uncached_req_o, + .evt_cmo_req_o, + .evt_write_req_o, + .evt_read_req_o, + .evt_prefetch_req_o, + .evt_req_on_hold_o, + .evt_rtab_rollback_o, + .evt_stall_refill_o, + .evt_stall_o + ); + // }}} + + // HPDcache write-buffer + // {{{ + if (HPDcacheCfg.u.wtEn) begin : gen_wbuf + hpdcache_wbuf #( + .HPDcacheCfg (HPDcacheCfg), + .wbuf_addr_t (wbuf_addr_t), + .wbuf_timecnt_t (wbuf_timecnt_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t) + ) hpdcache_wbuf_i( + .clk_i, + .rst_ni, + + .empty_o (wbuf_empty_o), + .full_o (/* unused */), + .flush_all_i (wbuf_flush_all), + + .cfg_threshold_i (cfg_wbuf_threshold_i), + .cfg_reset_timecnt_on_write_i (cfg_wbuf_reset_timecnt_on_write_i), + .cfg_sequential_waw_i (cfg_wbuf_sequential_waw_i), + .cfg_inhibit_write_coalescing_i (cfg_wbuf_inhibit_write_coalescing_i), + + .write_i (wbuf_write), + .write_ready_o (wbuf_write_ready), + .write_addr_i (wbuf_write_addr), + .write_data_i (wbuf_write_data), + .write_be_i (wbuf_write_be), + .write_uc_i (wbuf_write_uncacheable), + + .read_addr_i (wbuf_write_addr), + .read_hit_o (wbuf_read_hit), + .read_flush_hit_i (wbuf_read_flush_hit), + + .replay_addr_i (wbuf_rtab_addr), + .replay_is_read_i (wbuf_rtab_is_read), + .replay_open_hit_o (wbuf_rtab_hit_open), + .replay_pend_hit_o (wbuf_rtab_hit_pend), + .replay_sent_hit_o (wbuf_rtab_hit_sent), + .replay_not_ready_o (wbuf_rtab_not_ready), + + .mem_req_write_ready_i (mem_req_write_wbuf_ready), + .mem_req_write_valid_o (mem_req_write_wbuf_valid), + .mem_req_write_o (mem_req_write_wbuf), + + .mem_req_write_data_ready_i (mem_req_write_wbuf_data_ready), + .mem_req_write_data_valid_o (mem_req_write_wbuf_data_valid), + .mem_req_write_data_o (mem_req_write_wbuf_data), + + .mem_resp_write_ready_o (mem_resp_write_wbuf_ready), + .mem_resp_write_valid_i (mem_resp_write_wbuf_valid), + .mem_resp_write_i (mem_resp_write_wbuf) + ); + end else begin : gen_no_wbuf + // The write-buffer behaves as a black-hole: consumes but do not produce data + assign wbuf_empty_o = 1'b1; + assign wbuf_write_ready = 1'b1; + assign wbuf_read_hit = 1'b0; + assign wbuf_rtab_hit_open = 1'b0; + assign wbuf_rtab_hit_pend = 1'b0; + assign wbuf_rtab_hit_sent = 1'b0; + assign wbuf_rtab_not_ready = 1'b0; + assign mem_req_write_wbuf_valid = 1'b0; + assign mem_req_write_wbuf = '{ + mem_req_command: HPDCACHE_MEM_READ, + mem_req_atomic : HPDCACHE_MEM_ATOMIC_ADD, + default : '0 + }; + assign mem_req_write_wbuf_data_valid = 1'b0; + assign mem_req_write_wbuf_data = '0; + assign mem_resp_write_wbuf_ready = 1'b1; + end + // }}} + + // Miss handler + // {{{ + hpdcache_miss_handler #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + .hpdcache_way_t (hpdcache_way_t), + .hpdcache_dir_entry_t (hpdcache_dir_entry_t), + .hpdcache_refill_data_t (hpdcache_access_data_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_offset_t (hpdcache_req_offset_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_resp_r_t (hpdcache_mem_resp_r_t) + ) hpdcache_miss_handler_i( + .clk_i, + .rst_ni, + + .mshr_empty_o (miss_mshr_empty), + .mshr_full_o (/* unused */), + + .cfg_prefetch_updt_sel_victim_i (cfg_prefetch_updt_plru_i), + + .mshr_check_i (miss_mshr_check), + .mshr_check_offset_i (miss_mshr_check_offset), + .mshr_check_nline_i (miss_mshr_check_nline), + .mshr_check_hit_o (miss_mshr_hit), + + .mshr_alloc_ready_o (miss_mshr_alloc_ready), + .mshr_alloc_i (miss_mshr_alloc), + .mshr_alloc_cs_i (miss_mshr_alloc_cs), + .mshr_alloc_nline_i (miss_mshr_alloc_nline), + .mshr_alloc_full_o (miss_mshr_alloc_full), + .mshr_alloc_tid_i (miss_mshr_alloc_tid), + .mshr_alloc_sid_i (miss_mshr_alloc_sid), + .mshr_alloc_word_i (miss_mshr_alloc_word), + .mshr_alloc_victim_way_i (miss_mshr_alloc_victim_way), + .mshr_alloc_need_rsp_i (miss_mshr_alloc_need_rsp), + .mshr_alloc_is_prefetch_i (miss_mshr_alloc_is_prefetch), + .mshr_alloc_wback_i (miss_mshr_alloc_wback), + + .refill_req_ready_i (refill_req_ready), + .refill_req_valid_o (refill_req_valid), + .refill_is_error_o (refill_is_error), + .refill_busy_o (refill_busy), + .refill_updt_sel_victim_o (refill_updt_sel_victim), + .refill_set_o (refill_set), + .refill_way_o (refill_way), + .refill_dir_entry_o (refill_dir_entry), + .refill_write_dir_o (refill_write_dir), + .refill_write_data_o (refill_write_data), + .refill_data_o (refill_data), + .refill_word_o (refill_word), + .refill_nline_o (refill_nline), + .refill_updt_rtab_o (refill_updt_rtab), + + .inval_check_dir_o (inval_check_dir), + .inval_write_dir_o (inval_write_dir), + .inval_nline_o (inval_nline), + .inval_hit_i (inval_hit), + + .refill_core_rsp_valid_o (refill_core_rsp_valid), + .refill_core_rsp_o (refill_core_rsp), + + .mem_req_ready_i (mem_req_read_miss_ready), + .mem_req_valid_o (mem_req_read_miss_valid), + .mem_req_o (mem_req_read_miss), + + .mem_resp_ready_o (mem_resp_read_miss_ready), + .mem_resp_valid_i (mem_resp_read_miss_valid), + .mem_resp_i (mem_resp_read_miss), + .mem_resp_inval_i (mem_resp_read_miss_inval), + .mem_resp_inval_nline_i (mem_resp_read_miss_inval_nline) + ); + // }}} + + // Uncacheable request handler + // {{{ + hpdcache_uncached #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_offset_t (hpdcache_offset_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_req_addr_t (hpdcache_req_addr_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t (hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t) + ) hpdcache_uc_i( + .clk_i, + .rst_ni, + + .wbuf_empty_i (wbuf_empty_o), + .mshr_empty_i (miss_mshr_empty), + .rtab_empty_i (rtab_empty), + .ctrl_empty_i (ctrl_empty), + .flush_empty_i (flush_empty), + + .req_valid_i (uc_req_valid), + .req_ready_o (uc_ready), + .req_op_i (uc_req_op), + .req_addr_i (uc_req_addr), + .req_size_i (uc_req_size), + .req_data_i (uc_req_data), + .req_be_i (uc_req_be), + .req_uc_i (uc_req_uncacheable), + .req_sid_i (uc_req_sid), + .req_tid_i (uc_req_tid), + .req_need_rsp_i (uc_req_need_rsp), + + .wbuf_flush_all_o (uc_wbuf_flush_all), + + .dir_amo_match_o (uc_dir_amo_match), + .dir_amo_match_set_o (uc_dir_amo_match_set), + .dir_amo_match_tag_o (uc_dir_amo_match_tag), + .dir_amo_updt_sel_victim_o (uc_dir_amo_updt_sel_victim), + .dir_amo_hit_way_i (uc_dir_amo_hit_way), + + .data_amo_write_o (uc_data_amo_write), + .data_amo_write_enable_o (uc_data_amo_write_enable), + .data_amo_write_set_o (uc_data_amo_write_set), + .data_amo_write_size_o (uc_data_amo_write_size), + .data_amo_write_word_o (uc_data_amo_write_word), + .data_amo_write_data_o (uc_data_amo_write_data), + .data_amo_write_be_o (uc_data_amo_write_be), + + .lrsc_snoop_i (uc_lrsc_snoop), + .lrsc_snoop_addr_i (uc_lrsc_snoop_addr), + .lrsc_snoop_size_i (uc_lrsc_snoop_size), + + .core_rsp_ready_i (uc_core_rsp_ready), + .core_rsp_valid_o (uc_core_rsp_valid), + .core_rsp_o (uc_core_rsp), + + .mem_read_id_i (HPDCACHE_UC_READ_ID), + .mem_write_id_i (HPDCACHE_UC_WRITE_ID), + + .mem_req_read_ready_i (mem_req_read_uc_ready), + .mem_req_read_valid_o (mem_req_read_uc_valid), + .mem_req_read_o (mem_req_read_uc), + + .mem_resp_read_ready_o (mem_resp_read_uc_ready), + .mem_resp_read_valid_i (mem_resp_read_uc_valid), + .mem_resp_read_i (mem_resp_read_uc), + + .mem_req_write_ready_i (mem_req_write_uc_ready), + .mem_req_write_valid_o (mem_req_write_uc_valid), + .mem_req_write_o (mem_req_write_uc), + + .mem_req_write_data_ready_i (mem_req_write_uc_data_ready), + .mem_req_write_data_valid_o (mem_req_write_uc_data_valid), + .mem_req_write_data_o (mem_req_write_uc_data), + + .mem_resp_write_ready_o (mem_resp_write_uc_ready), + .mem_resp_write_valid_i (mem_resp_write_uc_valid), + .mem_resp_write_i (mem_resp_write_uc), + + .cfg_error_on_cacheable_amo_i + ); + // }}} + + // CMO Request Handler + // {{{ + hpdcache_cmo #( + .HPDcacheCfg (HPDcacheCfg), + + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + + .hpdcache_rsp_t (hpdcache_rsp_t), + .hpdcache_req_addr_t (hpdcache_req_addr_t), + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + .hpdcache_req_data_t (hpdcache_req_data_t) + ) hpdcache_cmo_i( + .clk_i, + .rst_ni, + + .wbuf_empty_i (wbuf_empty_o), + .mshr_empty_i (miss_mshr_empty), + .rtab_empty_i (rtab_empty), + .ctrl_empty_i (ctrl_empty), + + .req_valid_i (cmo_req_valid), + .req_ready_o (cmo_ready), + .req_op_i (cmo_req_op), + .req_addr_i (cmo_req_addr), + .req_wdata_i (cmo_req_wdata), + .req_sid_i (cmo_req_sid), + .req_tid_i (cmo_req_tid), + .req_need_rsp_i (cmo_req_need_rsp), + .req_wait_o (cmo_wait), + + .core_rsp_ready_i (cmo_core_rsp_ready), + .core_rsp_valid_o (cmo_core_rsp_valid), + .core_rsp_o (cmo_core_rsp), + + .wbuf_flush_all_o (cmo_wbuf_flush_all), + + .dir_check_nline_o (cmo_dir_check_nline), + .dir_check_nline_set_o (cmo_dir_check_nline_set), + .dir_check_nline_tag_o (cmo_dir_check_nline_tag), + .dir_check_nline_hit_way_i (cmo_dir_check_nline_hit_way), + .dir_check_nline_wback_i (cmo_dir_check_nline_wback), + .dir_check_nline_dirty_i (cmo_dir_check_nline_dirty), + + .dir_check_entry_o (cmo_dir_check_entry), + .dir_check_entry_set_o (cmo_dir_check_entry_set), + .dir_check_entry_way_o (cmo_dir_check_entry_way), + .dir_check_entry_valid_i (cmo_dir_check_entry_valid), + .dir_check_entry_wback_i (cmo_dir_check_entry_wback), + .dir_check_entry_dirty_i (cmo_dir_check_entry_dirty), + .dir_check_entry_tag_i (cmo_dir_check_entry_tag), + + .dir_updt_o (cmo_dir_updt), + .dir_updt_set_o (cmo_dir_updt_set), + .dir_updt_way_o (cmo_dir_updt_way), + .dir_updt_valid_o (cmo_dir_updt_valid), + .dir_updt_wback_o (cmo_dir_updt_wback), + .dir_updt_dirty_o (cmo_dir_updt_dirty), + .dir_updt_fetch_o (cmo_dir_updt_fetch), + .dir_updt_tag_o (cmo_dir_updt_tag), + + .flush_empty_i (flush_empty), + .flush_alloc_o (cmo_flush_alloc), + .flush_alloc_ready_i (flush_alloc_ready), + .flush_alloc_nline_o (cmo_flush_alloc_nline), + .flush_alloc_way_o (cmo_flush_alloc_way) + ); + // }}} + + // Flush controller + // {{{ + if (HPDcacheCfg.u.wbEn) begin : gen_flush + assign flush_alloc = ctrl_flush_alloc | cmo_flush_alloc; + assign flush_alloc_nline = + ctrl_flush_alloc ? ctrl_flush_alloc_nline : cmo_flush_alloc_nline; + assign flush_alloc_way = + ctrl_flush_alloc ? ctrl_flush_alloc_way : cmo_flush_alloc_way; + + hpdcache_flush #( + .HPDcacheCfg (HPDcacheCfg), + + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + .hpdcache_access_data_t (hpdcache_access_data_t), + + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_data_t (hpdcache_mem_data_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t) + ) flush_i( + .clk_i, + .rst_ni, + + .flush_empty_o (flush_empty), + .flush_full_o (/* open */), + .flush_busy_o (flush_busy), + + .flush_check_nline_i (flush_check_nline), + .flush_check_hit_o (flush_check_hit), + + .flush_alloc_i (flush_alloc), + .flush_alloc_ready_o (flush_alloc_ready), + .flush_alloc_nline_i (flush_alloc_nline), + .flush_alloc_way_i (flush_alloc_way), + + .flush_data_read_o (flush_data_read), + .flush_data_read_set_o (flush_data_read_set), + .flush_data_read_word_o (flush_data_read_word), + .flush_data_read_way_o (flush_data_read_way), + .flush_data_read_data_i (flush_data_read_data), + + .flush_ack_o (flush_ack), + .flush_ack_nline_o (flush_ack_nline), + + .mem_req_write_ready_i (mem_req_write_flush_ready), + .mem_req_write_valid_o (mem_req_write_flush_valid), + .mem_req_write_o (mem_req_write_flush), + + .mem_req_write_data_ready_i (mem_req_write_flush_data_ready), + .mem_req_write_data_valid_o (mem_req_write_flush_data_valid), + .mem_req_write_data_o (mem_req_write_flush_data), + + .mem_resp_write_ready_o (mem_resp_write_flush_ready), + .mem_resp_write_valid_i (mem_resp_write_flush_valid), + .mem_resp_write_i (mem_resp_write_flush) + ); + end else begin : gen_no_flush + // The flush controller behaves as a black-hole: consumes but do not produce data + assign flush_empty = 1'b1; + assign flush_busy = 1'b0; + assign flush_check_hit = 1'b0; + assign flush_alloc_ready = 1'b1; + assign flush_data_read = 1'b0; + assign flush_data_read_set = '0; + assign flush_data_read_word = '0; + assign flush_data_read_way = '0; + assign flush_ack = 1'b0; + assign flush_ack_nline = '0; + assign mem_req_write_flush_valid = 1'b0; + assign mem_req_write_flush = '{ + mem_req_command: HPDCACHE_MEM_READ, + mem_req_atomic : HPDCACHE_MEM_ATOMIC_ADD, + default : '0 + }; + assign mem_req_write_flush_data_valid = 1'b0; + assign mem_req_write_flush_data = '0; + assign mem_resp_write_flush_ready = 1'b1; + end + // }}} + + // Read and Write Arbiters for Memory interfaces + // {{{ + + // Read request interface + // + // There is a fixed-priority arbiter between: + // - the miss_handler (higher priority); + // - the uncacheable request handler (lower priority) + logic [1:0] arb_mem_req_read_ready; + logic [1:0] arb_mem_req_read_valid; + hpdcache_mem_req_t [1:0] arb_mem_req_read; + + assign mem_req_read_miss_ready = arb_mem_req_read_ready[0]; + assign arb_mem_req_read_valid[0] = mem_req_read_miss_valid; + assign arb_mem_req_read[0] = mem_req_read_miss; + + assign mem_req_read_uc_ready = arb_mem_req_read_ready[1]; + assign arb_mem_req_read_valid[1] = mem_req_read_uc_valid; + assign arb_mem_req_read[1] = mem_req_read_uc; + + hpdcache_mem_req_read_arbiter #( + .N (2), + .hpdcache_mem_req_t (hpdcache_mem_req_t) + ) hpdcache_mem_req_read_arbiter_i( + .clk_i, + .rst_ni, + + .mem_req_read_ready_o (arb_mem_req_read_ready), + .mem_req_read_valid_i (arb_mem_req_read_valid), + .mem_req_read_i (arb_mem_req_read), + + .mem_req_read_ready_i, + .mem_req_read_valid_o, + .mem_req_read_o (mem_req_read_o) + ); + + // Read response interface + always_comb + begin : mem_resp_read_demux_comb + mem_resp_read_uc_valid = 1'b0; + mem_resp_read_miss_valid = 1'b0; + mem_resp_read_ready_o = 1'b0; + if (mem_resp_read_valid_i) begin + if (mem_resp_read_i.mem_resp_r_id == {HPDcacheCfg.u.memIdWidth{1'b1}}) begin + mem_resp_read_uc_valid = 1'b1; + mem_resp_read_ready_o = mem_resp_read_uc_ready; + end else begin + mem_resp_read_miss_valid = 1'b1; + mem_resp_read_ready_o = mem_resp_read_miss_ready; + end + end + end + + assign mem_resp_read_uc = mem_resp_read_i; + assign mem_resp_read_miss = mem_resp_read_i; +`ifdef HPDCACHE_OPENPITON + assign mem_resp_read_miss_inval = mem_resp_read_inval_i; + assign mem_resp_read_miss_inval_nline = mem_resp_read_inval_nline_i; +`else + assign mem_resp_read_miss_inval = 1'b0; + assign mem_resp_read_miss_inval_nline = '0; +`endif + + // Write request interface + // + // There is a fixed-priority arbiter between: + // - the flush controller (higher priority) + // - the write buffer + // - the uncacheable request handler (lower priority) + logic [2:0] arb_mem_req_write_ready; + logic [2:0] arb_mem_req_write_valid; + hpdcache_mem_req_t [2:0] arb_mem_req_write; + + logic [2:0] arb_mem_req_write_data_valid; + logic [2:0] arb_mem_req_write_data_ready; + hpdcache_mem_req_w_t [2:0] arb_mem_req_write_data; + + // Split the ID space into 3 segments: + // 1111...1111 -> Uncached writes + // 1xxx...xxxx -> Flush writes (where at least one x is 0) + // 0xxx...xxxx -> Write buffer writes + function automatic hpdcache_mem_req_t hpdcache_req_write_sel_id( + hpdcache_mem_req_t req, int kind + ); + // Request from the write buffer + unique if (kind == 0) begin + req.mem_req_id = {1'b0, req.mem_req_id[0 +: HPDcacheCfg.u.memIdWidth-1]}; + end + // Request from the flush controller + else if (kind == 1) begin + req.mem_req_id = {1'b1, req.mem_req_id[0 +: HPDcacheCfg.u.memIdWidth-1]}; + end + // Request from the uncached controller + else if (kind == 2) begin + req.mem_req_id = '1; + end + return req; + endfunction + + function automatic hpdcache_mem_resp_w_t hpdcache_resp_write_sel_id( + hpdcache_mem_resp_w_t resp, int kind + ); + // Response to the write buffer + unique if (kind == 0) begin + resp.mem_resp_w_id = {1'b0, resp.mem_resp_w_id[0 +: HPDcacheCfg.u.memIdWidth-1]}; + end + // Response to the flush controller + else if (kind == 1) begin + resp.mem_resp_w_id = {1'b0, resp.mem_resp_w_id[0 +: HPDcacheCfg.u.memIdWidth-1]}; + end + // Response to the uncached controller + else if (kind == 2) begin + resp.mem_resp_w_id = '1; + end + return resp; + endfunction + + assign mem_req_write_wbuf_ready = arb_mem_req_write_ready[0]; + assign arb_mem_req_write_valid[0] = mem_req_write_wbuf_valid; + assign arb_mem_req_write[0] = hpdcache_req_write_sel_id(mem_req_write_wbuf, 0); + + assign mem_req_write_wbuf_data_ready = arb_mem_req_write_data_ready[0]; + assign arb_mem_req_write_data_valid[0] = mem_req_write_wbuf_data_valid; + assign arb_mem_req_write_data[0] = mem_req_write_wbuf_data; + + assign mem_req_write_flush_ready = arb_mem_req_write_ready[1]; + assign arb_mem_req_write_valid[1] = mem_req_write_flush_valid; + assign arb_mem_req_write[1] = hpdcache_req_write_sel_id(mem_req_write_flush, 1); + + assign mem_req_write_flush_data_ready = arb_mem_req_write_data_ready[1]; + assign arb_mem_req_write_data_valid[1] = mem_req_write_flush_data_valid; + assign arb_mem_req_write_data[1] = mem_req_write_flush_data; + + assign mem_req_write_uc_ready = arb_mem_req_write_ready[2]; + assign arb_mem_req_write_valid[2] = mem_req_write_uc_valid; + assign arb_mem_req_write[2] = hpdcache_req_write_sel_id(mem_req_write_uc, 2); + + assign mem_req_write_uc_data_ready = arb_mem_req_write_data_ready[2]; + assign arb_mem_req_write_data_valid[2] = mem_req_write_uc_data_valid; + assign arb_mem_req_write_data[2] = mem_req_write_uc_data; + + hpdcache_mem_req_write_arbiter #( + .N (3), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t) + ) hpdcache_mem_req_write_arbiter_i ( + .clk_i, + .rst_ni, + + .mem_req_write_ready_o (arb_mem_req_write_ready), + .mem_req_write_valid_i (arb_mem_req_write_valid), + .mem_req_write_i (arb_mem_req_write), + + .mem_req_write_data_ready_o (arb_mem_req_write_data_ready), + .mem_req_write_data_valid_i (arb_mem_req_write_data_valid), + .mem_req_write_data_i (arb_mem_req_write_data), + + .mem_req_write_ready_i, + .mem_req_write_valid_o, + .mem_req_write_o (mem_req_write_o), + + .mem_req_write_data_ready_i, + .mem_req_write_data_valid_o, + .mem_req_write_data_o (mem_req_write_data_o) + ); + + // Write response interface + always_comb + begin : mem_resp_write_demux_comb + mem_resp_write_flush_valid = 1'b0; + mem_resp_write_wbuf_valid = 1'b0; + mem_resp_write_uc_valid = 1'b0; + mem_resp_write_ready_o = 1'b0; + if (mem_resp_write_valid_i) begin + if (mem_resp_write_i.mem_resp_w_id == {HPDcacheCfg.u.memIdWidth{1'b1}}) begin + mem_resp_write_uc_valid = 1'b1; + mem_resp_write_ready_o = mem_resp_write_uc_ready; + end else if (mem_resp_write_i.mem_resp_w_id[HPDcacheCfg.u.memIdWidth-1]) begin + mem_resp_write_flush_valid = 1'b1; + mem_resp_write_ready_o = mem_resp_write_flush_ready; + end else begin + mem_resp_write_wbuf_valid = 1'b1; + mem_resp_write_ready_o = mem_resp_write_wbuf_ready; + end + end + end + + assign mem_resp_write_wbuf = hpdcache_resp_write_sel_id(mem_resp_write_i, 0); + assign mem_resp_write_flush = hpdcache_resp_write_sel_id(mem_resp_write_i, 1); + assign mem_resp_write_uc = hpdcache_resp_write_sel_id(mem_resp_write_i, 2); + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + assert property (@(posedge clk_i) disable iff (!rst_ni) + ctrl_flush_alloc |-> !cmo_flush_alloc) else + $error("Unsupported concurrent flush from ctrl and cmo"); + + initial begin + word_width_assert: + assert (HPDcacheCfg.u.wordWidth inside {32, 64}) else + $fatal("word width shall be 32 or 64"); + req_access_width_assert: + assert (HPDcacheCfg.u.reqWords <= HPDcacheCfg.u.accessWords) else + $fatal("req data width shall be l.e. to cache access width"); + refill_access_width_assert: + assert (HPDcacheCfg.u.clWords >= HPDcacheCfg.u.accessWords) else + $fatal("cache access width shall be l.e. to cache-line width"); + cl_words_assert: + assert (HPDcacheCfg.u.clWords > 1) else + $fatal("cacheline words shall be greater than 1"); + mem_width_assert: + assert (HPDcacheCfg.u.memDataWidth >= HPDcacheCfg.reqDataWidth) else + $fatal("memory interface data width shall be g.e. to req data width"); + miss_mem_id_width_assert: + assert (HPDcacheCfg.u.memIdWidth >= + ($clog2(HPDcacheCfg.u.mshrWays * HPDcacheCfg.u.mshrSets) + 1)) else + $fatal("insufficient ID bits on the mem interface to transport misses"); + wbuf_mem_id_width_assert: + assert (HPDcacheCfg.u.memIdWidth >= (HPDcacheCfg.wbufDirPtrWidth + 1)) else + $fatal("insufficient ID bits on the mem interface to transport writes"); + wt_or_wb_assert: + assert (HPDcacheCfg.u.wtEn || HPDcacheCfg.u.wbEn) else + $fatal("the cache shall be configured to support WT, WB or both"); + end +`endif + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv new file mode 100644 index 0000000000..d233af1d83 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv @@ -0,0 +1,67 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : May, 2021 + * Description : HPDcache AMO computing unit + * History : + */ +module hpdcache_amo +import hpdcache_pkg::*; +// Ports +// {{{ +( + input logic [63:0] ld_data_i, + input logic [63:0] st_data_i, + input hpdcache_uc_op_t op_i, + output logic [63:0] result_o +); +// }}} + + logic signed [63:0] ld_data; + logic signed [63:0] st_data; + logic signed [63:0] sum; + logic ugt, sgt; + + assign ld_data = ld_data_i, + st_data = st_data_i; + + assign ugt = (ld_data_i > st_data_i), + sgt = (ld_data > st_data), + sum = ld_data + st_data; + + always_comb + begin : amo_compute_comb + unique case (1'b1) + op_i.is_amo_lr : result_o = ld_data_i; + op_i.is_amo_sc : result_o = st_data_i; + op_i.is_amo_swap : result_o = st_data_i; + op_i.is_amo_add : result_o = sum; + op_i.is_amo_and : result_o = ld_data_i & st_data_i; + op_i.is_amo_or : result_o = ld_data_i | st_data_i; + op_i.is_amo_xor : result_o = ld_data_i ^ st_data_i; + op_i.is_amo_max : result_o = sgt ? ld_data_i : st_data_i; + op_i.is_amo_maxu : result_o = ugt ? ld_data_i : st_data_i; + op_i.is_amo_min : result_o = sgt ? st_data_i : ld_data_i; + op_i.is_amo_minu : result_o = ugt ? st_data_i : ld_data_i; + default : result_o = '0; + endcase + end +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv new file mode 100644 index 0000000000..6ab2955ff9 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv @@ -0,0 +1,633 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : July, 2021 + * Description : HPDcache Cache-Management-Operation Handler + * History : + */ +module hpdcache_cmo +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_way_vector_t = logic, + + parameter type hpdcache_rsp_t = logic, + parameter type hpdcache_req_addr_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_data_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Global control signals + // {{{ + input logic wbuf_empty_i, + input logic mshr_empty_i, + input logic rtab_empty_i, + input logic ctrl_empty_i, + // }}} + + // Request interface + // {{{ + input logic req_valid_i, + output logic req_ready_o, + input hpdcache_cmoh_op_t req_op_i, + input hpdcache_req_addr_t req_addr_i, + input hpdcache_req_data_t req_wdata_i/*unused*/, + input hpdcache_req_sid_t req_sid_i, + input hpdcache_req_tid_t req_tid_i, + input logic req_need_rsp_i, + output logic req_wait_o, + // }}} + + // Core response interface + // {{{ + input logic core_rsp_ready_i, + output logic core_rsp_valid_o, + output hpdcache_rsp_t core_rsp_o, + // }}} + + // Write Buffer Interface + // {{{ + output logic wbuf_flush_all_o, + // }}} + + // Cache Directory Interface + // {{{ + output logic dir_check_nline_o, + output hpdcache_set_t dir_check_nline_set_o, + output hpdcache_tag_t dir_check_nline_tag_o, + input hpdcache_way_vector_t dir_check_nline_hit_way_i, + input logic dir_check_nline_wback_i, + input logic dir_check_nline_dirty_i, + + output logic dir_check_entry_o, + output hpdcache_set_t dir_check_entry_set_o, + output hpdcache_way_vector_t dir_check_entry_way_o, + input logic dir_check_entry_valid_i, + input logic dir_check_entry_wback_i, + input logic dir_check_entry_dirty_i, + input hpdcache_tag_t dir_check_entry_tag_i, + + output logic dir_updt_o, + output hpdcache_set_t dir_updt_set_o, + output hpdcache_way_vector_t dir_updt_way_o, + output logic dir_updt_valid_o, + output logic dir_updt_wback_o, + output logic dir_updt_dirty_o, + output logic dir_updt_fetch_o, + output hpdcache_tag_t dir_updt_tag_o, + // }}} + + // Flush Controller Interface + // {{{ + input logic flush_empty_i, + output logic flush_alloc_o, + input logic flush_alloc_ready_i, + output hpdcache_nline_t flush_alloc_nline_o, + output hpdcache_way_vector_t flush_alloc_way_o + // }}} +); +// }}} + +// Definition of constants and types +// {{{ + typedef enum { + CMOH_IDLE, + CMOH_FENCE_WAIT_WBUF_RTAB_EMPTY, + CMOH_WAIT_MSHR_RTAB_EMPTY, + CMOH_INVAL_CHECK_NLINE, + CMOH_INVAL_SET, + CMOH_FLUSH_ALL_FIRST, + CMOH_FLUSH_ALL_NEXT, + CMOH_FLUSH_ALL_LAST, + CMOH_FLUSH_NLINE_FIRST, + CMOH_FLUSH_NLINE_NEXT + } hpdcache_cmoh_fsm_t; +// }}} + +// Internal signals and registers +// {{{ + hpdcache_cmoh_fsm_t cmoh_fsm_q, cmoh_fsm_d; + hpdcache_cmoh_op_t cmoh_op_q, cmoh_op_d; + hpdcache_req_addr_t cmoh_addr_q, cmoh_addr_d; + hpdcache_way_vector_t cmoh_way_q, cmoh_way_d; + hpdcache_set_t cmoh_set_q, cmoh_set_d; + + logic cmoh_flush_req_valid_q, cmoh_flush_req_valid_d; + hpdcache_set_t cmoh_flush_req_set_q, cmoh_flush_req_set_d; + hpdcache_way_vector_t cmoh_flush_req_way_q, cmoh_flush_req_way_d; + logic cmoh_flush_req_inval_q, cmoh_flush_req_inval_d; + + logic cmoh_dir_check_nline_hit; + hpdcache_nline_t cmoh_nline; + hpdcache_set_t cmoh_set; + hpdcache_tag_t cmoh_tag; + logic cmoh_flush_req_w; + logic cmoh_flush_req_wok; + hpdcache_set_t cmoh_flush_req_set; + hpdcache_tag_t cmoh_flush_req_tag; + hpdcache_way_vector_t cmoh_flush_req_way; + + logic core_rsp_w, core_rsp_r, core_rsp_rok; + hpdcache_rsp_t core_rsp; + logic core_rsp_send_q, core_rsp_send_d; + + logic cmoh_set_incr, cmoh_set_reset, cmoh_set_last; + logic cmoh_way_incr, cmoh_way_reset, cmoh_way_last; +// }}} + +// CMO core response buffer +// {{{ + hpdcache_sync_buffer #( + .FEEDTHROUGH (1'b0), + .data_t (hpdcache_rsp_t) + ) cmoh_core_rsp_buffer_i( + .clk_i, + .rst_ni, + .w_i (core_rsp_w), + .wok_o (/*unused*/), + .wdata_i (core_rsp), + .r_i (core_rsp_r), + .rok_o (core_rsp_rok), + .rdata_o (core_rsp_o) + ); + + assign core_rsp_r = core_rsp_send_q & core_rsp_ready_i; + assign core_rsp_valid_o = core_rsp_rok & core_rsp_send_q; +// }}} + +// CMO request handler FSM +// {{{ + assign cmoh_nline = cmoh_addr_q[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.nlineWidth]; + assign cmoh_set = cmoh_nline[0 +: HPDcacheCfg.setWidth]; + assign cmoh_tag = cmoh_nline[HPDcacheCfg.setWidth +: HPDcacheCfg.tagWidth]; + + assign req_wait_o = (cmoh_fsm_q == CMOH_FENCE_WAIT_WBUF_RTAB_EMPTY) | + (cmoh_fsm_q == CMOH_WAIT_MSHR_RTAB_EMPTY); + + assign cmoh_dir_check_nline_hit = |dir_check_nline_hit_way_i; + + assign core_rsp = '{ + rdata: '0, + sid: req_sid_i, + tid: req_tid_i, + error: 1'b0, + aborted: 1'b0 + }; + + always_comb + begin : cmoh_fsm_comb + cmoh_fsm_d = cmoh_fsm_q; + + cmoh_op_d = cmoh_op_q; + cmoh_addr_d = cmoh_addr_q; + + cmoh_flush_req_valid_d = cmoh_flush_req_valid_q; + cmoh_flush_req_set_d = cmoh_flush_req_set_q; + cmoh_flush_req_way_d = cmoh_flush_req_way_q; + cmoh_flush_req_inval_d = cmoh_flush_req_inval_q; + + cmoh_set_incr = 1'b0; + cmoh_set_reset = 1'b0; + cmoh_way_incr = 1'b0; + cmoh_way_reset = 1'b0; + + dir_check_nline_o = 1'b0; + dir_check_nline_set_o = cmoh_set; + dir_check_nline_tag_o = cmoh_tag; + dir_check_entry_o = 1'b0; + dir_check_entry_set_o = cmoh_set_q; + dir_check_entry_way_o = cmoh_way_q; + + dir_updt_o = 1'b0; + dir_updt_set_o = '0; + dir_updt_way_o = '0; + dir_updt_valid_o = 1'b0; + dir_updt_wback_o = 1'b0; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = '0; + + wbuf_flush_all_o = 1'b0; + + cmoh_flush_req_set = '0; + cmoh_flush_req_way = '0; + cmoh_flush_req_tag = '0; + + core_rsp_w = 1'b0; + core_rsp_send_d = core_rsp_send_q; + + req_ready_o = 1'b0; + + cmoh_fsm_d = cmoh_fsm_q; + + unique case (cmoh_fsm_q) + CMOH_IDLE: begin + req_ready_o = ~core_rsp_rok | core_rsp_r; + + if (core_rsp_r) begin + core_rsp_send_d = 1'b0; + end + + if (req_valid_i && req_ready_o) begin + core_rsp_w = req_need_rsp_i; + + unique case (1'b1) + req_op_i.is_fence: begin + // request to the write buffer to send all open entries + wbuf_flush_all_o = rtab_empty_i; + + // then wait for the write buffer to be empty + if (!rtab_empty_i || !wbuf_empty_i) begin + cmoh_fsm_d = CMOH_FENCE_WAIT_WBUF_RTAB_EMPTY; + end else begin + core_rsp_send_d = req_need_rsp_i; + end + end + + req_op_i.is_inval_by_nline, + req_op_i.is_inval_all, + req_op_i.is_flush_by_nline, + req_op_i.is_flush_all, + req_op_i.is_flush_inval_by_nline, + req_op_i.is_flush_inval_all: begin + cmoh_op_d = req_op_i; + cmoh_addr_d = req_addr_i; + cmoh_way_reset = 1'b1; + cmoh_set_reset = 1'b1; + if (mshr_empty_i && rtab_empty_i && ctrl_empty_i) begin // CMO + unique if (req_op_i.is_inval_by_nline) begin + cmoh_fsm_d = CMOH_INVAL_CHECK_NLINE; + end else if (req_op_i.is_inval_all) begin + cmoh_fsm_d = CMOH_INVAL_SET; + end else if (req_op_i.is_flush_by_nline) begin + cmoh_flush_req_inval_d = 1'b0; + cmoh_fsm_d = CMOH_FLUSH_NLINE_FIRST; + end else if (req_op_i.is_flush_all) begin + cmoh_flush_req_inval_d = 1'b0; + cmoh_fsm_d = CMOH_FLUSH_ALL_FIRST; + end else if (req_op_i.is_flush_inval_by_nline) begin + cmoh_flush_req_inval_d = 1'b1; + cmoh_fsm_d = CMOH_FLUSH_NLINE_FIRST; + end else if (req_op_i.is_flush_inval_all) begin + cmoh_flush_req_inval_d = 1'b1; + cmoh_fsm_d = CMOH_FLUSH_ALL_FIRST; + end + end else begin + cmoh_fsm_d = CMOH_WAIT_MSHR_RTAB_EMPTY; + end + end + endcase + end + end + CMOH_FENCE_WAIT_WBUF_RTAB_EMPTY: begin + wbuf_flush_all_o = rtab_empty_i; + if (wbuf_empty_i && rtab_empty_i) begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + CMOH_WAIT_MSHR_RTAB_EMPTY: begin + if (mshr_empty_i && rtab_empty_i && ctrl_empty_i) begin + unique if (cmoh_op_q.is_inval_by_nline) begin + cmoh_fsm_d = CMOH_INVAL_CHECK_NLINE; + end else if (cmoh_op_q.is_inval_all) begin + cmoh_fsm_d = CMOH_INVAL_SET; + end else if (cmoh_op_q.is_flush_by_nline) begin + cmoh_flush_req_inval_d = 1'b0; + cmoh_fsm_d = CMOH_FLUSH_NLINE_FIRST; + end else if (cmoh_op_q.is_flush_all) begin + cmoh_flush_req_inval_d = 1'b0; + cmoh_fsm_d = CMOH_FLUSH_ALL_FIRST; + end else if (cmoh_op_q.is_flush_inval_by_nline) begin + cmoh_flush_req_inval_d = 1'b1; + cmoh_fsm_d = CMOH_FLUSH_NLINE_FIRST; + end else if (cmoh_op_q.is_flush_inval_all) begin + cmoh_flush_req_inval_d = 1'b1; + cmoh_fsm_d = CMOH_FLUSH_ALL_FIRST; + end + end + end + CMOH_INVAL_CHECK_NLINE: begin + dir_check_nline_o = 1'b1; + cmoh_fsm_d = CMOH_INVAL_SET; + end + CMOH_INVAL_SET: begin + unique case (1'b1) + // The CMO requests the invalidation of a given cacheline (or flush with + // invalidation when the cache does not support WB policy) + cmoh_op_q.is_inval_by_nline, + cmoh_op_q.is_flush_inval_by_nline: begin + /* FIXME this adds a DIR to DIR timing path. We should probably delay the + * invalidation of one cycle to ease the timing closure */ + dir_updt_o = cmoh_dir_check_nline_hit; + dir_updt_set_o = cmoh_set; + dir_updt_way_o = dir_check_nline_hit_way_i; + dir_updt_valid_o = 1'b0; + dir_updt_wback_o = 1'b0; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = '0; + + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + + // The CMO requests a full invalidation (or flush with invalidation when the + // cache does not support WB policy) + cmoh_op_q.is_inval_all, + cmoh_op_q.is_flush_inval_all: + begin + dir_updt_o = 1'b1; + dir_updt_set_o = cmoh_set_q; + dir_updt_way_o = {HPDcacheCfg.u.ways{1'b1}}; + dir_updt_valid_o = 1'b0; + dir_updt_wback_o = 1'b0; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = '0; + cmoh_set_incr = 1'b1; + if (cmoh_set_last) begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + endcase + end + CMOH_FLUSH_ALL_FIRST: begin + if (HPDcacheCfg.u.wbEn) begin + if (cmoh_flush_req_wok) begin + dir_check_entry_o = 1'b1; + cmoh_set_incr = cmoh_way_last; + cmoh_way_incr = 1'b1; + cmoh_flush_req_valid_d = 1'b1; + cmoh_flush_req_set_d = cmoh_set_q; + cmoh_flush_req_way_d = cmoh_way_q; + cmoh_fsm_d = CMOH_FLUSH_ALL_NEXT; + end + end else if (cmoh_flush_req_inval_q) begin + cmoh_fsm_d = CMOH_INVAL_SET; + end else begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + CMOH_FLUSH_ALL_NEXT: begin + if (cmoh_flush_req_valid_q) begin + dir_updt_o = dir_check_entry_valid_i & + (dir_check_entry_dirty_i | cmoh_flush_req_inval_q); + + dir_updt_set_o = cmoh_flush_req_set_q; + dir_updt_way_o = cmoh_flush_req_way_q; + dir_updt_valid_o = ~cmoh_flush_req_inval_q; + dir_updt_wback_o = ~cmoh_flush_req_inval_q & dir_check_entry_wback_i; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = dir_check_entry_tag_i; + + cmoh_flush_req_set = cmoh_flush_req_set_q; + cmoh_flush_req_way = cmoh_flush_req_way_q; + cmoh_flush_req_tag = dir_check_entry_tag_i; + + // The CMO handler needs to dedicate one cycle to + // check the directory and one cycle to update that entry. + // This means that the CMO handler takes 2 cycles per flush request + cmoh_flush_req_valid_d = 1'b0; + end + + if (!cmoh_flush_req_valid_q && cmoh_flush_req_wok) begin + dir_check_entry_o = 1'b1; + cmoh_set_incr = cmoh_way_last; + cmoh_way_incr = 1'b1; + cmoh_flush_req_valid_d = 1'b1; + cmoh_flush_req_set_d = cmoh_set_q; + cmoh_flush_req_way_d = cmoh_way_q; + + if (cmoh_set_last && cmoh_way_last) begin + cmoh_fsm_d = CMOH_FLUSH_ALL_LAST; + end + end + end + CMOH_FLUSH_ALL_LAST: begin + cmoh_flush_req_valid_d = 1'b0; + if (cmoh_flush_req_valid_q) begin + dir_updt_o = dir_check_entry_valid_i & + (dir_check_entry_dirty_i | cmoh_flush_req_inval_q); + + dir_updt_set_o = cmoh_flush_req_set_q; + dir_updt_way_o = cmoh_flush_req_way_q; + dir_updt_valid_o = ~cmoh_flush_req_inval_q; + dir_updt_wback_o = ~cmoh_flush_req_inval_q & dir_check_entry_wback_i; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = dir_check_entry_tag_i; + cmoh_flush_req_set = cmoh_flush_req_set_q; + cmoh_flush_req_way = cmoh_flush_req_way_q; + cmoh_flush_req_tag = dir_check_entry_tag_i; + end + + // Make sure that all requests have been processed + if (flush_empty_i && !flush_alloc_o) begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + CMOH_FLUSH_NLINE_FIRST: begin + if (HPDcacheCfg.u.wbEn) begin + if (cmoh_flush_req_wok) begin + dir_check_nline_o = 1'b1; + cmoh_flush_req_valid_d = 1'b1; + cmoh_fsm_d = CMOH_FLUSH_NLINE_NEXT; + end + end else if (cmoh_flush_req_inval_q) begin + cmoh_fsm_d = CMOH_INVAL_CHECK_NLINE; + end else begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + CMOH_FLUSH_NLINE_NEXT: begin + cmoh_flush_req_valid_d = 1'b0; + if (cmoh_flush_req_valid_q) begin + /* FIXME this adds a DIR to DIR timing path. We should probably delay the + * invalidation of one cycle to ease the timing closure */ + dir_updt_o = cmoh_dir_check_nline_hit; + dir_updt_set_o = cmoh_set; + dir_updt_way_o = dir_check_nline_hit_way_i; + dir_updt_valid_o = ~cmoh_flush_req_inval_q; + dir_updt_wback_o = ~cmoh_flush_req_inval_q & dir_check_nline_wback_i; + dir_updt_dirty_o = 1'b0; + dir_updt_fetch_o = 1'b0; + dir_updt_tag_o = cmoh_tag; + cmoh_flush_req_set = cmoh_set; + cmoh_flush_req_tag = cmoh_tag; + cmoh_flush_req_way = dir_check_nline_hit_way_i; + end + + // Make sure that all requests have been processed + if (flush_empty_i && !flush_alloc_o) begin + core_rsp_send_d = core_rsp_rok; + cmoh_fsm_d = CMOH_IDLE; + end + end + endcase + end + + assign cmoh_set_last = (cmoh_set_q == hpdcache_set_t'(HPDcacheCfg.u.sets - 1)); + + always_comb + begin : set_incr_comb + cmoh_set_d = cmoh_set_q; + if (cmoh_set_reset) begin + cmoh_set_d = '0; + end else if (cmoh_set_incr) begin + cmoh_set_d = cmoh_set_last ? '0 : cmoh_set_q + 1; + end + end + + assign cmoh_way_last = cmoh_way_q[HPDcacheCfg.u.ways - 1]; + + always_comb + begin : way_incr_comb + cmoh_way_d = cmoh_way_q; + if (cmoh_way_reset) begin + cmoh_way_d = hpdcache_way_vector_t'(1); + end else if (cmoh_way_incr) begin + cmoh_way_d = cmoh_way_last ? + hpdcache_way_vector_t'(1) : {cmoh_way_q[0 +: HPDcacheCfg.u.ways-1], 1'b0}; + end + end +// }}} + +// CMO request handler set state +// {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + core_rsp_send_q <= 1'b0; + cmoh_fsm_q <= CMOH_IDLE; + end else begin + core_rsp_send_q <= core_rsp_send_d; + cmoh_fsm_q <= cmoh_fsm_d; + end + end + + always_ff @(posedge clk_i) + begin + cmoh_op_q <= cmoh_op_d; + cmoh_addr_q <= cmoh_addr_d; + cmoh_way_q <= cmoh_way_d; + cmoh_set_q <= cmoh_set_d; + cmoh_flush_req_valid_q <= cmoh_flush_req_valid_d; + cmoh_flush_req_set_q <= cmoh_flush_req_set_d; + cmoh_flush_req_way_q <= cmoh_flush_req_way_d; + cmoh_flush_req_inval_q <= cmoh_flush_req_inval_d; + end +// }}} + +// CMO internal components +// {{{ + typedef struct packed { + hpdcache_nline_t nline; + hpdcache_way_vector_t way; + } cmoh_flush_req_t; + + if (HPDcacheCfg.u.wbEn) begin : gen_cmo_flush_fifo + cmoh_flush_req_t cmoh_flush_req_wdata, cmoh_flush_req_rdata; + + always_comb + begin : cmoh_flush_req_w_comb + cmoh_flush_req_w = 1'b0; + if (cmoh_flush_req_valid_q) begin + unique case (cmoh_fsm_q) + CMOH_FLUSH_ALL_NEXT, CMOH_FLUSH_ALL_LAST: + cmoh_flush_req_w = dir_check_entry_valid_i & dir_check_entry_dirty_i; + CMOH_FLUSH_NLINE_NEXT: + cmoh_flush_req_w = cmoh_dir_check_nline_hit & dir_check_nline_dirty_i; + endcase + end + end + + assign cmoh_flush_req_wdata = '{ + nline: {cmoh_flush_req_tag, cmoh_flush_req_set}, + way : cmoh_flush_req_way + }; + + hpdcache_fifo_reg #( + .FIFO_DEPTH (3), + .FEEDTHROUGH (1'b1), + .fifo_data_t (cmoh_flush_req_t) + ) flush_req_fifo_i( + .clk_i, + .rst_ni, + .w_i (cmoh_flush_req_w), + .wok_o (cmoh_flush_req_wok), + .wdata_i (cmoh_flush_req_wdata), + .r_i (flush_alloc_ready_i), + .rok_o (flush_alloc_o), + .rdata_o (cmoh_flush_req_rdata) + ); + + assign flush_alloc_nline_o = cmoh_flush_req_rdata.nline; + assign flush_alloc_way_o = cmoh_flush_req_rdata.way; + end else begin : gen_cmo_no_flush_fifo + assign cmoh_flush_req_w = 1'b0; + assign cmoh_flush_req_wok = 1'b1; + assign flush_alloc_o = 1'b0; + assign flush_alloc_nline_o = '0; + assign flush_alloc_way_o = '0; + end +// }}} + +// Assertions +// {{{ +`ifndef HPDCACHE_ASSERT_OFF + assert property (@(posedge clk_i) disable iff (!rst_ni) + req_valid_i -> $onehot({req_op_i.is_fence, + req_op_i.is_inval_by_nline, + req_op_i.is_inval_all, + req_op_i.is_flush_by_nline, + req_op_i.is_flush_all, + req_op_i.is_flush_inval_by_nline, + req_op_i.is_flush_inval_all})) else + $error("cmo_handler: invalid request"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + req_valid_i -> (cmoh_fsm_q == CMOH_IDLE)) else + $error("cmo_handler: new request received while busy"); +`endif +// }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv new file mode 100644 index 0000000000..b1ac5509b8 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv @@ -0,0 +1,174 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : September, 2023 + * Description : HPDcache request arbiter + * History : + */ +module hpdcache_core_arbiter +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic +) + // }}} + + // Ports + // {{{ +( + // Clock and reset signals + input logic clk_i, + input logic rst_ni, + + // Core request interface + // 1st cycle + input logic core_req_valid_i [HPDcacheCfg.u.nRequesters], + output logic core_req_ready_o [HPDcacheCfg.u.nRequesters], + input hpdcache_req_t core_req_i [HPDcacheCfg.u.nRequesters], + // 2nd cycle + input logic core_req_abort_i [HPDcacheCfg.u.nRequesters], + input hpdcache_tag_t core_req_tag_i [HPDcacheCfg.u.nRequesters], + input hpdcache_pma_t core_req_pma_i [HPDcacheCfg.u.nRequesters], + + // Core response interface + input logic core_rsp_valid_i, + input hpdcache_rsp_t core_rsp_i, + output logic core_rsp_valid_o [HPDcacheCfg.u.nRequesters], + output hpdcache_rsp_t core_rsp_o [HPDcacheCfg.u.nRequesters], + + // Granted request + output logic arb_req_valid_o, + input logic arb_req_ready_i, + output hpdcache_req_t arb_req_o, + output logic arb_abort_o, + output hpdcache_tag_t arb_tag_o, + output hpdcache_pma_t arb_pma_o +); + + // }}} + + // Declaration of internal signals + // {{{ + logic [HPDcacheCfg.u.nRequesters-1:0] core_req_valid; + hpdcache_req_t [HPDcacheCfg.u.nRequesters-1:0] core_req; + logic [HPDcacheCfg.u.nRequesters-1:0] core_req_abort; + hpdcache_tag_t [HPDcacheCfg.u.nRequesters-1:0] core_req_tag; + hpdcache_pma_t [HPDcacheCfg.u.nRequesters-1:0] core_req_pma; + + logic [HPDcacheCfg.u.nRequesters-1:0] arb_req_gnt_q, arb_req_gnt_d; + // }}} + + // Requesters arbiter + // {{{ + // Pack request ports + genvar gen_i; + + generate + for (gen_i = 0; gen_i < int'(HPDcacheCfg.u.nRequesters); gen_i++) begin : gen_core_req + assign core_req_ready_o[gen_i] = arb_req_gnt_d[gen_i] & arb_req_ready_i, + core_req_valid[gen_i] = core_req_valid_i[gen_i], + core_req[gen_i] = core_req_i[gen_i]; + + assign core_req_abort[gen_i] = core_req_abort_i[gen_i], + core_req_tag[gen_i] = core_req_tag_i[gen_i], + core_req_pma[gen_i] = core_req_pma_i[gen_i]; + end + endgenerate + + // Arbiter + hpdcache_fxarb #(.N(HPDcacheCfg.u.nRequesters)) req_arbiter_i + ( + .clk_i, + .rst_ni, + .req_i (core_req_valid), + .gnt_o (arb_req_gnt_d), + .ready_i (arb_req_ready_i) + ); + + // Request multiplexor + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.nRequesters), + .DATA_WIDTH ($bits(hpdcache_req_t)), + .ONE_HOT_SEL (1'b1) + ) core_req_mux_i ( + .data_i (core_req), + .sel_i (arb_req_gnt_d), + .data_o (arb_req_o) + ); + + // Request abort multiplexor + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.nRequesters), + .DATA_WIDTH (1), + .ONE_HOT_SEL (1'b1) + ) core_req_abort_mux_i ( + .data_i (core_req_abort), + .sel_i (arb_req_gnt_q), + .data_o (arb_abort_o) + ); + + // Tag Multiplexor + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.nRequesters), + .DATA_WIDTH ($bits(hpdcache_tag_t)), + .ONE_HOT_SEL (1'b1) + ) core_req_tag_mux_i ( + .data_i (core_req_tag), + .sel_i (arb_req_gnt_q), + .data_o (arb_tag_o) + ); + + // PMA Multiplexor + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.nRequesters), + .DATA_WIDTH ($bits(hpdcache_pma_t)), + .ONE_HOT_SEL (1'b1) + ) core_req_pma_mux_i ( + .data_i (core_req_pma), + .sel_i (arb_req_gnt_q), + .data_o (arb_pma_o) + ); + + // Save the grant signal for the tag in the next cycle + always_ff @(posedge clk_i or negedge rst_ni) + begin : arb_req_gnt_ff + if (!rst_ni) arb_req_gnt_q <= '0; + else arb_req_gnt_q <= arb_req_gnt_d; + end + + assign arb_req_valid_o = |arb_req_gnt_d; + // }}} + + // Response demultiplexor + // {{{ + always_comb + begin : resp_demux + for (int unsigned i = 0; i < HPDcacheCfg.u.nRequesters; i++) begin + core_rsp_valid_o[i] = core_rsp_valid_i && (i == hpdcache_uint32'(core_rsp_i.sid)); + core_rsp_o[i] = core_rsp_i; + end + end + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv new file mode 100644 index 0000000000..9f8592e36a --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv @@ -0,0 +1,1115 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache controller + * History : + */ +module hpdcache_ctrl + // Package imports + // {{{ +import hpdcache_pkg::*; + // }}} + + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_word_t = logic, + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_data_be_t = logic, + parameter type hpdcache_dir_entry_t = logic, + parameter type hpdcache_way_vector_t = logic, + parameter type hpdcache_way_t = logic, + + parameter type wbuf_addr_t = logic, + parameter type wbuf_data_t = logic, + parameter type wbuf_be_t = logic, + + parameter type hpdcache_access_data_t = logic, + parameter type hpdcache_access_be_t = logic, + + parameter type hpdcache_req_addr_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic +) + // }}} + + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + + // Core request interface + input logic core_req_valid_i, + output logic core_req_ready_o, + input hpdcache_req_t core_req_i, + input logic core_req_abort_i, + input hpdcache_tag_t core_req_tag_i, + input hpdcache_pma_t core_req_pma_i, + + // Core response interface + output logic core_rsp_valid_o, + output hpdcache_rsp_t core_rsp_o, + + // Force the write buffer to send all pending writes + input logic wbuf_flush_i, + + // Global control signals + output logic cachedir_hit_o, + + // Miss handler interface + output logic st0_mshr_check_o, + output hpdcache_req_offset_t st0_mshr_check_offset_o, + output hpdcache_nline_t st1_mshr_check_nline_o, + input logic st1_mshr_hit_i, + input logic st1_mshr_alloc_ready_i, + input logic st1_mshr_alloc_full_i, + output logic st2_mshr_alloc_o, + output logic st2_mshr_alloc_cs_o, + output hpdcache_nline_t st2_mshr_alloc_nline_o, + output hpdcache_req_tid_t st2_mshr_alloc_tid_o, + output hpdcache_req_sid_t st2_mshr_alloc_sid_o, + output hpdcache_word_t st2_mshr_alloc_word_o, + output hpdcache_way_vector_t st2_mshr_alloc_victim_way_o, + output logic st2_mshr_alloc_need_rsp_o, + output logic st2_mshr_alloc_is_prefetch_o, + output logic st2_mshr_alloc_wback_o, + + // Refill interface + input logic refill_req_valid_i, + output logic refill_req_ready_o, + input logic refill_is_error_i, + input logic refill_busy_i, + input logic refill_updt_sel_victim_i, + input hpdcache_set_t refill_set_i, + input hpdcache_way_vector_t refill_way_i, + input hpdcache_dir_entry_t refill_dir_entry_i, + input logic refill_write_dir_i, + input logic refill_write_data_i, + input hpdcache_word_t refill_word_i, + input hpdcache_access_data_t refill_data_i, + input logic refill_core_rsp_valid_i, + input hpdcache_rsp_t refill_core_rsp_i, + input hpdcache_nline_t refill_nline_i, + input logic refill_updt_rtab_i, + + // Flush interface + input logic flush_busy_i, + output hpdcache_nline_t flush_check_nline_o, + input logic flush_check_hit_i, + output logic flush_alloc_o, + input logic flush_alloc_ready_i, + output hpdcache_nline_t flush_alloc_nline_o, + output hpdcache_way_vector_t flush_alloc_way_o, + input logic flush_data_read_i, + input hpdcache_set_t flush_data_read_set_i, + input hpdcache_word_t flush_data_read_word_i, + input hpdcache_way_vector_t flush_data_read_way_i, + output hpdcache_access_data_t flush_data_read_data_o, + input logic flush_ack_i, + input hpdcache_nline_t flush_ack_nline_i, + + // Invalidate interface + input logic inval_check_dir_i, + input logic inval_write_dir_i, + input hpdcache_nline_t inval_nline_i, + output logic inval_hit_o, + + // Write buffer interface + input logic wbuf_empty_i, + output logic wbuf_flush_all_o, + output logic wbuf_write_o, + input logic wbuf_write_ready_i, + output wbuf_addr_t wbuf_write_addr_o, + output wbuf_data_t wbuf_write_data_o, + output wbuf_be_t wbuf_write_be_o, + output logic wbuf_write_uncacheable_o, + input logic wbuf_read_hit_i, + output logic wbuf_read_flush_hit_o, + output hpdcache_req_addr_t wbuf_rtab_addr_o, + output logic wbuf_rtab_is_read_o, + input logic wbuf_rtab_hit_open_i, + input logic wbuf_rtab_hit_pend_i, + input logic wbuf_rtab_hit_sent_i, + input logic wbuf_rtab_not_ready_i, + + // Uncacheable request handler + input logic uc_busy_i, + output logic uc_lrsc_snoop_o, + output hpdcache_req_addr_t uc_lrsc_snoop_addr_o, + output hpdcache_req_size_t uc_lrsc_snoop_size_o, + output logic uc_req_valid_o, + output hpdcache_uc_op_t uc_req_op_o, + output hpdcache_req_addr_t uc_req_addr_o, + output hpdcache_req_size_t uc_req_size_o, + output hpdcache_req_data_t uc_req_data_o, + output hpdcache_req_be_t uc_req_be_o, + output logic uc_req_uc_o, + output hpdcache_req_sid_t uc_req_sid_o, + output hpdcache_req_tid_t uc_req_tid_o, + output logic uc_req_need_rsp_o, + input logic uc_wbuf_flush_all_i, + input logic uc_dir_amo_match_i, + input hpdcache_set_t uc_dir_amo_match_set_i, + input hpdcache_tag_t uc_dir_amo_match_tag_i, + input logic uc_dir_amo_updt_sel_victim_i, + output hpdcache_way_vector_t uc_dir_amo_hit_way_o, + input logic uc_data_amo_write_i, + input logic uc_data_amo_write_enable_i, + input hpdcache_set_t uc_data_amo_write_set_i, + input hpdcache_req_size_t uc_data_amo_write_size_i, + input hpdcache_word_t uc_data_amo_write_word_i, + input hpdcache_req_data_t uc_data_amo_write_data_i, + input hpdcache_req_be_t uc_data_amo_write_be_i, + output logic uc_core_rsp_ready_o, + input logic uc_core_rsp_valid_i, + input hpdcache_rsp_t uc_core_rsp_i, + + // Cache Management Operation (CMO) + input logic cmo_busy_i, + input logic cmo_wait_i, + output logic cmo_req_valid_o, + output hpdcache_cmoh_op_t cmo_req_op_o, + output hpdcache_req_addr_t cmo_req_addr_o, + output hpdcache_req_data_t cmo_req_wdata_o, + output hpdcache_req_sid_t cmo_req_sid_o, + output hpdcache_req_tid_t cmo_req_tid_o, + output logic cmo_req_need_rsp_o, + input logic cmo_wbuf_flush_all_i, + input logic cmo_dir_check_nline_i, + input hpdcache_set_t cmo_dir_check_nline_set_i, + input hpdcache_tag_t cmo_dir_check_nline_tag_i, + output hpdcache_way_vector_t cmo_dir_check_nline_hit_way_o, + output logic cmo_dir_check_nline_wback_o, + output logic cmo_dir_check_nline_dirty_o, + input logic cmo_dir_check_entry_i, + input hpdcache_set_t cmo_dir_check_entry_set_i, + input hpdcache_way_vector_t cmo_dir_check_entry_way_i, + output logic cmo_dir_check_entry_valid_o, + output logic cmo_dir_check_entry_wback_o, + output logic cmo_dir_check_entry_dirty_o, + output hpdcache_tag_t cmo_dir_check_entry_tag_o, + input logic cmo_dir_updt_i, + input hpdcache_set_t cmo_dir_updt_set_i, + input hpdcache_way_vector_t cmo_dir_updt_way_i, + input logic cmo_dir_updt_valid_i, + input logic cmo_dir_updt_wback_i, + input logic cmo_dir_updt_dirty_i, + input logic cmo_dir_updt_fetch_i, + input hpdcache_tag_t cmo_dir_updt_tag_i, + output logic cmo_core_rsp_ready_o, + input logic cmo_core_rsp_valid_i, + input hpdcache_rsp_t cmo_core_rsp_i, + + output logic rtab_empty_o, + output logic ctrl_empty_o, + + // Configuration signals + input logic cfg_enable_i, + input logic cfg_prefetch_updt_plru_i, + input logic cfg_rtab_single_entry_i, + input logic cfg_default_wb_i, + + // Performance events + output logic evt_cache_write_miss_o, + output logic evt_cache_read_miss_o, + output logic evt_uncached_req_o, + output logic evt_cmo_req_o, + output logic evt_write_req_o, + output logic evt_read_req_o, + output logic evt_prefetch_req_o, + output logic evt_req_on_hold_o, + output logic evt_rtab_rollback_o, + output logic evt_stall_refill_o, + output logic evt_stall_o +); + // }}} + + // Definition of internal registers + // {{{ + typedef logic [$clog2(HPDcacheCfg.u.rtabEntries)-1:0] rtab_ptr_t; + + typedef struct packed { + hpdcache_req_t req; + hpdcache_way_t way_fetch; + } rtab_entry_t; + // }}} + + // Definition of internal registers + // {{{ + logic st1_req_valid_q, st1_req_valid_d; + logic st1_req_is_error_q, st1_req_is_error_d; + hpdcache_req_t st1_req_q; + logic st1_req_rtab_q; + rtab_ptr_t st1_rtab_pop_try_ptr_q; + + logic st2_mshr_alloc_q, st2_mshr_alloc_d; + logic st2_mshr_alloc_is_prefetch_q; + logic st2_mshr_alloc_wback_q, st2_mshr_alloc_wback_d; + logic st2_mshr_alloc_need_rsp_q, st2_mshr_alloc_need_rsp_d; + hpdcache_req_addr_t st2_mshr_alloc_addr_q; + hpdcache_req_sid_t st2_mshr_alloc_sid_q; + hpdcache_req_tid_t st2_mshr_alloc_tid_q; + hpdcache_way_vector_t st2_mshr_alloc_victim_way_q; + + logic st2_flush_alloc_q, st2_flush_alloc_d; + hpdcache_nline_t st2_flush_alloc_nline_q; + hpdcache_way_vector_t st2_flush_alloc_way_q; + + logic st2_dir_updt_q, st2_dir_updt_d; + hpdcache_set_t st2_dir_updt_set_q; + hpdcache_way_vector_t st2_dir_updt_way_q; + hpdcache_tag_t st2_dir_updt_tag_q; + logic st2_dir_updt_valid_q, st2_dir_updt_valid_d; + logic st2_dir_updt_wback_q, st2_dir_updt_wback_d; + logic st2_dir_updt_dirty_q, st2_dir_updt_dirty_d; + logic st2_dir_updt_fetch_q, st2_dir_updt_fetch_d; + // }}} + + // Definition of internal signals + // {{{ + hpdcache_req_t st0_req; + hpdcache_pma_t st0_req_pma; + logic st0_req_is_error; + logic st0_req_is_uncacheable; + logic st0_req_is_load; + logic st0_req_is_store; + logic st0_req_is_amo; + logic st0_req_is_cmo_fence; + logic st0_req_is_cmo_inval; + logic st0_req_is_cmo_prefetch; + logic st0_req_cachedir_read; + logic st0_req_cachedata_read; + hpdcache_set_t st0_req_set; + hpdcache_word_t st0_req_word; + logic st0_rtab_pop_try_valid; + logic st0_rtab_pop_try_ready; + rtab_entry_t st0_rtab_pop_try_req; + rtab_ptr_t st0_rtab_pop_try_ptr; + logic st0_rtab_pop_try_error; + + logic st1_rsp_valid; + logic st1_rsp_error; + logic st1_rsp_aborted; + hpdcache_req_t st1_req; + logic st1_req_abort; + logic st1_req_cachedata_write; + logic st1_req_cachedata_write_enable; + hpdcache_pma_t st1_req_pma; + hpdcache_tag_t st1_req_tag; + hpdcache_set_t st1_req_set; + hpdcache_word_t st1_req_word; + hpdcache_nline_t st1_req_nline; + hpdcache_req_addr_t st1_req_addr; + logic st1_victim_sel; + logic st1_req_updt_sel_victim; + logic st1_req_is_uncacheable; + logic st1_req_is_load; + logic st1_req_is_store; + logic st1_req_is_amo; + logic st1_req_is_amo_lr; + logic st1_req_is_amo_sc; + logic st1_req_is_amo_swap; + logic st1_req_is_amo_add; + logic st1_req_is_amo_and; + logic st1_req_is_amo_or; + logic st1_req_is_amo_xor; + logic st1_req_is_amo_max; + logic st1_req_is_amo_maxu; + logic st1_req_is_amo_min; + logic st1_req_is_amo_minu; + logic st1_req_is_cmo_inval; + logic st1_req_is_cmo_flush; + logic st1_req_is_cmo_fence; + logic st1_req_is_cmo_prefetch; + logic st1_req_wr_wt; + logic st1_req_wr_wb; + logic st1_req_wr_auto; + logic st1_dir_hit; + logic st1_dir_hit_wback; + logic st1_dir_hit_dirty; + logic st1_dir_hit_fetch; + hpdcache_way_vector_t st1_dir_hit_way; + hpdcache_way_t st1_dir_hit_way_index; + hpdcache_tag_t st1_dir_hit_tag; + logic st1_dir_victim_unavailable; + logic st1_dir_victim_valid; + logic st1_dir_victim_wback; + logic st1_dir_victim_dirty; + hpdcache_tag_t st1_dir_victim_tag; + hpdcache_way_vector_t st1_dir_victim_way; + hpdcache_nline_t st1_victim_nline; + hpdcache_req_data_t st1_read_data; + logic st1_rtab_alloc; + logic st1_rtab_alloc_and_link; + logic st1_rtab_pop_try_commit; + logic st1_rtab_pop_try_rback; + hpdcache_rtab_deps_t st1_rtab_deps; + logic st1_rtab_check; + logic st1_rtab_check_hit; + + hpdcache_way_t refill_way_index; + + logic rtab_full; + logic rtab_fence; + + logic hpdcache_init_ready; + // }}} + + // Decoding of the request in stage 0 + // {{{ + always_comb + begin : st0_req_pma_comb + st0_req_pma = core_req_i.pma; + + // force uncacheable requests if the cache is disabled + if (!cfg_enable_i) begin + st0_req_pma.uncacheable = 1'b1; + end + + // if either WB or WT is not supported, force write-policy + if (!HPDcacheCfg.u.wtEn) begin + st0_req_pma.wr_policy_hint = HPDCACHE_WR_POLICY_WB; + end + if (!HPDcacheCfg.u.wbEn) begin + st0_req_pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + end + end + + // Select between request in the replay table or a new core requests + assign st0_req.addr_offset = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.addr_offset + : core_req_i.addr_offset; + assign st0_req.addr_tag = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.addr_tag + : core_req_i.addr_tag; + assign st0_req.wdata = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.wdata + : core_req_i.wdata; + assign st0_req.op = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.op + : core_req_i.op; + assign st0_req.be = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.be + : core_req_i.be; + assign st0_req.size = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.size + : core_req_i.size; + assign st0_req.sid = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.sid + : core_req_i.sid; + assign st0_req.tid = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.tid + : core_req_i.tid; + assign st0_req.need_rsp = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.need_rsp + : core_req_i.need_rsp; + assign st0_req.phys_indexed = st0_rtab_pop_try_valid ? 1'b1 : + core_req_i.phys_indexed; + assign st0_req.pma = st0_rtab_pop_try_valid ? st0_rtab_pop_try_req.req.pma + : st0_req_pma; + + // Check if the request from the RTAB has been tagged with an error + assign st0_req_is_error = st0_rtab_pop_try_valid & st0_rtab_pop_try_error; + + // Decode operation in stage 0 + assign st0_req_is_uncacheable = st0_req.pma.uncacheable; + assign st0_req_is_load = is_load(st0_req.op); + assign st0_req_is_store = is_store(st0_req.op); + assign st0_req_is_amo = is_amo(st0_req.op); + assign st0_req_is_cmo_fence = is_cmo_fence(st0_req.op); + assign st0_req_is_cmo_inval = is_cmo_inval(st0_req.op); + assign st0_req_is_cmo_prefetch = is_cmo_prefetch(st0_req.op); + // }}} + + // Decode operation in stage 1 + // {{{ + always_comb + begin : st1_req_pma_comb + st1_req_pma = st1_req_q.phys_indexed ? st1_req_q.pma : core_req_pma_i; + + // force uncacheable requests if the cache is disabled + if (!cfg_enable_i) begin + st1_req_pma.uncacheable = 1'b1; + end + + // if either WB or WT is not supported, force write-policy + if (!HPDcacheCfg.u.wtEn) begin + st1_req_pma.wr_policy_hint = HPDCACHE_WR_POLICY_WB; + end + if (!HPDcacheCfg.u.wbEn) begin + st1_req_pma.wr_policy_hint = HPDCACHE_WR_POLICY_WT; + end + end + + // In case of replay or physically-indexed cache, the tag and PMA come + // from stage 0. Otherwise, this information come directly from the + // requester in stage 1 + assign st1_req_tag = st1_req_q.phys_indexed ? st1_req_q.addr_tag : core_req_tag_i; + + assign st1_req.addr_offset = st1_req_q.addr_offset; + assign st1_req.addr_tag = st1_req_rtab_q ? st1_req_q.addr_tag : st1_req_tag; + assign st1_req.wdata = st1_req_q.wdata; + assign st1_req.op = st1_req_q.op; + assign st1_req.be = st1_req_q.be; + assign st1_req.size = st1_req_q.size; + assign st1_req.sid = st1_req_q.sid; + assign st1_req.tid = st1_req_q.tid; + assign st1_req.need_rsp = st1_req_q.need_rsp; + assign st1_req.phys_indexed = st1_req_q.phys_indexed; + assign st1_req.pma = st1_req_rtab_q ? st1_req_q.pma : st1_req_pma; + + // A requester can ask to abort a request it initiated on the + // previous cycle (stage 0). Useful in case of TLB miss for example + assign st1_req_abort = core_req_abort_i & ~st1_req.phys_indexed; + + assign st1_req_is_uncacheable = ~cfg_enable_i | st1_req.pma.uncacheable; + assign st1_req_is_load = is_load(st1_req.op); + assign st1_req_is_store = is_store(st1_req.op); + assign st1_req_is_amo = is_amo(st1_req.op); + assign st1_req_is_amo_lr = is_amo_lr(st1_req.op); + assign st1_req_is_amo_sc = is_amo_sc(st1_req.op); + assign st1_req_is_amo_swap = is_amo_swap(st1_req.op); + assign st1_req_is_amo_add = is_amo_add(st1_req.op); + assign st1_req_is_amo_and = is_amo_and(st1_req.op); + assign st1_req_is_amo_or = is_amo_or(st1_req.op); + assign st1_req_is_amo_xor = is_amo_xor(st1_req.op); + assign st1_req_is_amo_max = is_amo_max(st1_req.op); + assign st1_req_is_amo_maxu = is_amo_maxu(st1_req.op); + assign st1_req_is_amo_min = is_amo_min(st1_req.op); + assign st1_req_is_amo_minu = is_amo_minu(st1_req.op); + assign st1_req_is_cmo_inval = is_cmo_inval(st1_req.op); + assign st1_req_is_cmo_flush = is_cmo_flush(st1_req.op); + assign st1_req_is_cmo_fence = is_cmo_fence(st1_req.op); + assign st1_req_is_cmo_prefetch = is_cmo_prefetch(st1_req.op); + + // Decode write-policy hint + assign st1_req_wr_wt = (st1_req.pma.wr_policy_hint == HPDCACHE_WR_POLICY_WT); + assign st1_req_wr_wb = (st1_req.pma.wr_policy_hint == HPDCACHE_WR_POLICY_WB); + assign st1_req_wr_auto = (st1_req.pma.wr_policy_hint == HPDCACHE_WR_POLICY_AUTO); + // }}} + + // Cache controller protocol engine + // {{{ + hpdcache_ctrl_pe hpdcache_ctrl_pe_i( + .core_req_valid_i, + .core_req_ready_o, + .rtab_req_valid_i (st0_rtab_pop_try_valid), + .rtab_req_ready_o (st0_rtab_pop_try_ready), + .refill_req_valid_i, + .refill_req_ready_o, + + .st0_req_is_error_i (st0_req_is_error), + .st0_req_is_uncacheable_i (st0_req_is_uncacheable), + .st0_req_need_rsp_i (st0_req.need_rsp), + .st0_req_is_load_i (st0_req_is_load), + .st0_req_is_store_i (st0_req_is_store), + .st0_req_is_amo_i (st0_req_is_amo), + .st0_req_is_cmo_fence_i (st0_req_is_cmo_fence), + .st0_req_is_cmo_inval_i (st0_req_is_cmo_inval), + .st0_req_is_cmo_prefetch_i (st0_req_is_cmo_prefetch), + .st0_req_mshr_check_o (st0_mshr_check_o), + .st0_req_cachedir_read_o (st0_req_cachedir_read), + .st0_req_cachedata_read_o (st0_req_cachedata_read), + + .st1_req_valid_i (st1_req_valid_q), + .st1_req_abort_i (st1_req_abort), + .st1_req_rtab_i (st1_req_rtab_q), + .st1_req_is_error_i (st1_req_is_error_q), + .st1_req_is_uncacheable_i (st1_req_is_uncacheable), + .st1_req_need_rsp_i (st1_req.need_rsp), + .st1_req_is_load_i (st1_req_is_load), + .st1_req_is_store_i (st1_req_is_store), + .st1_req_is_amo_i (st1_req_is_amo), + .st1_req_is_cmo_inval_i (st1_req_is_cmo_inval), + .st1_req_is_cmo_flush_i (st1_req_is_cmo_flush), + .st1_req_is_cmo_fence_i (st1_req_is_cmo_fence), + .st1_req_is_cmo_prefetch_i (st1_req_is_cmo_prefetch), + .st1_req_wr_wt_i (st1_req_wr_wt), + .st1_req_wr_wb_i (st1_req_wr_wb), + .st1_req_wr_auto_i (st1_req_wr_auto), + .st1_dir_hit_wback_i (st1_dir_hit_wback), + .st1_dir_hit_dirty_i (st1_dir_hit_dirty), + .st1_dir_hit_fetch_i (st1_dir_hit_fetch), + .st1_dir_victim_unavailable_i (st1_dir_victim_unavailable), + .st1_dir_victim_valid_i (st1_dir_victim_valid), + .st1_dir_victim_wback_i (st1_dir_victim_wback), + .st1_dir_victim_dirty_i (st1_dir_victim_dirty), + .st1_req_valid_o (st1_req_valid_d), + .st1_req_is_error_o (st1_req_is_error_d), + .st1_rsp_valid_o (st1_rsp_valid), + .st1_rsp_error_o (st1_rsp_error), + .st1_rsp_aborted_o (st1_rsp_aborted), + .st1_req_cachedir_sel_victim_o (st1_victim_sel), + .st1_req_cachedir_updt_sel_victim_o (st1_req_updt_sel_victim), + .st1_req_cachedata_write_o (st1_req_cachedata_write), + .st1_req_cachedata_write_enable_o (st1_req_cachedata_write_enable), + + .st2_mshr_alloc_i (st2_mshr_alloc_q), + .st2_mshr_alloc_is_prefetch_i (st2_mshr_alloc_is_prefetch_q), + .st2_mshr_alloc_wback_i (st2_mshr_alloc_wback_q), + .st2_mshr_alloc_o (st2_mshr_alloc_d), + .st2_mshr_alloc_cs_o (st2_mshr_alloc_cs_o), + .st2_mshr_alloc_need_rsp_o (st2_mshr_alloc_need_rsp_d), + .st2_mshr_alloc_wback_o (st2_mshr_alloc_wback_d), + + .st2_dir_updt_i (st2_dir_updt_q), + .st2_dir_updt_valid_i (st2_dir_updt_valid_q), + .st2_dir_updt_wback_i (st2_dir_updt_wback_q), + .st2_dir_updt_dirty_i (st2_dir_updt_dirty_q), + .st2_dir_updt_fetch_i (st2_dir_updt_fetch_q), + .st2_dir_updt_o (st2_dir_updt_d), + .st2_dir_updt_valid_o (st2_dir_updt_valid_d), + .st2_dir_updt_wback_o (st2_dir_updt_wback_d), + .st2_dir_updt_dirty_o (st2_dir_updt_dirty_d), + .st2_dir_updt_fetch_o (st2_dir_updt_fetch_d), + + .flush_busy_i, + .st1_flush_check_hit_i (flush_check_hit_i), + .st1_flush_alloc_ready_i (flush_alloc_ready_i), + .st2_flush_alloc_i (st2_flush_alloc_q), + .st2_flush_alloc_o (st2_flush_alloc_d), + + .rtab_full_i (rtab_full), + .rtab_fence_i (rtab_fence), + .rtab_check_o (st1_rtab_check), + .rtab_check_hit_i (st1_rtab_check_hit), + .st1_rtab_alloc_o (st1_rtab_alloc), + .st1_rtab_alloc_and_link_o (st1_rtab_alloc_and_link), + .st1_rtab_commit_o (st1_rtab_pop_try_commit), + .st1_rtab_rback_o (st1_rtab_pop_try_rback), + .st1_rtab_mshr_hit_o (st1_rtab_deps.mshr_hit), + .st1_rtab_mshr_full_o (st1_rtab_deps.mshr_full), + .st1_rtab_mshr_ready_o (st1_rtab_deps.mshr_ready), + .st1_rtab_write_miss_o (st1_rtab_deps.write_miss), + .st1_rtab_wbuf_hit_o (st1_rtab_deps.wbuf_hit), + .st1_rtab_wbuf_not_ready_o (st1_rtab_deps.wbuf_not_ready), + .st1_rtab_dir_unavailable_o (st1_rtab_deps.dir_unavailable), + .st1_rtab_dir_fetch_o (st1_rtab_deps.dir_fetch), + .st1_rtab_flush_hit_o (st1_rtab_deps.flush_hit), + .st1_rtab_flush_not_ready_o (st1_rtab_deps.flush_not_ready), + + .cachedir_hit_i (cachedir_hit_o), + .cachedir_init_ready_i (hpdcache_init_ready), + + .st1_mshr_alloc_ready_i (st1_mshr_alloc_ready_i), + .st1_mshr_hit_i (st1_mshr_hit_i), + .st1_mshr_full_i (st1_mshr_alloc_full_i), + + .refill_busy_i, + .refill_core_rsp_valid_i, + + .wbuf_write_valid_o (wbuf_write_o), + .wbuf_write_ready_i, + .wbuf_read_hit_i, + .wbuf_write_uncacheable_o, + .wbuf_read_flush_hit_o, + + .uc_busy_i, + .uc_req_valid_o, + .uc_core_rsp_ready_o, + + .cmo_busy_i, + .cmo_wait_i, + .cmo_req_valid_o, + .cmo_core_rsp_ready_o, + + .cfg_prefetch_updt_plru_i, + .cfg_default_wb_i, + + .evt_cache_write_miss_o, + .evt_cache_read_miss_o, + .evt_uncached_req_o, + .evt_cmo_req_o, + .evt_write_req_o, + .evt_read_req_o, + .evt_prefetch_req_o, + .evt_req_on_hold_o, + .evt_rtab_rollback_o, + .evt_stall_refill_o, + .evt_stall_o + ); + + // pipeline is empty + assign ctrl_empty_o = ~(st1_req_valid_q | st2_mshr_alloc_q | st2_dir_updt_q); + + // no available victim cacheline (all pre-allocated for replacement) + assign st1_dir_victim_unavailable = ~(|st1_dir_victim_way); + + // }}} + + // Replay table + // {{{ + rtab_entry_t st1_alloc_rtab; + + hpdcache_1hot_to_binary #( + .N (HPDcacheCfg.u.ways) + ) dir_hit_way_encoder_i( + .val_i (st1_dir_hit_way), + .val_o (st1_dir_hit_way_index) + ); + + hpdcache_1hot_to_binary #( + .N (HPDcacheCfg.u.ways) + ) refill_way_encoder_i( + .val_i (refill_way_i), + .val_o (refill_way_index) + ); + + assign st1_alloc_rtab = '{ + req : st1_req, + way_fetch : st1_dir_hit_way_index + }; + + hpdcache_rtab #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_way_t (hpdcache_way_t), + .hpdcache_req_addr_t (hpdcache_req_addr_t), + .rtab_ptr_t (rtab_ptr_t), + .rtab_entry_t (rtab_entry_t) + ) hpdcache_rtab_i( + .clk_i, + .rst_ni, + + .empty_o (rtab_empty_o), + .full_o (rtab_full), + .fence_o (rtab_fence), + + .check_i (st1_rtab_check), + .check_nline_i (st1_req_nline), + .check_hit_o (st1_rtab_check_hit), + + .alloc_i (st1_rtab_alloc), + .alloc_and_link_i (st1_rtab_alloc_and_link), + .alloc_req_i (st1_alloc_rtab), + .alloc_deps_i (st1_rtab_deps), + + .pop_try_valid_o (st0_rtab_pop_try_valid), + .pop_try_i (st0_rtab_pop_try_ready), + .pop_try_req_o (st0_rtab_pop_try_req), + .pop_try_ptr_o (st0_rtab_pop_try_ptr), + .pop_try_error_o (st0_rtab_pop_try_error), + + .pop_commit_i (st1_rtab_pop_try_commit), + .pop_commit_ptr_i (st1_rtab_pop_try_ptr_q), + + .pop_rback_i (st1_rtab_pop_try_rback), + .pop_rback_ptr_i (st1_rtab_pop_try_ptr_q), + + .wbuf_addr_o (wbuf_rtab_addr_o), + .wbuf_is_read_o (wbuf_rtab_is_read_o), + .wbuf_hit_open_i (wbuf_rtab_hit_open_i), + .wbuf_hit_pend_i (wbuf_rtab_hit_pend_i), + .wbuf_hit_sent_i (wbuf_rtab_hit_sent_i), + .wbuf_not_ready_i (wbuf_rtab_not_ready_i), + + .miss_ready_i (st1_mshr_alloc_ready_i), + + .refill_i (refill_updt_rtab_i), + .refill_is_error_i, + .refill_nline_i, + .refill_way_index_i (refill_way_index), + + .flush_ack_i (flush_ack_i), + .flush_ack_nline_i (flush_ack_nline_i), + .flush_ready_i (flush_alloc_ready_i), + + .cfg_single_entry_i (cfg_rtab_single_entry_i) + ); + // }}} + + // Pipeline stage 1 registers + // {{{ + always_ff @(posedge clk_i) + begin : st1_req_payload_ff + if (core_req_ready_o | st0_rtab_pop_try_ready) begin + st1_req_q <= st0_req; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin : st1_req_valid_ff + if (!rst_ni) begin + st1_req_valid_q <= 1'b0; + st1_req_is_error_q <= 1'b0; + st1_req_rtab_q <= 1'b0; + st1_rtab_pop_try_ptr_q <= '0; + end else begin + st1_req_valid_q <= st1_req_valid_d; + st1_req_is_error_q <= st1_req_is_error_d; + if (core_req_ready_o | st0_rtab_pop_try_ready) begin + st1_req_rtab_q <= st0_rtab_pop_try_ready; + if (st0_rtab_pop_try_ready) begin + st1_rtab_pop_try_ptr_q <= st0_rtab_pop_try_ptr; + end + end + end + end + // }}} + + // Pipeline stage 2 registers + // {{{ + always_ff @(posedge clk_i) + begin : st2_metadata_ff + if (st2_mshr_alloc_d) begin + st2_mshr_alloc_need_rsp_q <= st2_mshr_alloc_need_rsp_d; + st2_mshr_alloc_addr_q <= st1_req_addr; + st2_mshr_alloc_sid_q <= st1_req.sid; + st2_mshr_alloc_tid_q <= st1_req.tid; + st2_mshr_alloc_is_prefetch_q <= st1_req_is_cmo_prefetch; + st2_mshr_alloc_wback_q <= st2_mshr_alloc_wback_d; + st2_mshr_alloc_victim_way_q <= st1_dir_victim_way; + end + + if (st2_flush_alloc_d) begin + st2_flush_alloc_nline_q <= st1_dir_hit ? st1_req_nline : st1_victim_nline; + st2_flush_alloc_way_q <= st1_dir_hit ? st1_dir_hit_way : st1_dir_victim_way; + end + + if (st2_dir_updt_d) begin + st2_dir_updt_tag_q <= st1_dir_hit ? st1_dir_hit_tag : st1_dir_victim_tag; + st2_dir_updt_set_q <= st1_req_set; + st2_dir_updt_way_q <= st1_dir_hit ? st1_dir_hit_way : st1_dir_victim_way; + st2_dir_updt_valid_q <= st2_dir_updt_valid_d; + st2_dir_updt_wback_q <= st2_dir_updt_wback_d; + st2_dir_updt_dirty_q <= st2_dir_updt_dirty_d; + st2_dir_updt_fetch_q <= st2_dir_updt_fetch_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin : st2_valid_ff + if (!rst_ni) begin + st2_mshr_alloc_q <= 1'b0; + st2_flush_alloc_q <= 1'b0; + st2_dir_updt_q <= 1'b0; + end else begin + st2_mshr_alloc_q <= st2_mshr_alloc_d; + st2_flush_alloc_q <= st2_flush_alloc_d; + st2_dir_updt_q <= st2_dir_updt_d; + end + end + // }}} + + // Controller for the HPDcache directory and data memory arrays + // {{{ + assign st0_req_set = st0_req.addr_offset[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.setWidth]; + assign st0_req_word = st0_req.addr_offset[HPDcacheCfg.wordByteIdxWidth +: + HPDcacheCfg.clWordIdxWidth]; + + assign st1_req_set = st1_req.addr_offset[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.setWidth]; + assign st1_req_word = st1_req.addr_offset[HPDcacheCfg.wordByteIdxWidth +: + HPDcacheCfg.clWordIdxWidth]; + assign st1_req_addr = {st1_req.addr_tag, st1_req.addr_offset}; + assign st1_req_nline = st1_req_addr[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.nlineWidth]; + + assign st1_victim_nline = {st1_dir_victim_tag, st1_req_set}; + + hpdcache_memctrl #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t), + .hpdcache_dir_entry_t (hpdcache_dir_entry_t), + .hpdcache_data_word_t (hpdcache_data_word_t), + .hpdcache_data_be_t (hpdcache_data_be_t), + .hpdcache_req_data_t (hpdcache_req_data_t), + .hpdcache_req_be_t (hpdcache_req_be_t), + .hpdcache_access_data_t (hpdcache_access_data_t), + .hpdcache_access_be_t (hpdcache_access_be_t) + ) hpdcache_memctrl_i( + .clk_i, + .rst_ni, + + .ready_o (hpdcache_init_ready), + + .dir_match_i (st0_req_cachedir_read), + .dir_match_set_i (st0_req_set), + .dir_match_tag_i (st1_req.addr_tag), + .dir_updt_sel_victim_i (st1_req_updt_sel_victim), + .dir_hit_way_o (st1_dir_hit_way), + .dir_hit_tag_o (st1_dir_hit_tag), + .dir_hit_wback_o (st1_dir_hit_wback), + .dir_hit_dirty_o (st1_dir_hit_dirty), + .dir_hit_fetch_o (st1_dir_hit_fetch), + + .dir_updt_i (st2_dir_updt_q), + .dir_updt_set_i (st2_dir_updt_set_q), + .dir_updt_way_i (st2_dir_updt_way_q), + .dir_updt_tag_i (st2_dir_updt_tag_q), + .dir_updt_valid_i (st2_dir_updt_valid_q), + .dir_updt_wback_i (st2_dir_updt_wback_q), + .dir_updt_dirty_i (st2_dir_updt_dirty_q), + .dir_updt_fetch_i (st2_dir_updt_fetch_q), + + .dir_amo_match_i (uc_dir_amo_match_i), + .dir_amo_match_set_i (uc_dir_amo_match_set_i), + .dir_amo_match_tag_i (uc_dir_amo_match_tag_i), + .dir_amo_updt_sel_victim_i (uc_dir_amo_updt_sel_victim_i), + .dir_amo_hit_way_o (uc_dir_amo_hit_way_o), + + .dir_refill_i (refill_write_dir_i), + .dir_refill_set_i (refill_set_i), + .dir_refill_way_i (refill_way_i), + .dir_refill_entry_i (refill_dir_entry_i), + .dir_refill_updt_sel_victim_i (refill_updt_sel_victim_i), + + .dir_victim_sel_i (st1_victim_sel), + .dir_victim_set_i (st1_req_set), + .dir_victim_valid_o (st1_dir_victim_valid), + .dir_victim_wback_o (st1_dir_victim_wback), + .dir_victim_dirty_o (st1_dir_victim_dirty), + .dir_victim_tag_o (st1_dir_victim_tag), + .dir_victim_way_o (st1_dir_victim_way), + + .dir_inval_check_i (inval_check_dir_i), + .dir_inval_nline_i (inval_nline_i), + .dir_inval_write_i (inval_write_dir_i), + .dir_inval_hit_o (inval_hit_o), + + .dir_cmo_check_nline_i (cmo_dir_check_nline_i), + .dir_cmo_check_nline_set_i (cmo_dir_check_nline_set_i), + .dir_cmo_check_nline_tag_i (cmo_dir_check_nline_tag_i), + .dir_cmo_check_nline_hit_way_o (cmo_dir_check_nline_hit_way_o), + .dir_cmo_check_nline_wback_o (cmo_dir_check_nline_wback_o), + .dir_cmo_check_nline_dirty_o (cmo_dir_check_nline_dirty_o), + + .dir_cmo_check_entry_i (cmo_dir_check_entry_i), + .dir_cmo_check_entry_set_i (cmo_dir_check_entry_set_i), + .dir_cmo_check_entry_way_i (cmo_dir_check_entry_way_i), + .dir_cmo_check_entry_valid_o (cmo_dir_check_entry_valid_o), + .dir_cmo_check_entry_wback_o (cmo_dir_check_entry_wback_o), + .dir_cmo_check_entry_dirty_o (cmo_dir_check_entry_dirty_o), + .dir_cmo_check_entry_tag_o (cmo_dir_check_entry_tag_o), + + .dir_cmo_updt_i (cmo_dir_updt_i), + .dir_cmo_updt_set_i (cmo_dir_updt_set_i), + .dir_cmo_updt_way_i (cmo_dir_updt_way_i), + .dir_cmo_updt_tag_i (cmo_dir_updt_tag_i), + .dir_cmo_updt_valid_i (cmo_dir_updt_valid_i), + .dir_cmo_updt_wback_i (cmo_dir_updt_wback_i), + .dir_cmo_updt_dirty_i (cmo_dir_updt_dirty_i), + .dir_cmo_updt_fetch_i (cmo_dir_updt_fetch_i), + + .data_req_read_i (st0_req_cachedata_read), + .data_req_read_set_i (st0_req_set), + .data_req_read_size_i (st0_req.size), + .data_req_read_word_i (st0_req_word), + .data_req_read_data_o (st1_read_data), + + .data_req_write_i (st1_req_cachedata_write), + .data_req_write_enable_i (st1_req_cachedata_write_enable), + .data_req_write_set_i (st1_req_set), + .data_req_write_size_i (st1_req.size), + .data_req_write_word_i (st1_req_word), + .data_req_write_data_i (st1_req.wdata), + .data_req_write_be_i (st1_req.be), + + .data_amo_write_i (uc_data_amo_write_i), + .data_amo_write_enable_i (uc_data_amo_write_enable_i), + .data_amo_write_set_i (uc_data_amo_write_set_i), + .data_amo_write_size_i (uc_data_amo_write_size_i), + .data_amo_write_word_i (uc_data_amo_write_word_i), + .data_amo_write_data_i (uc_data_amo_write_data_i), + .data_amo_write_be_i (uc_data_amo_write_be_i), + + .data_flush_read_i (flush_data_read_i), + .data_flush_read_set_i (flush_data_read_set_i), + .data_flush_read_way_i (flush_data_read_way_i), + .data_flush_read_word_i (flush_data_read_word_i), + .data_flush_read_data_o (flush_data_read_data_o), + + .data_refill_i (refill_write_data_i), + .data_refill_set_i (refill_set_i), + .data_refill_way_i (refill_way_i), + .data_refill_word_i (refill_word_i), + .data_refill_data_i (refill_data_i) + ); + + assign st1_dir_hit = |st1_dir_hit_way; + + assign cachedir_hit_o = st1_dir_hit; + // }}} + + // Write buffer outputs + // {{{ + assign wbuf_write_addr_o = st1_req_addr; + assign wbuf_write_data_o = st1_req.wdata; + assign wbuf_write_be_o = st1_req.be; + assign wbuf_flush_all_o = cmo_wbuf_flush_all_i | uc_wbuf_flush_all_i | wbuf_flush_i; + // }}} + + // Miss handler outputs + // {{{ + assign st0_mshr_check_offset_o = st0_req.addr_offset; + assign st1_mshr_check_nline_o = st1_req_nline; + assign st2_mshr_alloc_o = st2_mshr_alloc_q; + assign st2_mshr_alloc_nline_o = st2_mshr_alloc_addr_q[HPDcacheCfg.clOffsetWidth +: + HPDcacheCfg.nlineWidth]; + assign st2_mshr_alloc_tid_o = st2_mshr_alloc_tid_q; + assign st2_mshr_alloc_sid_o = st2_mshr_alloc_sid_q; + assign st2_mshr_alloc_word_o = st2_mshr_alloc_addr_q[HPDcacheCfg.wordByteIdxWidth +: + HPDcacheCfg.clWordIdxWidth]; + assign st2_mshr_alloc_victim_way_o = st2_mshr_alloc_victim_way_q; + assign st2_mshr_alloc_need_rsp_o = st2_mshr_alloc_need_rsp_q; + assign st2_mshr_alloc_is_prefetch_o = st2_mshr_alloc_is_prefetch_q; + assign st2_mshr_alloc_wback_o = st2_mshr_alloc_wback_q; + // }}} + + // Uncacheable request handler outputs + // {{{ + assign uc_lrsc_snoop_o = st1_req_valid_q & st1_req_is_store, + uc_lrsc_snoop_addr_o = st1_req_addr, + uc_lrsc_snoop_size_o = st1_req.size, + uc_req_addr_o = st1_req_addr, + uc_req_size_o = st1_req.size, + uc_req_data_o = st1_req.wdata, + uc_req_be_o = st1_req.be, + uc_req_uc_o = st1_req_is_uncacheable, + uc_req_sid_o = st1_req.sid, + uc_req_tid_o = st1_req.tid, + uc_req_need_rsp_o = st1_req.need_rsp, + uc_req_op_o.is_ld = st1_req_is_load, + uc_req_op_o.is_st = st1_req_is_store, + uc_req_op_o.is_amo_lr = st1_req_is_amo_lr, + uc_req_op_o.is_amo_sc = st1_req_is_amo_sc, + uc_req_op_o.is_amo_swap = st1_req_is_amo_swap, + uc_req_op_o.is_amo_add = st1_req_is_amo_add, + uc_req_op_o.is_amo_and = st1_req_is_amo_and, + uc_req_op_o.is_amo_or = st1_req_is_amo_or, + uc_req_op_o.is_amo_xor = st1_req_is_amo_xor, + uc_req_op_o.is_amo_max = st1_req_is_amo_max, + uc_req_op_o.is_amo_maxu = st1_req_is_amo_maxu, + uc_req_op_o.is_amo_min = st1_req_is_amo_min, + uc_req_op_o.is_amo_minu = st1_req_is_amo_minu; + // }}} + + // CMO request handler outputs + // {{{ + assign cmo_req_addr_o = st1_req_addr; + assign cmo_req_wdata_o = st1_req.wdata; + assign cmo_req_sid_o = st1_req.sid; + assign cmo_req_tid_o = st1_req.tid; + assign cmo_req_need_rsp_o = st1_req.need_rsp; + assign cmo_req_op_o.is_fence = st1_req_is_cmo_fence; + assign cmo_req_op_o.is_inval_by_nline = st1_req_is_cmo_inval & + is_cmo_inval_by_nline(st1_req.op); + assign cmo_req_op_o.is_inval_all = st1_req_is_cmo_inval & + is_cmo_inval_all(st1_req.op); + assign cmo_req_op_o.is_flush_by_nline = st1_req_is_cmo_flush & + is_cmo_flush_by_nline(st1_req.op); + assign cmo_req_op_o.is_flush_all = st1_req_is_cmo_flush & + is_cmo_flush_all(st1_req.op); + assign cmo_req_op_o.is_flush_inval_by_nline = st1_req_is_cmo_flush & + is_cmo_flush_inval_by_nline(st1_req.op); + assign cmo_req_op_o.is_flush_inval_all = st1_req_is_cmo_flush & + is_cmo_flush_inval_all(st1_req.op); + // }}} + + // Flush controller outputs + // {{{ + assign flush_check_nline_o = st1_req_nline; + assign flush_alloc_o = st2_flush_alloc_q; + assign flush_alloc_nline_o = st2_flush_alloc_nline_q; + assign flush_alloc_way_o = st2_flush_alloc_way_q; + // }}} + + // Control of the response to the core + // {{{ + assign core_rsp_valid_o = refill_core_rsp_valid_i | + (uc_core_rsp_valid_i & uc_core_rsp_ready_o) | + (cmo_core_rsp_valid_i & cmo_core_rsp_ready_o) | + st1_rsp_valid; + assign core_rsp_o.rdata = (refill_core_rsp_valid_i ? refill_core_rsp_i.rdata : + (cmo_core_rsp_valid_i ? cmo_core_rsp_i.rdata : + (uc_core_rsp_valid_i ? uc_core_rsp_i.rdata : st1_read_data))); + assign core_rsp_o.sid = (refill_core_rsp_valid_i ? refill_core_rsp_i.sid : + (cmo_core_rsp_valid_i ? cmo_core_rsp_i.sid : + (uc_core_rsp_valid_i ? uc_core_rsp_i.sid : st1_req.sid))); + assign core_rsp_o.tid = (refill_core_rsp_valid_i ? refill_core_rsp_i.tid : + (cmo_core_rsp_valid_i ? cmo_core_rsp_i.tid : + (uc_core_rsp_valid_i ? uc_core_rsp_i.tid : st1_req.tid))); + assign core_rsp_o.error = (refill_core_rsp_valid_i ? refill_core_rsp_i.error : + (cmo_core_rsp_valid_i ? cmo_core_rsp_i.error : + (uc_core_rsp_valid_i ? uc_core_rsp_i.error : st1_rsp_error))); + assign core_rsp_o.aborted = st1_rsp_aborted; + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + // Check that the cache controller is being used by one and only one among a core request, the + // RTAB or the miss handler. + assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot0({core_req_ready_o, st0_rtab_pop_try_ready, refill_req_ready_o})) else + $error("ctrl: only one request can be served per cycle"); + + // Check that requests have a valid size field. The check is not necessary for the fence, + // invalidation and flush CMOs because these requests do not use the size field. + property prop_core_req_size_max; + @(posedge clk_i) disable iff (!rst_ni) ( + core_req_valid_i && core_req_ready_o && + !(is_cmo_fence(core_req_i.op) || + is_cmo_inval(core_req_i.op) || + is_cmo_flush(core_req_i.op)) + ) |-> ( + (2**core_req_i.size) <= HPDcacheCfg.reqDataBytes + ); + endproperty + + assert property (prop_core_req_size_max) else + $error("ctrl: bad SIZE for request"); + + // Check that stores and AMOs requests have a valid Byte Enable field. In particular, check + // that it is aligned with respect to the address + function automatic bit check_is_be_aligned( + input hpdcache_req_offset_t req_offset, + input hpdcache_req_be_t req_be + ); + int offset = int'(req_offset) % HPDcacheCfg.reqDataBytes; + return (((req_be >> offset) << offset) == req_be); + endfunction + + property prop_core_req_be_align; + @(posedge clk_i) disable iff (!rst_ni) ( + core_req_valid_i && core_req_ready_o && + (is_store(core_req_i.op) || is_amo(core_req_i.op)) + ) |-> ( + check_is_be_aligned(core_req_i.addr_offset, core_req_i.be) + ); + endproperty + + assert property (prop_core_req_be_align) else + $error("ctrl: bad BE alignment for request"); + + // Check that only one cache victim way is required when reserving a slot in the MSHR + assert property (@(posedge clk_i) disable iff (!rst_ni) + st2_mshr_alloc_q |-> $onehot(st2_mshr_alloc_victim_way_q)) else + $error("ctrl: no victim way selected during MSHR allocation"); +`endif + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv new file mode 100644 index 0000000000..ed9e16694b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv @@ -0,0 +1,1036 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache Control Protocol Engine + * History : + */ +module hpdcache_ctrl_pe + // Ports + // {{{ +( + // Requests + // {{{ + input logic core_req_valid_i, + output logic core_req_ready_o, + + input logic rtab_req_valid_i, + output logic rtab_req_ready_o, + + input logic refill_req_valid_i, + output logic refill_req_ready_o, + // }}} + + // Pipeline stage 0 + // {{{ + input logic st0_req_is_error_i, + input logic st0_req_is_uncacheable_i, + input logic st0_req_need_rsp_i, + input logic st0_req_is_load_i, + input logic st0_req_is_store_i, + input logic st0_req_is_amo_i, + input logic st0_req_is_cmo_fence_i, + input logic st0_req_is_cmo_inval_i, + input logic st0_req_is_cmo_prefetch_i, + output logic st0_req_mshr_check_o, + output logic st0_req_cachedir_read_o, + output logic st0_req_cachedata_read_o, + // }}} + + // Pipeline stage 1 + // {{{ + input logic st1_req_valid_i, + input logic st1_req_abort_i, + input logic st1_req_rtab_i, + input logic st1_req_is_error_i, + input logic st1_req_is_uncacheable_i, + input logic st1_req_need_rsp_i, + input logic st1_req_is_load_i, + input logic st1_req_is_store_i, + input logic st1_req_is_amo_i, + input logic st1_req_is_cmo_inval_i, + input logic st1_req_is_cmo_flush_i, + input logic st1_req_is_cmo_fence_i, + input logic st1_req_is_cmo_prefetch_i, + input logic st1_req_wr_wt_i, + input logic st1_req_wr_wb_i, + input logic st1_req_wr_auto_i, + input logic st1_dir_hit_wback_i, + input logic st1_dir_hit_dirty_i, + input logic st1_dir_hit_fetch_i, + input logic st1_dir_victim_unavailable_i, + input logic st1_dir_victim_valid_i, + input logic st1_dir_victim_wback_i, + input logic st1_dir_victim_dirty_i, + output logic st1_req_valid_o, + output logic st1_req_is_error_o, + output logic st1_rsp_valid_o, + output logic st1_rsp_error_o, + output logic st1_rsp_aborted_o, + output logic st1_req_cachedir_sel_victim_o, + output logic st1_req_cachedir_updt_sel_victim_o, + output logic st1_req_cachedata_write_o, + output logic st1_req_cachedata_write_enable_o, + input logic st1_mshr_alloc_ready_i, + input logic st1_mshr_hit_i, + input logic st1_mshr_full_i, + // }}} + + // Pipeline stage 2 + // {{{ + input logic st2_mshr_alloc_i, + input logic st2_mshr_alloc_is_prefetch_i, + input logic st2_mshr_alloc_wback_i, + output logic st2_mshr_alloc_o, + output logic st2_mshr_alloc_cs_o, + output logic st2_mshr_alloc_need_rsp_o, + output logic st2_mshr_alloc_wback_o, + + input logic st2_dir_updt_i, + input logic st2_dir_updt_valid_i, + input logic st2_dir_updt_wback_i, + input logic st2_dir_updt_dirty_i, + input logic st2_dir_updt_fetch_i, + output logic st2_dir_updt_o, + output logic st2_dir_updt_valid_o, + output logic st2_dir_updt_wback_o, + output logic st2_dir_updt_dirty_o, + output logic st2_dir_updt_fetch_o, + // }}} + + // Replay + // {{{ + input logic rtab_full_i, + input logic rtab_fence_i, + output logic rtab_check_o, + input logic rtab_check_hit_i, + output logic st1_rtab_alloc_o, + output logic st1_rtab_alloc_and_link_o, + output logic st1_rtab_commit_o, + output logic st1_rtab_rback_o, + output logic st1_rtab_mshr_hit_o, + output logic st1_rtab_mshr_full_o, + output logic st1_rtab_mshr_ready_o, + output logic st1_rtab_write_miss_o, + output logic st1_rtab_wbuf_hit_o, + output logic st1_rtab_wbuf_not_ready_o, + output logic st1_rtab_dir_unavailable_o, + output logic st1_rtab_dir_fetch_o, + output logic st1_rtab_flush_hit_o, + output logic st1_rtab_flush_not_ready_o, + // }}} + + // Cache directory + // {{{ + input logic cachedir_hit_i, + input logic cachedir_init_ready_i, + // }}} + + // Refill interface + // {{{ + input logic refill_busy_i, + input logic refill_core_rsp_valid_i, + // }}} + + // Write buffer + // {{{ + input logic wbuf_write_ready_i, + input logic wbuf_read_hit_i, + output logic wbuf_write_valid_o, + output logic wbuf_write_uncacheable_o, + output logic wbuf_read_flush_hit_o, + // }}} + + // Flush controller + input logic flush_busy_i, + input logic st1_flush_check_hit_i, + input logic st1_flush_alloc_ready_i, + input logic st2_flush_alloc_i, + output logic st2_flush_alloc_o, + + // Uncacheable request handler + // {{{ + input logic uc_busy_i, + output logic uc_req_valid_o, + output logic uc_core_rsp_ready_o, + // }}} + + // Cache Management Operation (CMO) + // {{{ + input logic cmo_busy_i, + input logic cmo_wait_i, + output logic cmo_req_valid_o, + output logic cmo_core_rsp_ready_o, + // }}} + + // Configuration + // {{{ + input logic cfg_prefetch_updt_plru_i, + input logic cfg_default_wb_i, + // }}} + + // Performance events + // {{{ + output logic evt_cache_write_miss_o, + output logic evt_cache_read_miss_o, + output logic evt_uncached_req_o, + output logic evt_cmo_req_o, + output logic evt_write_req_o, + output logic evt_read_req_o, + output logic evt_prefetch_req_o, + output logic evt_req_on_hold_o, + output logic evt_rtab_rollback_o, + output logic evt_stall_refill_o, + output logic evt_stall_o + // }}} +); + // }}} + + // Definition of internal signals + // {{{ + logic st1_fence; + logic st1_rtab_alloc, st1_rtab_alloc_and_link; + // }}} + + // Global control signals + // {{{ + + // Determine if the new request is a "fence". Here, fence instructions are + // considered those that need to be executed in program order + // (irrespectively of addresses). This means that all memory operations + // arrived before the "fence" instruction need to be finished, and only + // then the "fence" instruction is executed. In the same manner, all + // instructions following the "fence" need to wait the completion of this + // last before being executed. + assign st1_fence = st1_req_is_uncacheable_i | + st1_req_is_cmo_fence_i | + st1_req_is_cmo_inval_i | + st1_req_is_cmo_flush_i; + + // Trigger an event signal when a new request cannot consumed + assign evt_stall_o = core_req_valid_i & ~core_req_ready_o; + // }}} + + // Arbitration of responses to the core + // {{{ + assign uc_core_rsp_ready_o = ~refill_core_rsp_valid_i; + assign cmo_core_rsp_ready_o = ~refill_core_rsp_valid_i; + // }}} + + // Replay logic + // {{{ + // Replay table allocation + assign st1_rtab_alloc_o = st1_rtab_alloc & ~st1_req_rtab_i, + st1_rtab_alloc_and_link_o = st1_rtab_alloc_and_link, + st1_rtab_rback_o = st1_rtab_alloc & st1_req_rtab_i; + + // Performance event + assign evt_req_on_hold_o = st1_rtab_alloc | st1_rtab_alloc_and_link, + evt_rtab_rollback_o = st1_rtab_rback_o; + // }}} + + // Data-cache control lines + // {{{ + always_comb + begin : hpdcache_ctrl_comb + automatic logic nop; + automatic logic st1_nop; // Do not consume a request in stage 0 because of stage 1 hazard + automatic logic st2_nop; // Do not consume a request in stage 0 because of stage 2 haward + automatic logic st1_req_is_cacheable_store; + + + uc_req_valid_o = 1'b0; + + cmo_req_valid_o = 1'b0; + + wbuf_write_valid_o = 1'b0; + wbuf_read_flush_hit_o = 1'b0; + wbuf_write_uncacheable_o = 1'b0; // unused + + core_req_ready_o = 1'b0; + rtab_req_ready_o = 1'b0; + refill_req_ready_o = 1'b0; + + st0_req_mshr_check_o = 1'b0; + st0_req_cachedir_read_o = 1'b0; + st0_req_cachedata_read_o = 1'b0; + + st1_req_valid_o = st1_req_valid_i; + st1_req_is_error_o = st1_req_is_error_i; + st1_req_is_cacheable_store = 1'b0; + st1_nop = 1'b0; + st1_req_cachedata_write_o = 1'b0; + st1_req_cachedata_write_enable_o = 1'b0; + st1_req_cachedir_sel_victim_o = 1'b0; + st1_req_cachedir_updt_sel_victim_o = 1'b0; + st1_rsp_valid_o = 1'b0; + st1_rsp_error_o = 1'b0; + st1_rsp_aborted_o = 1'b0; + + st2_mshr_alloc_o = st2_mshr_alloc_i; + st2_mshr_alloc_cs_o = 1'b0; + st2_mshr_alloc_need_rsp_o = 1'b0; + st2_mshr_alloc_wback_o = st2_mshr_alloc_wback_i; + + st2_flush_alloc_o = st2_flush_alloc_i; + + st2_dir_updt_o = st2_dir_updt_i; + st2_dir_updt_valid_o = st2_dir_updt_valid_i; + st2_dir_updt_wback_o = st2_dir_updt_wback_i; + st2_dir_updt_dirty_o = st2_dir_updt_dirty_i; + st2_dir_updt_fetch_o = st2_dir_updt_fetch_i; + + st2_nop = 1'b0; + + nop = 1'b0; + + rtab_check_o = 1'b0; + st1_rtab_alloc = 1'b0; + st1_rtab_alloc_and_link = 1'b0; + st1_rtab_commit_o = 1'b0; + st1_rtab_mshr_hit_o = 1'b0; + st1_rtab_mshr_full_o = 1'b0; + st1_rtab_mshr_ready_o = 1'b0; + st1_rtab_write_miss_o = 1'b0; + st1_rtab_wbuf_hit_o = 1'b0; + st1_rtab_wbuf_not_ready_o = 1'b0; + st1_rtab_dir_unavailable_o = 1'b0; + st1_rtab_dir_fetch_o = 1'b0; + st1_rtab_flush_hit_o = 1'b0; + st1_rtab_flush_not_ready_o = 1'b0; + + evt_cache_write_miss_o = 1'b0; + evt_cache_read_miss_o = 1'b0; + evt_uncached_req_o = 1'b0; + evt_cmo_req_o = 1'b0; + evt_write_req_o = 1'b0; + evt_read_req_o = 1'b0; + evt_prefetch_req_o = 1'b0; + evt_stall_refill_o = 1'b0; + + // Wait for the cache to be initialized + // {{{ + if (!cachedir_init_ready_i) begin + // initialization of the cache RAMs + end + // }}} + + // Refilling the cache + // {{{ + else if (refill_busy_i) begin + // miss handler has the control of the cache pipeline + evt_stall_refill_o = core_req_valid_i; + end + // }}} + + // Flush controller reading the cache + // {{{ + else if (flush_busy_i) begin + // flush controller has the control of the cache pipeline + end + // }}} + + // Normal pipeline operation + // {{{ + else begin + // Stage 2 request pending + // {{{ + // Allocate an entry in the MSHR + if (st2_mshr_alloc_i) begin + // Reset mshr alloc request + st2_mshr_alloc_o = 1'b0; + + // Enable the MSHR + st2_mshr_alloc_cs_o = 1'b1; + + // Introduce a NOP in the next cycle to prevent a hazard on the MSHR + st2_nop = 1'b1; + + // Performance event + evt_cache_read_miss_o = ~st2_mshr_alloc_is_prefetch_i; + evt_read_req_o = ~st2_mshr_alloc_is_prefetch_i; + evt_prefetch_req_o = st2_mshr_alloc_is_prefetch_i; + end + + // Flush a cacheline + if (st2_flush_alloc_i) begin + // Reset cache directory update request + st2_flush_alloc_o = 1'b0; + + // Introduce a NOP in the next cycle to prevent a hazard on the cache data + st2_nop = 1'b1; + end + + // Update the cache directory + if (st2_dir_updt_i) begin + // Reset cache directory update request + st2_dir_updt_o = 1'b0; + + // Introduce a NOP in the next cycle to prevent a hazard on the cache dir + st2_nop = 1'b1; + end + // }}} + + // Stage 1 request pending + // {{{ + if (st1_req_valid_i) begin + // Check if the request in stage 1 has a conflict with one of the + // request in the replay table. + rtab_check_o = ~st1_req_rtab_i & ~st1_fence; + + // Check if the current request is aborted. If so, respond to the + // core (when need_rsp is set) and set the aborted flag + if (st1_req_abort_i && !st1_req_rtab_i) begin + st1_rsp_valid_o = st1_req_need_rsp_i; + st1_rsp_aborted_o = 1'b1; + end + + else if (st1_req_is_error_i) begin + st1_rtab_commit_o = st1_req_rtab_i; + st1_rsp_valid_o = st1_req_need_rsp_i; + st1_rsp_error_o = st1_req_need_rsp_i; + + // Performance event + evt_write_req_o = st1_req_is_store_i; + end + + // Allocate a new entry in the replay table in case of conflict with + // an on-hold request + else if (rtab_check_o && rtab_check_hit_i) begin + st1_rtab_alloc_and_link = 1'b1; + + st1_nop = 1'b1; + end + + // CMO fence or invalidate + // {{{ + else if (st1_req_is_cmo_inval_i || + st1_req_is_cmo_flush_i || + st1_req_is_cmo_fence_i) + begin + cmo_req_valid_o = 1'b1; + st1_nop = 1'b1; + + // Performance event + evt_cmo_req_o = 1'b1; + end + // }}} + + // Uncacheable load, store or AMO request + // {{{ + else if (st1_req_is_uncacheable_i) begin + uc_req_valid_o = 1'b1; + st1_nop = 1'b1; + + // Performance event + evt_uncached_req_o = 1'b1; + end + // }}} + + // Cacheable request + // {{{ + else begin + // AMO cacheable request + // {{{ + if (st1_req_is_amo_i) begin + // Flush required but the controller is not ready + if (cachedir_hit_i && st1_dir_hit_dirty_i && !st1_flush_alloc_ready_i) + begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_not_ready_o = 1'b1; + st1_nop = 1'b1; + end + + // Process the AMO request + else begin + uc_req_valid_o = 1'b1; + st1_nop = 1'b1; + + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + if (cachedir_hit_i) begin + // When the hit cacheline is dirty, flush its data to the memory + st2_flush_alloc_o = st1_dir_hit_dirty_i; + + // Update the directory: an AMO request clears the dirty bit + // because it triggers a flush of the cacheline before actually + // executing the AMO. + // An AMO does not set the dirty bit because it is always forwarded + // to the memory. Then the local copy is updated with respect + // to the old data from the memory. + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = 1'b1; + st2_dir_updt_wback_o = st1_dir_hit_wback_i; + st2_dir_updt_dirty_o = 1'b0; + + // If the cacheline has been pre-allocated for a pending miss, keep + // the fetch bit set + st2_dir_updt_fetch_o = st1_dir_hit_fetch_i; + end + + // Performance event + evt_uncached_req_o = 1'b1; + end + end + // }}} + + // Load cacheable request + // {{{ + if (|{st1_req_is_load_i, + st1_req_is_cmo_prefetch_i}) + begin + // Cache miss + // {{{ + if (!cachedir_hit_i) begin + // A cache miss inserts a nop into the pipeline + st1_nop = 1'b1; + + // If there is a match in the write buffer, send the entry right away + wbuf_read_flush_hit_o = 1'b1; + + // Select a victim cacheline + st1_req_cachedir_sel_victim_o = 1'b1; + + // Pending miss on the same line + if (st1_mshr_hit_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_hit_o = 1'b1; + end + + // No available slot in the MSHR + else if (st1_mshr_full_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_full_o = 1'b1; + end + + // All entries in the target set are being fetched + else if (st1_dir_victim_unavailable_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_dir_unavailable_o = 1'b1; + end + + // Hit on an open entry of the write buffer: wait for the entry to be + // acknowledged + else if (wbuf_read_hit_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_wbuf_hit_o = 1'b1; + end + + // Miss Handler is not ready to send + else if (!st1_mshr_alloc_ready_i) begin + // Put the request on hold if the MISS HANDLER is not + // ready to send a new miss request. This is to prevent + // a deadlock between the read request channel and the + // read response channel. + // + // The request channel may be stalled by targets if they + // are not able to send a response (response is + // prioritary). Therefore, we need to put the request on + // hold to allow a possible refill read response to be + // accomplished. + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_ready_o = 1'b1; + end + + // Flush pending on the miss cacheline + else if (st1_flush_check_hit_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_hit_o = 1'b1; + end + + // Flush needed but the controller is not ready + else if (st1_dir_victim_dirty_i && !st1_flush_alloc_ready_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_not_ready_o = 1'b1; + end + + // Forward the request to the next stage to allocate the + // entry in the MSHR and send the refill request + else begin + // When the victim cacheline is dirty, flush its data to the + // memory + st2_flush_alloc_o = st1_dir_victim_dirty_i; + + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + // Request a MSHR allocation + st2_mshr_alloc_o = 1'b1; + st2_mshr_alloc_need_rsp_o = st1_req_need_rsp_i; + st2_mshr_alloc_wback_o = (st1_req_wr_auto_i & cfg_default_wb_i) | + st1_req_wr_wb_i; + + // Update the cache directory state to FETCHING + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = st1_dir_victim_valid_i; + st2_dir_updt_wback_o = st1_dir_victim_wback_i; + st2_dir_updt_dirty_o = 1'b0; + st2_dir_updt_fetch_o = 1'b1; + end + end + // }}} + + // Cache hit + // {{{ + else begin + // Flush needed but the controller is not ready + if (st1_req_wr_wt_i && st1_dir_hit_wback_i && + st1_dir_hit_dirty_i && !st1_flush_alloc_ready_i) + begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_not_ready_o = 1'b1; + st1_nop = 1'b1; + end + + // Process the load + else begin + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + // Add a NOP when replaying a request, and there is no available + // request from the replay table. + st1_nop = st1_req_rtab_i & ~rtab_req_valid_i; + + // Update victim selection for the accessed set + st1_req_cachedir_updt_sel_victim_o = + ~st1_req_is_cmo_prefetch_i | + cfg_prefetch_updt_plru_i; + + // Respond to the core (if needed) + st1_rsp_valid_o = st1_req_need_rsp_i; + + // Performance event + evt_read_req_o = ~st1_req_is_cmo_prefetch_i; + evt_prefetch_req_o = st1_req_is_cmo_prefetch_i; + + // If the cacheline is currently pre-allocated to be replaced, we + // can only forward the data, but no state update is allowed. + if (!st1_dir_hit_fetch_i) begin + // Hint is write-through but the current state is not. The + // controller needs to update the state of the cacheline to WT + if (st1_req_wr_wt_i && st1_dir_hit_wback_i) begin + // Update the directory state of the cacheline to WT + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = 1'b1; + st2_dir_updt_wback_o = 1'b0; + st2_dir_updt_dirty_o = 1'b0; + st2_dir_updt_fetch_o = 1'b0; + + // Cacheline is dirty, flush its data to the memory + st2_flush_alloc_o = st1_dir_hit_dirty_i; + + st1_nop = 1'b1; + end + + // Hint is write-back but the current state is not. The + // controller needs to update the state of the cacheline to WB + // (clean) + if (st1_req_wr_wb_i && !st1_dir_hit_wback_i) begin + // Update the directory state of the cacheline to WB + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = 1'b1; + st2_dir_updt_wback_o = 1'b1; + st2_dir_updt_dirty_o = 1'b0; + st2_dir_updt_fetch_o = 1'b0; + + st1_nop = 1'b1; + end + end + end + end + // }}} + end + // }}} + + // Store cacheable request + // {{{ + if (st1_req_is_store_i) begin + // Add a NOP in the pipeline when: + // - Structural hazard on the cache data if the st0 request is a load + // operation. + // - Replaying a request, the cache cannot accept a request from the + // core the next cycle. It can however accept a new request from the + // replay table + // + // IMPORTANT: we could remove the NOP in the first scenario if the + // controller checks for the hit of this write. However, this adds + // a DIR_RAM -> DATA_RAM timing path. + st1_nop = ((core_req_valid_i | rtab_req_valid_i) & st0_req_is_load_i) | + (st1_req_rtab_i & ~rtab_req_valid_i); + + // Enable the data RAM in case of write. However, the actual write + // depends on the hit signal from the cache directory. + // + // IMPORTANT: this produces unnecessary power consumption in case of + // write misses, but removes timing paths between the cache directory + // RAM and the data RAM chip-select. + st1_req_cachedata_write_o = 1'b1; + + // Pending miss on the same line + if (st1_mshr_hit_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_hit_o = 1'b1; + + st1_nop = 1'b1; + end + + // Hit in the flush controller + else if (st1_flush_check_hit_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_flush_hit_o = 1'b1; + + st1_nop = 1'b1; + end + + // Cache miss + // {{{ + else if (!cachedir_hit_i) begin + // Write is write-back + // {{{ + if (st1_req_wr_wb_i || (st1_req_wr_auto_i && cfg_default_wb_i)) + begin + // Select a victim cacheline + st1_req_cachedir_sel_victim_o = 1'b1; + + // If there is a match in the write buffer, send the entry right + // away + wbuf_read_flush_hit_o = 1'b1; + + // Add a nop as the next cycle the controller needs to write in the + // MSHR and the directory + st1_nop = 1'b1; + + // Miss Handler is not ready to send + if (!st1_mshr_alloc_ready_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_ready_o = 1'b1; + end + + // No available slot in the MSHR + else if (st1_mshr_full_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_mshr_full_o = 1'b1; + end + + // Hit on an entry of the write buffer: wait for the entry to be + // acknowledged + else if (wbuf_read_hit_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_wbuf_hit_o = 1'b1; + end + + // no available victim cacheline (all currently pre-allocated and + // waiting to be refilled) + else if (st1_dir_victim_unavailable_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_dir_unavailable_o = 1'b1; + end + + // Flush needed but the controller is not ready + else if (st1_dir_victim_dirty_i && !st1_flush_alloc_ready_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_not_ready_o = 1'b1; + end + + else begin + // When the victim cacheline is dirty, flush its data to the + // memory + st2_flush_alloc_o = st1_dir_victim_dirty_i; + + // Update the directory state of the cacheline to FETCHING + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = st1_dir_victim_valid_i; + st2_dir_updt_wback_o = st1_dir_victim_wback_i; + st2_dir_updt_dirty_o = 1'b0; + st2_dir_updt_fetch_o = 1'b1; + + // Send a miss request to the memory (write-allocate) + st2_mshr_alloc_o = 1'b1; + st2_mshr_alloc_need_rsp_o = 1'b0; + st2_mshr_alloc_wback_o = 1'b1; + // FIXME Optimization: ask here the miss handler to set the + // dirty bit when the new cacheline is refilled to avoid + // the update penalty of the pending write + // st2_mshr_alloc_dirty_o = 1'b1 + + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_write_miss_o = 1'b1; + + // Performance event + evt_cache_write_miss_o = 1'b1; + end + end + // }}} + + // Write is write-through + // {{{ + else begin + // Request write into the write-buffer + wbuf_write_valid_o = 1'b1; + + // No available entry in the write buffer (or conflict on pending + // entry) + if (!wbuf_write_ready_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_wbuf_not_ready_o = 1'b1; + + st1_nop = 1'b1; + end + + else begin + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + // Respond to the core (if needed) + st1_rsp_valid_o = st1_req_need_rsp_i; + + // Performance event + evt_cache_write_miss_o = 1'b1; + evt_write_req_o = 1'b1; + end + end + // }}} + end + // }}} + + // Cache hit + // {{{ + else begin + // The target cacheline is pre-allocated to be replaced. Put this write + // on-hold + if (st1_dir_hit_fetch_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_dir_fetch_o = 1'b1; + + st1_nop = 1'b1; + end + + // Write is write-back + // {{{ + else if (st1_req_wr_wb_i || (st1_req_wr_auto_i && st1_dir_hit_wback_i)) + begin + // If there is a match in the write buffer, send the entry right + // away + wbuf_read_flush_hit_o = 1'b1; + + // Hit on an entry of the write buffer: wait for the entry to be + // acknowledged. + // + // This check is to avoid a possible future race when flushing + // a dirty cacheline if there is a pending write in the write + // buffer concerning the same cacheline + if (wbuf_read_hit_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_wbuf_hit_o = 1'b1; + st1_nop = 1'b1; + + end else begin + // Update the directory state of the cacheline to dirty + if (!st1_dir_hit_wback_i || !st1_dir_hit_dirty_i) begin + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = 1'b1; + st2_dir_updt_wback_o = 1'b1; + st2_dir_updt_dirty_o = 1'b1; + st2_dir_updt_fetch_o = 1'b0; + + st1_nop = 1'b1; + end + + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + // Respond to the core + st1_rsp_valid_o = st1_req_need_rsp_i; + + // Write in the data RAM + st1_req_cachedata_write_enable_o = 1'b1; + + // Update victim selection for the accessed set + st1_req_cachedir_updt_sel_victim_o = 1'b1; + + // Performance event + evt_write_req_o = 1'b1; + end + end + // }}} + + // Write is write-through + // {{{ + else begin + // Write in the write buffer unless we need to flush the cacheline + // first + wbuf_write_valid_o = ~st1_dir_hit_dirty_i; + + // The cache needs to flush the cacheline but the flush controller + // is not ready + if (st1_dir_hit_dirty_i && !st1_flush_alloc_ready_i) begin + st1_rtab_alloc = 1'b1; + st1_rtab_flush_not_ready_o = 1'b1; + + st1_nop = 1'b1; + end + + // Flush the cacheline but keep it in the cache + else if (st1_dir_hit_dirty_i) begin + // Flush cacheline data to the memory + st2_flush_alloc_o = 1'b1; + + // Update the state to WT in the directory + st2_dir_updt_o = 1'b1; + st2_dir_updt_valid_o = 1'b1; + st2_dir_updt_wback_o = 1'b0; + st2_dir_updt_dirty_o = 1'b0; + st2_dir_updt_fetch_o = 1'b0; + + // Put the request in the replay table while waiting for the + // memory flushing + st1_rtab_alloc = 1'b1; + st1_rtab_flush_hit_o = 1'b1; + + st1_nop = 1'b1; + end + + // No available entry in the write buffer (or conflict on pending + // entry) + else if (!wbuf_write_ready_i) begin + // Put the request in the replay table + st1_rtab_alloc = 1'b1; + st1_rtab_wbuf_not_ready_o = 1'b1; + + st1_nop = 1'b1; + end + + // The store can be performed in the write buffer and in the cache + else begin + // If the request comes from the replay table, free the + // corresponding RTAB entry + st1_rtab_commit_o = st1_req_rtab_i; + + // Respond to the core + st1_rsp_valid_o = st1_req_need_rsp_i; + + // Update victim selection for the accessed set + st1_req_cachedir_updt_sel_victim_o = 1'b1; + + // Write in the data RAM + st1_req_cachedata_write_enable_o = 1'b1; + + // Performance event + evt_write_req_o = 1'b1; + end + end + // }}} + end + // }}} + end + // }}} + end + // }}} + end + // }}} + + // New request + // {{{ + nop = st1_nop | st2_nop; + + // New requests/refill are served according to the following priority: + // 0 - Refills/Invalidations (Highest priority) + // 1 - Replay Table + // 2 - Core (Lowest priority) + + // * IMPORTANT: When the replay table is full, the cache + // cannot accept new core requests to prevent a deadlock: If + // the core request needs to be put on hold, as there is no + // place the replay table, the pipeline needs to stall. If + // the pipeline is stalled, dependencies of on-hold requests + // cannot be solved, creating a deadlock + core_req_ready_o = core_req_valid_i + & ~rtab_req_valid_i + & ~refill_req_valid_i + & ~rtab_full_i + & ~cmo_busy_i + & ~uc_busy_i + & ~rtab_fence_i + & ~nop; + + rtab_req_ready_o = rtab_req_valid_i + & ~refill_req_valid_i + & (~cmo_busy_i | cmo_wait_i) + & ~nop; + + refill_req_ready_o = refill_req_valid_i + & (~cmo_busy_i | cmo_wait_i) + & ~st1_req_valid_i + & ~(st2_mshr_alloc_i | st2_dir_updt_i); + + // Forward the core/rtab request to stage 1 + st1_req_valid_o = core_req_ready_o | rtab_req_ready_o; + st1_req_is_error_o = st0_req_is_error_i; + + // New cacheable stage 0 request granted + // {{{ + // IMPORTANT: here the RAM is enabled independently if the + // request needs to be put on-hold. + // This increases the power consumption in that cases, but + // removes the timing paths RAM-to-RAM between the cache + // directory and the data array. + if ((core_req_ready_o | rtab_req_ready_o) && + !st0_req_is_uncacheable_i && + !st0_req_is_error_i) + begin + st1_req_is_cacheable_store = st1_req_valid_i & st1_req_is_store_i & + ~st1_req_is_uncacheable_i; + + st0_req_cachedata_read_o = st0_req_is_load_i & + (~st1_req_is_cacheable_store | st1_req_is_error_i); + + if (st0_req_is_load_i | + st0_req_is_cmo_prefetch_i | + st0_req_is_store_i | + st0_req_is_amo_i ) + begin + st0_req_mshr_check_o = 1'b1; + st0_req_cachedir_read_o = 1'b1; + end + end + // }}} + // }}} + end + // }}} end of normal pipeline operation + end + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv new file mode 100644 index 0000000000..5fe497de82 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv @@ -0,0 +1,382 @@ +/* + * Copyright 2024 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : September, 2024 + * Description : HPDcache Flush Controller + * History : + */ +module hpdcache_flush +// {{{ +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_word_t = logic, + parameter type hpdcache_way_vector_t = logic, + + parameter type hpdcache_access_data_t = logic, + + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_data_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_w_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Global control signals + // {{{ + output logic flush_empty_o, + output logic flush_full_o, + output logic flush_busy_o, + // }}} + + // CHECK interface + // {{{ + input hpdcache_nline_t flush_check_nline_i, + output logic flush_check_hit_o, + // }}} + + // ALLOC interface + // {{{ + input logic flush_alloc_i, + output logic flush_alloc_ready_o, + input hpdcache_nline_t flush_alloc_nline_i, + input hpdcache_way_vector_t flush_alloc_way_i, + // }}} + + // CACHE DATA interface + // {{{ + output logic flush_data_read_o, + output hpdcache_set_t flush_data_read_set_o, + output hpdcache_word_t flush_data_read_word_o, + output hpdcache_way_vector_t flush_data_read_way_o, + input hpdcache_access_data_t flush_data_read_data_i, + // }}} + + // ACK monitoring interface + // {{{ + output logic flush_ack_o, + output hpdcache_nline_t flush_ack_nline_o, + // }}} + + // MEMORY interface + // {{{ + input logic mem_req_write_ready_i, + output logic mem_req_write_valid_o, + output hpdcache_mem_req_t mem_req_write_o, + + input logic mem_req_write_data_ready_i, + output logic mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t mem_req_write_data_o, + + output logic mem_resp_write_ready_o, + input logic mem_resp_write_valid_i, + input hpdcache_mem_resp_w_t mem_resp_write_i + // }}} +); + + // Definition of constants and types + // {{{ + localparam int unsigned FlushEntries = HPDcacheCfg.u.flushEntries; + localparam int unsigned FlushIndexWidth = (FlushEntries > 1) ? $clog2(FlushEntries) : 1; + + typedef struct packed { + hpdcache_nline_t nline; + } flush_entry_t; + + typedef flush_entry_t [FlushEntries-1:0] flush_dir_t; + typedef logic [FlushIndexWidth-1:0] flush_dir_index_t; + + typedef enum { + FLUSH_IDLE, + FLUSH_SEND + } flush_fsm_e; + // }}} + + // Definition of internal signals and registers + // {{{ + logic [FlushEntries-1:0] flush_dir_valid_q; + flush_dir_t flush_dir_q; + flush_dir_index_t flush_dir_free_ptr; + logic [FlushEntries-1:0] flush_dir_free_bv; + logic [FlushEntries-1:0] flush_dir_alloc_bv; + flush_dir_index_t flush_dir_ack_ptr; + logic [FlushEntries-1:0] flush_dir_ack_bv; + hpdcache_set_t flush_set_q; + hpdcache_way_vector_t flush_way_q; + hpdcache_word_t flush_word_q, flush_word_d; + flush_fsm_e flush_fsm_q, flush_fsm_d; + + logic flush_eol; + logic flush_alloc; + hpdcache_set_t flush_alloc_set; + logic flush_ack; + logic flush_resizer_w, flush_resizer_wok; + logic flush_resizer_wlast; + + logic flush_mem_req_w, flush_mem_req_wok; + hpdcache_mem_req_t flush_mem_req_wmeta; + hpdcache_mem_data_t flush_mem_req_rdata; + logic flush_mem_req_rlast; + + logic [FlushEntries-1:0] flush_check_hit; + + genvar gen_i; + // }}} + + // Flush FSM + // {{{ + assign flush_full_o = (&flush_dir_valid_q); + assign flush_empty_o = ~(|flush_dir_valid_q); + assign flush_busy_o = (flush_fsm_q != FLUSH_IDLE); + assign flush_alloc_set = flush_alloc_nline_i[0 +: HPDcacheCfg.setWidth]; + + // End Of cache Line (EOL) + // This signal is used to determine when the entire cacheline has been flushed (read from the + // cache and written into the resizer). + // Here we make the assumption that the number of cacheline words is a power of 2. + assign flush_eol = (flush_word_q == 0); + + assign flush_alloc_ready_o = (flush_fsm_q == FLUSH_IDLE) + & flush_resizer_wok + & flush_mem_req_wok + & ~flush_full_o; + + always_comb + begin : flush_fsm_comb + flush_fsm_d = flush_fsm_q; + flush_word_d = flush_word_q; + + flush_alloc = 1'b0; + + flush_data_read_o = 1'b0; + flush_data_read_set_o = flush_set_q; + flush_data_read_word_o = flush_word_q; + flush_data_read_way_o = flush_way_q; + + flush_mem_req_w = 1'b0; + + flush_resizer_w = 1'b0; + flush_resizer_wlast = 1'b0; + + unique case (flush_fsm_q) + FLUSH_IDLE: begin + flush_mem_req_w = flush_resizer_wok & ~flush_full_o & flush_alloc_i; + if (flush_alloc_i && flush_alloc_ready_o) begin + flush_data_read_o = 1'b1; + flush_data_read_set_o = flush_alloc_set; + flush_data_read_way_o = flush_alloc_way_i; + flush_data_read_word_o = 0; + + flush_alloc = 1'b1; + flush_word_d = flush_word_q + hpdcache_word_t'(HPDcacheCfg.u.accessWords); + flush_fsm_d = FLUSH_SEND; + end + end + FLUSH_SEND: begin + flush_resizer_w = 1'b1; + flush_resizer_wlast = flush_eol; + if (flush_resizer_wok) begin + flush_data_read_o = ~flush_eol; + if (flush_eol) begin + flush_fsm_d = FLUSH_IDLE; + end else begin + flush_word_d = flush_word_q + hpdcache_word_t'(HPDcacheCfg.u.accessWords); + end + end + end + endcase + end + + // Acknowledgement interface + assign flush_ack = mem_resp_write_valid_i; + assign flush_dir_ack_ptr = flush_dir_index_t'(mem_resp_write_i.mem_resp_w_id); + assign mem_resp_write_ready_o = 1'b1; + + assign flush_ack_o = flush_ack; + assign flush_ack_nline_o = flush_dir_q[flush_dir_ack_ptr].nline; + // }}} + + // Check logic + // {{{ + for (gen_i = 0; gen_i < FlushEntries; gen_i++) begin : gen_check + assign flush_check_hit[gen_i] = (flush_check_nline_i == flush_dir_q[gen_i].nline); + end + assign flush_check_hit_o = |(flush_dir_valid_q & ~flush_dir_ack_bv & flush_check_hit); + // }}} + + // Internal state + // {{{ + + // FSM + always_ff @(posedge clk_i or negedge rst_ni) + begin : flush_fsm_ff + if (!rst_ni) begin + flush_fsm_q <= FLUSH_IDLE; + flush_word_q <= '0; + end else begin + flush_fsm_q <= flush_fsm_d; + flush_word_q <= flush_word_d; + end + end + + // Directory valid + assign flush_dir_alloc_bv = flush_dir_free_bv & {FlushEntries{flush_alloc}}; + + always_ff @(posedge clk_i or negedge rst_ni) + begin : flush_dir_valid_ff + if (!rst_ni) begin + flush_dir_valid_q <= '0; + end else begin + flush_dir_valid_q <= (~flush_dir_valid_q & flush_dir_alloc_bv) | + ( flush_dir_valid_q & ~flush_dir_ack_bv ); + end + end + // }}} + + // Buffers + always_ff @(posedge clk_i) + begin : flush_dir_ff + if (flush_alloc) begin + flush_dir_q[flush_dir_free_ptr] <= '{ + nline: flush_alloc_nline_i + }; + flush_set_q <= flush_alloc_set; + flush_way_q <= flush_alloc_way_i; + end + end + // }}} + + // Internal components + // {{{ + hpdcache_decoder #(.N(FlushIndexWidth)) flush_ack_decoder_i( + .en_i (flush_ack), + .val_i (flush_dir_ack_ptr), + .val_o (flush_dir_ack_bv) + ); + + // Select a free entry in the flush directory + // + hpdcache_fxarb #(.N(FlushEntries)) flush_dir_free_arb_i( + .clk_i, + .rst_ni, + .req_i (~flush_dir_valid_q), + .gnt_o (flush_dir_free_bv), + .ready_i (flush_alloc) + ); + hpdcache_1hot_to_binary #(.N (FlushEntries)) flush_dir_free_ptr_bin_i( + .val_i (flush_dir_free_bv), + .val_o (flush_dir_free_ptr) + ); + + // FIFO for memory request metadata + // + localparam hpdcache_uint32 MemReqFlits = HPDcacheCfg.u.memDataWidth < HPDcacheCfg.clWidth ? + (HPDcacheCfg.clWidth / HPDcacheCfg.u.memDataWidth) - 1 : 0; + + assign flush_mem_req_wmeta = '{ + mem_req_addr: {flush_alloc_nline_i, {HPDcacheCfg.clOffsetWidth{1'b0}} }, + mem_req_len: hpdcache_mem_len_t'(MemReqFlits), + mem_req_size: get_hpdcache_mem_size(HPDcacheCfg.u.memDataWidth/8), + mem_req_id: hpdcache_mem_id_t'(flush_dir_free_ptr), + mem_req_command: HPDCACHE_MEM_WRITE, + mem_req_atomic: HPDCACHE_MEM_ATOMIC_ADD, /* NOP */ + mem_req_cacheable: 1'b1 + }; + hpdcache_fifo_reg #( + .FIFO_DEPTH (2), + .FEEDTHROUGH (1'b0), + .fifo_data_t (hpdcache_mem_req_t) + ) mem_req_meta_fifo_i( + .clk_i, + .rst_ni, + .w_i (flush_mem_req_w), + .wok_o (flush_mem_req_wok), + .wdata_i (flush_mem_req_wmeta), + .r_i (mem_req_write_ready_i), + .rok_o (mem_req_write_valid_o), + .rdata_o (mem_req_write_o) + ); + + // Resize data width from the cache controller to the NoC data width + // + hpdcache_data_resize #( + .WR_WIDTH (HPDcacheCfg.accessWidth), + .RD_WIDTH (HPDcacheCfg.u.memDataWidth), + .DEPTH (HPDcacheCfg.u.flushFifoDepth) + ) flush_data_resizer_i( + .clk_i, + .rst_ni, + + .w_i (flush_resizer_w), + .wok_o (flush_resizer_wok), + .wdata_i (flush_data_read_data_i), + .wlast_i (flush_resizer_wlast), + + .r_i (mem_req_write_data_ready_i), + .rok_o (mem_req_write_data_valid_o), + .rdata_o (flush_mem_req_rdata), + .rlast_o (/* open */) + ); + + + // Logic to detect the end of a packet + // + hpdcache_mem_len_t write_flits_cnt_q; + + assign flush_mem_req_rlast = (hpdcache_uint32'(write_flits_cnt_q) == MemReqFlits); + + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + write_flits_cnt_q <= 0; + end else begin + if (mem_req_write_data_valid_o && mem_req_write_data_ready_i) begin + if (flush_mem_req_rlast) begin + write_flits_cnt_q <= 0; + end else begin + write_flits_cnt_q <= write_flits_cnt_q + 1; + end + end + end + end + + // Forward data flit to the NoC + // + assign mem_req_write_data_o = '{ + mem_req_w_data: flush_mem_req_rdata, + mem_req_w_be: '1, + mem_req_w_last: flush_mem_req_rlast + }; + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv new file mode 100644 index 0000000000..5a716ce748 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv @@ -0,0 +1,996 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache Directory and Data Memory RAMs Controller + * History : + */ +module hpdcache_memctrl +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_word_t = logic, + parameter type hpdcache_way_vector_t = logic, + parameter type hpdcache_dir_entry_t = logic, + + parameter type hpdcache_data_word_t = logic, + parameter type hpdcache_data_be_t = logic, + + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + + parameter type hpdcache_access_data_t = logic, + parameter type hpdcache_access_be_t = logic +) + // }}} + + // Ports + // {{{ +( + // Global clock and reset signals + // {{{ + input logic clk_i, + input logic rst_ni, + // }}} + + // Global control signals + // {{{ + output logic ready_o, + // }}} + + // DIR array access interface + // {{{ + input logic dir_match_i, + input hpdcache_set_t dir_match_set_i, + input hpdcache_tag_t dir_match_tag_i, + input logic dir_updt_sel_victim_i, + output hpdcache_way_vector_t dir_hit_way_o, + output hpdcache_tag_t dir_hit_tag_o, + output logic dir_hit_wback_o, + output logic dir_hit_dirty_o, + output logic dir_hit_fetch_o, + + input logic dir_updt_i, + input hpdcache_set_t dir_updt_set_i, + input hpdcache_way_vector_t dir_updt_way_i, + input hpdcache_tag_t dir_updt_tag_i, + input logic dir_updt_valid_i, + input logic dir_updt_wback_i, + input logic dir_updt_dirty_i, + input logic dir_updt_fetch_i, + + input logic dir_amo_match_i, + input hpdcache_set_t dir_amo_match_set_i, + input hpdcache_tag_t dir_amo_match_tag_i, + input logic dir_amo_updt_sel_victim_i, + output hpdcache_way_vector_t dir_amo_hit_way_o, + + input logic dir_refill_i, + input hpdcache_set_t dir_refill_set_i, + input hpdcache_way_vector_t dir_refill_way_i, + input hpdcache_dir_entry_t dir_refill_entry_i, + input logic dir_refill_updt_sel_victim_i, + + input logic dir_victim_sel_i, + input hpdcache_set_t dir_victim_set_i, + output logic dir_victim_valid_o, + output logic dir_victim_wback_o, + output logic dir_victim_dirty_o, + output hpdcache_tag_t dir_victim_tag_o, + output hpdcache_way_vector_t dir_victim_way_o, + + input logic dir_inval_check_i, + input hpdcache_nline_t dir_inval_nline_i, + input logic dir_inval_write_i, + output logic dir_inval_hit_o, + + input logic dir_cmo_check_nline_i, + input hpdcache_set_t dir_cmo_check_nline_set_i, + input hpdcache_tag_t dir_cmo_check_nline_tag_i, + output hpdcache_way_vector_t dir_cmo_check_nline_hit_way_o, + output logic dir_cmo_check_nline_wback_o, + output logic dir_cmo_check_nline_dirty_o, + + input logic dir_cmo_check_entry_i, + input hpdcache_set_t dir_cmo_check_entry_set_i, + input hpdcache_way_vector_t dir_cmo_check_entry_way_i, + output logic dir_cmo_check_entry_valid_o, + output logic dir_cmo_check_entry_wback_o, + output logic dir_cmo_check_entry_dirty_o, + output hpdcache_tag_t dir_cmo_check_entry_tag_o, + + input logic dir_cmo_updt_i, + input hpdcache_set_t dir_cmo_updt_set_i, + input hpdcache_way_vector_t dir_cmo_updt_way_i, + input hpdcache_tag_t dir_cmo_updt_tag_i, + input logic dir_cmo_updt_valid_i, + input logic dir_cmo_updt_wback_i, + input logic dir_cmo_updt_dirty_i, + input logic dir_cmo_updt_fetch_i, + // }}} + + // DATA array access interface + // {{{ + input logic data_req_read_i, + input hpdcache_set_t data_req_read_set_i, + input hpdcache_req_size_t data_req_read_size_i, + input hpdcache_word_t data_req_read_word_i, + output hpdcache_req_data_t data_req_read_data_o, + + input logic data_req_write_i, + input logic data_req_write_enable_i, + input hpdcache_set_t data_req_write_set_i, + input hpdcache_req_size_t data_req_write_size_i, + input hpdcache_word_t data_req_write_word_i, + input hpdcache_req_data_t data_req_write_data_i, + input hpdcache_req_be_t data_req_write_be_i, + + input logic data_amo_write_i, + input logic data_amo_write_enable_i, + input hpdcache_set_t data_amo_write_set_i, + input hpdcache_req_size_t data_amo_write_size_i, + input hpdcache_word_t data_amo_write_word_i, + input hpdcache_req_data_t data_amo_write_data_i, + input hpdcache_req_be_t data_amo_write_be_i, + + input logic data_flush_read_i, + input hpdcache_set_t data_flush_read_set_i, + input hpdcache_word_t data_flush_read_word_i, + input hpdcache_way_vector_t data_flush_read_way_i, + output hpdcache_access_data_t data_flush_read_data_o, + + input logic data_refill_i, + input hpdcache_set_t data_refill_set_i, + input hpdcache_way_vector_t data_refill_way_i, + input hpdcache_word_t data_refill_word_i, + input hpdcache_access_data_t data_refill_data_i + // }}} +); + // }}} + + // Definition of constants and types + // {{{ + localparam int unsigned HPDCACHE_DIR_RAM_WIDTH = $bits(hpdcache_dir_entry_t); + localparam int unsigned HPDCACHE_DIR_RAM_ADDR_WIDTH = $clog2(HPDcacheCfg.u.sets); + localparam int unsigned HPDCACHE_DATA_RAM_ENTR_PER_SET = HPDcacheCfg.u.clWords/ + HPDcacheCfg.u.accessWords; + localparam int unsigned HPDCACHE_DATA_RAM_DEPTH = HPDcacheCfg.u.sets* + HPDCACHE_DATA_RAM_ENTR_PER_SET; + localparam int unsigned HPDCACHE_DATA_RAM_WIDTH = HPDcacheCfg.u.dataWaysPerRamWord* + HPDcacheCfg.u.wordWidth; + localparam int unsigned HPDCACHE_DATA_RAM_ADDR_WIDTH = $clog2(HPDCACHE_DATA_RAM_DEPTH); + localparam int unsigned HPDCACHE_DATA_REQ_RATIO = HPDcacheCfg.u.accessWords/ + HPDcacheCfg.u.reqWords; + localparam int unsigned HPDCACHE_DATA_RAM_Y_CUTS = HPDcacheCfg.u.ways/ + HPDcacheCfg.u.dataWaysPerRamWord; + localparam int unsigned HPDCACHE_DATA_RAM_X_CUTS = HPDcacheCfg.u.accessWords; + localparam int unsigned HPDCACHE_ALL_CUTS = HPDCACHE_DATA_RAM_X_CUTS*HPDCACHE_DATA_RAM_Y_CUTS; + + typedef logic [HPDCACHE_DIR_RAM_ADDR_WIDTH-1:0] hpdcache_dir_addr_t; + + typedef logic [HPDCACHE_DATA_RAM_ADDR_WIDTH-1:0] hpdcache_data_ram_addr_t; + typedef hpdcache_data_word_t[HPDcacheCfg.u.dataWaysPerRamWord-1:0] hpdcache_data_ram_data_t; + typedef hpdcache_data_be_t [HPDcacheCfg.u.dataWaysPerRamWord-1:0] hpdcache_data_ram_be_t; + typedef logic [HPDCACHE_DATA_RAM_Y_CUTS-1:0] hpdcache_data_ram_row_idx_t; + typedef logic [$clog2(HPDcacheCfg.u.dataWaysPerRamWord)-1:0] hpdcache_data_ram_way_idx_t; + typedef logic [HPDCACHE_DATA_RAM_X_CUTS-1:0] hpdcache_data_row_enable_t; + typedef hpdcache_data_row_enable_t [HPDCACHE_DATA_RAM_Y_CUTS-1:0] hpdcache_data_enable_t; + + typedef hpdcache_data_ram_data_t + [HPDCACHE_DATA_RAM_Y_CUTS-1:0] + [HPDCACHE_DATA_RAM_X_CUTS-1:0] + hpdcache_data_entry_t; + typedef hpdcache_data_ram_data_t + [HPDCACHE_DATA_RAM_X_CUTS-1:0] + hpdcache_data_row_t; + typedef hpdcache_data_ram_be_t + [HPDCACHE_DATA_RAM_Y_CUTS-1:0] + [HPDCACHE_DATA_RAM_X_CUTS-1:0] + hpdcache_data_be_entry_t; + typedef hpdcache_data_ram_addr_t + [HPDCACHE_DATA_RAM_Y_CUTS-1:0] + [HPDCACHE_DATA_RAM_X_CUTS-1:0] + hpdcache_data_addr_t; + // }}} + + // Definition of functions + // {{{ + + // hpdcache_compute_data_ram_cs + // + // description: This function computes the chip-select signal for data + // RAMs depending on the request size and the word offset + function automatic hpdcache_data_row_enable_t hpdcache_compute_data_ram_cs( + input hpdcache_req_size_t size_i, + input hpdcache_word_t word_i); + + localparam hpdcache_uint32 OffWidth = + HPDcacheCfg.u.accessWords > 1 ? $clog2(HPDcacheCfg.u.accessWords) : 1; + + hpdcache_data_row_enable_t ret; + hpdcache_uint32 off; + + case (size_i) + 3'h0, + 3'h1, + 3'h2, + 3'h3: ret = hpdcache_data_row_enable_t'({ 64/HPDcacheCfg.u.wordWidth{1'b1}}); + 3'h4: ret = hpdcache_data_row_enable_t'({128/HPDcacheCfg.u.wordWidth{1'b1}}); + 3'h5: ret = hpdcache_data_row_enable_t'({256/HPDcacheCfg.u.wordWidth{1'b1}}); + default: ret = hpdcache_data_row_enable_t'({512/HPDcacheCfg.u.wordWidth{1'b1}}); + endcase + + off = HPDcacheCfg.u.accessWords > 1 ? hpdcache_uint'(word_i[0 +: OffWidth]) : 0; + return hpdcache_data_row_enable_t'(ret << off); + endfunction + + function automatic hpdcache_data_ram_row_idx_t hpdcache_way_to_data_ram_row( + input hpdcache_way_vector_t way); + hpdcache_data_ram_row_idx_t ret; + for (hpdcache_uint i = 0; i < HPDCACHE_DATA_RAM_Y_CUTS; i++) begin + ret[i] = |way[i*HPDcacheCfg.u.dataWaysPerRamWord +: HPDcacheCfg.u.dataWaysPerRamWord]; + end + return ret; + endfunction + + function automatic hpdcache_data_ram_way_idx_t hpdcache_way_to_data_ram_word( + input hpdcache_way_vector_t way); + for (hpdcache_uint i = 0; i < HPDcacheCfg.u.ways; i++) begin + if (way[i]) return hpdcache_data_ram_way_idx_t'(i % HPDcacheCfg.u.dataWaysPerRamWord); + end + return 0; + endfunction + + function automatic hpdcache_data_ram_addr_t hpdcache_set_to_data_ram_addr( + input hpdcache_set_t set, + input hpdcache_word_t word); + hpdcache_uint ret; + + ret = (hpdcache_uint'(set)*(HPDcacheCfg.u.clWords / HPDcacheCfg.u.accessWords)) + + (hpdcache_uint'(word) / HPDcacheCfg.u.accessWords); + + return hpdcache_data_ram_addr_t'(ret); + endfunction + // }}} + + // Definition of internal signals and registers + // {{{ + genvar gen_i, gen_j, gen_k; + + // Directory initialization signals and registers + logic init_q, init_d; + hpdcache_dir_addr_t init_set_q, init_set_d; + hpdcache_way_vector_t init_dir_cs; + + // Directory valid bit vector (one bit per set and way) + hpdcache_set_t dir_req_set_q; + hpdcache_way_vector_t dir_req_way_q; + hpdcache_dir_addr_t dir_addr; + hpdcache_way_vector_t dir_cs; + hpdcache_way_vector_t dir_we; + hpdcache_dir_entry_t [HPDcacheCfg.u.ways-1:0] dir_wentry; + hpdcache_dir_entry_t [HPDcacheCfg.u.ways-1:0] dir_rentry; + logic [HPDcacheCfg.u.ways-1:0] dir_valid; + logic [HPDcacheCfg.u.ways-1:0] dir_wback; + logic [HPDcacheCfg.u.ways-1:0] dir_dirty; + logic [HPDcacheCfg.u.ways-1:0] dir_fetch; + + hpdcache_data_addr_t data_addr; + hpdcache_data_enable_t data_cs; + hpdcache_data_enable_t data_we; + hpdcache_data_be_entry_t data_wbyteenable; + hpdcache_data_entry_t data_wentry; + hpdcache_data_entry_t data_rentry; + + logic data_write; + logic data_write_enable; + hpdcache_set_t data_write_set; + hpdcache_req_size_t data_write_size; + hpdcache_word_t data_write_word; + hpdcache_access_data_t data_write_data; + hpdcache_access_be_t data_write_be; + + hpdcache_access_data_t data_req_write_data; + hpdcache_access_be_t data_req_write_be; + + hpdcache_access_data_t data_amo_write_data; + hpdcache_access_be_t data_amo_write_be; + + hpdcache_way_vector_t data_way; + + hpdcache_data_ram_row_idx_t data_ram_row; + hpdcache_data_ram_way_idx_t data_ram_word; + + hpdcache_tag_t dir_inval_tag; + hpdcache_set_t dir_inval_set; + hpdcache_way_vector_t dir_inval_hit_way; + // }}} + + // Init FSM + // {{{ + always_comb + begin : init_comb + init_dir_cs = '0; + init_d = init_q; + init_set_d = init_set_q; + + unique case (init_q) + 1'b0: begin + init_d = (hpdcache_uint'(init_set_q) == (HPDcacheCfg.u.sets - 1)); + init_set_d = init_set_q + 1; + init_dir_cs = '1; + end + + 1'b1: begin + init_d = 1'b1; + init_set_d = init_set_q; + end + endcase + end + + assign ready_o = init_q; + + always_ff @(posedge clk_i or negedge rst_ni) + begin : init_ff + if (!rst_ni) begin + init_q <= 1'b0; + init_set_q <= 0; + end else begin + init_q <= init_d; + init_set_q <= init_set_d; + end + end + // }}} + + // Memory arrays + // {{{ + generate + genvar x, y, dir_w; + + // Directory + // + for (dir_w = 0; dir_w < int'(HPDcacheCfg.u.ways); dir_w++) begin : gen_dir_sram + hpdcache_sram #( + .DATA_SIZE (HPDCACHE_DIR_RAM_WIDTH), + .ADDR_SIZE (HPDCACHE_DIR_RAM_ADDR_WIDTH) + ) dir_sram ( + .clk (clk_i), + .rst_n (rst_ni), + .cs (dir_cs[dir_w]), + .we (dir_we[dir_w]), + .addr (dir_addr), + .wdata (dir_wentry[dir_w]), + .rdata (dir_rentry[dir_w]) + ); + end + + // Data + // + for (y = 0; y < int'(HPDCACHE_DATA_RAM_Y_CUTS); y++) begin : gen_data_sram_row + for (x = 0; x < int'(HPDCACHE_DATA_RAM_X_CUTS); x++) begin : gen_data_sram_col + if (HPDcacheCfg.u.dataRamByteEnable) begin : gen_data_sram_wbyteenable + hpdcache_sram_wbyteenable #( + .DATA_SIZE (HPDCACHE_DATA_RAM_WIDTH), + .ADDR_SIZE (HPDCACHE_DATA_RAM_ADDR_WIDTH) + ) data_sram ( + .clk (clk_i), + .rst_n (rst_ni), + .cs (data_cs[y][x]), + .we (data_we[y][x]), + .addr (data_addr[y][x]), + .wdata (data_wentry[y][x]), + .wbyteenable (data_wbyteenable[y][x]), + .rdata (data_rentry[y][x]) + ); + end else begin : gen_data_sram_wmask + hpdcache_data_ram_data_t data_wmask; + + // build the bitmask from the write byte enable signal + always_comb + begin : data_wmask_comb + for (int w = 0; w < HPDcacheCfg.u.dataWaysPerRamWord; w++) begin + for (int b = 0; b < HPDcacheCfg.u.wordWidth/8; b++) begin + data_wmask[w][8*b +: 8] = {8{data_wbyteenable[y][x][w][b]}}; + end + end + end + + hpdcache_sram_wmask #( + .DATA_SIZE (HPDCACHE_DATA_RAM_WIDTH), + .ADDR_SIZE (HPDCACHE_DATA_RAM_ADDR_WIDTH) + ) data_sram ( + .clk (clk_i), + .rst_n (rst_ni), + .cs (data_cs[y][x]), + .we (data_we[y][x]), + .addr (data_addr[y][x]), + .wdata (data_wentry[y][x]), + .wmask (data_wmask), + .rdata (data_rentry[y][x]) + ); + end + end + end + endgenerate + // }}} + + // Directory RAM request mux + // {{{ + assign dir_inval_set = dir_inval_nline_i[0 +: HPDcacheCfg.setWidth]; + assign dir_inval_tag = dir_inval_nline_i[HPDcacheCfg.setWidth +: HPDcacheCfg.tagWidth]; + + always_comb + begin : dir_ctrl_comb + unique case (1'b1) + // Cache directory initialization + ~init_q: begin + dir_addr = init_set_q; + dir_cs = init_dir_cs; + dir_we = '1; + dir_wentry = '0; + end + + // Cache directory match tag -> hit + dir_match_i: begin + dir_addr = dir_match_set_i; + dir_cs = '1; + dir_we = '0; + dir_wentry = '0; + end + + // Cache directory AMO match tag -> hit + dir_amo_match_i: begin + dir_addr = dir_amo_match_set_i; + dir_cs = '1; + dir_we = '0; + dir_wentry = '0; + end + + // Cache directory update + dir_refill_i: begin + dir_addr = dir_refill_set_i; + dir_cs = dir_refill_way_i; + dir_we = dir_refill_way_i; + dir_wentry = {HPDcacheCfg.u.ways{dir_refill_entry_i}}; + end + + // Cache directory invalidate check from the NoC + dir_inval_check_i: begin + dir_addr = dir_inval_set; + dir_cs = '1; + dir_we = '0; + dir_wentry = '0; + end + + // Cache directory invalidate from the NoC + dir_inval_write_i: begin + dir_addr = dir_inval_set; + dir_cs = dir_inval_hit_way; + dir_we = dir_inval_hit_way; + dir_wentry = '0; + end + + // Cache directory CMO match tag + dir_cmo_check_nline_i: begin + dir_addr = dir_cmo_check_nline_set_i; + dir_cs = '1; + dir_we = '0; + dir_wentry = '0; + end + + // Cache directory CMO match tag + dir_cmo_check_entry_i: begin + dir_addr = dir_cmo_check_entry_set_i; + dir_cs = dir_cmo_check_entry_way_i; + dir_we = '0; + dir_wentry = '0; + end + + // Cache directory CMO inval tag + dir_cmo_updt_i: begin + dir_addr = dir_cmo_updt_set_i; + dir_cs = dir_cmo_updt_way_i; + dir_we = dir_cmo_updt_way_i; + + for (hpdcache_uint i = 0; i < HPDcacheCfg.u.ways; i++) begin + dir_wentry[i] = '{ + valid: dir_cmo_updt_valid_i, + wback: dir_cmo_updt_wback_i, + dirty: dir_cmo_updt_dirty_i, + fetch: dir_cmo_updt_fetch_i, + tag : dir_cmo_updt_tag_i + }; + end + end + + // Cache directory match tag -> hit + dir_updt_i: begin + dir_addr = dir_updt_set_i; + dir_cs = dir_updt_way_i; + dir_we = dir_updt_way_i; + + for (hpdcache_uint i = 0; i < HPDcacheCfg.u.ways; i++) begin + dir_wentry[i] = '{ + valid: dir_updt_valid_i, + wback: dir_updt_wback_i, + dirty: dir_updt_dirty_i, + fetch: dir_updt_fetch_i, + tag : dir_updt_tag_i + }; + end + end + + // Do nothing + default: begin + dir_addr = dir_req_set_q; + dir_cs = '0; + dir_we = '0; + dir_wentry = '0; + end + endcase + end + + // }}} + + // Directory hit logic + // {{{ + hpdcache_tag_t [HPDcacheCfg.u.ways-1:0] dir_tags; + hpdcache_way_vector_t req_hit; + hpdcache_way_vector_t amo_hit; + hpdcache_way_vector_t cmo_hit; + hpdcache_way_vector_t inval_hit; + + for (gen_i = 0; gen_i < int'(HPDcacheCfg.u.ways); gen_i++) + begin : gen_dir_match_tag + assign dir_tags[gen_i] = dir_rentry[gen_i].tag; + + assign req_hit[gen_i] = (dir_tags[gen_i] == dir_match_tag_i); + assign amo_hit[gen_i] = (dir_tags[gen_i] == dir_amo_match_tag_i); + assign cmo_hit[gen_i] = (dir_tags[gen_i] == dir_cmo_check_nline_tag_i); + assign inval_hit[gen_i] = (dir_tags[gen_i] == dir_inval_tag); + + assign dir_hit_way_o[gen_i] = dir_valid[gen_i] & req_hit[gen_i]; + assign dir_amo_hit_way_o[gen_i] = dir_valid[gen_i] & amo_hit[gen_i]; + assign dir_cmo_check_nline_hit_way_o[gen_i] = dir_valid[gen_i] & cmo_hit[gen_i]; + assign dir_inval_hit_way[gen_i] = dir_valid[gen_i] & inval_hit[gen_i]; + end + + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.ways), + .DATA_WIDTH (HPDcacheCfg.tagWidth), + .ONE_HOT_SEL (1'b1) + ) hit_tag_mux_i( + .data_i (dir_tags), + .sel_i (dir_hit_way_o), + .data_o (dir_hit_tag_o) + ); + + assign dir_hit_wback_o = |(dir_hit_way_o & dir_wback); + assign dir_hit_dirty_o = |(dir_hit_way_o & dir_dirty); + assign dir_hit_fetch_o = |(dir_hit_way_o & dir_fetch); + + assign dir_cmo_check_nline_wback_o = |(dir_cmo_check_nline_hit_way_o & dir_wback); + assign dir_cmo_check_nline_dirty_o = |(dir_cmo_check_nline_hit_way_o & dir_dirty); + assign dir_cmo_check_entry_valid_o = |(dir_req_way_q & dir_valid); + assign dir_cmo_check_entry_wback_o = |(dir_req_way_q & dir_wback); + assign dir_cmo_check_entry_dirty_o = |(dir_req_way_q & dir_dirty); + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.ways), + .DATA_WIDTH (HPDcacheCfg.tagWidth), + .ONE_HOT_SEL (1'b1) + ) flush_tag_mux_i( + .data_i (dir_tags), + .sel_i (dir_req_way_q), + .data_o (dir_cmo_check_entry_tag_o) + ); + + assign dir_victim_valid_o = |(dir_victim_way_o & dir_valid); + assign dir_victim_wback_o = |(dir_victim_way_o & dir_wback); + assign dir_victim_dirty_o = |(dir_victim_way_o & dir_dirty); + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.ways), + .DATA_WIDTH (HPDcacheCfg.tagWidth), + .ONE_HOT_SEL (1'b1) + ) victim_tag_mux_i( + .data_i (dir_tags), + .sel_i (dir_victim_way_o), + .data_o (dir_victim_tag_o) + ); + + assign dir_inval_hit_o = |dir_inval_hit_way; + // }}} + + // Directory victim select logic + // {{{ + logic updt_sel_victim; + hpdcache_way_vector_t updt_sel_victim_way; + hpdcache_set_t updt_sel_victim_set; + + assign updt_sel_victim = dir_updt_sel_victim_i | + dir_refill_updt_sel_victim_i | + dir_amo_updt_sel_victim_i; + + assign updt_sel_victim_way = dir_updt_sel_victim_i ? dir_hit_way_o : + dir_refill_updt_sel_victim_i ? dir_refill_way_i : + dir_amo_hit_way_o; + + assign updt_sel_victim_set = dir_refill_updt_sel_victim_i ? dir_refill_set_i : + dir_req_set_q; + + for (gen_i = 0; gen_i < HPDcacheCfg.u.ways; gen_i++) begin : gen_dir_valid_bv + assign dir_valid[gen_i] = dir_rentry[gen_i].valid; + assign dir_wback[gen_i] = dir_rentry[gen_i].wback; + assign dir_dirty[gen_i] = dir_rentry[gen_i].dirty; + assign dir_fetch[gen_i] = dir_rentry[gen_i].fetch; + end + + + hpdcache_victim_sel #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_way_vector_t (hpdcache_way_vector_t) + ) victim_sel_i( + .clk_i, + .rst_ni, + + .updt_i (updt_sel_victim), + .updt_set_i (updt_sel_victim_set), + .updt_way_i (updt_sel_victim_way), + + .sel_victim_i (dir_victim_sel_i), + .sel_dir_valid_i (dir_valid), + .sel_dir_wback_i (dir_wback), + .sel_dir_dirty_i (dir_dirty), + .sel_dir_fetch_i (dir_fetch), + .sel_victim_set_i (dir_victim_set_i), + .sel_victim_way_o (dir_victim_way_o) + ); + // }}} + + // Data RAM request multiplexor + // {{{ + + // Upsize the request interface to match the maximum access width of the data RAM + if (HPDCACHE_DATA_REQ_RATIO > 1) begin : gen_upsize_data_req_write + // demux request DATA + assign data_req_write_data = {HPDCACHE_DATA_REQ_RATIO{data_req_write_data_i}}; + + // demux request BE + hpdcache_demux #( + .NOUTPUT (HPDCACHE_DATA_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth/8), + .ONE_HOT_SEL (1'b0) + ) data_req_write_be_demux_i ( + .data_i (data_req_write_be_i), + .sel_i (data_req_write_word_i[HPDcacheCfg.reqWordIdxWidth +: + $clog2(HPDCACHE_DATA_REQ_RATIO)]), + .data_o (data_req_write_be) + ); + end else begin : gen_eqsize_data_req_write + assign data_req_write_data = data_req_write_data_i; + assign data_req_write_be = data_req_write_be_i; + end + + // Upsize the AMO data interface to match the maximum access width of the data RAM + if (HPDCACHE_DATA_REQ_RATIO > 1) begin : gen_upsize_amo_req_write + assign data_amo_write_data = {HPDCACHE_DATA_REQ_RATIO{data_amo_write_data_i}}; + + hpdcache_demux #( + .NOUTPUT (HPDCACHE_DATA_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth/8), + .ONE_HOT_SEL (1'b0) + ) amo_be_demux_i( + .data_i (data_amo_write_be_i), + .sel_i (data_amo_write_word_i[HPDcacheCfg.reqWordIdxWidth +: + $clog2(HPDCACHE_DATA_REQ_RATIO)]), + .data_o (data_amo_write_be) + ); + end else begin : gen_eqsize_amo_req_write + assign data_amo_write_data = data_amo_write_data_i; + assign data_amo_write_be = data_amo_write_be_i; + end + + // Multiplex between data write requests + always_comb + begin : data_write_comb + unique case (1'b1) + data_refill_i: begin + data_write = 1'b1; + data_write_enable = 1'b1; + data_write_set = data_refill_set_i; + data_write_size = hpdcache_req_size_t'($clog2(HPDcacheCfg.accessWidth/8)); + data_write_word = data_refill_word_i; + data_write_data = data_refill_data_i; + data_write_be = '1; + end + + data_req_write_i: begin + data_write = 1'b1; + data_write_enable = data_req_write_enable_i; + data_write_set = data_req_write_set_i; + data_write_size = data_req_write_size_i; + data_write_word = data_req_write_word_i; + data_write_data = data_req_write_data; + data_write_be = data_req_write_be; + end + + data_amo_write_i: begin + data_write = 1'b1; + data_write_enable = data_amo_write_enable_i; + data_write_set = data_amo_write_set_i; + data_write_size = data_amo_write_size_i; + data_write_word = data_amo_write_word_i; + data_write_data = data_amo_write_data; + data_write_be = data_amo_write_be; + end + + default: begin + data_write = 1'b0; + data_write_enable = 1'b0; + data_write_set = '0; + data_write_size = '0; + data_write_word = '0; + data_write_data = '0; + data_write_be = '0; + end + endcase + end + + // Multiplex between read and write access on the data RAM + assign data_way = data_refill_i ? data_refill_way_i : + data_flush_read_i ? data_flush_read_way_i : + data_amo_write_i ? dir_amo_hit_way_o : + dir_hit_way_o; + + // Decode way index + assign data_ram_word = hpdcache_way_to_data_ram_word(data_way); + assign data_ram_row = hpdcache_way_to_data_ram_row(data_way); + + always_comb + begin : data_ctrl_comb + data_addr = '0; + data_cs = '0; + data_we = '0; + data_wbyteenable = '0; + data_wentry = '0; + + unique case (1'b1) + // Select data read inputs + data_req_read_i: begin + data_addr = {HPDCACHE_ALL_CUTS{ + hpdcache_set_to_data_ram_addr(data_req_read_set_i, data_req_read_word_i)} + }; + + for (int unsigned i = 0; i < HPDCACHE_DATA_RAM_Y_CUTS; i++) begin + data_cs[i] = hpdcache_compute_data_ram_cs(data_req_read_size_i, + data_req_read_word_i); + end + end + + // Select data flush read inputs + data_flush_read_i: begin + data_addr = {HPDCACHE_ALL_CUTS{ + hpdcache_set_to_data_ram_addr(data_flush_read_set_i, data_flush_read_word_i)} + }; + for (int unsigned i = 0; i < HPDCACHE_DATA_RAM_Y_CUTS; i++) begin + data_cs[i] = data_ram_row[i] ? '1 : '0; + end + end + + // Select data write inputs + data_write: begin + data_addr = {HPDCACHE_ALL_CUTS{hpdcache_set_to_data_ram_addr(data_write_set, + data_write_word)}}; + + for (int unsigned i = 0; i < HPDCACHE_DATA_RAM_Y_CUTS; i++) begin + for (int unsigned j = 0; j < HPDCACHE_DATA_RAM_X_CUTS; j++) begin + data_wentry[i][j] = {HPDcacheCfg.u.dataWaysPerRamWord{data_write_data[j]}}; + end + end + + for (int unsigned i = 0; i < HPDCACHE_DATA_RAM_Y_CUTS; i++) begin + data_cs[i] = hpdcache_compute_data_ram_cs(data_write_size, data_write_word); + + if (data_ram_row[i]) begin + data_we[i] = data_write_enable ? data_cs[i] : '0; + end + + // Build the write mask + for (int unsigned j = 0; j < HPDcacheCfg.u.accessWords; j++) begin + for (int unsigned k = 0; k < HPDcacheCfg.u.dataWaysPerRamWord; k++) begin + data_wbyteenable[i][j][k] = (k == hpdcache_uint'(data_ram_word)) ? + data_write_be[j] : '0; + end + end + end + end + + default: begin + // Do nothing + end + endcase + end + // }}} + + // Data RAM read data multiplexor + // {{{ + hpdcache_req_data_t [HPDCACHE_DATA_REQ_RATIO-1:0][HPDcacheCfg.u.ways-1:0] data_read_words; + hpdcache_req_data_t [HPDcacheCfg.u.ways-1:0] data_read_req_word; + + // Organize the read data by words (all ways for the same word are contiguous) + for (gen_i = 0; gen_i < int'(HPDCACHE_DATA_REQ_RATIO); gen_i++) begin : gen_data_rentry_i + for (gen_j = 0; gen_j < int'(HPDcacheCfg.u.ways); gen_j++) begin : gen_data_rentry_j + for (gen_k = 0; gen_k < int'(HPDcacheCfg.u.reqWords); gen_k++) begin : gen_data_rentry_k + assign data_read_words[gen_i][gen_j][gen_k] = + data_rentry[(gen_j / HPDcacheCfg.u.dataWaysPerRamWord)] + [(gen_i * HPDcacheCfg.u.reqWords) + gen_k] + [(gen_j % HPDcacheCfg.u.dataWaysPerRamWord)]; + end + end + end + + // Mux the data according to the access word + typedef logic [$clog2(HPDCACHE_DATA_REQ_RATIO)-1:0] data_req_word_t; + if (HPDCACHE_DATA_REQ_RATIO > 1) begin : gen_req_width_lt_ram_width + data_req_word_t data_read_req_word_index_q; + + hpdcache_mux #( + .NINPUT (HPDCACHE_DATA_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth*HPDcacheCfg.u.ways) + ) data_read_req_word_mux_i( + .data_i (data_read_words), + .sel_i (data_read_req_word_index_q), + .data_o (data_read_req_word) + ); + + always_ff @(posedge clk_i) + begin : data_req_read_word_ff + data_read_req_word_index_q <= + data_req_read_word_i[HPDcacheCfg.reqWordIdxWidth +: + $clog2(HPDCACHE_DATA_REQ_RATIO)]; + end + end + + // Request data interface width is equal to the data RAM width + else begin : gen_req_width_eq_ram_width + assign data_read_req_word = data_read_words; + end + + // Mux the data according to the hit way + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.ways), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth), + .ONE_HOT_SEL (1'b1) + ) data_read_req_word_way_mux_i( + .data_i (data_read_req_word), + .sel_i (dir_hit_way_o), + .data_o (data_req_read_data_o) + ); + + + // Delay the accessed set for checking the tag from the directory in the + // next cycle (hit logic) + always_ff @(posedge clk_i) + begin : req_read_ff + if (dir_match_i || dir_amo_match_i || dir_cmo_check_nline_i || dir_inval_check_i) begin + dir_req_set_q <= dir_addr; + end + if (dir_cmo_check_entry_i) begin + dir_req_way_q <= dir_cmo_check_entry_way_i; + end + end + // }}} + + // Select flush data + // {{{ + hpdcache_data_ram_data_t + [HPDcacheCfg.u.accessWords-1:0] + data_flush_row_data; + + hpdcache_data_word_t + [HPDcacheCfg.u.dataWaysPerRamWord-1:0] + [HPDcacheCfg.u.accessWords-1:0] + data_flush_ways_data; + + hpdcache_data_ram_row_idx_t data_flush_row_index_q; + logic [HPDcacheCfg.u.dataWaysPerRamWord-1:0] data_flush_read_way; + + always_ff @(posedge clk_i) + begin : data_flush_row_index_ff + if (data_flush_read_i) data_flush_row_index_q <= data_ram_row; + end + + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.ways/HPDcacheCfg.u.dataWaysPerRamWord), + .DATA_WIDTH (HPDcacheCfg.accessWidth*HPDcacheCfg.u.dataWaysPerRamWord), + .ONE_HOT_SEL (1'b1) + ) data_read_flush_mux_row_i( + .data_i (data_rentry), + .sel_i (data_flush_row_index_q), + .data_o (data_flush_row_data) + ); + + for (gen_i = 0; gen_i < HPDcacheCfg.u.dataWaysPerRamWord; gen_i++) + begin : gen_data_flush_way_i + for (gen_j = 0; gen_j < HPDcacheCfg.u.accessWords; gen_j++) + begin : gen_data_flush_way_j + assign data_flush_ways_data[gen_i][gen_j] = data_flush_row_data[gen_j][gen_i]; + end + end + + always_comb + begin : decode_flush_read_way_comb + data_flush_read_way = '0; + for (int i = 0; i < HPDcacheCfg.u.dataWaysPerRamWord; i++) begin + for (int j = 0; j < HPDcacheCfg.u.ways; j += HPDcacheCfg.u.dataWaysPerRamWord) begin + data_flush_read_way[i] |= data_flush_read_way_i[i + j]; + end + end + end + + hpdcache_mux #( + .NINPUT (HPDcacheCfg.u.dataWaysPerRamWord), + .DATA_WIDTH (HPDcacheCfg.accessWidth), + .ONE_HOT_SEL (1'b1) + ) data_read_flush_mux_way_i( + .data_i (data_flush_ways_data), + .sel_i (data_flush_read_way), + .data_o (data_flush_read_data_o) + ); + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + for (gen_i = 0; gen_i < HPDcacheCfg.u.ways; gen_i++) begin : gen_check_dirty_state + check_dirty_state: assert property (@(posedge clk_i) disable iff (!rst_ni || !init_q) + (dir_cs[gen_i] & ~dir_we[gen_i]) |=> (dir_dirty[gen_i] |-> dir_valid[gen_i])) else + $error("hpdcache_memctrl: wrong directory state - dirty but not valid"); + end + + concurrent_dir_access_assert: assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot0({dir_match_i, + dir_amo_match_i, + dir_refill_i, + dir_inval_check_i, + dir_inval_write_i, + dir_cmo_check_nline_i, + dir_cmo_check_entry_i, + dir_cmo_updt_i, + dir_updt_i})) else + $error("hpdcache_memctrl: more than one process is accessing the cache directory"); + + concurrent_data_access_assert: assert property (@(posedge clk_i) disable iff (!rst_ni) + $onehot0({data_req_read_i, + data_req_write_i, + data_amo_write_i, + data_refill_i, + data_flush_read_i})) else + $error("hpdcache_memctrl: more than one process is accessing the cache data"); +`endif + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv new file mode 100644 index 0000000000..76ac353e33 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv @@ -0,0 +1,751 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache Miss Handler + * History : + */ +module hpdcache_miss_handler +// {{{ +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_word_t = logic, + + parameter type hpdcache_way_vector_t = logic, + parameter type hpdcache_way_t = logic, + + parameter type hpdcache_dir_entry_t = logic, + + parameter type hpdcache_refill_data_t = logic, + + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_resp_r_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Global control signals + // {{{ + output logic mshr_empty_o, + output logic mshr_full_o, + // }}} + + // Configuration signals + // {{{ + input logic cfg_prefetch_updt_sel_victim_i, + // }}} + + // CHECK interface + // {{{ + input logic mshr_check_i, + input hpdcache_req_offset_t mshr_check_offset_i, + input hpdcache_nline_t mshr_check_nline_i, + output logic mshr_check_hit_o, + // }}} + + // MISS interface + // {{{ + // MISS request interface + output logic mshr_alloc_ready_o, + input logic mshr_alloc_i, + input logic mshr_alloc_cs_i, + input hpdcache_nline_t mshr_alloc_nline_i, + output logic mshr_alloc_full_o, + input hpdcache_req_tid_t mshr_alloc_tid_i, + input hpdcache_req_sid_t mshr_alloc_sid_i, + input hpdcache_word_t mshr_alloc_word_i, + input hpdcache_way_vector_t mshr_alloc_victim_way_i, + input logic mshr_alloc_need_rsp_i, + input logic mshr_alloc_is_prefetch_i, + input logic mshr_alloc_wback_i, + + // REFILL MISS / Invalidation interface + input logic refill_req_ready_i, + output logic refill_req_valid_o, + output logic refill_is_error_o, + output logic refill_busy_o, + output logic refill_updt_sel_victim_o, + output hpdcache_set_t refill_set_o, + output hpdcache_way_vector_t refill_way_o, + output hpdcache_dir_entry_t refill_dir_entry_o, + output logic refill_write_dir_o, + output logic refill_write_data_o, + output hpdcache_refill_data_t refill_data_o, + output hpdcache_word_t refill_word_o, + output hpdcache_nline_t refill_nline_o, + output logic refill_updt_rtab_o, + + output logic inval_check_dir_o, + output logic inval_write_dir_o, + output hpdcache_nline_t inval_nline_o, + input logic inval_hit_i, + + // REFILL core response interface + output logic refill_core_rsp_valid_o, + output hpdcache_rsp_t refill_core_rsp_o, + // }}} + + // MEMORY interface + // {{{ + input logic mem_req_ready_i, + output logic mem_req_valid_o, + output hpdcache_mem_req_t mem_req_o, + + output logic mem_resp_ready_o, + input logic mem_resp_valid_i, + input hpdcache_mem_resp_r_t mem_resp_i, + input logic mem_resp_inval_i, + input hpdcache_nline_t mem_resp_inval_nline_i + // }}} +); +// }}} + + // Declaration of constants and types + // {{{ + localparam hpdcache_uint REFILL_REQ_RATIO = HPDcacheCfg.u.accessWords / + HPDcacheCfg.u.reqWords; + localparam hpdcache_uint REFILL_LAST_CHUNK_WORD = HPDcacheCfg.u.clWords - + HPDcacheCfg.u.accessWords; + + typedef enum logic { + MISS_REQ_IDLE = 1'b0, + MISS_REQ_SEND = 1'b1 + } miss_req_fsm_e; + + typedef enum { + REFILL_IDLE, + REFILL_WRITE, + REFILL_WRITE_DIR, + REFILL_INVAL + } refill_fsm_e; + + typedef struct packed { + hpdcache_mem_error_e r_error; + hpdcache_mem_id_t r_id; + logic is_inval; + hpdcache_nline_t inval_nline; + } mem_resp_metadata_t; + + typedef logic [HPDcacheCfg.mshrWayWidth-1:0] mshr_way_t; + typedef logic [HPDcacheCfg.mshrSetWidth-1:0] mshr_set_t; + // }}} + + // Declaration of internal signals and registers + // {{{ + miss_req_fsm_e miss_req_fsm_q, miss_req_fsm_d; + mshr_way_t mshr_alloc_way_q, mshr_alloc_way_d; + hpdcache_nline_t mshr_alloc_nline_q; + + refill_fsm_e refill_fsm_q, refill_fsm_d; + hpdcache_set_t refill_set_q; + hpdcache_tag_t refill_tag_q; + hpdcache_way_t refill_way_q; + hpdcache_req_sid_t refill_sid_q; + hpdcache_req_tid_t refill_tid_q; + hpdcache_word_t refill_cnt_q, refill_cnt_d; + logic refill_need_rsp_q; + logic refill_is_prefetch_q; + logic refill_wback_q; + hpdcache_word_t refill_core_rsp_word_q; + hpdcache_way_t refill_way; + + mem_resp_metadata_t refill_fifo_resp_meta_wdata, refill_fifo_resp_meta_rdata; + logic refill_fifo_resp_meta_w, refill_fifo_resp_meta_wok; + logic refill_fifo_resp_meta_r, refill_fifo_resp_meta_rok; + + logic refill_fifo_resp_data_w, refill_fifo_resp_data_wok; + hpdcache_refill_data_t refill_fifo_resp_data_rdata; + logic refill_fifo_resp_data_r; + + logic refill_core_rsp_valid; + hpdcache_req_data_t refill_core_rsp_rdata; + hpdcache_req_sid_t refill_core_rsp_sid; + hpdcache_req_tid_t refill_core_rsp_tid; + logic refill_core_rsp_error; + hpdcache_word_t refill_core_rsp_word; + hpdcache_rsp_t refill_core_rsp; + + hpdcache_set_t mshr_check_set; + hpdcache_tag_t mshr_check_tag; + logic mshr_alloc; + logic mshr_alloc_cs; + hpdcache_way_t mshr_alloc_victim_way; + logic mshr_ack; + logic mshr_ack_cs; + mshr_set_t mshr_ack_set; + mshr_way_t mshr_ack_way; + hpdcache_set_t mshr_ack_cache_set; + hpdcache_way_t mshr_ack_cache_way; + hpdcache_tag_t mshr_ack_cache_tag; + hpdcache_req_sid_t mshr_ack_src_id; + hpdcache_req_tid_t mshr_ack_req_id; + hpdcache_word_t mshr_ack_word; + logic mshr_ack_need_rsp; + logic mshr_ack_is_prefetch; + logic mshr_ack_wback; + logic mshr_empty; + // }}} + + // Miss Request FSM + // {{{ + always_comb + begin : miss_req_fsm_comb + mshr_alloc_ready_o = 1'b0; + mshr_alloc = 1'b0; + mshr_alloc_cs = 1'b0; + mem_req_valid_o = 1'b0; + + miss_req_fsm_d = miss_req_fsm_q; + + unique case (miss_req_fsm_q) + MISS_REQ_IDLE: begin + mshr_alloc_ready_o = 1'b1; + mshr_alloc = mshr_alloc_i; + mshr_alloc_cs = mshr_alloc_cs_i; + if (mshr_alloc_i) begin + miss_req_fsm_d = MISS_REQ_SEND; + end else begin + miss_req_fsm_d = MISS_REQ_IDLE; + end + end + MISS_REQ_SEND: begin + mem_req_valid_o = 1'b1; + if (mem_req_ready_i) begin + miss_req_fsm_d = MISS_REQ_IDLE; + end else begin + miss_req_fsm_d = MISS_REQ_SEND; + end + end + endcase + end + + localparam hpdcache_uint REFILL_REQ_SIZE = $clog2(HPDcacheCfg.u.memDataWidth / 8); + localparam hpdcache_uint REFILL_REQ_LEN = HPDcacheCfg.clWidth / HPDcacheCfg.u.memDataWidth; + + assign mem_req_o.mem_req_addr = {mshr_alloc_nline_q, {HPDcacheCfg.clOffsetWidth{1'b0}} }; + assign mem_req_o.mem_req_len = hpdcache_mem_len_t'(REFILL_REQ_LEN-1); + assign mem_req_o.mem_req_size = hpdcache_mem_size_t'(REFILL_REQ_SIZE); + assign mem_req_o.mem_req_command = HPDCACHE_MEM_READ; + assign mem_req_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_ADD; + assign mem_req_o.mem_req_cacheable = 1'b1; + + if ((HPDcacheCfg.u.mshrSets > 1) && (HPDcacheCfg.u.mshrWays > 1)) + begin : gen_mem_id_mshr_sets_and_ways_gt_1 + assign mem_req_o.mem_req_id = hpdcache_mem_id_t'({ + mshr_alloc_way_q, mshr_alloc_nline_q[0 +: HPDcacheCfg.mshrSetWidth]}); + end else if (HPDcacheCfg.u.mshrSets > 1) begin : gen_mem_id_mshr_sets_gt_1 + assign mem_req_o.mem_req_id = hpdcache_mem_id_t'( + mshr_alloc_nline_q[0 +: HPDcacheCfg.mshrSetWidth]); + end else if (HPDcacheCfg.u.mshrWays > 1) begin : gen_mem_id_mshr_ways_gt_1 + assign mem_req_o.mem_req_id = hpdcache_mem_id_t'(mshr_alloc_way_q); + end else begin : gen_mem_id_mshr_sets_and_ways_eq_1 + assign mem_req_o.mem_req_id = '0; + end + + always_ff @(posedge clk_i) + begin : miss_req_fsm_internal_ff + if (mshr_alloc) begin + mshr_alloc_way_q <= mshr_alloc_way_d; + mshr_alloc_nline_q <= mshr_alloc_nline_i; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin : miss_req_fsm_ff + if (!rst_ni) begin + miss_req_fsm_q <= MISS_REQ_IDLE; + end else begin + miss_req_fsm_q <= miss_req_fsm_d; + end + end + // }}} + + // Refill FSM + // {{{ + + // ask permission to the refill arbiter if there is a pending refill + assign refill_req_valid_o = refill_fsm_q == REFILL_IDLE ? refill_fifo_resp_meta_rok : 1'b0; + + always_comb + begin : miss_resp_fsm_comb + refill_updt_sel_victim_o = 1'b0; + refill_set_o = '0; + refill_way = '0; + refill_write_dir_o = 1'b0; + refill_write_data_o = 1'b0; + refill_updt_rtab_o = 1'b0; + refill_cnt_d = refill_cnt_q; + + inval_check_dir_o = 1'b0; + inval_write_dir_o = 1'b0; + + refill_core_rsp_valid = 1'b0; + refill_core_rsp_sid = '0; + refill_core_rsp_tid = '0; + refill_core_rsp_error = 1'b0; + refill_core_rsp_word = 0; + + refill_fifo_resp_meta_r = 1'b0; + refill_fifo_resp_data_r = 1'b0; + + mshr_ack_cs = 1'b0; + mshr_ack = 1'b0; + + refill_fsm_d = refill_fsm_q; + + case (refill_fsm_q) + // Wait for refill responses + // {{{ + REFILL_IDLE: begin + if (refill_fifo_resp_meta_rok) begin + // anticipate the activation of the MSHR independently of the grant signal from + // the refill arbiter. This is to avoid the introduction of unnecessary timing + // paths (however there could be a minor augmentation of the power consumption) + mshr_ack_cs = ~refill_fifo_resp_meta_rdata.is_inval; + + // if the permission is granted, start refilling + if (refill_req_ready_i) begin + refill_set_o = mshr_ack_cache_set; + + if (refill_fifo_resp_meta_rdata.is_inval) begin + // check for a match with the line being invalidated in the cache dir + inval_check_dir_o = 1'b1; + + refill_fsm_d = REFILL_INVAL; + end else begin + // read the MSHR and reset the valid bit for the corresponding entry + mshr_ack = ~refill_fifo_resp_meta_rdata.is_inval; + + // initialize the counter for refill words + refill_cnt_d = 0; + refill_fsm_d = REFILL_WRITE; + end + end + end + end + // }}} + + // Write refill data into the cache + // {{{ + REFILL_WRITE: begin + automatic logic is_prefetch; + automatic hpdcache_uint core_rsp_word; + + // Respond to the core (when needed) + if (refill_cnt_q == 0) begin + core_rsp_word = hpdcache_uint'(mshr_ack_word)/HPDcacheCfg.u.accessWords; + + if (mshr_ack_need_rsp) begin + refill_core_rsp_valid = (hpdcache_uint'(core_rsp_word) == 0); + end + + refill_core_rsp_sid = mshr_ack_src_id; + refill_core_rsp_tid = mshr_ack_req_id; + refill_core_rsp_error = refill_is_error_o; + refill_core_rsp_word = hpdcache_word_t'( + hpdcache_uint'(mshr_ack_word)/HPDcacheCfg.u.reqWords); + end else begin + core_rsp_word = hpdcache_uint'(refill_core_rsp_word_q)/ + HPDcacheCfg.u.accessWords; + + if (refill_need_rsp_q) begin + automatic hpdcache_uint refill_cnt; + refill_cnt = hpdcache_uint'(refill_cnt_q)/HPDcacheCfg.u.accessWords; + refill_core_rsp_valid = (core_rsp_word == refill_cnt); + end + + refill_core_rsp_sid = refill_sid_q; + refill_core_rsp_tid = refill_tid_q; + refill_core_rsp_error = refill_is_error_o; + refill_core_rsp_word = hpdcache_word_t'( + hpdcache_uint'(refill_core_rsp_word_q)/HPDcacheCfg.u.reqWords); + end + + // Write the the data in the cache data array + if (refill_cnt_q == 0) begin + refill_set_o = mshr_ack_cache_set; + refill_way = mshr_ack_cache_way; + is_prefetch = mshr_ack_is_prefetch; + end else begin + refill_set_o = refill_set_q; + refill_way = refill_way_q; + is_prefetch = refill_is_prefetch_q; + end + refill_write_data_o = ~refill_is_error_o; + + // Consume chunk of data from the FIFO buffer in the memory interface + refill_fifo_resp_data_r = 1'b1; + + // Update directory on the last chunk of data + refill_cnt_d = refill_cnt_q + hpdcache_word_t'(HPDcacheCfg.u.accessWords); + + if (hpdcache_uint'(refill_cnt_q) == REFILL_LAST_CHUNK_WORD) begin + if (REFILL_LAST_CHUNK_WORD == 0) begin + // Special case: if the cache-line data can be written in a single cycle, + // wait an additional cycle to write the directory. This allows to prevent + // a RAM-to-RAM timing path between the MSHR and the DIR. + refill_fsm_d = REFILL_WRITE_DIR; + end else begin + // Write the new entry in the cache directory + refill_write_dir_o = 1'b1; + + // Update the victim selection. Only in the following cases: + // - There is no error in response AND + // - It is a prefetch and the cfg_prefetch_updt_sel_victim_i is set OR + // - It is a read miss. + refill_updt_sel_victim_o = ~refill_is_error_o & + (~is_prefetch | cfg_prefetch_updt_sel_victim_i); + + // Update dependency flags in the retry table + refill_updt_rtab_o = 1'b1; + + // consume the response from the network + refill_fifo_resp_meta_r = 1'b1; + + refill_fsm_d = REFILL_IDLE; + end + end + end + // }}} + + // Write cache directory (this state is only visited when ACCESS_WORDS == CL_WORDS, + // this is when the entire cache-line can be written in a single cycle) + // {{{ + REFILL_WRITE_DIR: begin + // Select the target set and way + refill_set_o = refill_set_q; + refill_way = refill_way_q; + + // Write the new entry in the cache directory + refill_write_dir_o = 1'b1; + + // Update the victim selection. Only in the following cases: + // - There is no error in response AND + // - It is a prefetch and the cfg_prefetch_updt_sel_victim_i is set OR + // - It is a read miss. + refill_updt_sel_victim_o = ~refill_is_error_o & + (~refill_is_prefetch_q | cfg_prefetch_updt_sel_victim_i); + + // Update dependency flags in the retry table + refill_updt_rtab_o = 1'b1; + + // consume the response from the network + refill_fifo_resp_meta_r = 1'b1; + + refill_fsm_d = REFILL_IDLE; + end + // }}} + + // Invalidate the target cacheline (if it matches a valid cacheline) + // {{{ + REFILL_INVAL: begin + // Invalidate if there is a match + inval_write_dir_o = inval_hit_i; + + // consume the invalidation from the network + refill_fifo_resp_meta_r = 1'b1; + + refill_fsm_d = REFILL_IDLE; + end + + default: begin +`ifndef HPDCACHE_ASSERT_OFF + assert (1) $error("miss_handler: illegal state"); +`endif + end + endcase + end + + assign refill_is_error_o = (refill_fifo_resp_meta_rdata.r_error == HPDCACHE_MEM_RESP_NOK); + + assign refill_busy_o = (refill_fsm_q != REFILL_IDLE); + assign refill_nline_o = {refill_tag_q, refill_set_q}; + assign refill_word_o = refill_cnt_q; + + assign inval_nline_o = refill_fifo_resp_meta_rdata.inval_nline; + + assign mshr_check_tag = mshr_check_nline_i[HPDcacheCfg.setWidth +: HPDcacheCfg.tagWidth]; + assign mshr_check_set = mshr_check_offset_i[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.setWidth]; + + if (HPDcacheCfg.u.mshrSets > 1) begin : gen_mshr_set_gt_1 + // MSHR ack set and way + assign mshr_ack_set = refill_fifo_resp_meta_rdata.r_id[0 +: HPDcacheCfg.mshrSetWidth]; + if (HPDcacheCfg.u.mshrWays > 1) begin : gen_mshr_ack_way_gt_1 + assign mshr_ack_way = refill_fifo_resp_meta_rdata.r_id[HPDcacheCfg.mshrSetWidth +: + HPDcacheCfg.mshrWayWidth]; + end else begin : gen_mshr_ack_way_eq_1 + assign mshr_ack_way = '0; + end + end else begin : gen_mshr_set_eq_1 + // MSHR ack set and way + assign mshr_ack_set = '0; + if (HPDcacheCfg.u.mshrWays > 1) begin : gen_mshr_ack_way_gt_1 + assign mshr_ack_way = refill_fifo_resp_meta_rdata.r_id[0 +: HPDcacheCfg.mshrWayWidth]; + end else begin : gen_mshr_ack_way_eq_1 + assign mshr_ack_way = '0; + end + end + + // Write the new entry in the cache directory + // In case of error in the refill response, invalidate pre-allocated cache directory entry + assign refill_dir_entry_o = '{ + valid : ~refill_is_error_o, + wback : ~refill_is_error_o & refill_wback_q, + dirty : 1'b0, + fetch : 1'b0, + tag : refill_tag_q, + default :'0 + }; + + assign refill_core_rsp.rdata = refill_core_rsp_rdata; + assign refill_core_rsp.sid = refill_core_rsp_sid; + assign refill_core_rsp.tid = refill_core_rsp_tid; + assign refill_core_rsp.error = refill_core_rsp_error; + assign refill_core_rsp.aborted = 1'b0; + + hpdcache_fifo_reg #( + .FIFO_DEPTH (1), + .FEEDTHROUGH (HPDcacheCfg.u.refillCoreRspFeedthrough), + .fifo_data_t (hpdcache_rsp_t) + ) i_refill_core_rsp_buf( + .clk_i, + .rst_ni, + .w_i (refill_core_rsp_valid), + .wok_o (/*unused*/), + .wdata_i (refill_core_rsp), + .r_i (1'b1), // core shall always be ready to consume a response + .rok_o (refill_core_rsp_valid_o), + .rdata_o (refill_core_rsp_o) + ); + + // refill's width is bigger than the width of the core's interface + if (REFILL_REQ_RATIO > 1) begin : gen_core_rsp_data_mux + hpdcache_mux #( + .NINPUT (REFILL_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth) + ) data_read_rsp_mux_i( + .data_i (refill_data_o), + .sel_i (refill_core_rsp_word[0 +: $clog2(REFILL_REQ_RATIO)]), + .data_o (refill_core_rsp_rdata) + ); + end + + // refill's width is equal to the width of the core's interface + else begin : gen_core_rsp_eqsize + assign refill_core_rsp_rdata = refill_data_o; + end + + /* FIXME: when multiple chunks, in case of error, the error bit is not + * necessarily set on all chunks */ + assign refill_fifo_resp_meta_wdata = '{ + r_error : mem_resp_i.mem_resp_r_error, + r_id : mem_resp_i.mem_resp_r_id, + is_inval : mem_resp_inval_i, + inval_nline: mem_resp_inval_nline_i + }; + + hpdcache_fifo_reg #( + .FIFO_DEPTH (HPDcacheCfg.u.refillFifoDepth), + .fifo_data_t (mem_resp_metadata_t) + ) i_r_metadata_fifo ( + .clk_i, + .rst_ni, + + .w_i (refill_fifo_resp_meta_w), + .wok_o (refill_fifo_resp_meta_wok), + .wdata_i(refill_fifo_resp_meta_wdata), + + .r_i (refill_fifo_resp_meta_r), + .rok_o (refill_fifo_resp_meta_rok), + .rdata_o(refill_fifo_resp_meta_rdata) + ); + + hpdcache_data_resize #( + .WR_WIDTH (HPDcacheCfg.u.memDataWidth), + .RD_WIDTH (HPDcacheCfg.accessWidth), + .DEPTH (HPDcacheCfg.u.refillFifoDepth) + ) i_data_resize( + .clk_i, + .rst_ni, + + .w_i (refill_fifo_resp_data_w), + .wok_o (refill_fifo_resp_data_wok), + .wdata_i(mem_resp_i.mem_resp_r_data), + .wlast_i(mem_resp_i.mem_resp_r_last), + + .r_i (refill_fifo_resp_data_r), + .rok_o (/* unused */), + .rdata_o(refill_fifo_resp_data_rdata), + .rlast_o(/* unused */) + ); + + assign refill_data_o = refill_fifo_resp_data_rdata; + + // The DATA fifo is only used for refill responses + assign refill_fifo_resp_data_w = mem_resp_valid_i & + ((refill_fifo_resp_meta_wok | ~mem_resp_i.mem_resp_r_last) & + ~mem_resp_inval_i); + + // The METADATA fifo is used for both refill responses and invalidations + assign refill_fifo_resp_meta_w = mem_resp_valid_i & + ((refill_fifo_resp_data_wok & mem_resp_i.mem_resp_r_last) | + mem_resp_inval_i); + + always_comb + begin : mem_resp_ready_comb + mem_resp_ready_o = 1'b0; + if (mem_resp_valid_i) begin + if (mem_resp_inval_i) begin + mem_resp_ready_o = refill_fifo_resp_meta_wok; + end else begin + mem_resp_ready_o = (refill_fifo_resp_meta_wok | ~mem_resp_i.mem_resp_r_last) & + refill_fifo_resp_data_wok; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin : miss_resp_fsm_ff + if (!rst_ni) begin + refill_fsm_q <= REFILL_IDLE; + end else begin + refill_fsm_q <= refill_fsm_d; + end + end + + always_ff @(posedge clk_i) + begin : miss_resp_fsm_internal_ff + if ((refill_fsm_q == REFILL_WRITE) && (refill_cnt_q == 0)) begin + refill_set_q <= mshr_ack_cache_set; + refill_way_q <= mshr_ack_cache_way; + refill_tag_q <= mshr_ack_cache_tag; + refill_sid_q <= mshr_ack_src_id; + refill_tid_q <= mshr_ack_req_id; + refill_need_rsp_q <= mshr_ack_need_rsp; + refill_is_prefetch_q <= mshr_ack_is_prefetch; + refill_wback_q <= mshr_ack_wback; + refill_core_rsp_word_q <= mshr_ack_word; + end + refill_cnt_q <= refill_cnt_d; + end + // }}} + // }}} + + // Miss Status Holding Register component + // {{{ + hpdcache_mshr #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_word_t (hpdcache_word_t), + .hpdcache_way_t (hpdcache_way_t), + + .hpdcache_req_tid_t (hpdcache_req_tid_t), + .hpdcache_req_sid_t (hpdcache_req_sid_t), + + .mshr_way_t (mshr_way_t), + .mshr_set_t (mshr_set_t) + ) hpdcache_mshr_i( + .clk_i, + .rst_ni, + + .empty_o (mshr_empty), + .full_o (mshr_full_o), + + .check_i (mshr_check_i), + .check_set_i (mshr_check_set), + .check_tag_i (mshr_check_tag), + .hit_o (mshr_check_hit_o), + .alloc_i (mshr_alloc), + .alloc_cs_i (mshr_alloc_cs), + .alloc_nline_i (mshr_alloc_nline_i), + .alloc_req_id_i (mshr_alloc_tid_i), + .alloc_src_id_i (mshr_alloc_sid_i), + .alloc_word_i (mshr_alloc_word_i), + .alloc_victim_way_i (mshr_alloc_victim_way), + .alloc_need_rsp_i (mshr_alloc_need_rsp_i), + .alloc_is_prefetch_i (mshr_alloc_is_prefetch_i), + .alloc_wback_i (mshr_alloc_wback_i), + .alloc_full_o (mshr_alloc_full_o), + .alloc_way_o (mshr_alloc_way_d), + + .ack_i (mshr_ack), + .ack_cs_i (mshr_ack_cs), + .ack_set_i (mshr_ack_set), + .ack_way_i (mshr_ack_way), + .ack_req_id_o (mshr_ack_req_id), + .ack_src_id_o (mshr_ack_src_id), + .ack_cache_set_o (mshr_ack_cache_set), + .ack_cache_way_o (mshr_ack_cache_way), + .ack_cache_tag_o (mshr_ack_cache_tag), + .ack_word_o (mshr_ack_word), + .ack_need_rsp_o (mshr_ack_need_rsp), + .ack_is_prefetch_o (mshr_ack_is_prefetch), + .ack_wback_o (mshr_ack_wback) + ); + + hpdcache_1hot_to_binary #(.N(HPDcacheCfg.u.ways)) victim_way_encoder_i( + .val_i(mshr_alloc_victim_way_i), + .val_o(mshr_alloc_victim_way) + ); + + hpdcache_decoder #(.N(HPDcacheCfg.wayIndexWidth)) victim_way_decoder_i( + .en_i (refill_busy_o), + .val_i(refill_way), + .val_o(refill_way_o) + ); + + // Indicate to the cache controller that there is no pending miss. This + // is, when the MSHR is empty, and the MISS handler has finished of + // processing the last miss response. + assign mshr_empty_o = mshr_empty & ~refill_busy_o; + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF +`endif + // }}} + +endmodule +// }}} diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv new file mode 100644 index 0000000000..34d55d3c69 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv @@ -0,0 +1,410 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache Miss Status Holding Register (MSHR) + * History : + */ +module hpdcache_mshr +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_word_t = logic, + parameter type hpdcache_way_t = logic, + + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_sid_t = logic, + + parameter type mshr_way_t = logic, + parameter type mshr_set_t = logic +) + // }}} + + // Ports + // {{{ +( + // Clock and reset signals + input logic clk_i, + input logic rst_ni, + + // Global control signals + output logic empty_o, + output logic full_o, + + // Check and allocation interface + input logic check_i, + input hpdcache_set_t check_set_i, + input hpdcache_tag_t check_tag_i, + output logic hit_o, + input logic alloc_i, + input logic alloc_cs_i, + input hpdcache_nline_t alloc_nline_i, + input hpdcache_req_tid_t alloc_req_id_i, + input hpdcache_req_sid_t alloc_src_id_i, + input hpdcache_word_t alloc_word_i, + input hpdcache_way_t alloc_victim_way_i, + input logic alloc_need_rsp_i, + input logic alloc_is_prefetch_i, + input logic alloc_wback_i, + output logic alloc_full_o, + output mshr_way_t alloc_way_o, + + // Acknowledge interface + input logic ack_i, + input logic ack_cs_i, + input mshr_set_t ack_set_i, + input mshr_way_t ack_way_i, + output hpdcache_req_tid_t ack_req_id_o, + output hpdcache_req_sid_t ack_src_id_o, + output hpdcache_set_t ack_cache_set_o, + output hpdcache_way_t ack_cache_way_o, + output hpdcache_tag_t ack_cache_tag_o, + output hpdcache_word_t ack_word_o, + output logic ack_need_rsp_o, + output logic ack_is_prefetch_o, + output logic ack_wback_o +); + // }}} + + // Definition of constants and types + // {{{ + typedef struct packed { + hpdcache_tag_t tag; + hpdcache_req_tid_t req_id; + hpdcache_req_sid_t src_id; + hpdcache_word_t word_idx; + hpdcache_way_t victim_way_idx; + logic wback; + logic need_rsp; + logic is_prefetch; + } mshr_entry_t; + + + // Compute the width of MSHR entries depending on the support of write + // bitmask or not (write byte enable) + localparam int unsigned HPDCACHE_MSHR_ENTRY_BITS = $bits(mshr_entry_t); + + localparam int unsigned HPDCACHE_MSHR_RAM_ENTRY_BITS = + HPDcacheCfg.u.mshrRamByteEnable ? + ((HPDCACHE_MSHR_ENTRY_BITS + 7)/8) * 8 : // align to 8 bits + HPDCACHE_MSHR_ENTRY_BITS; // or use the exact number of bits + + typedef logic [HPDCACHE_MSHR_RAM_ENTRY_BITS-1:0] mshr_sram_data_t; + // }}} + + // Definition of internal wires and registers + // {{{ + logic [HPDcacheCfg.u.mshrSets*HPDcacheCfg.u.mshrWays-1:0] mshr_valid_q; + hpdcache_set_t [HPDcacheCfg.u.mshrSets*HPDcacheCfg.u.mshrWays-1:0] mshr_cache_set_q; + + hpdcache_set_t check_cache_set_q; + mshr_set_t check_set_st0, check_set_st1; + mshr_set_t alloc_set; + mshr_way_t ack_way_q; + + logic [HPDcacheCfg.u.mshrSets*HPDcacheCfg.u.mshrWays-1:0] mshr_valid_set, mshr_valid_rst; + mshr_entry_t [HPDcacheCfg.u.mshrWays-1:0] mshr_wentry; + mshr_sram_data_t [HPDcacheCfg.u.mshrWays-1:0] mshr_wdata; + mshr_entry_t [HPDcacheCfg.u.mshrWays-1:0] mshr_rentry; + mshr_sram_data_t [HPDcacheCfg.u.mshrWays-1:0] mshr_rdata; + + logic mshr_we; + logic mshr_cs; + mshr_set_t mshr_addr; + logic check; + // }}} + + // Control part for the allocation and check operations + // {{{ + + // The allocation operation is prioritary with respect to the check operation + assign check = check_i & ~alloc_i; + + if (HPDcacheCfg.u.mshrSets > 1) begin : gen_alloc_mshr_sets_gt_1 + assign check_set_st0 = check_set_i[0 +: HPDcacheCfg.mshrSetWidth]; + assign check_set_st1 = check_cache_set_q[0 +: HPDcacheCfg.mshrSetWidth]; + assign alloc_set = alloc_nline_i[0 +: HPDcacheCfg.mshrSetWidth]; + end else begin : gen_alloc_mshr_sets_eq_1 + assign check_set_st0 = '0; + assign check_set_st1 = '0; + assign alloc_set = '0; + end + + // Look for an available way in case of allocation + always_comb + begin + automatic mshr_way_t found_available_way; + + found_available_way = 0; + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + if (!mshr_valid_q[i*HPDcacheCfg.u.mshrSets + hpdcache_uint32'(alloc_set)]) begin + found_available_way = mshr_way_t'(i); + break; + end + end + alloc_way_o = found_available_way; + end + + // Look if the mshr can accept the checked nline (in case of allocation) + always_comb + begin + automatic bit found_available; + + found_available = 1'b0; + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + if (!mshr_valid_q[i*HPDcacheCfg.u.mshrSets + hpdcache_uint32'(check_set_st1)]) begin + found_available = 1'b1; + break; + end + end + alloc_full_o = ~found_available; + end + + // Write when there is an allocation operation + assign mshr_we = alloc_i; + + // Generate write data and mask depending on the available way + always_comb + begin + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + mshr_wentry[i].tag = alloc_nline_i[HPDcacheCfg.setWidth +: HPDcacheCfg.tagWidth]; + mshr_wentry[i].req_id = alloc_req_id_i; + mshr_wentry[i].src_id = alloc_src_id_i; + mshr_wentry[i].word_idx = alloc_word_i; + mshr_wentry[i].victim_way_idx = alloc_victim_way_i; + mshr_wentry[i].need_rsp = alloc_need_rsp_i; + mshr_wentry[i].is_prefetch = alloc_is_prefetch_i; + mshr_wentry[i].wback = alloc_wback_i; + end + end + // }}} + + // Shared control signals + // {{{ + hpdcache_uint mshr_alloc_slot; + hpdcache_uint mshr_ack_slot; + + if ((HPDcacheCfg.u.mshrSets > 1) && (HPDcacheCfg.u.mshrWays > 1)) + begin : gen_mshr_set_associative + assign mshr_alloc_slot = hpdcache_uint'({alloc_way_o, alloc_set}); + assign mshr_ack_slot = hpdcache_uint'({ ack_way_i, ack_set_i}); + end else if (HPDcacheCfg.u.mshrSets > 1) begin : gen_mshr_direct_mapped + assign mshr_alloc_slot = hpdcache_uint'(alloc_set); + assign mshr_ack_slot = hpdcache_uint'(ack_set_i); + end else if (HPDcacheCfg.u.mshrWays > 1) begin : gen_mshr_fully_associative + assign mshr_alloc_slot = hpdcache_uint'(alloc_way_o); + assign mshr_ack_slot = hpdcache_uint'(ack_way_i); + end else begin : gen_mshr_single_entry + assign mshr_alloc_slot = '0; + assign mshr_ack_slot = '0; + end + + assign mshr_cs = check_i | alloc_cs_i | ack_cs_i; + assign mshr_addr = ack_i ? ack_set_i : (alloc_i ? alloc_set : check_set_st0); + + always_comb + begin : mshr_valid_comb + for (hpdcache_uint i = 0; i < HPDcacheCfg.u.mshrSets*HPDcacheCfg.u.mshrWays; i++) begin + mshr_valid_rst[i] = (i == mshr_ack_slot) ? ack_i : 1'b0; + mshr_valid_set[i] = (i == mshr_alloc_slot) ? alloc_i : 1'b0; + end + end + // }}} + + // Read interface (ack) + // {{{ + assign ack_cache_set_o = mshr_cache_set_q[mshr_ack_slot]; + assign ack_cache_way_o = mshr_rentry[ack_way_q].victim_way_idx; + assign ack_cache_tag_o = mshr_rentry[ack_way_q].tag; + assign ack_req_id_o = mshr_rentry[ack_way_q].req_id; + assign ack_src_id_o = mshr_rentry[ack_way_q].src_id; + assign ack_word_o = mshr_rentry[ack_way_q].word_idx; + assign ack_need_rsp_o = mshr_rentry[ack_way_q].need_rsp; + assign ack_is_prefetch_o = mshr_rentry[ack_way_q].is_prefetch; + assign ack_wback_o = mshr_rentry[ack_way_q].wback; + // }}} + + // Global control signals + // {{{ + assign empty_o = ~|mshr_valid_q; + assign full_o = &mshr_valid_q; + + always_comb + begin : hit_comb + automatic bit [HPDcacheCfg.u.mshrWays-1:0] v_hit_way; + + for (int unsigned w = 0; w < HPDcacheCfg.u.mshrWays; w++) begin + automatic bit v_valid; + hpdcache_uint32 v_check_set_st1; + hpdcache_set_t v_check_set; + automatic bit v_match_set; + automatic bit v_match_tag; + + v_valid = mshr_valid_q[w*HPDcacheCfg.u.mshrSets + hpdcache_uint32'(check_set_st1)]; + v_check_set_st1 = hpdcache_uint32'(check_set_st1); + v_check_set = mshr_cache_set_q[w*HPDcacheCfg.u.mshrSets + v_check_set_st1]; + v_match_set = (v_check_set == check_cache_set_q); + v_match_tag = (mshr_rentry[w].tag == check_tag_i); + v_hit_way[w] = (v_valid && v_match_tag && v_match_set); + end + + hit_o = |v_hit_way; + end + // }}} + + // Internal state assignment + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin : mshr_ff_set + if (!rst_ni) begin + mshr_valid_q <= '0; + ack_way_q <= '0; + check_cache_set_q <= '0; + end else begin + mshr_valid_q <= (~mshr_valid_q & mshr_valid_set) | (mshr_valid_q & ~mshr_valid_rst); + if (ack_i) ack_way_q <= ack_way_i; + if (check) check_cache_set_q <= check_set_i; + end + end + // }}} + + // Internal components + // {{{ + typedef logic [HPDCACHE_MSHR_RAM_ENTRY_BITS/8-1:0] mshr_sram_wbyteenable_t; + typedef logic [HPDCACHE_MSHR_RAM_ENTRY_BITS-1:0] mshr_sram_wmask_t; + if (HPDcacheCfg.u.mshrRamByteEnable) begin : gen_mshr_wbyteenable + mshr_sram_wbyteenable_t [HPDcacheCfg.u.mshrWays-1:0] mshr_wbyteenable; + + always_comb + begin : mshr_wbyteenable_comb + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + mshr_wbyteenable[i] = (hpdcache_uint32'(alloc_way_o) == i) ? '1 : '0; + end + end + + if (HPDcacheCfg.u.mshrUseRegbank) begin : gen_mshr_regbank + hpdcache_regbank_wbyteenable_1rw #( + .DATA_SIZE (HPDcacheCfg.u.mshrWays*HPDCACHE_MSHR_RAM_ENTRY_BITS), + .ADDR_SIZE (HPDcacheCfg.mshrSetWidth), + .DEPTH (HPDcacheCfg.u.mshrSets) + ) mshr_mem( + .clk (clk_i), + .rst_n (rst_ni), + .cs (mshr_cs), + .we (mshr_we), + .addr (mshr_addr), + .wbyteenable (mshr_wbyteenable), + .wdata (mshr_wdata), + .rdata (mshr_rdata) + ); + end else begin : gen_mshr_sram + hpdcache_sram_wbyteenable #( + .DATA_SIZE (HPDcacheCfg.u.mshrWays*HPDCACHE_MSHR_RAM_ENTRY_BITS), + .ADDR_SIZE (HPDcacheCfg.mshrSetWidth), + .DEPTH (HPDcacheCfg.u.mshrSets) + ) mshr_mem( + .clk (clk_i), + .rst_n (rst_ni), + .cs (mshr_cs), + .we (mshr_we), + .addr (mshr_addr), + .wbyteenable (mshr_wbyteenable), + .wdata (mshr_wdata), + .rdata (mshr_rdata) + ); + end + end else begin : gen_mshr_wmask + mshr_sram_wmask_t [HPDcacheCfg.u.mshrWays-1:0] mshr_wmask; + + always_comb + begin : mshr_wmask_comb + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + mshr_wmask[i] = (hpdcache_uint32'(alloc_way_o) == i) ? '1 : '0; + end + end + + if (HPDcacheCfg.u.mshrUseRegbank) begin : gen_mshr_regbank + hpdcache_regbank_wmask_1rw #( + .DATA_SIZE (HPDcacheCfg.u.mshrWays*HPDCACHE_MSHR_RAM_ENTRY_BITS), + .ADDR_SIZE (HPDcacheCfg.mshrSetWidth), + .DEPTH (HPDcacheCfg.u.mshrSets) + ) mshr_mem( + .clk (clk_i), + .rst_n (rst_ni), + .cs (mshr_cs), + .we (mshr_we), + .addr (mshr_addr), + .wmask (mshr_wmask), + .wdata (mshr_wdata), + .rdata (mshr_rdata) + ); + end else begin : gen_mshr_sram + hpdcache_sram_wmask #( + .DATA_SIZE (HPDcacheCfg.u.mshrWays*HPDCACHE_MSHR_RAM_ENTRY_BITS), + .ADDR_SIZE (HPDcacheCfg.mshrSetWidth), + .DEPTH (HPDcacheCfg.u.mshrSets) + ) mshr_mem( + .clk (clk_i), + .rst_n (rst_ni), + .cs (mshr_cs), + .we (mshr_we), + .addr (mshr_addr), + .wmask (mshr_wmask), + .wdata (mshr_wdata), + .rdata (mshr_rdata) + ); + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + mshr_cache_set_q <= '0; + end else begin + if (alloc_i) begin + mshr_cache_set_q[mshr_alloc_slot] <= alloc_nline_i[0 +: HPDcacheCfg.setWidth]; + end + end + end + + always_comb + begin : ram_word_fitting_comb + for (int unsigned i = 0; i < HPDcacheCfg.u.mshrWays; i++) begin + mshr_wdata[i] = mshr_sram_data_t'(mshr_wentry[i]); + mshr_rentry[i] = mshr_entry_t'(mshr_rdata[i][0 +: HPDCACHE_MSHR_ENTRY_BITS]); + end + end + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + one_command_assert: assert property (@(posedge clk_i) + (ack_i -> !(alloc_i || check_i))) else + $error("MSHR: ack with concurrent alloc or check"); +`endif + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv new file mode 100644 index 0000000000..7acb37234f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv @@ -0,0 +1,513 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Write-Through (WT), High-Throughput (HTPUT) HPDcache Package + * History : + */ +package hpdcache_pkg; + // Utility definitions + // {{{ + typedef logic unsigned [7:0] hpdcache_uint8; + typedef logic signed [7:0] hpdcache_int8; + typedef logic unsigned [31:0] hpdcache_uint32; + typedef logic signed [31:0] hpdcache_int32; + typedef logic unsigned [63:0] hpdcache_uint64; + typedef logic signed [63:0] hpdcache_int64; + typedef hpdcache_uint32 hpdcache_uint; + typedef hpdcache_int32 hpdcache_int; + // }}} + + // Definition of constants and types for HPDcache directory memory + // {{{ + // Victim selection policy + typedef enum logic { + HPDCACHE_VICTIM_RANDOM = 1'b0, + HPDCACHE_VICTIM_PLRU = 1'b1 + } hpdcache_victim_sel_policy_t; + // }}} + + // Definition of interface with requesters + // {{{ + typedef logic [2:0] hpdcache_req_size_t; + + // Definition of operation codes + // {{{ + typedef enum logic [4:0] { + HPDCACHE_REQ_LOAD = 5'h00, + HPDCACHE_REQ_STORE = 5'h01, + // RESERVED = 5'h02, + // RESERVED = 5'h03, + HPDCACHE_REQ_AMO_LR = 5'h04, + HPDCACHE_REQ_AMO_SC = 5'h05, + HPDCACHE_REQ_AMO_SWAP = 5'h06, + HPDCACHE_REQ_AMO_ADD = 5'h07, + HPDCACHE_REQ_AMO_AND = 5'h08, + HPDCACHE_REQ_AMO_OR = 5'h09, + HPDCACHE_REQ_AMO_XOR = 5'h0a, + HPDCACHE_REQ_AMO_MAX = 5'h0b, + HPDCACHE_REQ_AMO_MAXU = 5'h0c, + HPDCACHE_REQ_AMO_MIN = 5'h0d, + HPDCACHE_REQ_AMO_MINU = 5'h0e, + // RESERVED = 5'h0f, + HPDCACHE_REQ_CMO_FENCE = 5'h10, + HPDCACHE_REQ_CMO_PREFETCH = 5'h11, + HPDCACHE_REQ_CMO_INVAL_NLINE = 5'h12, + HPDCACHE_REQ_CMO_INVAL_ALL = 5'h13, + HPDCACHE_REQ_CMO_FLUSH_NLINE = 5'h14, + HPDCACHE_REQ_CMO_FLUSH_ALL = 5'h15, + HPDCACHE_REQ_CMO_FLUSH_INVAL_NLINE = 5'h16, + HPDCACHE_REQ_CMO_FLUSH_INVAL_ALL = 5'h17 + } hpdcache_req_op_t; + // }}} + + // Definition of Write Policy Hint + // {{{ + typedef enum logic[2:0] { + HPDCACHE_WR_POLICY_AUTO = 3'b001, + HPDCACHE_WR_POLICY_WB = 3'b010, + HPDCACHE_WR_POLICY_WT = 3'b100 + } hpdcache_wr_policy_hint_t; + // }}} + + // Definition of PMA flags + // {{{ + typedef struct packed + { + logic uncacheable; + logic io; // FIXME: for future use + + // Write Policy Hint + hpdcache_wr_policy_hint_t wr_policy_hint; + } hpdcache_pma_t; + // }}} + + // Definition of functions + // {{{ + function automatic int unsigned hpdcache_max(int unsigned x, int unsigned y); + return (x < y) ? y : x; + endfunction + + function automatic int unsigned hpdcache_min(int unsigned x, int unsigned y); + return (x < y) ? x : y; + endfunction + + function automatic logic is_load(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_LOAD: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_store(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_STORE: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_LR, + HPDCACHE_REQ_AMO_SC, + HPDCACHE_REQ_AMO_SWAP, + HPDCACHE_REQ_AMO_ADD, + HPDCACHE_REQ_AMO_AND, + HPDCACHE_REQ_AMO_OR, + HPDCACHE_REQ_AMO_XOR, + HPDCACHE_REQ_AMO_MAX, + HPDCACHE_REQ_AMO_MAXU, + HPDCACHE_REQ_AMO_MIN, + HPDCACHE_REQ_AMO_MINU: + return 1'b1; + default: + return 1'b0; + endcase + endfunction + + function automatic logic is_amo_lr(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_LR: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_sc(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_SC: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_swap(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_SWAP: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_add(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_ADD: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_and(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_AND: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_or(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_OR: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_xor(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_XOR: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_max(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_MAX: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_maxu(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_MAXU: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_min(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_MIN: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_amo_minu(input hpdcache_req_op_t op); + case (op) + HPDCACHE_REQ_AMO_MINU: return 1'b1; + default: return 1'b0; + endcase + endfunction + + function automatic logic is_cmo_inval(input hpdcache_req_op_t op); + return (op inside {HPDCACHE_REQ_CMO_INVAL_NLINE, HPDCACHE_REQ_CMO_INVAL_ALL}); + endfunction + + function automatic logic is_cmo_flush(input hpdcache_req_op_t op); + return (op inside {HPDCACHE_REQ_CMO_FLUSH_NLINE, + HPDCACHE_REQ_CMO_FLUSH_ALL, + HPDCACHE_REQ_CMO_FLUSH_INVAL_NLINE, + HPDCACHE_REQ_CMO_FLUSH_INVAL_ALL}); + endfunction + + function automatic logic is_cmo_fence(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_FENCE); + endfunction + + function automatic logic is_cmo_prefetch(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_PREFETCH); + endfunction + + function automatic logic is_cmo_inval_by_nline(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_INVAL_NLINE); + endfunction + + function automatic logic is_cmo_inval_all(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_INVAL_ALL); + endfunction + + function automatic logic is_cmo_flush_by_nline(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_FLUSH_NLINE); + endfunction + + function automatic logic is_cmo_flush_all(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_FLUSH_ALL); + endfunction + + function automatic logic is_cmo_flush_inval_by_nline(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_FLUSH_INVAL_NLINE); + endfunction + + function automatic logic is_cmo_flush_inval_all(input hpdcache_req_op_t op); + return (op == HPDCACHE_REQ_CMO_FLUSH_INVAL_ALL); + endfunction + + function automatic logic is_cmo(input hpdcache_req_op_t op); + return (is_cmo_flush(op) || + is_cmo_fence(op) || + is_cmo_inval(op) || + is_cmo_prefetch(op)); + endfunction + + // }}} + // }}} + + // Definition of interface with memory + // {{{ + typedef logic [7:0] hpdcache_mem_len_t; + typedef logic [2:0] hpdcache_mem_size_t; + + typedef enum logic [1:0] { + HPDCACHE_MEM_RESP_OK = 2'b00, + HPDCACHE_MEM_RESP_NOK = 2'b01 + } hpdcache_mem_error_e; + + typedef enum logic [1:0] { + HPDCACHE_MEM_READ = 2'b00, + HPDCACHE_MEM_WRITE = 2'b01, + HPDCACHE_MEM_ATOMIC = 2'b10 + // Reserved = 2'b11 - TODO: CMO ? + } hpdcache_mem_command_e; + + typedef enum logic [3:0] { + HPDCACHE_MEM_ATOMIC_ADD = 4'b0000, + HPDCACHE_MEM_ATOMIC_CLR = 4'b0001, + HPDCACHE_MEM_ATOMIC_SET = 4'b0010, + HPDCACHE_MEM_ATOMIC_EOR = 4'b0011, + HPDCACHE_MEM_ATOMIC_SMAX = 4'b0100, + HPDCACHE_MEM_ATOMIC_SMIN = 4'b0101, + HPDCACHE_MEM_ATOMIC_UMAX = 4'b0110, + HPDCACHE_MEM_ATOMIC_UMIN = 4'b0111, + HPDCACHE_MEM_ATOMIC_SWAP = 4'b1000, + // Reserved = 4'b1001, + // Reserved = 4'b1010, + // Reserved = 4'b1011, + HPDCACHE_MEM_ATOMIC_LDEX = 4'b1100, + HPDCACHE_MEM_ATOMIC_STEX = 4'b1101 + // Reserved = 4'b1110, + // Reserved = 4'b1111 + } hpdcache_mem_atomic_e; + + function automatic hpdcache_mem_size_t get_hpdcache_mem_size(int unsigned bytes); + if (bytes == 0) return 0; + else if (bytes <= 2) return 1; + else if (bytes <= 4) return 2; + else if (bytes <= 8) return 3; + else if (bytes <= 16) return 4; + else if (bytes <= 32) return 5; + else if (bytes <= 64) return 6; + else if (bytes <= 128) return 7; + else begin +`ifndef HPDCACHE_ASSERT_OFF + assert (1) $error("hpdcache: unsupported number of bytes"); +`endif + return 0; + end + endfunction + // }}} + + // Definition of constants and types for the uncacheable request handler (UC) + // {{{ + typedef struct packed { + logic is_ld; + logic is_st; + logic is_amo_lr; + logic is_amo_sc; + logic is_amo_swap; + logic is_amo_add; + logic is_amo_and; + logic is_amo_or; + logic is_amo_xor; + logic is_amo_max; + logic is_amo_maxu; + logic is_amo_min; + logic is_amo_minu; + } hpdcache_uc_op_t; + // }}} + + // Definition of constants and types for the CMO request handler (CMOH) + // {{{ + typedef struct packed { + logic is_flush_inval_by_nline; + logic is_flush_inval_all; + logic is_flush_by_nline; + logic is_flush_all; + logic is_inval_by_nline; + logic is_inval_all; + logic is_fence; + } hpdcache_cmoh_op_t; + // }}} + + // Definition Replay Table (RTAB) dependencies + // {{{ + typedef struct packed { + logic mshr_hit; + logic mshr_full; + logic mshr_ready; + logic write_miss; + logic wbuf_hit; + logic wbuf_not_ready; + logic dir_unavailable; + logic dir_fetch; + logic flush_hit; + logic flush_not_ready; + } hpdcache_rtab_deps_t; + // }}} + + // Definition of parameters + // {{{ + typedef struct packed { + // Number of requesters + int unsigned nRequesters; + // Physical Address Width + int unsigned paWidth; + // Word width (bits) + int unsigned wordWidth; + // Number of sets + int unsigned sets; + // Number of ways + int unsigned ways; + // Cache-Line width (bits) + int unsigned clWords; + // Number of words in the request data channels (request and response) + int unsigned reqWords; + // Request transaction ID width (bits) + int unsigned reqTransIdWidth; + // Request source ID width (bits) + int unsigned reqSrcIdWidth; + // Victim select + hpdcache_victim_sel_policy_t victimSel; + // Number of ways per RAM entry + int unsigned dataWaysPerRamWord; + // Number of sets per RAM + int unsigned dataSetsPerRam; + // DATA RAM macros implement write byte enable + // - Write byte enable (1'b1) + // - Write bit mask (1'b0) + bit dataRamByteEnable; + // Define the number of memory contiguous words that can be accessed + // simultaneously from the cache. + // - This limits the maximum width for the data channel from requesters + // - This impacts the refill latency (more ACCESS_WORDS -> less REFILL LATENCY) + int unsigned accessWords; + // MSHR number of sets + int unsigned mshrSets; + // MSHR number of ways + int unsigned mshrWays; + // MSHR number of ways in the same SRAM word (entry) + int unsigned mshrWaysPerRamWord; + // MSHR number of sets in the same SRAM + int unsigned mshrSetsPerRam; + // MSHR macros implement write byte enable + // - Write byte enable (1'b1) + // - Write bit mask (1'b0) + bit mshrRamByteEnable; + // MSHR uses whether FFs or SRAM + bit mshrUseRegbank; + // Use feedthrough FIFOs from the refill handler to the core + bit refillCoreRspFeedthrough; + // Depth of the refill FIFO + int refillFifoDepth; + // Write-Buffer number of entries in the directory + int unsigned wbufDirEntries; + // Write-Buffer number of entries in the data buffer + int unsigned wbufDataEntries; + // Write-Buffer number of words per entry + int unsigned wbufWords; + // Write-Buffer threshold counter width (in bits) + int unsigned wbufTimecntWidth; + // Number of entries in the replay table + int unsigned rtabEntries; + // Number of entries in the flush directory + int unsigned flushEntries; + // Depth of the flush FIFO + int unsigned flushFifoDepth; + // Width of the address in the memory interface + int unsigned memAddrWidth; + // Width of the ID in the memory interface + int unsigned memIdWidth; + // Width of the data in the memory interface + int unsigned memDataWidth; + // Enable support for the write-through policy + bit wtEn; + // Enable support for the write-back policy + bit wbEn; + } hpdcache_user_cfg_t; + + typedef struct packed { + // User configuration parameters + hpdcache_user_cfg_t u; + + // Internal parameters + int unsigned clWidth; + int unsigned clWordIdxWidth; + int unsigned clOffsetWidth; + int unsigned wordByteIdxWidth; + int unsigned wayIndexWidth; + int unsigned setWidth; + int unsigned nlineWidth; + int unsigned tagWidth; + int unsigned reqWordIdxWidth; + int unsigned reqOffsetWidth; + int unsigned reqDataWidth; + int unsigned reqDataBytes; + int unsigned mshrSetWidth; + int unsigned mshrWayWidth; + int unsigned wbufDataWidth; + int unsigned wbufDirPtrWidth; + int unsigned wbufDataPtrWidth; + int unsigned accessWidth; + } hpdcache_cfg_t; + + function automatic hpdcache_cfg_t hpdcacheBuildConfig(input hpdcache_user_cfg_t p); + hpdcache_cfg_t ret; + + ret.u = p; + + ret.clWidth = p.clWords * p.wordWidth; + ret.clOffsetWidth = $clog2(ret.clWidth / 8); + ret.clWordIdxWidth = $clog2(p.clWords); + ret.wordByteIdxWidth = $clog2(p.wordWidth / 8); + ret.wayIndexWidth = (p.ways > 1) ? $clog2(p.ways) : 1; + ret.setWidth = $clog2(p.sets); + ret.nlineWidth = p.paWidth - ret.clOffsetWidth; + ret.tagWidth = ret.nlineWidth - ret.setWidth; + ret.reqWordIdxWidth = $clog2(p.reqWords); + ret.reqOffsetWidth = p.paWidth - ret.tagWidth; + ret.reqDataWidth = p.reqWords * p.wordWidth; + ret.reqDataBytes = ret.reqDataWidth/8; + + ret.mshrSetWidth = (p.mshrSets > 1) ? $clog2(p.mshrSets) : 1; + ret.mshrWayWidth = (p.mshrWays > 1) ? $clog2(p.mshrWays) : 1; + + ret.wbufDataWidth = ret.reqDataWidth*p.wbufWords; + ret.wbufDirPtrWidth = $clog2(p.wbufDirEntries); + ret.wbufDataPtrWidth = $clog2(p.wbufDataEntries); + + ret.accessWidth = p.accessWords * p.wordWidth; + + return ret; + endfunction + // }}} +endpackage diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv new file mode 100644 index 0000000000..c5e2008e8b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv @@ -0,0 +1,689 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : September, 2021 + * Description : HPDcache Replay Table + * History : + */ +module hpdcache_rtab +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_way_t = logic, + + parameter type hpdcache_req_addr_t = logic, + + parameter type rtab_ptr_t = logic, + parameter type rtab_entry_t = logic +) +// }}} + +// Ports +// {{{ +( + // Clock and reset signals + input logic clk_i, + input logic rst_ni, + + // Global control signals + output logic empty_o, // RTAB is empty + output logic full_o, // RTAB is full + output logic fence_o, // There is a pending instruction with fence in the RTAB + + // Check RTAB signals + // This interface allows to check if there is an address-overlapping + // request in the RTAB with respect to the given nline. + input logic check_i, // Check for hit (nline) in the RTAB + input hpdcache_nline_t check_nline_i, + output logic check_hit_o, + + // Allocate signals + // This interface allows to allocate a new request in a new linked list + input logic alloc_i, + input logic alloc_and_link_i, + input rtab_entry_t alloc_req_i, + input hpdcache_rtab_deps_t alloc_deps_i, + + // Pop signals + // This interface allows to read (and remove) a request from the RTAB + output logic pop_try_valid_o, // Request ready to be replayed + input logic pop_try_i, + output rtab_entry_t pop_try_req_o, + output rtab_ptr_t pop_try_ptr_o, + output logic pop_try_error_o, + + // Pop Commit signals + // This interface allows to actually remove a popped request + input logic pop_commit_i, + input rtab_ptr_t pop_commit_ptr_i, + + // Pop Rollback signals + // This interface allows to put back a popped request + input logic pop_rback_i, + input rtab_ptr_t pop_rback_ptr_i, + + // Control signals from/to WBUF + output hpdcache_req_addr_t wbuf_addr_o, // address to check against ongoing writes + output logic wbuf_is_read_o, // monitored request is read + input logic wbuf_hit_open_i, // Hit on open entry in the write buf + input logic wbuf_hit_pend_i, // Hit on pend entry in the write buf + input logic wbuf_hit_sent_i, // Hit on sent entry in the write buf + input logic wbuf_not_ready_i, // Write buffer cannot accept the write + + // Control signals from the Miss Handler + input logic miss_ready_i, // Miss Handler is ready + + // Control signals from the Refill Handler + input logic refill_i, // Active refill + input logic refill_is_error_i, // Active refill has error bit set + input hpdcache_nline_t refill_nline_i, // Cache-line index being refilled + input hpdcache_way_t refill_way_index_i, // Way index being refilled + + // Control signals from the Flush Controller + input logic flush_ack_i, // Flush acknowledged + input hpdcache_nline_t flush_ack_nline_i, // Cache-line flush being acknowledged + input logic flush_ready_i, // Flush controller is available + + // Configuration parameters + input logic cfg_single_entry_i // Enable only one entry of the table +); +// }}} + +// Definition of constants, types and functions +// {{{ + localparam int N = HPDcacheCfg.u.rtabEntries; + + function automatic rtab_ptr_t rtab_bv_to_index( + input logic [N-1:0] bv); + for (int i = 0; i < N; i++) begin + if (bv[i]) return rtab_ptr_t'(i); + end + return 0; + endfunction + + function automatic logic [N-1:0] rtab_index_to_bv( + input rtab_ptr_t index); + logic [N-1:0] bv; + + for (int i = 0; i < N; i++) begin + bv[i] = (rtab_ptr_t'(i) == index); + end + return bv; + endfunction + + function automatic bit rtab_mshr_set_equal( + input hpdcache_nline_t x, + input hpdcache_nline_t y); + if (HPDcacheCfg.u.mshrSets > 1) begin + return (x[0 +: HPDcacheCfg.mshrSetWidth] == y[0 +: HPDcacheCfg.mshrSetWidth]); + end else begin + return 1'b1; + end + endfunction + + function automatic logic [N-1:0] rtab_next(rtab_ptr_t [N-1:0] next, rtab_ptr_t x); + return rtab_index_to_bv(next[x]); + endfunction + + typedef enum { + POP_TRY_HEAD, + POP_TRY_NEXT, + POP_TRY_NEXT_WAIT + } rtab_pop_try_state_e; +// }}} + +// Internal signals and registers +// {{{ + rtab_entry_t [N-1:0] req_q; + rtab_ptr_t [N-1:0] next_q; + + rtab_pop_try_state_e pop_try_state_q, pop_try_state_d; + logic [N-1:0] pop_try_next_q, pop_try_next_d; + + logic [N-1:0] valid_q; + logic [N-1:0] valid_set, valid_rst; + logic [N-1:0] alloc_valid_set; + logic [N-1:0] pop_commit_valid_rst; + logic [N-1:0] pop_rback_bv; + + // Bits indicating if the corresponding entry is an error response + logic [N-1:0] error_q; + logic [N-1:0] error_set, error_rst; + logic refill_is_error; + + // Bits indicating if the corresponding entry is the head of a linked list + logic [N-1:0] head_q; + logic [N-1:0] head_set, head_rst; + logic [N-1:0] alloc_head_set, alloc_head_rst; + logic [N-1:0] pop_try_head_rst; + logic [N-1:0] pop_commit_head_set; + logic [N-1:0] pop_rback_head_set; + + // Bits indicating if the corresponding entry is the tail of a linked list + logic [N-1:0] tail_q; + logic [N-1:0] tail_set, tail_rst; + logic [N-1:0] alloc_tail_set, alloc_tail_rst; + + // Bits indicating the pending dependencies of request + hpdcache_rtab_deps_t[N-1:0] deps_q; + hpdcache_rtab_deps_t[N-1:0] deps_set, deps_rst; + hpdcache_rtab_deps_t[N-1:0] alloc_deps_set; + hpdcache_rtab_deps_t[N-1:0] pop_rback_deps_set; + + logic [N-1:0] nodeps; + hpdcache_nline_t [N-1:0] nline; + hpdcache_req_addr_t [N-1:0] addr; + logic [N-1:0] is_read_bv; + logic [N-1:0] is_amo_bv; + logic [N-1:0] fence_bv; + logic [N-1:0] check_hit; + logic [N-1:0] match_check_nline; + logic [N-1:0] match_check_tail; + logic [N-1:0] match_refill_mshr_set; + logic [N-1:0] match_refill_nline; + logic [N-1:0] match_refill_set; + logic [N-1:0] match_refill_way; + logic [N-1:0] match_flush_nline; + + logic [N-1:0] free; + logic [N-1:0] free_alloc; + logic alloc; + + logic [N-1:0] pop_rback_ptr_bv; + logic [N-1:0] pop_try_bv; + logic [N-1:0] ready; + + genvar gen_i; +// }}} + +// Compute global control signals +// {{{ + // compute if entries are ready to be replayed + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_nodeps + assign nodeps[gen_i] = ~(|deps_q[gen_i]); + end + + assign ready = valid_q & head_q & nodeps; + assign free = ~valid_q; + + // compute the free vector (one-hot signal) + hpdcache_prio_1hot_encoder #( + .N (N) + ) free_encoder_i ( + .val_i (free), + .val_o (free_alloc) + ); + + // full and empty signals + assign empty_o = &(~valid_q); + assign full_o = &( valid_q) | (|valid_q & cfg_single_entry_i); + assign fence_o = |fence_bv; +// }}} + +// Check interface +// {{{ + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_check + assign addr[gen_i] = {req_q[gen_i].req.addr_tag, req_q[gen_i].req.addr_offset}; + assign nline[gen_i] = addr[gen_i][HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.nlineWidth]; + assign match_check_nline[gen_i] = (check_nline_i == nline[gen_i]); + assign is_read_bv[gen_i] = is_load(req_q[gen_i].req.op) | + is_cmo_prefetch(req_q[gen_i].req.op); + assign is_amo_bv[gen_i] = is_amo(req_q[gen_i].req.op); + end + + assign fence_bv = valid_q & is_amo_bv; + assign check_hit = valid_q & match_check_nline; + assign check_hit_o = |check_hit; + assign match_check_tail = check_hit & tail_q; +// }}} + +// Allocation process +// {{{ + assign alloc = alloc_i | alloc_and_link_i; + + // Set the valid bit-vector of the replay table + assign alloc_valid_set = free_alloc & {N{alloc}}; + + // Set of head and tail bit-vectors during an allocation + // - The head bit is only set when creating a new linked-list + // - The tail bit is always set because new requests are added on the tail. + assign alloc_head_set = free_alloc & {N{alloc_i}}; + assign alloc_tail_set = alloc_valid_set; + + // Reset of head and tail bit-vectors during an allocation + // - When doing an allocation and link, head bit shall be reset + // - when doing an allocation and link, the "prev" tail shall be reset + assign alloc_head_rst = free_alloc & {N{alloc_and_link_i}}; + assign alloc_tail_rst = match_check_tail & {N{alloc_and_link_i}}; + + // Set the dependency bits for the allocated entry + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_deps_set + assign alloc_deps_set[gen_i] = alloc_valid_set[gen_i] ? alloc_deps_i : '0; + end +// }}} + +// Update replay table dependencies +// {{{ + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_match_refill + assign match_refill_mshr_set[gen_i] = rtab_mshr_set_equal(refill_nline_i, nline[gen_i]); + assign match_refill_nline[gen_i] = (refill_nline_i == nline[gen_i]); + assign match_refill_set[gen_i] = (refill_nline_i[0 +: HPDcacheCfg.setWidth] == + nline[gen_i][0 +: HPDcacheCfg.setWidth]); + assign match_refill_way[gen_i] = (refill_way_index_i == req_q[gen_i].way_fetch); + end + + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_match_flush + assign match_flush_nline[gen_i] = (flush_ack_nline_i == nline[gen_i]); + end + + // Update write buffer hit dependencies + // {{{ + // Build a bit-vector with HEAD requests waiting for a conflict in the wbuf + logic [N-1:0] wbuf_rd_pending, wbuf_wr_pending; + logic [N-1:0] wbuf_rd_gnt, wbuf_wr_gnt; + logic [ 1:0] wbuf_pending; + logic [ 1:0] wbuf_gnt; + logic wbuf_ready; + logic [N-1:0] wbuf_sel; + + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_wbuf_pending + assign wbuf_rd_pending[gen_i] = valid_q[gen_i] & head_q[gen_i] & + deps_q[gen_i].wbuf_hit; + assign wbuf_wr_pending[gen_i] = valid_q[gen_i] & head_q[gen_i] & + deps_q[gen_i].wbuf_not_ready; + end + + // Choose in a round-robin manner a ready transaction waiting for a conflict in the wbuf + hpdcache_rrarb #( + .N (N) + ) wbuf_rd_pending_arb_i ( + .clk_i, + .rst_ni, + .req_i (wbuf_rd_pending), + .gnt_o (wbuf_rd_gnt), + .ready_i (wbuf_gnt[0] & wbuf_ready) + ); + + hpdcache_rrarb #( + .N (N) + ) wbuf_wr_pending_arb_i ( + .clk_i, + .rst_ni, + .req_i (wbuf_wr_pending), + .gnt_o (wbuf_wr_gnt), + .ready_i (wbuf_gnt[1] & wbuf_ready) + ); + + assign wbuf_pending = {|wbuf_wr_gnt, |wbuf_rd_gnt}, + wbuf_ready = |(pop_try_bv & (wbuf_rd_gnt | wbuf_wr_gnt)); + + hpdcache_fxarb #( + .N (2) + ) wbuf_pending_arb_i ( + .clk_i, + .rst_ni, + .req_i (wbuf_pending), + .gnt_o (wbuf_gnt), + .ready_i (wbuf_ready) + ); + + assign wbuf_sel = wbuf_gnt[0] ? wbuf_rd_gnt : + wbuf_gnt[1] ? wbuf_wr_gnt : '0; + + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH ($bits(hpdcache_req_addr_t)), + .ONE_HOT_SEL (1'b1) + ) wbuf_pending_addr_mux_i ( + .data_i (addr), + .sel_i (wbuf_sel), + .data_o (wbuf_addr_o) + ); + + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH (1), + .ONE_HOT_SEL (1'b1) + ) wbuf_pending_is_read_mux_i ( + .data_i (is_read_bv), + .sel_i (wbuf_sel), + .data_o (wbuf_is_read_o) + ); + // }}} + + always_comb + begin : deps_rst_comb + deps_rst = '0; + + for (int i = 0; i < N; i++) begin + + // reset write buffer dependency bits with the output from the write buffer + // {{{ + if (wbuf_sel[i]) begin + deps_rst[i].wbuf_hit = ~(wbuf_hit_open_i | wbuf_hit_pend_i | wbuf_hit_sent_i); + deps_rst[i].wbuf_not_ready = ~wbuf_not_ready_i; + end + // }}} + + // Update miss handler dependency + // {{{ + deps_rst[i].mshr_ready = miss_ready_i; + // }}} + + // Update refill dependencies + // {{{ + if (refill_i) begin + deps_rst[i].mshr_full = match_refill_mshr_set[i]; + deps_rst[i].mshr_hit = match_refill_nline[i]; + deps_rst[i].write_miss = match_refill_nline[i]; + deps_rst[i].dir_unavailable = match_refill_set[i]; + deps_rst[i].dir_fetch = match_refill_set[i] & match_refill_way[i]; + end + // }}} + + // Update flush dependencies + // {{{ + deps_rst[i].flush_hit = flush_ack_i & match_flush_nline[i]; + deps_rst[i].flush_not_ready = flush_ready_i; + // }}} + end + end +// }}} + +// Pop interface +// {{{ + logic [N-1:0] pop_sel; + + // Pop try process + // {{{ + logic [N-1:0] pop_gnt; + logic pop_head; + + hpdcache_rrarb #( + .N (N) + ) pop_arb_i ( + .clk_i, + .rst_ni, + .req_i (ready), + .gnt_o (pop_gnt), + .ready_i (pop_head) + ); + + always_comb + begin : req_valid_comb + case(pop_try_state_q) + POP_TRY_HEAD : pop_try_valid_o = |ready; + POP_TRY_NEXT : pop_try_valid_o = 1'b1; + POP_TRY_NEXT_WAIT: pop_try_valid_o = 1'b1; + default : pop_try_valid_o = 1'b0; + endcase + end + + always_comb + begin : pop_entry_sel_comb + pop_try_state_d = pop_try_state_q; + pop_try_next_d = pop_try_next_q; + pop_head = 1'b0; + pop_sel = '0; + + case (pop_try_state_q) + POP_TRY_HEAD: begin + // This FSM may be in this state after forwarding the tail of + // a list. In that case, a rollback may arrive in this cycle. + pop_sel = pop_gnt; + if (!pop_rback_i && pop_try_valid_o) begin + if (pop_try_i) begin + // If the request interface accepts the request, go to the next request + // in the list (if the current request is not the tail). Otherwise, stay in + // the same state to to forward a request from a new list + pop_head = 1'b1; + if ((pop_gnt & ~tail_q) != 0) begin + pop_try_state_d = POP_TRY_NEXT; + pop_try_next_d = rtab_next(next_q, pop_try_ptr_o); + end + end + end + end + POP_TRY_NEXT: begin + pop_sel = pop_try_next_q; + if (pop_rback_i) begin + pop_try_state_d = POP_TRY_HEAD; + end else begin + if (pop_try_i) begin + // If the request interface accepts the new request, go to the next request + // in the list (if the current request is not the tail). Otherwise, return + // to the POP_TRY_HEAD state to forward a request from a new list + if ((pop_try_next_q & ~tail_q) != 0) begin + pop_try_state_d = POP_TRY_NEXT; + pop_try_next_d = rtab_next(next_q, pop_try_ptr_o); + end else begin + pop_try_state_d = POP_TRY_HEAD; + end + end else begin + // If the request interface is not ready to consume the new request, wait + // until it is + pop_try_state_d = POP_TRY_NEXT_WAIT; + end + end + end + POP_TRY_NEXT_WAIT: begin + // Wait for the current request to be accepted. Then go to the next request in the + // list or to a new list + pop_sel = pop_try_next_q; + if (pop_try_i) begin + if ((pop_try_next_q & ~tail_q) != 0) begin + pop_try_state_d = POP_TRY_NEXT; + pop_try_next_d = rtab_next(next_q, pop_try_ptr_o); + end else begin + pop_try_state_d = POP_TRY_HEAD; + end + end + end + default: begin + end + endcase + end + + assign pop_commit_head_set = '0; + + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH ($bits(rtab_entry_t)), + .ONE_HOT_SEL (1'b1) + ) pop_mux_i ( + .data_i (req_q), + .sel_i (pop_sel), + .data_o (pop_try_req_o) + ); + + // Temporarily unset the head bit of the popped request to prevent it to be rescheduled + assign pop_try_bv = pop_sel & {N{pop_try_i}}; + assign pop_try_head_rst = pop_try_bv; + + + // Forward the index of the entry being popped. This is used later by the + // commit or rollback operations + assign pop_try_ptr_o = rtab_bv_to_index(pop_sel); + + // Forward the error bit + assign pop_try_error_o = |(pop_sel & error_q); + // }}} + + // Pop commit process + // {{{ + // Invalidate the entry being popped (head of the linked list) + assign pop_commit_valid_rst = {N{pop_commit_i}} & rtab_index_to_bv(pop_commit_ptr_i); + // }}} + + // Pop rollback process + // {{{ + // Set again the head bit of the rolled-back request + assign pop_rback_ptr_bv = rtab_index_to_bv(pop_rback_ptr_i); + assign pop_rback_bv = {N{pop_rback_i}} & pop_rback_ptr_bv; + assign pop_rback_head_set = pop_rback_bv; + + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_pop_rback_set + assign pop_rback_deps_set[gen_i] = pop_rback_bv[gen_i] ? alloc_deps_i : '0; + end + // }}} +// }}} + +// Internal state assignment +// {{{ + assign head_set = alloc_head_set | pop_commit_head_set | pop_rback_head_set; + assign head_rst = alloc_head_rst | pop_try_head_rst; + + assign tail_set = alloc_tail_set; + assign tail_rst = alloc_tail_rst; + + assign valid_set = alloc_valid_set; + assign valid_rst = pop_commit_valid_rst; + + assign refill_is_error = refill_i & refill_is_error_i; + + // Set the error flag + // - If the pending request is a write miss and the corresponding refill response is an error, + // then set the error bit of the pending request to abort it when replayed + for (gen_i = 0; gen_i < N; gen_i++) begin : gen_error_set + assign error_set[gen_i] = valid_q[gen_i] & + deps_q[gen_i].write_miss & + match_refill_nline[gen_i] & + refill_is_error; + end + assign error_rst = pop_commit_valid_rst; + + assign deps_set = alloc_deps_set | pop_rback_deps_set; + + always_ff @(posedge clk_i or negedge rst_ni) + begin : rtab_valid_ff + if (!rst_ni) begin + valid_q <= '0; + error_q <= '0; + head_q <= '0; + tail_q <= '0; + deps_q <= '0; + next_q <= '0; + end else begin + valid_q <= (~valid_q & valid_set) | (valid_q & ~valid_rst); + + // error flags + error_q <= (~error_q & error_set) | (error_q & ~error_rst); + + // update head and tail flags + head_q <= (~head_q & head_set) | (head_q & ~head_rst); + tail_q <= (~tail_q & tail_set) | (tail_q & ~tail_rst); + + // update dependency flags + deps_q <= (~deps_q & deps_set) | + ( deps_q & ~deps_rst); + + // update the next pointers + for (int i = 0; i < N; i++) begin + if (alloc_and_link_i && match_check_tail[i]) begin + next_q[i] <= rtab_bv_to_index(free_alloc); + end + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin : pop_try_ff + if (!rst_ni) begin + pop_try_state_q <= POP_TRY_HEAD; + pop_try_next_q <= '0; + end else begin + pop_try_state_q <= pop_try_state_d; + pop_try_next_q <= pop_try_next_d; + end + end + + always_ff @(posedge clk_i) + begin : rtab_ff + for (int i = 0; i < N; i++) begin + // Update the request array + // A RTAB request is stored at allocation time, but can be modified during + // a roll-back. Some fields such as the way_fetch are part of the RTAB request, and + // may need to be modified when rolling it back + if (valid_set[i] | pop_rback_bv[i]) begin + req_q[i] <= alloc_req_i; + end + end + end +// }}} + +// Assertions +// {{{ +`ifndef HPDCACHE_ASSERT_OFF + assert property (@(posedge clk_i) disable iff (!rst_ni) + check_i |-> $onehot0(match_check_tail)) else + $error("rtab: more than one entry matching"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + alloc_and_link_i |-> (check_i & check_hit_o)) else + $error("rtab: alloc and link shall be performed in case of check hit"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + alloc_and_link_i |-> + ({alloc_req_i.req.addr_tag, + alloc_req_i.req.addr_offset[HPDcacheCfg.clOffsetWidth +: + HPDcacheCfg.setWidth]} == check_nline_i)) else + $error("rtab: nline for alloc and link shall match the one being checked"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + alloc_i |-> !alloc_and_link_i) else + $error("rtab: only one allocation per cycle is allowed"); + +`ifndef VERILATOR + assert property (@(posedge clk_i) disable iff (!rst_ni) + pop_try_i |-> ##1 (pop_commit_i | pop_rback_i)) else + $error("rtab: a pop try shall be followed by a commit or rollback"); +`endif + + assert property (@(posedge clk_i) disable iff (!rst_ni) + pop_commit_i |-> valid_q[pop_commit_ptr_i]) else + $error("rtab: commiting an invalid entry"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + pop_rback_i |-> valid_q[pop_rback_ptr_i]) else + $error("rtab: rolling-back an invalid entry"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + pop_rback_i |-> !pop_try_i) else + $error("rtab: cache shall not accept a new request while rolling back"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + pop_rback_i |-> ~alloc) else + $error("rtab: trying to allocate a new request while rolling back"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + alloc |-> ~full_o) else + $error("rtab: trying to allocate while the table is full"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + alloc_and_link_i |-> ~cfg_single_entry_i) else + $error("rtab: trying to link a request in single entry mode"); +`endif +// }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv new file mode 100644 index 0000000000..55f9f35b86 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv @@ -0,0 +1,992 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : May, 2021 + * Description : HPDcache uncached and AMO request handler + * History : + */ +module hpdcache_uncached +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_offset_t = logic, + parameter type hpdcache_word_t = logic, + + parameter type hpdcache_req_addr_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + + parameter type hpdcache_way_vector_t = logic, + + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic +) + // }}} + + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + + // Global control signals + // {{{ + input logic wbuf_empty_i, + input logic mshr_empty_i, + input logic rtab_empty_i, + input logic ctrl_empty_i, + input logic flush_empty_i, + // }}} + + // Cache-side request interface + // {{{ + input logic req_valid_i, + output logic req_ready_o, + input hpdcache_uc_op_t req_op_i, + input hpdcache_req_addr_t req_addr_i, + input hpdcache_req_size_t req_size_i, + input hpdcache_req_data_t req_data_i, + input hpdcache_req_be_t req_be_i, + input logic req_uc_i, + input hpdcache_req_sid_t req_sid_i, + input hpdcache_req_tid_t req_tid_i, + input logic req_need_rsp_i, + // }}} + + // Write buffer interface + // {{{ + output logic wbuf_flush_all_o, + // }}} + + // AMO Cache Interface + // {{{ + output logic dir_amo_match_o, + output hpdcache_set_t dir_amo_match_set_o, + output hpdcache_tag_t dir_amo_match_tag_o, + output logic dir_amo_updt_sel_victim_o, + input hpdcache_way_vector_t dir_amo_hit_way_i, + + output logic data_amo_write_o, + output logic data_amo_write_enable_o, + output hpdcache_set_t data_amo_write_set_o, + output hpdcache_req_size_t data_amo_write_size_o, + output hpdcache_word_t data_amo_write_word_o, + output hpdcache_req_data_t data_amo_write_data_o, + output hpdcache_req_be_t data_amo_write_be_o, + // }}} + + // LR/SC reservation buffer + // {{{ + input logic lrsc_snoop_i, + input hpdcache_req_addr_t lrsc_snoop_addr_i, + input hpdcache_req_size_t lrsc_snoop_size_i, + // }}} + + // Core response interface + // {{{ + input logic core_rsp_ready_i, + output logic core_rsp_valid_o, + output hpdcache_rsp_t core_rsp_o, + // }}} + + // MEMORY interfaces + // {{{ + // Memory request unique identifier + input hpdcache_mem_id_t mem_read_id_i, + input hpdcache_mem_id_t mem_write_id_i, + + // Read interface + input logic mem_req_read_ready_i, + output logic mem_req_read_valid_o, + output hpdcache_mem_req_t mem_req_read_o, + + output logic mem_resp_read_ready_o, + input logic mem_resp_read_valid_i, + input hpdcache_mem_resp_r_t mem_resp_read_i, + + // Write interface + input logic mem_req_write_ready_i, + output logic mem_req_write_valid_o, + output hpdcache_mem_req_t mem_req_write_o, + + input logic mem_req_write_data_ready_i, + output logic mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t mem_req_write_data_o, + + output logic mem_resp_write_ready_o, + input logic mem_resp_write_valid_i, + input hpdcache_mem_resp_w_t mem_resp_write_i, + // }}} + + // Configuration interface + // {{{ + input logic cfg_error_on_cacheable_amo_i + // }}} +); + // }}} + +// Definition of constants and types +// {{{ + localparam hpdcache_uint MEM_REQ_RATIO = HPDcacheCfg.u.memDataWidth/HPDcacheCfg.reqDataWidth; + localparam hpdcache_uint MEM_REQ_WORD_INDEX_WIDTH = $clog2(MEM_REQ_RATIO); + + typedef enum { + UC_IDLE, + UC_WAIT_PENDING, + UC_MEM_REQ, + UC_MEM_W_REQ, + UC_MEM_WDATA_REQ, + UC_MEM_WAIT_RSP, + UC_CORE_RSP, + UC_AMO_READ_DIR, + UC_AMO_WRITE_DATA + } hpdcache_uc_fsm_t; + + localparam logic AMO_SC_SUCCESS = 1'b0; + localparam logic AMO_SC_FAILURE = 1'b1; + + function automatic logic [63:0] prepare_amo_data_operand( + input logic [63:0] data_i, + input hpdcache_req_size_t size_i, + input hpdcache_req_addr_t addr_i, + input logic sign_extend_i + ); + // 64-bits AMOs are already aligned, thus do nothing + if (size_i == hpdcache_req_size_t'(3)) begin + return data_i; + end + + // 32-bits AMOs + else begin + if (addr_i[2] == 1'b1) begin + if (sign_extend_i) begin + return {{32{data_i[63]}}, data_i[63:32]}; + end else begin + return {{32{ 1'b0}}, data_i[63:32]}; + end + end else begin + if (sign_extend_i) begin + return {{32{data_i[31]}}, data_i[31: 0]}; + end else begin + return {{32{ 1'b0}}, data_i[31: 0]}; + end + end + end + endfunction; + + function automatic logic [63:0] prepare_amo_data_result( + input logic [63:0] data_i, + input hpdcache_req_size_t size_i + ); + // 64-bits AMOs are already aligned, thus do nothing + if (size_i == hpdcache_req_size_t'(3)) begin + return data_i; + end + + // 32-bits AMOs + else begin + return {2{data_i[31:0]}}; + end + endfunction; + + function automatic logic amo_need_sign_extend(hpdcache_uc_op_t op); + unique case (1'b1) + op.is_amo_add, + op.is_amo_max, + op.is_amo_min: return 1'b1; + default : return 1'b0; + endcase; + endfunction +// }}} + +// Internal signals and registers +// {{{ + hpdcache_uc_fsm_t uc_fsm_q, uc_fsm_d; + hpdcache_uc_op_t req_op_q; + hpdcache_req_addr_t req_addr_q; + hpdcache_req_size_t req_size_q; + hpdcache_req_data_t req_data_q; + hpdcache_req_be_t req_be_q; + logic req_uc_q; + hpdcache_req_sid_t req_sid_q; + hpdcache_req_tid_t req_tid_q; + logic req_need_rsp_q; + logic no_pend_trans; + + logic uc_sc_retcode_q, uc_sc_retcode_d; + + hpdcache_req_data_t rsp_rdata_q, rsp_rdata_d; + logic rsp_error_set, rsp_error_rst; + logic rsp_error_q; + logic mem_resp_write_valid_q, mem_resp_write_valid_d; + logic mem_resp_read_valid_q, mem_resp_read_valid_d; + + hpdcache_req_data_t mem_req_write_data; + logic [63:0] amo_req_ld_data; + logic [63:0] amo_ld_data; + logic [63:0] amo_req_st_data; + logic [63:0] amo_st_data; + logic [63:0] amo_result; + logic [63:0] amo_write_data; +// }}} + +// LR/SC reservation buffer logic +// {{{ + logic lrsc_rsrv_valid_q; + hpdcache_req_addr_t lrsc_rsrv_addr_q, lrsc_rsrv_addr_d; + hpdcache_nline_t lrsc_rsrv_nline; + hpdcache_offset_t lrsc_rsrv_word; + + hpdcache_offset_t lrsc_snoop_words; + hpdcache_nline_t lrsc_snoop_nline; + hpdcache_offset_t lrsc_snoop_base, lrsc_snoop_end; + logic lrsc_snoop_hit; + logic lrsc_snoop_reset; + + hpdcache_nline_t lrsc_uc_nline; + hpdcache_offset_t lrsc_uc_word; + logic lrsc_uc_hit; + logic lrsc_uc_set, lrsc_uc_reset; + + // NOTE: Reservation set for LR instruction is always 8-bytes in this + // implementation. + assign lrsc_rsrv_nline = lrsc_rsrv_addr_q[HPDcacheCfg.clOffsetWidth +: + HPDcacheCfg.nlineWidth]; + assign lrsc_rsrv_word = lrsc_rsrv_addr_q[0 +: HPDcacheCfg.clOffsetWidth] >> 3; + + // Check hit on LR/SC reservation for snoop port (normal write accesses) + assign lrsc_snoop_words = (lrsc_snoop_size_i < 3) ? + 1 : hpdcache_offset_t'((8'h1 << lrsc_snoop_size_i) >> 3); + assign lrsc_snoop_nline = lrsc_snoop_addr_i[HPDcacheCfg.clOffsetWidth +: + HPDcacheCfg.nlineWidth]; + assign lrsc_snoop_base = lrsc_snoop_addr_i[0 +: HPDcacheCfg.clOffsetWidth] >> 3; + assign lrsc_snoop_end = lrsc_snoop_base + lrsc_snoop_words; + + assign lrsc_snoop_hit = lrsc_rsrv_valid_q & (lrsc_rsrv_nline == lrsc_snoop_nline) & + (lrsc_rsrv_word >= lrsc_snoop_base) & + (lrsc_rsrv_word < lrsc_snoop_end ); + + assign lrsc_snoop_reset = lrsc_snoop_i & lrsc_snoop_hit; + + // Check hit on LR/SC reservation for AMOs and SC + assign lrsc_uc_nline = req_addr_i[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.nlineWidth]; + assign lrsc_uc_word = req_addr_i[0 +: HPDcacheCfg.clOffsetWidth] >> 3; + + assign lrsc_uc_hit = lrsc_rsrv_valid_q & (lrsc_rsrv_nline == lrsc_uc_nline) & + (lrsc_rsrv_word == lrsc_uc_word); +// }}} + + assign no_pend_trans = wbuf_empty_i && + mshr_empty_i && + rtab_empty_i && + ctrl_empty_i && + flush_empty_i; + +// Uncacheable request FSM +// {{{ + always_comb + begin : uc_fsm_comb + mem_resp_write_valid_d = mem_resp_write_valid_q; + mem_resp_read_valid_d = mem_resp_read_valid_q; + rsp_error_set = 1'b0; + rsp_error_rst = 1'b0; + lrsc_rsrv_addr_d = lrsc_rsrv_addr_q; + uc_sc_retcode_d = uc_sc_retcode_q; + wbuf_flush_all_o = 1'b0; + lrsc_uc_set = 1'b0; + lrsc_uc_reset = 1'b0; + + uc_fsm_d = uc_fsm_q; + + unique case (uc_fsm_q) + // Wait for a request + // {{{ + UC_IDLE: begin + + if (req_valid_i) begin + wbuf_flush_all_o = 1'b1; + + unique case (1'b1) + req_op_i.is_ld, + req_op_i.is_st: begin + if (no_pend_trans) begin + uc_fsm_d = UC_MEM_REQ; + end else begin + uc_fsm_d = UC_WAIT_PENDING; + end + end + + req_op_i.is_amo_swap, + req_op_i.is_amo_add, + req_op_i.is_amo_and, + req_op_i.is_amo_or, + req_op_i.is_amo_xor, + req_op_i.is_amo_max, + req_op_i.is_amo_maxu, + req_op_i.is_amo_min, + req_op_i.is_amo_minu, + req_op_i.is_amo_lr: begin + // Reset LR/SC reservation if AMO matches its address + lrsc_uc_reset = ~req_op_i.is_amo_lr & lrsc_uc_hit; + + if (!req_uc_i && cfg_error_on_cacheable_amo_i) begin + rsp_error_set = 1'b1; + uc_fsm_d = UC_CORE_RSP; + end else begin + if (no_pend_trans) begin + uc_fsm_d = UC_MEM_REQ; + end else begin + uc_fsm_d = UC_WAIT_PENDING; + end + end + end + + req_op_i.is_amo_sc: begin + if (!req_uc_i && cfg_error_on_cacheable_amo_i) begin + rsp_error_set = 1'b1; + uc_fsm_d = UC_CORE_RSP; + end else begin + // Reset previous reservation (if any) + lrsc_uc_reset = 1'b1; + + // SC with valid reservation + if (lrsc_uc_hit) begin + if (no_pend_trans) begin + uc_fsm_d = UC_MEM_REQ; + end else begin + uc_fsm_d = UC_WAIT_PENDING; + end + end + // SC with no valid reservation, thus respond with the failure code + else begin + uc_sc_retcode_d = AMO_SC_FAILURE; + uc_fsm_d = UC_CORE_RSP; + end + end + end + + default: begin + if (req_need_rsp_i) begin + rsp_error_set = 1'b1; + uc_fsm_d = UC_CORE_RSP; + end + end + endcase + end + end + // }}} + + // Wait for all pending transactions to be completed + // {{{ + UC_WAIT_PENDING: begin + if (no_pend_trans) begin + uc_fsm_d = UC_MEM_REQ; + end else begin + uc_fsm_d = UC_WAIT_PENDING; + end + end + // }}} + + // Send request to memory + // {{{ + UC_MEM_REQ: begin + uc_fsm_d = UC_MEM_REQ; + + mem_resp_write_valid_d = 1'b0; + mem_resp_read_valid_d = 1'b0; + + unique case (1'b1) + req_op_q.is_ld, + req_op_q.is_amo_lr: begin + if (mem_req_read_ready_i) begin + uc_fsm_d = UC_MEM_WAIT_RSP; + end + end + + req_op_q.is_st, + req_op_q.is_amo_sc, + req_op_q.is_amo_swap, + req_op_q.is_amo_add, + req_op_q.is_amo_and, + req_op_q.is_amo_or, + req_op_q.is_amo_xor, + req_op_q.is_amo_max, + req_op_q.is_amo_maxu, + req_op_q.is_amo_min, + req_op_q.is_amo_minu: begin + if (mem_req_write_ready_i && mem_req_write_data_ready_i) begin + uc_fsm_d = UC_MEM_WAIT_RSP; + end else if (mem_req_write_ready_i) begin + uc_fsm_d = UC_MEM_WDATA_REQ; + end else if (mem_req_write_data_ready_i) begin + uc_fsm_d = UC_MEM_W_REQ; + end + end + endcase + end + // }}} + + // Send write address + // {{{ + UC_MEM_W_REQ: begin + mem_resp_write_valid_d = mem_resp_write_valid_q | mem_resp_write_valid_i; + mem_resp_read_valid_d = mem_resp_read_valid_q | mem_resp_read_valid_i; + + if (mem_req_write_ready_i) begin + uc_fsm_d = UC_MEM_WAIT_RSP; + end else begin + uc_fsm_d = UC_MEM_W_REQ; + end + end + // }}} + + // Send write data + // {{{ + UC_MEM_WDATA_REQ: begin + mem_resp_write_valid_d = mem_resp_write_valid_q | mem_resp_write_valid_i; + mem_resp_read_valid_d = mem_resp_read_valid_q | mem_resp_read_valid_i; + + if (mem_req_write_data_ready_i) begin + uc_fsm_d = UC_MEM_WAIT_RSP; + end else begin + uc_fsm_d = UC_MEM_WDATA_REQ; + end + end + // }}} + + // Wait for the response from the memory + // {{{ + UC_MEM_WAIT_RSP: begin + automatic bit rd_error; + automatic bit wr_error; + + uc_fsm_d = UC_MEM_WAIT_RSP; + mem_resp_write_valid_d = mem_resp_write_valid_q | mem_resp_write_valid_i; + mem_resp_read_valid_d = mem_resp_read_valid_q | mem_resp_read_valid_i; + + rd_error = mem_resp_read_valid_i && + ( mem_resp_read_i.mem_resp_r_error == HPDCACHE_MEM_RESP_NOK); + wr_error = mem_resp_write_valid_i && + (mem_resp_write_i.mem_resp_w_error == HPDCACHE_MEM_RESP_NOK); + rsp_error_set = req_need_rsp_q & (rd_error | wr_error); + + unique case (1'b1) + req_op_q.is_ld: begin + if (mem_resp_read_valid_i) begin + if (req_need_rsp_q) begin + uc_fsm_d = UC_CORE_RSP; + end else begin + uc_fsm_d = UC_IDLE; + end + end + end + req_op_q.is_st: begin + if (mem_resp_write_valid_i) begin + if (req_need_rsp_q) begin + uc_fsm_d = UC_CORE_RSP; + end else begin + uc_fsm_d = UC_IDLE; + end + end + end + req_op_q.is_amo_lr: begin + if (mem_resp_read_valid_i) begin + // set a new reservation + if (!rd_error) + begin + lrsc_uc_set = 1'b1; + lrsc_rsrv_addr_d = req_addr_q; + end + // in case of a memory error, do not make the reservation and + // invalidate an existing one (if valid) + else begin + lrsc_uc_reset = 1'b1; + end + + if (req_uc_q || rd_error) begin + uc_fsm_d = UC_CORE_RSP; + end else begin + uc_fsm_d = UC_AMO_READ_DIR; + end + end + end + req_op_q.is_amo_sc: begin + if (mem_resp_write_valid_i) begin + automatic bit is_atomic; + + is_atomic = mem_resp_write_i.mem_resp_w_is_atomic && !wr_error; + uc_sc_retcode_d = is_atomic ? AMO_SC_SUCCESS : AMO_SC_FAILURE; + + if (req_uc_q || !is_atomic) begin + uc_fsm_d = UC_CORE_RSP; + end else begin + uc_fsm_d = UC_AMO_READ_DIR; + end + end + end + req_op_q.is_amo_swap, + req_op_q.is_amo_add, + req_op_q.is_amo_and, + req_op_q.is_amo_or, + req_op_q.is_amo_xor, + req_op_q.is_amo_max, + req_op_q.is_amo_maxu, + req_op_q.is_amo_min, + req_op_q.is_amo_minu: begin + // wait for both old data and write acknowledged were received + if ((mem_resp_read_valid_i && mem_resp_write_valid_i) || + (mem_resp_read_valid_i && mem_resp_write_valid_q) || + (mem_resp_read_valid_q && mem_resp_write_valid_i)) + begin + if (req_uc_q || rsp_error_q || rd_error || wr_error) begin + uc_fsm_d = UC_CORE_RSP; + end else begin + uc_fsm_d = UC_AMO_READ_DIR; + end + end + end + endcase + end + // }}} + + // Send the response to the requester + // {{{ + UC_CORE_RSP: begin + if (core_rsp_ready_i) begin + rsp_error_rst = 1'b1; + uc_fsm_d = UC_IDLE; + end else begin + uc_fsm_d = UC_CORE_RSP; + end + end + // }}} + + // Check for a cache hit on the AMO target address + // {{{ + UC_AMO_READ_DIR: begin + uc_fsm_d = UC_AMO_WRITE_DATA; + end + // }}} + + // Write the locally computed AMO result in the cache + // {{{ + UC_AMO_WRITE_DATA: begin + uc_fsm_d = UC_CORE_RSP; + end + // }}} + endcase + end +// }}} + +// AMO unit +// {{{ + if (HPDcacheCfg.reqDataWidth > 64) begin : gen_amo_data_width_gt_64 + localparam hpdcache_uint AMO_WORD_INDEX_WIDTH = $clog2(HPDcacheCfg.reqDataWidth/64); + hpdcache_mux #( + .NINPUT (HPDcacheCfg.reqDataWidth/64), + .DATA_WIDTH (64), + .ONE_HOT_SEL (1'b0) + ) amo_ld_data_mux_i ( + .data_i (rsp_rdata_q), + .sel_i (req_addr_q[3 +: AMO_WORD_INDEX_WIDTH]), + .data_o (amo_req_ld_data) + ); + + hpdcache_mux #( + .NINPUT (HPDcacheCfg.reqDataWidth/64), + .DATA_WIDTH (64), + .ONE_HOT_SEL (1'b0) + ) amo_st_data_mux_i ( + .data_i (req_data_q), + .sel_i (req_addr_q[3 +: AMO_WORD_INDEX_WIDTH]), + .data_o (amo_req_st_data) + ); + end else if (HPDcacheCfg.reqDataWidth == 64) begin : gen_amo_data_width_eq_64 + assign amo_req_ld_data = rsp_rdata_q; + assign amo_req_st_data = req_data_q; + end else begin : gen_amo_data_width_eq_32 + assign amo_req_ld_data = req_addr_q[2] ? {rsp_rdata_q, 32'b0} : {32'b0, rsp_rdata_q}; + assign amo_req_st_data = req_addr_q[2] ? {req_data_q, 32'b0} : {32'b0, req_data_q}; + end + + assign amo_ld_data = prepare_amo_data_operand(amo_req_ld_data, req_size_q, + req_addr_q, amo_need_sign_extend(req_op_q)); + assign amo_st_data = prepare_amo_data_operand(amo_req_st_data, req_size_q, + req_addr_q, amo_need_sign_extend(req_op_q)); + + hpdcache_amo amo_unit_i ( + .ld_data_i (amo_ld_data), + .st_data_i (amo_st_data), + .op_i (req_op_q), + .result_o (amo_result) + ); + + assign dir_amo_match_o = (uc_fsm_q == UC_AMO_READ_DIR); + assign dir_amo_match_set_o = req_addr_q[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.setWidth]; + assign dir_amo_match_tag_o = req_addr_q[(HPDcacheCfg.clOffsetWidth + HPDcacheCfg.setWidth) +: + HPDcacheCfg.tagWidth]; + assign dir_amo_updt_sel_victim_o = (uc_fsm_q == UC_AMO_WRITE_DATA); + + assign data_amo_write_o = (uc_fsm_q == UC_AMO_WRITE_DATA); + assign data_amo_write_enable_o = |dir_amo_hit_way_i; + assign data_amo_write_set_o = req_addr_q[HPDcacheCfg.clOffsetWidth +: HPDcacheCfg.setWidth]; + assign data_amo_write_size_o = req_size_q; + assign data_amo_write_word_o = req_addr_q[HPDcacheCfg.wordByteIdxWidth +: + HPDcacheCfg.clWordIdxWidth]; + assign data_amo_write_be_o = req_be_q; + + assign amo_write_data = prepare_amo_data_result(amo_result, req_size_q); + if (HPDcacheCfg.reqDataWidth >= 64) begin : gen_amo_ram_write_data_ge_64 + assign data_amo_write_data_o = {HPDcacheCfg.reqDataWidth/64{amo_write_data}}; + end else begin : gen_amo_ram_write_data_lt_64 + assign data_amo_write_data_o = amo_write_data; + end +// }}} + +// Core response outputs +// {{{ + assign req_ready_o = (uc_fsm_q == UC_IDLE), + core_rsp_valid_o = (uc_fsm_q == UC_CORE_RSP); +// }}} + +// Memory read request outputs +// {{{ + always_comb + begin : mem_req_read_comb + mem_req_read_o.mem_req_addr = req_addr_q; + mem_req_read_o.mem_req_len = 0; + mem_req_read_o.mem_req_size = req_size_q; + mem_req_read_o.mem_req_id = mem_read_id_i; + mem_req_read_o.mem_req_cacheable = 1'b0; + mem_req_read_o.mem_req_command = HPDCACHE_MEM_READ; + mem_req_read_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_ADD; + + unique case (1'b1) + req_op_q.is_ld: begin + mem_req_read_valid_o = (uc_fsm_q == UC_MEM_REQ); + end + req_op_q.is_amo_lr: begin + mem_req_read_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_read_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_LDEX; + mem_req_read_valid_o = (uc_fsm_q == UC_MEM_REQ); + end + default: begin + mem_req_read_valid_o = 1'b0; + end + endcase + end +// }}} + +// Memory write request outputs +// {{{ + always_comb + begin : mem_req_write_comb + mem_req_write_data = req_data_q; + mem_req_write_o.mem_req_addr = req_addr_q; + mem_req_write_o.mem_req_len = 0; + mem_req_write_o.mem_req_size = req_size_q; + mem_req_write_o.mem_req_id = mem_write_id_i; + mem_req_write_o.mem_req_cacheable = 1'b0; + unique case (1'b1) + req_op_q.is_amo_sc: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_STEX; + end + req_op_q.is_amo_swap: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_SWAP; + end + req_op_q.is_amo_add: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_ADD; + end + req_op_q.is_amo_and: begin + mem_req_write_data = ~req_data_q; + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_CLR; + end + req_op_q.is_amo_or: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_SET; + end + req_op_q.is_amo_xor: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_EOR; + end + req_op_q.is_amo_max: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_SMAX; + end + req_op_q.is_amo_maxu: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_UMAX; + end + req_op_q.is_amo_min: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_SMIN; + end + req_op_q.is_amo_minu: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_ATOMIC; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_UMIN; + end + default: begin + mem_req_write_o.mem_req_command = HPDCACHE_MEM_WRITE; + mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_ADD; + end + endcase + + unique case (uc_fsm_q) + UC_MEM_REQ: begin + unique case (1'b1) + req_op_q.is_st, + req_op_q.is_amo_sc, + req_op_q.is_amo_swap, + req_op_q.is_amo_add, + req_op_q.is_amo_and, + req_op_q.is_amo_or, + req_op_q.is_amo_xor, + req_op_q.is_amo_max, + req_op_q.is_amo_maxu, + req_op_q.is_amo_min, + req_op_q.is_amo_minu: begin + mem_req_write_data_valid_o = 1'b1; + mem_req_write_valid_o = 1'b1; + end + + default: begin + mem_req_write_data_valid_o = 1'b0; + mem_req_write_valid_o = 1'b0; + end + endcase + end + + UC_MEM_W_REQ: begin + mem_req_write_valid_o = 1'b1; + mem_req_write_data_valid_o = 1'b0; + end + + UC_MEM_WDATA_REQ: begin + mem_req_write_valid_o = 1'b0; + mem_req_write_data_valid_o = 1'b1; + end + + default: begin + mem_req_write_valid_o = 1'b0; + mem_req_write_data_valid_o = 1'b0; + end + endcase + end + + // memory data width is bigger than the width of the core's interface + if (MEM_REQ_RATIO > 1) begin : gen_upsize_mem_req_data + // replicate data + assign mem_req_write_data_o.mem_req_w_data = {MEM_REQ_RATIO{mem_req_write_data}}; + + // demultiplex the byte-enable + hpdcache_demux #( + .NOUTPUT (MEM_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth/8) + ) mem_write_be_demux_i ( + .data_i (req_be_q), + .sel_i (req_addr_q[$clog2(HPDcacheCfg.reqDataWidth/8) +: + MEM_REQ_WORD_INDEX_WIDTH]), + .data_o (mem_req_write_data_o.mem_req_w_be) + ); + end + + // memory data width is equal to the width of the core's interface + else begin : gen_eqsize_mem_req_data + assign mem_req_write_data_o.mem_req_w_data = mem_req_write_data; + assign mem_req_write_data_o.mem_req_w_be = req_be_q; + end + + assign mem_req_write_data_o.mem_req_w_last = 1'b1; +// }}} + +// Response handling +// {{{ + logic [63:0] sc_retcode; + logic [63:0] sc_rdata_dword; + hpdcache_req_data_t sc_rdata; + + assign sc_retcode = {{63{1'b0}}, uc_sc_retcode_q}; + assign sc_rdata_dword = prepare_amo_data_result(sc_retcode, req_size_q); + if (HPDcacheCfg.reqDataWidth >= 64) begin : gen_sc_rdata_ge_64 + assign sc_rdata = {HPDcacheCfg.reqDataWidth/64{sc_rdata_dword}}; + end else begin : gen_sc_rdata_lt_64 + assign sc_rdata = sc_rdata_dword; + end + + assign core_rsp_o.rdata = req_op_q.is_amo_sc ? sc_rdata : rsp_rdata_q; + assign core_rsp_o.sid = req_sid_q; + assign core_rsp_o.tid = req_tid_q; + assign core_rsp_o.error = rsp_error_q; + assign core_rsp_o.aborted = 1'b0; + + // Resize the memory response data to the core response width + // memory data width is bigger than the width of the core's interface + if (MEM_REQ_RATIO > 1) begin : gen_downsize_core_rsp_data + hpdcache_mux #( + .NINPUT (MEM_REQ_RATIO), + .DATA_WIDTH (HPDcacheCfg.reqDataWidth) + ) data_read_rsp_mux_i( + .data_i (mem_resp_read_i.mem_resp_r_data), + .sel_i (req_addr_q[$clog2(HPDcacheCfg.reqDataWidth/8) +: + MEM_REQ_WORD_INDEX_WIDTH]), + .data_o (rsp_rdata_d) + ); + end + + // memory data width is equal to the width of the core's interface + else begin : gen_eqsize_core_rsp_data + assign rsp_rdata_d = mem_resp_read_i.mem_resp_r_data; + end + + // This FSM is always ready to accept the response + assign mem_resp_read_ready_o = 1'b1, + mem_resp_write_ready_o = 1'b1; +// }}} + +// Set cache request registers +// {{{ + always_ff @(posedge clk_i) + begin : req_ff + if (req_valid_i && req_ready_o) begin + req_op_q <= req_op_i; + req_addr_q <= req_addr_i; + req_size_q <= req_size_i; + req_data_q <= req_data_i; + req_be_q <= req_be_i; + req_uc_q <= req_uc_i; + req_sid_q <= req_sid_i; + req_tid_q <= req_tid_i; + req_need_rsp_q <= req_need_rsp_i; + end + end +// }}} + +// Uncacheable request FSM set state +// {{{ + logic lrsc_rsrv_valid_set, lrsc_rsrv_valid_reset; + + assign lrsc_rsrv_valid_set = lrsc_uc_set, + lrsc_rsrv_valid_reset = lrsc_uc_reset | lrsc_snoop_reset; + + always_ff @(posedge clk_i or negedge rst_ni) + begin : uc_fsm_ff + if (!rst_ni) begin + uc_fsm_q <= UC_IDLE; + lrsc_rsrv_valid_q <= 1'b0; + end else begin + uc_fsm_q <= uc_fsm_d; + lrsc_rsrv_valid_q <= (~lrsc_rsrv_valid_q & lrsc_rsrv_valid_set ) | + ( lrsc_rsrv_valid_q & ~lrsc_rsrv_valid_reset); + end + end + + always_ff @(posedge clk_i) + begin : uc_amo_ff + lrsc_rsrv_addr_q <= lrsc_rsrv_addr_d; + uc_sc_retcode_q <= uc_sc_retcode_d; + end +// }}} + +// Response registers +// {{{ + always_ff @(posedge clk_i) + begin + if (mem_resp_read_valid_i) begin + rsp_rdata_q <= rsp_rdata_d; + end + mem_resp_write_valid_q <= mem_resp_write_valid_d; + mem_resp_read_valid_q <= mem_resp_read_valid_d; + end + + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + rsp_error_q <= 1'b0; + end else begin + rsp_error_q <= (~rsp_error_q & rsp_error_set) | + ( rsp_error_q & ~rsp_error_rst); + end + end +// }}} + +// Assertions +// {{{ +`ifndef HPDCACHE_ASSERT_OFF + assert property (@(posedge clk_i) disable iff (!rst_ni) + (req_valid_i && req_op_i.is_ld) -> req_uc_i) else + $error("uc_handler: unexpected load request on cacheable region"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + (req_valid_i && req_op_i.is_st) -> req_uc_i) else + $error("uc_handler: unexpected store request on cacheable region"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + (req_valid_i && (req_op_i.is_amo_lr || + req_op_i.is_amo_sc || + req_op_i.is_amo_swap || + req_op_i.is_amo_add || + req_op_i.is_amo_and || + req_op_i.is_amo_or || + req_op_i.is_amo_xor || + req_op_i.is_amo_max || + req_op_i.is_amo_maxu || + req_op_i.is_amo_min || + req_op_i.is_amo_minu )) -> req_need_rsp_i) else + $error("uc_handler: amo requests shall need a response"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + (req_valid_i && (req_op_i.is_amo_lr || + req_op_i.is_amo_sc || + req_op_i.is_amo_swap || + req_op_i.is_amo_add || + req_op_i.is_amo_and || + req_op_i.is_amo_or || + req_op_i.is_amo_xor || + req_op_i.is_amo_max || + req_op_i.is_amo_maxu || + req_op_i.is_amo_min || + req_op_i.is_amo_minu )) -> (req_size_i inside {2,3})) else + $error("uc_handler: amo requests shall be 4 or 8 bytes wide"); + + assert property (@(posedge clk_i) disable iff (!rst_ni) + (mem_resp_write_valid_i || mem_resp_read_valid_i) -> (uc_fsm_q == UC_MEM_WAIT_RSP)) else + $error("uc_handler: unexpected response from memory"); +`endif +// }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv new file mode 100644 index 0000000000..1ab750642f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv @@ -0,0 +1,145 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : May, 2021 + * Description : HPDcache Pseudo-LRU replacement policy + * History : + */ +module hpdcache_victim_plru +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + localparam type set_t = logic [$clog2(HPDcacheCfg.u.sets)-1:0], + localparam type way_vector_t = logic [HPDcacheCfg.u.ways-1:0] +) + // }}} + + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + + // PLRU update interface + input logic updt_i, + input set_t updt_set_i, + input way_vector_t updt_way_i, + + // Victim selection interface + input logic sel_victim_i, /* unused */ + input way_vector_t sel_dir_valid_i, + input way_vector_t sel_dir_wback_i, + input way_vector_t sel_dir_dirty_i, + input way_vector_t sel_dir_fetch_i, + input set_t sel_victim_set_i, + output way_vector_t sel_victim_way_o +); + // }}} + + // Internal signals and registers + // {{{ + way_vector_t [HPDcacheCfg.u.sets-1:0] plru_q, plru_d; + + way_vector_t updt_plru; + logic unused_available, plru_available, clean_available, dirty_available; + way_vector_t unused_ways, plru_ways, clean_ways, dirty_ways; + way_vector_t unused_victim_way, plru_victim_way, clean_victim_way, dirty_victim_way; + // }}} + + // Victim way selection + // {{{ + assign unused_ways = ~sel_dir_fetch_i & ~sel_dir_valid_i; + assign plru_ways = ~sel_dir_fetch_i & sel_dir_valid_i & ~plru_q[sel_victim_set_i]; + assign clean_ways = ~sel_dir_fetch_i & sel_dir_valid_i & ~sel_dir_dirty_i; + assign dirty_ways = ~sel_dir_fetch_i & sel_dir_valid_i & sel_dir_dirty_i; + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + unused_victim_select_i( + .val_i (unused_ways), + .val_o (unused_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + plru_victim_select_i( + .val_i (plru_ways), + .val_o (plru_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + clean_victim_select_i( + .val_i (clean_ways), + .val_o (clean_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + dirty_victim_select_i( + .val_i (dirty_ways), + .val_o (dirty_victim_way) + ); + + assign unused_available = |unused_ways; + assign plru_available = |plru_ways; + assign clean_available = |clean_ways; + assign dirty_available = |dirty_ways; + + always_comb + begin : victim_way_selection_comb + priority case (1'b1) + unused_available: sel_victim_way_o = unused_victim_way; + plru_available: sel_victim_way_o = plru_victim_way; + clean_available: sel_victim_way_o = clean_victim_way; + dirty_available: sel_victim_way_o = dirty_victim_way; + default: sel_victim_way_o = '0; + endcase + end + // }}} + + // Pseudo-LRU update process + // {{{ + assign updt_plru = plru_q[updt_set_i] | updt_way_i; + + always_comb + begin : plru_update_comb + plru_d = plru_q; + + // When accessing a cache-line, set the corresponding PLRU bit + // If all PLRU bits of a given set are equal to 1, reset them all + // but the currently accessed way + if (updt_i) plru_d[updt_set_i] = &updt_plru ? updt_way_i : updt_plru; + end + // }}} + + // Set state process + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin : lru_ff + if (!rst_ni) begin + plru_q <= '0; + end else begin + if (updt_i) plru_q <= plru_d; + end + end + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv new file mode 100644 index 0000000000..efecab237b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv @@ -0,0 +1,125 @@ +/* + * Copyright 2023,2024 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : September, 2024 + * Description : HPDcache pseudo-random replacement policy + * History : + */ +module hpdcache_victim_random +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + localparam type set_t = logic [$clog2(HPDcacheCfg.u.sets)-1:0], + localparam type way_vector_t = logic [HPDcacheCfg.u.ways-1:0] +) + // }}} + + // Ports + // {{{ +( + input logic clk_i, + input logic rst_ni, + + // Update interface + input logic updt_i, /* unused */ + input set_t updt_set_i, /* unused */ + input way_vector_t updt_way_i, /* unused */ + + // Victim selection interface + input logic sel_victim_i, + input way_vector_t sel_dir_valid_i, + input way_vector_t sel_dir_wback_i, /* unused */ + input way_vector_t sel_dir_dirty_i, + input way_vector_t sel_dir_fetch_i, + input set_t sel_victim_set_i, /* unused */ + output way_vector_t sel_victim_way_o +); + // }}} + + // Internal signals and registers + // {{{ + logic unused_available, rand_available, clean_available, dirty_available; + way_vector_t unused_ways, rand_ways, clean_ways, dirty_ways; + way_vector_t unused_victim_way, rand_victim_way, clean_victim_way, dirty_victim_way; + logic [7:0] lfsr_val; + // }}} + + // Victim way selection + // {{{ + assign unused_ways = ~sel_dir_fetch_i & ~sel_dir_valid_i; + assign rand_ways = ~sel_dir_fetch_i & sel_dir_valid_i & rand_victim_way; + assign clean_ways = ~sel_dir_fetch_i & sel_dir_valid_i & ~sel_dir_dirty_i; + assign dirty_ways = ~sel_dir_fetch_i & sel_dir_valid_i & sel_dir_dirty_i; + + hpdcache_lfsr #(.WIDTH(8)) + lfsr_i( + .clk_i, + .rst_ni, + .shift_i (sel_victim_i & ~unused_available & rand_available), + .val_o (lfsr_val) + ); + + hpdcache_decoder #(.N(HPDcacheCfg.wayIndexWidth)) + rand_way_decoder_i( + .en_i (1'b1), + .val_i (lfsr_val[0 +: HPDcacheCfg.wayIndexWidth]), + .val_o (rand_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + unused_victim_select_i( + .val_i (unused_ways), + .val_o (unused_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + clean_victim_select_i( + .val_i (clean_ways), + .val_o (clean_victim_way) + ); + + hpdcache_prio_1hot_encoder #(.N(HPDcacheCfg.u.ways)) + dirty_victim_select_i( + .val_i (dirty_ways), + .val_o (dirty_victim_way) + ); + + assign unused_available = |unused_ways; + assign rand_available = |rand_ways; + assign clean_available = |clean_ways; + assign dirty_available = |dirty_ways; + + always_comb + begin : victim_way_selection_comb + priority case (1'b1) + unused_available: sel_victim_way_o = unused_victim_way; + rand_available: sel_victim_way_o = rand_victim_way; + clean_available: sel_victim_way_o = clean_victim_way; + dirty_available: sel_victim_way_o = dirty_victim_way; + default: sel_victim_way_o = '0; + endcase + end + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv new file mode 100644 index 0000000000..f2e1b91ef9 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv @@ -0,0 +1,121 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : Mars, 2024 + * Description : HPDcache Victim Selection + * History : + */ +module hpdcache_victim_sel +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type hpdcache_set_t = logic, + parameter type hpdcache_way_vector_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Victim policy update interface + input logic updt_i, + input hpdcache_set_t updt_set_i, + input hpdcache_way_vector_t updt_way_i, + + // Victim selection interface + input logic sel_victim_i, + input hpdcache_way_vector_t sel_dir_valid_i, + input hpdcache_way_vector_t sel_dir_wback_i, + input hpdcache_way_vector_t sel_dir_dirty_i, + input hpdcache_way_vector_t sel_dir_fetch_i, + input hpdcache_set_t sel_victim_set_i, + output hpdcache_way_vector_t sel_victim_way_o +); +// }}} + + // ----------------------------------------------------------------------- + // Direct mapped cache (one way) + if (HPDcacheCfg.u.ways == 1) + begin : gen_single_way_victim_sel + assign sel_victim_way_o = 1'b1; + end + + // ----------------------------------------------------------------------- + // Set-associative cache with pseudo random victim selection + else if (HPDcacheCfg.u.victimSel == HPDCACHE_VICTIM_RANDOM) + begin : gen_random_victim_sel + hpdcache_victim_random #( + .HPDcacheCfg (HPDcacheCfg) + ) victim_rand_i( + .clk_i, + .rst_ni, + + .updt_i, + .updt_set_i, + .updt_way_i, + + .sel_victim_i, + .sel_dir_valid_i, + .sel_dir_wback_i, + .sel_dir_dirty_i, + .sel_dir_fetch_i, + .sel_victim_set_i, + .sel_victim_way_o + ); + end + + // ----------------------------------------------------------------------- + // Set-associative cache with pseudo least-recently-used victim selection + else if (HPDcacheCfg.u.victimSel == HPDCACHE_VICTIM_PLRU) + begin : gen_plru_victim_sel + hpdcache_victim_plru #( + .HPDcacheCfg (HPDcacheCfg) + ) victim_plru_i( + .clk_i, + .rst_ni, + + .updt_i, + .updt_set_i, + .updt_way_i, + + .sel_victim_i, + .sel_dir_valid_i, + .sel_dir_wback_i, + .sel_dir_dirty_i, + .sel_dir_fetch_i, + .sel_victim_set_i, + .sel_victim_way_o + ); + end + +`ifndef HPDCACHE_ASSERT_OFF + initial victim_sel_assert: + assert (HPDcacheCfg.u.victimSel inside {HPDCACHE_VICTIM_RANDOM, HPDCACHE_VICTIM_PLRU}) + else $fatal("unsupported victim selection policy"); +`endif + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv new file mode 100644 index 0000000000..e4354152b5 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv @@ -0,0 +1,725 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : HPDcache Write Buffer + * History : + */ +module hpdcache_wbuf +import hpdcache_pkg::*; + // Parameters + // {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + + parameter type wbuf_addr_t = logic, + parameter type wbuf_timecnt_t = logic, + + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_w_t = logic, + + localparam int unsigned WBUF_WORD_WIDTH = HPDcacheCfg.u.reqWords*HPDcacheCfg.u.wordWidth, + localparam type wbuf_data_t = logic [WBUF_WORD_WIDTH-1:0], + localparam type wbuf_be_t = logic [WBUF_WORD_WIDTH/8-1:0] +) + // }}} + + // Ports + // {{{ +( + // Clock and reset signals + input logic clk_i, + input logic rst_ni, + + // Global control signals + output logic empty_o, + output logic full_o, + input logic flush_all_i, + + // Configuration signals + // Timer threshold + input wbuf_timecnt_t cfg_threshold_i, + // Reset timer on write + input logic cfg_reset_timecnt_on_write_i, + // Sequentialize write-after-write hazards + input logic cfg_sequential_waw_i, + // Inhibit write coalescing + input logic cfg_inhibit_write_coalescing_i, + + // Write interface + input logic write_i, + output logic write_ready_o, + input wbuf_addr_t write_addr_i, + input wbuf_data_t write_data_i, + input wbuf_be_t write_be_i, // byte-enable + input logic write_uc_i, // uncacheable write + + // Read hit interface + input wbuf_addr_t read_addr_i, + output logic read_hit_o, + input logic read_flush_hit_i, + + // Replay hit interface + input wbuf_addr_t replay_addr_i, + input logic replay_is_read_i, + output logic replay_open_hit_o, + output logic replay_pend_hit_o, + output logic replay_sent_hit_o, + output logic replay_not_ready_o, + + // Memory interface + input logic mem_req_write_ready_i, + output logic mem_req_write_valid_o, + output hpdcache_mem_req_t mem_req_write_o, + + input logic mem_req_write_data_ready_i, + output logic mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t mem_req_write_data_o, + + output logic mem_resp_write_ready_o, + input logic mem_resp_write_valid_i, + input hpdcache_mem_resp_w_t mem_resp_write_i +); + // }}} + + // Definition of constants, types and functions + // {{{ + localparam int unsigned WBUF_DIR_NENTRIES = HPDcacheCfg.u.wbufDirEntries; + localparam int unsigned WBUF_DATA_NENTRIES = HPDcacheCfg.u.wbufDataEntries; + localparam int unsigned WBUF_DATA_NWORDS = HPDcacheCfg.u.wbufWords; + localparam int unsigned WBUF_OFFSET_WIDTH = $clog2((WBUF_WORD_WIDTH/8)*WBUF_DATA_NWORDS); + localparam int unsigned WBUF_TAG_WIDTH = HPDcacheCfg.u.paWidth - WBUF_OFFSET_WIDTH; + localparam int unsigned WBUF_WORD_OFFSET = $clog2(WBUF_WORD_WIDTH/8); + localparam int WBUF_SEND_FIFO_DEPTH = WBUF_DATA_NENTRIES; + localparam int unsigned WBUF_READ_MATCH_WIDTH = HPDcacheCfg.nlineWidth; + localparam int unsigned WBUF_MEM_DATA_RATIO = HPDcacheCfg.u.memDataWidth/ + HPDcacheCfg.wbufDataWidth; + localparam int unsigned WBUF_MEM_DATA_WORD_INDEX_WIDTH = $clog2(WBUF_MEM_DATA_RATIO); + + typedef wbuf_data_t [WBUF_DATA_NWORDS-1:0] wbuf_data_buf_t; + typedef wbuf_be_t [WBUF_DATA_NWORDS-1:0] wbuf_be_buf_t; + typedef logic unsigned [HPDcacheCfg.wbufDirPtrWidth-1:0] wbuf_dir_ptr_t; + typedef logic unsigned [HPDcacheCfg.wbufDataPtrWidth-1:0] wbuf_data_ptr_t; + typedef logic unsigned [WBUF_TAG_WIDTH-1:0] wbuf_tag_t; + typedef logic unsigned [HPDcacheCfg.nlineWidth-1:0] wbuf_match_t; + + typedef enum logic [1:0] { + WBUF_FREE = 2'b00, // unused/free slot + WBUF_OPEN = 2'b01, // there are pending writes in this slot + WBUF_PEND = 2'b10, // the slot is waiting to be sent + WBUF_SENT = 2'b11 // the slot is sent and waits for the memory acknowledge + } wbuf_state_e; + + typedef struct packed { + wbuf_data_ptr_t ptr; + wbuf_timecnt_t cnt; + wbuf_tag_t tag; + logic uc; + } wbuf_dir_entry_t; + + typedef struct packed { + wbuf_data_buf_t data; + wbuf_be_buf_t be; + } wbuf_data_entry_t; + + typedef struct packed { + wbuf_data_ptr_t data_ptr; + wbuf_tag_t data_tag; + } wbuf_send_data_t; + + typedef struct packed { + wbuf_tag_t meta_tag; + wbuf_dir_ptr_t meta_id; + logic meta_uc; + } wbuf_send_meta_t; + + function automatic void wbuf_data_write( + output wbuf_data_buf_t wbuf_ret_data, + output wbuf_be_buf_t wbuf_ret_be, + input wbuf_data_buf_t wbuf_old_data, + input wbuf_be_buf_t wbuf_old_be, + input wbuf_data_buf_t wbuf_new_data, + input wbuf_be_buf_t wbuf_new_be); + for (int unsigned w = 0; w < WBUF_DATA_NWORDS; w++) begin + for (int unsigned b = 0; b < WBUF_WORD_WIDTH/8; b++) begin + wbuf_ret_data[w][b*8 +: 8] = wbuf_new_be[w][b] ? + wbuf_new_data[w][b*8 +: 8] : + wbuf_old_data[w][b*8 +: 8]; + end + wbuf_ret_be[w] = wbuf_old_be[w] | wbuf_new_be[w]; + end + endfunction + + function automatic wbuf_match_t wbuf_tag_to_match_addr(wbuf_tag_t tag); + return tag[WBUF_TAG_WIDTH - 1:WBUF_TAG_WIDTH - WBUF_READ_MATCH_WIDTH]; + endfunction + // }}} + + // Definition of internal wires and registers + // {{{ + wbuf_state_e [WBUF_DIR_NENTRIES-1:0] wbuf_dir_state_q, wbuf_dir_state_d; + wbuf_dir_entry_t [WBUF_DIR_NENTRIES-1:0] wbuf_dir_q, wbuf_dir_d; + logic [WBUF_DATA_NENTRIES-1:0] wbuf_data_valid_q, wbuf_data_valid_d; + wbuf_data_entry_t [WBUF_DATA_NENTRIES-1:0] wbuf_data_q, wbuf_data_d; + + logic wbuf_dir_free; + logic [WBUF_DIR_NENTRIES-1:0] wbuf_dir_free_ptr_bv; + logic wbuf_data_free; + wbuf_data_ptr_t wbuf_data_free_ptr; + logic [WBUF_DATA_NENTRIES-1:0] wbuf_data_free_ptr_bv; + + logic wbuf_write_free; + logic wbuf_write_hit_open; + logic wbuf_write_hit_pend; + logic wbuf_write_hit_sent; + wbuf_dir_ptr_t wbuf_write_hit_open_dir_ptr; + wbuf_dir_ptr_t wbuf_write_hit_pend_dir_ptr; + + logic [WBUF_DIR_NENTRIES-1:0] wbuf_dir_free_bv; + logic [WBUF_DIR_NENTRIES-1:0] wbuf_dir_open_bv; + logic [WBUF_DIR_NENTRIES-1:0] wbuf_dir_pend_bv; + logic [WBUF_DIR_NENTRIES-1:0] wbuf_dir_sent_bv; + + logic [WBUF_DIR_NENTRIES-1:0] wbuf_send_grant; + wbuf_send_meta_t [WBUF_DIR_NENTRIES-1:0] wbuf_meta_pend; + wbuf_data_ptr_t [WBUF_DIR_NENTRIES-1:0] wbuf_meta_pend_data_ptr; + wbuf_data_ptr_t wbuf_meta_send_data_ptr; + + logic send_meta_valid; + logic send_meta_ready; + wbuf_send_meta_t wbuf_meta_send, wbuf_meta_send_q; + + logic send_data_ready; + logic send_data_w; + wbuf_send_data_t send_data_d; + wbuf_send_data_t send_data_q; + + wbuf_addr_t send_tag; + wbuf_data_buf_t send_data; + wbuf_be_buf_t send_be; + + wbuf_dir_ptr_t ack_id; + logic ack_error; + + wbuf_tag_t write_tag; + wbuf_data_buf_t write_data; + wbuf_be_buf_t write_be; + + logic [WBUF_DIR_NENTRIES-1:0] replay_match; + logic [WBUF_DIR_NENTRIES-1:0] replay_open_hit; + logic [WBUF_DIR_NENTRIES-1:0] replay_pend_hit; + logic [WBUF_DIR_NENTRIES-1:0] replay_sent_hit; + + genvar gen_i; + // }}} + + // Global control signals + // {{{ + for (gen_i = 0; gen_i < WBUF_DIR_NENTRIES; gen_i++) begin : gen_dir_state_bv + assign wbuf_dir_free_bv[gen_i] = (wbuf_dir_state_q[gen_i] == WBUF_FREE); + assign wbuf_dir_open_bv[gen_i] = (wbuf_dir_state_q[gen_i] == WBUF_OPEN); + assign wbuf_dir_pend_bv[gen_i] = (wbuf_dir_state_q[gen_i] == WBUF_PEND); + assign wbuf_dir_sent_bv[gen_i] = (wbuf_dir_state_q[gen_i] == WBUF_SENT); + end + + always_comb + begin : empty_comb + empty_o = 1'b1; + for (int unsigned i = 0; i < WBUF_DIR_NENTRIES; i++) begin + empty_o &= wbuf_dir_free_bv[i]; + end + end + + always_comb + begin : full_comb + full_o = 1'b1; + for (int unsigned i = 0; i < WBUF_DIR_NENTRIES; i++) begin + full_o &= ~wbuf_dir_free_bv[i]; + end + end + // }}} + + // Write control + // {{{ + assign write_tag = write_addr_i[HPDcacheCfg.u.paWidth-1:WBUF_OFFSET_WIDTH]; + assign ack_id = mem_resp_write_i.mem_resp_w_id[0 +: HPDcacheCfg.wbufDirPtrWidth]; + assign ack_error = (mem_resp_write_i.mem_resp_w_error != HPDCACHE_MEM_RESP_OK); + + always_comb + begin : wbuf_write_data_comb + for (int unsigned w = 0; w < WBUF_DATA_NWORDS; w++) begin + write_data[w] = write_data_i; + end + end + + if (WBUF_OFFSET_WIDTH > WBUF_WORD_OFFSET) begin : gen_wbuf_write_be_gt + always_comb + begin : wbuf_write_be_comb + for (int unsigned w = 0; w < WBUF_DATA_NWORDS; w++) begin + if (w == hpdcache_uint32'(write_addr_i[WBUF_OFFSET_WIDTH-1:WBUF_WORD_OFFSET])) + begin + write_be[w] = write_be_i; + end else begin + write_be[w] = '0; + end + end + end + end else begin : gen_wbuf_write_be_le + always_comb + begin : wbuf_write_be_comb + for (int unsigned w = 0; w < WBUF_DATA_NWORDS; w++) begin + write_be[w] = write_be_i; + end + end + end + + hpdcache_fxarb #( + .N (WBUF_DIR_NENTRIES) + ) dir_free_rrarb_i( + .clk_i, + .rst_ni, + .req_i (wbuf_dir_free_bv), + .gnt_o (wbuf_dir_free_ptr_bv), + .ready_i (write_i & wbuf_write_free) + ); + + hpdcache_fxarb #( + .N (WBUF_DATA_NENTRIES) + ) data_free_rrarb_i( + .clk_i, + .rst_ni, + .req_i (~wbuf_data_valid_q), + .gnt_o (wbuf_data_free_ptr_bv), + .ready_i (write_i & wbuf_write_free) + ); + + hpdcache_1hot_to_binary #( + .N (WBUF_DATA_NENTRIES) + ) data_free_ptr_binary_i( + .val_i (wbuf_data_free_ptr_bv), + .val_o (wbuf_data_free_ptr) + ); + + assign wbuf_dir_free = |wbuf_dir_free_bv; + assign wbuf_data_free = ~(&wbuf_data_valid_q); + + always_comb + begin : wbuf_write_hit_comb + wbuf_write_hit_open = 1'b0; + wbuf_write_hit_pend = 1'b0; + wbuf_write_hit_sent = 1'b0; + + wbuf_write_hit_open_dir_ptr = 0; + wbuf_write_hit_pend_dir_ptr = 0; + for (int unsigned i = 0; i < WBUF_DIR_NENTRIES; i++) begin + if (wbuf_dir_q[i].tag == write_tag) begin + unique case (wbuf_dir_state_q[i]) + WBUF_OPEN: begin + wbuf_write_hit_open = 1'b1; + wbuf_write_hit_open_dir_ptr = wbuf_dir_ptr_t'(i); + end + WBUF_PEND: begin + wbuf_write_hit_pend = 1'b1; + wbuf_write_hit_pend_dir_ptr = wbuf_dir_ptr_t'(i); + end + WBUF_SENT: begin + wbuf_write_hit_sent = 1'b1; + end + default: begin + /* do nothing */ + end + endcase + end + end + end + + // Check if there is a match between the read address and the tag of one + // of the used slots in the write buffer directory + always_comb + begin : read_hit_comb + automatic logic [WBUF_DIR_NENTRIES-1:0] read_hit; + + for (int unsigned i = 0; i < WBUF_DIR_NENTRIES; i++) begin + read_hit[i] = 1'b0; + unique case (wbuf_dir_state_q[i]) + WBUF_OPEN, WBUF_PEND, WBUF_SENT: begin + automatic wbuf_addr_t wbuf_addr; + automatic wbuf_match_t wbuf_tag; + automatic wbuf_match_t read_tag; + + wbuf_addr = wbuf_addr_t'(wbuf_dir_q[i].tag) << WBUF_OFFSET_WIDTH; + read_tag = read_addr_i[HPDcacheCfg.u.paWidth-1:HPDcacheCfg.u.paWidth - + WBUF_READ_MATCH_WIDTH]; + wbuf_tag = wbuf_addr [HPDcacheCfg.u.paWidth-1:HPDcacheCfg.u.paWidth - + WBUF_READ_MATCH_WIDTH]; + read_hit[i] = (read_tag == wbuf_tag) ? 1'b1 : 1'b0; + end + default: begin + /* do nothing */ + end + endcase + end + + read_hit_o = |read_hit; + end + + // Check if there is a match between the replay address and the tag of one + // of the used slots in the write buffer directory + generate + for (gen_i = 0; gen_i < WBUF_DIR_NENTRIES; gen_i++) begin : gen_replay_match + assign replay_match[gen_i] = replay_is_read_i ? + /* replay is read: compare address block tag (e.g. cache line) */ + (wbuf_tag_to_match_addr(wbuf_dir_q[gen_i].tag) == + replay_addr_i[HPDcacheCfg.u.paWidth - 1: + HPDcacheCfg.u.paWidth - WBUF_READ_MATCH_WIDTH]) : + /* replay is write: compare wbuf tag */ + (wbuf_dir_q[gen_i].tag == + replay_addr_i[HPDcacheCfg.u.paWidth - 1: + HPDcacheCfg.u.paWidth - WBUF_TAG_WIDTH]); + + assign replay_open_hit[gen_i] = replay_match[gen_i] & wbuf_dir_open_bv[gen_i]; + assign replay_pend_hit[gen_i] = replay_match[gen_i] & wbuf_dir_pend_bv[gen_i]; + assign replay_sent_hit[gen_i] = replay_match[gen_i] & wbuf_dir_sent_bv[gen_i]; + end + endgenerate + + assign replay_open_hit_o = |replay_open_hit; + assign replay_pend_hit_o = |replay_pend_hit; + assign replay_sent_hit_o = |replay_sent_hit; + + always_comb + begin : replay_wbuf_not_ready_comb + replay_not_ready_o = 1'b0; + if (replay_pend_hit_o) begin + replay_not_ready_o = 1'b1; + end else if (replay_sent_hit_o && cfg_sequential_waw_i) begin + replay_not_ready_o = 1'b1; + end else if (!replay_open_hit_o && (!wbuf_dir_free || !wbuf_data_free)) begin + replay_not_ready_o = 1'b1; + end + end + + assign wbuf_write_free = + wbuf_dir_free + & wbuf_data_free + & ~wbuf_write_hit_open + & ~wbuf_write_hit_pend + & ~(wbuf_write_hit_sent & cfg_sequential_waw_i); + + assign write_ready_o = wbuf_write_free + | ((wbuf_write_hit_open | wbuf_write_hit_pend) + & ~cfg_inhibit_write_coalescing_i); + // }}} + + // Update control + // {{{ + always_comb + begin : wbuf_update_comb + automatic bit timeout; + automatic bit write_hit; + automatic bit read_hit; + automatic bit match_open_ptr; + automatic bit match_pend_ptr; + automatic bit match_free; + automatic bit send; + + timeout = 1'b0; + write_hit = 1'b0; + read_hit = 1'b0; + match_open_ptr = 1'b0; + match_pend_ptr = 1'b0; + match_free = 1'b0; + send = 1'b0; + + wbuf_dir_state_d = wbuf_dir_state_q; + wbuf_dir_d = wbuf_dir_q; + wbuf_data_d = wbuf_data_q; + + for (int unsigned i = 0; i < WBUF_DIR_NENTRIES; i++) begin + unique case (wbuf_dir_state_q[i]) + WBUF_FREE: begin + match_free = wbuf_write_free & wbuf_dir_free_ptr_bv[i]; + + if (write_i && match_free) begin + send = (cfg_threshold_i == 0) + | write_uc_i + | flush_all_i + | cfg_inhibit_write_coalescing_i; + + wbuf_dir_state_d[i] = send ? WBUF_PEND : WBUF_OPEN; + wbuf_dir_d[i].tag = write_tag; + wbuf_dir_d[i].cnt = 0; + wbuf_dir_d[i].ptr = wbuf_data_free_ptr; + wbuf_dir_d[i].uc = write_uc_i; + + wbuf_data_write( + wbuf_data_d[wbuf_data_free_ptr].data, + wbuf_data_d[wbuf_data_free_ptr].be, + '0, + '0, + write_data, + write_be + ); + end + end + + WBUF_OPEN: begin + match_open_ptr = (i == hpdcache_uint32'(wbuf_write_hit_open_dir_ptr)); + timeout = (wbuf_dir_q[i].cnt == (cfg_threshold_i - 1)); + read_hit = read_flush_hit_i & wbuf_write_hit_open & match_open_ptr; + write_hit = write_i + & wbuf_write_hit_open + & match_open_ptr + & ~cfg_inhibit_write_coalescing_i; + + if (!flush_all_i) begin + if (write_hit && cfg_reset_timecnt_on_write_i) begin + timeout = 1'b0; + wbuf_dir_d[i].cnt = 0; + end else if (!timeout) begin + wbuf_dir_d[i].cnt = wbuf_dir_q[i].cnt + 1; + end + + if (read_hit | timeout | cfg_inhibit_write_coalescing_i) begin + wbuf_dir_state_d[i] = WBUF_PEND; + end + end else begin + wbuf_dir_state_d[i] = WBUF_PEND; + end + + if (write_hit) begin + wbuf_data_write( + wbuf_data_d[wbuf_dir_q[i].ptr].data, + wbuf_data_d[wbuf_dir_q[i].ptr].be, + wbuf_data_q[wbuf_dir_q[i].ptr].data, + wbuf_data_q[wbuf_dir_q[i].ptr].be, + write_data, + write_be + ); + end + end + + WBUF_PEND: begin + match_pend_ptr = (i == hpdcache_uint32'(wbuf_write_hit_pend_dir_ptr)); + write_hit = write_i + & wbuf_write_hit_pend + & match_pend_ptr + & ~cfg_inhibit_write_coalescing_i; + + if (write_hit) begin + wbuf_data_write( + wbuf_data_d[wbuf_dir_q[i].ptr].data, + wbuf_data_d[wbuf_dir_q[i].ptr].be, + wbuf_data_q[wbuf_dir_q[i].ptr].data, + wbuf_data_q[wbuf_dir_q[i].ptr].be, + write_data, + write_be + ); + end + + if (wbuf_send_grant[i] && send_data_ready && send_meta_ready) begin + wbuf_dir_state_d[i] = WBUF_SENT; + end + end + + WBUF_SENT: begin + if (mem_resp_write_valid_i && (i == hpdcache_uint32'(ack_id))) begin + wbuf_dir_state_d[i] = WBUF_FREE; + end + end + endcase + end + end + + always_comb + begin : wbuf_data_valid_comb + wbuf_data_valid_d = wbuf_data_valid_q; + + // allocate a free data buffer on new write + if (write_i && wbuf_write_free) begin + wbuf_data_valid_d[wbuf_data_free_ptr] = 1'b1; + end + + // de-allocate a data buffer as soon as it is send + if (mem_req_write_data_valid_o && mem_req_write_data_ready_i) begin + wbuf_data_valid_d[send_data_q.data_ptr] = 1'b0; + end + end + // }}} + + // Send control + // {{{ + for (genvar i = 0; i < WBUF_DIR_NENTRIES; i++) begin : gen_wbuf_dir_pend + assign wbuf_meta_pend[i].meta_tag = wbuf_dir_q[i].tag; + assign wbuf_meta_pend[i].meta_id = i; + assign wbuf_meta_pend[i].meta_uc = wbuf_dir_q[i].uc; + assign wbuf_meta_pend_data_ptr[i] = wbuf_dir_q[i].ptr; + end + + hpdcache_rrarb #( + .N (WBUF_DIR_NENTRIES) + ) pend_rrarb_i( + .clk_i, + .rst_ni, + .req_i (wbuf_dir_pend_bv), + .gnt_o (wbuf_send_grant), + .ready_i (send_data_ready & send_meta_ready) + ); + + hpdcache_mux #( + .NINPUT (WBUF_DIR_NENTRIES), + .DATA_WIDTH ($bits(wbuf_send_meta_t)), + .ONE_HOT_SEL (1'b1) + ) wbuf_send_meta_mux_i( + .data_i (wbuf_meta_pend), + .sel_i (wbuf_send_grant), + .data_o (wbuf_meta_send) + ); + + hpdcache_mux #( + .NINPUT (WBUF_DIR_NENTRIES), + .DATA_WIDTH ($bits(wbuf_data_ptr_t)), + .ONE_HOT_SEL (1'b1) + ) wbuf_send_data_ptr_mux_i( + .data_i (wbuf_meta_pend_data_ptr), + .sel_i (wbuf_send_grant), + .data_o (wbuf_meta_send_data_ptr) + ); + + // Data channel + assign send_data_w = (|wbuf_dir_pend_bv) & send_meta_ready; + assign send_data_d.data_ptr = wbuf_meta_send_data_ptr; + assign send_data_d.data_tag = wbuf_meta_send.meta_tag; + + hpdcache_fifo_reg #( + .FIFO_DEPTH (WBUF_SEND_FIFO_DEPTH), + .FEEDTHROUGH (1'b0), + .fifo_data_t (wbuf_send_data_t) + ) send_data_ptr_fifo_i ( + .clk_i, + .rst_ni, + .w_i (send_data_w), + .wok_o (send_data_ready), + .wdata_i (send_data_d), + .r_i (mem_req_write_data_ready_i), + .rok_o (mem_req_write_data_valid_o), + .rdata_o (send_data_q) + ); + + assign send_tag = wbuf_addr_t'(send_data_q.data_tag); + assign send_data = wbuf_data_q[send_data_q.data_ptr].data; + assign send_be = wbuf_data_q[send_data_q.data_ptr].be; + + // Meta-data channel + assign send_meta_valid = (|wbuf_dir_pend_bv) & send_data_ready; + + hpdcache_fifo_reg #( + .FIFO_DEPTH (WBUF_SEND_FIFO_DEPTH), + .FEEDTHROUGH (1'b0), + .fifo_data_t (wbuf_send_meta_t) + ) send_meta_fifo_i ( + .clk_i, + .rst_ni, + .w_i (send_meta_valid), + .wok_o (send_meta_ready), + .wdata_i (wbuf_meta_send), + .r_i (mem_req_write_ready_i), + .rok_o (mem_req_write_valid_o), + .rdata_o (wbuf_meta_send_q) + ); + // }}} + + // Memory Address and Data Interface + // {{{ + assign mem_req_write_o.mem_req_addr = { wbuf_meta_send_q.meta_tag, {WBUF_OFFSET_WIDTH{1'b0}} }; + assign mem_req_write_o.mem_req_len = 0; + assign mem_req_write_o.mem_req_size = get_hpdcache_mem_size(HPDcacheCfg.wbufDataWidth/8); + assign mem_req_write_o.mem_req_id = hpdcache_mem_id_t'(wbuf_meta_send_q.meta_id); + assign mem_req_write_o.mem_req_command = HPDCACHE_MEM_WRITE; + assign mem_req_write_o.mem_req_atomic = HPDCACHE_MEM_ATOMIC_ADD; + assign mem_req_write_o.mem_req_cacheable = ~wbuf_meta_send_q.meta_uc; + + assign mem_req_write_data_o.mem_req_w_last = 1'b1; + + if (WBUF_MEM_DATA_RATIO > 1) begin : gen_wbuf_data_upsizing + logic [HPDcacheCfg.wbufDataWidth/8-1:0][WBUF_MEM_DATA_RATIO-1:0] mem_req_be; + + // demux send BE + hpdcache_demux #( + .NOUTPUT (WBUF_MEM_DATA_RATIO), + .DATA_WIDTH (HPDcacheCfg.wbufDataWidth/8), + .ONE_HOT_SEL (1'b0) + ) mem_write_be_demux_i ( + .data_i (send_be), + .sel_i (send_tag[0 +: WBUF_MEM_DATA_WORD_INDEX_WIDTH]), + .data_o (mem_req_be) + ); + + assign mem_req_write_data_o.mem_req_w_data = {WBUF_MEM_DATA_RATIO{send_data}}, + mem_req_write_data_o.mem_req_w_be = mem_req_be; + + end else if (WBUF_MEM_DATA_RATIO == 1) begin : gen_wbuf_data_forwarding + assign mem_req_write_data_o.mem_req_w_data = send_data, + mem_req_write_data_o.mem_req_w_be = send_be; + end + + assign mem_resp_write_ready_o = 1'b1; + // }}} + + // Internal state assignment + // {{{ + always_ff @(posedge clk_i) wbuf_data_q <= wbuf_data_d; + + always_ff @(posedge clk_i or negedge rst_ni) + begin : wbuf_state_ff + if (!rst_ni) begin + wbuf_dir_q <= '0; + wbuf_dir_state_q <= {WBUF_DIR_NENTRIES{WBUF_FREE}}; + wbuf_data_valid_q <= '0; + end else begin + wbuf_dir_q <= wbuf_dir_d; + wbuf_dir_state_q <= wbuf_dir_state_d; + wbuf_data_valid_q <= wbuf_data_valid_d; + end + end + // }}} + + // Assertions + // {{{ +`ifndef HPDCACHE_ASSERT_OFF + initial assert(WBUF_DATA_NWORDS inside {1, 2, 4, 8, 16}) else + $fatal("WBUF: width of data buffers must be a power of 2"); + initial assert(WBUF_MEM_DATA_RATIO > 0) else + $fatal($sformatf("WBUF: width of mem interface (%d) shall be g.e. to wbuf width(%d)", + HPDcacheCfg.u.memDataWidth, HPDcacheCfg.wbufDataWidth)); + initial assert (HPDcacheCfg.wbufDirPtrWidth <= HPDcacheCfg.u.memIdWidth) else + $fatal("MemIdWidth is not wide enough to fit all possible write buffer transactions"); + ack_sent_assert: assert property (@(posedge clk_i) disable iff (!rst_ni) + (mem_resp_write_valid_i -> (wbuf_dir_state_q[ack_id] == WBUF_SENT))) else + $error("WBUF: acknowledging a not SENT slot"); + send_valid_data_assert: assert property (@(posedge clk_i) disable iff (!rst_ni) + (mem_req_write_data_valid_o -> (wbuf_data_valid_q[send_data_q.data_ptr] == 1'b1))) else + $error("WBUF: sending a not valid data"); +`endif + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv new file mode 100644 index 0000000000..fd846bd915 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv @@ -0,0 +1,379 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Riccardo Alidori, Cesar Fuguet + * Maintainers(s): Cesar Fuguet + * Creation Date : June, 2021 + * Description : HPDcache Linear Hardware Memory Prefetcher. + * History : + */ +module hwpf_stride +import hwpf_stride_pkg::*; +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter type hpdcache_nline_t = logic, + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_set_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // CSR + input logic csr_base_set_i, + input hwpf_stride_base_t csr_base_i, + input logic csr_param_set_i, + input hwpf_stride_param_t csr_param_i, + input logic csr_throttle_set_i, + input hwpf_stride_throttle_t csr_throttle_i, + + output hwpf_stride_base_t csr_base_o, + output hwpf_stride_param_t csr_param_o, + output hwpf_stride_throttle_t csr_throttle_o, + + // If high, the prefetcher is enabled and active + output logic busy_o, + + // Snooping + // Address to snoop on requests ports + output hpdcache_nline_t snoop_nline_o, + // If set to one, the snoop address matched one of the requests + input logic snoop_match_i, + + // D-Cache interface + output logic hpdcache_req_valid_o, + input logic hpdcache_req_ready_i, + output hpdcache_req_t hpdcache_req_o, + input logic hpdcache_rsp_valid_i, + input hpdcache_rsp_t hpdcache_rsp_i +); +// }}} + + // Definition of constants + // {{{ + localparam int STRIDE_WIDTH = $bits(csr_param_i.stride); + localparam int NBLOCKS_WIDTH = $bits(csr_param_i.nblocks); + localparam int NLINES_WIDTH = $bits(csr_param_i.nlines); + localparam int NWAIT_WIDTH = $bits(csr_throttle_i.nwait); + localparam int INFLIGHT_WIDTH = $bits(csr_throttle_i.ninflight); + localparam int NLINES_CNT_WIDTH = NLINES_WIDTH; + // }}} + + // Internal registers and signals + // {{{ + // FSM + typedef enum { + IDLE, + SNOOP, + SEND_REQ, + WAIT, + DONE, + ABORT + } hwpf_stride_fsm_t; + + hwpf_stride_fsm_t state_d, state_q; + + logic [NBLOCKS_WIDTH-1:0] nblocks_cnt_d, nblocks_cnt_q; + logic [NLINES_CNT_WIDTH-1:0] nlines_cnt_d, nlines_cnt_q; + logic [NWAIT_WIDTH-1:0] nwait_cnt_d, nwait_cnt_q; + logic [INFLIGHT_WIDTH-1:0] inflight_cnt_d, inflight_cnt_q; + logic inflight_inc, inflight_dec; + + hwpf_stride_base_t csr_base_q; + hwpf_stride_base_t shadow_base_q, shadow_base_d; + hwpf_stride_param_t csr_param_q; + hwpf_stride_param_t shadow_param_q, shadow_param_d; + hwpf_stride_throttle_t csr_throttle_q; + hwpf_stride_throttle_t shadow_throttle_q, shadow_throttle_d; + hpdcache_nline_t request_nline_q, request_nline_d; + + hpdcache_set_t hpdcache_req_set; + hpdcache_tag_t hpdcache_req_tag; + + logic csr_base_update; + hpdcache_nline_t increment_stride; + logic is_inflight_max; + + // Default assignment + assign increment_stride = hpdcache_nline_t'(shadow_param_q.stride) + 1'b1; + assign inflight_dec = hpdcache_rsp_valid_i; + assign snoop_nline_o = shadow_base_q.base_cline; + assign is_inflight_max = (shadow_throttle_q.ninflight == '0) ? + 1'b0 : (inflight_cnt_q >= shadow_throttle_q.ninflight); + assign csr_base_o = csr_base_q; + assign csr_param_o = csr_param_q; + assign csr_throttle_o = csr_throttle_q; + // }}} + + // Dcache outputs + // {{{ + assign hpdcache_req_set = request_nline_q[0 +: HPDcacheCfg.setWidth], + hpdcache_req_tag = request_nline_q[HPDcacheCfg.setWidth +: HPDcacheCfg.tagWidth]; + + assign hpdcache_req_o.addr_offset = { hpdcache_req_set, {HPDcacheCfg.clOffsetWidth{1'b0}} }, + hpdcache_req_o.wdata = '0, + hpdcache_req_o.op = HPDCACHE_REQ_CMO_PREFETCH, + hpdcache_req_o.be = '1, + hpdcache_req_o.size = '0, + hpdcache_req_o.sid = '0, // this is set when connecting to the dcache + hpdcache_req_o.tid = '0, // this is set by the wrapper of the prefetcher + hpdcache_req_o.need_rsp = 1'b1, + hpdcache_req_o.phys_indexed = 1'b1, + hpdcache_req_o.addr_tag = hpdcache_req_tag, + hpdcache_req_o.pma.uncacheable = 1'b0, + hpdcache_req_o.pma.io = 1'b0; + // }}} + + // Set state of internal registers + // {{{ + always_ff @(posedge clk_i or negedge rst_ni) + begin + if (!rst_ni) begin + csr_base_q <= '0; + csr_param_q <= '0; + shadow_base_q <= '0; + shadow_param_q <= '0; + shadow_throttle_q <= '0; + request_nline_q <= '0; + state_q <= IDLE; + end else begin + if (csr_base_set_i) csr_base_q <= csr_base_i; + else if (csr_base_update) csr_base_q <= shadow_base_d; + if (csr_param_set_i) csr_param_q <= csr_param_i; + if (csr_throttle_set_i) csr_throttle_q <= csr_throttle_i; + shadow_base_q <= shadow_base_d; + shadow_param_q <= shadow_param_d; + shadow_throttle_q <= shadow_throttle_d; + request_nline_q <= request_nline_d; + state_q <= state_d; + end + end + // }}} + + // Update internal counters + // {{{ + always_comb begin : inflight_cnt + inflight_cnt_d = inflight_cnt_q; + + // Every time we send a dcache request, increment the counter + if ( inflight_inc ) begin + inflight_cnt_d++; + end + + // Every time we got a response from the cache, decrement the counter + if ( inflight_dec && ( inflight_cnt_q > 0 )) begin + inflight_cnt_d--; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + nblocks_cnt_q <= '0; + nlines_cnt_q <= '0; + nwait_cnt_q <= '0; + inflight_cnt_q <= '0; + end else begin + nblocks_cnt_q <= nblocks_cnt_d; + nlines_cnt_q <= nlines_cnt_d; + nwait_cnt_q <= nwait_cnt_d; + inflight_cnt_q <= inflight_cnt_d; + end + end + // }}} + + // FSM + // {{{ + always_comb begin : fsm_control + // default assignments + hpdcache_req_valid_o = 1'b0; + nblocks_cnt_d = nblocks_cnt_q; + nlines_cnt_d = nlines_cnt_q; + nwait_cnt_d = nwait_cnt_q; + inflight_inc = 1'b0; + busy_o = 1'b0; + csr_base_update = 1'b0; + + shadow_base_d = shadow_base_q; + shadow_param_d = shadow_param_q; + shadow_throttle_d = shadow_throttle_q; + request_nline_d = request_nline_q; + state_d = state_q; + + unique case ( state_q ) + + IDLE: begin + // If enabled, go snooping the dcache ports + if ( csr_base_q.enable ) begin + shadow_base_d = csr_base_q; + if (( csr_param_q.nlines > 0 ) || ( csr_param_q.nblocks > 0 )) begin + shadow_param_d = csr_param_q; + shadow_throttle_d = csr_throttle_q; + state_d = SNOOP; + end else begin + // no prefetch needed, disarm immediately + shadow_base_d.enable = 1'b0; + csr_base_update = 1'b1; + end + end + end + + + SNOOP: begin + if ( csr_base_q.enable ) begin + // If a snooper matched an address, send the request + if ( snoop_match_i ) begin + state_d = SEND_REQ; + + if ( shadow_param_q.nlines == 0 ) begin + // skip the first block + request_nline_d = shadow_base_q.base_cline + + hpdcache_nline_t'(increment_stride); + nblocks_cnt_d = ( shadow_param_q.nblocks > 0 ) ? + shadow_param_q.nblocks - 1 : 0; + nlines_cnt_d = 0; + + // update the base cacheline to the first one of the next block + shadow_base_d.base_cline = request_nline_d; + end else begin + // skip the first cacheline (of the first block) + request_nline_d = shadow_base_q.base_cline + 1'b1; + nblocks_cnt_d = shadow_param_q.nblocks; + nlines_cnt_d = shadow_param_q.nlines - 1; + end + end + end else begin + state_d = IDLE; + end + end + + + SEND_REQ: begin + busy_o = 1'b1; + + // make the prefetch request to memory + hpdcache_req_valid_o = 1'b1; + + // we've got a grant, so we can move to the next request + if ( hpdcache_req_ready_i ) begin + inflight_inc = 1'b1; + + if ( nlines_cnt_q == 0 ) begin + // go to the first cacheline of the next block + request_nline_d = shadow_base_q.base_cline + + hpdcache_nline_t'(increment_stride); + nblocks_cnt_d = ( nblocks_cnt_q > 0 ) ? nblocks_cnt_q - 1 : 0; + nlines_cnt_d = shadow_param_q.nlines; + + // update the base cacheline to the first one of the next block + shadow_base_d.base_cline = request_nline_d; + end else begin + // go to the next cacheline (within the same block) + request_nline_d = request_nline_q + 1'b1; + nlines_cnt_d = nlines_cnt_q - 1; + end + + // if the NWAIT parameter is equal 0, we can issue a request every cycle + if (( nblocks_cnt_q == 0 ) && ( nlines_cnt_q == 0 )) begin + state_d = DONE; + end else if ( shadow_throttle_q.nwait == 0 ) begin + // Wait if the number of inflight requests is greater than + // the maximum indicated. Otherwise, send the next request + state_d = is_inflight_max ? WAIT : SEND_REQ; + end else begin + // Wait the indicated cycles before sending the next request + nwait_cnt_d = shadow_throttle_q.nwait; + state_d = WAIT; + end + + if ( !csr_base_q.enable ) state_d = ABORT; + end + end + + + WAIT: begin + // Wait until: + // - the indicated number of wait cycles between requests is reached (nwait) + // - the number of inflight requests is below the indicated maximum (ninflight) + busy_o = 1'b1; + if ( csr_base_q.enable ) begin + if ( !is_inflight_max && ( nwait_cnt_q == 0 )) begin + state_d = SEND_REQ; + end + + if ( nwait_cnt_q > 0 ) begin + nwait_cnt_d = nwait_cnt_q - 1; + end + end else begin + state_d = ABORT; + end + end + + + DONE: begin + busy_o = 1'b1; + if ( csr_base_q.enable ) begin + if (( inflight_cnt_q == 0 ) && !is_inflight_max && ( nwait_cnt_q == 0 )) begin + // Copy back shadow base register into the user visible one + csr_base_update = 1'b1; + + // Check the rearm bit + if ( shadow_base_q.rearm ) begin + state_d = SNOOP; + end else begin + state_d = IDLE; + + // disarm the prefetcher + shadow_base_d.enable = 1'b0; + end + + // Check the cycle bit + if ( shadow_base_q.cycle ) begin + // restore the base address + shadow_base_d.base_cline = csr_base_q.base_cline; + end + end + + if ( nwait_cnt_q > 0 ) begin + nwait_cnt_d = nwait_cnt_q - 1; + end + end else begin + state_d = ABORT; + end + end + + ABORT: begin + busy_o = 1'b1; + if ( inflight_cnt_q == 0 ) begin + state_d = IDLE; + end + end + endcase + end + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv new file mode 100644 index 0000000000..1fc54967e2 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv @@ -0,0 +1,121 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Author(s) : Riccardo Alidori, Cesar Fuguet + * Creation Date : June, 2021 + * Description : Hw prefetchers arbiter + * History : + */ +module hwpf_stride_arb +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter int NUM_HW_PREFETCH = 4, + + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Dcache input interface + input logic [NUM_HW_PREFETCH-1:0] hwpf_stride_req_valid_i, + output logic [NUM_HW_PREFETCH-1:0] hwpf_stride_req_ready_o, + input hpdcache_req_t [NUM_HW_PREFETCH-1:0] hwpf_stride_req_i, + output logic [NUM_HW_PREFETCH-1:0] hwpf_stride_rsp_valid_o, + output hpdcache_rsp_t [NUM_HW_PREFETCH-1:0] hwpf_stride_rsp_o, // Not used + + // Dcache output interface + output logic hpdcache_req_valid_o, + input logic hpdcache_req_ready_i, + output hpdcache_req_t hpdcache_req_o, + input logic hpdcache_rsp_valid_i, + input hpdcache_rsp_t hpdcache_rsp_i // Not used +); +// }}} + + // Internal signals + // {{{ + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_req_valid; + hpdcache_req_t [NUM_HW_PREFETCH-1:0] hwpf_stride_req; + logic [NUM_HW_PREFETCH-1:0] arb_req_gnt; + // }}} + + // Requesters arbiter + // {{{ + // Pack request ports + genvar gen_i; + generate + for (gen_i = 0; gen_i < NUM_HW_PREFETCH; gen_i++) begin : gen_hwpf_stride_req + assign hwpf_stride_req_ready_o[gen_i] = arb_req_gnt[gen_i] & hpdcache_req_ready_i, + hwpf_stride_req_valid[gen_i] = hwpf_stride_req_valid_i[gen_i], + hwpf_stride_req[gen_i] = hwpf_stride_req_i[gen_i]; + end + endgenerate + + // Arbiter + hpdcache_rrarb #( + .N (NUM_HW_PREFETCH) + ) hwpf_stride_req_arbiter_i ( + .clk_i, + .rst_ni, + .req_i (hwpf_stride_req_valid), + .gnt_o (arb_req_gnt), + .ready_i (hpdcache_req_ready_i) + ); + + // Request Multiplexor + hpdcache_mux #( + .NINPUT (NUM_HW_PREFETCH), + .DATA_WIDTH ($bits(hpdcache_req_t)), + .ONE_HOT_SEL (1'b1) + ) hwpf_stride_req_mux_i ( + .data_i (hwpf_stride_req), + .sel_i (arb_req_gnt), + .data_o (hpdcache_req_o) + ); + + assign hpdcache_req_valid_o = |arb_req_gnt; + // }}} + + // Response demultiplexor + // {{{ + // As the HW prefetcher does not need the TID field in the request, we + // use it to transport the identifier of the specific hardware + // prefetcher. + // This way we share the same SID for all HW prefetchers. Using + // different SIDs means that we need different ports to the cache and + // we actually want to reduce those. + always_comb + begin : resp_demux + for (int unsigned i = 0; i < NUM_HW_PREFETCH; i++) begin + hwpf_stride_rsp_valid_o[i] = hpdcache_rsp_valid_i && + (i == hpdcache_uint32'(hpdcache_rsp_i.tid)); + hwpf_stride_rsp_o[i] = hpdcache_rsp_i; + end + end + // }}} +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv new file mode 100644 index 0000000000..3470b78620 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv @@ -0,0 +1,68 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : January, 2023 + * Description : High-Performance, Data-cache (HPDcache) HW memory + * prefetcher package + * History : + */ +package hwpf_stride_pkg; + // Base address configuration register of the hardware memory prefetcher + // {{{ + typedef struct packed { + logic [63:6] base_cline; + logic [5:3] unused; + logic cycle; + logic rearm; + logic enable; + } hwpf_stride_base_t; + // }}} + + // Parameters configuration register of the hardware memory prefetcher + // {{{ + typedef struct packed { + logic [63:48] nblocks; + logic [47:32] nlines; + logic [31:0] stride; + } hwpf_stride_param_t; + // }}} + + // Throttle configuration register of the hardware memory prefetcher + // {{{ + typedef struct packed { + logic [31:16] ninflight; + logic [15:0] nwait; + } hwpf_stride_throttle_t; + // }}} + + // Status register of the hardware memory prefetcher + // {{{ + typedef struct packed { + logic [63:48] unused1; + logic [47:32] busy; + logic free; + logic [30:20] unused0; + logic [19:16] free_index; + logic [15:0] enabled; + } hwpf_stride_status_t; + // }}} + +endpackage diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv new file mode 100644 index 0000000000..11989f0bf5 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv @@ -0,0 +1,291 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Riccardo Alidori, Cesar Fuguet + * Creation Date : June, 2021 + * Description : Linear Hardware Memory Prefetcher wrapper. + * History : + */ +`include "hpdcache_typedef.svh" + +module hwpf_stride_wrapper +import hwpf_stride_pkg::*; +import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter hpdcache_cfg_t HPDcacheCfg = '0, + parameter int unsigned NUM_HW_PREFETCH = 4, + parameter int unsigned NUM_SNOOP_PORTS = 1, + + // Request Interface Definitions + // {{{ + parameter type hpdcache_tag_t = logic, + parameter type hpdcache_req_offset_t = logic, + parameter type hpdcache_req_data_t = logic, + parameter type hpdcache_req_be_t = logic, + parameter type hpdcache_req_sid_t = logic, + parameter type hpdcache_req_tid_t = logic, + parameter type hpdcache_req_t = logic, + parameter type hpdcache_rsp_t = logic + // }}} +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // CSR + // {{{ + input logic [NUM_HW_PREFETCH-1:0] hwpf_stride_base_set_i, + input hwpf_stride_base_t [NUM_HW_PREFETCH-1:0] hwpf_stride_base_i, + output hwpf_stride_base_t [NUM_HW_PREFETCH-1:0] hwpf_stride_base_o, + + input logic [NUM_HW_PREFETCH-1:0] hwpf_stride_param_set_i, + input hwpf_stride_param_t [NUM_HW_PREFETCH-1:0] hwpf_stride_param_i, + output hwpf_stride_param_t [NUM_HW_PREFETCH-1:0] hwpf_stride_param_o, + + input logic [NUM_HW_PREFETCH-1:0] hwpf_stride_throttle_set_i, + input hwpf_stride_throttle_t [NUM_HW_PREFETCH-1:0] hwpf_stride_throttle_i, + output hwpf_stride_throttle_t [NUM_HW_PREFETCH-1:0] hwpf_stride_throttle_o, + + output hwpf_stride_status_t hwpf_stride_status_o, + // }}} + + // Snooping + // {{{ + input logic [NUM_SNOOP_PORTS-1:0] snoop_valid_i, + input logic [NUM_SNOOP_PORTS-1:0] snoop_abort_i, + input hpdcache_req_offset_t [NUM_SNOOP_PORTS-1:0] snoop_addr_offset_i, + input hpdcache_tag_t [NUM_SNOOP_PORTS-1:0] snoop_addr_tag_i, + input logic [NUM_SNOOP_PORTS-1:0] snoop_phys_indexed_i, + // }}} + + // Dcache interface + // {{{ + input hpdcache_req_sid_t hpdcache_req_sid_i, + output logic hpdcache_req_valid_o, + input logic hpdcache_req_ready_i, + output hpdcache_req_t hpdcache_req_o, + output logic hpdcache_req_abort_o, + output hpdcache_tag_t hpdcache_req_tag_o, + output hpdcache_pma_t hpdcache_req_pma_o, + input logic hpdcache_rsp_valid_i, + input hpdcache_rsp_t hpdcache_rsp_i + // }}} +); +// }}} + + // Internal registers + // {{{ + typedef logic [HPDcacheCfg.nlineWidth-1:0] hpdcache_nline_t; + typedef logic [HPDcacheCfg.setWidth-1:0] hpdcache_set_t; + // }}} + + // Internal registers + // {{{ + logic [NUM_SNOOP_PORTS-1:0] snoop_valid_q; + hpdcache_req_offset_t [NUM_SNOOP_PORTS-1:0] snoop_addr_offset_q; + // }}} + + // Internal signals + // {{{ + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_enable; + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_free; + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_status_busy; + logic [3:0] hwpf_stride_status_free_idx; + + hpdcache_nline_t [NUM_HW_PREFETCH-1:0] hwpf_snoop_nline; + logic [NUM_HW_PREFETCH-1:0] hwpf_snoop_match; + + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_req_valid; + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_req_ready; + hpdcache_req_t [NUM_HW_PREFETCH-1:0] hwpf_stride_req; + + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_arb_in_req_valid; + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_arb_in_req_ready; + hpdcache_req_t [NUM_HW_PREFETCH-1:0] hwpf_stride_arb_in_req; + logic [NUM_HW_PREFETCH-1:0] hwpf_stride_arb_in_rsp_valid; + hpdcache_rsp_t [NUM_HW_PREFETCH-1:0] hwpf_stride_arb_in_rsp; + // }}} + + // Assertions + // {{{ + // pragma translate_off + initial + begin : initial_assertions + max_hwpf_stride_assert: assert (NUM_HW_PREFETCH <= 16) else + $error("hwpf_stride: maximum number of HW prefetchers is 16"); + end + // pragma translate_on + // }}} + + // Compute the status information + // {{{ + always_comb begin: hwpf_stride_priority_encoder + hwpf_stride_status_free_idx = '0; + for (int unsigned i = 0; i < NUM_HW_PREFETCH; i++) begin + if (hwpf_stride_free[i]) begin + hwpf_stride_status_free_idx = i; + break; + end + end + end + + // Free flag of engines + assign hwpf_stride_free = ~(hwpf_stride_enable | hwpf_stride_status_busy); + // Busy flags + assign hwpf_stride_status_o[63:32] = {{32-NUM_HW_PREFETCH{1'b0}}, hwpf_stride_status_busy}; + // Global free flag + assign hwpf_stride_status_o[31] = |hwpf_stride_free; + // Free Index + assign hwpf_stride_status_o[30:16] = {11'b0, hwpf_stride_status_free_idx}; + // Enable flags + assign hwpf_stride_status_o[15:0] = {{16-NUM_HW_PREFETCH{1'b0}}, hwpf_stride_enable}; + // }}} + + // Hardware prefetcher engines + // {{{ + for (genvar j = 0; j < NUM_SNOOP_PORTS; j++) begin : gen_hwpf_snoop + always_ff @(posedge clk_i or negedge rst_ni) + begin : snoop_ff + if (!rst_ni) begin + snoop_valid_q[j] <= 1'b0; + snoop_addr_offset_q[j] <= '0; + end else begin + if (snoop_phys_indexed_i[j]) begin + snoop_valid_q[j] <= snoop_valid_i[j]; + snoop_addr_offset_q[j] <= snoop_addr_offset_i[j]; + end + end + end + end + + for (genvar i = 0; i < NUM_HW_PREFETCH; i++) begin : gen_hwpf_stride + assign hwpf_stride_enable[i] = hwpf_stride_base_o[i].enable; + + // Compute snoop match signals + // {{{ + always_comb + begin : snoop_comb + hwpf_snoop_match[i] = 1'b0; + for (int j = 0; j < NUM_SNOOP_PORTS; j++) begin + automatic logic snoop_valid; + automatic hpdcache_req_offset_t snoop_offset; + automatic hpdcache_nline_t snoop_nline; + + if (snoop_phys_indexed_i[j]) begin + snoop_valid = snoop_valid_i[j]; + snoop_offset = snoop_addr_offset_i[j]; + end else begin + snoop_valid = snoop_valid_q[j]; + snoop_offset = snoop_addr_offset_q[j]; + end + snoop_nline = {snoop_addr_tag_i[j], snoop_offset}; + hwpf_snoop_match[i] |= (snoop_valid && !snoop_abort_i[j] && + (hwpf_snoop_nline[i] == snoop_nline)); + end + end + // }}} + + hwpf_stride #( + .HPDcacheCfg (HPDcacheCfg), + .hpdcache_nline_t (hpdcache_nline_t), + .hpdcache_tag_t (hpdcache_tag_t), + .hpdcache_set_t (hpdcache_set_t), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t) + ) hwpf_stride_i( + .clk_i, + .rst_ni, + + .csr_base_set_i (hwpf_stride_base_set_i[i]), + .csr_base_i (hwpf_stride_base_i[i]), + .csr_param_set_i (hwpf_stride_param_set_i[i]), + .csr_param_i (hwpf_stride_param_i[i]), + .csr_throttle_set_i (hwpf_stride_throttle_set_i[i]), + .csr_throttle_i (hwpf_stride_throttle_i[i]), + + .csr_base_o (hwpf_stride_base_o[i]), + .csr_param_o (hwpf_stride_param_o[i]), + .csr_throttle_o (hwpf_stride_throttle_o[i]), + + .busy_o (hwpf_stride_status_busy[i]), + + .snoop_nline_o (hwpf_snoop_nline[i]), + .snoop_match_i (hwpf_snoop_match[i]), + + .hpdcache_req_valid_o (hwpf_stride_req_valid[i]), + .hpdcache_req_ready_i (hwpf_stride_req_ready[i]), + .hpdcache_req_o (hwpf_stride_req[i]), + .hpdcache_rsp_valid_i (hwpf_stride_arb_in_rsp_valid[i]), + .hpdcache_rsp_i (hwpf_stride_arb_in_rsp[i]) + ); + + assign hwpf_stride_req_ready[i] = hwpf_stride_arb_in_req_ready[i], + hwpf_stride_arb_in_req_valid[i] = hwpf_stride_req_valid[i], + hwpf_stride_arb_in_req[i].addr_offset = hwpf_stride_req[i].addr_offset, + hwpf_stride_arb_in_req[i].wdata = hwpf_stride_req[i].wdata, + hwpf_stride_arb_in_req[i].op = hwpf_stride_req[i].op, + hwpf_stride_arb_in_req[i].be = hwpf_stride_req[i].be, + hwpf_stride_arb_in_req[i].size = hwpf_stride_req[i].size, + hwpf_stride_arb_in_req[i].sid = hpdcache_req_sid_i, + hwpf_stride_arb_in_req[i].tid = hpdcache_req_tid_t'(i), + hwpf_stride_arb_in_req[i].need_rsp = hwpf_stride_req[i].need_rsp, + hwpf_stride_arb_in_req[i].phys_indexed = hwpf_stride_req[i].phys_indexed, + hwpf_stride_arb_in_req[i].addr_tag = '0, + hwpf_stride_arb_in_req[i].pma = '0; + end + // }}} + + // Hardware prefetcher arbiter betweem engines + // {{{ + hwpf_stride_arb #( + .NUM_HW_PREFETCH (NUM_HW_PREFETCH), + .hpdcache_req_t (hpdcache_req_t), + .hpdcache_rsp_t (hpdcache_rsp_t) + ) hwpf_stride_arb_i ( + .clk_i, + .rst_ni, + + // DCache input interface + .hwpf_stride_req_valid_i (hwpf_stride_arb_in_req_valid), + .hwpf_stride_req_ready_o (hwpf_stride_arb_in_req_ready), + .hwpf_stride_req_i (hwpf_stride_arb_in_req), + .hwpf_stride_rsp_valid_o (hwpf_stride_arb_in_rsp_valid), + .hwpf_stride_rsp_o (hwpf_stride_arb_in_rsp), + + // DCache output interface + .hpdcache_req_valid_o, + .hpdcache_req_ready_i, + .hpdcache_req_o, + .hpdcache_rsp_valid_i, + .hpdcache_rsp_i + ); + + assign hpdcache_req_abort_o = 1'b0, // unused on physically indexed requests + hpdcache_req_tag_o = '0, // unused on physically indexed requests + hpdcache_req_pma_o = '0; // unused on physically indexed requests + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv new file mode 100644 index 0000000000..73e3f81a64 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv @@ -0,0 +1,89 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Dcache Memory Read Request Channel Arbiter + * History : + */ +module hpdcache_mem_req_read_arbiter +// Parameters +// {{{ +#( + parameter int unsigned N = 0, + parameter type hpdcache_mem_req_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + output logic [N-1:0] mem_req_read_ready_o, + input logic [N-1:0] mem_req_read_valid_i, + input hpdcache_mem_req_t [N-1:0] mem_req_read_i, + + input logic mem_req_read_ready_i, + output logic mem_req_read_valid_o, + output hpdcache_mem_req_t mem_req_read_o +); +// }}} + + logic [N-1:0] mem_read_arb_req_gnt; + + logic req_valid; + + genvar gen_i; + + assign req_valid = |(mem_read_arb_req_gnt & mem_req_read_valid_i); + + // Fixed-priority arbiter + hpdcache_fxarb #( + .N (N) + ) hpdcache_fxarb_mem_req_write_i ( + .clk_i, + .rst_ni, + .req_i (mem_req_read_valid_i), + .gnt_o (mem_read_arb_req_gnt), + .ready_i (mem_req_read_ready_i) + ); + + // Demultiplexor for the ready signal + for (gen_i = 0; gen_i < int'(N); gen_i++) begin : gen_req_ready + assign mem_req_read_ready_o[gen_i] = mem_req_read_ready_i & mem_read_arb_req_gnt[gen_i] & + mem_req_read_valid_i[gen_i]; + end + + assign mem_req_read_valid_o = req_valid; + + // Multiplexor for requests + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH ($bits(hpdcache_mem_req_t)), + .ONE_HOT_SEL (1'b1) + ) mem_read_req_mux_i ( + .data_i (mem_req_read_i), + .sel_i (mem_read_arb_req_gnt), + .data_o (mem_req_read_o) + ); + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv new file mode 100644 index 0000000000..2680742565 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv @@ -0,0 +1,190 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Dcache Memory Write Channels Arbiter + * History : + */ +module hpdcache_mem_req_write_arbiter +// Parameters +// {{{ +#( + parameter int unsigned N = 0, + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic +) +// }}} +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + output logic [N-1:0] mem_req_write_ready_o, + input logic [N-1:0] mem_req_write_valid_i, + input hpdcache_mem_req_t [N-1:0] mem_req_write_i, + + output logic [N-1:0] mem_req_write_data_ready_o, + input logic [N-1:0] mem_req_write_data_valid_i, + input hpdcache_mem_req_w_t [N-1:0] mem_req_write_data_i, + + input logic mem_req_write_ready_i, + output logic mem_req_write_valid_o, + output hpdcache_mem_req_t mem_req_write_o, + + input logic mem_req_write_data_ready_i, + output logic mem_req_write_data_valid_o, + output hpdcache_mem_req_w_t mem_req_write_data_o +); +// }}} + + // Types and wires + // {{{ + typedef logic [N-1:0] arb_gnt_t; + + logic req_valid, req_data_valid, req_data_last; + + arb_gnt_t mem_write_arb_req_data_last; + arb_gnt_t mem_write_arb_req_gnt, mem_write_arb_req_gnt_q; + + logic mem_write_arb_req_r, mem_write_arb_req_w; + logic mem_write_arb_req_rok, mem_write_arb_req_wok; + logic mem_write_arb_req_ready; + + logic mem_req_write_w; + logic mem_req_write_wok; + hpdcache_mem_req_t mem_req_write; + + genvar gen_i; + // }}} + + // Combinational logic + // {{{ + for (gen_i = 0; gen_i < int'(N); gen_i++) begin : gen_bitvectors + assign mem_write_arb_req_data_last[gen_i] = mem_req_write_data_i[gen_i].mem_req_w_last; + + assign mem_req_write_ready_o[gen_i] = mem_write_arb_req_gnt[gen_i] & + mem_write_arb_req_ready; + + assign mem_req_write_data_ready_o[gen_i] = mem_write_arb_req_gnt_q[gen_i] & + mem_write_arb_req_rok & + mem_req_write_data_ready_i; + end + + assign req_valid = |(mem_write_arb_req_gnt & mem_req_write_valid_i); + assign req_data_valid = |(mem_write_arb_req_gnt_q & mem_req_write_data_valid_i); + assign req_data_last = |(mem_write_arb_req_gnt_q & mem_write_arb_req_data_last); + + // Accept a new request when the grant FIFO is not full and the NoC can accept the request + assign mem_write_arb_req_ready = mem_write_arb_req_wok & mem_req_write_wok; + + // Write a grant decision into the FIFO + assign mem_write_arb_req_w = req_valid & mem_req_write_wok; + + // Read grant FIFO when the NoC is able to receive the data and it is the last flit of data + assign mem_write_arb_req_r = mem_req_write_data_ready_i & + mem_write_arb_req_rok & + req_data_valid & + req_data_last; + + // Accept a new request when the grant FIFO is not full and the NoC can accept the request + assign mem_req_write_w = req_valid & mem_write_arb_req_wok; + + // Forward the data to the NoC if there is any and there is a grant decision in the FIFO + assign mem_req_write_data_valid_o = req_data_valid & mem_write_arb_req_rok; + // }}} + + // Fixed-priority arbiter + // {{{ + hpdcache_fxarb #( + .N (N) + ) hpdcache_fxarb_mem_req_write_i( + .clk_i, + .rst_ni, + .req_i (mem_req_write_valid_i), + .gnt_o (mem_write_arb_req_gnt), + .ready_i (mem_write_arb_req_ready) + ); + // }}} + + // Request FIFO + // {{{ + hpdcache_fifo_reg #( + .FIFO_DEPTH (1), + .FEEDTHROUGH (1'b1), + .fifo_data_t (hpdcache_mem_req_t) + ) req_fifo_i( + .clk_i, + .rst_ni, + .w_i (mem_req_write_w), + .wok_o (mem_req_write_wok), + .wdata_i (mem_req_write), + .r_i (mem_req_write_ready_i), + .rok_o (mem_req_write_valid_o), + .rdata_o (mem_req_write_o) + ); + // }}} + + // Grant signal FIFO + // {{{ + hpdcache_fifo_reg #( + .FIFO_DEPTH (2), + .FEEDTHROUGH (1'b1), + .fifo_data_t (arb_gnt_t) + ) req_gnt_fifo_i( + .clk_i, + .rst_ni, + .w_i (mem_write_arb_req_w), + .wok_o (mem_write_arb_req_wok), + .wdata_i (mem_write_arb_req_gnt), + .r_i (mem_write_arb_req_r), + .rok_o (mem_write_arb_req_rok), + .rdata_o (mem_write_arb_req_gnt_q) + ); + // }}} + + // Mux requests + // {{{ + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH ($bits(hpdcache_mem_req_t)), + .ONE_HOT_SEL (1'b1) + ) req_mux_i( + .data_i (mem_req_write_i), + .sel_i (mem_write_arb_req_gnt), + .data_o (mem_req_write) + ); + // }}} + + // Mux data + // {{{ + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH ($bits(hpdcache_mem_req_w_t)), + .ONE_HOT_SEL (1'b1) + ) data_mux_i( + .data_i (mem_req_write_data_i), + .sel_i (mem_write_arb_req_gnt_q), + .data_o (mem_req_write_data_o) + ); + // }}} + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv new file mode 100644 index 0000000000..c1502a985b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv @@ -0,0 +1,108 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : June, 2022 + * Description : Dcache Memory Reponse Demultiplexer + * History : + */ +module hpdcache_mem_resp_demux +// Parameters +// {{{ +#( + parameter int N = 0, + parameter type resp_t = logic, + parameter type resp_id_t = logic, + + localparam int RT_DEPTH = (1 << $bits(resp_id_t)), + localparam type rt_t = resp_id_t [RT_DEPTH-1:0] +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + output logic mem_resp_ready_o, + input logic mem_resp_valid_i, + input resp_id_t mem_resp_id_i, + input resp_t mem_resp_i, + + input logic mem_resp_ready_i [N-1:0], + output logic mem_resp_valid_o [N-1:0], + output resp_t mem_resp_o [N-1:0], + + input rt_t mem_resp_rt_i +); +// }}} + + typedef logic [$clog2(N)-1:0] sel_t; + + logic [N-1:0] mem_resp_demux_valid; + resp_t [N-1:0] mem_resp_demux; + logic [N-1:0] mem_resp_demux_ready; + sel_t mem_resp_demux_sel; + + // Route the response according to the response ID and the routing table + assign mem_resp_demux_sel = mem_resp_rt_i[int'(mem_resp_id_i)]; + + // Forward the response to the corresponding output port + hpdcache_demux #( + .NOUTPUT (N), + .DATA_WIDTH (1), + .ONE_HOT_SEL (0) + ) i_resp_valid_demux ( + .data_i (mem_resp_valid_i), + .sel_i (mem_resp_demux_sel), + .data_o (mem_resp_demux_valid) + ); + + hpdcache_demux #( + .NOUTPUT (N), + .DATA_WIDTH ($bits(resp_t)), + .ONE_HOT_SEL (0) + ) i_resp_demux ( + .data_i (mem_resp_i), + .sel_i (mem_resp_demux_sel), + .data_o (mem_resp_demux) + ); + + hpdcache_mux #( + .NINPUT (N), + .DATA_WIDTH (1), + .ONE_HOT_SEL (0) + ) i_resp_ready_mux ( + .data_i (mem_resp_demux_ready), + .sel_i (mem_resp_demux_sel), + .data_o (mem_resp_ready_o) + ); + + // Pack/unpack responses + generate + for (genvar gen_i = 0; gen_i < int'(N); gen_i++) begin : pack_unpack_resp_gen + assign mem_resp_valid_o [gen_i] = mem_resp_demux_valid [gen_i]; + assign mem_resp_o [gen_i] = mem_resp_demux [gen_i]; + assign mem_resp_demux_ready [gen_i] = mem_resp_ready_i [gen_i]; + end + endgenerate + +endmodule : hpdcache_mem_resp_demux diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv new file mode 100644 index 0000000000..ccbe49c993 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv @@ -0,0 +1,95 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Dcache memory request to axi read channels + * History : + */ +module hpdcache_mem_to_axi_read +import hpdcache_pkg::*; +#( + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic +) +( + output logic req_ready_o, + input logic req_valid_i, + input hpdcache_mem_req_t req_i, + + input logic resp_ready_i, + output logic resp_valid_o, + output hpdcache_mem_resp_r_t resp_o, + + output logic axi_ar_valid_o, + output ar_chan_t axi_ar_o, + input logic axi_ar_ready_i, + + input logic axi_r_valid_i, + input r_chan_t axi_r_i, + output logic axi_r_ready_o +); + + logic lock; + axi_pkg::cache_t cache; + hpdcache_mem_error_e resp; + + assign lock = (req_i.mem_req_command == HPDCACHE_MEM_ATOMIC) && + (req_i.mem_req_atomic == HPDCACHE_MEM_ATOMIC_LDEX); + + assign cache = req_i.mem_req_cacheable ? + axi_pkg::CACHE_BUFFERABLE | + axi_pkg::CACHE_MODIFIABLE | + axi_pkg::CACHE_RD_ALLOC | + axi_pkg::CACHE_WR_ALLOC : axi_pkg::CACHE_MODIFIABLE; + + always_comb + begin : resp_decode_comb + case (axi_r_i.resp) + axi_pkg::RESP_SLVERR, + axi_pkg::RESP_DECERR: resp = HPDCACHE_MEM_RESP_NOK; + default: resp = HPDCACHE_MEM_RESP_OK; + endcase + end + + assign req_ready_o = axi_ar_ready_i, + axi_ar_valid_o = req_valid_i, + axi_ar_o.id = req_i.mem_req_id, + axi_ar_o.addr = req_i.mem_req_addr, + axi_ar_o.len = req_i.mem_req_len, + axi_ar_o.size = req_i.mem_req_size, + axi_ar_o.burst = axi_pkg::BURST_INCR, + axi_ar_o.lock = lock, + axi_ar_o.cache = cache, + axi_ar_o.prot = '0, + axi_ar_o.qos = '0, + axi_ar_o.region = '0, + axi_ar_o.user = '0; + + assign axi_r_ready_o = resp_ready_i, + resp_valid_o = axi_r_valid_i, + resp_o.mem_resp_r_error = resp, + resp_o.mem_resp_r_id = axi_r_i.id, + resp_o.mem_resp_r_data = axi_r_i.data, + resp_o.mem_resp_r_last = axi_r_i.last; + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv new file mode 100644 index 0000000000..098bff4e3b --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv @@ -0,0 +1,148 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Cesar Fuguet + * Creation Date : April, 2021 + * Description : Dcache memory request to axi write channels + * History : + */ +module hpdcache_mem_to_axi_write +import hpdcache_pkg::*; +#( + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_w_t = logic, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic +) +( + output logic req_ready_o, + input logic req_valid_i, + input hpdcache_mem_req_t req_i, + + output logic req_data_ready_o, + input logic req_data_valid_i, + input hpdcache_mem_req_w_t req_data_i, + + input logic resp_ready_i, + output logic resp_valid_o, + output hpdcache_mem_resp_w_t resp_o, + + output logic axi_aw_valid_o, + output aw_chan_t axi_aw_o, + input logic axi_aw_ready_i, + + output logic axi_w_valid_o, + output w_chan_t axi_w_o, + input logic axi_w_ready_i, + + input logic axi_b_valid_i, + input b_chan_t axi_b_i, + output logic axi_b_ready_o +); + + logic lock; + axi_pkg::atop_t atop; + axi_pkg::cache_t cache; + hpdcache_mem_error_e resp; + + always_comb + begin : atop_comb + lock = 1'b0; + atop = '0; + case (req_i.mem_req_command) + HPDCACHE_MEM_ATOMIC: begin + case (req_i.mem_req_atomic) + HPDCACHE_MEM_ATOMIC_STEX: lock = 1'b1; + HPDCACHE_MEM_ATOMIC_ADD : atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_ADD}; + HPDCACHE_MEM_ATOMIC_CLR : atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_CLR}; + HPDCACHE_MEM_ATOMIC_SET : atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_SET}; + HPDCACHE_MEM_ATOMIC_EOR : atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_EOR}; + HPDCACHE_MEM_ATOMIC_SMAX: atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_SMAX}; + HPDCACHE_MEM_ATOMIC_SMIN: atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_SMIN}; + HPDCACHE_MEM_ATOMIC_UMAX: atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_UMAX}; + HPDCACHE_MEM_ATOMIC_UMIN: atop = {axi_pkg::ATOP_ATOMICLOAD, + axi_pkg::ATOP_LITTLE_END, + axi_pkg::ATOP_UMIN}; + HPDCACHE_MEM_ATOMIC_SWAP: atop = axi_pkg::ATOP_ATOMICSWAP; + endcase + end + endcase + end + + assign cache = (req_i.mem_req_cacheable && !lock) ? + axi_pkg::CACHE_BUFFERABLE | + axi_pkg::CACHE_MODIFIABLE | + axi_pkg::CACHE_RD_ALLOC | + axi_pkg::CACHE_WR_ALLOC : axi_pkg::CACHE_MODIFIABLE; + + always_comb + begin : resp_decode_comb + case (axi_b_i.resp) + axi_pkg::RESP_SLVERR, + axi_pkg::RESP_DECERR: resp = HPDCACHE_MEM_RESP_NOK; + default: resp = HPDCACHE_MEM_RESP_OK; + endcase + end + + assign req_ready_o = axi_aw_ready_i, + axi_aw_valid_o = req_valid_i, + axi_aw_o.id = req_i.mem_req_id, + axi_aw_o.addr = req_i.mem_req_addr, + axi_aw_o.len = req_i.mem_req_len, + axi_aw_o.size = req_i.mem_req_size, + axi_aw_o.burst = axi_pkg::BURST_INCR, + axi_aw_o.lock = lock, + axi_aw_o.cache = cache, + axi_aw_o.prot = '0, + axi_aw_o.qos = '0, + axi_aw_o.region = '0, + axi_aw_o.atop = atop, + axi_aw_o.user = '0; + + assign req_data_ready_o = axi_w_ready_i, + axi_w_valid_o = req_data_valid_i, + axi_w_o.data = req_data_i.mem_req_w_data, + axi_w_o.strb = req_data_i.mem_req_w_be, + axi_w_o.last = req_data_i.mem_req_w_last, + axi_w_o.user = '0; + + assign axi_b_ready_o = resp_ready_i, + resp_valid_o = axi_b_valid_i, + resp_o.mem_resp_w_error = resp, + resp_o.mem_resp_w_id = axi_b_i.id, + resp_o.mem_resp_w_is_atomic = (axi_b_i.resp == axi_pkg::RESP_EXOKAY); + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/std_cache_subsystem.sv b/flow/designs/src/cva6/core/cache_subsystem/std_cache_subsystem.sv new file mode 100644 index 0000000000..7adb935c27 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/std_cache_subsystem.sv @@ -0,0 +1,343 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba , ETH Zurich +// Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Standard Ariane cache subsystem with instruction cache and +// write-back data cache. + + +module std_cache_subsystem + import ariane_pkg::*; + import std_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter int unsigned NumPorts = 4, + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_w_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input riscv::priv_lvl_t priv_lvl_i, + // I$ + input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) + input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together + output logic icache_miss_o, // to performance counter + // address translation requests + input icache_areq_t icache_areq_i, // to/from frontend + output icache_arsp_t icache_areq_o, + // data requests + input icache_dreq_t icache_dreq_i, // to/from frontend + output icache_drsp_t icache_dreq_o, + // AMOs + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + // D$ + // Cache management + input logic dcache_enable_i, // from CSR + input logic dcache_flush_i, // high until acknowledged + output logic dcache_flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic dcache_miss_o, // we missed on a ld/st + output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system + // Request ports + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU + // memory side + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i +); + + assign wbuffer_empty_o = 1'b1; + + axi_req_t axi_req_icache; + axi_rsp_t axi_resp_icache; + axi_req_t axi_req_bypass; + axi_rsp_t axi_resp_bypass; + axi_req_t axi_req_data; + axi_rsp_t axi_resp_data; + + cva6_icache_axi_wrapper #( + .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .axi_req_t(axi_req_t), + .axi_rsp_t(axi_rsp_t) + ) i_cva6_icache_axi_wrapper ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .priv_lvl_i(priv_lvl_i), + .flush_i (icache_flush_i), + .en_i (icache_en_i), + .miss_o (icache_miss_o), + .areq_i (icache_areq_i), + .areq_o (icache_areq_o), + .dreq_i (icache_dreq_i), + .dreq_o (icache_dreq_o), + .axi_req_o (axi_req_icache), + .axi_resp_i(axi_resp_icache) + ); + + // decreasing priority + // Port 0: PTW + // Port 1: Load Unit + // Port 2: Accelerator + // Port 3: Store Unit + std_nbdcache #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts(NumPorts), + .axi_req_t(axi_req_t), + .axi_rsp_t(axi_rsp_t) + ) i_nbdcache ( + .clk_i, + .rst_ni, + .enable_i (dcache_enable_i), + .flush_i (dcache_flush_i), + .flush_ack_o (dcache_flush_ack_o), + .miss_o (dcache_miss_o), + .axi_bypass_o(axi_req_bypass), + .axi_bypass_i(axi_resp_bypass), + .axi_data_o (axi_req_data), + .axi_data_i (axi_resp_data), + .req_ports_i (dcache_req_ports_i), + .req_ports_o (dcache_req_ports_o), + .amo_req_i, + .amo_resp_o + ); + + // ----------------------- + // Arbitrate AXI Ports + // ----------------------- + logic [1:0] w_select, w_select_fifo, w_select_arbiter; + logic [1:0] w_fifo_usage; + logic w_fifo_empty, w_fifo_full; + logic w_fifo_push, w_fifo_pop; + logic aw_lock_q, aw_lock_d; + + + // AR Channel + stream_arbiter #( + .DATA_T(axi_ar_chan_t), + .N_INP (3) + ) i_stream_arbiter_ar ( + .clk_i, + .rst_ni, + .inp_data_i ({axi_req_icache.ar, axi_req_bypass.ar, axi_req_data.ar}), + .inp_valid_i({axi_req_icache.ar_valid, axi_req_bypass.ar_valid, axi_req_data.ar_valid}), + .inp_ready_o({axi_resp_icache.ar_ready, axi_resp_bypass.ar_ready, axi_resp_data.ar_ready}), + .oup_data_o (axi_req_o.ar), + .oup_valid_o(axi_req_o.ar_valid), + .oup_ready_i(axi_resp_i.ar_ready) + ); + + // AW Channel + stream_arbiter #( + .DATA_T(axi_aw_chan_t), + .N_INP (3) + ) i_stream_arbiter_aw ( + .clk_i, + .rst_ni, + .inp_data_i ({axi_req_icache.aw, axi_req_bypass.aw, axi_req_data.aw}), + .inp_valid_i({axi_req_icache.aw_valid, axi_req_bypass.aw_valid, axi_req_data.aw_valid}), + .inp_ready_o({axi_resp_icache.aw_ready, axi_resp_bypass.aw_ready, axi_resp_data.aw_ready}), + .oup_data_o (axi_req_o.aw), + .oup_valid_o(axi_req_o.aw_valid), + .oup_ready_i(axi_resp_i.aw_ready) + ); + + // WID has been removed in AXI 4 so we need to keep track which AW request has been accepted + // to forward the correct write data. + always_comb begin + w_select = 0; + unique casez (axi_req_o.aw.id) + 4'b0111: w_select = 2; // dcache + 4'b1???: w_select = 1; // bypass + default: w_select = 0; // icache + endcase + end + + // W Channel + cva6_fifo_v3 #( + .DATA_WIDTH (2), + // we can have a maximum of 4 oustanding transactions as each port is blocking + .DEPTH (4), + .FALL_THROUGH(1'b1), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_fifo_w_channel ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (w_fifo_full), + .empty_o (), // leave open + .usage_o (w_fifo_usage), + .data_i (w_select), + // a new transaction was requested and granted + .push_i (w_fifo_push), + // write ID to select the output MUX + .data_o (w_select_fifo), + // transaction has finished + .pop_i (w_fifo_pop) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin : aw_lock_reg + if (~rst_ni) aw_lock_q <= 1'b0; + else aw_lock_q <= aw_lock_d; + end + + assign w_fifo_push = ~aw_lock_q & axi_req_o.aw_valid; + assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last; + assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q); + + // In fall-through mode, the empty_o will be low when push_i is high (on zero usage). + // We do not want this here. Also, usage_o is missing the MSB, so on full fifo, usage_o is zero. + assign w_fifo_empty = w_fifo_usage == 0 && !w_fifo_full; + + // icache will never write so select it as default (e.g.: when no arbitration is active) + // this is equal to setting it to zero + assign w_select_arbiter = w_fifo_empty ? (axi_req_o.aw_valid ? w_select : 0) : w_select_fifo; + + stream_mux #( + .DATA_T(axi_w_chan_t), + .N_INP (3) + ) i_stream_mux_w ( + .inp_data_i ({axi_req_data.w, axi_req_bypass.w, axi_req_icache.w}), + .inp_valid_i({axi_req_data.w_valid, axi_req_bypass.w_valid, axi_req_icache.w_valid}), + .inp_ready_o({axi_resp_data.w_ready, axi_resp_bypass.w_ready, axi_resp_icache.w_ready}), + .inp_sel_i (w_select_arbiter), + .oup_data_o (axi_req_o.w), + .oup_valid_o(axi_req_o.w_valid), + .oup_ready_i(axi_resp_i.w_ready) + ); + + // Route responses based on ID + // 0000 -> I$ + // 0111 -> D$ + // 1??? -> Bypass + // R Channel + assign axi_resp_icache.r = axi_resp_i.r; + assign axi_resp_bypass.r = axi_resp_i.r; + assign axi_resp_data.r = axi_resp_i.r; + + logic [1:0] r_select; + + always_comb begin + r_select = 0; + unique casez (axi_resp_i.r.id) + 4'b0111: r_select = 0; // dcache + 4'b1???: r_select = 1; // bypass + 4'b0000: r_select = 2; // icache + default: r_select = 0; + endcase + end + + stream_demux #( + .N_OUP(3) + ) i_stream_demux_r ( + .inp_valid_i(axi_resp_i.r_valid), + .inp_ready_o(axi_req_o.r_ready), + .oup_sel_i (r_select), + .oup_valid_o({axi_resp_icache.r_valid, axi_resp_bypass.r_valid, axi_resp_data.r_valid}), + .oup_ready_i({axi_req_icache.r_ready, axi_req_bypass.r_ready, axi_req_data.r_ready}) + ); + + // B Channel + logic [1:0] b_select; + + assign axi_resp_icache.b = axi_resp_i.b; + assign axi_resp_bypass.b = axi_resp_i.b; + assign axi_resp_data.b = axi_resp_i.b; + + always_comb begin + b_select = 0; + unique casez (axi_resp_i.b.id) + 4'b0111: b_select = 0; // dcache + 4'b1???: b_select = 1; // bypass + 4'b0000: b_select = 2; // icache + default: b_select = 0; + endcase + end + + stream_demux #( + .N_OUP(3) + ) i_stream_demux_b ( + .inp_valid_i(axi_resp_i.b_valid), + .inp_ready_o(axi_req_o.b_ready), + .oup_sel_i (b_select), + .oup_valid_o({axi_resp_icache.b_valid, axi_resp_bypass.b_valid, axi_resp_data.b_valid}), + .oup_ready_i({axi_req_icache.b_ready, axi_req_bypass.b_ready, axi_req_data.b_ready}) + ); + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + + a_invalid_instruction_fetch : + assert property ( + @(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X", + icache_dreq_o.vaddr, + icache_dreq_o.data + ); + + a_invalid_write_data : + assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> |dcache_req_ports_i[NumPorts-1].data_be |-> (|dcache_req_ports_i[NumPorts-1].data_wdata) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X", + { + dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index + }, + dcache_req_ports_i[NumPorts-1].data_be, + dcache_req_ports_i[NumPorts-1].data_wdata + ); + generate + for (genvar j = 0; j < NumPorts - 1; j++) begin + a_invalid_read_data : + assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid data on port %01d: data=%016X", + j, + dcache_req_ports_o[j].data_rdata + ); + end + endgenerate + +`endif + //pragma translate_on +endmodule // std_cache_subsystem diff --git a/flow/designs/src/cva6/core/cache_subsystem/std_nbdcache.sv b/flow/designs/src/cva6/core/cache_subsystem/std_nbdcache.sv new file mode 100644 index 0000000000..d068e743b2 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/std_nbdcache.sv @@ -0,0 +1,302 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 13.10.2017 +// Description: Nonblocking private L1 dcache + + +module std_nbdcache + import std_cache_pkg::*; + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter int unsigned NumPorts = 4, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a LD/ST + // AMOs + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + // Request ports + input dcache_req_i_t [NumPorts-1:0] req_ports_i, // request ports + output dcache_req_o_t [NumPorts-1:0] req_ports_o, // request ports + // Cache AXI refill port + output axi_req_t axi_data_o, + input axi_rsp_t axi_data_i, + output axi_req_t axi_bypass_o, + input axi_rsp_t axi_bypass_i +); + + import std_cache_pkg::*; + + localparam DCACHE_DIRTY_WIDTH = CVA6Cfg.DCACHE_SET_ASSOC * 2; + + localparam type cache_line_t = struct packed { + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag; // tag array + logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] data; // data array + logic valid; // state array + logic dirty; // state array + }; + localparam type cl_be_t = struct packed { + logic [(CVA6Cfg.DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array + logic [(CVA6Cfg.DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits) + }; + + // ------------------------------- + // Controller <-> Arbiter + // ------------------------------- + // 1. Miss handler + // 2. PTW + // 3. Load Unit + // 4. Accelerator + // 5. Store unit + logic [ NumPorts:0][ CVA6Cfg.DCACHE_SET_ASSOC-1:0] req; + logic [ NumPorts:0][CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] addr; + logic [ NumPorts:0] gnt; + cache_line_t [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rdata; + logic [ NumPorts:0][ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag; + + cache_line_t [ NumPorts:0] wdata; + logic [ NumPorts:0] we; + cl_be_t [ NumPorts:0] be; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way; + // ------------------------------- + // Controller <-> Miss unit + // ------------------------------- + logic [ NumPorts-1:0] busy; + logic [ NumPorts-1:0][ 55:0] mshr_addr; + logic [ NumPorts-1:0] mshr_addr_matches; + logic [ NumPorts-1:0] mshr_index_matches; + logic [ 63:0] critical_word; + logic critical_word_valid; + + logic [ NumPorts-1:0][ $bits(miss_req_t)-1:0] miss_req; + logic [ NumPorts-1:0] miss_gnt; + logic [ NumPorts-1:0] active_serving; + + logic [ NumPorts-1:0] bypass_gnt; + logic [ NumPorts-1:0] bypass_valid; + logic [ NumPorts-1:0][ 63:0] bypass_data; + // ------------------------------- + // Arbiter <-> Datram, + // ------------------------------- + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] req_ram; + logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] addr_ram; + logic we_ram; + cache_line_t wdata_ram; + cache_line_t [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rdata_ram; + cl_be_t be_ram; + + // ------------------ + // Cache Controller + // ------------------ + generate + for (genvar i = 0; i < NumPorts; i++) begin : master_ports + cache_ctrl #( + .CVA6Cfg(CVA6Cfg), + .cache_line_t(cache_line_t), + .cl_be_t(cl_be_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t) + ) i_cache_ctrl ( + .bypass_i (~enable_i), + .busy_o (busy[i]), + // from core + .req_port_i(req_ports_i[i]), + .req_port_o(req_ports_o[i]), + // to SRAM array + .req_o (req[i+1]), + .addr_o (addr[i+1]), + .gnt_i (gnt[i+1]), + .data_i (rdata), + .tag_o (tag[i+1]), + .data_o (wdata[i+1]), + .we_o (we[i+1]), + .be_o (be[i+1]), + .hit_way_i (hit_way), + + .miss_req_o (miss_req[i]), + .miss_gnt_i (miss_gnt[i]), + .active_serving_i (active_serving[i]), + .critical_word_i (critical_word), + .critical_word_valid_i(critical_word_valid), + .bypass_gnt_i (bypass_gnt[i]), + .bypass_valid_i (bypass_valid[i]), + .bypass_data_i (bypass_data[i]), + + .mshr_addr_o (mshr_addr[i]), + .mshr_addr_matches_i (mshr_addr_matches[i]), + .mshr_index_matches_i(mshr_index_matches[i]), + .* + ); + end + endgenerate + + // ------------------ + // Miss Handling Unit + // ------------------ + miss_handler #( + .CVA6Cfg(CVA6Cfg), + .NR_PORTS(NumPorts), + .axi_req_t(axi_req_t), + .axi_rsp_t(axi_rsp_t), + .cache_line_t(cache_line_t), + .cl_be_t(cl_be_t) + ) i_miss_handler ( + .flush_i (flush_i), + .busy_i (|busy), + // AMOs + .amo_req_i (amo_req_i), + .amo_resp_o (amo_resp_o), + .miss_req_i (miss_req), + .miss_gnt_o (miss_gnt), + .bypass_gnt_o (bypass_gnt), + .bypass_valid_o (bypass_valid), + .bypass_data_o (bypass_data), + .critical_word_o (critical_word), + .critical_word_valid_o(critical_word_valid), + .mshr_addr_i (mshr_addr), + .mshr_addr_matches_o (mshr_addr_matches), + .mshr_index_matches_o (mshr_index_matches), + .active_serving_o (active_serving), + .req_o (req[0]), + .addr_o (addr[0]), + .data_i (rdata), + .be_o (be[0]), + .data_o (wdata[0]), + .we_o (we[0]), + .axi_bypass_o, + .axi_bypass_i, + .axi_data_o, + .axi_data_i, + .* + ); + + assign tag[0] = '0; + + // -------------- + // Memory Arrays + // -------------- + for (genvar i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin : sram_block + sram #( + .DATA_WIDTH(CVA6Cfg.DCACHE_LINE_WIDTH), + .NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS) + ) data_sram ( + .req_i (req_ram[i]), + .rst_ni (rst_ni), + .we_i (we_ram), + .addr_i (addr_ram[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]), + .wuser_i('0), + .wdata_i(wdata_ram.data), + .be_i (be_ram.data), + .ruser_o(), + .rdata_o(rdata_ram[i].data), + .* + ); + + sram #( + .DATA_WIDTH(CVA6Cfg.DCACHE_TAG_WIDTH), + .NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS) + ) tag_sram ( + .req_i (req_ram[i]), + .rst_ni (rst_ni), + .we_i (we_ram), + .addr_i (addr_ram[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]), + .wuser_i('0), + .wdata_i(wdata_ram.tag), + .be_i (be_ram.tag), + .ruser_o(), + .rdata_o(rdata_ram[i].tag), + .* + ); + + end + + // ---------------- + // Valid/Dirty Regs + // ---------------- + + // align each valid/dirty bit pair to a byte boundary in order to leverage byte enable signals. + // note: if you have an SRAM that supports flat bit enables for your target technology, + // you can use it here to save the extra 4x overhead introduced by this workaround. + logic [4*DCACHE_DIRTY_WIDTH-1:0] dirty_wdata, dirty_rdata; + + for (genvar i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin + assign dirty_wdata[8*i] = wdata_ram.dirty; + assign dirty_wdata[8*i+1] = wdata_ram.valid; + assign rdata_ram[i].dirty = dirty_rdata[8*i]; + assign rdata_ram[i].valid = dirty_rdata[8*i+1]; + end + + sram #( + .USER_WIDTH(1), + .DATA_WIDTH(4 * DCACHE_DIRTY_WIDTH), + .NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS) + ) valid_dirty_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (|req_ram), + .we_i (we_ram), + .addr_i (addr_ram[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]), + .wuser_i('0), + .wdata_i(dirty_wdata), + .be_i (be_ram.vldrty), + .ruser_o(), + .rdata_o(dirty_rdata) + ); + + // ------------------------------------------------ + // Tag Comparison and memory arbitration + // ------------------------------------------------ + tag_cmp #( + .CVA6Cfg (CVA6Cfg), + .NR_PORTS (NumPorts + 1), + .ADDR_WIDTH(CVA6Cfg.DCACHE_INDEX_WIDTH), + .l_data_t (cache_line_t), + .l_be_t (cl_be_t) + ) i_tag_cmp ( + .req_i (req), + .gnt_o (gnt), + .addr_i (addr), + .wdata_i (wdata), + .we_i (we), + .be_i (be), + .rdata_o (rdata), + .tag_i (tag), + .hit_way_o(hit_way), + + .req_o (req_ram), + .addr_o (addr_ram), + .wdata_o(wdata_ram), + .we_o (we_ram), + .be_o (be_ram), + .rdata_i(rdata_ram), + .* + ); + + + //pragma translate_off + initial begin + assert (CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth inside {2, 4, 8, 16}) + else $fatal(1, "Cache line size needs to be a power of two multiple of AxiDataWidth"); + end + //pragma translate_on +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/tag_cmp.sv b/flow/designs/src/cva6/core/cache_subsystem/tag_cmp.sv new file mode 100644 index 0000000000..38d1ce1145 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/tag_cmp.sv @@ -0,0 +1,106 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// Author: Florian Zaruba +// -------------- +// Tag Compare +// -------------- +// +// Description: Arbitrates access to cache memories, simplified request grant protocol +// checks for hit or miss on cache +// +module tag_cmp #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned NR_PORTS = 3, + parameter int unsigned ADDR_WIDTH = 64, + parameter type l_data_t = logic, + parameter type l_be_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + input logic [NR_PORTS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] req_i, + output logic [NR_PORTS-1:0] gnt_o, + input logic [NR_PORTS-1:0][ADDR_WIDTH-1:0] addr_i, + input l_data_t [NR_PORTS-1:0] wdata_i, + input logic [NR_PORTS-1:0] we_i, + input l_be_t [NR_PORTS-1:0] be_i, + output l_data_t [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rdata_o, + input logic [NR_PORTS-1:0][CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_i, // tag in - comes one cycle later + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way_o, // we've got a hit on the corresponding way + + + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] req_o, + output logic [ ADDR_WIDTH-1:0] addr_o, + output l_data_t wdata_o, + output logic we_o, + output l_be_t be_o, + input l_data_t [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rdata_i +); + + assign rdata_o = rdata_i; + // one hot encoded + logic [NR_PORTS-1:0] id_d, id_q; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] sel_tag; + + always_comb begin : tag_sel + sel_tag = '0; + for (int unsigned i = 0; i < NR_PORTS; i++) if (id_q[i]) sel_tag = tag_i[i]; + end + + for (genvar j = 0; j < CVA6Cfg.DCACHE_SET_ASSOC; j++) begin : tag_cmp + assign hit_way_o[j] = (sel_tag == rdata_i[j].tag) ? rdata_i[j].valid : 1'b0; + end + + always_comb begin + + gnt_o = '0; + id_d = '0; + wdata_o = '0; + req_o = '0; + addr_o = '0; + be_o = '0; + we_o = '0; + // Request Side + // priority select + for (int unsigned i = 0; i < NR_PORTS; i++) begin + req_o = req_i[i]; + id_d = (1'b1 << i); + gnt_o[i] = 1'b1; + addr_o = addr_i[i]; + be_o = be_i[i]; + we_o = we_i[i]; + wdata_o = wdata_i[i]; + + if (req_i[i]) break; + end + + end + +`ifndef SYNTHESIS +`ifndef VERILATOR + // assert that cache only hits on one way + // this only needs to be checked one cycle after all ways have been requested + onehot : + assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o)) + else begin + $fatal(1, "Hit should be one-hot encoded"); + end +`endif +`endif + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + id_q <= 0; + end else begin + id_q <= id_d; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_axi_adapter.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_axi_adapter.sv new file mode 100644 index 0000000000..22cc5c075c --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_axi_adapter.sv @@ -0,0 +1,726 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 08.08.2018 +// Description: adapter module to connect the L1D$ and L1I$ to a 64bit AXI bus. +// + + +module wt_axi_adapter + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned ReqFifoDepth = 2, + parameter int unsigned MetaFifoDepth = CVA6Cfg.DCACHE_MAX_TX, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, + parameter type dcache_inval_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + // icache + input logic icache_data_req_i, + output logic icache_data_ack_o, + input icache_req_t icache_data_i, + // returning packets must be consumed immediately + output logic icache_rtrn_vld_o, + output icache_rtrn_t icache_rtrn_o, + + // dcache + input logic dcache_data_req_i, + output logic dcache_data_ack_o, + input dcache_req_t dcache_data_i, + // returning packets must be consumed immediately + output logic dcache_rtrn_vld_o, + output dcache_rtrn_t dcache_rtrn_o, + + // AXI port + output axi_req_t axi_req_o, + input axi_rsp_t axi_resp_i, + + // Invalidations + input logic [63:0] inval_addr_i, + input logic inval_valid_i, + output logic inval_ready_o +); + + // support up to 512bit cache lines + localparam AxiNumWords = (CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (CVA6Cfg.ICACHE_LINE_WIDTH > CVA6Cfg.DCACHE_LINE_WIDTH) + + (CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (CVA6Cfg.ICACHE_LINE_WIDTH <= CVA6Cfg.DCACHE_LINE_WIDTH) ; + localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8); + localparam AxiRdBlenIcache = CVA6Cfg.ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; + localparam AxiRdBlenDcache = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; + localparam AxiBlenWidth = AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords; + + /////////////////////////////////////////////////////// + // request path + /////////////////////////////////////////////////////// + + icache_req_t icache_data; + logic icache_data_full, icache_data_empty; + dcache_req_t dcache_data; + logic dcache_data_full, dcache_data_empty; + + logic [1:0] arb_req, arb_ack; + logic arb_idx, arb_gnt; + + logic axi_rd_req, axi_rd_gnt; + logic axi_wr_req, axi_wr_gnt; + logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy; + logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay; + logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; + logic [AxiBlenWidth-1:0] axi_rd_blen, axi_wr_blen; + logic [2:0] axi_rd_size, axi_wr_size; + logic [CVA6Cfg.AxiIdWidth-1:0] + axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; + logic [AxiNumWords-1:0][CVA6Cfg.AxiDataWidth-1:0] axi_wr_data; + logic [AxiNumWords-1:0][CVA6Cfg.AxiUserWidth-1:0] axi_wr_user; + logic [CVA6Cfg.AxiDataWidth-1:0] axi_rd_data; + logic [CVA6Cfg.AxiUserWidth-1:0] axi_rd_user; + logic [AxiNumWords-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] axi_wr_be; + logic [5:0] axi_wr_atop; + logic invalidate; + logic [$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] amo_off_d, amo_off_q; + // AMO generates r beat + logic amo_gen_r_d, amo_gen_r_q; + + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q; + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q; + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid; + logic dcache_rd_pop, dcache_wr_pop; + logic icache_rd_full, icache_rd_empty; + logic dcache_rd_full, dcache_rd_empty; + logic dcache_wr_full, dcache_wr_empty; + + assign icache_data_ack_o = icache_data_req_i & ~icache_data_full; + assign dcache_data_ack_o = dcache_data_req_i & ~dcache_data_full; + + // arbiter + assign arb_req = { + ~(dcache_data_empty | dcache_wr_full | dcache_rd_full), ~(icache_data_empty | icache_rd_full) + }; + + assign arb_gnt = axi_rd_gnt | axi_wr_gnt; + + rr_arb_tree #( + .NumIn (2), + .DataWidth(1), + .AxiVldRdy(1'b1), + .LockIn (1'b1) + ) i_rr_arb_tree ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (arb_req), + .gnt_o (arb_ack), + .data_i ('0), + .gnt_i (arb_gnt), + .req_o (), + .data_o (), + .idx_o (arb_idx) + ); + + // request side + always_comb begin : p_axi_req + // write channel + axi_wr_id_in = {{CVA6Cfg.AxiIdWidth-1{1'b0}}, arb_idx}; + axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/CVA6Cfg.XLEN){dcache_data.data}}; + axi_wr_user[0] = dcache_data.user; + // Cast to AXI address width + axi_wr_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr); + axi_wr_size = dcache_data.size; + axi_wr_req = 1'b0; + axi_wr_blen = '0;// single word writes + axi_wr_be = '0; + axi_wr_lock = '0; + axi_wr_atop = '0; + amo_off_d = amo_off_q; + amo_gen_r_d = amo_gen_r_q; + + // read channel + axi_rd_id_in = {{CVA6Cfg.AxiIdWidth-1{1'b0}}, arb_idx}; + axi_rd_req = 1'b0; + axi_rd_lock = '0; + axi_rd_blen = '0; + + if (dcache_data.paddr[2] == 1'b0) begin + axi_wr_user = {{64 - CVA6Cfg.AxiUserWidth{1'b0}}, dcache_data.user}; + end else begin + axi_wr_user = {dcache_data.user, {64 - CVA6Cfg.AxiUserWidth{1'b0}}}; + end + + // arbiter mux + if (arb_idx) begin + // Cast to AXI address width + axi_rd_addr = CVA6Cfg.AxiAddrWidth'(dcache_data.paddr); + // If dcache_data.size MSB is set, we want to read as much as possible + axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; + if (dcache_data.size[2]) begin + axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; + end + end else begin + // Cast to AXI address width + axi_rd_addr = CVA6Cfg.AxiAddrWidth'(icache_data.paddr); + axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill + if (!icache_data.nc) begin + axi_rd_blen = AxiRdBlenIcache[AxiBlenWidth-1:0]; + end + end + + // signal that an invalidation message + // needs to be generated + invalidate = 1'b0; + + // decode message type + if (|arb_req) begin + if (arb_idx == 0) begin + ////////////////////////////////////// + // IMISS + axi_rd_req = 1'b1; + ////////////////////////////////////// + end else begin + unique case (dcache_data.rtype) + ////////////////////////////////////// + wt_cache_pkg::DCACHE_LOAD_REQ: begin + axi_rd_req = 1'b1; + end + ////////////////////////////////////// + wt_cache_pkg::DCACHE_STORE_REQ: begin + axi_wr_req = 1'b1; + axi_wr_be = '0; + unique case (dcache_data.size[1:0]) + 2'b00: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte + 2'b01: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:2] = '1; // hword + 2'b10: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = '1; // word + default: + if (CVA6Cfg.IS_XLEN64) + axi_wr_be[0][dcache_data.paddr[$clog2( + CVA6Cfg.AxiDataWidth/8 + )-1:0]+:8] = '1; // dword + endcase + end + ////////////////////////////////////// + wt_cache_pkg::DCACHE_ATOMIC_REQ: begin + if (CVA6Cfg.RVA) begin + // default + // push back an invalidation here. + // since we only keep one read tx in flight, and since + // the dcache drains all writes/reads before executing + // an atomic, this is safe. + invalidate = arb_gnt; + axi_wr_req = 1'b1; + axi_wr_be = '0; + unique case (dcache_data.size[1:0]) + 2'b00: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte + 2'b01: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:2] = + '1; // hword + 2'b10: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = + '1; // word + default: + axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = + '1; // dword + endcase + amo_gen_r_d = 1'b1; + // need to use a separate ID here, so concat an additional bit + axi_wr_id_in[1] = 1'b1; + + unique case (dcache_data.amo_op) + AMO_LR: begin + axi_rd_lock = 1'b1; + axi_rd_req = 1'b1; + axi_rd_id_in[1] = 1'b1; + // tie to zero in this special case + axi_wr_req = 1'b0; + axi_wr_be = '0; + end + AMO_SC: begin + axi_wr_lock = 1'b1; + amo_gen_r_d = 1'b0; + // needed to properly encode success. store the result at offset within the returned + // AXI data word aligned with the requested word size. + amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)- + 1:0] & ~((1 << dcache_data.size[1:0]) - 1); + end + // RISC-V atops have a load semantic + AMO_SWAP: axi_wr_atop = axi_pkg::ATOP_ATOMICSWAP; + AMO_ADD: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD + }; + AMO_AND: begin + // in this case we need to invert the data to get a "CLR" + axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.data}}; + axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.user}}; + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR + }; + end + AMO_OR: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET + }; + AMO_XOR: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR + }; + AMO_MAX: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX + }; + AMO_MAXU: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX + }; + AMO_MIN: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN + }; + AMO_MINU: + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN + }; + default: ; // Do nothing + endcase + end + end + default: ; // Do nothing + ////////////////////////////////////// + endcase + end + end + end + + cva6_fifo_v3 #( + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), + .dtype(icache_req_t), + .DEPTH(ReqFifoDepth), + .FPGA_EN(CVA6Cfg.FpgaEn) + ) i_icache_data_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (icache_data_full), + .empty_o (icache_data_empty), + .usage_o (), + .data_i (icache_data_i), + .push_i (icache_data_ack_o), + .data_o (icache_data), + .pop_i (arb_ack[0]) + ); + + cva6_fifo_v3 #( + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), + .dtype(dcache_req_t), + .DEPTH(ReqFifoDepth), + .FPGA_EN(CVA6Cfg.FpgaEn) + ) i_dcache_data_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (dcache_data_full), + .empty_o (dcache_data_empty), + .usage_o (), + .data_i (dcache_data_i), + .push_i (dcache_data_ack_o), + .data_o (dcache_data), + .pop_i (arb_ack[1]) + ); + + /////////////////////////////////////////////////////// + // meta info feedback fifos + /////////////////////////////////////////////////////// + + logic icache_rtrn_rd_en, dcache_rtrn_rd_en; + logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q; + + cva6_fifo_v3 #( + .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH), + .DEPTH (MetaFifoDepth), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_rd_icache_id ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (icache_rd_full), + .empty_o (icache_rd_empty), + .usage_o (), + .data_i (icache_data.tid), + .push_i (arb_ack[0] & axi_rd_gnt), + .data_o (icache_rtrn_tid_d), + .pop_i (icache_rtrn_vld_d) + ); + + cva6_fifo_v3 #( + .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH), + .DEPTH (MetaFifoDepth), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_rd_dcache_id ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (dcache_rd_full), + .empty_o (dcache_rd_empty), + .usage_o (), + .data_i (dcache_data.tid), + .push_i (arb_ack[1] & axi_rd_gnt), + .data_o (dcache_rtrn_rd_tid), + .pop_i (dcache_rd_pop) + ); + + cva6_fifo_v3 #( + .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH), + .DEPTH (MetaFifoDepth), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_wr_dcache_id ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (dcache_wr_full), + .empty_o (dcache_wr_empty), + .usage_o (), + .data_i (dcache_data.tid), + .push_i (arb_ack[1] & axi_wr_gnt), + .data_o (dcache_rtrn_wr_tid), + .pop_i (dcache_wr_pop) + ); + + // select correct tid to return + assign dcache_rtrn_tid_d = (dcache_wr_pop) ? dcache_rtrn_wr_tid : dcache_rtrn_rd_tid; + + /////////////////////////////////////////////////////// + // return path + /////////////////////////////////////////////////////// + + // buffer write responses + logic b_full, b_empty, b_push, b_pop; + assign axi_wr_rdy = ~b_full; + assign b_push = axi_wr_valid & axi_wr_rdy; + + cva6_fifo_v3 #( + .DATA_WIDTH (CVA6Cfg.AxiIdWidth + 1), + .DEPTH (MetaFifoDepth), + .FALL_THROUGH(1'b1), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_b_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (b_full), + .empty_o (b_empty), + .usage_o (), + .data_i ({axi_wr_exokay, axi_wr_id_out}), + .push_i (b_push), + .data_o ({wr_exokay, wr_id_out}), + .pop_i (b_pop) + ); + + // buffer read responses in shift regs + logic icache_first_d, icache_first_q, dcache_first_d, dcache_first_q; + logic [CVA6Cfg.ICACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:0][CVA6Cfg.AxiUserWidth-1:0] + icache_rd_shift_user_d, icache_rd_shift_user_q; + logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:0][CVA6Cfg.AxiUserWidth-1:0] + dcache_rd_shift_user_d, dcache_rd_shift_user_q; + logic [CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] + icache_rd_shift_d, icache_rd_shift_q; + logic [CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] + dcache_rd_shift_d, dcache_rd_shift_q; + wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q; + dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q; + logic dcache_sc_rtrn, axi_rd_last; + + always_comb begin : p_axi_rtrn_shift + // output directly from regs + icache_rtrn_o = '0; + icache_rtrn_o.rtype = wt_cache_pkg::ICACHE_IFILL_ACK; + icache_rtrn_o.tid = icache_rtrn_tid_q; + icache_rtrn_o.data = icache_rd_shift_q; + icache_rtrn_o.user = icache_rd_shift_user_q; + icache_rtrn_vld_o = icache_rtrn_vld_q; + + dcache_rtrn_o = '0; + dcache_rtrn_o.rtype = dcache_rtrn_type_q; + dcache_rtrn_o.inv = dcache_rtrn_inv_q; + dcache_rtrn_o.tid = dcache_rtrn_tid_q; + dcache_rtrn_o.data = dcache_rd_shift_q; + dcache_rtrn_o.user = dcache_rd_shift_user_q; + dcache_rtrn_vld_o = dcache_rtrn_vld_q; + + // read shift registers + icache_rd_shift_d = icache_rd_shift_q; + icache_rd_shift_user_d = icache_rd_shift_user_q; + dcache_rd_shift_d = dcache_rd_shift_q; + dcache_rd_shift_user_d = dcache_rd_shift_user_q; + icache_first_d = icache_first_q; + dcache_first_d = dcache_first_q; + + if (icache_rtrn_rd_en) begin + icache_first_d = axi_rd_last; + if (CVA6Cfg.ICACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin + icache_rd_shift_d[0] = axi_rd_data; + end else begin + icache_rd_shift_d = { + axi_rd_data, icache_rd_shift_q[CVA6Cfg.ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1] + }; + end + icache_rd_shift_user_d = { + axi_rd_user, icache_rd_shift_user_q[CVA6Cfg.ICACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:1] + }; + // if this is a single word transaction, we need to make sure that word is placed at offset 0 + if (icache_first_q) begin + icache_rd_shift_d[0] = axi_rd_data; + icache_rd_shift_user_d[0] = axi_rd_user; + end + end + + if (dcache_rtrn_rd_en) begin + dcache_first_d = axi_rd_last; + if (CVA6Cfg.DCACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin + dcache_rd_shift_d[0] = axi_rd_data; + end else begin + dcache_rd_shift_d = { + axi_rd_data, dcache_rd_shift_q[CVA6Cfg.DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1] + }; + end + dcache_rd_shift_user_d = { + axi_rd_user, dcache_rd_shift_user_q[CVA6Cfg.DCACHE_USER_LINE_WIDTH/CVA6Cfg.AxiUserWidth-1:1] + }; + // if this is a single word transaction, we need to make sure that word is placed at offset 0 + if (dcache_first_q) begin + dcache_rd_shift_d[0] = axi_rd_data; + dcache_rd_shift_user_d[0] = axi_rd_user; + end + end else if (CVA6Cfg.RVA && dcache_sc_rtrn) begin + // encode lr/sc success + dcache_rd_shift_d[0] = '0; + dcache_rd_shift_user_d[0] = '0; + dcache_rd_shift_d[0][amo_off_q*8] = (wr_exokay) ? '0 : 1'b1; + dcache_rd_shift_user_d[0][amo_off_q*8] = (wr_exokay) ? '0 : 1'b1; + end + end + + // decode virtual read channels of icache + always_comb begin : p_axi_rtrn_decode + // we are not ready when invalidating + // note: b's are buffered separately + axi_rd_rdy = ~invalidate; + + icache_rtrn_rd_en = 1'b0; + icache_rtrn_vld_d = 1'b0; + + // decode virtual icache channel, + // this is independent on dcache decoding below + if (axi_rd_valid && axi_rd_id_out == 0 && axi_rd_rdy) begin + icache_rtrn_rd_en = 1'b1; + icache_rtrn_vld_d = axi_rd_last; + end + + dcache_rtrn_rd_en = 1'b0; + dcache_rtrn_vld_d = 1'b0; + dcache_rd_pop = 1'b0; + dcache_wr_pop = 1'b0; + dcache_rtrn_inv_d = '0; + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_LOAD_ACK; + b_pop = 1'b0; + dcache_sc_rtrn = 1'b0; + + // External invalidation requests (from coprocessor). This is safe as + // there are no other transactions when a coprocessor has pending stores. + inval_ready_o = 1'b0; + if (inval_valid_i) begin + inval_ready_o = 1'b1; + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; + dcache_rtrn_vld_d = 1'b1; + dcache_rtrn_inv_d.all = 1'b1; + dcache_rtrn_inv_d.idx = inval_addr_i[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; + ////////////////////////////////////// + // dcache needs some special treatment + // for arbitration and decoding of atomics + ////////////////////////////////////// + // this is safe, there is no other read tx in flight than this atomic. + // note that this self invalidation is handled in this way due to the + // write-through cache architecture, which is aligned with the openpiton + // cache subsystem. + end else if (CVA6Cfg.RVA && invalidate) begin + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; + dcache_rtrn_vld_d = 1'b1; + + dcache_rtrn_inv_d.all = 1'b1; + dcache_rtrn_inv_d.idx = dcache_data.paddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; + ////////////////////////////////////// + // read responses + // note that in case of atomics, the dcache sequentializes requests and + // guarantees that there are no other pending transactions in flight + end else if (axi_rd_valid && axi_rd_id_out[0] && axi_rd_rdy) begin + dcache_rtrn_rd_en = 1'b1; + dcache_rtrn_vld_d = axi_rd_last; + + // if this was an atomic op + if (CVA6Cfg.RVA && axi_rd_id_out[1]) begin + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_ATOMIC_ACK; + + // check if transaction was issued over write channel and pop that ID + if (!dcache_wr_empty) begin + dcache_wr_pop = axi_rd_last; + // if this is not the case, there MUST be an id in the read channel (LR) + end else begin + dcache_rd_pop = axi_rd_last; + end + end else begin + dcache_rd_pop = axi_rd_last; + end + ////////////////////////////////////// + // write responses, check b fifo + end else if (!b_empty) begin + b_pop = 1'b1; + + // this was an atomic + if (CVA6Cfg.RVA && wr_id_out[1]) begin + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_ATOMIC_ACK; + + // silently discard b response if we already popped the fifo + // with a R beat (iff the amo transaction generated an R beat) + if (!amo_gen_r_q) begin + dcache_rtrn_vld_d = 1'b1; + dcache_wr_pop = 1'b1; + dcache_sc_rtrn = 1'b1; + end + end else begin + // regular response + dcache_rtrn_type_d = wt_cache_pkg::DCACHE_STORE_ACK; + dcache_rtrn_vld_d = 1'b1; + dcache_wr_pop = 1'b1; + end + end + ////////////////////////////////////// + end + + // remote invalidations are not supported yet (this needs a cache coherence protocol) + // note that the atomic transactions would also need a "master exclusive monitor" in that case + // assign icache_rtrn_o.inv.idx = '0; + // assign icache_rtrn_o.inv.way = '0; + // assign icache_rtrn_o.inv.vld = '0; + // assign icache_rtrn_o.inv.all = '0; + + // assign dcache_rtrn_o.inv.idx = '0; + // assign dcache_rtrn_o.inv.way = '0; + // assign dcache_rtrn_o.inv.vld = '0; + // assign dcache_rtrn_o.inv.all = '0; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf + if (!rst_ni) begin + icache_first_q <= 1'b1; + dcache_first_q <= 1'b1; + icache_rd_shift_q <= '0; + icache_rd_shift_user_q <= '0; + dcache_rd_shift_q <= '0; + dcache_rd_shift_user_q <= '0; + icache_rtrn_vld_q <= '0; + dcache_rtrn_vld_q <= '0; + icache_rtrn_tid_q <= '0; + dcache_rtrn_tid_q <= '0; + dcache_rtrn_type_q <= wt_cache_pkg::DCACHE_LOAD_ACK; + dcache_rtrn_inv_q <= '0; + amo_off_q <= '0; + amo_gen_r_q <= 1'b0; + end else begin + icache_first_q <= icache_first_d; + dcache_first_q <= dcache_first_d; + icache_rd_shift_q <= icache_rd_shift_d; + icache_rd_shift_user_q <= icache_rd_shift_user_d; + dcache_rd_shift_q <= dcache_rd_shift_d; + dcache_rd_shift_user_q <= dcache_rd_shift_user_d; + icache_rtrn_vld_q <= icache_rtrn_vld_d; + dcache_rtrn_vld_q <= dcache_rtrn_vld_d; + icache_rtrn_tid_q <= icache_rtrn_tid_d; + dcache_rtrn_tid_q <= dcache_rtrn_tid_d; + dcache_rtrn_type_q <= dcache_rtrn_type_d; + dcache_rtrn_inv_q <= dcache_rtrn_inv_d; + amo_off_q <= amo_off_d; + amo_gen_r_q <= amo_gen_r_d; + end + end + + + /////////////////////////////////////////////////////// + // axi protocol shim + /////////////////////////////////////////////////////// + + axi_shim #( + .CVA6Cfg (CVA6Cfg), + .AxiNumWords(AxiNumWords), + .axi_req_t (axi_req_t), + .axi_rsp_t (axi_rsp_t) + ) i_axi_shim ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rd_req_i (axi_rd_req), + .rd_gnt_o (axi_rd_gnt), + .rd_addr_i (axi_rd_addr), + .rd_blen_i (axi_rd_blen), + .rd_size_i (axi_rd_size), + .rd_id_i (axi_rd_id_in), + .rd_rdy_i (axi_rd_rdy), + .rd_lock_i (axi_rd_lock), + .rd_last_o (axi_rd_last), + .rd_valid_o (axi_rd_valid), + .rd_data_o (axi_rd_data), + .rd_user_o (axi_rd_user), + .rd_id_o (axi_rd_id_out), + .rd_exokay_o(axi_rd_exokay), + .wr_req_i (axi_wr_req), + .wr_gnt_o (axi_wr_gnt), + .wr_addr_i (axi_wr_addr), + .wr_data_i (axi_wr_data), + .wr_user_i (axi_wr_user), + .wr_be_i (axi_wr_be), + .wr_blen_i (axi_wr_blen), + .wr_size_i (axi_wr_size), + .wr_id_i (axi_wr_id_in), + .wr_lock_i (axi_wr_lock), + .wr_atop_i (axi_wr_atop), + .wr_rdy_i (axi_wr_rdy), + .wr_valid_o (axi_wr_valid), + .wr_id_o (axi_wr_id_out), + .wr_exokay_o(axi_wr_exokay), + .axi_req_o (axi_req_o), + .axi_resp_i (axi_resp_i) + ); + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + +`endif + //pragma translate_on + +endmodule // wt_l15_adapter diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_cache_subsystem.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_cache_subsystem.sv new file mode 100644 index 0000000000..0a2ac0c79c --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_cache_subsystem.sv @@ -0,0 +1,288 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Ariane cache subsystem that is compatible with the OpenPiton +// coherent memory system. +// +// Define PITON_ARIANE if you want to use this cache. +// Define CVA6Cfg.DCacheType if you want to use this cache +// with a standard 64 bit AXI interface instead of the OpenPiton +// L1.5 interface. + + +module wt_cache_subsystem + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + parameter int unsigned NumPorts = 4, + parameter type noc_req_t = logic, + parameter type noc_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // I$ + input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) + input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together + output logic icache_miss_o, // to performance counter + // address translation requests + input icache_areq_t icache_areq_i, // to/from frontend + output icache_arsp_t icache_areq_o, + // data requests + input icache_dreq_t icache_dreq_i, // to/from frontend + output icache_drsp_t icache_dreq_o, + // D$ + // Cache management + input logic dcache_enable_i, // from CSR + input logic dcache_flush_i, // high until acknowledged + output logic dcache_flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic dcache_miss_o, // we missed on a ld/st + // For Performance Counter + output logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, + // AMO interface + input amo_req_t dcache_amo_req_i, + output amo_resp_t dcache_amo_resp_o, + // Request ports + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU + // writebuffer status + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, + // memory side + output noc_req_t noc_req_o, + input noc_resp_t noc_resp_i, + // Invalidations + input logic [63:0] inval_addr_i, + input logic inval_valid_i, + output logic inval_ready_o + // TODO: interrupt interface +); + + // dcache interface + localparam type dcache_inval_t = struct packed { + logic vld; // invalidate only affected way + logic all; // invalidate all ways + logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate + logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate + }; + + localparam type dcache_req_t = struct packed { + wt_cache_pkg::dcache_out_t rtype; // see definitions above + logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to replace + logic [CVA6Cfg.PLEN-1:0] paddr; // physical address + logic [CVA6Cfg.XLEN-1:0] data; // word width of processor (no block stores at the moment) + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment) + logic nc; // noncacheable + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + ariane_pkg::amo_t amo_op; // amo opcode + }; + + localparam type dcache_rtrn_t = struct packed { + wt_cache_pkg::dcache_in_t rtype; // see definitions above + logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] user; // user bits + dcache_inval_t inv; // invalidation vector + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }; + + logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; + icache_req_t icache_adapter; + icache_rtrn_t adapter_icache; + + + logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld; + dcache_req_t dcache_adapter; + dcache_rtrn_t adapter_dcache; + + cva6_icache #( + // use ID 0 for icache reads + .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .RdTxId(0) + ) i_cva6_icache ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (icache_flush_i), + .en_i (icache_en_i), + .miss_o (icache_miss_o), + .areq_i (icache_areq_i), + .areq_o (icache_areq_o), + .dreq_i (icache_dreq_i), + .dreq_o (icache_dreq_o), + .mem_rtrn_vld_i(adapter_icache_rtrn_vld), + .mem_rtrn_i (adapter_icache), + .mem_data_req_o(icache_adapter_data_req), + .mem_data_ack_i(adapter_icache_data_ack), + .mem_data_o (icache_adapter) + ); + + + // Note: + // Ports 0/1 for PTW and LD unit are read only. + // they have equal prio and are RR arbited + // Port 2 is write only and goes into the merging write buffer + wt_dcache #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), + // use ID 1 for dcache reads and amos. note that the writebuffer + // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. + .RdAmoTxId(1) + ) i_wt_dcache ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .enable_i (dcache_enable_i), + .flush_i (dcache_flush_i), + .flush_ack_o (dcache_flush_ack_o), + .miss_o (dcache_miss_o), + .wbuffer_empty_o (wbuffer_empty_o), + .wbuffer_not_ni_o(wbuffer_not_ni_o), + .amo_req_i (dcache_amo_req_i), + .amo_resp_o (dcache_amo_resp_o), + .req_ports_i (dcache_req_ports_i), + .req_ports_o (dcache_req_ports_o), + .miss_vld_bits_o (miss_vld_bits_o), + .mem_rtrn_vld_i (adapter_dcache_rtrn_vld), + .mem_rtrn_i (adapter_dcache), + .mem_data_req_o (dcache_adapter_data_req), + .mem_data_ack_i (adapter_dcache_data_ack), + .mem_data_o (dcache_adapter) + ); + + + /////////////////////////////////////////////////////// + // memory plumbing, either use 64bit AXI port or native + // L15 cache interface (derived from OpenSPARC CCX). + /////////////////////////////////////////////////////// + +`ifdef PITON_ARIANE + wt_l15_adapter #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t) + ) i_adapter ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .icache_data_req_i(icache_adapter_data_req), + .icache_data_ack_o(adapter_icache_data_ack), + .icache_data_i (icache_adapter), + .icache_rtrn_vld_o(adapter_icache_rtrn_vld), + .icache_rtrn_o (adapter_icache), + .dcache_data_req_i(dcache_adapter_data_req), + .dcache_data_ack_o(adapter_dcache_data_ack), + .dcache_data_i (dcache_adapter), + .dcache_rtrn_vld_o(adapter_dcache_rtrn_vld), + .dcache_rtrn_o (adapter_dcache), + .l15_req_o (noc_req_o), + .l15_rtrn_i (noc_resp_i) + ); +`else + wt_axi_adapter #( + .CVA6Cfg(CVA6Cfg), + .axi_req_t(noc_req_t), + .axi_rsp_t(noc_resp_t), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), + .dcache_inval_t(dcache_inval_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t) + ) i_adapter ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .icache_data_req_i(icache_adapter_data_req), + .icache_data_ack_o(adapter_icache_data_ack), + .icache_data_i (icache_adapter), + .icache_rtrn_vld_o(adapter_icache_rtrn_vld), + .icache_rtrn_o (adapter_icache), + .dcache_data_req_i(dcache_adapter_data_req), + .dcache_data_ack_o(adapter_dcache_data_ack), + .dcache_data_i (dcache_adapter), + .dcache_rtrn_vld_o(adapter_dcache_rtrn_vld), + .dcache_rtrn_o (adapter_dcache), + .axi_req_o (noc_req_o), + .axi_resp_i (noc_resp_i), + .inval_addr_i (inval_addr_i), + .inval_valid_i (inval_valid_i), + .inval_ready_o (inval_ready_o) + ); +`endif + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + a_invalid_instruction_fetch : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X", + icache_dreq_o.vaddr, + icache_dreq_o.data + ); + + for (genvar j = 0; j < CVA6Cfg.XLEN / 8; j++) begin : gen_invalid_write_assertion + a_invalid_write_data : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> dcache_req_ports_i[NumPorts-1].data_be[j] |-> (|dcache_req_ports_i[NumPorts-1].data_wdata[j*8+:8] !== 1'hX)) + else + $warning( + 1, + "[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X, databe=%016X", + { + dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index + }, + dcache_req_ports_i[NumPorts-1].data_be, + dcache_req_ports_i[NumPorts-1].data_wdata, + dcache_req_ports_i[NumPorts-1].data_be & dcache_req_ports_i[NumPorts-1].data_wdata + ); + end + + + for (genvar j = 0; j < NumPorts - 1; j++) begin : gen_assertion + a_invalid_read_data : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_o[j].data_rvalid && ~dcache_req_ports_i[j].kill_req |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX) + else + $warning( + 1, + "[l1 dcache] reading invalid data on port %01d: data=%016X", + j, + dcache_req_ports_o[j].data_rdata + ); + end +`endif + //pragma translate_on + + +endmodule // wt_cache_subsystem diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_dcache.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache.sv new file mode 100644 index 0000000000..5b49d957fb --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache.sv @@ -0,0 +1,389 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: Write-Through Data cache that is compatible with openpiton. + + +module wt_dcache + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, + parameter int unsigned NumPorts = 4, // number of miss ports + // ID to be used for read and AMO transactions. + // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions + parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdAmoTxId = 1 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a ld/st + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, + + // AMO interface + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + + // Request ports + input dcache_req_i_t [NumPorts-1:0] req_ports_i, + output dcache_req_o_t [NumPorts-1:0] req_ports_o, + + output logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, + + input logic mem_rtrn_vld_i, + input dcache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output dcache_req_t mem_data_o +); + + localparam DCACHE_CL_IDX_WIDTH = $clog2(CVA6Cfg.DCACHE_NUM_WORDS); + + localparam type wbuffer_t = struct packed { + logic [CVA6Cfg.DCACHE_TAG_WIDTH+(CVA6Cfg.DCACHE_INDEX_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES)-1:0] wtag; + logic [CVA6Cfg.XLEN-1:0] data; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] user; + logic [(CVA6Cfg.XLEN/8)-1:0] dirty; // byte is dirty + logic [(CVA6Cfg.XLEN/8)-1:0] valid; // byte is valid + logic [(CVA6Cfg.XLEN/8)-1:0] txblock; // byte is part of transaction in-flight + logic checked; // if cache state of this word has been checked + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache + }; + + // miss unit <-> read controllers + logic cache_en; + + // miss unit <-> memory + logic wr_cl_vld; + logic wr_cl_nc; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_cl_we; + logic [ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] wr_cl_tag; + logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx; + logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_cl_off; + logic [ CVA6Cfg.DCACHE_LINE_WIDTH-1:0] wr_cl_data; + logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user; + logic [ CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_vld_bits; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_req; + logic wr_ack; + logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx; + logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off; + logic [ CVA6Cfg.XLEN-1:0] wr_data; + logic [ (CVA6Cfg.XLEN/8)-1:0] wr_data_be; + logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user; + + // miss unit <-> controllers/wbuffer + logic [ NumPorts-1:0] miss_req; + logic [ NumPorts-1:0] miss_ack; + logic [ NumPorts-1:0] miss_nc; + logic [ NumPorts-1:0] miss_we; + logic [ NumPorts-1:0][ CVA6Cfg.XLEN-1:0] miss_wdata; + logic [ NumPorts-1:0][ CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser; + logic [ NumPorts-1:0][ CVA6Cfg.PLEN-1:0] miss_paddr; + logic [ NumPorts-1:0][ 2:0] miss_size; + logic [ NumPorts-1:0][ CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id; + logic [ NumPorts-1:0] miss_replay; + logic [ NumPorts-1:0] miss_rtrn_vld; + logic [ CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id; + + // memory <-> read controllers/miss unit + logic [ NumPorts-1:0] rd_prio; + logic [ NumPorts-1:0] rd_tag_only; + logic [ NumPorts-1:0] rd_req; + logic [ NumPorts-1:0] rd_ack; + logic [ NumPorts-1:0][ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag; + logic [ NumPorts-1:0][ DCACHE_CL_IDX_WIDTH-1:0] rd_idx; + logic [ NumPorts-1:0][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] rd_off; + logic [ CVA6Cfg.XLEN-1:0] rd_data; + logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits; + logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh; + + // miss unit <-> wbuffer + logic [ CVA6Cfg.DCACHE_MAX_TX-1:0][ CVA6Cfg.PLEN-1:0] tx_paddr; + logic [ CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld; + + // wbuffer <-> memory + wbuffer_t [ CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_data; + + + /////////////////////////////////////////////////////// + // miss handling unit + /////////////////////////////////////////////////////// + + wt_dcache_missunit #( + .CVA6Cfg(CVA6Cfg), + .DCACHE_CL_IDX_WIDTH(DCACHE_CL_IDX_WIDTH), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), + .AmoTxId(RdAmoTxId), + .NumPorts(NumPorts) + ) i_wt_dcache_missunit ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .enable_i (enable_i), + .flush_i (flush_i), + .flush_ack_o (flush_ack_o), + .miss_o (miss_o), + .wbuffer_empty_i(wbuffer_empty_o), + .cache_en_o (cache_en), + // amo interface + .amo_req_i (amo_req_i), + .amo_resp_o (amo_resp_o), + // miss handling interface + .miss_req_i (miss_req), + .miss_ack_o (miss_ack), + .miss_nc_i (miss_nc), + .miss_we_i (miss_we), + .miss_wdata_i (miss_wdata), + .miss_wuser_i (miss_wuser), + .miss_paddr_i (miss_paddr), + .miss_vld_bits_i(miss_vld_bits_o), + .miss_size_i (miss_size), + .miss_id_i (miss_id), + .miss_replay_o (miss_replay), + .miss_rtrn_vld_o(miss_rtrn_vld), + .miss_rtrn_id_o (miss_rtrn_id), + // from writebuffer + .tx_paddr_i (tx_paddr), + .tx_vld_i (tx_vld), + // cache memory interface + .wr_cl_vld_o (wr_cl_vld), + .wr_cl_nc_o (wr_cl_nc), + .wr_cl_we_o (wr_cl_we), + .wr_cl_tag_o (wr_cl_tag), + .wr_cl_idx_o (wr_cl_idx), + .wr_cl_off_o (wr_cl_off), + .wr_cl_data_o (wr_cl_data), + .wr_cl_user_o (wr_cl_user), + .wr_cl_data_be_o(wr_cl_data_be), + .wr_vld_bits_o (wr_vld_bits), + // memory interface + .mem_rtrn_vld_i (mem_rtrn_vld_i), + .mem_rtrn_i (mem_rtrn_i), + .mem_data_req_o (mem_data_req_o), + .mem_data_ack_i (mem_data_ack_i), + .mem_data_o (mem_data_o) + ); + + /////////////////////////////////////////////////////// + // read controllers (LD unit and PTW/MMU) + /////////////////////////////////////////////////////// + + // 0 is used by MMU or implicit read by zcmt, 1 by READ access requests + for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports + // set these to high prio ports + if ((k == 0 && (CVA6Cfg.MmuPresent || CVA6Cfg.RVZCMT )) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin + assign rd_prio[k] = 1'b1; + wt_dcache_ctrl #( + .CVA6Cfg(CVA6Cfg), + .DCACHE_CL_IDX_WIDTH(DCACHE_CL_IDX_WIDTH), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .RdTxId(RdAmoTxId) + ) i_wt_dcache_ctrl ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .cache_en_i (cache_en), + // reqs from core + .req_port_i (req_ports_i[k]), + .req_port_o (req_ports_o[k]), + // miss interface + .miss_req_o (miss_req[k]), + .miss_ack_i (miss_ack[k]), + .miss_we_o (miss_we[k]), + .miss_wdata_o (miss_wdata[k]), + .miss_wuser_o (miss_wuser[k]), + .miss_vld_bits_o(miss_vld_bits_o[k]), + .miss_paddr_o (miss_paddr[k]), + .miss_nc_o (miss_nc[k]), + .miss_size_o (miss_size[k]), + .miss_id_o (miss_id[k]), + .miss_replay_i (miss_replay[k]), + .miss_rtrn_vld_i(miss_rtrn_vld[k]), + // used to detect readout mux collisions + .wr_cl_vld_i (wr_cl_vld), + // cache mem interface + .rd_tag_o (rd_tag[k]), + .rd_idx_o (rd_idx[k]), + .rd_off_o (rd_off[k]), + .rd_req_o (rd_req[k]), + .rd_tag_only_o (rd_tag_only[k]), + .rd_ack_i (rd_ack[k]), + .rd_data_i (rd_data), + .rd_user_i (rd_user), + .rd_vld_bits_i (rd_vld_bits), + .rd_hit_oh_i (rd_hit_oh) + ); + end else begin + assign rd_prio[k] = 1'b0; + assign req_ports_o[k] = '0; + assign miss_req[k] = 1'b0; + assign miss_we[k] = 1'b0; + assign miss_wdata[k] = {{CVA6Cfg.XLEN} {1'b0}}; + assign miss_wuser[k] = {{CVA6Cfg.DCACHE_USER_WIDTH} {1'b0}}; + assign miss_vld_bits_o[k] = {{CVA6Cfg.DCACHE_SET_ASSOC} {1'b0}}; + assign miss_paddr[k] = {{CVA6Cfg.PLEN} {1'b0}}; + assign miss_nc[k] = 1'b0; + assign miss_size[k] = 3'b0; + assign miss_id[k] = {{CVA6Cfg.MEM_TID_WIDTH} {1'b0}}; + assign rd_tag[k] = {{CVA6Cfg.DCACHE_TAG_WIDTH} {1'b0}}; + assign rd_idx[k] = {{DCACHE_CL_IDX_WIDTH} {1'b0}}; + assign rd_off[k] = {{CVA6Cfg.DCACHE_OFFSET_WIDTH} {1'b0}}; + assign rd_req[k] = 1'b0; + assign rd_tag_only[k] = 1'b0; + end + end + + /////////////////////////////////////////////////////// + // store unit controller + /////////////////////////////////////////////////////// + + // set read port to low priority + assign rd_prio[NumPorts-1] = 1'b0; + + wt_dcache_wbuffer #( + .CVA6Cfg(CVA6Cfg), + .DCACHE_CL_IDX_WIDTH(DCACHE_CL_IDX_WIDTH), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .wbuffer_t(wbuffer_t) + ) i_wt_dcache_wbuffer ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .empty_o (wbuffer_empty_o), + .not_ni_o (wbuffer_not_ni_o), + // TODO: fix this + .cache_en_i (cache_en), + // .cache_en_i ( '0 ), + // request ports from core (store unit) + .req_port_i (req_ports_i[NumPorts-1]), + .req_port_o (req_ports_o[NumPorts-1]), + // miss unit interface + .miss_req_o (miss_req[NumPorts-1]), + .miss_ack_i (miss_ack[NumPorts-1]), + .miss_we_o (miss_we[NumPorts-1]), + .miss_wdata_o (miss_wdata[NumPorts-1]), + .miss_wuser_o (miss_wuser[NumPorts-1]), + .miss_vld_bits_o(miss_vld_bits_o[NumPorts-1]), + .miss_paddr_o (miss_paddr[NumPorts-1]), + .miss_nc_o (miss_nc[NumPorts-1]), + .miss_size_o (miss_size[NumPorts-1]), + .miss_id_o (miss_id[NumPorts-1]), + .miss_rtrn_vld_i(miss_rtrn_vld[NumPorts-1]), + .miss_rtrn_id_i (miss_rtrn_id), + // cache read interface + .rd_tag_o (rd_tag[NumPorts-1]), + .rd_idx_o (rd_idx[NumPorts-1]), + .rd_off_o (rd_off[NumPorts-1]), + .rd_req_o (rd_req[NumPorts-1]), + .rd_tag_only_o (rd_tag_only[NumPorts-1]), + .rd_ack_i (rd_ack[NumPorts-1]), + .rd_data_i (rd_data), + .rd_vld_bits_i (rd_vld_bits), + .rd_hit_oh_i (rd_hit_oh), + // incoming invalidations/cache refills + .wr_cl_vld_i (wr_cl_vld), + .wr_cl_idx_i (wr_cl_idx), + // single word write interface + .wr_req_o (wr_req), + .wr_ack_i (wr_ack), + .wr_idx_o (wr_idx), + .wr_off_o (wr_off), + .wr_data_o (wr_data), + .wr_user_o (wr_user), + .wr_data_be_o (wr_data_be), + // write buffer forwarding + .wbuffer_data_o (wbuffer_data), + .tx_paddr_o (tx_paddr), + .tx_vld_o (tx_vld) + ); + + /////////////////////////////////////////////////////// + // memory arrays, arbitration and tag comparison + /////////////////////////////////////////////////////// + + wt_dcache_mem #( + .CVA6Cfg(CVA6Cfg), + .DCACHE_CL_IDX_WIDTH(DCACHE_CL_IDX_WIDTH), + .wbuffer_t(wbuffer_t), + .NumPorts(NumPorts) + ) i_wt_dcache_mem ( + .clk_i (clk_i), + .rst_ni (rst_ni), + // read ports + .rd_prio_i (rd_prio), + .rd_tag_i (rd_tag), + .rd_idx_i (rd_idx), + .rd_off_i (rd_off), + .rd_req_i (rd_req), + .rd_tag_only_i (rd_tag_only), + .rd_ack_o (rd_ack), + .rd_vld_bits_o (rd_vld_bits), + .rd_hit_oh_o (rd_hit_oh), + .rd_data_o (rd_data), + .rd_user_o (rd_user), + // cacheline write port + .wr_cl_vld_i (wr_cl_vld), + .wr_cl_nc_i (wr_cl_nc), + .wr_cl_we_i (wr_cl_we), + .wr_cl_tag_i (wr_cl_tag), + .wr_cl_idx_i (wr_cl_idx), + .wr_cl_off_i (wr_cl_off), + .wr_cl_data_i (wr_cl_data), + .wr_cl_user_i (wr_cl_user), + .wr_cl_data_be_i(wr_cl_data_be), + .wr_vld_bits_i (wr_vld_bits), + // single word write port + .wr_req_i (wr_req), + .wr_ack_o (wr_ack), + .wr_idx_i (wr_idx), + .wr_off_i (wr_off), + .wr_data_i (wr_data), + .wr_user_i (wr_user), + .wr_data_be_i (wr_data_be), + // write buffer forwarding + .wbuffer_data_i (wbuffer_data) + ); + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + // check for concurrency issues + + + //pragma translate_off +`ifndef VERILATOR + flush : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) flush_i |-> flush_ack_o |-> wbuffer_empty_o) + else $fatal(1, "[l1 dcache] flushed cache implies flushed wbuffer"); + + initial begin + // assert wrong parameterizations + assert (CVA6Cfg.DCACHE_INDEX_WIDTH <= 12) + else $fatal(1, "[l1 dcache] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif + //pragma translate_on + +endmodule // wt_dcache diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_ctrl.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_ctrl.sv new file mode 100644 index 0000000000..61fd7b0317 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_ctrl.sv @@ -0,0 +1,302 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: DCache controller for read port + + +module wt_dcache_ctrl + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter DCACHE_CL_IDX_WIDTH = 0, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 1 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic cache_en_i, + // core request ports + input dcache_req_i_t req_port_i, + output dcache_req_o_t req_port_o, + // interface to miss handler + output logic miss_req_o, + input logic miss_ack_i, + output logic miss_we_o, // unused (set to 0) + output logic [CVA6Cfg.XLEN-1:0] miss_wdata_o, // unused (set to 0) + output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_o, // unused (set to 0) + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // valid bits at the missed index + output logic [CVA6Cfg.PLEN-1:0] miss_paddr_o, + output logic miss_nc_o, // request to I/O space + output logic [2:0] miss_size_o, // 00: 1byte, 01: 2byte, 10: 4byte, 11: 8byte, 111: cacheline + output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_o, // set to constant ID + input logic miss_replay_i, // request collided with pending miss - have to replay the request + input logic miss_rtrn_vld_i, // signals that the miss has been served, asserted in the same cycle as when the data returns from memory + // used to detect readout mux collisions + input logic wr_cl_vld_i, + // cache memory interface + output logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag_o, // tag in - comes one cycle later + output logic [DCACHE_CL_IDX_WIDTH-1:0] rd_idx_o, + output logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] rd_off_o, + output logic rd_req_o, // read the word at offset off_i[:3] in all ways + output logic rd_tag_only_o, // set to zero here + input logic rd_ack_i, + input logic [CVA6Cfg.XLEN-1:0] rd_data_i, + input logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user_i, + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_i +); + + // controller FSM + typedef enum logic [2:0] { + IDLE, + READ, + MISS_REQ, + MISS_WAIT, + KILL_MISS, + KILL_MISS_ACK, + REPLAY_REQ, + REPLAY_READ + } state_e; + state_e state_d, state_q; + + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] address_tag_d, address_tag_q; + logic [DCACHE_CL_IDX_WIDTH-1:0] address_idx_d, address_idx_q; + logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] address_off_d, address_off_q; + logic [CVA6Cfg.DcacheIdWidth-1:0] id_d, id_q; + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vld_data_d, vld_data_q; + logic save_tag, rd_req_d, rd_req_q, rd_ack_d, rd_ack_q; + logic [1:0] data_size_d, data_size_q; + + /////////////////////////////////////////////////////// + // misc + /////////////////////////////////////////////////////// + + // map address to tag/idx/offset and save + assign vld_data_d = (rd_req_q) ? rd_vld_bits_i : vld_data_q; + assign address_tag_d = (save_tag) ? req_port_i.address_tag : address_tag_q; + assign address_idx_d = (req_port_o.data_gnt) ? req_port_i.address_index[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] : address_idx_q; + assign address_off_d = (req_port_o.data_gnt) ? req_port_i.address_index[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] : address_off_q; + assign id_d = (req_port_o.data_gnt) ? req_port_i.data_id : id_q; + assign data_size_d = (req_port_o.data_gnt) ? req_port_i.data_size : data_size_q; + assign rd_tag_o = address_tag_d; + assign rd_idx_o = address_idx_d; + assign rd_off_o = address_off_d; + + assign req_port_o.data_rdata = rd_data_i; + assign req_port_o.data_ruser = rd_user_i; + assign req_port_o.data_rid = id_q; + + // to miss unit + assign miss_vld_bits_o = vld_data_q; + assign miss_paddr_o = {address_tag_q, address_idx_q, address_off_q}; + assign miss_size_o = (miss_nc_o) ? {1'b0, data_size_q} : 3'b111; + + // noncacheable if request goes to I/O space, or if cache is disabled + assign miss_nc_o = (~cache_en_i) | (~config_pkg::is_inside_cacheable_regions( + CVA6Cfg, + {{{64-CVA6Cfg.DCACHE_TAG_WIDTH-CVA6Cfg.DCACHE_INDEX_WIDTH}{1'b0}}, address_tag_q, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}} + )); + + + assign miss_we_o = '0; + assign miss_wdata_o = '0; + assign miss_wuser_o = '0; + assign miss_id_o = RdTxId; + assign rd_req_d = rd_req_o; + assign rd_ack_d = rd_ack_i; + assign rd_tag_only_o = '0; + + /////////////////////////////////////////////////////// + // main control logic + /////////////////////////////////////////////////////// + + always_comb begin : p_fsm + // default assignment + state_d = state_q; + save_tag = 1'b0; + rd_req_o = 1'b0; + miss_req_o = 1'b0; + req_port_o.data_rvalid = 1'b0; + req_port_o.data_gnt = 1'b0; + + // interfaces + unique case (state_q) + ////////////////////////////////// + // wait for an incoming request + IDLE: begin + if (req_port_i.data_req) begin + rd_req_o = 1'b1; + // if read ack then ack the `req_port_o`, and goto `READ` state + if (rd_ack_i) begin + state_d = READ; + req_port_o.data_gnt = 1'b1; + end + end + end + ////////////////////////////////// + // check whether we have a hit + // in case the cache is disabled, + // or in case the address is NC, we + // reuse the miss mechanism to handle + // the request + READ, REPLAY_READ: begin + // speculatively request cache line + rd_req_o = 1'b1; + + // kill -> go back to IDLE + if (req_port_i.kill_req) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + end else if (req_port_i.tag_valid | state_q == REPLAY_READ) begin + save_tag = (state_q != REPLAY_READ); + if (wr_cl_vld_i || !rd_ack_q) begin + state_d = REPLAY_REQ; + // we've got a hit + end else if ((|rd_hit_oh_i) && cache_en_i) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + // we can handle another request + if (rd_ack_i && req_port_i.data_req) begin + state_d = READ; + req_port_o.data_gnt = 1'b1; + end + // we've got a miss + end else begin + state_d = MISS_REQ; + end + end + end + ////////////////////////////////// + // issue request + MISS_REQ: begin + miss_req_o = 1'b1; + + if (req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + if (miss_ack_i) begin + state_d = KILL_MISS; + end else begin + state_d = KILL_MISS_ACK; + end + end else if (miss_replay_i) begin + state_d = REPLAY_REQ; + end else if (miss_ack_i) begin + state_d = MISS_WAIT; + end + end + ////////////////////////////////// + // wait until the memory transaction + // returns. + MISS_WAIT: begin + if (req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + if (miss_rtrn_vld_i) begin + state_d = IDLE; + end else begin + state_d = KILL_MISS; + end + end else if (miss_rtrn_vld_i) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + end + end + ////////////////////////////////// + // replay read request + REPLAY_REQ: begin + rd_req_o = 1'b1; + if (req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + state_d = IDLE; + end else if (rd_ack_i) begin + state_d = REPLAY_READ; + end + end + ////////////////////////////////// + KILL_MISS_ACK: begin + miss_req_o = 1'b1; + // in this case the miss handler did not issue + // a transaction and we can safely go to idle + if (miss_replay_i) begin + state_d = IDLE; + end else if (miss_ack_i) begin + state_d = KILL_MISS; + end + end + ////////////////////////////////// + // killed miss, + // wait until miss unit responds and + // go back to idle + KILL_MISS: begin + if (miss_rtrn_vld_i) begin + state_d = IDLE; + end + end + default: begin + // we should never get here + state_d = IDLE; + end + endcase // state_q + end + + /////////////////////////////////////////////////////// + // ff's + /////////////////////////////////////////////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + state_q <= IDLE; + address_tag_q <= '0; + address_idx_q <= '0; + address_off_q <= '0; + id_q <= '0; + vld_data_q <= '0; + data_size_q <= '0; + rd_req_q <= '0; + rd_ack_q <= '0; + end else begin + state_q <= state_d; + address_tag_q <= address_tag_d; + address_idx_q <= address_idx_d; + address_off_q <= address_off_d; + id_q <= id_d; + vld_data_q <= vld_data_d; + data_size_q <= data_size_d; + rd_req_q <= rd_req_d; + rd_ack_q <= rd_ack_d; + end + end + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + + hot1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) (!rd_ack_i) |=> cache_en_i |-> $onehot0( + rd_hit_oh_i + )) + else $fatal(1, "[l1 dcache ctrl] rd_hit_oh_i signal must be hot1"); + + initial begin + // assert wrong parameterizations + assert (CVA6Cfg.DCACHE_INDEX_WIDTH <= 12) + else + $fatal(1, "[l1 dcache ctrl] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif + //pragma translate_on + +endmodule // wt_dcache_ctrl diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_mem.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_mem.sv new file mode 100644 index 0000000000..e20320de24 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_mem.sv @@ -0,0 +1,440 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: Memory arrays, arbiter and tag comparison for WT dcache. +// +// +// Notes: 1) all ports can trigger a readout of all ways, and the way where the tag hits is selected +// +// 2) only port0 can write full cache lines. higher ports are read only. also, port0 can only read the tag array, +// and does not trigger a cache line readout. +// +// 3) the single word write port is a separate port without access to the tag memory. +// these single word writes can interleave with read operations if they go to different +// cacheline offsets, since each word offset is placed into a different SRAM bank. +// +// 4) Read ports with same priority are RR arbited. but high prio ports (rd_prio_i[port_nr] = '1b1) will stall +// low prio ports (rd_prio_i[port_nr] = '1b0) + + +module wt_dcache_mem + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter DCACHE_CL_IDX_WIDTH = 0, + parameter type wbuffer_t = logic, + parameter int unsigned NumPorts = 3 +) ( + input logic clk_i, + input logic rst_ni, + + // ports + input logic [NumPorts-1:0][CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag_i, // tag in - comes one cycle later + input logic [NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx_i, + input logic [NumPorts-1:0][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] rd_off_i, + input logic [NumPorts-1:0] rd_req_i, // read the word at offset off_i[:3] in all ways + input logic [NumPorts-1:0] rd_tag_only_i, // only do a tag/valid lookup, no access to data arrays + input logic [NumPorts-1:0] rd_prio_i, // 0: low prio, 1: high prio + output logic [NumPorts-1:0] rd_ack_o, + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_o, + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_o, + output logic [CVA6Cfg.XLEN-1:0] rd_data_o, + output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user_o, + + // only available on port 0, uses address signals of port 0 + input logic wr_cl_vld_i, + input logic wr_cl_nc_i, // noncacheable access + input logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_cl_we_i, // writes a full cacheline + input logic [ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] wr_cl_tag_i, + input logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_i, + input logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_cl_off_i, + input logic [ CVA6Cfg.DCACHE_LINE_WIDTH-1:0] wr_cl_data_i, + input logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user_i, + input logic [ CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be_i, + input logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_vld_bits_i, + + // separate port for single word write, no tag access + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_req_i, // write a single word to offset off_i[:3] + output logic wr_ack_o, + input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_i, + input logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off_i, + input logic [CVA6Cfg.XLEN-1:0] wr_data_i, + input logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user_i, + input logic [(CVA6Cfg.XLEN/8)-1:0] wr_data_be_i, + + // forwarded wbuffer + input wbuffer_t [CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_data_i +); + + localparam DCACHE_NUM_BANKS = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN; + localparam DCACHE_NUM_BANKS_WIDTH = $clog2(DCACHE_NUM_BANKS); + + // functions + function automatic logic [DCACHE_NUM_BANKS-1:0] dcache_cl_bin2oh( + input logic [DCACHE_NUM_BANKS_WIDTH-1:0] in); + logic [DCACHE_NUM_BANKS-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + // number of bits needed to address AXI data. If AxiDataWidth equals CVA6Cfg.XLEN this parameter + // is not needed. Therefore, increment it by one to avoid reverse range select during elaboration. + localparam AXI_OFFSET_WIDTH = CVA6Cfg.AxiDataWidth == CVA6Cfg.XLEN ? $clog2( + CVA6Cfg.AxiDataWidth / 8 + ) + 1 : $clog2( + CVA6Cfg.AxiDataWidth / 8 + ); + + logic [DCACHE_NUM_BANKS-1:0] bank_req; + logic [DCACHE_NUM_BANKS-1:0] bank_we; + logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][(CVA6Cfg.XLEN/8)-1:0] bank_be; + logic [DCACHE_NUM_BANKS-1:0][ DCACHE_CL_IDX_WIDTH-1:0] bank_idx; + logic [DCACHE_CL_IDX_WIDTH-1:0] bank_idx_d, bank_idx_q; + logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] bank_off_d, bank_off_q; + + logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] bank_wdata; // + logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] bank_rdata; // + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] rdata_cl; // selected word from each cacheline + logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] bank_wuser; // + logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] bank_ruser; // + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] ruser_cl; // selected word from each cacheline + + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag; + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vld_req; // bit enable for valid regs + logic vld_we; // valid bits write enable + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vld_wdata; // valid bits to write + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_rdata; // these are the tags coming from the tagmem + logic [DCACHE_CL_IDX_WIDTH-1:0] vld_addr; // valid bit + + logic [$clog2(NumPorts)-1:0] vld_sel_d, vld_sel_q; + + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_hit_oh; + logic [(CVA6Cfg.XLEN/8)-1:0] wbuffer_be; + logic [CVA6Cfg.XLEN-1:0] wbuffer_rdata, rdata; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wbuffer_ruser, ruser; + logic [CVA6Cfg.PLEN-1:0] wbuffer_cmp_addr; + + logic cmp_en_d, cmp_en_q; + logic rd_acked; + logic [NumPorts-1:0] bank_collision, rd_req_masked, rd_req_prio; + + /////////////////////////////////////////////////////// + // arbiter + /////////////////////////////////////////////////////// + + // Priority is highest for lowest read port index + // + // SRAM bank mapping: + // + // Bank 0 Bank 2 + // [way0, w0] [way1, w0] .. [way0, w1] [way1, w1] .. + + // byte enable mapping + for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : gen_bank + for (genvar j = 0; j < CVA6Cfg.DCACHE_SET_ASSOC; j++) begin : gen_bank_way + assign bank_be[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_be_i[k*(CVA6Cfg.XLEN/8) +: (CVA6Cfg.XLEN/8)] : + (wr_req_i[j] & wr_ack_o) ? wr_data_be_i : + '0; + assign bank_wdata[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_i[k*CVA6Cfg.XLEN +: CVA6Cfg.XLEN] : + wr_data_i; + assign bank_wuser[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_user_i[k*CVA6Cfg.DCACHE_USER_WIDTH +: CVA6Cfg.DCACHE_USER_WIDTH] : + wr_user_i; + end + end + + assign vld_wdata = wr_vld_bits_i; + assign vld_addr = (wr_cl_vld_i) ? wr_cl_idx_i : rd_idx_i[vld_sel_d]; + assign rd_tag = rd_tag_i[vld_sel_q]; //delayed by one cycle + assign bank_off_d = (wr_cl_vld_i) ? wr_cl_off_i : rd_off_i[vld_sel_d]; + assign bank_idx_d = (wr_cl_vld_i) ? wr_cl_idx_i : rd_idx_i[vld_sel_d]; + assign vld_req = (wr_cl_vld_i) ? wr_cl_we_i : (rd_acked) ? '1 : '0; + + + // priority masking + // disable low prio requests when any of the high prio reqs is present + assign rd_req_prio = rd_req_i & rd_prio_i; + assign rd_req_masked = (|rd_req_prio) ? rd_req_prio : rd_req_i; + + logic rd_req; + rr_arb_tree #( + .NumIn (NumPorts), + .DataWidth(1) + ) i_rr_arb_tree ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (rd_req_masked), + .gnt_o (rd_ack_o), + .data_i ('0), + .gnt_i (~wr_cl_vld_i), + .req_o (rd_req), + .data_o (), + .idx_o (vld_sel_d) + ); + + assign rd_acked = rd_req & ~wr_cl_vld_i; + + always_comb begin : p_bank_req + vld_we = wr_cl_vld_i; + bank_req = '0; + wr_ack_o = '0; + bank_we = '0; + bank_idx = '{default: wr_idx_i}; + + for (int k = 0; k < NumPorts; k++) begin + bank_collision[k] = rd_off_i[k][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES] == wr_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]; + end + + if (wr_cl_vld_i & |wr_cl_we_i) begin + bank_req = '1; + bank_we = '1; + bank_idx = '{default: wr_cl_idx_i}; + end else begin + if (rd_acked) begin + if (!rd_tag_only_i[vld_sel_d]) begin + bank_req = dcache_cl_bin2oh( + rd_off_i[vld_sel_d][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]); + bank_idx[rd_off_i[vld_sel_d][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]] = rd_idx_i[vld_sel_d]; + end + end + + if (|wr_req_i) begin + if (rd_tag_only_i[vld_sel_d] || !(rd_ack_o[vld_sel_d] && bank_collision[vld_sel_d])) begin + wr_ack_o = 1'b1; + bank_req |= dcache_cl_bin2oh( + wr_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES] + ); + bank_we = + dcache_cl_bin2oh(wr_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]); + end + end + end + end + + /////////////////////////////////////////////////////// + // tag comparison, hit generatio, readoud muxes + /////////////////////////////////////////////////////// + + logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES-1:0] wr_cl_off; + logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES-1:0] wr_cl_nc_off; + logic [ $clog2(CVA6Cfg.WtDcacheWbufDepth)-1:0] wbuffer_hit_idx; + logic [ $clog2(CVA6Cfg.DCACHE_SET_ASSOC)-1:0] rd_hit_idx; + + assign cmp_en_d = (|vld_req) & ~vld_we; + + // word tag comparison in write buffer + assign wbuffer_cmp_addr = (wr_cl_vld_i) ? {wr_cl_tag_i, wr_cl_idx_i, wr_cl_off_i} : + {rd_tag, bank_idx_q, bank_off_q}; + // hit generation + for (genvar i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel + // tag comparison of ways >0 + assign rd_hit_oh_o[i] = (rd_tag == tag_rdata[i]) & rd_vld_bits_o[i] & cmp_en_q; + // byte offset mux of ways >0 + assign rdata_cl[i] = bank_rdata[bank_off_q[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]][i]; + assign ruser_cl[i] = bank_ruser[bank_off_q[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]][i]; + end + + for (genvar k = 0; k < CVA6Cfg.WtDcacheWbufDepth; k++) begin : gen_wbuffer_hit + assign wbuffer_hit_oh[k] = (|wbuffer_data_i[k].valid) & ({{CVA6Cfg.XLEN_ALIGN_BYTES{1'b0}}, wbuffer_data_i[k].wtag} == (wbuffer_cmp_addr >> CVA6Cfg.XLEN_ALIGN_BYTES)); + end + + lzc #( + .WIDTH(CVA6Cfg.WtDcacheWbufDepth) + ) i_lzc_wbuffer_hit ( + .in_i (wbuffer_hit_oh), + .cnt_o (wbuffer_hit_idx), + .empty_o() + ); + + lzc #( + .WIDTH(CVA6Cfg.DCACHE_SET_ASSOC) + ) i_lzc_rd_hit ( + .in_i (rd_hit_oh_o), + .cnt_o (rd_hit_idx), + .empty_o() + ); + + assign wbuffer_rdata = wbuffer_data_i[wbuffer_hit_idx].data; + assign wbuffer_ruser = wbuffer_data_i[wbuffer_hit_idx].user; + assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0; + + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset + // In case of an uncached read, return the desired CVA6Cfg.XLEN-bit segment of the most recent AXI read + assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == CVA6Cfg.XLEN) ? '0 : + {{CVA6Cfg.DCACHE_OFFSET_WIDTH-AXI_OFFSET_WIDTH{1'b0}}, wr_cl_off_i[AXI_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]} : + wr_cl_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]; + end else begin : gen_piton_offset + assign wr_cl_off = wr_cl_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3]; + end + + always_comb begin + if (wr_cl_vld_i) begin + rdata = wr_cl_data_i[wr_cl_off*CVA6Cfg.XLEN+:CVA6Cfg.XLEN]; + ruser = wr_cl_user_i[wr_cl_off*CVA6Cfg.DCACHE_USER_WIDTH+:CVA6Cfg.DCACHE_USER_WIDTH]; + end else begin + rdata = rdata_cl[rd_hit_idx]; + ruser = ruser_cl[rd_hit_idx]; + end + end + + // overlay bytes that hit in the write buffer + for (genvar k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin : gen_rd_data + assign rd_data_o[8*k+:8] = (wbuffer_be[k]) ? wbuffer_rdata[8*k+:8] : rdata[8*k+:8]; + end + for (genvar k = 0; k < CVA6Cfg.DCACHE_USER_WIDTH / 8; k++) begin : gen_rd_user + assign rd_user_o[8*k+:8] = (wbuffer_be[k]) ? wbuffer_ruser[8*k+:8] : ruser[8*k+:8]; + end + + /////////////////////////////////////////////////////// + // memory arrays and regs + /////////////////////////////////////////////////////// + + logic [CVA6Cfg.DCACHE_TAG_WIDTH:0] vld_tag_rdata[CVA6Cfg.DCACHE_SET_ASSOC-1:0]; + + for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : gen_data_banks + // Data RAM + sram_cache #( + .USER_WIDTH (CVA6Cfg.DCACHE_SET_ASSOC * CVA6Cfg.DCACHE_USER_WIDTH), + .DATA_WIDTH (CVA6Cfg.DCACHE_SET_ASSOC * CVA6Cfg.XLEN), + .USER_EN (CVA6Cfg.DATA_USER_EN), + .BYTE_ACCESS(1), + .TECHNO_CUT (CVA6Cfg.TechnoCut), + .NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS) + ) i_data_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (bank_req[k]), + .we_i (bank_we[k]), + .addr_i (bank_idx[k]), + .wuser_i(bank_wuser[k]), + .wdata_i(bank_wdata[k]), + .be_i (bank_be[k]), + .ruser_o(bank_ruser[k]), + .rdata_o(bank_rdata[k]) + ); + end + + for (genvar i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin : gen_tag_srams + + assign tag_rdata[i] = vld_tag_rdata[i][CVA6Cfg.DCACHE_TAG_WIDTH-1:0]; + assign rd_vld_bits_o[i] = vld_tag_rdata[i][CVA6Cfg.DCACHE_TAG_WIDTH]; + + // Tag RAM + sram_cache #( + // tag + valid bit + .DATA_WIDTH (CVA6Cfg.DCACHE_TAG_WIDTH + 1), + .BYTE_ACCESS(0), + .TECHNO_CUT (CVA6Cfg.TechnoCut), + .NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS) + ) i_tag_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (vld_req[i]), + .we_i (vld_we), + .addr_i (vld_addr), + .wuser_i('0), + .wdata_i({vld_wdata[i], wr_cl_tag_i}), + .be_i ('1), + .ruser_o(), + .rdata_o(vld_tag_rdata[i]) + ); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + bank_idx_q <= '0; + bank_off_q <= '0; + vld_sel_q <= '0; + cmp_en_q <= '0; + end else begin + bank_idx_q <= bank_idx_d; + bank_off_q <= bank_off_d; + vld_sel_q <= vld_sel_d; + cmp_en_q <= cmp_en_d; + end + end + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + initial begin + cach_line_width_axi : + assert (CVA6Cfg.DCACHE_LINE_WIDTH >= CVA6Cfg.AxiDataWidth) + else $fatal(1, "[l1 dcache] cache line size needs to be greater or equal AXI data width"); + end + + initial begin + axi_xlen : + assert (CVA6Cfg.AxiDataWidth >= CVA6Cfg.XLEN) + else $fatal(1, "[l1 dcache] AXI data width needs to be greater or equal CVA6Cfg.XLEN"); + end + + initial begin + cach_line_width_xlen : + assert (CVA6Cfg.DCACHE_LINE_WIDTH > CVA6Cfg.XLEN) + else $fatal(1, "[l1 dcache] cache_line_size needs to be greater than CVA6Cfg.XLEN"); + end + + hit_hot1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) &vld_req |-> !vld_we |=> $onehot0( + rd_hit_oh_o + )) + else $fatal(1, "[l1 dcache] rd_hit_oh_o signal must be hot1"); + + word_write_hot1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) wr_ack_o |-> $onehot0(wr_req_i)) + else $fatal(1, "[l1 dcache] wr_req_i signal must be hot1"); + + wbuffer_hit_hot1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) &vld_req |-> !vld_we |=> $onehot0( + wbuffer_hit_oh + )) + else $fatal(1, "[l1 dcache] wbuffer_hit_oh signal must be hot1"); + + // this is only used for verification! + logic vld_mirror[CVA6Cfg.DCACHE_NUM_WORDS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0]; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_mirror[CVA6Cfg.DCACHE_NUM_WORDS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0]; + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror + if (!rst_ni) begin + vld_mirror <= '{default: '0}; + tag_mirror <= '{default: '0}; + end else begin + for (int i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin + if (vld_req[i] & vld_we) begin + vld_mirror[vld_addr][i] <= vld_wdata[i]; + tag_mirror[vld_addr][i] <= wr_cl_tag_i; + end + end + end + end + + for (genvar i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin : gen_tag_dubl_test + assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == wr_cl_tag_i) & vld_mirror[vld_addr][i] & (|vld_wdata); + end + + tag_write_duplicate : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) |vld_req |-> vld_we |-> !(|tag_write_duplicate_test)) + else $fatal(1, "[l1 dcache] cannot allocate a CL that is already present in the cache"); + +`endif + //pragma translate_on + +endmodule // wt_dcache_mem diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_missunit.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_missunit.sv new file mode 100644 index 0000000000..5eb202e08e --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_missunit.sv @@ -0,0 +1,648 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: miss controller for WT dcache. Note that the current assumption +// is that the port with the highest index issues writes instead of reads. + + +module wt_dcache_missunit + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter DCACHE_CL_IDX_WIDTH = 0, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, + parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs + parameter int unsigned NumPorts = 4 // number of miss ports +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // cache management, signals from/to core + input logic enable_i, // from CSR + input logic flush_i, // flush request, this waits for pending tx (write, read) to finish and will clear the cache + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a ld/st + // local cache management signals + input logic wbuffer_empty_i, + output logic cache_en_o, // local cache enable signal + // AMO interface + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + // miss handling interface (ld, ptw, wbuffer) + input logic [NumPorts-1:0] miss_req_i, + output logic [NumPorts-1:0] miss_ack_o, + input logic [NumPorts-1:0] miss_nc_i, + input logic [NumPorts-1:0] miss_we_i, + input logic [NumPorts-1:0][CVA6Cfg.XLEN-1:0] miss_wdata_i, + input logic [NumPorts-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_i, + input logic [NumPorts-1:0][CVA6Cfg.PLEN-1:0] miss_paddr_i, + input logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_i, + input logic [NumPorts-1:0][2:0] miss_size_i, + input logic [NumPorts-1:0][CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_i, // used as transaction ID + // signals that the request collided with a pending read + output logic [NumPorts-1:0] miss_replay_o, + // signals response from memory + output logic [NumPorts-1:0] miss_rtrn_vld_o, + output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads + // from writebuffer + input logic [CVA6Cfg.DCACHE_MAX_TX-1:0][CVA6Cfg.PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations + input logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations + // write interface to cache memory + output logic wr_cl_vld_o, // writes a full cacheline + output logic wr_cl_nc_o, // writes a full cacheline + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_cl_we_o, // writes a full cacheline + output logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] wr_cl_tag_o, + output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_o, + output logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_cl_off_o, + output logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] wr_cl_data_o, + output logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user_o, + output logic [CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be_o, + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_vld_bits_o, + // memory interface + input logic mem_rtrn_vld_i, + input dcache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output dcache_req_t mem_data_o +); + + // functions + function automatic logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] dcache_way_bin2oh( + input logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] in); + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + // align the physical address to the specified size: + // 000: bytes + // 001: hword + // 010: word + // 011: dword + // 111: DCACHE line + function automatic logic [CVA6Cfg.PLEN-1:0] paddrSizeAlign(input logic [CVA6Cfg.PLEN-1:0] paddr, + input logic [2:0] size); + logic [CVA6Cfg.PLEN-1:0] out; + out = paddr; + unique case (size) + 3'b001: out[0:0] = '0; + 3'b010: out[1:0] = '0; + 3'b011: out[2:0] = '0; + 3'b111: out[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] = '0; + default: ; + endcase + return out; + endfunction : paddrSizeAlign + + // controller FSM + typedef enum logic [2:0] { + IDLE, + DRAIN, + AMO, + FLUSH, + STORE_WAIT, + LOAD_WAIT, + AMO_WAIT + } state_e; + state_e state_d, state_q; + + // MSHR for reads + typedef struct packed { + logic [CVA6Cfg.PLEN-1:0] paddr; + logic [2:0] size; + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vld_bits; + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] id; + logic nc; + logic [$clog2(CVA6Cfg.DCACHE_SET_ASSOC)-1:0] repl_way; + logic [$clog2(NumPorts)-1:0] miss_port_idx; + } mshr_t; + + mshr_t mshr_d, mshr_q; + logic [$clog2(CVA6Cfg.DCACHE_SET_ASSOC)-1:0] repl_way, inv_way, rnd_way; + logic mshr_vld_d, mshr_vld_q, mshr_vld_q1; + logic mshr_allocate; + logic update_lfsr, all_ways_valid; + + logic enable_d, enable_q; + logic flush_ack_d, flush_ack_q; + logic flush_en, flush_done; + logic mask_reads, lock_reqs; + logic amo_sel, miss_is_write; + logic amo_req_d, amo_req_q; + logic [63:0] amo_rtrn_mux; + logic [CVA6Cfg.XLEN-1:0] amo_data, amo_data_a, amo_data_b; + logic [CVA6Cfg.XLEN-1:0] amo_user; //DCACHE USER ? CVA6Cfg.DCACHE_USER_WIDTH + logic [CVA6Cfg.PLEN-1:0] tmp_paddr; + logic [$clog2(NumPorts)-1:0] miss_port_idx; + logic [DCACHE_CL_IDX_WIDTH-1:0] cnt_d, cnt_q; + logic [NumPorts-1:0] miss_req_masked_d, miss_req_masked_q; + + logic inv_vld, inv_vld_all, cl_write_en; + logic load_ack, store_ack, amo_ack; + + logic [NumPorts-1:0] mshr_rdrd_collision_d, mshr_rdrd_collision_q; + logic [NumPorts-1:0] mshr_rdrd_collision; + logic tx_rdwr_collision, mshr_rdwr_collision; + + /////////////////////////////////////////////////////// + // input arbitration and general control sigs + /////////////////////////////////////////////////////// + + assign cache_en_o = enable_q; + assign cnt_d = (flush_en) ? cnt_q + 1 : '0; + assign flush_done = (cnt_q == CVA6Cfg.DCACHE_NUM_WORDS - 1); + + assign miss_req_masked_d = (lock_reqs) ? miss_req_masked_q : + (mask_reads) ? miss_we_i & miss_req_i : miss_req_i; + assign miss_is_write = miss_we_i[miss_port_idx]; + + // read port arbiter + lzc #( + .WIDTH(NumPorts) + ) i_lzc_reqs ( + .in_i (miss_req_masked_d), + .cnt_o (miss_port_idx), + .empty_o() + ); + + always_comb begin : p_ack + miss_ack_o = '0; + if (!amo_sel) begin + miss_ack_o[miss_port_idx] = mem_data_ack_i & mem_data_req_o; + end + end + + /////////////////////////////////////////////////////// + // MSHR and way replacement logic (only for read ops) + /////////////////////////////////////////////////////// + + // find invalid cache line + lzc #( + .WIDTH(CVA6Cfg.DCACHE_SET_ASSOC) + ) i_lzc_inv ( + .in_i (~miss_vld_bits_i[miss_port_idx]), + .cnt_o (inv_way), + .empty_o(all_ways_valid) + ); + + // generate random cacheline index + lfsr #( + .LfsrWidth(8), + .OutWidth (CVA6Cfg.DCACHE_SET_ASSOC_WIDTH) + ) i_lfsr_inv ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .en_i (update_lfsr), + .out_o (rnd_way) + ); + + assign repl_way = (all_ways_valid) ? rnd_way : inv_way; + + assign mshr_d.size = (mshr_allocate) ? miss_size_i[miss_port_idx] : mshr_q.size; + assign mshr_d.paddr = (mshr_allocate) ? miss_paddr_i[miss_port_idx] : mshr_q.paddr; + assign mshr_d.vld_bits = (mshr_allocate) ? miss_vld_bits_i[miss_port_idx] : mshr_q.vld_bits; + assign mshr_d.id = (mshr_allocate) ? miss_id_i[miss_port_idx] : mshr_q.id; + assign mshr_d.nc = (mshr_allocate) ? miss_nc_i[miss_port_idx] : mshr_q.nc; + assign mshr_d.repl_way = (mshr_allocate) ? repl_way : mshr_q.repl_way; + assign mshr_d.miss_port_idx = (mshr_allocate) ? miss_port_idx : mshr_q.miss_port_idx; + + // currently we only have one outstanding read TX, hence an incoming load clears the MSHR + assign mshr_vld_d = (mshr_allocate) ? 1'b1 : (load_ack) ? 1'b0 : mshr_vld_q; + + assign miss_o = (mshr_allocate) ? ~miss_nc_i[miss_port_idx] : 1'b0; + + + for (genvar k = 0; k < NumPorts; k++) begin : gen_rdrd_collision + assign mshr_rdrd_collision[k] = (mshr_q.paddr[CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] == miss_paddr_i[k][CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]) && (mshr_vld_q | mshr_vld_q1); + assign mshr_rdrd_collision_d[k] = (!miss_req_i[k]) ? 1'b0 : mshr_rdrd_collision_q[k] | mshr_rdrd_collision[k]; + end + + // read/write collision, stalls the corresponding request + // write port[NumPorts-1] collides with MSHR_Q + assign mshr_rdwr_collision = (mshr_q.paddr[CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] == miss_paddr_i[NumPorts-1][CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]) && mshr_vld_q; + + // read collides with inflight TX + always_comb begin : p_tx_coll + tx_rdwr_collision = 1'b0; + for (int k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin + tx_rdwr_collision |= (miss_paddr_i[miss_port_idx][CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] == tx_paddr_i[k][CVA6Cfg.PLEN-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]) && tx_vld_i[k]; + end + end + + /////////////////////////////////////////////////////// + // to memory + /////////////////////////////////////////////////////// + + // if size = 32bit word, select appropriate offset, replicate for openpiton... + + if (CVA6Cfg.RVA) begin + if (CVA6Cfg.IS_XLEN64) begin : gen_amo_64b_data + assign amo_data_a = {amo_req_i.operand_b[0+:32], amo_req_i.operand_b[0+:32]}; + assign amo_data_b = amo_req_i.operand_b; + end else begin : gen_amo_32b_data + assign amo_data_a = amo_req_i.operand_b[0+:32]; + end + end + + always_comb begin + if (CVA6Cfg.RVA) begin + if (CVA6Cfg.IS_XLEN64) begin + if (amo_req_i.size == 2'b10) begin + amo_data = amo_data_a; + end else begin + amo_data = amo_data_b; + end + end else begin + amo_data = amo_data_a; + end + if (CVA6Cfg.DATA_USER_EN) begin + amo_user = amo_data; + end else begin + amo_user = '0; + end + end + end + + if (CVA6Cfg.RVA) begin + // note: openpiton returns a full cacheline! + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux + if (CVA6Cfg.AxiDataWidth > 64) begin + assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2( + CVA6Cfg.AxiDataWidth/8 + )-1:3]*64+:64]; + end else begin + assign amo_rtrn_mux = mem_rtrn_i.data[0+:64]; + end + end else begin : gen_piton_rtrn_mux + assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3]*64+:64]; + end + + // always sign extend 32bit values + assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} : + amo_rtrn_mux ; + assign amo_req_d = amo_req_i.req; + end + + // outgoing memory requests (AMOs are always uncached) + assign mem_data_o.tid = (CVA6Cfg.RVA && amo_sel) ? AmoTxId : miss_id_i[miss_port_idx]; + assign mem_data_o.nc = (CVA6Cfg.RVA && amo_sel) ? 1'b1 : miss_nc_i[miss_port_idx]; + assign mem_data_o.way = (CVA6Cfg.RVA && amo_sel) ? '0 : repl_way; + assign mem_data_o.data = (CVA6Cfg.RVA && amo_sel) ? amo_data : miss_wdata_i[miss_port_idx]; + assign mem_data_o.user = (CVA6Cfg.RVA && amo_sel) ? amo_user : miss_wuser_i[miss_port_idx]; + assign mem_data_o.size = (CVA6Cfg.RVA && amo_sel) ? {1'b0, amo_req_i.size} : miss_size_i [miss_port_idx]; + assign mem_data_o.amo_op = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.amo_op : AMO_NONE; + + assign tmp_paddr = (CVA6Cfg.RVA && amo_sel) ? amo_req_i.operand_a[CVA6Cfg.PLEN-1:0] : miss_paddr_i[miss_port_idx]; + assign mem_data_o.paddr = paddrSizeAlign(tmp_paddr, mem_data_o.size); + + /////////////////////////////////////////////////////// + // back-off mechanism for LR/SC completion guarantee + /////////////////////////////////////////////////////// + + logic sc_fail, sc_pass, sc_backoff_over; + exp_backoff #( + .Seed (3), + .MaxExp(16) + ) i_exp_backoff ( + .clk_i, + .rst_ni, + .set_i (sc_fail), + .clr_i (sc_pass), + .is_zero_o(sc_backoff_over) + ); + + /////////////////////////////////////////////////////// + // responses from memory + /////////////////////////////////////////////////////// + + // keep track of pending stores + logic store_sent; + logic [$clog2(CVA6Cfg.DCACHE_MAX_TX + 1)-1:0] stores_inflight_d, stores_inflight_q; + assign store_sent = mem_data_req_o & mem_data_ack_i & (mem_data_o.rtype == DCACHE_STORE_REQ); + + assign stores_inflight_d = (store_ack && store_sent) ? stores_inflight_q : + (store_ack) ? stores_inflight_q - 1 : + (store_sent) ? stores_inflight_q + 1 : + stores_inflight_q; + + // incoming responses + always_comb begin : p_rtrn_logic + load_ack = 1'b0; + store_ack = 1'b0; + amo_ack = 1'b0; + inv_vld = 1'b0; + inv_vld_all = 1'b0; + sc_fail = 1'b0; + sc_pass = 1'b0; + miss_rtrn_vld_o = '0; + if (mem_rtrn_vld_i) begin + unique case (mem_rtrn_i.rtype) + DCACHE_LOAD_ACK: begin + if (mshr_vld_q) begin + load_ack = 1'b1; + miss_rtrn_vld_o[mshr_q.miss_port_idx] = 1'b1; + end + end + DCACHE_STORE_ACK: begin + if (stores_inflight_q > 0) begin + store_ack = 1'b1; + miss_rtrn_vld_o[NumPorts-1] = 1'b1; + end + end + DCACHE_ATOMIC_ACK: begin + if (CVA6Cfg.RVA) begin + if (amo_req_q) begin + amo_ack = 1'b1; + // need to set SC backoff counter if + // this op failed + if (amo_req_i.amo_op == AMO_SC) begin + if (amo_resp_o.result > 0) begin + sc_fail = 1'b1; + end else begin + sc_pass = 1'b1; + end + end + end + end + end + DCACHE_INV_REQ: begin + inv_vld = mem_rtrn_i.inv.vld | mem_rtrn_i.inv.all; + inv_vld_all = mem_rtrn_i.inv.all; + end + // TODO: + // DCACHE_INT_REQ: begin + // end + default: begin + end + endcase + end + end + + // to write buffer + assign miss_rtrn_id_o = mem_rtrn_i.tid; + + /////////////////////////////////////////////////////// + // writes to cache memory + /////////////////////////////////////////////////////// + + // cacheline write port + assign wr_cl_nc_o = mshr_q.nc; + assign wr_cl_vld_o = load_ack | (|wr_cl_we_o); + + assign wr_cl_we_o = (flush_en) ? '1 : (inv_vld_all) ? '1 : (inv_vld) ? dcache_way_bin2oh( + mem_rtrn_i.inv.way + ) : (cl_write_en) ? dcache_way_bin2oh( + mshr_q.repl_way + ) : '0; + + assign wr_vld_bits_o = (flush_en) ? '0 : (inv_vld) ? '0 : (cl_write_en) ? dcache_way_bin2oh( + mshr_q.repl_way + ) : '0; + + assign wr_cl_idx_o = (flush_en) ? cnt_q : + (inv_vld) ? mem_rtrn_i.inv.idx[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] : + mshr_q.paddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]; + + assign wr_cl_tag_o = mshr_q.paddr[CVA6Cfg.DCACHE_TAG_WIDTH+CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_INDEX_WIDTH]; + assign wr_cl_off_o = mshr_q.paddr[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0]; + assign wr_cl_data_o = mem_rtrn_i.data; + assign wr_cl_user_o = mem_rtrn_i.user; + assign wr_cl_data_be_o = (cl_write_en) ? '1 : '0;// we only write complete cachelines into the memory + + // only non-NC responses write to the cache + assign cl_write_en = load_ack & ~mshr_q.nc; + + /////////////////////////////////////////////////////// + // main control logic for generating tx + /////////////////////////////////////////////////////// + + always_comb begin : p_fsm + // default assignment + state_d = state_q; + + flush_ack_o = 1'b0; + mem_data_o.rtype = DCACHE_LOAD_REQ; + mem_data_req_o = 1'b0; + amo_resp_o.ack = 1'b0; + miss_replay_o = '0; + + // disabling cache is possible anytime, enabling goes via flush + enable_d = enable_q & enable_i; + flush_ack_d = flush_ack_q; + flush_en = 1'b0; + amo_sel = 1'b0; + update_lfsr = 1'b0; + mshr_allocate = 1'b0; + lock_reqs = 1'b0; + mask_reads = mshr_vld_q; + + // interfaces + unique case (state_q) + ////////////////////////////////// + // wait for misses / amo ops + IDLE: begin + if (flush_i || (enable_i && !enable_q)) begin + if (wbuffer_empty_i && !mshr_vld_q) begin + flush_ack_d = flush_i; + state_d = FLUSH; + end else begin + state_d = DRAIN; + end + end else if (CVA6Cfg.RVA && amo_req_i.req) begin + if (wbuffer_empty_i && !mshr_vld_q) begin + state_d = AMO; + end else begin + state_d = DRAIN; + end + // we've got a miss to handle + end else if (|miss_req_masked_d) begin + // this is a write miss, just pass through (but check whether write collides with MSHR) + if (miss_is_write) begin + // stall in case this write collides with the MSHR address + if (!mshr_rdwr_collision) begin + mem_data_req_o = 1'b1; + mem_data_o.rtype = DCACHE_STORE_REQ; + if (!mem_data_ack_i) begin + state_d = STORE_WAIT; + end + end + // this is a read miss, can only allocate 1 MSHR + // in case of a load_ack we can accept a new miss, since the MSHR is being cleared + end else if (!mshr_vld_q || load_ack) begin + // replay the read request in case the address has collided with MSHR during the time the request was pending + // i.e., the cache state may have been updated in the mean time due to a refill at the same CL address + if (mshr_rdrd_collision_d[miss_port_idx]) begin + miss_replay_o[miss_port_idx] = 1'b1; + // stall in case this CL address overlaps with a write TX that is in flight + end else if (!tx_rdwr_collision) begin + mem_data_req_o = 1'b1; + mem_data_o.rtype = DCACHE_LOAD_REQ; + update_lfsr = all_ways_valid & mem_data_ack_i; // need to evict a random way + mshr_allocate = mem_data_ack_i; + if (!mem_data_ack_i) begin + state_d = LOAD_WAIT; + end + end + end + end + end + ////////////////////////////////// + // wait until this request is acked + STORE_WAIT: begin + lock_reqs = 1'b1; + mem_data_req_o = 1'b1; + mem_data_o.rtype = DCACHE_STORE_REQ; + if (mem_data_ack_i) begin + state_d = IDLE; + end + end + ////////////////////////////////// + // wait until this request is acked + LOAD_WAIT: begin + lock_reqs = 1'b1; + mem_data_req_o = 1'b1; + mem_data_o.rtype = DCACHE_LOAD_REQ; + if (mem_data_ack_i) begin + update_lfsr = all_ways_valid; // need to evict a random way + mshr_allocate = 1'b1; + state_d = IDLE; + end + end + ////////////////////////////////// + // only handle stores, do not accept new read requests + // wait until MSHR is cleared and wbuffer is empty + DRAIN: begin + mask_reads = 1'b1; + // these are writes, check whether they collide with MSHR + if (|miss_req_masked_d && !mshr_rdwr_collision) begin + mem_data_req_o = 1'b1; + mem_data_o.rtype = DCACHE_STORE_REQ; + end + + if (wbuffer_empty_i && !mshr_vld_q) begin + state_d = IDLE; + end + end + ////////////////////////////////// + // flush the cache + FLUSH: begin + // internal flush signal + flush_en = 1'b1; + if (flush_done) begin + state_d = IDLE; + flush_ack_o = flush_ack_q; + flush_ack_d = 1'b0; + enable_d = enable_i; + end + end + ////////////////////////////////// + // send out amo op request + AMO: begin + if (CVA6Cfg.RVA) begin + mem_data_o.rtype = DCACHE_ATOMIC_REQ; + amo_sel = 1'b1; + // if this is an LR, we need to consult the backoff counter + if ((amo_req_i.amo_op != AMO_LR) || sc_backoff_over) begin + mem_data_req_o = 1'b1; + if (mem_data_ack_i) begin + state_d = AMO_WAIT; + end + end + end + end + ////////////////////////////////// + // block and wait until AMO OP returns + AMO_WAIT: begin + if (CVA6Cfg.RVA) begin + amo_sel = 1'b1; + if (amo_ack) begin + amo_resp_o.ack = 1'b1; + state_d = IDLE; + end + end + end + ////////////////////////////////// + default: begin + // we should never get here + state_d = IDLE; + end + endcase // state_q + end + + /////////////////////////////////////////////////////// + // ff's + /////////////////////////////////////////////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + state_q <= FLUSH; + cnt_q <= '0; + enable_q <= '0; + flush_ack_q <= '0; + mshr_vld_q <= '0; + mshr_vld_q1 <= '0; + mshr_q <= '0; + mshr_rdrd_collision_q <= '0; + miss_req_masked_q <= '0; + amo_req_q <= '0; + stores_inflight_q <= '0; + end else begin + state_q <= state_d; + cnt_q <= cnt_d; + enable_q <= enable_d; + flush_ack_q <= flush_ack_d; + mshr_vld_q <= mshr_vld_d; + mshr_vld_q1 <= mshr_vld_q; + mshr_q <= mshr_d; + mshr_rdrd_collision_q <= mshr_rdrd_collision_d; + miss_req_masked_q <= miss_req_masked_d; + amo_req_q <= amo_req_d; + stores_inflight_q <= stores_inflight_d; + end + end + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + + read_tid : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) mshr_vld_q |-> mem_rtrn_vld_i |-> load_ack |-> mem_rtrn_i.tid == mshr_q.id) + else $fatal(1, "[l1 dcache missunit] TID of load response doesn't match"); + + read_ports : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) |miss_req_i[NumPorts-2:0] |-> miss_we_i[NumPorts-2:0] == 0) + else $fatal(1, "[l1 dcache missunit] only last port can issue write requests"); + + write_port : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) miss_req_i[NumPorts-1] |-> miss_we_i[NumPorts-1]) + else $fatal(1, "[l1 dcache missunit] last port can only issue write requests"); + + initial begin + // assert wrong parameterizations + assert (NumPorts >= 2) + else + $fatal( + 1, "[l1 dcache missunit] at least two ports are required (one read port, one write port)" + ); + end +`endif + //pragma translate_on + +endmodule // wt_dcache_missunit diff --git a/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv new file mode 100644 index 0000000000..ef3a62ef33 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -0,0 +1,697 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: coalescing write buffer for WT dcache +// +// A couple of notes: +// +// 1) the write buffer behaves as a fully-associative cache, and is therefore coalescing. +// this cache is used by the cache readout logic to forward data to the load unit. +// +// each byte can be in the following states (valid/dirty/txblock): +// +// 0/0/0: invalid -> free entry in the buffer +// 1/1/0: valid and dirty, Byte is hence not part of TX in-flight +// 1/0/1: valid and not dirty, Byte is part of a TX in-flight +// 1/1/1: valid and, part of tx and dirty. this means that the byte has been +// overwritten while in TX and needs to be retransmitted once the write of that byte returns. +// 1/0/0: this would represent a clean state, but is never reached in the wbuffer in the current implementation. +// this is because when a TX returns, and the byte is in state [1/0/1], it is written to cache if needed and +// its state is immediately cleared to 0/x/x. +// +// this state is used to distinguish between bytes that have been written and not +// yet sent to the memory subsystem, and bytes that are part of a transaction. +// +// 2) further, each word in the write buffer has a cache states (checked, hit_oh) +// +// checked == 0: unknown cache state +// checked == 1: cache state has been looked up, valid way is stored in "hit_oh" +// +// cache invalidations/refills affecting a particular word will clear its word state to 0, +// so another lookup has to be done. note that these lookups are triggered as soon as there is +// a valid word with checked == 0 in the write buffer. +// +// 3) returning write ACKs trigger a cache update if the word is present in the cache, and evict that +// word from the write buffer. if the word is not allocated to the cache, it is just evicted from the write buffer. +// if the word cache state is VOID, the pipeline is stalled until it is clear whether that word is in the cache or not. +// +// 4) we handle NC writes using the writebuffer circuitry. upon an NC request, the writebuffer will first be drained. +// then, only the NC word is written into the write buffer and no further write requests are acknowledged until that +// word has been evicted from the write buffer. + + +module wt_dcache_wbuffer + import ariane_pkg::*; + import wt_cache_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter DCACHE_CL_IDX_WIDTH = 0, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type wbuffer_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + input logic cache_en_i, // writes are treated as NC if disabled + output logic empty_o, // asserted if no data is present in write buffer + output logic not_ni_o, // asserted if no ni data is present in write buffer + // core request ports + input dcache_req_i_t req_port_i, + output dcache_req_o_t req_port_o, + // interface to miss handler + input logic miss_ack_i, + output logic [CVA6Cfg.PLEN-1:0] miss_paddr_o, + output logic miss_req_o, + output logic miss_we_o, // always 1 here + output logic [CVA6Cfg.XLEN-1:0] miss_wdata_o, + output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_o, + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // unused here (set to 0) + output logic miss_nc_o, // request to I/O space + output logic [2:0] miss_size_o, // + output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_o, // ID of this transaction (wbuffer uses all IDs from 0 to DCACHE_MAX_TX-1) + // write responses from memory + input logic miss_rtrn_vld_i, + input logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_i, // transaction ID to clear + // cache read interface + output logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag_o, // tag in - comes one cycle later + output logic [DCACHE_CL_IDX_WIDTH-1:0] rd_idx_o, + output logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] rd_off_o, + output logic rd_req_o, // read the word at offset off_i[:3] in all ways + output logic rd_tag_only_o, // set to 1 here as we do not have to read the data arrays + input logic rd_ack_i, + input logic [CVA6Cfg.XLEN-1:0] rd_data_i, // unused + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, // unused + input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_i, + // cacheline writes + input logic wr_cl_vld_i, + input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_i, + // cache word write interface + output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_req_o, + input logic wr_ack_i, + output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_o, + output logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off_o, + output logic [CVA6Cfg.XLEN-1:0] wr_data_o, + output logic [(CVA6Cfg.XLEN/8)-1:0] wr_data_be_o, + output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user_o, + // to forwarding logic and miss unit + output wbuffer_t [CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_data_o, + output logic [CVA6Cfg.DCACHE_MAX_TX-1:0][CVA6Cfg.PLEN-1:0] tx_paddr_o, // used to check for address collisions with read operations + output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o +); + + function automatic logic [(CVA6Cfg.XLEN/8)-1:0] to_byte_enable8( + input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); + logic [(CVA6Cfg.XLEN/8)-1:0] be; + be = '0; + unique case (size) + 2'b00: be[offset] = '1; // byte + 2'b01: be[offset+:2] = '1; // hword + 2'b10: be[offset+:4] = '1; // word + default: be = '1; // dword + endcase // size + return be; + endfunction : to_byte_enable8 + + function automatic logic [(CVA6Cfg.XLEN/8)-1:0] to_byte_enable4( + input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); + logic [3:0] be; + be = '0; + unique case (size) + 2'b00: be[offset] = '1; // byte + 2'b01: be[offset+:2] = '1; // hword + default: be = '1; // word + endcase // size + return be; + endfunction : to_byte_enable4 + + // openpiton requires the data to be replicated in case of smaller sizes than dwords + function automatic logic [CVA6Cfg.XLEN-1:0] repData64( + input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, + input logic [1:0] size); + logic [CVA6Cfg.XLEN-1:0] out; + unique case (size) + 2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte + 2'b01: for (int k = 0; k < 4; k++) out[k*16+:16] = data[offset*8+:16]; // hword + 2'b10: for (int k = 0; k < 2; k++) out[k*32+:32] = data[offset*8+:32]; // word + default: out = data; // dword + endcase // size + return out; + endfunction : repData64 + + function automatic logic [CVA6Cfg.XLEN-1:0] repData32( + input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, + input logic [1:0] size); + logic [CVA6Cfg.XLEN-1:0] out; + unique case (size) + 2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte + 2'b01: for (int k = 0; k < 2; k++) out[k*16+:16] = data[offset*8+:16]; // hword + default: out = data; // word + endcase // size + return out; + endfunction : repData32 + + typedef struct packed { + logic vld; + logic [(CVA6Cfg.XLEN/8)-1:0] be; + logic [$clog2(CVA6Cfg.WtDcacheWbufDepth)-1:0] ptr; + } tx_stat_t; + + tx_stat_t [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q; + wbuffer_t [CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_d, wbuffer_q; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] valid; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] dirty; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] tocheck; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_hit_oh, inval_hit; + //logic [CVA6Cfg.WtDcacheWbufDepth-1:0][7:0] bdirty; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0][(CVA6Cfg.XLEN/8)-1:0] bdirty; + + logic [$clog2(CVA6Cfg.WtDcacheWbufDepth)-1:0] + next_ptr, dirty_ptr, hit_ptr, wr_ptr, check_ptr_d, check_ptr_q, check_ptr_q1, rtrn_ptr; + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tx_id, rtrn_id; + + logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] bdirty_off; + logic [(CVA6Cfg.XLEN/8)-1:0] tx_be; + logic [CVA6Cfg.PLEN-1:0] wr_paddr, rd_paddr, extract_tag; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag_d, rd_tag_q; + logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_d, rd_hit_oh_q; + logic check_en_d, check_en_q, check_en_q1; + logic full, dirty_rd_en, rdy; + logic rtrn_empty, evict; + logic [CVA6Cfg.WtDcacheWbufDepth-1:0] ni_pending_d, ni_pending_q; + logic wbuffer_wren; + logic free_tx_slots; + + logic wr_cl_vld_q, wr_cl_vld_d; + logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_q, wr_cl_idx_d; + + logic [CVA6Cfg.PLEN-1:0] debug_paddr[CVA6Cfg.WtDcacheWbufDepth-1:0]; + + wbuffer_t wbuffer_check_mux, wbuffer_dirty_mux; + + /////////////////////////////////////////////////////// + // misc + /////////////////////////////////////////////////////// + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] miss_tag; + logic is_nc_miss; + logic is_ni; + assign miss_tag = miss_paddr_o[CVA6Cfg.DCACHE_INDEX_WIDTH+:CVA6Cfg.DCACHE_TAG_WIDTH]; + assign is_nc_miss = !config_pkg::is_inside_cacheable_regions( + CVA6Cfg, + { + {64 - CVA6Cfg.DCACHE_TAG_WIDTH - CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}, + miss_tag, + {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}} + } + ); + assign miss_nc_o = !cache_en_i || is_nc_miss; + // Non-idempotent if request goes to NI region + assign is_ni = config_pkg::is_inside_nonidempotent_regions( + CVA6Cfg, + { + {64 - CVA6Cfg.DCACHE_TAG_WIDTH - CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}, + req_port_i.address_tag, + {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}} + } + ); + + assign miss_we_o = 1'b1; + assign miss_vld_bits_o = '0; + assign wbuffer_data_o = wbuffer_q; + + for (genvar k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin : gen_tx_vld + assign tx_vld_o[k] = tx_stat_q[k].vld; + assign tx_paddr_o[k] = { + {CVA6Cfg.XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << CVA6Cfg.XLEN_ALIGN_BYTES + }; + end + + /////////////////////////////////////////////////////// + // openpiton does not understand byte enable sigs + // need to convert to the four cases: + // 00: byte + // 01: halfword + // 10: word + // 11: dword + // non-contiguous writes need to be serialized! + // e.g. merged dwords with BE like this: 8'b01001100 + /////////////////////////////////////////////////////// + + // get byte offset + lzc #( + .WIDTH(CVA6Cfg.XLEN / 8) + ) i_vld_bdirty ( + .in_i (bdirty[dirty_ptr]), + .cnt_o (bdirty_off), + .empty_o() + ); + + // add the offset to the physical base address of this buffer entry + assign miss_paddr_o = {wbuffer_dirty_mux.wtag, bdirty_off}; + assign miss_id_o = tx_id; + + // is there any dirty word to be transmitted, and is there a free TX slot? + assign miss_req_o = (|dirty) && free_tx_slots; + + // get size of aligned words, and the corresponding byte enables + // note: openpiton can only handle aligned offsets + size, and hence + // we have to split unaligned data into multiple transfers (see toSize64) + // e.g. if we have the following valid bytes: 0011_1001 -> TX0: 0000_0001, TX1: 0000_1000, TX2: 0011_0000 + if (CVA6Cfg.IS_XLEN64) begin : gen_size_64b + assign miss_size_o = {1'b0, toSize64(bdirty[dirty_ptr])}; + end else begin : gen_size_32b + assign miss_size_o = {1'b0, toSize32(bdirty[dirty_ptr])}; + end + + // replicate transfers shorter than a dword + assign miss_wdata_o = CVA6Cfg.IS_XLEN64 ? repData64( + wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0] + ) : repData32( + wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0] + ); + if (CVA6Cfg.DATA_USER_EN) begin + assign miss_wuser_o = CVA6Cfg.IS_XLEN64 ? repData64( + wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0] + ) : repData32( + wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0] + ); + end else begin + assign miss_wuser_o = '0; + end + + assign tx_be = CVA6Cfg.IS_XLEN64 ? to_byte_enable8( + bdirty_off, miss_size_o[1:0] + ) : to_byte_enable4( + bdirty_off, miss_size_o[1:0] + ); + + /////////////////////////////////////////////////////// + // TX status registers and ID counters + /////////////////////////////////////////////////////// + + // TODO: todo: make this fall through if timing permits it + cva6_fifo_v3 #( + .FALL_THROUGH(1'b0), + .DATA_WIDTH ($clog2(CVA6Cfg.DCACHE_MAX_TX)), + .DEPTH (CVA6Cfg.DCACHE_MAX_TX), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_rtrn_id_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .testmode_i(1'b0), + .full_o (), + .empty_o (rtrn_empty), + .usage_o (), + .data_i (miss_rtrn_id_i), + .push_i (miss_rtrn_vld_i), + .data_o (rtrn_id), + .pop_i (evict) + ); + + always_comb begin : p_tx_stat + tx_stat_d = tx_stat_q; + evict = 1'b0; + wr_req_o = '0; + + // clear entry if it is clear whether it can be pushed to the cache or not + if ((!rtrn_empty) && wbuffer_q[rtrn_ptr].checked) begin + // check if data is clean and can be written, otherwise skip + // check if CL is present, otherwise skip + if ((|wr_data_be_o) && (|wbuffer_q[rtrn_ptr].hit_oh)) begin + wr_req_o = wbuffer_q[rtrn_ptr].hit_oh; + if (wr_ack_i) begin + evict = 1'b1; + tx_stat_d[rtrn_id].vld = 1'b0; + end + end else begin + evict = 1'b1; + tx_stat_d[rtrn_id].vld = 1'b0; + end + end + + // allocate a new entry + if (dirty_rd_en) begin + tx_stat_d[tx_id].vld = 1'b1; + tx_stat_d[tx_id].ptr = dirty_ptr; + tx_stat_d[tx_id].be = tx_be; + end + end + + assign free_tx_slots = |(~tx_vld_o); + + // next word to lookup in the cache + rr_arb_tree #( + .NumIn (CVA6Cfg.DCACHE_MAX_TX), + .LockIn (1'b1), + .DataWidth(1) + ) i_tx_id_rr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (~tx_vld_o), + .gnt_o (), + .data_i ('0), + .gnt_i (dirty_rd_en), + .req_o (), + .data_o (), + .idx_o (tx_id) + ); + + /////////////////////////////////////////////////////// + // cache readout & update + /////////////////////////////////////////////////////// + + assign extract_tag = rd_paddr >> CVA6Cfg.DCACHE_INDEX_WIDTH; + assign rd_tag_d = extract_tag[CVA6Cfg.DCACHE_TAG_WIDTH-1:0]; + + // trigger TAG readout in cache + assign rd_tag_only_o = 1'b1; + assign rd_paddr = { + {CVA6Cfg.XLEN_ALIGN_BYTES{1'b0}}, wbuffer_check_mux.wtag << CVA6Cfg.XLEN_ALIGN_BYTES + }; + assign rd_req_o = |tocheck; + assign rd_tag_o = rd_tag_q; //delay by one cycle + assign rd_idx_o = rd_paddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]; + assign rd_off_o = rd_paddr[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0]; + assign check_en_d = rd_req_o & rd_ack_i; + + // cache update port + assign rtrn_ptr = tx_stat_q[rtrn_id].ptr; + // if we wrote into a word while it was in-flight, we cannot write the dirty bytes to the cache + // when the TX returns + assign wr_data_be_o = tx_stat_q[rtrn_id].be & (~wbuffer_q[rtrn_ptr].dirty); + assign wr_paddr = { + {CVA6Cfg.XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[rtrn_ptr].wtag << CVA6Cfg.XLEN_ALIGN_BYTES + }; + assign wr_idx_o = wr_paddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH]; + assign wr_off_o = wr_paddr[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0]; + assign wr_data_o = wbuffer_q[rtrn_ptr].data; + assign wr_user_o = wbuffer_q[rtrn_ptr].user; + + + /////////////////////////////////////////////////////// + // readout of status bits, index calculation + /////////////////////////////////////////////////////// + + logic [CVA6Cfg.WtDcacheWbufDepth-1:0][DCACHE_CL_IDX_WIDTH-1:0] wtag_comp; + + assign wr_cl_vld_d = wr_cl_vld_i; + assign wr_cl_idx_d = wr_cl_idx_i; + + for (genvar k = 0; k < CVA6Cfg.WtDcacheWbufDepth; k++) begin : gen_flags + // only for debug, will be pruned + if (CVA6Cfg.DebugEn) begin + assign debug_paddr[k] = { + {CVA6Cfg.XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << CVA6Cfg.XLEN_ALIGN_BYTES + }; + end + + // dirty bytes that are ready for transmission. + // note that we cannot retransmit a word that is already in-flight + // since the multiple transactions might overtake each other in the memory system! + assign bdirty[k] = (|wbuffer_q[k].txblock) ? '0 : wbuffer_q[k].dirty & wbuffer_q[k].valid; + + + assign dirty[k] = |bdirty[k]; + assign valid[k] = |wbuffer_q[k].valid; + assign wbuffer_hit_oh[k] = valid[k] & (wbuffer_q[k].wtag == {req_port_i.address_tag, req_port_i.address_index[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]}); + + // checks if an invalidation/cache refill hits a particular word + // note: an invalidation can hit multiple words! + // need to respect previous cycle, too, since we add a cycle of latency to the rd_hit_oh_i signal... + assign wtag_comp[k] = wbuffer_q[k].wtag[CVA6Cfg.DCACHE_INDEX_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES-1:CVA6Cfg.DCACHE_OFFSET_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES]; + assign inval_hit[k] = (wr_cl_vld_d & valid[k] & (wtag_comp[k] == wr_cl_idx_d)) | + (wr_cl_vld_q & valid[k] & (wtag_comp[k] == wr_cl_idx_q)); + + // these word have to be looked up in the cache + assign tocheck[k] = (~wbuffer_q[k].checked) & valid[k]; + end + + assign wr_ptr = (|wbuffer_hit_oh) ? hit_ptr : next_ptr; + assign rdy = (|wbuffer_hit_oh) | (~full); + + // next free entry in the buffer + lzc #( + .WIDTH(CVA6Cfg.WtDcacheWbufDepth) + ) i_vld_lzc ( + .in_i (~valid), + .cnt_o (next_ptr), + .empty_o(full) + ); + + // get index of hit + lzc #( + .WIDTH(CVA6Cfg.WtDcacheWbufDepth) + ) i_hit_lzc ( + .in_i (wbuffer_hit_oh), + .cnt_o (hit_ptr), + .empty_o() + ); + + // next dirty word to serve + rr_arb_tree #( + .NumIn (CVA6Cfg.WtDcacheWbufDepth), + .LockIn (1'b1), + .DataType(wbuffer_t) + ) i_dirty_rr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (dirty), + .gnt_o (), + .data_i (wbuffer_q), + .gnt_i (dirty_rd_en), + .req_o (), + .data_o (wbuffer_dirty_mux), + .idx_o (dirty_ptr) + ); + + // next word to lookup in the cache + rr_arb_tree #( + .NumIn (CVA6Cfg.WtDcacheWbufDepth), + .DataType(wbuffer_t) + ) i_clean_rr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (tocheck), + .gnt_o (), + .data_i (wbuffer_q), + .gnt_i (check_en_d), + .req_o (), + .data_o (wbuffer_check_mux), + .idx_o (check_ptr_d) + ); + + /////////////////////////////////////////////////////// + // update logic + /////////////////////////////////////////////////////// + + assign req_port_o.data_rvalid = '0; + assign req_port_o.data_rdata = '0; + assign req_port_o.data_ruser = '0; + assign req_port_o.data_rid = '0; + + assign rd_hit_oh_d = rd_hit_oh_i; + + logic ni_inside, ni_conflict; + assign ni_inside = |ni_pending_q; + assign ni_conflict = CVA6Cfg.NonIdemPotenceEn && is_ni && ni_inside; + assign not_ni_o = !ni_inside; + assign empty_o = !(|valid); + + // TODO: rewrite and separate into MUXES and write strobe logic + always_comb begin : p_buffer + wbuffer_d = wbuffer_q; + ni_pending_d = ni_pending_q; + dirty_rd_en = 1'b0; + req_port_o.data_gnt = 1'b0; + wbuffer_wren = 1'b0; + + // TAG lookup returns, mark corresponding word + if (check_en_q1) begin + if (|wbuffer_q[check_ptr_q1].valid) begin + wbuffer_d[check_ptr_q1].checked = 1'b1; + wbuffer_d[check_ptr_q1].hit_oh = rd_hit_oh_q; + end + end + + // if an invalidation or cache line refill comes in and hits on the write buffer, + // we have to discard our knowledge of the corresponding cacheline state + for (int k = 0; k < CVA6Cfg.WtDcacheWbufDepth; k++) begin + if (inval_hit[k]) begin + wbuffer_d[k].checked = 1'b0; + end + end + + // once TX write response came back, we can clear the TX block. if it was not dirty, we + // can completely evict it - otherwise we have to leave it there for retransmission + if (evict) begin + for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin + if (tx_stat_q[rtrn_id].be[k]) begin + wbuffer_d[rtrn_ptr].txblock[k] = 1'b0; + if (!wbuffer_q[rtrn_ptr].dirty[k]) begin + wbuffer_d[rtrn_ptr].valid[k] = 1'b0; + + // NOTE: this is not strictly needed, but makes it much + // easier to debug, since no invalid data remains in the buffer + // wbuffer_d[rtrn_ptr].data[k*8 +:8] = '0; + end + end + end + // if all bytes are evicted, clear the cache status flag + if (wbuffer_d[rtrn_ptr].valid == 0) begin + wbuffer_d[rtrn_ptr].checked = 1'b0; + ni_pending_d[rtrn_ptr] = 1'b0; + end + end + + // mark bytes sent out to the memory system + if (miss_req_o && miss_ack_i) begin + dirty_rd_en = 1'b1; + for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin + if (tx_be[k]) begin + wbuffer_d[dirty_ptr].dirty[k] = 1'b0; + wbuffer_d[dirty_ptr].txblock[k] = 1'b1; + end + end + end + + // write new word into the buffer + if (req_port_i.data_req && rdy) begin + // in case we have an NI address, need to drain the buffer first + // in case we are serving an NI address, we block until it is written to memory + if (!ni_conflict) begin //empty of NI operations + wbuffer_wren = 1'b1; + + req_port_o.data_gnt = 1'b1; + ni_pending_d[wr_ptr] = is_ni; + + wbuffer_d[wr_ptr].checked = 1'b0; + wbuffer_d[wr_ptr].wtag = { + req_port_i.address_tag, + req_port_i.address_index[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES] + }; + + // mark bytes as dirty + for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin + if (req_port_i.data_be[k]) begin + wbuffer_d[wr_ptr].valid[k] = 1'b1; + wbuffer_d[wr_ptr].dirty[k] = 1'b1; + wbuffer_d[wr_ptr].data[k*8+:8] = req_port_i.data_wdata[k*8+:8]; + if (CVA6Cfg.DATA_USER_EN) begin + wbuffer_d[wr_ptr].user[k*8+:8] = req_port_i.data_wuser[k*8+:8]; + end + end + end + end + end + end + + + /////////////////////////////////////////////////////// + // ff's + /////////////////////////////////////////////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + wbuffer_q <= '{default: '0}; + tx_stat_q <= '{default: '0}; + ni_pending_q <= '0; + check_ptr_q <= '0; + check_ptr_q1 <= '0; + check_en_q <= '0; + check_en_q1 <= '0; + rd_tag_q <= '0; + rd_hit_oh_q <= '0; + wr_cl_vld_q <= '0; + wr_cl_idx_q <= '0; + end else begin + wbuffer_q <= wbuffer_d; + tx_stat_q <= tx_stat_d; + ni_pending_q <= ni_pending_d; + check_ptr_q <= check_ptr_d; + check_ptr_q1 <= check_ptr_q; + check_en_q <= check_en_d; + check_en_q1 <= check_en_q; + rd_tag_q <= rd_tag_d; + rd_hit_oh_q <= rd_hit_oh_d; + wr_cl_vld_q <= wr_cl_vld_d; + wr_cl_idx_q <= wr_cl_idx_d; + end + end + + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off +`ifndef VERILATOR + + hot1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) req_port_i.data_req |-> $onehot0( + wbuffer_hit_oh + )) + else $fatal(1, "[l1 dcache wbuffer] wbuffer_hit_oh signal must be hot1"); + + tx_status : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) evict && miss_ack_i && miss_req_o |-> (tx_id != rtrn_id)) + else $fatal(1, "[l1 dcache wbuffer] cannot allocate and clear same tx slot id in the same cycle"); + + tx_valid0 : + assert property (@(posedge clk_i) disable iff (!rst_ni) evict |-> tx_stat_q[rtrn_id].vld) + else $fatal(1, "[l1 dcache wbuffer] evicting invalid transaction slot"); + + tx_valid1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) evict |-> |wbuffer_q[rtrn_ptr].valid) + else $fatal(1, "[l1 dcache wbuffer] wbuffer entry corresponding to this transaction is invalid"); + + write_full : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) req_port_i.data_req |-> req_port_o.data_gnt |-> ((!full) || (|wbuffer_hit_oh))) + else $fatal(1, "[l1 dcache wbuffer] cannot write if full or no hit"); + + unused0 : + assert property (@(posedge clk_i) disable iff (!rst_ni) !req_port_i.tag_valid) + else $fatal(1, "[l1 dcache wbuffer] req_port_i.tag_valid should not be asserted"); + + unused1 : + assert property (@(posedge clk_i) disable iff (!rst_ni) !req_port_i.kill_req) + else $fatal(1, "[l1 dcache wbuffer] req_port_i.kill_req should not be asserted"); + + for (genvar k = 0; k < CVA6Cfg.WtDcacheWbufDepth; k++) begin : gen_assert1 + for (genvar j = 0; j < (CVA6Cfg.XLEN / 8); j++) begin : gen_assert2 + byteStates : + assert property ( + @(posedge clk_i) disable iff (!rst_ni) {wbuffer_q[k].valid[j], wbuffer_q[k].dirty[j], wbuffer_q[k].txblock[j]} inside {3'b000, 3'b110, 3'b101, 3'b111} ) + else + $fatal( + 1, + "[l1 dcache wbuffer] byte %02d of wbuffer entry %02d has invalid state: valid=%01b, dirty=%01b, txblock=%01b", + j, + k, + wbuffer_q[k].valid[j], + wbuffer_q[k].dirty[j], + wbuffer_q[k].txblock[j] + ); + end + end +`endif + //pragma translate_on + +endmodule // wt_dcache_wbuffer diff --git a/flow/designs/src/cva6/core/commit_stage.sv b/flow/designs/src/cva6/core/commit_stage.sv new file mode 100644 index 0000000000..d41c6b5a30 --- /dev/null +++ b/flow/designs/src/cva6/core/commit_stage.sv @@ -0,0 +1,406 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 15.04.2017 +// Description: Commits to the architectural state resulting from the scoreboard. + + +module commit_stage + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, + parameter type scoreboard_entry_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Request to halt the core - CONTROLLER + input logic halt_i, + // request to flush dcache, also flush the pipeline - CACHE + input logic flush_dcache_i, + // TO_BE_COMPLETED - EX_STAGE + output exception_t exception_o, + // Mark the F state as dirty - CSR_REGFILE + output logic dirty_fp_state_o, + // TO_BE_COMPLETED - CSR_REGFILE + input logic single_step_i, + // The instruction we want to commit - ISSUE_STAGE + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + // The instruction is cancelled - ISSUE_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_i, + // Acknowledge that we are indeed committing - ISSUE_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o, + // Acknowledge that we are indeed committing - CSR_REGFILE + output logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack_o, + // Register file write address - ISSUE_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o, + // Register file write data - ISSUE_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_o, + // Register file write enable - ISSUE_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o, + // Floating point register enable - ISSUE_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_o, + // Result of AMO operation - CACHE + input amo_resp_t amo_resp_i, + // TO_BE_COMPLETED - FRONTEND_CSR_REGFILE + output logic [CVA6Cfg.VLEN-1:0] pc_o, + // Decoded CSR operation - CSR_REGFILE + output fu_op csr_op_o, + // Data to write to CSR - CSR_REGFILE + output logic [CVA6Cfg.XLEN-1:0] csr_wdata_o, + // Data to read from CSR - CSR_REGFILE + input logic [CVA6Cfg.XLEN-1:0] csr_rdata_i, + // Write the fflags CSR - CSR_REGFILE + output logic csr_write_fflags_o, + // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE + input exception_t csr_exception_i, + // Commit the pending store - EX_STAGE + output logic commit_lsu_o, + // Commit buffer of LSU is ready - EX_STAGE + input logic commit_lsu_ready_i, + // Transaction id of first commit port - ID_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_o, + // Valid AMO in commit stage - EX_STAGE + output logic amo_valid_commit_o, + // no store is pending - EX_STAGE + input logic no_st_pending_i, + // Commit the pending CSR instruction - EX_STAGE + output logic commit_csr_o, + // Flush I$ and pipeline - CONTROLLER + output logic fence_i_o, + // Flush D$ and pipeline - CONTROLLER + output logic fence_o, + // Request a pipeline flush - CONTROLLER + output logic flush_commit_o, + // Flush TLBs and pipeline - CONTROLLER + output logic sfence_vma_o, + // TO_BE_COMPLETED - CONTROLLER + output logic hfence_vvma_o, + // TO_BE_COMPLETED - CONTROLLER + output logic hfence_gvma_o +); + + // ila_0 i_ila_commit ( + // .clk(clk_i), // input wire clk + // .probe0(commit_instr_i[0].pc), // input wire [63:0] probe0 + // .probe1(commit_instr_i[1].pc), // input wire [63:0] probe1 + // .probe2(commit_instr_i[0].valid), // input wire [0:0] probe2 + // .probe3(commit_instr_i[1].valid), // input wire [0:0] probe3 + // .probe4(commit_ack_o[0]), // input wire [0:0] probe4 + // .probe5(commit_ack_o[0]), // input wire [0:0] probe5 + // .probe6(1'b0), // input wire [0:0] probe6 + // .probe7(1'b0), // input wire [0:0] probe7 + // .probe8(1'b0), // input wire [0:0] probe8 + // .probe9(1'b0) // input wire [0:0] probe9 + // ); + + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_waddr + assign waddr_o[i] = commit_instr_i[i].rd; + end + + assign pc_o = commit_instr_i[0].pc; + // Dirty the FP state if we are committing anything related to the FPU + always_comb begin : dirty_fp_state + dirty_fp_state_o = 1'b0; + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + commit_instr_i[i].op + // Check if we issued a vector floating-point instruction to the accellerator + ))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; + end + end + + assign commit_tran_id_o = commit_instr_i[0].trans_id; + + logic instr_0_is_amo; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack; + assign instr_0_is_amo = is_amo(commit_instr_i[0].op); + // ------------------- + // Commit Instruction + // ------------------- + // write register file or commit instruction in LSU or CSR Buffer + always_comb begin : commit + // default assignments + commit_ack_o[0] = 1'b0; + commit_macro_ack[0] = 1'b0; + + amo_valid_commit_o = 1'b0; + + we_gpr_o[0] = 1'b0; + we_fpr_o = '{default: 1'b0}; + commit_lsu_o = 1'b0; + commit_csr_o = 1'b0; + // amos will commit on port 0 + wdata_o[0] = (CVA6Cfg.RVA && amo_resp_i.ack) ? amo_resp_i.result[CVA6Cfg.XLEN-1:0] : commit_instr_i[0].result; + csr_op_o = ADD; // this corresponds to a CSR NOP + csr_wdata_o = {CVA6Cfg.XLEN{1'b0}}; + fence_i_o = 1'b0; + fence_o = 1'b0; + sfence_vma_o = 1'b0; + hfence_vvma_o = 1'b0; + hfence_gvma_o = 1'b0; + csr_write_fflags_o = 1'b0; + flush_commit_o = 1'b0; + + // we do not commit the instruction yet if we requested a halt + if (commit_instr_i[0].valid && !halt_i) begin + // we will not commit the instruction if we took an exception + if (commit_instr_i[0].ex.valid) begin + // However we can drop it (with its exception) + if (commit_drop_i[0]) begin + commit_ack_o[0] = 1'b1; + end + end else begin + commit_ack_o[0] = 1'b1; + + if (CVA6Cfg.RVZCMP && commit_instr_i[0].is_macro_instr && commit_instr_i[0].is_last_macro_instr) + commit_macro_ack[0] = 1'b1; + else commit_macro_ack[0] = 1'b0; + + if (!commit_drop_i[0]) begin + // we can definitely write the register file + // if the instruction is not committing anything the destination + if (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(commit_instr_i[0].op)) begin + we_fpr_o[0] = 1'b1; + end else begin + we_gpr_o[0] = 1'b1; + end + end + + // check whether the instruction we retire was a store + if (commit_instr_i[0].fu == STORE && !(CVA6Cfg.RVA && instr_0_is_amo)) begin + // check if the LSU is ready to accept another commit entry (e.g.: a non-speculative store) + if (commit_lsu_ready_i) begin + commit_lsu_o = 1'b1; + // stall in case the store buffer is not able to accept anymore instructions + end else begin + commit_ack_o[0] = 1'b0; + end + end + // --------- + // FPU Flags + // --------- + if (CVA6Cfg.FpPresent) begin + if (commit_instr_i[0].fu inside {FPU, FPU_VEC}) begin + if (!commit_drop_i[0]) begin + // write the CSR with potential exception flags from retiring floating point instruction + csr_wdata_o = {{CVA6Cfg.XLEN - 5{1'b0}}, commit_instr_i[0].ex.cause[4:0]}; + csr_write_fflags_o = 1'b1; + end + end + end + // --------- + // CSR Logic + // --------- + // check whether the instruction we retire was a CSR instruction and it did not + // throw an exception + if (commit_instr_i[0].fu == CSR) begin + // write the CSR file + csr_op_o = commit_instr_i[0].op; + csr_wdata_o = commit_instr_i[0].result; + if (!commit_drop_i[0]) begin + if (!csr_exception_i.valid) begin + commit_csr_o = 1'b1; + wdata_o[0] = csr_rdata_i; + end else begin + commit_ack_o[0] = 1'b0; + we_gpr_o[0] = 1'b0; + end + end + end + // ------------------ + // SFENCE.VMA Logic + // ------------------ + // sfence.vma is idempotent so we can safely re-execute it after returning + // from interrupt service routine + // check if this instruction was a SFENCE_VMA + if (CVA6Cfg.RVS && commit_instr_i[0].op == SFENCE_VMA) begin + if (!commit_drop_i[0]) begin + // no store pending so we can flush the TLBs and pipeline + sfence_vma_o = no_st_pending_i; + // wait for the store buffer to drain until flushing the pipeline + commit_ack_o[0] = no_st_pending_i; + end + end + // ------------------ + // HFENCE.VVMA Logic + // ------------------ + // hfence.vvma is idempotent so we can safely re-execute it after returning + // from interrupt service routine + // check if this instruction was a HFENCE_VVMA + if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_VVMA) begin + if (!commit_drop_i[0]) begin + // no store pending so we can flush the TLBs and pipeline + hfence_vvma_o = no_st_pending_i; + // wait for the store buffer to drain until flushing the pipeline + commit_ack_o[0] = no_st_pending_i; + end + end + // ------------------ + // HFENCE.GVMA Logic + // ------------------ + // hfence.gvma is idempotent so we can safely re-execute it after returning + // from interrupt service routine + // check if this instruction was a HFENCE_GVMA + if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_GVMA) begin + if (!commit_drop_i[0]) begin + // no store pending so we can flush the TLBs and pipeline + hfence_gvma_o = no_st_pending_i; + // wait for the store buffer to drain until flushing the pipeline + commit_ack_o[0] = no_st_pending_i; + end + end + // ------------------ + // FENCE.I Logic + // ------------------ + // fence.i is idempotent so we can safely re-execute it after returning + // from interrupt service routine + // Fence synchronizes data and instruction streams. That means that we need to flush the private icache + // and the private dcache. This is the most expensive instruction. + if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && CVA6Cfg.DCacheType == config_pkg::WB && commit_instr_i[0].fu != STORE)) begin + if (!commit_drop_i[0]) begin + commit_ack_o[0] = no_st_pending_i; + // tell the controller to flush the I$ + fence_i_o = no_st_pending_i; + end + end + // ------------------ + // FENCE Logic + // ------------------ + // fence is idempotent so we can safely re-execute it after returning + // from interrupt service routine + if (commit_instr_i[0].op == FENCE) begin + if (!commit_drop_i[0]) begin + commit_ack_o[0] = no_st_pending_i; + // tell the controller to flush the D$ + fence_o = no_st_pending_i; + end + end + // ------------------ + // AMO + // ------------------ + if (CVA6Cfg.RVA && instr_0_is_amo) begin + // AMO finished + commit_ack_o[0] = amo_resp_i.ack; + // flush the pipeline + flush_commit_o = amo_resp_i.ack; + amo_valid_commit_o = 1'b1; + we_gpr_o[0] = amo_resp_i.ack; + end + end + end + + if (CVA6Cfg.NrCommitPorts > 1) begin + commit_macro_ack[1] = 1'b0; + commit_ack_o[1] = 1'b0; + we_gpr_o[1] = 1'b0; + wdata_o[1] = commit_instr_i[1].result; + + // ----------------- + // Commit Port 2 + // ----------------- + // check if the second instruction can be committed as well and the first wasn't a CSR instruction + // also if we are in single step mode don't retire the second instruction + if (commit_ack_o[0] && commit_instr_i[1].valid + && !halt_i + && !(commit_instr_i[0].fu inside {CSR}) + && !flush_dcache_i + && !(CVA6Cfg.RVA && instr_0_is_amo) + && !single_step_i) begin + // only if the first instruction didn't throw an exception and this instruction won't throw an exception + // and the functional unit is of type ALU, LOAD, CTRL_FLOW, MULT, FPU or FPU_VEC + if (!commit_instr_i[1].ex.valid && (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin + + if (CVA6Cfg.RVZCMP && commit_instr_i[1].is_macro_instr && commit_instr_i[1].is_last_macro_instr) + commit_macro_ack[1] = 1'b1; + else commit_macro_ack[1] = 1'b0; + + commit_ack_o[1] = 1'b1; + + if (!commit_drop_i[1]) begin + if (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(commit_instr_i[1].op)) + we_fpr_o[1] = 1'b1; + else we_gpr_o[1] = 1'b1; + + // additionally check if we are retiring an FPU instruction because we need to make sure that we write all + // exception flags + if (CVA6Cfg.FpPresent) begin + if (commit_instr_i[1].fu inside {FPU, FPU_VEC}) begin + if (csr_write_fflags_o) + csr_wdata_o = { + {CVA6Cfg.XLEN - 5{1'b0}}, + (commit_instr_i[0].ex.cause[4:0] | commit_instr_i[1].ex.cause[4:0]) + }; + else csr_wdata_o = {{CVA6Cfg.XLEN - 5{1'b0}}, commit_instr_i[1].ex.cause[4:0]}; + csr_write_fflags_o = 1'b1; + end + end + end + end + end + end + if (CVA6Cfg.RVZCMP) begin + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + commit_macro_ack_o[i] = commit_instr_i[i].is_macro_instr ? commit_macro_ack[i] : commit_ack_o[i]; + end + end else commit_macro_ack_o = commit_ack_o; + end + + // ----------------------------- + // Exception & Interrupt Logic + // ----------------------------- + // here we know for sure that we are taking the exception + always_comb begin : exception_handling + // Multiple simultaneous interrupts and traps at the same privilege level are handled in the following decreasing + // priority order: external interrupts, software interrupts, timer interrupts, then finally any synchronous traps. (1.10 p.30) + // interrupts are correctly prioritized in the CSR reg file, exceptions are prioritized here + exception_o.valid = 1'b0; + exception_o.cause = '0; + exception_o.tval = '0; + exception_o.tval2 = '0; + exception_o.tinst = '0; + exception_o.gva = 1'b0; + + // we need a valid instruction in the commit stage + if (commit_instr_i[0].valid && !commit_drop_i[0]) begin + // ------------------------ + // check for CSR exception + // ------------------------ + if (csr_exception_i.valid) begin + exception_o = csr_exception_i; + // if no earlier exception happened the commit instruction will still contain + // the instruction bits from the ID stage. If a earlier exception happened we don't care + // as we will overwrite it anyway in the next IF bl + exception_o.tval = commit_instr_i[0].ex.tval; + if (CVA6Cfg.RVH) begin + exception_o.tinst = commit_instr_i[0].ex.tinst; + exception_o.tval2 = commit_instr_i[0].ex.tval2; + exception_o.gva = commit_instr_i[0].ex.gva; + end + end + // ------------------------ + // Earlier Exceptions + // ------------------------ + // but we give precedence to exceptions which happened earlier e.g.: instruction page + // faults for example + if (commit_instr_i[0].ex.valid) begin + exception_o = commit_instr_i[0].ex; + end + end + // Don't take any exceptions iff: + // - If we halted the processor + if (halt_i) begin + exception_o.valid = 1'b0; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/compressed_decoder.sv b/flow/designs/src/cva6/core/compressed_decoder.sv new file mode 100644 index 0000000000..26c0289a18 --- /dev/null +++ b/flow/designs/src/cva6/core/compressed_decoder.sv @@ -0,0 +1,947 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. // +// +// Author: Florian Zaruba - zarubaf@iis.ee.ethz.ch +// Engineer: Sven Stucki - svstucki@student.ethz.ch +// +// Design Name: Compressed instruction decoder +// Project Name: zero-riscy +// Language: SystemVerilog +// +// Description: Decodes RISC-V compressed instructions into their RV32 +// equivalent. This module is fully combinatorial. + + +module compressed_decoder #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Input instruction coming from fetch stage - FRONTEND + input logic [31:0] instr_i, + // Output instruction in uncompressed format - decoder + output logic [31:0] instr_o, + // Input instruction is illegal - decoder + output logic illegal_instr_o, + // Output instruction is macro - decoder + output logic is_macro_instr_o, + // Output instruction is compressed - decoder + output logic is_compressed_o, + // Output instruction is macro - decoder + output logic is_zcmt_instr_o +); + + // ------------------- + // Compressed Decoder + // ------------------- + always_comb begin + illegal_instr_o = 1'b0; + is_compressed_o = 1'b1; + instr_o = instr_i; + is_macro_instr_o = 0; + is_zcmt_instr_o = 1'b0; + + // I: | imm[11:0] | rs1 | funct3 | rd | opcode | + // S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode | + unique case (instr_i[1:0]) + // C0 + riscv::OpcodeC0: begin + unique case (instr_i[15:13]) + riscv::OpcodeC0Addi4spn: begin + // c.addi4spn -> addi rd', x2, imm + instr_o = { + 2'b0, + instr_i[10:7], + instr_i[12:11], + instr_i[5], + instr_i[6], + 2'b00, + 5'h02, + 3'b000, + 2'b01, + instr_i[4:2], + riscv::OpcodeOpImm + }; + if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1; + end + + riscv::OpcodeC0Fld: begin + if (CVA6Cfg.FpPresent) begin + // c.fld -> fld rd', imm(rs1') + // CLD: | funct3 | imm[5:3] | rs1' | imm[7:6] | rd' | C0 | + instr_o = { + 4'b0, + instr_i[6:5], + instr_i[12:10], + 3'b000, + 2'b01, + instr_i[9:7], + 3'b011, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoadFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + + riscv::OpcodeC0Lw: begin + // c.lw -> lw rd', imm(rs1') + instr_o = { + 5'b0, + instr_i[5], + instr_i[12:10], + instr_i[6], + 2'b00, + 2'b01, + instr_i[9:7], + 3'b010, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoad + }; + end + + riscv::OpcodeC0Ld: begin + // RV64 + // c.ld -> ld rd', imm(rs1') + // RV32 + // c.flw -> flw fprd', imm(rs1') + if (CVA6Cfg.IS_XLEN64) begin + // CLD: | funct3 | imm[5:3] | rs1' | imm[7:6] | rd' | C0 | + instr_o = { + 4'b0, + instr_i[6:5], + instr_i[12:10], + 3'b000, + 2'b01, + instr_i[9:7], + 3'b011, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoad + }; + end else begin + if (CVA6Cfg.FpPresent) begin + // CFLW: | funct3 (change to LW) | imm[5:3] | rs1' | imm[2|6] | rd' | C0 | + instr_o = { + 5'b0, + instr_i[5], + instr_i[12:10], + instr_i[6], + 2'b00, + 2'b01, + instr_i[9:7], + 3'b010, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoadFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + end + + riscv::OpcodeC0Zcb: begin + if (CVA6Cfg.RVZCB) begin + unique case (instr_i[12:10]) + 3'b000: begin + // c.lbu -> lbu rd', uimm(rs1') + instr_o = { + 10'b0, + instr_i[5], + instr_i[6], + 2'b01, + instr_i[9:7], + 3'b100, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoad + }; + end + + 3'b001: begin + if (instr_i[6]) begin + // c.lh -> lh rd', uimm(rs1') + instr_o = { + 10'b0, + instr_i[5], + 1'b0, + 2'b01, + instr_i[9:7], + 3'b001, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoad + }; + end else begin + // c.lhu -> lhu rd', uimm(rs1') + instr_o = { + 10'b0, + instr_i[5], + 1'b0, + 2'b01, + instr_i[9:7], + 3'b101, + 2'b01, + instr_i[4:2], + riscv::OpcodeLoad + }; + end + end + + 3'b010: begin + // c.sb -> sb rs2', uimm(rs1') + instr_o = { + 7'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b000, + 3'b0, + instr_i[5], + instr_i[6], + riscv::OpcodeStore + }; + end + + 3'b011: begin + // c.sh -> sh rs2', uimm(rs1') + instr_o = { + 7'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b001, + 3'b0, + instr_i[5], + 1'b0, + riscv::OpcodeStore + }; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + + end else begin + instr_o = instr_i; + illegal_instr_o = 1'b1; + end + end + + riscv::OpcodeC0Fsd: begin + if (CVA6Cfg.FpPresent) begin + // c.fsd -> fsd rs2', imm(rs1') + instr_o = { + 4'b0, + instr_i[6:5], + instr_i[12], + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b011, + instr_i[11:10], + 3'b000, + riscv::OpcodeStoreFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + + riscv::OpcodeC0Sw: begin + // c.sw -> sw rs2', imm(rs1') + instr_o = { + 5'b0, + instr_i[5], + instr_i[12], + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b010, + instr_i[11:10], + instr_i[6], + 2'b00, + riscv::OpcodeStore + }; + end + + riscv::OpcodeC0Sd: begin + // RV64 + // c.sd -> sd rs2', imm(rs1') + // RV32 + // c.fsw -> fsw fprs2', imm(rs1') + if (CVA6Cfg.IS_XLEN64) begin + instr_o = { + 4'b0, + instr_i[6:5], + instr_i[12], + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b011, + instr_i[11:10], + 3'b000, + riscv::OpcodeStore + }; + end else begin + if (CVA6Cfg.FpPresent) begin + instr_o = { + 5'b0, + instr_i[5], + instr_i[12], + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b010, + instr_i[11:10], + instr_i[6], + 2'b00, + riscv::OpcodeStoreFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // C1 + riscv::OpcodeC1: begin + unique case (instr_i[15:13]) + riscv::OpcodeC1Addi: begin + // c.addi -> addi rd, rd, nzimm + // c.nop -> addi 0, 0, 0 + instr_o = { + {6{instr_i[12]}}, + instr_i[12], + instr_i[6:2], + instr_i[11:7], + 3'b0, + instr_i[11:7], + riscv::OpcodeOpImm + }; + end + + + riscv::OpcodeC1Addiw: begin // or riscv::OpcodeC1Jal for RV32IC + if (CVA6Cfg.IS_XLEN64) begin + // c.addiw -> addiw rd, rd, nzimm for RV64IC + if (instr_i[11:7] != 5'h0) begin // only valid if the destination is not r0 + instr_o = { + {6{instr_i[12]}}, + instr_i[12], + instr_i[6:2], + instr_i[11:7], + 3'b0, + instr_i[11:7], + riscv::OpcodeOpImm32 + }; + end else begin + illegal_instr_o = 1'b1; + end + end else begin + // c.jal -> jal x1, imm for RV32IC only + instr_o = { + instr_i[12], + instr_i[8], + instr_i[10:9], + instr_i[6], + instr_i[7], + instr_i[2], + instr_i[11], + instr_i[5:3], + {9{instr_i[12]}}, + 5'b1, + riscv::OpcodeJal + }; + + + + end + end + + riscv::OpcodeC1Li: begin + // c.li -> addi rd, x0, nzimm + instr_o = { + {6{instr_i[12]}}, + instr_i[12], + instr_i[6:2], + 5'b0, + 3'b0, + instr_i[11:7], + riscv::OpcodeOpImm + }; + end + + riscv::OpcodeC1LuiAddi16sp: begin + // c.lui -> lui rd, imm + instr_o = {{15{instr_i[12]}}, instr_i[6:2], instr_i[11:7], riscv::OpcodeLui}; + + if (instr_i[11:7] == 5'h02) begin + // c.addi16sp -> addi x2, x2, nzimm + instr_o = { + {3{instr_i[12]}}, + instr_i[4:3], + instr_i[5], + instr_i[2], + instr_i[6], + 4'b0, + 5'h02, + 3'b000, + 5'h02, + riscv::OpcodeOpImm + }; + end + + if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1; + end + + riscv::OpcodeC1MiscAlu: begin + unique case (instr_i[11:10]) + 2'b00, 2'b01: begin + // 00: c.srli -> srli rd, rd, shamt + // 01: c.srai -> srai rd, rd, shamt + instr_o = { + 1'b0, + instr_i[10], + 4'b0, + instr_i[12], + instr_i[6:2], + 2'b01, + instr_i[9:7], + 3'b101, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end + + 2'b10: begin + // c.andi -> andi rd, rd, imm + instr_o = { + {6{instr_i[12]}}, + instr_i[12], + instr_i[6:2], + 2'b01, + instr_i[9:7], + 3'b111, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end + + 2'b11: begin + unique case ({ + instr_i[12], instr_i[6:5] + }) + 3'b000: begin + // c.sub -> sub rd', rd', rs2' + instr_o = { + 2'b01, + 5'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b000, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end + + 3'b001: begin + // c.xor -> xor rd', rd', rs2' + instr_o = { + 7'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b100, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end + + 3'b010: begin + // c.or -> or rd', rd', rs2' + instr_o = { + 7'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b110, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end + + 3'b011: begin + // c.and -> and rd', rd', rs2' + instr_o = { + 7'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b111, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end + + 3'b100: begin + if (CVA6Cfg.IS_XLEN64) begin + // c.subw -> subw rd', rd', rs2' + instr_o = { + 2'b01, + 5'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b000, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp32 + }; + end else begin + illegal_instr_o = 1'b1; + end + end + + 3'b101: begin + if (CVA6Cfg.IS_XLEN64) begin + // c.addw -> addw rd', rd', rs2' + instr_o = { + 2'b00, + 5'b0, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b000, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp32 + }; + end else begin + illegal_instr_o = 1'b1; + end + end + + 3'b110: begin + if (CVA6Cfg.RVZCB) begin + // c.mul -> mul rd', rd', rs2' + instr_o = { + 6'b0, + 1'b1, + 2'b01, + instr_i[4:2], + 2'b01, + instr_i[9:7], + 3'b000, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end else begin + instr_o = instr_i; + illegal_instr_o = 1'b1; + end + end + + 3'b111: begin + if (CVA6Cfg.RVZCB) begin + + unique case (instr_i[4:2]) + 3'b000: begin + // c.zext.b -> andi rd', rd', 0xff + instr_o = { + 4'b0, + 8'hFF, + 2'b01, + instr_i[9:7], + 3'b111, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end + + 3'b001: begin + if (CVA6Cfg.RVB) begin + // c.sext.b -> sext.b rd', rd' + instr_o = { + 7'h30, + 5'h4, + 2'b01, + instr_i[9:7], + 3'b001, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end else illegal_instr_o = 1'b1; + end + + 3'b010: begin + if (CVA6Cfg.RVB) begin + // c.zext.h -> zext.h rd', rd' + if (CVA6Cfg.IS_XLEN64) begin + instr_o = { + 7'h4, + 5'h0, + 2'b01, + instr_i[9:7], + 3'b100, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp32 + }; + end else begin + instr_o = { + 7'h4, + 5'h0, + 2'b01, + instr_i[9:7], + 3'b100, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp + }; + end + end else illegal_instr_o = 1'b1; + end + + 3'b011: begin + if (CVA6Cfg.RVB) begin + // c.sext.h -> sext.h rd', rd' + instr_o = { + 7'h30, + 5'h5, + 2'b01, + instr_i[9:7], + 3'b001, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end else illegal_instr_o = 1'b1; + end + + 3'b100: begin + if (CVA6Cfg.RVB) begin + // c.zext.w -> add.uw + if (CVA6Cfg.IS_XLEN64) begin + instr_o = { + 7'h4, + 5'h0, + 2'b01, + instr_i[9:7], + 3'b000, + 2'b01, + instr_i[9:7], + riscv::OpcodeOp32 + }; + end else begin + illegal_instr_o = 1'b1; + end + end else illegal_instr_o = 1'b1; + end + + 3'b101: begin + // c.not -> xori rd', rd', -1 + instr_o = { + 12'hFFF, + 2'b01, + instr_i[9:7], + 3'b100, + 2'b01, + instr_i[9:7], + riscv::OpcodeOpImm + }; + end + + default: begin + instr_o = instr_i; + illegal_instr_o = 1; + end + endcase + end + end + endcase + end + endcase + end + + riscv::OpcodeC1J: begin + // 101: c.j -> jal x0, imm + instr_o = { + instr_i[12], + instr_i[8], + instr_i[10:9], + instr_i[6], + instr_i[7], + instr_i[2], + instr_i[11], + instr_i[5:3], + {9{instr_i[12]}}, + 4'b0, + ~instr_i[15], + riscv::OpcodeJal + }; + end + + riscv::OpcodeC1Beqz, riscv::OpcodeC1Bnez: begin + // 0: c.beqz -> beq rs1', x0, imm + // 1: c.bnez -> bne rs1', x0, imm + instr_o = { + {4{instr_i[12]}}, + instr_i[6:5], + instr_i[2], + 5'b0, + 2'b01, + instr_i[9:7], + 2'b00, + instr_i[13], + instr_i[11:10], + instr_i[4:3], + instr_i[12], + riscv::OpcodeBranch + }; + end + endcase + end + + // C2 + riscv::OpcodeC2: begin + unique case (instr_i[15:13]) + riscv::OpcodeC2Slli: begin + // c.slli -> slli rd, rd, shamt + instr_o = { + 6'b0, + instr_i[12], + instr_i[6:2], + instr_i[11:7], + 3'b001, + instr_i[11:7], + riscv::OpcodeOpImm + }; + end + + riscv::OpcodeC2Fldsp: begin + if (CVA6Cfg.FpPresent) begin + // c.fldsp -> fld rd, imm(x2) + instr_o = { + 3'b0, + instr_i[4:2], + instr_i[12], + instr_i[6:5], + 3'b000, + 5'h02, + 3'b011, + instr_i[11:7], + riscv::OpcodeLoadFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + + riscv::OpcodeC2Lwsp: begin + // c.lwsp -> lw rd, imm(x2) + instr_o = { + 4'b0, + instr_i[3:2], + instr_i[12], + instr_i[6:4], + 2'b00, + 5'h02, + 3'b010, + instr_i[11:7], + riscv::OpcodeLoad + }; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + + riscv::OpcodeC2Ldsp: begin + // RV64 + // c.ldsp -> ld rd, imm(x2) + // RV32 + // c.flwsp -> flw fprd, imm(x2) + if (CVA6Cfg.IS_XLEN64) begin + instr_o = { + 3'b0, + instr_i[4:2], + instr_i[12], + instr_i[6:5], + 3'b000, + 5'h02, + 3'b011, + instr_i[11:7], + riscv::OpcodeLoad + }; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end else begin + if (CVA6Cfg.FpPresent) begin + instr_o = { + 4'b0, + instr_i[3:2], + instr_i[12], + instr_i[6:4], + 2'b00, + 5'h02, + 3'b010, + instr_i[11:7], + riscv::OpcodeLoadFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + end + + riscv::OpcodeC2JalrMvAdd: begin + if (instr_i[12] == 1'b0) begin + // c.mv -> add rd/rs1, x0, rs2 + instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], riscv::OpcodeOp}; + + if (instr_i[6:2] == 5'b0) begin + // c.jr -> jalr x0, rd/rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, riscv::OpcodeJalr}; + // rs1 != 0 + illegal_instr_o = (instr_i[11:7] != '0) ? 1'b0 : 1'b1; + end + end else begin + // c.add -> add rd, rd, rs2 + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], riscv::OpcodeOp}; + + if (instr_i[6:2] == 5'b0) begin + if (instr_i[11:7] == 5'b0) begin + // c.ebreak -> ebreak + instr_o = {32'h00_10_00_73}; + end else begin + // c.jalr -> jalr x1, rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, riscv::OpcodeJalr}; + end + end + end + end + + riscv::OpcodeC2Fsdsp: begin + if (CVA6Cfg.FpPresent) begin + // c.fsdsp -> fsd rs2, imm(x2) + instr_o = { + 3'b0, + instr_i[9:7], + instr_i[12], + instr_i[6:2], + 5'h02, + 3'b011, + instr_i[11:10], + 3'b000, + riscv::OpcodeStoreFp + }; + end else if (CVA6Cfg.RVZCMP && (instr_i[12:10] == 3'b110 || instr_i[12:10] == 3'b111 || instr_i[12:10] == 3'b011)) begin + is_macro_instr_o = 1; + instr_o = instr_i; + end else if (CVA6Cfg.RVZCMT && (instr_i[12:10] == 3'b000)) //jt/jalt instruction + is_zcmt_instr_o = 1'b1; + else illegal_instr_o = 1'b1; + end + riscv::OpcodeC2Swsp: begin + // c.swsp -> sw rs2, imm(x2) + instr_o = { + 4'b0, + instr_i[8:7], + instr_i[12], + instr_i[6:2], + 5'h02, + 3'b010, + instr_i[11:9], + 2'b00, + riscv::OpcodeStore + }; + end + + riscv::OpcodeC2Sdsp: begin + // RV64 + // c.sdsp -> sd rs2, imm(x2) + // RV32 + // c.fswsp -> fsw fprs2, imm(x2) + if (CVA6Cfg.IS_XLEN64) begin + instr_o = { + 3'b0, + instr_i[9:7], + instr_i[12], + instr_i[6:2], + 5'h02, + 3'b011, + instr_i[11:10], + 3'b000, + riscv::OpcodeStore + }; + end else begin + if (CVA6Cfg.FpPresent) begin + instr_o = { + 4'b0, + instr_i[8:7], + instr_i[12], + instr_i[6:2], + 5'h02, + 3'b010, + instr_i[11:9], + 2'b00, + riscv::OpcodeStoreFp + }; + end else begin + illegal_instr_o = 1'b1; + end + end + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // normal instruction + default: is_compressed_o = 1'b0; + endcase + + // Check if the instruction was illegal, if it was then output the offending instruction (zero-extended) + if (illegal_instr_o) begin + instr_o = instr_i; + end + end +endmodule + diff --git a/flow/designs/src/cva6/core/controller.sv b/flow/designs/src/cva6/core/controller.sv new file mode 100644 index 0000000000..8016869ec3 --- /dev/null +++ b/flow/designs/src/cva6/core/controller.sv @@ -0,0 +1,261 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.05.2017 +// Description: Flush controller + + +module controller + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Virtualization mode - CSR_REGFILE + input logic v_i, + // Set PC om PC Gen - FRONTEND + output logic set_pc_commit_o, + // Flush the IF stage - FRONTEND + output logic flush_if_o, + // Flush un-issued instructions of the scoreboard - FRONTEND + output logic flush_unissued_instr_o, + // Flush ID stage - ID_STAGE + output logic flush_id_o, + // Flush EX stage - EX_STAGE + output logic flush_ex_o, + // Flush branch predictors - FRONTEND + output logic flush_bp_o, + // Flush ICache - CACHE + output logic flush_icache_o, + // Flush DCache - CACHE + output logic flush_dcache_o, + // Acknowledge the whole DCache Flush - CACHE + input logic flush_dcache_ack_i, + // Flush TLBs - EX_STAGE + output logic flush_tlb_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic flush_tlb_vvma_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic flush_tlb_gvma_o, + // Halt request from CSR (WFI instruction) - CSR_REGFILE + input logic halt_csr_i, + // Halt request from accelerator dispatcher - ACC_DISPATCHER + input logic halt_acc_i, + // Halt signal to commit stage - COMMIT_STAGE + output logic halt_o, + // Return from exception - CSR_REGFILE + input logic eret_i, + // We got an exception, flush the pipeline - FRONTEND + input logic ex_valid_i, + // set the debug pc from CSR - FRONTEND + input logic set_debug_pc_i, + // We got a resolved branch, check if we need to flush the front-end - EX_STAGE + input bp_resolve_t resolved_branch_i, + // We got an instruction which altered the CSR, flush the pipeline - CSR_REGFILE + input logic flush_csr_i, + // fence.i in - ACC_DISPATCH + input logic fence_i_i, + // fence in - ACC_DISPATCH + input logic fence_i, + // We got an instruction to flush the TLBs and pipeline - COMMIT_STAGE + input logic sfence_vma_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic hfence_vvma_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic hfence_gvma_i, + // Flush request from commit stage - COMMIT_STAGE + input logic flush_commit_i, + // Flush request from accelerator - ACC_DISPATCHER + input logic flush_acc_i +); + + // active fence - high if we are currently flushing the dcache + logic fence_active_d, fence_active_q; + logic flush_dcache; + + // ------------ + // Flush CTRL + // ------------ + always_comb begin : flush_ctrl + fence_active_d = fence_active_q; + set_pc_commit_o = 1'b0; + flush_if_o = 1'b0; + flush_unissued_instr_o = 1'b0; + flush_id_o = 1'b0; + flush_ex_o = 1'b0; + flush_dcache = 1'b0; + flush_icache_o = 1'b0; + flush_tlb_o = 1'b0; + flush_tlb_vvma_o = 1'b0; + flush_tlb_gvma_o = 1'b0; + flush_bp_o = 1'b0; + // ------------ + // Mis-predict + // ------------ + // flush on mispredict + if (resolved_branch_i.is_mispredict) begin + // flush only un-issued instructions + flush_unissued_instr_o = 1'b1; + // and if stage + flush_if_o = 1'b1; + end + + // --------------------------------- + // FENCE + // --------------------------------- + if (fence_i) begin + // this can be seen as a CSR instruction with side-effect + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + // this is not needed in the case since we + // have a write-through cache in this case + if (CVA6Cfg.DcacheFlushOnFence) begin + flush_dcache = 1'b1; + fence_active_d = 1'b1; + end + end + + // --------------------------------- + // FENCE.I + // --------------------------------- + if (fence_i_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + flush_icache_o = 1'b1; + // this is not needed in the case since we + // have a write-through cache in this case + if (CVA6Cfg.DcacheFlushOnFence) begin + flush_dcache = 1'b1; + fence_active_d = 1'b1; + end + end + + // this is not needed in the case since we + // have a write-through cache in this case + if (CVA6Cfg.DcacheFlushOnFence) begin + // wait for the acknowledge here + if (flush_dcache_ack_i && fence_active_q) begin + fence_active_d = 1'b0; + // keep the flush dcache signal high as long as we didn't get the acknowledge from the cache + end else if (fence_active_q) begin + flush_dcache = 1'b1; + end + end + // --------------------------------- + // SFENCE.VMA + // --------------------------------- + if (CVA6Cfg.RVS && sfence_vma_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + + if (CVA6Cfg.RVH && v_i) flush_tlb_vvma_o = 1'b1; + else flush_tlb_o = 1'b1; + end + + // --------------------------------- + // HFENCE.VVMA + // --------------------------------- + if (CVA6Cfg.RVH && hfence_vvma_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + + flush_tlb_vvma_o = 1'b1; + end + + // --------------------------------- + // HFENCE.GVMA + // --------------------------------- + if (CVA6Cfg.RVH && hfence_gvma_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + + flush_tlb_gvma_o = 1'b1; + end + + // --------------------------------- + // CSR side effects and accelerate port + // --------------------------------- + // Set PC to commit stage and flush pipeline + if (flush_csr_i || flush_acc_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + end else if (CVA6Cfg.RVA && flush_commit_i) begin + set_pc_commit_o = 1'b1; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + end + + // --------------------------------- + // 1. Exception + // 2. Return from exception + // --------------------------------- + if (ex_valid_i || eret_i || (CVA6Cfg.DebugEn && set_debug_pc_i)) begin + // don't flush pcgen as we want to take the exception: Flush PCGen is not a flush signal + // for the PC Gen stage but instead tells it to take the PC we gave it + set_pc_commit_o = 1'b0; + flush_if_o = 1'b1; + flush_unissued_instr_o = 1'b1; + flush_id_o = 1'b1; + flush_ex_o = 1'b1; + // this potentially reduces performance, but is needed + // to suppress speculative fetches to virtual memory from + // machine mode. TODO: remove when PMA checkers have been + // added to the system + flush_bp_o = 1'b1; + end + end + + // ---------------------- + // Halt Logic + // ---------------------- + always_comb begin + // halt the core if the fence is active + halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DcacheFlushOnFence && fence_active_q); + end + + // ---------------------- + // Registers + // ---------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + fence_active_q <= 1'b0; + flush_dcache_o <= 1'b0; + end else begin + fence_active_q <= fence_active_d; + // register on the flush signal, this signal might be critical + flush_dcache_o <= flush_dcache; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/csr_buffer.sv b/flow/designs/src/cva6/core/csr_buffer.sv new file mode 100644 index 0000000000..3ea7eab05b --- /dev/null +++ b/flow/designs/src/cva6/core/csr_buffer.sv @@ -0,0 +1,83 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 05.05.2017 +// Description: Buffer to hold CSR address, this acts like a functional unit +// to the scoreboard. + + +module csr_buffer + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush CSR - CONTROLLER + input logic flush_i, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // CSR FU is ready - ISSUE_STAGE + output logic csr_ready_o, + // CSR instruction is valid - ISSUE_STAGE + input logic csr_valid_i, + // CSR buffer result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] csr_result_o, + // commit the pending CSR OP - TO_BE_COMPLETED + input logic csr_commit_i, + // CSR address to write - COMMIT_STAGE + output logic [11:0] csr_addr_o +); + // this is a single entry store buffer for the address of the CSR + // which we are going to need in the commit stage + struct packed { + logic [11:0] csr_address; + logic valid; + } + csr_reg_n, csr_reg_q; + + // control logic, scoreboard signals + assign csr_result_o = fu_data_i.operand_a; + assign csr_addr_o = csr_reg_q.csr_address; + + // write logic + always_comb begin : write + csr_reg_n = csr_reg_q; + // by default we are ready + csr_ready_o = 1'b1; + // if we have a valid uncomiited csr req or are just getting one WITHOUT a commit in, we are not ready + if ((csr_reg_q.valid || csr_valid_i) && ~csr_commit_i) csr_ready_o = 1'b0; + // if we got a valid from the scoreboard + // store the CSR address + if (csr_valid_i) begin + csr_reg_n.csr_address = fu_data_i.operand_b[11:0]; + csr_reg_n.valid = 1'b1; + end + // if we get a commit and no new valid instruction -> clear the valid bit + if (csr_commit_i && ~csr_valid_i) begin + csr_reg_n.valid = 1'b0; + end + // clear the buffer if we flushed + if (flush_i) csr_reg_n.valid = 1'b0; + end + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + csr_reg_q <= '{default: 0}; + end else begin + csr_reg_q <= csr_reg_n; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/csr_regfile.sv b/flow/designs/src/cva6/core/csr_regfile.sv new file mode 100644 index 0000000000..7bbf529048 --- /dev/null +++ b/flow/designs/src/cva6/core/csr_regfile.sv @@ -0,0 +1,2786 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 05.05.2017 +// Description: CSR Register File as specified by RISC-V + + +module csr_regfile + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, + parameter type jvt_t = logic, + parameter type irq_ctrl_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type rvfi_probes_csr_t = logic, + parameter int VmidWidth = 1, + parameter int unsigned MHPMCounterNum = 6 +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Timer threw a interrupt - SUBSYSTEM + input logic time_irq_i, + // send a flush request out when a CSR with a side effect changes - CONTROLLER + output logic flush_o, + // halt requested - CONTROLLER + output logic halt_csr_o, + // Instruction to be committed - ID_STAGE + input scoreboard_entry_t commit_instr_i, + // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM + input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, + // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + // We've got an exception from the commit stage, take it - COMMIT_STAGE + input exception_t ex_i, + // Operation to perform on the CSR file - COMMIT_STAGE + input fu_op csr_op_i, + // Address of the register to read/write - EX_STAGE + input logic [11:0] csr_addr_i, + // Write data in - COMMIT_STAGE + input logic [CVA6Cfg.XLEN-1:0] csr_wdata_i, + // Read data out - COMMIT_STAGE + output logic [CVA6Cfg.XLEN-1:0] csr_rdata_o, + // Mark the FP sate as dirty - COMMIT_STAGE + input logic dirty_fp_state_i, + // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE + input logic csr_write_fflags_i, + // Mark the V state as dirty - ACC_DISPATCHER + input logic dirty_v_state_i, + // PC of instruction accessing the CSR - COMMIT_STAGE + input logic [CVA6Cfg.VLEN-1:0] pc_i, + // attempts to access a CSR without appropriate privilege - COMMIT_STAGE + output exception_t csr_exception_o, + // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND + output logic [CVA6Cfg.VLEN-1:0] epc_o, + // Return from exception, set the PC of epc_o - FRONTEND + output logic eret_o, + // Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND + output logic [CVA6Cfg.VLEN-1:0] trap_vector_base_o, + // Current privilege level the CPU is in - EX_STAGE + output riscv::priv_lvl_t priv_lvl_o, + // Current virtualization mode state the CPU is in - EX_STAGE + output logic v_o, + // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER + input logic [4:0] acc_fflags_ex_i, + // An FP exception from the accelerator occurred - ACC_DISPATCHER + input logic acc_fflags_ex_valid_i, + // Floating point extension status - ID_STAGE + output riscv::xs_t fs_o, + // Floating point extension virtual status - ID_STAGE + output riscv::xs_t vfs_o, + // Floating-Point Accured Exceptions - COMMIT_STAGE + output logic [4:0] fflags_o, + // Floating-Point Dynamic Rounding Mode - EX_STAGE + output logic [2:0] frm_o, + // Floating-Point Precision Control - EX_STAGE + output logic [6:0] fprec_o, + // Vector extension status - ID_STAGE + output riscv::xs_t vs_o, + // interrupt management to id stage - ID_STAGE + output irq_ctrl_t irq_ctrl_o, + // Enable virtual address translation - EX_STAGE + output logic en_translation_o, + // Enable G-Stage address translation - EX_STAGE + output logic en_g_translation_o, + // Enable virtual address translation for load and stores - EX_STAGE + output logic en_ld_st_translation_o, + // Enable G-Stage address translation for load and stores - EX_STAGE + output logic en_ld_st_g_translation_o, + // Privilege level at which load and stores should happen - EX_STAGE + output riscv::priv_lvl_t ld_st_priv_lvl_o, + // Virtualization mode at which load and stores should happen - EX_STAGE + output logic ld_st_v_o, + // Current instruction is a Hypervisor Load/Store Instruction - EX_STAGE + input logic csr_hs_ld_st_inst_i, + // Supervisor User Memory - EX_STAGE + output logic sum_o, + // Virtual Supervisor User Memory - EX_STAGE + output logic vs_sum_o, + // Make Executable Readable - EX_STAGE + output logic mxr_o, + // Make Executable Readable for VS-mode - EX_STAGE + output logic vmxr_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.PPNW-1:0] satp_ppn_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.ASID_WIDTH-1:0] asid_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_o, + // TO_BE_COMPLETED - EX_STAGE + output logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_o, + // external interrupt in - SUBSYSTEM + input logic [1:0] irq_i, + // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM + input logic ipi_i, + // debug request in - ID_STAGE + input logic debug_req_i, + // TO_BE_COMPLETED - FRONTEND + output logic set_debug_pc_o, + // trap virtual memory - ID_STAGE + output logic tvm_o, + // timeout wait - ID_STAGE + output logic tw_o, + // virtual timeout wait - ID_STAGE + output logic vtw_o, + // trap sret - ID_STAGE + output logic tsr_o, + // hypervisor user mode - ID_STAGE + output logic hu_o, + // we are in debug mode -> that will change some decoding - EX_STAGE + output logic debug_mode_o, + // we are in single-step mode - COMMIT_STAGE + output logic single_step_o, + // L1 ICache Enable - CACHE + output logic icache_en_o, + // L1 DCache Enable - CACHE + output logic dcache_en_o, + // Accelerator memory consistent mode - ACC_DISPATCHER + output logic acc_cons_en_o, + // read/write address to performance counter module - PERF_COUNTERS + output logic [11:0] perf_addr_o, + // write data to performance counter module - PERF_COUNTERS + output logic [CVA6Cfg.XLEN-1:0] perf_data_o, + // read data from performance counter module - PERF_COUNTERS + input logic [CVA6Cfg.XLEN-1:0] perf_data_i, + // TO_BE_COMPLETED - PERF_COUNTERS + output logic perf_we_o, + // PMP configuration containing pmpcfg for max 64 PMPs - ACC_DISPATCHER + output riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_o, + // PMP addresses - ACC_DISPATCHER + output logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_o, + // TO_BE_COMPLETED - PERF_COUNTERS + output logic [31:0] mcountinhibit_o, + // RVFI + output rvfi_probes_csr_t rvfi_csr_o, + //jvt output + output jvt_t jvt_o +); + + localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg); + localparam logic [63:0] HS_DELEG_INTERRUPTS = { + {32{1'b0}}, ariane_pkg::hs_deleg_interrupts(CVA6Cfg) + }; + localparam logic [63:0] VS_DELEG_INTERRUPTS = { + {32{1'b0}}, ariane_pkg::vs_deleg_interrupts(CVA6Cfg) + }; + localparam int SELECT_COUNTER_WIDTH = CVA6Cfg.IS_XLEN64 ? 6 : 5; + + typedef struct packed { + logic [CVA6Cfg.ModeW-1:0] mode; + logic [CVA6Cfg.ASIDW-1:0] asid; + logic [CVA6Cfg.PPNW-1:0] ppn; + } satp_t; + + typedef struct packed { + logic [CVA6Cfg.ModeW-1:0] mode; + logic [1:0] warl0; + logic [CVA6Cfg.VMIDW-1:0] vmid; + logic [CVA6Cfg.PPNW-1:0] ppn; + } hgatp_t; + + // internal signal to keep track of access exceptions + logic read_access_exception, update_access_exception, privilege_violation; + logic virtual_read_access_exception, virtual_update_access_exception, virtual_privilege_violation; + logic csr_we, csr_read; + logic [CVA6Cfg.XLEN-1:0] csr_wdata, csr_rdata; + riscv::priv_lvl_t trap_to_priv_lvl; + logic trap_to_v; + // register for enabling load store address translation, this is critical, hence the register + logic en_ld_st_translation_d, en_ld_st_translation_q; + logic en_ld_st_g_translation_d, en_ld_st_g_translation_q; + logic mprv; + logic mret; // return from M-mode exception + logic sret; // return from S-mode exception + logic dret; // return from debug mode + // CSR write causes us to mark the FPU state as dirty + logic dirty_fp_state_csr; + riscv::mstatus_rv_t mstatus_q, mstatus_d; + riscv::hstatus_rv_t hstatus_q, hstatus_d; + riscv::mstatus_rv_t vsstatus_q, vsstatus_d; + logic [CVA6Cfg.XLEN-1:0] mstatus_extended; + logic [CVA6Cfg.XLEN-1:0] vsstatus_extended; + satp_t satp_q, satp_d; + satp_t vsatp_q, vsatp_d; + hgatp_t hgatp_q, hgatp_d; + riscv::dcsr_t dcsr_q, dcsr_d; + riscv::csr_t csr_addr; + riscv::csr_t conv_csr_addr; + // privilege level register + riscv::priv_lvl_t priv_lvl_d, priv_lvl_q; + logic v_q, v_d; // virtualization mode + // we are in debug + logic debug_mode_q, debug_mode_d; + logic mtvec_rst_load_q; // used to determine whether we came out of reset + + logic [CVA6Cfg.XLEN-1:0] dpc_q, dpc_d; + logic [CVA6Cfg.XLEN-1:0] dscratch0_q, dscratch0_d; + logic [CVA6Cfg.XLEN-1:0] dscratch1_q, dscratch1_d; + logic [CVA6Cfg.XLEN-1:0] mtvec_q, mtvec_d; + logic [CVA6Cfg.XLEN-1:0] medeleg_q, medeleg_d; + logic [CVA6Cfg.XLEN-1:0] mideleg_q, mideleg_d; + logic [CVA6Cfg.XLEN-1:0] mip_q, mip_d; + logic [CVA6Cfg.XLEN-1:0] mie_q, mie_d; + logic [CVA6Cfg.XLEN-1:0] mcounteren_q, mcounteren_d; + logic [CVA6Cfg.XLEN-1:0] mscratch_q, mscratch_d; + logic [CVA6Cfg.XLEN-1:0] mepc_q, mepc_d; + logic [CVA6Cfg.XLEN-1:0] mcause_q, mcause_d; + logic [CVA6Cfg.XLEN-1:0] mtval_q, mtval_d; + logic [CVA6Cfg.XLEN-1:0] mtinst_q, mtinst_d; + logic [CVA6Cfg.XLEN-1:0] mtval2_q, mtval2_d; + logic fiom_d, fiom_q; + + logic [CVA6Cfg.XLEN-1:0] stvec_q, stvec_d; + logic [CVA6Cfg.XLEN-1:0] scounteren_q, scounteren_d; + logic [CVA6Cfg.XLEN-1:0] sscratch_q, sscratch_d; + logic [CVA6Cfg.XLEN-1:0] sepc_q, sepc_d; + logic [CVA6Cfg.XLEN-1:0] scause_q, scause_d; + logic [CVA6Cfg.XLEN-1:0] stval_q, stval_d; + + logic [CVA6Cfg.XLEN-1:0] hedeleg_q, hedeleg_d; + logic [CVA6Cfg.XLEN-1:0] hideleg_q, hideleg_d; + logic [CVA6Cfg.XLEN-1:0] hcounteren_q, hcounteren_d; + logic [CVA6Cfg.XLEN-1:0] hgeie_q, hgeie_d; + logic [CVA6Cfg.XLEN-1:0] htinst_q, htinst_d; + logic [CVA6Cfg.XLEN-1:0] htval_q, htval_d; + + logic [CVA6Cfg.XLEN-1:0] vstvec_q, vstvec_d; + logic [CVA6Cfg.XLEN-1:0] vsscratch_q, vsscratch_d; + logic [CVA6Cfg.XLEN-1:0] vsepc_q, vsepc_d; + logic [CVA6Cfg.XLEN-1:0] vscause_q, vscause_d; + logic [CVA6Cfg.XLEN-1:0] vstval_q, vstval_d; + + logic [CVA6Cfg.XLEN-1:0] dcache_q, dcache_d; + logic [CVA6Cfg.XLEN-1:0] icache_q, icache_d; + logic [CVA6Cfg.XLEN-1:0] acc_cons_q, acc_cons_d; + + logic wfi_d, wfi_q; + + logic [63:0] cycle_q, cycle_d; + logic [63:0] instret_q, instret_d; + + riscv::pmpcfg_t [63:0] pmpcfg_q, pmpcfg_d, pmpcfg_next; + logic [63:0][CVA6Cfg.PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; + logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; + + localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // B - Bitmanip extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension + | (CVA6Cfg.XLEN'(CVA6Cfg.RVH) << 7) // H - Hypervisor extension + | (CVA6Cfg.XLEN'(1) << 8) // I - RV32I/64I/128I base ISA + | (CVA6Cfg.XLEN'(1) << 12) // M - Integer Multiply/Divide extension + | (CVA6Cfg.XLEN'(0) << 13) // N - User level interrupts supported + | (CVA6Cfg.XLEN'(CVA6Cfg.RVS) << 18) // S - Supervisor mode implemented + | (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented + | (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension + | (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present + | ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL + + assign pmpcfg_o = pmpcfg_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0]; + assign pmpaddr_o = pmpaddr_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0]; + + riscv::fcsr_t fcsr_q, fcsr_d; + jvt_t jvt_q, jvt_d; + // ---------------- + // Assignments + // ---------------- + assign csr_addr = riscv::csr_t'(csr_addr_i); + assign conv_csr_addr = (CVA6Cfg.RVH) ? riscv::convert_vs_access_csr( + (riscv::csr_t'(csr_addr_i)), v_q + ) : csr_addr; + assign fs_o = mstatus_q.fs; + assign vfs_o = (CVA6Cfg.RVH) ? vsstatus_q.fs : riscv::Off; + assign vs_o = mstatus_q.vs; + // ---------------- + // CSR Read logic + // ---------------- + assign mstatus_extended = CVA6Cfg.IS_XLEN64 ? mstatus_q[CVA6Cfg.XLEN-1:0] : + {mstatus_q.sd, mstatus_q.wpri3[7:0], mstatus_q[22:0]}; + if (CVA6Cfg.RVH) begin + if (CVA6Cfg.IS_XLEN64) begin : gen_vsstatus_64read + assign vsstatus_extended = vsstatus_q[CVA6Cfg.XLEN-1:0]; + end else begin : gen_vsstatus_32read + assign vsstatus_extended = {vsstatus_q.sd, vsstatus_q.wpri3[7:0], vsstatus_q[22:0]}; + end + end else begin + assign vsstatus_extended = '0; + end + + always_comb begin : csr_read_process + // a read access exception can only occur if we attempt to read a CSR which does not exist + read_access_exception = 1'b0; + virtual_read_access_exception = 1'b0; + csr_rdata = '0; + perf_addr_o = csr_addr.address[11:0]; + + if (csr_read) begin + unique case (conv_csr_addr.address) + riscv::CSR_FFLAGS: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + csr_rdata = {{CVA6Cfg.XLEN - 5{1'b0}}, fcsr_q.fflags}; + end else begin + read_access_exception = 1'b1; + end + end + riscv::CSR_FRM: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + csr_rdata = {{CVA6Cfg.XLEN - 3{1'b0}}, fcsr_q.frm}; + end else begin + read_access_exception = 1'b1; + end + end + riscv::CSR_FCSR: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + csr_rdata = {{CVA6Cfg.XLEN - 8{1'b0}}, fcsr_q.frm, fcsr_q.fflags}; + end else begin + read_access_exception = 1'b1; + end + end + riscv::CSR_JVT: begin + if (CVA6Cfg.RVZCMT) begin + csr_rdata = {jvt_q.base, jvt_q.mode}; + end else begin + read_access_exception = 1'b1; + end + end + // non-standard extension + riscv::CSR_FTRAN: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + csr_rdata = {{CVA6Cfg.XLEN - 7{1'b0}}, fcsr_q.fprec}; + end else begin + read_access_exception = 1'b1; + end + end + // debug registers + riscv::CSR_DCSR: + if (CVA6Cfg.DebugEn) csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, dcsr_q}; + else read_access_exception = 1'b1; + riscv::CSR_DPC: + if (CVA6Cfg.DebugEn) csr_rdata = dpc_q; + else read_access_exception = 1'b1; + riscv::CSR_DSCRATCH0: + if (CVA6Cfg.DebugEn) csr_rdata = dscratch0_q; + else read_access_exception = 1'b1; + riscv::CSR_DSCRATCH1: + if (CVA6Cfg.DebugEn) csr_rdata = dscratch1_q; + else read_access_exception = 1'b1; + // trigger module registers + riscv::CSR_TSELECT: read_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA1: read_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA2: read_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA3: read_access_exception = 1'b1; // not implemented + riscv::CSR_VSSTATUS: + if (CVA6Cfg.RVH) csr_rdata = vsstatus_extended; + else read_access_exception = 1'b1; + riscv::CSR_VSIE: + if (CVA6Cfg.RVH) + csr_rdata = (mie_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1; + else read_access_exception = 1'b1; + riscv::CSR_VSIP: + if (CVA6Cfg.RVH) + csr_rdata = (mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] & hideleg_q) >> 1; + else read_access_exception = 1'b1; + riscv::CSR_VSTVEC: + if (CVA6Cfg.RVH) csr_rdata = vstvec_q; + else read_access_exception = 1'b1; + riscv::CSR_VSSCRATCH: + if (CVA6Cfg.RVH) csr_rdata = vsscratch_q; + else read_access_exception = 1'b1; + riscv::CSR_VSEPC: + if (CVA6Cfg.RVH) csr_rdata = vsepc_q; + else read_access_exception = 1'b1; + riscv::CSR_VSCAUSE: + if (CVA6Cfg.RVH) csr_rdata = vscause_q; + else read_access_exception = 1'b1; + riscv::CSR_VSTVAL: + if (CVA6Cfg.RVH) csr_rdata = vstval_q; + else read_access_exception = 1'b1; + riscv::CSR_VSATP: + // intercept reads to VSATP if in VS-Mode and VTVM is enabled + if (CVA6Cfg.RVH) begin + if (priv_lvl_o == riscv::PRIV_LVL_S && hstatus_q.vtvm && v_q) + virtual_read_access_exception = 1'b1; + else csr_rdata = vsatp_q; + end else begin + read_access_exception = 1'b1; + end + // supervisor registers + riscv::CSR_SSTATUS: begin + if (CVA6Cfg.RVS) csr_rdata = mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + end + riscv::CSR_SIE: + if (CVA6Cfg.RVS) + csr_rdata = (CVA6Cfg.RVH) ? mie_q & mideleg_q & ~HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] : mie_q & mideleg_q; + else read_access_exception = 1'b1; + riscv::CSR_SIP: + if (CVA6Cfg.RVS) + csr_rdata = (CVA6Cfg.RVH) ? mip_q & mideleg_q & ~HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] : mip_q & mideleg_q; + else read_access_exception = 1'b1; + riscv::CSR_STVEC: + if (CVA6Cfg.RVS) csr_rdata = stvec_q; + else read_access_exception = 1'b1; + riscv::CSR_SCOUNTEREN: + if (CVA6Cfg.RVS) csr_rdata = scounteren_q; + else read_access_exception = 1'b1; + riscv::CSR_SSCRATCH: + if (CVA6Cfg.RVS) csr_rdata = sscratch_q; + else read_access_exception = 1'b1; + riscv::CSR_SEPC: + if (CVA6Cfg.RVS) csr_rdata = sepc_q; + else read_access_exception = 1'b1; + riscv::CSR_SCAUSE: + if (CVA6Cfg.RVS) csr_rdata = scause_q; + else read_access_exception = 1'b1; + riscv::CSR_STVAL: + if (CVA6Cfg.RVS) csr_rdata = stval_q; + else read_access_exception = 1'b1; + riscv::CSR_SATP: begin + if (CVA6Cfg.RVS) begin + // intercept reads to SATP if in S-Mode and TVM is enabled + if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) begin + read_access_exception = 1'b1; + end else begin + csr_rdata = satp_q; + end + end else begin + read_access_exception = 1'b1; + end + end + riscv::CSR_SENVCFG: + if (CVA6Cfg.RVS) csr_rdata = '0 | fiom_q; + else read_access_exception = 1'b1; + // hypervisor mode registers + riscv::CSR_HSTATUS: + if (CVA6Cfg.RVH) csr_rdata = hstatus_q[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_HEDELEG: + if (CVA6Cfg.RVH) csr_rdata = hedeleg_q; + else read_access_exception = 1'b1; + riscv::CSR_HIDELEG: + if (CVA6Cfg.RVH) csr_rdata = hideleg_q; + else read_access_exception = 1'b1; + riscv::CSR_HIE: + if (CVA6Cfg.RVH) csr_rdata = mie_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_HIP: + if (CVA6Cfg.RVH) csr_rdata = mip_q & HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_HVIP: + if (CVA6Cfg.RVH) csr_rdata = mip_q & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_HCOUNTEREN: + if (CVA6Cfg.RVH) csr_rdata = hcounteren_q; + else read_access_exception = 1'b1; + riscv::CSR_HTVAL: + if (CVA6Cfg.RVH) csr_rdata = htval_q; + else read_access_exception = 1'b1; + riscv::CSR_HTINST: + if (CVA6Cfg.RVH) csr_rdata = htinst_q; + else read_access_exception = 1'b1; + riscv::CSR_HGEIE: + if (CVA6Cfg.RVH) csr_rdata = '0; + else read_access_exception = 1'b1; + riscv::CSR_HGEIP: + if (CVA6Cfg.RVH) csr_rdata = '0; + else read_access_exception = 1'b1; + riscv::CSR_HENVCFG: + if (CVA6Cfg.RVH) csr_rdata = '0 | {{CVA6Cfg.XLEN - 1{1'b0}}, fiom_q}; + else read_access_exception = 1'b1; + riscv::CSR_HGATP: begin + if (CVA6Cfg.RVH) begin + // intercept reads to HGATP if in HS-Mode and TVM is enabled + if (priv_lvl_o == riscv::PRIV_LVL_S && !v_q && mstatus_q.tvm) begin + read_access_exception = 1'b1; + end else begin + csr_rdata = hgatp_q; + end + end else begin + read_access_exception = 1'b1; + end + end + + // machine mode registers + riscv::CSR_MSTATUS: csr_rdata = mstatus_extended; + riscv::CSR_MSTATUSH: + if (CVA6Cfg.XLEN == 32) csr_rdata = '0; + else read_access_exception = 1'b1; + riscv::CSR_MISA: csr_rdata = IsaCode; + riscv::CSR_MEDELEG: + if (CVA6Cfg.RVS) csr_rdata = medeleg_q; + else read_access_exception = 1'b1; + riscv::CSR_MIDELEG: + if (CVA6Cfg.RVS) csr_rdata = mideleg_q; + else read_access_exception = 1'b1; + riscv::CSR_MIE: csr_rdata = mie_q; + riscv::CSR_MTVEC: csr_rdata = mtvec_q; + riscv::CSR_MCOUNTEREN: + if (CVA6Cfg.RVU) csr_rdata = mcounteren_q; + else read_access_exception = 1'b1; + riscv::CSR_MSCRATCH: csr_rdata = mscratch_q; + riscv::CSR_MEPC: csr_rdata = mepc_q; + riscv::CSR_MCAUSE: csr_rdata = mcause_q; + riscv::CSR_MTVAL: + if (CVA6Cfg.TvalEn) csr_rdata = mtval_q; + else csr_rdata = '0; + riscv::CSR_MTINST: + if (CVA6Cfg.RVH) csr_rdata = mtinst_q; + else read_access_exception = 1'b1; + riscv::CSR_MTVAL2: + if (CVA6Cfg.RVH) csr_rdata = mtval2_q; + else read_access_exception = 1'b1; + riscv::CSR_MIP: csr_rdata = mip_q; + riscv::CSR_MENVCFG: begin + if (CVA6Cfg.RVU) csr_rdata = '0 | fiom_q; + else read_access_exception = 1'b1; + end + riscv::CSR_MENVCFGH: begin + if (CVA6Cfg.RVU && CVA6Cfg.XLEN == 32) csr_rdata = '0; + else read_access_exception = 1'b1; + end + riscv::CSR_MVENDORID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID}; + riscv::CSR_MARCHID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID}; + riscv::CSR_MIMPID: csr_rdata = '0; // not implemented + riscv::CSR_MHARTID: csr_rdata = hart_id_i; + riscv::CSR_MCONFIGPTR: csr_rdata = '0; // not implemented + riscv::CSR_MCOUNTINHIBIT: + csr_rdata = {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, mcountinhibit_q}; + // Counters and Timers + riscv::CSR_MCYCLE: csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0]; + riscv::CSR_MCYCLEH: + if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32]; + else read_access_exception = 1'b1; + riscv::CSR_MINSTRET: csr_rdata = instret_q[CVA6Cfg.XLEN-1:0]; + riscv::CSR_MINSTRETH: + if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32]; + else read_access_exception = 1'b1; + riscv::CSR_CYCLE: + if (CVA6Cfg.RVZicntr) csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_CYCLEH: + if (CVA6Cfg.RVZicntr) + if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32]; + else read_access_exception = 1'b1; + else read_access_exception = 1'b1; + riscv::CSR_INSTRET: + if (CVA6Cfg.RVZicntr) csr_rdata = instret_q[CVA6Cfg.XLEN-1:0]; + else read_access_exception = 1'b1; + riscv::CSR_INSTRETH: + if (CVA6Cfg.RVZicntr) + if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32]; + else read_access_exception = 1'b1; + else read_access_exception = 1'b1; + //Event Selector + riscv::CSR_MHPM_EVENT_3, + riscv::CSR_MHPM_EVENT_4, + riscv::CSR_MHPM_EVENT_5, + riscv::CSR_MHPM_EVENT_6, + riscv::CSR_MHPM_EVENT_7, + riscv::CSR_MHPM_EVENT_8, + riscv::CSR_MHPM_EVENT_9, + riscv::CSR_MHPM_EVENT_10, + riscv::CSR_MHPM_EVENT_11, + riscv::CSR_MHPM_EVENT_12, + riscv::CSR_MHPM_EVENT_13, + riscv::CSR_MHPM_EVENT_14, + riscv::CSR_MHPM_EVENT_15, + riscv::CSR_MHPM_EVENT_16, + riscv::CSR_MHPM_EVENT_17, + riscv::CSR_MHPM_EVENT_18, + riscv::CSR_MHPM_EVENT_19, + riscv::CSR_MHPM_EVENT_20, + riscv::CSR_MHPM_EVENT_21, + riscv::CSR_MHPM_EVENT_22, + riscv::CSR_MHPM_EVENT_23, + riscv::CSR_MHPM_EVENT_24, + riscv::CSR_MHPM_EVENT_25, + riscv::CSR_MHPM_EVENT_26, + riscv::CSR_MHPM_EVENT_27, + riscv::CSR_MHPM_EVENT_28, + riscv::CSR_MHPM_EVENT_29, + riscv::CSR_MHPM_EVENT_30, + riscv::CSR_MHPM_EVENT_31 : + csr_rdata = perf_data_i; + + riscv::CSR_MHPM_COUNTER_3, + riscv::CSR_MHPM_COUNTER_4, + riscv::CSR_MHPM_COUNTER_5, + riscv::CSR_MHPM_COUNTER_6, + riscv::CSR_MHPM_COUNTER_7, + riscv::CSR_MHPM_COUNTER_8, + riscv::CSR_MHPM_COUNTER_9, + riscv::CSR_MHPM_COUNTER_10, + riscv::CSR_MHPM_COUNTER_11, + riscv::CSR_MHPM_COUNTER_12, + riscv::CSR_MHPM_COUNTER_13, + riscv::CSR_MHPM_COUNTER_14, + riscv::CSR_MHPM_COUNTER_15, + riscv::CSR_MHPM_COUNTER_16, + riscv::CSR_MHPM_COUNTER_17, + riscv::CSR_MHPM_COUNTER_18, + riscv::CSR_MHPM_COUNTER_19, + riscv::CSR_MHPM_COUNTER_20, + riscv::CSR_MHPM_COUNTER_21, + riscv::CSR_MHPM_COUNTER_22, + riscv::CSR_MHPM_COUNTER_23, + riscv::CSR_MHPM_COUNTER_24, + riscv::CSR_MHPM_COUNTER_25, + riscv::CSR_MHPM_COUNTER_26, + riscv::CSR_MHPM_COUNTER_27, + riscv::CSR_MHPM_COUNTER_28, + riscv::CSR_MHPM_COUNTER_29, + riscv::CSR_MHPM_COUNTER_30, + riscv::CSR_MHPM_COUNTER_31 : + csr_rdata = perf_data_i; + + riscv::CSR_MHPM_COUNTER_3H, + riscv::CSR_MHPM_COUNTER_4H, + riscv::CSR_MHPM_COUNTER_5H, + riscv::CSR_MHPM_COUNTER_6H, + riscv::CSR_MHPM_COUNTER_7H, + riscv::CSR_MHPM_COUNTER_8H, + riscv::CSR_MHPM_COUNTER_9H, + riscv::CSR_MHPM_COUNTER_10H, + riscv::CSR_MHPM_COUNTER_11H, + riscv::CSR_MHPM_COUNTER_12H, + riscv::CSR_MHPM_COUNTER_13H, + riscv::CSR_MHPM_COUNTER_14H, + riscv::CSR_MHPM_COUNTER_15H, + riscv::CSR_MHPM_COUNTER_16H, + riscv::CSR_MHPM_COUNTER_17H, + riscv::CSR_MHPM_COUNTER_18H, + riscv::CSR_MHPM_COUNTER_19H, + riscv::CSR_MHPM_COUNTER_20H, + riscv::CSR_MHPM_COUNTER_21H, + riscv::CSR_MHPM_COUNTER_22H, + riscv::CSR_MHPM_COUNTER_23H, + riscv::CSR_MHPM_COUNTER_24H, + riscv::CSR_MHPM_COUNTER_25H, + riscv::CSR_MHPM_COUNTER_26H, + riscv::CSR_MHPM_COUNTER_27H, + riscv::CSR_MHPM_COUNTER_28H, + riscv::CSR_MHPM_COUNTER_29H, + riscv::CSR_MHPM_COUNTER_30H, + riscv::CSR_MHPM_COUNTER_31H : + if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i; + else read_access_exception = 1'b1; + + // Performance counters (User Mode - R/O Shadows) + riscv::CSR_HPM_COUNTER_3, + riscv::CSR_HPM_COUNTER_4, + riscv::CSR_HPM_COUNTER_5, + riscv::CSR_HPM_COUNTER_6, + riscv::CSR_HPM_COUNTER_7, + riscv::CSR_HPM_COUNTER_8, + riscv::CSR_HPM_COUNTER_9, + riscv::CSR_HPM_COUNTER_10, + riscv::CSR_HPM_COUNTER_11, + riscv::CSR_HPM_COUNTER_12, + riscv::CSR_HPM_COUNTER_13, + riscv::CSR_HPM_COUNTER_14, + riscv::CSR_HPM_COUNTER_15, + riscv::CSR_HPM_COUNTER_16, + riscv::CSR_HPM_COUNTER_17, + riscv::CSR_HPM_COUNTER_18, + riscv::CSR_HPM_COUNTER_19, + riscv::CSR_HPM_COUNTER_20, + riscv::CSR_HPM_COUNTER_21, + riscv::CSR_HPM_COUNTER_22, + riscv::CSR_HPM_COUNTER_23, + riscv::CSR_HPM_COUNTER_24, + riscv::CSR_HPM_COUNTER_25, + riscv::CSR_HPM_COUNTER_26, + riscv::CSR_HPM_COUNTER_27, + riscv::CSR_HPM_COUNTER_28, + riscv::CSR_HPM_COUNTER_29, + riscv::CSR_HPM_COUNTER_30, + riscv::CSR_HPM_COUNTER_31 : + if (CVA6Cfg.RVZihpm) begin + csr_rdata = perf_data_i; + end else begin + read_access_exception = 1'b1; + end + + riscv::CSR_HPM_COUNTER_3H, + riscv::CSR_HPM_COUNTER_4H, + riscv::CSR_HPM_COUNTER_5H, + riscv::CSR_HPM_COUNTER_6H, + riscv::CSR_HPM_COUNTER_7H, + riscv::CSR_HPM_COUNTER_8H, + riscv::CSR_HPM_COUNTER_9H, + riscv::CSR_HPM_COUNTER_10H, + riscv::CSR_HPM_COUNTER_11H, + riscv::CSR_HPM_COUNTER_12H, + riscv::CSR_HPM_COUNTER_13H, + riscv::CSR_HPM_COUNTER_14H, + riscv::CSR_HPM_COUNTER_15H, + riscv::CSR_HPM_COUNTER_16H, + riscv::CSR_HPM_COUNTER_17H, + riscv::CSR_HPM_COUNTER_18H, + riscv::CSR_HPM_COUNTER_19H, + riscv::CSR_HPM_COUNTER_20H, + riscv::CSR_HPM_COUNTER_21H, + riscv::CSR_HPM_COUNTER_22H, + riscv::CSR_HPM_COUNTER_23H, + riscv::CSR_HPM_COUNTER_24H, + riscv::CSR_HPM_COUNTER_25H, + riscv::CSR_HPM_COUNTER_26H, + riscv::CSR_HPM_COUNTER_27H, + riscv::CSR_HPM_COUNTER_28H, + riscv::CSR_HPM_COUNTER_29H, + riscv::CSR_HPM_COUNTER_30H, + riscv::CSR_HPM_COUNTER_31H : + if (CVA6Cfg.RVZihpm) begin + if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i; + else read_access_exception = 1'b1; + end else begin + read_access_exception = 1'b1; + end + + // custom (non RISC-V) cache control + riscv::CSR_DCACHE: csr_rdata = dcache_q; + riscv::CSR_ICACHE: csr_rdata = icache_q; + // custom (non RISC-V) accelerator memory consistency mode + riscv::CSR_ACC_CONS: begin + if (CVA6Cfg.EnableAccelerator) begin + csr_rdata = acc_cons_q; + end else begin + read_access_exception = 1'b1; + end + end + // PMPs + riscv::CSR_PMPCFG0, + riscv::CSR_PMPCFG1, + riscv::CSR_PMPCFG2, + riscv::CSR_PMPCFG3, + riscv::CSR_PMPCFG4, + riscv::CSR_PMPCFG5, + riscv::CSR_PMPCFG6, + riscv::CSR_PMPCFG7, + riscv::CSR_PMPCFG8, + riscv::CSR_PMPCFG9, + riscv::CSR_PMPCFG10, + riscv::CSR_PMPCFG11, + riscv::CSR_PMPCFG12, + riscv::CSR_PMPCFG13, + riscv::CSR_PMPCFG14, + riscv::CSR_PMPCFG15: begin + // index is calculated using PMPCFG0 as the offset + automatic logic [3:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; + + // if index is not even and XLEN==64, raise exception + if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) read_access_exception = 1'b1; + else begin + // The following line has no effect. It's here just to prevent the synthesizer from crashing + if (CVA6Cfg.XLEN == 64) index = (index >> 1) << 1; + csr_rdata = pmpcfg_q[index*4+:CVA6Cfg.XLEN/8]; + end + end + // PMPADDR + riscv::CSR_PMPADDR0, + riscv::CSR_PMPADDR1, + riscv::CSR_PMPADDR2, + riscv::CSR_PMPADDR3, + riscv::CSR_PMPADDR4, + riscv::CSR_PMPADDR5, + riscv::CSR_PMPADDR6, + riscv::CSR_PMPADDR7, + riscv::CSR_PMPADDR8, + riscv::CSR_PMPADDR9, + riscv::CSR_PMPADDR10, + riscv::CSR_PMPADDR11, + riscv::CSR_PMPADDR12, + riscv::CSR_PMPADDR13, + riscv::CSR_PMPADDR14, + riscv::CSR_PMPADDR15, + riscv::CSR_PMPADDR16, + riscv::CSR_PMPADDR17, + riscv::CSR_PMPADDR18, + riscv::CSR_PMPADDR19, + riscv::CSR_PMPADDR20, + riscv::CSR_PMPADDR21, + riscv::CSR_PMPADDR22, + riscv::CSR_PMPADDR23, + riscv::CSR_PMPADDR24, + riscv::CSR_PMPADDR25, + riscv::CSR_PMPADDR26, + riscv::CSR_PMPADDR27, + riscv::CSR_PMPADDR28, + riscv::CSR_PMPADDR29, + riscv::CSR_PMPADDR30, + riscv::CSR_PMPADDR31, + riscv::CSR_PMPADDR32, + riscv::CSR_PMPADDR33, + riscv::CSR_PMPADDR34, + riscv::CSR_PMPADDR35, + riscv::CSR_PMPADDR36, + riscv::CSR_PMPADDR37, + riscv::CSR_PMPADDR38, + riscv::CSR_PMPADDR39, + riscv::CSR_PMPADDR40, + riscv::CSR_PMPADDR41, + riscv::CSR_PMPADDR42, + riscv::CSR_PMPADDR43, + riscv::CSR_PMPADDR44, + riscv::CSR_PMPADDR45, + riscv::CSR_PMPADDR46, + riscv::CSR_PMPADDR47, + riscv::CSR_PMPADDR48, + riscv::CSR_PMPADDR49, + riscv::CSR_PMPADDR50, + riscv::CSR_PMPADDR51, + riscv::CSR_PMPADDR52, + riscv::CSR_PMPADDR53, + riscv::CSR_PMPADDR54, + riscv::CSR_PMPADDR55, + riscv::CSR_PMPADDR56, + riscv::CSR_PMPADDR57, + riscv::CSR_PMPADDR58, + riscv::CSR_PMPADDR59, + riscv::CSR_PMPADDR60, + riscv::CSR_PMPADDR61, + riscv::CSR_PMPADDR62, + riscv::CSR_PMPADDR63: begin + // index is calculated using PMPADDR0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0; + // Important: we only support granularity 8 bytes (G=1) + // -> last bit of pmpaddr must be set 0/1 based on the mode: + // NA4, NAPOT: 1 + // TOR, OFF: 0 + if (pmpcfg_q[index].addr_mode[1] == 1'b1) + csr_rdata = {pmpaddr_q[index][CVA6Cfg.PLEN-3:1], 1'b1}; + else csr_rdata = {pmpaddr_q[index][CVA6Cfg.PLEN-3:1], 1'b0}; + end + default: read_access_exception = 1'b1; + endcase + end + end + // --------------------------- + // CSR Write and update logic + // --------------------------- + logic [CVA6Cfg.XLEN-1:0] mask; + always_comb begin : csr_update + automatic satp_t satp; + automatic satp_t vsatp; + automatic hgatp_t hgatp; + automatic logic [63:0] instret; + + if (CVA6Cfg.RVS) begin + satp = satp_q; + end + if (CVA6Cfg.RVH) begin + hgatp = hgatp_q; + vsatp = vsatp_q; + end + instret = instret_q; + + mcountinhibit_d = mcountinhibit_q; + + // -------------------- + // Counters + // -------------------- + cycle_d = cycle_q; + instret_d = instret_q; + if (!(CVA6Cfg.DebugEn && debug_mode_q)) begin + // increase instruction retired counter + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2]))) + instret++; + end + instret_d = instret; + // increment the cycle count + if (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[0])) + cycle_d = cycle_q + 1'b1; + else cycle_d = cycle_q; + end + + eret_o = 1'b0; + flush_o = 1'b0; + update_access_exception = 1'b0; + virtual_update_access_exception = 1'b0; + + set_debug_pc_o = 1'b0; + + perf_we_o = 1'b0; + perf_data_o = 'b0; + if (CVA6Cfg.RVZCMT) begin + jvt_d = jvt_q; + end + fcsr_d = fcsr_q; + + priv_lvl_d = priv_lvl_q; + v_d = v_q; + debug_mode_d = debug_mode_q; + + if (CVA6Cfg.DebugEn) begin + dcsr_d = dcsr_q; + dpc_d = dpc_q; + dscratch0_d = dscratch0_q; + dscratch1_d = dscratch1_q; + end + mstatus_d = mstatus_q; + if (CVA6Cfg.RVH) begin + hstatus_d = hstatus_q; + vsstatus_d = vsstatus_q; + end + + // check whether we come out of reset + // this is a workaround. some tools have issues + // having boot_addr_i in the asynchronous + // reset assignment to mtvec_d, even though + // boot_addr_i will be assigned a constant + // on the top-level. + if (mtvec_rst_load_q) begin + mtvec_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, boot_addr_i} + 'h40; + end else begin + mtvec_d = mtvec_q; + end + + if (CVA6Cfg.RVS) begin + medeleg_d = medeleg_q; + mideleg_d = mideleg_q; + end + mip_d = mip_q; + mie_d = mie_q; + mepc_d = mepc_q; + mcause_d = mcause_q; + mcounteren_d = mcounteren_q; + mscratch_d = mscratch_q; + if (CVA6Cfg.TvalEn) mtval_d = mtval_q; + if (CVA6Cfg.RVH) begin + mtinst_d = mtinst_q; + mtval2_d = mtval2_q; + end + + fiom_d = fiom_q; + dcache_d = dcache_q; + icache_d = icache_q; + acc_cons_d = acc_cons_q; + + if (CVA6Cfg.RVH) begin + vstvec_d = vstvec_q; + vsscratch_d = vsscratch_q; + vsepc_d = vsepc_q; + vscause_d = vscause_q; + vstval_d = vstval_q; + vsatp_d = vsatp_q; + hgatp_d = hgatp_q; + hedeleg_d = hedeleg_q; + hideleg_d = hideleg_q; + hgeie_d = hgeie_q; + hcounteren_d = hcounteren_q; + htinst_d = htinst_q; + htval_d = htval_q; + en_ld_st_g_translation_d = en_ld_st_g_translation_q; + end + + if (CVA6Cfg.RVS) begin + sepc_d = sepc_q; + scause_d = scause_q; + stvec_d = stvec_q; + scounteren_d = scounteren_q; + sscratch_d = sscratch_q; + stval_d = stval_q; + satp_d = satp_q; + end + + en_ld_st_translation_d = en_ld_st_translation_q; + dirty_fp_state_csr = 1'b0; + + pmpcfg_d = pmpcfg_q; + pmpaddr_d = pmpaddr_q; + + // check for correct access rights and that we are writing + if (csr_we) begin + unique case (conv_csr_addr.address) + // Floating-Point + riscv::CSR_FFLAGS: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + dirty_fp_state_csr = 1'b1; + fcsr_d.fflags = csr_wdata[4:0]; + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_FRM: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + dirty_fp_state_csr = 1'b1; + fcsr_d.frm = csr_wdata[2:0]; + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_FCSR: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + dirty_fp_state_csr = 1'b1; + fcsr_d[7:0] = csr_wdata[7:0]; // ignore writes to reserved space + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_FTRAN: begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin + dirty_fp_state_csr = 1'b1; + fcsr_d.fprec = csr_wdata[6:0]; // ignore writes to reserved space + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + // debug CSR + riscv::CSR_DCSR: begin + if (CVA6Cfg.DebugEn) begin + dcsr_d = csr_wdata[31:0]; + // debug is implemented + dcsr_d.xdebugver = 4'h4; + // currently not supported + dcsr_d.nmip = 1'b0; + dcsr_d.stopcount = 1'b0; + dcsr_d.stoptime = 1'b0; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_DPC: + if (CVA6Cfg.DebugEn) dpc_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_DSCRATCH0: + if (CVA6Cfg.DebugEn) dscratch0_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_DSCRATCH1: + if (CVA6Cfg.DebugEn) dscratch1_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_JVT: begin + if (CVA6Cfg.RVZCMT) begin + jvt_d.base = csr_wdata[CVA6Cfg.XLEN-1:6]; + jvt_d.mode = 6'b000000; + end else begin + update_access_exception = 1'b1; + end + end + // trigger module CSRs + riscv::CSR_TSELECT: update_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA1: update_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA2: update_access_exception = 1'b1; // not implemented + riscv::CSR_TDATA3: update_access_exception = 1'b1; // not implemented + // virtual supervisor registers + riscv::CSR_VSSTATUS: begin + if (CVA6Cfg.RVH) begin + mask = ariane_pkg::SMODE_STATUS_WRITE_MASK[CVA6Cfg.XLEN-1:0]; + vsstatus_d = (vsstatus_q & ~{{64-CVA6Cfg.XLEN{1'b0}}, mask}) | {{64-CVA6Cfg.XLEN{1'b0}}, (csr_wdata & mask)}; + // hardwire to zero if floating point extension is not present + vsstatus_d.xs = riscv::Off; + if (!CVA6Cfg.FpPresent) begin + vsstatus_d.fs = riscv::Off; + end + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_VSIE: + if (CVA6Cfg.RVH) mie_d = (mie_q & ~hideleg_q) | ((csr_wdata << 1) & hideleg_q); + else update_access_exception = 1'b1; + riscv::CSR_VSIP: begin + if (CVA6Cfg.RVH) begin + // only the virtual supervisor software interrupt is write-able, iff delegated + mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP) & hideleg_q; + mip_d = (mip_q & ~mask) | ((csr_wdata << 1) & mask); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_VSTVEC: begin + if (CVA6Cfg.RVH) begin + vstvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, csr_wdata[0]}; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_VSSCRATCH: + if (CVA6Cfg.RVH) vsscratch_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_VSEPC: + if (CVA6Cfg.RVH) vsepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; + else update_access_exception = 1'b1; + riscv::CSR_VSCAUSE: + if (CVA6Cfg.RVH) vscause_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_VSTVAL: + if (CVA6Cfg.RVH) vstval_d = csr_wdata; + else update_access_exception = 1'b1; + // virtual supervisor address translation and protection + riscv::CSR_VSATP: begin + if (CVA6Cfg.RVH) begin + if (priv_lvl_o == riscv::PRIV_LVL_S && hstatus_q.vtvm && v_q) begin + virtual_update_access_exception = 1'b1; + end else begin + vsatp = satp_t'(csr_wdata); + // only make ASID_LEN - 1 bit stick, that way software can figure out how many ASID bits are supported + vsatp.asid = vsatp.asid & {{(CVA6Cfg.ASIDW - CVA6Cfg.ASID_WIDTH) {1'b0}}, {CVA6Cfg.ASID_WIDTH{1'b1}}}; + // only update if we actually support this mode + if (config_pkg::vm_mode_t'(vsatp.mode) == config_pkg::ModeOff || + config_pkg::vm_mode_t'(vsatp.mode) == CVA6Cfg.MODE_SV) + vsatp_d = vsatp; + end + // changing the mode can have side-effects on address translation (e.g.: other instructions), re-fetch + // the next instruction by executing a flush + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + // sstatus is a subset of mstatus - mask it accordingly + riscv::CSR_SSTATUS: begin + if (CVA6Cfg.RVS) begin + mask = ariane_pkg::SMODE_STATUS_WRITE_MASK[CVA6Cfg.XLEN-1:0]; + mstatus_d = (mstatus_q & ~{{64-CVA6Cfg.XLEN{1'b0}}, mask}) | {{64-CVA6Cfg.XLEN{1'b0}}, (csr_wdata & mask)}; + // hardwire to zero if floating point extension is not present + if (!CVA6Cfg.FpPresent) begin + mstatus_d.fs = riscv::Off; + end + // hardwire to zero if vector extension is not present + if (!CVA6Cfg.RVV) begin + mstatus_d.vs = riscv::Off; + end + // If h-extension is not enabled, priv level HS is reserved + if (!CVA6Cfg.RVH) begin + if (mstatus_d.mpp == riscv::PRIV_LVL_HS) begin + mstatus_d.mpp = mstatus_q.mpp; + end + end + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + // even machine mode interrupts can be visible and set-able to supervisor + // if the corresponding bit in mideleg is set + riscv::CSR_SIE: begin + if (CVA6Cfg.RVS) begin + mask = (CVA6Cfg.RVH) ? mideleg_q & ~HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] : mideleg_q; + // the mideleg makes sure only delegate-able register (and therefore also only implemented registers) are written + mie_d = (mie_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + + riscv::CSR_SIP: begin + if (CVA6Cfg.RVS) begin + // only the supervisor software interrupt is write-able, iff delegated + mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP) & mideleg_q; + mip_d = (mip_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + + riscv::CSR_STVEC: + if (CVA6Cfg.RVS) stvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, csr_wdata[0]}; + else update_access_exception = 1'b1; + riscv::CSR_SCOUNTEREN: + if (CVA6Cfg.RVS) scounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + else update_access_exception = 1'b1; + riscv::CSR_SSCRATCH: + if (CVA6Cfg.RVS) sscratch_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_SEPC: + if (CVA6Cfg.RVS) sepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; + else update_access_exception = 1'b1; + riscv::CSR_SCAUSE: + if (CVA6Cfg.RVS) scause_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_STVAL: + if (CVA6Cfg.RVS && CVA6Cfg.TvalEn) stval_d = csr_wdata; + else update_access_exception = 1'b1; + // supervisor address translation and protection + riscv::CSR_SATP: begin + if (CVA6Cfg.RVS) begin + // intercept SATP writes if in S-Mode and TVM is enabled + if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) update_access_exception = 1'b1; + else begin + satp = satp_t'(csr_wdata); + // only make ASID_LEN - 1 bit stick, that way software can figure out how many ASID bits are supported + satp.asid = satp.asid & {{(CVA6Cfg.ASIDW - CVA6Cfg.ASID_WIDTH) {1'b0}}, {CVA6Cfg.ASID_WIDTH{1'b1}}}; + // only update if we actually support this mode + if (config_pkg::vm_mode_t'(satp.mode) == config_pkg::ModeOff || + config_pkg::vm_mode_t'(satp.mode) == CVA6Cfg.MODE_SV) + satp_d = satp; + end + // changing the mode can have side-effects on address translation (e.g.: other instructions), re-fetch + // the next instruction by executing a flush + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_SENVCFG: + if (CVA6Cfg.RVU) fiom_d = csr_wdata[0]; + else update_access_exception = 1'b1; + //hypervisor mode registers + riscv::CSR_HSTATUS: begin + if (CVA6Cfg.RVH) begin + mask = ariane_pkg::HSTATUS_WRITE_MASK[CVA6Cfg.XLEN-1:0]; + hstatus_d = (hstatus_q & ~{{64-CVA6Cfg.XLEN{1'b0}}, mask}) | {{64-CVA6Cfg.XLEN{1'b0}}, (csr_wdata & mask)}; + // this instruction has side-effects + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HEDELEG: begin + if (CVA6Cfg.RVH) begin + mask = (1 << riscv::INSTR_ADDR_MISALIGNED) | + (1 << riscv::INSTR_ACCESS_FAULT) | + (1 << riscv::ILLEGAL_INSTR) | + (1 << riscv::BREAKPOINT) | + (1 << riscv::LD_ADDR_MISALIGNED) | + (1 << riscv::LD_ACCESS_FAULT) | + (1 << riscv::ST_ADDR_MISALIGNED) | + (1 << riscv::ST_ACCESS_FAULT) | + (1 << riscv::ENV_CALL_UMODE) | + (1 << riscv::INSTR_PAGE_FAULT) | + (1 << riscv::LOAD_PAGE_FAULT) | + (1 << riscv::STORE_PAGE_FAULT); + hedeleg_d = (hedeleg_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HIDELEG: begin + if (CVA6Cfg.RVH) begin + hideleg_d = (hideleg_q & ~VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]) | (csr_wdata & VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HIE: begin + if (CVA6Cfg.RVH) begin + mask = HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + mie_d = (mie_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HIP: begin + if (CVA6Cfg.RVH) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_VSSIP); + mip_d = (mip_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HVIP: begin + if (CVA6Cfg.RVH) begin + mask = VS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + mip_d = (mip_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HCOUNTEREN: begin + if (CVA6Cfg.RVH) begin + hcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HTVAL: begin + if (CVA6Cfg.RVH) begin + htval_d = csr_wdata; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HTINST: begin + if (CVA6Cfg.RVH) begin + htinst_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + end else begin + update_access_exception = 1'b1; + end + end + //TODO Hyp: implement hgeie write + riscv::CSR_HGEIE: begin + if (!CVA6Cfg.RVH) begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HGATP: begin + if (CVA6Cfg.RVH) begin + // intercept HGATP writes if in HS-Mode and TVM is enabled + if (priv_lvl_o == riscv::PRIV_LVL_S && !v_q && mstatus_q.tvm) + update_access_exception = 1'b1; + else begin + hgatp = hgatp_t'(csr_wdata); + //hardwire PPN[1:0] to zero + hgatp[1:0] = 2'b0; + // only make VMID_LEN - 1 bit stick, that way software can figure out how many VMID bits are supported + hgatp.vmid = hgatp.vmid & {{(CVA6Cfg.VMIDW - CVA6Cfg.VMID_WIDTH) {1'b0}}, {CVA6Cfg.VMID_WIDTH{1'b1}}}; + // only update if we actually support this mode + if (config_pkg::vm_mode_t'(hgatp.mode) == config_pkg::ModeOff || + config_pkg::vm_mode_t'(hgatp.mode) == CVA6Cfg.MODE_SV) + hgatp_d = hgatp; + end + // changing the mode can have side-effects on address translation (e.g.: other instructions), re-fetch + // the next instruction by executing a flush + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_HENVCFG: + if (CVA6Cfg.RVH) fiom_d = csr_wdata[0]; + else update_access_exception = 1'b1; + riscv::CSR_MSTATUS: begin + mstatus_d = {{64 - CVA6Cfg.XLEN{1'b0}}, csr_wdata}; + mstatus_d.xs = riscv::Off; + if (!CVA6Cfg.FpPresent) begin + mstatus_d.fs = riscv::Off; + end + if (!CVA6Cfg.RVV) begin + mstatus_d.vs = riscv::Off; + end + if (!CVA6Cfg.RVS) begin + mstatus_d.sie = riscv::Off; + mstatus_d.spie = riscv::Off; + mstatus_d.spp = riscv::Off; + mstatus_d.sum = riscv::Off; + mstatus_d.mxr = riscv::Off; + mstatus_d.tvm = riscv::Off; + mstatus_d.tsr = riscv::Off; + end + if (!CVA6Cfg.RVU) begin + mstatus_d.tw = riscv::Off; + mstatus_d.mprv = riscv::Off; + end + if ((!CVA6Cfg.RVH & mstatus_d.mpp == riscv::PRIV_LVL_HS) | + (!CVA6Cfg.RVS & mstatus_d.mpp == riscv::PRIV_LVL_S) | + (!CVA6Cfg.RVU & mstatus_d.mpp == riscv::PRIV_LVL_U)) begin + mstatus_d.mpp = mstatus_q.mpp; + end + mstatus_d.wpri3 = 9'b0; + mstatus_d.wpri1 = 1'b0; + mstatus_d.wpri2 = 1'b0; + mstatus_d.wpri0 = 1'b0; + mstatus_d.ube = 1'b0; // CVA6 is little-endian + // this register has side-effects on other registers, flush the pipeline + flush_o = 1'b1; + end + riscv::CSR_MSTATUSH: if (CVA6Cfg.XLEN != 32) update_access_exception = 1'b1; + // MISA is WARL (Write Any Value, Reads Legal Value) + riscv::CSR_MISA: ; + // machine exception delegation register + // 0 - 15 exceptions supported + riscv::CSR_MEDELEG: begin + if (CVA6Cfg.RVS) begin + mask = (1 << riscv::INSTR_ADDR_MISALIGNED) | + (1 << riscv::INSTR_ACCESS_FAULT) | + (1 << riscv::ILLEGAL_INSTR) | + (1 << riscv::BREAKPOINT) | + (1 << riscv::LD_ADDR_MISALIGNED) | + (1 << riscv::LD_ACCESS_FAULT) | + (1 << riscv::ST_ADDR_MISALIGNED) | + (1 << riscv::ST_ACCESS_FAULT) | + (1 << riscv::ENV_CALL_UMODE) | + ((CVA6Cfg.RVH ? 1 : 0) << riscv::ENV_CALL_VSMODE) | + (1 << riscv::INSTR_PAGE_FAULT) | + (1 << riscv::LOAD_PAGE_FAULT) | + (1 << riscv::STORE_PAGE_FAULT) | + ((CVA6Cfg.RVH ? 1 : 0) << riscv::INSTR_GUEST_PAGE_FAULT) | + ((CVA6Cfg.RVH ? 1 : 0) << riscv::LOAD_GUEST_PAGE_FAULT) | + ((CVA6Cfg.RVH ? 1 : 0) << riscv::VIRTUAL_INSTRUCTION) | + ((CVA6Cfg.RVH ? 1 : 0) << riscv::STORE_GUEST_PAGE_FAULT); + medeleg_d = (medeleg_q & ~mask) | (csr_wdata & mask); + end else begin + update_access_exception = 1'b1; + end + end + // machine interrupt delegation register + // we do not support user interrupt delegation + riscv::CSR_MIDELEG: begin + if (CVA6Cfg.RVS) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP) + | CVA6Cfg.XLEN'(riscv::MIP_STIP) + | CVA6Cfg.XLEN'(riscv::MIP_SEIP); + if (CVA6Cfg.RVH) begin + mideleg_d = (mideleg_q & ~mask) | (csr_wdata & mask) | HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]; + end else begin + mideleg_d = (mideleg_q & ~mask) | (csr_wdata & mask); + end + end else begin + update_access_exception = 1'b1; + end + end + // mask the register so that unsupported interrupts can never be set + riscv::CSR_MIE: begin + if (CVA6Cfg.RVH) begin + mask = HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] + | CVA6Cfg.XLEN'(riscv::MIP_SSIP) + | CVA6Cfg.XLEN'(riscv::MIP_STIP) + | CVA6Cfg.XLEN'(riscv::MIP_SEIP) + | CVA6Cfg.XLEN'(riscv::MIP_MSIP) + | CVA6Cfg.XLEN'(riscv::MIP_MTIP) + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); + end else begin + if (CVA6Cfg.RVS) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP) + | CVA6Cfg.XLEN'(riscv::MIP_STIP) + | CVA6Cfg.XLEN'(riscv::MIP_SEIP) + | CVA6Cfg.XLEN'(riscv::MIP_MSIP) + | CVA6Cfg.XLEN'(riscv::MIP_MTIP) + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); + end else begin + if (CVA6Cfg.SoftwareInterruptEn) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_MSIP) // same shift as MSIE + | CVA6Cfg.XLEN'(riscv::MIP_MTIP) // same shift as MTIE + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); // same shift as MEIE + end else begin + mask = CVA6Cfg.XLEN'(riscv::MIP_MTIP) // same shift as MTIE + | CVA6Cfg.XLEN'(riscv::MIP_MEIP); // same shift as MEIE + end + end + end + mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts + end + + riscv::CSR_MTVEC: begin + logic DirVecOnly; + DirVecOnly = CVA6Cfg.DirectVecOnly ? 1'b0 : csr_wdata[0]; + mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, DirVecOnly}; + // we are in vector mode, this implementation requires the additional + // alignment constraint of 64 * 4 bytes + if (DirVecOnly) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, DirVecOnly}; + end + riscv::CSR_MCOUNTEREN: begin + if (CVA6Cfg.RVU) mcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + else update_access_exception = 1'b1; + end + + riscv::CSR_MSCRATCH: mscratch_d = csr_wdata; + riscv::CSR_MEPC: mepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; + riscv::CSR_MCAUSE: mcause_d = csr_wdata; + riscv::CSR_MTVAL: begin + if (CVA6Cfg.TvalEn) mtval_d = csr_wdata; + end + riscv::CSR_MTINST: + if (CVA6Cfg.RVH) mtinst_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + else update_access_exception = 1'b1; + riscv::CSR_MTVAL2: + if (CVA6Cfg.RVH) mtval2_d = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_MIP: begin + if (CVA6Cfg.RVH) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP) + | CVA6Cfg.XLEN'(riscv::MIP_STIP) + | CVA6Cfg.XLEN'(riscv::MIP_SEIP) + | CVA6Cfg.XLEN'(riscv::MIP_VSSIP); + end else if (CVA6Cfg.RVS) begin + mask = CVA6Cfg.XLEN'(riscv::MIP_SSIP) + | CVA6Cfg.XLEN'(riscv::MIP_STIP) + | CVA6Cfg.XLEN'(riscv::MIP_SEIP); + end else begin + mask = '0; + end + mip_d = (mip_q & ~mask) | (csr_wdata & mask); + end + riscv::CSR_MENVCFG: if (CVA6Cfg.RVU) fiom_d = csr_wdata[0]; + riscv::CSR_MENVCFGH: begin + if (!CVA6Cfg.RVU || CVA6Cfg.XLEN != 32) update_access_exception = 1'b1; + end + riscv::CSR_MCOUNTINHIBIT: + if (CVA6Cfg.PerfCounterEn) + mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]}; + else mcountinhibit_d = '0; + // performance counters + riscv::CSR_MCYCLE: cycle_d[CVA6Cfg.XLEN-1:0] = csr_wdata; + riscv::CSR_MCYCLEH: + if (CVA6Cfg.XLEN == 32) cycle_d[63:32] = csr_wdata; + else update_access_exception = 1'b1; + riscv::CSR_MINSTRET: instret_d[CVA6Cfg.XLEN-1:0] = csr_wdata; + riscv::CSR_MINSTRETH: + if (CVA6Cfg.XLEN == 32) instret_d[63:32] = csr_wdata; + else update_access_exception = 1'b1; + //Event Selector + riscv::CSR_MHPM_EVENT_3, + riscv::CSR_MHPM_EVENT_4, + riscv::CSR_MHPM_EVENT_5, + riscv::CSR_MHPM_EVENT_6, + riscv::CSR_MHPM_EVENT_7, + riscv::CSR_MHPM_EVENT_8, + riscv::CSR_MHPM_EVENT_9, + riscv::CSR_MHPM_EVENT_10, + riscv::CSR_MHPM_EVENT_11, + riscv::CSR_MHPM_EVENT_12, + riscv::CSR_MHPM_EVENT_13, + riscv::CSR_MHPM_EVENT_14, + riscv::CSR_MHPM_EVENT_15, + riscv::CSR_MHPM_EVENT_16, + riscv::CSR_MHPM_EVENT_17, + riscv::CSR_MHPM_EVENT_18, + riscv::CSR_MHPM_EVENT_19, + riscv::CSR_MHPM_EVENT_20, + riscv::CSR_MHPM_EVENT_21, + riscv::CSR_MHPM_EVENT_22, + riscv::CSR_MHPM_EVENT_23, + riscv::CSR_MHPM_EVENT_24, + riscv::CSR_MHPM_EVENT_25, + riscv::CSR_MHPM_EVENT_26, + riscv::CSR_MHPM_EVENT_27, + riscv::CSR_MHPM_EVENT_28, + riscv::CSR_MHPM_EVENT_29, + riscv::CSR_MHPM_EVENT_30, + riscv::CSR_MHPM_EVENT_31 : begin + perf_we_o = 1'b1; + perf_data_o = csr_wdata; + end + + riscv::CSR_MHPM_COUNTER_3, + riscv::CSR_MHPM_COUNTER_4, + riscv::CSR_MHPM_COUNTER_5, + riscv::CSR_MHPM_COUNTER_6, + riscv::CSR_MHPM_COUNTER_7, + riscv::CSR_MHPM_COUNTER_8, + riscv::CSR_MHPM_COUNTER_9, + riscv::CSR_MHPM_COUNTER_10, + riscv::CSR_MHPM_COUNTER_11, + riscv::CSR_MHPM_COUNTER_12, + riscv::CSR_MHPM_COUNTER_13, + riscv::CSR_MHPM_COUNTER_14, + riscv::CSR_MHPM_COUNTER_15, + riscv::CSR_MHPM_COUNTER_16, + riscv::CSR_MHPM_COUNTER_17, + riscv::CSR_MHPM_COUNTER_18, + riscv::CSR_MHPM_COUNTER_19, + riscv::CSR_MHPM_COUNTER_20, + riscv::CSR_MHPM_COUNTER_21, + riscv::CSR_MHPM_COUNTER_22, + riscv::CSR_MHPM_COUNTER_23, + riscv::CSR_MHPM_COUNTER_24, + riscv::CSR_MHPM_COUNTER_25, + riscv::CSR_MHPM_COUNTER_26, + riscv::CSR_MHPM_COUNTER_27, + riscv::CSR_MHPM_COUNTER_28, + riscv::CSR_MHPM_COUNTER_29, + riscv::CSR_MHPM_COUNTER_30, + riscv::CSR_MHPM_COUNTER_31 : begin + perf_we_o = 1'b1; + perf_data_o = csr_wdata; + end + + riscv::CSR_MHPM_COUNTER_3H, + riscv::CSR_MHPM_COUNTER_4H, + riscv::CSR_MHPM_COUNTER_5H, + riscv::CSR_MHPM_COUNTER_6H, + riscv::CSR_MHPM_COUNTER_7H, + riscv::CSR_MHPM_COUNTER_8H, + riscv::CSR_MHPM_COUNTER_9H, + riscv::CSR_MHPM_COUNTER_10H, + riscv::CSR_MHPM_COUNTER_11H, + riscv::CSR_MHPM_COUNTER_12H, + riscv::CSR_MHPM_COUNTER_13H, + riscv::CSR_MHPM_COUNTER_14H, + riscv::CSR_MHPM_COUNTER_15H, + riscv::CSR_MHPM_COUNTER_16H, + riscv::CSR_MHPM_COUNTER_17H, + riscv::CSR_MHPM_COUNTER_18H, + riscv::CSR_MHPM_COUNTER_19H, + riscv::CSR_MHPM_COUNTER_20H, + riscv::CSR_MHPM_COUNTER_21H, + riscv::CSR_MHPM_COUNTER_22H, + riscv::CSR_MHPM_COUNTER_23H, + riscv::CSR_MHPM_COUNTER_24H, + riscv::CSR_MHPM_COUNTER_25H, + riscv::CSR_MHPM_COUNTER_26H, + riscv::CSR_MHPM_COUNTER_27H, + riscv::CSR_MHPM_COUNTER_28H, + riscv::CSR_MHPM_COUNTER_29H, + riscv::CSR_MHPM_COUNTER_30H, + riscv::CSR_MHPM_COUNTER_31H : begin + perf_we_o = 1'b1; + if (CVA6Cfg.XLEN == 32) perf_data_o = csr_wdata; + else update_access_exception = 1'b1; + end + + riscv::CSR_DCACHE: dcache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit + riscv::CSR_ICACHE: icache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit + riscv::CSR_ACC_CONS: begin + if (CVA6Cfg.EnableAccelerator) begin + acc_cons_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit + end else begin + update_access_exception = 1'b1; + end + end + // PMP locked logic + // 1. refuse to update any locked entry + // 2. also refuse to update the entry below a locked TOR entry + // Note that writes to pmpcfg below a locked TOR entry are valid + riscv::CSR_PMPCFG0, + riscv::CSR_PMPCFG1, + riscv::CSR_PMPCFG2, + riscv::CSR_PMPCFG3, + riscv::CSR_PMPCFG4, + riscv::CSR_PMPCFG5, + riscv::CSR_PMPCFG6, + riscv::CSR_PMPCFG7, + riscv::CSR_PMPCFG8, + riscv::CSR_PMPCFG9, + riscv::CSR_PMPCFG10, + riscv::CSR_PMPCFG11, + riscv::CSR_PMPCFG12, + riscv::CSR_PMPCFG13, + riscv::CSR_PMPCFG14, + riscv::CSR_PMPCFG15: begin + // index is calculated using PMPCFG0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; + + // if index is not even and XLEN==64, raise exception + if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) update_access_exception = 1'b1; + else begin + for (int i = 0; i < CVA6Cfg.XLEN / 8; i++) begin + if (!pmpcfg_q[index*4+i].locked) pmpcfg_d[index*4+i] = csr_wdata[i*8+:8]; + end + end + end + riscv::CSR_PMPADDR0, + riscv::CSR_PMPADDR1, + riscv::CSR_PMPADDR2, + riscv::CSR_PMPADDR3, + riscv::CSR_PMPADDR4, + riscv::CSR_PMPADDR5, + riscv::CSR_PMPADDR6, + riscv::CSR_PMPADDR7, + riscv::CSR_PMPADDR8, + riscv::CSR_PMPADDR9, + riscv::CSR_PMPADDR10, + riscv::CSR_PMPADDR11, + riscv::CSR_PMPADDR12, + riscv::CSR_PMPADDR13, + riscv::CSR_PMPADDR14, + riscv::CSR_PMPADDR15, + riscv::CSR_PMPADDR16, + riscv::CSR_PMPADDR17, + riscv::CSR_PMPADDR18, + riscv::CSR_PMPADDR19, + riscv::CSR_PMPADDR20, + riscv::CSR_PMPADDR21, + riscv::CSR_PMPADDR22, + riscv::CSR_PMPADDR23, + riscv::CSR_PMPADDR24, + riscv::CSR_PMPADDR25, + riscv::CSR_PMPADDR26, + riscv::CSR_PMPADDR27, + riscv::CSR_PMPADDR28, + riscv::CSR_PMPADDR29, + riscv::CSR_PMPADDR30, + riscv::CSR_PMPADDR31, + riscv::CSR_PMPADDR32, + riscv::CSR_PMPADDR33, + riscv::CSR_PMPADDR34, + riscv::CSR_PMPADDR35, + riscv::CSR_PMPADDR36, + riscv::CSR_PMPADDR37, + riscv::CSR_PMPADDR38, + riscv::CSR_PMPADDR39, + riscv::CSR_PMPADDR40, + riscv::CSR_PMPADDR41, + riscv::CSR_PMPADDR42, + riscv::CSR_PMPADDR43, + riscv::CSR_PMPADDR44, + riscv::CSR_PMPADDR45, + riscv::CSR_PMPADDR46, + riscv::CSR_PMPADDR47, + riscv::CSR_PMPADDR48, + riscv::CSR_PMPADDR49, + riscv::CSR_PMPADDR50, + riscv::CSR_PMPADDR51, + riscv::CSR_PMPADDR52, + riscv::CSR_PMPADDR53, + riscv::CSR_PMPADDR54, + riscv::CSR_PMPADDR55, + riscv::CSR_PMPADDR56, + riscv::CSR_PMPADDR57, + riscv::CSR_PMPADDR58, + riscv::CSR_PMPADDR59, + riscv::CSR_PMPADDR60, + riscv::CSR_PMPADDR61, + riscv::CSR_PMPADDR62, + riscv::CSR_PMPADDR63: begin + // index is calculated using PMPADDR0 as the offset + automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0; + // check if the entry or the entry above is locked + if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin + pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0]; + end + end + default: update_access_exception = 1'b1; + endcase + end + if (CVA6Cfg.IS_XLEN64) begin + mstatus_d.sxl = riscv::XLEN_64; + mstatus_d.uxl = riscv::XLEN_64; + end + if (!CVA6Cfg.RVU) begin + mstatus_d.mpp = riscv::PRIV_LVL_M; + end + + if (CVA6Cfg.RVH) begin + hstatus_d.vsxl = riscv::XLEN_64; + vsstatus_d.uxl = riscv::XLEN_64; + end + // mark the floating point extension register as dirty + if (CVA6Cfg.FpPresent && (dirty_fp_state_csr || dirty_fp_state_i)) begin + mstatus_d.fs = riscv::Dirty; + if (CVA6Cfg.RVH && v_q) begin + vsstatus_d.fs = riscv::Dirty; + end + end + // mark the vector extension register as dirty + if (CVA6Cfg.RVV && dirty_v_state_i) begin + mstatus_d.vs = riscv::Dirty; + end + // hardwired extension registers + if (CVA6Cfg.RVS || CVA6Cfg.RVF) begin + mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty); + end else begin + mstatus_d.sd = riscv::Off; + end + if (CVA6Cfg.RVH) begin + vsstatus_d.sd = (vsstatus_q.xs == riscv::Dirty) | (vsstatus_q.fs == riscv::Dirty); + end + + // reserve PMPCFG bits 5 and 6 (hardwire to 0) + for (int i = 0; i < CVA6Cfg.NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0; + + // write the floating point status register + if (CVA6Cfg.FpPresent && csr_write_fflags_i) begin + fcsr_d.fflags = csr_wdata_i[4:0] | fcsr_q.fflags; + end + + // ---------------------------- + // Accelerator FP imprecise exceptions + // ---------------------------- + + // Update fflags as soon as a FP exception occurs in the accelerator + // The exception is imprecise, and the fcsr.fflags update always happens immediately + if (CVA6Cfg.EnableAccelerator) begin + fcsr_d.fflags |= acc_fflags_ex_valid_i ? acc_fflags_ex_i : 5'b0; + end + + // --------------------- + // External Interrupts + // --------------------- + // Machine Mode External Interrupt Pending + mip_d[riscv::IRQ_M_EXT] = irq_i[0]; + // Machine software interrupt + mip_d[riscv::IRQ_M_SOFT] = CVA6Cfg.SoftwareInterruptEn && ipi_i; + // Timer interrupt pending, coming from platform timer + mip_d[riscv::IRQ_M_TIMER] = time_irq_i; + + // ----------------------- + // Manage Exception Stack + // ----------------------- + // update exception CSRs + // we got an exception update cause, pc and stval register + trap_to_priv_lvl = riscv::PRIV_LVL_M; + trap_to_v = 1'b0; + // Exception is taken and we are not in debug mode + // exceptions in debug mode don't update any fields + if ((CVA6Cfg.DebugEn && !debug_mode_q && ex_i.cause != riscv::DEBUG_REQUEST && ex_i.valid) || (!CVA6Cfg.DebugEn && ex_i.valid)) begin + // do not flush, flush is reserved for CSR writes with side effects + flush_o = 1'b0; + // figure out where to trap to + // a m-mode trap might be delegated if we are taking it in S mode + // first figure out if this was an exception or an interrupt e.g.: look at bit (XLEN-1) + // the cause register can only be $clog2(CVA6Cfg.XLEN) bits long (as we only support XLEN exceptions) + if (CVA6Cfg.RVS) begin + if ((ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]])) begin + // traps never transition from a more-privileged mode to a less privileged mode + // so if we are already in M mode, stay there + trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; + if (CVA6Cfg.RVH) begin + if ((ex_i.cause[CVA6Cfg.XLEN-1] && hideleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && hedeleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]])) begin + // trap to VS only if it is the currently active mode + trap_to_v = v_q; + end + end + end + end + + // trap to supervisor mode + if (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S) begin + if (CVA6Cfg.RVH && trap_to_v) begin + // update sstatus + vsstatus_d.sie = 1'b0; + vsstatus_d.spie = (CVA6Cfg.RVH) ? vsstatus_q.sie : '0; + // this can either be user or supervisor mode + vsstatus_d.spp = priv_lvl_q[0]; + // set cause + vscause_d = ex_i.cause[CVA6Cfg.XLEN-1] ? {ex_i.cause[CVA6Cfg.XLEN-1:2], 2'b01} : ex_i.cause; + // set epc + vsepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + // set vstval + vstval_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE + } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval; + end else begin + // update sstatus + mstatus_d.sie = 1'b0; + mstatus_d.spie = mstatus_q.sie; + // this can either be user or supervisor mode + mstatus_d.spp = priv_lvl_q[0]; + // set cause + scause_d = ex_i.cause; + // set epc + sepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + // set mtval or stval + stval_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE + } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval; + if (CVA6Cfg.RVH) begin + htinst_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::INSTR_ACCESS_FAULT, + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE, + riscv::INSTR_PAGE_FAULT, + riscv::INSTR_GUEST_PAGE_FAULT, + riscv::VIRTUAL_INSTRUCTION + } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : {{CVA6Cfg.XLEN - 32 {1'b0}}, ex_i.tinst}; + hstatus_d.spvp = v_q ? priv_lvl_q[0] : hstatus_d.spvp; + htval_d = {{CVA6Cfg.XLEN - CVA6Cfg.GPLEN + 2{1'b0}}, ex_i.tval2[CVA6Cfg.GPLEN-1:2]}; + hstatus_d.gva = ex_i.gva; + hstatus_d.spv = v_q; + end + end + // trap to machine mode + end else begin + // update mstatus + mstatus_d.mie = 1'b0; + mstatus_d.mpie = mstatus_q.mie; + // save the previous privilege mode + mstatus_d.mpp = priv_lvl_q; + mcause_d = ex_i.cause; + // set epc + mepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + // set mtval or stval + if (CVA6Cfg.TvalEn) begin + mtval_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE + } || ex_i.cause[CVA6Cfg.GPLEN-1])) ? '0 : ex_i.tval; + end else begin + mtval_d = '0; + end + + if (CVA6Cfg.RVH) begin + // save previous virtualization mode + mstatus_d.mpv = v_q; + mtinst_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::INSTR_ADDR_MISALIGNED, + riscv::INSTR_ACCESS_FAULT, + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE, + riscv::INSTR_PAGE_FAULT, + riscv::INSTR_GUEST_PAGE_FAULT, + riscv::VIRTUAL_INSTRUCTION + } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : {{CVA6Cfg.XLEN - 32 {1'b0}}, ex_i.tinst}; + mtval2_d = {{CVA6Cfg.XLEN - CVA6Cfg.GPLEN + 2{1'b0}}, ex_i.tval2[CVA6Cfg.GPLEN-1:2]}; + mstatus_d.gva = ex_i.gva; + end + end + + priv_lvl_d = trap_to_priv_lvl; + if (CVA6Cfg.RVH) begin + v_d = trap_to_v; + end + end + + // ------------------------------ + // Debug + // ------------------------------ + // Explains why Debug Mode was entered. + // When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set cause to the cause with the highest priority. + // 1: An ebreak instruction was executed. (priority 3) + // 2: The Trigger Module caused a breakpoint exception. (priority 4) + // 3: The debugger requested entry to Debug Mode. (priority 2) + // 4: The hart single stepped because step was set. (priority 1) + // we are currently not in debug mode and could potentially enter + if (CVA6Cfg.DebugEn && !debug_mode_q) begin + dcsr_d.prv = priv_lvl_o; + // save virtualization mode bit + dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; + // trigger module fired + + // caused by a breakpoint + if (ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin + dcsr_d.prv = priv_lvl_o; + // save virtualization mode bit + dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; + // check that we actually want to enter debug depending on the privilege level we are currently in + unique case (priv_lvl_o) + riscv::PRIV_LVL_M: begin + debug_mode_d = dcsr_q.ebreakm; + set_debug_pc_o = dcsr_q.ebreakm; + end + riscv::PRIV_LVL_S: begin + if (CVA6Cfg.RVS) begin + debug_mode_d = (CVA6Cfg.RVH && v_q) ? dcsr_q.ebreakvs : dcsr_q.ebreaks; + set_debug_pc_o = (CVA6Cfg.RVH && v_q) ? dcsr_q.ebreakvs : dcsr_q.ebreaks; + end + end + riscv::PRIV_LVL_U: begin + if (CVA6Cfg.RVU) begin + debug_mode_d = (CVA6Cfg.RVH && v_q) ? dcsr_q.ebreakvu : dcsr_q.ebreaku; + set_debug_pc_o = (CVA6Cfg.RVH && v_q) ? dcsr_q.ebreakvu : dcsr_q.ebreaku; + end + end + default: ; + endcase + // save PC of next this instruction e.g.: the next one to be executed + dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + dcsr_d.cause = ariane_pkg::CauseBreakpoint; + end + + // we've got a debug request + if (ex_i.valid && ex_i.cause == riscv::DEBUG_REQUEST) begin + dcsr_d.prv = priv_lvl_o; + dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; + // save the PC + dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + // enter debug mode + debug_mode_d = 1'b1; + // jump to the base address + set_debug_pc_o = 1'b1; + // save the cause as external debug request + dcsr_d.cause = ariane_pkg::CauseRequest; + end + + // single step enable and we just retired an instruction + if (dcsr_q.step && commit_ack_i[0]) begin + dcsr_d.prv = priv_lvl_o; + dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; + // valid CTRL flow change + if (commit_instr_i.fu == CTRL_FLOW) begin + // we saved the correct target address during execute + dpc_d = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.bp.predict_address[CVA6Cfg.VLEN-1]}}, + commit_instr_i.bp.predict_address + }; + // exception valid + end else if (ex_i.valid) begin + dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, trap_vector_base_o}; + // return from environment + end else if (eret_o) begin + dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, epc_o}; + // consecutive PC + end else begin + dpc_d = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.pc[CVA6Cfg.VLEN-1]}}, + commit_instr_i.pc + (commit_instr_i.is_compressed ? 'h2 : 'h4) + }; + end + debug_mode_d = 1'b1; + set_debug_pc_o = 1'b1; + dcsr_d.cause = ariane_pkg::CauseSingleStep; + end + end + // go in halt-state again when we encounter an exception + if (CVA6Cfg.DebugEn && debug_mode_q && ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin + set_debug_pc_o = 1'b1; + end + + // ------------------------------ + // MPRV - Modify Privilege Level + // ------------------------------ + // Set the address translation at which the load and stores should occur + // we can use the previous values since changing the address translation will always involve a pipeline flush + if (CVA6Cfg.RVH) begin + if (mprv && (mstatus_q.mpv == 1'b0) && (config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV) && (mstatus_q.mpp != riscv::PRIV_LVL_M)) begin + en_ld_st_translation_d = 1'b1; + end else if (mprv && (mstatus_q.mpv == 1'b1)) begin + if (config_pkg::vm_mode_t'(vsatp_q.mode) == CVA6Cfg.MODE_SV) begin + en_ld_st_translation_d = 1'b1; + end else begin + en_ld_st_translation_d = 1'b0; + end + end else begin // otherwise we go with the regular settings + en_ld_st_translation_d = en_translation_o; + end + + if (mprv && (mstatus_q.mpv == 1'b1)) begin + if (config_pkg::vm_mode_t'(hgatp_q.mode) == CVA6Cfg.MODE_SV) begin + en_ld_st_g_translation_d = 1'b1; + end else begin + en_ld_st_g_translation_d = 1'b0; + end + end else begin + en_ld_st_g_translation_d = en_g_translation_o; + end + + if (csr_hs_ld_st_inst_i) ld_st_priv_lvl_o = riscv::priv_lvl_t'(hstatus_q.spvp); + else ld_st_priv_lvl_o = (mprv) ? mstatus_q.mpp : priv_lvl_o; + + ld_st_v_o = ((mprv ? mstatus_q.mpv : v_q) || (csr_hs_ld_st_inst_i)); + + en_ld_st_translation_o = (en_ld_st_translation_q && !csr_hs_ld_st_inst_i) || (config_pkg::vm_mode_t'(vsatp_q.mode) == CVA6Cfg.MODE_SV && csr_hs_ld_st_inst_i); + + en_ld_st_g_translation_o = (en_ld_st_g_translation_q && !csr_hs_ld_st_inst_i) || (csr_hs_ld_st_inst_i && config_pkg::vm_mode_t'(hgatp_q.mode) == CVA6Cfg.MODE_SV && csr_hs_ld_st_inst_i); + end else begin + if (CVA6Cfg.MmuPresent && mprv && CVA6Cfg.RVS && config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && (mstatus_q.mpp != riscv::PRIV_LVL_M)) + en_ld_st_translation_d = 1'b1; + else // otherwise we go with the regular settings + en_ld_st_translation_d = en_translation_o; + + if (CVA6Cfg.RVU) begin + ld_st_priv_lvl_o = (mprv) ? mstatus_q.mpp : priv_lvl_o; + end else begin + ld_st_priv_lvl_o = priv_lvl_o; + end + en_ld_st_translation_o = en_ld_st_translation_q; + ld_st_v_o = 1'b0; + en_ld_st_g_translation_o = 1'b0; + end + // ------------------------------ + // Return from Environment + // ------------------------------ + // When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege + // mode is changed to y; xPIE is set to 1; and xPP is set to U + if (mret) begin + // return from exception, IF doesn't care from where we are returning + eret_o = 1'b1; + // return to the previous privilege level and restore all enable flags + // get the previous machine interrupt enable flag + mstatus_d.mie = mstatus_q.mpie; + // restore the previous privilege level + priv_lvl_d = mstatus_q.mpp; + mstatus_d.mpp = riscv::PRIV_LVL_M; + if (CVA6Cfg.RVU) begin + // set mpp to user mode + mstatus_d.mpp = riscv::PRIV_LVL_U; + end + // set mpie to 1 + mstatus_d.mpie = 1'b1; + if (CVA6Cfg.RVH) begin + // set virtualization mode + v_d = mstatus_q.mpv; + //set mstatus mpv to false + mstatus_d.mpv = 1'b0; + if (mstatus_q.mpp != riscv::PRIV_LVL_M) mstatus_d.mprv = 1'b0; + end + end + + if (CVA6Cfg.RVS && sret && ((CVA6Cfg.RVH && !v_q) || !CVA6Cfg.RVH)) begin + // return from exception, IF doesn't care from where we are returning + eret_o = 1'b1; + // return the previous supervisor interrupt enable flag + mstatus_d.sie = mstatus_q.spie; + // restore the previous privilege level + priv_lvl_d = riscv::priv_lvl_t'({1'b0, mstatus_q.spp}); + // set spp to user mode + mstatus_d.spp = 1'b0; + // set spie to 1 + mstatus_d.spie = 1'b1; + if (CVA6Cfg.RVH) begin + // set virtualization mode + v_d = hstatus_q.spv; + //set hstatus spv to false + hstatus_d.spv = 1'b0; + mstatus_d.mprv = 1'b0; + end + end + + if (CVA6Cfg.RVH) begin + if (sret && v_q) begin + // return from exception, IF doesn't care from where we are returning + eret_o = 1'b1; + // return the previous supervisor interrupt enable flag + vsstatus_d.sie = vsstatus_q.spie; + // restore the previous privilege level + priv_lvl_d = riscv::priv_lvl_t'({1'b0, vsstatus_q.spp}); + // set spp to user mode + vsstatus_d.spp = 1'b0; + // set spie to 1 + vsstatus_d.spie = 1'b1; + end + end + + // return from debug mode + if (CVA6Cfg.DebugEn) begin + if (dret) begin + // return from exception, IF doesn't care from where we are returning + eret_o = 1'b1; + // restore the previous privilege level + priv_lvl_d = riscv::priv_lvl_t'(dcsr_q.prv); + if (CVA6Cfg.RVH) begin + // restore the previous virtualization mode + v_d = dcsr_q.v; + end + // actually return from debug mode + debug_mode_d = 1'b0; + end + end + end + + // --------------------------- + // CSR OP Select Logic + // --------------------------- + always_comb begin : csr_op_logic + csr_wdata = csr_wdata_i; + csr_we = 1'b1; + csr_read = 1'b1; + mret = 1'b0; + sret = 1'b0; + dret = 1'b0; + + unique case (csr_op_i) + CSR_WRITE: csr_wdata = csr_wdata_i; + CSR_SET: csr_wdata = csr_wdata_i | csr_rdata; + CSR_CLEAR: csr_wdata = (~csr_wdata_i) & csr_rdata; + CSR_READ: csr_we = 1'b0; + MRET: begin + // the return should not have any write or read side-effects + csr_we = 1'b0; + csr_read = 1'b0; + mret = 1'b1; // signal a return from machine mode + end + default: begin + if (CVA6Cfg.RVS && csr_op_i == SRET) begin + // the return should not have any write or read side-effects + csr_we = 1'b0; + csr_read = 1'b0; + sret = 1'b1; // signal a return from supervisor mode + end else if (CVA6Cfg.DebugEn && csr_op_i == DRET) begin + // the return should not have any write or read side-effects + csr_we = 1'b0; + csr_read = 1'b0; + dret = 1'b1; // signal a return from debug mode + end else begin + csr_we = 1'b0; + csr_read = 1'b0; + end + end + endcase + // if we are violating our privilges do not update the architectural state + if (privilege_violation) begin + csr_we = 1'b0; + csr_read = 1'b0; + end + end + + assign irq_ctrl_o.mie = mie_q; + assign irq_ctrl_o.mip = mip_q; + if (CVA6Cfg.RVH) begin + assign irq_ctrl_o.sie = (v_q) ? vsstatus_q.sie : mstatus_q.sie; + end else begin + assign irq_ctrl_o.sie = mstatus_q.sie; + end + assign irq_ctrl_o.mideleg = (CVA6Cfg.RVS) ? mideleg_q : '0; + assign irq_ctrl_o.hideleg = (CVA6Cfg.RVH) ? hideleg_q : '0; + assign irq_ctrl_o.global_enable = ~(CVA6Cfg.DebugEn & debug_mode_q) + // interrupts are enabled during single step or we are not stepping + // No need to check interrupts during single step if we don't support DEBUG mode + & (~CVA6Cfg.DebugEn | (~dcsr_q.step | dcsr_q.stepie)) + & ((mstatus_q.mie & (priv_lvl_o == riscv::PRIV_LVL_M)) + | (CVA6Cfg.RVU & priv_lvl_o != riscv::PRIV_LVL_M)); + + always_comb begin : privilege_check + if (CVA6Cfg.RVH) begin + automatic riscv::priv_lvl_t access_priv; + automatic riscv::priv_lvl_t curr_priv; + automatic logic [SELECT_COUNTER_WIDTH-1:0] sel_cnt_en; + // transforms S mode accesses into HS mode + access_priv = (priv_lvl_o == riscv::PRIV_LVL_S && !v_q) ? riscv::PRIV_LVL_HS : priv_lvl_o; + curr_priv = priv_lvl_o; + sel_cnt_en = {{SELECT_COUNTER_WIDTH - 5{1'b0}}, csr_addr_i[4:0]}; + // ----------------- + // Privilege Check + // ----------------- + privilege_violation = 1'b0; + virtual_privilege_violation = 1'b0; + // if we are reading or writing, check for the correct privilege level this has + // precedence over interrupts + if (csr_op_i inside {CSR_WRITE, CSR_SET, CSR_CLEAR, CSR_READ}) begin + if (access_priv < csr_addr.csr_decode.priv_lvl) begin + if (v_q && csr_addr.csr_decode.priv_lvl <= riscv::PRIV_LVL_HS) + virtual_privilege_violation = 1'b1; + else privilege_violation = 1'b1; + end + // check access to debug mode only CSRs + if ((!CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b) || (CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b && !debug_mode_q)) begin + privilege_violation = 1'b1; + end + // check counter-enabled counter CSR accesses + // counter address range is C00 to C1F + if (CVA6Cfg.RVZihpm) begin + if (csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3 : riscv::CSR_HPM_COUNTER_31]} | + csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]}) begin + if (curr_priv == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; + privilege_violation = ~mcounteren_q[sel_cnt_en]; + end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin + virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; + if (v_q) begin + privilege_violation = ~mcounteren_q[sel_cnt_en] & ~scounteren_q[sel_cnt_en] & hcounteren_q[sel_cnt_en]; + end else begin + privilege_violation = ~mcounteren_q[sel_cnt_en] & ~scounteren_q[sel_cnt_en]; + end + end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin + privilege_violation = 1'b0; + end + end + end + if (CVA6Cfg.RVZicntr) begin + if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_INSTRET]} | + csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]}) begin + if (curr_priv == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; + privilege_violation = ~mcounteren_q[sel_cnt_en]; + end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin + virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; + if (v_q) begin + privilege_violation = ~mcounteren_q[sel_cnt_en] & ~scounteren_q[sel_cnt_en] & hcounteren_q[sel_cnt_en]; + end else begin + privilege_violation = ~mcounteren_q[sel_cnt_en] & ~scounteren_q[sel_cnt_en]; + end + end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin + privilege_violation = 1'b0; + end + end + end + end + end else begin + // ----------------- + // Privilege Check + // ----------------- + privilege_violation = 1'b0; + // if we are reading or writing, check for the correct privilege level this has + // precedence over interrupts + if (csr_op_i inside {CSR_WRITE, CSR_SET, CSR_CLEAR, CSR_READ}) begin + if (CVA6Cfg.RVU && (riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl)) begin + privilege_violation = 1'b1; + end + // check access to debug mode only CSRs + if ((!CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b) || (CVA6Cfg.DebugEn && csr_addr_i[11:4] == 8'h7b && !debug_mode_q)) begin + privilege_violation = 1'b1; + end + // check counter-enabled counter CSR accesses + // counter address range is C00 to C1F + if (CVA6Cfg.RVZihpm) begin + if (csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3 : riscv::CSR_HPM_COUNTER_31]} | + csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]}) begin + if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + privilege_violation = ~mcounteren_q[csr_addr_i[4:0]]; + end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin + privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]]; + end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin + privilege_violation = 1'b0; + end + end + end + if (CVA6Cfg.RVZicntr) begin + if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_INSTRET]} | + csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]}) begin + if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + privilege_violation = ~mcounteren_q[csr_addr_i[4:0]]; + end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin + privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]]; + end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin + privilege_violation = 1'b0; + end + end + end + end + end + end + // ---------------------- + // CSR Exception Control + // ---------------------- + always_comb begin : exception_ctrl + csr_exception_o = { + {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.GPLEN{1'b0}}, {32{1'b0}}, 1'b0, 1'b0 + }; + // ---------------------------------- + // Illegal Access (decode exception) + // ---------------------------------- + // we got an exception in one of the processes above + // throw an illegal instruction exception + if (update_access_exception || read_access_exception) begin + csr_exception_o.cause = riscv::ILLEGAL_INSTR; + // we don't set the tval field as this will be set by the commit stage + // this spares the extra wiring from commit to CSR and back to commit + csr_exception_o.valid = 1'b1; + end + + if (privilege_violation) begin + csr_exception_o.cause = riscv::ILLEGAL_INSTR; + csr_exception_o.valid = 1'b1; + end + + if (CVA6Cfg.RVH && (virtual_update_access_exception || virtual_read_access_exception || virtual_privilege_violation)) begin + csr_exception_o.cause = riscv::VIRTUAL_INSTRUCTION; + csr_exception_o.valid = 1'b1; + end + end + + // ------------------- + // Wait for Interrupt + // ------------------- + always_comb begin : wfi_ctrl + // wait for interrupt register + wfi_d = wfi_q; + // if there is any (enabled) interrupt pending un-stall the core + // also un-stall if we want to enter debug mode + if (|(mip_q & mie_q) || (CVA6Cfg.DebugEn && debug_req_i) || irq_i[1]) begin + wfi_d = 1'b0; + // or alternatively if there is no exception pending and we are not in debug mode wait here + // for the interrupt + end else if (((CVA6Cfg.DebugEn && !debug_mode_q) && csr_op_i == WFI && !ex_i.valid) || (!CVA6Cfg.DebugEn && csr_op_i == WFI && !ex_i.valid)) begin + wfi_d = 1'b1; + end + end + + // output assignments dependent on privilege mode + always_comb begin : priv_output + trap_vector_base_o = {mtvec_q[CVA6Cfg.VLEN-1:2], 2'b0}; + // output user mode stvec + if (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S) begin + trap_vector_base_o = (CVA6Cfg.RVH && trap_to_v) ? {vstvec_q[CVA6Cfg.VLEN-1:2], 2'b0} : {stvec_q[CVA6Cfg.VLEN-1:2], 2'b0}; + end + + // if we are in debug mode jump to a specific address + if (CVA6Cfg.DebugEn && debug_mode_q) begin + trap_vector_base_o = CVA6Cfg.DmBaseAddress[CVA6Cfg.VLEN-1:0] + CVA6Cfg.ExceptionAddress[CVA6Cfg.VLEN-1:0]; + end + + // check if we are in vectored mode, if yes then do BASE + 4 * cause we + // are imposing an additional alignment-constraint of 64 * 4 bytes since + // we want to spare the costly addition. Furthermore check to which + // privilege level we are jumping and whether the vectored mode is + // activated for _that_ privilege level. + if (ex_i.cause[CVA6Cfg.XLEN-1] && + ((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && (!CVA6Cfg.DirectVecOnly && mtvec_q[0])) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && (!CVA6Cfg.DirectVecOnly && mtvec_q[0]))) + || (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && !trap_to_v && stvec_q[0]))) begin + trap_vector_base_o[7:2] = ex_i.cause[5:0]; + end + if (ex_i.cause[CVA6Cfg.XLEN-1] && + (CVA6Cfg.RVH && trap_to_priv_lvl == riscv::PRIV_LVL_S && trap_to_v && vstvec_q[0])) begin + trap_vector_base_o[7:2] = {ex_i.cause[5:2], 2'b01}; + end + + epc_o = mepc_q[CVA6Cfg.VLEN-1:0]; + // we are returning from supervisor or virtual supervisor mode, so take the sepc register + if (CVA6Cfg.RVS) begin + if (sret) begin + epc_o = (CVA6Cfg.RVH && v_q) ? vsepc_q[CVA6Cfg.VLEN-1:0] : sepc_q[CVA6Cfg.VLEN-1:0]; + end + end + // we are returning from debug mode, to take the dpc register + if (CVA6Cfg.DebugEn) begin + if (dret) begin + epc_o = dpc_q[CVA6Cfg.VLEN-1:0]; + end + end + end + + // ------------------- + // Output Assignments + // ------------------- + always_comb begin + // When the SEIP bit is read with a CSRRW, CSRRS, or CSRRC instruction, the value + // returned in the rd destination register contains the logical-OR of the software-writable + // bit and the interrupt signal from the interrupt controller. + csr_rdata_o = csr_rdata; + + unique case (conv_csr_addr.address) + riscv::CSR_MIP: + csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); + // in supervisor mode we also need to check whether we delegated this bit + riscv::CSR_SIP: begin + if (CVA6Cfg.RVS) begin + csr_rdata_o = csr_rdata + | ({{CVA6Cfg.XLEN-1{1'b0}}, (irq_i[1] & mideleg_q[riscv::IRQ_S_EXT])} << riscv::IRQ_S_EXT); + end + end + default: ; + endcase + end + + // in debug mode we execute with privilege level M + assign priv_lvl_o = (CVA6Cfg.DebugEn && debug_mode_q) ? riscv::PRIV_LVL_M : priv_lvl_q; + assign v_o = CVA6Cfg.RVH ? v_q : 1'b0; + // FPU outputs + assign fflags_o = fcsr_q.fflags; + assign frm_o = fcsr_q.frm; + assign fprec_o = fcsr_q.fprec; + //JVT outputs + if (CVA6Cfg.RVZCMT) begin + assign jvt_o.base = jvt_q.base; + assign jvt_o.mode = jvt_q.mode; + end else begin + assign jvt_o.base = '0; + assign jvt_o.mode = '0; + end + // MMU outputs + assign satp_ppn_o = CVA6Cfg.RVS ? satp_q.ppn : '0; + assign vsatp_ppn_o = CVA6Cfg.RVH ? vsatp_q.ppn : '0; + assign hgatp_ppn_o = CVA6Cfg.RVH ? hgatp_q.ppn : '0; + if (CVA6Cfg.RVS) begin + assign asid_o = satp_q.asid[CVA6Cfg.ASID_WIDTH-1:0]; + end else begin + assign asid_o = '0; + end + assign vs_asid_o = CVA6Cfg.RVH ? vsatp_q.asid[CVA6Cfg.ASID_WIDTH-1:0] : '0; + assign vmid_o = CVA6Cfg.RVH ? hgatp_q.vmid[CVA6Cfg.VMID_WIDTH-1:0] : '0; + assign sum_o = mstatus_q.sum; + assign vs_sum_o = CVA6Cfg.RVH ? vsstatus_q.sum : '0; + assign hu_o = CVA6Cfg.RVH ? hstatus_q.hu : '0; + // we support bare memory addressing and SV39 + if (CVA6Cfg.RVH) begin + assign en_translation_o = (((config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && !v_q) || (config_pkg::vm_mode_t'(vsatp_q.mode) == CVA6Cfg.MODE_SV && v_q)) && + priv_lvl_o != riscv::PRIV_LVL_M) + ? 1'b1 + : 1'b0; + assign en_g_translation_o = (config_pkg::vm_mode_t'(hgatp_q.mode) == CVA6Cfg.MODE_SV && + priv_lvl_o != riscv::PRIV_LVL_M && v_q) + ? 1'b1 + : 1'b0; + end else begin + assign en_translation_o = (CVA6Cfg.RVS && config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && + priv_lvl_o != riscv::PRIV_LVL_M) + ? 1'b1 + : 1'b0; + assign en_g_translation_o = 1'b0; + end + assign mxr_o = mstatus_q.mxr; + assign vmxr_o = CVA6Cfg.RVH ? vsstatus_q.mxr : '0; + if (CVA6Cfg.RVH) begin + assign tvm_o = (v_q) ? hstatus_q.vtvm : mstatus_q.tvm; + end else begin + assign tvm_o = mstatus_q.tvm; + end + assign tw_o = mstatus_q.tw; + assign vtw_o = CVA6Cfg.RVH ? hstatus_q.vtw : '0; + if (CVA6Cfg.RVH) begin + assign tsr_o = (v_q) ? hstatus_q.vtsr : mstatus_q.tsr; + end else begin + assign tsr_o = mstatus_q.tsr; + end + assign halt_csr_o = wfi_q; +`ifdef PITON_ARIANE + assign icache_en_o = icache_q[0]; +`else + assign icache_en_o = icache_q[0] & ~(CVA6Cfg.DebugEn && debug_mode_q); +`endif + assign dcache_en_o = dcache_q[0]; + assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0; + + // determine if mprv needs to be considered if in debug mode + assign mprv = (CVA6Cfg.DebugEn && debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv; + assign debug_mode_o = debug_mode_q; + assign single_step_o = CVA6Cfg.DebugEn ? dcsr_q.step : 1'b0; + assign mcountinhibit_o = {{29 - MHPMCounterNum{1'b0}}, mcountinhibit_q}; + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + priv_lvl_q <= riscv::PRIV_LVL_M; + // floating-point registers + fcsr_q <= '0; + if (CVA6Cfg.RVZCMT) begin + jvt_q <= '0; + end + // debug signals + if (CVA6Cfg.DebugEn) begin + debug_mode_q <= 1'b0; + dcsr_q <= '{xdebugver: 4'h4, prv: riscv::PRIV_LVL_M, default: '0}; + dpc_q <= '0; + dscratch0_q <= {CVA6Cfg.XLEN{1'b0}}; + dscratch1_q <= {CVA6Cfg.XLEN{1'b0}}; + end + // machine mode registers + mstatus_q <= 64'b0; + // set to boot address + direct mode + 4 byte offset which is the initial trap + mtvec_rst_load_q <= 1'b1; + mtvec_q <= '0; + mip_q <= {CVA6Cfg.XLEN{1'b0}}; + mie_q <= {CVA6Cfg.XLEN{1'b0}}; + mepc_q <= {CVA6Cfg.XLEN{1'b0}}; + mcause_q <= {CVA6Cfg.XLEN{1'b0}}; + mcounteren_q <= {CVA6Cfg.XLEN{1'b0}}; + mscratch_q <= {CVA6Cfg.XLEN{1'b0}}; + if (CVA6Cfg.TvalEn) mtval_q <= {CVA6Cfg.XLEN{1'b0}}; + fiom_q <= '0; + dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + mcountinhibit_q <= '0; + acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; + // supervisor mode registers + if (CVA6Cfg.RVS) begin + medeleg_q <= {CVA6Cfg.XLEN{1'b0}}; + mideleg_q <= {CVA6Cfg.XLEN{1'b0}}; + sepc_q <= {CVA6Cfg.XLEN{1'b0}}; + scause_q <= {CVA6Cfg.XLEN{1'b0}}; + stvec_q <= {CVA6Cfg.XLEN{1'b0}}; + scounteren_q <= {CVA6Cfg.XLEN{1'b0}}; + sscratch_q <= {CVA6Cfg.XLEN{1'b0}}; + stval_q <= {CVA6Cfg.XLEN{1'b0}}; + satp_q <= {CVA6Cfg.XLEN{1'b0}}; + end + + if (CVA6Cfg.RVH) begin + v_q <= '0; + mtval2_q <= {CVA6Cfg.XLEN{1'b0}}; + mtinst_q <= {CVA6Cfg.XLEN{1'b0}}; + hstatus_q <= 64'b0; + hedeleg_q <= {CVA6Cfg.XLEN{1'b0}}; + hideleg_q <= {CVA6Cfg.XLEN{1'b0}}; + hgeie_q <= {CVA6Cfg.XLEN{1'b0}}; + hgatp_q <= {CVA6Cfg.XLEN{1'b0}}; + hcounteren_q <= {CVA6Cfg.XLEN{1'b0}}; + htval_q <= {CVA6Cfg.XLEN{1'b0}}; + htinst_q <= {CVA6Cfg.XLEN{1'b0}}; + // virtual supervisor mode registers + vsstatus_q <= 64'b0; + vsepc_q <= {CVA6Cfg.XLEN{1'b0}}; + vscause_q <= {CVA6Cfg.XLEN{1'b0}}; + vstvec_q <= {CVA6Cfg.XLEN{1'b0}}; + vsscratch_q <= {CVA6Cfg.XLEN{1'b0}}; + vstval_q <= {CVA6Cfg.XLEN{1'b0}}; + vsatp_q <= {CVA6Cfg.XLEN{1'b0}}; + en_ld_st_g_translation_q <= 1'b0; + end + // timer and counters + cycle_q <= 64'b0; + instret_q <= 64'b0; + // aux registers + en_ld_st_translation_q <= 1'b0; + // wait for interrupt + wfi_q <= 1'b0; + // pmp + for (int i = 0; i < 64; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + pmpcfg_q[i] <= riscv::pmpcfg_t'(CVA6Cfg.PMPCfgRstVal[i]); + pmpaddr_q[i] <= CVA6Cfg.PMPAddrRstVal[i][CVA6Cfg.PLEN-3:0]; + end else begin + pmpcfg_q[i] <= '0; + pmpaddr_q[i] <= '0; + end + end + end else begin + priv_lvl_q <= priv_lvl_d; + // floating-point registers + fcsr_q <= fcsr_d; + if (CVA6Cfg.RVZCMT) begin + jvt_q <= jvt_d; + end + // debug signals + if (CVA6Cfg.DebugEn) begin + debug_mode_q <= debug_mode_d; + dcsr_q <= dcsr_d; + dpc_q <= dpc_d; + dscratch0_q <= dscratch0_d; + dscratch1_q <= dscratch1_d; + end + // machine mode registers + mstatus_q <= mstatus_d; + mtvec_rst_load_q <= 1'b0; + mtvec_q <= mtvec_d; + mip_q <= mip_d; + mie_q <= mie_d; + mepc_q <= mepc_d; + mcause_q <= mcause_d; + mcounteren_q <= mcounteren_d; + mscratch_q <= mscratch_d; + if (CVA6Cfg.TvalEn) mtval_q <= mtval_d; + fiom_q <= fiom_d; + dcache_q <= dcache_d; + icache_q <= icache_d; + mcountinhibit_q <= mcountinhibit_d; + acc_cons_q <= acc_cons_d; + // supervisor mode registers + if (CVA6Cfg.RVS) begin + medeleg_q <= medeleg_d; + mideleg_q <= mideleg_d; + sepc_q <= sepc_d; + scause_q <= scause_d; + stvec_q <= stvec_d; + scounteren_q <= scounteren_d; + sscratch_q <= sscratch_d; + if (CVA6Cfg.TvalEn) stval_q <= stval_d; + satp_q <= satp_d; + end + if (CVA6Cfg.RVH) begin + v_q <= v_d; + mtval2_q <= mtval2_d; + mtinst_q <= mtinst_d; + // hypervisor mode registers + hstatus_q <= hstatus_d; + hedeleg_q <= hedeleg_d; + hideleg_q <= hideleg_d; + hgeie_q <= hgeie_d; + hgatp_q <= hgatp_d; + hcounteren_q <= hcounteren_d; + htval_q <= htval_d; + htinst_q <= htinst_d; + // virtual supervisor mode registers + vsstatus_q <= vsstatus_d; + vsepc_q <= vsepc_d; + vscause_q <= vscause_d; + vstvec_q <= vstvec_d; + vsscratch_q <= vsscratch_d; + vstval_q <= vstval_d; + vsatp_q <= vsatp_d; + en_ld_st_g_translation_q <= en_ld_st_g_translation_d; + end + // timer and counters + cycle_q <= cycle_d; + instret_q <= instret_d; + // aux registers + en_ld_st_translation_q <= en_ld_st_translation_d; + // wait for interrupt + wfi_q <= wfi_d; + // pmp + pmpcfg_q <= pmpcfg_next; + pmpaddr_q <= pmpaddr_next; + end + end + + // write logic pmp + always_comb begin : write + for (int i = 0; i < 64; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + // PMP locked logic is handled in the CSR write process above + pmpcfg_next[i] = pmpcfg_d[i]; + // We only support >=8-byte granularity, NA4 is not supported + if ((!CVA6Cfg.PMPNapotEn && pmpcfg_d[i].addr_mode == riscv::NAPOT) ||pmpcfg_d[i].addr_mode == riscv::NA4) begin + pmpcfg_next[i].addr_mode = pmpcfg_q[i].addr_mode; + end + // Follow collective WARL spec for RWX fields + if (pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1) begin + pmpcfg_next[i].access_type = pmpcfg_q[i].access_type; + end + end else begin + pmpcfg_next[i] = pmpcfg_q[i]; + end + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + pmpaddr_next[i] = pmpaddr_d[i]; + end else begin + pmpaddr_next[i] = pmpaddr_q[i]; + end + end else begin + pmpcfg_next[i] = '0; + pmpaddr_next[i] = '0; + end + end + end + + //------------- + // Assertions + //------------- + //pragma translate_off + // check that eret and ex are never valid together + assert property (@(posedge clk_i) disable iff (!rst_ni !== '0) !(eret_o && ex_i.valid)) + else begin + $error("eret and exception should never be valid at the same time"); + $stop(); + end + //pragma translate_on + + + //RVFI CSR + + //------------- + // RVFI + //------------- + assign rvfi_csr_o.fcsr_q = CVA6Cfg.FpPresent ? fcsr_q : '0; + assign rvfi_csr_o.jvt_q = CVA6Cfg.RVZCMT ? jvt_q : '0; + assign rvfi_csr_o.dcsr_q = CVA6Cfg.DebugEn ? dcsr_q : '0; + assign rvfi_csr_o.dpc_q = CVA6Cfg.DebugEn ? dpc_q : '0; + assign rvfi_csr_o.dscratch0_q = CVA6Cfg.DebugEn ? dscratch0_q : '0; + assign rvfi_csr_o.dscratch1_q = CVA6Cfg.DebugEn ? dscratch1_q : '0; + assign rvfi_csr_o.mie_q = mie_q; + assign rvfi_csr_o.mip_q = mip_q; + assign rvfi_csr_o.stvec_q = CVA6Cfg.RVS ? stvec_q : '0; + assign rvfi_csr_o.scounteren_q = CVA6Cfg.RVS ? scounteren_q : '0; + assign rvfi_csr_o.sscratch_q = CVA6Cfg.RVS ? sscratch_q : '0; + assign rvfi_csr_o.sepc_q = CVA6Cfg.RVS ? sepc_q : '0; + assign rvfi_csr_o.scause_q = CVA6Cfg.RVS ? scause_q : '0; + assign rvfi_csr_o.stval_q = CVA6Cfg.RVS ? stval_q : '0; + assign rvfi_csr_o.satp_q = CVA6Cfg.RVS ? satp_q : '0; + assign rvfi_csr_o.mstatus_extended = mstatus_extended; + assign rvfi_csr_o.medeleg_q = CVA6Cfg.RVS ? medeleg_q : '0; + assign rvfi_csr_o.mideleg_q = CVA6Cfg.RVS ? mideleg_q : '0; + assign rvfi_csr_o.mtvec_q = mtvec_q; + assign rvfi_csr_o.mcounteren_q = mcounteren_q; + assign rvfi_csr_o.mscratch_q = mscratch_q; + assign rvfi_csr_o.mepc_q = mepc_q; + assign rvfi_csr_o.mcause_q = mcause_q; + assign rvfi_csr_o.mtval_q = CVA6Cfg.TvalEn ? mtval_q : '0; + assign rvfi_csr_o.fiom_q = fiom_q; + assign rvfi_csr_o.mcountinhibit_q = mcountinhibit_q; + assign rvfi_csr_o.cycle_q = cycle_q; + assign rvfi_csr_o.instret_q = instret_q; + assign rvfi_csr_o.dcache_q = dcache_q; + assign rvfi_csr_o.icache_q = icache_q; + assign rvfi_csr_o.acc_cons_q = CVA6Cfg.EnableAccelerator ? acc_cons_q : '0; + assign rvfi_csr_o.pmpcfg_q = pmpcfg_q; + assign rvfi_csr_o.pmpaddr_q = pmpaddr_q; + + +endmodule diff --git a/flow/designs/src/cva6/core/cva6.sv b/flow/designs/src/cva6/core/cva6.sv new file mode 100644 index 0000000000..6c341da5bc --- /dev/null +++ b/flow/designs/src/cva6/core/cva6.sv @@ -0,0 +1,1817 @@ +// Copyright 2017-2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 19.03.2017 +// Description: CVA6 Top-level module + +`include "rvfi_types.svh" +`include "cvxif_types.svh" + +module cva6 + import ariane_pkg::*; +#( + // CVA6 config + parameter config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config( + cva6_config_pkg::cva6_cfg + ), + + // RVFI PROBES + parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg), + parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg), + parameter type rvfi_probes_t = struct packed { + rvfi_probes_csr_t csr; + rvfi_probes_instr_t instr; + }, + + // branchpredict scoreboard entry + // this is the struct which we will inject into the pipeline to guide the various + // units towards the correct branch decision and resolve + localparam type branchpredict_sbe_t = struct packed { + cf_t cf; // type of control flow prediction + logic [CVA6Cfg.VLEN-1:0] predict_address; // target address at which to jump, or not + }, + + parameter type exception_t = struct packed { + logic [CVA6Cfg.XLEN-1:0] cause; // cause of exception + logic [CVA6Cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it), + // address of LD/ST fault + logic [CVA6Cfg.GPLEN-1:0] tval2; // additional information when the causing exception in a guest exception + logic [31:0] tinst; // transformed instruction information + logic gva; // signals when a guest virtual address is written to tval + logic valid; + }, + + // cache request ports + // I$ address translation requests + localparam type icache_areq_t = struct packed { + logic fetch_valid; // address translation valid + logic [CVA6Cfg.PLEN-1:0] fetch_paddr; // physical address in + exception_t fetch_exception; // exception occurred during fetch + }, + localparam type icache_arsp_t = struct packed { + logic fetch_req; // address translation request + logic [CVA6Cfg.VLEN-1:0] fetch_vaddr; // virtual address out + }, + + // I$ data requests + localparam type icache_dreq_t = struct packed { + logic req; // we request a new word + logic kill_s1; // kill the current request + logic kill_s2; // kill the last request + logic spec; // request is speculative + logic [CVA6Cfg.VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup + }, + localparam type icache_drsp_t = struct packed { + logic ready; // icache is ready + logic valid; // signals a valid read + logic [CVA6Cfg.FETCH_WIDTH-1:0] data; // 2+ cycle out: tag + logic [CVA6Cfg.FETCH_USER_WIDTH-1:0] user; // User bits + logic [CVA6Cfg.VLEN-1:0] vaddr; // virtual address out + exception_t ex; // we've encountered an exception + }, + + // IF/ID Stage + // store the decompressed instruction + localparam type fetch_entry_t = struct packed { + logic [CVA6Cfg.VLEN-1:0] address; // the address of the instructions from below + logic [31:0] instruction; // instruction word + branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path + exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions + }, + //JVT struct{base,mode} + localparam type jvt_t = struct packed { + logic [CVA6Cfg.XLEN-7:0] base; + logic [5:0] mode; + }, + + // ID/EX/WB Stage + localparam type scoreboard_entry_t = struct packed { + logic [CVA6Cfg.VLEN-1:0] pc; // PC of instruction + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry + // with the transaction id in any case make the width more generic + fu_t fu; // functional unit to use + fu_op op; // operation to perform in each functional unit + logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1 + logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2 + logic [REG_ADDR_SIZE-1:0] rd; // register destination address + logic [CVA6Cfg.XLEN-1:0] result; // for unfinished instructions this field also holds the immediate, + // for unfinished floating-point that are partly encoded in rs2, this field also holds rs2 + // for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB) + // this field holds the address of the third operand from the floating-point register file + logic valid; // is the result valid + logic use_imm; // should we use the immediate as operand b? + logic use_zimm; // use zimm as operand a + logic use_pc; // set if we need to use the PC as operand a, PC from exception + exception_t ex; // exception has occurred + branchpredict_sbe_t bp; // branch predict scoreboard data structure + logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if + // we want jump accordingly e.g.: +4, +2 + logic is_macro_instr; // is an instruction executed as predefined sequence of instructions called macro definition + logic is_last_macro_instr; // is last decoded 32bit instruction of macro definition + logic is_double_rd_macro_instr; // is double move decoded 32bit instruction of macro definition + logic vfp; // is this a vector floating-point instruction? + logic is_zcmt; //is a zcmt instruction + }, + localparam type writeback_t = struct packed { + logic valid; // wb data is valid + logic [CVA6Cfg.XLEN-1:0] data; //wb data + logic ex_valid; // exception from WB + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; //transaction ID + }, + + // branch-predict + // this is the struct we get back from ex stage and we will use it to update + // all the necessary data structures + // bp_resolve_t + localparam type bp_resolve_t = struct packed { + logic valid; // prediction with all its values is valid + logic [CVA6Cfg.VLEN-1:0] pc; // PC of predict or mis-predict + logic [CVA6Cfg.VLEN-1:0] target_address; // target address at which to jump, or not + logic is_mispredict; // set if this was a mis-predict + logic is_taken; // branch is taken + cf_t cf_type; // Type of control flow change + }, + + // All information needed to determine whether we need to associate an interrupt + // with the corresponding instruction or not. + localparam type irq_ctrl_t = struct packed { + logic [CVA6Cfg.XLEN-1:0] mie; + logic [CVA6Cfg.XLEN-1:0] mip; + logic [CVA6Cfg.XLEN-1:0] mideleg; + logic [CVA6Cfg.XLEN-1:0] hideleg; + logic sie; + logic global_enable; + }, + + localparam type lsu_ctrl_t = struct packed { + logic valid; + logic [CVA6Cfg.VLEN-1:0] vaddr; + logic [31:0] tinst; + logic hs_ld_st_inst; + logic hlvx_inst; + logic overflow; + logic g_overflow; + logic [CVA6Cfg.XLEN-1:0] data; + logic [(CVA6Cfg.XLEN/8)-1:0] be; + fu_t fu; + fu_op operation; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; + }, + + localparam type fu_data_t = struct packed { + fu_t fu; + fu_op operation; + logic [CVA6Cfg.XLEN-1:0] operand_a; + logic [CVA6Cfg.XLEN-1:0] operand_b; + logic [CVA6Cfg.XLEN-1:0] imm; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; + }, + + localparam type icache_req_t = struct packed { + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] way; // way to replace + logic [CVA6Cfg.PLEN-1:0] paddr; // physical address + logic nc; // noncacheable + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }, + localparam type icache_rtrn_t = struct packed { + wt_cache_pkg::icache_in_t rtype; // see definitions above + logic [CVA6Cfg.ICACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [CVA6Cfg.ICACHE_USER_LINE_WIDTH-1:0] user; // user bits + struct packed { + logic vld; // invalidate only affected way + logic all; // invalidate all ways + logic [CVA6Cfg.ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate + logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate + } inv; // invalidation vector + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }, + + // D$ data requests + localparam type dcache_req_i_t = struct packed { + logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] address_index; + logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] address_tag; + logic [CVA6Cfg.XLEN-1:0] data_wdata; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_wuser; + logic data_req; + logic data_we; + logic [(CVA6Cfg.XLEN/8)-1:0] data_be; + logic [1:0] data_size; + logic [CVA6Cfg.DcacheIdWidth-1:0] data_id; + logic kill_req; + logic tag_valid; + }, + + localparam type dcache_req_o_t = struct packed { + logic data_gnt; + logic data_rvalid; + logic [CVA6Cfg.DcacheIdWidth-1:0] data_rid; + logic [CVA6Cfg.XLEN-1:0] data_rdata; + logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser; + }, + + // Accelerator - CVA6 + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + + // Accelerator - CVA6's MMU + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + + // AXI types + parameter type axi_ar_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiAddrWidth-1:0] addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type axi_aw_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiAddrWidth-1:0] addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + axi_pkg::atop_t atop; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type axi_w_chan_t = struct packed { + logic [CVA6Cfg.AxiDataWidth-1:0] data; + logic [(CVA6Cfg.AxiDataWidth/8)-1:0] strb; + logic last; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type b_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + axi_pkg::resp_t resp; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type r_chan_t = struct packed { + logic [CVA6Cfg.AxiIdWidth-1:0] id; + logic [CVA6Cfg.AxiDataWidth-1:0] data; + axi_pkg::resp_t resp; + logic last; + logic [CVA6Cfg.AxiUserWidth-1:0] user; + }, + parameter type noc_req_t = struct packed { + axi_aw_chan_t aw; + logic aw_valid; + axi_w_chan_t w; + logic w_valid; + logic b_ready; + axi_ar_chan_t ar; + logic ar_valid; + logic r_ready; + }, + parameter type noc_resp_t = struct packed { + logic aw_ready; + logic ar_ready; + logic w_ready; + logic b_valid; + b_chan_t b; + logic r_valid; + r_chan_t r; + }, + // + parameter type acc_cfg_t = logic, + parameter acc_cfg_t AccCfg = '0, + // CVXIF Types + parameter type readregflags_t = `READREGFLAGS_T(CVA6Cfg), + parameter type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg), + parameter type id_t = `ID_T(CVA6Cfg), + parameter type hartid_t = `HARTID_T(CVA6Cfg), + parameter type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t), + parameter type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg), + parameter type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t), + parameter type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t), + parameter type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t), + parameter type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t), + parameter type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t), + parameter type cvxif_req_t = + `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t), + parameter type cvxif_resp_t = + `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t) +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Reset boot address - SUBSYSTEM + input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, + // Hard ID reflected as CSR - SUBSYSTEM + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + // Level sensitive (async) interrupts - SUBSYSTEM + input logic [1:0] irq_i, + // Inter-processor (async) interrupt - SUBSYSTEM + input logic ipi_i, + // Timer (async) interrupt - SUBSYSTEM + input logic time_irq_i, + // Debug (async) request - SUBSYSTEM + input logic debug_req_i, + // Probes to build RVFI, can be left open when not used - RVFI + output rvfi_probes_t rvfi_probes_o, + // CVXIF request - SUBSYSTEM + output cvxif_req_t cvxif_req_o, + // CVXIF response - SUBSYSTEM + input cvxif_resp_t cvxif_resp_i, + // noc request, can be AXI or OpenPiton - SUBSYSTEM + output noc_req_t noc_req_o, + // noc response, can be AXI or OpenPiton - SUBSYSTEM + input noc_resp_t noc_resp_i +); + + localparam type interrupts_t = struct packed { + logic [CVA6Cfg.XLEN-1:0] S_SW; + logic [CVA6Cfg.XLEN-1:0] VS_SW; + logic [CVA6Cfg.XLEN-1:0] M_SW; + logic [CVA6Cfg.XLEN-1:0] S_TIMER; + logic [CVA6Cfg.XLEN-1:0] VS_TIMER; + logic [CVA6Cfg.XLEN-1:0] M_TIMER; + logic [CVA6Cfg.XLEN-1:0] S_EXT; + logic [CVA6Cfg.XLEN-1:0] VS_EXT; + logic [CVA6Cfg.XLEN-1:0] M_EXT; + logic [CVA6Cfg.XLEN-1:0] HS_EXT; + }; + + localparam interrupts_t INTERRUPTS = '{ + S_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_SOFT), + VS_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_SOFT), + M_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_SOFT), + S_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_TIMER), + VS_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_TIMER), + M_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_TIMER), + S_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_EXT), + VS_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_EXT), + M_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_EXT), + HS_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_HS_EXT) + }; + + // ------------------------------------------ + // Global Signals + // Signals connecting more than one module + // ------------------------------------------ + riscv::priv_lvl_t priv_lvl; + logic v; + exception_t ex_commit; // exception from commit stage + bp_resolve_t resolved_branch; + logic [ CVA6Cfg.VLEN-1:0] pc_commit; + logic eret; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack; + + localparam NumPorts = 4; + + // CVXIF + cvxif_req_t cvxif_req; + // CVXIF OUTPUTS + logic x_compressed_valid; + x_compressed_req_t x_compressed_req; + logic x_issue_valid; + x_issue_req_t x_issue_req; + logic x_register_valid; + x_register_t x_register; + logic x_commit_valid; + x_commit_t x_commit; + logic x_result_ready; + // CVXIF INPUTS + logic x_compressed_ready; + x_compressed_resp_t x_compressed_resp; + logic x_issue_ready; + x_issue_resp_t x_issue_resp; + logic x_register_ready; + logic x_result_valid; + x_result_t x_result; + + // -------------- + // PCGEN <-> CSR + // -------------- + logic [CVA6Cfg.VLEN-1:0] trap_vector_base_commit_pcgen; + logic [CVA6Cfg.VLEN-1:0] epc_commit_pcgen; + // -------------- + // IF <-> ID + // -------------- + fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_if_id; + logic [CVA6Cfg.NrIssuePorts-1:0] fetch_valid_if_id; + logic [CVA6Cfg.NrIssuePorts-1:0] fetch_ready_id_if; + + // -------------- + // ID <-> ISSUE + // -------------- + scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_entry_id_issue, issue_entry_id_issue_prev; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_id_issue; + logic [CVA6Cfg.NrIssuePorts-1:0] issue_entry_valid_id_issue; + logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_fow_id_issue; + logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_issue_id; + + // -------------- + // ISSUE <-> EX + // -------------- + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2; + + fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_id_ex; + logic [CVA6Cfg.VLEN-1:0] pc_id_ex; + logic zcmt_id_ex; + logic is_compressed_instr_id_ex; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_ex; + // fixed latency units + logic flu_ready_ex_id; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_ex_id; + logic flu_valid_ex_id; + logic [CVA6Cfg.XLEN-1:0] flu_result_ex_id; + exception_t flu_exception_ex_id; + // ALU + logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_id_ex; + // Branches and Jumps + logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_id_ex; + + branchpredict_sbe_t branch_predict_id_ex; + logic resolve_branch_ex_id; + // LSU + logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_id_ex; + logic lsu_ready_ex_id; + + logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_ex_id; + logic [CVA6Cfg.XLEN-1:0] load_result_ex_id; + logic load_valid_ex_id; + exception_t load_exception_ex_id; + + logic [CVA6Cfg.XLEN-1:0] store_result_ex_id; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_ex_id; + logic store_valid_ex_id; + exception_t store_exception_ex_id; + // MULT + logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_id_ex; + // FPU + logic fpu_ready_ex_id; + logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_id_ex; + logic [1:0] fpu_fmt_id_ex; + logic [2:0] fpu_rm_id_ex; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_ex_id; + logic [CVA6Cfg.XLEN-1:0] fpu_result_ex_id; + logic fpu_valid_ex_id; + exception_t fpu_exception_ex_id; + // ALU2 + logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_id_ex; + // Accelerator + logic stall_acc_id; + scoreboard_entry_t issue_instr_id_acc; + logic issue_instr_hs_id_acc; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] acc_trans_id_ex_id; + logic [CVA6Cfg.XLEN-1:0] acc_result_ex_id; + logic acc_valid_ex_id; + exception_t acc_exception_ex_id; + logic halt_acc_ctrl; + logic [4:0] acc_resp_fflags; + logic acc_resp_fflags_valid; + logic single_step_acc_commit; + // CSR + logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_id_ex; + logic csr_hs_ld_st_inst_ex; + // CVXIF + logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_ex_id; + logic [CVA6Cfg.XLEN-1:0] x_result_ex_id; + logic x_valid_ex_id; + exception_t x_exception_ex_id; + logic x_we_ex_id; + logic [4:0] x_rd_ex_id; + logic [CVA6Cfg.NrIssuePorts-1:0] x_issue_valid_id_ex; + logic x_issue_ready_ex_id; + logic [31:0] x_off_instr_id_ex; + logic x_transaction_rejected; + // -------------- + // EX <-> COMMIT + // -------------- + // CSR Commit + logic csr_commit_commit_ex; + logic dirty_fp_state; + logic dirty_v_state; + // LSU Commit + logic lsu_commit_commit_ex; + logic lsu_commit_ready_ex_commit; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_commit_trans_id; + logic stall_st_pending_ex; + logic no_st_pending_ex; + logic no_st_pending_commit; + logic amo_valid_commit; + // ACCEL Commit + logic acc_valid_acc_ex; + // -------------- + // EX <-> ACC_DISP + // -------------- + acc_mmu_req_t acc_mmu_req; + acc_mmu_resp_t acc_mmu_resp; + // -------------- + // ID <-> COMMIT + // -------------- + scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_id_commit; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_id_commit; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_commit_id; + + // -------------- + // RVFI + // -------------- + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer; + // -------------- + // COMMIT <-> ID + // -------------- + logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_commit_id; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_commit_id; + logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_commit_id; + logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_commit_id; + // -------------- + // CSR <-> * + // -------------- + logic [4:0] fflags_csr_commit; + riscv::xs_t fs; + riscv::xs_t vfs; + logic [2:0] frm_csr_id_issue_ex; + logic [6:0] fprec_csr_ex; + riscv::xs_t vs; + logic enable_translation_csr_ex; + logic enable_g_translation_csr_ex; + logic en_ld_st_translation_csr_ex; + logic en_ld_st_g_translation_csr_ex; + riscv::priv_lvl_t ld_st_priv_lvl_csr_ex; + logic ld_st_v_csr_ex; + logic sum_csr_ex; + logic vs_sum_csr_ex; + logic mxr_csr_ex; + logic vmxr_csr_ex; + logic [CVA6Cfg.PPNW-1:0] satp_ppn_csr_ex; + logic [CVA6Cfg.ASID_WIDTH-1:0] asid_csr_ex; + logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_csr_ex; + logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_csr_ex; + logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_csr_ex; + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_csr_ex; + logic [11:0] csr_addr_ex_csr; + fu_op csr_op_commit_csr; + logic [CVA6Cfg.XLEN-1:0] csr_wdata_commit_csr; + logic [CVA6Cfg.XLEN-1:0] csr_rdata_csr_commit; + exception_t csr_exception_csr_commit; + logic tvm_csr_id; + logic tw_csr_id; + logic vtw_csr_id; + logic tsr_csr_id; + logic hu; + irq_ctrl_t irq_ctrl_csr_id; + logic dcache_en_csr_nbdcache; + logic csr_write_fflags_commit_cs; + logic icache_en_csr; + logic acc_cons_en_csr; + logic debug_mode; + logic single_step_csr_commit; + riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg; + logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr; + logic [31:0] mcountinhibit_csr_perf; + //jvt + jvt_t jvt; + // ---------------------------- + // Performance Counters <-> * + // ---------------------------- + logic [11:0] addr_csr_perf; + logic [CVA6Cfg.XLEN-1:0] data_csr_perf, data_perf_csr; + logic we_csr_perf; + + logic icache_flush_ctrl_cache; + logic itlb_miss_ex_perf; + logic dtlb_miss_ex_perf; + logic dcache_miss_cache_perf; + logic icache_miss_cache_perf; + logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits; + logic stall_issue; + // -------------- + // CTRL <-> * + // -------------- + logic set_pc_ctrl_pcgen; + logic flush_csr_ctrl; + logic flush_unissued_instr_ctrl_id; + logic flush_ctrl_if; + logic flush_ctrl_id; + logic flush_ctrl_ex; + logic flush_ctrl_bp; + logic flush_tlb_ctrl_ex; + logic flush_tlb_vvma_ctrl_ex; + logic flush_tlb_gvma_ctrl_ex; + logic fence_i_commit_controller; + logic fence_commit_controller; + logic sfence_vma_commit_controller; + logic hfence_vvma_commit_controller; + logic hfence_gvma_commit_controller; + logic halt_ctrl; + logic halt_csr_ctrl; + logic dcache_flush_ctrl_cache; + logic dcache_flush_ack_cache_ctrl; + logic set_debug_pc; + logic flush_commit; + logic flush_acc; + + icache_areq_t icache_areq_ex_cache; + icache_arsp_t icache_areq_cache_ex; + icache_dreq_t icache_dreq_if_cache; + icache_drsp_t icache_dreq_cache_if; + + amo_req_t amo_req; + amo_resp_t amo_resp; + logic sb_full; + + // ---------------- + // DCache <-> * + // ---------------- + dcache_req_i_t [2:0] dcache_req_ports_ex_cache; + dcache_req_o_t [2:0] dcache_req_ports_cache_ex; + dcache_req_i_t dcache_req_ports_id_cache; + dcache_req_o_t dcache_req_ports_cache_id; + dcache_req_i_t [1:0] dcache_req_ports_acc_cache; + dcache_req_o_t [1:0] dcache_req_ports_cache_acc; + logic dcache_commit_wbuffer_empty; + logic dcache_commit_wbuffer_not_ni; + + //RVFI + lsu_ctrl_t rvfi_lsu_ctrl; + logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr; + logic [CVA6Cfg.NrIssuePorts-1:0] rvfi_is_compressed; + rvfi_probes_csr_t rvfi_csr; + + // Accelerator port + logic [63:0] inval_addr; + logic inval_valid; + logic inval_ready; + + // -------------- + // Frontend + // -------------- + frontend #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .fetch_entry_t(fetch_entry_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t) + ) i_frontend ( + .clk_i, + .rst_ni, + .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), + .flush_bp_i (1'b0), + .flush_i (flush_ctrl_if), // not entirely correct + .halt_i (halt_ctrl), + .set_pc_commit_i (set_pc_ctrl_pcgen), + .pc_commit_i (pc_commit), + .ex_valid_i (ex_commit.valid), + .resolved_branch_i (resolved_branch), + .eret_i (eret), + .epc_i (epc_commit_pcgen), + .trap_vector_base_i (trap_vector_base_commit_pcgen), + .set_debug_pc_i (set_debug_pc), + .debug_mode_i (debug_mode), + .icache_dreq_o (icache_dreq_if_cache), + .icache_dreq_i (icache_dreq_cache_if), + .fetch_entry_o (fetch_entry_if_id), + .fetch_entry_valid_o(fetch_valid_if_id), + .fetch_entry_ready_i(fetch_ready_id_if) + ); + + // --------- + // ID + // --------- + id_stage #( + .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), + .fetch_entry_t(fetch_entry_t), + .jvt_t(jvt_t), + .irq_ctrl_t(irq_ctrl_t), + .scoreboard_entry_t(scoreboard_entry_t), + .interrupts_t(interrupts_t), + .INTERRUPTS(INTERRUPTS), + .x_compressed_req_t(x_compressed_req_t), + .x_compressed_resp_t(x_compressed_resp_t) + ) id_stage_i ( + .clk_i, + .rst_ni, + .flush_i(flush_ctrl_if), + .debug_req_i, + + .fetch_entry_i (fetch_entry_if_id), + .fetch_entry_valid_i(fetch_valid_if_id), + .fetch_entry_ready_o(fetch_ready_id_if), + + .issue_entry_o (issue_entry_id_issue), + .issue_entry_o_prev (issue_entry_id_issue_prev), + .orig_instr_o (orig_instr_id_issue), + .issue_entry_valid_o(issue_entry_valid_id_issue), + .is_ctrl_flow_o (is_ctrl_fow_id_issue), + .issue_instr_ack_i (issue_instr_issue_id), + + .rvfi_is_compressed_o(rvfi_is_compressed), + + .priv_lvl_i (priv_lvl), + .v_i (v), + .fs_i (fs), + .vfs_i (vfs), + .frm_i (frm_csr_id_issue_ex), + .vs_i (vs), + .irq_i (irq_i), + .irq_ctrl_i (irq_ctrl_csr_id), + .debug_mode_i (debug_mode), + .tvm_i (tvm_csr_id), + .tw_i (tw_csr_id), + .vtw_i (vtw_csr_id), + .tsr_i (tsr_csr_id), + .hu_i (hu), + .hart_id_i (hart_id_i), + .compressed_ready_i(x_compressed_ready), + .compressed_resp_i (x_compressed_resp), + .compressed_valid_o(x_compressed_valid), + .compressed_req_o (x_compressed_req), + .jvt_i (jvt), + // DCACHE interfaces + .dcache_req_ports_i(dcache_req_ports_cache_id), + .dcache_req_ports_o(dcache_req_ports_id_cache) + ); + + logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_ex_id; + logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_ex_id; + exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_ex_id; // exception from execute, ex_stage to id_stage + logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_ex_id; + + assign trans_id_ex_id[FLU_WB] = flu_trans_id_ex_id; + assign wbdata_ex_id[FLU_WB] = flu_result_ex_id; + assign ex_ex_ex_id[FLU_WB] = flu_exception_ex_id; + assign wt_valid_ex_id[FLU_WB] = flu_valid_ex_id; + + assign trans_id_ex_id[STORE_WB] = store_trans_id_ex_id; + assign wbdata_ex_id[STORE_WB] = store_result_ex_id; + assign ex_ex_ex_id[STORE_WB] = store_exception_ex_id; + assign wt_valid_ex_id[STORE_WB] = store_valid_ex_id; + + assign trans_id_ex_id[LOAD_WB] = load_trans_id_ex_id; + assign wbdata_ex_id[LOAD_WB] = load_result_ex_id; + assign ex_ex_ex_id[LOAD_WB] = load_exception_ex_id; + assign wt_valid_ex_id[LOAD_WB] = load_valid_ex_id; + + assign trans_id_ex_id[FPU_WB] = fpu_trans_id_ex_id; + assign wbdata_ex_id[FPU_WB] = fpu_result_ex_id; + assign ex_ex_ex_id[FPU_WB] = fpu_exception_ex_id; + assign wt_valid_ex_id[FPU_WB] = fpu_valid_ex_id; + + if (CVA6Cfg.CvxifEn) begin + always_comb begin : gen_cvxif_input_assignement + x_compressed_ready = cvxif_resp_i.compressed_ready; + x_compressed_resp = cvxif_resp_i.compressed_resp; + x_issue_ready = cvxif_resp_i.issue_ready; + x_issue_resp = cvxif_resp_i.issue_resp; + x_register_ready = cvxif_resp_i.register_ready; + x_result_valid = cvxif_resp_i.result_valid; + x_result = cvxif_resp_i.result; + end + + always_comb begin : gen_cvxif_output_assignement + cvxif_req.compressed_valid = x_compressed_valid; + cvxif_req.compressed_req = x_compressed_req; + cvxif_req.issue_valid = x_issue_valid; + cvxif_req.issue_req = x_issue_req; + cvxif_req.register_valid = x_register_valid; + cvxif_req.register = x_register; + cvxif_req.commit_valid = x_commit_valid; + cvxif_req.commit = x_commit; + cvxif_req.result_ready = x_result_ready; + end + assign trans_id_ex_id[X_WB] = x_trans_id_ex_id; + assign wbdata_ex_id[X_WB] = x_result_ex_id; + assign ex_ex_ex_id[X_WB] = x_exception_ex_id; + assign wt_valid_ex_id[X_WB] = x_valid_ex_id; + end else if (CVA6Cfg.EnableAccelerator) begin + assign cvxif_req = '0; + assign trans_id_ex_id[ACC_WB] = acc_trans_id_ex_id; + assign wbdata_ex_id[ACC_WB] = acc_result_ex_id; + assign ex_ex_ex_id[ACC_WB] = acc_exception_ex_id; + assign wt_valid_ex_id[ACC_WB] = acc_valid_ex_id; + end else begin + assign cvxif_req = '0; + end + + if (CVA6Cfg.CvxifEn && CVA6Cfg.EnableAccelerator) begin : gen_err_xif_and_acc + $error("X-interface and accelerator port cannot be enabled at the same time."); + end + + // --------- + // Issue + // --------- + issue_stage #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), + .fu_data_t(fu_data_t), + .scoreboard_entry_t(scoreboard_entry_t), + .writeback_t(writeback_t), + .x_issue_req_t(x_issue_req_t), + .x_issue_resp_t(x_issue_resp_t), + .x_register_t(x_register_t), + .x_commit_t(x_commit_t) + ) issue_stage_i ( + .clk_i, + .rst_ni, + .sb_full_o (sb_full), + .flush_unissued_instr_i (flush_unissued_instr_ctrl_id), + .flush_i (flush_ctrl_id), + .stall_i (stall_acc_id), + // ID Stage + .decoded_instr_i (issue_entry_id_issue), + .decoded_instr_i_prev (issue_entry_id_issue_prev), + .orig_instr_i (orig_instr_id_issue), + .decoded_instr_valid_i (issue_entry_valid_id_issue), + .is_ctrl_flow_i (is_ctrl_fow_id_issue), + .decoded_instr_ack_o (issue_instr_issue_id), + // Functional Units + .rs1_forwarding_o (rs1_forwarding_id_ex), + .rs2_forwarding_o (rs2_forwarding_id_ex), + .fu_data_o (fu_data_id_ex), + .pc_o (pc_id_ex), + .is_zcmt_o (zcmt_id_ex), + .is_compressed_instr_o (is_compressed_instr_id_ex), + .tinst_o (tinst_ex), + // fixed latency unit ready + .flu_ready_i (flu_ready_ex_id), + // ALU + .alu_valid_o (alu_valid_id_ex), + // Branches and Jumps + .branch_valid_o (branch_valid_id_ex), // branch is valid + .branch_predict_o (branch_predict_id_ex), // branch predict to ex + .resolve_branch_i (resolve_branch_ex_id), // in order to resolve the branch + // LSU + .lsu_ready_i (lsu_ready_ex_id), + .lsu_valid_o (lsu_valid_id_ex), + // Multiplier + .mult_valid_o (mult_valid_id_ex), + // FPU + .fpu_ready_i (fpu_ready_ex_id), + .fpu_valid_o (fpu_valid_id_ex), + .fpu_fmt_o (fpu_fmt_id_ex), + .fpu_rm_o (fpu_rm_id_ex), + // ALU2 + .alu2_valid_o (alu2_valid_id_ex), + // CSR + .csr_valid_o (csr_valid_id_ex), + // CVXIF + .xfu_valid_o (x_issue_valid_id_ex), + .xfu_ready_i (x_issue_ready_ex_id), + .x_off_instr_o (x_off_instr_id_ex), + .hart_id_i (hart_id_i), + .x_issue_ready_i (x_issue_ready), + .x_issue_resp_i (x_issue_resp), + .x_issue_valid_o (x_issue_valid), + .x_issue_req_o (x_issue_req), + .x_register_ready_i (x_register_ready), + .x_register_valid_o (x_register_valid), + .x_register_o (x_register), + .x_commit_valid_o (x_commit_valid), + .x_commit_o (x_commit), + .x_transaction_rejected_o(x_transaction_rejected), + // Accelerator + .issue_instr_o (issue_instr_id_acc), + .issue_instr_hs_o (issue_instr_hs_id_acc), + // Commit + .trans_id_i (trans_id_ex_id), + .resolved_branch_i (resolved_branch), + .wbdata_i (wbdata_ex_id), + .ex_ex_i (ex_ex_ex_id), + .wt_valid_i (wt_valid_ex_id), + .x_we_i (x_we_ex_id), + .x_rd_i (x_rd_ex_id), + + .waddr_i (waddr_commit_id), + .wdata_i (wdata_commit_id), + .we_gpr_i (we_gpr_commit_id), + .we_fpr_i (we_fpr_commit_id), + .commit_instr_o (commit_instr_id_commit), + .commit_drop_o (commit_drop_id_commit), + .commit_ack_i (commit_ack_commit_id), + // Performance Counters + .stall_issue_o (stall_issue), + //RVFI + .rvfi_issue_pointer_o (rvfi_issue_pointer), + .rvfi_commit_pointer_o(rvfi_commit_pointer), + .rvfi_rs1_o (rvfi_rs1), + .rvfi_rs2_o (rvfi_rs2) + ); + + // --------- + // EX + // --------- + ex_stage #( + .CVA6Cfg (CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), + .fu_data_t(fu_data_t), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .lsu_ctrl_t(lsu_ctrl_t), + .x_result_t(x_result_t), + .acc_mmu_req_t(acc_mmu_req_t), + .acc_mmu_resp_t(acc_mmu_resp_t) + ) ex_stage_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .debug_mode_i(debug_mode), + .flush_i(flush_ctrl_ex), + .rs1_forwarding_i(rs1_forwarding_id_ex), + .rs2_forwarding_i(rs2_forwarding_id_ex), + .fu_data_i(fu_data_id_ex), + .pc_i(pc_id_ex), + .is_zcmt_i(zcmt_id_ex), + .is_compressed_instr_i(is_compressed_instr_id_ex), + .tinst_i(tinst_ex), + // fixed latency units + .flu_result_o(flu_result_ex_id), + .flu_trans_id_o(flu_trans_id_ex_id), + .flu_valid_o(flu_valid_ex_id), + .flu_exception_o(flu_exception_ex_id), + .flu_ready_o(flu_ready_ex_id), + // ALU + .alu_valid_i(alu_valid_id_ex), + // Branches and Jumps + .branch_valid_i(branch_valid_id_ex), + .branch_predict_i(branch_predict_id_ex), // branch predict to ex + .resolved_branch_o(resolved_branch), + .resolve_branch_o(resolve_branch_ex_id), + // CSR + .csr_valid_i(csr_valid_id_ex), + .csr_addr_o(csr_addr_ex_csr), + .csr_commit_i(csr_commit_commit_ex), // from commit + .csr_hs_ld_st_inst_o(csr_hs_ld_st_inst_ex), // signals a Hypervisor Load/Store Instruction + // MULT + .mult_valid_i(mult_valid_id_ex), + // LSU + .lsu_ready_o(lsu_ready_ex_id), + .lsu_valid_i(lsu_valid_id_ex), + + .load_result_o (load_result_ex_id), + .load_trans_id_o (load_trans_id_ex_id), + .load_valid_o (load_valid_ex_id), + .load_exception_o(load_exception_ex_id), + + .store_result_o (store_result_ex_id), + .store_trans_id_o (store_trans_id_ex_id), + .store_valid_o (store_valid_ex_id), + .store_exception_o(store_exception_ex_id), + + .lsu_commit_i (lsu_commit_commit_ex), // from commit + .lsu_commit_ready_o (lsu_commit_ready_ex_commit), // to commit + .commit_tran_id_i (lsu_commit_trans_id), // from commit + .stall_st_pending_i (stall_st_pending_ex), + .no_st_pending_o (no_st_pending_ex), + // FPU + .fpu_ready_o (fpu_ready_ex_id), + .fpu_valid_i (fpu_valid_id_ex), + .fpu_fmt_i (fpu_fmt_id_ex), + .fpu_rm_i (fpu_rm_id_ex), + .fpu_frm_i (frm_csr_id_issue_ex), + .fpu_prec_i (fprec_csr_ex), + .fpu_trans_id_o (fpu_trans_id_ex_id), + .fpu_result_o (fpu_result_ex_id), + .fpu_valid_o (fpu_valid_ex_id), + .fpu_exception_o (fpu_exception_ex_id), + // ALU2 + .alu2_valid_i (alu2_valid_id_ex), + .amo_valid_commit_i (amo_valid_commit), + .amo_req_o (amo_req), + .amo_resp_i (amo_resp), + // CoreV-X-Interface + .x_valid_i (x_issue_valid_id_ex), + .x_ready_o (x_issue_ready_ex_id), + .x_off_instr_i (x_off_instr_id_ex), + .x_transaction_rejected_i(x_transaction_rejected), + .x_trans_id_o (x_trans_id_ex_id), + .x_exception_o (x_exception_ex_id), + .x_result_o (x_result_ex_id), + .x_valid_o (x_valid_ex_id), + .x_we_o (x_we_ex_id), + .x_rd_o (x_rd_ex_id), + .x_result_valid_i (x_result_valid), + .x_result_i (x_result), + .x_result_ready_o (x_result_ready), + // Accelerator + .acc_valid_i (acc_valid_acc_ex), + // Accelerator MMU access + .acc_mmu_req_i (acc_mmu_req), + .acc_mmu_resp_o (acc_mmu_resp), + // Performance counters + .itlb_miss_o (itlb_miss_ex_perf), + .dtlb_miss_o (dtlb_miss_ex_perf), + // Memory Management + .enable_translation_i (enable_translation_csr_ex), // from CSR + .enable_g_translation_i (enable_g_translation_csr_ex), // from CSR + .en_ld_st_translation_i (en_ld_st_translation_csr_ex), + .en_ld_st_g_translation_i(en_ld_st_g_translation_csr_ex), + .flush_tlb_i (flush_tlb_ctrl_ex), + .flush_tlb_vvma_i (flush_tlb_vvma_ctrl_ex), + .flush_tlb_gvma_i (flush_tlb_gvma_ctrl_ex), + .priv_lvl_i (priv_lvl), // from CSR + .v_i (v), // from CSR + .ld_st_priv_lvl_i (ld_st_priv_lvl_csr_ex), // from CSR + .ld_st_v_i (ld_st_v_csr_ex), // from CSR + .sum_i (sum_csr_ex), // from CSR + .vs_sum_i (vs_sum_csr_ex), // from CSR + .mxr_i (mxr_csr_ex), // from CSR + .vmxr_i (vmxr_csr_ex), // from CSR + .satp_ppn_i (satp_ppn_csr_ex), // from CSR + .asid_i (asid_csr_ex), // from CSR + .vsatp_ppn_i (vsatp_ppn_csr_ex), // from CSR + .vs_asid_i (vs_asid_csr_ex), // from CSR + .hgatp_ppn_i (hgatp_ppn_csr_ex), // from CSR + .vmid_i (vmid_csr_ex), // from CSR + .icache_areq_i (icache_areq_cache_ex), + .icache_areq_o (icache_areq_ex_cache), + // DCACHE interfaces + .dcache_req_ports_i (dcache_req_ports_cache_ex), + .dcache_req_ports_o (dcache_req_ports_ex_cache), + .dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty), + .dcache_wbuffer_not_ni_i (dcache_commit_wbuffer_not_ni), + // PMP + .pmpcfg_i (pmpcfg), + .pmpaddr_i (pmpaddr), + //RVFI + .rvfi_lsu_ctrl_o (rvfi_lsu_ctrl), + .rvfi_mem_paddr_o (rvfi_mem_paddr) + ); + + // --------- + // Commit + // --------- + + // we have to make sure that the whole write buffer path is empty before + // used e.g. for fence instructions. + assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty; + + commit_stage #( + .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), + .scoreboard_entry_t(scoreboard_entry_t) + ) commit_stage_i ( + .clk_i, + .rst_ni, + .halt_i (halt_ctrl), + .flush_dcache_i (dcache_flush_ctrl_cache), + .exception_o (ex_commit), + .dirty_fp_state_o (dirty_fp_state), + .single_step_i (single_step_csr_commit || single_step_acc_commit), + .commit_instr_i (commit_instr_id_commit), + .commit_drop_i (commit_drop_id_commit), + .commit_ack_o (commit_ack_commit_id), + .commit_macro_ack_o(commit_macro_ack), + .waddr_o (waddr_commit_id), + .wdata_o (wdata_commit_id), + .we_gpr_o (we_gpr_commit_id), + .we_fpr_o (we_fpr_commit_id), + .amo_resp_i (amo_resp), + .pc_o (pc_commit), + .csr_op_o (csr_op_commit_csr), + .csr_wdata_o (csr_wdata_commit_csr), + .csr_rdata_i (csr_rdata_csr_commit), + .csr_write_fflags_o(csr_write_fflags_commit_cs), + .csr_exception_i (csr_exception_csr_commit), + .commit_lsu_o (lsu_commit_commit_ex), + .commit_lsu_ready_i(lsu_commit_ready_ex_commit), + .commit_tran_id_o (lsu_commit_trans_id), + .amo_valid_commit_o(amo_valid_commit), + .no_st_pending_i (no_st_pending_commit), + .commit_csr_o (csr_commit_commit_ex), + .fence_i_o (fence_i_commit_controller), + .fence_o (fence_commit_controller), + .flush_commit_o (flush_commit), + .sfence_vma_o (sfence_vma_commit_controller), + .hfence_vvma_o (hfence_vvma_commit_controller), + .hfence_gvma_o (hfence_gvma_commit_controller) + ); + + assign commit_ack = commit_macro_ack & ~commit_drop_id_commit; + + // --------- + // CSR + // --------- + csr_regfile #( + .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), + .jvt_t (jvt_t), + .irq_ctrl_t (irq_ctrl_t), + .scoreboard_entry_t(scoreboard_entry_t), + .rvfi_probes_csr_t (rvfi_probes_csr_t), + .MHPMCounterNum (MHPMCounterNum) + ) csr_regfile_i ( + .clk_i, + .rst_ni, + .time_irq_i, + .flush_o (flush_csr_ctrl), + .halt_csr_o (halt_csr_ctrl), + .commit_instr_i (commit_instr_id_commit[0]), + .commit_ack_i (commit_ack), + .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), + .hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]), + .ex_i (ex_commit), + .csr_op_i (csr_op_commit_csr), + .csr_addr_i (csr_addr_ex_csr), + .csr_wdata_i (csr_wdata_commit_csr), + .csr_rdata_o (csr_rdata_csr_commit), + .dirty_fp_state_i (dirty_fp_state), + .csr_write_fflags_i (csr_write_fflags_commit_cs), + .dirty_v_state_i (dirty_v_state), + .pc_i (pc_commit), + .csr_exception_o (csr_exception_csr_commit), + .epc_o (epc_commit_pcgen), + .eret_o (eret), + .trap_vector_base_o (trap_vector_base_commit_pcgen), + .priv_lvl_o (priv_lvl), + .v_o (v), + .acc_fflags_ex_i (acc_resp_fflags), + .acc_fflags_ex_valid_i (acc_resp_fflags_valid), + .fs_o (fs), + .vfs_o (vfs), + .fflags_o (fflags_csr_commit), + .frm_o (frm_csr_id_issue_ex), + .fprec_o (fprec_csr_ex), + .vs_o (vs), + .irq_ctrl_o (irq_ctrl_csr_id), + .en_translation_o (enable_translation_csr_ex), + .en_g_translation_o (enable_g_translation_csr_ex), + .en_ld_st_translation_o (en_ld_st_translation_csr_ex), + .en_ld_st_g_translation_o(en_ld_st_g_translation_csr_ex), + .ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex), + .ld_st_v_o (ld_st_v_csr_ex), + .csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex), + .sum_o (sum_csr_ex), + .vs_sum_o (vs_sum_csr_ex), + .mxr_o (mxr_csr_ex), + .vmxr_o (vmxr_csr_ex), + .satp_ppn_o (satp_ppn_csr_ex), + .asid_o (asid_csr_ex), + .vsatp_ppn_o (vsatp_ppn_csr_ex), + .vs_asid_o (vs_asid_csr_ex), + .hgatp_ppn_o (hgatp_ppn_csr_ex), + .vmid_o (vmid_csr_ex), + .irq_i, + .ipi_i, + .debug_req_i, + .set_debug_pc_o (set_debug_pc), + .tvm_o (tvm_csr_id), + .tw_o (tw_csr_id), + .vtw_o (vtw_csr_id), + .tsr_o (tsr_csr_id), + .hu_o (hu), + .debug_mode_o (debug_mode), + .single_step_o (single_step_csr_commit), + .icache_en_o (icache_en_csr), + .dcache_en_o (dcache_en_csr_nbdcache), + .acc_cons_en_o (acc_cons_en_csr), + .perf_addr_o (addr_csr_perf), + .perf_data_o (data_csr_perf), + .perf_data_i (data_perf_csr), + .perf_we_o (we_csr_perf), + .pmpcfg_o (pmpcfg), + .pmpaddr_o (pmpaddr), + .mcountinhibit_o (mcountinhibit_csr_perf), + .jvt_o (jvt), + //RVFI + .rvfi_csr_o (rvfi_csr) + ); + + // ------------------------ + // Performance Counters + // ------------------------ + if (CVA6Cfg.PerfCounterEn) begin : gen_perf_counter + perf_counters #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .exception_t(exception_t), + .scoreboard_entry_t(scoreboard_entry_t), + .icache_dreq_t(icache_dreq_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts(NumPorts) + ) perf_counters_i ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .debug_mode_i (debug_mode), + .addr_i (addr_csr_perf), + .we_i (we_csr_perf), + .data_i (data_csr_perf), + .data_o (data_perf_csr), + .commit_instr_i(commit_instr_id_commit), + .commit_ack_i (commit_ack), + + .l1_icache_miss_i (icache_miss_cache_perf), + .l1_dcache_miss_i (dcache_miss_cache_perf), + .itlb_miss_i (itlb_miss_ex_perf), + .dtlb_miss_i (dtlb_miss_ex_perf), + .sb_full_i (sb_full), + // TODO this is more complex that that + // If superscalar then we additionally have to check [1] when transaction 0 succeeded + .if_empty_i (~fetch_valid_if_id[0]), + .ex_i (ex_commit), + .eret_i (eret), + .resolved_branch_i (resolved_branch), + .branch_exceptions_i(flu_exception_ex_id), + .l1_icache_access_i (icache_dreq_if_cache), + .l1_dcache_access_i (dcache_req_ports_ex_cache), + .miss_vld_bits_i (miss_vld_bits), + .i_tlb_flush_i (flush_tlb_ctrl_ex), + .stall_issue_i (stall_issue), + .mcountinhibit_i (mcountinhibit_csr_perf) + ); + end : gen_perf_counter + else begin : gen_no_perf_counter + assign data_perf_csr = '0; + end : gen_no_perf_counter + + // ------------ + // Controller + // ------------ + controller #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t) + ) controller_i ( + .clk_i, + .rst_ni, + // virtualization mode + .v_i (v), + // flush ports + .set_pc_commit_o (set_pc_ctrl_pcgen), + .flush_if_o (flush_ctrl_if), + .flush_unissued_instr_o(flush_unissued_instr_ctrl_id), + .flush_id_o (flush_ctrl_id), + .flush_ex_o (flush_ctrl_ex), + .flush_bp_o (flush_ctrl_bp), + .flush_icache_o (icache_flush_ctrl_cache), + .flush_dcache_o (dcache_flush_ctrl_cache), + .flush_dcache_ack_i (dcache_flush_ack_cache_ctrl), + .flush_tlb_o (flush_tlb_ctrl_ex), + .flush_tlb_vvma_o (flush_tlb_vvma_ctrl_ex), + .flush_tlb_gvma_o (flush_tlb_gvma_ctrl_ex), + .halt_csr_i (halt_csr_ctrl), + .halt_acc_i (halt_acc_ctrl), + .halt_o (halt_ctrl), + // control ports + .eret_i (eret), + .ex_valid_i (ex_commit.valid), + .set_debug_pc_i (set_debug_pc), + .resolved_branch_i (resolved_branch), + .flush_csr_i (flush_csr_ctrl), + .fence_i_i (fence_i_commit_controller), + .fence_i (fence_commit_controller), + .sfence_vma_i (sfence_vma_commit_controller), + .hfence_vvma_i (hfence_vvma_commit_controller), + .hfence_gvma_i (hfence_gvma_commit_controller), + .flush_commit_i (flush_commit), + .flush_acc_i (flush_acc) + ); + + // ------------------- + // Cache Subsystem + // ------------------- + + // Acc dispatcher and store buffer share a dcache request port. + // Store buffer always has priority access over acc dipsatcher. + dcache_req_i_t [NumPorts-1:0] dcache_req_to_cache; + dcache_req_o_t [NumPorts-1:0] dcache_req_from_cache; + + // D$ request + // Since ZCMT is only enable for embdeed class so MMU should be disable. + // Cache port 0 is being ultilize in implicit read access in ZCMT extension. + if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin + assign dcache_req_to_cache[0] = dcache_req_ports_id_cache; + end else begin + assign dcache_req_to_cache[0] = dcache_req_ports_ex_cache[0]; + end + assign dcache_req_to_cache[1] = dcache_req_ports_ex_cache[1]; + assign dcache_req_to_cache[2] = dcache_req_ports_acc_cache[0]; + assign dcache_req_to_cache[3] = dcache_req_ports_ex_cache[2].data_req ? dcache_req_ports_ex_cache [2] : + dcache_req_ports_acc_cache[1]; + + // D$ response + // Since ZCMT is only enable for embdeed class so MMU should be disable. + // Cache port 0 is being ultilized in implicit read access in ZCMT extension. + if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin + assign dcache_req_ports_cache_id = dcache_req_from_cache[0]; + assign dcache_req_ports_cache_ex[0] = '0; + end else begin + assign dcache_req_ports_cache_ex[0] = dcache_req_from_cache[0]; + assign dcache_req_ports_cache_id = '0; + end + assign dcache_req_ports_cache_ex[1] = dcache_req_from_cache[1]; + assign dcache_req_ports_cache_acc[0] = dcache_req_from_cache[2]; + always_comb begin : gen_dcache_req_store_data_gnt + dcache_req_ports_cache_ex[2] = dcache_req_from_cache[3]; + dcache_req_ports_cache_acc[1] = dcache_req_from_cache[3]; + + // Set gnt signal + dcache_req_ports_cache_ex[2].data_gnt &= dcache_req_ports_ex_cache[2].data_req; + dcache_req_ports_cache_acc[1].data_gnt &= !dcache_req_ports_ex_cache[2].data_req; + end + + if (CVA6Cfg.DCacheType == config_pkg::WT) begin : gen_cache_wt + // this is a cache subsystem that is compatible with OpenPiton + wt_cache_subsystem #( + .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts (NumPorts), + .noc_req_t (noc_req_t), + .noc_resp_t(noc_resp_t) + ) i_cache_subsystem ( + // to D$ + .clk_i (clk_i), + .rst_ni (rst_ni), + // I$ + .icache_en_i (icache_en_csr), + .icache_flush_i (icache_flush_ctrl_cache), + .icache_miss_o (icache_miss_cache_perf), + .icache_areq_i (icache_areq_ex_cache), + .icache_areq_o (icache_areq_cache_ex), + .icache_dreq_i (icache_dreq_if_cache), + .icache_dreq_o (icache_dreq_cache_if), + // D$ + .dcache_enable_i (dcache_en_csr_nbdcache), + .dcache_flush_i (dcache_flush_ctrl_cache), + .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), + // to commit stage + .dcache_amo_req_i (amo_req), + .dcache_amo_resp_o (amo_resp), + // from PTW, Load Unit and Store Unit + .dcache_miss_o (dcache_miss_cache_perf), + .miss_vld_bits_o (miss_vld_bits), + .dcache_req_ports_i(dcache_req_to_cache), + .dcache_req_ports_o(dcache_req_from_cache), + // write buffer status + .wbuffer_empty_o (dcache_commit_wbuffer_empty), + .wbuffer_not_ni_o (dcache_commit_wbuffer_not_ni), + // memory side + .noc_req_o (noc_req_o), + .noc_resp_i (noc_resp_i), + .inval_addr_i (inval_addr), + .inval_valid_i (inval_valid), + .inval_ready_o (inval_ready) + ); + end else if ( + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT || + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB || + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB + ) + begin : gen_cache_hpd + cva6_hpdcache_subsystem #( + .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts (NumPorts), + .axi_ar_chan_t(axi_ar_chan_t), + .axi_aw_chan_t(axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_b_chan_t (b_chan_t), + .axi_r_chan_t (r_chan_t), + .noc_req_t (noc_req_t), + .noc_resp_t(noc_resp_t), + .cmo_req_t (logic /*FIXME*/), + .cmo_rsp_t (logic /*FIXME*/) + ) i_cache_subsystem ( + .clk_i (clk_i), + .rst_ni(rst_ni), + + .icache_en_i (icache_en_csr), + .icache_flush_i(icache_flush_ctrl_cache), + .icache_miss_o (icache_miss_cache_perf), + .icache_areq_i (icache_areq_ex_cache), + .icache_areq_o (icache_areq_cache_ex), + .icache_dreq_i (icache_dreq_if_cache), + .icache_dreq_o (icache_dreq_cache_if), + + .dcache_enable_i (dcache_en_csr_nbdcache), + .dcache_flush_i (dcache_flush_ctrl_cache), + .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), + .dcache_miss_o (dcache_miss_cache_perf), + + .dcache_amo_req_i (amo_req), + .dcache_amo_resp_o(amo_resp), + + .dcache_cmo_req_i ('0 /*FIXME*/), + .dcache_cmo_resp_o( /*FIXME*/), + + .dcache_req_ports_i(dcache_req_to_cache), + .dcache_req_ports_o(dcache_req_from_cache), + + .wbuffer_empty_o (dcache_commit_wbuffer_empty), + .wbuffer_not_ni_o(dcache_commit_wbuffer_not_ni), + + .hwpf_base_set_i ('0 /*FIXME*/), + .hwpf_base_i ('0 /*FIXME*/), + .hwpf_base_o ( /*FIXME*/), + .hwpf_param_set_i ('0 /*FIXME*/), + .hwpf_param_i ('0 /*FIXME*/), + .hwpf_param_o ( /*FIXME*/), + .hwpf_throttle_set_i('0 /*FIXME*/), + .hwpf_throttle_i ('0 /*FIXME*/), + .hwpf_throttle_o ( /*FIXME*/), + .hwpf_status_o ( /*FIXME*/), + + .noc_req_o (noc_req_o), + .noc_resp_i(noc_resp_i) + ); + assign inval_ready = 1'b1; + end else begin : gen_cache_wb + std_cache_subsystem #( + // note: this only works with one cacheable region + // not as important since this cache subsystem is about to be + // deprecated + .CVA6Cfg (CVA6Cfg), + .icache_areq_t (icache_areq_t), + .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .NumPorts (NumPorts), + .axi_ar_chan_t (axi_ar_chan_t), + .axi_aw_chan_t (axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_req_t (noc_req_t), + .axi_rsp_t (noc_resp_t) + ) i_cache_subsystem ( + // to D$ + .clk_i (clk_i), + .rst_ni (rst_ni), + .priv_lvl_i (priv_lvl), + // I$ + .icache_en_i (icache_en_csr), + .icache_flush_i (icache_flush_ctrl_cache), + .icache_miss_o (icache_miss_cache_perf), + .icache_areq_i (icache_areq_ex_cache), + .icache_areq_o (icache_areq_cache_ex), + .icache_dreq_i (icache_dreq_if_cache), + .icache_dreq_o (icache_dreq_cache_if), + // D$ + .dcache_enable_i (dcache_en_csr_nbdcache), + .dcache_flush_i (dcache_flush_ctrl_cache), + .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), + // to commit stage + .amo_req_i (amo_req), + .amo_resp_o (amo_resp), + .dcache_miss_o (dcache_miss_cache_perf), + // this is statically set to 1 as the std_cache does not have a wbuffer + .wbuffer_empty_o (dcache_commit_wbuffer_empty), + // from PTW, Load Unit and Store Unit + .dcache_req_ports_i(dcache_req_to_cache), + .dcache_req_ports_o(dcache_req_from_cache), + // memory side + .axi_req_o (noc_req_o), + .axi_resp_i (noc_resp_i) + ); + assign dcache_commit_wbuffer_not_ni = 1'b1; + assign inval_ready = 1'b1; + end + + // ---------------- + // Accelerator + // ---------------- + + if (CVA6Cfg.EnableAccelerator) begin : gen_accelerator + acc_dispatcher #( + .CVA6Cfg (CVA6Cfg), + .fu_data_t (fu_data_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), + .exception_t (exception_t), + .scoreboard_entry_t(scoreboard_entry_t), + .acc_cfg_t (acc_cfg_t), + .AccCfg (AccCfg), + .acc_req_t (cvxif_req_t), + .acc_resp_t (cvxif_resp_t), + .accelerator_req_t (accelerator_req_t), + .accelerator_resp_t(accelerator_resp_t), + .acc_mmu_req_t (acc_mmu_req_t), + .acc_mmu_resp_t (acc_mmu_resp_t) + ) i_acc_dispatcher ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_unissued_instr_i(flush_unissued_instr_ctrl_id), + .flush_ex_i (flush_ctrl_ex), + .flush_pipeline_o (flush_acc), + .single_step_o (single_step_acc_commit), + .acc_cons_en_i (acc_cons_en_csr), + .acc_fflags_valid_o (acc_resp_fflags_valid), + .acc_fflags_o (acc_resp_fflags), + .ld_st_priv_lvl_i (ld_st_priv_lvl_csr_ex), + .sum_i (sum_csr_ex), + .pmpcfg_i (pmpcfg), + .pmpaddr_i (pmpaddr), + .fcsr_frm_i (frm_csr_id_issue_ex), + .acc_mmu_en_i (enable_translation_csr_ex), + .dirty_v_state_o (dirty_v_state), + .issue_instr_i (issue_instr_id_acc), + .issue_instr_hs_i (issue_instr_hs_id_acc), + .issue_stall_o (stall_acc_id), + .fu_data_i (fu_data_id_ex[0]), + .commit_instr_i (commit_instr_id_commit), + .commit_st_barrier_i (fence_i_commit_controller | fence_commit_controller), + .acc_trans_id_o (acc_trans_id_ex_id), + .acc_result_o (acc_result_ex_id), + .acc_valid_o (acc_valid_ex_id), + .acc_exception_o (acc_exception_ex_id), + .acc_valid_ex_o (acc_valid_acc_ex), + .commit_ack_i (commit_ack), + .acc_stall_st_pending_o(stall_st_pending_ex), + .acc_no_st_pending_i (no_st_pending_commit), + .dcache_req_ports_i (dcache_req_ports_ex_cache), + .acc_mmu_req_o (acc_mmu_req), + .acc_mmu_resp_i (acc_mmu_resp), + .ctrl_halt_o (halt_acc_ctrl), + .csr_addr_i (csr_addr_ex_csr), + .acc_dcache_req_ports_o(dcache_req_ports_acc_cache), + .acc_dcache_req_ports_i(dcache_req_ports_cache_acc), + .inval_ready_i (inval_ready), + .inval_valid_o (inval_valid), + .inval_addr_o (inval_addr), + .acc_req_o (cvxif_req_o), + .acc_resp_i (cvxif_resp_i) + ); + end : gen_accelerator + else begin : gen_no_accelerator + assign acc_trans_id_ex_id = '0; + assign acc_result_ex_id = '0; + assign acc_valid_ex_id = '0; + assign acc_exception_ex_id = '0; + assign acc_resp_fflags = '0; + assign acc_resp_fflags_valid = '0; + assign stall_acc_id = '0; + assign dirty_v_state = '0; + assign acc_valid_acc_ex = '0; + assign halt_acc_ctrl = '0; + assign stall_st_pending_ex = '0; + assign flush_acc = '0; + assign single_step_acc_commit = '0; + + // D$ connection is unused + assign dcache_req_ports_acc_cache = '0; + + // MMU access is unused + assign acc_mmu_req = '0; + + // No invalidation interface + assign inval_valid = '0; + assign inval_addr = '0; + + // Feed through cvxif + assign cvxif_req_o = cvxif_req; + end : gen_no_accelerator + + // ------------------- + // Parameter Check + // ------------------- + // pragma translate_off + initial config_pkg::check_cfg(CVA6Cfg); + // pragma translate_on + + // ------------------- + // Instruction Tracer + // ------------------- + + //pragma translate_off +`ifdef PITON_ARIANE + localparam PC_QUEUE_DEPTH = 16; + + logic piton_pc_vld; + logic [ CVA6Cfg.VLEN-1:0] piton_pc; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] pc_data; + logic [CVA6Cfg.NrCommitPorts-1:0] pc_pop, pc_empty; + + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_pc_fifo + fifo_v3 #( + .DATA_WIDTH(64), + .DEPTH(PC_QUEUE_DEPTH), + .FPGA_EN(CVA6Cfg.FpgaEn) + ) i_pc_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i ('0), + .testmode_i('0), + .full_o (), + .empty_o (pc_empty[i]), + .usage_o (), + .data_i (commit_instr_id_commit[i].pc), + .push_i (commit_ack[i] & ~commit_instr_id_commit[i].ex.valid), + .data_o (pc_data[i]), + .pop_i (pc_pop[i]) + ); + end + + rr_arb_tree #( + .NumIn(CVA6Cfg.NrCommitPorts), + .DataWidth(64) + ) i_rr_arb_tree ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i('0), + .rr_i ('0), + .req_i (~pc_empty), + .gnt_o (pc_pop), + .data_i (pc_data), + .gnt_i (piton_pc_vld), + .req_o (piton_pc_vld), + .data_o (piton_pc), + .idx_o () + ); +`endif // PITON_ARIANE + +`ifndef VERILATOR + instr_tracer #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .scoreboard_entry_t(scoreboard_entry_t), + .interrupts_t(interrupts_t), + .exception_t(exception_t), + .INTERRUPTS(INTERRUPTS) + ) instr_tracer_i ( + // .tracer_if(tracer_if), + .pck(clk_i), + .rstn(rst_ni), + .flush_unissued(flush_unissued_instr_ctrl_id), + .flush_all(flush_ctrl_ex), + .instruction(id_stage_i.fetch_entry_i[0].instruction), + .fetch_valid(id_stage_i.fetch_entry_valid_i[0]), + .fetch_ack(id_stage_i.fetch_entry_ready_o[0]), + .issue_ack(issue_stage_i.i_scoreboard.issue_ack_i), + .issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o), + .waddr(waddr_commit_id), + .wdata(wdata_commit_id), + .we_gpr(we_gpr_commit_id), + .we_fpr(we_fpr_commit_id), + .commit_instr(commit_instr_id_commit), + .commit_ack(commit_ack), + .st_valid(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i), + .st_paddr(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i), + .ld_valid(ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid), + .ld_kill(ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req), + .ld_paddr(ex_stage_i.lsu_i.i_load_unit.paddr_i), + .resolve_branch(resolved_branch), + .commit_exception(commit_stage_i.exception_o), + .priv_lvl(priv_lvl), + .debug_mode(debug_mode), + .hart_id_i(hart_id_i) + ); + + // mock tracer for Verilator, to be used with spike-dasm +`else + + int f; + logic [63:0] cycles; + + initial begin + string fn; + $sformat(fn, "trace_hart_%0.0f.dasm", hart_id_i); + f = $fopen(fn, "w"); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + cycles <= 0; + end else begin + byte mode = ""; + if (CVA6Cfg.DebugEn && debug_mode) mode = "D"; + else begin + case (priv_lvl) + riscv::PRIV_LVL_M: mode = "M"; + riscv::PRIV_LVL_S: if (CVA6Cfg.RVS) mode = "S"; + riscv::PRIV_LVL_U: mode = "U"; + default: ; // Do nothing + endcase + end + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, + commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); + end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin + if (commit_instr_id_commit[i].ex.cause == 2) begin + $fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", + commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); + end else begin + if (CVA6Cfg.DebugEn && debug_mode) begin + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, + mode, commit_instr_id_commit[i].ex.tval[31:0], + commit_instr_id_commit[i].ex.tval[31:0]); + end else begin + $fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", + commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0], + commit_instr_id_commit[i].pc); + end + end + end + end + cycles <= cycles + 1; + end + end + + final begin + $fclose(f); + end +`endif // VERILATOR + //pragma translate_on + + + //RVFI INSTR + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] rvfi_fetch_instr; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign rvfi_fetch_instr[i] = fetch_entry_if_id[i].instruction; + end + + cva6_rvfi_probes #( + .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), + .scoreboard_entry_t (scoreboard_entry_t), + .lsu_ctrl_t (lsu_ctrl_t), + .rvfi_probes_instr_t(rvfi_probes_instr_t), + .rvfi_probes_csr_t (rvfi_probes_csr_t), + .rvfi_probes_t (rvfi_probes_t) + ) i_cva6_rvfi_probes ( + + .flush_i (flush_ctrl_if), + .issue_instr_ack_i (issue_instr_issue_id), + .fetch_entry_valid_i(fetch_valid_if_id), + .instruction_i (rvfi_fetch_instr), + .is_compressed_i (rvfi_is_compressed), + + .issue_pointer_i (rvfi_issue_pointer), + .commit_pointer_i(rvfi_commit_pointer), + + .flush_unissued_instr_i(flush_unissued_instr_ctrl_id), + .decoded_instr_valid_i (issue_entry_valid_id_issue), + .decoded_instr_ack_i (issue_instr_issue_id), + + .rs1_i(rvfi_rs1), + .rs2_i(rvfi_rs2), + + .commit_instr_i(commit_instr_id_commit), + .commit_drop_i (commit_drop_id_commit), + .ex_commit_i (ex_commit), + .priv_lvl_i (priv_lvl), + + .lsu_ctrl_i (rvfi_lsu_ctrl), + .wbdata_i (wbdata_ex_id), + .commit_ack_i(commit_ack), + .mem_paddr_i (rvfi_mem_paddr), + .debug_mode_i(debug_mode), + .wdata_i (wdata_commit_id), + + .csr_i(rvfi_csr), + .irq_i(irq_i), + + .rvfi_probes_o(rvfi_probes_o) + + ); + + //pragma translate_off + initial begin + assert (!(CVA6Cfg.SuperscalarEn && CVA6Cfg.EnableAccelerator)) + else $fatal(1, "Accelerator is not supported by superscalar pipeline"); + end + //pragma translate_on + +endmodule // ariane diff --git a/flow/designs/src/cva6/core/cva6_accel_first_pass_decoder_stub.sv b/flow/designs/src/cva6/core/cva6_accel_first_pass_decoder_stub.sv new file mode 100644 index 0000000000..7996bce6cb --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_accel_first_pass_decoder_stub.sv @@ -0,0 +1,34 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Nils Wistoff + +// Module stub for the cva6_accel_first_pass_decoder. Replace this with your accelerator's +// first pass decoder. + +module cva6_accel_first_pass_decoder + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = '0, + parameter type scoreboard_entry_t = logic +) ( + input logic [31:0] instruction_i, // instruction from IF + input riscv::xs_t fs_i, // floating point extension status + input riscv::xs_t vs_i, // vector extension status + output logic is_accel_o, // is an accelerator instruction + output scoreboard_entry_t instruction_o, // predecoded instruction + output logic illegal_instr_o, // is an illegal instruction + output logic is_control_flow_instr_o // is a control flow instruction +); + + assign is_accel_o = 1'b0; + assign instruction_o = '0; + assign illegal_instr_o = 1'b0; + assign is_control_flow_instr_o = 1'b0; + + $error("cva6_accel_first_pass_decoder: instantiated non-functional module stub.\ + Please replace this with your accelerator's first pass decoder \ + (or unset ENABLE_ACCELERATOR)."); + +endmodule : cva6_accel_first_pass_decoder diff --git a/flow/designs/src/cva6/core/cva6_fifo_v3.sv b/flow/designs/src/cva6/core/cva6_fifo_v3.sv new file mode 100644 index 0000000000..d1faa01b3a --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_fifo_v3.sv @@ -0,0 +1,231 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba +// Additional contributions by: +// Angela Gonzalez - PlanV Technologies + +module cva6_fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter bit FPGA_ALTERA = 1'b0, // FPGA Altera optimizations enabled + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter type dtype = logic [DATA_WIDTH-1:0], + parameter bit FPGA_EN = 1'b0, + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + // local parameter + // FIFO depth - handle the case of pass-through, synthesizer will do constant propagation + localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1; + // clock gating control + logic gate_clock; + // pointer to the read and write section of the queue + logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q; + // keep a counter to keep track of the current queue status + // this integer will be truncated by the synthesis tool + logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q; + // actual memory + dtype [FifoDepth - 1:0] mem_n, mem_q; + dtype data_ft_n, data_ft_q; + logic first_word_n, first_word_q; + + // fifo ram signals for fpga target + logic fifo_ram_we; + logic [ADDR_DEPTH-1:0] fifo_ram_read_address; + logic [ADDR_DEPTH-1:0] fifo_ram_write_address; + logic [$bits(dtype)-1:0] fifo_ram_wdata; + logic [$bits(dtype)-1:0] fifo_ram_rdata; + + assign usage_o = status_cnt_q[ADDR_DEPTH-1:0]; + + if (DEPTH == 0) begin : gen_pass_through + assign empty_o = ~push_i; + assign full_o = ~pop_i; + end else begin : gen_fifo + assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]); + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + // status flags + + // read and write queue logic + always_comb begin : read_write_comb + // default assignment + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + status_cnt_n = status_cnt_q; + if (FPGA_EN && FPGA_ALTERA) data_ft_n = data_ft_q; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q; + if (FPGA_EN) begin + fifo_ram_we = '0; + fifo_ram_write_address = '0; + fifo_ram_wdata = '0; + if (DEPTH == 0) begin + data_o = data_i; + end else begin + if (FPGA_ALTERA) data_o = first_word_q ? data_ft_q : fifo_ram_rdata; + else data_o = fifo_ram_rdata; + end + end else begin + data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; + mem_n = mem_q; + gate_clock = 1'b1; + end + + // push a new element to the queue + if (push_i && ~full_o) begin + if (FPGA_EN) begin + fifo_ram_we = 1'b1; + fifo_ram_write_address = write_pointer_q; + fifo_ram_wdata = data_i; + if (FPGA_ALTERA) first_word_n = first_word_q && pop_i; + end else begin + // push the data onto the queue + mem_n[write_pointer_q] = data_i; + // un-gate the clock, we want to write something + gate_clock = 1'b0; + end + + // increment the write counter + if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1) write_pointer_n = '0; + else write_pointer_n = write_pointer_q + 1; + // increment the overall counter + status_cnt_n = status_cnt_q + 1; + end + + if (pop_i && ~empty_o) begin + data_ft_n = data_i; + if (FPGA_EN && FPGA_ALTERA) first_word_n = first_word_q && push_i; + // read from the queue is a default assignment + // but increment the read pointer... + if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) read_pointer_n = '0; + else read_pointer_n = read_pointer_q + 1; + // ... and decrement the overall count + status_cnt_n = status_cnt_q - 1; + end + + // keep the count pointer stable if we push and pop at the same time + if (push_i && pop_i && ~full_o && ~empty_o) status_cnt_n = status_cnt_q; + + // FIFO is in pass through mode -> do not change the pointers + if ((FALL_THROUGH || (FPGA_EN && FPGA_ALTERA)) && (status_cnt_q == 0) && push_i) begin + if (FALL_THROUGH) data_o = data_i; + if (FPGA_EN && FPGA_ALTERA) begin + data_ft_n = data_i; + first_word_n = '1; + end + if (pop_i) begin + first_word_n = '0; + status_cnt_n = status_cnt_q; + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + end + end + + if (FPGA_EN) fifo_ram_read_address = (FPGA_ALTERA == 1) ? read_pointer_n : read_pointer_q; + else fifo_ram_read_address = '0; + + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + if (FPGA_ALTERA) first_word_q <= '0; + if (FPGA_ALTERA) data_ft_q <= '0; + end else begin + if (flush_i) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + if (FPGA_ALTERA) first_word_q <= '0; + if (FPGA_ALTERA) data_ft_q <= '0; + end else begin + read_pointer_q <= read_pointer_n; + write_pointer_q <= write_pointer_n; + status_cnt_q <= status_cnt_n; + if (FPGA_ALTERA) data_ft_q <= data_ft_n; + if (FPGA_ALTERA) first_word_q <= first_word_n; + end + end + end + + if (FPGA_EN) begin : gen_fpga_queue + if (FPGA_ALTERA) begin + SyncDpRam_ind_r_w #( + .ADDR_WIDTH(ADDR_DEPTH), + .DATA_DEPTH(DEPTH), + .DATA_WIDTH($bits(dtype)) + ) fifo_ram ( + .Clk_CI (clk_i), + .WrEn_SI (fifo_ram_we), + .RdAddr_DI(fifo_ram_read_address), + .WrAddr_DI(fifo_ram_write_address), + .WrData_DI(fifo_ram_wdata), + .RdData_DO(fifo_ram_rdata) + ); + end else begin + AsyncDpRam #( + .ADDR_WIDTH(ADDR_DEPTH), + .DATA_DEPTH(DEPTH), + .DATA_WIDTH($bits(dtype)) + ) fifo_ram ( + .Clk_CI (clk_i), + .WrEn_SI (fifo_ram_we), + .RdAddr_DI(fifo_ram_read_address), + .WrAddr_DI(fifo_ram_write_address), + .WrData_DI(fifo_ram_wdata), + .RdData_DO(fifo_ram_rdata) + ); + end + end else begin : gen_asic_queue + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mem_q <= '0; + end else if (!gate_clock) begin + mem_q <= mem_n; + end + end + end + + // pragma translate_off + initial begin + assert (DEPTH > 0) + else $error("DEPTH must be greater than 0."); + end + + full_write : + assert property (@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i)) + else $fatal(1, "Trying to push new data although the FIFO is full."); + + empty_read : + assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) + else $fatal(1, "Trying to pop data although the FIFO is empty."); + // pragma translate_on + +endmodule // fifo_v3 diff --git a/flow/designs/src/cva6/core/cva6_mmu/cva6_mmu.sv b/flow/designs/src/cva6/core/cva6_mmu/cva6_mmu.sv new file mode 100644 index 0000000000..eebb9b6e46 --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_mmu/cva6_mmu.sv @@ -0,0 +1,762 @@ +// Copyright (c) 2018 ETH Zurich and University of Bologna. +// Copyright (c) 2021 Thales. +// Copyright (c) 2022 Bruno Sá and Zero-Day Labs. +// Copyright (c) 2024 PlanV Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Angela Gonzalez, PlanV Technology +// Date: 26/02/2024 +// +// Description: Memory Management Unit for CVA6, contains TLB and +// address translation unit. SV32 SV39 and SV39x4 as defined in RISC-V +// privilege specification 1.11-WIP. +// This module is an merge of the MMU Sv39 developed +// by Florian Zaruba, the MMU Sv32 developed by Sebastien Jacq and the MMU Sv39x4 developed by Bruno Sá. + + +module cva6_mmu + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter int unsigned HYP_EXT = 0 + +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic enable_translation_i, + input logic enable_g_translation_i, + input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores + input logic en_ld_st_g_translation_i, // enable G-Stage translation for load/stores + // IF interface + input icache_arsp_t icache_areq_i, + output icache_areq_t icache_areq_o, + // LSU interface + // this is a more minimalistic interface because the actual addressing logic is handled + // in the LSU as we distinguish load and stores, what we do here is simple address translation + input exception_t misaligned_ex_i, + input logic lsu_req_i, // request address translation + input logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_i, // virtual address in + input logic [31:0] lsu_tinst_i, // transformed instruction in + input logic lsu_is_store_i, // the translation is requested by a store + output logic csr_hs_ld_st_inst_o, // hyp load store instruction + // if we need to walk the page table we can't grant in the same cycle + // Cycle 0 + output logic lsu_dtlb_hit_o, // sent in same cycle as the request if translation hits in DTLB + output logic [CVA6Cfg.PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit) + // Cycle 1 + output logic lsu_valid_o, // translation is valid + output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address + output exception_t lsu_exception_o, // address translation threw an exception + // General control signals + input riscv::priv_lvl_t priv_lvl_i, + input logic v_i, + input riscv::priv_lvl_t ld_st_priv_lvl_i, + input logic ld_st_v_i, + input logic sum_i, + input logic vs_sum_i, + input logic mxr_i, + input logic vmxr_i, + input logic hlvx_inst_i, + input logic hs_ld_st_inst_i, + // input logic flag_mprv_i, + input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i, + input logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_i, + input logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_i, + + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed_i, + input logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i, + input logic [CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed_i, + + input logic flush_tlb_i, + input logic flush_tlb_vvma_i, + input logic flush_tlb_gvma_i, + + // Performance counters + output logic itlb_miss_o, + output logic dtlb_miss_o, + // PTW memory interface + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o, + + // PMP + + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i +); + + // memory management, pte for cva6 + localparam type pte_cva6_t = struct packed { + logic [9:0] reserved; + logic [CVA6Cfg.PPNW-1:0] ppn; // PPN length for + logic [1:0] rsw; + logic d; + logic a; + logic g; + logic u; + logic x; + logic w; + logic r; + logic v; + }; + + localparam type tlb_update_cva6_t = struct packed { + logic valid; + logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; + logic [CVA6Cfg.VpnLen-1:0] vpn; + logic [CVA6Cfg.ASID_WIDTH-1:0] asid; + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; + logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + pte_cva6_t content; + pte_cva6_t g_content; + }; + + logic iaccess_err; // insufficient privilege to access this instruction page + logic i_g_st_access_err; // insufficient privilege at g stage to access this instruction page + logic daccess_err; // insufficient privilege to access this data page + logic canonical_addr_check; // canonical check on the virtual address for SV39 + logic d_g_st_access_err; // insufficient privilege to access this data page + logic ptw_active; // PTW is currently walking a page table + logic walking_instr; // PTW is walking because of an ITLB miss + logic ptw_error; // PTW threw an exception + logic ptw_error_at_g_st; // PTW threw an exception at the G-Stage + logic ptw_err_at_g_int_st; // PTW threw an exception at the G-Stage during S-Stage translation + logic ptw_access_exception; // PTW threw an access exception (PMPs) + logic [CVA6Cfg.PLEN-1:0] ptw_bad_paddr; // PTW page fault bad physical addr + logic [CVA6Cfg.GPLEN-1:0] ptw_bad_gpaddr; // PTW guest page fault bad guest physical addr + + logic [CVA6Cfg.VLEN-1:0] update_vaddr, shared_tlb_vaddr; + + tlb_update_cva6_t update_itlb, update_dtlb, update_shared_tlb; + + logic itlb_lu_access; + pte_cva6_t itlb_content; + pte_cva6_t itlb_g_content; + logic [ CVA6Cfg.PtLevels-2:0] itlb_is_page; + logic itlb_lu_hit; + logic [ CVA6Cfg.GPLEN-1:0] itlb_gpaddr; + logic [CVA6Cfg.ASID_WIDTH-1:0] itlb_lu_asid; + + logic dtlb_lu_access; + pte_cva6_t dtlb_content; + pte_cva6_t dtlb_g_content; + logic [ CVA6Cfg.PtLevels-2:0] dtlb_is_page; + logic [CVA6Cfg.ASID_WIDTH-1:0] dtlb_lu_asid; + logic dtlb_lu_hit; + logic [ CVA6Cfg.GPLEN-1:0] dtlb_gpaddr; + + logic shared_tlb_access, shared_tlb_miss; + logic shared_tlb_hit, itlb_req; + + // Assignments + + assign itlb_lu_access = icache_areq_i.fetch_req; + assign dtlb_lu_access = lsu_req_i; + assign itlb_lu_asid = v_i ? vs_asid_i : asid_i; + assign dtlb_lu_asid = (ld_st_v_i || flush_tlb_vvma_i) ? vs_asid_i : asid_i; + + + cva6_tlb #( + .CVA6Cfg (CVA6Cfg), + .pte_cva6_t (pte_cva6_t), + .tlb_update_cva6_t(tlb_update_cva6_t), + .TLB_ENTRIES (CVA6Cfg.InstrTlbEntries), + .HYP_EXT (HYP_EXT) + ) i_itlb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_tlb_i), + .flush_vvma_i (flush_tlb_vvma_i), + .flush_gvma_i (flush_tlb_gvma_i), + .s_st_enbl_i (enable_translation_i), + .g_st_enbl_i (enable_g_translation_i), + .v_i (v_i), + .update_i (update_itlb), + .lu_access_i (itlb_lu_access), + .lu_asid_i (itlb_lu_asid), + .lu_vmid_i (vmid_i), + .lu_vaddr_i (icache_areq_i.fetch_vaddr), + .lu_gpaddr_o (itlb_gpaddr), + .lu_content_o (itlb_content), + .lu_g_content_o(itlb_g_content), + .asid_to_be_flushed_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, + .lu_is_page_o (itlb_is_page), + .lu_hit_o (itlb_lu_hit) + ); + + cva6_tlb #( + .CVA6Cfg (CVA6Cfg), + .pte_cva6_t (pte_cva6_t), + .tlb_update_cva6_t(tlb_update_cva6_t), + .TLB_ENTRIES (CVA6Cfg.DataTlbEntries), + .HYP_EXT (HYP_EXT) + ) i_dtlb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_tlb_i), + .flush_vvma_i (flush_tlb_vvma_i), + .flush_gvma_i (flush_tlb_gvma_i), + .s_st_enbl_i (en_ld_st_translation_i), + .g_st_enbl_i (en_ld_st_g_translation_i), + .v_i (ld_st_v_i), + .update_i (update_dtlb), + .lu_access_i (dtlb_lu_access), + .lu_asid_i (itlb_lu_asid), + .lu_vmid_i (vmid_i), + .lu_vaddr_i (lsu_vaddr_i), + .lu_gpaddr_o (dtlb_gpaddr), + .lu_content_o (dtlb_content), + .lu_g_content_o(dtlb_g_content), + .asid_to_be_flushed_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, + .lu_is_page_o (dtlb_is_page), + .lu_hit_o (dtlb_lu_hit) + ); + + + cva6_shared_tlb #( + .CVA6Cfg (CVA6Cfg), + .SHARED_TLB_WAYS (2), + .HYP_EXT (HYP_EXT), + .pte_cva6_t (pte_cva6_t), + .tlb_update_cva6_t(tlb_update_cva6_t) + ) i_shared_tlb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_tlb_i), + .flush_vvma_i (flush_tlb_vvma_i), + .flush_gvma_i (flush_tlb_gvma_i), + .s_st_enbl_i (enable_translation_i), + .g_st_enbl_i (enable_g_translation_i), + .v_i (v_i), + .s_ld_st_enbl_i(en_ld_st_translation_i), + .g_ld_st_enbl_i(en_ld_st_g_translation_i), + .ld_st_v_i (ld_st_v_i), + + .dtlb_asid_i (dtlb_lu_asid), + .itlb_asid_i (itlb_lu_asid), + .lu_vmid_i (vmid_i), + // from TLBs + // did we miss? + .itlb_access_i(itlb_lu_access), + .itlb_hit_i (itlb_lu_hit), + .itlb_vaddr_i (icache_areq_i.fetch_vaddr), + + .dtlb_access_i(dtlb_lu_access), + .dtlb_hit_i (dtlb_lu_hit), + .dtlb_vaddr_i (lsu_vaddr_i), + + // to TLBs, update logic + .itlb_update_o(update_itlb), + .dtlb_update_o(update_dtlb), + + // Performance counters + .itlb_miss_o(itlb_miss_o), + .dtlb_miss_o(dtlb_miss_o), + .shared_tlb_miss_i(shared_tlb_miss), + + .shared_tlb_access_o(shared_tlb_access), + .shared_tlb_hit_o (shared_tlb_hit), + .shared_tlb_vaddr_o (shared_tlb_vaddr), + + .itlb_req_o (itlb_req), + // to update shared tlb + .shared_tlb_update_i(update_shared_tlb) + ); + + cva6_ptw #( + .CVA6Cfg (CVA6Cfg), + .pte_cva6_t (pte_cva6_t), + .tlb_update_cva6_t(tlb_update_cva6_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), + .HYP_EXT (HYP_EXT) + ) i_ptw ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .flush_i, + + .ptw_active_o (ptw_active), + .walking_instr_o (walking_instr), + .ptw_error_o (ptw_error), + .ptw_error_at_g_st_o (ptw_error_at_g_st), + .ptw_err_at_g_int_st_o (ptw_err_at_g_int_st), + .ptw_access_exception_o(ptw_access_exception), + .enable_translation_i, + .enable_g_translation_i, + .en_ld_st_translation_i, + .en_ld_st_g_translation_i, + .v_i, + .ld_st_v_i, + .hlvx_inst_i (hlvx_inst_i), + + .lsu_is_store_i(lsu_is_store_i), + // PTW memory interface + .req_port_i (req_port_i), + .req_port_o (req_port_o), + + // to Shared TLB, update logic + .shared_tlb_update_o(update_shared_tlb), + + .update_vaddr_o(update_vaddr), + + .asid_i, + .vs_asid_i, + .vmid_i, + + // from shared TLB + // did we miss? + .shared_tlb_access_i(shared_tlb_access), + .shared_tlb_hit_i (shared_tlb_hit), + .shared_tlb_vaddr_i (shared_tlb_vaddr), + + .itlb_req_i(itlb_req), + + .satp_ppn_i, + .vsatp_ppn_i, + .hgatp_ppn_i, + .mxr_i, + .vmxr_i, + + // Performance counters + .shared_tlb_miss_o(shared_tlb_miss), //open for now + + // PMP + .pmpcfg_i (pmpcfg_i), + .pmpaddr_i (pmpaddr_i), + .bad_paddr_o(ptw_bad_paddr), + .bad_gpaddr_o(ptw_bad_gpaddr) + ); + + //----------------------- + // Instruction Interface + //----------------------- + localparam int PPNWMin = (CVA6Cfg.PPNW - 1 > 29) ? 29 : CVA6Cfg.PPNW - 1; + + // The instruction interface is a simple request response interface + always_comb begin : instr_interface + // MMU disabled: just pass through + icache_areq_o.fetch_valid = icache_areq_i.fetch_req; + icache_areq_o.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]); + // two potential exception sources: + // 1. HPTW threw an exception -> signal with a page fault exception + // 2. We got an access error because of insufficient permissions -> throw an access exception + icache_areq_o.fetch_exception = '0; + // Check whether we are allowed to access this memory region from a fetch perspective + iaccess_err = icache_areq_i.fetch_req && enable_translation_i && // + (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content.u) // + || ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content.u)); + + if (CVA6Cfg.RVH) + i_g_st_access_err = icache_areq_i.fetch_req && enable_g_translation_i && !itlb_g_content.u; + // MMU enabled: address from TLB, request delayed until hit. Error when TLB + // hit and no access right or TLB hit and translated address not valid (e.g. + // AXI decode error), or when PTW performs walk due to ITLB miss and raises + // an error. + if ((enable_translation_i || enable_g_translation_i)) begin + // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal + if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)) begin + + icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(icache_areq_i.fetch_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end + + icache_areq_o.fetch_valid = 1'b0; + + icache_areq_o.fetch_paddr = { + (enable_g_translation_i && CVA6Cfg.RVH) ? itlb_g_content.ppn : itlb_content.ppn, + icache_areq_i.fetch_vaddr[11:0] + }; + + if (CVA6Cfg.PtLevels == 3 && itlb_is_page[CVA6Cfg.PtLevels-2]) begin + + icache_areq_o.fetch_paddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = icache_areq_i.fetch_vaddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; + + end + + if (itlb_is_page[0]) begin + + icache_areq_o.fetch_paddr[PPNWMin:12] = icache_areq_i.fetch_vaddr[PPNWMin:12]; + + end + // ---------// + // ITLB Hit + // --------// + // if we hit the ITLB output the request signal immediately + if (itlb_lu_hit) begin + icache_areq_o.fetch_valid = icache_areq_i.fetch_req; + if (CVA6Cfg.RVH && i_g_st_access_err) begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_GUEST_PAGE_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(icache_areq_i.fetch_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = itlb_gpaddr[CVA6Cfg.GPLEN-1:0]; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + + // we got an access error + end else if (iaccess_err) begin + // throw a page fault + icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(icache_areq_i.fetch_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end + end else if (ptw_active && walking_instr) begin + // ---------// + // ITLB Miss + // ---------// + // watch out for exceptions happening during walking the page table + icache_areq_o.fetch_valid = ptw_error | ptw_access_exception; + if (ptw_error) begin + if (CVA6Cfg.RVH && ptw_error_at_g_st) begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_GUEST_PAGE_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; + icache_areq_o.fetch_exception.tinst=(ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + icache_areq_o.fetch_exception.gva = v_i; + end + end else begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end + end else begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) //To confirm this is the right TVAL + icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr); + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end + end + end + end + + + //----------------------- + // Data Interface + //----------------------- + logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_n, lsu_vaddr_q; + logic [CVA6Cfg.GPLEN-1:0] lsu_gpaddr_n, lsu_gpaddr_q; + logic [31:0] lsu_tinst_n, lsu_tinst_q; + logic hs_ld_st_inst_n, hs_ld_st_inst_q; + pte_cva6_t dtlb_pte_n, dtlb_pte_q; + pte_cva6_t dtlb_gpte_n, dtlb_gpte_q; + logic lsu_req_n, lsu_req_q; + logic lsu_is_store_n, lsu_is_store_q; + logic dtlb_hit_n, dtlb_hit_q; + logic [CVA6Cfg.PtLevels-2:0] dtlb_is_page_n, dtlb_is_page_q; + exception_t misaligned_ex_n, misaligned_ex_q; + + // check if we need to do translation or if we are always ready (e.g.: we are not translating anything) + assign lsu_dtlb_hit_o = (en_ld_st_translation_i || en_ld_st_g_translation_i) ? dtlb_lu_hit : 1'b1; + + + // The data interface is simpler and only consists of a request/response interface + always_comb begin : data_interface + // save request and DTLB response + lsu_vaddr_n = lsu_vaddr_i; + lsu_req_n = lsu_req_i; + dtlb_pte_n = dtlb_content; + dtlb_hit_n = dtlb_lu_hit; + lsu_is_store_n = lsu_is_store_i; + dtlb_is_page_n = dtlb_is_page; + misaligned_ex_n = misaligned_ex_i; + + lsu_valid_o = lsu_req_q; + lsu_exception_o = misaligned_ex_q; + + // mute misaligned exceptions if there is no request otherwise they will throw accidental exceptions + misaligned_ex_n.valid = misaligned_ex_i.valid & lsu_req_i; + + // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal to bit [CVA6Cfg.SV] + canonical_addr_check = (lsu_req_i && en_ld_st_translation_i && + !((&lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)); + + // Check if the User flag is set, then we may only access it in supervisor mode + // if SUM is enabled + daccess_err = en_ld_st_translation_i && + ((ld_st_priv_lvl_i == riscv::PRIV_LVL_S && (ld_st_v_i ? !vs_sum_i : !sum_i ) && dtlb_pte_q.u) || // SUM is not set and we are trying to access a user page in supervisor mode + (ld_st_priv_lvl_i == riscv::PRIV_LVL_U && !dtlb_pte_q.u)); + + if (CVA6Cfg.RVH) begin + lsu_tinst_n = lsu_tinst_i; + hs_ld_st_inst_n = hs_ld_st_inst_i; + lsu_gpaddr_n[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0] = dtlb_gpaddr[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0]; + csr_hs_ld_st_inst_o = hs_ld_st_inst_i || hs_ld_st_inst_q; + d_g_st_access_err = en_ld_st_g_translation_i && !dtlb_gpte_q.u; + dtlb_gpte_n = dtlb_g_content; + end + + lsu_paddr_o = (CVA6Cfg.PLEN)'(lsu_vaddr_q[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]); + lsu_dtlb_ppn_o = (CVA6Cfg.PPNW)'(lsu_vaddr_n[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):12]); + + // translation is enabled and no misaligned exception occurred + if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_q.valid) begin + lsu_valid_o = 1'b0; + + lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH)? dtlb_g_content.ppn :dtlb_content.ppn; + lsu_paddr_o = { + (en_ld_st_g_translation_i && CVA6Cfg.RVH) ? dtlb_gpte_q.ppn : dtlb_pte_q.ppn, + lsu_vaddr_q[11:0] + }; + + if (CVA6Cfg.PtLevels == 3 && dtlb_is_page_q[CVA6Cfg.PtLevels-2]) begin + lsu_paddr_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_q[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; + lsu_dtlb_ppn_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_n[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; + end + + if (dtlb_is_page_q[0]) begin + lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[PPNWMin:12]; + lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[PPNWMin:12]; + end + + + + // --------- + // DTLB Hit + // -------- + if (dtlb_hit_q && lsu_req_q) begin + lsu_valid_o = 1'b1; + // exception priority: + // PAGE_FAULTS have higher priority than ACCESS_FAULTS + // virtual memory based exceptions are PAGE_FAULTS + // physical memory based exceptions are ACCESS_FAULTS (PMA/PMP) + + // this is a store + if (lsu_is_store_q) begin + // check if the page is write-able and we are not violating privileges + // also check if the dirty flag is set + if(CVA6Cfg.RVH && en_ld_st_g_translation_i && (!dtlb_gpte_q.w || d_g_st_access_err || !dtlb_gpte_q.d)) begin + lsu_exception_o.cause = riscv::STORE_GUEST_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); + lsu_exception_o.tinst = '0; + lsu_exception_o.gva = ld_st_v_i; + end + end else if ((en_ld_st_translation_i || !CVA6Cfg.RVH) && (!dtlb_pte_q.w || daccess_err || canonical_addr_check || !dtlb_pte_q.d)) begin + lsu_exception_o.cause = riscv::STORE_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = lsu_tinst_q; + lsu_exception_o.gva = ld_st_v_i; + end + end + // this is a load + end else begin + if (CVA6Cfg.RVH && d_g_st_access_err) begin + lsu_exception_o.cause = riscv::LOAD_GUEST_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); + lsu_exception_o.tinst = '0; + lsu_exception_o.gva = ld_st_v_i; + end + // check for sufficient access privileges - throw a page fault if necessary + end else if (daccess_err || canonical_addr_check) begin + lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = lsu_tinst_q; + lsu_exception_o.gva = ld_st_v_i; + end + end + end + end else + + // --------- + // DTLB Miss + // --------- + // watch out for exceptions + if (ptw_active && !walking_instr) begin + // page table walker threw an exception + if (ptw_error) begin + // an error makes the translation valid + lsu_valid_o = 1'b1; + // the page table walker can only throw page faults + if (lsu_is_store_q) begin + if (CVA6Cfg.RVH && ptw_error_at_g_st) begin + lsu_exception_o.cause = riscv::STORE_GUEST_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; + lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + lsu_exception_o.gva = ld_st_v_i; + end + end else begin + lsu_exception_o.cause = riscv::STORE_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = lsu_tinst_q; + lsu_exception_o.gva = ld_st_v_i; + end + end + end else begin + if (CVA6Cfg.RVH && ptw_error_at_g_st) begin + lsu_exception_o.cause = riscv::LOAD_GUEST_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; + lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + lsu_exception_o.gva = ld_st_v_i; + end + end else begin + lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = lsu_tinst_q; + lsu_exception_o.gva = ld_st_v_i; + end + end + end + end + if (ptw_access_exception) begin + // an error makes the translation valid + lsu_valid_o = 1'b1; + // Any fault of the page table walk should be based of the original access type + if (lsu_is_store_q && !CVA6Cfg.RVH && CVA6Cfg.PtLevels == 3) begin + lsu_exception_o.cause = riscv::ST_ACCESS_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + end else begin + // the page table walker can only throw page faults + lsu_exception_o.cause = riscv::LD_ACCESS_FAULT; + lsu_exception_o.valid = 1'b1; + if (CVA6Cfg.TvalEn) + lsu_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr + }; + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = lsu_tinst_q; + lsu_exception_o.gva = ld_st_v_i; + end + end + end + end + end + end + + // ---------- + // Registers + // ---------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + lsu_vaddr_q <= '0; + lsu_gpaddr_q <= '0; + lsu_req_q <= '0; + dtlb_pte_q <= '0; + dtlb_gpte_q <= '0; + dtlb_hit_q <= '0; + lsu_is_store_q <= '0; + dtlb_is_page_q <= '0; + lsu_tinst_q <= '0; + hs_ld_st_inst_q <= '0; + misaligned_ex_q <= '0; + end else begin + lsu_vaddr_q <= lsu_vaddr_n; + lsu_req_q <= lsu_req_n; + dtlb_pte_q <= dtlb_pte_n; + dtlb_hit_q <= dtlb_hit_n; + lsu_is_store_q <= lsu_is_store_n; + dtlb_is_page_q <= dtlb_is_page_n; + + if (CVA6Cfg.RVH) begin + lsu_tinst_q <= lsu_tinst_n; + hs_ld_st_inst_q <= hs_ld_st_inst_n; + dtlb_gpte_q <= dtlb_gpte_n; + lsu_gpaddr_q <= lsu_gpaddr_n; + misaligned_ex_q <= misaligned_ex_n; + end + end + end +endmodule diff --git a/flow/designs/src/cva6/core/cva6_mmu/cva6_ptw.sv b/flow/designs/src/cva6/core/cva6_mmu/cva6_ptw.sv new file mode 100644 index 0000000000..1d6444be18 --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_mmu/cva6_ptw.sv @@ -0,0 +1,654 @@ +// Copyright (c) 2018 ETH Zurich and University of Bologna. +// Copyright (c) 2021 Thales. +// Copyright (c) 2022 Bruno Sá and Zero-Day Labs. +// Copyright (c) 2024 PlanV Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Angela Gonzalez, PlanV Technology +// Date: 26/02/2024 +// Description: Hardware-PTW (Page-Table-Walker) for CVA6 supporting sv32, sv39 and sv39x4. +// This module is an merge of the PTW Sv39 developed by Florian Zaruba, +// the PTW Sv32 developed by Sebastien Jacq and the PTW Sv39x4 by Bruno Sá. + +/* verilator lint_off WIDTH */ + +module cva6_ptw + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type pte_cva6_t = logic, + parameter type tlb_update_cva6_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter int unsigned HYP_EXT = 0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush everything, we need to do this because + // actually everything we do is speculative at this stage + // e.g.: there could be a CSR instruction that changes everything + output logic ptw_active_o, + output logic walking_instr_o, // set when walking for TLB + output logic ptw_error_o, // set when an error occurred + output logic ptw_error_at_g_st_o, // set when an error occurred at the G-Stage + output logic ptw_err_at_g_int_st_o, // set when an error occurred at the G-Stage during S-Stage translation + output logic ptw_access_exception_o, // set when an PMP access exception occured + input logic enable_translation_i, // CSRs indicate to enable SV39 VS-Stage translation + input logic enable_g_translation_i, // CSRs indicate to enable SV39 G-Stage translation + input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores + input logic en_ld_st_g_translation_i, // enable G-Stage translation for load/stores + input logic v_i, // current virtualization mode bit + input logic ld_st_v_i, // load/store virtualization mode bit + input logic hlvx_inst_i, // is a HLVX load/store instruction + + input logic lsu_is_store_i, // this translation was triggered by a store + // PTW memory interface + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o, + + + // to TLBs, update logic + output tlb_update_cva6_t shared_tlb_update_o, + + output logic [CVA6Cfg.VLEN-1:0] update_vaddr_o, + + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_i, + + // from TLBs + // did we miss? + input logic shared_tlb_access_i, + input logic shared_tlb_hit_i, + input logic [CVA6Cfg.VLEN-1:0] shared_tlb_vaddr_i, + + input logic itlb_req_i, + + // from CSR file + input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i, // ppn from satp + input logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_i, // ppn from satp + input logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_i, // ppn from hgatp + input logic mxr_i, + input logic vmxr_i, + + // Performance counters + output logic shared_tlb_miss_o, + + // PMP + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, + output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o +); + + // input registers + logic data_rvalid_q; + logic [CVA6Cfg.XLEN-1:0] data_rdata_q; + + pte_cva6_t pte; + // register to perform context switch between stages + pte_cva6_t gpte_q, gpte_d; + assign pte = pte_cva6_t'(data_rdata_q); + + enum logic [2:0] { + IDLE, + WAIT_GRANT, + PTE_LOOKUP, + WAIT_RVALID, + PROPAGATE_ERROR, + PROPAGATE_ACCESS_ERROR, + LATENCY + } + state_q, state_d; + + logic [CVA6Cfg.PtLevels-2:0] misaligned_page; + logic [HYP_EXT:0][CVA6Cfg.PtLevels-2:0] ptw_lvl_n, ptw_lvl_q; + + // define 3 PTW stages to be used in sv39x4. sv32 and sv39 are always in S_STAGE + // S_STAGE -> S/VS-stage normal translation controlled by the satp/vsatp CSRs + // G_INTERMED_STAGE -> Converts the S/VS-stage non-leaf GPA pointers to HPA (controlled by hgatp) + // G_FINAL_STAGE -> Converts the S/VS-stage final GPA to HPA (controlled by hgatp) + enum logic [1:0] { + S_STAGE, + G_INTERMED_STAGE, + G_FINAL_STAGE + } + ptw_stage_q, ptw_stage_d; + + // is this an instruction page table walk? + logic is_instr_ptw_q, is_instr_ptw_n; + logic global_mapping_q, global_mapping_n; + // latched tag signal + logic tag_valid_n, tag_valid_q; + // register the ASID + logic [CVA6Cfg.ASID_WIDTH-1:0] tlb_update_asid_q, tlb_update_asid_n; + // register the VMID + logic [CVA6Cfg.VMID_WIDTH-1:0] tlb_update_vmid_q, tlb_update_vmid_n; + // register the VPN we need to walk, SV39 defines a 39 bit virtual address + logic [CVA6Cfg.VLEN-1:0] vaddr_q, vaddr_n; + logic [HYP_EXT*2:0][CVA6Cfg.PtLevels-2:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vaddr_lvl; + // register the VPN we need to walk, SV39x4 defines a 41 bit virtual address for the G-Stage + logic [CVA6Cfg.GPLEN-1:0] gpaddr_q, gpaddr_n, gpaddr_base; + logic [CVA6Cfg.PtLevels-1:0][CVA6Cfg.GPLEN-1:0] gpaddr; + // 4 byte aligned physical pointer + logic [CVA6Cfg.PLEN-1:0] ptw_pptr_q, ptw_pptr_n; + logic [CVA6Cfg.PLEN-1:0] gptw_pptr_q, gptw_pptr_n; + + // Assignments + assign update_vaddr_o = vaddr_q; + + assign ptw_active_o = (state_q != IDLE); + assign walking_instr_o = is_instr_ptw_q; + // directly output the correct physical address + assign req_port_o.address_index = ptw_pptr_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; + assign req_port_o.address_tag = ptw_pptr_q[CVA6Cfg.DCACHE_INDEX_WIDTH+CVA6Cfg.DCACHE_TAG_WIDTH-1:CVA6Cfg.DCACHE_INDEX_WIDTH]; + // we are never going to kill this request + assign req_port_o.kill_req = '0; + // we are never going to write with the HPTW + assign req_port_o.data_wdata = '0; + // we only issue one single request at a time + assign req_port_o.data_id = '0; + + // ----------- + // TLB Update + // ----------- + + assign gpaddr_base = {pte.ppn[CVA6Cfg.GPPNW-1:0], vaddr_q[11:0]}; + assign gpaddr[CVA6Cfg.PtLevels-1] = gpaddr_base; + assign shared_tlb_update_o.vpn = CVA6Cfg.VpnLen'(vaddr_q[CVA6Cfg.SV+HYP_EXT*2-1:12]); + + genvar z, w; + generate + for (z = 0; z < CVA6Cfg.PtLevels - 1; z++) begin + + // check if the ppn is correctly aligned: + // 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned superpage; stop and raise a page-fault + // exception. + assign misaligned_page[z] = (ptw_lvl_q[0] == (z)) && (pte.ppn[(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-1-z)-1:0] != '0); + + //record the vaddr corresponding to each level + for (w = 0; w < HYP_EXT * 2 + 1; w++) begin + assign vaddr_lvl[w][z] = w==0 ? vaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))] : + w==1 ? gptw_pptr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]: + gpaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]; + end + + if (CVA6Cfg.RVH) begin + assign gpaddr[z][CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0]= (ptw_lvl_q[0] == z) ? vaddr_q[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0] : gpaddr_base[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0]; + assign gpaddr[z][CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1]= (ptw_lvl_q[0] == 0) ? vaddr_q[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1] : gpaddr_base[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1]; + assign gpaddr[z][CVA6Cfg.GPLEN-1:CVA6Cfg.VpnLen+1] = gpaddr_base[CVA6Cfg.GPLEN-1:CVA6Cfg.VpnLen+1]; + end + + + end + endgenerate + + always_comb begin : tlb_update + // update the correct page table level + for (int unsigned y = 0; y < HYP_EXT + 1; y++) begin + for (int unsigned x = 0; x < CVA6Cfg.PtLevels - 1; x++) begin + if((enable_g_translation_i && enable_translation_i) || (en_ld_st_g_translation_i && en_ld_st_translation_i) && CVA6Cfg.RVH) begin + shared_tlb_update_o.is_page[x][y] = (ptw_lvl_q[y==HYP_EXT?0 : 1] == x); + end else if (enable_translation_i || en_ld_st_translation_i || !CVA6Cfg.RVH) begin + shared_tlb_update_o.is_page[x][y] = y == 0 ? (ptw_lvl_q[0] == x) : 1'b0; + end else begin + shared_tlb_update_o.is_page[x][y] = y != 0 ? (ptw_lvl_q[0] == x) : 1'b0; + end + end + end + + // set the global mapping bit + if ((enable_g_translation_i || en_ld_st_g_translation_i) && CVA6Cfg.RVH) begin + shared_tlb_update_o.content = gpte_q | (global_mapping_q << 5); + shared_tlb_update_o.g_content = pte; + end else begin + shared_tlb_update_o.content = (pte | (global_mapping_q << 5)); + shared_tlb_update_o.g_content = '0; + end + + // output the correct ASIDs + shared_tlb_update_o.asid = tlb_update_asid_q; + shared_tlb_update_o.vmid = CVA6Cfg.RVH ? tlb_update_vmid_q : '0; + + bad_paddr_o = ptw_access_exception_o ? ptw_pptr_q : 'b0; + if (CVA6Cfg.RVH) + bad_gpaddr_o[CVA6Cfg.GPLEN-1:0] = ptw_error_at_g_st_o ? ((ptw_stage_q == G_INTERMED_STAGE) ? gptw_pptr_q[CVA6Cfg.GPLEN-1:0] : gpaddr_q) : 'b0; + end + + assign req_port_o.tag_valid = tag_valid_q; + + logic allow_access; + + + + pmp #( + .CVA6Cfg(CVA6Cfg) + ) i_pmp_ptw ( + .addr_i (ptw_pptr_q), + // PTW access are always checked as if in S-Mode... + .priv_lvl_i (riscv::PRIV_LVL_S), + // ...and they are always loads + .access_type_i(riscv::ACCESS_READ), + // Configuration + .conf_addr_i (pmpaddr_i), + .conf_i (pmpcfg_i), + .allow_o (allow_access) + ); + + + assign req_port_o.data_be = CVA6Cfg.XLEN == 32 ? be_gen_32( + req_port_o.address_index[1:0], req_port_o.data_size + ) : '1; + + + + //------------------- + // Page table walker + //------------------- + // A virtual address va is translated into a physical address pa as follows: + // 1. Let a be sptbr.ppn × PAGESIZE, and let i = LEVELS-1. (For Sv39, + // PAGESIZE=2^12 and LEVELS=3.) + // 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For + // Sv32, PTESIZE=4.) + // 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if any bits or encodings + // that are reserved for future standard use are set within pte, stop and raise + // a page-fault exception corresponding to the original access type. + // 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to step 5. + // Otherwise, this PTE is a pointer to the next level of the page table. + // Let i=i-1. If i < 0, stop and raise an access exception. Otherwise, let + // a = pte.ppn × PAGESIZE and go to step 2. + // 5. A leaf PTE has been found. Determine if the requested memory access + // is allowed by the pte.r, pte.w, and pte.x bits. If not, stop and + // raise an access exception. Otherwise, the translation is successful. + // Set pte.a to 1, and, if the memory access is a store, set pte.d to 1. + // The translated physical address is given as follows: + // - pa.pgoff = va.pgoff. + // - If i > 0, then this is a superpage translation and + // pa.ppn[i-1:0] = va.vpn[i-1:0]. + // - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i]. + always_comb begin : ptw + automatic logic [CVA6Cfg.PLEN-1:0] pptr; + // automatic logic [CVA6Cfg.GPLEN-1:0] gpaddr; + // default assignments + // PTW memory interface + tag_valid_n = 1'b0; + req_port_o.data_req = 1'b0; + req_port_o.data_size = 2'(CVA6Cfg.PtLevels); + req_port_o.data_we = 1'b0; + ptw_error_o = 1'b0; + ptw_error_at_g_st_o = 1'b0; + ptw_err_at_g_int_st_o = 1'b0; + ptw_access_exception_o = 1'b0; + shared_tlb_update_o.valid = 1'b0; + is_instr_ptw_n = is_instr_ptw_q; + ptw_lvl_n = ptw_lvl_q; + ptw_pptr_n = ptw_pptr_q; + state_d = state_q; + ptw_stage_d = ptw_stage_q; + global_mapping_n = global_mapping_q; + // input registers + tlb_update_asid_n = tlb_update_asid_q; + vaddr_n = vaddr_q; + pptr = ptw_pptr_q; + + if (CVA6Cfg.RVH) begin + gpaddr_n = gpaddr_q; + gptw_pptr_n = gptw_pptr_q; + gpte_d = gpte_q; + tlb_update_vmid_n = tlb_update_vmid_q; + end + + shared_tlb_miss_o = 1'b0; + + + case (state_q) + + IDLE: begin + // by default we start with the top-most page table + ptw_lvl_n = '0; + global_mapping_n = 1'b0; + is_instr_ptw_n = 1'b0; + + + if (CVA6Cfg.RVH) begin + gpte_d = '0; + gpaddr_n = '0; + end + + + // if we got an ITLB miss + if (((enable_translation_i | enable_g_translation_i) || (en_ld_st_translation_i || en_ld_st_g_translation_i) || !CVA6Cfg.RVH) && shared_tlb_access_i && ~shared_tlb_hit_i) begin + if (((enable_translation_i && enable_g_translation_i) || (en_ld_st_translation_i && en_ld_st_g_translation_i)) && CVA6Cfg.RVH) begin + ptw_stage_d = G_INTERMED_STAGE; + pptr = { + vsatp_ppn_i, + shared_tlb_vaddr_i[CVA6Cfg.SV-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + gptw_pptr_n = pptr; + ptw_pptr_n = { + hgatp_ppn_i[CVA6Cfg.PPNW-1:2], + pptr[CVA6Cfg.SV+HYP_EXT*2-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + end else if ((((enable_translation_i | enable_g_translation_i) && !enable_translation_i) || ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !en_ld_st_translation_i)) && CVA6Cfg.RVH) begin + ptw_stage_d = G_FINAL_STAGE; + gpaddr_n = shared_tlb_vaddr_i[CVA6Cfg.SV+HYP_EXT*2-1:0]; + ptw_pptr_n = { + hgatp_ppn_i[CVA6Cfg.PPNW-1:2], + shared_tlb_vaddr_i[CVA6Cfg.SV+HYP_EXT*2-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + end else begin + ptw_stage_d = S_STAGE; + if ((v_i || ld_st_v_i) && CVA6Cfg.RVH) + ptw_pptr_n = { + vsatp_ppn_i, + shared_tlb_vaddr_i[CVA6Cfg.SV-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + else + ptw_pptr_n = { + satp_ppn_i, + shared_tlb_vaddr_i[CVA6Cfg.SV-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + end + + is_instr_ptw_n = itlb_req_i; + vaddr_n = shared_tlb_vaddr_i; + state_d = WAIT_GRANT; + shared_tlb_miss_o = 1'b1; + + if (itlb_req_i) begin + tlb_update_asid_n = v_i ? vs_asid_i : asid_i; + if (CVA6Cfg.RVH) tlb_update_vmid_n = vmid_i; + end else begin + tlb_update_asid_n = ld_st_v_i ? vs_asid_i : asid_i; + if (CVA6Cfg.RVH) tlb_update_vmid_n = vmid_i; + end + end + end + + WAIT_GRANT: begin + // send a request out + req_port_o.data_req = 1'b1; + // wait for the WAIT_GRANT + if (req_port_i.data_gnt) begin + // send the tag valid signal one cycle later + tag_valid_n = 1'b1; + state_d = PTE_LOOKUP; + end + end + + PTE_LOOKUP: begin + // we wait for the valid signal + if (data_rvalid_q) begin + + // check if the global mapping bit is set + if (pte.g && (ptw_stage_q == S_STAGE || !CVA6Cfg.RVH)) global_mapping_n = 1'b1; + + // ------------- + // Invalid PTE + // ------------- + // If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if pte.reserved !=0 in sv39 and sv39x4, stop and raise a page-fault exception. + if (!pte.v || (!pte.r && pte.w) || (|pte.reserved && CVA6Cfg.XLEN == 64)) + state_d = PROPAGATE_ERROR; + // ----------- + // Valid PTE + // ----------- + else begin + state_d = LATENCY; + // it is a valid PTE + // if pte.r = 1 or pte.x = 1 it is a valid PTE + if (pte.r || pte.x) begin + if (CVA6Cfg.RVH) begin + case (ptw_stage_q) + S_STAGE: begin + if ((is_instr_ptw_q && enable_g_translation_i) || (!is_instr_ptw_q && en_ld_st_g_translation_i)) begin + state_d = WAIT_GRANT; + ptw_stage_d = G_FINAL_STAGE; + if (CVA6Cfg.RVH) gpte_d = pte; + ptw_lvl_n[HYP_EXT] = ptw_lvl_q[0]; + gpaddr_n = gpaddr[ptw_lvl_q[0]]; + ptw_pptr_n = { + hgatp_ppn_i[CVA6Cfg.PPNW-1:2], + gpaddr[ptw_lvl_q[0]][CVA6Cfg.SV+HYP_EXT*2-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + ptw_lvl_n[0] = '0; + end + end + G_INTERMED_STAGE: begin + state_d = WAIT_GRANT; + ptw_stage_d = S_STAGE; + ptw_lvl_n[0] = ptw_lvl_q[HYP_EXT]; + pptr = {pte.ppn[CVA6Cfg.GPPNW-1:0], gptw_pptr_q[11:0]}; + if (ptw_lvl_q[0] == 1) pptr[20:0] = gptw_pptr_q[20:0]; + if (ptw_lvl_q[0] == 0) pptr[29:0] = gptw_pptr_q[29:0]; + ptw_pptr_n = pptr; + end + default: ; + endcase + end + // Valid translation found (either 1G, 2M or 4K entry) + if (is_instr_ptw_q) begin + // ------------ + // Update ITLB + // ------------ + // If page is not executable, we can directly raise an error. This + // doesn't put a useless entry into the TLB. The same idea applies + // to the access flag since we let the access flag be managed by SW. + if (!pte.x || !pte.a) begin + state_d = PROPAGATE_ERROR; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + end else if (CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !enable_g_translation_i) || !CVA6Cfg.RVH) + shared_tlb_update_o.valid = 1'b1; + + end else begin + // ------------ + // Update DTLB + // ------------ + // Check if the access flag has been set, otherwise throw a page-fault + // and let the software handle those bits. + // If page is not readable (there are no write-only pages) + // we can directly raise an error. This doesn't put a useless + // entry into the TLB. + if (pte.a && ((pte.r && !hlvx_inst_i) || (pte.x && (mxr_i || hlvx_inst_i || (ptw_stage_q == S_STAGE && vmxr_i && ld_st_v_i && CVA6Cfg.RVH))))) begin + if (CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !en_ld_st_g_translation_i) || !CVA6Cfg.RVH) + shared_tlb_update_o.valid = 1'b1; + end else begin + state_d = PROPAGATE_ERROR; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + end + // Request is a store: perform some additional checks + // If the request was a store and the page is not write-able, raise an error + // the same applies if the dirty flag is not set + if (lsu_is_store_i && (!pte.w || !pte.d)) begin + shared_tlb_update_o.valid = 1'b0; + state_d = PROPAGATE_ERROR; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + end + end + + //if there is a misaligned page, propagate error + if (|misaligned_page) begin + state_d = PROPAGATE_ERROR; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + shared_tlb_update_o.valid = 1'b0; + end + + // check if 63:41 are all zeros + if (CVA6Cfg.RVH) begin + if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW-1+HYP_EXT]) == 1'b0)) begin + state_d = PROPAGATE_ERROR; + ptw_stage_d = G_FINAL_STAGE; + end + end + // this is a pointer to the next TLB level + end else begin + // pointer to next level of page table + + if (ptw_lvl_q[0] == CVA6Cfg.PtLevels - 1) begin + // Should already be the last level page table => Error + ptw_lvl_n[0] = ptw_lvl_q[0]; + state_d = PROPAGATE_ERROR; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + + + end else begin + ptw_lvl_n[0] = ptw_lvl_q[0] + 1'b1; + state_d = WAIT_GRANT; + + if (CVA6Cfg.RVH) begin + case (ptw_stage_q) + S_STAGE: begin + if (CVA6Cfg.RVH && ((is_instr_ptw_q && enable_g_translation_i) || (!is_instr_ptw_q && en_ld_st_g_translation_i))) begin + ptw_stage_d = G_INTERMED_STAGE; + if (CVA6Cfg.RVH) gpte_d = pte; + ptw_lvl_n[HYP_EXT] = ptw_lvl_q[0] + 1; + pptr = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)}; + gptw_pptr_n = pptr; + ptw_pptr_n = { + hgatp_ppn_i[CVA6Cfg.PPNW-1:2], + pptr[CVA6Cfg.SV+HYP_EXT*2-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + (CVA6Cfg.PtLevels)'(0) + }; + ptw_lvl_n[0] = '0; + end else begin + ptw_pptr_n = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)}; + end + end + G_INTERMED_STAGE: begin + ptw_pptr_n = { + pte.ppn, vaddr_lvl[HYP_EXT][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0) + }; + end + G_FINAL_STAGE: begin + ptw_pptr_n = { + pte.ppn, vaddr_lvl[HYP_EXT*2][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0) + }; + end + endcase + end else ptw_pptr_n = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)}; + + if (CVA6Cfg.RVH && (pte.a || pte.d || pte.u)) begin + state_d = PROPAGATE_ERROR; + ptw_stage_d = ptw_stage_q; + end + + end + + // check if 63:41 are all zeros + if (CVA6Cfg.RVH) begin + if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW-1+HYP_EXT]) == 1'b0)) begin + state_d = PROPAGATE_ERROR; + ptw_stage_d = ptw_stage_q; + end + end + end + end + + // Check if this access was actually allowed from a PMP perspective + if (!allow_access) begin + shared_tlb_update_o.valid = 1'b0; + // we have to return the failed address in bad_addr + ptw_pptr_n = ptw_pptr_q; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; + state_d = PROPAGATE_ACCESS_ERROR; + end + end + // we've got a data WAIT_GRANT so tell the cache that the tag is valid + end + // Propagate error to MMU/LSU + PROPAGATE_ERROR: begin + state_d = LATENCY; + ptw_error_o = 1'b1; + if (CVA6Cfg.RVH) begin + ptw_error_at_g_st_o = (ptw_stage_q != S_STAGE) ? 1'b1 : 1'b0; + ptw_err_at_g_int_st_o = (ptw_stage_q == G_INTERMED_STAGE) ? 1'b1 : 1'b0; + end + end + PROPAGATE_ACCESS_ERROR: begin + state_d = LATENCY; + ptw_access_exception_o = 1'b1; + end + // wait for the rvalid before going back to IDLE + WAIT_RVALID: begin + if (data_rvalid_q) state_d = IDLE; + end + LATENCY: begin + state_d = IDLE; + end + default: begin + state_d = IDLE; + end + endcase + + // ------- + // Flush + // ------- + // should we have flushed before we got an rvalid, wait for it until going back to IDLE + if (flush_i) begin + // on a flush check whether we are + // 1. in the PTE Lookup check whether we still need to wait for an rvalid + // 2. waiting for a grant, if so: wait for it + // if not, go back to idle + if (((state_q inside {PTE_LOOKUP, WAIT_RVALID}) && !data_rvalid_q) || ((state_q == WAIT_GRANT) && req_port_i.data_gnt)) + state_d = WAIT_RVALID; + else state_d = LATENCY; + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + is_instr_ptw_q <= 1'b0; + ptw_lvl_q <= '0; + tag_valid_q <= 1'b0; + tlb_update_asid_q <= '0; + vaddr_q <= '0; + ptw_pptr_q <= '0; + global_mapping_q <= 1'b0; + data_rdata_q <= '0; + data_rvalid_q <= 1'b0; + if (CVA6Cfg.RVH) begin + gpaddr_q <= '0; + gptw_pptr_q <= '0; + ptw_stage_q <= S_STAGE; + gpte_q <= '0; + tlb_update_vmid_q <= '0; + end + end else begin + state_q <= state_d; + ptw_pptr_q <= ptw_pptr_n; + is_instr_ptw_q <= is_instr_ptw_n; + ptw_lvl_q <= ptw_lvl_n; + tag_valid_q <= tag_valid_n; + tlb_update_asid_q <= tlb_update_asid_n; + vaddr_q <= vaddr_n; + global_mapping_q <= global_mapping_n; + data_rdata_q <= req_port_i.data_rdata; + data_rvalid_q <= req_port_i.data_rvalid; + + if (CVA6Cfg.RVH) begin + gpaddr_q <= gpaddr_n; + gptw_pptr_q <= gptw_pptr_n; + ptw_stage_q <= ptw_stage_d; + gpte_q <= gpte_d; + tlb_update_vmid_q <= tlb_update_vmid_n; + end + end + end + +endmodule +/* verilator lint_on WIDTH */ diff --git a/flow/designs/src/cva6/core/cva6_mmu/cva6_shared_tlb.sv b/flow/designs/src/cva6/core/cva6_mmu/cva6_shared_tlb.sv new file mode 100644 index 0000000000..729d2194c5 --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_mmu/cva6_shared_tlb.sv @@ -0,0 +1,502 @@ +// Copyright (c) 2023 Thales. +// Copyright (c) 2024, PlanV Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Angela Gonzalez PlanV Technology +// Date: 26/02/2024 +// +// Description: N-way associative shared TLB, it allows to reduce the number +// of ITLB and DTLB entries. This module is an update of the +// shared TLB sv32 developed by Sebastien Jacq (Thales Research & Technology) +// to be used with sv32, sv39 and sv39x4. + +/* verilator lint_off WIDTH */ + +module cva6_shared_tlb #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type pte_cva6_t = logic, + parameter type tlb_update_cva6_t = logic, + parameter int SHARED_TLB_WAYS = 2, + parameter int unsigned HYP_EXT = 0 + +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // Flush normal translations signal + input logic flush_vvma_i, // Flush vs stage signal + input logic flush_gvma_i, // Flush g stage signal + input logic s_st_enbl_i, // s-stage enabled + input logic g_st_enbl_i, // g-stage enabled + input logic v_i, // virtualization mode + input logic s_ld_st_enbl_i, // s-stage enabled for load stores + input logic g_ld_st_enbl_i, // g-stage enabled for load stores + input logic ld_st_v_i, // virtualization mode for load stores + + input logic [CVA6Cfg.ASID_WIDTH-1:0] dtlb_asid_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] itlb_asid_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] lu_vmid_i, + + // from TLBs + // did we miss? + input logic itlb_access_i, + input logic itlb_hit_i, + input logic [CVA6Cfg.VLEN-1:0] itlb_vaddr_i, + + input logic dtlb_access_i, + input logic dtlb_hit_i, + input logic [CVA6Cfg.VLEN-1:0] dtlb_vaddr_i, + + input logic shared_tlb_miss_i, + + // to TLBs, update logic + output tlb_update_cva6_t itlb_update_o, + output tlb_update_cva6_t dtlb_update_o, + + // Performance counters + output logic itlb_miss_o, + output logic dtlb_miss_o, + + output logic shared_tlb_access_o, + output logic shared_tlb_hit_o, + output logic [CVA6Cfg.VLEN-1:0] shared_tlb_vaddr_o, + + output logic itlb_req_o, + + // Update shared TLB in case of miss + input tlb_update_cva6_t shared_tlb_update_i + +); + + function logic [SHARED_TLB_WAYS-1:0] shared_tlb_way_bin2oh(input logic [$clog2(SHARED_TLB_WAYS +)-1:0] in); + logic [SHARED_TLB_WAYS-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + typedef struct packed { + logic [CVA6Cfg.ASID_WIDTH-1:0] asid; + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; + logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn; + logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; + logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + } shared_tag_t; + + shared_tag_t shared_tag_wr; + shared_tag_t [SHARED_TLB_WAYS-1:0] shared_tag_rd; + + logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0] shared_tag_valid_q, shared_tag_valid_d; + + logic [ SHARED_TLB_WAYS-1:0] shared_tag_valid; + + logic [ SHARED_TLB_WAYS-1:0] tag_wr_en; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] tag_wr_addr; + logic [ $bits(shared_tag_t)-1:0] tag_wr_data; + + logic [ SHARED_TLB_WAYS-1:0] tag_rd_en; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] tag_rd_addr; + logic [ $bits(shared_tag_t)-1:0] tag_rd_data [SHARED_TLB_WAYS-1:0]; + + logic [ SHARED_TLB_WAYS-1:0] tag_req; + logic [ SHARED_TLB_WAYS-1:0] tag_we; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] tag_addr; + + logic [ SHARED_TLB_WAYS-1:0] pte_wr_en; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] pte_wr_addr; + logic [ CVA6Cfg.XLEN-1:0] pte_wr_data [ 1:0]; + + logic [ SHARED_TLB_WAYS-1:0] pte_rd_en; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] pte_rd_addr; + logic [ CVA6Cfg.XLEN-1:0] pte_rd_data [SHARED_TLB_WAYS-1:0] [HYP_EXT:0]; + + logic [ SHARED_TLB_WAYS-1:0] pte_req; + logic [ SHARED_TLB_WAYS-1:0] pte_we; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] pte_addr; + + logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn_d, vpn_q; + logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] vpn_match; + logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] page_match; + logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] level_match; + + logic [SHARED_TLB_WAYS-1:0] match_asid; + logic [SHARED_TLB_WAYS-1:0] match_vmid; + logic [SHARED_TLB_WAYS-1:0] match_stage; + + pte_cva6_t [SHARED_TLB_WAYS-1:0][HYP_EXT:0] pte; + + logic [CVA6Cfg.VLEN-1-12:0] itlb_vpn_q; + logic [CVA6Cfg.VLEN-1-12:0] dtlb_vpn_q; + + logic [CVA6Cfg.ASID_WIDTH-1:0] tlb_update_asid_q, tlb_update_asid_d; + logic [CVA6Cfg.VMID_WIDTH-1:0] tlb_update_vmid_q, tlb_update_vmid_d; + + logic shared_tlb_access_q, shared_tlb_access_d; + logic shared_tlb_hit_d; + logic [CVA6Cfg.VLEN-1:0] shared_tlb_vaddr_q, shared_tlb_vaddr_d; + + logic itlb_req_d, itlb_req_q; + logic dtlb_req_d, dtlb_req_q; + + int i_req_d, i_req_q; + + logic [1:0][2:0] v_st_enbl; + + // replacement strategy + logic [SHARED_TLB_WAYS-1:0] way_valid; + logic update_lfsr; // shift the LFSR + logic [$clog2(SHARED_TLB_WAYS)-1:0] inv_way; // first non-valid encountered + logic [$clog2(SHARED_TLB_WAYS)-1:0] rnd_way; // random index for replacement + logic [$clog2(SHARED_TLB_WAYS)-1:0] repl_way; // way to replace + logic [SHARED_TLB_WAYS-1:0] repl_way_oh_d; // way to replace (onehot) + logic all_ways_valid; // we need to switch repl strategy since all are valid + + assign shared_tlb_access_o = shared_tlb_access_q; + assign shared_tlb_hit_o = shared_tlb_hit_d; + assign shared_tlb_vaddr_o = shared_tlb_vaddr_q; + assign itlb_req_o = itlb_req_q; + assign v_st_enbl = {{v_i, g_st_enbl_i, s_st_enbl_i}, {ld_st_v_i, g_ld_st_enbl_i, s_ld_st_enbl_i}}; + + genvar i, x; + generate + for (i = 0; i < SHARED_TLB_WAYS; i++) begin : gen_match_tlb_ways + //identify page_match for all TLB Entries + + for (x = 0; x < CVA6Cfg.PtLevels; x++) begin : gen_match + assign page_match[i][x] = x==0 ? 1 :((HYP_EXT==0 || x==(CVA6Cfg.PtLevels-1)) ? // PAGE_MATCH CONTAINS THE MATCH INFORMATION FOR EACH TAG OF is_1G and is_2M in sv39x4. HIGHER LEVEL (Giga page), THEN THERE IS THE Mega page AND AT THE LOWER LEVEL IS ALWAYS 1 + &(shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x] | (~v_st_enbl[i_req_q][HYP_EXT:0])): + ((&v_st_enbl[i_req_q][HYP_EXT:0]) ? + ((shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0] && (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-2-x][HYP_EXT] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT])) + || (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-2-x][0] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0]))): + shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0] && v_st_enbl[i_req_q][0] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && v_st_enbl[i_req_q][HYP_EXT])); + + //identify if vpn matches at all PT levels for all TLB entries + assign vpn_match[i][x] = (HYP_EXT==1 && x==(CVA6Cfg.PtLevels-1) && ~v_st_enbl[i_req_q][0]) ? // + vpn_q[x] == shared_tag_rd[i].vpn[x] && vpn_q[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0] == shared_tag_rd[i].vpn[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0]: // + vpn_q[x] == shared_tag_rd[i].vpn[x]; + + //identify if there is a hit at each PT level for all TLB entries + assign level_match[i][x] = &vpn_match[i][CVA6Cfg.PtLevels-1:x] && page_match[i][x]; + + end + end + endgenerate + + genvar w; + generate + for (w = 0; w < CVA6Cfg.PtLevels; w++) begin + assign vpn_d[w] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // + itlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w)] : // + (((|v_st_enbl[0][HYP_EXT:0]) && dtlb_access_i && ~dtlb_hit_i) ? // + dtlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w)] : vpn_q[w]); + end + endgenerate + + if (CVA6Cfg.RVH) //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4 + assign vpn_d[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // + itlb_vaddr_i[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] : // + (((|v_st_enbl[0][HYP_EXT:0]) && dtlb_access_i && ~dtlb_hit_i) ? // + dtlb_vaddr_i[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] : vpn_q[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0]); + + /////////////////////////////////////////////////////// + // tag comparison, hit generation + /////////////////////////////////////////////////////// + always_comb begin : itlb_dtlb_miss + itlb_miss_o = 1'b0; + dtlb_miss_o = 1'b0; + + tag_rd_en = '0; + pte_rd_en = '0; + + itlb_req_d = 1'b0; + dtlb_req_d = 1'b0; + + tlb_update_asid_d = tlb_update_asid_q; + tlb_update_vmid_d = tlb_update_vmid_q; + + shared_tlb_access_d = '0; + shared_tlb_vaddr_d = shared_tlb_vaddr_q; + + tag_rd_addr = '0; + pte_rd_addr = '0; + i_req_d = i_req_q; + + // if we got an ITLB miss + if ((|v_st_enbl[1][HYP_EXT:0]) & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) begin + tag_rd_en = '1; + tag_rd_addr = itlb_vaddr_i[12+:$clog2(CVA6Cfg.SharedTlbDepth)]; + pte_rd_en = '1; + pte_rd_addr = itlb_vaddr_i[12+:$clog2(CVA6Cfg.SharedTlbDepth)]; + + itlb_miss_o = shared_tlb_miss_i; + itlb_req_d = 1'b1; + tlb_update_asid_d = itlb_asid_i; + tlb_update_vmid_d = lu_vmid_i; + + shared_tlb_access_d = '1; + shared_tlb_vaddr_d = itlb_vaddr_i; + i_req_d = 1; + + // we got an DTLB miss + end else if ((|v_st_enbl[0][HYP_EXT:0]) & dtlb_access_i & ~dtlb_hit_i) begin + tag_rd_en = '1; + tag_rd_addr = dtlb_vaddr_i[12+:$clog2(CVA6Cfg.SharedTlbDepth)]; + pte_rd_en = '1; + pte_rd_addr = dtlb_vaddr_i[12+:$clog2(CVA6Cfg.SharedTlbDepth)]; + + dtlb_miss_o = shared_tlb_miss_i; + dtlb_req_d = 1'b1; + tlb_update_asid_d = dtlb_asid_i; + tlb_update_vmid_d = lu_vmid_i; + + shared_tlb_access_d = '1; + shared_tlb_vaddr_d = dtlb_vaddr_i; + i_req_d = 0; + end + end //itlb_dtlb_miss + + always_comb begin : tag_comparison + shared_tlb_hit_d = 1'b0; + dtlb_update_o = '0; + itlb_update_o = '0; + match_asid = '{default: 0}; + match_vmid = CVA6Cfg.RVH ? '{default: 0} : '{default: 1}; + + + if (!CVA6Cfg.UseSharedTlb) begin + if (shared_tlb_update_i.valid) begin + shared_tlb_hit_d = 1'b1; + if (itlb_req_q) begin + itlb_update_o.valid = 1'b1; + itlb_update_o.vpn = shared_tlb_update_i.vpn; + itlb_update_o.is_page = shared_tlb_update_i.is_page; + itlb_update_o.content = shared_tlb_update_i.content; + itlb_update_o.g_content = shared_tlb_update_i.g_content; + itlb_update_o.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; + itlb_update_o.asid = shared_tlb_update_i.asid; + itlb_update_o.vmid = shared_tlb_update_i.vmid; + + end else if (dtlb_req_q) begin + dtlb_update_o.valid = 1'b1; + dtlb_update_o.vpn = shared_tlb_update_i.vpn; + dtlb_update_o.is_page = shared_tlb_update_i.is_page; + dtlb_update_o.content = shared_tlb_update_i.content; + dtlb_update_o.g_content = shared_tlb_update_i.g_content; + dtlb_update_o.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; + dtlb_update_o.asid = shared_tlb_update_i.asid; + dtlb_update_o.vmid = shared_tlb_update_i.vmid; + end + end + end else begin + + //number of ways + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + // first level match, this may be a giga page, check the ASID flags as well + // if the entry is associated to a global address, don't match the ASID (ASID is don't care) + match_asid[i] = (((tlb_update_asid_q == shared_tag_rd[i].asid) || pte[i][0].g) && v_st_enbl[i_req_q][0]) || !v_st_enbl[i_req_q][0]; + + if (CVA6Cfg.RVH) begin + match_vmid[i] = (tlb_update_vmid_q == shared_tag_rd[i].vmid && v_st_enbl[i_req_q][HYP_EXT]) || !v_st_enbl[i_req_q][HYP_EXT]; + end + + // check if translation is a: S-Stage and G-Stage, S-Stage only or G-Stage only translation and virtualization mode is on/off + match_stage[i] = shared_tag_rd[i].v_st_enbl == v_st_enbl[i_req_q][HYP_EXT*2:0]; + + if (shared_tag_valid[i] && match_asid && match_vmid && match_stage[i]) begin + if (|level_match[i]) begin + shared_tlb_hit_d = 1'b1; + if (itlb_req_q) begin + itlb_update_o.valid = 1'b1; + itlb_update_o.vpn = itlb_vpn_q; + itlb_update_o.is_page = shared_tag_rd[i].is_page; + itlb_update_o.content = pte[i][0]; + itlb_update_o.g_content = pte[i][HYP_EXT]; + itlb_update_o.v_st_enbl = shared_tag_rd[i].v_st_enbl; + itlb_update_o.asid = tlb_update_asid_q; + itlb_update_o.vmid = tlb_update_vmid_q; + end else if (dtlb_req_q) begin + dtlb_update_o.valid = 1'b1; + dtlb_update_o.vpn = dtlb_vpn_q; + dtlb_update_o.is_page = shared_tag_rd[i].is_page; + dtlb_update_o.content = pte[i][0]; + dtlb_update_o.g_content = pte[i][HYP_EXT]; + dtlb_update_o.v_st_enbl = shared_tag_rd[i].v_st_enbl; + dtlb_update_o.asid = tlb_update_asid_q; + dtlb_update_o.vmid = tlb_update_vmid_q; + end + end + end + end + end + end //tag_comparison + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + itlb_vpn_q <= '0; + dtlb_vpn_q <= '0; + tlb_update_asid_q <= '{default: 0}; + tlb_update_vmid_q <= '{default: 0}; + shared_tlb_access_q <= '0; + shared_tlb_vaddr_q <= '0; + shared_tag_valid_q <= '0; + vpn_q <= 0; + itlb_req_q <= '0; + dtlb_req_q <= '0; + i_req_q <= 0; + shared_tag_valid <= '0; + end else begin + itlb_vpn_q <= itlb_vaddr_i[CVA6Cfg.SV-1:12]; + dtlb_vpn_q <= dtlb_vaddr_i[CVA6Cfg.SV-1:12]; + tlb_update_asid_q <= tlb_update_asid_d; + shared_tlb_access_q <= shared_tlb_access_d; + shared_tlb_vaddr_q <= shared_tlb_vaddr_d; + shared_tag_valid_q <= shared_tag_valid_d; + vpn_q <= vpn_d; + itlb_req_q <= itlb_req_d; + dtlb_req_q <= dtlb_req_d; + i_req_q <= i_req_d; + shared_tag_valid <= shared_tag_valid_q[tag_rd_addr]; + + if (CVA6Cfg.RVH) tlb_update_vmid_q <= tlb_update_vmid_d; + end + end + + // ------------------ + // Update and Flush + // ------------------ + always_comb begin : update_flush + shared_tag_valid_d = shared_tag_valid_q; + tag_wr_en = '0; + pte_wr_en = '0; + + if (flush_i || flush_vvma_i || flush_gvma_i) begin + shared_tag_valid_d = '0; + end else if (shared_tlb_update_i.valid) begin + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + if (repl_way_oh_d[i]) begin + shared_tag_valid_d[shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]][i] = 1'b1; + tag_wr_en[i] = 1'b1; + pte_wr_en[i] = 1'b1; + end + end + end + end //update_flush + + assign shared_tag_wr.asid = shared_tlb_update_i.asid; + assign shared_tag_wr.vmid = shared_tlb_update_i.vmid; + assign shared_tag_wr.is_page = shared_tlb_update_i.is_page; + assign shared_tag_wr.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; + + genvar z; + generate + for (z = 0; z < CVA6Cfg.PtLevels; z++) begin : gen_shared_tag + assign shared_tag_wr.vpn[z] = shared_tlb_update_i.vpn[((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(z+1))-1:((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*z)]; + end + if (CVA6Cfg.RVH) begin : gen_shared_tag_hyp + //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4 + assign shared_tag_wr.vpn[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]; + end + endgenerate + + + assign tag_wr_addr = shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]; + assign tag_wr_data = shared_tag_wr; + + assign pte_wr_addr = shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]; + + assign pte_wr_data[0] = shared_tlb_update_i.content[CVA6Cfg.XLEN-1:0]; + assign pte_wr_data[1] = shared_tlb_update_i.g_content[CVA6Cfg.XLEN-1:0]; + + + + assign way_valid = shared_tag_valid_q[shared_tlb_update_i.vpn[$clog2( + CVA6Cfg.SharedTlbDepth + )-1:0]]; + assign repl_way = (all_ways_valid) ? rnd_way : inv_way; + assign update_lfsr = shared_tlb_update_i.valid & all_ways_valid; + assign repl_way_oh_d = (shared_tlb_update_i.valid) ? shared_tlb_way_bin2oh(repl_way) : '0; + + lzc #( + .WIDTH(SHARED_TLB_WAYS) + ) i_lzc ( + .in_i (~way_valid), + .cnt_o (inv_way), + .empty_o(all_ways_valid) + ); + + lfsr #( + .LfsrWidth(8), + .OutWidth ($clog2(SHARED_TLB_WAYS)) + ) i_lfsr ( + .clk_i (clk_i), + .rst_ni(rst_ni), + .en_i (update_lfsr), + .out_o (rnd_way) + ); + + /////////////////////////////////////////////////////// + // memory arrays and regs + /////////////////////////////////////////////////////// + + assign tag_req = tag_wr_en | tag_rd_en; + assign tag_we = tag_wr_en; + assign tag_addr = tag_wr_en ? tag_wr_addr : tag_rd_addr; + + assign pte_req = pte_wr_en | pte_rd_en; + assign pte_we = pte_wr_en; + assign pte_addr = pte_wr_en ? pte_wr_addr : pte_rd_addr; + + for (genvar i = 0; i < SHARED_TLB_WAYS; i++) begin : gen_sram + if (CVA6Cfg.UseSharedTlb) begin + // Tag RAM + sram #( + .DATA_WIDTH($bits(shared_tag_t)), + .NUM_WORDS (CVA6Cfg.SharedTlbDepth) + ) tag_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (tag_req[i]), + .we_i (tag_we[i]), + .addr_i (tag_addr), + .wuser_i('0), + .wdata_i(tag_wr_data), + .be_i ('1), + .ruser_o(), + .rdata_o(tag_rd_data[i]) + ); + + assign shared_tag_rd[i] = shared_tag_t'(tag_rd_data[i]); + + for (genvar a = 0; a < HYP_EXT + 1; a++) begin : g_content_sram + // PTE RAM + sram #( + .DATA_WIDTH(CVA6Cfg.XLEN), + .NUM_WORDS (CVA6Cfg.SharedTlbDepth) + ) pte_sram ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .req_i (pte_req[i]), + .we_i (pte_we[i]), + .addr_i (pte_addr), + .wuser_i('0), + .wdata_i(pte_wr_data[a]), + .be_i ('1), + .ruser_o(), + .rdata_o(pte_rd_data[i][a]) + ); + assign pte[i][a] = pte_cva6_t'(pte_rd_data[i][a]); + end + end + end +endmodule + +/* verilator lint_on WIDTH */ diff --git a/flow/designs/src/cva6/core/cva6_mmu/cva6_tlb.sv b/flow/designs/src/cva6/core/cva6_mmu/cva6_tlb.sv new file mode 100644 index 0000000000..68083f3e22 --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_mmu/cva6_tlb.sv @@ -0,0 +1,439 @@ +// Copyright (c) 2018 ETH Zurich and University of Bologna. +// Copyright (c) 2021 Thales. +// Copyright (c) 2022 Bruno Sá and Zero-Day Labs. +// Copyright (c) 2024 PlanV Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Angela Gonzalez PlanV Technology +// Date: 26/02/2024 +// +// Description: Translation Lookaside Buffer, parameterizable to Sv32 or Sv39 , +// or sv39x4 fully set-associative +// This module is an merge of the Sv32 TLB developed by Sebastien +// Jacq (Thales Research & Technology), the Sv39 TLB developed +// by Florian Zaruba and David Schaffenrath and the Sv39x4 by Bruno Sá. + +module cva6_tlb + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type pte_cva6_t = logic, + parameter type tlb_update_cva6_t = logic, + parameter int unsigned TLB_ENTRIES = 4, + parameter int unsigned HYP_EXT = 0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // Flush normal translations signal + input logic flush_vvma_i, // Flush vs stage signal + input logic flush_gvma_i, // Flush g stage signal + input logic s_st_enbl_i, // s-stage enabled + input logic g_st_enbl_i, // g-stage enabled + input logic v_i, // virtualization mode + // Update TLB + input tlb_update_cva6_t update_i, + // Lookup signals + input logic lu_access_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] lu_asid_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] lu_vmid_i, + input logic [CVA6Cfg.VLEN-1:0] lu_vaddr_i, + output logic [CVA6Cfg.GPLEN-1:0] lu_gpaddr_o, + output pte_cva6_t lu_content_o, + output pte_cva6_t lu_g_content_o, + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed_i, + input logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i, + input logic [CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed_i, + output logic [CVA6Cfg.PtLevels-2:0] lu_is_page_o, + output logic lu_hit_o +); + localparam GPPN2 = (CVA6Cfg.XLEN == 32) ? CVA6Cfg.VLEN - 33 : 10; + // SV39 defines three levels of page tables + struct packed { + logic [CVA6Cfg.ASID_WIDTH-1:0] asid; + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; + logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn; + logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; + logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + logic valid; + } [TLB_ENTRIES-1:0] + tags_q, tags_n; + + struct packed { + pte_cva6_t pte; + pte_cva6_t gpte; + } [TLB_ENTRIES-1:0] + content_q, content_n; + + logic [TLB_ENTRIES-1:0][CVA6Cfg.PtLevels-1:0] vpn_match; + logic [TLB_ENTRIES-1:0][CVA6Cfg.PtLevels-1:0] level_match; + logic [TLB_ENTRIES-1:0][HYP_EXT:0][CVA6Cfg.PtLevels-1:0] vaddr_vpn_match; + logic [TLB_ENTRIES-1:0][HYP_EXT:0][CVA6Cfg.PtLevels-1:0] vaddr_level_match; + logic [TLB_ENTRIES-1:0] lu_hit; // to replacement logic + logic [TLB_ENTRIES-1:0] replace_en; // replace the following entry, set by replacement strategy + logic [TLB_ENTRIES-1:0] match_asid; + logic [TLB_ENTRIES-1:0] match_vmid; + logic [TLB_ENTRIES-1:0][CVA6Cfg.PtLevels-1:0] page_match; + logic [TLB_ENTRIES-1:0][HYP_EXT:0][CVA6Cfg.PtLevels-1:0] vpage_match; + logic [TLB_ENTRIES-1:0][CVA6Cfg.PtLevels-2:0] is_page_o; + logic [TLB_ENTRIES-1:0] match_stage; + pte_cva6_t g_content; + logic [TLB_ENTRIES-1:0][(CVA6Cfg.GPPNW-1):0] gppn; + logic [2:0] v_st_enbl; + + assign v_st_enbl = (CVA6Cfg.RVH) ? {v_i, g_st_enbl_i, s_st_enbl_i} : '1; + //------------- + // Translation + //------------- + + genvar i, x, z, w; + generate + for (i = 0; i < TLB_ENTRIES; i++) begin + for (x = 0; x < CVA6Cfg.PtLevels; x++) begin + //identify page_match for all TLB Entries + assign page_match[i][x] = x==0 ? 1 :((HYP_EXT==0 || x==(CVA6Cfg.PtLevels-1)) ? // PAGE_MATCH CONTAINS THE MATCH INFORMATION FOR EACH TAG OF is_1G and is_2M in sv39x4. HIGHER LEVEL (Giga page), THEN THERE IS THE Mega page AND AT THE LOWER LEVEL IS ALWAYS 1 + &(tags_q[i].is_page[CVA6Cfg.PtLevels-1-x] | (~v_st_enbl[HYP_EXT:0])): + ((&v_st_enbl[HYP_EXT:0]) ? + ((tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0] && (tags_q[i].is_page[CVA6Cfg.PtLevels-2-x][HYP_EXT] || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT])) + || (tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && (tags_q[i].is_page[CVA6Cfg.PtLevels-2-x][0] || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0]))): + tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0] && s_st_enbl_i || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && g_st_enbl_i)); + + //identify if vpn matches at all PT levels for all TLB entries + assign vpn_match[i][x] = (CVA6Cfg.RVH && x == (CVA6Cfg.PtLevels - 1) && ~s_st_enbl_i) ? // + lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x] && lu_vaddr_i[12+HYP_EXT*(CVA6Cfg.VpnLen-1): 12+HYP_EXT*(CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))] == tags_q[i].vpn[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0]: // + lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x]; + + //identify if there is a hit at each PT level for all TLB entries + assign level_match[i][x] = &vpn_match[i][CVA6Cfg.PtLevels-1:x] && page_match[i][x]; + + //identify vpage_match for all TLB Entries and vaddr_level match (if there is a hit at each PT level for all TLB entries on the vaddr) + for (z = 0; z < HYP_EXT + 1; z++) begin + assign vpage_match[i][z][x] = x == 0 ? 1 : tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][z]; + assign vaddr_level_match[i][z][x]= &vaddr_vpn_match[i][z][CVA6Cfg.PtLevels-1:x] && vpage_match[i][z][x]; + + end + //identify if virtual address vpn matches at all PT levels for all TLB entries + assign vaddr_vpn_match[i][0][x] = vaddr_to_be_flushed_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x]; + + end + + + + if (CVA6Cfg.RVH) begin + //identify if GPADDR matches the GPPN + assign vaddr_vpn_match[i][HYP_EXT][0] = (gpaddr_to_be_flushed_i[20:12] == gppn[i][8:0]); + assign vaddr_vpn_match[i][HYP_EXT][HYP_EXT] = (gpaddr_to_be_flushed_i[29:21] == gppn[i][17:9]); + assign vaddr_vpn_match[i][HYP_EXT][HYP_EXT*2] = (gpaddr_to_be_flushed_i[30+GPPN2:30] == gppn[i][18+GPPN2:18]); + + end + + for (w = 0; w < CVA6Cfg.PtLevels - 1; w++) begin + assign is_page_o[i][w] = page_match[i][CVA6Cfg.PtLevels - 1 - w]; //THIS REORGANIZES THE PAGES TO MATCH THE OUTPUT STRUCTURE (2M,1G) + end + end + endgenerate + + always_comb begin : translation + + // default assignment + lu_hit = '{default: 0}; + lu_hit_o = 1'b0; + lu_content_o = '{default: 0}; + lu_g_content_o = '{default: 0}; + lu_is_page_o = '{default: 0}; + match_asid = '{default: 0}; + match_vmid = CVA6Cfg.RVH ? '{default: 0} : '{default: 1}; + match_stage = '{default: 0}; + g_content = '{default: 0}; + lu_gpaddr_o = '{default: 0}; + + for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin + // first level match, this may be a giga page, check the ASID flags as well + // if the entry is associated to a global address, don't match the ASID (ASID is don't care) + match_asid[i] = ((lu_asid_i == tags_q[i].asid || content_q[i].pte.g) && s_st_enbl_i) || !s_st_enbl_i; + + if (CVA6Cfg.RVH) begin + match_vmid[i] = (lu_vmid_i == tags_q[i].vmid && g_st_enbl_i) || !g_st_enbl_i; + end + + // check if translation is a: S-Stage and G-Stage, S-Stage only or G-Stage only translation and virtualization mode is on/off + match_stage[i] = tags_q[i].v_st_enbl[HYP_EXT*2:0] == v_st_enbl[HYP_EXT*2:0]; + + if (tags_q[i].valid && match_asid[i] && match_vmid[i] && match_stage[i]) begin + + if (CVA6Cfg.RVH && vpn_match[i][HYP_EXT*2]) begin + if (s_st_enbl_i) begin + lu_gpaddr_o = {content_q[i].pte.ppn[(CVA6Cfg.GPPNW-1):0], lu_vaddr_i[11:0]}; + // Giga page + if (tags_q[i].is_page[0][0]) + lu_gpaddr_o[12+2*CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12] = lu_vaddr_i[12+2*CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12]; + // Mega page + if (tags_q[i].is_page[HYP_EXT][0]) + lu_gpaddr_o[12+CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12] = lu_vaddr_i[12+CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12]; + end else begin + lu_gpaddr_o =CVA6Cfg.GPLEN'(lu_vaddr_i[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0]); + end + end + + if (|level_match[i]) begin + lu_is_page_o = is_page_o[i]; + lu_content_o = content_q[i].pte; + lu_hit_o = 1'b1; + lu_hit[i] = 1'b1; + + if (CVA6Cfg.RVH) begin + // Compute G-Stage PPN based on the gpaddr + g_content = content_q[i].gpte; + if (tags_q[i].is_page[HYP_EXT][HYP_EXT]) g_content.ppn[8:0] = lu_gpaddr_o[20:12]; + if (tags_q[i].is_page[0][HYP_EXT]) g_content.ppn[17:0] = lu_gpaddr_o[29:12]; + // Output G-stage and S-stage content + lu_g_content_o = level_match[i][CVA6Cfg.PtLevels-1] ? content_q[i].gpte : g_content; + end + end + end + end + end + + logic [HYP_EXT:0]asid_to_be_flushed_is0; // indicates that the ASID provided by SFENCE.VMA (rs2)is 0, active high + logic [HYP_EXT:0] vaddr_to_be_flushed_is0; // indicates that the VADDR provided by SFENCE.VMA (rs1)is 0, active high + logic vmid_to_be_flushed_is0; // indicates that the VMID provided is 0, active high + logic gpaddr_to_be_flushed_is0; // indicates that the GPADDR provided is 0, active high + + assign asid_to_be_flushed_is0 = ~(|asid_to_be_flushed_i); + assign vaddr_to_be_flushed_is0 = ~(|vaddr_to_be_flushed_i); + assign vmid_to_be_flushed_is0 = ~(|vmid_to_be_flushed_i); + assign gpaddr_to_be_flushed_is0 = ~(|gpaddr_to_be_flushed_i); + + // ------------------ + // Update and Flush + // ------------------ + always_comb begin : update_flush + tags_n = tags_q; + content_n = content_q; + + for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin + + + if (CVA6Cfg.RVH) begin + + if (tags_q[i].v_st_enbl[0]) begin + gppn[i] = content_q[i].pte.ppn[(CVA6Cfg.GPPNW-1):0]; + if (tags_q[i].is_page[HYP_EXT][0]) + gppn[i][CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:0] = tags_q[i].vpn[0]; + if (tags_q[i].is_page[0][0]) + gppn[i][2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] = { + tags_q[i].vpn[HYP_EXT], tags_q[i].vpn[0] + }; + end else begin + gppn[i][CVA6Cfg.VpnLen-1:0] = CVA6Cfg.VpnLen'(tags_q[i].vpn); + end + end + + + if (flush_i) begin + if (!tags_q[i].v_st_enbl[HYP_EXT*2] || HYP_EXT == 0) begin + // invalidate logic + // flush everything if ASID is 0 and vaddr is 0 ("SFENCE.VMA x0 x0" case) + if (asid_to_be_flushed_is0 && vaddr_to_be_flushed_is0) tags_n[i].valid = 1'b0; + // flush vaddr in all addressing space ("SFENCE.VMA vaddr x0" case), it should happen only for leaf pages + else if (asid_to_be_flushed_is0 && (|vaddr_level_match[i][0] ) && (~vaddr_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + // the entry is flushed if it's not global and asid and vaddr both matches with the entry to be flushed ("SFENCE.VMA vaddr asid" case) + else if ((!content_q[i].pte.g) && (|vaddr_level_match[i][0]) && (asid_to_be_flushed_i == tags_q[i].asid ) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + // the entry is flushed if it's not global, and the asid matches and vaddr is 0. ("SFENCE.VMA 0 asid" case) + else if ((!content_q[i].pte.g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid ) && (!asid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + end + end else if (flush_vvma_i && CVA6Cfg.RVH) begin + if (tags_q[i].v_st_enbl[HYP_EXT*2] && tags_q[i].v_st_enbl[0]) begin + // invalidate logic + // flush everything if current VMID matches and ASID is 0 and vaddr is 0 ("SFENCE.VMA/HFENCE.VVMA x0 x0" case) + if (asid_to_be_flushed_is0 && vaddr_to_be_flushed_is0 && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) + tags_n[i].valid = 1'b0; + // flush vaddr in all addressing space if current VMID matches ("SFENCE.VMA/HFENCE.VVMA vaddr x0" case), it should happen only for leaf pages + else if (asid_to_be_flushed_is0 && (|vaddr_level_match[i][0]) && (~vaddr_to_be_flushed_is0) && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) + tags_n[i].valid = 1'b0; + // the entry is flushed if it's not global and asid and vaddr and current VMID matches with the entry to be flushed ("SFENCE.VMA/HFENCE.VVMA vaddr asid" case) + else if ((!content_q[i].pte.g) && (|vaddr_level_match[i][0]) && (asid_to_be_flushed_i == tags_q[i].asid && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + // the entry is flushed if it's not global, and the asid and the current VMID matches and vaddr is 0. ("SFENCE.VMA/HFENCE.VVMA 0 asid" case) + else if ((!content_q[i].pte.g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) && (!asid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + end + end else if (flush_gvma_i && CVA6Cfg.RVH) begin + if (tags_q[i].v_st_enbl[HYP_EXT]) begin + // invalidate logic + // flush everything if vmid is 0 and addr is 0 ("HFENCE.GVMA x0 x0" case) + if (vmid_to_be_flushed_is0 && gpaddr_to_be_flushed_is0) tags_n[i].valid = 1'b0; + // flush gpaddr in all addressing space ("HFENCE.GVMA gpaddr x0" case), it should happen only for leaf pages + else if (vmid_to_be_flushed_is0 && (|vaddr_level_match[i][HYP_EXT] ) && (~gpaddr_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + // the entry vmid and gpaddr both matches with the entry to be flushed ("HFENCE.GVMA gpaddr vmid" case) + else if ((|vaddr_level_match[i][HYP_EXT]) && (vmid_to_be_flushed_i == tags_q[i].vmid) && (~gpaddr_to_be_flushed_is0) && (~vmid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + // the entry is flushed if the vmid matches and gpaddr is 0. ("HFENCE.GVMA 0 vmid" case) + else if ((gpaddr_to_be_flushed_is0) && (vmid_to_be_flushed_i == tags_q[i].vmid) && (!vmid_to_be_flushed_is0)) + tags_n[i].valid = 1'b0; + end + // normal replacement + end else if (update_i.valid & replace_en[i] & !lu_hit_o) begin + //update tag + tags_n[i] = { + update_i.asid, + update_i.vmid, + ((CVA6Cfg.PtLevels + HYP_EXT) * (CVA6Cfg.VpnLen / CVA6Cfg.PtLevels))'(update_i.vpn), + update_i.is_page, + update_i.v_st_enbl, + 1'b1 + }; + // update content as well + content_n[i].pte = update_i.content; + if (CVA6Cfg.RVH) content_n[i].gpte = update_i.g_content; + end + end + end + + // ----------------------------------------------- + // PLRU - Pseudo Least Recently Used Replacement + // ----------------------------------------------- + logic [2*(TLB_ENTRIES-1)-1:0] plru_tree_q, plru_tree_n; + always_comb begin : plru_replacement + plru_tree_n = plru_tree_q; + // The PLRU-tree indexing: + // lvl0 0 + // / \ +// / \ +// lvl1 1 2 +// / \ / \ +// lvl2 3 4 5 6 +// / \ /\/\ /\ +// ... ... ... ... +// Just predefine which nodes will be set/cleared +// E.g. for a TLB with 8 entries, the for-loop is semantically +// equivalent to the following pseudo-code: +// unique case (1'b1) +// lu_hit[7]: plru_tree_n[0, 2, 6] = {1, 1, 1}; +// lu_hit[6]: plru_tree_n[0, 2, 6] = {1, 1, 0}; +// lu_hit[5]: plru_tree_n[0, 2, 5] = {1, 0, 1}; +// lu_hit[4]: plru_tree_n[0, 2, 5] = {1, 0, 0}; +// lu_hit[3]: plru_tree_n[0, 1, 4] = {0, 1, 1}; +// lu_hit[2]: plru_tree_n[0, 1, 4] = {0, 1, 0}; +// lu_hit[1]: plru_tree_n[0, 1, 3] = {0, 0, 1}; +// lu_hit[0]: plru_tree_n[0, 1, 3] = {0, 0, 0}; +// default: begin /* No hit */ end +// endcase +for ( + int unsigned i = 0; i < TLB_ENTRIES; i++ + ) begin + automatic int unsigned idx_base, shift, new_index; + // we got a hit so update the pointer as it was least recently used + if (lu_hit[i] & lu_access_i) begin + // Set the nodes to the values we would expect + for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin + idx_base = $unsigned((2 ** lvl) - 1); + // lvl0 <=> MSB, lvl1 <=> MSB-1, ... + shift = $clog2(TLB_ENTRIES) - lvl; + // to circumvent the 32 bit integer arithmetic assignment + new_index = ~((i >> (shift - 1)) & 32'b1); + plru_tree_n[idx_base+(i>>shift)] = new_index[0]; + end + end + end + // Decode tree to write enable signals + // Next for-loop basically creates the following logic for e.g. an 8 entry + // TLB (note: pseudo-code obviously): + // replace_en[7] = &plru_tree_q[ 6, 2, 0]; //plru_tree_q[0,2,6]=={1,1,1} + // replace_en[6] = &plru_tree_q[~6, 2, 0]; //plru_tree_q[0,2,6]=={1,1,0} + // replace_en[5] = &plru_tree_q[ 5,~2, 0]; //plru_tree_q[0,2,5]=={1,0,1} + // replace_en[4] = &plru_tree_q[~5,~2, 0]; //plru_tree_q[0,2,5]=={1,0,0} + // replace_en[3] = &plru_tree_q[ 4, 1,~0]; //plru_tree_q[0,1,4]=={0,1,1} + // replace_en[2] = &plru_tree_q[~4, 1,~0]; //plru_tree_q[0,1,4]=={0,1,0} + // replace_en[1] = &plru_tree_q[ 3,~1,~0]; //plru_tree_q[0,1,3]=={0,0,1} + // replace_en[0] = &plru_tree_q[~3,~1,~0]; //plru_tree_q[0,1,3]=={0,0,0} + // For each entry traverse the tree. If every tree-node matches, + // the corresponding bit of the entry's index, this is + // the next entry to replace. + for (int unsigned i = 0; i < TLB_ENTRIES; i += 1) begin + automatic logic en; + automatic int unsigned idx_base, shift, new_index; + en = 1'b1; + for (int unsigned lvl = 0; lvl < $clog2(TLB_ENTRIES); lvl++) begin + idx_base = $unsigned((2 ** lvl) - 1); + // lvl0 <=> MSB, lvl1 <=> MSB-1, ... + shift = $clog2(TLB_ENTRIES) - lvl; + + // en &= plru_tree_q[idx_base + (i>>shift)] == ((i >> (shift-1)) & 1'b1); + new_index = (i >> (shift - 1)) & 32'b1; + if (new_index[0]) begin + en &= plru_tree_q[idx_base+(i>>shift)]; + end else begin + en &= ~plru_tree_q[idx_base+(i>>shift)]; + end + end + replace_en[i] = en; + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + tags_q <= '{default: 0}; + content_q <= '{default: 0}; + plru_tree_q <= '{default: 0}; + end else begin + tags_q <= tags_n; + content_q <= content_n; + plru_tree_q <= plru_tree_n; + end + end + //-------------- + // Sanity checks + //-------------- + + //pragma translate_off + + initial begin : p_assertions + assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1)) + else begin + $error("TLB size must be a multiple of 2 and greater than 1"); + $stop(); + end + assert (CVA6Cfg.ASID_WIDTH >= 1) + else begin + $error("ASID width must be at least 1"); + $stop(); + end + end + + // Just for checking + function int countSetBits(logic [TLB_ENTRIES-1:0] vector); + automatic int count = 0; + foreach (vector[idx]) begin + count += vector[idx]; + end + return count; + endfunction + + assert property (@(posedge clk_i) (countSetBits(lu_hit) <= 1)) + else begin + $error("More then one hit in TLB!"); + $stop(); + end + assert property (@(posedge clk_i) (countSetBits(replace_en) <= 1)) + else begin + $error("More then one TLB entry selected for next replace!"); + $stop(); + end + + //pragma translate_on + +endmodule diff --git a/flow/designs/src/cva6/core/cva6_rvfi_probes.sv b/flow/designs/src/cva6/core/cva6_rvfi_probes.sv new file mode 100644 index 0000000000..34b865d8d9 --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_rvfi_probes.sv @@ -0,0 +1,133 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Yannick Casamatta - Thales +// Date: 09/01/2024 + + +module cva6_rvfi_probes + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type lsu_ctrl_t = logic, + parameter type rvfi_probes_instr_t = logic, + parameter type rvfi_probes_csr_t = logic, + parameter type rvfi_probes_t = logic + +) ( + + input logic flush_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_i, + + input logic [CVA6Cfg.NrIssuePorts-1 : 0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i, + input logic [ CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_i, + + input logic flush_unissued_instr_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, + input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_i, + + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_i, + + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_i, + input exception_t ex_commit_i, + input riscv::priv_lvl_t priv_lvl_i, + + input lsu_ctrl_t lsu_ctrl_i, + input logic [ CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [ CVA6Cfg.PLEN-1:0] mem_paddr_i, + input logic debug_mode_i, + input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i, + + input rvfi_probes_csr_t csr_i, + input logic [1:0] irq_i, + + output rvfi_probes_t rvfi_probes_o +); + + + rvfi_probes_csr_t csr; + rvfi_probes_instr_t instr; + + always_comb begin + csr = '0; + instr = '0; + + instr.flush = flush_i; + instr.issue_instr_ack = issue_instr_ack_i; + instr.fetch_entry_valid = fetch_entry_valid_i; + instr.instruction = instruction_i; + instr.is_compressed = is_compressed_i; + + instr.issue_pointer = issue_pointer_i; + + instr.flush_unissued_instr = flush_unissued_instr_i; + instr.decoded_instr_valid = decoded_instr_valid_i; + instr.decoded_instr_ack = decoded_instr_ack_i; + + instr.rs1 = rs1_i; + instr.rs2 = rs2_i; + + instr.ex_commit_cause = ex_commit_i.cause; + instr.ex_commit_valid = ex_commit_i.valid; + + instr.priv_lvl = priv_lvl_i; + + instr.lsu_ctrl_vaddr = lsu_ctrl_i.vaddr; + instr.lsu_ctrl_fu = lsu_ctrl_i.fu; + instr.lsu_ctrl_be = lsu_ctrl_i.be; + instr.lsu_ctrl_trans_id = lsu_ctrl_i.trans_id; + + instr.wbdata = wbdata_i; + instr.mem_paddr = mem_paddr_i; + instr.debug_mode = debug_mode_i; + + instr.commit_pointer = commit_pointer_i; + + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + instr.commit_instr_pc[i] = commit_instr_i[i].pc; + instr.commit_instr_op[i] = commit_instr_i[i].op; + instr.commit_instr_rs1[i] = commit_instr_i[i].rs1; + instr.commit_instr_rs2[i] = commit_instr_i[i].rs2; + instr.commit_instr_rd[i] = commit_instr_i[i].rd; + instr.commit_instr_result[i] = commit_instr_i[i].result; + instr.commit_instr_valid[i] = commit_instr_i[i].valid; + end + + instr.commit_drop = commit_drop_i; + instr.commit_ack = commit_ack_i; + instr.wdata = wdata_i; + + csr = csr_i; + csr.mip_q = csr_i.mip_q | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); + + end + + + always_comb begin + rvfi_probes_o = '0; + + if ($bits(rvfi_probes_o.instr) == $bits(instr)) begin + rvfi_probes_o.instr = instr; + end + + if ($bits(rvfi_probes_o.csr) == $bits(csr)) begin + rvfi_probes_o.csr = csr; + end + + end + + +endmodule + diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/common_cells/registers.svh b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/common_cells/registers.svh new file mode 100644 index 0000000000..c1975edcb3 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/common_cells/registers.svh @@ -0,0 +1,224 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Common register defines for RTL designs +`ifndef COMMON_CELLS_REGISTERS_SVH_ +`define COMMON_CELLS_REGISTERS_SVH_ + +// Abridged Summary of available FF macros: +// `FF: asynchronous active-low reset (implicit clock and reset) +// `FFAR: asynchronous active-high reset +// `FFARN: asynchronous active-low reset +// `FFSR: synchronous active-high reset +// `FFSRN: synchronous active-low reset +// `FFNR: without reset +// `FFL: load-enable and asynchronous active-low reset (implicit clock and reset) +// `FFLAR: load-enable and asynchronous active-high reset +// `FFLARN: load-enable and asynchronous active-low reset +// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear +// `FFLSR: load-enable and synchronous active-high reset +// `FFLSRN: load-enable and synchronous active-low reset +// `FFLNR: load-enable without reset + + +// Flip-Flop with asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FF(__q, __d, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFAR(__q, __d, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFSR(__q, __d, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : (__d); \ + end + +// Flip-Flop with synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFSRN(__q, __d, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : (__d); \ + end + +// Always-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __clk: clock input +`define FFNR(__q, __d, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__d); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FFL(__q, __d, __load, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFLAR(__q, __d, __load, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARN(__q, __d, __load, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFLSR(__q, __d, __load, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFLSRN(__q, __d, __load, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset and synchronous clear +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clear: assign reset value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__clear`" *``/ \ + `endif \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__clear) ? (__reset_value) : (__load) ? (__d) : (__q); \ + end \ + end + +// Load-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clk: clock input +`define FFLNR(__q, __d, __load, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__load) ? (__d) : (__q); \ + end + +`endif diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_cast_multi.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_cast_multi.sv new file mode 100644 index 0000000000..e166d0bf16 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_cast_multi.sv @@ -0,0 +1,794 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_cast_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, + // FPU configuration + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig), + fpnew_pkg::max_int_width(IntFmtConfig)), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [WIDTH-1:0] operands_i, // 1 operand + input logic [NUM_FORMATS-1:0] is_boxed_i, // 1 operand + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------- + // Constants + // ---------- + localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS; + localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig); + + localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig); + + localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits; + localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits; + localparam int unsigned SUPER_BIAS = 2**(SUPER_EXP_BITS - 1) - 1; + + // The internal mantissa includes normal bit or an entire integer + localparam int unsigned INT_MAN_WIDTH = fpnew_pkg::maximum(SUPER_MAN_BITS + 1, MAX_INT_WIDTH); + // If needed, there will be a LZC for renormalization + localparam int unsigned LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH); + // The internal exponent must be able to represent the smallest denormal input value as signed + // or the number of bits in an integer + localparam int unsigned INT_EXP_WIDTH = fpnew_pkg::maximum($clog2(MAX_INT_WIDTH), + fpnew_pkg::maximum(SUPER_EXP_BITS, $clog2(SUPER_BIAS + SUPER_MAN_BITS))) + 1; + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [WIDTH-1:0] operands_q; + logic [NUM_FORMATS-1:0] is_boxed_q; + logic op_mod_q; + fpnew_pkg::fp_format_e src_fmt_q; + fpnew_pkg::fp_format_e dst_fmt_q; + fpnew_pkg::int_format_e int_fmt_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][NUM_FORMATS-1:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; + fpnew_pkg::int_format_e [0:NUM_INP_REGS] inp_pipe_int_fmt_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_src_fmt_q[0] = src_fmt_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; + assign inp_pipe_int_fmt_q[0] = int_fmt_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_int_fmt_q[i+1], inp_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0)) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign is_boxed_q = inp_pipe_is_boxed_q[NUM_INP_REGS]; + assign op_mod_q = inp_pipe_op_mod_q[NUM_INP_REGS]; + assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; + assign int_fmt_q = inp_pipe_int_fmt_q[NUM_INP_REGS]; + + // ----------------- + // Input processing + // ----------------- + logic src_is_int, dst_is_int; // if 0, it's a float + + assign src_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::I2F); + assign dst_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::F2I); + + logic [INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit + + logic [NUM_FORMATS-1:0] fmt_sign; + logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_exponent; + logic [NUM_FORMATS-1:0][INT_MAN_WIDTH-1:0] fmt_mantissa; + logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_shift_compensation; // for LZC + + fpnew_pkg::fp_info_t [NUM_FORMATS-1:0] info; + + logic [NUM_INT_FORMATS-1:0][INT_MAN_WIDTH-1:0] ifmt_input_val; + logic int_sign; + logic [INT_MAN_WIDTH-1:0] int_value, int_mantissa; + + // FP Input initialization + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + // Classify input + fpnew_classifier #( + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .NumOperands ( 1 ) + ) i_fpnew_classifier ( + .operands_i ( operands_q[FP_WIDTH-1:0] ), + .is_boxed_i ( is_boxed_q[fmt] ), + .info_o ( info[fmt] ) + ); + + assign fmt_sign[fmt] = operands_q[FP_WIDTH-1]; + assign fmt_exponent[fmt] = signed'({1'b0, operands_q[MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[fmt] = {info[fmt].is_normal, operands_q[MAN_BITS-1:0]}; // zero pad + // Compensation for the difference in mantissa widths used for leading-zero count + assign fmt_shift_compensation[fmt] = signed'(INT_MAN_WIDTH - 1 - MAN_BITS); + end else begin : inactive_format + assign info[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled + assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_shift_compensation[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + // Sign-extend INT input + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_sign_extend_int + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format // only active formats + always_comb begin : sign_ext_input + // sign-extend value only if it's signed + ifmt_input_val[ifmt] = '{default: operands_q[INT_WIDTH-1] & ~op_mod_q}; + ifmt_input_val[ifmt][INT_WIDTH-1:0] = operands_q[INT_WIDTH-1:0]; + end + end else begin : inactive_format + assign ifmt_input_val[ifmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + // Construct input mantissa from integer + assign int_value = ifmt_input_val[int_fmt_q]; + assign int_sign = int_value[INT_MAN_WIDTH-1] & ~op_mod_q; // only signed ints are negative + assign int_mantissa = int_sign ? unsigned'(-int_value) : int_value; // get magnitude of negative + + // select mantissa with source format + assign encoded_mant = src_is_int ? int_mantissa : fmt_mantissa[src_fmt_q]; + + // -------------- + // Normalization + // -------------- + logic signed [INT_EXP_WIDTH-1:0] src_bias; // src format bias + logic signed [INT_EXP_WIDTH-1:0] src_exp; // src format exponent (biased) + logic signed [INT_EXP_WIDTH-1:0] src_subnormal; // src is subnormal + logic signed [INT_EXP_WIDTH-1:0] src_offset; // src offset within mantissa + + assign src_bias = signed'(fpnew_pkg::bias(src_fmt_q)); + assign src_exp = fmt_exponent[src_fmt_q]; + assign src_subnormal = signed'({1'b0, info[src_fmt_q].is_subnormal}); + assign src_offset = fmt_shift_compensation[src_fmt_q]; + + logic input_sign; // input sign + logic signed [INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent + logic [INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa + logic mant_is_zero; // for integer zeroes + + logic signed [INT_EXP_WIDTH-1:0] fp_input_exp; + logic signed [INT_EXP_WIDTH-1:0] int_input_exp; + + // Input mantissa needs to be normalized + logic [LZC_RESULT_WIDTH-1:0] renorm_shamt; // renormalization shift amount + logic [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; // signed form for calculations + + // Leading-zero counter is needed for renormalization + lzc #( + .WIDTH ( INT_MAN_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( encoded_mant ), + .cnt_o ( renorm_shamt ), + .empty_o ( mant_is_zero ) + ); + assign renorm_shamt_sgn = signed'({1'b0, renorm_shamt}); + + // Get the sign from the proper source + assign input_sign = src_is_int ? int_sign : fmt_sign[src_fmt_q]; + // Realign input mantissa, append zeroes if destination is wider + assign input_mant = encoded_mant << renorm_shamt; + // Unbias exponent and compensate for shift + assign fp_input_exp = signed'(src_exp + src_subnormal - src_bias - + renorm_shamt_sgn + src_offset); // compensate for shift + assign int_input_exp = signed'(INT_MAN_WIDTH - 1 - renorm_shamt_sgn); + + assign input_exp = src_is_int ? int_input_exp : fp_input_exp; + + logic signed [INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination + + // Rebias the exponent + assign destination_exp = input_exp + signed'(fpnew_pkg::bias(dst_fmt_q)); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic input_sign_q; + logic signed [INT_EXP_WIDTH-1:0] input_exp_q; + logic [INT_MAN_WIDTH-1:0] input_mant_q; + logic signed [INT_EXP_WIDTH-1:0] destination_exp_q; + logic src_is_int_q; + logic dst_is_int_q; + fpnew_pkg::fp_info_t info_q; + logic mant_is_zero_q; + logic op_mod_q2; + fpnew_pkg::roundmode_e rnd_mode_q; + fpnew_pkg::fp_format_e src_fmt_q2; + fpnew_pkg::fp_format_e dst_fmt_q2; + fpnew_pkg::int_format_e int_fmt_q2; + // Internal pipeline signals, index i holds signal after i register stages + + + logic [0:NUM_MID_REGS] mid_pipe_input_sign_q; + logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_input_exp_q; + logic [0:NUM_MID_REGS][INT_MAN_WIDTH-1:0] mid_pipe_input_mant_q; + logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_dest_exp_q; + logic [0:NUM_MID_REGS] mid_pipe_src_is_int_q; + logic [0:NUM_MID_REGS] mid_pipe_dst_is_int_q; + fpnew_pkg::fp_info_t [0:NUM_MID_REGS] mid_pipe_info_q; + logic [0:NUM_MID_REGS] mid_pipe_mant_zero_q; + logic [0:NUM_MID_REGS] mid_pipe_op_mod_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q; + fpnew_pkg::int_format_e [0:NUM_MID_REGS] mid_pipe_int_fmt_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_input_sign_q[0] = input_sign; + assign mid_pipe_input_exp_q[0] = input_exp; + assign mid_pipe_input_mant_q[0] = input_mant; + assign mid_pipe_dest_exp_q[0] = destination_exp; + assign mid_pipe_src_is_int_q[0] = src_is_int; + assign mid_pipe_dst_is_int_q[0] = dst_is_int; + assign mid_pipe_info_q[0] = info[src_fmt_q]; + assign mid_pipe_mant_zero_q[0] = mant_is_zero; + assign mid_pipe_op_mod_q[0] = op_mod_q; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_src_fmt_q[0] = src_fmt_q; + assign mid_pipe_dst_fmt_q[0] = dst_fmt_q; + assign mid_pipe_int_fmt_q[0] = int_fmt_q; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = mid_pipe_ready[i] & mid_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_input_sign_q[i+1], mid_pipe_input_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_input_exp_q[i+1], mid_pipe_input_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_input_mant_q[i+1], mid_pipe_input_mant_q[i], reg_ena, '0) + `FFL(mid_pipe_dest_exp_q[i+1], mid_pipe_dest_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_src_is_int_q[i+1], mid_pipe_src_is_int_q[i], reg_ena, '0) + `FFL(mid_pipe_dst_is_int_q[i+1], mid_pipe_dst_is_int_q[i], reg_ena, '0) + `FFL(mid_pipe_info_q[i+1], mid_pipe_info_q[i], reg_ena, '0) + `FFL(mid_pipe_mant_zero_q[i+1], mid_pipe_mant_zero_q[i], reg_ena, '0) + `FFL(mid_pipe_op_mod_q[i+1], mid_pipe_op_mod_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_src_fmt_q[i+1], mid_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_int_fmt_q[i+1], mid_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0)) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign input_sign_q = mid_pipe_input_sign_q[NUM_MID_REGS]; + assign input_exp_q = mid_pipe_input_exp_q[NUM_MID_REGS]; + assign input_mant_q = mid_pipe_input_mant_q[NUM_MID_REGS]; + assign destination_exp_q = mid_pipe_dest_exp_q[NUM_MID_REGS]; + assign src_is_int_q = mid_pipe_src_is_int_q[NUM_MID_REGS]; + assign dst_is_int_q = mid_pipe_dst_is_int_q[NUM_MID_REGS]; + assign info_q = mid_pipe_info_q[NUM_MID_REGS]; + assign mant_is_zero_q = mid_pipe_mant_zero_q[NUM_MID_REGS]; + assign op_mod_q2 = mid_pipe_op_mod_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign src_fmt_q2 = mid_pipe_src_fmt_q[NUM_MID_REGS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS]; + assign int_fmt_q2 = mid_pipe_int_fmt_q[NUM_MID_REGS]; + + // -------- + // Casting + // -------- + logic [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments + + logic [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift + logic [2*INT_MAN_WIDTH:0] destination_mant; // mantissa from shifter, with rnd bit + logic [SUPER_MAN_BITS-1:0] final_mant; // mantissa after adjustments + logic [MAX_INT_WIDTH-1:0] final_int; // integer shifted in position + + logic [$clog2(INT_MAN_WIDTH+1)-1:0] denorm_shamt; // shift amount for denormalization + + logic [1:0] fp_round_sticky_bits, int_round_sticky_bits, round_sticky_bits; + logic of_before_round, uf_before_round; + + + // Perform adjustments to mantissa and exponent + always_comb begin : cast_value + // Default assignment + final_exp = unsigned'(destination_exp_q); // take exponent as is, only look at lower bits + preshift_mant = '0; // initialize mantissa container with zeroes + denorm_shamt = SUPER_MAN_BITS - fpnew_pkg::man_bits(dst_fmt_q2); // right of mantissa + of_before_round = 1'b0; + uf_before_round = 1'b0; + + // Place mantissa to the left of the shifter + preshift_mant = input_mant_q << (INT_MAN_WIDTH + 1); + + // Handle INT casts + if (dst_is_int_q) begin + // By default right shift mantissa to be an integer + denorm_shamt = unsigned'(MAX_INT_WIDTH - 1 - input_exp_q); + // overflow: when converting to unsigned the range is larger by one + if (input_exp_q >= signed'(fpnew_pkg::int_width(int_fmt_q2) - 1 + op_mod_q2)) begin + denorm_shamt = '0; // prevent shifting + of_before_round = 1'b1; + // underflow + end else if (input_exp_q < -1) begin + denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky + uf_before_round = 1'b1; + end + // Handle FP over-/underflows + end else begin + // Overflow or infinities (for proper rounding) + if ((destination_exp_q >= signed'(2**fpnew_pkg::exp_bits(dst_fmt_q2))-1) || + (~src_is_int_q && info_q.is_inf)) begin + final_exp = unsigned'(2**fpnew_pkg::exp_bits(dst_fmt_q2)-2); // largest normal value + preshift_mant = '1; // largest normal value and RS bits set + of_before_round = 1'b1; + // Denormalize underflowing values + end else if (destination_exp_q < 1 && + destination_exp_q >= -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin + final_exp = '0; // denormal result + denorm_shamt = unsigned'(denorm_shamt + 1 - destination_exp_q); // adjust right shifting + uf_before_round = 1'b1; + // Limit the shift to retain sticky bits + end else if (destination_exp_q < -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin + final_exp = '0; // denormal result + denorm_shamt = unsigned'(denorm_shamt + 2 + fpnew_pkg::man_bits(dst_fmt_q2)); // to sticky + uf_before_round = 1'b1; + end + end + end + + localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - SUPER_MAN_BITS - 1; // removed mantissa, 1. and R + localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R + + // Mantissa adjustment shift + assign destination_mant = preshift_mant >> denorm_shamt; + // Extract final mantissa and round bit, discard the normal bit (for FP) + assign {final_mant, fp_round_sticky_bits[1]} = + destination_mant[2*INT_MAN_WIDTH-1-:SUPER_MAN_BITS+1]; + assign {final_int, int_round_sticky_bits[1]} = destination_mant[2*INT_MAN_WIDTH-:MAX_INT_WIDTH+1]; + // Collapse sticky bits + assign fp_round_sticky_bits[0] = (| {destination_mant[NUM_FP_STICKY-1:0]}); + assign int_round_sticky_bits[0] = (| {destination_mant[NUM_INT_STICKY-1:0]}); + + // select RS bits for destination operation + assign round_sticky_bits = dst_is_int_q ? int_round_sticky_bits : fp_round_sticky_bits; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic [WIDTH-1:0] pre_round_abs; // absolute value of result before rnd + logic of_after_round; // overflow + logic uf_after_round; // underflow + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_pre_round_abs; // per format + logic [NUM_FORMATS-1:0] fmt_of_after_round; + logic [NUM_FORMATS-1:0] fmt_uf_after_round; + + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_pre_round_abs; // per format + logic [NUM_INT_FORMATS-1:0] ifmt_of_after_round; + + logic rounded_sign; + logic [WIDTH-1:0] rounded_abs; // absolute value of result after rounding + logic result_true_zero; + + logic [WIDTH-1:0] rounded_int_res; // after possible inversion + logic rounded_int_res_zero; // after rounding + + + // Pack exponent and mantissa into proper rounding form + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble + // Set up some constants + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : assemble_result + fmt_pre_round_abs[fmt] = {final_exp[EXP_BITS-1:0], final_mant[MAN_BITS-1:0]}; // 0-extend + end + end else begin : inactive_format + assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Sign-extend integer result + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_sign_ext + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : assemble_result + // sign-extend reusult + ifmt_pre_round_abs[ifmt] = '{default: final_int[INT_WIDTH-1]}; + ifmt_pre_round_abs[ifmt][INT_WIDTH-1:0] = final_int[INT_WIDTH-1:0]; + end + end else begin : inactive_format + assign ifmt_pre_round_abs[ifmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Select output with destination format and operation + assign pre_round_abs = dst_is_int_q ? ifmt_pre_round_abs[int_fmt_q2] : fmt_pre_round_abs[dst_fmt_q2]; + + fpnew_rounding #( + .AbsWidth ( WIDTH ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( input_sign_q ), // source format + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( 1'b0 ), // no operation happened + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_true_zero ) + ); + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result; + + // Detect overflows and inject sign + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : post_process + // detect of / uf + fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal + fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. + + // Assemble regular result, nan box short ones. Int zeroes need to be detected` + fmt_result[fmt] = '1; + fmt_result[fmt][FP_WIDTH-1:0] = src_is_int_q & mant_is_zero_q + ? '0 + : {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]}; + end + end else begin : inactive_format + assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Negative integer result needs to be brought into two's complement + assign rounded_int_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs; + assign rounded_int_res_zero = (rounded_int_res == '0); + + // Detect integer overflows after rounding (only positives) + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_overflow + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : detect_overflow + ifmt_of_after_round[ifmt] = 1'b0; + // Int result can overflow if we're at the max exponent + if (!rounded_sign && input_exp_q == signed'(INT_WIDTH - 2 + op_mod_q2)) begin + // Check whether the rounded MSB differs from unrounded MSB + ifmt_of_after_round[ifmt] = ~rounded_int_res[INT_WIDTH-2+op_mod_q2]; + end + end + end else begin : inactive_format + assign ifmt_of_after_round[ifmt] = fpnew_pkg::DONT_CARE; + end + end + + // Classification after rounding select by destination format + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = dst_is_int_q ? ifmt_of_after_round[int_fmt_q2] : fmt_of_after_round[dst_fmt_q2]; + + // ------------------------- + // FP Special case handling + // ------------------------- + logic [WIDTH-1:0] fp_special_result; + fpnew_pkg::status_t fp_special_status; + logic fp_result_is_special; + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result; + + // Special result construction + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : special_results + logic [FP_WIDTH-1:0] special_res; + special_res = info_q.is_zero + ? input_sign_q << FP_WIDTH-1 // signed zero + : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + + // Initialize special result with ones (NaN-box) + fmt_special_result[fmt] = '1; + fmt_special_result[fmt][FP_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Detect special case from source format, I2F casts don't produce a special result + assign fp_result_is_special = ~src_is_int_q & (info_q.is_zero | + info_q.is_nan | + ~info_q.is_boxed); + + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign fp_special_status = '{NV: info_q.is_signalling, default: 1'b0}; + + // Assemble result according to destination format + assign fp_special_result = fmt_special_result[dst_fmt_q2]; // destination format + + // -------------------------- + // INT Special case handling + // -------------------------- + logic [WIDTH-1:0] int_special_result; + fpnew_pkg::status_t int_special_status; + logic int_result_is_special; + + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_special_result; + + // Special result construction + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_special_results_int + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : special_results + automatic logic [INT_WIDTH-1:0] special_res; + + // Default is overflow to positive max, which is 2**INT_WIDTH-1 or 2**(INT_WIDTH-1)-1 + special_res[INT_WIDTH-2:0] = '1; // alone yields 2**(INT_WIDTH-1)-1 + special_res[INT_WIDTH-1] = op_mod_q2; // for unsigned casts yields 2**INT_WIDTH-1 + + // Negative special case (except for nans) tie to -max or 0 + if (input_sign_q && !info_q.is_nan) + special_res = ~special_res; + + // Initialize special result with sign-extension + ifmt_special_result[ifmt] = '{default: special_res[INT_WIDTH-1]}; + ifmt_special_result[ifmt][INT_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign ifmt_special_result[ifmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) + assign int_result_is_special = info_q.is_nan | info_q.is_inf | + of_before_round | of_after_round | ~info_q.is_boxed | + (input_sign_q & op_mod_q2 & ~rounded_int_res_zero); + + // All integer special cases are invalid + assign int_special_status = '{NV: 1'b1, default: 1'b0}; + + // Assemble result according to destination format + assign int_special_result = ifmt_special_result[int_fmt_q2]; // destination format + + // ----------------- + // Result selection + // ----------------- + fpnew_pkg::status_t int_regular_status, fp_regular_status; + + logic [WIDTH-1:0] fp_result, int_result; + fpnew_pkg::status_t fp_status, int_status; + + assign fp_regular_status.NV = src_is_int_q & (of_before_round | of_after_round); // overflow is invalid for I2F casts + assign fp_regular_status.DZ = 1'b0; // no divisions + assign fp_regular_status.OF = ~src_is_int_q & (~info_q.is_inf & (of_before_round | of_after_round)); // inf casts no OF + assign fp_regular_status.UF = uf_after_round & fp_regular_status.NX; + assign fp_regular_status.NX = src_is_int_q ? (| fp_round_sticky_bits) // overflow is invalid in i2f + : (| fp_round_sticky_bits) | (~info_q.is_inf & (of_before_round | of_after_round)); + assign int_regular_status = '{NX: (| int_round_sticky_bits), default: 1'b0}; + + assign fp_result = fp_result_is_special ? fp_special_result : fmt_result[dst_fmt_q2]; + assign fp_status = fp_result_is_special ? fp_special_status : fp_regular_status; + assign int_result = int_result_is_special ? int_special_result : rounded_int_res; + assign int_status = int_result_is_special ? int_special_status : int_regular_status; + + // Final results for output pipeline + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + logic extension_bit; + + // Select output depending on special case detection + assign result_d = dst_is_int_q ? int_result : fp_result; + assign status_d = dst_is_int_q ? int_status : fp_status; + + // MSB of int result decides extension, otherwise NaN box + assign extension_bit = dst_is_int_q ? int_result[WIDTH-1] : 1'b1; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + logic [0:NUM_OUT_REGS] out_pipe_ext_bit_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_ext_bit_q[0] = extension_bit; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_ext_bit_q[i+1], out_pipe_ext_bit_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = out_pipe_ext_bit_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_classifier.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_classifier.sv new file mode 100644 index 0000000000..a322946d73 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_classifier.sv @@ -0,0 +1,74 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_classifier #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumOperands = 1, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) +) ( + input logic [NumOperands-1:0][WIDTH-1:0] operands_i, + input logic [NumOperands-1:0] is_boxed_i, + output fpnew_pkg::fp_info_t [NumOperands-1:0] info_o +); + + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + + // Type definition + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // Iterate through all operands + for (genvar op = 0; op < int'(NumOperands); op++) begin : gen_num_values + + fp_t value; + logic is_boxed; + logic is_normal; + logic is_inf; + logic is_nan; + logic is_signalling; + logic is_quiet; + logic is_zero; + logic is_subnormal; + + // --------------- + // Classify Input + // --------------- + always_comb begin : classify_input + value = operands_i[op]; + is_boxed = is_boxed_i[op]; + is_normal = is_boxed && (value.exponent != '0) && (value.exponent != '1); + is_zero = is_boxed && (value.exponent == '0) && (value.mantissa == '0); + is_subnormal = is_boxed && (value.exponent == '0) && !is_zero; + is_inf = is_boxed && ((value.exponent == '1) && (value.mantissa == '0)); + is_nan = !is_boxed || ((value.exponent == '1) && (value.mantissa != '0)); + is_signalling = is_boxed && is_nan && (value.mantissa[MAN_BITS-1] == 1'b0); + is_quiet = is_nan && !is_signalling; + // Assign output for current input + info_o[op].is_normal = is_normal; + info_o[op].is_subnormal = is_subnormal; + info_o[op].is_zero = is_zero; + info_o[op].is_inf = is_inf; + info_o[op].is_nan = is_nan; + info_o[op].is_signalling = is_signalling; + info_o[op].is_quiet = is_quiet; + info_o[op].is_boxed = is_boxed; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv new file mode 100644 index 0000000000..0f7ea5d559 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_divsqrt_multi.sv @@ -0,0 +1,366 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_divsqrt_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + // FPU configuration + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::AFTER, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [1:0][WIDTH-1:0] operands_i, // 2 operands + input logic [NUM_FORMATS-1:0][1:0] is_boxed_i, // 2 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + output logic divsqrt_done_o, + input logic simd_synch_done_i, + output logic divsqrt_ready_o, + input logic simd_synch_rdy_i, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------- + // Constants + // ---------- + // Pipelines + localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 2) // Last to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 2) // First to get distributed regs + : 0); // no regs here otherwise + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [1:0][WIDTH-1:0] operands_q; + fpnew_pkg::roundmode_e rnd_mode_q; + fpnew_pkg::operation_e op_q; + fpnew_pkg::fp_format_e dst_fmt_q; + logic in_valid_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign op_q = inp_pipe_op_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; + assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS]; + + // ----------------- + // Input processing + // ----------------- + logic [1:0] divsqrt_fmt; + logic [1:0][63:0] divsqrt_operands; // those are fixed to 64bit + logic input_is_fp8; + + // Translate fpnew formats into divsqrt formats + always_comb begin : translate_fmt + unique case (dst_fmt_q) + fpnew_pkg::FP32: divsqrt_fmt = 2'b00; + fpnew_pkg::FP64: divsqrt_fmt = 2'b01; + fpnew_pkg::FP16: divsqrt_fmt = 2'b10; + fpnew_pkg::FP16ALT: divsqrt_fmt = 2'b11; + default: divsqrt_fmt = 2'b10; // maps also FP8 to FP16 + endcase + + // Only if FP8 is enabled + input_is_fp8 = FpFmtConfig[fpnew_pkg::FP8] & (dst_fmt_q == fpnew_pkg::FP8); + + // If FP8 is supported, map it to an FP16 value + divsqrt_operands[0] = input_is_fp8 ? operands_q[0] << 8 : operands_q[0]; + divsqrt_operands[1] = input_is_fp8 ? operands_q[1] << 8 : operands_q[1]; + end + + // ------------ + // Control FSM + // ------------ + + logic in_ready; // input handshake with upstream + logic div_valid, sqrt_valid; // input signalling with unit + logic unit_ready, unit_done, unit_done_q; // status signals from unit instance + logic op_starting; // high in the cycle a new operation starts + logic out_valid, out_ready; // output handshake with downstream + logic unit_busy; // valid data in flight + // FSM states + typedef enum logic [1:0] {IDLE, BUSY, HOLD} fsm_state_e; + fsm_state_e state_q, state_d; + + // Ready synch with other lanes + // Bring the FSM-generated ready outside the unit, to synchronize it with the other lanes + assign divsqrt_ready_o = in_ready; + // Upstream ready comes from sanitization FSM, and it is synched among all the lanes + assign inp_pipe_ready[NUM_INP_REGS] = simd_synch_rdy_i; + + // Valid synch with other lanes + // When one divsqrt unit completes an operation, keep its done high, waiting for the other lanes + // As soon as all the lanes are over, we can clear this FF and start with a new operation + `FFLARNC(unit_done_q, unit_done, unit_done, simd_synch_done_i, 1'b0, clk_i, rst_ni); + // Tell the other units that this unit has finished now or in the past + assign divsqrt_done_o = unit_done_q | unit_done; + + // Valids are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr. + assign div_valid = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i; + assign sqrt_valid = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i; + assign op_starting = div_valid | sqrt_valid; + + // FSM to safely apply and receive data from DIVSQRT unit + always_comb begin : flag_fsm + // Default assignments + in_ready = 1'b0; + out_valid = 1'b0; + unit_busy = 1'b0; + state_d = state_q; + + unique case (state_q) + // Waiting for work + IDLE: begin + in_ready = 1'b1; // we're ready + if (in_valid_q && unit_ready) begin // New work arrives + state_d = BUSY; // go into processing state + end + end + // Operation in progress + BUSY: begin + unit_busy = 1'b1; // data in flight + // If all the lanes are done with processing + if (simd_synch_done_i) begin + out_valid = 1'b1; // try to commit result downstream + // If downstream accepts our result + if (out_ready) begin + state_d = IDLE; // we anticipate going back to idling.. + if (in_valid_q && unit_ready) begin // ..unless new work comes in + in_ready = 1'b1; // we acknowledge the instruction + state_d = BUSY; // and stay busy with it + end + // Otherwise if downstream is not ready for the result + end else begin + state_d = HOLD; // wait for the pipeline to take the data + end + end + end + // Waiting with valid result for downstream + HOLD: begin + unit_busy = 1'b1; // data in flight + out_valid = 1'b1; // try to commit result downstream + // If the result is accepted by downstream + if (out_ready) begin + state_d = IDLE; // go back to idle.. + if (in_valid_q && unit_ready) begin // ..unless new work comes in + in_ready = 1'b1; // acknowledge the new transaction + state_d = BUSY; // will be busy with the next instruction + end + end + end + // fall into idle state otherwise + default: state_d = IDLE; + endcase + + // Flushing overrides the other actions + if (flush_i) begin + unit_busy = 1'b0; // data is invalidated + out_valid = 1'b0; // cancel any valid data + state_d = IDLE; // go to default state + end + end + + // FSM status register (asynch active low reset) + `FF(state_q, state_d, IDLE) + + // Hold additional information while the operation is in progress + logic result_is_fp8_q; + TagType result_tag_q; + logic result_mask_q; + AuxType result_aux_q; + + // Fill the registers everytime a valid operation arrives (load FF, active low asynch rst) + `FFL(result_is_fp8_q, input_is_fp8, op_starting, '0) + `FFL(result_tag_q, inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0) + `FFL(result_mask_q, inp_pipe_mask_q[NUM_INP_REGS],op_starting, '0) + `FFL(result_aux_q, inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0) + + // ----------------- + // DIVSQRT instance + // ----------------- + logic [63:0] unit_result; + logic [WIDTH-1:0] adjusted_result, held_result_q; + fpnew_pkg::status_t unit_status, held_status_q; + logic hold_en; + + div_sqrt_top_mvp i_divsqrt_lei ( + .Clk_CI ( clk_i ), + .Rst_RBI ( rst_ni ), + .Div_start_SI ( div_valid ), + .Sqrt_start_SI ( sqrt_valid ), + .Operand_a_DI ( divsqrt_operands[0] ), + .Operand_b_DI ( divsqrt_operands[1] ), + .RM_SI ( rnd_mode_q ), + .Precision_ctl_SI ( '0 ), + .Format_sel_SI ( divsqrt_fmt ), + .Kill_SI ( flush_i ), + .Result_DO ( unit_result ), + .Fflags_SO ( unit_status ), + .Ready_SO ( unit_ready ), + .Done_SO ( unit_done ) + ); + + // Adjust result width and fix FP8 + assign adjusted_result = result_is_fp8_q ? unit_result >> 8 : unit_result; + + // Hold the result when one lane has finished execution, except when all the lanes finish together + // and the result can be accepted downstream + assign hold_en = unit_done & (~simd_synch_done_i | ~out_ready); + // The Hold register (load, no reset) + `FFLNR(held_result_q, adjusted_result, hold_en, clk_i) + `FFLNR(held_status_q, unit_status, hold_en, clk_i) + + // -------------- + // Output Select + // -------------- + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + // Prioritize hold register data + assign result_d = unit_done_q ? held_result_q : adjusted_result; + assign status_d = unit_done_q ? held_status_q : unit_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = result_tag_q; + assign out_pipe_mask_q[0] = result_mask_q; + assign out_pipe_aux_q[0] = result_aux_q; + assign out_pipe_valid_q[0] = out_valid; + // Input stage: Propagate pipeline ready signal to inside pipe + assign out_ready = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q}); +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma.sv new file mode 100644 index 0000000000..c29e7b3e24 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma.sv @@ -0,0 +1,690 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_fma #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) // do not change +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [2:0][WIDTH-1:0] operands_i, // 3 operands + input logic [2:0] is_boxed_i, // 3 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------- + // Constants + // ---------- + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + localparam int unsigned BIAS = fpnew_pkg::bias(FpFormat); + // Precision bits 'p' include the implicit bit + localparam int unsigned PRECISION_BITS = MAN_BITS + 1; + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam int unsigned LOWER_SUM_WIDTH = 2 * PRECISION_BITS + 3; + localparam int unsigned LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + // Internal exponent width of FMA must accomodate all meaningful exponent values in order to avoid + // datapath leakage. This is either given by the exponent bits or the width of the LZC result. + // In most reasonable FP formats the internal exponent will be wider than the LZC result. + localparam int unsigned EXP_WIDTH = unsigned'(fpnew_pkg::maximum(EXP_BITS + 2, LZC_RESULT_WIDTH)); + // Shift amount width: maximum internal mantissa size is 3p+4 bits + localparam int unsigned SHIFT_AMOUNT_WIDTH = $clog2(3 * PRECISION_BITS + 5); + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][2:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][2:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + + // ----------------- + // Input processing + // ----------------- + fpnew_pkg::fp_info_t [2:0] info_q; + + // Classify input + fpnew_classifier #( + .FpFormat ( FpFormat ), + .NumOperands ( 3 ) + ) i_class_inputs ( + .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ), + .info_o ( info_q ) + ); + + fp_t operand_a, operand_b, operand_c; + fpnew_pkg::fp_info_t info_a, info_b, info_c; + + // Operation selection and operand adjustment + // | \c op_q | \c op_mod_q | Operation Adjustment + // |:--------:|:-----------:|--------------------- + // | FMADD | \c 0 | FMADD: none + // | FMADD | \c 1 | FMSUB: Invert sign of operand C + // | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A + // | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C + // | ADD | \c 0 | ADD: Set operand A to +1.0 + // | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C + // | MUL | \c 0 | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode + // | *others* | \c - | *invalid* + // \note \c op_mod_q always inverts the sign of the addend. + always_comb begin : op_select + + // Default assignments - packing-order-agnostic + operand_a = inp_pipe_operands_q[NUM_INP_REGS][0]; + operand_b = inp_pipe_operands_q[NUM_INP_REGS][1]; + operand_c = inp_pipe_operands_q[NUM_INP_REGS][2]; + info_a = info_q[0]; + info_b = info_q[1]; + info_c = info_q[2]; + + // op_mod_q inverts sign of operand C + operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::FMADD: ; // do nothing + fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product + fpnew_pkg::ADD: begin // Set multiplicand to +1 + operand_a = '{sign: 1'b0, exponent: BIAS, mantissa: '0}; + info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. + end + fpnew_pkg::MUL: begin // Set addend to +0 or -0, depending whether the rounding mode is RDN + if (inp_pipe_rnd_mode_q[NUM_INP_REGS] == fpnew_pkg::RDN) + operand_c = '{sign: 1'b0, exponent: '0, mantissa: '0}; + else + operand_c = '{sign: 1'b1, exponent: '0, mantissa: '0}; + info_c = '{is_zero: 1'b1, is_boxed: 1'b1, default: 1'b0}; //zero, boxed value. + end + default: begin // propagate don't cares + operand_a = '{default: fpnew_pkg::DONT_CARE}; + operand_b = '{default: fpnew_pkg::DONT_CARE}; + operand_c = '{default: fpnew_pkg::DONT_CARE}; + info_a = '{default: fpnew_pkg::DONT_CARE}; + info_b = '{default: fpnew_pkg::DONT_CARE}; + info_c = '{default: fpnew_pkg::DONT_CARE}; + end + endcase + end + + // --------------------- + // Input classification + // --------------------- + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + logic effective_subtraction; + logic tentative_sign; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf, info_c.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan, info_c.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling, info_c.is_signalling}); + // Effective subtraction in FMA occurs when product and addend signs differ + assign effective_subtraction = operand_a.sign ^ operand_b.sign ^ operand_c.sign; + // The tentative sign of the FMA shall be the sign of the product + assign tentative_sign = operand_a.sign ^ operand_b.sign; + + // ---------------------- + // Special case handling + // ---------------------- + fp_t special_result; + fpnew_pkg::status_t special_status; + logic result_is_special; + + always_comb begin : special_cases + // Default assignments + special_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; // canonical qNaN + special_status = '0; + result_is_special = 1'b0; + + // Handle potentially mixed nan & infinity input => important for the case where infinity and + // zero are multiplied and added to a qnan. + // RISC-V mandates raising the NV exception in these cases: + // (inf * 0) + c or (0 * inf) + c INVALID, no matter c (even quiet NaNs) + if ((info_a.is_inf && info_b.is_zero) || (info_a.is_zero && info_b.is_inf)) begin + result_is_special = 1'b1; // bypass FMA, output is the canonical qNaN + special_status.NV = 1'b1; // invalid operation + // NaN Inputs cause canonical quiet NaN at the output and maybe invalid OP + end else if (any_operand_nan) begin + result_is_special = 1'b1; // bypass FMA, output is the canonical qNaN + special_status.NV = signalling_nan; // raise the invalid operation flag if signalling + // Special cases involving infinity + end else if (any_operand_inf) begin + result_is_special = 1'b1; // bypass FMA + // Effective addition of opposite infinities (±inf - ±inf) is invalid! + if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) + special_status.NV = 1'b1; // invalid operation + // Handle cases where output will be inf because of inf product input + else if (info_a.is_inf || info_b.is_inf) begin + // Result is infinity with the sign of the product + special_result = '{sign: operand_a.sign ^ operand_b.sign, exponent: '1, mantissa: '0}; + // Handle cases where the addend is inf + end else if (info_c.is_inf) begin + // Result is inifinity with sign of the addend (= operand_c) + special_result = '{sign: operand_c.sign, exponent: '1, mantissa: '0}; + end + end + end + + // --------------------------- + // Initial exponent data path + // --------------------------- + logic signed [EXP_WIDTH-1:0] exponent_a, exponent_b, exponent_c; + logic signed [EXP_WIDTH-1:0] exponent_addend, exponent_product, exponent_difference; + logic signed [EXP_WIDTH-1:0] tentative_exponent; + + // Zero-extend exponents into signed container - implicit width extension + assign exponent_a = signed'({1'b0, operand_a.exponent}); + assign exponent_b = signed'({1'b0, operand_b.exponent}); + assign exponent_c = signed'({1'b0, operand_c.exponent}); + + // Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx) + // with Ex the encoded exponent and nx the implicit bit. Internal exponents stay biased. + assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm + // Biased product exponent is the sum of encoded exponents minus the bias. + assign exponent_product = (info_a.is_zero || info_b.is_zero) + ? 2 - signed'(BIAS) // in case the product is zero, set minimum exp. + : signed'(exponent_a + info_a.is_subnormal + + exponent_b + info_b.is_subnormal + - signed'(BIAS)); + // Exponent difference is the addend exponent minus the product exponent + assign exponent_difference = exponent_addend - exponent_product; + // The tentative exponent will be the larger of the product or addend exponent + assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product; + + // Shift amount for addend based on exponents (unsigned as only right shifts) + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt; + + always_comb begin : addend_shift_amount + // Product-anchored case, saturated shift (addend is only in the sticky bit) + if (exponent_difference <= signed'(-2 * PRECISION_BITS - 1)) + addend_shamt = 3 * PRECISION_BITS + 4; + // Addend and product will have mutual bits to add + else if (exponent_difference <= signed'(PRECISION_BITS + 2)) + addend_shamt = unsigned'(signed'(PRECISION_BITS) + 3 - exponent_difference); + // Addend-anchored case, saturated shift (product is only in the sticky bit) + else + addend_shamt = 0; + end + + // ------------------ + // Product data path + // ------------------ + logic [PRECISION_BITS-1:0] mantissa_a, mantissa_b, mantissa_c; + logic [2*PRECISION_BITS-1:0] product; // the p*p product is 2p bits wide + logic [3*PRECISION_BITS+3:0] product_shifted; // addends are 3p+4 bit wide (including G/R) + + // Add implicit bits to mantissae + assign mantissa_a = {info_a.is_normal, operand_a.mantissa}; + assign mantissa_b = {info_b.is_normal, operand_b.mantissa}; + assign mantissa_c = {info_c.is_normal, operand_c.mantissa}; + + // Mantissa multiplier (a*b) + assign product = mantissa_a * mantissa_b; + + // Product is placed into a 3p+4 bit wide vector, padded with 2 bits for round and sticky: + // | 000...000 | product | RS | + // <- p+2 -> <- 2p -> < 2> + assign product_shifted = product << 2; // constant shift + + // ----------------- + // Addend data path + // ----------------- + logic [3*PRECISION_BITS+3:0] addend_after_shift; // upper 3p+4 bits are needed to go on + logic [PRECISION_BITS-1:0] addend_sticky_bits; // up to p bit of shifted addend are sticky + logic sticky_before_add; // they are compressed into a single sticky bit + logic [3*PRECISION_BITS+3:0] addend_shifted; // addends are 3p+4 bit wide (including G/R) + logic inject_carry_in; // inject carry for subtractions if needed + + // In parallel, the addend is right-shifted according to the exponent difference. Up to p bits + // are shifted out and compressed into a sticky bit. + // BEFORE THE SHIFT: + // | mantissa_c | 000..000 | + // <- p -> <- 3p+4 -> + // AFTER THE SHIFT: + // | 000..........000 | mantissa_c | 000...............0GR | sticky bits | + // <- addend_shamt -> <- p -> <- 2p+4-addend_shamt -> <- up to p -> + assign {addend_after_shift, addend_sticky_bits} = + (mantissa_c << (3 * PRECISION_BITS + 4)) >> addend_shamt; + + assign sticky_before_add = (| addend_sticky_bits); + // assign addend_after_shift[0] = sticky_before_add; + + // In case of a subtraction, the addend is inverted + assign addend_shifted = (effective_subtraction) ? ~addend_after_shift : addend_after_shift; + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + + // ------ + // Adder + // ------ + logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry + logic sum_carry; // observe carry bit from sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic final_sign; + + //Mantissa adder (ab+c). In normal addition, it cannot overflow. + assign sum_raw = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + + // Complement negative sum (can only happen in subtraction -> overflows for positive results) + assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + + // In case of a mispredicted subtraction result, do a sign flip + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) + ? 1'b1 + : (effective_subtraction ? 1'b0 : tentative_sign); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic effective_subtraction_q; + logic signed [EXP_WIDTH-1:0] exponent_product_q; + logic signed [EXP_WIDTH-1:0] exponent_difference_q; + logic signed [EXP_WIDTH-1:0] tentative_exponent_q; + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q; + logic sticky_before_add_q; + logic [3*PRECISION_BITS+3:0] sum_q; + logic final_sign_q; + fpnew_pkg::roundmode_e rnd_mode_q; + logic result_is_special_q; + fp_t special_result_q; + fpnew_pkg::status_t special_status_q; + // Internal pipeline signals, index i holds signal after i register stages + logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; + logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; + logic [0:NUM_MID_REGS] mid_pipe_sticky_q; + logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; + logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_eff_sub_q[0] = effective_subtraction; + assign mid_pipe_exp_prod_q[0] = exponent_product; + assign mid_pipe_exp_diff_q[0] = exponent_difference; + assign mid_pipe_tent_exp_q[0] = tentative_exponent; + assign mid_pipe_add_shamt_q[0] = addend_shamt; + assign mid_pipe_sticky_q[0] = sticky_before_add; + assign mid_pipe_sum_q[0] = sum; + assign mid_pipe_final_sign_q[0] = final_sign; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_res_is_spec_q[0] = result_is_special; + assign mid_pipe_spec_res_q[0] = special_result; + assign mid_pipe_spec_stat_q[0] = special_status; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = mid_pipe_ready[i] & mid_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_eff_sub_q[i+1], mid_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_prod_q[i+1], mid_pipe_exp_prod_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_diff_q[i+1], mid_pipe_exp_diff_q[i], reg_ena, '0) + `FFL(mid_pipe_tent_exp_q[i+1], mid_pipe_tent_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0) + `FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0) + `FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0) + `FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_res_is_spec_q[i+1], mid_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_res_q[i+1], mid_pipe_spec_res_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_stat_q[i+1], mid_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + + // -------------- + // Normalization + // -------------- + logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched + logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes + logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count + logic lzc_zeroes; // in case only zeroes found + + logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount + logic signed [EXP_WIDTH-1:0] normalized_exponent; + + logic [3*PRECISION_BITS+4:0] sum_shifted; // result after first normalization shift + logic [PRECISION_BITS:0] final_mantissa; // final mantissa before rounding with round bit + logic [2*PRECISION_BITS+2:0] sum_sticky_bits; // remaining 2p+3 sticky bits after normalization + logic sticky_after_norm; // sticky bit after normalization + + logic signed [EXP_WIDTH-1:0] final_exponent; + + assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; + + // Leading zero counter for cancellations + lzc #( + .WIDTH ( LOWER_SUM_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( sum_lower ), + .cnt_o ( leading_zero_count ), + .empty_o ( lzc_zeroes ) + ); + + assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count}); + + // Normalization shift amount based on exponents and LZC (unsigned as only left shifts) + always_comb begin : norm_shift_amount + // Product-anchored case or cancellations require LZC + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + // Normal result (biased exponent > 0 and not a zero) + if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin + // Undo initial product shift, remove the counted zeroes + norm_shamt = PRECISION_BITS + 2 + leading_zero_count; + normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift + // Subnormal result + end else begin + // Cap the shift distance to align mantissa with minimum exponent + norm_shamt = unsigned'(signed'(PRECISION_BITS) + 2 + exponent_product_q); + normalized_exponent = 0; // subnormals encoded as 0 + end + // Addend-anchored case + end else begin + norm_shamt = addend_shamt_q; // Undo the initial shift + normalized_exponent = tentative_exponent_q; + end + end + + // Do the large normalization shift + assign sum_shifted = sum_q << norm_shamt; + + // The addend-anchored case needs a 1-bit normalization since the leading-one can be to the left + // or right of the (non-carry) MSB of the sum. + always_comb begin : small_norm + // Default assignment, discarding carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + + // The normalized sum has overflown, align right and fix exponent + if (sum_shifted[3*PRECISION_BITS+4]) begin // check the carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + // The normalized sum is normal, nothing to do + end else if (sum_shifted[3*PRECISION_BITS+3]) begin // check the sum MSB + // do nothing + // The normalized sum is still denormal, align left - unless the result is not already subnormal + end else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + // Otherwise we're denormal + end else begin + final_exponent = '0; + end + end + + // Update the sticky bit with the shifted-out bits + assign sticky_after_norm = (| {sum_sticky_bits}) | sticky_before_add_q; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic pre_round_sign; + logic [EXP_BITS-1:0] pre_round_exponent; + logic [MAN_BITS-1:0] pre_round_mantissa; + logic [EXP_BITS+MAN_BITS-1:0] pre_round_abs; // absolute value of result before rounding + logic [1:0] round_sticky_bits; + + logic of_before_round, of_after_round; // overflow + logic uf_before_round, uf_after_round; // underflow + logic result_zero; + + logic rounded_sign; + logic [EXP_BITS+MAN_BITS-1:0] rounded_abs; // absolute value of result after rounding + + // Classification before round. RISC-V mandates checking underflow AFTER rounding! + assign of_before_round = final_exponent >= 2**(EXP_BITS)-1; // infinity exponent is all ones + assign uf_before_round = final_exponent == 0; // exponent for subnormals capped to 0 + + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign pre_round_sign = final_sign_q; + assign pre_round_exponent = (of_before_round) ? 2**EXP_BITS-2 : unsigned'(final_exponent[EXP_BITS-1:0]); + assign pre_round_mantissa = (of_before_round) ? '1 : final_mantissa[MAN_BITS:1]; // bit 0 is R bit + assign pre_round_abs = {pre_round_exponent, pre_round_mantissa}; + + // In case of overflow, the round and sticky bits are set for proper rounding + assign round_sticky_bits = (of_before_round) ? 2'b11 : {final_mantissa[0], sticky_after_norm}; + + // Perform the rounding + fpnew_rounding #( + .AbsWidth ( EXP_BITS + MAN_BITS ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( pre_round_sign ), + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( effective_subtraction_q ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) + ); + + // Classification after rounding + assign uf_after_round = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // exponent = 0 + assign of_after_round = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // exponent all ones + + // ----------------- + // Result selection + // ----------------- + logic [WIDTH-1:0] regular_result; + fpnew_pkg::status_t regular_status; + + // Assemble regular result + assign regular_result = {rounded_sign, rounded_abs}; + assign regular_status.NV = 1'b0; // only valid cases are handled in regular path + assign regular_status.DZ = 1'b0; // no divisions + assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF + assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + + // Final results for output pipeline + fp_t result_d; + fpnew_pkg::status_t status_d; + + // Select output depending on special case detection + assign result_d = result_is_special_q ? special_result_q : regular_result; + assign status_d = result_is_special_q ? special_status_q : regular_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + fp_t [0:NUM_OUT_REGS] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma_multi.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma_multi.sv new file mode 100644 index 0000000000..cceeae3c3c --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_fma_multi.sv @@ -0,0 +1,839 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_fma_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [2:0][WIDTH-1:0] operands_i, // 3 operands + input logic [NUM_FORMATS-1:0][2:0] is_boxed_i, // 3 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, // format of the multiplicands + input fpnew_pkg::fp_format_e dst_fmt_i, // format of the addend and result + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------- + // Constants + // ---------- + // The super-format that can hold all formats + localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig); + + localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits; + localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits; + + // Precision bits 'p' include the implicit bit + localparam int unsigned PRECISION_BITS = SUPER_MAN_BITS + 1; + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam int unsigned LOWER_SUM_WIDTH = 2 * PRECISION_BITS + 3; + localparam int unsigned LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + // Internal exponent width of FMA must accomodate all meaningful exponent values in order to avoid + // datapath leakage. This is either given by the exponent bits or the width of the LZC result. + // In most reasonable FP formats the internal exponent will be wider than the LZC result. + localparam int unsigned EXP_WIDTH = fpnew_pkg::maximum(SUPER_EXP_BITS + 2, LZC_RESULT_WIDTH); + // Shift amount width: maximum internal mantissa size is 3p+4 bits + localparam int unsigned SHIFT_AMOUNT_WIDTH = $clog2(3 * PRECISION_BITS + 5); + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [SUPER_EXP_BITS-1:0] exponent; + logic [SUPER_MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [2:0][WIDTH-1:0] operands_q; + fpnew_pkg::fp_format_e src_fmt_q; + fpnew_pkg::fp_format_e dst_fmt_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][2:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][NUM_FORMATS-1:0][2:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_src_fmt_q[0] = src_fmt_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; + + // ----------------- + // Input processing + // ----------------- + logic [NUM_FORMATS-1:0][2:0] fmt_sign; + logic signed [NUM_FORMATS-1:0][2:0][SUPER_EXP_BITS-1:0] fmt_exponent; + logic [NUM_FORMATS-1:0][2:0][SUPER_MAN_BITS-1:0] fmt_mantissa; + + fpnew_pkg::fp_info_t [NUM_FORMATS-1:0][2:0] info_q; + + // FP Input initialization + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + logic [2:0][FP_WIDTH-1:0] trimmed_ops; + + // Classify input + fpnew_classifier #( + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .NumOperands ( 3 ) + ) i_fpnew_classifier ( + .operands_i ( trimmed_ops ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS][fmt] ), + .info_o ( info_q[fmt] ) + ); + for (genvar op = 0; op < 3; op++) begin : gen_operands + assign trimmed_ops[op] = operands_q[op][FP_WIDTH-1:0]; + assign fmt_sign[fmt][op] = operands_q[op][FP_WIDTH-1]; + assign fmt_exponent[fmt][op] = signed'({1'b0, operands_q[op][MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[fmt][op] = {info_q[fmt][op].is_normal, operands_q[op][MAN_BITS-1:0]} << + (SUPER_MAN_BITS - MAN_BITS); // move to left of mantissa + end + end else begin : inactive_format + assign info_q[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled + assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + fp_t operand_a, operand_b, operand_c; + fpnew_pkg::fp_info_t info_a, info_b, info_c; + + // Operation selection and operand adjustment + // | \c op_q | \c op_mod_q | Operation Adjustment + // |:--------:|:-----------:|--------------------- + // | FMADD | \c 0 | FMADD: none + // | FMADD | \c 1 | FMSUB: Invert sign of operand C + // | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A + // | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C + // | ADD | \c 0 | ADD: Set operand A to +1.0 + // | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C + // | MUL | \c 0 | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode + // | *others* | \c - | *invalid* + // \note \c op_mod_q always inverts the sign of the addend. + always_comb begin : op_select + + // Default assignments - packing-order-agnostic + operand_a = {fmt_sign[src_fmt_q][0], fmt_exponent[src_fmt_q][0], fmt_mantissa[src_fmt_q][0]}; + operand_b = {fmt_sign[src_fmt_q][1], fmt_exponent[src_fmt_q][1], fmt_mantissa[src_fmt_q][1]}; + operand_c = {fmt_sign[dst_fmt_q][2], fmt_exponent[dst_fmt_q][2], fmt_mantissa[dst_fmt_q][2]}; + info_a = info_q[src_fmt_q][0]; + info_b = info_q[src_fmt_q][1]; + info_c = info_q[dst_fmt_q][2]; + + // op_mod_q inverts sign of operand C + operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::FMADD: ; // do nothing + fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product + fpnew_pkg::ADD: begin // Set multiplicand to +1 + operand_a = '{sign: 1'b0, exponent: fpnew_pkg::bias(src_fmt_q), mantissa: '0}; + info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. + end + fpnew_pkg::MUL: begin // Set addend to +0 or -0, depending whether the rounding mode is RDN + if (inp_pipe_rnd_mode_q[NUM_INP_REGS] == fpnew_pkg::RDN) + operand_c = '{sign: 1'b0, exponent: '0, mantissa: '0}; + else + operand_c = '{sign: 1'b1, exponent: '0, mantissa: '0}; + info_c = '{is_zero: 1'b1, is_boxed: 1'b1, default: 1'b0}; //zero, boxed value. + end + default: begin // propagate don't cares + operand_a = '{default: fpnew_pkg::DONT_CARE}; + operand_b = '{default: fpnew_pkg::DONT_CARE}; + operand_c = '{default: fpnew_pkg::DONT_CARE}; + info_a = '{default: fpnew_pkg::DONT_CARE}; + info_b = '{default: fpnew_pkg::DONT_CARE}; + info_c = '{default: fpnew_pkg::DONT_CARE}; + end + endcase + end + + // --------------------- + // Input classification + // --------------------- + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + logic effective_subtraction; + logic tentative_sign; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf, info_c.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan, info_c.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling, info_c.is_signalling}); + // Effective subtraction in FMA occurs when product and addend signs differ + assign effective_subtraction = operand_a.sign ^ operand_b.sign ^ operand_c.sign; + // The tentative sign of the FMA shall be the sign of the product + assign tentative_sign = operand_a.sign ^ operand_b.sign; + + // ---------------------- + // Special case handling + // ---------------------- + logic [WIDTH-1:0] special_result; + fpnew_pkg::status_t special_status; + logic result_is_special; + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result; + fpnew_pkg::status_t [NUM_FORMATS-1:0] fmt_special_status; + logic [NUM_FORMATS-1:0] fmt_result_is_special; + + + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + localparam logic [MAN_BITS-1:0] ZERO_MANTISSA = '0; + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : special_results + logic [FP_WIDTH-1:0] special_res; + + // Default assignment + special_res = {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + fmt_special_status[fmt] = '0; + fmt_result_is_special[fmt] = 1'b0; + + // Handle potentially mixed nan & infinity input => important for the case where infinity and + // zero are multiplied and added to a qnan. + // RISC-V mandates raising the NV exception in these cases: + // (inf * 0) + c or (0 * inf) + c INVALID, no matter c (even quiet NaNs) + if ((info_a.is_inf && info_b.is_zero) || (info_a.is_zero && info_b.is_inf)) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN + fmt_special_status[fmt].NV = 1'b1; // invalid operation + // NaN Inputs cause canonical quiet NaN at the output and maybe invalid OP + end else if (any_operand_nan) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN + fmt_special_status[fmt].NV = signalling_nan; // raise the invalid operation flag if signalling + // Special cases involving infinity + end else if (any_operand_inf) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA + // Effective addition of opposite infinities (±inf - ±inf) is invalid! + if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) + fmt_special_status[fmt].NV = 1'b1; // invalid operation + // Handle cases where output will be inf because of inf product input + else if (info_a.is_inf || info_b.is_inf) begin + // Result is infinity with the sign of the product + special_res = {operand_a.sign ^ operand_b.sign, QNAN_EXPONENT, ZERO_MANTISSA}; + // Handle cases where the addend is inf + end else if (info_c.is_inf) begin + // Result is inifinity with sign of the addend (= operand_c) + special_res = {operand_c.sign, QNAN_EXPONENT, ZERO_MANTISSA}; + end + end + // Initialize special result with ones (NaN-box) + fmt_special_result[fmt] = '1; + fmt_special_result[fmt][FP_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_special_status[fmt] = '0; + assign fmt_result_is_special[fmt] = 1'b0; + end + end + + // Detect special case from source format, I2F casts don't produce a special result + assign result_is_special = fmt_result_is_special[dst_fmt_q]; // they're all the same + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign special_status = fmt_special_status[dst_fmt_q]; + // Assemble result according to destination format + assign special_result = fmt_special_result[dst_fmt_q]; // destination format + + // --------------------------- + // Initial exponent data path + // --------------------------- + logic signed [EXP_WIDTH-1:0] exponent_a, exponent_b, exponent_c; + logic signed [EXP_WIDTH-1:0] exponent_addend, exponent_product, exponent_difference; + logic signed [EXP_WIDTH-1:0] tentative_exponent; + + // Zero-extend exponents into signed container - implicit width extension + assign exponent_a = signed'({1'b0, operand_a.exponent}); + assign exponent_b = signed'({1'b0, operand_b.exponent}); + assign exponent_c = signed'({1'b0, operand_c.exponent}); + + // Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx) + // with Ex the encoded exponent and nx the implicit bit. Internal exponents are biased to dst fmt. + assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm + // Biased product exponent is the sum of encoded exponents minus the bias. + assign exponent_product = (info_a.is_zero || info_b.is_zero) // in case the product is zero, set minimum exp. + ? 2 - signed'(fpnew_pkg::bias(dst_fmt_q)) + : signed'(exponent_a + info_a.is_subnormal + + exponent_b + info_b.is_subnormal + - 2*signed'(fpnew_pkg::bias(src_fmt_q)) + + signed'(fpnew_pkg::bias(dst_fmt_q))); // rebias for dst fmt + // Exponent difference is the addend exponent minus the product exponent + assign exponent_difference = exponent_addend - exponent_product; + // The tentative exponent will be the larger of the product or addend exponent + assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product; + + // Shift amount for addend based on exponents (unsigned as only right shifts) + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt; + + always_comb begin : addend_shift_amount + // Product-anchored case, saturated shift (addend is only in the sticky bit) + if (exponent_difference <= signed'(-2 * PRECISION_BITS - 1)) + addend_shamt = 3 * PRECISION_BITS + 4; + // Addend and product will have mutual bits to add + else if (exponent_difference <= signed'(PRECISION_BITS + 2)) + addend_shamt = unsigned'(signed'(PRECISION_BITS) + 3 - exponent_difference); + // Addend-anchored case, saturated shift (product is only in the sticky bit) + else + addend_shamt = 0; + end + + // ------------------ + // Product data path + // ------------------ + logic [PRECISION_BITS-1:0] mantissa_a, mantissa_b, mantissa_c; + logic [2*PRECISION_BITS-1:0] product; // the p*p product is 2p bits wide + logic [3*PRECISION_BITS+3:0] product_shifted; // addends are 3p+4 bit wide (including G/R) + + // Add implicit bits to mantissae + assign mantissa_a = {info_a.is_normal, operand_a.mantissa}; + assign mantissa_b = {info_b.is_normal, operand_b.mantissa}; + assign mantissa_c = {info_c.is_normal, operand_c.mantissa}; + + // Mantissa multiplier (a*b) + assign product = mantissa_a * mantissa_b; + + // Product is placed into a 3p+4 bit wide vector, padded with 2 bits for round and sticky: + // | 000...000 | product | RS | + // <- p+2 -> <- 2p -> < 2> + assign product_shifted = product << 2; // constant shift + + // ----------------- + // Addend data path + // ----------------- + logic [3*PRECISION_BITS+3:0] addend_after_shift; // upper 3p+4 bits are needed to go on + logic [PRECISION_BITS-1:0] addend_sticky_bits; // up to p bit of shifted addend are sticky + logic sticky_before_add; // they are compressed into a single sticky bit + logic [3*PRECISION_BITS+3:0] addend_shifted; // addends are 3p+4 bit wide (including G/R) + logic inject_carry_in; // inject carry for subtractions if needed + + // In parallel, the addend is right-shifted according to the exponent difference. Up to p bits are + // shifted out and compressed into a sticky bit. + // BEFORE THE SHIFT: + // | mantissa_c | 000..000 | + // <- p -> <- 3p+4 -> + // AFTER THE SHIFT: + // | 000..........000 | mantissa_c | 000...............0GR | sticky bits | + // <- addend_shamt -> <- p -> <- 2p+4-addend_shamt -> <- up to p -> + assign {addend_after_shift, addend_sticky_bits} = + (mantissa_c << (3 * PRECISION_BITS + 4)) >> addend_shamt; + + assign sticky_before_add = (| addend_sticky_bits); + + // In case of a subtraction, the addend is inverted + assign addend_shifted = (effective_subtraction) ? ~addend_after_shift : addend_after_shift; + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + + // ------ + // Adder + // ------ + logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry + logic sum_carry; // observe carry bit from sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic final_sign; + + //Mantissa adder (ab+c). In normal addition, it cannot overflow. + assign sum_raw = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + + // Complement negative sum (can only happen in subtraction -> overflows for positive results) + assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + + // In case of a mispredicted subtraction result, do a sign flip + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) + ? 1'b1 + : (effective_subtraction ? 1'b0 : tentative_sign); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic effective_subtraction_q; + logic signed [EXP_WIDTH-1:0] exponent_product_q; + logic signed [EXP_WIDTH-1:0] exponent_difference_q; + logic signed [EXP_WIDTH-1:0] tentative_exponent_q; + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q; + logic sticky_before_add_q; + logic [3*PRECISION_BITS+3:0] sum_q; + logic final_sign_q; + fpnew_pkg::fp_format_e dst_fmt_q2; + fpnew_pkg::roundmode_e rnd_mode_q; + logic result_is_special_q; + fp_t special_result_q; + fpnew_pkg::status_t special_status_q; + // Internal pipeline signals, index i holds signal after i register stages + logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; + logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; + logic [0:NUM_MID_REGS] mid_pipe_sticky_q; + logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; + logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q; + logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_eff_sub_q[0] = effective_subtraction; + assign mid_pipe_exp_prod_q[0] = exponent_product; + assign mid_pipe_exp_diff_q[0] = exponent_difference; + assign mid_pipe_tent_exp_q[0] = tentative_exponent; + assign mid_pipe_add_shamt_q[0] = addend_shamt; + assign mid_pipe_sticky_q[0] = sticky_before_add; + assign mid_pipe_sum_q[0] = sum; + assign mid_pipe_final_sign_q[0] = final_sign; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_dst_fmt_q[0] = dst_fmt_q; + assign mid_pipe_res_is_spec_q[0] = result_is_special; + assign mid_pipe_spec_res_q[0] = special_result; + assign mid_pipe_spec_stat_q[0] = special_status; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = mid_pipe_ready[i] & mid_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_eff_sub_q[i+1], mid_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_prod_q[i+1], mid_pipe_exp_prod_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_diff_q[i+1], mid_pipe_exp_diff_q[i], reg_ena, '0) + `FFL(mid_pipe_tent_exp_q[i+1], mid_pipe_tent_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0) + `FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0) + `FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0) + `FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_res_is_spec_q[i+1], mid_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_res_q[i+1], mid_pipe_spec_res_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_stat_q[i+1], mid_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + + // -------------- + // Normalization + // -------------- + logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched + logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes + logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count + logic lzc_zeroes; // in case only zeroes found + + logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount + logic signed [EXP_WIDTH-1:0] normalized_exponent; + + logic [3*PRECISION_BITS+4:0] sum_shifted; // result after first normalization shift + logic [PRECISION_BITS:0] final_mantissa; // final mantissa before rounding with round bit + logic [2*PRECISION_BITS+2:0] sum_sticky_bits; // remaining 2p+3 sticky bits after normalization + logic sticky_after_norm; // sticky bit after normalization + + logic signed [EXP_WIDTH-1:0] final_exponent; + + assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; + + // Leading zero counter for cancellations + lzc #( + .WIDTH ( LOWER_SUM_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( sum_lower ), + .cnt_o ( leading_zero_count ), + .empty_o ( lzc_zeroes ) + ); + + assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count}); + + // Normalization shift amount based on exponents and LZC (unsigned as only left shifts) + always_comb begin : norm_shift_amount + // Product-anchored case or cancellations require LZC + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + // Normal result (biased exponent > 0 and not a zero) + if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin + // Undo initial product shift, remove the counted zeroes + norm_shamt = PRECISION_BITS + 2 + leading_zero_count; + normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift + // Subnormal result + end else begin + // Cap the shift distance to align mantissa with minimum exponent + norm_shamt = unsigned'(signed'(PRECISION_BITS + 2 + exponent_product_q)); + normalized_exponent = 0; // subnormals encoded as 0 + end + // Addend-anchored case + end else begin + norm_shamt = addend_shamt_q; // Undo the initial shift + normalized_exponent = tentative_exponent_q; + end + end + + // Do the large normalization shift + assign sum_shifted = sum_q << norm_shamt; + + // The addend-anchored case needs a 1-bit normalization since the leading-one can be to the left + // or right of the (non-carry) MSB of the sum. + always_comb begin : small_norm + // Default assignment, discarding carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + + // The normalized sum has overflown, align right and fix exponent + if (sum_shifted[3*PRECISION_BITS+4]) begin // check the carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + // The normalized sum is normal, nothing to do + end else if (sum_shifted[3*PRECISION_BITS+3]) begin // check the sum MSB + // do nothing + // The normalized sum is still denormal, align left - unless the result is not already subnormal + end else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + // Otherwise we're denormal + end else begin + final_exponent = '0; + end + end + + // Update the sticky bit with the shifted-out bits + assign sticky_after_norm = (| {sum_sticky_bits}) | sticky_before_add_q; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic pre_round_sign; + logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] pre_round_abs; // absolute value of result before rounding + logic [1:0] round_sticky_bits; + + logic of_before_round, of_after_round; // overflow + logic uf_before_round, uf_after_round; // underflow + + logic [NUM_FORMATS-1:0][SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] fmt_pre_round_abs; // per format + logic [NUM_FORMATS-1:0][1:0] fmt_round_sticky_bits; + + logic [NUM_FORMATS-1:0] fmt_of_after_round; + logic [NUM_FORMATS-1:0] fmt_uf_after_round; + + logic rounded_sign; + logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] rounded_abs; // absolute value of result after rounding + logic result_zero; + + // Classification before round. RISC-V mandates checking underflow AFTER rounding! + assign of_before_round = final_exponent >= 2**(fpnew_pkg::exp_bits(dst_fmt_q2))-1; // infinity exponent is all ones + assign uf_before_round = final_exponent == 0; // exponent for subnormals capped to 0 + + // Pack exponent and mantissa into proper rounding form + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble + // Set up some constants + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + logic [EXP_BITS-1:0] pre_round_exponent; + logic [MAN_BITS-1:0] pre_round_mantissa; + + if (FpFmtConfig[fmt]) begin : active_format + + assign pre_round_exponent = (of_before_round) ? 2**EXP_BITS-2 : final_exponent[EXP_BITS-1:0]; + assign pre_round_mantissa = (of_before_round) ? '1 : final_mantissa[SUPER_MAN_BITS-:MAN_BITS]; + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign fmt_pre_round_abs[fmt] = {pre_round_exponent, pre_round_mantissa}; // 0-extend + + // Round bit is after mantissa (1 in case of overflow for rounding) + assign fmt_round_sticky_bits[fmt][1] = final_mantissa[SUPER_MAN_BITS-MAN_BITS] | + of_before_round; + + // remaining bits in mantissa to sticky (1 in case of overflow for rounding) + if (MAN_BITS < SUPER_MAN_BITS) begin : narrow_sticky + assign fmt_round_sticky_bits[fmt][0] = (| final_mantissa[SUPER_MAN_BITS-MAN_BITS-1:0]) | + sticky_after_norm | of_before_round; + end else begin : normal_sticky + assign fmt_round_sticky_bits[fmt][0] = sticky_after_norm | of_before_round; + end + end else begin : inactive_format + assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_round_sticky_bits[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign pre_round_sign = final_sign_q; + assign pre_round_abs = fmt_pre_round_abs[dst_fmt_q2]; + + // In case of overflow, the round and sticky bits are set for proper rounding + assign round_sticky_bits = fmt_round_sticky_bits[dst_fmt_q2]; + + // Perform the rounding + fpnew_rounding #( + .AbsWidth ( SUPER_EXP_BITS + SUPER_MAN_BITS ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( pre_round_sign ), + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( effective_subtraction_q ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) + ); + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result; + + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : post_process + // detect of / uf + fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal + fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. + + // Assemble regular result, nan box short ones. + fmt_result[fmt] = '1; + fmt_result[fmt][FP_WIDTH-1:0] = {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]}; + end + end else begin : inactive_format + assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Classification after rounding select by destination format + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = fmt_of_after_round[dst_fmt_q2]; + + + // ----------------- + // Result selection + // ----------------- + logic [WIDTH-1:0] regular_result; + fpnew_pkg::status_t regular_status; + + // Assemble regular result + assign regular_result = fmt_result[dst_fmt_q2]; + assign regular_status.NV = 1'b0; // only valid cases are handled in regular path + assign regular_status.DZ = 1'b0; // no divisions + assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF + assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + + // Final results for output pipeline + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + + // Select output depending on special case detection + assign result_d = result_is_special_q ? special_result_q : regular_result; + assign status_d = result_is_special_q ? special_status_q : regular_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_noncomp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_noncomp.sv new file mode 100644 index 0000000000..8a182617ba --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_noncomp.sv @@ -0,0 +1,415 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_noncomp #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) // do not change +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [1:0][WIDTH-1:0] operands_i, // 2 operands + input logic [1:0] is_boxed_i, // 2 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output fpnew_pkg::classmask_e class_mask_o, + output logic is_class_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------- + // Constants + // ---------- + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + // Pipelines + localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 2) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 2) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][1:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + + // --------------------- + // Input classification + // --------------------- + fpnew_pkg::fp_info_t [1:0] info_q; + + // Classify input + fpnew_classifier #( + .FpFormat ( FpFormat ), + .NumOperands ( 2 ) + ) i_class_a ( + .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ), + .info_o ( info_q ) + ); + + fp_t operand_a, operand_b; + fpnew_pkg::fp_info_t info_a, info_b; + + // Packing-order-agnostic assignments + assign operand_a = inp_pipe_operands_q[NUM_INP_REGS][0]; + assign operand_b = inp_pipe_operands_q[NUM_INP_REGS][1]; + assign info_a = info_q[0]; + assign info_b = info_q[1]; + + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling}); + + logic operands_equal, operand_a_smaller; + + // Equality checks for zeroes too + assign operands_equal = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero); + // Invert result if non-zero signs involved (unsigned comparison) + assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a.sign || operand_b.sign); + + // --------------- + // Sign Injection + // --------------- + fp_t sgnj_result; + fpnew_pkg::status_t sgnj_status; + logic sgnj_extension_bit; + + // Sign Injection - operation is encoded in rnd_mode_q: + // RNE = SGNJ, RTZ = SGNJN, RDN = SGNJX, RUP = Passthrough (no NaN-box check) + always_comb begin : sign_injections + logic sign_a, sign_b; // internal signs + // Default assignment + sgnj_result = operand_a; // result based on operand a + + // NaN-boxing check will treat invalid inputs as canonical NaNs + if (!info_a.is_boxed) sgnj_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; + + // Internal signs are treated as positive in case of non-NaN-boxed values + sign_a = operand_a.sign & info_a.is_boxed; + sign_b = operand_b.sign & info_b.is_boxed; + + // Do the sign injection based on rm field + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: sgnj_result.sign = sign_b; // SGNJ + fpnew_pkg::RTZ: sgnj_result.sign = ~sign_b; // SGNJN + fpnew_pkg::RDN: sgnj_result.sign = sign_a ^ sign_b; // SGNJX + fpnew_pkg::RUP: sgnj_result = operand_a; // passthrough + default: sgnj_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + + assign sgnj_status = '0; // sign injections never raise exceptions + + // op_mod_q enables integer sign-extension of result (for storing to integer regfile) + assign sgnj_extension_bit = inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result.sign : 1'b1; + + // ------------------ + // Minimum / Maximum + // ------------------ + fp_t minmax_result; + fpnew_pkg::status_t minmax_status; + logic minmax_extension_bit; + + // Minimum/Maximum - operation is encoded in rnd_mode_q: + // RNE = MIN, RTZ = MAX + always_comb begin : min_max + // Default assignment + minmax_status = '0; + + // Min/Max use quiet comparisons - only sNaN are invalid + minmax_status.NV = signalling_nan; + + // Both NaN inputs cause a NaN output + if (info_a.is_nan && info_b.is_nan) + minmax_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; // canonical qNaN + // If one operand is NaN, the non-NaN operand is returned + else if (info_a.is_nan) minmax_result = operand_b; + else if (info_b.is_nan) minmax_result = operand_a; + // Otherwise decide according to the operation + else begin + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: minmax_result = operand_a_smaller ? operand_a : operand_b; // MIN + fpnew_pkg::RTZ: minmax_result = operand_a_smaller ? operand_b : operand_a; // MAX + default: minmax_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + end + + assign minmax_extension_bit = 1'b1; // NaN-box as result is always a float value + + // ------------ + // Comparisons + // ------------ + fp_t cmp_result; + fpnew_pkg::status_t cmp_status; + logic cmp_extension_bit; + + // Comparisons - operation is encoded in rnd_mode_q: + // RNE = LE, RTZ = LT, RDN = EQ + // op_mod_q inverts boolean outputs + always_comb begin : comparisons + // Default assignment + cmp_result = '0; // false + cmp_status = '0; // no flags + + // Signalling NaNs always compare as false and are illegal + if (signalling_nan) cmp_status.NV = 1'b1; // invalid operation + // Otherwise do comparisons + else begin + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: begin // Less than or equal + if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid + else cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + fpnew_pkg::RTZ: begin // Less than + if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid + else cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + fpnew_pkg::RDN: begin // Equal + if (any_operand_nan) cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS]; // NaN always not equal + else cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + default: cmp_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + end + + assign cmp_extension_bit = 1'b0; // Comparisons always produce booleans in integer registers + + // --------------- + // Classification + // --------------- + fpnew_pkg::status_t class_status; + logic class_extension_bit; + fpnew_pkg::classmask_e class_mask_d; // the result is actually here + + // Classification - always return the classification mask on the dedicated port + always_comb begin : classify + if (info_a.is_normal) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGNORM : fpnew_pkg::POSNORM; + end else if (info_a.is_subnormal) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGSUBNORM : fpnew_pkg::POSSUBNORM; + end else if (info_a.is_zero) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGZERO : fpnew_pkg::POSZERO; + end else if (info_a.is_inf) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGINF : fpnew_pkg::POSINF; + end else if (info_a.is_nan) begin + class_mask_d = info_a.is_signalling ? fpnew_pkg::SNAN : fpnew_pkg::QNAN; + end else begin + class_mask_d = fpnew_pkg::QNAN; // default value + end + end + + assign class_status = '0; // classification does not set flags + assign class_extension_bit = 1'b0; // classification always produces results in integer registers + + // ----------------- + // Result selection + // ----------------- + fp_t result_d; + fpnew_pkg::status_t status_d; + logic extension_bit_d; + logic is_class_d; + + // Select result + always_comb begin : select_result + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::SGNJ: begin + result_d = sgnj_result; + status_d = sgnj_status; + extension_bit_d = sgnj_extension_bit; + end + fpnew_pkg::MINMAX: begin + result_d = minmax_result; + status_d = minmax_status; + extension_bit_d = minmax_extension_bit; + end + fpnew_pkg::CMP: begin + result_d = cmp_result; + status_d = cmp_status; + extension_bit_d = cmp_extension_bit; + end + fpnew_pkg::CLASSIFY: begin + result_d = '{default: fpnew_pkg::DONT_CARE}; // unused + status_d = class_status; + extension_bit_d = class_extension_bit; + end + default: begin + result_d = '{default: fpnew_pkg::DONT_CARE}; // dont care + status_d = '{default: fpnew_pkg::DONT_CARE}; // dont care + extension_bit_d = fpnew_pkg::DONT_CARE; // dont care + end + endcase + end + + assign is_class_d = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::CLASSIFY); + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + fp_t [0:NUM_OUT_REGS] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + logic [0:NUM_OUT_REGS] out_pipe_extension_bit_q; + fpnew_pkg::classmask_e [0:NUM_OUT_REGS] out_pipe_class_mask_q; + logic [0:NUM_OUT_REGS] out_pipe_is_class_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_extension_bit_q[0] = extension_bit_d; + assign out_pipe_class_mask_q[0] = class_mask_d; + assign out_pipe_is_class_q[0] = is_class_d; + assign out_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign out_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign out_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign out_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_extension_bit_q[i+1], out_pipe_extension_bit_q[i], reg_ena, '0) + `FFL(out_pipe_class_mask_q[i+1], out_pipe_class_mask_q[i], reg_ena, fpnew_pkg::QNAN) + `FFL(out_pipe_is_class_q[i+1], out_pipe_is_class_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS]; + assign class_mask_o = out_pipe_class_mask_q[NUM_OUT_REGS]; + assign is_class_o = out_pipe_is_class_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, out_pipe_valid_q}); +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_block.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_block.sv new file mode 100644 index 0000000000..2633406f2b --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_block.sv @@ -0,0 +1,244 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_opgroup_block #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::ADDMUL, + // FPU configuration + parameter int unsigned Width = 32, + parameter logic EnableVectors = 1'b1, + parameter fpnew_pkg::fmt_logic_t FpFmtMask = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtMask = '1, + parameter fpnew_pkg::fmt_unsigned_t FmtPipeRegs = '{default: 0}, + parameter fpnew_pkg::fmt_unit_types_t FmtUnitTypes = '{default: fpnew_pkg::PARALLEL}, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + // Do not change + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtMask, EnableVectors), + localparam type MaskType = logic [NUM_LANES-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------------- + // Type Definition + // ---------------- + typedef struct packed { + logic [Width-1:0] result; + fpnew_pkg::status_t status; + logic ext_bit; + TagType tag; + } output_t; + + // Handshake signals for the slices + logic [NUM_FORMATS-1:0] fmt_in_ready, fmt_out_valid, fmt_out_ready, fmt_busy; + output_t [NUM_FORMATS-1:0] fmt_outputs; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = in_valid_i & fmt_in_ready[dst_fmt_i]; // Ready is given by selected format + + // ------------------------- + // Generate Parallel Slices + // ------------------------- + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_parallel_slices + // Some constants for this format + localparam logic ANY_MERGED = fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam logic IS_FIRST_MERGED = + fpnew_pkg::is_first_enabled_multi(fpnew_pkg::fp_format_e'(fmt), FmtUnitTypes, FpFmtMask); + + // Generate slice only if format enabled + if (FpFmtMask[fmt] && (FmtUnitTypes[fmt] == fpnew_pkg::PARALLEL)) begin : active_format + + logic in_valid; + + assign in_valid = in_valid_i & (dst_fmt_i == fmt); // enable selected format + + // Forward masks related to the right SIMD lane + localparam int unsigned INTERNAL_LANES = fpnew_pkg::num_lanes(Width, fpnew_pkg::fp_format_e'(fmt), EnableVectors); + logic [INTERNAL_LANES-1:0] mask_slice; + always_comb for (int b = 0; b < INTERNAL_LANES; b++) mask_slice[b] = simd_mask_i[(NUM_LANES/INTERNAL_LANES)*b]; + + fpnew_opgroup_fmt_slice #( + .OpGroup ( OpGroup ), + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .Width ( Width ), + .EnableVectors ( EnableVectors ), + .NumPipeRegs ( FmtPipeRegs[fmt] ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) + ) i_fmt_slice ( + .clk_i, + .rst_ni, + .operands_i ( operands_i ), + .is_boxed_i ( is_boxed_i[fmt] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( mask_slice ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[fmt] ), + .flush_i, + .result_o ( fmt_outputs[fmt].result ), + .status_o ( fmt_outputs[fmt].status ), + .extension_bit_o( fmt_outputs[fmt].ext_bit ), + .tag_o ( fmt_outputs[fmt].tag ), + .out_valid_o ( fmt_out_valid[fmt] ), + .out_ready_i ( fmt_out_ready[fmt] ), + .busy_o ( fmt_busy[fmt] ) + ); + // If the format wants to use merged ops, tie off the dangling ones not used here + end else if (FpFmtMask[fmt] && ANY_MERGED && !IS_FIRST_MERGED) begin : merged_unused + + localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + // Ready is split up into formats + assign fmt_in_ready[fmt] = fmt_in_ready[int'(FMT)]; + + assign fmt_out_valid[fmt] = 1'b0; // don't emit values + assign fmt_busy[fmt] = 1'b0; // never busy + // Outputs are don't care + assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; + assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); + + // Tie off disabled formats + end else if (!FpFmtMask[fmt] || (FmtUnitTypes[fmt] == fpnew_pkg::DISABLED)) begin : disable_fmt + assign fmt_in_ready[fmt] = 1'b0; // don't accept operations + assign fmt_out_valid[fmt] = 1'b0; // don't emit values + assign fmt_busy[fmt] = 1'b0; // never busy + // Outputs are don't care + assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; + assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); + end + end + + // ---------------------- + // Generate Merged Slice + // ---------------------- + if (fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask)) begin : gen_merged_slice + + localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam REG = fpnew_pkg::get_num_regs_multi(FmtPipeRegs, FmtUnitTypes, FpFmtMask); + + logic in_valid; + + assign in_valid = in_valid_i & (FmtUnitTypes[dst_fmt_i] == fpnew_pkg::MERGED); + + fpnew_opgroup_multifmt_slice #( + .OpGroup ( OpGroup ), + .Width ( Width ), + .FpFmtConfig ( FpFmtMask ), + .IntFmtConfig ( IntFmtMask ), + .EnableVectors ( EnableVectors ), + .NumPipeRegs ( REG ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ) + ) i_multifmt_slice ( + .clk_i, + .rst_ni, + .operands_i, + .is_boxed_i, + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( simd_mask_i ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[FMT] ), + .flush_i, + .result_o ( fmt_outputs[FMT].result ), + .status_o ( fmt_outputs[FMT].status ), + .extension_bit_o ( fmt_outputs[FMT].ext_bit ), + .tag_o ( fmt_outputs[FMT].tag ), + .out_valid_o ( fmt_out_valid[FMT] ), + .out_ready_i ( fmt_out_ready[FMT] ), + .busy_o ( fmt_busy[FMT] ) + ); + + end + + // ------------------ + // Arbitrate Outputs + // ------------------ + output_t arbiter_output; + + // Round-Robin arbiter to decide which result to use + rr_arb_tree #( + .NumIn ( NUM_FORMATS ), + .DataType ( output_t ), + .AxiVldRdy ( 1'b1 ) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ( '0 ), + .req_i ( fmt_out_valid ), + .gnt_o ( fmt_out_ready ), + .data_i ( fmt_outputs ), + .gnt_i ( out_ready_i ), + .req_o ( out_valid_o ), + .data_o ( arbiter_output ), + .idx_o ( /* unused */ ) + ); + + // Unpack output + assign result_o = arbiter_output.result; + assign status_o = arbiter_output.status; + assign extension_bit_o = arbiter_output.ext_bit; + assign tag_o = arbiter_output.tag; + + assign busy_o = (| fmt_busy); + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv new file mode 100644 index 0000000000..35fbe4840c --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv @@ -0,0 +1,292 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_opgroup_fmt_slice #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::ADDMUL, + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + // FPU configuration + parameter int unsigned Width = 32, + parameter logic EnableVectors = 1'b1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + // Do not change + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_LANES = fpnew_pkg::num_lanes(Width, FpFormat, EnableVectors), + localparam type MaskType = logic [NUM_LANES-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(FpFormat); + localparam int unsigned SIMD_WIDTH = unsigned'(Width/NUM_LANES); + + + logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid; // Handshake signals for the lanes + logic vectorial_op; + + logic [NUM_LANES*FP_WIDTH-1:0] slice_result; + logic [Width-1:0] slice_regular_result, slice_class_result, slice_vec_class_result; + + fpnew_pkg::status_t [NUM_LANES-1:0] lane_status; + logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used + fpnew_pkg::classmask_e [NUM_LANES-1:0] lane_class_mask; + TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used + logic [NUM_LANES-1:0] lane_masks; + logic [NUM_LANES-1:0] lane_vectorial, lane_busy, lane_is_class; // dito + + logic result_is_vector, result_is_class; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane + assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled + + // --------------- + // Generate Lanes + // --------------- + for (genvar lane = 0; lane < int'(NUM_LANES); lane++) begin : gen_num_lanes + logic [FP_WIDTH-1:0] local_result; // lane-local results + logic local_sign; + + // Generate instances only if needed, lane 0 always generated + if ((lane == 0) || EnableVectors) begin : active_lane + logic in_valid, out_valid, out_ready; // lane-local handshake + + logic [NUM_OPERANDS-1:0][FP_WIDTH-1:0] local_operands; // lane-local operands + logic [FP_WIDTH-1:0] op_result; // lane-local results + fpnew_pkg::status_t op_status; + + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors + // Slice out the operands for this lane + always_comb begin : prepare_input + for (int i = 0; i < int'(NUM_OPERANDS); i++) begin + local_operands[i] = operands_i[i][(unsigned'(lane)+1)*FP_WIDTH-1:unsigned'(lane)*FP_WIDTH]; + end + end + + // Instantiate the operation from the selected opgroup + if (OpGroup == fpnew_pkg::ADDMUL) begin : lane_instance + fpnew_fma #( + .FpFormat ( FpFormat ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic ) + ) i_fma ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ) + ); + assign lane_is_class[lane] = 1'b0; + assign lane_class_mask[lane] = fpnew_pkg::NEGINF; + end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance + // fpnew_divsqrt #( + // .FpFormat (FpFormat), + // .NumPipeRegs(NumPipeRegs), + // .PipeConfig (PipeConfig), + // .TagType (TagType), + // .AuxType (logic) + // ) i_divsqrt ( + // .clk_i, + // .rst_ni, + // .operands_i ( local_operands ), + // .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + // .rnd_mode_i, + // .op_i, + // .op_mod_i, + // .tag_i, + // .aux_i ( vectorial_op ), // Remember whether operation was vectorial + // .in_valid_i ( in_valid ), + // .in_ready_o ( lane_in_ready[lane] ), + // .flush_i, + // .result_o ( op_result ), + // .status_o ( op_status ), + // .extension_bit_o ( lane_ext_bit[lane] ), + // .tag_o ( lane_tags[lane] ), + // .aux_o ( lane_vectorial[lane] ), + // .out_valid_o ( out_valid ), + // .out_ready_i ( out_ready ), + // .busy_o ( lane_busy[lane] ) + // ); + // assign lane_is_class[lane] = 1'b0; + end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance + fpnew_noncomp #( + .FpFormat (FpFormat), + .NumPipeRegs(NumPipeRegs), + .PipeConfig (PipeConfig), + .TagType (TagType), + .AuxType (logic) + ) i_noncomp ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .class_mask_o ( lane_class_mask[lane] ), + .is_class_o ( lane_is_class[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ) + ); + end // ADD OTHER OPTIONS HERE + + // Handshakes are only done if the lane is actually used + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + + // Properly NaN-box or sign-extend the slice result if not in use + assign local_result = lane_out_valid[lane] ? op_result : '{default: lane_ext_bit[0]}; + assign lane_status[lane] = lane_out_valid[lane] ? op_status : '0; + + // Otherwise generate constant sign-extension + end else begin + assign lane_out_valid[lane] = 1'b0; // unused lane + assign lane_in_ready[lane] = 1'b0; // unused lane + assign local_result = '{default: lane_ext_bit[0]}; // sign-extend/nan box + assign lane_status[lane] = '0; + assign lane_busy[lane] = 1'b0; + assign lane_is_class[lane] = 1'b0; + end + + // Insert lane result into slice result + assign slice_result[(unsigned'(lane)+1)*FP_WIDTH-1:unsigned'(lane)*FP_WIDTH] = local_result; + + // Create Classification results + if (TrueSIMDClass && SIMD_WIDTH >= 10) begin : vectorial_true_class // true vectorial class blocks are 10bits in size + assign slice_vec_class_result[lane*SIMD_WIDTH +: 10] = lane_class_mask[lane]; + assign slice_vec_class_result[(lane+1)*SIMD_WIDTH-1 -: SIMD_WIDTH-10] = '0; + end else if ((lane+1)*8 <= Width) begin : vectorial_class // vectorial class blocks are 8bits in size + assign local_sign = (lane_class_mask[lane] == fpnew_pkg::NEGINF || + lane_class_mask[lane] == fpnew_pkg::NEGNORM || + lane_class_mask[lane] == fpnew_pkg::NEGSUBNORM || + lane_class_mask[lane] == fpnew_pkg::NEGZERO); + // Write the current block segment + assign slice_vec_class_result[(lane+1)*8-1:lane*8] = { + local_sign, // BIT 7 + ~local_sign, // BIT 6 + lane_class_mask[lane] == fpnew_pkg::QNAN, // BIT 5 + lane_class_mask[lane] == fpnew_pkg::SNAN, // BIT 4 + lane_class_mask[lane] == fpnew_pkg::POSZERO + || lane_class_mask[lane] == fpnew_pkg::NEGZERO, // BIT 3 + lane_class_mask[lane] == fpnew_pkg::POSSUBNORM + || lane_class_mask[lane] == fpnew_pkg::NEGSUBNORM, // BIT 2 + lane_class_mask[lane] == fpnew_pkg::POSNORM + || lane_class_mask[lane] == fpnew_pkg::NEGNORM, // BIT 1 + lane_class_mask[lane] == fpnew_pkg::POSINF + || lane_class_mask[lane] == fpnew_pkg::NEGINF // BIT 0 + }; + end + end + + // ------------ + // Output Side + // ------------ + assign result_is_vector = lane_vectorial[0]; + assign result_is_class = lane_is_class[0]; + + assign slice_regular_result = $signed({extension_bit_o, slice_result}); + + localparam int unsigned CLASS_VEC_BITS = (NUM_LANES*8 > Width) ? 8 * (Width / 8) : NUM_LANES*8; + + // Pad out unused vec_class bits if each classify result is on 8 bits + if (!(TrueSIMDClass && SIMD_WIDTH >= 10)) begin + if (CLASS_VEC_BITS < Width) begin : pad_vectorial_class + assign slice_vec_class_result[Width-1:CLASS_VEC_BITS] = '0; + end + end + + // localparam logic [Width-1:0] CLASS_VEC_MASK = 2**CLASS_VEC_BITS - 1; + + assign slice_class_result = result_is_vector ? slice_vec_class_result : lane_class_mask[0]; + + // Select the proper result + assign result_o = result_is_class ? slice_class_result : slice_regular_result; + + assign extension_bit_o = lane_ext_bit[0]; // upper lanes unused + assign tag_o = lane_tags[0]; // upper lanes unused + assign busy_o = (| lane_busy); + assign out_valid_o = lane_out_valid[0]; // upper lanes unused + + + // Collapse the lane status + always_comb begin : output_processing + // Collapse the status + automatic fpnew_pkg::status_t temp_status; + temp_status = '0; + for (int i = 0; i < int'(NUM_LANES); i++) + temp_status |= lane_status[i] & {5{lane_masks[i]}}; + status_o = temp_status; + end +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv new file mode 100644 index 0000000000..08facb83c5 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv @@ -0,0 +1,449 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +`include "common_cells/registers.svh" + +module fpnew_opgroup_multifmt_slice #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV, + parameter int unsigned Width = 64, + // FPU configuration + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, + parameter logic EnableVectors = 1'b1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + // Do not change + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned NUM_SIMD_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors), + localparam type MaskType = logic [NUM_SIMD_LANES-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + localparam int unsigned MAX_FP_WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig); + localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig); + localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, 1'b1); + localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS; + // We will send the format information along with the data + localparam int unsigned FMT_BITS = + fpnew_pkg::maximum($clog2(NUM_FORMATS), $clog2(NUM_INT_FORMATS)); + localparam int unsigned AUX_BITS = FMT_BITS + 2; // also add vectorial and integer flags + + logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid, divsqrt_done, divsqrt_ready; // Handshake signals for the lanes + logic vectorial_op; + logic [FMT_BITS-1:0] dst_fmt; // destination format to pass along with operation + logic [AUX_BITS-1:0] aux_data; + + // additional flags for CONV + logic dst_fmt_is_int, dst_is_cpk; + logic [1:0] dst_vec_op; // info for vectorial results (for packing) + logic [2:0] target_aux_d, target_aux_q; + logic is_up_cast, is_down_cast; + + logic [NUM_FORMATS-1:0][Width-1:0] fmt_slice_result; + logic [NUM_INT_FORMATS-1:0][Width-1:0] ifmt_slice_result; + logic [Width-1:0] conv_slice_result; + + + logic [Width-1:0] conv_target_d, conv_target_q; // vectorial conversions update a register + + fpnew_pkg::status_t [NUM_LANES-1:0] lane_status; + logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used + TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used + logic [NUM_LANES-1:0] lane_masks; + logic [NUM_LANES-1:0][AUX_BITS-1:0] lane_aux; // only the first one is actually used + logic [NUM_LANES-1:0] lane_busy; // dito + + logic result_is_vector; + logic [FMT_BITS-1:0] result_fmt; + logic result_fmt_is_int, result_is_cpk; + logic [1:0] result_vec_op; // info for vectorial results (for packing) + + logic simd_synch_rdy, simd_synch_done; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane + assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled + + // Cast-and-Pack ops are encoded in operation and modifier + assign dst_fmt_is_int = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::F2I); + assign dst_is_cpk = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::CPKAB || + op_i == fpnew_pkg::CPKCD); + assign dst_vec_op = (OpGroup == fpnew_pkg::CONV) & {(op_i == fpnew_pkg::CPKCD), op_mod_i}; + + assign is_up_cast = (fpnew_pkg::fp_width(dst_fmt_i) > fpnew_pkg::fp_width(src_fmt_i)); + assign is_down_cast = (fpnew_pkg::fp_width(dst_fmt_i) < fpnew_pkg::fp_width(src_fmt_i)); + + // The destination format is the int format for F2I casts + assign dst_fmt = dst_fmt_is_int ? int_fmt_i : dst_fmt_i; + + // The data sent along consists of the vectorial flag and format bits + assign aux_data = {dst_fmt_is_int, vectorial_op, dst_fmt}; + assign target_aux_d = {dst_vec_op, dst_is_cpk}; + + // CONV passes one operand for assembly after the unit: opC for cpk, opB for others + if (OpGroup == fpnew_pkg::CONV) begin : conv_target + assign conv_target_d = dst_is_cpk ? operands_i[2] : operands_i[1]; + end + + // For 2-operand units, prepare boxing info + logic [NUM_FORMATS-1:0] is_boxed_1op; + logic [NUM_FORMATS-1:0][1:0] is_boxed_2op; + + always_comb begin : boxed_2op + for (int fmt = 0; fmt < NUM_FORMATS; fmt++) begin + is_boxed_1op[fmt] = is_boxed_i[fmt][0]; + is_boxed_2op[fmt] = is_boxed_i[fmt][1:0]; + end + end + + // --------------- + // Generate Lanes + // --------------- + for (genvar lane = 0; lane < int'(NUM_LANES); lane++) begin : gen_num_lanes + localparam int unsigned LANE = unsigned'(lane); // unsigned to please the linter + // Get a mask of active formats for this lane + localparam fpnew_pkg::fmt_logic_t ACTIVE_FORMATS = + fpnew_pkg::get_lane_formats(Width, FpFmtConfig, LANE); + localparam fpnew_pkg::ifmt_logic_t ACTIVE_INT_FORMATS = + fpnew_pkg::get_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam int unsigned MAX_WIDTH = fpnew_pkg::max_fp_width(ACTIVE_FORMATS); + + // Cast-specific parameters + localparam fpnew_pkg::fmt_logic_t CONV_FORMATS = + fpnew_pkg::get_conv_lane_formats(Width, FpFmtConfig, LANE); + localparam fpnew_pkg::ifmt_logic_t CONV_INT_FORMATS = + fpnew_pkg::get_conv_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam int unsigned CONV_WIDTH = fpnew_pkg::max_fp_width(CONV_FORMATS); + + // Lane parameters from Opgroup + localparam fpnew_pkg::fmt_logic_t LANE_FORMATS = (OpGroup == fpnew_pkg::CONV) + ? CONV_FORMATS : ACTIVE_FORMATS; + localparam int unsigned LANE_WIDTH = (OpGroup == fpnew_pkg::CONV) ? CONV_WIDTH : MAX_WIDTH; + + logic [LANE_WIDTH-1:0] local_result; // lane-local results + + // Generate instances only if needed, lane 0 always generated + if ((lane == 0) || EnableVectors) begin : active_lane + logic in_valid, out_valid, out_ready; // lane-local handshake + + logic [NUM_OPERANDS-1:0][LANE_WIDTH-1:0] local_operands; // lane-local oprands + logic [LANE_WIDTH-1:0] op_result; // lane-local results + fpnew_pkg::status_t op_status; + + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors + + // Slice out the operands for this lane, upper bits are ignored in the unit + always_comb begin : prepare_input + for (int unsigned i = 0; i < NUM_OPERANDS; i++) begin + local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(src_fmt_i); + end + + // override operand 0 for some conversions + if (OpGroup == fpnew_pkg::CONV) begin + // Source is an integer + if (op_i == fpnew_pkg::I2F) begin + local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::int_width(int_fmt_i); + // vectorial F2F up casts + end else if (op_i == fpnew_pkg::F2F) begin + if (vectorial_op && op_mod_i && is_up_cast) begin // up cast with upper half + local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::fp_width(src_fmt_i) + + MAX_FP_WIDTH/2; + end + // CPK + end else if (dst_is_cpk) begin + if (lane == 1) begin + local_operands[0] = operands_i[1][LANE_WIDTH-1:0]; // using opB as second argument + end + end + end + end + + // Instantiate the operation from the selected opgroup + if (OpGroup == fpnew_pkg::ADDMUL) begin : lane_instance + fpnew_fma_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_fma_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i, + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ) + ); + + end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance + fpnew_divsqrt_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_divsqrt_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[1:0] ), // 2 operands + .is_boxed_i ( is_boxed_2op ), // 2 operands + .rnd_mode_i, + .op_i, + .dst_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .divsqrt_done_o ( divsqrt_done[lane] ), + .simd_synch_done_i( simd_synch_done ), + .divsqrt_ready_o ( divsqrt_ready[lane]), + .simd_synch_rdy_i( simd_synch_rdy ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ) + ); + end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance + + end else if (OpGroup == fpnew_pkg::CONV) begin : lane_instance + fpnew_cast_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .IntFmtConfig ( CONV_INT_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_cast_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[0] ), + .is_boxed_i ( is_boxed_1op ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ) + ); + end // ADD OTHER OPTIONS HERE + + // Handshakes are only done if the lane is actually used + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + + // Properly NaN-box or sign-extend the slice result if not in use + assign local_result = lane_out_valid[lane] ? op_result : '{default: lane_ext_bit[0]}; + assign lane_status[lane] = lane_out_valid[lane] ? op_status : '0; + + // Otherwise generate constant sign-extension + end else begin : inactive_lane + assign lane_out_valid[lane] = 1'b0; // unused lane + assign lane_in_ready[lane] = 1'b0; // unused lane + assign local_result = '{default: lane_ext_bit[0]}; // sign-extend/nan box + assign lane_status[lane] = '0; + assign lane_busy[lane] = 1'b0; + end + + // Generate result packing depending on float format + for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : pack_fp_result + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + // only for active formats within the lane + if (ACTIVE_FORMATS[fmt]) begin + assign fmt_slice_result[fmt][(LANE+1)*FP_WIDTH-1:LANE*FP_WIDTH] = + local_result[FP_WIDTH-1:0]; + end else if ((LANE+1)*FP_WIDTH <= Width) begin + assign fmt_slice_result[fmt][(LANE+1)*FP_WIDTH-1:LANE*FP_WIDTH] = + '{default: lane_ext_bit[LANE]}; + end else if (LANE*FP_WIDTH < Width) begin + assign fmt_slice_result[fmt][Width-1:LANE*FP_WIDTH] = + '{default: lane_ext_bit[LANE]}; + end + end + + // Generate result packing depending on integer format + if (OpGroup == fpnew_pkg::CONV) begin : int_results_enabled + for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : pack_int_result + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + if (ACTIVE_INT_FORMATS[ifmt]) begin + assign ifmt_slice_result[ifmt][(LANE+1)*INT_WIDTH-1:LANE*INT_WIDTH] = + local_result[INT_WIDTH-1:0]; + end else if ((LANE+1)*INT_WIDTH <= Width) begin + assign ifmt_slice_result[ifmt][(LANE+1)*INT_WIDTH-1:LANE*INT_WIDTH] = '0; + end else if (LANE*INT_WIDTH < Width) begin + assign ifmt_slice_result[ifmt][Width-1:LANE*INT_WIDTH] = '0; + end + end + end + end + + // Extend slice result if needed + for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : extend_fp_result + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + if (NUM_LANES*FP_WIDTH < Width) + assign fmt_slice_result[fmt][Width-1:NUM_LANES*FP_WIDTH] = '{default: lane_ext_bit[0]}; + end + + // Mute int results if unused + for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : int_results_disabled + if (OpGroup != fpnew_pkg::CONV) begin : mute_int_result + assign ifmt_slice_result[ifmt] = '0; + end + end + + // Bypass lanes with target operand for vectorial casts + if (OpGroup == fpnew_pkg::CONV) begin : target_regs + // Bypass pipeline signals, index i holds signal after i register stages + logic [0:NumPipeRegs][Width-1:0] byp_pipe_target_q; + logic [0:NumPipeRegs][2:0] byp_pipe_aux_q; + logic [0:NumPipeRegs] byp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NumPipeRegs] byp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign byp_pipe_target_q[0] = conv_target_d; + assign byp_pipe_aux_q[0] = target_aux_d; + assign byp_pipe_valid_q[0] = in_valid_i & vectorial_op; + // Generate the register stages + for (genvar i = 0; i < NumPipeRegs; i++) begin : gen_bypass_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign byp_pipe_ready[i] = byp_pipe_ready[i+1] | ~byp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(byp_pipe_valid_q[i+1], byp_pipe_valid_q[i], byp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = byp_pipe_ready[i] & byp_pipe_valid_q[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(byp_pipe_target_q[i+1], byp_pipe_target_q[i], reg_ena, '0) + `FFL(byp_pipe_aux_q[i+1], byp_pipe_aux_q[i], reg_ena, '0) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign byp_pipe_ready[NumPipeRegs] = out_ready_i & result_is_vector; + // Output stage: assign module outputs + assign conv_target_q = byp_pipe_target_q[NumPipeRegs]; + + // decode the aux data + assign {result_vec_op, result_is_cpk} = byp_pipe_aux_q[NumPipeRegs]; + end else begin : no_conv + assign {result_vec_op, result_is_cpk} = '0; + end + + // Synch lanes if there is more than one + assign simd_synch_rdy = EnableVectors ? &divsqrt_ready : divsqrt_ready[0]; + assign simd_synch_done = EnableVectors ? &divsqrt_done : divsqrt_done[0]; + + // ------------ + // Output Side + // ------------ + assign {result_fmt_is_int, result_is_vector, result_fmt} = lane_aux[0]; + + assign result_o = result_fmt_is_int + ? ifmt_slice_result[result_fmt] + : fmt_slice_result[result_fmt]; + + assign extension_bit_o = lane_ext_bit[0]; // don't care about upper ones + assign tag_o = lane_tags[0]; // don't care about upper ones + assign busy_o = (| lane_busy); + + assign out_valid_o = lane_out_valid[0]; // don't care about upper ones + + // Collapse the status + always_comb begin : output_processing + // Collapse the status + automatic fpnew_pkg::status_t temp_status; + temp_status = '0; + for (int i = 0; i < int'(NUM_LANES); i++) + temp_status |= lane_status[i] & {5{lane_masks[i]}}; + status_o = temp_status; + end + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_pkg.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_pkg.sv new file mode 100644 index 0000000000..7addc3e9b2 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_pkg.sv @@ -0,0 +1,495 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +package fpnew_pkg; + + // --------- + // FP TYPES + // --------- + // | Enumerator | Format | Width | EXP_BITS | MAN_BITS + // |:----------:|------------------|-------:|:--------:|:--------: + // | FP32 | IEEE binary32 | 32 bit | 8 | 23 + // | FP64 | IEEE binary64 | 64 bit | 11 | 52 + // | FP16 | IEEE binary16 | 16 bit | 5 | 10 + // | FP8 | binary8 | 8 bit | 5 | 2 + // | FP16ALT | binary16alt | 16 bit | 8 | 7 + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + // Encoding for a format + typedef struct packed { + int unsigned exp_bits; + int unsigned man_bits; + } fp_encoding_t; + + localparam int unsigned NUM_FP_FORMATS = 5; // change me to add formats + localparam int unsigned FP_FORMAT_BITS = $clog2(NUM_FP_FORMATS); + + // FP formats + typedef enum logic [FP_FORMAT_BITS-1:0] { + FP32 = 'd0, + FP64 = 'd1, + FP16 = 'd2, + FP8 = 'd3, + FP16ALT = 'd4 + // add new formats here + } fp_format_e; + + // Encodings for supported FP formats + localparam fp_encoding_t [0:NUM_FP_FORMATS-1] FP_ENCODINGS = '{ + '{8, 23}, // IEEE binary32 (single) + '{11, 52}, // IEEE binary64 (double) + '{5, 10}, // IEEE binary16 (half) + '{5, 2}, // custom binary8 + '{8, 7} // custom binary16alt + // add new formats here + }; + + typedef logic [0:NUM_FP_FORMATS-1] fmt_logic_t; // Logic indexed by FP format (for masks) + typedef logic [0:NUM_FP_FORMATS-1][31:0] fmt_unsigned_t; // Unsigned indexed by FP format + + localparam fmt_logic_t CPK_FORMATS = 5'b11000; // FP32 and FP64 can provide CPK only + + // --------- + // INT TYPES + // --------- + // | Enumerator | Width | + // |:----------:|-------:| + // | INT8 | 8 bit | + // | INT16 | 16 bit | + // | INT32 | 32 bit | + // | INT64 | 64 bit | + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + localparam int unsigned NUM_INT_FORMATS = 4; // change me to add formats + localparam int unsigned INT_FORMAT_BITS = $clog2(NUM_INT_FORMATS); + + // Int formats + typedef enum logic [INT_FORMAT_BITS-1:0] { + INT8, + INT16, + INT32, + INT64 + // add new formats here + } int_format_e; + + // Returns the width of an INT format by index + function automatic int unsigned int_width(int_format_e ifmt); + unique case (ifmt) + INT8: return 8; + INT16: return 16; + INT32: return 32; + INT64: return 64; + default: begin + // pragma translate_off + $fatal(1, "Invalid INT format supplied"); + // pragma translate_on + // just return any integer to avoid any latches + // hopefully this error is caught by simulation + return INT8; + end + endcase + endfunction + + typedef logic [0:NUM_INT_FORMATS-1] ifmt_logic_t; // Logic indexed by INT format (for masks) + + // -------------- + // FP OPERATIONS + // -------------- + localparam int unsigned NUM_OPGROUPS = 4; + + // Each FP operation belongs to an operation group + typedef enum logic [1:0] { + ADDMUL, DIVSQRT, NONCOMP, CONV + } opgroup_e; + + localparam int unsigned OP_BITS = 4; + + typedef enum logic [OP_BITS-1:0] { + FMADD, FNMSUB, ADD, MUL, // ADDMUL operation group + DIV, SQRT, // DIVSQRT operation group + SGNJ, MINMAX, CMP, CLASSIFY, // NONCOMP operation group + F2F, F2I, I2F, CPKAB, CPKCD // CONV operation group + } operation_e; + + // ------------------- + // RISC-V FP-SPECIFIC + // ------------------- + // Rounding modes + typedef enum logic [2:0] { + RNE = 3'b000, + RTZ = 3'b001, + RDN = 3'b010, + RUP = 3'b011, + RMM = 3'b100, + ROD = 3'b101, // This mode is not defined in RISC-V FP-SPEC + DYN = 3'b111 + } roundmode_e; + + // Status flags + typedef struct packed { + logic NV; // Invalid + logic DZ; // Divide by zero + logic OF; // Overflow + logic UF; // Underflow + logic NX; // Inexact + } status_t; + + // Information about a floating point value + typedef struct packed { + logic is_normal; // is the value normal + logic is_subnormal; // is the value subnormal + logic is_zero; // is the value zero + logic is_inf; // is the value infinity + logic is_nan; // is the value NaN + logic is_signalling; // is the value a signalling NaN + logic is_quiet; // is the value a quiet NaN + logic is_boxed; // is the value properly NaN-boxed (RISC-V specific) + } fp_info_t; + + // Classification mask + typedef enum logic [9:0] { + NEGINF = 10'b00_0000_0001, + NEGNORM = 10'b00_0000_0010, + NEGSUBNORM = 10'b00_0000_0100, + NEGZERO = 10'b00_0000_1000, + POSZERO = 10'b00_0001_0000, + POSSUBNORM = 10'b00_0010_0000, + POSNORM = 10'b00_0100_0000, + POSINF = 10'b00_1000_0000, + SNAN = 10'b01_0000_0000, + QNAN = 10'b10_0000_0000 + } classmask_e; + + // ------------------ + // FPU configuration + // ------------------ + // Pipelining registers can be inserted (at elaboration time) into operational units + typedef enum logic [1:0] { + BEFORE, // registers are inserted at the inputs of the unit + AFTER, // registers are inserted at the outputs of the unit + INSIDE, // registers are inserted at predetermined (suboptimal) locations in the unit + DISTRIBUTED // registers are evenly distributed, INSIDE >= AFTER >= BEFORE + } pipe_config_t; + + // Arithmetic units can be arranged in parallel (per format), merged (multi-format) or not at all. + typedef enum logic [1:0] { + DISABLED, // arithmetic units are not generated + PARALLEL, // arithmetic units are generated in prallel slices, one for each format + MERGED // arithmetic units are contained within a merged unit holding multiple formats + } unit_type_t; + + // Array of unit types indexed by format + typedef unit_type_t [0:NUM_FP_FORMATS-1] fmt_unit_types_t; + + // Array of format-specific unit types by opgroup + typedef fmt_unit_types_t [0:NUM_OPGROUPS-1] opgrp_fmt_unit_types_t; + // same with unsigned + typedef fmt_unsigned_t [0:NUM_OPGROUPS-1] opgrp_fmt_unsigned_t; + + // FPU configuration: features + typedef struct packed { + int unsigned Width; + logic EnableVectors; + logic EnableNanBox; + fmt_logic_t FpFmtMask; + ifmt_logic_t IntFmtMask; + } fpu_features_t; + + localparam fpu_features_t RV64D = '{ + Width: 64, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0011 + }; + + localparam fpu_features_t RV32D = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV32F = '{ + Width: 32, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV64D_Xsflt = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11111, + IntFmtMask: 4'b1111 + }; + + localparam fpu_features_t RV32F_Xsflt = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10111, + IntFmtMask: 4'b1110 + }; + + localparam fpu_features_t RV32F_Xf16alt_Xfvec = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10001, + IntFmtMask: 4'b0110 + }; + + + // FPU configuraion: implementation + typedef struct packed { + opgrp_fmt_unsigned_t PipeRegs; + opgrp_fmt_unit_types_t UnitTypes; + pipe_config_t PipeConfig; + } fpu_implementation_t; + + localparam fpu_implementation_t DEFAULT_NOREGS = '{ + PipeRegs: '{default: 0}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: MERGED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + localparam fpu_implementation_t DEFAULT_SNITCH = '{ + PipeRegs: '{default: 1}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: DISABLED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + // ----------------------- + // Synthesis optimization + // ----------------------- + localparam logic DONT_CARE = 1'b1; // the value to assign as don't care + + // ------------------------- + // General helper functions + // ------------------------- + function automatic int minimum(int a, int b); + return (a < b) ? a : b; + endfunction + + function automatic int maximum(int a, int b); + return (a > b) ? a : b; + endfunction + + // ------------------------------------------- + // Helper functions for FP formats and values + // ------------------------------------------- + // Returns the width of a FP format + function automatic int unsigned fp_width(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits + FP_ENCODINGS[fmt].man_bits + 1; + endfunction + + // Returns the widest FP format present + function automatic int unsigned max_fp_width(fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(maximum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the narrowest FP format present + function automatic int unsigned min_fp_width(fmt_logic_t cfg); + automatic int unsigned res = max_fp_width(cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(minimum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the number of expoent bits for a format + function automatic int unsigned exp_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits; + endfunction + + // Returns the number of mantissa bits for a format + function automatic int unsigned man_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].man_bits; + endfunction + + // Returns the bias value for a given format (as per IEEE 754-2008) + function automatic int unsigned bias(fp_format_e fmt); + return unsigned'(2**(FP_ENCODINGS[fmt].exp_bits-1)-1); // symmetrical bias + endfunction + + function automatic fp_encoding_t super_format(fmt_logic_t cfg); + automatic fp_encoding_t res; + res = '0; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + if (cfg[fmt]) begin // only active format + res.exp_bits = unsigned'(maximum(res.exp_bits, exp_bits(fp_format_e'(fmt)))); + res.man_bits = unsigned'(maximum(res.man_bits, man_bits(fp_format_e'(fmt)))); + end + return res; + endfunction + + // ------------------------------------------- + // Helper functions for INT formats and values + // ------------------------------------------- + // Returns the widest INT format present + function automatic int unsigned max_int_width(ifmt_logic_t cfg); + automatic int unsigned res = 0; + for (int ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin + if (cfg[ifmt]) res = maximum(res, int_width(int_format_e'(ifmt))); + end + return res; + endfunction + + // -------------------------------------------------- + // Helper functions for operations and FPU structure + // -------------------------------------------------- + // Returns the operation group of the given operation + function automatic opgroup_e get_opgroup(operation_e op); + unique case (op) + FMADD, FNMSUB, ADD, MUL: return ADDMUL; + DIV, SQRT: return DIVSQRT; + SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP; + F2F, F2I, I2F, CPKAB, CPKCD: return CONV; + default: return NONCOMP; + endcase + endfunction + + // Returns the number of operands by operation group + function automatic int unsigned num_operands(opgroup_e grp); + unique case (grp) + ADDMUL: return 3; + DIVSQRT: return 2; + NONCOMP: return 2; + CONV: return 3; // vectorial casts use 3 operands + default: return 0; + endcase + endfunction + + // Returns the number of lanes according to width, format and vectors + function automatic int unsigned num_lanes(int unsigned width, fp_format_e fmt, logic vec); + return vec ? width / fp_width(fmt) : 1; // if no vectors, only one lane + endfunction + + // Returns the maximum number of lanes in the FPU according to width, format config and vectors + function automatic int unsigned max_num_lanes(int unsigned width, fmt_logic_t cfg, logic vec); + return vec ? width / min_fp_width(cfg) : 1; // if no vectors, only one lane + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a multiformat slice + function automatic fmt_logic_t get_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format + res[fmt] = cfg[fmt] & (width / fp_width(fp_format_e'(fmt)) > lane_no); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a multiformat slice + function automatic ifmt_logic_t get_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + if ((fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt)))) + res[ifmt] |= icfg[ifmt] && lanefmts[fmt]; + return res; + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a CONV slice + function automatic fmt_logic_t get_conv_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format, CPK at least twice + res[fmt] = cfg[fmt] && ((width / fp_width(fp_format_e'(fmt)) > lane_no) || + (CPK_FORMATS[fmt] && (lane_no < 2))); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a CONV slice + function automatic ifmt_logic_t get_conv_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_conv_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + res[ifmt] |= icfg[ifmt] && lanefmts[fmt] && + (fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt))); + return res; + endfunction + + // Return whether any active format is set as MERGED + function automatic logic any_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return 1'b1; + return 1'b0; + endfunction + + // Return whether the given format is the first active one set as MERGED + function automatic logic is_first_enabled_multi(fp_format_e fmt, + fmt_unit_types_t types, + fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) return (fp_format_e'(i) == fmt); + end + return 1'b0; + endfunction + + // Returns the first format that is active and is set as MERGED + function automatic fp_format_e get_first_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return fp_format_e'(i); + return fp_format_e'(0); + endfunction + + // Returns the largest number of regs that is active and is set as MERGED + function automatic int unsigned get_num_regs_multi(fmt_unsigned_t regs, + fmt_unit_types_t types, + fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) res = maximum(res, regs[i]); + end + return res; + endfunction + +endpackage diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_rounding.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_rounding.sv new file mode 100644 index 0000000000..4e67720942 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_rounding.sv @@ -0,0 +1,76 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_rounding #( + parameter int unsigned AbsWidth=2 // Width of the abolute value, without sign bit +) ( + // Input value + input logic [AbsWidth-1:0] abs_value_i, // absolute value without sign + input logic sign_i, + // Rounding information + input logic [1:0] round_sticky_bits_i, // round and sticky bits {RS} + input fpnew_pkg::roundmode_e rnd_mode_i, + input logic effective_subtraction_i, // sign of inputs affects rounding of zeroes + // Output value + output logic [AbsWidth-1:0] abs_rounded_o, // absolute value without sign + output logic sign_o, + // Output classification + output logic exact_zero_o // output is an exact zero +); + + logic round_up; // Rounding decision + + // Take the rounding decision according to RISC-V spec + // RoundMode | Mnemonic | Meaning + // :--------:|:--------:|:------- + // 000 | RNE | Round to Nearest, ties to Even + // 001 | RTZ | Round towards Zero + // 010 | RDN | Round Down (towards -\infty) + // 011 | RUP | Round Up (towards \infty) + // 100 | RMM | Round to Nearest, ties to Max Magnitude + // 101 | ROD | Round towards odd (this mode is not define in RISC-V FP-SPEC) + // others | | *invalid* + always_comb begin : rounding_decision + unique case (rnd_mode_i) + fpnew_pkg::RNE: // Decide accoring to round/sticky bits + unique case (round_sticky_bits_i) + 2'b00, + 2'b01: round_up = 1'b0; // < ulp/2 away, round down + 2'b10: round_up = abs_value_i[0]; // = ulp/2 away, round towards even result + 2'b11: round_up = 1'b1; // > ulp/2 away, round up + default: round_up = fpnew_pkg::DONT_CARE; + endcase + fpnew_pkg::RTZ: round_up = 1'b0; // always round down + fpnew_pkg::RDN: round_up = (| round_sticky_bits_i) ? sign_i : 1'b0; // to 0 if +, away if - + fpnew_pkg::RUP: round_up = (| round_sticky_bits_i) ? ~sign_i : 1'b0; // to 0 if -, away if + + fpnew_pkg::RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + fpnew_pkg::ROD: round_up = ~abs_value_i[0] & (| round_sticky_bits_i); + default: round_up = fpnew_pkg::DONT_CARE; // propagate x + endcase + end + + // Perform the rounding, exponent change and overflow to inf happens automagically + assign abs_rounded_o = abs_value_i + round_up; + + // True zero result is a zero result without dirty round/sticky bits + assign exact_zero_o = (abs_value_i == '0) && (round_sticky_bits_i == '0); + + // In case of effective subtraction (thus signs of addition operands must have differed) and a + // true zero result, the result sign is '-' in case of RDN and '+' for other modes. + assign sign_o = (exact_zero_o && effective_subtraction_i) + ? (rnd_mode_i == fpnew_pkg::RDN) + : sign_i; + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpnew_top.sv b/flow/designs/src/cva6/core/cvfpu/src/fpnew_top.sv new file mode 100644 index 0000000000..f6116a5d59 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpnew_top.sv @@ -0,0 +1,185 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_top #( + // FPU configuration + parameter fpnew_pkg::fpu_features_t Features = fpnew_pkg::RV64D_Xsflt, + parameter fpnew_pkg::fpu_implementation_t Implementation = fpnew_pkg::DEFAULT_NOREGS, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + parameter int unsigned EnableSIMDMask = 0, + // Do not change + localparam int unsigned NumLanes = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors), + localparam type MaskType = logic [NumLanes-1:0], + localparam int unsigned WIDTH = Features.Width, + localparam int unsigned NUM_OPERANDS = 3 +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][WIDTH-1:0] operands_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + localparam int unsigned NUM_OPGROUPS = fpnew_pkg::NUM_OPGROUPS; + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS; + + // ---------------- + // Type Definition + // ---------------- + typedef struct packed { + logic [WIDTH-1:0] result; + fpnew_pkg::status_t status; + TagType tag; + } output_t; + + // Handshake signals for the blocks + logic [NUM_OPGROUPS-1:0] opgrp_in_ready, opgrp_out_valid, opgrp_out_ready, opgrp_ext, opgrp_busy; + output_t [NUM_OPGROUPS-1:0] opgrp_outputs; + + logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = in_valid_i & opgrp_in_ready[fpnew_pkg::get_opgroup(op_i)]; + + // NaN-boxing check + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_nanbox_check + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + // NaN boxing is only generated if it's enabled and needed + if (Features.EnableNanBox && (FP_WIDTH < WIDTH)) begin : check + for (genvar op = 0; op < int'(NUM_OPERANDS); op++) begin : operands + assign is_boxed[fmt][op] = (!vectorial_op_i) + ? operands_i[op][WIDTH-1:FP_WIDTH] == '1 + : 1'b1; + end + end else begin : no_check + assign is_boxed[fmt] = '1; + end + end + + // Filter out the mask if not used + MaskType simd_mask; + assign simd_mask = simd_mask_i | ~{NumLanes{logic'(EnableSIMDMask)}}; + + // ------------------------- + // Generate Operation Blocks + // ------------------------- + for (genvar opgrp = 0; opgrp < int'(NUM_OPGROUPS); opgrp++) begin : gen_operation_groups + localparam int unsigned NUM_OPS = fpnew_pkg::num_operands(fpnew_pkg::opgroup_e'(opgrp)); + + logic in_valid; + logic [NUM_FORMATS-1:0][NUM_OPS-1:0] input_boxed; + + assign in_valid = in_valid_i & (fpnew_pkg::get_opgroup(op_i) == fpnew_pkg::opgroup_e'(opgrp)); + + // slice out input boxing + always_comb begin : slice_inputs + for (int unsigned fmt = 0; fmt < NUM_FORMATS; fmt++) + input_boxed[fmt] = is_boxed[fmt][NUM_OPS-1:0]; + end + + fpnew_opgroup_block #( + .OpGroup ( fpnew_pkg::opgroup_e'(opgrp) ), + .Width ( WIDTH ), + .EnableVectors ( Features.EnableVectors ), + .FpFmtMask ( Features.FpFmtMask ), + .IntFmtMask ( Features.IntFmtMask ), + .FmtPipeRegs ( Implementation.PipeRegs[opgrp] ), + .FmtUnitTypes ( Implementation.UnitTypes[opgrp] ), + .PipeConfig ( Implementation.PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) + ) i_opgroup_block ( + .clk_i, + .rst_ni, + .operands_i ( operands_i[NUM_OPS-1:0] ), + .is_boxed_i ( input_boxed ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( simd_mask ), + .in_valid_i ( in_valid ), + .in_ready_o ( opgrp_in_ready[opgrp] ), + .flush_i, + .result_o ( opgrp_outputs[opgrp].result ), + .status_o ( opgrp_outputs[opgrp].status ), + .extension_bit_o ( opgrp_ext[opgrp] ), + .tag_o ( opgrp_outputs[opgrp].tag ), + .out_valid_o ( opgrp_out_valid[opgrp] ), + .out_ready_i ( opgrp_out_ready[opgrp] ), + .busy_o ( opgrp_busy[opgrp] ) + ); + end + + // ------------------ + // Arbitrate Outputs + // ------------------ + output_t arbiter_output; + + // Round-Robin arbiter to decide which result to use + rr_arb_tree #( + .NumIn ( NUM_OPGROUPS ), + .DataType ( output_t ), + .AxiVldRdy ( 1'b1 ) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ( '0 ), + .req_i ( opgrp_out_valid ), + .gnt_o ( opgrp_out_ready ), + .data_i ( opgrp_outputs ), + .gnt_i ( out_ready_i ), + .req_o ( out_valid_o ), + .data_o ( arbiter_output ), + .idx_o ( /* unused */ ) + ); + + // Unpack output + assign result_o = arbiter_output.result; + assign status_o = arbiter_output.status; + assign tag_o = arbiter_output.tag; + + assign busy_o = (| opgrp_busy); + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv new file mode 100644 index 0000000000..bda9c01fb7 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv @@ -0,0 +1,3413 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 04/03/2018 // +// Design Name: FPU // +// Module Name: control_mvp.sv // +// Project Name: Private FPU // +// Language: SystemVerilog // +// // +// Description: the control logic of div and sqrt // +// // +// Revision Date: 12/04/2018 // +// Lei Li // +// To address some requirements by Stefan and add low power // +// control for special cases // +// Revision Date: 13/04/2018 // +// Lei Li // +// To fix some bug found in Control FSM // +// when Iteration_unit_num_S = 2'b10 // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +import defs_div_sqrt_mvp::*; + +module control_mvp + + (//Input + input logic Clk_CI, + input logic Rst_RBI, + input logic Div_start_SI , + input logic Sqrt_start_SI, + input logic Start_SI, + input logic Kill_SI, + input logic Special_case_SBI, + input logic Special_case_dly_SBI, + input logic [C_PC-1:0] Precision_ctl_SI, + input logic [1:0] Format_sel_SI, + input logic [C_MANT_FP64:0] Numerator_DI, + input logic [C_EXP_FP64:0] Exp_num_DI, + input logic [C_MANT_FP64:0] Denominator_DI, + input logic [C_EXP_FP64:0] Exp_den_DI, + + + output logic Div_start_dly_SO , + output logic Sqrt_start_dly_SO, + output logic Div_enable_SO, + output logic Sqrt_enable_SO, + + + //To next stage + output logic Full_precision_SO, + output logic FP32_SO, + output logic FP64_SO, + output logic FP16_SO, + output logic FP16ALT_SO, + + output logic Ready_SO, + output logic Done_SO, + + output logic [C_MANT_FP64+4:0] Mant_result_prenorm_DO, + // output logic [3:0] Round_bit_DO, + output logic [C_EXP_FP64+1:0] Exp_result_prenorm_DO + ); + + logic [C_MANT_FP64+1+4:0] Partial_remainder_DN,Partial_remainder_DP; //58bits,r=q+2 + logic [C_MANT_FP64+4:0] Quotient_DP; //57bits + ///////////////////////////////////////////////////////////////////////////// + // Assign Inputs // + ///////////////////////////////////////////////////////////////////////////// + logic [C_MANT_FP64+1:0] Numerator_se_D; //sign extension and hidden bit + logic [C_MANT_FP64+1:0] Denominator_se_D; //signa extension and hidden bit + logic [C_MANT_FP64+1:0] Denominator_se_DB; //1's complement + + assign Numerator_se_D={1'b0,Numerator_DI}; + + assign Denominator_se_D={1'b0,Denominator_DI}; + + always_comb + begin + if(FP32_SO) + begin + Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; + end + else if(FP64_SO) begin + Denominator_se_DB=~Denominator_se_D; + end + else if(FP16_SO) begin + Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; + end + else begin + Denominator_se_DB={~Denominator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; + end + end + + + logic [C_MANT_FP64+1:0] Mant_D_sqrt_Norm; + + assign Mant_D_sqrt_Norm=Exp_num_DI[0]?{1'b0,Numerator_DI}:{Numerator_DI,1'b0}; //for sqrt + + ///////////////////////////////////////////////////////////////////////////// + // Format Selection // + ///////////////////////////////////////////////////////////////////////////// + logic [1:0] Format_sel_S; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Format_sel_S<='b0; + end + else if(Start_SI&&Ready_SO) + begin + Format_sel_S<=Format_sel_SI; + end + else + begin + Format_sel_S<=Format_sel_S; + end + end + + assign FP32_SO = (Format_sel_S==2'b00); + assign FP64_SO = (Format_sel_S==2'b01); + assign FP16_SO = (Format_sel_S==2'b10); + assign FP16ALT_SO = (Format_sel_S==2'b11); + + + + ///////////////////////////////////////////////////////////////////////////// + // Precision Control // + ///////////////////////////////////////////////////////////////////////////// + + logic [C_PC-1:0] Precision_ctl_S; + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Precision_ctl_S<='b0; + end + else if(Start_SI&&Ready_SO) + begin + Precision_ctl_S<=Precision_ctl_SI; + end + else + begin + Precision_ctl_S<=Precision_ctl_S; + end + end + assign Full_precision_SO = (Precision_ctl_S==6'h00); + + + + logic [5:0] State_ctl_S; + logic [5:0] State_Two_iteration_unit_S; + logic [5:0] State_Four_iteration_unit_S; + + assign State_Two_iteration_unit_S = Precision_ctl_S[C_PC-1:1]; //Two iteration units + assign State_Four_iteration_unit_S = Precision_ctl_S[C_PC-1:2]; //Four iteration units + always_comb + begin + case(Iteration_unit_num_S) +//////////////////////one iteration unit, start/////////////////////////////////////// + 2'b00: //one iteration unit + begin + case(Format_sel_S) + 2'b00: //FP32 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h1b; //24+4 more iterations for rounding bits + end + else + begin + State_ctl_S = Precision_ctl_S; + end + end + 2'b01: //FP64 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h38; //53+4 more iterations for rounding bits + end + else + begin + State_ctl_S = Precision_ctl_S; + end + end + 2'b10: //FP16 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h0e; //11+4 more iterations for rounding bits + end + else + begin + State_ctl_S = Precision_ctl_S; + end + end + 2'b11: //FP16ALT + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h0b; //8+4 more iterations for rounding bits + end + else + begin + State_ctl_S = Precision_ctl_S; + end + end + endcase + end +//////////////////////one iteration unit, end/////////////////////////////////////// + +//////////////////////two iteration units, start/////////////////////////////////////// + 2'b01: //two iteration units + begin + case(Format_sel_S) + 2'b00: //FP32 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h0d; //24+4 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Two_iteration_unit_S; + end + end + 2'b01: //FP64 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h1b; //53+3 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Two_iteration_unit_S; + end + end + 2'b10: //FP16 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h06; //11+3 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Two_iteration_unit_S; + end + end + 2'b11: //FP16ALT + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h05; //8+4 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Two_iteration_unit_S; + end + end + endcase + end +//////////////////////two iteration units, end/////////////////////////////////////// + +//////////////////////three iteration units, start/////////////////////////////////////// + 2'b10: //three iteration units + begin + case(Format_sel_S) + 2'b00: //FP32 + begin + case(Precision_ctl_S) + 6'h00: + begin + State_ctl_S = 6'h08; //24+3 more iterations for rounding bits + end + 6'h06,6'h07,6'h08: + begin + State_ctl_S = 6'h02; + end + 6'h09,6'h0a,6'h0b: + begin + State_ctl_S = 6'h03; + end + 6'h0c,6'h0d,6'h0e: + begin + State_ctl_S = 6'h04; + end + 6'h0f,6'h10,6'h11: + begin + State_ctl_S = 6'h05; + end + 6'h12,6'h13,6'h14: + begin + State_ctl_S = 6'h06; + end + 6'h15,6'h16,6'h17: + begin + State_ctl_S = 6'h07; + end + default: + begin + State_ctl_S = 6'h08; //24+3 more iterations for rounding bits + end + endcase + end + 2'b01: //FP64 + begin + case(Precision_ctl_S) + 6'h00: + begin + State_ctl_S = 6'h12; //53+4 more iterations for rounding bits + end + 6'h06,6'h07,6'h08: + begin + State_ctl_S = 6'h02; + end + 6'h09,6'h0a,6'h0b: + begin + State_ctl_S = 6'h03; + end + 6'h0c,6'h0d,6'h0e: + begin + State_ctl_S = 6'h04; + end + 6'h0f,6'h10,6'h11: + begin + State_ctl_S = 6'h05; + end + 6'h12,6'h13,6'h14: + begin + State_ctl_S = 6'h06; + end + 6'h15,6'h16,6'h17: + begin + State_ctl_S = 6'h07; + end + 6'h18,6'h19,6'h1a: + begin + State_ctl_S = 6'h08; + end + 6'h1b,6'h1c,6'h1d: + begin + State_ctl_S = 6'h09; + end + 6'h1e,6'h1f,6'h20: + begin + State_ctl_S = 6'h0a; + end + 6'h21,6'h22,6'h23: + begin + State_ctl_S = 6'h0b; + end + 6'h24,6'h25,6'h26: + begin + State_ctl_S = 6'h0c; + end + 6'h27,6'h28,6'h29: + begin + State_ctl_S = 6'h0d; + end + 6'h2a,6'h2b,6'h2c: + begin + State_ctl_S = 6'h0e; + end + 6'h2d,6'h2e,6'h2f: + begin + State_ctl_S = 6'h0f; + end + 6'h30,6'h31,6'h32: + begin + State_ctl_S = 6'h10; + end + 6'h33,6'h34,6'h35: + begin + State_ctl_S = 6'h11; + end + default: + begin + State_ctl_S = 6'h12; //53+4 more iterations for rounding bits + end + endcase + end + 2'b10: //FP16 + begin + case(Precision_ctl_S) + 6'h00: + begin + State_ctl_S = 6'h04; //12+3 more iterations for rounding bits + end + 6'h06,6'h07,6'h08: + begin + State_ctl_S = 6'h02; + end + 6'h09,6'h0a,6'h0b: + begin + State_ctl_S = 6'h03; + end + default: + begin + State_ctl_S = 6'h04; //12+3 more iterations for rounding bits + end + endcase + end + 2'b11: //FP16ALT + begin + case(Precision_ctl_S) + 6'h00: + begin + State_ctl_S = 6'h03; //8+4 more iterations for rounding bits + end + 6'h06,6'h07,6'h08: + begin + State_ctl_S = 6'h02; + end + default: + begin + State_ctl_S = 6'h03; //8+4 more iterations for rounding bits + end + endcase + end + endcase + end +//////////////////////three iteration units, end/////////////////////////////////////// + +//////////////////////four iteration units, start/////////////////////////////////////// + 2'b11: //four iteration units + begin + case(Format_sel_S) + 2'b00: //FP32 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h06; //24+4 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Four_iteration_unit_S; + end + end + 2'b01: //FP64 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h0d; //53+3 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Four_iteration_unit_S; + end + end + 2'b10: //FP16 + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h03; //11+4 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Four_iteration_unit_S; + end + end + 2'b11: //FP16ALT + begin + if(Full_precision_SO) + begin + State_ctl_S = 6'h02; //8+4 more iterations for rounding bits + end + else + begin + State_ctl_S = State_Four_iteration_unit_S; + end + end + endcase + end +//////////////////////four iteration units, end/////////////////////////////////////// + + endcase + end + + + ///////////////////////////////////////////////////////////////////////////// + // control logic // + ///////////////////////////////////////////////////////////////////////////// + + logic Div_start_dly_S; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Div_start_dly_S signal + begin + if(~Rst_RBI) + begin + Div_start_dly_S<=1'b0; + end + else if(Div_start_SI&&Ready_SO) + begin + Div_start_dly_S<=1'b1; + end + else + begin + Div_start_dly_S<=1'b0; + end + end + + assign Div_start_dly_SO=Div_start_dly_S; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Div_enable_SO signal + if(~Rst_RBI) + Div_enable_SO<=1'b0; + // Synchronous reset with Flush + else if (Kill_SI) + Div_enable_SO <= 1'b0; + else if(Div_start_SI&&Ready_SO) + Div_enable_SO<=1'b1; + else if(Done_SO) + Div_enable_SO<=1'b0; + else + Div_enable_SO<=Div_enable_SO; + end + + logic Sqrt_start_dly_S; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) // generate Sqrt_start_dly_SI signal + begin + if(~Rst_RBI) + begin + Sqrt_start_dly_S<=1'b0; + end + else if(Sqrt_start_SI&&Ready_SO) + begin + Sqrt_start_dly_S<=1'b1; + end + else + begin + Sqrt_start_dly_S<=1'b0; + end + end + assign Sqrt_start_dly_SO=Sqrt_start_dly_S; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) begin // generate Sqrt_enable_SO signal + if(~Rst_RBI) + Sqrt_enable_SO<=1'b0; + else if (Kill_SI) + Sqrt_enable_SO <= 1'b0; + else if(Sqrt_start_SI&&Ready_SO) + Sqrt_enable_SO<=1'b1; + else if(Done_SO) + Sqrt_enable_SO<=1'b0; + else + Sqrt_enable_SO<=Sqrt_enable_SO; + end + + logic [5:0] Crtl_cnt_S; + logic Start_dly_S; + + assign Start_dly_S=Div_start_dly_S |Sqrt_start_dly_S; + + logic Fsm_enable_S; + assign Fsm_enable_S=( (Start_dly_S | (| Crtl_cnt_S)) && (~Kill_SI) && Special_case_dly_SBI); + + logic Final_state_S; + assign Final_state_S= (Crtl_cnt_S==State_ctl_S); + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) //control_FSM + begin + if (~Rst_RBI) + begin + Crtl_cnt_S <= '0; + end + else if (Final_state_S | Kill_SI) + begin + Crtl_cnt_S <= '0; + end + else if(Fsm_enable_S) // one cycle Start_SI + begin + Crtl_cnt_S <= Crtl_cnt_S+1; + end + else + begin + Crtl_cnt_S <= '0; + end + end // always_ff + + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Done_SO, they can share this Done_SO. + begin + if(~Rst_RBI) + begin + Done_SO<=1'b0; + end + else if(Start_SI&&Ready_SO) + begin + if(~Special_case_SBI) + begin + Done_SO<=1'b1; + end + else + begin + Done_SO<=1'b0; + end + end + else if(Final_state_S) + begin + Done_SO<=1'b1; + end + else + begin + Done_SO<=1'b0; + end + end + + + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) //Generate Ready_SO + begin + if(~Rst_RBI) + begin + Ready_SO<=1'b1; + end + + else if(Start_SI&&Ready_SO) + begin + if(~Special_case_SBI) + begin + Ready_SO<=1'b1; + end + else + begin + Ready_SO<=1'b0; + end + end + else if(Final_state_S | Kill_SI) + begin + Ready_SO<=1'b1; + end + else + begin + Ready_SO<=Ready_SO; + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b00, start // + //////////////////////////////////////////////////////////////////////////// + + logic Qcnt_one_0; + logic Qcnt_one_1; + logic [1:0] Qcnt_one_2; + logic [2:0] Qcnt_one_3; + logic [3:0] Qcnt_one_4; + logic [4:0] Qcnt_one_5; + logic [5:0] Qcnt_one_6; + logic [6:0] Qcnt_one_7; + logic [7:0] Qcnt_one_8; + logic [8:0] Qcnt_one_9; + logic [9:0] Qcnt_one_10; + logic [10:0] Qcnt_one_11; + logic [11:0] Qcnt_one_12; + logic [12:0] Qcnt_one_13; + logic [13:0] Qcnt_one_14; + logic [14:0] Qcnt_one_15; + logic [15:0] Qcnt_one_16; + logic [16:0] Qcnt_one_17; + logic [17:0] Qcnt_one_18; + logic [18:0] Qcnt_one_19; + logic [19:0] Qcnt_one_20; + logic [20:0] Qcnt_one_21; + logic [21:0] Qcnt_one_22; + logic [22:0] Qcnt_one_23; + logic [23:0] Qcnt_one_24; + logic [24:0] Qcnt_one_25; + logic [25:0] Qcnt_one_26; + logic [26:0] Qcnt_one_27; + logic [27:0] Qcnt_one_28; + logic [28:0] Qcnt_one_29; + logic [29:0] Qcnt_one_30; + logic [30:0] Qcnt_one_31; + logic [31:0] Qcnt_one_32; + logic [32:0] Qcnt_one_33; + logic [33:0] Qcnt_one_34; + logic [34:0] Qcnt_one_35; + logic [35:0] Qcnt_one_36; + logic [36:0] Qcnt_one_37; + logic [37:0] Qcnt_one_38; + logic [38:0] Qcnt_one_39; + logic [39:0] Qcnt_one_40; + logic [40:0] Qcnt_one_41; + logic [41:0] Qcnt_one_42; + logic [42:0] Qcnt_one_43; + logic [43:0] Qcnt_one_44; + logic [44:0] Qcnt_one_45; + logic [45:0] Qcnt_one_46; + logic [46:0] Qcnt_one_47; + logic [47:0] Qcnt_one_48; + logic [48:0] Qcnt_one_49; + logic [49:0] Qcnt_one_50; + logic [50:0] Qcnt_one_51; + logic [51:0] Qcnt_one_52; + logic [52:0] Qcnt_one_53; + logic [53:0] Qcnt_one_54; + logic [54:0] Qcnt_one_55; + logic [55:0] Qcnt_one_56; + logic [56:0] Qcnt_one_57; + logic [57:0] Qcnt_one_58; + logic [58:0] Qcnt_one_59; + logic [59:0] Qcnt_one_60; + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b00, end // + //////////////////////////////////////////////////////////////////////////// + + + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b01, start // + //////////////////////////////////////////////////////////////////////////// + logic [1:0] Qcnt_two_0; + logic [2:0] Qcnt_two_1; + logic [4:0] Qcnt_two_2; + logic [6:0] Qcnt_two_3; + logic [8:0] Qcnt_two_4; + logic [10:0] Qcnt_two_5; + logic [12:0] Qcnt_two_6; + logic [14:0] Qcnt_two_7; + logic [16:0] Qcnt_two_8; + logic [18:0] Qcnt_two_9; + logic [20:0] Qcnt_two_10; + logic [22:0] Qcnt_two_11; + logic [24:0] Qcnt_two_12; + logic [26:0] Qcnt_two_13; + logic [28:0] Qcnt_two_14; + logic [30:0] Qcnt_two_15; + logic [32:0] Qcnt_two_16; + logic [34:0] Qcnt_two_17; + logic [36:0] Qcnt_two_18; + logic [38:0] Qcnt_two_19; + logic [40:0] Qcnt_two_20; + logic [42:0] Qcnt_two_21; + logic [44:0] Qcnt_two_22; + logic [46:0] Qcnt_two_23; + logic [48:0] Qcnt_two_24; + logic [50:0] Qcnt_two_25; + logic [52:0] Qcnt_two_26; + logic [54:0] Qcnt_two_27; + logic [56:0] Qcnt_two_28; + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b01, end // + //////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b10, start // + //////////////////////////////////////////////////////////////////////////// + logic [2:0] Qcnt_three_0; + logic [4:0] Qcnt_three_1; + logic [7:0] Qcnt_three_2; + logic [10:0] Qcnt_three_3; + logic [13:0] Qcnt_three_4; + logic [16:0] Qcnt_three_5; + logic [19:0] Qcnt_three_6; + logic [22:0] Qcnt_three_7; + logic [25:0] Qcnt_three_8; + logic [28:0] Qcnt_three_9; + logic [31:0] Qcnt_three_10; + logic [34:0] Qcnt_three_11; + logic [37:0] Qcnt_three_12; + logic [40:0] Qcnt_three_13; + logic [43:0] Qcnt_three_14; + logic [46:0] Qcnt_three_15; + logic [49:0] Qcnt_three_16; + logic [52:0] Qcnt_three_17; + logic [55:0] Qcnt_three_18; + logic [58:0] Qcnt_three_19; + logic [61:0] Qcnt_three_20; + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b10, end // + //////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b11, start // + //////////////////////////////////////////////////////////////////////////// + logic [3:0] Qcnt_four_0; + logic [6:0] Qcnt_four_1; + logic [10:0] Qcnt_four_2; + logic [14:0] Qcnt_four_3; + logic [18:0] Qcnt_four_4; + logic [22:0] Qcnt_four_5; + logic [26:0] Qcnt_four_6; + logic [30:0] Qcnt_four_7; + logic [34:0] Qcnt_four_8; + logic [38:0] Qcnt_four_9; + logic [42:0] Qcnt_four_10; + logic [46:0] Qcnt_four_11; + logic [50:0] Qcnt_four_12; + logic [54:0] Qcnt_four_13; + logic [58:0] Qcnt_four_14; + + ///////////////////////////////////////////////////////////////////////////// + // Declarations for square root when Iteration_unit_num_S = 2'b11, end // + //////////////////////////////////////////////////////////////////////////// + + + + logic [C_MANT_FP64+1+4:0] Sqrt_R0,Sqrt_Q0,Q_sqrt0,Q_sqrt_com_0; + logic [C_MANT_FP64+1+4:0] Sqrt_R1,Sqrt_Q1,Q_sqrt1,Q_sqrt_com_1; + logic [C_MANT_FP64+1+4:0] Sqrt_R2,Sqrt_Q2,Q_sqrt2,Q_sqrt_com_2; + logic [C_MANT_FP64+1+4:0] Sqrt_R3,Sqrt_Q3,Q_sqrt3,Q_sqrt_com_3,Sqrt_R4; //Sqrt_Q4; + + + logic [1:0] Sqrt_DI [3:0]; + logic [1:0] Sqrt_DO [3:0]; + logic Sqrt_carry_DO; + + + logic [C_MANT_FP64+1+4:0] Iteration_cell_a_D [3:0]; + logic [C_MANT_FP64+1+4:0] Iteration_cell_b_D [3:0]; + logic [C_MANT_FP64+1+4:0] Iteration_cell_a_BMASK_D [3:0]; + logic [C_MANT_FP64+1+4:0] Iteration_cell_b_BMASK_D [3:0]; + logic Iteration_cell_carry_D [3:0]; + logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_D [3:0]; + logic [C_MANT_FP64+1+4:0] Iteration_cell_sum_AMASK_D [3:0]; + + + logic [3:0] Sqrt_quotinent_S; + + + always_comb + begin // + case (Format_sel_S) + 2'b00: + begin + Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP32+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP32+5])}; + Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt0[C_MANT_FP32+5:0] }; + Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt1[C_MANT_FP32+5:0] }; + Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt2[C_MANT_FP32+5:0] }; + Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP32){1'b0}},~Q_sqrt3[C_MANT_FP32+5:0] }; + end + 2'b01: + begin + Sqrt_quotinent_S = {Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; + Q_sqrt_com_0=~Q_sqrt0; + Q_sqrt_com_1=~Q_sqrt1; + Q_sqrt_com_2=~Q_sqrt2; + Q_sqrt_com_3=~Q_sqrt3; + end + 2'b10: + begin + Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16+5])}; + Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt0[C_MANT_FP16+5:0] }; + Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt1[C_MANT_FP16+5:0] }; + Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt2[C_MANT_FP16+5:0] }; + Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16){1'b0}},~Q_sqrt3[C_MANT_FP16+5:0] }; + end + 2'b11: + begin + Sqrt_quotinent_S = {(~Iteration_cell_sum_AMASK_D[0][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[1][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[2][C_MANT_FP16ALT+5]),(~Iteration_cell_sum_AMASK_D[3][C_MANT_FP16ALT+5])}; + Q_sqrt_com_0 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt0[C_MANT_FP16ALT+5:0] }; + Q_sqrt_com_1 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt1[C_MANT_FP16ALT+5:0] }; + Q_sqrt_com_2 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt2[C_MANT_FP16ALT+5:0] }; + Q_sqrt_com_3 ={ {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}},~Q_sqrt3[C_MANT_FP16ALT+5:0] }; + end + endcase + end + + + + assign Qcnt_one_0= {1'b0}; //qk for each feedback + assign Qcnt_one_1= {Quotient_DP[0]}; + assign Qcnt_one_2= {Quotient_DP[1:0]}; + assign Qcnt_one_3= {Quotient_DP[2:0]}; + assign Qcnt_one_4= {Quotient_DP[3:0]}; + assign Qcnt_one_5= {Quotient_DP[4:0]}; + assign Qcnt_one_6= {Quotient_DP[5:0]}; + assign Qcnt_one_7= {Quotient_DP[6:0]}; + assign Qcnt_one_8= {Quotient_DP[7:0]}; + assign Qcnt_one_9= {Quotient_DP[8:0]}; + assign Qcnt_one_10= {Quotient_DP[9:0]}; + assign Qcnt_one_11= {Quotient_DP[10:0]}; + assign Qcnt_one_12= {Quotient_DP[11:0]}; + assign Qcnt_one_13= {Quotient_DP[12:0]}; + assign Qcnt_one_14= {Quotient_DP[13:0]}; + assign Qcnt_one_15= {Quotient_DP[14:0]}; + assign Qcnt_one_16= {Quotient_DP[15:0]}; + assign Qcnt_one_17= {Quotient_DP[16:0]}; + assign Qcnt_one_18= {Quotient_DP[17:0]}; + assign Qcnt_one_19= {Quotient_DP[18:0]}; + assign Qcnt_one_20= {Quotient_DP[19:0]}; + assign Qcnt_one_21= {Quotient_DP[20:0]}; + assign Qcnt_one_22= {Quotient_DP[21:0]}; + assign Qcnt_one_23= {Quotient_DP[22:0]}; + assign Qcnt_one_24= {Quotient_DP[23:0]}; + assign Qcnt_one_25= {Quotient_DP[24:0]}; + assign Qcnt_one_26= {Quotient_DP[25:0]}; + assign Qcnt_one_27= {Quotient_DP[26:0]}; + assign Qcnt_one_28= {Quotient_DP[27:0]}; + assign Qcnt_one_29= {Quotient_DP[28:0]}; + assign Qcnt_one_30= {Quotient_DP[29:0]}; + assign Qcnt_one_31= {Quotient_DP[30:0]}; + assign Qcnt_one_32= {Quotient_DP[31:0]}; + assign Qcnt_one_33= {Quotient_DP[32:0]}; + assign Qcnt_one_34= {Quotient_DP[33:0]}; + assign Qcnt_one_35= {Quotient_DP[34:0]}; + assign Qcnt_one_36= {Quotient_DP[35:0]}; + assign Qcnt_one_37= {Quotient_DP[36:0]}; + assign Qcnt_one_38= {Quotient_DP[37:0]}; + assign Qcnt_one_39= {Quotient_DP[38:0]}; + assign Qcnt_one_40= {Quotient_DP[39:0]}; + assign Qcnt_one_41= {Quotient_DP[40:0]}; + assign Qcnt_one_42= {Quotient_DP[41:0]}; + assign Qcnt_one_43= {Quotient_DP[42:0]}; + assign Qcnt_one_44= {Quotient_DP[43:0]}; + assign Qcnt_one_45= {Quotient_DP[44:0]}; + assign Qcnt_one_46= {Quotient_DP[45:0]}; + assign Qcnt_one_47= {Quotient_DP[46:0]}; + assign Qcnt_one_48= {Quotient_DP[47:0]}; + assign Qcnt_one_49= {Quotient_DP[48:0]}; + assign Qcnt_one_50= {Quotient_DP[49:0]}; + assign Qcnt_one_51= {Quotient_DP[50:0]}; + assign Qcnt_one_52= {Quotient_DP[51:0]}; + assign Qcnt_one_53= {Quotient_DP[52:0]}; + assign Qcnt_one_54= {Quotient_DP[53:0]}; + assign Qcnt_one_55= {Quotient_DP[54:0]}; + assign Qcnt_one_56= {Quotient_DP[55:0]}; + assign Qcnt_one_57= {Quotient_DP[56:0]}; + + + assign Qcnt_two_0 = {1'b0, Sqrt_quotinent_S[3]}; //qk for each feedback + assign Qcnt_two_1 = {Quotient_DP[1:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_2 = {Quotient_DP[3:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_3 = {Quotient_DP[5:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_4 = {Quotient_DP[7:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_5 = {Quotient_DP[9:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_6 = {Quotient_DP[11:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_7 = {Quotient_DP[13:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_8 = {Quotient_DP[15:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_9 = {Quotient_DP[17:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_10 = {Quotient_DP[19:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_11 = {Quotient_DP[21:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_12 = {Quotient_DP[23:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_13 = {Quotient_DP[25:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_14 = {Quotient_DP[27:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_15 = {Quotient_DP[29:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_16 = {Quotient_DP[31:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_17 = {Quotient_DP[33:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_18 = {Quotient_DP[35:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_19 = {Quotient_DP[37:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_20 = {Quotient_DP[39:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_21 = {Quotient_DP[41:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_22 = {Quotient_DP[43:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_23 = {Quotient_DP[45:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_24 = {Quotient_DP[47:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_25 = {Quotient_DP[49:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_26 = {Quotient_DP[51:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_27 = {Quotient_DP[53:0],Sqrt_quotinent_S[3]}; + assign Qcnt_two_28 = {Quotient_DP[55:0],Sqrt_quotinent_S[3]}; + + + assign Qcnt_three_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; //qk for each feedback + assign Qcnt_three_1 = {Quotient_DP[2:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_2 = {Quotient_DP[5:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_3 = {Quotient_DP[8:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_4 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_5 = {Quotient_DP[14:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_6 = {Quotient_DP[17:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_7 = {Quotient_DP[20:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_8 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_9 = {Quotient_DP[26:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_10 = {Quotient_DP[29:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_11 = {Quotient_DP[32:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_12 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_13 = {Quotient_DP[38:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_14 = {Quotient_DP[41:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_15 = {Quotient_DP[44:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_16 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_17 = {Quotient_DP[50:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_18 = {Quotient_DP[53:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + assign Qcnt_three_19 = {Quotient_DP[56:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2]}; + + + assign Qcnt_four_0 = {1'b0, Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_1 = {Quotient_DP[3:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_2 = {Quotient_DP[7:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_3 = {Quotient_DP[11:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_4 = {Quotient_DP[15:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_5 = {Quotient_DP[19:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_6 = {Quotient_DP[23:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_7 = {Quotient_DP[27:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_8 = {Quotient_DP[31:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_9 = {Quotient_DP[35:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_10 = {Quotient_DP[39:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_11 = {Quotient_DP[43:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_12 = {Quotient_DP[47:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_13 = {Quotient_DP[51:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + assign Qcnt_four_14 = {Quotient_DP[55:0],Sqrt_quotinent_S[3],Sqrt_quotinent_S[2],Sqrt_quotinent_S[1]}; + + + + + always_comb begin // the intermediate operands for sqrt + + case(Iteration_unit_num_S) + 2'b00: + begin + + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b00, start // + ///////////////////////////////////////////////////////////////////////////// + + + + + case(Crtl_cnt_S) + + 6'b000000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_0}; + Sqrt_Q0=Q_sqrt_com_0; + end + 6'b000001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_one_1}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_one_2}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; + Q_sqrt0={{(C_MANT_FP64+3){1'b0}},Qcnt_one_3}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; + Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_one_4}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; + Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_one_5}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; + Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_one_6}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b000111: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; + Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_one_7}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; + Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_one_8}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; + Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_one_9}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; + Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_one_10}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; + Q_sqrt0={{(C_MANT_FP64-5){1'b0}},Qcnt_one_11}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; + Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_one_12}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; + Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_one_13}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; + Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_one_14}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b001111: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; + Q_sqrt0={{(C_MANT_FP64-9){1'b0}},Qcnt_one_15}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; + Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_one_16}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; + Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_one_17}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; + Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_one_18}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; + Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_one_19}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; + Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_one_20}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; + Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_one_21}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; + Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_one_22}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b010111: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; + Q_sqrt0={{(C_MANT_FP64-17){1'b0}},Qcnt_one_23}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; + Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_one_24}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; + Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_one_25}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; + Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_one_26}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-21){1'b0}},Qcnt_one_27}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_one_28}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_one_29}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_one_30}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b011111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_one_31}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_one_32}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_one_33}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_one_34}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-29){1'b0}},Qcnt_one_35}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_one_36}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_one_37}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_one_38}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b100111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-33){1'b0}},Qcnt_one_39}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_one_40}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_one_41}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_one_42}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_one_43}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_one_44}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_one_45}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_one_46}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b101111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-41){1'b0}},Qcnt_one_47}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_one_48}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_one_49}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_one_50}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-45){1'b0}},Qcnt_one_51}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_one_52}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_one_53}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_one_54}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b110111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_one_55}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + 6'b111000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_one_56}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + end + + default: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0='0; + Sqrt_Q0='0; + end + endcase + end + + + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b00, end // + ///////////////////////////////////////////////////////////////////////////// + + + 2'b01: + begin + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b01, start // + ///////////////////////////////////////////////////////////////////////////// + case(Crtl_cnt_S) + + 6'b000000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt0={{(C_MANT_FP64+4){1'b0}},Qcnt_two_1[2:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; + Q_sqrt1={{(C_MANT_FP64+3){1'b0}},Qcnt_two_1[2:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; + Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_two_2[4:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; + Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_two_2[4:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; + Q_sqrt0={{(C_MANT_FP64){1'b0}},Qcnt_two_3[6:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; + Q_sqrt1={{(C_MANT_FP64-1){1'b0}},Qcnt_two_3[6:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; + Q_sqrt0={{(C_MANT_FP64-2){1'b0}},Qcnt_two_4[8:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; + Q_sqrt1={{(C_MANT_FP64-3){1'b0}},Qcnt_two_4[8:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; + Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_two_5[10:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; + Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_two_5[10:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; + Q_sqrt0={{(C_MANT_FP64-6){1'b0}},Qcnt_two_6[12:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; + Q_sqrt1={{(C_MANT_FP64-7){1'b0}},Qcnt_two_6[12:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b000111: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; + Q_sqrt0={{(C_MANT_FP64-8){1'b0}},Qcnt_two_7[14:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; + Q_sqrt1={{(C_MANT_FP64-9){1'b0}},Qcnt_two_7[14:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; + Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_two_8[16:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; + Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_two_8[16:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; + Q_sqrt0={{(C_MANT_FP64-12){1'b0}},Qcnt_two_9[18:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; + Q_sqrt1={{(C_MANT_FP64-13){1'b0}},Qcnt_two_9[18:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; + Q_sqrt0={{(C_MANT_FP64-14){1'b0}},Qcnt_two_10[20:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; + Q_sqrt1={{(C_MANT_FP64-15){1'b0}},Qcnt_two_10[20:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; + Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_two_11[22:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; + Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_two_11[22:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; + Q_sqrt0={{(C_MANT_FP64-18){1'b0}},Qcnt_two_12[24:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; + Q_sqrt1={{(C_MANT_FP64-19){1'b0}},Qcnt_two_12[24:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; + Q_sqrt0={{(C_MANT_FP64-20){1'b0}},Qcnt_two_13[26:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-21){1'b0}},Qcnt_two_13[26:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_two_14[28:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_two_14[28:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b001111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-24){1'b0}},Qcnt_two_15[30:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-25){1'b0}},Qcnt_two_15[30:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-26){1'b0}},Qcnt_two_16[32:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-27){1'b0}},Qcnt_two_16[32:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_two_17[34:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_two_17[34:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-30){1'b0}},Qcnt_two_18[36:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-31){1'b0}},Qcnt_two_18[36:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-32){1'b0}},Qcnt_two_19[38:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-33){1'b0}},Qcnt_two_19[38:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_two_20[40:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_two_20[40:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-36){1'b0}},Qcnt_two_21[42:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-37){1'b0}},Qcnt_two_21[42:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-38){1'b0}},Qcnt_two_22[44:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-39){1'b0}},Qcnt_two_22[44:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b010111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_two_23[46:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_two_23[46:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b011000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-42){1'b0}},Qcnt_two_24[48:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-43){1'b0}},Qcnt_two_24[48:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b011001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-44){1'b0}},Qcnt_two_25[50:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-45){1'b0}},Qcnt_two_25[50:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b011010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_two_26[52:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_two_26[52:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b011011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-48){1'b0}},Qcnt_two_27[54:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-49){1'b0}},Qcnt_two_27[54:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + 6'b011100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-50){1'b0}},Qcnt_two_28[56:1]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-51){1'b0}},Qcnt_two_28[56:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + default: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_two_0[1]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_two_0[1:0]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + end + + endcase + end + + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b01, end // + ///////////////////////////////////////////////////////////////////////////// + + + 2'b10: + begin + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b10, start // + ///////////////////////////////////////////////////////////////////////////// + + case(Crtl_cnt_S) + 6'b000000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; + Q_sqrt0={{(C_MANT_FP64+2){1'b0}},Qcnt_three_1[4:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; + Q_sqrt1={{(C_MANT_FP64+1){1'b0}},Qcnt_three_1[4:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; + Q_sqrt2={{(C_MANT_FP64){1'b0}},Qcnt_three_1[4:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; + Q_sqrt0={{(C_MANT_FP64-1){1'b0}},Qcnt_three_2[7:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; + Q_sqrt1={{(C_MANT_FP64-2){1'b0}},Qcnt_three_2[7:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; + Q_sqrt2={{(C_MANT_FP64-3){1'b0}},Qcnt_three_2[7:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; + Q_sqrt0={{(C_MANT_FP64-4){1'b0}},Qcnt_three_3[10:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; + Q_sqrt1={{(C_MANT_FP64-5){1'b0}},Qcnt_three_3[10:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; + Q_sqrt2={{(C_MANT_FP64-6){1'b0}},Qcnt_three_3[10:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; + Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_three_4[13:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; + Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_three_4[13:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; + Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_three_4[13:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; + Q_sqrt0={{(C_MANT_FP64-10){1'b0}},Qcnt_three_5[16:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; + Q_sqrt1={{(C_MANT_FP64-11){1'b0}},Qcnt_three_5[16:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; + Q_sqrt2={{(C_MANT_FP64-12){1'b0}},Qcnt_three_5[16:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; + Q_sqrt0={{(C_MANT_FP64-13){1'b0}},Qcnt_three_6[19:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; + Q_sqrt1={{(C_MANT_FP64-14){1'b0}},Qcnt_three_6[19:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; + Q_sqrt2={{(C_MANT_FP64-15){1'b0}},Qcnt_three_6[19:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b000111: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; + Q_sqrt0={{(C_MANT_FP64-16){1'b0}},Qcnt_three_7[22:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; + Q_sqrt1={{(C_MANT_FP64-17){1'b0}},Qcnt_three_7[22:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; + Q_sqrt2={{(C_MANT_FP64-18){1'b0}},Qcnt_three_7[22:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; + Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_three_8[25:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; + Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_three_8[25:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; + Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_three_8[25:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-22){1'b0}},Qcnt_three_9[28:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-23){1'b0}},Qcnt_three_9[28:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-24){1'b0}},Qcnt_three_9[28:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-25){1'b0}},Qcnt_three_10[31:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-26){1'b0}},Qcnt_three_10[31:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-27){1'b0}},Qcnt_three_10[31:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-28){1'b0}},Qcnt_three_11[34:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-29){1'b0}},Qcnt_three_11[34:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-30){1'b0}},Qcnt_three_11[34:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_three_12[37:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_three_12[37:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_three_12[37:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-34){1'b0}},Qcnt_three_13[40:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-35){1'b0}},Qcnt_three_13[40:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-36){1'b0}},Qcnt_three_13[40:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001110: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-37){1'b0}},Qcnt_three_14[43:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-38){1'b0}},Qcnt_three_14[43:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-39){1'b0}},Qcnt_three_14[43:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b001111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-40){1'b0}},Qcnt_three_15[46:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-41){1'b0}},Qcnt_three_15[46:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-42){1'b0}},Qcnt_three_15[46:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b010000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_three_16[49:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_three_16[49:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_three_16[49:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b010001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-46){1'b0}},Qcnt_three_17[52:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-47){1'b0}},Qcnt_three_17[52:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-48){1'b0}},Qcnt_three_17[52:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + 6'b010010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-49){1'b0}},Qcnt_three_18[55:2]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-50){1'b0}},Qcnt_three_18[55:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-51){1'b0}},Qcnt_three_18[55:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + + default : + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_three_0[2]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_three_0[2:1]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_three_0[2:0]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + end + endcase + + end + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b10, end // + ///////////////////////////////////////////////////////////////////////////// + + + 2'b11: + begin + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b11, start // + ///////////////////////////////////////////////////////////////////////////// + + case(Crtl_cnt_S) + + 6'b000000: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; + Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000001: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-7:C_MANT_FP64-8]; + Q_sqrt0={{(C_MANT_FP64+1){1'b0}},Qcnt_four_1[6:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-9:C_MANT_FP64-10]; + Q_sqrt1={{(C_MANT_FP64){1'b0}},Qcnt_four_1[6:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-11:C_MANT_FP64-12]; + Q_sqrt2={{(C_MANT_FP64-1){1'b0}},Qcnt_four_1[6:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-13:C_MANT_FP64-14]; + Q_sqrt3={{(C_MANT_FP64-2){1'b0}},Qcnt_four_1[6:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000010: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-15:C_MANT_FP64-16]; + Q_sqrt0={{(C_MANT_FP64-3){1'b0}},Qcnt_four_2[10:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-17:C_MANT_FP64-18]; + Q_sqrt1={{(C_MANT_FP64-4){1'b0}},Qcnt_four_2[10:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-19:C_MANT_FP64-20]; + Q_sqrt2={{(C_MANT_FP64-5){1'b0}},Qcnt_four_2[10:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-21:C_MANT_FP64-22]; + Q_sqrt3={{(C_MANT_FP64-6){1'b0}},Qcnt_four_2[10:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000011: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-23:C_MANT_FP64-24]; + Q_sqrt0={{(C_MANT_FP64-7){1'b0}},Qcnt_four_3[14:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-25:C_MANT_FP64-26]; + Q_sqrt1={{(C_MANT_FP64-8){1'b0}},Qcnt_four_3[14:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-27:C_MANT_FP64-28]; + Q_sqrt2={{(C_MANT_FP64-9){1'b0}},Qcnt_four_3[14:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-29:C_MANT_FP64-30]; + Q_sqrt3={{(C_MANT_FP64-10){1'b0}},Qcnt_four_3[14:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000100: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-31:C_MANT_FP64-32]; + Q_sqrt0={{(C_MANT_FP64-11){1'b0}},Qcnt_four_4[18:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-33:C_MANT_FP64-34]; + Q_sqrt1={{(C_MANT_FP64-12){1'b0}},Qcnt_four_4[18:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-35:C_MANT_FP64-36]; + Q_sqrt2={{(C_MANT_FP64-13){1'b0}},Qcnt_four_4[18:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-37:C_MANT_FP64-38]; + Q_sqrt3={{(C_MANT_FP64-14){1'b0}},Qcnt_four_4[18:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000101: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-39:C_MANT_FP64-40]; + Q_sqrt0={{(C_MANT_FP64-15){1'b0}},Qcnt_four_5[22:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-41:C_MANT_FP64-42]; + Q_sqrt1={{(C_MANT_FP64-16){1'b0}},Qcnt_four_5[22:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-43:C_MANT_FP64-44]; + Q_sqrt2={{(C_MANT_FP64-17){1'b0}},Qcnt_four_5[22:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-45:C_MANT_FP64-46]; + Q_sqrt3={{(C_MANT_FP64-18){1'b0}},Qcnt_four_5[22:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000110: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64-47:C_MANT_FP64-48]; + Q_sqrt0={{(C_MANT_FP64-19){1'b0}},Qcnt_four_6[26:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-49:C_MANT_FP64-50]; + Q_sqrt1={{(C_MANT_FP64-20){1'b0}},Qcnt_four_6[26:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-51:C_MANT_FP64-52]; + Q_sqrt2={{(C_MANT_FP64-21){1'b0}},Qcnt_four_6[26:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-22){1'b0}},Qcnt_four_6[26:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b000111: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-23){1'b0}},Qcnt_four_7[30:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-24){1'b0}},Qcnt_four_7[30:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-25){1'b0}},Qcnt_four_7[30:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-26){1'b0}},Qcnt_four_7[30:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001000: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-27){1'b0}},Qcnt_four_8[34:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-28){1'b0}},Qcnt_four_8[34:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-29){1'b0}},Qcnt_four_8[34:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-30){1'b0}},Qcnt_four_8[34:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001001: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-31){1'b0}},Qcnt_four_9[38:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-32){1'b0}},Qcnt_four_9[38:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-33){1'b0}},Qcnt_four_9[38:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-34){1'b0}},Qcnt_four_9[38:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001010: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-35){1'b0}},Qcnt_four_10[42:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-36){1'b0}},Qcnt_four_10[42:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-37){1'b0}},Qcnt_four_10[42:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-38){1'b0}},Qcnt_four_10[42:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001011: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-39){1'b0}},Qcnt_four_11[46:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-40){1'b0}},Qcnt_four_11[46:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-41){1'b0}},Qcnt_four_11[46:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-42){1'b0}},Qcnt_four_11[46:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001100: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-43){1'b0}},Qcnt_four_12[50:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-44){1'b0}},Qcnt_four_12[50:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-45){1'b0}},Qcnt_four_12[50:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-46){1'b0}},Qcnt_four_12[50:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + 6'b001101: + begin + Sqrt_DI[0]=2'b00; + Q_sqrt0={{(C_MANT_FP64-47){1'b0}},Qcnt_four_13[54:3]}; + Sqrt_Q0=Quotient_DP[0]?Q_sqrt_com_0:Q_sqrt0; + Sqrt_DI[1]=2'b00; + Q_sqrt1={{(C_MANT_FP64-48){1'b0}},Qcnt_four_13[54:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=2'b00; + Q_sqrt2={{(C_MANT_FP64-49){1'b0}},Qcnt_four_13[54:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=2'b00; + Q_sqrt3={{(C_MANT_FP64-50){1'b0}},Qcnt_four_13[54:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + + default: + begin + Sqrt_DI[0]=Mant_D_sqrt_Norm[C_MANT_FP64+1:C_MANT_FP64]; + Q_sqrt0={{(C_MANT_FP64+5){1'b0}},Qcnt_four_0[3]}; + Sqrt_Q0=Q_sqrt_com_0; + Sqrt_DI[1]=Mant_D_sqrt_Norm[C_MANT_FP64-1:C_MANT_FP64-2]; + Q_sqrt1={{(C_MANT_FP64+4){1'b0}},Qcnt_four_0[3:2]}; + Sqrt_Q1=Sqrt_quotinent_S[3]?Q_sqrt_com_1:Q_sqrt1; + Sqrt_DI[2]=Mant_D_sqrt_Norm[C_MANT_FP64-3:C_MANT_FP64-4]; + Q_sqrt2={{(C_MANT_FP64+3){1'b0}},Qcnt_four_0[3:1]}; + Sqrt_Q2=Sqrt_quotinent_S[2]?Q_sqrt_com_2:Q_sqrt2; + Sqrt_DI[3]=Mant_D_sqrt_Norm[C_MANT_FP64-5:C_MANT_FP64-6]; + Q_sqrt3={{(C_MANT_FP64+2){1'b0}},Qcnt_four_0[3:0]}; + Sqrt_Q3=Sqrt_quotinent_S[1]?Q_sqrt_com_3:Q_sqrt3; + end + endcase + end + endcase + ///////////////////////////////////////////////////////////////////////////// + // Operands for square root when Iteration_unit_num_S = 2'b11, end // + ///////////////////////////////////////////////////////////////////////////// + end + + + + assign Sqrt_R0= ((Sqrt_start_dly_S)?'0:{Partial_remainder_DP[C_MANT_FP64+5:0]}); + assign Sqrt_R1= {Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+2:0],Sqrt_DO[0]} ; + assign Sqrt_R2= {Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+2:0],Sqrt_DO[1]}; + assign Sqrt_R3= {Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+2:0],Sqrt_DO[2]}; + assign Sqrt_R4= {Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+5],Iteration_cell_sum_AMASK_D[3][C_MANT_FP64+2:0],Sqrt_DO[3]}; + + logic [C_MANT_FP64+5:0] Denominator_se_format_DB; // + + assign Denominator_se_format_DB={Denominator_se_DB[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-1]}, + Denominator_se_DB[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-1]}, + Denominator_se_DB[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-1]}, + Denominator_se_DB[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} ; + // for iteration cell_U0 + logic [C_MANT_FP64+5:0] First_iteration_cell_div_a_D,First_iteration_cell_div_b_D; + logic Sel_b_for_first_S; + + + assign First_iteration_cell_div_a_D=(Div_start_dly_S)?{Numerator_se_D[C_MANT_FP64+1:C_MANT_FP64-C_MANT_FP16ALT],{FP16ALT_SO?FP16ALT_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-1]}, + Numerator_se_D[C_MANT_FP64-C_MANT_FP16ALT-2:C_MANT_FP64-C_MANT_FP16],{FP16_SO?FP16_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP16-1]}, + Numerator_se_D[C_MANT_FP64-C_MANT_FP16-2:C_MANT_FP64-C_MANT_FP32],{FP32_SO?FP32_SO:Numerator_se_D[C_MANT_FP64-C_MANT_FP32-1]}, + Numerator_se_D[C_MANT_FP64-C_MANT_FP32-2:C_MANT_FP64-C_MANT_FP64],FP64_SO,3'b0} + :{Partial_remainder_DP[C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+2]}, + Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+2]}, + Partial_remainder_DP[C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Quotient_DP[0]:Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+2]}, + Partial_remainder_DP[C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Quotient_DP[0],3'b0}; + assign Sel_b_for_first_S=(Div_start_dly_S)?1:Quotient_DP[0]; + assign First_iteration_cell_div_b_D=Sel_b_for_first_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; + assign Iteration_cell_a_BMASK_D[0]=Sqrt_enable_SO?Sqrt_R0:{First_iteration_cell_div_a_D}; + assign Iteration_cell_b_BMASK_D[0]=Sqrt_enable_SO?Sqrt_Q0:{First_iteration_cell_div_b_D}; + + + + // for iteration cell_U1 + logic [C_MANT_FP64+5:0] Sec_iteration_cell_div_a_D,Sec_iteration_cell_div_b_D; + logic Sel_b_for_sec_S; + generate + if(|Iteration_unit_num_S) + begin + assign Sel_b_for_sec_S=~Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+5]; + assign Sec_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[0][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+2]}, + Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+2]}, + Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_sec_S:Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+2]}, + Iteration_cell_sum_AMASK_D[0][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_sec_S,3'b0}; + assign Sec_iteration_cell_div_b_D=Sel_b_for_sec_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; + assign Iteration_cell_a_BMASK_D[1]=Sqrt_enable_SO?Sqrt_R1:{Sec_iteration_cell_div_a_D}; + assign Iteration_cell_b_BMASK_D[1]=Sqrt_enable_SO?Sqrt_Q1:{Sec_iteration_cell_div_b_D}; + end + endgenerate + + // for iteration cell_U2 + logic [C_MANT_FP64+5:0] Thi_iteration_cell_div_a_D,Thi_iteration_cell_div_b_D; + logic Sel_b_for_thi_S; + generate + if((Iteration_unit_num_S==2'b10) | (Iteration_unit_num_S==2'b11)) + begin + assign Sel_b_for_thi_S=~Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+5]; + assign Thi_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[1][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+2]}, + Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+2]}, + Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_thi_S:Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+2]}, + Iteration_cell_sum_AMASK_D[1][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_thi_S,3'b0}; + assign Thi_iteration_cell_div_b_D=Sel_b_for_thi_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; + assign Iteration_cell_a_BMASK_D[2]=Sqrt_enable_SO?Sqrt_R2:{Thi_iteration_cell_div_a_D}; + assign Iteration_cell_b_BMASK_D[2]=Sqrt_enable_SO?Sqrt_Q2:{Thi_iteration_cell_div_b_D}; + end + endgenerate + + // for iteration cell_U3 + logic [C_MANT_FP64+5:0] Fou_iteration_cell_div_a_D,Fou_iteration_cell_div_b_D; + logic Sel_b_for_fou_S; + + generate + if(Iteration_unit_num_S==2'b11) + begin + assign Sel_b_for_fou_S=~Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+5]; + assign Fou_iteration_cell_div_a_D={Iteration_cell_sum_AMASK_D[2][C_MANT_FP64+4:C_MANT_FP64-C_MANT_FP16ALT+3],{FP16ALT_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+2]}, + Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16ALT+1:C_MANT_FP64-C_MANT_FP16+3],{FP16_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+2]}, + Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP16+1:C_MANT_FP64-C_MANT_FP32+3],{FP32_SO?Sel_b_for_fou_S:Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+2]}, + Iteration_cell_sum_AMASK_D[2][C_MANT_FP64-C_MANT_FP32+1:C_MANT_FP64-C_MANT_FP64+3],FP64_SO&&Sel_b_for_fou_S,3'b0}; + assign Fou_iteration_cell_div_b_D=Sel_b_for_fou_S?Denominator_se_format_DB:{Denominator_se_D,4'b0}; + assign Iteration_cell_a_BMASK_D[3]=Sqrt_enable_SO?Sqrt_R3:{Fou_iteration_cell_div_a_D}; + assign Iteration_cell_b_BMASK_D[3]=Sqrt_enable_SO?Sqrt_Q3:{Fou_iteration_cell_div_b_D}; + end + endgenerate + + ///////////////////////////////////////////////////////////////////////////// + // Masking Contrl // + ///////////////////////////////////////////////////////////////////////////// + + + logic [C_MANT_FP64+1+4:0] Mask_bits_ctl_S; //For extension + + assign Mask_bits_ctl_S =58'h3ff_ffff_ffff_ffff; //It is not needed. The corresponding process is handled the above codes + + ///////////////////////////////////////////////////////////////////////////// + // Iteration Instances with masking control // + ///////////////////////////////////////////////////////////////////////////// + + + logic Div_enable_SI [3:0]; + logic Div_start_dly_SI [3:0]; + logic Sqrt_enable_SI [3:0]; + generate + genvar i,j; + for (i=0; i <= Iteration_unit_num_S ; i++) + begin + for (j = 0; j <= C_MANT_FP64+5; j++) begin + assign Iteration_cell_a_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_a_BMASK_D[i][j]; + assign Iteration_cell_b_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_b_BMASK_D[i][j]; + assign Iteration_cell_sum_AMASK_D[i][j] = Mask_bits_ctl_S[j] && Iteration_cell_sum_D[i][j]; + end + + assign Div_enable_SI[i] = Div_enable_SO; + assign Div_start_dly_SI[i] = Div_start_dly_S; + assign Sqrt_enable_SI[i] = Sqrt_enable_SO; + iteration_div_sqrt_mvp #(C_MANT_FP64+6) iteration_div_sqrt + ( + .A_DI (Iteration_cell_a_D[i] ), + .B_DI (Iteration_cell_b_D[i] ), + .Div_enable_SI (Div_enable_SI[i] ), + .Div_start_dly_SI (Div_start_dly_SI[i] ), + .Sqrt_enable_SI (Sqrt_enable_SI[i] ), + .D_DI (Sqrt_DI[i] ), + .D_DO (Sqrt_DO[i] ), + .Sum_DO (Iteration_cell_sum_D[i] ), + .Carry_out_DO (Iteration_cell_carry_D[i] ) + ); + + end + + endgenerate + + + + always_comb + begin + case (Iteration_unit_num_S) + 2'b00: + begin + if(Fsm_enable_S) + Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R1:Iteration_cell_sum_AMASK_D[0]; + else + Partial_remainder_DN = Partial_remainder_DP; + end + 2'b01: + begin + if(Fsm_enable_S) + Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R2:Iteration_cell_sum_AMASK_D[1]; + else + Partial_remainder_DN = Partial_remainder_DP; + end + 2'b10: + begin + if(Fsm_enable_S) + Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R3:Iteration_cell_sum_AMASK_D[2]; + else + Partial_remainder_DN = Partial_remainder_DP; + end + 2'b11: + begin + if(Fsm_enable_S) + Partial_remainder_DN = Sqrt_enable_SO?Sqrt_R4:Iteration_cell_sum_AMASK_D[3]; + else + Partial_remainder_DN = Partial_remainder_DP; + end + endcase + end + + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) // partial_remainder + begin + if(~Rst_RBI) + begin + Partial_remainder_DP <= '0; + end + else + begin + Partial_remainder_DP <= Partial_remainder_DN; + end + end + + logic [C_MANT_FP64+4:0] Quotient_DN; + + always_comb // Can choosen the different carry-outs based on different operations + begin + case (Iteration_unit_num_S) + 2'b00: + begin + if(Fsm_enable_S) + Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+3:0],Sqrt_quotinent_S[3]} :{Quotient_DP[C_MANT_FP64+3:0],Iteration_cell_carry_D[0]}; + else + Quotient_DN= Quotient_DP; + end + 2'b01: + begin + if(Fsm_enable_S) + Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+2:0],Sqrt_quotinent_S[3:2]} :{Quotient_DP[C_MANT_FP64+2:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1]}; + else + Quotient_DN= Quotient_DP; + end + 2'b10: + begin + if(Fsm_enable_S) + Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64+1:0],Sqrt_quotinent_S[3:1]} : {Quotient_DP[C_MANT_FP64+1:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2]}; + else + Quotient_DN= Quotient_DP; + end + 2'b11: + begin + if(Fsm_enable_S) + Quotient_DN= Sqrt_enable_SO ? {Quotient_DP[C_MANT_FP64:0],Sqrt_quotinent_S } : {Quotient_DP[C_MANT_FP64:0],Iteration_cell_carry_D[0],Iteration_cell_carry_D[1],Iteration_cell_carry_D[2],Iteration_cell_carry_D[3]}; + else + Quotient_DN= Quotient_DP; + end + endcase + end + + always_ff @(posedge Clk_CI, negedge Rst_RBI) // Quotient + begin + if(~Rst_RBI) + begin + Quotient_DP <= '0; + end + else + Quotient_DP <= Quotient_DN; + end + + + ///////////////////////////////////////////////////////////////////////////// + // Precision Control for outputs // + ///////////////////////////////////////////////////////////////////////////// + + +//////////////////////one iteration unit, start/////////////////////////////////////// + generate + if(Iteration_unit_num_S==2'b00) + begin + always_comb + begin + case (Format_sel_S) + 2'b00: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + 6'h17: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h16: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-1:0],{(C_MANT_FP64-C_MANT_FP32+4+1){1'b0}}}; //Precision_ctl_S+1 + end + 6'h15: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 + end + 6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 + end + 6'h13: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-5:0],{(C_MANT_FP64-C_MANT_FP32+4+5){1'b0}}}; //Precision_ctl_S+1 + end + 6'h11: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 + end + 6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-7:0],{(C_MANT_FP64-C_MANT_FP32+4+7){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0d: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-11:0],{(C_MANT_FP64-C_MANT_FP32+4+11){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0b: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-13:0],{(C_MANT_FP64-C_MANT_FP32+4+13){1'b0}}}; //Precision_ctl_S+1 + end + 6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 + end + 6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + endcase + end + + 2'b01: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 + end + 6'h34: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64:0],{(4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h33: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}}}; //Precision_ctl_S+1 + end + 6'h32: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}}}; //Precision_ctl_S+1 + end + 6'h31: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}}}; //Precision_ctl_S+1 + end + 6'h30: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-4:0],{(4+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-6:0],{(4+6){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2d: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2b: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}}}; //Precision_ctl_S+1 + end + 6'h2a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-10:0],{(4+10){1'b0}}}; //Precision_ctl_S+1 + end + 6'h29: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}}}; //Precision_ctl_S+1 + end + 6'h28: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-12:0],{(4+12){1'b0}}}; //Precision_ctl_S+1 + end + 6'h27: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}}}; //Precision_ctl_S+1 + end + 6'h26: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}}}; //Precision_ctl_S+1 + end + 6'h25: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}}}; //Precision_ctl_S+1 + end + 6'h24: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-16:0],{(4+16){1'b0}}}; //Precision_ctl_S+1 + end + 6'h23: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}}}; //Precision_ctl_S+1 + end + 6'h22: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-18:0],{(4+18){1'b0}}}; //Precision_ctl_S+1 + end + 6'h21: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}}}; //Precision_ctl_S+1 + end + 6'h20: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-22:0],{(4+22){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1d: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-24:0],{(4+24){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1b: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}}}; //Precision_ctl_S+1 + end + 6'h1a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}}}; //Precision_ctl_S+1 + end + 6'h19: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}}}; //Precision_ctl_S+1 + end + 6'h18: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-28:0],{(4+28){1'b0}}}; //Precision_ctl_S+1 + end + 6'h17: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}}}; //Precision_ctl_S+1 + end + 6'h16: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-30:0],{(4+30){1'b0}}}; //Precision_ctl_S+1 + end + 6'h15: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}}}; //Precision_ctl_S+1 + end + 6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}}}; //Precision_ctl_S+1 + end + 6'h13: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}}}; //Precision_ctl_S+1 + end + 6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-34:0],{(4+34){1'b0}}}; //Precision_ctl_S+1 + end + 6'h11: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}}}; //Precision_ctl_S+1 + end + 6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-36:0],{(4+36){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0d: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-40:0],{(4+40){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0b: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-42:0],{(4+42){1'b0}}}; //Precision_ctl_S+1 + end + 6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}}}; //Precision_ctl_S+1 + end + 6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}}}; //Precision_ctl_S+1 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}}}; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 + end + endcase + end + + 2'b10: + begin + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 + end + 6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16:0],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}}}; //Precision_ctl_S+1 + end + 6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}}}; //Precision_ctl_S+1 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}}}; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}}}; //+4 + end + endcase + end + + 2'b11: + begin + + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}}}; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}}}; //+4 + end + endcase + end + endcase + end + end + endgenerate +//////////////////////one iteration unit, end////////////////////////////////////////// + +//////////////////////two iteration units, start/////////////////////////////////////// + generate + if(Iteration_unit_num_S==2'b01) + begin + always_comb + begin + case (Format_sel_S) + 2'b00: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + 6'h17,6'h16: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h15,6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-2:0],{(C_MANT_FP64-C_MANT_FP32+4+2){1'b0}}}; //Precision_ctl_S+1 + end + 6'h13,6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h11,6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0f,6'h0e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-10:0],{(C_MANT_FP64-C_MANT_FP32+4+10){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0b,6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 + end + 6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-14:0],{(C_MANT_FP64-C_MANT_FP32+4+14){1'b0}}}; //Precision_ctl_S+1 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + endcase + end + 2'b01: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 + end + 6'h34: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 + end + 6'h33,6'h32: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(4+1){1'b0}} }; //Precision_ctl_S+1 + end + 6'h31,6'h30: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-3:0],{(4+3){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2f,6'h2e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2d,6'h2c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-7:0],{(4+7){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2b,6'h2a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(4+9){1'b0}} }; //Precision_ctl_S+1 + end + 6'h29,6'h28: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 + end + 6'h27,6'h26: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(4+13){1'b0}} }; //Precision_ctl_S+1 + end + 6'h25,6'h24: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-15:0],{(4+15){1'b0}} }; //Precision_ctl_S+1 + end + 6'h23,6'h22: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 + end + 6'h21,6'h20: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-19:0],{(4+19){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1f,6'h1e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(4+21){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1d,6'h1c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1b,6'h1a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(4+25){1'b0}} }; //Precision_ctl_S+1 + end + 6'h19,6'h18: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-27:0],{(4+27){1'b0}} }; //Precision_ctl_S+1 + end + 6'h17,6'h16: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 + end + 6'h15,6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-31:0],{(4+31){1'b0}} }; //Precision_ctl_S+1 + end + 6'h13,6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(4+33){1'b0}} }; //Precision_ctl_S+1 + end + 6'h11,6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0f,6'h0e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(4+37){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-39:0],{(4+39){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0b,6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 + end + 6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-43:0],{(4+43){1'b0}} }; //Precision_ctl_S+1 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(4+45){1'b0}} }; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],1'b0}; //+3 + end + endcase + end + + 2'b10: + begin + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+3:0],{(C_MANT_FP64-C_MANT_FP16+1){1'b0}} }; //+3 + end + 6'h0a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 + end + 6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-1:0],{(C_MANT_FP64-C_MANT_FP16+4+1){1'b0}} }; //Precision_ctl_S+1 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-3:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 + end + endcase + end + + 2'b11: + begin + + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + 6'h07: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + endcase + end + endcase + end + end + endgenerate +//////////////////////two iteration units, end////////////////////////////////////////// + +//////////////////////three iteration units, start/////////////////////////////////////// + generate + if(Iteration_unit_num_S==2'b10) + begin + always_comb + begin + case (Format_sel_S) + 2'b00: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 + end + 6'h17,6'h16,6'h15: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h14,6'h13,6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-3:0],{(C_MANT_FP64-C_MANT_FP32+4+3){1'b0}}}; //Precision_ctl_S+1 + end + 6'h11,6'h10,6'h0f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-6:0],{(C_MANT_FP64-C_MANT_FP32+4+6){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0e,6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-9:0],{(C_MANT_FP64-C_MANT_FP32+4+9){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0b,6'h0a,6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 + end + 6'h08,6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-15:0],{(C_MANT_FP64-C_MANT_FP32+4+15){1'b0}}}; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+3:0],{(C_MANT_FP64-C_MANT_FP32+1){1'b0}}}; //+3 + end + endcase + end + + 2'b01: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 + end + 6'h34,6'h33: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+1:1],{(4){1'b0}} }; //Precision_ctl_S+1 + end + 6'h32,6'h31,6'h30: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-2:0],{(4+2){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2f,6'h2e,6'h2d: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(4+5){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2c,6'h2b,6'h2a: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-8:0],{(4+8){1'b0}} }; //Precision_ctl_S+1 + end + 6'h29,6'h28,6'h27: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-11:0],{(4+11){1'b0}} }; //Precision_ctl_S+1 + end + 6'h26,6'h25,6'h24: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-14:0],{(4+14){1'b0}} }; //Precision_ctl_S+1 + end + 6'h23,6'h22,6'h21: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(4+17){1'b0}} }; //Precision_ctl_S+1 + end + 6'h20,6'h1f,6'h1e: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-20:0],{(4+20){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1d,6'h1c,6'h1b: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-23:0],{(4+23){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1a,6'h19,6'h18: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-26:0],{(4+26){1'b0}} }; //Precision_ctl_S+1 + end + 6'h17,6'h16,6'h15: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(4+29){1'b0}} }; //Precision_ctl_S+1 + end + 6'h14,6'h13,6'h12: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-32:0],{(4+32){1'b0}} }; //Precision_ctl_S+1 + end + 6'h11,6'h10,6'h0f: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-35:0],{(4+35){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0e,6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-38:0],{(4+38){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0b,6'h0a,6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(4+41){1'b0}} }; //Precision_ctl_S+1 + end + 6'h08,6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-44:0],{(4+44){1'b0}} }; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = Quotient_DP[C_MANT_FP64+4:0]; //+4 + end + endcase + end + + 2'b10: + begin + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 + end + 6'h0a,6'h09: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 + end + 6'h08,6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16-2:0],{(C_MANT_FP64-C_MANT_FP16+4+2){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+4:0],{(C_MANT_FP64-C_MANT_FP16){1'b0}} }; //+4 + end + endcase + end + + 2'b11: + begin + + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+1:1],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + endcase + end + endcase + end + end + endgenerate +//////////////////////three iteration units, end////////////////////////////////////////// + +//////////////////////four iteration units, start/////////////////////////////////////// + generate + if(Iteration_unit_num_S==2'b11) + begin + always_comb + begin + case (Format_sel_S) + 2'b00: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + 6'h17,6'h16,6'h15,6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32:0],{(C_MANT_FP64-C_MANT_FP32+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h13,6'h12,6'h11,6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-4:0],{(C_MANT_FP64-C_MANT_FP32+4+4){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0f,6'h0e,6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-8:0],{(C_MANT_FP64-C_MANT_FP32+4+8){1'b0}}}; //Precision_ctl_S+1 + end + 6'h0b,6'h0a,6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-12:0],{(C_MANT_FP64-C_MANT_FP32+4+12){1'b0}}}; //Precision_ctl_S+1 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32-16:0],{(C_MANT_FP64-C_MANT_FP32+4+16){1'b0}}}; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP32+4:0],{(C_MANT_FP64-C_MANT_FP32){1'b0}}}; //+4 + end + endcase + end + + 2'b01: + begin + case (Precision_ctl_S) + 6'h00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 + end + 6'h34: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}} }; //Precision_ctl_S+1 + end + 6'h33,6'h32,6'h31,6'h30: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-1:0],{(5){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2f,6'h2e,6'h2d,6'h2c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-5:0],{(9){1'b0}} }; //Precision_ctl_S+1 + end + 6'h2b,6'h2a,6'h29,6'h28: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-9:0],{(13){1'b0}} }; //Precision_ctl_S+1 + end + 6'h27,6'h26,6'h25,6'h24: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-13:0],{(17){1'b0}} }; //Precision_ctl_S+1 + end + 6'h23,6'h22,6'h21,6'h20: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-17:0],{(21){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1f,6'h1e,6'h1d,6'h1c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-21:0],{(25){1'b0}} }; //Precision_ctl_S+1 + end + 6'h1b,6'h1a,6'h19,6'h18: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-25:0],{(29){1'b0}} }; //Precision_ctl_S+1 + end + 6'h17,6'h16,6'h15,6'h14: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-29:0],{(33){1'b0}} }; //Precision_ctl_S+1 + end + 6'h13,6'h12,6'h11,6'h10: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-33:0],{(37){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0f,6'h0e,6'h0d,6'h0c: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-37:0],{(41){1'b0}} }; //Precision_ctl_S+1 + end + 6'h0b,6'h0a,6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-41:0],{(45){1'b0}} }; //Precision_ctl_S+1 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64-45:0],{(49){1'b0}} }; //Precision_ctl_S+1 + end + default: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP64+3:0],{(1){1'b0}}}; //+3 + end + endcase + end + + 2'b10: + begin + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 + end + 6'h0a,6'h09,6'h08: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1:1],{(C_MANT_FP64-C_MANT_FP16+4){1'b0}} }; //Precision_ctl_S+1 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+1-4:0],{(C_MANT_FP64-C_MANT_FP16+4+3){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16+5:0],{(C_MANT_FP64-C_MANT_FP16-1){1'b0}} }; //+5 + end + endcase + end + + 2'b11: + begin + + case (Precision_ctl_S) + 6'b00: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + 6'h07,6'h06: + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT:0],{(C_MANT_FP64-C_MANT_FP16ALT+4){1'b0}} }; //Precision_ctl_S+1 + end + default : + begin + Mant_result_prenorm_DO = {Quotient_DP[C_MANT_FP16ALT+4:0],{(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; //+4 + end + endcase + end + endcase + end + end + endgenerate +//////////////////////four iteration units, end/////////////////////////////////////// + + + + + +// resultant exponent + logic [C_EXP_FP64+1:0] Exp_result_prenorm_DN,Exp_result_prenorm_DP; + + logic [C_EXP_FP64+1:0] Exp_add_a_D; + logic [C_EXP_FP64+1:0] Exp_add_b_D; + logic [C_EXP_FP64+1:0] Exp_add_c_D; + + integer C_BIAS_AONE, C_HALF_BIAS; + always_comb + begin // + case (Format_sel_S) + 2'b00: + begin + C_BIAS_AONE =C_BIAS_AONE_FP32; + C_HALF_BIAS =C_HALF_BIAS_FP32; + end + 2'b01: + begin + C_BIAS_AONE =C_BIAS_AONE_FP64; + C_HALF_BIAS =C_HALF_BIAS_FP64; + end + 2'b10: + begin + C_BIAS_AONE =C_BIAS_AONE_FP16; + C_HALF_BIAS =C_HALF_BIAS_FP16; + end + 2'b11: + begin + C_BIAS_AONE =C_BIAS_AONE_FP16ALT; + C_HALF_BIAS =C_HALF_BIAS_FP16ALT; + end + endcase + end + +//For division, exponent=(Exp_a_D-LZ1)-(Exp_b_D-LZ2)+BIAS +//For square root, exponent=(Exp_a_D-LZ1)/2+(Exp_a_D-LZ1)%2+C_HALF_BIAS +//For exponent, in preprorces module, (Exp_a_D-LZ1) and (Exp_b_D-LZ2) have been processed with the corresponding process for denormal numbers. + + assign Exp_add_a_D = {Sqrt_start_dly_S?{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64:1]}:{Exp_num_DI[C_EXP_FP64],Exp_num_DI[C_EXP_FP64],Exp_num_DI}}; + assign Exp_add_b_D = {Sqrt_start_dly_S?{1'b0,{C_EXP_ZERO_FP64},Exp_num_DI[0]}:{~Exp_den_DI[C_EXP_FP64],~Exp_den_DI[C_EXP_FP64],~Exp_den_DI}}; + assign Exp_add_c_D = {Div_start_dly_S?{{C_BIAS_AONE}}:{{C_HALF_BIAS}}}; + assign Exp_result_prenorm_DN = (Start_dly_S)?{Exp_add_a_D + Exp_add_b_D + Exp_add_c_D}:Exp_result_prenorm_DP; + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Exp_result_prenorm_DP <= '0; + end + else + begin + Exp_result_prenorm_DP<= Exp_result_prenorm_DN; + end + end + + assign Exp_result_prenorm_DO = Exp_result_prenorm_DP; + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv new file mode 100644 index 0000000000..b3f41fec61 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv @@ -0,0 +1,83 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// This file contains all div_sqrt_top_mvp parameters +// Authors : Lei Li (lile@iis.ee.ethz.ch) + +package defs_div_sqrt_mvp; + + // op command + localparam C_RM = 3; + localparam C_RM_NEAREST = 3'h0; + localparam C_RM_TRUNC = 3'h1; + localparam C_RM_PLUSINF = 3'h2; + localparam C_RM_MINUSINF = 3'h3; + localparam C_PC = 6; // Precision Control + localparam C_FS = 2; // Format Selection + localparam C_IUNC = 2; // Iteration Unit Number Control + localparam Iteration_unit_num_S = 2'b10; + + // FP64 + localparam C_OP_FP64 = 64; + localparam C_MANT_FP64 = 52; + localparam C_EXP_FP64 = 11; + localparam C_BIAS_FP64 = 1023; + localparam C_BIAS_AONE_FP64 = 11'h400; + localparam C_HALF_BIAS_FP64 = 511; + localparam C_EXP_ZERO_FP64 = 11'h000; + localparam C_EXP_ONE_FP64 = 13'h001; // Bit width is in agreement with in norm + localparam C_EXP_INF_FP64 = 11'h7FF; + localparam C_MANT_ZERO_FP64 = 52'h0; + localparam C_MANT_NAN_FP64 = 52'h8_0000_0000_0000; + localparam C_PZERO_FP64 = 64'h0000_0000_0000_0000; + localparam C_MZERO_FP64 = 64'h8000_0000_0000_0000; + localparam C_QNAN_FP64 = 64'h7FF8_0000_0000_0000; + + // FP32 + localparam C_OP_FP32 = 32; + localparam C_MANT_FP32 = 23; + localparam C_EXP_FP32 = 8; + localparam C_BIAS_FP32 = 127; + localparam C_BIAS_AONE_FP32 = 8'h80; + localparam C_HALF_BIAS_FP32 = 63; + localparam C_EXP_ZERO_FP32 = 8'h00; + localparam C_EXP_INF_FP32 = 8'hFF; + localparam C_MANT_ZERO_FP32 = 23'h0; + localparam C_PZERO_FP32 = 32'h0000_0000; + localparam C_MZERO_FP32 = 32'h8000_0000; + localparam C_QNAN_FP32 = 32'h7FC0_0000; + + // FP16 + localparam C_OP_FP16 = 16; + localparam C_MANT_FP16 = 10; + localparam C_EXP_FP16 = 5; + localparam C_BIAS_FP16 = 15; + localparam C_BIAS_AONE_FP16 = 5'h10; + localparam C_HALF_BIAS_FP16 = 7; + localparam C_EXP_ZERO_FP16 = 5'h00; + localparam C_EXP_INF_FP16 = 5'h1F; + localparam C_MANT_ZERO_FP16 = 10'h0; + localparam C_PZERO_FP16 = 16'h0000; + localparam C_MZERO_FP16 = 16'h8000; + localparam C_QNAN_FP16 = 16'h7E00; + + // FP16alt + localparam C_OP_FP16ALT = 16; + localparam C_MANT_FP16ALT = 7; + localparam C_EXP_FP16ALT = 8; + localparam C_BIAS_FP16ALT = 127; + localparam C_BIAS_AONE_FP16ALT = 8'h80; + localparam C_HALF_BIAS_FP16ALT = 63; + localparam C_EXP_ZERO_FP16ALT = 8'h00; + localparam C_EXP_INF_FP16ALT = 8'hFF; + localparam C_MANT_ZERO_FP16ALT = 7'h0; + localparam C_QNAN_FP16ALT = 16'h7FC0; + +endpackage : defs_div_sqrt_mvp diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv new file mode 100644 index 0000000000..3af6081b7f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv @@ -0,0 +1,180 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li -- lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 03/03/2018 // +// Design Name: div_sqrt_top_mvp // +// Module Name: div_sqrt_top_mvp.sv // +// Project Name: The shared divisor and square root // +// Language: SystemVerilog // +// // +// Description: The top of div and sqrt // +// // +// // +// Revision Date: 12/04/2018 // +// Lei Li // +// To address some requirements by Stefan and add low power // +// control for special cases // +//////////////////////////////////////////////////////////////////////////////// + +import defs_div_sqrt_mvp::*; + +module div_sqrt_top_mvp + + (//Input + input logic Clk_CI, + input logic Rst_RBI, + input logic Div_start_SI, + input logic Sqrt_start_SI, + + //Input Operands + input logic [C_OP_FP64-1:0] Operand_a_DI, + input logic [C_OP_FP64-1:0] Operand_b_DI, + + // Input Control + input logic [C_RM-1:0] RM_SI, //Rounding Mode + input logic [C_PC-1:0] Precision_ctl_SI, // Precision Control + input logic [C_FS-1:0] Format_sel_SI, // Format Selection, + input logic Kill_SI, + + //Output Result + output logic [C_OP_FP64-1:0] Result_DO, + + //Output-Flags + output logic [4:0] Fflags_SO, + output logic Ready_SO, + output logic Done_SO + ); + + + + + + //Operand components + logic [C_EXP_FP64:0] Exp_a_D; + logic [C_EXP_FP64:0] Exp_b_D; + logic [C_MANT_FP64:0] Mant_a_D; + logic [C_MANT_FP64:0] Mant_b_D; + + logic [C_EXP_FP64+1:0] Exp_z_D; + logic [C_MANT_FP64+4:0] Mant_z_D; + logic Sign_z_D; + logic Start_S; + logic [C_RM-1:0] RM_dly_S; + logic Div_enable_S; + logic Sqrt_enable_S; + logic Inf_a_S; + logic Inf_b_S; + logic Zero_a_S; + logic Zero_b_S; + logic NaN_a_S; + logic NaN_b_S; + logic SNaN_S; + logic Special_case_SB,Special_case_dly_SB; + + logic Full_precision_S; + logic FP32_S; + logic FP64_S; + logic FP16_S; + logic FP16ALT_S; + + + preprocess_mvp preprocess_U0 + ( + .Clk_CI (Clk_CI ), + .Rst_RBI (Rst_RBI ), + .Div_start_SI (Div_start_SI ), + .Sqrt_start_SI (Sqrt_start_SI ), + .Ready_SI (Ready_SO ), + .Operand_a_DI (Operand_a_DI ), + .Operand_b_DI (Operand_b_DI ), + .RM_SI (RM_SI ), + .Format_sel_SI (Format_sel_SI ), + .Start_SO (Start_S ), + .Exp_a_DO_norm (Exp_a_D ), + .Exp_b_DO_norm (Exp_b_D ), + .Mant_a_DO_norm (Mant_a_D ), + .Mant_b_DO_norm (Mant_b_D ), + .RM_dly_SO (RM_dly_S ), + .Sign_z_DO (Sign_z_D ), + .Inf_a_SO (Inf_a_S ), + .Inf_b_SO (Inf_b_S ), + .Zero_a_SO (Zero_a_S ), + .Zero_b_SO (Zero_b_S ), + .NaN_a_SO (NaN_a_S ), + .NaN_b_SO (NaN_b_S ), + .SNaN_SO (SNaN_S ), + .Special_case_SBO (Special_case_SB ), + .Special_case_dly_SBO (Special_case_dly_SB) + ); + + nrbd_nrsc_mvp nrbd_nrsc_U0 + ( + .Clk_CI (Clk_CI ), + .Rst_RBI (Rst_RBI ), + .Div_start_SI (Div_start_SI ) , + .Sqrt_start_SI (Sqrt_start_SI ), + .Start_SI (Start_S ), + .Kill_SI (Kill_SI ), + .Special_case_SBI (Special_case_SB ), + .Special_case_dly_SBI (Special_case_dly_SB), + .Div_enable_SO (Div_enable_S ), + .Sqrt_enable_SO (Sqrt_enable_S ), + .Precision_ctl_SI (Precision_ctl_SI ), + .Format_sel_SI (Format_sel_SI ), + .Exp_a_DI (Exp_a_D ), + .Exp_b_DI (Exp_b_D ), + .Mant_a_DI (Mant_a_D ), + .Mant_b_DI (Mant_b_D ), + .Full_precision_SO (Full_precision_S ), + .FP32_SO (FP32_S ), + .FP64_SO (FP64_S ), + .FP16_SO (FP16_S ), + .FP16ALT_SO (FP16ALT_S ), + .Ready_SO (Ready_SO ), + .Done_SO (Done_SO ), + .Exp_z_DO (Exp_z_D ), + .Mant_z_DO (Mant_z_D ) + ); + + + norm_div_sqrt_mvp fpu_norm_U0 + ( + .Mant_in_DI (Mant_z_D ), + .Exp_in_DI (Exp_z_D ), + .Sign_in_DI (Sign_z_D ), + .Div_enable_SI (Div_enable_S ), + .Sqrt_enable_SI (Sqrt_enable_S ), + .Inf_a_SI (Inf_a_S ), + .Inf_b_SI (Inf_b_S ), + .Zero_a_SI (Zero_a_S ), + .Zero_b_SI (Zero_b_S ), + .NaN_a_SI (NaN_a_S ), + .NaN_b_SI (NaN_b_S ), + .SNaN_SI (SNaN_S ), + .RM_SI (RM_dly_S ), + .Full_precision_SI (Full_precision_S ), + .FP32_SI (FP32_S ), + .FP64_SI (FP64_S ), + .FP16_SI (FP16_S ), + .FP16ALT_SI (FP16ALT_S ), + .Result_DO (Result_DO ), + .Fflags_SO (Fflags_SO ) //{NV,DZ,OF,UF,NX} + ); + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv new file mode 100644 index 0000000000..0c645e6ebe --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv @@ -0,0 +1,61 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 12/01/2017 // +// Design Name: FPU // +// Module Name: iteration_div_sqrt_mvp // +// Project Name: Private FPU // +// Language: SystemVerilog // +// // +// Description: iteration unit for div and sqrt // +// // +// // +// Revision: 03/14/2018 // +// For div_sqrt_mvp // +//////////////////////////////////////////////////////////////////////////////// + +module iteration_div_sqrt_mvp +#( + parameter WIDTH=25 +) + (//Input + + input logic [WIDTH-1:0] A_DI, + input logic [WIDTH-1:0] B_DI, + input logic Div_enable_SI, + input logic Div_start_dly_SI, + input logic Sqrt_enable_SI, + input logic [1:0] D_DI, + + output logic [1:0] D_DO, + output logic [WIDTH-1:0] Sum_DO, + output logic Carry_out_DO + ); + + logic D_carry_D; + logic Sqrt_cin_D; + logic Cin_D; + + assign D_DO[0]=~D_DI[0]; + assign D_DO[1]=~(D_DI[1] ^ D_DI[0]); + assign D_carry_D=D_DI[1] | D_DI[0]; + assign Sqrt_cin_D=Sqrt_enable_SI&&D_carry_D; + assign Cin_D=Div_enable_SI?1'b0:Sqrt_cin_D; + assign {Carry_out_DO,Sum_DO}=A_DI+B_DI+Cin_D; + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv new file mode 100644 index 0000000000..590abe969b --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv @@ -0,0 +1,470 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 09/03/2018 // +// Design Name: FPU // +// Module Name: norm_div_sqrt_mvp.sv // +// Project Name: // +// Language: SystemVerilog // +// // +// Description: Floating point Normalizer/Rounding unit // +// Since this module is design as a combinatinal logic, it can// +// be added arbinary register stages for different frequency // +// in the wrapper module. // +// // +// // +// // +// Revision Date: 12/04/2018 // +// Lei Li // +// To address some requirements by Stefan // +// // +// // +// // +// // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +import defs_div_sqrt_mvp::*; + +module norm_div_sqrt_mvp + (//Inputs + input logic [C_MANT_FP64+4:0] Mant_in_DI, // Include the needed 4-bit for rounding and hidden bit + input logic signed [C_EXP_FP64+1:0] Exp_in_DI, + input logic Sign_in_DI, + input logic Div_enable_SI, + input logic Sqrt_enable_SI, + input logic Inf_a_SI, + input logic Inf_b_SI, + input logic Zero_a_SI, + input logic Zero_b_SI, + input logic NaN_a_SI, + input logic NaN_b_SI, + input logic SNaN_SI, + input logic [C_RM-1:0] RM_SI, + input logic Full_precision_SI, + input logic FP32_SI, + input logic FP64_SI, + input logic FP16_SI, + input logic FP16ALT_SI, + //Outputs + output logic [C_EXP_FP64+C_MANT_FP64:0] Result_DO, + output logic [4:0] Fflags_SO //{NV,DZ,OF,UF,NX} + ); + + + logic Sign_res_D; + + logic NV_OP_S; + logic Exp_OF_S; + logic Exp_UF_S; + logic Div_Zero_S; + logic In_Exact_S; + + ///////////////////////////////////////////////////////////////////////////// + // Normalization // + ///////////////////////////////////////////////////////////////////////////// + logic [C_MANT_FP64:0] Mant_res_norm_D; + logic [C_EXP_FP64-1:0] Exp_res_norm_D; + + ///////////////////////////////////////////////////////////////////////////// + // Right shift operations for negtive exponents // + ///////////////////////////////////////////////////////////////////////////// + + logic [C_EXP_FP64+1:0] Exp_Max_RS_FP64_D; + logic [C_EXP_FP32+1:0] Exp_Max_RS_FP32_D; + logic [C_EXP_FP16+1:0] Exp_Max_RS_FP16_D; + logic [C_EXP_FP16ALT+1:0] Exp_Max_RS_FP16ALT_D; + // + assign Exp_Max_RS_FP64_D=Exp_in_DI[C_EXP_FP64:0]+C_MANT_FP64+1; // to check exponent after (C_MANT_FP64+1)-bit >> when Exp_in_DI is negative + assign Exp_Max_RS_FP32_D=Exp_in_DI[C_EXP_FP32:0]+C_MANT_FP32+1; // to check exponent after (C_MANT_FP32+1)-bit >> when Exp_in_DI is negative + assign Exp_Max_RS_FP16_D=Exp_in_DI[C_EXP_FP16:0]+C_MANT_FP16+1; // to check exponent after (C_MANT_FP16+1)-bit >> when Exp_in_DI is negative + assign Exp_Max_RS_FP16ALT_D=Exp_in_DI[C_EXP_FP16ALT:0]+C_MANT_FP16ALT+1; // to check exponent after (C_MANT_FP16ALT+1)-bit >> when Exp_in_DI is negative + logic [C_EXP_FP64+1:0] Num_RS_D; + assign Num_RS_D=~Exp_in_DI+1+1; // How many right shifts(RS) are needed to generate a denormal number? >> is need only when Exp_in_DI is negative + logic [C_MANT_FP64:0] Mant_RS_D; + logic [C_MANT_FP64+4:0] Mant_forsticky_D; + assign {Mant_RS_D,Mant_forsticky_D} ={Mant_in_DI,{(C_MANT_FP64+1){1'b0}} } >>(Num_RS_D); // +// + logic [C_EXP_FP64+1:0] Exp_subOne_D; + assign Exp_subOne_D = Exp_in_DI -1; + + //normalization + logic [1:0] Mant_lower_D; + logic Mant_sticky_bit_D; + logic [C_MANT_FP64+4:0] Mant_forround_D; + + always_comb + begin + + if(NaN_a_SI) // if a is NaN, return NaN + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = SNaN_SI; + end + + else if(NaN_b_SI) //if b is NaN, return NaN + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = SNaN_SI; + end + + else if(Inf_a_SI) + begin + if(Div_enable_SI&&Inf_b_SI) //Inf/Inf, retrurn NaN + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = 1'b1; + end + else if (Sqrt_enable_SI && Sign_in_DI) begin // catch sqrt(-inf) + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = 1'b1; + end else begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b1; + Exp_UF_S=1'b0; + Mant_res_norm_D= '0; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + end + + else if(Div_enable_SI&&Inf_b_SI) + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b1; + Exp_UF_S=1'b0; + Mant_res_norm_D= '0; + Exp_res_norm_D='0; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else if(Zero_a_SI) + begin + if(Div_enable_SI&&Zero_b_SI) + begin + Div_Zero_S=1'b1; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = 1'b1; + end + else + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D='0; + Exp_res_norm_D='0; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + end + + else if(Div_enable_SI&&(Zero_b_SI)) //div Zero + begin + Div_Zero_S=1'b1; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D='0; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else if(Sign_in_DI&&Sqrt_enable_SI) //sqrt(-a) + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D={1'b0,C_MANT_NAN_FP64}; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=1'b0; + NV_OP_S = 1'b1; + end + + else if((Exp_in_DI[C_EXP_FP64:0]=='0)) + begin + if(Mant_in_DI!='0) //Exp=0, Mant!=0, it is denormal + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b1; + Mant_res_norm_D={1'b0,Mant_in_DI[C_MANT_FP64+4:5]}; + Exp_res_norm_D='0; + Mant_forround_D={Mant_in_DI[4:0],{(C_MANT_FP64){1'b0}} }; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + else // Zero + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D='0; + Exp_res_norm_D='0; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + end + + else if((Exp_in_DI[C_EXP_FP64:0]==C_EXP_ONE_FP64)&&(~Mant_in_DI[C_MANT_FP64+4])) //denormal + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b1; + Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+4:4]; + Exp_res_norm_D='0; + Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else if(Exp_in_DI[C_EXP_FP64+1]) //minus //consider format + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b1; + Mant_res_norm_D={Mant_RS_D[C_MANT_FP64:0]}; + Exp_res_norm_D='0; + Mant_forround_D={Mant_forsticky_D[C_MANT_FP64+4:0]}; //?? + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else if( (Exp_in_DI[C_EXP_FP32]&&FP32_SI) | (Exp_in_DI[C_EXP_FP64]&&FP64_SI) | (Exp_in_DI[C_EXP_FP16]&&FP16_SI) | (Exp_in_DI[C_EXP_FP16ALT]&&FP16ALT_SI) ) //OF + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b1; + Exp_UF_S=1'b0; + Mant_res_norm_D='0; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else if( ((Exp_in_DI[C_EXP_FP32-1:0]=='1)&&FP32_SI) | ((Exp_in_DI[C_EXP_FP64-1:0]=='1)&&FP64_SI) | ((Exp_in_DI[C_EXP_FP16-1:0]=='1)&&FP16_SI) | ((Exp_in_DI[C_EXP_FP16ALT-1:0]=='1)&&FP16ALT_SI) )//255 + begin + if(~Mant_in_DI[C_MANT_FP64+4]) // MSB=0 + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; + Exp_res_norm_D=Exp_subOne_D; + Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + else if(Mant_in_DI!='0) //NaN + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b1; + Exp_UF_S=1'b0; + Mant_res_norm_D= '0; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + else //infinity + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b1; + Exp_UF_S=1'b0; + Mant_res_norm_D= '0; + Exp_res_norm_D='1; + Mant_forround_D='0; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + end + + else if(Mant_in_DI[C_MANT_FP64+4]) //normal numbers with 1.XXX + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D= Mant_in_DI[C_MANT_FP64+4:4]; + Exp_res_norm_D=Exp_in_DI[C_EXP_FP64-1:0]; + Mant_forround_D={Mant_in_DI[3:0],{(C_MANT_FP64+1){1'b0}}}; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + else //normal numbers with 0.1XX + begin + Div_Zero_S=1'b0; + Exp_OF_S=1'b0; + Exp_UF_S=1'b0; + Mant_res_norm_D=Mant_in_DI[C_MANT_FP64+3:3]; + Exp_res_norm_D=Exp_subOne_D; + Mant_forround_D={Mant_in_DI[2:0],{(C_MANT_FP64+2){1'b0}}}; + Sign_res_D=Sign_in_DI; + NV_OP_S = 1'b0; + end + + end + + ///////////////////////////////////////////////////////////////////////////// + // Rounding enable only for full precision (Full_precision_SI==1'b1) // + ///////////////////////////////////////////////////////////////////////////// + + logic [C_MANT_FP64:0] Mant_upper_D; + logic [C_MANT_FP64+1:0] Mant_upperRounded_D; + logic Mant_roundUp_S; + logic Mant_rounded_S; + + always_comb //determine which bits for Mant_lower_D and Mant_sticky_bit_D + begin + if(FP32_SI) + begin + Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP32], {(C_MANT_FP64-C_MANT_FP32){1'b0}} }; + Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-1:C_MANT_FP64-C_MANT_FP32-2]; + Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP32-3:0]; + end + else if(FP64_SI) + begin + Mant_upper_D = Mant_res_norm_D[C_MANT_FP64:0]; + Mant_lower_D = Mant_forround_D[C_MANT_FP64+4:C_MANT_FP64+3]; + Mant_sticky_bit_D = | Mant_forround_D[C_MANT_FP64+3:0]; + end + else if(FP16_SI) + begin + Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16], {(C_MANT_FP64-C_MANT_FP16){1'b0}} }; + Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-1:C_MANT_FP64-C_MANT_FP16-2]; + Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16-3:30]; + end + else //FP16ALT + begin + Mant_upper_D = {Mant_res_norm_D[C_MANT_FP64:C_MANT_FP64-C_MANT_FP16ALT], {(C_MANT_FP64-C_MANT_FP16ALT){1'b0}} }; + Mant_lower_D = Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-1:C_MANT_FP64-C_MANT_FP16ALT-2]; + Mant_sticky_bit_D = | Mant_res_norm_D[C_MANT_FP64-C_MANT_FP16ALT-3:30]; + end + end + + assign Mant_rounded_S = (|(Mant_lower_D))| Mant_sticky_bit_D; + + + + + always_comb //determine whether to round up or not + begin + Mant_roundUp_S = 1'b0; + case (RM_SI) + C_RM_NEAREST : + Mant_roundUp_S = Mant_lower_D[1] && ((Mant_lower_D[0] | Mant_sticky_bit_D )| ( (FP32_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP32]) | (FP64_SI&&Mant_upper_D[0]) | (FP16_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16]) | (FP16ALT_SI&&Mant_upper_D[C_MANT_FP64-C_MANT_FP16ALT]) ) ); + C_RM_TRUNC : + Mant_roundUp_S = 0; + C_RM_PLUSINF : + Mant_roundUp_S = Mant_rounded_S & ~Sign_in_DI; + C_RM_MINUSINF: + Mant_roundUp_S = Mant_rounded_S & Sign_in_DI; + default : + Mant_roundUp_S = 0; + endcase // case (RM_DI) + end // always_comb begin + + logic Mant_renorm_S; + logic [C_MANT_FP64:0] Mant_roundUp_Vector_S; // for all the formats + + assign Mant_roundUp_Vector_S={7'h0,(FP16ALT_SI&&Mant_roundUp_S),2'h0,(FP16_SI&&Mant_roundUp_S),12'h0,(FP32_SI&&Mant_roundUp_S),28'h0,(FP64_SI&&Mant_roundUp_S)}; + + + assign Mant_upperRounded_D = Mant_upper_D + Mant_roundUp_Vector_S; + assign Mant_renorm_S = Mant_upperRounded_D[C_MANT_FP64+1]; + + ///////////////////////////////////////////////////////////////////////////// + // Renormalization for Rounding // + ///////////////////////////////////////////////////////////////////////////// + logic [C_MANT_FP64-1:0] Mant_res_round_D; + logic [C_EXP_FP64-1:0] Exp_res_round_D; + + + assign Mant_res_round_D = (Mant_renorm_S)?Mant_upperRounded_D[C_MANT_FP64:1]:Mant_upperRounded_D[C_MANT_FP64-1:0]; // including the process of the hidden bit + assign Exp_res_round_D = Exp_res_norm_D+Mant_renorm_S; + + ///////////////////////////////////////////////////////////////////////////// + // Output Assignments // + ///////////////////////////////////////////////////////////////////////////// + logic [C_MANT_FP64-1:0] Mant_before_format_ctl_D; + logic [C_EXP_FP64-1:0] Exp_before_format_ctl_D; + assign Mant_before_format_ctl_D = Full_precision_SI ? Mant_res_round_D : Mant_res_norm_D; + assign Exp_before_format_ctl_D = Full_precision_SI ? Exp_res_round_D : Exp_res_norm_D; + + always_comb //NaN Boxing + begin // + if(FP32_SI) + begin + Result_DO ={32'hffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP32-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP32]}; + end + else if(FP64_SI) + begin + Result_DO ={Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP64-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:0]}; + end + else if(FP16_SI) + begin + Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16]}; + end + else + begin + Result_DO ={48'hffff_ffff_ffff,Sign_res_D,Exp_before_format_ctl_D[C_EXP_FP16ALT-1:0],Mant_before_format_ctl_D[C_MANT_FP64-1:C_MANT_FP64-C_MANT_FP16ALT]}; + end + end + +assign In_Exact_S = (~Full_precision_SI) | Mant_rounded_S; +assign Fflags_SO = {NV_OP_S,Div_Zero_S,Exp_OF_S,Exp_UF_S,In_Exact_S}; //{NV,DZ,OF,UF,NX} + +endmodule // norm_div_sqrt_mvp diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv new file mode 100644 index 0000000000..62bd147f61 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv @@ -0,0 +1,104 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 10/04/2018 // +// Design Name: FPU // +// Module Name: nrbd_nrsc_mvp.sv // +// Project Name: Private FPU // +// Language: SystemVerilog // +// // +// Description: non restroring binary divisior/ square root // +// // +// Revision Date: 12/04/2018 // +// Lei Li // +// To address some requirements by Stefan and add low power // +// control for special cases // +// // +//////////////////////////////////////////////////////////////////////////////// + +import defs_div_sqrt_mvp::*; + +module nrbd_nrsc_mvp + + (//Input + input logic Clk_CI, + input logic Rst_RBI, + input logic Div_start_SI, + input logic Sqrt_start_SI, + input logic Start_SI, + input logic Kill_SI, + input logic Special_case_SBI, + input logic Special_case_dly_SBI, + input logic [C_PC-1:0] Precision_ctl_SI, + input logic [1:0] Format_sel_SI, + input logic [C_MANT_FP64:0] Mant_a_DI, + input logic [C_MANT_FP64:0] Mant_b_DI, + input logic [C_EXP_FP64:0] Exp_a_DI, + input logic [C_EXP_FP64:0] Exp_b_DI, + //output + output logic Div_enable_SO, + output logic Sqrt_enable_SO, + + output logic Full_precision_SO, + output logic FP32_SO, + output logic FP64_SO, + output logic FP16_SO, + output logic FP16ALT_SO, + output logic Ready_SO, + output logic Done_SO, + output logic [C_MANT_FP64+4:0] Mant_z_DO, + output logic [C_EXP_FP64+1:0] Exp_z_DO + ); + + + logic Div_start_dly_S,Sqrt_start_dly_S; + + +control_mvp control_U0 +( .Clk_CI (Clk_CI ), + .Rst_RBI (Rst_RBI ), + .Div_start_SI (Div_start_SI ), + .Sqrt_start_SI (Sqrt_start_SI ), + .Start_SI (Start_SI ), + .Kill_SI (Kill_SI ), + .Special_case_SBI (Special_case_SBI ), + .Special_case_dly_SBI (Special_case_dly_SBI ), + .Precision_ctl_SI (Precision_ctl_SI ), + .Format_sel_SI (Format_sel_SI ), + .Numerator_DI (Mant_a_DI ), + .Exp_num_DI (Exp_a_DI ), + .Denominator_DI (Mant_b_DI ), + .Exp_den_DI (Exp_b_DI ), + .Div_start_dly_SO (Div_start_dly_S ), + .Sqrt_start_dly_SO (Sqrt_start_dly_S ), + .Div_enable_SO (Div_enable_SO ), + .Sqrt_enable_SO (Sqrt_enable_SO ), + .Full_precision_SO (Full_precision_SO ), + .FP32_SO (FP32_SO ), + .FP64_SO (FP64_SO ), + .FP16_SO (FP16_SO ), + .FP16ALT_SO (FP16ALT_SO ), + .Ready_SO (Ready_SO ), + .Done_SO (Done_SO ), + .Mant_result_prenorm_DO (Mant_z_DO ), + .Exp_result_prenorm_DO (Exp_z_DO ) +); + + + +endmodule diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv new file mode 100644 index 0000000000..9e0d25f38f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv @@ -0,0 +1,425 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +// Company: IIS @ ETHZ - Federal Institute of Technology // +// // +// Engineers: Lei Li //lile@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// // +// // +// // +// Create Date: 01/03/2018 // +// Design Name: FPU // +// Module Name: preprocess_mvp.sv // +// Project Name: Private FPU // +// Language: SystemVerilog // +// // +// Description: decode and data preparation // +// // +// Revision Date: 12/04/2018 // +// Lei Li // +// To address some requirements by Stefan and add low power // +// control for special cases // +// // +// // +//////////////////////////////////////////////////////////////////////////////// + +import defs_div_sqrt_mvp::*; + +module preprocess_mvp + ( + input logic Clk_CI, + input logic Rst_RBI, + input logic Div_start_SI, + input logic Sqrt_start_SI, + input logic Ready_SI, + //Input Operands + input logic [C_OP_FP64-1:0] Operand_a_DI, + input logic [C_OP_FP64-1:0] Operand_b_DI, + input logic [C_RM-1:0] RM_SI, //Rounding Mode + input logic [C_FS-1:0] Format_sel_SI, // Format Selection + + // to control + output logic Start_SO, + output logic [C_EXP_FP64:0] Exp_a_DO_norm, + output logic [C_EXP_FP64:0] Exp_b_DO_norm, + output logic [C_MANT_FP64:0] Mant_a_DO_norm, + output logic [C_MANT_FP64:0] Mant_b_DO_norm, + + output logic [C_RM-1:0] RM_dly_SO, + + output logic Sign_z_DO, + output logic Inf_a_SO, + output logic Inf_b_SO, + output logic Zero_a_SO, + output logic Zero_b_SO, + output logic NaN_a_SO, + output logic NaN_b_SO, + output logic SNaN_SO, + output logic Special_case_SBO, + output logic Special_case_dly_SBO + ); + + //Hidden Bits + logic Hb_a_D; + logic Hb_b_D; + + logic [C_EXP_FP64-1:0] Exp_a_D; + logic [C_EXP_FP64-1:0] Exp_b_D; + logic [C_MANT_FP64-1:0] Mant_a_NonH_D; + logic [C_MANT_FP64-1:0] Mant_b_NonH_D; + logic [C_MANT_FP64:0] Mant_a_D; + logic [C_MANT_FP64:0] Mant_b_D; + + ///////////////////////////////////////////////////////////////////////////// + // Disassemble operands + ///////////////////////////////////////////////////////////////////////////// + logic Sign_a_D,Sign_b_D; + logic Start_S; + + always_comb + begin + case(Format_sel_SI) + 2'b00: + begin + Sign_a_D = Operand_a_DI[C_OP_FP32-1]; + Sign_b_D = Operand_b_DI[C_OP_FP32-1]; + Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP32-2:C_MANT_FP32]}; + Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP32-2:C_MANT_FP32]}; + Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP32-1:0],29'h0}; + Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP32-1:0],29'h0}; + end + 2'b01: + begin + Sign_a_D = Operand_a_DI[C_OP_FP64-1]; + Sign_b_D = Operand_b_DI[C_OP_FP64-1]; + Exp_a_D = Operand_a_DI[C_OP_FP64-2:C_MANT_FP64]; + Exp_b_D = Operand_b_DI[C_OP_FP64-2:C_MANT_FP64]; + Mant_a_NonH_D = Operand_a_DI[C_MANT_FP64-1:0]; + Mant_b_NonH_D = Operand_b_DI[C_MANT_FP64-1:0]; + end + 2'b10: + begin + Sign_a_D = Operand_a_DI[C_OP_FP16-1]; + Sign_b_D = Operand_b_DI[C_OP_FP16-1]; + Exp_a_D = {6'h00, Operand_a_DI[C_OP_FP16-2:C_MANT_FP16]}; + Exp_b_D = {6'h00, Operand_b_DI[C_OP_FP16-2:C_MANT_FP16]}; + Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16-1:0],42'h0}; + Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16-1:0],42'h0}; + end + 2'b11: + begin + Sign_a_D = Operand_a_DI[C_OP_FP16ALT-1]; + Sign_b_D = Operand_b_DI[C_OP_FP16ALT-1]; + Exp_a_D = {3'h0, Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; + Exp_b_D = {3'h0, Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT]}; + Mant_a_NonH_D = {Operand_a_DI[C_MANT_FP16ALT-1:0],45'h0}; + Mant_b_NonH_D = {Operand_b_DI[C_MANT_FP16ALT-1:0],45'h0}; + end + endcase + end + + + assign Mant_a_D = {Hb_a_D,Mant_a_NonH_D}; + assign Mant_b_D = {Hb_b_D,Mant_b_NonH_D}; + + assign Hb_a_D = | Exp_a_D; // hidden bit + assign Hb_b_D = | Exp_b_D; // hidden bit + + assign Start_S= Div_start_SI | Sqrt_start_SI; + + + + ///////////////////////////////////////////////////////////////////////////// + // preliminary checks for infinite/zero/NaN operands // + ///////////////////////////////////////////////////////////////////////////// + + logic Mant_a_prenorm_zero_S; + logic Mant_b_prenorm_zero_S; + + logic Exp_a_prenorm_zero_S; + logic Exp_b_prenorm_zero_S; + assign Exp_a_prenorm_zero_S = ~Hb_a_D; + assign Exp_b_prenorm_zero_S = ~Hb_b_D; + + logic Exp_a_prenorm_Inf_NaN_S; + logic Exp_b_prenorm_Inf_NaN_S; + + logic Mant_a_prenorm_QNaN_S; + logic Mant_a_prenorm_SNaN_S; + logic Mant_b_prenorm_QNaN_S; + logic Mant_b_prenorm_SNaN_S; + + assign Mant_a_prenorm_QNaN_S=Mant_a_NonH_D[C_MANT_FP64-1]&&(~(|Mant_a_NonH_D[C_MANT_FP64-2:0])); + assign Mant_a_prenorm_SNaN_S=(~Mant_a_NonH_D[C_MANT_FP64-1])&&((|Mant_a_NonH_D[C_MANT_FP64-2:0])); + assign Mant_b_prenorm_QNaN_S=Mant_b_NonH_D[C_MANT_FP64-1]&&(~(|Mant_b_NonH_D[C_MANT_FP64-2:0])); + assign Mant_b_prenorm_SNaN_S=(~Mant_b_NonH_D[C_MANT_FP64-1])&&((|Mant_b_NonH_D[C_MANT_FP64-2:0])); + + always_comb + begin + case(Format_sel_SI) + 2'b00: + begin + Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); + Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP32-1:0] == C_MANT_ZERO_FP32); + Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); + Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP32-2:C_MANT_FP32] == C_EXP_INF_FP32); + end + 2'b01: + begin + Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); + Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP64-1:0] == C_MANT_ZERO_FP64); + Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); + Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP64-2:C_MANT_FP64] == C_EXP_INF_FP64); + end + 2'b10: + begin + Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); + Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16-1:0] == C_MANT_ZERO_FP16); + Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); + Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16-2:C_MANT_FP16] == C_EXP_INF_FP16); + end + 2'b11: + begin + Mant_a_prenorm_zero_S=(Operand_a_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); + Mant_b_prenorm_zero_S=(Operand_b_DI[C_MANT_FP16ALT-1:0] == C_MANT_ZERO_FP16ALT); + Exp_a_prenorm_Inf_NaN_S=(Operand_a_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); + Exp_b_prenorm_Inf_NaN_S=(Operand_b_DI[C_OP_FP16ALT-2:C_MANT_FP16ALT] == C_EXP_INF_FP16ALT); + end + endcase + end + + + + + logic Zero_a_SN,Zero_a_SP; + logic Zero_b_SN,Zero_b_SP; + logic Inf_a_SN,Inf_a_SP; + logic Inf_b_SN,Inf_b_SP; + logic NaN_a_SN,NaN_a_SP; + logic NaN_b_SN,NaN_b_SP; + logic SNaN_SN,SNaN_SP; + + assign Zero_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_zero_S&&Mant_a_prenorm_zero_S):Zero_a_SP; + assign Zero_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_zero_S&&Mant_b_prenorm_zero_S):Zero_b_SP; + assign Inf_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&Mant_a_prenorm_zero_S):Inf_a_SP; + assign Inf_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&Mant_b_prenorm_zero_S):Inf_b_SP; + assign NaN_a_SN = (Start_S&&Ready_SI)?(Exp_a_prenorm_Inf_NaN_S&&(~Mant_a_prenorm_zero_S)):NaN_a_SP; + assign NaN_b_SN = (Start_S&&Ready_SI)?(Exp_b_prenorm_Inf_NaN_S&&(~Mant_b_prenorm_zero_S)):NaN_b_SP; + assign SNaN_SN = (Start_S&&Ready_SI) ? ((Mant_a_prenorm_SNaN_S&&NaN_a_SN) | (Mant_b_prenorm_SNaN_S&&NaN_b_SN)) : SNaN_SP; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Zero_a_SP <='0; + Zero_b_SP <='0; + Inf_a_SP <='0; + Inf_b_SP <='0; + NaN_a_SP <='0; + NaN_b_SP <='0; + SNaN_SP <= '0; + end + else + begin + Inf_a_SP <=Inf_a_SN; + Inf_b_SP <=Inf_b_SN; + Zero_a_SP <=Zero_a_SN; + Zero_b_SP <=Zero_b_SN; + NaN_a_SP <=NaN_a_SN; + NaN_b_SP <=NaN_b_SN; + SNaN_SP <= SNaN_SN; + end + end + + ///////////////////////////////////////////////////////////////////////////// + // Low power control + ///////////////////////////////////////////////////////////////////////////// + + assign Special_case_SBO=(~{(Div_start_SI)?(Zero_a_SN | Zero_b_SN | Inf_a_SN | Inf_b_SN | NaN_a_SN | NaN_b_SN): (Zero_a_SN | Inf_a_SN | NaN_a_SN | Sign_a_D) })&&(Start_S&&Ready_SI); + + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Special_case_dly_SBO <= '0; + end + else if((Start_S&&Ready_SI)) + begin + Special_case_dly_SBO <= Special_case_SBO; + end + else if(Special_case_dly_SBO) + begin + Special_case_dly_SBO <= 1'b1; + end + else + begin + Special_case_dly_SBO <= '0; + end + end + + ///////////////////////////////////////////////////////////////////////////// + // Delay sign for normalization and round // + ///////////////////////////////////////////////////////////////////////////// + + logic Sign_z_DN; + logic Sign_z_DP; + + always_comb + begin + if(Div_start_SI&&Ready_SI) + Sign_z_DN = Sign_a_D ^ Sign_b_D; + else if(Sqrt_start_SI&&Ready_SI) + Sign_z_DN = Sign_a_D; + else + Sign_z_DN = Sign_z_DP; + end + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Sign_z_DP <= '0; + end + else + begin + Sign_z_DP <= Sign_z_DN; + end + end + + logic [C_RM-1:0] RM_DN; + logic [C_RM-1:0] RM_DP; + + always_comb + begin + if(Start_S&&Ready_SI) + RM_DN = RM_SI; + else + RM_DN = RM_DP; + end + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + RM_DP <= '0; + end + else + begin + RM_DP <= RM_DN; + end + end + assign RM_dly_SO = RM_DP; + + logic [5:0] Mant_leadingOne_a, Mant_leadingOne_b; + logic Mant_zero_S_a,Mant_zero_S_b; + + lzc #( + .WIDTH ( C_MANT_FP64+1 ), + .MODE ( 1 ) + ) LOD_Ua ( + .in_i ( Mant_a_D ), + .cnt_o ( Mant_leadingOne_a ), + .empty_o ( Mant_zero_S_a ) + ); + + logic [C_MANT_FP64:0] Mant_a_norm_DN,Mant_a_norm_DP; + + assign Mant_a_norm_DN = ((Start_S&&Ready_SI))?(Mant_a_D<<(Mant_leadingOne_a)):Mant_a_norm_DP; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Mant_a_norm_DP <= '0; + end + else + begin + Mant_a_norm_DP<=Mant_a_norm_DN; + end + end + + logic [C_EXP_FP64:0] Exp_a_norm_DN,Exp_a_norm_DP; + assign Exp_a_norm_DN = ((Start_S&&Ready_SI))?(Exp_a_D-Mant_leadingOne_a+(|Mant_leadingOne_a)):Exp_a_norm_DP; //Covering the process of denormal numbers + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Exp_a_norm_DP <= '0; + end + else + begin + Exp_a_norm_DP<=Exp_a_norm_DN; + end + end + + lzc #( + .WIDTH ( C_MANT_FP64+1 ), + .MODE ( 1 ) + ) LOD_Ub ( + .in_i ( Mant_b_D ), + .cnt_o ( Mant_leadingOne_b ), + .empty_o ( Mant_zero_S_b ) + ); + + + logic [C_MANT_FP64:0] Mant_b_norm_DN,Mant_b_norm_DP; + + assign Mant_b_norm_DN = ((Start_S&&Ready_SI))?(Mant_b_D<<(Mant_leadingOne_b)):Mant_b_norm_DP; + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Mant_b_norm_DP <= '0; + end + else + begin + Mant_b_norm_DP<=Mant_b_norm_DN; + end + end + + logic [C_EXP_FP64:0] Exp_b_norm_DN,Exp_b_norm_DP; + assign Exp_b_norm_DN = ((Start_S&&Ready_SI))?(Exp_b_D-Mant_leadingOne_b+(|Mant_leadingOne_b)):Exp_b_norm_DP; //Covering the process of denormal numbers + + always_ff @(posedge Clk_CI, negedge Rst_RBI) + begin + if(~Rst_RBI) + begin + Exp_b_norm_DP <= '0; + end + else + begin + Exp_b_norm_DP<=Exp_b_norm_DN; + end + end + + ///////////////////////////////////////////////////////////////////////////// + // Output assignments // + ///////////////////////////////////////////////////////////////////////////// + + assign Start_SO=Start_S; + assign Exp_a_DO_norm=Exp_a_norm_DP; + assign Exp_b_DO_norm=Exp_b_norm_DP; + assign Mant_a_DO_norm=Mant_a_norm_DP; + assign Mant_b_DO_norm=Mant_b_norm_DP; + assign Sign_z_DO=Sign_z_DP; + assign Inf_a_SO=Inf_a_SP; + assign Inf_b_SO=Inf_b_SP; + assign Zero_a_SO=Zero_a_SP; + assign Zero_b_SO=Zero_b_SP; + assign NaN_a_SO=NaN_a_SP; + assign NaN_b_SO=NaN_b_SP; + assign SNaN_SO=SNaN_SP; + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_compressed_if_driver.sv b/flow/designs/src/cva6/core/cvxif_compressed_if_driver.sv new file mode 100644 index 0000000000..ab759f8e4c --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_compressed_if_driver.sv @@ -0,0 +1,66 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +module cvxif_compressed_if_driver #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type x_compressed_req_t = logic, + parameter type x_compressed_resp_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + input logic flush_i, + // CVA6 Hart id + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + + input logic is_compressed_i, + input logic is_illegal_i, + input logic [31:0] instruction_i, + + output logic is_compressed_o, + output logic is_illegal_o, + output logic [31:0] instruction_o, + input logic stall_i, + output logic stall_o, + // CVXIF Compressed interface + input logic compressed_ready_i, + input x_compressed_resp_t compressed_resp_i, + output logic compressed_valid_o, + output x_compressed_req_t compressed_req_o +); + + + always_comb begin + is_illegal_o = is_illegal_i; + instruction_o = instruction_i; + is_compressed_o = is_compressed_i; + compressed_valid_o = 1'b0; + compressed_req_o.instr = '0; + compressed_req_o.hartid = hart_id_i; + stall_o = stall_i; + if (is_illegal_i) begin + compressed_valid_o = is_illegal_i; + compressed_req_o.instr = instruction_i[15:0]; + is_illegal_o = ~compressed_resp_i.accept; + instruction_o = compressed_resp_i.accept ? compressed_resp_i.instr : instruction_i; + is_compressed_o = compressed_resp_i.accept ? 1'b0 : is_compressed_i; + if (~stall_i) begin + // Propagate stall from macro decoder or wait for compressed ready if compressed transaction is happening. + stall_o = (compressed_valid_o && ~compressed_ready_i); + end + end + if (flush_i) begin + compressed_valid_o = 1'b0; + compressed_req_o.instr = '0; + compressed_req_o.hartid = hart_id_i; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_example/compressed_instr_decoder.sv b/flow/designs/src/cva6/core/cvxif_example/compressed_instr_decoder.sv new file mode 100644 index 0000000000..de2fbb391c --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/compressed_instr_decoder.sv @@ -0,0 +1,49 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +module compressed_instr_decoder #( + parameter type copro_compressed_resp_t = logic, + parameter int NbInstr = 1, + parameter copro_compressed_resp_t CoproInstr [NbInstr] = {0}, + parameter type x_compressed_req_t = logic, + parameter type x_compressed_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic compressed_valid_i, + input x_compressed_req_t compressed_req_i, + output logic compressed_ready_o, + output x_compressed_resp_t compressed_resp_o +); + + logic [NbInstr-1:0] sel; + + for (genvar i = 0; i < NbInstr; i++) begin : gen_predecoder_selector + assign sel[i] = ((CoproInstr[i].mask & compressed_req_i.instr) == CoproInstr[i].instr); + end + + always_comb begin + compressed_ready_o = '1; + compressed_resp_o.accept = '0; + compressed_resp_o.instr = '0; + for (int unsigned i = 0; i < NbInstr; i++) begin + if (sel[i] && compressed_valid_i) begin + compressed_resp_o.accept = CoproInstr[i].resp.accept; + compressed_resp_o.instr = CoproInstr[i].resp.instr; + // Remap rs1 and rs2 + compressed_resp_o.instr[19:15] = compressed_req_i.instr[11:7]; + compressed_resp_o.instr[24:20] = compressed_req_i.instr[6:2]; + end + end + end + + assert property (@(posedge clk_i) $onehot0(sel)) + else $warning("This offloaded instruction is valid for multiple coprocessor instructions !"); + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_example/copro_alu.sv b/flow/designs/src/cva6/core/cvxif_example/copro_alu.sv new file mode 100644 index 0000000000..4e980ffea4 --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/copro_alu.sv @@ -0,0 +1,160 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +module copro_alu + import cvxif_instr_pkg::*; +#( + parameter int unsigned NrRgprPorts = 2, + parameter int unsigned XLEN = 32, + parameter type hartid_t = logic, + parameter type id_t = logic, + parameter type registers_t = logic + +) ( + input logic clk_i, + input logic rst_ni, + input registers_t registers_i, + input opcode_t opcode_i, + input hartid_t hartid_i, + input id_t id_i, + input logic [ 4:0] rd_i, + output logic [XLEN-1:0] result_o, + output hartid_t hartid_o, + output id_t id_o, + output logic [ 4:0] rd_o, + output logic valid_o, + output logic we_o +); + + logic [XLEN-1:0] result_n, result_q; + hartid_t hartid_n, hartid_q; + id_t id_n, id_q; + logic valid_n, valid_q; + logic [4:0] rd_n, rd_q; + logic we_n, we_q; + + assign result_o = result_q; + assign hartid_o = hartid_q; + assign id_o = id_q; + assign valid_o = valid_q; + assign rd_o = rd_q; + assign we_o = we_q; + + always_comb begin + case (opcode_i) + cvxif_instr_pkg::NOP: begin + result_n = '0; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = '0; + we_n = '0; + end + cvxif_instr_pkg::ADD: begin + result_n = registers_i[1] + registers_i[0]; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::DOUBLE_RS1: begin + result_n = registers_i[0] + registers_i[0]; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::DOUBLE_RS2: begin + result_n = registers_i[1] + registers_i[1]; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::ADD_MULTI: begin + result_n = registers_i[1] + registers_i[0]; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::MADD_RS3_R4: begin + result_n = NrRgprPorts == 3 ? (registers_i[0] + registers_i[1] + registers_i[2]) : (registers_i[0] + registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::MSUB_RS3_R4: begin + result_n = NrRgprPorts == 3 ? (registers_i[0] - registers_i[1] - registers_i[2]) : (registers_i[0] - registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::NMADD_RS3_R4: begin + result_n = NrRgprPorts == 3 ? ~(registers_i[0] + registers_i[1] + registers_i[2]) : ~(registers_i[0] + registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::NMSUB_RS3_R4: begin + result_n = NrRgprPorts == 3 ? ~(registers_i[0] - registers_i[1] - registers_i[2]) : ~(registers_i[0] - registers_i[1]); + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = rd_i; + we_n = 1'b1; + end + cvxif_instr_pkg::ADD_RS3_R: begin + result_n = NrRgprPorts == 3 ? registers_i[2] + registers_i[1] + registers_i[0] : registers_i[1] + registers_i[0]; + hartid_n = hartid_i; + id_n = id_i; + valid_n = 1'b1; + rd_n = 5'b01010; + we_n = 1'b1; + end + default: begin + result_n = '0; + hartid_n = '0; + id_n = '0; + valid_n = '0; + rd_n = '0; + we_n = '0; + end + endcase + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + result_q <= '0; + hartid_q <= '0; + id_q <= '0; + valid_q <= '0; + rd_q <= '0; + we_q <= '0; + end else begin + result_q <= result_n; + hartid_q <= hartid_n; + id_q <= id_n; + valid_q <= valid_n; + rd_q <= rd_n; + we_q <= we_n; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_example/include/cvxif_instr_pkg.sv b/flow/designs/src/cva6/core/cvxif_example/include/cvxif_instr_pkg.sv new file mode 100644 index 0000000000..496cddba8f --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/include/cvxif_instr_pkg.sv @@ -0,0 +1,154 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon (guillaume.chauvon@thalesgroup.com) + + + +package cvxif_instr_pkg; + + typedef enum logic [3:0] { + ILLEGAL = 4'b0000, + NOP = 4'b0001, + ADD = 4'b0010, + DOUBLE_RS1 = 4'b0011, + DOUBLE_RS2 = 4'b0100, + ADD_MULTI = 4'b0101, + MADD_RS3_R4 = 4'b0110, + MSUB_RS3_R4 = 4'b0111, + NMADD_RS3_R4 = 4'b1000, + NMSUB_RS3_R4 = 4'b1001, + ADD_RS3_R = 4'b1111 + } opcode_t; + + + typedef struct packed { + logic accept; + logic writeback; // TODO depends on dualwrite + logic [2:0] register_read; // TODO Nr read ports + } issue_resp_t; + + typedef struct packed { + logic accept; + logic [31:0] instr; + } compressed_resp_t; + + typedef struct packed { + logic [31:0] instr; + logic [31:0] mask; + issue_resp_t resp; + opcode_t opcode; + } copro_issue_resp_t; + + + typedef struct packed { + logic [15:0] instr; + logic [15:0] mask; + compressed_resp_t resp; + } copro_compressed_resp_t; + + // 4 Possible RISCV instructions for Coprocessor + parameter int unsigned NbInstr = 10; + parameter copro_issue_resp_t CoproInstr[NbInstr] = '{ + '{ + // Custom Nop + instr: + 32'b00000_00_00000_00000_0_00_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b0, register_read : {1'b0, 1'b0, 1'b0}}, + opcode : NOP + }, + '{ + // Custom Add : cus_add rd, rs1, rs2 + instr: + 32'b00000_00_00000_00000_0_01_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b0, 1'b1, 1'b1}}, + opcode : ADD + }, + '{ + // Custom Add rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_01_00000_00000_0_01_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b0, 1'b0, 1'b1}}, + opcode : DOUBLE_RS1 + }, + '{ + // Custom Add rs2 : cus_add rd, rs2, rs2 + instr: + 32'b00000_10_00000_00000_0_01_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b0, 1'b1, 1'b0}}, + opcode : DOUBLE_RS2 + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_11_00000_00000_0_01_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b0, 1'b1, 1'b1}}, + opcode : ADD_MULTI + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00001_00_00000_00000_0_01_00000_1111011, // custom3 opcode + mask: 32'b11111_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, + opcode : ADD_RS3_R + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_00_00000_00000_0_00_00000_1000011, // MADD opcode + mask: 32'b00000_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, + opcode : MADD_RS3_R4 + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_00_00000_00000_0_00_00000_1000111, // MSUB opcode + mask: 32'b00000_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, + opcode : MSUB_RS3_R4 + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_00_00000_00000_0_00_00000_1001011, // NMSUB opcode + mask: 32'b00000_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, + opcode : NMSUB_RS3_R4 + }, + '{ + // Custom Add Multi rs1 : cus_add rd, rs1, rs1 + instr: + 32'b00000_00_00000_00000_0_00_00000_1001111, // NMADD opcode + mask: 32'b00000_11_00000_00000_1_11_00000_1111111, + resp : '{accept : 1'b1, writeback : 1'b1, register_read : {1'b1, 1'b1, 1'b1}}, + opcode : NMADD_RS3_R4 + } + }; + + parameter int unsigned NbCompInstr = 2; + parameter copro_compressed_resp_t CoproCompInstr[NbCompInstr] = '{ + // C_NOP + '{ + instr : 16'b111_0_00000_00000_00, + mask : 16'b111_1_00000_00000_11, + resp : '{accept : 1'b1, instr : 32'b00000_00_00000_00000_0_00_00000_1111011} + }, + '{ + instr : 16'b111_1_00000_00000_00, + mask : 16'b111_1_00000_00000_11, + resp : '{accept : 1'b1, instr : 32'b00000_00_00000_00000_0_01_01010_1111011} + } + }; + +endpackage diff --git a/flow/designs/src/cva6/core/cvxif_example/instr_decoder.sv b/flow/designs/src/cva6/core/cvxif_example/instr_decoder.sv new file mode 100644 index 0000000000..8e952b6dfe --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/instr_decoder.sv @@ -0,0 +1,89 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +module instr_decoder #( + parameter type copro_issue_resp_t = logic, + parameter type opcode_t = logic, + parameter int NbInstr = 1, + parameter copro_issue_resp_t CoproInstr [NbInstr] = {0}, + parameter int unsigned NrRgprPorts = 2, + parameter type hartid_t = logic, + parameter type id_t = logic, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type registers_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic issue_valid_i, + input x_issue_req_t issue_req_i, + output logic issue_ready_o, + output x_issue_resp_t issue_resp_o, + input logic register_valid_i, + input x_register_t register_i, + output registers_t registers_o, + output opcode_t opcode_o, + output hartid_t hartid_o, + output id_t id_o, + output logic [4:0] rd_o +); + + logic [NbInstr-1:0] sel; + logic rs1_ready; + logic rs2_ready; + logic rs3_ready; + + for (genvar i = 0; i < NbInstr; i++) begin : gen_predecoder_selector + assign sel[i] = ((CoproInstr[i].mask & issue_req_i.instr) == CoproInstr[i].instr); + end + + always_comb begin + rs1_ready = '0; + rs2_ready = '0; + rs3_ready = '0; + issue_ready_o = '0; + issue_resp_o.accept = '0; + issue_resp_o.writeback = '0; + issue_resp_o.register_read = '0; + registers_o = '0; + opcode_o = opcode_t'(0); // == ILLEGAL see cvxif_instr_pkg.sv + hartid_o = '0; + id_o = '0; + rd_o = '0; + for (int unsigned i = 0; i < NbInstr; i++) begin + if (sel[i] && issue_valid_i) begin + issue_resp_o.accept = CoproInstr[i].resp.accept; + issue_resp_o.writeback = CoproInstr[i].resp.writeback; + issue_resp_o.register_read = CoproInstr[i].resp.register_read; // Warning : potential 3 bits vector into 2 bits one + if (issue_resp_o.accept) begin + rs1_ready = (~CoproInstr[i].resp.register_read[0] || register_i.rs_valid[0]); + rs2_ready = (~CoproInstr[i].resp.register_read[1] || register_i.rs_valid[1]); + rs3_ready = NrRgprPorts == 3 ? (~CoproInstr[i].resp.register_read[2] || register_i.rs_valid[2]) : 1'b1; + issue_ready_o = rs1_ready && rs2_ready && rs3_ready; + end + opcode_o = CoproInstr[i].opcode; + id_o = issue_req_i.id; + hartid_o = issue_req_i.hartid; + rd_o = issue_req_i.instr[11:7]; + for (int unsigned j = 0; j < NrRgprPorts; j++) begin + registers_o[j] = issue_resp_o.register_read[j] ? register_i.rs[j] : '0; + end + end + end + // Coprocessor could not decode offloaded instruction -> instruction is not accepted + if (issue_valid_i && ~(|sel)) begin + issue_ready_o = 1'b1; + end + end + + assert property (@(posedge clk_i) $onehot0(sel)) + else $warning("This offloaded instruction is valid for multiple coprocessor instructions !"); + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_fu.sv b/flow/designs/src/cva6/core/cvxif_fu.sv new file mode 100644 index 0000000000..cf6ee15215 --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_fu.sv @@ -0,0 +1,73 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +// Functional Unit for the CoreV-X-Interface +// Handles Result interface and exception forwarding to next stages. + + +module cvxif_fu + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, + parameter type x_result_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // CVXIF instruction is valid - ISSUE_STAGE + input logic x_valid_i, + // Transaction ID - ISSUE_STAGE + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i, + // Instruction is illegal, determined during CVXIF issue transaction - ISSUE_STAGE + input logic x_illegal_i, + // Offloaded instruction - ISSUE_STAGE + input logic [ 31:0] x_off_instr_i, + // CVXIF is ready - ISSUE_STAGE + output logic x_ready_o, + // CVXIF result transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_o, + // CVXIF exception - ISSUE_STAGE + output exception_t x_exception_o, + // CVXIF FU result - ISSUE_STAGE + output logic [ CVA6Cfg.XLEN-1:0] x_result_o, + // CVXIF result valid - ISSUE_STAGE + output logic x_valid_o, + // CVXIF write enable - ISSUE_STAGE + output logic x_we_o, + // CVXIF destination register - ISSUE_STAGE + output logic [ 4:0] x_rd_o, + // CVXIF result interface + input logic result_valid_i, + input x_result_t result_i, + output logic result_ready_o +); + + + + assign result_ready_o = 1'b1; + + assign x_ready_o = 1'b1; // Readyness of cvxif_fu is determined in issue stage by CVXIF issue interface + // Result signals + assign x_valid_o = x_illegal_i || result_valid_i; + assign x_result_o = result_i.data; + assign x_trans_id_o = x_illegal_i ? x_trans_id_i : result_i.id; + assign x_we_o = result_i.we; + assign x_rd_o = result_i.rd; + + // Handling of illegal instruction exception + always_comb begin + x_exception_o.valid = x_illegal_i; + x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0; + if (CVA6Cfg.TvalEn) + x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO. + end + +endmodule diff --git a/flow/designs/src/cva6/core/cvxif_issue_register_commit_if_driver.sv b/flow/designs/src/cva6/core/cvxif_issue_register_commit_if_driver.sv new file mode 100644 index 0000000000..88efc0002d --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_issue_register_commit_if_driver.sv @@ -0,0 +1,66 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Guillaume Chauvon + +module cvxif_issue_register_commit_if_driver #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type x_commit_t = logic +) ( + // CVA6 inputs + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + // CVXIF Issue interface + input logic issue_ready_i, + input x_issue_resp_t issue_resp_i, + output logic issue_valid_o, + output x_issue_req_t issue_req_o, + // CVXIF Register interface + input logic register_ready_i, + output logic register_valid_o, + output x_register_t register_o, + // CVXIF Commit interface + output logic commit_valid_o, + output x_commit_t commit_o, + // IRO in/out + input logic valid_i, + input logic [31:0] x_off_instr_i, + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i, + input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i, + input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i +); + // X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone + // Mandatory assignement + assign register_valid_o = issue_valid_o; + assign register_o.hartid = issue_req_o.hartid; + assign register_o.id = issue_req_o.id; + + always_comb begin + issue_valid_o = valid_i && ~flush_i; + issue_req_o.instr = x_off_instr_i; + issue_req_o.hartid = hart_id_i; + issue_req_o.id = x_trans_id_i; + register_o.rs = register_i; + register_o.rs_valid = rs_valid_i; + end + + /* WARNING */ + // Always commit since speculation in execute in not possible : TODO to be verified + + // Always do commit transaction with issue + // If instruction goes to execute then it is not speculative + assign commit_valid_o = issue_valid_o && issue_ready_i; + assign commit_o.hartid = issue_req_o.hartid; + assign commit_o.id = issue_req_o.id; + assign commit_o.commit_kill = 1'b0; + +endmodule diff --git a/flow/designs/src/cva6/core/decoder.sv b/flow/designs/src/cva6/core/decoder.sv new file mode 100644 index 0000000000..de52e7f232 --- /dev/null +++ b/flow/designs/src/cva6/core/decoder.sv @@ -0,0 +1,1722 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// File: issue_read_operands.sv +// Author: Florian Zaruba +// Date: 8.4.2017 +// +// Copyright (C) 2017 ETH Zurich, University of Bologna +// All rights reserved. +// +// Description: Issues instruction from the scoreboard and fetches the operands +// This also includes all the forwarding logic +// + +module decoder + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, + parameter type irq_ctrl_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type interrupts_t = logic, + parameter interrupts_t INTERRUPTS = '0 +) ( + // Debug (async) request - SUBSYSTEM + input logic debug_req_i, + // PC from fetch stage - FRONTEND + input logic [CVA6Cfg.VLEN-1:0] pc_i, + // Is a compressed instruction - compressed_decoder + input logic is_compressed_i, + // Compressed form of instruction - FRONTEND + input logic [15:0] compressed_instr_i, + // Illegal compressed instruction - compressed_decoder + input logic is_illegal_i, + // Instruction from fetch stage - FRONTEND + input logic [31:0] instruction_i, + // Is a macro instruction - macro_decoder + input logic is_macro_instr_i, + // Is a last macro instruction - macro_decoder + input logic is_last_macro_instr_i, + // Is mvsa01/mva01s macro instruction - macro_decoder + input logic is_double_rd_macro_instr_i, + // Zcmt instruction - FRONTEND + input logic is_zcmt_i, + // Jump address - zcmt_decoder + input logic [CVA6Cfg.XLEN-1:0] jump_address_i, + // Is a branch predict instruction - FRONTEND + input branchpredict_sbe_t branch_predict_i, + // If an exception occured in fetch stage - FRONTEND + input exception_t ex_i, + // Level sensitive (async) interrupts - SUBSYSTEM + input logic [1:0] irq_i, + // Interrupt control status - CSR_REGFILE + input irq_ctrl_t irq_ctrl_i, + // Current privilege level - CSR_REGFILE + input riscv::priv_lvl_t priv_lvl_i, + // Current virtualization mode - CSR_REGFILE + input logic v_i, + // Is debug mode - CSR_REGFILE + input logic debug_mode_i, + // Floating point extension status - CSR_REGFILE + input riscv::xs_t fs_i, + // Virtual floating point extension status - CSR_REGFILE + input riscv::xs_t vfs_i, + // Floating-point dynamic rounding mode - CSR_REGFILE + input logic [2:0] frm_i, + // Vector extension status - CSR_REGFILE + input riscv::xs_t vs_i, + // Trap virtual memory - CSR_REGFILE + input logic tvm_i, + // Timeout wait - CSR_REGFILE + input logic tw_i, + // Virtual timeout wait - CSR_REGFILE + input logic vtw_i, + // Trap sret - CSR_REGFILE + input logic tsr_i, + // Hypervisor user mode - CSR_REGFILE + input logic hu_i, + // Instruction to be added to scoreboard entry - ISSUE_STAGE + output scoreboard_entry_t instruction_o, + // Instruction - ISSUE_STAGE + output logic [31:0] orig_instr_o, + // Is a control flow instruction - ISSUE_STAGE + output logic is_control_flow_instr_o +); + logic illegal_instr; + logic illegal_instr_bm; + logic illegal_instr_zic; + logic illegal_instr_non_bm; + logic virtual_illegal_instr; + // this instruction is an environment call (ecall), it is handled like an exception + logic ecall; + // this instruction is a software break-point + logic ebreak; + // this instruction needs floating-point rounding-mode verification + logic check_fprm; + riscv::instruction_t instr; + assign instr = riscv::instruction_t'(instruction_i); + // transformed instruction + logic [31:0] tinst; + // -------------------- + // Immediate select + // -------------------- + enum logic [3:0] { + NOIMM, + IIMM, + SIMM, + SBIMM, + UIMM, + JIMM, + RS3, + MUX_RD_RS3 + } imm_select; + + logic [CVA6Cfg.XLEN-1:0] imm_i_type; + logic [CVA6Cfg.XLEN-1:0] imm_s_type; + logic [CVA6Cfg.XLEN-1:0] imm_sb_type; + logic [CVA6Cfg.XLEN-1:0] imm_u_type; + logic [CVA6Cfg.XLEN-1:0] imm_uj_type; + + // --------------------------------------- + // Accelerator instructions' first-pass decoder + // --------------------------------------- + logic is_accel; + scoreboard_entry_t acc_instruction; + logic acc_illegal_instr; + logic acc_is_control_flow_instr; + + if (CVA6Cfg.EnableAccelerator) begin : gen_accel_decoder + // This module is responsible for a light-weight decoding of accelerator instructions, + // identifying them, but also whether they read/write scalar registers. + // Accelerators are supposed to define this module. + cva6_accel_first_pass_decoder #( + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) + ) i_accel_decoder ( + .instruction_i(instruction_i), + .fs_i(fs_i), + .vs_i(vs_i), + .is_accel_o(is_accel), + .instruction_o(acc_instruction), + .illegal_instr_o(acc_illegal_instr), + .is_control_flow_instr_o(acc_is_control_flow_instr) + ); + end : gen_accel_decoder + else begin + assign is_accel = 1'b0; + assign acc_instruction = '0; + assign acc_illegal_instr = 1'b1; // this should never propagate + assign acc_is_control_flow_instr = 1'b0; + end + + always_comb begin : decoder + + imm_select = NOIMM; + is_control_flow_instr_o = 1'b0; + illegal_instr = 1'b0; + illegal_instr_non_bm = 1'b0; + illegal_instr_bm = 1'b0; + illegal_instr_zic = 1'b0; + virtual_illegal_instr = 1'b0; + instruction_o.pc = pc_i; + instruction_o.trans_id = '0; + instruction_o.fu = NONE; + instruction_o.op = ariane_pkg::ADD; + instruction_o.rs1 = '0; + instruction_o.rs2 = '0; + instruction_o.rd = '0; + instruction_o.use_pc = 1'b0; + instruction_o.is_compressed = is_compressed_i; + instruction_o.is_macro_instr = is_macro_instr_i; + instruction_o.is_last_macro_instr = is_last_macro_instr_i; + instruction_o.is_double_rd_macro_instr = is_double_rd_macro_instr_i; + instruction_o.use_zimm = 1'b0; + instruction_o.bp = branch_predict_i; + instruction_o.vfp = 1'b0; + instruction_o.is_zcmt = is_zcmt_i; + ecall = 1'b0; + ebreak = 1'b0; + check_fprm = 1'b0; + + if (~ex_i.valid) begin + case (instr.rtype.opcode) + riscv::OpcodeSystem: begin + instruction_o.fu = CSR; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rs2 = instr.rtype.rs2; //TODO: needs to be checked if better way is available + instruction_o.rd = instr.itype.rd; + + unique case (instr.itype.funct3) + 3'b000: begin + // check if the RD and and RS1 fields are zero, this may be reset for the SENCE.VMA instruction + if (instr.itype.rs1 != '0 || instr.itype.rd != '0) begin + if (CVA6Cfg.RVH && v_i) begin + virtual_illegal_instr = 1'b1; + end else begin + illegal_instr = 1'b1; + end + end + // decode the immiediate field + case (instr.itype.imm) + // ECALL -> inject exception + 12'b0: ecall = 1'b1; + // EBREAK -> inject exception + 12'b1: ebreak = 1'b1; + // SRET + 12'b1_0000_0010: begin + if (CVA6Cfg.RVS) begin + instruction_o.op = ariane_pkg::SRET; + // check privilege level, SRET can only be executed in S and M mode + // we'll just decode an illegal instruction if we are in the wrong privilege level + if (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U) begin + if (CVA6Cfg.RVH && v_i) begin + virtual_illegal_instr = 1'b1; + end else begin + illegal_instr = 1'b1; + end + // do not change privilege level if this is an illegal instruction + instruction_o.op = ariane_pkg::ADD; + end + // if we are in S-Mode and Trap SRET (tsr) is set -> trap on illegal instruction + if (priv_lvl_i == riscv::PRIV_LVL_S && tsr_i) begin + if (CVA6Cfg.RVH && v_i) begin + virtual_illegal_instr = 1'b1; + end else begin + illegal_instr = 1'b1; + end + // do not change privilege level if this is an illegal instruction + instruction_o.op = ariane_pkg::ADD; + end + end else begin + illegal_instr = 1'b1; + instruction_o.op = ariane_pkg::ADD; + end + end + // MRET + 12'b11_0000_0010: begin + instruction_o.op = ariane_pkg::MRET; + // check privilege level, MRET can only be executed in M mode + // otherwise we decode an illegal instruction + if ((CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) + illegal_instr = 1'b1; + end + // DRET + 12'b111_1011_0010: begin + instruction_o.op = ariane_pkg::DRET; + if (CVA6Cfg.DebugEn) begin + // check that we are in debug mode when executing this instruction + illegal_instr = (!debug_mode_i) ? 1'b1 : illegal_instr; + end else begin + illegal_instr = 1'b1; + end + end + // WFI + 12'b1_0000_0101: begin + instruction_o.op = ariane_pkg::WFI; + // if timeout wait is set, trap on an illegal instruction in S Mode + // (after 0 cycles timeout) + if (CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S && tw_i) begin + illegal_instr = 1'b1; + instruction_o.op = ariane_pkg::ADD; + end + if (CVA6Cfg.RVH && priv_lvl_i == riscv::PRIV_LVL_S && v_i && vtw_i && !tw_i) begin + virtual_illegal_instr = 1'b1; + instruction_o.op = ariane_pkg::ADD; + end + // we don't support U mode interrupts so WFI is illegal in this context + if (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U) begin + if (CVA6Cfg.RVH && v_i) virtual_illegal_instr = 1'b1; + else illegal_instr = 1'b1; + instruction_o.op = ariane_pkg::ADD; + end + end + // SFENCE.VMA + default: begin + if (instr.instr[31:25] == 7'b1001) begin + // check privilege level, SFENCE.VMA can only be executed in M/S mode + // only if S mode is supported + // otherwise decode an illegal instruction + if (CVA6Cfg.RVH && v_i) begin + virtual_illegal_instr = (priv_lvl_i == riscv::PRIV_LVL_S) ? 1'b0 : 1'b1; + end else begin + illegal_instr = (CVA6Cfg.RVS && (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) && instr.itype.rd == '0) ? 1'b0 : 1'b1; + end + instruction_o.op = ariane_pkg::SFENCE_VMA; + // check TVM flag and intercept SFENCE.VMA call if necessary + if (CVA6Cfg.RVS && priv_lvl_i == riscv::PRIV_LVL_S && tvm_i) begin + if (CVA6Cfg.RVH && v_i) virtual_illegal_instr = 1'b1; + else illegal_instr = 1'b1; + end + end else if (CVA6Cfg.RVH) begin + if (instr.instr[31:25] == 7'b10001) begin + // check privilege level, HFENCE.VVMA can only be executed in M/S mode + // otherwise decode an illegal instruction or virtual illegal instruction + if (v_i) begin + virtual_illegal_instr = 1'b1; + end else begin + illegal_instr = (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) ? 1'b0 : 1'b1; + end + instruction_o.op = ariane_pkg::HFENCE_VVMA; + end else if (instr.instr[31:25] == 7'b110001) begin + // check privilege level, HFENCE.GVMA can only be executed in M/S mode + // otherwise decode an illegal instruction or virtual illegal instruction + if (v_i) begin + virtual_illegal_instr = 1'b1; + end else begin + illegal_instr = (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) ? 1'b0 : 1'b1; + end + instruction_o.op = ariane_pkg::HFENCE_GVMA; + // check TVM flag and intercept HFENCE.GVMA call if necessary + if (priv_lvl_i == riscv::PRIV_LVL_S && !v_i && tvm_i) illegal_instr = 1'b1; + end else begin + illegal_instr = 1'b1; + end + end else begin + illegal_instr = 1'b1; + end + end + endcase + end + 3'b100: begin + // Hypervisor load/store instructions + if (CVA6Cfg.RVH) begin + if (instr.instr[25] != 1'b0) begin + instruction_o.fu = STORE; + imm_select = NOIMM; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; + end else begin + instruction_o.fu = LOAD; + imm_select = NOIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + end + + // Hypervisor load/store instructions when V=1 cause virtual instruction + if (v_i) virtual_illegal_instr = 1'b1; + // Hypervisor load/store instructions in U-mode when hstatus.HU=0 cause an illegal instruction trap. + else if (!hu_i && priv_lvl_i == riscv::PRIV_LVL_U) illegal_instr = 1'b1; + unique case (instr.rtype.funct7) + 7'b011_0000: begin + if (instr.rtype.rs2 == 5'b0) begin + instruction_o.op = ariane_pkg::HLV_B; + end + if (instr.rtype.rs2 == 5'b1) begin + instruction_o.op = ariane_pkg::HLV_BU; + end + end + 7'b011_0010: begin + if (instr.rtype.rs2 == 5'b0) begin + instruction_o.op = ariane_pkg::HLV_H; + end + if (instr.rtype.rs2 == 5'b1) begin + instruction_o.op = ariane_pkg::HLV_HU; + end + if (instr.rtype.rs2 == 5'b11) begin + instruction_o.op = ariane_pkg::HLVX_HU; + end + end + 7'b011_0100: begin + if (instr.rtype.rs2 == 5'b0) begin + instruction_o.op = ariane_pkg::HLV_W; + end + if (instr.rtype.rs2 == 5'b1) begin + instruction_o.op = ariane_pkg::HLV_WU; + end + if (instr.rtype.rs2 == 5'b11) begin + instruction_o.op = ariane_pkg::HLVX_WU; + end + end + 7'b011_0001: instruction_o.op = ariane_pkg::HSV_B; + 7'b011_0011: instruction_o.op = ariane_pkg::HSV_H; + 7'b011_0101: instruction_o.op = ariane_pkg::HSV_W; + 7'b011_0110: instruction_o.op = ariane_pkg::HLV_D; + 7'b011_0111: instruction_o.op = ariane_pkg::HSV_D; + default: illegal_instr = 1'b1; + + endcase + tinst = { + instr.rtype.funct7, + instr.rtype.rs2, + 5'b0, + instr.rtype.funct3, + instr.rtype.rd, + instr.rtype.opcode + }; + end else begin + illegal_instr = 1'b1; + end + end + // atomically swaps values in the CSR and integer register + 3'b001: begin // CSRRW + imm_select = IIMM; + instruction_o.op = ariane_pkg::CSR_WRITE; + end + // atomically set values in the CSR and write back to rd + 3'b010: begin // CSRRS + imm_select = IIMM; + // this is just a read + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; + else instruction_o.op = ariane_pkg::CSR_SET; + end + // atomically clear values in the CSR and write back to rd + 3'b011: begin // CSRRC + imm_select = IIMM; + // this is just a read + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; + else instruction_o.op = ariane_pkg::CSR_CLEAR; + end + // use zimm and iimm + 3'b101: begin // CSRRWI + instruction_o.rs1 = instr.itype.rs1; + imm_select = IIMM; + instruction_o.use_zimm = 1'b1; + instruction_o.op = ariane_pkg::CSR_WRITE; + end + 3'b110: begin // CSRRSI + instruction_o.rs1 = instr.itype.rs1; + imm_select = IIMM; + instruction_o.use_zimm = 1'b1; + // this is just a read + if (instr.itype.rs1 == 5'b0) instruction_o.op = ariane_pkg::CSR_READ; + else instruction_o.op = ariane_pkg::CSR_SET; + end + 3'b111: begin // CSRRCI + instruction_o.rs1 = instr.itype.rs1; + imm_select = IIMM; + instruction_o.use_zimm = 1'b1; + // this is just a read + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; + else instruction_o.op = ariane_pkg::CSR_CLEAR; + end + default: illegal_instr = 1'b1; + endcase + end + // Memory ordering instructions + riscv::OpcodeMiscMem: begin + instruction_o.fu = CSR; + instruction_o.rs1 = '0; + instruction_o.rs2 = '0; + instruction_o.rd = '0; + + case (instr.stype.funct3) + // FENCE + // Currently implemented as a whole DCache flush boldly ignoring other things + 3'b000: instruction_o.op = ariane_pkg::FENCE; + // FENCE.I + 3'b001: instruction_o.op = ariane_pkg::FENCE_I; + + default: illegal_instr = 1'b1; + endcase + end + + // -------------------------- + // Reg-Reg Operations + // -------------------------- + riscv::OpcodeOp: begin + // -------------------------------------------- + // Vectorial Floating-Point Reg-Reg Operations + // -------------------------------------------- + if (instr.rvftype.funct2 == 2'b10) begin // Prefix 10 for all Xfvec ops + // only generate decoder if FP extensions are enabled (static) + if (CVA6Cfg.FpPresent && CVA6Cfg.XFVec && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin + automatic logic allow_replication; // control honoring of replication flag + + instruction_o.fu = FPU_VEC; // Same unit, but sets 'vectorial' signal + instruction_o.rs1 = instr.rvftype.rs1; + instruction_o.rs2 = instr.rvftype.rs2; + instruction_o.rd = instr.rvftype.rd; + check_fprm = 1'b1; + allow_replication = 1'b1; + // decode vectorial FP instruction + unique case (instr.rvftype.vecfltop) + 5'b00001: begin + instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 + end + 5'b00010: begin + instruction_o.op = ariane_pkg::FSUB; // vfsub.vfmt - Vectorial FP Subtraction + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 + end + 5'b00011: + instruction_o.op = ariane_pkg::FMUL; // vfmul.vfmt - Vectorial FP Multiplication + 5'b00100: + instruction_o.op = ariane_pkg::FDIV; // vfdiv.vfmt - Vectorial FP Division + 5'b00101: begin + instruction_o.op = ariane_pkg::VFMIN; // vfmin.vfmt - Vectorial FP Minimum + check_fprm = 1'b0; // rounding mode irrelevant + end + 5'b00110: begin + instruction_o.op = ariane_pkg::VFMAX; // vfmax.vfmt - Vectorial FP Maximum + check_fprm = 1'b0; // rounding mode irrelevant + end + 5'b00111: begin + instruction_o.op = ariane_pkg::FSQRT; // vfsqrt.vfmt - Vectorial FP Square Root + allow_replication = 1'b0; // only one operand + if (instr.rvftype.rs2 != 5'b00000) illegal_instr = 1'b1; // rs2 must be 0 + end + 5'b01000: begin + instruction_o.op = ariane_pkg::FMADD; // vfmac.vfmt - Vectorial FP Multiply-Accumulate + imm_select = SIMM; // rd into result field (upper bits don't matter) + end + 5'b01001: begin + instruction_o.op = ariane_pkg::FMSUB; // vfmre.vfmt - Vectorial FP Multiply-Reduce + imm_select = SIMM; // rd into result field (upper bits don't matter) + end + 5'b01100: begin + unique case (instr.rvftype.rs2) inside // operation encoded in rs2, `inside` for matching ? + 5'b00000: begin + instruction_o.rs2 = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + if (instr.rvftype.repl) + instruction_o.op = ariane_pkg::FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move + else instruction_o.op = ariane_pkg::FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move + check_fprm = 1'b0; // no rounding for moves + end + 5'b00001: begin + instruction_o.op = ariane_pkg::FCLASS; // vfclass.vfmt - Vectorial FP Classify + check_fprm = 1'b0; // no rounding for classification + allow_replication = 1'b0; // R must not be set + end + 5'b00010: + instruction_o.op = ariane_pkg::FCVT_F2I; // vfcvt.x.vfmt - Vectorial FP to Int Conversion + 5'b00011: + instruction_o.op = ariane_pkg::FCVT_I2F; // vfcvt.vfmt.x - Vectorial Int to FP Conversion + 5'b001??: begin + instruction_o.op = ariane_pkg::FCVT_F2F; // vfcvt.vfmt.vfmt - Vectorial FP to FP Conversion + instruction_o.rs2 = instr.rvftype.rd; // set rs2 = rd as target vector for conversion + imm_select = IIMM; // rs2 holds part of the intruction + // TODO CHECK R bit for valid fmt combinations + // determine source format + unique case (instr.rvftype.rs2[21:20]) + // Only process instruction if corresponding extension is active (static) + 2'b00: if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + end + default: illegal_instr = 1'b1; + endcase + end + 5'b01101: begin + check_fprm = 1'b0; // no rounding for sign-injection + instruction_o.op = ariane_pkg::VFSGNJ; // vfsgnj.vfmt - Vectorial FP Sign Injection + end + 5'b01110: begin + check_fprm = 1'b0; // no rounding for sign-injection + instruction_o.op = ariane_pkg::VFSGNJN; // vfsgnjn.vfmt - Vectorial FP Negated Sign Injection + end + 5'b01111: begin + check_fprm = 1'b0; // no rounding for sign-injection + instruction_o.op = ariane_pkg::VFSGNJX; // vfsgnjx.vfmt - Vectorial FP XORed Sign Injection + end + 5'b10000: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFEQ; // vfeq.vfmt - Vectorial FP Equality + end + 5'b10001: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFNE; // vfne.vfmt - Vectorial FP Non-Equality + end + 5'b10010: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFLT; // vfle.vfmt - Vectorial FP Less Than + end + 5'b10011: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFGE; // vfge.vfmt - Vectorial FP Greater or Equal + end + 5'b10100: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFLE; // vfle.vfmt - Vectorial FP Less or Equal + end + 5'b10101: begin + check_fprm = 1'b0; // no rounding for comparisons + instruction_o.op = ariane_pkg::VFGT; // vfgt.vfmt - Vectorial FP Greater Than + end + 5'b11000: begin + instruction_o.op = ariane_pkg::VFCPKAB_S; // vfcpka/b.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, lowest 4 entries + imm_select = SIMM; // rd into result field (upper bits don't matter) + if (~CVA6Cfg.RVF) + illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 + // check destination format + unique case (instr.rvftype.vfmt) + // Only process instruction if corresponding extension is active and FLEN suffices (static) + 2'b00: begin + if (~CVA6Cfg.RVFVec) + illegal_instr = 1'b1; // destination vector not supported + if (instr.rvftype.repl) + illegal_instr = 1'b1; // no entries 2/3 in vector of 2 fp32 + end + 2'b01: begin + if (~CVA6Cfg.XF16ALTVec) + illegal_instr = 1'b1; // destination vector not supported + end + 2'b10: begin + if (~CVA6Cfg.XF16Vec) + illegal_instr = 1'b1; // destination vector not supported + end + 2'b11: begin + if (~CVA6Cfg.XF8Vec) + illegal_instr = 1'b1; // destination vector not supported + end + default: illegal_instr = 1'b1; + endcase + end + 5'b11001: begin + instruction_o.op = ariane_pkg::VFCPKCD_S; // vfcpkc/d.vfmt.s - Vectorial FP Cast-and-Pack from 2x FP32, second 4 entries + imm_select = SIMM; // rd into result field (upper bits don't matter) + if (~CVA6Cfg.RVF) + illegal_instr = 1'b1; // if we don't support RVF, we can't cast from FP32 + // check destination format + unique case (instr.rvftype.vfmt) + // Only process instruction if corresponding extension is active and FLEN suffices (static) + 2'b00: illegal_instr = 1'b1; // no entries 4-7 in vector of 2 FP32 + 2'b01: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16ALT + 2'b10: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16 + 2'b11: begin + if (~CVA6Cfg.XF8Vec) + illegal_instr = 1'b1; // destination vector not supported + end + default: illegal_instr = 1'b1; + endcase + end + 5'b11010: begin + instruction_o.op = ariane_pkg::VFCPKAB_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, lowest 4 entries + imm_select = SIMM; // rd into result field (upper bits don't matter) + if (~CVA6Cfg.RVD) + illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 + // check destination format + unique case (instr.rvftype.vfmt) + // Only process instruction if corresponding extension is active and FLEN suffices (static) + 2'b00: begin + if (~CVA6Cfg.RVFVec) + illegal_instr = 1'b1; // destination vector not supported + if (instr.rvftype.repl) + illegal_instr = 1'b1; // no entries 2/3 in vector of 2 fp32 + end + 2'b01: begin + if (~CVA6Cfg.XF16ALTVec) + illegal_instr = 1'b1; // destination vector not supported + end + 2'b10: begin + if (~CVA6Cfg.XF16Vec) + illegal_instr = 1'b1; // destination vector not supported + end + 2'b11: begin + if (~CVA6Cfg.XF8Vec) + illegal_instr = 1'b1; // destination vector not supported + end + default: illegal_instr = 1'b1; + endcase + end + 5'b11011: begin + instruction_o.op = ariane_pkg::VFCPKCD_D; // vfcpka/b.vfmt.d - Vectorial FP Cast-and-Pack from 2x FP64, second 4 entries + imm_select = SIMM; // rd into result field (upper bits don't matter) + if (~CVA6Cfg.RVD) + illegal_instr = 1'b1; // if we don't support RVD, we can't cast from FP64 + // check destination format + unique case (instr.rvftype.vfmt) + // Only process instruction if corresponding extension is active and FLEN suffices (static) + 2'b00: illegal_instr = 1'b1; // no entries 4-7 in vector of 2 FP32 + 2'b01: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16ALT + 2'b10: illegal_instr = 1'b1; // no entries 4-7 in vector of 4 FP16 + 2'b11: begin + if (~CVA6Cfg.XF8Vec) + illegal_instr = 1'b1; // destination vector not supported + end + default: illegal_instr = 1'b1; + endcase + end + default: illegal_instr = 1'b1; + endcase + + // check format + unique case (instr.rvftype.vfmt) + // Only process instruction if corresponding extension is active (static) + 2'b00: if (~CVA6Cfg.RVFVec) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.XF16ALTVec) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16Vec) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8Vec) illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + + // check disallowed replication + if (~allow_replication & instr.rvftype.repl) illegal_instr = 1'b1; + + // check rounding mode + if (check_fprm) begin + unique case (frm_i) inside // actual rounding mode from frm csr + [3'b000 : 3'b100]: ; //legal rounding modes + default: illegal_instr = 1'b1; + endcase + end + + end else begin // No vectorial FP enabled (static) + illegal_instr = 1'b1; + end + + // --------------------------- + // Integer Reg-Reg Operations + // --------------------------- + end else begin + if (CVA6Cfg.RVB) begin + instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001 || ((instr.rtype.funct7 == 7'b000_0101) && !(instr.rtype.funct3[14]))) ? MULT : ALU; + end else begin + instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU; + end + instruction_o.rs1 = instr.rtype.rs1; + instruction_o.rs2 = instr.rtype.rs2; + instruction_o.rd = instr.rtype.rd; + + unique case ({ + instr.rtype.funct7, instr.rtype.funct3 + }) + {7'b000_0000, 3'b000} : instruction_o.op = ariane_pkg::ADD; // Add + {7'b010_0000, 3'b000} : instruction_o.op = ariane_pkg::SUB; // Sub + {7'b000_0000, 3'b010} : instruction_o.op = ariane_pkg::SLTS; // Set Lower Than + { + 7'b000_0000, 3'b011 + } : + instruction_o.op = ariane_pkg::SLTU; // Set Lower Than Unsigned + {7'b000_0000, 3'b100} : instruction_o.op = ariane_pkg::XORL; // Xor + {7'b000_0000, 3'b110} : instruction_o.op = ariane_pkg::ORL; // Or + {7'b000_0000, 3'b111} : instruction_o.op = ariane_pkg::ANDL; // And + {7'b000_0000, 3'b001} : instruction_o.op = ariane_pkg::SLL; // Shift Left Logical + {7'b000_0000, 3'b101} : instruction_o.op = ariane_pkg::SRL; // Shift Right Logical + {7'b010_0000, 3'b101} : instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetic + // Multiplications + {7'b000_0001, 3'b000} : instruction_o.op = ariane_pkg::MUL; + {7'b000_0001, 3'b001} : instruction_o.op = ariane_pkg::MULH; + {7'b000_0001, 3'b010} : instruction_o.op = ariane_pkg::MULHSU; + {7'b000_0001, 3'b011} : instruction_o.op = ariane_pkg::MULHU; + {7'b000_0001, 3'b100} : instruction_o.op = ariane_pkg::DIV; + {7'b000_0001, 3'b101} : instruction_o.op = ariane_pkg::DIVU; + {7'b000_0001, 3'b110} : instruction_o.op = ariane_pkg::REM; + {7'b000_0001, 3'b111} : instruction_o.op = ariane_pkg::REMU; + default: begin + illegal_instr_non_bm = 1'b1; + end + endcase + if (CVA6Cfg.RVB) begin + unique case ({ + instr.rtype.funct7, instr.rtype.funct3 + }) + //Logical with Negate + {7'b010_0000, 3'b111} : instruction_o.op = ariane_pkg::ANDN; // Andn + {7'b010_0000, 3'b110} : instruction_o.op = ariane_pkg::ORN; // Orn + {7'b010_0000, 3'b100} : instruction_o.op = ariane_pkg::XNOR; // Xnor + //Shift and Add (Bitmanip) + {7'b001_0000, 3'b010} : instruction_o.op = ariane_pkg::SH1ADD; // Sh1add + {7'b001_0000, 3'b100} : instruction_o.op = ariane_pkg::SH2ADD; // Sh2add + {7'b001_0000, 3'b110} : instruction_o.op = ariane_pkg::SH3ADD; // Sh3add + // Integer maximum/minimum + {7'b000_0101, 3'b110} : instruction_o.op = ariane_pkg::MAX; // max + {7'b000_0101, 3'b111} : instruction_o.op = ariane_pkg::MAXU; // maxu + {7'b000_0101, 3'b100} : instruction_o.op = ariane_pkg::MIN; // min + {7'b000_0101, 3'b101} : instruction_o.op = ariane_pkg::MINU; // minu + // Single bit instructions + {7'b010_0100, 3'b001} : instruction_o.op = ariane_pkg::BCLR; // bclr + {7'b010_0100, 3'b101} : instruction_o.op = ariane_pkg::BEXT; // bext + {7'b011_0100, 3'b001} : instruction_o.op = ariane_pkg::BINV; // binv + {7'b001_0100, 3'b001} : instruction_o.op = ariane_pkg::BSET; // bset + // Carry-Less-Multiplication (clmul, clmulh, clmulr) + {7'b000_0101, 3'b001} : instruction_o.op = ariane_pkg::CLMUL; // clmul + {7'b000_0101, 3'b011} : instruction_o.op = ariane_pkg::CLMULH; // clmulh + {7'b000_0101, 3'b010} : instruction_o.op = ariane_pkg::CLMULR; // clmulr + // Bitwise Shifting + {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL; // rol + {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR; // ror + { + 7'b000_0100, 3'b111 + } : begin + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; //packh + else illegal_instr_bm = 1'b1; + end + // Zero Extend Op RV32 encoding + { + 7'b000_0100, 3'b100 + } : begin + if (!CVA6Cfg.IS_XLEN64 && instr.instr[24:20] == 5'b00000) + instruction_o.op = ariane_pkg::ZEXTH; // Zero Extend Op RV32 encoding + else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; // pack + else illegal_instr_bm = 1'b1; + end + default: begin + illegal_instr_bm = 1'b1; + end + endcase + end + if (CVA6Cfg.RVZiCond) begin + unique case ({ + instr.rtype.funct7, instr.rtype.funct3 + }) + //Conditional move + {7'b000_0111, 3'b101} : instruction_o.op = ariane_pkg::CZERO_EQZ; // czero.eqz + {7'b000_0111, 3'b111} : instruction_o.op = ariane_pkg::CZERO_NEZ; // czero.nez + default: begin + illegal_instr_zic = 1'b1; + end + endcase + end + //VCS coverage on + unique case ({ + CVA6Cfg.RVB, CVA6Cfg.RVZiCond + }) + 2'b00: illegal_instr = illegal_instr_non_bm; + 2'b01: illegal_instr = illegal_instr_non_bm & illegal_instr_zic; + 2'b10: illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + 2'b11: illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic; + default: ; // TODO: Check that default case is not synthesized. + endcase + end + end + + // -------------------------- + // 32bit Reg-Reg Operations + // -------------------------- + riscv::OpcodeOp32: begin + instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU; + instruction_o.rs1 = instr.rtype.rs1; + instruction_o.rs2 = instr.rtype.rs2; + instruction_o.rd = instr.rtype.rd; + if (CVA6Cfg.IS_XLEN64) begin + unique case ({ + instr.rtype.funct7, instr.rtype.funct3 + }) + {7'b000_0000, 3'b000} : instruction_o.op = ariane_pkg::ADDW; // addw + {7'b010_0000, 3'b000} : instruction_o.op = ariane_pkg::SUBW; // subw + {7'b000_0000, 3'b001} : instruction_o.op = ariane_pkg::SLLW; // sllw + {7'b000_0000, 3'b101} : instruction_o.op = ariane_pkg::SRLW; // srlw + {7'b010_0000, 3'b101} : instruction_o.op = ariane_pkg::SRAW; // sraw + // Multiplications + {7'b000_0001, 3'b000} : instruction_o.op = ariane_pkg::MULW; + {7'b000_0001, 3'b100} : instruction_o.op = ariane_pkg::DIVW; + {7'b000_0001, 3'b101} : instruction_o.op = ariane_pkg::DIVUW; + {7'b000_0001, 3'b110} : instruction_o.op = ariane_pkg::REMW; + {7'b000_0001, 3'b111} : instruction_o.op = ariane_pkg::REMUW; + default: illegal_instr_non_bm = 1'b1; + endcase + if (CVA6Cfg.RVB) begin + unique case ({ + instr.rtype.funct7, instr.rtype.funct3 + }) + // Shift with Add (Unsigned Word) + {7'b001_0000, 3'b010} : instruction_o.op = ariane_pkg::SH1ADDUW; // sh1add.uw + {7'b001_0000, 3'b100} : instruction_o.op = ariane_pkg::SH2ADDUW; // sh2add.uw + {7'b001_0000, 3'b110} : instruction_o.op = ariane_pkg::SH3ADDUW; // sh3add.uw + // Unsigned word Op's + {7'b000_0100, 3'b000} : instruction_o.op = ariane_pkg::ADDUW; // add.uw + // Bitwise Shifting + {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW; // rolw + {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW; // rorw + { + 7'b000_0100, 3'b100 + } : begin + if (instr.instr[24:20] == 5'b00000) + instruction_o.op = ariane_pkg::ZEXTH; // Zero Extend Op RV64 encoding + else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; // packw + else illegal_instr_bm = 1'b1; + end + default: illegal_instr_bm = 1'b1; + endcase + illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + end else begin + illegal_instr = illegal_instr_non_bm; + end + end else illegal_instr = 1'b1; + end + // -------------------------------- + // Reg-Immediate Operations + // -------------------------------- + riscv::OpcodeOpImm: begin + instruction_o.fu = ALU; + imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + unique case (instr.itype.funct3) + 3'b000: instruction_o.op = ariane_pkg::ADD; // Add Immediate + 3'b010: instruction_o.op = ariane_pkg::SLTS; // Set to one if Lower Than Immediate + 3'b011: + instruction_o.op = ariane_pkg::SLTU; // Set to one if Lower Than Immediate Unsigned + 3'b100: instruction_o.op = ariane_pkg::XORL; // Exclusive Or with Immediate + 3'b110: instruction_o.op = ariane_pkg::ORL; // Or with Immediate + 3'b111: instruction_o.op = ariane_pkg::ANDL; // And with Immediate + + 3'b001: begin + instruction_o.op = ariane_pkg::SLL; // Shift Left Logical by Immediate + if (instr.instr[31:26] != 6'b0) illegal_instr_non_bm = 1'b1; + if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1; + end + + 3'b101: begin + if (instr.instr[31:26] == 6'b0) + instruction_o.op = ariane_pkg::SRL; // Shift Right Logical by Immediate + else if (instr.instr[31:26] == 6'b010_000) + instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetically by Immediate + else illegal_instr_non_bm = 1'b1; + if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1; + end + endcase + if (CVA6Cfg.RVB) begin + unique case (instr.itype.funct3) + 3'b001: begin + if (instr.instr[31:25] == 7'b0110000) begin + if (instr.instr[24:20] == 5'b00100) instruction_o.op = ariane_pkg::SEXTB; + else if (instr.instr[24:20] == 5'b00101) instruction_o.op = ariane_pkg::SEXTH; + else if (instr.instr[24:20] == 5'b00010) instruction_o.op = ariane_pkg::CPOP; + else if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::CLZ; + else if (instr.instr[24:20] == 5'b00001) instruction_o.op = ariane_pkg::CTZ; + else illegal_instr_bm = 1'b1; + end else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010010) + instruction_o.op = ariane_pkg::BCLRI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0100100) + instruction_o.op = ariane_pkg::BCLRI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011010) + instruction_o.op = ariane_pkg::BINVI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0110100) + instruction_o.op = ariane_pkg::BINVI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b001010) + instruction_o.op = ariane_pkg::BSETI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0010100) + instruction_o.op = ariane_pkg::BSETI; + else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) + instruction_o.op = ariane_pkg::ZIP; + else illegal_instr_bm = 1'b1; + end + 3'b101: begin + if (instr.instr[31:20] == 12'b001010000111) instruction_o.op = ariane_pkg::ORCB; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:20] == 12'b011010111000) + instruction_o.op = ariane_pkg::REV8; + else if (instr.instr[31:20] == 12'b011010011000) + instruction_o.op = ariane_pkg::REV8; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010_010) + instruction_o.op = ariane_pkg::BEXTI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b010_0100) + instruction_o.op = ariane_pkg::BEXTI; + else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011_000) + instruction_o.op = ariane_pkg::RORI; + else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b011_0000) + instruction_o.op = ariane_pkg::RORI; + else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b011010000111) + instruction_o.op = ariane_pkg::BREV8; + else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) + instruction_o.op = ariane_pkg::UNZIP; + else illegal_instr_bm = 1'b1; + end + default: illegal_instr_bm = 1'b1; + endcase + illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + end else begin + illegal_instr = illegal_instr_non_bm; + end + end + + // -------------------------------- + // 32 bit Reg-Immediate Operations + // -------------------------------- + riscv::OpcodeOpImm32: begin + instruction_o.fu = ALU; + imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + if (CVA6Cfg.IS_XLEN64) begin + unique case (instr.itype.funct3) + 3'b000: instruction_o.op = ariane_pkg::ADDW; // Add Immediate + 3'b001: begin + instruction_o.op = ariane_pkg::SLLW; // Shift Left Logical by Immediate + if (instr.instr[31:25] != 7'b0) illegal_instr_non_bm = 1'b1; + end + 3'b101: begin + if (instr.instr[31:25] == 7'b0) + instruction_o.op = ariane_pkg::SRLW; // Shift Right Logical by Immediate + else if (instr.instr[31:25] == 7'b010_0000) + instruction_o.op = ariane_pkg::SRAW; // Shift Right Arithmetically by Immediate + else illegal_instr_non_bm = 1'b1; + end + default: illegal_instr_non_bm = 1'b1; + endcase + if (CVA6Cfg.RVB) begin + unique case (instr.itype.funct3) + 3'b001: begin + if (instr.instr[31:25] == 7'b0110000) begin + if (instr.instr[21:20] == 2'b10) instruction_o.op = ariane_pkg::CPOPW; + else if (instr.instr[21:20] == 2'b00) instruction_o.op = ariane_pkg::CLZW; + else if (instr.instr[21:20] == 2'b01) instruction_o.op = ariane_pkg::CTZW; + else illegal_instr_bm = 1'b1; + end else if (instr.instr[31:26] == 6'b000010) begin + instruction_o.op = ariane_pkg::SLLIUW; // Shift Left Logic by Immediate (Unsigned Word) + end else illegal_instr_bm = 1'b1; + end + 3'b101: begin + if (instr.instr[31:25] == 7'b011_0000) instruction_o.op = ariane_pkg::RORIW; + else illegal_instr_bm = 1'b1; + end + default: illegal_instr_bm = 1'b1; + endcase + illegal_instr = illegal_instr_non_bm & illegal_instr_bm; + end else begin + illegal_instr = illegal_instr_non_bm; + end + + end else illegal_instr = 1'b1; + end + // -------------------------------- + // LSU + // -------------------------------- + riscv::OpcodeStore: begin + instruction_o.fu = STORE; + imm_select = SIMM; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; + // determine store size + unique case (instr.stype.funct3) + 3'b000: instruction_o.op = ariane_pkg::SB; + 3'b001: instruction_o.op = ariane_pkg::SH; + 3'b010: instruction_o.op = ariane_pkg::SW; + 3'b011: + if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::SD; + else illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + if (CVA6Cfg.RVH) begin + tinst = {7'b0, instr.stype.rs2, 5'b0, instr.stype.funct3, 5'b0, instr.stype.opcode}; + tinst[1] = is_compressed_i ? 1'b0 : 'b1; + end + end + + riscv::OpcodeLoad: begin + instruction_o.fu = LOAD; + imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + // determine load size and signed type + unique case (instr.itype.funct3) + 3'b000: instruction_o.op = ariane_pkg::LB; + 3'b001: instruction_o.op = ariane_pkg::LH; + 3'b010: instruction_o.op = ariane_pkg::LW; + 3'b100: instruction_o.op = ariane_pkg::LBU; + 3'b101: instruction_o.op = ariane_pkg::LHU; + 3'b110: + if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LWU; + else illegal_instr = 1'b1; + 3'b011: + if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LD; + else illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + if (CVA6Cfg.RVH) begin + tinst = {17'b0, instr.itype.funct3, instr.itype.rd, instr.itype.opcode}; + tinst[1] = is_compressed_i ? 1'b0 : 'b1; + end + end + + // -------------------------------- + // Floating-Point Load/store + // -------------------------------- + riscv::OpcodeStoreFp: begin + if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) + instruction_o.fu = STORE; + imm_select = SIMM; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; + // determine store size + unique case (instr.stype.funct3) + // Only process instruction if corresponding extension is active (static) + 3'b000: + if (CVA6Cfg.XF8) instruction_o.op = ariane_pkg::FSB; + else illegal_instr = 1'b1; + 3'b001: + if (CVA6Cfg.XF16 | CVA6Cfg.XF16ALT) instruction_o.op = ariane_pkg::FSH; + else illegal_instr = 1'b1; + 3'b010: + if (CVA6Cfg.RVF) instruction_o.op = ariane_pkg::FSW; + else illegal_instr = 1'b1; + 3'b011: + if (CVA6Cfg.RVD) instruction_o.op = ariane_pkg::FSD; + else illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + if (CVA6Cfg.RVH) begin + tinst = {7'b0, instr.stype.rs2, 5'b0, instr.stype.funct3, 5'b0, instr.stype.opcode}; + tinst[1] = is_compressed_i ? 1'b0 : 'b1; + end + end else illegal_instr = 1'b1; + end + + riscv::OpcodeLoadFp: begin + if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) + instruction_o.fu = LOAD; + imm_select = IIMM; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; + // determine load size + unique case (instr.itype.funct3) + // Only process instruction if corresponding extension is active (static) + 3'b000: + if (CVA6Cfg.XF8) instruction_o.op = ariane_pkg::FLB; + else illegal_instr = 1'b1; + 3'b001: + if (CVA6Cfg.XF16 | CVA6Cfg.XF16ALT) instruction_o.op = ariane_pkg::FLH; + else illegal_instr = 1'b1; + 3'b010: + if (CVA6Cfg.RVF) instruction_o.op = ariane_pkg::FLW; + else illegal_instr = 1'b1; + 3'b011: + if (CVA6Cfg.RVD) instruction_o.op = ariane_pkg::FLD; + else illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + if (CVA6Cfg.RVH) begin + tinst = {17'b0, instr.itype.funct3, instr.itype.rd, instr.itype.opcode}; + tinst[1] = is_compressed_i ? 1'b0 : 'b1; + end + end else illegal_instr = 1'b1; + end + + // ---------------------------------- + // Floating-Point Reg-Reg Operations + // ---------------------------------- + riscv::OpcodeMadd, riscv::OpcodeMsub, riscv::OpcodeNmsub, riscv::OpcodeNmadd: begin + if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) + instruction_o.fu = FPU; + instruction_o.rs1 = instr.r4type.rs1; + instruction_o.rs2 = instr.r4type.rs2; + instruction_o.rd = instr.r4type.rd; + imm_select = RS3; // rs3 into result field + check_fprm = 1'b1; + // select the correct fused operation + unique case (instr.r4type.opcode) + default: instruction_o.op = ariane_pkg::FMADD; // fmadd.fmt - FP Fused multiply-add + riscv::OpcodeMsub: + instruction_o.op = ariane_pkg::FMSUB; // fmsub.fmt - FP Fused multiply-subtract + riscv::OpcodeNmsub: + instruction_o.op = ariane_pkg::FNMSUB; // fnmsub.fmt - FP Negated fused multiply-subtract + riscv::OpcodeNmadd: + instruction_o.op = ariane_pkg::FNMADD; // fnmadd.fmt - FP Negated fused multiply-add + endcase + + // determine fp format + unique case (instr.r4type.funct2) + // Only process instruction if corresponding extension is active (static) + 2'b00: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16 & ~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + + // check rounding mode + if (check_fprm) begin + unique case (instr.rftype.rm) inside + [3'b000 : 3'b100]: ; //legal rounding modes + 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; + unique case (frm_i) inside // actual rounding mode from frm csr + [3'b000 : 3'b100]: ; //legal rounding modes + default: illegal_instr = 1'b1; + endcase + end + 3'b111: begin + // rounding mode from frm csr + unique case (frm_i) inside + [3'b000 : 3'b100]: ; //legal rounding modes + default: illegal_instr = 1'b1; + endcase + end + default: illegal_instr = 1'b1; + endcase + end + end else begin + illegal_instr = 1'b1; + end + end + + riscv::OpcodeOpFp: begin + if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) + instruction_o.fu = FPU; + instruction_o.rs1 = instr.rftype.rs1; + instruction_o.rs2 = instr.rftype.rs2; + instruction_o.rd = instr.rftype.rd; + check_fprm = 1'b1; + // decode FP instruction + unique case (instr.rftype.funct5) + 5'b00000: begin + instruction_o.op = ariane_pkg::FADD; // fadd.fmt - FP Addition + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 + end + 5'b00001: begin + instruction_o.op = ariane_pkg::FSUB; // fsub.fmt - FP Subtraction + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 + end + 5'b00010: instruction_o.op = ariane_pkg::FMUL; // fmul.fmt - FP Multiplication + 5'b00011: instruction_o.op = ariane_pkg::FDIV; // fdiv.fmt - FP Division + 5'b01011: begin + instruction_o.op = ariane_pkg::FSQRT; // fsqrt.fmt - FP Square Root + // rs2 must be zero + if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; + end + 5'b00100: begin + instruction_o.op = ariane_pkg::FSGNJ; // fsgn{j[n]/jx}.fmt - FP Sign Injection + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr.rftype.rm inside {[3'b000 : 3'b010], [3'b100 : 3'b110]})) + illegal_instr = 1'b1; + end else begin + if (!(instr.rftype.rm inside {[3'b000 : 3'b010]})) illegal_instr = 1'b1; + end + end + 5'b00101: begin + instruction_o.op = ariane_pkg::FMIN_MAX; // fmin/fmax.fmt - FP Minimum / Maximum + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr.rftype.rm inside {[3'b000 : 3'b001], [3'b100 : 3'b101]})) + illegal_instr = 1'b1; + end else begin + if (!(instr.rftype.rm inside {[3'b000 : 3'b001]})) illegal_instr = 1'b1; + end + end + 5'b01000: begin + instruction_o.op = ariane_pkg::FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion + instruction_o.rs2 = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2) + imm_select = IIMM; // rs2 holds part of the intruction + if (|instr.rftype.rs2[24:23]) + illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0 + // check source format + unique case (instr.rftype.rs2[22:20]) + // Only process instruction if corresponding extension is active (static) + 3'b000: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 3'b001: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 3'b010: if (~CVA6Cfg.XF16) illegal_instr = 1'b1; + 3'b110: if (~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 3'b011: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + end + 5'b10100: begin + instruction_o.op = ariane_pkg::FCMP; // feq/flt/fle.fmt - FP Comparisons + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (CVA6Cfg.XF16ALT) begin // FP16ALT instructions encoded in rm separately (static) + if (!(instr.rftype.rm inside {[3'b000 : 3'b010], [3'b100 : 3'b110]})) + illegal_instr = 1'b1; + end else begin + if (!(instr.rftype.rm inside {[3'b000 : 3'b010]})) illegal_instr = 1'b1; + end + end + 5'b11000: begin + instruction_o.op = ariane_pkg::FCVT_F2I; // fcvt.ifmt.fmt - FP to Int Conversion + imm_select = IIMM; // rs2 holds part of the instruction + if (|instr.rftype.rs2[24:22]) + illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 + end + 5'b11010: begin + instruction_o.op = ariane_pkg::FCVT_I2F; // fcvt.fmt.ifmt - Int to FP Conversion + imm_select = IIMM; // rs2 holds part of the instruction + if (|instr.rftype.rs2[24:22]) + illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 + end + 5'b11100: begin + instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100)) // FP16ALT has separate encoding + instruction_o.op = ariane_pkg::FMV_F2X; // fmv.ifmt.fmt - FPR to GPR Move + else if (instr.rftype.rm == 3'b001 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b101)) // FP16ALT has separate encoding + instruction_o.op = ariane_pkg::FCLASS; // fclass.fmt - FP Classify + else illegal_instr = 1'b1; + // rs2 must be zero + if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; + end + 5'b11110: begin + instruction_o.op = ariane_pkg::FMV_X2F; // fmv.fmt.ifmt - GPR to FPR Move + instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + check_fprm = 1'b0; // instruction encoded in rm, do the check here + if (!(instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100))) + illegal_instr = 1'b1; + // rs2 must be zero + if (instr.rftype.rs2 != 5'b00000) illegal_instr = 1'b1; + end + default: illegal_instr = 1'b1; + endcase + + // check format + unique case (instr.rftype.fmt) + // Only process instruction if corresponding extension is active (static) + 2'b00: if (~CVA6Cfg.RVF) illegal_instr = 1'b1; + 2'b01: if (~CVA6Cfg.RVD) illegal_instr = 1'b1; + 2'b10: if (~CVA6Cfg.XF16 & ~CVA6Cfg.XF16ALT) illegal_instr = 1'b1; + 2'b11: if (~CVA6Cfg.XF8) illegal_instr = 1'b1; + default: illegal_instr = 1'b1; + endcase + + // check rounding mode + if (check_fprm) begin + unique case (instr.rftype.rm) inside + [3'b000 : 3'b100]: ; //legal rounding modes + 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; + unique case (frm_i) inside // actual rounding mode from frm csr + [3'b000 : 3'b100]: ; //legal rounding modes + default: illegal_instr = 1'b1; + endcase + end + 3'b111: begin + // rounding mode from frm csr + unique case (frm_i) inside + [3'b000 : 3'b100]: ; //legal rounding modes + default: illegal_instr = 1'b1; + endcase + end + default: illegal_instr = 1'b1; + endcase + end + end else begin + illegal_instr = 1'b1; + end + end + + // ---------------------------------- + // Atomic Operations + // ---------------------------------- + riscv::OpcodeAmo: begin + // we are going to use the load unit for AMOs + instruction_o.fu = STORE; + instruction_o.rs1 = instr.atype.rs1; + instruction_o.rs2 = instr.atype.rs2; + instruction_o.rd = instr.atype.rd; + // TODO(zarubaf): Ordering + // words + if (CVA6Cfg.RVA && instr.stype.funct3 == 3'h2) begin + unique case (instr.instr[31:27]) + 5'h0: instruction_o.op = ariane_pkg::AMO_ADDW; + 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPW; + 5'h2: begin + instruction_o.op = ariane_pkg::AMO_LRW; + if (instr.atype.rs2 != 0) illegal_instr = 1'b1; + end + 5'h3: instruction_o.op = ariane_pkg::AMO_SCW; + 5'h4: instruction_o.op = ariane_pkg::AMO_XORW; + 5'h8: instruction_o.op = ariane_pkg::AMO_ORW; + 5'hC: instruction_o.op = ariane_pkg::AMO_ANDW; + 5'h10: instruction_o.op = ariane_pkg::AMO_MINW; + 5'h14: instruction_o.op = ariane_pkg::AMO_MAXW; + 5'h18: instruction_o.op = ariane_pkg::AMO_MINWU; + 5'h1C: instruction_o.op = ariane_pkg::AMO_MAXWU; + default: illegal_instr = 1'b1; + endcase + // double words + end else if (CVA6Cfg.IS_XLEN64 && CVA6Cfg.RVA && instr.stype.funct3 == 3'h3) begin + unique case (instr.instr[31:27]) + 5'h0: instruction_o.op = ariane_pkg::AMO_ADDD; + 5'h1: instruction_o.op = ariane_pkg::AMO_SWAPD; + 5'h2: begin + instruction_o.op = ariane_pkg::AMO_LRD; + if (instr.atype.rs2 != 0) illegal_instr = 1'b1; + end + 5'h3: instruction_o.op = ariane_pkg::AMO_SCD; + 5'h4: instruction_o.op = ariane_pkg::AMO_XORD; + 5'h8: instruction_o.op = ariane_pkg::AMO_ORD; + 5'hC: instruction_o.op = ariane_pkg::AMO_ANDD; + 5'h10: instruction_o.op = ariane_pkg::AMO_MIND; + 5'h14: instruction_o.op = ariane_pkg::AMO_MAXD; + 5'h18: instruction_o.op = ariane_pkg::AMO_MINDU; + 5'h1C: instruction_o.op = ariane_pkg::AMO_MAXDU; + default: illegal_instr = 1'b1; + endcase + end else begin + illegal_instr = 1'b1; + end + if (CVA6Cfg.RVH) begin + tinst = { + instr.atype.funct5, + instr.atype.aq, + instr.atype.rl, + instr.atype.rs2, + 5'b0, + instr.atype.funct3, + instr.atype.rd, + instr.atype.opcode + }; + end + end + + // -------------------------------- + // Control Flow Instructions + // -------------------------------- + riscv::OpcodeBranch: begin + imm_select = SBIMM; + instruction_o.fu = CTRL_FLOW; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; + + is_control_flow_instr_o = 1'b1; + + case (instr.stype.funct3) + 3'b000: instruction_o.op = ariane_pkg::EQ; + 3'b001: instruction_o.op = ariane_pkg::NE; + 3'b100: instruction_o.op = ariane_pkg::LTS; + 3'b101: instruction_o.op = ariane_pkg::GES; + 3'b110: instruction_o.op = ariane_pkg::LTU; + 3'b111: instruction_o.op = ariane_pkg::GEU; + default: begin + is_control_flow_instr_o = 1'b0; + illegal_instr = 1'b1; + end + endcase + end + // Jump and link register + riscv::OpcodeJalr: begin + instruction_o.fu = CTRL_FLOW; + instruction_o.op = ariane_pkg::JALR; + instruction_o.rs1 = instr.itype.rs1; + imm_select = IIMM; + instruction_o.rd = instr.itype.rd; + is_control_flow_instr_o = 1'b1; + // invalid jump and link register -> reserved for vector encoding + if (instr.itype.funct3 != 3'b0) illegal_instr = 1'b1; + end + // Jump and link + riscv::OpcodeJal: begin + instruction_o.fu = CTRL_FLOW; + imm_select = JIMM; + instruction_o.rd = instr.utype.rd; + is_control_flow_instr_o = 1'b1; + end + + riscv::OpcodeAuipc: begin + instruction_o.fu = ALU; + imm_select = UIMM; + instruction_o.use_pc = 1'b1; + instruction_o.rd = instr.utype.rd; + end + + riscv::OpcodeLui: begin + imm_select = UIMM; + instruction_o.fu = ALU; + instruction_o.rd = instr.utype.rd; + end + + default: illegal_instr = 1'b1; + endcase + end + if (CVA6Cfg.CvxifEn) begin + if (~ex_i.valid && (is_illegal_i || illegal_instr)) begin + instruction_o.fu = CVXIF; + instruction_o.rs1 = instr.r4type.rs1; + instruction_o.rs2 = instr.r4type.rs2; + instruction_o.rd = instr.r4type.rd; + instruction_o.op = ariane_pkg::OFFLOAD; + imm_select = instr.rtype.opcode == riscv::OpcodeMadd || + instr.rtype.opcode == riscv::OpcodeMsub || + instr.rtype.opcode == riscv::OpcodeNmadd || + instr.rtype.opcode == riscv::OpcodeNmsub ? RS3 : MUX_RD_RS3; + end + end + + // Accelerator instructions. + // These can overwrite the previous decoding entirely. + if (CVA6Cfg.EnableAccelerator) begin // only generate decoder if accelerators are enabled (static) + if (is_accel) begin + instruction_o.fu = acc_instruction.fu; + instruction_o.vfp = acc_instruction.vfp; + instruction_o.rs1 = acc_instruction.rs1; + instruction_o.rs2 = acc_instruction.rs2; + instruction_o.rd = acc_instruction.rd; + instruction_o.op = acc_instruction.op; + illegal_instr = acc_illegal_instr; + is_control_flow_instr_o = acc_is_control_flow_instr; + end + end + end + + // -------------------------------- + // Sign extend immediate + // -------------------------------- + always_comb begin : sign_extend + imm_i_type = {{CVA6Cfg.XLEN - 12{instruction_i[31]}}, instruction_i[31:20]}; + imm_s_type = { + {CVA6Cfg.XLEN - 12{instruction_i[31]}}, instruction_i[31:25], instruction_i[11:7] + }; + imm_sb_type = { + {CVA6Cfg.XLEN - 13{instruction_i[31]}}, + instruction_i[31], + instruction_i[7], + instruction_i[30:25], + instruction_i[11:8], + 1'b0 + }; + imm_u_type = { + {CVA6Cfg.XLEN - 32{instruction_i[31]}}, instruction_i[31:12], 12'b0 + }; // JAL, AUIPC, sign extended to 64 bit + // if zcmt then xlen jump address assign to immidiate + if (CVA6Cfg.RVZCMT && is_zcmt_i) begin + imm_uj_type = {{CVA6Cfg.XLEN - 32{jump_address_i[31]}}, jump_address_i[31:0]}; + end else begin + imm_uj_type = { + {CVA6Cfg.XLEN - 20{instruction_i[31]}}, + instruction_i[19:12], + instruction_i[20], + instruction_i[30:21], + 1'b0 + }; + end + + // NOIMM, IIMM, SIMM, SBIMM, UIMM, JIMM, RS3 + // select immediate + case (imm_select) + IIMM: begin + instruction_o.result = imm_i_type; + instruction_o.use_imm = 1'b1; + end + SIMM: begin + instruction_o.result = imm_s_type; + instruction_o.use_imm = 1'b1; + end + SBIMM: begin + instruction_o.result = imm_sb_type; + instruction_o.use_imm = 1'b1; + end + UIMM: begin + instruction_o.result = imm_u_type; + instruction_o.use_imm = 1'b1; + end + JIMM: begin + instruction_o.result = imm_uj_type; + instruction_o.use_imm = 1'b1; + end + RS3: begin + // result holds address of fp operand rs3 + instruction_o.result = {{CVA6Cfg.XLEN - 5{1'b0}}, instr.r4type.rs3}; + instruction_o.use_imm = 1'b0; + end + MUX_RD_RS3: begin + // result holds address of operand rs3 which is in rd field + instruction_o.result = {{CVA6Cfg.XLEN - 5{1'b0}}, instr.rtype.rd}; + instruction_o.use_imm = 1'b0; + end + default: begin + instruction_o.result = {CVA6Cfg.XLEN{1'b0}}; + instruction_o.use_imm = 1'b0; + end + endcase + + if (CVA6Cfg.EnableAccelerator) begin + if (is_accel) begin + instruction_o.result = acc_instruction.result; + instruction_o.use_imm = acc_instruction.use_imm; + end + end + end + + // --------------------- + // Exception handling + // --------------------- + logic [CVA6Cfg.XLEN-1:0] interrupt_cause; + + // this instruction has already executed if the exception is valid + assign instruction_o.valid = instruction_o.ex.valid; + + always_comb begin : exception_handling + interrupt_cause = '0; + instruction_o.ex = ex_i; + orig_instr_o = '0; + // look if we didn't already get an exception in any previous + // stage - we should not overwrite it as we retain order regarding the exception + if (~ex_i.valid) begin + // if we didn't already get an exception save the instruction here as we may need it + // in the commit stage if we got a access exception to one of the CSR registers + if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF) + orig_instr_o = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i}; + if (CVA6Cfg.TvalEn) + instruction_o.ex.tval = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i}; + else instruction_o.ex.tval = '0; + if (CVA6Cfg.RVH) instruction_o.ex.tinst = tinst; + else instruction_o.ex.tinst = '0; + // instructions which will throw an exception are marked as valid + // e.g.: they can be committed anytime and do not need to wait for any functional unit + // check here if we decoded an invalid instruction or if the compressed decoder already decoded + // a invalid instruction + if (illegal_instr || is_illegal_i) begin + if (!CVA6Cfg.CvxifEn) instruction_o.ex.valid = 1'b1; + // we decoded an illegal exception here + instruction_o.ex.cause = riscv::ILLEGAL_INSTR; + end else if (CVA6Cfg.RVH && virtual_illegal_instr) begin + instruction_o.ex.valid = 1'b1; + // we decoded an virtual illegal exception here + instruction_o.ex.cause = riscv::VIRTUAL_INSTRUCTION; + // we got an ecall, set the correct cause depending on the current privilege level + end else if (ecall) begin + // this exception is valid + instruction_o.ex.valid = 1'b1; + // depending on the privilege mode, set the appropriate cause + if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + instruction_o.ex.cause = (CVA6Cfg.RVH && v_i) ? riscv::ENV_CALL_VSMODE : riscv::ENV_CALL_SMODE; + end else if (priv_lvl_i == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin + instruction_o.ex.cause = riscv::ENV_CALL_UMODE; + end else if (priv_lvl_i == riscv::PRIV_LVL_M) begin + instruction_o.ex.cause = riscv::ENV_CALL_MMODE; + end + end else if (ebreak) begin + // this exception is valid + instruction_o.ex.valid = 1'b1; + // set breakpoint cause + instruction_o.ex.cause = riscv::BREAKPOINT; + // set gva bit + if (CVA6Cfg.RVH) instruction_o.ex.gva = v_i; + else instruction_o.ex.gva = 1'b0; + end + // ----------------- + // Interrupt Control + // ----------------- + // we decode an interrupt the same as an exception, hence it will be taken if the instruction did not + // throw any previous exception. + // we have three interrupt sources: external interrupts, software interrupts, timer interrupts (order of precedence) + // for two privilege levels: Supervisor and Machine Mode + // Virtual Supervisor Timer Interrupt + if (CVA6Cfg.RVH) begin + if (irq_ctrl_i.mie[riscv::IRQ_VS_TIMER] && irq_ctrl_i.mip[riscv::IRQ_VS_TIMER]) begin + interrupt_cause = INTERRUPTS.VS_TIMER; + end + // Virtual Supervisor Software Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_VS_SOFT] && irq_ctrl_i.mip[riscv::IRQ_VS_SOFT]) begin + interrupt_cause = INTERRUPTS.VS_SW; + end + // Virtual Supervisor External Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_VS_EXT] && (irq_ctrl_i.mip[riscv::IRQ_VS_EXT])) begin + interrupt_cause = INTERRUPTS.VS_EXT; + end + // Hypervisor Guest External Interrupts + if (irq_ctrl_i.mie[riscv::IRQ_HS_EXT] && irq_ctrl_i.mip[riscv::IRQ_HS_EXT]) begin + interrupt_cause = INTERRUPTS.HS_EXT; + end + end + if (CVA6Cfg.RVS) begin + // Supervisor Timer Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_S_TIMER] && irq_ctrl_i.mip[riscv::IRQ_S_TIMER]) begin + interrupt_cause = INTERRUPTS.S_TIMER; + end + // Supervisor Software Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_S_SOFT] && irq_ctrl_i.mip[riscv::IRQ_S_SOFT]) begin + interrupt_cause = INTERRUPTS.S_SW; + end + // Supervisor External Interrupt + // The logical-OR of the software-writable bit and the signal from the external interrupt controller is + // used to generate external interrupts to the supervisor + if (irq_ctrl_i.mie[riscv::IRQ_S_EXT] && (irq_ctrl_i.mip[riscv::IRQ_S_EXT] | irq_i[ariane_pkg::SupervisorIrq])) begin + interrupt_cause = INTERRUPTS.S_EXT; + end + end + // Machine Timer Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_TIMER] && irq_ctrl_i.mie[riscv::IRQ_M_TIMER]) begin + interrupt_cause = INTERRUPTS.M_TIMER; + end + if (CVA6Cfg.SoftwareInterruptEn) begin + // Machine Mode Software Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_SOFT] && irq_ctrl_i.mie[riscv::IRQ_M_SOFT]) begin + interrupt_cause = INTERRUPTS.M_SW; + end + end + // Machine Mode External Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_EXT] && irq_ctrl_i.mie[riscv::IRQ_M_EXT]) begin + interrupt_cause = INTERRUPTS.M_EXT; + end + + if (interrupt_cause[CVA6Cfg.XLEN-1] && irq_ctrl_i.global_enable) begin + // However, if bit i in mideleg is set, interrupts are considered to be globally enabled if the hart’s current privilege + // mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit + // (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode. + if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin + if (CVA6Cfg.RVH) begin : hyp_int_gen + if (v_i && irq_ctrl_i.hideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin + if ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end + end else if (v_i && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end else if (!v_i && ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end + end else begin + if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end + end + end else begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end + end + end + + // a debug request has precendece over everything else + if (CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = riscv::DEBUG_REQUEST; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/ex_stage.sv b/flow/designs/src/cva6/core/ex_stage.sv new file mode 100644 index 0000000000..84f5369717 --- /dev/null +++ b/flow/designs/src/cva6/core/ex_stage.sv @@ -0,0 +1,725 @@ + +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 19.04.2017 +// Description: Instantiation of all functional units residing in the execute stage + + +module ex_stage + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type fu_data_t = logic, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type lsu_ctrl_t = logic, + parameter type x_result_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Debug mode is enabled - CSR_REGFILE + input logic debug_mode_i, + // rs1 forwarding - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i, + // rs2 forwarding - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i, + // FU data useful to execute instruction - ISSUE_STAGE + input fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_i, + // PC of the current instruction - ISSUE_STAGE + input logic [CVA6Cfg.VLEN-1:0] pc_i, + // Is_zcmt instruction - ISSUE_STAGE + input logic is_zcmt_i, + // Report whether instruction is compressed - ISSUE_STAGE + input logic is_compressed_instr_i, + // Report instruction encoding - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_i, + // Fixed Latency Unit result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] flu_result_o, + // ID of the scoreboard entry at which a=to write back - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_o, + // Fixed Latency Unit exception - ISSUE_STAGE + output exception_t flu_exception_o, + // FLU is ready - ISSUE_STAGE + output logic flu_ready_o, + // FLU result is valid - ISSUE_STAGE + output logic flu_valid_o, + // ALU instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_i, + // Branch unit instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_i, + // Information of branch prediction - ISSUE_STAGE + input branchpredict_sbe_t branch_predict_i, + // The branch engine uses the write back from the ALU - several_modules + output bp_resolve_t resolved_branch_o, + // Signaling that we resolved the branch - ISSUE_STAGE + output logic resolve_branch_o, + // CSR instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_i, + // CSR address to write - COMMIT_STAGE + output logic [11:0] csr_addr_o, + // CSR commit - COMMIT_STAGE + input logic csr_commit_i, + // MULT instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_i, + // LSU is ready - ISSUE_STAGE + output logic lsu_ready_o, + // LSU instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_i, + // Load result is valid - ISSUE_STAGE + output logic load_valid_o, + // Load result valid - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] load_result_o, + // Load instruction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o, + // Exception generated by load instruction - ISSUE_STAGE + output exception_t load_exception_o, + // Store result is valid - ISSUe_STAGE + output logic store_valid_o, + // Store result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] store_result_o, + // Store instruction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_o, + // Exception generated by store instruction - ISSUE_STAGE + output exception_t store_exception_o, + // LSU commit - COMMIT_STAGE + input logic lsu_commit_i, + // Commit queue ready to accept another commit request - COMMIT_STAGE + output logic lsu_commit_ready_o, + // Commit transaction ID - COMMIT_STAGE + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i, + // TO_BE_COMPLETED - ACC_DISPATCHER + input logic stall_st_pending_i, + // TO_BE_COMPLETED - COMMIT_STAGE + output logic no_st_pending_o, + // Atomic result is valid - COMMIT_STAGE + input logic amo_valid_commit_i, + // FU is ready - ISSUE_STAGE + output logic fpu_ready_o, + // FPU instruction is ready - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_i, + // FPU format - ISSUE_STAGE + input logic [1:0] fpu_fmt_i, + // FPU rm - ISSUE_STAGE + input logic [2:0] fpu_rm_i, + // FPU frm - ISSUE_STAGE + input logic [2:0] fpu_frm_i, + // FPU precision control - CSR_REGFILE + input logic [6:0] fpu_prec_i, + // FPU transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_o, + // FPU result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] fpu_result_o, + // FPU valid - ISSUE_STAGE + output logic fpu_valid_o, + // FPU exception - ISSUE_STAGE + output exception_t fpu_exception_o, + // ALU2 instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_i, + // CVXIF instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] x_valid_i, + // CVXIF is ready - ISSUE_STAGE + output logic x_ready_o, + // CVXIF undecoded instruction + input logic [31:0] x_off_instr_i, + // CVXIF transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_o, + // CVXIF exception - ISSUE_STAGE + output exception_t x_exception_o, + // CVXIF result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] x_result_o, + // CVXIF result valid - ISSUE_STAGE + output logic x_valid_o, + // CVXIF write enable - ISSUE_STAGE + output logic x_we_o, + // CVXIF destination register - ISSUE_STAGE + output logic [4:0] x_rd_o, + // CVXIF Result interface - SUBSYSTEM + input logic x_result_valid_i, + input x_result_t x_result_i, + output logic x_result_ready_o, + // CVXIF Issue transaction rejected -> illegal instruction - ISSUE_STAGE + input logic x_transaction_rejected_i, + // accelerate port result is valid - ACC_DISPATCHER + input logic acc_valid_i, + // Accelerator MMU access + input acc_mmu_req_t acc_mmu_req_i, + output acc_mmu_resp_t acc_mmu_resp_o, + // Enable virtual memory translation - CSR_REGFILE + input logic enable_translation_i, + // Enable G-Stage memory translation - CSR_REGFILE + input logic enable_g_translation_i, + // Enable virtual memory translation for load/stores - CSR_REGFILE + input logic en_ld_st_translation_i, + // Enable G-Stage memory translation for load/stores - CSR_REGFILE + input logic en_ld_st_g_translation_i, + // Flush TLB - CONTROLLER + input logic flush_tlb_i, + input logic flush_tlb_vvma_i, + input logic flush_tlb_gvma_i, + // Privilege mode - CSR_REGFILE + input riscv::priv_lvl_t priv_lvl_i, + // Virtualization mode - CSR_REGFILE + input logic v_i, + // Privilege level at which load and stores should happen - CSR_REGFILE + input riscv::priv_lvl_t ld_st_priv_lvl_i, + // Virtualization mode at which load and stores should happen - CSR_REGFILE + input logic ld_st_v_i, + // Instruction is hypervisor load/store - CSR_REGFILE + output logic csr_hs_ld_st_inst_o, + // Supervisor user memory - CSR_REGFILE + input logic sum_i, + // Virtual Supervisor user memory - CSR_REGFILE + input logic vs_sum_i, + // Make executable readable - CSR_REGFILE + input logic mxr_i, + // Make executable readable Virtual Supervisor - CSR_REGFILE + input logic vmxr_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_i, + // TO_BE_COMPLETED - CSR_REGFILE + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_i, + // icache translation response - CACHE + input icache_arsp_t icache_areq_i, + // icache translation request - CACHE + output icache_areq_t icache_areq_o, + // Data cache request ouput - CACHE + input dcache_req_o_t [2:0] dcache_req_ports_i, + // Data cache request input - CACHE + output dcache_req_i_t [2:0] dcache_req_ports_o, + // Write buffer is empty - CACHE + input logic dcache_wbuffer_empty_i, + // TO_BE_COMPLETED - CACHE + input logic dcache_wbuffer_not_ni_i, + // AMO request - CACHE + output amo_req_t amo_req_o, + // AMO response - CACHE + input amo_resp_t amo_resp_i, + // To count the instruction TLB misses - PERF_COUNTERS + output logic itlb_miss_o, + // To count the data TLB misses - PERF_COUNTERS + output logic dtlb_miss_o, + // Report the PMP configuration - CSR_REGFILE + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + // Report the PMP addresses - CSR_REGFILE + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + // Information dedicated to RVFI - RVFI + output lsu_ctrl_t rvfi_lsu_ctrl_o, + // Information dedicated to RVFI - RVFI + output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o +); + + // ------------------------- + // Fixed Latency Units + // ------------------------- + // all fixed latency units share a single issue port and a sing write + // port into the scoreboard. At the moment those are: + // 1. ALU - all operations are single cycle + // 2. Branch unit: operation is single cycle, the ALU is needed + // for comparison + // 3. CSR: This is a small buffer which saves the address of the CSR. + // The value is then re-fetched once the instruction retires. The buffer + // is only a single entry deep, hence this operation will block all + // other operations once this buffer is full. This should not be a major + // concern though as CSRs are infrequent. + // 4. Multiplier/Divider: The multiplier has a fixed latency of 1 cycle. + // The issue logic will take care of not issuing + // another instruction if it will collide on the + // output port. Divisions are arbitrary in length + // they will simply block the issue of all other + // instructions. + + + logic current_instruction_is_sfence_vma; + logic current_instruction_is_hfence_vvma; + logic current_instruction_is_hfence_gvma; + // These two register store the rs1 and rs2 parameters in case of `SFENCE_VMA` + // instruction to be used for TLB flush in the next clock cycle. + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed; + logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed; + logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed; + logic [CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed; + + // from ALU to branch unit + logic alu_branch_res; // branch comparison result + logic [CVA6Cfg.XLEN-1:0] alu_result, csr_result, mult_result; + logic [CVA6Cfg.VLEN-1:0] branch_result; + logic csr_ready, mult_ready; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id; + logic mult_valid; + + logic [CVA6Cfg.NrIssuePorts-1:0] one_cycle_select; + assign one_cycle_select = alu_valid_i | branch_valid_i | csr_valid_i; + + fu_data_t one_cycle_data; + logic [CVA6Cfg.VLEN-1:0] rs1_forwarding; + logic [CVA6Cfg.VLEN-1:0] rs2_forwarding; + always_comb begin + // data silence operation + one_cycle_data = one_cycle_select[0] ? fu_data_i[0] : '0; + rs1_forwarding = rs1_forwarding_i[0]; + rs2_forwarding = rs2_forwarding_i[0]; + + if (CVA6Cfg.SuperscalarEn) begin + if (one_cycle_select[1]) begin + one_cycle_data = fu_data_i[1]; + rs1_forwarding = rs1_forwarding_i[1]; + rs2_forwarding = rs2_forwarding_i[1]; + end + end + end + + // 1. ALU (combinatorial) + alu #( + .CVA6Cfg (CVA6Cfg), + .HasBranch(1'b1), + .fu_data_t(fu_data_t) + ) alu_i ( + .clk_i, + .rst_ni, + .fu_data_i (one_cycle_data), + .result_o (alu_result), + .alu_branch_res_o(alu_branch_res) + ); + + // 2. Branch Unit (combinatorial) + // we don't silence the branch unit as this is already critical and we do + // not want to add another layer of logic + branch_unit #( + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), + .fu_data_t(fu_data_t) + ) branch_unit_i ( + .clk_i, + .rst_ni, + .v_i, + .debug_mode_i, + .fu_data_i (one_cycle_data), + .pc_i, + .is_zcmt_i, + .is_compressed_instr_i, + .branch_valid_i (|branch_valid_i), + .branch_comp_res_i (alu_branch_res), + .branch_result_o (branch_result), + .branch_predict_i, + .resolved_branch_o, + .resolve_branch_o, + .branch_exception_o(flu_exception_o) + ); + + // 3. CSR (sequential) + csr_buffer #( + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) + ) csr_buffer_i ( + .clk_i, + .rst_ni, + .flush_i, + .fu_data_i (one_cycle_data), + .csr_valid_i (|csr_valid_i), + .csr_ready_o (csr_ready), + .csr_result_o(csr_result), + .csr_commit_i, + .csr_addr_o + ); + + assign flu_valid_o = |one_cycle_select | mult_valid; + + // result MUX + always_comb begin + // Branch result as default case + flu_result_o = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, branch_result}; + flu_trans_id_o = one_cycle_data.trans_id; + // ALU result + if (|alu_valid_i) begin + flu_result_o = alu_result; + // CSR result + end else if (|csr_valid_i) begin + flu_result_o = csr_result; + end else if (mult_valid) begin + flu_result_o = mult_result; + flu_trans_id_o = mult_trans_id; + end + end + + // ready flags for FLU + always_comb begin + flu_ready_o = csr_ready & mult_ready; + end + + // 4. Multiplication (Sequential) + fu_data_t mult_data; + // input silencing of multiplier + always_comb begin + mult_data = mult_valid_i[0] ? fu_data_i[0] : '0; + if (CVA6Cfg.SuperscalarEn) begin + if (mult_valid_i[1]) begin + mult_data = fu_data_i[1]; + end + end + end + + mult #( + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) + ) i_mult ( + .clk_i, + .rst_ni, + .flush_i, + .mult_valid_i (|mult_valid_i), + .fu_data_i (mult_data), + .result_o (mult_result), + .mult_valid_o (mult_valid), + .mult_ready_o (mult_ready), + .mult_trans_id_o(mult_trans_id) + ); + + // ---------------- + // FPU + // ---------------- + logic fpu_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id; + logic [CVA6Cfg.XLEN-1:0] fpu_result; + logic alu2_valid; + logic [CVA6Cfg.XLEN-1:0] alu2_result; + + generate + if (CVA6Cfg.FpPresent) begin : fpu_gen + fu_data_t fpu_data; + always_comb begin + fpu_data = fpu_valid_i[0] ? fu_data_i[0] : '0; + if (CVA6Cfg.SuperscalarEn) begin + if (fpu_valid_i[1]) begin + fpu_data = fu_data_i[1]; + end + end + end + + fpu_wrap #( + .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), + .fu_data_t(fu_data_t) + ) fpu_i ( + .clk_i, + .rst_ni, + .flush_i, + .fpu_valid_i(|fpu_valid_i), + .fpu_ready_o, + .fu_data_i(fpu_data), + .fpu_fmt_i, + .fpu_rm_i, + .fpu_frm_i, + .fpu_prec_i, + .fpu_trans_id_o(fpu_trans_id), + .result_o(fpu_result), + .fpu_valid_o(fpu_valid), + .fpu_exception_o + ); + end else begin : no_fpu_gen + assign fpu_ready_o = '0; + assign fpu_trans_id = '0; + assign fpu_result = '0; + assign fpu_valid = '0; + assign fpu_exception_o = '0; + end + endgenerate + + // ---------------- + // ALU2 + // ---------------- + fu_data_t alu2_data; + if (CVA6Cfg.SuperscalarEn) begin : alu2_gen + always_comb begin + alu2_data = alu2_valid_i[0] ? fu_data_i[0] : '0; + if (alu2_valid_i[1]) begin + alu2_data = fu_data_i[1]; + end + end + + alu #( + .CVA6Cfg (CVA6Cfg), + .HasBranch(1'b0), + .fu_data_t(fu_data_t) + ) alu2_i ( + .clk_i, + .rst_ni, + .fu_data_i (alu2_data), + .result_o (alu2_result), + .alu_branch_res_o( /* this ALU does not handle branching */) + ); + end else begin + assign alu2_data = '0; + assign alu2_result = '0; + end + + // result MUX + // This is really explicit so that synthesis tools can elide unused signals + if (CVA6Cfg.SuperscalarEn) begin + if (CVA6Cfg.FpPresent) begin + assign fpu_valid_o = fpu_valid || |alu2_valid_i; + assign fpu_result_o = fpu_valid ? fpu_result : alu2_result; + assign fpu_trans_id_o = fpu_valid ? fpu_trans_id : alu2_data.trans_id; + end else begin + assign fpu_valid_o = |alu2_valid_i; + assign fpu_result_o = alu2_result; + assign fpu_trans_id_o = alu2_data.trans_id; + end + end else begin + if (CVA6Cfg.FpPresent) begin + assign fpu_valid_o = fpu_valid; + assign fpu_result_o = fpu_result; + assign fpu_trans_id_o = fpu_trans_id; + end else begin + assign fpu_valid_o = '0; + assign fpu_result_o = '0; + assign fpu_trans_id_o = '0; + end + end + + // ---------------- + // Load-Store Unit + // ---------------- + fu_data_t lsu_data; + logic [31:0] lsu_tinst; + always_comb begin + lsu_data = lsu_valid_i[0] ? fu_data_i[0] : '0; + lsu_tinst = tinst_i[0]; + + if (CVA6Cfg.SuperscalarEn) begin + if (lsu_valid_i[1]) begin + lsu_data = fu_data_i[1]; + lsu_tinst = tinst_i[1]; + end + end + end + + load_store_unit #( + .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), + .fu_data_t (fu_data_t), + .icache_areq_t(icache_areq_t), + .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), + .lsu_ctrl_t(lsu_ctrl_t), + .acc_mmu_req_t(acc_mmu_req_t), + .acc_mmu_resp_t(acc_mmu_resp_t) + ) lsu_i ( + .clk_i, + .rst_ni, + .flush_i, + .stall_st_pending_i, + .no_st_pending_o, + .fu_data_i (lsu_data), + .lsu_ready_o, + .lsu_valid_i (|lsu_valid_i), + .load_trans_id_o, + .load_result_o, + .load_valid_o, + .load_exception_o, + .store_trans_id_o, + .store_result_o, + .store_valid_o, + .store_exception_o, + .commit_i (lsu_commit_i), + .commit_ready_o (lsu_commit_ready_o), + .commit_tran_id_i, + .enable_translation_i, + .enable_g_translation_i, + .en_ld_st_translation_i, + .en_ld_st_g_translation_i, + .acc_mmu_req_i, + .acc_mmu_resp_o, + .icache_areq_i, + .icache_areq_o, + .priv_lvl_i, + .v_i, + .ld_st_priv_lvl_i, + .ld_st_v_i, + .csr_hs_ld_st_inst_o, + .sum_i, + .vs_sum_i, + .mxr_i, + .vmxr_i, + .satp_ppn_i, + .vsatp_ppn_i, + .hgatp_ppn_i, + .asid_i, + .vs_asid_i, + .asid_to_be_flushed_i (asid_to_be_flushed), + .vmid_i, + .vmid_to_be_flushed_i (vmid_to_be_flushed), + .vaddr_to_be_flushed_i (vaddr_to_be_flushed), + .gpaddr_to_be_flushed_i(gpaddr_to_be_flushed), + .flush_tlb_i, + .flush_tlb_vvma_i, + .flush_tlb_gvma_i, + .itlb_miss_o, + .dtlb_miss_o, + .dcache_req_ports_i, + .dcache_req_ports_o, + .dcache_wbuffer_empty_i, + .dcache_wbuffer_not_ni_i, + .amo_valid_commit_i, + .amo_req_o, + .amo_resp_i, + .tinst_i (lsu_tinst), + .pmpcfg_i, + .pmpaddr_i, + .rvfi_lsu_ctrl_o, + .rvfi_mem_paddr_o + ); + + if (CVA6Cfg.CvxifEn) begin : gen_cvxif + fu_data_t cvxif_data; + always_comb begin + cvxif_data = x_valid_i[0] ? fu_data_i[0] : '0; + if (CVA6Cfg.SuperscalarEn) begin + if (x_valid_i[1]) begin + cvxif_data = fu_data_i[1]; + end + end + end + + cvxif_fu #( + .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), + .x_result_t(x_result_t) + ) cvxif_fu_i ( + .clk_i, + .rst_ni, + .x_valid_i(|x_valid_i), + .x_trans_id_i(cvxif_data.trans_id), + .x_illegal_i(x_transaction_rejected_i), + .x_off_instr_i, + .x_ready_o, + .x_trans_id_o, + .x_exception_o, + .x_result_o, + .x_valid_o, + .x_we_o, + .x_rd_o, + .result_valid_i(x_result_valid_i), + .result_i(x_result_i), + .result_ready_o(x_result_ready_o) + ); + end else begin : gen_no_cvxif + assign x_result_ready_o = '0; + assign x_trans_id_o = '0; + assign x_exception_o = '0; + assign x_result_o = '0; + assign x_valid_o = '0; + end + + if (CVA6Cfg.RVS) begin + if (CVA6Cfg.RVH) begin + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + current_instruction_is_sfence_vma <= 1'b0; + current_instruction_is_hfence_vvma <= 1'b0; + current_instruction_is_hfence_gvma <= 1'b0; + end else begin + // TODO handle this with superscalar (issue only one instruction in this case?) + if (flush_i) begin + current_instruction_is_sfence_vma <= 1'b0; + current_instruction_is_hfence_vvma <= 1'b0; + current_instruction_is_hfence_gvma <= 1'b0; + end else if ((fu_data_i[0].operation == SFENCE_VMA && !v_i) && |csr_valid_i) begin + current_instruction_is_sfence_vma <= 1'b1; + end else if (((fu_data_i[0].operation == SFENCE_VMA && v_i) || fu_data_i[0].operation == HFENCE_VVMA) && |csr_valid_i) begin + current_instruction_is_hfence_vvma <= 1'b1; + end else if ((fu_data_i[0].operation == HFENCE_GVMA) && |csr_valid_i) begin + current_instruction_is_hfence_gvma <= 1'b1; + end + end + end + end else begin + assign current_instruction_is_hfence_vvma = 1'b0; + assign current_instruction_is_hfence_gvma = 1'b0; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + current_instruction_is_sfence_vma <= 1'b0; + end else begin + if (flush_i) begin + current_instruction_is_sfence_vma <= 1'b0; + end else if (fu_data_i[0].operation == SFENCE_VMA && |csr_valid_i) begin + current_instruction_is_sfence_vma <= 1'b1; + end + end + end + end + if (CVA6Cfg.RVH) begin + // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + vmid_to_be_flushed <= '0; + asid_to_be_flushed <= '0; + vaddr_to_be_flushed <= '0; + gpaddr_to_be_flushed <= '0; + // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen + end else if ((~(current_instruction_is_sfence_vma || current_instruction_is_hfence_vvma || current_instruction_is_hfence_gvma)) && (~((fu_data_i[0].operation == SFENCE_VMA || fu_data_i[0].operation == HFENCE_VVMA || fu_data_i[0].operation == HFENCE_GVMA ) && |csr_valid_i))) begin + vaddr_to_be_flushed <= rs1_forwarding; + gpaddr_to_be_flushed <= {2'b00, rs1_forwarding[CVA6Cfg.GPLEN-1:2]}; + asid_to_be_flushed <= rs2_forwarding[CVA6Cfg.ASID_WIDTH-1:0]; + vmid_to_be_flushed <= rs2_forwarding[CVA6Cfg.VMID_WIDTH-1:0]; + end + end + end else begin + assign vmid_to_be_flushed = '0; + assign gpaddr_to_be_flushed = '0; + // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + asid_to_be_flushed <= '0; + vaddr_to_be_flushed <= '0; + // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen + end else if ((~current_instruction_is_sfence_vma) && (~((fu_data_i[0].operation == SFENCE_VMA) && |csr_valid_i))) begin + vaddr_to_be_flushed <= rs1_forwarding; + asid_to_be_flushed <= rs2_forwarding[CVA6Cfg.ASID_WIDTH-1:0]; + end + end + end + end else begin + assign current_instruction_is_sfence_vma = 1'b0; + assign current_instruction_is_hfence_vvma = 1'b0; + assign current_instruction_is_hfence_gvma = 1'b0; + assign asid_to_be_flushed = '0; + assign vaddr_to_be_flushed = '0; + assign vmid_to_be_flushed = '0; + assign gpaddr_to_be_flushed = '0; + end + +endmodule diff --git a/flow/designs/src/cva6/core/fpu_wrap.sv b/flow/designs/src/cva6/core/fpu_wrap.sv new file mode 100644 index 0000000000..c30033463f --- /dev/null +++ b/flow/designs/src/cva6/core/fpu_wrap.sv @@ -0,0 +1,571 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Stefan Mach, ETH Zurich +// Date: 12.04.2018 +// Description: Wrapper for the floating-point unit + + +module fpu_wrap + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, + parameter type fu_data_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic fpu_valid_i, + output logic fpu_ready_o, + input fu_data_t fu_data_i, + + input logic [ 1:0] fpu_fmt_i, + input logic [ 2:0] fpu_rm_i, + input logic [ 2:0] fpu_frm_i, + input logic [ 6:0] fpu_prec_i, + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_o, + output logic [ CVA6Cfg.FLen-1:0] result_o, + output logic fpu_valid_o, + output exception_t fpu_exception_o +); + + // this is a workaround + // otherwise compilation might issue an error if FLEN=0 + enum logic { + READY, + STALL + } + state_q, state_d; + if (CVA6Cfg.FpPresent) begin : fpu_gen + logic [CVA6Cfg.FLen-1:0] operand_a_i; + logic [CVA6Cfg.FLen-1:0] operand_b_i; + logic [CVA6Cfg.FLen-1:0] operand_c_i; + assign operand_a_i = fu_data_i.operand_a[CVA6Cfg.FLen-1:0]; + assign operand_b_i = fu_data_i.operand_b[CVA6Cfg.FLen-1:0]; + assign operand_c_i = fu_data_i.imm[CVA6Cfg.FLen-1:0]; + + //----------------------------------- + // FPnew config from FPnew package + //----------------------------------- + localparam OPBITS = fpnew_pkg::OP_BITS; + localparam FMTBITS = $clog2(fpnew_pkg::NUM_FP_FORMATS); + localparam IFMTBITS = $clog2(fpnew_pkg::NUM_INT_FORMATS); + + // Features (enabled formats, vectors etc.) + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: unsigned'(CVA6Cfg.FLen), // parameterized using CVA6Cfg.FLen + EnableVectors: CVA6Cfg.XFVec, + EnableNanBox: 1'b1, + FpFmtMask: {CVA6Cfg.RVF, CVA6Cfg.RVD, CVA6Cfg.XF16, CVA6Cfg.XF8, CVA6Cfg.XF16ALT}, + IntFmtMask: { + CVA6Cfg.XFVec && CVA6Cfg.XF8, + CVA6Cfg.XFVec && (CVA6Cfg.XF16 || CVA6Cfg.XF16ALT), + 1'b1, + 1'b1 + } + }; + + // Implementation (number of registers etc) + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs: '{ // FP32, FP64, FP16, FP8, FP16alt + '{ + unsigned'(LAT_COMP_FP32), + unsigned'(LAT_COMP_FP64), + unsigned'(LAT_COMP_FP16), + unsigned'(LAT_COMP_FP8), + unsigned'(LAT_COMP_FP16ALT) + }, // ADDMUL + '{default: unsigned'(LAT_DIVSQRT)}, // DIVSQRT + '{default: unsigned'(LAT_NONCOMP)}, // NONCOMP + '{default: unsigned'(LAT_CONV)} + }, // CONV + UnitTypes: '{ + '{default: fpnew_pkg::PARALLEL}, // ADDMUL + '{default: fpnew_pkg::MERGED}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED} + }, // CONV + PipeConfig: fpnew_pkg::DISTRIBUTED + }; + + //------------------------------------------------- + // Inputs to the FPU and protocol inversion buffer + //------------------------------------------------- + logic [CVA6Cfg.FLen-1:0] operand_a_d, operand_a_q, operand_a; + logic [CVA6Cfg.FLen-1:0] operand_b_d, operand_b_q, operand_b; + logic [CVA6Cfg.FLen-1:0] operand_c_d, operand_c_q, operand_c; + logic [OPBITS-1:0] fpu_op_d, fpu_op_q, fpu_op; + logic fpu_op_mod_d, fpu_op_mod_q, fpu_op_mod; + logic [FMTBITS-1:0] fpu_srcfmt_d, fpu_srcfmt_q, fpu_srcfmt; + logic [FMTBITS-1:0] fpu_dstfmt_d, fpu_dstfmt_q, fpu_dstfmt; + logic [IFMTBITS-1:0] fpu_ifmt_d, fpu_ifmt_q, fpu_ifmt; + logic [2:0] fpu_rm_d, fpu_rm_q, fpu_rm; + logic fpu_vec_op_d, fpu_vec_op_q, fpu_vec_op; + + logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_tag_d, fpu_tag_q, fpu_tag; + + logic fpu_in_ready, fpu_in_valid; + logic fpu_out_ready, fpu_out_valid; + + logic [4:0] fpu_status; + + // FSM to handle protocol inversion + logic hold_inputs; + logic use_hold; + + //----------------------------- + // Translate inputs + //----------------------------- + + always_comb begin : input_translation + + automatic logic vec_replication; // control honoring of replication flag + automatic logic replicate_c; // replicate operand C instead of B (for ADD/SUB) + automatic logic check_ah; // Decide for AH from RM field encoding + + // Default Values + operand_a_d = operand_a_i; + operand_b_d = operand_b_i; // immediates come through this port unless used as operand + operand_c_d = operand_c_i; // immediates come through this port unless used as operand + fpu_op_d = fpnew_pkg::SGNJ; // sign injection by default + fpu_op_mod_d = 1'b0; + fpu_dstfmt_d = fpnew_pkg::FP32; + fpu_ifmt_d = fpnew_pkg::INT32; + fpu_rm_d = fpu_rm_i; + fpu_vec_op_d = fu_data_i.fu == FPU_VEC; + fpu_tag_d = fu_data_i.trans_id; + vec_replication = fpu_rm_i[0]; // replication bit is sent via rm field + replicate_c = 1'b0; + check_ah = 1'b0; // whether set scalar AH encoding from MSB of rm_i + + // Scalar Rounding Modes - some ops encode inside RM but use smaller range + if (!(fpu_rm_i inside {[3'b000 : 3'b100]})) fpu_rm_d = fpu_frm_i; + + // Vectorial ops always consult FRM + if (fpu_vec_op_d) fpu_rm_d = fpu_frm_i; + + // Formats + unique case (fpu_fmt_i) + // FP32 + 2'b00: fpu_dstfmt_d = fpnew_pkg::FP32; + // FP64 or FP16ALT (vectorial) + 2'b01: fpu_dstfmt_d = fpu_vec_op_d ? fpnew_pkg::FP16ALT : fpnew_pkg::FP64; + // FP16 or FP16ALT (scalar) + 2'b10: begin + if (!fpu_vec_op_d && fpu_rm_i == 3'b101) fpu_dstfmt_d = fpnew_pkg::FP16ALT; + else fpu_dstfmt_d = fpnew_pkg::FP16; + end + // FP8 + default: fpu_dstfmt_d = fpnew_pkg::FP8; + endcase + + // By default, set src=dst + fpu_srcfmt_d = fpu_dstfmt_d; + + // Operations (this can modify the rounding mode field and format!) + unique case (fu_data_i.operation) + // Addition + FADD: begin + fpu_op_d = fpnew_pkg::ADD; + replicate_c = 1'b1; // second operand is in C + end + // Subtraction is modified ADD + FSUB: begin + fpu_op_d = fpnew_pkg::ADD; + fpu_op_mod_d = 1'b1; + replicate_c = 1'b1; // second operand is in C + end + // Multiplication + FMUL: fpu_op_d = fpnew_pkg::MUL; + // Division + FDIV: fpu_op_d = fpnew_pkg::DIV; + // Min/Max - OP is encoded in rm (000-001) + FMIN_MAX: begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Square Root + FSQRT: fpu_op_d = fpnew_pkg::SQRT; + // Fused Multiply Add + FMADD: fpu_op_d = fpnew_pkg::FMADD; + // Fused Multiply Subtract is modified FMADD + FMSUB: begin + fpu_op_d = fpnew_pkg::FMADD; + fpu_op_mod_d = 1'b1; + end + // Fused Negated Multiply Subtract + FNMSUB: fpu_op_d = fpnew_pkg::FNMSUB; + // Fused Negated Multiply Add is modified FNMSUB + FNMADD: begin + fpu_op_d = fpnew_pkg::FNMSUB; + fpu_op_mod_d = 1'b1; + end + // Float to Int Cast - Op encoded in lowest two imm bits or rm + FCVT_F2I: begin + fpu_op_d = fpnew_pkg::F2I; + // Vectorial Ops encoded in R bit + if (fpu_vec_op_d) begin + fpu_op_mod_d = fpu_rm_i[0]; + vec_replication = 1'b0; // no replication, R bit used for op + unique case (fpu_fmt_i) + 2'b00: fpu_ifmt_d = fpnew_pkg::INT32; + 2'b01, 2'b10: fpu_ifmt_d = fpnew_pkg::INT16; + 2'b11: fpu_ifmt_d = fpnew_pkg::INT8; + endcase + // Scalar casts encoded in imm + end else begin + fpu_op_mod_d = operand_c_i[0]; + if (operand_c_i[1]) fpu_ifmt_d = fpnew_pkg::INT64; + else fpu_ifmt_d = fpnew_pkg::INT32; + end + end + // Int to Float Cast - Op encoded in lowest two imm bits or rm + FCVT_I2F: begin + fpu_op_d = fpnew_pkg::I2F; + // Vectorial Ops encoded in R bit + if (fpu_vec_op_d) begin + fpu_op_mod_d = fpu_rm_i[0]; + vec_replication = 1'b0; // no replication, R bit used for op + unique case (fpu_fmt_i) + 2'b00: fpu_ifmt_d = fpnew_pkg::INT32; + 2'b01, 2'b10: fpu_ifmt_d = fpnew_pkg::INT16; + 2'b11: fpu_ifmt_d = fpnew_pkg::INT8; + endcase + // Scalar casts encoded in imm + end else begin + fpu_op_mod_d = operand_c_i[0]; + if (operand_c_i[1]) fpu_ifmt_d = fpnew_pkg::INT64; + else fpu_ifmt_d = fpnew_pkg::INT32; + end + end + // Float to Float Cast - Source format encoded in lowest two/three imm bits + FCVT_F2F: begin + fpu_op_d = fpnew_pkg::F2F; + // Vectorial ops encoded in lowest two imm bits + if (fpu_vec_op_d) begin + vec_replication = 1'b0; // no replication for casts (not needed) + unique case (operand_c_i[1:0]) + 2'b00: fpu_srcfmt_d = fpnew_pkg::FP32; + 2'b01: fpu_srcfmt_d = fpnew_pkg::FP16ALT; + 2'b10: fpu_srcfmt_d = fpnew_pkg::FP16; + 2'b11: fpu_srcfmt_d = fpnew_pkg::FP8; + endcase + // Scalar ops encoded in lowest three imm bits + end else begin + unique case (operand_c_i[2:0]) + 3'b000: fpu_srcfmt_d = fpnew_pkg::FP32; + 3'b001: fpu_srcfmt_d = fpnew_pkg::FP64; + 3'b010: fpu_srcfmt_d = fpnew_pkg::FP16; + 3'b110: fpu_srcfmt_d = fpnew_pkg::FP16ALT; + 3'b011: fpu_srcfmt_d = fpnew_pkg::FP8; + default: ; // Do nothing + endcase + end + end + // Scalar Sign Injection - op encoded in rm (000-010) + FSGNJ: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Move from FPR to GPR - mapped to SGNJ-passthrough since no recoding + FMV_F2X: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b011; // passthrough without checking nan-box + fpu_op_mod_d = 1'b1; // no NaN-Boxing + check_ah = 1'b1; // AH has RM MSB encoding + vec_replication = 1'b0; // no replication, we set second operand + end + // Move from GPR to FPR - mapped to NOP since no recoding + FMV_X2F: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b011; // passthrough without checking nan-box + check_ah = 1'b1; // AH has RM MSB encoding + vec_replication = 1'b0; // no replication, we set second operand + end + // Scalar Comparisons - op encoded in rm (000-010) + FCMP: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit + check_ah = 1'b1; // AH has RM MSB encoding + end + // Classification + FCLASS: begin + fpu_op_d = fpnew_pkg::CLASSIFY; + fpu_rm_d = { + 1'b0, fpu_rm_i[1:0] + }; // mask out AH encoding bit - CLASS doesn't care anyways + check_ah = 1'b1; // AH has RM MSB encoding + end + // Vectorial Minimum - set up scalar encoding in rm + VFMIN: begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = 3'b000; // min + end + // Vectorial Maximum - set up scalar encoding in rm + VFMAX: begin + fpu_op_d = fpnew_pkg::MINMAX; + fpu_rm_d = 3'b001; // max + end + // Vectorial Sign Injection - set up scalar encoding in rm + VFSGNJ: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b000; // sgnj + end + // Vectorial Negated Sign Injection - set up scalar encoding in rm + VFSGNJN: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b001; // sgnjn + end + // Vectorial Xored Sign Injection - set up scalar encoding in rm + VFSGNJX: begin + fpu_op_d = fpnew_pkg::SGNJ; + fpu_rm_d = 3'b010; // sgnjx + end + // Vectorial Equals - set up scalar encoding in rm + VFEQ: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b010; // eq + end + // Vectorial Not Equals - set up scalar encoding in rm + VFNE: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b010; // eq + end + // Vectorial Less Than - set up scalar encoding in rm + VFLT: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b001; // lt + end + // Vectorial Greater or Equal - set up scalar encoding in rm + VFGE: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b001; // lt + end + // Vectorial Less or Equal - set up scalar encoding in rm + VFLE: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_rm_d = 3'b000; // le + end + // Vectorial Greater Than - set up scalar encoding in rm + VFGT: begin + fpu_op_d = fpnew_pkg::CMP; + fpu_op_mod_d = 1'b1; // invert output + fpu_rm_d = 3'b000; // le + end + // Vectorial Convert-and-Pack from FP32, lower 4 entries + VFCPKAB_S: begin + fpu_op_d = fpnew_pkg::CPKAB; + fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32 + end + // Vectorial Convert-and-Pack from FP32, upper 4 entries + VFCPKCD_S: begin + fpu_op_d = fpnew_pkg::CPKCD; + fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32 + end + // Vectorial Convert-and-Pack from FP64, lower 4 entries + VFCPKAB_D: begin + fpu_op_d = fpnew_pkg::CPKAB; + fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64 + end + // Vectorial Convert-and-Pack from FP64, upper 4 entries + VFCPKCD_D: begin + fpu_op_d = fpnew_pkg::CPKCD; + fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit + vec_replication = 1'b0; // no replication, R bit used for op + fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64 + end + // No changes per default + default: ; //nothing + endcase + + // Scalar AH encoding fixing + if (!fpu_vec_op_d && check_ah) if (fpu_rm_i[2]) fpu_dstfmt_d = fpnew_pkg::FP16ALT; + + // Replication + if (fpu_vec_op_d && vec_replication) begin + if (replicate_c) begin + unique case (fpu_dstfmt_d) + fpnew_pkg::FP32: operand_c_d = CVA6Cfg.RVD ? {2{operand_c_i[31:0]}} : operand_c_i; + fpnew_pkg::FP16, fpnew_pkg::FP16ALT: + operand_c_d = CVA6Cfg.RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}}; + fpnew_pkg::FP8: + operand_c_d = CVA6Cfg.RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}}; + default: ; // Do nothing + endcase // fpu_dstfmt_d + end else begin + unique case (fpu_dstfmt_d) + fpnew_pkg::FP32: operand_b_d = CVA6Cfg.RVD ? {2{operand_b_i[31:0]}} : operand_b_i; + fpnew_pkg::FP16, fpnew_pkg::FP16ALT: + operand_b_d = CVA6Cfg.RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}}; + fpnew_pkg::FP8: + operand_b_d = CVA6Cfg.RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}}; + default: ; // Do nothing + endcase // fpu_dstfmt_d + end + end + end + + + //--------------------------------------------------------- + // Upstream protocol inversion: InValid depends on InReady + //--------------------------------------------------------- + + always_comb begin : p_inputFSM + // Default Values + fpu_ready_o = 1'b0; + fpu_in_valid = 1'b0; + hold_inputs = 1'b0; // hold register disabled + use_hold = 1'b0; // inputs go directly to unit + state_d = state_q; // stay in the same state + + // FSM + unique case (state_q) + // Default state, ready for instructions + READY: begin + fpu_ready_o = 1'b1; // Act as if FPU ready + fpu_in_valid = fpu_valid_i; // Forward input valid to FPU + // There is a transaction but the FPU can't handle it + if (fpu_valid_i & ~fpu_in_ready) begin + fpu_ready_o = 1'b0; // No token given to Issue + hold_inputs = 1'b1; // save inputs to the holding register + state_d = STALL; // stall future incoming requests + end + end + // We're stalling the upstream (ready=0) + STALL: begin + fpu_in_valid = 1'b1; // we have data for the FPU + use_hold = 1'b1; // the data comes from the hold reg + // Wait until it's consumed + if (fpu_in_ready) begin + fpu_ready_o = 1'b1; // Give a token to issue + state_d = READY; // accept future requests + end + end + // Default: emit default values + default: ; + endcase + + // Flushing will override issue and go back to idle + if (flush_i) begin + state_d = READY; + end + + end + + // Buffer register and FSM state holding + always_ff @(posedge clk_i or negedge rst_ni) begin : fp_hold_reg + if (~rst_ni) begin + state_q <= READY; + operand_a_q <= '0; + operand_b_q <= '0; + operand_c_q <= '0; + fpu_op_q <= '0; + fpu_op_mod_q <= '0; + fpu_srcfmt_q <= '0; + fpu_dstfmt_q <= '0; + fpu_ifmt_q <= '0; + fpu_rm_q <= '0; + fpu_vec_op_q <= '0; + fpu_tag_q <= '0; + end else begin + state_q <= state_d; + // Hold register is [TRIGGERED] by FSM + if (hold_inputs) begin + operand_a_q <= operand_a_d; + operand_b_q <= operand_b_d; + operand_c_q <= operand_c_d; + fpu_op_q <= fpu_op_d; + fpu_op_mod_q <= fpu_op_mod_d; + fpu_srcfmt_q <= fpu_srcfmt_d; + fpu_dstfmt_q <= fpu_dstfmt_d; + fpu_ifmt_q <= fpu_ifmt_d; + fpu_rm_q <= fpu_rm_d; + fpu_vec_op_q <= fpu_vec_op_d; + fpu_tag_q <= fpu_tag_d; + end + end + end + + // Select FPU input data: from register if valid data in register, else directly from input + assign operand_a = use_hold ? operand_a_q : operand_a_d; + assign operand_b = use_hold ? operand_b_q : operand_b_d; + assign operand_c = use_hold ? operand_c_q : operand_c_d; + assign fpu_op = use_hold ? fpu_op_q : fpu_op_d; + assign fpu_op_mod = use_hold ? fpu_op_mod_q : fpu_op_mod_d; + assign fpu_srcfmt = use_hold ? fpu_srcfmt_q : fpu_srcfmt_d; + assign fpu_dstfmt = use_hold ? fpu_dstfmt_q : fpu_dstfmt_d; + assign fpu_ifmt = use_hold ? fpu_ifmt_q : fpu_ifmt_d; + assign fpu_rm = use_hold ? fpu_rm_q : fpu_rm_d; + assign fpu_vec_op = use_hold ? fpu_vec_op_q : fpu_vec_op_d; + assign fpu_tag = use_hold ? fpu_tag_q : fpu_tag_d; + + // Consolidate operands + logic [2:0][CVA6Cfg.FLen-1:0] fpu_operands; + + assign fpu_operands[0] = operand_a; + assign fpu_operands[1] = operand_b; + assign fpu_operands[2] = operand_c; + + //--------------- + // FPU instance + //--------------- + + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation(FPU_IMPLEMENTATION), + .TagType (logic [CVA6Cfg.TRANS_ID_BITS-1:0]) + ) i_fpnew_bulk ( + .clk_i, + .rst_ni, + .operands_i (fpu_operands), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rm)), + .op_i (fpnew_pkg::operation_e'(fpu_op)), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpnew_pkg::fp_format_e'(fpu_srcfmt)), + .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dstfmt)), + .int_fmt_i (fpnew_pkg::int_format_e'(fpu_ifmt)), + .vectorial_op_i(fpu_vec_op), + .tag_i (fpu_tag), + .simd_mask_i (1'b1), + .in_valid_i (fpu_in_valid), + .in_ready_o (fpu_in_ready), + .flush_i, + .result_o, + .status_o (fpu_status), + .tag_o (fpu_trans_id_o), + .out_valid_o (fpu_out_valid), + .out_ready_i (fpu_out_ready), + .busy_o ( /* unused */) + ); + + // Pack status flag into exception cause, tval ignored in wb, exception is always invalid + assign fpu_exception_o.cause = {59'h0, fpu_status}; + assign fpu_exception_o.valid = 1'b0; + assign fpu_exception_o.tval = '0; + + // Donwstream write port is dedicated to FPU and always ready + assign fpu_out_ready = 1'b1; + + // Downstream valid from unit + assign fpu_valid_o = fpu_out_valid; + + end +endmodule diff --git a/flow/designs/src/cva6/core/frontend/bht.sv b/flow/designs/src/cva6/core/frontend/bht.sv new file mode 100644 index 0000000000..e95c536770 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/bht.sv @@ -0,0 +1,313 @@ +// Copyright 2018 - 2019 ETH Zurich and University of Bologna. +// Copyright 2023 - Thales for additionnal contribution. +// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 2.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-2.0. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.02.2018 +// Migrated: Luis Vitorio Cargnini, IEEE +// Date: 09.06.2018 +// FPGA optimization: Sebastien Jacq, Thales +// Date: 2023-01-30 +// FPGA optimization for Altera: Angela Gonzalez, PlanV Technolgies +// Date: 2024-10-16 + +// branch history table - 2 bit saturation counter + +module bht #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bht_update_t = logic, + parameter int unsigned NR_ENTRIES = 1024 +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Branch prediction flush request - zero + input logic flush_bp_i, + // Debug mode state - CSR + input logic debug_mode_i, + // Virtual PC - CACHE + input logic [CVA6Cfg.VLEN-1:0] vpc_i, + // Update bht with resolved address - EXECUTE + input bht_update_t bht_update_i, + // Prediction from bht - FRONTEND + output ariane_pkg::bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_o +); + // the last bit is always zero, we don't need it for indexing + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; + // re-shape the branch history table + localparam NR_ROWS = NR_ENTRIES / CVA6Cfg.INSTR_PER_FETCH; + // number of bits needed to index the row + localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH); + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1; + // number of bits we should use for prediction + localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; + + struct packed { + logic valid; + logic [1:0] saturation_counter; + } + bht_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0], + bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + + logic [$clog2(NR_ROWS)-1:0] index, update_pc; + logic [ROW_INDEX_BITS-1:0] update_row_index, update_row_index_q, check_update_row_index; + + assign index = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_pc = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + if (CVA6Cfg.RVC) begin : gen_update_row_index + assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign update_row_index = '0; + end + + if (!CVA6Cfg.FpgaEn) begin : gen_asic_bht // ASIC TARGET + + logic [1:0] saturation_counter; + // prediction assignment + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_output + assign bht_prediction_o[i].valid = bht_q[index][i].valid; + assign bht_prediction_o[i].taken = bht_q[index][i].saturation_counter[1] == 1'b1; + end + + always_comb begin : update_bht + bht_d = bht_q; + saturation_counter = bht_q[update_pc][update_row_index].saturation_counter; + + if ((bht_update_i.valid && CVA6Cfg.DebugEn && !debug_mode_i) || (bht_update_i.valid && !CVA6Cfg.DebugEn)) begin + bht_d[update_pc][update_row_index].valid = 1'b1; + + if (saturation_counter == 2'b11) begin + // we can safely decrease it + if (!bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter = saturation_counter - 1; + // then check if it saturated in the negative regime e.g.: branch not taken + end else if (saturation_counter == 2'b00) begin + // we can safely increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter = saturation_counter + 1; + end else begin // otherwise we are not in any boundaries and can decrease or increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter = saturation_counter + 1; + else bht_d[update_pc][update_row_index].saturation_counter = saturation_counter - 1; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int unsigned i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j] <= '0; + end + end + end else begin + // evict all entries + if (flush_bp_i) begin + for (int i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j].valid <= 1'b0; + bht_q[i][j].saturation_counter <= 2'b10; + end + end + end else begin + bht_q <= bht_d; + end + end + end + + end else begin : gen_fpga_bht //FPGA TARGETS + + // number of bits par word in the bram + localparam BRAM_WORD_BITS = $bits(ariane_pkg::bht_t); + logic [ROW_INDEX_BITS-1:0] row_index, row_index_q, check_row_index; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_ram_we, bht_ram_we_q; + logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_0; + logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] bht_ram_read_address_1; + logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] + bht_ram_write_address, bht_ram_write_address_q; + logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_wdata, bht_ram_wdata_q; + logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_0; + logic [CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] bht_ram_rdata_1; + + ariane_pkg::bht_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht; + ariane_pkg::bht_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_updated; + + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][1:0] bht_updated_valid; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][1:0][CVA6Cfg.VLEN-1:0] bht_updated_pc; + logic bht_update_taken, check_bht_update_taken; + logic [CVA6Cfg.VLEN-1:0] vpc_q; + + if (CVA6Cfg.RVC) begin : gen_row_index + assign row_index = vpc_i[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign row_index = '0; + end + + // ------------------------- + // prediction assignment & update Branch History Table + // ------------------------- + always_comb begin : prediction_update_bht + bht_ram_we = '0; + bht_ram_read_address_0 = '0; + bht_ram_read_address_1 = '0; + bht_ram_write_address = '0; + bht_ram_wdata = '0; + bht_updated = '0; + bht = '0; + + //Write to RAM + if (bht_update_i.valid && !debug_mode_i) begin + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + if (update_row_index == i) begin + bht_updated[i].valid = 1'b1; + bht_ram_we[i] = 1'b1; + bht_ram_write_address[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc; + end + end + end + + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + + //When synchronous RAM is used, addresses are needed as soon as available + if (CVA6Cfg.FpgaAlteraEn) + bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index; + if (CVA6Cfg.FpgaAlteraEn) + bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc; + + if (check_update_row_index == i) begin + //When asynchronous RAM is used, the address can be updated on the cycle when data is read + if (!CVA6Cfg.FpgaAlteraEn) + bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc; + bht[i].saturation_counter = bht_ram_rdata_1[i*BRAM_WORD_BITS+:2]; + + if (bht[i].saturation_counter == 2'b11) begin + // we can safely decrease it + if (!check_bht_update_taken) + bht_updated[i].saturation_counter = bht[i].saturation_counter - 1; + else bht_updated[i].saturation_counter = 2'b11; + // then check if it saturated in the negative regime e.g.: branch not taken + end else if (bht[i].saturation_counter == 2'b00) begin + // we can safely increase it + if (check_bht_update_taken) + bht_updated[i].saturation_counter = bht[i].saturation_counter + 1; + else bht_updated[i].saturation_counter = 2'b00; + end else begin // otherwise we are not in any boundaries and can decrease or increase it + if (check_bht_update_taken) + bht_updated[i].saturation_counter = bht[i].saturation_counter + 1; + else bht_updated[i].saturation_counter = bht[i].saturation_counter - 1; + end + + //The data written in the RAM will have the valid bit from current input (async RAM) or the one from one clock cycle before (sync RAM) + bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS] = CVA6Cfg.FpgaAlteraEn ? {bht_updated_valid[i][0], bht_updated[i].saturation_counter} : + {bht_updated[i].valid, bht_updated[i].saturation_counter}; + end + + + if (!rst_ni) begin + //initialize output + bht_prediction_o[i] = '0; + end else begin + //When asynchronous RAM is used, addresses can be calculated on the same cycle as data is read + if (!CVA6Cfg.FpgaAlteraEn) + bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index; + //When synchronous RAM is used and data is read right after writing, we need some buffering + // This is one cycle of buffering + if (CVA6Cfg.FpgaAlteraEn && bht_updated_valid[i][0] && vpc_q == bht_updated_pc[i][0]) begin + bht_prediction_o[i].valid = bht_ram_wdata[i*BRAM_WORD_BITS+2]; + bht_prediction_o[i].taken = bht_ram_wdata[i*BRAM_WORD_BITS+1]; + //This is two cycles of buffering + end else if (CVA6Cfg.FpgaAlteraEn && bht_updated_valid[i][1] && vpc_q == bht_updated_pc[i][1]) begin + bht_prediction_o[i].valid = bht_ram_wdata_q[i*BRAM_WORD_BITS+2]; + bht_prediction_o[i].taken = bht_ram_wdata_q[i*BRAM_WORD_BITS+1]; + //In any other case we can safely read from the RAM as data is available + end else begin + bht_prediction_o[i].valid = bht_ram_rdata_0[i*BRAM_WORD_BITS+2]; + bht_prediction_o[i].taken = bht_ram_rdata_0[i*BRAM_WORD_BITS+1]; + end + end + end + end + + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_ram + if (CVA6Cfg.FpgaAlteraEn) begin + SyncThreePortRam #( + .ADDR_WIDTH($clog2(NR_ROWS)), + .DATA_DEPTH(NR_ROWS), + .DATA_WIDTH(BRAM_WORD_BITS) + ) i_bht_ram ( + .Clk_CI (clk_i), + .WrEn_SI (bht_ram_we_q[i]), + .WrAddr_DI (bht_ram_write_address_q[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .WrData_DI (bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdAddr_DI_0(bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .RdAddr_DI_1(bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .RdData_DO_0(bht_ram_rdata_0[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdData_DO_1(bht_ram_rdata_1[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]) + ); + + end else begin + AsyncThreePortRam #( + .ADDR_WIDTH($clog2(NR_ROWS)), + .DATA_DEPTH(NR_ROWS), + .DATA_WIDTH(BRAM_WORD_BITS) + ) i_bht_ram ( + .Clk_CI (clk_i), + .WrEn_SI (bht_ram_we[i]), + .WrAddr_DI (bht_ram_write_address[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .WrData_DI (bht_ram_wdata[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdAddr_DI_0(bht_ram_read_address_0[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .RdAddr_DI_1(bht_ram_read_address_1[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .RdData_DO_0(bht_ram_rdata_0[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdData_DO_1(bht_ram_rdata_1[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]) + ); + end + end + + // Extra buffering signals needed when synchronous RAM is used + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (CVA6Cfg.FpgaAlteraEn) begin + if (!rst_ni) begin + bht_updated_valid <= '0; + bht_update_taken <= '0; + bht_ram_wdata_q <= '0; + row_index_q <= '0; + bht_ram_we_q <= '0; + bht_ram_write_address_q <= '0; + update_row_index_q <= '0; + end else begin + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + bht_updated_valid[i][1] <= bht_updated_valid[i][0]; + bht_updated_valid[i][0] <= bht_updated[i].valid; + bht_updated_pc[i][1] <= bht_updated_pc[i][0]; + bht_updated_pc[i][0] <= bht_update_i.pc; + + end + vpc_q <= vpc_i; + bht_update_taken <= bht_update_i.taken; + bht_ram_wdata_q <= bht_ram_wdata; + bht_ram_we_q <= bht_ram_we; + bht_ram_write_address_q <= bht_ram_write_address; + update_row_index_q <= update_row_index; + + row_index_q <= row_index; + end + end + end + + // Assignment of indexes checked to generate data written in the RAM. When synchronous RAM is used these signals need to be delayed + assign check_update_row_index = CVA6Cfg.FpgaAlteraEn ? update_row_index_q : update_row_index; + assign check_bht_update_taken = CVA6Cfg.FpgaAlteraEn ? bht_update_taken : bht_update_i.taken; + assign check_row_index = CVA6Cfg.FpgaAlteraEn ? row_index_q : row_index; + + end +endmodule diff --git a/flow/designs/src/cva6/core/frontend/bht2lvl.sv b/flow/designs/src/cva6/core/frontend/bht2lvl.sv new file mode 100644 index 0000000000..7b0d4ad821 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/bht2lvl.sv @@ -0,0 +1,133 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Original author: Gianmarco Ottavi, University of Bologna +// Description: Private history BHT + +module bht2lvl #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bht_update_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic [ CVA6Cfg.VLEN-1:0] vpc_i, + input bht_update_t bht_update_i, + // we potentially need INSTR_PER_FETCH predictions/cycle + output ariane_pkg::bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_o +); + + // the last bit is always zero, we don't need it for indexing + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; + // re-shape the branch history table + localparam NR_ROWS = CVA6Cfg.BHTEntries / CVA6Cfg.INSTR_PER_FETCH; + // number of bits needed to index the row + localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH); + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1; + // number of bits we should use for prediction + localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; + + struct packed { + logic valid; + logic [CVA6Cfg.BHTHist-1:0] hist; + logic [2**CVA6Cfg.BHTHist-1:0][1:0] saturation_counter; + } + bht_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0], + bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + + + logic [$clog2(NR_ROWS)-1:0] index, update_pc; + logic [CVA6Cfg.BHTHist-1:0] update_hist; + logic [ ROW_INDEX_BITS-1:0] update_row_index; + + assign index = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_pc = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_hist = bht_q[update_pc][update_row_index].hist; + + if (CVA6Cfg.RVC) begin : gen_update_row_index + assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign update_row_index = '0; + end + + + logic [1:0] saturation_counter; + + // Get the current history of the entry + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.BHTHist-1:0] read_history; + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + assign read_history[i] = bht_q[index][i].hist; + end + + // prediction assignment + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_output + assign bht_prediction_o[i].valid = bht_q[index][i].valid; + assign bht_prediction_o[i].taken = bht_q[index][i].saturation_counter[read_history[i]][1] == 1'b1; + end + + always_comb begin : update_bht + bht_d = bht_q; + saturation_counter = bht_q[update_pc][update_row_index].saturation_counter[update_hist]; + + if (bht_update_i.valid) begin + bht_d[update_pc][update_row_index].valid = 1'b1; + + if (saturation_counter == 2'b11) begin + // we can safely decrease it + if (!bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + // then check if it saturated in the negative regime e.g.: branch not taken + end else if (saturation_counter == 2'b00) begin + // we can safely increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + end else begin // otherwise we are not in any boundaries and can decrease or increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + else + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + end + + bht_d[update_pc][update_row_index].hist = { + update_hist[CVA6Cfg.BHTHist-2:0], bht_update_i.taken + }; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int unsigned i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j] <= '0; + for (int k = 0; k < 2 ** CVA6Cfg.BHTHist; k++) begin + bht_q[i][j].saturation_counter[k] <= 2'b10; + end + end + end + end else begin + // evict all entries + if (flush_i) begin + for (int i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + bht_q[i][j].valid <= 1'b0; + bht_q[i][j].hist <= '0; + for (int k = 0; k < 2 ** CVA6Cfg.BHTHist; k++) begin + bht_q[i][j].saturation_counter[k] <= 2'b10; + end + end + end + end else begin + bht_q <= bht_d; + end + end + end + + +endmodule diff --git a/flow/designs/src/cva6/core/frontend/btb.sv b/flow/designs/src/cva6/core/frontend/btb.sv new file mode 100644 index 0000000000..139f6558c7 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/btb.sv @@ -0,0 +1,193 @@ +// Copyright 2018 - 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 2.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-2.0. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.02.2018 +// Migrated: Luis Vitorio Cargnini, IEEE +// Date: 09.06.2018 +// +// Additional contributions by: +// Sebastien Jacq, Thales - sjthales on github.com +// Date: 2022-12-01 +// +// Description: This module is an adaptation of the BTB (Branch Target Buffer) +// module both FPGA and ASIC targets. +// Prediction target address is stored in BRAM on FPGA while for +// original module, target address is stored in D flip-flop. +// For FPGA flushing is not supported because the frontend module +// flushing signal is not connected. +// +// branch target buffer +module btb #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type btb_update_t = logic, + parameter type btb_prediction_t = logic, + parameter int NR_ENTRIES = 8 +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Branch prediction flush request - zero + input logic flush_bp_i, + // Debug mode state - CSR + input logic debug_mode_i, + // Virtual PC - CACHE + input logic [CVA6Cfg.VLEN-1:0] vpc_i, + // Update BTB with resolved address - EXECUTE + input btb_update_t btb_update_i, + // BTB Prediction - FRONTEND + output btb_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] btb_prediction_o +); + // the last bit is always zero, we don't need it for indexing + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; + // re-shape the branch history table + localparam NR_ROWS = NR_ENTRIES / CVA6Cfg.INSTR_PER_FETCH; + // number of bits needed to index the row + localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH); + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1; + // number of bits we should use for prediction + localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; + // prevent aliasing to degrade performance + localparam ANTIALIAS_BITS = 8; + // number of bits par word in the bram + localparam BRAM_WORD_BITS = $bits(btb_prediction_t); + // we are not interested in all bits of the address + unread i_unread (.d_i(|vpc_i)); + + + logic [$clog2(NR_ROWS)-1:0] index, update_pc; + logic [ROW_INDEX_BITS-1:0] update_row_index; + + assign index = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_pc = btb_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + if (CVA6Cfg.RVC) begin : gen_update_row_index + assign update_row_index = btb_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign update_row_index = '0; + end + + if (CVA6Cfg.FpgaEn) begin : gen_fpga_btb //FPGA TARGETS + logic [ CVA6Cfg.INSTR_PER_FETCH-1:0] btb_ram_csel_prediction; + logic [ CVA6Cfg.INSTR_PER_FETCH-1:0] btb_ram_we_prediction; + logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] btb_ram_addr_prediction; + logic [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] btb_ram_wdata_prediction; + logic [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] btb_ram_rdata_prediction; + + logic [ CVA6Cfg.INSTR_PER_FETCH-1:0] btb_ram_csel_update; + logic [ CVA6Cfg.INSTR_PER_FETCH-1:0] btb_ram_we_update; + logic [CVA6Cfg.INSTR_PER_FETCH*$clog2(NR_ROWS)-1:0] btb_ram_addr_update; + logic [ CVA6Cfg.INSTR_PER_FETCH*BRAM_WORD_BITS-1:0] btb_ram_wdata_update; + + // output matching prediction + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_btb_output + assign btb_ram_csel_prediction[i] = 1'b1; + assign btb_ram_we_prediction[i] = 1'b0; + assign btb_ram_wdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS] = '0; + assign btb_ram_addr_prediction[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = index; + assign btb_prediction_o[i] = btb_ram_rdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]; + end + + // ------------------------- + // Update Branch Prediction + // ------------------------- + // update on a mis-predict + always_comb begin : update_branch_predict + btb_ram_csel_update = '0; + btb_ram_we_update = '0; + btb_ram_addr_update = '0; + btb_ram_wdata_update = '0; + + if (btb_update_i.valid && !debug_mode_i) begin + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + if (update_row_index == i) begin + btb_ram_csel_update[i] = 1'b1; + btb_ram_we_update[i] = 1'b1; + btb_ram_addr_update[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)] = update_pc; + btb_ram_wdata_update[i*BRAM_WORD_BITS+:BRAM_WORD_BITS] = { + 1'b1, btb_update_i.target_address + }; + end + end + end + end + + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_btb_ram + SyncDpRam #( + .ADDR_WIDTH($clog2(NR_ROWS)), + .DATA_DEPTH(NR_ROWS), + .DATA_WIDTH(BRAM_WORD_BITS), + .OUT_REGS (0), + .SIM_INIT (1) + ) i_btb_ram ( + .Clk_CI (clk_i), + .Rst_RBI (rst_ni), + //---------------------------- + .CSelA_SI (btb_ram_csel_update[i]), + .WrEnA_SI (btb_ram_we_update[i]), + .AddrA_DI (btb_ram_addr_update[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .WrDataA_DI(btb_ram_wdata_update[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdDataA_DO(), + //----------------------------- + .CSelB_SI (btb_ram_csel_prediction[i]), + .WrEnB_SI (btb_ram_we_prediction[i]), + .AddrB_DI (btb_ram_addr_prediction[i*$clog2(NR_ROWS)+:$clog2(NR_ROWS)]), + .WrDataB_DI(btb_ram_wdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]), + .RdDataB_DO(btb_ram_rdata_prediction[i*BRAM_WORD_BITS+:BRAM_WORD_BITS]) + ); + end + + end else begin : gen_asic_btb // ASIC TARGET + + // typedef for all branch target entries + // we may want to try to put a tag field that fills the rest of the PC in-order to mitigate aliasing effects + btb_prediction_t + btb_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0], + btb_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + + // output matching prediction + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_btb_output + assign btb_prediction_o[i] = btb_q[index][i]; // workaround + end + + // ------------------------- + // Update Branch Prediction + // ------------------------- + // update on a mis-predict + always_comb begin : update_branch_predict + btb_d = btb_q; + + if (btb_update_i.valid && !debug_mode_i) begin + btb_d[update_pc][update_row_index].valid = 1'b1; + // the target address is simply updated + btb_d[update_pc][update_row_index].target_address = btb_update_i.target_address; + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + // Bias the branches to be taken upon first arrival + for (int i = 0; i < NR_ROWS; i++) btb_q[i] <= '{default: 0}; + end else begin + // evict all entries + if (flush_bp_i) begin + for (int i = 0; i < NR_ROWS; i++) begin + for (int j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin + btb_q[i][j].valid <= 1'b0; + end + end + end else begin + btb_q <= btb_d; + end + end + end + end +endmodule diff --git a/flow/designs/src/cva6/core/frontend/frontend.sv b/flow/designs/src/cva6/core/frontend/frontend.sv new file mode 100644 index 0000000000..3133fff625 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/frontend.sv @@ -0,0 +1,590 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.02.2018 +// Description: Ariane Instruction Fetch Frontend +// +// This module interfaces with the instruction cache, handles control +// change request from the back-end and does branch prediction. + +module frontend + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type fetch_entry_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Next PC when reset - SUBSYSTEM + input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, + // Flush branch prediction - zero + input logic flush_bp_i, + // Flush requested by FENCE, mis-predict and exception - CONTROLLER + input logic flush_i, + // Halt requested by WFI and Accelerate port - CONTROLLER + input logic halt_i, + // Set COMMIT PC as next PC requested by FENCE, CSR side-effect and Accelerate port - CONTROLLER + input logic set_pc_commit_i, + // COMMIT PC - COMMIT + input logic [CVA6Cfg.VLEN-1:0] pc_commit_i, + // Exception event - COMMIT + input logic ex_valid_i, + // Mispredict event and next PC - EXECUTE + input bp_resolve_t resolved_branch_i, + // Return from exception event - CSR + input logic eret_i, + // Next PC when returning from exception - CSR + input logic [CVA6Cfg.VLEN-1:0] epc_i, + // Next PC when jumping into exception - CSR + input logic [CVA6Cfg.VLEN-1:0] trap_vector_base_i, + // Debug event - CSR + input logic set_debug_pc_i, + // Debug mode state - CSR + input logic debug_mode_i, + // Handshake between CACHE and FRONTEND (fetch) - CACHES + output icache_dreq_t icache_dreq_o, + // Handshake between CACHE and FRONTEND (fetch) - CACHES + input icache_drsp_t icache_dreq_i, + // Handshake's data between fetch and decode - ID_STAGE + output fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_o, + // Handshake's valid between fetch and decode - ID_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_o, + // Handshake's ready between fetch and decode - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_i +); + + localparam type bht_update_t = struct packed { + logic valid; + logic [CVA6Cfg.VLEN-1:0] pc; // update at PC + logic taken; + }; + + localparam type btb_prediction_t = struct packed { + logic valid; + logic [CVA6Cfg.VLEN-1:0] target_address; + }; + + localparam type btb_update_t = struct packed { + logic valid; + logic [CVA6Cfg.VLEN-1:0] pc; // update at PC + logic [CVA6Cfg.VLEN-1:0] target_address; + }; + + localparam type ras_t = struct packed { + logic valid; + logic [CVA6Cfg.VLEN-1:0] ra; + }; + + // Instruction Cache Registers, from I$ + logic [ CVA6Cfg.FETCH_WIDTH-1:0] icache_data_q; + logic icache_valid_q; + ariane_pkg::frontend_exception_t icache_ex_valid_q; + logic [ CVA6Cfg.VLEN-1:0] icache_vaddr_q; + logic [ CVA6Cfg.GPLEN-1:0] icache_gpaddr_q; + logic [ 31:0] icache_tinst_q; + logic icache_gva_q; + logic instr_queue_ready; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_queue_consumed; + // upper-most branch-prediction from last cycle + btb_prediction_t btb_q; + bht_prediction_t bht_q; + // instruction fetch is ready + logic if_ready; + logic [CVA6Cfg.VLEN-1:0] npc_d, npc_q; // next PC + + // indicates whether we come out of reset (then we need to load boot_addr_i) + logic npc_rst_load_q; + + logic replay; + logic [ CVA6Cfg.VLEN-1:0] replay_addr; + + // shift amount + logic [$clog2(CVA6Cfg.INSTR_PER_FETCH)-1:0] shamt; + // address will always be 16 bit aligned, make this explicit here + if (CVA6Cfg.RVC) begin : gen_shamt + assign shamt = icache_dreq_i.vaddr[$clog2(CVA6Cfg.INSTR_PER_FETCH):1]; + end else begin + assign shamt = 1'b0; + end + + // ----------------------- + // Ctrl Flow Speculation + // ----------------------- + // RVI ctrl flow prediction + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvi_return, rvi_call, rvi_branch, rvi_jalr, rvi_jump; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvi_imm; + // RVC branching + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvc_branch, rvc_jump, rvc_jr, rvc_return, rvc_jalr, rvc_call; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvc_imm; + // re-aligned instruction and address (coming from cache - combinationally) + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][ 31:0] instr; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] addr; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instruction_valid; + // BHT, BTB and RAS prediction + bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction; + btb_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] btb_prediction; + bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_shifted; + btb_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] btb_prediction_shifted; + ras_t ras_predict; + logic [ CVA6Cfg.VLEN-1:0] vpc_btb; + logic [ CVA6Cfg.VLEN-1:0] vpc_bht; + + // branch-predict update + logic is_mispredict; + logic ras_push, ras_pop; + logic [ CVA6Cfg.VLEN-1:0] ras_update; + + // Instruction FIFO + logic [ CVA6Cfg.VLEN-1:0] predict_address; + cf_t [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_type; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] taken_rvi_cf; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] taken_rvc_cf; + + logic serving_unaligned; + // Re-align instructions + instr_realign #( + .CVA6Cfg(CVA6Cfg) + ) i_instr_realign ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (icache_dreq_o.kill_s2), + .valid_i (icache_valid_q), + .serving_unaligned_o(serving_unaligned), + .address_i (icache_vaddr_q), + .data_i (icache_data_q), + .valid_o (instruction_valid), + .addr_o (addr), + .instr_o (instr) + ); + // -------------------- + // Branch Prediction + // -------------------- + // select the right branch prediction result + // in case we are serving an unaligned instruction in instr[0] we need to take + // the prediction we saved from the previous fetch + if (CVA6Cfg.RVC) begin : gen_btb_prediction_shifted + assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][$clog2( + CVA6Cfg.INSTR_PER_FETCH + ):1]]; + assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][$clog2( + CVA6Cfg.INSTR_PER_FETCH + ):1]]; + + // for all other predictions we can use the generated address to index + // into the branch prediction data structures + for (genvar i = 1; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_prediction_address + assign bht_prediction_shifted[i] = bht_prediction[addr[i][$clog2(CVA6Cfg.INSTR_PER_FETCH):1]]; + assign btb_prediction_shifted[i] = btb_prediction[addr[i][$clog2(CVA6Cfg.INSTR_PER_FETCH):1]]; + end + end else begin + assign bht_prediction_shifted[0] = (serving_unaligned) ? bht_q : bht_prediction[addr[0][1]]; + assign btb_prediction_shifted[0] = (serving_unaligned) ? btb_q : btb_prediction[addr[0][1]]; + end + ; + + // for the return address stack it doens't matter as we have the + // address of the call/return already + logic bp_valid; + + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_branch; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_call; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_jump; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_return; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_jalr; + + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + // branch history table -> BHT + assign is_branch[i] = instruction_valid[i] & (rvi_branch[i] | rvc_branch[i]); + // function calls -> RAS + assign is_call[i] = instruction_valid[i] & (rvi_call[i] | rvc_call[i]); + // function return -> RAS + assign is_return[i] = instruction_valid[i] & (rvi_return[i] | rvc_return[i]); + // unconditional jumps with known target -> immediately resolved + assign is_jump[i] = instruction_valid[i] & (rvi_jump[i] | rvc_jump[i]); + // unconditional jumps with unknown target -> BTB + assign is_jalr[i] = instruction_valid[i] & ~is_return[i] & (rvi_jalr[i] | rvc_jalr[i] | rvc_jr[i]); + end + + // taken/not taken + always_comb begin + taken_rvi_cf = '0; + taken_rvc_cf = '0; + predict_address = '0; + + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) cf_type[i] = ariane_pkg::NoCF; + + ras_push = 1'b0; + ras_pop = 1'b0; + ras_update = '0; + + // lower most prediction gets precedence + for (int i = CVA6Cfg.INSTR_PER_FETCH - 1; i >= 0; i--) begin + unique case ({ + is_branch[i], is_return[i], is_jump[i], is_jalr[i] + }) + 4'b0000: ; // regular instruction e.g.: no branch + // unconditional jump to register, we need the BTB to resolve this + 4'b0001: begin + ras_pop = 1'b0; + ras_push = 1'b0; + if (CVA6Cfg.BTBEntries != 0 && btb_prediction_shifted[i].valid) begin + predict_address = btb_prediction_shifted[i].target_address; + cf_type[i] = ariane_pkg::JumpR; + end + end + // its an unconditional jump to an immediate + 4'b0010: begin + ras_pop = 1'b0; + ras_push = 1'b0; + taken_rvi_cf[i] = rvi_jump[i]; + taken_rvc_cf[i] = rvc_jump[i]; + cf_type[i] = ariane_pkg::Jump; + end + // return + 4'b0100: begin + // make sure to only alter the RAS if we actually consumed the instruction + ras_pop = ras_predict.valid & instr_queue_consumed[i]; + ras_push = 1'b0; + predict_address = ras_predict.ra; + cf_type[i] = ariane_pkg::Return; + end + // branch prediction + 4'b1000: begin + ras_pop = 1'b0; + ras_push = 1'b0; + // if we have a valid dynamic prediction use it + if (bht_prediction_shifted[i].valid) begin + taken_rvi_cf[i] = rvi_branch[i] & bht_prediction_shifted[i].taken; + taken_rvc_cf[i] = rvc_branch[i] & bht_prediction_shifted[i].taken; + // otherwise default to static prediction + end else begin + // set if immediate is negative - static prediction + taken_rvi_cf[i] = rvi_branch[i] & rvi_imm[i][CVA6Cfg.VLEN-1]; + taken_rvc_cf[i] = rvc_branch[i] & rvc_imm[i][CVA6Cfg.VLEN-1]; + end + if (taken_rvi_cf[i] || taken_rvc_cf[i]) begin + cf_type[i] = ariane_pkg::Branch; + end + end + default: ; + // default: $error("Decoded more than one control flow"); + endcase + // if this instruction, in addition, is a call, save the resulting address + // but only if we actually consumed the address + if (is_call[i]) begin + ras_push = instr_queue_consumed[i]; + ras_update = addr[i] + (rvc_call[i] ? 2 : 4); + end + // calculate the jump target address + if (taken_rvc_cf[i] || taken_rvi_cf[i]) begin + predict_address = addr[i] + (taken_rvc_cf[i] ? rvc_imm[i] : rvi_imm[i]); + end + end + end + // or reduce struct + always_comb begin + bp_valid = 1'b0; + // BP cannot be valid if we have a return instruction and the RAS is not giving a valid address + // Check that we encountered a control flow and that for a return the RAS + // contains a valid prediction. + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) + bp_valid |= ((cf_type[i] != NoCF & cf_type[i] != Return) | ((cf_type[i] == Return) & ras_predict.valid)); + end + assign is_mispredict = resolved_branch_i.valid & resolved_branch_i.is_mispredict; + + // Cache interface + assign icache_dreq_o.req = instr_queue_ready; + assign if_ready = icache_dreq_i.ready & instr_queue_ready; + // We need to flush the cache pipeline if: + // 1. We mispredicted + // 2. Want to flush the whole processor front-end + // 3. Need to replay an instruction because the fetch-fifo was full + assign icache_dreq_o.kill_s1 = is_mispredict | flush_i | replay; + // if we have a valid branch-prediction we need to only kill the last cache request + // also if we killed the first stage we also need to kill the second stage (inclusive flush) + assign icache_dreq_o.kill_s2 = icache_dreq_o.kill_s1 | bp_valid; + + // Update Control Flow Predictions + bht_update_t bht_update; + btb_update_t btb_update; + + // assert on branch, deassert when resolved + logic speculative_q, speculative_d; + assign speculative_d = (speculative_q && !resolved_branch_i.valid || |is_branch || |is_return || |is_jalr) && !flush_i; + assign icache_dreq_o.spec = speculative_d; + + assign bht_update.valid = resolved_branch_i.valid + & (resolved_branch_i.cf_type == ariane_pkg::Branch); + assign bht_update.pc = resolved_branch_i.pc; + assign bht_update.taken = resolved_branch_i.is_taken; + // only update mispredicted branches e.g. no returns from the RAS + assign btb_update.valid = resolved_branch_i.valid + & resolved_branch_i.is_mispredict + & (resolved_branch_i.cf_type == ariane_pkg::JumpR); + assign btb_update.pc = resolved_branch_i.pc; + assign btb_update.target_address = resolved_branch_i.target_address; + + // ------------------- + // Next PC + // ------------------- + // next PC (NPC) can come from (in order of precedence): + // 0. Default assignment/replay instruction + // 1. Branch Predict taken + // 2. Control flow change request (misprediction) + // 3. Return from environment call + // 4. Exception/Interrupt + // 5. Pipeline Flush because of CSR side effects + // Mis-predict handling is a little bit different + // select PC a.k.a PC Gen + always_comb begin : npc_select + automatic logic [CVA6Cfg.VLEN-1:0] fetch_address; + // check whether we come out of reset + // this is a workaround. some tools have issues + // having boot_addr_i in the asynchronous + // reset assignment to npc_q, even though + // boot_addr_i will be assigned a constant + // on the top-level. + if (npc_rst_load_q) begin + npc_d = boot_addr_i; + fetch_address = boot_addr_i; + end else begin + fetch_address = npc_q; + // keep stable by default + npc_d = npc_q; + end + // 0. Branch Prediction + if (bp_valid) begin + fetch_address = predict_address; + npc_d = predict_address; + end + // 1. Default assignment + if (if_ready) begin + npc_d = { + fetch_address[CVA6Cfg.VLEN-1:CVA6Cfg.FETCH_ALIGN_BITS] + 1, {CVA6Cfg.FETCH_ALIGN_BITS{1'b0}} + }; + end + // 2. Replay instruction fetch + if (replay) begin + npc_d = replay_addr; + end + // 3. Control flow change request + if (is_mispredict) begin + npc_d = resolved_branch_i.target_address; + end + // 4. Return from environment call + if (eret_i) begin + npc_d = epc_i; + end + // 5. Exception/Interrupt + if (ex_valid_i) begin + npc_d = trap_vector_base_i; + end + // 6. Pipeline Flush because of CSR side effects + // On a pipeline flush start fetching from the next address + // of the instruction in the commit stage + // we either came here from a flush request of a CSR instruction or AMO, + // so as CSR or AMO instructions do not exist in a compressed form + // we can unconditionally do PC + 4 here + // or if the commit stage is halted, just take the current pc of the + // instruction in the commit stage + // TODO(zarubaf) This adder can at least be merged with the one in the csr_regfile stage + if (set_pc_commit_i) begin + npc_d = pc_commit_i + (halt_i ? '0 : {{CVA6Cfg.VLEN - 3{1'b0}}, 3'b100}); + end + // 7. Debug + // enter debug on a hard-coded base-address + if (CVA6Cfg.DebugEn && set_debug_pc_i) + npc_d = CVA6Cfg.DmBaseAddress[CVA6Cfg.VLEN-1:0] + CVA6Cfg.HaltAddress[CVA6Cfg.VLEN-1:0]; + icache_dreq_o.vaddr = fetch_address; + end + + logic [CVA6Cfg.FETCH_WIDTH-1:0] icache_data; + // re-align the cache line + assign icache_data = icache_dreq_i.data >> {shamt, 4'b0}; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + npc_rst_load_q <= 1'b1; + npc_q <= '0; + speculative_q <= '0; + icache_data_q <= '0; + icache_valid_q <= 1'b0; + icache_vaddr_q <= 'b0; + icache_gpaddr_q <= 'b0; + icache_tinst_q <= 'b0; + icache_gva_q <= 1'b0; + icache_ex_valid_q <= ariane_pkg::FE_NONE; + btb_q <= '0; + bht_q <= '0; + end else begin + npc_rst_load_q <= 1'b0; + npc_q <= npc_d; + speculative_q <= speculative_d; + icache_valid_q <= icache_dreq_i.valid; + if (icache_dreq_i.valid) begin + icache_data_q <= icache_data; + icache_vaddr_q <= icache_dreq_i.vaddr; + if (CVA6Cfg.RVH) begin + icache_gpaddr_q <= icache_dreq_i.ex.tval2[CVA6Cfg.GPLEN-1:0]; + icache_tinst_q <= icache_dreq_i.ex.tinst; + icache_gva_q <= icache_dreq_i.ex.gva; + end else begin + icache_gpaddr_q <= 'b0; + icache_tinst_q <= 'b0; + icache_gva_q <= 1'b0; + end + + // Map the only three exceptions which can occur in the frontend to a two bit enum + if (CVA6Cfg.MmuPresent && icache_dreq_i.ex.cause == riscv::INSTR_GUEST_PAGE_FAULT) begin + icache_ex_valid_q <= ariane_pkg::FE_INSTR_GUEST_PAGE_FAULT; + end else if (CVA6Cfg.MmuPresent && icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin + icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT; + end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin + icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT; + end else begin + icache_ex_valid_q <= ariane_pkg::FE_NONE; + end + // save the uppermost prediction + btb_q <= btb_prediction[CVA6Cfg.INSTR_PER_FETCH-1]; + bht_q <= bht_prediction[CVA6Cfg.INSTR_PER_FETCH-1]; + end + end + end + + if (CVA6Cfg.RASDepth == 0) begin + assign ras_predict = '0; + end else begin : ras_gen + ras #( + .CVA6Cfg(CVA6Cfg), + .ras_t (ras_t), + .DEPTH (CVA6Cfg.RASDepth) + ) i_ras ( + .clk_i, + .rst_ni, + .flush_bp_i(flush_bp_i), + .push_i(ras_push), + .pop_i(ras_pop), + .data_i(ras_update), + .data_o(ras_predict) + ); + end + + //For FPGA, BTB is implemented in read synchronous BRAM + //while for ASIC, BTB is implemented in D flip-flop + //and can be read at the same cycle. + //Same for BHT + assign vpc_btb = (CVA6Cfg.FpgaEn) ? icache_dreq_i.vaddr : icache_vaddr_q; + assign vpc_bht = (CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn && icache_dreq_i.valid) ? icache_dreq_i.vaddr : icache_vaddr_q; + + if (CVA6Cfg.BTBEntries == 0) begin + assign btb_prediction = '0; + end else begin : btb_gen + btb #( + .CVA6Cfg (CVA6Cfg), + .btb_update_t(btb_update_t), + .btb_prediction_t(btb_prediction_t), + .NR_ENTRIES(CVA6Cfg.BTBEntries) + ) i_btb ( + .clk_i, + .rst_ni, + .flush_bp_i (flush_bp_i), + .debug_mode_i, + .vpc_i (vpc_btb), + .btb_update_i (btb_update), + .btb_prediction_o(btb_prediction) + ); + end + + if (CVA6Cfg.BHTEntries == 0) begin + assign bht_prediction = '0; + end else if (CVA6Cfg.BPType == config_pkg::BHT) begin : bht_gen + bht #( + .CVA6Cfg (CVA6Cfg), + .bht_update_t(bht_update_t), + .NR_ENTRIES(CVA6Cfg.BHTEntries) + ) i_bht ( + .clk_i, + .rst_ni, + .flush_bp_i (flush_bp_i), + .debug_mode_i, + .vpc_i (vpc_bht), + .bht_update_i (bht_update), + .bht_prediction_o(bht_prediction) + ); + end else if (CVA6Cfg.BPType == config_pkg::PH_BHT) begin : bht2lvl_gen + bht2lvl #( + .CVA6Cfg (CVA6Cfg), + .bht_update_t(bht_update_t) + ) i_bht ( + .clk_i, + .rst_ni, + .flush_i (flush_bp_i), + .vpc_i (icache_vaddr_q), + .bht_update_i (bht_update), + .bht_prediction_o(bht_prediction) + ); + end + + // we need to inspect up to CVA6Cfg.INSTR_PER_FETCH instructions for branches + // and jumps + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_instr_scan + instr_scan #( + .CVA6Cfg(CVA6Cfg) + ) i_instr_scan ( + .instr_i (instr[i]), + .rvi_return_o(rvi_return[i]), + .rvi_call_o (rvi_call[i]), + .rvi_branch_o(rvi_branch[i]), + .rvi_jalr_o (rvi_jalr[i]), + .rvi_jump_o (rvi_jump[i]), + .rvi_imm_o (rvi_imm[i]), + .rvc_branch_o(rvc_branch[i]), + .rvc_jump_o (rvc_jump[i]), + .rvc_jr_o (rvc_jr[i]), + .rvc_return_o(rvc_return[i]), + .rvc_jalr_o (rvc_jalr[i]), + .rvc_call_o (rvc_call[i]), + .rvc_imm_o (rvc_imm[i]) + ); + end + + instr_queue #( + .CVA6Cfg(CVA6Cfg), + .fetch_entry_t(fetch_entry_t) + ) i_instr_queue ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .instr_i (instr), // from re-aligner + .addr_i (addr), // from re-aligner + .exception_i (icache_ex_valid_q), // from I$ + .exception_addr_i (icache_vaddr_q), + .exception_gpaddr_i (icache_gpaddr_q), + .exception_tinst_i (icache_tinst_q), + .exception_gva_i (icache_gva_q), + .predict_address_i (predict_address), + .cf_type_i (cf_type), + .valid_i (instruction_valid), // from re-aligner + .consumed_o (instr_queue_consumed), + .ready_o (instr_queue_ready), + .replay_o (replay), + .replay_addr_o (replay_addr), + .fetch_entry_o (fetch_entry_o), // to back-end + .fetch_entry_valid_o(fetch_entry_valid_o), // to back-end + .fetch_entry_ready_i(fetch_entry_ready_i) // to back-end + ); + +endmodule diff --git a/flow/designs/src/cva6/core/frontend/instr_queue.sv b/flow/designs/src/cva6/core/frontend/instr_queue.sv new file mode 100644 index 0000000000..28254e4708 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/instr_queue.sv @@ -0,0 +1,565 @@ +// Copyright 2018 - 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 26.10.2018sim:/ariane_tb/dut/i_ariane/i_frontend/icache_ex_valid_q + +// Description: Instruction Queue, separates instruction front-end from processor +// back-end. +// +// This is an optimized instruction queue which supports the handling of +// compressed instructions (16 bit instructions). Internally it is organized as +// FETCH_ENTRY x 32 bit queues which are filled in a consecutive manner. Two pointers +// point into (`idx_is_q` and `idx_ds_q`) the fill port and the read port. The read port +// is designed so that it will easily allow for multiple issue implementation. +// The input supports arbitrary power of two instruction fetch widths. +// +// The queue supports handling of branch prediction and will take care of +// only saving a valid instruction stream. +// +// Furthermore it contains a replay interface in case the instruction queue +// is already full. As instructions are in general easily replayed this should +// increase the efficiency as I$ misses are potentially hidden. This stands in +// contrast to pessimistic actions (early stalling) or credit based approaches. +// Credit based systems might be difficult to implement with the current system +// as we do not exactly know how much space we are going to need in the fifos +// as each instruction can take either one or two slots. +// +// So the consumed/valid interface degenerates to a `information` interface. If the +// upstream circuits keeps pushing the queue will discard the information +// and start replaying from the point were it could last manage to accept instructions. +// +// The instruction front-end will stop issuing instructions as soon as the +// fifo is full. This will gate the logic if the processor is e.g.: halted +// +// TODO(zarubaf): The instruction queues can be reduced to 16 bit. Potentially +// the replay mechanism gets more complicated as it can be that a 32 bit instruction +// can not be pushed at once. + +module instr_queue + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fetch_entry_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Instruction - instr_realign + input logic [CVA6Cfg.INSTR_PER_FETCH-1:0][31:0] instr_i, + // Instruction address - instr_realign + input logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] addr_i, + // Instruction is valid - instr_realign + input logic [CVA6Cfg.INSTR_PER_FETCH-1:0] valid_i, + // Handshake’s ready with CACHE - CACHE + output logic ready_o, + // Indicates instructions consummed, or popped by ID_STAGE - FRONTEND + output logic [CVA6Cfg.INSTR_PER_FETCH-1:0] consumed_o, + // Exception (which is page-table fault) - CACHE + input ariane_pkg::frontend_exception_t exception_i, + // Exception address - CACHE + input logic [CVA6Cfg.VLEN-1:0] exception_addr_i, + input logic [CVA6Cfg.GPLEN-1:0] exception_gpaddr_i, + input logic [31:0] exception_tinst_i, + input logic exception_gva_i, + // Branch predict - FRONTEND + input logic [CVA6Cfg.VLEN-1:0] predict_address_i, + // Instruction predict address - FRONTEND + input ariane_pkg::cf_t [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_type_i, + // Replay instruction because one of the FIFO was full - FRONTEND + output logic replay_o, + // Address at which to replay the fetch - FRONTEND + output logic [CVA6Cfg.VLEN-1:0] replay_addr_o, + // Handshake’s data with ID_STAGE - ID_STAGE + output fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_o, + // Handshake’s valid with ID_STAGE - ID_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_o, + // Handshake’s ready with ID_STAGE - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_i +); + + // Calculate next index based on whether superscalar is enabled or not. + localparam NID = CVA6Cfg.SuperscalarEn ? 1 : 0; + + typedef struct packed { + logic [31:0] instr; // instruction word + ariane_pkg::cf_t cf; // branch was taken + ariane_pkg::frontend_exception_t ex; // exception happened + logic [CVA6Cfg.VLEN-1:0] ex_vaddr; // lower VLEN bits of tval for exception + logic [CVA6Cfg.GPLEN-1:0] ex_gpaddr; // lower GPLEN bits of tval2 for exception + logic [31:0] ex_tinst; // tinst of exception + logic ex_gva; + } instr_data_t; + + logic [CVA6Cfg.LOG2_INSTR_PER_FETCH-1:0] branch_index; + // instruction queues + instr_data_t [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_data_in, instr_data_out; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] push_instr, push_instr_fifo; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] pop_instr; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_queue_full; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_queue_empty; + logic instr_overflow; + // address queue + logic [ CVA6Cfg.VLEN-1:0] address_out; + logic pop_address; + logic push_address; + logic full_address; + logic address_overflow; + // input stream counter + logic [CVA6Cfg.LOG2_INSTR_PER_FETCH-1:0] idx_is_d, idx_is_q; + + // Registers + // output FIFO select, one-hot + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] idx_ds_d, idx_ds_q; + // rotated by N + logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.INSTR_PER_FETCH-1:0] idx_ds; + + logic [CVA6Cfg.VLEN-1:0] pc_d, pc_q; // current PC + logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.VLEN-1:0] pc_j; + logic reset_address_d, reset_address_q; // we need to re-set the address because of a flush + + logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_is_cf, fetch_entry_fire; + + logic [CVA6Cfg.INSTR_PER_FETCH*2-2:0] branch_mask_extended; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] branch_mask; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] taken; + // shift amount, e.g.: instructions we want to retire + logic [CVA6Cfg.LOG2_INSTR_PER_FETCH:0] popcount; + logic [CVA6Cfg.LOG2_INSTR_PER_FETCH-1:0] shamt; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] valid; + logic [CVA6Cfg.INSTR_PER_FETCH*2-1:0] consumed_extended; + // FIFO mask + logic [CVA6Cfg.INSTR_PER_FETCH*2-1:0] fifo_pos_extended; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] fifo_pos; + logic [CVA6Cfg.INSTR_PER_FETCH*2-1:0][31:0] instr; + ariane_pkg::cf_t [CVA6Cfg.INSTR_PER_FETCH*2-1:0] cf; + // replay interface + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_overflow_fifo; + + assign ready_o = ~(|instr_queue_full) & ~full_address; + + if (CVA6Cfg.RVC) begin : gen_multiple_instr_per_fetch_with_C + + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_unpack_taken + assign taken[i] = cf_type_i[i] != ariane_pkg::NoCF; + end + + // calculate a branch mask, e.g.: get the first taken branch + lzc #( + .WIDTH(CVA6Cfg.INSTR_PER_FETCH), + .MODE (0) // count trailing zeros + ) i_lzc_branch_index ( + .in_i (taken), // we want to count trailing zeros + .cnt_o (branch_index), // first branch on branch_index + .empty_o() + ); + + + // the first index is for sure valid + // for example (64 bit fetch): + // taken mask: 0 1 1 0 + // leading zero count = 1 + // 0 0 0 1, 1 1 1 << 1 = 0 0 1 1, 1 1 0 + // take the upper 4 bits: 0 0 1 1 + assign branch_mask_extended = {{{CVA6Cfg.INSTR_PER_FETCH-1}{1'b0}}, {{CVA6Cfg.INSTR_PER_FETCH}{1'b1}}} << branch_index; + assign branch_mask = branch_mask_extended[CVA6Cfg.INSTR_PER_FETCH * 2 - 2:CVA6Cfg.INSTR_PER_FETCH - 1]; + + // mask with taken branches to get the actual amount of instructions we want to push + assign valid = valid_i & branch_mask; + // rotate right again + assign consumed_extended = {push_instr_fifo, push_instr_fifo} >> idx_is_q; + assign consumed_o = consumed_extended[CVA6Cfg.INSTR_PER_FETCH-1:0]; + // count the numbers of valid instructions we've pushed from this package + popcount #( + .INPUT_WIDTH(CVA6Cfg.INSTR_PER_FETCH) + ) i_popcount ( + .data_i (push_instr_fifo), + .popcount_o(popcount) + ); + assign shamt = popcount[$bits(shamt)-1:0]; + + // save the shift amount for next cycle + assign idx_is_d = idx_is_q + shamt; + + // ---------------------- + // Input interface + // ---------------------- + // rotate left by the current position + assign fifo_pos_extended = {valid, valid} << idx_is_q; + // we just care about the upper bits + assign fifo_pos = fifo_pos_extended[CVA6Cfg.INSTR_PER_FETCH*2-1:CVA6Cfg.INSTR_PER_FETCH]; + // the fifo_position signal can directly be used to guide the push signal of each FIFO + // make sure it is not full + assign push_instr = fifo_pos & ~instr_queue_full; + + // duplicate the entries for easier selection e.g.: 3 2 1 0 3 2 1 0 + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_duplicate_instr_input + assign instr[i] = instr_i[i]; + assign instr[i+CVA6Cfg.INSTR_PER_FETCH] = instr_i[i]; + assign cf[i] = cf_type_i[i]; + assign cf[i+CVA6Cfg.INSTR_PER_FETCH] = cf_type_i[i]; + end + + // shift the inputs + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_fifo_input_select + /* verilator lint_off WIDTH */ + assign instr_data_in[i].instr = instr[CVA6Cfg.INSTR_PER_FETCH+i-idx_is_q]; + assign instr_data_in[i].cf = cf[CVA6Cfg.INSTR_PER_FETCH+i-idx_is_q]; + assign instr_data_in[i].ex = exception_i; // exceptions hold for the whole fetch packet + assign instr_data_in[i].ex_vaddr = exception_addr_i; + if (CVA6Cfg.RVH) begin : gen_hyp_ex_with_C + assign instr_data_in[i].ex_gpaddr = exception_gpaddr_i; + assign instr_data_in[i].ex_tinst = exception_tinst_i; + assign instr_data_in[i].ex_gva = exception_gva_i; + end else begin : gen_no_hyp_ex_with_C + assign instr_data_in[i].ex_gpaddr = '0; + assign instr_data_in[i].ex_tinst = '0; + assign instr_data_in[i].ex_gva = 1'b0; + end + /* verilator lint_on WIDTH */ + end + end else begin : gen_multiple_instr_per_fetch_without_C + + assign taken = '0; + assign branch_index = '0; + assign branch_mask_extended = '0; + assign branch_mask = '0; + assign consumed_extended = '0; + assign fifo_pos_extended = '0; + assign fifo_pos = '0; + assign instr = '0; + assign popcount = '0; + assign shamt = '0; + assign valid = '0; + + + assign consumed_o = push_instr_fifo[0]; + // ---------------------- + // Input interface + // ---------------------- + assign push_instr = valid_i & ~instr_queue_full; + + /* verilator lint_off WIDTH */ + assign instr_data_in[0].instr = instr_i[0]; + assign instr_data_in[0].cf = cf_type_i[0]; + assign instr_data_in[0].ex = exception_i; // exceptions hold for the whole fetch packet + assign instr_data_in[0].ex_vaddr = exception_addr_i; + if (CVA6Cfg.RVH) begin : gen_hyp_ex_without_C + assign instr_data_in[0].ex_gpaddr = exception_gpaddr_i; + assign instr_data_in[0].ex_tinst = exception_tinst_i; + assign instr_data_in[0].ex_gva = exception_gva_i; + end else begin : gen_no_hyp_ex_without_C + assign instr_data_in[0].ex_gpaddr = '0; + assign instr_data_in[0].ex_tinst = '0; + assign instr_data_in[0].ex_gva = 1'b0; + end + /* verilator lint_on WIDTH */ + end + + // ---------------------- + // Replay Logic + // ---------------------- + // We need to replay a instruction fetch iff: + // 1. One of the instruction data FIFOs was full and we needed it + // (e.g.: we pushed and it was full) + // 2. The address/branch predict FIFO was full + // if one of the FIFOs was full we need to replay the faulting instruction + if (CVA6Cfg.RVC == 1'b1) begin : gen_instr_overflow_fifo_with_C + assign instr_overflow_fifo = instr_queue_full & fifo_pos; + end else begin : gen_instr_overflow_fifo_without_C + assign instr_overflow_fifo = instr_queue_full & valid_i; + end + assign instr_overflow = |instr_overflow_fifo; // at least one instruction overflowed + assign address_overflow = full_address & push_address; + assign replay_o = instr_overflow | address_overflow; + + if (CVA6Cfg.RVC) begin : gen_replay_addr_o_with_c + // select the address, in the case of an address fifo overflow just + // use the base of this package + // if we successfully pushed some instructions we can output the next instruction + // which we didn't manage to push + assign replay_addr_o = (address_overflow) ? addr_i[0] : addr_i[shamt]; + end else begin : gen_replay_addr_o_without_C + assign replay_addr_o = addr_i[0]; + end + + // ---------------------- + // Downstream interface + // ---------------------- + // as long as there is at least one queue which can take the value we have a valid instruction + assign fetch_entry_valid_o[0] = ~(&instr_queue_empty); + if (CVA6Cfg.SuperscalarEn) begin : gen_fetch_entry_valid_1 + // TODO Maybe this additional fetch_entry_is_cf check is useless as issue-stage already performs it? + assign fetch_entry_valid_o[NID] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf); + end + + assign idx_ds[0] = idx_ds_q; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (CVA6Cfg.INSTR_PER_FETCH > 1) begin + assign idx_ds[i+1] = { + idx_ds[i][CVA6Cfg.INSTR_PER_FETCH-2:0], idx_ds[i][CVA6Cfg.INSTR_PER_FETCH-1] + }; + end else begin + assign idx_ds[i+1] = idx_ds[i]; + end + end + + if (CVA6Cfg.RVC) begin : gen_downstream_itf_with_c + always_comb begin + idx_ds_d = idx_ds_q; + + pop_instr = '0; + // assemble fetch entry + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + fetch_entry_o[i].instruction = '0; + fetch_entry_o[i].address = pc_j[i]; + fetch_entry_o[i].ex.valid = 1'b0; + fetch_entry_o[i].ex.cause = '0; + + fetch_entry_o[i].ex.tval = '0; + fetch_entry_o[i].ex.tval2 = '0; + fetch_entry_o[i].ex.gva = 1'b0; + fetch_entry_o[i].ex.tinst = '0; + fetch_entry_o[i].branch_predict.predict_address = address_out; + fetch_entry_o[i].branch_predict.cf = ariane_pkg::NoCF; + end + + // output mux select + for (int unsigned i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + // TODO handle fetch_entry_o[1] if superscalar + if (idx_ds[0][i]) begin + if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin + fetch_entry_o[0].ex.cause = riscv::INSTR_ACCESS_FAULT; + end else if (CVA6Cfg.RVH && instr_data_out[i].ex == ariane_pkg::FE_INSTR_GUEST_PAGE_FAULT) begin + fetch_entry_o[0].ex.cause = riscv::INSTR_GUEST_PAGE_FAULT; + end else begin + fetch_entry_o[0].ex.cause = riscv::INSTR_PAGE_FAULT; + end + fetch_entry_o[0].instruction = instr_data_out[i].instr; + fetch_entry_o[0].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; + if (CVA6Cfg.TvalEn) + fetch_entry_o[0].ex.tval = { + {(CVA6Cfg.XLEN - CVA6Cfg.VLEN) {1'b0}}, instr_data_out[i].ex_vaddr + }; + if (CVA6Cfg.RVH) begin + fetch_entry_o[0].ex.tval2 = instr_data_out[i].ex_gpaddr; + fetch_entry_o[0].ex.tinst = instr_data_out[i].ex_tinst; + fetch_entry_o[0].ex.gva = instr_data_out[i].ex_gva; + end + fetch_entry_o[0].branch_predict.cf = instr_data_out[i].cf; + pop_instr[i] = fetch_entry_fire[0]; + end + + if (CVA6Cfg.SuperscalarEn) begin + if (idx_ds[1][i]) begin + if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin + fetch_entry_o[NID].ex.cause = riscv::INSTR_ACCESS_FAULT; + end else begin + fetch_entry_o[NID].ex.cause = riscv::INSTR_PAGE_FAULT; + end + fetch_entry_o[NID].instruction = instr_data_out[i].instr; + fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; + fetch_entry_o[NID].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; + fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf; + // Cannot output two CF the same cycle. + pop_instr[i] = fetch_entry_fire[NID]; + end + end + end + // rotate the pointer left + if (fetch_entry_fire[0]) begin + if (CVA6Cfg.SuperscalarEn) begin + idx_ds_d = fetch_entry_fire[NID] ? idx_ds[2] : idx_ds[1]; + end else begin + idx_ds_d = idx_ds[1]; + end + end + end + end else begin : gen_downstream_itf_without_c + always_comb begin + idx_ds_d = '0; + idx_is_d = '0; + fetch_entry_o[0].instruction = instr_data_out[0].instr; + fetch_entry_o[0].address = pc_q; + + fetch_entry_o[0].ex.valid = instr_data_out[0].ex != ariane_pkg::FE_NONE; + if (instr_data_out[0].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin + fetch_entry_o[0].ex.cause = riscv::INSTR_ACCESS_FAULT; + end else begin + fetch_entry_o[0].ex.cause = riscv::INSTR_PAGE_FAULT; + end + if (CVA6Cfg.TvalEn) + fetch_entry_o[0].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[0].ex_vaddr}; + else fetch_entry_o[0].ex.tval = '0; + if (CVA6Cfg.RVH) begin + fetch_entry_o[0].ex.tval2 = instr_data_out[0].ex_gpaddr; + fetch_entry_o[0].ex.tinst = instr_data_out[0].ex_tinst; + fetch_entry_o[0].ex.gva = instr_data_out[0].ex_gva; + end else begin + fetch_entry_o[0].ex.tval2 = '0; + fetch_entry_o[0].ex.tinst = '0; + fetch_entry_o[0].ex.gva = 1'b0; + end + + fetch_entry_o[0].branch_predict.predict_address = address_out; + fetch_entry_o[0].branch_predict.cf = instr_data_out[0].cf; + + pop_instr[0] = fetch_entry_valid_o[0] & fetch_entry_ready_i[0]; + end + end + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign fetch_entry_is_cf[i] = fetch_entry_o[i].branch_predict.cf != ariane_pkg::NoCF; + assign fetch_entry_fire[i] = fetch_entry_valid_o[i] & fetch_entry_ready_i[i]; + end + + assign pop_address = |(fetch_entry_is_cf & fetch_entry_fire); + + // ---------------------- + // Calculate (Next) PC + // ---------------------- + assign pc_j[0] = pc_q; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign pc_j[i+1] = fetch_entry_is_cf[i] ? address_out : ( + pc_j[i] + ((fetch_entry_o[i].instruction[1:0] != 2'b11) ? 'd2 : 'd4) + ); + end + + always_comb begin + pc_d = pc_q; + reset_address_d = flush_i ? 1'b1 : reset_address_q; + + if (fetch_entry_fire[0]) begin + pc_d = pc_j[1]; + if (CVA6Cfg.SuperscalarEn) begin + if (fetch_entry_fire[NID]) begin + pc_d = pc_j[2]; + end + end + end + + // we previously flushed so we need to reset the address + if (valid_i[0] && reset_address_q) begin + // this is the base of the first instruction + pc_d = addr_i[0]; + reset_address_d = 1'b0; + end + end + + // FIFOs + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_instr_fifo + // Make sure we don't save any instructions if we couldn't save the address + assign push_instr_fifo[i] = push_instr[i] & ~address_overflow; + cva6_fifo_v3 #( + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), + .DEPTH(ariane_pkg::FETCH_FIFO_DEPTH), + .dtype(instr_data_t), + .FPGA_EN(CVA6Cfg.FpgaEn) + ) i_fifo_instr_data ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .testmode_i(1'b0), + .full_o (instr_queue_full[i]), + .empty_o (instr_queue_empty[i]), + .usage_o (), + .data_i (instr_data_in[i]), + .push_i (push_instr_fifo[i]), + .data_o (instr_data_out[i]), + .pop_i (pop_instr[i]) + ); + end + // or reduce and check whether we are retiring a taken branch (might be that the corresponding) + // fifo is full. + always_comb begin + push_address = 1'b0; + // check if we are pushing a ctrl flow change, if so save the address + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + push_address |= push_instr[i] & (instr_data_in[i].cf != ariane_pkg::NoCF); + end + end + + cva6_fifo_v3 #( + .FPGA_ALTERA(CVA6Cfg.FpgaAlteraEn), + .DEPTH (ariane_pkg::FETCH_ADDR_FIFO_DEPTH), + .DATA_WIDTH (CVA6Cfg.VLEN), + .FPGA_EN (CVA6Cfg.FpgaEn) + ) i_fifo_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .testmode_i(1'b0), + .full_o (full_address), + .empty_o (), + .usage_o (), + .data_i (predict_address_i), + .push_i (push_address & ~full_address), + .data_o (address_out), + .pop_i (pop_address) + ); + + unread i_unread_branch_mask (.d_i(|branch_mask_extended)); + unread i_unread_fifo_pos (.d_i(|fifo_pos_extended)); // we don't care about the lower signals + + if (CVA6Cfg.RVC) begin : gen_pc_q_with_c + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + idx_ds_q <= 'b1; + idx_is_q <= '0; + pc_q <= '0; + reset_address_q <= 1'b1; + end else begin + pc_q <= pc_d; + reset_address_q <= reset_address_d; + if (flush_i) begin + // one-hot encoded + idx_ds_q <= 'b1; + // binary encoded + idx_is_q <= '0; + reset_address_q <= 1'b1; + end else begin + idx_ds_q <= idx_ds_d; + idx_is_q <= idx_is_d; + end + end + end + end else begin : gen_pc_q_without_C + assign idx_ds_q = '0; + assign idx_is_q = '0; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pc_q <= '0; + reset_address_q <= 1'b1; + end else begin + pc_q <= pc_d; + reset_address_q <= reset_address_d; + if (flush_i) begin + reset_address_q <= 1'b1; + end + end + end + end + + // pragma translate_off + replay_address_fifo : + assert property (@(posedge clk_i) disable iff (!rst_ni) replay_o |-> !i_fifo_address.push_i) + else $fatal(1, "[instr_queue] Pushing address although replay asserted"); + + output_select_onehot : + assert property (@(posedge clk_i) $onehot0(idx_ds_q)) + else begin + $error("Output select should be one-hot encoded"); + $stop(); + end + // pragma translate_on +endmodule diff --git a/flow/designs/src/cva6/core/frontend/instr_scan.sv b/flow/designs/src/cva6/core/frontend/instr_scan.sv new file mode 100644 index 0000000000..69e45ff69e --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/instr_scan.sv @@ -0,0 +1,110 @@ +// Copyright 2018 - 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 2.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-2.0. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// Author: Florian Zaruba, ETH Zurich +// Date: 08.02.2018 +// Migrated: Luis Vitorio Cargnini, IEEE +// Date: 09.06.2018 + +// ------------------------------ +// Instruction Scanner +// ------------------------------ +module instr_scan #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Instruction to be predecoded - instr_realign + input logic [31:0] instr_i, + // Return instruction - FRONTEND + output logic rvi_return_o, + // JAL instruction - FRONTEND + output logic rvi_call_o, + // Branch instruction - FRONTEND + output logic rvi_branch_o, + // JALR instruction - FRONTEND + output logic rvi_jalr_o, + // Unconditional jump instruction - FRONTEND + output logic rvi_jump_o, + // Instruction immediate - FRONTEND + output logic [CVA6Cfg.VLEN-1:0] rvi_imm_o, + // Branch compressed instruction - FRONTEND + output logic rvc_branch_o, + // Unconditional jump compressed instruction - FRONTEND + output logic rvc_jump_o, + // JR compressed instruction - FRONTEND + output logic rvc_jr_o, + // Return compressed instruction - FRONTEND + output logic rvc_return_o, + // JALR compressed instruction - FRONTEND + output logic rvc_jalr_o, + // JAL compressed instruction - FRONTEND + output logic rvc_call_o, + // Instruction compressed immediate - FRONTEND + output logic [CVA6Cfg.VLEN-1:0] rvc_imm_o +); + + function automatic logic [CVA6Cfg.VLEN-1:0] uj_imm(logic [31:0] instruction_i); + return { + {44 + CVA6Cfg.VLEN - 64{instruction_i[31]}}, + instruction_i[19:12], + instruction_i[20], + instruction_i[30:21], + 1'b0 + }; + endfunction + + function automatic logic [CVA6Cfg.VLEN-1:0] sb_imm(logic [31:0] instruction_i); + return { + {51 + CVA6Cfg.VLEN - 64{instruction_i[31]}}, + instruction_i[31], + instruction_i[7], + instruction_i[30:25], + instruction_i[11:8], + 1'b0 + }; + endfunction + + logic rv32_rvc_jal; + assign rv32_rvc_jal = (CVA6Cfg.XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & (instr_i[1:0] == riscv::OpcodeC1)); + + logic is_xret; + assign is_xret = logic'(instr_i[31:30] == 2'b00) & logic'(instr_i[28:0] == 29'b10000001000000000000001110011); + + // check that rs1 is either x1 or x5 and that rd is not rs1 + assign rvi_return_o = rvi_jalr_o & ((instr_i[19:15] == 5'd1) | instr_i[19:15] == 5'd5) + & (instr_i[19:15] != instr_i[11:7]); + // Opocde is JAL[R] and destination register is either x1 or x5 + assign rvi_call_o = (rvi_jalr_o | rvi_jump_o) & ((instr_i[11:7] == 5'd1) | instr_i[11:7] == 5'd5); + // differentiates between JAL and BRANCH opcode, JALR comes from BHT + assign rvi_imm_o = is_xret ? '0 : (instr_i[3]) ? uj_imm(instr_i) : sb_imm(instr_i); + assign rvi_branch_o = (instr_i[6:0] == riscv::OpcodeBranch); + assign rvi_jalr_o = (instr_i[6:0] == riscv::OpcodeJalr); + assign rvi_jump_o = logic'(instr_i[6:0] == riscv::OpcodeJal) | is_xret; + + // opcode JAL + assign rvc_jump_o = ((instr_i[15:13] == riscv::OpcodeC1J) & (instr_i[1:0] == riscv::OpcodeC1)) | rv32_rvc_jal; + + // always links to register 0 + logic is_jal_r; + assign is_jal_r = (instr_i[15:13] == riscv::OpcodeC2JalrMvAdd) + & (instr_i[6:2] == 5'b00000) + & (instr_i[1:0] == riscv::OpcodeC2); + assign rvc_jr_o = is_jal_r & ~instr_i[12]; + // always links to register 1 e.g.: it is a jump + assign rvc_jalr_o = is_jal_r & instr_i[12]; + assign rvc_call_o = rvc_jalr_o | rv32_rvc_jal; + + assign rvc_branch_o = ((instr_i[15:13] == riscv::OpcodeC1Beqz) | (instr_i[15:13] == riscv::OpcodeC1Bnez)) + & (instr_i[1:0] == riscv::OpcodeC1); + // check that rs1 is x1 or x5 + assign rvc_return_o = ((instr_i[11:7] == 5'd1) | (instr_i[11:7] == 5'd5)) & rvc_jr_o; + + // differentiates between JAL and BRANCH opcode, JALR comes from BHT + assign rvc_imm_o = (instr_i[14]) ? {{56+CVA6Cfg.VLEN-64{instr_i[12]}}, instr_i[6:5], instr_i[2], instr_i[11:10], instr_i[4:3], 1'b0} + : {{53+CVA6Cfg.VLEN-64{instr_i[12]}}, instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], 1'b0}; +endmodule diff --git a/flow/designs/src/cva6/core/frontend/ras.sv b/flow/designs/src/cva6/core/frontend/ras.sv new file mode 100644 index 0000000000..422a829fa4 --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/ras.sv @@ -0,0 +1,79 @@ +//Copyright (C) 2018 to present, +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 2.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-2.0. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.02.2018 +// Migrated: Luis Vitorio Cargnini, IEEE +// Date: 09.06.2018 + +// return address stack +module ras #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type ras_t = logic, + parameter int unsigned DEPTH = 2 +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Branch prediction flush request - zero + input logic flush_bp_i, + // Push address in RAS - FRONTEND + input logic push_i, + // Pop address from RAS - FRONTEND + input logic pop_i, + // Data to be pushed - FRONTEND + input logic [CVA6Cfg.VLEN-1:0] data_i, + // Popped data - FRONTEND + output ras_t data_o +); + + ras_t [DEPTH-1:0] stack_d, stack_q; + + assign data_o = stack_q[0]; + + always_comb begin + stack_d = stack_q; + + // push on the stack + if (push_i) begin + stack_d[0].ra = data_i; + // mark the new return address as valid + stack_d[0].valid = 1'b1; + stack_d[DEPTH-1:1] = stack_q[DEPTH-2:0]; + end + + if (pop_i) begin + stack_d[DEPTH-2:0] = stack_q[DEPTH-1:1]; + // we popped the value so invalidate the end of the stack + stack_d[DEPTH-1].valid = 1'b0; + stack_d[DEPTH-1].ra = 'b0; + end + // leave everything untouched and just push the latest value to the + // top of the stack + if (pop_i && push_i) begin + stack_d = stack_q; + stack_d[0].ra = data_i; + stack_d[0].valid = 1'b1; + end + + if (flush_bp_i) begin + stack_d = '0; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + stack_q <= '0; + end else begin + stack_q <= stack_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/id_stage.sv b/flow/designs/src/cva6/core/id_stage.sv new file mode 100644 index 0000000000..d37554db4f --- /dev/null +++ b/flow/designs/src/cva6/core/id_stage.sv @@ -0,0 +1,451 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 15.04.2017 +// Description: Instruction decode, contains the logic for decode, +// issue and read operands. + +module id_stage #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type fetch_entry_t = logic, + parameter type jvt_t = logic, + parameter type irq_ctrl_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type interrupts_t = logic, + parameter interrupts_t INTERRUPTS = '0, + parameter type x_compressed_req_t = logic, + parameter type x_compressed_resp_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Debug (async) request - SUBSYSTEM + input logic debug_req_i, + // Handshake's data between fetch and decode - FRONTEND + input fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_i, + // Handshake's valid between fetch and decode - FRONTEND + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_i, + // Handshake's ready between fetch and decode - FRONTEND + output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_o, + // Handshake's data between decode and issue - ISSUE + output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_entry_o, + output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_entry_o_prev, + // Instruction value - ISSUE + output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_o, + // Handshake's valid between decode and issue - ISSUE + output logic [CVA6Cfg.NrIssuePorts-1:0] issue_entry_valid_o, + // Report if instruction is a control flow instruction - ISSUE + output logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_o, + // Handshake's acknowlege between decode and issue - ISSUE + input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack_i, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0] rvfi_is_compressed_o, + // Current privilege level - CSR_REGFILE + input riscv::priv_lvl_t priv_lvl_i, + // Current virtualization mode - CSR_REGFILE + input logic v_i, + // Floating point extension status - CSR_REGFILE + input riscv::xs_t fs_i, + // Floating point extension virtual status - CSR_REGFILE + input riscv::xs_t vfs_i, + // Floating point dynamic rounding mode - CSR_REGFILE + input logic [2:0] frm_i, + // Vector extension status - CSR_REGFILE + input riscv::xs_t vs_i, + // Level sensitive (async) interrupts - SUBSYSTEM + input logic [1:0] irq_i, + // Interrupt control status - CSR_REGFILE + input irq_ctrl_t irq_ctrl_i, + // Is current mode debug ? - CSR_REGFILE + input logic debug_mode_i, + // Trap virtual memory - CSR_REGFILE + input logic tvm_i, + // Timeout wait - CSR_REGFILE + input logic tw_i, + // Virtual timeout wait - CSR_REGFILE + input logic vtw_i, + // Trap sret - CSR_REGFILE + input logic tsr_i, + // Hypervisor user mode - CSR_REGFILE + input logic hu_i, + // CVXIF Compressed interface + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + input logic compressed_ready_i, + //JVT + input jvt_t jvt_i, + input x_compressed_resp_t compressed_resp_i, + output logic compressed_valid_o, + output x_compressed_req_t compressed_req_o, + // Data cache request ouput - CACHE + input dcache_req_o_t dcache_req_ports_i, + // Data cache request input - CACHE + output dcache_req_i_t dcache_req_ports_o +); + // ID/ISSUE register stage + typedef struct packed { + logic valid; + scoreboard_entry_t sbe; + logic [31:0] orig_instr; + logic is_ctrl_flow; + } issue_struct_t; + issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q; + // stall required for ZCMP ZCMT CVXIF + logic [CVA6Cfg.NrIssuePorts-1:0] stall_instr_fetch; + + logic [CVA6Cfg.NrIssuePorts-1:0] is_control_flow_instr; + scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instruction; + logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instruction_valid; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr; + + // Compressed decoder signals + logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_rvc; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_rvc; + logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_rvc; + logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr; + logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr; + + // CVXIF compressed interface driver signals + // Inputs + logic is_illegal_cvxif_i; + logic [ 31:0] instruction_cvxif_i; + logic is_compressed_cvxif_i; + logic stall_macro_deco; + // Outputs + logic is_illegal_cvxif_o; + logic [ 31:0] instruction_cvxif_o; + logic is_compressed_cvxif_o; + + // ZCMP decoder signals + logic is_illegal_zcmp; + logic [ 31:0] instruction_zcmp; + logic is_compressed_zcmp; + logic stall_macro_deco_zcmp; + logic is_last_macro_instr; + logic is_double_rd_macro_instr; + + // ZCMT decoder signals + logic is_illegal_zcmt; + logic [ 31:0] instruction_zcmt; + logic is_compressed_zcmt; + logic stall_macro_deco_zcmt; + logic [ CVA6Cfg.XLEN-1:0] jump_address; + + // Decoder signals + logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_deco; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_deco; + logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_deco; + + + if (CVA6Cfg.RVC) begin + // --------------------------------------------------------- + // 1. Check if they are compressed and expand in case they are + // --------------------------------------------------------- + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + compressed_decoder #( + .CVA6Cfg(CVA6Cfg) + ) compressed_decoder_i ( + .instr_i (fetch_entry_i[i].instruction), + .instr_o (instruction_rvc[i]), + .illegal_instr_o (is_illegal_rvc[i]), + .is_compressed_o (is_compressed_rvc[i]), + .is_macro_instr_o(is_macro_instr[i]), + .is_zcmt_instr_o (is_zcmt_instr[i]) + ); + end + + if (CVA6Cfg.SuperscalarEn) begin + assign stall_instr_fetch[1] = is_illegal_rvc[1] || is_macro_instr[1] || is_zcmt_instr[1]; + end + + if (CVA6Cfg.RVZCMP) begin + macro_decoder #( + .CVA6Cfg(CVA6Cfg) + ) macro_decoder_i ( + .instr_i (instruction_rvc[0]), + .is_macro_instr_i (is_macro_instr[0]), + .clk_i (clk_i), + .rst_ni (rst_ni), + .instr_o (instruction_zcmp), + .illegal_instr_i (is_illegal_rvc[0]), + .is_compressed_i (is_compressed_rvc[0]), + .issue_ack_i (issue_instr_ack_i[0]), + .illegal_instr_o (is_illegal_zcmp), + .is_compressed_o (is_compressed_zcmp), + .fetch_stall_o (stall_macro_deco_zcmp), + .is_last_macro_instr_o (is_last_macro_instr), + .is_double_rd_macro_instr_o(is_double_rd_macro_instr) + ); + end else begin + assign instruction_zcmp = instruction_rvc; + assign is_illegal_zcmp = is_illegal_rvc; + assign is_compressed_zcmp = is_compressed_rvc; + assign stall_macro_deco_zcmp = '0; + assign is_last_macro_instr = '0; + assign is_double_rd_macro_instr = '0; + end + + if (CVA6Cfg.RVZCMT) begin + zcmt_decoder #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .jvt_t(jvt_t), + .branchpredict_sbe_t(branchpredict_sbe_t) + ) zcmt_decoder_i ( + .instr_i (instruction_rvc[0]), + .pc_i (fetch_entry_i[0].address), + .is_zcmt_instr_i(is_zcmt_instr[0]), + .clk_i (clk_i), + .rst_ni (rst_ni), + .instr_o (instruction_zcmt), + .illegal_instr_i(is_illegal_rvc[0]), + .is_compressed_i(is_compressed_rvc[0]), + .illegal_instr_o(is_illegal_zcmt), + .is_compressed_o(is_compressed_zcmt), + .fetch_stall_o (stall_macro_deco_zcmt), + .jvt_i (jvt_i), + .req_port_i (dcache_req_ports_i), + .req_port_o (dcache_req_ports_o), + .jump_address_o (jump_address) + ); + end else begin + assign instruction_zcmt = instruction_rvc; + assign is_illegal_zcmt = is_illegal_rvc; + assign is_compressed_zcmt = is_compressed_rvc; + assign stall_macro_deco_zcmt = '0; + assign jump_address = '0; + end + + if (CVA6Cfg.RVZCMT) begin + assign instruction_cvxif_i = is_zcmt_instr[0] ? instruction_zcmt : instruction_zcmp; + assign is_illegal_cvxif_i = is_zcmt_instr[0] ? is_illegal_zcmt : is_illegal_zcmp; + assign is_compressed_cvxif_i = is_zcmt_instr[0] ? is_compressed_zcmt : is_compressed_zcmp; + assign stall_macro_deco = is_zcmt_instr[0] ? stall_macro_deco_zcmt : stall_macro_deco_zcmp; + end else begin // Do not instantiate the mux which is not optimized cross-bondaries + assign instruction_cvxif_i = instruction_zcmp; + assign is_illegal_cvxif_i = is_illegal_zcmp; + assign is_compressed_cvxif_i = is_compressed_zcmp; + assign stall_macro_deco = stall_macro_deco_zcmp; + end + + if (CVA6Cfg.CvxifEn) begin + cvxif_compressed_if_driver #( + .CVA6Cfg(CVA6Cfg), + .x_compressed_req_t(x_compressed_req_t), + .x_compressed_resp_t(x_compressed_resp_t) + ) i_cvxif_compressed_if_driver_i ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .hart_id_i (hart_id_i), + .is_compressed_i (is_compressed_cvxif_i), + .is_illegal_i (is_illegal_cvxif_i), + .instruction_i (instruction_cvxif_i), + .is_compressed_o (is_compressed_cvxif_o), + .is_illegal_o (is_illegal_cvxif_o), + .instruction_o (instruction_cvxif_o), + .stall_i (stall_macro_deco), + .stall_o (stall_instr_fetch[0]), + .compressed_ready_i(compressed_ready_i), + .compressed_resp_i (compressed_resp_i), + .compressed_valid_o(compressed_valid_o), + .compressed_req_o (compressed_req_o) + ); + end else begin + assign stall_instr_fetch[0] = stall_macro_deco; + end + end + + // --------------------------------------------------------- + // 2. Decode and emit instruction to issue stage + // --------------------------------------------------------- + + always_comb begin + // No CVXIF, No ZCMP, No ZCMT => Connect directly compressed decoder to decoder + is_illegal_deco = is_illegal_rvc; + instruction_deco = instruction_rvc; + is_compressed_deco = is_compressed_rvc; + if (CVA6Cfg.CvxifEn) begin + is_illegal_deco[0] = is_illegal_cvxif_o; + instruction_deco[0] = instruction_cvxif_o; + is_compressed_deco[0] = is_compressed_cvxif_o; + end else if (!CVA6Cfg.CvxifEn && (CVA6Cfg.RVZCMP || CVA6Cfg.RVZCMT)) begin + is_illegal_deco[0] = is_illegal_cvxif_i; + instruction_deco[0] = instruction_cvxif_i; + is_compressed_deco[0] = is_compressed_cvxif_i; + end + end + + assign rvfi_is_compressed_o = is_compressed_rvc; + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + decoder #( + .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), + .irq_ctrl_t(irq_ctrl_t), + .scoreboard_entry_t(scoreboard_entry_t), + .interrupts_t(interrupts_t), + .INTERRUPTS(INTERRUPTS) + ) decoder_i ( + .debug_req_i, + .irq_ctrl_i, + .irq_i, + .pc_i (fetch_entry_i[i].address), + .is_compressed_i (is_compressed_deco[i]), + .is_macro_instr_i (is_macro_instr[i]), + .is_zcmt_i (is_zcmt_instr[i]), + .is_last_macro_instr_i (is_last_macro_instr), + .is_double_rd_macro_instr_i(is_double_rd_macro_instr), + .jump_address_i (jump_address), + .is_illegal_i (is_illegal_deco[i]), + .instruction_i (instruction_deco[i]), + .compressed_instr_i (fetch_entry_i[i].instruction[15:0]), + .branch_predict_i (fetch_entry_i[i].branch_predict), + .ex_i (fetch_entry_i[i].ex), + .priv_lvl_i (priv_lvl_i), + .v_i (v_i), + .debug_mode_i (debug_mode_i), + .fs_i, + .vfs_i, + .frm_i, + .vs_i, + .tvm_i, + .tw_i, + .vtw_i, + .tsr_i, + .hu_i, + .instruction_o (decoded_instruction[i]), + .orig_instr_o (orig_instr[i]), + .is_control_flow_instr_o (is_control_flow_instr[i]) + ); + end + + // ------------------ + // 3. Pipeline Register + // ------------------ + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign issue_entry_o[i] = issue_q[i].sbe; + assign issue_entry_o_prev[i] = CVA6Cfg.FpgaAlteraEn ? issue_n[i].sbe : '0; + assign issue_entry_valid_o[i] = issue_q[i].valid; + assign is_ctrl_flow_o[i] = issue_q[i].is_ctrl_flow; + assign orig_instr_o[i] = issue_q[i].orig_instr; + end + + if (CVA6Cfg.SuperscalarEn) begin + always_comb begin + issue_n = issue_q; + fetch_entry_ready_o = '0; + // instruction is not valid if we stall due to ZCMT or CVXIF + decoded_instruction_valid[0] = (CVA6Cfg.RVZCMT && is_zcmt_instr[0] && stall_macro_deco_zcmt) || + (CVA6Cfg.CvxifEn && is_illegal_cvxif_i && ~stall_macro_deco) && stall_instr_fetch[0] + ? 1'b0 : 1'b1; + // Instruction on port 1 are always valid. It is either 32bits or legal 16bits. + decoded_instruction_valid[1] = ~stall_instr_fetch[1]; + + // Clear the valid flag if issue has acknowledged the instruction + if (issue_instr_ack_i[0]) begin + issue_n[0].valid = 1'b0; + end + if (issue_instr_ack_i[1]) begin + issue_n[1].valid = 1'b0; + end + + if (!issue_n[0].valid) begin + if (issue_n[1].valid) begin + issue_n[0] = issue_n[1]; + issue_n[1].valid = 1'b0; + end else if (fetch_entry_valid_i[0]) begin + fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; + issue_n[0] = '{ + decoded_instruction_valid[0], + decoded_instruction[0], + orig_instr[0], + is_control_flow_instr[0] + }; + end + end + + if (!issue_n[1].valid) begin + if (fetch_entry_ready_o[0]) begin + if (fetch_entry_valid_i[1]) begin + fetch_entry_ready_o[1] = ~stall_instr_fetch[1]; + issue_n[1] = '{ + decoded_instruction_valid[1], + decoded_instruction[1], + orig_instr[1], + is_control_flow_instr[1] + }; + end + end else if (fetch_entry_valid_i[0]) begin + fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; + issue_n[1] = '{ + decoded_instruction_valid[0], + decoded_instruction[0], + orig_instr[0], + is_control_flow_instr[0] + }; + end + end + + if (flush_i) begin + issue_n[0].valid = 1'b0; + issue_n[1].valid = 1'b0; + end + end + end else begin + always_comb begin + issue_n = issue_q; + fetch_entry_ready_o = '0; + // instruction is not valid if we stall due to ZCMT or CVXIF + decoded_instruction_valid[0] = (CVA6Cfg.RVZCMT && is_zcmt_instr[0] && stall_macro_deco_zcmt) || + (CVA6Cfg.CvxifEn && is_illegal_cvxif_i && ~stall_macro_deco && stall_instr_fetch[0]) + ? 1'b0 : 1'b1; + // Clear the valid flag if issue has acknowledged the instruction + if (issue_instr_ack_i[0]) issue_n[0].valid = 1'b0; + + // TODO: refaire + // if we have a space in the register and the fetch is valid, go get it + // or the issue stage is currently acknowledging an instruction, which means that we will have space + // for a new instruction + if (!issue_n[0].valid && fetch_entry_valid_i[0]) begin + fetch_entry_ready_o[0] = ~stall_instr_fetch[0]; + issue_n[0] = '{ + decoded_instruction_valid[0], + decoded_instruction[0], + orig_instr[0], + is_control_flow_instr[0] + }; + end + + // invalidate the pipeline register on a flush + if (flush_i) issue_n[0].valid = 1'b0; + end + end + // ------------------------- + // Registers (ID <-> Issue) + // ------------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + issue_q <= '0; + end else begin + issue_q <= issue_n; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/include/ariane_pkg.sv b/flow/designs/src/cva6/core/include/ariane_pkg.sv new file mode 100644 index 0000000000..e965b1e093 --- /dev/null +++ b/flow/designs/src/cva6/core/include/ariane_pkg.sv @@ -0,0 +1,818 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: ariane_pkg.sv + * Author: Florian Zaruba + * Date: 8.4.2017 + * + * Description: Contains all the necessary defines for Ariane + * in one package. + */ + +// this is needed to propagate the +// configuration in case Ariane is +// instantiated in OpenPiton +`ifdef PITON_ARIANE +`include "l15.tmp.h" +`endif + +/// This package contains `functions` and global defines for CVA6. +/// *Note*: There are some parameters here as well which will eventually be +/// moved out to favour a fully parameterizable core. +package ariane_pkg; + + // TODO: Slowly move those parameters to the new system. + localparam BITS_SATURATION_COUNTER = 2; + + // depth of store-buffers, this needs to be a power of two + localparam logic [2:0] DEPTH_SPEC = 'd4; + + // if CVA6Cfg.DCacheType = cva6_config_pkg::WT + // we can use a small commit queue since we have a write buffer in the dcache + // we could in principle do without the commit queue in this case, but the timing degrades if we do that due + // to longer paths into the commit stage + // if CVA6Cfg.DCacheType = cva6_config_pkg::WB + // allocate more space for the commit buffer to be on the save side, this needs to be a power of two + localparam logic [2:0] DEPTH_COMMIT = 'd4; + + // Transprecision float unit + localparam int unsigned LAT_COMP_FP32 = 'd2; + localparam int unsigned LAT_COMP_FP64 = 'd3; + localparam int unsigned LAT_COMP_FP16 = 'd1; + localparam int unsigned LAT_COMP_FP16ALT = 'd1; + localparam int unsigned LAT_COMP_FP8 = 'd1; + localparam int unsigned LAT_DIVSQRT = 'd2; + localparam int unsigned LAT_NONCOMP = 'd1; + localparam int unsigned LAT_CONV = 'd2; + + localparam logic [31:0] OPENHWGROUP_MVENDORID = 32'h0602; + localparam logic [31:0] ARIANE_MARCHID = 32'd3; + + // 32 registers + localparam REG_ADDR_SIZE = 5; + + // Read ports for general purpose register files + localparam NR_RGPR_PORTS = 2; + + // static debug hartinfo + // debug causes + localparam logic [2:0] CauseBreakpoint = 3'h1; + localparam logic [2:0] CauseTrigger = 3'h2; + localparam logic [2:0] CauseRequest = 3'h3; + localparam logic [2:0] CauseSingleStep = 3'h4; + // amount of data count registers implemented + localparam logic [3:0] DataCount = 4'h2; + + // address where data0-15 is shadowed or if shadowed in a CSR + // address of the first CSR used for shadowing the data + localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here + typedef struct packed { + logic [31:24] zero1; + logic [23:20] nscratch; + logic [19:17] zero0; + logic dataaccess; + logic [15:12] datasize; + logic [11:0] dataaddr; + } hartinfo_t; + + localparam hartinfo_t DebugHartInfo = '{ + zero1: '0, + nscratch: 2, // Debug module needs at least two scratch regs + zero0: '0, + dataaccess: 1'b1, // data registers are memory mapped in the debugger + datasize: DataCount, + dataaddr: DataAddr + }; + + // enables a commit log which matches spikes commit log format for easier trace comparison + localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b1; + + // ------------- Dangerous ------------- + // if set to zero a flush will not invalidate the cache-lines, in a single core environment + // where coherence is not necessary this can improve performance. This needs to be switched on + // when more than one core is in a system + localparam logic INVALIDATE_ON_FLUSH = 1'b1; + +`ifdef SPIKE_TANDEM + // Spike still places 0 in TVAL for ENV_CALL_* exceptions. + // This may eventually go away when Spike starts to handle TVAL for *all* exceptions. + localparam bit ZERO_TVAL = 1'b1; +`else + localparam bit ZERO_TVAL = 1'b0; +`endif + + // read mask for SSTATUS over MMSTATUS + function automatic logic [63:0] smode_status_read_mask(config_pkg::cva6_cfg_t Cfg); + return riscv::SSTATUS_UIE + | riscv::SSTATUS_SIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_SPP + | riscv::SSTATUS_FS + | riscv::SSTATUS_XS + | riscv::SSTATUS_SUM + | riscv::SSTATUS_MXR + | riscv::SSTATUS_UPIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_UXL + | riscv::sstatus_sd(Cfg.IS_XLEN64); + endfunction + + localparam logic [63:0] SMODE_STATUS_WRITE_MASK = riscv::SSTATUS_SIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_SPP + | riscv::SSTATUS_FS + | riscv::SSTATUS_SUM + | riscv::SSTATUS_MXR; + + localparam logic [63:0] HSTATUS_WRITE_MASK = riscv::HSTATUS_VSBE + | riscv::HSTATUS_GVA + | riscv::HSTATUS_SPV + | riscv::HSTATUS_SPVP + | riscv::HSTATUS_HU + | riscv::HSTATUS_VTVM + | riscv::HSTATUS_VTW + | riscv::HSTATUS_VTSR; + + // hypervisor delegable interrupts + function automatic logic [31:0] hs_deleg_interrupts(config_pkg::cva6_cfg_t Cfg); + return riscv::MIP_VSSIP | riscv::MIP_VSTIP | riscv::MIP_VSEIP; + endfunction + + // virtual supervisor delegable interrupts + function automatic logic [31:0] vs_deleg_interrupts(config_pkg::cva6_cfg_t Cfg); + return riscv::MIP_VSSIP | riscv::MIP_VSTIP | riscv::MIP_VSEIP; + endfunction + + // --------------- + // AXI + // --------------- + + typedef enum logic { + SINGLE_REQ, + CACHE_LINE_REQ + } ad_req_t; + + // --------------- + // Fetch Stage + // --------------- + + // leave as is (fails with >8 entries and wider fetch width) + localparam int unsigned FETCH_FIFO_DEPTH = 4; + localparam int unsigned FETCH_ADDR_FIFO_DEPTH = 2; + + typedef enum logic [2:0] { + NoCF, // No control flow prediction + Branch, // Branch + Jump, // Jump to address from immediate + JumpR, // Jump to address from registers + Return // Return Address Prediction + } cf_t; + + typedef struct packed { + logic valid; + logic taken; + } bht_prediction_t; + + typedef struct packed { + logic valid; + logic [1:0] saturation_counter; + } bht_t; + + typedef enum logic [3:0] { + NONE, // 0 + LOAD, // 1 + STORE, // 2 + ALU, // 3 + CTRL_FLOW, // 4 + MULT, // 5 + CSR, // 6 + FPU, // 7 + FPU_VEC, // 8 + CVXIF, // 9 + ACCEL // 10 + } fu_t; + + // Index of writeback ports + localparam FLU_WB = 0; + localparam STORE_WB = 1; + localparam LOAD_WB = 2; + localparam FPU_WB = 3; + localparam ACC_WB = 4; + localparam X_WB = 4; + + localparam EXC_OFF_RST = 8'h80; + + localparam SupervisorIrq = 1; + localparam MachineIrq = 0; + + // --------------- + // Cache config + // --------------- + + // for usage in OpenPiton we have to propagate the openpiton L15 configuration from l15.h +`ifdef PITON_ARIANE + +`ifndef CONFIG_L1I_CACHELINE_WIDTH + `define CONFIG_L1I_CACHELINE_WIDTH 128 +`endif + +`ifndef CONFIG_L1I_ASSOCIATIVITY + `define CONFIG_L1I_ASSOCIATIVITY 4 +`endif + +`ifndef CONFIG_L1I_SIZE + `define CONFIG_L1I_SIZE 16*1024 +`endif + +`ifndef CONFIG_L1D_CACHELINE_WIDTH + `define CONFIG_L1D_CACHELINE_WIDTH 128 +`endif + +`ifndef CONFIG_L1D_ASSOCIATIVITY + `define CONFIG_L1D_ASSOCIATIVITY 8 +`endif + +`ifndef CONFIG_L1D_SIZE + `define CONFIG_L1D_SIZE 32*1024 +`endif + +`ifndef L15_THREADID_WIDTH + `define L15_THREADID_WIDTH 3 +`endif + + // I$ + localparam int unsigned ICACHE_LINE_WIDTH = `CONFIG_L1I_CACHELINE_WIDTH; + localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY; + localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); + localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN - ICACHE_INDEX_WIDTH; + localparam int unsigned ICACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit + // D$ + localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH; + localparam int unsigned DCACHE_SET_ASSOC = `CONFIG_L1D_ASSOCIATIVITY; + localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(`CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); + localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN - DCACHE_INDEX_WIDTH; + localparam int unsigned DCACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit + localparam int unsigned DCACHE_USER_WIDTH = cva6_config_pkg::CVA6ConfigDataUserWidth; + + localparam int unsigned MEM_TID_WIDTH = `L15_THREADID_WIDTH; +`endif + + // --------------- + // EX Stage + // --------------- + + typedef enum logic [7:0] { // basic ALU op + ADD, + SUB, + ADDW, + SUBW, + // logic operations + XORL, + ORL, + ANDL, + // shifts + SRA, + SRL, + SLL, + SRLW, + SLLW, + SRAW, + // comparisons + LTS, + LTU, + GES, + GEU, + EQ, + NE, + // jumps + JALR, + BRANCH, + // set lower than operations + SLTS, + SLTU, + // CSR functions + MRET, + SRET, + DRET, + ECALL, + WFI, + FENCE, + FENCE_I, + SFENCE_VMA, + HFENCE_VVMA, + HFENCE_GVMA, + CSR_WRITE, + CSR_READ, + CSR_SET, + CSR_CLEAR, + // LSU functions + LD, + SD, + LW, + LWU, + SW, + LH, + LHU, + SH, + LB, + SB, + LBU, + // Hypervisor Virtual-Machine Load and Store Instructions + HLV_B, + HLV_BU, + HLV_H, + HLV_HU, + HLVX_HU, + HLV_W, + HLVX_WU, + HSV_B, + HSV_H, + HSV_W, + HLV_WU, + HLV_D, + HSV_D, + // Atomic Memory Operations + AMO_LRW, + AMO_LRD, + AMO_SCW, + AMO_SCD, + AMO_SWAPW, + AMO_ADDW, + AMO_ANDW, + AMO_ORW, + AMO_XORW, + AMO_MAXW, + AMO_MAXWU, + AMO_MINW, + AMO_MINWU, + AMO_SWAPD, + AMO_ADDD, + AMO_ANDD, + AMO_ORD, + AMO_XORD, + AMO_MAXD, + AMO_MAXDU, + AMO_MIND, + AMO_MINDU, + // Multiplications + MUL, + MULH, + MULHU, + MULHSU, + MULW, + // Divisions + DIV, + DIVU, + DIVW, + DIVUW, + REM, + REMU, + REMW, + REMUW, + // Floating-Point Load and Store Instructions + FLD, + FLW, + FLH, + FLB, + FSD, + FSW, + FSH, + FSB, + // Floating-Point Computational Instructions + FADD, + FSUB, + FMUL, + FDIV, + FMIN_MAX, + FSQRT, + FMADD, + FMSUB, + FNMSUB, + FNMADD, + // Floating-Point Conversion and Move Instructions + FCVT_F2I, + FCVT_I2F, + FCVT_F2F, + FSGNJ, + FMV_F2X, + FMV_X2F, + // Floating-Point Compare Instructions + FCMP, + // Floating-Point Classify Instruction + FCLASS, + // Vectorial Floating-Point Instructions that don't directly map onto the scalar ones + VFMIN, + VFMAX, + VFSGNJ, + VFSGNJN, + VFSGNJX, + VFEQ, + VFNE, + VFLT, + VFGE, + VFLE, + VFGT, + VFCPKAB_S, + VFCPKCD_S, + VFCPKAB_D, + VFCPKCD_D, + // Offload Instructions to be directed into cv_x_if + OFFLOAD, + // Or-Combine and REV8 + ORCB, + REV8, + // Bitwise Rotation + ROL, + ROLW, + ROR, + RORI, + RORIW, + RORW, + // Sign and Zero Extend + SEXTB, + SEXTH, + ZEXTH, + // Count population + CPOP, + CPOPW, + // Count Leading/Training Zeros + CLZ, + CLZW, + CTZ, + CTZW, + // Carry less multiplication Op's + CLMUL, + CLMULH, + CLMULR, + // Single bit instructions Op's + BCLR, + BCLRI, + BEXT, + BEXTI, + BINV, + BINVI, + BSET, + BSETI, + // Integer minimum/maximum + MAX, + MAXU, + MIN, + MINU, + // Shift with Add Unsigned Word and Unsigned Word Op's (Bitmanip) + SH1ADDUW, + SH2ADDUW, + SH3ADDUW, + ADDUW, + SLLIUW, + // Shift with Add (Bitmanip) + SH1ADD, + SH2ADD, + SH3ADD, + // Bitmanip Logical with negate op (Bitmanip) + ANDN, + ORN, + XNOR, + // Accelerator operations + ACCEL_OP, + ACCEL_OP_FS1, + ACCEL_OP_FD, + ACCEL_OP_LOAD, + ACCEL_OP_STORE, + // Zicond instruction + CZERO_EQZ, + CZERO_NEZ, + // Pack instructions + PACK, + PACK_H, + PACK_W, + // Brev8 instruction + BREV8, + // Zip instructions + UNZIP, + ZIP + } fu_op; + + function automatic logic op_is_branch(input fu_op op); + unique case (op) inside + EQ, NE, LTS, GES, LTU, GEU: return 1'b1; + default: return 1'b0; // all other ops + endcase + endfunction + + // ------------------------------- + // Extract Src/Dst FP Reg from Op + // ------------------------------- + // function used in instr_trace svh + // is_rs1_fpr function is kept to allow cva6 compilation with instr_trace feature + function automatic logic is_rs1_fpr(input fu_op op); + unique case (op) inside + [FMUL : FNMADD], // Computational Operations (except ADD/SUB) + FCVT_F2I, // Float-Int Casts + FCVT_F2F, // Float-Float Casts + FSGNJ, // Sign Injections + FMV_F2X, // FPR-GPR Moves + FCMP, // Comparisons + FCLASS, // Classifications + [VFMIN : VFCPKCD_D], // Additional Vectorial FP ops + ACCEL_OP_FS1: + return 1'b1; // Accelerator instructions + default: return 1'b0; // all other ops + endcase + endfunction + + // function used in instr_trace svh + // is_rs2_fpr function is kept to allow cva6 compilation with instr_trace feature + function automatic logic is_rs2_fpr(input fu_op op); + unique case (op) inside + [FSD : FSB], // FP Stores + [FADD : FMIN_MAX], // Computational Operations (no sqrt) + [FMADD : FNMADD], // Fused Computational Operations + FCVT_F2F, // Vectorial F2F Conversions requrie target + [FSGNJ : FMV_F2X], // Sign Injections and moves mapped to SGNJ + FCMP, // Comparisons + [VFMIN : VFCPKCD_D]: + return 1'b1; // Additional Vectorial FP ops + default: return 1'b0; // all other ops + endcase + endfunction + + // function used in instr_trace svh + // is_imm_fpr function is kept to allow cva6 compilation with instr_trace feature + // ternary operations encode the rs3 address in the imm field, also add/sub + function automatic logic is_imm_fpr(input fu_op op); + unique case (op) inside + [FADD : FSUB], // ADD/SUB need inputs as Operand B/C + [FMADD : FNMADD], // Fused Computational Operations + [VFCPKAB_S : VFCPKCD_D]: + return 1'b1; // Vectorial FP cast and pack ops + default: return 1'b0; // all other ops + endcase + endfunction + + // function used in instr_trace svh + // is_rd_fpr function is kept to allow cva6 compilation with instr_trace feature + function automatic logic is_rd_fpr(input fu_op op); + unique case (op) inside + [FLD : FLB], // FP Loads + [FADD : FNMADD], // Computational Operations + FCVT_I2F, // Int-Float Casts + FCVT_F2F, // Float-Float Casts + FSGNJ, // Sign Injections + FMV_X2F, // GPR-FPR Moves + [VFMIN : VFSGNJX], // Vectorial MIN/MAX and SGNJ + [VFCPKAB_S : VFCPKCD_D], // Vectorial FP cast and pack ops + ACCEL_OP_FD: + return 1'b1; // Accelerator instructions + default: return 1'b0; // all other ops + endcase + endfunction + + function automatic logic is_amo(fu_op op); + case (op) inside + [AMO_LRW : AMO_MINDU]: begin + return 1'b1; + end + default: return 1'b0; + endcase + endfunction + + // ------------------- + // Performance counter + // ------------------- + localparam int unsigned MHPMCounterNum = 6; + + // -------------------- + // Atomics + // -------------------- + typedef enum logic [3:0] { + AMO_NONE = 4'b0000, + AMO_LR = 4'b0001, + AMO_SC = 4'b0010, + AMO_SWAP = 4'b0011, + AMO_ADD = 4'b0100, + AMO_AND = 4'b0101, + AMO_OR = 4'b0110, + AMO_XOR = 4'b0111, + AMO_MAX = 4'b1000, + AMO_MAXU = 4'b1001, + AMO_MIN = 4'b1010, + AMO_MINU = 4'b1011, + AMO_CAS1 = 4'b1100, // unused, not part of riscv spec, but provided in OpenPiton + AMO_CAS2 = 4'b1101 // unused, not part of riscv spec, but provided in OpenPiton + } amo_t; + + // Bits required for representation of physical address space as 4K pages + // (e.g. 27*4K == 39bit address space). + localparam PPN4K_WIDTH = 38; + + typedef struct packed { + logic valid; // valid flag + logic is_4M; // + logic [20-1:0] vpn; //VPN (32bits) = 20bits + 12bits offset + logic [9-1:0] asid; //ASID length = 9 for Sv32 mmu + riscv::pte_sv32_t content; + } tlb_update_sv32_t; + + typedef enum logic [1:0] { + FE_NONE, + FE_INSTR_ACCESS_FAULT, + FE_INSTR_PAGE_FAULT, + FE_INSTR_GUEST_PAGE_FAULT + } frontend_exception_t; + + // AMO request going to cache. this request is unconditionally valid as soon + // as request goes high. + // Furthermore, those signals are kept stable until the response indicates + // completion by asserting ack. + typedef struct packed { + logic req; // this request is valid + amo_t amo_op; // atomic memory operation to perform + logic [1:0] size; // 2'b10 --> word operation, 2'b11 --> double word operation + logic [63:0] operand_a; // address + logic [63:0] operand_b; // data as layouted in the register + } amo_req_t; + + // AMO response coming from cache. + typedef struct packed { + logic ack; // response is valid + logic [63:0] result; // sign-extended, result + } amo_resp_t; + + localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace; + + // ---------------------- + // Arithmetic Functions + // ---------------------- + function automatic logic [63:0] sext32to64(logic [31:0] operand); + return {{32{operand[31]}}, operand[31:0]}; + endfunction + + // ---------------------- + // LSU Functions + // ---------------------- + // generate byte enable mask + function automatic logic [7:0] be_gen(logic [2:0] addr, logic [1:0] size); + case (size) + 2'b11: begin + return 8'b1111_1111; + end + 2'b10: begin + case (addr[2:0]) + 3'b000: return 8'b0000_1111; + 3'b001: return 8'b0001_1110; + 3'b010: return 8'b0011_1100; + 3'b011: return 8'b0111_1000; + 3'b100: return 8'b1111_0000; + default: ; // Do nothing + endcase + end + 2'b01: begin + case (addr[2:0]) + 3'b000: return 8'b0000_0011; + 3'b001: return 8'b0000_0110; + 3'b010: return 8'b0000_1100; + 3'b011: return 8'b0001_1000; + 3'b100: return 8'b0011_0000; + 3'b101: return 8'b0110_0000; + 3'b110: return 8'b1100_0000; + default: ; // Do nothing + endcase + end + 2'b00: begin + case (addr[2:0]) + 3'b000: return 8'b0000_0001; + 3'b001: return 8'b0000_0010; + 3'b010: return 8'b0000_0100; + 3'b011: return 8'b0000_1000; + 3'b100: return 8'b0001_0000; + 3'b101: return 8'b0010_0000; + 3'b110: return 8'b0100_0000; + 3'b111: return 8'b1000_0000; + endcase + end + endcase + return 8'b0; + endfunction + + function automatic logic [3:0] be_gen_32(logic [1:0] addr, logic [1:0] size); + case (size) + 2'b10: begin + return 4'b1111; + end + 2'b01: begin + case (addr[1:0]) + 2'b00: return 4'b0011; + 2'b01: return 4'b0110; + 2'b10: return 4'b1100; + default: ; // Do nothing + endcase + end + 2'b00: begin + case (addr[1:0]) + 2'b00: return 4'b0001; + 2'b01: return 4'b0010; + 2'b10: return 4'b0100; + 2'b11: return 4'b1000; + endcase + end + default: return 4'b0; + endcase + return 4'b0; + endfunction + + // ---------------------- + // Extract Bytes from Op + // ---------------------- + function automatic logic [1:0] extract_transfer_size(fu_op op); + case (op) + LD, HLV_D, SD, HSV_D, FLD, FSD, + AMO_LRD, AMO_SCD, + AMO_SWAPD, AMO_ADDD, + AMO_ANDD, AMO_ORD, + AMO_XORD, AMO_MAXD, + AMO_MAXDU, AMO_MIND, + AMO_MINDU: begin + return 2'b11; + end + LW, LWU, HLV_W, HLV_WU, HLVX_WU, + SW, HSV_W, FLW, FSW, + AMO_LRW, AMO_SCW, + AMO_SWAPW, AMO_ADDW, + AMO_ANDW, AMO_ORW, + AMO_XORW, AMO_MAXW, + AMO_MAXWU, AMO_MINW, + AMO_MINWU: begin + return 2'b10; + end + LH, LHU, HLV_H, HLV_HU, HLVX_HU, SH, HSV_H, FLH, FSH: return 2'b01; + LB, LBU, HLV_B, HLV_BU, SB, HSV_B, FLB, FSB: return 2'b00; + default: return 2'b11; + endcase + endfunction + // ---------------------- + // MMU Functions + // ---------------------- + + // checks if final translation page size is 1G when H-extension is enabled + function automatic logic is_trans_1G(input logic s_st_enbl, input logic g_st_enbl, + input logic is_s_1G, input logic is_g_1G); + return (((is_s_1G && s_st_enbl) || !s_st_enbl) && ((is_g_1G && g_st_enbl) || !g_st_enbl)); + endfunction : is_trans_1G + + // checks if final translation page size is 2M when H-extension is enabled + function automatic logic is_trans_2M(input logic s_st_enbl, input logic g_st_enbl, + input logic is_s_1G, input logic is_s_2M, + input logic is_g_1G, input logic is_g_2M); + return (s_st_enbl && g_st_enbl) ? + ((is_s_2M && (is_g_1G || is_g_2M)) || (is_g_2M && (is_s_1G || is_s_2M))) : + ((is_s_2M && s_st_enbl) || (is_g_2M && g_st_enbl)); + endfunction : is_trans_2M + + // computes the paddr based on the page size, ppn and offset + function automatic logic [40:0] make_gpaddr(input logic s_st_enbl, input logic is_1G, + input logic is_2M, input logic [63:0] vaddr, + input riscv::pte_t pte); + logic [40:0] gpaddr; + if (s_st_enbl) begin + gpaddr = {pte.ppn[28:0], vaddr[11:0]}; + // Giga page + if (is_1G) gpaddr[29:12] = vaddr[29:12]; + // Mega page + if (is_2M) gpaddr[20:12] = vaddr[20:12]; + end else begin + gpaddr = vaddr[40:0]; + end + return gpaddr; + endfunction : make_gpaddr + + // computes the final gppn based on the guest physical address + function automatic logic [28:0] make_gppn(input logic s_st_enbl, input logic is_1G, + input logic is_2M, input logic [28:0] vpn, + input riscv::pte_t pte); + logic [28:0] gppn; + if (s_st_enbl) begin + gppn = pte.ppn[28:0]; + if (is_2M) gppn[8:0] = vpn[8:0]; + if (is_1G) gppn[17:0] = vpn[17:0]; + end else begin + gppn = vpn; + end + return gppn; + endfunction : make_gppn + + // ---------------------- + // Helper functions + // ---------------------- + // Avoid negative array slices when defining parametrized sizes + function automatic int unsigned avoid_neg(int n); + return (n < 0) ? 0 : n; + endfunction : avoid_neg + +endpackage diff --git a/flow/designs/src/cva6/core/include/build_config_pkg.sv b/flow/designs/src/cva6/core/include/build_config_pkg.sv new file mode 100644 index 0000000000..e40ad5c987 --- /dev/null +++ b/flow/designs/src/cva6/core/include/build_config_pkg.sv @@ -0,0 +1,196 @@ +package build_config_pkg; + + function automatic config_pkg::cva6_cfg_t build_config(config_pkg::cva6_user_cfg_t CVA6Cfg); + bit IS_XLEN32 = (CVA6Cfg.XLEN == 32) ? 1'b1 : 1'b0; + bit IS_XLEN64 = (CVA6Cfg.XLEN == 32) ? 1'b0 : 1'b1; + bit FpPresent = CVA6Cfg.RVF | CVA6Cfg.RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8; + bit NSX = CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8 | CVA6Cfg.XFVec; // Are non-standard extensions present? + int unsigned FLen = CVA6Cfg.RVD ? 64 : // D ext. + CVA6Cfg.RVF ? 32 : // F ext. + CVA6Cfg.XF16 ? 16 : // Xf16 ext. + CVA6Cfg.XF16ALT ? 16 : // Xf16alt ext. + CVA6Cfg.XF8 ? 8 : // Xf8 ext. + 1; // Unused in case of no FP + + // Transprecision floating-point extensions configuration + bit RVFVec = CVA6Cfg.RVF & CVA6Cfg.XFVec & FLen>32; // FP32 vectors available if vectors and larger fmt enabled + bit XF16Vec = CVA6Cfg.XF16 & CVA6Cfg.XFVec & FLen>16; // FP16 vectors available if vectors and larger fmt enabled + bit XF16ALTVec = CVA6Cfg.XF16ALT & CVA6Cfg.XFVec & FLen>16; // FP16ALT vectors available if vectors and larger fmt enabled + bit XF8Vec = CVA6Cfg.XF8 & CVA6Cfg.XFVec & FLen>8; // FP8 vectors available if vectors and larger fmt enabled + + bit EnableAccelerator = CVA6Cfg.RVV; // Currently only used by V extension (Ara) + int unsigned NrWbPorts = (CVA6Cfg.CvxifEn || EnableAccelerator) ? 5 : 4; + + int unsigned ICACHE_INDEX_WIDTH = $clog2(CVA6Cfg.IcacheByteSize / CVA6Cfg.IcacheSetAssoc); + int unsigned DCACHE_INDEX_WIDTH = $clog2(CVA6Cfg.DcacheByteSize / CVA6Cfg.DcacheSetAssoc); + int unsigned DCACHE_OFFSET_WIDTH = $clog2(CVA6Cfg.DcacheLineWidth / 8); + + // MMU + int unsigned VpnLen = (CVA6Cfg.XLEN == 64) ? (CVA6Cfg.RVH ? 29 : 27) : 20; + int unsigned PtLevels = (CVA6Cfg.XLEN == 64) ? 3 : 2; + + config_pkg::cva6_cfg_t cfg; + + cfg.XLEN = CVA6Cfg.XLEN; + cfg.VLEN = CVA6Cfg.VLEN; + cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56; + cfg.GPLEN = (CVA6Cfg.XLEN == 32) ? 34 : 41; + cfg.IS_XLEN32 = IS_XLEN32; + cfg.IS_XLEN64 = IS_XLEN64; + cfg.XLEN_ALIGN_BYTES = $clog2(CVA6Cfg.XLEN / 8); + cfg.ASID_WIDTH = (CVA6Cfg.XLEN == 64) ? 16 : 1; + cfg.VMID_WIDTH = (CVA6Cfg.XLEN == 64) ? 14 : 1; + + cfg.FpgaEn = CVA6Cfg.FpgaEn; + cfg.FpgaAlteraEn = CVA6Cfg.FpgaAlteraEn; + cfg.TechnoCut = CVA6Cfg.TechnoCut; + + cfg.SuperscalarEn = CVA6Cfg.SuperscalarEn; + cfg.NrCommitPorts = CVA6Cfg.SuperscalarEn ? unsigned'(2) : CVA6Cfg.NrCommitPorts; + cfg.NrIssuePorts = unsigned'(CVA6Cfg.SuperscalarEn ? 2 : 1); + cfg.SpeculativeSb = CVA6Cfg.SuperscalarEn; + + cfg.NrLoadPipeRegs = CVA6Cfg.NrLoadPipeRegs; + cfg.NrStorePipeRegs = CVA6Cfg.NrStorePipeRegs; + cfg.AxiAddrWidth = CVA6Cfg.AxiAddrWidth; + cfg.AxiDataWidth = CVA6Cfg.AxiDataWidth; + cfg.AxiIdWidth = CVA6Cfg.AxiIdWidth; + cfg.AxiUserWidth = CVA6Cfg.AxiUserWidth; + cfg.MEM_TID_WIDTH = CVA6Cfg.MemTidWidth; + cfg.NrLoadBufEntries = CVA6Cfg.NrLoadBufEntries; + cfg.RVF = CVA6Cfg.RVF; + cfg.RVD = CVA6Cfg.RVD; + cfg.XF16 = CVA6Cfg.XF16; + cfg.XF16ALT = CVA6Cfg.XF16ALT; + cfg.XF8 = CVA6Cfg.XF8; + cfg.RVA = CVA6Cfg.RVA; + cfg.RVB = CVA6Cfg.RVB; + cfg.ZKN = CVA6Cfg.ZKN; + cfg.RVV = CVA6Cfg.RVV; + cfg.RVC = CVA6Cfg.RVC; + cfg.RVH = CVA6Cfg.RVH; + cfg.RVZCB = CVA6Cfg.RVZCB; + cfg.RVZCMT = CVA6Cfg.RVZCMT; + cfg.RVZCMP = CVA6Cfg.RVZCMP; + cfg.XFVec = CVA6Cfg.XFVec; + cfg.CvxifEn = CVA6Cfg.CvxifEn; + cfg.CoproType = CVA6Cfg.CoproType; + cfg.RVZiCond = CVA6Cfg.RVZiCond; + cfg.RVZicntr = CVA6Cfg.RVZicntr; + cfg.RVZihpm = CVA6Cfg.RVZihpm; + cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries; + cfg.TRANS_ID_BITS = $clog2(CVA6Cfg.NrScoreboardEntries); + + cfg.FpPresent = bit'(FpPresent); + cfg.NSX = bit'(NSX); + cfg.FLen = unsigned'(FLen); + cfg.RVFVec = bit'(RVFVec); + cfg.XF16Vec = bit'(XF16Vec); + cfg.XF16ALTVec = bit'(XF16ALTVec); + cfg.XF8Vec = bit'(XF8Vec); + // Can take 2 or 3 in single issue. 4 or 6 in dual issue. + cfg.NrRgprPorts = unsigned'(CVA6Cfg.SuperscalarEn ? 4 : 2); + // cfg.NrRgprPorts = unsigned'(CVA6Cfg.SuperscalarEn ? 6 : 3); + cfg.NrWbPorts = unsigned'(NrWbPorts); + cfg.EnableAccelerator = bit'(EnableAccelerator); + cfg.PerfCounterEn = CVA6Cfg.PerfCounterEn; + cfg.MmuPresent = CVA6Cfg.MmuPresent; + cfg.RVS = CVA6Cfg.RVS; + cfg.RVU = CVA6Cfg.RVU; + cfg.SoftwareInterruptEn = CVA6Cfg.SoftwareInterruptEn; + + cfg.HaltAddress = CVA6Cfg.HaltAddress; + cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress; + cfg.RASDepth = CVA6Cfg.RASDepth; + cfg.BTBEntries = CVA6Cfg.BTBEntries; + cfg.BPType = CVA6Cfg.BPType; + cfg.BHTEntries = CVA6Cfg.BHTEntries; + cfg.BHTHist = CVA6Cfg.BHTHist; + cfg.DmBaseAddress = CVA6Cfg.DmBaseAddress; + cfg.TvalEn = CVA6Cfg.TvalEn; + cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly; + cfg.NrPMPEntries = CVA6Cfg.NrPMPEntries; + cfg.PMPCfgRstVal = CVA6Cfg.PMPCfgRstVal; + cfg.PMPAddrRstVal = CVA6Cfg.PMPAddrRstVal; + cfg.PMPEntryReadOnly = CVA6Cfg.PMPEntryReadOnly; + cfg.PMPNapotEn = CVA6Cfg.PMPNapotEn; + cfg.NOCType = CVA6Cfg.NOCType; + cfg.NrNonIdempotentRules = CVA6Cfg.NrNonIdempotentRules; + cfg.NonIdempotentAddrBase = CVA6Cfg.NonIdempotentAddrBase; + cfg.NonIdempotentLength = CVA6Cfg.NonIdempotentLength; + cfg.NrExecuteRegionRules = CVA6Cfg.NrExecuteRegionRules; + cfg.ExecuteRegionAddrBase = CVA6Cfg.ExecuteRegionAddrBase; + cfg.ExecuteRegionLength = CVA6Cfg.ExecuteRegionLength; + cfg.NrCachedRegionRules = CVA6Cfg.NrCachedRegionRules; + cfg.CachedRegionAddrBase = CVA6Cfg.CachedRegionAddrBase; + cfg.CachedRegionLength = CVA6Cfg.CachedRegionLength; + cfg.MaxOutstandingStores = CVA6Cfg.MaxOutstandingStores; + cfg.DebugEn = CVA6Cfg.DebugEn; + cfg.NonIdemPotenceEn = (CVA6Cfg.NrNonIdempotentRules > 0) && (CVA6Cfg.NonIdempotentLength > 0); + cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; + + cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc; + cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : + CVA6Cfg.IcacheSetAssoc; + cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH; + cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH; + cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth; + cfg.ICACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.IcacheLineWidth; + cfg.DCacheType = CVA6Cfg.DCacheType; + cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth; + cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc; + cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : + CVA6Cfg.DcacheSetAssoc; + cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH; + cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH; + cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth; + cfg.DCACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.DcacheLineWidth; + cfg.DCACHE_USER_WIDTH = CVA6Cfg.AxiUserWidth; + cfg.DCACHE_OFFSET_WIDTH = DCACHE_OFFSET_WIDTH; + cfg.DCACHE_NUM_WORDS = 2 ** (DCACHE_INDEX_WIDTH - DCACHE_OFFSET_WIDTH); + + cfg.DCACHE_MAX_TX = unsigned'(2 ** CVA6Cfg.MemTidWidth); + + cfg.DcacheFlushOnFence = CVA6Cfg.DcacheFlushOnFence; + cfg.DcacheInvalidateOnFlush = CVA6Cfg.DcacheInvalidateOnFlush; + + cfg.DATA_USER_EN = CVA6Cfg.DataUserEn; + cfg.WtDcacheWbufDepth = CVA6Cfg.WtDcacheWbufDepth; + cfg.FETCH_USER_WIDTH = CVA6Cfg.FetchUserWidth; + cfg.FETCH_USER_EN = CVA6Cfg.FetchUserEn; + cfg.AXI_USER_EN = CVA6Cfg.DataUserEn | CVA6Cfg.FetchUserEn; + + cfg.FETCH_WIDTH = unsigned'(CVA6Cfg.SuperscalarEn ? 64 : 32); + cfg.FETCH_ALIGN_BITS = $clog2(cfg.FETCH_WIDTH / 8); + cfg.INSTR_PER_FETCH = cfg.FETCH_WIDTH / (CVA6Cfg.RVC ? 16 : 32); + cfg.LOG2_INSTR_PER_FETCH = cfg.INSTR_PER_FETCH > 1 ? $clog2(cfg.INSTR_PER_FETCH) : 1; + + cfg.ModeW = (CVA6Cfg.XLEN == 32) ? 1 : 4; + cfg.ASIDW = (CVA6Cfg.XLEN == 32) ? 9 : 16; + cfg.VMIDW = (CVA6Cfg.XLEN == 32) ? 7 : 14; + cfg.PPNW = (CVA6Cfg.XLEN == 32) ? 22 : 44; + cfg.GPPNW = (CVA6Cfg.XLEN == 32) ? 22 : 29; + cfg.MODE_SV = (CVA6Cfg.XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39; + cfg.SV = (cfg.MODE_SV == config_pkg::ModeSv32) ? 32 : 39; + cfg.SVX = (cfg.MODE_SV == config_pkg::ModeSv32) ? 34 : 41; + cfg.InstrTlbEntries = CVA6Cfg.InstrTlbEntries; + cfg.DataTlbEntries = CVA6Cfg.DataTlbEntries; + cfg.UseSharedTlb = CVA6Cfg.UseSharedTlb; + cfg.SharedTlbDepth = CVA6Cfg.SharedTlbDepth; + cfg.VpnLen = VpnLen; + cfg.PtLevels = PtLevels; + + cfg.X_NUM_RS = cfg.NrRgprPorts / cfg.NrIssuePorts; + cfg.X_ID_WIDTH = cfg.TRANS_ID_BITS; + cfg.X_RFR_WIDTH = cfg.XLEN; + cfg.X_RFW_WIDTH = cfg.XLEN; + cfg.X_NUM_HARTS = 1; + cfg.X_HARTID_WIDTH = cfg.XLEN; + cfg.X_DUALREAD = 0; + cfg.X_DUALWRITE = 0; + cfg.X_ISSUE_REGISTER_SPLIT = 0; + + return cfg; + endfunction + +endpackage diff --git a/flow/designs/src/cva6/core/include/config_pkg.sv b/flow/designs/src/cva6/core/include/config_pkg.sv new file mode 100644 index 0000000000..c6a5f2308a --- /dev/null +++ b/flow/designs/src/cva6/core/include/config_pkg.sv @@ -0,0 +1,465 @@ +// Copyright 2023 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +package config_pkg; + + // --------------- + // Global Config + // --------------- + localparam int unsigned ILEN = 32; + localparam int unsigned NRET = 1; + + /// The NoC type is a top-level parameter, hence we need a bit more + /// information on what protocol those type parameters are supporting. + /// Currently two values are supported" + typedef enum { + /// The "classic" AXI4 protocol. + NOC_TYPE_AXI4_ATOP, + /// In the OpenPiton setting the WT cache is connected to the L15. + NOC_TYPE_L15_BIG_ENDIAN, + NOC_TYPE_L15_LITTLE_ENDIAN + } noc_type_e; + + /// Cache type parameter + typedef enum logic [2:0] { + WB = 0, + WT = 1, + HPDCACHE_WT = 2, + HPDCACHE_WB = 3, + HPDCACHE_WT_WB = 4 + } cache_type_t; + + /// Branch predictor parameter + typedef enum logic { + BHT = 0, // Bimodal predictor + PH_BHT = 1 // Private History Bimodal predictor + } bp_type_t; + + /// Data and Address length + typedef enum logic [3:0] { + ModeOff = 0, + ModeSv32 = 1, + ModeSv39 = 8, + ModeSv48 = 9, + ModeSv57 = 10, + ModeSv64 = 11 + } vm_mode_t; + + /// Coprocessor type parameter + typedef enum { + COPRO_NONE, + COPRO_EXAMPLE + } copro_type_t; + + localparam NrMaxRules = 16; + + typedef struct packed { + // General Purpose Register Size (in bits) + int unsigned XLEN; + // Virtual address Size (in bits) + int unsigned VLEN; + // Atomic RISC-V extension + bit RVA; + // Bit manipulation RISC-V extension + bit RVB; + // Scalar Cryptography RISC-V entension + bit ZKN; + // Vector RISC-V extension + bit RVV; + // Compress RISC-V extension + bit RVC; + // Hypervisor RISC-V extension + bit RVH; + // Zcb RISC-V extension + bit RVZCB; + // Zcmp RISC-V extension + bit RVZCMP; + // Zcmt RISC-V extension + bit RVZCMT; + // Zicond RISC-V extension + bit RVZiCond; + // Zicntr RISC-V extension + bit RVZicntr; + // Zihpm RISC-V extension + bit RVZihpm; + // Floating Point + bit RVF; + // Floating Point + bit RVD; + // Non standard 16bits Floating Point extension + bit XF16; + // Non standard 16bits Floating Point Alt extension + bit XF16ALT; + // Non standard 8bits Floating Point extension + bit XF8; + // Non standard Vector Floating Point extension + bit XFVec; + // Perf counters + bit PerfCounterEn; + // MMU + bit MmuPresent; + // Supervisor mode + bit RVS; + // User mode + bit RVU; + // Software interrupts are enabled + bit SoftwareInterruptEn; + // Debug support + bit DebugEn; + // Base address of the debug module + logic [63:0] DmBaseAddress; + // Address to jump when halt request + logic [63:0] HaltAddress; + // Address to jump when exception + logic [63:0] ExceptionAddress; + // Tval Support Enable + bit TvalEn; + // MTVEC CSR supports only direct mode + bit DirectVecOnly; + // PMP entries number + int unsigned NrPMPEntries; + // PMP CSR configuration reset values + logic [63:0][63:0] PMPCfgRstVal; + // PMP CSR address reset values + logic [63:0][63:0] PMPAddrRstVal; + // PMP CSR read-only bits + bit [63:0] PMPEntryReadOnly; + // PMP NA4 and NAPOT mode enable + bit PMPNapotEn; + // PMA non idempotent rules number + int unsigned NrNonIdempotentRules; + // PMA NonIdempotent region base address + logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; + // PMA NonIdempotent region length + logic [NrMaxRules-1:0][63:0] NonIdempotentLength; + // PMA regions with execute rules number + int unsigned NrExecuteRegionRules; + // PMA Execute region base address + logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase; + // PMA Execute region address base + logic [NrMaxRules-1:0][63:0] ExecuteRegionLength; + // PMA regions with cache rules number + int unsigned NrCachedRegionRules; + // PMA cache region base address + logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase; + // PMA cache region rules + logic [NrMaxRules-1:0][63:0] CachedRegionLength; + // CV-X-IF coprocessor interface enable + bit CvxifEn; + // Coprocessor type + copro_type_t CoproType; + // NOC bus type + noc_type_e NOCType; + // AXI address width + int unsigned AxiAddrWidth; + // AXI data width + int unsigned AxiDataWidth; + // AXI ID width + int unsigned AxiIdWidth; + // AXI User width + int unsigned AxiUserWidth; + // AXI burst in write + bit AxiBurstWriteEn; + // TODO + int unsigned MemTidWidth; + // Instruction cache size (in bytes) + int unsigned IcacheByteSize; + // Instruction cache associativity (number of ways) + int unsigned IcacheSetAssoc; + // Instruction cache line width + int unsigned IcacheLineWidth; + // Cache Type + cache_type_t DCacheType; + // Data cache ID + int unsigned DcacheIdWidth; + // Data cache size (in bytes) + int unsigned DcacheByteSize; + // Data cache associativity (number of ways) + int unsigned DcacheSetAssoc; + // Data cache line width + int unsigned DcacheLineWidth; + // Data cache flush on fence + bit DcacheFlushOnFence; + // Data cache invalidate on flush + bit DcacheInvalidateOnFlush; + // User field on data bus enable + int unsigned DataUserEn; + // Write-through data cache write buffer depth + int unsigned WtDcacheWbufDepth; + // User field on fetch bus enable + int unsigned FetchUserEn; + // Width of fetch user field + int unsigned FetchUserWidth; + // Is FPGA optimization of CV32A6 for Xilinx and Altera + bit FpgaEn; + // Is FPGA optimization for Altera FPGA + bit FpgaAlteraEn; + // Is Techno Cut instanciated + bit TechnoCut; + // Enable superscalar* with 2 issue ports and 2 commit ports. + bit SuperscalarEn; + // Number of commit ports. Forced to 2 if SuperscalarEn. + int unsigned NrCommitPorts; + // Load cycle latency number + int unsigned NrLoadPipeRegs; + // Store cycle latency number + int unsigned NrStorePipeRegs; + // Scoreboard length + int unsigned NrScoreboardEntries; + // Load buffer entry buffer + int unsigned NrLoadBufEntries; + // Maximum number of outstanding stores + int unsigned MaxOutstandingStores; + // Return address stack depth + int unsigned RASDepth; + // Branch target buffer entries + int unsigned BTBEntries; + // Branch predictor type + bp_type_t BPType; + // Branch history entries + int unsigned BHTEntries; + // Branch history bits + int unsigned BHTHist; + // MMU instruction TLB entries + int unsigned InstrTlbEntries; + // MMU data TLB entries + int unsigned DataTlbEntries; + // MMU option to use shared TLB + bit unsigned UseSharedTlb; + // MMU depth of shared TLB + int unsigned SharedTlbDepth; + } cva6_user_cfg_t; + + typedef struct packed { + int unsigned XLEN; + int unsigned VLEN; + int unsigned PLEN; + int unsigned GPLEN; + bit IS_XLEN32; + bit IS_XLEN64; + int unsigned XLEN_ALIGN_BYTES; + int unsigned ASID_WIDTH; + int unsigned VMID_WIDTH; + + bit FpgaEn; + bit FpgaAlteraEn; + bit TechnoCut; + + bit SuperscalarEn; + int unsigned NrCommitPorts; + int unsigned NrIssuePorts; + bit SpeculativeSb; + + int unsigned NrLoadPipeRegs; + int unsigned NrStorePipeRegs; + /// AXI parameters. + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned AxiIdWidth; + int unsigned AxiUserWidth; + int unsigned MEM_TID_WIDTH; + int unsigned NrLoadBufEntries; + bit RVF; + bit RVD; + bit XF16; + bit XF16ALT; + bit XF8; + bit RVA; + bit RVB; + bit ZKN; + bit RVV; + bit RVC; + bit RVH; + bit RVZCB; + bit RVZCMP; + bit RVZCMT; + bit XFVec; + bit CvxifEn; + copro_type_t CoproType; + bit RVZiCond; + bit RVZicntr; + bit RVZihpm; + + int unsigned NR_SB_ENTRIES; + int unsigned TRANS_ID_BITS; + + bit FpPresent; + bit NSX; + int unsigned FLen; + bit RVFVec; + bit XF16Vec; + bit XF16ALTVec; + bit XF8Vec; + int unsigned NrRgprPorts; + int unsigned NrWbPorts; + bit EnableAccelerator; + bit PerfCounterEn; + bit MmuPresent; + bit RVS; //Supervisor mode + bit RVU; //User mode + bit SoftwareInterruptEn; + + logic [63:0] HaltAddress; + logic [63:0] ExceptionAddress; + int unsigned RASDepth; + int unsigned BTBEntries; + bp_type_t BPType; + int unsigned BHTEntries; + int unsigned BHTHist; + int unsigned InstrTlbEntries; + int unsigned DataTlbEntries; + bit unsigned UseSharedTlb; + int unsigned SharedTlbDepth; + int unsigned VpnLen; + int unsigned PtLevels; + + logic [63:0] DmBaseAddress; + bit TvalEn; + bit DirectVecOnly; + int unsigned NrPMPEntries; + logic [63:0][63:0] PMPCfgRstVal; + logic [63:0][63:0] PMPAddrRstVal; + bit [63:0] PMPEntryReadOnly; + bit PMPNapotEn; + noc_type_e NOCType; + int unsigned NrNonIdempotentRules; + logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; + logic [NrMaxRules-1:0][63:0] NonIdempotentLength; + int unsigned NrExecuteRegionRules; + logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase; + logic [NrMaxRules-1:0][63:0] ExecuteRegionLength; + int unsigned NrCachedRegionRules; + logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase; + logic [NrMaxRules-1:0][63:0] CachedRegionLength; + int unsigned MaxOutstandingStores; + bit DebugEn; + bit NonIdemPotenceEn; // Currently only used by V extension (Ara) + bit AxiBurstWriteEn; + + int unsigned ICACHE_SET_ASSOC; + int unsigned ICACHE_SET_ASSOC_WIDTH; + int unsigned ICACHE_INDEX_WIDTH; + int unsigned ICACHE_TAG_WIDTH; + int unsigned ICACHE_LINE_WIDTH; + int unsigned ICACHE_USER_LINE_WIDTH; + cache_type_t DCacheType; + int unsigned DcacheIdWidth; + int unsigned DCACHE_SET_ASSOC; + int unsigned DCACHE_SET_ASSOC_WIDTH; + int unsigned DCACHE_INDEX_WIDTH; + int unsigned DCACHE_TAG_WIDTH; + int unsigned DCACHE_LINE_WIDTH; + int unsigned DCACHE_USER_LINE_WIDTH; + int unsigned DCACHE_USER_WIDTH; + int unsigned DCACHE_OFFSET_WIDTH; + int unsigned DCACHE_NUM_WORDS; + + int unsigned DCACHE_MAX_TX; + + bit DcacheFlushOnFence; + bit DcacheInvalidateOnFlush; + + int unsigned DATA_USER_EN; + int unsigned WtDcacheWbufDepth; + int unsigned FETCH_USER_WIDTH; + int unsigned FETCH_USER_EN; + bit AXI_USER_EN; + + int unsigned FETCH_WIDTH; + int unsigned FETCH_ALIGN_BITS; + int unsigned INSTR_PER_FETCH; + int unsigned LOG2_INSTR_PER_FETCH; + + int unsigned ModeW; + int unsigned ASIDW; + int unsigned VMIDW; + int unsigned PPNW; + int unsigned GPPNW; + vm_mode_t MODE_SV; + int unsigned SV; + int unsigned SVX; + + int unsigned X_NUM_RS; + int unsigned X_ID_WIDTH; + int unsigned X_RFR_WIDTH; + int unsigned X_RFW_WIDTH; + int unsigned X_NUM_HARTS; + int unsigned X_HARTID_WIDTH; + int unsigned X_DUALREAD; + int unsigned X_DUALWRITE; + int unsigned X_ISSUE_REGISTER_SPLIT; + + } cva6_cfg_t; + + /// Empty configuration to sanity check proper parameter passing. Whenever + /// you develop a module that resides within the core, assign this constant. + localparam cva6_cfg_t cva6_cfg_empty = cva6_cfg_t'(0); + + /// Utility function being called to check parameters. Not all values make + /// sense for all parameters, here is the place to sanity check them. + function automatic void check_cfg(cva6_cfg_t Cfg); + // pragma translate_off + assert (Cfg.RASDepth > 0); + assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries)); + assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries)); + assert (Cfg.NrNonIdempotentRules <= NrMaxRules); + assert (Cfg.NrExecuteRegionRules <= NrMaxRules); + assert (Cfg.NrCachedRegionRules <= NrMaxRules); + assert (Cfg.NrPMPEntries <= 64); + assert (!(Cfg.SuperscalarEn && Cfg.RVF)); + assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64) + else $fatal(1, "[frontend] fetch width != not supported"); + // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported + // Software Interrupt can be disabled when there is only M machine mode in CVA6. + assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn)); + assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn)); + assert (!(Cfg.RVZCMT && ~Cfg.MmuPresent)); + // pragma translate_on + endfunction + + function automatic logic range_check(logic [63:0] base, logic [63:0] len, logic [63:0] address); + // if len is a power of two, and base is properly aligned, this check could be simplified + // Extend base by one bit to prevent an overflow. + return (address >= base) && (({1'b0, address}) < (65'(base) + len)); + endfunction : range_check + + + function automatic logic is_inside_nonidempotent_regions(cva6_cfg_t Cfg, logic [63:0] address); + logic [NrMaxRules-1:0] pass; + pass = '0; + for (int unsigned k = 0; k < Cfg.NrNonIdempotentRules; k++) begin + pass[k] = range_check(Cfg.NonIdempotentAddrBase[k], Cfg.NonIdempotentLength[k], address); + end + return |pass; + endfunction : is_inside_nonidempotent_regions + + function automatic logic is_inside_execute_regions(cva6_cfg_t Cfg, logic [63:0] address); + // if we don't specify any region we assume everything is accessible + logic [NrMaxRules-1:0] pass; + if (Cfg.NrExecuteRegionRules != 0) begin + pass = '0; + for (int unsigned k = 0; k < Cfg.NrExecuteRegionRules; k++) begin + pass[k] = range_check(Cfg.ExecuteRegionAddrBase[k], Cfg.ExecuteRegionLength[k], address); + end + return |pass; + end else begin + return 1; + end + endfunction : is_inside_execute_regions + + function automatic logic is_inside_cacheable_regions(cva6_cfg_t Cfg, logic [63:0] address); + automatic logic [NrMaxRules-1:0] pass; + pass = '0; + for (int unsigned k = 0; k < Cfg.NrCachedRegionRules; k++) begin + pass[k] = range_check(Cfg.CachedRegionAddrBase[k], Cfg.CachedRegionLength[k], address); + end + return |pass; + endfunction : is_inside_cacheable_regions + +endpackage diff --git a/flow/designs/src/cva6/core/include/cv32a65x_config_pkg.sv b/flow/designs/src/cva6/core/include/cv32a65x_config_pkg.sv new file mode 100644 index 0000000000..d3c530a6ca --- /dev/null +++ b/flow/designs/src/cva6/core/include/cv32a65x_config_pkg.sv @@ -0,0 +1,111 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 32; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv + localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv + localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv + localparam CVA6ConfigDataUserWidth = 32; // axi_pkg.sv + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(32), + FpgaEn: bit'(0), + FpgaAlteraEn: bit'(0), + TechnoCut: bit'(1), + SuperscalarEn: bit'(1), + NrCommitPorts: unsigned'(1), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(2), + RVF: bit'(0), + RVD: bit'(0), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(0), + RVB: bit'(1), + ZKN: bit'(0), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCMT: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_EXAMPLE, + RVZiCond: bit'(0), + RVZicntr: bit'(0), + RVZihpm: bit'(0), + NrScoreboardEntries: unsigned'(8), + PerfCounterEn: bit'(0), + MmuPresent: bit'(0), + RVS: bit'(0), + RVU: bit'(0), + SoftwareInterruptEn: bit'(0), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(2), + BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, + BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), + DmBaseAddress: 64'h0, + TvalEn: bit'(0), + DirectVecOnly: bit'(1), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(0), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(0), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(0), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(0), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(2048), + IcacheSetAssoc: unsigned'(2), + IcacheLineWidth: unsigned'(128), + DCacheType: config_pkg::HPDCACHE_WT, + DcacheByteSize: unsigned'(2028), + DcacheSetAssoc: unsigned'(2), + DcacheLineWidth: unsigned'(128), + DcacheFlushOnFence: bit'(0), + DcacheInvalidateOnFlush: bit'(0), + DataUserEn: unsigned'(1), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(1), + InstrTlbEntries: int'(2), + DataTlbEntries: int'(2), + UseSharedTlb: bit'(1), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(1) + }; + +endpackage diff --git a/flow/designs/src/cva6/core/include/cvxif_types.svh b/flow/designs/src/cva6/core/include/cvxif_types.svh new file mode 100644 index 0000000000..211742e05a --- /dev/null +++ b/flow/designs/src/cva6/core/include/cvxif_types.svh @@ -0,0 +1,73 @@ +`ifndef CVXIF_TYPES_SVH +`define CVXIF_TYPES_SVH + +//CVXIF +`define READREGFLAGS_T(Cfg) logic [Cfg.X_NUM_RS+Cfg.X_DUALREAD-1:0] +`define WRITEREGFLAGS_T(Cfg) logic [Cfg.X_DUALWRITE:0] +`define ID_T(Cfg) logic [Cfg.X_ID_WIDTH-1:0] +`define HARTID_T(Cfg) logic [Cfg.X_HARTID_WIDTH-1:0] + +`define X_COMPRESSED_REQ_T(Cfg, hartid_t) struct packed { \ + logic [15:0] instr; /*Offloaded compressed instruction*/ \ + hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ +} +`define X_COMPRESSED_RESP_T(Cfg) struct packed { \ + logic [31:0] instr; /*Uncompressed instruction*/ \ + logic accept; /*Is the offloaded compressed instruction (id) accepted by the coprocessor?*/ \ +} + +`define X_ISSUE_REQ_T(Cfg, hartit_t, id_t) struct packed { \ + logic [31:0] instr; /*Offloaded instruction*/ \ + hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ + id_t id; /*Identification of the offloaded instruction*/ \ +} +`define X_ISSUE_RESP_T(Cfg, writeregflags_t, readregflags_t) struct packed { \ + logic accept; /*Is the offloaded instruction (id) accepted by the coprocessor?*/ \ + writeregflags_t writeback; /*Will the coprocessor perform a writeback in the core to rd?*/ \ + readregflags_t register_read; /*Will the coprocessor perform require specific registers to be read?*/ \ +} + +`define X_REGISTER_T(Cfg, hartid_t, id_t, readregflags_t) struct packed { \ + hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ + id_t id; /*Identification of the offloaded instruction*/ \ + logic [Cfg.X_NUM_RS-1:0][Cfg.X_RFR_WIDTH-1:0] rs; /*Register file source operands for the offloaded instruction.*/ \ + readregflags_t rs_valid; /*Validity of the register file source operand(s).*/ \ +} + +`define X_COMMIT_T(Cfg, hartid_t, id_t) struct packed { \ + hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ + id_t id; /*Identification of the offloaded instruction*/ \ + logic commit_kill; /*Shall an offloaded instruction be killed?*/ \ +} + +`define X_RESULT_T(Cfg, hartid_t, id_t, writeregflags_t) struct packed { \ + hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ + id_t id; /*Identification of the offloaded instruction*/ \ + logic [Cfg.X_RFW_WIDTH-1:0] data; /*Register file write data value(s)*/ \ + logic [4:0] rd; /*Register file destination address(es)*/ \ + writeregflags_t we; /*Register file write enable(s)*/ \ +} + +`define CVXIF_REQ_T(Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t) struct packed { \ + logic compressed_valid; \ + x_compressed_req_t compressed_req; \ + logic issue_valid; \ + x_issue_req_t issue_req; \ + logic register_valid; \ + x_register_t register; \ + logic commit_valid; \ + x_commit_t commit; \ + logic result_ready; \ +} + +`define CVXIF_RESP_T(Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t) struct packed { \ + logic compressed_ready; \ + x_compressed_resp_t compressed_resp; \ + logic issue_ready; \ + x_issue_resp_t issue_resp; \ + logic register_ready; \ + logic result_valid; \ + x_result_t result; \ +} + +`endif // CVXIF_TYPES_SVH diff --git a/flow/designs/src/cva6/core/include/riscv_pkg.sv b/flow/designs/src/cva6/core/include/riscv_pkg.sv new file mode 100644 index 0000000000..e9dbc65a18 --- /dev/null +++ b/flow/designs/src/cva6/core/include/riscv_pkg.sv @@ -0,0 +1,1008 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: riscv_pkg.sv + * Author: Florian Zaruba + * Date: 30.6.2017 + * + * Description: Common RISC-V definitions. + */ + +package riscv; + + // ---------------------- + // Import cva6 config from cva6_config_pkg + // ---------------------- + // FIXME stop using them from CoreV-Verif and HPDCache + // Then remove them from this package + localparam XLEN = cva6_config_pkg::CVA6ConfigXlen; + localparam PLEN = (XLEN == 32) ? 34 : 56; + + // -------------------- + // Privilege Spec + // -------------------- + typedef enum logic [1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_HS = 2'b10, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 + } priv_lvl_t; + + // type which holds xlen + typedef enum logic [1:0] { + XLEN_32 = 2'b01, + XLEN_64 = 2'b10, + XLEN_128 = 2'b11 + } xlen_e; + + typedef enum logic [1:0] { + Off = 2'b00, + Initial = 2'b01, + Clean = 2'b10, + Dirty = 2'b11 + } xs_t; + + typedef struct packed { + logic sd; // signal dirty state - read-only + logic [62:34] wpri6; // writes preserved reads ignored + xlen_e uxl; // variable user mode xlen - hardwired to zero + logic [11:0] wpri5; // writes preserved reads ignored + logic mxr; // make executable readable + logic sum; // permit supervisor user memory access + logic wpri4; // writes preserved reads ignored + xs_t xs; // extension register - hardwired to zero + xs_t fs; // floating point extension register + logic [1:0] wpri3; // writes preserved reads ignored + xs_t vs; // vector extension register + logic spp; // holds the previous privilege mode up to supervisor + logic wpri2; // writes preserved reads ignored + logic mpie; // machine interrupts enable bit active prior to trap + logic ube; // UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1) + logic spie; // supervisor interrupts enable bit active prior to trap + logic [2:0] wpri1; // writes preserved reads ignored + logic sie; // supervisor interrupts enable + logic wpri0; // writes preserved reads ignored + } sstatus_rv_t; + + typedef struct packed { + logic [63:34] wpri4; // writes preserved reads ignored + xlen_e vsxl; // variable virtual supervisor mode xlen - hardwired to zero + logic [8:0] wpri3; // floating point extension register + logic vtsr; // virtual trap sret + logic vtw; // virtual time wait + logic vtvm; // virtual trap virtual memory + logic [1:0] wpri2; // writes preserved reads ignored + logic [5:0] vgein; // virtual guest external interrupt number + logic [1:0] wpri1; // writes preserved reads ignored + logic hu; // virtual-machine load/store instructions enable in U-mode + logic spvp; // supervisor previous virtual privilege + logic spv; // supervisor previous virtualization mode + logic gva; // variable set when trap writes to stval + logic vsbe; // endianness of explicit memory accesses made from VS-mode + logic [4:0] wpri0; // writes preserved reads ignored + } hstatus_rv_t; + + typedef struct packed { + logic sd; // signal dirty state - read-only + logic [62:40] wpri4; // writes preserved reads ignored + logic mpv; // machine previous virtualization mode + logic gva; // variable set when trap writes to stval + logic mbe; // endianness memory accesses made from M-mode + logic sbe; // endianness memory accesses made from S-mode + xlen_e sxl; // variable supervisor mode xlen - hardwired to zero + xlen_e uxl; // variable user mode xlen - hardwired to zero + logic [8:0] wpri3; // writes preserved reads ignored + logic tsr; // trap sret + logic tw; // time wait + logic tvm; // trap virtual memory + logic mxr; // make executable readable + logic sum; // permit supervisor user memory access + logic mprv; // modify privilege - privilege level for ld/st + xs_t xs; // extension register - hardwired to zero + xs_t fs; // floating point extension register + priv_lvl_t mpp; // holds the previous privilege mode up to machine + xs_t vs; // vector extension register + logic spp; // holds the previous privilege mode up to supervisor + logic mpie; // machine interrupts enable bit active prior to trap + logic ube; // UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1) + logic spie; // supervisor interrupts enable bit active prior to trap + logic wpri2; // writes preserved reads ignored + logic mie; // machine interrupts enable + logic wpri1; // writes preserved reads ignored + logic sie; // supervisor interrupts enable + logic wpri0; // writes preserved reads ignored + } mstatus_rv_t; + + typedef struct packed { + logic stce; // not implemented - requires Sctc extension + logic pbmte; // not implemented - requires Svpbmt extension + logic [61:8] wpri1; // writes preserved reads ignored + logic cbze; // not implemented - requires Zicboz extension + logic cbcfe; // not implemented - requires Zicbom extension + logic [1:0] cbie; // not implemented - requires Zicbom extension + logic [2:0] wpri0; // writes preserved reads ignored + logic fiom; // fence of I/O implies memory + } envcfg_rv_t; + + // -------------------- + // Instruction Types + // -------------------- + typedef struct packed { + logic [31:25] funct7; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; + } rtype_t; + + typedef struct packed { + logic [31:27] rs3; + logic [26:25] funct2; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; + } r4type_t; + + typedef struct packed { + logic [31:27] funct5; + logic [26:25] fmt; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] rm; + logic [11:7] rd; + logic [6:0] opcode; + } rftype_t; // floating-point + + typedef struct packed { + logic [31:30] funct2; + logic [29:25] vecfltop; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:14] repl; + logic [13:12] vfmt; + logic [11:7] rd; + logic [6:0] opcode; + } rvftype_t; // vectorial floating-point + + typedef struct packed { + logic [31:20] imm; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; + } itype_t; + + typedef struct packed { + logic [31:25] imm; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] imm0; + logic [6:0] opcode; + } stype_t; + + typedef struct packed { + logic [31:12] imm; + logic [11:7] rd; + logic [6:0] opcode; + } utype_t; + + // atomic instructions + typedef struct packed { + logic [31:27] funct5; + logic aq; + logic rl; + logic [24:20] rs2; + logic [19:15] rs1; + logic [14:12] funct3; + logic [11:7] rd; + logic [6:0] opcode; + } atype_t; + + typedef union packed { + logic [31:0] instr; + rtype_t rtype; + r4type_t r4type; + rftype_t rftype; + rvftype_t rvftype; + itype_t itype; + stype_t stype; + utype_t utype; + atype_t atype; + } instruction_t; + + // -------------------- + // Opcodes + // -------------------- + // RV32/64G listings: + // Quadrant 0 + localparam OpcodeLoad = 7'b00_000_11; + localparam OpcodeLoadFp = 7'b00_001_11; + localparam OpcodeCustom0 = 7'b00_010_11; + localparam OpcodeMiscMem = 7'b00_011_11; + localparam OpcodeOpImm = 7'b00_100_11; + localparam OpcodeAuipc = 7'b00_101_11; + localparam OpcodeOpImm32 = 7'b00_110_11; + // Quadrant 1 + localparam OpcodeStore = 7'b01_000_11; + localparam OpcodeStoreFp = 7'b01_001_11; + localparam OpcodeCustom1 = 7'b01_010_11; + localparam OpcodeAmo = 7'b01_011_11; + localparam OpcodeOp = 7'b01_100_11; + localparam OpcodeLui = 7'b01_101_11; + localparam OpcodeOp32 = 7'b01_110_11; + // Quadrant 2 + localparam OpcodeMadd = 7'b10_000_11; + localparam OpcodeMsub = 7'b10_001_11; + localparam OpcodeNmsub = 7'b10_010_11; + localparam OpcodeNmadd = 7'b10_011_11; + localparam OpcodeOpFp = 7'b10_100_11; + localparam OpcodeVec = 7'b10_101_11; + localparam OpcodeCustom2 = 7'b10_110_11; + // Quadrant 3 + localparam OpcodeBranch = 7'b11_000_11; + localparam OpcodeJalr = 7'b11_001_11; + localparam OpcodeRsrvd2 = 7'b11_010_11; + localparam OpcodeJal = 7'b11_011_11; + localparam OpcodeSystem = 7'b11_100_11; + localparam OpcodeRsrvd3 = 7'b11_101_11; + localparam OpcodeCustom3 = 7'b11_110_11; + + // RV64C/RV32C listings: + // Quadrant 0 + localparam OpcodeC0 = 2'b00; + localparam OpcodeC0Addi4spn = 3'b000; + localparam OpcodeC0Fld = 3'b001; + localparam OpcodeC0Lw = 3'b010; + localparam OpcodeC0Ld = 3'b011; + localparam OpcodeC0Zcb = 3'b100; + localparam OpcodeC0Fsd = 3'b101; + localparam OpcodeC0Sw = 3'b110; + localparam OpcodeC0Sd = 3'b111; + // Quadrant 1 + localparam OpcodeC1 = 2'b01; + localparam OpcodeC1Addi = 3'b000; + localparam OpcodeC1Addiw = 3'b001; //for RV64I only + localparam OpcodeC1Jal = 3'b001; //for RV32I only + localparam OpcodeC1Li = 3'b010; + localparam OpcodeC1LuiAddi16sp = 3'b011; + localparam OpcodeC1MiscAlu = 3'b100; + localparam OpcodeC1J = 3'b101; + localparam OpcodeC1Beqz = 3'b110; + localparam OpcodeC1Bnez = 3'b111; + // Quadrant 2 + localparam OpcodeC2 = 2'b10; + localparam OpcodeC2Slli = 3'b000; + localparam OpcodeC2Fldsp = 3'b001; + localparam OpcodeC2Lwsp = 3'b010; + localparam OpcodeC2Ldsp = 3'b011; + localparam OpcodeC2JalrMvAdd = 3'b100; + localparam OpcodeC2Fsdsp = 3'b101; + localparam OpcodeC2Swsp = 3'b110; + localparam OpcodeC2Sdsp = 3'b111; + + // ---------------------- + // Virtual Memory + // ---------------------- + // memory management, pte for sv39 + typedef struct packed { + logic [9:0] reserved; + logic [44-1:0] ppn; // PPN length for + logic [1:0] rsw; + logic d; + logic a; + logic g; + logic u; + logic x; + logic w; + logic r; + logic v; + } pte_t; + + // memory management, pte for sv32 + typedef struct packed { + logic [22-1:0] ppn; // PPN length for + logic [1:0] rsw; + logic d; + logic a; + logic g; + logic u; + logic x; + logic w; + logic r; + logic v; + } pte_sv32_t; + + // ---------------------- + // Exception Cause Codes + // ---------------------- + localparam logic [XLEN-1:0] INSTR_ADDR_MISALIGNED = 0; + localparam logic [XLEN-1:0] INSTR_ACCESS_FAULT = 1; // Illegal access as governed by PMPs and PMAs + localparam logic [XLEN-1:0] ILLEGAL_INSTR = 2; + localparam logic [XLEN-1:0] BREAKPOINT = 3; + localparam logic [XLEN-1:0] LD_ADDR_MISALIGNED = 4; + localparam logic [XLEN-1:0] LD_ACCESS_FAULT = 5; // Illegal access as governed by PMPs and PMAs + localparam logic [XLEN-1:0] ST_ADDR_MISALIGNED = 6; + localparam logic [XLEN-1:0] ST_ACCESS_FAULT = 7; // Illegal access as governed by PMPs and PMAs + localparam logic [XLEN-1:0] ENV_CALL_UMODE = 8; // environment call from user mode or virtual user mode + localparam logic [XLEN-1:0] ENV_CALL_SMODE = 9; // environment call from hypervisor-extended supervisor mode + localparam logic [XLEN-1:0] ENV_CALL_VSMODE = 10; // environment call from virtual supervisor mode + localparam logic [XLEN-1:0] ENV_CALL_MMODE = 11; // environment call from machine mode + localparam logic [XLEN-1:0] INSTR_PAGE_FAULT = 12; // Instruction page fault + localparam logic [XLEN-1:0] LOAD_PAGE_FAULT = 13; // Load page fault + localparam logic [XLEN-1:0] STORE_PAGE_FAULT = 15; // Store page fault + localparam logic [XLEN-1:0] INSTR_GUEST_PAGE_FAULT = 20; // Instruction guest-page fault + localparam logic [XLEN-1:0] LOAD_GUEST_PAGE_FAULT = 21; // Load guest-page fault + localparam logic [XLEN-1:0] VIRTUAL_INSTRUCTION = 22; // virtual instruction + localparam logic [XLEN-1:0] STORE_GUEST_PAGE_FAULT = 23; // Store guest-page fault + localparam logic [XLEN-1:0] DEBUG_REQUEST = 24; // Debug request + + localparam int unsigned IRQ_S_SOFT = 1; + localparam int unsigned IRQ_VS_SOFT = 2; + localparam int unsigned IRQ_M_SOFT = 3; + localparam int unsigned IRQ_S_TIMER = 5; + localparam int unsigned IRQ_VS_TIMER = 6; + localparam int unsigned IRQ_M_TIMER = 7; + localparam int unsigned IRQ_S_EXT = 9; + localparam int unsigned IRQ_VS_EXT = 10; + localparam int unsigned IRQ_M_EXT = 11; + localparam int unsigned IRQ_HS_EXT = 12; + + localparam logic [31:0] MIP_SSIP = 1 << IRQ_S_SOFT; + localparam logic [31:0] MIP_VSSIP = 1 << IRQ_VS_SOFT; + localparam logic [31:0] MIP_MSIP = 1 << IRQ_M_SOFT; + localparam logic [31:0] MIP_STIP = 1 << IRQ_S_TIMER; + localparam logic [31:0] MIP_VSTIP = 1 << IRQ_VS_TIMER; + localparam logic [31:0] MIP_MTIP = 1 << IRQ_M_TIMER; + localparam logic [31:0] MIP_SEIP = 1 << IRQ_S_EXT; + localparam logic [31:0] MIP_VSEIP = 1 << IRQ_VS_EXT; + localparam logic [31:0] MIP_MEIP = 1 << IRQ_M_EXT; + localparam logic [31:0] MIP_SGEIP = 1 << IRQ_HS_EXT; + + // ---------------------- + // PseudoInstructions Codes + // ---------------------- + localparam logic [31:0] READ_32_PSEUDOINSTRUCTION = 32'h00002000; + localparam logic [31:0] WRITE_32_PSEUDOINSTRUCTION = 32'h00002020; + localparam logic [31:0] READ_64_PSEUDOINSTRUCTION = 32'h00003000; + localparam logic [31:0] WRITE_64_PSEUDOINSTRUCTION = 32'h00003020; + + // ----- + // CSRs + // ----- + typedef enum logic [11:0] { + // Floating-Point CSRs + CSR_FFLAGS = 12'h001, + CSR_FRM = 12'h002, + CSR_FCSR = 12'h003, + //jvt + CSR_JVT = 12'h017, + CSR_FTRAN = 12'h800, + // Vector CSRs + CSR_VSTART = 12'h008, + CSR_VXSAT = 12'h009, + CSR_VXRM = 12'h00A, + CSR_VCSR = 12'h00F, + CSR_VL = 12'hC20, + CSR_VTYPE = 12'hC21, + CSR_VLENB = 12'hC22, + // Virtual Supervisor Mode CSRs + CSR_VSSTATUS = 12'h200, + CSR_VSIE = 12'h204, + CSR_VSTVEC = 12'h205, + CSR_VSSCRATCH = 12'h240, + CSR_VSEPC = 12'h241, + CSR_VSCAUSE = 12'h242, + CSR_VSTVAL = 12'h243, + CSR_VSIP = 12'h244, + CSR_VSATP = 12'h280, + // Supervisor Mode CSRs + CSR_SSTATUS = 12'h100, + CSR_SIE = 12'h104, + CSR_STVEC = 12'h105, + CSR_SCOUNTEREN = 12'h106, + CSR_SENVCFG = 12'h10A, + CSR_SSCRATCH = 12'h140, + CSR_SEPC = 12'h141, + CSR_SCAUSE = 12'h142, + CSR_STVAL = 12'h143, + CSR_SIP = 12'h144, + CSR_SATP = 12'h180, + // Hypervisor-extended Supervisor Mode CSRs + CSR_HSTATUS = 12'h600, + CSR_HEDELEG = 12'h602, + CSR_HIDELEG = 12'h603, + CSR_HIE = 12'h604, + CSR_HCOUNTEREN = 12'h606, + CSR_HGEIE = 12'h607, + CSR_HTVAL = 12'h643, + CSR_HIP = 12'h644, + CSR_HVIP = 12'h645, + CSR_HTINST = 12'h64A, + CSR_HGEIP = 12'hE12, + CSR_HENVCFG = 12'h60A, + CSR_HENVCFGH = 12'h61A, + CSR_HGATP = 12'h680, + CSR_HCONTEXT = 12'h6A8, + CSR_HTIMEDELTA = 12'h605, + CSR_HTIMEDELTAH = 12'h615, + // Machine Mode CSRs + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MEDELEG = 12'h302, + CSR_MIDELEG = 12'h303, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + CSR_MCOUNTEREN = 12'h306, + CSR_MSTATUSH = 12'h310, + CSR_MCOUNTINHIBIT = 12'h320, + CSR_MHPM_EVENT_3 = 12'h323, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_4 = 12'h324, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_5 = 12'h325, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_6 = 12'h326, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_7 = 12'h327, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_8 = 12'h328, //Machine performance monitoring Event Selector + CSR_MHPM_EVENT_9 = 12'h329, //Reserved + CSR_MHPM_EVENT_10 = 12'h32A, //Reserved + CSR_MHPM_EVENT_11 = 12'h32B, //Reserved + CSR_MHPM_EVENT_12 = 12'h32C, //Reserved + CSR_MHPM_EVENT_13 = 12'h32D, //Reserved + CSR_MHPM_EVENT_14 = 12'h32E, //Reserved + CSR_MHPM_EVENT_15 = 12'h32F, //Reserved + CSR_MHPM_EVENT_16 = 12'h330, //Reserved + CSR_MHPM_EVENT_17 = 12'h331, //Reserved + CSR_MHPM_EVENT_18 = 12'h332, //Reserved + CSR_MHPM_EVENT_19 = 12'h333, //Reserved + CSR_MHPM_EVENT_20 = 12'h334, //Reserved + CSR_MHPM_EVENT_21 = 12'h335, //Reserved + CSR_MHPM_EVENT_22 = 12'h336, //Reserved + CSR_MHPM_EVENT_23 = 12'h337, //Reserved + CSR_MHPM_EVENT_24 = 12'h338, //Reserved + CSR_MHPM_EVENT_25 = 12'h339, //Reserved + CSR_MHPM_EVENT_26 = 12'h33A, //Reserved + CSR_MHPM_EVENT_27 = 12'h33B, //Reserved + CSR_MHPM_EVENT_28 = 12'h33C, //Reserved + CSR_MHPM_EVENT_29 = 12'h33D, //Reserved + CSR_MHPM_EVENT_30 = 12'h33E, //Reserved + CSR_MHPM_EVENT_31 = 12'h33F, //Reserved + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + CSR_MTINST = 12'h34A, + CSR_MTVAL2 = 12'h34B, + CSR_MENVCFG = 12'h30A, + CSR_MENVCFGH = 12'h31A, + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPCFG1 = 12'h3A1, + CSR_PMPCFG2 = 12'h3A2, + CSR_PMPCFG3 = 12'h3A3, + CSR_PMPCFG4 = 12'h3A4, + CSR_PMPCFG5 = 12'h3A5, + CSR_PMPCFG6 = 12'h3A6, + CSR_PMPCFG7 = 12'h3A7, + CSR_PMPCFG8 = 12'h3A8, + CSR_PMPCFG9 = 12'h3A9, + CSR_PMPCFG10 = 12'h3AA, + CSR_PMPCFG11 = 12'h3AB, + CSR_PMPCFG12 = 12'h3AC, + CSR_PMPCFG13 = 12'h3AD, + CSR_PMPCFG14 = 12'h3AE, + CSR_PMPCFG15 = 12'h3AF, + CSR_PMPADDR0 = 12'h3B0, + CSR_PMPADDR1 = 12'h3B1, + CSR_PMPADDR2 = 12'h3B2, + CSR_PMPADDR3 = 12'h3B3, + CSR_PMPADDR4 = 12'h3B4, + CSR_PMPADDR5 = 12'h3B5, + CSR_PMPADDR6 = 12'h3B6, + CSR_PMPADDR7 = 12'h3B7, + CSR_PMPADDR8 = 12'h3B8, + CSR_PMPADDR9 = 12'h3B9, + CSR_PMPADDR10 = 12'h3BA, + CSR_PMPADDR11 = 12'h3BB, + CSR_PMPADDR12 = 12'h3BC, + CSR_PMPADDR13 = 12'h3BD, + CSR_PMPADDR14 = 12'h3BE, + CSR_PMPADDR15 = 12'h3BF, + CSR_PMPADDR16 = 12'h3C0, + CSR_PMPADDR17 = 12'h3C1, + CSR_PMPADDR18 = 12'h3C2, + CSR_PMPADDR19 = 12'h3C3, + CSR_PMPADDR20 = 12'h3C4, + CSR_PMPADDR21 = 12'h3C5, + CSR_PMPADDR22 = 12'h3C6, + CSR_PMPADDR23 = 12'h3C7, + CSR_PMPADDR24 = 12'h3C8, + CSR_PMPADDR25 = 12'h3C9, + CSR_PMPADDR26 = 12'h3CA, + CSR_PMPADDR27 = 12'h3CB, + CSR_PMPADDR28 = 12'h3CC, + CSR_PMPADDR29 = 12'h3CD, + CSR_PMPADDR30 = 12'h3CE, + CSR_PMPADDR31 = 12'h3CF, + CSR_PMPADDR32 = 12'h3D0, + CSR_PMPADDR33 = 12'h3D1, + CSR_PMPADDR34 = 12'h3D2, + CSR_PMPADDR35 = 12'h3D3, + CSR_PMPADDR36 = 12'h3D4, + CSR_PMPADDR37 = 12'h3D5, + CSR_PMPADDR38 = 12'h3D6, + CSR_PMPADDR39 = 12'h3D7, + CSR_PMPADDR40 = 12'h3D8, + CSR_PMPADDR41 = 12'h3D9, + CSR_PMPADDR42 = 12'h3DA, + CSR_PMPADDR43 = 12'h3DB, + CSR_PMPADDR44 = 12'h3DC, + CSR_PMPADDR45 = 12'h3DD, + CSR_PMPADDR46 = 12'h3DE, + CSR_PMPADDR47 = 12'h3DF, + CSR_PMPADDR48 = 12'h3E0, + CSR_PMPADDR49 = 12'h3E1, + CSR_PMPADDR50 = 12'h3E2, + CSR_PMPADDR51 = 12'h3E3, + CSR_PMPADDR52 = 12'h3E4, + CSR_PMPADDR53 = 12'h3E5, + CSR_PMPADDR54 = 12'h3E6, + CSR_PMPADDR55 = 12'h3E7, + CSR_PMPADDR56 = 12'h3E8, + CSR_PMPADDR57 = 12'h3E9, + CSR_PMPADDR58 = 12'h3EA, + CSR_PMPADDR59 = 12'h3EB, + CSR_PMPADDR60 = 12'h3EC, + CSR_PMPADDR61 = 12'h3ED, + CSR_PMPADDR62 = 12'h3EE, + CSR_PMPADDR63 = 12'h3EF, + CSR_MVENDORID = 12'hF11, + CSR_MARCHID = 12'hF12, + CSR_MIMPID = 12'hF13, + CSR_MHARTID = 12'hF14, + CSR_MCONFIGPTR = 12'hF15, + CSR_MCYCLE = 12'hB00, + CSR_MCYCLEH = 12'hB80, + CSR_MINSTRET = 12'hB02, + CSR_MINSTRETH = 12'hB82, + //Performance Counters + CSR_MHPM_COUNTER_3 = 12'hB03, + CSR_MHPM_COUNTER_4 = 12'hB04, + CSR_MHPM_COUNTER_5 = 12'hB05, + CSR_MHPM_COUNTER_6 = 12'hB06, + CSR_MHPM_COUNTER_7 = 12'hB07, + CSR_MHPM_COUNTER_8 = 12'hB08, + CSR_MHPM_COUNTER_9 = 12'hB09, // reserved + CSR_MHPM_COUNTER_10 = 12'hB0A, // reserved + CSR_MHPM_COUNTER_11 = 12'hB0B, // reserved + CSR_MHPM_COUNTER_12 = 12'hB0C, // reserved + CSR_MHPM_COUNTER_13 = 12'hB0D, // reserved + CSR_MHPM_COUNTER_14 = 12'hB0E, // reserved + CSR_MHPM_COUNTER_15 = 12'hB0F, // reserved + CSR_MHPM_COUNTER_16 = 12'hB10, // reserved + CSR_MHPM_COUNTER_17 = 12'hB11, // reserved + CSR_MHPM_COUNTER_18 = 12'hB12, // reserved + CSR_MHPM_COUNTER_19 = 12'hB13, // reserved + CSR_MHPM_COUNTER_20 = 12'hB14, // reserved + CSR_MHPM_COUNTER_21 = 12'hB15, // reserved + CSR_MHPM_COUNTER_22 = 12'hB16, // reserved + CSR_MHPM_COUNTER_23 = 12'hB17, // reserved + CSR_MHPM_COUNTER_24 = 12'hB18, // reserved + CSR_MHPM_COUNTER_25 = 12'hB19, // reserved + CSR_MHPM_COUNTER_26 = 12'hB1A, // reserved + CSR_MHPM_COUNTER_27 = 12'hB1B, // reserved + CSR_MHPM_COUNTER_28 = 12'hB1C, // reserved + CSR_MHPM_COUNTER_29 = 12'hB1D, // reserved + CSR_MHPM_COUNTER_30 = 12'hB1E, // reserved + CSR_MHPM_COUNTER_31 = 12'hB1F, // reserved + CSR_MHPM_COUNTER_3H = 12'hB83, + CSR_MHPM_COUNTER_4H = 12'hB84, + CSR_MHPM_COUNTER_5H = 12'hB85, + CSR_MHPM_COUNTER_6H = 12'hB86, + CSR_MHPM_COUNTER_7H = 12'hB87, + CSR_MHPM_COUNTER_8H = 12'hB88, + CSR_MHPM_COUNTER_9H = 12'hB89, // reserved + CSR_MHPM_COUNTER_10H = 12'hB8A, // reserved + CSR_MHPM_COUNTER_11H = 12'hB8B, // reserved + CSR_MHPM_COUNTER_12H = 12'hB8C, // reserved + CSR_MHPM_COUNTER_13H = 12'hB8D, // reserved + CSR_MHPM_COUNTER_14H = 12'hB8E, // reserved + CSR_MHPM_COUNTER_15H = 12'hB8F, // reserved + CSR_MHPM_COUNTER_16H = 12'hB90, // reserved + CSR_MHPM_COUNTER_17H = 12'hB91, // reserved + CSR_MHPM_COUNTER_18H = 12'hB92, // reserved + CSR_MHPM_COUNTER_19H = 12'hB93, // reserved + CSR_MHPM_COUNTER_20H = 12'hB94, // reserved + CSR_MHPM_COUNTER_21H = 12'hB95, // reserved + CSR_MHPM_COUNTER_22H = 12'hB96, // reserved + CSR_MHPM_COUNTER_23H = 12'hB97, // reserved + CSR_MHPM_COUNTER_24H = 12'hB98, // reserved + CSR_MHPM_COUNTER_25H = 12'hB99, // reserved + CSR_MHPM_COUNTER_26H = 12'hB9A, // reserved + CSR_MHPM_COUNTER_27H = 12'hB9B, // reserved + CSR_MHPM_COUNTER_28H = 12'hB9C, // reserved + CSR_MHPM_COUNTER_29H = 12'hB9D, // reserved + CSR_MHPM_COUNTER_30H = 12'hB9E, // reserved + CSR_MHPM_COUNTER_31H = 12'hB9F, // reserved + // Cache Control (platform specifc) + CSR_DCACHE = 12'h7C1, + CSR_ICACHE = 12'h7C0, + // Accelerator memory consistency (platform specific) + CSR_ACC_CONS = 12'h7C2, + // Triggers + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_TINFO = 12'h7A4, + // Debug CSR + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + CSR_DSCRATCH0 = 12'h7b2, // optional + CSR_DSCRATCH1 = 12'h7b3, // optional + // Counters and Timers from Zicntr extension (User Mode - R/O Shadows) + CSR_CYCLE = 12'hC00, + CSR_CYCLEH = 12'hC80, + CSR_TIME = 12'hC01, + CSR_TIMEH = 12'hC81, + CSR_INSTRET = 12'hC02, + CSR_INSTRETH = 12'hC82, + // Performance counters from Zihpm extension (User Mode - R/O Shadows) + CSR_HPM_COUNTER_3 = 12'hC03, + CSR_HPM_COUNTER_4 = 12'hC04, + CSR_HPM_COUNTER_5 = 12'hC05, + CSR_HPM_COUNTER_6 = 12'hC06, + CSR_HPM_COUNTER_7 = 12'hC07, + CSR_HPM_COUNTER_8 = 12'hC08, + CSR_HPM_COUNTER_9 = 12'hC09, // reserved + CSR_HPM_COUNTER_10 = 12'hC0A, // reserved + CSR_HPM_COUNTER_11 = 12'hC0B, // reserved + CSR_HPM_COUNTER_12 = 12'hC0C, // reserved + CSR_HPM_COUNTER_13 = 12'hC0D, // reserved + CSR_HPM_COUNTER_14 = 12'hC0E, // reserved + CSR_HPM_COUNTER_15 = 12'hC0F, // reserved + CSR_HPM_COUNTER_16 = 12'hC10, // reserved + CSR_HPM_COUNTER_17 = 12'hC11, // reserved + CSR_HPM_COUNTER_18 = 12'hC12, // reserved + CSR_HPM_COUNTER_19 = 12'hC13, // reserved + CSR_HPM_COUNTER_20 = 12'hC14, // reserved + CSR_HPM_COUNTER_21 = 12'hC15, // reserved + CSR_HPM_COUNTER_22 = 12'hC16, // reserved + CSR_HPM_COUNTER_23 = 12'hC17, // reserved + CSR_HPM_COUNTER_24 = 12'hC18, // reserved + CSR_HPM_COUNTER_25 = 12'hC19, // reserved + CSR_HPM_COUNTER_26 = 12'hC1A, // reserved + CSR_HPM_COUNTER_27 = 12'hC1B, // reserved + CSR_HPM_COUNTER_28 = 12'hC1C, // reserved + CSR_HPM_COUNTER_29 = 12'hC1D, // reserved + CSR_HPM_COUNTER_30 = 12'hC1E, // reserved + CSR_HPM_COUNTER_31 = 12'hC1F, // reserved + CSR_HPM_COUNTER_3H = 12'hC83, + CSR_HPM_COUNTER_4H = 12'hC84, + CSR_HPM_COUNTER_5H = 12'hC85, + CSR_HPM_COUNTER_6H = 12'hC86, + CSR_HPM_COUNTER_7H = 12'hC87, + CSR_HPM_COUNTER_8H = 12'hC88, + CSR_HPM_COUNTER_9H = 12'hC89, // reserved + CSR_HPM_COUNTER_10H = 12'hC8A, // reserved + CSR_HPM_COUNTER_11H = 12'hC8B, // reserved + CSR_HPM_COUNTER_12H = 12'hC8C, // reserved + CSR_HPM_COUNTER_13H = 12'hC8D, // reserved + CSR_HPM_COUNTER_14H = 12'hC8E, // reserved + CSR_HPM_COUNTER_15H = 12'hC8F, // reserved + CSR_HPM_COUNTER_16H = 12'hC90, // reserved + CSR_HPM_COUNTER_17H = 12'hC91, // reserved + CSR_HPM_COUNTER_18H = 12'hC92, // reserved + CSR_HPM_COUNTER_19H = 12'hC93, // reserved + CSR_HPM_COUNTER_20H = 12'hC94, // reserved + CSR_HPM_COUNTER_21H = 12'hC95, // reserved + CSR_HPM_COUNTER_22H = 12'hC96, // reserved + CSR_HPM_COUNTER_23H = 12'hC97, // reserved + CSR_HPM_COUNTER_24H = 12'hC98, // reserved + CSR_HPM_COUNTER_25H = 12'hC99, // reserved + CSR_HPM_COUNTER_26H = 12'hC9A, // reserved + CSR_HPM_COUNTER_27H = 12'hC9B, // reserved + CSR_HPM_COUNTER_28H = 12'hC9C, // reserved + CSR_HPM_COUNTER_29H = 12'hC9D, // reserved + CSR_HPM_COUNTER_30H = 12'hC9E, // reserved + CSR_HPM_COUNTER_31H = 12'hC9F // reserved + } csr_reg_t; + + localparam logic [63:0] SSTATUS_UIE = 'h00000001; + localparam logic [63:0] SSTATUS_SIE = 'h00000002; + localparam logic [63:0] SSTATUS_SPIE = 'h00000020; + localparam logic [63:0] SSTATUS_SPP = 'h00000100; + localparam logic [63:0] SSTATUS_FS = 'h00006000; + localparam logic [63:0] SSTATUS_XS = 'h00018000; + localparam logic [63:0] SSTATUS_SUM = 'h00040000; + localparam logic [63:0] SSTATUS_MXR = 'h00080000; + localparam logic [63:0] SSTATUS_UPIE = 'h00000010; + localparam logic [63:0] SSTATUS_UXL = 64'h0000000300000000; + // CSR Bit Implementation Masks + + function automatic logic [63:0] sstatus_sd(logic IS_XLEN64); + return {IS_XLEN64, 31'h00000000, ~IS_XLEN64, 31'h00000000}; + endfunction + + localparam logic [63:0] HSTATUS_VSBE = 'h00000020; + localparam logic [63:0] HSTATUS_GVA = 'h00000040; + localparam logic [63:0] HSTATUS_SPV = 'h00000080; + localparam logic [63:0] HSTATUS_SPVP = 'h00000100; + localparam logic [63:0] HSTATUS_HU = 'h00000200; + localparam logic [63:0] HSTATUS_VGEIN = 'h0003F000; + localparam logic [63:0] HSTATUS_VTVM = 'h00100000; + localparam logic [63:0] HSTATUS_VTW = 'h00200000; + localparam logic [63:0] HSTATUS_VTSR = 'h00400000; + localparam logic [63:0] HSTATUS_VSXL = 64'h0000000300000000; + + localparam logic [63:0] MSTATUS_UIE = 'h00000001; + localparam logic [63:0] MSTATUS_SIE = 'h00000002; + localparam logic [63:0] MSTATUS_HIE = 'h00000004; + localparam logic [63:0] MSTATUS_MIE = 'h00000008; + localparam logic [63:0] MSTATUS_UPIE = 'h00000010; + localparam logic [63:0] MSTATUS_SPIE = 'h00000020; + localparam logic [63:0] MSTATUS_HPIE = 'h00000040; + localparam logic [63:0] MSTATUS_MPIE = 'h00000080; + localparam logic [63:0] MSTATUS_SPP = 'h00000100; + localparam logic [63:0] MSTATUS_HPP = 'h00000600; + localparam logic [63:0] MSTATUS_MPP = 'h00001800; + localparam logic [63:0] MSTATUS_FS = 'h00006000; + localparam logic [63:0] MSTATUS_XS = 'h00018000; + localparam logic [63:0] MSTATUS_MPRV = 'h00020000; + localparam logic [63:0] MSTATUS_SUM = 'h00040000; + localparam logic [63:0] MSTATUS_MXR = 'h00080000; + localparam logic [63:0] MSTATUS_TVM = 'h00100000; + localparam logic [63:0] MSTATUS_TW = 'h00200000; + localparam logic [63:0] MSTATUS_TSR = 'h00400000; + function automatic logic [63:0] mstatus_uxl(logic IS_XLEN64); + return {30'h0000000, IS_XLEN64, IS_XLEN64, 32'h00000000}; + endfunction + function automatic logic [63:0] mstatus_sxl(logic IS_XLEN64); + return {28'h0000000, IS_XLEN64, IS_XLEN64, 34'h00000000}; + endfunction + function automatic logic [63:0] mstatus_sd(logic IS_XLEN64); + return {IS_XLEN64, 31'h00000000, ~IS_XLEN64, 31'h00000000}; + endfunction + + localparam logic [63:0] MENVCFG_FIOM = 'h00000001; + localparam logic [63:0] MENVCFG_CBIE = 'h00000030; + localparam logic [63:0] MENVCFG_CBFE = 'h00000040; + localparam logic [63:0] MENVCFG_CBZE = 'h00000080; + localparam logic [63:0] MENVCFG_PBMTE = 64'h4000000000000000; + localparam logic [63:0] MENVCFG_STCE = 64'h8000000000000000; + + + + typedef enum logic [2:0] { + CSRRW = 3'h1, + CSRRS = 3'h2, + CSRRC = 3'h3, + CSRRWI = 3'h5, + CSRRSI = 3'h6, + CSRRCI = 3'h7 + } csr_op_t; + + // decoded CSR address + typedef struct packed { + logic [1:0] rw; + priv_lvl_t priv_lvl; + logic [7:0] address; + } csr_addr_t; + + typedef union packed { + csr_reg_t address; + csr_addr_t csr_decode; + } csr_t; + + // Floating-Point control and status register (32-bit!) + typedef struct packed { + logic [31:15] reserved; // reserved for L extension, return 0 otherwise + logic [6:0] fprec; // div/sqrt precision control + logic [2:0] frm; // float rounding mode + logic [4:0] fflags; // float exception flags + } fcsr_t; + + // PMP + typedef enum logic [1:0] { + OFF = 2'b00, + TOR = 2'b01, + NA4 = 2'b10, + NAPOT = 2'b11 + } pmp_addr_mode_t; + + // PMP Access Type + typedef enum logic [2:0] { + ACCESS_NONE = 3'b000, + ACCESS_READ = 3'b001, + ACCESS_WRITE = 3'b010, + ACCESS_EXEC = 3'b100 + } pmp_access_t; + + typedef struct packed { + logic x; + logic w; + logic r; + } pmpcfg_access_t; + + // packed struct of a PMP configuration register (8bit) + typedef struct packed { + logic locked; // lock this configuration + logic [1:0] reserved; + pmp_addr_mode_t addr_mode; // Off, TOR, NA4, NAPOT + pmpcfg_access_t access_type; + } pmpcfg_t; + + // ----- + // Debug + // ----- + typedef struct packed { + logic [31:28] xdebugver; + logic [27:18] zero2; + logic ebreakvs; + logic ebreakvu; + logic ebreakm; + logic zero1; + logic ebreaks; + logic ebreaku; + logic stepie; + logic stopcount; + logic stoptime; + logic [8:6] cause; + logic v; + logic mprven; + logic nmip; + logic step; + priv_lvl_t prv; + } dcsr_t; + + // Instruction Generation *incomplete* + function automatic logic [31:0] jal(logic [4:0] rd, logic [20:0] imm); + // OpCode Jal + return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f}; + endfunction + + function automatic logic [31:0] jalr(logic [4:0] rd, logic [4:0] rs1, logic [11:0] offset); + // OpCode Jal + return {offset[11:0], rs1, 3'b0, rd, 7'h67}; + endfunction + + function automatic logic [31:0] andi(logic [4:0] rd, logic [4:0] rs1, logic [11:0] imm); + // OpCode andi + return {imm[11:0], rs1, 3'h7, rd, 7'h13}; + endfunction + + function automatic logic [31:0] slli(logic [4:0] rd, logic [4:0] rs1, logic [5:0] shamt); + // OpCode slli + return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13}; + endfunction + + function automatic logic [31:0] srli(logic [4:0] rd, logic [4:0] rs1, logic [5:0] shamt); + // OpCode srli + return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13}; + endfunction + + function automatic logic [31:0] load(logic [2:0] size, logic [4:0] dest, logic [4:0] base, + logic [11:0] offset); + // OpCode Load + return {offset[11:0], base, size, dest, 7'h03}; + endfunction + + function automatic logic [31:0] auipc(logic [4:0] rd, logic [20:0] imm); + // OpCode Auipc + return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17}; + endfunction + + function automatic logic [31:0] store(logic [2:0] size, logic [4:0] src, logic [4:0] base, + logic [11:0] offset); + // OpCode Store + return {offset[11:5], src, base, size, offset[4:0], 7'h23}; + endfunction + + function automatic logic [31:0] float_load(logic [2:0] size, logic [4:0] dest, logic [4:0] base, + logic [11:0] offset); + // OpCode Load + return {offset[11:0], base, size, dest, 7'b00_001_11}; + endfunction + + function automatic logic [31:0] float_store(logic [2:0] size, logic [4:0] src, logic [4:0] base, + logic [11:0] offset); + // OpCode Store + return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11}; + endfunction + + function automatic logic [31:0] csrw(csr_reg_t csr, logic [4:0] rs1); + // CSRRW, rd, OpCode System + return {csr, rs1, 3'h1, 5'h0, 7'h73}; + endfunction + + function automatic logic [31:0] csrr(csr_reg_t csr, logic [4:0] dest); + // rs1, CSRRS, rd, OpCode System + return {csr, 5'h0, 3'h2, dest, 7'h73}; + endfunction + + function automatic logic [31:0] branch(logic [4:0] src2, logic [4:0] src1, logic [2:0] funct3, + logic [11:0] offset); + // OpCode Branch + return {offset[11], offset[9:4], src2, src1, funct3, offset[3:0], offset[10], 7'b11_000_11}; + endfunction + + function automatic logic [31:0] ebreak(); + return 32'h00100073; + endfunction + + function automatic logic [31:0] wfi(); + return 32'h10500073; + endfunction + + function automatic logic [31:0] nop(); + return 32'h00000013; + endfunction + + function automatic logic [31:0] illegal(); + return 32'h00000000; + endfunction + + // This functions converts S-mode CSR addresses into VS-mode CSR addresses + // when V=1 (i.e., running in VS-mode). + function automatic csr_t convert_vs_access_csr(csr_t csr_addr, logic v); + csr_t ret; + ret = csr_addr; + unique case (csr_addr.address) inside + [CSR_SSTATUS : CSR_STVEC], [CSR_SSCRATCH : CSR_SATP]: begin + if (v) begin + ret.csr_decode.priv_lvl = PRIV_LVL_HS; + end + return ret; + end + default: return ret; + endcase + endfunction + + + // trace log compatible to spikes commit log feature + // pragma translate_off + function string spikeCommitLog(logic [63:0] pc, priv_lvl_t priv_lvl, logic [31:0] instr, + logic [4:0] rd, logic [63:0] result, logic rd_fpr); + string rd_s; + string instr_word; + + automatic string rf_s = rd_fpr ? "f" : "x"; + + if (instr[1:0] != 2'b11) begin + instr_word = $sformatf("(0x%h)", instr[15:0]); + end else begin + instr_word = $sformatf("(0x%h)", instr); + end + + if (rd < 10) rd_s = $sformatf("%s %0d", rf_s, rd); + else rd_s = $sformatf("%s%0d", rf_s, rd); + + if (rd_fpr || rd != 0) begin + // 0 0x0000000080000118 (0xeecf8f93) x31 0x0000000080004000 + return $sformatf("%d 0x%h %s %s 0x%h\n", priv_lvl, pc, instr_word, rd_s, result); + end else begin + // 0 0x000000008000019c (0x0040006f) + return $sformatf("%d 0x%h %s\n", priv_lvl, pc, instr_word); + end + endfunction + + typedef struct { + byte priv; + longint unsigned pc; + byte is_fp; + byte rd; + longint unsigned data; + int unsigned instr; + byte was_exception; + } commit_log_t; + // pragma translate_on + +endpackage diff --git a/flow/designs/src/cva6/core/include/rvfi_types.svh b/flow/designs/src/cva6/core/include/rvfi_types.svh new file mode 100644 index 0000000000..69c552e7a3 --- /dev/null +++ b/flow/designs/src/cva6/core/include/rvfi_types.svh @@ -0,0 +1,167 @@ +`ifndef RVFI_TYPES_SVH +`define RVFI_TYPES_SVH + +// RVFI +`define RVFI_INSTR_T(Cfg) struct packed { \ + logic [config_pkg::NRET-1:0] valid; \ + logic [config_pkg::NRET*64-1:0] order; \ + logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; \ + logic [config_pkg::NRET-1:0] trap; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] cause; \ + logic [config_pkg::NRET-1:0] halt; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] intr; \ + logic [config_pkg::NRET*2-1:0] mode; \ + logic [config_pkg::NRET*2-1:0] ixl; \ + logic [config_pkg::NRET*5-1:0] rs1_addr; \ + logic [config_pkg::NRET*5-1:0] rs2_addr; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] rs1_rdata; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] rs2_rdata; \ + logic [config_pkg::NRET*5-1:0] rd_addr; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] rd_wdata; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] pc_rdata; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] pc_wdata; \ + logic [config_pkg::NRET*Cfg.VLEN-1:0] mem_addr; \ + logic [config_pkg::NRET*Cfg.PLEN-1:0] mem_paddr; \ + logic [config_pkg::NRET*(Cfg.XLEN/8)-1:0] mem_rmask; \ + logic [config_pkg::NRET*(Cfg.XLEN/8)-1:0] mem_wmask; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] mem_rdata; \ + logic [config_pkg::NRET*Cfg.XLEN-1:0] mem_wdata; \ +} + +`define RVFI_CSR_ELMT_T(Cfg) struct packed { \ + logic [Cfg.XLEN-1:0] rdata; \ + logic [Cfg.XLEN-1:0] rmask; \ + logic [Cfg.XLEN-1:0] wdata; \ + logic [Cfg.XLEN-1:0] wmask; \ +} + +`define RVFI_CSR_T(Cfg, rvfi_csr_elmt_t) struct packed { \ + rvfi_csr_elmt_t fflags; \ + rvfi_csr_elmt_t frm; \ + rvfi_csr_elmt_t fcsr; \ + rvfi_csr_elmt_t jvt; \ + rvfi_csr_elmt_t ftran; \ + rvfi_csr_elmt_t dcsr; \ + rvfi_csr_elmt_t dpc; \ + rvfi_csr_elmt_t dscratch0; \ + rvfi_csr_elmt_t dscratch1; \ + rvfi_csr_elmt_t sstatus; \ + rvfi_csr_elmt_t sie; \ + rvfi_csr_elmt_t sip; \ + rvfi_csr_elmt_t stvec; \ + rvfi_csr_elmt_t scounteren; \ + rvfi_csr_elmt_t sscratch; \ + rvfi_csr_elmt_t sepc; \ + rvfi_csr_elmt_t scause; \ + rvfi_csr_elmt_t stval; \ + rvfi_csr_elmt_t satp; \ + rvfi_csr_elmt_t mstatus; \ + rvfi_csr_elmt_t mstatush; \ + rvfi_csr_elmt_t misa; \ + rvfi_csr_elmt_t medeleg; \ + rvfi_csr_elmt_t mideleg; \ + rvfi_csr_elmt_t mie; \ + rvfi_csr_elmt_t mtvec; \ + rvfi_csr_elmt_t mcounteren; \ + rvfi_csr_elmt_t mscratch; \ + rvfi_csr_elmt_t mepc; \ + rvfi_csr_elmt_t mcause; \ + rvfi_csr_elmt_t mtval; \ + rvfi_csr_elmt_t mip; \ + rvfi_csr_elmt_t menvcfg; \ + rvfi_csr_elmt_t menvcfgh; \ + rvfi_csr_elmt_t mvendorid; \ + rvfi_csr_elmt_t marchid; \ + rvfi_csr_elmt_t mhartid; \ + rvfi_csr_elmt_t mcountinhibit; \ + rvfi_csr_elmt_t mcycle; \ + rvfi_csr_elmt_t mcycleh; \ + rvfi_csr_elmt_t minstret; \ + rvfi_csr_elmt_t minstreth; \ + rvfi_csr_elmt_t cycle; \ + rvfi_csr_elmt_t cycleh; \ + rvfi_csr_elmt_t instret; \ + rvfi_csr_elmt_t instreth; \ + rvfi_csr_elmt_t dcache; \ + rvfi_csr_elmt_t icache; \ + rvfi_csr_elmt_t acc_cons; \ + rvfi_csr_elmt_t pmpcfg0; \ + rvfi_csr_elmt_t pmpcfg1; \ + rvfi_csr_elmt_t pmpcfg2; \ + rvfi_csr_elmt_t pmpcfg3; \ + rvfi_csr_elmt_t [15:0] pmpaddr; \ +} + +// RVFI PROBES +`define RVFI_PROBES_INSTR_T(Cfg) struct packed { \ + logic [Cfg.NrIssuePorts-1:0][Cfg.TRANS_ID_BITS-1:0] issue_pointer; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.TRANS_ID_BITS-1:0] commit_pointer; \ + logic flush_unissued_instr; \ + logic [Cfg.NrIssuePorts-1:0] decoded_instr_valid; \ + logic [Cfg.NrIssuePorts-1:0] decoded_instr_ack; \ + logic flush; \ + logic [Cfg.NrIssuePorts-1:0] issue_instr_ack; \ + logic [Cfg.NrIssuePorts-1:0] fetch_entry_valid; \ + logic [Cfg.NrIssuePorts-1:0][31:0] instruction; \ + logic [Cfg.NrIssuePorts-1:0] is_compressed; \ + logic [Cfg.NrIssuePorts-1:0][Cfg.XLEN-1:0] rs1; \ + logic [Cfg.NrIssuePorts-1:0][Cfg.XLEN-1:0] rs2; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \ + ariane_pkg::fu_op [Cfg.NrCommitPorts-1:0] commit_instr_op; \ + logic [Cfg.NrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \ + logic [Cfg.NrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs2; \ + logic [Cfg.NrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rd; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.XLEN-1:0] commit_instr_result; \ + logic [Cfg.NrCommitPorts-1:0] commit_instr_valid; \ + logic [Cfg.NrCommitPorts-1:0] commit_drop; \ + logic [Cfg.XLEN-1:0] ex_commit_cause; \ + logic ex_commit_valid; \ + riscv::priv_lvl_t priv_lvl; \ + logic [Cfg.VLEN-1:0] lsu_ctrl_vaddr; \ + ariane_pkg::fu_t lsu_ctrl_fu; \ + logic [(Cfg.XLEN/8)-1:0] lsu_ctrl_be; \ + logic [Cfg.TRANS_ID_BITS-1:0] lsu_ctrl_trans_id; \ + logic [Cfg.NrWbPorts-1:0][Cfg.XLEN-1:0] wbdata; \ + logic [Cfg.NrCommitPorts-1:0] commit_ack; \ + logic [Cfg.PLEN-1:0] mem_paddr; \ + logic debug_mode; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.XLEN-1:0] wdata; \ +} + +`define RVFI_PROBES_CSR_T(Cfg) struct packed { \ + riscv::fcsr_t fcsr_q; \ + riscv::dcsr_t dcsr_q; \ + logic [Cfg.XLEN-1:0] jvt_q; \ + logic [Cfg.XLEN-1:0] dpc_q; \ + logic [Cfg.XLEN-1:0] dscratch0_q; \ + logic [Cfg.XLEN-1:0] dscratch1_q; \ + logic [Cfg.XLEN-1:0] mie_q; \ + logic [Cfg.XLEN-1:0] mip_q; \ + logic [Cfg.XLEN-1:0] stvec_q; \ + logic [Cfg.XLEN-1:0] scounteren_q; \ + logic [Cfg.XLEN-1:0] sscratch_q; \ + logic [Cfg.XLEN-1:0] sepc_q; \ + logic [Cfg.XLEN-1:0] scause_q; \ + logic [Cfg.XLEN-1:0] stval_q; \ + logic [Cfg.XLEN-1:0] satp_q; \ + logic [Cfg.XLEN-1:0] mstatus_extended; \ + logic [Cfg.XLEN-1:0] medeleg_q; \ + logic [Cfg.XLEN-1:0] mideleg_q; \ + logic [Cfg.XLEN-1:0] mtvec_q; \ + logic [Cfg.XLEN-1:0] mcounteren_q; \ + logic [Cfg.XLEN-1:0] mscratch_q; \ + logic [Cfg.XLEN-1:0] mepc_q; \ + logic [Cfg.XLEN-1:0] mcause_q; \ + logic [Cfg.XLEN-1:0] mtval_q; \ + logic fiom_q; \ + logic [ariane_pkg::MHPMCounterNum+3-1:0] mcountinhibit_q; \ + logic [63:0] cycle_q; \ + logic [63:0] instret_q; \ + logic [Cfg.XLEN-1:0] dcache_q; \ + logic [Cfg.XLEN-1:0] icache_q; \ + logic [Cfg.XLEN-1:0] acc_cons_q; \ + riscv::pmpcfg_t [63:0] pmpcfg_q; \ + logic [63:0][Cfg.PLEN-3:0] pmpaddr_q; \ +} + +`endif // RVFI_TYPES_SVH diff --git a/flow/designs/src/cva6/core/include/std_cache_pkg.sv b/flow/designs/src/cva6/core/include/std_cache_pkg.sv new file mode 100644 index 0000000000..e6c337e1aa --- /dev/null +++ b/flow/designs/src/cva6/core/include/std_cache_pkg.sv @@ -0,0 +1,60 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba , ETH Zurich +// Michael Schaffner , ETH Zurich +// Date: 15.08.2018 + +// ******* WIP ******* +// Description: package for the standard Ariane cache subsystem. + +package std_cache_pkg; + + // localparam DECISION_BIT = 30; // bit on which to decide whether the request is cache-able or not + + typedef struct packed { + logic [1:0] id; // id for which we handle the miss + logic valid; + logic we; + logic [55:0] addr; + logic [7:0][7:0] wdata; + logic [7:0] be; + } mshr_t; + + typedef struct packed { + logic valid; + logic [63:0] addr; + logic [7:0] be; + logic [1:0] size; + logic we; + logic [63:0] wdata; + logic bypass; + } miss_req_t; + + typedef struct packed { + logic req; + ariane_pkg::ad_req_t reqtype; + ariane_pkg::amo_t amo; + logic [3:0] id; + logic [63:0] addr; + logic [63:0] wdata; + logic we; + logic [7:0] be; + logic [1:0] size; + } bypass_req_t; + + typedef struct packed { + logic gnt; + logic valid; + logic [63:0] rdata; + } bypass_rsp_t; + +endpackage : std_cache_pkg + diff --git a/flow/designs/src/cva6/core/include/wt_cache_pkg.sv b/flow/designs/src/cva6/core/include/wt_cache_pkg.sv new file mode 100644 index 0000000000..38ea500e12 --- /dev/null +++ b/flow/designs/src/cva6/core/include/wt_cache_pkg.sv @@ -0,0 +1,154 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Package for OpenPiton compatible L1 cache subsystem + +// this is needed to propagate the +// configuration in case Ariane is +// instantiated in OpenPiton +`ifdef PITON_ARIANE +`include "l15.tmp.h" +`include "define.tmp.h" +`endif + +package wt_cache_pkg; + + // these parames need to coincide with the + // L1.5 parameterization, do not change +`ifdef PITON_ARIANE + +`ifndef CONFIG_L15_ASSOCIATIVITY + `define CONFIG_L15_ASSOCIATIVITY 4 +`endif + +`ifndef TLB_CSM_WIDTH + `define TLB_CSM_WIDTH 33 +`endif + + localparam L15_SET_ASSOC = `CONFIG_L15_ASSOCIATIVITY; + localparam L15_TLB_CSM_WIDTH = `TLB_CSM_WIDTH; +`else + localparam L15_TLB_CSM_WIDTH = 33; +`endif + + // FIFO depths of L15 adapter + localparam ADAPTER_REQ_FIFO_DEPTH = 2; + localparam ADAPTER_RTRN_FIFO_DEPTH = 2; + + + // TX status registers are indexed with the transaction ID + // they basically store which bytes from which buffer entry are part + // of that transaction + + // local interfaces between caches and L15 adapter + typedef enum logic [1:0] { + DCACHE_STORE_REQ, + DCACHE_LOAD_REQ, + DCACHE_ATOMIC_REQ, + DCACHE_INT_REQ + } dcache_out_t; + + typedef enum logic [2:0] { + DCACHE_INV_REQ, // no ack from the core required + DCACHE_STORE_ACK, // note: this may contain an invalidation vector, too + DCACHE_LOAD_ACK, + DCACHE_ATOMIC_ACK, + DCACHE_INT_ACK + } dcache_in_t; + + typedef enum logic [0:0] { + ICACHE_INV_REQ, // no ack from the core required + ICACHE_IFILL_ACK + } icache_in_t; + + // taken from iop.h in openpiton + // to l1.5 (only marked subset is used) + typedef enum logic [4:0] { + L15_LOAD_RQ = 5'b00000, // load request + L15_IMISS_RQ = 5'b10000, // instruction fill request + L15_STORE_RQ = 5'b00001, // store request + L15_ATOMIC_RQ = 5'b00110, // atomic op + //L15_CAS1_RQ = 5'b00010, // compare and swap1 packet (OpenSparc atomics) + //L15_CAS2_RQ = 5'b00011, // compare and swap2 packet (OpenSparc atomics) + //L15_SWAP_RQ = 5'b00110, // swap packet (OpenSparc atomics) + L15_STRLOAD_RQ = 5'b00100, // unused + L15_STRST_RQ = 5'b00101, // unused + L15_STQ_RQ = 5'b00111, // unused + L15_INT_RQ = 5'b01001, // interrupt request + L15_FWD_RQ = 5'b01101, // unused + L15_FWD_RPY = 5'b01110, // unused + L15_RSVD_RQ = 5'b11111 // unused + } l15_reqtypes_t; + + // from l1.5 (only marked subset is used) + typedef enum logic [3:0] { + L15_LOAD_RET = 4'b0000, // load packet + // L15_INV_RET = 4'b0011, // invalidate packet, not unique... + L15_ST_ACK = 4'b0100, // store ack packet + //L15_AT_ACK = 4'b0011, // unused, not unique... + L15_INT_RET = 4'b0111, // interrupt packet + L15_TEST_RET = 4'b0101, // unused + L15_FP_RET = 4'b1000, // unused + L15_IFILL_RET = 4'b0001, // instruction fill packet + L15_EVICT_REQ = 4'b0011, // eviction request + L15_ERR_RET = 4'b1100, // unused + L15_STRLOAD_RET = 4'b0010, // unused + L15_STRST_ACK = 4'b0110, // unused + L15_FWD_RQ_RET = 4'b1010, // unused + L15_FWD_RPY_RET = 4'b1011, // unused + L15_RSVD_RET = 4'b1111, // unused + L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses + } l15_rtrntypes_t; + + // swap endianess in a 64bit word + function automatic logic [63:0] swendian64(input logic [63:0] in); + automatic logic [63:0] out; + for (int k = 0; k < 64; k += 8) begin + out[k+:8] = in[63-k-:8]; + end + return out; + endfunction + + function automatic logic [5:0] popcnt64(input logic [63:0] in); + logic [5:0] cnt = 0; + foreach (in[k]) begin + cnt += 6'(in[k]); + end + return cnt; + endfunction : popcnt64 + + // note: this is openpiton specific. cannot transmit unaligned words. + // hence we default to individual bytes in that case, and they have to be transmitted + // one after the other + function automatic logic [1:0] toSize64(input logic [7:0] be); + logic [1:0] size; + unique case (be) + 8'b1111_1111: size = 2'b11; // dword + 8'b0000_1111, 8'b1111_0000: size = 2'b10; // word + 8'b1100_0000, 8'b0011_0000, 8'b0000_1100, 8'b0000_0011: size = 2'b01; // hword + default: size = 2'b00; // individual bytes + endcase // be + return size; + endfunction : toSize64 + + + function automatic logic [1:0] toSize32(input logic [3:0] be); + logic [1:0] size; + unique case (be) + 4'b1111: size = 2'b10; // word + 4'b1100, 4'b0011: size = 2'b01; // hword + default: size = 2'b00; // individual bytes + endcase // be + return size; + endfunction : toSize32 + +endpackage diff --git a/flow/designs/src/cva6/core/instr_realign.sv b/flow/designs/src/cva6/core/instr_realign.sv new file mode 100644 index 0000000000..3aae6ff922 --- /dev/null +++ b/flow/designs/src/cva6/core/instr_realign.sv @@ -0,0 +1,365 @@ +// Copyright 2018 - 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba +// Description: Instruction Re-aligner +// +// This module takes cache blocks and extracts the instructions. +// As we are supporting the compressed instruction set extension, in a 32 bit instruction word +// are up to 2 compressed instructions. +// Furthermore those instructions can be arbitrarily interleaved which makes it possible to fetch +// only the lower part of a 32 bit instruction. +// Furthermore we need to handle the case if we want to start fetching from an unaligned +// instruction e.g. a branch. + +module instr_realign + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // 32-bit block is valid - CACHE + input logic valid_i, + // Instruction is unaligned - FRONTEND + output logic serving_unaligned_o, + // 32-bit block address - CACHE + input logic [CVA6Cfg.VLEN-1:0] address_i, + // 32-bit block - CACHE + input logic [CVA6Cfg.FETCH_WIDTH-1:0] data_i, + // instruction is valid - FRONTEND + output logic [CVA6Cfg.INSTR_PER_FETCH-1:0] valid_o, + // Instruction address - FRONTEND + output logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] addr_o, + // Instruction - instr_scan&instr_queue + output logic [CVA6Cfg.INSTR_PER_FETCH-1:0][31:0] instr_o +); + // as a maximum we support a fetch width of 64-bit, hence there can be 4 compressed instructions + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_is_compressed; + + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + // LSB != 2'b11 + assign instr_is_compressed[i] = ~&data_i[i*16+:2]; + end + + // save the unaligned part of the instruction to this ff + logic [15:0] unaligned_instr_d, unaligned_instr_q; + // the last instruction was unaligned + logic unaligned_d, unaligned_q; + // register to save the unaligned address + logic [CVA6Cfg.VLEN-1:0] unaligned_address_d, unaligned_address_q; + // we have an unaligned instruction + assign serving_unaligned_o = unaligned_q; + + // Instruction re-alignment + if (CVA6Cfg.FETCH_WIDTH == 32) begin : realign_bp_32 + always_comb begin : re_align + unaligned_d = unaligned_q; + unaligned_address_d = {address_i[CVA6Cfg.VLEN-1:2], 2'b10}; + unaligned_instr_d = data_i[31:16]; + + valid_o[0] = valid_i; + instr_o[0] = unaligned_q ? {data_i[15:0], unaligned_instr_q} : data_i[31:0]; + addr_o[0] = unaligned_q ? unaligned_address_q : address_i; + + if (CVA6Cfg.INSTR_PER_FETCH != 1) begin + valid_o[CVA6Cfg.INSTR_PER_FETCH-1] = 1'b0; + instr_o[CVA6Cfg.INSTR_PER_FETCH-1] = '0; + addr_o[CVA6Cfg.INSTR_PER_FETCH-1] = {address_i[CVA6Cfg.VLEN-1:2], 2'b10}; + end + // this instruction is compressed or the last instruction was unaligned + if (instr_is_compressed[0] || unaligned_q) begin + // check if this is instruction is still unaligned e.g.: it is not compressed + // if its compressed re-set unaligned flag + // for 32 bit we can simply check the next instruction and whether it is compressed or not + // if it is compressed the next fetch will contain an aligned instruction + // is instruction 1 also compressed + // yes? -> no problem, no -> we've got an unaligned instruction + if (instr_is_compressed[CVA6Cfg.INSTR_PER_FETCH-1] && CVA6Cfg.RVC) begin + unaligned_d = 1'b0; + valid_o[CVA6Cfg.INSTR_PER_FETCH-1] = valid_i; + instr_o[CVA6Cfg.INSTR_PER_FETCH-1] = {16'b0, data_i[31:16]}; + end else begin + // save the upper bits for next cycle + unaligned_d = 1'b1; + unaligned_instr_d = data_i[31:16]; + unaligned_address_d = {address_i[CVA6Cfg.VLEN-1:2], 2'b10}; + end + end // else -> normal fetch + + // we started to fetch on a unaligned boundary with a whole instruction -> wait until we've + // received the next instruction + if (valid_i && address_i[1]) begin + // the instruction is not compressed so we can't do anything in this cycle + if (!instr_is_compressed[0]) begin + valid_o = '0; + unaligned_d = 1'b1; + unaligned_address_d = {address_i[CVA6Cfg.VLEN-1:2], 2'b10}; + unaligned_instr_d = data_i[15:0]; + // the instruction isn't compressed but only the lower is ready + end else begin + valid_o = {{CVA6Cfg.INSTR_PER_FETCH - 1{1'b0}}, 1'b1}; + end + end + end + end else if (CVA6Cfg.FETCH_WIDTH == 64) begin : realign_bp_64 + always_comb begin : re_align + unaligned_d = 1'b0; + unaligned_address_d = unaligned_address_q; + unaligned_instr_d = unaligned_instr_q; + + valid_o = '0; + instr_o[0] = '0; + addr_o[0] = '0; + instr_o[1] = '0; + addr_o[1] = '0; + instr_o[2] = '0; + addr_o[2] = '0; + instr_o[3] = {16'b0, data_i[63:48]}; + addr_o[3] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + + case (address_i[2:1]) + 2'b00: begin + valid_o[0] = valid_i; + valid_o[1] = valid_i; + + unaligned_d = unaligned_q; + + // last instruction was unaligned + // TODO how are jumps + unaligned managed? + if (unaligned_q) begin + // for 64 bit there exist the following options: + // 64 48 32 16 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | I | I | U | -> again unaligned + // | * | C | I | U | -> aligned + // | * | I | C | U | -> aligned + // | I | C | C | U | -> again unaligned + // | * | C | C | C | U | -> aligned + // Legend: C = compressed, I = 32 bit instruction, U = unaligned upper half + + instr_o[0] = {data_i[15:0], unaligned_instr_q}; + addr_o[0] = unaligned_address_q; + + instr_o[1] = data_i[47:16]; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + + if (instr_is_compressed[1]) begin + instr_o[2] = data_i[63:32]; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + valid_o[2] = valid_i; + + if (instr_is_compressed[2]) begin + if (instr_is_compressed[3]) begin + unaligned_d = 1'b0; + valid_o[3] = valid_i; + end else begin + unaligned_instr_d = instr_o[3]; + unaligned_address_d = addr_o[3]; + end + end else begin + unaligned_d = 1'b0; + valid_o[2] = valid_i; + end + end else begin + instr_o[2] = instr_o[3]; + addr_o[2] = addr_o[3]; + if (instr_is_compressed[3]) begin + unaligned_d = 1'b0; + valid_o[2] = valid_i; + end else begin + unaligned_instr_d = instr_o[3]; + unaligned_address_d = addr_o[3]; + end + end + end else begin + instr_o[0] = data_i[31:0]; + addr_o[0] = address_i; + + if (instr_is_compressed[0]) begin + instr_o[1] = data_i[47:16]; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + + // 64 48 32 16 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | I | I | C | -> again unaligned + // | * | C | I | C | -> aligned + // | * | I | C | C | -> aligned + // | I | C | C | C | -> again unaligned + // | * | C | C | C | C | -> aligned + if (instr_is_compressed[1]) begin + instr_o[2] = data_i[63:32]; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + valid_o[2] = valid_i; + + if (instr_is_compressed[2]) begin + if (instr_is_compressed[3]) begin + valid_o[3] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[3]; + unaligned_address_d = addr_o[3]; + end + end + end else begin + instr_o[2] = instr_o[3]; + addr_o[2] = addr_o[3]; + + if (instr_is_compressed[3]) begin + valid_o[2] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[3]; + unaligned_address_d = addr_o[3]; + end + end + end else begin + // 64 32 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | I | C | I | + // | * | C | C | I | + // | * | I | I | + instr_o[1] = data_i[63:32]; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + + instr_o[2] = instr_o[3]; + addr_o[2] = addr_o[3]; + + if (instr_is_compressed[2]) begin + if (instr_is_compressed[3]) begin + valid_o[2] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[3]; + unaligned_address_d = addr_o[3]; + end + end + end + end + end + // this means the previous instruction was either compressed or unaligned + // in any case we don't care + // TODO input is actually right-shifted so the code below is wrong + 2'b01: begin + // 64 48 32 16 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | I | I | -> again unaligned + // | * | C | I | -> aligned + // | * | I | C | -> aligned + // | I | C | C | -> again unaligned + // | * | C | C | C | -> aligned + // 000 110 100 010 <- unaligned address + + instr_o[0] = data_i[31:0]; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b010}; + valid_o[0] = valid_i; + + instr_o[2] = data_i[63:32]; + addr_o[2] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + + if (instr_is_compressed[0]) begin + instr_o[1] = data_i[47:16]; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + valid_o[1] = valid_i; + + if (instr_is_compressed[1]) begin + if (instr_is_compressed[2]) begin + valid_o[2] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[2]; + unaligned_address_d = addr_o[2]; + end + end + end else begin + instr_o[1] = instr_o[2]; + addr_o[1] = addr_o[2]; + + if (instr_is_compressed[2]) begin + valid_o[1] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[2]; + unaligned_address_d = addr_o[2]; + end + end + end + 2'b10: begin + // 64 48 32 16 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | * | I | C | <- unaligned + // | * | C | C | <- aligned + // | * | I | <- aligned + // 1000 110 100 <- unaligned address + + instr_o[0] = data_i[31:0]; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b100}; + valid_o[0] = valid_i; + + instr_o[1] = data_i[47:16]; + addr_o[1] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + + if (instr_is_compressed[0]) begin + if (instr_is_compressed[1]) begin + valid_o[1] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[1]; + unaligned_address_d = addr_o[1]; + end + end + end + // we started to fetch on a unaligned boundary with a whole instruction -> wait until we've + // received the next instruction + 2'b11: begin + // 64 48 32 16 0 + // | 3 | 2 | 1 | 0 | <- instruction slot + // | * | I | <- unaligned + // | * | C | <- aligned + // 1000 110 <- unaligned address + + instr_o[0] = data_i[31:0]; + addr_o[0] = {address_i[CVA6Cfg.VLEN-1:3], 3'b110}; + + if (instr_is_compressed[0]) begin + valid_o[0] = valid_i; + end else begin + unaligned_d = 1'b1; + unaligned_instr_d = instr_o[0]; + unaligned_address_d = addr_o[0]; + end + end + endcase + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + unaligned_q <= 1'b0; + unaligned_address_q <= '0; + unaligned_instr_q <= '0; + end else begin + if (valid_i) begin + unaligned_address_q <= unaligned_address_d; + unaligned_instr_q <= unaligned_instr_d; + end + + if (flush_i) begin + unaligned_q <= 1'b0; + end else if (valid_i) begin + unaligned_q <= unaligned_d; + end + end + end +endmodule diff --git a/flow/designs/src/cva6/core/issue_read_operands.sv b/flow/designs/src/cva6/core/issue_read_operands.sv new file mode 100644 index 0000000000..8f70016f07 --- /dev/null +++ b/flow/designs/src/cva6/core/issue_read_operands.sv @@ -0,0 +1,1215 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.04.2017 +// Description: Issues instruction from the scoreboard and fetches the operands +// This also includes all the forwarding logic + + +module issue_read_operands + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, + parameter type fu_data_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type forwarding_t = logic, + parameter type writeback_t = logic, + parameter type rs3_len_t = logic, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type x_commit_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Prevent from issuing - CONTROLLER + input logic flush_i, + // Stall inserted by Acc dispatcher - ACC_DISPATCHER + input logic stall_i, + // Entry about the instruction to issue - SCOREBOARD + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_i_prev, + // Instruction to issue - SCOREBOARD + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i, + // Is there an instruction to issue - SCOREBOARD + input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_i, + // Issue stage acknowledge - SCOREBOARD + output logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_o, + // Forwarding - SCOREBOARD + input forwarding_t fwd_i, + // FU data useful to execute instruction - EX_STAGE + output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o, + // Unregistered version of fu_data_o.operanda - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o, + // Unregistered version of fu_data_o.operandb - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o, + // Program Counter - EX_STAGE + output logic [CVA6Cfg.VLEN-1:0] pc_o, + // Is zcmt - EX_STAGE + output logic is_zcmt_o, + // Is compressed instruction - EX_STAGE + output logic is_compressed_instr_o, + // Fixed Latency Unit is ready - EX_STAGE + input logic flu_ready_i, + // ALU output is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o, + // Branch unit is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, + // Transformed trap instruction - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o, + // Information of branch prediction - EX_STAGE + output branchpredict_sbe_t branch_predict_o, + // Load store unit FU is ready - EX_STAGE + input logic lsu_ready_i, + // Load store unit FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o, + // Mult FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o, + // FPU FU is ready - EX_STAGE + input logic fpu_ready_i, + // FPU FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o, + // FPU fmt field - EX_STAGE + output logic [1:0] fpu_fmt_o, + // FPU rm field - EX_STAGE + output logic [2:0] fpu_rm_o, + // ALU2 FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o, + // CSR is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_o, + // CVXIF FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_o, + // CVXIF is FU ready - EX_STAGE + input logic cvxif_ready_i, + // CVXIF offloader instruction value - EX_STAGE + output logic [31:0] cvxif_off_instr_o, + // CVA6 Hart ID - SUBSYSTEM + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + // CVXIF Issue interface + input logic x_issue_ready_i, + input x_issue_resp_t x_issue_resp_i, + output logic x_issue_valid_o, + output x_issue_req_t x_issue_req_o, + // CVXIF Register interface + input logic x_register_ready_i, + output logic x_register_valid_o, + output x_register_t x_register_o, + // CVXIF Commit interface + output logic x_commit_valid_o, + output x_commit_t x_commit_o, + // Writeback Handling of CVXIF + output logic x_transaction_accepted_o, + output logic x_transaction_rejected_o, + output logic x_issue_writeback_o, + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_o, + // Destination register in the register file - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i, + // Value to write to register file - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i, + // GPR write enable - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i, + // FPR write enable - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, + // Issue stall - PERF_COUNTERS + output logic stall_issue_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o + +); + + localparam OPERANDS_PER_INSTR = CVA6Cfg.NrRgprPorts / CVA6Cfg.NrIssuePorts; + + typedef struct packed { + logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel; + } fus_busy_t; + + logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_waw, stall_rs1, stall_rs2, stall_rs3; + logic [CVA6Cfg.NrIssuePorts-1:0] fu_busy; // functional unit is busy + fus_busy_t [CVA6Cfg.NrIssuePorts-1:0] fus_busy; // which functional units are considered busy + logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack; + // operands coming from regfile + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] operand_a_regfile, operand_b_regfile; + // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 + rs3_len_t [CVA6Cfg.NrIssuePorts-1:0] operand_c_regfile, operand_c_gpr; + rs3_len_t operand_c_fpr; + // output flipflop (ID <-> EX) + fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_n, fu_data_q; + logic [CVA6Cfg.VLEN-1:0] pc_n; + logic is_compressed_instr_n; + branchpredict_sbe_t branch_predict_n; + logic [CVA6Cfg.XLEN-1:0] imm_forward_rs3; + + logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_n, alu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_n, mult_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_n, fpu_valid_q; + logic [1:0] fpu_fmt_n, fpu_fmt_q; + logic [2:0] fpu_rm_n, fpu_rm_q; + logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_n, alu2_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_n, lsu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_n, csr_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_n, branch_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_n, cvxif_valid_q; + logic [31:0] cvxif_off_instr_n, cvxif_off_instr_q; + logic cvxif_instruction_valid; + + //fwd logic + logic [CVA6Cfg.NrIssuePorts-1:0] rs1_has_raw; + logic [CVA6Cfg.NrIssuePorts-1:0] rs2_has_raw; + logic [CVA6Cfg.NrIssuePorts-1:0] rs3_has_raw; + + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3; + logic [CVA6Cfg.NrIssuePorts-1:0] rs3_fpr; + + logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid; + logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid; + logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid; + + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_res; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_res; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3_res; + + // clobber + fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr, rd_clobber_fpr; + logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] gpr_clobber_vld; + logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] fpr_clobber_vld; + ariane_pkg::fu_t [ CVA6Cfg.NR_SB_ENTRIES:0] clobber_fu; + + //forward logic + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0] + rs1_fwd_req, rs2_fwd_req, rs3_fwd_req; + logic [CVA6Cfg.NrIssuePorts-1:0] rs1_is_not_gpr0, rs2_is_not_gpr0, rs3_is_not_gpr0; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data; + logic [CVA6Cfg.NrIssuePorts-1:0] rs1_available, rs2_available, rs3_available; + + + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_n, tinst_q; // transformed instruction + + // forwarding signals + logic [CVA6Cfg.NrIssuePorts-1:0] forward_rs1, forward_rs2, forward_rs3; + + // original instruction + riscv::instruction_t orig_instr; + assign orig_instr = riscv::instruction_t'(orig_instr_i[0]); + + // CVXIF Signals + logic cvxif_req_allowed; + logic x_transaction_rejected, x_transaction_rejected_n; + logic [OPERANDS_PER_INSTR-1:0] rs_valid; + logic [OPERANDS_PER_INSTR-1:0][CVA6Cfg.XLEN-1:0] rs; + + cvxif_issue_register_commit_if_driver #( + .CVA6Cfg (CVA6Cfg), + .x_issue_req_t (x_issue_req_t), + .x_issue_resp_t(x_issue_resp_t), + .x_register_t (x_register_t), + .x_commit_t (x_commit_t) + ) i_cvxif_issue_register_commit_if_driver ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (flush_i), + .hart_id_i (hart_id_i), + .issue_ready_i (x_issue_ready_i), + .issue_resp_i (x_issue_resp_i), + .issue_valid_o (x_issue_valid_o), + .issue_req_o (x_issue_req_o), + .register_ready_i(x_register_ready_i), + .register_valid_o(x_register_valid_o), + .register_o (x_register_o), + .commit_valid_o (x_commit_valid_o), + .commit_o (x_commit_o), + .valid_i (cvxif_instruction_valid), + .x_off_instr_i (orig_instr_i[0]), + .x_trans_id_i (issue_instr_i[0].trans_id), + .register_i (rs), + .rs_valid_i (rs_valid) + ); + if (OPERANDS_PER_INSTR == 3) begin + assign rs_valid = {~stall_rs3[0], ~stall_rs2[0], ~stall_rs1[0]}; + assign rs = {fu_data_n[0].imm, fu_data_n[0].operand_b, fu_data_n[0].operand_a}; + end else begin + assign rs_valid = {~stall_rs2[0], ~stall_rs1[0]}; + assign rs = {fu_data_n[0].operand_b, fu_data_n[0].operand_a}; + end + + // TODO check only for 1st instruction ?? + // Allow a cvxif transaction if we WaW condition are ok. + assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF) && !stall_waw[0]; + assign cvxif_instruction_valid = !issue_instr_i[0].ex.valid && issue_instr_valid_i[0] && cvxif_req_allowed; + assign x_transaction_accepted_o = x_issue_valid_o && x_issue_ready_i && x_issue_resp_i.accept; + assign x_transaction_rejected = x_issue_valid_o && x_issue_ready_i && ~x_issue_resp_i.accept; + assign x_issue_writeback_o = x_issue_resp_i.writeback; + assign x_id_o = x_issue_req_o.id; + + // ID <-> EX registers + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign rs1_forwarding_o[i] = fu_data_n[i].operand_a[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs1 value + assign rs2_forwarding_o[i] = fu_data_n[i].operand_b[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs2 value + assign rvfi_rs1_o[i] = fu_data_n[i].operand_a; + assign rvfi_rs2_o[i] = fu_data_n[i].operand_b; + end + + assign fu_data_o = fu_data_q; + assign alu_valid_o = alu_valid_q; + assign branch_valid_o = branch_valid_q; + assign lsu_valid_o = lsu_valid_q; + assign csr_valid_o = csr_valid_q; + assign mult_valid_o = mult_valid_q; + assign fpu_valid_o = fpu_valid_q; + assign fpu_fmt_o = fpu_fmt_q; + assign fpu_rm_o = fpu_rm_q; + assign alu2_valid_o = alu2_valid_q; + assign cvxif_valid_o = CVA6Cfg.CvxifEn ? cvxif_valid_q : '0; + assign cvxif_off_instr_o = CVA6Cfg.CvxifEn ? cvxif_off_instr_q : '0; + assign stall_issue_o = stall_raw[0]; + assign tinst_o = CVA6Cfg.RVH ? tinst_q : '0; + // --------------- + // Issue Stage + // --------------- + + always_comb begin : structural_hazards + fus_busy = '0; + // CVXIF is always ready to try a new transaction on 1st issue port + // If a transaction is already pending then we stall until the transaction is done.(issue_ack_o[0] = 0) + // Since we can not have two CVXIF instruction on 1st issue port, CVXIF is always ready for the pending instruction. + if (!flu_ready_i) begin + fus_busy[0].alu = 1'b1; + fus_busy[0].ctrl_flow = 1'b1; + fus_busy[0].csr = 1'b1; + fus_busy[0].mult = 1'b1; + end + + // after a multiplication was issued we can only issue another multiplication + // otherwise we will get contentions on the fixed latency bus + if (|mult_valid_q) begin + fus_busy[0].alu = 1'b1; + fus_busy[0].ctrl_flow = 1'b1; + fus_busy[0].csr = 1'b1; + end + + if (CVA6Cfg.FpPresent && !fpu_ready_i) begin + fus_busy[0].fpu = 1'b1; + fus_busy[0].fpu_vec = 1'b1; + if (CVA6Cfg.SuperscalarEn) fus_busy[0].alu2 = 1'b1; + end + + if (!lsu_ready_i) begin + fus_busy[0].load = 1'b1; + fus_busy[0].store = 1'b1; + end + + if (CVA6Cfg.SuperscalarEn) begin + fus_busy[1] = fus_busy[0]; + + // Never issue CSR instruction on second issue port. + fus_busy[1].csr = 1'b1; + // Never issue CVXIF instruction on second issue port. + fus_busy[1].cvxif = 1'b1; + + unique case (issue_instr_i[0].fu) + NONE: fus_busy[1].none = 1'b1; + CTRL_FLOW: begin + if (CVA6Cfg.SpeculativeSb) begin + // Issue speculative instruction, will be removed on BMISS + fus_busy[1].alu = 1'b1; + fus_busy[1].ctrl_flow = 1'b1; + fus_busy[1].csr = 1'b1; + // Speculative non-idempotent loads are not supported yet + fus_busy[1].load = 1'b1; + // The store buffer cannot be partially flushed yet + fus_busy[1].store = 1'b1; + end else begin + // There are no branch misses on a JAL + if (issue_instr_i[0].op == ariane_pkg::ADD) begin + fus_busy[1].alu = 1'b1; + fus_busy[1].ctrl_flow = 1'b1; + fus_busy[1].csr = 1'b1; + end else begin + // Control hazard + fus_busy[1] = '1; + end + end + end + ALU: begin + if (CVA6Cfg.SuperscalarEn && !fus_busy[0].alu2) begin + fus_busy[1].alu2 = 1'b1; + // TODO is there a minimum float execution time? + // If so we could issue FPU & ALU2 the same cycle + fus_busy[1].fpu = 1'b1; + fus_busy[1].fpu_vec = 1'b1; + end else begin + fus_busy[1].alu = 1'b1; + fus_busy[1].ctrl_flow = 1'b1; + fus_busy[1].csr = 1'b1; + end + end + CSR: begin + // Control hazard + fus_busy[1] = '1; + end + MULT: fus_busy[1].mult = 1'b1; + FPU, FPU_VEC: begin + fus_busy[1].fpu = 1'b1; + fus_busy[1].fpu_vec = 1'b1; + end + LOAD, STORE: begin + fus_busy[1].load = 1'b1; + fus_busy[1].store = 1'b1; + end + CVXIF: ; + default: ; + endcase + end + end + + // select the right busy signal + // this obviously depends on the functional unit we need + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + always_comb begin + unique case (issue_instr_i[i].fu) + NONE: fu_busy[i] = fus_busy[i].none; + ALU: begin + if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + fu_busy[i] = fus_busy[i].alu2; + end else begin + fu_busy[i] = fus_busy[i].alu; + end + end + CTRL_FLOW: fu_busy[i] = fus_busy[i].ctrl_flow; + CSR: fu_busy[i] = fus_busy[i].csr; + MULT: fu_busy[i] = fus_busy[i].mult; + LOAD: fu_busy[i] = fus_busy[i].load; + STORE: fu_busy[i] = fus_busy[i].store; + CVXIF: fu_busy[i] = fus_busy[i].cvxif; + default: + if (CVA6Cfg.FpPresent) begin + unique case (issue_instr_i[i].fu) + FPU: fu_busy[i] = fus_busy[i].fpu; + FPU_VEC: fu_busy[i] = fus_busy[i].fpu_vec; + default: fu_busy[i] = 1'b0; + endcase + end else begin + fu_busy[i] = 1'b0; + end + endcase + end + end + + // ------------------- + // RD clobber process + // ------------------- + // rd_clobber output: output currently clobbered destination registers + + always_comb begin : clobber_assign + gpr_clobber_vld = '0; + fpr_clobber_vld = '0; + + // default (highest entry hast lowest prio in arbiter tree below) + clobber_fu[CVA6Cfg.NR_SB_ENTRIES] = ariane_pkg::NONE; + for (int unsigned i = 0; i < 2 ** ariane_pkg::REG_ADDR_SIZE; i++) begin + gpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1; + fpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1; + end + + // check for all valid entries and set the clobber accordingly + + for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + gpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & ~(CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[i].op)); + fpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[i].op)); + clobber_fu[i] = fwd_i.sbe[i].fu; + end + + // GPR[0] is always free + gpr_clobber_vld[0] = '0; + end + + for (genvar k = 0; k < 2 ** ariane_pkg::REG_ADDR_SIZE; k++) begin : gen_sel_clobbers + // get fu that is going to clobber this register (there should be only one) + rr_arb_tree #( + .NumIn(CVA6Cfg.NR_SB_ENTRIES + 1), + .DataType(ariane_pkg::fu_t), + .ExtPrio(1'b1), + .AxiVldRdy(1'b1) + ) i_sel_gpr_clobbers ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i(1'b0), + .rr_i ('0), + .req_i (gpr_clobber_vld[k]), + .gnt_o (), + .data_i (clobber_fu), + .gnt_i (1'b1), + .req_o (), + .data_o (rd_clobber_gpr[k]), + .idx_o () + ); + if (CVA6Cfg.FpPresent) begin + rr_arb_tree #( + .NumIn(CVA6Cfg.NR_SB_ENTRIES + 1), + .DataType(ariane_pkg::fu_t), + .ExtPrio(1'b1), + .AxiVldRdy(1'b1) + ) i_sel_fpr_clobbers ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i(1'b0), + .rr_i ('0), + .req_i (fpr_clobber_vld[k]), + .gnt_o (), + .data_i (clobber_fu), + .gnt_i (1'b1), + .req_o (), + .data_o (rd_clobber_fpr[k]), + .idx_o () + ); + end else begin + assign rd_clobber_fpr[k] = NONE; + end + end + + // ---------------------------------- + // Read Operands (a.k.a forwarding) + // ---------------------------------- + // read operand interface: same logic as register file + + // WB ports have higher prio than entries + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb + + assign rs1_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs1) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[fwd_i.wb[k].trans_id].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr( + issue_instr_i[i].op + ))); + + assign rs2_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs2) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[fwd_i.wb[k].trans_id].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr( + issue_instr_i[i].op + ))); + + assign rs3_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[fwd_i.wb[k].trans_id].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr( + issue_instr_i[i].op + ))); + + assign rs_data[i][k] = fwd_i.wb[k].data; + end + + for (genvar k = 0; unsigned'(k) < CVA6Cfg.NR_SB_ENTRIES; k++) begin : gen_rs_entries + + assign rs1_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs1) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[k].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr( + issue_instr_i[i].op + ))); + + assign rs2_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs2) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[k].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr( + issue_instr_i[i].op + ))); + + assign rs3_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + fwd_i.sbe[k].op + )) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr( + issue_instr_i[i].op + ))); + + assign rs_data[i][k+CVA6Cfg.NrWbPorts] = fwd_i.sbe[k].result; + end + + // use fixed prio here + // this implicitly gives higher prio to WB ports + rr_arb_tree #( + .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), + .DataWidth(CVA6Cfg.XLEN), + .ExtPrio(1'b1), + .AxiVldRdy(1'b1) + ) i_sel_rs1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i(1'b0), + .rr_i ('0), + .req_i (rs1_fwd_req[i]), + .gnt_o (), + .data_i (rs_data[i]), + .gnt_i (1'b1), + .req_o (rs1_available[i]), + .data_o (rs1_res[i]), + .idx_o () + ); + + rr_arb_tree #( + .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), + .DataWidth(CVA6Cfg.XLEN), + .ExtPrio(1'b1), + .AxiVldRdy(1'b1) + ) i_sel_rs2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i(1'b0), + .rr_i ('0), + .req_i (rs2_fwd_req[i]), + .gnt_o (), + .data_i (rs_data[i]), + .gnt_i (1'b1), + .req_o (rs2_available[i]), + .data_o (rs2_res[i]), + .idx_o () + ); + + + rr_arb_tree #( + .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), + .DataWidth(CVA6Cfg.XLEN), + .ExtPrio(1'b1), + .AxiVldRdy(1'b1) + ) i_sel_rs3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i(1'b0), + .rr_i ('0), + .req_i (rs3_fwd_req[i]), + .gnt_o (), + .data_i (rs_data[i]), + .gnt_i (1'b1), + .req_o (rs3_available[i]), + .data_o (rs3[i]), + .idx_o () + ); + + if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_three_port + assign rs3_res[i] = rs3[i][riscv::XLEN-1:0]; + end else begin : gen_fp_three_port + assign rs3_res[i] = rs3[i][CVA6Cfg.FLen-1:0]; + end + + assign rs1_has_raw[i] = !issue_instr_i[i].use_zimm && ((CVA6Cfg.FpPresent && is_rs1_fpr( + issue_instr_i[i].op + )) ? rd_clobber_fpr[issue_instr_i[i].rs1] != NONE : + rd_clobber_gpr[issue_instr_i[i].rs1] != NONE); + + assign rs1_valid[i] = rs1_available[i] && (CVA6Cfg.FpPresent && is_rs1_fpr( + issue_instr_i[i].op + ) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs1] != CSR) || + (CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA))); + + assign rs2_has_raw[i] = ((CVA6Cfg.FpPresent && is_rs2_fpr( + issue_instr_i[i].op + )) ? rd_clobber_fpr[issue_instr_i[i].rs2] != NONE : + rd_clobber_gpr[issue_instr_i[i].rs2] != NONE); + + assign rs2_valid[i] = rs2_available[i] && (CVA6Cfg.FpPresent && is_rs2_fpr( + issue_instr_i[i].op + ) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs2] != CSR) || + (CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA))); + + assign rs3_has_raw[i] = ((CVA6Cfg.FpPresent && is_imm_fpr( + issue_instr_i[i].op + )) ? rd_clobber_fpr[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0); + + assign rs3_valid[i] = rs3_available[i]; + assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op)); + + end + + // --------------- + // Register stage + // --------------- + // check that all operands are available, otherwise stall + // forward corresponding register + always_comb begin : operands_available + stall_raw = '{default: stall_i}; + stall_rs1 = '{default: stall_i}; + stall_rs2 = '{default: stall_i}; + stall_rs3 = '{default: stall_i}; + // operand forwarding signals + forward_rs1 = '0; + forward_rs2 = '0; + forward_rs3 = '0; // FPR only + + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (rs1_has_raw[i]) begin + if (rs1_valid[i]) begin + forward_rs1[i] = 1'b1; + end else begin // the operand is not available -> stall + stall_raw[i] = 1'b1; + stall_rs1[i] = 1'b1; + end + end + + if (rs2_has_raw[i]) begin + if (rs2_valid[i]) begin + forward_rs2[i] = 1'b1; + end else begin // the operand is not available -> stall + stall_raw[i] = 1'b1; + stall_rs2[i] = 1'b1; + end + end + + if (rs3_has_raw[i] && rs3_fpr[i]) begin + if (rs3_valid[i]) begin + forward_rs3[i] = 1'b1; + end else begin // the operand is not available -> stall + stall_raw[i] = 1'b1; + stall_rs3[i] = 1'b1; + end + end + end + + if (CVA6Cfg.CvxifEn) begin + // Remove unecessary forward and stall in case source register is not needed by coprocessor. + if (x_issue_valid_o && x_issue_resp_i.accept) begin + if (~x_issue_resp_i.register_read[0]) begin + forward_rs1[0] = 1'b0; + stall_rs1[0] = 1'b0; + end + if (~x_issue_resp_i.register_read[1]) begin + forward_rs2[0] = 1'b0; + stall_rs2[0] = 1'b0; + end + if (OPERANDS_PER_INSTR == 3 && ~x_issue_resp_i.register_read[2]) begin + forward_rs3[0] = 1'b0; + stall_rs3[0] = 1'b0; + end + end + stall_raw[0] = x_transaction_rejected ? 1'b0 : stall_rs1[0] || stall_rs2[0] || stall_rs3[0]; + end + + if (CVA6Cfg.SuperscalarEn) begin + if (!issue_instr_i[1].use_zimm && (!CVA6Cfg.FpPresent || (is_rs1_fpr( + issue_instr_i[1].op + ) == is_rd_fpr( + issue_instr_i[0].op + ))) && issue_instr_i[1].rs1 == issue_instr_i[0].rd && issue_instr_i[1].rs1 != '0) begin + stall_raw[1] = 1'b1; + end + + if ((!CVA6Cfg.FpPresent || (is_rs2_fpr( + issue_instr_i[1].op + ) == is_rd_fpr( + issue_instr_i[0].op + ))) && issue_instr_i[1].rs2 == issue_instr_i[0].rd && issue_instr_i[1].rs2 != '0) begin + stall_raw[1] = 1'b1; + end + + // Only check clobbered gpr for OFFLOADED instruction + if ((CVA6Cfg.FpPresent && is_imm_fpr( + issue_instr_i[1].op + )) ? is_rd_fpr( + issue_instr_i[0].op + ) && issue_instr_i[0].rd == issue_instr_i[1].result[REG_ADDR_SIZE-1:0] : + issue_instr_i[1].op == OFFLOAD && OPERANDS_PER_INSTR == 3 ? + issue_instr_i[0].rd == issue_instr_i[1].result[REG_ADDR_SIZE-1:0] : 1'b0) begin + stall_raw[1] = 1'b1; + end + end + end + + // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 + if (OPERANDS_PER_INSTR == 3) begin : gen_gp_rs3 + assign imm_forward_rs3 = rs3_res[0]; + end else begin : gen_fp_rs3 + assign imm_forward_rs3 = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, rs3_res[0]}; + end + + // Forwarding/Output MUX + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + always_comb begin : forwarding_operand_select + // default is regfiles (gpr or fpr) + fu_data_n[i].operand_a = operand_a_regfile[i]; + fu_data_n[i].operand_b = operand_b_regfile[i]; + + // immediates are the third operands in the store case + // for FP operations, the imm field can also be the third operand from the regfile + if (OPERANDS_PER_INSTR == 3) begin + fu_data_n[i].imm = (CVA6Cfg.FpPresent && is_imm_fpr(issue_instr_i[i].op)) ? + {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile[i]} : + issue_instr_i[i].op == OFFLOAD ? operand_c_regfile[i] : issue_instr_i[i].result; + end else begin + fu_data_n[i].imm = (CVA6Cfg.FpPresent && is_imm_fpr(issue_instr_i[i].op)) ? + {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile[i]} : issue_instr_i[i].result; + end + fu_data_n[i].trans_id = issue_instr_i[i].trans_id; + fu_data_n[i].fu = issue_instr_i[i].fu; + fu_data_n[i].operation = issue_instr_i[i].op; + if (CVA6Cfg.RVH) begin + tinst_n[i] = issue_instr_i[i].ex.tinst; + end + + // or should we forward + if (forward_rs1[i]) begin + fu_data_n[i].operand_a = rs1_res[i]; + end + if (forward_rs2[i]) begin + fu_data_n[i].operand_b = rs2_res[i]; + end + if ((CVA6Cfg.FpPresent || (CVA6Cfg.CvxifEn && OPERANDS_PER_INSTR == 3)) && forward_rs3[i]) begin + fu_data_n[i].imm = imm_forward_rs3; + end + + // use the PC as operand a + if (issue_instr_i[i].use_pc) begin + fu_data_n[i].operand_a = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{issue_instr_i[i].pc[CVA6Cfg.VLEN-1]}}, issue_instr_i[i].pc + }; + end + + // use the zimm as operand a + if (issue_instr_i[i].use_zimm) begin + // zero extend operand a + fu_data_n[i].operand_a = {{CVA6Cfg.XLEN - 5{1'b0}}, issue_instr_i[i].rs1[4:0]}; + end + // or is it an immediate (including PC), this is not the case for a store, control flow, and accelerator instructions + // also make sure operand B is not already used as an FP operand + if (issue_instr_i[i].use_imm && (issue_instr_i[i].fu != STORE) && (issue_instr_i[i].fu != CTRL_FLOW) && (issue_instr_i[i].fu != ACCEL) && !(CVA6Cfg.FpPresent && is_rs2_fpr( + issue_instr_i[i].op + ))) begin + fu_data_n[i].operand_b = issue_instr_i[i].result; + end + end + end + + always_comb begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + fpu_fmt_n = '0; + fpu_rm_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin + case (issue_instr_i[i].fu) + ALU: begin + if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + alu2_valid_n[i] = 1'b1; + end else begin + alu_valid_n[i] = 1'b1; + end + end + CTRL_FLOW: begin + branch_valid_n[i] = 1'b1; + end + MULT: begin + mult_valid_n[i] = 1'b1; + end + LOAD, STORE: begin + lsu_valid_n[i] = 1'b1; + end + CSR: begin + csr_valid_n[i] = 1'b1; + end + default: begin + if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rftype.fmt; // fmt bits from instruction + fpu_rm_n = orig_instr.rftype.rm; // rm bits from instruction + end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin + fpu_valid_n[i] = 1'b1; + fpu_fmt_n = orig_instr.rvftype.vfmt; // vfmt bits from instruction + fpu_rm_n = {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction + end + end + endcase + end + end + // if we got a flush request, de-assert the valid flag, otherwise we will start this + // functional unit with the wrong inputs + if (flush_i) begin + alu_valid_n = '0; + lsu_valid_n = '0; + mult_valid_n = '0; + fpu_valid_n = '0; + alu2_valid_n = '0; + csr_valid_n = '0; + branch_valid_n = '0; + end + end + // FU select, assert the correct valid out signal (in the next cycle) + // This needs to be like this to make verilator happy. I know its ugly. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + alu_valid_q <= '0; + lsu_valid_q <= '0; + mult_valid_q <= '0; + fpu_valid_q <= '0; + fpu_fmt_q <= '0; + fpu_rm_q <= '0; + alu2_valid_q <= '0; + csr_valid_q <= '0; + branch_valid_q <= '0; + end else begin + alu_valid_q <= alu_valid_n; + lsu_valid_q <= lsu_valid_n; + mult_valid_q <= mult_valid_n; + fpu_valid_q <= fpu_valid_n; + fpu_fmt_q <= fpu_fmt_n; + fpu_rm_q <= fpu_rm_n; + alu2_valid_q <= alu2_valid_n; + csr_valid_q <= csr_valid_n; + branch_valid_q <= branch_valid_n; + end + end + + if (CVA6Cfg.CvxifEn) begin + always_comb begin + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin + case (issue_instr_i[i].fu) + CVXIF: begin + cvxif_valid_n[i] = 1'b1; + cvxif_off_instr_n = orig_instr[i]; + end + default: ; + endcase + end + end + if (flush_i) begin + cvxif_valid_n = '0; + cvxif_off_instr_n = 32'b0; + end + end + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cvxif_valid_q <= '0; + cvxif_off_instr_q <= 32'b0; + end else begin + cvxif_valid_q <= cvxif_valid_n; + cvxif_off_instr_q <= cvxif_off_instr_n; + end + end + end + + always_comb begin : gen_check_waw_dependencies + stall_waw = '1; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (issue_instr_valid_i[i] && !fu_busy[i]) begin + // ----------------------------------------- + // WAW - Write After Write Dependency Check + // ----------------------------------------- + // no other instruction has the same destination register -> issue the instruction + if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + issue_instr_i[i].op + )) ? (rd_clobber_fpr[issue_instr_i[i].rd] == NONE) : + (rd_clobber_gpr[issue_instr_i[i].rd] == NONE)) begin + stall_waw[i] = 1'b0; + end + // or check that the target destination register will be written in this cycle by the + // commit stage + for (int unsigned c = 0; c < CVA6Cfg.NrCommitPorts; c++) begin + if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + issue_instr_i[i].op + )) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd) : + (we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd)) begin + stall_waw[i] = 1'b0; + end + end + if (i > 0) begin + if ((issue_instr_i[i].rd == issue_instr_i[i-1].rd) && (issue_instr_i[i].rd != '0)) begin + stall_waw[i] = 1'b1; + end + end + end + end + end + + + // We can issue an instruction if we do not detect that any other instruction is writing the same + // destination register. + // We also need to check if there is an unresolved branch in the scoreboard. + always_comb begin : issue_scoreboard + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + // default assignment + issue_ack[i] = 1'b0; + // check that the instruction we got is valid + // and that the functional unit we need is not busy + if (issue_instr_valid_i[i] && !fu_busy[i]) begin + if (!stall_raw[i] && !stall_waw[i]) begin + issue_ack[i] = 1'b1; + end + if (issue_instr_i[i].ex.valid) begin + issue_ack[i] = 1'b1; + end + end + end + + issue_ack_o = issue_ack; + // Do not acknoledge the issued instruction if transaction is not completed. + if (issue_instr_i[0].fu == CVXIF && !(x_transaction_accepted_o || x_transaction_rejected)) begin + issue_ack_o[0] = issue_instr_i[0].ex.valid && issue_instr_valid_i[0]; + end + if (CVA6Cfg.SuperscalarEn) begin + if (!issue_ack_o[0]) begin + issue_ack_o[1] = 1'b0; + end + end + end + + // ---------------------- + // Integer Register File + // ---------------------- + logic [ CVA6Cfg.NrRgprPorts-1:0][CVA6Cfg.XLEN-1:0] rdata; + logic [ CVA6Cfg.NrRgprPorts-1:0][ 4:0] raddr_pack; + + // pack signals + logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_pack; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_pack; + logic [CVA6Cfg.NrCommitPorts-1:0] we_pack; + + //adjust address to read from register file (when synchronous RAM is used reads take one cycle, so we advance the address) + for (genvar i = 0; i <= CVA6Cfg.NrIssuePorts - 1; i++) begin + assign raddr_pack[i*OPERANDS_PER_INSTR+0] = CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn ? issue_instr_i_prev[i].rs1[4:0] : issue_instr_i[i].rs1[4:0]; + assign raddr_pack[i*OPERANDS_PER_INSTR+1] = CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn ? issue_instr_i_prev[i].rs2[4:0] : issue_instr_i[i].rs2[4:0]; + if (OPERANDS_PER_INSTR == 3) begin + assign raddr_pack[i*OPERANDS_PER_INSTR+2] = CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn ? issue_instr_i_prev[i].result[4:0] : issue_instr_i[i].result[4:0]; + end + end + + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_write_back_port + assign waddr_pack[i] = waddr_i[i]; + assign wdata_pack[i] = wdata_i[i]; + assign we_pack[i] = we_gpr_i[i]; + end + if (CVA6Cfg.FpgaEn) begin : gen_fpga_regfile + ariane_regfile_fpga #( + .CVA6Cfg (CVA6Cfg), + .DATA_WIDTH (CVA6Cfg.XLEN), + .NR_READ_PORTS(CVA6Cfg.NrRgprPorts), + .ZERO_REG_ZERO(1) + ) i_ariane_regfile_fpga ( + .clk_i, + .rst_ni, + .test_en_i(1'b0), + .raddr_i (raddr_pack), + .rdata_o (rdata), + .waddr_i (waddr_pack), + .wdata_i (wdata_pack), + .we_i (we_pack) + ); + end else begin : gen_asic_regfile + ariane_regfile #( + .CVA6Cfg (CVA6Cfg), + .DATA_WIDTH (CVA6Cfg.XLEN), + .NR_READ_PORTS(CVA6Cfg.NrRgprPorts), + .ZERO_REG_ZERO(1) + ) i_ariane_regfile ( + .clk_i, + .rst_ni, + .test_en_i(1'b0), + .raddr_i (raddr_pack), + .rdata_o (rdata), + .waddr_i (waddr_pack), + .wdata_i (wdata_pack), + .we_i (we_pack) + ); + end + + // ----------------------------- + // Floating-Point Register File + // ----------------------------- + logic [2:0][CVA6Cfg.FLen-1:0] fprdata; + + // pack signals + logic [2:0][4:0] fp_raddr_pack; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] fp_wdata_pack; + + always_comb begin : assign_fp_raddr_pack + fp_raddr_pack = { + issue_instr_i[0].result[4:0], issue_instr_i[0].rs2[4:0], issue_instr_i[0].rs1[4:0] + }; + + if (CVA6Cfg.SuperscalarEn) begin + if (!(issue_instr_i[0].fu inside {FPU, FPU_VEC})) begin + fp_raddr_pack = { + issue_instr_i[1].result[4:0], issue_instr_i[1].rs2[4:0], issue_instr_i[1].rs1[4:0] + }; + end + end + end + + generate + if (CVA6Cfg.FpPresent) begin : float_regfile_gen + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_fp_wdata_pack + assign fp_wdata_pack[i] = {wdata_i[i][CVA6Cfg.FLen-1:0]}; + end + if (CVA6Cfg.FpgaEn) begin : gen_fpga_fp_regfile + ariane_regfile_fpga #( + .CVA6Cfg (CVA6Cfg), + .DATA_WIDTH (CVA6Cfg.FLen), + .NR_READ_PORTS(3), + .ZERO_REG_ZERO(0) + ) i_ariane_fp_regfile_fpga ( + .clk_i, + .rst_ni, + .test_en_i(1'b0), + .raddr_i (fp_raddr_pack), + .rdata_o (fprdata), + .waddr_i (waddr_pack), + .wdata_i (fp_wdata_pack), + .we_i (we_fpr_i) + ); + end else begin : gen_asic_fp_regfile + ariane_regfile #( + .CVA6Cfg (CVA6Cfg), + .DATA_WIDTH (CVA6Cfg.FLen), + .NR_READ_PORTS(3), + .ZERO_REG_ZERO(0) + ) i_ariane_fp_regfile ( + .clk_i, + .rst_ni, + .test_en_i(1'b0), + .raddr_i (fp_raddr_pack), + .rdata_o (fprdata), + .waddr_i (waddr_pack), + .wdata_i (fp_wdata_pack), + .we_i (we_fpr_i) + ); + end + end else begin : no_fpr_gen + assign fprdata = '{default: '0}; + end + endgenerate + + if (OPERANDS_PER_INSTR == 3) begin : gen_operand_c + assign operand_c_fpr = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[2]}; + end else begin + assign operand_c_fpr = fprdata[2]; + end + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (OPERANDS_PER_INSTR == 3) begin : gen_operand_c + assign operand_c_gpr[i] = rdata[i*OPERANDS_PER_INSTR+2]; + end + + assign operand_a_regfile[i] = (CVA6Cfg.FpPresent && is_rs1_fpr( + issue_instr_i[i].op + )) ? {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[i*OPERANDS_PER_INSTR+0]; + assign operand_b_regfile[i] = (CVA6Cfg.FpPresent && is_rs2_fpr( + issue_instr_i[i].op + )) ? {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[i*OPERANDS_PER_INSTR+1]; + assign operand_c_regfile[i] = (OPERANDS_PER_INSTR == 3) ? ((CVA6Cfg.FpPresent && is_imm_fpr( + issue_instr_i[i].op + )) ? operand_c_fpr : operand_c_gpr[i]) : operand_c_fpr; + end + + // ---------------------- + // Registers (ID <-> EX) + // ---------------------- + + always_comb begin + pc_n = '0; + is_compressed_instr_n = 1'b0; + branch_predict_n = {cf_t'(0), {CVA6Cfg.VLEN{1'b0}}}; + if (CVA6Cfg.SuperscalarEn) begin + if (issue_instr_i[1].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[1].pc; + is_compressed_instr_n = issue_instr_i[1].is_compressed; + branch_predict_n = issue_instr_i[1].bp; + end + end + if (issue_instr_i[0].fu == CTRL_FLOW) begin + pc_n = issue_instr_i[0].pc; + is_compressed_instr_n = issue_instr_i[0].is_compressed; + branch_predict_n = issue_instr_i[0].bp; + end + x_transaction_rejected_n = 1'b0; + if (issue_instr_i[0].fu == CVXIF) begin + x_transaction_rejected_n = x_transaction_rejected; + end + end + + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + fu_data_q <= '0; + if (CVA6Cfg.RVH) begin + tinst_q <= '0; + end + pc_o <= '0; + is_zcmt_o <= '0; + is_compressed_instr_o <= 1'b0; + branch_predict_o <= {cf_t'(0), {CVA6Cfg.VLEN{1'b0}}}; + x_transaction_rejected_o <= 1'b0; + end else begin + fu_data_q <= fu_data_n; + if (CVA6Cfg.RVH) begin + tinst_q <= tinst_n; + end + if (CVA6Cfg.SuperscalarEn) begin + if (issue_instr_i[1].fu == CTRL_FLOW) begin + pc_o <= issue_instr_i[1].pc; + is_compressed_instr_o <= issue_instr_i[1].is_compressed; + branch_predict_o <= issue_instr_i[1].bp; + end + end + if (issue_instr_i[0].fu == CTRL_FLOW) begin + pc_o <= issue_instr_i[0].pc; + is_compressed_instr_o <= issue_instr_i[0].is_compressed; + branch_predict_o <= issue_instr_i[0].bp; + if (CVA6Cfg.RVZCMT) is_zcmt_o <= issue_instr_i[0].is_zcmt; + else is_zcmt_o <= '0; + end + x_transaction_rejected_o <= 1'b0; + if (issue_instr_i[0].fu == CVXIF) begin + x_transaction_rejected_o <= x_transaction_rejected; + end + end + end + + //pragma translate_off + initial begin + assert (OPERANDS_PER_INSTR == 2 || (OPERANDS_PER_INSTR == 3 && CVA6Cfg.CvxifEn)) + else + $fatal( + 1, + "If CVXIF is enable, ariane regfile can have either 2 or 3 read ports. Else it has 2 read ports." + ); + end + + // FPU does not declare that it will return a result the subsequent cycle so + // it is not possible for issue stage to know when ALU2 can be used if there + // is an FPU. As there are discussions to change the FPU, I did not explore + // its architecture to create this "FPU returns next cycle" signal. Also, a + // "lookahead" optimization should be added to be performant with FPU: when + // issue port 2 is issuing to FPU, issue port 1 should issue to ALU1 instead + // of ALU2 so that FPU is not busy. However, if FPU has a minimum execution + // time of 2 cycles, it is possible to simply not raise fus_busy[1].alu2. + initial begin + assert (!(CVA6Cfg.SuperscalarEn && CVA6Cfg.FpPresent)) + else + $fatal(1, "FPU is not yet supported in superscalar CVA6, see comments above this assertion."); + end + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assert property (@(posedge clk_i) (branch_valid_q) |-> (!$isunknown( + fu_data_q[i].operand_a + ) && !$isunknown( + fu_data_q[i].operand_b + ))) + else $warning("Got unknown value in one of the operands"); + end + //pragma translate_on + +endmodule diff --git a/flow/designs/src/cva6/core/issue_stage.sv b/flow/designs/src/cva6/core/issue_stage.sv new file mode 100644 index 0000000000..4ffc5382e8 --- /dev/null +++ b/flow/designs/src/cva6/core/issue_stage.sv @@ -0,0 +1,306 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 21.05.2017 +// Description: Issue stage dispatches instructions to the FUs and keeps track of them +// in a scoreboard like data-structure. + + +module issue_stage + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, + parameter type fu_data_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type writeback_t = logic, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type x_commit_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Is scoreboard full - PERF_COUNTERS + output logic sb_full_o, + // Prevent from issuing - CONTROLLER + input logic flush_unissued_instr_i, + // Flush whole scoreboard - CONTROLLER + input logic flush_i, + // Stall inserted by Acc dispatcher - ACC_DISPATCHER + input logic stall_i, + // Handshake's data with decode stage - ID_STAGE + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i_prev, + // instruction value - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i, + // Handshake's valid with decode stage - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, + // Is instruction a control flow instruction - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_i, + // Handshake's acknowlege with decode stage - ID_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o, + // rs1 forwarding - EX_STAGE + output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o, + // rs2 forwarding - EX_STAGE + output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o, + // FU data useful to execute instruction - EX_STAGE + output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o, + // Program Counter - EX_STAGE + output logic [CVA6Cfg.VLEN-1:0] pc_o, + // Is zcmt instruction - EX_STAGE + output logic is_zcmt_o, + // Is compressed instruction - EX_STAGE + output logic is_compressed_instr_o, + // Transformed trap instruction - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o, + // Fixed Latency Unit is ready - EX_STAGE + input logic flu_ready_i, + // ALU output is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o, + // Branch unit is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, + // Information of branch prediction - EX_STAGE + output branchpredict_sbe_t branch_predict_o, + // Signaling that we resolved the branch - EX_STAGE + input logic resolve_branch_i, + // Load store unit FU is ready - EX_STAGE + input logic lsu_ready_i, + // Load store unit FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o, + // Mult FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o, + // FPU FU is ready - EX_STAGE + input logic fpu_ready_i, + // FPU FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o, + // FPU fmt field - EX_STAGE + output logic [1:0] fpu_fmt_o, + // FPU rm field - EX_STAGE + output logic [2:0] fpu_rm_o, + // ALU2 FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o, + // CSR is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_o, + // CVXIF FU is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] xfu_valid_o, + // CVXIF is FU ready - EX_STAGE + input logic xfu_ready_i, + // CVXIF offloader instruction value - EX_STAGE + output logic [31:0] x_off_instr_o, + // CVA6 Hart ID - SUBSYSTEM + input logic [CVA6Cfg.XLEN-1:0] hart_id_i, + // CVXIF Issue interface - EX_STAGE + input logic x_issue_ready_i, + // TO_BE_COMPLETED - EX_STAGE + input x_issue_resp_t x_issue_resp_i, + // TO_BE_COMPLETED - EX_STAGE + output logic x_issue_valid_o, + // TO_BE_COMPLETED - EX_STAGE + output x_issue_req_t x_issue_req_o, + // CVXIF Register interface - EX_STAGE + input logic x_register_ready_i, + // TO_BE_COMPLETED - EX_STAGE + output logic x_register_valid_o, + // TO_BE_COMPLETED - EX_STAGE + output x_register_t x_register_o, + // CVXIF Commit interface - EX_STAGE + output logic x_commit_valid_o, + // TO_BE_COMPLETED - EX_STAGE + output x_commit_t x_commit_o, + // CVXIF Transaction rejected -> instruction is illegal - EX_STAGE + output logic x_transaction_rejected_o, + // Issue scoreboard entry - ACC_DISPATCHER + output scoreboard_entry_t issue_instr_o, + // TO_BE_COMPLETED - ACC_DISPATCHER + output logic issue_instr_hs_o, + // Transaction ID - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i, + // Result from branch unit - EX_STAGE + input bp_resolve_t resolved_branch_i, + // Results to write back - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i, + // exception from execute stage or CVXIF - EX_STAGE + input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i, + // Indicates valid results - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, + // CVXIF write enable - EX_STAGE + input logic x_we_i, + // CVXIF destination register - EX_STAGE + input logic [4:0] x_rd_i, + // Destination register in register file - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i, + // Value to write to register file - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i, + // GPR write enable - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i, + // FPR write enable - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, + // Instructions to commit - COMMIT_STAGE + output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, + // Instruction is cancelled - COMMIT_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_o, + // Commit acknowledge - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + // Issue stall - PERF_COUNTERS + output logic stall_issue_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, + // Information dedicated to RVFI - RVFI + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o +); + // --------------------------------------------------- + // Scoreboard (SB) <-> Issue and Read Operands (IRO) + // --------------------------------------------------- + typedef logic [(CVA6Cfg.NrRgprPorts == 3 ? CVA6Cfg.XLEN : CVA6Cfg.FLen)-1:0] rs3_len_t; + typedef struct packed { + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer; + writeback_t [CVA6Cfg.NrWbPorts-1:0] wb; + scoreboard_entry_t [CVA6Cfg.NR_SB_ENTRIES-1:0] sbe; + } forwarding_t; + + forwarding_t fwd; + scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_sb_iro; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_sb_iro; + logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_sb_iro; + logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_iro_sb; + + assign issue_instr_o = issue_instr_sb_iro[0]; + assign issue_instr_hs_o = issue_instr_valid_sb_iro[0] & issue_ack_iro_sb[0]; + + logic x_transaction_accepted_iro_sb, x_issue_writeback_iro_sb; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_iro_sb; + + // --------------------------------------------------------- + // 2. Manage instructions in a scoreboard + // --------------------------------------------------------- + scoreboard #( + .CVA6Cfg (CVA6Cfg), + .rs3_len_t (rs3_len_t), + .bp_resolve_t(bp_resolve_t), + .writeback_t(writeback_t), + .forwarding_t(forwarding_t), + .exception_t(exception_t), + .scoreboard_entry_t(scoreboard_entry_t) + ) i_scoreboard ( + .clk_i, + .rst_ni, + .sb_full_o (sb_full_o), + .flush_unissued_instr_i, + .flush_i, + .x_transaction_accepted_i(x_transaction_accepted_iro_sb), + .x_issue_writeback_i (x_issue_writeback_iro_sb), + .x_id_i (x_id_iro_sb), + .commit_instr_o, + .commit_drop_o, + .commit_ack_i, + .decoded_instr_i (decoded_instr_i), + .orig_instr_i, + .decoded_instr_valid_i (decoded_instr_valid_i), + .decoded_instr_ack_o (decoded_instr_ack_o), + .issue_instr_o (issue_instr_sb_iro), + .orig_instr_o (orig_instr_sb_iro), + .issue_instr_valid_o (issue_instr_valid_sb_iro), + .issue_ack_i (issue_ack_iro_sb), + .fwd_o (fwd), + .resolved_branch_i (resolved_branch_i), + .trans_id_i (trans_id_i), + .wbdata_i (wbdata_i), + .ex_i (ex_ex_i), + .wt_valid_i, + .x_we_i, + .x_rd_i, + .rvfi_issue_pointer_o, + .rvfi_commit_pointer_o + ); + + // --------------------------------------------------------- + // 3. Issue instruction and read operand, also commit + // --------------------------------------------------------- + issue_read_operands #( + .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), + .fu_data_t(fu_data_t), + .scoreboard_entry_t(scoreboard_entry_t), + .rs3_len_t(rs3_len_t), + .writeback_t(writeback_t), + .forwarding_t(forwarding_t), + .x_issue_req_t(x_issue_req_t), + .x_issue_resp_t(x_issue_resp_t), + .x_register_t(x_register_t), + .x_commit_t(x_commit_t) + ) i_issue_read_operands ( + .clk_i, + .rst_ni, + .flush_i (flush_unissued_instr_i), + .stall_i, + .issue_instr_i (issue_instr_sb_iro), + .issue_instr_i_prev (decoded_instr_i_prev), + .orig_instr_i (orig_instr_sb_iro), + .issue_instr_valid_i (issue_instr_valid_sb_iro), + .issue_ack_o (issue_ack_iro_sb), + .fwd_i (fwd), + .fu_data_o (fu_data_o), + .rs1_forwarding_o (rs1_forwarding_o), + .rs2_forwarding_o (rs2_forwarding_o), + .pc_o, + .is_zcmt_o, + .is_compressed_instr_o, + .flu_ready_i (flu_ready_i), + .alu_valid_o (alu_valid_o), + .branch_valid_o (branch_valid_o), + .tinst_o (tinst_o), + .branch_predict_o, + .lsu_ready_i, + .lsu_valid_o, + .mult_valid_o, + .fpu_ready_i, + .fpu_valid_o, + .fpu_fmt_o, + .fpu_rm_o, + .alu2_valid_o, + .csr_valid_o, + .cvxif_valid_o (xfu_valid_o), + .cvxif_ready_i (xfu_ready_i), + .cvxif_off_instr_o (x_off_instr_o), + .hart_id_i (hart_id_i), + .x_issue_ready_i (x_issue_ready_i), + .x_issue_resp_i (x_issue_resp_i), + .x_issue_valid_o (x_issue_valid_o), + .x_issue_req_o (x_issue_req_o), + .x_register_ready_i (x_register_ready_i), + .x_register_valid_o (x_register_valid_o), + .x_register_o (x_register_o), + .x_commit_valid_o (x_commit_valid_o), + .x_commit_o (x_commit_o), + .x_transaction_accepted_o(x_transaction_accepted_iro_sb), + .x_transaction_rejected_o(x_transaction_rejected_o), + .x_issue_writeback_o (x_issue_writeback_iro_sb), + .x_id_o (x_id_iro_sb), + .waddr_i, + .wdata_i, + .we_gpr_i, + .we_fpr_i, + .stall_issue_o, + .rvfi_rs1_o (rvfi_rs1_o), + .rvfi_rs2_o (rvfi_rs2_o) + ); + +endmodule diff --git a/flow/designs/src/cva6/core/load_store_unit.sv b/flow/designs/src/cva6/core/load_store_unit.sv new file mode 100644 index 0000000000..ccce630112 --- /dev/null +++ b/flow/designs/src/cva6/core/load_store_unit.sv @@ -0,0 +1,876 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 19.04.2017 +// Description: Load Store Unit, handles address calculation and memory interface signals + + +module load_store_unit + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type fu_data_t = logic, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, + parameter type lsu_ctrl_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic flush_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic stall_st_pending_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic no_st_pending_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic amo_valid_commit_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [31:0] tinst_i, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // Load Store Unit is ready - ISSUE_STAGE + output logic lsu_ready_o, + // Load Store Unit instruction is valid - ISSUE_STAGE + input logic lsu_valid_i, + + // Load transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o, + // Load result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] load_result_o, + // Load result is valid - ISSUE_STAGE + output logic load_valid_o, + // Load exception - ISSUE_STAGE + output exception_t load_exception_o, + + // Store transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_o, + // Store result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] store_result_o, + // Store result is valid - ISSUE_STAGE + output logic store_valid_o, + // Store exception - ISSUE_STAGE + output exception_t store_exception_o, + + // Commit the first pending store - TO_BE_COMPLETED + input logic commit_i, + // Commit queue is ready to accept another commit request - TO_BE_COMPLETED + output logic commit_ready_o, + // Commit transaction ID - TO_BE_COMPLETED + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i, + + // Enable virtual memory translation - TO_BE_COMPLETED + input logic enable_translation_i, + // Enable G-Stage memory translation - TO_BE_COMPLETED + input logic enable_g_translation_i, + // Enable virtual memory translation for load/stores - TO_BE_COMPLETED + input logic en_ld_st_translation_i, + // Enable G-Stage memory translation for load/stores - TO_BE_COMPLETED + input logic en_ld_st_g_translation_i, + + // Accelerator request for CVA6's MMU + input acc_mmu_req_t acc_mmu_req_i, + output acc_mmu_resp_t acc_mmu_resp_o, + + // Instruction cache input request - CACHES + input icache_arsp_t icache_areq_i, + // Instruction cache output request - CACHES + output icache_areq_t icache_areq_o, + + // Current privilege mode - CSR_REGFILE + input riscv::priv_lvl_t priv_lvl_i, + // Current virtualization mode - CSR_REGFILE + input logic v_i, + // Privilege level at which load and stores should happen - CSR_REGFILE + input riscv::priv_lvl_t ld_st_priv_lvl_i, + // Virtualization mode at which load and stores should happen - CSR_REGFILE + input logic ld_st_v_i, + // Instruction is a hyp load/store - CSR_REGFILE + output logic csr_hs_ld_st_inst_o, + // Supervisor User Memory - CSR_REGFILE + input logic sum_i, + // Virtual Supervisor User Memory - CSR_REGFILE + input logic vs_sum_i, + // Make Executable Readable - CSR_REGFILE + input logic mxr_i, + // Make Executable Readable Virtual Supervisor - CSR_REGFILE + input logic vmxr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ CVA6Cfg.PPNW-1:0] satp_ppn_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ CVA6Cfg.PPNW-1:0] vsatp_ppn_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ CVA6Cfg.PPNW-1:0] hgatp_ppn_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed_i, + // TLB flush - CONTROLLER + input logic flush_tlb_i, + input logic flush_tlb_vvma_i, + input logic flush_tlb_gvma_i, + // Instruction TLB miss - PERF_COUNTERS + output logic itlb_miss_o, + // Data TLB miss - PERF_COUNTERS + output logic dtlb_miss_o, + + // Data cache request output - CACHES + input dcache_req_o_t [2:0] dcache_req_ports_i, + // Data cache request input - CACHES + output dcache_req_i_t [2:0] dcache_req_ports_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic dcache_wbuffer_empty_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic dcache_wbuffer_not_ni_i, + // AMO request - CACHE + output amo_req_t amo_req_o, + // AMO response - CACHE + input amo_resp_t amo_resp_i, + + // PMP configuration - CSR_REGFILE + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + // PMP address - CSR_REGFILE + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + + // RVFI inforamtion - RVFI + output lsu_ctrl_t rvfi_lsu_ctrl_o, + // RVFI information - RVFI + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o +); + + // data is misaligned + logic data_misaligned; + // -------------------------------------- + // 1st register stage - (stall registers) + // -------------------------------------- + // those are the signals which are always correct + // e.g.: they keep the value in the stall case + lsu_ctrl_t lsu_ctrl, lsu_ctrl_byp; + + logic pop_st; + logic pop_ld; + + // ------------------------------ + // Address Generation Unit (AGU) + // ------------------------------ + // virtual address as calculated by the AGU in the first cycle + logic [ CVA6Cfg.VLEN-1:0] vaddr_i; + logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen; + logic overflow; + logic g_overflow; + logic [(CVA6Cfg.XLEN/8)-1:0] be_i; + + assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); + assign vaddr_i = vaddr_xlen[CVA6Cfg.VLEN-1:0]; + // we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal + assign overflow = (CVA6Cfg.IS_XLEN64 && (!((&vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b0))); + if (CVA6Cfg.RVH) begin : gen_g_overflow_hyp + assign g_overflow = (CVA6Cfg.IS_XLEN64 && (!((|vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SVX]) == 1'b0))); + end else begin : gen_g_overflow_no_hyp + assign g_overflow = 1'b0; + end + + logic st_valid_i; + logic ld_valid_i; + logic ld_translation_req; + logic st_translation_req, cva6_st_translation_req, acc_st_translation_req; + logic [CVA6Cfg.VLEN-1:0] ld_vaddr; + logic [ 31:0] ld_tinst; + logic ld_hs_ld_st_inst; + logic ld_hlvx_inst; + logic [CVA6Cfg.VLEN-1:0] st_vaddr; + logic [ 31:0] st_tinst; + logic st_hs_ld_st_inst; + logic st_hlvx_inst; + logic translation_req, cva6_translation_req, acc_translation_req; + logic translation_valid, cva6_translation_valid, acc_translataion_valid; + logic [CVA6Cfg.VLEN-1:0] mmu_vaddr, cva6_mmu_vaddr, acc_mmu_vaddr; + logic [CVA6Cfg.PLEN-1:0] mmu_paddr, cva6_mmu_paddr, acc_mmu_paddr, lsu_paddr; + logic [31:0] mmu_tinst; + logic mmu_hs_ld_st_inst; + logic mmu_hlvx_inst; + exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; + exception_t pmp_exception; + icache_areq_t pmp_icache_areq_i; + logic pmp_translation_valid; + logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; + logic [CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; + + logic ld_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; + logic [ CVA6Cfg.XLEN-1:0] ld_result; + logic st_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; + logic [ CVA6Cfg.XLEN-1:0] st_result; + + logic [ 11:0] page_offset; + logic page_offset_matches; + + exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; + exception_t ld_ex; + exception_t st_ex; + + logic hs_ld_st_inst; + logic hlvx_inst; + logic [1:0] sum, mxr; + logic [CVA6Cfg.PPNW-1:0] satp_ppn[2:0]; + logic [CVA6Cfg.ASID_WIDTH-1:0] asid[2:0], asid_to_be_flushed[1:0]; + logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed[1:0]; + + // ------------------- + // MMU e.g.: TLBs/PTW + // ------------------- + + if (CVA6Cfg.MmuPresent) begin : gen_mmu + localparam HYP_EXT = CVA6Cfg.RVH ? 1 : 0; + + cva6_mmu #( + .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), + .icache_areq_t (icache_areq_t), + .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .HYP_EXT (HYP_EXT) + ) i_cva6_mmu ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(flush_i), + .enable_translation_i(enable_translation_i), + .enable_g_translation_i(enable_g_translation_i), + .en_ld_st_translation_i(en_ld_st_translation_i), + .en_ld_st_g_translation_i(en_ld_st_g_translation_i), + .icache_areq_i(icache_areq_i), + .icache_areq_o(pmp_icache_areq_i), + // misaligned bypass + .misaligned_ex_i(misaligned_exception), + .lsu_req_i(translation_req), + .lsu_vaddr_i(mmu_vaddr), + .lsu_tinst_i(mmu_tinst), + .lsu_is_store_i(st_translation_req), + .csr_hs_ld_st_inst_o(csr_hs_ld_st_inst_o), + .lsu_dtlb_hit_o(dtlb_hit), // send in the same cycle as the request + .lsu_dtlb_ppn_o(dtlb_ppn), // send in the same cycle as the request + + .lsu_valid_o (pmp_translation_valid), + .lsu_paddr_o (lsu_paddr), + .lsu_exception_o(pmp_exception), + + .priv_lvl_i (priv_lvl_i), + .v_i, + .ld_st_priv_lvl_i(ld_st_priv_lvl_i), + .ld_st_v_i, + .sum_i, + .vs_sum_i, + .mxr_i, + .vmxr_i, + + .hlvx_inst_i (mmu_hlvx_inst), + .hs_ld_st_inst_i(mmu_hs_ld_st_inst), + .satp_ppn_i, + .vsatp_ppn_i, + .hgatp_ppn_i, + .asid_i, + .vs_asid_i, + .asid_to_be_flushed_i, + .vmid_i, + .vmid_to_be_flushed_i, + .vaddr_to_be_flushed_i, + .gpaddr_to_be_flushed_i, + .flush_tlb_i, + .flush_tlb_vvma_i, + .flush_tlb_gvma_i, + + .itlb_miss_o(itlb_miss_o), + .dtlb_miss_o(dtlb_miss_o), + + .req_port_i(dcache_req_ports_i[0]), + .req_port_o(dcache_req_ports_o[0]), + + .pmpcfg_i, + .pmpaddr_i + ); + end else begin : gen_no_mmu + // icache request without MMU, virtual and physical address are identical + assign pmp_icache_areq_i.fetch_valid = icache_areq_i.fetch_req; + if (CVA6Cfg.VLEN >= CVA6Cfg.PLEN) begin : gen_virtual_physical_address_instruction_vlen_greater + assign pmp_icache_areq_i.fetch_paddr = icache_areq_i.fetch_vaddr[CVA6Cfg.PLEN-1:0]; + end else begin : gen_virtual_physical_address_instruction_plen_greater + assign pmp_icache_areq_i.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr); + end + assign pmp_icache_areq_i.fetch_exception = 'h0; + // dcache request without mmu for load or store, + // Delay of 1 cycle to match MMU latency giving the address tag + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + lsu_paddr <= '0; + pmp_exception <= '0; + pmp_translation_valid <= 1'b0; + end else begin + if (CVA6Cfg.VLEN >= CVA6Cfg.PLEN) begin : gen_virtual_physical_address_lsu + lsu_paddr <= mmu_vaddr[CVA6Cfg.PLEN-1:0]; + end else begin + lsu_paddr <= CVA6Cfg.PLEN'(mmu_vaddr); + end + pmp_exception <= misaligned_exception; + pmp_translation_valid <= translation_req; + end + end + + // dcache interface of PTW not used + assign dcache_req_ports_o[0].address_index = '0; + assign dcache_req_ports_o[0].address_tag = '0; + assign dcache_req_ports_o[0].data_wdata = '0; + assign dcache_req_ports_o[0].data_req = 1'b0; + assign dcache_req_ports_o[0].data_be = '1; + assign dcache_req_ports_o[0].data_size = 2'b11; + assign dcache_req_ports_o[0].data_we = 1'b0; + assign dcache_req_ports_o[0].kill_req = '0; + assign dcache_req_ports_o[0].tag_valid = 1'b0; + + assign itlb_miss_o = 1'b0; + assign dtlb_miss_o = 1'b0; + assign dtlb_ppn = lsu_paddr[CVA6Cfg.PLEN-1:12]; + assign dtlb_hit = 1'b1; + + end + + // ------------------ + // PMP + // ------------------ + + pmp_data_if #( + .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), + .exception_t (exception_t) + ) i_pmp_data_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .icache_areq_i (pmp_icache_areq_i), + .icache_areq_o (icache_areq_o), + .icache_fetch_vaddr_i(icache_areq_i.fetch_vaddr), + .lsu_valid_i (pmp_translation_valid), + .lsu_paddr_i (lsu_paddr), + .lsu_vaddr_i (mmu_vaddr), + .lsu_exception_i (pmp_exception), + .lsu_is_store_i (st_translation_req), + .lsu_valid_o (translation_valid), + .lsu_paddr_o (mmu_paddr), + .lsu_exception_o (mmu_exception), + .priv_lvl_i (priv_lvl_i), + .v_i (v_i), + .ld_st_priv_lvl_i (ld_st_priv_lvl_i), + .ld_st_v_i (ld_st_v_i), + .pmpcfg_i (pmpcfg_i), + .pmpaddr_i (pmpaddr_i) + ); + + // ------------------ + // External MMU port + // ------------------ + + if (CVA6Cfg.EnableAccelerator) begin + // The MMU can be connected to CVA6 or the ACCELERATOR + enum logic { + CVA6, + ACC + } + mmu_state_d, mmu_state_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mmu_state_q <= CVA6; + end else begin + mmu_state_q <= mmu_state_d; + end + end + // Straightforward and slow-reactive MMU arbitration logic + // This logic can be optimized to reduce answer latency and contention + always_comb begin + // Maintain state + mmu_state_d = mmu_state_q; + // Serve CVA6 and gate the accelerator by default + // MMU input + misaligned_exception = cva6_misaligned_exception; + st_translation_req = cva6_st_translation_req; + translation_req = cva6_translation_req; + mmu_vaddr = cva6_mmu_vaddr; + // MMU output + cva6_translation_valid = translation_valid; + cva6_mmu_paddr = mmu_paddr; + cva6_mmu_exception = mmu_exception; + cva6_dtlb_hit = dtlb_hit; + cva6_dtlb_ppn = dtlb_ppn; + acc_mmu_resp_o.acc_mmu_valid = '0; + acc_mmu_resp_o.acc_mmu_paddr = '0; + acc_mmu_resp_o.acc_mmu_exception = '0; + acc_mmu_resp_o.acc_mmu_dtlb_hit = '0; + acc_mmu_resp_o.acc_mmu_dtlb_ppn = '0; + unique case (mmu_state_q) + CVA6: begin + // Only the accelerator is requesting, and the lsu bypass queue is empty. + if (acc_mmu_req_i.acc_mmu_req && !lsu_valid_i && lsu_ready_o) begin + // Lock the MMU to the accelerator. + // If the issue stage is firing a mem op in this cycle, + // the bypass queue will buffer it. + mmu_state_d = ACC; + end + // Make this a mealy FSM to cut some latency. + // It should be okay timing-wise since cva6's requests already + // depend on lsu_valid_i. Moreover, lsu_ready_o is sequentially + // generated by the bypass and, in this first implementation, + // the acc request already depends combinatorially upon acc_mmu_req_i.acc_mmu_req. + end + ACC: begin + // MMU input + misaligned_exception = acc_mmu_req_i.acc_mmu_misaligned_ex; + st_translation_req = acc_mmu_req_i.acc_mmu_is_store; + translation_req = acc_mmu_req_i.acc_mmu_req; + mmu_vaddr = acc_mmu_req_i.acc_mmu_vaddr; + // MMU output + acc_mmu_resp_o.acc_mmu_valid = translation_valid; + acc_mmu_resp_o.acc_mmu_paddr = mmu_paddr; + acc_mmu_resp_o.acc_mmu_exception = mmu_exception; + acc_mmu_resp_o.acc_mmu_dtlb_hit = dtlb_hit; + acc_mmu_resp_o.acc_mmu_dtlb_ppn = dtlb_ppn; + cva6_translation_valid = '0; + cva6_mmu_paddr = '0; + cva6_mmu_exception = '0; + cva6_dtlb_hit = '0; + cva6_dtlb_ppn = '0; + // Get back to CVA6 after the translation + if (translation_valid) mmu_state_d = CVA6; + end + default: mmu_state_d = CVA6; + endcase + end + always_comb begin + // Feed forward + lsu_ctrl = lsu_ctrl_byp; + // Mask the lsu valid so that cva6's req gets buffered in the + // bypass queue when the MMU is being used by the accelerator. + lsu_ctrl.valid = (mmu_state_q == ACC) ? 1'b0 : lsu_ctrl_byp.valid; + end + end else begin + // MMU input + assign misaligned_exception = cva6_misaligned_exception; + assign st_translation_req = cva6_st_translation_req; + assign translation_req = cva6_translation_req; + assign mmu_vaddr = cva6_mmu_vaddr; + // MMU output + assign cva6_translation_valid = translation_valid; + assign cva6_mmu_paddr = mmu_paddr; + assign cva6_mmu_exception = mmu_exception; + assign cva6_dtlb_hit = dtlb_hit; + assign cva6_dtlb_ppn = dtlb_ppn; + // No accelerator + assign acc_mmu_resp_o = '0; + // Feed forward the lsu_ctrl bypass + assign lsu_ctrl = lsu_ctrl_byp; + end + + logic store_buffer_empty; + // ------------------ + // Store Unit + // ------------------ + store_unit #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), + .lsu_ctrl_t(lsu_ctrl_t) + ) i_store_unit ( + .clk_i, + .rst_ni, + .flush_i, + .stall_st_pending_i, + .no_st_pending_o, + .store_buffer_empty_o(store_buffer_empty), + + .valid_i (st_valid_i), + .lsu_ctrl_i(lsu_ctrl), + .pop_st_o (pop_st), + .commit_i, + .commit_ready_o, + .amo_valid_commit_i, + + .valid_o (st_valid), + .trans_id_o (st_trans_id), + .result_o (st_result), + .ex_o (st_ex), + // MMU port + .translation_req_o (cva6_st_translation_req), + .vaddr_o (st_vaddr), + .rvfi_mem_paddr_o (rvfi_mem_paddr_o), + .tinst_o (st_tinst), + .hs_ld_st_inst_o (st_hs_ld_st_inst), + .hlvx_inst_o (st_hlvx_inst), + .paddr_i (cva6_mmu_paddr), + .ex_i (cva6_mmu_exception), + .dtlb_hit_i (cva6_dtlb_hit), + // Load Unit + .page_offset_i (page_offset), + .page_offset_matches_o(page_offset_matches), + // AMOs + .amo_req_o, + .amo_resp_i, + // to memory arbiter + .req_port_i (dcache_req_ports_i[2]), + .req_port_o (dcache_req_ports_o[2]) + ); + + // ------------------ + // Load Unit + // ------------------ + load_unit #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), + .lsu_ctrl_t(lsu_ctrl_t) + ) i_load_unit ( + .clk_i, + .rst_ni, + .flush_i, + .valid_i (ld_valid_i), + .lsu_ctrl_i(lsu_ctrl), + .pop_ld_o (pop_ld), + + .valid_o (ld_valid), + .trans_id_o (ld_trans_id), + .result_o (ld_result), + .ex_o (ld_ex), + // MMU port + .translation_req_o (ld_translation_req), + .vaddr_o (ld_vaddr), + .tinst_o (ld_tinst), + .hs_ld_st_inst_o (ld_hs_ld_st_inst), + .hlvx_inst_o (ld_hlvx_inst), + .paddr_i (cva6_mmu_paddr), + .ex_i (cva6_mmu_exception), + .dtlb_hit_i (cva6_dtlb_hit), + .dtlb_ppn_i (cva6_dtlb_ppn), + // to store unit + .page_offset_o (page_offset), + .page_offset_matches_i(page_offset_matches), + .store_buffer_empty_i (store_buffer_empty), + .commit_tran_id_i, + // to memory arbiter + .req_port_i (dcache_req_ports_i[1]), + .req_port_o (dcache_req_ports_o[1]), + .dcache_wbuffer_not_ni_i + ); + + // ---------------------------- + // Output Pipeline Register + // ---------------------------- + + // amount of pipeline registers inserted for load/store return path + // can be tuned to trade-off IPC vs. cycle time + + shift_reg #( + .dtype(logic [$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1:0]), + .Depth(CVA6Cfg.NrLoadPipeRegs) + ) i_pipe_reg_load ( + .clk_i, + .rst_ni, + .d_i({ld_valid, ld_trans_id, ld_result, ld_ex}), + .d_o({load_valid_o, load_trans_id_o, load_result_o, load_exception_o}) + ); + + shift_reg #( + .dtype(logic [$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1:0]), + .Depth(CVA6Cfg.NrStorePipeRegs) + ) i_pipe_reg_store ( + .clk_i, + .rst_ni, + .d_i({st_valid, st_trans_id, st_result, st_ex}), + .d_o({store_valid_o, store_trans_id_o, store_result_o, store_exception_o}) + ); + + // determine whether this is a load or store + always_comb begin : which_op + + ld_valid_i = 1'b0; + st_valid_i = 1'b0; + + cva6_translation_req = 1'b0; + cva6_mmu_vaddr = {CVA6Cfg.VLEN{1'b0}}; + mmu_tinst = {32{1'b0}}; + mmu_hs_ld_st_inst = 1'b0; + mmu_hlvx_inst = 1'b0; + + // check the operation to activate the right functional unit accordingly + unique case (lsu_ctrl.fu) + // all loads go here + LOAD: begin + ld_valid_i = lsu_ctrl.valid; + cva6_translation_req = ld_translation_req; + cva6_mmu_vaddr = ld_vaddr; + if (CVA6Cfg.RVH) begin + mmu_tinst = ld_tinst; + mmu_hs_ld_st_inst = ld_hs_ld_st_inst; + mmu_hlvx_inst = ld_hlvx_inst; + end + end + // all stores go here + STORE: begin + st_valid_i = lsu_ctrl.valid; + cva6_translation_req = st_translation_req; + cva6_mmu_vaddr = st_vaddr; + if (CVA6Cfg.RVH) begin + mmu_tinst = st_tinst; + mmu_hs_ld_st_inst = st_hs_ld_st_inst; + mmu_hlvx_inst = st_hlvx_inst; + end + end + // not relevant for the LSU + default: ; + endcase + end + + // ------------------------ + // Hypervisor Load/Store + // ------------------------ + // determine whether this is a hypervisor load or store + if (CVA6Cfg.RVH) begin + always_comb begin : hyp_ld_st + // check the operator to activate the right functional unit accordingly + hs_ld_st_inst = 1'b0; + hlvx_inst = 1'b0; + case (lsu_ctrl.operation) + // all loads go here + HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HSV_B, HSV_H, HSV_W, HLV_WU, HLV_D, HSV_D: begin + hs_ld_st_inst = 1'b1; + end + HLVX_WU, HLVX_HU: begin + hs_ld_st_inst = 1'b1; + hlvx_inst = 1'b1; + end + default: ; + endcase + end + end else begin + assign hs_ld_st_inst = 1'b0; + assign hlvx_inst = 1'b0; + end + + // --------------- + // Byte Enable + // --------------- + // we can generate the byte enable from the virtual address since the last + // 12 bit are the same anyway + // and we can always generate the byte enable from the address at hand + + if (CVA6Cfg.IS_XLEN64) begin : gen_8b_be + assign be_i = be_gen(vaddr_i[2:0], extract_transfer_size(fu_data_i.operation)); + end else begin : gen_4b_be + assign be_i = be_gen_32(vaddr_i[1:0], extract_transfer_size(fu_data_i.operation)); + end + + // ------------------------ + // Misaligned Exception + // ------------------------ + // we can detect a misaligned exception immediately + // the misaligned exception is passed to the functional unit via the MMU, which in case + // can augment the exception if other memory related exceptions like a page fault or access errors + always_comb begin : data_misaligned_detection + cva6_misaligned_exception = { + {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.GPLEN{1'b0}}, {32{1'b0}}, 1'b0, 1'b0 + }; + data_misaligned = 1'b0; + + if (lsu_ctrl.valid) begin + if (CVA6Cfg.IS_XLEN64) begin + case (lsu_ctrl.operation) + // double word + LD, SD, FLD, FSD, + AMO_LRD, AMO_SCD, + AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD, + AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND, + AMO_MINDU, HLV_D, HSV_D: begin + if (lsu_ctrl.vaddr[2:0] != 3'b000) begin + data_misaligned = 1'b1; + end + end + default: ; + endcase + end + case (lsu_ctrl.operation) + // word + LW, LWU, SW, FLW, FSW, + AMO_LRW, AMO_SCW, + AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW, + AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW, + AMO_MINWU, HLV_W, HLV_WU, HLVX_WU, HSV_W: begin + if (lsu_ctrl.vaddr[1:0] != 2'b00) begin + data_misaligned = 1'b1; + end + end + // half word + LH, LHU, SH, FLH, FSH, HLV_H, HLV_HU, HLVX_HU, HSV_H: begin + if (lsu_ctrl.vaddr[0] != 1'b0) begin + data_misaligned = 1'b1; + end + end + // byte -> is always aligned + default: ; + endcase + end + + if (data_misaligned) begin + case (lsu_ctrl.fu) + LOAD: begin + cva6_misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + STORE: begin + + cva6_misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + default: ; + endcase + end + + if (CVA6Cfg.MmuPresent && en_ld_st_translation_i && lsu_ctrl.overflow) begin + + case (lsu_ctrl.fu) + LOAD: begin + cva6_misaligned_exception.cause = riscv::LOAD_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + STORE: begin + cva6_misaligned_exception.cause = riscv::STORE_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + default: ; + endcase + end + + if (CVA6Cfg.MmuPresent && CVA6Cfg.RVH && en_ld_st_g_translation_i && !en_ld_st_translation_i && lsu_ctrl.g_overflow) begin + + case (lsu_ctrl.fu) + LOAD: begin + cva6_misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + STORE: begin + cva6_misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; + if (CVA6Cfg.TvalEn) + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + if (CVA6Cfg.RVH) begin + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; + end + end + default: ; + endcase + end + end + + + // ------------------ + // LSU Control + // ------------------ + // new data arrives here + lsu_ctrl_t lsu_req_i; + + assign lsu_req_i = { + lsu_valid_i, + vaddr_i, + tinst_i, + hs_ld_st_inst, + hlvx_inst, + overflow, + g_overflow, + fu_data_i.operand_b, + be_i, + fu_data_i.fu, + fu_data_i.operation, + fu_data_i.trans_id + }; + + lsu_bypass #( + .CVA6Cfg(CVA6Cfg), + .lsu_ctrl_t(lsu_ctrl_t) + ) lsu_bypass_i ( + .clk_i, + .rst_ni, + .flush_i, + .lsu_req_i (lsu_req_i), + .lsu_req_valid_i(lsu_valid_i), + .pop_ld_i (pop_ld), + .pop_st_i (pop_st), + + .lsu_ctrl_o(lsu_ctrl_byp), + .ready_o (lsu_ready_o) + ); + + assign rvfi_lsu_ctrl_o = lsu_ctrl; + +endmodule diff --git a/flow/designs/src/cva6/core/load_unit.sv b/flow/designs/src/cva6/core/load_unit.sv new file mode 100644 index 0000000000..0a66c51062 --- /dev/null +++ b/flow/designs/src/cva6/core/load_unit.sv @@ -0,0 +1,567 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba , ETH Zurich +// Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Load Unit, takes care of all load requests +// +// Contributor: Cesar Fuguet , CEA List +// Date: August 29, 2023 +// Modification: add support for multiple outstanding load operations +// to the data cache + +module load_unit + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type lsu_ctrl_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush signal - CONTROLLER + input logic flush_i, + // Load request is valid - LSU_BYPASS + input logic valid_i, + // Load request input - LSU_BYPASS + input lsu_ctrl_t lsu_ctrl_i, + // Pop the load request from the LSU bypass FIFO - LSU_BYPASS + output logic pop_ld_o, + // Load unit result is valid - ISSUE_STAGE + output logic valid_o, + // Load transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_o, + // Load result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] result_o, + // Load exception - ISSUE_STAGE + output exception_t ex_o, + // Request address translation - MMU + output logic translation_req_o, + // Virtual address - MMU + output logic [CVA6Cfg.VLEN-1:0] vaddr_o, + // Transformed trap instruction out - MMU + output logic [31:0] tinst_o, + // Instruction is a hyp load store instruction - MMU + output logic hs_ld_st_inst_o, + // Hyp load store with execute permissions - MMU + output logic hlvx_inst_o, + // Physical address - MMU + input logic [CVA6Cfg.PLEN-1:0] paddr_i, + // Excepted which appears before load - MMU + input exception_t ex_i, + // Data TLB hit - MMU + input logic dtlb_hit_i, + // Physical page number from the DTLB - MMU + input logic [CVA6Cfg.PPNW-1:0] dtlb_ppn_i, + // Page offset for address checking - STORE_UNIT + output logic [11:0] page_offset_o, + // Indicates if the page offset matches a store unit entry - STORE_UNIT + input logic page_offset_matches_i, + // Store buffer is empty - STORE_UNIT + input logic store_buffer_empty_i, + // Transaction ID of the committing instruction - COMMIT_STAGE + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i, + // Data cache request out - CACHES + input dcache_req_o_t req_port_i, + // Data cache request in - CACHES + output dcache_req_i_t req_port_o, + // Presence of non-idempotent operations in the D$ write buffer - CACHES + input logic dcache_wbuffer_not_ni_i +); + enum logic [3:0] { + IDLE, + WAIT_GNT, + SEND_TAG, + WAIT_PAGE_OFFSET, + ABORT_TRANSACTION, + ABORT_TRANSACTION_NI, + WAIT_TRANSLATION, + WAIT_FLUSH, + WAIT_WB_EMPTY + } + state_d, state_q; + + // in order to decouple the response interface from the request interface, + // we need a a buffer which can hold all inflight memory load requests + typedef struct packed { + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; // scoreboard identifier + logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] address_offset; // least significant bits of the address + fu_op operation; // type of load + } ldbuf_t; + + + // to support a throughput of one load per cycle, if the number of entries + // of the load buffer is 1, implement a fall-through mode. This however + // adds a combinational path between the request and response interfaces + // towards the cache. + localparam logic LDBUF_FALLTHROUGH = (CVA6Cfg.NrLoadBufEntries == 1); + localparam int unsigned REQ_ID_BITS = CVA6Cfg.NrLoadBufEntries > 1 ? $clog2( + CVA6Cfg.NrLoadBufEntries + ) : 1; + + typedef logic [REQ_ID_BITS-1:0] ldbuf_id_t; + + logic [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_valid_q, ldbuf_valid_d; + logic [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_flushed_q, ldbuf_flushed_d; + ldbuf_t [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_q; + logic ldbuf_empty, ldbuf_full; + ldbuf_id_t ldbuf_free_index; + logic ldbuf_w; + ldbuf_t ldbuf_wdata; + ldbuf_id_t ldbuf_windex; + logic ldbuf_r; + ldbuf_t ldbuf_rdata; + ldbuf_id_t ldbuf_rindex; + ldbuf_id_t ldbuf_last_id_q; + + assign ldbuf_full = &ldbuf_valid_q; + + // + // buffer of outstanding loads + + // write in the first available slot + generate + if (CVA6Cfg.NrLoadBufEntries > 1) begin : ldbuf_free_index_multi_gen + lzc #( + .WIDTH(CVA6Cfg.NrLoadBufEntries), + .MODE (1'b0) // Count leading zeros + ) lzc_windex_i ( + .in_i (~ldbuf_valid_q), + .cnt_o (ldbuf_free_index), + .empty_o(ldbuf_empty) + ); + end else begin : ldbuf_free_index_single_gen + assign ldbuf_free_index = 1'b0; + end + endgenerate + + assign ldbuf_windex = (LDBUF_FALLTHROUGH && ldbuf_r) ? ldbuf_rindex : ldbuf_free_index; + + always_comb begin : ldbuf_comb + ldbuf_flushed_d = ldbuf_flushed_q; + ldbuf_valid_d = ldbuf_valid_q; + + // In case of flush, raise the flushed flag in all slots. + if (flush_i) begin + ldbuf_flushed_d = '1; + end + // Free read entry (in the case of fall-through mode, free the entry + // only if there is no pending load) + if (ldbuf_r && (!LDBUF_FALLTHROUGH || !ldbuf_w)) begin + ldbuf_valid_d[ldbuf_rindex] = 1'b0; + end + // Track a new outstanding operation in the load buffer + if (ldbuf_w) begin + ldbuf_flushed_d[ldbuf_windex] = 1'b0; + ldbuf_valid_d[ldbuf_windex] = 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : ldbuf_ff + if (!rst_ni) begin + ldbuf_flushed_q <= '0; + ldbuf_valid_q <= '0; + ldbuf_last_id_q <= '0; + ldbuf_q <= '0; + end else begin + ldbuf_flushed_q <= ldbuf_flushed_d; + ldbuf_valid_q <= ldbuf_valid_d; + if (ldbuf_w) begin + ldbuf_last_id_q <= ldbuf_windex; + ldbuf_q[ldbuf_windex] <= ldbuf_wdata; + end + end + end + + // page offset is defined as the lower 12 bits, feed through for address checker + assign page_offset_o = lsu_ctrl_i.vaddr[11:0]; + // feed-through the virtual address for VA translation + assign vaddr_o = lsu_ctrl_i.vaddr; + assign hs_ld_st_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hs_ld_st_inst : 1'b0; + assign hlvx_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hlvx_inst : 1'b0; + // feed-through the transformed instruction for mmu + assign tinst_o = CVA6Cfg.RVH ? lsu_ctrl_i.tinst : '0; + // this is a read-only interface so set the write enable to 0 + assign req_port_o.data_we = 1'b0; + assign req_port_o.data_wdata = '0; + // compose the load buffer write data, control is handled in the FSM + assign ldbuf_wdata = { + lsu_ctrl_i.trans_id, lsu_ctrl_i.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0], lsu_ctrl_i.operation + }; + // output address + // we can now output the lower 12 bit as the index to the cache + assign req_port_o.address_index = lsu_ctrl_i.vaddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; + // translation from last cycle, again: control is handled in the FSM + assign req_port_o.address_tag = paddr_i[CVA6Cfg.DCACHE_TAG_WIDTH + + CVA6Cfg.DCACHE_INDEX_WIDTH-1 : + CVA6Cfg.DCACHE_INDEX_WIDTH]; + // request id = index of the load buffer's entry + assign req_port_o.data_id = ldbuf_windex; + // directly forward exception fields (valid bit is set below) + assign ex_o.cause = ex_i.cause; + assign ex_o.tval = ex_i.tval; + assign ex_o.tval2 = CVA6Cfg.RVH ? ex_i.tval2 : '0; + assign ex_o.tinst = CVA6Cfg.RVH ? ex_i.tinst : '0; + assign ex_o.gva = CVA6Cfg.RVH ? ex_i.gva : 1'b0; + + // Check that NI operations follow the necessary conditions + logic paddr_ni; + logic not_commit_time; + logic inflight_stores; + logic stall_ni; + assign paddr_ni = config_pkg::is_inside_nonidempotent_regions( + CVA6Cfg, {{52 - CVA6Cfg.PPNW{1'b0}}, dtlb_ppn_i, 12'd0} + ); + assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id; + assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i); + assign stall_ni = (inflight_stores || not_commit_time) && (paddr_ni && CVA6Cfg.NonIdemPotenceEn); + + // --------------- + // Load Control + // --------------- + always_comb begin : load_control + automatic logic accept_req; + + // default assignments + state_d = state_q; + translation_req_o = 1'b0; + req_port_o.data_req = 1'b0; + // tag control + req_port_o.kill_req = 1'b0; + req_port_o.tag_valid = 1'b0; + req_port_o.data_be = lsu_ctrl_i.be; + req_port_o.data_size = extract_transfer_size(lsu_ctrl_i.operation); + pop_ld_o = 1'b0; + + // In IDLE and SEND_TAG states, this unit can accept a new load request + // when the load buffer is not full or if there is a response and the + // load buffer is in fall-through mode + accept_req = (valid_i && (!ldbuf_full || (LDBUF_FALLTHROUGH && ldbuf_r))); + + case (state_q) + IDLE: begin + if (accept_req) begin + // start the translation process even though we do not know if the addresses match + // this should ease timing + translation_req_o = 1'b1; + // check if the page offset matches with a store, if it does then stall and wait + if (!page_offset_matches_i) begin + // make a load request to memory + req_port_o.data_req = 1'b1; + // we got no data grant so wait for the grant before sending the tag + if (!req_port_i.data_gnt) begin + state_d = WAIT_GNT; + end else begin + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; + end + end + end + end else begin + // wait for the store buffer to train and the page offset to not match anymore + state_d = WAIT_PAGE_OFFSET; + end + end + end + + // wait here for the page offset to not match anymore + WAIT_PAGE_OFFSET: begin + // we make a new request as soon as the page offset does not match anymore + if (!page_offset_matches_i) begin + state_d = WAIT_GNT; + end + end + + WAIT_GNT: begin + // keep the translation request up + translation_req_o = 1'b1; + // keep the request up + req_port_o.data_req = 1'b1; + // we finally got a data grant + if (req_port_i.data_gnt) begin + // so we send the tag in the next cycle + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; + end + end + + end + // otherwise we keep waiting on our grant + end + // we know for sure that the tag we want to send is valid + SEND_TAG: begin + req_port_o.tag_valid = 1'b1; + state_d = IDLE; + + if (accept_req) begin + // start the translation process even though we do not know if the addresses match + // this should ease timing + translation_req_o = 1'b1; + // check if the page offset matches with a store, if it does stall and wait + if (!page_offset_matches_i) begin + // make a load request to memory + req_port_o.data_req = 1'b1; + // we got no data grant so wait for the grant before sending the tag + if (!req_port_i.data_gnt) begin + state_d = WAIT_GNT; + end else begin + // we got a grant so we can send the tag in the next cycle + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; + end + end + end + end else begin + // wait for the store buffer to train and the page offset to not match anymore + state_d = WAIT_PAGE_OFFSET; + end + end + // ---------- + // Exception + // ---------- + // if we got an exception we need to kill the request immediately + if (ex_i.valid) begin + req_port_o.kill_req = 1'b1; + end + end + + WAIT_FLUSH: begin + // the D$ arbiter will take care of presenting this to the memory only in case we + // have an outstanding request + req_port_o.kill_req = 1'b1; + req_port_o.tag_valid = 1'b1; + // we've killed the current request so we can go back to idle + state_d = IDLE; + end + + default: begin + // abort the previous request - free the D$ arbiter + // we are here because of a TLB miss, we need to abort the current request and give way for the + // PTW walker to satisfy the TLB miss + if (state_q == ABORT_TRANSACTION && CVA6Cfg.MmuPresent) begin + req_port_o.kill_req = 1'b1; + req_port_o.tag_valid = 1'b1; + // wait until the WB is empty + state_d = WAIT_TRANSLATION; + end else if (state_q == ABORT_TRANSACTION_NI && CVA6Cfg.NonIdemPotenceEn) begin + req_port_o.kill_req = 1'b1; + req_port_o.tag_valid = 1'b1; + // re-do the request + state_d = WAIT_WB_EMPTY; + end else if (state_q == WAIT_WB_EMPTY && CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) begin + // Wait until the write-back buffer is empty in the data cache. + // the write buffer is empty, so lets go and re-do the translation. + state_d = WAIT_TRANSLATION; + end else if(state_q == WAIT_TRANSLATION && (CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn)) begin + translation_req_o = 1'b1; + // we've got a hit and we can continue with the request process + if (dtlb_hit_i) state_d = WAIT_GNT; + + // we got an exception + if (ex_i.valid) begin + // the next state will be the idle state + state_d = IDLE; + // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction + pop_ld_o = ~req_port_i.data_rvalid; + end + end else begin + state_d = IDLE; + end + end + endcase + + // if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in a extra stage + if (flush_i) begin + state_d = WAIT_FLUSH; + end + end + + // track the load data for later usage + assign ldbuf_w = req_port_o.data_req & req_port_i.data_gnt; + + // --------------- + // Retire Load + // --------------- + assign ldbuf_rindex = (CVA6Cfg.NrLoadBufEntries > 1) ? ldbuf_id_t'(req_port_i.data_rid) : 1'b0, + ldbuf_rdata = ldbuf_q[ldbuf_rindex]; + + // decoupled rvalid process + always_comb begin : rvalid_output + // read the pending load buffer + ldbuf_r = req_port_i.data_rvalid; + trans_id_o = ldbuf_q[ldbuf_rindex].trans_id; + valid_o = 1'b0; + ex_o.valid = 1'b0; + + // we got an rvalid and it's corresponding request was not flushed + if (req_port_i.data_rvalid && !ldbuf_flushed_q[ldbuf_rindex]) begin + // if the response corresponds to the last request, check that we are not killing it + if ((ldbuf_last_id_q != ldbuf_rindex) || !req_port_o.kill_req) valid_o = 1'b1; + // the output is also valid if we got an exception. An exception arrives one cycle after + // dtlb_hit_i is asserted, i.e. when we are in SEND_TAG. Otherwise, the exception + // corresponds to the next request that is already being translated (see below). + if (ex_i.valid && (state_q == SEND_TAG)) begin + valid_o = 1'b1; + ex_o.valid = 1'b1; + end + end + + // an exception occurred during translation + // exceptions can retire out-of-order -> but we need to give priority to non-excepting load and stores + // so we simply check if we got an rvalid if so we prioritize it by not retiring the exception - we simply go for another + // round in the load FSM + if ((CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn) && (state_q == WAIT_TRANSLATION) && !req_port_i.data_rvalid && ex_i.valid && valid_i) begin + trans_id_o = lsu_ctrl_i.trans_id; + valid_o = 1'b1; + ex_o.valid = 1'b1; + end + end + + + // latch physical address for the tag cycle (one cycle after applying the index) + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + end else begin + state_q <= state_d; + end + end + + // --------------- + // Sign Extend + // --------------- + logic [CVA6Cfg.XLEN-1:0] shifted_data; + + // realign as needed + assign shifted_data = req_port_i.data_rdata >> {ldbuf_rdata.address_offset, 3'b000}; + + /* // result mux (leaner code, but more logic stages. + // can be used instead of the code below (in between //result mux fast) if timing is not so critical) + always_comb begin + unique case (ldbuf_rdata.operation) + LWU: result_o = shifted_data[31:0]; + LHU: result_o = shifted_data[15:0]; + LBU: result_o = shifted_data[7:0]; + LW: result_o = 64'(signed'(shifted_data[31:0])); + LH: result_o = 64'(signed'(shifted_data[15:0])); + LB: result_o = 64'(signed'(shifted_data[ 7:0])); + default: result_o = shifted_data; + endcase + end */ + + // result mux fast + logic [ (CVA6Cfg.XLEN/8)-1:0] rdata_sign_bits; + logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] rdata_offset; + logic rdata_sign_bit, rdata_is_signed, rdata_is_fp_signed; + + + // prepare these signals for faster selection in the next cycle + assign rdata_is_signed = ldbuf_rdata.operation inside {ariane_pkg::LW, ariane_pkg::LH, ariane_pkg::LB, ariane_pkg::HLV_W, ariane_pkg::HLV_H, ariane_pkg::HLV_B}; + assign rdata_is_fp_signed = ldbuf_rdata.operation inside {ariane_pkg::FLW, ariane_pkg::FLH, ariane_pkg::FLB}; + assign rdata_offset = ((ldbuf_rdata.operation inside {ariane_pkg::LW, ariane_pkg::FLW, ariane_pkg::HLV_W}) & CVA6Cfg.IS_XLEN64) ? ldbuf_rdata.address_offset + 3 : + ( ldbuf_rdata.operation inside {ariane_pkg::LH, ariane_pkg::FLH, ariane_pkg::HLV_H}) ? ldbuf_rdata.address_offset + 1 : + ldbuf_rdata.address_offset; + + for (genvar i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : gen_sign_bits + assign rdata_sign_bits[i] = req_port_i.data_rdata[(i+1)*8-1]; + end + + + // select correct sign bit in parallel to result shifter above + // pull to 0 if unsigned + assign rdata_sign_bit = rdata_is_signed & rdata_sign_bits[rdata_offset] | (CVA6Cfg.FpPresent && rdata_is_fp_signed); + + // result mux + always_comb begin + unique case (ldbuf_rdata.operation) + ariane_pkg::LW, ariane_pkg::LWU, ariane_pkg::HLV_W, ariane_pkg::HLV_WU, ariane_pkg::HLVX_WU: + result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]}; + ariane_pkg::LH, ariane_pkg::LHU, ariane_pkg::HLV_H, ariane_pkg::HLV_HU, ariane_pkg::HLVX_HU: + result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]}; + ariane_pkg::LB, ariane_pkg::LBU, ariane_pkg::HLV_B, ariane_pkg::HLV_BU: + result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]}; + default: begin + // FLW, FLH and FLB have been defined here in default case to improve Code Coverage + if (CVA6Cfg.FpPresent) begin + unique case (ldbuf_rdata.operation) + ariane_pkg::FLW: begin + result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]}; + end + ariane_pkg::FLH: begin + result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]}; + end + ariane_pkg::FLB: begin + result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]}; + end + default: begin + result_o = shifted_data[CVA6Cfg.XLEN-1:0]; + end + endcase + end else begin + result_o = shifted_data[CVA6Cfg.XLEN-1:0]; + end + end + endcase + end + // end result mux fast + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off + initial + assert (CVA6Cfg.DcacheIdWidth >= REQ_ID_BITS) + else $fatal(1, "DcacheIdWidth parameter is not wide enough to encode pending loads"); + // check invalid offsets, but only issue a warning as these conditions actually trigger a load address misaligned exception + addr_offset0 : + assert property (@(posedge clk_i) disable iff (~rst_ni) + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LW, ariane_pkg::LWU}) |-> ldbuf_wdata.address_offset < 5) + else $fatal(1, "invalid address offset used with {LW, LWU}"); + addr_offset1 : + assert property (@(posedge clk_i) disable iff (~rst_ni) + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LH, ariane_pkg::LHU}) |-> ldbuf_wdata.address_offset < 7) + else $fatal(1, "invalid address offset used with {LH, LHU}"); + addr_offset2 : + assert property (@(posedge clk_i) disable iff (~rst_ni) + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8) + else $fatal(1, "invalid address offset used with {LB, LBU}"); + //pragma translate_on + +endmodule diff --git a/flow/designs/src/cva6/core/lsu_bypass.sv b/flow/designs/src/cva6/core/lsu_bypass.sv new file mode 100644 index 0000000000..2b9f2aaa6f --- /dev/null +++ b/flow/designs/src/cva6/core/lsu_bypass.sv @@ -0,0 +1,132 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 19.04.2017 +// Description: Load Store Unit, handles address calculation and memory interface signals + + +// ------------------ +// LSU Control +// ------------------ +// The LSU consists of two independent block which share a common address translation block. +// The one block is the load unit, the other one is the store unit. They will signal their readiness +// with separate signals. If they are not ready the LSU control should keep the last applied signals stable. +// Furthermore it can be the case that another request for one of the two store units arrives in which case +// the LSU control should sample it and store it for later application to the units. It does so, by storing it in a +// two element FIFO. This is necessary as we only know very late in the cycle whether the load/store will succeed (address check, +// TLB hit mainly). So we better unconditionally allow another request to arrive and store this request in case we need to. +module lsu_bypass + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type lsu_ctrl_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic flush_i, + + // TO_BE_COMPLETED - TO_BE_COMPLETED + input lsu_ctrl_t lsu_req_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic lsu_req_valid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic pop_ld_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic pop_st_i, + + // TO_BE_COMPLETED - TO_BE_COMPLETED + output lsu_ctrl_t lsu_ctrl_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic ready_o +); + + lsu_ctrl_t [1:0] mem_n, mem_q; + logic read_pointer_n, read_pointer_q; + logic write_pointer_n, write_pointer_q; + logic [1:0] status_cnt_n, status_cnt_q; + + logic empty; + assign empty = (status_cnt_q == 0); + assign ready_o = empty; + + always_comb begin + automatic logic [1:0] status_cnt; + automatic logic write_pointer; + automatic logic read_pointer; + + status_cnt = status_cnt_q; + write_pointer = write_pointer_q; + read_pointer = read_pointer_q; + + mem_n = mem_q; + // we've got a valid LSU request + if (lsu_req_valid_i) begin + mem_n[write_pointer_q] = lsu_req_i; + write_pointer++; + status_cnt++; + end + + if (pop_ld_i) begin + // invalidate the result + mem_n[read_pointer_q].valid = 1'b0; + read_pointer++; + status_cnt--; + end + + if (pop_st_i) begin + // invalidate the result + mem_n[read_pointer_q].valid = 1'b0; + read_pointer++; + status_cnt--; + end + + if (pop_st_i && pop_ld_i) mem_n = '0; + + if (flush_i) begin + status_cnt = '0; + write_pointer = '0; + read_pointer = '0; + mem_n = '0; + end + // default assignments + read_pointer_n = read_pointer; + write_pointer_n = write_pointer; + status_cnt_n = status_cnt; + end + + // output assignment + always_comb begin : output_assignments + if (empty) begin + lsu_ctrl_o = lsu_req_i; + end else begin + lsu_ctrl_o = mem_q[read_pointer_q]; + end + end + + // registers + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mem_q <= '0; + status_cnt_q <= '0; + write_pointer_q <= '0; + read_pointer_q <= '0; + end else begin + mem_q <= mem_n; + status_cnt_q <= status_cnt_n; + write_pointer_q <= write_pointer_n; + read_pointer_q <= read_pointer_n; + end + end +endmodule + diff --git a/flow/designs/src/cva6/core/macro_decoder.sv b/flow/designs/src/cva6/core/macro_decoder.sv new file mode 100644 index 0000000000..0d695a3372 --- /dev/null +++ b/flow/designs/src/cva6/core/macro_decoder.sv @@ -0,0 +1,765 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Rohan Arshid, 10xEngineers +// Date: 22.01.2024 +// Description: Contains the logic for decoding cm.push, cm.pop, cm.popret, +// cm.popretz, cm.mvsa01, and cm.mva01s instructions of the +// Zcmp Extension + +module macro_decoder #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + input logic [31:0] instr_i, + input logic clk_i, // Clock + input logic rst_ni, // Synchronous reset + input logic is_macro_instr_i, // Intruction is of macro extension + input logic illegal_instr_i, // From compressed decoder + input logic is_compressed_i, + input logic issue_ack_i, // Check if the intruction is acknowledged + output logic [31:0] instr_o, + output logic illegal_instr_o, + output logic is_compressed_o, + output logic fetch_stall_o, //Wait while push/pop/move instructions expand + output logic is_last_macro_instr_o, + output logic is_double_rd_macro_instr_o +); + + // FSM States + enum logic [2:0] { + IDLE, + INIT, + PUSH_ADDI, + POPRETZ_1, + MOVE, + PUSH_POP_INSTR_2 + } + state_d, state_q; + + // Instruction Types + enum logic [2:0] { + PUSH, + POP, + POPRETZ, + POPRET, + MVA01S, + MVSA01 + } macro_instr_type; + + // Temporary registers + logic [3:0] reg_numbers, reg_numbers_q, reg_numbers_d; + logic [11:0] stack_adj; + logic [4:0] xreg1, xreg2, store_reg, store_reg_q, store_reg_d; + logic [1:0] popretz_inst_q, popretz_inst_d; + logic [11:0] offset_reg, offset_q, offset_d; + logic [31:0] instr_o_reg; + + riscv::itype_t itype_inst; + assign instr_o = instr_o_reg; + always_comb begin + illegal_instr_o = 1'b0; + fetch_stall_o = 1'b0; + is_last_macro_instr_o = 1'b0; + is_double_rd_macro_instr_o = 1'b0; + is_compressed_o = is_macro_instr_i ? 1'b1 : is_compressed_i; + reg_numbers = '0; + stack_adj = '0; + state_d = state_q; + offset_d = offset_q; + reg_numbers_d = reg_numbers_q; + store_reg_d = store_reg_q; + popretz_inst_d = popretz_inst_q; + + if (is_macro_instr_i) begin + + unique case (instr_i[12:10]) + // push or pop + 3'b110: begin + unique case (instr_i[9:8]) + 2'b00: begin + macro_instr_type = PUSH; + end + 2'b10: begin + macro_instr_type = POP; + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + // popret or popretz + 3'b111: begin + unique case (instr_i[9:8]) + 2'b00: begin + macro_instr_type = POPRETZ; + end + 2'b10: begin + macro_instr_type = POPRET; + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + // mvq01s or mvsa01 + 3'b011: begin + unique case (instr_i[6:5]) + 2'b01: begin + macro_instr_type = MVSA01; + end + 2'b11: begin + macro_instr_type = MVA01S; + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + + // Calculate xreg1 & xreg2 for move instructions + if (macro_instr_type == MVSA01 || macro_instr_type == MVA01S) begin + if (instr_i[9:7] != instr_i[4:2]) begin + xreg1 = {instr_i[9:8] > 0, instr_i[9:8] == 0, instr_i[9:7]}; + xreg2 = {instr_i[4:3] > 0, instr_i[4:3] == 0, instr_i[4:2]}; + end else begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + end else begin + xreg1 = '0; + xreg2 = '0; + end + + // push/pop/popret/popretz instructions + unique case (instr_i[7:4]) + 4'b0100: reg_numbers = 4'b0001; // 4 + 4'b0101: reg_numbers = 4'b0010; // 5 + 4'b0110: reg_numbers = 4'b0011; // 6 + 4'b0111: reg_numbers = 4'b0100; // 7 + 4'b1000: reg_numbers = 4'b0101; // 8 + 4'b1001: reg_numbers = 4'b0110; // 9 + 4'b1010: reg_numbers = 4'b0111; // 10 + 4'b1011: reg_numbers = 4'b1000; // 11 + 4'b1100: reg_numbers = 4'b1001; // 12 + 4'b1101: reg_numbers = 4'b1010; // 13 + 4'b1110: reg_numbers = 4'b1011; // 14 + 4'b1111: reg_numbers = 4'b1100; // 15 + default: reg_numbers = '0; + endcase + + if (CVA6Cfg.XLEN == 32) begin + unique case (instr_i[7:4]) + 4'b0100, 4'b0101, 4'b0110, 4'b0111: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 16; + 2'b01: stack_adj = 32; + 2'b10: stack_adj = 48; + 2'b11: stack_adj = 64; + endcase + end + 4'b1000, 4'b1001, 4'b1010, 4'b1011: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 32; + 2'b01: stack_adj = 48; + 2'b10: stack_adj = 64; + 2'b11: stack_adj = 80; + endcase + end + 4'b1100, 4'b1101, 4'b1110: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 48; + 2'b01: stack_adj = 64; + 2'b10: stack_adj = 80; + 2'b11: stack_adj = 96; + endcase + end + 4'b1111: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 64; + 2'b01: stack_adj = 80; + 2'b10: stack_adj = 96; + 2'b11: stack_adj = 112; + endcase + end + default: ; + endcase + end else begin + unique case (instr_i[7:4]) + 4'b0100, 4'b0101: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 16; + 2'b01: stack_adj = 32; + 2'b10: stack_adj = 48; + 2'b11: stack_adj = 64; + endcase + end + 4'b0110, 4'b0111: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 32; + 2'b01: stack_adj = 48; + 2'b10: stack_adj = 64; + 2'b11: stack_adj = 80; + endcase + end + 4'b1000, 4'b1001: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 48; + 2'b01: stack_adj = 64; + 2'b10: stack_adj = 80; + 2'b11: stack_adj = 96; + endcase + end + 4'b1010, 4'b1011: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 64; + 2'b01: stack_adj = 80; + 2'b10: stack_adj = 96; + 2'b11: stack_adj = 112; + endcase + end + 4'b1100, 4'b1101: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 80; + 2'b01: stack_adj = 96; + 2'b10: stack_adj = 112; + 2'b11: stack_adj = 128; + endcase + end + 4'b1110: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 96; + 2'b01: stack_adj = 112; + 2'b10: stack_adj = 128; + 2'b11: stack_adj = 144; + endcase + end + 4'b1111: begin + unique case (instr_i[3:2]) + 2'b00: stack_adj = 112; + 2'b01: stack_adj = 128; + 2'b10: stack_adj = 144; + 2'b11: stack_adj = 160; + endcase + end + endcase + end + + //Take 2's compliment in case of PUSH instruction + if (macro_instr_type == PUSH) begin + itype_inst.imm = ~stack_adj + 1'b1; + end else begin + itype_inst.imm = stack_adj - 12'h4; + end + end else begin + illegal_instr_o = illegal_instr_i; + instr_o_reg = instr_i; + end + + unique case (state_q) + IDLE: begin + if (is_macro_instr_i) begin + reg_numbers_d = reg_numbers - 1'b1; + state_d = issue_ack_i ? INIT : IDLE; + case (macro_instr_type) + PUSH: begin + offset_d = 12'hFFC + 12'hFFC; + end + POP, POPRETZ, POPRET: begin + offset_d = itype_inst.imm + 12'hFFC; + offset_reg = itype_inst.imm; + case (macro_instr_type) + POPRETZ: begin + popretz_inst_d = 2'b11; + end + POPRET: begin + popretz_inst_d = 2'b01; + end + default: begin + popretz_inst_d = 'b0; + end + endcase + end + default: ; + endcase + // when rlist is 4, max reg is x18 i.e. 14(const) + 4 + // when rlist is 12, max reg is x27 i.e. 15(const) + 12 + if (reg_numbers == 4'b1100) begin + store_reg_d = 4'b1110 + reg_numbers; + store_reg = 4'b1111 + reg_numbers; + end else begin + store_reg_d = 4'b1101 + reg_numbers; + store_reg = 4'b1110 + reg_numbers; + end + + if (macro_instr_type == MVSA01) begin + fetch_stall_o = 1; + is_double_rd_macro_instr_o = 1; + // addi xreg1, a0, 0 + instr_o_reg = {12'h0, 5'hA, 3'h0, xreg1, riscv::OpcodeOpImm}; + state_d = MOVE; + end + + if (macro_instr_type == MVA01S) begin + fetch_stall_o = 1; + is_double_rd_macro_instr_o = 1; + // addi a0, xreg1, 0 + instr_o_reg = {12'h0, xreg1, 3'h0, 5'hA, riscv::OpcodeOpImm}; + state_d = MOVE; + end + + if (macro_instr_type == PUSH) begin + + fetch_stall_o = 1'b1; // stall inst fetch + + if (reg_numbers == 4'b0001) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + 7'b1111111, 5'h1, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore + }; // sd store_reg, -4(sp) + end else begin + instr_o_reg = { + 7'b1111111, 5'h1, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore + }; // sw store_reg, -4(sp) + end + state_d = PUSH_ADDI; + end + + if (reg_numbers == 4'b0010) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; + end else begin + instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; + end + end + + if (reg_numbers == 4'b0011) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; + end else begin + instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; + end + + end + + if (reg_numbers >= 4 && reg_numbers <= 12) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; + end else begin + instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; + end + + if (reg_numbers == 12) begin + state_d = PUSH_POP_INSTR_2; + end + end + end + + if ((macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin + fetch_stall_o = 1; // stall inst fetch + if (reg_numbers == 1) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_reg - 12'h4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad + }; // ld store_reg, Imm(sp) + end else begin + instr_o_reg = { + offset_reg, 5'h2, 3'h2, 5'h1, riscv::OpcodeLoad + }; // lw store_reg, Imm(sp) + end + unique case (macro_instr_type) + PUSH, POP, POPRET: begin + state_d = PUSH_ADDI; + end + POPRETZ: begin + state_d = POPRETZ_1; + end + default: ; + endcase + end + + if (reg_numbers == 2) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad}; + end else begin + instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h8, riscv::OpcodeLoad}; + end + end + + if (reg_numbers == 3) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad}; + end else begin + instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h9, riscv::OpcodeLoad}; + end + end + + if (reg_numbers >= 4 && reg_numbers <= 12) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad}; + end else begin + instr_o_reg = {offset_reg, 5'h2, 3'h2, store_reg, riscv::OpcodeLoad}; + end + + if (reg_numbers == 12) begin + state_d = PUSH_POP_INSTR_2; + end + end + end + end + end + INIT: begin + fetch_stall_o = is_macro_instr_i; // stall inst fetch + if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin + if (reg_numbers_q == 4'b0001) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:5], + 5'h1, + 5'h2, + 3'h3, + offset_d[4:3], + 1'b0, + offset_d[1:0], + riscv::OpcodeStore + }; + end else begin + instr_o_reg = {offset_d[11:5], 5'h1, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore}; + end + state_d = PUSH_ADDI; + end + + if (reg_numbers_q == 4'b0010) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:5], + 5'h8, + 5'h2, + 3'h3, + offset_d[4:3], + 1'b0, + offset_d[1:0], + riscv::OpcodeStore + }; + end else begin + instr_o_reg = {offset_d[11:5], 5'h8, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore}; + end + reg_numbers_d = reg_numbers_q - 1; + offset_d = offset_q + 12'hFFC; // decrement offset by -4 i.e. add 2's compilment of 4 + end + + if (reg_numbers_q == 4'b0011) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:5], + 5'h9, + 5'h2, + 3'h3, + offset_d[4:3], + 1'b0, + offset_d[1:0], + riscv::OpcodeStore + }; + end else begin + instr_o_reg = {offset_d[11:5], 5'h9, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore}; + end + reg_numbers_d = reg_numbers_q - 1; + offset_d = offset_q + 12'hFFC; + end + + if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:5], + store_reg_q, + 5'h2, + 3'h3, + offset_d[4:3], + 1'b0, + offset_d[1:0], + riscv::OpcodeStore + }; + end else begin + instr_o_reg = { + offset_d[11:5], store_reg_q, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore + }; + end + reg_numbers_d = reg_numbers_q - 1; + store_reg_d = store_reg_q - 1; + offset_d = offset_q + 12'hFFC; + if (reg_numbers_q == 12) begin + state_d = PUSH_POP_INSTR_2; + end + end + end + + if (issue_ack_i && is_macro_instr_i && (macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin + + if (reg_numbers_q == 1) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad + }; + end else begin + instr_o_reg = {offset_d[11:0], 5'h2, 3'h2, 5'h1, riscv::OpcodeLoad}; + end + unique case (macro_instr_type) + PUSH, POP, POPRET: begin + state_d = PUSH_ADDI; + end + POPRETZ: begin + state_d = POPRETZ_1; + end + default: ; + endcase + end + + if (reg_numbers_q == 2) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad + }; + end else begin + instr_o_reg = {offset_d[11:0], 5'h2, 3'h2, 5'h8, riscv::OpcodeLoad}; + end + reg_numbers_d = reg_numbers_q - 1; + offset_d = offset_q + 12'hFFC; // decrement offset by -4 i.e. add 2's compilment of 4 + end + + if (reg_numbers_q == 3) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad + }; + end else begin + instr_o_reg = {offset_d[11:0], 5'h2, 3'h2, 5'h9, riscv::OpcodeLoad}; + end + reg_numbers_d = reg_numbers_q - 1; + offset_d = offset_q + 12'hFFC; + end + + if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin + if (CVA6Cfg.XLEN == 64) begin + instr_o_reg = { + offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, store_reg_q, riscv::OpcodeLoad + }; + end else begin + instr_o_reg = {offset_d[11:0], 5'h2, 3'h2, store_reg_q, riscv::OpcodeLoad}; + end + reg_numbers_d = reg_numbers_q - 1; + store_reg_d = store_reg_q - 1; + offset_d = offset_q + 12'hFFC; + if (reg_numbers_q == 12) begin + state_d = PUSH_POP_INSTR_2; + end + end + end + end + + MOVE: begin + case (macro_instr_type) + MVSA01: begin + if (issue_ack_i) begin + // addi xreg2, a1, 0 + instr_o_reg = {12'h0, 5'hB, 3'h0, xreg2, riscv::OpcodeOpImm}; + fetch_stall_o = 0; + is_last_macro_instr_o = 1; + is_double_rd_macro_instr_o = 1; + state_d = IDLE; + end + end + MVA01S: begin + if (issue_ack_i) begin + // addi a1, xreg2, 0 + instr_o_reg = {12'h0, xreg2, 3'h0, 5'hB, riscv::OpcodeOpImm}; + fetch_stall_o = 0; + is_last_macro_instr_o = 1; + is_double_rd_macro_instr_o = 1; + state_d = IDLE; + end + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + + PUSH_ADDI: begin + if (CVA6Cfg.XLEN == 64) begin + if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin + // addi sp, sp, stack_adj + instr_o_reg = {itype_inst.imm - 12'h4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm}; + end else begin + if (issue_ack_i) begin + instr_o_reg = {stack_adj - 12'h4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm}; + end + end + if (issue_ack_i && is_macro_instr_i && (macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin + state_d = POPRETZ_1; + fetch_stall_o = 1; + end else begin + if (issue_ack_i) begin + state_d = IDLE; + fetch_stall_o = 0; + is_last_macro_instr_o = 1; + end else begin + fetch_stall_o = 1; + end + end + end else begin + if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin + // addi sp, sp, stack_adj + instr_o_reg = {itype_inst.imm, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm}; + end else begin + if (issue_ack_i) begin + instr_o_reg = {stack_adj, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm}; + end + end + if (issue_ack_i && is_macro_instr_i && (macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin + state_d = POPRETZ_1; + fetch_stall_o = 1; + end else begin + if (issue_ack_i) begin + state_d = IDLE; + fetch_stall_o = 0; + is_last_macro_instr_o = 1; + end else begin + fetch_stall_o = 1; + end + end + end + end + + PUSH_POP_INSTR_2: begin + if (CVA6Cfg.XLEN == 64) begin + case (macro_instr_type) + PUSH: begin + if (issue_ack_i) begin + instr_o_reg = { + offset_d[11:5], + store_reg_q, + 5'h2, + 3'h3, + offset_d[4:3], + 1'b0, + offset_d[1:0], + riscv::OpcodeStore + }; + offset_d = offset_q + 12'hFFC; + store_reg_d = store_reg_q - 1; + state_d = INIT; + end + end + POP, POPRETZ, POPRET: begin + if (issue_ack_i) begin + instr_o_reg = { + offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, store_reg_q, riscv::OpcodeLoad + }; + offset_d = offset_q + 12'hFFC; + store_reg_d = store_reg_q - 1; + state_d = INIT; + end + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end else begin + case (macro_instr_type) + PUSH: begin + if (issue_ack_i) begin + instr_o_reg = { + offset_d[11:5], store_reg_q, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore + }; + offset_d = offset_q + 12'hFFC; + store_reg_d = store_reg_q - 1; + state_d = INIT; + end + end + POP, POPRETZ, POPRET: begin + if (issue_ack_i) begin + instr_o_reg = {offset_d[11:0], 5'h2, 3'h2, store_reg_q, riscv::OpcodeLoad}; + offset_d = offset_q + 12'hFFC; + store_reg_d = store_reg_q - 1; + state_d = INIT; + end + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + fetch_stall_o = 1; + end + + POPRETZ_1: begin + unique case (popretz_inst_q) + 2'b11: begin + if (issue_ack_i) begin + instr_o_reg = {20'h0, 5'hA, riscv::OpcodeLui}; //lui a0, 0x0 + popretz_inst_d = popretz_inst_q - 1; + end + fetch_stall_o = 1; + end + 2'b10: begin + if (issue_ack_i) begin + instr_o_reg = {12'h0, 5'hA, 3'h0, 5'hA, riscv::OpcodeOpImm}; //addi a0, a0, 0x0 + popretz_inst_d = popretz_inst_q - 1; + state_d = PUSH_ADDI; + end + fetch_stall_o = 1; + end + 2'b01: begin + if (issue_ack_i) begin + instr_o_reg = {12'h0, 5'h1, 3'h0, 5'h0, riscv::OpcodeJalr}; //ret - jalr x0, x1, 0 + state_d = IDLE; + fetch_stall_o = 0; + is_last_macro_instr_o = 1; + popretz_inst_d = popretz_inst_q - 1; + end + end + default: begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + endcase + end + default: begin + state_d = IDLE; + end + endcase + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + offset_q <= '0; + popretz_inst_q <= '0; + reg_numbers_q <= '0; + store_reg_q <= '0; + end else begin + state_q <= state_d; + offset_q <= offset_d; + reg_numbers_q <= reg_numbers_d; + store_reg_q <= store_reg_d; + popretz_inst_q <= popretz_inst_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/mult.sv b/flow/designs/src/cva6/core/mult.sv new file mode 100644 index 0000000000..ae4962ac8c --- /dev/null +++ b/flow/designs/src/cva6/core/mult.sv @@ -0,0 +1,158 @@ + + +module mult + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush - CONTROLLER + input logic flush_i, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // Mult instruction is valid - ISSUE_STAGE + input logic mult_valid_i, + // Mult result - ISSUE_STAGE + output logic [ CVA6Cfg.XLEN-1:0] result_o, + // Mult result is valid - ISSUE_STAGE + output logic mult_valid_o, + // Mutl is ready - ISSUE_STAGE + output logic mult_ready_o, + // Mult transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id_o +); + logic mul_valid; + logic div_valid; + logic div_ready_i; // receiver of division result is able to accept the result + logic [CVA6Cfg.TRANS_ID_BITS-1:0] mul_trans_id; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] div_trans_id; + logic [CVA6Cfg.XLEN-1:0] mul_result; + logic [CVA6Cfg.XLEN-1:0] div_result; + + logic div_valid_op; + logic mul_valid_op; + // Input Arbitration + + assign mul_valid_op = ~flush_i && mult_valid_i && (fu_data_i.operation inside { MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR }); + + assign div_valid_op = ~flush_i && mult_valid_i && (fu_data_i.operation inside { DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW }); + + // --------------------- + // Output Arbitration + // --------------------- + // we give precedence to multiplication as the divider supports stalling and the multiplier is + // just a dumb pipelined multiplier + assign div_ready_i = (mul_valid) ? 1'b0 : 1'b1; + assign mult_trans_id_o = (mul_valid) ? mul_trans_id : div_trans_id; + assign result_o = (mul_valid) ? mul_result : div_result; + assign mult_valid_o = div_valid | mul_valid; + // mult_ready_o = division as the multiplication will unconditionally be ready to accept new requests + + // --------------------- + // Multiplication + // --------------------- + multiplier #( + .CVA6Cfg(CVA6Cfg) + ) i_multiplier ( + .clk_i, + .rst_ni, + .trans_id_i (fu_data_i.trans_id), + .operation_i (fu_data_i.operation), + .operand_a_i (fu_data_i.operand_a), + .operand_b_i (fu_data_i.operand_b), + .result_o (mul_result), + .mult_valid_i (mul_valid_op), + .mult_valid_o (mul_valid), + .mult_trans_id_o(mul_trans_id) + ); + + // --------------------- + // Division + // --------------------- + logic [CVA6Cfg.XLEN-1:0] + operand_b, + operand_a; // input operands after input MUX (input silencing, word operations or full inputs) + logic [CVA6Cfg.XLEN-1:0] result; // result before result mux + + logic div_signed; // signed or unsigned division + logic rem; // is it a reminder (or not a reminder e.g.: a division) + logic word_op_d, word_op_q; // save whether the operation was signed or not + + // is this a signed op? + assign div_signed = fu_data_i.operation inside {DIV, DIVW, REM, REMW}; + // is this a modulo? + assign rem = fu_data_i.operation inside {REM, REMU, REMW, REMUW}; + + // prepare the input operands and control divider + always_comb begin + // silence the inputs + operand_a = '0; + operand_b = '0; + // control signals + word_op_d = word_op_q; + + // we've go a new division operation + if (mult_valid_i && fu_data_i.operation inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin + // is this a word operation? + if (CVA6Cfg.IS_XLEN64 && (fu_data_i.operation == DIVW || fu_data_i.operation == DIVUW || fu_data_i.operation == REMW || fu_data_i.operation == REMUW)) begin + // yes so check if we should sign extend this is only done for a signed operation + if (div_signed) begin + operand_a = sext32to64(fu_data_i.operand_a[31:0]); + operand_b = sext32to64(fu_data_i.operand_b[31:0]); + end else begin + operand_a = fu_data_i.operand_a[31:0]; + operand_b = fu_data_i.operand_b[31:0]; + end + + // save whether we want sign extend the result or not, this is done for all word operations + word_op_d = 1'b1; + end else begin + // regular op + operand_a = fu_data_i.operand_a; + operand_b = fu_data_i.operand_b; + word_op_d = 1'b0; + end + end + end + + // --------------------- + // Serial Divider + // --------------------- + serdiv #( + .CVA6Cfg(CVA6Cfg), + .WIDTH (CVA6Cfg.XLEN) + ) i_div ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .id_i (fu_data_i.trans_id), + .op_a_i (operand_a), + .op_b_i (operand_b), + .opcode_i ({rem, div_signed}), // 00: udiv, 10: urem, 01: div, 11: rem + .in_vld_i (div_valid_op), + .in_rdy_o (mult_ready_o), + .flush_i (flush_i), + .out_vld_o(div_valid), + .out_rdy_i(div_ready_i), + .id_o (div_trans_id), + .res_o (result) + ); + + // Result multiplexer + // if it was a signed word operation the bit will be set and the result will be sign extended accordingly + assign div_result = (CVA6Cfg.IS_XLEN64 && word_op_q) ? sext32to64(result) : result; + + // --------------------- + // Registers + // --------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + word_op_q <= '0; + end else begin + word_op_q <= word_op_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/multiplier.sv b/flow/designs/src/cva6/core/multiplier.sv new file mode 100644 index 0000000000..b6c44f7f7b --- /dev/null +++ b/flow/designs/src/cva6/core/multiplier.sv @@ -0,0 +1,166 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba +// +// Description: Multiplication Unit with one pipeline register +// This unit relies on retiming features of the synthesizer +// + + +module multiplier + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Multiplier transaction ID - Mult + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i, + // Multiplier instruction is valid - Mult + input logic mult_valid_i, + // Multiplier operation - Mult + input fu_op operation_i, + // A operand - Mult + input logic [ CVA6Cfg.XLEN-1:0] operand_a_i, + // B operand - Mult + input logic [ CVA6Cfg.XLEN-1:0] operand_b_i, + // Multiplier result - Mult + output logic [ CVA6Cfg.XLEN-1:0] result_o, + // Mutliplier result is valid - Mult + output logic mult_valid_o, + // Multiplier transaction ID - Mult + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id_o +); + // Carry-less multiplication + logic [CVA6Cfg.XLEN-1:0] + clmul_q, clmul_d, clmulr_q, clmulr_d, operand_a, operand_b, operand_a_rev, operand_b_rev; + logic clmul_rmode, clmul_hmode; + + if (CVA6Cfg.RVB) begin : gen_bitmanip + // checking for clmul_rmode and clmul_hmode + assign clmul_rmode = (operation_i == CLMULR); + assign clmul_hmode = (operation_i == CLMULH); + + // operand_a and b reverse generator + for (genvar i = 0; i < CVA6Cfg.XLEN; i++) begin + assign operand_a_rev[i] = operand_a_i[(CVA6Cfg.XLEN-1)-i]; + assign operand_b_rev[i] = operand_b_i[(CVA6Cfg.XLEN-1)-i]; + end + + // operand_a and operand_b selection + assign operand_a = (clmul_rmode | clmul_hmode) ? operand_a_rev : operand_a_i; + assign operand_b = (clmul_rmode | clmul_hmode) ? operand_b_rev : operand_b_i; + + // implementation + always_comb begin + clmul_d = '0; + for (int i = 0; i <= CVA6Cfg.XLEN; i++) begin + clmul_d = (|((operand_b >> i) & 1)) ? clmul_d ^ (operand_a << i) : clmul_d; + end + end + + // clmulr + clmulh result generator + for (genvar i = 0; i < CVA6Cfg.XLEN; i++) begin + assign clmulr_d[i] = clmul_d[(CVA6Cfg.XLEN-1)-i]; + end + end + + // Pipeline register + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_q; + logic mult_valid_q; + fu_op operator_d, operator_q; + logic [CVA6Cfg.XLEN*2-1:0] mult_result_d, mult_result_q; + + // control registers + logic sign_a, sign_b; + logic mult_valid; + + // control signals + assign mult_valid_o = mult_valid_q; + assign mult_trans_id_o = trans_id_q; + + assign mult_valid = mult_valid_i && (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR}); + + // Sign Select MUX + always_comb begin + sign_a = 1'b0; + sign_b = 1'b0; + + // signed multiplication + if (operation_i == MULH) begin + sign_a = 1'b1; + sign_b = 1'b1; + // signed - unsigned multiplication + end else if (operation_i == MULHSU) begin + sign_a = 1'b1; + // unsigned multiplication + end else begin + sign_a = 1'b0; + sign_b = 1'b0; + end + end + + + // single stage version + assign mult_result_d = $signed( + {operand_a_i[CVA6Cfg.XLEN-1] & sign_a, operand_a_i} + ) * $signed( + {operand_b_i[CVA6Cfg.XLEN-1] & sign_b, operand_b_i} + ); + + + assign operator_d = operation_i; + + always_comb begin : p_selmux + unique case (operator_q) + MULH, MULHU, MULHSU: result_o = mult_result_q[CVA6Cfg.XLEN*2-1:CVA6Cfg.XLEN]; + CLMUL: result_o = clmul_q; + CLMULH: result_o = clmulr_q >> 1; + CLMULR: result_o = clmulr_q; + // MUL performs an CVA6Cfg.XLEN-bit×CVA6Cfg.XLEN-bit multiplication and places the lower CVA6Cfg.XLEN bits in the destination register + default: begin + if (operator_q == MULW && CVA6Cfg.IS_XLEN64) result_o = sext32to64(mult_result_q[31:0]); + else result_o = mult_result_q[CVA6Cfg.XLEN-1:0]; // including MUL + end + endcase + end + if (CVA6Cfg.RVB) begin + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + clmul_q <= '0; + clmulr_q <= '0; + end else begin + clmul_q <= clmul_d; + clmulr_q <= clmulr_d; + end + end + end + // ----------------------- + // Output pipeline register + // ----------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mult_valid_q <= '0; + trans_id_q <= '0; + operator_q <= MUL; + mult_result_q <= '0; + end else begin + // Input silencing + trans_id_q <= trans_id_i; + // Output Register + mult_valid_q <= mult_valid; + operator_q <= operator_d; + mult_result_q <= mult_result_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/core/perf_counters.sv b/flow/designs/src/cva6/core/perf_counters.sv new file mode 100644 index 0000000000..8ef2faf1e0 --- /dev/null +++ b/flow/designs/src/cva6/core/perf_counters.sv @@ -0,0 +1,217 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 06.10.2017 +// Description: Performance counters + + +module perf_counters + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type icache_dreq_t = logic, + parameter type scoreboard_entry_t = logic, + parameter int unsigned NumPorts = 3 // number of miss ports +) ( + input logic clk_i, + input logic rst_ni, + input logic debug_mode_i, // debug mode + // SRAM like interface + input logic [11:0] addr_i, // read/write address (up to ariane_pkg::MHPMCounterNum counters possible) + input logic we_i, // write enable + input logic [CVA6Cfg.XLEN-1:0] data_i, // data to write + output logic [CVA6Cfg.XLEN-1:0] data_o, // data to read + // from commit stage + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // acknowledge that we are indeed committing + // from L1 caches + input logic l1_icache_miss_i, + input logic l1_dcache_miss_i, + // from MMU + input logic itlb_miss_i, + input logic dtlb_miss_i, + // from issue stage + input logic sb_full_i, + // from frontend + input logic if_empty_i, + // from PC Gen + input exception_t ex_i, + input logic eret_i, + input bp_resolve_t resolved_branch_i, + // for newly added events + input exception_t branch_exceptions_i, //Branch exceptions->execute unit-> branch_exception_o + input icache_dreq_t l1_icache_access_i, + input dcache_req_i_t [2:0] l1_dcache_access_i, + input logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0]miss_vld_bits_i, //For Cache eviction (3ports-LOAD,STORE,PTW) + input logic i_tlb_flush_i, + input logic stall_issue_i, //stall-read operands + input logic [31:0] mcountinhibit_i +); + + typedef logic [11:0] csr_addr_t; + + logic [63:0] generic_counter_d[MHPMCounterNum:1]; + logic [63:0] generic_counter_q[MHPMCounterNum:1]; + + //internal signal to keep track of exception + logic read_access_exception, update_access_exception; + + logic events[MHPMCounterNum:1]; + //internal signal for MUX select line input + logic [4:0] mhpmevent_d[MHPMCounterNum:1]; + logic [4:0] mhpmevent_q[MHPMCounterNum:1]; + // internal signal to detect event on multiple commit ports + logic [CVA6Cfg.NrCommitPorts-1:0] load_event; + logic [CVA6Cfg.NrCommitPorts-1:0] store_event; + logic [CVA6Cfg.NrCommitPorts-1:0] branch_event; + logic [CVA6Cfg.NrCommitPorts-1:0] call_event; + logic [CVA6Cfg.NrCommitPorts-1:0] return_event; + logic [CVA6Cfg.NrCommitPorts-1:0] int_event; + logic [CVA6Cfg.NrCommitPorts-1:0] fp_event; + + //Multiplexer + always_comb begin : Mux + events[MHPMCounterNum:1] = '{default: 0}; + load_event = '{default: 0}; + store_event = '{default: 0}; + branch_event = '{default: 0}; + call_event = '{default: 0}; + return_event = '{default: 0}; + int_event = '{default: 0}; + fp_event = '{default: 0}; + + for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin + load_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == LOAD); + store_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == STORE); + branch_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == CTRL_FLOW); + call_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == CTRL_FLOW && (commit_instr_i[j].op == ADD || commit_instr_i[j].op == JALR) && (commit_instr_i[j].rd == 'd1 || commit_instr_i[j].rd == 'd5)); + return_event[j] = commit_ack_i[j] & (commit_instr_i[j].op == JALR && commit_instr_i[j].rd == 'd0); + int_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == ALU || commit_instr_i[j].fu == MULT); + fp_event[j] = commit_ack_i[j] & (commit_instr_i[j].fu == FPU || commit_instr_i[j].fu == FPU_VEC); + end + + for (int unsigned i = 1; i <= MHPMCounterNum; i++) begin + case (mhpmevent_q[i]) + 5'b00000: events[i] = 0; + 5'b00001: events[i] = l1_icache_miss_i; //L1 I-Cache misses + 5'b00010: events[i] = l1_dcache_miss_i; //L1 D-Cache misses + 5'b00011: events[i] = itlb_miss_i; //ITLB misses + 5'b00100: events[i] = dtlb_miss_i; //DTLB misses + 5'b00101: events[i] = |load_event; //Load accesses + 5'b00110: events[i] = |store_event; //Store accesses + 5'b00111: events[i] = ex_i.valid; //Exceptions + 5'b01000: events[i] = eret_i; //Exception handler returns + 5'b01001: events[i] = |branch_event; // Branch instructions + 5'b01010: + events[i] = resolved_branch_i.valid && resolved_branch_i.is_mispredict;//Branch mispredicts + 5'b01011: events[i] = branch_exceptions_i.valid; //Branch exceptions + // The standard software calling convention uses register x1 to hold the return address on a call + // the unconditional jump is decoded as ADD op + 5'b01100: events[i] = |call_event; //Call + 5'b01101: events[i] = |return_event; //Return + 5'b01110: events[i] = sb_full_i; //MSB Full + 5'b01111: events[i] = if_empty_i; //Instruction fetch Empty + 5'b10000: events[i] = l1_icache_access_i.req; //L1 I-Cache accesses + 5'b10001: + events[i] = l1_dcache_access_i[0].data_req || l1_dcache_access_i[1].data_req || l1_dcache_access_i[2].data_req;//L1 D-Cache accesses + 5'b10010: + events[i] = (l1_dcache_miss_i && miss_vld_bits_i[0] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[1] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[2] == 8'hFF);//eviction + 5'b10011: events[i] = i_tlb_flush_i; //I-TLB flush + 5'b10100: events[i] = |int_event; //Integer instructions + 5'b10101: events[i] = |fp_event; //Floating Point Instructions + 5'b10110: events[i] = stall_issue_i; //Pipeline bubbles + default: events[i] = 0; + endcase + end + + end + + always_comb begin : generic_counter + generic_counter_d = generic_counter_q; + data_o = 'b0; + mhpmevent_d = mhpmevent_q; + read_access_exception = 1'b0; + update_access_exception = 1'b0; + + // Increment the non-inhibited counters with active events + for (int unsigned i = 1; i <= MHPMCounterNum; i++) begin + if ((!debug_mode_i) && (!we_i)) begin + if ((events[i]) == 1 && (!mcountinhibit_i[i+2])) begin + generic_counter_d[i] = generic_counter_q[i] + 1'b1; + end + end + end + + //Read + if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_COUNTER_3)) && (addr_i < ( csr_addr_t'(riscv::CSR_MHPM_COUNTER_3) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0]; + end else begin + data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1]; + end + end else if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_COUNTER_3H)) && (addr_i < ( csr_addr_t'(riscv::CSR_MHPM_COUNTER_3H) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32]; + end else begin + read_access_exception = 1'b1; + end + end else if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_EVENT_3)) && (addr_i < (csr_addr_t'(riscv::CSR_MHPM_EVENT_3) + MHPMCounterNum)) ) begin + data_o = mhpmevent_q[addr_i-riscv::CSR_MHPM_EVENT_3+1]; + end else if( (addr_i >= csr_addr_t'(riscv::CSR_HPM_COUNTER_3)) && (addr_i < (csr_addr_t'(riscv::CSR_HPM_COUNTER_3) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1][31:0]; + end else begin + data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1]; + end + end else if( (addr_i > csr_addr_t'(riscv::CSR_HPM_COUNTER_3H)) && (addr_i < (csr_addr_t'(riscv::CSR_HPM_COUNTER_3H) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32]; + end else begin + read_access_exception = 1'b1; + end + end + + //Write + if (we_i) begin + if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_COUNTER_3)) && (addr_i < (csr_addr_t'(riscv::CSR_MHPM_COUNTER_3) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0] = data_i; + end else begin + generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3+1] = data_i; + end + end else if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_COUNTER_3H)) && (addr_i < (csr_addr_t'(riscv::CSR_MHPM_COUNTER_3H) + MHPMCounterNum)) ) begin + if (riscv::XLEN == 32) begin + generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32] = data_i; + end else begin + update_access_exception = 1'b1; + end + end else if( (addr_i >= csr_addr_t'(riscv::CSR_MHPM_EVENT_3)) && (addr_i < csr_addr_t'(riscv::CSR_MHPM_EVENT_3) + MHPMCounterNum) ) begin + mhpmevent_d[addr_i-riscv::CSR_MHPM_EVENT_3+1] = data_i; + end + end + end + + //Registers + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + generic_counter_q <= '{default: 0}; + mhpmevent_q <= '{default: 0}; + end else begin + generic_counter_q <= generic_counter_d; + mhpmevent_q <= mhpmevent_d; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/pmp/src/pmp.sv b/flow/designs/src/cva6/core/pmp/src/pmp.sv new file mode 100644 index 0000000000..b6d0dbf2ec --- /dev/null +++ b/flow/designs/src/cva6/core/pmp/src/pmp.sv @@ -0,0 +1,75 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Moritz Schneider, ETH Zurich +// Date: 2.10.2019 +// Description: purely combinatorial PMP unit (with extraction for more complex configs such as NAPOT) + +module pmp + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Input + input logic [CVA6Cfg.PLEN-1:0] addr_i, + input riscv::pmp_access_t access_type_i, + input riscv::priv_lvl_t priv_lvl_i, + // Configuration + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] conf_addr_i, + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] conf_i, + // Output + output logic allow_o +); + // if there are no PMPs we can always grant the access. + if (CVA6Cfg.NrPMPEntries > 0) begin : gen_pmp + logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] match; + + for (genvar i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin + logic [CVA6Cfg.PLEN-3:0] conf_addr_prev; + + assign conf_addr_prev = (i == 0) ? '0 : conf_addr_i[i-1]; + + pmp_entry #( + .CVA6Cfg(CVA6Cfg) + ) i_pmp_entry ( + .addr_i (addr_i), + .conf_addr_i (conf_addr_i[i]), + .conf_addr_prev_i(conf_addr_prev), + .conf_addr_mode_i(conf_i[i].addr_mode), + .match_o (match[i]) + ); + end + + always_comb begin + int i; + + allow_o = 1'b0; + for (i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin + // either we are in S or U mode or the config is locked in which + // case it also applies in M mode + if (priv_lvl_i != riscv::PRIV_LVL_M || conf_i[i].locked) begin + if (match[i]) begin + if ((access_type_i & conf_i[i].access_type) != access_type_i) allow_o = 1'b0; + else allow_o = 1'b1; + break; + end + end + end + if (i == CVA6Cfg.NrPMPEntries) begin // no PMP entry matched the address + // allow all accesses from M-mode for no pmp match + if (priv_lvl_i == riscv::PRIV_LVL_M) allow_o = 1'b1; + // disallow accesses for all other modes + else + allow_o = 1'b0; + end + end + end else assign allow_o = 1'b1; + +endmodule diff --git a/flow/designs/src/cva6/core/pmp/src/pmp_data_if.sv b/flow/designs/src/cva6/core/pmp/src/pmp_data_if.sv new file mode 100644 index 0000000000..fc325db260 --- /dev/null +++ b/flow/designs/src/cva6/core/pmp/src/pmp_data_if.sv @@ -0,0 +1,192 @@ +//----------------------------------------------------------------------------- +// Copyright 2024 Robert Bosch GmbH +// +// SPDX-License-Identifier: SHL-0.51 +// +// Original Author: Coralie Allioux - Robert Bosch France SAS +//----------------------------------------------------------------------------- + +module pmp_data_if + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type exception_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // IF interface + input icache_areq_t icache_areq_i, + output icache_areq_t icache_areq_o, + input [CVA6Cfg.VLEN-1:0] icache_fetch_vaddr_i, // virtual address for tval only + // LSU interface + // this is a more minimalistic interface because the actual addressing logic is handled + // in the LSU as we distinguish load and stores, what we do here is simple address translation + input logic lsu_valid_i, // request lsu access + input logic [CVA6Cfg.PLEN-1:0] lsu_paddr_i, // physical address in + input logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_i, // virtual address in, for tval only + input exception_t lsu_exception_i, // lsu exception coming from MMU, or misaligned exception + input logic lsu_is_store_i, // the translation is requested by a store + output logic lsu_valid_o, // translation is valid + output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address + output exception_t lsu_exception_o, // address translation threw an exception + // General control signals + input riscv::priv_lvl_t priv_lvl_i, + input logic v_i, + input riscv::priv_lvl_t ld_st_priv_lvl_i, + input logic ld_st_v_i, + // PMP + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i +); + // virtual address causing the exception + logic [CVA6Cfg.XLEN-1:0] fetch_vaddr_xlen, lsu_vaddr_xlen; + + logic pmp_if_allow; + logic match_any_execute_region; + logic data_allow_o; + + // Wires to PMP checks + riscv::pmp_access_t pmp_access_type; + + logic no_locked_data, no_locked_if; + + // For exception tval reporting, use the virtual address and resize it + if (CVA6Cfg.VLEN >= CVA6Cfg.XLEN) begin + assign lsu_vaddr_xlen = lsu_vaddr_i[CVA6Cfg.XLEN-1:0]; + assign fetch_vaddr_xlen = icache_fetch_vaddr_i[CVA6Cfg.XLEN-1:0]; + end else begin + assign lsu_vaddr_xlen = CVA6Cfg.XLEN'(lsu_vaddr_i); + assign fetch_vaddr_xlen = CVA6Cfg.XLEN'(icache_fetch_vaddr_i); + end + + //----------------------- + // Instruction Interface + //----------------------- + + // check for execute flag on memory + assign match_any_execute_region = config_pkg::is_inside_execute_regions( + CVA6Cfg, {{64 - CVA6Cfg.PLEN{1'b0}}, icache_areq_i.fetch_paddr} + ); + + // As the PMP check is combinatorial, pass the icache_areq directly if no + // exception + always_comb begin : instr_interface + icache_areq_o.fetch_valid = icache_areq_i.fetch_valid; + icache_areq_o.fetch_paddr = icache_areq_i.fetch_paddr; + icache_areq_o.fetch_exception = icache_areq_i.fetch_exception; + + // if it didn't match any execute region throw an `Instruction Access Fault` (PMA) + // or if PMP reject the access + if (!match_any_execute_region || !pmp_if_allow) begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + // For exception, the virtual address is required for tval, if no MMU is + // instantiated then it will be equal to physical address + if (CVA6Cfg.TvalEn) begin + icache_areq_o.fetch_exception.tval = fetch_vaddr_xlen; + end + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end + end + + // Instruction fetch + pmp #( + .CVA6Cfg(CVA6Cfg) + ) i_pmp_if ( + .addr_i (icache_areq_i.fetch_paddr), + .priv_lvl_i (priv_lvl_i), + // we will always execute on the instruction fetch port + .access_type_i(riscv::ACCESS_EXEC), + // Configuration + .conf_addr_i (pmpaddr_i), + .conf_i (pmpcfg_i), + .allow_o (pmp_if_allow) + ); + + //----------------------- + // Data Interface + //----------------------- + always_comb begin : data_interface + // save request and DTLB response + lsu_valid_o = lsu_valid_i; + lsu_paddr_o = lsu_paddr_i; + lsu_exception_o = lsu_exception_i; + pmp_access_type = lsu_is_store_i ? riscv::ACCESS_WRITE : riscv::ACCESS_READ; + + // If translation is not enabled, check the paddr immediately against PMPs + if (lsu_valid_i && !data_allow_o) begin + lsu_exception_o.valid = 1'b1; + + if (CVA6Cfg.TvalEn) begin + lsu_exception_o.tval = lsu_vaddr_xlen; + end + + if (lsu_is_store_i) begin + lsu_exception_o.cause = riscv::ST_ACCESS_FAULT; + end else begin + lsu_exception_o.cause = riscv::LD_ACCESS_FAULT; + end + if (CVA6Cfg.RVH) begin + lsu_exception_o.tval2 = '0; + lsu_exception_o.tinst = '0; + lsu_exception_o.gva = ld_st_v_i; + end + end + end + + // Load/store PMP check + pmp #( + .CVA6Cfg(CVA6Cfg) + ) i_pmp_data ( + .addr_i (lsu_paddr_i), + .priv_lvl_i (ld_st_priv_lvl_i), + .access_type_i(pmp_access_type), + // Configuration + .conf_addr_i (pmpaddr_i), + .conf_i (pmpcfg_i), + .allow_o (data_allow_o) + ); + + // ---------------- + // Assert for PMPs + // ---------------- + + // synthesis translate_off + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + no_locked_data <= 1'b0; + end else begin + if (ld_st_priv_lvl_i == riscv::PRIV_LVL_M) begin + no_locked_data <= 1'b1; + for (int i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin + if (pmpcfg_i[i].locked && pmpcfg_i[i].addr_mode != riscv::OFF) begin + no_locked_data <= no_locked_data & 1'b0; + end else no_locked_data <= no_locked_data & 1'b1; + end + if (no_locked_data == 1'b1) assert (data_allow_o == 1'b1); + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + no_locked_if <= 1'b0; + end else begin + if (priv_lvl_i == riscv::PRIV_LVL_M) begin + no_locked_if <= 1'b1; + for (int i = 0; i < CVA6Cfg.NrPMPEntries; i++) begin + if (pmpcfg_i[i].locked && pmpcfg_i[i].addr_mode != riscv::OFF) begin + no_locked_if <= no_locked_if & 1'b0; + end else no_locked_if <= no_locked_if & 1'b1; + end + if (no_locked_if == 1'b1) assert (pmp_if_allow == 1'b1); + end + end + end + // synthesis translate_on +endmodule diff --git a/flow/designs/src/cva6/core/pmp/src/pmp_entry.sv b/flow/designs/src/cva6/core/pmp/src/pmp_entry.sv new file mode 100644 index 0000000000..d024a9a09f --- /dev/null +++ b/flow/designs/src/cva6/core/pmp/src/pmp_entry.sv @@ -0,0 +1,122 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Moritz Schneider, ETH Zurich +// Date: 2.10.2019 +// Description: single PMP entry + +module pmp_entry #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned PLEN = 56, + parameter int unsigned PMP_LEN = 54 +) ( + // Input + input logic [CVA6Cfg.PLEN-1:0] addr_i, + + // Configuration + input logic [CVA6Cfg.PLEN-3:0] conf_addr_i, + input logic [CVA6Cfg.PLEN-3:0] conf_addr_prev_i, + input riscv::pmp_addr_mode_t conf_addr_mode_i, + + // Output + output logic match_o +); + logic [CVA6Cfg.PLEN-1:0] conf_addr_n; + logic [$clog2(CVA6Cfg.PLEN)-1:0] trail_ones; + logic [CVA6Cfg.PLEN-1:0] base; + logic [CVA6Cfg.PLEN-1:0] mask; + int unsigned size; + assign conf_addr_n = {2'b11, ~conf_addr_i}; + lzc #( + .WIDTH(CVA6Cfg.PLEN), + .MODE (1'b0) + ) i_lzc ( + .in_i (conf_addr_n), + .cnt_o (trail_ones), + .empty_o() + ); + + always_comb begin + case (conf_addr_mode_i) + riscv::TOR: begin + base = '0; + mask = '0; + size = '0; + // check that the requested address is in between the two + // configuration addresses + if (addr_i >= ({2'b0, conf_addr_prev_i} << 2) && addr_i < ({2'b0, conf_addr_i} << 2)) begin + match_o = 1'b1; + end else match_o = 1'b0; + + // synthesis translate_off + if (match_o == 0) begin + assert (addr_i >= ({2'b0, conf_addr_i} << 2) || addr_i < ({2'b0, conf_addr_prev_i} << 2)); + end else begin + assert (addr_i < ({2'b0, conf_addr_i} << 2) && addr_i >= ({2'b0, conf_addr_prev_i} << 2)); + end + // synthesis translate_on + + end + riscv::NAPOT: begin + + // use the extracted trailing ones + size = {{(32 - $clog2(CVA6Cfg.PLEN)) {1'b0}}, trail_ones} + 3; + + mask = '1 << size; + base = ({2'b0, conf_addr_i} << 2) & mask; + match_o = (addr_i & mask) == base ? 1'b1 : 1'b0; + + // synthesis translate_off + // size extract checks + assert (size >= 2); + if (conf_addr_mode_i == riscv::NAPOT) begin + assert (size > 2); + if (size < CVA6Cfg.PLEN - 2) assert (conf_addr_i[size-3] == 0); + for (int i = 0; i < CVA6Cfg.PLEN - 2; i++) begin + if (size > 3 && i <= size - 4) begin + assert (conf_addr_i[i] == 1); // check that all the rest are ones + end + end + end + + if (size < CVA6Cfg.PLEN - 1) begin + if (base + 2 ** size > base) begin // check for overflow + if (match_o == 0) begin + assert (addr_i >= base + 2 ** size || addr_i < base); + end else begin + assert (addr_i < base + 2 ** size && addr_i >= base); + end + end else begin + if (match_o == 0) begin + assert (addr_i - 2 ** size >= base || addr_i < base); + end else begin + assert (addr_i - 2 ** size < base && addr_i >= base); + end + end + end + // synthesis translate_on + + end + riscv::OFF: begin + match_o = 1'b0; + base = '0; + mask = '0; + size = '0; + end + default: begin + match_o = 0; + base = '0; + mask = '0; + size = '0; + end + endcase + end + +endmodule diff --git a/flow/designs/src/cva6/core/scoreboard.sv b/flow/designs/src/cva6/core/scoreboard.sv new file mode 100644 index 0000000000..6a1b3d094f --- /dev/null +++ b/flow/designs/src/cva6/core/scoreboard.sv @@ -0,0 +1,356 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 08.04.2017 +// Description: Scoreboard - keeps track of all decoded, issued and committed instructions + +module scoreboard #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type exception_t = logic, + parameter type scoreboard_entry_t = logic, + parameter type forwarding_t = logic, + parameter type writeback_t = logic, + parameter type rs3_len_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Is scoreboard full - PERF_COUNTERS + output logic sb_full_o, + // Prevent from issuing - CONTROLLER + input logic flush_unissued_instr_i, + // Flush whole scoreboard - CONTROLLER + input logic flush_i, + // Writeback Handling of CVXIF + // TO_BE_COMPLETED - ISSUE_READ_OPERANDS + input logic x_transaction_accepted_i, + // TO_BE_COMPLETED - ISSUE_READ_OPERANDS + input logic x_issue_writeback_i, + // TO_BE_COMPLETED - ISSUE_READ_OPERANDS + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_id_i, + // advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer + // Instructions to commit - COMMIT_STAGE + output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, + // Instruction is cancelled - COMMIT_STAGE + output logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_o, + // Commit acknowledge - COMMIT_STAGE + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + + // instruction to put on top of scoreboard e.g.: top pointer + // we can always put this instruction to the top unless we signal with asserted full_o + // Handshake's data with decode stage - ID_STAGE + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i, + // instruction value - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i, + // Handshake's valid with decode stage - ID_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, + // Handshake's acknowlege with decode stage - ID_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o, + + // instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer + // Entry about the instruction to issue - ISSUE_READ_OPERANDS + output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_o, + // Instruction to issue - ISSUE_READ_OPERANDS + output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_o, + // Is there an instruction to issue - ISSUE_READ_OPERANDS + output logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_o, + // Issue stage acknowledge - ISSUE_READ_OPERANDS + input logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_i, + // Forwarding - ISSUE_READ_OPERANDS + output forwarding_t fwd_o, + + // Result from branch unit - EX_STAGE + input bp_resolve_t resolved_branch_i, + // Transaction ID at which to write the result back - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i, + // Results to write back - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i, + // Exception from a functional unit (e.g.: ld/st exception) - EX_STAGE + input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, + // Indicates valid results - EX_STAGE + input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, + // Cvxif we for writeback - EX_STAGE + input logic x_we_i, + // CVXIF destination register - ISSUE_STAGE + input logic [4:0] x_rd_i, + + // Issue pointer - RVFI + output logic [ CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o, + // Commit pointer - RVFI + output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o +); + + // this is the FIFO struct of the issue queue + typedef struct packed { + logic issued; // this bit indicates whether we issued this instruction e.g.: if it is valid + logic cancelled; // this instruction was cancelled (speculative scoreboard) + logic is_rd_fpr_flag; // redundant meta info, added for speed + scoreboard_entry_t sbe; // this is the score board entry we will send to ex + } sb_mem_t; + sb_mem_t [CVA6Cfg.NR_SB_ENTRIES-1:0] mem_q, mem_n; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued; + + logic [CVA6Cfg.NrIssuePorts-1:0] issue_full; + logic [1:0][CVA6Cfg.NR_SB_ENTRIES/2-1:0] issued_instrs_even_odd; + + logic bmiss; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] after_flu_wb; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] speculative_instrs; + + logic [CVA6Cfg.NrIssuePorts-1:0] num_issue; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_n, issue_pointer_q; + logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer; + + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_n, commit_pointer_q; + logic [$clog2(CVA6Cfg.NrCommitPorts):0] num_commit; + + for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + assign still_issued[i] = mem_q[i].issued & ~mem_q[i].cancelled; + end + + for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + assign issued_instrs_even_odd[i%2][i/2] = mem_q[i].issued; + end + + // the issue queue is full don't issue any new instructions + assign issue_full[0] = &issued_instrs_even_odd[0] && &issued_instrs_even_odd[1]; + if (CVA6Cfg.SuperscalarEn) begin : assign_issue_full + // Need two slots available to issue two instructions. + // They are next to each other so one must be even and one odd + assign issue_full[1] = &issued_instrs_even_odd[0] || &issued_instrs_even_odd[1]; + end + + assign sb_full_o = issue_full[0]; + + // output commit instruction directly + always_comb begin : commit_ports + for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + commit_instr_o[i] = mem_q[commit_pointer_q[i]].sbe; + commit_instr_o[i].trans_id = commit_pointer_q[i]; + commit_drop_o[i] = mem_q[commit_pointer_q[i]].cancelled; + end + end + + assign issue_pointer[0] = issue_pointer_q; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign issue_pointer[i+1] = issue_pointer[i] + 'd1; + end + + // an instruction is ready for issue if we have place in the issue FIFO and it the decoder says it is valid + always_comb begin + issue_instr_o = decoded_instr_i; + orig_instr_o = orig_instr_i; + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + // make sure we assign the correct trans ID + issue_instr_o[i].trans_id = issue_pointer[i]; + + issue_instr_valid_o[i] = decoded_instr_valid_i[i] & ~issue_full[i]; + decoded_instr_ack_o[i] = issue_ack_i[i] & ~issue_full[i]; + end + end + + // maintain a FIFO with issued instructions + // keep track of all issued instructions + always_comb begin : issue_fifo + // default assignment + mem_n = mem_q; + num_issue = '0; + + // if we got a acknowledge from the issue stage, put this scoreboard entry in the queue + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (decoded_instr_valid_i[i] && decoded_instr_ack_o[i] && !flush_unissued_instr_i) begin + // the decoded instruction we put in there is valid (1st bit) + // increase the issue counter and advance issue pointer + num_issue += 'd1; + mem_n[issue_pointer[i]] = '{ + issued: 1'b1, + cancelled: 1'b0, + is_rd_fpr_flag: CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(decoded_instr_i[i].op), + sbe: decoded_instr_i[i] + }; + end + end + + // ------------ + // FU NONE + // ------------ + for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + // The FU is NONE -> this instruction is valid immediately + if (mem_q[i].sbe.fu == ariane_pkg::NONE && mem_q[i].issued) mem_n[i].sbe.valid = 1'b1; + end + + // ------------ + // Write Back + // ------------ + for (int unsigned i = 0; i < CVA6Cfg.NrWbPorts; i++) begin + // check if this instruction was issued (e.g.: it could happen after a flush that there is still + // something in the pipeline e.g. an incomplete memory operation) + if (wt_valid_i[i] && mem_q[trans_id_i[i]].issued) begin + if (mem_q[trans_id_i[i]].sbe.is_double_rd_macro_instr && mem_q[trans_id_i[i]].sbe.is_macro_instr) begin + if (mem_q[trans_id_i[i]].sbe.is_last_macro_instr) begin + mem_n[trans_id_i[i]].sbe.valid = 1'b1; + mem_n[8'(trans_id_i[i])-1].sbe.valid = 1'b1; + end else begin + mem_n[trans_id_i[i]].sbe.valid = 1'b0; + end + end else begin + mem_n[trans_id_i[i]].sbe.valid = 1'b1; + end + mem_n[trans_id_i[i]].sbe.result = wbdata_i[i]; + // save the target address of a branch (needed for debug in commit stage) + if (CVA6Cfg.DebugEn) begin + mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address; + end + if (mem_n[trans_id_i[i]].sbe.fu == ariane_pkg::CVXIF) begin + if (x_we_i) mem_n[trans_id_i[i]].sbe.rd = x_rd_i; + else mem_n[trans_id_i[i]].sbe.rd = 5'b0; + end + // write the exception back if it is valid + if (ex_i[i].valid) mem_n[trans_id_i[i]].sbe.ex = ex_i[i]; + // write the fflags back from the FPU (exception valid is never set), leave tval intact + else if(CVA6Cfg.FpPresent && (mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU || mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU_VEC)) begin + mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause; + end + end + end + + // ------------ + // Cancel + // ------------ + if (CVA6Cfg.SpeculativeSb) begin + if (bmiss) begin + if (after_flu_wb != issue_pointer[0]) begin + mem_n[after_flu_wb].cancelled = 1'b1; + end + end + end + + // ------------ + // Commit Port + // ------------ + // we've got an acknowledge from commit + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + if (commit_ack_i[i]) begin + // this instruction is no longer in issue e.g.: it is considered finished + mem_n[commit_pointer_q[i]].issued = 1'b0; + mem_n[commit_pointer_q[i]].cancelled = 1'b0; + mem_n[commit_pointer_q[i]].sbe.valid = 1'b0; + end + end + + // ------ + // Flush + // ------ + if (flush_i) begin + for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + // set all valid flags for all entries to zero + mem_n[i].issued = 1'b0; + mem_n[i].cancelled = 1'b0; + mem_n[i].sbe.valid = 1'b0; + mem_n[i].sbe.ex.valid = 1'b0; + end + end + end + + assign bmiss = resolved_branch_i.valid && resolved_branch_i.is_mispredict; + assign after_flu_wb = trans_id_i[ariane_pkg::FLU_WB] + 'd1; + + // FIFO counter updates + if (CVA6Cfg.NrCommitPorts == 2) begin : gen_commit_ports + assign num_commit = commit_ack_i[1] + commit_ack_i[0]; + end else begin : gen_one_commit_port + assign num_commit = commit_ack_i[0]; + end + + assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit; + + always_comb begin : assign_issue_pointer_n + issue_pointer_n = issue_pointer[num_issue]; + if (flush_i) issue_pointer_n = '0; + end + + // precompute offsets for commit slots + for (genvar k = 1; k < CVA6Cfg.NrCommitPorts; k++) begin : gen_cnt_incr + assign commit_pointer_n[k] = (flush_i) ? '0 : commit_pointer_n[0] + unsigned'(k); + end + + // Forwarding logic + writeback_t [CVA6Cfg.NrWbPorts-1:0] wb; + for (genvar i = 0; i < CVA6Cfg.NrWbPorts; i++) begin + assign wb[i].valid = wt_valid_i[i]; + assign wb[i].data = wbdata_i[i]; + assign wb[i].ex_valid = ex_i[i].valid; + assign wb[i].trans_id = trans_id_i[i]; + end + + assign fwd_o.still_issued = still_issued; + assign fwd_o.issue_pointer = issue_pointer; + assign fwd_o.wb = wb; + for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + assign fwd_o.sbe[i] = mem_q[i].sbe; + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin : regs + if (!rst_ni) begin + mem_q <= '{default: sb_mem_t'(0)}; + commit_pointer_q <= '0; + issue_pointer_q <= '0; + end else begin + issue_pointer_q <= issue_pointer_n; + mem_q <= mem_n; + mem_q[x_id_i].sbe.rd <= (x_transaction_accepted_i && ~x_issue_writeback_i) ? 5'b0 : mem_n[x_id_i].sbe.rd; + commit_pointer_q <= commit_pointer_n; + end + end + + //RVFI + assign rvfi_issue_pointer_o = issue_pointer[CVA6Cfg.NrIssuePorts-1:0]; + assign rvfi_commit_pointer_o = commit_pointer_q; + + //pragma translate_off + initial begin + assert (CVA6Cfg.NR_SB_ENTRIES == 2 ** CVA6Cfg.TRANS_ID_BITS) + else $fatal(1, "Scoreboard size needs to be a power of two."); + end + // assert that we never acknowledge a commit if the instruction is not valid + assert property ( + @(posedge clk_i) disable iff (!rst_ni) commit_ack_i[0] |-> commit_instr_o[0].valid) + else $fatal(1, "Commit acknowledged but instruction is not valid"); + if (CVA6Cfg.NrCommitPorts == 2) begin : gen_two_commit_ports + assert property ( + @(posedge clk_i) disable iff (!rst_ni) commit_ack_i[1] |-> commit_instr_o[1].valid) + else $fatal(1, "Commit acknowledged but instruction is not valid"); + end + // assert that we never give an issue ack signal if the instruction is not valid + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assert property ( + @(posedge clk_i) disable iff (!rst_ni) issue_ack_i[i] |-> issue_instr_valid_o[i]) + else $fatal(1, "Issue acknowledged but instruction is not valid"); + end + + // there should never be more than one instruction writing the same destination register (except x0) + // check that no functional unit is retiring with the same transaction id + for (genvar i = 0; i < CVA6Cfg.NrWbPorts; i++) begin + for (genvar j = 0; j < CVA6Cfg.NrWbPorts; j++) begin + assert property ( + @(posedge clk_i) disable iff (!rst_ni) wt_valid_i[i] && wt_valid_i[j] && (i != j) |-> (trans_id_i[i] != trans_id_i[j])) + else + $fatal( + 1, + "Two or more functional units are retiring instructions with the same transaction id!" + ); + end + end + //pragma translate_on +endmodule diff --git a/flow/designs/src/cva6/core/serdiv.sv b/flow/designs/src/cva6/core/serdiv.sv new file mode 100644 index 0000000000..fd103fbb91 --- /dev/null +++ b/flow/designs/src/cva6/core/serdiv.sv @@ -0,0 +1,277 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Andreas Traber , ETH Zurich +// +// Date: 18.10.2018 +// Description: simple 64bit serial divider + + +module serdiv + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter WIDTH = 64, + parameter STABLE_HANDSHAKE = 0 // Guarantee a stable in_rdy_o during the input handshake. Keep it at 0 in CVA6 +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Serdiv translation ID - Mult + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] id_i, + // A operand - Mult + input logic [WIDTH-1:0] op_a_i, + // B operand - Mult + input logic [WIDTH-1:0] op_b_i, + // Serdiv operation - Mult + input logic [1:0] opcode_i, // 0: udiv, 2: urem, 1: div, 3: rem + // Serdiv instruction is valid - Mult + input logic in_vld_i, + // Serdiv FU is ready - Mult + output logic in_rdy_o, + // Flush - CONTROLLER + input logic flush_i, + // Serdiv result is valid - Mult + output logic out_vld_o, + // Serdiv is ready - Mult + input logic out_rdy_i, + // Serdiv transaction ID - Mult + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] id_o, + // Serdiv result - Mult + output logic [WIDTH-1:0] res_o +); + + ///////////////////////////////////// + // signal declarations + ///////////////////////////////////// + + enum logic [1:0] { + IDLE, + DIVIDE, + FINISH + } + state_d, state_q; + + logic [WIDTH-1:0] res_q, res_d; + logic [WIDTH-1:0] op_a_q, op_a_d; + logic [WIDTH-1:0] op_b_q, op_b_d; + logic op_a_sign, op_b_sign; + logic op_b_zero, op_b_zero_q, op_b_zero_d; + logic op_b_neg_one, op_b_neg_one_q, op_b_neg_one_d; + + logic [CVA6Cfg.TRANS_ID_BITS-1:0] id_q, id_d; + + logic rem_sel_d, rem_sel_q; + logic comp_inv_d, comp_inv_q; + logic res_inv_d, res_inv_q; + + logic [WIDTH-1:0] add_mux; + logic [WIDTH-1:0] add_out; + logic [WIDTH-1:0] add_tmp; + logic [WIDTH-1:0] b_mux; + logic [WIDTH-1:0] out_mux; + + logic [$clog2(WIDTH)-1:0] cnt_q, cnt_d; + logic cnt_zero; + + logic [WIDTH-1:0] lzc_a_input, lzc_b_input, op_b; + logic [$clog2(WIDTH)-1:0] lzc_a_result, lzc_b_result; + logic [$clog2(WIDTH+1)-1:0] shift_a; + logic [ $clog2(WIDTH+1):0] div_shift; + + logic a_reg_en, b_reg_en, res_reg_en, ab_comp, pm_sel, load_en; + logic lzc_a_no_one, lzc_b_no_one; + logic div_res_zero_d, div_res_zero_q; + + + ///////////////////////////////////// + // align the input operands + // for faster division + ///////////////////////////////////// + + assign op_a_sign = op_a_i[$high(op_a_i)]; + assign op_b_sign = op_b_i[$high(op_b_i)]; + assign op_b_zero = lzc_b_no_one & ~op_b_sign; + assign op_b_neg_one = lzc_b_no_one & op_b_sign; + + assign lzc_a_input = (opcode_i[0] & op_a_sign) ? {~op_a_i[$high(op_a_i)-1:0], 1'b1} : op_a_i; + assign lzc_b_input = (opcode_i[0] & op_b_sign) ? ~op_b_i : op_b_i; + + lzc #( + .MODE (1), // count leading zeros + .WIDTH(WIDTH) + ) i_lzc_a ( + .in_i (lzc_a_input), + .cnt_o (lzc_a_result), + .empty_o(lzc_a_no_one) + ); + + lzc #( + .MODE (1), // count leading zeros + .WIDTH(WIDTH) + ) i_lzc_b ( + .in_i (lzc_b_input), + .cnt_o (lzc_b_result), + .empty_o(lzc_b_no_one) + ); + + assign shift_a = (lzc_a_no_one) ? WIDTH : {1'b0, lzc_a_result}; + assign div_shift = {1'b0, lzc_b_result} - shift_a; + + assign op_b = op_b_i <<< div_shift; + + // the division is zero if |opB| > |opA| and can be terminated + assign div_res_zero_d = (load_en) ? div_shift[$high(div_shift)] : div_res_zero_q; + + ///////////////////////////////////// + // Datapath + ///////////////////////////////////// + + assign pm_sel = load_en & ~(opcode_i[0] & (op_a_sign ^ op_b_sign)); + + // muxes + assign add_mux = (load_en) ? op_a_i : op_b_q; + + // attention: logical shift by one in case of negative operand B! + assign b_mux = (load_en) ? op_b : {comp_inv_q, (op_b_q[$high(op_b_q):1])}; + + // in case of bad timing, we could output from regs -> needs a cycle more in the FSM + assign out_mux = (rem_sel_q) ? (op_b_neg_one_q ? '0 : op_a_q) : (op_b_zero_q ? '1 : (op_b_neg_one_q ? op_a_q : res_q)); + + // invert if necessary + assign res_o = (res_inv_q) ? -$signed(out_mux) : out_mux; + + // main comparator + assign ab_comp = ((op_a_q == op_b_q) | ((op_a_q > op_b_q) ^ comp_inv_q)) & ((|op_a_q) | op_b_zero_q); + + // main adder + assign add_tmp = (load_en) ? 0 : op_a_q; + assign add_out = (pm_sel) ? add_tmp + add_mux : add_tmp - $signed(add_mux); + + ///////////////////////////////////// + // FSM, counter + ///////////////////////////////////// + + assign cnt_zero = (cnt_q == 0); + assign cnt_d = (load_en) ? div_shift[$clog2(WIDTH)-1:0] : (~cnt_zero) ? cnt_q - 1 : cnt_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + in_rdy_o = 1'b0; + out_vld_o = 1'b0; + load_en = 1'b0; + a_reg_en = 1'b0; + b_reg_en = 1'b0; + res_reg_en = 1'b0; + + unique case (state_q) + IDLE: begin + in_rdy_o = 1'b1; + + if (in_vld_i) begin + // CVA6: there is a cycle delay until the valid signal is asserted by the id stage + // Ara: we need a stable handshake + in_rdy_o = (STABLE_HANDSHAKE) ? 1'b1 : 1'b0; + a_reg_en = 1'b1; + b_reg_en = 1'b1; + load_en = 1'b1; + state_d = DIVIDE; + end + end + DIVIDE: begin + if (~(div_res_zero_q | op_b_zero_q | op_b_neg_one_q)) begin + a_reg_en = ab_comp; + b_reg_en = 1'b1; + res_reg_en = 1'b1; + end + // can end the division immediately if the result is known + if (div_res_zero_q | op_b_zero_q | op_b_neg_one_q) begin + out_vld_o = 1'b1; + state_d = FINISH; + if (out_rdy_i) begin + // in_rdy_o = 1'b1;// there is a cycle delay until the valid signal is asserted by the id stage + state_d = IDLE; + end + end else if (cnt_zero) begin + state_d = FINISH; + end + end + FINISH: begin + out_vld_o = 1'b1; + + if (out_rdy_i) begin + // in_rdy_o = 1'b1;// there is a cycle delay until the valid signal is asserted by the id stage + state_d = IDLE; + end + end + default: state_d = IDLE; + endcase + + if (flush_i) begin + a_reg_en = 1'b0; + b_reg_en = 1'b0; + load_en = 1'b0; + state_d = IDLE; + end + end + + ///////////////////////////////////// + // regs, flags + ///////////////////////////////////// + + // get flags + assign rem_sel_d = (load_en) ? opcode_i[1] : rem_sel_q; + assign comp_inv_d = (load_en) ? opcode_i[0] & op_b_sign : comp_inv_q; + assign op_b_zero_d = (load_en) ? op_b_zero : op_b_zero_q; + assign op_b_neg_one_d = (load_en) ? op_b_neg_one : op_b_neg_one_q; + assign res_inv_d = (load_en) ? (~op_b_zero | opcode_i[1]) & opcode_i[0] & (op_a_sign ^ op_b_sign ^ op_b_neg_one) : res_inv_q; + + // transaction id + assign id_d = (load_en) ? id_i : id_q; + assign id_o = id_q; + + assign op_a_d = (a_reg_en) ? add_out : op_a_q; + assign op_b_d = (b_reg_en) ? b_mux : op_b_q; + assign res_d = (load_en) ? '0 : (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (~rst_ni) begin + state_q <= IDLE; + op_a_q <= '0; + op_b_q <= '0; + res_q <= '0; + cnt_q <= '0; + id_q <= '0; + rem_sel_q <= 1'b0; + comp_inv_q <= 1'b0; + res_inv_q <= 1'b0; + op_b_zero_q <= 1'b0; + op_b_neg_one_q <= 1'b0; + div_res_zero_q <= 1'b0; + end else begin + state_q <= state_d; + op_a_q <= op_a_d; + op_b_q <= op_b_d; + res_q <= res_d; + cnt_q <= cnt_d; + id_q <= id_d; + rem_sel_q <= rem_sel_d; + comp_inv_q <= comp_inv_d; + res_inv_q <= res_inv_d; + op_b_zero_q <= op_b_zero_d; + op_b_neg_one_q <= op_b_neg_one_d; + div_res_zero_q <= div_res_zero_d; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/store_buffer.sv b/flow/designs/src/cva6/core/store_buffer.sv new file mode 100644 index 0000000000..7c22a97fe2 --- /dev/null +++ b/flow/designs/src/cva6/core/store_buffer.sv @@ -0,0 +1,293 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 25.04.2017 +// Description: Store queue persists store requests and pushes them to memory +// if they are no longer speculative + + +module store_buffer + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // if we flush we need to pause the transactions on the memory + // otherwise we will run in a deadlock with the memory arbiter + input logic stall_st_pending_i, // Stall issuing non-speculative request + output logic no_st_pending_o, // non-speculative queue is empty (e.g.: everything is committed to the memory hierarchy) + output logic store_buffer_empty_o, // there is no store pending in neither the speculative unit or the non-speculative queue + + input logic [11:0] page_offset_i, // check for the page offset (the last 12 bit if the current load matches them) + output logic page_offset_matches_o, // the above input page offset matches -> let the store buffer drain + + input logic commit_i, // commit the instruction which was placed there most recently + output logic commit_ready_o, // commit queue is ready to accept another commit request + output logic ready_o, // the store queue is ready to accept a new request + // it is only ready if it can unconditionally commit the instruction, e.g.: + // the commit buffer needs to be empty + input logic valid_i, // this is a valid store + input logic valid_without_flush_i, // just tell if the address is valid which we are current putting and do not take any further action + + input logic [CVA6Cfg.PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue + input logic [(CVA6Cfg.XLEN/8)-1:0] be_i, // byte enable in + input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) + + // D$ interface + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o +); + + // the store queue has two parts: + // 1. Speculative queue + // 2. Commit queue which is non-speculative, e.g.: the store will definitely happen. + struct packed { + logic [CVA6Cfg.PLEN-1:0] address; + logic [CVA6Cfg.XLEN-1:0] data; + logic [(CVA6Cfg.XLEN/8)-1:0] be; + logic [1:0] data_size; + logic valid; // this entry is valid, we need this for checking if the address offset matches + } + speculative_queue_n[DEPTH_SPEC-1:0], + speculative_queue_q[DEPTH_SPEC-1:0], + commit_queue_n[DEPTH_COMMIT-1:0], + commit_queue_q[DEPTH_COMMIT-1:0]; + + // keep a status count for both buffers + logic [$clog2(DEPTH_SPEC):0] speculative_status_cnt_n, speculative_status_cnt_q; + logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt_n, commit_status_cnt_q; + // Speculative queue + logic [$clog2(DEPTH_SPEC)-1:0] speculative_read_pointer_n, speculative_read_pointer_q; + logic [$clog2(DEPTH_SPEC)-1:0] speculative_write_pointer_n, speculative_write_pointer_q; + // Commit Queue + logic [$clog2(DEPTH_COMMIT)-1:0] commit_read_pointer_n, commit_read_pointer_q; + logic [$clog2(DEPTH_COMMIT)-1:0] commit_write_pointer_n, commit_write_pointer_q; + + assign store_buffer_empty_o = (speculative_status_cnt_q == 0) & no_st_pending_o; + // ---------------------------------------- + // Speculative Queue - Core Interface + // ---------------------------------------- + always_comb begin : core_if + automatic logic [$clog2(DEPTH_SPEC):0] speculative_status_cnt; + speculative_status_cnt = speculative_status_cnt_q; + + // default assignments + speculative_read_pointer_n = speculative_read_pointer_q; + speculative_write_pointer_n = speculative_write_pointer_q; + speculative_queue_n = speculative_queue_q; + // LSU interface + // we are ready to accept a new entry and the input data is valid + if (valid_i) begin + speculative_queue_n[speculative_write_pointer_q].address = paddr_i; + speculative_queue_n[speculative_write_pointer_q].data = data_i; + speculative_queue_n[speculative_write_pointer_q].be = be_i; + speculative_queue_n[speculative_write_pointer_q].data_size = data_size_i; + speculative_queue_n[speculative_write_pointer_q].valid = 1'b1; + // advance the write pointer + speculative_write_pointer_n = speculative_write_pointer_q + 1'b1; + speculative_status_cnt++; + end + + // evict the current entry out of this queue, the commit queue will thankfully take it and commit it + // to the memory hierarchy + if (commit_i) begin + // invalidate + speculative_queue_n[speculative_read_pointer_q].valid = 1'b0; + // advance the read pointer + speculative_read_pointer_n = speculative_read_pointer_q + 1'b1; + speculative_status_cnt--; + end + + speculative_status_cnt_n = speculative_status_cnt; + + // when we flush evict the speculative stores + if (flush_i) begin + // reset all valid flags + for (int unsigned i = 0; i < DEPTH_SPEC; i++) speculative_queue_n[i].valid = 1'b0; + + speculative_write_pointer_n = speculative_read_pointer_q; + // also reset the status count + speculative_status_cnt_n = 'b0; + end + + // we are ready if the speculative and the commit queue have a space left + ready_o = (speculative_status_cnt_n < (DEPTH_SPEC)) || commit_i; + end + + // ---------------------------------------- + // Commit Queue - Memory Interface + // ---------------------------------------- + + // we will never kill a request in the store buffer since we already know that the translation is valid + // e.g.: a kill request will only be necessary if we are not sure if the requested memory address will result in a TLB fault + assign req_port_o.kill_req = 1'b0; + assign req_port_o.data_we = 1'b1; // we will always write in the store queue + assign req_port_o.tag_valid = 1'b0; + + // we do not require an acknowledgement for writes, thus we do not need to identify uniquely the responses + assign req_port_o.data_id = '0; + // those signals can directly be output to the memory + assign req_port_o.address_index = commit_queue_q[commit_read_pointer_q].address[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; + // if we got a new request we already saved the tag from the previous cycle + assign req_port_o.address_tag = commit_queue_q[commit_read_pointer_q].address[CVA6Cfg.DCACHE_TAG_WIDTH + + CVA6Cfg.DCACHE_INDEX_WIDTH-1 : + CVA6Cfg.DCACHE_INDEX_WIDTH]; + assign req_port_o.data_wdata = commit_queue_q[commit_read_pointer_q].data; + assign req_port_o.data_wuser = '0; + assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be; + assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size; + + assign rvfi_mem_paddr_o = speculative_queue_q[speculative_read_pointer_q].address; + + always_comb begin : store_if + automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt; + commit_status_cnt = commit_status_cnt_q; + + commit_ready_o = (commit_status_cnt_q < DEPTH_COMMIT); + // no store is pending if we don't have any element in the commit queue e.g.: it is empty + no_st_pending_o = (commit_status_cnt_q == 0); + // default assignments + commit_read_pointer_n = commit_read_pointer_q; + commit_write_pointer_n = commit_write_pointer_q; + + commit_queue_n = commit_queue_q; + + req_port_o.data_req = 1'b0; + + // there should be no commit when we are flushing + // if the entry in the commit queue is valid and not speculative anymore we can issue this instruction + if (commit_queue_q[commit_read_pointer_q].valid && !stall_st_pending_i) begin + req_port_o.data_req = 1'b1; + if (req_port_i.data_gnt) begin + // we can evict it from the commit buffer + commit_queue_n[commit_read_pointer_q].valid = 1'b0; + // advance the read_pointer + commit_read_pointer_n = commit_read_pointer_q + 1'b1; + commit_status_cnt--; + end + end + // we ignore the rvalid signal for now as we assume that the store + // happened if we got a grant + + // shift the store request from the speculative buffer to the non-speculative + if (commit_i) begin + commit_queue_n[commit_write_pointer_q] = speculative_queue_q[speculative_read_pointer_q]; + commit_write_pointer_n = commit_write_pointer_n + 1'b1; + commit_status_cnt++; + end + + commit_status_cnt_n = commit_status_cnt; + end + + // ------------------ + // Address Checker + // ------------------ + // The load should return the data stored by the most recent store to the + // same physical address. The most direct way to implement this is to + // maintain physical addresses in the store buffer. + + // Of course, there are other micro-architectural techniques to accomplish + // the same thing: you can interlock and wait for the store buffer to + // drain if the load VA matches any store VA modulo the page size (i.e. + // bits 11:0). As a special case, it is correct to bypass if the full VA + // matches, and no younger stores' VAs match in bits 11:0. + // + // checks if the requested load is in the store buffer + // page offsets are virtually and physically the same + always_comb begin : address_checker + page_offset_matches_o = 1'b0; + + // check if the LSBs are identical and the entry is valid + for (int unsigned i = 0; i < DEPTH_COMMIT; i++) begin + // Check if the page offset matches and whether the entry is valid, for the commit queue + if ((page_offset_i[11:3] == commit_queue_q[i].address[11:3]) && commit_queue_q[i].valid) begin + page_offset_matches_o = 1'b1; + break; + end + end + + for (int unsigned i = 0; i < DEPTH_SPEC; i++) begin + // do the same for the speculative queue + if ((page_offset_i[11:3] == speculative_queue_q[i].address[11:3]) && speculative_queue_q[i].valid) begin + page_offset_matches_o = 1'b1; + break; + end + end + // or it matches with the entry we are currently putting into the queue + if ((page_offset_i[11:3] == paddr_i[11:3]) && valid_without_flush_i) begin + page_offset_matches_o = 1'b1; + end + end + + + // registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_spec + if (~rst_ni) begin + speculative_queue_q <= '{default: 0}; + speculative_read_pointer_q <= '0; + speculative_write_pointer_q <= '0; + speculative_status_cnt_q <= '0; + end else begin + speculative_queue_q <= speculative_queue_n; + speculative_read_pointer_q <= speculative_read_pointer_n; + speculative_write_pointer_q <= speculative_write_pointer_n; + speculative_status_cnt_q <= speculative_status_cnt_n; + end + end + + // registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_commit + if (~rst_ni) begin + commit_queue_q <= '{default: 0}; + commit_read_pointer_q <= '0; + commit_write_pointer_q <= '0; + commit_status_cnt_q <= '0; + end else begin + commit_queue_q <= commit_queue_n; + commit_read_pointer_q <= commit_read_pointer_n; + commit_write_pointer_q <= commit_write_pointer_n; + commit_status_cnt_q <= commit_status_cnt_n; + end + end + + /////////////////////////////////////////////////////// + // assertions + /////////////////////////////////////////////////////// + + //pragma translate_off + // assert that commit is never set when we are flushing this would be counter intuitive + // as flush and commit is decided in the same stage + commit_and_flush : + assert property (@(posedge clk_i) rst_ni && flush_i |-> !commit_i) + else $error("[Commit Queue] You are trying to commit and flush in the same cycle"); + + speculative_buffer_overflow : + assert property (@(posedge clk_i) rst_ni && (speculative_status_cnt_q == DEPTH_SPEC) |-> !valid_i) + else + $error("[Speculative Queue] You are trying to push new data although the buffer is not ready"); + + speculative_buffer_underflow : + assert property (@(posedge clk_i) rst_ni && (speculative_status_cnt_q == 0) |-> !commit_i) + else $error("[Speculative Queue] You are committing although there are no stores to commit"); + + commit_buffer_overflow : + assert property (@(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_COMMIT) |-> !commit_i) + else $error("[Commit Queue] You are trying to commit a store although the buffer is full"); + //pragma translate_on +endmodule + + + diff --git a/flow/designs/src/cva6/core/store_unit.sv b/flow/designs/src/cva6/core/store_unit.sv new file mode 100644 index 0000000000..141763dda7 --- /dev/null +++ b/flow/designs/src/cva6/core/store_unit.sv @@ -0,0 +1,366 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 22.05.2017 +// Description: Store Unit, takes care of all store requests and atomic memory operations (AMOs) + + +module store_unit + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, + parameter type lsu_ctrl_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush - CONTROLLER + input logic flush_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic stall_st_pending_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic no_st_pending_o, + // Store buffer is empty - TO_BE_COMPLETED + output logic store_buffer_empty_o, + // Store instruction is valid - ISSUE_STAGE + input logic valid_i, + // Data input - ISSUE_STAGE + input lsu_ctrl_t lsu_ctrl_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic pop_st_o, + // Instruction commit - TO_BE_COMPLETED + input logic commit_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic commit_ready_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic amo_valid_commit_i, + // Store result is valid - ISSUE_STAGE + output logic valid_o, + // Transaction ID - ISSUE_STAGE + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_o, + // Store result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] result_o, + // Store exception output - TO_BE_COMPLETED + output exception_t ex_o, + // Address translation request - TO_BE_COMPLETED + output logic translation_req_o, + // Virtual address - TO_BE_COMPLETED + output logic [CVA6Cfg.VLEN-1:0] vaddr_o, + // RVFI information - RVFI + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + // Transformed trap instruction out - TO_BE_COMPLETED + output logic [31:0] tinst_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic hs_ld_st_inst_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED + output logic hlvx_inst_o, + // Physical address - TO_BE_COMPLETED + input logic [CVA6Cfg.PLEN-1:0] paddr_i, + // Exception raised before store - TO_BE_COMPLETED + input exception_t ex_i, + // Data TLB hit - lsu + input logic dtlb_hit_i, + // Address to be checked - load_unit + input logic [11:0] page_offset_i, + // Address check result - load_unit + output logic page_offset_matches_o, + // AMO request - CACHES + output amo_req_t amo_req_o, + // AMO response - CACHES + input amo_resp_t amo_resp_i, + // Data cache request - CACHES + input dcache_req_o_t req_port_i, + // Data cache response - CACHES + output dcache_req_i_t req_port_o +); + + // align data to address e.g.: shift data to be naturally 64 + function automatic [CVA6Cfg.XLEN-1:0] data_align(logic [2:0] addr, logic [63:0] data); + // Set addr[2] to 1'b0 when 32bits + logic [ 2:0] addr_tmp = {(addr[2] && CVA6Cfg.IS_XLEN64), addr[1:0]}; + logic [63:0] data_tmp = {64{1'b0}}; + case (addr_tmp) + 3'b000: data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-1:0]}; + 3'b001: + data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-9:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-8]}; + 3'b010: + data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-17:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-16]}; + 3'b011: + data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-25:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-24]}; + default: + if (CVA6Cfg.IS_XLEN64) begin + case (addr_tmp) + 3'b100: data_tmp = {data[31:0], data[63:32]}; + 3'b101: data_tmp = {data[23:0], data[63:24]}; + 3'b110: data_tmp = {data[15:0], data[63:16]}; + 3'b111: data_tmp = {data[7:0], data[63:8]}; + default: data_tmp = {data[63:0]}; + endcase + end + endcase + return data_tmp[CVA6Cfg.XLEN-1:0]; + endfunction + + // it doesn't matter what we are writing back as stores don't return anything + assign result_o = lsu_ctrl_i.data; + + enum logic [1:0] { + IDLE, + VALID_STORE, + WAIT_TRANSLATION, + WAIT_STORE_READY + } + state_d, state_q; + + // store buffer control signals + logic st_ready; + logic st_valid; + logic st_valid_without_flush; + logic instr_is_amo; + assign instr_is_amo = is_amo(lsu_ctrl_i.operation); + // keep the data and the byte enable for the second cycle (after address translation) + logic [CVA6Cfg.XLEN-1:0] st_data_n, st_data_q; + logic [(CVA6Cfg.XLEN/8)-1:0] st_be_n, st_be_q; + logic [1:0] st_data_size_n, st_data_size_q; + amo_t amo_op_d, amo_op_q; + + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_n, trans_id_q; + + // output assignments + assign vaddr_o = lsu_ctrl_i.vaddr; // virtual address + assign hs_ld_st_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hs_ld_st_inst : 1'b0; + assign hlvx_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hlvx_inst : 1'b0; + assign tinst_o = CVA6Cfg.RVH ? lsu_ctrl_i.tinst : '0; // transformed instruction + assign trans_id_o = trans_id_q; // transaction id from previous cycle + + always_comb begin : store_control + translation_req_o = 1'b0; + valid_o = 1'b0; + st_valid = 1'b0; + st_valid_without_flush = 1'b0; + pop_st_o = 1'b0; + ex_o = ex_i; + trans_id_n = lsu_ctrl_i.trans_id; + state_d = state_q; + + case (state_q) + // we got a valid store + IDLE: begin + if (valid_i) begin + state_d = VALID_STORE; + translation_req_o = 1'b1; + pop_st_o = 1'b1; + // check if translation was valid and we have space in the store buffer + // otherwise simply stall + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = WAIT_TRANSLATION; + pop_st_o = 1'b0; + end + + if (!st_ready) begin + state_d = WAIT_STORE_READY; + pop_st_o = 1'b0; + end + end + end + + VALID_STORE: begin + valid_o = 1'b1; + // post this store to the store buffer if we are not flushing + if (!flush_i) st_valid = 1'b1; + + st_valid_without_flush = 1'b1; + + // we have another request and its not an AMO (the AMO buffer only has depth 1) + if ((valid_i && CVA6Cfg.RVA && !instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin + + translation_req_o = 1'b1; + state_d = VALID_STORE; + pop_st_o = 1'b1; + + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = WAIT_TRANSLATION; + pop_st_o = 1'b0; + end + + if (!st_ready) begin + state_d = WAIT_STORE_READY; + pop_st_o = 1'b0; + end + // if we do not have another request go back to idle + end else begin + state_d = IDLE; + end + end + + // the store queue is currently full + WAIT_STORE_READY: begin + // keep the translation request high + translation_req_o = 1'b1; + + if (st_ready && dtlb_hit_i) begin + state_d = IDLE; + end + end + + default: begin + // we didn't receive a valid translation, wait for one + // but we know that the store queue is not full as we could only have landed here if + // it wasn't full + if (state_q == WAIT_TRANSLATION && CVA6Cfg.MmuPresent) begin + translation_req_o = 1'b1; + + if (dtlb_hit_i) begin + state_d = IDLE; + end + end + end + endcase + + // ----------------- + // Access Exception + // ----------------- + // we got an address translation exception (access rights, misaligned or page fault) + if (ex_i.valid && (state_q != IDLE)) begin + // the only difference is that we do not want to store this request + pop_st_o = 1'b1; + st_valid = 1'b0; + state_d = IDLE; + valid_o = 1'b1; + end + + if (flush_i) state_d = IDLE; + end + + // ----------- + // Re-aligner + // ----------- + // re-align the write data to comply with the address offset + always_comb begin + st_be_n = lsu_ctrl_i.be; + // don't shift the data if we are going to perform an AMO as we still need to operate on this data + st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[CVA6Cfg.XLEN-1:0] : + data_align(lsu_ctrl_i.vaddr[2:0], {{64 - CVA6Cfg.XLEN{1'b0}}, lsu_ctrl_i.data}); + st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation); + // save AMO op for next cycle + if (CVA6Cfg.RVA) begin + case (lsu_ctrl_i.operation) + AMO_LRW, AMO_LRD: amo_op_d = AMO_LR; + AMO_SCW, AMO_SCD: amo_op_d = AMO_SC; + AMO_SWAPW, AMO_SWAPD: amo_op_d = AMO_SWAP; + AMO_ADDW, AMO_ADDD: amo_op_d = AMO_ADD; + AMO_ANDW, AMO_ANDD: amo_op_d = AMO_AND; + AMO_ORW, AMO_ORD: amo_op_d = AMO_OR; + AMO_XORW, AMO_XORD: amo_op_d = AMO_XOR; + AMO_MAXW, AMO_MAXD: amo_op_d = AMO_MAX; + AMO_MAXWU, AMO_MAXDU: amo_op_d = AMO_MAXU; + AMO_MINW, AMO_MIND: amo_op_d = AMO_MIN; + AMO_MINWU, AMO_MINDU: amo_op_d = AMO_MINU; + default: amo_op_d = AMO_NONE; + endcase + end else begin + amo_op_d = AMO_NONE; + end + end + + logic store_buffer_valid, amo_buffer_valid; + logic store_buffer_ready, amo_buffer_ready; + + // multiplex between store unit and amo buffer + assign store_buffer_valid = st_valid & (!CVA6Cfg.RVA || (amo_op_q == AMO_NONE)); + assign amo_buffer_valid = st_valid & (CVA6Cfg.RVA && (amo_op_q != AMO_NONE)); + + assign st_ready = store_buffer_ready & amo_buffer_ready; + + // --------------- + // Store Queue + // --------------- + store_buffer #( + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t) + ) store_buffer_i ( + .clk_i, + .rst_ni, + .flush_i, + .stall_st_pending_i, + .no_st_pending_o, + .store_buffer_empty_o, + .page_offset_i, + .page_offset_matches_o, + .commit_i, + .commit_ready_o, + .ready_o (store_buffer_ready), + .valid_i (store_buffer_valid), + // the flush signal can be critical and we need this valid + // signal to check whether the page_offset matches or not, + // functionaly it doesn't make a difference whether we use + // the correct valid signal or not as we are flushing + // the whole pipeline anyway + .valid_without_flush_i(st_valid_without_flush), + .paddr_i, + .rvfi_mem_paddr_o (rvfi_mem_paddr_o), + .data_i (st_data_q), + .be_i (st_be_q), + .data_size_i (st_data_size_q), + .req_port_i (req_port_i), + .req_port_o (req_port_o) + ); + + if (CVA6Cfg.RVA) begin + amo_buffer #( + .CVA6Cfg(CVA6Cfg) + ) i_amo_buffer ( + .clk_i, + .rst_ni, + .flush_i, + .valid_i (amo_buffer_valid), + .ready_o (amo_buffer_ready), + .paddr_i (paddr_i), + .amo_op_i (amo_op_q), + .data_i (st_data_q), + .data_size_i (st_data_size_q), + .amo_req_o (amo_req_o), + .amo_resp_i (amo_resp_i), + .amo_valid_commit_i(amo_valid_commit_i), + .no_st_pending_i (no_st_pending_o) + ); + end else begin + assign amo_buffer_ready = '1; + assign amo_req_o = '0; + end + + // --------------- + // Registers + // --------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + st_be_q <= '0; + st_data_q <= '0; + st_data_size_q <= '0; + trans_id_q <= '0; + amo_op_q <= AMO_NONE; + end else begin + state_q <= state_d; + st_be_q <= st_be_n; + st_data_q <= st_data_n; + trans_id_q <= trans_id_n; + st_data_size_q <= st_data_size_n; + amo_op_q <= amo_op_d; + end + end + +endmodule diff --git a/flow/designs/src/cva6/core/zcmt_decoder.sv b/flow/designs/src/cva6/core/zcmt_decoder.sv new file mode 100644 index 0000000000..c37c11fda5 --- /dev/null +++ b/flow/designs/src/cva6/core/zcmt_decoder.sv @@ -0,0 +1,133 @@ +// Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Author: Farhan Ali Shah, 10xEngineers +// Date: 15.11.2024 +// Description: ZCMT extension in the CVA6 core targeting the 32-bit embedded-class platforms (CV32A60x). +// ZCMT is a code-size reduction feature that utilizes compressed table jump instructions (cm.jt and cm.jalt) to +//reduce code size for embedded systems +// +module zcmt_decoder #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type jvt_t = logic, + parameter type branchpredict_sbe_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Instruction input - compressed_decoder + input logic [ 31:0] instr_i, + // current PC - FRONTEND + input logic [CVA6Cfg.VLEN-1:0] pc_i, + // Intruction is of ZCMT extension - compressed_decoder + input logic is_zcmt_instr_i, + // Instruction is illegal - compressed_decoder + input logic illegal_instr_i, + // Instruction is compressed - compressed_decoder + input logic is_compressed_i, + // JVT struct input - CSR + input jvt_t jvt_i, + // Data cache request output - CACHE + input dcache_req_o_t req_port_i, + // Instruction out - cvxif_compressed_if_driver + output logic [ 31:0] instr_o, + // Instruction is illegal out - cvxif_compressed_if_driver + output logic illegal_instr_o, + // Instruction is compressed out - cvxif_compressed_if_driver + output logic is_compressed_o, + // Fetch stall - cvxif_compressed_if_driver + output logic fetch_stall_o, + // Data cache request input - CACHE + output dcache_req_i_t req_port_o, + // jump_address + output logic [CVA6Cfg.XLEN-1:0] jump_address_o +); + + // FSM States + enum logic { + IDLE, // if ZCMT instruction then request sent to fetch the entry from jump table + TABLE_JUMP // Check the valid data from jump table and Calculate the offset for jump and create jal instruction + } + state_d, state_q; + // Temporary registers + // Physical address: jvt + (index <<2) + logic [CVA6Cfg.VLEN-1:0] table_address; + + always_comb begin + state_d = state_q; + illegal_instr_o = 1'b0; + is_compressed_o = is_zcmt_instr_i || is_compressed_i; + fetch_stall_o = '0; + jump_address_o = '0; + + // cache request port + req_port_o.data_wdata = '0; + req_port_o.data_wuser = '0; + req_port_o.data_req = 1'b0; + req_port_o.data_we = 1'b0; + req_port_o.data_be = '0; + req_port_o.data_size = 2'b10; + req_port_o.data_id = 1'b1; + req_port_o.kill_req = 1'b0; + req_port_o.tag_valid = 1'b1; + + unique case (state_q) + IDLE: begin + fetch_stall_o = 1'b0; + if (is_zcmt_instr_i) begin + if (CVA6Cfg.XLEN == 32) begin //It is only target for 32 bit targets in cva6 with No MMU + table_address = {jvt_i.base, 6'b000000} + {24'h0, instr_i[7:2], 2'b00}; + req_port_o.address_index = table_address[9:0]; + req_port_o.address_tag = table_address[CVA6Cfg.VLEN-1:10]; // No MMU support + state_d = TABLE_JUMP; + req_port_o.data_req = 1'b1; + fetch_stall_o = 1'b1; + end else illegal_instr_o = 1'b1; + // Condition may be extented for 64 bits embedded targets with No MMU + end else begin + illegal_instr_o = illegal_instr_i; + instr_o = instr_i; + state_d = IDLE; + end + end + TABLE_JUMP: begin + if (req_port_i.data_rvalid) begin + // save the PC relative Xlen table jump address + jump_address_o = $unsigned($signed(req_port_i.data_rdata) - $signed(pc_i)); + if (instr_i[9:2] < 32) begin // jal pc_offset, x0 for no return stack + instr_o = { + 20'h0, 5'h0, riscv::OpcodeJal + }; // immidiate assigned here (0) will be overwrite in decode stage with jump_address_o + end else if ((instr_i[9:2] >= 32) & (instr_i[9:2] <= 255)) begin //- jal pc_offset, x1 for return stack + instr_o = { + 20'h0, 5'h1, riscv::OpcodeJal + }; // immidiate assigned here (0) will be overwrite in decode stage with jump_address_o + end else begin + illegal_instr_o = 1'b1; + instr_o = instr_i; + end + state_d = IDLE; + end else begin + state_d = TABLE_JUMP; + end + end + default: begin + state_d = IDLE; + end + endcase + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= IDLE; + + end else begin + state_q <= state_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv new file mode 100644 index 0000000000..92ede558c1 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv @@ -0,0 +1,423 @@ +// Copyright (c) 2014-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Andreas Kurth +// - Florian Zaruba +// - Wolfgang Roenninger +// - Fabian Schuiki +// - Matheus Cavalcante + +//! AXI Package +/// Contains all necessary type definitions, constants, and generally useful functions. +package axi_pkg; + /// AXI Transaction Burst Type. + typedef logic [1:0] burst_t; + /// AXI Transaction Response Type. + typedef logic [1:0] resp_t; + /// AXI Transaction Cacheability Type. + typedef logic [3:0] cache_t; + /// AXI Transaction Protection Type. + typedef logic [2:0] prot_t; + /// AXI Transaction Quality of Service Type. + typedef logic [3:0] qos_t; + /// AXI Transaction Region Type. + typedef logic [3:0] region_t; + /// AXI Transaction Length Type. + typedef logic [7:0] len_t; + /// AXI Transaction Size Type. + typedef logic [2:0] size_t; + /// AXI5 Atomic Operation Type. + typedef logic [5:0] atop_t; // atomic operations + /// AXI5 Non-Secure Address Identifier. + typedef logic [3:0] nsaid_t; + + /// In a fixed burst: + /// - The address is the same for every transfer in the burst. + /// - The byte lanes that are valid are constant for all beats in the burst. However, within + /// those byte lanes, the actual bytes that have `wstrb` asserted can differ for each beat in + /// the burst. + /// This burst type is used for repeated accesses to the same location such as when loading or + /// emptying a FIFO. + localparam BURST_FIXED = 2'b00; + /// In an incrementing burst, the address for each transfer in the burst is an increment of the + /// address for the previous transfer. The increment value depends on the size of the transfer. + /// For example, the address for each transfer in a burst with a size of 4 bytes is the previous + /// address plus four. + /// This burst type is used for accesses to normal sequential memory. + localparam BURST_INCR = 2'b01; + /// A wrapping burst is similar to an incrementing burst, except that the address wraps around to + /// a lower address if an upper address limit is reached. + /// The following restrictions apply to wrapping bursts: + /// - The start address must be aligned to the size of each transfer. + /// - The length of the burst must be 2, 4, 8, or 16 transfers. + localparam BURST_WRAP = 2'b10; + + /// Normal access success. Indicates that a normal access has been successful. Can also indicate + /// that an exclusive access has failed. + localparam RESP_OKAY = 2'b00; + /// Exclusive access okay. Indicates that either the read or write portion of an exclusive access + /// has been successful. + localparam RESP_EXOKAY = 2'b01; + /// Slave error. Used when the access has reached the slave successfully, but the slave wishes to + /// return an error condition to the originating master. + localparam RESP_SLVERR = 2'b10; + /// Decode error. Generated, typically by an interconnect component, to indicate that there is no + /// slave at the transaction address. + localparam RESP_DECERR = 2'b11; + + /// When this bit is asserted, the interconnect, or any component, can delay the transaction + /// reaching its final destination for any number of cycles. + localparam CACHE_BUFFERABLE = 4'b0001; + /// When HIGH, Modifiable indicates that the characteristics of the transaction can be modified. + /// When Modifiable is LOW, the transaction is Non-modifiable. + localparam CACHE_MODIFIABLE = 4'b0010; + /// When this bit is asserted, read allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_RD_ALLOC = 4'b0100; + /// When this bit is asserted, write allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_WR_ALLOC = 4'b1000; + + /// Maximum number of bytes per burst, as specified by `size` (see Table A3-2). + function automatic shortint unsigned num_bytes(size_t size); + return 1 << size; + endfunction + + /// An overly long address type. + /// It lets us define functions that work generically for shorter addresses. We rely on the + /// synthesizer to optimize the unused bits away. + typedef logic [127:0] largest_addr_t; + + /// Aligned address of burst (see A3-51). + function automatic largest_addr_t aligned_addr(largest_addr_t addr, size_t size); + return (addr >> size) << size; + endfunction + + /// Warp boundary of a `BURST_WRAP` transfer (see A3-51). + /// This is the lowest address accessed within a wrapping burst. + /// This address is aligned to the size and length of the burst. + /// The length of a `BURST_WRAP` has to be 2, 4, 8, or 16 transfers. + function automatic largest_addr_t wrap_boundary (largest_addr_t addr, size_t size, len_t len); + largest_addr_t wrap_addr; + + // pragma translate_off + `ifndef VERILATOR + assume (len == len_t'(4'b1) || len == len_t'(4'b11) || len == len_t'(4'b111) || + len == len_t'(4'b1111)) else + $error("AXI BURST_WRAP with not allowed len of: %0h", len); + `endif + // pragma translate_on + + // In A3-51 the wrap boundary is defined as: + // `Wrap_Boundary = (INT(Start_Address / (Number_Bytes × Burst_Length))) × + // (Number_Bytes × Burst_Length)` + // Whereas the aligned address is defined as: + // `Aligned_Address = (INT(Start_Address / Number_Bytes)) × Number_Bytes` + // This leads to the wrap boundary using the same calculation as the aligned address, difference + // being the additional dependency on the burst length. The addition in the case statement + // is equal to the multiplication with `Burst_Length` as a shift (used by `aligned_addr`) is + // equivalent with multiplication and division by a power of two, which conveniently are the + // only allowed values for `len` of a `BURST_WRAP`. + unique case (len) + 4'b1 : wrap_addr = (addr >> (unsigned'(size) + 1)) << (unsigned'(size) + 1); // multiply `Number_Bytes` by `2` + 4'b11 : wrap_addr = (addr >> (unsigned'(size) + 2)) << (unsigned'(size) + 2); // multiply `Number_Bytes` by `4` + 4'b111 : wrap_addr = (addr >> (unsigned'(size) + 3)) << (unsigned'(size) + 3); // multiply `Number_Bytes` by `8` + 4'b1111 : wrap_addr = (addr >> (unsigned'(size) + 4)) << (unsigned'(size) + 4); // multiply `Number_Bytes` by `16` + default : wrap_addr = '0; + endcase + return wrap_addr; + endfunction + + /// Address of beat (see A3-51). + function automatic largest_addr_t + beat_addr(largest_addr_t addr, size_t size, len_t len, burst_t burst, shortint unsigned i_beat); + largest_addr_t ret_addr = addr; + largest_addr_t wrp_bond = '0; + if (burst == BURST_WRAP) begin + // do not trigger the function if there is no wrapping burst, to prevent assumptions firing + wrp_bond = wrap_boundary(addr, size, len); + end + if (i_beat != 0 && burst != BURST_FIXED) begin + // From A3-51: + // For an INCR burst, and for a WRAP burst for which the address has not wrapped, this + // equation determines the address of any transfer after the first transfer in a burst: + // `Address_N = Aligned_Address + (N – 1) × Number_Bytes` (N counts from 1 to len!) + ret_addr = aligned_addr(addr, size) + i_beat * num_bytes(size); + // From A3-51: + // For a WRAP burst, if Address_N = Wrap_Boundary + (Number_Bytes × Burst_Length), then: + // * Use this equation for the current transfer: + // `Address_N = Wrap_Boundary` + // * Use this equation for any subsequent transfers: + // `Address_N = Start_Address + ((N – 1) × Number_Bytes) – (Number_Bytes × Burst_Length)` + // This means that the address calculation of a `BURST_WRAP` fundamentally works the same + // as for a `BURST_INC`, the difference is when the calculated address increments + // over the wrap threshold, the address wraps around by subtracting the accessed address + // space from the normal `BURST_INCR` address. The lower wrap boundary is equivalent to + // The wrap trigger condition minus the container size (`num_bytes(size) * (len + 1)`). + if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin + ret_addr = ret_addr - (num_bytes(size) * (len + 1)); + end + end + return ret_addr; + endfunction + + /// Index of lowest byte in beat (see A3-51). + function automatic shortint unsigned + beat_lower_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst, + shortint unsigned strobe_width, shortint unsigned i_beat); + largest_addr_t _addr = beat_addr(addr, size, len, burst, i_beat); + return _addr - (_addr / strobe_width) * strobe_width; + endfunction + + /// Index of highest byte in beat (see A3-51). + function automatic shortint unsigned + beat_upper_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst, + shortint unsigned strobe_width, shortint unsigned i_beat); + if (i_beat == 0) begin + return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width; + end else begin + return beat_lower_byte(addr, size, len, burst, strobe_width, i_beat) + num_bytes(size) - 1; + end + endfunction + + /// Is the bufferable bit set? + function automatic logic bufferable(cache_t cache); + return |(cache & CACHE_BUFFERABLE); + endfunction + + /// Is the modifiable bit set? + function automatic logic modifiable(cache_t cache); + return |(cache & CACHE_MODIFIABLE); + endfunction + + /// Memory Type. + typedef enum logic [3:0] { + DEVICE_NONBUFFERABLE, + DEVICE_BUFFERABLE, + NORMAL_NONCACHEABLE_NONBUFFERABLE, + NORMAL_NONCACHEABLE_BUFFERABLE, + WTHRU_NOALLOCATE, + WTHRU_RALLOCATE, + WTHRU_WALLOCATE, + WTHRU_RWALLOCATE, + WBACK_NOALLOCATE, + WBACK_RALLOCATE, + WBACK_WALLOCATE, + WBACK_RWALLOCATE + } mem_type_t; + + /// Create an `AR_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_arcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b1010; + WTHRU_RALLOCATE : return 4'b1110; + WTHRU_WALLOCATE : return 4'b1010; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b1011; + WBACK_RALLOCATE : return 4'b1111; + WBACK_WALLOCATE : return 4'b1011; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + /// Create an `AW_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_awcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b0110; + WTHRU_RALLOCATE : return 4'b0110; + WTHRU_WALLOCATE : return 4'b1110; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b0111; + WBACK_RALLOCATE : return 4'b0111; + WBACK_WALLOCATE : return 4'b1111; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + /// RESP precedence: DECERR > SLVERR > OKAY > EXOKAY. This is not defined in the AXI standard but + /// depends on the implementation. We consistently use the precedence above. Rationale: + /// - EXOKAY means an exclusive access was successful, whereas OKAY means it was not. Thus, if + /// OKAY and EXOKAY are to be merged, OKAY precedes because the exclusive access was not fully + /// successful. + /// - Both DECERR and SLVERR mean (part of) a transaction were unsuccessful, whereas OKAY means an + /// entire transaction was successful. Thus both DECERR and SLVERR precede OKAY. + /// - DECERR means (part of) a transactions could not be routed to a slave component, whereas + /// SLVERR means the transaction reached a slave component but lead to an error condition there. + /// Thus DECERR precedes SLVERR because DECERR happens earlier in the handling of a transaction. + function automatic resp_t resp_precedence(resp_t resp_a, resp_t resp_b); + unique case (resp_a) + RESP_OKAY: begin + // Any response except EXOKAY precedes OKAY. + if (resp_b == RESP_EXOKAY) begin + return resp_a; + end else begin + return resp_b; + end + end + RESP_EXOKAY: begin + // Any response precedes EXOKAY. + return resp_b; + end + RESP_SLVERR: begin + // Only DECERR precedes SLVERR. + if (resp_b == RESP_DECERR) begin + return resp_b; + end else begin + return resp_a; + end + end + RESP_DECERR: begin + // No response precedes DECERR. + return resp_a; + end + endcase + endfunction + + // ATOP[5:0] + /// - Sends a single data value with an address. + /// - The target swaps the value at the addressed location with the data value that is supplied in + /// the transaction. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICSWAP = 6'b110000; + /// - Sends two data values, the compare value and the swap value, to the addressed location. + /// The compare and swap values are of equal size. + /// - The data value at the addressed location is checked against the compare value: + /// - If the values match, the swap value is written to the addressed location. + /// - If the values do not match, the swap value is not written to the addressed location. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 2, 4, 8, 16, or 32 bytes. + /// - Inbound data size is half of the outbound data size because the outbound data contains both + /// compare and swap values, whereas the inbound data has only the original data value. + localparam ATOP_ATOMICCMP = 6'b110001; + // ATOP[5:4] + /// Perform no atomic operation. + localparam ATOP_NONE = 2'b00; + /// - Sends a single data value with an address and the atomic operation to be performed. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - A single response is given without data. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + localparam ATOP_ATOMICSTORE = 2'b01; + /// Sends a single data value with an address and the atomic operation to be performed. + /// - The original data value at the addressed location is returned. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICLOAD = 2'b10; + // ATOP[3] + /// For AtomicStore and AtomicLoad transactions `AWATOP[3]` indicates the endianness that is + /// required for the atomic operation. The value of `AWATOP[3]` applies to arithmetic operations + /// only and is ignored for bitwise logical operations. + /// When deasserted, this bit indicates that the operation is little-endian. + localparam ATOP_LITTLE_END = 1'b0; + /// When asserted, this bit indicates that the operation is big-endian. + localparam ATOP_BIG_END = 1'b1; + // ATOP[2:0] + /// The value in memory is added to the sent data and the result stored in memory. + localparam ATOP_ADD = 3'b000; + /// Every set bit in the sent data clears the corresponding bit of the data in memory. + localparam ATOP_CLR = 3'b001; + /// Bitwise exclusive OR of the sent data and value in memory. + localparam ATOP_EOR = 3'b010; + /// Every set bit in the sent data sets the corresponding bit of the data in memory. + localparam ATOP_SET = 3'b011; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMAX = 3'b100; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMIN = 3'b101; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMAX = 3'b110; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMIN = 3'b111; + // ATOP[5] == 1'b1 indicated that an atomic transaction has a read response + // Ussage eg: if (req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + localparam ATOP_R_RESP = 32'd5; + + // `xbar_latency_e` and `xbar_cfg_t` are documented in `doc/axi_xbar.md`. + /// Slice on Demux AW channel. + localparam logic [9:0] DemuxAw = (1 << 9); + /// Slice on Demux W channel. + localparam logic [9:0] DemuxW = (1 << 8); + /// Slice on Demux B channel. + localparam logic [9:0] DemuxB = (1 << 7); + /// Slice on Demux AR channel. + localparam logic [9:0] DemuxAr = (1 << 6); + /// Slice on Demux R channel. + localparam logic [9:0] DemuxR = (1 << 5); + /// Slice on Mux AW channel. + localparam logic [9:0] MuxAw = (1 << 4); + /// Slice on Mux W channel. + localparam logic [9:0] MuxW = (1 << 3); + /// Slice on Mux B channel. + localparam logic [9:0] MuxB = (1 << 2); + /// Slice on Mux AR channel. + localparam logic [9:0] MuxAr = (1 << 1); + /// Slice on Mux R channel. + localparam logic [9:0] MuxR = (1 << 0); + /// Latency configuration for `axi_xbar`. + typedef enum logic [9:0] { + NO_LATENCY = 10'b000_00_000_00, + CUT_SLV_AX = DemuxAw | DemuxAr, + CUT_MST_AX = MuxAw | MuxAr, + CUT_ALL_AX = DemuxAw | DemuxAr | MuxAw | MuxAr, + CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR, + CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR, + CUT_ALL_PORTS = 10'b111_11_111_11 + } xbar_latency_e; + + /// Configuration for `axi_xbar`. + typedef struct packed { + int unsigned NoSlvPorts; + int unsigned NoMstPorts; + int unsigned MaxMstTrans; + int unsigned MaxSlvTrans; + bit FallThrough; + xbar_latency_e LatencyMode; + int unsigned AxiIdWidthSlvPorts; + int unsigned AxiIdUsedSlvPorts; + bit UniqueIds; + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned NoAddrRules; + } xbar_cfg_t; + + /// Commonly used rule types for `axi_xbar` (64-bit addresses). + typedef struct packed { + int unsigned idx; + logic [63:0] start_addr; + logic [63:0] end_addr; + } xbar_rule_64_t; + + /// Commonly used rule types for `axi_xbar` (32-bit addresses). + typedef struct packed { + int unsigned idx; + logic [31:0] start_addr; + logic [31:0] end_addr; + } xbar_rule_32_t; +endpackage diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv new file mode 100644 index 0000000000..9f35a44e98 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv @@ -0,0 +1,61 @@ +// Copyright 2016 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// cf_math_pkg: Constant Function Implementations of Mathematical Functions for HDL Elaboration +/// +/// This package contains a collection of mathematical functions that are commonly used when defining +/// the value of constants in HDL code. These functions are implemented as Verilog constants +/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (§ 10.3.5) is a +/// function whose value can be evaluated at compile time or during elaboration. A constant function +/// must be called with arguments that are constants. +package cf_math_pkg; + + /// Ceiled Division of Two Natural Numbers + /// + /// Returns the quotient of two natural numbers, rounded towards plus infinity. + function automatic integer ceil_div (input longint dividend, input longint divisor); + automatic longint remainder; + + // pragma translate_off + `ifndef VERILATOR + if (dividend < 0) begin + $fatal(1, "Dividend %0d is not a natural number!", dividend); + end + + if (divisor < 0) begin + $fatal(1, "Divisor %0d is not a natural number!", divisor); + end + + if (divisor == 0) begin + $fatal(1, "Division by zero!"); + end + `endif + // pragma translate_on + + remainder = dividend; + for (ceil_div = 0; remainder > 0; ceil_div++) begin + remainder = remainder - divisor; + end + endfunction + + /// Index width required to be able to represent up to `num_idx` indices as a binary + /// encoded signal. + /// Ensures that the minimum width if an index signal is `1`, regardless of parametrization. + /// + /// Sample usage in type definition: + /// As parameter: + /// `parameter type idx_t = logic[cf_math_pkg::idx_width(NumIdx)-1:0]` + /// As typedef: + /// `typedef logic [cf_math_pkg::idx_width(NumIdx)-1:0] idx_t` + function automatic integer unsigned idx_width (input integer unsigned num_idx); + return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; + endfunction + +endpackage diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/counter.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/counter.sv new file mode 100644 index 0000000000..43392e4bfd --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/counter.sv @@ -0,0 +1,43 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba +// Description: Generic up/down counter + +module counter #( + parameter int unsigned WIDTH = 4, + parameter bit STICKY_OVERFLOW = 1'b0 +)( + input logic clk_i, + input logic rst_ni, + input logic clear_i, // synchronous clear + input logic en_i, // enable the counter + input logic load_i, // load a new value + input logic down_i, // downcount, default is up + input logic [WIDTH-1:0] d_i, + output logic [WIDTH-1:0] q_o, + output logic overflow_o +); + delta_counter #( + .WIDTH (WIDTH), + .STICKY_OVERFLOW (STICKY_OVERFLOW) + ) i_counter ( + .clk_i, + .rst_ni, + .clear_i, + .en_i, + .load_i, + .down_i, + .delta_i({{WIDTH-1{1'b0}}, 1'b1}), + .d_i, + .q_o, + .overflow_o + ); +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv new file mode 100644 index 0000000000..90b5cffa9a --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv @@ -0,0 +1,74 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Up/down counter with variable delta + +module delta_counter #( + parameter int unsigned WIDTH = 4, + parameter bit STICKY_OVERFLOW = 1'b0 +)( + input logic clk_i, + input logic rst_ni, + input logic clear_i, // synchronous clear + input logic en_i, // enable the counter + input logic load_i, // load a new value + input logic down_i, // downcount, default is up + input logic [WIDTH-1:0] delta_i, + input logic [WIDTH-1:0] d_i, + output logic [WIDTH-1:0] q_o, + output logic overflow_o +); + logic [WIDTH:0] counter_q, counter_d; + if (STICKY_OVERFLOW) begin : gen_sticky_overflow + logic overflow_d, overflow_q; + always_ff @(posedge clk_i or negedge rst_ni) overflow_q <= ~rst_ni ? 1'b0 : overflow_d; + always_comb begin + overflow_d = overflow_q; + if (clear_i || load_i) begin + overflow_d = 1'b0; + end else if (!overflow_q && en_i) begin + if (down_i) begin + overflow_d = delta_i > counter_q[WIDTH-1:0]; + end else begin + overflow_d = counter_q[WIDTH-1:0] > ({WIDTH{1'b1}} - delta_i); + end + end + end + assign overflow_o = overflow_q; + end else begin : gen_transient_overflow + // counter overflowed if the MSB is set + assign overflow_o = counter_q[WIDTH]; + end + assign q_o = counter_q[WIDTH-1:0]; + + always_comb begin + counter_d = counter_q; + + if (clear_i) begin + counter_d = '0; + end else if (load_i) begin + counter_d = {1'b0, d_i}; + end else if (en_i) begin + if (down_i) begin + counter_d = counter_q - delta_i; + end else begin + counter_d = counter_q + delta_i; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + counter_q <= '0; + end else begin + counter_q <= counter_d; + end + end +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv new file mode 100644 index 0000000000..91dccb075c --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv @@ -0,0 +1,98 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 10.04.2019 +// Description: exponential backoff counter with randomization. +// +// For each failed trial (set_i pulsed), this unit exponentially increases the +// (average) backoff time by masking an LFSR with a shifted mask in order to +// create the backoff counter initial value. +// +// The shift register mask and the counter value are both reset to '0 in case of +// a successful trial (clr_i). +// + +module exp_backoff #( + /// Seed for 16bit LFSR + parameter int unsigned Seed = 'hffff, + /// 2**MaxExp-1 determines the maximum range from which random wait counts are drawn + parameter int unsigned MaxExp = 16 +) ( + input logic clk_i, + input logic rst_ni, + /// Sets the backoff counter (pulse) -> use when trial did not succeed + input logic set_i, + /// Clears the backoff counter (pulse) -> use when trial succeeded + input logic clr_i, + /// Indicates whether the backoff counter is equal to zero and a new trial can be launched + output logic is_zero_o +); + + // leave this constant + localparam int unsigned WIDTH = 16; + + logic [WIDTH-1:0] lfsr_d, lfsr_q, cnt_d, cnt_q, mask_d, mask_q; + logic lfsr; + + // generate random wait counts + // note: we use a flipped lfsr here to + // avoid strange correlation effects between + // the (left-shifted) mask and the lfsr + assign lfsr = lfsr_q[15-15] ^ + lfsr_q[15-13] ^ + lfsr_q[15-12] ^ + lfsr_q[15-10]; + + assign lfsr_d = (set_i) ? {lfsr, lfsr_q[$high(lfsr_q):1]} : + lfsr_q; + + // mask the wait counts with exponentially increasing mask (shift reg) + assign mask_d = (clr_i) ? '0 : + (set_i) ? {{(WIDTH-MaxExp){1'b0}},mask_q[MaxExp-2:0], 1'b1} : + mask_q; + + assign cnt_d = (clr_i) ? '0 : + (set_i) ? (mask_q & lfsr_q) : + (!is_zero_o) ? cnt_q - 1'b1 : '0; + + assign is_zero_o = (cnt_q=='0); + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + lfsr_q <= WIDTH'(Seed); + mask_q <= '0; + cnt_q <= '0; + end else begin + lfsr_q <= lfsr_d; + mask_q <= mask_d; + cnt_q <= cnt_d; + end + end + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + initial begin + // assert wrong parameterizations + assert (MaxExp>0) + else $fatal(1,"MaxExp must be greater than 0"); + assert (MaxExp<=16) + else $fatal(1,"MaxExp cannot be greater than 16"); + assert (Seed>0) + else $fatal(1,"Zero seed is not allowed for LFSR"); + end +`endif +//pragma translate_on + +endmodule // exp_backoff diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv new file mode 100644 index 0000000000..a1b6118083 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv @@ -0,0 +1,156 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +module fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter type dtype = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + // local parameter + // FIFO depth - handle the case of pass-through, synthesizer will do constant propagation + localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1; + // clock gating control + logic gate_clock; + // pointer to the read and write section of the queue + logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q; + // keep a counter to keep track of the current queue status + // this integer will be truncated by the synthesis tool + logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q; + // actual memory + dtype [FifoDepth - 1:0] mem_n, mem_q; + + assign usage_o = status_cnt_q[ADDR_DEPTH-1:0]; + + if (DEPTH == 0) begin : gen_pass_through + assign empty_o = ~push_i; + assign full_o = ~pop_i; + end else begin : gen_fifo + assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]); + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + // status flags + + // read and write queue logic + always_comb begin : read_write_comb + // default assignment + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + status_cnt_n = status_cnt_q; + data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; + mem_n = mem_q; + gate_clock = 1'b1; + + // push a new element to the queue + if (push_i && ~full_o) begin + // push the data onto the queue + mem_n[write_pointer_q] = data_i; + // un-gate the clock, we want to write something + gate_clock = 1'b0; + // increment the write counter + // this is dead code when DEPTH is a power of two + if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1) + write_pointer_n = '0; + else + write_pointer_n = write_pointer_q + 1; + // increment the overall counter + status_cnt_n = status_cnt_q + 1; + end + + if (pop_i && ~empty_o) begin + // read from the queue is a default assignment + // but increment the read pointer... + // this is dead code when DEPTH is a power of two + if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) + read_pointer_n = '0; + else + read_pointer_n = read_pointer_q + 1; + // ... and decrement the overall count + status_cnt_n = status_cnt_q - 1; + end + + // keep the count pointer stable if we push and pop at the same time + if (push_i && pop_i && ~full_o && ~empty_o) + status_cnt_n = status_cnt_q; + + // FIFO is in pass through mode -> do not change the pointers + if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin + data_o = data_i; + if (pop_i) begin + status_cnt_n = status_cnt_q; + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + end + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + if (flush_i) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + read_pointer_q <= read_pointer_n; + write_pointer_q <= write_pointer_n; + status_cnt_q <= status_cnt_n; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + mem_q <= '0; + end else if (!gate_clock) begin + mem_q <= mem_n; + end + end + +`ifndef SYNTHESIS +`ifndef COMMON_CELLS_ASSERTS_OFF + initial begin + assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); + end + + full_write : assert property( + @(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i)) + else $fatal (1, "Trying to push new data although the FIFO is full."); + + empty_read : assert property( + @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) + else $fatal (1, "Trying to pop data although the FIFO is empty."); +`endif +`endif + +endmodule // fifo_v3 diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv new file mode 100644 index 0000000000..aae2e2df83 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv @@ -0,0 +1,315 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 26.04.2019 +// +// Description: This is a parametric LFSR with precomputed coefficients for +// LFSR lengths from 4 to 64bit. + +// Additional block cipher layers can be instantiated to non-linearly transform +// the pseudo-random LFSR sequence at the output, and hence break the shifting +// patterns. The additional cipher layers can only be used for an LFSR width +// of 64bit, since the block cipher has been designed for that block length. + +module lfsr #( + parameter int unsigned LfsrWidth = 64, // [4,64] + parameter int unsigned OutWidth = 8, // [1,LfsrWidth] + parameter logic [LfsrWidth-1:0] RstVal = '1, // [1,2^LfsrWidth-1] + // 0: disabled, the present cipher uses 31, but just a few layers (1-3) are enough + // to break linear shifting patterns + parameter int unsigned CipherLayers = 0, + parameter bit CipherReg = 1'b1 // additional output reg after cipher +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + output logic [OutWidth-1:0] out_o +); + +// Galois LFSR feedback masks +// Automatically generated with get_lfsr_masks.py +// Masks are from https://users.ece.cmu.edu/~koopman/lfsr/ +localparam logic [63:0] Masks [4:64] = '{64'hC, + 64'h1E, + 64'h39, + 64'h7E, + 64'hFA, + 64'h1FD, + 64'h3FC, + 64'h64B, + 64'hD8F, + 64'h1296, + 64'h2496, + 64'h4357, + 64'h8679, + 64'h1030E, + 64'h206CD, + 64'h403FE, + 64'h807B8, + 64'h1004B2, + 64'h2006A8, + 64'h4004B2, + 64'h800B87, + 64'h10004F3, + 64'h200072D, + 64'h40006AE, + 64'h80009E3, + 64'h10000583, + 64'h20000C92, + 64'h400005B6, + 64'h80000EA6, + 64'h1000007A3, + 64'h200000ABF, + 64'h400000842, + 64'h80000123E, + 64'h100000074E, + 64'h2000000AE9, + 64'h400000086A, + 64'h8000001213, + 64'h1000000077E, + 64'h2000000123B, + 64'h40000000877, + 64'h8000000108D, + 64'h100000000AE9, + 64'h200000000E9F, + 64'h4000000008A6, + 64'h80000000191E, + 64'h100000000090E, + 64'h2000000000FB3, + 64'h4000000000D7D, + 64'h80000000016A5, + 64'h10000000000B4B, + 64'h200000000010AF, + 64'h40000000000DDE, + 64'h8000000000181A, + 64'h100000000000B65, + 64'h20000000000102D, + 64'h400000000000CD5, + 64'h8000000000024C1, + 64'h1000000000000EF6, + 64'h2000000000001363, + 64'h4000000000000FCD, + 64'h80000000000019E2}; + +// this S-box and permutation P has been taken from the Present Cipher, +// a super lightweight block cipher. use the cipher layers to add additional +// non-linearity to the LFSR output. note one layer does not fully correspond +// to the present cipher round, since the key and rekeying function is not applied here. +// +// See also: +// "PRESENT: An Ultra-Lightweight Block Cipher", A. Bogdanov et al., Ches 2007 +// http://www.lightweightcrypto.org/present/present_ches2007.pdf + +// this is the sbox from the present cipher +localparam logic[15:0][3:0] Sbox4 = {4'h2, 4'h1, 4'h7, 4'h4, + 4'h8, 4'hF, 4'hE, 4'h3, + 4'hD, 4'hA, 4'h0, 4'h9, + 4'hB, 4'h6, 4'h5, 4'hC }; + +// these are the permutation indices of the present cipher +localparam logic[63:0][5:0] Perm = {6'd63, 6'd47, 6'd31, 6'd15, 6'd62, 6'd46, 6'd30, 6'd14, + 6'd61, 6'd45, 6'd29, 6'd13, 6'd60, 6'd44, 6'd28, 6'd12, + 6'd59, 6'd43, 6'd27, 6'd11, 6'd58, 6'd42, 6'd26, 6'd10, + 6'd57, 6'd41, 6'd25, 6'd09, 6'd56, 6'd40, 6'd24, 6'd08, + 6'd55, 6'd39, 6'd23, 6'd07, 6'd54, 6'd38, 6'd22, 6'd06, + 6'd53, 6'd37, 6'd21, 6'd05, 6'd52, 6'd36, 6'd20, 6'd04, + 6'd51, 6'd35, 6'd19, 6'd03, 6'd50, 6'd34, 6'd18, 6'd02, + 6'd49, 6'd33, 6'd17, 6'd01, 6'd48, 6'd32, 6'd16, 6'd00}; + + +function automatic logic [63:0] sbox4_layer(logic [63:0] in); + logic [63:0] out; + //for (logic [4:0] j = '0; j<16; j++) out[j*4 +: 4] = sbox4[in[j*4 +: 4]]; + // this simulates much faster than the loop + out[0*4 +: 4] = Sbox4[in[0*4 +: 4]]; + out[1*4 +: 4] = Sbox4[in[1*4 +: 4]]; + out[2*4 +: 4] = Sbox4[in[2*4 +: 4]]; + out[3*4 +: 4] = Sbox4[in[3*4 +: 4]]; + + out[4*4 +: 4] = Sbox4[in[4*4 +: 4]]; + out[5*4 +: 4] = Sbox4[in[5*4 +: 4]]; + out[6*4 +: 4] = Sbox4[in[6*4 +: 4]]; + out[7*4 +: 4] = Sbox4[in[7*4 +: 4]]; + + out[8*4 +: 4] = Sbox4[in[8*4 +: 4]]; + out[9*4 +: 4] = Sbox4[in[9*4 +: 4]]; + out[10*4 +: 4] = Sbox4[in[10*4 +: 4]]; + out[11*4 +: 4] = Sbox4[in[11*4 +: 4]]; + + out[12*4 +: 4] = Sbox4[in[12*4 +: 4]]; + out[13*4 +: 4] = Sbox4[in[13*4 +: 4]]; + out[14*4 +: 4] = Sbox4[in[14*4 +: 4]]; + out[15*4 +: 4] = Sbox4[in[15*4 +: 4]]; + return out; +endfunction : sbox4_layer + +function automatic logic [63:0] perm_layer(logic [63:0] in); + logic [63:0] out; + // for (logic [7:0] j = '0; j<64; j++) out[perm[j]] = in[j]; + // this simulates much faster than the loop + out[Perm[0]] = in[0]; + out[Perm[1]] = in[1]; + out[Perm[2]] = in[2]; + out[Perm[3]] = in[3]; + out[Perm[4]] = in[4]; + out[Perm[5]] = in[5]; + out[Perm[6]] = in[6]; + out[Perm[7]] = in[7]; + out[Perm[8]] = in[8]; + out[Perm[9]] = in[9]; + + out[Perm[10]] = in[10]; + out[Perm[11]] = in[11]; + out[Perm[12]] = in[12]; + out[Perm[13]] = in[13]; + out[Perm[14]] = in[14]; + out[Perm[15]] = in[15]; + out[Perm[16]] = in[16]; + out[Perm[17]] = in[17]; + out[Perm[18]] = in[18]; + out[Perm[19]] = in[19]; + + out[Perm[20]] = in[20]; + out[Perm[21]] = in[21]; + out[Perm[22]] = in[22]; + out[Perm[23]] = in[23]; + out[Perm[24]] = in[24]; + out[Perm[25]] = in[25]; + out[Perm[26]] = in[26]; + out[Perm[27]] = in[27]; + out[Perm[28]] = in[28]; + out[Perm[29]] = in[29]; + + out[Perm[30]] = in[30]; + out[Perm[31]] = in[31]; + out[Perm[32]] = in[32]; + out[Perm[33]] = in[33]; + out[Perm[34]] = in[34]; + out[Perm[35]] = in[35]; + out[Perm[36]] = in[36]; + out[Perm[37]] = in[37]; + out[Perm[38]] = in[38]; + out[Perm[39]] = in[39]; + + out[Perm[40]] = in[40]; + out[Perm[41]] = in[41]; + out[Perm[42]] = in[42]; + out[Perm[43]] = in[43]; + out[Perm[44]] = in[44]; + out[Perm[45]] = in[45]; + out[Perm[46]] = in[46]; + out[Perm[47]] = in[47]; + out[Perm[48]] = in[48]; + out[Perm[49]] = in[49]; + + out[Perm[50]] = in[50]; + out[Perm[51]] = in[51]; + out[Perm[52]] = in[52]; + out[Perm[53]] = in[53]; + out[Perm[54]] = in[54]; + out[Perm[55]] = in[55]; + out[Perm[56]] = in[56]; + out[Perm[57]] = in[57]; + out[Perm[58]] = in[58]; + out[Perm[59]] = in[59]; + + out[Perm[60]] = in[60]; + out[Perm[61]] = in[61]; + out[Perm[62]] = in[62]; + out[Perm[63]] = in[63]; + return out; +endfunction : perm_layer + +//////////////////////////////////////////////////////////////////////// +// lfsr +//////////////////////////////////////////////////////////////////////// + +logic [LfsrWidth-1:0] lfsr_d, lfsr_q; +assign lfsr_d = + (en_i) ? (lfsr_q>>1) ^ ({LfsrWidth{lfsr_q[0]}} & Masks[LfsrWidth][LfsrWidth-1:0]) : lfsr_q; + +always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + //$display("%b %h", en_i, lfsr_d); + if (!rst_ni) begin + lfsr_q <= LfsrWidth'(RstVal); + end else begin + lfsr_q <= lfsr_d; + end +end + +//////////////////////////////////////////////////////////////////////// +// block cipher layers +//////////////////////////////////////////////////////////////////////// + +if (CipherLayers > unsigned'(0)) begin : g_cipher_layers + logic [63:0] ciph_layer; + localparam int unsigned NumRepl = ((64+LfsrWidth)/LfsrWidth); + + always_comb begin : p_ciph_layer + automatic logic [63:0] tmp; + tmp = 64'({NumRepl{lfsr_q}}); + for(int unsigned k = 0; k < CipherLayers; k++) begin + tmp = perm_layer(sbox4_layer(tmp)); + end + ciph_layer = tmp; + end + + // additiona output reg after cipher + if (CipherReg) begin : g_cipher_reg + logic [OutWidth-1:0] out_d, out_q; + + assign out_d = (en_i) ? ciph_layer[OutWidth-1:0] : out_q; + assign out_o = out_q[OutWidth-1:0]; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + out_q <= '0; + end else begin + out_q <= out_d; + end + end + // no outreg + end else begin : g_no_out_reg + assign out_o = ciph_layer[OutWidth-1:0]; + end + +// no block cipher +end else begin : g_no_cipher_layers + assign out_o = lfsr_q[OutWidth-1:0]; +end + +//////////////////////////////////////////////////////////////////////// +// assertions +//////////////////////////////////////////////////////////////////////// + +// pragma translate_off +initial begin + // these are the LUT limits + assert(OutWidth <= LfsrWidth) else + $fatal(1,"OutWidth must be smaller equal the LfsrWidth."); + assert(RstVal > unsigned'(0)) else + $fatal(1,"RstVal must be nonzero."); + assert((LfsrWidth >= $low(Masks)) && (LfsrWidth <= $high(Masks))) else + $fatal(1,"Unsupported LfsrWidth."); + assert(Masks[LfsrWidth][LfsrWidth-1]) else + $fatal(1, "LFSR mask is not correct. The MSB must be 1." ); + assert((CipherLayers > 0) && (LfsrWidth == 64) || (CipherLayers == 0)) else + $fatal(1, "Use additional cipher layers only in conjunction with an LFSR width of 64 bit." ); +end + +`ifndef VERILATOR + all_zero: assert property ( + @(posedge clk_i) disable iff (!rst_ni) en_i |-> lfsr_d) + else $fatal(1,"Lfsr must not be all-zero."); +`endif +// pragma translate_on + +endmodule // lfsr diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv new file mode 100644 index 0000000000..60fdf19f7f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv @@ -0,0 +1,61 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Igor Loi - University of Bologna +// Author: Florian Zaruba, ETH Zurich +// Date: 12.11.2017 +// Description: 8-bit LFSR + +/// 8 bit Linear Feedback Shift register +module lfsr_8bit #( + parameter logic [7:0] SEED = 8'b0, + parameter int unsigned WIDTH = 8 +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + output logic [ WIDTH-1:0] refill_way_oh, + output logic [$clog2(WIDTH)-1:0] refill_way_bin +); + + localparam int unsigned LogWidth = $clog2(WIDTH); + + logic [7:0] shift_d, shift_q; + + always_comb begin + + automatic logic shift_in; + shift_in = !(shift_q[7] ^ shift_q[3] ^ shift_q[2] ^ shift_q[1]); + + shift_d = shift_q; + + if (en_i) shift_d = {shift_q[6:0], shift_in}; + + // output assignment + refill_way_oh = 'b0; + refill_way_oh[shift_q[LogWidth - 1:0]] = 1'b1; + refill_way_bin = shift_q; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ + if (~rst_ni) begin + shift_q <= SEED; + end else begin + shift_q <= shift_d; + end + end + + //pragma translate_off + initial begin + assert (WIDTH <= 8) else $fatal(1, "WIDTH needs to be less than 8 because of the 8-bit LFSR"); + end + //pragma translate_on + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lzc.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lzc.sv new file mode 100644 index 0000000000..424eb2ef62 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/lzc.sv @@ -0,0 +1,112 @@ +// Copyright (c) 2018 - 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +/// A trailing zero counter / leading zero counter. +/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) +/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) +/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains +/// the maximum number of zeros - 1. For example: +/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) +/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) +/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) +/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). +/// This speeds up simulation significantly. +module lzc #( + /// The width of the input vector. + parameter int unsigned WIDTH = 2, + /// Mode selection: 0 -> trailing zero, 1 -> leading zero + parameter bit MODE = 1'b0, + /// Dependent parameter. Do **not** change! + /// + /// Width of the output signal with the zero count. + parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) +) ( + /// Input vector to be counted. + input logic [WIDTH-1:0] in_i, + /// Count of the leading / trailing zeros. + output logic [CNT_WIDTH-1:0] cnt_o, + /// Counter is empty: Asserted if all bits in in_i are zero. + output logic empty_o +); + + if (WIDTH == 1) begin : gen_degenerate_lzc + + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + + end else begin : gen_lzc + + localparam int unsigned NumLevels = $clog2(WIDTH); + + // pragma translate_off + initial begin + assert(WIDTH > 0) else $fatal(1, "input must be at least one bit wide"); + end + // pragma translate_on + + logic [WIDTH-1:0][NumLevels-1:0] index_lut; + logic [2**NumLevels-1:0] sel_nodes; + logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes; + + logic [WIDTH-1:0] in_tmp; + + // reverse vector if required + always_comb begin : flip_vector + for (int unsigned i = 0; i < WIDTH; i++) begin + in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; + end + end + + for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut + assign index_lut[j] = (NumLevels)'(unsigned'(j)); + end + + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : g_levels + if (unsigned'(level) == NumLevels - 1) begin : g_last_level + for (genvar k = 0; k < 2 ** level; k++) begin : g_level + // if two successive indices are still in the vector... + if (unsigned'(k) * 2 < WIDTH - 1) begin : g_reduce + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2] | in_tmp[k * 2 + 1]; + assign index_nodes[2 ** level - 1 + k] = (in_tmp[k * 2] == 1'b1) + ? index_lut[k * 2] : + index_lut[k * 2 + 1]; + end + // if only the first index is still in the vector... + if (unsigned'(k) * 2 == WIDTH - 1) begin : g_base + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2]; + assign index_nodes[2 ** level - 1 + k] = index_lut[k * 2]; + end + // if index is out of range + if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range + assign sel_nodes[2 ** level - 1 + k] = 1'b0; + assign index_nodes[2 ** level - 1 + k] = '0; + end + end + end else begin : g_not_last_level + for (genvar l = 0; l < 2 ** level; l++) begin : g_level + assign sel_nodes[2 ** level - 1 + l] = + sel_nodes[2 ** (level + 1) - 1 + l * 2] | sel_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + assign index_nodes[2 ** level - 1 + l] = (sel_nodes[2 ** (level + 1) - 1 + l * 2] == 1'b1) + ? index_nodes[2 ** (level + 1) - 1 + l * 2] : + index_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + end + end + end + + assign cnt_o = NumLevels > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)) {1'b0}}; + assign empty_o = NumLevels > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); + + end : gen_lzc + +endmodule : lzc diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/popcount.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/popcount.sv new file mode 100644 index 0000000000..6fde114f3e --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/popcount.sv @@ -0,0 +1,57 @@ +// Copyright (C) 2013-2018 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Manuel Eggimann + +// Description: This module calculates the hamming weight (number of ones) in +// its input vector using a balanced binary adder tree. Recursive instantiation +// is used to build the tree. Any unsigned INPUT_WIDTH larger or equal 2 is +// legal. The module pads the signal internally to the next power of two. The +// output result width is ceil(log2(INPUT_WIDTH))+1. + +module popcount #( + parameter int unsigned INPUT_WIDTH = 256, + localparam int unsigned PopcountWidth = $clog2(INPUT_WIDTH)+1 +) ( + input logic [INPUT_WIDTH-1:0] data_i, + output logic [PopcountWidth-1:0] popcount_o +); + + localparam int unsigned PaddedWidth = 1 << $clog2(INPUT_WIDTH); + + logic [PaddedWidth-1:0] padded_input; + logic [PopcountWidth-2:0] left_child_result, right_child_result; + + //Zero pad the input to next power of two + assign padded_input = {{{PaddedWidth-INPUT_WIDTH}{1'b0}}, data_i}; + + //Recursive instantiation to build binary adder tree + if (INPUT_WIDTH == 1) begin : single_node + assign left_child_result = 1'b0; + assign right_child_result = padded_input[0]; + end else if (INPUT_WIDTH == 2) begin : leaf_node + assign left_child_result = padded_input[1]; + assign right_child_result = padded_input[0]; + end else begin : non_leaf_node + popcount #(.INPUT_WIDTH(PaddedWidth / 2)) + left_child( + .data_i(padded_input[PaddedWidth-1:PaddedWidth/2]), + .popcount_o(left_child_result)); + + popcount #(.INPUT_WIDTH(PaddedWidth / 2)) + right_child( + .data_i(padded_input[PaddedWidth/2-1:0]), + .popcount_o(right_child_result)); + end + + //Output assignment + assign popcount_o = left_child_result + right_child_result; + +endmodule : popcount diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv new file mode 100644 index 0000000000..90301c822c --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv @@ -0,0 +1,348 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Wolfgang Roenninger , ETH Zurich +// Date: 02.04.2019 +// Description: logarithmic arbitration tree with round robin arbitration scheme. + +/// The rr_arb_tree employs non-starving round robin-arbitration - i.e., the priorities +/// rotate each cycle. +/// +/// ## Fair vs. unfair Arbitration +/// +/// This refers to fair throughput distribution when not all inputs have active requests. +/// This module has an internal state `rr_q` which defines the highest priority input. (When +/// `ExtPrio` is `1'b1` this state is provided from the outside.) The arbitration tree will +/// choose the input with the same index as currently defined by the state if it has an active +/// request. Otherwise a *random* other active input is selected. The parameter `FairArb` is used +/// to distinguish between two methods of calculating the next state. +/// * `1'b0`: The next state is calculated by advancing the current state by one. This leads to the +/// state being calculated without the context of the active request. Leading to an +/// unfair throughput distribution if not all inputs have active requests. +/// * `1'b1`: The next state jumps to the next unserved request with higher index. +/// This is achieved by using two trailing-zero-counters (`lzc`). The upper has the masked +/// `req_i` signal with all indices which will have a higher priority in the next state. +/// The trailing zero count defines the input index with the next highest priority after +/// the current one is served. When the upper is empty the lower `lzc` provides the +/// wrapped index if there are outstanding requests with lower or same priority. +/// The implication of throughput fairness on the module timing are: +/// * The trailing zero counter (`lzc`) has a loglog relation of input to output timing. This means +/// that in this module the input to register path scales with Log(Log(`NumIn`)). +/// * The `rr_arb_tree` data multiplexing scales with Log(`NumIn`). This means that the input to output +/// timing path of this module also scales scales with Log(`NumIn`). +/// This implies that in this module the input to output path is always longer than the input to +/// register path. As the output data usually also terminates in a register the parameter `FairArb` +/// only has implications on the area. When it is `1'b0` a static plus one adder is instantiated. +/// If it is `1'b1` two `lzc`, a masking logic stage and a two input multiplexer are instantiated. +/// However these are small in respect of the data multiplexers needed, as the width of the `req_i` +/// signal is usually less as than `DataWidth`. +module rr_arb_tree #( + /// Number of inputs to be arbitrated. + parameter int unsigned NumIn = 64, + /// Data width of the payload in bits. Not needed if `DataType` is overwritten. + parameter int unsigned DataWidth = 32, + /// Data type of the payload, can be overwritten with custom type. Only use of `DataWidth`. + parameter type DataType = logic [DataWidth-1:0], + /// The `ExtPrio` option allows to override the internal round robin counter via the + /// `rr_i` signal. This can be useful in case multiple arbiters need to have + /// rotating priorities that are operating in lock-step. If static priority arbitration + /// is needed, just connect `rr_i` to '0. + /// + /// Set to 1'b1 to enable. + parameter bit ExtPrio = 1'b0, + /// If `AxiVldRdy` is set, the req/gnt signals are compliant with the AXI style vld/rdy + /// handshake. Namely, upstream vld (req) must not depend on rdy (gnt), as it can be deasserted + /// again even though vld is asserted. Enabling `AxiVldRdy` leads to a reduction of arbiter + /// delay and area. + /// + /// Set to `1'b1` to treat req/gnt as vld/rdy. + parameter bit AxiVldRdy = 1'b0, + /// The `LockIn` option prevents the arbiter from changing the arbitration + /// decision when the arbiter is disabled. I.e., the index of the first request + /// that wins the arbitration will be locked in case the destination is not + /// able to grant the request in the same cycle. + /// + /// Set to `1'b1` to enable. + parameter bit LockIn = 1'b0, + /// When set, ensures that throughput gets distributed evenly between all inputs. + /// + /// Set to `1'b0` to disable. + parameter bit FairArb = 1'b1, + /// Dependent parameter, do **not** overwrite. + /// Width of the arbitration priority signal and the arbitrated index. + parameter int unsigned IdxWidth = (NumIn > 32'd1) ? unsigned'($clog2(NumIn)) : 32'd1, + /// Dependent parameter, do **not** overwrite. + /// Type for defining the arbitration priority and arbitrated index signal. + parameter type idx_t = logic [IdxWidth-1:0] +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Clears the arbiter state. Only used if `ExtPrio` is `1'b0` or `LockIn` is `1'b1`. + input logic flush_i, + /// External round-robin priority. Only used if `ExtPrio` is `1'b1.` + input idx_t rr_i, + /// Input requests arbitration. + input logic [NumIn-1:0] req_i, + /* verilator lint_off UNOPTFLAT */ + /// Input request is granted. + output logic [NumIn-1:0] gnt_o, + /* verilator lint_on UNOPTFLAT */ + /// Input data for arbitration. + input DataType [NumIn-1:0] data_i, + /// Output request is valid. + output logic req_o, + /// Output request is granted. + input logic gnt_i, + /// Output data. + output DataType data_o, + /// Index from which input the data came from. + output idx_t idx_o +); + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + // Default SVA reset + default disable iff (!rst_ni || flush_i); + `endif + `endif + // pragma translate_on + + // just pass through in this corner case + if (NumIn == unsigned'(1)) begin : gen_pass_through + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[0]; + assign idx_o = '0; + // non-degenerate cases + end else begin : gen_arbiter + localparam int unsigned NumLevels = unsigned'($clog2(NumIn)); + + /* verilator lint_off UNOPTFLAT */ + idx_t [2**NumLevels-2:0] index_nodes; // used to propagate the indices + DataType [2**NumLevels-2:0] data_nodes; // used to propagate the data + logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters + logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave + /* lint_off */ + idx_t rr_q; + logic [NumIn-1:0] req_d; + + // the final arbitration decision can be taken from the root of the tree + assign req_o = req_nodes[0]; + assign data_o = data_nodes[0]; + assign idx_o = index_nodes[0]; + + if (ExtPrio) begin : gen_ext_rr + assign rr_q = rr_i; + assign req_d = req_i; + end else begin : gen_int_rr + idx_t rr_d; + + // lock arbiter decision in case we got at least one req and no acknowledge + if (LockIn) begin : gen_lock + logic lock_d, lock_q; + logic [NumIn-1:0] req_q; + + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q) ? req_q : req_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) begin + lock_q <= '0; + end else begin + if (flush_i) begin + lock_q <= '0; + end else begin + lock_q <= lock_d; + end + end + end + + // pragma translate_off + `ifndef VERILATOR + lock: assert property( + @(posedge clk_i) LockIn |-> req_o && + (!gnt_i && !flush_i) |=> idx_o == $past(idx_o)) else + $fatal (1, "Lock implies same arbiter decision in next cycle if output is not \ + ready."); + + logic [NumIn-1:0] req_tmp; + assign req_tmp = req_q & req_i; + lock_req: assume property( + @(posedge clk_i) LockIn |-> lock_d |=> req_tmp == req_q) else + $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is \ + enabled."); + `endif + // pragma translate_on + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) begin + req_q <= '0; + end else begin + if (flush_i) begin + req_q <= '0; + end else begin + req_q <= req_d; + end + end + end + end else begin : gen_no_lock + assign req_d = req_i; + end + + if (FairArb) begin : gen_fair_arb + logic [NumIn-1:0] upper_mask, lower_mask; + idx_t upper_idx, lower_idx, next_idx; + logic upper_empty, lower_empty; + + for (genvar i = 0; i < NumIn; i++) begin : gen_mask + assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0; + assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0; + end + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_upper ( + .in_i ( upper_mask ), + .cnt_o ( upper_idx ), + .empty_o ( upper_empty ) + ); + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_lower ( + .in_i ( lower_mask ), + .cnt_o ( lower_idx ), + .empty_o ( /*unused*/ ) + ); + + assign next_idx = upper_empty ? lower_idx : upper_idx; + assign rr_d = (gnt_i && req_o) ? next_idx : rr_q; + + end else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o) ? ((rr_q == idx_t'(NumIn-1)) ? '0 : rr_q + 1'b1) : rr_q; + end + + // this holds the highest priority + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) begin + rr_q <= '0; + end else begin + if (flush_i) begin + rr_q <= '0; + end else begin + rr_q <= rr_d; + end + end + end + end + + assign gnt_nodes[0] = gnt_i; + + // arbiter tree + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : gen_levels + for (genvar l = 0; l < 2**level; l++) begin : gen_level + // local select signal + logic sel; + // index calcs + localparam int unsigned Idx0 = 2**level-1+l;// current node + localparam int unsigned Idx1 = 2**(level+1)-1+l*2; + ////////////////////////////////////////////////////////////// + // uppermost level where data is fed in from the inputs + if (unsigned'(level) == NumLevels-1) begin : gen_first_level + // if two successive indices are still in the vector... + if (unsigned'(l) * 2 < NumIn-1) begin : gen_reduce + assign req_nodes[Idx0] = req_d[l*2] | req_d[l*2+1]; + + // arbitration: round robin + assign sel = ~req_d[l*2] | req_d[l*2+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = idx_t'(sel); + assign data_nodes[Idx0] = (sel) ? data_i[l*2+1] : data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]) & ~sel; + assign gnt_o[l*2+1] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2+1]) & sel; + end + // if only the first index is still in the vector... + if (unsigned'(l) * 2 == NumIn-1) begin : gen_first + assign req_nodes[Idx0] = req_d[l*2]; + assign index_nodes[Idx0] = '0;// always zero in this case + assign data_nodes[Idx0] = data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]); + end + // if index is out of range, fill up with zeros (will get pruned) + if (unsigned'(l) * 2 > NumIn-1) begin : gen_out_of_range + assign req_nodes[Idx0] = 1'b0; + assign index_nodes[Idx0] = idx_t'('0); + assign data_nodes[Idx0] = DataType'('0); + end + ////////////////////////////////////////////////////////////// + // general case for other levels within the tree + end else begin : gen_other_levels + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1+1]; + + // arbitration: round robin + assign sel = ~req_nodes[Idx1] | req_nodes[Idx1+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = (sel) ? + idx_t'({1'b1, index_nodes[Idx1+1][NumLevels-unsigned'(level)-2:0]}) : + idx_t'({1'b0, index_nodes[Idx1][NumLevels-unsigned'(level)-2:0]}); + + assign data_nodes[Idx0] = (sel) ? data_nodes[Idx1+1] : data_nodes[Idx1]; + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + assign gnt_nodes[Idx1+1] = gnt_nodes[Idx0] & sel; + end + ////////////////////////////////////////////////////////////// + end + end + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + initial begin : p_assert + assert(NumIn) + else $fatal(1, "Input must be at least one element wide."); + assert(!(LockIn && ExtPrio)) + else $fatal(1,"Cannot use LockIn feature together with external ExtPrio."); + end + + hot_one : assert property( + @(posedge clk_i) $onehot0(gnt_o)) + else $fatal (1, "Grant signal must be hot1 or zero."); + + gnt0 : assert property( + @(posedge clk_i) |gnt_o |-> gnt_i) + else $fatal (1, "Grant out implies grant in."); + + gnt1 : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> |gnt_o) + else $fatal (1, "Req out and grant in implies grant out."); + + gnt_idx : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> gnt_o[idx_o]) + else $fatal (1, "Idx_o / gnt_o do not match."); + + req0 : assert property( + @(posedge clk_i) |req_i |-> req_o) + else $fatal (1, "Req in implies req out."); + + req1 : assert property( + @(posedge clk_i) req_o |-> |req_i) + else $fatal (1, "Req out implies req in."); + `endif + `endif + // pragma translate_on + end + +endmodule : rr_arb_tree diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv new file mode 100644 index 0000000000..7193fbcd81 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv @@ -0,0 +1,53 @@ + +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: +// +// Description: Simple shift register for arbitrary depth and types + +module shift_reg #( + parameter type dtype = logic, + parameter int unsigned Depth = 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input dtype d_i, + output dtype d_o +); + + // register of depth 0 is a wire + if (Depth == 0) begin : gen_pass_through + assign d_o = d_i; + // register of depth 1 is a simple register + end else if (Depth == 1) begin : gen_register + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + d_o <= '0; + end else begin + d_o <= d_i; + end + end + // if depth is greater than 1 it becomes a shift register + end else if (Depth > 1) begin : gen_shift_reg + dtype [Depth-1:0] reg_d, reg_q; + assign d_o = reg_q[Depth-1]; + assign reg_d = {reg_q[Depth-2:0], d_i}; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + reg_q <= '0; + end else begin + reg_q <= reg_d; + end + end + end + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv new file mode 100644 index 0000000000..c8ca2a8769 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv @@ -0,0 +1,49 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. + +module stream_arbiter #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + stream_arbiter_flushable #( + .DATA_T (DATA_T), + .N_INP (N_INP), + .ARBITER (ARBITER) + ) i_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .inp_data_i (inp_data_i), + .inp_valid_i (inp_valid_i), + .inp_ready_o (inp_ready_o), + .oup_data_o (oup_data_o), + .oup_valid_o (oup_valid_o), + .oup_ready_i (oup_ready_i) + ); + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv new file mode 100644 index 0000000000..32946e6859 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv @@ -0,0 +1,82 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is fair round-robin tree, see `rr_arb_tree` for details. + +module stream_arbiter_flushable #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + if (ARBITER == "rr") begin : gen_rr_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b0), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else if (ARBITER == "prio") begin : gen_prio_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b1), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else begin : gen_arb_error + // pragma translate_off + $fatal(1, "Invalid value for parameter 'ARBITER'!"); + // pragma translate_on + end + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv new file mode 100644 index 0000000000..69ad3099b1 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv @@ -0,0 +1,36 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Connects the input stream (valid-ready) handshake to one of `N_OUP` output stream handshakes. +/// +/// This module has no data ports because stream data does not need to be demultiplexed: the data of +/// the input stream can just be applied at all output streams. +module stream_demux #( + /// Number of connected outputs. + parameter int unsigned N_OUP = 32'd1, + /// Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned LOG_N_OUP = (N_OUP > 32'd1) ? unsigned'($clog2(N_OUP)) : 1'b1 +) ( + input logic inp_valid_i, + output logic inp_ready_o, + + input logic [LOG_N_OUP-1:0] oup_sel_i, + + output logic [N_OUP-1:0] oup_valid_o, + input logic [N_OUP-1:0] oup_ready_i +); + + always_comb begin + oup_valid_o = '0; + oup_valid_o[oup_sel_i] = inp_valid_i; + end + assign inp_ready_o = oup_ready_i[oup_sel_i]; + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv new file mode 100644 index 0000000000..34607d916d --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv @@ -0,0 +1,46 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Stream multiplexer: connects the output to one of `N_INP` data streams with valid-ready +/// handshaking. + +module stream_mux #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = 0, // Synopsys DC requires a default value for value parameters. + /// Dependent parameters, DO NOT OVERRIDE! + parameter integer LOG_N_INP = $clog2(N_INP) +) ( + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + input logic [LOG_N_INP-1:0] inp_sel_i, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + always_comb begin + inp_ready_o = '0; + inp_ready_o[inp_sel_i] = oup_ready_i; + end + assign oup_data_o = inp_data_i[inp_sel_i]; + assign oup_valid_o = inp_valid_i[inp_sel_i]; + +// pragma translate_off +`ifndef VERILATOR + initial begin: p_assertions + assert (N_INP >= 1) else $fatal (1, "The number of inputs must be at least 1!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/unread.sv b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/unread.sv new file mode 100644 index 0000000000..80e7356237 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/unread.sv @@ -0,0 +1,21 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 29.10.2018 +// Description: Dummy circuit to mitigate Open Pin warnings + +/* verilator lint_off UNUSED */ +module unread ( + input logic d_i +); + +endmodule +/* verilator lint_on UNUSED */ diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv new file mode 100644 index 0000000000..c1f7992707 --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv @@ -0,0 +1,248 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// Description: Functional module of a generic SRAM +// +// Parameters: +// - NumWords: Number of words in the macro. Address width can be calculated with: +// `AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1` +// The module issues a warning if there is a request on an address which is +// not in range. +// - DataWidth: Width of the ports `wdata_i` and `rdata_o`. +// - ByteWidth: Width of a byte, the byte enable signal `be_i` can be calculated with the +// ceiling division `ceil(DataWidth, ByteWidth)`. +// - NumPorts: Number of read and write ports. Each is a full port. Ports with a higher +// index read and write after the ones with lower indices. +// - Latency: Read latency, the read data is available this many cycles after a request. +// - SimInit: Macro simulation initialization. Values are: +// "zeros": Each bit gets initialized with 1'b0. +// "ones": Each bit gets initialized with 1'b1. +// "random": Each bit gets random initialized with 1'b0 or 1'b1. +// "none": Each bit gets initialized with 1'bx. (default) +// - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with +// the instantiated parameters and signal widths. +// - ImplKey: Key by which an instance can refer to a specific implementation (e.g. macro). +// May be used to look up additional parameters for implementation (e.g. generator, +// line width, muxing) in an external reference, such as a configuration file. +// +// Ports: +// - `clk_i`: Clock +// - `rst_ni`: Asynchronous reset, active low +// - `req_i`: Request, active high +// - `we_i`: Write request, active high +// - `addr_i`: Request address +// - `wdata_i`: Write data, has to be valid on request +// - `be_i`: Byte enable, active high +// - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low. +// +// Behaviour: +// - Address collision: When Ports are making a write access onto the same address, +// the write operation will start at the port with the lowest address +// index, each port will overwrite the changes made by the previous ports +// according how the respective `be_i` signal is set. +// - Read data on write: This implementation will not produce a read data output on the signal +// `rdata_o` when `req_i` and `we_i` are asserted. The output data is stable +// on write requests. + +module tc_sram #( + parameter int unsigned NumWords = 32'd1024, // Number of Words in data array + parameter int unsigned DataWidth = 32'd128, // Data signal width + parameter int unsigned ByteWidth = 32'd8, // Width of a data byte + parameter int unsigned NumPorts = 32'd2, // Number of read and write ports + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter bit PrintSimCfg = 1'b0, // Print configuration + parameter ImplKey = "none", // Reference to specific implementation + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type be_t = logic [BeWidth-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable + input addr_t [NumPorts-1:0] addr_i, // request address + input data_t [NumPorts-1:0] wdata_i, // write data + input be_t [NumPorts-1:0] be_i, // write byte enable + // output ports + output data_t [NumPorts-1:0] rdata_o // read data +); + + // memory array + data_t sram [NumWords-1:0]; + // hold the read address when no read access is made + addr_t [NumPorts-1:0] r_addr_q; + + // SRAM simulation initialization + data_t init_val[NumWords-1:0]; + initial begin : proc_sram_init + for (int unsigned i = 0; i < NumWords; i++) begin + case (SimInit) + "zeros": init_val[i] = {DataWidth{1'b0}}; + "ones": init_val[i] = {DataWidth{1'b1}}; + "random": init_val[i] = {DataWidth{$urandom()}}; + default: init_val[i] = {DataWidth{1'bx}}; + endcase + end + end + + // set the read output if requested + // The read data at the highest array index is set combinational. + // It gets then delayed for a number of cycles until it gets available at the output at + // array index 0. + + // read data output assignment + data_t [NumPorts-1:0][Latency-1:0] rdata_q, rdata_d; + if (Latency == 32'd0) begin : gen_no_read_lat + for (genvar i = 0; i < NumPorts; i++) begin : gen_port + assign rdata_o[i] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end else begin : gen_read_lat + + always_comb begin + for (int unsigned i = 0; i < NumPorts; i++) begin + rdata_o[i] = rdata_q[i][0]; + for (int unsigned j = 0; j < (Latency-1); j++) begin + rdata_d[i][j] = rdata_q[i][j+1]; + end + rdata_d[i][Latency-1] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end + end + + // In case simulation initialization is disabled (SimInit == 'none'), don't assign to the sram + // content at all. This improves simulation performance in tools like verilator + if (SimInit == "none") begin + // write memory array without initialization + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + end + end else begin + // read value latch happens before new data is written to the sram + for (int unsigned i = 0; i < NumPorts; i++) begin + if (Latency != 0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= rdata_d[i][j]; + end + end + end + // there is a request for the SRAM, latch the required register + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin + // update value when write is set at clock + for (int unsigned j = 0; j < BeWidth; j++) begin + if (be_i[i][j]) begin + sram[addr_i[i]][j*ByteWidth+:ByteWidth] <= wdata_i[i][j*ByteWidth+:ByteWidth]; + end + end + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; + end + end // if req_i + end // for ports + end // if !rst_ni + end + end else begin + // write memory array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + // Fix to avoid runtime space reaching maximum capacity in simulation + foreach (init_val[i]) begin + sram[i] <= init_val[i]; + end + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + // initialize the read output register for each port + if (Latency != 32'd0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= init_val[{AddrWidth{1'b0}}]; + end + end + end + end else begin + // read value latch happens before new data is written to the sram + for (int unsigned i = 0; i < NumPorts; i++) begin + if (Latency != 0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= rdata_d[i][j]; + end + end + end + // there is a request for the SRAM, latch the required register + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin + // update value when write is set at clock + for (int unsigned j = 0; j < BeWidth; j++) begin + if (be_i[i][j]) begin + sram[addr_i[i]][j*ByteWidth+:ByteWidth] <= wdata_i[i][j*ByteWidth+:ByteWidth]; + end + end + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; + end + end // if req_i + end // for ports + end // if !rst_ni + end + end + +// Validate parameters. +// pragma translate_off +`ifndef VERILATOR +`ifndef TARGET_SYNTHESIS + initial begin: p_assertions + assert ($bits(addr_i) == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`"); + assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`"); + assert ($bits(be_i) == NumPorts * BeWidth) else $fatal(1, "BeWidth problem on `be_i`" ); + assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`"); + assert (NumWords >= 32'd1) else $fatal(1, "NumWords has to be > 0"); + assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0"); + assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0"); + assert (NumPorts >= 32'd1) else $fatal(1, "The number of ports must be at least 1!"); + end + initial begin: p_sim_hello + if (PrintSimCfg) begin + $display("#################################################################################"); + $display("tc_sram functional instantiated with the configuration:" ); + $display("Instance: %m" ); + $display("Number of ports (dec): %0d", NumPorts ); + $display("Number of words (dec): %0d", NumWords ); + $display("Address width (dec): %0d", AddrWidth ); + $display("Data width (dec): %0d", DataWidth ); + $display("Byte width (dec): %0d", ByteWidth ); + $display("Byte enable width (dec): %0d", BeWidth ); + $display("Latency Cycles (dec): %0d", Latency ); + $display("Simulation init (str): %0s", SimInit ); + $display("#################################################################################"); + end + end + for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions + assert property ( @(posedge clk_i) disable iff (!rst_ni) + (req_i[i] |-> (addr_i[i] < NumWords))) else + $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!", + addr_i[i], i); + end + +`endif +`endif +// pragma translate_on +endmodule diff --git a/flow/designs/src/ethmac/BUILD.bazel b/flow/designs/src/ethmac/BUILD.bazel new file mode 100644 index 0000000000..1639cf0a3b --- /dev/null +++ b/flow/designs/src/ethmac/BUILD.bazel @@ -0,0 +1,5 @@ +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/gcd/BUILD.bazel b/flow/designs/src/gcd/BUILD.bazel new file mode 100644 index 0000000000..1639cf0a3b --- /dev/null +++ b/flow/designs/src/gcd/BUILD.bazel @@ -0,0 +1,5 @@ +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/harness/.gitignore b/flow/designs/src/harness/.gitignore deleted file mode 100644 index 7f2238d06e..0000000000 --- a/flow/designs/src/harness/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.v -*.fir -*.json -*.v diff --git a/flow/designs/src/harness/design.sdc b/flow/designs/src/harness/design.sdc deleted file mode 100644 index b0fe5c6ab4..0000000000 --- a/flow/designs/src/harness/design.sdc +++ /dev/null @@ -1,12 +0,0 @@ -################################################################### - -# Created by write_sdc on Mon Jun 17 07:26:34 2019 - -################################################################### -set sdc_version 2.0 - -set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA -# Start with 250MHz for nangate45, relatively conservative -create_clock [get_ports clock] -period 4 -waveform {0 2} -set_clock_uncertainty 0 [get_clocks clock] -set_input_delay -clock clock -max 0 [get_ports clock] diff --git a/flow/designs/src/ibex/ibex_alu.v b/flow/designs/src/ibex/ibex_alu.v deleted file mode 100644 index 1c008c800e..0000000000 --- a/flow/designs/src/ibex/ibex_alu.v +++ /dev/null @@ -1,729 +0,0 @@ -module ibex_alu ( - operator_i, - operand_a_i, - operand_b_i, - instr_first_cycle_i, - multdiv_operand_a_i, - multdiv_operand_b_i, - multdiv_sel_i, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - adder_result_o, - adder_result_ext_o, - result_o, - comparison_result_o, - is_equal_result_o -); - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - input wire [5:0] operator_i; - input wire [31:0] operand_a_i; - input wire [31:0] operand_b_i; - input wire instr_first_cycle_i; - input wire [32:0] multdiv_operand_a_i; - input wire [32:0] multdiv_operand_b_i; - input wire multdiv_sel_i; - input wire [63:0] imd_val_q_i; - output reg [63:0] imd_val_d_o; - output reg [1:0] imd_val_we_o; - output wire [31:0] adder_result_o; - output wire [33:0] adder_result_ext_o; - output reg [31:0] result_o; - output wire comparison_result_o; - output wire is_equal_result_o; - wire [31:0] operand_a_rev; - wire [32:0] operand_b_neg; - generate - genvar k; - for (k = 0; k < 32; k = k + 1) begin : gen_rev_operand_a - assign operand_a_rev[k] = operand_a_i[31 - k]; - end - endgenerate - reg adder_op_b_negate; - wire [32:0] adder_in_a; - reg [32:0] adder_in_b; - wire [31:0] adder_result; - localparam [5:0] ibex_pkg_ALU_EQ = 23; - localparam [5:0] ibex_pkg_ALU_GE = 21; - localparam [5:0] ibex_pkg_ALU_GEU = 22; - localparam [5:0] ibex_pkg_ALU_LT = 19; - localparam [5:0] ibex_pkg_ALU_LTU = 20; - localparam [5:0] ibex_pkg_ALU_MAX = 27; - localparam [5:0] ibex_pkg_ALU_MAXU = 28; - localparam [5:0] ibex_pkg_ALU_MIN = 25; - localparam [5:0] ibex_pkg_ALU_MINU = 26; - localparam [5:0] ibex_pkg_ALU_NE = 24; - localparam [5:0] ibex_pkg_ALU_SLT = 37; - localparam [5:0] ibex_pkg_ALU_SLTU = 38; - localparam [5:0] ibex_pkg_ALU_SUB = 1; - always @(*) begin - adder_op_b_negate = 1'b0; - case (operator_i) - ibex_pkg_ALU_SUB, ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: adder_op_b_negate = 1'b1; - default: - ; - endcase - end - assign adder_in_a = (multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i, 1'b1}); - assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {1'b1}}; - always @(*) - case (1'b1) - multdiv_sel_i: adder_in_b = multdiv_operand_b_i; - adder_op_b_negate: adder_in_b = operand_b_neg; - default: adder_in_b = {operand_b_i, 1'b0}; - endcase - assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); - assign adder_result = adder_result_ext_o[32:1]; - assign adder_result_o = adder_result; - wire is_equal; - reg is_greater_equal; - reg cmp_signed; - always @(*) - case (operator_i) - ibex_pkg_ALU_GE, ibex_pkg_ALU_LT, ibex_pkg_ALU_SLT, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX: cmp_signed = 1'b1; - default: cmp_signed = 1'b0; - endcase - assign is_equal = adder_result == 32'b00000000000000000000000000000000; - assign is_equal_result_o = is_equal; - always @(*) - if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) - is_greater_equal = adder_result[31] == 1'b0; - else - is_greater_equal = operand_a_i[31] ^ cmp_signed; - reg cmp_result; - always @(*) - case (operator_i) - ibex_pkg_ALU_EQ: cmp_result = is_equal; - ibex_pkg_ALU_NE: cmp_result = ~is_equal; - ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: cmp_result = is_greater_equal; - ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: cmp_result = ~is_greater_equal; - default: cmp_result = is_equal; - endcase - assign comparison_result_o = cmp_result; - reg shift_left; - wire shift_ones; - wire shift_arith; - wire shift_funnel; - wire shift_sbmode; - reg [5:0] shift_amt; - wire [5:0] shift_amt_compl; - reg [31:0] shift_operand; - reg [32:0] shift_result_ext; - reg unused_shift_result_ext; - reg [31:0] shift_result; - reg [31:0] shift_result_rev; - wire bfp_op; - wire [4:0] bfp_len; - wire [4:0] bfp_off; - wire [31:0] bfp_mask; - wire [31:0] bfp_mask_rev; - wire [31:0] bfp_result; - localparam [5:0] ibex_pkg_ALU_BFP = 49; - assign bfp_op = (RV32B != ibex_pkg_RV32BNone ? operator_i == ibex_pkg_ALU_BFP : 1'b0); - assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; - assign bfp_off = operand_b_i[20:16]; - assign bfp_mask = (RV32B != ibex_pkg_RV32BNone ? ~(32'hffffffff << bfp_len) : {32 {1'sb0}}); - generate - genvar i; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_bfp_mask - assign bfp_mask_rev[i] = bfp_mask[31 - i]; - end - endgenerate - assign bfp_result = (RV32B != ibex_pkg_RV32BNone ? (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : {32 {1'sb0}}); - wire [1:1] sv2v_tmp_86907; - assign sv2v_tmp_86907 = operand_b_i[5] & shift_funnel; - always @(*) shift_amt[5] = sv2v_tmp_86907; - assign shift_amt_compl = 32 - operand_b_i[4:0]; - always @(*) - if (bfp_op) - shift_amt[4:0] = bfp_off; - else - shift_amt[4:0] = (instr_first_cycle_i ? (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0])); - localparam [5:0] ibex_pkg_ALU_SBCLR = 44; - localparam [5:0] ibex_pkg_ALU_SBINV = 45; - localparam [5:0] ibex_pkg_ALU_SBSET = 43; - assign shift_sbmode = (RV32B != ibex_pkg_RV32BNone ? ((operator_i == ibex_pkg_ALU_SBSET) | (operator_i == ibex_pkg_ALU_SBCLR)) | (operator_i == ibex_pkg_ALU_SBINV) : 1'b0); - localparam [5:0] ibex_pkg_ALU_FSL = 41; - localparam [5:0] ibex_pkg_ALU_FSR = 42; - localparam [5:0] ibex_pkg_ALU_ROL = 14; - localparam [5:0] ibex_pkg_ALU_ROR = 13; - localparam [5:0] ibex_pkg_ALU_SLL = 10; - localparam [5:0] ibex_pkg_ALU_SLO = 12; - always @(*) begin - case (operator_i) - ibex_pkg_ALU_SLL: shift_left = 1'b1; - ibex_pkg_ALU_SLO, ibex_pkg_ALU_BFP: shift_left = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0); - ibex_pkg_ALU_ROL: shift_left = (RV32B != ibex_pkg_RV32BNone ? instr_first_cycle_i : 0); - ibex_pkg_ALU_ROR: shift_left = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 0); - ibex_pkg_ALU_FSL: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0); - ibex_pkg_ALU_FSR: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0); - default: shift_left = 1'b0; - endcase - if (shift_sbmode) - shift_left = 1'b1; - end - localparam [5:0] ibex_pkg_ALU_SRA = 8; - assign shift_arith = operator_i == ibex_pkg_ALU_SRA; - localparam [5:0] ibex_pkg_ALU_SRO = 11; - assign shift_ones = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_SLO) | (operator_i == ibex_pkg_ALU_SRO) : 1'b0); - assign shift_funnel = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_FSL) | (operator_i == ibex_pkg_ALU_FSR) : 1'b0); - always @(*) begin - if (RV32B == ibex_pkg_RV32BNone) - shift_operand = (shift_left ? operand_a_rev : operand_a_i); - else - case (1'b1) - bfp_op: shift_operand = bfp_mask_rev; - shift_sbmode: shift_operand = 32'h80000000; - default: shift_operand = (shift_left ? operand_a_rev : operand_a_i); - endcase - shift_result_ext = $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0]); - shift_result = shift_result_ext[31:0]; - unused_shift_result_ext = shift_result_ext[32]; - begin : sv2v_autoblock_6 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - shift_result_rev[i] = shift_result[31 - i]; - end - shift_result = (shift_left ? shift_result_rev : shift_result); - end - wire bwlogic_or; - wire bwlogic_and; - wire [31:0] bwlogic_operand_b; - wire [31:0] bwlogic_or_result; - wire [31:0] bwlogic_and_result; - wire [31:0] bwlogic_xor_result; - reg [31:0] bwlogic_result; - reg bwlogic_op_b_negate; - localparam [5:0] ibex_pkg_ALU_ANDN = 7; - localparam [5:0] ibex_pkg_ALU_CMIX = 40; - localparam [5:0] ibex_pkg_ALU_ORN = 6; - localparam [5:0] ibex_pkg_ALU_XNOR = 5; - always @(*) - case (operator_i) - ibex_pkg_ALU_XNOR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_ANDN: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0); - ibex_pkg_ALU_CMIX: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 1'b0); - default: bwlogic_op_b_negate = 1'b0; - endcase - assign bwlogic_operand_b = (bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i); - assign bwlogic_or_result = operand_a_i | bwlogic_operand_b; - assign bwlogic_and_result = operand_a_i & bwlogic_operand_b; - assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b; - localparam [5:0] ibex_pkg_ALU_OR = 3; - assign bwlogic_or = (operator_i == ibex_pkg_ALU_OR) | (operator_i == ibex_pkg_ALU_ORN); - localparam [5:0] ibex_pkg_ALU_AND = 4; - assign bwlogic_and = (operator_i == ibex_pkg_ALU_AND) | (operator_i == ibex_pkg_ALU_ANDN); - always @(*) - case (1'b1) - bwlogic_or: bwlogic_result = bwlogic_or_result; - bwlogic_and: bwlogic_result = bwlogic_and_result; - default: bwlogic_result = bwlogic_xor_result; - endcase - wire [5:0] bitcnt_result; - wire [31:0] minmax_result; - reg [31:0] pack_result; - wire [31:0] sext_result; - reg [31:0] singlebit_result; - reg [31:0] rev_result; - reg [31:0] shuffle_result; - reg [31:0] butterfly_result; - reg [31:0] invbutterfly_result; - reg [31:0] clmul_result; - reg [31:0] multicycle_result; - localparam [5:0] ibex_pkg_ALU_BDEP = 48; - localparam [5:0] ibex_pkg_ALU_BEXT = 47; - localparam [5:0] ibex_pkg_ALU_CLMULH = 52; - localparam [5:0] ibex_pkg_ALU_CLMULR = 51; - localparam [5:0] ibex_pkg_ALU_CLZ = 34; - localparam [5:0] ibex_pkg_ALU_CMOV = 39; - localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54; - localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56; - localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58; - localparam [5:0] ibex_pkg_ALU_CRC32_B = 53; - localparam [5:0] ibex_pkg_ALU_CRC32_H = 55; - localparam [5:0] ibex_pkg_ALU_CRC32_W = 57; - localparam [5:0] ibex_pkg_ALU_CTZ = 35; - localparam [5:0] ibex_pkg_ALU_GORC = 16; - localparam [5:0] ibex_pkg_ALU_PACKH = 31; - localparam [5:0] ibex_pkg_ALU_PACKU = 30; - localparam [5:0] ibex_pkg_ALU_SEXTB = 32; - localparam [5:0] ibex_pkg_ALU_UNSHFL = 18; - localparam integer ibex_pkg_RV32BFull = 2; - generate - if (RV32B != ibex_pkg_RV32BNone) begin : g_alu_rvb - wire zbe_op; - wire bitcnt_ctz; - wire bitcnt_clz; - wire bitcnt_cz; - reg [31:0] bitcnt_bits; - wire [31:0] bitcnt_mask_op; - reg [31:0] bitcnt_bit_mask; - reg [191:0] bitcnt_partial; - wire [31:0] bitcnt_partial_lsb_d; - wire [31:0] bitcnt_partial_msb_d; - assign bitcnt_ctz = operator_i == ibex_pkg_ALU_CTZ; - assign bitcnt_clz = operator_i == ibex_pkg_ALU_CLZ; - assign bitcnt_cz = bitcnt_ctz | bitcnt_clz; - assign bitcnt_result = bitcnt_partial[0+:6]; - assign bitcnt_mask_op = (bitcnt_clz ? operand_a_rev : operand_a_i); - always @(*) begin - bitcnt_bit_mask = bitcnt_mask_op; - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 1); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 2); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 4); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 8); - bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 16); - bitcnt_bit_mask = ~bitcnt_bit_mask; - end - assign zbe_op = (operator_i == ibex_pkg_ALU_BEXT) | (operator_i == ibex_pkg_ALU_BDEP); - always @(*) - case (1'b1) - zbe_op: bitcnt_bits = operand_b_i; - bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; - default: bitcnt_bits = operand_a_i; - endcase - always @(*) begin - bitcnt_partial = {32 {6'b000000}}; - begin : sv2v_autoblock_7 - reg [31:0] i; - for (i = 1; i < 32; i = i + 2) - bitcnt_partial[(31 - i) * 6+:6] = {5'h00, bitcnt_bits[i]} + {5'h00, bitcnt_bits[i - 1]}; - end - begin : sv2v_autoblock_8 - reg [31:0] i; - for (i = 3; i < 32; i = i + 4) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_9 - reg [31:0] i; - for (i = 7; i < 32; i = i + 8) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_10 - reg [31:0] i; - for (i = 15; i < 32; i = i + 16) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(39 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - bitcnt_partial[0+:6] = bitcnt_partial[96+:6] + bitcnt_partial[0+:6]; - bitcnt_partial[48+:6] = bitcnt_partial[96+:6] + bitcnt_partial[48+:6]; - begin : sv2v_autoblock_11 - reg [31:0] i; - for (i = 11; i < 32; i = i + 8) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - begin : sv2v_autoblock_12 - reg [31:0] i; - for (i = 5; i < 32; i = i + 4) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; - end - bitcnt_partial[186+:6] = {5'h00, bitcnt_bits[0]}; - begin : sv2v_autoblock_13 - reg [31:0] i; - for (i = 2; i < 32; i = i + 2) - bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(32 - i) * 6+:6] + {5'h00, bitcnt_bits[i]}; - end - end - assign minmax_result = (cmp_result ? operand_a_i : operand_b_i); - wire packu; - wire packh; - assign packu = operator_i == ibex_pkg_ALU_PACKU; - assign packh = operator_i == ibex_pkg_ALU_PACKH; - always @(*) - case (1'b1) - packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]}; - packh: pack_result = {16'h0000, operand_b_i[7:0], operand_a_i[7:0]}; - default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]}; - endcase - assign sext_result = (operator_i == ibex_pkg_ALU_SEXTB ? {{24 {operand_a_i[7]}}, operand_a_i[7:0]} : {{16 {operand_a_i[15]}}, operand_a_i[15:0]}); - always @(*) - case (operator_i) - ibex_pkg_ALU_SBSET: singlebit_result = operand_a_i | shift_result; - ibex_pkg_ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; - ibex_pkg_ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; - default: singlebit_result = {31'h00000000, shift_result[0]}; - endcase - wire [4:0] zbp_shift_amt; - wire gorc_op; - assign gorc_op = operator_i == ibex_pkg_ALU_GORC; - assign zbp_shift_amt[2:0] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[2:0] : {3 {&shift_amt[2:0]}}); - assign zbp_shift_amt[4:3] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[4:3] : {2 {&shift_amt[4:3]}}); - always @(*) begin - rev_result = operand_a_i; - if (zbp_shift_amt[0]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h55555555) << 1)) | ((rev_result & 32'haaaaaaaa) >> 1); - if (zbp_shift_amt[1]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h33333333) << 2)) | ((rev_result & 32'hcccccccc) >> 2); - if (zbp_shift_amt[2]) - rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h0f0f0f0f) << 4)) | ((rev_result & 32'hf0f0f0f0) >> 4); - if (zbp_shift_amt[3]) - rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h00ff00ff) << 8)) | ((rev_result & 32'hff00ff00) >> 8); - if (zbp_shift_amt[4]) - rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h0000ffff) << 16)) | ((rev_result & 32'hffff0000) >> 16); - end - wire crc_hmode; - wire crc_bmode; - wire [31:0] clmul_result_rev; - if (RV32B == ibex_pkg_RV32BFull) begin : gen_alu_rvb_full - localparam [127:0] SHUFFLE_MASK_L = {32'h00ff0000, 32'h0f000f00, 32'h30303030, 32'h44444444}; - localparam [127:0] SHUFFLE_MASK_R = {32'h0000ff00, 32'h00f000f0, 32'h0c0c0c0c, 32'h22222222}; - localparam [127:0] FLIP_MASK_L = {32'h22001100, 32'h00440000, 32'h44110000, 32'h11000000}; - localparam [127:0] FLIP_MASK_R = {32'h00880044, 32'h00002200, 32'h00008822, 32'h00000088}; - wire [31:0] SHUFFLE_MASK_NOT [0:3]; - for (i = 0; i < 4; i = i + 1) begin : gen_shuffle_mask_not - assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[(3 - i) * 32+:32] | SHUFFLE_MASK_R[(3 - i) * 32+:32]); - end - wire shuffle_flip; - assign shuffle_flip = operator_i == ibex_pkg_ALU_UNSHFL; - reg [3:0] shuffle_mode; - always @(*) begin - shuffle_result = operand_a_i; - if (shuffle_flip) begin - shuffle_mode[3] = shift_amt[0]; - shuffle_mode[2] = shift_amt[1]; - shuffle_mode[1] = shift_amt[2]; - shuffle_mode[0] = shift_amt[3]; - end - else - shuffle_mode = shift_amt[3:0]; - if (shuffle_flip) - shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); - if (shuffle_mode[3]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | (((shuffle_result << 8) & SHUFFLE_MASK_L[96+:32]) | ((shuffle_result >> 8) & SHUFFLE_MASK_R[96+:32])); - if (shuffle_mode[2]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | (((shuffle_result << 4) & SHUFFLE_MASK_L[64+:32]) | ((shuffle_result >> 4) & SHUFFLE_MASK_R[64+:32])); - if (shuffle_mode[1]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | (((shuffle_result << 2) & SHUFFLE_MASK_L[32+:32]) | ((shuffle_result >> 2) & SHUFFLE_MASK_R[32+:32])); - if (shuffle_mode[0]) - shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | (((shuffle_result << 1) & SHUFFLE_MASK_L[0+:32]) | ((shuffle_result >> 1) & SHUFFLE_MASK_R[0+:32])); - if (shuffle_flip) - shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); - end - reg [191:0] bitcnt_partial_q; - for (i = 0; i < 32; i = i + 1) begin : gen_bitcnt_reg_in_lsb - assign bitcnt_partial_lsb_d[i] = bitcnt_partial[(31 - i) * 6]; - end - for (i = 0; i < 16; i = i + 1) begin : gen_bitcnt_reg_in_b1 - assign bitcnt_partial_msb_d[i] = bitcnt_partial[((31 - ((2 * i) + 1)) * 6) + 1]; - end - for (i = 0; i < 8; i = i + 1) begin : gen_bitcnt_reg_in_b2 - assign bitcnt_partial_msb_d[16 + i] = bitcnt_partial[((31 - ((4 * i) + 3)) * 6) + 2]; - end - for (i = 0; i < 4; i = i + 1) begin : gen_bitcnt_reg_in_b3 - assign bitcnt_partial_msb_d[24 + i] = bitcnt_partial[((31 - ((8 * i) + 7)) * 6) + 3]; - end - for (i = 0; i < 2; i = i + 1) begin : gen_bitcnt_reg_in_b4 - assign bitcnt_partial_msb_d[28 + i] = bitcnt_partial[((31 - ((16 * i) + 15)) * 6) + 4]; - end - assign bitcnt_partial_msb_d[30] = bitcnt_partial[5]; - assign bitcnt_partial_msb_d[31] = 1'b0; - always @(*) begin - bitcnt_partial_q = {32 {6'b000000}}; - begin : sv2v_autoblock_14 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_bitcnt_reg_out_lsb - bitcnt_partial_q[(31 - i) * 6] = imd_val_q_i[32 + i]; - end - end - begin : sv2v_autoblock_15 - reg [31:0] i; - for (i = 0; i < 16; i = i + 1) - begin : gen_bitcnt_reg_out_b1 - bitcnt_partial_q[((31 - ((2 * i) + 1)) * 6) + 1] = imd_val_q_i[i]; - end - end - begin : sv2v_autoblock_16 - reg [31:0] i; - for (i = 0; i < 8; i = i + 1) - begin : gen_bitcnt_reg_out_b2 - bitcnt_partial_q[((31 - ((4 * i) + 3)) * 6) + 2] = imd_val_q_i[16 + i]; - end - end - begin : sv2v_autoblock_17 - reg [31:0] i; - for (i = 0; i < 4; i = i + 1) - begin : gen_bitcnt_reg_out_b3 - bitcnt_partial_q[((31 - ((8 * i) + 7)) * 6) + 3] = imd_val_q_i[24 + i]; - end - end - begin : sv2v_autoblock_18 - reg [31:0] i; - for (i = 0; i < 2; i = i + 1) - begin : gen_bitcnt_reg_out_b4 - bitcnt_partial_q[((31 - ((16 * i) + 15)) * 6) + 4] = imd_val_q_i[28 + i]; - end - end - bitcnt_partial_q[5] = imd_val_q_i[30]; - end - wire [31:0] butterfly_mask_l [0:4]; - wire [31:0] butterfly_mask_r [0:4]; - wire [31:0] butterfly_mask_not [0:4]; - wire [31:0] lrotc_stage [0:4]; - genvar stg; - for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_ctrl_stage - genvar seg; - for (seg = 0; seg < (2 ** stg); seg = seg + 1) begin : gen_butterfly_ctrl - assign lrotc_stage[stg][((2 * (16 >> stg)) * (seg + 1)) - 1:(2 * (16 >> stg)) * seg] = {{16 >> stg {1'b0}}, {16 >> stg {1'b1}}} << bitcnt_partial_q[((32 - ((16 >> stg) * ((2 * seg) + 1))) * 6) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) : ($clog2(16 >> stg) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))) - 1)-:($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))]; - assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; - assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; - assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = {((((16 >> stg) * ((2 * seg) + 1)) - 1) >= ((16 >> stg) * (2 * seg)) ? ((((16 >> stg) * ((2 * seg) + 1)) - 1) - ((16 >> stg) * (2 * seg))) + 1 : (((16 >> stg) * (2 * seg)) - (((16 >> stg) * ((2 * seg) + 1)) - 1)) + 1) {1'sb0}}; - assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = {((((16 >> stg) * ((2 * seg) + 2)) - 1) >= ((16 >> stg) * ((2 * seg) + 1)) ? ((((16 >> stg) * ((2 * seg) + 2)) - 1) - ((16 >> stg) * ((2 * seg) + 1))) + 1 : (((16 >> stg) * ((2 * seg) + 1)) - (((16 >> stg) * ((2 * seg) + 2)) - 1)) + 1) {1'sb0}}; - end - end - for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_not - assign butterfly_mask_not[stg] = ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]); - end - always @(*) begin - butterfly_result = operand_a_i; - butterfly_result = ((butterfly_result & butterfly_mask_not[0]) | ((butterfly_result & butterfly_mask_l[0]) >> 16)) | ((butterfly_result & butterfly_mask_r[0]) << 16); - butterfly_result = ((butterfly_result & butterfly_mask_not[1]) | ((butterfly_result & butterfly_mask_l[1]) >> 8)) | ((butterfly_result & butterfly_mask_r[1]) << 8); - butterfly_result = ((butterfly_result & butterfly_mask_not[2]) | ((butterfly_result & butterfly_mask_l[2]) >> 4)) | ((butterfly_result & butterfly_mask_r[2]) << 4); - butterfly_result = ((butterfly_result & butterfly_mask_not[3]) | ((butterfly_result & butterfly_mask_l[3]) >> 2)) | ((butterfly_result & butterfly_mask_r[3]) << 2); - butterfly_result = ((butterfly_result & butterfly_mask_not[4]) | ((butterfly_result & butterfly_mask_l[4]) >> 1)) | ((butterfly_result & butterfly_mask_r[4]) << 1); - butterfly_result = butterfly_result & operand_b_i; - end - always @(*) begin - invbutterfly_result = operand_a_i & operand_b_i; - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[4]) | ((invbutterfly_result & butterfly_mask_l[4]) >> 1)) | ((invbutterfly_result & butterfly_mask_r[4]) << 1); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[3]) | ((invbutterfly_result & butterfly_mask_l[3]) >> 2)) | ((invbutterfly_result & butterfly_mask_r[3]) << 2); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[2]) | ((invbutterfly_result & butterfly_mask_l[2]) >> 4)) | ((invbutterfly_result & butterfly_mask_r[2]) << 4); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[1]) | ((invbutterfly_result & butterfly_mask_l[1]) >> 8)) | ((invbutterfly_result & butterfly_mask_r[1]) << 8); - invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[0]) | ((invbutterfly_result & butterfly_mask_l[0]) >> 16)) | ((invbutterfly_result & butterfly_mask_r[0]) << 16); - end - wire clmul_rmode; - wire clmul_hmode; - reg [31:0] clmul_op_a; - reg [31:0] clmul_op_b; - wire [31:0] operand_b_rev; - wire [31:0] clmul_and_stage [0:31]; - wire [31:0] clmul_xor_stage1 [0:15]; - wire [31:0] clmul_xor_stage2 [0:7]; - wire [31:0] clmul_xor_stage3 [0:3]; - wire [31:0] clmul_xor_stage4 [0:1]; - wire [31:0] clmul_result_raw; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_operand_b - assign operand_b_rev[i] = operand_b_i[31 - i]; - end - assign clmul_rmode = operator_i == ibex_pkg_ALU_CLMULR; - assign clmul_hmode = operator_i == ibex_pkg_ALU_CLMULH; - localparam [31:0] CRC32_POLYNOMIAL = 32'h04c11db7; - localparam [31:0] CRC32_MU_REV = 32'hf7011641; - localparam [31:0] CRC32C_POLYNOMIAL = 32'h1edc6f41; - localparam [31:0] CRC32C_MU_REV = 32'hdea713f1; - wire crc_op; - wire crc_cpoly; - reg [31:0] crc_operand; - wire [31:0] crc_poly; - wire [31:0] crc_mu_rev; - assign crc_op = (((((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32_W)) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B)) | (operator_i == ibex_pkg_ALU_CRC32_B); - assign crc_cpoly = ((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B); - assign crc_hmode = (operator_i == ibex_pkg_ALU_CRC32_H) | (operator_i == ibex_pkg_ALU_CRC32C_H); - assign crc_bmode = (operator_i == ibex_pkg_ALU_CRC32_B) | (operator_i == ibex_pkg_ALU_CRC32C_B); - assign crc_poly = (crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL); - assign crc_mu_rev = (crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV); - always @(*) - case (1'b1) - crc_bmode: crc_operand = {operand_a_i[7:0], 24'h000000}; - crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0000}; - default: crc_operand = operand_a_i; - endcase - always @(*) - if (crc_op) begin - clmul_op_a = (instr_first_cycle_i ? crc_operand : imd_val_q_i[32+:32]); - clmul_op_b = (instr_first_cycle_i ? crc_mu_rev : crc_poly); - end - else begin - clmul_op_a = (clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i); - clmul_op_b = (clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i); - end - for (i = 0; i < 32; i = i + 1) begin : gen_clmul_and_op - assign clmul_and_stage[i] = (clmul_op_b[i] ? clmul_op_a << i : {32 {1'sb0}}); - end - for (i = 0; i < 16; i = i + 1) begin : gen_clmul_xor_op_l1 - assign clmul_xor_stage1[i] = clmul_and_stage[2 * i] ^ clmul_and_stage[(2 * i) + 1]; - end - for (i = 0; i < 8; i = i + 1) begin : gen_clmul_xor_op_l2 - assign clmul_xor_stage2[i] = clmul_xor_stage1[2 * i] ^ clmul_xor_stage1[(2 * i) + 1]; - end - for (i = 0; i < 4; i = i + 1) begin : gen_clmul_xor_op_l3 - assign clmul_xor_stage3[i] = clmul_xor_stage2[2 * i] ^ clmul_xor_stage2[(2 * i) + 1]; - end - for (i = 0; i < 2; i = i + 1) begin : gen_clmul_xor_op_l4 - assign clmul_xor_stage4[i] = clmul_xor_stage3[2 * i] ^ clmul_xor_stage3[(2 * i) + 1]; - end - assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1]; - for (i = 0; i < 32; i = i + 1) begin : gen_rev_clmul_result - assign clmul_result_rev[i] = clmul_result_raw[31 - i]; - end - always @(*) - case (1'b1) - clmul_rmode: clmul_result = clmul_result_rev; - clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]}; - default: clmul_result = clmul_result_raw; - endcase - end - else begin : gen_alu_rvb_notfull - wire [31:0] unused_imd_val_q_1; - assign unused_imd_val_q_1 = imd_val_q_i[0+:32]; - wire [32:1] sv2v_tmp_8C42B; - assign sv2v_tmp_8C42B = {32 {1'sb0}}; - always @(*) shuffle_result = sv2v_tmp_8C42B; - wire [32:1] sv2v_tmp_B0AD4; - assign sv2v_tmp_B0AD4 = {32 {1'sb0}}; - always @(*) butterfly_result = sv2v_tmp_B0AD4; - wire [32:1] sv2v_tmp_AFC2C; - assign sv2v_tmp_AFC2C = {32 {1'sb0}}; - always @(*) invbutterfly_result = sv2v_tmp_AFC2C; - wire [32:1] sv2v_tmp_3A741; - assign sv2v_tmp_3A741 = {32 {1'sb0}}; - always @(*) clmul_result = sv2v_tmp_3A741; - assign bitcnt_partial_lsb_d = {32 {1'sb0}}; - assign bitcnt_partial_msb_d = {32 {1'sb0}}; - assign clmul_result_rev = {32 {1'sb0}}; - assign crc_bmode = 1'b0; - assign crc_hmode = 1'b0; - end - always @(*) - case (operator_i) - ibex_pkg_ALU_CMOV: begin - multicycle_result = (operand_b_i == 32'h00000000 ? operand_a_i : imd_val_q_i[32+:32]); - imd_val_d_o = {operand_a_i, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_CMIX: begin - multicycle_result = imd_val_q_i[32+:32] | bwlogic_and_result; - imd_val_d_o = {bwlogic_and_result, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_FSR, ibex_pkg_ALU_FSL, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR: begin - if (shift_amt[4:0] == 5'h00) - multicycle_result = (shift_amt[5] ? operand_a_i : imd_val_q_i[32+:32]); - else - multicycle_result = imd_val_q_i[32+:32] | shift_result; - imd_val_d_o = {shift_result, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B: - if (RV32B == ibex_pkg_RV32BFull) begin - case (1'b1) - crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8); - crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16); - default: multicycle_result = clmul_result_rev; - endcase - imd_val_d_o = {clmul_result_rev, 32'h00000000}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b01; - else - imd_val_we_o = 2'b00; - end - else begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP: - if (RV32B == ibex_pkg_RV32BFull) begin - multicycle_result = (operator_i == ibex_pkg_ALU_BDEP ? butterfly_result : invbutterfly_result); - imd_val_d_o = {bitcnt_partial_lsb_d, bitcnt_partial_msb_d}; - if (instr_first_cycle_i) - imd_val_we_o = 2'b11; - else - imd_val_we_o = 2'b00; - end - else begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - default: begin - imd_val_d_o = {operand_a_i, 32'h00000000}; - imd_val_we_o = 2'b00; - multicycle_result = {32 {1'sb0}}; - end - endcase - end - else begin : g_no_alu_rvb - wire [63:0] unused_imd_val_q; - assign unused_imd_val_q = imd_val_q_i; - wire [31:0] unused_butterfly_result; - assign unused_butterfly_result = butterfly_result; - wire [31:0] unused_invbutterfly_result; - assign unused_invbutterfly_result = invbutterfly_result; - assign bitcnt_result = {6 {1'sb0}}; - assign minmax_result = {32 {1'sb0}}; - wire [32:1] sv2v_tmp_68181; - assign sv2v_tmp_68181 = {32 {1'sb0}}; - always @(*) pack_result = sv2v_tmp_68181; - assign sext_result = {32 {1'sb0}}; - wire [32:1] sv2v_tmp_D756E; - assign sv2v_tmp_D756E = {32 {1'sb0}}; - always @(*) singlebit_result = sv2v_tmp_D756E; - wire [32:1] sv2v_tmp_BAAB3; - assign sv2v_tmp_BAAB3 = {32 {1'sb0}}; - always @(*) rev_result = sv2v_tmp_BAAB3; - wire [32:1] sv2v_tmp_8C42B; - assign sv2v_tmp_8C42B = {32 {1'sb0}}; - always @(*) shuffle_result = sv2v_tmp_8C42B; - wire [32:1] sv2v_tmp_B0AD4; - assign sv2v_tmp_B0AD4 = {32 {1'sb0}}; - always @(*) butterfly_result = sv2v_tmp_B0AD4; - wire [32:1] sv2v_tmp_AFC2C; - assign sv2v_tmp_AFC2C = {32 {1'sb0}}; - always @(*) invbutterfly_result = sv2v_tmp_AFC2C; - wire [32:1] sv2v_tmp_3A741; - assign sv2v_tmp_3A741 = {32 {1'sb0}}; - always @(*) clmul_result = sv2v_tmp_3A741; - wire [32:1] sv2v_tmp_172E8; - assign sv2v_tmp_172E8 = {32 {1'sb0}}; - always @(*) multicycle_result = sv2v_tmp_172E8; - wire [64:1] sv2v_tmp_CAB3F; - assign sv2v_tmp_CAB3F = {2 {32'b00000000000000000000000000000000}}; - always @(*) imd_val_d_o = sv2v_tmp_CAB3F; - wire [2:1] sv2v_tmp_B65CC; - assign sv2v_tmp_B65CC = {2 {1'b0}}; - always @(*) imd_val_we_o = sv2v_tmp_B65CC; - end - endgenerate - localparam [5:0] ibex_pkg_ALU_ADD = 0; - localparam [5:0] ibex_pkg_ALU_CLMUL = 50; - localparam [5:0] ibex_pkg_ALU_GREV = 15; - localparam [5:0] ibex_pkg_ALU_PACK = 29; - localparam [5:0] ibex_pkg_ALU_PCNT = 36; - localparam [5:0] ibex_pkg_ALU_SBEXT = 46; - localparam [5:0] ibex_pkg_ALU_SEXTH = 33; - localparam [5:0] ibex_pkg_ALU_SHFL = 17; - localparam [5:0] ibex_pkg_ALU_SRL = 9; - localparam [5:0] ibex_pkg_ALU_XOR = 2; - always @(*) begin - result_o = {32 {1'sb0}}; - case (operator_i) - ibex_pkg_ALU_XOR, ibex_pkg_ALU_XNOR, ibex_pkg_ALU_OR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_AND, ibex_pkg_ALU_ANDN: result_o = bwlogic_result; - ibex_pkg_ALU_ADD, ibex_pkg_ALU_SUB: result_o = adder_result; - ibex_pkg_ALU_SLL, ibex_pkg_ALU_SRL, ibex_pkg_ALU_SRA, ibex_pkg_ALU_SLO, ibex_pkg_ALU_SRO: result_o = shift_result; - ibex_pkg_ALU_SHFL, ibex_pkg_ALU_UNSHFL: result_o = shuffle_result; - ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: result_o = {31'h00000000, cmp_result}; - ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAXU: result_o = minmax_result; - ibex_pkg_ALU_CLZ, ibex_pkg_ALU_CTZ, ibex_pkg_ALU_PCNT: result_o = {26'h0000000, bitcnt_result}; - ibex_pkg_ALU_PACK, ibex_pkg_ALU_PACKH, ibex_pkg_ALU_PACKU: result_o = pack_result; - ibex_pkg_ALU_SEXTB, ibex_pkg_ALU_SEXTH: result_o = sext_result; - ibex_pkg_ALU_CMIX, ibex_pkg_ALU_CMOV, ibex_pkg_ALU_FSL, ibex_pkg_ALU_FSR, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR, ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B, ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP: result_o = multicycle_result; - ibex_pkg_ALU_SBSET, ibex_pkg_ALU_SBCLR, ibex_pkg_ALU_SBINV, ibex_pkg_ALU_SBEXT: result_o = singlebit_result; - ibex_pkg_ALU_GREV, ibex_pkg_ALU_GORC: result_o = rev_result; - ibex_pkg_ALU_BFP: result_o = bfp_result; - ibex_pkg_ALU_CLMUL, ibex_pkg_ALU_CLMULR, ibex_pkg_ALU_CLMULH: result_o = clmul_result; - default: - ; - endcase - end - wire unused_shift_amt_compl; - assign unused_shift_amt_compl = shift_amt_compl[5]; -endmodule diff --git a/flow/designs/src/ibex/ibex_branch_predict.v b/flow/designs/src/ibex/ibex_branch_predict.v deleted file mode 100644 index 1a54f2e099..0000000000 --- a/flow/designs/src/ibex/ibex_branch_predict.v +++ /dev/null @@ -1,53 +0,0 @@ -module ibex_branch_predict ( - clk_i, - rst_ni, - fetch_rdata_i, - fetch_pc_i, - fetch_valid_i, - predict_branch_taken_o, - predict_branch_pc_o -); - input wire clk_i; - input wire rst_ni; - input wire [31:0] fetch_rdata_i; - input wire [31:0] fetch_pc_i; - input wire fetch_valid_i; - output wire predict_branch_taken_o; - output wire [31:0] predict_branch_pc_o; - wire [31:0] imm_j_type; - wire [31:0] imm_b_type; - wire [31:0] imm_cj_type; - wire [31:0] imm_cb_type; - reg [31:0] branch_imm; - wire [31:0] instr; - wire instr_j; - wire instr_b; - wire instr_cj; - wire instr_cb; - wire instr_b_taken; - assign instr = fetch_rdata_i; - assign imm_j_type = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; - assign imm_b_type = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - assign imm_cj_type = {{20 {instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0}; - assign imm_cb_type = {{23 {instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0}; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - assign instr_b = instr[6:0] == ibex_pkg_OPCODE_BRANCH; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - assign instr_j = instr[6:0] == ibex_pkg_OPCODE_JAL; - assign instr_cb = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b110) | (instr[15:13] == 3'b111)); - assign instr_cj = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b101) | (instr[15:13] == 3'b001)); - always @(*) begin - branch_imm = imm_b_type; - case (1'b1) - instr_j: branch_imm = imm_j_type; - instr_b: branch_imm = imm_b_type; - instr_cj: branch_imm = imm_cj_type; - instr_cb: branch_imm = imm_cb_type; - default: - ; - endcase - end - assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]); - assign predict_branch_taken_o = fetch_valid_i & ((instr_j | instr_cj) | instr_b_taken); - assign predict_branch_pc_o = fetch_pc_i + branch_imm; -endmodule diff --git a/flow/designs/src/ibex/ibex_compressed_decoder.v b/flow/designs/src/ibex/ibex_compressed_decoder.v deleted file mode 100644 index 1321aa0948..0000000000 --- a/flow/designs/src/ibex/ibex_compressed_decoder.v +++ /dev/null @@ -1,115 +0,0 @@ -module ibex_compressed_decoder ( - clk_i, - rst_ni, - valid_i, - instr_i, - instr_o, - is_compressed_o, - illegal_instr_o -); - input wire clk_i; - input wire rst_ni; - input wire valid_i; - input wire [31:0] instr_i; - output reg [31:0] instr_o; - output wire is_compressed_o; - output reg illegal_instr_o; - wire unused_valid; - assign unused_valid = valid_i; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67; - localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03; - localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37; - localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33; - localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13; - localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23; - always @(*) begin - instr_o = instr_i; - illegal_instr_o = 1'b0; - case (instr_i[1:0]) - 2'b00: - case (instr_i[15:13]) - 3'b000: begin - instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12:5] == 8'b00000000) - illegal_instr_o = 1'b1; - end - 3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_LOAD}}; - 3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, {ibex_pkg_OPCODE_STORE}}; - 3'b001, 3'b011, 3'b100, 3'b101, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - 2'b01: - case (instr_i[15:13]) - 3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - 3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], {ibex_pkg_OPCODE_JAL}}; - 3'b010: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - 3'b011: begin - instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {ibex_pkg_OPCODE_LUI}}; - if (instr_i[11:7] == 5'h02) - instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, {ibex_pkg_OPCODE_OP_IMM}}; - if ({instr_i[12], instr_i[6:2]} == 6'b000000) - illegal_instr_o = 1'b1; - end - 3'b100: - case (instr_i[11:10]) - 2'b00, 2'b01: begin - instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12] == 1'b1) - illegal_instr_o = 1'b1; - end - 2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}}; - 2'b11: - case ({instr_i[12], instr_i[6:5]}) - 3'b000: instr_o = {2'b01, 5'b00000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b001: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b010: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b011: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}}; - 3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - default: illegal_instr_o = 1'b1; - endcase - 3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], {ibex_pkg_OPCODE_BRANCH}}; - default: illegal_instr_o = 1'b1; - endcase - 2'b10: - case (instr_i[15:13]) - 3'b000: begin - instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}}; - if (instr_i[12] == 1'b1) - illegal_instr_o = 1'b1; - end - 3'b010: begin - instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], ibex_pkg_OPCODE_LOAD}; - if (instr_i[11:7] == 5'b00000) - illegal_instr_o = 1'b1; - end - 3'b100: - if (instr_i[12] == 1'b0) begin - if (instr_i[6:2] != 5'b00000) - instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}}; - else begin - instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, {ibex_pkg_OPCODE_JALR}}; - if (instr_i[11:7] == 5'b00000) - illegal_instr_o = 1'b1; - end - end - else if (instr_i[6:2] != 5'b00000) - instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}}; - else if (instr_i[11:7] == 5'b00000) - instr_o = 32'h00100073; - else - instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, {ibex_pkg_OPCODE_JALR}}; - 3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, {ibex_pkg_OPCODE_STORE}}; - 3'b001, 3'b011, 3'b101, 3'b111: illegal_instr_o = 1'b1; - default: illegal_instr_o = 1'b1; - endcase - 2'b11: - ; - default: illegal_instr_o = 1'b1; - endcase - end - assign is_compressed_o = instr_i[1:0] != 2'b11; -endmodule diff --git a/flow/designs/src/ibex/ibex_controller.v b/flow/designs/src/ibex/ibex_controller.v deleted file mode 100644 index 6b4388e039..0000000000 --- a/flow/designs/src/ibex/ibex_controller.v +++ /dev/null @@ -1,579 +0,0 @@ -module ibex_controller ( - clk_i, - rst_ni, - ctrl_busy_o, - illegal_insn_i, - ecall_insn_i, - mret_insn_i, - dret_insn_i, - wfi_insn_i, - ebrk_insn_i, - csr_pipe_flush_i, - instr_valid_i, - instr_i, - instr_compressed_i, - instr_is_compressed_i, - instr_bp_taken_i, - instr_fetch_err_i, - instr_fetch_err_plus2_i, - pc_id_i, - instr_valid_clear_o, - id_in_ready_o, - controller_run_o, - instr_req_o, - pc_set_o, - pc_set_spec_o, - pc_mux_o, - nt_branch_mispredict_o, - exc_pc_mux_o, - exc_cause_o, - lsu_addr_last_i, - load_err_i, - store_err_i, - wb_exception_o, - branch_set_i, - branch_set_spec_i, - branch_not_set_i, - jump_set_i, - csr_mstatus_mie_i, - irq_pending_i, - irqs_i, - irq_nm_i, - nmi_mode_o, - debug_req_i, - debug_cause_o, - debug_csr_save_o, - debug_mode_o, - debug_single_step_i, - debug_ebreakm_i, - debug_ebreaku_i, - trigger_match_i, - csr_save_if_o, - csr_save_id_o, - csr_save_wb_o, - csr_restore_mret_id_o, - csr_restore_dret_id_o, - csr_save_cause_o, - csr_mtval_o, - priv_mode_i, - csr_mstatus_tw_i, - stall_id_i, - stall_wb_i, - flush_id_o, - ready_wb_i, - perf_jump_o, - perf_tbranch_o -); - parameter [0:0] WritebackStage = 0; - parameter [0:0] BranchPredictor = 0; - input wire clk_i; - input wire rst_ni; - output reg ctrl_busy_o; - input wire illegal_insn_i; - input wire ecall_insn_i; - input wire mret_insn_i; - input wire dret_insn_i; - input wire wfi_insn_i; - input wire ebrk_insn_i; - input wire csr_pipe_flush_i; - input wire instr_valid_i; - input wire [31:0] instr_i; - input wire [15:0] instr_compressed_i; - input wire instr_is_compressed_i; - input wire instr_bp_taken_i; - input wire instr_fetch_err_i; - input wire instr_fetch_err_plus2_i; - input wire [31:0] pc_id_i; - output wire instr_valid_clear_o; - output wire id_in_ready_o; - output reg controller_run_o; - output reg instr_req_o; - output reg pc_set_o; - output reg pc_set_spec_o; - output reg [2:0] pc_mux_o; - output reg nt_branch_mispredict_o; - output reg [1:0] exc_pc_mux_o; - output reg [5:0] exc_cause_o; - input wire [31:0] lsu_addr_last_i; - input wire load_err_i; - input wire store_err_i; - output wire wb_exception_o; - input wire branch_set_i; - input wire branch_set_spec_i; - input wire branch_not_set_i; - input wire jump_set_i; - input wire csr_mstatus_mie_i; - input wire irq_pending_i; - input wire [17:0] irqs_i; - input wire irq_nm_i; - output wire nmi_mode_o; - input wire debug_req_i; - output reg [2:0] debug_cause_o; - output reg debug_csr_save_o; - output wire debug_mode_o; - input wire debug_single_step_i; - input wire debug_ebreakm_i; - input wire debug_ebreaku_i; - input wire trigger_match_i; - output reg csr_save_if_o; - output reg csr_save_id_o; - output reg csr_save_wb_o; - output reg csr_restore_mret_id_o; - output reg csr_restore_dret_id_o; - output reg csr_save_cause_o; - output reg [31:0] csr_mtval_o; - input wire [1:0] priv_mode_i; - input wire csr_mstatus_tw_i; - input wire stall_id_i; - input wire stall_wb_i; - output wire flush_id_o; - input wire ready_wb_i; - output reg perf_jump_o; - output reg perf_tbranch_o; - reg [3:0] ctrl_fsm_cs; - reg [3:0] ctrl_fsm_ns; - reg nmi_mode_q; - reg nmi_mode_d; - reg debug_mode_q; - reg debug_mode_d; - reg load_err_q; - wire load_err_d; - reg store_err_q; - wire store_err_d; - reg exc_req_q; - wire exc_req_d; - reg illegal_insn_q; - wire illegal_insn_d; - reg instr_fetch_err_prio; - reg illegal_insn_prio; - reg ecall_insn_prio; - reg ebrk_insn_prio; - reg store_err_prio; - reg load_err_prio; - wire stall; - reg halt_if; - reg retain_id; - reg flush_id; - wire illegal_dret; - wire illegal_umode; - wire exc_req_lsu; - wire special_req_all; - wire special_req_branch; - wire enter_debug_mode; - wire ebreak_into_debug; - wire handle_irq; - reg [3:0] mfip_id; - wire unused_irq_timer; - wire ecall_insn; - wire mret_insn; - wire dret_insn; - wire wfi_insn; - wire ebrk_insn; - wire csr_pipe_flush; - wire instr_fetch_err; - assign load_err_d = load_err_i; - assign store_err_d = store_err_i; - assign ecall_insn = ecall_insn_i & instr_valid_i; - assign mret_insn = mret_insn_i & instr_valid_i; - assign dret_insn = dret_insn_i & instr_valid_i; - assign wfi_insn = wfi_insn_i & instr_valid_i; - assign ebrk_insn = ebrk_insn_i & instr_valid_i; - assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; - assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; - assign illegal_dret = dret_insn & ~debug_mode_q; - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - assign illegal_umode = (priv_mode_i != ibex_pkg_PRIV_LVL_M) & (mret_insn | (csr_mstatus_tw_i & wfi_insn)); - localparam [3:0] FLUSH = 6; - assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != FLUSH); - assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != FLUSH); - assign exc_req_lsu = store_err_i | load_err_i; - assign special_req_all = ((((mret_insn | dret_insn) | wfi_insn) | csr_pipe_flush) | exc_req_d) | exc_req_lsu; - assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); - generate - if (WritebackStage) begin : g_wb_exceptions - always @(*) begin - instr_fetch_err_prio = 0; - illegal_insn_prio = 0; - ecall_insn_prio = 0; - ebrk_insn_prio = 0; - store_err_prio = 0; - load_err_prio = 0; - if (store_err_q) - store_err_prio = 1'b1; - else if (load_err_q) - load_err_prio = 1'b1; - else if (instr_fetch_err) - instr_fetch_err_prio = 1'b1; - else if (illegal_insn_q) - illegal_insn_prio = 1'b1; - else if (ecall_insn) - ecall_insn_prio = 1'b1; - else if (ebrk_insn) - ebrk_insn_prio = 1'b1; - end - assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i; - end - else begin : g_no_wb_exceptions - always @(*) begin - instr_fetch_err_prio = 0; - illegal_insn_prio = 0; - ecall_insn_prio = 0; - ebrk_insn_prio = 0; - store_err_prio = 0; - load_err_prio = 0; - if (instr_fetch_err) - instr_fetch_err_prio = 1'b1; - else if (illegal_insn_q) - illegal_insn_prio = 1'b1; - else if (ecall_insn) - ecall_insn_prio = 1'b1; - else if (ebrk_insn) - ebrk_insn_prio = 1'b1; - else if (store_err_q) - store_err_prio = 1'b1; - else if (load_err_q) - load_err_prio = 1'b1; - end - assign wb_exception_o = 1'b0; - end - endgenerate - assign enter_debug_mode = ((debug_req_i | (debug_single_step_i & instr_valid_i)) | trigger_match_i) & ~debug_mode_q; - localparam [1:0] ibex_pkg_PRIV_LVL_U = 2'b00; - assign ebreak_into_debug = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? debug_ebreakm_i : (priv_mode_i == ibex_pkg_PRIV_LVL_U ? debug_ebreaku_i : 1'b0)); - assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); - always @(*) begin : gen_mfip_id - if (irqs_i[14]) - mfip_id = 4'd14; - else if (irqs_i[13]) - mfip_id = 4'd13; - else if (irqs_i[12]) - mfip_id = 4'd12; - else if (irqs_i[11]) - mfip_id = 4'd11; - else if (irqs_i[10]) - mfip_id = 4'd10; - else if (irqs_i[9]) - mfip_id = 4'd9; - else if (irqs_i[8]) - mfip_id = 4'd8; - else if (irqs_i[7]) - mfip_id = 4'd7; - else if (irqs_i[6]) - mfip_id = 4'd6; - else if (irqs_i[5]) - mfip_id = 4'd5; - else if (irqs_i[4]) - mfip_id = 4'd4; - else if (irqs_i[3]) - mfip_id = 4'd3; - else if (irqs_i[2]) - mfip_id = 4'd2; - else if (irqs_i[1]) - mfip_id = 4'd1; - else - mfip_id = 4'd0; - end - assign unused_irq_timer = irqs_i[16]; - localparam [3:0] BOOT_SET = 1; - localparam [3:0] DBG_TAKEN_ID = 9; - localparam [3:0] DBG_TAKEN_IF = 8; - localparam [3:0] DECODE = 5; - localparam [3:0] FIRST_FETCH = 4; - localparam [3:0] IRQ_TAKEN = 7; - localparam [3:0] RESET = 0; - localparam [3:0] SLEEP = 3; - localparam [3:0] WAIT_SLEEP = 2; - localparam [2:0] ibex_pkg_DBG_CAUSE_EBREAK = 3'h1; - localparam [2:0] ibex_pkg_DBG_CAUSE_HALTREQ = 3'h3; - localparam [2:0] ibex_pkg_DBG_CAUSE_STEP = 3'h4; - localparam [2:0] ibex_pkg_DBG_CAUSE_TRIGGER = 3'h2; - localparam [5:0] ibex_pkg_EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; - localparam [5:0] ibex_pkg_EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; - localparam [5:0] ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; - localparam [5:0] ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; - localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; - localparam [5:0] ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; - localparam [5:0] ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; - localparam [1:0] ibex_pkg_EXC_PC_DBD = 2; - localparam [1:0] ibex_pkg_EXC_PC_DBG_EXC = 3; - localparam [1:0] ibex_pkg_EXC_PC_EXC = 0; - localparam [1:0] ibex_pkg_EXC_PC_IRQ = 1; - localparam [2:0] ibex_pkg_PC_BOOT = 0; - localparam [2:0] ibex_pkg_PC_DRET = 4; - localparam [2:0] ibex_pkg_PC_ERET = 3; - localparam [2:0] ibex_pkg_PC_EXC = 2; - localparam [2:0] ibex_pkg_PC_JUMP = 1; - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - always @(*) begin - instr_req_o = 1'b1; - csr_save_if_o = 1'b0; - csr_save_id_o = 1'b0; - csr_save_wb_o = 1'b0; - csr_restore_mret_id_o = 1'b0; - csr_restore_dret_id_o = 1'b0; - csr_save_cause_o = 1'b0; - csr_mtval_o = {32 {1'sb0}}; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b0; - pc_set_spec_o = 1'b0; - nt_branch_mispredict_o = 1'b0; - exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ; - exc_cause_o = ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA; - ctrl_fsm_ns = ctrl_fsm_cs; - ctrl_busy_o = 1'b1; - halt_if = 1'b0; - retain_id = 1'b0; - flush_id = 1'b0; - debug_csr_save_o = 1'b0; - debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK; - debug_mode_d = debug_mode_q; - nmi_mode_d = nmi_mode_q; - perf_tbranch_o = 1'b0; - perf_jump_o = 1'b0; - controller_run_o = 1'b0; - case (ctrl_fsm_cs) - RESET: begin - instr_req_o = 1'b0; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - ctrl_fsm_ns = BOOT_SET; - end - BOOT_SET: begin - instr_req_o = 1'b1; - pc_mux_o = ibex_pkg_PC_BOOT; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - ctrl_fsm_ns = FIRST_FETCH; - end - WAIT_SLEEP: begin - ctrl_busy_o = 1'b0; - instr_req_o = 1'b0; - halt_if = 1'b1; - flush_id = 1'b1; - ctrl_fsm_ns = SLEEP; - end - SLEEP: begin - instr_req_o = 1'b0; - halt_if = 1'b1; - flush_id = 1'b1; - if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i) - ctrl_fsm_ns = FIRST_FETCH; - else - ctrl_busy_o = 1'b0; - end - FIRST_FETCH: begin - if (id_in_ready_o) - ctrl_fsm_ns = DECODE; - if (handle_irq) begin - ctrl_fsm_ns = IRQ_TAKEN; - halt_if = 1'b1; - end - if (enter_debug_mode) begin - ctrl_fsm_ns = DBG_TAKEN_IF; - halt_if = 1'b1; - end - end - DECODE: begin - controller_run_o = 1'b1; - pc_mux_o = ibex_pkg_PC_JUMP; - if (special_req_all) begin - retain_id = 1'b1; - if (ready_wb_i | wb_exception_o) - ctrl_fsm_ns = FLUSH; - end - if (!special_req_branch) begin - if (branch_set_i || jump_set_i) begin - pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); - perf_tbranch_o = branch_set_i; - perf_jump_o = jump_set_i; - end - if (BranchPredictor) - if (instr_bp_taken_i & branch_not_set_i) - nt_branch_mispredict_o = 1'b1; - end - if ((branch_set_spec_i || jump_set_i) && !special_req_branch) - pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); - if ((enter_debug_mode || handle_irq) && stall) - halt_if = 1'b1; - if (!stall && !special_req_all) - if (enter_debug_mode) begin - ctrl_fsm_ns = DBG_TAKEN_IF; - halt_if = 1'b1; - end - else if (handle_irq) begin - ctrl_fsm_ns = IRQ_TAKEN; - halt_if = 1'b1; - end - end - IRQ_TAKEN: begin - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ; - if (handle_irq) begin - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_save_if_o = 1'b1; - csr_save_cause_o = 1'b1; - if (irq_nm_i && !nmi_mode_q) begin - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_NM; - nmi_mode_d = 1'b1; - end - else if (irqs_i[14-:15] != 15'b000000000000000) - exc_cause_o = sv2v_cast_6({2'b11, mfip_id}); - else if (irqs_i[15]) - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M; - else if (irqs_i[17]) - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M; - else - exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_TIMER_M; - end - ctrl_fsm_ns = DECODE; - end - DBG_TAKEN_IF: begin - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = ibex_pkg_EXC_PC_DBD; - if ((debug_single_step_i || debug_req_i) || trigger_match_i) begin - flush_id = 1'b1; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_save_if_o = 1'b1; - debug_csr_save_o = 1'b1; - csr_save_cause_o = 1'b1; - if (trigger_match_i) - debug_cause_o = ibex_pkg_DBG_CAUSE_TRIGGER; - else if (debug_single_step_i) - debug_cause_o = ibex_pkg_DBG_CAUSE_STEP; - else - debug_cause_o = ibex_pkg_DBG_CAUSE_HALTREQ; - debug_mode_d = 1'b1; - end - ctrl_fsm_ns = DECODE; - end - DBG_TAKEN_ID: begin - flush_id = 1'b1; - pc_mux_o = ibex_pkg_PC_EXC; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - exc_pc_mux_o = ibex_pkg_EXC_PC_DBD; - if (ebreak_into_debug && !debug_mode_q) begin - csr_save_cause_o = 1'b1; - csr_save_id_o = 1'b1; - debug_csr_save_o = 1'b1; - debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK; - end - debug_mode_d = 1'b1; - ctrl_fsm_ns = DECODE; - end - FLUSH: begin - halt_if = 1'b1; - flush_id = 1'b1; - ctrl_fsm_ns = DECODE; - if ((exc_req_q || store_err_q) || load_err_q) begin - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - pc_mux_o = ibex_pkg_PC_EXC; - exc_pc_mux_o = (debug_mode_q ? ibex_pkg_EXC_PC_DBG_EXC : ibex_pkg_EXC_PC_EXC); - if (WritebackStage) begin : g_writeback_mepc_save - csr_save_id_o = ~(store_err_q | load_err_q); - csr_save_wb_o = store_err_q | load_err_q; - end - else begin : g_no_writeback_mepc_save - csr_save_id_o = 1'b0; - end - csr_save_cause_o = 1'b1; - case (1'b1) - instr_fetch_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT; - csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i); - end - illegal_insn_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_ILLEGAL_INSN; - csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i); - end - ecall_insn_prio: exc_cause_o = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? ibex_pkg_EXC_CAUSE_ECALL_MMODE : ibex_pkg_EXC_CAUSE_ECALL_UMODE); - ebrk_insn_prio: - if (debug_mode_q | ebreak_into_debug) begin - pc_set_o = 1'b0; - pc_set_spec_o = 1'b0; - csr_save_id_o = 1'b0; - csr_save_cause_o = 1'b0; - ctrl_fsm_ns = DBG_TAKEN_ID; - flush_id = 1'b0; - end - else - exc_cause_o = ibex_pkg_EXC_CAUSE_BREAKPOINT; - store_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT; - csr_mtval_o = lsu_addr_last_i; - end - load_err_prio: begin - exc_cause_o = ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT; - csr_mtval_o = lsu_addr_last_i; - end - default: - ; - endcase - end - else if (mret_insn) begin - pc_mux_o = ibex_pkg_PC_ERET; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - csr_restore_mret_id_o = 1'b1; - if (nmi_mode_q) - nmi_mode_d = 1'b0; - end - else if (dret_insn) begin - pc_mux_o = ibex_pkg_PC_DRET; - pc_set_o = 1'b1; - pc_set_spec_o = 1'b1; - debug_mode_d = 1'b0; - csr_restore_dret_id_o = 1'b1; - end - else if (wfi_insn) - ctrl_fsm_ns = WAIT_SLEEP; - else if (csr_pipe_flush && handle_irq) - ctrl_fsm_ns = IRQ_TAKEN; - if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) - ctrl_fsm_ns = DBG_TAKEN_IF; - end - default: begin - instr_req_o = 1'b0; - ctrl_fsm_ns = RESET; - end - endcase - end - assign flush_id_o = flush_id; - assign debug_mode_o = debug_mode_q; - assign nmi_mode_o = nmi_mode_q; - assign stall = stall_id_i | stall_wb_i; - assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id; - assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; - always @(posedge clk_i or negedge rst_ni) begin : update_regs - if (!rst_ni) begin - ctrl_fsm_cs <= RESET; - nmi_mode_q <= 1'b0; - debug_mode_q <= 1'b0; - load_err_q <= 1'b0; - store_err_q <= 1'b0; - exc_req_q <= 1'b0; - illegal_insn_q <= 1'b0; - end - else begin - ctrl_fsm_cs <= ctrl_fsm_ns; - nmi_mode_q <= nmi_mode_d; - debug_mode_q <= debug_mode_d; - load_err_q <= load_err_d; - store_err_q <= store_err_d; - exc_req_q <= exc_req_d; - illegal_insn_q <= illegal_insn_d; - end - end -endmodule diff --git a/flow/designs/src/ibex/ibex_core.v b/flow/designs/src/ibex/ibex_core.v deleted file mode 100644 index 79d926cca0..0000000000 --- a/flow/designs/src/ibex/ibex_core.v +++ /dev/null @@ -1,782 +0,0 @@ -module ibex_core ( - clk_i, - rst_ni, - test_en_i, - hart_id_i, - boot_addr_i, - instr_req_o, - instr_gnt_i, - instr_rvalid_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_we_o, - data_be_o, - data_addr_o, - data_wdata_o, - data_rdata_i, - data_err_i, - irq_software_i, - irq_timer_i, - irq_external_i, - irq_fast_i, - irq_nm_i, - debug_req_i, - fetch_enable_i, - alert_minor_o, - alert_major_o, - core_sleep_o -); - parameter [0:0] PMPEnable = 1'b0; - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumRegions = 4; - parameter [31:0] MHPMCounterNum = 0; - parameter [31:0] MHPMCounterWidth = 40; - parameter [0:0] RV32E = 1'b0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - localparam integer ibex_pkg_RegFileFF = 0; - parameter integer RegFile = ibex_pkg_RegFileFF; - parameter [0:0] BranchTargetALU = 1'b0; - parameter [0:0] WritebackStage = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [0:0] ICacheECC = 1'b0; - parameter [0:0] BranchPredictor = 1'b0; - parameter [0:0] DbgTriggerEn = 1'b0; - parameter [31:0] DbgHwBreakNum = 1; - parameter [0:0] SecureIbex = 1'b0; - parameter [31:0] DmHaltAddr = 32'h1a110800; - parameter [31:0] DmExceptionAddr = 32'h1a110808; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire [31:0] hart_id_i; - input wire [31:0] boot_addr_i; - output wire instr_req_o; - input wire instr_gnt_i; - input wire instr_rvalid_i; - output wire [31:0] instr_addr_o; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - output wire data_req_o; - input wire data_gnt_i; - input wire data_rvalid_i; - output wire data_we_o; - output wire [3:0] data_be_o; - output wire [31:0] data_addr_o; - output wire [31:0] data_wdata_o; - input wire [31:0] data_rdata_i; - input wire data_err_i; - input wire irq_software_i; - input wire irq_timer_i; - input wire irq_external_i; - input wire [14:0] irq_fast_i; - input wire irq_nm_i; - input wire debug_req_i; - input wire fetch_enable_i; - output wire alert_minor_o; - output wire alert_major_o; - output wire core_sleep_o; - localparam [31:0] PMP_NUM_CHAN = 2; - localparam [0:0] DataIndTiming = SecureIbex; - localparam [0:0] DummyInstructions = SecureIbex; - localparam [0:0] PCIncrCheck = SecureIbex; - localparam [0:0] ShadowCSR = SecureIbex; - localparam [0:0] SpecBranch = PMPEnable & (PMPNumRegions == 16); - localparam [0:0] RegFileECC = SecureIbex; - localparam [31:0] RegFileDataWidth = (RegFileECC ? 39 : 32); - wire dummy_instr_id; - wire instr_valid_id; - wire instr_new_id; - wire [31:0] instr_rdata_id; - wire [31:0] instr_rdata_alu_id; - wire [15:0] instr_rdata_c_id; - wire instr_is_compressed_id; - wire instr_perf_count_id; - wire instr_bp_taken_id; - wire instr_fetch_err; - wire instr_fetch_err_plus2; - wire illegal_c_insn_id; - wire [31:0] pc_if; - wire [31:0] pc_id; - wire [31:0] pc_wb; - wire [67:0] imd_val_d_ex; - wire [67:0] imd_val_q_ex; - wire [1:0] imd_val_we_ex; - wire data_ind_timing; - wire dummy_instr_en; - wire [2:0] dummy_instr_mask; - wire dummy_instr_seed_en; - wire [31:0] dummy_instr_seed; - wire icache_enable; - wire icache_inval; - wire pc_mismatch_alert; - wire csr_shadow_err; - wire instr_first_cycle_id; - wire instr_valid_clear; - wire pc_set; - wire pc_set_spec; - wire nt_branch_mispredict; - wire [2:0] pc_mux_id; - wire [1:0] exc_pc_mux_id; - wire [5:0] exc_cause; - wire lsu_load_err; - wire lsu_store_err; - wire lsu_addr_incr_req; - wire [31:0] lsu_addr_last; - wire [31:0] branch_target_ex; - wire branch_decision; - wire ctrl_busy; - wire if_busy; - wire lsu_busy; - wire core_busy_d; - reg core_busy_q; - wire [4:0] rf_raddr_a; - wire [31:0] rf_rdata_a; - wire [4:0] rf_raddr_b; - wire [31:0] rf_rdata_b; - wire rf_ren_a; - wire rf_ren_b; - wire [4:0] rf_waddr_wb; - wire [31:0] rf_wdata_wb; - wire [31:0] rf_wdata_fwd_wb; - wire [31:0] rf_wdata_lsu; - wire rf_we_wb; - wire rf_we_lsu; - wire [4:0] rf_waddr_id; - wire [31:0] rf_wdata_id; - wire rf_we_id; - wire rf_rd_a_wb_match; - wire rf_rd_b_wb_match; - wire [5:0] alu_operator_ex; - wire [31:0] alu_operand_a_ex; - wire [31:0] alu_operand_b_ex; - wire [31:0] bt_a_operand; - wire [31:0] bt_b_operand; - wire [31:0] alu_adder_result_ex; - wire [31:0] result_ex; - wire mult_en_ex; - wire div_en_ex; - wire mult_sel_ex; - wire div_sel_ex; - wire [1:0] multdiv_operator_ex; - wire [1:0] multdiv_signed_mode_ex; - wire [31:0] multdiv_operand_a_ex; - wire [31:0] multdiv_operand_b_ex; - wire multdiv_ready_id; - wire csr_access; - wire [1:0] csr_op; - wire csr_op_en; - wire [11:0] csr_addr; - wire [31:0] csr_rdata; - wire [31:0] csr_wdata; - wire illegal_csr_insn_id; - wire lsu_we; - wire [1:0] lsu_type; - wire lsu_sign_ext; - wire lsu_req; - wire [31:0] lsu_wdata; - wire lsu_req_done; - wire id_in_ready; - wire ex_valid; - wire lsu_resp_valid; - wire lsu_resp_err; - wire instr_req_int; - wire en_wb; - wire [1:0] instr_type_wb; - wire ready_wb; - wire rf_write_wb; - wire outstanding_load_wb; - wire outstanding_store_wb; - wire irq_pending; - wire nmi_mode; - wire [17:0] irqs; - wire csr_mstatus_mie; - wire [31:0] csr_mepc; - wire [31:0] csr_depc; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg; - wire [0:PMP_NUM_CHAN - 1] pmp_req_err; - wire instr_req_out; - wire data_req_out; - wire csr_save_if; - wire csr_save_id; - wire csr_save_wb; - wire csr_restore_mret_id; - wire csr_restore_dret_id; - wire csr_save_cause; - wire csr_mtvec_init; - wire [31:0] csr_mtvec; - wire [31:0] csr_mtval; - wire csr_mstatus_tw; - wire [1:0] priv_mode_id; - wire [1:0] priv_mode_if; - wire [1:0] priv_mode_lsu; - wire debug_mode; - wire [2:0] debug_cause; - wire debug_csr_save; - wire debug_single_step; - wire debug_ebreakm; - wire debug_ebreaku; - wire trigger_match; - wire instr_id_done; - wire instr_done_wb; - wire perf_instr_ret_wb; - wire perf_instr_ret_compressed_wb; - wire perf_iside_wait; - wire perf_dside_wait; - wire perf_mul_wait; - wire perf_div_wait; - wire perf_jump; - wire perf_branch; - wire perf_tbranch; - wire perf_load; - wire perf_store; - wire illegal_insn_id; - wire unused_illegal_insn_id; - wire clk; - wire clock_en; - assign core_busy_d = (ctrl_busy | if_busy) | lsu_busy; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - core_busy_q <= 1'b0; - else - core_busy_q <= core_busy_d; - reg fetch_enable_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - fetch_enable_q <= 1'b0; - else if (fetch_enable_i) - fetch_enable_q <= 1'b1; - assign clock_en = fetch_enable_q & (((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i); - assign core_sleep_o = ~clock_en; - prim_clock_gating core_clock_gate_i( - .clk_i(clk_i), - .en_i(clock_en), - .test_en_i(test_en_i), - .clk_o(clk) - ); - localparam [31:0] ibex_pkg_PMP_I = 0; - ibex_if_stage #( - .DmHaltAddr(DmHaltAddr), - .DmExceptionAddr(DmExceptionAddr), - .DummyInstructions(DummyInstructions), - .ICache(ICache), - .ICacheECC(ICacheECC), - .PCIncrCheck(PCIncrCheck), - .BranchPredictor(BranchPredictor) - ) if_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .boot_addr_i(boot_addr_i), - .req_i(instr_req_int), - .instr_req_o(instr_req_out), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(pmp_req_err[ibex_pkg_PMP_I]), - .instr_valid_id_o(instr_valid_id), - .instr_new_id_o(instr_new_id), - .instr_rdata_id_o(instr_rdata_id), - .instr_rdata_alu_id_o(instr_rdata_alu_id), - .instr_rdata_c_id_o(instr_rdata_c_id), - .instr_is_compressed_id_o(instr_is_compressed_id), - .instr_bp_taken_o(instr_bp_taken_id), - .instr_fetch_err_o(instr_fetch_err), - .instr_fetch_err_plus2_o(instr_fetch_err_plus2), - .illegal_c_insn_id_o(illegal_c_insn_id), - .dummy_instr_id_o(dummy_instr_id), - .pc_if_o(pc_if), - .pc_id_o(pc_id), - .instr_valid_clear_i(instr_valid_clear), - .pc_set_i(pc_set), - .pc_set_spec_i(pc_set_spec), - .pc_mux_i(pc_mux_id), - .nt_branch_mispredict_i(nt_branch_mispredict), - .exc_pc_mux_i(exc_pc_mux_id), - .exc_cause(exc_cause), - .dummy_instr_en_i(dummy_instr_en), - .dummy_instr_mask_i(dummy_instr_mask), - .dummy_instr_seed_en_i(dummy_instr_seed_en), - .dummy_instr_seed_i(dummy_instr_seed), - .icache_enable_i(icache_enable), - .icache_inval_i(icache_inval), - .branch_target_ex_i(branch_target_ex), - .csr_mepc_i(csr_mepc), - .csr_depc_i(csr_depc), - .csr_mtvec_i(csr_mtvec), - .csr_mtvec_init_o(csr_mtvec_init), - .id_in_ready_i(id_in_ready), - .pc_mismatch_alert_o(pc_mismatch_alert), - .if_busy_o(if_busy) - ); - assign perf_iside_wait = id_in_ready & ~instr_valid_id; - assign instr_req_o = instr_req_out & ~pmp_req_err[ibex_pkg_PMP_I]; - ibex_id_stage #( - .RV32E(RV32E), - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU), - .DataIndTiming(DataIndTiming), - .SpecBranch(SpecBranch), - .WritebackStage(WritebackStage), - .BranchPredictor(BranchPredictor) - ) id_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .ctrl_busy_o(ctrl_busy), - .illegal_insn_o(illegal_insn_id), - .instr_valid_i(instr_valid_id), - .instr_rdata_i(instr_rdata_id), - .instr_rdata_alu_i(instr_rdata_alu_id), - .instr_rdata_c_i(instr_rdata_c_id), - .instr_is_compressed_i(instr_is_compressed_id), - .instr_bp_taken_i(instr_bp_taken_id), - .branch_decision_i(branch_decision), - .instr_first_cycle_id_o(instr_first_cycle_id), - .instr_valid_clear_o(instr_valid_clear), - .id_in_ready_o(id_in_ready), - .instr_req_o(instr_req_int), - .pc_set_o(pc_set), - .pc_set_spec_o(pc_set_spec), - .pc_mux_o(pc_mux_id), - .nt_branch_mispredict_o(nt_branch_mispredict), - .exc_pc_mux_o(exc_pc_mux_id), - .exc_cause_o(exc_cause), - .icache_inval_o(icache_inval), - .instr_fetch_err_i(instr_fetch_err), - .instr_fetch_err_plus2_i(instr_fetch_err_plus2), - .illegal_c_insn_i(illegal_c_insn_id), - .pc_id_i(pc_id), - .ex_valid_i(ex_valid), - .lsu_resp_valid_i(lsu_resp_valid), - .alu_operator_ex_o(alu_operator_ex), - .alu_operand_a_ex_o(alu_operand_a_ex), - .alu_operand_b_ex_o(alu_operand_b_ex), - .imd_val_q_ex_o(imd_val_q_ex), - .imd_val_d_ex_i(imd_val_d_ex), - .imd_val_we_ex_i(imd_val_we_ex), - .bt_a_operand_o(bt_a_operand), - .bt_b_operand_o(bt_b_operand), - .mult_en_ex_o(mult_en_ex), - .div_en_ex_o(div_en_ex), - .mult_sel_ex_o(mult_sel_ex), - .div_sel_ex_o(div_sel_ex), - .multdiv_operator_ex_o(multdiv_operator_ex), - .multdiv_signed_mode_ex_o(multdiv_signed_mode_ex), - .multdiv_operand_a_ex_o(multdiv_operand_a_ex), - .multdiv_operand_b_ex_o(multdiv_operand_b_ex), - .multdiv_ready_id_o(multdiv_ready_id), - .csr_access_o(csr_access), - .csr_op_o(csr_op), - .csr_op_en_o(csr_op_en), - .csr_save_if_o(csr_save_if), - .csr_save_id_o(csr_save_id), - .csr_save_wb_o(csr_save_wb), - .csr_restore_mret_id_o(csr_restore_mret_id), - .csr_restore_dret_id_o(csr_restore_dret_id), - .csr_save_cause_o(csr_save_cause), - .csr_mtval_o(csr_mtval), - .priv_mode_i(priv_mode_id), - .csr_mstatus_tw_i(csr_mstatus_tw), - .illegal_csr_insn_i(illegal_csr_insn_id), - .data_ind_timing_i(data_ind_timing), - .lsu_req_o(lsu_req), - .lsu_we_o(lsu_we), - .lsu_type_o(lsu_type), - .lsu_sign_ext_o(lsu_sign_ext), - .lsu_wdata_o(lsu_wdata), - .lsu_req_done_i(lsu_req_done), - .lsu_addr_incr_req_i(lsu_addr_incr_req), - .lsu_addr_last_i(lsu_addr_last), - .lsu_load_err_i(lsu_load_err), - .lsu_store_err_i(lsu_store_err), - .csr_mstatus_mie_i(csr_mstatus_mie), - .irq_pending_i(irq_pending), - .irqs_i(irqs), - .irq_nm_i(irq_nm_i), - .nmi_mode_o(nmi_mode), - .debug_mode_o(debug_mode), - .debug_cause_o(debug_cause), - .debug_csr_save_o(debug_csr_save), - .debug_req_i(debug_req_i), - .debug_single_step_i(debug_single_step), - .debug_ebreakm_i(debug_ebreakm), - .debug_ebreaku_i(debug_ebreaku), - .trigger_match_i(trigger_match), - .result_ex_i(result_ex), - .csr_rdata_i(csr_rdata), - .rf_raddr_a_o(rf_raddr_a), - .rf_rdata_a_i(rf_rdata_a), - .rf_raddr_b_o(rf_raddr_b), - .rf_rdata_b_i(rf_rdata_b), - .rf_ren_a_o(rf_ren_a), - .rf_ren_b_o(rf_ren_b), - .rf_waddr_id_o(rf_waddr_id), - .rf_wdata_id_o(rf_wdata_id), - .rf_we_id_o(rf_we_id), - .rf_rd_a_wb_match_o(rf_rd_a_wb_match), - .rf_rd_b_wb_match_o(rf_rd_b_wb_match), - .rf_waddr_wb_i(rf_waddr_wb), - .rf_wdata_fwd_wb_i(rf_wdata_fwd_wb), - .rf_write_wb_i(rf_write_wb), - .en_wb_o(en_wb), - .instr_type_wb_o(instr_type_wb), - .instr_perf_count_id_o(instr_perf_count_id), - .ready_wb_i(ready_wb), - .outstanding_load_wb_i(outstanding_load_wb), - .outstanding_store_wb_i(outstanding_store_wb), - .perf_jump_o(perf_jump), - .perf_branch_o(perf_branch), - .perf_tbranch_o(perf_tbranch), - .perf_dside_wait_o(perf_dside_wait), - .perf_mul_wait_o(perf_mul_wait), - .perf_div_wait_o(perf_div_wait), - .instr_id_done_o(instr_id_done) - ); - assign unused_illegal_insn_id = illegal_insn_id; - ibex_ex_block #( - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU) - ) ex_block_i( - .clk_i(clk), - .rst_ni(rst_ni), - .alu_operator_i(alu_operator_ex), - .alu_operand_a_i(alu_operand_a_ex), - .alu_operand_b_i(alu_operand_b_ex), - .alu_instr_first_cycle_i(instr_first_cycle_id), - .bt_a_operand_i(bt_a_operand), - .bt_b_operand_i(bt_b_operand), - .multdiv_operator_i(multdiv_operator_ex), - .mult_en_i(mult_en_ex), - .div_en_i(div_en_ex), - .mult_sel_i(mult_sel_ex), - .div_sel_i(div_sel_ex), - .multdiv_signed_mode_i(multdiv_signed_mode_ex), - .multdiv_operand_a_i(multdiv_operand_a_ex), - .multdiv_operand_b_i(multdiv_operand_b_ex), - .multdiv_ready_id_i(multdiv_ready_id), - .data_ind_timing_i(data_ind_timing), - .imd_val_we_o(imd_val_we_ex), - .imd_val_d_o(imd_val_d_ex), - .imd_val_q_i(imd_val_q_ex), - .alu_adder_result_ex_o(alu_adder_result_ex), - .result_ex_o(result_ex), - .branch_target_o(branch_target_ex), - .branch_decision_o(branch_decision), - .ex_valid_o(ex_valid) - ); - localparam [31:0] ibex_pkg_PMP_D = 1; - assign data_req_o = data_req_out & ~pmp_req_err[ibex_pkg_PMP_D]; - assign lsu_resp_err = lsu_load_err | lsu_store_err; - ibex_load_store_unit load_store_unit_i( - .clk_i(clk), - .rst_ni(rst_ni), - .data_req_o(data_req_out), - .data_gnt_i(data_gnt_i), - .data_rvalid_i(data_rvalid_i), - .data_err_i(data_err_i), - .data_pmp_err_i(pmp_req_err[ibex_pkg_PMP_D]), - .data_addr_o(data_addr_o), - .data_we_o(data_we_o), - .data_be_o(data_be_o), - .data_wdata_o(data_wdata_o), - .data_rdata_i(data_rdata_i), - .lsu_we_i(lsu_we), - .lsu_type_i(lsu_type), - .lsu_wdata_i(lsu_wdata), - .lsu_sign_ext_i(lsu_sign_ext), - .lsu_rdata_o(rf_wdata_lsu), - .lsu_rdata_valid_o(rf_we_lsu), - .lsu_req_i(lsu_req), - .lsu_req_done_o(lsu_req_done), - .adder_result_ex_i(alu_adder_result_ex), - .addr_incr_req_o(lsu_addr_incr_req), - .addr_last_o(lsu_addr_last), - .lsu_resp_valid_o(lsu_resp_valid), - .load_err_o(lsu_load_err), - .store_err_o(lsu_store_err), - .busy_o(lsu_busy), - .perf_load_o(perf_load), - .perf_store_o(perf_store) - ); - ibex_wb_stage #(.WritebackStage(WritebackStage)) wb_stage_i( - .clk_i(clk), - .rst_ni(rst_ni), - .en_wb_i(en_wb), - .instr_type_wb_i(instr_type_wb), - .pc_id_i(pc_id), - .instr_is_compressed_id_i(instr_is_compressed_id), - .instr_perf_count_id_i(instr_perf_count_id), - .ready_wb_o(ready_wb), - .rf_write_wb_o(rf_write_wb), - .outstanding_load_wb_o(outstanding_load_wb), - .outstanding_store_wb_o(outstanding_store_wb), - .pc_wb_o(pc_wb), - .perf_instr_ret_wb_o(perf_instr_ret_wb), - .perf_instr_ret_compressed_wb_o(perf_instr_ret_compressed_wb), - .rf_waddr_id_i(rf_waddr_id), - .rf_wdata_id_i(rf_wdata_id), - .rf_we_id_i(rf_we_id), - .rf_wdata_lsu_i(rf_wdata_lsu), - .rf_we_lsu_i(rf_we_lsu), - .rf_wdata_fwd_wb_o(rf_wdata_fwd_wb), - .rf_waddr_wb_o(rf_waddr_wb), - .rf_wdata_wb_o(rf_wdata_wb), - .rf_we_wb_o(rf_we_wb), - .lsu_resp_valid_i(lsu_resp_valid), - .lsu_resp_err_i(lsu_resp_err), - .instr_done_wb_o(instr_done_wb) - ); - wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc; - wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc; - wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc; - wire rf_ecc_err_comb; - generate - if (RegFileECC) begin : gen_regfile_ecc - wire [1:0] rf_ecc_err_a; - wire [1:0] rf_ecc_err_b; - wire rf_ecc_err_a_id; - wire rf_ecc_err_b_id; - prim_secded_39_32_enc regfile_ecc_enc( - .in(rf_wdata_wb), - .out(rf_wdata_wb_ecc) - ); - prim_secded_39_32_dec regfile_ecc_dec_a( - .in(rf_rdata_a_ecc), - .d_o(), - .syndrome_o(), - .err_o(rf_ecc_err_a) - ); - prim_secded_39_32_dec regfile_ecc_dec_b( - .in(rf_rdata_b_ecc), - .d_o(), - .syndrome_o(), - .err_o(rf_ecc_err_b) - ); - assign rf_rdata_a = rf_rdata_a_ecc[31:0]; - assign rf_rdata_b = rf_rdata_b_ecc[31:0]; - assign rf_ecc_err_a_id = (|rf_ecc_err_a & rf_ren_a) & ~rf_rd_a_wb_match; - assign rf_ecc_err_b_id = (|rf_ecc_err_b & rf_ren_b) & ~rf_rd_b_wb_match; - assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id); - end - else begin : gen_no_regfile_ecc - wire unused_rf_ren_a; - wire unused_rf_ren_b; - wire unused_rf_rd_a_wb_match; - wire unused_rf_rd_b_wb_match; - assign unused_rf_ren_a = rf_ren_a; - assign unused_rf_ren_b = rf_ren_b; - assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match; - assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match; - assign rf_wdata_wb_ecc = rf_wdata_wb; - assign rf_rdata_a = rf_rdata_a_ecc; - assign rf_rdata_b = rf_rdata_b_ecc; - assign rf_ecc_err_comb = 1'b0; - end - endgenerate - localparam integer ibex_pkg_RegFileFPGA = 1; - localparam integer ibex_pkg_RegFileLatch = 2; - generate - if (RegFile == ibex_pkg_RegFileFF) begin : gen_regfile_ff - ibex_register_file_ff #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - else if (RegFile == ibex_pkg_RegFileFPGA) begin : gen_regfile_fpga - ibex_register_file_fpga #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - else if (RegFile == ibex_pkg_RegFileLatch) begin : gen_regfile_latch - ibex_register_file_latch #( - .RV32E(RV32E), - .DataWidth(RegFileDataWidth), - .DummyInstructions(DummyInstructions) - ) register_file_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .test_en_i(test_en_i), - .dummy_instr_id_i(dummy_instr_id), - .raddr_a_i(rf_raddr_a), - .rdata_a_o(rf_rdata_a_ecc), - .raddr_b_i(rf_raddr_b), - .rdata_b_o(rf_rdata_b_ecc), - .waddr_a_i(rf_waddr_wb), - .wdata_a_i(rf_wdata_wb_ecc), - .we_a_i(rf_we_wb) - ); - end - endgenerate - assign alert_minor_o = 1'b0; - assign alert_major_o = (rf_ecc_err_comb | pc_mismatch_alert) | csr_shadow_err; - assign csr_wdata = alu_operand_a_ex; - function automatic [11:0] sv2v_cast_12; - input reg [11:0] inp; - sv2v_cast_12 = inp; - endfunction - assign csr_addr = sv2v_cast_12((csr_access ? alu_operand_b_ex[11:0] : 12'b000000000000)); - ibex_cs_registers #( - .DbgTriggerEn(DbgTriggerEn), - .DbgHwBreakNum(DbgHwBreakNum), - .DataIndTiming(DataIndTiming), - .DummyInstructions(DummyInstructions), - .ShadowCSR(ShadowCSR), - .ICache(ICache), - .MHPMCounterNum(MHPMCounterNum), - .MHPMCounterWidth(MHPMCounterWidth), - .PMPEnable(PMPEnable), - .PMPGranularity(PMPGranularity), - .PMPNumRegions(PMPNumRegions), - .RV32E(RV32E), - .RV32M(RV32M) - ) cs_registers_i( - .clk_i(clk), - .rst_ni(rst_ni), - .hart_id_i(hart_id_i), - .priv_mode_id_o(priv_mode_id), - .priv_mode_if_o(priv_mode_if), - .priv_mode_lsu_o(priv_mode_lsu), - .csr_mtvec_o(csr_mtvec), - .csr_mtvec_init_i(csr_mtvec_init), - .boot_addr_i(boot_addr_i), - .csr_access_i(csr_access), - .csr_addr_i(csr_addr), - .csr_wdata_i(csr_wdata), - .csr_op_i(csr_op), - .csr_op_en_i(csr_op_en), - .csr_rdata_o(csr_rdata), - .irq_software_i(irq_software_i), - .irq_timer_i(irq_timer_i), - .irq_external_i(irq_external_i), - .irq_fast_i(irq_fast_i), - .nmi_mode_i(nmi_mode), - .irq_pending_o(irq_pending), - .irqs_o(irqs), - .csr_mstatus_mie_o(csr_mstatus_mie), - .csr_mstatus_tw_o(csr_mstatus_tw), - .csr_mepc_o(csr_mepc), - .csr_pmp_cfg_o(csr_pmp_cfg), - .csr_pmp_addr_o(csr_pmp_addr), - .csr_depc_o(csr_depc), - .debug_mode_i(debug_mode), - .debug_cause_i(debug_cause), - .debug_csr_save_i(debug_csr_save), - .debug_single_step_o(debug_single_step), - .debug_ebreakm_o(debug_ebreakm), - .debug_ebreaku_o(debug_ebreaku), - .trigger_match_o(trigger_match), - .pc_if_i(pc_if), - .pc_id_i(pc_id), - .pc_wb_i(pc_wb), - .data_ind_timing_o(data_ind_timing), - .dummy_instr_en_o(dummy_instr_en), - .dummy_instr_mask_o(dummy_instr_mask), - .dummy_instr_seed_en_o(dummy_instr_seed_en), - .dummy_instr_seed_o(dummy_instr_seed), - .icache_enable_o(icache_enable), - .csr_shadow_err_o(csr_shadow_err), - .csr_save_if_i(csr_save_if), - .csr_save_id_i(csr_save_id), - .csr_save_wb_i(csr_save_wb), - .csr_restore_mret_i(csr_restore_mret_id), - .csr_restore_dret_i(csr_restore_dret_id), - .csr_save_cause_i(csr_save_cause), - .csr_mcause_i(exc_cause), - .csr_mtval_i(csr_mtval), - .illegal_csr_insn_o(illegal_csr_insn_id), - .instr_ret_i(perf_instr_ret_wb), - .instr_ret_compressed_i(perf_instr_ret_compressed_wb), - .iside_wait_i(perf_iside_wait), - .jump_i(perf_jump), - .branch_i(perf_branch), - .branch_taken_i(perf_tbranch), - .mem_load_i(perf_load), - .mem_store_i(perf_store), - .dside_wait_i(perf_dside_wait), - .mul_wait_i(perf_mul_wait), - .div_wait_i(perf_div_wait) - ); - localparam [1:0] ibex_pkg_PMP_ACC_EXEC = 2'b00; - localparam [1:0] ibex_pkg_PMP_ACC_READ = 2'b10; - localparam [1:0] ibex_pkg_PMP_ACC_WRITE = 2'b01; - generate - if (PMPEnable) begin : g_pmp - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 34) + (((PMP_NUM_CHAN - 1) * 34) - 1) : (PMP_NUM_CHAN * 34) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 34 : 0)] pmp_req_addr; - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 2) + (((PMP_NUM_CHAN - 1) * 2) - 1) : (PMP_NUM_CHAN * 2) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 2 : 0)] pmp_req_type; - wire [(0 >= (PMP_NUM_CHAN - 1) ? ((2 - PMP_NUM_CHAN) * 2) + (((PMP_NUM_CHAN - 1) * 2) - 1) : (PMP_NUM_CHAN * 2) - 1):(0 >= (PMP_NUM_CHAN - 1) ? (PMP_NUM_CHAN - 1) * 2 : 0)] pmp_priv_lvl; - assign pmp_req_addr[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 34+:34] = {2'b00, instr_addr_o[31:0]}; - assign pmp_req_type[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 2+:2] = ibex_pkg_PMP_ACC_EXEC; - assign pmp_priv_lvl[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_I : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_I) * 2+:2] = priv_mode_if; - assign pmp_req_addr[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 34+:34] = {2'b00, data_addr_o[31:0]}; - assign pmp_req_type[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 2+:2] = (data_we_o ? ibex_pkg_PMP_ACC_WRITE : ibex_pkg_PMP_ACC_READ); - assign pmp_priv_lvl[(0 >= (PMP_NUM_CHAN - 1) ? ibex_pkg_PMP_D : (PMP_NUM_CHAN - 1) - ibex_pkg_PMP_D) * 2+:2] = priv_mode_lsu; - ibex_pmp #( - .PMPGranularity(PMPGranularity), - .PMPNumChan(PMP_NUM_CHAN), - .PMPNumRegions(PMPNumRegions) - ) pmp_i( - .clk_i(clk), - .rst_ni(rst_ni), - .csr_pmp_cfg_i(csr_pmp_cfg), - .csr_pmp_addr_i(csr_pmp_addr), - .priv_mode_i(pmp_priv_lvl), - .pmp_req_addr_i(pmp_req_addr), - .pmp_req_type_i(pmp_req_type), - .pmp_req_err_o(pmp_req_err) - ); - end - else begin : g_no_pmp - wire [1:0] unused_priv_lvl_if; - wire [1:0] unused_priv_lvl_ls; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] unused_csr_pmp_addr; - wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] unused_csr_pmp_cfg; - assign unused_priv_lvl_if = priv_mode_if; - assign unused_priv_lvl_ls = priv_mode_lsu; - assign unused_csr_pmp_addr = csr_pmp_addr; - assign unused_csr_pmp_cfg = csr_pmp_cfg; - assign pmp_req_err[ibex_pkg_PMP_I] = 1'b0; - assign pmp_req_err[ibex_pkg_PMP_D] = 1'b0; - end - endgenerate - wire unused_instr_new_id; - wire unused_instr_done_wb; - assign unused_instr_new_id = instr_new_id; - assign unused_instr_done_wb = instr_done_wb; -endmodule diff --git a/flow/designs/src/ibex/ibex_counter.v b/flow/designs/src/ibex/ibex_counter.v deleted file mode 100644 index 081590ebf1..0000000000 --- a/flow/designs/src/ibex/ibex_counter.v +++ /dev/null @@ -1,57 +0,0 @@ -module ibex_counter ( - clk_i, - rst_ni, - counter_inc_i, - counterh_we_i, - counter_we_i, - counter_val_i, - counter_val_o -); - parameter signed [31:0] CounterWidth = 32; - input wire clk_i; - input wire rst_ni; - input wire counter_inc_i; - input wire counterh_we_i; - input wire counter_we_i; - input wire [31:0] counter_val_i; - output wire [63:0] counter_val_o; - wire [63:0] counter; - reg [CounterWidth - 1:0] counter_upd; - reg [63:0] counter_load; - reg we; - reg [CounterWidth - 1:0] counter_d; - always @(*) begin - we = counter_we_i | counterh_we_i; - counter_load[63:32] = counter[63:32]; - counter_load[31:0] = counter_val_i; - if (counterh_we_i) begin - counter_load[63:32] = counter_val_i; - counter_load[31:0] = counter[31:0]; - end - counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1}; - if (we) - counter_d = counter_load[CounterWidth - 1:0]; - else if (counter_inc_i) - counter_d = counter_upd[CounterWidth - 1:0]; - else - counter_d = counter[CounterWidth - 1:0]; - end - reg [CounterWidth - 1:0] counter_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - counter_q <= {CounterWidth {1'sb0}}; - else - counter_q <= counter_d; - generate - if (CounterWidth < 64) begin : g_counter_narrow - wire [63:CounterWidth] unused_counter_load; - assign counter[CounterWidth - 1:0] = counter_q; - assign counter[63:CounterWidth] = {(63 >= CounterWidth ? 64 - CounterWidth : CounterWidth - 62) {1'sb0}}; - assign unused_counter_load = counter_load[63:CounterWidth]; - end - else begin : g_counter_full - assign counter = counter_q; - end - endgenerate - assign counter_val_o = counter; -endmodule diff --git a/flow/designs/src/ibex/ibex_cs_registers.v b/flow/designs/src/ibex/ibex_cs_registers.v deleted file mode 100644 index 5e7000abd6..0000000000 --- a/flow/designs/src/ibex/ibex_cs_registers.v +++ /dev/null @@ -1,1191 +0,0 @@ -module ibex_cs_registers ( - clk_i, - rst_ni, - hart_id_i, - priv_mode_id_o, - priv_mode_if_o, - priv_mode_lsu_o, - csr_mstatus_tw_o, - csr_mtvec_o, - csr_mtvec_init_i, - boot_addr_i, - csr_access_i, - csr_addr_i, - csr_wdata_i, - csr_op_i, - csr_op_en_i, - csr_rdata_o, - irq_software_i, - irq_timer_i, - irq_external_i, - irq_fast_i, - nmi_mode_i, - irq_pending_o, - irqs_o, - csr_mstatus_mie_o, - csr_mepc_o, - csr_pmp_cfg_o, - csr_pmp_addr_o, - debug_mode_i, - debug_cause_i, - debug_csr_save_i, - csr_depc_o, - debug_single_step_o, - debug_ebreakm_o, - debug_ebreaku_o, - trigger_match_o, - pc_if_i, - pc_id_i, - pc_wb_i, - data_ind_timing_o, - dummy_instr_en_o, - dummy_instr_mask_o, - dummy_instr_seed_en_o, - dummy_instr_seed_o, - icache_enable_o, - csr_shadow_err_o, - csr_save_if_i, - csr_save_id_i, - csr_save_wb_i, - csr_restore_mret_i, - csr_restore_dret_i, - csr_save_cause_i, - csr_mcause_i, - csr_mtval_i, - illegal_csr_insn_o, - instr_ret_i, - instr_ret_compressed_i, - iside_wait_i, - jump_i, - branch_i, - branch_taken_i, - mem_load_i, - mem_store_i, - dside_wait_i, - mul_wait_i, - div_wait_i -); - parameter [0:0] DbgTriggerEn = 0; - parameter [31:0] DbgHwBreakNum = 1; - parameter [0:0] DataIndTiming = 1'b0; - parameter [0:0] DummyInstructions = 1'b0; - parameter [0:0] ShadowCSR = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [31:0] MHPMCounterNum = 10; - parameter [31:0] MHPMCounterWidth = 40; - parameter [0:0] PMPEnable = 0; - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumRegions = 4; - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - input wire clk_i; - input wire rst_ni; - input wire [31:0] hart_id_i; - output wire [1:0] priv_mode_id_o; - output wire [1:0] priv_mode_if_o; - output wire [1:0] priv_mode_lsu_o; - output wire csr_mstatus_tw_o; - output wire [31:0] csr_mtvec_o; - input wire csr_mtvec_init_i; - input wire [31:0] boot_addr_i; - input wire csr_access_i; - input wire [11:0] csr_addr_i; - input wire [31:0] csr_wdata_i; - input wire [1:0] csr_op_i; - input csr_op_en_i; - output wire [31:0] csr_rdata_o; - input wire irq_software_i; - input wire irq_timer_i; - input wire irq_external_i; - input wire [14:0] irq_fast_i; - input wire nmi_mode_i; - output wire irq_pending_o; - output wire [17:0] irqs_o; - output wire csr_mstatus_mie_o; - output wire [31:0] csr_mepc_o; - output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_o; - output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_o; - input wire debug_mode_i; - input wire [2:0] debug_cause_i; - input wire debug_csr_save_i; - output wire [31:0] csr_depc_o; - output wire debug_single_step_o; - output wire debug_ebreakm_o; - output wire debug_ebreaku_o; - output wire trigger_match_o; - input wire [31:0] pc_if_i; - input wire [31:0] pc_id_i; - input wire [31:0] pc_wb_i; - output wire data_ind_timing_o; - output wire dummy_instr_en_o; - output wire [2:0] dummy_instr_mask_o; - output wire dummy_instr_seed_en_o; - output wire [31:0] dummy_instr_seed_o; - output wire icache_enable_o; - output wire csr_shadow_err_o; - input wire csr_save_if_i; - input wire csr_save_id_i; - input wire csr_save_wb_i; - input wire csr_restore_mret_i; - input wire csr_restore_dret_i; - input wire csr_save_cause_i; - input wire [5:0] csr_mcause_i; - input wire [31:0] csr_mtval_i; - output wire illegal_csr_insn_o; - input wire instr_ret_i; - input wire instr_ret_compressed_i; - input wire iside_wait_i; - input wire jump_i; - input wire branch_i; - input wire branch_taken_i; - input wire mem_load_i; - input wire mem_store_i; - input wire dside_wait_i; - input wire mul_wait_i; - input wire div_wait_i; - localparam integer ibex_pkg_RV32MNone = 0; - localparam [31:0] RV32MEnabled = (RV32M == ibex_pkg_RV32MNone ? 0 : 1); - localparam [31:0] PMPAddrWidth = (PMPGranularity > 0 ? 33 - PMPGranularity : 32); - localparam [1:0] ibex_pkg_CSR_MISA_MXL = 2'd1; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - localparam [31:0] MISA_VALUE = ((((((((((0 | 4) | 0) | (sv2v_cast_32(RV32E) << 4)) | 0) | (sv2v_cast_32(!RV32E) << 8)) | (RV32MEnabled << 12)) | 0) | 0) | 1048576) | 0) | (sv2v_cast_32(ibex_pkg_CSR_MISA_MXL) << 30); - reg [31:0] exception_pc; - reg [1:0] priv_lvl_q; - reg [1:0] priv_lvl_d; - wire [5:0] mstatus_q; - reg [5:0] mstatus_d; - wire mstatus_err; - reg mstatus_en; - wire [17:0] mie_q; - wire [17:0] mie_d; - reg mie_en; - wire [31:0] mscratch_q; - reg mscratch_en; - wire [31:0] mepc_q; - reg [31:0] mepc_d; - reg mepc_en; - wire [5:0] mcause_q; - reg [5:0] mcause_d; - reg mcause_en; - wire [31:0] mtval_q; - reg [31:0] mtval_d; - reg mtval_en; - wire [31:0] mtvec_q; - reg [31:0] mtvec_d; - wire mtvec_err; - reg mtvec_en; - wire [17:0] mip; - wire [31:0] dcsr_q; - reg [31:0] dcsr_d; - reg dcsr_en; - wire [31:0] depc_q; - reg [31:0] depc_d; - reg depc_en; - wire [31:0] dscratch0_q; - wire [31:0] dscratch1_q; - reg dscratch0_en; - reg dscratch1_en; - wire [2:0] mstack_q; - reg [2:0] mstack_d; - reg mstack_en; - wire [31:0] mstack_epc_q; - reg [31:0] mstack_epc_d; - wire [5:0] mstack_cause_q; - reg [5:0] mstack_cause_d; - localparam [31:0] ibex_pkg_PMP_MAX_REGIONS = 16; - reg [31:0] pmp_addr_rdata [0:ibex_pkg_PMP_MAX_REGIONS - 1]; - localparam [31:0] ibex_pkg_PMP_CFG_W = 8; - wire [ibex_pkg_PMP_CFG_W - 1:0] pmp_cfg_rdata [0:ibex_pkg_PMP_MAX_REGIONS - 1]; - wire pmp_csr_err; - wire [31:0] mcountinhibit; - reg [MHPMCounterNum + 2:0] mcountinhibit_d; - reg [MHPMCounterNum + 2:0] mcountinhibit_q; - reg mcountinhibit_we; - wire [63:0] mhpmcounter [0:31]; - reg [31:0] mhpmcounter_we; - reg [31:0] mhpmcounterh_we; - reg [31:0] mhpmcounter_incr; - reg [31:0] mhpmevent [0:31]; - wire [4:0] mhpmcounter_idx; - wire unused_mhpmcounter_we_1; - wire unused_mhpmcounterh_we_1; - wire unused_mhpmcounter_incr_1; - wire [31:0] tselect_rdata; - wire [31:0] tmatch_control_rdata; - wire [31:0] tmatch_value_rdata; - wire [5:0] cpuctrl_q; - wire [5:0] cpuctrl_d; - wire [5:0] cpuctrl_wdata; - reg cpuctrl_we; - wire cpuctrl_err; - reg [31:0] csr_wdata_int; - reg [31:0] csr_rdata_int; - wire csr_we_int; - wire csr_wreq; - reg illegal_csr; - wire illegal_csr_priv; - wire illegal_csr_write; - wire [7:0] unused_boot_addr; - wire [2:0] unused_csr_addr; - assign unused_boot_addr = boot_addr_i[7:0]; - wire [11:0] csr_addr; - assign csr_addr = {csr_addr_i}; - assign unused_csr_addr = csr_addr[7:5]; - assign mhpmcounter_idx = csr_addr[4:0]; - assign illegal_csr_priv = csr_addr[9:8] > {priv_lvl_q}; - assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq; - assign illegal_csr_insn_o = csr_access_i & ((illegal_csr | illegal_csr_write) | illegal_csr_priv); - assign mip[17] = irq_software_i; - assign mip[16] = irq_timer_i; - assign mip[15] = irq_external_i; - assign mip[14-:15] = irq_fast_i; - localparam [31:0] ibex_pkg_CSR_MEIX_BIT = 11; - localparam [31:0] ibex_pkg_CSR_MFIX_BIT_HIGH = 30; - localparam [31:0] ibex_pkg_CSR_MFIX_BIT_LOW = 16; - localparam [31:0] ibex_pkg_CSR_MSIX_BIT = 3; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MIE_BIT = 3; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPIE_BIT = 7; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH = 12; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW = 11; - localparam [31:0] ibex_pkg_CSR_MSTATUS_MPRV_BIT = 17; - localparam [31:0] ibex_pkg_CSR_MSTATUS_TW_BIT = 21; - localparam [31:0] ibex_pkg_CSR_MTIX_BIT = 7; - localparam [11:0] ibex_pkg_CSR_CPUCTRL = 12'h7c0; - localparam [11:0] ibex_pkg_CSR_DCSR = 12'h7b0; - localparam [11:0] ibex_pkg_CSR_DPC = 12'h7b1; - localparam [11:0] ibex_pkg_CSR_DSCRATCH0 = 12'h7b2; - localparam [11:0] ibex_pkg_CSR_DSCRATCH1 = 12'h7b3; - localparam [11:0] ibex_pkg_CSR_MCAUSE = 12'h342; - localparam [11:0] ibex_pkg_CSR_MCONTEXT = 12'h7a8; - localparam [11:0] ibex_pkg_CSR_MCOUNTINHIBIT = 12'h320; - localparam [11:0] ibex_pkg_CSR_MCYCLE = 12'hb00; - localparam [11:0] ibex_pkg_CSR_MCYCLEH = 12'hb80; - localparam [11:0] ibex_pkg_CSR_MEPC = 12'h341; - localparam [11:0] ibex_pkg_CSR_MHARTID = 12'hf14; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER10 = 12'hb0a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER10H = 12'hb8a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER11 = 12'hb0b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER11H = 12'hb8b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER12 = 12'hb0c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER12H = 12'hb8c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER13 = 12'hb0d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER13H = 12'hb8d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER14 = 12'hb0e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER14H = 12'hb8e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER15 = 12'hb0f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER15H = 12'hb8f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER16 = 12'hb10; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER16H = 12'hb90; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER17 = 12'hb11; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER17H = 12'hb91; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER18 = 12'hb12; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER18H = 12'hb92; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER19 = 12'hb13; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER19H = 12'hb93; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER20 = 12'hb14; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER20H = 12'hb94; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER21 = 12'hb15; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER21H = 12'hb95; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER22 = 12'hb16; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER22H = 12'hb96; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER23 = 12'hb17; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER23H = 12'hb97; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER24 = 12'hb18; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER24H = 12'hb98; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER25 = 12'hb19; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER25H = 12'hb99; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER26 = 12'hb1a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER26H = 12'hb9a; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER27 = 12'hb1b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER27H = 12'hb9b; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER28 = 12'hb1c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER28H = 12'hb9c; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER29 = 12'hb1d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER29H = 12'hb9d; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER3 = 12'hb03; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER30 = 12'hb1e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER30H = 12'hb9e; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER31 = 12'hb1f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER31H = 12'hb9f; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER3H = 12'hb83; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER4 = 12'hb04; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER4H = 12'hb84; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER5 = 12'hb05; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER5H = 12'hb85; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER6 = 12'hb06; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER6H = 12'hb86; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER7 = 12'hb07; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER7H = 12'hb87; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER8 = 12'hb08; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER8H = 12'hb88; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER9 = 12'hb09; - localparam [11:0] ibex_pkg_CSR_MHPMCOUNTER9H = 12'hb89; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT10 = 12'h32a; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT11 = 12'h32b; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT12 = 12'h32c; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT13 = 12'h32d; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT14 = 12'h32e; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT15 = 12'h32f; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT16 = 12'h330; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT17 = 12'h331; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT18 = 12'h332; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT19 = 12'h333; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT20 = 12'h334; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT21 = 12'h335; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT22 = 12'h336; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT23 = 12'h337; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT24 = 12'h338; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT25 = 12'h339; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT26 = 12'h33a; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT27 = 12'h33b; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT28 = 12'h33c; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT29 = 12'h33d; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT3 = 12'h323; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT30 = 12'h33e; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT31 = 12'h33f; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT4 = 12'h324; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT5 = 12'h325; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT6 = 12'h326; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT7 = 12'h327; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT8 = 12'h328; - localparam [11:0] ibex_pkg_CSR_MHPMEVENT9 = 12'h329; - localparam [11:0] ibex_pkg_CSR_MIE = 12'h304; - localparam [11:0] ibex_pkg_CSR_MINSTRET = 12'hb02; - localparam [11:0] ibex_pkg_CSR_MINSTRETH = 12'hb82; - localparam [11:0] ibex_pkg_CSR_MIP = 12'h344; - localparam [11:0] ibex_pkg_CSR_MISA = 12'h301; - localparam [11:0] ibex_pkg_CSR_MSCRATCH = 12'h340; - localparam [11:0] ibex_pkg_CSR_MSTATUS = 12'h300; - localparam [11:0] ibex_pkg_CSR_MTVAL = 12'h343; - localparam [11:0] ibex_pkg_CSR_MTVEC = 12'h305; - localparam [11:0] ibex_pkg_CSR_PMPADDR0 = 12'h3b0; - localparam [11:0] ibex_pkg_CSR_PMPADDR1 = 12'h3b1; - localparam [11:0] ibex_pkg_CSR_PMPADDR10 = 12'h3ba; - localparam [11:0] ibex_pkg_CSR_PMPADDR11 = 12'h3bb; - localparam [11:0] ibex_pkg_CSR_PMPADDR12 = 12'h3bc; - localparam [11:0] ibex_pkg_CSR_PMPADDR13 = 12'h3bd; - localparam [11:0] ibex_pkg_CSR_PMPADDR14 = 12'h3be; - localparam [11:0] ibex_pkg_CSR_PMPADDR15 = 12'h3bf; - localparam [11:0] ibex_pkg_CSR_PMPADDR2 = 12'h3b2; - localparam [11:0] ibex_pkg_CSR_PMPADDR3 = 12'h3b3; - localparam [11:0] ibex_pkg_CSR_PMPADDR4 = 12'h3b4; - localparam [11:0] ibex_pkg_CSR_PMPADDR5 = 12'h3b5; - localparam [11:0] ibex_pkg_CSR_PMPADDR6 = 12'h3b6; - localparam [11:0] ibex_pkg_CSR_PMPADDR7 = 12'h3b7; - localparam [11:0] ibex_pkg_CSR_PMPADDR8 = 12'h3b8; - localparam [11:0] ibex_pkg_CSR_PMPADDR9 = 12'h3b9; - localparam [11:0] ibex_pkg_CSR_PMPCFG0 = 12'h3a0; - localparam [11:0] ibex_pkg_CSR_PMPCFG1 = 12'h3a1; - localparam [11:0] ibex_pkg_CSR_PMPCFG2 = 12'h3a2; - localparam [11:0] ibex_pkg_CSR_PMPCFG3 = 12'h3a3; - localparam [11:0] ibex_pkg_CSR_SCONTEXT = 12'h7aa; - localparam [11:0] ibex_pkg_CSR_SECURESEED = 12'h7c1; - localparam [11:0] ibex_pkg_CSR_TDATA1 = 12'h7a1; - localparam [11:0] ibex_pkg_CSR_TDATA2 = 12'h7a2; - localparam [11:0] ibex_pkg_CSR_TDATA3 = 12'h7a3; - localparam [11:0] ibex_pkg_CSR_TSELECT = 12'h7a0; - always @(*) begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = 1'b0; - case (csr_addr_i) - ibex_pkg_CSR_MHARTID: csr_rdata_int = hart_id_i; - ibex_pkg_CSR_MSTATUS: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT] = mstatus_q[5]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT] = mstatus_q[4]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q[3-:2]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT] = mstatus_q[1]; - csr_rdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT] = mstatus_q[0]; - end - ibex_pkg_CSR_MISA: csr_rdata_int = MISA_VALUE; - ibex_pkg_CSR_MIE: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mie_q[17]; - csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mie_q[16]; - csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mie_q[15]; - csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mie_q[14-:15]; - end - ibex_pkg_CSR_MSCRATCH: csr_rdata_int = mscratch_q; - ibex_pkg_CSR_MTVEC: csr_rdata_int = mtvec_q; - ibex_pkg_CSR_MEPC: csr_rdata_int = mepc_q; - ibex_pkg_CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b00000000000000000000000000, mcause_q[4:0]}; - ibex_pkg_CSR_MTVAL: csr_rdata_int = mtval_q; - ibex_pkg_CSR_MIP: begin - csr_rdata_int = {32 {1'sb0}}; - csr_rdata_int[ibex_pkg_CSR_MSIX_BIT] = mip[17]; - csr_rdata_int[ibex_pkg_CSR_MTIX_BIT] = mip[16]; - csr_rdata_int[ibex_pkg_CSR_MEIX_BIT] = mip[15]; - csr_rdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW] = mip[14-:15]; - end - ibex_pkg_CSR_PMPCFG0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], pmp_cfg_rdata[1], pmp_cfg_rdata[0]}; - ibex_pkg_CSR_PMPCFG1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], pmp_cfg_rdata[5], pmp_cfg_rdata[4]}; - ibex_pkg_CSR_PMPCFG2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], pmp_cfg_rdata[9], pmp_cfg_rdata[8]}; - ibex_pkg_CSR_PMPCFG3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], pmp_cfg_rdata[13], pmp_cfg_rdata[12]}; - ibex_pkg_CSR_PMPADDR0: csr_rdata_int = pmp_addr_rdata[0]; - ibex_pkg_CSR_PMPADDR1: csr_rdata_int = pmp_addr_rdata[1]; - ibex_pkg_CSR_PMPADDR2: csr_rdata_int = pmp_addr_rdata[2]; - ibex_pkg_CSR_PMPADDR3: csr_rdata_int = pmp_addr_rdata[3]; - ibex_pkg_CSR_PMPADDR4: csr_rdata_int = pmp_addr_rdata[4]; - ibex_pkg_CSR_PMPADDR5: csr_rdata_int = pmp_addr_rdata[5]; - ibex_pkg_CSR_PMPADDR6: csr_rdata_int = pmp_addr_rdata[6]; - ibex_pkg_CSR_PMPADDR7: csr_rdata_int = pmp_addr_rdata[7]; - ibex_pkg_CSR_PMPADDR8: csr_rdata_int = pmp_addr_rdata[8]; - ibex_pkg_CSR_PMPADDR9: csr_rdata_int = pmp_addr_rdata[9]; - ibex_pkg_CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10]; - ibex_pkg_CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11]; - ibex_pkg_CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12]; - ibex_pkg_CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13]; - ibex_pkg_CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14]; - ibex_pkg_CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15]; - ibex_pkg_CSR_DCSR: begin - csr_rdata_int = dcsr_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DPC: begin - csr_rdata_int = depc_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DSCRATCH0: begin - csr_rdata_int = dscratch0_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_DSCRATCH1: begin - csr_rdata_int = dscratch1_q; - illegal_csr = ~debug_mode_i; - end - ibex_pkg_CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit; - ibex_pkg_CSR_MHPMEVENT3, ibex_pkg_CSR_MHPMEVENT4, ibex_pkg_CSR_MHPMEVENT5, ibex_pkg_CSR_MHPMEVENT6, ibex_pkg_CSR_MHPMEVENT7, ibex_pkg_CSR_MHPMEVENT8, ibex_pkg_CSR_MHPMEVENT9, ibex_pkg_CSR_MHPMEVENT10, ibex_pkg_CSR_MHPMEVENT11, ibex_pkg_CSR_MHPMEVENT12, ibex_pkg_CSR_MHPMEVENT13, ibex_pkg_CSR_MHPMEVENT14, ibex_pkg_CSR_MHPMEVENT15, ibex_pkg_CSR_MHPMEVENT16, ibex_pkg_CSR_MHPMEVENT17, ibex_pkg_CSR_MHPMEVENT18, ibex_pkg_CSR_MHPMEVENT19, ibex_pkg_CSR_MHPMEVENT20, ibex_pkg_CSR_MHPMEVENT21, ibex_pkg_CSR_MHPMEVENT22, ibex_pkg_CSR_MHPMEVENT23, ibex_pkg_CSR_MHPMEVENT24, ibex_pkg_CSR_MHPMEVENT25, ibex_pkg_CSR_MHPMEVENT26, ibex_pkg_CSR_MHPMEVENT27, ibex_pkg_CSR_MHPMEVENT28, ibex_pkg_CSR_MHPMEVENT29, ibex_pkg_CSR_MHPMEVENT30, ibex_pkg_CSR_MHPMEVENT31: csr_rdata_int = mhpmevent[mhpmcounter_idx]; - ibex_pkg_CSR_MCYCLE, ibex_pkg_CSR_MINSTRET, ibex_pkg_CSR_MHPMCOUNTER3, ibex_pkg_CSR_MHPMCOUNTER4, ibex_pkg_CSR_MHPMCOUNTER5, ibex_pkg_CSR_MHPMCOUNTER6, ibex_pkg_CSR_MHPMCOUNTER7, ibex_pkg_CSR_MHPMCOUNTER8, ibex_pkg_CSR_MHPMCOUNTER9, ibex_pkg_CSR_MHPMCOUNTER10, ibex_pkg_CSR_MHPMCOUNTER11, ibex_pkg_CSR_MHPMCOUNTER12, ibex_pkg_CSR_MHPMCOUNTER13, ibex_pkg_CSR_MHPMCOUNTER14, ibex_pkg_CSR_MHPMCOUNTER15, ibex_pkg_CSR_MHPMCOUNTER16, ibex_pkg_CSR_MHPMCOUNTER17, ibex_pkg_CSR_MHPMCOUNTER18, ibex_pkg_CSR_MHPMCOUNTER19, ibex_pkg_CSR_MHPMCOUNTER20, ibex_pkg_CSR_MHPMCOUNTER21, ibex_pkg_CSR_MHPMCOUNTER22, ibex_pkg_CSR_MHPMCOUNTER23, ibex_pkg_CSR_MHPMCOUNTER24, ibex_pkg_CSR_MHPMCOUNTER25, ibex_pkg_CSR_MHPMCOUNTER26, ibex_pkg_CSR_MHPMCOUNTER27, ibex_pkg_CSR_MHPMCOUNTER28, ibex_pkg_CSR_MHPMCOUNTER29, ibex_pkg_CSR_MHPMCOUNTER30, ibex_pkg_CSR_MHPMCOUNTER31: csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0]; - ibex_pkg_CSR_MCYCLEH, ibex_pkg_CSR_MINSTRETH, ibex_pkg_CSR_MHPMCOUNTER3H, ibex_pkg_CSR_MHPMCOUNTER4H, ibex_pkg_CSR_MHPMCOUNTER5H, ibex_pkg_CSR_MHPMCOUNTER6H, ibex_pkg_CSR_MHPMCOUNTER7H, ibex_pkg_CSR_MHPMCOUNTER8H, ibex_pkg_CSR_MHPMCOUNTER9H, ibex_pkg_CSR_MHPMCOUNTER10H, ibex_pkg_CSR_MHPMCOUNTER11H, ibex_pkg_CSR_MHPMCOUNTER12H, ibex_pkg_CSR_MHPMCOUNTER13H, ibex_pkg_CSR_MHPMCOUNTER14H, ibex_pkg_CSR_MHPMCOUNTER15H, ibex_pkg_CSR_MHPMCOUNTER16H, ibex_pkg_CSR_MHPMCOUNTER17H, ibex_pkg_CSR_MHPMCOUNTER18H, ibex_pkg_CSR_MHPMCOUNTER19H, ibex_pkg_CSR_MHPMCOUNTER20H, ibex_pkg_CSR_MHPMCOUNTER21H, ibex_pkg_CSR_MHPMCOUNTER22H, ibex_pkg_CSR_MHPMCOUNTER23H, ibex_pkg_CSR_MHPMCOUNTER24H, ibex_pkg_CSR_MHPMCOUNTER25H, ibex_pkg_CSR_MHPMCOUNTER26H, ibex_pkg_CSR_MHPMCOUNTER27H, ibex_pkg_CSR_MHPMCOUNTER28H, ibex_pkg_CSR_MHPMCOUNTER29H, ibex_pkg_CSR_MHPMCOUNTER30H, ibex_pkg_CSR_MHPMCOUNTER31H: csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32]; - ibex_pkg_CSR_TSELECT: begin - csr_rdata_int = tselect_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA1: begin - csr_rdata_int = tmatch_control_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA2: begin - csr_rdata_int = tmatch_value_rdata; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_TDATA3: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_MCONTEXT: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_SCONTEXT: begin - csr_rdata_int = {32 {1'sb0}}; - illegal_csr = ~DbgTriggerEn; - end - ibex_pkg_CSR_CPUCTRL: csr_rdata_int = {{26 {1'b0}}, cpuctrl_q}; - ibex_pkg_CSR_SECURESEED: csr_rdata_int = {32 {1'sb0}}; - default: illegal_csr = 1'b1; - endcase - end - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - localparam [1:0] ibex_pkg_PRIV_LVL_U = 2'b00; - localparam [3:0] ibex_pkg_XDEBUGVER_STD = 4'd4; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - always @(*) begin - exception_pc = pc_id_i; - priv_lvl_d = priv_lvl_q; - mstatus_en = 1'b0; - mstatus_d = mstatus_q; - mie_en = 1'b0; - mscratch_en = 1'b0; - mepc_en = 1'b0; - mepc_d = {csr_wdata_int[31:1], 1'b0}; - mcause_en = 1'b0; - mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; - mtval_en = 1'b0; - mtval_d = csr_wdata_int; - mtvec_en = csr_mtvec_init_i; - mtvec_d = (csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b000000, 2'b01} : {csr_wdata_int[31:8], 6'b000000, 2'b01}); - dcsr_en = 1'b0; - dcsr_d = dcsr_q; - depc_d = {csr_wdata_int[31:1], 1'b0}; - depc_en = 1'b0; - dscratch0_en = 1'b0; - dscratch1_en = 1'b0; - mstack_en = 1'b0; - mstack_d[2] = mstatus_q[4]; - mstack_d[1-:2] = mstatus_q[3-:2]; - mstack_epc_d = mepc_q; - mstack_cause_d = mcause_q; - mcountinhibit_we = 1'b0; - mhpmcounter_we = {32 {1'sb0}}; - mhpmcounterh_we = {32 {1'sb0}}; - cpuctrl_we = 1'b0; - if (csr_we_int) - case (csr_addr_i) - ibex_pkg_CSR_MSTATUS: begin - mstatus_en = 1'b1; - mstatus_d = {csr_wdata_int[ibex_pkg_CSR_MSTATUS_MIE_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPIE_BIT], sv2v_cast_2(csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPP_BIT_HIGH:ibex_pkg_CSR_MSTATUS_MPP_BIT_LOW]), csr_wdata_int[ibex_pkg_CSR_MSTATUS_MPRV_BIT], csr_wdata_int[ibex_pkg_CSR_MSTATUS_TW_BIT]}; - if ((mstatus_d[3-:2] != ibex_pkg_PRIV_LVL_M) && (mstatus_d[3-:2] != ibex_pkg_PRIV_LVL_U)) - mstatus_d[3-:2] = ibex_pkg_PRIV_LVL_M; - end - ibex_pkg_CSR_MIE: mie_en = 1'b1; - ibex_pkg_CSR_MSCRATCH: mscratch_en = 1'b1; - ibex_pkg_CSR_MEPC: mepc_en = 1'b1; - ibex_pkg_CSR_MCAUSE: mcause_en = 1'b1; - ibex_pkg_CSR_MTVAL: mtval_en = 1'b1; - ibex_pkg_CSR_MTVEC: mtvec_en = 1'b1; - ibex_pkg_CSR_DCSR: begin - dcsr_d = csr_wdata_int; - dcsr_d[31-:4] = ibex_pkg_XDEBUGVER_STD; - if ((dcsr_d[1-:2] != ibex_pkg_PRIV_LVL_M) && (dcsr_d[1-:2] != ibex_pkg_PRIV_LVL_U)) - dcsr_d[1-:2] = ibex_pkg_PRIV_LVL_M; - dcsr_d[8-:3] = dcsr_q[8-:3]; - dcsr_d[3] = 1'b0; - dcsr_d[4] = 1'b0; - dcsr_d[10] = 1'b0; - dcsr_d[9] = 1'b0; - dcsr_d[5] = 1'b0; - dcsr_d[14] = 1'b0; - dcsr_d[27-:12] = 12'h000; - dcsr_en = 1'b1; - end - ibex_pkg_CSR_DPC: depc_en = 1'b1; - ibex_pkg_CSR_DSCRATCH0: dscratch0_en = 1'b1; - ibex_pkg_CSR_DSCRATCH1: dscratch1_en = 1'b1; - ibex_pkg_CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1; - ibex_pkg_CSR_MCYCLE, ibex_pkg_CSR_MINSTRET, ibex_pkg_CSR_MHPMCOUNTER3, ibex_pkg_CSR_MHPMCOUNTER4, ibex_pkg_CSR_MHPMCOUNTER5, ibex_pkg_CSR_MHPMCOUNTER6, ibex_pkg_CSR_MHPMCOUNTER7, ibex_pkg_CSR_MHPMCOUNTER8, ibex_pkg_CSR_MHPMCOUNTER9, ibex_pkg_CSR_MHPMCOUNTER10, ibex_pkg_CSR_MHPMCOUNTER11, ibex_pkg_CSR_MHPMCOUNTER12, ibex_pkg_CSR_MHPMCOUNTER13, ibex_pkg_CSR_MHPMCOUNTER14, ibex_pkg_CSR_MHPMCOUNTER15, ibex_pkg_CSR_MHPMCOUNTER16, ibex_pkg_CSR_MHPMCOUNTER17, ibex_pkg_CSR_MHPMCOUNTER18, ibex_pkg_CSR_MHPMCOUNTER19, ibex_pkg_CSR_MHPMCOUNTER20, ibex_pkg_CSR_MHPMCOUNTER21, ibex_pkg_CSR_MHPMCOUNTER22, ibex_pkg_CSR_MHPMCOUNTER23, ibex_pkg_CSR_MHPMCOUNTER24, ibex_pkg_CSR_MHPMCOUNTER25, ibex_pkg_CSR_MHPMCOUNTER26, ibex_pkg_CSR_MHPMCOUNTER27, ibex_pkg_CSR_MHPMCOUNTER28, ibex_pkg_CSR_MHPMCOUNTER29, ibex_pkg_CSR_MHPMCOUNTER30, ibex_pkg_CSR_MHPMCOUNTER31: mhpmcounter_we[mhpmcounter_idx] = 1'b1; - ibex_pkg_CSR_MCYCLEH, ibex_pkg_CSR_MINSTRETH, ibex_pkg_CSR_MHPMCOUNTER3H, ibex_pkg_CSR_MHPMCOUNTER4H, ibex_pkg_CSR_MHPMCOUNTER5H, ibex_pkg_CSR_MHPMCOUNTER6H, ibex_pkg_CSR_MHPMCOUNTER7H, ibex_pkg_CSR_MHPMCOUNTER8H, ibex_pkg_CSR_MHPMCOUNTER9H, ibex_pkg_CSR_MHPMCOUNTER10H, ibex_pkg_CSR_MHPMCOUNTER11H, ibex_pkg_CSR_MHPMCOUNTER12H, ibex_pkg_CSR_MHPMCOUNTER13H, ibex_pkg_CSR_MHPMCOUNTER14H, ibex_pkg_CSR_MHPMCOUNTER15H, ibex_pkg_CSR_MHPMCOUNTER16H, ibex_pkg_CSR_MHPMCOUNTER17H, ibex_pkg_CSR_MHPMCOUNTER18H, ibex_pkg_CSR_MHPMCOUNTER19H, ibex_pkg_CSR_MHPMCOUNTER20H, ibex_pkg_CSR_MHPMCOUNTER21H, ibex_pkg_CSR_MHPMCOUNTER22H, ibex_pkg_CSR_MHPMCOUNTER23H, ibex_pkg_CSR_MHPMCOUNTER24H, ibex_pkg_CSR_MHPMCOUNTER25H, ibex_pkg_CSR_MHPMCOUNTER26H, ibex_pkg_CSR_MHPMCOUNTER27H, ibex_pkg_CSR_MHPMCOUNTER28H, ibex_pkg_CSR_MHPMCOUNTER29H, ibex_pkg_CSR_MHPMCOUNTER30H, ibex_pkg_CSR_MHPMCOUNTER31H: mhpmcounterh_we[mhpmcounter_idx] = 1'b1; - ibex_pkg_CSR_CPUCTRL: cpuctrl_we = 1'b1; - default: - ; - endcase - case (1'b1) - csr_save_cause_i: begin - case (1'b1) - csr_save_if_i: exception_pc = pc_if_i; - csr_save_id_i: exception_pc = pc_id_i; - csr_save_wb_i: exception_pc = pc_wb_i; - default: - ; - endcase - priv_lvl_d = ibex_pkg_PRIV_LVL_M; - if (debug_csr_save_i) begin - dcsr_d[1-:2] = priv_lvl_q; - dcsr_d[8-:3] = debug_cause_i; - dcsr_en = 1'b1; - depc_d = exception_pc; - depc_en = 1'b1; - end - else if (!debug_mode_i) begin - mtval_en = 1'b1; - mtval_d = csr_mtval_i; - mstatus_en = 1'b1; - mstatus_d[5] = 1'b0; - mstatus_d[4] = mstatus_q[5]; - mstatus_d[3-:2] = priv_lvl_q; - mepc_en = 1'b1; - mepc_d = exception_pc; - mcause_en = 1'b1; - mcause_d = {csr_mcause_i}; - mstack_en = 1'b1; - end - end - csr_restore_dret_i: priv_lvl_d = dcsr_q[1-:2]; - csr_restore_mret_i: begin - priv_lvl_d = mstatus_q[3-:2]; - mstatus_en = 1'b1; - mstatus_d[5] = mstatus_q[4]; - if (nmi_mode_i) begin - mstatus_d[4] = mstack_q[2]; - mstatus_d[3-:2] = mstack_q[1-:2]; - mepc_en = 1'b1; - mepc_d = mstack_epc_q; - mcause_en = 1'b1; - mcause_d = mstack_cause_q; - end - else begin - mstatus_d[4] = 1'b1; - mstatus_d[3-:2] = ibex_pkg_PRIV_LVL_U; - end - end - default: - ; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - priv_lvl_q <= ibex_pkg_PRIV_LVL_M; - else - priv_lvl_q <= priv_lvl_d; - assign priv_mode_id_o = priv_lvl_q; - assign priv_mode_if_o = priv_lvl_d; - assign priv_mode_lsu_o = (mstatus_q[1] ? mstatus_q[3-:2] : priv_lvl_q); - localparam [1:0] ibex_pkg_CSR_OP_CLEAR = 3; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - always @(*) - case (csr_op_i) - ibex_pkg_CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; - ibex_pkg_CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; - ibex_pkg_CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o; - ibex_pkg_CSR_OP_READ: csr_wdata_int = csr_wdata_i; - default: csr_wdata_int = csr_wdata_i; - endcase - assign csr_wreq = csr_op_en_i & |{csr_op_i == ibex_pkg_CSR_OP_WRITE, csr_op_i == ibex_pkg_CSR_OP_SET, csr_op_i == ibex_pkg_CSR_OP_CLEAR}; - assign csr_we_int = csr_wreq & ~illegal_csr_insn_o; - assign csr_rdata_o = csr_rdata_int; - assign csr_mepc_o = mepc_q; - assign csr_depc_o = depc_q; - assign csr_mtvec_o = mtvec_q; - assign csr_mstatus_mie_o = mstatus_q[5]; - assign csr_mstatus_tw_o = mstatus_q[0]; - assign debug_single_step_o = dcsr_q[2]; - assign debug_ebreakm_o = dcsr_q[15]; - assign debug_ebreaku_o = dcsr_q[12]; - assign irqs_o = mip & mie_q; - assign irq_pending_o = |irqs_o; - localparam [5:0] MSTATUS_RST_VAL = {1'b0, 1'b1, ibex_pkg_PRIV_LVL_U, 1'b0, 1'b0}; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue({MSTATUS_RST_VAL}) - ) u_mstatus_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mstatus_d}), - .wr_en_i(mstatus_en), - .rd_data_o(mstatus_q), - .rd_error_o(mstatus_err) - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mepc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mepc_d), - .wr_en_i(mepc_en), - .rd_data_o(mepc_q), - .rd_error_o() - ); - assign mie_d[17] = csr_wdata_int[ibex_pkg_CSR_MSIX_BIT]; - assign mie_d[16] = csr_wdata_int[ibex_pkg_CSR_MTIX_BIT]; - assign mie_d[15] = csr_wdata_int[ibex_pkg_CSR_MEIX_BIT]; - assign mie_d[14-:15] = csr_wdata_int[ibex_pkg_CSR_MFIX_BIT_HIGH:ibex_pkg_CSR_MFIX_BIT_LOW]; - ibex_csr #( - .Width(18), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mie_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mie_d}), - .wr_en_i(mie_en), - .rd_data_o(mie_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mscratch_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(mscratch_en), - .rd_data_o(mscratch_q), - .rd_error_o() - ); - ibex_csr #( - .Width(6), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mcause_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mcause_d), - .wr_en_i(mcause_en), - .rd_data_o(mcause_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mtval_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mtval_d), - .wr_en_i(mtval_en), - .rd_data_o(mtval_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(ShadowCSR), - .ResetValue(32'd1) - ) u_mtvec_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mtvec_d), - .wr_en_i(mtvec_en), - .rd_data_o(mtvec_q), - .rd_error_o(mtvec_err) - ); - localparam [2:0] ibex_pkg_DBG_CAUSE_NONE = 3'h0; - localparam [31:0] DCSR_RESET_VAL = {ibex_pkg_XDEBUGVER_STD, 12'b000000000000, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, ibex_pkg_DBG_CAUSE_NONE, 1'b0, 1'b0, 1'b0, 1'b0, ibex_pkg_PRIV_LVL_M}; - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue({DCSR_RESET_VAL}) - ) u_dcsr_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({dcsr_d}), - .wr_en_i(dcsr_en), - .rd_data_o(dcsr_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_depc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(depc_d), - .wr_en_i(depc_en), - .rd_data_o(depc_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_dscratch0_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(dscratch0_en), - .rd_data_o(dscratch0_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_dscratch1_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int), - .wr_en_i(dscratch1_en), - .rd_data_o(dscratch1_q), - .rd_error_o() - ); - localparam [2:0] MSTACK_RESET_VAL = {1'b1, ibex_pkg_PRIV_LVL_U}; - ibex_csr #( - .Width(3), - .ShadowCopy(1'b0), - .ResetValue({MSTACK_RESET_VAL}) - ) u_mstack_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({mstack_d}), - .wr_en_i(mstack_en), - .rd_data_o(mstack_q), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mstack_epc_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mstack_epc_d), - .wr_en_i(mstack_en), - .rd_data_o(mstack_epc_q), - .rd_error_o() - ); - ibex_csr #( - .Width(6), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_mstack_cause_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(mstack_cause_d), - .wr_en_i(mstack_en), - .rd_data_o(mstack_cause_q), - .rd_error_o() - ); - localparam [11:0] ibex_pkg_CSR_OFF_PMP_ADDR = 12'h3b0; - localparam [11:0] ibex_pkg_CSR_OFF_PMP_CFG = 12'h3a0; - localparam [1:0] ibex_pkg_PMP_MODE_NA4 = 2'b10; - localparam [1:0] ibex_pkg_PMP_MODE_NAPOT = 2'b11; - localparam [1:0] ibex_pkg_PMP_MODE_OFF = 2'b00; - localparam [1:0] ibex_pkg_PMP_MODE_TOR = 2'b01; - generate - if (PMPEnable) begin : g_pmp_registers - wire [5:0] pmp_cfg [0:PMPNumRegions - 1]; - reg [5:0] pmp_cfg_wdata [0:PMPNumRegions - 1]; - wire [PMPAddrWidth - 1:0] pmp_addr [0:PMPNumRegions - 1]; - wire [PMPNumRegions - 1:0] pmp_cfg_we; - wire [PMPNumRegions - 1:0] pmp_cfg_err; - wire [PMPNumRegions - 1:0] pmp_addr_we; - wire [PMPNumRegions - 1:0] pmp_addr_err; - genvar i; - for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_exp_rd_data - if (i < PMPNumRegions) begin : g_implemented_regions - assign pmp_cfg_rdata[i] = {pmp_cfg[i][5], 2'b00, pmp_cfg[i][4-:2], pmp_cfg[i][2], pmp_cfg[i][1], pmp_cfg[i][0]}; - if (PMPGranularity == 0) begin : g_pmp_g0 - wire [PMPAddrWidth:1] sv2v_tmp_D3A6A; - assign sv2v_tmp_D3A6A = pmp_addr[i]; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_D3A6A; - end - else if (PMPGranularity == 1) begin : g_pmp_g1 - always @(*) begin - pmp_addr_rdata[i] = pmp_addr[i]; - if ((pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_TOR)) - pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; - end - end - else begin : g_pmp_g2 - always @(*) begin - pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity - 1 {1'b1}}}; - if ((pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == ibex_pkg_PMP_MODE_TOR)) - pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; - end - end - end - else begin : g_other_regions - assign pmp_cfg_rdata[i] = {ibex_pkg_PMP_CFG_W {1'sb0}}; - wire [32:1] sv2v_tmp_313D8; - assign sv2v_tmp_313D8 = {32 {1'sb0}}; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_313D8; - end - end - for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_pmp_csrs - assign pmp_cfg_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_CFG + (i[11:0] >> 2))); - wire [1:1] sv2v_tmp_12AC7; - assign sv2v_tmp_12AC7 = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 7]; - always @(*) pmp_cfg_wdata[i][5] = sv2v_tmp_12AC7; - always @(*) - case (csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 3+:2]) - 2'b00: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_OFF; - 2'b01: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_TOR; - 2'b10: pmp_cfg_wdata[i][4-:2] = (PMPGranularity == 0 ? ibex_pkg_PMP_MODE_NA4 : ibex_pkg_PMP_MODE_OFF); - 2'b11: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_NAPOT; - default: pmp_cfg_wdata[i][4-:2] = ibex_pkg_PMP_MODE_OFF; - endcase - wire [1:1] sv2v_tmp_B1072; - assign sv2v_tmp_B1072 = csr_wdata_int[((i % 4) * ibex_pkg_PMP_CFG_W) + 2]; - always @(*) pmp_cfg_wdata[i][2] = sv2v_tmp_B1072; - wire [1:1] sv2v_tmp_CFE62; - assign sv2v_tmp_CFE62 = &csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W+:2]; - always @(*) pmp_cfg_wdata[i][1] = sv2v_tmp_CFE62; - wire [1:1] sv2v_tmp_FD795; - assign sv2v_tmp_FD795 = csr_wdata_int[(i % 4) * ibex_pkg_PMP_CFG_W]; - always @(*) pmp_cfg_wdata[i][0] = sv2v_tmp_FD795; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_pmp_cfg_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({pmp_cfg_wdata[i]}), - .wr_en_i(pmp_cfg_we[i]), - .rd_data_o(pmp_cfg[i]), - .rd_error_o(pmp_cfg_err[i]) - ); - if (i < (PMPNumRegions - 1)) begin : g_lower - assign pmp_addr_we[i] = ((csr_we_int & ~pmp_cfg[i][5]) & (~pmp_cfg[i + 1][5] | (pmp_cfg[i + 1][4-:2] != ibex_pkg_PMP_MODE_TOR))) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0])); - end - else begin : g_upper - assign pmp_addr_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (ibex_pkg_CSR_OFF_PMP_ADDR + i[11:0])); - end - ibex_csr #( - .Width(PMPAddrWidth), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_pmp_addr_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(csr_wdata_int[31-:PMPAddrWidth]), - .wr_en_i(pmp_addr_we[i]), - .rd_data_o(pmp_addr[i]), - .rd_error_o(pmp_addr_err[i]) - ); - assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = pmp_cfg[i]; - assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {pmp_addr_rdata[i], 2'b00}; - end - assign pmp_csr_err = |pmp_cfg_err | |pmp_addr_err; - end - else begin : g_no_pmp_tieoffs - genvar i; - for (i = 0; i < ibex_pkg_PMP_MAX_REGIONS; i = i + 1) begin : g_rdata - wire [32:1] sv2v_tmp_313D8; - assign sv2v_tmp_313D8 = {32 {1'sb0}}; - always @(*) pmp_addr_rdata[i] = sv2v_tmp_313D8; - assign pmp_cfg_rdata[i] = {ibex_pkg_PMP_CFG_W {1'sb0}}; - end - for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_outputs - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = sv2v_cast_6(1'b0); - assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {34 {1'sb0}}; - end - assign pmp_csr_err = 1'b0; - end - endgenerate - always @(*) begin : mcountinhibit_update - if (mcountinhibit_we == 1'b1) - mcountinhibit_d = {csr_wdata_int[MHPMCounterNum + 2:2], 1'b0, csr_wdata_int[0]}; - else - mcountinhibit_d = mcountinhibit_q; - end - always @(*) begin : gen_mhpmcounter_incr - begin : sv2v_autoblock_7 - reg [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_mhpmcounter_incr_inactive - mhpmcounter_incr[i] = 1'b0; - end - end - mhpmcounter_incr[0] = 1'b1; - mhpmcounter_incr[1] = 1'b0; - mhpmcounter_incr[2] = instr_ret_i; - mhpmcounter_incr[3] = dside_wait_i; - mhpmcounter_incr[4] = iside_wait_i; - mhpmcounter_incr[5] = mem_load_i; - mhpmcounter_incr[6] = mem_store_i; - mhpmcounter_incr[7] = jump_i; - mhpmcounter_incr[8] = branch_i; - mhpmcounter_incr[9] = branch_taken_i; - mhpmcounter_incr[10] = instr_ret_compressed_i; - mhpmcounter_incr[11] = mul_wait_i; - mhpmcounter_incr[12] = div_wait_i; - end - always @(*) begin : gen_mhpmevent - begin : sv2v_autoblock_8 - reg signed [31:0] i; - for (i = 0; i < 32; i = i + 1) - begin : gen_mhpmevent_active - mhpmevent[i] = {32 {1'sb0}}; - mhpmevent[i][i] = 1'b1; - end - end - mhpmevent[1] = {32 {1'sb0}}; - begin : sv2v_autoblock_9 - reg [31:0] i; - for (i = 3 + MHPMCounterNum; i < 32; i = i + 1) - begin : gen_mhpmevent_inactive - mhpmevent[i] = {32 {1'sb0}}; - end - end - end - ibex_counter #(.CounterWidth(64)) mcycle_counter_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]), - .counterh_we_i(mhpmcounterh_we[0]), - .counter_we_i(mhpmcounter_we[0]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[0]) - ); - ibex_counter #(.CounterWidth(64)) minstret_counter_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]), - .counterh_we_i(mhpmcounterh_we[2]), - .counter_we_i(mhpmcounter_we[2]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[2]) - ); - assign mhpmcounter[1] = {64 {1'sb0}}; - assign unused_mhpmcounter_we_1 = mhpmcounter_we[1]; - assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1]; - assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1]; - generate - genvar cnt; - for (cnt = 0; cnt < 29; cnt = cnt + 1) begin : gen_cntrs - if (cnt < MHPMCounterNum) begin : gen_imp - ibex_counter #(.CounterWidth(MHPMCounterWidth)) mcounters_variable_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .counter_inc_i(mhpmcounter_incr[cnt + 3] & ~mcountinhibit[cnt + 3]), - .counterh_we_i(mhpmcounterh_we[cnt + 3]), - .counter_we_i(mhpmcounter_we[cnt + 3]), - .counter_val_i(csr_wdata_int), - .counter_val_o(mhpmcounter[cnt + 3]) - ); - end - else begin : gen_unimp - assign mhpmcounter[cnt + 3] = {64 {1'sb0}}; - end - end - endgenerate - generate - if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_we; - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounterh_we; - wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_incr; - assign mcountinhibit = {{29 - MHPMCounterNum {1'b1}}, mcountinhibit_q}; - assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum + 3]; - assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum + 3]; - assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum + 3]; - end - else begin : g_mcountinhibit_full - assign mcountinhibit = mcountinhibit_q; - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mcountinhibit_q <= {((MHPMCounterNum + 2) >= 0 ? MHPMCounterNum + 3 : 1 - (MHPMCounterNum + 2)) {1'sb0}}; - else - mcountinhibit_q <= mcountinhibit_d; - generate - if (DbgTriggerEn) begin : gen_trigger_regs - localparam [31:0] DbgHwNumLen = (DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1); - wire [DbgHwNumLen - 1:0] tselect_d; - wire [DbgHwNumLen - 1:0] tselect_q; - wire tmatch_control_d; - wire [DbgHwBreakNum - 1:0] tmatch_control_q; - wire [31:0] tmatch_value_d; - wire [31:0] tmatch_value_q [0:DbgHwBreakNum - 1]; - wire tselect_we; - wire [DbgHwBreakNum - 1:0] tmatch_control_we; - wire [DbgHwBreakNum - 1:0] tmatch_value_we; - wire [DbgHwBreakNum - 1:0] trigger_match; - assign tselect_we = (csr_we_int & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TSELECT); - genvar i; - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_we - assign tmatch_control_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TDATA1); - assign tmatch_value_we[i] = (((i[DbgHwNumLen - 1:0] == tselect_q) & csr_we_int) & debug_mode_i) & (csr_addr_i == ibex_pkg_CSR_TDATA2); - end - assign tselect_d = (csr_wdata_int < DbgHwBreakNum ? csr_wdata_int[DbgHwNumLen - 1:0] : DbgHwBreakNum - 1); - assign tmatch_control_d = csr_wdata_int[2]; - assign tmatch_value_d = csr_wdata_int[31:0]; - ibex_csr #( - .Width(DbgHwNumLen), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tselect_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tselect_d), - .wr_en_i(tselect_we), - .rd_data_o(tselect_q), - .rd_error_o() - ); - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_tmatch_reg - ibex_csr #( - .Width(1), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tmatch_control_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tmatch_control_d), - .wr_en_i(tmatch_control_we[i]), - .rd_data_o(tmatch_control_q[i]), - .rd_error_o() - ); - ibex_csr #( - .Width(32), - .ShadowCopy(1'b0), - .ResetValue('0) - ) u_tmatch_value_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i(tmatch_value_d), - .wr_en_i(tmatch_value_we[i]), - .rd_data_o(tmatch_value_q[i]), - .rd_error_o() - ); - end - localparam [31:0] TSelectRdataPadlen = (DbgHwNumLen >= 32 ? 0 : 32 - DbgHwNumLen); - assign tselect_rdata = {{TSelectRdataPadlen {1'b0}}, tselect_q}; - assign tmatch_control_rdata = {4'h2, 1'b1, 6'h00, 1'b0, 1'b0, 1'b0, 2'b00, 4'h1, 1'b0, 4'h0, 1'b1, 1'b0, 1'b0, 1'b1, tmatch_control_q[tselect_q], 1'b0, 1'b0}; - assign tmatch_value_rdata = tmatch_value_q[tselect_q]; - for (i = 0; i < DbgHwBreakNum; i = i + 1) begin : g_dbg_trigger_match - assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]); - end - assign trigger_match_o = |trigger_match; - end - else begin : gen_no_trigger_regs - assign tselect_rdata = 'b0; - assign tmatch_control_rdata = 'b0; - assign tmatch_value_rdata = 'b0; - assign trigger_match_o = 'b0; - end - endgenerate - assign cpuctrl_wdata = csr_wdata_int[5:0]; - generate - if (DataIndTiming) begin : gen_dit - assign cpuctrl_d[1] = cpuctrl_wdata[1]; - end - else begin : gen_no_dit - wire unused_dit; - assign unused_dit = cpuctrl_wdata[1]; - assign cpuctrl_d[1] = 1'b0; - end - endgenerate - assign data_ind_timing_o = cpuctrl_q[1]; - generate - if (DummyInstructions) begin : gen_dummy - assign cpuctrl_d[2] = cpuctrl_wdata[2]; - assign cpuctrl_d[5-:3] = cpuctrl_wdata[5-:3]; - assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == ibex_pkg_CSR_SECURESEED); - assign dummy_instr_seed_o = csr_wdata_int; - end - else begin : gen_no_dummy - wire unused_dummy_en; - wire [2:0] unused_dummy_mask; - assign unused_dummy_en = cpuctrl_wdata[2]; - assign unused_dummy_mask = cpuctrl_wdata[5-:3]; - assign cpuctrl_d[2] = 1'b0; - assign cpuctrl_d[5-:3] = 3'b000; - assign dummy_instr_seed_en_o = 1'b0; - assign dummy_instr_seed_o = {32 {1'sb0}}; - end - endgenerate - assign dummy_instr_en_o = cpuctrl_q[2]; - assign dummy_instr_mask_o = cpuctrl_q[5-:3]; - generate - if (ICache) begin : gen_icache_enable - assign cpuctrl_d[0] = cpuctrl_wdata[0]; - end - else begin : gen_no_icache - wire unused_icen; - assign unused_icen = cpuctrl_wdata[0]; - assign cpuctrl_d[0] = 1'b0; - end - endgenerate - assign icache_enable_o = cpuctrl_q[0]; - ibex_csr #( - .Width(6), - .ShadowCopy(ShadowCSR), - .ResetValue('0) - ) u_cpuctrl_csr( - .clk_i(clk_i), - .rst_ni(rst_ni), - .wr_data_i({cpuctrl_d}), - .wr_en_i(cpuctrl_we), - .rd_data_o(cpuctrl_q), - .rd_error_o(cpuctrl_err) - ); - assign csr_shadow_err_o = ((mstatus_err | mtvec_err) | pmp_csr_err) | cpuctrl_err; -endmodule diff --git a/flow/designs/src/ibex/ibex_csr.v b/flow/designs/src/ibex/ibex_csr.v deleted file mode 100644 index edae878e0c..0000000000 --- a/flow/designs/src/ibex/ibex_csr.v +++ /dev/null @@ -1,39 +0,0 @@ -module ibex_csr ( - clk_i, - rst_ni, - wr_data_i, - wr_en_i, - rd_data_o, - rd_error_o -); - parameter [31:0] Width = 32; - parameter [0:0] ShadowCopy = 1'b0; - parameter [Width - 1:0] ResetValue = 1'sb0; - input wire clk_i; - input wire rst_ni; - input wire [Width - 1:0] wr_data_i; - input wire wr_en_i; - output wire [Width - 1:0] rd_data_o; - output wire rd_error_o; - reg [Width - 1:0] rdata_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rdata_q <= ResetValue; - else if (wr_en_i) - rdata_q <= wr_data_i; - assign rd_data_o = rdata_q; - generate - if (ShadowCopy) begin : gen_shadow - reg [Width - 1:0] shadow_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - shadow_q <= ~ResetValue; - else if (wr_en_i) - shadow_q <= ~wr_data_i; - assign rd_error_o = rdata_q != ~shadow_q; - end - else begin : gen_no_shadow - assign rd_error_o = 1'b0; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_decoder.v b/flow/designs/src/ibex/ibex_decoder.v deleted file mode 100644 index b41d5f0bf2..0000000000 --- a/flow/designs/src/ibex/ibex_decoder.v +++ /dev/null @@ -1,948 +0,0 @@ -module ibex_decoder ( - clk_i, - rst_ni, - illegal_insn_o, - ebrk_insn_o, - mret_insn_o, - dret_insn_o, - ecall_insn_o, - wfi_insn_o, - jump_set_o, - branch_taken_i, - icache_inval_o, - instr_first_cycle_i, - instr_rdata_i, - instr_rdata_alu_i, - illegal_c_insn_i, - imm_a_mux_sel_o, - imm_b_mux_sel_o, - bt_a_mux_sel_o, - bt_b_mux_sel_o, - imm_i_type_o, - imm_s_type_o, - imm_b_type_o, - imm_u_type_o, - imm_j_type_o, - zimm_rs1_type_o, - rf_wdata_sel_o, - rf_we_o, - rf_raddr_a_o, - rf_raddr_b_o, - rf_waddr_o, - rf_ren_a_o, - rf_ren_b_o, - alu_operator_o, - alu_op_a_mux_sel_o, - alu_op_b_mux_sel_o, - alu_multicycle_o, - mult_en_o, - div_en_o, - mult_sel_o, - div_sel_o, - multdiv_operator_o, - multdiv_signed_mode_o, - csr_access_o, - csr_op_o, - data_req_o, - data_we_o, - data_type_o, - data_sign_extension_o, - jump_in_dec_o, - branch_in_dec_o -); - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] BranchTargetALU = 0; - input wire clk_i; - input wire rst_ni; - output wire illegal_insn_o; - output reg ebrk_insn_o; - output reg mret_insn_o; - output reg dret_insn_o; - output reg ecall_insn_o; - output reg wfi_insn_o; - output reg jump_set_o; - input wire branch_taken_i; - output reg icache_inval_o; - input wire instr_first_cycle_i; - input wire [31:0] instr_rdata_i; - input wire [31:0] instr_rdata_alu_i; - input wire illegal_c_insn_i; - output reg imm_a_mux_sel_o; - output reg [2:0] imm_b_mux_sel_o; - output reg [1:0] bt_a_mux_sel_o; - output reg [2:0] bt_b_mux_sel_o; - output wire [31:0] imm_i_type_o; - output wire [31:0] imm_s_type_o; - output wire [31:0] imm_b_type_o; - output wire [31:0] imm_u_type_o; - output wire [31:0] imm_j_type_o; - output wire [31:0] zimm_rs1_type_o; - output reg rf_wdata_sel_o; - output wire rf_we_o; - output wire [4:0] rf_raddr_a_o; - output wire [4:0] rf_raddr_b_o; - output wire [4:0] rf_waddr_o; - output reg rf_ren_a_o; - output reg rf_ren_b_o; - output reg [5:0] alu_operator_o; - output reg [1:0] alu_op_a_mux_sel_o; - output reg alu_op_b_mux_sel_o; - output reg alu_multicycle_o; - output wire mult_en_o; - output wire div_en_o; - output reg mult_sel_o; - output reg div_sel_o; - output reg [1:0] multdiv_operator_o; - output reg [1:0] multdiv_signed_mode_o; - output reg csr_access_o; - output reg [1:0] csr_op_o; - output reg data_req_o; - output reg data_we_o; - output reg [1:0] data_type_o; - output reg data_sign_extension_o; - output reg jump_in_dec_o; - output reg branch_in_dec_o; - reg illegal_insn; - wire illegal_reg_rv32e; - reg csr_illegal; - reg rf_we; - wire [31:0] instr; - wire [31:0] instr_alu; - wire [9:0] unused_instr_alu; - wire [4:0] instr_rs1; - wire [4:0] instr_rs2; - wire [4:0] instr_rs3; - wire [4:0] instr_rd; - reg use_rs3_d; - reg use_rs3_q; - reg [1:0] csr_op; - reg [6:0] opcode; - reg [6:0] opcode_alu; - assign instr = instr_rdata_i; - assign instr_alu = instr_rdata_alu_i; - assign imm_i_type_o = {{20 {instr[31]}}, instr[31:20]}; - assign imm_s_type_o = {{20 {instr[31]}}, instr[31:25], instr[11:7]}; - assign imm_b_type_o = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; - assign imm_u_type_o = {instr[31:12], 12'b000000000000}; - assign imm_j_type_o = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; - assign zimm_rs1_type_o = {27'b000000000000000000000000000, instr_rs1}; - generate - if (RV32B != ibex_pkg_RV32BNone) begin : gen_rs3_flop - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - use_rs3_q <= 1'b0; - else - use_rs3_q <= use_rs3_d; - end - else begin : gen_no_rs3_flop - wire [1:1] sv2v_tmp_66FD5; - assign sv2v_tmp_66FD5 = use_rs3_d; - always @(*) use_rs3_q = sv2v_tmp_66FD5; - end - endgenerate - assign instr_rs1 = instr[19:15]; - assign instr_rs2 = instr[24:20]; - assign instr_rs3 = instr[31:27]; - assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i ? instr_rs3 : instr_rs1); - assign rf_raddr_b_o = instr_rs2; - assign instr_rd = instr[11:7]; - assign rf_waddr_o = instr_rd; - localparam [1:0] ibex_pkg_OP_A_REG_A = 0; - localparam [0:0] ibex_pkg_OP_B_REG_B = 0; - generate - if (RV32E) begin : gen_rv32e_reg_check_active - assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == ibex_pkg_OP_A_REG_A)) | (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == ibex_pkg_OP_B_REG_B))) | (rf_waddr_o[4] & rf_we); - end - else begin : gen_rv32e_reg_check_inactive - assign illegal_reg_rv32e = 1'b0; - end - endgenerate - localparam [1:0] ibex_pkg_CSR_OP_CLEAR = 3; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - always @(*) begin : csr_operand_check - csr_op_o = csr_op; - if (((csr_op == ibex_pkg_CSR_OP_SET) || (csr_op == ibex_pkg_CSR_OP_CLEAR)) && (instr_rs1 == {5 {1'sb0}})) - csr_op_o = ibex_pkg_CSR_OP_READ; - end - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - localparam [1:0] ibex_pkg_MD_OP_MULH = 1; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_REM = 3; - localparam [6:0] ibex_pkg_OPCODE_AUIPC = 7'h17; - localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63; - localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f; - localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67; - localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03; - localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37; - localparam [6:0] ibex_pkg_OPCODE_MISC_MEM = 7'h0f; - localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33; - localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13; - localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23; - localparam [6:0] ibex_pkg_OPCODE_SYSTEM = 7'h73; - localparam [0:0] ibex_pkg_RF_WD_CSR = 1; - localparam [0:0] ibex_pkg_RF_WD_EX = 0; - localparam integer ibex_pkg_RV32BBalanced = 1; - localparam integer ibex_pkg_RV32BFull = 2; - localparam integer ibex_pkg_RV32MNone = 0; - always @(*) begin - jump_in_dec_o = 1'b0; - jump_set_o = 1'b0; - branch_in_dec_o = 1'b0; - icache_inval_o = 1'b0; - multdiv_operator_o = ibex_pkg_MD_OP_MULL; - multdiv_signed_mode_o = 2'b00; - rf_wdata_sel_o = ibex_pkg_RF_WD_EX; - rf_we = 1'b0; - rf_ren_a_o = 1'b0; - rf_ren_b_o = 1'b0; - csr_access_o = 1'b0; - csr_illegal = 1'b0; - csr_op = ibex_pkg_CSR_OP_READ; - data_we_o = 1'b0; - data_type_o = 2'b00; - data_sign_extension_o = 1'b0; - data_req_o = 1'b0; - illegal_insn = 1'b0; - ebrk_insn_o = 1'b0; - mret_insn_o = 1'b0; - dret_insn_o = 1'b0; - ecall_insn_o = 1'b0; - wfi_insn_o = 1'b0; - opcode = instr[6:0]; - case (opcode) - ibex_pkg_OPCODE_JAL: begin - jump_in_dec_o = 1'b1; - if (instr_first_cycle_i) begin - rf_we = BranchTargetALU; - jump_set_o = 1'b1; - end - else - rf_we = 1'b1; - end - ibex_pkg_OPCODE_JALR: begin - jump_in_dec_o = 1'b1; - if (instr_first_cycle_i) begin - rf_we = BranchTargetALU; - jump_set_o = 1'b1; - end - else - rf_we = 1'b1; - if (instr[14:12] != 3'b000) - illegal_insn = 1'b1; - rf_ren_a_o = 1'b1; - end - ibex_pkg_OPCODE_BRANCH: begin - branch_in_dec_o = 1'b1; - case (instr[14:12]) - 3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: illegal_insn = 1'b0; - default: illegal_insn = 1'b1; - endcase - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - end - ibex_pkg_OPCODE_STORE: begin - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - data_req_o = 1'b1; - data_we_o = 1'b1; - if (instr[14]) - illegal_insn = 1'b1; - case (instr[13:12]) - 2'b00: data_type_o = 2'b10; - 2'b01: data_type_o = 2'b01; - 2'b10: data_type_o = 2'b00; - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_LOAD: begin - rf_ren_a_o = 1'b1; - data_req_o = 1'b1; - data_type_o = 2'b00; - data_sign_extension_o = ~instr[14]; - case (instr[13:12]) - 2'b00: data_type_o = 2'b10; - 2'b01: data_type_o = 2'b01; - 2'b10: begin - data_type_o = 2'b00; - if (instr[14]) - illegal_insn = 1'b1; - end - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_LUI: rf_we = 1'b1; - ibex_pkg_OPCODE_AUIPC: rf_we = 1'b1; - ibex_pkg_OPCODE_OP_IMM: begin - rf_ren_a_o = 1'b1; - rf_we = 1'b1; - case (instr[14:12]) - 3'b000, 3'b010, 3'b011, 3'b100, 3'b110, 3'b111: illegal_insn = 1'b0; - 3'b001: - case (instr[31:27]) - 5'b00000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); - 5'b00100, 5'b01001, 5'b00101, 5'b01101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 5'b00001: - if (instr[26] == 1'b0) - illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - 5'b01100: - case (instr[26:20]) - 7'b0000000, 7'b0000001, 7'b0000010, 7'b0000100, 7'b0000101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 7'b0010000, 7'b0010001, 7'b0010010, 7'b0011000, 7'b0011001, 7'b0011010: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - default: illegal_insn = 1'b1; - endcase - default: illegal_insn = 1'b1; - endcase - 3'b101: - if (instr[26]) - illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - else - case (instr[31:27]) - 5'b00000, 5'b01000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); - 5'b00100, 5'b01100, 5'b01001: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - 5'b01101: - if (RV32B == ibex_pkg_RV32BFull) - illegal_insn = 1'b0; - else - case (instr[24:20]) - 5'b11111, 5'b11000: illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1); - default: illegal_insn = 1'b1; - endcase - 5'b00101: - if (RV32B == ibex_pkg_RV32BFull) - illegal_insn = 1'b0; - else if (instr[24:20] == 5'b00111) - illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - 5'b00001: - if (instr[26] == 1'b0) - illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - else - illegal_insn = 1'b1; - default: illegal_insn = 1'b1; - endcase - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_OP: begin - rf_ren_a_o = 1'b1; - rf_ren_b_o = 1'b1; - rf_we = 1'b1; - if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) - illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - else - case ({instr[31:25], instr[14:12]}) - {7'b0000000, 3'b000}, {7'b0100000, 3'b000}, {7'b0000000, 3'b010}, {7'b0000000, 3'b011}, {7'b0000000, 3'b100}, {7'b0000000, 3'b110}, {7'b0000000, 3'b111}, {7'b0000000, 3'b001}, {7'b0000000, 3'b101}, {7'b0100000, 3'b101}: illegal_insn = 1'b0; - {7'b0100000, 3'b111}, {7'b0100000, 3'b110}, {7'b0100000, 3'b100}, {7'b0010000, 3'b001}, {7'b0010000, 3'b101}, {7'b0110000, 3'b001}, {7'b0110000, 3'b101}, {7'b0000101, 3'b100}, {7'b0000101, 3'b101}, {7'b0000101, 3'b110}, {7'b0000101, 3'b111}, {7'b0000100, 3'b100}, {7'b0100100, 3'b100}, {7'b0000100, 3'b111}, {7'b0100100, 3'b001}, {7'b0010100, 3'b001}, {7'b0110100, 3'b001}, {7'b0100100, 3'b101}, {7'b0100100, 3'b111}: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1); - {7'b0100100, 3'b110}, {7'b0000100, 3'b110}, {7'b0110100, 3'b101}, {7'b0010100, 3'b101}, {7'b0000100, 3'b001}, {7'b0000100, 3'b101}, {7'b0000101, 3'b001}, {7'b0000101, 3'b010}, {7'b0000101, 3'b011}: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1); - {7'b0000001, 3'b000}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULL; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b001}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b010}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b01; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b011}: begin - multdiv_operator_o = ibex_pkg_MD_OP_MULH; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b100}: begin - multdiv_operator_o = ibex_pkg_MD_OP_DIV; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b101}: begin - multdiv_operator_o = ibex_pkg_MD_OP_DIV; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b110}: begin - multdiv_operator_o = ibex_pkg_MD_OP_REM; - multdiv_signed_mode_o = 2'b11; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - {7'b0000001, 3'b111}: begin - multdiv_operator_o = ibex_pkg_MD_OP_REM; - multdiv_signed_mode_o = 2'b00; - illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0); - end - default: illegal_insn = 1'b1; - endcase - end - ibex_pkg_OPCODE_MISC_MEM: - case (instr[14:12]) - 3'b000: rf_we = 1'b0; - 3'b001: begin - jump_in_dec_o = 1'b1; - rf_we = 1'b0; - if (instr_first_cycle_i) begin - jump_set_o = 1'b1; - icache_inval_o = 1'b1; - end - end - default: illegal_insn = 1'b1; - endcase - ibex_pkg_OPCODE_SYSTEM: - if (instr[14:12] == 3'b000) begin - case (instr[31:20]) - 12'h000: ecall_insn_o = 1'b1; - 12'h001: ebrk_insn_o = 1'b1; - 12'h302: mret_insn_o = 1'b1; - 12'h7b2: dret_insn_o = 1'b1; - 12'h105: wfi_insn_o = 1'b1; - default: illegal_insn = 1'b1; - endcase - if ((instr_rs1 != 5'b00000) || (instr_rd != 5'b00000)) - illegal_insn = 1'b1; - end - else begin - csr_access_o = 1'b1; - rf_wdata_sel_o = ibex_pkg_RF_WD_CSR; - rf_we = 1'b1; - if (~instr[14]) - rf_ren_a_o = 1'b1; - case (instr[13:12]) - 2'b01: csr_op = ibex_pkg_CSR_OP_WRITE; - 2'b10: csr_op = ibex_pkg_CSR_OP_SET; - 2'b11: csr_op = ibex_pkg_CSR_OP_CLEAR; - default: csr_illegal = 1'b1; - endcase - illegal_insn = csr_illegal; - end - default: illegal_insn = 1'b1; - endcase - if (illegal_c_insn_i) - illegal_insn = 1'b1; - if (illegal_insn) begin - rf_we = 1'b0; - data_req_o = 1'b0; - data_we_o = 1'b0; - jump_in_dec_o = 1'b0; - jump_set_o = 1'b0; - branch_in_dec_o = 1'b0; - csr_access_o = 1'b0; - end - end - localparam [5:0] ibex_pkg_ALU_ADD = 0; - localparam [5:0] ibex_pkg_ALU_AND = 4; - localparam [5:0] ibex_pkg_ALU_ANDN = 7; - localparam [5:0] ibex_pkg_ALU_BDEP = 48; - localparam [5:0] ibex_pkg_ALU_BEXT = 47; - localparam [5:0] ibex_pkg_ALU_BFP = 49; - localparam [5:0] ibex_pkg_ALU_CLMUL = 50; - localparam [5:0] ibex_pkg_ALU_CLMULH = 52; - localparam [5:0] ibex_pkg_ALU_CLMULR = 51; - localparam [5:0] ibex_pkg_ALU_CLZ = 34; - localparam [5:0] ibex_pkg_ALU_CMIX = 40; - localparam [5:0] ibex_pkg_ALU_CMOV = 39; - localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54; - localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56; - localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58; - localparam [5:0] ibex_pkg_ALU_CRC32_B = 53; - localparam [5:0] ibex_pkg_ALU_CRC32_H = 55; - localparam [5:0] ibex_pkg_ALU_CRC32_W = 57; - localparam [5:0] ibex_pkg_ALU_CTZ = 35; - localparam [5:0] ibex_pkg_ALU_EQ = 23; - localparam [5:0] ibex_pkg_ALU_FSL = 41; - localparam [5:0] ibex_pkg_ALU_FSR = 42; - localparam [5:0] ibex_pkg_ALU_GE = 21; - localparam [5:0] ibex_pkg_ALU_GEU = 22; - localparam [5:0] ibex_pkg_ALU_GORC = 16; - localparam [5:0] ibex_pkg_ALU_GREV = 15; - localparam [5:0] ibex_pkg_ALU_LT = 19; - localparam [5:0] ibex_pkg_ALU_LTU = 20; - localparam [5:0] ibex_pkg_ALU_MAX = 27; - localparam [5:0] ibex_pkg_ALU_MAXU = 28; - localparam [5:0] ibex_pkg_ALU_MIN = 25; - localparam [5:0] ibex_pkg_ALU_MINU = 26; - localparam [5:0] ibex_pkg_ALU_NE = 24; - localparam [5:0] ibex_pkg_ALU_OR = 3; - localparam [5:0] ibex_pkg_ALU_ORN = 6; - localparam [5:0] ibex_pkg_ALU_PACK = 29; - localparam [5:0] ibex_pkg_ALU_PACKH = 31; - localparam [5:0] ibex_pkg_ALU_PACKU = 30; - localparam [5:0] ibex_pkg_ALU_PCNT = 36; - localparam [5:0] ibex_pkg_ALU_ROL = 14; - localparam [5:0] ibex_pkg_ALU_ROR = 13; - localparam [5:0] ibex_pkg_ALU_SBCLR = 44; - localparam [5:0] ibex_pkg_ALU_SBEXT = 46; - localparam [5:0] ibex_pkg_ALU_SBINV = 45; - localparam [5:0] ibex_pkg_ALU_SBSET = 43; - localparam [5:0] ibex_pkg_ALU_SEXTB = 32; - localparam [5:0] ibex_pkg_ALU_SEXTH = 33; - localparam [5:0] ibex_pkg_ALU_SHFL = 17; - localparam [5:0] ibex_pkg_ALU_SLL = 10; - localparam [5:0] ibex_pkg_ALU_SLO = 12; - localparam [5:0] ibex_pkg_ALU_SLT = 37; - localparam [5:0] ibex_pkg_ALU_SLTU = 38; - localparam [5:0] ibex_pkg_ALU_SRA = 8; - localparam [5:0] ibex_pkg_ALU_SRL = 9; - localparam [5:0] ibex_pkg_ALU_SRO = 11; - localparam [5:0] ibex_pkg_ALU_SUB = 1; - localparam [5:0] ibex_pkg_ALU_UNSHFL = 18; - localparam [5:0] ibex_pkg_ALU_XNOR = 5; - localparam [5:0] ibex_pkg_ALU_XOR = 2; - localparam [0:0] ibex_pkg_IMM_A_Z = 0; - localparam [0:0] ibex_pkg_IMM_A_ZERO = 1; - localparam [2:0] ibex_pkg_IMM_B_B = 2; - localparam [2:0] ibex_pkg_IMM_B_I = 0; - localparam [2:0] ibex_pkg_IMM_B_INCR_PC = 5; - localparam [2:0] ibex_pkg_IMM_B_J = 4; - localparam [2:0] ibex_pkg_IMM_B_S = 1; - localparam [2:0] ibex_pkg_IMM_B_U = 3; - localparam [1:0] ibex_pkg_OP_A_CURRPC = 2; - localparam [1:0] ibex_pkg_OP_A_IMM = 3; - localparam [0:0] ibex_pkg_OP_B_IMM = 1; - always @(*) begin - alu_operator_o = ibex_pkg_ALU_SLTU; - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_I; - opcode_alu = instr_alu[6:0]; - use_rs3_d = 1'b0; - alu_multicycle_o = 1'b0; - mult_sel_o = 1'b0; - div_sel_o = 1'b0; - case (opcode_alu) - ibex_pkg_OPCODE_JAL: begin - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_J; - end - if (instr_first_cycle_i && !BranchTargetALU) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_J; - alu_operator_o = ibex_pkg_ALU_ADD; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_JALR: begin - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - bt_b_mux_sel_o = ibex_pkg_IMM_B_I; - end - if (instr_first_cycle_i && !BranchTargetALU) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - alu_operator_o = ibex_pkg_ALU_ADD; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_BRANCH: begin - case (instr_alu[14:12]) - 3'b000: alu_operator_o = ibex_pkg_ALU_EQ; - 3'b001: alu_operator_o = ibex_pkg_ALU_NE; - 3'b100: alu_operator_o = ibex_pkg_ALU_LT; - 3'b101: alu_operator_o = ibex_pkg_ALU_GE; - 3'b110: alu_operator_o = ibex_pkg_ALU_LTU; - 3'b111: alu_operator_o = ibex_pkg_ALU_GEU; - default: - ; - endcase - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC); - end - if (instr_first_cycle_i) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC); - alu_operator_o = ibex_pkg_ALU_ADD; - end - end - ibex_pkg_OPCODE_STORE: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - alu_operator_o = ibex_pkg_ALU_ADD; - if (!instr_alu[14]) begin - imm_b_mux_sel_o = ibex_pkg_IMM_B_S; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - end - ibex_pkg_OPCODE_LOAD: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_operator_o = ibex_pkg_ALU_ADD; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - end - ibex_pkg_OPCODE_LUI: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO; - imm_b_mux_sel_o = ibex_pkg_IMM_B_U; - alu_operator_o = ibex_pkg_ALU_ADD; - end - ibex_pkg_OPCODE_AUIPC: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_U; - alu_operator_o = ibex_pkg_ALU_ADD; - end - ibex_pkg_OPCODE_OP_IMM: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - case (instr_alu[14:12]) - 3'b000: alu_operator_o = ibex_pkg_ALU_ADD; - 3'b010: alu_operator_o = ibex_pkg_ALU_SLT; - 3'b011: alu_operator_o = ibex_pkg_ALU_SLTU; - 3'b100: alu_operator_o = ibex_pkg_ALU_XOR; - 3'b110: alu_operator_o = ibex_pkg_ALU_OR; - 3'b111: alu_operator_o = ibex_pkg_ALU_AND; - 3'b001: - if (RV32B != ibex_pkg_RV32BNone) - case (instr_alu[31:27]) - 5'b00000: alu_operator_o = ibex_pkg_ALU_SLL; - 5'b00100: alu_operator_o = ibex_pkg_ALU_SLO; - 5'b01001: alu_operator_o = ibex_pkg_ALU_SBCLR; - 5'b00101: alu_operator_o = ibex_pkg_ALU_SBSET; - 5'b01101: alu_operator_o = ibex_pkg_ALU_SBINV; - 5'b00001: - if (instr_alu[26] == 0) - alu_operator_o = ibex_pkg_ALU_SHFL; - 5'b01100: - case (instr_alu[26:20]) - 7'b0000000: alu_operator_o = ibex_pkg_ALU_CLZ; - 7'b0000001: alu_operator_o = ibex_pkg_ALU_CTZ; - 7'b0000010: alu_operator_o = ibex_pkg_ALU_PCNT; - 7'b0000100: alu_operator_o = ibex_pkg_ALU_SEXTB; - 7'b0000101: alu_operator_o = ibex_pkg_ALU_SEXTH; - 7'b0010000: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_B; - alu_multicycle_o = 1'b1; - end - 7'b0010001: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_H; - alu_multicycle_o = 1'b1; - end - 7'b0010010: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32_W; - alu_multicycle_o = 1'b1; - end - 7'b0011000: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_B; - alu_multicycle_o = 1'b1; - end - 7'b0011001: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_H; - alu_multicycle_o = 1'b1; - end - 7'b0011010: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_CRC32C_W; - alu_multicycle_o = 1'b1; - end - default: - ; - endcase - default: - ; - endcase - else - alu_operator_o = ibex_pkg_ALU_SLL; - 3'b101: - if (RV32B != ibex_pkg_RV32BNone) begin - if (instr_alu[26] == 1'b1) begin - alu_operator_o = ibex_pkg_ALU_FSR; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - else - case (instr_alu[31:27]) - 5'b00000: alu_operator_o = ibex_pkg_ALU_SRL; - 5'b01000: alu_operator_o = ibex_pkg_ALU_SRA; - 5'b00100: alu_operator_o = ibex_pkg_ALU_SRO; - 5'b01001: alu_operator_o = ibex_pkg_ALU_SBEXT; - 5'b01100: begin - alu_operator_o = ibex_pkg_ALU_ROR; - alu_multicycle_o = 1'b1; - end - 5'b01101: alu_operator_o = ibex_pkg_ALU_GREV; - 5'b00101: alu_operator_o = ibex_pkg_ALU_GORC; - 5'b00001: - if (RV32B == ibex_pkg_RV32BFull) - if (instr_alu[26] == 1'b0) - alu_operator_o = ibex_pkg_ALU_UNSHFL; - default: - ; - endcase - end - else if (instr_alu[31:27] == 5'b00000) - alu_operator_o = ibex_pkg_ALU_SRL; - else if (instr_alu[31:27] == 5'b01000) - alu_operator_o = ibex_pkg_ALU_SRA; - default: - ; - endcase - end - ibex_pkg_OPCODE_OP: begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B; - if (instr_alu[26]) begin - if (RV32B != ibex_pkg_RV32BNone) - case ({instr_alu[26:25], instr_alu[14:12]}) - {2'b11, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_CMIX; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b11, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_CMOV; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b10, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_FSL; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - {2'b10, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_FSR; - alu_multicycle_o = 1'b1; - if (instr_first_cycle_i) - use_rs3_d = 1'b1; - else - use_rs3_d = 1'b0; - end - default: - ; - endcase - end - else - case ({instr_alu[31:25], instr_alu[14:12]}) - {7'b0000000, 3'b000}: alu_operator_o = ibex_pkg_ALU_ADD; - {7'b0100000, 3'b000}: alu_operator_o = ibex_pkg_ALU_SUB; - {7'b0000000, 3'b010}: alu_operator_o = ibex_pkg_ALU_SLT; - {7'b0000000, 3'b011}: alu_operator_o = ibex_pkg_ALU_SLTU; - {7'b0000000, 3'b100}: alu_operator_o = ibex_pkg_ALU_XOR; - {7'b0000000, 3'b110}: alu_operator_o = ibex_pkg_ALU_OR; - {7'b0000000, 3'b111}: alu_operator_o = ibex_pkg_ALU_AND; - {7'b0000000, 3'b001}: alu_operator_o = ibex_pkg_ALU_SLL; - {7'b0000000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRL; - {7'b0100000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRA; - {7'b0010000, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SLO; - {7'b0010000, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SRO; - {7'b0110000, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) begin - alu_operator_o = ibex_pkg_ALU_ROL; - alu_multicycle_o = 1'b1; - end - {7'b0110000, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) begin - alu_operator_o = ibex_pkg_ALU_ROR; - alu_multicycle_o = 1'b1; - end - {7'b0000101, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MIN; - {7'b0000101, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MAX; - {7'b0000101, 3'b110}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MINU; - {7'b0000101, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_MAXU; - {7'b0000100, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACK; - {7'b0100100, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACKU; - {7'b0000100, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_PACKH; - {7'b0100000, 3'b100}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_XNOR; - {7'b0100000, 3'b110}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_ORN; - {7'b0100000, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_ANDN; - {7'b0100100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBCLR; - {7'b0010100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBSET; - {7'b0110100, 3'b001}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBINV; - {7'b0100100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_SBEXT; - {7'b0100100, 3'b111}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_BFP; - {7'b0110100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_GREV; - {7'b0010100, 3'b101}: - if (RV32B != ibex_pkg_RV32BNone) - alu_operator_o = ibex_pkg_ALU_GORC; - {7'b0000100, 3'b001}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_SHFL; - {7'b0000100, 3'b101}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_UNSHFL; - {7'b0000101, 3'b001}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMUL; - {7'b0000101, 3'b010}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMULR; - {7'b0000101, 3'b011}: - if (RV32B == ibex_pkg_RV32BFull) - alu_operator_o = ibex_pkg_ALU_CLMULH; - {7'b0100100, 3'b110}: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_BDEP; - alu_multicycle_o = 1'b1; - end - {7'b0000100, 3'b110}: - if (RV32B == ibex_pkg_RV32BFull) begin - alu_operator_o = ibex_pkg_ALU_BEXT; - alu_multicycle_o = 1'b1; - end - {7'b0000001, 3'b000}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b001}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b010}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b011}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b100}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b101}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b110}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - {7'b0000001, 3'b111}: begin - alu_operator_o = ibex_pkg_ALU_ADD; - div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1); - end - default: - ; - endcase - end - ibex_pkg_OPCODE_MISC_MEM: - case (instr_alu[14:12]) - 3'b000: begin - alu_operator_o = ibex_pkg_ALU_ADD; - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - 3'b001: - if (BranchTargetALU) begin - bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - bt_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - end - else begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC; - alu_operator_o = ibex_pkg_ALU_ADD; - end - default: - ; - endcase - ibex_pkg_OPCODE_SYSTEM: - if (instr_alu[14:12] == 3'b000) begin - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - end - else begin - alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM; - imm_a_mux_sel_o = ibex_pkg_IMM_A_Z; - imm_b_mux_sel_o = ibex_pkg_IMM_B_I; - if (instr_alu[14]) - alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM; - else - alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A; - end - default: - ; - endcase - end - assign mult_en_o = (illegal_insn ? 1'b0 : mult_sel_o); - assign div_en_o = (illegal_insn ? 1'b0 : div_sel_o); - assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; - assign rf_we_o = rf_we & ~illegal_reg_rv32e; - assign unused_instr_alu = {instr_alu[19:15], instr_alu[11:7]}; -endmodule diff --git a/flow/designs/src/ibex/ibex_dummy_instr.v b/flow/designs/src/ibex/ibex_dummy_instr.v deleted file mode 100644 index e38acb35a3..0000000000 --- a/flow/designs/src/ibex/ibex_dummy_instr.v +++ /dev/null @@ -1,104 +0,0 @@ -module ibex_dummy_instr ( - clk_i, - rst_ni, - dummy_instr_en_i, - dummy_instr_mask_i, - dummy_instr_seed_en_i, - dummy_instr_seed_i, - fetch_valid_i, - id_in_ready_i, - insert_dummy_instr_o, - dummy_instr_data_o -); - input wire clk_i; - input wire rst_ni; - input wire dummy_instr_en_i; - input wire [2:0] dummy_instr_mask_i; - input wire dummy_instr_seed_en_i; - input wire [31:0] dummy_instr_seed_i; - input wire fetch_valid_i; - input wire id_in_ready_i; - output wire insert_dummy_instr_o; - output wire [31:0] dummy_instr_data_o; - localparam [31:0] TIMEOUT_CNT_W = 5; - localparam [31:0] OP_W = 5; - localparam [31:0] LFSR_OUT_W = ((2 + OP_W) + OP_W) + TIMEOUT_CNT_W; - wire [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] lfsr_data; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_incr; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_threshold; - wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_d; - reg [TIMEOUT_CNT_W - 1:0] dummy_cnt_q; - wire dummy_cnt_en; - wire lfsr_en; - wire [LFSR_OUT_W - 1:0] lfsr_state; - wire insert_dummy_instr; - reg [6:0] dummy_set; - reg [2:0] dummy_opcode; - wire [31:0] dummy_instr; - reg [31:0] dummy_instr_seed_q; - wire [31:0] dummy_instr_seed_d; - assign lfsr_en = insert_dummy_instr & id_in_ready_i; - assign dummy_instr_seed_d = dummy_instr_seed_q ^ dummy_instr_seed_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_instr_seed_q <= {32 {1'sb0}}; - else if (dummy_instr_seed_en_i) - dummy_instr_seed_q <= dummy_instr_seed_d; - prim_lfsr #( - .LfsrDw(32), - .StateOutDw(LFSR_OUT_W) - ) lfsr_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .seed_en_i(dummy_instr_seed_en_i), - .seed_i(dummy_instr_seed_d), - .lfsr_en_i(lfsr_en), - .entropy_i('0), - .state_o(lfsr_state) - ); - function automatic [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] sv2v_cast_4AF33; - input reg [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] inp; - sv2v_cast_4AF33 = inp; - endfunction - assign lfsr_data = sv2v_cast_4AF33(lfsr_state); - assign dummy_cnt_threshold = lfsr_data[TIMEOUT_CNT_W - 1-:TIMEOUT_CNT_W] & {dummy_instr_mask_i, {TIMEOUT_CNT_W - 3 {1'b1}}}; - assign dummy_cnt_incr = dummy_cnt_q + {{TIMEOUT_CNT_W - 1 {1'b0}}, 1'b1}; - assign dummy_cnt_d = (insert_dummy_instr ? {TIMEOUT_CNT_W {1'sb0}} : dummy_cnt_incr); - assign dummy_cnt_en = (dummy_instr_en_i & id_in_ready_i) & (fetch_valid_i | insert_dummy_instr); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_cnt_q <= {TIMEOUT_CNT_W {1'sb0}}; - else if (dummy_cnt_en) - dummy_cnt_q <= dummy_cnt_d; - assign insert_dummy_instr = dummy_instr_en_i & (dummy_cnt_q == dummy_cnt_threshold); - localparam [1:0] DUMMY_ADD = 2'b00; - localparam [1:0] DUMMY_AND = 2'b11; - localparam [1:0] DUMMY_DIV = 2'b10; - localparam [1:0] DUMMY_MUL = 2'b01; - always @(*) - case (lfsr_data[2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))-:((2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) >= (OP_W + (OP_W + TIMEOUT_CNT_W)) ? ((2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) - (OP_W + (OP_W + TIMEOUT_CNT_W))) + 1 : ((OP_W + (OP_W + TIMEOUT_CNT_W)) - (2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1))))) + 1)]) - DUMMY_ADD: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b000; - end - DUMMY_MUL: begin - dummy_set = 7'b0000001; - dummy_opcode = 3'b000; - end - DUMMY_DIV: begin - dummy_set = 7'b0000001; - dummy_opcode = 3'b100; - end - DUMMY_AND: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b111; - end - default: begin - dummy_set = 7'b0000000; - dummy_opcode = 3'b000; - end - endcase - assign dummy_instr = {dummy_set, lfsr_data[OP_W + (OP_W + (TIMEOUT_CNT_W - 1))-:((OP_W + (OP_W + (TIMEOUT_CNT_W - 1))) >= (OP_W + TIMEOUT_CNT_W) ? ((OP_W + (OP_W + (TIMEOUT_CNT_W - 1))) - (OP_W + TIMEOUT_CNT_W)) + 1 : ((OP_W + TIMEOUT_CNT_W) - (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) + 1)], lfsr_data[OP_W + (TIMEOUT_CNT_W - 1)-:((OP_W + (TIMEOUT_CNT_W - 1)) >= TIMEOUT_CNT_W ? ((OP_W + (TIMEOUT_CNT_W - 1)) - TIMEOUT_CNT_W) + 1 : (TIMEOUT_CNT_W - (OP_W + (TIMEOUT_CNT_W - 1))) + 1)], dummy_opcode, 5'h00, 7'h33}; - assign insert_dummy_instr_o = insert_dummy_instr; - assign dummy_instr_data_o = dummy_instr; -endmodule diff --git a/flow/designs/src/ibex/ibex_ex_block.v b/flow/designs/src/ibex/ibex_ex_block.v deleted file mode 100644 index 91eeb2f268..0000000000 --- a/flow/designs/src/ibex/ibex_ex_block.v +++ /dev/null @@ -1,179 +0,0 @@ -module ibex_ex_block ( - clk_i, - rst_ni, - alu_operator_i, - alu_operand_a_i, - alu_operand_b_i, - alu_instr_first_cycle_i, - bt_a_operand_i, - bt_b_operand_i, - multdiv_operator_i, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - multdiv_signed_mode_i, - multdiv_operand_a_i, - multdiv_operand_b_i, - multdiv_ready_id_i, - data_ind_timing_i, - imd_val_we_o, - imd_val_d_o, - imd_val_q_i, - alu_adder_result_ex_o, - result_ex_o, - branch_target_o, - branch_decision_o, - ex_valid_o -); - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] BranchTargetALU = 0; - input wire clk_i; - input wire rst_ni; - input wire [5:0] alu_operator_i; - input wire [31:0] alu_operand_a_i; - input wire [31:0] alu_operand_b_i; - input wire alu_instr_first_cycle_i; - input wire [31:0] bt_a_operand_i; - input wire [31:0] bt_b_operand_i; - input wire [1:0] multdiv_operator_i; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] multdiv_signed_mode_i; - input wire [31:0] multdiv_operand_a_i; - input wire [31:0] multdiv_operand_b_i; - input wire multdiv_ready_id_i; - input wire data_ind_timing_i; - output wire [1:0] imd_val_we_o; - output wire [67:0] imd_val_d_o; - input wire [67:0] imd_val_q_i; - output wire [31:0] alu_adder_result_ex_o; - output wire [31:0] result_ex_o; - output wire [31:0] branch_target_o; - output wire branch_decision_o; - output wire ex_valid_o; - wire [31:0] alu_result; - wire [31:0] multdiv_result; - wire [32:0] multdiv_alu_operand_b; - wire [32:0] multdiv_alu_operand_a; - wire [33:0] alu_adder_result_ext; - wire alu_cmp_result; - wire alu_is_equal_result; - wire multdiv_valid; - wire multdiv_sel; - wire [63:0] alu_imd_val_q; - wire [63:0] alu_imd_val_d; - wire [1:0] alu_imd_val_we; - wire [67:0] multdiv_imd_val_d; - wire [1:0] multdiv_imd_val_we; - localparam integer ibex_pkg_RV32MNone = 0; - generate - if (RV32M != ibex_pkg_RV32MNone) begin : gen_multdiv_m - assign multdiv_sel = mult_sel_i | div_sel_i; - end - else begin : gen_multdiv_no_m - assign multdiv_sel = 1'b0; - end - endgenerate - assign imd_val_d_o[34+:34] = (multdiv_sel ? multdiv_imd_val_d[34+:34] : {2'b00, alu_imd_val_d[32+:32]}); - assign imd_val_d_o[0+:34] = (multdiv_sel ? multdiv_imd_val_d[0+:34] : {2'b00, alu_imd_val_d[0+:32]}); - assign imd_val_we_o = (multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we); - assign alu_imd_val_q = {imd_val_q_i[65-:32], imd_val_q_i[31-:32]}; - assign result_ex_o = (multdiv_sel ? multdiv_result : alu_result); - assign branch_decision_o = alu_cmp_result; - generate - if (BranchTargetALU) begin : g_branch_target_alu - wire [32:0] bt_alu_result; - wire unused_bt_carry; - assign bt_alu_result = bt_a_operand_i + bt_b_operand_i; - assign unused_bt_carry = bt_alu_result[32]; - assign branch_target_o = bt_alu_result[31:0]; - end - else begin : g_no_branch_target_alu - wire [31:0] unused_bt_a_operand; - wire [31:0] unused_bt_b_operand; - assign unused_bt_a_operand = bt_a_operand_i; - assign unused_bt_b_operand = bt_b_operand_i; - assign branch_target_o = alu_adder_result_ex_o; - end - endgenerate - ibex_alu #(.RV32B(RV32B)) alu_i( - .operator_i(alu_operator_i), - .operand_a_i(alu_operand_a_i), - .operand_b_i(alu_operand_b_i), - .instr_first_cycle_i(alu_instr_first_cycle_i), - .imd_val_q_i(alu_imd_val_q), - .imd_val_we_o(alu_imd_val_we), - .imd_val_d_o(alu_imd_val_d), - .multdiv_operand_a_i(multdiv_alu_operand_a), - .multdiv_operand_b_i(multdiv_alu_operand_b), - .multdiv_sel_i(multdiv_sel), - .adder_result_o(alu_adder_result_ex_o), - .adder_result_ext_o(alu_adder_result_ext), - .result_o(alu_result), - .comparison_result_o(alu_cmp_result), - .is_equal_result_o(alu_is_equal_result) - ); - localparam integer ibex_pkg_RV32MSingleCycle = 3; - localparam integer ibex_pkg_RV32MSlow = 1; - generate - if (RV32M == ibex_pkg_RV32MSlow) begin : gen_multdiv_slow - ibex_multdiv_slow multdiv_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .mult_en_i(mult_en_i), - .div_en_i(div_en_i), - .mult_sel_i(mult_sel_i), - .div_sel_i(div_sel_i), - .operator_i(multdiv_operator_i), - .signed_mode_i(multdiv_signed_mode_i), - .op_a_i(multdiv_operand_a_i), - .op_b_i(multdiv_operand_b_i), - .alu_adder_ext_i(alu_adder_result_ext), - .alu_adder_i(alu_adder_result_ex_o), - .equal_to_zero_i(alu_is_equal_result), - .data_ind_timing_i(data_ind_timing_i), - .valid_o(multdiv_valid), - .alu_operand_a_o(multdiv_alu_operand_a), - .alu_operand_b_o(multdiv_alu_operand_b), - .imd_val_q_i(imd_val_q_i), - .imd_val_d_o(multdiv_imd_val_d), - .imd_val_we_o(multdiv_imd_val_we), - .multdiv_ready_id_i(multdiv_ready_id_i), - .multdiv_result_o(multdiv_result) - ); - end - else if ((RV32M == ibex_pkg_RV32MFast) || (RV32M == ibex_pkg_RV32MSingleCycle)) begin : gen_multdiv_fast - ibex_multdiv_fast #(.RV32M(RV32M)) multdiv_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .mult_en_i(mult_en_i), - .div_en_i(div_en_i), - .mult_sel_i(mult_sel_i), - .div_sel_i(div_sel_i), - .operator_i(multdiv_operator_i), - .signed_mode_i(multdiv_signed_mode_i), - .op_a_i(multdiv_operand_a_i), - .op_b_i(multdiv_operand_b_i), - .alu_operand_a_o(multdiv_alu_operand_a), - .alu_operand_b_o(multdiv_alu_operand_b), - .alu_adder_ext_i(alu_adder_result_ext), - .alu_adder_i(alu_adder_result_ex_o), - .equal_to_zero_i(alu_is_equal_result), - .data_ind_timing_i(data_ind_timing_i), - .imd_val_q_i(imd_val_q_i), - .imd_val_d_o(multdiv_imd_val_d), - .imd_val_we_o(multdiv_imd_val_we), - .multdiv_ready_id_i(multdiv_ready_id_i), - .valid_o(multdiv_valid), - .multdiv_result_o(multdiv_result) - ); - end - endgenerate - assign ex_valid_o = (multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we)); -endmodule diff --git a/flow/designs/src/ibex/ibex_fetch_fifo.v b/flow/designs/src/ibex/ibex_fetch_fifo.v deleted file mode 100644 index e83b98c504..0000000000 --- a/flow/designs/src/ibex/ibex_fetch_fifo.v +++ /dev/null @@ -1,136 +0,0 @@ -module ibex_fetch_fifo ( - clk_i, - rst_ni, - clear_i, - busy_o, - in_valid_i, - in_addr_i, - in_rdata_i, - in_err_i, - out_valid_o, - out_ready_i, - out_addr_o, - out_addr_next_o, - out_rdata_o, - out_err_o, - out_err_plus2_o -); - parameter [31:0] NUM_REQS = 2; - input wire clk_i; - input wire rst_ni; - input wire clear_i; - output wire [NUM_REQS - 1:0] busy_o; - input wire in_valid_i; - input wire [31:0] in_addr_i; - input wire [31:0] in_rdata_i; - input wire in_err_i; - output reg out_valid_o; - input wire out_ready_i; - output wire [31:0] out_addr_o; - output wire [31:0] out_addr_next_o; - output reg [31:0] out_rdata_o; - output reg out_err_o; - output reg out_err_plus2_o; - localparam [31:0] DEPTH = NUM_REQS + 1; - wire [(DEPTH * 32) - 1:0] rdata_d; - reg [(DEPTH * 32) - 1:0] rdata_q; - wire [DEPTH - 1:0] err_d; - reg [DEPTH - 1:0] err_q; - wire [DEPTH - 1:0] valid_d; - reg [DEPTH - 1:0] valid_q; - wire [DEPTH - 1:0] lowest_free_entry; - wire [DEPTH - 1:0] valid_pushed; - wire [DEPTH - 1:0] valid_popped; - wire [DEPTH - 1:0] entry_en; - wire pop_fifo; - wire [31:0] rdata; - wire [31:0] rdata_unaligned; - wire err; - wire err_unaligned; - wire err_plus2; - wire valid; - wire valid_unaligned; - wire aligned_is_compressed; - wire unaligned_is_compressed; - wire addr_incr_two; - wire [31:1] instr_addr_next; - wire [31:1] instr_addr_d; - reg [31:1] instr_addr_q; - wire instr_addr_en; - wire unused_addr_in; - assign rdata = (valid_q[0] ? rdata_q[0+:32] : in_rdata_i); - assign err = (valid_q[0] ? err_q[0] : in_err_i); - assign valid = valid_q[0] | in_valid_i; - assign rdata_unaligned = (valid_q[1] ? {rdata_q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]}); - assign err_unaligned = (valid_q[1] ? (err_q[1] & ~unaligned_is_compressed) | err_q[0] : (valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))); - assign err_plus2 = (valid_q[1] ? err_q[1] & ~err_q[0] : (in_err_i & valid_q[0]) & ~err_q[0]); - assign valid_unaligned = (valid_q[1] ? 1'b1 : valid_q[0] & in_valid_i); - assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err; - assign aligned_is_compressed = (rdata[1:0] != 2'b11) & ~err; - always @(*) - if (out_addr_o[1]) begin - out_rdata_o = rdata_unaligned; - out_err_o = err_unaligned; - out_err_plus2_o = err_plus2; - if (unaligned_is_compressed) - out_valid_o = valid; - else - out_valid_o = valid_unaligned; - end - else begin - out_rdata_o = rdata; - out_err_o = err; - out_err_plus2_o = 1'b0; - out_valid_o = valid; - end - assign instr_addr_en = clear_i | (out_ready_i & out_valid_o); - assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed); - assign instr_addr_next = instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}; - assign instr_addr_d = (clear_i ? in_addr_i[31:1] : instr_addr_next); - always @(posedge clk_i) - if (instr_addr_en) - instr_addr_q <= instr_addr_d; - assign out_addr_next_o = {instr_addr_next, 1'b0}; - assign out_addr_o = {instr_addr_q, 1'b0}; - assign unused_addr_in = in_addr_i[0]; - assign busy_o = valid_q[DEPTH - 1:DEPTH - NUM_REQS]; - assign pop_fifo = (out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]); - generate - genvar i; - for (i = 0; i < (DEPTH - 1); i = i + 1) begin : g_fifo_next - if (i == 0) begin : g_ent0 - assign lowest_free_entry[i] = ~valid_q[i]; - end - else begin : g_ent_others - assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i - 1]; - end - assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | valid_q[i]; - assign valid_popped[i] = (pop_fifo ? valid_pushed[i + 1] : valid_pushed[i]); - assign valid_d[i] = valid_popped[i] & ~clear_i; - assign entry_en[i] = (valid_pushed[i + 1] & pop_fifo) | ((in_valid_i & lowest_free_entry[i]) & ~pop_fifo); - assign rdata_d[i * 32+:32] = (valid_q[i + 1] ? rdata_q[(i + 1) * 32+:32] : in_rdata_i); - assign err_d[i] = (valid_q[i + 1] ? err_q[i + 1] : in_err_i); - end - endgenerate - assign lowest_free_entry[DEPTH - 1] = ~valid_q[DEPTH - 1] & valid_q[DEPTH - 2]; - assign valid_pushed[DEPTH - 1] = valid_q[DEPTH - 1] | (in_valid_i & lowest_free_entry[DEPTH - 1]); - assign valid_popped[DEPTH - 1] = (pop_fifo ? 1'b0 : valid_pushed[DEPTH - 1]); - assign valid_d[DEPTH - 1] = valid_popped[DEPTH - 1] & ~clear_i; - assign entry_en[DEPTH - 1] = in_valid_i & lowest_free_entry[DEPTH - 1]; - assign rdata_d[(DEPTH - 1) * 32+:32] = in_rdata_i; - assign err_d[DEPTH - 1] = in_err_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - valid_q <= {DEPTH {1'sb0}}; - else - valid_q <= valid_d; - generate - for (i = 0; i < DEPTH; i = i + 1) begin : g_fifo_regs - always @(posedge clk_i) - if (entry_en[i]) begin - rdata_q[i * 32+:32] <= rdata_d[i * 32+:32]; - err_q[i] <= err_d[i]; - end - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_icache.v b/flow/designs/src/ibex/ibex_icache.v deleted file mode 100644 index 808ed8562b..0000000000 --- a/flow/designs/src/ibex/ibex_icache.v +++ /dev/null @@ -1,635 +0,0 @@ -module ibex_icache ( - clk_i, - rst_ni, - req_i, - branch_i, - branch_spec_i, - addr_i, - ready_i, - valid_o, - rdata_o, - addr_o, - err_o, - err_plus2_o, - instr_req_o, - instr_gnt_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_rvalid_i, - icache_enable_i, - icache_inval_i, - busy_o -); - parameter [31:0] BusWidth = 32; - parameter [31:0] CacheSizeBytes = 4096; - parameter [0:0] ICacheECC = 1'b0; - parameter [31:0] LineSize = 64; - parameter [31:0] NumWays = 2; - parameter [0:0] SpecRequest = 1'b0; - parameter [0:0] BranchCache = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire req_i; - input wire branch_i; - input wire branch_spec_i; - input wire [31:0] addr_i; - input wire ready_i; - output wire valid_o; - output wire [31:0] rdata_o; - output wire [31:0] addr_o; - output wire err_o; - output wire err_plus2_o; - output wire instr_req_o; - input wire instr_gnt_i; - output wire [31:0] instr_addr_o; - input wire [BusWidth - 1:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - input wire instr_rvalid_i; - input wire icache_enable_i; - input wire icache_inval_i; - output wire busy_o; - localparam [31:0] ADDR_W = 32; - localparam [31:0] NUM_FB = 4; - localparam [31:0] FB_THRESHOLD = NUM_FB - 2; - localparam [31:0] LINE_SIZE_ECC = (ICacheECC ? LineSize + 8 : LineSize); - localparam [31:0] LINE_SIZE_BYTES = LineSize / 8; - localparam [31:0] LINE_W = $clog2(LINE_SIZE_BYTES); - localparam [31:0] BUS_BYTES = BusWidth / 8; - localparam [31:0] BUS_W = $clog2(BUS_BYTES); - localparam [31:0] LINE_BEATS = LINE_SIZE_BYTES / BUS_BYTES; - localparam [31:0] LINE_BEATS_W = $clog2(LINE_BEATS); - localparam [31:0] NUM_LINES = (CacheSizeBytes / NumWays) / LINE_SIZE_BYTES; - localparam [31:0] INDEX_W = $clog2(NUM_LINES); - localparam [31:0] INDEX_HI = (INDEX_W + LINE_W) - 1; - localparam [31:0] TAG_SIZE = ((ADDR_W - INDEX_W) - LINE_W) + 1; - localparam [31:0] TAG_SIZE_ECC = (ICacheECC ? TAG_SIZE + 6 : TAG_SIZE); - localparam [31:0] OUTPUT_BEATS = BUS_BYTES / 2; - wire [ADDR_W - 1:0] lookup_addr_aligned; - wire [ADDR_W - 1:0] prefetch_addr_d; - reg [ADDR_W - 1:0] prefetch_addr_q; - wire prefetch_addr_en; - wire branch_suppress; - wire lookup_throttle; - wire lookup_req_ic0; - wire [ADDR_W - 1:0] lookup_addr_ic0; - wire [INDEX_W - 1:0] lookup_index_ic0; - wire fill_req_ic0; - wire [INDEX_W - 1:0] fill_index_ic0; - wire [TAG_SIZE - 1:0] fill_tag_ic0; - wire [LineSize - 1:0] fill_wdata_ic0; - wire lookup_grant_ic0; - wire lookup_actual_ic0; - wire fill_grant_ic0; - wire tag_req_ic0; - wire [INDEX_W - 1:0] tag_index_ic0; - wire [NumWays - 1:0] tag_banks_ic0; - wire tag_write_ic0; - wire [TAG_SIZE_ECC - 1:0] tag_wdata_ic0; - wire data_req_ic0; - wire [INDEX_W - 1:0] data_index_ic0; - wire [NumWays - 1:0] data_banks_ic0; - wire data_write_ic0; - wire [LINE_SIZE_ECC - 1:0] data_wdata_ic0; - wire [TAG_SIZE_ECC - 1:0] tag_rdata_ic1 [0:NumWays - 1]; - wire [LINE_SIZE_ECC - 1:0] data_rdata_ic1 [0:NumWays - 1]; - reg [LINE_SIZE_ECC - 1:0] hit_data_ic1; - reg lookup_valid_ic1; - reg [ADDR_W - 1:INDEX_HI + 1] lookup_addr_ic1; - wire [NumWays - 1:0] tag_match_ic1; - wire tag_hit_ic1; - wire [NumWays - 1:0] tag_invalid_ic1; - wire [NumWays - 1:0] lowest_invalid_way_ic1; - wire [NumWays - 1:0] round_robin_way_ic1; - reg [NumWays - 1:0] round_robin_way_q; - wire [NumWays - 1:0] sel_way_ic1; - wire ecc_err_ic1; - wire ecc_write_req; - wire [NumWays - 1:0] ecc_write_ways; - wire [INDEX_W - 1:0] ecc_write_index; - wire gnt_or_pmp_err; - wire gnt_not_pmp_err; - reg [1:0] fb_fill_level; - wire fill_cache_new; - wire fill_new_alloc; - wire fill_spec_req; - wire fill_spec_done; - wire fill_spec_hold; - wire [(NUM_FB * NUM_FB) - 1:0] fill_older_d; - reg [(NUM_FB * NUM_FB) - 1:0] fill_older_q; - wire [NUM_FB - 1:0] fill_alloc_sel; - wire [NUM_FB - 1:0] fill_alloc; - wire [NUM_FB - 1:0] fill_busy_d; - reg [NUM_FB - 1:0] fill_busy_q; - wire [NUM_FB - 1:0] fill_done; - reg [NUM_FB - 1:0] fill_in_ic1; - wire [NUM_FB - 1:0] fill_stale_d; - reg [NUM_FB - 1:0] fill_stale_q; - wire [NUM_FB - 1:0] fill_cache_d; - reg [NUM_FB - 1:0] fill_cache_q; - wire [NUM_FB - 1:0] fill_hit_ic1; - wire [NUM_FB - 1:0] fill_hit_d; - reg [NUM_FB - 1:0] fill_hit_q; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_ext_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_ext_cnt_q; - wire [NUM_FB - 1:0] fill_ext_hold_d; - reg [NUM_FB - 1:0] fill_ext_hold_q; - wire [NUM_FB - 1:0] fill_ext_done; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_cnt_q; - wire [NUM_FB - 1:0] fill_rvd_done; - wire [NUM_FB - 1:0] fill_ram_done_d; - reg [NUM_FB - 1:0] fill_ram_done_q; - wire [NUM_FB - 1:0] fill_out_grant; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_out_cnt_d; - reg [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_out_cnt_q; - wire [NUM_FB - 1:0] fill_out_done; - wire [NUM_FB - 1:0] fill_ext_req; - wire [NUM_FB - 1:0] fill_rvd_exp; - wire [NUM_FB - 1:0] fill_ram_req; - wire [NUM_FB - 1:0] fill_out_req; - wire [NUM_FB - 1:0] fill_data_sel; - wire [NUM_FB - 1:0] fill_data_reg; - wire [NUM_FB - 1:0] fill_data_hit; - wire [NUM_FB - 1:0] fill_data_rvd; - wire [(NUM_FB * LINE_BEATS_W) - 1:0] fill_ext_off; - wire [(NUM_FB * LINE_BEATS_W) - 1:0] fill_rvd_off; - wire [(LINE_BEATS_W >= 0 ? (NUM_FB * (LINE_BEATS_W + 1)) - 1 : (NUM_FB * (1 - LINE_BEATS_W)) + (LINE_BEATS_W - 1)):(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W)] fill_rvd_beat; - wire [NUM_FB - 1:0] fill_ext_arb; - wire [NUM_FB - 1:0] fill_ram_arb; - wire [NUM_FB - 1:0] fill_out_arb; - wire [NUM_FB - 1:0] fill_rvd_arb; - wire [NUM_FB - 1:0] fill_entry_en; - wire [NUM_FB - 1:0] fill_addr_en; - wire [NUM_FB - 1:0] fill_way_en; - wire [(NUM_FB * LINE_BEATS) - 1:0] fill_data_en; - wire [(NUM_FB * LINE_BEATS) - 1:0] fill_err_d; - reg [(NUM_FB * LINE_BEATS) - 1:0] fill_err_q; - reg [ADDR_W - 1:0] fill_addr_q [0:NUM_FB - 1]; - reg [NumWays - 1:0] fill_way_q [0:NUM_FB - 1]; - wire [LineSize - 1:0] fill_data_d [0:NUM_FB - 1]; - reg [LineSize - 1:0] fill_data_q [0:NUM_FB - 1]; - reg [ADDR_W - 1:BUS_W] fill_ext_req_addr; - reg [ADDR_W - 1:0] fill_ram_req_addr; - reg [NumWays - 1:0] fill_ram_req_way; - reg [LineSize - 1:0] fill_ram_req_data; - reg [LineSize - 1:0] fill_out_data; - reg [LINE_BEATS - 1:0] fill_out_err; - wire instr_req; - wire [ADDR_W - 1:BUS_W] instr_addr; - wire skid_complete_instr; - wire skid_ready; - wire output_compressed; - wire skid_valid_d; - reg skid_valid_q; - wire skid_en; - wire [15:0] skid_data_d; - reg [15:0] skid_data_q; - reg skid_err_q; - wire output_valid; - wire addr_incr_two; - wire output_addr_en; - wire [ADDR_W - 1:1] output_addr_d; - reg [ADDR_W - 1:1] output_addr_q; - reg [15:0] output_data_lo; - reg [15:0] output_data_hi; - wire data_valid; - wire output_ready; - wire [LineSize - 1:0] line_data; - wire [LINE_BEATS - 1:0] line_err; - reg [31:0] line_data_muxed; - reg line_err_muxed; - wire [31:0] output_data; - wire output_err; - wire start_inval; - wire inval_done; - reg reset_inval_q; - wire inval_prog_d; - reg inval_prog_q; - wire [INDEX_W - 1:0] inval_index_d; - reg [INDEX_W - 1:0] inval_index_q; - assign lookup_addr_aligned = {lookup_addr_ic0[ADDR_W - 1:LINE_W], {LINE_W {1'b0}}}; - assign prefetch_addr_d = (lookup_grant_ic0 ? lookup_addr_aligned + {{(ADDR_W - LINE_W) - 1 {1'b0}}, 1'b1, {LINE_W {1'b0}}} : addr_i); - assign prefetch_addr_en = branch_i | lookup_grant_ic0; - always @(posedge clk_i) - if (prefetch_addr_en) - prefetch_addr_q <= prefetch_addr_d; - assign lookup_throttle = fb_fill_level > FB_THRESHOLD[1:0]; - assign lookup_req_ic0 = ((req_i & ~&fill_busy_q) & (branch_i | ~lookup_throttle)) & ~ecc_write_req; - assign lookup_addr_ic0 = (branch_spec_i ? addr_i : prefetch_addr_q); - assign lookup_index_ic0 = lookup_addr_ic0[INDEX_HI:LINE_W]; - assign fill_req_ic0 = |fill_ram_req; - assign fill_index_ic0 = fill_ram_req_addr[INDEX_HI:LINE_W]; - assign fill_tag_ic0 = {~inval_prog_q & ~ecc_write_req, fill_ram_req_addr[ADDR_W - 1:INDEX_HI + 1]}; - assign fill_wdata_ic0 = fill_ram_req_data; - assign branch_suppress = branch_spec_i & ~branch_i; - assign lookup_grant_ic0 = lookup_req_ic0 & ~branch_suppress; - assign fill_grant_ic0 = ((fill_req_ic0 & (~lookup_req_ic0 | branch_suppress)) & ~inval_prog_q) & ~ecc_write_req; - assign lookup_actual_ic0 = ((lookup_grant_ic0 & icache_enable_i) & ~inval_prog_q) & ~start_inval; - assign tag_req_ic0 = ((lookup_req_ic0 | fill_req_ic0) | inval_prog_q) | ecc_write_req; - assign tag_index_ic0 = (inval_prog_q ? inval_index_q : (ecc_write_req ? ecc_write_index : (fill_grant_ic0 ? fill_index_ic0 : lookup_index_ic0))); - assign tag_banks_ic0 = (ecc_write_req ? ecc_write_ways : (fill_grant_ic0 ? fill_ram_req_way : {NumWays {1'b1}})); - assign tag_write_ic0 = (fill_grant_ic0 | inval_prog_q) | ecc_write_req; - assign data_req_ic0 = lookup_req_ic0 | fill_req_ic0; - assign data_index_ic0 = tag_index_ic0; - assign data_banks_ic0 = tag_banks_ic0; - assign data_write_ic0 = tag_write_ic0; - generate - if (ICacheECC) begin : gen_ecc_wdata - wire [21:0] tag_ecc_input_padded; - wire [27:0] tag_ecc_output_padded; - wire [22 - TAG_SIZE:0] tag_ecc_output_unused; - assign tag_ecc_input_padded = {{22 - TAG_SIZE {1'b0}}, fill_tag_ic0}; - assign tag_ecc_output_unused = tag_ecc_output_padded[21:TAG_SIZE - 1]; - prim_secded_28_22_enc tag_ecc_enc( - .in(tag_ecc_input_padded), - .out(tag_ecc_output_padded) - ); - assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22], tag_ecc_output_padded[TAG_SIZE - 1:0]}; - prim_secded_72_64_enc data_ecc_enc( - .in(fill_wdata_ic0), - .out(data_wdata_ic0) - ); - end - else begin : gen_noecc_wdata - assign tag_wdata_ic0 = fill_tag_ic0; - assign data_wdata_ic0 = fill_wdata_ic0; - end - endgenerate - generate - genvar way; - for (way = 0; way < NumWays; way = way + 1) begin : gen_rams - prim_ram_1p #( - .Width(TAG_SIZE_ECC), - .Depth(NUM_LINES), - .DataBitsPerMask(TAG_SIZE_ECC) - ) tag_bank( - .clk_i(clk_i), - .req_i(tag_req_ic0 & tag_banks_ic0[way]), - .write_i(tag_write_ic0), - .wmask_i({TAG_SIZE_ECC {1'b1}}), - .addr_i(tag_index_ic0), - .wdata_i(tag_wdata_ic0), - .rdata_o(tag_rdata_ic1[way]) - ); - prim_ram_1p #( - .Width(LINE_SIZE_ECC), - .Depth(NUM_LINES), - .DataBitsPerMask(LINE_SIZE_ECC) - ) data_bank( - .clk_i(clk_i), - .req_i(data_req_ic0 & data_banks_ic0[way]), - .write_i(data_write_ic0), - .wmask_i({LINE_SIZE_ECC {1'b1}}), - .addr_i(data_index_ic0), - .wdata_i(data_wdata_ic0), - .rdata_o(data_rdata_ic1[way]) - ); - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - lookup_valid_ic1 <= 1'b0; - else - lookup_valid_ic1 <= lookup_actual_ic0; - always @(posedge clk_i) - if (lookup_grant_ic0) begin - lookup_addr_ic1 <= lookup_addr_ic0[ADDR_W - 1:INDEX_HI + 1]; - fill_in_ic1 <= fill_alloc_sel; - end - generate - for (way = 0; way < NumWays; way = way + 1) begin : gen_tag_match - assign tag_match_ic1[way] = tag_rdata_ic1[way][TAG_SIZE - 1:0] == {1'b1, lookup_addr_ic1[ADDR_W - 1:INDEX_HI + 1]}; - assign tag_invalid_ic1[way] = ~tag_rdata_ic1[way][TAG_SIZE - 1]; - end - endgenerate - assign tag_hit_ic1 = |tag_match_ic1; - always @(*) begin - hit_data_ic1 = 'b0; - begin : sv2v_autoblock_1 - reg signed [31:0] way; - for (way = 0; way < NumWays; way = way + 1) - if (tag_match_ic1[way]) - hit_data_ic1 = hit_data_ic1 | data_rdata_ic1[way]; - end - end - assign lowest_invalid_way_ic1[0] = tag_invalid_ic1[0]; - assign round_robin_way_ic1[0] = round_robin_way_q[NumWays - 1]; - generate - for (way = 1; way < NumWays; way = way + 1) begin : gen_lowest_way - assign lowest_invalid_way_ic1[way] = tag_invalid_ic1[way] & ~|tag_invalid_ic1[way - 1:0]; - assign round_robin_way_ic1[way] = round_robin_way_q[way - 1]; - end - endgenerate - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - round_robin_way_q <= {{NumWays - 1 {1'b0}}, 1'b1}; - else if (lookup_valid_ic1) - round_robin_way_q <= round_robin_way_ic1; - assign sel_way_ic1 = (|tag_invalid_ic1 ? lowest_invalid_way_ic1 : round_robin_way_q); - generate - if (ICacheECC) begin : gen_data_ecc_checking - wire [NumWays - 1:0] tag_err_ic1; - wire [1:0] data_err_ic1; - wire ecc_correction_write_d; - reg ecc_correction_write_q; - wire [NumWays - 1:0] ecc_correction_ways_d; - reg [NumWays - 1:0] ecc_correction_ways_q; - reg [INDEX_W - 1:0] lookup_index_ic1; - reg [INDEX_W - 1:0] ecc_correction_index_q; - for (way = 0; way < NumWays; way = way + 1) begin : gen_tag_ecc - wire [1:0] tag_err_bank_ic1; - wire [27:0] tag_rdata_padded_ic1; - assign tag_rdata_padded_ic1 = {tag_rdata_ic1[way][TAG_SIZE_ECC - 1-:6], {22 - TAG_SIZE {1'b0}}, tag_rdata_ic1[way][TAG_SIZE - 1:0]}; - prim_secded_28_22_dec data_ecc_dec( - .in(tag_rdata_padded_ic1), - .d_o(), - .syndrome_o(), - .err_o(tag_err_bank_ic1) - ); - assign tag_err_ic1[way] = |tag_err_bank_ic1; - end - prim_secded_72_64_dec data_ecc_dec( - .in(hit_data_ic1), - .d_o(), - .syndrome_o(), - .err_o(data_err_ic1) - ); - assign ecc_err_ic1 = lookup_valid_ic1 & (|data_err_ic1 | |tag_err_ic1); - assign ecc_correction_ways_d = {NumWays {|tag_err_ic1}} | (tag_match_ic1 & {NumWays {|data_err_ic1}}); - assign ecc_correction_write_d = ecc_err_ic1; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - ecc_correction_write_q <= 1'b0; - else - ecc_correction_write_q <= ecc_correction_write_d; - always @(posedge clk_i) - if (lookup_grant_ic0) - lookup_index_ic1 <= lookup_addr_ic0[INDEX_HI-:INDEX_W]; - always @(posedge clk_i) - if (ecc_err_ic1) begin - ecc_correction_ways_q <= ecc_correction_ways_d; - ecc_correction_index_q <= lookup_index_ic1; - end - assign ecc_write_req = ecc_correction_write_q; - assign ecc_write_ways = ecc_correction_ways_q; - assign ecc_write_index = ecc_correction_index_q; - end - else begin : gen_no_data_ecc - assign ecc_err_ic1 = 1'b0; - assign ecc_write_req = 1'b0; - assign ecc_write_ways = {NumWays {1'sb0}}; - assign ecc_write_index = {INDEX_W {1'sb0}}; - end - endgenerate - generate - if (BranchCache) begin : gen_caching_logic - localparam [31:0] CACHE_AHEAD = 2; - localparam [31:0] CACHE_CNT_W = (CACHE_AHEAD == 1 ? 1 : 2); - wire cache_cnt_dec; - wire [CACHE_CNT_W - 1:0] cache_cnt_d; - reg [CACHE_CNT_W - 1:0] cache_cnt_q; - assign cache_cnt_dec = lookup_grant_ic0 & |cache_cnt_q; - assign cache_cnt_d = (branch_i ? CACHE_AHEAD[CACHE_CNT_W - 1:0] : cache_cnt_q - {{CACHE_CNT_W - 1 {1'b0}}, cache_cnt_dec}); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - cache_cnt_q <= {CACHE_CNT_W {1'sb0}}; - else - cache_cnt_q <= cache_cnt_d; - assign fill_cache_new = (((branch_i | |cache_cnt_q) & icache_enable_i) & ~icache_inval_i) & ~inval_prog_q; - end - else begin : gen_cache_all - assign fill_cache_new = (icache_enable_i & ~start_inval) & ~inval_prog_q; - end - endgenerate - always @(*) begin - fb_fill_level = {2 {1'sb0}}; - begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_busy_q[i] & ~fill_stale_q[i]) - fb_fill_level = fb_fill_level + {1'b0, 1'b1}; - end - end - assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; - assign gnt_not_pmp_err = instr_gnt_i & ~instr_pmp_err_i; - assign fill_new_alloc = lookup_grant_ic0; - assign fill_spec_req = (SpecRequest | branch_i) & ~|fill_ext_req; - assign fill_spec_done = fill_spec_req & gnt_not_pmp_err; - assign fill_spec_hold = fill_spec_req & ~gnt_or_pmp_err; - generate - genvar fb; - for (fb = 0; fb < NUM_FB; fb = fb + 1) begin : gen_fbs - if (fb == 0) begin : gen_fb_zero - assign fill_alloc_sel[fb] = ~fill_busy_q[fb]; - end - else begin : gen_fb_rest - assign fill_alloc_sel[fb] = ~fill_busy_q[fb] & &fill_busy_q[fb - 1:0]; - end - assign fill_alloc[fb] = fill_alloc_sel[fb] & fill_new_alloc; - assign fill_busy_d[fb] = fill_alloc[fb] | (fill_busy_q[fb] & ~fill_done[fb]); - assign fill_older_d[fb * NUM_FB+:NUM_FB] = (fill_alloc[fb] ? fill_busy_q : fill_older_q[fb * NUM_FB+:NUM_FB]) & ~fill_done; - assign fill_done[fb] = ((((fill_ram_done_q[fb] | fill_hit_q[fb]) | ~fill_cache_q[fb]) | |fill_err_q[fb * LINE_BEATS+:LINE_BEATS]) & ((fill_out_done[fb] | fill_stale_q[fb]) | branch_i)) & fill_rvd_done[fb]; - assign fill_stale_d[fb] = fill_busy_q[fb] & (branch_i | fill_stale_q[fb]); - assign fill_cache_d[fb] = (fill_alloc[fb] & fill_cache_new) | (((fill_cache_q[fb] & fill_busy_q[fb]) & icache_enable_i) & ~icache_inval_i); - assign fill_hit_ic1[fb] = ((lookup_valid_ic1 & fill_in_ic1[fb]) & tag_hit_ic1) & ~ecc_err_ic1; - assign fill_hit_d[fb] = fill_hit_ic1[fb] | (fill_hit_q[fb] & fill_busy_q[fb]); - assign fill_ext_req[fb] = fill_busy_q[fb] & ~fill_ext_done[fb]; - assign fill_ext_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {{LINE_BEATS_W {1'b0}}, fill_spec_done} : fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_ext_arb[fb] & gnt_not_pmp_err}); - assign fill_ext_hold_d[fb] = (fill_alloc[fb] & fill_spec_hold) | (fill_ext_arb[fb] & ~gnt_or_pmp_err); - assign fill_ext_done[fb] = ((((fill_ext_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)] | fill_hit_ic1[fb]) | fill_hit_q[fb]) | fill_err_q[(fb * LINE_BEATS) + fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W]]) | (~fill_cache_q[fb] & (branch_i | fill_stale_q[fb]))) & ~fill_ext_hold_q[fb]; - assign fill_rvd_exp[fb] = fill_busy_q[fb] & ~fill_rvd_done[fb]; - assign fill_rvd_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}} : fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_rvd_arb[fb]}); - assign fill_rvd_done[fb] = fill_ext_done[fb] & (fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] == fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]); - assign fill_out_req[fb] = ((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & ((((fill_hit_ic1[fb] | fill_hit_q[fb]) | fill_err_q[(fb * LINE_BEATS) + fill_out_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]]) | (fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] > fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)])) | fill_rvd_arb[fb]); - assign fill_out_grant[fb] = fill_out_arb[fb] & output_ready; - assign fill_out_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = (fill_alloc[fb] ? {1'b0, lookup_addr_ic0[LINE_W - 1:BUS_W]} : fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] + {{LINE_BEATS_W {1'b0}}, fill_out_grant[fb]}); - assign fill_out_done[fb] = fill_out_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)]; - assign fill_ram_req[fb] = ((((fill_busy_q[fb] & fill_rvd_cnt_q[(fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W : LINE_BEATS_W - LINE_BEATS_W)]) & ~fill_hit_q[fb]) & fill_cache_q[fb]) & ~|fill_err_q[fb * LINE_BEATS+:LINE_BEATS]) & ~fill_ram_done_q[fb]; - assign fill_ram_done_d[fb] = fill_ram_arb[fb] | (fill_ram_done_q[fb] & fill_busy_q[fb]); - assign fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] = {1'b0, fill_addr_q[fb][LINE_W - 1:BUS_W]} + fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1) : LINE_BEATS_W - (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1) : LINE_BEATS_W - (LINE_BEATS_W >= 0 ? LINE_BEATS_W : (LINE_BEATS_W + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1))) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) - 1)-:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - assign fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W] = fill_addr_q[fb][LINE_W - 1:BUS_W] + fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]; - assign fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] = fill_rvd_beat[(LINE_BEATS_W >= 0 ? (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1)) : (((fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)) + (LINE_BEATS_W >= 0 ? LINE_BEATS_W - 1 : LINE_BEATS_W - (LINE_BEATS_W - 1))) + LINE_BEATS_W) - 1)-:LINE_BEATS_W]; - assign fill_ext_arb[fb] = fill_ext_req[fb] & ~|(fill_ext_req & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_ram_arb[fb] = (fill_ram_req[fb] & fill_grant_ic0) & ~|(fill_ram_req & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_data_sel[fb] = ~|(((fill_busy_q & ~fill_out_done) & ~fill_stale_q) & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_out_arb[fb] = fill_out_req[fb] & fill_data_sel[fb]; - assign fill_rvd_arb[fb] = (instr_rvalid_i & fill_rvd_exp[fb]) & ~|(fill_rvd_exp & fill_older_q[fb * NUM_FB+:NUM_FB]); - assign fill_data_reg[fb] = (((fill_busy_q[fb] & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & fill_data_sel[fb]) & (((fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] > fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]) | fill_hit_q[fb]) | |fill_err_q[fb * LINE_BEATS+:LINE_BEATS]); - assign fill_data_hit[fb] = (fill_busy_q[fb] & fill_hit_ic1[fb]) & fill_data_sel[fb]; - assign fill_data_rvd[fb] = ((((((fill_busy_q[fb] & fill_rvd_arb[fb]) & ~fill_hit_q[fb]) & ~fill_hit_ic1[fb]) & ~fill_stale_q[fb]) & ~fill_out_done[fb]) & (fill_rvd_beat[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] == fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)])) & fill_data_sel[fb]; - assign fill_entry_en[fb] = fill_alloc[fb] | fill_busy_q[fb]; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - fill_busy_q[fb] <= 1'b0; - fill_older_q[fb * NUM_FB+:NUM_FB] <= {NUM_FB {1'sb0}}; - fill_stale_q[fb] <= 1'b0; - fill_cache_q[fb] <= 1'b0; - fill_hit_q[fb] <= 1'b0; - fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - fill_ext_hold_q[fb] <= 1'b0; - fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - fill_ram_done_q[fb] <= 1'b0; - fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= {(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W) {1'sb0}}; - end - else if (fill_entry_en[fb]) begin - fill_busy_q[fb] <= fill_busy_d[fb]; - fill_older_q[fb * NUM_FB+:NUM_FB] <= fill_older_d[fb * NUM_FB+:NUM_FB]; - fill_stale_q[fb] <= fill_stale_d[fb]; - fill_cache_q[fb] <= fill_cache_d[fb]; - fill_hit_q[fb] <= fill_hit_d[fb]; - fill_ext_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_ext_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - fill_ext_hold_q[fb] <= fill_ext_hold_d[fb]; - fill_rvd_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_rvd_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - fill_ram_done_q[fb] <= fill_ram_done_d[fb]; - fill_out_cnt_q[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)] <= fill_out_cnt_d[(LINE_BEATS_W >= 0 ? 0 : LINE_BEATS_W) + (fb * (LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W))+:(LINE_BEATS_W >= 0 ? LINE_BEATS_W + 1 : 1 - LINE_BEATS_W)]; - end - assign fill_addr_en[fb] = fill_alloc[fb]; - assign fill_way_en[fb] = lookup_valid_ic1 & fill_in_ic1[fb]; - always @(posedge clk_i) - if (fill_addr_en[fb]) - fill_addr_q[fb] <= lookup_addr_ic0; - always @(posedge clk_i) - if (fill_way_en[fb]) - fill_way_q[fb] <= sel_way_ic1; - assign fill_data_d[fb] = (fill_hit_ic1[fb] ? hit_data_ic1[LineSize - 1:0] : {LINE_BEATS {instr_rdata_i}}); - genvar b; - for (b = 0; b < LINE_BEATS; b = b + 1) begin : gen_data_buf - assign fill_err_d[(fb * LINE_BEATS) + b] = (((((instr_pmp_err_i & fill_alloc[fb]) & fill_spec_req) & (lookup_addr_ic0[LINE_W - 1:BUS_W] == b[LINE_BEATS_W - 1:0])) | ((instr_pmp_err_i & fill_ext_arb[fb]) & (fill_ext_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0]))) | ((fill_rvd_arb[fb] & instr_err_i) & (fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0]))) | (fill_busy_q[fb] & fill_err_q[(fb * LINE_BEATS) + b]); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - fill_err_q[(fb * LINE_BEATS) + b] <= 1'b0; - else if (fill_entry_en[fb]) - fill_err_q[(fb * LINE_BEATS) + b] <= fill_err_d[(fb * LINE_BEATS) + b]; - assign fill_data_en[(fb * LINE_BEATS) + b] = fill_hit_ic1[fb] | ((fill_rvd_arb[fb] & ~fill_hit_q[fb]) & (fill_rvd_off[fb * LINE_BEATS_W+:LINE_BEATS_W] == b[LINE_BEATS_W - 1:0])); - always @(posedge clk_i) - if (fill_data_en[(fb * LINE_BEATS) + b]) - fill_data_q[fb][b * BusWidth+:BusWidth] <= fill_data_d[fb][b * BusWidth+:BusWidth]; - end - end - endgenerate - always @(*) begin - fill_ext_req_addr = {((ADDR_W - 1) >= BUS_W ? ((ADDR_W - 1) - BUS_W) + 1 : (BUS_W - (ADDR_W - 1)) + 1) {1'sb0}}; - begin : sv2v_autoblock_3 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_ext_arb[i]) - fill_ext_req_addr = fill_ext_req_addr | {fill_addr_q[i][ADDR_W - 1:LINE_W], fill_ext_off[i * LINE_BEATS_W+:LINE_BEATS_W]}; - end - end - always @(*) begin - fill_ram_req_addr = {ADDR_W {1'sb0}}; - fill_ram_req_way = {NumWays {1'sb0}}; - fill_ram_req_data = {LineSize {1'sb0}}; - begin : sv2v_autoblock_4 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_ram_arb[i]) begin - fill_ram_req_addr = fill_ram_req_addr | fill_addr_q[i]; - fill_ram_req_way = fill_ram_req_way | fill_way_q[i]; - fill_ram_req_data = fill_ram_req_data | fill_data_q[i]; - end - end - end - always @(*) begin - fill_out_data = {LineSize {1'sb0}}; - fill_out_err = {LINE_BEATS {1'sb0}}; - begin : sv2v_autoblock_5 - reg signed [31:0] i; - for (i = 0; i < NUM_FB; i = i + 1) - if (fill_data_reg[i]) begin - fill_out_data = fill_out_data | fill_data_q[i]; - fill_out_err = fill_out_err | (fill_err_q[i * LINE_BEATS+:LINE_BEATS] & ~{LINE_BEATS {fill_hit_q[i]}}); - end - end - end - assign instr_req = ((SpecRequest | branch_i) & lookup_grant_ic0) | |fill_ext_req; - assign instr_addr = (|fill_ext_req ? fill_ext_req_addr : lookup_addr_ic0[ADDR_W - 1:BUS_W]); - assign instr_req_o = instr_req; - assign instr_addr_o = {instr_addr[ADDR_W - 1:BUS_W], {BUS_W {1'b0}}}; - assign line_data = (|fill_data_hit ? hit_data_ic1[LineSize - 1:0] : fill_out_data); - assign line_err = (|fill_data_hit ? {LINE_BEATS {1'b0}} : fill_out_err); - always @(*) begin - line_data_muxed = {32 {1'sb0}}; - line_err_muxed = 1'b0; - begin : sv2v_autoblock_6 - reg signed [31:0] i; - for (i = 0; i < LINE_BEATS; i = i + 1) - if ((output_addr_q[LINE_W - 1:BUS_W] + {{LINE_BEATS_W - 1 {1'b0}}, skid_valid_q}) == i[LINE_BEATS_W - 1:0]) begin - line_data_muxed = line_data_muxed | line_data[i * 32+:32]; - line_err_muxed = line_err_muxed | line_err[i]; - end - end - end - assign output_data = (|fill_data_rvd ? instr_rdata_i : line_data_muxed); - assign output_err = (|fill_data_rvd ? instr_err_i : line_err_muxed); - assign data_valid = |fill_out_arb; - assign skid_data_d = output_data[31:16]; - assign skid_en = data_valid & (ready_i | skid_ready); - always @(posedge clk_i) - if (skid_en) begin - skid_data_q <= skid_data_d; - skid_err_q <= output_err; - end - assign skid_complete_instr = skid_valid_q & ((skid_data_q[1:0] != 2'b11) | skid_err_q); - assign skid_ready = (output_addr_q[1] & ~skid_valid_q) & (~output_compressed | output_err); - assign output_ready = (ready_i | skid_ready) & ~skid_complete_instr; - assign output_compressed = rdata_o[1:0] != 2'b11; - assign skid_valid_d = (branch_i ? 1'b0 : (skid_valid_q ? ~(ready_i & ((skid_data_q[1:0] != 2'b11) | skid_err_q)) : ((output_addr_q[1] & (~output_compressed | output_err)) | (((~output_addr_q[1] & output_compressed) & ~output_err) & ready_i)) & data_valid)); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - skid_valid_q <= 1'b0; - else - skid_valid_q <= skid_valid_d; - assign output_valid = skid_complete_instr | (data_valid & (((~output_addr_q[1] | skid_valid_q) | output_err) | (output_data[17:16] != 2'b11))); - assign output_addr_en = branch_i | (ready_i & valid_o); - assign addr_incr_two = output_compressed & ~err_o; - assign output_addr_d = (branch_i ? addr_i[31:1] : output_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}); - always @(posedge clk_i) - if (output_addr_en) - output_addr_q <= output_addr_d; - always @(*) begin - output_data_lo = {16 {1'sb0}}; - begin : sv2v_autoblock_7 - reg signed [31:0] i; - for (i = 0; i < OUTPUT_BEATS; i = i + 1) - if (output_addr_q[BUS_W - 1:1] == i[BUS_W - 2:0]) - output_data_lo = output_data_lo | output_data[i * 16+:16]; - end - end - always @(*) begin - output_data_hi = {16 {1'sb0}}; - begin : sv2v_autoblock_8 - reg signed [31:0] i; - for (i = 0; i < (OUTPUT_BEATS - 1); i = i + 1) - if (output_addr_q[BUS_W - 1:1] == i[BUS_W - 2:0]) - output_data_hi = output_data_hi | output_data[(i + 1) * 16+:16]; - end - if (&output_addr_q[BUS_W - 1:1]) - output_data_hi = output_data_hi | output_data[15:0]; - end - assign valid_o = output_valid; - assign rdata_o = {output_data_hi, (skid_valid_q ? skid_data_q : output_data_lo)}; - assign addr_o = {output_addr_q, 1'b0}; - assign err_o = (skid_valid_q & skid_err_q) | (~skid_complete_instr & output_err); - assign err_plus2_o = skid_valid_q & ~skid_err_q; - assign start_inval = (~reset_inval_q | icache_inval_i) & ~inval_prog_q; - assign inval_prog_d = start_inval | (inval_prog_q & ~inval_done); - assign inval_done = &inval_index_q; - assign inval_index_d = (start_inval ? {INDEX_W {1'sb0}} : inval_index_q + {{INDEX_W - 1 {1'b0}}, 1'b1}); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - inval_prog_q <= 1'b0; - reset_inval_q <= 1'b0; - end - else begin - inval_prog_q <= inval_prog_d; - reset_inval_q <= 1'b1; - end - always @(posedge clk_i) - if (inval_prog_d) - inval_index_q <= inval_index_d; - assign busy_o = inval_prog_q | |(fill_busy_q & ~fill_rvd_done); -endmodule diff --git a/flow/designs/src/ibex/ibex_id_stage.v b/flow/designs/src/ibex/ibex_id_stage.v deleted file mode 100644 index 10187d0c85..0000000000 --- a/flow/designs/src/ibex/ibex_id_stage.v +++ /dev/null @@ -1,751 +0,0 @@ -module ibex_id_stage ( - clk_i, - rst_ni, - ctrl_busy_o, - illegal_insn_o, - instr_valid_i, - instr_rdata_i, - instr_rdata_alu_i, - instr_rdata_c_i, - instr_is_compressed_i, - instr_bp_taken_i, - instr_req_o, - instr_first_cycle_id_o, - instr_valid_clear_o, - id_in_ready_o, - icache_inval_o, - branch_decision_i, - pc_set_o, - pc_set_spec_o, - pc_mux_o, - nt_branch_mispredict_o, - exc_pc_mux_o, - exc_cause_o, - illegal_c_insn_i, - instr_fetch_err_i, - instr_fetch_err_plus2_i, - pc_id_i, - ex_valid_i, - lsu_resp_valid_i, - alu_operator_ex_o, - alu_operand_a_ex_o, - alu_operand_b_ex_o, - imd_val_we_ex_i, - imd_val_d_ex_i, - imd_val_q_ex_o, - bt_a_operand_o, - bt_b_operand_o, - mult_en_ex_o, - div_en_ex_o, - mult_sel_ex_o, - div_sel_ex_o, - multdiv_operator_ex_o, - multdiv_signed_mode_ex_o, - multdiv_operand_a_ex_o, - multdiv_operand_b_ex_o, - multdiv_ready_id_o, - csr_access_o, - csr_op_o, - csr_op_en_o, - csr_save_if_o, - csr_save_id_o, - csr_save_wb_o, - csr_restore_mret_id_o, - csr_restore_dret_id_o, - csr_save_cause_o, - csr_mtval_o, - priv_mode_i, - csr_mstatus_tw_i, - illegal_csr_insn_i, - data_ind_timing_i, - lsu_req_o, - lsu_we_o, - lsu_type_o, - lsu_sign_ext_o, - lsu_wdata_o, - lsu_req_done_i, - lsu_addr_incr_req_i, - lsu_addr_last_i, - csr_mstatus_mie_i, - irq_pending_i, - irqs_i, - irq_nm_i, - nmi_mode_o, - lsu_load_err_i, - lsu_store_err_i, - debug_mode_o, - debug_cause_o, - debug_csr_save_o, - debug_req_i, - debug_single_step_i, - debug_ebreakm_i, - debug_ebreaku_i, - trigger_match_i, - result_ex_i, - csr_rdata_i, - rf_raddr_a_o, - rf_rdata_a_i, - rf_raddr_b_o, - rf_rdata_b_i, - rf_ren_a_o, - rf_ren_b_o, - rf_waddr_id_o, - rf_wdata_id_o, - rf_we_id_o, - rf_rd_a_wb_match_o, - rf_rd_b_wb_match_o, - rf_waddr_wb_i, - rf_wdata_fwd_wb_i, - rf_write_wb_i, - en_wb_o, - instr_type_wb_o, - instr_perf_count_id_o, - ready_wb_i, - outstanding_load_wb_i, - outstanding_store_wb_i, - perf_jump_o, - perf_branch_o, - perf_tbranch_o, - perf_dside_wait_o, - perf_mul_wait_o, - perf_div_wait_o, - instr_id_done_o -); - parameter [0:0] RV32E = 0; - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - localparam integer ibex_pkg_RV32BNone = 0; - parameter integer RV32B = ibex_pkg_RV32BNone; - parameter [0:0] DataIndTiming = 1'b0; - parameter [0:0] BranchTargetALU = 0; - parameter [0:0] SpecBranch = 0; - parameter [0:0] WritebackStage = 0; - parameter [0:0] BranchPredictor = 0; - input wire clk_i; - input wire rst_ni; - output wire ctrl_busy_o; - output wire illegal_insn_o; - input wire instr_valid_i; - input wire [31:0] instr_rdata_i; - input wire [31:0] instr_rdata_alu_i; - input wire [15:0] instr_rdata_c_i; - input wire instr_is_compressed_i; - input wire instr_bp_taken_i; - output wire instr_req_o; - output wire instr_first_cycle_id_o; - output wire instr_valid_clear_o; - output wire id_in_ready_o; - output wire icache_inval_o; - input wire branch_decision_i; - output wire pc_set_o; - output wire pc_set_spec_o; - output wire [2:0] pc_mux_o; - output wire nt_branch_mispredict_o; - output wire [1:0] exc_pc_mux_o; - output wire [5:0] exc_cause_o; - input wire illegal_c_insn_i; - input wire instr_fetch_err_i; - input wire instr_fetch_err_plus2_i; - input wire [31:0] pc_id_i; - input wire ex_valid_i; - input wire lsu_resp_valid_i; - output wire [5:0] alu_operator_ex_o; - output wire [31:0] alu_operand_a_ex_o; - output wire [31:0] alu_operand_b_ex_o; - input wire [1:0] imd_val_we_ex_i; - input wire [67:0] imd_val_d_ex_i; - output wire [67:0] imd_val_q_ex_o; - output reg [31:0] bt_a_operand_o; - output reg [31:0] bt_b_operand_o; - output wire mult_en_ex_o; - output wire div_en_ex_o; - output wire mult_sel_ex_o; - output wire div_sel_ex_o; - output wire [1:0] multdiv_operator_ex_o; - output wire [1:0] multdiv_signed_mode_ex_o; - output wire [31:0] multdiv_operand_a_ex_o; - output wire [31:0] multdiv_operand_b_ex_o; - output wire multdiv_ready_id_o; - output wire csr_access_o; - output wire [1:0] csr_op_o; - output wire csr_op_en_o; - output wire csr_save_if_o; - output wire csr_save_id_o; - output wire csr_save_wb_o; - output wire csr_restore_mret_id_o; - output wire csr_restore_dret_id_o; - output wire csr_save_cause_o; - output wire [31:0] csr_mtval_o; - input wire [1:0] priv_mode_i; - input wire csr_mstatus_tw_i; - input wire illegal_csr_insn_i; - input wire data_ind_timing_i; - output wire lsu_req_o; - output wire lsu_we_o; - output wire [1:0] lsu_type_o; - output wire lsu_sign_ext_o; - output wire [31:0] lsu_wdata_o; - input wire lsu_req_done_i; - input wire lsu_addr_incr_req_i; - input wire [31:0] lsu_addr_last_i; - input wire csr_mstatus_mie_i; - input wire irq_pending_i; - input wire [17:0] irqs_i; - input wire irq_nm_i; - output wire nmi_mode_o; - input wire lsu_load_err_i; - input wire lsu_store_err_i; - output wire debug_mode_o; - output wire [2:0] debug_cause_o; - output wire debug_csr_save_o; - input wire debug_req_i; - input wire debug_single_step_i; - input wire debug_ebreakm_i; - input wire debug_ebreaku_i; - input wire trigger_match_i; - input wire [31:0] result_ex_i; - input wire [31:0] csr_rdata_i; - output wire [4:0] rf_raddr_a_o; - input wire [31:0] rf_rdata_a_i; - output wire [4:0] rf_raddr_b_o; - input wire [31:0] rf_rdata_b_i; - output wire rf_ren_a_o; - output wire rf_ren_b_o; - output wire [4:0] rf_waddr_id_o; - output reg [31:0] rf_wdata_id_o; - output wire rf_we_id_o; - output wire rf_rd_a_wb_match_o; - output wire rf_rd_b_wb_match_o; - input wire [4:0] rf_waddr_wb_i; - input wire [31:0] rf_wdata_fwd_wb_i; - input wire rf_write_wb_i; - output wire en_wb_o; - output wire [1:0] instr_type_wb_o; - output wire instr_perf_count_id_o; - input wire ready_wb_i; - input wire outstanding_load_wb_i; - input wire outstanding_store_wb_i; - output wire perf_jump_o; - output reg perf_branch_o; - output wire perf_tbranch_o; - output wire perf_dside_wait_o; - output wire perf_mul_wait_o; - output wire perf_div_wait_o; - output wire instr_id_done_o; - wire illegal_insn_dec; - wire ebrk_insn; - wire mret_insn_dec; - wire dret_insn_dec; - wire ecall_insn_dec; - wire wfi_insn_dec; - wire wb_exception; - wire branch_in_dec; - reg branch_spec; - wire branch_set_spec; - wire branch_set; - reg branch_set_d; - reg branch_not_set; - wire branch_taken; - wire jump_in_dec; - wire jump_set_dec; - reg jump_set; - wire instr_first_cycle; - wire instr_executing; - wire instr_done; - wire controller_run; - wire stall_ld_hz; - wire stall_mem; - reg stall_multdiv; - reg stall_branch; - reg stall_jump; - wire stall_id; - wire stall_wb; - wire flush_id; - wire multicycle_done; - wire [31:0] imm_i_type; - wire [31:0] imm_s_type; - wire [31:0] imm_b_type; - wire [31:0] imm_u_type; - wire [31:0] imm_j_type; - wire [31:0] zimm_rs1_type; - wire [31:0] imm_a; - reg [31:0] imm_b; - wire rf_wdata_sel; - wire rf_we_dec; - reg rf_we_raw; - wire rf_ren_a; - wire rf_ren_b; - assign rf_ren_a_o = rf_ren_a; - assign rf_ren_b_o = rf_ren_b; - wire [31:0] rf_rdata_a_fwd; - wire [31:0] rf_rdata_b_fwd; - wire [5:0] alu_operator; - wire [1:0] alu_op_a_mux_sel; - wire [1:0] alu_op_a_mux_sel_dec; - wire alu_op_b_mux_sel; - wire alu_op_b_mux_sel_dec; - wire alu_multicycle_dec; - reg stall_alu; - reg [67:0] imd_val_q; - wire [1:0] bt_a_mux_sel; - wire [2:0] bt_b_mux_sel; - wire imm_a_mux_sel; - wire [2:0] imm_b_mux_sel; - wire [2:0] imm_b_mux_sel_dec; - wire mult_en_id; - wire mult_en_dec; - wire div_en_id; - wire div_en_dec; - wire multdiv_en_dec; - wire [1:0] multdiv_operator; - wire [1:0] multdiv_signed_mode; - wire lsu_we; - wire [1:0] lsu_type; - wire lsu_sign_ext; - wire lsu_req; - wire lsu_req_dec; - wire data_req_allowed; - reg csr_pipe_flush; - reg [31:0] alu_operand_a; - wire [31:0] alu_operand_b; - localparam [1:0] ibex_pkg_OP_A_FWD = 1; - assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_OP_A_FWD : alu_op_a_mux_sel_dec); - localparam [0:0] ibex_pkg_OP_B_IMM = 1; - assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_OP_B_IMM : alu_op_b_mux_sel_dec); - localparam [2:0] ibex_pkg_IMM_B_INCR_ADDR = 6; - assign imm_b_mux_sel = (lsu_addr_incr_req_i ? ibex_pkg_IMM_B_INCR_ADDR : imm_b_mux_sel_dec); - localparam [0:0] ibex_pkg_IMM_A_Z = 0; - assign imm_a = (imm_a_mux_sel == ibex_pkg_IMM_A_Z ? zimm_rs1_type : {32 {1'sb0}}); - localparam [1:0] ibex_pkg_OP_A_CURRPC = 2; - localparam [1:0] ibex_pkg_OP_A_IMM = 3; - localparam [1:0] ibex_pkg_OP_A_REG_A = 0; - always @(*) begin : alu_operand_a_mux - case (alu_op_a_mux_sel) - ibex_pkg_OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; - ibex_pkg_OP_A_FWD: alu_operand_a = lsu_addr_last_i; - ibex_pkg_OP_A_CURRPC: alu_operand_a = pc_id_i; - ibex_pkg_OP_A_IMM: alu_operand_a = imm_a; - default: alu_operand_a = pc_id_i; - endcase - end - localparam [2:0] ibex_pkg_IMM_B_B = 2; - localparam [2:0] ibex_pkg_IMM_B_I = 0; - localparam [2:0] ibex_pkg_IMM_B_INCR_PC = 5; - localparam [2:0] ibex_pkg_IMM_B_J = 4; - localparam [2:0] ibex_pkg_IMM_B_S = 1; - localparam [2:0] ibex_pkg_IMM_B_U = 3; - generate - if (BranchTargetALU) begin : g_btalu_muxes - always @(*) begin : bt_operand_a_mux - case (bt_a_mux_sel) - ibex_pkg_OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; - ibex_pkg_OP_A_CURRPC: bt_a_operand_o = pc_id_i; - default: bt_a_operand_o = pc_id_i; - endcase - end - always @(*) begin : bt_immediate_b_mux - case (bt_b_mux_sel) - ibex_pkg_IMM_B_I: bt_b_operand_o = imm_i_type; - ibex_pkg_IMM_B_B: bt_b_operand_o = imm_b_type; - ibex_pkg_IMM_B_J: bt_b_operand_o = imm_j_type; - ibex_pkg_IMM_B_INCR_PC: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - default: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - endcase - end - always @(*) begin : immediate_b_mux - case (imm_b_mux_sel) - ibex_pkg_IMM_B_I: imm_b = imm_i_type; - ibex_pkg_IMM_B_S: imm_b = imm_s_type; - ibex_pkg_IMM_B_U: imm_b = imm_u_type; - ibex_pkg_IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - ibex_pkg_IMM_B_INCR_ADDR: imm_b = 32'h00000004; - default: imm_b = 32'h00000004; - endcase - end - end - else begin : g_nobtalu - wire [1:0] unused_a_mux_sel; - wire [2:0] unused_b_mux_sel; - assign unused_a_mux_sel = bt_a_mux_sel; - assign unused_b_mux_sel = bt_b_mux_sel; - wire [32:1] sv2v_tmp_456A8; - assign sv2v_tmp_456A8 = {32 {1'sb0}}; - always @(*) bt_a_operand_o = sv2v_tmp_456A8; - wire [32:1] sv2v_tmp_EDBFD; - assign sv2v_tmp_EDBFD = {32 {1'sb0}}; - always @(*) bt_b_operand_o = sv2v_tmp_EDBFD; - always @(*) begin : immediate_b_mux - case (imm_b_mux_sel) - ibex_pkg_IMM_B_I: imm_b = imm_i_type; - ibex_pkg_IMM_B_S: imm_b = imm_s_type; - ibex_pkg_IMM_B_B: imm_b = imm_b_type; - ibex_pkg_IMM_B_U: imm_b = imm_u_type; - ibex_pkg_IMM_B_J: imm_b = imm_j_type; - ibex_pkg_IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); - ibex_pkg_IMM_B_INCR_ADDR: imm_b = 32'h00000004; - default: imm_b = 32'h00000004; - endcase - end - end - endgenerate - assign alu_operand_b = (alu_op_b_mux_sel == ibex_pkg_OP_B_IMM ? imm_b : rf_rdata_b_fwd); - generate - genvar i; - for (i = 0; i < 2; i = i + 1) begin : gen_intermediate_val_reg - always @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg - if (!rst_ni) - imd_val_q[(1 - i) * 34+:34] <= {34 {1'sb0}}; - else if (imd_val_we_ex_i[i]) - imd_val_q[(1 - i) * 34+:34] <= imd_val_d_ex_i[(1 - i) * 34+:34]; - end - end - endgenerate - assign imd_val_q_ex_o = imd_val_q; - assign rf_we_id_o = (rf_we_raw & instr_executing) & ~illegal_csr_insn_i; - localparam [0:0] ibex_pkg_RF_WD_CSR = 1; - localparam [0:0] ibex_pkg_RF_WD_EX = 0; - always @(*) begin : rf_wdata_id_mux - case (rf_wdata_sel) - ibex_pkg_RF_WD_EX: rf_wdata_id_o = result_ex_i; - ibex_pkg_RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; - default: rf_wdata_id_o = result_ex_i; - endcase - end - ibex_decoder #( - .RV32E(RV32E), - .RV32M(RV32M), - .RV32B(RV32B), - .BranchTargetALU(BranchTargetALU) - ) decoder_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .illegal_insn_o(illegal_insn_dec), - .ebrk_insn_o(ebrk_insn), - .mret_insn_o(mret_insn_dec), - .dret_insn_o(dret_insn_dec), - .ecall_insn_o(ecall_insn_dec), - .wfi_insn_o(wfi_insn_dec), - .jump_set_o(jump_set_dec), - .branch_taken_i(branch_taken), - .icache_inval_o(icache_inval_o), - .instr_first_cycle_i(instr_first_cycle), - .instr_rdata_i(instr_rdata_i), - .instr_rdata_alu_i(instr_rdata_alu_i), - .illegal_c_insn_i(illegal_c_insn_i), - .imm_a_mux_sel_o(imm_a_mux_sel), - .imm_b_mux_sel_o(imm_b_mux_sel_dec), - .bt_a_mux_sel_o(bt_a_mux_sel), - .bt_b_mux_sel_o(bt_b_mux_sel), - .imm_i_type_o(imm_i_type), - .imm_s_type_o(imm_s_type), - .imm_b_type_o(imm_b_type), - .imm_u_type_o(imm_u_type), - .imm_j_type_o(imm_j_type), - .zimm_rs1_type_o(zimm_rs1_type), - .rf_wdata_sel_o(rf_wdata_sel), - .rf_we_o(rf_we_dec), - .rf_raddr_a_o(rf_raddr_a_o), - .rf_raddr_b_o(rf_raddr_b_o), - .rf_waddr_o(rf_waddr_id_o), - .rf_ren_a_o(rf_ren_a), - .rf_ren_b_o(rf_ren_b), - .alu_operator_o(alu_operator), - .alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec), - .alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec), - .alu_multicycle_o(alu_multicycle_dec), - .mult_en_o(mult_en_dec), - .div_en_o(div_en_dec), - .mult_sel_o(mult_sel_ex_o), - .div_sel_o(div_sel_ex_o), - .multdiv_operator_o(multdiv_operator), - .multdiv_signed_mode_o(multdiv_signed_mode), - .csr_access_o(csr_access_o), - .csr_op_o(csr_op_o), - .data_req_o(lsu_req_dec), - .data_we_o(lsu_we), - .data_type_o(lsu_type), - .data_sign_extension_o(lsu_sign_ext), - .jump_in_dec_o(jump_in_dec), - .branch_in_dec_o(branch_in_dec) - ); - localparam [11:0] ibex_pkg_CSR_DCSR = 12'h7b0; - localparam [11:0] ibex_pkg_CSR_DPC = 12'h7b1; - localparam [11:0] ibex_pkg_CSR_DSCRATCH0 = 12'h7b2; - localparam [11:0] ibex_pkg_CSR_DSCRATCH1 = 12'h7b3; - localparam [11:0] ibex_pkg_CSR_MIE = 12'h304; - localparam [11:0] ibex_pkg_CSR_MSTATUS = 12'h300; - localparam [1:0] ibex_pkg_CSR_OP_READ = 0; - localparam [1:0] ibex_pkg_CSR_OP_SET = 2; - localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1; - always @(*) begin : csr_pipeline_flushes - csr_pipe_flush = 1'b0; - if ((csr_op_en_o == 1'b1) && ((csr_op_o == ibex_pkg_CSR_OP_WRITE) || (csr_op_o == ibex_pkg_CSR_OP_SET))) begin - if ((instr_rdata_i[31:20] == ibex_pkg_CSR_MSTATUS) || (instr_rdata_i[31:20] == ibex_pkg_CSR_MIE)) - csr_pipe_flush = 1'b1; - end - else if ((csr_op_en_o == 1'b1) && (csr_op_o != ibex_pkg_CSR_OP_READ)) - if ((((instr_rdata_i[31:20] == ibex_pkg_CSR_DCSR) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DPC)) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DSCRATCH0)) || (instr_rdata_i[31:20] == ibex_pkg_CSR_DSCRATCH1)) - csr_pipe_flush = 1'b1; - end - assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); - ibex_controller #( - .WritebackStage(WritebackStage), - .BranchPredictor(BranchPredictor) - ) controller_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .ctrl_busy_o(ctrl_busy_o), - .illegal_insn_i(illegal_insn_o), - .ecall_insn_i(ecall_insn_dec), - .mret_insn_i(mret_insn_dec), - .dret_insn_i(dret_insn_dec), - .wfi_insn_i(wfi_insn_dec), - .ebrk_insn_i(ebrk_insn), - .csr_pipe_flush_i(csr_pipe_flush), - .instr_valid_i(instr_valid_i), - .instr_i(instr_rdata_i), - .instr_compressed_i(instr_rdata_c_i), - .instr_is_compressed_i(instr_is_compressed_i), - .instr_bp_taken_i(instr_bp_taken_i), - .instr_fetch_err_i(instr_fetch_err_i), - .instr_fetch_err_plus2_i(instr_fetch_err_plus2_i), - .pc_id_i(pc_id_i), - .instr_valid_clear_o(instr_valid_clear_o), - .id_in_ready_o(id_in_ready_o), - .controller_run_o(controller_run), - .instr_req_o(instr_req_o), - .pc_set_o(pc_set_o), - .pc_set_spec_o(pc_set_spec_o), - .pc_mux_o(pc_mux_o), - .nt_branch_mispredict_o(nt_branch_mispredict_o), - .exc_pc_mux_o(exc_pc_mux_o), - .exc_cause_o(exc_cause_o), - .lsu_addr_last_i(lsu_addr_last_i), - .load_err_i(lsu_load_err_i), - .store_err_i(lsu_store_err_i), - .wb_exception_o(wb_exception), - .branch_set_i(branch_set), - .branch_set_spec_i(branch_set_spec), - .branch_not_set_i(branch_not_set), - .jump_set_i(jump_set), - .csr_mstatus_mie_i(csr_mstatus_mie_i), - .irq_pending_i(irq_pending_i), - .irqs_i(irqs_i), - .irq_nm_i(irq_nm_i), - .nmi_mode_o(nmi_mode_o), - .csr_save_if_o(csr_save_if_o), - .csr_save_id_o(csr_save_id_o), - .csr_save_wb_o(csr_save_wb_o), - .csr_restore_mret_id_o(csr_restore_mret_id_o), - .csr_restore_dret_id_o(csr_restore_dret_id_o), - .csr_save_cause_o(csr_save_cause_o), - .csr_mtval_o(csr_mtval_o), - .priv_mode_i(priv_mode_i), - .csr_mstatus_tw_i(csr_mstatus_tw_i), - .debug_mode_o(debug_mode_o), - .debug_cause_o(debug_cause_o), - .debug_csr_save_o(debug_csr_save_o), - .debug_req_i(debug_req_i), - .debug_single_step_i(debug_single_step_i), - .debug_ebreakm_i(debug_ebreakm_i), - .debug_ebreaku_i(debug_ebreaku_i), - .trigger_match_i(trigger_match_i), - .stall_id_i(stall_id), - .stall_wb_i(stall_wb), - .flush_id_o(flush_id), - .ready_wb_i(ready_wb_i), - .perf_jump_o(perf_jump_o), - .perf_tbranch_o(perf_tbranch_o) - ); - assign multdiv_en_dec = mult_en_dec | div_en_dec; - assign lsu_req = (instr_executing ? data_req_allowed & lsu_req_dec : 1'b0); - assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0); - assign div_en_id = (instr_executing ? div_en_dec : 1'b0); - assign lsu_req_o = lsu_req; - assign lsu_we_o = lsu_we; - assign lsu_type_o = lsu_type; - assign lsu_sign_ext_o = lsu_sign_ext; - assign lsu_wdata_o = rf_rdata_b_fwd; - assign csr_op_en_o = (csr_access_o & instr_executing) & instr_id_done_o; - assign alu_operator_ex_o = alu_operator; - assign alu_operand_a_ex_o = alu_operand_a; - assign alu_operand_b_ex_o = alu_operand_b; - assign mult_en_ex_o = mult_en_id; - assign div_en_ex_o = div_en_id; - assign multdiv_operator_ex_o = multdiv_operator; - assign multdiv_signed_mode_ex_o = multdiv_signed_mode; - assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; - assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; - generate - if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct - assign branch_set = branch_set_d; - assign branch_set_spec = branch_spec; - end - else begin : g_branch_set_flop - reg branch_set_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - branch_set_q <= 1'b0; - else - branch_set_q <= branch_set_d; - assign branch_set = (BranchTargetALU && !data_ind_timing_i ? branch_set_d : branch_set_q); - assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i ? branch_spec : branch_set_q); - end - endgenerate - generate - if (DataIndTiming) begin : g_sec_branch_taken - reg branch_taken_q; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - branch_taken_q <= 1'b0; - else - branch_taken_q <= branch_decision_i; - assign branch_taken = ~data_ind_timing_i | branch_taken_q; - end - else begin : g_nosec_branch_taken - assign branch_taken = 1'b1; - end - endgenerate - reg id_fsm_q; - reg id_fsm_d; - localparam [0:0] FIRST_CYCLE = 0; - always @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg - if (!rst_ni) - id_fsm_q <= FIRST_CYCLE; - else - id_fsm_q <= id_fsm_d; - end - localparam [0:0] MULTI_CYCLE = 1; - always @(*) begin - id_fsm_d = id_fsm_q; - rf_we_raw = rf_we_dec; - stall_multdiv = 1'b0; - stall_jump = 1'b0; - stall_branch = 1'b0; - stall_alu = 1'b0; - branch_set_d = 1'b0; - branch_spec = 1'b0; - branch_not_set = 1'b0; - jump_set = 1'b0; - perf_branch_o = 1'b0; - if (instr_executing) - case (id_fsm_q) - FIRST_CYCLE: - case (1'b1) - lsu_req_dec: - if (!WritebackStage) - id_fsm_d = MULTI_CYCLE; - else if (~lsu_req_done_i) - id_fsm_d = MULTI_CYCLE; - multdiv_en_dec: - if (~ex_valid_i) begin - id_fsm_d = MULTI_CYCLE; - rf_we_raw = 1'b0; - stall_multdiv = 1'b1; - end - branch_in_dec: begin - id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i) ? MULTI_CYCLE : FIRST_CYCLE); - stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; - branch_set_d = branch_decision_i | data_ind_timing_i; - if (BranchPredictor) - branch_not_set = ~branch_decision_i; - branch_spec = (SpecBranch ? 1'b1 : branch_decision_i); - perf_branch_o = 1'b1; - end - jump_in_dec: begin - id_fsm_d = (BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE); - stall_jump = ~BranchTargetALU; - jump_set = jump_set_dec; - end - alu_multicycle_dec: begin - stall_alu = 1'b1; - id_fsm_d = MULTI_CYCLE; - rf_we_raw = 1'b0; - end - default: id_fsm_d = FIRST_CYCLE; - endcase - MULTI_CYCLE: begin - if (multdiv_en_dec) - rf_we_raw = rf_we_dec & ex_valid_i; - if (multicycle_done & ready_wb_i) - id_fsm_d = FIRST_CYCLE; - else begin - stall_multdiv = multdiv_en_dec; - stall_branch = branch_in_dec; - stall_jump = jump_in_dec; - end - end - default: id_fsm_d = FIRST_CYCLE; - endcase - end - assign multdiv_ready_id_o = ready_wb_i; - assign stall_id = ((((stall_ld_hz | stall_mem) | stall_multdiv) | stall_jump) | stall_branch) | stall_alu; - assign instr_done = (~stall_id & ~flush_id) & instr_executing; - assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); - assign instr_first_cycle_id_o = instr_first_cycle; - localparam [1:0] ibex_pkg_WB_INSTR_LOAD = 0; - localparam [1:0] ibex_pkg_WB_INSTR_OTHER = 2; - localparam [1:0] ibex_pkg_WB_INSTR_STORE = 1; - generate - if (WritebackStage) begin : gen_stall_mem - wire rf_rd_a_wb_match; - wire rf_rd_b_wb_match; - wire rf_rd_a_hz; - wire rf_rd_b_hz; - wire outstanding_memory_access; - wire instr_kill; - assign multicycle_done = (lsu_req_dec ? ~stall_mem : ex_valid_i); - assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & ~lsu_resp_valid_i; - assign data_req_allowed = ~outstanding_memory_access; - assign instr_kill = (instr_fetch_err_i | wb_exception) | ~controller_run; - assign instr_executing = ((instr_valid_i & ~instr_kill) & ~stall_ld_hz) & ~outstanding_memory_access; - assign stall_mem = instr_valid_i & (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); - assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; - assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; - assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; - assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; - assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; - assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; - assign rf_rdata_a_fwd = (rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i); - assign rf_rdata_b_fwd = (rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i); - assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); - assign instr_type_wb_o = (~lsu_req_dec ? ibex_pkg_WB_INSTR_OTHER : (lsu_we ? ibex_pkg_WB_INSTR_STORE : ibex_pkg_WB_INSTR_LOAD)); - assign instr_id_done_o = en_wb_o & ready_wb_i; - assign stall_wb = en_wb_o & ~ready_wb_i; - assign perf_dside_wait_o = (instr_valid_i & ~instr_kill) & (outstanding_memory_access | stall_ld_hz); - end - else begin : gen_no_stall_mem - assign multicycle_done = (lsu_req_dec ? lsu_resp_valid_i : ex_valid_i); - assign data_req_allowed = instr_first_cycle; - assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); - assign stall_ld_hz = 1'b0; - assign instr_executing = (instr_valid_i & ~instr_fetch_err_i) & controller_run; - assign rf_rdata_a_fwd = rf_rdata_a_i; - assign rf_rdata_b_fwd = rf_rdata_b_i; - assign rf_rd_a_wb_match_o = 1'b0; - assign rf_rd_b_wb_match_o = 1'b0; - wire unused_data_req_done_ex; - wire [4:0] unused_rf_waddr_wb; - wire unused_rf_write_wb; - wire unused_outstanding_load_wb; - wire unused_outstanding_store_wb; - wire unused_wb_exception; - wire [31:0] unused_rf_wdata_fwd_wb; - assign unused_data_req_done_ex = lsu_req_done_i; - assign unused_rf_waddr_wb = rf_waddr_wb_i; - assign unused_rf_write_wb = rf_write_wb_i; - assign unused_outstanding_load_wb = outstanding_load_wb_i; - assign unused_outstanding_store_wb = outstanding_store_wb_i; - assign unused_wb_exception = wb_exception; - assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; - assign instr_type_wb_o = ibex_pkg_WB_INSTR_OTHER; - assign stall_wb = 1'b0; - assign perf_dside_wait_o = (instr_executing & lsu_req_dec) & ~lsu_resp_valid_i; - assign instr_id_done_o = instr_done; - end - endgenerate - assign instr_perf_count_id_o = (((~ebrk_insn & ~ecall_insn_dec) & ~illegal_insn_dec) & ~illegal_csr_insn_i) & ~instr_fetch_err_i; - assign en_wb_o = instr_done; - assign perf_mul_wait_o = stall_multdiv & mult_en_dec; - assign perf_div_wait_o = stall_multdiv & div_en_dec; -endmodule diff --git a/flow/designs/src/ibex/ibex_if_stage.v b/flow/designs/src/ibex/ibex_if_stage.v deleted file mode 100644 index 712cb73b5e..0000000000 --- a/flow/designs/src/ibex/ibex_if_stage.v +++ /dev/null @@ -1,396 +0,0 @@ -module ibex_if_stage ( - clk_i, - rst_ni, - boot_addr_i, - req_i, - instr_req_o, - instr_addr_o, - instr_gnt_i, - instr_rvalid_i, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_valid_id_o, - instr_new_id_o, - instr_rdata_id_o, - instr_rdata_alu_id_o, - instr_rdata_c_id_o, - instr_is_compressed_id_o, - instr_bp_taken_o, - instr_fetch_err_o, - instr_fetch_err_plus2_o, - illegal_c_insn_id_o, - dummy_instr_id_o, - pc_if_o, - pc_id_o, - instr_valid_clear_i, - pc_set_i, - pc_set_spec_i, - pc_mux_i, - nt_branch_mispredict_i, - exc_pc_mux_i, - exc_cause, - dummy_instr_en_i, - dummy_instr_mask_i, - dummy_instr_seed_en_i, - dummy_instr_seed_i, - icache_enable_i, - icache_inval_i, - branch_target_ex_i, - csr_mepc_i, - csr_depc_i, - csr_mtvec_i, - csr_mtvec_init_o, - id_in_ready_i, - pc_mismatch_alert_o, - if_busy_o -); - parameter [31:0] DmHaltAddr = 32'h1a110800; - parameter [31:0] DmExceptionAddr = 32'h1a110808; - parameter [0:0] DummyInstructions = 1'b0; - parameter [0:0] ICache = 1'b0; - parameter [0:0] ICacheECC = 1'b0; - parameter [0:0] PCIncrCheck = 1'b0; - parameter [0:0] BranchPredictor = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire [31:0] boot_addr_i; - input wire req_i; - output wire instr_req_o; - output wire [31:0] instr_addr_o; - input wire instr_gnt_i; - input wire instr_rvalid_i; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - output wire instr_valid_id_o; - output wire instr_new_id_o; - output reg [31:0] instr_rdata_id_o; - output reg [31:0] instr_rdata_alu_id_o; - output reg [15:0] instr_rdata_c_id_o; - output reg instr_is_compressed_id_o; - output wire instr_bp_taken_o; - output reg instr_fetch_err_o; - output reg instr_fetch_err_plus2_o; - output reg illegal_c_insn_id_o; - output reg dummy_instr_id_o; - output wire [31:0] pc_if_o; - output reg [31:0] pc_id_o; - input wire instr_valid_clear_i; - input wire pc_set_i; - input wire pc_set_spec_i; - input wire [2:0] pc_mux_i; - input wire nt_branch_mispredict_i; - input wire [1:0] exc_pc_mux_i; - input wire [5:0] exc_cause; - input wire dummy_instr_en_i; - input wire [2:0] dummy_instr_mask_i; - input wire dummy_instr_seed_en_i; - input wire [31:0] dummy_instr_seed_i; - input wire icache_enable_i; - input wire icache_inval_i; - input wire [31:0] branch_target_ex_i; - input wire [31:0] csr_mepc_i; - input wire [31:0] csr_depc_i; - input wire [31:0] csr_mtvec_i; - output wire csr_mtvec_init_o; - input wire id_in_ready_i; - output wire pc_mismatch_alert_o; - output wire if_busy_o; - wire instr_valid_id_d; - reg instr_valid_id_q; - wire instr_new_id_d; - reg instr_new_id_q; - wire prefetch_busy; - wire branch_req; - wire branch_spec; - wire predicted_branch; - reg [31:0] fetch_addr_n; - wire unused_fetch_addr_n0; - wire fetch_valid; - wire fetch_ready; - wire [31:0] fetch_rdata; - wire [31:0] fetch_addr; - wire fetch_err; - wire fetch_err_plus2; - wire if_instr_valid; - wire [31:0] if_instr_rdata; - wire [31:0] if_instr_addr; - wire if_instr_err; - reg [31:0] exc_pc; - wire [5:0] irq_id; - wire unused_irq_bit; - wire if_id_pipe_reg_we; - wire stall_dummy_instr; - wire [31:0] instr_out; - wire instr_is_compressed_out; - wire illegal_c_instr_out; - wire instr_err_out; - wire predict_branch_taken; - wire [31:0] predict_branch_pc; - wire [2:0] pc_mux_internal; - wire [7:0] unused_boot_addr; - wire [7:0] unused_csr_mtvec; - assign unused_boot_addr = boot_addr_i[7:0]; - assign unused_csr_mtvec = csr_mtvec_i[7:0]; - assign irq_id = {exc_cause}; - assign unused_irq_bit = irq_id[5]; - localparam [1:0] ibex_pkg_EXC_PC_DBD = 2; - localparam [1:0] ibex_pkg_EXC_PC_DBG_EXC = 3; - localparam [1:0] ibex_pkg_EXC_PC_EXC = 0; - localparam [1:0] ibex_pkg_EXC_PC_IRQ = 1; - always @(*) begin : exc_pc_mux - case (exc_pc_mux_i) - ibex_pkg_EXC_PC_EXC: exc_pc = {csr_mtvec_i[31:8], 8'h00}; - ibex_pkg_EXC_PC_IRQ: exc_pc = {csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00}; - ibex_pkg_EXC_PC_DBD: exc_pc = DmHaltAddr; - ibex_pkg_EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; - default: exc_pc = {csr_mtvec_i[31:8], 8'h00}; - endcase - end - localparam [2:0] ibex_pkg_PC_BP = 5; - assign pc_mux_internal = ((BranchPredictor && predict_branch_taken) && !pc_set_i ? ibex_pkg_PC_BP : pc_mux_i); - localparam [2:0] ibex_pkg_PC_BOOT = 0; - localparam [2:0] ibex_pkg_PC_DRET = 4; - localparam [2:0] ibex_pkg_PC_ERET = 3; - localparam [2:0] ibex_pkg_PC_EXC = 2; - localparam [2:0] ibex_pkg_PC_JUMP = 1; - always @(*) begin : fetch_addr_mux - case (pc_mux_internal) - ibex_pkg_PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; - ibex_pkg_PC_JUMP: fetch_addr_n = branch_target_ex_i; - ibex_pkg_PC_EXC: fetch_addr_n = exc_pc; - ibex_pkg_PC_ERET: fetch_addr_n = csr_mepc_i; - ibex_pkg_PC_DRET: fetch_addr_n = csr_depc_i; - ibex_pkg_PC_BP: fetch_addr_n = (BranchPredictor ? predict_branch_pc : {boot_addr_i[31:8], 8'h80}); - default: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; - endcase - end - assign csr_mtvec_init_o = (pc_mux_i == ibex_pkg_PC_BOOT) & pc_set_i; - generate - if (ICache) begin : gen_icache - ibex_icache #(.ICacheECC(ICacheECC)) icache_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(req_i), - .branch_i(branch_req), - .branch_spec_i(branch_spec), - .addr_i({fetch_addr_n[31:1], 1'b0}), - .ready_i(fetch_ready), - .valid_o(fetch_valid), - .rdata_o(fetch_rdata), - .addr_o(fetch_addr), - .err_o(fetch_err), - .err_plus2_o(fetch_err_plus2), - .instr_req_o(instr_req_o), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(instr_pmp_err_i), - .icache_enable_i(icache_enable_i), - .icache_inval_i(icache_inval_i), - .busy_o(prefetch_busy) - ); - wire unused_nt_branch_mispredict; - wire unused_predicted_branch; - assign unused_nt_branch_mispredict = nt_branch_mispredict_i; - assign unused_predicted_branch = predicted_branch; - end - else begin : gen_prefetch_buffer - ibex_prefetch_buffer #(.BranchPredictor(BranchPredictor)) prefetch_buffer_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(req_i), - .branch_i(branch_req), - .branch_spec_i(branch_spec), - .predicted_branch_i(predicted_branch), - .branch_mispredict_i(nt_branch_mispredict_i), - .addr_i({fetch_addr_n[31:1], 1'b0}), - .ready_i(fetch_ready), - .valid_o(fetch_valid), - .rdata_o(fetch_rdata), - .addr_o(fetch_addr), - .err_o(fetch_err), - .err_plus2_o(fetch_err_plus2), - .instr_req_o(instr_req_o), - .instr_addr_o(instr_addr_o), - .instr_gnt_i(instr_gnt_i), - .instr_rvalid_i(instr_rvalid_i), - .instr_rdata_i(instr_rdata_i), - .instr_err_i(instr_err_i), - .instr_pmp_err_i(instr_pmp_err_i), - .busy_o(prefetch_busy) - ); - wire unused_icen; - wire unused_icinv; - assign unused_icen = icache_enable_i; - assign unused_icinv = icache_inval_i; - end - endgenerate - assign unused_fetch_addr_n0 = fetch_addr_n[0]; - assign branch_req = pc_set_i | predict_branch_taken; - assign branch_spec = pc_set_spec_i | predict_branch_taken; - assign pc_if_o = if_instr_addr; - assign if_busy_o = prefetch_busy; - wire [31:0] instr_decompressed; - wire illegal_c_insn; - wire instr_is_compressed; - ibex_compressed_decoder compressed_decoder_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .valid_i(fetch_valid & ~fetch_err), - .instr_i(if_instr_rdata), - .instr_o(instr_decompressed), - .is_compressed_o(instr_is_compressed), - .illegal_instr_o(illegal_c_insn) - ); - generate - if (DummyInstructions) begin : gen_dummy_instr - wire insert_dummy_instr; - wire [31:0] dummy_instr_data; - ibex_dummy_instr dummy_instr_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .dummy_instr_en_i(dummy_instr_en_i), - .dummy_instr_mask_i(dummy_instr_mask_i), - .dummy_instr_seed_en_i(dummy_instr_seed_en_i), - .dummy_instr_seed_i(dummy_instr_seed_i), - .fetch_valid_i(fetch_valid), - .id_in_ready_i(id_in_ready_i), - .insert_dummy_instr_o(insert_dummy_instr), - .dummy_instr_data_o(dummy_instr_data) - ); - assign instr_out = (insert_dummy_instr ? dummy_instr_data : instr_decompressed); - assign instr_is_compressed_out = (insert_dummy_instr ? 1'b0 : instr_is_compressed); - assign illegal_c_instr_out = (insert_dummy_instr ? 1'b0 : illegal_c_insn); - assign instr_err_out = (insert_dummy_instr ? 1'b0 : if_instr_err); - assign stall_dummy_instr = insert_dummy_instr; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - dummy_instr_id_o <= 1'b0; - else if (if_id_pipe_reg_we) - dummy_instr_id_o <= insert_dummy_instr; - end - else begin : gen_no_dummy_instr - wire unused_dummy_en; - wire [2:0] unused_dummy_mask; - wire unused_dummy_seed_en; - wire [31:0] unused_dummy_seed; - assign unused_dummy_en = dummy_instr_en_i; - assign unused_dummy_mask = dummy_instr_mask_i; - assign unused_dummy_seed_en = dummy_instr_seed_en_i; - assign unused_dummy_seed = dummy_instr_seed_i; - assign instr_out = instr_decompressed; - assign instr_is_compressed_out = instr_is_compressed; - assign illegal_c_instr_out = illegal_c_insn; - assign instr_err_out = if_instr_err; - assign stall_dummy_instr = 1'b0; - wire [1:1] sv2v_tmp_253B9; - assign sv2v_tmp_253B9 = 1'b0; - always @(*) dummy_instr_id_o = sv2v_tmp_253B9; - end - endgenerate - assign instr_valid_id_d = ((if_instr_valid & id_in_ready_i) & ~pc_set_i) | (instr_valid_id_q & ~instr_valid_clear_i); - assign instr_new_id_d = if_instr_valid & id_in_ready_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - instr_valid_id_q <= 1'b0; - instr_new_id_q <= 1'b0; - end - else begin - instr_valid_id_q <= instr_valid_id_d; - instr_new_id_q <= instr_new_id_d; - end - assign instr_valid_id_o = instr_valid_id_q; - assign instr_new_id_o = instr_new_id_q; - assign if_id_pipe_reg_we = instr_new_id_d; - always @(posedge clk_i) - if (if_id_pipe_reg_we) begin - instr_rdata_id_o <= instr_out; - instr_rdata_alu_id_o <= instr_out; - instr_fetch_err_o <= instr_err_out; - instr_fetch_err_plus2_o <= fetch_err_plus2; - instr_rdata_c_id_o <= if_instr_rdata[15:0]; - instr_is_compressed_id_o <= instr_is_compressed_out; - illegal_c_insn_id_o <= illegal_c_instr_out; - pc_id_o <= pc_if_o; - end - generate - if (PCIncrCheck) begin : g_secure_pc - wire [31:0] prev_instr_addr_incr; - reg prev_instr_seq_q; - wire prev_instr_seq_d; - assign prev_instr_seq_d = ((prev_instr_seq_q | instr_new_id_d) & ~branch_req) & ~stall_dummy_instr; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - prev_instr_seq_q <= 1'b0; - else - prev_instr_seq_q <= prev_instr_seq_d; - assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o && !instr_fetch_err_o ? 32'd2 : 32'd4); - assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); - end - else begin : g_no_secure_pc - assign pc_mismatch_alert_o = 1'b0; - end - endgenerate - generate - if (BranchPredictor) begin : g_branch_predictor - reg [31:0] instr_skid_data_q; - reg [31:0] instr_skid_addr_q; - reg instr_skid_bp_taken_q; - reg instr_skid_valid_q; - wire instr_skid_valid_d; - wire instr_skid_en; - reg instr_bp_taken_q; - wire instr_bp_taken_d; - wire predict_branch_taken_raw; - always @(posedge clk_i) - if (if_id_pipe_reg_we) - instr_bp_taken_q <= instr_bp_taken_d; - assign instr_skid_en = (predicted_branch & ~id_in_ready_i) & ~instr_skid_valid_q; - assign instr_skid_valid_d = ((instr_skid_valid_q & ~id_in_ready_i) & ~stall_dummy_instr) | instr_skid_en; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - instr_skid_valid_q <= 1'b0; - else - instr_skid_valid_q <= instr_skid_valid_d; - always @(posedge clk_i) - if (instr_skid_en) begin - instr_skid_bp_taken_q <= predict_branch_taken; - instr_skid_data_q <= fetch_rdata; - instr_skid_addr_q <= fetch_addr; - end - ibex_branch_predict branch_predict_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .fetch_rdata_i(fetch_rdata), - .fetch_pc_i(fetch_addr), - .fetch_valid_i(fetch_valid), - .predict_branch_taken_o(predict_branch_taken_raw), - .predict_branch_pc_o(predict_branch_pc) - ); - assign predict_branch_taken = (predict_branch_taken_raw & ~instr_skid_valid_q) & ~fetch_err; - assign predicted_branch = predict_branch_taken & ~pc_set_i; - assign if_instr_valid = fetch_valid | instr_skid_valid_q; - assign if_instr_rdata = (instr_skid_valid_q ? instr_skid_data_q : fetch_rdata); - assign if_instr_addr = (instr_skid_valid_q ? instr_skid_addr_q : fetch_addr); - assign if_instr_err = ~instr_skid_valid_q & fetch_err; - assign instr_bp_taken_d = (instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken); - assign fetch_ready = (id_in_ready_i & ~stall_dummy_instr) & ~instr_skid_valid_q; - assign instr_bp_taken_o = instr_bp_taken_q; - end - else begin : g_no_branch_predictor - assign instr_bp_taken_o = 1'b0; - assign predict_branch_taken = 1'b0; - assign predicted_branch = 1'b0; - assign predict_branch_pc = 32'b00000000000000000000000000000000; - assign if_instr_valid = fetch_valid; - assign if_instr_rdata = fetch_rdata; - assign if_instr_addr = fetch_addr; - assign if_instr_err = fetch_err; - assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_load_store_unit.v b/flow/designs/src/ibex/ibex_load_store_unit.v deleted file mode 100644 index c302b6130e..0000000000 --- a/flow/designs/src/ibex/ibex_load_store_unit.v +++ /dev/null @@ -1,337 +0,0 @@ -module ibex_load_store_unit ( - clk_i, - rst_ni, - data_req_o, - data_gnt_i, - data_rvalid_i, - data_err_i, - data_pmp_err_i, - data_addr_o, - data_we_o, - data_be_o, - data_wdata_o, - data_rdata_i, - lsu_we_i, - lsu_type_i, - lsu_wdata_i, - lsu_sign_ext_i, - lsu_rdata_o, - lsu_rdata_valid_o, - lsu_req_i, - adder_result_ex_i, - addr_incr_req_o, - addr_last_o, - lsu_req_done_o, - lsu_resp_valid_o, - load_err_o, - store_err_o, - busy_o, - perf_load_o, - perf_store_o -); - input wire clk_i; - input wire rst_ni; - output reg data_req_o; - input wire data_gnt_i; - input wire data_rvalid_i; - input wire data_err_i; - input wire data_pmp_err_i; - output wire [31:0] data_addr_o; - output wire data_we_o; - output wire [3:0] data_be_o; - output wire [31:0] data_wdata_o; - input wire [31:0] data_rdata_i; - input wire lsu_we_i; - input wire [1:0] lsu_type_i; - input wire [31:0] lsu_wdata_i; - input wire lsu_sign_ext_i; - output wire [31:0] lsu_rdata_o; - output wire lsu_rdata_valid_o; - input wire lsu_req_i; - input wire [31:0] adder_result_ex_i; - output reg addr_incr_req_o; - output wire [31:0] addr_last_o; - output wire lsu_req_done_o; - output wire lsu_resp_valid_o; - output wire load_err_o; - output wire store_err_o; - output wire busy_o; - output reg perf_load_o; - output reg perf_store_o; - wire [31:0] data_addr; - wire [31:0] data_addr_w_aligned; - reg [31:0] addr_last_q; - reg addr_update; - reg ctrl_update; - reg rdata_update; - reg [31:8] rdata_q; - reg [1:0] rdata_offset_q; - reg [1:0] data_type_q; - reg data_sign_ext_q; - reg data_we_q; - wire [1:0] data_offset; - reg [3:0] data_be; - reg [31:0] data_wdata; - reg [31:0] data_rdata_ext; - reg [31:0] rdata_w_ext; - reg [31:0] rdata_h_ext; - reg [31:0] rdata_b_ext; - wire split_misaligned_access; - reg handle_misaligned_q; - reg handle_misaligned_d; - reg pmp_err_q; - reg pmp_err_d; - reg lsu_err_q; - reg lsu_err_d; - wire data_or_pmp_err; - reg [2:0] ls_fsm_cs; - reg [2:0] ls_fsm_ns; - assign data_addr = adder_result_ex_i; - assign data_offset = data_addr[1:0]; - always @(*) - case (lsu_type_i) - 2'b00: - if (!handle_misaligned_q) - case (data_offset) - 2'b00: data_be = 4'b1111; - 2'b01: data_be = 4'b1110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - else - case (data_offset) - 2'b00: data_be = 4'b0000; - 2'b01: data_be = 4'b0001; - 2'b10: data_be = 4'b0011; - 2'b11: data_be = 4'b0111; - default: data_be = 4'b1111; - endcase - 2'b01: - if (!handle_misaligned_q) - case (data_offset) - 2'b00: data_be = 4'b0011; - 2'b01: data_be = 4'b0110; - 2'b10: data_be = 4'b1100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - else - data_be = 4'b0001; - 2'b10, 2'b11: - case (data_offset) - 2'b00: data_be = 4'b0001; - 2'b01: data_be = 4'b0010; - 2'b10: data_be = 4'b0100; - 2'b11: data_be = 4'b1000; - default: data_be = 4'b1111; - endcase - default: data_be = 4'b1111; - endcase - always @(*) - case (data_offset) - 2'b00: data_wdata = lsu_wdata_i[31:0]; - 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]}; - 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]}; - 2'b11: data_wdata = {lsu_wdata_i[7:0], lsu_wdata_i[31:8]}; - default: data_wdata = lsu_wdata_i[31:0]; - endcase - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rdata_q <= {24 {1'sb0}}; - else if (rdata_update) - rdata_q <= data_rdata_i[31:8]; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - rdata_offset_q <= 2'h0; - data_type_q <= 2'h0; - data_sign_ext_q <= 1'b0; - data_we_q <= 1'b0; - end - else if (ctrl_update) begin - rdata_offset_q <= data_offset; - data_type_q <= lsu_type_i; - data_sign_ext_q <= lsu_sign_ext_i; - data_we_q <= lsu_we_i; - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - addr_last_q <= {32 {1'sb0}}; - else if (addr_update) - addr_last_q <= data_addr; - always @(*) - case (rdata_offset_q) - 2'b00: rdata_w_ext = data_rdata_i[31:0]; - 2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]}; - 2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]}; - 2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]}; - default: rdata_w_ext = data_rdata_i[31:0]; - endcase - always @(*) - case (rdata_offset_q) - 2'b00: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; - else - rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]}; - 2'b01: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[23:8]}; - else - rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]}; - 2'b10: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[31:16]}; - else - rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]}; - 2'b11: - if (!data_sign_ext_q) - rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]}; - else - rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]}; - default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; - endcase - always @(*) - case (rdata_offset_q) - 2'b00: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; - else - rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]}; - 2'b01: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[15:8]}; - else - rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]}; - 2'b10: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[23:16]}; - else - rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]}; - 2'b11: - if (!data_sign_ext_q) - rdata_b_ext = {24'h000000, data_rdata_i[31:24]}; - else - rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]}; - default: rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; - endcase - always @(*) - case (data_type_q) - 2'b00: data_rdata_ext = rdata_w_ext; - 2'b01: data_rdata_ext = rdata_h_ext; - 2'b10, 2'b11: data_rdata_ext = rdata_b_ext; - default: data_rdata_ext = rdata_w_ext; - endcase - assign split_misaligned_access = ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); - localparam [2:0] IDLE = 0; - localparam [2:0] WAIT_GNT = 3; - localparam [2:0] WAIT_GNT_MIS = 1; - localparam [2:0] WAIT_RVALID_MIS = 2; - localparam [2:0] WAIT_RVALID_MIS_GNTS_DONE = 4; - always @(*) begin - ls_fsm_ns = ls_fsm_cs; - data_req_o = 1'b0; - addr_incr_req_o = 1'b0; - handle_misaligned_d = handle_misaligned_q; - pmp_err_d = pmp_err_q; - lsu_err_d = lsu_err_q; - addr_update = 1'b0; - ctrl_update = 1'b0; - rdata_update = 1'b0; - perf_load_o = 1'b0; - perf_store_o = 1'b0; - case (ls_fsm_cs) - IDLE: begin - pmp_err_d = 1'b0; - if (lsu_req_i) begin - data_req_o = 1'b1; - pmp_err_d = data_pmp_err_i; - lsu_err_d = 1'b0; - perf_load_o = ~lsu_we_i; - perf_store_o = lsu_we_i; - if (data_gnt_i) begin - ctrl_update = 1'b1; - addr_update = 1'b1; - handle_misaligned_d = split_misaligned_access; - ls_fsm_ns = (split_misaligned_access ? WAIT_RVALID_MIS : IDLE); - end - else - ls_fsm_ns = (split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT); - end - end - WAIT_GNT_MIS: begin - data_req_o = 1'b1; - if (data_gnt_i || pmp_err_q) begin - addr_update = 1'b1; - ctrl_update = 1'b1; - handle_misaligned_d = 1'b1; - ls_fsm_ns = WAIT_RVALID_MIS; - end - end - WAIT_RVALID_MIS: begin - data_req_o = 1'b1; - addr_incr_req_o = 1'b1; - if (data_rvalid_i || pmp_err_q) begin - pmp_err_d = data_pmp_err_i; - lsu_err_d = data_err_i | pmp_err_q; - rdata_update = ~data_we_q; - ls_fsm_ns = (data_gnt_i ? IDLE : WAIT_GNT); - addr_update = data_gnt_i & ~(data_err_i | pmp_err_q); - handle_misaligned_d = ~data_gnt_i; - end - else if (data_gnt_i) begin - ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE; - handle_misaligned_d = 1'b0; - end - end - WAIT_GNT: begin - addr_incr_req_o = handle_misaligned_q; - data_req_o = 1'b1; - if (data_gnt_i || pmp_err_q) begin - ctrl_update = 1'b1; - addr_update = ~lsu_err_q; - ls_fsm_ns = IDLE; - handle_misaligned_d = 1'b0; - end - end - WAIT_RVALID_MIS_GNTS_DONE: begin - addr_incr_req_o = 1'b1; - if (data_rvalid_i) begin - pmp_err_d = data_pmp_err_i; - lsu_err_d = data_err_i; - addr_update = ~data_err_i; - rdata_update = ~data_we_q; - ls_fsm_ns = IDLE; - end - end - default: ls_fsm_ns = IDLE; - endcase - end - assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - ls_fsm_cs <= IDLE; - handle_misaligned_q <= 1'b0; - pmp_err_q <= 1'b0; - lsu_err_q <= 1'b0; - end - else begin - ls_fsm_cs <= ls_fsm_ns; - handle_misaligned_q <= handle_misaligned_d; - pmp_err_q <= pmp_err_d; - lsu_err_q <= lsu_err_d; - end - assign data_or_pmp_err = (lsu_err_q | data_err_i) | pmp_err_q; - assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE); - assign lsu_rdata_valid_o = (((ls_fsm_cs == IDLE) & data_rvalid_i) & ~data_or_pmp_err) & ~data_we_q; - assign lsu_rdata_o = data_rdata_ext; - assign data_addr_w_aligned = {data_addr[31:2], 2'b00}; - assign data_addr_o = data_addr_w_aligned; - assign data_wdata_o = data_wdata; - assign data_we_o = lsu_we_i; - assign data_be_o = data_be; - assign addr_last_o = addr_last_q; - assign load_err_o = (data_or_pmp_err & ~data_we_q) & lsu_resp_valid_o; - assign store_err_o = (data_or_pmp_err & data_we_q) & lsu_resp_valid_o; - assign busy_o = ls_fsm_cs != IDLE; -endmodule diff --git a/flow/designs/src/ibex/ibex_multdiv_fast.v b/flow/designs/src/ibex/ibex_multdiv_fast.v deleted file mode 100644 index 695e01b622..0000000000 --- a/flow/designs/src/ibex/ibex_multdiv_fast.v +++ /dev/null @@ -1,400 +0,0 @@ -module ibex_multdiv_fast ( - clk_i, - rst_ni, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - operator_i, - signed_mode_i, - op_a_i, - op_b_i, - alu_adder_ext_i, - alu_adder_i, - equal_to_zero_i, - data_ind_timing_i, - alu_operand_a_o, - alu_operand_b_o, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - multdiv_ready_id_i, - multdiv_result_o, - valid_o -); - localparam integer ibex_pkg_RV32MFast = 2; - parameter integer RV32M = ibex_pkg_RV32MFast; - input wire clk_i; - input wire rst_ni; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] operator_i; - input wire [1:0] signed_mode_i; - input wire [31:0] op_a_i; - input wire [31:0] op_b_i; - input wire [33:0] alu_adder_ext_i; - input wire [31:0] alu_adder_i; - input wire equal_to_zero_i; - input wire data_ind_timing_i; - output reg [32:0] alu_operand_a_o; - output reg [32:0] alu_operand_b_o; - input wire [67:0] imd_val_q_i; - output wire [67:0] imd_val_d_o; - output wire [1:0] imd_val_we_o; - input wire multdiv_ready_id_i; - output wire [31:0] multdiv_result_o; - output wire valid_o; - wire signed [34:0] mac_res_signed; - wire [34:0] mac_res_ext; - reg [33:0] accum; - reg sign_a; - reg sign_b; - reg mult_valid; - wire signed_mult; - reg [33:0] mac_res_d; - reg [33:0] op_remainder_d; - wire [33:0] mac_res; - wire div_sign_a; - wire div_sign_b; - reg is_greater_equal; - wire div_change_sign; - wire rem_change_sign; - wire [31:0] one_shift; - wire [31:0] op_denominator_q; - reg [31:0] op_numerator_q; - reg [31:0] op_quotient_q; - reg [31:0] op_denominator_d; - reg [31:0] op_numerator_d; - reg [31:0] op_quotient_d; - wire [31:0] next_remainder; - wire [32:0] next_quotient; - wire [31:0] res_adder_h; - reg div_valid; - reg [4:0] div_counter_q; - reg [4:0] div_counter_d; - wire multdiv_en; - reg mult_hold; - reg div_hold; - reg div_by_zero_d; - reg div_by_zero_q; - wire mult_en_internal; - wire div_en_internal; - reg [2:0] md_state_q; - reg [2:0] md_state_d; - wire unused_mult_sel_i; - assign unused_mult_sel_i = mult_sel_i; - assign mult_en_internal = mult_en_i & ~mult_hold; - assign div_en_internal = div_en_i & ~div_hold; - localparam [2:0] MD_IDLE = 0; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - div_counter_q <= {5 {1'sb0}}; - md_state_q <= MD_IDLE; - op_numerator_q <= {32 {1'sb0}}; - op_quotient_q <= {32 {1'sb0}}; - div_by_zero_q <= 1'b0; - end - else if (div_en_internal) begin - div_counter_q <= div_counter_d; - op_numerator_q <= op_numerator_d; - op_quotient_q <= op_quotient_d; - md_state_q <= md_state_d; - div_by_zero_q <= div_by_zero_d; - end - assign multdiv_en = mult_en_internal | div_en_internal; - assign imd_val_d_o[34+:34] = (div_sel_i ? op_remainder_d : mac_res_d); - assign imd_val_we_o[0] = multdiv_en; - assign imd_val_d_o[0+:34] = {2'b00, op_denominator_d}; - assign imd_val_we_o[1] = div_en_internal; - assign op_denominator_q = imd_val_q_i[31-:32]; - wire [1:0] unused_imd_val; - assign unused_imd_val = imd_val_q_i[33-:2]; - wire unused_mac_res_ext; - assign unused_mac_res_ext = mac_res_ext[34]; - assign signed_mult = signed_mode_i != 2'b00; - assign multdiv_result_o = (div_sel_i ? imd_val_q_i[65-:32] : mac_res_d[31:0]); - localparam [1:0] AHBH = 3; - localparam [1:0] AHBL = 2; - localparam [1:0] ALBH = 1; - localparam [1:0] ALBL = 0; - localparam [0:0] MULH = 1; - localparam [0:0] MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam integer ibex_pkg_RV32MSingleCycle = 3; - generate - if (RV32M == ibex_pkg_RV32MSingleCycle) begin : gen_mult_single_cycle - reg mult_state_q; - reg mult_state_d; - wire signed [33:0] mult1_res; - wire signed [33:0] mult2_res; - wire signed [33:0] mult3_res; - wire [33:0] mult1_res_uns; - wire [33:32] unused_mult1_res_uns; - wire [15:0] mult1_op_a; - wire [15:0] mult1_op_b; - wire [15:0] mult2_op_a; - wire [15:0] mult2_op_b; - reg [15:0] mult3_op_a; - reg [15:0] mult3_op_b; - wire mult1_sign_a; - wire mult1_sign_b; - wire mult2_sign_a; - wire mult2_sign_b; - reg mult3_sign_a; - reg mult3_sign_b; - reg [33:0] summand1; - reg [33:0] summand2; - reg [33:0] summand3; - assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b}); - assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b}); - assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b}); - assign mac_res_signed = ($signed(summand1) + $signed(summand2)) + $signed(summand3); - assign mult1_res_uns = $unsigned(mult1_res); - assign mac_res_ext = $unsigned(mac_res_signed); - assign mac_res = mac_res_ext[33:0]; - wire [1:1] sv2v_tmp_1E8D3; - assign sv2v_tmp_1E8D3 = signed_mode_i[0] & op_a_i[31]; - always @(*) sign_a = sv2v_tmp_1E8D3; - wire [1:1] sv2v_tmp_3B65C; - assign sv2v_tmp_3B65C = signed_mode_i[1] & op_b_i[31]; - always @(*) sign_b = sv2v_tmp_3B65C; - assign mult1_sign_a = 1'b0; - assign mult1_sign_b = 1'b0; - assign mult1_op_a = op_a_i[15:0]; - assign mult1_op_b = op_b_i[15:0]; - assign mult2_sign_a = 1'b0; - assign mult2_sign_b = sign_b; - assign mult2_op_a = op_a_i[15:0]; - assign mult2_op_b = op_b_i[31:16]; - wire [18:1] sv2v_tmp_4D45D; - assign sv2v_tmp_4D45D = imd_val_q_i[67-:18]; - always @(*) accum[17:0] = sv2v_tmp_4D45D; - wire [16:1] sv2v_tmp_D5F47; - assign sv2v_tmp_D5F47 = {16 {signed_mult & imd_val_q_i[67]}}; - always @(*) accum[33:18] = sv2v_tmp_D5F47; - always @(*) begin - mult3_sign_a = sign_a; - mult3_sign_b = 1'b0; - mult3_op_a = op_a_i[31:16]; - mult3_op_b = op_b_i[15:0]; - summand1 = {18'h00000, mult1_res_uns[31:16]}; - summand2 = $unsigned(mult2_res); - summand3 = $unsigned(mult3_res); - mac_res_d = {2'b00, mac_res[15:0], mult1_res_uns[15:0]}; - mult_valid = mult_en_i; - mult_state_d = MULL; - mult_hold = 1'b0; - case (mult_state_q) - MULL: - if (operator_i != ibex_pkg_MD_OP_MULL) begin - mac_res_d = mac_res; - mult_valid = 1'b0; - mult_state_d = MULH; - end - else - mult_hold = ~multdiv_ready_id_i; - MULH: begin - mult3_sign_a = sign_a; - mult3_sign_b = sign_b; - mult3_op_a = op_a_i[31:16]; - mult3_op_b = op_b_i[31:16]; - mac_res_d = mac_res; - summand1 = {34 {1'sb0}}; - summand2 = accum; - summand3 = mult3_res; - mult_state_d = MULL; - mult_valid = 1'b1; - mult_hold = ~multdiv_ready_id_i; - end - default: mult_state_d = MULL; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mult_state_q <= MULL; - else if (mult_en_internal) - mult_state_q <= mult_state_d; - assign unused_mult1_res_uns = mult1_res_uns[33:32]; - end - else begin : gen_mult_fast - reg [15:0] mult_op_a; - reg [15:0] mult_op_b; - reg [1:0] mult_state_q; - reg [1:0] mult_state_d; - assign mac_res_signed = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum); - assign mac_res_ext = $unsigned(mac_res_signed); - assign mac_res = mac_res_ext[33:0]; - always @(*) begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[15:0]; - sign_a = 1'b0; - sign_b = 1'b0; - accum = imd_val_q_i[34+:34]; - mac_res_d = mac_res; - mult_state_d = mult_state_q; - mult_valid = 1'b0; - mult_hold = 1'b0; - case (mult_state_q) - ALBL: begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[15:0]; - sign_a = 1'b0; - sign_b = 1'b0; - accum = {34 {1'sb0}}; - mac_res_d = mac_res; - mult_state_d = ALBH; - end - ALBH: begin - mult_op_a = op_a_i[15:0]; - mult_op_b = op_b_i[31:16]; - sign_a = 1'b0; - sign_b = signed_mode_i[1] & op_b_i[31]; - accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; - if (operator_i == ibex_pkg_MD_OP_MULL) - mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; - else - mac_res_d = mac_res; - mult_state_d = AHBL; - end - AHBL: begin - mult_op_a = op_a_i[31:16]; - mult_op_b = op_b_i[15:0]; - sign_a = signed_mode_i[0] & op_a_i[31]; - sign_b = 1'b0; - if (operator_i == ibex_pkg_MD_OP_MULL) begin - accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; - mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; - mult_valid = 1'b1; - mult_state_d = ALBL; - mult_hold = ~multdiv_ready_id_i; - end - else begin - accum = imd_val_q_i[34+:34]; - mac_res_d = mac_res; - mult_state_d = AHBH; - end - end - AHBH: begin - mult_op_a = op_a_i[31:16]; - mult_op_b = op_b_i[31:16]; - sign_a = signed_mode_i[0] & op_a_i[31]; - sign_b = signed_mode_i[1] & op_b_i[31]; - accum[17:0] = imd_val_q_i[67-:18]; - accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}}; - mac_res_d = mac_res; - mult_valid = 1'b1; - mult_state_d = ALBL; - mult_hold = ~multdiv_ready_id_i; - end - default: mult_state_d = ALBL; - endcase - end - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - mult_state_q <= ALBL; - else if (mult_en_internal) - mult_state_q <= mult_state_d; - end - endgenerate - assign res_adder_h = alu_adder_ext_i[32:1]; - wire [1:0] unused_alu_adder_ext; - assign unused_alu_adder_ext = {alu_adder_ext_i[33], alu_adder_ext_i[0]}; - assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[65-:32]); - assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q}); - assign one_shift = {31'b0000000000000000000000000000000, 1'b1} << div_counter_q; - always @(*) - if ((imd_val_q_i[65] ^ op_denominator_q[31]) == 1'b0) - is_greater_equal = res_adder_h[31] == 1'b0; - else - is_greater_equal = imd_val_q_i[65]; - assign div_sign_a = op_a_i[31] & signed_mode_i[0]; - assign div_sign_b = op_b_i[31] & signed_mode_i[1]; - assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q; - assign rem_change_sign = div_sign_a; - localparam [2:0] MD_ABS_A = 1; - localparam [2:0] MD_ABS_B = 2; - localparam [2:0] MD_CHANGE_SIGN = 5; - localparam [2:0] MD_COMP = 3; - localparam [2:0] MD_FINISH = 6; - localparam [2:0] MD_LAST = 4; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - always @(*) begin - div_counter_d = div_counter_q - 5'h01; - op_remainder_d = imd_val_q_i[34+:34]; - op_quotient_d = op_quotient_q; - md_state_d = md_state_q; - op_numerator_d = op_numerator_q; - op_denominator_d = op_denominator_q; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - div_valid = 1'b0; - div_hold = 1'b0; - div_by_zero_d = div_by_zero_q; - case (md_state_q) - MD_IDLE: begin - if (operator_i == ibex_pkg_MD_OP_DIV) begin - op_remainder_d = {34 {1'sb1}}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - div_by_zero_d = equal_to_zero_i; - end - else begin - op_remainder_d = {2'b00, op_a_i}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - end - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - div_counter_d = 5'd31; - end - MD_ABS_A: begin - op_quotient_d = {32 {1'sb0}}; - op_numerator_d = (div_sign_a ? alu_adder_i : op_a_i); - md_state_d = MD_ABS_B; - div_counter_d = 5'd31; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_a_i, 1'b1}; - end - MD_ABS_B: begin - op_remainder_d = {33'h000000000, op_numerator_q[31]}; - op_denominator_d = (div_sign_b ? alu_adder_i : op_b_i); - md_state_d = MD_COMP; - div_counter_d = 5'd31; - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_COMP: begin - op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]}; - op_quotient_d = next_quotient[31:0]; - md_state_d = (div_counter_q == 5'd1 ? MD_LAST : MD_COMP); - alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; - alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; - end - MD_LAST: begin - if (operator_i == ibex_pkg_MD_OP_DIV) - op_remainder_d = {1'b0, next_quotient}; - else - op_remainder_d = {2'b00, next_remainder[31:0]}; - alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; - alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; - md_state_d = MD_CHANGE_SIGN; - end - MD_CHANGE_SIGN: begin - md_state_d = MD_FINISH; - if (operator_i == ibex_pkg_MD_OP_DIV) - op_remainder_d = (div_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); - else - op_remainder_d = (rem_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~imd_val_q_i[65-:32], 1'b1}; - end - MD_FINISH: begin - md_state_d = MD_IDLE; - div_hold = ~multdiv_ready_id_i; - div_valid = 1'b1; - end - default: md_state_d = MD_IDLE; - endcase - end - assign valid_o = mult_valid | div_valid; -endmodule diff --git a/flow/designs/src/ibex/ibex_multdiv_slow.v b/flow/designs/src/ibex/ibex_multdiv_slow.v deleted file mode 100644 index 84934ee753..0000000000 --- a/flow/designs/src/ibex/ibex_multdiv_slow.v +++ /dev/null @@ -1,279 +0,0 @@ -module ibex_multdiv_slow ( - clk_i, - rst_ni, - mult_en_i, - div_en_i, - mult_sel_i, - div_sel_i, - operator_i, - signed_mode_i, - op_a_i, - op_b_i, - alu_adder_ext_i, - alu_adder_i, - equal_to_zero_i, - data_ind_timing_i, - alu_operand_a_o, - alu_operand_b_o, - imd_val_q_i, - imd_val_d_o, - imd_val_we_o, - multdiv_ready_id_i, - multdiv_result_o, - valid_o -); - input wire clk_i; - input wire rst_ni; - input wire mult_en_i; - input wire div_en_i; - input wire mult_sel_i; - input wire div_sel_i; - input wire [1:0] operator_i; - input wire [1:0] signed_mode_i; - input wire [31:0] op_a_i; - input wire [31:0] op_b_i; - input wire [33:0] alu_adder_ext_i; - input wire [31:0] alu_adder_i; - input wire equal_to_zero_i; - input wire data_ind_timing_i; - output reg [32:0] alu_operand_a_o; - output reg [32:0] alu_operand_b_o; - input wire [67:0] imd_val_q_i; - output wire [67:0] imd_val_d_o; - output wire [1:0] imd_val_we_o; - input wire multdiv_ready_id_i; - output wire [31:0] multdiv_result_o; - output wire valid_o; - reg [2:0] md_state_q; - reg [2:0] md_state_d; - wire [32:0] accum_window_q; - reg [32:0] accum_window_d; - wire unused_imd_val0; - wire [1:0] unused_imd_val1; - wire [32:0] res_adder_l; - wire [32:0] res_adder_h; - reg [4:0] multdiv_count_q; - reg [4:0] multdiv_count_d; - reg [32:0] op_b_shift_q; - reg [32:0] op_b_shift_d; - reg [32:0] op_a_shift_q; - reg [32:0] op_a_shift_d; - wire [32:0] op_a_ext; - wire [32:0] op_b_ext; - wire [32:0] one_shift; - wire [32:0] op_a_bw_pp; - wire [32:0] op_a_bw_last_pp; - wire [31:0] b_0; - wire sign_a; - wire sign_b; - wire [32:0] next_quotient; - wire [31:0] next_remainder; - wire [31:0] op_numerator_q; - reg [31:0] op_numerator_d; - wire is_greater_equal; - wire div_change_sign; - wire rem_change_sign; - reg div_by_zero_d; - reg div_by_zero_q; - reg multdiv_hold; - wire multdiv_en; - assign res_adder_l = alu_adder_ext_i[32:0]; - assign res_adder_h = alu_adder_ext_i[33:1]; - assign imd_val_d_o[34+:34] = {1'b0, accum_window_d}; - assign imd_val_we_o[0] = ~multdiv_hold; - assign accum_window_q = imd_val_q_i[66-:33]; - assign unused_imd_val0 = imd_val_q_i[67]; - assign imd_val_d_o[0+:34] = {2'b00, op_numerator_d}; - assign imd_val_we_o[1] = multdiv_en; - assign op_numerator_q = imd_val_q_i[31-:32]; - assign unused_imd_val1 = imd_val_q_i[33-:2]; - localparam [2:0] MD_ABS_A = 1; - localparam [2:0] MD_ABS_B = 2; - localparam [2:0] MD_CHANGE_SIGN = 5; - localparam [2:0] MD_IDLE = 0; - localparam [2:0] MD_LAST = 4; - localparam [1:0] ibex_pkg_MD_OP_DIV = 2; - localparam [1:0] ibex_pkg_MD_OP_MULH = 1; - localparam [1:0] ibex_pkg_MD_OP_MULL = 0; - localparam [1:0] ibex_pkg_MD_OP_REM = 3; - always @(*) begin - alu_operand_a_o = accum_window_q; - case (operator_i) - ibex_pkg_MD_OP_MULL: alu_operand_b_o = op_a_bw_pp; - ibex_pkg_MD_OP_MULH: alu_operand_b_o = (md_state_q == MD_LAST ? op_a_bw_last_pp : op_a_bw_pp); - ibex_pkg_MD_OP_DIV, ibex_pkg_MD_OP_REM: - case (md_state_q) - MD_IDLE: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_ABS_A: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_a_i, 1'b1}; - end - MD_ABS_B: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~op_b_i, 1'b1}; - end - MD_CHANGE_SIGN: begin - alu_operand_a_o = {32'h00000000, 1'b1}; - alu_operand_b_o = {~accum_window_q[31:0], 1'b1}; - end - default: begin - alu_operand_a_o = {accum_window_q[31:0], 1'b1}; - alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; - end - endcase - default: begin - alu_operand_a_o = accum_window_q; - alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; - end - endcase - end - assign b_0 = {32 {op_b_shift_q[0]}}; - assign op_a_bw_pp = {~(op_a_shift_q[32] & op_b_shift_q[0]), op_a_shift_q[31:0] & b_0}; - assign op_a_bw_last_pp = {op_a_shift_q[32] & op_b_shift_q[0], ~(op_a_shift_q[31:0] & b_0)}; - assign sign_a = op_a_i[31] & signed_mode_i[0]; - assign sign_b = op_b_i[31] & signed_mode_i[1]; - assign op_a_ext = {sign_a, op_a_i}; - assign op_b_ext = {sign_b, op_b_i}; - assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31] ? ~res_adder_h[31] : accum_window_q[31]); - assign one_shift = {32'b00000000000000000000000000000000, 1'b1} << multdiv_count_q; - assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]); - assign next_quotient = (is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q); - assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q; - assign rem_change_sign = sign_a; - localparam [2:0] MD_COMP = 3; - localparam [2:0] MD_FINISH = 6; - always @(*) begin - multdiv_count_d = multdiv_count_q; - accum_window_d = accum_window_q; - op_b_shift_d = op_b_shift_q; - op_a_shift_d = op_a_shift_q; - op_numerator_d = op_numerator_q; - md_state_d = md_state_q; - multdiv_hold = 1'b0; - div_by_zero_d = div_by_zero_q; - if (mult_sel_i || div_sel_i) - case (md_state_q) - MD_IDLE: begin - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - op_a_shift_d = op_a_ext << 1; - accum_window_d = {~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:0] & {32 {op_b_i[0]}}}; - op_b_shift_d = op_b_ext >> 1; - md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0) ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_MULH: begin - op_a_shift_d = op_a_ext; - accum_window_d = {1'b1, ~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:1] & {31 {op_b_i[0]}}}; - op_b_shift_d = op_b_ext >> 1; - md_state_d = MD_COMP; - end - ibex_pkg_MD_OP_DIV: begin - accum_window_d = {33 {1'b1}}; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - div_by_zero_d = equal_to_zero_i; - end - ibex_pkg_MD_OP_REM: begin - accum_window_d = op_a_ext; - md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); - end - default: - ; - endcase - multdiv_count_d = 5'd31; - end - MD_ABS_A: begin - op_a_shift_d = {33 {1'sb0}}; - op_numerator_d = (sign_a ? alu_adder_i : op_a_i); - md_state_d = MD_ABS_B; - end - MD_ABS_B: begin - accum_window_d = {32'h00000000, op_numerator_q[31]}; - op_b_shift_d = (sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i}); - md_state_d = MD_COMP; - end - MD_COMP: begin - multdiv_count_d = multdiv_count_q - 5'h01; - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - accum_window_d = res_adder_l; - op_a_shift_d = op_a_shift_q << 1; - op_b_shift_d = op_b_shift_q >> 1; - md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_MULH: begin - accum_window_d = res_adder_h; - op_a_shift_d = op_a_shift_q; - op_b_shift_d = op_b_shift_q >> 1; - md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); - end - ibex_pkg_MD_OP_DIV, ibex_pkg_MD_OP_REM: begin - accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]}; - op_a_shift_d = next_quotient; - md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); - end - default: - ; - endcase - end - MD_LAST: - case (operator_i) - ibex_pkg_MD_OP_MULL: begin - accum_window_d = res_adder_l; - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - ibex_pkg_MD_OP_MULH: begin - accum_window_d = res_adder_l; - md_state_d = MD_IDLE; - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - ibex_pkg_MD_OP_DIV: begin - accum_window_d = next_quotient; - md_state_d = MD_CHANGE_SIGN; - end - ibex_pkg_MD_OP_REM: begin - accum_window_d = {1'b0, next_remainder[31:0]}; - md_state_d = MD_CHANGE_SIGN; - end - default: - ; - endcase - MD_CHANGE_SIGN: begin - md_state_d = MD_FINISH; - case (operator_i) - ibex_pkg_MD_OP_DIV: accum_window_d = (div_change_sign ? {1'b0, alu_adder_i} : accum_window_q); - ibex_pkg_MD_OP_REM: accum_window_d = (rem_change_sign ? {1'b0, alu_adder_i} : accum_window_q); - default: - ; - endcase - end - MD_FINISH: begin - md_state_d = MD_IDLE; - multdiv_hold = ~multdiv_ready_id_i; - end - default: md_state_d = MD_IDLE; - endcase - end - assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - multdiv_count_q <= 5'h00; - op_b_shift_q <= 33'h000000000; - op_a_shift_q <= 33'h000000000; - md_state_q <= MD_IDLE; - div_by_zero_q <= 1'b0; - end - else if (multdiv_en) begin - multdiv_count_q <= multdiv_count_d; - op_b_shift_q <= op_b_shift_d; - op_a_shift_q <= op_a_shift_d; - md_state_q <= md_state_d; - div_by_zero_q <= div_by_zero_d; - end - assign valid_o = (md_state_q == MD_FINISH) | ((md_state_q == MD_LAST) & ((operator_i == ibex_pkg_MD_OP_MULL) | (operator_i == ibex_pkg_MD_OP_MULH))); - assign multdiv_result_o = (div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]); -endmodule diff --git a/flow/designs/src/ibex/ibex_pmp.v b/flow/designs/src/ibex/ibex_pmp.v deleted file mode 100644 index 5487cc0271..0000000000 --- a/flow/designs/src/ibex/ibex_pmp.v +++ /dev/null @@ -1,89 +0,0 @@ -module ibex_pmp ( - clk_i, - rst_ni, - csr_pmp_cfg_i, - csr_pmp_addr_i, - priv_mode_i, - pmp_req_addr_i, - pmp_req_type_i, - pmp_req_err_o -); - parameter [31:0] PMPGranularity = 0; - parameter [31:0] PMPNumChan = 2; - parameter [31:0] PMPNumRegions = 4; - input wire clk_i; - input wire rst_ni; - input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_i; - input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] priv_mode_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 34) + (((PMPNumChan - 1) * 34) - 1) : (PMPNumChan * 34) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 34 : 0)] pmp_req_addr_i; - input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] pmp_req_type_i; - output wire [0:PMPNumChan - 1] pmp_req_err_o; - wire [33:0] region_start_addr [0:PMPNumRegions - 1]; - wire [33:PMPGranularity + 2] region_addr_mask [0:PMPNumRegions - 1]; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_gt; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_lt; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_eq; - reg [(PMPNumChan * PMPNumRegions) - 1:0] region_match_all; - wire [(PMPNumChan * PMPNumRegions) - 1:0] region_perm_check; - reg [PMPNumChan - 1:0] access_fault; - localparam [1:0] ibex_pkg_PMP_MODE_NAPOT = 2'b11; - localparam [1:0] ibex_pkg_PMP_MODE_TOR = 2'b01; - generate - genvar r; - for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_addr_exp - if (r == 0) begin : g_entry0 - assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? 34'h000000000 : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); - end - else begin : g_oth - assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r - 1 : (PMPNumRegions - 1) - (r - 1)) * 34+:34] : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); - end - genvar b; - for (b = PMPGranularity + 2; b < 34; b = b + 1) begin : g_bitmask - if (b == 2) begin : g_bit0 - assign region_addr_mask[r][b] = csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT; - end - else begin : g_others - assign region_addr_mask[r][b] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT) | ~&csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + ((b - 1) >= (PMPGranularity + 1) ? b - 1 : ((b - 1) + ((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)) - 1)-:((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)]; - end - end - end - endgenerate - localparam [1:0] ibex_pkg_PMP_ACC_EXEC = 2'b00; - localparam [1:0] ibex_pkg_PMP_ACC_READ = 2'b10; - localparam [1:0] ibex_pkg_PMP_ACC_WRITE = 2'b01; - localparam [1:0] ibex_pkg_PMP_MODE_NA4 = 2'b10; - localparam [1:0] ibex_pkg_PMP_MODE_OFF = 2'b00; - localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11; - generate - genvar c; - for (c = 0; c < PMPNumChan; c = c + 1) begin : g_access_check - for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_regions - assign region_match_eq[(c * PMPNumRegions) + r] = (pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] & region_addr_mask[r]) == (region_start_addr[r][33:PMPGranularity + 2] & region_addr_mask[r]); - assign region_match_gt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] > region_start_addr[r][33:PMPGranularity + 2]; - assign region_match_lt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] < csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)]; - always @(*) begin - region_match_all[(c * PMPNumRegions) + r] = 1'b0; - case (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2]) - ibex_pkg_PMP_MODE_OFF: region_match_all[(c * PMPNumRegions) + r] = 1'b0; - ibex_pkg_PMP_MODE_NA4: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; - ibex_pkg_PMP_MODE_NAPOT: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; - ibex_pkg_PMP_MODE_TOR: region_match_all[(c * PMPNumRegions) + r] = (region_match_eq[(c * PMPNumRegions) + r] | region_match_gt[(c * PMPNumRegions) + r]) & region_match_lt[(c * PMPNumRegions) + r]; - default: region_match_all[(c * PMPNumRegions) + r] = 1'b0; - endcase - end - assign region_perm_check[(c * PMPNumRegions) + r] = (((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_EXEC) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 2]) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_WRITE) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 1])) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_READ) & csr_pmp_cfg_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6]); - end - always @(*) begin - access_fault[c] = priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] != ibex_pkg_PRIV_LVL_M; - begin : sv2v_autoblock_1 - reg signed [31:0] r; - for (r = PMPNumRegions - 1; r >= 0; r = r - 1) - if (region_match_all[(c * PMPNumRegions) + r]) - access_fault[c] = (priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PRIV_LVL_M ? csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 5] & ~region_perm_check[(c * PMPNumRegions) + r] : ~region_perm_check[(c * PMPNumRegions) + r]); - end - end - assign pmp_req_err_o[c] = access_fault[c]; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_prefetch_buffer.v b/flow/designs/src/ibex/ibex_prefetch_buffer.v deleted file mode 100644 index c954b108c3..0000000000 --- a/flow/designs/src/ibex/ibex_prefetch_buffer.v +++ /dev/null @@ -1,188 +0,0 @@ -module ibex_prefetch_buffer ( - clk_i, - rst_ni, - req_i, - branch_i, - branch_spec_i, - predicted_branch_i, - branch_mispredict_i, - addr_i, - ready_i, - valid_o, - rdata_o, - addr_o, - err_o, - err_plus2_o, - instr_req_o, - instr_gnt_i, - instr_addr_o, - instr_rdata_i, - instr_err_i, - instr_pmp_err_i, - instr_rvalid_i, - busy_o -); - parameter [0:0] BranchPredictor = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire req_i; - input wire branch_i; - input wire branch_spec_i; - input wire predicted_branch_i; - input wire branch_mispredict_i; - input wire [31:0] addr_i; - input wire ready_i; - output wire valid_o; - output wire [31:0] rdata_o; - output wire [31:0] addr_o; - output wire err_o; - output wire err_plus2_o; - output wire instr_req_o; - input wire instr_gnt_i; - output wire [31:0] instr_addr_o; - input wire [31:0] instr_rdata_i; - input wire instr_err_i; - input wire instr_pmp_err_i; - input wire instr_rvalid_i; - output wire busy_o; - localparam [31:0] NUM_REQS = 2; - wire branch_suppress; - wire valid_new_req; - wire valid_req; - wire valid_req_d; - reg valid_req_q; - wire discard_req_d; - reg discard_req_q; - wire gnt_or_pmp_err; - wire rvalid_or_pmp_err; - wire [NUM_REQS - 1:0] rdata_outstanding_n; - wire [NUM_REQS - 1:0] rdata_outstanding_s; - reg [NUM_REQS - 1:0] rdata_outstanding_q; - wire [NUM_REQS - 1:0] branch_discard_n; - wire [NUM_REQS - 1:0] branch_discard_s; - reg [NUM_REQS - 1:0] branch_discard_q; - wire [NUM_REQS - 1:0] rdata_pmp_err_n; - wire [NUM_REQS - 1:0] rdata_pmp_err_s; - reg [NUM_REQS - 1:0] rdata_pmp_err_q; - wire [NUM_REQS - 1:0] rdata_outstanding_rev; - wire [31:0] stored_addr_d; - reg [31:0] stored_addr_q; - wire stored_addr_en; - wire [31:0] fetch_addr_d; - reg [31:0] fetch_addr_q; - wire fetch_addr_en; - wire [31:0] branch_mispredict_addr; - wire [31:0] instr_addr; - wire [31:0] instr_addr_w_aligned; - wire instr_or_pmp_err; - wire fifo_valid; - wire [31:0] fifo_addr; - wire fifo_ready; - wire fifo_clear; - wire [NUM_REQS - 1:0] fifo_busy; - wire valid_raw; - wire [31:0] addr_next; - wire branch_or_mispredict; - assign busy_o = |rdata_outstanding_q | instr_req_o; - assign branch_or_mispredict = branch_i | branch_mispredict_i; - assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0]; - assign fifo_clear = branch_or_mispredict; - generate - genvar i; - for (i = 0; i < NUM_REQS; i = i + 1) begin : gen_rd_rev - assign rdata_outstanding_rev[i] = rdata_outstanding_q[(NUM_REQS - 1) - i]; - end - endgenerate - assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev); - ibex_fetch_fifo #(.NUM_REQS(NUM_REQS)) fifo_i( - .clk_i(clk_i), - .rst_ni(rst_ni), - .clear_i(fifo_clear), - .busy_o(fifo_busy), - .in_valid_i(fifo_valid), - .in_addr_i(fifo_addr), - .in_rdata_i(instr_rdata_i), - .in_err_i(instr_or_pmp_err), - .out_valid_o(valid_raw), - .out_ready_i(ready_i), - .out_rdata_o(rdata_o), - .out_addr_o(addr_o), - .out_addr_next_o(addr_next), - .out_err_o(err_o), - .out_err_plus2_o(err_plus2_o) - ); - assign branch_suppress = branch_spec_i & ~branch_i; - assign valid_new_req = ((~branch_suppress & req_i) & (fifo_ready | branch_or_mispredict)) & ~rdata_outstanding_q[NUM_REQS - 1]; - assign valid_req = valid_req_q | valid_new_req; - assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; - assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]); - assign valid_req_d = valid_req & ~gnt_or_pmp_err; - assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q); - assign stored_addr_en = (valid_new_req & ~valid_req_q) & ~gnt_or_pmp_err; - assign stored_addr_d = instr_addr; - always @(posedge clk_i) - if (stored_addr_en) - stored_addr_q <= stored_addr_d; - generate - if (BranchPredictor) begin : g_branch_predictor - reg [31:0] branch_mispredict_addr_q; - wire branch_mispredict_addr_en; - assign branch_mispredict_addr_en = branch_i & predicted_branch_i; - always @(posedge clk_i) - if (branch_mispredict_addr_en) - branch_mispredict_addr_q <= addr_next; - assign branch_mispredict_addr = branch_mispredict_addr_q; - end - else begin : g_no_branch_predictor - wire unused_predicted_branch; - wire [31:0] unused_addr_next; - assign unused_predicted_branch = predicted_branch_i; - assign unused_addr_next = addr_next; - assign branch_mispredict_addr = {32 {1'sb0}}; - end - endgenerate - assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q); - assign fetch_addr_d = (branch_i ? addr_i : (branch_mispredict_i ? {branch_mispredict_addr[31:2], 2'b00} : {fetch_addr_q[31:2], 2'b00})) + {{29 {1'b0}}, valid_new_req & ~valid_req_q, 2'b00}; - always @(posedge clk_i) - if (fetch_addr_en) - fetch_addr_q <= fetch_addr_d; - assign instr_addr = (valid_req_q ? stored_addr_q : (branch_spec_i ? addr_i : (branch_mispredict_i ? branch_mispredict_addr : fetch_addr_q))); - assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00}; - generate - for (i = 0; i < NUM_REQS; i = i + 1) begin : g_outstanding_reqs - if (i == 0) begin : g_req0 - assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | rdata_outstanding_q[i]; - assign branch_discard_n[i] = (((valid_req & gnt_or_pmp_err) & discard_req_d) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; - assign rdata_pmp_err_n[i] = ((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) | rdata_pmp_err_q[i]; - end - else begin : g_reqtop - assign rdata_outstanding_n[i] = ((valid_req & gnt_or_pmp_err) & rdata_outstanding_q[i - 1]) | rdata_outstanding_q[i]; - assign branch_discard_n[i] = ((((valid_req & gnt_or_pmp_err) & discard_req_d) & rdata_outstanding_q[i - 1]) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; - assign rdata_pmp_err_n[i] = (((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) & rdata_outstanding_q[i - 1]) | rdata_pmp_err_q[i]; - end - end - endgenerate - assign rdata_outstanding_s = (rvalid_or_pmp_err ? {1'b0, rdata_outstanding_n[NUM_REQS - 1:1]} : rdata_outstanding_n); - assign branch_discard_s = (rvalid_or_pmp_err ? {1'b0, branch_discard_n[NUM_REQS - 1:1]} : branch_discard_n); - assign rdata_pmp_err_s = (rvalid_or_pmp_err ? {1'b0, rdata_pmp_err_n[NUM_REQS - 1:1]} : rdata_pmp_err_n); - assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0]; - assign fifo_addr = (branch_mispredict_i ? branch_mispredict_addr : addr_i); - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - valid_req_q <= 1'b0; - discard_req_q <= 1'b0; - rdata_outstanding_q <= 'b0; - branch_discard_q <= 'b0; - rdata_pmp_err_q <= 'b0; - end - else begin - valid_req_q <= valid_req_d; - discard_req_q <= discard_req_d; - rdata_outstanding_q <= rdata_outstanding_s; - branch_discard_q <= branch_discard_s; - rdata_pmp_err_q <= rdata_pmp_err_s; - end - assign instr_req_o = valid_req; - assign instr_addr_o = instr_addr_w_aligned; - assign valid_o = valid_raw & ~branch_mispredict_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_ff.v b/flow/designs/src/ibex/ibex_register_file_ff.v deleted file mode 100644 index d70dad1e53..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_ff.v +++ /dev/null @@ -1,77 +0,0 @@ -module ibex_register_file_ff ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - wire [(NUM_WORDS * DataWidth) - 1:0] rf_reg; - reg [((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) * DataWidth) + (DataWidth - 1) : ((3 - NUM_WORDS) * DataWidth) + (((NUM_WORDS - 1) * DataWidth) - 1)):((NUM_WORDS - 1) >= 1 ? DataWidth : (NUM_WORDS - 1) * DataWidth)] rf_reg_q; - reg [NUM_WORDS - 1:1] we_a_dec; - function automatic [4:0] sv2v_cast_5; - input reg [4:0] inp; - sv2v_cast_5 = inp; - endfunction - always @(*) begin : we_a_decoder - begin : sv2v_autoblock_2 - reg [31:0] i; - for (i = 1; i < NUM_WORDS; i = i + 1) - we_a_dec[i] = (waddr_a_i == sv2v_cast_5(i) ? we_a_i : 1'b0); - end - end - generate - genvar i; - for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_flops - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= {DataWidth {1'sb0}}; - else if (we_a_dec[i]) - rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= wdata_a_i; - end - endgenerate - generate - if (DummyInstructions) begin : g_dummy_r0 - wire we_r0_dummy; - reg [DataWidth - 1:0] rf_r0_q; - assign we_r0_dummy = we_a_i & dummy_instr_id_i; - always @(posedge clk_i or negedge rst_ni) - if (!rst_ni) - rf_r0_q <= {DataWidth {1'sb0}}; - else if (we_r0_dummy) - rf_r0_q <= wdata_a_i; - assign rf_reg[0+:DataWidth] = (dummy_instr_id_i ? rf_r0_q : {DataWidth {1'sb0}}); - end - else begin : g_normal_r0 - wire unused_dummy_instr_id; - assign unused_dummy_instr_id = dummy_instr_id_i; - assign rf_reg[0+:DataWidth] = {DataWidth {1'sb0}}; - end - endgenerate - assign rf_reg[DataWidth * (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)] = rf_reg_q[DataWidth * ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) : 1 - (((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) - (NUM_WORDS - 1)))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)]; - assign rdata_a_o = rf_reg[raddr_a_i * DataWidth+:DataWidth]; - assign rdata_b_o = rf_reg[raddr_b_i * DataWidth+:DataWidth]; - wire unused_test_en; - assign unused_test_en = test_en_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_fpga.v b/flow/designs/src/ibex/ibex_register_file_fpga.v deleted file mode 100644 index a249fcfb4e..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_fpga.v +++ /dev/null @@ -1,45 +0,0 @@ -module ibex_register_file_fpga ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1]; - wire we; - assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]); - assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]); - assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i); - always @(posedge clk_i) begin : sync_write - if (we == 1'b1) - mem[waddr_a_i] <= wdata_a_i; - end - wire unused_rst_ni; - assign unused_rst_ni = rst_ni; - wire unused_dummy_instr; - assign unused_dummy_instr = dummy_instr_id_i; - wire unused_test_en; - assign unused_test_en = test_en_i; -endmodule diff --git a/flow/designs/src/ibex/ibex_register_file_latch.v b/flow/designs/src/ibex/ibex_register_file_latch.v deleted file mode 100644 index c9a02bfcb8..0000000000 --- a/flow/designs/src/ibex/ibex_register_file_latch.v +++ /dev/null @@ -1,118 +0,0 @@ -module ibex_register_file_latch ( - clk_i, - rst_ni, - test_en_i, - dummy_instr_id_i, - raddr_a_i, - rdata_a_o, - raddr_b_i, - rdata_b_o, - waddr_a_i, - wdata_a_i, - we_a_i -); - parameter [0:0] RV32E = 0; - parameter [31:0] DataWidth = 32; - parameter [0:0] DummyInstructions = 0; - input wire clk_i; - input wire rst_ni; - input wire test_en_i; - input wire dummy_instr_id_i; - input wire [4:0] raddr_a_i; - output wire [DataWidth - 1:0] rdata_a_o; - input wire [4:0] raddr_b_i; - output wire [DataWidth - 1:0] rdata_b_o; - input wire [4:0] waddr_a_i; - input wire [DataWidth - 1:0] wdata_a_i; - input wire we_a_i; - localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); - localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; - reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1]; - reg [NUM_WORDS - 1:1] waddr_onehot_a; - wire [NUM_WORDS - 1:1] mem_clocks; - reg [DataWidth - 1:0] wdata_a_q; - wire [ADDR_WIDTH - 1:0] raddr_a_int; - wire [ADDR_WIDTH - 1:0] raddr_b_int; - wire [ADDR_WIDTH - 1:0] waddr_a_int; - assign raddr_a_int = raddr_a_i[ADDR_WIDTH - 1:0]; - assign raddr_b_int = raddr_b_i[ADDR_WIDTH - 1:0]; - assign waddr_a_int = waddr_a_i[ADDR_WIDTH - 1:0]; - wire clk_int; - assign rdata_a_o = mem[raddr_a_int]; - assign rdata_b_o = mem[raddr_b_int]; - prim_clock_gating cg_we_global( - .clk_i(clk_i), - .en_i(we_a_i), - .test_en_i(test_en_i), - .clk_o(clk_int) - ); - always @(posedge clk_int or negedge rst_ni) begin : sample_wdata - if (!rst_ni) - wdata_a_q <= {DataWidth {1'sb0}}; - else if (we_a_i) - wdata_a_q <= wdata_a_i; - end - function automatic signed [4:0] sv2v_cast_5_signed; - input reg signed [4:0] inp; - sv2v_cast_5_signed = inp; - endfunction - always @(*) begin : wad - begin : sv2v_autoblock_5 - reg signed [31:0] i; - for (i = 1; i < NUM_WORDS; i = i + 1) - begin : wad_word_iter - if (we_a_i && (waddr_a_int == sv2v_cast_5_signed(i))) - waddr_onehot_a[i] = 1'b1; - else - waddr_onehot_a[i] = 1'b0; - end - end - end - generate - genvar x; - for (x = 1; x < NUM_WORDS; x = x + 1) begin : gen_cg_word_iter - prim_clock_gating cg_i( - .clk_i(clk_int), - .en_i(waddr_onehot_a[x]), - .test_en_i(test_en_i), - .clk_o(mem_clocks[x]) - ); - end - endgenerate - generate - genvar i; - for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_latches - always @(*) - if (mem_clocks[i]) - mem[i] = wdata_a_q; - end - endgenerate - generate - if (DummyInstructions) begin : g_dummy_r0 - wire we_r0_dummy; - wire r0_clock; - reg [DataWidth - 1:0] mem_r0; - assign we_r0_dummy = we_a_i & dummy_instr_id_i; - prim_clock_gating cg_i( - .clk_i(clk_int), - .en_i(we_r0_dummy), - .test_en_i(test_en_i), - .clk_o(r0_clock) - ); - always @(*) begin : latch_wdata - if (r0_clock) - mem_r0 = wdata_a_q; - end - wire [(DataWidth >= DataWidth ? DataWidth : DataWidth):1] sv2v_tmp_22903; - assign sv2v_tmp_22903 = (dummy_instr_id_i ? mem_r0 : {DataWidth {1'sb0}}); - always @(*) mem[0] = sv2v_tmp_22903; - end - else begin : g_normal_r0 - wire unused_dummy_instr_id; - assign unused_dummy_instr_id = dummy_instr_id_i; - wire [DataWidth:1] sv2v_tmp_F0978; - assign sv2v_tmp_F0978 = {DataWidth {1'sb0}}; - always @(*) mem[0] = sv2v_tmp_F0978; - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/ibex_wb_stage.v b/flow/designs/src/ibex/ibex_wb_stage.v deleted file mode 100644 index f92c4e93cc..0000000000 --- a/flow/designs/src/ibex/ibex_wb_stage.v +++ /dev/null @@ -1,130 +0,0 @@ -module ibex_wb_stage ( - clk_i, - rst_ni, - en_wb_i, - instr_type_wb_i, - pc_id_i, - instr_is_compressed_id_i, - instr_perf_count_id_i, - ready_wb_o, - rf_write_wb_o, - outstanding_load_wb_o, - outstanding_store_wb_o, - pc_wb_o, - perf_instr_ret_wb_o, - perf_instr_ret_compressed_wb_o, - rf_waddr_id_i, - rf_wdata_id_i, - rf_we_id_i, - rf_wdata_lsu_i, - rf_we_lsu_i, - rf_wdata_fwd_wb_o, - rf_waddr_wb_o, - rf_wdata_wb_o, - rf_we_wb_o, - lsu_resp_valid_i, - lsu_resp_err_i, - instr_done_wb_o -); - parameter [0:0] WritebackStage = 1'b0; - input wire clk_i; - input wire rst_ni; - input wire en_wb_i; - input wire [1:0] instr_type_wb_i; - input wire [31:0] pc_id_i; - input wire instr_is_compressed_id_i; - input wire instr_perf_count_id_i; - output wire ready_wb_o; - output wire rf_write_wb_o; - output wire outstanding_load_wb_o; - output wire outstanding_store_wb_o; - output wire [31:0] pc_wb_o; - output wire perf_instr_ret_wb_o; - output wire perf_instr_ret_compressed_wb_o; - input wire [4:0] rf_waddr_id_i; - input wire [31:0] rf_wdata_id_i; - input wire rf_we_id_i; - input wire [31:0] rf_wdata_lsu_i; - input wire rf_we_lsu_i; - output wire [31:0] rf_wdata_fwd_wb_o; - output wire [4:0] rf_waddr_wb_o; - output wire [31:0] rf_wdata_wb_o; - output wire rf_we_wb_o; - input wire lsu_resp_valid_i; - input wire lsu_resp_err_i; - output wire instr_done_wb_o; - wire [31:0] rf_wdata_wb_mux [0:1]; - wire [1:0] rf_wdata_wb_mux_we; - localparam [1:0] ibex_pkg_WB_INSTR_LOAD = 0; - localparam [1:0] ibex_pkg_WB_INSTR_OTHER = 2; - localparam [1:0] ibex_pkg_WB_INSTR_STORE = 1; - generate - if (WritebackStage) begin : g_writeback_stage - reg [31:0] rf_wdata_wb_q; - reg rf_we_wb_q; - reg [4:0] rf_waddr_wb_q; - wire wb_done; - reg wb_valid_q; - reg [31:0] wb_pc_q; - reg wb_compressed_q; - reg wb_count_q; - reg [1:0] wb_instr_type_q; - wire wb_valid_d; - assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done); - assign wb_done = (wb_instr_type_q == ibex_pkg_WB_INSTR_OTHER) | lsu_resp_valid_i; - always @(posedge clk_i or negedge rst_ni) - if (~rst_ni) - wb_valid_q <= 1'b0; - else - wb_valid_q <= wb_valid_d; - always @(posedge clk_i) - if (en_wb_i) begin - rf_we_wb_q <= rf_we_id_i; - rf_waddr_wb_q <= rf_waddr_id_i; - rf_wdata_wb_q <= rf_wdata_id_i; - wb_instr_type_q <= instr_type_wb_i; - wb_pc_q <= pc_id_i; - wb_compressed_q <= instr_is_compressed_id_i; - wb_count_q <= instr_perf_count_id_i; - end - assign rf_waddr_wb_o = rf_waddr_wb_q; - assign rf_wdata_wb_mux[0] = rf_wdata_wb_q; - assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q; - assign ready_wb_o = ~wb_valid_q | wb_done; - assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD)); - assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD); - assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_STORE); - assign pc_wb_o = wb_pc_q; - assign instr_done_wb_o = wb_valid_q & wb_done; - assign perf_instr_ret_wb_o = (instr_done_wb_o & wb_count_q) & ~(lsu_resp_valid_i & lsu_resp_err_i); - assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q; - assign rf_wdata_fwd_wb_o = rf_wdata_wb_q; - end - else begin : g_bypass_wb - assign rf_waddr_wb_o = rf_waddr_id_i; - assign rf_wdata_wb_mux[0] = rf_wdata_id_i; - assign rf_wdata_wb_mux_we[0] = rf_we_id_i; - assign perf_instr_ret_wb_o = (instr_perf_count_id_i & en_wb_i) & ~(lsu_resp_valid_i & lsu_resp_err_i); - assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i; - assign ready_wb_o = 1'b1; - wire unused_clk; - wire unused_rst; - wire [1:0] unused_instr_type_wb; - wire [31:0] unused_pc_id; - assign unused_clk = clk_i; - assign unused_rst = rst_ni; - assign unused_instr_type_wb = instr_type_wb_i; - assign unused_pc_id = pc_id_i; - assign outstanding_load_wb_o = 1'b0; - assign outstanding_store_wb_o = 1'b0; - assign pc_wb_o = {32 {1'sb0}}; - assign rf_write_wb_o = 1'b0; - assign rf_wdata_fwd_wb_o = 32'b00000000000000000000000000000000; - assign instr_done_wb_o = 1'b0; - end - endgenerate - assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i; - assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i; - assign rf_wdata_wb_o = (rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]); - assign rf_we_wb_o = |rf_wdata_wb_mux_we; -endmodule diff --git a/flow/designs/src/ibex/prim_badbit_ram_1p.v b/flow/designs/src/ibex/prim_badbit_ram_1p.v deleted file mode 100644 index 1099bd11eb..0000000000 --- a/flow/designs/src/ibex/prim_badbit_ram_1p.v +++ /dev/null @@ -1,51 +0,0 @@ -module prim_badbit_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output wire [Width - 1:0] rdata_o; - wire [Width - 1:0] sram_rdata; - prim_generic_ram_1p #( - .Width(Width), - .Depth(Depth), - .DataBitsPerMask(DataBitsPerMask), - .MemInitFile(MemInitFile) - ) u_mem( - .clk_i(clk_i), - .req_i(req_i), - .write_i(write_i), - .addr_i(addr_i), - .wdata_i(wdata_i), - .wmask_i(wmask_i), - .rdata_o(sram_rdata) - ); - wire [31:0] width; - assign width = Width; - wire [31:0] addr; - wire [127:0] wdata; - wire [127:0] wmask; - wire [127:0] rdata; - assign addr = {{32 - Aw {1'b0}}, addr_i}; - assign wdata = {{128 - Width {1'b0}}, wdata_i}; - assign wmask = {{128 - Width {1'b0}}, wmask_i}; - assign rdata = {{128 - Width {1'b0}}, sram_rdata}; - wor [127:0] bad_bit_mask; - assign bad_bit_mask = 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - assign rdata_o = sram_rdata ^ bad_bit_mask; -endmodule diff --git a/flow/designs/src/ibex/prim_generic_clock_gating.v b/flow/designs/src/ibex/prim_generic_clock_gating.v deleted file mode 100644 index c88af55ee6..0000000000 --- a/flow/designs/src/ibex/prim_generic_clock_gating.v +++ /dev/null @@ -1,16 +0,0 @@ -module prim_generic_clock_gating ( - clk_i, - en_i, - test_en_i, - clk_o -); - input clk_i; - input en_i; - input test_en_i; - output wire clk_o; - reg en_latch; - always @(*) - if (!clk_i) - en_latch = en_i | test_en_i; - assign clk_o = en_latch & clk_i; -endmodule diff --git a/flow/designs/src/ibex/prim_generic_ram_1p.v b/flow/designs/src/ibex/prim_generic_ram_1p.v deleted file mode 100644 index 3278371897..0000000000 --- a/flow/designs/src/ibex/prim_generic_ram_1p.v +++ /dev/null @@ -1,46 +0,0 @@ -module prim_generic_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output reg [Width - 1:0] rdata_o; - localparam signed [31:0] MaskWidth = Width / DataBitsPerMask; - reg [Width - 1:0] mem [0:Depth - 1]; - wire [MaskWidth - 1:0] wmask; - generate - genvar k; - for (k = 0; k < MaskWidth; k = k + 1) begin : gen_wmask - assign wmask[k] = &wmask_i[k * DataBitsPerMask+:DataBitsPerMask]; - end - endgenerate - always @(posedge clk_i) - if (req_i) - if (write_i) begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < MaskWidth; i = i + 1) - if (wmask[i]) - mem[addr_i][i * DataBitsPerMask+:DataBitsPerMask] <= wdata_i[i * DataBitsPerMask+:DataBitsPerMask]; - end - else - rdata_o <= mem[addr_i]; - initial if (MemInitFile != "") begin : gen_meminit - $display("Initializing memory %m from file '%s'.", MemInitFile); - $readmemh(MemInitFile, mem); - end -endmodule diff --git a/flow/designs/src/ibex/prim_lfsr.v b/flow/designs/src/ibex/prim_lfsr.v deleted file mode 100644 index c4a5912331..0000000000 --- a/flow/designs/src/ibex/prim_lfsr.v +++ /dev/null @@ -1,88 +0,0 @@ -module prim_lfsr ( - clk_i, - rst_ni, - seed_en_i, - seed_i, - lfsr_en_i, - entropy_i, - state_o -); - parameter _sv2v_width_LfsrType = 56; - parameter [_sv2v_width_LfsrType - 1:0] LfsrType = "GAL_XOR"; - parameter [31:0] LfsrDw = 32; - parameter [31:0] EntropyDw = 8; - parameter [31:0] StateOutDw = 8; - function automatic signed [LfsrDw - 1:0] sv2v_cast_FFBD2_signed; - input reg signed [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2_signed = inp; - endfunction - parameter [LfsrDw - 1:0] DefaultSeed = sv2v_cast_FFBD2_signed(1); - parameter [LfsrDw - 1:0] CustomCoeffs = 1'sb0; - parameter [0:0] MaxLenSVA = 1'b1; - parameter [0:0] LockupSVA = 1'b1; - parameter [0:0] ExtSeedSVA = 1'b1; - input clk_i; - input rst_ni; - input seed_en_i; - input [LfsrDw - 1:0] seed_i; - input lfsr_en_i; - input [EntropyDw - 1:0] entropy_i; - output wire [StateOutDw - 1:0] state_o; - localparam [31:0] GAL_XOR_LUT_OFF = 4; - localparam [3903:0] GAL_XOR_COEFFS = {64'h0000000000000009, 64'h0000000000000012, 64'h0000000000000021, 64'h0000000000000041, 64'h000000000000008e, 64'h0000000000000108, 64'h0000000000000204, 64'h0000000000000402, 64'h0000000000000829, 64'h000000000000100d, 64'h0000000000002015, 64'h0000000000004001, 64'h0000000000008016, 64'h0000000000010004, 64'h0000000000020013, 64'h0000000000040013, 64'h0000000000080004, 64'h0000000000100002, 64'h0000000000200001, 64'h0000000000400010, 64'h000000000080000d, 64'h0000000001000004, 64'h0000000002000023, 64'h0000000004000013, 64'h0000000008000004, 64'h0000000010000002, 64'h0000000020000029, 64'h0000000040000004, 64'h0000000080000057, 64'h0000000100000029, 64'h0000000200000073, 64'h0000000400000002, 64'h000000080000003b, 64'h000000100000001f, 64'h0000002000000031, 64'h0000004000000008, 64'h000000800000001c, 64'h0000010000000004, 64'h000002000000001f, 64'h000004000000002c, 64'h0000080000000032, 64'h000010000000000d, 64'h0000200000000097, 64'h0000400000000010, 64'h000080000000005b, 64'h0001000000000038, 64'h000200000000000e, 64'h0004000000000025, 64'h0008000000000004, 64'h0010000000000023, 64'h002000000000003e, 64'h0040000000000023, 64'h008000000000004a, 64'h0100000000000016, 64'h0200000000000031, 64'h040000000000003d, 64'h0800000000000001, 64'h1000000000000013, 64'h2000000000000034, 64'h4000000000000001, 64'h800000000000000d}; - localparam [31:0] FIB_XNOR_LUT_OFF = 3; - localparam [27887:0] FIB_XNOR_COEFFS = {168'h000000000000000000000000000000000000000006, 168'h00000000000000000000000000000000000000000c, 168'h000000000000000000000000000000000000000014, 168'h000000000000000000000000000000000000000030, 168'h000000000000000000000000000000000000000060, 168'h0000000000000000000000000000000000000000b8, 168'h000000000000000000000000000000000000000110, 168'h000000000000000000000000000000000000000240, 168'h000000000000000000000000000000000000000500, 168'h000000000000000000000000000000000000000829, 168'h00000000000000000000000000000000000000100d, 168'h000000000000000000000000000000000000002015, 168'h000000000000000000000000000000000000006000, 168'h00000000000000000000000000000000000000d008, 168'h000000000000000000000000000000000000012000, 168'h000000000000000000000000000000000000020400, 168'h000000000000000000000000000000000000040023, 168'h000000000000000000000000000000000000090000, 168'h000000000000000000000000000000000000140000, 168'h000000000000000000000000000000000000300000, 168'h000000000000000000000000000000000000420000, 168'h000000000000000000000000000000000000e10000, 168'h000000000000000000000000000000000001200000, 168'h000000000000000000000000000000000002000023, 168'h000000000000000000000000000000000004000013, 168'h000000000000000000000000000000000009000000, 168'h000000000000000000000000000000000014000000, 168'h000000000000000000000000000000000020000029, 168'h000000000000000000000000000000000048000000, 168'h000000000000000000000000000000000080200003, 168'h000000000000000000000000000000000100080000, 168'h000000000000000000000000000000000204000003, 168'h000000000000000000000000000000000500000000, 168'h000000000000000000000000000000000801000000, 168'h00000000000000000000000000000000100000001f, 168'h000000000000000000000000000000002000000031, 168'h000000000000000000000000000000004400000000, 168'h00000000000000000000000000000000a000140000, 168'h000000000000000000000000000000012000000000, 168'h0000000000000000000000000000000300000c0000, 168'h000000000000000000000000000000063000000000, 168'h0000000000000000000000000000000c0000030000, 168'h0000000000000000000000000000001b0000000000, 168'h000000000000000000000000000000300003000000, 168'h000000000000000000000000000000420000000000, 168'h000000000000000000000000000000c00000180000, 168'h000000000000000000000000000001008000000000, 168'h000000000000000000000000000003000000c00000, 168'h000000000000000000000000000006000c00000000, 168'h000000000000000000000000000009000000000000, 168'h000000000000000000000000000018003000000000, 168'h000000000000000000000000000030000000030000, 168'h000000000000000000000000000040000040000000, 168'h0000000000000000000000000000c0000600000000, 168'h000000000000000000000000000102000000000000, 168'h000000000000000000000000000200004000000000, 168'h000000000000000000000000000600003000000000, 168'h000000000000000000000000000c00000000000000, 168'h000000000000000000000000001800300000000000, 168'h000000000000000000000000003000000000000030, 168'h000000000000000000000000006000000000000000, 168'h00000000000000000000000000d800000000000000, 168'h000000000000000000000000010000400000000000, 168'h000000000000000000000000030180000000000000, 168'h000000000000000000000000060300000000000000, 168'h000000000000000000000000080400000000000000, 168'h000000000000000000000000140000028000000000, 168'h000000000000000000000000300060000000000000, 168'h000000000000000000000000410000000000000000, 168'h000000000000000000000000820000000001040000, 168'h000000000000000000000001000000800000000000, 168'h000000000000000000000003000600000000000000, 168'h000000000000000000000006018000000000000000, 168'h00000000000000000000000c000000018000000000, 168'h000000000000000000000018000000600000000000, 168'h000000000000000000000030000600000000000000, 168'h000000000000000000000040200000000000000000, 168'h0000000000000000000000c0000000060000000000, 168'h000000000000000000000110000000000000000000, 168'h000000000000000000000240000000480000000000, 168'h000000000000000000000600000000003000000000, 168'h000000000000000000000800400000000000000000, 168'h000000000000000000001800000300000000000000, 168'h000000000000000000003003000000000000000000, 168'h000000000000000000004002000000000000000000, 168'h00000000000000000000c000000000000000018000, 168'h000000000000000000010000000004000000000000, 168'h000000000000000000030000c00000000000000000, 168'h0000000000000000000600000000000000000000c0, 168'h0000000000000000000c00c0000000000000000000, 168'h000000000000000000140000000000000000000000, 168'h000000000000000000200001000000000000000000, 168'h000000000000000000400800000000000000000000, 168'h000000000000000000a00000000001400000000000, 168'h000000000000000001040000000000000000000000, 168'h000000000000000002004000000000000000000000, 168'h000000000000000005000000000028000000000000, 168'h000000000000000008000000004000000000000000, 168'h000000000000000018600000000000000000000000, 168'h000000000000000030000000000000000c00000000, 168'h000000000000000040200000000000000000000000, 168'h0000000000000000c0300000000000000000000000, 168'h000000000000000100010000000000000000000000, 168'h000000000000000200040000000000000000000000, 168'h0000000000000005000000000000000a0000000000, 168'h000000000000000800000010000000000000000000, 168'h000000000000001860000000000000000000000000, 168'h000000000000003003000000000000000000000000, 168'h000000000000004010000000000000000000000000, 168'h00000000000000a000000000140000000000000000, 168'h000000000000010080000000000000000000000000, 168'h000000000000030000000000000000000180000000, 168'h000000000000060018000000000000000000000000, 168'h0000000000000c0000000000000000300000000000, 168'h000000000000140005000000000000000000000000, 168'h000000000000200000001000000000000000000000, 168'h000000000000404000000000000000000000000000, 168'h000000000000810000000000000000000000000102, 168'h000000000001000040000000000000000000000000, 168'h000000000003000000000000006000000000000000, 168'h000000000005000000000000000000000000000000, 168'h000000000008000000004000000000000000000000, 168'h000000000018000000000000000000000000030000, 168'h000000000030000000030000000000000000000000, 168'h000000000060000000000000000000000000000000, 168'h0000000000a0000014000000000000000000000000, 168'h000000000108000000000000000000000000000000, 168'h000000000240000000000000000000000000000000, 168'h000000000600000000000c00000000000000000000, 168'h000000000800000040000000000000000000000000, 168'h000000001800000000000300000000000000000000, 168'h000000002000000000000010000000000000000000, 168'h000000004008000000000000000000000000000000, 168'h00000000c000000000000000000000000000000600, 168'h000000010000080000000000000000000000000000, 168'h000000030600000000000000000000000000000000, 168'h00000004a400000000000000000000000000000000, 168'h000000080000004000000000000000000000000000, 168'h000000180000003000000000000000000000000000, 168'h000000200001000000000000000000000000000000, 168'h000000600006000000000000000000000000000000, 168'h000000c00000000000000006000000000000000000, 168'h000001000000000000100000000000000000000000, 168'h000003000000000000006000000000000000000000, 168'h000006000000003000000000000000000000000000, 168'h000008000001000000000000000000000000000000, 168'h00001800000000000000000000000000c000000000, 168'h000020000000000001000000000000000000000000, 168'h000048000000000000000000000000000000000000, 168'h0000c0000000000000006000000000000000000000, 168'h000180000000000000000000000000000000000000, 168'h000280000000000000000000000000000005000000, 168'h00060000000c000000000000000000000000000000, 168'h000c00000000000000000000000000018000000000, 168'h001800000600000000000000000000000000000000, 168'h003000000c00000000000000000000000000000000, 168'h004000000080000000000000000000000000000000, 168'h00c000300000000000000000000000000000000000, 168'h010000400000000000000000000000000000000000, 168'h030000000000000000000006000000000000000000, 168'h0600000000000000c0000000000000000000000000, 168'h0c0060000000000000000000000000000000000000, 168'h180000006000000000000000000000000000000000, 168'h3000000000c0000000000000000000000000000000, 168'h410000000000000000000000000000000000000000, 168'ha00140000000000000000000000000000000000000}; - wire lockup; - wire [LfsrDw - 1:0] lfsr_d; - reg [LfsrDw - 1:0] lfsr_q; - wire [LfsrDw - 1:0] next_lfsr_state; - wire [LfsrDw - 1:0] coeffs; - generate - function automatic [63:0] sv2v_cast_64; - input reg [63:0] inp; - sv2v_cast_64 = inp; - endfunction - if (sv2v_cast_64(LfsrType) == sv2v_cast_64("GAL_XOR")) begin : gen_gal_xor - if (CustomCoeffs > 0) begin : gen_custom - assign coeffs = CustomCoeffs[LfsrDw - 1:0]; - end - else begin : gen_lut - assign coeffs = GAL_XOR_COEFFS[((60 - (LfsrDw - GAL_XOR_LUT_OFF)) * 64) + (LfsrDw - 1)-:LfsrDw]; - end - function automatic [LfsrDw - 1:0] sv2v_cast_FFBD2; - input reg [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2 = inp; - endfunction - assign next_lfsr_state = (sv2v_cast_FFBD2(entropy_i) ^ ({LfsrDw {lfsr_q[0]}} & coeffs)) ^ (lfsr_q >> 1); - assign lockup = ~(|lfsr_q); - end - else begin - function automatic [63:0] sv2v_cast_64; - input reg [63:0] inp; - sv2v_cast_64 = inp; - endfunction - if (sv2v_cast_64(LfsrType) == "FIB_XNOR") begin : gen_fib_xnor - if (CustomCoeffs > 0) begin : gen_custom - assign coeffs = CustomCoeffs[LfsrDw - 1:0]; - end - else begin : gen_lut - assign coeffs = FIB_XNOR_COEFFS[((165 - (LfsrDw - FIB_XNOR_LUT_OFF)) * 168) + (LfsrDw - 1)-:LfsrDw]; - end - function automatic [LfsrDw - 1:0] sv2v_cast_FFBD2; - input reg [LfsrDw - 1:0] inp; - sv2v_cast_FFBD2 = inp; - endfunction - assign next_lfsr_state = sv2v_cast_FFBD2(entropy_i) ^ {lfsr_q[LfsrDw - 2:0], ~(^(lfsr_q & coeffs))}; - assign lockup = &lfsr_q; - end - end - endgenerate - assign lfsr_d = (seed_en_i ? seed_i : (lfsr_en_i && lockup ? DefaultSeed : (lfsr_en_i ? next_lfsr_state : lfsr_q))); - assign state_o = lfsr_q[StateOutDw - 1:0]; - always @(posedge clk_i or negedge rst_ni) begin : p_reg - if (!rst_ni) - lfsr_q <= DefaultSeed; - else - lfsr_q <= lfsr_d; - end -endmodule diff --git a/flow/designs/src/ibex/prim_ram_1p.v b/flow/designs/src/ibex/prim_ram_1p.v deleted file mode 100644 index 93f789f42a..0000000000 --- a/flow/designs/src/ibex/prim_ram_1p.v +++ /dev/null @@ -1,44 +0,0 @@ -module prim_ram_1p ( - clk_i, - req_i, - write_i, - addr_i, - wdata_i, - wmask_i, - rdata_o -); - parameter signed [31:0] Width = 32; - parameter signed [31:0] Depth = 128; - parameter signed [31:0] DataBitsPerMask = 1; - parameter _sv2v_width_MemInitFile = 1; - parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = ""; - localparam signed [31:0] Aw = $clog2(Depth); - input wire clk_i; - input wire req_i; - input wire write_i; - input wire [Aw - 1:0] addr_i; - input wire [Width - 1:0] wdata_i; - input wire [Width - 1:0] wmask_i; - output wire [Width - 1:0] rdata_o; - localparam integer prim_pkg_ImplGeneric = 0; - parameter integer Impl = prim_pkg_ImplGeneric; - localparam integer prim_pkg_ImplBadbit = 2; - generate - if (Impl == prim_pkg_ImplBadbit) begin : gen_badbit - prim_badbit_ram_1p #( - .Depth(Depth), - .Width(Width), - .MemInitFile(MemInitFile), - .DataBitsPerMask(DataBitsPerMask) - ) u_impl_badbit(.*); - end - else begin : gen_generic - prim_generic_ram_1p #( - .Depth(Depth), - .Width(Width), - .MemInitFile(MemInitFile), - .DataBitsPerMask(DataBitsPerMask) - ) u_impl_generic(.*); - end - endgenerate -endmodule diff --git a/flow/designs/src/ibex/prim_secded_28_22_dec.v b/flow/designs/src/ibex/prim_secded_28_22_dec.v deleted file mode 100644 index 40753d1e8b..0000000000 --- a/flow/designs/src/ibex/prim_secded_28_22_dec.v +++ /dev/null @@ -1,43 +0,0 @@ -module prim_secded_28_22_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [27:0] in; - output wire [21:0] d_o; - output wire [5:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = (((((((((((in[22] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[20]) ^ in[21]; - assign syndrome_o[1] = (((((((((((in[23] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[20]) ^ in[21]; - assign syndrome_o[2] = ((((((((((in[24] ^ in[0]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[20]; - assign syndrome_o[3] = ((((((((((in[25] ^ in[1]) ^ in[4]) ^ in[7]) ^ in[8]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[17]) ^ in[19]) ^ in[21]; - assign syndrome_o[4] = (((((((((((in[26] ^ in[2]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[11]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign syndrome_o[5] = (((((((((((in[27] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[9]) ^ in[12]) ^ in[14]) ^ in[15]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign d_o[0] = (syndrome_o == 6'h07) ^ in[0]; - assign d_o[1] = (syndrome_o == 6'h0b) ^ in[1]; - assign d_o[2] = (syndrome_o == 6'h13) ^ in[2]; - assign d_o[3] = (syndrome_o == 6'h23) ^ in[3]; - assign d_o[4] = (syndrome_o == 6'h0d) ^ in[4]; - assign d_o[5] = (syndrome_o == 6'h15) ^ in[5]; - assign d_o[6] = (syndrome_o == 6'h25) ^ in[6]; - assign d_o[7] = (syndrome_o == 6'h19) ^ in[7]; - assign d_o[8] = (syndrome_o == 6'h29) ^ in[8]; - assign d_o[9] = (syndrome_o == 6'h31) ^ in[9]; - assign d_o[10] = (syndrome_o == 6'h0e) ^ in[10]; - assign d_o[11] = (syndrome_o == 6'h16) ^ in[11]; - assign d_o[12] = (syndrome_o == 6'h26) ^ in[12]; - assign d_o[13] = (syndrome_o == 6'h1a) ^ in[13]; - assign d_o[14] = (syndrome_o == 6'h2a) ^ in[14]; - assign d_o[15] = (syndrome_o == 6'h32) ^ in[15]; - assign d_o[16] = (syndrome_o == 6'h1c) ^ in[16]; - assign d_o[17] = (syndrome_o == 6'h2c) ^ in[17]; - assign d_o[18] = (syndrome_o == 6'h34) ^ in[18]; - assign d_o[19] = (syndrome_o == 6'h38) ^ in[19]; - assign d_o[20] = (syndrome_o == 6'h37) ^ in[20]; - assign d_o[21] = (syndrome_o == 6'h3b) ^ in[21]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_28_22_enc.v b/flow/designs/src/ibex/prim_secded_28_22_enc.v deleted file mode 100644 index 45069c8973..0000000000 --- a/flow/designs/src/ibex/prim_secded_28_22_enc.v +++ /dev/null @@ -1,35 +0,0 @@ -module prim_secded_28_22_enc ( - in, - out -); - input [21:0] in; - output wire [27:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = ((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[20]) ^ in[21]; - assign out[23] = ((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[20]) ^ in[21]; - assign out[24] = (((((((((in[0] ^ in[4]) ^ in[5]) ^ in[6]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[20]; - assign out[25] = (((((((((in[1] ^ in[4]) ^ in[7]) ^ in[8]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[17]) ^ in[19]) ^ in[21]; - assign out[26] = ((((((((((in[2] ^ in[5]) ^ in[7]) ^ in[9]) ^ in[11]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; - assign out[27] = ((((((((((in[3] ^ in[6]) ^ in[8]) ^ in[9]) ^ in[12]) ^ in[14]) ^ in[15]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_39_32_dec.v b/flow/designs/src/ibex/prim_secded_39_32_dec.v deleted file mode 100644 index e4f90ca0eb..0000000000 --- a/flow/designs/src/ibex/prim_secded_39_32_dec.v +++ /dev/null @@ -1,54 +0,0 @@ -module prim_secded_39_32_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [38:0] in; - output wire [31:0] d_o; - output wire [6:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = ((((((((((((in[32] ^ in[2]) ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29]; - assign syndrome_o[1] = (((((((((((((in[33] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31]; - assign syndrome_o[2] = (((((((((((((in[34] ^ in[0]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31]; - assign syndrome_o[3] = (((((((((((((in[35] ^ in[0]) ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30]; - assign syndrome_o[4] = (((((((((((in[36] ^ in[0]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30]; - assign syndrome_o[5] = (((((((((((((in[37] ^ in[1]) ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26]; - assign syndrome_o[6] = ((((((((((((((in[38] ^ in[1]) ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31]; - assign d_o[0] = (syndrome_o == 7'h1c) ^ in[0]; - assign d_o[1] = (syndrome_o == 7'h68) ^ in[1]; - assign d_o[2] = (syndrome_o == 7'h31) ^ in[2]; - assign d_o[3] = (syndrome_o == 7'h13) ^ in[3]; - assign d_o[4] = (syndrome_o == 7'h38) ^ in[4]; - assign d_o[5] = (syndrome_o == 7'h54) ^ in[5]; - assign d_o[6] = (syndrome_o == 7'h2a) ^ in[6]; - assign d_o[7] = (syndrome_o == 7'h45) ^ in[7]; - assign d_o[8] = (syndrome_o == 7'h43) ^ in[8]; - assign d_o[9] = (syndrome_o == 7'h4c) ^ in[9]; - assign d_o[10] = (syndrome_o == 7'h64) ^ in[10]; - assign d_o[11] = (syndrome_o == 7'h58) ^ in[11]; - assign d_o[12] = (syndrome_o == 7'h0e) ^ in[12]; - assign d_o[13] = (syndrome_o == 7'h26) ^ in[13]; - assign d_o[14] = (syndrome_o == 7'h29) ^ in[14]; - assign d_o[15] = (syndrome_o == 7'h07) ^ in[15]; - assign d_o[16] = (syndrome_o == 7'h25) ^ in[16]; - assign d_o[17] = (syndrome_o == 7'h52) ^ in[17]; - assign d_o[18] = (syndrome_o == 7'h61) ^ in[18]; - assign d_o[19] = (syndrome_o == 7'h23) ^ in[19]; - assign d_o[20] = (syndrome_o == 7'h70) ^ in[20]; - assign d_o[21] = (syndrome_o == 7'h62) ^ in[21]; - assign d_o[22] = (syndrome_o == 7'h2c) ^ in[22]; - assign d_o[23] = (syndrome_o == 7'h0d) ^ in[23]; - assign d_o[24] = (syndrome_o == 7'h51) ^ in[24]; - assign d_o[25] = (syndrome_o == 7'h4a) ^ in[25]; - assign d_o[26] = (syndrome_o == 7'h34) ^ in[26]; - assign d_o[27] = (syndrome_o == 7'h16) ^ in[27]; - assign d_o[28] = (syndrome_o == 7'h49) ^ in[28]; - assign d_o[29] = (syndrome_o == 7'h0b) ^ in[29]; - assign d_o[30] = (syndrome_o == 7'h1a) ^ in[30]; - assign d_o[31] = (syndrome_o == 7'h46) ^ in[31]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_39_32_enc.v b/flow/designs/src/ibex/prim_secded_39_32_enc.v deleted file mode 100644 index c8bcadafcb..0000000000 --- a/flow/designs/src/ibex/prim_secded_39_32_enc.v +++ /dev/null @@ -1,46 +0,0 @@ -module prim_secded_39_32_enc ( - in, - out -); - input [31:0] in; - output wire [38:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = in[22]; - assign out[23] = in[23]; - assign out[24] = in[24]; - assign out[25] = in[25]; - assign out[26] = in[26]; - assign out[27] = in[27]; - assign out[28] = in[28]; - assign out[29] = in[29]; - assign out[30] = in[30]; - assign out[31] = in[31]; - assign out[32] = (((((((((((in[2] ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29]; - assign out[33] = ((((((((((((in[3] ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31]; - assign out[34] = ((((((((((((in[0] ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31]; - assign out[35] = ((((((((((((in[0] ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30]; - assign out[36] = ((((((((((in[0] ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30]; - assign out[37] = ((((((((((((in[1] ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26]; - assign out[38] = (((((((((((((in[1] ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31]; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_72_64_dec.v b/flow/designs/src/ibex/prim_secded_72_64_dec.v deleted file mode 100644 index ccd34844a2..0000000000 --- a/flow/designs/src/ibex/prim_secded_72_64_dec.v +++ /dev/null @@ -1,87 +0,0 @@ -module prim_secded_72_64_dec ( - in, - d_o, - syndrome_o, - err_o -); - input [71:0] in; - output wire [63:0] d_o; - output wire [7:0] syndrome_o; - output wire [1:0] err_o; - wire single_error; - assign syndrome_o[0] = (((((((((((((((((((((((((in[64] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63]; - assign syndrome_o[1] = (((((((((((((((((((((((((in[65] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63]; - assign syndrome_o[2] = (((((((((((((((((((((((((in[66] ^ in[0]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63]; - assign syndrome_o[3] = (((((((((((((((((((((((((in[67] ^ in[1]) ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63]; - assign syndrome_o[4] = (((((((((((((((((((((((((in[68] ^ in[2]) ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62]; - assign syndrome_o[5] = (((((((((((((((((((((((((in[69] ^ in[3]) ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61]; - assign syndrome_o[6] = (((((((((((((((((((((((((in[70] ^ in[4]) ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62]; - assign syndrome_o[7] = (((((((((((((((((((((((((in[71] ^ in[5]) ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63]; - assign d_o[0] = (syndrome_o == 8'h07) ^ in[0]; - assign d_o[1] = (syndrome_o == 8'h0b) ^ in[1]; - assign d_o[2] = (syndrome_o == 8'h13) ^ in[2]; - assign d_o[3] = (syndrome_o == 8'h23) ^ in[3]; - assign d_o[4] = (syndrome_o == 8'h43) ^ in[4]; - assign d_o[5] = (syndrome_o == 8'h83) ^ in[5]; - assign d_o[6] = (syndrome_o == 8'h0d) ^ in[6]; - assign d_o[7] = (syndrome_o == 8'h15) ^ in[7]; - assign d_o[8] = (syndrome_o == 8'h25) ^ in[8]; - assign d_o[9] = (syndrome_o == 8'h45) ^ in[9]; - assign d_o[10] = (syndrome_o == 8'h85) ^ in[10]; - assign d_o[11] = (syndrome_o == 8'h19) ^ in[11]; - assign d_o[12] = (syndrome_o == 8'h29) ^ in[12]; - assign d_o[13] = (syndrome_o == 8'h49) ^ in[13]; - assign d_o[14] = (syndrome_o == 8'h89) ^ in[14]; - assign d_o[15] = (syndrome_o == 8'h31) ^ in[15]; - assign d_o[16] = (syndrome_o == 8'h51) ^ in[16]; - assign d_o[17] = (syndrome_o == 8'h91) ^ in[17]; - assign d_o[18] = (syndrome_o == 8'h61) ^ in[18]; - assign d_o[19] = (syndrome_o == 8'ha1) ^ in[19]; - assign d_o[20] = (syndrome_o == 8'hc1) ^ in[20]; - assign d_o[21] = (syndrome_o == 8'h0e) ^ in[21]; - assign d_o[22] = (syndrome_o == 8'h16) ^ in[22]; - assign d_o[23] = (syndrome_o == 8'h26) ^ in[23]; - assign d_o[24] = (syndrome_o == 8'h46) ^ in[24]; - assign d_o[25] = (syndrome_o == 8'h86) ^ in[25]; - assign d_o[26] = (syndrome_o == 8'h1a) ^ in[26]; - assign d_o[27] = (syndrome_o == 8'h2a) ^ in[27]; - assign d_o[28] = (syndrome_o == 8'h4a) ^ in[28]; - assign d_o[29] = (syndrome_o == 8'h8a) ^ in[29]; - assign d_o[30] = (syndrome_o == 8'h32) ^ in[30]; - assign d_o[31] = (syndrome_o == 8'h52) ^ in[31]; - assign d_o[32] = (syndrome_o == 8'h92) ^ in[32]; - assign d_o[33] = (syndrome_o == 8'h62) ^ in[33]; - assign d_o[34] = (syndrome_o == 8'ha2) ^ in[34]; - assign d_o[35] = (syndrome_o == 8'hc2) ^ in[35]; - assign d_o[36] = (syndrome_o == 8'h1c) ^ in[36]; - assign d_o[37] = (syndrome_o == 8'h2c) ^ in[37]; - assign d_o[38] = (syndrome_o == 8'h4c) ^ in[38]; - assign d_o[39] = (syndrome_o == 8'h8c) ^ in[39]; - assign d_o[40] = (syndrome_o == 8'h34) ^ in[40]; - assign d_o[41] = (syndrome_o == 8'h54) ^ in[41]; - assign d_o[42] = (syndrome_o == 8'h94) ^ in[42]; - assign d_o[43] = (syndrome_o == 8'h64) ^ in[43]; - assign d_o[44] = (syndrome_o == 8'ha4) ^ in[44]; - assign d_o[45] = (syndrome_o == 8'hc4) ^ in[45]; - assign d_o[46] = (syndrome_o == 8'h38) ^ in[46]; - assign d_o[47] = (syndrome_o == 8'h58) ^ in[47]; - assign d_o[48] = (syndrome_o == 8'h98) ^ in[48]; - assign d_o[49] = (syndrome_o == 8'h68) ^ in[49]; - assign d_o[50] = (syndrome_o == 8'ha8) ^ in[50]; - assign d_o[51] = (syndrome_o == 8'hc8) ^ in[51]; - assign d_o[52] = (syndrome_o == 8'h70) ^ in[52]; - assign d_o[53] = (syndrome_o == 8'hb0) ^ in[53]; - assign d_o[54] = (syndrome_o == 8'hd0) ^ in[54]; - assign d_o[55] = (syndrome_o == 8'he0) ^ in[55]; - assign d_o[56] = (syndrome_o == 8'h7c) ^ in[56]; - assign d_o[57] = (syndrome_o == 8'had) ^ in[57]; - assign d_o[58] = (syndrome_o == 8'h9b) ^ in[58]; - assign d_o[59] = (syndrome_o == 8'h76) ^ in[59]; - assign d_o[60] = (syndrome_o == 8'he6) ^ in[60]; - assign d_o[61] = (syndrome_o == 8'h79) ^ in[61]; - assign d_o[62] = (syndrome_o == 8'hd3) ^ in[62]; - assign d_o[63] = (syndrome_o == 8'h8f) ^ in[63]; - assign single_error = ^syndrome_o; - assign err_o[0] = single_error; - assign err_o[1] = ~single_error & |syndrome_o; -endmodule diff --git a/flow/designs/src/ibex/prim_secded_72_64_enc.v b/flow/designs/src/ibex/prim_secded_72_64_enc.v deleted file mode 100644 index e2003508f7..0000000000 --- a/flow/designs/src/ibex/prim_secded_72_64_enc.v +++ /dev/null @@ -1,79 +0,0 @@ -module prim_secded_72_64_enc ( - in, - out -); - input [63:0] in; - output wire [71:0] out; - assign out[0] = in[0]; - assign out[1] = in[1]; - assign out[2] = in[2]; - assign out[3] = in[3]; - assign out[4] = in[4]; - assign out[5] = in[5]; - assign out[6] = in[6]; - assign out[7] = in[7]; - assign out[8] = in[8]; - assign out[9] = in[9]; - assign out[10] = in[10]; - assign out[11] = in[11]; - assign out[12] = in[12]; - assign out[13] = in[13]; - assign out[14] = in[14]; - assign out[15] = in[15]; - assign out[16] = in[16]; - assign out[17] = in[17]; - assign out[18] = in[18]; - assign out[19] = in[19]; - assign out[20] = in[20]; - assign out[21] = in[21]; - assign out[22] = in[22]; - assign out[23] = in[23]; - assign out[24] = in[24]; - assign out[25] = in[25]; - assign out[26] = in[26]; - assign out[27] = in[27]; - assign out[28] = in[28]; - assign out[29] = in[29]; - assign out[30] = in[30]; - assign out[31] = in[31]; - assign out[32] = in[32]; - assign out[33] = in[33]; - assign out[34] = in[34]; - assign out[35] = in[35]; - assign out[36] = in[36]; - assign out[37] = in[37]; - assign out[38] = in[38]; - assign out[39] = in[39]; - assign out[40] = in[40]; - assign out[41] = in[41]; - assign out[42] = in[42]; - assign out[43] = in[43]; - assign out[44] = in[44]; - assign out[45] = in[45]; - assign out[46] = in[46]; - assign out[47] = in[47]; - assign out[48] = in[48]; - assign out[49] = in[49]; - assign out[50] = in[50]; - assign out[51] = in[51]; - assign out[52] = in[52]; - assign out[53] = in[53]; - assign out[54] = in[54]; - assign out[55] = in[55]; - assign out[56] = in[56]; - assign out[57] = in[57]; - assign out[58] = in[58]; - assign out[59] = in[59]; - assign out[60] = in[60]; - assign out[61] = in[61]; - assign out[62] = in[62]; - assign out[63] = in[63]; - assign out[64] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63]; - assign out[65] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63]; - assign out[66] = ((((((((((((((((((((((((in[0] ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63]; - assign out[67] = ((((((((((((((((((((((((in[1] ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63]; - assign out[68] = ((((((((((((((((((((((((in[2] ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62]; - assign out[69] = ((((((((((((((((((((((((in[3] ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61]; - assign out[70] = ((((((((((((((((((((((((in[4] ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62]; - assign out[71] = ((((((((((((((((((((((((in[5] ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63]; -endmodule diff --git a/flow/designs/src/ibex/prim_xilinx_clock_gating.v b/flow/designs/src/ibex/prim_xilinx_clock_gating.v deleted file mode 100644 index 0f9bd6bd1e..0000000000 --- a/flow/designs/src/ibex/prim_xilinx_clock_gating.v +++ /dev/null @@ -1,16 +0,0 @@ -module prim_xilinx_clock_gating ( - clk_i, - en_i, - test_en_i, - clk_o -); - input clk_i; - input en_i; - input test_en_i; - output wire clk_o; - BUFGCE u_bufgce( - .I(clk_i), - .CE(en_i | test_en_i), - .O(clk_o) - ); -endmodule diff --git a/flow/designs/src/ibex_sv/BUILD.bazel b/flow/designs/src/ibex_sv/BUILD.bazel new file mode 100644 index 0000000000..964365b4e1 --- /dev/null +++ b/flow/designs/src/ibex_sv/BUILD.bazel @@ -0,0 +1,9 @@ +filegroup( + name = "verilog", + srcs = glob(include = [ + "**/*.sv", + "**/*.svh", + "**/*.v", + ]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex/LICENSE b/flow/designs/src/ibex_sv/LICENSE similarity index 100% rename from flow/designs/src/ibex/LICENSE rename to flow/designs/src/ibex_sv/LICENSE diff --git a/flow/designs/src/ibex/README.md b/flow/designs/src/ibex_sv/README.md similarity index 80% rename from flow/designs/src/ibex/README.md rename to flow/designs/src/ibex_sv/README.md index cc32773ce0..0ee889695e 100644 --- a/flow/designs/src/ibex/README.md +++ b/flow/designs/src/ibex_sv/README.md @@ -10,6 +10,6 @@ Cloned from https://github.com/lowRISC/ibex (`commit 77d801001554cce8fe69e742e96 # Modifications - Default configuration from Repository. -- Converted to verilog [using](https://github.com/zachjs/sv2v). +- Pruned to only those source files which are used and moved most to the top directory. - Added timing constraints. - Added LICENSE. diff --git a/flow/designs/src/ibex_sv/ibex_alu.sv b/flow/designs/src/ibex_sv/ibex_alu.sv new file mode 100644 index 0000000000..1438ff5c7f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_alu.sv @@ -0,0 +1,1271 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Arithmetic logic unit + */ +module ibex_alu #( + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone +) ( + input ibex_pkg::alu_op_e operator_i, + input logic [31:0] operand_a_i, + input logic [31:0] operand_b_i, + + input logic instr_first_cycle_i, + + input logic [32:0] multdiv_operand_a_i, + input logic [32:0] multdiv_operand_b_i, + + input logic multdiv_sel_i, + + input logic [31:0] imd_val_q_i[2], + output logic [31:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + output logic [31:0] adder_result_o, + output logic [33:0] adder_result_ext_o, + + output logic [31:0] result_o, + output logic comparison_result_o, + output logic is_equal_result_o +); + import ibex_pkg::*; + + logic [31:0] operand_a_rev; + logic [32:0] operand_b_neg; + + // bit reverse operand_a for left shifts and bit counting + for (genvar k = 0; k < 32; k++) begin : gen_rev_operand_a + assign operand_a_rev[k] = operand_a_i[31-k]; + end + + /////////// + // Adder // + /////////// + + logic adder_op_b_negate; + logic [32:0] adder_in_a, adder_in_b; + logic [31:0] adder_result; + + always_comb begin + adder_op_b_negate = 1'b0; + unique case (operator_i) + // Adder OPs + ALU_SUB, + + // Comparator OPs + ALU_EQ, ALU_NE, + ALU_GE, ALU_GEU, + ALU_LT, ALU_LTU, + ALU_SLT, ALU_SLTU, + + // MinMax OPs (RV32B Ops) + ALU_MIN, ALU_MINU, + ALU_MAX, ALU_MAXU: adder_op_b_negate = 1'b1; + + default:; + endcase + end + + // prepare operand a + assign adder_in_a = multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i,1'b1}; + + // prepare operand b + assign operand_b_neg = {operand_b_i,1'b0} ^ {33{1'b1}}; + always_comb begin + unique case(1'b1) + multdiv_sel_i: adder_in_b = multdiv_operand_b_i; + adder_op_b_negate: adder_in_b = operand_b_neg; + default : adder_in_b = {operand_b_i, 1'b0}; + endcase + end + + // actual adder + assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); + + assign adder_result = adder_result_ext_o[32:1]; + + assign adder_result_o = adder_result; + + //////////////// + // Comparison // + //////////////// + + logic is_equal; + logic is_greater_equal; // handles both signed and unsigned forms + logic cmp_signed; + + always_comb begin + unique case (operator_i) + ALU_GE, + ALU_LT, + ALU_SLT, + // RV32B only + ALU_MIN, + ALU_MAX: cmp_signed = 1'b1; + + default: cmp_signed = 1'b0; + endcase + end + + assign is_equal = (adder_result == 32'b0); + assign is_equal_result_o = is_equal; + + // Is greater equal + always_comb begin + if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) begin + is_greater_equal = (adder_result[31] == 1'b0); + end else begin + is_greater_equal = operand_a_i[31] ^ (cmp_signed); + end + end + + // GTE unsigned: + // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0 + // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0 + // (a[31] == 1 && b[31] == 0) => 1 + // (a[31] == 0 && b[31] == 1) => 0 + + // GTE signed: + // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0 + // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0 + // (a[31] == 1 && b[31] == 0) => 0 + // (a[31] == 0 && b[31] == 1) => 1 + + // generate comparison result + logic cmp_result; + + always_comb begin + unique case (operator_i) + ALU_EQ: cmp_result = is_equal; + ALU_NE: cmp_result = ~is_equal; + ALU_GE, ALU_GEU, + ALU_MAX, ALU_MAXU: cmp_result = is_greater_equal; // RV32B only + ALU_LT, ALU_LTU, + ALU_MIN, ALU_MINU, //RV32B only + ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal; + + default: cmp_result = is_equal; + endcase + end + + assign comparison_result_o = cmp_result; + + /////////// + // Shift // + /////////// + + // The shifter structure consists of a 33-bit shifter: 32-bit operand + 1 bit extension for + // arithmetic shifts and one-shift support. + // Rotations and funnel shifts are implemented as multi-cycle instructions. + // The shifter is also used for single-bit instructions and bit-field place as detailed below. + // + // Standard Shifts + // =============== + // For standard shift instructions, the direction of the shift is to the right by default. For + // left shifts, the signal shift_left signal is set. If so, the operand is initially reversed, + // shifted to the right by the specified amount and shifted back again. For arithmetic- and + // one-shifts the 33rd bit of the shifter operand can is set accordingly. + // + // Multicycle Shifts + // ================= + // + // Rotation + // -------- + // For rotations, the operand signals operand_a_i and operand_b_i are kept constant to rs1 and + // rs2 respectively. + // + // Rotation pseudocode: + // shift_amt = rs2 & 31; + // multicycle_result = (rs1 >> shift_amt) | (rs1 << (32 - shift_amt)); + // ^-- cycle 0 -----^ ^-- cycle 1 --------------^ + // + // Funnel Shifts + // ------------- + // For funnel shifs, operand_a_i is tied to rs1 in the first cycle and rs3 in the + // second cycle. operand_b_i is always tied to rs2. The order of applying the shift amount or + // its complement is determined by bit [5] of shift_amt. + // + // Funnel shift Pseudocode: (fsl) + // shift_amt = rs2 & 63; + // shift_amt_compl = 32 - shift_amt[4:0] + // if (shift_amt >=33): + // multicycle_result = (rs1 >> shift_amt_compl[4:0]) | (rs3 << shift_amt[4:0]); + // ^-- cycle 0 ----------------^ ^-- cycle 1 ------------^ + // else if (shift_amt <= 31 && shift_amt > 0): + // multicycle_result = (rs1 << shift_amt[4:0]) | (rs3 >> shift_amt_compl[4:0]); + // ^-- cycle 0 ----------^ ^-- cycle 1 -------------------^ + // For shift_amt == 0, 32, both shift_amt[4:0] and shift_amt_compl[4:0] == '0. + // these cases need to be handled separately outside the shifting structure: + // else if (shift_amt == 32): + // multicycle_result = rs3 + // else if (shift_amt == 0): + // multicycle_result = rs1. + // + // Single-Bit Instructions + // ======================= + // Single bit instructions operate on bit operand_b_i[4:0] of operand_a_i. + + // The operations sbset, sbclr and sbinv are implemented by generation of a bit-mask using the + // shifter structure. This is done by left-shifting the operand 32'h1 by the required amount. + // The signal shift_sbmode multiplexes the shifter input and sets the signal shift_left. + // Further processing is taken care of by a separate structure. + // + // For sbext, the bit defined by operand_b_i[4:0] is to be returned. This is done by simply + // shifting operand_a_i to the right by the required amount and returning bit [0] of the result. + // + // Bit-Field Place + // =============== + // The shifter structure is shared to compute bfp_mask << bfp_off. + + logic shift_left; + logic shift_ones; + logic shift_arith; + logic shift_funnel; + logic shift_sbmode; + logic [5:0] shift_amt; + logic [5:0] shift_amt_compl; // complementary shift amount (32 - shift_amt) + + logic [31:0] shift_operand; + logic [32:0] shift_result_ext; + logic unused_shift_result_ext; + logic [31:0] shift_result; + logic [31:0] shift_result_rev; + + // zbf + logic bfp_op; + logic [4:0] bfp_len; + logic [4:0] bfp_off; + logic [31:0] bfp_mask; + logic [31:0] bfp_mask_rev; + logic [31:0] bfp_result; + + // bfp: shares the shifter structure to compute bfp_mask << bfp_off + assign bfp_op = (RV32B != RV32BNone) ? (operator_i == ALU_BFP) : 1'b0; + assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; // len = 0 encodes for len = 16 + assign bfp_off = operand_b_i[20:16]; + assign bfp_mask = (RV32B != RV32BNone) ? ~(32'hffff_ffff << bfp_len) : '0; + for (genvar i=0; i<32; i++) begin : gen_rev_bfp_mask + assign bfp_mask_rev[i] = bfp_mask[31-i]; + end + + assign bfp_result =(RV32B != RV32BNone) ? + (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : '0; + + // bit shift_amt[5]: word swap bit: only considered for FSL/FSR. + // if set, reverse operations in first and second cycle. + assign shift_amt[5] = operand_b_i[5] & shift_funnel; + assign shift_amt_compl = 32 - operand_b_i[4:0]; + + always_comb begin + if (bfp_op) begin + shift_amt[4:0] = bfp_off ; // length field of bfp control word + end else begin + shift_amt[4:0] = instr_first_cycle_i ? + (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : + (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0]); + end + end + + // single-bit mode: shift + assign shift_sbmode = (RV32B != RV32BNone) ? + (operator_i == ALU_SBSET) | (operator_i == ALU_SBCLR) | (operator_i == ALU_SBINV) : 1'b0; + + // left shift if this is: + // * a standard left shift (slo, sll) + // * a rol in the first cycle + // * a ror in the second cycle + // * fsl: without word-swap bit: first cycle, else: second cycle + // * fsr: without word-swap bit: second cycle, else: first cycle + // * a single-bit instruction: sbclr, sbset, sbinv (excluding sbext) + // * bfp: bfp_mask << bfp_off + always_comb begin + unique case (operator_i) + ALU_SLL: shift_left = 1'b1; + ALU_SLO, + ALU_BFP: shift_left = (RV32B != RV32BNone) ? 1'b1 : 1'b0; + ALU_ROL: shift_left = (RV32B != RV32BNone) ? instr_first_cycle_i : 0; + ALU_ROR: shift_left = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 0; + ALU_FSL: shift_left = (RV32B != RV32BNone) ? + (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0; + ALU_FSR: shift_left = (RV32B != RV32BNone) ? + (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0; + default: shift_left = 1'b0; + endcase + if (shift_sbmode) begin + shift_left = 1'b1; + end + end + + assign shift_arith = (operator_i == ALU_SRA); + assign shift_ones = + (RV32B != RV32BNone) ? (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0; + assign shift_funnel = + (RV32B != RV32BNone) ? (operator_i == ALU_FSL) | (operator_i == ALU_FSR) : 1'b0; + + // shifter structure. + always_comb begin + // select shifter input + // for bfp, sbmode and shift_left the corresponding bit-reversed input is chosen. + if (RV32B == RV32BNone) begin + shift_operand = shift_left ? operand_a_rev : operand_a_i; + end else begin + unique case (1'b1) + bfp_op: shift_operand = bfp_mask_rev; + shift_sbmode: shift_operand = 32'h8000_0000; + default: shift_operand = shift_left ? operand_a_rev : operand_a_i; + endcase + end + + shift_result_ext = + $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> + shift_amt[4:0]); + + shift_result = shift_result_ext[31:0]; + unused_shift_result_ext = shift_result_ext[32]; + + for (int unsigned i=0; i<32; i++) begin + shift_result_rev[i] = shift_result[31-i]; + end + + shift_result = shift_left ? shift_result_rev : shift_result; + + end + + /////////////////// + // Bitwise Logic // + /////////////////// + + logic bwlogic_or; + logic bwlogic_and; + logic [31:0] bwlogic_operand_b; + logic [31:0] bwlogic_or_result; + logic [31:0] bwlogic_and_result; + logic [31:0] bwlogic_xor_result; + logic [31:0] bwlogic_result; + + logic bwlogic_op_b_negate; + + always_comb begin + unique case (operator_i) + // Logic-with-negate OPs (RV32B Ops) + ALU_XNOR, + ALU_ORN, + ALU_ANDN: bwlogic_op_b_negate = (RV32B != RV32BNone) ? 1'b1 : 1'b0; + ALU_CMIX: bwlogic_op_b_negate = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 1'b0; + default: bwlogic_op_b_negate = 1'b0; + endcase + end + + assign bwlogic_operand_b = bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i; + + assign bwlogic_or_result = operand_a_i | bwlogic_operand_b; + assign bwlogic_and_result = operand_a_i & bwlogic_operand_b; + assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b; + + assign bwlogic_or = (operator_i == ALU_OR) | (operator_i == ALU_ORN); + assign bwlogic_and = (operator_i == ALU_AND) | (operator_i == ALU_ANDN); + + always_comb begin + unique case (1'b1) + bwlogic_or: bwlogic_result = bwlogic_or_result; + bwlogic_and: bwlogic_result = bwlogic_and_result; + default: bwlogic_result = bwlogic_xor_result; + endcase + end + + logic [5:0] bitcnt_result; + logic [31:0] minmax_result; + logic [31:0] pack_result; + logic [31:0] sext_result; + logic [31:0] singlebit_result; + logic [31:0] rev_result; + logic [31:0] shuffle_result; + logic [31:0] butterfly_result; + logic [31:0] invbutterfly_result; + logic [31:0] clmul_result; + logic [31:0] multicycle_result; + + if (RV32B != RV32BNone) begin : g_alu_rvb + + ///////////////// + // Bitcounting // + ///////////////// + + // The bit-counter structure computes the number of set bits in its operand. Partial results + // (from left to right) are needed to compute the control masks for computation of bext/bdep + // by the butterfly network, if implemented. + // For pcnt, clz and ctz, only the end result is used. + + logic zbe_op; + logic bitcnt_ctz; + logic bitcnt_clz; + logic bitcnt_cz; + logic [31:0] bitcnt_bits; + logic [31:0] bitcnt_mask_op; + logic [31:0] bitcnt_bit_mask; + logic [ 5:0] bitcnt_partial [32]; + logic [31:0] bitcnt_partial_lsb_d; + logic [31:0] bitcnt_partial_msb_d; + + + assign bitcnt_ctz = operator_i == ALU_CTZ; + assign bitcnt_clz = operator_i == ALU_CLZ; + assign bitcnt_cz = bitcnt_ctz | bitcnt_clz; + assign bitcnt_result = bitcnt_partial[31]; + + // Bit-mask generation for clz and ctz: + // The bit mask is generated by spreading the lowest-order set bit in the operand to all + // higher order bits. The resulting mask is inverted to cover the lowest order zeros. In order + // to create the bit mask for leading zeros, the input operand needs to be reversed. + assign bitcnt_mask_op = bitcnt_clz ? operand_a_rev : operand_a_i; + + always_comb begin + bitcnt_bit_mask = bitcnt_mask_op; + bitcnt_bit_mask |= bitcnt_bit_mask << 1; + bitcnt_bit_mask |= bitcnt_bit_mask << 2; + bitcnt_bit_mask |= bitcnt_bit_mask << 4; + bitcnt_bit_mask |= bitcnt_bit_mask << 8; + bitcnt_bit_mask |= bitcnt_bit_mask << 16; + bitcnt_bit_mask = ~bitcnt_bit_mask; + end + + assign zbe_op = (operator_i == ALU_BEXT) | (operator_i == ALU_BDEP); + + always_comb begin + case(1'b1) + zbe_op: bitcnt_bits = operand_b_i; + bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; // clz / ctz + default: bitcnt_bits = operand_a_i; // pcnt + endcase + end + + // The parallel prefix counter is of the structure of a Brent-Kung Adder. In the first + // log2(width) stages, the sum of the n preceding bit lines is computed for the bit lines at + // positions 2**n-1 (power-of-two positions) where n denotes the current stage. + // In stage n=log2(width), the count for position width-1 (the MSB) is finished. + // For the intermediate values, an inverse adder tree then computes the bit counts for the bit + // lines at positions + // m = 2**(n-1) + i*2**(n-2), where i = [1 ... width / 2**(n-1)-1] and n = [log2(width) ... 2]. + // Thus, at every subsequent stage the result of two previously unconnected sub-trees is + // summed, starting at the node summing bits [width/2-1 : 0] and [3*width/4-1: width/2] + // and moving to iteratively sum up all the sub-trees. + // The inverse adder tree thus features log2(width) - 1 stages the first of these stages is a + // single addition at position 3*width/4 - 1. It does not interfere with the last + // stage of the primary adder tree. These stages can thus be folded together, resulting in a + // total of 2*log2(width)-2 stages. + // For more details refer to R. Brent, H. T. Kung, "A Regular Layout for Parallel Adders", + // (1982). + // For a bitline at position p, only bits + // bitcnt_partial[max(i, such that p % log2(i) == 0)-1 : 0] are needed for generation of the + // butterfly network control signals. The adders in the intermediate value adder tree thus need + // not be full 5-bit adders. We leave the optimization to the synthesis tools. + // + // Consider the following 8-bit example for illustraton. + // + // let bitcnt_bits = 8'babcdefgh. + // + // a b c d e f g h + // | /: | /: | /: | /: + // |/ : |/ : |/ : |/ : + // stage 1: + : + : + : + : + // | : /: : | : /: : + // |,--+ : : |,--+ : : + // stage 2: + : : : + : : : + // | : | : /: : : : + // |,-----,--+ : : : : ^-primary adder tree + // stage 3: + : + : : : : : ------------------------- + // : | /| /| /| /| /| : ,-intermediate adder tree + // : |/ |/ |/ |/ |/ : : + // stage 4 : + + + + + : : + // : : : : : : : : + // bitcnt_partial[i] 7 6 5 4 3 2 1 0 + + always_comb begin + bitcnt_partial = '{default: '0}; + // stage 1 + for (int unsigned i=1; i<32; i+=2) begin + bitcnt_partial[i] = {5'h0, bitcnt_bits[i]} + {5'h0, bitcnt_bits[i-1]}; + end + // stage 2 + for (int unsigned i=3; i<32; i+=4) begin + bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i]; + end + // stage 3 + for (int unsigned i=7; i<32; i+=8) begin + bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i]; + end + // stage 4 + for (int unsigned i=15; i <32; i+=16) begin + bitcnt_partial[i] = bitcnt_partial[i-8] + bitcnt_partial[i]; + end + // stage 5 + bitcnt_partial[31] = bitcnt_partial[15] + bitcnt_partial[31]; + // ^- primary adder tree + // ------------------------------- + // ,-intermediate value adder tree + bitcnt_partial[23] = bitcnt_partial[15] + bitcnt_partial[23]; + + // stage 6 + for (int unsigned i=11; i<32; i+=8) begin + bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i]; + end + + // stage 7 + for (int unsigned i=5; i<32; i+=4) begin + bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i]; + end + // stage 8 + bitcnt_partial[0] = {5'h0, bitcnt_bits[0]}; + for (int unsigned i=2; i<32; i+=2) begin + bitcnt_partial[i] = bitcnt_partial[i-1] + {5'h0, bitcnt_bits[i]}; + end + end + + /////////////// + // Min / Max // + /////////////// + + assign minmax_result = cmp_result ? operand_a_i : operand_b_i; + + ////////// + // Pack // + ////////// + + logic packu; + logic packh; + assign packu = operator_i == ALU_PACKU; + assign packh = operator_i == ALU_PACKH; + + always_comb begin + unique case (1'b1) + packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]}; + packh: pack_result = {16'h0, operand_b_i[7:0], operand_a_i[7:0]}; + default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]}; + endcase + end + + ////////// + // Sext // + ////////// + + assign sext_result = (operator_i == ALU_SEXTB) ? + { {24{operand_a_i[7]}}, operand_a_i[7:0]} : { {16{operand_a_i[15]}}, operand_a_i[15:0]}; + + ///////////////////////////// + // Single-bit Instructions // + ///////////////////////////// + + always_comb begin + unique case (operator_i) + ALU_SBSET: singlebit_result = operand_a_i | shift_result; + ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; + ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; + default: singlebit_result = {31'h0, shift_result[0]}; // ALU_SBEXT + endcase + end + + //////////////////////////////////// + // General Reverse and Or-combine // + //////////////////////////////////// + + // Only a subset of the General reverse and or-combine instructions are implemented in the + // balanced version of the B extension. Currently rev, rev8 and orc.b are supported in the + // base extension. + + logic [4:0] zbp_shift_amt; + logic gorc_op; + + assign gorc_op = (operator_i == ALU_GORC); + assign zbp_shift_amt[2:0] = (RV32B == RV32BFull) ? shift_amt[2:0] : {3{&shift_amt[2:0]}}; + assign zbp_shift_amt[4:3] = (RV32B == RV32BFull) ? shift_amt[4:3] : {2{&shift_amt[4:3]}}; + + always_comb begin + rev_result = operand_a_i; + + if (zbp_shift_amt[0]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h5555_5555) << 1) | + ((rev_result & 32'haaaa_aaaa) >> 1); + end + + if (zbp_shift_amt[1]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h3333_3333) << 2) | + ((rev_result & 32'hcccc_cccc) >> 2); + end + + if (zbp_shift_amt[2]) begin + rev_result = (gorc_op ? rev_result : 32'h0) | + ((rev_result & 32'h0f0f_0f0f) << 4) | + ((rev_result & 32'hf0f0_f0f0) >> 4); + end + + if (zbp_shift_amt[3]) begin + rev_result = (gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h0) | + ((rev_result & 32'h00ff_00ff) << 8) | + ((rev_result & 32'hff00_ff00) >> 8); + end + + if (zbp_shift_amt[4]) begin + rev_result = (gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h0) | + ((rev_result & 32'h0000_ffff) << 16) | + ((rev_result & 32'hffff_0000) >> 16); + end + end + + logic crc_hmode; + logic crc_bmode; + logic [31:0] clmul_result_rev; + + if (RV32B == RV32BFull) begin : gen_alu_rvb_full + + ///////////////////////// + // Shuffle / Unshuffle // + ///////////////////////// + + localparam logic [31:0] SHUFFLE_MASK_L [4] = + '{32'h00ff_0000, 32'h0f00_0f00, 32'h3030_3030, 32'h4444_4444}; + localparam logic [31:0] SHUFFLE_MASK_R [4] = + '{32'h0000_ff00, 32'h00f0_00f0, 32'h0c0c_0c0c, 32'h2222_2222}; + + localparam logic [31:0] FLIP_MASK_L [4] = + '{32'h2200_1100, 32'h0044_0000, 32'h4411_0000, 32'h1100_0000}; + localparam logic [31:0] FLIP_MASK_R [4] = + '{32'h0088_0044, 32'h0000_2200, 32'h0000_8822, 32'h0000_0088}; + + logic [31:0] SHUFFLE_MASK_NOT [4]; + for(genvar i = 0; i < 4; i++) begin : gen_shuffle_mask_not + assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[i] | SHUFFLE_MASK_R[i]); + end + + logic shuffle_flip; + assign shuffle_flip = operator_i == ALU_UNSHFL; + + logic [3:0] shuffle_mode; + + always_comb begin + shuffle_result = operand_a_i; + + if (shuffle_flip) begin + shuffle_mode[3] = shift_amt[0]; + shuffle_mode[2] = shift_amt[1]; + shuffle_mode[1] = shift_amt[2]; + shuffle_mode[0] = shift_amt[3]; + end else begin + shuffle_mode = shift_amt[3:0]; + end + + if (shuffle_flip) begin + shuffle_result = (shuffle_result & 32'h8822_4411) | + ((shuffle_result << 6) & FLIP_MASK_L[0]) | + ((shuffle_result >> 6) & FLIP_MASK_R[0]) | + ((shuffle_result << 9) & FLIP_MASK_L[1]) | + ((shuffle_result >> 9) & FLIP_MASK_R[1]) | + ((shuffle_result << 15) & FLIP_MASK_L[2]) | + ((shuffle_result >> 15) & FLIP_MASK_R[2]) | + ((shuffle_result << 21) & FLIP_MASK_L[3]) | + ((shuffle_result >> 21) & FLIP_MASK_R[3]); + end + + if (shuffle_mode[3]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | + (((shuffle_result << 8) & SHUFFLE_MASK_L[0]) | + ((shuffle_result >> 8) & SHUFFLE_MASK_R[0])); + end + if (shuffle_mode[2]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | + (((shuffle_result << 4) & SHUFFLE_MASK_L[1]) | + ((shuffle_result >> 4) & SHUFFLE_MASK_R[1])); + end + if (shuffle_mode[1]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | + (((shuffle_result << 2) & SHUFFLE_MASK_L[2]) | + ((shuffle_result >> 2) & SHUFFLE_MASK_R[2])); + end + if (shuffle_mode[0]) begin + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | + (((shuffle_result << 1) & SHUFFLE_MASK_L[3]) | + ((shuffle_result >> 1) & SHUFFLE_MASK_R[3])); + end + + if (shuffle_flip) begin + shuffle_result = (shuffle_result & 32'h8822_4411) | + ((shuffle_result << 6) & FLIP_MASK_L[0]) | + ((shuffle_result >> 6) & FLIP_MASK_R[0]) | + ((shuffle_result << 9) & FLIP_MASK_L[1]) | + ((shuffle_result >> 9) & FLIP_MASK_R[1]) | + ((shuffle_result << 15) & FLIP_MASK_L[2]) | + ((shuffle_result >> 15) & FLIP_MASK_R[2]) | + ((shuffle_result << 21) & FLIP_MASK_L[3]) | + ((shuffle_result >> 21) & FLIP_MASK_R[3]); + end + end + + /////////////// + // Butterfly // + /////////////// + + // The butterfly / inverse butterfly network executing bext/bdep (zbe) instructions. + // For bdep, the control bits mask of a local left region is generated by + // the inverse of a n-bit left rotate and complement upon wrap (LROTC) operation by the number + // of ones in the deposit bitmask to the right of the segment. n hereby denotes the width + // of the according segment. The bitmask for a pertaining local right region is equal to the + // corresponding local left region. Bext uses an analogue inverse process. + // Consider the following 8-bit example. For details, see Hilewitz et al. "Fast Bit Gather, + // Bit Scatter and Bit Permuation Instructions for Commodity Microprocessors", (2008). + // + // The bext/bdep instructions are completed in 2 cycles. In the first cycle, the control + // bitmask is prepared by executing the parallel prefix bit count. In the second cycle, + // the bit swapping is executed according to the control masks. + + // 8-bit example: (Hilewitz et al.) + // Consider the instruction bdep operand_a_i deposit_mask + // Let operand_a_i = 8'babcd_efgh + // deposit_mask = 8'b1010_1101 + // + // control bitmask for stage 1: + // - number of ones in the right half of the deposit bitmask: 3 + // - width of the segment: 4 + // - control bitmask = ~LROTC(4'b0, 3)[3:0] = 4'b1000 + // + // control bitmask: c3 c2 c1 c0 c3 c2 c1 c0 + // 1 0 0 0 1 0 0 0 + // <- L -----> <- R -----> + // operand_a_i a b c d e f g h + // :\ | | | /: | | | + // : +|---|--|-+ : | | | + // :/ | | | \: | | | + // stage 1 e b c d a f g h + // + // control bitmask: c3 c2 c3 c2 c1 c0 c1 c0 + // 1 1 1 1 1 0 1 0 + // :\ :\ /: /: :\ | /: | + // : +:-+-:+ : : +|-+ : | + // :/ :/ \: \: :/ | \: | + // stage 2 c d e b g f a h + // L R L R L R L R + // control bitmask: c3 c3 c2 c2 c1 c1 c0 c0 + // 1 1 0 0 1 1 0 0 + // :\/: | | :\/: | | + // : : | | : : | | + // :/\: | | :/\: | | + // stage 3 d c e b f g a h + // & deposit bitmask: 1 0 1 0 1 1 0 1 + // result: d 0 e 0 f g 0 h + + logic [ 5:0] bitcnt_partial_q [32]; + + // first cycle + // Store partial bitcnts + for (genvar i=0; i<32; i++) begin : gen_bitcnt_reg_in_lsb + assign bitcnt_partial_lsb_d[i] = bitcnt_partial[i][0]; + end + + for (genvar i=0; i<16; i++) begin : gen_bitcnt_reg_in_b1 + assign bitcnt_partial_msb_d[i] = bitcnt_partial[2*i+1][1]; + end + + for (genvar i=0; i<8; i++) begin : gen_bitcnt_reg_in_b2 + assign bitcnt_partial_msb_d[16+i] = bitcnt_partial[4*i+3][2]; + end + + for (genvar i=0; i<4; i++) begin : gen_bitcnt_reg_in_b3 + assign bitcnt_partial_msb_d[24+i] = bitcnt_partial[8*i+7][3]; + end + + for (genvar i=0; i<2; i++) begin : gen_bitcnt_reg_in_b4 + assign bitcnt_partial_msb_d[28+i] = bitcnt_partial[16*i+15][4]; + end + + assign bitcnt_partial_msb_d[30] = bitcnt_partial[31][5]; + assign bitcnt_partial_msb_d[31] = 1'b0; // unused + + // Second cycle + // Load partial bitcnts + always_comb begin + bitcnt_partial_q = '{default: '0}; + + for (int unsigned i=0; i<32; i++) begin : gen_bitcnt_reg_out_lsb + bitcnt_partial_q[i][0] = imd_val_q_i[0][i]; + end + + for (int unsigned i=0; i<16; i++) begin : gen_bitcnt_reg_out_b1 + bitcnt_partial_q[2*i+1][1] = imd_val_q_i[1][i]; + end + + for (int unsigned i=0; i<8; i++) begin : gen_bitcnt_reg_out_b2 + bitcnt_partial_q[4*i+3][2] = imd_val_q_i[1][16+i]; + end + + for (int unsigned i=0; i<4; i++) begin : gen_bitcnt_reg_out_b3 + bitcnt_partial_q[8*i+7][3] = imd_val_q_i[1][24+i]; + end + + for (int unsigned i=0; i<2; i++) begin : gen_bitcnt_reg_out_b4 + bitcnt_partial_q[16*i+15][4] = imd_val_q_i[1][28+i]; + end + + bitcnt_partial_q[31][5] = imd_val_q_i[1][30]; + end + + logic [31:0] butterfly_mask_l[5]; + logic [31:0] butterfly_mask_r[5]; + logic [31:0] butterfly_mask_not[5]; + logic [31:0] lrotc_stage [5]; // left rotate and complement upon wrap + + // number of bits in local r = 32 / 2**(stage + 1) = 16/2**stage + `define _N(stg) (16 >> stg) + + // bext / bdep control bit generation + for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_ctrl_stage + // number of segs: 2** stg + for (genvar seg=0; seg<2**stg; seg++) begin : gen_butterfly_ctrl + + assign lrotc_stage[stg][2*`_N(stg)*(seg+1)-1 : 2*`_N(stg)*seg] = + {{`_N(stg){1'b0}},{`_N(stg){1'b1}}} << + bitcnt_partial_q[`_N(stg)*(2*seg+1)-1][$clog2(`_N(stg)):0]; + + assign butterfly_mask_l[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)] + = ~lrotc_stage[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)]; + + assign butterfly_mask_r[stg][`_N(stg)*(2*seg+1)-1 : `_N(stg)*(2*seg)] + = ~lrotc_stage[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)]; + + assign butterfly_mask_l[stg][`_N(stg)*(2*seg+1)-1 : `_N(stg)*(2*seg)] = '0; + assign butterfly_mask_r[stg][`_N(stg)*(2*seg+2)-1 : `_N(stg)*(2*seg+1)] = '0; + end + end + `undef _N + + for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_not + assign butterfly_mask_not[stg] = + ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]); + end + + always_comb begin + butterfly_result = operand_a_i; + + butterfly_result = butterfly_result & butterfly_mask_not[0] | + ((butterfly_result & butterfly_mask_l[0]) >> 16)| + ((butterfly_result & butterfly_mask_r[0]) << 16); + + butterfly_result = butterfly_result & butterfly_mask_not[1] | + ((butterfly_result & butterfly_mask_l[1]) >> 8)| + ((butterfly_result & butterfly_mask_r[1]) << 8); + + butterfly_result = butterfly_result & butterfly_mask_not[2] | + ((butterfly_result & butterfly_mask_l[2]) >> 4)| + ((butterfly_result & butterfly_mask_r[2]) << 4); + + butterfly_result = butterfly_result & butterfly_mask_not[3] | + ((butterfly_result & butterfly_mask_l[3]) >> 2)| + ((butterfly_result & butterfly_mask_r[3]) << 2); + + butterfly_result = butterfly_result & butterfly_mask_not[4] | + ((butterfly_result & butterfly_mask_l[4]) >> 1)| + ((butterfly_result & butterfly_mask_r[4]) << 1); + + butterfly_result = butterfly_result & operand_b_i; + end + + always_comb begin + invbutterfly_result = operand_a_i & operand_b_i; + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[4] | + ((invbutterfly_result & butterfly_mask_l[4]) >> 1)| + ((invbutterfly_result & butterfly_mask_r[4]) << 1); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[3] | + ((invbutterfly_result & butterfly_mask_l[3]) >> 2)| + ((invbutterfly_result & butterfly_mask_r[3]) << 2); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[2] | + ((invbutterfly_result & butterfly_mask_l[2]) >> 4)| + ((invbutterfly_result & butterfly_mask_r[2]) << 4); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[1] | + ((invbutterfly_result & butterfly_mask_l[1]) >> 8)| + ((invbutterfly_result & butterfly_mask_r[1]) << 8); + + invbutterfly_result = invbutterfly_result & butterfly_mask_not[0] | + ((invbutterfly_result & butterfly_mask_l[0]) >> 16)| + ((invbutterfly_result & butterfly_mask_r[0]) << 16); + end + + /////////////////////////////////////////////////// + // Carry-less Multiply + Cyclic Redundancy Check // + /////////////////////////////////////////////////// + + // Carry-less multiplication can be understood as multiplication based on + // the addition interpreted as the bit-wise xor operation. + // + // Example: 1101 X 1011 = 1111111: + // + // 1011 X 1101 + // ----------- + // 1101 + // xor 1101 + // --------- + // 10111 + // xor 0000 + // ---------- + // 010111 + // xor 1101 + // ----------- + // 1111111 + // + // Architectural details: + // A 32 x 32-bit array + // [ operand_b[i] ? (operand_a << i) : '0 for i in 0 ... 31 ] + // is generated. The entries of the array are pairwise 'xor-ed' + // together in a 5-stage binary tree. + // + // + // Cyclic Redundancy Check: + // + // CRC-32 (CRC-32/ISO-HDLC) and CRC-32C (CRC-32/ISCSI) are directly implemented. For + // documentation of the crc configuration (crc-polynomials, initialization, reflection, etc.) + // see http://reveng.sourceforge.net/crc-catalogue/all.htm + // A useful guide to crc arithmetic and algorithms is given here: + // http://www.piclist.com/techref/method/math/crcguide.html. + // + // The CRC operation solves the following equation using binary polynomial arithmetic: + // + // rev(rd)(x) = rev(rs1)(x) * x**n mod {1, P}(x) + // + // where P denotes lower 32 bits of the corresponding CRC polynomial, rev(a) the bit reversal + // of a, n = 8,16, or 32 for .b, .h, .w -variants. {a, b} denotes bit concatenation. + // + // Using barret reduction, one can show that + // + // M(x) mod P(x) = R(x) = + // (M(x) * x**n) & {deg(P(x)'{1'b1}}) ^ (M(x) x**-(deg(P(x) - n)) cx mu(x) cx P(x), + // + // Where mu(x) = polydiv(x**64, {1,P}) & 0xffffffff. Here, 'cx' refers to carry-less + // multiplication. Substituting rev(rd)(x) for R(x) and rev(rs1)(x) for M(x) and solving for + // rd(x) with P(x) a crc32 polynomial (deg(P(x)) = 32), we get + // + // rd = rev( (rev(rs1) << n) ^ ((rev(rs1) >> (32-n)) cx mu cx P) + // = (rs1 >> n) ^ rev(rev( (rs1 << (32-n)) cx rev(mu)) cx P) + // ^-- cycle 0--------------------^ + // ^- cycle 1 -------------------------------------------^ + // + // In the last step we used the fact that carry-less multiplication is bit-order agnostic: + // rev(a cx b) = rev(a) cx rev(b). + + logic clmul_rmode; + logic clmul_hmode; + logic [31:0] clmul_op_a; + logic [31:0] clmul_op_b; + logic [31:0] operand_b_rev; + logic [31:0] clmul_and_stage[32]; + logic [31:0] clmul_xor_stage1[16]; + logic [31:0] clmul_xor_stage2[8]; + logic [31:0] clmul_xor_stage3[4]; + logic [31:0] clmul_xor_stage4[2]; + + logic [31:0] clmul_result_raw; + + for (genvar i=0; i<32; i++) begin: gen_rev_operand_b + assign operand_b_rev[i] = operand_b_i[31-i]; + end + + assign clmul_rmode = operator_i == ALU_CLMULR; + assign clmul_hmode = operator_i == ALU_CLMULH; + + // CRC + localparam logic [31:0] CRC32_POLYNOMIAL = 32'h04c1_1db7; + localparam logic [31:0] CRC32_MU_REV = 32'hf701_1641; + + localparam logic [31:0] CRC32C_POLYNOMIAL = 32'h1edc_6f41; + localparam logic [31:0] CRC32C_MU_REV = 32'hdea7_13f1; + + logic crc_op; + + logic crc_cpoly; + + logic [31:0] crc_operand; + logic [31:0] crc_poly; + logic [31:0] crc_mu_rev; + + assign crc_op = (operator_i == ALU_CRC32C_W) | (operator_i == ALU_CRC32_W) | + (operator_i == ALU_CRC32C_H) | (operator_i == ALU_CRC32_H) | + (operator_i == ALU_CRC32C_B) | (operator_i == ALU_CRC32_B); + + assign crc_cpoly = (operator_i == ALU_CRC32C_W) | + (operator_i == ALU_CRC32C_H) | + (operator_i == ALU_CRC32C_B); + + assign crc_hmode = (operator_i == ALU_CRC32_H) | (operator_i == ALU_CRC32C_H); + assign crc_bmode = (operator_i == ALU_CRC32_B) | (operator_i == ALU_CRC32C_B); + + assign crc_poly = crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL; + assign crc_mu_rev = crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV; + + always_comb begin + unique case(1'b1) + crc_bmode: crc_operand = {operand_a_i[7:0], 24'h0}; + crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0}; + default: crc_operand = operand_a_i; + endcase + end + + // Select clmul input + always_comb begin + if (crc_op) begin + clmul_op_a = instr_first_cycle_i ? crc_operand : imd_val_q_i[0]; + clmul_op_b = instr_first_cycle_i ? crc_mu_rev : crc_poly; + end else begin + clmul_op_a = clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i; + clmul_op_b = clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i; + end + end + + for (genvar i=0; i<32; i++) begin : gen_clmul_and_op + assign clmul_and_stage[i] = clmul_op_b[i] ? clmul_op_a << i : '0; + end + + for (genvar i=0; i<16; i++) begin : gen_clmul_xor_op_l1 + assign clmul_xor_stage1[i] = clmul_and_stage[2*i] ^ clmul_and_stage[2*i+1]; + end + + for (genvar i=0; i<8; i++) begin : gen_clmul_xor_op_l2 + assign clmul_xor_stage2[i] = clmul_xor_stage1[2*i] ^ clmul_xor_stage1[2*i+1]; + end + + for (genvar i=0; i<4; i++) begin : gen_clmul_xor_op_l3 + assign clmul_xor_stage3[i] = clmul_xor_stage2[2*i] ^ clmul_xor_stage2[2*i+1]; + end + + for (genvar i=0; i<2; i++) begin : gen_clmul_xor_op_l4 + assign clmul_xor_stage4[i] = clmul_xor_stage3[2*i] ^ clmul_xor_stage3[2*i+1]; + end + + assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1]; + + for (genvar i=0; i<32; i++) begin : gen_rev_clmul_result + assign clmul_result_rev[i] = clmul_result_raw[31-i]; + end + + // clmulr_result = rev(clmul(rev(a), rev(b))) + // clmulh_result = clmulr_result >> 1 + always_comb begin + case(1'b1) + clmul_rmode: clmul_result = clmul_result_rev; + clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]}; + default: clmul_result = clmul_result_raw; + endcase + end + end else begin : gen_alu_rvb_notfull + logic [31:0] unused_imd_val_q_1; + assign unused_imd_val_q_1 = imd_val_q_i[1]; + assign shuffle_result = '0; + assign butterfly_result = '0; + assign invbutterfly_result = '0; + assign clmul_result = '0; + // support signals + assign bitcnt_partial_lsb_d = '0; + assign bitcnt_partial_msb_d = '0; + assign clmul_result_rev = '0; + assign crc_bmode = '0; + assign crc_hmode = '0; + end + + ////////////////////////////////////// + // Multicycle Bitmanip Instructions // + ////////////////////////////////////// + // Ternary instructions + Shift Rotations + Bit extract/deposit + CRC + // For ternary instructions (zbt), operand_a_i is tied to rs1 in the first cycle and rs3 in the + // second cycle. operand_b_i is always tied to rs2. + + always_comb begin + unique case (operator_i) + ALU_CMOV: begin + multicycle_result = (operand_b_i == 32'h0) ? operand_a_i : imd_val_q_i[0]; + imd_val_d_o = '{operand_a_i, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_CMIX: begin + multicycle_result = imd_val_q_i[0] | bwlogic_and_result; + imd_val_d_o = '{bwlogic_and_result, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_FSR, ALU_FSL, + ALU_ROL, ALU_ROR: begin + if (shift_amt[4:0] == 5'h0) begin + multicycle_result = shift_amt[5] ? operand_a_i : imd_val_q_i[0]; + end else begin + multicycle_result = imd_val_q_i[0] | shift_result; + end + imd_val_d_o = '{shift_result, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end + + ALU_CRC32_W, ALU_CRC32C_W, + ALU_CRC32_H, ALU_CRC32C_H, + ALU_CRC32_B, ALU_CRC32C_B: begin + if (RV32B == RV32BFull) begin + unique case(1'b1) + crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8); + crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16); + default: multicycle_result = clmul_result_rev; + endcase + imd_val_d_o = '{clmul_result_rev, 32'h0}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b01; + end else begin + imd_val_we_o = 2'b00; + end + end else begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + end + + ALU_BEXT, ALU_BDEP: begin + if (RV32B == RV32BFull) begin + multicycle_result = (operator_i == ALU_BDEP) ? butterfly_result : invbutterfly_result; + imd_val_d_o = '{bitcnt_partial_lsb_d, bitcnt_partial_msb_d}; + if (instr_first_cycle_i) begin + imd_val_we_o = 2'b11; + end else begin + imd_val_we_o = 2'b00; + end + end else begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + end + + default: begin + imd_val_d_o = '{operand_a_i, 32'h0}; + imd_val_we_o = 2'b00; + multicycle_result = '0; + end + endcase + end + + + end else begin : g_no_alu_rvb + logic [31:0] unused_imd_val_q[2]; + assign unused_imd_val_q = imd_val_q_i; + logic [31:0] unused_butterfly_result; + assign unused_butterfly_result = butterfly_result; + logic [31:0] unused_invbutterfly_result; + assign unused_invbutterfly_result = invbutterfly_result; + // RV32B result signals + assign bitcnt_result = '0; + assign minmax_result = '0; + assign pack_result = '0; + assign sext_result = '0; + assign singlebit_result = '0; + assign rev_result = '0; + assign shuffle_result = '0; + assign butterfly_result = '0; + assign invbutterfly_result = '0; + assign clmul_result = '0; + assign multicycle_result = '0; + // RV32B support signals + assign imd_val_d_o = '{default: '0}; + assign imd_val_we_o = '{default: '0}; + end + + //////////////// + // Result mux // + //////////////// + + always_comb begin + result_o = '0; + + unique case (operator_i) + // Bitwise Logic Operations (negate: RV32B) + ALU_XOR, ALU_XNOR, + ALU_OR, ALU_ORN, + ALU_AND, ALU_ANDN: result_o = bwlogic_result; + + // Adder Operations + ALU_ADD, ALU_SUB: result_o = adder_result; + + // Shift Operations + ALU_SLL, ALU_SRL, + ALU_SRA, + // RV32B + ALU_SLO, ALU_SRO: result_o = shift_result; + + // Shuffle Operations (RV32B) + ALU_SHFL, ALU_UNSHFL: result_o = shuffle_result; + + // Comparison Operations + ALU_EQ, ALU_NE, + ALU_GE, ALU_GEU, + ALU_LT, ALU_LTU, + ALU_SLT, ALU_SLTU: result_o = {31'h0,cmp_result}; + + // MinMax Operations (RV32B) + ALU_MIN, ALU_MAX, + ALU_MINU, ALU_MAXU: result_o = minmax_result; + + // Bitcount Operations (RV32B) + ALU_CLZ, ALU_CTZ, + ALU_PCNT: result_o = {26'h0, bitcnt_result}; + + // Pack Operations (RV32B) + ALU_PACK, ALU_PACKH, + ALU_PACKU: result_o = pack_result; + + // Sign-Extend (RV32B) + ALU_SEXTB, ALU_SEXTH: result_o = sext_result; + + // Ternary Bitmanip Operations (RV32B) + ALU_CMIX, ALU_CMOV, + ALU_FSL, ALU_FSR, + // Rotate Shift (RV32B) + ALU_ROL, ALU_ROR, + // Cyclic Redundancy Checks (RV32B) + ALU_CRC32_W, ALU_CRC32C_W, + ALU_CRC32_H, ALU_CRC32C_H, + ALU_CRC32_B, ALU_CRC32C_B, + // Bit Extract / Deposit (RV32B) + ALU_BEXT, ALU_BDEP: result_o = multicycle_result; + + // Single-Bit Bitmanip Operations (RV32B) + ALU_SBSET, ALU_SBCLR, + ALU_SBINV, ALU_SBEXT: result_o = singlebit_result; + + // General Reverse / Or-combine (RV32B) + ALU_GREV, ALU_GORC: result_o = rev_result; + + // Bit Field Place (RV32B) + ALU_BFP: result_o = bfp_result; + + // Carry-less Multiply Operations (RV32B) + ALU_CLMUL, ALU_CLMULR, + ALU_CLMULH: result_o = clmul_result; + + default: ; + endcase + end + + logic unused_shift_amt_compl; + assign unused_shift_amt_compl = shift_amt_compl[5]; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv b/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv new file mode 100644 index 0000000000..12a487fe1d --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_compressed_decoder.sv @@ -0,0 +1,300 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Compressed instruction decoder + * + * Decodes RISC-V compressed instructions into their RV32 equivalent. + * This module is fully combinatorial, clock and reset are used for + * assertions only. + */ + +`include "prim_assert.sv" + +module ibex_compressed_decoder ( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + input logic [31:0] instr_i, + output logic [31:0] instr_o, + output logic is_compressed_o, + output logic illegal_instr_o +); + import ibex_pkg::*; + + // valid_i indicates if instr_i is valid and is used for assertions only. + // The following signal is used to avoid possible lint errors. + logic unused_valid; + assign unused_valid = valid_i; + + //////////////////////// + // Compressed decoder // + //////////////////////// + + always_comb begin + // By default, forward incoming instruction, mark it as legal. + instr_o = instr_i; + illegal_instr_o = 1'b0; + + // Check if incoming instruction is compressed. + unique case (instr_i[1:0]) + // C0 + 2'b00: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi4spn -> addi rd', x2, imm + instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], + instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}}; + if (instr_i[12:5] == 8'b0) illegal_instr_o = 1'b1; + end + + 3'b010: begin + // c.lw -> lw rd', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6], + 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}}; + end + + 3'b110: begin + // c.sw -> sw rs2', imm(rs1') + instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], + 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], + 2'b00, {OPCODE_STORE}}; + end + + 3'b001, + 3'b011, + 3'b100, + 3'b101, + 3'b111: begin + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // C1 + // + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b01: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.addi -> addi rd, rd, nzimm + // c.nop + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], + instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}}; + end + + 3'b001, 3'b101: begin + // 001: c.jal -> jal x1, imm + // 101: c.j -> jal x0, imm + instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], + instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], + {9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}}; + end + + 3'b010: begin + // c.li -> addi rd, x0, nzimm + // (c.li hints are translated into an addi hint) + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, + 3'b0, instr_i[11:7], {OPCODE_OP_IMM}}; + end + + 3'b011: begin + // c.lui -> lui rd, imm + // (c.lui hints are translated into a lui hint) + instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}}; + + if (instr_i[11:7] == 5'h02) begin + // c.addi16sp -> addi x2, x2, nzimm + instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], + instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}}; + end + + if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1; + end + + 3'b100: begin + unique case (instr_i[11:10]) + 2'b00, + 2'b01: begin + // 00: c.srli -> srli rd, rd, shamt + // 01: c.srai -> srai rd, rd, shamt + // (c.srli/c.srai hints are translated into a srli/srai hint) + instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7], + 3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}}; + if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; + end + + 2'b10: begin + // c.andi -> andi rd, rd, imm + instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], + 3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}}; + end + + 2'b11: begin + unique case ({instr_i[12], instr_i[6:5]}) + 3'b000: begin + // c.sub -> sub rd', rd', rs2' + instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], + 3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b001: begin + // c.xor -> xor rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b010: begin + // c.or -> or rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b011: begin + // c.and -> and rd', rd', rs2' + instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, + 2'b01, instr_i[9:7], {OPCODE_OP}}; + end + + 3'b100, + 3'b101, + 3'b110, + 3'b111: begin + // 100: c.subw + // 101: c.addw + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + 3'b110, 3'b111: begin + // 0: c.beqz -> beq rs1', x0, imm + // 1: c.bnez -> bne rs1', x0, imm + instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01, + instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], + instr_i[12], {OPCODE_BRANCH}}; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // C2 + // + // Register address checks for RV32E are performed in the regular instruction decoder. + // If this check fails, an illegal instruction exception is triggered and the controller + // writes the actual faulting instruction to mtval. + 2'b10: begin + unique case (instr_i[15:13]) + 3'b000: begin + // c.slli -> slli rd, rd, shamt + // (c.ssli hints are translated into a slli hint) + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}}; + if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1; // reserved for custom extensions + end + + 3'b010: begin + // c.lwsp -> lw rd, imm(x2) + instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, + 3'b010, instr_i[11:7], OPCODE_LOAD}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + + 3'b100: begin + if (instr_i[12] == 1'b0) begin + if (instr_i[6:2] != 5'b0) begin + // c.mv -> add rd/rs1, x0, rs2 + // (c.mv hints are translated into an add hint) + instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}}; + end else begin + // c.jr -> jalr x0, rd/rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}}; + if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1; + end + end else begin + if (instr_i[6:2] != 5'b0) begin + // c.add -> add rd, rd, rs2 + // (c.add hints are translated into an add hint) + instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}}; + end else begin + if (instr_i[11:7] == 5'b0) begin + // c.ebreak -> ebreak + instr_o = {32'h00_10_00_73}; + end else begin + // c.jalr -> jalr x1, rs1, 0 + instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}}; + end + end + end + end + + 3'b110: begin + // c.swsp -> sw rs2, imm(x2) + instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, + instr_i[11:9], 2'b00, {OPCODE_STORE}}; + end + + 3'b001, + 3'b011, + 3'b101, + 3'b111: begin + illegal_instr_o = 1'b1; + end + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + // Incoming instruction is not compressed. + 2'b11:; + + default: begin + illegal_instr_o = 1'b1; + end + endcase + end + + assign is_compressed_o = (instr_i[1:0] != 2'b11); + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexInstrLSBsKnown, valid_i |-> + !$isunknown(instr_i[1:0])) + `ASSERT(IbexC0Known1, (valid_i && (instr_i[1:0] == 2'b00)) |-> + !$isunknown(instr_i[15:13])) + `ASSERT(IbexC1Known1, (valid_i && (instr_i[1:0] == 2'b01)) |-> + !$isunknown(instr_i[15:13])) + `ASSERT(IbexC1Known2, (valid_i && (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100)) |-> + !$isunknown(instr_i[11:10])) + `ASSERT(IbexC1Known3, (valid_i && + (instr_i[1:0] == 2'b01) && (instr_i[15:13] == 3'b100) && (instr_i[11:10] == 2'b11)) |-> + !$isunknown({instr_i[12], instr_i[6:5]})) + `ASSERT(IbexC2Known1, (valid_i && (instr_i[1:0] == 2'b10)) |-> + !$isunknown(instr_i[15:13])) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_controller.sv b/flow/designs/src/ibex_sv/ibex_controller.sv new file mode 100644 index 0000000000..b59833d5b6 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_controller.sv @@ -0,0 +1,846 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Main controller of the processor + */ + +`include "prim_assert.sv" + +module ibex_controller #( + parameter bit WritebackStage = 0, + parameter bit BranchPredictor = 0 + ) ( + input logic clk_i, + input logic rst_ni, + + output logic ctrl_busy_o, // core is busy processing instrs + + // decoder related signals + input logic illegal_insn_i, // decoder has an invalid instr + input logic ecall_insn_i, // decoder has ECALL instr + input logic mret_insn_i, // decoder has MRET instr + input logic dret_insn_i, // decoder has DRET instr + input logic wfi_insn_i, // decoder has WFI instr + input logic ebrk_insn_i, // decoder has EBREAK instr + input logic csr_pipe_flush_i, // do CSR-related pipeline flush + + // instr from IF-ID pipeline stage + input logic instr_valid_i, // instr is valid + input logic [31:0] instr_i, // uncompressed instr data for mtval + input logic [15:0] instr_compressed_i, // instr compressed data for mtval + input logic instr_is_compressed_i, // instr is compressed + input logic instr_bp_taken_i, // instr was predicted taken branch + input logic instr_fetch_err_i, // instr has error + input logic instr_fetch_err_plus2_i, // instr error is x32 + input logic [31:0] pc_id_i, // instr address + + // to IF-ID pipeline stage + output logic instr_valid_clear_o, // kill instr in IF-ID reg + output logic id_in_ready_o, // ID stage is ready for new instr + output logic controller_run_o, // Controller is in standard instruction + // run mode + + // to prefetcher + output logic instr_req_o, // start fetching instructions + output logic pc_set_o, // jump to address set by pc_mux + output logic pc_set_spec_o, // speculative branch + output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector + // (boot, normal, exception...) + output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was + // mispredicted (predicted taken) + output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC + output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs + + // LSU + input logic [31:0] lsu_addr_last_i, // for mtval + input logic load_err_i, + input logic store_err_i, + output logic wb_exception_o, // Instruction in WB taking an exception + + // jump/branch signals + input logic branch_set_i, // branch set signal (branch definitely + // taken) + input logic branch_set_spec_i, // speculative branch signal (branch + // may be taken) + input logic branch_not_set_i, // branch is definitely not taken + input logic jump_set_i, // jump taken set signal + + // interrupt signals + input logic csr_mstatus_mie_i, // M-mode interrupt enable bit + input logic irq_pending_i, // interrupt request pending + input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with + // mie CSR + input logic irq_nm_i, // non-maskeable interrupt + output logic nmi_mode_o, // core executing NMI handler + + // debug signals + input logic debug_req_i, + output ibex_pkg::dbg_cause_e debug_cause_o, + output logic debug_csr_save_o, + output logic debug_mode_o, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_wb_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_dret_id_o, + output logic csr_save_cause_o, + output logic [31:0] csr_mtval_o, + input ibex_pkg::priv_lvl_e priv_mode_i, + input logic csr_mstatus_tw_i, + + // stall & flush signals + input logic stall_id_i, + input logic stall_wb_i, + output logic flush_id_o, + input logic ready_wb_i, + + // performance monitors + output logic perf_jump_o, // we are executing a jump + // instruction (j, jr, jal, jalr) + output logic perf_tbranch_o // we are executing a taken branch + // instruction +); + import ibex_pkg::*; + + // FSM state encoding + typedef enum logic [3:0] { + RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, + IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID + } ctrl_fsm_e; + + ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns; + + logic nmi_mode_q, nmi_mode_d; + logic debug_mode_q, debug_mode_d; + logic load_err_q, load_err_d; + logic store_err_q, store_err_d; + logic exc_req_q, exc_req_d; + logic illegal_insn_q, illegal_insn_d; + + // Of the various exception/fault signals, which one takes priority in FLUSH and hence controls + // what happens next (setting exc_cause, csr_mtval etc) + logic instr_fetch_err_prio; + logic illegal_insn_prio; + logic ecall_insn_prio; + logic ebrk_insn_prio; + logic store_err_prio; + logic load_err_prio; + + logic stall; + logic halt_if; + logic retain_id; + logic flush_id; + logic illegal_dret; + logic illegal_umode; + logic exc_req_lsu; + logic special_req_all; + logic special_req_branch; + logic enter_debug_mode; + logic ebreak_into_debug; + logic handle_irq; + + logic [3:0] mfip_id; + logic unused_irq_timer; + + logic ecall_insn; + logic mret_insn; + logic dret_insn; + logic wfi_insn; + logic ebrk_insn; + logic csr_pipe_flush; + logic instr_fetch_err; + +`ifndef SYNTHESIS + // synopsys translate_off + // make sure we are called later so that we do not generate messages for + // glitches + always_ff @(negedge clk_i) begin + // print warning in case of decoding errors + if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin + $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i, + ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i); + end + end + // synopsys translate_on +`endif + + //////////////// + // Exceptions // + //////////////// + + assign load_err_d = load_err_i; + assign store_err_d = store_err_i; + + // Decoder doesn't take instr_valid into account, factor it in here. + assign ecall_insn = ecall_insn_i & instr_valid_i; + assign mret_insn = mret_insn_i & instr_valid_i; + assign dret_insn = dret_insn_i & instr_valid_i; + assign wfi_insn = wfi_insn_i & instr_valid_i; + assign ebrk_insn = ebrk_insn_i & instr_valid_i; + assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; + assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; + + // "Executing DRET outside of Debug Mode causes an illegal instruction exception." + // [Debug Spec v0.13.2, p.41] + assign illegal_dret = dret_insn & ~debug_mode_q; + + // Some instructions can only be executed in M-Mode + assign illegal_umode = (priv_mode_i != PRIV_LVL_M) & + // MRET must be in M-Mode. TW means trap WFI to M-Mode. + (mret_insn | (csr_mstatus_tw_i & wfi_insn)); + + // This is recorded in the illegal_insn_q flop to help timing. Specifically + // it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o + // to pc_set_o. Clear when controller is in FLUSH so it won't remain set + // once illegal instruction is handled. + // All terms in this expression are qualified by instr_valid_i + assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH); + + // exception requests + // requests are flopped in exc_req_q. This is cleared when controller is in + // the FLUSH state so the cycle following exc_req_q won't remain set for an + // exception request that has just been handled. + // All terms in this expression are qualified by instr_valid_i + assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) & + (ctrl_fsm_cs != FLUSH); + + // LSU exception requests + assign exc_req_lsu = store_err_i | load_err_i; + + + // special requests: special instructions, pipeline flushes, exceptions... + + // To avoid creating a path from data_err_i -> instr_req_o and to help timing the below + // special_req_all has a version that only applies to branches. For a branch the controller needs + // to set pc_set_o but only if there is no special request. If the generic special_req_all signal + // is used then a variety of signals that will never cause a special request during a branch + // instruction end up factored into pc_set_o. The special_req_branch only considers the special + // request reasons that are relevant to a branch. + + // generic special request signal, applies to all instructions + // All terms in this expression are qualified by instr_valid_i except exc_req_lsu which can come + // from the Writeback stage with no instr_valid_i from the ID stage + assign special_req_all = mret_insn | dret_insn | wfi_insn | csr_pipe_flush | + exc_req_d | exc_req_lsu; + + // special request that can specifically occur during branch instructions + // All terms in this expression are qualified by instr_valid_i + assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); + + `ASSERT(SpecialReqBranchGivesSpecialReqAll, + special_req_branch |-> special_req_all) + + `ASSERT(SpecialReqAllGivesSpecialReqBranchIfBranchInst, + special_req_all && (branch_set_i || jump_set_i) |-> special_req_branch) + + // Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11 + if (WritebackStage) begin : g_wb_exceptions + always_comb begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + + // Note that with the writeback stage store/load errors occur on the instruction in writeback, + // all other exception/faults occur on the instruction in ID/EX. The faults from writeback + // must take priority as that instruction is architecurally ordered before the one in ID/EX. + if (store_err_q) begin + store_err_prio = 1'b1; + end else if (load_err_q) begin + load_err_prio = 1'b1; + end else if (instr_fetch_err) begin + instr_fetch_err_prio = 1'b1; + end else if (illegal_insn_q) begin + illegal_insn_prio = 1'b1; + end else if (ecall_insn) begin + ecall_insn_prio = 1'b1; + end else if (ebrk_insn) begin + ebrk_insn_prio = 1'b1; + end + end + + // Instruction in writeback is generating an exception so instruction in ID must not execute + assign wb_exception_o = load_err_q | store_err_q | load_err_i | store_err_i; + end else begin : g_no_wb_exceptions + always_comb begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + + if (instr_fetch_err) begin + instr_fetch_err_prio = 1'b1; + end else if (illegal_insn_q) begin + illegal_insn_prio = 1'b1; + end else if (ecall_insn) begin + ecall_insn_prio = 1'b1; + end else if (ebrk_insn) begin + ebrk_insn_prio = 1'b1; + end else if (store_err_q) begin + store_err_prio = 1'b1; + end else if (load_err_q) begin + load_err_prio = 1'b1; + end + end + assign wb_exception_o = 1'b0; + end + + `ASSERT_IF(IbexExceptionPrioOnehot, + $onehot({instr_fetch_err_prio, + illegal_insn_prio, + ecall_insn_prio, + ebrk_insn_prio, + store_err_prio, + load_err_prio}), + (ctrl_fsm_cs == FLUSH) & exc_req_q) + + //////////////// + // Interrupts // + //////////////// + + // Enter debug mode due to an external debug_req_i or because the core is in + // single step mode (dcsr.step == 1). Single step must be qualified with + // instruction valid otherwise the core will immediately enter debug mode + // due to a recently flushed IF (or a delay in an instruction returning from + // memory) before it has had anything to single step. + // Also enter debug mode on a trigger match (hardware breakpoint) + assign enter_debug_mode = (debug_req_i | (debug_single_step_i & instr_valid_i) | + trigger_match_i) & ~debug_mode_q; + + // Set when an ebreak should enter debug mode rather than jump to exception + // handler + assign ebreak_into_debug = priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i : + priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i : + 1'b0; + + // Interrupts including NMI are ignored, + // - while in debug mode [Debug Spec v0.13.2, p.39], + // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and + // cannot be interrupted by regular interrupts). + assign handle_irq = ~debug_mode_q & ~nmi_mode_q & + (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); + + // generate ID of fast interrupts, highest priority to highest ID + always_comb begin : gen_mfip_id + if (irqs_i.irq_fast[14]) mfip_id = 4'd14; + else if (irqs_i.irq_fast[13]) mfip_id = 4'd13; + else if (irqs_i.irq_fast[12]) mfip_id = 4'd12; + else if (irqs_i.irq_fast[11]) mfip_id = 4'd11; + else if (irqs_i.irq_fast[10]) mfip_id = 4'd10; + else if (irqs_i.irq_fast[ 9]) mfip_id = 4'd9; + else if (irqs_i.irq_fast[ 8]) mfip_id = 4'd8; + else if (irqs_i.irq_fast[ 7]) mfip_id = 4'd7; + else if (irqs_i.irq_fast[ 6]) mfip_id = 4'd6; + else if (irqs_i.irq_fast[ 5]) mfip_id = 4'd5; + else if (irqs_i.irq_fast[ 4]) mfip_id = 4'd4; + else if (irqs_i.irq_fast[ 3]) mfip_id = 4'd3; + else if (irqs_i.irq_fast[ 2]) mfip_id = 4'd2; + else if (irqs_i.irq_fast[ 1]) mfip_id = 4'd1; + else mfip_id = 4'd0; + end + + assign unused_irq_timer = irqs_i.irq_timer; + + ///////////////////// + // Core controller // + ///////////////////// + + always_comb begin + // Default values + instr_req_o = 1'b1; + + csr_save_if_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_wb_o = 1'b0; + csr_restore_mret_id_o = 1'b0; + csr_restore_dret_id_o = 1'b0; + csr_save_cause_o = 1'b0; + csr_mtval_o = '0; + + // The values of pc_mux and exc_pc_mux are only relevant if pc_set is set. Some of the states + // below always set pc_mux and exc_pc_mux but only set pc_set if certain conditions are met. + // This avoid having to factor those conditions into the pc_mux and exc_pc_mux select signals + // helping timing. + pc_mux_o = PC_BOOT; + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + nt_branch_mispredict_o = 1'b0; + + exc_pc_mux_o = EXC_PC_IRQ; + exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00 + + ctrl_fsm_ns = ctrl_fsm_cs; + + ctrl_busy_o = 1'b1; + + halt_if = 1'b0; + retain_id = 1'b0; + flush_id = 1'b0; + + debug_csr_save_o = 1'b0; + debug_cause_o = DBG_CAUSE_EBREAK; + debug_mode_d = debug_mode_q; + nmi_mode_d = nmi_mode_q; + + perf_tbranch_o = 1'b0; + perf_jump_o = 1'b0; + + controller_run_o = 1'b0; + + unique case (ctrl_fsm_cs) + RESET: begin + instr_req_o = 1'b0; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + ctrl_fsm_ns = BOOT_SET; + end + + BOOT_SET: begin + // copy boot address to instr fetch address + instr_req_o = 1'b1; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + ctrl_fsm_ns = FIRST_FETCH; + end + + WAIT_SLEEP: begin + ctrl_busy_o = 1'b0; + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = SLEEP; + end + + SLEEP: begin + // instruction in IF stage is already valid + // we begin execution when an interrupt has arrived + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + + // normal execution flow + // in debug mode or single step mode we leave immediately (wfi=nop) + if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin + ctrl_fsm_ns = FIRST_FETCH; + end else begin + // Make sure clock remains disabled. + ctrl_busy_o = 1'b0; + end + end + + FIRST_FETCH: begin + // Stall because of IF miss + if (id_in_ready_o) begin + ctrl_fsm_ns = DECODE; + end + + // handle interrupts + if (handle_irq) begin + // We are handling an interrupt. Set halt_if to tell IF not to give + // us any more instructions before it redirects to the handler, but + // don't set flush_id: we must allow this instruction to complete + // (since it might have outstanding loads or stores). + ctrl_fsm_ns = IRQ_TAKEN; + halt_if = 1'b1; + end + + // enter debug mode + if (enter_debug_mode) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the + // ID state is needed for correct debug mode entry + halt_if = 1'b1; + end + end + + DECODE: begin + // normal operating mode of the ID stage, in case of debug and interrupt requests, + // priorities are as follows (lower number == higher priority) + // 1. currently running (multicycle) instructions and exceptions caused by these + // 2. debug requests + // 3. interrupt requests + + controller_run_o = 1'b1; + + // Set PC mux for branch and jump here to ease timing. Value is only relevant if pc_set_o is + // also set. Setting the mux value here avoids factoring in special_req and instr_valid_i + // which helps timing. + pc_mux_o = PC_JUMP; + + + // Get ready for special instructions, exceptions, pipeline flushes + if (special_req_all) begin + // Halt IF but don't flush ID. This leaves a valid instruction in + // ID so controller can determine appropriate action in the + // FLUSH state. + retain_id = 1'b1; + + // Wait for the writeback stage to either be ready for a new instruction or raise its own + // exception before going to FLUSH. If the instruction in writeback raises an exception it + // must take priority over any exception from an instruction in ID/EX. Only once the + // writeback stage is ready can we be certain that won't happen. Without a writeback + // stage ready_wb_i == 1 so the FSM will always go directly to FLUSH. + + if (ready_wb_i | wb_exception_o) begin + ctrl_fsm_ns = FLUSH; + end + end + + if (!special_req_branch) begin + if (branch_set_i || jump_set_i) begin + // Only set the PC if the branch predictor hasn't already done the branch for us + pc_set_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1; + + perf_tbranch_o = branch_set_i; + perf_jump_o = jump_set_i; + end + + if (BranchPredictor) begin + if (instr_bp_taken_i & branch_not_set_i) begin + // If the instruction is a branch that was predicted to be taken but was not taken + // signal a mispredict. + nt_branch_mispredict_o = 1'b1; + end + end + end + + // pc_set signal excluding branch taken condition + if ((branch_set_spec_i || jump_set_i) && !special_req_branch) begin + // Only speculatively set the PC if the branch predictor hasn't already done the branch + // for us + pc_set_spec_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1; + end + + // If entering debug mode or handling an IRQ the core needs to wait + // until the current instruction has finished executing. Stall IF + // during that time. + if ((enter_debug_mode || handle_irq) && stall) begin + halt_if = 1'b1; + end + + if (!stall && !special_req_all) begin + if (enter_debug_mode) begin + // enter debug mode + ctrl_fsm_ns = DBG_TAKEN_IF; + // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the + // ID state is needed for correct debug mode entry + halt_if = 1'b1; + end else if (handle_irq) begin + // handle interrupt (not in debug mode) + ctrl_fsm_ns = IRQ_TAKEN; + // We are handling an interrupt (not in debug mode). Set halt_if to + // tell IF not to give us any more instructions before it redirects + // to the handler, but don't set flush_id: we must allow this + // instruction to complete (since it might have outstanding loads + // or stores). + halt_if = 1'b1; + end + end + + end // DECODE + + IRQ_TAKEN: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_IRQ; + + if (handle_irq) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + csr_save_if_o = 1'b1; + csr_save_cause_o = 1'b1; + + // interrupt priorities according to Privileged Spec v1.11 p.31 + if (irq_nm_i && !nmi_mode_q) begin + exc_cause_o = EXC_CAUSE_IRQ_NM; + nmi_mode_d = 1'b1; // enter NMI mode + end else if (irqs_i.irq_fast != 15'b0) begin + // generate exception cause ID from fast interrupt ID: + // - first bit distinguishes interrupts from exceptions, + // - second bit adds 16 to fast interrupt ID + // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16} + exc_cause_o = exc_cause_e'({2'b11, mfip_id}); + end else if (irqs_i.irq_external) begin + exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; + end else if (irqs_i.irq_software) begin + exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M; + end else begin // irqs_i.irq_timer + exc_cause_o = EXC_CAUSE_IRQ_TIMER_M; + end + end + + ctrl_fsm_ns = DECODE; + end + + DBG_TAKEN_IF: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_DBD; + + // enter debug mode and save PC in IF to dpc + // jump to debug exception handler in debug memory + if (debug_single_step_i || debug_req_i || trigger_match_i) begin + flush_id = 1'b1; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + + csr_save_if_o = 1'b1; + debug_csr_save_o = 1'b1; + + csr_save_cause_o = 1'b1; + if (trigger_match_i) begin + debug_cause_o = DBG_CAUSE_TRIGGER; + end else if (debug_single_step_i) begin + debug_cause_o = DBG_CAUSE_STEP; + end else begin + debug_cause_o = DBG_CAUSE_HALTREQ; + end + + // enter debug mode + debug_mode_d = 1'b1; + end + + ctrl_fsm_ns = DECODE; + end + + DBG_TAKEN_ID: begin + // enter debug mode and save PC in ID to dpc, used when encountering + // 1. EBREAK during debug mode + // 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set). + // regular ebreak's go through FLUSH. + // + // for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39] + // jump to debug exception handler in debug memory + flush_id = 1'b1; + pc_mux_o = PC_EXC; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + exc_pc_mux_o = EXC_PC_DBD; + + // update dcsr and dpc + if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry + + // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage) + csr_save_cause_o = 1'b1; + csr_save_id_o = 1'b1; + + // dcsr + debug_csr_save_o = 1'b1; + debug_cause_o = DBG_CAUSE_EBREAK; + end + + // enter debug mode + debug_mode_d = 1'b1; + + ctrl_fsm_ns = DECODE; + end + + FLUSH: begin + // flush the pipeline + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = DECODE; + + // As pc_mux and exc_pc_mux can take various values in this state they aren't set early + // here. + + // exceptions: set exception PC, save PC and exception cause + // exc_req_lsu is high for one clock cycle only (in DECODE) + if (exc_req_q || store_err_q || load_err_q) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + pc_mux_o = PC_EXC; + exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC; + + if (WritebackStage) begin : g_writeback_mepc_save + // With the writeback stage present whether an instruction accessing memory will cause + // an exception is only known when it is in writeback. So when taking such an exception + // epc must come from writeback. + csr_save_id_o = ~(store_err_q | load_err_q); + csr_save_wb_o = store_err_q | load_err_q; + end else begin : g_no_writeback_mepc_save + csr_save_id_o = 1'b0; + end + + csr_save_cause_o = 1'b1; + + // Exception/fault prioritisation logic will have set exactly 1 X_prio signal + unique case (1'b1) + instr_fetch_err_prio: begin + exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT; + csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i; + end + illegal_insn_prio: begin + exc_cause_o = EXC_CAUSE_ILLEGAL_INSN; + csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i; + end + ecall_insn_prio: begin + exc_cause_o = (priv_mode_i == PRIV_LVL_M) ? EXC_CAUSE_ECALL_MMODE : + EXC_CAUSE_ECALL_UMODE; + end + ebrk_insn_prio: begin + if (debug_mode_q | ebreak_into_debug) begin + /* + * EBREAK in debug mode re-enters debug mode + * + * "The only exception is EBREAK. When that is executed in Debug + * Mode, it halts the hart again but without updating dpc or + * dcsr." [Debug Spec v0.13.2, p.39] + */ + + /* + * dcsr.ebreakm == 1: + * "EBREAK instructions in M-mode enter Debug Mode." + * [Debug Spec v0.13.2, p.42] + */ + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_cause_o = 1'b0; + ctrl_fsm_ns = DBG_TAKEN_ID; + flush_id = 1'b0; + end else begin + /* + * "The EBREAK instruction is used by debuggers to cause control + * to be transferred back to a debugging environment. It + * generates a breakpoint exception and performs no other + * operation. [...] ECALL and EBREAK cause the receiving + * privilege mode's epc register to be set to the address of the + * ECALL or EBREAK instruction itself, not the address of the + * following instruction." [Privileged Spec v1.11, p.40] + */ + exc_cause_o = EXC_CAUSE_BREAKPOINT; + end + end + store_err_prio: begin + exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + load_err_prio: begin + exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + default: ; + endcase + end else begin + // special instructions and pipeline flushes + if (mret_insn) begin + pc_mux_o = PC_ERET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + csr_restore_mret_id_o = 1'b1; + if (nmi_mode_q) begin + nmi_mode_d = 1'b0; // exit NMI mode + end + end else if (dret_insn) begin + pc_mux_o = PC_DRET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + debug_mode_d = 1'b0; + csr_restore_dret_id_o = 1'b1; + end else if (wfi_insn) begin + ctrl_fsm_ns = WAIT_SLEEP; + end else if (csr_pipe_flush && handle_irq) begin + // start handling IRQs when doing CSR-related pipeline flushes + ctrl_fsm_ns = IRQ_TAKEN; + end + end // exc_req_q + + // Entering debug mode due to either single step or debug_req. Ensure + // registers are set for exception but then enter debug handler rather + // than exception handler [Debug Spec v0.13.2, p.44] + // Leave all other signals as is to ensure CSRs and PC get set as if + // core was entering exception handler, entry to debug mode will then + // see the appropriate state and setup dpc correctly. + // If an EBREAK instruction is causing us to enter debug mode on the + // same cycle as a debug_req or single step, honor the EBREAK and + // proceed to DBG_TAKEN_ID. + if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + end + end // FLUSH + + default: begin + instr_req_o = 1'b0; + ctrl_fsm_ns = RESET; + end + endcase + end + + assign flush_id_o = flush_id; + + // signal to CSR when in debug mode + assign debug_mode_o = debug_mode_q; + + // signal to CSR when in an NMI handler (for nested exception handling) + assign nmi_mode_o = nmi_mode_q; + + /////////////////// + // Stall control // + /////////////////// + + // If high current instruction cannot complete this cycle. Either because it needs more cycles to + // finish (stall_id_i) or because the writeback stage cannot accept it yet (stall_wb_i). If there + // is no writeback stage stall_wb_i is a constant 0. + assign stall = stall_id_i | stall_wb_i; + + // signal to IF stage that ID stage is ready for next instr + assign id_in_ready_o = ~stall & ~halt_if & ~retain_id; + + // kill instr in IF-ID pipeline reg that are done, or if a + // multicycle instr causes an exception for example + // retain_id is another kind of stall, where the instr_valid bit must remain + // set (unless flush_id is set also). It cannot be factored directly into + // stall as this causes a combinational loop. + assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; + + // update registers + always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs + if (!rst_ni) begin + ctrl_fsm_cs <= RESET; + nmi_mode_q <= 1'b0; + debug_mode_q <= 1'b0; + load_err_q <= 1'b0; + store_err_q <= 1'b0; + exc_req_q <= 1'b0; + illegal_insn_q <= 1'b0; + end else begin + ctrl_fsm_cs <= ctrl_fsm_ns; + nmi_mode_q <= nmi_mode_d; + debug_mode_q <= debug_mode_d; + load_err_q <= load_err_d; + store_err_q <= store_err_d; + exc_req_q <= exc_req_d; + illegal_insn_q <= illegal_insn_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o -> instr_valid_clear_o) + + // Selectors must be known/valid. + `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside { + RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, + IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID}) + + // The speculative branch signal should be set whenever the actual branch signal is set + `ASSERT(IbexSpecImpliesSetPC, pc_set_o |-> pc_set_spec_o) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_core.sv b/flow/designs/src/ibex_sv/ibex_core.sv new file mode 100644 index 0000000000..ff5ecef864 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_core.sv @@ -0,0 +1,1457 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`ifdef RISCV_FORMAL + `define RVFI +`endif + +`include "prim_assert.sv" + +/** + * Top level module of the ibex RISC-V core + */ +module ibex_core #( + parameter bit PMPEnable = 1'b0, + parameter int unsigned PMPGranularity = 0, + parameter int unsigned PMPNumRegions = 4, + parameter int unsigned MHPMCounterNum = 0, + parameter int unsigned MHPMCounterWidth = 40, + parameter bit RV32E = 1'b0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF, + parameter bit BranchTargetALU = 1'b0, + parameter bit WritebackStage = 1'b0, + parameter bit ICache = 1'b0, + parameter bit ICacheECC = 1'b0, + parameter bit BranchPredictor = 1'b0, + parameter bit DbgTriggerEn = 1'b0, + parameter int unsigned DbgHwBreakNum = 1, + parameter bit SecureIbex = 1'b0, + parameter int unsigned DmHaltAddr = 32'h1A110800, + parameter int unsigned DmExceptionAddr = 32'h1A110808 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic test_en_i, // enable all clock gates for testing + + input logic [31:0] hart_id_i, + input logic [31:0] boot_addr_i, + + // Instruction memory interface + output logic instr_req_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + + // Data memory interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_addr_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + input logic data_err_i, + + // Interrupt inputs + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + input logic irq_nm_i, // non-maskeable interrupt + + // Debug Interface + input logic debug_req_i, + + // RISC-V Formal Interface + // Does not comply with the coding standards of _i/_o suffixes, but follows + // the convention of RISC-V Formal Interface Specification. +`ifdef RVFI + output logic rvfi_valid, + output logic [63:0] rvfi_order, + output logic [31:0] rvfi_insn, + output logic rvfi_trap, + output logic rvfi_halt, + output logic rvfi_intr, + output logic [ 1:0] rvfi_mode, + output logic [ 1:0] rvfi_ixl, + output logic [ 4:0] rvfi_rs1_addr, + output logic [ 4:0] rvfi_rs2_addr, + output logic [ 4:0] rvfi_rs3_addr, + output logic [31:0] rvfi_rs1_rdata, + output logic [31:0] rvfi_rs2_rdata, + output logic [31:0] rvfi_rs3_rdata, + output logic [ 4:0] rvfi_rd_addr, + output logic [31:0] rvfi_rd_wdata, + output logic [31:0] rvfi_pc_rdata, + output logic [31:0] rvfi_pc_wdata, + output logic [31:0] rvfi_mem_addr, + output logic [ 3:0] rvfi_mem_rmask, + output logic [ 3:0] rvfi_mem_wmask, + output logic [31:0] rvfi_mem_rdata, + output logic [31:0] rvfi_mem_wdata, +`endif + + // CPU Control Signals + input logic fetch_enable_i, + output logic alert_minor_o, + output logic alert_major_o, + output logic core_sleep_o +); + + import ibex_pkg::*; + + localparam int unsigned PMP_NUM_CHAN = 2; + localparam bit DataIndTiming = SecureIbex; + localparam bit DummyInstructions = SecureIbex; + localparam bit PCIncrCheck = SecureIbex; + localparam bit ShadowCSR = SecureIbex; + // Speculative branch option, trades-off performance against timing. + // Setting this to 1 eases branch target critical paths significantly but reduces performance + // by ~3% (based on CoreMark/MHz score). + // Set by default in the max PMP config which has the tightest budget for branch target timing. + localparam bit SpecBranch = PMPEnable & (PMPNumRegions == 16); + localparam bit RegFileECC = SecureIbex; + localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32; + + // IF/ID signals + logic dummy_instr_id; + logic instr_valid_id; + logic instr_new_id; + logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage + logic [31:0] instr_rdata_alu_id; // Instruction sampled inside IF stage (replicated to + // ease fan-out) + logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage + logic instr_is_compressed_id; + logic instr_perf_count_id; + logic instr_bp_taken_id; + logic instr_fetch_err; // Bus error on instr fetch + logic instr_fetch_err_plus2; // Instruction error is misaligned + logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage + logic [31:0] pc_if; // Program counter in IF stage + logic [31:0] pc_id; // Program counter in ID stage + logic [31:0] pc_wb; // Program counter in WB stage + logic [33:0] imd_val_d_ex[2]; // Intermediate register for multicycle Ops + logic [33:0] imd_val_q_ex[2]; // Intermediate register for multicycle Ops + logic [1:0] imd_val_we_ex; + + logic data_ind_timing; + logic dummy_instr_en; + logic [2:0] dummy_instr_mask; + logic dummy_instr_seed_en; + logic [31:0] dummy_instr_seed; + logic icache_enable; + logic icache_inval; + logic pc_mismatch_alert; + logic csr_shadow_err; + + logic instr_first_cycle_id; + logic instr_valid_clear; + logic pc_set; + logic pc_set_spec; + logic nt_branch_mispredict; + pc_sel_e pc_mux_id; // Mux selector for next PC + exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC + exc_cause_e exc_cause; // Exception cause + + logic lsu_load_err; + logic lsu_store_err; + + // LSU signals + logic lsu_addr_incr_req; + logic [31:0] lsu_addr_last; + + // Jump and branch target and decision (EX->IF) + logic [31:0] branch_target_ex; + logic branch_decision; + + // Core busy signals + logic ctrl_busy; + logic if_busy; + logic lsu_busy; + logic core_busy_d, core_busy_q; + + // Register File + logic [4:0] rf_raddr_a; + logic [31:0] rf_rdata_a; + logic [4:0] rf_raddr_b; + logic [31:0] rf_rdata_b; + logic rf_ren_a; + logic rf_ren_b; + logic [4:0] rf_waddr_wb; + logic [31:0] rf_wdata_wb; + // Writeback register write data that can be used on the forwarding path (doesn't factor in memory + // read data as this is too late for the forwarding path) + logic [31:0] rf_wdata_fwd_wb; + logic [31:0] rf_wdata_lsu; + logic rf_we_wb; + logic rf_we_lsu; + + logic [4:0] rf_waddr_id; + logic [31:0] rf_wdata_id; + logic rf_we_id; + logic rf_rd_a_wb_match; + logic rf_rd_b_wb_match; + + // ALU Control + alu_op_e alu_operator_ex; + logic [31:0] alu_operand_a_ex; + logic [31:0] alu_operand_b_ex; + + logic [31:0] bt_a_operand; + logic [31:0] bt_b_operand; + + logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU + logic [31:0] result_ex; + + // Multiplier Control + logic mult_en_ex; + logic div_en_ex; + logic mult_sel_ex; + logic div_sel_ex; + md_op_e multdiv_operator_ex; + logic [1:0] multdiv_signed_mode_ex; + logic [31:0] multdiv_operand_a_ex; + logic [31:0] multdiv_operand_b_ex; + logic multdiv_ready_id; + + // CSR control + logic csr_access; + csr_op_e csr_op; + logic csr_op_en; + csr_num_e csr_addr; + logic [31:0] csr_rdata; + logic [31:0] csr_wdata; + logic illegal_csr_insn_id; // CSR access to non-existent register, + // with wrong priviledge level, + // or missing write permissions + + // Data Memory Control + logic lsu_we; + logic [1:0] lsu_type; + logic lsu_sign_ext; + logic lsu_req; + logic [31:0] lsu_wdata; + logic lsu_req_done; + + // stall control + logic id_in_ready; + logic ex_valid; + + logic lsu_resp_valid; + logic lsu_resp_err; + + // Signals between instruction core interface and pipe (if and id stages) + logic instr_req_int; // Id stage asserts a req to instruction core interface + + // Writeback stage + logic en_wb; + wb_instr_type_e instr_type_wb; + logic ready_wb; + logic rf_write_wb; + logic outstanding_load_wb; + logic outstanding_store_wb; + + // Interrupts + logic irq_pending; + logic nmi_mode; + irqs_t irqs; + logic csr_mstatus_mie; + logic [31:0] csr_mepc, csr_depc; + + // PMP signals + logic [33:0] csr_pmp_addr [PMPNumRegions]; + pmp_cfg_t csr_pmp_cfg [PMPNumRegions]; + logic pmp_req_err [PMP_NUM_CHAN]; + logic instr_req_out; + logic data_req_out; + + logic csr_save_if; + logic csr_save_id; + logic csr_save_wb; + logic csr_restore_mret_id; + logic csr_restore_dret_id; + logic csr_save_cause; + logic csr_mtvec_init; + logic [31:0] csr_mtvec; + logic [31:0] csr_mtval; + logic csr_mstatus_tw; + priv_lvl_e priv_mode_id; + priv_lvl_e priv_mode_if; + priv_lvl_e priv_mode_lsu; + + // debug mode and dcsr configuration + logic debug_mode; + dbg_cause_e debug_cause; + logic debug_csr_save; + logic debug_single_step; + logic debug_ebreakm; + logic debug_ebreaku; + logic trigger_match; + + // signals relating to instruction movements between pipeline stages + // used by performance counters and RVFI + logic instr_id_done; + logic instr_done_wb; + + logic perf_instr_ret_wb; + logic perf_instr_ret_compressed_wb; + logic perf_iside_wait; + logic perf_dside_wait; + logic perf_mul_wait; + logic perf_div_wait; + logic perf_jump; + logic perf_branch; + logic perf_tbranch; + logic perf_load; + logic perf_store; + + // for RVFI + logic illegal_insn_id, unused_illegal_insn_id; // ID stage sees an illegal instruction + + // RISC-V Formal Interface signals +`ifdef RVFI + logic rvfi_instr_new_wb; + logic rvfi_intr_d; + logic rvfi_intr_q; + logic rvfi_set_trap_pc_d; + logic rvfi_set_trap_pc_q; + logic [31:0] rvfi_insn_id; + logic [4:0] rvfi_rs1_addr_d; + logic [4:0] rvfi_rs1_addr_q; + logic [4:0] rvfi_rs2_addr_d; + logic [4:0] rvfi_rs2_addr_q; + logic [4:0] rvfi_rs3_addr_d; + logic [31:0] rvfi_rs1_data_d; + logic [31:0] rvfi_rs1_data_q; + logic [31:0] rvfi_rs2_data_d; + logic [31:0] rvfi_rs2_data_q; + logic [31:0] rvfi_rs3_data_d; + logic [4:0] rvfi_rd_addr_wb; + logic [4:0] rvfi_rd_addr_q; + logic [4:0] rvfi_rd_addr_d; + logic [31:0] rvfi_rd_wdata_wb; + logic [31:0] rvfi_rd_wdata_d; + logic [31:0] rvfi_rd_wdata_q; + logic rvfi_rd_we_wb; + logic [3:0] rvfi_mem_mask_int; + logic [31:0] rvfi_mem_rdata_d; + logic [31:0] rvfi_mem_rdata_q; + logic [31:0] rvfi_mem_wdata_d; + logic [31:0] rvfi_mem_wdata_q; + logic [31:0] rvfi_mem_addr_d; + logic [31:0] rvfi_mem_addr_q; +`endif + + ////////////////////// + // Clock management // + ////////////////////// + + logic clk; + + logic clock_en; + + // Before going to sleep, wait for I- and D-side + // interfaces to finish ongoing operations. + assign core_busy_d = ctrl_busy | if_busy | lsu_busy; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + core_busy_q <= 1'b0; + end else begin + core_busy_q <= core_busy_d; + end + end + // capture fetch_enable_i in fetch_enable_q, once for ever + logic fetch_enable_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + fetch_enable_q <= 1'b0; + end else if (fetch_enable_i) begin + fetch_enable_q <= 1'b1; + end + end + + assign clock_en = fetch_enable_q & (core_busy_q | debug_req_i | irq_pending | irq_nm_i); + assign core_sleep_o = ~clock_en; + + // main clock gate of the core + // generates all clocks except the one for the debug unit which is + // independent + prim_clock_gating core_clock_gate_i ( + .clk_i ( clk_i ), + .en_i ( clock_en ), + .test_en_i ( test_en_i ), + .clk_o ( clk ) + ); + + ////////////// + // IF stage // + ////////////// + + ibex_if_stage #( + .DmHaltAddr ( DmHaltAddr ), + .DmExceptionAddr ( DmExceptionAddr ), + .DummyInstructions ( DummyInstructions ), + .ICache ( ICache ), + .ICacheECC ( ICacheECC ), + .PCIncrCheck ( PCIncrCheck ), + .BranchPredictor ( BranchPredictor ) + ) if_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + .boot_addr_i ( boot_addr_i ), + .req_i ( instr_req_int ), // instruction request control + + // instruction cache interface + .instr_req_o ( instr_req_out ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( pmp_req_err[PMP_I] ), + + // outputs to ID stage + .instr_valid_id_o ( instr_valid_id ), + .instr_new_id_o ( instr_new_id ), + .instr_rdata_id_o ( instr_rdata_id ), + .instr_rdata_alu_id_o ( instr_rdata_alu_id ), + .instr_rdata_c_id_o ( instr_rdata_c_id ), + .instr_is_compressed_id_o ( instr_is_compressed_id ), + .instr_bp_taken_o ( instr_bp_taken_id ), + .instr_fetch_err_o ( instr_fetch_err ), + .instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ), + .illegal_c_insn_id_o ( illegal_c_insn_id ), + .dummy_instr_id_o ( dummy_instr_id ), + .pc_if_o ( pc_if ), + .pc_id_o ( pc_id ), + + // control signals + .instr_valid_clear_i ( instr_valid_clear ), + .pc_set_i ( pc_set ), + .pc_set_spec_i ( pc_set_spec ), + .pc_mux_i ( pc_mux_id ), + .nt_branch_mispredict_i ( nt_branch_mispredict ), + .exc_pc_mux_i ( exc_pc_mux_id ), + .exc_cause ( exc_cause ), + .dummy_instr_en_i ( dummy_instr_en ), + .dummy_instr_mask_i ( dummy_instr_mask ), + .dummy_instr_seed_en_i ( dummy_instr_seed_en ), + .dummy_instr_seed_i ( dummy_instr_seed ), + .icache_enable_i ( icache_enable ), + .icache_inval_i ( icache_inval ), + + // branch targets + .branch_target_ex_i ( branch_target_ex ), + + // CSRs + .csr_mepc_i ( csr_mepc ), // exception return address + .csr_depc_i ( csr_depc ), // debug return address + .csr_mtvec_i ( csr_mtvec ), // trap-vector base address + .csr_mtvec_init_o ( csr_mtvec_init ), + + // pipeline stalls + .id_in_ready_i ( id_in_ready ), + + .pc_mismatch_alert_o ( pc_mismatch_alert ), + .if_busy_o ( if_busy ) + ); + + // Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are + // available + assign perf_iside_wait = id_in_ready & ~instr_valid_id; + + // Qualify the instruction request with PMP error + assign instr_req_o = instr_req_out & ~pmp_req_err[PMP_I]; + + ////////////// + // ID stage // + ////////////// + + ibex_id_stage #( + .RV32E ( RV32E ), + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ), + .DataIndTiming ( DataIndTiming ), + .SpecBranch ( SpecBranch ), + .WritebackStage ( WritebackStage ), + .BranchPredictor ( BranchPredictor ) + ) id_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // Processor Enable + .ctrl_busy_o ( ctrl_busy ), + .illegal_insn_o ( illegal_insn_id ), + + // from/to IF-ID pipeline register + .instr_valid_i ( instr_valid_id ), + .instr_rdata_i ( instr_rdata_id ), + .instr_rdata_alu_i ( instr_rdata_alu_id ), + .instr_rdata_c_i ( instr_rdata_c_id ), + .instr_is_compressed_i ( instr_is_compressed_id ), + .instr_bp_taken_i ( instr_bp_taken_id ), + + // Jumps and branches + .branch_decision_i ( branch_decision ), + + // IF and ID control signals + .instr_first_cycle_id_o ( instr_first_cycle_id ), + .instr_valid_clear_o ( instr_valid_clear ), + .id_in_ready_o ( id_in_ready ), + .instr_req_o ( instr_req_int ), + .pc_set_o ( pc_set ), + .pc_set_spec_o ( pc_set_spec ), + .pc_mux_o ( pc_mux_id ), + .nt_branch_mispredict_o ( nt_branch_mispredict ), + .exc_pc_mux_o ( exc_pc_mux_id ), + .exc_cause_o ( exc_cause ), + .icache_inval_o ( icache_inval ), + + .instr_fetch_err_i ( instr_fetch_err ), + .instr_fetch_err_plus2_i ( instr_fetch_err_plus2 ), + .illegal_c_insn_i ( illegal_c_insn_id ), + + .pc_id_i ( pc_id ), + + // Stalls + .ex_valid_i ( ex_valid ), + .lsu_resp_valid_i ( lsu_resp_valid ), + + .alu_operator_ex_o ( alu_operator_ex ), + .alu_operand_a_ex_o ( alu_operand_a_ex ), + .alu_operand_b_ex_o ( alu_operand_b_ex ), + + .imd_val_q_ex_o ( imd_val_q_ex ), + .imd_val_d_ex_i ( imd_val_d_ex ), + .imd_val_we_ex_i ( imd_val_we_ex ), + + .bt_a_operand_o ( bt_a_operand ), + .bt_b_operand_o ( bt_b_operand ), + + .mult_en_ex_o ( mult_en_ex ), + .div_en_ex_o ( div_en_ex ), + .mult_sel_ex_o ( mult_sel_ex ), + .div_sel_ex_o ( div_sel_ex ), + .multdiv_operator_ex_o ( multdiv_operator_ex ), + .multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ), + .multdiv_operand_a_ex_o ( multdiv_operand_a_ex ), + .multdiv_operand_b_ex_o ( multdiv_operand_b_ex ), + .multdiv_ready_id_o ( multdiv_ready_id ), + + // CSR ID/EX + .csr_access_o ( csr_access ), + .csr_op_o ( csr_op ), + .csr_op_en_o ( csr_op_en ), + .csr_save_if_o ( csr_save_if ), // control signal to save PC + .csr_save_id_o ( csr_save_id ), // control signal to save PC + .csr_save_wb_o ( csr_save_wb ), // control signal to save PC + .csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET + .csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET + .csr_save_cause_o ( csr_save_cause ), + .csr_mtval_o ( csr_mtval ), + .priv_mode_i ( priv_mode_id ), + .csr_mstatus_tw_i ( csr_mstatus_tw ), + .illegal_csr_insn_i ( illegal_csr_insn_id ), + .data_ind_timing_i ( data_ind_timing ), + + // LSU + .lsu_req_o ( lsu_req ), // to load store unit + .lsu_we_o ( lsu_we ), // to load store unit + .lsu_type_o ( lsu_type ), // to load store unit + .lsu_sign_ext_o ( lsu_sign_ext ), // to load store unit + .lsu_wdata_o ( lsu_wdata ), // to load store unit + .lsu_req_done_i ( lsu_req_done ), // from load store unit + + .lsu_addr_incr_req_i ( lsu_addr_incr_req ), + .lsu_addr_last_i ( lsu_addr_last ), + + .lsu_load_err_i ( lsu_load_err ), + .lsu_store_err_i ( lsu_store_err ), + + // Interrupt Signals + .csr_mstatus_mie_i ( csr_mstatus_mie ), + .irq_pending_i ( irq_pending ), + .irqs_i ( irqs ), + .irq_nm_i ( irq_nm_i ), + .nmi_mode_o ( nmi_mode ), + + // Debug Signal + .debug_mode_o ( debug_mode ), + .debug_cause_o ( debug_cause ), + .debug_csr_save_o ( debug_csr_save ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step ), + .debug_ebreakm_i ( debug_ebreakm ), + .debug_ebreaku_i ( debug_ebreaku ), + .trigger_match_i ( trigger_match ), + + // write data to commit in the register file + .result_ex_i ( result_ex ), + .csr_rdata_i ( csr_rdata ), + + .rf_raddr_a_o ( rf_raddr_a ), + .rf_rdata_a_i ( rf_rdata_a ), + .rf_raddr_b_o ( rf_raddr_b ), + .rf_rdata_b_i ( rf_rdata_b ), + .rf_ren_a_o ( rf_ren_a ), + .rf_ren_b_o ( rf_ren_b ), + .rf_waddr_id_o ( rf_waddr_id ), + .rf_wdata_id_o ( rf_wdata_id ), + .rf_we_id_o ( rf_we_id ), + .rf_rd_a_wb_match_o ( rf_rd_a_wb_match ), + .rf_rd_b_wb_match_o ( rf_rd_b_wb_match ), + + .rf_waddr_wb_i ( rf_waddr_wb ), + .rf_wdata_fwd_wb_i ( rf_wdata_fwd_wb ), + .rf_write_wb_i ( rf_write_wb ), + + .en_wb_o ( en_wb ), + .instr_type_wb_o ( instr_type_wb ), + .instr_perf_count_id_o ( instr_perf_count_id ), + .ready_wb_i ( ready_wb ), + .outstanding_load_wb_i ( outstanding_load_wb ), + .outstanding_store_wb_i ( outstanding_store_wb ), + + // Performance Counters + .perf_jump_o ( perf_jump ), + .perf_branch_o ( perf_branch ), + .perf_tbranch_o ( perf_tbranch ), + .perf_dside_wait_o ( perf_dside_wait ), + .perf_mul_wait_o ( perf_mul_wait ), + .perf_div_wait_o ( perf_div_wait ), + .instr_id_done_o ( instr_id_done ) + ); + + // for RVFI only + assign unused_illegal_insn_id = illegal_insn_id; + + ibex_ex_block #( + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ) + ) ex_block_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // ALU signal from ID stage + .alu_operator_i ( alu_operator_ex ), + .alu_operand_a_i ( alu_operand_a_ex ), + .alu_operand_b_i ( alu_operand_b_ex ), + .alu_instr_first_cycle_i ( instr_first_cycle_id ), + + // Branch target ALU signal from ID stage + .bt_a_operand_i ( bt_a_operand ), + .bt_b_operand_i ( bt_b_operand ), + + // Multipler/Divider signal from ID stage + .multdiv_operator_i ( multdiv_operator_ex ), + .mult_en_i ( mult_en_ex ), + .div_en_i ( div_en_ex ), + .mult_sel_i ( mult_sel_ex ), + .div_sel_i ( div_sel_ex ), + .multdiv_signed_mode_i ( multdiv_signed_mode_ex ), + .multdiv_operand_a_i ( multdiv_operand_a_ex ), + .multdiv_operand_b_i ( multdiv_operand_b_ex ), + .multdiv_ready_id_i ( multdiv_ready_id ), + .data_ind_timing_i ( data_ind_timing ), + + // Intermediate value register + .imd_val_we_o ( imd_val_we_ex ), + .imd_val_d_o ( imd_val_d_ex ), + .imd_val_q_i ( imd_val_q_ex ), + + // Outputs + .alu_adder_result_ex_o ( alu_adder_result_ex ), // to LSU + .result_ex_o ( result_ex ), // to ID + + .branch_target_o ( branch_target_ex ), // to IF + .branch_decision_o ( branch_decision ), // to ID + + .ex_valid_o ( ex_valid ) + ); + + ///////////////////// + // Load/store unit // + ///////////////////// + + assign data_req_o = data_req_out & ~pmp_req_err[PMP_D]; + assign lsu_resp_err = lsu_load_err | lsu_store_err; + + ibex_load_store_unit load_store_unit_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // data interface + .data_req_o ( data_req_out ), + .data_gnt_i ( data_gnt_i ), + .data_rvalid_i ( data_rvalid_i ), + .data_err_i ( data_err_i ), + .data_pmp_err_i ( pmp_req_err[PMP_D] ), + + .data_addr_o ( data_addr_o ), + .data_we_o ( data_we_o ), + .data_be_o ( data_be_o ), + .data_wdata_o ( data_wdata_o ), + .data_rdata_i ( data_rdata_i ), + + // signals to/from ID/EX stage + .lsu_we_i ( lsu_we ), + .lsu_type_i ( lsu_type ), + .lsu_wdata_i ( lsu_wdata ), + .lsu_sign_ext_i ( lsu_sign_ext ), + + .lsu_rdata_o ( rf_wdata_lsu ), + .lsu_rdata_valid_o ( rf_we_lsu ), + .lsu_req_i ( lsu_req ), + .lsu_req_done_o ( lsu_req_done ), + + .adder_result_ex_i ( alu_adder_result_ex ), + + .addr_incr_req_o ( lsu_addr_incr_req ), + .addr_last_o ( lsu_addr_last ), + + + .lsu_resp_valid_o ( lsu_resp_valid ), + + // exception signals + .load_err_o ( lsu_load_err ), + .store_err_o ( lsu_store_err ), + + .busy_o ( lsu_busy ), + + .perf_load_o ( perf_load ), + .perf_store_o ( perf_store ) + ); + + ibex_wb_stage #( + .WritebackStage ( WritebackStage ) + ) wb_stage_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + .en_wb_i ( en_wb ), + .instr_type_wb_i ( instr_type_wb ), + .pc_id_i ( pc_id ), + .instr_is_compressed_id_i ( instr_is_compressed_id ), + .instr_perf_count_id_i ( instr_perf_count_id ), + + .ready_wb_o ( ready_wb ), + .rf_write_wb_o ( rf_write_wb ), + .outstanding_load_wb_o ( outstanding_load_wb ), + .outstanding_store_wb_o ( outstanding_store_wb ), + .pc_wb_o ( pc_wb ), + .perf_instr_ret_wb_o ( perf_instr_ret_wb ), + .perf_instr_ret_compressed_wb_o ( perf_instr_ret_compressed_wb ), + + .rf_waddr_id_i ( rf_waddr_id ), + .rf_wdata_id_i ( rf_wdata_id ), + .rf_we_id_i ( rf_we_id ), + + .rf_wdata_lsu_i ( rf_wdata_lsu ), + .rf_we_lsu_i ( rf_we_lsu ), + + .rf_wdata_fwd_wb_o ( rf_wdata_fwd_wb ), + + .rf_waddr_wb_o ( rf_waddr_wb ), + .rf_wdata_wb_o ( rf_wdata_wb ), + .rf_we_wb_o ( rf_we_wb ), + + .lsu_resp_valid_i ( lsu_resp_valid ), + .lsu_resp_err_i ( lsu_resp_err ), + + .instr_done_wb_o ( instr_done_wb ) + ); + + /////////////////////// + // Register file ECC // + /////////////////////// + + logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc; + logic [RegFileDataWidth-1:0] rf_rdata_a_ecc; + logic [RegFileDataWidth-1:0] rf_rdata_b_ecc; + logic rf_ecc_err_comb; + + if (RegFileECC) begin : gen_regfile_ecc + + logic [1:0] rf_ecc_err_a, rf_ecc_err_b; + logic rf_ecc_err_a_id, rf_ecc_err_b_id; + + // ECC checkbit generation for regiter file wdata + prim_secded_39_32_enc regfile_ecc_enc ( + .in (rf_wdata_wb), + .out (rf_wdata_wb_ecc) + ); + + // ECC checking on register file rdata + prim_secded_39_32_dec regfile_ecc_dec_a ( + .in (rf_rdata_a_ecc), + .d_o (), + .syndrome_o (), + .err_o (rf_ecc_err_a) + ); + prim_secded_39_32_dec regfile_ecc_dec_b ( + .in (rf_rdata_b_ecc), + .d_o (), + .syndrome_o (), + .err_o (rf_ecc_err_b) + ); + + // Assign read outputs - no error correction, just trigger an alert + assign rf_rdata_a = rf_rdata_a_ecc[31:0]; + assign rf_rdata_b = rf_rdata_b_ecc[31:0]; + + // Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal + assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~rf_rd_a_wb_match; + assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~rf_rd_b_wb_match; + + // Combined error + assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id); + + end else begin : gen_no_regfile_ecc + logic unused_rf_ren_a, unused_rf_ren_b; + logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match; + + assign unused_rf_ren_a = rf_ren_a; + assign unused_rf_ren_b = rf_ren_b; + assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match; + assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match; + assign rf_wdata_wb_ecc = rf_wdata_wb; + assign rf_rdata_a = rf_rdata_a_ecc; + assign rf_rdata_b = rf_rdata_b_ecc; + assign rf_ecc_err_comb = 1'b0; + end + + if (RegFile == RegFileFF) begin : gen_regfile_ff + ibex_register_file_ff #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga + ibex_register_file_fpga #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end else if (RegFile == RegFileLatch) begin : gen_regfile_latch + ibex_register_file_latch #( + .RV32E ( RV32E ), + .DataWidth ( RegFileDataWidth ), + .DummyInstructions ( DummyInstructions ) + ) register_file_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( test_en_i ), + .dummy_instr_id_i ( dummy_instr_id ), + + .raddr_a_i ( rf_raddr_a ), + .rdata_a_o ( rf_rdata_a_ecc ), + .raddr_b_i ( rf_raddr_b ), + .rdata_b_o ( rf_rdata_b_ecc ), + .waddr_a_i ( rf_waddr_wb ), + .wdata_a_i ( rf_wdata_wb_ecc ), + .we_a_i ( rf_we_wb ) + ); + end + + /////////////////// + // Alert outputs // + /////////////////// + + // Minor alert - core is in a recoverable state + // TODO add I$ ECC errors here + assign alert_minor_o = 1'b0; + + // Major alert - core is unrecoverable + assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert | csr_shadow_err; + + `ASSERT_KNOWN(IbexAlertMinorX, alert_minor_o) + `ASSERT_KNOWN(IbexAlertMajorX, alert_major_o) + + // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included + `ifdef INC_ASSERT + // Signals used for assertions only + logic outstanding_load_resp; + logic outstanding_store_resp; + + logic outstanding_load_id; + logic outstanding_store_id; + + assign outstanding_load_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & + ~id_stage_i.lsu_we; + assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec & + id_stage_i.lsu_we; + + if (WritebackStage) begin : gen_wb_stage + // When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can + // see a response before it moves to WB when it is unaligned otherwise we should only see + // a response when load/store is in WB. + assign outstanding_load_resp = outstanding_load_wb | + (outstanding_load_id & load_store_unit_i.split_misaligned_access); + + assign outstanding_store_resp = outstanding_store_wb | + (outstanding_store_id & load_store_unit_i.split_misaligned_access); + + // When writing back the result of a load, the load must have made it to writeback + `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni) + end else begin : gen_no_wb_stage + // Without writeback stage only look into whether load or store is in ID to determine if + // a response is expected. + assign outstanding_load_resp = outstanding_load_id; + assign outstanding_store_resp = outstanding_store_id; + + `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni) + end + + `ASSERT(NoMemResponseWithoutPendingAccess, + data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni) + `endif + + //////////////////////// + // RF (Register File) // + //////////////////////// +`ifdef RVFI + assign rvfi_rd_addr_wb = rf_waddr_wb; + assign rvfi_rd_wdata_wb = rf_we_wb ? rf_wdata_wb : rf_wdata_lsu; + assign rvfi_rd_we_wb = rf_we_wb | rf_we_lsu; +`endif + + + ///////////////////////////////////////// + // CSRs (Control and Status Registers) // + ///////////////////////////////////////// + + assign csr_wdata = alu_operand_a_ex; + assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0); + + ibex_cs_registers #( + .DbgTriggerEn ( DbgTriggerEn ), + .DbgHwBreakNum ( DbgHwBreakNum ), + .DataIndTiming ( DataIndTiming ), + .DummyInstructions ( DummyInstructions ), + .ShadowCSR ( ShadowCSR ), + .ICache ( ICache ), + .MHPMCounterNum ( MHPMCounterNum ), + .MHPMCounterWidth ( MHPMCounterWidth ), + .PMPEnable ( PMPEnable ), + .PMPGranularity ( PMPGranularity ), + .PMPNumRegions ( PMPNumRegions ), + .RV32E ( RV32E ), + .RV32M ( RV32M ) + ) cs_registers_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + + // Hart ID from outside + .hart_id_i ( hart_id_i ), + .priv_mode_id_o ( priv_mode_id ), + .priv_mode_if_o ( priv_mode_if ), + .priv_mode_lsu_o ( priv_mode_lsu ), + + // mtvec + .csr_mtvec_o ( csr_mtvec ), + .csr_mtvec_init_i ( csr_mtvec_init ), + .boot_addr_i ( boot_addr_i ), + + // Interface to CSRs ( SRAM like ) + .csr_access_i ( csr_access ), + .csr_addr_i ( csr_addr ), + .csr_wdata_i ( csr_wdata ), + .csr_op_i ( csr_op ), + .csr_op_en_i ( csr_op_en ), + .csr_rdata_o ( csr_rdata ), + + // Interrupt related control signals + .irq_software_i ( irq_software_i ), + .irq_timer_i ( irq_timer_i ), + .irq_external_i ( irq_external_i ), + .irq_fast_i ( irq_fast_i ), + .nmi_mode_i ( nmi_mode ), + .irq_pending_o ( irq_pending ), + .irqs_o ( irqs ), + .csr_mstatus_mie_o ( csr_mstatus_mie ), + .csr_mstatus_tw_o ( csr_mstatus_tw ), + .csr_mepc_o ( csr_mepc ), + + // PMP + .csr_pmp_cfg_o ( csr_pmp_cfg ), + .csr_pmp_addr_o ( csr_pmp_addr ), + + // debug + .csr_depc_o ( csr_depc ), + .debug_mode_i ( debug_mode ), + .debug_cause_i ( debug_cause ), + .debug_csr_save_i ( debug_csr_save ), + .debug_single_step_o ( debug_single_step ), + .debug_ebreakm_o ( debug_ebreakm ), + .debug_ebreaku_o ( debug_ebreaku ), + .trigger_match_o ( trigger_match ), + + .pc_if_i ( pc_if ), + .pc_id_i ( pc_id ), + .pc_wb_i ( pc_wb ), + + .data_ind_timing_o ( data_ind_timing ), + .dummy_instr_en_o ( dummy_instr_en ), + .dummy_instr_mask_o ( dummy_instr_mask ), + .dummy_instr_seed_en_o ( dummy_instr_seed_en ), + .dummy_instr_seed_o ( dummy_instr_seed ), + .icache_enable_o ( icache_enable ), + .csr_shadow_err_o ( csr_shadow_err ), + + .csr_save_if_i ( csr_save_if ), + .csr_save_id_i ( csr_save_id ), + .csr_save_wb_i ( csr_save_wb ), + .csr_restore_mret_i ( csr_restore_mret_id ), + .csr_restore_dret_i ( csr_restore_dret_id ), + .csr_save_cause_i ( csr_save_cause ), + .csr_mcause_i ( exc_cause ), + .csr_mtval_i ( csr_mtval ), + .illegal_csr_insn_o ( illegal_csr_insn_id ), + + // performance counter related signals + .instr_ret_i ( perf_instr_ret_wb ), + .instr_ret_compressed_i ( perf_instr_ret_compressed_wb ), + .iside_wait_i ( perf_iside_wait ), + .jump_i ( perf_jump ), + .branch_i ( perf_branch ), + .branch_taken_i ( perf_tbranch ), + .mem_load_i ( perf_load ), + .mem_store_i ( perf_store ), + .dside_wait_i ( perf_dside_wait ), + .mul_wait_i ( perf_mul_wait ), + .div_wait_i ( perf_div_wait ) + ); + + // These assertions are in top-level as instr_valid_id required as the enable term + `ASSERT(IbexCsrOpValid, instr_valid_id |-> csr_op inside { + CSR_OP_READ, + CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR + }) + `ASSERT_KNOWN_IF(IbexCsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_op_en) + + if (PMPEnable) begin : g_pmp + logic [33:0] pmp_req_addr [PMP_NUM_CHAN]; + pmp_req_e pmp_req_type [PMP_NUM_CHAN]; + priv_lvl_e pmp_priv_lvl [PMP_NUM_CHAN]; + + assign pmp_req_addr[PMP_I] = {2'b00,instr_addr_o[31:0]}; + assign pmp_req_type[PMP_I] = PMP_ACC_EXEC; + assign pmp_priv_lvl[PMP_I] = priv_mode_if; + assign pmp_req_addr[PMP_D] = {2'b00,data_addr_o[31:0]}; + assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ; + assign pmp_priv_lvl[PMP_D] = priv_mode_lsu; + + ibex_pmp #( + .PMPGranularity ( PMPGranularity ), + .PMPNumChan ( PMP_NUM_CHAN ), + .PMPNumRegions ( PMPNumRegions ) + ) pmp_i ( + .clk_i ( clk ), + .rst_ni ( rst_ni ), + // Interface to CSRs + .csr_pmp_cfg_i ( csr_pmp_cfg ), + .csr_pmp_addr_i ( csr_pmp_addr ), + .priv_mode_i ( pmp_priv_lvl ), + // Access checking channels + .pmp_req_addr_i ( pmp_req_addr ), + .pmp_req_type_i ( pmp_req_type ), + .pmp_req_err_o ( pmp_req_err ) + ); + end else begin : g_no_pmp + // Unused signal tieoff + priv_lvl_e unused_priv_lvl_if, unused_priv_lvl_ls; + logic [33:0] unused_csr_pmp_addr [PMPNumRegions]; + pmp_cfg_t unused_csr_pmp_cfg [PMPNumRegions]; + assign unused_priv_lvl_if = priv_mode_if; + assign unused_priv_lvl_ls = priv_mode_lsu; + assign unused_csr_pmp_addr = csr_pmp_addr; + assign unused_csr_pmp_cfg = csr_pmp_cfg; + + // Output tieoff + assign pmp_req_err[PMP_I] = 1'b0; + assign pmp_req_err[PMP_D] = 1'b0; + end + +`ifdef RVFI + // When writeback stage is present RVFI information is emitted when instruction is finished in + // third stage but some information must be captured whilst the instruction is in the second + // stage. Without writeback stage RVFI information is all emitted when instruction retires in + // second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single + // set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb + // => RVFI_out) + localparam int RVFI_STAGES = WritebackStage ? 2 : 1; + + logic rvfi_stage_valid [RVFI_STAGES]; + logic [63:0] rvfi_stage_order [RVFI_STAGES]; + logic [31:0] rvfi_stage_insn [RVFI_STAGES]; + logic rvfi_stage_trap [RVFI_STAGES]; + logic rvfi_stage_halt [RVFI_STAGES]; + logic rvfi_stage_intr [RVFI_STAGES]; + logic [ 1:0] rvfi_stage_mode [RVFI_STAGES]; + logic [ 1:0] rvfi_stage_ixl [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs1_addr [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs2_addr [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rs3_addr [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs1_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs2_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_rs3_rdata [RVFI_STAGES]; + logic [ 4:0] rvfi_stage_rd_addr [RVFI_STAGES]; + logic [31:0] rvfi_stage_rd_wdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_pc_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_pc_wdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_addr [RVFI_STAGES]; + logic [ 3:0] rvfi_stage_mem_rmask [RVFI_STAGES]; + logic [ 3:0] rvfi_stage_mem_wmask [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_rdata [RVFI_STAGES]; + logic [31:0] rvfi_stage_mem_wdata [RVFI_STAGES]; + + logic rvfi_stage_valid_d [RVFI_STAGES]; + + assign rvfi_valid = rvfi_stage_valid [RVFI_STAGES-1]; + assign rvfi_order = rvfi_stage_order [RVFI_STAGES-1]; + assign rvfi_insn = rvfi_stage_insn [RVFI_STAGES-1]; + assign rvfi_trap = rvfi_stage_trap [RVFI_STAGES-1]; + assign rvfi_halt = rvfi_stage_halt [RVFI_STAGES-1]; + assign rvfi_intr = rvfi_stage_intr [RVFI_STAGES-1]; + assign rvfi_mode = rvfi_stage_mode [RVFI_STAGES-1]; + assign rvfi_ixl = rvfi_stage_ixl [RVFI_STAGES-1]; + assign rvfi_rs1_addr = rvfi_stage_rs1_addr [RVFI_STAGES-1]; + assign rvfi_rs2_addr = rvfi_stage_rs2_addr [RVFI_STAGES-1]; + assign rvfi_rs3_addr = rvfi_stage_rs3_addr [RVFI_STAGES-1]; + assign rvfi_rs1_rdata = rvfi_stage_rs1_rdata[RVFI_STAGES-1]; + assign rvfi_rs2_rdata = rvfi_stage_rs2_rdata[RVFI_STAGES-1]; + assign rvfi_rs3_rdata = rvfi_stage_rs3_rdata[RVFI_STAGES-1]; + assign rvfi_rd_addr = rvfi_stage_rd_addr [RVFI_STAGES-1]; + assign rvfi_rd_wdata = rvfi_stage_rd_wdata [RVFI_STAGES-1]; + assign rvfi_pc_rdata = rvfi_stage_pc_rdata [RVFI_STAGES-1]; + assign rvfi_pc_wdata = rvfi_stage_pc_wdata [RVFI_STAGES-1]; + assign rvfi_mem_addr = rvfi_stage_mem_addr [RVFI_STAGES-1]; + assign rvfi_mem_rmask = rvfi_stage_mem_rmask[RVFI_STAGES-1]; + assign rvfi_mem_wmask = rvfi_stage_mem_wmask[RVFI_STAGES-1]; + assign rvfi_mem_rdata = rvfi_stage_mem_rdata[RVFI_STAGES-1]; + assign rvfi_mem_wdata = rvfi_stage_mem_wdata[RVFI_STAGES-1]; + + if (WritebackStage) begin : gen_rvfi_wb_stage + logic unused_instr_new_id; + + assign unused_instr_new_id = instr_new_id; + + // With writeback stage first RVFI stage buffers instruction information captured in ID/EX + // awaiting instruction retirement and RF Write data/Mem read data whilst instruction is in WB + // So first stage becomes valid when instruction leaves ID/EX stage and remains valid until + // instruction leaves WB + assign rvfi_stage_valid_d[0] = (instr_id_done & ~dummy_instr_id) | + (rvfi_stage_valid[0] & ~instr_done_wb); + // Second stage is output stage so simple valid cycle after instruction leaves WB (and so has + // retired) + assign rvfi_stage_valid_d[1] = instr_done_wb; + + // Signal new instruction in WB cycle after instruction leaves ID/EX (to enter WB) + logic rvfi_instr_new_wb_q; + + assign rvfi_instr_new_wb = rvfi_instr_new_wb_q; + + always_ff @(posedge clk or negedge rst_ni) begin + if (~rst_ni) begin + rvfi_instr_new_wb_q <= 0; + end else begin + rvfi_instr_new_wb_q <= instr_id_done; + end + end + end else begin : gen_rvfi_no_wb_stage + // Without writeback stage first RVFI stage is output stage so simply valid the cycle after + // instruction leaves ID/EX (and so has retired) + assign rvfi_stage_valid_d[0] = instr_id_done & ~dummy_instr_id; + // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly + // setup register write signals + assign rvfi_instr_new_wb = instr_new_id; + end + + for (genvar i = 0;i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_stage_halt[i] <= '0; + rvfi_stage_trap[i] <= '0; + rvfi_stage_intr[i] <= '0; + rvfi_stage_order[i] <= '0; + rvfi_stage_insn[i] <= '0; + rvfi_stage_mode[i] <= {PRIV_LVL_M}; + rvfi_stage_ixl[i] <= CSR_MISA_MXL; + rvfi_stage_rs1_addr[i] <= '0; + rvfi_stage_rs2_addr[i] <= '0; + rvfi_stage_rs3_addr[i] <= '0; + rvfi_stage_pc_rdata[i] <= '0; + rvfi_stage_pc_wdata[i] <= '0; + rvfi_stage_mem_rmask[i] <= '0; + rvfi_stage_mem_wmask[i] <= '0; + rvfi_stage_valid[i] <= '0; + rvfi_stage_rs1_rdata[i] <= '0; + rvfi_stage_rs2_rdata[i] <= '0; + rvfi_stage_rs3_rdata[i] <= '0; + rvfi_stage_rd_wdata[i] <= '0; + rvfi_stage_rd_addr[i] <= '0; + rvfi_stage_mem_rdata[i] <= '0; + rvfi_stage_mem_wdata[i] <= '0; + rvfi_stage_mem_addr[i] <= '0; + end else begin + rvfi_stage_valid[i] <= rvfi_stage_valid_d[i]; + + if (i == 0) begin + if(instr_id_done) begin + rvfi_stage_halt[i] <= '0; + rvfi_stage_trap[i] <= illegal_insn_id; + rvfi_stage_intr[i] <= rvfi_intr_d; + rvfi_stage_order[i] <= rvfi_stage_order[i] + 64'(rvfi_stage_valid_d[i]); + rvfi_stage_insn[i] <= rvfi_insn_id; + rvfi_stage_mode[i] <= {priv_mode_id}; + rvfi_stage_ixl[i] <= CSR_MISA_MXL; + rvfi_stage_rs1_addr[i] <= rvfi_rs1_addr_d; + rvfi_stage_rs2_addr[i] <= rvfi_rs2_addr_d; + rvfi_stage_rs3_addr[i] <= rvfi_rs3_addr_d; + rvfi_stage_pc_rdata[i] <= pc_id; + rvfi_stage_pc_wdata[i] <= pc_set ? branch_target_ex : pc_if; + rvfi_stage_mem_rmask[i] <= rvfi_mem_mask_int; + rvfi_stage_mem_wmask[i] <= data_we_o ? rvfi_mem_mask_int : 4'b0000; + rvfi_stage_rs1_rdata[i] <= rvfi_rs1_data_d; + rvfi_stage_rs2_rdata[i] <= rvfi_rs2_data_d; + rvfi_stage_rs3_rdata[i] <= rvfi_rs3_data_d; + rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d; + rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d; + rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d; + rvfi_stage_mem_wdata[i] <= rvfi_mem_wdata_d; + rvfi_stage_mem_addr[i] <= rvfi_mem_addr_d; + end + end else begin + if(instr_done_wb) begin + rvfi_stage_halt[i] <= rvfi_stage_halt[i-1]; + rvfi_stage_trap[i] <= rvfi_stage_trap[i-1]; + rvfi_stage_intr[i] <= rvfi_stage_intr[i-1]; + rvfi_stage_order[i] <= rvfi_stage_order[i-1]; + rvfi_stage_insn[i] <= rvfi_stage_insn[i-1]; + rvfi_stage_mode[i] <= rvfi_stage_mode[i-1]; + rvfi_stage_ixl[i] <= rvfi_stage_ixl[i-1]; + rvfi_stage_rs1_addr[i] <= rvfi_stage_rs1_addr[i-1]; + rvfi_stage_rs2_addr[i] <= rvfi_stage_rs2_addr[i-1]; + rvfi_stage_rs3_addr[i] <= rvfi_stage_rs3_addr[i-1]; + rvfi_stage_pc_rdata[i] <= rvfi_stage_pc_rdata[i-1]; + rvfi_stage_pc_wdata[i] <= rvfi_stage_pc_wdata[i-1]; + rvfi_stage_mem_rmask[i] <= rvfi_stage_mem_rmask[i-1]; + rvfi_stage_mem_wmask[i] <= rvfi_stage_mem_wmask[i-1]; + rvfi_stage_rs1_rdata[i] <= rvfi_stage_rs1_rdata[i-1]; + rvfi_stage_rs2_rdata[i] <= rvfi_stage_rs2_rdata[i-1]; + rvfi_stage_rs3_rdata[i] <= rvfi_stage_rs3_rdata[i-1]; + rvfi_stage_mem_wdata[i] <= rvfi_stage_mem_wdata[i-1]; + rvfi_stage_mem_addr[i] <= rvfi_stage_mem_addr[i-1]; + + // For 2 RVFI_STAGES/Writeback Stage ignore first stage flops for rd_addr, rd_wdata and + // mem_rdata. For RF write addr/data actual write happens in writeback so capture + // address/data there. For mem_rdata that is only available from the writeback stage. + // Previous stage flops still exist in RTL as they are used by the non writeback config + rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d; + rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d; + rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d; + end + end + end + end + end + + + // Memory adddress/write data available first cycle of ld/st instruction from register read + always_comb begin + if (instr_first_cycle_id) begin + rvfi_mem_addr_d = alu_adder_result_ex; + rvfi_mem_wdata_d = lsu_wdata; + end else begin + rvfi_mem_addr_d = rvfi_mem_addr_q; + rvfi_mem_wdata_d = rvfi_mem_wdata_q; + end + end + + // Capture read data from LSU when it becomes valid + always_comb begin + if (lsu_resp_valid) begin + rvfi_mem_rdata_d = rf_wdata_lsu; + end else begin + rvfi_mem_rdata_d = rvfi_mem_rdata_q; + end + end + + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_mem_addr_q <= '0; + rvfi_mem_rdata_q <= '0; + rvfi_mem_wdata_q <= '0; + end else begin + rvfi_mem_addr_q <= rvfi_mem_addr_d; + rvfi_mem_rdata_q <= rvfi_mem_rdata_d; + rvfi_mem_wdata_q <= rvfi_mem_wdata_d; + end + end + // Byte enable based on data type + always_comb begin + unique case (lsu_type) + 2'b00: rvfi_mem_mask_int = 4'b1111; + 2'b01: rvfi_mem_mask_int = 4'b0011; + 2'b10: rvfi_mem_mask_int = 4'b0001; + default: rvfi_mem_mask_int = 4'b0000; + endcase + end + + always_comb begin + if (instr_is_compressed_id) begin + rvfi_insn_id = {16'b0, instr_rdata_c_id}; + end else begin + rvfi_insn_id = instr_rdata_id; + end + end + + // Source registers 1 and 2 are read in the first instruction cycle + // Source register 3 is read in the second instruction cycle. + always_comb begin + if (instr_first_cycle_id) begin + rvfi_rs1_data_d = rf_ren_a ? multdiv_operand_a_ex : '0; + rvfi_rs1_addr_d = rf_ren_a ? rf_raddr_a : '0; + rvfi_rs2_data_d = rf_ren_b ? multdiv_operand_b_ex : '0; + rvfi_rs2_addr_d = rf_ren_b ? rf_raddr_b : '0; + rvfi_rs3_data_d = '0; + rvfi_rs3_addr_d = '0; + end else begin + rvfi_rs1_data_d = rvfi_rs1_data_q; + rvfi_rs1_addr_d = rvfi_rs1_addr_q; + rvfi_rs2_data_d = rvfi_rs2_data_q; + rvfi_rs2_addr_d = rvfi_rs2_addr_q; + rvfi_rs3_data_d = multdiv_operand_a_ex; + rvfi_rs3_addr_d = rf_raddr_a; + end + end + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_rs1_data_q <= '0; + rvfi_rs1_addr_q <= '0; + rvfi_rs2_data_q <= '0; + rvfi_rs2_addr_q <= '0; + + end else begin + rvfi_rs1_data_q <= rvfi_rs1_data_d; + rvfi_rs1_addr_q <= rvfi_rs1_addr_d; + rvfi_rs2_data_q <= rvfi_rs2_data_d; + rvfi_rs2_addr_q <= rvfi_rs2_addr_d; + end + end + + always_comb begin + if(rvfi_rd_we_wb) begin + // Capture address/data of write to register file + rvfi_rd_addr_d = rvfi_rd_addr_wb; + // If writing to x0 zero write data as required by RVFI specification + if(rvfi_rd_addr_wb == 5'b0) begin + rvfi_rd_wdata_d = '0; + end else begin + rvfi_rd_wdata_d = rvfi_rd_wdata_wb; + end + end else if(rvfi_instr_new_wb) begin + // If no RF write but new instruction in Writeback (when present) or ID/EX (when no writeback + // stage present) then zero RF write address/data as required by RVFI specification + rvfi_rd_addr_d = '0; + rvfi_rd_wdata_d = '0; + end else begin + // Otherwise maintain previous value + rvfi_rd_addr_d = rvfi_rd_addr_q; + rvfi_rd_wdata_d = rvfi_rd_wdata_q; + end + end + + // RD write register is refreshed only once per cycle and + // then it is kept stable for the cycle. + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_rd_addr_q <= '0; + rvfi_rd_wdata_q <= '0; + end else begin + rvfi_rd_addr_q <= rvfi_rd_addr_d; + rvfi_rd_wdata_q <= rvfi_rd_wdata_d; + end + end + + // rvfi_intr must be set for first instruction that is part of a trap handler. + // On the first cycle of a new instruction see if a trap PC was set by the previous instruction, + // otherwise maintain value. + assign rvfi_intr_d = instr_first_cycle_id ? rvfi_set_trap_pc_q : rvfi_intr_q; + + always_comb begin + rvfi_set_trap_pc_d = rvfi_set_trap_pc_q; + + if (pc_set && pc_mux_id == PC_EXC && + (exc_pc_mux_id == EXC_PC_EXC || exc_pc_mux_id == EXC_PC_IRQ)) begin + // PC is set to enter a trap handler + rvfi_set_trap_pc_d = 1'b1; + end else if (rvfi_set_trap_pc_q && instr_id_done) begin + // first instruction has been executed after PC is set to trap handler + rvfi_set_trap_pc_d = 1'b0; + end + end + + always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) begin + rvfi_set_trap_pc_q <= 1'b0; + rvfi_intr_q <= 1'b0; + end else begin + rvfi_set_trap_pc_q <= rvfi_set_trap_pc_d; + rvfi_intr_q <= rvfi_intr_d; + end + end + +`else + logic unused_instr_new_id, unused_instr_done_wb; + assign unused_instr_new_id = instr_new_id; + assign unused_instr_done_wb = instr_done_wb; +`endif + + // Certain parameter combinations are not supported + `ASSERT_INIT(IllegalParamSecure, !(SecureIbex && (RV32M == RV32MNone))) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_counter.sv b/flow/designs/src/ibex_sv/ibex_counter.sv new file mode 100644 index 0000000000..0091d5af30 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_counter.sv @@ -0,0 +1,82 @@ +module ibex_counter #( + parameter int CounterWidth = 32 +) ( + input logic clk_i, + input logic rst_ni, + + input logic counter_inc_i, + input logic counterh_we_i, + input logic counter_we_i, + input logic [31:0] counter_val_i, + output logic [63:0] counter_val_o +); + + logic [63:0] counter; + logic [CounterWidth-1:0] counter_upd; + logic [63:0] counter_load; + logic we; + logic [CounterWidth-1:0] counter_d; + + // Update + always_comb begin + + // Write + we = counter_we_i | counterh_we_i; + counter_load[63:32] = counter[63:32]; + counter_load[31:0] = counter_val_i; + if (counterh_we_i) begin + counter_load[63:32] = counter_val_i; + counter_load[31:0] = counter[31:0]; + end + + // Increment + counter_upd = counter[CounterWidth-1:0] + {{CounterWidth-1{1'b0}},1'b1}; + + // Next value logic + if (we) begin + counter_d = counter_load[CounterWidth-1:0]; + end else if (counter_inc_i)begin + counter_d = counter_upd[CounterWidth-1:0]; + end else begin + counter_d = counter[CounterWidth-1:0]; + end + end + +`ifdef FPGA_XILINX + // Set DSP pragma for supported xilinx FPGAs + localparam int DspPragma = CounterWidth < 49 ? "yes" : "no"; + (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q; + + // DSP output register requires synchronous reset. + `define COUNTER_FLOP_RST posedge clk_i +`else + logic [CounterWidth-1:0] counter_q; + + `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni +`endif + + // Counter flop + always_ff @(`COUNTER_FLOP_RST) begin + if (!rst_ni) begin + counter_q <= '0; + end else begin + counter_q <= counter_d; + end + end + + if (CounterWidth < 64) begin : g_counter_narrow + logic [63:CounterWidth] unused_counter_load; + + assign counter[CounterWidth-1:0] = counter_q; + assign counter[63:CounterWidth] = '0; + assign unused_counter_load = counter_load[63:CounterWidth]; + end else begin : g_counter_full + assign counter = counter_q; + end + + assign counter_val_o = counter; + +endmodule + +// Keep helper defines file-local. +`undef COUNTER_FLOP_RST diff --git a/flow/designs/src/ibex_sv/ibex_cs_registers.sv b/flow/designs/src/ibex_sv/ibex_cs_registers.sv new file mode 100644 index 0000000000..16a8acd3fc --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_cs_registers.sv @@ -0,0 +1,1420 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Control and Status Registers + * + * Control and Status Registers (CSRs) following the RISC-V Privileged + * Specification, draft version 1.11 + */ + +`include "prim_assert.sv" + +module ibex_cs_registers #( + parameter bit DbgTriggerEn = 0, + parameter int unsigned DbgHwBreakNum = 1, + parameter bit DataIndTiming = 1'b0, + parameter bit DummyInstructions = 1'b0, + parameter bit ShadowCSR = 1'b0, + parameter bit ICache = 1'b0, + parameter int unsigned MHPMCounterNum = 10, + parameter int unsigned MHPMCounterWidth = 40, + parameter bit PMPEnable = 0, + parameter int unsigned PMPGranularity = 0, + parameter int unsigned PMPNumRegions = 4, + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + // Hart ID + input logic [31:0] hart_id_i, + + // Privilege mode + output ibex_pkg::priv_lvl_e priv_mode_id_o, + output ibex_pkg::priv_lvl_e priv_mode_if_o, + output ibex_pkg::priv_lvl_e priv_mode_lsu_o, + output logic csr_mstatus_tw_o, + + // mtvec + output logic [31:0] csr_mtvec_o, + input logic csr_mtvec_init_i, + input logic [31:0] boot_addr_i, + + // Interface to registers (SRAM like) + input logic csr_access_i, + input ibex_pkg::csr_num_e csr_addr_i, + input logic [31:0] csr_wdata_i, + input ibex_pkg::csr_op_e csr_op_i, + input csr_op_en_i, + output logic [31:0] csr_rdata_o, + + // interrupts + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + input logic nmi_mode_i, + output logic irq_pending_o, // interrupt request pending + output ibex_pkg::irqs_t irqs_o, // interrupt requests qualified with mie + output logic csr_mstatus_mie_o, + output logic [31:0] csr_mepc_o, + + // PMP + output ibex_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions], + output logic [33:0] csr_pmp_addr_o [PMPNumRegions], + + // debug + input logic debug_mode_i, + input ibex_pkg::dbg_cause_e debug_cause_i, + input logic debug_csr_save_i, + output logic [31:0] csr_depc_o, + output logic debug_single_step_o, + output logic debug_ebreakm_o, + output logic debug_ebreaku_o, + output logic trigger_match_o, + + input logic [31:0] pc_if_i, + input logic [31:0] pc_id_i, + input logic [31:0] pc_wb_i, + + // CPU control bits + output logic data_ind_timing_o, + output logic dummy_instr_en_o, + output logic [2:0] dummy_instr_mask_o, + output logic dummy_instr_seed_en_o, + output logic [31:0] dummy_instr_seed_o, + output logic icache_enable_o, + output logic csr_shadow_err_o, + + // Exception save/restore + input logic csr_save_if_i, + input logic csr_save_id_i, + input logic csr_save_wb_i, + input logic csr_restore_mret_i, + input logic csr_restore_dret_i, + input logic csr_save_cause_i, + input ibex_pkg::exc_cause_e csr_mcause_i, + input logic [31:0] csr_mtval_i, + output logic illegal_csr_insn_o, // access to non-existent CSR, + // with wrong priviledge level, or + // missing write permissions + // Performance Counters + input logic instr_ret_i, // instr retired in ID/EX stage + input logic instr_ret_compressed_i, // compressed instr retired + input logic iside_wait_i, // core waiting for the iside + input logic jump_i, // jump instr seen (j, jr, jal, jalr) + input logic branch_i, // branch instr seen (bf, bnf) + input logic branch_taken_i, // branch was taken + input logic mem_load_i, // load from memory in this cycle + input logic mem_store_i, // store to memory in this cycle + input logic dside_wait_i, // core waiting for the dside + input logic mul_wait_i, // core waiting for multiply + input logic div_wait_i // core waiting for divide +); + + import ibex_pkg::*; + + localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1; + localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32; + + // misa + localparam logic [31:0] MISA_VALUE = + (0 << 0) // A - Atomic Instructions extension + | (1 << 2) // C - Compressed extension + | (0 << 3) // D - Double precision floating-point extension + | (32'(RV32E) << 4) // E - RV32E base ISA + | (0 << 5) // F - Single precision floating-point extension + | (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA + | (RV32MEnabled << 12) // M - Integer Multiply/Divide extension + | (0 << 13) // N - User level interrupts supported + | (0 << 18) // S - Supervisor mode implemented + | (1 << 20) // U - User mode implemented + | (0 << 23) // X - Non-standard extensions present + | (32'(CSR_MISA_MXL) << 30); // M-XLEN + + typedef struct packed { + logic mie; + logic mpie; + priv_lvl_e mpp; + logic mprv; + logic tw; + } status_t; + + typedef struct packed { + logic mpie; + priv_lvl_e mpp; + } status_stk_t; + + typedef struct packed { + x_debug_ver_e xdebugver; + logic [11:0] zero2; + logic ebreakm; + logic zero1; + logic ebreaks; + logic ebreaku; + logic stepie; + logic stopcount; + logic stoptime; + dbg_cause_e cause; + logic zero0; + logic mprven; + logic nmip; + logic step; + priv_lvl_e prv; + } dcsr_t; + + // CPU control register fields + typedef struct packed { + logic [2:0] dummy_instr_mask; + logic dummy_instr_en; + logic data_ind_timing; + logic icache_enable; + } cpu_ctrl_t; + + // Interrupt and exception control signals + logic [31:0] exception_pc; + + // CSRs + priv_lvl_e priv_lvl_q, priv_lvl_d; + status_t mstatus_q, mstatus_d; + logic mstatus_err; + logic mstatus_en; + irqs_t mie_q, mie_d; + logic mie_en; + logic [31:0] mscratch_q; + logic mscratch_en; + logic [31:0] mepc_q, mepc_d; + logic mepc_en; + logic [5:0] mcause_q, mcause_d; + logic mcause_en; + logic [31:0] mtval_q, mtval_d; + logic mtval_en; + logic [31:0] mtvec_q, mtvec_d; + logic mtvec_err; + logic mtvec_en; + irqs_t mip; + dcsr_t dcsr_q, dcsr_d; + logic dcsr_en; + logic [31:0] depc_q, depc_d; + logic depc_en; + logic [31:0] dscratch0_q; + logic [31:0] dscratch1_q; + logic dscratch0_en, dscratch1_en; + + // CSRs for recoverable NMIs + // NOTE: these CSRS are nonstandard, see https://github.com/riscv/riscv-isa-manual/issues/261 + status_stk_t mstack_q, mstack_d; + logic mstack_en; + logic [31:0] mstack_epc_q, mstack_epc_d; + logic [5:0] mstack_cause_q, mstack_cause_d; + + // PMP Signals + logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS]; + logic [PMP_CFG_W-1:0] pmp_cfg_rdata [PMP_MAX_REGIONS]; + logic pmp_csr_err; + + // Hardware performance monitor signals + logic [31:0] mcountinhibit; + // Only have mcountinhibit flops for counters that actually exist + logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; + logic mcountinhibit_we; + + // mhpmcounter flops are elaborated below providing only the precise number that is required based + // on MHPMCounterNum/MHPMCounterWidth. This signal connects to the Q output of these flops + // where they exist and is otherwise 0. + logic [63:0] mhpmcounter [32]; + logic [31:0] mhpmcounter_we; + logic [31:0] mhpmcounterh_we; + logic [31:0] mhpmcounter_incr; + logic [31:0] mhpmevent [32]; + logic [4:0] mhpmcounter_idx; + logic unused_mhpmcounter_we_1; + logic unused_mhpmcounterh_we_1; + logic unused_mhpmcounter_incr_1; + + // Debug / trigger registers + logic [31:0] tselect_rdata; + logic [31:0] tmatch_control_rdata; + logic [31:0] tmatch_value_rdata; + + // CPU control bits + cpu_ctrl_t cpuctrl_q, cpuctrl_d, cpuctrl_wdata; + logic cpuctrl_we; + logic cpuctrl_err; + + // CSR update logic + logic [31:0] csr_wdata_int; + logic [31:0] csr_rdata_int; + logic csr_we_int; + logic csr_wreq; + + // Access violation signals + logic illegal_csr; + logic illegal_csr_priv; + logic illegal_csr_write; + + logic [7:0] unused_boot_addr; + logic [2:0] unused_csr_addr; + + assign unused_boot_addr = boot_addr_i[7:0]; + + ///////////// + // CSR reg // + ///////////// + + logic [$bits(csr_num_e)-1:0] csr_addr; + assign csr_addr = {csr_addr_i}; + assign unused_csr_addr = csr_addr[7:5]; + assign mhpmcounter_idx = csr_addr[4:0]; + + // See RISC-V Privileged Specification, version 1.11, Section 2.1 + assign illegal_csr_priv = (csr_addr[9:8] > {priv_lvl_q}); + assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq; + assign illegal_csr_insn_o = csr_access_i & (illegal_csr | illegal_csr_write | illegal_csr_priv); + + // mip CSR is purely combinational - must be able to re-enable the clock upon WFI + assign mip.irq_software = irq_software_i; + assign mip.irq_timer = irq_timer_i; + assign mip.irq_external = irq_external_i; + assign mip.irq_fast = irq_fast_i; + + // read logic + always_comb begin + csr_rdata_int = '0; + illegal_csr = 1'b0; + + unique case (csr_addr_i) + // mhartid: unique hardware thread id + CSR_MHARTID: csr_rdata_int = hart_id_i; + + // mstatus: always M-mode, contains IE bit + CSR_MSTATUS: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSTATUS_MIE_BIT] = mstatus_q.mie; + csr_rdata_int[CSR_MSTATUS_MPIE_BIT] = mstatus_q.mpie; + csr_rdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp; + csr_rdata_int[CSR_MSTATUS_MPRV_BIT] = mstatus_q.mprv; + csr_rdata_int[CSR_MSTATUS_TW_BIT] = mstatus_q.tw; + end + + // misa + CSR_MISA: csr_rdata_int = MISA_VALUE; + + // interrupt enable + CSR_MIE: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mie_q.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mie_q.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mie_q.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q.irq_fast; + end + + CSR_MSCRATCH: csr_rdata_int = mscratch_q; + + // mtvec: trap-vector base address + CSR_MTVEC: csr_rdata_int = mtvec_q; + + // mepc: exception program counter + CSR_MEPC: csr_rdata_int = mepc_q; + + // mcause: exception cause + CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]}; + + // mtval: trap value + CSR_MTVAL: csr_rdata_int = mtval_q; + + // mip: interrupt pending + CSR_MIP: begin + csr_rdata_int = '0; + csr_rdata_int[CSR_MSIX_BIT] = mip.irq_software; + csr_rdata_int[CSR_MTIX_BIT] = mip.irq_timer; + csr_rdata_int[CSR_MEIX_BIT] = mip.irq_external; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast; + end + + // PMP registers + CSR_PMPCFG0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], + pmp_cfg_rdata[1], pmp_cfg_rdata[0]}; + CSR_PMPCFG1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], + pmp_cfg_rdata[5], pmp_cfg_rdata[4]}; + CSR_PMPCFG2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], + pmp_cfg_rdata[9], pmp_cfg_rdata[8]}; + CSR_PMPCFG3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], + pmp_cfg_rdata[13], pmp_cfg_rdata[12]}; + CSR_PMPADDR0: csr_rdata_int = pmp_addr_rdata[0]; + CSR_PMPADDR1: csr_rdata_int = pmp_addr_rdata[1]; + CSR_PMPADDR2: csr_rdata_int = pmp_addr_rdata[2]; + CSR_PMPADDR3: csr_rdata_int = pmp_addr_rdata[3]; + CSR_PMPADDR4: csr_rdata_int = pmp_addr_rdata[4]; + CSR_PMPADDR5: csr_rdata_int = pmp_addr_rdata[5]; + CSR_PMPADDR6: csr_rdata_int = pmp_addr_rdata[6]; + CSR_PMPADDR7: csr_rdata_int = pmp_addr_rdata[7]; + CSR_PMPADDR8: csr_rdata_int = pmp_addr_rdata[8]; + CSR_PMPADDR9: csr_rdata_int = pmp_addr_rdata[9]; + CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10]; + CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11]; + CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12]; + CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13]; + CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14]; + CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15]; + + CSR_DCSR: begin + csr_rdata_int = dcsr_q; + illegal_csr = ~debug_mode_i; + end + CSR_DPC: begin + csr_rdata_int = depc_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH0: begin + csr_rdata_int = dscratch0_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH1: begin + csr_rdata_int = dscratch1_q; + illegal_csr = ~debug_mode_i; + end + + // machine counter/timers + CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit; + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, + CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, + CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, + CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, + CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, + CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, + CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: begin + csr_rdata_int = mhpmevent[mhpmcounter_idx]; + end + + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin + csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0]; + end + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin + csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32]; + end + + // Debug triggers + CSR_TSELECT: begin + csr_rdata_int = tselect_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA1: begin + csr_rdata_int = tmatch_control_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA2: begin + csr_rdata_int = tmatch_value_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA3: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + CSR_MCONTEXT: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + CSR_SCONTEXT: begin + csr_rdata_int = '0; + illegal_csr = ~DbgTriggerEn; + end + + // Custom CSR for controlling CPU features + CSR_CPUCTRL: begin + csr_rdata_int = {{32-$bits(cpu_ctrl_t){1'b0}},cpuctrl_q}; + end + + // Custom CSR for LFSR re-seeding (cannot be read) + CSR_SECURESEED: begin + csr_rdata_int = '0; + end + + default: begin + illegal_csr = 1'b1; + end + endcase + end + + // write logic + always_comb begin + exception_pc = pc_id_i; + + priv_lvl_d = priv_lvl_q; + mstatus_en = 1'b0; + mstatus_d = mstatus_q; + mie_en = 1'b0; + mscratch_en = 1'b0; + mepc_en = 1'b0; + mepc_d = {csr_wdata_int[31:1], 1'b0}; + mcause_en = 1'b0; + mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; + mtval_en = 1'b0; + mtval_d = csr_wdata_int; + mtvec_en = csr_mtvec_init_i; + // mtvec.MODE set to vectored + // mtvec.BASE must be 256-byte aligned + mtvec_d = csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b0, 2'b01} : + {csr_wdata_int[31:8], 6'b0, 2'b01}; + dcsr_en = 1'b0; + dcsr_d = dcsr_q; + depc_d = {csr_wdata_int[31:1], 1'b0}; + depc_en = 1'b0; + dscratch0_en = 1'b0; + dscratch1_en = 1'b0; + + mstack_en = 1'b0; + mstack_d.mpie = mstatus_q.mpie; + mstack_d.mpp = mstatus_q.mpp; + mstack_epc_d = mepc_q; + mstack_cause_d = mcause_q; + + mcountinhibit_we = 1'b0; + mhpmcounter_we = '0; + mhpmcounterh_we = '0; + + cpuctrl_we = 1'b0; + + if (csr_we_int) begin + unique case (csr_addr_i) + // mstatus: IE bit + CSR_MSTATUS: begin + mstatus_en = 1'b1; + mstatus_d = '{ + mie: csr_wdata_int[CSR_MSTATUS_MIE_BIT], + mpie: csr_wdata_int[CSR_MSTATUS_MPIE_BIT], + mpp: priv_lvl_e'(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW]), + mprv: csr_wdata_int[CSR_MSTATUS_MPRV_BIT], + tw: csr_wdata_int[CSR_MSTATUS_TW_BIT] + }; + // Convert illegal values to M-mode + if ((mstatus_d.mpp != PRIV_LVL_M) && (mstatus_d.mpp != PRIV_LVL_U)) begin + mstatus_d.mpp = PRIV_LVL_M; + end + end + + // interrupt enable + CSR_MIE: mie_en = 1'b1; + + CSR_MSCRATCH: mscratch_en = 1'b1; + + // mepc: exception program counter + CSR_MEPC: mepc_en = 1'b1; + + // mcause + CSR_MCAUSE: mcause_en = 1'b1; + + // mtval: trap value + CSR_MTVAL: mtval_en = 1'b1; + + // mtvec + CSR_MTVEC: mtvec_en = 1'b1; + + CSR_DCSR: begin + dcsr_d = csr_wdata_int; + dcsr_d.xdebugver = XDEBUGVER_STD; + // Change to PRIV_LVL_M if software writes an unsupported value + if ((dcsr_d.prv != PRIV_LVL_M) && (dcsr_d.prv != PRIV_LVL_U)) begin + dcsr_d.prv = PRIV_LVL_M; + end + + // Read-only for SW + dcsr_d.cause = dcsr_q.cause; + + // currently not supported: + dcsr_d.nmip = 1'b0; + dcsr_d.mprven = 1'b0; + dcsr_d.stopcount = 1'b0; + dcsr_d.stoptime = 1'b0; + + // forced to be zero + dcsr_d.zero0 = 1'b0; + dcsr_d.zero1 = 1'b0; + dcsr_d.zero2 = 12'h0; + dcsr_en = 1'b1; + end + + // dpc: debug program counter + CSR_DPC: depc_en = 1'b1; + + CSR_DSCRATCH0: dscratch0_en = 1'b1; + CSR_DSCRATCH1: dscratch1_en = 1'b1; + + // machine counter/timers + CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1; + + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin + mhpmcounter_we[mhpmcounter_idx] = 1'b1; + end + + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin + mhpmcounterh_we[mhpmcounter_idx] = 1'b1; + end + + CSR_CPUCTRL: cpuctrl_we = 1'b1; + + default:; + endcase + end + + // exception controller gets priority over other writes + unique case (1'b1) + + csr_save_cause_i: begin + unique case (1'b1) + csr_save_if_i: begin + exception_pc = pc_if_i; + end + csr_save_id_i: begin + exception_pc = pc_id_i; + end + csr_save_wb_i: begin + exception_pc = pc_wb_i; + end + default:; + endcase + + // Any exception, including debug mode, causes a switch to M-mode + priv_lvl_d = PRIV_LVL_M; + + if (debug_csr_save_i) begin + // all interrupts are masked + // do not update cause, epc, tval, epc and status + dcsr_d.prv = priv_lvl_q; + dcsr_d.cause = debug_cause_i; + dcsr_en = 1'b1; + depc_d = exception_pc; + depc_en = 1'b1; + end else if (!debug_mode_i) begin + // In debug mode, "exceptions do not update any registers. That + // includes cause, epc, tval, dpc and mstatus." [Debug Spec v0.13.2, p.39] + mtval_en = 1'b1; + mtval_d = csr_mtval_i; + mstatus_en = 1'b1; + mstatus_d.mie = 1'b0; // disable interrupts + // save current status + mstatus_d.mpie = mstatus_q.mie; + mstatus_d.mpp = priv_lvl_q; + mepc_en = 1'b1; + mepc_d = exception_pc; + mcause_en = 1'b1; + mcause_d = {csr_mcause_i}; + // save previous status for recoverable NMI + mstack_en = 1'b1; + end + end // csr_save_cause_i + + csr_restore_dret_i: begin // DRET + priv_lvl_d = dcsr_q.prv; + end // csr_restore_dret_i + + csr_restore_mret_i: begin // MRET + priv_lvl_d = mstatus_q.mpp; + mstatus_en = 1'b1; + mstatus_d.mie = mstatus_q.mpie; // re-enable interrupts + + if (nmi_mode_i) begin + // when returning from an NMI restore state from mstack CSR + mstatus_d.mpie = mstack_q.mpie; + mstatus_d.mpp = mstack_q.mpp; + mepc_en = 1'b1; + mepc_d = mstack_epc_q; + mcause_en = 1'b1; + mcause_d = mstack_cause_q; + end else begin + // otherwise just set mstatus.MPIE/MPP + // See RISC-V Privileged Specification, version 1.11, Section 3.1.6.1 + mstatus_d.mpie = 1'b1; + mstatus_d.mpp = PRIV_LVL_U; + end + end // csr_restore_mret_i + + default:; + endcase + end + + // Update current priv level + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + priv_lvl_q <= PRIV_LVL_M; + end else begin + priv_lvl_q <= priv_lvl_d; + end + end + + // Send current priv level to the decoder + assign priv_mode_id_o = priv_lvl_q; + // New instruction fetches need to account for updates to priv_lvl_q this cycle + assign priv_mode_if_o = priv_lvl_d; + // Load/store instructions must factor in MPRV for PMP checking + assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q; + + // CSR operation logic + always_comb begin + unique case (csr_op_i) + CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; + CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; + CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o; + CSR_OP_READ: csr_wdata_int = csr_wdata_i; + default: csr_wdata_int = csr_wdata_i; + endcase + end + + assign csr_wreq = csr_op_en_i & + (csr_op_i inside {CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR}); + + // only write CSRs during one clock cycle + assign csr_we_int = csr_wreq & ~illegal_csr_insn_o; + + assign csr_rdata_o = csr_rdata_int; + + // directly output some registers + assign csr_mepc_o = mepc_q; + assign csr_depc_o = depc_q; + assign csr_mtvec_o = mtvec_q; + + assign csr_mstatus_mie_o = mstatus_q.mie; + assign csr_mstatus_tw_o = mstatus_q.tw; + assign debug_single_step_o = dcsr_q.step; + assign debug_ebreakm_o = dcsr_q.ebreakm; + assign debug_ebreaku_o = dcsr_q.ebreaku; + + // Qualify incoming interrupt requests in mip CSR with mie CSR for controller and to re-enable + // clock upon WFI (must be purely combinational). + assign irqs_o = mip & mie_q; + assign irq_pending_o = |irqs_o; + + //////////////////////// + // CSR instantiations // + //////////////////////// + + // MSTATUS + localparam status_t MSTATUS_RST_VAL = '{mie: 1'b0, + mpie: 1'b1, + mpp: PRIV_LVL_U, + mprv: 1'b0, + tw: 1'b0}; + ibex_csr #( + .Width ($bits(status_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ({MSTATUS_RST_VAL}) + ) u_mstatus_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mstatus_d}), + .wr_en_i (mstatus_en), + .rd_data_o (mstatus_q), + .rd_error_o (mstatus_err) + ); + + // MEPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mepc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mepc_d), + .wr_en_i (mepc_en), + .rd_data_o (mepc_q), + .rd_error_o () + ); + + // MIE + assign mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT]; + assign mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT]; + assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT]; + assign mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW]; + ibex_csr #( + .Width ($bits(irqs_t)), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mie_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mie_d}), + .wr_en_i (mie_en), + .rd_data_o (mie_q), + .rd_error_o () + ); + + // MSCRATCH + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mscratch_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (mscratch_en), + .rd_data_o (mscratch_q), + .rd_error_o () + ); + + // MCAUSE + ibex_csr #( + .Width (6), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mcause_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mcause_d), + .wr_en_i (mcause_en), + .rd_data_o (mcause_q), + .rd_error_o () + ); + + // MTVAL + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mtval_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mtval_d), + .wr_en_i (mtval_en), + .rd_data_o (mtval_q), + .rd_error_o () + ); + + // MTVEC + ibex_csr #( + .Width (32), + .ShadowCopy (ShadowCSR), + .ResetValue (32'd1) + ) u_mtvec_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mtvec_d), + .wr_en_i (mtvec_en), + .rd_data_o (mtvec_q), + .rd_error_o (mtvec_err) + ); + + // DCSR + localparam dcsr_t DCSR_RESET_VAL = '{ + xdebugver: XDEBUGVER_STD, + cause: DBG_CAUSE_NONE, // 3'h0 + prv: PRIV_LVL_M, + default: '0 + }; + ibex_csr #( + .Width ($bits(dcsr_t)), + .ShadowCopy (1'b0), + .ResetValue ({DCSR_RESET_VAL}) + ) u_dcsr_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({dcsr_d}), + .wr_en_i (dcsr_en), + .rd_data_o (dcsr_q), + .rd_error_o () + ); + + // DEPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_depc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (depc_d), + .wr_en_i (depc_en), + .rd_data_o (depc_q), + .rd_error_o () + ); + + // DSCRATCH0 + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_dscratch0_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (dscratch0_en), + .rd_data_o (dscratch0_q), + .rd_error_o () + ); + + // DSCRATCH1 + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_dscratch1_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int), + .wr_en_i (dscratch1_en), + .rd_data_o (dscratch1_q), + .rd_error_o () + ); + + // MSTACK + localparam status_stk_t MSTACK_RESET_VAL = '{ + mpie: 1'b1, + mpp: PRIV_LVL_U + }; + ibex_csr #( + .Width ($bits(status_stk_t)), + .ShadowCopy (1'b0), + .ResetValue ({MSTACK_RESET_VAL}) + ) u_mstack_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({mstack_d}), + .wr_en_i (mstack_en), + .rd_data_o (mstack_q), + .rd_error_o () + ); + + // MSTACK_EPC + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mstack_epc_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mstack_epc_d), + .wr_en_i (mstack_en), + .rd_data_o (mstack_epc_q), + .rd_error_o () + ); + + // MSTACK_CAUSE + ibex_csr #( + .Width (6), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_mstack_cause_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (mstack_cause_d), + .wr_en_i (mstack_en), + .rd_data_o (mstack_cause_q), + .rd_error_o () + ); + + // ----------------- + // PMP registers + // ----------------- + + if (PMPEnable) begin : g_pmp_registers + pmp_cfg_t pmp_cfg [PMPNumRegions]; + pmp_cfg_t pmp_cfg_wdata [PMPNumRegions]; + logic [PMPAddrWidth-1:0] pmp_addr [PMPNumRegions]; + logic [PMPNumRegions-1:0] pmp_cfg_we; + logic [PMPNumRegions-1:0] pmp_cfg_err; + logic [PMPNumRegions-1:0] pmp_addr_we; + logic [PMPNumRegions-1:0] pmp_addr_err; + + // Expanded / qualified register read data + for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_exp_rd_data + if (i < PMPNumRegions) begin : g_implemented_regions + // Add in zero padding for reserved fields + assign pmp_cfg_rdata[i] = {pmp_cfg[i].lock, 2'b00, pmp_cfg[i].mode, + pmp_cfg[i].exec, pmp_cfg[i].write, pmp_cfg[i].read}; + + // Address field read data depends on the current programmed mode and the granularity + // See RISC-V Privileged Specification, version 1.11, Section 3.6.1 + if (PMPGranularity == 0) begin : g_pmp_g0 + // If G == 0, read data is unmodified + assign pmp_addr_rdata[i] = pmp_addr[i]; + + end else if (PMPGranularity == 1) begin : g_pmp_g1 + // If G == 1, bit [G-1] reads as zero in TOR or OFF mode + always_comb begin + pmp_addr_rdata[i] = pmp_addr[i]; + if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin + pmp_addr_rdata[i][PMPGranularity-1:0] = '0; + end + end + + end else begin : g_pmp_g2 + // For G >= 2, bits are masked to one or zero depending on the mode + always_comb begin + // In NAPOT mode, bits [G-2:0] must read as one + pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity-1{1'b1}}}; + + if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin + // In TOR or OFF mode, bits [G-1:0] must read as zero + pmp_addr_rdata[i][PMPGranularity-1:0] = '0; + end + end + end + + end else begin : g_other_regions + // Non-implemented regions read as zero + assign pmp_cfg_rdata[i] = '0; + assign pmp_addr_rdata[i] = '0; + end + end + + // Write data calculation + for (genvar i = 0; i < PMPNumRegions; i++) begin : g_pmp_csrs + // ------------------------- + // Instantiate cfg registers + // ------------------------- + assign pmp_cfg_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (csr_addr == (CSR_OFF_PMP_CFG + (i[11:0] >> 2))); + + // Select the correct WDATA (each CSR contains 4 CFG fields, each with 2 RES bits) + assign pmp_cfg_wdata[i].lock = csr_wdata_int[(i%4)*PMP_CFG_W+7]; + // NA4 mode is not selectable when G > 0, mode is treated as OFF + always_comb begin + unique case (csr_wdata_int[(i%4)*PMP_CFG_W+3+:2]) + 2'b00 : pmp_cfg_wdata[i].mode = PMP_MODE_OFF; + 2'b01 : pmp_cfg_wdata[i].mode = PMP_MODE_TOR; + 2'b10 : pmp_cfg_wdata[i].mode = (PMPGranularity == 0) ? PMP_MODE_NA4: + PMP_MODE_OFF; + 2'b11 : pmp_cfg_wdata[i].mode = PMP_MODE_NAPOT; + default : pmp_cfg_wdata[i].mode = PMP_MODE_OFF; + endcase + end + assign pmp_cfg_wdata[i].exec = csr_wdata_int[(i%4)*PMP_CFG_W+2]; + // W = 1, R = 0 is a reserved combination. For now, we force W to 0 if R == 0 + assign pmp_cfg_wdata[i].write = &csr_wdata_int[(i%4)*PMP_CFG_W+:2]; + assign pmp_cfg_wdata[i].read = csr_wdata_int[(i%4)*PMP_CFG_W]; + + ibex_csr #( + .Width ($bits(pmp_cfg_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_pmp_cfg_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({pmp_cfg_wdata[i]}), + .wr_en_i (pmp_cfg_we[i]), + .rd_data_o (pmp_cfg[i]), + .rd_error_o (pmp_cfg_err[i]) + ); + + // -------------------------- + // Instantiate addr registers + // -------------------------- + if (i < PMPNumRegions - 1) begin : g_lower + assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (~pmp_cfg[i+1].lock | (pmp_cfg[i+1].mode != PMP_MODE_TOR)) & + (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end else begin : g_upper + assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg[i].lock & + (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end + + ibex_csr #( + .Width (PMPAddrWidth), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_pmp_addr_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (csr_wdata_int[31-:PMPAddrWidth]), + .wr_en_i (pmp_addr_we[i]), + .rd_data_o (pmp_addr[i]), + .rd_error_o (pmp_addr_err[i]) + ); + + assign csr_pmp_cfg_o[i] = pmp_cfg[i]; + assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00}; + end + + assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err); + + end else begin : g_no_pmp_tieoffs + // Generate tieoffs when PMP is not configured + for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_rdata + assign pmp_addr_rdata[i] = '0; + assign pmp_cfg_rdata[i] = '0; + end + for (genvar i = 0; i < PMPNumRegions; i++) begin : g_outputs + assign csr_pmp_cfg_o[i] = pmp_cfg_t'(1'b0); + assign csr_pmp_addr_o[i] = '0; + end + assign pmp_csr_err = 1'b0; + end + + ////////////////////////// + // Performance monitor // + ////////////////////////// + + // update enable signals + always_comb begin : mcountinhibit_update + if (mcountinhibit_we == 1'b1) begin + // bit 1 must always be 0 + mcountinhibit_d = {csr_wdata_int[MHPMCounterNum+2:2], 1'b0, csr_wdata_int[0]}; + end else begin + mcountinhibit_d = mcountinhibit_q; + end + end + + // event selection (hardwired) & control + always_comb begin : gen_mhpmcounter_incr + + // Assign inactive counters (first to prevent latch inference) + for (int unsigned i=0; i<32; i++) begin : gen_mhpmcounter_incr_inactive + mhpmcounter_incr[i] = 1'b0; + end + + // When adding or altering performance counter meanings and default + // mappings please update dv/verilator/pcount/cpp/ibex_pcounts.cc + // appropriately. + // + // active counters + mhpmcounter_incr[0] = 1'b1; // mcycle + mhpmcounter_incr[1] = 1'b0; // reserved + mhpmcounter_incr[2] = instr_ret_i; // minstret + mhpmcounter_incr[3] = dside_wait_i; // cycles waiting for data memory + mhpmcounter_incr[4] = iside_wait_i; // cycles waiting for instr fetches + mhpmcounter_incr[5] = mem_load_i; // num of loads + mhpmcounter_incr[6] = mem_store_i; // num of stores + mhpmcounter_incr[7] = jump_i; // num of jumps (unconditional) + mhpmcounter_incr[8] = branch_i; // num of branches (conditional) + mhpmcounter_incr[9] = branch_taken_i; // num of taken branches (conditional) + mhpmcounter_incr[10] = instr_ret_compressed_i; // num of compressed instr + mhpmcounter_incr[11] = mul_wait_i; // cycles waiting for multiply + mhpmcounter_incr[12] = div_wait_i; // cycles waiting for divide + end + + // event selector (hardwired, 0 means no event) + always_comb begin : gen_mhpmevent + + // activate all + for (int i=0; i<32; i++) begin : gen_mhpmevent_active + mhpmevent[i] = '0; + mhpmevent[i][i] = 1'b1; + end + + // deactivate + mhpmevent[1] = '0; // not existing, reserved + for (int unsigned i=3+MHPMCounterNum; i<32; i++) begin : gen_mhpmevent_inactive + mhpmevent[i] = '0; + end + end + + // mcycle + ibex_counter #( + .CounterWidth(64) + ) mcycle_counter_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]), + .counterh_we_i(mhpmcounterh_we[0]), + .counter_we_i(mhpmcounter_we[0]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[0]) + ); + + // minstret + ibex_counter #( + .CounterWidth(64) + ) minstret_counter_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]), + .counterh_we_i(mhpmcounterh_we[2]), + .counter_we_i(mhpmcounter_we[2]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[2]) + ); + + // reserved: + assign mhpmcounter[1] = '0; + assign unused_mhpmcounter_we_1 = mhpmcounter_we[1]; + assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1]; + assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1]; + + for (genvar cnt=0; cnt < 29; cnt++) begin : gen_cntrs + if (cnt < MHPMCounterNum) begin : gen_imp + ibex_counter #( + .CounterWidth(MHPMCounterWidth) + ) mcounters_variable_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[cnt+3] & ~mcountinhibit[cnt+3]), + .counterh_we_i(mhpmcounterh_we[cnt+3]), + .counter_we_i(mhpmcounter_we[cnt+3]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[cnt+3]) + ); + end else begin : gen_unimp + assign mhpmcounter[cnt+3] = '0; + end + end + + if(MHPMCounterNum < 29) begin : g_mcountinhibit_reduced + logic [29-MHPMCounterNum-1:0] unused_mhphcounter_we; + logic [29-MHPMCounterNum-1:0] unused_mhphcounterh_we; + logic [29-MHPMCounterNum-1:0] unused_mhphcounter_incr; + + assign mcountinhibit = {{29-MHPMCounterNum{1'b1}}, mcountinhibit_q}; + // Lint tieoffs for unused bits + assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum+3]; + assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum+3]; + assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum+3]; + end else begin : g_mcountinhibit_full + assign mcountinhibit = mcountinhibit_q; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mcountinhibit_q <= '0; + end else begin + mcountinhibit_q <= mcountinhibit_d; + end + end + + ///////////////////////////// + // Debug trigger registers // + ///////////////////////////// + + if (DbgTriggerEn) begin : gen_trigger_regs + localparam int unsigned DbgHwNumLen = DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1; + // Register values + logic [DbgHwNumLen-1:0] tselect_d, tselect_q; + logic tmatch_control_d; + logic [DbgHwBreakNum-1:0] tmatch_control_q; + logic [31:0] tmatch_value_d; + logic [31:0] tmatch_value_q[DbgHwBreakNum]; + // Write enables + logic tselect_we; + logic [DbgHwBreakNum-1:0] tmatch_control_we; + logic [DbgHwBreakNum-1:0] tmatch_value_we; + // Trigger comparison result + logic [DbgHwBreakNum-1:0] trigger_match; + + // Write select + assign tselect_we = csr_we_int & debug_mode_i & (csr_addr_i == CSR_TSELECT); + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_we + assign tmatch_control_we[i] = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i & + (csr_addr_i == CSR_TDATA1); + assign tmatch_value_we[i] = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i & + (csr_addr_i == CSR_TDATA2); + end + + // Debug interface tests the available number of triggers by writing and reading the trigger + // select register. Only allow changes to the register if it is within the supported region. + assign tselect_d = (csr_wdata_int < DbgHwBreakNum) ? csr_wdata_int[DbgHwNumLen-1:0] : + DbgHwBreakNum-1; + // tmatch_control is enabled when the execute bit is set + assign tmatch_control_d = csr_wdata_int[2]; + assign tmatch_value_d = csr_wdata_int[31:0]; + + // Registers + ibex_csr #( + .Width (DbgHwNumLen), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tselect_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tselect_d), + .wr_en_i (tselect_we), + .rd_data_o (tselect_q), + .rd_error_o () + ); + + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg + ibex_csr #( + .Width (1), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tmatch_control_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tmatch_control_d), + .wr_en_i (tmatch_control_we[i]), + .rd_data_o (tmatch_control_q[i]), + .rd_error_o () + ); + + ibex_csr #( + .Width (32), + .ShadowCopy (1'b0), + .ResetValue ('0) + ) u_tmatch_value_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i (tmatch_value_d), + .wr_en_i (tmatch_value_we[i]), + .rd_data_o (tmatch_value_q[i]), + .rd_error_o () + ); + end + + // Assign read data + // TSELECT - number of supported triggers defined by parameter DbgHwBreakNum + localparam int unsigned TSelectRdataPadlen = DbgHwNumLen >= 32 ? 0 : (32 - DbgHwNumLen); + assign tselect_rdata = {{TSelectRdataPadlen{1'b0}}, tselect_q}; + + // TDATA0 - only support simple address matching + assign tmatch_control_rdata = {4'h2, // type : address/data match + 1'b1, // dmode : access from D mode only + 6'h00, // maskmax : exact match only + 1'b0, // hit : not supported + 1'b0, // select : address match only + 1'b0, // timing : match before execution + 2'b00, // sizelo : match any access + 4'h1, // action : enter debug mode + 1'b0, // chain : not supported + 4'h0, // match : simple match + 1'b1, // m : match in m-mode + 1'b0, // 0 : zero + 1'b0, // s : not supported + 1'b1, // u : match in u-mode + tmatch_control_q[tselect_q], // execute : match instruction address + 1'b0, // store : not supported + 1'b0}; // load : not supported + // TDATA1 - address match value only + assign tmatch_value_rdata = tmatch_value_q[tselect_q]; + + // Breakpoint matching + // We match against the next address, as the breakpoint must be taken before execution + for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_trigger_match + assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]); + end + assign trigger_match_o = |trigger_match; + + end else begin : gen_no_trigger_regs + assign tselect_rdata = 'b0; + assign tmatch_control_rdata = 'b0; + assign tmatch_value_rdata = 'b0; + assign trigger_match_o = 'b0; + end + + ////////////////////////// + // CPU control register // + ////////////////////////// + + // Cast register write data + assign cpuctrl_wdata = cpu_ctrl_t'(csr_wdata_int[$bits(cpu_ctrl_t)-1:0]); + + // Generate fixed time execution bit + if (DataIndTiming) begin : gen_dit + assign cpuctrl_d.data_ind_timing = cpuctrl_wdata.data_ind_timing; + + end else begin : gen_no_dit + // tieoff for the unused bit + logic unused_dit; + assign unused_dit = cpuctrl_wdata.data_ind_timing; + + // field will always read as zero if not configured + assign cpuctrl_d.data_ind_timing = 1'b0; + end + + assign data_ind_timing_o = cpuctrl_q.data_ind_timing; + + // Generate dummy instruction signals + if (DummyInstructions) begin : gen_dummy + assign cpuctrl_d.dummy_instr_en = cpuctrl_wdata.dummy_instr_en; + assign cpuctrl_d.dummy_instr_mask = cpuctrl_wdata.dummy_instr_mask; + + // Signal a write to the seed register + assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == CSR_SECURESEED); + assign dummy_instr_seed_o = csr_wdata_int; + + end else begin : gen_no_dummy + // tieoff for the unused bit + logic unused_dummy_en; + logic [2:0] unused_dummy_mask; + assign unused_dummy_en = cpuctrl_wdata.dummy_instr_en; + assign unused_dummy_mask = cpuctrl_wdata.dummy_instr_mask; + + // field will always read as zero if not configured + assign cpuctrl_d.dummy_instr_en = 1'b0; + assign cpuctrl_d.dummy_instr_mask = 3'b000; + assign dummy_instr_seed_en_o = 1'b0; + assign dummy_instr_seed_o = '0; + end + + assign dummy_instr_en_o = cpuctrl_q.dummy_instr_en; + assign dummy_instr_mask_o = cpuctrl_q.dummy_instr_mask; + + // Generate icache enable bit + if (ICache) begin : gen_icache_enable + assign cpuctrl_d.icache_enable = cpuctrl_wdata.icache_enable; + end else begin : gen_no_icache + // tieoff for the unused icen bit + logic unused_icen; + assign unused_icen = cpuctrl_wdata.icache_enable; + + // icen field will always read as zero if ICache not configured + assign cpuctrl_d.icache_enable = 1'b0; + end + + assign icache_enable_o = cpuctrl_q.icache_enable; + + ibex_csr #( + .Width ($bits(cpu_ctrl_t)), + .ShadowCopy (ShadowCSR), + .ResetValue ('0) + ) u_cpuctrl_csr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .wr_data_i ({cpuctrl_d}), + .wr_en_i (cpuctrl_we), + .rd_data_o (cpuctrl_q), + .rd_error_o (cpuctrl_err) + ); + + assign csr_shadow_err_o = mstatus_err | mtvec_err | pmp_csr_err | cpuctrl_err; + + //////////////// + // Assertions // + //////////////// + + `ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_csr.sv b/flow/designs/src/ibex_sv/ibex_csr.sv new file mode 100644 index 0000000000..8623fa552f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_csr.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Control / status register primitive + */ + +`include "prim_assert.sv" + +module ibex_csr #( + parameter int unsigned Width = 32, + parameter bit ShadowCopy = 1'b0, + parameter bit [Width-1:0] ResetValue = '0 + ) ( + input logic clk_i, + input logic rst_ni, + + input logic [Width-1:0] wr_data_i, + input logic wr_en_i, + output logic [Width-1:0] rd_data_o, + + output logic rd_error_o +); + + logic [Width-1:0] rdata_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= ResetValue; + end else if (wr_en_i) begin + rdata_q <= wr_data_i; + end + end + + assign rd_data_o = rdata_q; + + if (ShadowCopy) begin : gen_shadow + logic [Width-1:0] shadow_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + shadow_q <= ~ResetValue; + end else if (wr_en_i) begin + shadow_q <= ~wr_data_i; + end + end + + assign rd_error_o = rdata_q != ~shadow_q; + + end else begin : gen_no_shadow + assign rd_error_o = 1'b0; + end + + `ASSERT_KNOWN(IbexCSREnValid, wr_en_i) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_decoder.sv b/flow/designs/src/ibex_sv/ibex_decoder.sv new file mode 100644 index 0000000000..b61520ed8c --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_decoder.sv @@ -0,0 +1,1155 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +/** + * Instruction decoder + * + * This module is fully combinatorial, clock and reset are used for + * assertions only. + */ + +`include "prim_assert.sv" + +module ibex_decoder #( + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit BranchTargetALU = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // to/from controller + output logic illegal_insn_o, // illegal instr encountered + output logic ebrk_insn_o, // trap instr encountered + output logic mret_insn_o, // return from exception instr + // encountered + output logic dret_insn_o, // return from debug instr encountered + output logic ecall_insn_o, // syscall instr encountered + output logic wfi_insn_o, // wait for interrupt instr encountered + output logic jump_set_o, // jump taken set signal + input logic branch_taken_i, // registered branch decision + output logic icache_inval_o, + + // from IF-ID pipeline register + input logic instr_first_cycle_i, // instruction read is in its first cycle + input logic [31:0] instr_rdata_i, // instruction read from memory/cache + input logic [31:0] instr_rdata_alu_i, // instruction read from memory/cache + // replicated to ease fan-out) + + input logic illegal_c_insn_i, // compressed instruction decode failed + + // immediates + output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a + output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b + output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a + output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b + output logic [31:0] imm_i_type_o, + output logic [31:0] imm_s_type_o, + output logic [31:0] imm_b_type_o, + output logic [31:0] imm_u_type_o, + output logic [31:0] imm_j_type_o, + output logic [31:0] zimm_rs1_type_o, + + // register file + output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection + output logic rf_we_o, // write enable for regfile + output logic [4:0] rf_raddr_a_o, + output logic [4:0] rf_raddr_b_o, + output logic [4:0] rf_waddr_o, + output logic rf_ren_a_o, // Instruction reads from RF addr A + output logic rf_ren_b_o, // Instruction reads from RF addr B + + // ALU + output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection + output ibex_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC, + // immediate or zero + output ibex_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or + // immediate + output logic alu_multicycle_o, // ternary bitmanip instruction + + // MULT & DIV + output logic mult_en_o, // perform integer multiplication + output logic div_en_o, // perform integer division or remainder + output logic mult_sel_o, // as above but static, for data muxes + output logic div_sel_o, // as above but static, for data muxes + + output ibex_pkg::md_op_e multdiv_operator_o, + output logic [1:0] multdiv_signed_mode_o, + + // CSRs + output logic csr_access_o, // access to CSR + output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR + + // LSU + output logic data_req_o, // start transaction to data memory + output logic data_we_o, // write enable + output logic [1:0] data_type_o, // size of transaction: byte, half + // word or word + output logic data_sign_extension_o, // sign extension for data read from + // memory + + // jump/branches + output logic jump_in_dec_o, // jump is being calculated in ALU + output logic branch_in_dec_o +); + + import ibex_pkg::*; + + logic illegal_insn; + logic illegal_reg_rv32e; + logic csr_illegal; + logic rf_we; + + logic [31:0] instr; + logic [31:0] instr_alu; + logic [9:0] unused_instr_alu; + // Source/Destination register instruction index + logic [4:0] instr_rs1; + logic [4:0] instr_rs2; + logic [4:0] instr_rs3; + logic [4:0] instr_rd; + + logic use_rs3_d; + logic use_rs3_q; + + csr_op_e csr_op; + + opcode_e opcode; + opcode_e opcode_alu; + + // To help timing the flops containing the current instruction are replicated to reduce fan-out. + // instr_alu is used to determine the ALU control logic and associated operand/imm select signals + // as the ALU is often on the more critical timing paths. instr is used for everything else. + assign instr = instr_rdata_i; + assign instr_alu = instr_rdata_alu_i; + + ////////////////////////////////////// + // Register and immediate selection // + ////////////////////////////////////// + + // immediate extraction and sign extension + assign imm_i_type_o = { {20{instr[31]}}, instr[31:20] }; + assign imm_s_type_o = { {20{instr[31]}}, instr[31:25], instr[11:7] }; + assign imm_b_type_o = { {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }; + assign imm_u_type_o = { instr[31:12], 12'b0 }; + assign imm_j_type_o = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; + + // immediate for CSR manipulation (zero extended) + assign zimm_rs1_type_o = { 27'b0, instr_rs1 }; // rs1 + + if (RV32B != RV32BNone) begin : gen_rs3_flop + // the use of rs3 is known one cycle ahead. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + use_rs3_q <= 1'b0; + end else begin + use_rs3_q <= use_rs3_d; + end + end + end else begin : gen_no_rs3_flop + // always zero + assign use_rs3_q = use_rs3_d; + end + + // source registers + assign instr_rs1 = instr[19:15]; + assign instr_rs2 = instr[24:20]; + assign instr_rs3 = instr[31:27]; + assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i) ? instr_rs3 : instr_rs1; // rs3 / rs1 + assign rf_raddr_b_o = instr_rs2; // rs2 + + // destination register + assign instr_rd = instr[11:7]; + assign rf_waddr_o = instr_rd; // rd + + //////////////////// + // Register check // + //////////////////// + if (RV32E) begin : gen_rv32e_reg_check_active + assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) | + (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B)) | + (rf_waddr_o[4] & rf_we)); + end else begin : gen_rv32e_reg_check_inactive + assign illegal_reg_rv32e = 1'b0; + end + + /////////////////////// + // CSR operand check // + /////////////////////// + always_comb begin : csr_operand_check + csr_op_o = csr_op; + + // CSRRSI/CSRRCI must not write 0 to CSRs (uimm[4:0]=='0) + // CSRRS/CSRRC must not write from x0 to CSRs (rs1=='0) + if ((csr_op == CSR_OP_SET || csr_op == CSR_OP_CLEAR) && + instr_rs1 == '0) begin + csr_op_o = CSR_OP_READ; + end + end + + ///////////// + // Decoder // + ///////////// + + always_comb begin + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + icache_inval_o = 1'b0; + + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + + rf_wdata_sel_o = RF_WD_EX; + rf_we = 1'b0; + rf_ren_a_o = 1'b0; + rf_ren_b_o = 1'b0; + + csr_access_o = 1'b0; + csr_illegal = 1'b0; + csr_op = CSR_OP_READ; + + data_we_o = 1'b0; + data_type_o = 2'b00; + data_sign_extension_o = 1'b0; + data_req_o = 1'b0; + + illegal_insn = 1'b0; + ebrk_insn_o = 1'b0; + mret_insn_o = 1'b0; + dret_insn_o = 1'b0; + ecall_insn_o = 1'b0; + wfi_insn_o = 1'b0; + + opcode = opcode_e'(instr[6:0]); + + unique case (opcode) + + /////////// + // Jumps // + /////////// + + OPCODE_JAL: begin // Jump and Link + jump_in_dec_o = 1'b1; + + if (instr_first_cycle_i) begin + // Calculate jump target (and store PC + 4 if BranchTargetALU is configured) + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end else begin + // Calculate and store PC+4 + rf_we = 1'b1; + end + end + + OPCODE_JALR: begin // Jump and Link Register + jump_in_dec_o = 1'b1; + + if (instr_first_cycle_i) begin + // Calculate jump target (and store PC + 4 if BranchTargetALU is configured) + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end else begin + // Calculate and store PC+4 + rf_we = 1'b1; + end + if (instr[14:12] != 3'b0) begin + illegal_insn = 1'b1; + end + + rf_ren_a_o = 1'b1; + end + + OPCODE_BRANCH: begin // Branch + branch_in_dec_o = 1'b1; + // Check branch condition selection + unique case (instr[14:12]) + 3'b000, + 3'b001, + 3'b100, + 3'b101, + 3'b110, + 3'b111: illegal_insn = 1'b0; + default: illegal_insn = 1'b1; + endcase + + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + end + + //////////////// + // Load/store // + //////////////// + + OPCODE_STORE: begin + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + data_req_o = 1'b1; + data_we_o = 1'b1; + + if (instr[14]) begin + illegal_insn = 1'b1; + end + + // store size + unique case (instr[13:12]) + 2'b00: data_type_o = 2'b10; // sb + 2'b01: data_type_o = 2'b01; // sh + 2'b10: data_type_o = 2'b00; // sw + default: illegal_insn = 1'b1; + endcase + end + + OPCODE_LOAD: begin + rf_ren_a_o = 1'b1; + data_req_o = 1'b1; + data_type_o = 2'b00; + + // sign/zero extension + data_sign_extension_o = ~instr[14]; + + // load size + unique case (instr[13:12]) + 2'b00: data_type_o = 2'b10; // lb(u) + 2'b01: data_type_o = 2'b01; // lh(u) + 2'b10: begin + data_type_o = 2'b00; // lw + if (instr[14]) begin + illegal_insn = 1'b1; // lwu does not exist + end + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + + ///////// + // ALU // + ///////// + + OPCODE_LUI: begin // Load Upper Immediate + rf_we = 1'b1; + end + + OPCODE_AUIPC: begin // Add Upper Immediate to PC + rf_we = 1'b1; + end + + OPCODE_OP_IMM: begin // Register-Immediate ALU Operations + rf_ren_a_o = 1'b1; + rf_we = 1'b1; + + unique case (instr[14:12]) + 3'b000, + 3'b010, + 3'b011, + 3'b100, + 3'b110, + 3'b111: illegal_insn = 1'b0; + + 3'b001: begin + unique case (instr[31:27]) + 5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // slli + 5'b0_0100, // sloi + 5'b0_1001, // sbclri + 5'b0_0101, // sbseti + 5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbinvi + 5'b0_0001: if (instr[26] == 1'b0) begin + illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // shfl + end else begin + illegal_insn = 1'b1; + end + 5'b0_1100: begin + unique case(instr[26:20]) + 7'b000_0000, // clz + 7'b000_0001, // ctz + 7'b000_0010, // pcnt + 7'b000_0100, // sext.b + 7'b000_0101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sext.h + 7'b001_0000, // crc32.b + 7'b001_0001, // crc32.h + 7'b001_0010, // crc32.w + 7'b001_1000, // crc32c.b + 7'b001_1001, // crc32c.h + 7'b001_1010: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // crc32c.w + + default: illegal_insn = 1'b1; + endcase + end + default : illegal_insn = 1'b1; + endcase + end + + 3'b101: begin + if (instr[26]) begin + illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // fsri + end else begin + unique case (instr[31:27]) + 5'b0_0000, // srli + 5'b0_1000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1; // srai + + 5'b0_0100, // sroi + 5'b0_1100, // rori + 5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // sbexti + + 5'b0_1101: begin + if ((RV32B == RV32BFull)) begin + illegal_insn = 1'b0; // grevi + end else begin + unique case (instr[24:20]) + 5'b11111, // rev + 5'b11000: illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // rev8 + + default: illegal_insn = 1'b1; + endcase + end + end + 5'b0_0101: begin + if ((RV32B == RV32BFull)) begin + illegal_insn = 1'b0; // gorci + end else if (instr[24:20] == 5'b00111) begin + illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1; // orc.b + end else begin + illegal_insn = 1'b1; + end + end + 5'b0_0001: begin + if (instr[26] == 1'b0) begin + illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // unshfl + end else begin + illegal_insn = 1'b1; + end + end + + default: illegal_insn = 1'b1; + endcase + end + end + + default: illegal_insn = 1'b1; + endcase + end + + OPCODE_OP: begin // Register-Register ALU operation + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + rf_we = 1'b1; + if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin + illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr + end else begin + unique case ({instr[31:25], instr[14:12]}) + // RV32I ALU operations + {7'b000_0000, 3'b000}, + {7'b010_0000, 3'b000}, + {7'b000_0000, 3'b010}, + {7'b000_0000, 3'b011}, + {7'b000_0000, 3'b100}, + {7'b000_0000, 3'b110}, + {7'b000_0000, 3'b111}, + {7'b000_0000, 3'b001}, + {7'b000_0000, 3'b101}, + {7'b010_0000, 3'b101}: illegal_insn = 1'b0; + + // RV32B zbb + {7'b010_0000, 3'b111}, // andn + {7'b010_0000, 3'b110}, // orn + {7'b010_0000, 3'b100}, // xnor + {7'b001_0000, 3'b001}, // slo + {7'b001_0000, 3'b101}, // sro + {7'b011_0000, 3'b001}, // rol + {7'b011_0000, 3'b101}, // ror + {7'b000_0101, 3'b100}, // min + {7'b000_0101, 3'b101}, // max + {7'b000_0101, 3'b110}, // minu + {7'b000_0101, 3'b111}, // maxu + {7'b000_0100, 3'b100}, // pack + {7'b010_0100, 3'b100}, // packu + {7'b000_0100, 3'b111}, // packh + // RV32B zbs + {7'b010_0100, 3'b001}, // sbclr + {7'b001_0100, 3'b001}, // sbset + {7'b011_0100, 3'b001}, // sbinv + {7'b010_0100, 3'b101}, // sbext + // RV32B zbf + {7'b010_0100, 3'b111}: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bfp + // RV32B zbe + {7'b010_0100, 3'b110}, // bdep + {7'b000_0100, 3'b110}, // bext + // RV32B zbp + {7'b011_0100, 3'b101}, // grev + {7'b001_0100, 3'b101}, // gorc + {7'b000_0100, 3'b001}, // shfl + {7'b000_0100, 3'b101}, // unshfl + // RV32B zbc + {7'b000_0101, 3'b001}, // clmul + {7'b000_0101, 3'b010}, // clmulr + {7'b000_0101, 3'b011}: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // clmulh + + // RV32M instructions + {7'b000_0001, 3'b000}: begin // mul + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b001}: begin // mulh + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b010}: begin // mulhsu + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b01; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b011}: begin // mulhu + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b100}: begin // div + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b101}: begin // divu + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b110}: begin // rem + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + {7'b000_0001, 3'b111}: begin // remu + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone) ? 1'b1 : 1'b0; + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + end + + ///////////// + // Special // + ///////////// + + OPCODE_MISC_MEM: begin + unique case (instr[14:12]) + 3'b000: begin + // FENCE is treated as a NOP since all memory operations are already strictly ordered. + rf_we = 1'b0; + end + 3'b001: begin + // FENCE.I is implemented as a jump to the next PC, this gives the required flushing + // behaviour (iside prefetch buffer flushed and response to any outstanding iside + // requests will be ignored). + // If present, the ICache will also be flushed. + jump_in_dec_o = 1'b1; + + rf_we = 1'b0; + + if (instr_first_cycle_i) begin + jump_set_o = 1'b1; + icache_inval_o = 1'b1; + end + end + default: begin + illegal_insn = 1'b1; + end + endcase + end + + OPCODE_SYSTEM: begin + if (instr[14:12] == 3'b000) begin + // non CSR related SYSTEM instructions + unique case (instr[31:20]) + 12'h000: // ECALL + // environment (system) call + ecall_insn_o = 1'b1; + + 12'h001: // ebreak + // debugger trap + ebrk_insn_o = 1'b1; + + 12'h302: // mret + mret_insn_o = 1'b1; + + 12'h7b2: // dret + dret_insn_o = 1'b1; + + 12'h105: // wfi + wfi_insn_o = 1'b1; + + default: + illegal_insn = 1'b1; + endcase + + // rs1 and rd must be 0 + if (instr_rs1 != 5'b0 || instr_rd != 5'b0) begin + illegal_insn = 1'b1; + end + end else begin + // instruction to read/modify CSR + csr_access_o = 1'b1; + rf_wdata_sel_o = RF_WD_CSR; + rf_we = 1'b1; + + if (~instr[14]) begin + rf_ren_a_o = 1'b1; + end + + unique case (instr[13:12]) + 2'b01: csr_op = CSR_OP_WRITE; + 2'b10: csr_op = CSR_OP_SET; + 2'b11: csr_op = CSR_OP_CLEAR; + default: csr_illegal = 1'b1; + endcase + + illegal_insn = csr_illegal; + end + + end + default: begin + illegal_insn = 1'b1; + end + endcase + + // make sure illegal compressed instructions cause illegal instruction exceptions + if (illegal_c_insn_i) begin + illegal_insn = 1'b1; + end + + // make sure illegal instructions detected in the decoder do not propagate from decoder + // into register file, LSU, EX, WB, CSRs, PC + // NOTE: instructions can also be detected to be illegal inside the CSRs (upon accesses with + // insufficient privileges), or when accessing non-available registers in RV32E, + // these cases are not handled here + if (illegal_insn) begin + rf_we = 1'b0; + data_req_o = 1'b0; + data_we_o = 1'b0; + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + csr_access_o = 1'b0; + end + end + + ///////////////////////////// + // Decoder for ALU control // + ///////////////////////////// + + always_comb begin + alu_operator_o = ALU_SLTU; + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_I; + + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_I; + + + opcode_alu = opcode_e'(instr_alu[6:0]); + + use_rs3_d = 1'b0; + alu_multicycle_o = 1'b0; + mult_sel_o = 1'b0; + div_sel_o = 1'b0; + + unique case (opcode_alu) + + /////////// + // Jumps // + /////////// + + OPCODE_JAL: begin // Jump and Link + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_J; + end + + // Jumps take two cycles without the BTALU + if (instr_first_cycle_i && !BranchTargetALU) begin + // Calculate jump target + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_J; + alu_operator_o = ALU_ADD; + end else begin + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + OPCODE_JALR: begin // Jump and Link Register + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_REG_A; + bt_b_mux_sel_o = IMM_B_I; + end + + // Jumps take two cycles without the BTALU + if (instr_first_cycle_i && !BranchTargetALU) begin + // Calculate jump target + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + alu_operator_o = ALU_ADD; + end else begin + // Calculate and store PC+4 + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + OPCODE_BRANCH: begin // Branch + // Check branch condition selection + unique case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_EQ; + 3'b001: alu_operator_o = ALU_NE; + 3'b100: alu_operator_o = ALU_LT; + 3'b101: alu_operator_o = ALU_GE; + 3'b110: alu_operator_o = ALU_LTU; + 3'b111: alu_operator_o = ALU_GEU; + default: ; + endcase + + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + // Not-taken branch will jump to next instruction (used in secure mode) + bt_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC; + end + + // Without branch target ALU, a branch is a two-stage operation using the Main ALU in both + // stages + if (instr_first_cycle_i) begin + // First evaluate the branch condition + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + end else begin + // Then calculate jump target + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + // Not-taken branch will jump to next instruction (used in secure mode) + imm_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + + //////////////// + // Load/store // + //////////////// + + OPCODE_STORE: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + alu_operator_o = ALU_ADD; + + if (!instr_alu[14]) begin + // offset from immediate + imm_b_mux_sel_o = IMM_B_S; + alu_op_b_mux_sel_o = OP_B_IMM; + end + end + + OPCODE_LOAD: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + + // offset from immediate + alu_operator_o = ALU_ADD; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + end + + ///////// + // ALU // + ///////// + + OPCODE_LUI: begin // Load Upper Immediate + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + + OPCODE_AUIPC: begin // Add Upper Immediate to PC + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + + OPCODE_OP_IMM: begin // Register-Immediate ALU Operations + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + + unique case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_ADD; // Add Immediate + 3'b010: alu_operator_o = ALU_SLT; // Set to one if Lower Than Immediate + 3'b011: alu_operator_o = ALU_SLTU; // Set to one if Lower Than Immediate Unsigned + 3'b100: alu_operator_o = ALU_XOR; // Exclusive Or with Immediate + 3'b110: alu_operator_o = ALU_OR; // Or with Immediate + 3'b111: alu_operator_o = ALU_AND; // And with Immediate + + 3'b001: begin + if (RV32B != RV32BNone) begin + unique case (instr_alu[31:27]) + 5'b0_0000: alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate + 5'b0_0100: alu_operator_o = ALU_SLO; // Shift Left Ones by Immediate + 5'b0_1001: alu_operator_o = ALU_SBCLR; // Clear bit specified by immediate + 5'b0_0101: alu_operator_o = ALU_SBSET; // Set bit specified by immediate + 5'b0_1101: alu_operator_o = ALU_SBINV; // Invert bit specified by immediate. + // Shuffle with Immediate Control Value + 5'b0_0001: if (instr_alu[26] == 0) alu_operator_o = ALU_SHFL; + 5'b0_1100: begin + unique case (instr_alu[26:20]) + 7'b000_0000: alu_operator_o = ALU_CLZ; // clz + 7'b000_0001: alu_operator_o = ALU_CTZ; // ctz + 7'b000_0010: alu_operator_o = ALU_PCNT; // pcnt + 7'b000_0100: alu_operator_o = ALU_SEXTB; // sext.b + 7'b000_0101: alu_operator_o = ALU_SEXTH; // sext.h + 7'b001_0000: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_B; // crc32.b + alu_multicycle_o = 1'b1; + end + end + 7'b001_0001: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_H; // crc32.h + alu_multicycle_o = 1'b1; + end + end + 7'b001_0010: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_W; // crc32.w + alu_multicycle_o = 1'b1; + end + end + 7'b001_1000: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_B; // crc32c.b + alu_multicycle_o = 1'b1; + end + end + 7'b001_1001: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_H; // crc32c.h + alu_multicycle_o = 1'b1; + end + end + 7'b001_1010: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_W; // crc32c.w + alu_multicycle_o = 1'b1; + end + end + default: ; + endcase + end + + default: ; + endcase + end else begin + alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate + end + end + + 3'b101: begin + if (RV32B != RV32BNone) begin + if (instr_alu[26] == 1'b1) begin + alu_operator_o = ALU_FSR; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end else begin + unique case (instr_alu[31:27]) + 5'b0_0000: alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate + 5'b0_1000: alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate + 5'b0_0100: alu_operator_o = ALU_SRO; // Shift Right Ones by Immediate + 5'b0_1001: alu_operator_o = ALU_SBEXT; // Extract bit specified by immediate. + 5'b0_1100: begin + alu_operator_o = ALU_ROR; // Rotate Right by Immediate + alu_multicycle_o = 1'b1; + end + 5'b0_1101: alu_operator_o = ALU_GREV; // General Reverse with Imm Control Val + 5'b0_0101: alu_operator_o = ALU_GORC; // General Or-combine with Imm Control Val + // Unshuffle with Immediate Control Value + 5'b0_0001: begin + if (RV32B == RV32BFull) begin + if (instr_alu[26] == 1'b0) alu_operator_o = ALU_UNSHFL; + end + end + default: ; + endcase + end + + end else begin + if (instr_alu[31:27] == 5'b0_0000) begin + alu_operator_o = ALU_SRL; // Shift Right Logical by Immediate + end else if (instr_alu[31:27] == 5'b0_1000) begin + alu_operator_o = ALU_SRA; // Shift Right Arithmetically by Immediate + end + end + end + + default: ; + endcase + end + + OPCODE_OP: begin // Register-Register ALU operation + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + + if (instr_alu[26]) begin + if (RV32B != RV32BNone) begin + unique case ({instr_alu[26:25], instr_alu[14:12]}) + {2'b11, 3'b001}: begin + alu_operator_o = ALU_CMIX; // cmix + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b11, 3'b101}: begin + alu_operator_o = ALU_CMOV; // cmov + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b10, 3'b001}: begin + alu_operator_o = ALU_FSL; // fsl + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + {2'b10, 3'b101}: begin + alu_operator_o = ALU_FSR; // fsr + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) begin + use_rs3_d = 1'b1; + end else begin + use_rs3_d = 1'b0; + end + end + default: ; + endcase + end + end else begin + unique case ({instr_alu[31:25], instr_alu[14:12]}) + // RV32I ALU operations + {7'b000_0000, 3'b000}: alu_operator_o = ALU_ADD; // Add + {7'b010_0000, 3'b000}: alu_operator_o = ALU_SUB; // Sub + {7'b000_0000, 3'b010}: alu_operator_o = ALU_SLT; // Set Lower Than + {7'b000_0000, 3'b011}: alu_operator_o = ALU_SLTU; // Set Lower Than Unsigned + {7'b000_0000, 3'b100}: alu_operator_o = ALU_XOR; // Xor + {7'b000_0000, 3'b110}: alu_operator_o = ALU_OR; // Or + {7'b000_0000, 3'b111}: alu_operator_o = ALU_AND; // And + {7'b000_0000, 3'b001}: alu_operator_o = ALU_SLL; // Shift Left Logical + {7'b000_0000, 3'b101}: alu_operator_o = ALU_SRL; // Shift Right Logical + {7'b010_0000, 3'b101}: alu_operator_o = ALU_SRA; // Shift Right Arithmetic + + // RV32B ALU Operations + {7'b001_0000, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SLO; // slo + {7'b001_0000, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SRO; // sro + {7'b011_0000, 3'b001}: begin + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROL; // rol + alu_multicycle_o = 1'b1; + end + end + {7'b011_0000, 3'b101}: begin + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROR; // ror + alu_multicycle_o = 1'b1; + end + end + + {7'b000_0101, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_MIN; // min + {7'b000_0101, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAX; // max + {7'b000_0101, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_MINU; // minu + {7'b000_0101, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAXU; // maxu + + {7'b000_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACK; // pack + {7'b010_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKU; // packu + {7'b000_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKH; // packh + + {7'b010_0000, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_XNOR; // xnor + {7'b010_0000, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_ORN; // orn + {7'b010_0000, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_ANDN; // andn + + // RV32B zbs + {7'b010_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBCLR; // sbclr + {7'b001_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBSET; // sbset + {7'b011_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBINV; // sbinv + {7'b010_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_SBEXT; // sbext + + // RV32B zbf + {7'b010_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_BFP; // bfp + + // RV32B zbp + {7'b011_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GREV; // grev + {7'b001_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GORC; // grev + {7'b000_0100, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_SHFL; // shfl + {7'b000_0100, 3'b101}: if (RV32B == RV32BFull) alu_operator_o = ALU_UNSHFL; // unshfl + + // RV32B zbc + {7'b000_0101, 3'b001}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMUL; // clmul + {7'b000_0101, 3'b010}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMULR; // clmulr + {7'b000_0101, 3'b011}: if (RV32B == RV32BFull) alu_operator_o = ALU_CLMULH; // clmulh + + // RV32B zbe + {7'b010_0100, 3'b110}: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BDEP; // bdep + alu_multicycle_o = 1'b1; + end + end + {7'b000_0100, 3'b110}: begin + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BEXT; // bext + alu_multicycle_o = 1'b1; + end + end + + // RV32M instructions, all use the same ALU operation + {7'b000_0001, 3'b000}: begin // mul + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b001}: begin // mulh + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b010}: begin // mulhsu + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b011}: begin // mulhu + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b100}: begin // div + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b101}: begin // divu + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b110}: begin // rem + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + {7'b000_0001, 3'b111}: begin // remu + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone) ? 1'b0 : 1'b1; + end + + default: ; + endcase + end + end + + ///////////// + // Special // + ///////////// + + OPCODE_MISC_MEM: begin + unique case (instr_alu[14:12]) + 3'b000: begin + // FENCE is treated as a NOP since all memory operations are already strictly ordered. + alu_operator_o = ALU_ADD; // nop + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end + 3'b001: begin + // FENCE.I will flush the IF stage, prefetch buffer and ICache if present. + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_INCR_PC; + end else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + default: ; + endcase + end + + OPCODE_SYSTEM: begin + if (instr_alu[14:12] == 3'b000) begin + // non CSR related SYSTEM instructions + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end else begin + // instruction to read/modify CSR + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_Z; + imm_b_mux_sel_o = IMM_B_I; // CSR address is encoded in I imm + + if (instr_alu[14]) begin + // rs1 field is used as immediate + alu_op_a_mux_sel_o = OP_A_IMM; + end else begin + alu_op_a_mux_sel_o = OP_A_REG_A; + end + end + + end + default: ; + endcase + end + + // do not enable multdiv in case of illegal instruction exceptions + assign mult_en_o = illegal_insn ? 1'b0 : mult_sel_o; + assign div_en_o = illegal_insn ? 1'b0 : div_sel_o; + + // make sure instructions accessing non-available registers in RV32E cause illegal + // instruction exceptions + assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; + + // do not propgate regfile write enable if non-available registers are accessed in RV32E + assign rf_we_o = rf_we & ~illegal_reg_rv32e; + + // Not all bits are used + assign unused_instr_alu = {instr_alu[19:15],instr_alu[11:7]}; + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexRegImmAluOpKnown, (opcode == OPCODE_OP_IMM) |-> + !$isunknown(instr[14:12])) +endmodule // controller diff --git a/flow/designs/src/ibex_sv/ibex_ex_block.sv b/flow/designs/src/ibex_sv/ibex_ex_block.sv new file mode 100644 index 0000000000..62e039645f --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_ex_block.sv @@ -0,0 +1,199 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Execution stage + * + * Execution block: Hosts ALU and MUL/DIV unit + */ +module ibex_ex_block #( + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit BranchTargetALU = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // ALU + input ibex_pkg::alu_op_e alu_operator_i, + input logic [31:0] alu_operand_a_i, + input logic [31:0] alu_operand_b_i, + input logic alu_instr_first_cycle_i, + + // Branch Target ALU + // All of these signals are unusued when BranchTargetALU == 0 + input logic [31:0] bt_a_operand_i, + input logic [31:0] bt_b_operand_i, + + // Multiplier/Divider + input ibex_pkg::md_op_e multdiv_operator_i, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input logic [1:0] multdiv_signed_mode_i, + input logic [31:0] multdiv_operand_a_i, + input logic [31:0] multdiv_operand_b_i, + input logic multdiv_ready_id_i, + input logic data_ind_timing_i, + + // intermediate val reg + output logic [1:0] imd_val_we_o, + output logic [33:0] imd_val_d_o[2], + input logic [33:0] imd_val_q_i[2], + + // Outputs + output logic [31:0] alu_adder_result_ex_o, // to LSU + output logic [31:0] result_ex_o, + output logic [31:0] branch_target_o, // to IF + output logic branch_decision_o, // to ID + + output logic ex_valid_o // EX has valid output +); + + import ibex_pkg::*; + + logic [31:0] alu_result, multdiv_result; + + logic [32:0] multdiv_alu_operand_b, multdiv_alu_operand_a; + logic [33:0] alu_adder_result_ext; + logic alu_cmp_result, alu_is_equal_result; + logic multdiv_valid; + logic multdiv_sel; + logic [31:0] alu_imd_val_q[2]; + logic [31:0] alu_imd_val_d[2]; + logic [ 1:0] alu_imd_val_we; + logic [33:0] multdiv_imd_val_d[2]; + logic [ 1:0] multdiv_imd_val_we; + + /* + The multdiv_i output is never selected if RV32M=RV32MNone + At synthesis time, all the combinational and sequential logic + from the multdiv_i module are eliminated + */ + if (RV32M != RV32MNone) begin : gen_multdiv_m + assign multdiv_sel = mult_sel_i | div_sel_i; + end else begin : gen_multdiv_no_m + assign multdiv_sel = 1'b0; + end + + // Intermediate Value Register Mux + assign imd_val_d_o[0] = multdiv_sel ? multdiv_imd_val_d[0] : {2'b0, alu_imd_val_d[0]}; + assign imd_val_d_o[1] = multdiv_sel ? multdiv_imd_val_d[1] : {2'b0, alu_imd_val_d[1]}; + assign imd_val_we_o = multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we; + + assign alu_imd_val_q = '{imd_val_q_i[0][31:0], imd_val_q_i[1][31:0]}; + + assign result_ex_o = multdiv_sel ? multdiv_result : alu_result; + + // branch handling + assign branch_decision_o = alu_cmp_result; + + if (BranchTargetALU) begin : g_branch_target_alu + logic [32:0] bt_alu_result; + logic unused_bt_carry; + + assign bt_alu_result = bt_a_operand_i + bt_b_operand_i; + + assign unused_bt_carry = bt_alu_result[32]; + assign branch_target_o = bt_alu_result[31:0]; + end else begin : g_no_branch_target_alu + // Unused bt_operand signals cause lint errors, this avoids them + logic [31:0] unused_bt_a_operand, unused_bt_b_operand; + + assign unused_bt_a_operand = bt_a_operand_i; + assign unused_bt_b_operand = bt_b_operand_i; + + assign branch_target_o = alu_adder_result_ex_o; + end + + ///////// + // ALU // + ///////// + + ibex_alu #( + .RV32B(RV32B) + ) alu_i ( + .operator_i ( alu_operator_i ), + .operand_a_i ( alu_operand_a_i ), + .operand_b_i ( alu_operand_b_i ), + .instr_first_cycle_i ( alu_instr_first_cycle_i ), + .imd_val_q_i ( alu_imd_val_q ), + .imd_val_we_o ( alu_imd_val_we ), + .imd_val_d_o ( alu_imd_val_d ), + .multdiv_operand_a_i ( multdiv_alu_operand_a ), + .multdiv_operand_b_i ( multdiv_alu_operand_b ), + .multdiv_sel_i ( multdiv_sel ), + .adder_result_o ( alu_adder_result_ex_o ), + .adder_result_ext_o ( alu_adder_result_ext ), + .result_o ( alu_result ), + .comparison_result_o ( alu_cmp_result ), + .is_equal_result_o ( alu_is_equal_result ) + ); + + //////////////// + // Multiplier // + //////////////// + + if (RV32M == RV32MSlow) begin : gen_multdiv_slow + ibex_multdiv_slow multdiv_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mult_en_i ( mult_en_i ), + .div_en_i ( div_en_i ), + .mult_sel_i ( mult_sel_i ), + .div_sel_i ( div_sel_i ), + .operator_i ( multdiv_operator_i ), + .signed_mode_i ( multdiv_signed_mode_i ), + .op_a_i ( multdiv_operand_a_i ), + .op_b_i ( multdiv_operand_b_i ), + .alu_adder_ext_i ( alu_adder_result_ext ), + .alu_adder_i ( alu_adder_result_ex_o ), + .equal_to_zero_i ( alu_is_equal_result ), + .data_ind_timing_i ( data_ind_timing_i ), + .valid_o ( multdiv_valid ), + .alu_operand_a_o ( multdiv_alu_operand_a ), + .alu_operand_b_o ( multdiv_alu_operand_b ), + .imd_val_q_i ( imd_val_q_i ), + .imd_val_d_o ( multdiv_imd_val_d ), + .imd_val_we_o ( multdiv_imd_val_we ), + .multdiv_ready_id_i ( multdiv_ready_id_i ), + .multdiv_result_o ( multdiv_result ) + ); + end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast + ibex_multdiv_fast # ( + .RV32M ( RV32M ) + ) multdiv_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mult_en_i ( mult_en_i ), + .div_en_i ( div_en_i ), + .mult_sel_i ( mult_sel_i ), + .div_sel_i ( div_sel_i ), + .operator_i ( multdiv_operator_i ), + .signed_mode_i ( multdiv_signed_mode_i ), + .op_a_i ( multdiv_operand_a_i ), + .op_b_i ( multdiv_operand_b_i ), + .alu_operand_a_o ( multdiv_alu_operand_a ), + .alu_operand_b_o ( multdiv_alu_operand_b ), + .alu_adder_ext_i ( alu_adder_result_ext ), + .alu_adder_i ( alu_adder_result_ex_o ), + .equal_to_zero_i ( alu_is_equal_result ), + .data_ind_timing_i ( data_ind_timing_i ), + .imd_val_q_i ( imd_val_q_i ), + .imd_val_d_o ( multdiv_imd_val_d ), + .imd_val_we_o ( multdiv_imd_val_we ), + .multdiv_ready_id_i ( multdiv_ready_id_i ), + .valid_o ( multdiv_valid ), + .multdiv_result_o ( multdiv_result ) + ); + end + + // Multiplier/divider may require multiple cycles. The ALU output is valid in the same cycle + // unless the intermediate result register is being written (which indicates this isn't the + // final cycle of ALU operation). + assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we); + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv b/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv new file mode 100644 index 0000000000..52fcc8ea90 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_fetch_fifo.sv @@ -0,0 +1,250 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Fetch Fifo for 32 bit memory interface + * + * input port: send address and data to the FIFO + * clear_i clears the FIFO for the following cycle, including any new request + */ + +`include "prim_assert.sv" + +module ibex_fetch_fifo #( + parameter int unsigned NUM_REQS = 2 +) ( + input logic clk_i, + input logic rst_ni, + + // control signals + input logic clear_i, // clears the contents of the FIFO + output logic [NUM_REQS-1:0] busy_o, + + // input port + input logic in_valid_i, + input logic [31:0] in_addr_i, + input logic [31:0] in_rdata_i, + input logic in_err_i, + + // output port + output logic out_valid_o, + input logic out_ready_i, + output logic [31:0] out_addr_o, + output logic [31:0] out_addr_next_o, + output logic [31:0] out_rdata_o, + output logic out_err_o, + output logic out_err_plus2_o +); + + localparam int unsigned DEPTH = NUM_REQS+1; + + // index 0 is used for output + logic [DEPTH-1:0] [31:0] rdata_d, rdata_q; + logic [DEPTH-1:0] err_d, err_q; + logic [DEPTH-1:0] valid_d, valid_q; + logic [DEPTH-1:0] lowest_free_entry; + logic [DEPTH-1:0] valid_pushed, valid_popped; + logic [DEPTH-1:0] entry_en; + + logic pop_fifo; + logic [31:0] rdata, rdata_unaligned; + logic err, err_unaligned, err_plus2; + logic valid, valid_unaligned; + + logic aligned_is_compressed, unaligned_is_compressed; + + logic addr_incr_two; + logic [31:1] instr_addr_next; + logic [31:1] instr_addr_d, instr_addr_q; + logic instr_addr_en; + logic unused_addr_in; + + ///////////////// + // Output port // + ///////////////// + + assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i; + assign err = valid_q[0] ? err_q[0] : in_err_i; + assign valid = valid_q[0] | in_valid_i; + + // The FIFO contains word aligned memory fetches, but the instructions contained in each entry + // might be half-word aligned (due to compressed instructions) + // e.g. + // | 31 16 | 15 0 | + // FIFO entry 0 | Instr 1 [15:0] | Instr 0 [15:0] | + // FIFO entry 1 | Instr 2 [15:0] | Instr 1 [31:16] | + // + // The FIFO also has a direct bypass path, so a complete instruction might be made up of data + // from the FIFO and new incoming data. + // + + // Construct the output data for an unaligned instruction + assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} : + {in_rdata_i[15:0], rdata[31:16]}; + + // If entry[1] is valid, an error can come from entry[0] or entry[1], unless the + // instruction in entry[0] is compressed (entry[1] is a new instruction) + // If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming + // data, unless the instruction in entry[0] is compressed + // If entry[0] is not valid, the error must come from the incoming data + assign err_unaligned = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) : + ((valid_q[0] & err_q[0]) | + (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))); + + // Record when an error is caused by the second half of an unaligned 32bit instruction. + // Only needs to be correct when unaligned and if err_unaligned is set + assign err_plus2 = valid_q[1] ? (err_q[1] & ~err_q[0]) : + (in_err_i & valid_q[0] & ~err_q[0]); + + // An uncompressed unaligned instruction is only valid if both parts are available + assign valid_unaligned = valid_q[1] ? 1'b1 : + (valid_q[0] & in_valid_i); + + // If there is an error, rdata is unknown + assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err; + assign aligned_is_compressed = (rdata[ 1: 0] != 2'b11) & ~err; + + //////////////////////////////////////// + // Instruction aligner (if unaligned) // + //////////////////////////////////////// + + always_comb begin + if (out_addr_o[1]) begin + // unaligned case + out_rdata_o = rdata_unaligned; + out_err_o = err_unaligned; + out_err_plus2_o = err_plus2; + + if (unaligned_is_compressed) begin + out_valid_o = valid; + end else begin + out_valid_o = valid_unaligned; + end + end else begin + // aligned case + out_rdata_o = rdata; + out_err_o = err; + out_err_plus2_o = 1'b0; + out_valid_o = valid; + end + end + + ///////////////////////// + // Instruction address // + ///////////////////////// + + // Update the address on branches and every time an instruction is driven + assign instr_addr_en = clear_i | (out_ready_i & out_valid_o); + + // Increment the address by two every time a compressed instruction is popped + assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed : + aligned_is_compressed; + + assign instr_addr_next = (instr_addr_q[31:1] + + // Increment address by 4 or 2 + {29'd0,~addr_incr_two,addr_incr_two}); + + assign instr_addr_d = clear_i ? in_addr_i[31:1] : + instr_addr_next; + + always_ff @(posedge clk_i) begin + if (instr_addr_en) begin + instr_addr_q <= instr_addr_d; + end + end + + // Output both PC of current instruction and instruction following. PC of instruction following is + // required for the branch predictor. It's used to fetch the instruction following a branch that + // was not-taken but (mis)predicted taken. + assign out_addr_next_o = {instr_addr_next, 1'b0}; + assign out_addr_o = {instr_addr_q, 1'b0}; + + // The LSB of the address is unused, since all addresses are halfword aligned + assign unused_addr_in = in_addr_i[0]; + + ///////////////// + // FIFO status // + ///////////////// + + // Indicate the fill level of fifo-entries. This is used to determine when a new request can be + // made on the bus. The prefetch buffer only needs to know about the upper entries which overlap + // with NUM_REQS. + assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS]; + + ///////////////////// + // FIFO management // + ///////////////////// + + // Since an entry can contain unaligned instructions, popping an entry can leave the entry valid + assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]); + + for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next + // Calculate lowest free entry (write pointer) + if (i == 0) begin : g_ent0 + assign lowest_free_entry[i] = ~valid_q[i]; + end else begin : g_ent_others + assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1]; + end + + // An entry is set when an incoming request chooses the lowest available entry + assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | + valid_q[i]; + // Popping the FIFO shifts all entries down + assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i]; + // All entries are wiped out on a clear + assign valid_d[i] = valid_popped[i] & ~clear_i; + + // data flops are enabled if there is new data to shift into it, or + assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) | + // a new request is incoming and this is the lowest free entry + (in_valid_i & lowest_free_entry[i] & ~pop_fifo); + + // take the next entry or the incoming data + assign rdata_d[i] = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i; + assign err_d [i] = valid_q[i+1] ? err_q [i+1] : in_err_i; + end + // The top entry is similar but with simpler muxing + assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2]; + assign valid_pushed [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]); + assign valid_popped [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1]; + assign valid_d [DEPTH-1] = valid_popped[DEPTH-1] & ~clear_i; + assign entry_en[DEPTH-1] = in_valid_i & lowest_free_entry[DEPTH-1]; + assign rdata_d [DEPTH-1] = in_rdata_i; + assign err_d [DEPTH-1] = in_err_i; + + //////////////////// + // FIFO registers // + //////////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid_q <= '0; + end else begin + valid_q <= valid_d; + end + end + + for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs + always_ff @(posedge clk_i) begin + if (entry_en[i]) begin + rdata_q[i] <= rdata_d[i]; + err_q[i] <= err_d[i]; + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Must not push and pop simultaneously when FIFO full. + `ASSERT(IbexFetchFifoPushPopFull, + (in_valid_i && pop_fifo) |-> (!valid_q[DEPTH-1] || clear_i)) + + // Must not push to FIFO when full. + `ASSERT(IbexFetchFifoPushFull, + (in_valid_i) |-> (!valid_q[DEPTH-1] || clear_i)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_id_stage.sv b/flow/designs/src/ibex_sv/ibex_id_stage.sv new file mode 100644 index 0000000000..7c91eae1ff --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_id_stage.sv @@ -0,0 +1,1044 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`ifdef RISCV_FORMAL + `define RVFI +`endif + +/** + * Instruction Decode Stage + * + * Decode stage of the core. It decodes the instructions and hosts the register + * file. + */ + +`include "prim_assert.sv" + +module ibex_id_stage #( + parameter bit RV32E = 0, + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast, + parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone, + parameter bit DataIndTiming = 1'b0, + parameter bit BranchTargetALU = 0, + parameter bit SpecBranch = 0, + parameter bit WritebackStage = 0, + parameter bit BranchPredictor = 0 +) ( + input logic clk_i, + input logic rst_ni, + + output logic ctrl_busy_o, + output logic illegal_insn_o, + + // Interface to IF stage + input logic instr_valid_i, + input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers + input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers + input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers + input logic instr_is_compressed_i, + input logic instr_bp_taken_i, + output logic instr_req_o, + output logic instr_first_cycle_id_o, + output logic instr_valid_clear_o, // kill instr in IF-ID reg + output logic id_in_ready_o, // ID stage is ready for next instr + output logic icache_inval_o, + + // Jumps and branches + input logic branch_decision_i, + + // IF and ID stage signals + output logic pc_set_o, + output logic pc_set_spec_o, + output ibex_pkg::pc_sel_e pc_mux_o, + output logic nt_branch_mispredict_o, + output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, + output ibex_pkg::exc_cause_e exc_cause_o, + + input logic illegal_c_insn_i, + input logic instr_fetch_err_i, + input logic instr_fetch_err_plus2_i, + + input logic [31:0] pc_id_i, + + // Stalls + input logic ex_valid_i, // EX stage has valid output + input logic lsu_resp_valid_i, // LSU has valid output, or is done + // ALU + output ibex_pkg::alu_op_e alu_operator_ex_o, + output logic [31:0] alu_operand_a_ex_o, + output logic [31:0] alu_operand_b_ex_o, + + // Multicycle Operation Stage Register + input logic [1:0] imd_val_we_ex_i, + input logic [33:0] imd_val_d_ex_i[2], + output logic [33:0] imd_val_q_ex_o[2], + + // Branch target ALU + output logic [31:0] bt_a_operand_o, + output logic [31:0] bt_b_operand_o, + + // MUL, DIV + output logic mult_en_ex_o, + output logic div_en_ex_o, + output logic mult_sel_ex_o, + output logic div_sel_ex_o, + output ibex_pkg::md_op_e multdiv_operator_ex_o, + output logic [1:0] multdiv_signed_mode_ex_o, + output logic [31:0] multdiv_operand_a_ex_o, + output logic [31:0] multdiv_operand_b_ex_o, + output logic multdiv_ready_id_o, + + // CSR + output logic csr_access_o, + output ibex_pkg::csr_op_e csr_op_o, + output logic csr_op_en_o, + output logic csr_save_if_o, + output logic csr_save_id_o, + output logic csr_save_wb_o, + output logic csr_restore_mret_id_o, + output logic csr_restore_dret_id_o, + output logic csr_save_cause_o, + output logic [31:0] csr_mtval_o, + input ibex_pkg::priv_lvl_e priv_mode_i, + input logic csr_mstatus_tw_i, + input logic illegal_csr_insn_i, + input logic data_ind_timing_i, + + // Interface to load store unit + output logic lsu_req_o, + output logic lsu_we_o, + output logic [1:0] lsu_type_o, + output logic lsu_sign_ext_o, + output logic [31:0] lsu_wdata_o, + + input logic lsu_req_done_i, // Data req to LSU is complete and + // instruction can move to writeback + // (only relevant where writeback stage is + // present) + + input logic lsu_addr_incr_req_i, + input logic [31:0] lsu_addr_last_i, + + // Interrupt signals + input logic csr_mstatus_mie_i, + input logic irq_pending_i, + input ibex_pkg::irqs_t irqs_i, + input logic irq_nm_i, + output logic nmi_mode_o, + + input logic lsu_load_err_i, + input logic lsu_store_err_i, + + // Debug Signal + output logic debug_mode_o, + output ibex_pkg::dbg_cause_e debug_cause_o, + output logic debug_csr_save_o, + input logic debug_req_i, + input logic debug_single_step_i, + input logic debug_ebreakm_i, + input logic debug_ebreaku_i, + input logic trigger_match_i, + + // Write back signal + input logic [31:0] result_ex_i, + input logic [31:0] csr_rdata_i, + + // Register file read + output logic [4:0] rf_raddr_a_o, + input logic [31:0] rf_rdata_a_i, + output logic [4:0] rf_raddr_b_o, + input logic [31:0] rf_rdata_b_i, + output logic rf_ren_a_o, + output logic rf_ren_b_o, + + // Register file write (via writeback) + output logic [4:0] rf_waddr_id_o, + output logic [31:0] rf_wdata_id_o, + output logic rf_we_id_o, + output logic rf_rd_a_wb_match_o, + output logic rf_rd_b_wb_match_o, + + // Register write information from writeback (for resolving data hazards) + input logic [4:0] rf_waddr_wb_i, + input logic [31:0] rf_wdata_fwd_wb_i, + input logic rf_write_wb_i, + + output logic en_wb_o, + output ibex_pkg::wb_instr_type_e instr_type_wb_o, + output logic instr_perf_count_id_o, + input logic ready_wb_i, + input logic outstanding_load_wb_i, + input logic outstanding_store_wb_i, + + // Performance Counters + output logic perf_jump_o, // executing a jump instr + output logic perf_branch_o, // executing a branch instr + output logic perf_tbranch_o, // executing a taken branch instr + output logic perf_dside_wait_o, // instruction in ID/EX is awaiting memory + // access to finish before proceeding + output logic perf_mul_wait_o, + output logic perf_div_wait_o, + output logic instr_id_done_o +); + + import ibex_pkg::*; + + // Decoder/Controller, ID stage internal signals + logic illegal_insn_dec; + logic ebrk_insn; + logic mret_insn_dec; + logic dret_insn_dec; + logic ecall_insn_dec; + logic wfi_insn_dec; + + logic wb_exception; + + logic branch_in_dec; + logic branch_spec, branch_set_spec; + logic branch_set, branch_set_d; + logic branch_not_set; + logic branch_taken; + logic jump_in_dec; + logic jump_set_dec; + logic jump_set; + + logic instr_first_cycle; + logic instr_executing; + logic instr_done; + logic controller_run; + logic stall_ld_hz; + logic stall_mem; + logic stall_multdiv; + logic stall_branch; + logic stall_jump; + logic stall_id; + logic stall_wb; + logic flush_id; + logic multicycle_done; + + // Immediate decoding and sign extension + logic [31:0] imm_i_type; + logic [31:0] imm_s_type; + logic [31:0] imm_b_type; + logic [31:0] imm_u_type; + logic [31:0] imm_j_type; + logic [31:0] zimm_rs1_type; + + logic [31:0] imm_a; // contains the immediate for operand b + logic [31:0] imm_b; // contains the immediate for operand b + + // Register file interface + + rf_wd_sel_e rf_wdata_sel; + logic rf_we_dec, rf_we_raw; + logic rf_ren_a, rf_ren_b; + + assign rf_ren_a_o = rf_ren_a; + assign rf_ren_b_o = rf_ren_b; + + logic [31:0] rf_rdata_a_fwd; + logic [31:0] rf_rdata_b_fwd; + + // ALU Control + alu_op_e alu_operator; + op_a_sel_e alu_op_a_mux_sel, alu_op_a_mux_sel_dec; + op_b_sel_e alu_op_b_mux_sel, alu_op_b_mux_sel_dec; + logic alu_multicycle_dec; + logic stall_alu; + + logic [33:0] imd_val_q[2]; + + op_a_sel_e bt_a_mux_sel; + imm_b_sel_e bt_b_mux_sel; + + imm_a_sel_e imm_a_mux_sel; + imm_b_sel_e imm_b_mux_sel, imm_b_mux_sel_dec; + + // Multiplier Control + logic mult_en_id, mult_en_dec; // use integer multiplier + logic div_en_id, div_en_dec; // use integer division or reminder + logic multdiv_en_dec; + md_op_e multdiv_operator; + logic [1:0] multdiv_signed_mode; + + // Data Memory Control + logic lsu_we; + logic [1:0] lsu_type; + logic lsu_sign_ext; + logic lsu_req, lsu_req_dec; + logic data_req_allowed; + + // CSR control + logic csr_pipe_flush; + + logic [31:0] alu_operand_a; + logic [31:0] alu_operand_b; + + ///////////// + // LSU Mux // + ///////////// + + // Misaligned loads/stores result in two aligned loads/stores, compute second address + assign alu_op_a_mux_sel = lsu_addr_incr_req_i ? OP_A_FWD : alu_op_a_mux_sel_dec; + assign alu_op_b_mux_sel = lsu_addr_incr_req_i ? OP_B_IMM : alu_op_b_mux_sel_dec; + assign imm_b_mux_sel = lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec; + + /////////////////// + // Operand MUXES // + /////////////////// + + // Main ALU immediate MUX for Operand A + assign imm_a = (imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : '0; + + // Main ALU MUX for Operand A + always_comb begin : alu_operand_a_mux + unique case (alu_op_a_mux_sel) + OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; + OP_A_FWD: alu_operand_a = lsu_addr_last_i; + OP_A_CURRPC: alu_operand_a = pc_id_i; + OP_A_IMM: alu_operand_a = imm_a; + default: alu_operand_a = pc_id_i; + endcase + end + + if (BranchTargetALU) begin : g_btalu_muxes + // Branch target ALU operand A mux + always_comb begin : bt_operand_a_mux + unique case (bt_a_mux_sel) + OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; + OP_A_CURRPC: bt_a_operand_o = pc_id_i; + default: bt_a_operand_o = pc_id_i; + endcase + end + + // Branch target ALU operand B mux + always_comb begin : bt_immediate_b_mux + unique case (bt_b_mux_sel) + IMM_B_I: bt_b_operand_o = imm_i_type; + IMM_B_B: bt_b_operand_o = imm_b_type; + IMM_B_J: bt_b_operand_o = imm_j_type; + IMM_B_INCR_PC: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4; + default: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4; + endcase + end + + // Reduced main ALU immediate MUX for Operand B + always_comb begin : immediate_b_mux + unique case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4; + IMM_B_INCR_ADDR: imm_b = 32'h4; + default: imm_b = 32'h4; + endcase + end + `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { + IMM_B_I, + IMM_B_S, + IMM_B_U, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR}) + end else begin : g_nobtalu + op_a_sel_e unused_a_mux_sel; + imm_b_sel_e unused_b_mux_sel; + + assign unused_a_mux_sel = bt_a_mux_sel; + assign unused_b_mux_sel = bt_b_mux_sel; + assign bt_a_operand_o = '0; + assign bt_b_operand_o = '0; + + // Full main ALU immediate MUX for Operand B + always_comb begin : immediate_b_mux + unique case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_B: imm_b = imm_b_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_J: imm_b = imm_j_type; + IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4; + IMM_B_INCR_ADDR: imm_b = 32'h4; + default: imm_b = 32'h4; + endcase + end + `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside { + IMM_B_I, + IMM_B_S, + IMM_B_B, + IMM_B_U, + IMM_B_J, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR}) + end + + // ALU MUX for Operand B + assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : rf_rdata_b_fwd; + + ///////////////////////////////////////// + // Multicycle Operation Stage Register // + ///////////////////////////////////////// + + for (genvar i=0; i<2; i++) begin : gen_intermediate_val_reg + always_ff @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg + if (!rst_ni) begin + imd_val_q[i] <= '0; + end else if (imd_val_we_ex_i[i]) begin + imd_val_q[i] <= imd_val_d_ex_i[i]; + end + end + end + + assign imd_val_q_ex_o = imd_val_q; + + /////////////////////// + // Register File MUX // + /////////////////////// + + // Suppress register write if there is an illegal CSR access or instruction is not executing + assign rf_we_id_o = rf_we_raw & instr_executing & ~illegal_csr_insn_i; + + // Register file write data mux + always_comb begin : rf_wdata_id_mux + unique case (rf_wdata_sel) + RF_WD_EX: rf_wdata_id_o = result_ex_i; + RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; + default: rf_wdata_id_o = result_ex_i; + endcase + end + + ///////////// + // Decoder // + ///////////// + + ibex_decoder #( + .RV32E ( RV32E ), + .RV32M ( RV32M ), + .RV32B ( RV32B ), + .BranchTargetALU ( BranchTargetALU ) + ) decoder_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + // controller + .illegal_insn_o ( illegal_insn_dec ), + .ebrk_insn_o ( ebrk_insn ), + .mret_insn_o ( mret_insn_dec ), + .dret_insn_o ( dret_insn_dec ), + .ecall_insn_o ( ecall_insn_dec ), + .wfi_insn_o ( wfi_insn_dec ), + .jump_set_o ( jump_set_dec ), + .branch_taken_i ( branch_taken ), + .icache_inval_o ( icache_inval_o ), + + // from IF-ID pipeline register + .instr_first_cycle_i ( instr_first_cycle ), + .instr_rdata_i ( instr_rdata_i ), + .instr_rdata_alu_i ( instr_rdata_alu_i ), + .illegal_c_insn_i ( illegal_c_insn_i ), + + // immediates + .imm_a_mux_sel_o ( imm_a_mux_sel ), + .imm_b_mux_sel_o ( imm_b_mux_sel_dec ), + .bt_a_mux_sel_o ( bt_a_mux_sel ), + .bt_b_mux_sel_o ( bt_b_mux_sel ), + + .imm_i_type_o ( imm_i_type ), + .imm_s_type_o ( imm_s_type ), + .imm_b_type_o ( imm_b_type ), + .imm_u_type_o ( imm_u_type ), + .imm_j_type_o ( imm_j_type ), + .zimm_rs1_type_o ( zimm_rs1_type ), + + // register file + .rf_wdata_sel_o ( rf_wdata_sel ), + .rf_we_o ( rf_we_dec ), + + .rf_raddr_a_o ( rf_raddr_a_o ), + .rf_raddr_b_o ( rf_raddr_b_o ), + .rf_waddr_o ( rf_waddr_id_o ), + .rf_ren_a_o ( rf_ren_a ), + .rf_ren_b_o ( rf_ren_b ), + + // ALU + .alu_operator_o ( alu_operator ), + .alu_op_a_mux_sel_o ( alu_op_a_mux_sel_dec ), + .alu_op_b_mux_sel_o ( alu_op_b_mux_sel_dec ), + .alu_multicycle_o ( alu_multicycle_dec ), + + // MULT & DIV + .mult_en_o ( mult_en_dec ), + .div_en_o ( div_en_dec ), + .mult_sel_o ( mult_sel_ex_o ), + .div_sel_o ( div_sel_ex_o ), + .multdiv_operator_o ( multdiv_operator ), + .multdiv_signed_mode_o ( multdiv_signed_mode ), + + // CSRs + .csr_access_o ( csr_access_o ), + .csr_op_o ( csr_op_o ), + + // LSU + .data_req_o ( lsu_req_dec ), + .data_we_o ( lsu_we ), + .data_type_o ( lsu_type ), + .data_sign_extension_o ( lsu_sign_ext ), + + // jump/branches + .jump_in_dec_o ( jump_in_dec ), + .branch_in_dec_o ( branch_in_dec ) + ); + + ///////////////////////////////// + // CSR-related pipline flushes // + ///////////////////////////////// + always_comb begin : csr_pipeline_flushes + csr_pipe_flush = 1'b0; + + // A pipeline flush is needed to let the controller react after modifying certain CSRs: + // - When enabling interrupts, pending IRQs become visible to the controller only during + // the next cycle. If during that cycle the core disables interrupts again, it does not + // see any pending IRQs and consequently does not start to handle interrupts. + // - When modifying debug CSRs - TODO: Check if this is really needed + if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin + if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS || + csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin + csr_pipe_flush = 1'b1; + end + end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin + if (csr_num_e'(instr_rdata_i[31:20]) == CSR_DCSR || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DPC || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH0 || + csr_num_e'(instr_rdata_i[31:20]) == CSR_DSCRATCH1) begin + csr_pipe_flush = 1'b1; + end + end + end + + //////////////// + // Controller // + //////////////// + + assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); + + ibex_controller #( + .WritebackStage ( WritebackStage ), + .BranchPredictor ( BranchPredictor ) + ) controller_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .ctrl_busy_o ( ctrl_busy_o ), + + // decoder related signals + .illegal_insn_i ( illegal_insn_o ), + .ecall_insn_i ( ecall_insn_dec ), + .mret_insn_i ( mret_insn_dec ), + .dret_insn_i ( dret_insn_dec ), + .wfi_insn_i ( wfi_insn_dec ), + .ebrk_insn_i ( ebrk_insn ), + .csr_pipe_flush_i ( csr_pipe_flush ), + + // from IF-ID pipeline + .instr_valid_i ( instr_valid_i ), + .instr_i ( instr_rdata_i ), + .instr_compressed_i ( instr_rdata_c_i ), + .instr_is_compressed_i ( instr_is_compressed_i ), + .instr_bp_taken_i ( instr_bp_taken_i ), + .instr_fetch_err_i ( instr_fetch_err_i ), + .instr_fetch_err_plus2_i ( instr_fetch_err_plus2_i ), + .pc_id_i ( pc_id_i ), + + // to IF-ID pipeline + .instr_valid_clear_o ( instr_valid_clear_o ), + .id_in_ready_o ( id_in_ready_o ), + .controller_run_o ( controller_run ), + + // to prefetcher + .instr_req_o ( instr_req_o ), + .pc_set_o ( pc_set_o ), + .pc_set_spec_o ( pc_set_spec_o ), + .pc_mux_o ( pc_mux_o ), + .nt_branch_mispredict_o ( nt_branch_mispredict_o ), + .exc_pc_mux_o ( exc_pc_mux_o ), + .exc_cause_o ( exc_cause_o ), + + // LSU + .lsu_addr_last_i ( lsu_addr_last_i ), + .load_err_i ( lsu_load_err_i ), + .store_err_i ( lsu_store_err_i ), + .wb_exception_o ( wb_exception ), + + // jump/branch control + .branch_set_i ( branch_set ), + .branch_set_spec_i ( branch_set_spec ), + .branch_not_set_i ( branch_not_set ), + .jump_set_i ( jump_set ), + + // interrupt signals + .csr_mstatus_mie_i ( csr_mstatus_mie_i ), + .irq_pending_i ( irq_pending_i ), + .irqs_i ( irqs_i ), + .irq_nm_i ( irq_nm_i ), + .nmi_mode_o ( nmi_mode_o ), + + // CSR Controller Signals + .csr_save_if_o ( csr_save_if_o ), + .csr_save_id_o ( csr_save_id_o ), + .csr_save_wb_o ( csr_save_wb_o ), + .csr_restore_mret_id_o ( csr_restore_mret_id_o ), + .csr_restore_dret_id_o ( csr_restore_dret_id_o ), + .csr_save_cause_o ( csr_save_cause_o ), + .csr_mtval_o ( csr_mtval_o ), + .priv_mode_i ( priv_mode_i ), + .csr_mstatus_tw_i ( csr_mstatus_tw_i ), + + // Debug Signal + .debug_mode_o ( debug_mode_o ), + .debug_cause_o ( debug_cause_o ), + .debug_csr_save_o ( debug_csr_save_o ), + .debug_req_i ( debug_req_i ), + .debug_single_step_i ( debug_single_step_i ), + .debug_ebreakm_i ( debug_ebreakm_i ), + .debug_ebreaku_i ( debug_ebreaku_i ), + .trigger_match_i ( trigger_match_i ), + + .stall_id_i ( stall_id ), + .stall_wb_i ( stall_wb ), + .flush_id_o ( flush_id ), + .ready_wb_i ( ready_wb_i ), + + // Performance Counters + .perf_jump_o ( perf_jump_o ), + .perf_tbranch_o ( perf_tbranch_o ) + ); + + assign multdiv_en_dec = mult_en_dec | div_en_dec; + + assign lsu_req = instr_executing ? data_req_allowed & lsu_req_dec : 1'b0; + assign mult_en_id = instr_executing ? mult_en_dec : 1'b0; + assign div_en_id = instr_executing ? div_en_dec : 1'b0; + + assign lsu_req_o = lsu_req; + assign lsu_we_o = lsu_we; + assign lsu_type_o = lsu_type; + assign lsu_sign_ext_o = lsu_sign_ext; + assign lsu_wdata_o = rf_rdata_b_fwd; + // csr_op_en_o is set when CSR access should actually happen. + // csv_access_o is set when CSR access instruction is present and is used to compute whether a CSR + // access is illegal. A combinational loop would be created if csr_op_en_o was used along (as + // asserting it for an illegal csr access would result in a flush that would need to deassert it). + assign csr_op_en_o = csr_access_o & instr_executing & instr_id_done_o; + + assign alu_operator_ex_o = alu_operator; + assign alu_operand_a_ex_o = alu_operand_a; + assign alu_operand_b_ex_o = alu_operand_b; + + assign mult_en_ex_o = mult_en_id; + assign div_en_ex_o = div_en_id; + + assign multdiv_operator_ex_o = multdiv_operator; + assign multdiv_signed_mode_ex_o = multdiv_signed_mode; + assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; + assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; + + //////////////////////// + // Branch set control // + //////////////////////// + + if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct + // Branch set fed straight to controller with branch target ALU + // (condition pass/fail used same cycle as generated instruction request) + assign branch_set = branch_set_d; + assign branch_set_spec = branch_spec; + end else begin : g_branch_set_flop + // Branch set flopped without branch target ALU, or in fixed time execution mode + // (condition pass/fail used next cycle where branch target is calculated) + logic branch_set_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + branch_set_q <= 1'b0; + end else begin + branch_set_q <= branch_set_d; + end + end + + // Branches always take two cycles in fixed time execution mode, with or without the branch + // target ALU (to avoid a path from the branch decision into the branch target ALU operand + // muxing). + assign branch_set = (BranchTargetALU && !data_ind_timing_i) ? branch_set_d : branch_set_q; + // Use the speculative branch signal when BTALU is enabled + assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i) ? branch_spec : branch_set_q; + end + + // Branch condition is calculated in the first cycle and flopped for use in the second cycle + // (only used in fixed time execution mode to determine branch destination). + if (DataIndTiming) begin : g_sec_branch_taken + logic branch_taken_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + branch_taken_q <= 1'b0; + end else begin + branch_taken_q <= branch_decision_i; + end + end + + assign branch_taken = ~data_ind_timing_i | branch_taken_q; + + end else begin : g_nosec_branch_taken + + // Signal unused without fixed time execution mode - only taken branches will trigger branch_set + assign branch_taken = 1'b1; + + end + + // Holding branch_set/jump_set high for more than one cycle should not cause a functional issue. + // However it could generate needless prefetch buffer flushes and instruction fetches. The ID/EX + // designs ensures that this never happens for non-predicted branches. + `ASSERT(NeverDoubleBranch, branch_set & ~instr_bp_taken_i |=> ~branch_set) + `ASSERT(NeverDoubleJump, jump_set & ~instr_bp_taken_i |=> ~jump_set) + + /////////////// + // ID-EX FSM // + /////////////// + + typedef enum logic { FIRST_CYCLE, MULTI_CYCLE } id_fsm_e; + id_fsm_e id_fsm_q, id_fsm_d; + + always_ff @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg + if (!rst_ni) begin + id_fsm_q <= FIRST_CYCLE; + end else begin + id_fsm_q <= id_fsm_d; + end + end + + // ID/EX stage can be in two states, FIRST_CYCLE and MULTI_CYCLE. An instruction enters + // MULTI_CYCLE if it requires multiple cycles to complete regardless of stalls and other + // considerations. An instruction may be held in FIRST_CYCLE if it's unable to begin executing + // (this is controlled by instr_executing). + + always_comb begin + id_fsm_d = id_fsm_q; + rf_we_raw = rf_we_dec; + stall_multdiv = 1'b0; + stall_jump = 1'b0; + stall_branch = 1'b0; + stall_alu = 1'b0; + branch_set_d = 1'b0; + branch_spec = 1'b0; + branch_not_set = 1'b0; + jump_set = 1'b0; + perf_branch_o = 1'b0; + + if (instr_executing) begin + unique case (id_fsm_q) + FIRST_CYCLE: begin + unique case (1'b1) + lsu_req_dec: begin + if (!WritebackStage) begin + // LSU operation + id_fsm_d = MULTI_CYCLE; + end else begin + if(~lsu_req_done_i) begin + id_fsm_d = MULTI_CYCLE; + end + end + end + multdiv_en_dec: begin + // MUL or DIV operation + if (~ex_valid_i) begin + // When single-cycle multiply is configured mul can finish in the first cycle so + // only enter MULTI_CYCLE state if a result isn't immediately available + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + stall_multdiv = 1'b1; + end + end + branch_in_dec: begin + // cond branch operation + // All branches take two cycles in fixed time execution mode, regardless of branch + // condition. + id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i)) ? + MULTI_CYCLE : FIRST_CYCLE; + stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; + branch_set_d = branch_decision_i | data_ind_timing_i; + + if (BranchPredictor) begin + branch_not_set = ~branch_decision_i; + end + + // Speculative branch (excludes branch_decision_i) + branch_spec = SpecBranch ? 1'b1 : branch_decision_i; + perf_branch_o = 1'b1; + end + jump_in_dec: begin + // uncond branch operation + // BTALU means jumps only need one cycle + id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE; + stall_jump = ~BranchTargetALU; + jump_set = jump_set_dec; + end + alu_multicycle_dec: begin + stall_alu = 1'b1; + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + end + default: begin + id_fsm_d = FIRST_CYCLE; + end + endcase + end + + MULTI_CYCLE: begin + if(multdiv_en_dec) begin + rf_we_raw = rf_we_dec & ex_valid_i; + end + + if (multicycle_done & ready_wb_i) begin + id_fsm_d = FIRST_CYCLE; + end else begin + stall_multdiv = multdiv_en_dec; + stall_branch = branch_in_dec; + stall_jump = jump_in_dec; + end + end + + default: begin + id_fsm_d = FIRST_CYCLE; + end + endcase + end + end + + // Note for the two-stage configuration ready_wb_i is always set + assign multdiv_ready_id_o = ready_wb_i; + + `ASSERT(StallIDIfMulticycle, (id_fsm_q == FIRST_CYCLE) & (id_fsm_d == MULTI_CYCLE) |-> stall_id) + + // Stall ID/EX stage for reason that relates to instruction in ID/EX + assign stall_id = stall_ld_hz | stall_mem | stall_multdiv | stall_jump | stall_branch | + stall_alu; + + assign instr_done = ~stall_id & ~flush_id & instr_executing; + + // Signal instruction in ID is in it's first cycle. It can remain in its + // first cycle if it is stalled. + assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); + // Used by RVFI to know when to capture register read data + // Used by ALU to access RS3 if ternary instruction. + assign instr_first_cycle_id_o = instr_first_cycle; + + if (WritebackStage) begin : gen_stall_mem + // Register read address matches write address in WB + logic rf_rd_a_wb_match; + logic rf_rd_b_wb_match; + // Hazard between registers being read and written + logic rf_rd_a_hz; + logic rf_rd_b_hz; + + logic outstanding_memory_access; + + logic instr_kill; + + assign multicycle_done = lsu_req_dec ? ~stall_mem : ex_valid_i; + + // Is a memory access ongoing that isn't finishing this cycle + assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & + ~lsu_resp_valid_i; + + // Can start a new memory access if any previous one has finished or is finishing + assign data_req_allowed = ~outstanding_memory_access; + + // Instruction won't execute because: + // - There is a pending exception in writeback + // The instruction in ID/EX will be flushed and the core will jump to an exception handler + // - The controller isn't running instructions + // This either happens in preparation for a flush and jump to an exception handler e.g. in + // response to an IRQ or debug request or whilst the core is sleeping or resetting/fetching + // first instruction in which case any valid instruction in ID/EX should be ignored. + // - There was an error on instruction fetch + assign instr_kill = instr_fetch_err_i | + wb_exception | + ~controller_run; + + // With writeback stage instructions must be prevented from executing if there is: + // - A load hazard + // - A pending memory access + // If it receives an error response this results in a precise exception from WB so ID/EX + // instruction must not execute until error response is known). + // - A load/store error + // This will cause a precise exception for the instruction in WB so ID/EX instruction must not + // execute + assign instr_executing = instr_valid_i & + ~instr_kill & + ~stall_ld_hz & + ~outstanding_memory_access; + + `ASSERT(IbexStallIfValidInstrNotExecuting, + instr_valid_i & ~instr_kill & ~instr_executing |-> stall_id) + + // Stall for reasons related to memory: + // * There is an outstanding memory access that won't resolve this cycle (need to wait to allow + // precise exceptions) + // * There is a load/store request not being granted or which is unaligned and waiting to issue + // a second request (needs to stay in ID for the address calculation) + assign stall_mem = instr_valid_i & + (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); + + // If we stall a load in ID for any reason, it must not make an LSU request + // (otherwide we might issue two requests for the same instruction) + `ASSERT(IbexStallMemNoRequest, + instr_valid_i & lsu_req_dec & ~instr_done |-> ~lsu_req_done_i) + + assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; + assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; + + assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; + assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; + + // If instruction is reading register that load will be writing stall in + // ID until load is complete. No need to stall when reading zero register. + assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; + assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; + + // If instruction is read register that writeback is writing forward writeback data to read + // data. Note this doesn't factor in load data as it arrives too late, such hazards are + // resolved via a stall (see above). + assign rf_rdata_a_fwd = rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i; + + assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); + + assign instr_type_wb_o = ~lsu_req_dec ? WB_INSTR_OTHER : + lsu_we ? WB_INSTR_STORE : + WB_INSTR_LOAD; + + assign instr_id_done_o = en_wb_o & ready_wb_i; + + // Stall ID/EX as instruction in ID/EX cannot proceed to writeback yet + assign stall_wb = en_wb_o & ~ready_wb_i; + + assign perf_dside_wait_o = instr_valid_i & ~instr_kill & + (outstanding_memory_access | stall_ld_hz); + end else begin : gen_no_stall_mem + + assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i; + + assign data_req_allowed = instr_first_cycle; + + // Without Writeback Stage always stall the first cycle of a load/store. + // Then stall until it is complete + assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); + + // No load hazards without Writeback Stage + assign stall_ld_hz = 1'b0; + + // Without writeback stage any valid instruction that hasn't seen an error will execute + assign instr_executing = instr_valid_i & ~instr_fetch_err_i & controller_run; + + `ASSERT(IbexStallIfValidInstrNotExecuting, + instr_valid_i & ~instr_fetch_err_i & ~instr_executing & controller_run |-> stall_id) + + // No data forwarding without writeback stage so always take source register data direct from + // register file + assign rf_rdata_a_fwd = rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rdata_b_i; + + assign rf_rd_a_wb_match_o = 1'b0; + assign rf_rd_b_wb_match_o = 1'b0; + + // Unused Writeback stage only IO & wiring + // Assign inputs and internal wiring to unused signals to satisfy lint checks + // Tie-off outputs to constant values + logic unused_data_req_done_ex; + logic [4:0] unused_rf_waddr_wb; + logic unused_rf_write_wb; + logic unused_outstanding_load_wb; + logic unused_outstanding_store_wb; + logic unused_wb_exception; + logic [31:0] unused_rf_wdata_fwd_wb; + + assign unused_data_req_done_ex = lsu_req_done_i; + assign unused_rf_waddr_wb = rf_waddr_wb_i; + assign unused_rf_write_wb = rf_write_wb_i; + assign unused_outstanding_load_wb = outstanding_load_wb_i; + assign unused_outstanding_store_wb = outstanding_store_wb_i; + assign unused_wb_exception = wb_exception; + assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; + + assign instr_type_wb_o = WB_INSTR_OTHER; + assign stall_wb = 1'b0; + + assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i; + + assign instr_id_done_o = instr_done; + end + + // Signal which instructions to count as retired in minstret, all traps along with ebrk and + // ecall instructions are not counted. + assign instr_perf_count_id_o = ~ebrk_insn & ~ecall_insn_dec & ~illegal_insn_dec & + ~illegal_csr_insn_i & ~instr_fetch_err_i; + + // An instruction is ready to move to the writeback stage (or retire if there is no writeback + // stage) + assign en_wb_o = instr_done; + + assign perf_mul_wait_o = stall_multdiv & mult_en_dec; + assign perf_div_wait_o = stall_multdiv & div_en_dec; + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT_KNOWN_IF(IbexAluOpMuxSelKnown, alu_op_a_mux_sel, instr_valid_i) + `ASSERT(IbexAluAOpMuxSelValid, instr_valid_i |-> alu_op_a_mux_sel inside { + OP_A_REG_A, + OP_A_FWD, + OP_A_CURRPC, + OP_A_IMM}) + `ASSERT_KNOWN_IF(IbexBTAluAOpMuxSelKnown, bt_a_mux_sel, instr_valid_i) + `ASSERT(IbexBTAluAOpMuxSelValid, instr_valid_i |-> bt_a_mux_sel inside { + OP_A_REG_A, + OP_A_CURRPC}) + `ASSERT_KNOWN_IF(IbexBTAluBOpMuxSelKnown, bt_b_mux_sel, instr_valid_i) + `ASSERT(IbexBTAluBOpMuxSelValid, instr_valid_i |-> bt_b_mux_sel inside { + IMM_B_I, + IMM_B_B, + IMM_B_J, + IMM_B_INCR_PC}) + `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside { + RF_WD_EX, + RF_WD_CSR}) + `ASSERT_KNOWN(IbexWbStateKnown, id_fsm_q) + + // Branch decision must be valid when jumping. + `ASSERT_KNOWN_IF(IbexBranchDecisionValid, branch_decision_i, + instr_valid_i && !(illegal_csr_insn_i || instr_fetch_err_i)) + + // Instruction delivered to ID stage can not contain X. + `ASSERT_KNOWN_IF(IbexIdInstrKnown, instr_rdata_i, + instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) + + // Instruction delivered to ID stage can not contain X. + `ASSERT_KNOWN_IF(IbexIdInstrALUKnown, instr_rdata_alu_i, + instr_valid_i && !(illegal_c_insn_i || instr_fetch_err_i)) + + // Multicycle enable signals must be unique. + `ASSERT(IbexMulticycleEnableUnique, + $onehot0({lsu_req_dec, multdiv_en_dec, branch_in_dec, jump_in_dec})) + + // Duplicated instruction flops must match + // === as DV environment can produce instructions with Xs in, so must use precise match that + // includes Xs + `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i) + + `ifdef CHECK_MISALIGNED + `ASSERT(IbexMisalignedMemoryAccess, !lsu_addr_incr_req_i) + `endif + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_if_stage.sv b/flow/designs/src/ibex_sv/ibex_if_stage.sv new file mode 100644 index 0000000000..ee217a8c44 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_if_stage.sv @@ -0,0 +1,614 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Instruction Fetch Stage + * + * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of + * the read instruction. + */ + +`include "prim_assert.sv" + +module ibex_if_stage #( + parameter int unsigned DmHaltAddr = 32'h1A110800, + parameter int unsigned DmExceptionAddr = 32'h1A110808, + parameter bit DummyInstructions = 1'b0, + parameter bit ICache = 1'b0, + parameter bit ICacheECC = 1'b0, + parameter bit PCIncrCheck = 1'b0, + parameter bit BranchPredictor = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [31:0] boot_addr_i, // also used for mtvec + input logic req_i, // instruction request control + + // instruction cache interface + output logic instr_req_o, + output logic [31:0] instr_addr_o, + input logic instr_gnt_i, + input logic instr_rvalid_i, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + input logic instr_pmp_err_i, + + // output of ID stage + output logic instr_valid_id_o, // instr in IF-ID is valid + output logic instr_new_id_o, // instr in IF-ID is new + output logic [31:0] instr_rdata_id_o, // instr for ID stage + output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage + // to reduce fan-out + output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage + // (mtval), meaningful only if + // instr_is_compressed_id_o = 1'b1 + output logic instr_is_compressed_id_o, // compressed decoder thinks this + // is a compressed instr + output logic instr_bp_taken_o, // instruction was predicted to be + // a taken branch + output logic instr_fetch_err_o, // bus error on fetch + output logic instr_fetch_err_plus2_o, // bus error misaligned + output logic illegal_c_insn_id_o, // compressed decoder thinks this + // is an invalid instr + output logic dummy_instr_id_o, // Instruction is a dummy + output logic [31:0] pc_if_o, + output logic [31:0] pc_id_o, + + // control signals + input logic instr_valid_clear_i, // clear instr valid bit in IF-ID + input logic pc_set_i, // set the PC to a new value + input logic pc_set_spec_i, + input ibex_pkg::pc_sel_e pc_mux_i, // selector for PC multiplexer + input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was + // mispredicted (predicted taken) + input ibex_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address + input ibex_pkg::exc_cause_e exc_cause, // selects ISR address for + // vectorized interrupt lines + input logic dummy_instr_en_i, + input logic [2:0] dummy_instr_mask_i, + input logic dummy_instr_seed_en_i, + input logic [31:0] dummy_instr_seed_i, + input logic icache_enable_i, + input logic icache_inval_i, + + // jump and branch target + input logic [31:0] branch_target_ex_i, // branch/jump target address + + // CSRs + input logic [31:0] csr_mepc_i, // PC to restore after handling + // the interrupt/exception + input logic [31:0] csr_depc_i, // PC to restore after handling + // the debug request + input logic [31:0] csr_mtvec_i, // base PC to jump to on exception + output logic csr_mtvec_init_o, // tell CS regfile to init mtvec + + // pipeline stall + input logic id_in_ready_i, // ID stage is ready for new instr + + // misc signals + output logic pc_mismatch_alert_o, + output logic if_busy_o // IF stage is busy fetching instr +); + + import ibex_pkg::*; + + logic instr_valid_id_d, instr_valid_id_q; + logic instr_new_id_d, instr_new_id_q; + + // prefetch buffer related signals + logic prefetch_busy; + logic branch_req; + logic branch_spec; + logic predicted_branch; + logic [31:0] fetch_addr_n; + logic unused_fetch_addr_n0; + + logic fetch_valid; + logic fetch_ready; + logic [31:0] fetch_rdata; + logic [31:0] fetch_addr; + logic fetch_err; + logic fetch_err_plus2; + + logic if_instr_valid; + logic [31:0] if_instr_rdata; + logic [31:0] if_instr_addr; + logic if_instr_err; + + logic [31:0] exc_pc; + + logic [5:0] irq_id; + logic unused_irq_bit; + + logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable + + // Dummy instruction signals + logic stall_dummy_instr; + logic [31:0] instr_out; + logic instr_is_compressed_out; + logic illegal_c_instr_out; + logic instr_err_out; + + logic predict_branch_taken; + logic [31:0] predict_branch_pc; + + ibex_pkg::pc_sel_e pc_mux_internal; + + logic [7:0] unused_boot_addr; + logic [7:0] unused_csr_mtvec; + + assign unused_boot_addr = boot_addr_i[7:0]; + assign unused_csr_mtvec = csr_mtvec_i[7:0]; + + // extract interrupt ID from exception cause + assign irq_id = {exc_cause}; + assign unused_irq_bit = irq_id[5]; // MSB distinguishes interrupts from exceptions + + // exception PC selection mux + always_comb begin : exc_pc_mux + unique case (exc_pc_mux_i) + EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; + EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 }; + EXC_PC_DBD: exc_pc = DmHaltAddr; + EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; + default: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; + endcase + end + + // The Branch predictor can provide a new PC which is internal to if_stage. Only override the mux + // select to choose this if the core isn't already trying to set a PC. + assign pc_mux_internal = + (BranchPredictor && predict_branch_taken && !pc_set_i) ? PC_BP : pc_mux_i; + + // fetch address selection mux + always_comb begin : fetch_addr_mux + unique case (pc_mux_internal) + PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h80 }; + PC_JUMP: fetch_addr_n = branch_target_ex_i; + PC_EXC: fetch_addr_n = exc_pc; // set PC to exception handler + PC_ERET: fetch_addr_n = csr_mepc_i; // restore PC when returning from EXC + PC_DRET: fetch_addr_n = csr_depc_i; + // Without branch predictor will never get pc_mux_internal == PC_BP. We still handle no branch + // predictor case here to ensure redundant mux logic isn't synthesised. + PC_BP: fetch_addr_n = BranchPredictor ? predict_branch_pc : { boot_addr_i[31:8], 8'h80 }; + default: fetch_addr_n = { boot_addr_i[31:8], 8'h80 }; + endcase + end + + // tell CS register file to initialize mtvec on boot + assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i; + + if (ICache) begin : gen_icache + // Full I-Cache option + ibex_icache #( + .ICacheECC (ICacheECC) + ) icache_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .req_i ( req_i ), + + .branch_i ( branch_req ), + .branch_spec_i ( branch_spec ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .err_o ( fetch_err ), + .err_plus2_o ( fetch_err_plus2 ), + + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( instr_pmp_err_i ), + + .icache_enable_i ( icache_enable_i ), + .icache_inval_i ( icache_inval_i ), + .busy_o ( prefetch_busy ) + ); + // Branch predictor tie-offs (which are unused when the instruction cache is enabled) + logic unused_nt_branch_mispredict, unused_predicted_branch; + assign unused_nt_branch_mispredict = nt_branch_mispredict_i; + assign unused_predicted_branch = predicted_branch; + end else begin : gen_prefetch_buffer + // prefetch buffer, caches a fixed number of instructions + ibex_prefetch_buffer #( + .BranchPredictor (BranchPredictor) + ) prefetch_buffer_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .req_i ( req_i ), + + .branch_i ( branch_req ), + .branch_spec_i ( branch_spec ), + .predicted_branch_i ( predicted_branch ), + .branch_mispredict_i ( nt_branch_mispredict_i ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .err_o ( fetch_err ), + .err_plus2_o ( fetch_err_plus2 ), + + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( instr_pmp_err_i ), + + .busy_o ( prefetch_busy ) + ); + // ICache tieoffs + logic unused_icen, unused_icinv; + assign unused_icen = icache_enable_i; + assign unused_icinv = icache_inval_i; + end + + assign unused_fetch_addr_n0 = fetch_addr_n[0]; + + assign branch_req = pc_set_i | predict_branch_taken; + assign branch_spec = pc_set_spec_i | predict_branch_taken; + + assign pc_if_o = if_instr_addr; + assign if_busy_o = prefetch_busy; + + // compressed instruction decoding, or more precisely compressed instruction + // expander + // + // since it does not matter where we decompress instructions, we do it here + // to ease timing closure + logic [31:0] instr_decompressed; + logic illegal_c_insn; + logic instr_is_compressed; + + ibex_compressed_decoder compressed_decoder_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( fetch_valid & ~fetch_err ), + .instr_i ( if_instr_rdata ), + .instr_o ( instr_decompressed ), + .is_compressed_o ( instr_is_compressed ), + .illegal_instr_o ( illegal_c_insn ) + ); + + // Dummy instruction insertion + if (DummyInstructions) begin : gen_dummy_instr + logic insert_dummy_instr; + logic [31:0] dummy_instr_data; + + ibex_dummy_instr dummy_instr_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .dummy_instr_en_i ( dummy_instr_en_i ), + .dummy_instr_mask_i ( dummy_instr_mask_i ), + .dummy_instr_seed_en_i ( dummy_instr_seed_en_i ), + .dummy_instr_seed_i ( dummy_instr_seed_i ), + .fetch_valid_i ( fetch_valid ), + .id_in_ready_i ( id_in_ready_i ), + .insert_dummy_instr_o ( insert_dummy_instr ), + .dummy_instr_data_o ( dummy_instr_data ) + ); + + // Mux between actual instructions and dummy instructions + assign instr_out = insert_dummy_instr ? dummy_instr_data : instr_decompressed; + assign instr_is_compressed_out = insert_dummy_instr ? 1'b0 : instr_is_compressed; + assign illegal_c_instr_out = insert_dummy_instr ? 1'b0 : illegal_c_insn; + assign instr_err_out = insert_dummy_instr ? 1'b0 : if_instr_err; + + // Stall the IF stage if we insert a dummy instruction. The dummy will execute between whatever + // is currently in the ID stage and whatever is valid from the prefetch buffer this cycle. The + // PC of the dummy instruction will match whatever is next from the prefetch buffer. + assign stall_dummy_instr = insert_dummy_instr; + + // Register the dummy instruction indication into the ID stage + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + dummy_instr_id_o <= 1'b0; + end else if (if_id_pipe_reg_we) begin + dummy_instr_id_o <= insert_dummy_instr; + end + end + + end else begin : gen_no_dummy_instr + logic unused_dummy_en; + logic [2:0] unused_dummy_mask; + logic unused_dummy_seed_en; + logic [31:0] unused_dummy_seed; + + assign unused_dummy_en = dummy_instr_en_i; + assign unused_dummy_mask = dummy_instr_mask_i; + assign unused_dummy_seed_en = dummy_instr_seed_en_i; + assign unused_dummy_seed = dummy_instr_seed_i; + assign instr_out = instr_decompressed; + assign instr_is_compressed_out = instr_is_compressed; + assign illegal_c_instr_out = illegal_c_insn; + assign instr_err_out = if_instr_err; + assign stall_dummy_instr = 1'b0; + assign dummy_instr_id_o = 1'b0; + end + + // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops. + // Note that the current instruction is squashed by the incoming pc_set_i signal. + // Valid is held until it is explicitly cleared (due to an instruction completing or an exception) + assign instr_valid_id_d = (if_instr_valid & id_in_ready_i & ~pc_set_i) | + (instr_valid_id_q & ~instr_valid_clear_i); + assign instr_new_id_d = if_instr_valid & id_in_ready_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + instr_valid_id_q <= 1'b0; + instr_new_id_q <= 1'b0; + end else begin + instr_valid_id_q <= instr_valid_id_d; + instr_new_id_q <= instr_new_id_d; + end + end + + assign instr_valid_id_o = instr_valid_id_q; + // Signal when a new instruction enters the ID stage (only used for RVFI signalling). + assign instr_new_id_o = instr_new_id_q; + + // IF-ID pipeline registers, frozen when the ID stage is stalled + assign if_id_pipe_reg_we = instr_new_id_d; + + always_ff @(posedge clk_i) begin + if (if_id_pipe_reg_we) begin + instr_rdata_id_o <= instr_out; + // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated. + instr_rdata_alu_id_o <= instr_out; + instr_fetch_err_o <= instr_err_out; + instr_fetch_err_plus2_o <= fetch_err_plus2; + instr_rdata_c_id_o <= if_instr_rdata[15:0]; + instr_is_compressed_id_o <= instr_is_compressed_out; + illegal_c_insn_id_o <= illegal_c_instr_out; + pc_id_o <= pc_if_o; + end + end + + // Check for expected increments of the PC when security hardening enabled + if (PCIncrCheck) begin : g_secure_pc + logic [31:0] prev_instr_addr_incr; + logic prev_instr_seq_q, prev_instr_seq_d; + + // Do not check for sequential increase after a branch, jump, exception, interrupt or debug + // request, all of which will set branch_req. Also do not check after reset or for dummys. + assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) & + ~branch_req & ~stall_dummy_instr; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + prev_instr_seq_q <= 1'b0; + end else begin + prev_instr_seq_q <= prev_instr_seq_d; + end + end + + assign prev_instr_addr_incr = pc_id_o + ((instr_is_compressed_id_o && !instr_fetch_err_o) ? + 32'd2 : 32'd4); + + // Check that the address equals the previous address +2/+4 + assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); + + end else begin : g_no_secure_pc + assign pc_mismatch_alert_o = 1'b0; + end + + if (BranchPredictor) begin : g_branch_predictor + logic [31:0] instr_skid_data_q; + logic [31:0] instr_skid_addr_q; + logic instr_skid_bp_taken_q; + logic instr_skid_valid_q, instr_skid_valid_d; + logic instr_skid_en; + logic instr_bp_taken_q, instr_bp_taken_d; + + logic predict_branch_taken_raw; + + // ID stages needs to know if branch was predicted taken so it can signal mispredicts + always_ff @(posedge clk_i) begin + if (if_id_pipe_reg_we) begin + instr_bp_taken_q <= instr_bp_taken_d; + end + end + + // When branch prediction is enabled a skid buffer between the IF and ID/EX stage is introduced. + // If an instruction in IF is predicted to be a taken branch and ID/EX is not ready the + // instruction in IF is moved to the skid buffer which becomes the output of the IF stage until + // the ID/EX stage accepts the instruction. The skid buffer is required as otherwise the ID/EX + // ready signal is coupled to the instr_req_o output which produces a feedthrough path from + // data_gnt_i -> instr_req_o (which needs to be avoided as for some interconnects this will + // result in a combinational loop). + + assign instr_skid_en = predicted_branch & ~id_in_ready_i & ~instr_skid_valid_q; + + assign instr_skid_valid_d = (instr_skid_valid_q & ~id_in_ready_i & ~stall_dummy_instr) | + instr_skid_en; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + instr_skid_valid_q <= 1'b0; + end else begin + instr_skid_valid_q <= instr_skid_valid_d; + end + end + + always_ff @(posedge clk_i) begin + if (instr_skid_en) begin + instr_skid_bp_taken_q <= predict_branch_taken; + instr_skid_data_q <= fetch_rdata; + instr_skid_addr_q <= fetch_addr; + end + end + + ibex_branch_predict branch_predict_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .fetch_rdata_i ( fetch_rdata ), + .fetch_pc_i ( fetch_addr ), + .fetch_valid_i ( fetch_valid ), + + .predict_branch_taken_o ( predict_branch_taken_raw ), + .predict_branch_pc_o ( predict_branch_pc ) + ); + + // If there is an instruction in the skid buffer there must be no branch prediction. + // Instructions are only placed in the skid after they have been predicted to be a taken branch + // so with the skid valid any prediction has already occurred. + // Do not branch predict on instruction errors. + assign predict_branch_taken = predict_branch_taken_raw & ~instr_skid_valid_q & ~fetch_err; + + // pc_set_i takes precendence over branch prediction + assign predicted_branch = predict_branch_taken & ~pc_set_i; + + assign if_instr_valid = fetch_valid | instr_skid_valid_q; + assign if_instr_rdata = instr_skid_valid_q ? instr_skid_data_q : fetch_rdata; + assign if_instr_addr = instr_skid_valid_q ? instr_skid_addr_q : fetch_addr; + + // Don't branch predict on instruction error so only instructions without errors end up in the + // skid buffer. + assign if_instr_err = ~instr_skid_valid_q & fetch_err; + assign instr_bp_taken_d = instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken; + + assign fetch_ready = id_in_ready_i & ~stall_dummy_instr & ~instr_skid_valid_q; + + assign instr_bp_taken_o = instr_bp_taken_q; + + `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken) + `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn) + end else begin : g_no_branch_predictor + assign instr_bp_taken_o = 1'b0; + assign predict_branch_taken = 1'b0; + assign predicted_branch = 1'b0; + assign predict_branch_pc = 32'b0; + + assign if_instr_valid = fetch_valid; + assign if_instr_rdata = fetch_rdata; + assign if_instr_addr = fetch_addr; + assign if_instr_err = fetch_err; + assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; + end + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i) + + if (BranchPredictor) begin : g_branch_predictor_asserts + `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET, + PC_BP}, + pc_set_i) + +`ifdef INC_ASSERT + /** + * Checks for branch prediction interface to fetch_fifo/icache + * + * The interface has two signals: + * - predicted_branch_i: When set with a branch (branch_i) indicates the branch is a predicted + * one, it should be ignored when a branch_i isn't set. + * - branch_mispredict_i: Indicates the previously predicted branch was mis-predicted and + * execution should resume with the not-taken side of the branch (i.e. continue with the PC + * that followed the predicted branch). This must be raised before the instruction that is + * made available following a predicted branch is accepted (Following a cycle with branch_i + * & predicted_branch_i, branch_mispredict_i can only be asserted before or on the same cycle + * as seeing fetch_valid & fetch_ready). When branch_mispredict_i is asserted, fetch_valid may + * be asserted in response. If fetch_valid is asserted on the same cycle as + * branch_mispredict_i this indicates the fetch_fifo/icache has the not-taken side of the + * branch immediately ready for use + */ + logic predicted_branch_live_q, predicted_branch_live_d; + logic [31:0] predicted_branch_nt_pc_q, predicted_branch_nt_pc_d; + logic [31:0] awaiting_instr_after_mispredict_q, awaiting_instr_after_mispredict_d; + logic [31:0] next_pc; + + logic mispredicted, mispredicted_d, mispredicted_q; + + assign next_pc = fetch_addr + (instr_is_compressed_out ? 32'd2 : 32'd4); + + always_comb begin + predicted_branch_live_d = predicted_branch_live_q; + mispredicted_d = mispredicted_q; + + if (branch_req & predicted_branch) begin + predicted_branch_live_d = 1'b1; + mispredicted_d = 1'b0; + end else if (predicted_branch_live_q) begin + if (fetch_valid & fetch_ready) begin + predicted_branch_live_d = 1'b0; + end else if (nt_branch_mispredict_i) begin + mispredicted_d = 1'b1; + end + end + end + + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + predicted_branch_live_q <= 1'b0; + mispredicted_q <= 1'b0; + end else begin + predicted_branch_live_q <= predicted_branch_live_d; + mispredicted_q <= mispredicted_d; + end + end + + always @(posedge clk_i) begin + if (branch_req & predicted_branch) begin + predicted_branch_nt_pc_q <= next_pc; + end + end + + // Must only see mispredict after we've performed a predicted branch but before we've accepted + // any instruction (with fetch_ready & fetch_valid) that follows that predicted branch. + `ASSERT(MispredictOnlyImmediatelyAfterPredictedBranch, + nt_branch_mispredict_i |-> predicted_branch_live_q) + // Check that on mispredict we get the correct PC for the non-taken side of the branch when + // prefetch buffer/icache makes that PC available. + `ASSERT(CorrectPCOnMispredict, + predicted_branch_live_q & mispredicted_d & fetch_valid |-> + fetch_addr == predicted_branch_nt_pc_q) + // Must not signal mispredict over multiple cycles but it's possible to have back to back + // mispredicts for different branches (core signals mispredict, prefetch buffer/icache immediate + // has not-taken side of the mispredicted branch ready, which itself is a predicted branch, + // following cycle core signal that that branch has mispredicted). + `ASSERT(MispredictSingleCycle, + nt_branch_mispredict_i & ~(fetch_valid & fetch_ready) |=> ~nt_branch_mispredict_i) +`endif + + end else begin : g_no_branch_predictor_asserts + `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET}, + pc_set_i) + end + + // Boot address must be aligned to 256 bytes. + `ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00) + + // Address must not contain X when request is sent. + `ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o)) + + // Address must be word aligned when request is sent. + `ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_load_store_unit.sv b/flow/designs/src/ibex_sv/ibex_load_store_unit.sv new file mode 100644 index 0000000000..4d89b25703 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_load_store_unit.sv @@ -0,0 +1,516 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +/** + * Load Store Unit + * + * Load Store Unit, used to eliminate multiple access during processor stalls, + * and to align bytes and halfwords. + */ + +`include "prim_assert.sv" + +module ibex_load_store_unit +( + input logic clk_i, + input logic rst_ni, + + // data interface + output logic data_req_o, + input logic data_gnt_i, + input logic data_rvalid_i, + input logic data_err_i, + input logic data_pmp_err_i, + + output logic [31:0] data_addr_o, + output logic data_we_o, + output logic [3:0] data_be_o, + output logic [31:0] data_wdata_o, + input logic [31:0] data_rdata_i, + + // signals to/from ID/EX stage + input logic lsu_we_i, // write enable -> from ID/EX + input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX + input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX + input logic lsu_sign_ext_i, // sign extension -> from ID/EX + + output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX + output logic lsu_rdata_valid_o, + input logic lsu_req_i, // data request -> from ID/EX + + input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX + + output logic addr_incr_req_o, // request address increment for + // misaligned accesses -> to ID/EX + output logic [31:0] addr_last_o, // address of last transaction -> to controller + // -> mtval + // -> AGU for misaligned accesses + + output logic lsu_req_done_o, // Signals that data request is complete + // (only need to await final data + // response) -> to ID/EX + + output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX + + // exception signals + output logic load_err_o, + output logic store_err_o, + + output logic busy_o, + + output logic perf_load_o, + output logic perf_store_o +); + + logic [31:0] data_addr; + logic [31:0] data_addr_w_aligned; + logic [31:0] addr_last_q; + + logic addr_update; + logic ctrl_update; + logic rdata_update; + logic [31:8] rdata_q; + logic [1:0] rdata_offset_q; + logic [1:0] data_type_q; + logic data_sign_ext_q; + logic data_we_q; + + logic [1:0] data_offset; // mux control for data to be written to memory + + logic [3:0] data_be; + logic [31:0] data_wdata; + + logic [31:0] data_rdata_ext; + + logic [31:0] rdata_w_ext; // word realignment for misaligned loads + logic [31:0] rdata_h_ext; // sign extension for half words + logic [31:0] rdata_b_ext; // sign extension for bytes + + logic split_misaligned_access; + logic handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first + // part of a misaligned access + logic pmp_err_q, pmp_err_d; + logic lsu_err_q, lsu_err_d; + logic data_or_pmp_err; + + typedef enum logic [2:0] { + IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, + WAIT_RVALID_MIS_GNTS_DONE + } ls_fsm_e; + + ls_fsm_e ls_fsm_cs, ls_fsm_ns; + + assign data_addr = adder_result_ex_i; + assign data_offset = data_addr[1:0]; + + /////////////////// + // BE generation // + /////////////////// + + always_comb begin + unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte + 2'b00: begin // Writing a word + if (!handle_misaligned_q) begin // first part of potentially misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b1111; + 2'b01: data_be = 4'b1110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end else begin // second part of misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b0000; // this is not used, but included for completeness + 2'b01: data_be = 4'b0001; + 2'b10: data_be = 4'b0011; + 2'b11: data_be = 4'b0111; + default: data_be = 4'b1111; + endcase // case (data_offset) + end + end + + 2'b01: begin // Writing a half word + if (!handle_misaligned_q) begin // first part of potentially misaligned transaction + unique case (data_offset) + 2'b00: data_be = 4'b0011; + 2'b01: data_be = 4'b0110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end else begin // second part of misaligned transaction + data_be = 4'b0001; + end + end + + 2'b10, + 2'b11: begin // Writing a byte + unique case (data_offset) + 2'b00: data_be = 4'b0001; + 2'b01: data_be = 4'b0010; + 2'b10: data_be = 4'b0100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase // case (data_offset) + end + + default: data_be = 4'b1111; + endcase // case (lsu_type_i) + end + + ///////////////////// + // WData alignment // + ///////////////////// + + // prepare data to be written to the memory + // we handle misaligned accesses, half word and byte accesses here + always_comb begin + unique case (data_offset) + 2'b00: data_wdata = lsu_wdata_i[31:0]; + 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]}; + 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]}; + 2'b11: data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]}; + default: data_wdata = lsu_wdata_i[31:0]; + endcase // case (data_offset) + end + + ///////////////////// + // RData alignment // + ///////////////////// + + // register for unaligned rdata + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_q <= '0; + end else if (rdata_update) begin + rdata_q <= data_rdata_i[31:8]; + end + end + + // registers for transaction control + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rdata_offset_q <= 2'h0; + data_type_q <= 2'h0; + data_sign_ext_q <= 1'b0; + data_we_q <= 1'b0; + end else if (ctrl_update) begin + rdata_offset_q <= data_offset; + data_type_q <= lsu_type_i; + data_sign_ext_q <= lsu_sign_ext_i; + data_we_q <= lsu_we_i; + end + end + + // Store last address for mtval + AGU for misaligned transactions. + // Do not update in case of errors, mtval needs the (first) failing address + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + addr_last_q <= '0; + end else if (addr_update) begin + addr_last_q <= data_addr; + end + end + + // take care of misaligned words + always_comb begin + unique case (rdata_offset_q) + 2'b00: rdata_w_ext = data_rdata_i[31:0]; + 2'b01: rdata_w_ext = {data_rdata_i[ 7:0], rdata_q[31:8]}; + 2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]}; + 2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]}; + default: rdata_w_ext = data_rdata_i[31:0]; + endcase + end + + //////////////////// + // Sign extension // + //////////////////// + + // sign extension for half words + always_comb begin + unique case (rdata_offset_q) + 2'b00: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]}; + end + end + + 2'b01: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[23:8]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[23]}}, data_rdata_i[23:8]}; + end + end + + 2'b10: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[31:16]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]}; + end + end + + 2'b11: begin + if (!data_sign_ext_q) begin + rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]}; + end else begin + rdata_h_ext = {{16{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]}; + end + end + + default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + endcase // case (rdata_offset_q) + end + + // sign extension for bytes + always_comb begin + unique case (rdata_offset_q) + 2'b00: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]}; + end + end + + 2'b01: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]}; + end + end + + 2'b10: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]}; + end + end + + 2'b11: begin + if (!data_sign_ext_q) begin + rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]}; + end else begin + rdata_b_ext = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]}; + end + end + + default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]}; + endcase // case (rdata_offset_q) + end + + // select word, half word or byte sign extended version + always_comb begin + unique case (data_type_q) + 2'b00: data_rdata_ext = rdata_w_ext; + 2'b01: data_rdata_ext = rdata_h_ext; + 2'b10,2'b11: data_rdata_ext = rdata_b_ext; + default: data_rdata_ext = rdata_w_ext; + endcase // case (data_type_q) + end + + ///////////// + // LSU FSM // + ///////////// + + // check for misaligned accesses that need to be split into two word-aligned accesses + assign split_misaligned_access = + ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access + ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); // misaligned half-word access + + // FSM + always_comb begin + ls_fsm_ns = ls_fsm_cs; + + data_req_o = 1'b0; + addr_incr_req_o = 1'b0; + handle_misaligned_d = handle_misaligned_q; + pmp_err_d = pmp_err_q; + lsu_err_d = lsu_err_q; + + addr_update = 1'b0; + ctrl_update = 1'b0; + rdata_update = 1'b0; + + perf_load_o = 1'b0; + perf_store_o = 1'b0; + + unique case (ls_fsm_cs) + + IDLE: begin + pmp_err_d = 1'b0; + if (lsu_req_i) begin + data_req_o = 1'b1; + pmp_err_d = data_pmp_err_i; + lsu_err_d = 1'b0; + perf_load_o = ~lsu_we_i; + perf_store_o = lsu_we_i; + + if (data_gnt_i) begin + ctrl_update = 1'b1; + addr_update = 1'b1; + handle_misaligned_d = split_misaligned_access; + ls_fsm_ns = split_misaligned_access ? WAIT_RVALID_MIS : IDLE; + end else begin + ls_fsm_ns = split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT; + end + end + end + + WAIT_GNT_MIS: begin + data_req_o = 1'b1; + // data_pmp_err_i is valid during the address phase of a request. An error will block the + // external request and so a data_gnt_i might never be signalled. The registered version + // pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and + // WAIT_RVALID* states + if (data_gnt_i || pmp_err_q) begin + addr_update = 1'b1; + ctrl_update = 1'b1; + handle_misaligned_d = 1'b1; + ls_fsm_ns = WAIT_RVALID_MIS; + end + end + + WAIT_RVALID_MIS: begin + // push out second request + data_req_o = 1'b1; + // tell ID/EX stage to update the address + addr_incr_req_o = 1'b1; + + // first part rvalid is received, or gets a PMP error + if (data_rvalid_i || pmp_err_q) begin + // Update the PMP error for the second part + pmp_err_d = data_pmp_err_i; + // Record the error status of the first part + lsu_err_d = data_err_i | pmp_err_q; + // Capture the first rdata for loads + rdata_update = ~data_we_q; + // If already granted, wait for second rvalid + ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT; + // Update the address for the second part, if no error + addr_update = data_gnt_i & ~(data_err_i | pmp_err_q); + // clear handle_misaligned if second request is granted + handle_misaligned_d = ~data_gnt_i; + end else begin + // first part rvalid is NOT received + if (data_gnt_i) begin + // second grant is received + ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE; + handle_misaligned_d = 1'b0; + end + end + end + + WAIT_GNT: begin + // tell ID/EX stage to update the address + addr_incr_req_o = handle_misaligned_q; + data_req_o = 1'b1; + if (data_gnt_i || pmp_err_q) begin + ctrl_update = 1'b1; + // Update the address, unless there was an error + addr_update = ~lsu_err_q; + ls_fsm_ns = IDLE; + handle_misaligned_d = 1'b0; + end + end + + WAIT_RVALID_MIS_GNTS_DONE: begin + // tell ID/EX stage to update the address (to make sure the + // second address can be captured correctly for mtval and PMP checking) + addr_incr_req_o = 1'b1; + // Wait for the first rvalid, second request is already granted + if (data_rvalid_i) begin + // Update the pmp error for the second part + pmp_err_d = data_pmp_err_i; + // The first part cannot see a PMP error in this state + lsu_err_d = data_err_i; + // Now we can update the address for the second part if no error + addr_update = ~data_err_i; + // Capture the first rdata for loads + rdata_update = ~data_we_q; + // Wait for second rvalid + ls_fsm_ns = IDLE; + end + end + + default: begin + ls_fsm_ns = IDLE; + end + endcase + end + + assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE); + + // registers for FSM + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ls_fsm_cs <= IDLE; + handle_misaligned_q <= '0; + pmp_err_q <= '0; + lsu_err_q <= '0; + end else begin + ls_fsm_cs <= ls_fsm_ns; + handle_misaligned_q <= handle_misaligned_d; + pmp_err_q <= pmp_err_d; + lsu_err_q <= lsu_err_d; + end + end + + ///////////// + // Outputs // + ///////////// + + assign data_or_pmp_err = lsu_err_q | data_err_i | pmp_err_q; + assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE); + assign lsu_rdata_valid_o = (ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q; + + // output to register file + assign lsu_rdata_o = data_rdata_ext; + + // output data address must be word aligned + assign data_addr_w_aligned = {data_addr[31:2], 2'b00}; + + // output to data interface + assign data_addr_o = data_addr_w_aligned; + assign data_wdata_o = data_wdata; + assign data_we_o = lsu_we_i; + assign data_be_o = data_be; + + // output to ID stage: mtval + AGU for misaligned transactions + assign addr_last_o = addr_last_q; + + // Signal a load or store error depending on the transaction type outstanding + assign load_err_o = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o; + assign store_err_o = data_or_pmp_err & data_we_q & lsu_resp_valid_o; + + assign busy_o = (ls_fsm_cs != IDLE); + + //////////////// + // Assertions // + //////////////// + + // Selectors must be known/valid. + `ASSERT(IbexDataTypeKnown, (lsu_req_i | busy_o) |-> !$isunknown(lsu_type_i)) + `ASSERT(IbexDataOffsetKnown, (lsu_req_i | busy_o) |-> !$isunknown(data_offset)) + `ASSERT_KNOWN(IbexRDataOffsetQKnown, rdata_offset_q) + `ASSERT_KNOWN(IbexDataTypeQKnown, data_type_q) + `ASSERT(IbexLsuStateValid, ls_fsm_cs inside { + IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT, + WAIT_RVALID_MIS_GNTS_DONE}) + + // Address must not contain X when request is sent. + `ASSERT(IbexDataAddrUnknown, data_req_o |-> !$isunknown(data_addr_o)) + + // Address must be word aligned when request is sent. + `ASSERT(IbexDataAddrUnaligned, data_req_o |-> (data_addr_o[1:0] == 2'b00)) + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv b/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv new file mode 100644 index 0000000000..cf69f00541 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_multdiv_fast.sv @@ -0,0 +1,531 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define OP_L 15:0 +`define OP_H 31:16 + +/** + * Fast Multiplier and Division + * + * 16x16 kernel multiplier and Long Division + */ + +`include "prim_assert.sv" + +module ibex_multdiv_fast #( + parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast + ) ( + input logic clk_i, + input logic rst_ni, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input ibex_pkg::md_op_e operator_i, + input logic [1:0] signed_mode_i, + input logic [31:0] op_a_i, + input logic [31:0] op_b_i, + input logic [33:0] alu_adder_ext_i, + input logic [31:0] alu_adder_i, + input logic equal_to_zero_i, + input logic data_ind_timing_i, + + output logic [32:0] alu_operand_a_o, + output logic [32:0] alu_operand_b_o, + + input logic [33:0] imd_val_q_i[2], + output logic [33:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + input logic multdiv_ready_id_i, + + output logic [31:0] multdiv_result_o, + output logic valid_o +); + + import ibex_pkg::*; + + // Both multiplier variants + logic signed [34:0] mac_res_signed; + logic [34:0] mac_res_ext; + logic [33:0] accum; + logic sign_a, sign_b; + logic mult_valid; + logic signed_mult; + + // Results that become intermediate value depending on whether mul or div is being calculated + logic [33:0] mac_res_d, op_remainder_d; + // Raw output of MAC calculation + logic [33:0] mac_res; + + // Divider signals + logic div_sign_a, div_sign_b; + logic is_greater_equal; + logic div_change_sign, rem_change_sign; + logic [31:0] one_shift; + logic [31:0] op_denominator_q; + logic [31:0] op_numerator_q; + logic [31:0] op_quotient_q; + logic [31:0] op_denominator_d; + logic [31:0] op_numerator_d; + logic [31:0] op_quotient_d; + logic [31:0] next_remainder; + logic [32:0] next_quotient; + logic [31:0] res_adder_h; + logic div_valid; + logic [ 4:0] div_counter_q, div_counter_d; + logic multdiv_en; + logic mult_hold; + logic div_hold; + logic div_by_zero_d, div_by_zero_q; + + logic mult_en_internal; + logic div_en_internal; + + typedef enum logic [2:0] { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + } md_fsm_e; + md_fsm_e md_state_q, md_state_d; + + logic unused_mult_sel_i; + assign unused_mult_sel_i = mult_sel_i; + + assign mult_en_internal = mult_en_i & ~mult_hold; + assign div_en_internal = div_en_i & ~div_hold; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + div_counter_q <= '0; + md_state_q <= MD_IDLE; + op_numerator_q <= '0; + op_quotient_q <= '0; + div_by_zero_q <= '0; + end else if (div_en_internal) begin + div_counter_q <= div_counter_d; + op_numerator_q <= op_numerator_d; + op_quotient_q <= op_quotient_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + end + + `ASSERT_KNOWN(DivEnKnown, div_en_internal) + `ASSERT_KNOWN(MultEnKnown, mult_en_internal) + `ASSERT_KNOWN(MultDivEnKnown, multdiv_en) + + assign multdiv_en = mult_en_internal | div_en_internal; + + // Intermediate value register shared with ALU + assign imd_val_d_o[0] = div_sel_i ? op_remainder_d : mac_res_d; + assign imd_val_we_o[0] = multdiv_en; + + assign imd_val_d_o[1] = {2'b0, op_denominator_d}; + assign imd_val_we_o[1] = div_en_internal; + assign op_denominator_q = imd_val_q_i[1][31:0]; + logic [1:0] unused_imd_val; + assign unused_imd_val = imd_val_q_i[1][33:32]; + logic unused_mac_res_ext; + assign unused_mac_res_ext = mac_res_ext[34]; + + assign signed_mult = (signed_mode_i != 2'b00); + assign multdiv_result_o = div_sel_i ? imd_val_q_i[0][31:0] : mac_res_d[31:0]; + + // The single cycle multiplier uses three 17 bit multipliers to compute MUL instructions in a + // single cycle and MULH instructions in two cycles. + if (RV32M == RV32MSingleCycle) begin : gen_mult_single_cycle + + typedef enum logic { + MULL, MULH + } mult_fsm_e; + mult_fsm_e mult_state_q, mult_state_d; + + logic signed [33:0] mult1_res, mult2_res, mult3_res; + logic [33:0] mult1_res_uns; + logic [33:32] unused_mult1_res_uns; + logic [15:0] mult1_op_a, mult1_op_b; + logic [15:0] mult2_op_a, mult2_op_b; + logic [15:0] mult3_op_a, mult3_op_b; + logic mult1_sign_a, mult1_sign_b; + logic mult2_sign_a, mult2_sign_b; + logic mult3_sign_a, mult3_sign_b; + logic [33:0] summand1, summand2, summand3; + + assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b}); + assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b}); + assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b}); + + assign mac_res_signed = $signed(summand1) + $signed(summand2) + $signed(summand3); + + assign mult1_res_uns = $unsigned(mult1_res); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + + assign sign_a = signed_mode_i[0] & op_a_i[31]; + assign sign_b = signed_mode_i[1] & op_b_i[31]; + + // The first two multipliers are only used in state 1 (MULL). We can assign them statically. + // al*bl + assign mult1_sign_a = 1'b0; + assign mult1_sign_b = 1'b0; + assign mult1_op_a = op_a_i[`OP_L]; + assign mult1_op_b = op_b_i[`OP_L]; + + // al*bh + assign mult2_sign_a = 1'b0; + assign mult2_sign_b = sign_b; + assign mult2_op_a = op_a_i[`OP_L]; + assign mult2_op_b = op_b_i[`OP_H]; + + // used in MULH + assign accum[17:0] = imd_val_q_i[0][33:16]; + assign accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}}; + + always_comb begin + // Default values == MULL + + // ah*bl + mult3_sign_a = sign_a; + mult3_sign_b = 1'b0; + mult3_op_a = op_a_i[`OP_H]; + mult3_op_b = op_b_i[`OP_L]; + + summand1 = {18'h0, mult1_res_uns[`OP_H]}; + summand2 = $unsigned(mult2_res); + summand3 = $unsigned(mult3_res); + + // mac_res = A*B[47:16], mult1_res = A*B[15:0] + mac_res_d = {2'b0, mac_res[`OP_L], mult1_res_uns[`OP_L]}; + mult_valid = mult_en_i; + mult_state_d = MULL; + + mult_hold = 1'b0; + + unique case (mult_state_q) + + MULL: begin + if (operator_i != MD_OP_MULL) begin + mac_res_d = mac_res; + mult_valid = 1'b0; + mult_state_d = MULH; + end else begin + mult_hold = ~multdiv_ready_id_i; + end + end + + MULH: begin + // ah*bh + mult3_sign_a = sign_a; + mult3_sign_b = sign_b; + mult3_op_a = op_a_i[`OP_H]; + mult3_op_b = op_b_i[`OP_H]; + mac_res_d = mac_res; + + summand1 = '0; + summand2 = accum; + summand3 = mult3_res; + + mult_state_d = MULL; + mult_valid = 1'b1; + + mult_hold = ~multdiv_ready_id_i; + end + + default: begin + mult_state_d = MULL; + end + + endcase // mult_state_q + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mult_state_q <= MULL; + end else begin + if (mult_en_internal) begin + mult_state_q <= mult_state_d; + end + end + end + + assign unused_mult1_res_uns = mult1_res_uns[33:32]; + + // States must be knwon/valid. + `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + + // The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles + // and MULH instructions in 4 cycles. + end else begin : gen_mult_fast + logic [15:0] mult_op_a; + logic [15:0] mult_op_b; + + typedef enum logic [1:0] { + ALBL, ALBH, AHBL, AHBH + } mult_fsm_e; + mult_fsm_e mult_state_q, mult_state_d; + + // The 2 MSBs of mac_res_ext (mac_res_ext[34:33]) are always equal since: + // 1. The 2 MSBs of the multiplicants are always equal, and + // 2. The 16 MSBs of the addend (accum[33:18]) are always equal. + // Thus, it is safe to ignore mac_res_ext[34]. + assign mac_res_signed = + $signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b}) + $signed(accum); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + + always_comb begin + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_L]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = imd_val_q_i[0]; + mac_res_d = mac_res; + mult_state_d = mult_state_q; + mult_valid = 1'b0; + mult_hold = 1'b0; + + unique case (mult_state_q) + + ALBL: begin + // al*bl + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_L]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = '0; + mac_res_d = mac_res; + mult_state_d = ALBH; + end + + ALBH: begin + // al*bh<<16 + mult_op_a = op_a_i[`OP_L]; + mult_op_b = op_b_i[`OP_H]; + sign_a = 1'b0; + sign_b = signed_mode_i[1] & op_b_i[31]; + // result of AL*BL (in imd_val_q_i[0]) always unsigned with no carry + accum = {18'b0, imd_val_q_i[0][31:16]}; + if (operator_i == MD_OP_MULL) begin + mac_res_d = {2'b0, mac_res[`OP_L], imd_val_q_i[0][`OP_L]}; + end else begin + // MD_OP_MULH + mac_res_d = mac_res; + end + mult_state_d = AHBL; + end + + AHBL: begin + // ah*bl<<16 + mult_op_a = op_a_i[`OP_H]; + mult_op_b = op_b_i[`OP_L]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = 1'b0; + if (operator_i == MD_OP_MULL) begin + accum = {18'b0, imd_val_q_i[0][31:16]}; + mac_res_d = {2'b0, mac_res[15:0], imd_val_q_i[0][15:0]}; + mult_valid = 1'b1; + + // Note no state transition will occur if mult_hold is set + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end else begin + accum = imd_val_q_i[0]; + mac_res_d = mac_res; + mult_state_d = AHBH; + end + end + + AHBH: begin + // only MD_OP_MULH here + // ah*bh + mult_op_a = op_a_i[`OP_H]; + mult_op_b = op_b_i[`OP_H]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = signed_mode_i[1] & op_b_i[31]; + accum[17: 0] = imd_val_q_i[0][33:16]; + accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}}; + // result of AH*BL is not signed only if signed_mode_i == 2'b00 + mac_res_d = mac_res; + mult_valid = 1'b1; + + // Note no state transition will occur if mult_hold is set + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end + default: begin + mult_state_d = ALBL; + end + endcase // mult_state_q + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mult_state_q <= ALBL; + end else begin + if (mult_en_internal) begin + mult_state_q <= mult_state_d; + end + end + end + + // States must be knwon/valid. + `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) + + end // gen_mult_fast + + // Divider + assign res_adder_h = alu_adder_ext_i[32:1]; + logic [1:0] unused_alu_adder_ext; + assign unused_alu_adder_ext = {alu_adder_ext_i[33],alu_adder_ext_i[0]}; + + assign next_remainder = is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[0][31:0]; + assign next_quotient = is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : + {1'b0, op_quotient_q}; + + assign one_shift = {31'b0, 1'b1} << div_counter_q; + + // The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means + // Remainder - Divisor. If Remainder - Divisor >= 0, is_greater_equal is equal to 1, + // the next Remainder is Remainder - Divisor contained in res_adder_h and the + always_comb begin + if ((imd_val_q_i[0][31] ^ op_denominator_q[31]) == 1'b0) begin + is_greater_equal = (res_adder_h[31] == 1'b0); + end else begin + is_greater_equal = imd_val_q_i[0][31]; + end + end + + assign div_sign_a = op_a_i[31] & signed_mode_i[0]; + assign div_sign_b = op_b_i[31] & signed_mode_i[1]; + assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q; + assign rem_change_sign = div_sign_a; + + + always_comb begin + div_counter_d = div_counter_q - 5'h1; + op_remainder_d = imd_val_q_i[0]; + op_quotient_d = op_quotient_q; + md_state_d = md_state_q; + op_numerator_d = op_numerator_q; + op_denominator_d = op_denominator_q; + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_valid = 1'b0; + div_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + + unique case(md_state_q) + MD_IDLE: begin + if (operator_i == MD_OP_DIV) begin + // Check if the Denominator is 0 + // quotient for division by 0 is specified to be -1 + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return -1 + op_remainder_d = '1; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + // Record that this is a div by zero to stop the sign change at the end of the + // division (in data_ind_timing mode). + div_by_zero_d = equal_to_zero_i; + end else begin + // Check if the Denominator is 0 + // remainder for division by 0 is specified to be the numerator (operand a) + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return operand a + op_remainder_d = {2'b0, op_a_i}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + end + // 0 - B = 0 iff B == 0 + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_counter_d = 5'd31; + end + + MD_ABS_A: begin + // quotient + op_quotient_d = '0; + // A abs value + op_numerator_d = div_sign_a ? alu_adder_i : op_a_i; + md_state_d = MD_ABS_B; + div_counter_d = 5'd31; + // ABS(A) = 0 - A + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + + MD_ABS_B: begin + // remainder + op_remainder_d = { 33'h0, op_numerator_q[31]}; + // B abs value + op_denominator_d = div_sign_b ? alu_adder_i : op_b_i; + md_state_d = MD_COMP; + div_counter_d = 5'd31; + // ABS(B) = 0 - B + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + + MD_COMP: begin + op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]}; + op_quotient_d = next_quotient[31:0]; + md_state_d = (div_counter_q == 5'd1) ? MD_LAST : MD_COMP; + // Division + alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment + end + + MD_LAST: begin + if (operator_i == MD_OP_DIV) begin + // this time we save the quotient in op_remainder_d (i.e. imd_val_q_i[0]) since + // we do not need anymore the remainder + op_remainder_d = {1'b0, next_quotient}; + end else begin + // this time we do not save the quotient anymore since we need only the remainder + op_remainder_d = {2'b0, next_remainder[31:0]}; + end + // Division + alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; // -denominator two's compliment + + md_state_d = MD_CHANGE_SIGN; + end + + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + if (operator_i == MD_OP_DIV) begin + op_remainder_d = (div_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0]; + end else begin + op_remainder_d = (rem_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0]; + end + // ABS(Quotient) = 0 - Quotient (or Remainder) + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~imd_val_q_i[0][31:0], 1'b1}; + end + + MD_FINISH: begin + // Hold result until ID stage is ready to accept it + // Note no state transition will occur if div_hold is set + md_state_d = MD_IDLE; + div_hold = ~multdiv_ready_id_i; + div_valid = 1'b1; + end + + default: begin + md_state_d = MD_IDLE; + end + endcase // md_state_q + end + + assign valid_o = mult_valid | div_valid; + + // States must be knwon/valid. + `ASSERT(IbexMultDivStateValid, md_state_q inside { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH}) + +`ifdef FORMAL + `ifdef YOSYS + `include "formal_tb_frag.svh" + `endif +`endif + +endmodule // ibex_mult diff --git a/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv b/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv new file mode 100644 index 0000000000..a8d60b4eae --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_multdiv_slow.sv @@ -0,0 +1,374 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Slow Multiplier and Division + * + * Baugh-Wooley multiplier and Long Division + */ + +`include "prim_assert.sv" + +module ibex_multdiv_slow +( + input logic clk_i, + input logic rst_ni, + input logic mult_en_i, // dynamic enable signal, for FSM control + input logic div_en_i, // dynamic enable signal, for FSM control + input logic mult_sel_i, // static decoder output, for data muxes + input logic div_sel_i, // static decoder output, for data muxes + input ibex_pkg::md_op_e operator_i, + input logic [1:0] signed_mode_i, + input logic [31:0] op_a_i, + input logic [31:0] op_b_i, + input logic [33:0] alu_adder_ext_i, + input logic [31:0] alu_adder_i, + input logic equal_to_zero_i, + input logic data_ind_timing_i, + + output logic [32:0] alu_operand_a_o, + output logic [32:0] alu_operand_b_o, + + input logic [33:0] imd_val_q_i[2], + output logic [33:0] imd_val_d_o[2], + output logic [1:0] imd_val_we_o, + + input logic multdiv_ready_id_i, + + output logic [31:0] multdiv_result_o, + + output logic valid_o +); + + import ibex_pkg::*; + + typedef enum logic [2:0] { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + } md_fsm_e; + md_fsm_e md_state_q, md_state_d; + + logic [32:0] accum_window_q, accum_window_d; + logic unused_imd_val0; + logic [ 1:0] unused_imd_val1; + + logic [32:0] res_adder_l; + logic [32:0] res_adder_h; + + logic [ 4:0] multdiv_count_q, multdiv_count_d; + logic [32:0] op_b_shift_q, op_b_shift_d; + logic [32:0] op_a_shift_q, op_a_shift_d; + logic [32:0] op_a_ext, op_b_ext; + logic [32:0] one_shift; + logic [32:0] op_a_bw_pp, op_a_bw_last_pp; + logic [31:0] b_0; + logic sign_a, sign_b; + logic [32:0] next_quotient; + logic [31:0] next_remainder; + logic [31:0] op_numerator_q, op_numerator_d; + logic is_greater_equal; + logic div_change_sign, rem_change_sign; + logic div_by_zero_d, div_by_zero_q; + logic multdiv_hold; + logic multdiv_en; + + // (accum_window_q + op_a_shift_q) + assign res_adder_l = alu_adder_ext_i[32:0]; + // (accum_window_q + op_a_shift_q)>>1 + assign res_adder_h = alu_adder_ext_i[33:1]; + + ///////////////////// + // ALU Operand MUX // + ///////////////////// + + // Intermediate value register shared with ALU + assign imd_val_d_o[0] = {1'b0,accum_window_d}; + assign imd_val_we_o[0] = ~multdiv_hold; + assign accum_window_q = imd_val_q_i[0][32:0]; + assign unused_imd_val0 = imd_val_q_i[0][33]; + + assign imd_val_d_o[1] = {2'b00, op_numerator_d}; + assign imd_val_we_o[1] = multdiv_en; + assign op_numerator_q = imd_val_q_i[1][31:0]; + assign unused_imd_val1 = imd_val_q_i[1][33:32]; + + always_comb begin + alu_operand_a_o = accum_window_q; + + unique case(operator_i) + + MD_OP_MULL: begin + alu_operand_b_o = op_a_bw_pp; + end + + MD_OP_MULH: begin + alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp; + end + + MD_OP_DIV, + MD_OP_REM: begin + unique case(md_state_q) + MD_IDLE: begin + // 0 - B = 0 iff B == 0 + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_ABS_A: begin + // ABS(A) = 0 - A + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + MD_ABS_B: begin + // ABS(B) = 0 - B + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_CHANGE_SIGN: begin + // ABS(Quotient) = 0 - Quotient (or Reminder) + alu_operand_a_o = {32'h0 , 1'b1}; + alu_operand_b_o = {~accum_window_q[31:0], 1'b1}; + end + default: begin + // Division + alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the remainder + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; // -denominator two's compliment + end + endcase + end + default: begin + alu_operand_a_o = accum_window_q; + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; + end + endcase + end + + // Multiplier partial product calculation + assign b_0 = {32{op_b_shift_q[0]}}; + assign op_a_bw_pp = { ~(op_a_shift_q[32] & op_b_shift_q[0]), (op_a_shift_q[31:0] & b_0) }; + assign op_a_bw_last_pp = { (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) }; + + // Sign extend the input operands + assign sign_a = op_a_i[31] & signed_mode_i[0]; + assign sign_b = op_b_i[31] & signed_mode_i[1]; + + assign op_a_ext = {sign_a, op_a_i}; + assign op_b_ext = {sign_b, op_b_i}; + + // Divider calculations + + // The adder in the ALU computes Remainder - Divisor. If Remainder - Divisor >= 0, + // is_greater_equal is true, the next Remainder is the subtraction result and the Quotient + // multdiv_count_q-th bit is set to 1. + assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31]) ? + ~res_adder_h[31] : accum_window_q[31]; + + assign one_shift = {32'b0, 1'b1} << multdiv_count_q; + + assign next_remainder = is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]; + assign next_quotient = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q; + + assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q; + assign rem_change_sign = sign_a; + + always_comb begin + multdiv_count_d = multdiv_count_q; + accum_window_d = accum_window_q; + op_b_shift_d = op_b_shift_q; + op_a_shift_d = op_a_shift_q; + op_numerator_d = op_numerator_q; + md_state_d = md_state_q; + multdiv_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + if (mult_sel_i || div_sel_i) begin + unique case(md_state_q) + MD_IDLE: begin + unique case(operator_i) + MD_OP_MULL: begin + op_a_shift_d = op_a_ext << 1; + accum_window_d = { ~(op_a_ext[32] & op_b_i[0]), + op_a_ext[31:0] & {32{op_b_i[0]}} }; + op_b_shift_d = op_b_ext >> 1; + // Proceed with multiplication by 0/1 in data-independent time mode + md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0)) ? MD_LAST : MD_COMP; + end + MD_OP_MULH: begin + op_a_shift_d = op_a_ext; + accum_window_d = { 1'b1, ~(op_a_ext[32] & op_b_i[0]), + op_a_ext[31:1] & {31{op_b_i[0]}} }; + op_b_shift_d = op_b_ext >> 1; + md_state_d = MD_COMP; + end + MD_OP_DIV: begin + // Check if the denominator is 0 + // quotient for division by 0 is specified to be -1 + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return -1 + accum_window_d = {33{1'b1}}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + // Record that this is a div by zero to stop the sign change at the end of the + // division (in data_ind_timing mode). + div_by_zero_d = equal_to_zero_i; + end + MD_OP_REM: begin + // Check if the denominator is 0 + // remainder for division by 0 is specified to be the numerator (operand a) + // Note with data-independent time option, the full divide operation will proceed as + // normal and will naturally return operand a + accum_window_d = op_a_ext; + md_state_d = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A; + end + default:; + endcase + multdiv_count_d = 5'd31; + end + + MD_ABS_A: begin + // quotient + op_a_shift_d = '0; + // A abs value + op_numerator_d = sign_a ? alu_adder_i : op_a_i; + md_state_d = MD_ABS_B; + end + + MD_ABS_B: begin + // remainder + accum_window_d = {32'h0,op_numerator_q[31]}; + // B abs value + op_b_shift_d = sign_b ? {1'b0,alu_adder_i} : {1'b0,op_b_i}; + md_state_d = MD_COMP; + end + + MD_COMP: begin + multdiv_count_d = multdiv_count_q - 5'h1; + unique case(operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + op_a_shift_d = op_a_shift_q << 1; + op_b_shift_d = op_b_shift_q >> 1; + // Multiplication is complete once op_b is zero, unless in data_ind_timing mode where + // the maximum possible shift-add operations will be completed regardless of op_b + md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || + (multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP; + end + MD_OP_MULH: begin + accum_window_d = res_adder_h; + op_a_shift_d = op_a_shift_q; + op_b_shift_d = op_b_shift_q >> 1; + md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP; + end + MD_OP_DIV, + MD_OP_REM: begin + accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]}; + op_a_shift_d = next_quotient; + md_state_d = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP; + end + default: ; + endcase + end + + MD_LAST: begin + unique case(operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_MULH: begin + accum_window_d = res_adder_l; + md_state_d = MD_IDLE; + + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_DIV: begin + // this time we save the quotient in accum_window_q since we do not need anymore the + // remainder + accum_window_d = next_quotient; + md_state_d = MD_CHANGE_SIGN; + end + MD_OP_REM: begin + // this time we do not save the quotient anymore since we need only the remainder + accum_window_d = {1'b0, next_remainder[31:0]}; + md_state_d = MD_CHANGE_SIGN; + end + default: ; + endcase + end + + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + unique case(operator_i) + MD_OP_DIV: + accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q; + MD_OP_REM: + accum_window_d = rem_change_sign ? {1'b0,alu_adder_i} : accum_window_q; + default: ; + endcase + end + + MD_FINISH: begin + // Note no state transition will occur if multdiv_hold is set + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + + default: begin + md_state_d = MD_IDLE; + end + endcase // md_state_q + end // (mult_sel_i || div_sel_i) + end + + ////////////////////////////////////////// + // Mutliplier / Divider state registers // + ////////////////////////////////////////// + + assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + multdiv_count_q <= 5'h0; + op_b_shift_q <= 33'h0; + op_a_shift_q <= 33'h0; + md_state_q <= MD_IDLE; + div_by_zero_q <= 1'b0; + end else if (multdiv_en) begin + multdiv_count_q <= multdiv_count_d; + op_b_shift_q <= op_b_shift_d; + op_a_shift_q <= op_a_shift_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + end + + ///////////// + // Outputs // + ///////////// + + assign valid_o = (md_state_q == MD_FINISH) | + (md_state_q == MD_LAST & + (operator_i == MD_OP_MULL | + operator_i == MD_OP_MULH)); + + assign multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]; + + //////////////// + // Assertions // + //////////////// + + // State must be valid. + `ASSERT(IbexMultDivStateValid, md_state_q inside { + MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH + }, clk_i, !rst_ni) + +`ifdef FORMAL + `ifdef YOSYS + `include "formal_tb_frag.svh" + `endif +`endif + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_pkg.sv b/flow/designs/src/ibex_sv/ibex_pkg.sv new file mode 100644 index 0000000000..42ac4863ca --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_pkg.sv @@ -0,0 +1,508 @@ +// Copyright lowRISC contributors. +// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Package with constants used by Ibex + */ +package ibex_pkg; + +///////////////////// +// Parameter Enums // +///////////////////// + +typedef enum integer { + RegFileFF = 0, + RegFileFPGA = 1, + RegFileLatch = 2 +} regfile_e; + +typedef enum integer { + RV32MNone = 0, + RV32MSlow = 1, + RV32MFast = 2, + RV32MSingleCycle = 3 +} rv32m_e; + +typedef enum integer { + RV32BNone = 0, + RV32BBalanced = 1, + RV32BFull = 2 +} rv32b_e; + +///////////// +// Opcodes // +///////////// + +typedef enum logic [6:0] { + OPCODE_LOAD = 7'h03, + OPCODE_MISC_MEM = 7'h0f, + OPCODE_OP_IMM = 7'h13, + OPCODE_AUIPC = 7'h17, + OPCODE_STORE = 7'h23, + OPCODE_OP = 7'h33, + OPCODE_LUI = 7'h37, + OPCODE_BRANCH = 7'h63, + OPCODE_JALR = 7'h67, + OPCODE_JAL = 7'h6f, + OPCODE_SYSTEM = 7'h73 +} opcode_e; + + +//////////////////// +// ALU operations // +//////////////////// + +typedef enum logic [5:0] { + // Arithmetics + ALU_ADD, + ALU_SUB, + + // Logics + ALU_XOR, + ALU_OR, + ALU_AND, + // RV32B + ALU_XNOR, + ALU_ORN, + ALU_ANDN, + + // Shifts + ALU_SRA, + ALU_SRL, + ALU_SLL, + // RV32B + ALU_SRO, + ALU_SLO, + ALU_ROR, + ALU_ROL, + ALU_GREV, + ALU_GORC, + ALU_SHFL, + ALU_UNSHFL, + + // Comparisons + ALU_LT, + ALU_LTU, + ALU_GE, + ALU_GEU, + ALU_EQ, + ALU_NE, + // RV32B + ALU_MIN, + ALU_MINU, + ALU_MAX, + ALU_MAXU, + + // Pack + // RV32B + ALU_PACK, + ALU_PACKU, + ALU_PACKH, + + // Sign-Extend + // RV32B + ALU_SEXTB, + ALU_SEXTH, + + // Bitcounting + // RV32B + ALU_CLZ, + ALU_CTZ, + ALU_PCNT, + + // Set lower than + ALU_SLT, + ALU_SLTU, + + // Ternary Bitmanip Operations + // RV32B + ALU_CMOV, + ALU_CMIX, + ALU_FSL, + ALU_FSR, + + // Single-Bit Operations + // RV32B + ALU_SBSET, + ALU_SBCLR, + ALU_SBINV, + ALU_SBEXT, + + // Bit Extract / Deposit + // RV32B + ALU_BEXT, + ALU_BDEP, + + // Bit Field Place + // RV32B + ALU_BFP, + + // Carry-less Multiply + // RV32B + ALU_CLMUL, + ALU_CLMULR, + ALU_CLMULH, + + // Cyclic Redundancy Check + ALU_CRC32_B, + ALU_CRC32C_B, + ALU_CRC32_H, + ALU_CRC32C_H, + ALU_CRC32_W, + ALU_CRC32C_W +} alu_op_e; + +typedef enum logic [1:0] { + // Multiplier/divider + MD_OP_MULL, + MD_OP_MULH, + MD_OP_DIV, + MD_OP_REM +} md_op_e; + + +////////////////////////////////// +// Control and status registers // +////////////////////////////////// + +// CSR operations +typedef enum logic [1:0] { + CSR_OP_READ, + CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR +} csr_op_e; + +// Privileged mode +typedef enum logic[1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_H = 2'b10, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 +} priv_lvl_e; + +// Constants for the dcsr.xdebugver fields +typedef enum logic[3:0] { + XDEBUGVER_NO = 4'd0, // no external debug support + XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec + XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec +} x_debug_ver_e; + +////////////// +// WB stage // +////////////// + +// Type of instruction present in writeback stage +typedef enum logic[1:0] { + WB_INSTR_LOAD, // Instruction is awaiting load data + WB_INSTR_STORE, // Instruction is awaiting store response + WB_INSTR_OTHER // Instruction doesn't fit into above categories +} wb_instr_type_e; + +////////////// +// ID stage // +////////////// + +// Operand a selection +typedef enum logic[1:0] { + OP_A_REG_A, + OP_A_FWD, + OP_A_CURRPC, + OP_A_IMM +} op_a_sel_e; + +// Immediate a selection +typedef enum logic { + IMM_A_Z, + IMM_A_ZERO +} imm_a_sel_e; + +// Operand b selection +typedef enum logic { + OP_B_REG_B, + OP_B_IMM +} op_b_sel_e; + +// Immediate b selection +typedef enum logic [2:0] { + IMM_B_I, + IMM_B_S, + IMM_B_B, + IMM_B_U, + IMM_B_J, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR +} imm_b_sel_e; + +// Regfile write data selection +typedef enum logic { + RF_WD_EX, + RF_WD_CSR +} rf_wd_sel_e; + +////////////// +// IF stage // +////////////// + +// PC mux selection +typedef enum logic [2:0] { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET, + PC_BP +} pc_sel_e; + +// Exception PC mux selection +typedef enum logic [1:0] { + EXC_PC_EXC, + EXC_PC_IRQ, + EXC_PC_DBD, + EXC_PC_DBG_EXC // Exception while in debug mode +} exc_pc_sel_e; + +// Interrupt requests +typedef struct packed { + logic irq_software; + logic irq_timer; + logic irq_external; + logic [14:0] irq_fast; // 15 fast interrupts, + // one interrupt is reserved for NMI (not visible through mip/mie) +} irqs_t; + +// Exception cause +typedef enum logic [5:0] { + EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03}, + EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07}, + EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}, + // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}, + // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30}, + EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15 + EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00}, + EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01}, + EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02}, + EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03}, + EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05}, + EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07}, + EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08}, + EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11} +} exc_cause_e; + +// Debug cause +typedef enum logic [2:0] { + DBG_CAUSE_NONE = 3'h0, + DBG_CAUSE_EBREAK = 3'h1, + DBG_CAUSE_TRIGGER = 3'h2, + DBG_CAUSE_HALTREQ = 3'h3, + DBG_CAUSE_STEP = 3'h4 +} dbg_cause_e; + +// PMP constants +parameter int unsigned PMP_MAX_REGIONS = 16; +parameter int unsigned PMP_CFG_W = 8; + +// PMP acces type +parameter int unsigned PMP_I = 0; +parameter int unsigned PMP_D = 1; + +typedef enum logic [1:0] { + PMP_ACC_EXEC = 2'b00, + PMP_ACC_WRITE = 2'b01, + PMP_ACC_READ = 2'b10 +} pmp_req_e; + +// PMP cfg structures +typedef enum logic [1:0] { + PMP_MODE_OFF = 2'b00, + PMP_MODE_TOR = 2'b01, + PMP_MODE_NA4 = 2'b10, + PMP_MODE_NAPOT = 2'b11 +} pmp_cfg_mode_e; + +typedef struct packed { + logic lock; + pmp_cfg_mode_e mode; + logic exec; + logic write; + logic read; +} pmp_cfg_t; + +// CSRs +typedef enum logic[11:0] { + // Machine information + CSR_MHARTID = 12'hF14, + + // Machine trap setup + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + + // Machine trap handling + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + + // Physical memory protection + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPCFG1 = 12'h3A1, + CSR_PMPCFG2 = 12'h3A2, + CSR_PMPCFG3 = 12'h3A3, + CSR_PMPADDR0 = 12'h3B0, + CSR_PMPADDR1 = 12'h3B1, + CSR_PMPADDR2 = 12'h3B2, + CSR_PMPADDR3 = 12'h3B3, + CSR_PMPADDR4 = 12'h3B4, + CSR_PMPADDR5 = 12'h3B5, + CSR_PMPADDR6 = 12'h3B6, + CSR_PMPADDR7 = 12'h3B7, + CSR_PMPADDR8 = 12'h3B8, + CSR_PMPADDR9 = 12'h3B9, + CSR_PMPADDR10 = 12'h3BA, + CSR_PMPADDR11 = 12'h3BB, + CSR_PMPADDR12 = 12'h3BC, + CSR_PMPADDR13 = 12'h3BD, + CSR_PMPADDR14 = 12'h3BE, + CSR_PMPADDR15 = 12'h3BF, + + // Debug trigger + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_MCONTEXT = 12'h7A8, + CSR_SCONTEXT = 12'h7AA, + + // Debug/trace + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + + // Debug + CSR_DSCRATCH0 = 12'h7b2, // optional + CSR_DSCRATCH1 = 12'h7b3, // optional + + // Machine Counter/Timers + CSR_MCOUNTINHIBIT = 12'h320, + CSR_MHPMEVENT3 = 12'h323, + CSR_MHPMEVENT4 = 12'h324, + CSR_MHPMEVENT5 = 12'h325, + CSR_MHPMEVENT6 = 12'h326, + CSR_MHPMEVENT7 = 12'h327, + CSR_MHPMEVENT8 = 12'h328, + CSR_MHPMEVENT9 = 12'h329, + CSR_MHPMEVENT10 = 12'h32A, + CSR_MHPMEVENT11 = 12'h32B, + CSR_MHPMEVENT12 = 12'h32C, + CSR_MHPMEVENT13 = 12'h32D, + CSR_MHPMEVENT14 = 12'h32E, + CSR_MHPMEVENT15 = 12'h32F, + CSR_MHPMEVENT16 = 12'h330, + CSR_MHPMEVENT17 = 12'h331, + CSR_MHPMEVENT18 = 12'h332, + CSR_MHPMEVENT19 = 12'h333, + CSR_MHPMEVENT20 = 12'h334, + CSR_MHPMEVENT21 = 12'h335, + CSR_MHPMEVENT22 = 12'h336, + CSR_MHPMEVENT23 = 12'h337, + CSR_MHPMEVENT24 = 12'h338, + CSR_MHPMEVENT25 = 12'h339, + CSR_MHPMEVENT26 = 12'h33A, + CSR_MHPMEVENT27 = 12'h33B, + CSR_MHPMEVENT28 = 12'h33C, + CSR_MHPMEVENT29 = 12'h33D, + CSR_MHPMEVENT30 = 12'h33E, + CSR_MHPMEVENT31 = 12'h33F, + CSR_MCYCLE = 12'hB00, + CSR_MINSTRET = 12'hB02, + CSR_MHPMCOUNTER3 = 12'hB03, + CSR_MHPMCOUNTER4 = 12'hB04, + CSR_MHPMCOUNTER5 = 12'hB05, + CSR_MHPMCOUNTER6 = 12'hB06, + CSR_MHPMCOUNTER7 = 12'hB07, + CSR_MHPMCOUNTER8 = 12'hB08, + CSR_MHPMCOUNTER9 = 12'hB09, + CSR_MHPMCOUNTER10 = 12'hB0A, + CSR_MHPMCOUNTER11 = 12'hB0B, + CSR_MHPMCOUNTER12 = 12'hB0C, + CSR_MHPMCOUNTER13 = 12'hB0D, + CSR_MHPMCOUNTER14 = 12'hB0E, + CSR_MHPMCOUNTER15 = 12'hB0F, + CSR_MHPMCOUNTER16 = 12'hB10, + CSR_MHPMCOUNTER17 = 12'hB11, + CSR_MHPMCOUNTER18 = 12'hB12, + CSR_MHPMCOUNTER19 = 12'hB13, + CSR_MHPMCOUNTER20 = 12'hB14, + CSR_MHPMCOUNTER21 = 12'hB15, + CSR_MHPMCOUNTER22 = 12'hB16, + CSR_MHPMCOUNTER23 = 12'hB17, + CSR_MHPMCOUNTER24 = 12'hB18, + CSR_MHPMCOUNTER25 = 12'hB19, + CSR_MHPMCOUNTER26 = 12'hB1A, + CSR_MHPMCOUNTER27 = 12'hB1B, + CSR_MHPMCOUNTER28 = 12'hB1C, + CSR_MHPMCOUNTER29 = 12'hB1D, + CSR_MHPMCOUNTER30 = 12'hB1E, + CSR_MHPMCOUNTER31 = 12'hB1F, + CSR_MCYCLEH = 12'hB80, + CSR_MINSTRETH = 12'hB82, + CSR_MHPMCOUNTER3H = 12'hB83, + CSR_MHPMCOUNTER4H = 12'hB84, + CSR_MHPMCOUNTER5H = 12'hB85, + CSR_MHPMCOUNTER6H = 12'hB86, + CSR_MHPMCOUNTER7H = 12'hB87, + CSR_MHPMCOUNTER8H = 12'hB88, + CSR_MHPMCOUNTER9H = 12'hB89, + CSR_MHPMCOUNTER10H = 12'hB8A, + CSR_MHPMCOUNTER11H = 12'hB8B, + CSR_MHPMCOUNTER12H = 12'hB8C, + CSR_MHPMCOUNTER13H = 12'hB8D, + CSR_MHPMCOUNTER14H = 12'hB8E, + CSR_MHPMCOUNTER15H = 12'hB8F, + CSR_MHPMCOUNTER16H = 12'hB90, + CSR_MHPMCOUNTER17H = 12'hB91, + CSR_MHPMCOUNTER18H = 12'hB92, + CSR_MHPMCOUNTER19H = 12'hB93, + CSR_MHPMCOUNTER20H = 12'hB94, + CSR_MHPMCOUNTER21H = 12'hB95, + CSR_MHPMCOUNTER22H = 12'hB96, + CSR_MHPMCOUNTER23H = 12'hB97, + CSR_MHPMCOUNTER24H = 12'hB98, + CSR_MHPMCOUNTER25H = 12'hB99, + CSR_MHPMCOUNTER26H = 12'hB9A, + CSR_MHPMCOUNTER27H = 12'hB9B, + CSR_MHPMCOUNTER28H = 12'hB9C, + CSR_MHPMCOUNTER29H = 12'hB9D, + CSR_MHPMCOUNTER30H = 12'hB9E, + CSR_MHPMCOUNTER31H = 12'hB9F, + CSR_CPUCTRL = 12'h7C0, + CSR_SECURESEED = 12'h7C1 +} csr_num_e; + +// CSR pmp-related offsets +parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3 +parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf + +// CSR status bits +parameter int unsigned CSR_MSTATUS_MIE_BIT = 3; +parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7; +parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11; +parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12; +parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17; +parameter int unsigned CSR_MSTATUS_TW_BIT = 21; + +// CSR machine ISA +parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32 + +// CSR interrupt pending/enable bits +parameter int unsigned CSR_MSIX_BIT = 3; +parameter int unsigned CSR_MTIX_BIT = 7; +parameter int unsigned CSR_MEIX_BIT = 11; +parameter int unsigned CSR_MFIX_BIT_LOW = 16; +parameter int unsigned CSR_MFIX_BIT_HIGH = 30; + +endpackage diff --git a/flow/designs/src/ibex_sv/ibex_pmp.sv b/flow/designs/src/ibex_sv/ibex_pmp.sv new file mode 100644 index 0000000000..cbe2193310 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_pmp.sv @@ -0,0 +1,128 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ibex_pmp #( + // Granularity of NAPOT access, + // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc. + parameter int unsigned PMPGranularity = 0, + // Number of access channels (e.g. i-side + d-side) + parameter int unsigned PMPNumChan = 2, + // Number of implemented regions + parameter int unsigned PMPNumRegions = 4 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + // Interface to CSRs + input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions], + input logic [33:0] csr_pmp_addr_i [PMPNumRegions], + + input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan], + // Access checking channels + input logic [33:0] pmp_req_addr_i [PMPNumChan], + input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan], + output logic pmp_req_err_o [PMPNumChan] + +); + + import ibex_pkg::*; + + // Access Checking Signals + logic [33:0] region_start_addr [PMPNumRegions]; + logic [33:PMPGranularity+2] region_addr_mask [PMPNumRegions]; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_gt; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_lt; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_eq; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_all; + logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check; + logic [PMPNumChan-1:0] access_fault; + + + // --------------- + // Access checking + // --------------- + + for (genvar r = 0; r < PMPNumRegions; r++) begin : g_addr_exp + // Start address for TOR matching + if (r == 0) begin : g_entry0 + assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? 34'h000000000 : + csr_pmp_addr_i[r]; + end else begin : g_oth + assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? csr_pmp_addr_i[r-1] : + csr_pmp_addr_i[r]; + end + // Address mask for NA matching + for (genvar b = PMPGranularity+2; b < 34; b++) begin : g_bitmask + if (b == 2) begin : g_bit0 + // Always mask bit 2 for NAPOT + assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT); + end else begin : g_others + // We will mask this bit if it is within the programmed granule + // i.e. addr = yyyy 0111 + // ^ + // | This bit pos is the top of the mask, all lower bits set + // thus mask = 1111 0000 + assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT) | + ~&csr_pmp_addr_i[r][b-1:PMPGranularity+1]; + end + end + end + + for (genvar c = 0; c < PMPNumChan; c++) begin : g_access_check + for (genvar r = 0; r < PMPNumRegions; r++) begin : g_regions + // Comparators are sized according to granularity + assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] & + region_addr_mask[r]) == + (region_start_addr[r][33:PMPGranularity+2] & + region_addr_mask[r]); + assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] > + region_start_addr[r][33:PMPGranularity+2]; + assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] < + csr_pmp_addr_i[r][33:PMPGranularity+2]; + + always_comb begin + region_match_all[c][r] = 1'b0; + unique case (csr_pmp_cfg_i[r].mode) + PMP_MODE_OFF : region_match_all[c][r] = 1'b0; + PMP_MODE_NA4 : region_match_all[c][r] = region_match_eq[c][r]; + PMP_MODE_NAPOT : region_match_all[c][r] = region_match_eq[c][r]; + PMP_MODE_TOR : begin + region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) & + region_match_lt[c][r]; + end + default : region_match_all[c][r] = 1'b0; + endcase + end + + // Check specific required permissions + assign region_perm_check[c][r] = + ((pmp_req_type_i[c] == PMP_ACC_EXEC) & csr_pmp_cfg_i[r].exec) | + ((pmp_req_type_i[c] == PMP_ACC_WRITE) & csr_pmp_cfg_i[r].write) | + ((pmp_req_type_i[c] == PMP_ACC_READ) & csr_pmp_cfg_i[r].read); + end + + // Access fault determination / prioritization + always_comb begin + // Default is allow for M-mode, deny for other modes + access_fault[c] = (priv_mode_i[c] != PRIV_LVL_M); + + // PMP entries are statically prioritized, from 0 to N-1 + // The lowest-numbered PMP entry which matches an address determines accessability + for (int r = PMPNumRegions-1; r >= 0; r--) begin + if (region_match_all[c][r]) begin + access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ? + // For M-mode, any region which matches with the L-bit clear, or with sufficient + // access permissions will be allowed + (csr_pmp_cfg_i[r].lock & ~region_perm_check[c][r]) : + // For other modes, the lock bit doesn't matter + ~region_perm_check[c][r]; + end + end + end + + assign pmp_req_err_o[c] = access_fault[c]; + end + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv b/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv new file mode 100644 index 0000000000..f206b2ad6a --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_prefetch_buffer.sv @@ -0,0 +1,320 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Prefetcher Buffer for 32 bit memory interface + * + * Prefetch Buffer that caches instructions. This cuts overly long critical + * paths to the instruction cache. + */ +module ibex_prefetch_buffer #( + parameter bit BranchPredictor = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic req_i, + + input logic branch_i, + input logic branch_spec_i, + input logic predicted_branch_i, + input logic branch_mispredict_i, + input logic [31:0] addr_i, + + + input logic ready_i, + output logic valid_o, + output logic [31:0] rdata_o, + output logic [31:0] addr_o, + output logic err_o, + output logic err_plus2_o, + + + // goes to instruction memory / instruction cache + output logic instr_req_o, + input logic instr_gnt_i, + output logic [31:0] instr_addr_o, + input logic [31:0] instr_rdata_i, + input logic instr_err_i, + input logic instr_pmp_err_i, + input logic instr_rvalid_i, + + // Prefetch Buffer Status + output logic busy_o +); + + localparam int unsigned NUM_REQS = 2; + + logic branch_suppress; + logic valid_new_req, valid_req; + logic valid_req_d, valid_req_q; + logic discard_req_d, discard_req_q; + logic gnt_or_pmp_err, rvalid_or_pmp_err; + logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q; + logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q; + logic [NUM_REQS-1:0] rdata_pmp_err_n, rdata_pmp_err_s, rdata_pmp_err_q; + logic [NUM_REQS-1:0] rdata_outstanding_rev; + + logic [31:0] stored_addr_d, stored_addr_q; + logic stored_addr_en; + logic [31:0] fetch_addr_d, fetch_addr_q; + logic fetch_addr_en; + logic [31:0] branch_mispredict_addr; + logic [31:0] instr_addr, instr_addr_w_aligned; + logic instr_or_pmp_err; + + logic fifo_valid; + logic [31:0] fifo_addr; + logic fifo_ready; + logic fifo_clear; + logic [NUM_REQS-1:0] fifo_busy; + + logic valid_raw; + + logic [31:0] addr_next; + + logic branch_or_mispredict; + + //////////////////////////// + // Prefetch buffer status // + //////////////////////////// + + assign busy_o = (|rdata_outstanding_q) | instr_req_o; + + assign branch_or_mispredict = branch_i | branch_mispredict_i; + + ////////////////////////////////////////////// + // Fetch fifo - consumes addresses and data // + ////////////////////////////////////////////// + + // Instruction fetch errors are valid on the data phase of a request + // PMP errors are generated in the address phase, and registered into a fake data phase + assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0]; + + // A branch will invalidate any previously fetched instructions. + // Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is + // altered the FENCE.I implementation may require changes. + assign fifo_clear = branch_or_mispredict; + + // Reversed version of rdata_outstanding_q which can be overlaid with fifo fill state + for (genvar i = 0; i < NUM_REQS; i++) begin : gen_rd_rev + assign rdata_outstanding_rev[i] = rdata_outstanding_q[NUM_REQS-1-i]; + end + + // The fifo is ready to accept a new request if it is not full - including space reserved for + // requests already outstanding. + // Overlay the fifo fill state with the outstanding requests to see if there is space. + assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev); + + ibex_fetch_fifo #( + .NUM_REQS (NUM_REQS) + ) fifo_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .clear_i ( fifo_clear ), + .busy_o ( fifo_busy ), + + .in_valid_i ( fifo_valid ), + .in_addr_i ( fifo_addr ), + .in_rdata_i ( instr_rdata_i ), + .in_err_i ( instr_or_pmp_err ), + + .out_valid_o ( valid_raw ), + .out_ready_i ( ready_i ), + .out_rdata_o ( rdata_o ), + .out_addr_o ( addr_o ), + .out_addr_next_o ( addr_next ), + .out_err_o ( err_o ), + .out_err_plus2_o ( err_plus2_o ) + ); + + ////////////// + // Requests // + ////////////// + + // Suppress a new request on a not-taken branch (as the external address will be incorrect) + assign branch_suppress = branch_spec_i & ~branch_i; + + // Make a new request any time there is space in the FIFO, and space in the request queue + assign valid_new_req = ~branch_suppress & req_i & (fifo_ready | branch_or_mispredict) & + ~rdata_outstanding_q[NUM_REQS-1]; + + assign valid_req = valid_req_q | valid_new_req; + + // If a request address triggers a PMP error, the external bus request is suppressed. We might + // therefore never receive a grant for such a request. The grant is faked in this case to make + // sure the request proceeds and the error is pushed to the FIFO. + assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; + + // As with the grant, the rvalid must be faked for a PMP error, since the request was suppressed. + assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]); + + // Hold the request stable for requests that didn't get granted + assign valid_req_d = valid_req & ~gnt_or_pmp_err; + + // Record whether an outstanding bus request is cancelled by a branch + assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q); + + //////////////// + // Fetch addr // + //////////////// + + // Two addresses are tracked in the prefetch buffer: + // 1. stored_addr_q - This is the address issued on the bus. It stays stable until + // the request is granted. + // 2. fetch_addr_q - This is our next address to fetch from. It is updated on branches to + // capture the new address, and then for each new request issued. + // A third address is tracked in the fetch FIFO itself: + // 3. instr_addr_q - This is the address at the head of the FIFO, efectively our oldest fetched + // address. This address is updated on branches, and does its own increment + // each time the FIFO is popped. + + // 1. stored_addr_q + + // Only update stored_addr_q for new ungranted requests + assign stored_addr_en = valid_new_req & ~valid_req_q & ~gnt_or_pmp_err; + + // Store whatever address was issued on the bus + assign stored_addr_d = instr_addr; + + // CPU resets with a branch, so no need to reset these addresses + always_ff @(posedge clk_i) begin + if (stored_addr_en) begin + stored_addr_q <= stored_addr_d; + end + end + + if (BranchPredictor) begin : g_branch_predictor + // Where the branch predictor is present record what address followed a predicted branch. If + // that branch is predicted taken but mispredicted (so not-taken) this is used to resume on + // the not-taken code path. + logic [31:0] branch_mispredict_addr_q; + logic branch_mispredict_addr_en; + + assign branch_mispredict_addr_en = branch_i & predicted_branch_i; + + always_ff @(posedge clk_i) begin + if (branch_mispredict_addr_en) begin + branch_mispredict_addr_q <= addr_next; + end + end + + assign branch_mispredict_addr = branch_mispredict_addr_q; + end else begin : g_no_branch_predictor + logic unused_predicted_branch; + logic [31:0] unused_addr_next; + + assign unused_predicted_branch = predicted_branch_i; + assign unused_addr_next = addr_next; + + assign branch_mispredict_addr = '0; + end + + // 2. fetch_addr_q + + // Update on a branch or as soon as a request is issued + assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q); + + assign fetch_addr_d = (branch_i ? addr_i : + branch_mispredict_i ? {branch_mispredict_addr[31:2], 2'b00} : + {fetch_addr_q[31:2], 2'b00}) + + // Current address + 4 + {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00}; + + always_ff @(posedge clk_i) begin + if (fetch_addr_en) begin + fetch_addr_q <= fetch_addr_d; + end + end + + // Address mux + assign instr_addr = valid_req_q ? stored_addr_q : + branch_spec_i ? addr_i : + branch_mispredict_i ? branch_mispredict_addr : + fetch_addr_q; + + assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00}; + + /////////////////////////////// + // Request outstanding queue // + /////////////////////////////// + + for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs + // Request 0 (always the oldest outstanding request) + if (i == 0) begin : g_req0 + // A request becomes outstanding once granted, and is cleared once the rvalid is received. + // Outstanding requests shift down the queue towards entry 0. + assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | + rdata_outstanding_q[i]; + // If a branch is received at any point while a request is outstanding, it must be tracked + // to ensure we discard the data once received + assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d) | + (branch_or_mispredict & rdata_outstanding_q[i]) | + branch_discard_q[i]; + // Record whether this request received a PMP error + assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i) | + rdata_pmp_err_q[i]; + + end else begin : g_reqtop + // Entries > 0 consider the FIFO fill state to calculate their next state (by checking + // whether the previous entry is valid) + + assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err & + rdata_outstanding_q[i-1]) | + rdata_outstanding_q[i]; + assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d & + rdata_outstanding_q[i-1]) | + (branch_or_mispredict & rdata_outstanding_q[i]) | + branch_discard_q[i]; + assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i & + rdata_outstanding_q[i-1]) | + rdata_pmp_err_q[i]; + end + end + + // Shift the entries down on each instr_rvalid_i + assign rdata_outstanding_s = rvalid_or_pmp_err ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} : + rdata_outstanding_n; + assign branch_discard_s = rvalid_or_pmp_err ? {1'b0,branch_discard_n[NUM_REQS-1:1]} : + branch_discard_n; + assign rdata_pmp_err_s = rvalid_or_pmp_err ? {1'b0,rdata_pmp_err_n[NUM_REQS-1:1]} : + rdata_pmp_err_n; + + // Push a new entry to the FIFO once complete (and not cancelled by a branch) + assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0]; + + assign fifo_addr = branch_mispredict_i ? branch_mispredict_addr : addr_i; + + /////////////// + // Registers // + /////////////// + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid_req_q <= 1'b0; + discard_req_q <= 1'b0; + rdata_outstanding_q <= 'b0; + branch_discard_q <= 'b0; + rdata_pmp_err_q <= 'b0; + end else begin + valid_req_q <= valid_req_d; + discard_req_q <= discard_req_d; + rdata_outstanding_q <= rdata_outstanding_s; + branch_discard_q <= branch_discard_s; + rdata_pmp_err_q <= rdata_pmp_err_s; + end + end + + ///////////// + // Outputs // + ///////////// + + assign instr_req_o = valid_req; + assign instr_addr_o = instr_addr_w_aligned; + + assign valid_o = valid_raw & ~branch_mispredict_i; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_register_file_ff.sv b/flow/designs/src/ibex_sv/ibex_register_file_ff.sv new file mode 100644 index 0000000000..3e887b1294 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_register_file_ff.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors. +// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * RISC-V register file + * + * Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0. + * This register file is based on flip flops. Use this register file when + * targeting FPGA synthesis or Verilator simulation. + */ +module ibex_register_file_ff #( + parameter bit RV32E = 0, + parameter int unsigned DataWidth = 32, + parameter bit DummyInstructions = 0 +) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic test_en_i, + input logic dummy_instr_id_i, + + //Read port R1 + input logic [4:0] raddr_a_i, + output logic [DataWidth-1:0] rdata_a_o, + + //Read port R2 + input logic [4:0] raddr_b_i, + output logic [DataWidth-1:0] rdata_b_o, + + + // Write port W1 + input logic [4:0] waddr_a_i, + input logic [DataWidth-1:0] wdata_a_i, + input logic we_a_i + +); + + localparam int unsigned ADDR_WIDTH = RV32E ? 4 : 5; + localparam int unsigned NUM_WORDS = 2**ADDR_WIDTH; + + logic [NUM_WORDS-1:0][DataWidth-1:0] rf_reg; + logic [NUM_WORDS-1:1][DataWidth-1:0] rf_reg_q; + logic [NUM_WORDS-1:1] we_a_dec; + + always_comb begin : we_a_decoder + for (int unsigned i = 1; i < NUM_WORDS; i++) begin + we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0; + end + end + + // No flops for R0 as it's hard-wired to 0 + for (genvar i = 1; i < NUM_WORDS; i++) begin : g_rf_flops + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rf_reg_q[i] <= '0; + end else if(we_a_dec[i]) begin + rf_reg_q[i] <= wdata_a_i; + end + end + end + + // With dummy instructions enabled, R0 behaves as a real register but will always return 0 for + // real instructions. + if (DummyInstructions) begin : g_dummy_r0 + logic we_r0_dummy; + logic [DataWidth-1:0] rf_r0_q; + + // Write enable for dummy R0 register (waddr_a_i will always be 0 for dummy instructions) + assign we_r0_dummy = we_a_i & dummy_instr_id_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rf_r0_q <= '0; + end else if (we_r0_dummy) begin + rf_r0_q <= wdata_a_i; + end + end + + // Output the dummy data for dummy instructions, otherwise R0 reads as zero + assign rf_reg[0] = dummy_instr_id_i ? rf_r0_q : '0; + + end else begin : g_normal_r0 + logic unused_dummy_instr_id; + assign unused_dummy_instr_id = dummy_instr_id_i; + + // R0 is nil + assign rf_reg[0] = '0; + end + + assign rf_reg[NUM_WORDS-1:1] = rf_reg_q[NUM_WORDS-1:1]; + + assign rdata_a_o = rf_reg[raddr_a_i]; + assign rdata_b_o = rf_reg[raddr_b_i]; + + // Signal not used in FF register file + logic unused_test_en; + assign unused_test_en = test_en_i; + +endmodule diff --git a/flow/designs/src/ibex_sv/ibex_wb_stage.sv b/flow/designs/src/ibex_sv/ibex_wb_stage.sv new file mode 100644 index 0000000000..7299ad1151 --- /dev/null +++ b/flow/designs/src/ibex_sv/ibex_wb_stage.sv @@ -0,0 +1,176 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Writeback Stage + * + * Writeback is an optional third pipeline stage. It writes data back to the register file that was + * produced in the ID/EX stage or awaits a response to a load/store (LSU writes direct to register + * file for load data). If the writeback stage is not present (WritebackStage == 0) this acts as + * a simple passthrough to write data direct to the register file. + */ + +`include "prim_assert.sv" + +module ibex_wb_stage #( + parameter bit WritebackStage = 1'b0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic en_wb_i, + input ibex_pkg::wb_instr_type_e instr_type_wb_i, + input logic [31:0] pc_id_i, + input logic instr_is_compressed_id_i, + input logic instr_perf_count_id_i, + + output logic ready_wb_o, + output logic rf_write_wb_o, + output logic outstanding_load_wb_o, + output logic outstanding_store_wb_o, + output logic [31:0] pc_wb_o, + output logic perf_instr_ret_wb_o, + output logic perf_instr_ret_compressed_wb_o, + + input logic [4:0] rf_waddr_id_i, + input logic [31:0] rf_wdata_id_i, + input logic rf_we_id_i, + + input logic [31:0] rf_wdata_lsu_i, + input logic rf_we_lsu_i, + + output logic [31:0] rf_wdata_fwd_wb_o, + + output logic [4:0] rf_waddr_wb_o, + output logic [31:0] rf_wdata_wb_o, + output logic rf_we_wb_o, + + input logic lsu_resp_valid_i, + input logic lsu_resp_err_i, + + output logic instr_done_wb_o +); + + import ibex_pkg::*; + + // 0 == RF write from ID + // 1 == RF write from LSU + logic [31:0] rf_wdata_wb_mux [2]; + logic [1:0] rf_wdata_wb_mux_we; + + if(WritebackStage) begin : g_writeback_stage + logic [31:0] rf_wdata_wb_q; + logic rf_we_wb_q; + logic [4:0] rf_waddr_wb_q; + + logic wb_done; + + logic wb_valid_q; + logic [31:0] wb_pc_q; + logic wb_compressed_q; + logic wb_count_q; + wb_instr_type_e wb_instr_type_q; + + logic wb_valid_d; + + // Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction + // is done + assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done); + + // Writeback for non load/store instructions always completes in a cycle (so instantly done) + // Writeback for load/store must wait for response to be received by the LSU + // Signal only relevant if wb_valid_q set + assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + wb_valid_q <= 1'b0; + end else begin + wb_valid_q <= wb_valid_d; + end + end + + always_ff @(posedge clk_i) begin + if(en_wb_i) begin + rf_we_wb_q <= rf_we_id_i; + rf_waddr_wb_q <= rf_waddr_id_i; + rf_wdata_wb_q <= rf_wdata_id_i; + wb_instr_type_q <= instr_type_wb_i; + wb_pc_q <= pc_id_i; + wb_compressed_q <= instr_is_compressed_id_i; + wb_count_q <= instr_perf_count_id_i; + end + end + + assign rf_waddr_wb_o = rf_waddr_wb_q; + assign rf_wdata_wb_mux[0] = rf_wdata_wb_q; + assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q; + + assign ready_wb_o = ~wb_valid_q | wb_done; + + // Instruction in writeback will be writing to register file if either rf_we is set or writeback + // is awaiting load data. This is used for determining RF read hazards in ID/EX + assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD)); + + assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD); + assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE); + + assign pc_wb_o = wb_pc_q; + + assign instr_done_wb_o = wb_valid_q & wb_done; + + // Increment instruction retire counters for valid instructions which are not lsu errors + assign perf_instr_ret_wb_o = instr_done_wb_o & wb_count_q & + ~(lsu_resp_valid_i & lsu_resp_err_i); + assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q; + + // Forward data that will be written to the RF back to ID to resolve data hazards. The flopped + // rf_wdata_wb_q is used rather than rf_wdata_wb_o as the latter includes read data from memory + // that returns too late to be used on the forwarding path. + assign rf_wdata_fwd_wb_o = rf_wdata_wb_q; + end else begin : g_bypass_wb + // without writeback stage just pass through register write signals + assign rf_waddr_wb_o = rf_waddr_id_i; + assign rf_wdata_wb_mux[0] = rf_wdata_id_i; + assign rf_wdata_wb_mux_we[0] = rf_we_id_i; + + // Increment instruction retire counters for valid instructions which are not lsu errors + assign perf_instr_ret_wb_o = instr_perf_count_id_i & en_wb_i & + ~(lsu_resp_valid_i & lsu_resp_err_i); + assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i; + + // ready needs to be constant 1 without writeback stage (otherwise ID/EX stage will stall) + assign ready_wb_o = 1'b1; + + // Unused Writeback stage only IO & wiring + // Assign inputs and internal wiring to unused signals to satisfy lint checks + // Tie-off outputs to constant values + logic unused_clk; + logic unused_rst; + wb_instr_type_e unused_instr_type_wb; + logic [31:0] unused_pc_id; + + assign unused_clk = clk_i; + assign unused_rst = rst_ni; + assign unused_instr_type_wb = instr_type_wb_i; + assign unused_pc_id = pc_id_i; + + assign outstanding_load_wb_o = 1'b0; + assign outstanding_store_wb_o = 1'b0; + assign pc_wb_o = '0; + assign rf_write_wb_o = 1'b0; + assign rf_wdata_fwd_wb_o = 32'b0; + assign instr_done_wb_o = 1'b0; + end + + assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i; + assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i; + + // RF write data can come from ID results (all RF writes that aren't because of loads will come + // from here) or the LSU (RF writes for load data) + assign rf_wdata_wb_o = rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]; + assign rf_we_wb_o = |rf_wdata_wb_mux_we; + + `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we)) +endmodule diff --git a/flow/designs/src/ibex/prim_clock_gating.v b/flow/designs/src/ibex_sv/syn/rtl/prim_clock_gating.v similarity index 100% rename from flow/designs/src/ibex/prim_clock_gating.v rename to flow/designs/src/ibex_sv/syn/rtl/prim_clock_gating.v diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv new file mode 100644 index 0000000000..ddfc76a680 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert.sv @@ -0,0 +1,129 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macros and helper code for using assertions. +// - Provides default clk and rst options to simplify code +// - Provides boiler plate template for common assertions + +`ifndef PRIM_ASSERT_SV +`define PRIM_ASSERT_SV + +`ifdef UVM + // report assertion error with UVM if compiled + package assert_rpt_pkg; + import uvm_pkg::*; + `include "uvm_macros.svh" + function void assert_rpt(string msg); + `uvm_error("ASSERT FAILED", msg) + endfunction + endpackage +`endif + +/////////////////// +// Helper macros // +/////////////////// + +// Default clk and reset signals used by assertion macros below. +`define ASSERT_DEFAULT_CLK clk_i +`define ASSERT_DEFAULT_RST !rst_ni + +// Converts an arbitrary block of code into a Verilog string +`define PRIM_STRINGIFY(__x) `"__x`" + +// The basic helper macros are actually defined in "implementation headers". The macros should do +// the same thing in each case (except for the dummy flavour), but in a way that the respective +// tools support. +// +// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to +// hide signal definitions that are only used for assertions). +// +// The list of basic macros supported is: +// +// ASSERT_I: Immediate assertion. Note that immediate assertions are sensitive to simulation +// glitches. +// +// ASSERT_INIT: Assertion in initial block. Can be used for things like parameter checking. +// +// ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of +// sim, all credits returned at end of sim, state machines in idle at end of sim. +// +// ASSERT: Assert a concurrent property directly. It can be called as a module (or +// interface) body item. +// +// Note: We use (__rst !== '0) in the disable iff statements instead of (__rst == +// '1). This properly disables the assertion in cases when reset is X at the +// beginning of a simulation. For that case, (reset == '1) does not disable the +// assertion. +// +// ASSERT_NEVER: Assert a concurrent property NEVER happens +// +// ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset. +// It can be called as a module (or interface) body item. +// +// COVER: Cover a concurrent property +// +// ASSUME: Assume a concurrent property +// +// ASSUME_I: Assume an immediate property + +`ifdef VERILATOR + `include "prim_assert_dummy_macros.svh" +`elsif SYNTHESIS + `include "prim_assert_dummy_macros.svh" +`elsif YOSYS + `include "prim_assert_yosys_macros.svh" + `define INC_ASSERT +`else + `include "prim_assert_standard_macros.svh" + `define INC_ASSERT +`endif + +////////////////////////////// +// Complex assertion macros // +////////////////////////////// + +// Assert that signal is an active-high pulse with pulse length of 1 clock cycle +`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) + +// Assert that a property is true only when an enable signal is set. It can be called as a module +// (or interface) body item. +`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) + +// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is +// set. It can be called as a module (or interface) body item. +`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ + `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ + `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) + +////////////////////////////////// +// For formal verification only // +////////////////////////////////// + +// Note that the existing set of ASSERT macros specified above shall be used for FPV, +// thereby ensuring that the assertions are evaluated during DV simulations as well. + +// ASSUME_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `ASSUME(__name, __prop, __clk, __rst) \ +`endif + +// ASSUME_I_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_I_FPV(__name, __prop) \ +`ifdef FPV_ON \ + `ASSUME_I(__name, __prop) \ +`endif + +// COVER_FPV +// Cover a concurrent property during formal verification +`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `COVER(__name, __prop, __clk, __rst) \ +`endif + +`endif // PRIM_ASSERT_SV diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh new file mode 100644 index 0000000000..4a0da70336 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/prim_assert_dummy_macros.svh @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macro bodies included by prim_assert.sv for tools that don't support assertions. See +// prim_assert.sv for documentation for each of the macros. + +`define ASSERT_I(__name, __prop) +`define ASSERT_INIT(__name, __prop) +`define ASSERT_FINAL(__name, __prop) +`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) +`define ASSUME_I(__name, __prop) diff --git a/flow/designs/src/mempool_group/README.md b/flow/designs/src/mempool_group/README.md new file mode 100644 index 0000000000..7d51cf7a5f --- /dev/null +++ b/flow/designs/src/mempool_group/README.md @@ -0,0 +1 @@ +Extracted from https://github.com/TILOS-AI-Institute/MacroPlacement diff --git a/flow/designs/src/mempool_group/rtl/address_scrambler.sv b/flow/designs/src/mempool_group/rtl/address_scrambler.sv new file mode 100644 index 0000000000..d2c790a65b --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/address_scrambler.sv @@ -0,0 +1,64 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Description: Scrambles the address in such a way, that part of the memory is accessed +// sequentially and part is interleaved. +// Current constraints: + +// Author: Samuel Riedel + +module address_scrambler #( + parameter int unsigned AddrWidth = 32, + parameter int unsigned ByteOffset = 2, + parameter int unsigned NumTiles = 2, + parameter int unsigned NumBanksPerTile = 2, + parameter bit Bypass = 0, + parameter int unsigned SeqMemSizePerTile = 4*1024 +) ( + input logic [AddrWidth-1:0] address_i, + output logic [AddrWidth-1:0] address_o +); + localparam int unsigned BankOffsetBits = $clog2(NumBanksPerTile); + localparam int unsigned TileIdBits = $clog2(NumTiles); + localparam int unsigned SeqPerTileBits = $clog2(SeqMemSizePerTile); + localparam int unsigned SeqTotalBits = SeqPerTileBits+TileIdBits; + localparam int unsigned ConstantBitsLSB = ByteOffset + BankOffsetBits; + localparam int unsigned ScrambleBits = SeqPerTileBits-ConstantBitsLSB; + + if (Bypass || NumTiles < 2) begin + assign address_o = address_i; + end else begin + logic [ScrambleBits-1:0] scramble; // Address bits that have to be shuffled around + logic [TileIdBits-1:0] tile_id; // Which tile does this address region belong to + + // Leave this part of the address unchanged + // The LSBs that correspond to the offset inside a tile. These are the byte offset (bank width) + // and the Bank offset (Number of Banks in tile) + assign address_o[ConstantBitsLSB-1:0] = address_i[ConstantBitsLSB-1:0]; + // The MSBs that are outside of the sequential memory size. Currently the sequential memory size + // always starts at 0. These are all the MSBs up to SeqMemSizePerTile*NumTiles + assign address_o[AddrWidth-1:SeqTotalBits] = address_i[AddrWidth-1:SeqTotalBits]; + + // Scramble the middle part + // Bits that would have gone to different tiles but now go to increasing lines in the same tile + assign scramble = address_i[SeqPerTileBits-1:ConstantBitsLSB]; // Bits that would + // Bits that would have gone to increasing lines in the same tile but now go to different tiles + assign tile_id = address_i[SeqTotalBits-1:SeqPerTileBits]; + + always_comb begin + // Default: Unscrambled + address_o[SeqTotalBits-1:ConstantBitsLSB] = {tile_id, scramble}; + // If not in bypass mode and address is in sequential region and more than one tile + if (address_i < (NumTiles * SeqMemSizePerTile)) begin + address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id}; + end + end + end + + // Check for unsupported configurations + if (NumBanksPerTile < 2) + $fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!"); + if (SeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0) + $fatal(1, "SeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!"); +endmodule : address_scrambler diff --git a/flow/designs/src/mempool_group/rtl/axi/assign.svh b/flow/designs/src/mempool_group/rtl/axi/assign.svh new file mode 100644 index 0000000000..14bb1944c6 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/assign.svh @@ -0,0 +1,541 @@ +// Copyright (c) 2014-2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Andreas Kurth +// - Wolfgang Roenninger + +// Macros to assign AXI Interfaces and Structs + +`ifndef AXI_ASSIGN_SVH_ +`define AXI_ASSIGN_SVH_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Internal implementation for assigning one AXI struct or interface to another struct or interface. +// The path to the signals on each side is defined by the `__sep*` arguments. The `__opt_as` +// argument allows to use this standalone (with `__opt_as = assign`) or in assignments inside +// processes (with `__opt_as` void). +`define __AXI_TO_AW(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``id = __rhs``__rhs_sep``id; \ + __opt_as __lhs``__lhs_sep``addr = __rhs``__rhs_sep``addr; \ + __opt_as __lhs``__lhs_sep``len = __rhs``__rhs_sep``len; \ + __opt_as __lhs``__lhs_sep``size = __rhs``__rhs_sep``size; \ + __opt_as __lhs``__lhs_sep``burst = __rhs``__rhs_sep``burst; \ + __opt_as __lhs``__lhs_sep``lock = __rhs``__rhs_sep``lock; \ + __opt_as __lhs``__lhs_sep``cache = __rhs``__rhs_sep``cache; \ + __opt_as __lhs``__lhs_sep``prot = __rhs``__rhs_sep``prot; \ + __opt_as __lhs``__lhs_sep``qos = __rhs``__rhs_sep``qos; \ + __opt_as __lhs``__lhs_sep``region = __rhs``__rhs_sep``region; \ + __opt_as __lhs``__lhs_sep``atop = __rhs``__rhs_sep``atop; \ + __opt_as __lhs``__lhs_sep``user = __rhs``__rhs_sep``user; +`define __AXI_TO_W(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``data = __rhs``__rhs_sep``data; \ + __opt_as __lhs``__lhs_sep``strb = __rhs``__rhs_sep``strb; \ + __opt_as __lhs``__lhs_sep``last = __rhs``__rhs_sep``last; \ + __opt_as __lhs``__lhs_sep``user = __rhs``__rhs_sep``user; +`define __AXI_TO_B(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``id = __rhs``__rhs_sep``id; \ + __opt_as __lhs``__lhs_sep``resp = __rhs``__rhs_sep``resp; \ + __opt_as __lhs``__lhs_sep``user = __rhs``__rhs_sep``user; +`define __AXI_TO_AR(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``id = __rhs``__rhs_sep``id; \ + __opt_as __lhs``__lhs_sep``addr = __rhs``__rhs_sep``addr; \ + __opt_as __lhs``__lhs_sep``len = __rhs``__rhs_sep``len; \ + __opt_as __lhs``__lhs_sep``size = __rhs``__rhs_sep``size; \ + __opt_as __lhs``__lhs_sep``burst = __rhs``__rhs_sep``burst; \ + __opt_as __lhs``__lhs_sep``lock = __rhs``__rhs_sep``lock; \ + __opt_as __lhs``__lhs_sep``cache = __rhs``__rhs_sep``cache; \ + __opt_as __lhs``__lhs_sep``prot = __rhs``__rhs_sep``prot; \ + __opt_as __lhs``__lhs_sep``qos = __rhs``__rhs_sep``qos; \ + __opt_as __lhs``__lhs_sep``region = __rhs``__rhs_sep``region; \ + __opt_as __lhs``__lhs_sep``user = __rhs``__rhs_sep``user; +`define __AXI_TO_R(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``id = __rhs``__rhs_sep``id; \ + __opt_as __lhs``__lhs_sep``data = __rhs``__rhs_sep``data; \ + __opt_as __lhs``__lhs_sep``resp = __rhs``__rhs_sep``resp; \ + __opt_as __lhs``__lhs_sep``last = __rhs``__rhs_sep``last; \ + __opt_as __lhs``__lhs_sep``user = __rhs``__rhs_sep``user; +`define __AXI_TO_REQ(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + `__AXI_TO_AW(__opt_as, __lhs.aw, __lhs_sep, __rhs.aw, __rhs_sep) \ + __opt_as __lhs.aw_valid = __rhs.aw_valid; \ + `__AXI_TO_W(__opt_as, __lhs.w, __lhs_sep, __rhs.w, __rhs_sep) \ + __opt_as __lhs.w_valid = __rhs.w_valid; \ + __opt_as __lhs.b_ready = __rhs.b_ready; \ + `__AXI_TO_AR(__opt_as, __lhs.ar, __lhs_sep, __rhs.ar, __rhs_sep) \ + __opt_as __lhs.ar_valid = __rhs.ar_valid; \ + __opt_as __lhs.r_ready = __rhs.r_ready; +`define __AXI_TO_RESP(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs.aw_ready = __rhs.aw_ready; \ + __opt_as __lhs.ar_ready = __rhs.ar_ready; \ + __opt_as __lhs.w_ready = __rhs.w_ready; \ + __opt_as __lhs.b_valid = __rhs.b_valid; \ + `__AXI_TO_B(__opt_as, __lhs.b, __lhs_sep, __rhs.b, __rhs_sep) \ + __opt_as __lhs.r_valid = __rhs.r_valid; \ + `__AXI_TO_R(__opt_as, __lhs.r, __lhs_sep, __rhs.r, __rhs_sep) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning one AXI4+ATOP interface to another, as if you would do `assign slv = mst;` +// +// The channel assignments `AXI_ASSIGN_XX(dst, src)` assign all payload and the valid signal of the +// `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the +// `src` to the `dst` interface. +// The interface assignment `AXI_ASSIGN(dst, src)` assigns all channels including handshakes as if +// `src` was the master of `dst`. +// +// Usage Example: +// `AXI_ASSIGN(slv, mst) +// `AXI_ASSIGN_AW(dst, src) +// `AXI_ASSIGN_R(dst, src) +`define AXI_ASSIGN_AW(dst, src) \ + `__AXI_TO_AW(assign, dst.aw, _, src.aw, _) \ + assign dst.aw_valid = src.aw_valid; \ + assign src.aw_ready = dst.aw_ready; +`define AXI_ASSIGN_W(dst, src) \ + `__AXI_TO_W(assign, dst.w, _, src.w, _) \ + assign dst.w_valid = src.w_valid; \ + assign src.w_ready = dst.w_ready; +`define AXI_ASSIGN_B(dst, src) \ + `__AXI_TO_B(assign, dst.b, _, src.b, _) \ + assign dst.b_valid = src.b_valid; \ + assign src.b_ready = dst.b_ready; +`define AXI_ASSIGN_AR(dst, src) \ + `__AXI_TO_AR(assign, dst.ar, _, src.ar, _) \ + assign dst.ar_valid = src.ar_valid; \ + assign src.ar_ready = dst.ar_ready; +`define AXI_ASSIGN_R(dst, src) \ + `__AXI_TO_R(assign, dst.r, _, src.r, _) \ + assign dst.r_valid = src.r_valid; \ + assign src.r_ready = dst.r_ready; +`define AXI_ASSIGN(slv, mst) \ + `AXI_ASSIGN_AW(slv, mst) \ + `AXI_ASSIGN_W(slv, mst) \ + `AXI_ASSIGN_B(mst, slv) \ + `AXI_ASSIGN_AR(slv, mst) \ + `AXI_ASSIGN_R(mst, slv) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning a AXI4+ATOP interface to a monitor modport, as if you would do `assign mon = axi_if;` +// +// The channel assignment `AXI_ASSIGN_MONITOR(mon_dv, axi_if)` assigns all signals from `axi_if` +// to the `mon_dv` interface. +// +// Usage Example: +// `AXI_ASSIGN_MONITOR(mon_dv, axi_if) +`define AXI_ASSIGN_MONITOR(mon_dv, axi_if) \ + `__AXI_TO_AW(assign, mon_dv.aw, _, axi_if.aw, _) \ + assign mon_dv.aw_valid = axi_if.aw_valid; \ + assign mon_dv.aw_ready = axi_if.aw_ready; \ + `__AXI_TO_W(assign, mon_dv.w, _, axi_if.w, _) \ + assign mon_dv.w_valid = axi_if.w_valid; \ + assign mon_dv.w_ready = axi_if.w_ready; \ + `__AXI_TO_B(assign, mon_dv.b, _, axi_if.b, _) \ + assign mon_dv.b_valid = axi_if.b_valid; \ + assign mon_dv.b_ready = axi_if.b_ready; \ + `__AXI_TO_AR(assign, mon_dv.ar, _, axi_if.ar, _) \ + assign mon_dv.ar_valid = axi_if.ar_valid; \ + assign mon_dv.ar_ready = axi_if.ar_ready; \ + `__AXI_TO_R(assign, mon_dv.r, _, axi_if.r, _) \ + assign mon_dv.r_valid = axi_if.r_valid; \ + assign mon_dv.r_ready = axi_if.r_ready; +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting an interface from channel or request/response structs inside a process. +// +// The channel macros `AXI_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the `axi_if` +// interface from the signals in `xx_struct`. They do not set the handshake signals. +// The request macro `AXI_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W, AR) +// and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the `axi_if` +// interface from the signals in `req_struct`. +// The response macro `AXI_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B and R) +// and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the `axi_if` +// interface from the signals in `resp_struct`. +// +// Usage Example: +// always_comb begin +// `AXI_SET_FROM_REQ(my_if, my_req_struct) +// end +`define AXI_SET_FROM_AW(axi_if, aw_struct) `__AXI_TO_AW(, axi_if.aw, _, aw_struct, .) +`define AXI_SET_FROM_W(axi_if, w_struct) `__AXI_TO_W(, axi_if.w, _, w_struct, .) +`define AXI_SET_FROM_B(axi_if, b_struct) `__AXI_TO_B(, axi_if.b, _, b_struct, .) +`define AXI_SET_FROM_AR(axi_if, ar_struct) `__AXI_TO_AR(, axi_if.ar, _, ar_struct, .) +`define AXI_SET_FROM_R(axi_if, r_struct) `__AXI_TO_R(, axi_if.r, _, r_struct, .) +`define AXI_SET_FROM_REQ(axi_if, req_struct) `__AXI_TO_REQ(, axi_if, _, req_struct, .) +`define AXI_SET_FROM_RESP(axi_if, resp_struct) `__AXI_TO_RESP(, axi_if, _, resp_struct, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning an interface from channel or request/response structs outside a process. +// +// The channel macros `AXI_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the +// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals. +// The request macro `AXI_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels (AW, W, +// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the +// `axi_if` interface from the signals in `req_struct`. +// The response macro `AXI_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response channels (B +// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the +// `axi_if` interface from the signals in `resp_struct`. +// +// Usage Example: +// `AXI_ASSIGN_FROM_REQ(my_if, my_req_struct) +`define AXI_ASSIGN_FROM_AW(axi_if, aw_struct) `__AXI_TO_AW(assign, axi_if.aw, _, aw_struct, .) +`define AXI_ASSIGN_FROM_W(axi_if, w_struct) `__AXI_TO_W(assign, axi_if.w, _, w_struct, .) +`define AXI_ASSIGN_FROM_B(axi_if, b_struct) `__AXI_TO_B(assign, axi_if.b, _, b_struct, .) +`define AXI_ASSIGN_FROM_AR(axi_if, ar_struct) `__AXI_TO_AR(assign, axi_if.ar, _, ar_struct, .) +`define AXI_ASSIGN_FROM_R(axi_if, r_struct) `__AXI_TO_R(assign, axi_if.r, _, r_struct, .) +`define AXI_ASSIGN_FROM_REQ(axi_if, req_struct) `__AXI_TO_REQ(assign, axi_if, _, req_struct, .) +`define AXI_ASSIGN_FROM_RESP(axi_if, resp_struct) `__AXI_TO_RESP(assign, axi_if, _, resp_struct, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting channel or request/response structs from an interface inside a process. +// +// The channel macros `AXI_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the +// payload signals of that channel in the `axi_if` interface. They do not set the handshake +// signals. +// The request macro `AXI_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct` (i.e., +// request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR valid and +// B and R ready)) to the signals in the `axi_if` interface. +// The response macro `AXI_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct` +// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and +// AW, W, and AR ready)) to the signals in the `axi_if` interface. +// +// Usage Example: +// always_comb begin +// `AXI_SET_TO_REQ(my_req_struct, my_if) +// end +`define AXI_SET_TO_AW(aw_struct, axi_if) `__AXI_TO_AW(, aw_struct, ., axi_if.aw, _) +`define AXI_SET_TO_W(w_struct, axi_if) `__AXI_TO_W(, w_struct, ., axi_if.w, _) +`define AXI_SET_TO_B(b_struct, axi_if) `__AXI_TO_B(, b_struct, ., axi_if.b, _) +`define AXI_SET_TO_AR(ar_struct, axi_if) `__AXI_TO_AR(, ar_struct, ., axi_if.ar, _) +`define AXI_SET_TO_R(r_struct, axi_if) `__AXI_TO_R(, r_struct, ., axi_if.r, _) +`define AXI_SET_TO_REQ(req_struct, axi_if) `__AXI_TO_REQ(, req_struct, ., axi_if, _) +`define AXI_SET_TO_RESP(resp_struct, axi_if) `__AXI_TO_RESP(, resp_struct, ., axi_if, _) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning channel or request/response structs from an interface outside a process. +// +// The channel macros `AXI_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct` to the +// payload signals of that channel in the `axi_if` interface. They do not assign the handshake +// signals. +// The request macro `AXI_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of `req_struct` +// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR +// valid and B and R ready)) to the signals in the `axi_if` interface. +// The response macro `AXI_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of `resp_struct` +// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and +// AW, W, and AR ready)) to the signals in the `axi_if` interface. +// +// Usage Example: +// `AXI_ASSIGN_TO_REQ(my_req_struct, my_if) +`define AXI_ASSIGN_TO_AW(aw_struct, axi_if) `__AXI_TO_AW(assign, aw_struct, ., axi_if.aw, _) +`define AXI_ASSIGN_TO_W(w_struct, axi_if) `__AXI_TO_W(assign, w_struct, ., axi_if.w, _) +`define AXI_ASSIGN_TO_B(b_struct, axi_if) `__AXI_TO_B(assign, b_struct, ., axi_if.b, _) +`define AXI_ASSIGN_TO_AR(ar_struct, axi_if) `__AXI_TO_AR(assign, ar_struct, ., axi_if.ar, _) +`define AXI_ASSIGN_TO_R(r_struct, axi_if) `__AXI_TO_R(assign, r_struct, ., axi_if.r, _) +`define AXI_ASSIGN_TO_REQ(req_struct, axi_if) `__AXI_TO_REQ(assign, req_struct, ., axi_if, _) +`define AXI_ASSIGN_TO_RESP(resp_struct, axi_if) `__AXI_TO_RESP(assign, resp_struct, ., axi_if, _) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting channel or request/response structs from another struct inside a process. +// +// The channel macros `AXI_SET_XX_STRUCT(lhs, rhs)` set the fields of the `lhs` channel struct to +// the fields of the `rhs` channel struct. They do not set the handshake signals, which are not +// part of channel structs. +// The request macro `AXI_SET_REQ_STRUCT(lhs, rhs)` sets all fields of the `lhs` request struct to +// the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) payload +// and request-side handshake signals (AW, W, and AR valid and B and R ready). +// The response macro `AXI_SET_RESP_STRUCT(lhs, rhs)` sets all fields of the `lhs` response struct +// to the fields of the `rhs` response struct. This includes all response channel (B and R) payload +// and response-side handshake signals (B and R valid and AW, W, and R ready). +// +// Usage Example: +// always_comb begin +// `AXI_SET_REQ_STRUCT(my_req_struct, another_req_struct) +// end +`define AXI_SET_AW_STRUCT(lhs, rhs) `__AXI_TO_AW(, lhs, ., rhs, .) +`define AXI_SET_W_STRUCT(lhs, rhs) `__AXI_TO_W(, lhs, ., rhs, .) +`define AXI_SET_B_STRUCT(lhs, rhs) `__AXI_TO_B(, lhs, ., rhs, .) +`define AXI_SET_AR_STRUCT(lhs, rhs) `__AXI_TO_AR(, lhs, ., rhs, .) +`define AXI_SET_R_STRUCT(lhs, rhs) `__AXI_TO_R(, lhs, ., rhs, .) +`define AXI_SET_REQ_STRUCT(lhs, rhs) `__AXI_TO_REQ(, lhs, ., rhs, .) +`define AXI_SET_RESP_STRUCT(lhs, rhs) `__AXI_TO_RESP(, lhs, ., rhs, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning channel or request/response structs from another struct outside a process. +// +// The channel macros `AXI_ASSIGN_XX_STRUCT(lhs, rhs)` assign the fields of the `lhs` channel struct +// to the fields of the `rhs` channel struct. They do not assign the handshake signals, which are +// not part of the channel structs. +// The request macro `AXI_ASSIGN_REQ_STRUCT(lhs, rhs)` assigns all fields of the `lhs` request +// struct to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) +// payload and request-side handshake signals (AW, W, and AR valid and B and R ready). +// The response macro `AXI_ASSIGN_RESP_STRUCT(lhs, rhs)` assigns all fields of the `lhs` response +// struct to the fields of the `rhs` response struct. This includes all response channel (B and R) +// payload and response-side handshake signals (B and R valid and AW, W, and R ready). +// +// Usage Example: +// `AXI_ASSIGN_REQ_STRUCT(my_req_struct, another_req_struct) +`define AXI_ASSIGN_AW_STRUCT(lhs, rhs) `__AXI_TO_AW(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_W_STRUCT(lhs, rhs) `__AXI_TO_W(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_B_STRUCT(lhs, rhs) `__AXI_TO_B(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_AR_STRUCT(lhs, rhs) `__AXI_TO_AR(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_R_STRUCT(lhs, rhs) `__AXI_TO_R(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_REQ_STRUCT(lhs, rhs) `__AXI_TO_REQ(assign, lhs, ., rhs, .) +`define AXI_ASSIGN_RESP_STRUCT(lhs, rhs) `__AXI_TO_RESP(assign, lhs, ., rhs, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Internal implementation for assigning one Lite structs or interface to another struct or +// interface. The path to the signals on each side is defined by the `__sep*` arguments. The +// `__opt_as` argument allows to use this standalne (with `__opt_as = assign`) or in assignments +// inside processes (with `__opt_as` void). +`define __AXI_LITE_TO_AX(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``addr = __rhs``__rhs_sep``addr; \ + __opt_as __lhs``__lhs_sep``prot = __rhs``__rhs_sep``prot; +`define __AXI_LITE_TO_W(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``data = __rhs``__rhs_sep``data; \ + __opt_as __lhs``__lhs_sep``strb = __rhs``__rhs_sep``strb; +`define __AXI_LITE_TO_B(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``resp = __rhs``__rhs_sep``resp; +`define __AXI_LITE_TO_R(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs``__lhs_sep``data = __rhs``__rhs_sep``data; \ + __opt_as __lhs``__lhs_sep``resp = __rhs``__rhs_sep``resp; +`define __AXI_LITE_TO_REQ(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + `__AXI_LITE_TO_AX(__opt_as, __lhs.aw, __lhs_sep, __rhs.aw, __rhs_sep) \ + __opt_as __lhs.aw_valid = __rhs.aw_valid; \ + `__AXI_LITE_TO_W(__opt_as, __lhs.w, __lhs_sep, __rhs.w, __rhs_sep) \ + __opt_as __lhs.w_valid = __rhs.w_valid; \ + __opt_as __lhs.b_ready = __rhs.b_ready; \ + `__AXI_LITE_TO_AX(__opt_as, __lhs.ar, __lhs_sep, __rhs.ar, __rhs_sep) \ + __opt_as __lhs.ar_valid = __rhs.ar_valid; \ + __opt_as __lhs.r_ready = __rhs.r_ready; +`define __AXI_LITE_TO_RESP(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \ + __opt_as __lhs.aw_ready = __rhs.aw_ready; \ + __opt_as __lhs.ar_ready = __rhs.ar_ready; \ + __opt_as __lhs.w_ready = __rhs.w_ready; \ + __opt_as __lhs.b_valid = __rhs.b_valid; \ + `__AXI_LITE_TO_B(__opt_as, __lhs.b, __lhs_sep, __rhs.b, __rhs_sep) \ + __opt_as __lhs.r_valid = __rhs.r_valid; \ + `__AXI_LITE_TO_R(__opt_as, __lhs.r, __lhs_sep, __rhs.r, __rhs_sep) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning one AXI-Lite interface to another, as if you would do `assign slv = mst;` +// +// The channel assignments `AXI_LITE_ASSIGN_XX(dst, src)` assign all payload and the valid signal of +// the `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the +// `src` to the `dst` interface. +// The interface assignment `AXI_LITE_ASSIGN(dst, src)` assigns all channels including handshakes as +// if `src` was the master of `dst`. +// +// Usage Example: +// `AXI_LITE_ASSIGN(slv, mst) +// `AXI_LITE_ASSIGN_AW(dst, src) +// `AXI_LITE_ASSIGN_R(dst, src) +`define AXI_LITE_ASSIGN_AW(dst, src) \ + `__AXI_LITE_TO_AX(assign, dst.aw, _, src.aw, _) \ + assign dst.aw_valid = src.aw_valid; \ + assign src.aw_ready = dst.aw_ready; +`define AXI_LITE_ASSIGN_W(dst, src) \ + `__AXI_LITE_TO_W(assign, dst.w, _, src.w, _) \ + assign dst.w_valid = src.w_valid; \ + assign src.w_ready = dst.w_ready; +`define AXI_LITE_ASSIGN_B(dst, src) \ + `__AXI_LITE_TO_B(assign, dst.b, _, src.b, _) \ + assign dst.b_valid = src.b_valid; \ + assign src.b_ready = dst.b_ready; +`define AXI_LITE_ASSIGN_AR(dst, src) \ + `__AXI_LITE_TO_AX(assign, dst.ar, _, src.ar, _) \ + assign dst.ar_valid = src.ar_valid; \ + assign src.ar_ready = dst.ar_ready; +`define AXI_LITE_ASSIGN_R(dst, src) \ + `__AXI_LITE_TO_R(assign, dst.r, _, src.r, _) \ + assign dst.r_valid = src.r_valid; \ + assign src.r_ready = dst.r_ready; +`define AXI_LITE_ASSIGN(slv, mst) \ + `AXI_LITE_ASSIGN_AW(slv, mst) \ + `AXI_LITE_ASSIGN_W(slv, mst) \ + `AXI_LITE_ASSIGN_B(mst, slv) \ + `AXI_LITE_ASSIGN_AR(slv, mst) \ + `AXI_LITE_ASSIGN_R(mst, slv) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting a Lite interface from channel or request/response structs inside a process. +// +// The channel macros `AXI_LITE_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the +// `axi_if` interface from the signals in `xx_struct`. They do not set the handshake signals. +// The request macro `AXI_LITE_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W, +// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the +// `axi_if` interface from the signals in `req_struct`. +// The response macro `AXI_LITE_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B +// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the +// `axi_if` interface from the signals in `resp_struct`. +// +// Usage Example: +// always_comb begin +// `AXI_LITE_SET_FROM_REQ(my_if, my_req_struct) +// end +`define AXI_LITE_SET_FROM_AW(axi_if, aw_struct) `__AXI_LITE_TO_AX(, axi_if.aw, _, aw_struct, .) +`define AXI_LITE_SET_FROM_W(axi_if, w_struct) `__AXI_LITE_TO_W(, axi_if.w, _, w_struct, .) +`define AXI_LITE_SET_FROM_B(axi_if, b_struct) `__AXI_LITE_TO_B(, axi_if.b, _, b_struct, .) +`define AXI_LITE_SET_FROM_AR(axi_if, ar_struct) `__AXI_LITE_TO_AX(, axi_if.ar, _, ar_struct, .) +`define AXI_LITE_SET_FROM_R(axi_if, r_struct) `__AXI_LITE_TO_R(, axi_if.r, _, r_struct, .) +`define AXI_LITE_SET_FROM_REQ(axi_if, req_struct) `__AXI_LITE_TO_REQ(, axi_if, _, req_struct, .) +`define AXI_LITE_SET_FROM_RESP(axi_if, resp_struct) `__AXI_LITE_TO_RESP(, axi_if, _, resp_struct, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning a Lite interface from channel or request/response structs outside a process. +// +// The channel macros `AXI_LITE_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the +// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals. +// The request macro `AXI_LITE_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels +// (AW, W, AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the +// `axi_if` interface from the signals in `req_struct`. +// The response macro `AXI_LITE_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response +// channels (B and R) and the response-side handshake signals (B and R valid and AW, W, and AR +// ready) of the `axi_if` interface from the signals in `resp_struct`. +// +// Usage Example: +// `AXI_LITE_ASSIGN_FROM_REQ(my_if, my_req_struct) +`define AXI_LITE_ASSIGN_FROM_AW(axi_if, aw_struct) `__AXI_LITE_TO_AX(assign, axi_if.aw, _, aw_struct, .) +`define AXI_LITE_ASSIGN_FROM_W(axi_if, w_struct) `__AXI_LITE_TO_W(assign, axi_if.w, _, w_struct, .) +`define AXI_LITE_ASSIGN_FROM_B(axi_if, b_struct) `__AXI_LITE_TO_B(assign, axi_if.b, _, b_struct, .) +`define AXI_LITE_ASSIGN_FROM_AR(axi_if, ar_struct) `__AXI_LITE_TO_AX(assign, axi_if.ar, _, ar_struct, .) +`define AXI_LITE_ASSIGN_FROM_R(axi_if, r_struct) `__AXI_LITE_TO_R(assign, axi_if.r, _, r_struct, .) +`define AXI_LITE_ASSIGN_FROM_REQ(axi_if, req_struct) `__AXI_LITE_TO_REQ(assign, axi_if, _, req_struct, .) +`define AXI_LITE_ASSIGN_FROM_RESP(axi_if, resp_struct) `__AXI_LITE_TO_RESP(assign, axi_if, _, resp_struct, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting channel or request/response structs from an interface inside a process. +// +// The channel macros `AXI_LITE_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the +// payload signals of that channel in the `axi_if` interface. They do not set the handshake +// signals. +// The request macro `AXI_LITE_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct` +// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR +// valid and B and R ready)) to the signals in the `axi_if` interface. +// The response macro `AXI_LITE_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct` +// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and +// AW, W, and AR ready)) to the signals in the `axi_if` interface. +// +// Usage Example: +// always_comb begin +// `AXI_LITE_SET_TO_REQ(my_req_struct, my_if) +// end +`define AXI_LITE_SET_TO_AW(aw_struct, axi_if) `__AXI_LITE_TO_AX(, aw_struct, ., axi_if.aw, _) +`define AXI_LITE_SET_TO_W(w_struct, axi_if) `__AXI_LITE_TO_W(, w_struct, ., axi_if.w, _) +`define AXI_LITE_SET_TO_B(b_struct, axi_if) `__AXI_LITE_TO_B(, b_struct, ., axi_if.b, _) +`define AXI_LITE_SET_TO_AR(ar_struct, axi_if) `__AXI_LITE_TO_AX(, ar_struct, ., axi_if.ar, _) +`define AXI_LITE_SET_TO_R(r_struct, axi_if) `__AXI_LITE_TO_R(, r_struct, ., axi_if.r, _) +`define AXI_LITE_SET_TO_REQ(req_struct, axi_if) `__AXI_LITE_TO_REQ(, req_struct, ., axi_if, _) +`define AXI_LITE_SET_TO_RESP(resp_struct, axi_if) `__AXI_LITE_TO_RESP(, resp_struct, ., axi_if, _) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning channel or request/response structs from an interface outside a process. +// +// The channel macros `AXI_LITE_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct` +// to the payload signals of that channel in the `axi_if` interface. They do not assign the +// handshake signals. +// The request macro `AXI_LITE_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of +// `req_struct` (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, +// W, and AR valid and B and R ready)) to the signals in the `axi_if` interface. +// The response macro `AXI_LITE_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of +// `resp_struct` (i.e., response channel (B and R) payload and response-side handshake signals (B +// and R valid and AW, W, and AR ready)) to the signals in the `axi_if` interface. +// +// Usage Example: +// `AXI_LITE_ASSIGN_TO_REQ(my_req_struct, my_if) +`define AXI_LITE_ASSIGN_TO_AW(aw_struct, axi_if) `__AXI_LITE_TO_AX(assign, aw_struct, ., axi_if.aw, _) +`define AXI_LITE_ASSIGN_TO_W(w_struct, axi_if) `__AXI_LITE_TO_W(assign, w_struct, ., axi_if.w, _) +`define AXI_LITE_ASSIGN_TO_B(b_struct, axi_if) `__AXI_LITE_TO_B(assign, b_struct, ., axi_if.b, _) +`define AXI_LITE_ASSIGN_TO_AR(ar_struct, axi_if) `__AXI_LITE_TO_AX(assign, ar_struct, ., axi_if.ar, _) +`define AXI_LITE_ASSIGN_TO_R(r_struct, axi_if) `__AXI_LITE_TO_R(assign, r_struct, ., axi_if.r, _) +`define AXI_LITE_ASSIGN_TO_REQ(req_struct, axi_if) `__AXI_LITE_TO_REQ(assign, req_struct, ., axi_if, _) +`define AXI_LITE_ASSIGN_TO_RESP(resp_struct, axi_if) `__AXI_LITE_TO_RESP(assign, resp_struct, ., axi_if, _) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Setting channel or request/response structs from another struct inside a process. +// +// The channel macros `AXI_LITE_SET_XX_STRUCT(lhs, rhs)` set the fields of the `lhs` channel struct +// to the fields of the `rhs` channel struct. They do not set the handshake signals, which are not +// part of channel structs. +// The request macro `AXI_LITE_SET_REQ_STRUCT(lhs, rhs)` sets all fields of the `lhs` request struct +// to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) payload +// and request-side handshake signals (AW, W, and AR valid and B and R ready). +// The response macro `AXI_LITE_SET_RESP_STRUCT(lhs, rhs)` sets all fields of the `lhs` response +// struct to the fields of the `rhs` response struct. This includes all response channel (B and R) +// payload and response-side handshake signals (B and R valid and AW, W, and R ready). +// +// Usage Example: +// always_comb begin +// `AXI_LITE_SET_REQ_STRUCT(my_req_struct, another_req_struct) +// end +`define AXI_LITE_SET_AW_STRUCT(lhs, rhs) `__AXI_LITE_TO_AX(, lhs, ., rhs, .) +`define AXI_LITE_SET_W_STRUCT(lhs, rhs) `__AXI_LITE_TO_W(, lhs, ., rhs, .) +`define AXI_LITE_SET_B_STRUCT(lhs, rhs) `__AXI_LITE_TO_B(, lhs, ., rhs, .) +`define AXI_LITE_SET_AR_STRUCT(lhs, rhs) `__AXI_LITE_TO_AX(, lhs, ., rhs, .) +`define AXI_LITE_SET_R_STRUCT(lhs, rhs) `__AXI_LITE_TO_R(, lhs, ., rhs, .) +`define AXI_LITE_SET_REQ_STRUCT(lhs, rhs) `__AXI_LITE_TO_REQ(, lhs, ., rhs, .) +`define AXI_LITE_SET_RESP_STRUCT(lhs, rhs) `__AXI_LITE_TO_RESP(, lhs, ., rhs, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Assigning channel or request/response structs from another struct outside a process. +// +// The channel macros `AXI_LITE_ASSIGN_XX_STRUCT(lhs, rhs)` assign the fields of the `lhs` channel +// struct to the fields of the `rhs` channel struct. They do not assign the handshake signals, +// which are not part of the channel structs. +// The request macro `AXI_LITE_ASSIGN_REQ_STRUCT(lhs, rhs)` assigns all fields of the `lhs` request +// struct to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) +// payload and request-side handshake signals (AW, W, and AR valid and B and R ready). +// The response macro `AXI_LITE_ASSIGN_RESP_STRUCT(lhs, rhs)` assigns all fields of the `lhs` +// response struct to the fields of the `rhs` response struct. This includes all response channel +// (B and R) payload and response-side handshake signals (B and R valid and AW, W, and R ready). +// +// Usage Example: +// `AXI_LITE_ASSIGN_REQ_STRUCT(my_req_struct, another_req_struct) +`define AXI_LITE_ASSIGN_AW_STRUCT(lhs, rhs) `__AXI_LITE_TO_AX(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_W_STRUCT(lhs, rhs) `__AXI_LITE_TO_W(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_B_STRUCT(lhs, rhs) `__AXI_LITE_TO_B(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_AR_STRUCT(lhs, rhs) `__AXI_LITE_TO_AX(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_R_STRUCT(lhs, rhs) `__AXI_LITE_TO_R(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_REQ_STRUCT(lhs, rhs) `__AXI_LITE_TO_REQ(assign, lhs, ., rhs, .) +`define AXI_LITE_ASSIGN_RESP_STRUCT(lhs, rhs) `__AXI_LITE_TO_RESP(assign, lhs, ., rhs, .) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +`endif diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_cut.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_cut.sv new file mode 100644 index 0000000000..6c31321b67 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_cut.sv @@ -0,0 +1,265 @@ +// Copyright (c) 2014-2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Fabian Schuiki +// - Andreas Kurth + +/// An AXI4 cut. +/// +/// Breaks all combinatorial paths between its input and output. +module axi_cut #( + // bypass enable + parameter bit Bypass = 1'b0, + // AXI channel structs + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + // AXI request & response structs + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // salve port + input req_t slv_req_i, + output resp_t slv_resp_o, + // master port + output req_t mst_req_o, + input resp_t mst_resp_i +); + + // a spill register for each channel + spill_register #( + .T ( aw_chan_t ), + .Bypass ( Bypass ) + ) i_reg_aw ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.aw_valid ), + .ready_o ( slv_resp_o.aw_ready ), + .data_i ( slv_req_i.aw ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + + spill_register #( + .T ( w_chan_t ), + .Bypass ( Bypass ) + ) i_reg_w ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.w_valid ), + .ready_o ( slv_resp_o.w_ready ), + .data_i ( slv_req_i.w ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + + spill_register #( + .T ( b_chan_t ), + .Bypass ( Bypass ) + ) i_reg_b ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( slv_resp_o.b_valid ), + .ready_i ( slv_req_i.b_ready ), + .data_o ( slv_resp_o.b ) + ); + + spill_register #( + .T ( ar_chan_t ), + .Bypass ( Bypass ) + ) i_reg_ar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( slv_req_i.ar_valid ), + .ready_o ( slv_resp_o.ar_ready ), + .data_i ( slv_req_i.ar ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + + spill_register #( + .T ( r_chan_t ), + .Bypass ( Bypass ) + ) i_reg_r ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( slv_resp_o.r_valid ), + .ready_i ( slv_req_i.r_ready ), + .data_o ( slv_resp_o.r ) + ); +endmodule + +`include "axi/assign.svh" +`include "axi/typedef.svh" + +// interface wrapper +module axi_cut_intf #( + // Bypass eneable + parameter bit BYPASS = 1'b0, + // The address width. + parameter int unsigned ADDR_WIDTH = 0, + // The data width. + parameter int unsigned DATA_WIDTH = 0, + // The ID width. + parameter int unsigned ID_WIDTH = 0, + // The user data width. + parameter int unsigned USER_WIDTH = 0 +) ( + input logic clk_i , + input logic rst_ni , + AXI_BUS.Slave in , + AXI_BUS.Master out +); + + typedef logic [ID_WIDTH-1:0] id_t; + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + typedef logic [USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, in) + `AXI_ASSIGN_FROM_RESP(in, slv_resp) + + `AXI_ASSIGN_FROM_REQ(out, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, out) + + axi_cut #( + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + + // Check the invariants. + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); + assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); + assert (ID_WIDTH > 0) else $fatal(1, "Wrong id width parameter"); + assert (USER_WIDTH > 0) else $fatal(1, "Wrong user width parameter"); + assert (in.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ID_WIDTH == ID_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_USER_WIDTH == USER_WIDTH) else $fatal(1, "Wrong interface definition"); + end + `endif + // pragma translate_on +endmodule + +module axi_lite_cut_intf #( + // bypass enable + parameter bit BYPASS = 1'b0, + /// The address width. + parameter int unsigned ADDR_WIDTH = 0, + /// The data width. + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic clk_i , + input logic rst_ni , + AXI_LITE.Slave in , + AXI_LITE.Master out +); + + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; + + `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t) + `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t) + `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) + `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) + `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) + `AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) + `AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) + + req_t slv_req, mst_req; + resp_t slv_resp, mst_resp; + + `AXI_LITE_ASSIGN_TO_REQ(slv_req, in) + `AXI_LITE_ASSIGN_FROM_RESP(in, slv_resp) + + `AXI_LITE_ASSIGN_FROM_REQ(out, mst_req) + `AXI_LITE_ASSIGN_TO_RESP(mst_resp, out) + + axi_cut #( + .Bypass ( BYPASS ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( r_chan_t ), + .req_t ( req_t ), + .resp_t ( resp_t ) + ) i_axi_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + + // Check the invariants. + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ADDR_WIDTH > 0) else $fatal(1, "Wrong addr width parameter"); + assert (DATA_WIDTH > 0) else $fatal(1, "Wrong data width parameter"); + assert (in.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (in.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_ADDR_WIDTH == ADDR_WIDTH) else $fatal(1, "Wrong interface definition"); + assert (out.AXI_DATA_WIDTH == DATA_WIDTH) else $fatal(1, "Wrong interface definition"); + end + `endif + // pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_id_prepend.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_id_prepend.sv new file mode 100644 index 0000000000..e9359b9024 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_id_prepend.sv @@ -0,0 +1,161 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Andreas Kurth + +// AXI ID Prepend: This module prepends/strips the MSB from the AXI IDs. +// Constraints enforced through assertions: ID width of slave and master port + +module axi_id_prepend #( + parameter int unsigned NoBus = 1, // Can take multiple axi busses + parameter int unsigned AxiIdWidthSlvPort = 4, // AXI ID Width of the Slave Ports + parameter int unsigned AxiIdWidthMstPort = 6, // AXI ID Width of the Master Ports + parameter type slv_aw_chan_t = logic, // AW Channel Type for slv port + parameter type slv_w_chan_t = logic, // W Channel Type for slv port + parameter type slv_b_chan_t = logic, // B Channel Type for slv port + parameter type slv_ar_chan_t = logic, // AR Channel Type for slv port + parameter type slv_r_chan_t = logic, // R Channel Type for slv port + parameter type mst_aw_chan_t = logic, // AW Channel Type for mst port + parameter type mst_w_chan_t = logic, // W Channel Type for mst port + parameter type mst_b_chan_t = logic, // B Channel Type for mst port + parameter type mst_ar_chan_t = logic, // AR Channel Type for mst port + parameter type mst_r_chan_t = logic, // R Channel Type for mst port + // DEPENDENT PARAMETER DO NOT OVERWRITE! + parameter int unsigned PreIdWidth = AxiIdWidthMstPort - AxiIdWidthSlvPort +) ( + input logic [PreIdWidth-1:0] pre_id_i, // ID to be prepended + // slave port (input), connect master modules here + // AW channel + input slv_aw_chan_t [NoBus-1:0] slv_aw_chans_i, + input logic [NoBus-1:0] slv_aw_valids_i, + output logic [NoBus-1:0] slv_aw_readies_o, + // W channel + input slv_w_chan_t [NoBus-1:0] slv_w_chans_i, + input logic [NoBus-1:0] slv_w_valids_i, + output logic [NoBus-1:0] slv_w_readies_o, + // B channel + output slv_b_chan_t [NoBus-1:0] slv_b_chans_o, + output logic [NoBus-1:0] slv_b_valids_o, + input logic [NoBus-1:0] slv_b_readies_i, + // AR channel + input slv_ar_chan_t [NoBus-1:0] slv_ar_chans_i, + input logic [NoBus-1:0] slv_ar_valids_i, + output logic [NoBus-1:0] slv_ar_readies_o, + // R channel + output slv_r_chan_t [NoBus-1:0] slv_r_chans_o, + output logic [NoBus-1:0] slv_r_valids_o, + input logic [NoBus-1:0] slv_r_readies_i, + // master ports (output), connect slave modules here + // AW channel + output mst_aw_chan_t [NoBus-1:0] mst_aw_chans_o, + output logic [NoBus-1:0] mst_aw_valids_o, + input logic [NoBus-1:0] mst_aw_readies_i, + // W channel + output mst_w_chan_t [NoBus-1:0] mst_w_chans_o, + output logic [NoBus-1:0] mst_w_valids_o, + input logic [NoBus-1:0] mst_w_readies_i, + // B channel + input mst_b_chan_t [NoBus-1:0] mst_b_chans_i, + input logic [NoBus-1:0] mst_b_valids_i, + output logic [NoBus-1:0] mst_b_readies_o, + // AR channel + output mst_ar_chan_t [NoBus-1:0] mst_ar_chans_o, + output logic [NoBus-1:0] mst_ar_valids_o, + input logic [NoBus-1:0] mst_ar_readies_i, + // R channel + input mst_r_chan_t [NoBus-1:0] mst_r_chans_i, + input logic [NoBus-1:0] mst_r_valids_i, + output logic [NoBus-1:0] mst_r_readies_o +); + + // prepend the ID + for (genvar i = 0; i < NoBus; i++) begin : gen_id_prepend + if (PreIdWidth == 0) begin : gen_no_prepend + assign mst_aw_chans_o[i] = slv_aw_chans_i[i]; + assign mst_ar_chans_o[i] = slv_ar_chans_i[i]; + end else begin : gen_prepend + always_comb begin + mst_aw_chans_o[i] = slv_aw_chans_i[i]; + mst_ar_chans_o[i] = slv_ar_chans_i[i]; + mst_aw_chans_o[i].id = {pre_id_i, slv_aw_chans_i[i].id[AxiIdWidthSlvPort-1:0]}; + mst_ar_chans_o[i].id = {pre_id_i, slv_ar_chans_i[i].id[AxiIdWidthSlvPort-1:0]}; + end + end + // The ID is in the highest bits of the struct, so an assignment from a channel with a wide ID + // to a channel with a shorter ID correctly cuts the prepended ID. + assign slv_b_chans_o[i] = mst_b_chans_i[i]; + assign slv_r_chans_o[i] = mst_r_chans_i[i]; + end + + // assign the handshaking's and w channel + assign mst_w_chans_o = slv_w_chans_i; + assign mst_aw_valids_o = slv_aw_valids_i; + assign slv_aw_readies_o = mst_aw_readies_i; + assign mst_w_valids_o = slv_w_valids_i; + assign slv_w_readies_o = mst_w_readies_i; + assign slv_b_valids_o = mst_b_valids_i; + assign mst_b_readies_o = slv_b_readies_i; + assign mst_ar_valids_o = slv_ar_valids_i; + assign slv_ar_readies_o = mst_ar_readies_i; + assign slv_r_valids_o = mst_r_valids_i; + assign mst_r_readies_o = slv_r_readies_i; + +// pragma translate_off +`ifndef VERILATOR + initial begin : p_assert + assert(NoBus > 0) + else $fatal(1, "Input must be at least one element wide."); + assert(PreIdWidth == ($bits(mst_aw_chans_o[0].id) - $bits(slv_aw_chans_i[0].id))) + else $fatal(1, "Prepend ID Width must be: $bits(mst_aw_chans_o.id)-$bits(slv_aw_chans_i.id)"); + assert ($bits(mst_aw_chans_o[0].id) > $bits(slv_aw_chans_i[0].id)) + else $fatal(1, "The master AXI port has to have a wider ID than the slave port."); + end + + aw_id : assert final( + mst_aw_chans_o[0].id[$bits(slv_aw_chans_i[0].id)-1:0] === slv_aw_chans_i[0].id) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_addr : assert final(mst_aw_chans_o[0].addr === slv_aw_chans_i[0].addr) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_len : assert final(mst_aw_chans_o[0].len === slv_aw_chans_i[0].len) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_size : assert final(mst_aw_chans_o[0].size === slv_aw_chans_i[0].size) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + aw_qos : assert final(mst_aw_chans_o[0].qos === slv_aw_chans_i[0].qos) + else $fatal (1, "Something with the AW channel ID prepending went wrong."); + + b_id : assert final( + mst_b_chans_i[0].id[$bits(slv_b_chans_o[0].id)-1:0] === slv_b_chans_o[0].id) + else $fatal (1, "Something with the B channel ID stripping went wrong."); + b_resp : assert final(mst_b_chans_i[0].resp === slv_b_chans_o[0].resp) + else $fatal (1, "Something with the B channel ID stripping went wrong."); + + ar_id : assert final( + mst_ar_chans_o[0].id[$bits(slv_ar_chans_i[0].id)-1:0] === slv_ar_chans_i[0].id) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_addr : assert final(mst_ar_chans_o[0].addr === slv_ar_chans_i[0].addr) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_len : assert final(mst_ar_chans_o[0].len === slv_ar_chans_i[0].len) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_size : assert final(mst_ar_chans_o[0].size === slv_ar_chans_i[0].size) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + ar_qos : assert final(mst_ar_chans_o[0].qos === slv_ar_chans_i[0].qos) + else $fatal (1, "Something with the AR channel ID prepending went wrong."); + + r_id : assert final(mst_r_chans_i[0].id[$bits(slv_r_chans_o[0].id)-1:0] === slv_r_chans_o[0].id) + else $fatal (1, "Something with the R channel ID stripping went wrong."); + r_data : assert final(mst_r_chans_i[0].data === slv_r_chans_o[0].data) + else $fatal (1, "Something with the R channel ID stripping went wrong."); + r_resp : assert final(mst_r_chans_i[0].resp === slv_r_chans_o[0].resp) + else $fatal (1, "Something with the R channel ID stripping went wrong."); +`endif +// pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_id_remap.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_id_remap.sv new file mode 100644 index 0000000000..a2cc347618 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_id_remap.sv @@ -0,0 +1,638 @@ +// Copyright (c) 2014-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Andreas Kurth +// Florian Zaruba +// Wolfgang Roenninger + +`include "common_cells/registers.svh" + +/// Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port. +/// +/// This module is designed to remap an overly wide, sparsely used ID space to a narrower, densely +/// used ID space. This scenario occurs, for example, when an AXI master has wide ID ports but +/// effectively only uses a (not necessarily contiguous) subset of IDs. +/// +/// This module retains the independence of IDs. That is, if two transactions have different IDs at +/// the slave port of this module, they are guaranteed to have different IDs at the master port of +/// this module. This implies a lower bound on the [width of IDs on the master +/// port](#parameter.AxiMstPortIdWidth). If you require narrower master port IDs and can forgo ID +/// independence, use [`axi_id_serialize`](module.axi_id_serialize) instead. +/// +/// Internally, a [table is used for remapping IDs](module.axi_id_remap_table). +module axi_id_remap #( + /// ID width of the AXI4+ATOP slave port. + parameter int unsigned AxiSlvPortIdWidth = 32'd0, + /// Maximum number of different IDs that can be in flight at the slave port. Reads and writes are + /// counted separately (except for ATOPs, which count as both read and write). + /// + /// It is legal for upstream to have transactions with more unique IDs than the maximum given by + /// this parameter in flight, but a transaction exceeding the maximum will be stalled until all + /// transactions of another ID complete. + /// + /// The maximum value of this parameter is `2**AxiSlvPortIdWidth`. + parameter int unsigned AxiSlvPortMaxUniqIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID. + /// + /// It is legal for upstream to have more transactions than the maximum given by this parameter in + /// flight for any ID, but a transaction exceeding the maximum will be stalled until another + /// transaction with the same ID completes. + parameter int unsigned AxiMaxTxnsPerId = 32'd0, + /// ID width of the AXI4+ATOP master port. + /// + /// The minimum value of this parameter is the ceiled binary logarithm of `AxiSlvPortMaxUniqIds`, + /// because IDs at the master port must be wide enough to represent IDs up to + /// `AxiSlvPortMaxUniqIds-1`. + /// + /// If master IDs are wider than the minimum, they are extended by prepending zeros. + parameter int unsigned AxiMstPortIdWidth = 32'd0, + /// Request struct type of the AXI4+ATOP slave port. + /// + /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. + parameter type slv_req_t = logic, + /// Response struct type of the AXI4+ATOP slave port. + /// + /// The width of all IDs in this struct must match `AxiSlvPortIdWidth`. + parameter type slv_resp_t = logic, + /// Request struct type of the AXI4+ATOP master port + /// + /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. + parameter type mst_req_t = logic, + /// Response struct type of the AXI4+ATOP master port + /// + /// The width of all IDs in this struct must match `AxiMstPortIdWidth`. + parameter type mst_resp_t = logic +) ( + /// Rising-edge clock of all ports + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + /// Slave port request + input slv_req_t slv_req_i, + /// Slave port response + output slv_resp_t slv_resp_o, + /// Master port request + output mst_req_t mst_req_o, + /// Master port response + input mst_resp_t mst_resp_i +); + + // Feed all signals that are not ID or flow control of AW and AR through. + assign mst_req_o.aw.addr = slv_req_i.aw.addr; + assign mst_req_o.aw.len = slv_req_i.aw.len; + assign mst_req_o.aw.size = slv_req_i.aw.size; + assign mst_req_o.aw.burst = slv_req_i.aw.burst; + assign mst_req_o.aw.lock = slv_req_i.aw.lock; + assign mst_req_o.aw.cache = slv_req_i.aw.cache; + assign mst_req_o.aw.prot = slv_req_i.aw.prot; + assign mst_req_o.aw.qos = slv_req_i.aw.qos; + assign mst_req_o.aw.region = slv_req_i.aw.region; + assign mst_req_o.aw.atop = slv_req_i.aw.atop; + assign mst_req_o.aw.user = slv_req_i.aw.user; + + assign mst_req_o.w.data = slv_req_i.w.data; + assign mst_req_o.w.strb = slv_req_i.w.strb; + assign mst_req_o.w.last = slv_req_i.w.last; + assign mst_req_o.w.user = slv_req_i.w.user; + assign mst_req_o.w_valid = slv_req_i.w_valid; + assign slv_resp_o.w_ready = mst_resp_i.w_ready; + + assign slv_resp_o.b.resp = mst_resp_i.b.resp; + assign slv_resp_o.b.user = mst_resp_i.b.user; + assign slv_resp_o.b_valid = mst_resp_i.b_valid; + assign mst_req_o.b_ready = slv_req_i.b_ready; + + assign mst_req_o.ar.addr = slv_req_i.ar.addr; + assign mst_req_o.ar.len = slv_req_i.ar.len; + assign mst_req_o.ar.size = slv_req_i.ar.size; + assign mst_req_o.ar.burst = slv_req_i.ar.burst; + assign mst_req_o.ar.lock = slv_req_i.ar.lock; + assign mst_req_o.ar.cache = slv_req_i.ar.cache; + assign mst_req_o.ar.prot = slv_req_i.ar.prot; + assign mst_req_o.ar.qos = slv_req_i.ar.qos; + assign mst_req_o.ar.region = slv_req_i.ar.region; + assign mst_req_o.ar.user = slv_req_i.ar.user; + + assign slv_resp_o.r.data = mst_resp_i.r.data; + assign slv_resp_o.r.resp = mst_resp_i.r.resp; + assign slv_resp_o.r.last = mst_resp_i.r.last; + assign slv_resp_o.r.user = mst_resp_i.r.user; + assign slv_resp_o.r_valid = mst_resp_i.r_valid; + assign mst_req_o.r_ready = slv_req_i.r_ready; + + + // Remap tables keep track of in-flight bursts and their input and output IDs. + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(AxiSlvPortMaxUniqIds); + typedef logic [AxiSlvPortMaxUniqIds-1:0] field_t; + typedef logic [AxiSlvPortIdWidth-1:0] id_inp_t; + typedef logic [IdxWidth-1:0] idx_t; + field_t wr_free, rd_free, both_free; + id_inp_t rd_push_inp_id; + idx_t wr_free_oup_id, rd_free_oup_id, both_free_oup_id, + wr_push_oup_id, rd_push_oup_id, + wr_exists_id, rd_exists_id; + logic wr_exists, rd_exists, + wr_exists_full, rd_exists_full, + wr_full, rd_full, + wr_push, rd_push; + + axi_id_remap_table #( + .InpIdWidth ( AxiSlvPortIdWidth ), + .MaxUniqInpIds ( AxiSlvPortMaxUniqIds ), + .MaxTxnsPerId ( AxiMaxTxnsPerId ) + ) i_wr_table ( + .clk_i, + .rst_ni, + .free_o ( wr_free ), + .free_oup_id_o ( wr_free_oup_id ), + .full_o ( wr_full ), + .push_i ( wr_push ), + .push_inp_id_i ( slv_req_i.aw.id ), + .push_oup_id_i ( wr_push_oup_id ), + .exists_inp_id_i ( slv_req_i.aw.id ), + .exists_o ( wr_exists ), + .exists_oup_id_o ( wr_exists_id ), + .exists_full_o ( wr_exists_full ), + .pop_i ( slv_resp_o.b_valid && slv_req_i.b_ready ), + .pop_oup_id_i ( mst_resp_i.b.id[IdxWidth-1:0] ), + .pop_inp_id_o ( slv_resp_o.b.id ) + ); + axi_id_remap_table #( + .InpIdWidth ( AxiSlvPortIdWidth ), + .MaxUniqInpIds ( AxiSlvPortMaxUniqIds ), + .MaxTxnsPerId ( AxiMaxTxnsPerId ) + ) i_rd_table ( + .clk_i, + .rst_ni, + .free_o ( rd_free ), + .free_oup_id_o ( rd_free_oup_id ), + .full_o ( rd_full ), + .push_i ( rd_push ), + .push_inp_id_i ( rd_push_inp_id ), + .push_oup_id_i ( rd_push_oup_id ), + .exists_inp_id_i ( slv_req_i.ar.id ), + .exists_o ( rd_exists ), + .exists_oup_id_o ( rd_exists_id ), + .exists_full_o ( rd_exists_full ), + .pop_i ( slv_resp_o.r_valid && slv_req_i.r_ready && slv_resp_o.r.last ), + .pop_oup_id_i ( mst_resp_i.r.id[IdxWidth-1:0] ), + .pop_inp_id_o ( slv_resp_o.r.id ) + ); + assign both_free = wr_free & rd_free; + lzc #( + .WIDTH ( AxiSlvPortMaxUniqIds ), + .MODE ( 1'b0 ) + ) i_lzc ( + .in_i ( both_free ), + .cnt_o ( both_free_oup_id ), + .empty_o ( /* unused */ ) + ); + + // Zero-extend output IDs if the output IDs is are wider than the IDs from the tables. + localparam ZeroWidth = AxiMstPortIdWidth - IdxWidth; + assign mst_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id}; + assign mst_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id}; + + // Handle requests. + enum logic [1:0] {Ready, HoldAR, HoldAW, HoldAx} state_d, state_q; + idx_t ar_id_d, ar_id_q, + aw_id_d, aw_id_q; + always_comb begin + mst_req_o.aw_valid = 1'b0; + slv_resp_o.aw_ready = 1'b0; + wr_push = 1'b0; + wr_push_oup_id = '0; + mst_req_o.ar_valid = 1'b0; + slv_resp_o.ar_ready = 1'b0; + rd_push = 1'b0; + rd_push_inp_id = '0; + rd_push_oup_id = '0; + ar_id_d = ar_id_q; + aw_id_d = aw_id_q; + state_d = state_q; + + unique case (state_q) + Ready: begin + // Reads + if (slv_req_i.ar_valid) begin + // If a burst with the same input ID is already in flight or there are free output IDs: + if ((rd_exists && !rd_exists_full) || (!rd_exists && !rd_full)) begin + // Determine the output ID: if another in-flight burst had the same input ID, we must + // reuse its output ID to maintain ordering; else, we assign the next free ID. + rd_push_inp_id = slv_req_i.ar.id; + rd_push_oup_id = rd_exists ? rd_exists_id : rd_free_oup_id; + // Forward the AR and push a new entry to the read table. + mst_req_o.ar_valid = 1'b1; + rd_push = 1'b1; + end + end + + // Writes + if (slv_req_i.aw_valid) begin + // If this is not an ATOP that gives rise to an R response, we can handle it in isolation + // on the write direction. + if (!slv_req_i.aw.atop[5]) begin + // If a burst with the same input ID is already in flight or there are free output IDs: + if ((wr_exists && !wr_exists_full) || (!wr_exists && !wr_full)) begin + // Determine the output ID: if another in-flight burst had the same input ID, we must + // reuse its output ID to maintain ordering; else, we assign the next free ID. + wr_push_oup_id = wr_exists ? wr_exists_id : wr_free_oup_id; + // Forward the AW and push a new entry to the write table. + mst_req_o.aw_valid = 1'b1; + wr_push = 1'b1; + end + // If this is an ATOP that gives rise to an R response, we must remap to an ID that is + // free on both read and write direction and push also to the read table. + end else begin + // Nullify a potential AR at our output. This is legal in this state. + mst_req_o.ar_valid = 1'b0; + slv_resp_o.ar_ready = 1'b0; + rd_push = 1'b0; + if ((|both_free)) begin + // Use an output ID that is free in both directions. + wr_push_oup_id = both_free_oup_id; + rd_push_inp_id = slv_req_i.aw.id; + rd_push_oup_id = both_free_oup_id; + // Forward the AW and push a new entry to both tables. + mst_req_o.aw_valid = 1'b1; + rd_push = 1'b1; + wr_push = 1'b1; + end + end + end + + // Hold AR, AW, or both if they are valid but not yet ready. + if (mst_req_o.ar_valid) begin + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + if (!mst_resp_i.ar_ready) begin + ar_id_d = rd_push_oup_id; + end + end + if (mst_req_o.aw_valid) begin + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + if (!mst_resp_i.aw_ready) begin + aw_id_d = wr_push_oup_id; + end + end + priority casez ({mst_req_o.ar_valid, mst_resp_i.ar_ready, + mst_req_o.aw_valid, mst_resp_i.aw_ready}) + 4'b1010: state_d = HoldAx; + 4'b10??: state_d = HoldAR; + 4'b??10: state_d = HoldAW; + default: state_d = Ready; + endcase + end + + HoldAR: begin + // Drive `mst_req_o.ar.id` through `rd_push_oup_id`. + rd_push_oup_id = ar_id_q; + mst_req_o.ar_valid = 1'b1; + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + if (mst_resp_i.ar_ready) begin + state_d = Ready; + end + end + + HoldAW: begin + // Drive mst_req_o.aw.id through `wr_push_oup_id`. + wr_push_oup_id = aw_id_q; + mst_req_o.aw_valid = 1'b1; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + if (mst_resp_i.aw_ready) begin + state_d = Ready; + end + end + + HoldAx: begin + rd_push_oup_id = ar_id_q; + mst_req_o.ar_valid = 1'b1; + slv_resp_o.ar_ready = mst_resp_i.ar_ready; + wr_push_oup_id = aw_id_q; + mst_req_o.aw_valid = 1'b1; + slv_resp_o.aw_ready = mst_resp_i.aw_ready; + unique case ({mst_resp_i.ar_ready, mst_resp_i.aw_ready}) + 2'b01: state_d = HoldAR; + 2'b10: state_d = HoldAW; + 2'b11: state_d = Ready; + default: /*do nothing / stay in this state*/; + endcase + end + + default: state_d = Ready; + endcase + end + + // Registers + `FFARN(ar_id_q, ar_id_d, '0, clk_i, rst_ni) + `FFARN(aw_id_q, aw_id_d, '0, clk_i, rst_ni) + `FFARN(state_q, state_d, Ready, clk_i, rst_ni) + + // pragma translate_off + `ifndef VERILATOR + initial begin : p_assert + assert(AxiSlvPortIdWidth > 32'd0) + else $fatal(1, "Parameter AxiSlvPortIdWidth has to be larger than 0!"); + assert(AxiMstPortIdWidth >= IdxWidth) + else $fatal(1, "Parameter AxiMstPortIdWidth has to be at least IdxWidth!"); + assert (AxiSlvPortMaxUniqIds > 0) + else $fatal(1, "Parameter AxiSlvPortMaxUniqIds has to be larger than 0!"); + assert (AxiSlvPortMaxUniqIds <= 2**AxiSlvPortIdWidth) + else $fatal(1, "Parameter AxiSlvPortMaxUniqIds may be at most 2**AxiSlvPortIdWidth!"); + assert (AxiMaxTxnsPerId > 0) + else $fatal(1, "Parameter AxiMaxTxnsPerId has to be larger than 0!"); + assert($bits(slv_req_i.aw.addr) == $bits(mst_req_o.aw.addr)) + else $fatal(1, "AXI AW address widths are not equal!"); + assert($bits(slv_req_i.w.data) == $bits(mst_req_o.w.data)) + else $fatal(1, "AXI W data widths are not equal!"); + assert($bits(slv_req_i.w.user) == $bits(mst_req_o.w.user)) + else $fatal(1, "AXI W user widths are not equal!"); + assert($bits(slv_req_i.ar.addr) == $bits(mst_req_o.ar.addr)) + else $fatal(1, "AXI AR address widths are not equal!"); + assert($bits(slv_resp_o.r.data) == $bits(mst_resp_i.r.data)) + else $fatal(1, "AXI R data widths are not equal!"); + assert ($bits(slv_req_i.aw.id) == AxiSlvPortIdWidth); + assert ($bits(slv_resp_o.b.id) == AxiSlvPortIdWidth); + assert ($bits(slv_req_i.ar.id) == AxiSlvPortIdWidth); + assert ($bits(slv_resp_o.r.id) == AxiSlvPortIdWidth); + assert ($bits(mst_req_o.aw.id) == AxiMstPortIdWidth); + assert ($bits(mst_resp_i.b.id) == AxiMstPortIdWidth); + assert ($bits(mst_req_o.ar.id) == AxiMstPortIdWidth); + assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth); + end + default disable iff (!rst_ni); + assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready + |-> mst_req_o.aw_valid && mst_resp_i.aw_ready); + assert property (@(posedge clk_i) mst_resp_i.b_valid && mst_req_o.b_ready + |-> slv_resp_o.b_valid && slv_req_i.b_ready); + assert property (@(posedge clk_i) slv_req_i.ar_valid && slv_resp_o.ar_ready + |-> mst_req_o.ar_valid && mst_resp_i.ar_ready); + assert property (@(posedge clk_i) mst_resp_i.r_valid && mst_req_o.r_ready + |-> slv_resp_o.r_valid && slv_req_i.r_ready); + assert property (@(posedge clk_i) slv_resp_o.r_valid + |-> slv_resp_o.r.last == mst_resp_i.r.last); + assert property (@(posedge clk_i) mst_req_o.ar_valid && !mst_resp_i.ar_ready + |=> mst_req_o.ar_valid && $stable(mst_req_o.ar.id)); + assert property (@(posedge clk_i) mst_req_o.aw_valid && !mst_resp_i.aw_ready + |=> mst_req_o.aw_valid && $stable(mst_req_o.aw.id)); + `endif + // pragma translate_on +endmodule + +/// Internal module of [`axi_id_remap`](module.axi_id_remap): Table to remap input to output IDs. +/// +/// This module contains a table indexed by the output ID (type `idx_t`). Each table entry has two +/// fields: the input ID and a counter that records how many transactions with the input and output +/// ID of the entry are in-flight. +/// +/// The mapping from input and output IDs is injective. Therefore, when the table contains an entry +/// for an input ID with non-zero counter value, subsequent input IDs must use the same entry and +/// thus the same output ID. +/// +/// ## Relation of types and table layout +/// ![diagram of table](axi_id_remap_table.svg) +/// +/// ## Complexity +/// This module has: +/// - `MaxUniqInpIds * InpIdWidth * clog2(MaxTxnsPerId)` flip flops; +/// - `MaxUniqInpIds` comparators of width `InpIdWidth`; +/// - 2 leading-zero counters of width `MaxUniqInpIds`. +module axi_id_remap_table #( + /// Width of input IDs, therefore width of `id_inp_t`. + parameter int unsigned InpIdWidth = 32'd0, + /// Maximum number of different input IDs that can be in-flight. This defines the number of remap + /// table entries. + /// + /// The maximum value of this parameter is `2**InpIdWidth`. + parameter int unsigned MaxUniqInpIds = 32'd0, + /// Maximum number of in-flight transactions with the same ID. + parameter int unsigned MaxTxnsPerId = 32'd0, + /// Derived (**=do not override**) type of input IDs. + localparam type id_inp_t = logic [InpIdWidth-1:0], + /// Derived (**=do not override**) width of table index (ceiled binary logarithm of + /// `MaxUniqInpIds`). + localparam int unsigned IdxWidth = cf_math_pkg::idx_width(MaxUniqInpIds), + /// Derived (**=do not override**) type of table index (width = `IdxWidth`). + localparam type idx_t = logic [IdxWidth-1:0], + /// Derived (**=do not override**) type with one bit per table entry (thus also output ID). + localparam type field_t = logic [MaxUniqInpIds-1:0] +) ( + /// Rising-edge clock of all ports + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + + /// One bit per table entry / output ID that indicates whether the entry is free. + output field_t free_o, + /// Lowest free output ID. Only valid if the table is not full (i.e., `!full_o`). + output idx_t free_oup_id_o, + /// Indicates whether the table is full. + output logic full_o, + + /// Push an input/output ID pair to the table. + input logic push_i, + /// Input ID to be pushed. If the table already contains this ID, its counter must be smaller than + /// `MaxTxnsPerId`. + input id_inp_t push_inp_id_i, + /// Output ID to be pushed. If the table already contains the input ID to be pushed, the output + /// ID **must** match the output ID of the existing entry with the same input ID. + input idx_t push_oup_id_i, + + /// Input ID to look up in the table. + input id_inp_t exists_inp_id_i, + /// Indicates whether the given input ID exists in the table. + output logic exists_o, + /// The output ID of the given input ID. Only valid if the input ID exists (i.e., `exists_o`). + output idx_t exists_oup_id_o, + /// Indicates whether the maximum number of transactions for the given input ID is reached. Only + /// valid if the input ID exists (i.e., `exists_o`). + output logic exists_full_o, + + /// Pop an output ID from the table. This reduces the counter for the table index given in + /// `pop_oup_id_i` by one. + input logic pop_i, + /// Output ID to be popped. The counter for this ID must be larger than `0`. + input idx_t pop_oup_id_i, + /// Input ID corresponding to the popped output ID. + output id_inp_t pop_inp_id_o +); + + /// Counter width, derived to hold numbers up to `MaxTxnsPerId`. + localparam int unsigned CntWidth = $clog2(MaxTxnsPerId+1); + /// Counter that tracks the number of in-flight transactions with an ID. + typedef logic [CntWidth-1:0] cnt_t; + + /// Type of a table entry. + typedef struct packed { + id_inp_t inp_id; + cnt_t cnt; + } entry_t; + + // Table indexed by output IDs that contains the corresponding input IDs + entry_t [MaxUniqInpIds-1:0] table_d, table_q; + + // Determine lowest free output ID. + for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_free_o + assign free_o[i] = table_q[i].cnt == '0; + end + lzc #( + .WIDTH ( MaxUniqInpIds ), + .MODE ( 1'b0 ) + ) i_lzc_free ( + .in_i ( free_o ), + .cnt_o ( free_oup_id_o ), + .empty_o ( full_o ) + ); + + // Determine the input ID for a given output ID. + assign pop_inp_id_o = table_q[pop_oup_id_i].inp_id; + + // Determine if given output ID is already used and, if it is, by which input ID. + field_t match; + for (genvar i = 0; i < MaxUniqInpIds; i++) begin : gen_match + assign match[i] = table_q[i].cnt > 0 && table_q[i].inp_id == exists_inp_id_i; + end + logic no_match; + lzc #( + .WIDTH ( MaxUniqInpIds ), + .MODE ( 1'b0 ) + ) i_lzc_match ( + .in_i ( match ), + .cnt_o ( exists_oup_id_o ), + .empty_o ( no_match ) + ); + assign exists_o = ~no_match; + assign exists_full_o = table_q[exists_oup_id_o].cnt == MaxTxnsPerId; + + // Push and pop table entries. + always_comb begin + table_d = table_q; + if (push_i) begin + table_d[push_oup_id_i].inp_id = push_inp_id_i; + table_d[push_oup_id_i].cnt += 1; + end + if (pop_i) begin + table_d[pop_oup_id_i].cnt -= 1; + end + end + + // Registers + `FFARN(table_q, table_d, '0, clk_i, rst_ni) + + // Assertions + // pragma translate_off + `ifndef VERILATOR + default disable iff (!rst_ni); + assume property (@(posedge clk_i) push_i |-> + table_q[push_oup_id_i].cnt == '0 || table_q[push_oup_id_i].inp_id == push_inp_id_i) + else $error("Push must be to empty output ID or match existing input ID!"); + assume property (@(posedge clk_i) push_i |-> table_q[push_oup_id_i].cnt < MaxTxnsPerId) + else $error("Maximum number of in-flight bursts must not be exceeded!"); + assume property (@(posedge clk_i) pop_i |-> table_q[pop_oup_id_i].cnt > 0) + else $error("Pop must target output ID with non-zero counter!"); + assume property (@(posedge clk_i) $onehot0(match)) + else $error("Input ID in table must be unique!"); + initial begin + assert (InpIdWidth > 0); + assert (MaxUniqInpIds > 0); + assert (MaxUniqInpIds <= (1 << InpIdWidth)); + assert (MaxTxnsPerId > 0); + assert (IdxWidth >= 1); + end + `endif + // pragma translate_on + +endmodule + + +`include "axi/typedef.svh" +`include "axi/assign.svh" +/// Interface variant of [`axi_id_remap`](module.axi_id_remap). +/// +/// See the documentation of the main module for the definition of ports and parameters. +module axi_id_remap_intf #( + parameter int unsigned AXI_SLV_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_SLV_PORT_MAX_UNIQ_IDS = 32'd0, + parameter int unsigned AXI_MAX_TXNS_PER_ID = 32'd0, + parameter int unsigned AXI_MST_PORT_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Slave slv, + AXI_BUS.Master mst +); + typedef logic [AXI_SLV_PORT_ID_WIDTH-1:0] slv_id_t; + typedef logic [AXI_MST_PORT_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] axi_addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] axi_data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t; + typedef logic [AXI_USER_WIDTH-1:0] axi_user_t; + + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(slv_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, axi_addr_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, axi_data_t, slv_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, slv_w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, axi_addr_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(mst_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, axi_addr_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, axi_data_t, mst_id_t, axi_user_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, mst_w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + + slv_req_t slv_req; + slv_resp_t slv_resp; + mst_req_t mst_req; + mst_resp_t mst_resp; + + `AXI_ASSIGN_TO_REQ(slv_req, slv) + `AXI_ASSIGN_FROM_RESP(slv, slv_resp) + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_id_remap #( + .AxiSlvPortIdWidth ( AXI_SLV_PORT_ID_WIDTH ), + .AxiSlvPortMaxUniqIds ( AXI_SLV_PORT_MAX_UNIQ_IDS ), + .AxiMaxTxnsPerId ( AXI_MAX_TXNS_PER_ID ), + .AxiMstPortIdWidth ( AXI_MST_PORT_ID_WIDTH ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ) + ) i_axi_id_remap ( + .clk_i, + .rst_ni, + .slv_req_i ( slv_req ), + .slv_resp_o ( slv_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (slv.AXI_ID_WIDTH == AXI_SLV_PORT_ID_WIDTH); + assert (slv.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (slv.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (slv.AXI_USER_WIDTH == AXI_USER_WIDTH); + assert (mst.AXI_ID_WIDTH == AXI_MST_PORT_ID_WIDTH); + assert (mst.AXI_ADDR_WIDTH == AXI_ADDR_WIDTH); + assert (mst.AXI_DATA_WIDTH == AXI_DATA_WIDTH); + assert (mst.AXI_USER_WIDTH == AXI_USER_WIDTH); + end + `endif + // pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_intf.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_intf.sv new file mode 100644 index 0000000000..0d43ffbae4 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_intf.sv @@ -0,0 +1,549 @@ +// Copyright (c) 2014-2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Fabian Schuiki +// - Wolfgang Roenninger +// - Andreas Kurth + + + +/// An AXI4 interface. +interface AXI_BUS #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0 +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + logic w_valid; + logic w_ready; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + logic b_valid; + logic b_ready; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + logic ar_valid; + logic ar_ready; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, + output w_data, w_strb, w_last, w_user, w_valid, input w_ready, + input b_id, b_resp, b_user, b_valid, output b_ready, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, + input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, + input w_data, w_strb, w_last, w_user, w_valid, output w_ready, + output b_id, b_resp, b_user, b_valid, input b_ready, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, + output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready + ); + +endinterface + + +/// A clocked AXI4 interface for use in design verification. +interface AXI_BUS_DV #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0 +)( + input logic clk_i +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + logic w_valid; + logic w_ready; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + logic b_valid; + logic b_ready; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + logic ar_valid; + logic ar_ready; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, input aw_ready, + output w_data, w_strb, w_last, w_user, w_valid, input w_ready, + input b_id, b_resp, b_user, b_valid, output b_ready, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, input ar_ready, + input r_id, r_data, r_resp, r_last, r_user, r_valid, output r_ready + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, output aw_ready, + input w_data, w_strb, w_last, w_user, w_valid, output w_ready, + output b_id, b_resp, b_user, b_valid, input b_ready, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, output ar_ready, + output r_id, r_data, r_resp, r_last, r_user, r_valid, input r_ready + ); + + modport Monitor ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_valid, aw_ready, + w_data, w_strb, w_last, w_user, w_valid, w_ready, + b_id, b_resp, b_user, b_valid, b_ready, + ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_valid, ar_ready, + r_id, r_data, r_resp, r_last, r_user, r_valid, r_ready + ); + + // pragma translate_off + `ifndef VERILATOR + // Single-Channel Assertions: Signals including valid must not change between valid and handshake. + // AW + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_id))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_addr))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_len))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_size))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_burst))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_lock))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_cache))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_prot))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_qos))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_region))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_atop))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> $stable(aw_user))); + assert property (@(posedge clk_i) (aw_valid && !aw_ready |=> aw_valid)); + // W + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_data))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_strb))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_last))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> $stable(w_user))); + assert property (@(posedge clk_i) ( w_valid && ! w_ready |=> w_valid)); + // B + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_id))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_resp))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> $stable(b_user))); + assert property (@(posedge clk_i) ( b_valid && ! b_ready |=> b_valid)); + // AR + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_id))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_addr))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_len))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_size))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_burst))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_lock))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_cache))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_prot))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_qos))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_region))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> $stable(ar_user))); + assert property (@(posedge clk_i) (ar_valid && !ar_ready |=> ar_valid)); + // R + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_id))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_data))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_resp))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_last))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> $stable(r_user))); + assert property (@(posedge clk_i) ( r_valid && ! r_ready |=> r_valid)); + `endif + // pragma translate_on + +endinterface + + +/// An asynchronous AXI4 interface. +interface AXI_BUS_ASYNC +#( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned BUFFER_WIDTH = 0 +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + typedef logic [BUFFER_WIDTH-1:0] buffer_t; + + id_t aw_id; + addr_t aw_addr; + axi_pkg::len_t aw_len; + axi_pkg::size_t aw_size; + axi_pkg::burst_t aw_burst; + logic aw_lock; + axi_pkg::cache_t aw_cache; + axi_pkg::prot_t aw_prot; + axi_pkg::qos_t aw_qos; + axi_pkg::region_t aw_region; + axi_pkg::atop_t aw_atop; + user_t aw_user; + buffer_t aw_writetoken; + buffer_t aw_readpointer; + + data_t w_data; + strb_t w_strb; + logic w_last; + user_t w_user; + buffer_t w_writetoken; + buffer_t w_readpointer; + + id_t b_id; + axi_pkg::resp_t b_resp; + user_t b_user; + buffer_t b_writetoken; + buffer_t b_readpointer; + + id_t ar_id; + addr_t ar_addr; + axi_pkg::len_t ar_len; + axi_pkg::size_t ar_size; + axi_pkg::burst_t ar_burst; + logic ar_lock; + axi_pkg::cache_t ar_cache; + axi_pkg::prot_t ar_prot; + axi_pkg::qos_t ar_qos; + axi_pkg::region_t ar_region; + user_t ar_user; + buffer_t ar_writetoken; + buffer_t ar_readpointer; + + id_t r_id; + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_last; + user_t r_user; + buffer_t r_writetoken; + buffer_t r_readpointer; + + modport Master ( + output aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, input aw_readpointer, + output w_data, w_strb, w_last, w_user, w_writetoken, input w_readpointer, + input b_id, b_resp, b_user, b_writetoken, output b_readpointer, + output ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, input ar_readpointer, + input r_id, r_data, r_resp, r_last, r_user, r_writetoken, output r_readpointer + ); + + modport Slave ( + input aw_id, aw_addr, aw_len, aw_size, aw_burst, aw_lock, aw_cache, aw_prot, aw_qos, aw_region, aw_atop, aw_user, aw_writetoken, output aw_readpointer, + input w_data, w_strb, w_last, w_user, w_writetoken, output w_readpointer, + output b_id, b_resp, b_user, b_writetoken, input b_readpointer, + input ar_id, ar_addr, ar_len, ar_size, ar_burst, ar_lock, ar_cache, ar_prot, ar_qos, ar_region, ar_user, ar_writetoken, output ar_readpointer, + output r_id, r_data, r_resp, r_last, r_user, r_writetoken, input r_readpointer + ); + +endinterface + + +`include "axi/typedef.svh" + +/// An asynchronous AXI4 interface for Gray CDCs. +interface AXI_BUS_ASYNC_GRAY #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + parameter int unsigned LOG_DEPTH = 0 +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ID_WIDTH-1:0] id_t; + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) + + aw_chan_t [2**LOG_DEPTH-1:0] aw_data; + w_chan_t [2**LOG_DEPTH-1:0] w_data; + b_chan_t [2**LOG_DEPTH-1:0] b_data; + ar_chan_t [2**LOG_DEPTH-1:0] ar_data; + r_chan_t [2**LOG_DEPTH-1:0] r_data; + logic [LOG_DEPTH:0] aw_wptr, aw_rptr, + w_wptr, w_rptr, + b_wptr, b_rptr, + ar_wptr, ar_rptr, + r_wptr, r_rptr; + + modport Master ( + output aw_data, aw_wptr, input aw_rptr, + output w_data, w_wptr, input w_rptr, + input b_data, b_wptr, output b_rptr, + output ar_data, ar_wptr, input ar_rptr, + input r_data, r_wptr, output r_rptr); + + modport Slave ( + input aw_data, aw_wptr, output aw_rptr, + input w_data, w_wptr, output w_rptr, + output b_data, b_wptr, input b_rptr, + input ar_data, ar_wptr, output ar_rptr, + output r_data, r_wptr, input r_rptr); + +endinterface + + +/// An AXI4-Lite interface. +interface AXI_LITE #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0 +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + + // AW channel + addr_t aw_addr; + axi_pkg::prot_t aw_prot; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_ready; + + axi_pkg::resp_t b_resp; + logic b_valid; + logic b_ready; + + addr_t ar_addr; + axi_pkg::prot_t ar_prot; + logic ar_valid; + logic ar_ready; + + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_addr, aw_prot, aw_valid, input aw_ready, + output w_data, w_strb, w_valid, input w_ready, + input b_resp, b_valid, output b_ready, + output ar_addr, ar_prot, ar_valid, input ar_ready, + input r_data, r_resp, r_valid, output r_ready + ); + + modport Slave ( + input aw_addr, aw_prot, aw_valid, output aw_ready, + input w_data, w_strb, w_valid, output w_ready, + output b_resp, b_valid, input b_ready, + input ar_addr, ar_prot, ar_valid, output ar_ready, + output r_data, r_resp, r_valid, input r_ready + ); + +endinterface + + +/// A clocked AXI4-Lite interface for use in design verification. +interface AXI_LITE_DV #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0 +)( + input logic clk_i +); + + localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + + // AW channel + addr_t aw_addr; + axi_pkg::prot_t aw_prot; + logic aw_valid; + logic aw_ready; + + data_t w_data; + strb_t w_strb; + logic w_valid; + logic w_ready; + + axi_pkg::resp_t b_resp; + logic b_valid; + logic b_ready; + + addr_t ar_addr; + axi_pkg::prot_t ar_prot; + logic ar_valid; + logic ar_ready; + + data_t r_data; + axi_pkg::resp_t r_resp; + logic r_valid; + logic r_ready; + + modport Master ( + output aw_addr, aw_prot, aw_valid, input aw_ready, + output w_data, w_strb, w_valid, input w_ready, + input b_resp, b_valid, output b_ready, + output ar_addr, ar_prot, ar_valid, input ar_ready, + input r_data, r_resp, r_valid, output r_ready + ); + + modport Slave ( + input aw_addr, aw_prot, aw_valid, output aw_ready, + input w_data, w_strb, w_valid, output w_ready, + output b_resp, b_valid, input b_ready, + input ar_addr, ar_prot, ar_valid, output ar_ready, + output r_data, r_resp, r_valid, input r_ready + ); + +endinterface + + +/// An asynchronous AXI4-Lite interface for Gray CDCs. +interface AXI_LITE_ASYNC_GRAY #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned LOG_DEPTH = 0 +); + + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; + + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_STRB_WIDTH-1:0] strb_t; + + `AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t) + `AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t) + `AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t) + `AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t) + `AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t) + + aw_chan_t [2**LOG_DEPTH-1:0] aw_data; + w_chan_t [2**LOG_DEPTH-1:0] w_data; + b_chan_t [2**LOG_DEPTH-1:0] b_data; + ar_chan_t [2**LOG_DEPTH-1:0] ar_data; + r_chan_t [2**LOG_DEPTH-1:0] r_data; + logic [LOG_DEPTH:0] aw_wptr, aw_rptr, + w_wptr, w_rptr, + b_wptr, b_rptr, + ar_wptr, ar_rptr, + r_wptr, r_rptr; + + modport Master ( + output aw_data, aw_wptr, input aw_rptr, + output w_data, w_wptr, input w_rptr, + input b_data, b_wptr, output b_rptr, + output ar_data, ar_wptr, input ar_rptr, + input r_data, r_wptr, output r_rptr); + + modport Slave ( + input aw_data, aw_wptr, output aw_rptr, + input w_data, w_wptr, output w_rptr, + output b_data, b_wptr, input b_rptr, + input ar_data, ar_wptr, output ar_rptr, + output r_data, r_wptr, input r_rptr); + +endinterface diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_mux.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_mux.sv new file mode 100644 index 0000000000..59ee3ec465 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_mux.sv @@ -0,0 +1,522 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Wolfgang Roenninger +// - Andreas Kurth + +// AXI Multiplexer: This module multiplexes the AXI4 slave ports down to one master port. +// The AXI IDs from the slave ports get extended with the respective slave port index. +// The extension width can be calculated with `$clog2(NoSlvPorts)`. This means the AXI +// ID for the master port has to be this `$clog2(NoSlvPorts)` wider than the ID for the +// slave ports. +// Responses are switched based on these bits. For example, with 4 slave ports +// a response with ID `6'b100110` will be forwarded to slave port 2 (`2'b10`). + +// register macros +`include "common_cells/registers.svh" + +module axi_mux #( + // AXI parameter and channel types + parameter int unsigned SlvAxiIDWidth = 32'd0, // AXI ID width, slave ports + parameter type slv_aw_chan_t = logic, // AW Channel Type, slave ports + parameter type mst_aw_chan_t = logic, // AW Channel Type, master port + parameter type w_chan_t = logic, // W Channel Type, all ports + parameter type slv_b_chan_t = logic, // B Channel Type, slave ports + parameter type mst_b_chan_t = logic, // B Channel Type, master port + parameter type slv_ar_chan_t = logic, // AR Channel Type, slave ports + parameter type mst_ar_chan_t = logic, // AR Channel Type, master port + parameter type slv_r_chan_t = logic, // R Channel Type, slave ports + parameter type mst_r_chan_t = logic, // R Channel Type, master port + parameter type slv_req_t = logic, // Slave port request type + parameter type slv_resp_t = logic, // Slave port response type + parameter type mst_req_t = logic, // Master ports request type + parameter type mst_resp_t = logic, // Master ports response type + parameter int unsigned NoSlvPorts = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MaxWTrans = 32'd8, + // If enabled, this multiplexer is purely combinatorial + parameter bit FallThrough = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SpillAw = 1'b1, + parameter bit SpillW = 1'b0, + parameter bit SpillB = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SpillAr = 1'b1, + parameter bit SpillR = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Test Mode enable + // slave ports (AXI inputs), connect master modules here + input slv_req_t [NoSlvPorts-1:0] slv_reqs_i, + output slv_resp_t [NoSlvPorts-1:0] slv_resps_o, + // master port (AXI outputs), connect slave modules here + output mst_req_t mst_req_o, + input mst_resp_t mst_resp_i +); + + localparam int unsigned MstIdxBits = $clog2(NoSlvPorts); + localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits; + + // pass through if only one slave port + if (NoSlvPorts == 32'h1) begin : gen_no_mux + assign mst_req_o = slv_reqs_i[0]; + assign slv_resps_o[0] = mst_resp_i; + // other non degenerate cases + end else begin : gen_mux + + typedef logic [MstIdxBits-1:0] switch_id_t; + + // AXI channels between the ID prepend unit and the rest of the multiplexer + mst_aw_chan_t [NoSlvPorts-1:0] slv_aw_chans; + logic [NoSlvPorts-1:0] slv_aw_valids, slv_aw_readies; + w_chan_t [NoSlvPorts-1:0] slv_w_chans; + logic [NoSlvPorts-1:0] slv_w_valids, slv_w_readies; + mst_b_chan_t [NoSlvPorts-1:0] slv_b_chans; + logic [NoSlvPorts-1:0] slv_b_valids, slv_b_readies; + mst_ar_chan_t [NoSlvPorts-1:0] slv_ar_chans; + logic [NoSlvPorts-1:0] slv_ar_valids, slv_ar_readies; + mst_r_chan_t [NoSlvPorts-1:0] slv_r_chans; + logic [NoSlvPorts-1:0] slv_r_valids, slv_r_readies; + + // These signals are all ID prepended + // AW channel + mst_aw_chan_t mst_aw_chan; + logic mst_aw_valid, mst_aw_ready; + + // AW master handshake internal, so that we are able to stall, if w_fifo is full + logic aw_valid, aw_ready; + + // FF to lock the AW valid signal, when a new arbitration decision is made the decision + // gets pushed into the W FIFO, when it now stalls prevent subsequent pushing + // This FF removes AW to W dependency + logic lock_aw_valid_d, lock_aw_valid_q; + logic load_aw_lock; + + // signals for the FIFO that holds the last switching decision of the AW channel + logic w_fifo_full, w_fifo_empty; + logic w_fifo_push, w_fifo_pop; + switch_id_t w_fifo_data; + + // W channel spill reg + w_chan_t mst_w_chan; + logic mst_w_valid, mst_w_ready; + + // master ID in the b_id + switch_id_t switch_b_id; + + // B channel spill reg + mst_b_chan_t mst_b_chan; + logic mst_b_valid; + + // AR channel for when spill is enabled + mst_ar_chan_t mst_ar_chan; + logic ar_valid, ar_ready; + + // master ID in the r_id + switch_id_t switch_r_id; + + // R channel spill reg + mst_r_chan_t mst_r_chan; + logic mst_r_valid; + + //-------------------------------------- + // ID prepend for all slave ports + //-------------------------------------- + for (genvar i = 0; i < NoSlvPorts; i++) begin : gen_id_prepend + axi_id_prepend #( + .NoBus ( 32'd1 ), // one AXI bus per slave port + .AxiIdWidthSlvPort( SlvAxiIDWidth ), + .AxiIdWidthMstPort( MstAxiIDWidth ), + .slv_aw_chan_t ( slv_aw_chan_t ), + .slv_w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .slv_ar_chan_t ( slv_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_aw_chan_t ( mst_aw_chan_t ), + .mst_w_chan_t ( w_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .mst_ar_chan_t ( mst_ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ) + ) i_id_prepend ( + .pre_id_i ( switch_id_t'(i) ), + .slv_aw_chans_i ( slv_reqs_i[i].aw ), + .slv_aw_valids_i ( slv_reqs_i[i].aw_valid ), + .slv_aw_readies_o ( slv_resps_o[i].aw_ready ), + .slv_w_chans_i ( slv_reqs_i[i].w ), + .slv_w_valids_i ( slv_reqs_i[i].w_valid ), + .slv_w_readies_o ( slv_resps_o[i].w_ready ), + .slv_b_chans_o ( slv_resps_o[i].b ), + .slv_b_valids_o ( slv_resps_o[i].b_valid ), + .slv_b_readies_i ( slv_reqs_i[i].b_ready ), + .slv_ar_chans_i ( slv_reqs_i[i].ar ), + .slv_ar_valids_i ( slv_reqs_i[i].ar_valid ), + .slv_ar_readies_o ( slv_resps_o[i].ar_ready ), + .slv_r_chans_o ( slv_resps_o[i].r ), + .slv_r_valids_o ( slv_resps_o[i].r_valid ), + .slv_r_readies_i ( slv_reqs_i[i].r_ready ), + .mst_aw_chans_o ( slv_aw_chans[i] ), + .mst_aw_valids_o ( slv_aw_valids[i] ), + .mst_aw_readies_i ( slv_aw_readies[i] ), + .mst_w_chans_o ( slv_w_chans[i] ), + .mst_w_valids_o ( slv_w_valids[i] ), + .mst_w_readies_i ( slv_w_readies[i] ), + .mst_b_chans_i ( slv_b_chans[i] ), + .mst_b_valids_i ( slv_b_valids[i] ), + .mst_b_readies_o ( slv_b_readies[i] ), + .mst_ar_chans_o ( slv_ar_chans[i] ), + .mst_ar_valids_o ( slv_ar_valids[i] ), + .mst_ar_readies_i ( slv_ar_readies[i] ), + .mst_r_chans_i ( slv_r_chans[i] ), + .mst_r_valids_i ( slv_r_valids[i] ), + .mst_r_readies_o ( slv_r_readies[i] ) + ); + end + + //-------------------------------------- + // AW Channel + //-------------------------------------- + rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .DataType ( mst_aw_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_aw_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_aw_valids ), + .gnt_o ( slv_aw_readies ), + .data_i ( slv_aw_chans ), + .gnt_i ( aw_ready ), + .req_o ( aw_valid ), + .data_o ( mst_aw_chan ), + .idx_o ( ) + ); + + // control of the AW channel + always_comb begin + // default assignments + lock_aw_valid_d = lock_aw_valid_q; + load_aw_lock = 1'b0; + w_fifo_push = 1'b0; + mst_aw_valid = 1'b0; + aw_ready = 1'b0; + // had a downstream stall, be valid and send the AW along + if (lock_aw_valid_q) begin + mst_aw_valid = 1'b1; + // transaction + if (mst_aw_ready) begin + aw_ready = 1'b1; + lock_aw_valid_d = 1'b0; + load_aw_lock = 1'b1; + end + end else begin + if (!w_fifo_full && aw_valid) begin + mst_aw_valid = 1'b1; + w_fifo_push = 1'b1; + if (mst_aw_ready) begin + aw_ready = 1'b1; + end else begin + // go to lock if transaction not in this cycle + lock_aw_valid_d = 1'b1; + load_aw_lock = 1'b1; + end + end + end + end + + `FFLARN(lock_aw_valid_q, lock_aw_valid_d, load_aw_lock, '0, clk_i, rst_ni) + + fifo_v3 #( + .FALL_THROUGH ( FallThrough ), + .DEPTH ( MaxWTrans ), + .dtype ( switch_id_t ) + ) i_w_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i( test_i ), + .full_o ( w_fifo_full ), + .empty_o ( w_fifo_empty ), + .usage_o ( ), + .data_i ( mst_aw_chan.id[SlvAxiIDWidth+:MstIdxBits] ), + .push_i ( w_fifo_push ), + .data_o ( w_fifo_data ), + .pop_i ( w_fifo_pop ) + ); + + spill_register #( + .T ( mst_aw_chan_t ), + .Bypass ( ~SpillAw ) // Param indicated that we want a spill reg + ) i_aw_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_aw_valid ), + .ready_o ( mst_aw_ready ), + .data_i ( mst_aw_chan ), + .valid_o ( mst_req_o.aw_valid ), + .ready_i ( mst_resp_i.aw_ready ), + .data_o ( mst_req_o.aw ) + ); + + //-------------------------------------- + // W Channel + //-------------------------------------- + // multiplexer + assign mst_w_chan = slv_w_chans[w_fifo_data]; + always_comb begin + // default assignments + mst_w_valid = 1'b0; + slv_w_readies = '0; + w_fifo_pop = 1'b0; + // control + if (!w_fifo_empty) begin + // connect the handshake + mst_w_valid = slv_w_valids[w_fifo_data]; + slv_w_readies[w_fifo_data] = mst_w_ready; + // pop FIFO on a last transaction + w_fifo_pop = slv_w_valids[w_fifo_data] & mst_w_ready & mst_w_chan.last; + end + end + + spill_register #( + .T ( w_chan_t ), + .Bypass ( ~SpillW ) + ) i_w_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_w_valid ), + .ready_o ( mst_w_ready ), + .data_i ( mst_w_chan ), + .valid_o ( mst_req_o.w_valid ), + .ready_i ( mst_resp_i.w_ready ), + .data_o ( mst_req_o.w ) + ); + + //-------------------------------------- + // B Channel + //-------------------------------------- + // replicate B channels + assign slv_b_chans = {NoSlvPorts{mst_b_chan}}; + // control B channel handshake + assign switch_b_id = mst_b_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_b_valids = (mst_b_valid) ? (1 << switch_b_id) : '0; + + spill_register #( + .T ( mst_b_chan_t ), + .Bypass ( ~SpillB ) + ) i_b_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.b_valid ), + .ready_o ( mst_req_o.b_ready ), + .data_i ( mst_resp_i.b ), + .valid_o ( mst_b_valid ), + .ready_i ( slv_b_readies[switch_b_id] ), + .data_o ( mst_b_chan ) + ); + + //-------------------------------------- + // AR Channel + //-------------------------------------- + rr_arb_tree #( + .NumIn ( NoSlvPorts ), + .DataType ( mst_ar_chan_t ), + .AxiVldRdy( 1'b1 ), + .LockIn ( 1'b1 ) + ) i_ar_arbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( 1'b0 ), + .rr_i ( '0 ), + .req_i ( slv_ar_valids ), + .gnt_o ( slv_ar_readies ), + .data_i ( slv_ar_chans ), + .gnt_i ( ar_ready ), + .req_o ( ar_valid ), + .data_o ( mst_ar_chan ), + .idx_o ( ) + ); + + spill_register #( + .T ( mst_ar_chan_t ), + .Bypass ( ~SpillAr ) + ) i_ar_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( ar_valid ), + .ready_o ( ar_ready ), + .data_i ( mst_ar_chan ), + .valid_o ( mst_req_o.ar_valid ), + .ready_i ( mst_resp_i.ar_ready ), + .data_o ( mst_req_o.ar ) + ); + + //-------------------------------------- + // R Channel + //-------------------------------------- + // replicate R channels + assign slv_r_chans = {NoSlvPorts{mst_r_chan}}; + // R channel handshake control + assign switch_r_id = mst_r_chan.id[SlvAxiIDWidth+:MstIdxBits]; + assign slv_r_valids = (mst_r_valid) ? (1 << switch_r_id) : '0; + + spill_register #( + .T ( mst_r_chan_t ), + .Bypass ( ~SpillR ) + ) i_r_spill_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( mst_resp_i.r_valid ), + .ready_o ( mst_req_o.r_ready ), + .data_i ( mst_resp_i.r ), + .valid_o ( mst_r_valid ), + .ready_i ( slv_r_readies[switch_r_id] ), + .data_o ( mst_r_chan ) + ); + end + +// pragma translate_off +`ifndef VERILATOR + initial begin + assert (SlvAxiIDWidth > 0) else $fatal(1, "AXI ID width of slave ports must be non-zero!"); + assert (NoSlvPorts > 0) else $fatal(1, "Number of slave ports must be non-zero!"); + assert (MaxWTrans > 0) + else $fatal(1, "Maximum number of outstanding writes must be non-zero!"); + assert (MstAxiIDWidth >= SlvAxiIDWidth + $clog2(NoSlvPorts)) + else $fatal(1, "AXI ID width of master ports must be wide enough to identify slave ports!"); + // Assert ID widths (one slave is sufficient since they all have the same type). + assert ($unsigned($bits(slv_reqs_i[0].aw.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AW channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_reqs_i[0].ar.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of AR channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].b.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of B channel of slave ports does not match parameter!"); + assert ($unsigned($bits(slv_resps_o[0].r.id)) == SlvAxiIDWidth) + else $fatal(1, "ID width of R channel of slave ports does not match parameter!"); + assert ($unsigned($bits(mst_req_o.aw.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AW channel of master port is wrong!"); + assert ($unsigned($bits(mst_req_o.ar.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of AR channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.b.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of B channel of master port is wrong!"); + assert ($unsigned($bits(mst_resp_i.r.id)) == MstAxiIDWidth) + else $fatal(1, "ID width of R channel of master port is wrong!"); + end +`endif +// pragma translate_on +endmodule + +// interface wrap +`include "axi/assign.svh" +`include "axi/typedef.svh" +module axi_mux_intf #( + parameter int unsigned SLV_AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params + parameter int unsigned MST_AXI_ID_WIDTH = 32'd0, + parameter int unsigned AXI_ADDR_WIDTH = 32'd0, + parameter int unsigned AXI_DATA_WIDTH = 32'd0, + parameter int unsigned AXI_USER_WIDTH = 32'd0, + parameter int unsigned NO_SLV_PORTS = 32'd0, // Number of slave ports + // Maximum number of outstanding transactions per write + parameter int unsigned MAX_W_TRANS = 32'd8, + // if enabled, this multiplexer is purely combinatorial + parameter bit FALL_THROUGH = 1'b0, + // add spill register on write master ports, adds a cycle latency on write channels + parameter bit SPILL_AW = 1'b1, + parameter bit SPILL_W = 1'b0, + parameter bit SPILL_B = 1'b0, + // add spill register on read master ports, adds a cycle latency on read channels + parameter bit SPILL_AR = 1'b1, + parameter bit SPILL_R = 1'b0 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic test_i, // Testmode enable + AXI_BUS.Slave slv [NO_SLV_PORTS-1:0], // slave ports + AXI_BUS.Master mst // master port +); + + typedef logic [SLV_AXI_ID_WIDTH-1:0] slv_id_t; + typedef logic [MST_AXI_ID_WIDTH-1:0] mst_id_t; + typedef logic [AXI_ADDR_WIDTH -1:0] addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + // channels typedef + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + + slv_req_t [NO_SLV_PORTS-1:0] slv_reqs; + slv_resp_t [NO_SLV_PORTS-1:0] slv_resps; + mst_req_t mst_req; + mst_resp_t mst_resp; + + for (genvar i = 0; i < NO_SLV_PORTS; i++) begin : gen_assign_slv_ports + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv[i]) + `AXI_ASSIGN_FROM_RESP(slv[i], slv_resps[i]) + end + + `AXI_ASSIGN_FROM_REQ(mst, mst_req) + `AXI_ASSIGN_TO_RESP(mst_resp, mst) + + axi_mux #( + .SlvAxiIDWidth ( SLV_AXI_ID_WIDTH ), + .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port + .w_chan_t ( w_chan_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .NoSlvPorts ( NO_SLV_PORTS ), // Number of slave ports + .MaxWTrans ( MAX_W_TRANS ), + .FallThrough ( FALL_THROUGH ), + .SpillAw ( SPILL_AW ), + .SpillW ( SPILL_W ), + .SpillB ( SPILL_B ), + .SpillAr ( SPILL_AR ), + .SpillR ( SPILL_R ) + ) i_axi_mux ( + .clk_i ( clk_i ), // Clock + .rst_ni ( rst_ni ), // Asynchronous reset active low + .test_i ( test_i ), // Test Mode enable + .slv_reqs_i ( slv_reqs ), + .slv_resps_o ( slv_resps ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); +endmodule diff --git a/flow/designs/src/mempool_group/rtl/axi/src/axi_pkg.sv b/flow/designs/src/mempool_group/rtl/axi/src/axi_pkg.sv new file mode 100644 index 0000000000..92ede558c1 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/axi_pkg.sv @@ -0,0 +1,423 @@ +// Copyright (c) 2014-2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Andreas Kurth +// - Florian Zaruba +// - Wolfgang Roenninger +// - Fabian Schuiki +// - Matheus Cavalcante + +//! AXI Package +/// Contains all necessary type definitions, constants, and generally useful functions. +package axi_pkg; + /// AXI Transaction Burst Type. + typedef logic [1:0] burst_t; + /// AXI Transaction Response Type. + typedef logic [1:0] resp_t; + /// AXI Transaction Cacheability Type. + typedef logic [3:0] cache_t; + /// AXI Transaction Protection Type. + typedef logic [2:0] prot_t; + /// AXI Transaction Quality of Service Type. + typedef logic [3:0] qos_t; + /// AXI Transaction Region Type. + typedef logic [3:0] region_t; + /// AXI Transaction Length Type. + typedef logic [7:0] len_t; + /// AXI Transaction Size Type. + typedef logic [2:0] size_t; + /// AXI5 Atomic Operation Type. + typedef logic [5:0] atop_t; // atomic operations + /// AXI5 Non-Secure Address Identifier. + typedef logic [3:0] nsaid_t; + + /// In a fixed burst: + /// - The address is the same for every transfer in the burst. + /// - The byte lanes that are valid are constant for all beats in the burst. However, within + /// those byte lanes, the actual bytes that have `wstrb` asserted can differ for each beat in + /// the burst. + /// This burst type is used for repeated accesses to the same location such as when loading or + /// emptying a FIFO. + localparam BURST_FIXED = 2'b00; + /// In an incrementing burst, the address for each transfer in the burst is an increment of the + /// address for the previous transfer. The increment value depends on the size of the transfer. + /// For example, the address for each transfer in a burst with a size of 4 bytes is the previous + /// address plus four. + /// This burst type is used for accesses to normal sequential memory. + localparam BURST_INCR = 2'b01; + /// A wrapping burst is similar to an incrementing burst, except that the address wraps around to + /// a lower address if an upper address limit is reached. + /// The following restrictions apply to wrapping bursts: + /// - The start address must be aligned to the size of each transfer. + /// - The length of the burst must be 2, 4, 8, or 16 transfers. + localparam BURST_WRAP = 2'b10; + + /// Normal access success. Indicates that a normal access has been successful. Can also indicate + /// that an exclusive access has failed. + localparam RESP_OKAY = 2'b00; + /// Exclusive access okay. Indicates that either the read or write portion of an exclusive access + /// has been successful. + localparam RESP_EXOKAY = 2'b01; + /// Slave error. Used when the access has reached the slave successfully, but the slave wishes to + /// return an error condition to the originating master. + localparam RESP_SLVERR = 2'b10; + /// Decode error. Generated, typically by an interconnect component, to indicate that there is no + /// slave at the transaction address. + localparam RESP_DECERR = 2'b11; + + /// When this bit is asserted, the interconnect, or any component, can delay the transaction + /// reaching its final destination for any number of cycles. + localparam CACHE_BUFFERABLE = 4'b0001; + /// When HIGH, Modifiable indicates that the characteristics of the transaction can be modified. + /// When Modifiable is LOW, the transaction is Non-modifiable. + localparam CACHE_MODIFIABLE = 4'b0010; + /// When this bit is asserted, read allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_RD_ALLOC = 4'b0100; + /// When this bit is asserted, write allocation of the transaction is recommended but is not + /// mandatory. + localparam CACHE_WR_ALLOC = 4'b1000; + + /// Maximum number of bytes per burst, as specified by `size` (see Table A3-2). + function automatic shortint unsigned num_bytes(size_t size); + return 1 << size; + endfunction + + /// An overly long address type. + /// It lets us define functions that work generically for shorter addresses. We rely on the + /// synthesizer to optimize the unused bits away. + typedef logic [127:0] largest_addr_t; + + /// Aligned address of burst (see A3-51). + function automatic largest_addr_t aligned_addr(largest_addr_t addr, size_t size); + return (addr >> size) << size; + endfunction + + /// Warp boundary of a `BURST_WRAP` transfer (see A3-51). + /// This is the lowest address accessed within a wrapping burst. + /// This address is aligned to the size and length of the burst. + /// The length of a `BURST_WRAP` has to be 2, 4, 8, or 16 transfers. + function automatic largest_addr_t wrap_boundary (largest_addr_t addr, size_t size, len_t len); + largest_addr_t wrap_addr; + + // pragma translate_off + `ifndef VERILATOR + assume (len == len_t'(4'b1) || len == len_t'(4'b11) || len == len_t'(4'b111) || + len == len_t'(4'b1111)) else + $error("AXI BURST_WRAP with not allowed len of: %0h", len); + `endif + // pragma translate_on + + // In A3-51 the wrap boundary is defined as: + // `Wrap_Boundary = (INT(Start_Address / (Number_Bytes × Burst_Length))) × + // (Number_Bytes × Burst_Length)` + // Whereas the aligned address is defined as: + // `Aligned_Address = (INT(Start_Address / Number_Bytes)) × Number_Bytes` + // This leads to the wrap boundary using the same calculation as the aligned address, difference + // being the additional dependency on the burst length. The addition in the case statement + // is equal to the multiplication with `Burst_Length` as a shift (used by `aligned_addr`) is + // equivalent with multiplication and division by a power of two, which conveniently are the + // only allowed values for `len` of a `BURST_WRAP`. + unique case (len) + 4'b1 : wrap_addr = (addr >> (unsigned'(size) + 1)) << (unsigned'(size) + 1); // multiply `Number_Bytes` by `2` + 4'b11 : wrap_addr = (addr >> (unsigned'(size) + 2)) << (unsigned'(size) + 2); // multiply `Number_Bytes` by `4` + 4'b111 : wrap_addr = (addr >> (unsigned'(size) + 3)) << (unsigned'(size) + 3); // multiply `Number_Bytes` by `8` + 4'b1111 : wrap_addr = (addr >> (unsigned'(size) + 4)) << (unsigned'(size) + 4); // multiply `Number_Bytes` by `16` + default : wrap_addr = '0; + endcase + return wrap_addr; + endfunction + + /// Address of beat (see A3-51). + function automatic largest_addr_t + beat_addr(largest_addr_t addr, size_t size, len_t len, burst_t burst, shortint unsigned i_beat); + largest_addr_t ret_addr = addr; + largest_addr_t wrp_bond = '0; + if (burst == BURST_WRAP) begin + // do not trigger the function if there is no wrapping burst, to prevent assumptions firing + wrp_bond = wrap_boundary(addr, size, len); + end + if (i_beat != 0 && burst != BURST_FIXED) begin + // From A3-51: + // For an INCR burst, and for a WRAP burst for which the address has not wrapped, this + // equation determines the address of any transfer after the first transfer in a burst: + // `Address_N = Aligned_Address + (N – 1) × Number_Bytes` (N counts from 1 to len!) + ret_addr = aligned_addr(addr, size) + i_beat * num_bytes(size); + // From A3-51: + // For a WRAP burst, if Address_N = Wrap_Boundary + (Number_Bytes × Burst_Length), then: + // * Use this equation for the current transfer: + // `Address_N = Wrap_Boundary` + // * Use this equation for any subsequent transfers: + // `Address_N = Start_Address + ((N – 1) × Number_Bytes) – (Number_Bytes × Burst_Length)` + // This means that the address calculation of a `BURST_WRAP` fundamentally works the same + // as for a `BURST_INC`, the difference is when the calculated address increments + // over the wrap threshold, the address wraps around by subtracting the accessed address + // space from the normal `BURST_INCR` address. The lower wrap boundary is equivalent to + // The wrap trigger condition minus the container size (`num_bytes(size) * (len + 1)`). + if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin + ret_addr = ret_addr - (num_bytes(size) * (len + 1)); + end + end + return ret_addr; + endfunction + + /// Index of lowest byte in beat (see A3-51). + function automatic shortint unsigned + beat_lower_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst, + shortint unsigned strobe_width, shortint unsigned i_beat); + largest_addr_t _addr = beat_addr(addr, size, len, burst, i_beat); + return _addr - (_addr / strobe_width) * strobe_width; + endfunction + + /// Index of highest byte in beat (see A3-51). + function automatic shortint unsigned + beat_upper_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst, + shortint unsigned strobe_width, shortint unsigned i_beat); + if (i_beat == 0) begin + return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width; + end else begin + return beat_lower_byte(addr, size, len, burst, strobe_width, i_beat) + num_bytes(size) - 1; + end + endfunction + + /// Is the bufferable bit set? + function automatic logic bufferable(cache_t cache); + return |(cache & CACHE_BUFFERABLE); + endfunction + + /// Is the modifiable bit set? + function automatic logic modifiable(cache_t cache); + return |(cache & CACHE_MODIFIABLE); + endfunction + + /// Memory Type. + typedef enum logic [3:0] { + DEVICE_NONBUFFERABLE, + DEVICE_BUFFERABLE, + NORMAL_NONCACHEABLE_NONBUFFERABLE, + NORMAL_NONCACHEABLE_BUFFERABLE, + WTHRU_NOALLOCATE, + WTHRU_RALLOCATE, + WTHRU_WALLOCATE, + WTHRU_RWALLOCATE, + WBACK_NOALLOCATE, + WBACK_RALLOCATE, + WBACK_WALLOCATE, + WBACK_RWALLOCATE + } mem_type_t; + + /// Create an `AR_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_arcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b1010; + WTHRU_RALLOCATE : return 4'b1110; + WTHRU_WALLOCATE : return 4'b1010; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b1011; + WBACK_RALLOCATE : return 4'b1111; + WBACK_WALLOCATE : return 4'b1011; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + /// Create an `AW_CACHE` field from a `mem_type_t` type. + function automatic logic [3:0] get_awcache(mem_type_t mtype); + unique case (mtype) + DEVICE_NONBUFFERABLE : return 4'b0000; + DEVICE_BUFFERABLE : return 4'b0001; + NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010; + NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011; + WTHRU_NOALLOCATE : return 4'b0110; + WTHRU_RALLOCATE : return 4'b0110; + WTHRU_WALLOCATE : return 4'b1110; + WTHRU_RWALLOCATE : return 4'b1110; + WBACK_NOALLOCATE : return 4'b0111; + WBACK_RALLOCATE : return 4'b0111; + WBACK_WALLOCATE : return 4'b1111; + WBACK_RWALLOCATE : return 4'b1111; + endcase // mtype + endfunction + + /// RESP precedence: DECERR > SLVERR > OKAY > EXOKAY. This is not defined in the AXI standard but + /// depends on the implementation. We consistently use the precedence above. Rationale: + /// - EXOKAY means an exclusive access was successful, whereas OKAY means it was not. Thus, if + /// OKAY and EXOKAY are to be merged, OKAY precedes because the exclusive access was not fully + /// successful. + /// - Both DECERR and SLVERR mean (part of) a transaction were unsuccessful, whereas OKAY means an + /// entire transaction was successful. Thus both DECERR and SLVERR precede OKAY. + /// - DECERR means (part of) a transactions could not be routed to a slave component, whereas + /// SLVERR means the transaction reached a slave component but lead to an error condition there. + /// Thus DECERR precedes SLVERR because DECERR happens earlier in the handling of a transaction. + function automatic resp_t resp_precedence(resp_t resp_a, resp_t resp_b); + unique case (resp_a) + RESP_OKAY: begin + // Any response except EXOKAY precedes OKAY. + if (resp_b == RESP_EXOKAY) begin + return resp_a; + end else begin + return resp_b; + end + end + RESP_EXOKAY: begin + // Any response precedes EXOKAY. + return resp_b; + end + RESP_SLVERR: begin + // Only DECERR precedes SLVERR. + if (resp_b == RESP_DECERR) begin + return resp_b; + end else begin + return resp_a; + end + end + RESP_DECERR: begin + // No response precedes DECERR. + return resp_a; + end + endcase + endfunction + + // ATOP[5:0] + /// - Sends a single data value with an address. + /// - The target swaps the value at the addressed location with the data value that is supplied in + /// the transaction. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICSWAP = 6'b110000; + /// - Sends two data values, the compare value and the swap value, to the addressed location. + /// The compare and swap values are of equal size. + /// - The data value at the addressed location is checked against the compare value: + /// - If the values match, the swap value is written to the addressed location. + /// - If the values do not match, the swap value is not written to the addressed location. + /// - The original data value at the addressed location is returned. + /// - Outbound data size is 2, 4, 8, 16, or 32 bytes. + /// - Inbound data size is half of the outbound data size because the outbound data contains both + /// compare and swap values, whereas the inbound data has only the original data value. + localparam ATOP_ATOMICCMP = 6'b110001; + // ATOP[5:4] + /// Perform no atomic operation. + localparam ATOP_NONE = 2'b00; + /// - Sends a single data value with an address and the atomic operation to be performed. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - A single response is given without data. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + localparam ATOP_ATOMICSTORE = 2'b01; + /// Sends a single data value with an address and the atomic operation to be performed. + /// - The original data value at the addressed location is returned. + /// - The target performs the operation using the sent data and value at the addressed location as + /// operands. + /// - The result is stored in the address location. + /// - Outbound data size is 1, 2, 4, or 8 bytes. + /// - Inbound data size is the same as the outbound data size. + localparam ATOP_ATOMICLOAD = 2'b10; + // ATOP[3] + /// For AtomicStore and AtomicLoad transactions `AWATOP[3]` indicates the endianness that is + /// required for the atomic operation. The value of `AWATOP[3]` applies to arithmetic operations + /// only and is ignored for bitwise logical operations. + /// When deasserted, this bit indicates that the operation is little-endian. + localparam ATOP_LITTLE_END = 1'b0; + /// When asserted, this bit indicates that the operation is big-endian. + localparam ATOP_BIG_END = 1'b1; + // ATOP[2:0] + /// The value in memory is added to the sent data and the result stored in memory. + localparam ATOP_ADD = 3'b000; + /// Every set bit in the sent data clears the corresponding bit of the data in memory. + localparam ATOP_CLR = 3'b001; + /// Bitwise exclusive OR of the sent data and value in memory. + localparam ATOP_EOR = 3'b010; + /// Every set bit in the sent data sets the corresponding bit of the data in memory. + localparam ATOP_SET = 3'b011; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMAX = 3'b100; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes signed data. + localparam ATOP_SMIN = 3'b101; + /// The value stored in memory is the maximum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMAX = 3'b110; + /// The value stored in memory is the minimum of the existing value and sent data. This operation + /// assumes unsigned data. + localparam ATOP_UMIN = 3'b111; + // ATOP[5] == 1'b1 indicated that an atomic transaction has a read response + // Ussage eg: if (req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin + localparam ATOP_R_RESP = 32'd5; + + // `xbar_latency_e` and `xbar_cfg_t` are documented in `doc/axi_xbar.md`. + /// Slice on Demux AW channel. + localparam logic [9:0] DemuxAw = (1 << 9); + /// Slice on Demux W channel. + localparam logic [9:0] DemuxW = (1 << 8); + /// Slice on Demux B channel. + localparam logic [9:0] DemuxB = (1 << 7); + /// Slice on Demux AR channel. + localparam logic [9:0] DemuxAr = (1 << 6); + /// Slice on Demux R channel. + localparam logic [9:0] DemuxR = (1 << 5); + /// Slice on Mux AW channel. + localparam logic [9:0] MuxAw = (1 << 4); + /// Slice on Mux W channel. + localparam logic [9:0] MuxW = (1 << 3); + /// Slice on Mux B channel. + localparam logic [9:0] MuxB = (1 << 2); + /// Slice on Mux AR channel. + localparam logic [9:0] MuxAr = (1 << 1); + /// Slice on Mux R channel. + localparam logic [9:0] MuxR = (1 << 0); + /// Latency configuration for `axi_xbar`. + typedef enum logic [9:0] { + NO_LATENCY = 10'b000_00_000_00, + CUT_SLV_AX = DemuxAw | DemuxAr, + CUT_MST_AX = MuxAw | MuxAr, + CUT_ALL_AX = DemuxAw | DemuxAr | MuxAw | MuxAr, + CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR, + CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR, + CUT_ALL_PORTS = 10'b111_11_111_11 + } xbar_latency_e; + + /// Configuration for `axi_xbar`. + typedef struct packed { + int unsigned NoSlvPorts; + int unsigned NoMstPorts; + int unsigned MaxMstTrans; + int unsigned MaxSlvTrans; + bit FallThrough; + xbar_latency_e LatencyMode; + int unsigned AxiIdWidthSlvPorts; + int unsigned AxiIdUsedSlvPorts; + bit UniqueIds; + int unsigned AxiAddrWidth; + int unsigned AxiDataWidth; + int unsigned NoAddrRules; + } xbar_cfg_t; + + /// Commonly used rule types for `axi_xbar` (64-bit addresses). + typedef struct packed { + int unsigned idx; + logic [63:0] start_addr; + logic [63:0] end_addr; + } xbar_rule_64_t; + + /// Commonly used rule types for `axi_xbar` (32-bit addresses). + typedef struct packed { + int unsigned idx; + logic [31:0] start_addr; + logic [31:0] end_addr; + } xbar_rule_32_t; +endpackage diff --git a/flow/designs/src/mempool_group/rtl/axi/typedef.svh b/flow/designs/src/mempool_group/rtl/axi/typedef.svh new file mode 100644 index 0000000000..a2a860e509 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/typedef.svh @@ -0,0 +1,211 @@ +// Copyright (c) 2019 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Authors: +// - Andreas Kurth +// - Florian Zaruba +// - Wolfgang Roenninger + +// Macros to define AXI and AXI-Lite Channel and Request/Response Structs + +`ifndef AXI_TYPEDEF_SVH_ +`define AXI_TYPEDEF_SVH_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// AXI4+ATOP Channel and Request/Response Structs +// +// Usage Example: +// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t) +// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t) +// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_user_t) +// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t) +// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t) +// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t) +// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t) +`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \ + typedef struct packed { \ + id_t id; \ + addr_t addr; \ + axi_pkg::len_t len; \ + axi_pkg::size_t size; \ + axi_pkg::burst_t burst; \ + logic lock; \ + axi_pkg::cache_t cache; \ + axi_pkg::prot_t prot; \ + axi_pkg::qos_t qos; \ + axi_pkg::region_t region; \ + axi_pkg::atop_t atop; \ + user_t user; \ + } aw_chan_t; +`define AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) \ + typedef struct packed { \ + data_t data; \ + strb_t strb; \ + logic last; \ + user_t user; \ + } w_chan_t; +`define AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) \ + typedef struct packed { \ + id_t id; \ + axi_pkg::resp_t resp; \ + user_t user; \ + } b_chan_t; +`define AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) \ + typedef struct packed { \ + id_t id; \ + addr_t addr; \ + axi_pkg::len_t len; \ + axi_pkg::size_t size; \ + axi_pkg::burst_t burst; \ + logic lock; \ + axi_pkg::cache_t cache; \ + axi_pkg::prot_t prot; \ + axi_pkg::qos_t qos; \ + axi_pkg::region_t region; \ + user_t user; \ + } ar_chan_t; +`define AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) \ + typedef struct packed { \ + id_t id; \ + data_t data; \ + axi_pkg::resp_t resp; \ + logic last; \ + user_t user; \ + } r_chan_t; +`define AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t) \ + typedef struct packed { \ + aw_chan_t aw; \ + logic aw_valid; \ + w_chan_t w; \ + logic w_valid; \ + logic b_ready; \ + ar_chan_t ar; \ + logic ar_valid; \ + logic r_ready; \ + } req_t; +`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) \ + typedef struct packed { \ + logic aw_ready; \ + logic ar_ready; \ + logic w_ready; \ + logic b_valid; \ + b_chan_t b; \ + logic r_valid; \ + r_chan_t r; \ + } resp_t; +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// All AXI4+ATOP Channels and Request/Response Structs in One Macro +// +// This can be used whenever the user is not interested in "precise" control of the naming of the +// individual channels. +// +// Usage Example: +// `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t) +// +// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`, +// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs. +`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \ + `AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \ + `AXI_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t, __user_t) \ + `AXI_TYPEDEF_B_CHAN_T(__name``_b_chan_t, __id_t, __user_t) \ + `AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \ + `AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \ + `AXI_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ + `AXI_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// AXI4-Lite Channel and Request/Response Structs +// +// Usage Example: +// `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_t, axi_lite_addr_t) +// `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_w_t, axi_lite_data_t, axi_lite_strb_t) +// `AXI_LITE_TYPEDEF_B_CHAN_T(axi_lite_b_t) +// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t) +// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t) +// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t) +// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t) +`define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \ + typedef struct packed { \ + addr_t addr; \ + axi_pkg::prot_t prot; \ + } aw_chan_lite_t; +`define AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_lite_t, data_t, strb_t) \ + typedef struct packed { \ + data_t data; \ + strb_t strb; \ + } w_chan_lite_t; +`define AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_lite_t) \ + typedef struct packed { \ + axi_pkg::resp_t resp; \ + } b_chan_lite_t; +`define AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_lite_t, addr_t) \ + typedef struct packed { \ + addr_t addr; \ + axi_pkg::prot_t prot; \ + } ar_chan_lite_t; +`define AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_lite_t, data_t) \ + typedef struct packed { \ + data_t data; \ + axi_pkg::resp_t resp; \ + } r_chan_lite_t; +`define AXI_LITE_TYPEDEF_REQ_T(req_lite_t, aw_chan_lite_t, w_chan_lite_t, ar_chan_lite_t) \ + typedef struct packed { \ + aw_chan_lite_t aw; \ + logic aw_valid; \ + w_chan_lite_t w; \ + logic w_valid; \ + logic b_ready; \ + ar_chan_lite_t ar; \ + logic ar_valid; \ + logic r_ready; \ + } req_lite_t; +`define AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) \ + typedef struct packed { \ + logic aw_ready; \ + logic w_ready; \ + b_chan_lite_t b; \ + logic b_valid; \ + logic ar_ready; \ + r_chan_lite_t r; \ + logic r_valid; \ + } resp_lite_t; +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// All AXI4-Lite Channels and Request/Response Structs in One Macro +// +// This can be used whenever the user is not interested in "precise" control of the naming of the +// individual channels. +// +// Usage Example: +// `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) +// +// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as +// `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and +// `axi_lite_r_chan_t` channel structs. +`define AXI_LITE_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \ + `AXI_LITE_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t) \ + `AXI_LITE_TYPEDEF_W_CHAN_T(__name``_w_chan_t, __data_t, __strb_t) \ + `AXI_LITE_TYPEDEF_B_CHAN_T(__name``_b_chan_t) \ + `AXI_LITE_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t) \ + `AXI_LITE_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t) \ + `AXI_LITE_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \ + `AXI_LITE_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t) +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +`endif diff --git a/flow/designs/src/mempool_group/rtl/axi_hier_interco.sv b/flow/designs/src/mempool_group/rtl/axi_hier_interco.sv new file mode 100644 index 0000000000..7c696efa52 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi_hier_interco.sv @@ -0,0 +1,240 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// +// Implement a hierarchical AXI interconnect. Below shows one level of the interconnect. This module +// recursively instantiates itself and creates a tree of interconnects, each with `NumPortsPerMux` +// slave ports. +// +// TODO: Add a configurable cache per level +// +// AXI Mux ID Width +// Converter +// |‾╲ +// +-------->| ╲ +// | + +-------+ +// +-------->| M | | | +// | U |------->| > |---------> +// | X | | | +// | + +-------+ +// +-------->| ╱ +// |_╱ +// Internal +// Slave type type Master type + +module axi_hier_interco #( + parameter int unsigned NumSlvPorts = 0, + parameter int unsigned NumPortsPerMux = NumSlvPorts, + parameter int unsigned EnableCache = 1'b0, + parameter int unsigned AddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned SlvIdWidth = 0, + parameter int unsigned MstIdWidth = 0, + parameter int unsigned UserWidth = 0, + parameter type slv_req_t = logic, + parameter type slv_resp_t = logic, + parameter type mst_req_t = logic, + parameter type mst_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic test_i, + input slv_req_t [NumSlvPorts-1:0] slv_req_i, + output slv_resp_t [NumSlvPorts-1:0] slv_resp_o, + output mst_req_t mst_req_o, + input mst_resp_t mst_resp_i +); + + //////////////// + // Typedefs // + //////////////// + + localparam int unsigned IntIdWidth = SlvIdWidth + $clog2(NumSlvPorts); + + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [DataWidth/8-1:0] strb_t; + typedef logic [SlvIdWidth-1:0] slv_id_t; + typedef logic [MstIdWidth-1:0] mst_id_t; + typedef logic [IntIdWidth-1:0] int_id_t; + typedef logic [UserWidth-1:0] user_t; + + `include "axi/typedef.svh" + // Common AXI types + `AXI_TYPEDEF_W_CHAN_T(w_t, data_t, strb_t, user_t); + // Slave AXI types + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_t, addr_t, slv_id_t, user_t); + `AXI_TYPEDEF_B_CHAN_T(slv_b_t, slv_id_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_t, addr_t, slv_id_t, user_t); + `AXI_TYPEDEF_R_CHAN_T(slv_r_t, data_t, slv_id_t, user_t); + // Intermediate AXI types + `AXI_TYPEDEF_AW_CHAN_T(int_aw_t, addr_t, int_id_t, user_t); + `AXI_TYPEDEF_B_CHAN_T(int_b_t, int_id_t, user_t); + `AXI_TYPEDEF_AR_CHAN_T(int_ar_t, addr_t, int_id_t, user_t); + `AXI_TYPEDEF_R_CHAN_T(int_r_t, data_t, int_id_t, user_t); + `AXI_TYPEDEF_REQ_T(int_req_t, int_aw_t, w_t, int_ar_t); + `AXI_TYPEDEF_RESP_T(int_resp_t, int_b_t, int_r_t ); + + /////////////// + // Interco // + /////////////// + + // Recursive module to implement multiple hierarchy levels at once + + if (NumSlvPorts <= NumPortsPerMux) begin : gen_axi_level_final + + // Intermediate AXI channel + int_req_t int_req; + int_resp_t int_resp; + + axi_mux #( + // AXI parameter and channel types + .SlvAxiIDWidth (SlvIdWidth ), // AXI ID width, slave ports + .slv_aw_chan_t (slv_aw_t ), // AW Channel Type, slave ports + .mst_aw_chan_t (int_aw_t ), // AW Channel Type, master port + .w_chan_t (w_t ), // W Channel Type, all ports + .slv_b_chan_t (slv_b_t ), // B Channel Type, slave ports + .mst_b_chan_t (int_b_t ), // B Channel Type, master port + .slv_ar_chan_t (slv_ar_t ), // AR Channel Type, slave ports + .mst_ar_chan_t (int_ar_t ), // AR Channel Type, master port + .slv_r_chan_t (slv_r_t ), // R Channel Type, slave ports + .mst_r_chan_t (int_r_t ), // R Channel Type, master port + .slv_req_t (slv_req_t ), // Slave port request type + .slv_resp_t (slv_resp_t ), // Slave port response type + .mst_req_t (int_req_t ), // Master ports request type + .mst_resp_t (int_resp_t ), // Master ports response type + .NoSlvPorts (NumSlvPorts), // Number of slave ports + // Maximum number of outstanding transactions per write + .MaxWTrans (8 ), + // If enabled, this multiplexer is purely combinatorial + .FallThrough (1'b0 ), + // add spill register on write master ports, adds a cycle latency on write channels + .SpillAw (1'b1 ), + .SpillW (1'b1 ), + .SpillB (1'b1 ), + // add spill register on read master ports, adds a cycle latency on read channels + .SpillAr (1'b1 ), + .SpillR (1'b1 ) + ) i_axi_mux ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (test_i ), + .slv_reqs_i (slv_req_i ), + .slv_resps_o (slv_resp_o), + .mst_req_o (int_req ), + .mst_resp_i (int_resp ) + ); + + axi_id_remap #( + .AxiSlvPortIdWidth (IntIdWidth), + .AxiSlvPortMaxUniqIds (IntIdWidth), + .AxiMaxTxnsPerId (4 ), + .AxiMstPortIdWidth (MstIdWidth), + .slv_req_t (int_req_t ), + .slv_resp_t (int_resp_t), + .mst_req_t (mst_req_t ), + .mst_resp_t (mst_resp_t) + ) i_axi_id_remap ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_req_i (int_req ), + .slv_resp_o (int_resp ), + .mst_req_o (mst_req_o ), + .mst_resp_i (mst_resp_i) + ); + + // TODO: Implement cache + if (EnableCache[0]) + $error("[axi_hier_interco] `EnableCache` not yet supported."); + // Check all the AXI widths + if ($bits(slv_req_i[0].aw.addr) != AddrWidth) + $error("[axi_hier_interco] `slv_req_i.aw.addr` does not match AddrWidth."); + if ($bits(slv_req_i[0].w.data) != DataWidth) + $error("[axi_hier_interco] `slv_req_i.w.data` does not match DataWidth."); + if ($bits(slv_req_i[0].aw.id) != SlvIdWidth) + $error("[axi_hier_interco] `slv_req_i.aw.id` does not match SlvIdWidth."); + if ($bits(slv_req_i[0].aw.user) != UserWidth) + $error("[axi_hier_interco] `slv_req_i.aw.user` does not match UserWidth."); + + if ($bits(mst_req_o.aw.addr) != AddrWidth) + $error("[axi_hier_interco] `mst_req_o.aw.addr` does not match AddrWidth."); + if ($bits(mst_req_o.w.data) != DataWidth) + $error("[axi_hier_interco] `mst_req_o.w.data` does not match DataWidth."); + if ($bits(mst_req_o.aw.id) != MstIdWidth) + $error("[axi_hier_interco] `mst_req_o.aw.id` does not match MstIdWidth."); + if ($bits(mst_req_o.aw.user) != UserWidth) + $error("[axi_hier_interco] `mst_req_o.aw.user` does not match UserWidth."); + + if ($bits(int_req.aw.addr) != AddrWidth) + $error("[axi_hier_interco] `int_req.aw.addr` does not match AddrWidth."); + if ($bits(int_req.w.data) != DataWidth) + $error("[axi_hier_interco] `int_req.w.data` does not match DataWidth."); + if ($bits(int_req.aw.id) != IntIdWidth) + $error("[axi_hier_interco] `int_req.aw.id` does not match IntIdWidth."); + if ($bits(int_req.aw.user) != UserWidth) + $error("[axi_hier_interco] `int_req.aw.user` does not match UserWidth."); + end else begin : gen_axi_level_recursive + // More than one level missing. --> Recursively call this module + // This level will contain `NumMuxes` interconnects + localparam int unsigned NumMuxes = NumSlvPorts / NumPortsPerMux; + + slv_req_t [NumMuxes-1:0] int_req; + slv_resp_t [NumMuxes-1:0] int_resp; + + for (genvar i = 0; i < NumMuxes; i++) begin : gen_axi_intercos + axi_hier_interco #( + .NumSlvPorts (NumPortsPerMux), + .NumPortsPerMux (NumPortsPerMux), + .EnableCache (EnableCache[0]), + .AddrWidth (AddrWidth ), + .DataWidth (DataWidth ), + .SlvIdWidth (SlvIdWidth ), + .MstIdWidth (SlvIdWidth ), + .UserWidth (UserWidth ), + .slv_req_t (slv_req_t ), + .slv_resp_t (slv_resp_t ), + .mst_req_t (slv_req_t ), + .mst_resp_t (slv_resp_t ) + ) i_axi_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (test_i ), + .slv_req_i (slv_req_i[i*NumPortsPerMux +: NumPortsPerMux] ), + .slv_resp_o (slv_resp_o[i*NumPortsPerMux +: NumPortsPerMux]), + .mst_req_o (int_req[i] ), + .mst_resp_i (int_resp[i] ) + ); + end + + axi_hier_interco #( + .NumSlvPorts (NumMuxes ), + .NumPortsPerMux (NumPortsPerMux), + .EnableCache (EnableCache>>1), + .AddrWidth (AddrWidth ), + .DataWidth (DataWidth ), + .SlvIdWidth (SlvIdWidth ), + .MstIdWidth (MstIdWidth ), + .UserWidth (UserWidth ), + .slv_req_t (slv_req_t ), + .slv_resp_t (slv_resp_t ), + .mst_req_t (mst_req_t ), + .mst_resp_t (mst_resp_t ) + ) i_axi_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (test_i ), + .slv_req_i (int_req ), + .slv_resp_o (int_resp ), + .mst_req_o (mst_req_o ), + .mst_resp_i (mst_resp_i) + ); + + if (NumMuxes * NumPortsPerMux != NumSlvPorts) + $error("[axi_hier_interco] `NumSlvPorts mod NumPortsPerMux` must be 0."); + end + + if (NumPortsPerMux <= 1) + $error("[axi_hier_interco] `NumPortsPerMux` must be bigger than 1."); + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv new file mode 100644 index 0000000000..7bdd0edeb1 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv @@ -0,0 +1,73 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 28.05.2019 +// Description: Package with important constants and lookup tables for TCDM +// interconnect. + +package tcdm_interconnect_pkg; + +typedef enum logic [1:0] { LIC, BFLY2, BFLY4, CLOS } topo_e; + +//////////////////////////////////////////////////////////////////////// +// LUT params for Clos net with configs: 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n, +// to be indexed with [config_idx][$clog2(BankingFact)][$clog2(NumBanks)] +// generated with MATLAB script gen_clos_params.m +//////////////////////////////////////////////////////////////////////// +localparam logic [3:1][4:0][12:2][15:0] ClosNLut = {16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2}; +localparam logic [3:1][4:0][12:2][15:0] ClosMLut = {16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4, + 16'd128,16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1, + 16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2,16'd1,16'd1}; +localparam logic [3:1][4:0][12:2][15:0] ClosRLut = {16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2,16'd2, + 16'd64,16'd64,16'd32,16'd32,16'd16,16'd16,16'd8,16'd8,16'd4,16'd4,16'd2}; + + + +endpackage : tcdm_interconnect_pkg diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv new file mode 100644 index 0000000000..8c6eaae88d --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv @@ -0,0 +1,268 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Michael Schaffner , ETH Zurich +// Matheus Cavalcante , ETH Zurich + +// Date: 16.01.2020 + +// Description: Interconnect with support to variable target latencies with different +// network topologies. Currently supported are: full crossbar and radix-2/4 butterflies. +// Note that only the full crossbar allows NumIn/NumOut configurations that are not +// aligned to a power of 2. + +module variable_latency_interconnect import tcdm_interconnect_pkg::topo_e; #( + // Global parameters + parameter int unsigned NumIn = 32, // Number of Initiators. Must be aligned with a power of 2 for butterflies. + parameter int unsigned NumOut = 64, // Number of Targets. Must be aligned with a power of 2 for butterflies. + parameter int unsigned AddrWidth = 32, // Address Width on the Initiator Side + parameter int unsigned DataWidth = 32, // Data Word Width + parameter int unsigned BeWidth = DataWidth/8, // Byte Strobe Width + parameter int unsigned AddrMemWidth = 12, // Number of Address bits per Target + parameter bit AxiVldRdy = 1'b1, // Valid/ready signaling + // Spill registers + // A bit set at position i indicates a spill register at the i-th crossbar layer. + // The layers are counted starting at 0 from the initiator, for the requests, and from the target, for the responses. + parameter logic [63:0] SpillRegisterReq = 64'h0, + parameter logic [63:0] SpillRegisterResp = 64'h0, + parameter bit FallThroughRegister = 1'b0, // Insert a fall-through register, if missing a spill register in that stage + // Determines the width of the byte offset in a memory word. Normally this can be left at the default value, + // but sometimes it needs to be overridden (e.g., when metadata is supplied to the memory via the wdata signal). + parameter int unsigned ByteOffWidth = $clog2(DataWidth-1)-3, + // Topology can be: LIC, BFLY2, BFLY4, CLOS + parameter topo_e Topology = tcdm_interconnect_pkg::LIC, + // Dependant parameters. DO NOT CHANGE! + parameter int unsigned NumInLog2 = NumIn == 1 ? 1 : $clog2(NumIn) +) ( + input logic clk_i, + input logic rst_ni, + // Initiator side + input logic [NumIn-1:0] req_valid_i, // Request valid + output logic [NumIn-1:0] req_ready_o, // Request ready + input logic [NumIn-1:0][AddrWidth-1:0] req_tgt_addr_i, // Target address + input logic [NumIn-1:0] req_wen_i, // Write enable + input logic [NumIn-1:0][DataWidth-1:0] req_wdata_i, // Write data + input logic [NumIn-1:0][BeWidth-1:0] req_be_i, // Byte enable + output logic [NumIn-1:0] resp_valid_o, // Response valid + input logic [NumIn-1:0] resp_ready_i, // Response ready + output logic [NumIn-1:0][DataWidth-1:0] resp_rdata_o, // Data response + // Target side + output logic [NumOut-1:0] req_valid_o, // Request valid + input logic [NumOut-1:0] req_ready_i, // Request ready + output logic [NumOut-1:0][NumInLog2-1:0] req_ini_addr_o, // Initiator address + output logic [NumOut-1:0][AddrMemWidth-1:0] req_tgt_addr_o, // Target address + output logic [NumOut-1:0] req_wen_o, // Write enable + output logic [NumOut-1:0][DataWidth-1:0] req_wdata_o, // Write data + output logic [NumOut-1:0][BeWidth-1:0] req_be_o, // Byte enable + input logic [NumOut-1:0] resp_valid_i, // Response valid + output logic [NumOut-1:0] resp_ready_o, // Response ready + input logic [NumOut-1:0][NumInLog2-1:0] resp_ini_addr_i, // Initiator address + input logic [NumOut-1:0][DataWidth-1:0] resp_rdata_i // Data response +); + + /****************** + * Parameters * + ******************/ + + // localparams and aggregation of address, wen and payload data + + localparam int unsigned NumOutLog2 = $clog2(NumOut); + localparam int unsigned IniAggDataWidth = 1 + BeWidth + AddrMemWidth + DataWidth; + + /************* + * Signals * + *************/ + + logic [NumIn-1:0][IniAggDataWidth-1:0] data_agg_in; + logic [NumOut-1:0][IniAggDataWidth-1:0] data_agg_out; + logic [NumIn-1:0][cf_math_pkg::idx_width(NumOut)-1:0] tgt_sel; + + for (genvar j = 0; unsigned'(j) < NumIn; j++) begin : gen_inputs + // Extract target index + if (NumIn == 1) begin + assign tgt_sel[j] = '0; + end else begin + if (NumOut == 1) begin + assign tgt_sel[j] = 0; + end else begin + assign tgt_sel[j] = req_tgt_addr_i[j][ByteOffWidth +: NumOutLog2]; + end + end + + // Aggregate data to be routed to targets + assign data_agg_in[j] = {req_wen_i[j], req_be_i[j], req_tgt_addr_i[j][ByteOffWidth + NumOutLog2 +: AddrMemWidth], req_wdata_i[j]}; + end + + // Disaggregate data + for (genvar k = 0; unsigned'(k) < NumOut; k++) begin : gen_outputs + assign {req_wen_o[k], req_be_o[k], req_tgt_addr_o[k], req_wdata_o[k]} = data_agg_out[k]; + end + + /**************** + * Networks * + ****************/ + + // Direct connection + if (NumIn < 2 && NumOut < 2) begin : gen_con + assign req_valid_o = req_valid_i; + assign req_ready_o = req_ready_i; + assign req_ini_addr_o = '0; + assign data_agg_out = data_agg_in; + assign resp_valid_o = resp_valid_i; + assign resp_ready_o = resp_ready_i; + assign resp_rdata_o = resp_rdata_i; + // Tuned logarithmic interconnect architecture, based on rr_arb_tree primitives + end else if (Topology == tcdm_interconnect_pkg::LIC) begin : gen_lic + full_duplex_xbar #( + .NumIn (NumIn ), + .NumOut (NumOut ), + .ReqDataWidth (IniAggDataWidth ), + .RespDataWidth (DataWidth ), + .AxiVldRdy (AxiVldRdy ), + .SpillRegisterReq (SpillRegisterReq[0] ), + .SpillRegisterResp (SpillRegisterResp[0]), + .FallThroughRegister(FallThroughRegister ) + ) i_xbar ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Extern priority flags + .req_rr_i ('0 ), + .resp_rr_i ('0 ), + // Initiator side + .req_valid_i (req_valid_i ), + .req_ready_o (req_ready_o ), + .req_tgt_addr_i (tgt_sel ), + .req_wdata_i (data_agg_in ), + .resp_valid_o (resp_valid_o ), + .resp_rdata_o (resp_rdata_o ), + .resp_ready_i (resp_ready_i ), + // Target side + .req_valid_o (req_valid_o ), + .req_ini_addr_o (req_ini_addr_o ), + .req_ready_i (req_ready_i ), + .req_wdata_o (data_agg_out ), + .resp_valid_i (resp_valid_i ), + .resp_ready_o (resp_ready_o ), + .resp_ini_addr_i(resp_ini_addr_i), + .resp_rdata_i (resp_rdata_i ) + ); + end + + // Butterfly network (radix 2 or 4) + else if (Topology == tcdm_interconnect_pkg::BFLY2 || Topology == tcdm_interconnect_pkg::BFLY4) begin: gen_bfly + localparam int unsigned Radix = 2**Topology; + + logic [$clog2(NumOut)-1:0] req_rr ; + logic [$clog2(NumOut)-1:0] resp_rr; + + // Although round robin arbitration works in some cases, it + // it is quite likely that it interferes with linear access patterns + // hence we use a relatively long LFSR + block cipher here to create a + // pseudo random sequence with good randomness. the block cipher layers + // are used to break shift register linearity. + /* + // NOTE(matheusd): This is a long path. We are removing it for now. + + lfsr #( + .LfsrWidth (64 ), + .OutWidth ($clog2(NumOut)), + .CipherLayers(3 ), + .CipherReg (1'b1 ) + ) lfsr_req_i ( + .clk_i (clk_i ), + .rst_ni(rst_ni ), + .en_i (|(ini_req_ready & ini_req_valid)), + .out_o (req_rr ) + ); + + lfsr #( + .LfsrWidth (64 ), + .OutWidth ($clog2(NumOut)), + .CipherLayers(3 ), + .CipherReg (1'b1 ) + ) lfsr_resp_i ( + .clk_i (clk_i ), + .rst_ni(rst_ni ), + .en_i (|(tgt_resp_valid & tgt_resp_ready)), + .out_o (resp_rr ) + );*/ + + assign req_rr = '0; + assign resp_rr = '0; + + variable_latency_bfly_net #( + .NumIn (NumIn ), + .NumOut (NumOut ), + .DataWidth (IniAggDataWidth ), + .Radix (Radix ), + .ExtPrio (1'b0 ), + .SpillRegister (SpillRegisterReq ), + .AxiVldRdy (AxiVldRdy ), + .FallThroughRegister(FallThroughRegister ) + ) i_req_bfly_net ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Extern priority flags + .rr_i (req_rr ), + // Initiator side + .valid_i (req_valid_i ), + .ready_o (req_ready_o ), + .tgt_addr_i(tgt_sel ), + .wdata_i (data_agg_in ), + // Target side + .valid_o (req_valid_o ), + .ini_addr_o(req_ini_addr_o ), + .ready_i (req_ready_i ), + .wdata_o (data_agg_out ) + ); + + variable_latency_bfly_net #( + .NumIn (NumOut ), + .NumOut (NumIn ), + .DataWidth (DataWidth ), + .Radix (Radix ), + .ExtPrio (1'b0 ), + .SpillRegister (SpillRegisterResp ), + .AxiVldRdy (AxiVldRdy ), + .FallThroughRegister(FallThroughRegister ) + ) i_resp_bfly_net ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Extern priority flags + .rr_i (resp_rr ), + // Target side + .valid_i (resp_valid_i ), + .ready_o (resp_ready_o ), + .tgt_addr_i(resp_ini_addr_i), + .wdata_i (resp_rdata_i ), + // Initiator side + .valid_o (resp_valid_o ), + .ready_i (resp_ready_i ), + .ini_addr_o(/* Unused */ ), + .wdata_o (resp_rdata_o ) + ); + end + + // Unknown network + else begin: gen_unknown + $fatal(1, "[variable_latency_interconnect] Unknown TCDM configuration %d.", Topology); + end + + /****************** + * Assertions * + ******************/ + + if (NumOut != 1 && AddrMemWidth + NumOutLog2 > AddrWidth) + $fatal(1, "[variable_latency_interconnect] Address is not wide enough to accommodate the requested TCDM configuration."); + + if (Topology != tcdm_interconnect_pkg::LIC && NumOut < NumIn) + $fatal(1, "[variable_latency_interconnect] NumOut < NumIn is not supported with the chosen TCDM configuration."); + +endmodule : variable_latency_interconnect diff --git a/flow/designs/src/mempool_group/rtl/common_cells/assertions.svh b/flow/designs/src/mempool_group/rtl/common_cells/assertions.svh new file mode 100644 index 0000000000..b6b4b73782 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/assertions.svh @@ -0,0 +1,201 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macros and helper code for using assertions. +// - Provides default clk and rst options to simplify code +// - Provides boiler plate template for common assertions + +`ifndef PRIM_ASSERT_SV +`define PRIM_ASSERT_SV + +`ifdef UVM + // report assertion error with UVM if compiled + package assert_rpt_pkg; + import uvm_pkg::*; + `include "uvm_macros.svh" + function void assert_rpt(string msg); + `uvm_error("ASSERT FAILED", msg) + endfunction + endpackage +`endif + +/////////////////// +// Helper macros // +/////////////////// + +// local helper macro to reduce code clutter. undefined at the end of this file +`ifndef VERILATOR +`ifndef SYNTHESIS +`ifndef XSIM +`define INC_ASSERT +`endif +`endif +`endif + +// Converts an arbitrary block of code into a Verilog string +`define PRIM_STRINGIFY(__x) `"__x`" + +// ASSERT_RPT is available to change the reporting mechanism when an assert fails +`define ASSERT_RPT(__name) \ +`ifdef UVM \ + assert_rpt_pkg::assert_rpt($sformatf("[%m] %s (%s:%0d)", \ + __name, `__FILE__, `__LINE__)); \ +`else \ + $error("[ASSERT FAILED] [%m] %s (%s:%0d)", __name, `__FILE__, `__LINE__); \ +`endif + +/////////////////////////////////////// +// Simple assertion and cover macros // +/////////////////////////////////////// + +// Default clk and reset signals used by assertion macros below. +`define ASSERT_DEFAULT_CLK clk_i +`define ASSERT_DEFAULT_RST !rst_ni + +// Immediate assertion +// Note that immediate assertions are sensitive to simulation glitches. +`define ASSERT_I(__name, __prop) \ +`ifdef INC_ASSERT \ + __name: assert (__prop) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ +`endif + +// Assertion in initial block. Can be used for things like parameter checking. +`define ASSERT_INIT(__name, __prop) \ +`ifdef INC_ASSERT \ + initial begin \ + __name: assert (__prop) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ + end \ +`endif + +// Assertion in final block. Can be used for things like queues being empty +// at end of sim, all credits returned at end of sim, state machines in idle +// at end of sim. +`define ASSERT_FINAL(__name, __prop) \ +`ifdef INC_ASSERT \ + final begin \ + __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ + end \ +`endif + +// Assert a concurrent property directly. +// It can be called as a module (or interface) body item. +`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ +`endif +// Note: Above we use (__rst !== '0) in the disable iff statements instead of +// (__rst == '1). This properly disables the assertion in cases when reset is X at +// the beginning of a simulation. For that case, (reset == '1) does not disable the +// assertion. + +// Assert a concurrent property NEVER happens +`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ +`endif + +// Assert that signal has a known value (each bit is either '0' or '1') after reset. +// It can be called as a module (or interface) body item. +`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + `ASSERT(__name, !$isunknown(__sig), __clk, __rst) \ +`endif + +// Cover a concurrent property +`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); \ +`endif + +////////////////////////////// +// Complex assertion macros // +////////////////////////////// + +// Assert that signal is an active-high pulse with pulse length of 1 clock cycle +`define ASSERT_PULSE(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + `ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) \ +`endif + +// Assert that a property is true only when an enable signal is set. It can be called as a module +// (or interface) body item. +`define ASSERT_IF(__name, __prop, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + `ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) \ +`endif + +// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is +// set. It can be called as a module (or interface) body item. +`define ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + `ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ + `ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) \ +`endif + +/////////////////////// +// Assumption macros // +/////////////////////// + +// Assume a concurrent property +`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef INC_ASSERT \ + __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ +`endif + +// Assume an immediate property +`define ASSUME_I(__name, __prop) \ +`ifdef INC_ASSERT \ + __name: assume (__prop) \ + else begin \ + `ASSERT_RPT(`PRIM_STRINGIFY(__name)) \ + end \ +`endif + +////////////////////////////////// +// For formal verification only // +////////////////////////////////// + +// Note that the existing set of ASSERT macros specified above shall be used for FPV, +// thereby ensuring that the assertions are evaluated during DV simulations as well. + +// ASSUME_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `ASSUME(__name, __prop, __clk, __rst) \ +`endif + +// ASSUME_I_FPV +// Assume a concurrent property during formal verification only. +`define ASSUME_I_FPV(__name, __prop) \ +`ifdef FPV_ON \ + `ASSUME_I(__name, __prop) \ +`endif + +// COVER_FPV +// Cover a concurrent property during formal verification +`define COVER_FPV(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `COVER(__name, __prop, __clk, __rst) \ +`endif + +`endif // PRIM_ASSERT_SV diff --git a/flow/designs/src/mempool_group/rtl/common_cells/registers.svh b/flow/designs/src/mempool_group/rtl/common_cells/registers.svh new file mode 100644 index 0000000000..b64f31a013 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/registers.svh @@ -0,0 +1,221 @@ +// Copyright 2018, 2021 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Stefan Mach +// Description: Common register defines for RTL designs + +`ifndef COMMON_CELLS_REGISTERS_SVH_ +`define COMMON_CELLS_REGISTERS_SVH_ + +// Abridged Summary of available FF macros: +// `FF: asynchronous active-low reset +// `FFAR: asynchronous active-high reset +// `FFARN: [deprecated] asynchronous active-low reset +// `FFSR: synchronous active-high reset +// `FFSRN: synchronous active-low reset +// `FFNR: without reset +// `FFL: load-enable and asynchronous active-low reset +// `FFLAR: load-enable and asynchronous active-high reset +// `FFLARN: [deprecated] load-enable and asynchronous active-low reset +// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear +// `FFLSR: load-enable and synchronous active-high reset +// `FFLSRN: load-enable and synchronous active-low reset +// `FFLNR: load-enable without reset + +`ifdef VERILATOR +`define NO_SYNOPSYS_FF 1 +`endif + +`define REG_DFLT_CLK clk_i +`define REG_DFLT_RST rst_ni + +// Flip-Flop with asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// (__clk: clock input) +// (__arst_n: asynchronous reset, active-low) +`define FF(__q, __d, __reset_value, __clk = `REG_DFLT_CLK, __arst_n = `REG_DFLT_RST) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset, active-high +`define FFAR(__q, __d, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// DEPRECATED - use `FF instead +// Flip-Flop with asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset, active-low +`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \ + `FF(__q, __d, __reset_value, __clk, __arst_n) + +// Flip-Flop with synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input, active-high +`define FFSR(__q, __d, __reset_value, __clk, __reset_clk) \ + `ifndef NO_SYNOPSYS_FF \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : (__d); \ + end + +// Flip-Flop with synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input, active-low +`define FFSRN(__q, __d, __reset_value, __clk, __reset_n_clk) \ + `ifndef NO_SYNOPSYS_FF \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : (__d); \ + end + +// Always-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __clk: clock input +`define FFNR(__q, __d, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__d); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// (__clk: clock input) +// (__arst_n: asynchronous reset, active-low) +`define FFL(__q, __d, __load, __reset_value, __clk = `REG_DFLT_CLK, __arst_n = `REG_DFLT_RST) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset, active-high +`define FFLAR(__q, __d, __load, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// DEPRECATED - use `FFL instead +// Flip-Flop with load-enable and asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset, active-low +`define FFLARN(__q, __d, __load, __reset_value, __clk, __arst_n) \ + `FFL(__q, __d, __load, __reset_value, __clk, __arst_n) + +// Flip-Flop with load-enable and synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input, active-high +`define FFLSR(__q, __d, __load, __reset_value, __clk, __reset_clk) \ + `ifndef NO_SYNOPSYS_FF \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input, active-low +`define FFLSRN(__q, __d, __load, __reset_value, __clk, __reset_n_clk) \ + `ifndef NO_SYNOPSYS_FF \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset and synchronous clear +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clear: assign reset value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset, active-low +`define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \ + `ifndef NO_SYNOPSYS_FF \ + /``* synopsys sync_set_reset `"__clear`" *``/ \ + `endif \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__clear) ? (__reset_value) : (__load) ? (__d) : (__q); \ + end \ + end + +// Load-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clk: clock input +`define FFLNR(__q, __d, __load, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__load) ? (__d) : (__q); \ + end + +`endif diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/cf_math_pkg.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/cf_math_pkg.sv new file mode 100644 index 0000000000..9f35a44e98 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/cf_math_pkg.sv @@ -0,0 +1,61 @@ +// Copyright 2016 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// cf_math_pkg: Constant Function Implementations of Mathematical Functions for HDL Elaboration +/// +/// This package contains a collection of mathematical functions that are commonly used when defining +/// the value of constants in HDL code. These functions are implemented as Verilog constants +/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (§ 10.3.5) is a +/// function whose value can be evaluated at compile time or during elaboration. A constant function +/// must be called with arguments that are constants. +package cf_math_pkg; + + /// Ceiled Division of Two Natural Numbers + /// + /// Returns the quotient of two natural numbers, rounded towards plus infinity. + function automatic integer ceil_div (input longint dividend, input longint divisor); + automatic longint remainder; + + // pragma translate_off + `ifndef VERILATOR + if (dividend < 0) begin + $fatal(1, "Dividend %0d is not a natural number!", dividend); + end + + if (divisor < 0) begin + $fatal(1, "Divisor %0d is not a natural number!", divisor); + end + + if (divisor == 0) begin + $fatal(1, "Division by zero!"); + end + `endif + // pragma translate_on + + remainder = dividend; + for (ceil_div = 0; remainder > 0; ceil_div++) begin + remainder = remainder - divisor; + end + endfunction + + /// Index width required to be able to represent up to `num_idx` indices as a binary + /// encoded signal. + /// Ensures that the minimum width if an index signal is `1`, regardless of parametrization. + /// + /// Sample usage in type definition: + /// As parameter: + /// `parameter type idx_t = logic[cf_math_pkg::idx_width(NumIdx)-1:0]` + /// As typedef: + /// `typedef logic [cf_math_pkg::idx_width(NumIdx)-1:0] idx_t` + function automatic integer unsigned idx_width (input integer unsigned num_idx); + return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; + endfunction + +endpackage diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/fifo_v2.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/fifo_v2.sv new file mode 100644 index 0000000000..9c87ed9692 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/fifo_v2.sv @@ -0,0 +1,79 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +module fifo_v2 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter int unsigned ALM_EMPTY_TH = 1, // almost empty threshold (when to assert alm_empty_o) + parameter int unsigned ALM_FULL_TH = 1, // almost full threshold (when to assert alm_full_o) + parameter type dtype = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic alm_full_o, // FIFO fillstate >= the specified threshold + output logic alm_empty_o, // FIFO fillstate <= the specified threshold + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + + logic [ADDR_DEPTH-1:0] usage; + + // generate threshold parameters + if (DEPTH == 0) begin + assign alm_full_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0 + assign alm_empty_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0 + end else begin + assign alm_full_o = (usage >= ALM_FULL_TH[ADDR_DEPTH-1:0]); + assign alm_empty_o = (usage <= ALM_EMPTY_TH[ADDR_DEPTH-1:0]); + end + + fifo_v3 #( + .FALL_THROUGH ( FALL_THROUGH ), + .DATA_WIDTH ( DATA_WIDTH ), + .DEPTH ( DEPTH ), + .dtype ( dtype ) + ) i_fifo_v3 ( + .clk_i, + .rst_ni, + .flush_i, + .testmode_i, + .full_o, + .empty_o, + .usage_o (usage), + .data_i, + .push_i, + .data_o, + .pop_i + ); + + // pragma translate_off + `ifndef VERILATOR + initial begin + assert (ALM_FULL_TH <= DEPTH) else $error("ALM_FULL_TH can't be larger than the DEPTH."); + assert (ALM_EMPTY_TH <= DEPTH) else $error("ALM_EMPTY_TH can't be larger than the DEPTH."); + end + `endif + // pragma translate_on + +endmodule // fifo_v2 diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/find_first_one.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/find_first_one.sv new file mode 100644 index 0000000000..ee3ba20f70 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/find_first_one.sv @@ -0,0 +1,83 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Deprecated, use lzc unit instead. + +/// A leading-one finder / leading zero counter. +/// Set FLIP to 0 for find_first_one => first_one_o is the index of the first one (from the LSB) +/// Set FLIP to 1 for leading zero counter => first_one_o is the number of leading zeroes (from the MSB) +module find_first_one #( + /// The width of the input vector. + parameter int WIDTH = -1, + parameter int FLIP = 0 +)( + input logic [WIDTH-1:0] in_i, + output logic [$clog2(WIDTH)-1:0] first_one_o, + output logic no_ones_o +); + + localparam int NUM_LEVELS = $clog2(WIDTH); + + // pragma translate_off + initial begin + assert(WIDTH >= 0); + end + // pragma translate_on + + logic [WIDTH-1:0][NUM_LEVELS-1:0] index_lut; + logic [2**NUM_LEVELS-1:0] sel_nodes; + logic [2**NUM_LEVELS-1:0][NUM_LEVELS-1:0] index_nodes; + + logic [WIDTH-1:0] in_tmp; + + for (genvar i = 0; i < WIDTH; i++) begin + assign in_tmp[i] = FLIP ? in_i[WIDTH-1-i] : in_i[i]; + end + + for (genvar j = 0; j < WIDTH; j++) begin + assign index_lut[j] = j; + end + + for (genvar level = 0; level < NUM_LEVELS; level++) begin + + if (level < NUM_LEVELS-1) begin + for (genvar l = 0; l < 2**level; l++) begin + assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1]; + assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? + index_nodes[2**(level+1)-1+l*2] : index_nodes[2**(level+1)-1+l*2+1]; + end + end + + if (level == NUM_LEVELS-1) begin + for (genvar k = 0; k < 2**level; k++) begin + // if two successive indices are still in the vector... + if (k * 2 < WIDTH-1) begin + assign sel_nodes[2**level-1+k] = in_tmp[k*2] | in_tmp[k*2+1]; + assign index_nodes[2**level-1+k] = (in_tmp[k*2] == 1'b1) ? index_lut[k*2] : index_lut[k*2+1]; + end + // if only the first index is still in the vector... + if (k * 2 == WIDTH-1) begin + assign sel_nodes[2**level-1+k] = in_tmp[k*2]; + assign index_nodes[2**level-1+k] = index_lut[k*2]; + end + // if index is out of range + if (k * 2 > WIDTH-1) begin + assign sel_nodes[2**level-1+k] = 1'b0; + assign index_nodes[2**level-1+k] = '0; + end + end + end + end + + assign first_one_o = NUM_LEVELS > 0 ? index_nodes[0] : '0; + assign no_ones_o = NUM_LEVELS > 0 ? ~sel_nodes[0] : '1; + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/fall_through_register.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/fall_through_register.sv new file mode 100644 index 0000000000..fcbbe31dbc --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/fall_through_register.sv @@ -0,0 +1,58 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Fall-through register with a simple stream-like ready/valid handshake. +// This register does not cut combinatorial paths on any signals: in case the module at its output +// is ready to accept data within the same clock cycle, they are forwarded. Use this module to get a +// 'default ready' behavior towards the input. +module fall_through_register #( + parameter type T = logic // Vivado requires a default value for type parameters. +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous active-low reset + input logic clr_i, // Synchronous clear + input logic testmode_i, // Test mode to bypass clock gating + // Input port + input logic valid_i, + output logic ready_o, + input T data_i, + // Output port + output logic valid_o, + input logic ready_i, + output T data_o +); + + logic fifo_empty, + fifo_full; + + fifo_v2 #( + .FALL_THROUGH (1'b1), + .DATA_WIDTH ($size(T)), + .DEPTH (1), + .dtype (T) + ) i_fifo ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (clr_i), + .testmode_i (testmode_i), + .full_o (fifo_full), + .empty_o (fifo_empty), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i (data_i), + .push_i (valid_i & ~fifo_full), + .data_o (data_o), + .pop_i (ready_i & ~fifo_empty) + ); + + assign ready_o = ~fifo_full; + assign valid_o = ~fifo_empty; + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/fifo_v3.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/fifo_v3.sv new file mode 100644 index 0000000000..e417a3e7b0 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/fifo_v3.sv @@ -0,0 +1,154 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Florian Zaruba + +module fifo_v3 #( + parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode + parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic + parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32 + parameter type dtype = logic [DATA_WIDTH-1:0], + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic flush_i, // flush the queue + input logic testmode_i, // test_mode to bypass clock gating + // status flags + output logic full_o, // queue is full + output logic empty_o, // queue is empty + output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer + // as long as the queue is not full we can push new data + input dtype data_i, // data to push into the queue + input logic push_i, // data is valid and can be pushed to the queue + // as long as the queue is not empty we can pop new elements + output dtype data_o, // output data + input logic pop_i // pop head from queue +); + // local parameter + // FIFO depth - handle the case of pass-through, synthesizer will do constant propagation + localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1; + // clock gating control + logic gate_clock; + // pointer to the read and write section of the queue + logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q; + // keep a counter to keep track of the current queue status + // this integer will be truncated by the synthesis tool + logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q; + // actual memory + dtype [FifoDepth - 1:0] mem_n, mem_q; + + assign usage_o = status_cnt_q[ADDR_DEPTH-1:0]; + + if (DEPTH == 0) begin : gen_pass_through + assign empty_o = ~push_i; + assign full_o = ~pop_i; + end else begin : gen_fifo + assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]); + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + // status flags + + // read and write queue logic + always_comb begin : read_write_comb + // default assignment + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + status_cnt_n = status_cnt_q; + data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q]; + mem_n = mem_q; + gate_clock = 1'b1; + + // push a new element to the queue + if (push_i && ~full_o) begin + // push the data onto the queue + mem_n[write_pointer_q] = data_i; + // un-gate the clock, we want to write something + gate_clock = 1'b0; + // increment the write counter + if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1) + write_pointer_n = '0; + else + write_pointer_n = write_pointer_q + 1; + // increment the overall counter + status_cnt_n = status_cnt_q + 1; + end + + if (pop_i && ~empty_o) begin + // read from the queue is a default assignment + // but increment the read pointer... + if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1) + read_pointer_n = '0; + else + read_pointer_n = read_pointer_q + 1; + // ... and decrement the overall count + status_cnt_n = status_cnt_q - 1; + end + + // keep the count pointer stable if we push and pop at the same time + if (push_i && pop_i && ~full_o && ~empty_o) + status_cnt_n = status_cnt_q; + + // FIFO is in pass through mode -> do not change the pointers + if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin + data_o = data_i; + if (pop_i) begin + status_cnt_n = status_cnt_q; + read_pointer_n = read_pointer_q; + write_pointer_n = write_pointer_q; + end + end + end + + // sequential process + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + if (flush_i) begin + read_pointer_q <= '0; + write_pointer_q <= '0; + status_cnt_q <= '0; + end else begin + read_pointer_q <= read_pointer_n; + write_pointer_q <= write_pointer_n; + status_cnt_q <= status_cnt_n; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + mem_q <= '0; + end else if (!gate_clock) begin + mem_q <= mem_n; + end + end + +// pragma translate_off +`ifndef VERILATOR + initial begin + assert (DEPTH > 0) else $error("DEPTH must be greater than 0."); + end + + full_write : assert property( + @(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i)) + else $fatal (1, "Trying to push new data although the FIFO is full."); + + empty_read : assert property( + @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i)) + else $fatal (1, "Trying to pop data although the FIFO is empty."); +`endif +// pragma translate_on + +endmodule // fifo_v3 diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/isochronous_spill_register.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/isochronous_spill_register.sv new file mode 100644 index 0000000000..35c9d6d728 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/isochronous_spill_register.sv @@ -0,0 +1,111 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Florian Zaruba + +`include "common_cells/registers.svh" + +/// A register with handshakes that completely cuts any combinatorial paths +/// between the input and output in isochronous clock domains. +/// +/// > Definition of isochronous: In telecommunication, an isochronous signal is a signal +/// > in which the time interval separating any two significant instants is equal to the +/// > unit interval or a multiple of the unit interval. +/// +/// The source and destination clock domains must be derived from the same clock +/// but can vary in frequency by a constant factor (e.g., double the frequency). +/// +/// The module is basically a two deep dual-clock fifo with read and write pointers +/// in different clock domains. As we know the static timing relationship between the +/// clock domains we can rely on static timing analysis (STA) to get the sampling windows +/// right and therefore don't need any synchronization. +/// +/// # Restrictions +/// +/// Source and destination clock domains must be an integer multiple of each other and +/// all timing-paths need to be covered by STA. For example a recommended SDC would be: +/// +/// `create_generated_clock dst_clk_i -name dst_clk -source src_clk_i -divide_by 2 +/// +/// There are _no_ restrictions on which clock domain should be the faster, any integer +/// ratio will work. +module isochronous_spill_register #( + /// Data type of spill register. + parameter type T = logic, + /// Make this spill register transparent. + parameter bit Bypass = 1'b0 +) ( + /// Clock of source clock domain. + input logic src_clk_i, + /// Active low async reset in source domain. + input logic src_rst_ni, + /// Source input data is valid. + input logic src_valid_i, + /// Source is ready to accept. + output logic src_ready_o, + /// Source input data. + input T src_data_i, + /// Clock of destination clock domain. + input logic dst_clk_i, + /// Active low async reset in destination domain. + input logic dst_rst_ni, + /// Destination output data is valid. + output logic dst_valid_o, + /// Destination is ready to accept. + input logic dst_ready_i, + /// Destination output data. + output T dst_data_o +); + // Don't generate the spill register. + if (Bypass) begin : gen_bypass + assign dst_valid_o = src_valid_i; + assign src_ready_o = dst_ready_i; + assign dst_data_o = src_data_i; + // Generate the spill register + end else begin : gen_isochronous_spill_register + /// Read/write pointer are one bit wider than necessary. + /// We implicitly capture the full and empty state with the second bit: + /// If all but the topmost bit of `rd_pointer_q` and `wr_pointer_q` agree, the + /// FIFO is in a critical state. If the topmost bit is equal, the FIFO is + /// empty, otherwise it is full. + logic [1:0] rd_pointer_q, wr_pointer_q; + // Advance write pointer if we pushed a new item into the FIFO. (Source clock domain) + `FFLARN(wr_pointer_q, wr_pointer_q+1, (src_valid_i && src_ready_o), '0, src_clk_i, src_rst_ni) + // Advance read pointer if downstream consumed an item. (Destination clock domain) + `FFLARN(rd_pointer_q, rd_pointer_q+1, (dst_valid_o && dst_ready_i), '0, dst_clk_i, dst_rst_ni) + + T [1:0] mem_d, mem_q; + `FFLNR(mem_q, mem_d, (src_valid_i && src_ready_o), src_clk_i) + always_comb begin + mem_d = mem_q; + mem_d[wr_pointer_q[0]] = src_data_i; + end + + assign src_ready_o = (rd_pointer_q ^ wr_pointer_q) != 2'b10; + + assign dst_valid_o = (rd_pointer_q ^ wr_pointer_q) != '0; + assign dst_data_o = mem_q[rd_pointer_q[0]]; + end + + // pragma translate_off + // stability guarantees + `ifndef VERILATOR + assert property (@(posedge src_clk_i) disable iff (src_rst_ni) + (src_valid_i && !src_ready_o |=> $stable(src_valid_i))) else $error("src_valid_i is unstable"); + assert property (@(posedge src_clk_i) disable iff (src_rst_ni) + (src_valid_i && !src_ready_o |=> $stable(src_data_i))) else $error("src_data_i is unstable"); + assert property (@(posedge dst_clk_i) disable iff (dst_rst_ni) + (dst_valid_o && !dst_ready_i |=> $stable(dst_valid_o))) else $error("dst_valid_o is unstable"); + assert property (@(posedge dst_clk_i) disable iff (dst_rst_ni) + (dst_valid_o && !dst_ready_i |=> $stable(dst_data_o))) else $error("dst_data_o is unstable"); + `endif + // pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/lzc.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/lzc.sv new file mode 100644 index 0000000000..424eb2ef62 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/lzc.sv @@ -0,0 +1,112 @@ +// Copyright (c) 2018 - 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +/// A trailing zero counter / leading zero counter. +/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) +/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) +/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains +/// the maximum number of zeros - 1. For example: +/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) +/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) +/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) +/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). +/// This speeds up simulation significantly. +module lzc #( + /// The width of the input vector. + parameter int unsigned WIDTH = 2, + /// Mode selection: 0 -> trailing zero, 1 -> leading zero + parameter bit MODE = 1'b0, + /// Dependent parameter. Do **not** change! + /// + /// Width of the output signal with the zero count. + parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) +) ( + /// Input vector to be counted. + input logic [WIDTH-1:0] in_i, + /// Count of the leading / trailing zeros. + output logic [CNT_WIDTH-1:0] cnt_o, + /// Counter is empty: Asserted if all bits in in_i are zero. + output logic empty_o +); + + if (WIDTH == 1) begin : gen_degenerate_lzc + + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + + end else begin : gen_lzc + + localparam int unsigned NumLevels = $clog2(WIDTH); + + // pragma translate_off + initial begin + assert(WIDTH > 0) else $fatal(1, "input must be at least one bit wide"); + end + // pragma translate_on + + logic [WIDTH-1:0][NumLevels-1:0] index_lut; + logic [2**NumLevels-1:0] sel_nodes; + logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes; + + logic [WIDTH-1:0] in_tmp; + + // reverse vector if required + always_comb begin : flip_vector + for (int unsigned i = 0; i < WIDTH; i++) begin + in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; + end + end + + for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut + assign index_lut[j] = (NumLevels)'(unsigned'(j)); + end + + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : g_levels + if (unsigned'(level) == NumLevels - 1) begin : g_last_level + for (genvar k = 0; k < 2 ** level; k++) begin : g_level + // if two successive indices are still in the vector... + if (unsigned'(k) * 2 < WIDTH - 1) begin : g_reduce + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2] | in_tmp[k * 2 + 1]; + assign index_nodes[2 ** level - 1 + k] = (in_tmp[k * 2] == 1'b1) + ? index_lut[k * 2] : + index_lut[k * 2 + 1]; + end + // if only the first index is still in the vector... + if (unsigned'(k) * 2 == WIDTH - 1) begin : g_base + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2]; + assign index_nodes[2 ** level - 1 + k] = index_lut[k * 2]; + end + // if index is out of range + if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range + assign sel_nodes[2 ** level - 1 + k] = 1'b0; + assign index_nodes[2 ** level - 1 + k] = '0; + end + end + end else begin : g_not_last_level + for (genvar l = 0; l < 2 ** level; l++) begin : g_level + assign sel_nodes[2 ** level - 1 + l] = + sel_nodes[2 ** (level + 1) - 1 + l * 2] | sel_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + assign index_nodes[2 ** level - 1 + l] = (sel_nodes[2 ** (level + 1) - 1 + l * 2] == 1'b1) + ? index_nodes[2 ** (level + 1) - 1 + l * 2] : + index_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + end + end + end + + assign cnt_o = NumLevels > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)) {1'b0}}; + assign empty_o = NumLevels > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); + + end : gen_lzc + +endmodule : lzc diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/onehot_to_bin.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/onehot_to_bin.sv new file mode 100644 index 0000000000..0c33f084b9 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/onehot_to_bin.sv @@ -0,0 +1,38 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Franceco Conti + +module onehot_to_bin #( + parameter int unsigned ONEHOT_WIDTH = 16, + // Do Not Change + parameter int unsigned BIN_WIDTH = ONEHOT_WIDTH == 1 ? 1 : $clog2(ONEHOT_WIDTH) +) ( + input logic [ONEHOT_WIDTH-1:0] onehot, + output logic [BIN_WIDTH-1:0] bin +); + + for (genvar j = 0; j < BIN_WIDTH; j++) begin : jl + logic [ONEHOT_WIDTH-1:0] tmp_mask; + for (genvar i = 0; i < ONEHOT_WIDTH; i++) begin : il + logic [BIN_WIDTH-1:0] tmp_i; + assign tmp_i = i; + assign tmp_mask[i] = tmp_i[j]; + end + assign bin[j] = |(tmp_mask & onehot); + end + +// pragma translate_off +`ifndef VERILATOR + assert final ($onehot0(onehot)) else + $fatal(1, "[onehot_to_bin] More than two bit set in the one-hot signal"); +`endif +// pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/rr_arb_tree.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/rr_arb_tree.sv new file mode 100644 index 0000000000..90301c822c --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/rr_arb_tree.sv @@ -0,0 +1,348 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Wolfgang Roenninger , ETH Zurich +// Date: 02.04.2019 +// Description: logarithmic arbitration tree with round robin arbitration scheme. + +/// The rr_arb_tree employs non-starving round robin-arbitration - i.e., the priorities +/// rotate each cycle. +/// +/// ## Fair vs. unfair Arbitration +/// +/// This refers to fair throughput distribution when not all inputs have active requests. +/// This module has an internal state `rr_q` which defines the highest priority input. (When +/// `ExtPrio` is `1'b1` this state is provided from the outside.) The arbitration tree will +/// choose the input with the same index as currently defined by the state if it has an active +/// request. Otherwise a *random* other active input is selected. The parameter `FairArb` is used +/// to distinguish between two methods of calculating the next state. +/// * `1'b0`: The next state is calculated by advancing the current state by one. This leads to the +/// state being calculated without the context of the active request. Leading to an +/// unfair throughput distribution if not all inputs have active requests. +/// * `1'b1`: The next state jumps to the next unserved request with higher index. +/// This is achieved by using two trailing-zero-counters (`lzc`). The upper has the masked +/// `req_i` signal with all indices which will have a higher priority in the next state. +/// The trailing zero count defines the input index with the next highest priority after +/// the current one is served. When the upper is empty the lower `lzc` provides the +/// wrapped index if there are outstanding requests with lower or same priority. +/// The implication of throughput fairness on the module timing are: +/// * The trailing zero counter (`lzc`) has a loglog relation of input to output timing. This means +/// that in this module the input to register path scales with Log(Log(`NumIn`)). +/// * The `rr_arb_tree` data multiplexing scales with Log(`NumIn`). This means that the input to output +/// timing path of this module also scales scales with Log(`NumIn`). +/// This implies that in this module the input to output path is always longer than the input to +/// register path. As the output data usually also terminates in a register the parameter `FairArb` +/// only has implications on the area. When it is `1'b0` a static plus one adder is instantiated. +/// If it is `1'b1` two `lzc`, a masking logic stage and a two input multiplexer are instantiated. +/// However these are small in respect of the data multiplexers needed, as the width of the `req_i` +/// signal is usually less as than `DataWidth`. +module rr_arb_tree #( + /// Number of inputs to be arbitrated. + parameter int unsigned NumIn = 64, + /// Data width of the payload in bits. Not needed if `DataType` is overwritten. + parameter int unsigned DataWidth = 32, + /// Data type of the payload, can be overwritten with custom type. Only use of `DataWidth`. + parameter type DataType = logic [DataWidth-1:0], + /// The `ExtPrio` option allows to override the internal round robin counter via the + /// `rr_i` signal. This can be useful in case multiple arbiters need to have + /// rotating priorities that are operating in lock-step. If static priority arbitration + /// is needed, just connect `rr_i` to '0. + /// + /// Set to 1'b1 to enable. + parameter bit ExtPrio = 1'b0, + /// If `AxiVldRdy` is set, the req/gnt signals are compliant with the AXI style vld/rdy + /// handshake. Namely, upstream vld (req) must not depend on rdy (gnt), as it can be deasserted + /// again even though vld is asserted. Enabling `AxiVldRdy` leads to a reduction of arbiter + /// delay and area. + /// + /// Set to `1'b1` to treat req/gnt as vld/rdy. + parameter bit AxiVldRdy = 1'b0, + /// The `LockIn` option prevents the arbiter from changing the arbitration + /// decision when the arbiter is disabled. I.e., the index of the first request + /// that wins the arbitration will be locked in case the destination is not + /// able to grant the request in the same cycle. + /// + /// Set to `1'b1` to enable. + parameter bit LockIn = 1'b0, + /// When set, ensures that throughput gets distributed evenly between all inputs. + /// + /// Set to `1'b0` to disable. + parameter bit FairArb = 1'b1, + /// Dependent parameter, do **not** overwrite. + /// Width of the arbitration priority signal and the arbitrated index. + parameter int unsigned IdxWidth = (NumIn > 32'd1) ? unsigned'($clog2(NumIn)) : 32'd1, + /// Dependent parameter, do **not** overwrite. + /// Type for defining the arbitration priority and arbitrated index signal. + parameter type idx_t = logic [IdxWidth-1:0] +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Clears the arbiter state. Only used if `ExtPrio` is `1'b0` or `LockIn` is `1'b1`. + input logic flush_i, + /// External round-robin priority. Only used if `ExtPrio` is `1'b1.` + input idx_t rr_i, + /// Input requests arbitration. + input logic [NumIn-1:0] req_i, + /* verilator lint_off UNOPTFLAT */ + /// Input request is granted. + output logic [NumIn-1:0] gnt_o, + /* verilator lint_on UNOPTFLAT */ + /// Input data for arbitration. + input DataType [NumIn-1:0] data_i, + /// Output request is valid. + output logic req_o, + /// Output request is granted. + input logic gnt_i, + /// Output data. + output DataType data_o, + /// Index from which input the data came from. + output idx_t idx_o +); + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + // Default SVA reset + default disable iff (!rst_ni || flush_i); + `endif + `endif + // pragma translate_on + + // just pass through in this corner case + if (NumIn == unsigned'(1)) begin : gen_pass_through + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[0]; + assign idx_o = '0; + // non-degenerate cases + end else begin : gen_arbiter + localparam int unsigned NumLevels = unsigned'($clog2(NumIn)); + + /* verilator lint_off UNOPTFLAT */ + idx_t [2**NumLevels-2:0] index_nodes; // used to propagate the indices + DataType [2**NumLevels-2:0] data_nodes; // used to propagate the data + logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters + logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave + /* lint_off */ + idx_t rr_q; + logic [NumIn-1:0] req_d; + + // the final arbitration decision can be taken from the root of the tree + assign req_o = req_nodes[0]; + assign data_o = data_nodes[0]; + assign idx_o = index_nodes[0]; + + if (ExtPrio) begin : gen_ext_rr + assign rr_q = rr_i; + assign req_d = req_i; + end else begin : gen_int_rr + idx_t rr_d; + + // lock arbiter decision in case we got at least one req and no acknowledge + if (LockIn) begin : gen_lock + logic lock_d, lock_q; + logic [NumIn-1:0] req_q; + + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q) ? req_q : req_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) begin + lock_q <= '0; + end else begin + if (flush_i) begin + lock_q <= '0; + end else begin + lock_q <= lock_d; + end + end + end + + // pragma translate_off + `ifndef VERILATOR + lock: assert property( + @(posedge clk_i) LockIn |-> req_o && + (!gnt_i && !flush_i) |=> idx_o == $past(idx_o)) else + $fatal (1, "Lock implies same arbiter decision in next cycle if output is not \ + ready."); + + logic [NumIn-1:0] req_tmp; + assign req_tmp = req_q & req_i; + lock_req: assume property( + @(posedge clk_i) LockIn |-> lock_d |=> req_tmp == req_q) else + $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is \ + enabled."); + `endif + // pragma translate_on + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) begin + req_q <= '0; + end else begin + if (flush_i) begin + req_q <= '0; + end else begin + req_q <= req_d; + end + end + end + end else begin : gen_no_lock + assign req_d = req_i; + end + + if (FairArb) begin : gen_fair_arb + logic [NumIn-1:0] upper_mask, lower_mask; + idx_t upper_idx, lower_idx, next_idx; + logic upper_empty, lower_empty; + + for (genvar i = 0; i < NumIn; i++) begin : gen_mask + assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0; + assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0; + end + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_upper ( + .in_i ( upper_mask ), + .cnt_o ( upper_idx ), + .empty_o ( upper_empty ) + ); + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_lower ( + .in_i ( lower_mask ), + .cnt_o ( lower_idx ), + .empty_o ( /*unused*/ ) + ); + + assign next_idx = upper_empty ? lower_idx : upper_idx; + assign rr_d = (gnt_i && req_o) ? next_idx : rr_q; + + end else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o) ? ((rr_q == idx_t'(NumIn-1)) ? '0 : rr_q + 1'b1) : rr_q; + end + + // this holds the highest priority + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) begin + rr_q <= '0; + end else begin + if (flush_i) begin + rr_q <= '0; + end else begin + rr_q <= rr_d; + end + end + end + end + + assign gnt_nodes[0] = gnt_i; + + // arbiter tree + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : gen_levels + for (genvar l = 0; l < 2**level; l++) begin : gen_level + // local select signal + logic sel; + // index calcs + localparam int unsigned Idx0 = 2**level-1+l;// current node + localparam int unsigned Idx1 = 2**(level+1)-1+l*2; + ////////////////////////////////////////////////////////////// + // uppermost level where data is fed in from the inputs + if (unsigned'(level) == NumLevels-1) begin : gen_first_level + // if two successive indices are still in the vector... + if (unsigned'(l) * 2 < NumIn-1) begin : gen_reduce + assign req_nodes[Idx0] = req_d[l*2] | req_d[l*2+1]; + + // arbitration: round robin + assign sel = ~req_d[l*2] | req_d[l*2+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = idx_t'(sel); + assign data_nodes[Idx0] = (sel) ? data_i[l*2+1] : data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]) & ~sel; + assign gnt_o[l*2+1] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2+1]) & sel; + end + // if only the first index is still in the vector... + if (unsigned'(l) * 2 == NumIn-1) begin : gen_first + assign req_nodes[Idx0] = req_d[l*2]; + assign index_nodes[Idx0] = '0;// always zero in this case + assign data_nodes[Idx0] = data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]); + end + // if index is out of range, fill up with zeros (will get pruned) + if (unsigned'(l) * 2 > NumIn-1) begin : gen_out_of_range + assign req_nodes[Idx0] = 1'b0; + assign index_nodes[Idx0] = idx_t'('0); + assign data_nodes[Idx0] = DataType'('0); + end + ////////////////////////////////////////////////////////////// + // general case for other levels within the tree + end else begin : gen_other_levels + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1+1]; + + // arbitration: round robin + assign sel = ~req_nodes[Idx1] | req_nodes[Idx1+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = (sel) ? + idx_t'({1'b1, index_nodes[Idx1+1][NumLevels-unsigned'(level)-2:0]}) : + idx_t'({1'b0, index_nodes[Idx1][NumLevels-unsigned'(level)-2:0]}); + + assign data_nodes[Idx0] = (sel) ? data_nodes[Idx1+1] : data_nodes[Idx1]; + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + assign gnt_nodes[Idx1+1] = gnt_nodes[Idx0] & sel; + end + ////////////////////////////////////////////////////////////// + end + end + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + initial begin : p_assert + assert(NumIn) + else $fatal(1, "Input must be at least one element wide."); + assert(!(LockIn && ExtPrio)) + else $fatal(1,"Cannot use LockIn feature together with external ExtPrio."); + end + + hot_one : assert property( + @(posedge clk_i) $onehot0(gnt_o)) + else $fatal (1, "Grant signal must be hot1 or zero."); + + gnt0 : assert property( + @(posedge clk_i) |gnt_o |-> gnt_i) + else $fatal (1, "Grant out implies grant in."); + + gnt1 : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> |gnt_o) + else $fatal (1, "Req out and grant in implies grant out."); + + gnt_idx : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> gnt_o[idx_o]) + else $fatal (1, "Idx_o / gnt_o do not match."); + + req0 : assert property( + @(posedge clk_i) |req_i |-> req_o) + else $fatal (1, "Req in implies req out."); + + req1 : assert property( + @(posedge clk_i) req_o |-> |req_i) + else $fatal (1, "Req out implies req in."); + `endif + `endif + // pragma translate_on + end + +endmodule : rr_arb_tree diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register.sv new file mode 100644 index 0000000000..80ff37f149 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register.sv @@ -0,0 +1,46 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki + + +/// Wrapper around the flushable spill register to maintain back-ward +/// compatibility. +module spill_register #( + parameter type T = logic, + parameter bit Bypass = 1'b0 // make this spill register transparent +) ( + input logic clk_i , + input logic rst_ni , + input logic valid_i , + output logic ready_o , + input T data_i , + output logic valid_o , + input logic ready_i , + output T data_o +); + + spill_register_flushable #( + .T(T), + .Bypass(Bypass) + ) spill_register_flushable_i ( + .clk_i, + .rst_ni, + .valid_i, + .flush_i(1'b0), + .ready_o, + .data_i, + .valid_o, + .ready_i, + .data_o + ); + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register_flushable.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register_flushable.sv new file mode 100644 index 0000000000..c03ad274de --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/spill_register_flushable.sv @@ -0,0 +1,105 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Fabian Schuiki + + +/// A register with handshakes that completely cuts any combinational paths +/// between the input and output. This spill register can be flushed. +module spill_register_flushable #( + parameter type T = logic, + parameter bit Bypass = 1'b0 // make this spill register transparent +) ( + input logic clk_i , + input logic rst_ni , + input logic valid_i , + input logic flush_i , + output logic ready_o , + input T data_i , + output logic valid_o , + input logic ready_i , + output T data_o +); + + if (Bypass) begin : gen_bypass + assign valid_o = valid_i; + assign ready_o = ready_i; + assign data_o = data_i; + end else begin : gen_spill_reg + // The A register. + T a_data_q; + logic a_full_q; + logic a_fill, a_drain; + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_data + if (!rst_ni) + a_data_q <= '0; + else if (a_fill) + a_data_q <= data_i; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_full + if (!rst_ni) + a_full_q <= 0; + else if (a_fill || a_drain) + a_full_q <= a_fill; + end + + // The B register. + T b_data_q; + logic b_full_q; + logic b_fill, b_drain; + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_data + if (!rst_ni) + b_data_q <= '0; + else if (b_fill) + b_data_q <= a_data_q; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_full + if (!rst_ni) + b_full_q <= 0; + else if (b_fill || b_drain) + b_full_q <= b_fill; + end + + // Fill the A register when the A or B register is empty. Drain the A register + // whenever it is full and being filled, or if a flush is requested. + assign a_fill = valid_i && ready_o && (!flush_i); + assign a_drain = (a_full_q && !b_full_q) || flush_i; + + // Fill the B register whenever the A register is drained, but the downstream + // circuit is not ready. Drain the B register whenever it is full and the + // downstream circuit is ready, or if a flush is requested. + assign b_fill = a_drain && (!ready_i) && (!flush_i); + assign b_drain = (b_full_q && ready_i) || flush_i; + + // We can accept input as long as register B is not full. + // Note: flush_i and valid_i must not be high at the same time, + // otherwise an invalid handshake may occur + assign ready_o = !a_full_q || !b_full_q; + + // The unit provides output as long as one of the registers is filled. + assign valid_o = a_full_q | b_full_q; + + // We empty the spill register before the slice register. + assign data_o = b_full_q ? b_data_q : a_data_q; + + // pragma translate_off + `ifndef VERILATOR + flush_valid : assert property ( + @(posedge clk_i) disable iff (~rst_ni) (flush_i |-> ~valid_i)) else + $warning("Trying to flush and feed the spill register simultaneously. You will lose data!"); + `endif + // pragma translate_on + end +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter.sv new file mode 100644 index 0000000000..c8ca2a8769 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter.sv @@ -0,0 +1,49 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is round-robin with "look ahead", see the `rrarbiter` for details. + +module stream_arbiter #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + stream_arbiter_flushable #( + .DATA_T (DATA_T), + .N_INP (N_INP), + .ARBITER (ARBITER) + ) i_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i (1'b0), + .inp_data_i (inp_data_i), + .inp_valid_i (inp_valid_i), + .inp_ready_o (inp_ready_o), + .oup_data_o (oup_data_o), + .oup_valid_o (oup_valid_o), + .oup_ready_i (oup_ready_i) + ); + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter_flushable.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter_flushable.sv new file mode 100644 index 0000000000..32946e6859 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_arbiter_flushable.sv @@ -0,0 +1,82 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Stream arbiter: Arbitrates a parametrizable number of input streams (i.e., valid-ready +// handshaking with dependency rules as in AXI4) to a single output stream. Once `oup_valid_o` is +// asserted, `oup_data_o` remains invariant until the output handshake has occurred. The +// arbitration scheme is fair round-robin tree, see `rr_arb_tree` for details. + +module stream_arbiter_flushable #( + parameter type DATA_T = logic, // Vivado requires a default value for type parameters. + parameter integer N_INP = -1, // Synopsys DC requires a default value for parameters. + parameter ARBITER = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + + input DATA_T [N_INP-1:0] inp_data_i, + input logic [N_INP-1:0] inp_valid_i, + output logic [N_INP-1:0] inp_ready_o, + + output DATA_T oup_data_o, + output logic oup_valid_o, + input logic oup_ready_i +); + + if (ARBITER == "rr") begin : gen_rr_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b0), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else if (ARBITER == "prio") begin : gen_prio_arb + rr_arb_tree #( + .NumIn (N_INP), + .DataType (DATA_T), + .ExtPrio (1'b1), + .AxiVldRdy (1'b1), + .LockIn (1'b1) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ('0), + .req_i (inp_valid_i), + .gnt_o (inp_ready_o), + .data_i (inp_data_i), + .gnt_i (oup_ready_i), + .req_o (oup_valid_o), + .data_o (oup_data_o), + .idx_o () + ); + + end else begin : gen_arb_error + // pragma translate_off + $fatal(1, "Invalid value for parameter 'ARBITER'!"); + // pragma translate_on + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/stream_demux.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_demux.sv new file mode 100644 index 0000000000..69ad3099b1 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_demux.sv @@ -0,0 +1,36 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// Connects the input stream (valid-ready) handshake to one of `N_OUP` output stream handshakes. +/// +/// This module has no data ports because stream data does not need to be demultiplexed: the data of +/// the input stream can just be applied at all output streams. +module stream_demux #( + /// Number of connected outputs. + parameter int unsigned N_OUP = 32'd1, + /// Dependent parameters, DO NOT OVERRIDE! + parameter int unsigned LOG_N_OUP = (N_OUP > 32'd1) ? unsigned'($clog2(N_OUP)) : 1'b1 +) ( + input logic inp_valid_i, + output logic inp_ready_o, + + input logic [LOG_N_OUP-1:0] oup_sel_i, + + output logic [N_OUP-1:0] oup_valid_o, + input logic [N_OUP-1:0] oup_ready_i +); + + always_comb begin + oup_valid_o = '0; + oup_valid_o[oup_sel_i] = inp_valid_i; + end + assign inp_ready_o = oup_ready_i[oup_sel_i]; + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/stream_xbar.sv b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_xbar.sv new file mode 100644 index 0000000000..957400680b --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/stream_xbar.sv @@ -0,0 +1,198 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +/// Fully connected stream crossbar. +/// +/// Handshaking rules as defined by the `AMBA AXI` standard on default. +module stream_xbar #( + /// Number of inputs into the crossbar (`> 0`). + parameter int unsigned NumInp = 32'd0, + /// Number of outputs from the crossbar (`> 0`). + parameter int unsigned NumOut = 32'd0, + /// Data width of the stream. Can be overwritten by defining the type parameter `payload_t`. + parameter int unsigned DataWidth = 32'd1, + /// Payload type of the data ports, only usage of parameter `DataWidth`. + parameter type payload_t = logic [DataWidth-1:0], + /// Adds a spill register stage at each output. + parameter bit OutSpillReg = 1'b0, + /// Use external priority for the individual `rr_arb_trees`. + parameter int unsigned ExtPrio = 1'b0, + /// Use strict AXI valid ready handshaking. + /// To be protocol conform also the parameter `LockIn` has to be set. + parameter int unsigned AxiVldRdy = 1'b1, + /// Lock in the arbitration decision of the `rr_arb_tree`. + /// When this is set, valids have to be asserted until the corresponding transaction is indicated + /// by ready. + parameter int unsigned LockIn = 1'b1, + /// Derived parameter, do **not** overwrite! + /// + /// Width of the output selection signal. + parameter int unsigned SelWidth = (NumOut > 32'd1) ? unsigned'($clog2(NumOut)) : 32'd1, + /// Derived parameter, do **not** overwrite! + /// + /// Signal type definition for selecting the output at the inputs. + parameter type sel_oup_t = logic[SelWidth-1:0], + /// Derived parameter, do **not** overwrite! + /// + /// Width of the input index signal. + parameter int unsigned IdxWidth = (NumInp > 32'd1) ? unsigned'($clog2(NumInp)) : 32'd1, + /// Derived parameter, do **not** overwrite! + /// + /// Signal type definition indicating from which input the output came. + parameter type idx_inp_t = logic[IdxWidth-1:0] +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Flush the state of the internal `rr_arb_tree` modules. + /// If not used set to `0`. + /// Flush should only be used if there are no active `valid_i`, otherwise it will + /// not adhere to the AXI handshaking. + input logic flush_i, + /// Provide an external state for the `rr_arb_tree` models. + /// Will only do something if ExtPrio is `1` otherwise tie to `0`. + input idx_inp_t [NumOut-1:0] rr_i, + /// Input data ports. + /// Has to be stable as long as `valid_i` is asserted when parameter `AxiVldRdy` is set. + input payload_t [NumInp-1:0] data_i, + /// Selection of the output port where the data should be routed. + /// Has to be stable as long as `valid_i` is asserted and parameter `AxiVldRdy` is set. + input sel_oup_t [NumInp-1:0] sel_i, + /// Input is valid. + input logic [NumInp-1:0] valid_i, + /// Input is ready to accept data. + output logic [NumInp-1:0] ready_o, + /// Output data ports. Valid if `valid_o = 1` + output payload_t [NumOut-1:0] data_o, + /// Index of the input port where data came from. + output idx_inp_t [NumOut-1:0] idx_o, + /// Output is valid. + output logic [NumOut-1:0] valid_o, + /// Output can be accepted. + input logic [NumOut-1:0] ready_i +); + typedef struct packed { + payload_t data; + idx_inp_t idx; + } spill_data_t; + + logic [NumInp-1:0][NumOut-1:0] inp_valid; + logic [NumInp-1:0][NumOut-1:0] inp_ready; + + payload_t [NumOut-1:0][NumInp-1:0] out_data; + logic [NumOut-1:0][NumInp-1:0] out_valid; + logic [NumOut-1:0][NumInp-1:0] out_ready; + + // Generate the input selection + for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_inps + stream_demux #( + .N_OUP ( NumOut ) + ) i_stream_demux ( + .inp_valid_i ( valid_i[i] ), + .inp_ready_o ( ready_o[i] ), + .oup_sel_i ( sel_i[i] ), + .oup_valid_o ( inp_valid[i] ), + .oup_ready_i ( inp_ready[i] ) + ); + + // Do the switching cross of the signals. + for (genvar j = 0; unsigned'(j) < NumOut; j++) begin : gen_cross + // Propagate the data from this input to all outputs. + assign out_data[j][i] = data_i[i]; + // switch handshaking + assign out_valid[j][i] = inp_valid[i][j]; + assign inp_ready[i][j] = out_ready[j][i]; + end + end + + // Generate the output arbitration. + for (genvar j = 0; unsigned'(j) < NumOut; j++) begin : gen_outs + spill_data_t arb; + logic arb_valid, arb_ready; + + rr_arb_tree #( + .NumIn ( NumInp ), + .DataType ( payload_t ), + .ExtPrio ( ExtPrio ), + .AxiVldRdy ( AxiVldRdy ), + .LockIn ( LockIn ) + ) i_rr_arb_tree ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ( rr_i[j] ), + .req_i ( out_valid[j] ), + .gnt_o ( out_ready[j] ), + .data_i ( out_data[j] ), + .req_o ( arb_valid ), + .gnt_i ( arb_ready ), + .data_o ( arb.data ), + .idx_o ( arb.idx ) + ); + + spill_data_t spill; + + spill_register #( + .T ( spill_data_t ), + .Bypass ( !OutSpillReg ) + ) i_spill_register ( + .clk_i, + .rst_ni, + .valid_i ( arb_valid ), + .ready_o ( arb_ready ), + .data_i ( arb ), + .valid_o ( valid_o[j] ), + .ready_i ( ready_i[j] ), + .data_o ( spill ) + ); + // Assign the outputs (deaggregate the data). + assign data_o[j] = spill.data; + assign idx_o[j] = spill.idx; + end + + // Assertions + // Make sure that the handshake and payload is stable + // pragma translate_off + `ifndef VERILATOR + default disable iff rst_ni; + for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_sel_assertions + assert property (@(posedge clk_i) (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else + $fatal(1, "Non-existing output is selected!"); + end + + if (AxiVldRdy) begin : gen_handshake_assertions + for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_inp_assertions + assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else + $error("data_i is unstable at input: %0d", i); + assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else + $error("sel_i is unstable at input: %0d", i); + assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> valid_i[i])) else + $error("valid_i at input %0d has been taken away without a ready.", i); + end + for (genvar i = 0; unsigned'(i) < NumOut; i++) begin : gen_out_assertions + assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else + $error("data_o is unstable at output: %0d Check that parameter LockIn is set.", i); + assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else + $error("idx_o is unstable at output: %0d Check that parameter LockIn is set.", i); + assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> valid_o[i])) else + $error("valid_o at output %0d has been taken away without a ready.", i); + end + end + + initial begin : proc_parameter_assertions + assert (NumInp > 32'd0) else $fatal(1, "NumInp has to be > 0!"); + assert (NumOut > 32'd0) else $fatal(1, "NumOut has to be > 0!"); + end + `endif + // pragma translate_on +endmodule diff --git a/flow/designs/src/mempool_group/rtl/fakeram45_256x32.sv b/flow/designs/src/mempool_group/rtl/fakeram45_256x32.sv new file mode 100644 index 0000000000..a7f6e60726 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/fakeram45_256x32.sv @@ -0,0 +1,9 @@ +module fakeram45_256x32 ( + output reg [31:0] rd_out, + input logic [7:0] addr_in, + input logic we_in, + input logic [31:0] wd_in, + input logic clk, + input logic ce_in +); +endmodule diff --git a/flow/designs/src/mempool_group/rtl/fakeram45_64x64.sv b/flow/designs/src/mempool_group/rtl/fakeram45_64x64.sv new file mode 100644 index 0000000000..566738074c --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/fakeram45_64x64.sv @@ -0,0 +1,9 @@ +module fakeram45_64x64 ( + output reg [63:0] rd_out, + input logic [5:0] addr_in, + input logic we_in, + input logic [63:0] wd_in, + input logic clk, + input logic ce_in +); +endmodule diff --git a/flow/designs/src/mempool_group/rtl/latch_scm.sv b/flow/designs/src/mempool_group/rtl/latch_scm.sv new file mode 100644 index 0000000000..aee1bff9a3 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/latch_scm.sv @@ -0,0 +1,122 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +module latch_scm #( + parameter ADDR_WIDTH = 5, + parameter DATA_WIDTH = 32 +) ( + input logic clk, + // Read port + input logic ReadEnable, + input logic [ADDR_WIDTH-1:0] ReadAddr, + output logic [DATA_WIDTH-1:0] ReadData, + // Write port + input logic WriteEnable, + input logic [ADDR_WIDTH-1:0] WriteAddr, + input logic [DATA_WIDTH-1:0] WriteData +); + + localparam NUM_WORDS = 2**ADDR_WIDTH; + + // Read address register, located at the input of the address decoder + logic [ADDR_WIDTH-1:0] RAddrRegxDP; + logic [NUM_WORDS-1:0] RAddrOneHotxD; + + logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS]; + + logic [NUM_WORDS-1:0] WAddrOneHotxD; + logic [NUM_WORDS-1:0] ClocksxC; + logic [DATA_WIDTH-1:0] WDataIntxD; + + logic clk_int; + + int unsigned i; + int unsigned j; + int unsigned k; + int unsigned l; + int unsigned m; + + genvar x; + genvar y; + + tc_clk_gating CG_WE_GLOBAL ( + .clk_o (clk_int ), + .en_i (WriteEnable), + .test_en_i (1'b0 ), + .clk_i (clk ) + ); + + //----------------------------------------------------------------------------- + //-- READ : Read address register + //----------------------------------------------------------------------------- + always_ff @(posedge clk) begin : p_RAddrReg + if(ReadEnable) + RAddrRegxDP <= ReadAddr; + end + + + //----------------------------------------------------------------------------- + //-- READ : Read address decoder RAD + //----------------------------------------------------------------------------- + always_comb begin : p_RAD + RAddrOneHotxD = '0; + RAddrOneHotxD[RAddrRegxDP] = 1'b1; + end + assign ReadData = MemContentxDP[RAddrRegxDP]; + + + //----------------------------------------------------------------------------- + //-- WRITE : Write Address Decoder (WAD), combinatorial process + //----------------------------------------------------------------------------- + always_comb begin : p_WAD + for(i=0; i Flatten them for Verilator + `define STRUCT_PORT(struct_t) \ + `ifndef VERILATOR \ + struct_t \ + `else \ + logic[$bits(struct_t)-1:0] \ + `endif + + // Create a flattened vector of a struct. Make sure the first dimension is + // the dimension into the vector of struct types and not the struct itself. + `define STRUCT_VECT(struct_t, dim) \ + `ifndef VERILATOR \ + struct_t dim \ + `else \ + logic dim [$bits(struct_t)-1:0] \ + `endif + +`endif diff --git a/flow/designs/src/mempool_group/rtl/mempool_cc.sv b/flow/designs/src/mempool_group/rtl/mempool_cc.sv new file mode 100644 index 0000000000..3a07a786de --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/mempool_cc.sv @@ -0,0 +1,320 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +module mempool_cc + import snitch_pkg::meta_id_t; +#( + parameter logic [31:0] BootAddr = 32'h0000_1000, + parameter logic [31:0] MTVEC = BootAddr, + parameter bit RVE = 0, // Reduced-register extension + parameter bit RVM = 1, // Enable IntegerMmultiplication & Division Extension + parameter bit RegisterOffloadReq = 1, + parameter bit RegisterOffloadResp = 1, + parameter bit RegisterTCDMReq = 0, + parameter bit RegisterTCDMResp = 0 +) ( + input logic clk_i, + input logic rst_i, + input logic [31:0] hart_id_i, + // Instruction Port + output logic [31:0] inst_addr_o, + input logic [31:0] inst_data_i, + output logic inst_valid_o, + input logic inst_ready_i, + // TCDM Ports + output logic [31:0] data_qaddr_o, + output logic data_qwrite_o, + output logic [3:0] data_qamo_o, + output logic [31:0] data_qdata_o, + output logic [3:0] data_qstrb_o, + output meta_id_t data_qid_o, + output logic data_qvalid_o, + input logic data_qready_i, + input logic [31:0] data_pdata_i, + input logic data_perror_i, + input meta_id_t data_pid_i, + input logic data_pvalid_i, + output logic data_pready_o, + input logic wake_up_sync_i, + // Core event strobes + output snitch_pkg::core_events_t core_events_o +); + + // Data port signals + snitch_pkg::dreq_t data_req_d, data_req_q; + snitch_pkg::dresp_t data_resp_d, data_resp_q; + + logic data_req_d_valid, data_req_d_ready, data_resp_d_valid, data_resp_d_ready; + logic data_req_q_valid, data_req_q_ready, data_resp_q_valid, data_resp_q_ready; + + // Accelerator signals + snitch_pkg::acc_req_t acc_req_d, acc_req_q; + snitch_pkg::acc_resp_t acc_resp_d, acc_resp_q; + + logic acc_req_d_valid, acc_req_d_ready, acc_resp_d_valid, acc_resp_d_ready; + logic acc_req_q_valid, acc_req_q_ready, acc_resp_q_valid, acc_resp_q_ready; + + // Snitch Integer Core + snitch #( + .BootAddr ( BootAddr ), + .MTVEC ( MTVEC ), + .RVE ( RVE ), + .RVM ( RVM ) + ) i_snitch ( + .clk_i , + .rst_i , + .hart_id_i , + .inst_addr_o , + .inst_data_i , + .inst_valid_o , + .inst_ready_i , + .acc_qaddr_o ( acc_req_d.addr ), + .acc_qid_o ( acc_req_d.id ), + .acc_qdata_op_o ( acc_req_d.data_op ), + .acc_qdata_arga_o ( acc_req_d.data_arga ), + .acc_qdata_argb_o ( acc_req_d.data_argb ), + .acc_qdata_argc_o ( acc_req_d.data_argc ), + .acc_qvalid_o ( acc_req_d_valid ), + .acc_qready_i ( acc_req_d_ready ), + .acc_pdata_i ( acc_resp_q.data ), + .acc_pid_i ( acc_resp_q.id ), + .acc_perror_i ( acc_resp_q.error ), + .acc_pvalid_i ( acc_resp_q_valid ), + .acc_pready_o ( acc_resp_q_ready ), + .data_qaddr_o ( data_req_d.addr ), + .data_qwrite_o ( data_req_d.write ), + .data_qamo_o ( data_req_d.amo ), + .data_qdata_o ( data_req_d.data ), + .data_qstrb_o ( data_req_d.strb ), + .data_qid_o ( data_req_d.id ), + .data_qvalid_o ( data_req_d_valid ), + .data_qready_i ( data_req_d_ready ), + .data_pdata_i ( data_resp_q.data ), + .data_perror_i ( data_resp_q.error ), + .data_pid_i ( data_resp_q.id ), + .data_pvalid_i ( data_resp_q_valid ), + .data_pready_o ( data_resp_q_ready ), + .wake_up_sync_i ( wake_up_sync_i ), + .core_events_o ( core_events_o ) + ); + + // Cut off-loading request path + spill_register #( + .T ( snitch_pkg::acc_req_t ), + .Bypass ( !RegisterOffloadReq ) + ) i_spill_register_acc_req ( + .clk_i , + .rst_ni ( ~rst_i ), + .valid_i ( acc_req_d_valid ), + .ready_o ( acc_req_d_ready ), + .data_i ( acc_req_d ), + .valid_o ( acc_req_q_valid ), + .ready_i ( acc_req_q_ready ), + .data_o ( acc_req_q ) + ); + + // Cut off-loading response path + spill_register #( + .T ( snitch_pkg::acc_resp_t ), + .Bypass ( !RegisterOffloadResp ) + ) i_spill_register_acc_resp ( + .clk_i , + .rst_ni ( ~rst_i ), + .valid_i ( acc_resp_d_valid ), + .ready_o ( acc_resp_d_ready ), + .data_i ( acc_resp_d ), + .valid_o ( acc_resp_q_valid ), + .ready_i ( acc_resp_q_ready ), + .data_o ( acc_resp_q ) + ); + + // Snitch IPU accelerator + snitch_ipu #( + .IdWidth ( 5 ) + ) i_snitch_ipu ( + .clk_i , + .rst_i , + .acc_qaddr_i ( acc_req_q.addr ), + .acc_qid_i ( acc_req_q.id ), + .acc_qdata_op_i ( acc_req_q.data_op ), + .acc_qdata_arga_i ( acc_req_q.data_arga ), + .acc_qdata_argb_i ( acc_req_q.data_argb ), + .acc_qdata_argc_i ( acc_req_q.data_argc ), + .acc_qvalid_i ( acc_req_q_valid ), + .acc_qready_o ( acc_req_q_ready ), + .acc_pdata_o ( acc_resp_d.data ), + .acc_pid_o ( acc_resp_d.id ), + .acc_perror_o ( acc_resp_d.error ), + .acc_pvalid_o ( acc_resp_d_valid ), + .acc_pready_i ( acc_resp_d_ready ) + ); + + // Cut TCDM data request path + spill_register #( + .T ( snitch_pkg::dreq_t ), + .Bypass ( !RegisterTCDMReq ) + ) i_spill_register_tcdm_req ( + .clk_i , + .rst_ni ( ~rst_i ), + .valid_i ( data_req_d_valid ), + .ready_o ( data_req_d_ready ), + .data_i ( data_req_d ), + .valid_o ( data_req_q_valid ), + .ready_i ( data_req_q_ready ), + .data_o ( data_req_q ) + ); + + // Cut TCDM data response path + spill_register #( + .T ( snitch_pkg::dresp_t ), + .Bypass ( !RegisterTCDMResp ) + ) i_spill_register_tcdm_resp ( + .clk_i , + .rst_ni ( ~rst_i ), + .valid_i ( data_resp_d_valid ), + .ready_o ( data_resp_d_ready ), + .data_i ( data_resp_d ), + .valid_o ( data_resp_q_valid ), + .ready_i ( data_resp_q_ready ), + .data_o ( data_resp_q ) + ); + + // Assign TCDM data interface + assign data_qaddr_o = data_req_q.addr; + assign data_qwrite_o = data_req_q.write; + assign data_qamo_o = data_req_q.amo; + assign data_qdata_o = data_req_q.data; + assign data_qstrb_o = data_req_q.strb; + assign data_qid_o = data_req_q.id; + assign data_qvalid_o = data_req_q_valid; + assign data_req_q_ready = data_qready_i; + assign data_resp_d.data = data_pdata_i; + assign data_resp_d.id = data_pid_i; + assign data_resp_d.error = data_perror_i; + assign data_resp_d_valid = data_pvalid_i; + assign data_pready_o = data_resp_d_ready; + + // -------------------------- + // Tracer + // -------------------------- + // pragma translate_off + int f; + string fn; + logic [63:0] cycle; + int unsigned stall, stall_ins, stall_raw, stall_lsu, stall_acc; + + always_ff @(posedge rst_i) begin + if(rst_i) begin + $sformat(fn, "trace_hart_%04x.dasm", hart_id_i); + f = $fopen(fn, "w"); + $display("[Tracer] Logging Hart %d to %s", hart_id_i, fn); + end + end + + typedef enum logic [1:0] {SrcSnitch = 0, SrcFpu = 1, SrcFpuSeq = 2} trace_src_e; + localparam int SnitchTrace = `ifdef SNITCH_TRACE `SNITCH_TRACE `else 0 `endif; + + always_ff @(posedge clk_i or posedge rst_i) begin + automatic string trace_entry; + automatic string extras_str; + + if (!rst_i) begin + cycle <= cycle + 1; + // Trace snitch iff: + // Tracing enabled by CSR register + // we are not stalled <==> we have issued and processed an instruction (including offloads) + // OR we are retiring (issuing a writeback from) a load or accelerator instruction + if ((i_snitch.csr_trace_q || SnitchTrace) && (!i_snitch.stall || i_snitch.retire_load || i_snitch.retire_acc)) begin + // Manual loop unrolling for Verilator + // Data type keys for arrays are currently not supported in Verilator + extras_str = "{"; + // State + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "source", SrcSnitch); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall", i_snitch.stall); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall_tot", stall); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall_ins", stall_ins); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall_raw", stall_raw); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall_lsu", stall_lsu); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "stall_acc", stall_acc); + // Decoding + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "rs1", i_snitch.rs1); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "rs2", i_snitch.rs2); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "rd", i_snitch.rd); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "is_load", i_snitch.is_load); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "is_store", i_snitch.is_store); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "is_branch", i_snitch.is_branch); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "pc_d", i_snitch.pc_d); + // Operands + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "opa", i_snitch.opa); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "opb", i_snitch.opb); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "opa_select", i_snitch.opa_select); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "opb_select", i_snitch.opb_select); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "write_rd", i_snitch.write_rd); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "csr_addr", i_snitch.inst_data_i[31:20]); + // Pipeline writeback + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "writeback", i_snitch.alu_writeback); + // Load/Store + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "gpr_rdata_1", i_snitch.gpr_rdata[1]); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "ls_size", i_snitch.ls_size); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "ld_result_32",i_snitch.ld_result[31:0]); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "lsu_rd", i_snitch.lsu_rd); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "retire_load", i_snitch.retire_load); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "alu_result", i_snitch.alu_result); + // Atomics + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "ls_amo", i_snitch.ls_amo); + // Accumulator + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "retire_acc", i_snitch.retire_acc); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "acc_pid", i_snitch.acc_pid_i); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "acc_pdata_32",i_snitch.acc_pdata_i[31:0]); + // FPU offload + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "fpu_offload", 1'b0); + extras_str = $sformatf("%s'%s': 0x%8x, ", extras_str, "is_seq_insn", 1'b0); + extras_str = $sformatf("%s}", extras_str); + + $sformat(trace_entry, "%t %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, i_snitch.pc_q, i_snitch.inst_data_i, extras_str); + $fwrite(f, trace_entry); + end + + // Reset all stalls when we execute an instruction + if (!i_snitch.stall) begin + stall <= 0; + stall_ins <= 0; + stall_raw <= 0; + stall_lsu <= 0; + stall_acc <= 0; + end else begin + // We are currently stalled, let's count the stall causes + if (i_snitch.stall) begin + stall <= stall + 1; + end + if ((!i_snitch.inst_ready_i) && (i_snitch.inst_valid_o)) begin + stall_ins <= stall_ins + 1; + end + if ((!i_snitch.operands_ready) || (!i_snitch.dst_ready)) begin + stall_raw <= stall_raw + 1; + end + if (i_snitch.lsu_stall) begin + stall_lsu <= stall_lsu + 1; + end + if (i_snitch.acc_stall) begin + stall_acc <= stall_acc + 1; + end + end + end else begin + cycle <= '0; + stall <= 0; + stall_ins <= 0; + stall_raw <= 0; + stall_lsu <= 0; + stall_acc <= 0; + end + end + + final begin + $fclose(f); + end + // pragma translate_on + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/mempool_group.sv b/flow/designs/src/mempool_group/rtl/mempool_group.sv new file mode 100644 index 0000000000..6492f22c8a --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/mempool_group.sv @@ -0,0 +1,605 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +`include "mempool/mempool.svh" + +module mempool_group + import mempool_pkg::*; + import cf_math_pkg::idx_width; +#( + // TCDM + parameter addr_t TCDMBaseAddr = 32'b0, + // Boot address + parameter logic [31:0] BootAddr = 32'h0000_1000, + // Dependant parameters. DO NOT CHANGE! + parameter int unsigned NumAXIMasters = NumTilesPerGroup +) ( + // Clock and reset + input logic clk_i, + input logic rst_ni, + input logic testmode_i, + // Scan chain + input logic scan_enable_i, + input logic scan_data_i, + output logic scan_data_o, + // Group ID + input logic [idx_width(NumGroups)-1:0] group_id_i, + // TCDM Master interfaces + output `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_master_north_req_o, + output logic [NumTilesPerGroup-1:0] tcdm_master_north_req_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_master_north_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_master_north_resp_i, + input logic [NumTilesPerGroup-1:0] tcdm_master_north_resp_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_master_north_resp_ready_o, + output `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_master_northeast_req_o, + output logic [NumTilesPerGroup-1:0] tcdm_master_northeast_req_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_master_northeast_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_master_northeast_resp_i, + input logic [NumTilesPerGroup-1:0] tcdm_master_northeast_resp_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_master_northeast_resp_ready_o, + output `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_master_bypass_req_o, + output logic [NumTilesPerGroup-1:0] tcdm_master_bypass_req_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_master_bypass_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_master_bypass_resp_i, + input logic [NumTilesPerGroup-1:0] tcdm_master_bypass_resp_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_master_bypass_resp_ready_o, + output `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_master_east_req_o, + output logic [NumTilesPerGroup-1:0] tcdm_master_east_req_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_master_east_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_master_east_resp_i, + input logic [NumTilesPerGroup-1:0] tcdm_master_east_resp_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_master_east_resp_ready_o, + // TCDM Slave interfaces + input `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_slave_north_req_i, + input logic [NumTilesPerGroup-1:0] tcdm_slave_north_req_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_slave_north_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_slave_north_resp_o, + output logic [NumTilesPerGroup-1:0] tcdm_slave_north_resp_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_slave_north_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_slave_northeast_req_i, + input logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_req_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_slave_northeast_resp_o, + output logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_slave_bypass_req_i, + input logic [NumTilesPerGroup-1:0] tcdm_slave_bypass_req_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_slave_bypass_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_slave_bypass_resp_o, + output logic [NumTilesPerGroup-1:0] tcdm_slave_bypass_resp_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_slave_bypass_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumTilesPerGroup-1:0]) tcdm_slave_east_req_i, + input logic [NumTilesPerGroup-1:0] tcdm_slave_east_req_valid_i, + output logic [NumTilesPerGroup-1:0] tcdm_slave_east_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumTilesPerGroup-1:0]) tcdm_slave_east_resp_o, + output logic [NumTilesPerGroup-1:0] tcdm_slave_east_resp_valid_o, + input logic [NumTilesPerGroup-1:0] tcdm_slave_east_resp_ready_i, + // Wake up interface + input logic [NumCoresPerGroup-1:0] wake_up_i, + // AXI Interface + output `STRUCT_PORT(axi_tile_req_t) axi_mst_req_o, + input `STRUCT_PORT(axi_tile_resp_t) axi_mst_resp_i +); + + /***************** + * Definitions * + *****************/ + + typedef logic [idx_width(NumTiles)-1:0] tile_id_t; + + /********************** + * Ports to structs * + **********************/ + + // The ports might be structs flattened to vectors. To access the structs' + // internal signals, assign the flattened vectors back to structs. + tcdm_slave_req_t [NumTilesPerGroup-1:0] tcdm_master_north_req_s; + tcdm_slave_req_t [NumTilesPerGroup-1:0] tcdm_master_northeast_req_s; + tcdm_slave_req_t [NumTilesPerGroup-1:0] tcdm_master_east_req_s; + tcdm_master_resp_t [NumTilesPerGroup-1:0] tcdm_slave_north_resp_s; + tcdm_master_resp_t [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp_s; + tcdm_master_resp_t [NumTilesPerGroup-1:0] tcdm_slave_east_resp_s; + + assign tcdm_master_north_req_o = tcdm_master_north_req_s; + assign tcdm_master_northeast_req_o = tcdm_master_northeast_req_s; + assign tcdm_master_east_req_o = tcdm_master_east_req_s; + assign tcdm_slave_north_resp_o = tcdm_slave_north_resp_s; + assign tcdm_slave_northeast_resp_o = tcdm_slave_northeast_resp_s; + assign tcdm_slave_east_resp_o = tcdm_slave_east_resp_s; + + /*********** + * Tiles * + ***********/ + + // TCDM interfaces + // North + tcdm_master_req_t [NumTilesPerGroup-1:0] tcdm_master_north_req; + logic [NumTilesPerGroup-1:0] tcdm_master_north_req_valid; + logic [NumTilesPerGroup-1:0] tcdm_master_north_req_ready; + tcdm_slave_resp_t [NumTilesPerGroup-1:0] tcdm_slave_north_resp; + logic [NumTilesPerGroup-1:0] tcdm_slave_north_resp_valid; + logic [NumTilesPerGroup-1:0] tcdm_slave_north_resp_ready; + // East + tcdm_master_req_t [NumTilesPerGroup-1:0] tcdm_master_east_req; + logic [NumTilesPerGroup-1:0] tcdm_master_east_req_valid; + logic [NumTilesPerGroup-1:0] tcdm_master_east_req_ready; + tcdm_slave_resp_t [NumTilesPerGroup-1:0] tcdm_slave_east_resp; + logic [NumTilesPerGroup-1:0] tcdm_slave_east_resp_valid; + logic [NumTilesPerGroup-1:0] tcdm_slave_east_resp_ready; + // Northeast + tcdm_master_req_t [NumTilesPerGroup-1:0] tcdm_master_northeast_req; + logic [NumTilesPerGroup-1:0] tcdm_master_northeast_req_valid; + logic [NumTilesPerGroup-1:0] tcdm_master_northeast_req_ready; + tcdm_slave_resp_t [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp; + logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp_valid; + logic [NumTilesPerGroup-1:0] tcdm_slave_northeast_resp_ready; + // Center + tcdm_master_req_t [NumTilesPerGroup-1:0] tcdm_master_local_req; + logic [NumTilesPerGroup-1:0] tcdm_master_local_req_valid; + logic [NumTilesPerGroup-1:0] tcdm_master_local_req_ready; + tcdm_master_resp_t [NumTilesPerGroup-1:0] tcdm_master_local_resp; + logic [NumTilesPerGroup-1:0] tcdm_master_local_resp_valid; + logic [NumTilesPerGroup-1:0] tcdm_master_local_resp_ready; + tcdm_slave_req_t [NumTilesPerGroup-1:0] tcdm_slave_local_req; + logic [NumTilesPerGroup-1:0] tcdm_slave_local_req_valid; + logic [NumTilesPerGroup-1:0] tcdm_slave_local_req_ready; + tcdm_slave_resp_t [NumTilesPerGroup-1:0] tcdm_slave_local_resp; + logic [NumTilesPerGroup-1:0] tcdm_slave_local_resp_valid; + logic [NumTilesPerGroup-1:0] tcdm_slave_local_resp_ready; + + // AXI interfaces + axi_tile_req_t [NumTilesPerGroup-1:0] axi_tile_req; + axi_tile_resp_t [NumTilesPerGroup-1:0] axi_tile_resp; + + for (genvar t = 0; unsigned'(t) < NumTilesPerGroup; t++) begin: gen_tiles + tile_id_t id; + assign id = (group_id_i << $clog2(NumTilesPerGroup)) | t[idx_width(NumTilesPerGroup)-1:0]; + mempool_tile_wrap #( + .TCDMBaseAddr(TCDMBaseAddr), + .BootAddr (BootAddr ) + ) i_tile ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .scan_enable_i (scan_enable_i ), + .scan_data_i (/* Unconnected */ ), + .scan_data_o (/* Unconnected */ ), + .tile_id_i (id ), + // TCDM Master interfaces + .tcdm_master_north_req_o (tcdm_master_north_req[t] ), + .tcdm_master_north_req_valid_o (tcdm_master_north_req_valid[t] ), + .tcdm_master_north_req_ready_i (tcdm_master_north_req_ready[t] ), + .tcdm_master_north_resp_i (tcdm_master_north_resp_i[t] ), + .tcdm_master_north_resp_valid_i (tcdm_master_north_resp_valid_i[t] ), + .tcdm_master_north_resp_ready_o (tcdm_master_north_resp_ready_o[t] ), + .tcdm_master_east_req_o (tcdm_master_east_req[t] ), + .tcdm_master_east_req_valid_o (tcdm_master_east_req_valid[t] ), + .tcdm_master_east_req_ready_i (tcdm_master_east_req_ready[t] ), + .tcdm_master_east_resp_i (tcdm_master_east_resp_i[t] ), + .tcdm_master_east_resp_valid_i (tcdm_master_east_resp_valid_i[t] ), + .tcdm_master_east_resp_ready_o (tcdm_master_east_resp_ready_o[t] ), + .tcdm_master_northeast_req_o (tcdm_master_northeast_req[t] ), + .tcdm_master_northeast_req_valid_o (tcdm_master_northeast_req_valid[t] ), + .tcdm_master_northeast_req_ready_i (tcdm_master_northeast_req_ready[t] ), + .tcdm_master_northeast_resp_i (tcdm_master_northeast_resp_i[t] ), + .tcdm_master_northeast_resp_valid_i(tcdm_master_northeast_resp_valid_i[t] ), + .tcdm_master_northeast_resp_ready_o(tcdm_master_northeast_resp_ready_o[t] ), + .tcdm_master_local_req_o (tcdm_master_local_req[t] ), + .tcdm_master_local_req_valid_o (tcdm_master_local_req_valid[t] ), + .tcdm_master_local_req_ready_i (tcdm_master_local_req_ready[t] ), + .tcdm_master_local_resp_i (tcdm_master_local_resp[t] ), + .tcdm_master_local_resp_valid_i (tcdm_master_local_resp_valid[t] ), + .tcdm_master_local_resp_ready_o (tcdm_master_local_resp_ready[t] ), + // TCDM banks interface + .tcdm_slave_north_req_i (tcdm_slave_north_req_i[t] ), + .tcdm_slave_north_req_valid_i (tcdm_slave_north_req_valid_i[t] ), + .tcdm_slave_north_req_ready_o (tcdm_slave_north_req_ready_o[t] ), + .tcdm_slave_north_resp_o (tcdm_slave_north_resp[t] ), + .tcdm_slave_north_resp_valid_o (tcdm_slave_north_resp_valid[t] ), + .tcdm_slave_north_resp_ready_i (tcdm_slave_north_resp_ready[t] ), + .tcdm_slave_east_req_i (tcdm_slave_east_req_i[t] ), + .tcdm_slave_east_req_valid_i (tcdm_slave_east_req_valid_i[t] ), + .tcdm_slave_east_req_ready_o (tcdm_slave_east_req_ready_o[t] ), + .tcdm_slave_east_resp_o (tcdm_slave_east_resp[t] ), + .tcdm_slave_east_resp_valid_o (tcdm_slave_east_resp_valid[t] ), + .tcdm_slave_east_resp_ready_i (tcdm_slave_east_resp_ready[t] ), + .tcdm_slave_northeast_req_i (tcdm_slave_northeast_req_i[t] ), + .tcdm_slave_northeast_req_valid_i (tcdm_slave_northeast_req_valid_i[t] ), + .tcdm_slave_northeast_req_ready_o (tcdm_slave_northeast_req_ready_o[t] ), + .tcdm_slave_northeast_resp_o (tcdm_slave_northeast_resp[t] ), + .tcdm_slave_northeast_resp_valid_o (tcdm_slave_northeast_resp_valid[t] ), + .tcdm_slave_northeast_resp_ready_i (tcdm_slave_northeast_resp_ready[t] ), + .tcdm_slave_local_req_i (tcdm_slave_local_req[t] ), + .tcdm_slave_local_req_valid_i (tcdm_slave_local_req_valid[t] ), + .tcdm_slave_local_req_ready_o (tcdm_slave_local_req_ready[t] ), + .tcdm_slave_local_resp_o (tcdm_slave_local_resp[t] ), + .tcdm_slave_local_resp_valid_o (tcdm_slave_local_resp_valid[t] ), + .tcdm_slave_local_resp_ready_i (tcdm_slave_local_resp_ready[t] ), + // AXI interface + .axi_mst_req_o (axi_tile_req[t] ), + .axi_mst_resp_i (axi_tile_resp[t] ), + // Wake up interface + .wake_up_i (wake_up_i[t*NumCoresPerTile +: NumCoresPerTile]) + ); + end : gen_tiles + + /************************* + * Local Interconnect * + *************************/ + + logic [NumTilesPerGroup-1:0] master_local_req_valid; + logic [NumTilesPerGroup-1:0] master_local_req_ready; + tcdm_addr_t [NumTilesPerGroup-1:0] master_local_req_tgt_addr; + logic [NumTilesPerGroup-1:0] master_local_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] master_local_req_wdata; + strb_t [NumTilesPerGroup-1:0] master_local_req_be; + logic [NumTilesPerGroup-1:0] master_local_resp_valid; + logic [NumTilesPerGroup-1:0] master_local_resp_ready; + tcdm_payload_t [NumTilesPerGroup-1:0] master_local_resp_rdata; + logic [NumTilesPerGroup-1:0] slave_local_req_valid; + logic [NumTilesPerGroup-1:0] slave_local_req_ready; + tile_addr_t [NumTilesPerGroup-1:0] slave_local_req_tgt_addr; + tile_group_id_t [NumTilesPerGroup-1:0] slave_local_req_ini_addr; + logic [NumTilesPerGroup-1:0] slave_local_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_local_req_wdata; + strb_t [NumTilesPerGroup-1:0] slave_local_req_be; + logic [NumTilesPerGroup-1:0] slave_local_resp_valid; + logic [NumTilesPerGroup-1:0] slave_local_resp_ready; + tile_group_id_t [NumTilesPerGroup-1:0] slave_local_resp_ini_addr; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_local_resp_rdata; + + for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_local_connections + assign master_local_req_valid[t] = tcdm_master_local_req_valid[t]; + assign master_local_req_tgt_addr[t] = tcdm_master_local_req[t].tgt_addr; + assign master_local_req_wen[t] = tcdm_master_local_req[t].wen; + assign master_local_req_wdata[t] = tcdm_master_local_req[t].wdata; + assign master_local_req_be[t] = tcdm_master_local_req[t].be; + assign tcdm_master_local_req_ready[t] = master_local_req_ready[t]; + assign slave_local_resp_valid[t] = tcdm_slave_local_resp_valid[t]; + assign slave_local_resp_ini_addr[t] = tcdm_slave_local_resp[t].ini_addr; + assign slave_local_resp_rdata[t] = tcdm_slave_local_resp[t].rdata; + assign tcdm_slave_local_resp_ready[t] = slave_local_resp_ready[t]; + assign tcdm_master_local_resp_valid[t] = master_local_resp_valid[t]; + assign tcdm_master_local_resp[t].rdata = master_local_resp_rdata[t]; + assign master_local_resp_ready[t] = tcdm_master_local_resp_ready[t]; + assign tcdm_slave_local_req_valid[t] = slave_local_req_valid[t]; + assign tcdm_slave_local_req[t].tgt_addr = slave_local_req_tgt_addr[t]; + assign tcdm_slave_local_req[t].ini_addr = slave_local_req_ini_addr[t]; + assign tcdm_slave_local_req[t].wen = slave_local_req_wen[t]; + assign tcdm_slave_local_req[t].wdata = slave_local_req_wdata[t]; + assign tcdm_slave_local_req[t].be = slave_local_req_be[t]; + assign slave_local_req_ready[t] = tcdm_slave_local_req_ready[t]; + end + + variable_latency_interconnect #( + .NumIn (NumTilesPerGroup ), + .NumOut (NumTilesPerGroup ), + .AddrWidth (TCDMAddrWidth ), + .DataWidth ($bits(tcdm_payload_t) ), + .BeWidth (DataWidth/8 ), + .ByteOffWidth(0 ), + .AddrMemWidth(TCDMAddrMemWidth + idx_width(NumBanksPerTile)), + .Topology (tcdm_interconnect_pkg::LIC ), + .AxiVldRdy (1'b1 ) + ) i_local_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_valid_i (master_local_req_valid ), + .req_ready_o (master_local_req_ready ), + .req_tgt_addr_i (master_local_req_tgt_addr), + .req_wen_i (master_local_req_wen ), + .req_wdata_i (master_local_req_wdata ), + .req_be_i (master_local_req_be ), + .resp_valid_o (master_local_resp_valid ), + .resp_ready_i (master_local_resp_ready ), + .resp_rdata_o (master_local_resp_rdata ), + .resp_ini_addr_i(slave_local_resp_ini_addr), + .resp_rdata_i (slave_local_resp_rdata ), + .resp_valid_i (slave_local_resp_valid ), + .resp_ready_o (slave_local_resp_ready ), + .req_valid_o (slave_local_req_valid ), + .req_ready_i (slave_local_req_ready ), + .req_be_o (slave_local_req_be ), + .req_wdata_o (slave_local_req_wdata ), + .req_wen_o (slave_local_req_wen ), + .req_ini_addr_o (slave_local_req_ini_addr ), + .req_tgt_addr_o (slave_local_req_tgt_addr ) + ); + + /*********************** + * East Interconnect * + ***********************/ + + logic [NumTilesPerGroup-1:0] master_east_req_valid; + logic [NumTilesPerGroup-1:0] master_east_req_ready; + tcdm_addr_t [NumTilesPerGroup-1:0] master_east_req_tgt_addr; + logic [NumTilesPerGroup-1:0] master_east_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] master_east_req_wdata; + strb_t [NumTilesPerGroup-1:0] master_east_req_be; + logic [NumTilesPerGroup-1:0] master_east_resp_valid; + logic [NumTilesPerGroup-1:0] master_east_resp_ready; + tcdm_payload_t [NumTilesPerGroup-1:0] master_east_resp_rdata; + logic [NumTilesPerGroup-1:0] slave_east_req_valid; + logic [NumTilesPerGroup-1:0] slave_east_req_ready; + tile_addr_t [NumTilesPerGroup-1:0] slave_east_req_tgt_addr; + tile_group_id_t [NumTilesPerGroup-1:0] slave_east_req_ini_addr; + logic [NumTilesPerGroup-1:0] slave_east_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_east_req_wdata; + strb_t [NumTilesPerGroup-1:0] slave_east_req_be; + logic [NumTilesPerGroup-1:0] slave_east_resp_valid; + logic [NumTilesPerGroup-1:0] slave_east_resp_ready; + tile_group_id_t [NumTilesPerGroup-1:0] slave_east_resp_ini_addr; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_east_resp_rdata; + + for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_east_connections + assign master_east_req_valid[t] = tcdm_master_east_req_valid[t]; + assign master_east_req_tgt_addr[t] = tcdm_master_east_req[t].tgt_addr; + assign master_east_req_wen[t] = tcdm_master_east_req[t].wen; + assign master_east_req_wdata[t] = tcdm_master_east_req[t].wdata; + assign master_east_req_be[t] = tcdm_master_east_req[t].be; + assign tcdm_master_east_req_ready[t] = master_east_req_ready[t]; + assign tcdm_master_east_req_valid_o[t] = slave_east_req_valid[t]; + assign tcdm_master_east_req_s[t].tgt_addr = slave_east_req_tgt_addr[t]; + assign tcdm_master_east_req_s[t].ini_addr = slave_east_req_ini_addr[t]; + assign tcdm_master_east_req_s[t].wen = slave_east_req_wen[t]; + assign tcdm_master_east_req_s[t].wdata = slave_east_req_wdata[t]; + assign tcdm_master_east_req_s[t].be = slave_east_req_be[t]; + assign slave_east_req_ready[t] = tcdm_master_east_req_ready_i[t]; + assign slave_east_resp_valid[t] = tcdm_slave_east_resp_valid[t]; + assign slave_east_resp_ini_addr[t] = tcdm_slave_east_resp[t].ini_addr; + assign slave_east_resp_rdata[t] = tcdm_slave_east_resp[t].rdata; + assign tcdm_slave_east_resp_ready[t] = slave_east_resp_ready[t]; + assign tcdm_slave_east_resp_valid_o[t] = master_east_resp_valid[t]; + assign tcdm_slave_east_resp_s[t].rdata = master_east_resp_rdata[t]; + assign master_east_resp_ready[t] = tcdm_slave_east_resp_ready_i[t]; + end + + variable_latency_interconnect #( + .NumIn (NumTilesPerGroup ), + .NumOut (NumTilesPerGroup ), + .AddrWidth (TCDMAddrWidth ), + .DataWidth ($bits(tcdm_payload_t) ), + .BeWidth (DataWidth/8 ), + .ByteOffWidth (0 ), + .AddrMemWidth (TCDMAddrMemWidth + idx_width(NumBanksPerTile)), + .Topology (tcdm_interconnect_pkg::LIC ), + .AxiVldRdy (1'b1 ), + .SpillRegisterReq (64'b1 ), + .SpillRegisterResp (64'b1 ), + .FallThroughRegister(1'b1 ) + ) i_east_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_valid_i (master_east_req_valid ), + .req_ready_o (master_east_req_ready ), + .req_tgt_addr_i (master_east_req_tgt_addr), + .req_wen_i (master_east_req_wen ), + .req_wdata_i (master_east_req_wdata ), + .req_be_i (master_east_req_be ), + .resp_valid_o (master_east_resp_valid ), + .resp_ready_i (master_east_resp_ready ), + .resp_rdata_o (master_east_resp_rdata ), + .resp_ini_addr_i(slave_east_resp_ini_addr), + .resp_rdata_i (slave_east_resp_rdata ), + .resp_valid_i (slave_east_resp_valid ), + .resp_ready_o (slave_east_resp_ready ), + .req_valid_o (slave_east_req_valid ), + .req_ready_i (slave_east_req_ready ), + .req_be_o (slave_east_req_be ), + .req_wdata_o (slave_east_req_wdata ), + .req_wen_o (slave_east_req_wen ), + .req_ini_addr_o (slave_east_req_ini_addr ), + .req_tgt_addr_o (slave_east_req_tgt_addr ) + ); + + /************************ + * North Interconnect * + ************************/ + + logic [NumTilesPerGroup-1:0] master_north_req_valid; + logic [NumTilesPerGroup-1:0] master_north_req_ready; + tcdm_addr_t [NumTilesPerGroup-1:0] master_north_req_tgt_addr; + logic [NumTilesPerGroup-1:0] master_north_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] master_north_req_wdata; + strb_t [NumTilesPerGroup-1:0] master_north_req_be; + logic [NumTilesPerGroup-1:0] master_north_resp_valid; + logic [NumTilesPerGroup-1:0] master_north_resp_ready; + tcdm_payload_t [NumTilesPerGroup-1:0] master_north_resp_rdata; + logic [NumTilesPerGroup-1:0] slave_north_req_valid; + logic [NumTilesPerGroup-1:0] slave_north_req_ready; + tile_addr_t [NumTilesPerGroup-1:0] slave_north_req_tgt_addr; + tile_group_id_t [NumTilesPerGroup-1:0] slave_north_req_ini_addr; + logic [NumTilesPerGroup-1:0] slave_north_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_north_req_wdata; + strb_t [NumTilesPerGroup-1:0] slave_north_req_be; + logic [NumTilesPerGroup-1:0] slave_north_resp_valid; + logic [NumTilesPerGroup-1:0] slave_north_resp_ready; + tile_group_id_t [NumTilesPerGroup-1:0] slave_north_resp_ini_addr; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_north_resp_rdata; + + for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_north_connections + assign master_north_req_valid[t] = tcdm_master_north_req_valid[t]; + assign master_north_req_tgt_addr[t] = tcdm_master_north_req[t].tgt_addr; + assign master_north_req_wen[t] = tcdm_master_north_req[t].wen; + assign master_north_req_wdata[t] = tcdm_master_north_req[t].wdata; + assign master_north_req_be[t] = tcdm_master_north_req[t].be; + assign tcdm_master_north_req_ready[t] = master_north_req_ready[t]; + assign tcdm_master_north_req_valid_o[t] = slave_north_req_valid[t]; + assign tcdm_master_north_req_s[t].tgt_addr = slave_north_req_tgt_addr[t]; + assign tcdm_master_north_req_s[t].ini_addr = slave_north_req_ini_addr[t]; + assign tcdm_master_north_req_s[t].wen = slave_north_req_wen[t]; + assign tcdm_master_north_req_s[t].wdata = slave_north_req_wdata[t]; + assign tcdm_master_north_req_s[t].be = slave_north_req_be[t]; + assign slave_north_req_ready[t] = tcdm_master_north_req_ready_i[t]; + assign slave_north_resp_valid[t] = tcdm_slave_north_resp_valid[t]; + assign slave_north_resp_ini_addr[t] = tcdm_slave_north_resp[t].ini_addr; + assign slave_north_resp_rdata[t] = tcdm_slave_north_resp[t].rdata; + assign tcdm_slave_north_resp_ready[t] = slave_north_resp_ready[t]; + assign tcdm_slave_north_resp_valid_o[t] = master_north_resp_valid[t]; + assign tcdm_slave_north_resp_s[t].rdata = master_north_resp_rdata[t]; + assign master_north_resp_ready[t] = tcdm_slave_north_resp_ready_i[t]; + end + + variable_latency_interconnect #( + .NumIn (NumTilesPerGroup ), + .NumOut (NumTilesPerGroup ), + .AddrWidth (TCDMAddrWidth ), + .DataWidth ($bits(tcdm_payload_t) ), + .BeWidth (DataWidth/8 ), + .ByteOffWidth (0 ), + .AddrMemWidth (TCDMAddrMemWidth + idx_width(NumBanksPerTile)), + .Topology (tcdm_interconnect_pkg::LIC ), + .AxiVldRdy (1'b1 ), + .SpillRegisterReq (64'b1 ), + .SpillRegisterResp (64'b1 ), + .FallThroughRegister(1'b1 ) + ) i_north_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_valid_i (master_north_req_valid ), + .req_ready_o (master_north_req_ready ), + .req_tgt_addr_i (master_north_req_tgt_addr), + .req_wen_i (master_north_req_wen ), + .req_wdata_i (master_north_req_wdata ), + .req_be_i (master_north_req_be ), + .resp_valid_o (master_north_resp_valid ), + .resp_ready_i (master_north_resp_ready ), + .resp_rdata_o (master_north_resp_rdata ), + .req_valid_o (slave_north_req_valid ), + .req_ready_i (slave_north_req_ready ), + .req_be_o (slave_north_req_be ), + .req_wdata_o (slave_north_req_wdata ), + .req_wen_o (slave_north_req_wen ), + .req_ini_addr_o (slave_north_req_ini_addr ), + .req_tgt_addr_o (slave_north_req_tgt_addr ), + .resp_ini_addr_i(slave_north_resp_ini_addr), + .resp_rdata_i (slave_north_resp_rdata ), + .resp_valid_i (slave_north_resp_valid ), + .resp_ready_o (slave_north_resp_ready ) + ); + + /**************************** + * Northeast Interconnect * + ****************************/ + + logic [NumTilesPerGroup-1:0] master_northeast_req_valid; + logic [NumTilesPerGroup-1:0] master_northeast_req_ready; + tcdm_addr_t [NumTilesPerGroup-1:0] master_northeast_req_tgt_addr; + logic [NumTilesPerGroup-1:0] master_northeast_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] master_northeast_req_wdata; + strb_t [NumTilesPerGroup-1:0] master_northeast_req_be; + logic [NumTilesPerGroup-1:0] master_northeast_resp_valid; + logic [NumTilesPerGroup-1:0] master_northeast_resp_ready; + tcdm_payload_t [NumTilesPerGroup-1:0] master_northeast_resp_rdata; + logic [NumTilesPerGroup-1:0] slave_northeast_req_valid; + logic [NumTilesPerGroup-1:0] slave_northeast_req_ready; + tile_addr_t [NumTilesPerGroup-1:0] slave_northeast_req_tgt_addr; + tile_group_id_t [NumTilesPerGroup-1:0] slave_northeast_req_ini_addr; + logic [NumTilesPerGroup-1:0] slave_northeast_req_wen; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_northeast_req_wdata; + strb_t [NumTilesPerGroup-1:0] slave_northeast_req_be; + logic [NumTilesPerGroup-1:0] slave_northeast_resp_valid; + logic [NumTilesPerGroup-1:0] slave_northeast_resp_ready; + tile_group_id_t [NumTilesPerGroup-1:0] slave_northeast_resp_ini_addr; + tcdm_payload_t [NumTilesPerGroup-1:0] slave_northeast_resp_rdata; + + for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_northeast_connections + assign master_northeast_req_valid[t] = tcdm_master_northeast_req_valid[t]; + assign master_northeast_req_tgt_addr[t] = tcdm_master_northeast_req[t].tgt_addr; + assign master_northeast_req_wen[t] = tcdm_master_northeast_req[t].wen; + assign master_northeast_req_wdata[t] = tcdm_master_northeast_req[t].wdata; + assign master_northeast_req_be[t] = tcdm_master_northeast_req[t].be; + assign tcdm_master_northeast_req_ready[t] = master_northeast_req_ready[t]; + assign tcdm_master_northeast_req_valid_o[t] = slave_northeast_req_valid[t]; + assign tcdm_master_northeast_req_s[t].tgt_addr = slave_northeast_req_tgt_addr[t]; + assign tcdm_master_northeast_req_s[t].ini_addr = slave_northeast_req_ini_addr[t]; + assign tcdm_master_northeast_req_s[t].wen = slave_northeast_req_wen[t]; + assign tcdm_master_northeast_req_s[t].wdata = slave_northeast_req_wdata[t]; + assign tcdm_master_northeast_req_s[t].be = slave_northeast_req_be[t]; + assign slave_northeast_req_ready[t] = tcdm_master_northeast_req_ready_i[t]; + assign slave_northeast_resp_valid[t] = tcdm_slave_northeast_resp_valid[t]; + assign slave_northeast_resp_ini_addr[t] = tcdm_slave_northeast_resp[t].ini_addr; + assign slave_northeast_resp_rdata[t] = tcdm_slave_northeast_resp[t].rdata; + assign tcdm_slave_northeast_resp_ready[t] = slave_northeast_resp_ready[t]; + assign tcdm_slave_northeast_resp_valid_o[t] = master_northeast_resp_valid[t]; + assign tcdm_slave_northeast_resp_s[t].rdata = master_northeast_resp_rdata[t]; + assign master_northeast_resp_ready[t] = tcdm_slave_northeast_resp_ready_i[t]; + end + + variable_latency_interconnect #( + .NumIn (NumTilesPerGroup ), + .NumOut (NumTilesPerGroup ), + .AddrWidth (TCDMAddrWidth ), + .DataWidth ($bits(tcdm_payload_t) ), + .BeWidth (DataWidth/8 ), + .ByteOffWidth (0 ), + .AddrMemWidth (TCDMAddrMemWidth + idx_width(NumBanksPerTile)), + .Topology (tcdm_interconnect_pkg::LIC ), + .AxiVldRdy (1'b1 ), + .SpillRegisterReq (64'b1 ), + .SpillRegisterResp (64'b1 ), + .FallThroughRegister(1'b1 ) + ) i_northeast_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_valid_i (master_northeast_req_valid ), + .req_ready_o (master_northeast_req_ready ), + .req_tgt_addr_i (master_northeast_req_tgt_addr), + .req_wen_i (master_northeast_req_wen ), + .req_wdata_i (master_northeast_req_wdata ), + .req_be_i (master_northeast_req_be ), + .resp_valid_o (master_northeast_resp_valid ), + .resp_ready_i (master_northeast_resp_ready ), + .resp_rdata_o (master_northeast_resp_rdata ), + .resp_ini_addr_i(slave_northeast_resp_ini_addr), + .resp_rdata_i (slave_northeast_resp_rdata ), + .resp_valid_i (slave_northeast_resp_valid ), + .resp_ready_o (slave_northeast_resp_ready ), + .req_valid_o (slave_northeast_req_valid ), + .req_ready_i (slave_northeast_req_ready ), + .req_be_o (slave_northeast_req_be ), + .req_wdata_o (slave_northeast_req_wdata ), + .req_wen_o (slave_northeast_req_wen ), + .req_ini_addr_o (slave_northeast_req_ini_addr ), + .req_tgt_addr_o (slave_northeast_req_tgt_addr ) + ); + + /********************** + * AXI Interconnect * + **********************/ + + axi_hier_interco #( + .NumSlvPorts (NumTilesPerGroup), + .NumPortsPerMux (4 ), + .EnableCache (1'b0 ), + .AddrWidth (AddrWidth ), + .DataWidth (AxiDataWidth ), + .SlvIdWidth (AxiTileIdWidth ), + .MstIdWidth (AxiTileIdWidth ), + .UserWidth (1 ), + .slv_req_t (axi_tile_req_t ), + .slv_resp_t (axi_tile_resp_t ), + .mst_req_t (axi_tile_req_t ), + .mst_resp_t (axi_tile_resp_t ) + ) i_axi_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .slv_req_i (axi_tile_req ), + .slv_resp_o (axi_tile_resp ), + .mst_req_o (axi_mst_req_o ), + .mst_resp_i (axi_mst_resp_i) + ); + + /********************* + * Bypass Channels * + *********************/ + + assign tcdm_master_bypass_req_o = tcdm_slave_bypass_req_i; + assign tcdm_master_bypass_req_valid_o = tcdm_slave_bypass_req_valid_i; + assign tcdm_slave_bypass_req_ready_o = tcdm_master_bypass_req_ready_i; + assign tcdm_slave_bypass_resp_o = tcdm_master_bypass_resp_i; + assign tcdm_slave_bypass_resp_valid_o = tcdm_master_bypass_resp_valid_i; + assign tcdm_master_bypass_resp_ready_o = tcdm_slave_bypass_resp_ready_i; + +endmodule: mempool_group diff --git a/flow/designs/src/mempool_group/rtl/mempool_pkg.sv b/flow/designs/src/mempool_group/rtl/mempool_pkg.sv new file mode 100644 index 0000000000..5b112724e9 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/mempool_pkg.sv @@ -0,0 +1,187 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// csamudra : 12/24 edited line 18 localparam integer ...NumCores ..16..endif; earlier it was 0 instead of 16 +// csamudra : 12/24 edited line 19 localparam integer ...NumCoresPerTile..4..endif; earlier it was 0 instead of 4 +package mempool_pkg; + + import snitch_pkg::MetaIdWidth; + import cf_math_pkg::idx_width; + + /********************* + * TILE PARAMETERS * + *********************/ + + `include "axi/assign.svh" + `include "axi/typedef.svh" + + localparam integer unsigned NumCores = `ifdef NUM_CORES `NUM_CORES `else 16 `endif; + localparam integer unsigned NumCoresPerTile = `ifdef NUM_CORES_PER_TILE `NUM_CORES_PER_TILE `else 4 `endif; + localparam integer unsigned NumGroups = 4; + localparam integer unsigned NumTiles = NumCores / NumCoresPerTile; + localparam integer unsigned NumTilesPerGroup = NumTiles / NumGroups; + localparam integer unsigned NumCoresPerGroup = NumCores / NumGroups; + localparam integer unsigned NumCoresPerCache = NumCoresPerTile; + localparam integer unsigned AxiCoreIdWidth = 1; + localparam integer unsigned AxiTileIdWidth = AxiCoreIdWidth+1; // + 1 for cache + localparam integer unsigned AxiDataWidth = 128; + localparam integer unsigned AxiLiteDataWidth = 32; + + /*********************** + * MEMORY PARAMETERS * + ***********************/ + + localparam integer unsigned AddrWidth = 32; + localparam integer unsigned DataWidth = 32; + localparam integer unsigned BeWidth = DataWidth / 8; + localparam integer unsigned ByteOffset = $clog2(BeWidth); + localparam integer unsigned BankingFactor = 4; + localparam bit LrScEnable = 1'b1; + localparam integer unsigned TCDMSizePerBank = 1024; // [B] + localparam integer unsigned NumBanks = NumCores * BankingFactor; + localparam integer unsigned NumBanksPerTile = NumBanks / NumTiles; + localparam integer unsigned NumBanksPerGroup = NumBanks / NumGroups; + localparam integer unsigned TCDMAddrMemWidth = $clog2(TCDMSizePerBank / mempool_pkg::BeWidth); + localparam integer unsigned TCDMAddrWidth = TCDMAddrMemWidth + idx_width(NumBanksPerGroup); + localparam integer unsigned L2Size = `ifdef L2_SIZE `L2_SIZE `else 0 `endif; // [B] + localparam integer unsigned L2BeWidth = AxiDataWidth/8; + localparam integer unsigned L2ByteOffset = $clog2(L2BeWidth); + + typedef logic [AxiCoreIdWidth-1:0] axi_core_id_t; + typedef logic [AxiTileIdWidth-1:0] axi_tile_id_t; + typedef logic [AxiDataWidth-1:0] axi_data_t; + typedef logic [AxiDataWidth/8-1:0] axi_strb_t; + typedef logic [AxiLiteDataWidth-1:0] axi_lite_data_t; + typedef logic [AxiLiteDataWidth/8-1:0] axi_lite_strb_t; + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [BeWidth-1:0] strb_t; + + localparam NumSystemXbarMasters = NumGroups + 1; + localparam AxiSystemIdWidth = $clog2(NumSystemXbarMasters) + AxiTileIdWidth; + typedef logic [AxiSystemIdWidth-1:0] axi_system_id_t; + + localparam NumTestbenchXbarMasters = 1; + localparam AxiTestbenchIdWidth = $clog2(NumTestbenchXbarMasters) + AxiSystemIdWidth; + typedef logic [AxiTestbenchIdWidth-1:0] axi_tb_id_t; + + + `AXI_TYPEDEF_AW_CHAN_T(axi_core_aw_t, addr_t, axi_core_id_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_core_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_B_CHAN_T(axi_core_b_t, axi_core_id_t, logic); + `AXI_TYPEDEF_AR_CHAN_T(axi_core_ar_t, addr_t, axi_core_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_core_r_t, axi_data_t, axi_core_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_core_req_t, axi_core_aw_t, axi_core_w_t, axi_core_ar_t); + `AXI_TYPEDEF_RESP_T(axi_core_resp_t, axi_core_b_t, axi_core_r_t ); + + `AXI_TYPEDEF_AW_CHAN_T(axi_tile_aw_t, addr_t, axi_tile_id_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_tile_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_B_CHAN_T(axi_tile_b_t, axi_tile_id_t, logic); + `AXI_TYPEDEF_AR_CHAN_T(axi_tile_ar_t, addr_t, axi_tile_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_tile_r_t, axi_data_t, axi_tile_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_tile_req_t, axi_tile_aw_t, axi_tile_w_t, axi_tile_ar_t); + `AXI_TYPEDEF_RESP_T(axi_tile_resp_t, axi_tile_b_t, axi_tile_r_t ); + + `AXI_TYPEDEF_AW_CHAN_T(axi_system_aw_t, addr_t, axi_system_id_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_system_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_B_CHAN_T(axi_system_b_t, axi_system_id_t, logic); + `AXI_TYPEDEF_AR_CHAN_T(axi_system_ar_t, addr_t, axi_system_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_system_r_t, axi_data_t, axi_system_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_system_req_t, axi_system_aw_t, axi_system_w_t, axi_system_ar_t); + `AXI_TYPEDEF_RESP_T(axi_system_resp_t, axi_system_b_t, axi_system_r_t); + + // AXI to ctrl registers + `AXI_TYPEDEF_W_CHAN_T(axi_ctrl_w_t, axi_lite_data_t, axi_lite_strb_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_ctrl_r_t, axi_lite_data_t, axi_system_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_ctrl_req_t, axi_system_aw_t, axi_ctrl_w_t, axi_system_ar_t); + `AXI_TYPEDEF_RESP_T(axi_ctrl_resp_t, axi_system_b_t, axi_ctrl_r_t); + + `AXI_TYPEDEF_AW_CHAN_T(axi_tb_aw_t, addr_t, axi_tb_id_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_tb_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_B_CHAN_T(axi_tb_b_t, axi_tb_id_t, logic); + `AXI_TYPEDEF_AR_CHAN_T(axi_tb_ar_t, addr_t, axi_tb_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_tb_r_t, axi_data_t, axi_tb_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_tb_req_t, axi_tb_aw_t, axi_tb_w_t, axi_tb_ar_t); + `AXI_TYPEDEF_RESP_T(axi_tb_resp_t, axi_tb_b_t, axi_tb_r_t); + + `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_slv_aw_t, addr_t) + `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_slv_w_t, axi_lite_data_t, axi_lite_strb_t) + `AXI_LITE_TYPEDEF_B_CHAN_T(axi_lite_slv_b_t) + `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_slv_ar_t, addr_t) + `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_slv_r_t, axi_lite_data_t) + `AXI_LITE_TYPEDEF_REQ_T(axi_lite_slv_req_t, axi_lite_slv_aw_t, axi_lite_slv_w_t, axi_lite_slv_ar_t) + `AXI_LITE_TYPEDEF_RESP_T(axi_lite_slv_resp_t, axi_lite_slv_b_t, axi_lite_slv_r_t) + + /*********************** + * INSTRUCTION CACHE * + ***********************/ + + localparam int unsigned ICacheSizeByte = 512 * NumCoresPerCache; // Total Size of instruction cache in bytes + localparam int unsigned ICacheSets = NumCoresPerCache / 2; // Number of sets + localparam int unsigned ICacheLineWidth = 32 * 2 * NumCoresPerCache; // Size of each cache line in bits, + + /********************************** + * TCDM INTERCONNECT PARAMETERS * + **********************************/ + + typedef logic [TCDMAddrWidth-1:0] tcdm_addr_t; + typedef logic [TCDMAddrMemWidth-1:0] bank_addr_t; + typedef logic [TCDMAddrMemWidth+idx_width(NumBanksPerTile)-1:0] tile_addr_t; + typedef logic [MetaIdWidth-1:0] meta_id_t; + typedef logic [idx_width(NumCoresPerTile)-1:0] tile_core_id_t; + typedef logic [idx_width(NumTilesPerGroup)-1:0] tile_group_id_t; + typedef logic [idx_width(NumGroups)-1:0] group_id_t; + typedef logic [3:0] amo_t; + + typedef struct packed { + meta_id_t meta_id; + tile_core_id_t core_id; + amo_t amo; + data_t data; + } tcdm_payload_t; + + typedef struct packed { + tcdm_payload_t wdata; + logic wen; + strb_t be; + tcdm_addr_t tgt_addr; + } tcdm_master_req_t; + + typedef struct packed { + tcdm_payload_t rdata; + } tcdm_master_resp_t; + + typedef struct packed { + tcdm_payload_t wdata; + logic wen; + strb_t be; + tile_addr_t tgt_addr; + tile_group_id_t ini_addr; + } tcdm_slave_req_t; + + typedef struct packed { + tcdm_payload_t rdata; + tile_group_id_t ini_addr; + } tcdm_slave_resp_t; + + /***************** + * ADDRESS MAP * + *****************/ + + // Size in bytes of memory that is sequentially addressable per tile + localparam int unsigned SeqMemSizePerTile = NumCoresPerTile*1024; // 1 KiB + + typedef struct packed { + int unsigned slave_idx; + addr_t mask; + addr_t value; + } address_map_t; + + /*********************** + * TRAFFIC GENERATOR * + ***********************/ + + // Replaces core with a traffic generator + parameter bit TrafficGeneration = `ifdef TRAFFIC_GEN `TRAFFIC_GEN `else 0 `endif; + +endpackage : mempool_pkg diff --git a/flow/designs/src/mempool_group/rtl/mempool_tile.sv b/flow/designs/src/mempool_group/rtl/mempool_tile.sv new file mode 100644 index 0000000000..0c25e90358 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/mempool_tile.sv @@ -0,0 +1,971 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + + +module mempool_tile + import mempool_pkg::*; + import cf_math_pkg::idx_width; +#( + // TCDM + parameter addr_t TCDMBaseAddr = 32'b0, + // Boot address + parameter logic [31:0] BootAddr = 32'h0000_1000, + // Dependent parameters. DO NOT CHANGE. + parameter int unsigned NumCaches = NumCoresPerTile / NumCoresPerCache +) ( + // Clock and reset + input logic clk_i, + input logic rst_ni, + // Scan chain + input logic scan_enable_i, + input logic scan_data_i, + output logic scan_data_o, + // Tile ID + input logic [idx_width(NumTiles)-1:0] tile_id_i, + // TCDM Master interfaces + output tcdm_master_req_t [NumGroups-1:0] tcdm_master_req_o, + output logic [NumGroups-1:0] tcdm_master_req_valid_o, + input logic [NumGroups-1:0] tcdm_master_req_ready_i, + input tcdm_master_resp_t [NumGroups-1:0] tcdm_master_resp_i, + input logic [NumGroups-1:0] tcdm_master_resp_valid_i, + output logic [NumGroups-1:0] tcdm_master_resp_ready_o, + // TCDM slave interfaces + input tcdm_slave_req_t [NumGroups-1:0] tcdm_slave_req_i, + input logic [NumGroups-1:0] tcdm_slave_req_valid_i, + output logic [NumGroups-1:0] tcdm_slave_req_ready_o, + output tcdm_slave_resp_t [NumGroups-1:0] tcdm_slave_resp_o, + output logic [NumGroups-1:0] tcdm_slave_resp_valid_o, + input logic [NumGroups-1:0] tcdm_slave_resp_ready_i, + // AXI Interface + output axi_tile_req_t axi_mst_req_o, + input axi_tile_resp_t axi_mst_resp_i, + // Wake up interface + input logic [NumCoresPerTile-1:0] wake_up_i +); + + /**************** + * Includes * + ****************/ +//the below line includes register definitions --> not sure why this is required, why do we have such a file ? + `include "common_cells/registers.svh" + + /***************** + * Definitions * + *****************/ + + import snitch_pkg::dreq_t; + import snitch_pkg::dresp_t; + + typedef logic [idx_width(NumGroups)-1:0] group_id_t; + + // TCDM Memory Region + localparam addr_t TCDMSize = NumBanks * TCDMSizePerBank; + localparam addr_t TCDMMask = ~(TCDMSize - 1); + + // Local interconnect address width + typedef logic [idx_width(NumCoresPerTile + NumGroups)-1:0] local_req_interco_addr_t; + + // Group ID + logic [idx_width(NumGroups)-1:0] group_id; + if (NumGroups != 1) begin: gen_group_id + assign group_id = tile_id_i[$clog2(NumTiles)-1 -: $clog2(NumGroups)]; + end else begin: gen_group_id + assign group_id = '0; + end: gen_group_id + + /*********** + * Cores * + ***********/ + + // Instruction interfaces + addr_t [NumCaches-1:0][NumCoresPerCache-1:0] snitch_inst_addr; + data_t [NumCaches-1:0][NumCoresPerCache-1:0] snitch_inst_data; + logic [NumCaches-1:0][NumCoresPerCache-1:0] snitch_inst_valid; + logic [NumCaches-1:0][NumCoresPerCache-1:0] snitch_inst_ready; + + // Data interfaces + addr_t [NumCoresPerTile-1:0] snitch_data_qaddr; + logic [NumCoresPerTile-1:0] snitch_data_qwrite; + amo_t [NumCoresPerTile-1:0] snitch_data_qamo; + data_t [NumCoresPerTile-1:0] snitch_data_qdata; + strb_t [NumCoresPerTile-1:0] snitch_data_qstrb; + meta_id_t [NumCoresPerTile-1:0] snitch_data_qid; + logic [NumCoresPerTile-1:0] snitch_data_qvalid; + logic [NumCoresPerTile-1:0] snitch_data_qready; + data_t [NumCoresPerTile-1:0] snitch_data_pdata; + logic [NumCoresPerTile-1:0] snitch_data_perror; + meta_id_t [NumCoresPerTile-1:0] snitch_data_pid; + logic [NumCoresPerTile-1:0] snitch_data_pvalid; + logic [NumCoresPerTile-1:0] snitch_data_pready; + + for (genvar c = 0; unsigned'(c) < NumCoresPerTile; c++) begin: gen_cores + logic [31:0] hart_id; + assign hart_id = {unsigned'(tile_id_i), c[idx_width(NumCoresPerTile)-1:0]}; + + if (!TrafficGeneration) begin: gen_mempool_cc + mempool_cc #( + .BootAddr (BootAddr) + ) riscv_core ( + .clk_i (clk_i ), + .rst_i (!rst_ni ), + .hart_id_i (hart_id ), + // IMEM Port + .inst_addr_o (snitch_inst_addr[c/NumCoresPerCache][c%NumCoresPerCache] ), + .inst_data_i (snitch_inst_data[c/NumCoresPerCache][c%NumCoresPerCache] ), + .inst_valid_o (snitch_inst_valid[c/NumCoresPerCache][c%NumCoresPerCache]), + .inst_ready_i (snitch_inst_ready[c/NumCoresPerCache][c%NumCoresPerCache]), + // Data Ports + .data_qaddr_o (snitch_data_qaddr[c] ), + .data_qwrite_o (snitch_data_qwrite[c] ), + .data_qamo_o (snitch_data_qamo[c] ), + .data_qdata_o (snitch_data_qdata[c] ), + .data_qstrb_o (snitch_data_qstrb[c] ), + .data_qid_o (snitch_data_qid[c] ), + .data_qvalid_o (snitch_data_qvalid[c] ), + .data_qready_i (snitch_data_qready[c] ), + .data_pdata_i (snitch_data_pdata[c] ), + .data_perror_i (snitch_data_perror[c] ), + .data_pid_i (snitch_data_pid[c] ), + .data_pvalid_i (snitch_data_pvalid[c] ), + .data_pready_o (snitch_data_pready[c] ), + .wake_up_sync_i(wake_up_i[c] ), + // Core Events + .core_events_o (/* Unused */ ) + ); + end else begin + assign snitch_data_qaddr[c] = '0; + assign snitch_data_qwrite[c] = '0; + assign snitch_data_qamo[c] = '0; + assign snitch_data_qdata[c] = '0; + assign snitch_data_qstrb[c] = '0; + assign snitch_data_qid[c] = '0; + assign snitch_data_qvalid[c] = '0; + assign snitch_data_pready[c] = '0; + assign snitch_inst_addr[c/NumCoresPerCache][c%NumCoresPerCache] = '0; + assign snitch_inst_valid[c/NumCoresPerCache][c%NumCoresPerCache] = '0; + end + end + + /*********************** + * Instruction Cache * + ***********************/ + // Instruction interface + addr_t [NumCaches-1:0] refill_qaddr; + logic [NumCaches-1:0][7:0] refill_qlen; + logic [NumCaches-1:0] refill_qvalid; + logic [NumCaches-1:0] refill_qready; + logic [NumCaches-1:0][AxiDataWidth-1:0] refill_pdata; + logic [NumCaches-1:0] refill_perror; + logic [NumCaches-1:0] refill_pvalid; + logic [NumCaches-1:0] refill_plast; + logic [NumCaches-1:0] refill_pready; + + for (genvar c = 0; unsigned'(c) < NumCaches; c++) begin: gen_caches + snitch_icache #( + .NR_FETCH_PORTS (NumCoresPerCache ), + /// Cache Line Width + .L0_LINE_COUNT (4 ), + .LINE_WIDTH (ICacheLineWidth ), + .LINE_COUNT (ICacheSizeByte / (ICacheSets * ICacheLineWidth / 8) ), + .SET_COUNT (ICacheSets ), + .FETCH_AW (AddrWidth ), + .FETCH_DW (DataWidth ), + .FILL_AW (AddrWidth ), + .FILL_DW (AxiDataWidth ), + .L1_TAG_SCM (1 ), + /// Make the early cache latch-based. This reduces latency at the cost of + /// increased combinatorial path lengths and the hassle of having latches in + /// the design. + .EARLY_LATCH (1 ), + .L0_EARLY_TAG_WIDTH (11 ), + .ISO_CROSSING (0 ) + ) i_snitch_icache ( + .clk_i (clk_i ), + .clk_d2_i (clk_i ), + .rst_ni (rst_ni ), + .enable_prefetching_i (snitch_inst_valid[c] ), + .icache_events_o (/* Unused */ ), + .flush_valid_i (1'b0 ), + .flush_ready_o (/* Unused */ ), + .inst_addr_i (snitch_inst_addr[c] ), + .inst_data_o (snitch_inst_data[c] ), + .inst_cacheable_i ({NumCoresPerCache{1'b1}}), + .inst_valid_i (snitch_inst_valid[c] ), + .inst_ready_o (snitch_inst_ready[c] ), + .inst_error_o (/* Unused */ ), + .refill_qaddr_o (refill_qaddr[c] ), + .refill_qlen_o (refill_qlen[c] ), + .refill_qvalid_o (refill_qvalid[c] ), + .refill_qready_i (refill_qready[c] ), + .refill_pdata_i (refill_pdata[c] ), + .refill_perror_i (refill_perror[c] ), + .refill_pvalid_i (refill_pvalid[c] ), + .refill_plast_i (refill_plast[c] ), + .refill_pready_o (refill_pready[c] ) + ); + end + + /****************** + * Memory Banks * + ******************/ + + // Bank metadata + typedef struct packed { + local_req_interco_addr_t ini_addr; + meta_id_t meta_id; + tile_group_id_t tile_id; + tile_core_id_t core_id; + } bank_metadata_t; + + // Memory interfaces + logic [NumBanksPerTile-1:0] bank_req_valid; + logic [NumBanksPerTile-1:0] bank_req_ready; + local_req_interco_addr_t [NumBanksPerTile-1:0] bank_req_ini_addr; + tcdm_slave_req_t [NumBanksPerTile-1:0] bank_req_payload; + logic [NumBanksPerTile-1:0] bank_resp_valid; + logic [NumBanksPerTile-1:0] bank_resp_ready; + tcdm_slave_resp_t [NumBanksPerTile-1:0] bank_resp_payload; + local_req_interco_addr_t [NumBanksPerTile-1:0] bank_resp_ini_addr; + + for (genvar b = 0; unsigned'(b) < NumBanksPerTile; b++) begin: gen_banks + bank_metadata_t meta_in; + bank_metadata_t meta_out; + logic req_valid; + logic req_write; + bank_addr_t req_addr; + data_t req_wdata; + data_t resp_rdata; + strb_t req_be; + + // Un/Pack metadata + assign meta_in = '{ + ini_addr : bank_req_ini_addr[b], + meta_id : bank_req_payload[b].wdata.meta_id, + core_id : bank_req_payload[b].wdata.core_id, + tile_id : bank_req_payload[b].ini_addr + }; + assign bank_resp_ini_addr[b] = meta_out.ini_addr; + assign bank_resp_payload[b].rdata.meta_id = meta_out.meta_id; + assign bank_resp_payload[b].ini_addr = meta_out.tile_id; + assign bank_resp_payload[b].rdata.core_id = meta_out.core_id; + assign bank_resp_payload[b].rdata.amo = '0; // Don't care + + tcdm_adapter #( + .AddrWidth (TCDMAddrMemWidth), + .DataWidth (DataWidth ), + .metadata_t (bank_metadata_t ), + .LrScEnable (LrScEnable ), + .RegisterAmo(1'b0 ) + ) i_tcdm_adapter ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .in_valid_i (bank_req_valid[b] ), + .in_ready_o (bank_req_ready[b] ), + .in_address_i(bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth]), + .in_amo_i (bank_req_payload[b].wdata.amo ), + .in_write_i (bank_req_payload[b].wen ), + .in_wdata_i (bank_req_payload[b].wdata.data ), + .in_meta_i (meta_in ), + .in_be_i (bank_req_payload[b].be ), + .in_valid_o (bank_resp_valid[b] ), + .in_ready_i (bank_resp_ready[b] ), + .in_rdata_o (bank_resp_payload[b].rdata.data ), + .in_meta_o (meta_out ), + .out_req_o (req_valid ), + .out_add_o (req_addr ), + .out_write_o (req_write ), + .out_wdata_o (req_wdata ), + .out_be_o (req_be ), + .out_rdata_i (resp_rdata ) + ); + + // Bank + tc_sram #( + .DataWidth(DataWidth ), + .NumWords (2**TCDMAddrMemWidth), + .NumPorts (1 ) + ) mem_bank ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_i (req_valid ), + .we_i (req_write ), + .addr_i (req_addr ), + .wdata_i(req_wdata ), + .be_i (req_be ), + .rdata_o(resp_rdata) + ); + end + + /*************** + * Registers * + ***************/ + + // These are required to break dependencies between request and response, establishing a correct + // valid/ready handshake. + tcdm_master_req_t [NumGroups-1:0] prereg_tcdm_master_req; + logic [NumGroups-1:0] prereg_tcdm_master_req_valid; + logic [NumGroups-1:0] prereg_tcdm_master_req_ready; + tcdm_slave_req_t [NumGroups-1:0] postreg_tcdm_slave_req; + logic [NumGroups-1:0] postreg_tcdm_slave_req_valid; + logic [NumGroups-1:0] postreg_tcdm_slave_req_ready; + tcdm_slave_resp_t [NumGroups-1:0] prereg_tcdm_slave_resp; + logic [NumGroups-1:0] prereg_tcdm_slave_resp_valid; + logic [NumGroups-1:0] prereg_tcdm_slave_resp_ready; + tcdm_master_resp_t [NumGroups-1:0] postreg_tcdm_master_resp; + tile_core_id_t [NumGroups-1:0] postreg_tcdm_master_resp_ini_sel; + logic [NumGroups-1:0] postreg_tcdm_master_resp_valid; + logic [NumGroups-1:0] postreg_tcdm_master_resp_ready; + + // Break paths between request and response with registers + for (genvar h = 0; unsigned'(h) < NumGroups; h++) begin: gen_tcdm_registers + spill_register #( + .T(tcdm_master_req_t) + ) i_tcdm_master_req_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .data_i (prereg_tcdm_master_req[h] ), + .valid_i(prereg_tcdm_master_req_valid[h]), + .ready_o(prereg_tcdm_master_req_ready[h]), + .data_o (tcdm_master_req_o[h] ), + .valid_o(tcdm_master_req_valid_o[h] ), + .ready_i(tcdm_master_req_ready_i[h] ) + ); + + fall_through_register #( + .T(tcdm_master_resp_t) + ) i_tcdm_master_resp_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .clr_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (tcdm_master_resp_i[h] ), + .valid_i (tcdm_master_resp_valid_i[h] ), + .ready_o (tcdm_master_resp_ready_o[h] ), + .data_o (postreg_tcdm_master_resp[h] ), + .valid_o (postreg_tcdm_master_resp_valid[h]), + .ready_i (postreg_tcdm_master_resp_ready[h]) + ); + + // Helper signal to drive the remote response interconnect + assign postreg_tcdm_master_resp_ini_sel[h] = postreg_tcdm_master_resp[h].rdata.core_id; + + fall_through_register #( + .T(tcdm_slave_req_t) + ) i_tcdm_slave_req_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .clr_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (tcdm_slave_req_i[h] ), + .valid_i (tcdm_slave_req_valid_i[h] ), + .ready_o (tcdm_slave_req_ready_o[h] ), + .data_o (postreg_tcdm_slave_req[h] ), + .valid_o (postreg_tcdm_slave_req_valid[h]), + .ready_i (postreg_tcdm_slave_req_ready[h]) + ); + + spill_register #( + .T(tcdm_slave_resp_t) + ) i_tcdm_slave_resp_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .data_i (prereg_tcdm_slave_resp[h] ), + .valid_i(prereg_tcdm_slave_resp_valid[h]), + .ready_o(prereg_tcdm_slave_resp_ready[h]), + .data_o (tcdm_slave_resp_o[h] ), + .valid_o(tcdm_slave_resp_valid_o[h] ), + .ready_i(tcdm_slave_resp_ready_i[h] ) + ); + end: gen_tcdm_registers + + /**************************** + * Remote Interconnects * + ****************************/ + + tcdm_master_req_t [NumCoresPerTile-1:0] remote_req_interco; + logic [NumCoresPerTile-1:0] remote_req_interco_valid; + logic [NumCoresPerTile-1:0] remote_req_interco_ready; + group_id_t [NumCoresPerTile-1:0] remote_req_interco_tgt_sel; + tcdm_master_resp_t [NumCoresPerTile-1:0] remote_resp_interco; + logic [NumCoresPerTile-1:0] remote_resp_interco_valid; + logic [NumCoresPerTile-1:0] remote_resp_interco_ready; + + stream_xbar #( + .NumInp (NumCoresPerTile ), + .NumOut (NumGroups ), + .payload_t(tcdm_master_req_t) + ) i_remote_req_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + // External priority flag + .rr_i ('0 ), + // Master + .data_i (remote_req_interco ), + .valid_i(remote_req_interco_valid ), + .ready_o(remote_req_interco_ready ), + .sel_i (remote_req_interco_tgt_sel ), + // Slave + .data_o (prereg_tcdm_master_req ), + .valid_o(prereg_tcdm_master_req_valid), + .ready_i(prereg_tcdm_master_req_ready), + .idx_o (/* Unused */ ) + ); + + stream_xbar #( + .NumInp (NumGroups ), + .NumOut (NumCoresPerTile ), + .payload_t(tcdm_master_resp_t) + ) i_remote_resp_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + // External priority flag + .rr_i ('0 ), + // Master + .data_i (postreg_tcdm_master_resp ), + .valid_i(postreg_tcdm_master_resp_valid ), + .ready_o(postreg_tcdm_master_resp_ready ), + .sel_i (postreg_tcdm_master_resp_ini_sel), + // Slave + .data_o (remote_resp_interco ), + .valid_o(remote_resp_interco_valid ), + .ready_i(remote_resp_interco_ready ), + .idx_o (/* Unused */ ) + ); + + /********************** + * Local Intercos * + **********************/ + + logic [NumCoresPerTile-1:0] local_req_interco_valid; + logic [NumCoresPerTile-1:0] local_req_interco_ready; + tcdm_slave_req_t [NumCoresPerTile-1:0] local_req_interco_payload; + logic [NumCoresPerTile-1:0] local_resp_interco_valid; + logic [NumCoresPerTile-1:0] local_resp_interco_ready; + tcdm_slave_resp_t [NumCoresPerTile-1:0] local_resp_interco_payload; + + logic [NumCoresPerTile+NumGroups-1:0][idx_width(NumBanksPerTile)-1:0] local_req_interco_tgt_sel; + for (genvar j = 0; unsigned'(j) < NumCoresPerTile; j++) begin: gen_local_req_interco_tgt_sel_local + assign local_req_interco_tgt_sel[j] = local_req_interco_payload[j].tgt_addr[idx_width(NumBanksPerTile)-1:0]; + end: gen_local_req_interco_tgt_sel_local + for (genvar j = 0; unsigned'(j) < NumGroups; j++) begin: gen_local_req_interco_tgt_sel_remote + assign local_req_interco_tgt_sel[j + NumCoresPerTile] = postreg_tcdm_slave_req[j].tgt_addr[idx_width(NumBanksPerTile)-1:0]; + end: gen_local_req_interco_tgt_sel_remote + + stream_xbar #( + .NumInp (NumCoresPerTile+NumGroups), + .NumOut (NumBanksPerTile ), + .payload_t(tcdm_slave_req_t ) + ) i_local_req_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + // External priority flag + .rr_i ('0 ), + // Master + .data_i ({postreg_tcdm_slave_req, local_req_interco_payload} ), + .valid_i({postreg_tcdm_slave_req_valid, local_req_interco_valid}), + .ready_o({postreg_tcdm_slave_req_ready, local_req_interco_ready}), + .sel_i (local_req_interco_tgt_sel ), + // Slave + .data_o (bank_req_payload ), + .valid_o(bank_req_valid ), + .ready_i(bank_req_ready ), + .idx_o (bank_req_ini_addr ) + ); + + stream_xbar #( + .NumInp (NumBanksPerTile ), + .NumOut (NumCoresPerTile+NumGroups), + .payload_t(tcdm_slave_resp_t ) + ) i_local_resp_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + // External priority flag + .rr_i ('0 ), + // Master + .data_i (bank_resp_payload ), + .valid_i(bank_resp_valid ), + .ready_o(bank_resp_ready ), + .sel_i (bank_resp_ini_addr ), + // Slave + .data_o ({prereg_tcdm_slave_resp, local_resp_interco_payload} ), + .valid_o({prereg_tcdm_slave_resp_valid, local_resp_interco_valid}), + .ready_i({prereg_tcdm_slave_resp_ready, local_resp_interco_ready}), + .idx_o (/* Unused */ ) + ); + + /******************* + * Core De/mux * + *******************/ + + // SoC requests + dreq_t [NumCoresPerTile-1:0] soc_data_q; + logic [NumCoresPerTile-1:0] soc_data_qvalid; + logic [NumCoresPerTile-1:0] soc_data_qready; + dresp_t [NumCoresPerTile-1:0] soc_data_p; + logic [NumCoresPerTile-1:0] soc_data_pvalid; + logic [NumCoresPerTile-1:0] soc_data_pready; + + // Address map + typedef enum int unsigned { + TCDM_EXTERNAL = 0, TCDM_LOCAL, SOC + } addr_map_slave_t; + + address_map_t [2:0] mask_map; + assign mask_map = '{ + // Lowest priority: send request through the SoC port + '{slave_idx: SOC, + mask : '0, + value : '0 + }, + // Send request through the external TCDM port + '{slave_idx: TCDM_EXTERNAL, + mask : TCDMMask, + value : TCDMBaseAddr + }, + // Highest priority: send request through the local TCDM port + '{slave_idx: TCDM_LOCAL, + mask : TCDMMask | ({idx_width(NumTiles){1'b1}} << (ByteOffset + $clog2(NumBanksPerTile))), + value : TCDMBaseAddr | (tile_id_i << (ByteOffset + $clog2(NumBanksPerTile))) + } + }; + + for (genvar c = 0; c < NumCoresPerTile; c++) begin: gen_core_mux + // Remove tile index from local_req_interco_addr_int, since it will not be used for routing. + addr_t local_req_interco_addr_int; + assign local_req_interco_payload[c].tgt_addr = + tcdm_addr_t'({local_req_interco_addr_int[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTiles) +: TCDMAddrMemWidth], // Bank address + local_req_interco_addr_int[ByteOffset +: idx_width(NumBanksPerTile)]}); // Bank + + // Switch tile and bank indexes for correct upper level routing, and remove the group index + addr_t prescramble_tcdm_req_tgt_addr; + if (NumTilesPerGroup == 1) begin : gen_remote_req_interco_tgt_addr + assign remote_req_interco[c].tgt_addr = + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)]}); // Tile + end else begin : gen_remote_req_interco_tgt_addr + assign remote_req_interco[c].tgt_addr = + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)], // Bank + prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) +: $clog2(NumTilesPerGroup)]}); // Tile + end + if (NumGroups == 1) begin : gen_remote_req_interco_tgt_sel + assign remote_req_interco_tgt_sel[c] = 1'b0; + end else begin : gen_remote_req_interco_tgt_sel + // Output port depends on both the target and initiator group + assign remote_req_interco_tgt_sel[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroups)]) ^ group_id; + end + + // We don't care about these + assign local_req_interco_payload[c].wdata.core_id = '0; + assign local_req_interco_payload[c].ini_addr = '0; + assign soc_data_q[c].id = '0; + + // Constant value + assign remote_req_interco[c].wdata.core_id = c[idx_width(NumCoresPerTile)-1:0]; + + // Scramble address before entering TCDM shim for sequential+interleaved memory map + addr_t snitch_data_qaddr_scrambled; + address_scrambler #( + .AddrWidth (AddrWidth ), + .ByteOffset (ByteOffset ), + .NumTiles (NumTiles ), + .NumBanksPerTile (NumBanksPerTile ), + .Bypass (0 ), + .SeqMemSizePerTile (SeqMemSizePerTile) + ) i_address_scrambler ( + .address_i (snitch_data_qaddr[c] ), + .address_o (snitch_data_qaddr_scrambled) + ); + + if (!TrafficGeneration) begin: gen_tcdm_shim + tcdm_shim #( + .AddrWidth (AddrWidth ), + .DataWidth (DataWidth ), + .MaxOutStandingReads (snitch_pkg::NumIntOutstandingLoads), + .NrTCDM (2 ), + .NrSoC (1 ), + .NumRules (3 ) + ) i_tcdm_shim ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // to TCDM --> FF Connection to outside of tile + .tcdm_req_valid_o ({local_req_interco_valid[c], remote_req_interco_valid[c]} ), + .tcdm_req_tgt_addr_o({local_req_interco_addr_int, prescramble_tcdm_req_tgt_addr} ), + .tcdm_req_wen_o ({local_req_interco_payload[c].wen, remote_req_interco[c].wen} ), + .tcdm_req_wdata_o ({local_req_interco_payload[c].wdata.data, remote_req_interco[c].wdata.data} ), + .tcdm_req_amo_o ({local_req_interco_payload[c].wdata.amo, remote_req_interco[c].wdata.amo} ), + .tcdm_req_id_o ({local_req_interco_payload[c].wdata.meta_id, remote_req_interco[c].wdata.meta_id} ), + .tcdm_req_be_o ({local_req_interco_payload[c].be, remote_req_interco[c].be} ), + .tcdm_req_ready_i ({local_req_interco_ready[c], remote_req_interco_ready[c]} ), + .tcdm_resp_valid_i ({local_resp_interco_valid[c], remote_resp_interco_valid[c]} ), + .tcdm_resp_ready_o ({local_resp_interco_ready[c], remote_resp_interco_ready[c]} ), + .tcdm_resp_rdata_i ({local_resp_interco_payload[c].rdata.data, remote_resp_interco[c].rdata.data} ), + .tcdm_resp_id_i ({local_resp_interco_payload[c].rdata.meta_id, remote_resp_interco[c].rdata.meta_id}), + // to SoC + .soc_qaddr_o (soc_data_q[c].addr ), + .soc_qwrite_o (soc_data_q[c].write ), + .soc_qamo_o (soc_data_q[c].amo ), + .soc_qdata_o (soc_data_q[c].data ), + .soc_qstrb_o (soc_data_q[c].strb ), + .soc_qvalid_o (soc_data_qvalid[c] ), + .soc_qready_i (soc_data_qready[c] ), + .soc_pdata_i (soc_data_p[c].data ), + .soc_perror_i (soc_data_p[c].error ), + .soc_pvalid_i (soc_data_pvalid[c] ), + .soc_pready_o (soc_data_pready[c] ), + // from core + .data_qaddr_i (snitch_data_qaddr_scrambled ), + .data_qwrite_i (snitch_data_qwrite[c] ), + .data_qamo_i (snitch_data_qamo[c] ), + .data_qdata_i (snitch_data_qdata[c] ), + .data_qstrb_i (snitch_data_qstrb[c] ), + .data_qid_i (snitch_data_qid[c] ), + .data_qvalid_i (snitch_data_qvalid[c] ), + .data_qready_o (snitch_data_qready[c] ), + .data_pdata_o (snitch_data_pdata[c] ), + .data_perror_o (snitch_data_perror[c] ), + .data_pid_o (snitch_data_pid[c] ), + .data_pvalid_o (snitch_data_pvalid[c] ), + .data_pready_i (snitch_data_pready[c] ), + .address_map_i (mask_map ) + ); + end else begin: gen_traffic_generator + traffic_generator #( + .NumRules (3 ), + .TCDMBaseAddr (TCDMBaseAddr ), + .MaxOutStandingReads(snitch_pkg::NumIntOutstandingLoads) + ) i_traffic_gen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .core_id_i ({tile_id_i, c[idx_width(NumCoresPerTile)-1:0]} ), + // Address map + .address_map_i (mask_map ), + // To TCDM + .tcdm_req_valid_o ({local_req_interco_valid[c], remote_req_interco_valid[c]} ), + .tcdm_req_tgt_addr_o({local_req_interco_addr_int, prescramble_tcdm_req_tgt_addr} ), + .tcdm_req_wen_o ({local_req_interco_payload[c].wen, remote_req_interco[c].wen}), + .tcdm_req_wdata_o ({local_req_interco_payload[c].wdata.data, + remote_req_interco[c].wdata.data}), + .tcdm_req_amo_o({local_req_interco_payload[c].wdata.amo, + remote_req_interco[c].wdata.amo}), + .tcdm_req_id_o({local_req_interco_payload[c] + .wdata.meta_id, remote_req_interco[c].wdata.meta_id}), + .tcdm_req_be_o ({local_req_interco_payload[c].be, remote_req_interco[c].be}), + .tcdm_req_ready_i ({local_req_interco_ready[c], remote_req_interco_ready[c]} ), + .tcdm_resp_valid_i({local_resp_interco_valid[c], remote_resp_interco_valid[c]}), + .tcdm_resp_ready_o({local_resp_interco_ready[c], remote_resp_interco_ready[c]}), + .tcdm_resp_rdata_i({local_resp_interco_payload[c].rdata.data, + remote_resp_interco[c].rdata.data} ), + .tcdm_resp_id_i ({local_resp_interco_payload[c].rdata.meta_id, + remote_resp_interco[c].rdata.meta_id}) + ); + + // Tie unused signals + assign soc_data_q[c].addr = '0; + assign soc_data_q[c].write = '0; + assign soc_data_q[c].amo = '0; + assign soc_data_q[c].data = '0; + assign soc_data_q[c].strb = '0; + assign soc_data_qvalid[c] = '0; + assign soc_data_pready[c] = '0; + assign snitch_data_qready[c] = '0; + assign snitch_data_pdata[c] = '0; + assign snitch_data_perror[c] = '0; + assign snitch_data_pid[c] = '0; + assign snitch_data_pvalid[c] = '0; + end + end + + /**************** + * AXI Plug * + ****************/ + + snitch_pkg::dreq_t soc_req_o; + snitch_pkg::dresp_t soc_resp_i; + + logic soc_qvalid; + logic soc_qready; + logic soc_pvalid; + logic soc_pready; + + // We don't care about this + assign soc_resp_i.id = 'x; + + snitch_demux #( + .NrPorts (NumCoresPerTile ), + .req_t (snitch_pkg::dreq_t ), + .resp_t (snitch_pkg::dresp_t) + ) i_snitch_demux_data ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + // Inputs + .req_payload_i (soc_data_q ), + .req_valid_i (soc_data_qvalid), + .req_ready_o (soc_data_qready), + .resp_payload_o(soc_data_p ), + .resp_last_o (/* Unused */ ), + .resp_valid_o (soc_data_pvalid), + .resp_ready_i (soc_data_pready), + // Output + .req_payload_o (soc_req_o ), + .req_valid_o (soc_qvalid ), + .req_ready_i (soc_qready ), + .resp_payload_i(soc_resp_i ), + .resp_last_i (1'b1 ), + .resp_valid_i (soc_pvalid ), + .resp_ready_o (soc_pready ) + ); + + // Core request + axi_core_req_t axi_cores_req, axi_cache_req; + axi_core_resp_t axi_cores_resp, axi_cache_resp; + axi_tile_req_t axi_mst_req; + axi_tile_resp_t axi_mst_resp; + + snitch_axi_adapter #( + .addr_t (snitch_pkg::addr_t), + .data_t (snitch_pkg::data_t), + .strb_t (snitch_pkg::strb_t), + .axi_mst_req_t (axi_core_req_t ), + .axi_mst_resp_t (axi_core_resp_t ) + ) i_snitch_core_axi_adapter ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_qaddr_i (soc_req_o.addr ), + .slv_qwrite_i(soc_req_o.write ), + .slv_qamo_i (soc_req_o.amo ), + .slv_qdata_i (soc_req_o.data ), + .slv_qsize_i (3'b010 ), + .slv_qstrb_i (soc_req_o.strb ), + .slv_qrlen_i ('0 ), + .slv_qvalid_i(soc_qvalid ), + .slv_qready_o(soc_qready ), + .slv_pdata_o (soc_resp_i.data ), + .slv_perror_o(soc_resp_i.error), + .slv_plast_o (/* Unused */ ), + .slv_pvalid_o(soc_pvalid ), + .slv_pready_i(soc_pready ), + .axi_req_o (axi_cores_req ), + .axi_resp_i (axi_cores_resp ) + ); + + // TODO: Add demux for the case where we have many intruction caches + snitch_axi_adapter #( + .addr_t (snitch_pkg::addr_t), + .data_t (axi_data_t ), + .strb_t (axi_strb_t ), + .axi_mst_req_t (axi_core_req_t ), + .axi_mst_resp_t (axi_core_resp_t ) + ) i_snitch_cache_axi_adapter ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_qaddr_i (refill_qaddr[0] ), + .slv_qwrite_i('0 ), + .slv_qamo_i ('0 ), + .slv_qdata_i ('0 ), + .slv_qsize_i (3'($clog2(AxiDataWidth/8))), + .slv_qstrb_i ('0 ), + .slv_qrlen_i (refill_qlen[0] ), + .slv_qvalid_i(refill_qvalid[0] ), + .slv_qready_o(refill_qready[0] ), + .slv_pdata_o (refill_pdata[0] ), + .slv_perror_o(refill_perror[0] ), + .slv_plast_o (refill_plast[0] ), + .slv_pvalid_o(refill_pvalid[0] ), + .slv_pready_i(refill_pready[0] ), + .axi_req_o (axi_cache_req ), + .axi_resp_i (axi_cache_resp ) + ); + + axi_mux #( + .SlvAxiIDWidth (AxiCoreIdWidth ), + .slv_aw_chan_t (axi_core_aw_t ), + .mst_aw_chan_t (axi_tile_aw_t ), + .w_chan_t (axi_tile_w_t ), + .slv_b_chan_t (axi_core_b_t ), + .mst_b_chan_t (axi_tile_b_t ), + .slv_ar_chan_t (axi_core_ar_t ), + .mst_ar_chan_t (axi_tile_ar_t ), + .slv_r_chan_t (axi_core_r_t ), + .mst_r_chan_t (axi_tile_r_t ), + .slv_req_t (axi_core_req_t ), + .slv_resp_t (axi_core_resp_t), + .mst_req_t (axi_tile_req_t ), + .mst_resp_t (axi_tile_resp_t), + .NoSlvPorts (2 ), + .MaxWTrans (8 ), + .FallThrough (1 ) + ) i_axi_mux ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .slv_reqs_i ({axi_cores_req, axi_cache_req} ), + .slv_resps_o({axi_cores_resp, axi_cache_resp}), + .mst_req_o (axi_mst_req ), + .mst_resp_i (axi_mst_resp ) + ); + + axi_cut #( + .aw_chan_t(axi_tile_aw_t ), + .w_chan_t (axi_tile_w_t ), + .b_chan_t (axi_tile_b_t ), + .ar_chan_t(axi_tile_ar_t ), + .r_chan_t (axi_tile_r_t ), + .req_t (axi_tile_req_t ), + .resp_t (axi_tile_resp_t) + ) axi_mst_slice ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_req_i (axi_mst_req ), + .slv_resp_o(axi_mst_resp ), + .mst_req_o (axi_mst_req_o ), + .mst_resp_i(axi_mst_resp_i) + ); + + /****************** + * Assertions * + ******************/ + + // Check invariants. + if (BootAddr[1:0] != 2'b00) + $fatal(1, "[mempool_tile] Boot address should be aligned in a 4-byte boundary."); + + if (NumCoresPerTile != 2**$clog2(NumCoresPerTile)) + $fatal(1, "[mempool_tile] The number of cores per tile must be a power of two."); + + if (NumCores != unsigned'(2**$clog2(NumCores))) + $fatal(1, "[mempool_tile] The number of cores must be a power of two."); + + if (NumBanksPerTile < 1) + $fatal(1, "[mempool_tile] The number of banks per tile must be larger than one"); + + if (NumCaches != 1) + $error("NumCaches > 1 is not supported!"); + + if (DataWidth > AxiDataWidth) + $error("AxiDataWidth needs to be larger than DataWidth!"); + +endmodule : mempool_tile + +/***************** + * WRAPPER * + *****************/ +/*verilator lint_off DECLFILENAME*/ +//what is the below file exactly used for ? +`include "mempool/mempool.svh" + +module mempool_tile_wrap + import mempool_pkg::*; + import cf_math_pkg::idx_width; +#( + // TCDM + parameter addr_t TCDMBaseAddr = 32'b0, + // Boot address + parameter logic [31:0] BootAddr = 32'h0000_1000, + // Dependent parameters. DO NOT CHANGE. + parameter int unsigned NumCaches = NumCoresPerTile / NumCoresPerCache +) ( + // Clock and reset + input logic clk_i, + input logic rst_ni, + // Scan chain + input logic scan_enable_i, + input logic scan_data_i, + output logic scan_data_o, + // Tile ID + input logic [idx_width(NumTiles)-1:0] tile_id_i, + // TCDM Master interfaces + output `STRUCT_PORT(tcdm_master_req_t) tcdm_master_north_req_o, + output logic tcdm_master_north_req_valid_o, + input logic tcdm_master_north_req_ready_i, + input `STRUCT_PORT(tcdm_master_resp_t) tcdm_master_north_resp_i, + input logic tcdm_master_north_resp_valid_i, + output logic tcdm_master_north_resp_ready_o, + output `STRUCT_PORT(tcdm_master_req_t) tcdm_master_northeast_req_o, + output logic tcdm_master_northeast_req_valid_o, + input logic tcdm_master_northeast_req_ready_i, + input `STRUCT_PORT(tcdm_master_resp_t) tcdm_master_northeast_resp_i, + input logic tcdm_master_northeast_resp_valid_i, + output logic tcdm_master_northeast_resp_ready_o, + output `STRUCT_PORT(tcdm_master_req_t) tcdm_master_east_req_o, + output logic tcdm_master_east_req_valid_o, + input logic tcdm_master_east_req_ready_i, + input `STRUCT_PORT(tcdm_master_resp_t) tcdm_master_east_resp_i, + input logic tcdm_master_east_resp_valid_i, + output logic tcdm_master_east_resp_ready_o, + output `STRUCT_PORT(tcdm_master_req_t) tcdm_master_local_req_o, + output logic tcdm_master_local_req_valid_o, + input logic tcdm_master_local_req_ready_i, + input `STRUCT_PORT(tcdm_master_resp_t) tcdm_master_local_resp_i, + input logic tcdm_master_local_resp_valid_i, + output logic tcdm_master_local_resp_ready_o, + // TCDM Slave interfaces + input `STRUCT_PORT(tcdm_slave_req_t) tcdm_slave_north_req_i, + input logic tcdm_slave_north_req_valid_i, + output logic tcdm_slave_north_req_ready_o, + output `STRUCT_PORT(tcdm_slave_resp_t) tcdm_slave_north_resp_o, + output logic tcdm_slave_north_resp_valid_o, + input logic tcdm_slave_north_resp_ready_i, + input `STRUCT_PORT(tcdm_slave_req_t) tcdm_slave_northeast_req_i, + input logic tcdm_slave_northeast_req_valid_i, + output logic tcdm_slave_northeast_req_ready_o, + output `STRUCT_PORT(tcdm_slave_resp_t) tcdm_slave_northeast_resp_o, + output logic tcdm_slave_northeast_resp_valid_o, + input logic tcdm_slave_northeast_resp_ready_i, + input `STRUCT_PORT(tcdm_slave_req_t) tcdm_slave_east_req_i, + input logic tcdm_slave_east_req_valid_i, + output logic tcdm_slave_east_req_ready_o, + output `STRUCT_PORT(tcdm_slave_resp_t) tcdm_slave_east_resp_o, + output logic tcdm_slave_east_resp_valid_o, + input logic tcdm_slave_east_resp_ready_i, + input `STRUCT_PORT(tcdm_slave_req_t) tcdm_slave_local_req_i, + input logic tcdm_slave_local_req_valid_i, + output logic tcdm_slave_local_req_ready_o, + output `STRUCT_PORT(tcdm_slave_resp_t) tcdm_slave_local_resp_o, + output logic tcdm_slave_local_resp_valid_o, + input logic tcdm_slave_local_resp_ready_i, + // AXI Interface + output `STRUCT_PORT(axi_tile_req_t) axi_mst_req_o, + input `STRUCT_PORT(axi_tile_resp_t) axi_mst_resp_i, + // Wake up interface + input logic [NumCoresPerTile-1:0] wake_up_i +); + + mempool_tile #( + .TCDMBaseAddr(TCDMBaseAddr), + .BootAddr (BootAddr ) + ) i_tile ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .tile_id_i (tile_id_i ), + // Scan chain + .scan_enable_i (scan_enable_i ), + .scan_data_i (scan_data_i ), + .scan_data_o (scan_data_o ), + // TCDM Master + .tcdm_master_req_o ({tcdm_master_northeast_req_o, tcdm_master_north_req_o, tcdm_master_east_req_o, tcdm_master_local_req_o} ), + .tcdm_master_req_ready_i ({tcdm_master_northeast_req_ready_i, tcdm_master_north_req_ready_i, tcdm_master_east_req_ready_i, tcdm_master_local_req_ready_i} ), + .tcdm_master_req_valid_o ({tcdm_master_northeast_req_valid_o, tcdm_master_north_req_valid_o, tcdm_master_east_req_valid_o, tcdm_master_local_req_valid_o} ), + .tcdm_master_resp_i ({tcdm_master_northeast_resp_i, tcdm_master_north_resp_i, tcdm_master_east_resp_i, tcdm_master_local_resp_i} ), + .tcdm_master_resp_ready_o({tcdm_master_northeast_resp_ready_o, tcdm_master_north_resp_ready_o, tcdm_master_east_resp_ready_o, tcdm_master_local_resp_ready_o}), + .tcdm_master_resp_valid_i({tcdm_master_northeast_resp_valid_i, tcdm_master_north_resp_valid_i, tcdm_master_east_resp_valid_i, tcdm_master_local_resp_valid_i}), + // TCDM Slave + .tcdm_slave_req_i ({tcdm_slave_northeast_req_i, tcdm_slave_north_req_i, tcdm_slave_east_req_i, tcdm_slave_local_req_i} ), + .tcdm_slave_req_ready_o ({tcdm_slave_northeast_req_ready_o, tcdm_slave_north_req_ready_o, tcdm_slave_east_req_ready_o, tcdm_slave_local_req_ready_o} ), + .tcdm_slave_req_valid_i ({tcdm_slave_northeast_req_valid_i, tcdm_slave_north_req_valid_i, tcdm_slave_east_req_valid_i, tcdm_slave_local_req_valid_i} ), + .tcdm_slave_resp_o ({tcdm_slave_northeast_resp_o, tcdm_slave_north_resp_o, tcdm_slave_east_resp_o, tcdm_slave_local_resp_o} ), + .tcdm_slave_resp_ready_i ({tcdm_slave_northeast_resp_ready_i, tcdm_slave_north_resp_ready_i, tcdm_slave_east_resp_ready_i, tcdm_slave_local_resp_ready_i} ), + .tcdm_slave_resp_valid_o ({tcdm_slave_northeast_resp_valid_o, tcdm_slave_north_resp_valid_o, tcdm_slave_east_resp_valid_o, tcdm_slave_local_resp_valid_o} ), + // AXI interface + .axi_mst_req_o (axi_mst_req_o ), + .axi_mst_resp_i (axi_mst_resp_i ), + // Wake up interface + .wake_up_i (wake_up_i ) + ); + +endmodule: mempool_tile_wrap diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/assign.svh b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/assign.svh new file mode 100644 index 0000000000..30c44acf66 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/assign.svh @@ -0,0 +1,46 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Florian Zaruba +/// Macros to define register bus request/response structs. + +`ifndef REGISTER_INTERFACE_ASSIGN_SVH_ +`define REGISTER_INTERFACE_ASSIGN_SVH_ + +`define REG_BUS_ASSIGN_TO_REQ(lhs, rhs) \ + assign lhs = '{ \ + addr: rhs.addr, \ + write: rhs.write, \ + wdata: rhs.wdata, \ + wstrb: rhs.wstrb, \ + valid: rhs.valid \ + }; + +`define REG_BUS_ASSIGN_FROM_REQ(lhs, rhs) \ + assign lhs.addr = rhs.addr; \ + assign lhs.write = rhs.write; \ + assign lhs.wdata = rhs.wdata; \ + assign lhs.wstrb = rhs.wstrb; \ + assign lhs.valid = rhs.valid; \ + +`define REG_BUS_ASSIGN_TO_RSP(lhs, rhs) \ + assign lhs = '{ \ + rdata: rhs.rdata, \ + error: rhs.error, \ + ready: rhs.ready \ + }; + +`define REG_BUS_ASSIGN_FROM_RSP(lhs, rhs) \ + assign lhs.rdata = rhs.rdata; \ + assign lhs.error = rhs.error; \ + assign lhs.ready = rhs.ready; + +`endif \ No newline at end of file diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/typedef.svh b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/typedef.svh new file mode 100644 index 0000000000..350d79e164 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/typedef.svh @@ -0,0 +1,38 @@ +// Copyright (c) 2020 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Florian Zaruba +/// Macros to define register bus request/response structs. + +`ifndef REGISTER_INTERFACE_TYPEDEF_SVH_ +`define REGISTER_INTERFACE_TYPEDEF_SVH_ + +`define REG_BUS_TYPEDEF_REQ(req_t, addr_t, data_t, strb_t) \ + typedef struct packed { \ + addr_t addr; \ + logic write; \ + data_t wdata; \ + strb_t wstrb; \ + logic valid; \ + } req_t; + +`define REG_BUS_TYPEDEF_RSP(rsp_t, data_t) \ + typedef struct packed { \ + data_t rdata; \ + logic error; \ + logic ready; \ + } rsp_t; + +`define REG_BUS_TYPEDEF_ALL(name, addr_t, data_t, strb_t) \ + `REG_BUS_TYPEDEF_REQ(name``_req_t, addr_t, data_t, strb_t) \ + `REG_BUS_TYPEDEF_RSP(name``_rsp_t, data_t) + +`endif diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/riscv_instr.sv b/flow/designs/src/mempool_group/rtl/snitch/src/riscv_instr.sv new file mode 100644 index 0000000000..ab7a904410 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/riscv_instr.sv @@ -0,0 +1,1546 @@ +/* Automatically generated by parse_opcodes */ +package riscv_instr; + localparam [31:0] CUSTOM0 = 32'b?????????????????000?????0001011; + localparam [31:0] CUSTOM0_RS1 = 32'b?????????????????010?????0001011; + localparam [31:0] CUSTOM0_RS1_RS2 = 32'b?????????????????011?????0001011; + localparam [31:0] CUSTOM0_RD = 32'b?????????????????100?????0001011; + localparam [31:0] CUSTOM0_RD_RS1 = 32'b?????????????????110?????0001011; + localparam [31:0] CUSTOM0_RD_RS1_RS2 = 32'b?????????????????111?????0001011; + localparam [31:0] CUSTOM1 = 32'b?????????????????000?????0101011; + localparam [31:0] CUSTOM1_RS1 = 32'b?????????????????010?????0101011; + localparam [31:0] CUSTOM1_RS1_RS2 = 32'b?????????????????011?????0101011; + localparam [31:0] CUSTOM1_RD = 32'b?????????????????100?????0101011; + localparam [31:0] CUSTOM1_RD_RS1 = 32'b?????????????????110?????0101011; + localparam [31:0] CUSTOM1_RD_RS1_RS2 = 32'b?????????????????111?????0101011; + localparam [31:0] CUSTOM2 = 32'b?????????????????000?????1011011; + localparam [31:0] CUSTOM2_RS1 = 32'b?????????????????010?????1011011; + localparam [31:0] CUSTOM2_RS1_RS2 = 32'b?????????????????011?????1011011; + localparam [31:0] CUSTOM2_RD = 32'b?????????????????100?????1011011; + localparam [31:0] CUSTOM2_RD_RS1 = 32'b?????????????????110?????1011011; + localparam [31:0] CUSTOM2_RD_RS1_RS2 = 32'b?????????????????111?????1011011; + localparam [31:0] CUSTOM3 = 32'b?????????????????000?????1111011; + localparam [31:0] CUSTOM3_RS1 = 32'b?????????????????010?????1111011; + localparam [31:0] CUSTOM3_RS1_RS2 = 32'b?????????????????011?????1111011; + localparam [31:0] CUSTOM3_RD = 32'b?????????????????100?????1111011; + localparam [31:0] CUSTOM3_RD_RS1 = 32'b?????????????????110?????1111011; + localparam [31:0] CUSTOM3_RD_RS1_RS2 = 32'b?????????????????111?????1111011; + localparam [31:0] SLLI_RV32 = 32'b0000000??????????001?????0010011; + localparam [31:0] SRLI_RV32 = 32'b0000000??????????101?????0010011; + localparam [31:0] SRAI_RV32 = 32'b0100000??????????101?????0010011; + localparam [31:0] FRFLAGS = 32'b00000000000100000010?????1110011; + localparam [31:0] FSFLAGS = 32'b000000000001?????001?????1110011; + localparam [31:0] FSFLAGSI = 32'b000000000001?????101?????1110011; + localparam [31:0] FRRM = 32'b00000000001000000010?????1110011; + localparam [31:0] FSRM = 32'b000000000010?????001?????1110011; + localparam [31:0] FSRMI = 32'b000000000010?????101?????1110011; + localparam [31:0] FSCSR = 32'b000000000011?????001?????1110011; + localparam [31:0] FRCSR = 32'b00000000001100000010?????1110011; + localparam [31:0] RDCYCLE = 32'b11000000000000000010?????1110011; + localparam [31:0] RDTIME = 32'b11000000000100000010?????1110011; + localparam [31:0] RDINSTRET = 32'b11000000001000000010?????1110011; + localparam [31:0] RDCYCLEH = 32'b11001000000000000010?????1110011; + localparam [31:0] RDTIMEH = 32'b11001000000100000010?????1110011; + localparam [31:0] RDINSTRETH = 32'b11001000001000000010?????1110011; + localparam [31:0] SCALL = 32'b00000000000000000000000001110011; + localparam [31:0] SBREAK = 32'b00000000000100000000000001110011; + localparam [31:0] FMV_X_S = 32'b111000000000?????000?????1010011; + localparam [31:0] FMV_S_X = 32'b111100000000?????000?????1010011; + localparam [31:0] FENCE_TSO = 32'b100000110011?????000?????0001111; + localparam [31:0] PAUSE = 32'b00000001000000000000000000001111; + localparam [31:0] AMOADD_W = 32'b00000????????????010?????0101111; + localparam [31:0] AMOXOR_W = 32'b00100????????????010?????0101111; + localparam [31:0] AMOOR_W = 32'b01000????????????010?????0101111; + localparam [31:0] AMOAND_W = 32'b01100????????????010?????0101111; + localparam [31:0] AMOMIN_W = 32'b10000????????????010?????0101111; + localparam [31:0] AMOMAX_W = 32'b10100????????????010?????0101111; + localparam [31:0] AMOMINU_W = 32'b11000????????????010?????0101111; + localparam [31:0] AMOMAXU_W = 32'b11100????????????010?????0101111; + localparam [31:0] AMOSWAP_W = 32'b00001????????????010?????0101111; + localparam [31:0] LR_W = 32'b00010??00000?????010?????0101111; + localparam [31:0] SC_W = 32'b00011????????????010?????0101111; + localparam [31:0] C_SRLI_RV32 = 32'b????????????????100000????????01; + localparam [31:0] C_SRAI_RV32 = 32'b????????????????100001????????01; + localparam [31:0] C_SLLI_RV32 = 32'b????????????????0000??????????10; + localparam [31:0] FADD_D = 32'b0000001??????????????????1010011; + localparam [31:0] FSUB_D = 32'b0000101??????????????????1010011; + localparam [31:0] FMUL_D = 32'b0001001??????????????????1010011; + localparam [31:0] FDIV_D = 32'b0001101??????????????????1010011; + localparam [31:0] FSGNJ_D = 32'b0010001??????????000?????1010011; + localparam [31:0] FSGNJN_D = 32'b0010001??????????001?????1010011; + localparam [31:0] FSGNJX_D = 32'b0010001??????????010?????1010011; + localparam [31:0] FMIN_D = 32'b0010101??????????000?????1010011; + localparam [31:0] FMAX_D = 32'b0010101??????????001?????1010011; + localparam [31:0] FCVT_S_D = 32'b010000000001?????????????1010011; + localparam [31:0] FCVT_D_S = 32'b010000100000?????????????1010011; + localparam [31:0] FSQRT_D = 32'b010110100000?????????????1010011; + localparam [31:0] FLE_D = 32'b1010001??????????000?????1010011; + localparam [31:0] FLT_D = 32'b1010001??????????001?????1010011; + localparam [31:0] FEQ_D = 32'b1010001??????????010?????1010011; + localparam [31:0] FCVT_W_D = 32'b110000100000?????????????1010011; + localparam [31:0] FCVT_WU_D = 32'b110000100001?????????????1010011; + localparam [31:0] FCLASS_D = 32'b111000100000?????001?????1010011; + localparam [31:0] FCVT_D_W = 32'b110100100000?????????????1010011; + localparam [31:0] FCVT_D_WU = 32'b110100100001?????????????1010011; + localparam [31:0] FLD = 32'b?????????????????011?????0000111; + localparam [31:0] FSD = 32'b?????????????????011?????0100111; + localparam [31:0] FMADD_D = 32'b?????01??????????????????1000011; + localparam [31:0] FMSUB_D = 32'b?????01??????????????????1000111; + localparam [31:0] FNMSUB_D = 32'b?????01??????????????????1001011; + localparam [31:0] FNMADD_D = 32'b?????01??????????????????1001111; + localparam [31:0] FCVT_H_D = 32'b010001000001?????????????1010011; + localparam [31:0] FCVT_D_H = 32'b010000100010?????????????1010011; + localparam [31:0] FADD_S = 32'b0000000??????????????????1010011; + localparam [31:0] FSUB_S = 32'b0000100??????????????????1010011; + localparam [31:0] FMUL_S = 32'b0001000??????????????????1010011; + localparam [31:0] FDIV_S = 32'b0001100??????????????????1010011; + localparam [31:0] FSGNJ_S = 32'b0010000??????????000?????1010011; + localparam [31:0] FSGNJN_S = 32'b0010000??????????001?????1010011; + localparam [31:0] FSGNJX_S = 32'b0010000??????????010?????1010011; + localparam [31:0] FMIN_S = 32'b0010100??????????000?????1010011; + localparam [31:0] FMAX_S = 32'b0010100??????????001?????1010011; + localparam [31:0] FSQRT_S = 32'b010110000000?????????????1010011; + localparam [31:0] FLE_S = 32'b1010000??????????000?????1010011; + localparam [31:0] FLT_S = 32'b1010000??????????001?????1010011; + localparam [31:0] FEQ_S = 32'b1010000??????????010?????1010011; + localparam [31:0] FCVT_W_S = 32'b110000000000?????????????1010011; + localparam [31:0] FCVT_WU_S = 32'b110000000001?????????????1010011; + localparam [31:0] FMV_X_W = 32'b111000000000?????000?????1010011; + localparam [31:0] FCLASS_S = 32'b111000000000?????001?????1010011; + localparam [31:0] FCVT_S_W = 32'b110100000000?????????????1010011; + localparam [31:0] FCVT_S_WU = 32'b110100000001?????????????1010011; + localparam [31:0] FMV_W_X = 32'b111100000000?????000?????1010011; + localparam [31:0] FLW = 32'b?????????????????010?????0000111; + localparam [31:0] FSW = 32'b?????????????????010?????0100111; + localparam [31:0] FMADD_S = 32'b?????00??????????????????1000011; + localparam [31:0] FMSUB_S = 32'b?????00??????????????????1000111; + localparam [31:0] FNMSUB_S = 32'b?????00??????????????????1001011; + localparam [31:0] FNMADD_S = 32'b?????00??????????????????1001111; + localparam [31:0] HFENCE_VVMA = 32'b0010001??????????000000001110011; + localparam [31:0] HFENCE_GVMA = 32'b0110001??????????000000001110011; + localparam [31:0] HLV_B = 32'b011000000000?????100?????1110011; + localparam [31:0] HLV_BU = 32'b011000000001?????100?????1110011; + localparam [31:0] HLV_H = 32'b011001000000?????100?????1110011; + localparam [31:0] HLV_HU = 32'b011001000001?????100?????1110011; + localparam [31:0] HLVX_HU = 32'b011001000011?????100?????1110011; + localparam [31:0] HLV_W = 32'b011010000000?????100?????1110011; + localparam [31:0] HLVX_WU = 32'b011010000011?????100?????1110011; + localparam [31:0] HSV_B = 32'b0110001??????????100000001110011; + localparam [31:0] HSV_H = 32'b0110011??????????100000001110011; + localparam [31:0] HSV_W = 32'b0110101??????????100000001110011; + localparam [31:0] BEQ = 32'b?????????????????000?????1100011; + localparam [31:0] BNE = 32'b?????????????????001?????1100011; + localparam [31:0] BLT = 32'b?????????????????100?????1100011; + localparam [31:0] BGE = 32'b?????????????????101?????1100011; + localparam [31:0] BLTU = 32'b?????????????????110?????1100011; + localparam [31:0] BGEU = 32'b?????????????????111?????1100011; + localparam [31:0] JALR = 32'b?????????????????000?????1100111; + localparam [31:0] JAL = 32'b?????????????????????????1101111; + localparam [31:0] LUI = 32'b?????????????????????????0110111; + localparam [31:0] AUIPC = 32'b?????????????????????????0010111; + localparam [31:0] ADDI = 32'b?????????????????000?????0010011; + localparam [31:0] SLLI = 32'b000000???????????001?????0010011; + localparam [31:0] SLTI = 32'b?????????????????010?????0010011; + localparam [31:0] SLTIU = 32'b?????????????????011?????0010011; + localparam [31:0] XORI = 32'b?????????????????100?????0010011; + localparam [31:0] SRLI = 32'b000000???????????101?????0010011; + localparam [31:0] SRAI = 32'b010000???????????101?????0010011; + localparam [31:0] ORI = 32'b?????????????????110?????0010011; + localparam [31:0] ANDI = 32'b?????????????????111?????0010011; + localparam [31:0] ADD = 32'b0000000??????????000?????0110011; + localparam [31:0] SUB = 32'b0100000??????????000?????0110011; + localparam [31:0] SLL = 32'b0000000??????????001?????0110011; + localparam [31:0] SLT = 32'b0000000??????????010?????0110011; + localparam [31:0] SLTU = 32'b0000000??????????011?????0110011; + localparam [31:0] XOR = 32'b0000000??????????100?????0110011; + localparam [31:0] SRL = 32'b0000000??????????101?????0110011; + localparam [31:0] SRA = 32'b0100000??????????101?????0110011; + localparam [31:0] OR = 32'b0000000??????????110?????0110011; + localparam [31:0] AND = 32'b0000000??????????111?????0110011; + localparam [31:0] LB = 32'b?????????????????000?????0000011; + localparam [31:0] LH = 32'b?????????????????001?????0000011; + localparam [31:0] LW = 32'b?????????????????010?????0000011; + localparam [31:0] LBU = 32'b?????????????????100?????0000011; + localparam [31:0] LHU = 32'b?????????????????101?????0000011; + localparam [31:0] SB = 32'b?????????????????000?????0100011; + localparam [31:0] SH = 32'b?????????????????001?????0100011; + localparam [31:0] SW = 32'b?????????????????010?????0100011; + localparam [31:0] FENCE = 32'b?????????????????000?????0001111; + localparam [31:0] FENCE_I = 32'b?????????????????001?????0001111; + localparam [31:0] MUL = 32'b0000001??????????000?????0110011; + localparam [31:0] MULH = 32'b0000001??????????001?????0110011; + localparam [31:0] MULHSU = 32'b0000001??????????010?????0110011; + localparam [31:0] MULHU = 32'b0000001??????????011?????0110011; + localparam [31:0] DIV = 32'b0000001??????????100?????0110011; + localparam [31:0] DIVU = 32'b0000001??????????101?????0110011; + localparam [31:0] REM = 32'b0000001??????????110?????0110011; + localparam [31:0] REMU = 32'b0000001??????????111?????0110011; + localparam [31:0] FADD_Q = 32'b0000011??????????????????1010011; + localparam [31:0] FSUB_Q = 32'b0000111??????????????????1010011; + localparam [31:0] FMUL_Q = 32'b0001011??????????????????1010011; + localparam [31:0] FDIV_Q = 32'b0001111??????????????????1010011; + localparam [31:0] FSGNJ_Q = 32'b0010011??????????000?????1010011; + localparam [31:0] FSGNJN_Q = 32'b0010011??????????001?????1010011; + localparam [31:0] FSGNJX_Q = 32'b0010011??????????010?????1010011; + localparam [31:0] FMIN_Q = 32'b0010111??????????000?????1010011; + localparam [31:0] FMAX_Q = 32'b0010111??????????001?????1010011; + localparam [31:0] FCVT_S_Q = 32'b010000000011?????????????1010011; + localparam [31:0] FCVT_Q_S = 32'b010001100000?????????????1010011; + localparam [31:0] FCVT_D_Q = 32'b010000100011?????????????1010011; + localparam [31:0] FCVT_Q_D = 32'b010001100001?????????????1010011; + localparam [31:0] FSQRT_Q = 32'b010111100000?????????????1010011; + localparam [31:0] FLE_Q = 32'b1010011??????????000?????1010011; + localparam [31:0] FLT_Q = 32'b1010011??????????001?????1010011; + localparam [31:0] FEQ_Q = 32'b1010011??????????010?????1010011; + localparam [31:0] FCVT_W_Q = 32'b110001100000?????????????1010011; + localparam [31:0] FCVT_WU_Q = 32'b110001100001?????????????1010011; + localparam [31:0] FCLASS_Q = 32'b111001100000?????001?????1010011; + localparam [31:0] FCVT_Q_W = 32'b110101100000?????????????1010011; + localparam [31:0] FCVT_Q_WU = 32'b110101100001?????????????1010011; + localparam [31:0] FLQ = 32'b?????????????????100?????0000111; + localparam [31:0] FSQ = 32'b?????????????????100?????0100111; + localparam [31:0] FMADD_Q = 32'b?????11??????????????????1000011; + localparam [31:0] FMSUB_Q = 32'b?????11??????????????????1000111; + localparam [31:0] FNMSUB_Q = 32'b?????11??????????????????1001011; + localparam [31:0] FNMADD_Q = 32'b?????11??????????????????1001111; + localparam [31:0] FCVT_H_Q = 32'b010001000011?????????????1010011; + localparam [31:0] FCVT_Q_H = 32'b010001100010?????????????1010011; + localparam [31:0] FADD_H = 32'b0000010??????????????????1010011; + localparam [31:0] FSUB_H = 32'b0000110??????????????????1010011; + localparam [31:0] FMUL_H = 32'b0001010??????????????????1010011; + localparam [31:0] FDIV_H = 32'b0001110??????????????????1010011; + localparam [31:0] FSGNJ_H = 32'b0010010??????????000?????1010011; + localparam [31:0] FSGNJN_H = 32'b0010010??????????001?????1010011; + localparam [31:0] FSGNJX_H = 32'b0010010??????????010?????1010011; + localparam [31:0] FMIN_H = 32'b0010110??????????000?????1010011; + localparam [31:0] FMAX_H = 32'b0010110??????????001?????1010011; + localparam [31:0] FCVT_H_S = 32'b010001000000?????????????1010011; + localparam [31:0] FCVT_S_H = 32'b010000000010?????????????1010011; + localparam [31:0] FSQRT_H = 32'b010111000000?????????????1010011; + localparam [31:0] FLE_H = 32'b1010010??????????000?????1010011; + localparam [31:0] FLT_H = 32'b1010010??????????001?????1010011; + localparam [31:0] FEQ_H = 32'b1010010??????????010?????1010011; + localparam [31:0] FCVT_W_H = 32'b110001000000?????????????1010011; + localparam [31:0] FCVT_WU_H = 32'b110001000001?????????????1010011; + localparam [31:0] FMV_X_H = 32'b111001000000?????000?????1010011; + localparam [31:0] FCLASS_H = 32'b111001000000?????001?????1010011; + localparam [31:0] FCVT_H_W = 32'b110101000000?????????????1010011; + localparam [31:0] FCVT_H_WU = 32'b110101000001?????????????1010011; + localparam [31:0] FMV_H_X = 32'b111101000000?????000?????1010011; + localparam [31:0] FLH = 32'b?????????????????001?????0000111; + localparam [31:0] FSH = 32'b?????????????????001?????0100111; + localparam [31:0] FMADD_H = 32'b?????10??????????????????1000011; + localparam [31:0] FMSUB_H = 32'b?????10??????????????????1000111; + localparam [31:0] FNMSUB_H = 32'b?????10??????????????????1001011; + localparam [31:0] FNMADD_H = 32'b?????10??????????????????1001111; + localparam [31:0] AMOADD_D = 32'b00000????????????011?????0101111; + localparam [31:0] AMOXOR_D = 32'b00100????????????011?????0101111; + localparam [31:0] AMOOR_D = 32'b01000????????????011?????0101111; + localparam [31:0] AMOAND_D = 32'b01100????????????011?????0101111; + localparam [31:0] AMOMIN_D = 32'b10000????????????011?????0101111; + localparam [31:0] AMOMAX_D = 32'b10100????????????011?????0101111; + localparam [31:0] AMOMINU_D = 32'b11000????????????011?????0101111; + localparam [31:0] AMOMAXU_D = 32'b11100????????????011?????0101111; + localparam [31:0] AMOSWAP_D = 32'b00001????????????011?????0101111; + localparam [31:0] LR_D = 32'b00010??00000?????011?????0101111; + localparam [31:0] SC_D = 32'b00011????????????011?????0101111; + localparam [31:0] C_LD = 32'b????????????????011???????????00; + localparam [31:0] C_SD = 32'b????????????????111???????????00; + localparam [31:0] C_SUBW = 32'b????????????????100111???00???01; + localparam [31:0] C_ADDW = 32'b????????????????100111???01???01; + localparam [31:0] C_ADDIW = 32'b????????????????001???????????01; + localparam [31:0] C_LDSP = 32'b????????????????011???????????10; + localparam [31:0] C_SDSP = 32'b????????????????111???????????10; + localparam [31:0] FCVT_L_D = 32'b110000100010?????????????1010011; + localparam [31:0] FCVT_LU_D = 32'b110000100011?????????????1010011; + localparam [31:0] FMV_X_D = 32'b111000100000?????000?????1010011; + localparam [31:0] FCVT_D_L = 32'b110100100010?????????????1010011; + localparam [31:0] FCVT_D_LU = 32'b110100100011?????????????1010011; + localparam [31:0] FMV_D_X = 32'b111100100000?????000?????1010011; + localparam [31:0] FCVT_L_S = 32'b110000000010?????????????1010011; + localparam [31:0] FCVT_LU_S = 32'b110000000011?????????????1010011; + localparam [31:0] FCVT_S_L = 32'b110100000010?????????????1010011; + localparam [31:0] FCVT_S_LU = 32'b110100000011?????????????1010011; + localparam [31:0] HLV_WU = 32'b011010000001?????100?????1110011; + localparam [31:0] HLV_D = 32'b011011000000?????100?????1110011; + localparam [31:0] HSV_D = 32'b0110111??????????100000001110011; + localparam [31:0] ADDIW = 32'b?????????????????000?????0011011; + localparam [31:0] SLLIW = 32'b0000000??????????001?????0011011; + localparam [31:0] SRLIW = 32'b0000000??????????101?????0011011; + localparam [31:0] SRAIW = 32'b0100000??????????101?????0011011; + localparam [31:0] ADDW = 32'b0000000??????????000?????0111011; + localparam [31:0] SUBW = 32'b0100000??????????000?????0111011; + localparam [31:0] SLLW = 32'b0000000??????????001?????0111011; + localparam [31:0] SRLW = 32'b0000000??????????101?????0111011; + localparam [31:0] SRAW = 32'b0100000??????????101?????0111011; + localparam [31:0] LD = 32'b?????????????????011?????0000011; + localparam [31:0] LWU = 32'b?????????????????110?????0000011; + localparam [31:0] SD = 32'b?????????????????011?????0100011; + localparam [31:0] MULW = 32'b0000001??????????000?????0111011; + localparam [31:0] DIVW = 32'b0000001??????????100?????0111011; + localparam [31:0] DIVUW = 32'b0000001??????????101?????0111011; + localparam [31:0] REMW = 32'b0000001??????????110?????0111011; + localparam [31:0] REMUW = 32'b0000001??????????111?????0111011; + localparam [31:0] FCVT_L_Q = 32'b110001100010?????????????1010011; + localparam [31:0] FCVT_LU_Q = 32'b110001100011?????????????1010011; + localparam [31:0] FCVT_Q_L = 32'b110101100010?????????????1010011; + localparam [31:0] FCVT_Q_LU = 32'b110101100011?????????????1010011; + localparam [31:0] FCVT_L_H = 32'b110001000010?????????????1010011; + localparam [31:0] FCVT_LU_H = 32'b110001000011?????????????1010011; + localparam [31:0] FCVT_H_L = 32'b110101000010?????????????1010011; + localparam [31:0] FCVT_H_LU = 32'b110101000011?????????????1010011; + localparam [31:0] C_NOP = 32'b????????????????0000000000000001; + localparam [31:0] C_ADDI16SP = 32'b????????????????011?00010?????01; + localparam [31:0] C_JR = 32'b????????????????1000?????0000010; + localparam [31:0] C_JALR = 32'b????????????????1001?????0000010; + localparam [31:0] C_EBREAK = 32'b????????????????1001000000000010; + localparam [31:0] C_ADDI4SPN = 32'b????????????????000???????????00; + localparam [31:0] C_FLD = 32'b????????????????001???????????00; + localparam [31:0] C_LW = 32'b????????????????010???????????00; + localparam [31:0] C_FLW = 32'b????????????????011???????????00; + localparam [31:0] C_FSD = 32'b????????????????101???????????00; + localparam [31:0] C_SW = 32'b????????????????110???????????00; + localparam [31:0] C_FSW = 32'b????????????????111???????????00; + localparam [31:0] C_ADDI = 32'b????????????????000???????????01; + localparam [31:0] C_JAL = 32'b????????????????001???????????01; + localparam [31:0] C_LI = 32'b????????????????010???????????01; + localparam [31:0] C_LUI = 32'b????????????????011???????????01; + localparam [31:0] C_SRLI = 32'b????????????????100?00????????01; + localparam [31:0] C_SRAI = 32'b????????????????100?01????????01; + localparam [31:0] C_ANDI = 32'b????????????????100?10????????01; + localparam [31:0] C_SUB = 32'b????????????????100011???00???01; + localparam [31:0] C_XOR = 32'b????????????????100011???01???01; + localparam [31:0] C_OR = 32'b????????????????100011???10???01; + localparam [31:0] C_AND = 32'b????????????????100011???11???01; + localparam [31:0] C_J = 32'b????????????????101???????????01; + localparam [31:0] C_BEQZ = 32'b????????????????110???????????01; + localparam [31:0] C_BNEZ = 32'b????????????????111???????????01; + localparam [31:0] C_SLLI = 32'b????????????????000???????????10; + localparam [31:0] C_FLDSP = 32'b????????????????001???????????10; + localparam [31:0] C_LWSP = 32'b????????????????010???????????10; + localparam [31:0] C_FLWSP = 32'b????????????????011???????????10; + localparam [31:0] C_MV = 32'b????????????????1000??????????10; + localparam [31:0] C_ADD = 32'b????????????????1001??????????10; + localparam [31:0] C_FSDSP = 32'b????????????????101???????????10; + localparam [31:0] C_SWSP = 32'b????????????????110???????????10; + localparam [31:0] C_FSWSP = 32'b????????????????111???????????10; + localparam [31:0] VSETVLI = 32'b0????????????????111?????1010111; + localparam [31:0] VLE8_V = 32'b???000?00000?????000?????0000111; + localparam [31:0] VLE16_V = 32'b???000?00000?????101?????0000111; + localparam [31:0] VLE32_V = 32'b???000?00000?????110?????0000111; + localparam [31:0] VLE64_V = 32'b???000?00000?????111?????0000111; + localparam [31:0] VLE128_V = 32'b???100?00000?????000?????0000111; + localparam [31:0] VLE256_V = 32'b???100?00000?????101?????0000111; + localparam [31:0] VLE512_V = 32'b???100?00000?????110?????0000111; + localparam [31:0] VLE1024_V = 32'b???100?00000?????111?????0000111; + localparam [31:0] VSE8_V = 32'b???000?00000?????000?????0100111; + localparam [31:0] VSE16_V = 32'b???000?00000?????101?????0100111; + localparam [31:0] VSE32_V = 32'b???000?00000?????110?????0100111; + localparam [31:0] VSE64_V = 32'b???000?00000?????111?????0100111; + localparam [31:0] VSE128_V = 32'b???100?00000?????000?????0100111; + localparam [31:0] VSE256_V = 32'b???100?00000?????101?????0100111; + localparam [31:0] VSE512_V = 32'b???100?00000?????110?????0100111; + localparam [31:0] VSE1024_V = 32'b???100?00000?????111?????0100111; + localparam [31:0] VLSE8_V = 32'b???010???????????000?????0000111; + localparam [31:0] VLSE16_V = 32'b???010???????????101?????0000111; + localparam [31:0] VLSE32_V = 32'b???010???????????110?????0000111; + localparam [31:0] VLSE64_V = 32'b???010???????????111?????0000111; + localparam [31:0] VLSE128_V = 32'b???110???????????000?????0000111; + localparam [31:0] VLSE256_V = 32'b???110???????????101?????0000111; + localparam [31:0] VLSE512_V = 32'b???110???????????110?????0000111; + localparam [31:0] VLSE1024_V = 32'b???110???????????111?????0000111; + localparam [31:0] VSSE8_V = 32'b???010???????????000?????0100111; + localparam [31:0] VSSE16_V = 32'b???010???????????101?????0100111; + localparam [31:0] VSSE32_V = 32'b???010???????????110?????0100111; + localparam [31:0] VSSE64_V = 32'b???010???????????111?????0100111; + localparam [31:0] VSSE128_V = 32'b???110???????????000?????0100111; + localparam [31:0] VSSE256_V = 32'b???110???????????101?????0100111; + localparam [31:0] VSSE512_V = 32'b???110???????????110?????0100111; + localparam [31:0] VSSE1024_V = 32'b???110???????????111?????0100111; + localparam [31:0] VLXEI8_V = 32'b???011???????????000?????0000111; + localparam [31:0] VLXEI16_V = 32'b???011???????????101?????0000111; + localparam [31:0] VLXEI32_V = 32'b???011???????????110?????0000111; + localparam [31:0] VLXEI64_V = 32'b???011???????????111?????0000111; + localparam [31:0] VLXEI128_V = 32'b???111???????????000?????0000111; + localparam [31:0] VLXEI256_V = 32'b???111???????????101?????0000111; + localparam [31:0] VLXEI512_V = 32'b???111???????????110?????0000111; + localparam [31:0] VLXEI1024_V = 32'b???111???????????111?????0000111; + localparam [31:0] VSXEI8_V = 32'b???011???????????000?????0100111; + localparam [31:0] VSXEI16_V = 32'b???011???????????101?????0100111; + localparam [31:0] VSXEI32_V = 32'b???011???????????110?????0100111; + localparam [31:0] VSXEI64_V = 32'b???011???????????111?????0100111; + localparam [31:0] VSXEI128_V = 32'b???111???????????000?????0100111; + localparam [31:0] VSXEI256_V = 32'b???111???????????101?????0100111; + localparam [31:0] VSXEI512_V = 32'b???111???????????110?????0100111; + localparam [31:0] VSXEI1024_V = 32'b???111???????????111?????0100111; + localparam [31:0] VSUXEI8_V = 32'b???001???????????000?????0100111; + localparam [31:0] VSUXEI16_V = 32'b???001???????????101?????0100111; + localparam [31:0] VSUXEI32_V = 32'b???001???????????110?????0100111; + localparam [31:0] VSUXEI64_V = 32'b???001???????????111?????0100111; + localparam [31:0] VSUXEI128_V = 32'b???101???????????000?????0100111; + localparam [31:0] VSUXEI256_V = 32'b???101???????????101?????0100111; + localparam [31:0] VSUXEI512_V = 32'b???101???????????110?????0100111; + localparam [31:0] VSUXEI1024_V = 32'b???101???????????111?????0100111; + localparam [31:0] VLE8FF_V = 32'b???000?10000?????000?????0000111; + localparam [31:0] VLE16FF_V = 32'b???000?10000?????101?????0000111; + localparam [31:0] VLE32FF_V = 32'b???000?10000?????110?????0000111; + localparam [31:0] VLE64FF_V = 32'b???000?10000?????111?????0000111; + localparam [31:0] VLE128FF_V = 32'b???100?10000?????000?????0000111; + localparam [31:0] VLE256FF_V = 32'b???100?10000?????101?????0000111; + localparam [31:0] VLE512FF_V = 32'b???100?10000?????110?????0000111; + localparam [31:0] VLE1024FF_V = 32'b???100?10000?????111?????0000111; + localparam [31:0] VL1RE8_V = 32'b000000101000?????000?????0000111; + localparam [31:0] VL1RE16_V = 32'b000000101000?????101?????0000111; + localparam [31:0] VL1RE32_V = 32'b000000101000?????110?????0000111; + localparam [31:0] VL1RE64_V = 32'b000000101000?????111?????0000111; + localparam [31:0] VL2RE8_V = 32'b001000101000?????000?????0000111; + localparam [31:0] VL2RE16_V = 32'b001000101000?????101?????0000111; + localparam [31:0] VL2RE32_V = 32'b001000101000?????110?????0000111; + localparam [31:0] VL2RE64_V = 32'b001000101000?????111?????0000111; + localparam [31:0] VL4RE8_V = 32'b011000101000?????000?????0000111; + localparam [31:0] VL4RE16_V = 32'b011000101000?????101?????0000111; + localparam [31:0] VL4RE32_V = 32'b011000101000?????110?????0000111; + localparam [31:0] VL4RE64_V = 32'b011000101000?????111?????0000111; + localparam [31:0] VL8RE8_V = 32'b111000101000?????000?????0000111; + localparam [31:0] VL8RE16_V = 32'b111000101000?????101?????0000111; + localparam [31:0] VL8RE32_V = 32'b111000101000?????110?????0000111; + localparam [31:0] VL8RE64_V = 32'b111000101000?????111?????0000111; + localparam [31:0] VS1R_V = 32'b000000101000?????000?????0100111; + localparam [31:0] VS2R_V = 32'b001000101000?????000?????0100111; + localparam [31:0] VS4R_V = 32'b011000101000?????000?????0100111; + localparam [31:0] VS8R_V = 32'b111000101000?????000?????0100111; + localparam [31:0] VFADD_VF = 32'b000000???????????101?????1010111; + localparam [31:0] VFSUB_VF = 32'b000010???????????101?????1010111; + localparam [31:0] VFMIN_VF = 32'b000100???????????101?????1010111; + localparam [31:0] VFMAX_VF = 32'b000110???????????101?????1010111; + localparam [31:0] VFSGNJ_VF = 32'b001000???????????101?????1010111; + localparam [31:0] VFSGNJN_VF = 32'b001001???????????101?????1010111; + localparam [31:0] VFSGNJX_VF = 32'b001010???????????101?????1010111; + localparam [31:0] VFSLIDE1UP_VF = 32'b001110???????????101?????1010111; + localparam [31:0] VFSLIDE1DOWN_VF = 32'b001111???????????101?????1010111; + localparam [31:0] VFMV_S_F = 32'b010000100000?????101?????1010111; + localparam [31:0] VFMERGE_VFM = 32'b0101110??????????101?????1010111; + localparam [31:0] VFMV_V_F = 32'b010111100000?????101?????1010111; + localparam [31:0] VMFEQ_VF = 32'b011000???????????101?????1010111; + localparam [31:0] VMFLE_VF = 32'b011001???????????101?????1010111; + localparam [31:0] VMFLT_VF = 32'b011011???????????101?????1010111; + localparam [31:0] VMFNE_VF = 32'b011100???????????101?????1010111; + localparam [31:0] VMFGT_VF = 32'b011101???????????101?????1010111; + localparam [31:0] VMFGE_VF = 32'b011111???????????101?????1010111; + localparam [31:0] VFDIV_VF = 32'b100000???????????101?????1010111; + localparam [31:0] VFRDIV_VF = 32'b100001???????????101?????1010111; + localparam [31:0] VFMUL_VF = 32'b100100???????????101?????1010111; + localparam [31:0] VFRSUB_VF = 32'b100111???????????101?????1010111; + localparam [31:0] VFMADD_VF = 32'b101000???????????101?????1010111; + localparam [31:0] VFNMADD_VF = 32'b101001???????????101?????1010111; + localparam [31:0] VFMSUB_VF = 32'b101010???????????101?????1010111; + localparam [31:0] VFNMSUB_VF = 32'b101011???????????101?????1010111; + localparam [31:0] VFMACC_VF = 32'b101100???????????101?????1010111; + localparam [31:0] VFNMACC_VF = 32'b101101???????????101?????1010111; + localparam [31:0] VFMSAC_VF = 32'b101110???????????101?????1010111; + localparam [31:0] VFNMSAC_VF = 32'b101111???????????101?????1010111; + localparam [31:0] VFWADD_VF = 32'b110000???????????101?????1010111; + localparam [31:0] VFWSUB_VF = 32'b110010???????????101?????1010111; + localparam [31:0] VFWADD_WF = 32'b110100???????????101?????1010111; + localparam [31:0] VFWSUB_WF = 32'b110110???????????101?????1010111; + localparam [31:0] VFWMUL_VF = 32'b111000???????????101?????1010111; + localparam [31:0] VFWMACC_VF = 32'b111100???????????101?????1010111; + localparam [31:0] VFWNMACC_VF = 32'b111101???????????101?????1010111; + localparam [31:0] VFWMSAC_VF = 32'b111110???????????101?????1010111; + localparam [31:0] VFWNMSAC_VF = 32'b111111???????????101?????1010111; + localparam [31:0] VFADD_VV = 32'b000000???????????001?????1010111; + localparam [31:0] VFREDSUM_VS = 32'b000001???????????001?????1010111; + localparam [31:0] VFSUB_VV = 32'b000010???????????001?????1010111; + localparam [31:0] VFREDOSUM_VS = 32'b000011???????????001?????1010111; + localparam [31:0] VFMIN_VV = 32'b000100???????????001?????1010111; + localparam [31:0] VFREDMIN_VS = 32'b000101???????????001?????1010111; + localparam [31:0] VFMAX_VV = 32'b000110???????????001?????1010111; + localparam [31:0] VFREDMAX_VS = 32'b000111???????????001?????1010111; + localparam [31:0] VFSGNJ_VV = 32'b001000???????????001?????1010111; + localparam [31:0] VFSGNJN_VV = 32'b001001???????????001?????1010111; + localparam [31:0] VFSGNJX_VV = 32'b001010???????????001?????1010111; + localparam [31:0] VFMV_F_S = 32'b0100001?????00000001?????1010111; + localparam [31:0] VMFEQ_VV = 32'b011000???????????001?????1010111; + localparam [31:0] VMFLE_VV = 32'b011001???????????001?????1010111; + localparam [31:0] VMFLT_VV = 32'b011011???????????001?????1010111; + localparam [31:0] VMFNE_VV = 32'b011100???????????001?????1010111; + localparam [31:0] VFDIV_VV = 32'b100000???????????001?????1010111; + localparam [31:0] VFMUL_VV = 32'b100100???????????001?????1010111; + localparam [31:0] VFMADD_VV = 32'b101000???????????001?????1010111; + localparam [31:0] VFNMADD_VV = 32'b101001???????????001?????1010111; + localparam [31:0] VFMSUB_VV = 32'b101010???????????001?????1010111; + localparam [31:0] VFNMSUB_VV = 32'b101011???????????001?????1010111; + localparam [31:0] VFMACC_VV = 32'b101100???????????001?????1010111; + localparam [31:0] VFNMACC_VV = 32'b101101???????????001?????1010111; + localparam [31:0] VFMSAC_VV = 32'b101110???????????001?????1010111; + localparam [31:0] VFNMSAC_VV = 32'b101111???????????001?????1010111; + localparam [31:0] VFCVT_XU_F_V = 32'b010010??????00000001?????1010111; + localparam [31:0] VFCVT_F_XU_V = 32'b010010??????00010001?????1010111; + localparam [31:0] VFCVT_F_X_V = 32'b010010??????00011001?????1010111; + localparam [31:0] VFCVT_RTZ_XU_F_V = 32'b010010??????00110001?????1010111; + localparam [31:0] VFCVT_RTZ_X_F_V = 32'b010010??????00111001?????1010111; + localparam [31:0] VFWCVT_XU_F_V = 32'b010010??????01000001?????1010111; + localparam [31:0] VFWCVT_X_F_V = 32'b010010??????01001001?????1010111; + localparam [31:0] VFWCVT_F_XU_V = 32'b010010??????01010001?????1010111; + localparam [31:0] VFWCVT_F_X_V = 32'b010010??????01011001?????1010111; + localparam [31:0] VFWCVT_F_F_V = 32'b010010??????01100001?????1010111; + localparam [31:0] VFWCVT_RTZ_XU_F_V = 32'b010010??????01110001?????1010111; + localparam [31:0] VFWCVT_RTZ_X_F_V = 32'b010010??????01111001?????1010111; + localparam [31:0] VFNCVT_XU_F_W = 32'b010010??????10000001?????1010111; + localparam [31:0] VFNCVT_X_F_W = 32'b010010??????10001001?????1010111; + localparam [31:0] VFNCVT_F_XU_W = 32'b010010??????10010001?????1010111; + localparam [31:0] VFNCVT_F_X_W = 32'b010010??????10011001?????1010111; + localparam [31:0] VFNCVT_F_F_W = 32'b010010??????10100001?????1010111; + localparam [31:0] VFNCVT_ROD_F_F_W = 32'b010010??????10101001?????1010111; + localparam [31:0] VFNCVT_RTZ_XU_F_W = 32'b010010??????10110001?????1010111; + localparam [31:0] VFNCVT_RTZ_X_F_W = 32'b010010??????10111001?????1010111; + localparam [31:0] VFSQRT_V = 32'b010011??????00000001?????1010111; + localparam [31:0] VFRSQRTE7_V = 32'b010011??????00100001?????1010111; + localparam [31:0] VFRECE7_V = 32'b010011??????00101001?????1010111; + localparam [31:0] VFCLASS_V = 32'b010011??????10000001?????1010111; + localparam [31:0] VFWADD_VV = 32'b110000???????????001?????1010111; + localparam [31:0] VFWREDSUM_VS = 32'b110001???????????001?????1010111; + localparam [31:0] VFWSUB_VV = 32'b110010???????????001?????1010111; + localparam [31:0] VFWREDOSUM_VS = 32'b110011???????????001?????1010111; + localparam [31:0] VFWADD_WV = 32'b110100???????????001?????1010111; + localparam [31:0] VFWSUB_WV = 32'b110110???????????001?????1010111; + localparam [31:0] VFWMUL_VV = 32'b111000???????????001?????1010111; + localparam [31:0] VFDOT_VV = 32'b111001???????????001?????1010111; + localparam [31:0] VFWMACC_VV = 32'b111100???????????001?????1010111; + localparam [31:0] VFWNMACC_VV = 32'b111101???????????001?????1010111; + localparam [31:0] VFWMSAC_VV = 32'b111110???????????001?????1010111; + localparam [31:0] VFWNMSAC_VV = 32'b111111???????????001?????1010111; + localparam [31:0] VADD_VX = 32'b000000???????????100?????1010111; + localparam [31:0] VSUB_VX = 32'b000010???????????100?????1010111; + localparam [31:0] VRSUB_VX = 32'b000011???????????100?????1010111; + localparam [31:0] VMINU_VX = 32'b000100???????????100?????1010111; + localparam [31:0] VMIN_VX = 32'b000101???????????100?????1010111; + localparam [31:0] VMAXU_VX = 32'b000110???????????100?????1010111; + localparam [31:0] VMAX_VX = 32'b000111???????????100?????1010111; + localparam [31:0] VAND_VX = 32'b001001???????????100?????1010111; + localparam [31:0] VOR_VX = 32'b001010???????????100?????1010111; + localparam [31:0] VXOR_VX = 32'b001011???????????100?????1010111; + localparam [31:0] VRGATHER_VX = 32'b001100???????????100?????1010111; + localparam [31:0] VSLIDEUP_VX = 32'b001110???????????100?????1010111; + localparam [31:0] VSLIDEDOWN_VX = 32'b001111???????????100?????1010111; + localparam [31:0] VMADC_VXM = 32'b010001???????????100?????1010111; + localparam [31:0] VMSBC_VXM = 32'b010011???????????100?????1010111; + localparam [31:0] VMERGE_VXM = 32'b0101110??????????100?????1010111; + localparam [31:0] VMV_V_X = 32'b010111100000?????100?????1010111; + localparam [31:0] VMSEQ_VX = 32'b011000???????????100?????1010111; + localparam [31:0] VMSNE_VX = 32'b011001???????????100?????1010111; + localparam [31:0] VMSLTU_VX = 32'b011010???????????100?????1010111; + localparam [31:0] VMSLT_VX = 32'b011011???????????100?????1010111; + localparam [31:0] VMSLEU_VX = 32'b011100???????????100?????1010111; + localparam [31:0] VMSLE_VX = 32'b011101???????????100?????1010111; + localparam [31:0] VMSGTU_VX = 32'b011110???????????100?????1010111; + localparam [31:0] VMSGT_VX = 32'b011111???????????100?????1010111; + localparam [31:0] VSADDU_VX = 32'b100000???????????100?????1010111; + localparam [31:0] VSADD_VX = 32'b100001???????????100?????1010111; + localparam [31:0] VSSUBU_VX = 32'b100010???????????100?????1010111; + localparam [31:0] VSSUB_VX = 32'b100011???????????100?????1010111; + localparam [31:0] VSLL_VX = 32'b100101???????????100?????1010111; + localparam [31:0] VSMUL_VX = 32'b100111???????????100?????1010111; + localparam [31:0] VSRL_VX = 32'b101000???????????100?????1010111; + localparam [31:0] VSRA_VX = 32'b101001???????????100?????1010111; + localparam [31:0] VSSRL_VX = 32'b101010???????????100?????1010111; + localparam [31:0] VSSRA_VX = 32'b101011???????????100?????1010111; + localparam [31:0] VNSRL_WX = 32'b101100???????????100?????1010111; + localparam [31:0] VNSRA_WX = 32'b101101???????????100?????1010111; + localparam [31:0] VNCLIPU_WX = 32'b101110???????????100?????1010111; + localparam [31:0] VNCLIP_WX = 32'b101111???????????100?????1010111; + localparam [31:0] VQMACCU_VX = 32'b111100???????????100?????1010111; + localparam [31:0] VQMACC_VX = 32'b111101???????????100?????1010111; + localparam [31:0] VQMACCUS_VX = 32'b111110???????????100?????1010111; + localparam [31:0] VQMACCSU_VX = 32'b111111???????????100?????1010111; + localparam [31:0] VADD_VV = 32'b000000???????????000?????1010111; + localparam [31:0] VSUB_VV = 32'b000010???????????000?????1010111; + localparam [31:0] VMINU_VV = 32'b000100???????????000?????1010111; + localparam [31:0] VMIN_VV = 32'b000101???????????000?????1010111; + localparam [31:0] VMAXU_VV = 32'b000110???????????000?????1010111; + localparam [31:0] VMAX_VV = 32'b000111???????????000?????1010111; + localparam [31:0] VAND_VV = 32'b001001???????????000?????1010111; + localparam [31:0] VOR_VV = 32'b001010???????????000?????1010111; + localparam [31:0] VXOR_VV = 32'b001011???????????000?????1010111; + localparam [31:0] VRGATHER_VV = 32'b001100???????????000?????1010111; + localparam [31:0] VRGATHEREI16_VV = 32'b001110???????????000?????1010111; + localparam [31:0] VMADC_VVM = 32'b010001???????????000?????1010111; + localparam [31:0] VMSBC_VVM = 32'b010011???????????000?????1010111; + localparam [31:0] VMERGE_VVM = 32'b0101110??????????000?????1010111; + localparam [31:0] VMV_V_V = 32'b010111100000?????000?????1010111; + localparam [31:0] VMSEQ_VV = 32'b011000???????????000?????1010111; + localparam [31:0] VMSNE_VV = 32'b011001???????????000?????1010111; + localparam [31:0] VMSLTU_VV = 32'b011010???????????000?????1010111; + localparam [31:0] VMSLT_VV = 32'b011011???????????000?????1010111; + localparam [31:0] VMSLEU_VV = 32'b011100???????????000?????1010111; + localparam [31:0] VMSLE_VV = 32'b011101???????????000?????1010111; + localparam [31:0] VSADDU_VV = 32'b100000???????????000?????1010111; + localparam [31:0] VSADD_VV = 32'b100001???????????000?????1010111; + localparam [31:0] VSSUBU_VV = 32'b100010???????????000?????1010111; + localparam [31:0] VSSUB_VV = 32'b100011???????????000?????1010111; + localparam [31:0] VSLL_VV = 32'b100101???????????000?????1010111; + localparam [31:0] VSMUL_VV = 32'b100111???????????000?????1010111; + localparam [31:0] VSRL_VV = 32'b101000???????????000?????1010111; + localparam [31:0] VSRA_VV = 32'b101001???????????000?????1010111; + localparam [31:0] VSSRL_VV = 32'b101010???????????000?????1010111; + localparam [31:0] VSSRA_VV = 32'b101011???????????000?????1010111; + localparam [31:0] VNSRL_WV = 32'b101100???????????000?????1010111; + localparam [31:0] VNSRA_WV = 32'b101101???????????000?????1010111; + localparam [31:0] VNCLIPU_WV = 32'b101110???????????000?????1010111; + localparam [31:0] VNCLIP_WV = 32'b101111???????????000?????1010111; + localparam [31:0] VWREDSUMU_VS = 32'b110000???????????000?????1010111; + localparam [31:0] VWREDSUM_VS = 32'b110001???????????000?????1010111; + localparam [31:0] VDOTU_VV = 32'b111000???????????000?????1010111; + localparam [31:0] VDOT_VV = 32'b111001???????????000?????1010111; + localparam [31:0] VQMACCU_VV = 32'b111100???????????000?????1010111; + localparam [31:0] VQMACC_VV = 32'b111101???????????000?????1010111; + localparam [31:0] VQMACCSU_VV = 32'b111111???????????000?????1010111; + localparam [31:0] VADD_VI = 32'b000000???????????011?????1010111; + localparam [31:0] VRSUB_VI = 32'b000011???????????011?????1010111; + localparam [31:0] VAND_VI = 32'b001001???????????011?????1010111; + localparam [31:0] VOR_VI = 32'b001010???????????011?????1010111; + localparam [31:0] VXOR_VI = 32'b001011???????????011?????1010111; + localparam [31:0] VRGATHER_VI = 32'b001100???????????011?????1010111; + localparam [31:0] VSLIDEUP_VI = 32'b001110???????????011?????1010111; + localparam [31:0] VSLIDEDOWN_VI = 32'b001111???????????011?????1010111; + localparam [31:0] VADC_VIM = 32'b0100000??????????011?????1010111; + localparam [31:0] VMADC_VIM = 32'b010001???????????011?????1010111; + localparam [31:0] VMERGE_VIM = 32'b0101110??????????011?????1010111; + localparam [31:0] VMV_V_I = 32'b010111100000?????011?????1010111; + localparam [31:0] VMSEQ_VI = 32'b011000???????????011?????1010111; + localparam [31:0] VMSNE_VI = 32'b011001???????????011?????1010111; + localparam [31:0] VMSLEU_VI = 32'b011100???????????011?????1010111; + localparam [31:0] VMSLE_VI = 32'b011101???????????011?????1010111; + localparam [31:0] VMSGTU_VI = 32'b011110???????????011?????1010111; + localparam [31:0] VMSGT_VI = 32'b011111???????????011?????1010111; + localparam [31:0] VSADDU_VI = 32'b100000???????????011?????1010111; + localparam [31:0] VSADD_VI = 32'b100001???????????011?????1010111; + localparam [31:0] VSLL_VI = 32'b100101???????????011?????1010111; + localparam [31:0] VMV1R_V = 32'b1001111?????00000011?????1010111; + localparam [31:0] VMV2R_V = 32'b1001111?????00001011?????1010111; + localparam [31:0] VMV4R_V = 32'b1001111?????00011011?????1010111; + localparam [31:0] VMV8R_V = 32'b1001111?????00111011?????1010111; + localparam [31:0] VSRL_VI = 32'b101000???????????011?????1010111; + localparam [31:0] VSRA_VI = 32'b101001???????????011?????1010111; + localparam [31:0] VSSRL_VI = 32'b101010???????????011?????1010111; + localparam [31:0] VSSRA_VI = 32'b101011???????????011?????1010111; + localparam [31:0] VNSRL_WI = 32'b101100???????????011?????1010111; + localparam [31:0] VNSRA_WI = 32'b101101???????????011?????1010111; + localparam [31:0] VNCLIPU_WI = 32'b101110???????????011?????1010111; + localparam [31:0] VNCLIP_WI = 32'b101111???????????011?????1010111; + localparam [31:0] VREDSUM_VS = 32'b000000???????????010?????1010111; + localparam [31:0] VREDAND_VS = 32'b000001???????????010?????1010111; + localparam [31:0] VREDOR_VS = 32'b000010???????????010?????1010111; + localparam [31:0] VREDXOR_VS = 32'b000011???????????010?????1010111; + localparam [31:0] VREDMINU_VS = 32'b000100???????????010?????1010111; + localparam [31:0] VREDMIN_VS = 32'b000101???????????010?????1010111; + localparam [31:0] VREDMAXU_VS = 32'b000110???????????010?????1010111; + localparam [31:0] VREDMAX_VS = 32'b000111???????????010?????1010111; + localparam [31:0] VAADDU_VV = 32'b001000???????????010?????1010111; + localparam [31:0] VAADD_VV = 32'b001001???????????010?????1010111; + localparam [31:0] VASUBU_VV = 32'b001010???????????010?????1010111; + localparam [31:0] VASUB_VV = 32'b001011???????????010?????1010111; + localparam [31:0] VMV_X_S = 32'b0100001?????00000010?????1010111; + localparam [31:0] VZEXT_VF8 = 32'b010010??????00010010?????1010111; + localparam [31:0] VSEXT_VF8 = 32'b010010??????00011010?????1010111; + localparam [31:0] VZEXT_VF4 = 32'b010010??????00100010?????1010111; + localparam [31:0] VSEXT_VF4 = 32'b010010??????00101010?????1010111; + localparam [31:0] VZEXT_VF2 = 32'b010010??????00110010?????1010111; + localparam [31:0] VSEXT_VF2 = 32'b010010??????00111010?????1010111; + localparam [31:0] VCOMPRESS_VM = 32'b0101111??????????010?????1010111; + localparam [31:0] VMANDNOT_MM = 32'b011000???????????010?????1010111; + localparam [31:0] VMAND_MM = 32'b011001???????????010?????1010111; + localparam [31:0] VMOR_MM = 32'b011010???????????010?????1010111; + localparam [31:0] VMXOR_MM = 32'b011011???????????010?????1010111; + localparam [31:0] VMORNOT_MM = 32'b011100???????????010?????1010111; + localparam [31:0] VMNAND_MM = 32'b011101???????????010?????1010111; + localparam [31:0] VMNOR_MM = 32'b011110???????????010?????1010111; + localparam [31:0] VMXNOR_MM = 32'b011111???????????010?????1010111; + localparam [31:0] VMSBF_M = 32'b010100??????00001010?????1010111; + localparam [31:0] VMSOF_M = 32'b010100??????00010010?????1010111; + localparam [31:0] VMSIF_M = 32'b010100??????00011010?????1010111; + localparam [31:0] VIOTA_M = 32'b010100??????10000010?????1010111; + localparam [31:0] VID_V = 32'b010100?0000010001010?????1010111; + localparam [31:0] VPOPC_M = 32'b010000??????10000010?????1010111; + localparam [31:0] VFIRST_M = 32'b010000??????10001010?????1010111; + localparam [31:0] VDIVU_VV = 32'b100000???????????010?????1010111; + localparam [31:0] VDIV_VV = 32'b100001???????????010?????1010111; + localparam [31:0] VREMU_VV = 32'b100010???????????010?????1010111; + localparam [31:0] VREM_VV = 32'b100011???????????010?????1010111; + localparam [31:0] VMULHU_VV = 32'b100100???????????010?????1010111; + localparam [31:0] VMUL_VV = 32'b100101???????????010?????1010111; + localparam [31:0] VMULHSU_VV = 32'b100110???????????010?????1010111; + localparam [31:0] VMULH_VV = 32'b100111???????????010?????1010111; + localparam [31:0] VMADD_VV = 32'b101001???????????010?????1010111; + localparam [31:0] VNMSUB_VV = 32'b101011???????????010?????1010111; + localparam [31:0] VMACC_VV = 32'b101101???????????010?????1010111; + localparam [31:0] VNMSAC_VV = 32'b101111???????????010?????1010111; + localparam [31:0] VWADDU_VV = 32'b110000???????????010?????1010111; + localparam [31:0] VWADD_VV = 32'b110001???????????010?????1010111; + localparam [31:0] VWSUBU_VV = 32'b110010???????????010?????1010111; + localparam [31:0] VWSUB_VV = 32'b110011???????????010?????1010111; + localparam [31:0] VWADDU_WV = 32'b110100???????????010?????1010111; + localparam [31:0] VWADD_WV = 32'b110101???????????010?????1010111; + localparam [31:0] VWSUBU_WV = 32'b110110???????????010?????1010111; + localparam [31:0] VWSUB_WV = 32'b110111???????????010?????1010111; + localparam [31:0] VWMULU_VV = 32'b111000???????????010?????1010111; + localparam [31:0] VWMULSU_VV = 32'b111010???????????010?????1010111; + localparam [31:0] VWMUL_VV = 32'b111011???????????010?????1010111; + localparam [31:0] VWMACCU_VV = 32'b111100???????????010?????1010111; + localparam [31:0] VWMACC_VV = 32'b111101???????????010?????1010111; + localparam [31:0] VWMACCSU_VV = 32'b111111???????????010?????1010111; + localparam [31:0] VAADD_VX = 32'b001001???????????110?????1010111; + localparam [31:0] VASUB_VX = 32'b001011???????????110?????1010111; + localparam [31:0] VMV_S_X = 32'b010000100000?????110?????1010111; + localparam [31:0] VSLIDE1DOWN_VX = 32'b001111???????????110?????1010111; + localparam [31:0] VDIV_VX = 32'b100001???????????110?????1010111; + localparam [31:0] VREMU_VX = 32'b100010???????????110?????1010111; + localparam [31:0] VREM_VX = 32'b100011???????????110?????1010111; + localparam [31:0] VMUL_VX = 32'b100101???????????110?????1010111; + localparam [31:0] VMULH_VX = 32'b100111???????????110?????1010111; + localparam [31:0] VMADD_VX = 32'b101001???????????110?????1010111; + localparam [31:0] VNMSUB_VX = 32'b101011???????????110?????1010111; + localparam [31:0] VMACC_VX = 32'b101101???????????110?????1010111; + localparam [31:0] VNMSAC_VX = 32'b101111???????????110?????1010111; + localparam [31:0] VWADDU_VX = 32'b110000???????????110?????1010111; + localparam [31:0] VWADD_VX = 32'b110001???????????110?????1010111; + localparam [31:0] VWSUBU_VX = 32'b110010???????????110?????1010111; + localparam [31:0] VWSUB_VX = 32'b110011???????????110?????1010111; + localparam [31:0] VWADDU_WX = 32'b110100???????????110?????1010111; + localparam [31:0] VWADD_WX = 32'b110101???????????110?????1010111; + localparam [31:0] VWSUBU_WX = 32'b110110???????????110?????1010111; + localparam [31:0] VWSUB_WX = 32'b110111???????????110?????1010111; + localparam [31:0] VWMULU_VX = 32'b111000???????????110?????1010111; + localparam [31:0] VWMULSU_VX = 32'b111010???????????110?????1010111; + localparam [31:0] VWMUL_VX = 32'b111011???????????110?????1010111; + localparam [31:0] VWMACCU_VX = 32'b111100???????????110?????1010111; + localparam [31:0] VWMACC_VX = 32'b111101???????????110?????1010111; + localparam [31:0] VWMACCUS_VX = 32'b111110???????????110?????1010111; + localparam [31:0] VWMACCSU_VX = 32'b111111???????????110?????1010111; + localparam [31:0] VAMOSWAPEI8_V = 32'b00001????????????000?????0101111; + localparam [31:0] VAMOADDEI8_V = 32'b00000????????????000?????0101111; + localparam [31:0] VAMOXOREI8_V = 32'b00100????????????000?????0101111; + localparam [31:0] VAMOANDEI8_V = 32'b01100????????????000?????0101111; + localparam [31:0] VAMOOREI8_V = 32'b01000????????????000?????0101111; + localparam [31:0] VAMOMINEI8_V = 32'b10000????????????000?????0101111; + localparam [31:0] VAMOMAXEI8_V = 32'b10100????????????000?????0101111; + localparam [31:0] VAMOMINUEI8_V = 32'b11000????????????000?????0101111; + localparam [31:0] VAMOMAXUEI8_V = 32'b11100????????????000?????0101111; + localparam [31:0] VAMOSWAPEI16_V = 32'b00001????????????101?????0101111; + localparam [31:0] VAMOADDEI16_V = 32'b00000????????????101?????0101111; + localparam [31:0] VAMOXOREI16_V = 32'b00100????????????101?????0101111; + localparam [31:0] VAMOANDEI16_V = 32'b01100????????????101?????0101111; + localparam [31:0] VAMOOREI16_V = 32'b01000????????????101?????0101111; + localparam [31:0] VAMOMINEI16_V = 32'b10000????????????101?????0101111; + localparam [31:0] VAMOMAXEI16_V = 32'b10100????????????101?????0101111; + localparam [31:0] VAMOMINUEI16_V = 32'b11000????????????101?????0101111; + localparam [31:0] VAMOMAXUEI16_V = 32'b11100????????????101?????0101111; + localparam [31:0] VAMOSWAPEI32_V = 32'b00001????????????110?????0101111; + localparam [31:0] VAMOADDEI32_V = 32'b00000????????????110?????0101111; + localparam [31:0] VAMOXOREI32_V = 32'b00100????????????110?????0101111; + localparam [31:0] VAMOANDEI32_V = 32'b01100????????????110?????0101111; + localparam [31:0] VAMOOREI32_V = 32'b01000????????????110?????0101111; + localparam [31:0] VAMOMINEI32_V = 32'b10000????????????110?????0101111; + localparam [31:0] VAMOMAXEI32_V = 32'b10100????????????110?????0101111; + localparam [31:0] VAMOMINUEI32_V = 32'b11000????????????110?????0101111; + localparam [31:0] VAMOMAXUEI32_V = 32'b11100????????????110?????0101111; + localparam [31:0] VAMOSWAPEI64_V = 32'b00001????????????111?????0101111; + localparam [31:0] VAMOADDEI64_V = 32'b00000????????????111?????0101111; + localparam [31:0] VAMOXOREI64_V = 32'b00100????????????111?????0101111; + localparam [31:0] VAMOANDEI64_V = 32'b01100????????????111?????0101111; + localparam [31:0] VAMOOREI64_V = 32'b01000????????????111?????0101111; + localparam [31:0] VAMOMINEI64_V = 32'b10000????????????111?????0101111; + localparam [31:0] VAMOMAXEI64_V = 32'b10100????????????111?????0101111; + localparam [31:0] VAMOMINUEI64_V = 32'b11000????????????111?????0101111; + localparam [31:0] VAMOMAXUEI64_V = 32'b11100????????????111?????0101111; + localparam [31:0] VMVNFR_V = 32'b1001111??????????011?????1010111; + localparam [31:0] VL1R_V = 32'b000000101000?????000?????0000111; + localparam [31:0] VL2R_V = 32'b000001101000?????101?????0000111; + localparam [31:0] VL4R_V = 32'b000011101000?????110?????0000111; + localparam [31:0] VL8R_V = 32'b000111101000?????111?????0000111; + localparam [31:0] ECALL = 32'b00000000000000000000000001110011; + localparam [31:0] EBREAK = 32'b00000000000100000000000001110011; + localparam [31:0] URET = 32'b00000000001000000000000001110011; + localparam [31:0] SRET = 32'b00010000001000000000000001110011; + localparam [31:0] MRET = 32'b00110000001000000000000001110011; + localparam [31:0] DRET = 32'b01111011001000000000000001110011; + localparam [31:0] SFENCE_VMA = 32'b0001001??????????000000001110011; + localparam [31:0] WFI = 32'b00010000010100000000000001110011; + localparam [31:0] CSRRW = 32'b?????????????????001?????1110011; + localparam [31:0] CSRRS = 32'b?????????????????010?????1110011; + localparam [31:0] CSRRC = 32'b?????????????????011?????1110011; + localparam [31:0] CSRRWI = 32'b?????????????????101?????1110011; + localparam [31:0] CSRRSI = 32'b?????????????????110?????1110011; + localparam [31:0] CSRRCI = 32'b?????????????????111?????1110011; + localparam [31:0] P_LB_IRPOST = 32'b?????????????????000?????0001011; + localparam [31:0] P_LBU_IRPOST = 32'b?????????????????100?????0001011; + localparam [31:0] P_LH_IRPOST = 32'b?????????????????001?????0001011; + localparam [31:0] P_LHU_IRPOST = 32'b?????????????????101?????0001011; + localparam [31:0] P_LW_IRPOST = 32'b?????????????????010?????0001011; + localparam [31:0] P_LB_RRPOST = 32'b0000000??????????111?????0001011; + localparam [31:0] P_LBU_RRPOST = 32'b0100000??????????111?????0001011; + localparam [31:0] P_LH_RRPOST = 32'b0001000??????????111?????0001011; + localparam [31:0] P_LHU_RRPOST = 32'b0101000??????????111?????0001011; + localparam [31:0] P_LW_RRPOST = 32'b0010000??????????111?????0001011; + localparam [31:0] P_LB_RR = 32'b0000000??????????111?????0000011; + localparam [31:0] P_LBU_RR = 32'b0100000??????????111?????0000011; + localparam [31:0] P_LH_RR = 32'b0001000??????????111?????0000011; + localparam [31:0] P_LHU_RR = 32'b0101000??????????111?????0000011; + localparam [31:0] P_LW_RR = 32'b0010000??????????111?????0000011; + localparam [31:0] P_SB_IRPOST = 32'b?????????????????000?????0101011; + localparam [31:0] P_SH_IRPOST = 32'b?????????????????001?????0101011; + localparam [31:0] P_SW_IRPOST = 32'b?????????????????010?????0101011; + localparam [31:0] P_SB_RRPOST = 32'b0000000??????????100?????0101011; + localparam [31:0] P_SH_RRPOST = 32'b0000000??????????101?????0101011; + localparam [31:0] P_SW_RRPOST = 32'b0000000??????????110?????0101011; + localparam [31:0] P_SB_RR = 32'b0000000??????????100?????0100011; + localparam [31:0] P_SH_RR = 32'b0000000??????????101?????0100011; + localparam [31:0] P_SW_RR = 32'b0000000??????????110?????0100011; + localparam [31:0] P_ABS = 32'b000001000000?????000?????0110011; + localparam [31:0] P_SLET = 32'b0000010??????????010?????0110011; + localparam [31:0] P_SLETU = 32'b0000010??????????011?????0110011; + localparam [31:0] P_MIN = 32'b0000010??????????100?????0110011; + localparam [31:0] P_MINU = 32'b0000010??????????101?????0110011; + localparam [31:0] P_MAX = 32'b0000010??????????110?????0110011; + localparam [31:0] P_MAXU = 32'b0000010??????????111?????0110011; + localparam [31:0] P_EXTHS = 32'b000100000000?????100?????0110011; + localparam [31:0] P_EXTHZ = 32'b000100000000?????101?????0110011; + localparam [31:0] P_EXTBS = 32'b000100000000?????110?????0110011; + localparam [31:0] P_EXTBZ = 32'b000100000000?????111?????0110011; + localparam [31:0] P_CLIP = 32'b0001010??????????001?????0110011; + localparam [31:0] P_CLIPU = 32'b0001010??????????010?????0110011; + localparam [31:0] P_CLIPR = 32'b0001010??????????101?????0110011; + localparam [31:0] P_CLIPUR = 32'b0001010??????????110?????0110011; + localparam [31:0] P_BEQIMM = 32'b?????????????????010?????1100011; + localparam [31:0] P_BNEIMM = 32'b?????????????????011?????1100011; + localparam [31:0] P_MAC = 32'b0100001??????????000?????0110011; + localparam [31:0] P_MSU = 32'b0100001??????????001?????0110011; + localparam [31:0] PV_ADD_H = 32'b0000000??????????000?????1010111; + localparam [31:0] PV_ADD_SC_H = 32'b0000000??????????100?????1010111; + localparam [31:0] PV_ADD_SCI_H = 32'b000000???????????110?????1010111; + localparam [31:0] PV_ADD_B = 32'b0000000??????????001?????1010111; + localparam [31:0] PV_ADD_SC_B = 32'b0000000??????????101?????1010111; + localparam [31:0] PV_ADD_SCI_B = 32'b000000???????????111?????1010111; + localparam [31:0] PV_SUB_H = 32'b0000100??????????000?????1010111; + localparam [31:0] PV_SUB_SC_H = 32'b0000100??????????100?????1010111; + localparam [31:0] PV_SUB_SCI_H = 32'b000010???????????110?????1010111; + localparam [31:0] PV_SUB_B = 32'b0000100??????????001?????1010111; + localparam [31:0] PV_SUB_SC_B = 32'b0000100??????????101?????1010111; + localparam [31:0] PV_SUB_SCI_B = 32'b000010???????????111?????1010111; + localparam [31:0] PV_AVG_H = 32'b0001000??????????000?????1010111; + localparam [31:0] PV_AVG_SC_H = 32'b0001000??????????100?????1010111; + localparam [31:0] PV_AVG_SCI_H = 32'b000100???????????110?????1010111; + localparam [31:0] PV_AVG_B = 32'b0001000??????????001?????1010111; + localparam [31:0] PV_AVG_SC_B = 32'b0001000??????????101?????1010111; + localparam [31:0] PV_AVG_SCI_B = 32'b000100???????????111?????1010111; + localparam [31:0] PV_AVGU_H = 32'b0001100??????????000?????1010111; + localparam [31:0] PV_AVGU_SC_H = 32'b0001100??????????100?????1010111; + localparam [31:0] PV_AVGU_SCI_H = 32'b000110???????????110?????1010111; + localparam [31:0] PV_AVGU_B = 32'b0001100??????????001?????1010111; + localparam [31:0] PV_AVGU_SC_B = 32'b0001100??????????101?????1010111; + localparam [31:0] PV_AVGU_SCI_B = 32'b000110???????????111?????1010111; + localparam [31:0] PV_MIN_H = 32'b0010000??????????000?????1010111; + localparam [31:0] PV_MIN_SC_H = 32'b0010000??????????100?????1010111; + localparam [31:0] PV_MIN_SCI_H = 32'b001000???????????110?????1010111; + localparam [31:0] PV_MIN_B = 32'b0010000??????????001?????1010111; + localparam [31:0] PV_MIN_SC_B = 32'b0010000??????????101?????1010111; + localparam [31:0] PV_MIN_SCI_B = 32'b001000???????????111?????1010111; + localparam [31:0] PV_MINU_H = 32'b0010100??????????000?????1010111; + localparam [31:0] PV_MINU_SC_H = 32'b0010100??????????100?????1010111; + localparam [31:0] PV_MINU_SCI_H = 32'b001010???????????110?????1010111; + localparam [31:0] PV_MINU_B = 32'b0010100??????????001?????1010111; + localparam [31:0] PV_MINU_SC_B = 32'b0010100??????????101?????1010111; + localparam [31:0] PV_MINU_SCI_B = 32'b001010???????????111?????1010111; + localparam [31:0] PV_MAX_H = 32'b0011000??????????000?????1010111; + localparam [31:0] PV_MAX_SC_H = 32'b0011000??????????100?????1010111; + localparam [31:0] PV_MAX_SCI_H = 32'b001100???????????110?????1010111; + localparam [31:0] PV_MAX_B = 32'b0011000??????????001?????1010111; + localparam [31:0] PV_MAX_SC_B = 32'b0011000??????????101?????1010111; + localparam [31:0] PV_MAX_SCI_B = 32'b001100???????????111?????1010111; + localparam [31:0] PV_MAXU_H = 32'b0011100??????????000?????1010111; + localparam [31:0] PV_MAXU_SC_H = 32'b0011100??????????100?????1010111; + localparam [31:0] PV_MAXU_SCI_H = 32'b001110???????????110?????1010111; + localparam [31:0] PV_MAXU_B = 32'b0011100??????????001?????1010111; + localparam [31:0] PV_MAXU_SC_B = 32'b0011100??????????101?????1010111; + localparam [31:0] PV_MAXU_SCI_B = 32'b001110???????????111?????1010111; + localparam [31:0] PV_SRL_H = 32'b0100000??????????000?????1010111; + localparam [31:0] PV_SRL_SC_H = 32'b0100000??????????100?????1010111; + localparam [31:0] PV_SRL_SCI_H = 32'b010000???????????110?????1010111; + localparam [31:0] PV_SRL_B = 32'b0100000??????????001?????1010111; + localparam [31:0] PV_SRL_SC_B = 32'b0100000??????????101?????1010111; + localparam [31:0] PV_SRL_SCI_B = 32'b010000???????????111?????1010111; + localparam [31:0] PV_SRA_H = 32'b0100100??????????000?????1010111; + localparam [31:0] PV_SRA_SC_H = 32'b0100100??????????100?????1010111; + localparam [31:0] PV_SRA_SCI_H = 32'b010010???????????110?????1010111; + localparam [31:0] PV_SRA_B = 32'b0100100??????????001?????1010111; + localparam [31:0] PV_SRA_SC_B = 32'b0100100??????????101?????1010111; + localparam [31:0] PV_SRA_SCI_B = 32'b010010???????????111?????1010111; + localparam [31:0] PV_SLL_H = 32'b0101000??????????000?????1010111; + localparam [31:0] PV_SLL_SC_H = 32'b0101000??????????100?????1010111; + localparam [31:0] PV_SLL_SCI_H = 32'b010100???????????110?????1010111; + localparam [31:0] PV_SLL_B = 32'b0101000??????????001?????1010111; + localparam [31:0] PV_SLL_SC_B = 32'b0101000??????????101?????1010111; + localparam [31:0] PV_SLL_SCI_B = 32'b010100???????????111?????1010111; + localparam [31:0] PV_OR_H = 32'b0101100??????????000?????1010111; + localparam [31:0] PV_OR_SC_H = 32'b0101100??????????100?????1010111; + localparam [31:0] PV_OR_SCI_H = 32'b010110???????????110?????1010111; + localparam [31:0] PV_OR_B = 32'b0101100??????????001?????1010111; + localparam [31:0] PV_OR_SC_B = 32'b0101100??????????101?????1010111; + localparam [31:0] PV_OR_SCI_B = 32'b010110???????????111?????1010111; + localparam [31:0] PV_XOR_H = 32'b0110000??????????000?????1010111; + localparam [31:0] PV_XOR_SC_H = 32'b0110000??????????100?????1010111; + localparam [31:0] PV_XOR_SCI_H = 32'b011000???????????110?????1010111; + localparam [31:0] PV_XOR_B = 32'b0110000??????????001?????1010111; + localparam [31:0] PV_XOR_SC_B = 32'b0110000??????????101?????1010111; + localparam [31:0] PV_XOR_SCI_B = 32'b011000???????????111?????1010111; + localparam [31:0] PV_AND_H = 32'b0110100??????????000?????1010111; + localparam [31:0] PV_AND_SC_H = 32'b0110100??????????100?????1010111; + localparam [31:0] PV_AND_SCI_H = 32'b011010???????????110?????1010111; + localparam [31:0] PV_AND_B = 32'b0110100??????????001?????1010111; + localparam [31:0] PV_AND_SC_B = 32'b0110100??????????101?????1010111; + localparam [31:0] PV_AND_SCI_B = 32'b011010???????????111?????1010111; + localparam [31:0] PV_ABS_H = 32'b011100000000?????000?????1010111; + localparam [31:0] PV_ABS_B = 32'b011100000000?????001?????1010111; + localparam [31:0] PV_EXTRACT_H = 32'b011110???????????110?????1010111; + localparam [31:0] PV_EXTRACT_B = 32'b011110???????????111?????1010111; + localparam [31:0] PV_EXTRACTU_H = 32'b100100???????????110?????1010111; + localparam [31:0] PV_EXTRACTU_B = 32'b100100???????????111?????1010111; + localparam [31:0] PV_INSERT_H = 32'b101100???????????110?????1010111; + localparam [31:0] PV_INSERT_B = 32'b101100???????????111?????1010111; + localparam [31:0] PV_DOTUP_H = 32'b1000000??????????000?????1010111; + localparam [31:0] PV_DOTUP_SC_H = 32'b1000000??????????100?????1010111; + localparam [31:0] PV_DOTUP_SCI_H = 32'b100000???????????110?????1010111; + localparam [31:0] PV_DOTUP_B = 32'b1000000??????????001?????1010111; + localparam [31:0] PV_DOTUP_SC_B = 32'b1000000??????????101?????1010111; + localparam [31:0] PV_DOTUP_SCI_B = 32'b100000???????????111?????1010111; + localparam [31:0] PV_DOTUSP_H = 32'b1000100??????????000?????1010111; + localparam [31:0] PV_DOTUSP_SC_H = 32'b1000100??????????100?????1010111; + localparam [31:0] PV_DOTUSP_SCI_H = 32'b100010???????????110?????1010111; + localparam [31:0] PV_DOTUSP_B = 32'b1000100??????????001?????1010111; + localparam [31:0] PV_DOTUSP_SC_B = 32'b1000100??????????101?????1010111; + localparam [31:0] PV_DOTUSP_SCI_B = 32'b100010???????????111?????1010111; + localparam [31:0] PV_DOTSP_H = 32'b1001100??????????000?????1010111; + localparam [31:0] PV_DOTSP_SC_H = 32'b1001100??????????100?????1010111; + localparam [31:0] PV_DOTSP_SCI_H = 32'b100110???????????110?????1010111; + localparam [31:0] PV_DOTSP_B = 32'b1001100??????????001?????1010111; + localparam [31:0] PV_DOTSP_SC_B = 32'b1001100??????????101?????1010111; + localparam [31:0] PV_DOTSP_SCI_B = 32'b100110???????????111?????1010111; + localparam [31:0] PV_SDOTUP_H = 32'b1010000??????????000?????1010111; + localparam [31:0] PV_SDOTUP_SC_H = 32'b1010000??????????100?????1010111; + localparam [31:0] PV_SDOTUP_SCI_H = 32'b101000???????????110?????1010111; + localparam [31:0] PV_SDOTUP_B = 32'b1010000??????????001?????1010111; + localparam [31:0] PV_SDOTUP_SC_B = 32'b1010000??????????101?????1010111; + localparam [31:0] PV_SDOTUP_SCI_B = 32'b101000???????????111?????1010111; + localparam [31:0] PV_SDOTUSP_H = 32'b1010100??????????000?????1010111; + localparam [31:0] PV_SDOTUSP_SC_H = 32'b1010100??????????100?????1010111; + localparam [31:0] PV_SDOTUSP_SCI_H = 32'b101010???????????110?????1010111; + localparam [31:0] PV_SDOTUSP_B = 32'b1010100??????????001?????1010111; + localparam [31:0] PV_SDOTUSP_SC_B = 32'b1010100??????????101?????1010111; + localparam [31:0] PV_SDOTUSP_SCI_B = 32'b101010???????????111?????1010111; + localparam [31:0] PV_SDOTSP_H = 32'b1011100??????????000?????1010111; + localparam [31:0] PV_SDOTSP_SC_H = 32'b1011100??????????100?????1010111; + localparam [31:0] PV_SDOTSP_SCI_H = 32'b101110???????????110?????1010111; + localparam [31:0] PV_SDOTSP_B = 32'b1011100??????????001?????1010111; + localparam [31:0] PV_SDOTSP_SC_B = 32'b1011100??????????101?????1010111; + localparam [31:0] PV_SDOTSP_SCI_B = 32'b101110???????????111?????1010111; + localparam [31:0] PV_SHUFFLE2_H = 32'b1100100??????????000?????1010111; + localparam [31:0] PV_SHUFFLE2_B = 32'b1100100??????????001?????1010111; + localparam [31:0] FLAH = 32'b?????????????????001?????0000111; + localparam [31:0] FSAH = 32'b?????????????????001?????0100111; + localparam [31:0] FMADD_AH = 32'b?????10??????????101?????1000011; + localparam [31:0] FMSUB_AH = 32'b?????10??????????101?????1000111; + localparam [31:0] FNMSUB_AH = 32'b?????10??????????101?????1001011; + localparam [31:0] FNMADD_AH = 32'b?????10??????????101?????1001111; + localparam [31:0] FADD_AH = 32'b0000010??????????101?????1010011; + localparam [31:0] FSUB_AH = 32'b0000110??????????101?????1010011; + localparam [31:0] FMUL_AH = 32'b0001010??????????101?????1010011; + localparam [31:0] FDIV_AH = 32'b0001110??????????101?????1010011; + localparam [31:0] FSQRT_AH = 32'b010111000000?????101?????1010011; + localparam [31:0] FSGNJ_AH = 32'b0010010??????????100?????1010011; + localparam [31:0] FSGNJN_AH = 32'b0010010??????????101?????1010011; + localparam [31:0] FSGNJX_AH = 32'b0010010??????????110?????1010011; + localparam [31:0] FMIN_AH = 32'b0010110??????????100?????1010011; + localparam [31:0] FMAX_AH = 32'b0010110??????????101?????1010011; + localparam [31:0] FEQ_AH = 32'b1010010??????????110?????1010011; + localparam [31:0] FLT_AH = 32'b1010010??????????101?????1010011; + localparam [31:0] FLE_AH = 32'b1010010??????????100?????1010011; + localparam [31:0] FCVT_W_AH = 32'b110001000000?????101?????1010011; + localparam [31:0] FCVT_WU_AH = 32'b110001000001?????101?????1010011; + localparam [31:0] FCVT_AH_W = 32'b110101000000?????101?????1010011; + localparam [31:0] FCVT_AH_WU = 32'b110101000001?????101?????1010011; + localparam [31:0] FMV_X_AH = 32'b111001000000?????100?????1010011; + localparam [31:0] FCLASS_AH = 32'b111001000000?????101?????1010011; + localparam [31:0] FMV_AH_X = 32'b111101000000?????100?????1010011; + localparam [31:0] FCVT_L_AH = 32'b110001000010?????101?????1010011; + localparam [31:0] FCVT_LU_AH = 32'b110001000011?????101?????1010011; + localparam [31:0] FCVT_AH_L = 32'b110101000010?????101?????1010011; + localparam [31:0] FCVT_AH_LU = 32'b110101000011?????101?????1010011; + localparam [31:0] FCVT_S_AH = 32'b010000000110?????000?????1010011; + localparam [31:0] FCVT_AH_S = 32'b010001000000?????101?????1010011; + localparam [31:0] FCVT_D_AH = 32'b010000100110?????000?????1010011; + localparam [31:0] FCVT_AH_D = 32'b010001000001?????101?????1010011; + localparam [31:0] FCVT_H_AH = 32'b010001000110?????????????1010011; + localparam [31:0] FCVT_AH_H = 32'b010001000010?????101?????1010011; + localparam [31:0] FLB = 32'b?????????????????000?????0000111; + localparam [31:0] FSB = 32'b?????????????????000?????0100111; + localparam [31:0] FMADD_B = 32'b?????11??????????????????1000011; + localparam [31:0] FMSUB_B = 32'b?????11??????????????????1000111; + localparam [31:0] FNMSUB_B = 32'b?????11??????????????????1001011; + localparam [31:0] FNMADD_B = 32'b?????11??????????????????1001111; + localparam [31:0] FADD_B = 32'b0000011??????????????????1010011; + localparam [31:0] FSUB_B = 32'b0000111??????????????????1010011; + localparam [31:0] FMUL_B = 32'b0001011??????????????????1010011; + localparam [31:0] FDIV_B = 32'b0001111??????????????????1010011; + localparam [31:0] FSQRT_B = 32'b010111100000?????????????1010011; + localparam [31:0] FSGNJ_B = 32'b0010011??????????000?????1010011; + localparam [31:0] FSGNJN_B = 32'b0010011??????????001?????1010011; + localparam [31:0] FSGNJX_B = 32'b0010011??????????010?????1010011; + localparam [31:0] FMIN_B = 32'b0010111??????????000?????1010011; + localparam [31:0] FMAX_B = 32'b0010111??????????001?????1010011; + localparam [31:0] FEQ_B = 32'b1010011??????????010?????1010011; + localparam [31:0] FLT_B = 32'b1010011??????????001?????1010011; + localparam [31:0] FLE_B = 32'b1010011??????????000?????1010011; + localparam [31:0] FCVT_W_B = 32'b110001100000?????????????1010011; + localparam [31:0] FCVT_WU_B = 32'b110001100001?????????????1010011; + localparam [31:0] FCVT_B_W = 32'b110101100000?????????????1010011; + localparam [31:0] FCVT_B_WU = 32'b110101100001?????????????1010011; + localparam [31:0] FMV_X_B = 32'b111001100000?????000?????1010011; + localparam [31:0] FCLASS_B = 32'b111001100000?????001?????1010011; + localparam [31:0] FMV_B_X = 32'b111101100000?????000?????1010011; + localparam [31:0] FCVT_L_B = 32'b110001100010?????????????1010011; + localparam [31:0] FCVT_LU_B = 32'b110001100011?????????????1010011; + localparam [31:0] FCVT_B_L = 32'b110101100010?????????????1010011; + localparam [31:0] FCVT_B_LU = 32'b110101100011?????????????1010011; + localparam [31:0] FCVT_S_B = 32'b010000000011?????000?????1010011; + localparam [31:0] FCVT_B_S = 32'b010001100000?????????????1010011; + localparam [31:0] FCVT_D_B = 32'b010000100011?????000?????1010011; + localparam [31:0] FCVT_B_D = 32'b010001100001?????????????1010011; + localparam [31:0] FCVT_H_B = 32'b010001000011?????000?????1010011; + localparam [31:0] FCVT_B_H = 32'b010001100010?????????????1010011; + localparam [31:0] FCVT_AH_B = 32'b010001000011?????101?????1010011; + localparam [31:0] FCVT_B_AH = 32'b010001100110?????????????1010011; + localparam [31:0] VFADD_S = 32'b1000001??????????000?????0110011; + localparam [31:0] VFADD_R_S = 32'b1000001??????????100?????0110011; + localparam [31:0] VFSUB_S = 32'b1000010??????????000?????0110011; + localparam [31:0] VFSUB_R_S = 32'b1000010??????????100?????0110011; + localparam [31:0] VFMUL_S = 32'b1000011??????????000?????0110011; + localparam [31:0] VFMUL_R_S = 32'b1000011??????????100?????0110011; + localparam [31:0] VFDIV_S = 32'b1000100??????????000?????0110011; + localparam [31:0] VFDIV_R_S = 32'b1000100??????????100?????0110011; + localparam [31:0] VFMIN_S = 32'b1000101??????????000?????0110011; + localparam [31:0] VFMIN_R_S = 32'b1000101??????????100?????0110011; + localparam [31:0] VFMAX_S = 32'b1000110??????????000?????0110011; + localparam [31:0] VFMAX_R_S = 32'b1000110??????????100?????0110011; + localparam [31:0] VFSQRT_S = 32'b100011100000?????000?????0110011; + localparam [31:0] VFMAC_S = 32'b1001000??????????000?????0110011; + localparam [31:0] VFMAC_R_S = 32'b1001000??????????100?????0110011; + localparam [31:0] VFMRE_S = 32'b1001001??????????000?????0110011; + localparam [31:0] VFMRE_R_S = 32'b1001001??????????100?????0110011; + localparam [31:0] VFCLASS_S = 32'b100110000001?????000?????0110011; + localparam [31:0] VFSGNJ_S = 32'b1001101??????????000?????0110011; + localparam [31:0] VFSGNJ_R_S = 32'b1001101??????????100?????0110011; + localparam [31:0] VFSGNJN_S = 32'b1001110??????????000?????0110011; + localparam [31:0] VFSGNJN_R_S = 32'b1001110??????????100?????0110011; + localparam [31:0] VFSGNJX_S = 32'b1001111??????????000?????0110011; + localparam [31:0] VFSGNJX_R_S = 32'b1001111??????????100?????0110011; + localparam [31:0] VFEQ_S = 32'b1010000??????????000?????0110011; + localparam [31:0] VFEQ_R_S = 32'b1010000??????????100?????0110011; + localparam [31:0] VFNE_S = 32'b1010001??????????000?????0110011; + localparam [31:0] VFNE_R_S = 32'b1010001??????????100?????0110011; + localparam [31:0] VFLT_S = 32'b1010010??????????000?????0110011; + localparam [31:0] VFLT_R_S = 32'b1010010??????????100?????0110011; + localparam [31:0] VFGE_S = 32'b1010011??????????000?????0110011; + localparam [31:0] VFGE_R_S = 32'b1010011??????????100?????0110011; + localparam [31:0] VFLE_S = 32'b1010100??????????000?????0110011; + localparam [31:0] VFLE_R_S = 32'b1010100??????????100?????0110011; + localparam [31:0] VFGT_S = 32'b1010101??????????000?????0110011; + localparam [31:0] VFGT_R_S = 32'b1010101??????????100?????0110011; + localparam [31:0] VFMV_X_S = 32'b100110000000?????000?????0110011; + localparam [31:0] VFMV_S_X = 32'b100110000000?????100?????0110011; + localparam [31:0] VFCVT_X_S = 32'b100110000010?????000?????0110011; + localparam [31:0] VFCVT_XU_S = 32'b100110000010?????100?????0110011; + localparam [31:0] VFCVT_S_X = 32'b100110000011?????000?????0110011; + localparam [31:0] VFCVT_S_XU = 32'b100110000011?????100?????0110011; + localparam [31:0] VFCPKA_S_S = 32'b1011000??????????000?????0110011; + localparam [31:0] VFCPKB_S_S = 32'b1011000??????????100?????0110011; + localparam [31:0] VFCPKC_S_S = 32'b1011001??????????000?????0110011; + localparam [31:0] VFCPKD_S_S = 32'b1011001??????????100?????0110011; + localparam [31:0] VFCPKA_S_D = 32'b1011010??????????000?????0110011; + localparam [31:0] VFCPKB_S_D = 32'b1011010??????????100?????0110011; + localparam [31:0] VFCPKC_S_D = 32'b1011011??????????000?????0110011; + localparam [31:0] VFCPKD_S_D = 32'b1011011??????????100?????0110011; + localparam [31:0] VFADD_H = 32'b1000001??????????010?????0110011; + localparam [31:0] VFADD_R_H = 32'b1000001??????????110?????0110011; + localparam [31:0] VFSUB_H = 32'b1000010??????????010?????0110011; + localparam [31:0] VFSUB_R_H = 32'b1000010??????????110?????0110011; + localparam [31:0] VFMUL_H = 32'b1000011??????????010?????0110011; + localparam [31:0] VFMUL_R_H = 32'b1000011??????????110?????0110011; + localparam [31:0] VFDIV_H = 32'b1000100??????????010?????0110011; + localparam [31:0] VFDIV_R_H = 32'b1000100??????????110?????0110011; + localparam [31:0] VFMIN_H = 32'b1000101??????????010?????0110011; + localparam [31:0] VFMIN_R_H = 32'b1000101??????????110?????0110011; + localparam [31:0] VFMAX_H = 32'b1000110??????????010?????0110011; + localparam [31:0] VFMAX_R_H = 32'b1000110??????????110?????0110011; + localparam [31:0] VFSQRT_H = 32'b100011100000?????010?????0110011; + localparam [31:0] VFMAC_H = 32'b1001000??????????010?????0110011; + localparam [31:0] VFMAC_R_H = 32'b1001000??????????110?????0110011; + localparam [31:0] VFMRE_H = 32'b1001001??????????010?????0110011; + localparam [31:0] VFMRE_R_H = 32'b1001001??????????110?????0110011; + localparam [31:0] VFCLASS_H = 32'b100110000001?????010?????0110011; + localparam [31:0] VFSGNJ_H = 32'b1001101??????????010?????0110011; + localparam [31:0] VFSGNJ_R_H = 32'b1001101??????????110?????0110011; + localparam [31:0] VFSGNJN_H = 32'b1001110??????????010?????0110011; + localparam [31:0] VFSGNJN_R_H = 32'b1001110??????????110?????0110011; + localparam [31:0] VFSGNJX_H = 32'b1001111??????????010?????0110011; + localparam [31:0] VFSGNJX_R_H = 32'b1001111??????????110?????0110011; + localparam [31:0] VFEQ_H = 32'b1010000??????????010?????0110011; + localparam [31:0] VFEQ_R_H = 32'b1010000??????????110?????0110011; + localparam [31:0] VFNE_H = 32'b1010001??????????010?????0110011; + localparam [31:0] VFNE_R_H = 32'b1010001??????????110?????0110011; + localparam [31:0] VFLT_H = 32'b1010010??????????010?????0110011; + localparam [31:0] VFLT_R_H = 32'b1010010??????????110?????0110011; + localparam [31:0] VFGE_H = 32'b1010011??????????010?????0110011; + localparam [31:0] VFGE_R_H = 32'b1010011??????????110?????0110011; + localparam [31:0] VFLE_H = 32'b1010100??????????010?????0110011; + localparam [31:0] VFLE_R_H = 32'b1010100??????????110?????0110011; + localparam [31:0] VFGT_H = 32'b1010101??????????010?????0110011; + localparam [31:0] VFGT_R_H = 32'b1010101??????????110?????0110011; + localparam [31:0] VFMV_X_H = 32'b100110000000?????010?????0110011; + localparam [31:0] VFMV_H_X = 32'b100110000000?????110?????0110011; + localparam [31:0] VFCVT_X_H = 32'b100110000010?????010?????0110011; + localparam [31:0] VFCVT_XU_H = 32'b100110000010?????110?????0110011; + localparam [31:0] VFCVT_H_X = 32'b100110000011?????010?????0110011; + localparam [31:0] VFCVT_H_XU = 32'b100110000011?????110?????0110011; + localparam [31:0] VFCPKA_H_S = 32'b1011000??????????010?????0110011; + localparam [31:0] VFCPKB_H_S = 32'b1011000??????????110?????0110011; + localparam [31:0] VFCPKC_H_S = 32'b1011001??????????010?????0110011; + localparam [31:0] VFCPKD_H_S = 32'b1011001??????????110?????0110011; + localparam [31:0] VFCPKA_H_D = 32'b1011010??????????010?????0110011; + localparam [31:0] VFCPKB_H_D = 32'b1011010??????????110?????0110011; + localparam [31:0] VFCPKC_H_D = 32'b1011011??????????010?????0110011; + localparam [31:0] VFCPKD_H_D = 32'b1011011??????????110?????0110011; + localparam [31:0] VFCVT_S_H = 32'b100110000110?????000?????0110011; + localparam [31:0] VFCVTU_S_H = 32'b100110000110?????100?????0110011; + localparam [31:0] VFCVT_H_S = 32'b100110000100?????010?????0110011; + localparam [31:0] VFCVTU_H_S = 32'b100110000100?????110?????0110011; + localparam [31:0] VFADD_AH = 32'b1000001??????????001?????0110011; + localparam [31:0] VFADD_R_AH = 32'b1000001??????????101?????0110011; + localparam [31:0] VFSUB_AH = 32'b1000010??????????001?????0110011; + localparam [31:0] VFSUB_R_AH = 32'b1000010??????????101?????0110011; + localparam [31:0] VFMUL_AH = 32'b1000011??????????001?????0110011; + localparam [31:0] VFMUL_R_AH = 32'b1000011??????????101?????0110011; + localparam [31:0] VFDIV_AH = 32'b1000100??????????001?????0110011; + localparam [31:0] VFDIV_R_AH = 32'b1000100??????????101?????0110011; + localparam [31:0] VFMIN_AH = 32'b1000101??????????001?????0110011; + localparam [31:0] VFMIN_R_AH = 32'b1000101??????????101?????0110011; + localparam [31:0] VFMAX_AH = 32'b1000110??????????001?????0110011; + localparam [31:0] VFMAX_R_AH = 32'b1000110??????????101?????0110011; + localparam [31:0] VFSQRT_AH = 32'b100011100000?????001?????0110011; + localparam [31:0] VFMAC_AH = 32'b1001000??????????001?????0110011; + localparam [31:0] VFMAC_R_AH = 32'b1001000??????????101?????0110011; + localparam [31:0] VFMRE_AH = 32'b1001001??????????001?????0110011; + localparam [31:0] VFMRE_R_AH = 32'b1001001??????????101?????0110011; + localparam [31:0] VFCLASS_AH = 32'b100110000001?????001?????0110011; + localparam [31:0] VFSGNJ_AH = 32'b1001101??????????001?????0110011; + localparam [31:0] VFSGNJ_R_AH = 32'b1001101??????????101?????0110011; + localparam [31:0] VFSGNJN_AH = 32'b1001110??????????001?????0110011; + localparam [31:0] VFSGNJN_R_AH = 32'b1001110??????????101?????0110011; + localparam [31:0] VFSGNJX_AH = 32'b1001111??????????001?????0110011; + localparam [31:0] VFSGNJX_R_AH = 32'b1001111??????????101?????0110011; + localparam [31:0] VFEQ_AH = 32'b1010000??????????001?????0110011; + localparam [31:0] VFEQ_R_AH = 32'b1010000??????????101?????0110011; + localparam [31:0] VFNE_AH = 32'b1010001??????????001?????0110011; + localparam [31:0] VFNE_R_AH = 32'b1010001??????????101?????0110011; + localparam [31:0] VFLT_AH = 32'b1010010??????????001?????0110011; + localparam [31:0] VFLT_R_AH = 32'b1010010??????????101?????0110011; + localparam [31:0] VFGE_AH = 32'b1010011??????????001?????0110011; + localparam [31:0] VFGE_R_AH = 32'b1010011??????????101?????0110011; + localparam [31:0] VFLE_AH = 32'b1010100??????????001?????0110011; + localparam [31:0] VFLE_R_AH = 32'b1010100??????????101?????0110011; + localparam [31:0] VFGT_AH = 32'b1010101??????????001?????0110011; + localparam [31:0] VFGT_R_AH = 32'b1010101??????????101?????0110011; + localparam [31:0] VFMV_X_AH = 32'b100110000000?????001?????0110011; + localparam [31:0] VFMV_AH_X = 32'b100110000000?????101?????0110011; + localparam [31:0] VFCVT_X_AH = 32'b100110000010?????001?????0110011; + localparam [31:0] VFCVT_XU_AH = 32'b100110000010?????101?????0110011; + localparam [31:0] VFCVT_AH_X = 32'b100110000011?????001?????0110011; + localparam [31:0] VFCVT_AH_XU = 32'b100110000011?????101?????0110011; + localparam [31:0] VFCPKA_AH_S = 32'b1011000??????????001?????0110011; + localparam [31:0] VFCPKB_AH_S = 32'b1011000??????????101?????0110011; + localparam [31:0] VFCPKC_AH_S = 32'b1011001??????????001?????0110011; + localparam [31:0] VFCPKD_AH_S = 32'b1011001??????????101?????0110011; + localparam [31:0] VFCPKA_AH_D = 32'b1011010??????????001?????0110011; + localparam [31:0] VFCPKB_AH_D = 32'b1011010??????????101?????0110011; + localparam [31:0] VFCPKC_AH_D = 32'b1011011??????????001?????0110011; + localparam [31:0] VFCPKD_AH_D = 32'b1011011??????????101?????0110011; + localparam [31:0] VFCVT_S_AH = 32'b100110000101?????000?????0110011; + localparam [31:0] VFCVTU_S_AH = 32'b100110000101?????100?????0110011; + localparam [31:0] VFCVT_AH_S = 32'b100110000100?????001?????0110011; + localparam [31:0] VFCVTU_AH_S = 32'b100110000100?????101?????0110011; + localparam [31:0] VFCVT_H_AH = 32'b100110000101?????010?????0110011; + localparam [31:0] VFCVTU_H_AH = 32'b100110000101?????110?????0110011; + localparam [31:0] VFCVT_AH_H = 32'b100110000110?????001?????0110011; + localparam [31:0] VFCVTU_AH_H = 32'b100110000110?????101?????0110011; + localparam [31:0] VFADD_B = 32'b1000001??????????011?????0110011; + localparam [31:0] VFADD_R_B = 32'b1000001??????????111?????0110011; + localparam [31:0] VFSUB_B = 32'b1000010??????????011?????0110011; + localparam [31:0] VFSUB_R_B = 32'b1000010??????????111?????0110011; + localparam [31:0] VFMUL_B = 32'b1000011??????????011?????0110011; + localparam [31:0] VFMUL_R_B = 32'b1000011??????????111?????0110011; + localparam [31:0] VFDIV_B = 32'b1000100??????????011?????0110011; + localparam [31:0] VFDIV_R_B = 32'b1000100??????????111?????0110011; + localparam [31:0] VFMIN_B = 32'b1000101??????????011?????0110011; + localparam [31:0] VFMIN_R_B = 32'b1000101??????????111?????0110011; + localparam [31:0] VFMAX_B = 32'b1000110??????????011?????0110011; + localparam [31:0] VFMAX_R_B = 32'b1000110??????????111?????0110011; + localparam [31:0] VFSQRT_B = 32'b100011100000?????011?????0110011; + localparam [31:0] VFMAC_B = 32'b1001000??????????011?????0110011; + localparam [31:0] VFMAC_R_B = 32'b1001000??????????111?????0110011; + localparam [31:0] VFMRE_B = 32'b1001001??????????011?????0110011; + localparam [31:0] VFMRE_R_B = 32'b1001001??????????111?????0110011; + localparam [31:0] VFSGNJ_B = 32'b1001101??????????011?????0110011; + localparam [31:0] VFSGNJ_R_B = 32'b1001101??????????111?????0110011; + localparam [31:0] VFSGNJN_B = 32'b1001110??????????011?????0110011; + localparam [31:0] VFSGNJN_R_B = 32'b1001110??????????111?????0110011; + localparam [31:0] VFSGNJX_B = 32'b1001111??????????011?????0110011; + localparam [31:0] VFSGNJX_R_B = 32'b1001111??????????111?????0110011; + localparam [31:0] VFEQ_B = 32'b1010000??????????011?????0110011; + localparam [31:0] VFEQ_R_B = 32'b1010000??????????111?????0110011; + localparam [31:0] VFNE_B = 32'b1010001??????????011?????0110011; + localparam [31:0] VFNE_R_B = 32'b1010001??????????111?????0110011; + localparam [31:0] VFLT_B = 32'b1010010??????????011?????0110011; + localparam [31:0] VFLT_R_B = 32'b1010010??????????111?????0110011; + localparam [31:0] VFGE_B = 32'b1010011??????????011?????0110011; + localparam [31:0] VFGE_R_B = 32'b1010011??????????111?????0110011; + localparam [31:0] VFLE_B = 32'b1010100??????????011?????0110011; + localparam [31:0] VFLE_R_B = 32'b1010100??????????111?????0110011; + localparam [31:0] VFGT_B = 32'b1010101??????????011?????0110011; + localparam [31:0] VFGT_R_B = 32'b1010101??????????111?????0110011; + localparam [31:0] VFMV_X_B = 32'b100110000000?????011?????0110011; + localparam [31:0] VFMV_B_X = 32'b100110000000?????111?????0110011; + localparam [31:0] VFCLASS_B = 32'b100110000001?????011?????0110011; + localparam [31:0] VFCVT_X_B = 32'b100110000010?????011?????0110011; + localparam [31:0] VFCVT_XU_B = 32'b100110000010?????111?????0110011; + localparam [31:0] VFCVT_B_X = 32'b100110000011?????011?????0110011; + localparam [31:0] VFCVT_B_XU = 32'b100110000011?????111?????0110011; + localparam [31:0] VFCPKA_B_S = 32'b1011000??????????011?????0110011; + localparam [31:0] VFCPKB_B_S = 32'b1011000??????????111?????0110011; + localparam [31:0] VFCPKC_B_S = 32'b1011001??????????011?????0110011; + localparam [31:0] VFCPKD_B_S = 32'b1011001??????????111?????0110011; + localparam [31:0] VFCPKA_B_D = 32'b1011010??????????011?????0110011; + localparam [31:0] VFCPKB_B_D = 32'b1011010??????????111?????0110011; + localparam [31:0] VFCPKC_B_D = 32'b1011011??????????011?????0110011; + localparam [31:0] VFCPKD_B_D = 32'b1011011??????????111?????0110011; + localparam [31:0] VFCVT_S_B = 32'b100110000111?????000?????0110011; + localparam [31:0] VFCVTU_S_B = 32'b100110000111?????100?????0110011; + localparam [31:0] VFCVT_B_S = 32'b100110000100?????011?????0110011; + localparam [31:0] VFCVTU_B_S = 32'b100110000100?????111?????0110011; + localparam [31:0] VFCVT_H_B = 32'b100110000111?????010?????0110011; + localparam [31:0] VFCVTU_H_B = 32'b100110000111?????110?????0110011; + localparam [31:0] VFCVT_B_H = 32'b100110000110?????011?????0110011; + localparam [31:0] VFCVTU_B_H = 32'b100110000110?????111?????0110011; + localparam [31:0] VFCVT_AH_B = 32'b100110000111?????001?????0110011; + localparam [31:0] VFCVTU_AH_B = 32'b100110000111?????101?????0110011; + localparam [31:0] VFCVT_B_AH = 32'b100110000101?????011?????0110011; + localparam [31:0] VFCVTU_B_AH = 32'b100110000101?????111?????0110011; + localparam [31:0] VFDOTP_S = 32'b1001010??????????000?????0110011; + localparam [31:0] VFDOTP_R_S = 32'b1001010??????????100?????0110011; + localparam [31:0] VFAVG_S = 32'b1010110??????????000?????0110011; + localparam [31:0] VFAVG_R_S = 32'b1010110??????????100?????0110011; + localparam [31:0] FMULEX_S_H = 32'b0100110??????????????????1010011; + localparam [31:0] FMACEX_S_H = 32'b0101010??????????????????1010011; + localparam [31:0] VFDOTP_H = 32'b1001010??????????010?????0110011; + localparam [31:0] VFDOTP_R_H = 32'b1001010??????????110?????0110011; + localparam [31:0] VFDOTPEX_S_H = 32'b1001011??????????010?????0110011; + localparam [31:0] VFDOTPEX_S_R_H = 32'b1001011??????????110?????0110011; + localparam [31:0] VFAVG_H = 32'b1010110??????????010?????0110011; + localparam [31:0] VFAVG_R_H = 32'b1010110??????????110?????0110011; + localparam [31:0] FMULEX_S_AH = 32'b0100110??????????101?????1010011; + localparam [31:0] FMACEX_S_AH = 32'b0101010??????????101?????1010011; + localparam [31:0] VFDOTP_AH = 32'b1001010??????????001?????0110011; + localparam [31:0] VFDOTP_R_AH = 32'b1001010??????????101?????0110011; + localparam [31:0] VFDOTPEX_S_AH = 32'b1001011??????????001?????0110011; + localparam [31:0] VFDOTPEX_S_R_AH = 32'b1001011??????????101?????0110011; + localparam [31:0] VFAVG_AH = 32'b1010110??????????001?????0110011; + localparam [31:0] VFAVG_R_AH = 32'b1010110??????????101?????0110011; + localparam [31:0] FMULEX_S_B = 32'b0100111??????????????????1010011; + localparam [31:0] FMACEX_S_B = 32'b0101011??????????????????1010011; + localparam [31:0] VFDOTP_B = 32'b1001010??????????011?????0110011; + localparam [31:0] VFDOTP_R_B = 32'b1001010??????????111?????0110011; + localparam [31:0] VFDOTPEX_S_B = 32'b1001011??????????011?????0110011; + localparam [31:0] VFDOTPEX_S_R_B = 32'b1001011??????????111?????0110011; + localparam [31:0] VFAVG_B = 32'b1010110??????????011?????0110011; + localparam [31:0] VFAVG_R_B = 32'b1010110??????????111?????0110011; + /* CSR Addresses */ + localparam logic [11:0] CSR_FFLAGS = 12'h1; + localparam logic [11:0] CSR_FRM = 12'h2; + localparam logic [11:0] CSR_FCSR = 12'h3; + localparam logic [11:0] CSR_USTATUS = 12'h0; + localparam logic [11:0] CSR_UIE = 12'h4; + localparam logic [11:0] CSR_UTVEC = 12'h5; + localparam logic [11:0] CSR_VSTART = 12'h8; + localparam logic [11:0] CSR_VXSAT = 12'h9; + localparam logic [11:0] CSR_VXRM = 12'ha; + localparam logic [11:0] CSR_VCSR = 12'hf; + localparam logic [11:0] CSR_USCRATCH = 12'h40; + localparam logic [11:0] CSR_UEPC = 12'h41; + localparam logic [11:0] CSR_UCAUSE = 12'h42; + localparam logic [11:0] CSR_UTVAL = 12'h43; + localparam logic [11:0] CSR_UIP = 12'h44; + localparam logic [11:0] CSR_CYCLE = 12'hc00; + localparam logic [11:0] CSR_TIME = 12'hc01; + localparam logic [11:0] CSR_INSTRET = 12'hc02; + localparam logic [11:0] CSR_HPMCOUNTER3 = 12'hc03; + localparam logic [11:0] CSR_HPMCOUNTER4 = 12'hc04; + localparam logic [11:0] CSR_HPMCOUNTER5 = 12'hc05; + localparam logic [11:0] CSR_HPMCOUNTER6 = 12'hc06; + localparam logic [11:0] CSR_HPMCOUNTER7 = 12'hc07; + localparam logic [11:0] CSR_HPMCOUNTER8 = 12'hc08; + localparam logic [11:0] CSR_HPMCOUNTER9 = 12'hc09; + localparam logic [11:0] CSR_HPMCOUNTER10 = 12'hc0a; + localparam logic [11:0] CSR_HPMCOUNTER11 = 12'hc0b; + localparam logic [11:0] CSR_HPMCOUNTER12 = 12'hc0c; + localparam logic [11:0] CSR_HPMCOUNTER13 = 12'hc0d; + localparam logic [11:0] CSR_HPMCOUNTER14 = 12'hc0e; + localparam logic [11:0] CSR_HPMCOUNTER15 = 12'hc0f; + localparam logic [11:0] CSR_HPMCOUNTER16 = 12'hc10; + localparam logic [11:0] CSR_HPMCOUNTER17 = 12'hc11; + localparam logic [11:0] CSR_HPMCOUNTER18 = 12'hc12; + localparam logic [11:0] CSR_HPMCOUNTER19 = 12'hc13; + localparam logic [11:0] CSR_HPMCOUNTER20 = 12'hc14; + localparam logic [11:0] CSR_HPMCOUNTER21 = 12'hc15; + localparam logic [11:0] CSR_HPMCOUNTER22 = 12'hc16; + localparam logic [11:0] CSR_HPMCOUNTER23 = 12'hc17; + localparam logic [11:0] CSR_HPMCOUNTER24 = 12'hc18; + localparam logic [11:0] CSR_HPMCOUNTER25 = 12'hc19; + localparam logic [11:0] CSR_HPMCOUNTER26 = 12'hc1a; + localparam logic [11:0] CSR_HPMCOUNTER27 = 12'hc1b; + localparam logic [11:0] CSR_HPMCOUNTER28 = 12'hc1c; + localparam logic [11:0] CSR_HPMCOUNTER29 = 12'hc1d; + localparam logic [11:0] CSR_HPMCOUNTER30 = 12'hc1e; + localparam logic [11:0] CSR_HPMCOUNTER31 = 12'hc1f; + localparam logic [11:0] CSR_VL = 12'hc20; + localparam logic [11:0] CSR_VTYPE = 12'hc21; + localparam logic [11:0] CSR_VLENB = 12'hc22; + localparam logic [11:0] CSR_SSTATUS = 12'h100; + localparam logic [11:0] CSR_SEDELEG = 12'h102; + localparam logic [11:0] CSR_SIDELEG = 12'h103; + localparam logic [11:0] CSR_SIE = 12'h104; + localparam logic [11:0] CSR_STVEC = 12'h105; + localparam logic [11:0] CSR_SCOUNTEREN = 12'h106; + localparam logic [11:0] CSR_SSCRATCH = 12'h140; + localparam logic [11:0] CSR_SEPC = 12'h141; + localparam logic [11:0] CSR_SCAUSE = 12'h142; + localparam logic [11:0] CSR_STVAL = 12'h143; + localparam logic [11:0] CSR_SIP = 12'h144; + localparam logic [11:0] CSR_SATP = 12'h180; + localparam logic [11:0] CSR_VSSTATUS = 12'h200; + localparam logic [11:0] CSR_VSIE = 12'h204; + localparam logic [11:0] CSR_VSTVEC = 12'h205; + localparam logic [11:0] CSR_VSSCRATCH = 12'h240; + localparam logic [11:0] CSR_VSEPC = 12'h241; + localparam logic [11:0] CSR_VSCAUSE = 12'h242; + localparam logic [11:0] CSR_VSTVAL = 12'h243; + localparam logic [11:0] CSR_VSIP = 12'h244; + localparam logic [11:0] CSR_VSATP = 12'h280; + localparam logic [11:0] CSR_HSTATUS = 12'h600; + localparam logic [11:0] CSR_HEDELEG = 12'h602; + localparam logic [11:0] CSR_HIDELEG = 12'h603; + localparam logic [11:0] CSR_HIE = 12'h604; + localparam logic [11:0] CSR_HTIMEDELTA = 12'h605; + localparam logic [11:0] CSR_HCOUNTEREN = 12'h606; + localparam logic [11:0] CSR_HGEIE = 12'h607; + localparam logic [11:0] CSR_HTVAL = 12'h643; + localparam logic [11:0] CSR_HIP = 12'h644; + localparam logic [11:0] CSR_HVIP = 12'h645; + localparam logic [11:0] CSR_HTINST = 12'h64a; + localparam logic [11:0] CSR_HGATP = 12'h680; + localparam logic [11:0] CSR_HGEIP = 12'he12; + localparam logic [11:0] CSR_UTVT = 12'h7; + localparam logic [11:0] CSR_UNXTI = 12'h45; + localparam logic [11:0] CSR_UINTSTATUS = 12'h46; + localparam logic [11:0] CSR_USCRATCHCSW = 12'h48; + localparam logic [11:0] CSR_USCRATCHCSWL = 12'h49; + localparam logic [11:0] CSR_STVT = 12'h107; + localparam logic [11:0] CSR_SNXTI = 12'h145; + localparam logic [11:0] CSR_SINTSTATUS = 12'h146; + localparam logic [11:0] CSR_SSCRATCHCSW = 12'h148; + localparam logic [11:0] CSR_SSCRATCHCSWL = 12'h149; + localparam logic [11:0] CSR_MTVT = 12'h307; + localparam logic [11:0] CSR_MNXTI = 12'h345; + localparam logic [11:0] CSR_MINTSTATUS = 12'h346; + localparam logic [11:0] CSR_MSCRATCHCSW = 12'h348; + localparam logic [11:0] CSR_MSCRATCHCSWL = 12'h349; + localparam logic [11:0] CSR_MSTATUS = 12'h300; + localparam logic [11:0] CSR_MISA = 12'h301; + localparam logic [11:0] CSR_MEDELEG = 12'h302; + localparam logic [11:0] CSR_MIDELEG = 12'h303; + localparam logic [11:0] CSR_MIE = 12'h304; + localparam logic [11:0] CSR_MTVEC = 12'h305; + localparam logic [11:0] CSR_MCOUNTEREN = 12'h306; + localparam logic [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam logic [11:0] CSR_MSCRATCH = 12'h340; + localparam logic [11:0] CSR_MEPC = 12'h341; + localparam logic [11:0] CSR_MCAUSE = 12'h342; + localparam logic [11:0] CSR_MTVAL = 12'h343; + localparam logic [11:0] CSR_MIP = 12'h344; + localparam logic [11:0] CSR_MTINST = 12'h34a; + localparam logic [11:0] CSR_MTVAL2 = 12'h34b; + localparam logic [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam logic [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam logic [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam logic [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam logic [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam logic [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam logic [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam logic [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam logic [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam logic [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam logic [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam logic [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam logic [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam logic [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam logic [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam logic [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam logic [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam logic [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam logic [11:0] CSR_PMPADDR14 = 12'h3be; + localparam logic [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam logic [11:0] CSR_TSELECT = 12'h7a0; + localparam logic [11:0] CSR_TDATA1 = 12'h7a1; + localparam logic [11:0] CSR_TDATA2 = 12'h7a2; + localparam logic [11:0] CSR_TDATA3 = 12'h7a3; + localparam logic [11:0] CSR_DCSR = 12'h7b0; + localparam logic [11:0] CSR_DPC = 12'h7b1; + localparam logic [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam logic [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam logic [11:0] CSR_MCYCLE = 12'hb00; + localparam logic [11:0] CSR_MINSTRET = 12'hb02; + localparam logic [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam logic [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam logic [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam logic [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam logic [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam logic [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam logic [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam logic [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam logic [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam logic [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam logic [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam logic [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam logic [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam logic [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam logic [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam logic [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam logic [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam logic [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam logic [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam logic [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam logic [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam logic [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam logic [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam logic [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam logic [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam logic [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam logic [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam logic [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam logic [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam logic [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam logic [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam logic [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam logic [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam logic [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam logic [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam logic [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam logic [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam logic [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam logic [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam logic [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam logic [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam logic [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam logic [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam logic [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam logic [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam logic [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam logic [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam logic [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam logic [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam logic [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam logic [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam logic [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam logic [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam logic [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam logic [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam logic [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam logic [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam logic [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam logic [11:0] CSR_TRACE = 12'h7d0; + localparam logic [11:0] CSR_MVENDORID = 12'hf11; + localparam logic [11:0] CSR_MARCHID = 12'hf12; + localparam logic [11:0] CSR_MIMPID = 12'hf13; + localparam logic [11:0] CSR_MHARTID = 12'hf14; + localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615; + localparam logic [11:0] CSR_CYCLEH = 12'hc80; + localparam logic [11:0] CSR_TIMEH = 12'hc81; + localparam logic [11:0] CSR_INSTRETH = 12'hc82; + localparam logic [11:0] CSR_HPMCOUNTER3H = 12'hc83; + localparam logic [11:0] CSR_HPMCOUNTER4H = 12'hc84; + localparam logic [11:0] CSR_HPMCOUNTER5H = 12'hc85; + localparam logic [11:0] CSR_HPMCOUNTER6H = 12'hc86; + localparam logic [11:0] CSR_HPMCOUNTER7H = 12'hc87; + localparam logic [11:0] CSR_HPMCOUNTER8H = 12'hc88; + localparam logic [11:0] CSR_HPMCOUNTER9H = 12'hc89; + localparam logic [11:0] CSR_HPMCOUNTER10H = 12'hc8a; + localparam logic [11:0] CSR_HPMCOUNTER11H = 12'hc8b; + localparam logic [11:0] CSR_HPMCOUNTER12H = 12'hc8c; + localparam logic [11:0] CSR_HPMCOUNTER13H = 12'hc8d; + localparam logic [11:0] CSR_HPMCOUNTER14H = 12'hc8e; + localparam logic [11:0] CSR_HPMCOUNTER15H = 12'hc8f; + localparam logic [11:0] CSR_HPMCOUNTER16H = 12'hc90; + localparam logic [11:0] CSR_HPMCOUNTER17H = 12'hc91; + localparam logic [11:0] CSR_HPMCOUNTER18H = 12'hc92; + localparam logic [11:0] CSR_HPMCOUNTER19H = 12'hc93; + localparam logic [11:0] CSR_HPMCOUNTER20H = 12'hc94; + localparam logic [11:0] CSR_HPMCOUNTER21H = 12'hc95; + localparam logic [11:0] CSR_HPMCOUNTER22H = 12'hc96; + localparam logic [11:0] CSR_HPMCOUNTER23H = 12'hc97; + localparam logic [11:0] CSR_HPMCOUNTER24H = 12'hc98; + localparam logic [11:0] CSR_HPMCOUNTER25H = 12'hc99; + localparam logic [11:0] CSR_HPMCOUNTER26H = 12'hc9a; + localparam logic [11:0] CSR_HPMCOUNTER27H = 12'hc9b; + localparam logic [11:0] CSR_HPMCOUNTER28H = 12'hc9c; + localparam logic [11:0] CSR_HPMCOUNTER29H = 12'hc9d; + localparam logic [11:0] CSR_HPMCOUNTER30H = 12'hc9e; + localparam logic [11:0] CSR_HPMCOUNTER31H = 12'hc9f; + localparam logic [11:0] CSR_MSTATUSH = 12'h310; + localparam logic [11:0] CSR_MCYCLEH = 12'hb80; + localparam logic [11:0] CSR_MINSTRETH = 12'hb82; + localparam logic [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam logic [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam logic [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam logic [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam logic [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam logic [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam logic [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam logic [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam logic [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam logic [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam logic [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam logic [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam logic [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam logic [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam logic [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam logic [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam logic [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam logic [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam logic [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam logic [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam logic [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam logic [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam logic [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam logic [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam logic [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam logic [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam logic [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam logic [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam logic [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; +endpackage diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch.sv new file mode 100644 index 0000000000..e4a588ae9a --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch.sv @@ -0,0 +1,1793 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Authors: Florian Zaruba +// Sergio Mazzola +// Description: Top-Level of Snitch Integer Core RV32E + +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + +// `SNITCH_ENABLE_PERF Enables mcycle, minstret performance counters (read only) + +module snitch + import snitch_pkg::meta_id_t; +#( + parameter logic [31:0] BootAddr = 32'h0000_1000, + parameter logic [31:0] MTVEC = BootAddr, // Exception Base Address (see privileged spec 3.1.7) + parameter bit RVE = 0, // Reduced-register Extension + parameter bit RVM = 1, // Enable IntegerMmultiplication & Division Extension + parameter int RegNrWritePorts = 2 // Implement one or two write ports into the register file +) ( + input logic clk_i, + input logic rst_i, + input logic [31:0] hart_id_i, + // Instruction Refill Port + output logic [31:0] inst_addr_o, + input logic [31:0] inst_data_i, + output logic inst_valid_o, + input logic inst_ready_i, +`ifdef RISCV_FORMAL + output logic [0:0] rvfi_valid, + output logic [0:0][63:0] rvfi_order, + output logic [0:0][31:0] rvfi_insn, + output logic [0:0] rvfi_trap, + output logic [0:0] rvfi_halt, + output logic [0:0] rvfi_intr, + output logic [0:0][1:0] rvfi_mode, + output logic [0:0][4:0] rvfi_rs1_addr, + output logic [0:0][4:0] rvfi_rs2_addr, + output logic [0:0][31:0] rvfi_rs1_rdata, + output logic [0:0][31:0] rvfi_rs2_rdata, + output logic [0:0][4:0] rvfi_rd_addr, + output logic [0:0][31:0] rvfi_rd_wdata, + output logic [0:0][31:0] rvfi_pc_rdata, + output logic [0:0][31:0] rvfi_pc_wdata, + output logic [0:0][31:0] rvfi_mem_addr, + output logic [0:0][3:0] rvfi_mem_rmask, + output logic [0:0][3:0] rvfi_mem_wmask, + output logic [0:0][31:0] rvfi_mem_rdata, + output logic [0:0][31:0] rvfi_mem_wdata, +`endif + /// Accelerator Interface - Master Port + /// Independent channels for transaction request and read completion. + /// AXI-like handshaking. + /// Same IDs need to be handled in-order. + output logic [31:0] acc_qaddr_o, + output logic [4:0] acc_qid_o, + output logic [31:0] acc_qdata_op_o, + output logic [31:0] acc_qdata_arga_o, + output logic [31:0] acc_qdata_argb_o, + output logic [31:0] acc_qdata_argc_o, + output logic acc_qvalid_o, + input logic acc_qready_i, + input logic [31:0] acc_pdata_i, + input logic [4:0] acc_pid_i, + input logic acc_perror_i, + input logic acc_pvalid_i, + output logic acc_pready_o, + /// TCDM Data Interface + /// Write transactions do not return data on the `P Channel` + /// Transactions need to be handled strictly in-order. + output logic [31:0] data_qaddr_o, + output logic data_qwrite_o, + output logic [3:0] data_qamo_o, + output logic [31:0] data_qdata_o, + output logic [3:0] data_qstrb_o, + output meta_id_t data_qid_o, + output logic data_qvalid_o, + input logic data_qready_i, + input logic [31:0] data_pdata_i, + input logic data_perror_i, + input meta_id_t data_pid_i, + input logic data_pvalid_i, + output logic data_pready_o, + input logic wake_up_sync_i, // synchronous wake-up interrupt + // Core event strobes + output snitch_pkg::core_events_t core_events_o +); + + localparam int RegWidth = RVE ? 4 : 5; + localparam int RegNrReadPorts = snitch_pkg::XPULPIMG ? 3 : 2; + + logic illegal_inst; + logic zero_lsb; + + // Instruction fetch + logic [31:0] pc_d, pc_q; + logic wfi_d, wfi_q; + logic wake_up_d, wake_up_q; + logic [31:0] consec_pc; + // Immediates + logic [31:0] iimm, uimm, jimm, bimm, simm, pbimm; + /* verilator lint_off WIDTH */ + assign iimm = $signed({inst_data_i[31:20]}); + assign uimm = {inst_data_i[31:12], 12'b0}; + assign jimm = $signed({inst_data_i[31], + inst_data_i[19:12], inst_data_i[20], inst_data_i[30:21], 1'b0}); + assign bimm = $signed({inst_data_i[31], + inst_data_i[7], inst_data_i[30:25], inst_data_i[11:8], 1'b0}); + assign simm = $signed({inst_data_i[31:25], inst_data_i[11:7]}); + assign pbimm = $signed(inst_data_i[24:20]); // Xpulpimg immediate branching signed immediate + /* verilator lint_on WIDTH */ + + logic [31:0] opa, opb; + logic [32:0] adder_result; + logic [31:0] alu_result; + + logic [RegWidth-1:0] rd, rs1, rs2; + logic stall, lsu_stall; + // Register connections + logic [RegNrReadPorts-1:0][RegWidth-1:0] gpr_raddr; + logic [RegNrReadPorts-1:0][31:0] gpr_rdata; + logic [RegNrWritePorts-1:0][RegWidth-1:0] gpr_waddr; + logic [RegNrWritePorts-1:0][31:0] gpr_wdata; + logic [RegNrWritePorts-1:0] gpr_we; + logic [2**RegWidth-1:0] sb_d, sb_q; + + // Load/Store Defines + logic is_load, is_store, is_signed, is_postincr; + logic is_fp_load, is_fp_store; + logic ls_misaligned; + logic ld_addr_misaligned; + logic st_addr_misaligned; + + enum logic [1:0] { + Byte = 2'b00, + HalfWord = 2'b01, + Word = 2'b10, + Double = 2'b11 + } ls_size; + + enum logic [3:0] { + AMONone = 4'h0, + AMOSwap = 4'h1, + AMOAdd = 4'h2, + AMOAnd = 4'h3, + AMOOr = 4'h4, + AMOXor = 4'h5, + AMOMax = 4'h6, + AMOMaxu = 4'h7, + AMOMin = 4'h8, + AMOMinu = 4'h9, + AMOLR = 4'hA, + AMOSC = 4'hB + } ls_amo; + + logic [31:0] ld_result; + logic lsu_qready, lsu_qvalid; + logic lsu_pvalid, lsu_pready; + logic [RegWidth-1:0] lsu_rd; + logic [31:0] lsu_qaddr; + + logic retire_load; // retire a load instruction + logic retire_p; // retire from post-increment instructions + logic retire_i; // retire the rest of the base instruction set + logic retire_acc; // retire an instruction we offloaded + + logic acc_stall; + logic valid_instr; + logic exception; + + // ALU Operations + enum logic [3:0] { + // Arithmetical operations + Add, Sub, + // Shifts + Sll, Srl, Sra, + // Logical operations + LXor, LOr, LAnd, LNAnd, + // Comparisons + Eq, Neq, Ge, Geu, + Slt, Sltu, + // Miscellaneous + BypassA + } alu_op; + + enum logic [3:0] { + None, Reg, IImmediate, UImmediate, JImmediate, SImmediate, SFImmediate, PC, CSR, CSRImmediate, PBImmediate, RegRd, RegRs2 + } opa_select, opb_select, opc_select; + + logic write_rd; // write rd desitnation this cycle + logic uses_rd; + logic write_rs1; // write rs1 destination this cycle + logic uses_rs1; + enum logic [1:0] {Consec, Alu, Exception} next_pc; + + enum logic [1:0] {RdAlu, RdConsecPC, RdBypass} rd_select; + logic [31:0] rd_bypass; + + logic is_branch; + + logic [31:0] csr_rvalue; + logic csr_en; + + // Registers + `FFAR(pc_q, pc_d, BootAddr, clk_i, rst_i) + `FFAR(wfi_q, wfi_d, '0, clk_i, rst_i) + `FFAR(wake_up_q, wake_up_d, '0, clk_i, rst_i) + `FFAR(sb_q, sb_d, '0, clk_i, rst_i) + + // performance counter + `ifdef SNITCH_ENABLE_PERF + logic [63:0] cycle_q; + logic [63:0] instret_q; + `FFAR(cycle_q, cycle_q + 1, '0, clk_i, rst_i); + `FFLAR(instret_q, instret_q + 1, !stall, '0, clk_i, rst_i); + `endif + + always_comb begin + core_events_o = '0; + core_events_o.retired_insts = ~stall; + end + + // accelerator offloading interface + // register int destination in scoreboard + logic acc_register_rd; + + assign acc_qaddr_o = hart_id_i; + assign acc_qid_o = rd; + assign acc_qdata_op_o = inst_data_i; + assign acc_qdata_arga_o = {{32{gpr_rdata[0][31]}}, gpr_rdata[0]}; + assign acc_qdata_argb_o = {{32{gpr_rdata[1][31]}}, gpr_rdata[1]}; + assign acc_qdata_argc_o = {{32{gpr_rdata[2][31]}}, gpr_rdata[2]}; + + // instruction fetch interface + assign inst_addr_o = pc_q; + assign inst_valid_o = ~wfi_q; + + // -------------------- + // Control + // -------------------- + // Scoreboard: Keep track of rd dependencies (only loads at the moment) + logic operands_ready; + logic dst_ready; + logic opa_ready, opb_ready, opc_ready; + logic dstrd_ready, dstrs1_ready; + + always_comb begin + sb_d = sb_q; + if (retire_load) sb_d[lsu_rd] = 1'b0; + // only place the reservation if we actually executed the load or offload instruction + if ((is_load | acc_register_rd) && !stall && !exception) sb_d[rd] = 1'b1; + if (retire_acc) sb_d[acc_pid_i[RegWidth-1:0]] = 1'b0; + sb_d[0] = 1'b0; + end + // TODO(zarubaf): This can probably be described a bit more efficient + assign opa_ready = (opa_select != Reg) | ~sb_q[rs1]; + assign opb_ready = ((opb_select != Reg & opb_select != SImmediate) | ~sb_q[rs2]) & ((opb_select != RegRd) | ~sb_q[rd]); + assign opc_ready = ((opc_select != Reg) | ~sb_q[rd]) & ((opc_select != RegRs2) | ~sb_q[rs2]); + assign operands_ready = opa_ready & opb_ready & opc_ready; + // either we are not using the destination register or we need to make + // sure that its destination operand is not marked busy in the scoreboard. + assign dstrd_ready = ~uses_rd | (uses_rd & ~sb_q[rd]); + assign dstrs1_ready = ~uses_rs1 | (uses_rs1 & ~sb_q[rs1]); + assign dst_ready = dstrd_ready & dstrs1_ready; + + assign valid_instr = (inst_ready_i & inst_valid_o) & operands_ready & dst_ready; + // the accelerator interface stalled us + assign acc_stall = (acc_qvalid_o & ~acc_qready_i); + // the LSU Interface didn't accept our request yet + assign lsu_stall = (lsu_qvalid & ~lsu_qready); + // Stall the stage if we either didn't get a valid instruction or the LSU/Accelerator is not ready + assign stall = ~valid_instr | lsu_stall | acc_stall; + + // -------------------- + // Instruction Frontend + // -------------------- + assign consec_pc = pc_q + ((is_branch & alu_result[0]) ? bimm : 'd4); + + always_comb begin + pc_d = pc_q; + // if we got a valid instruction word increment the PC unless we are waiting for an event + if (!stall && !wfi_q) begin + casez (next_pc) + Consec: pc_d = consec_pc; + Alu: pc_d = alu_result & {{31{1'b1}}, ~zero_lsb}; + Exception: pc_d = MTVEC; + endcase + end + end + + // -------------------- + // Decoder + // -------------------- + assign rd = inst_data_i[7 + RegWidth - 1:7]; + assign rs1 = inst_data_i[15 + RegWidth - 1:15]; + assign rs2 = inst_data_i[20 + RegWidth - 1:20]; + + always_comb begin + illegal_inst = 1'b0; + alu_op = Add; + opa_select = None; + opb_select = None; + opc_select = None; + + next_pc = Consec; + + // set up rd destination + rd_select = RdAlu; + write_rd = 1'b1; + // if we are writing the field this cycle we need an int destination register + uses_rd = write_rd; + // set up rs1 destination + write_rs1 = 1'b0; + uses_rs1 = write_rs1; + + rd_bypass = '0; + zero_lsb = 1'b0; + is_branch = 1'b0; + // LSU interface + is_load = 1'b0; + is_store = 1'b0; + is_postincr = 1'b0; + is_fp_load = 1'b0; + is_fp_store = 1'b0; + is_signed = 1'b0; + ls_size = Byte; + ls_amo = AMONone; + + acc_qvalid_o = 1'b0; + acc_register_rd = 1'b0; + + csr_en = 1'b0; + // Wake up if a wake-up is incoming or pending + wfi_d = (wake_up_q || wake_up_sync_i) ? 1'b0 : wfi_q; + // Only store a pending wake-up if we are not asleep + wake_up_d = (wake_up_sync_i && !wfi_q) ? 1'b1 : wake_up_q; + + unique casez (inst_data_i) + riscv_instr::ADD: begin + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::ADDI: begin + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SUB: begin + alu_op = Sub; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::XOR: begin + opa_select = Reg; + opb_select = Reg; + alu_op = LXor; + end + riscv_instr::XORI: begin + alu_op = LXor; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::OR: begin + opa_select = Reg; + opb_select = Reg; + alu_op = LOr; + end + riscv_instr::ORI: begin + alu_op = LOr; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::AND: begin + alu_op = LAnd; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::ANDI: begin + alu_op = LAnd; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SLT: begin + alu_op = Slt; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SLTI: begin + alu_op = Slt; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SLTU: begin + alu_op = Sltu; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SLTIU: begin + alu_op = Sltu; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SLL: begin + alu_op = Sll; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SRL: begin + alu_op = Srl; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SRA: begin + alu_op = Sra; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SLLI: begin + alu_op = Sll; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SRLI: begin + alu_op = Srl; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::SRAI: begin + alu_op = Sra; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::LUI: begin + opa_select = None; + opb_select = None; + rd_select = RdBypass; + rd_bypass = uimm; + end + riscv_instr::AUIPC: begin + opa_select = UImmediate; + opb_select = PC; + end + riscv_instr::JAL: begin + rd_select = RdConsecPC; + opa_select = JImmediate; + opb_select = PC; + next_pc = Alu; + end + riscv_instr::JALR: begin + rd_select = RdConsecPC; + opa_select = Reg; + opb_select = IImmediate; + next_pc = Alu; + zero_lsb = 1'b1; + end + // use the ALU for comparisons + riscv_instr::BEQ: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Eq; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::BNE: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Neq; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::BLT: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Slt; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::BLTU: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Sltu; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::BGE: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Ge; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::BGEU: begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Geu; + opa_select = Reg; + opb_select = Reg; + end + // Load/Stores + riscv_instr::SB: begin + write_rd = 1'b0; + is_store = 1'b1; + opa_select = Reg; + opb_select = SImmediate; + end + riscv_instr::SH: begin + write_rd = 1'b0; + is_store = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = SImmediate; + end + riscv_instr::SW: begin + write_rd = 1'b0; + is_store = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = SImmediate; + end + riscv_instr::LB: begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::LH: begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::LW: begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::LBU: begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + opa_select = Reg; + opb_select = IImmediate; + end + riscv_instr::LHU: begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = IImmediate; + end + // CSR Instructions + riscv_instr::CSRRW: begin // Atomic Read/Write CSR + opa_select = Reg; + opb_select = None; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + riscv_instr::CSRRWI: begin + opa_select = CSRImmediate; + opb_select = None; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + riscv_instr::CSRRS: begin // Atomic Read and Set Bits in CSR + alu_op = LOr; + opa_select = Reg; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + riscv_instr::CSRRSI: begin + // offload CSR enable to FP SS + if (inst_data_i[31:20] != snitch_pkg::CSR_SSR) begin + alu_op = LOr; + opa_select = CSRImmediate; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end else begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end + end + riscv_instr::CSRRC: begin // Atomic Read and Clear Bits in CSR + alu_op = LNAnd; + opa_select = Reg; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end + riscv_instr::CSRRCI: begin + if (inst_data_i[31:20] != snitch_pkg::CSR_SSR) begin + alu_op = LNAnd; + opa_select = CSRImmediate; + opb_select = CSR; + rd_select = RdBypass; + rd_bypass = csr_rvalue; + csr_en = 1'b1; + end else begin + write_rd = 1'b0; + acc_qvalid_o = valid_instr; + end + end + riscv_instr::ECALL, + riscv_instr::EBREAK: begin + // TODO(zarubaf): Trap to precise address + write_rd = 1'b0; + end + // NOP Instructions + riscv_instr::FENCE: begin + write_rd = 1'b0; + end + riscv_instr::WFI: begin + if (valid_instr) begin + wfi_d = 1'b1; + if (wake_up_q || wake_up_sync_i) begin + // Do not sleep if a wake-up is pending + wfi_d = 1'b0; + wake_up_d = 1'b0; + end + end + end + // Atomics + riscv_instr::AMOADD_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOAdd; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOXOR_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOXor; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOOR_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOOr; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOAND_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOAnd; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOMIN_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOMin; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOMAX_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOMax; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOMINU_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOMinu; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOMAXU_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOMaxu; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::AMOSWAP_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOSwap; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::LR_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOLR; + opa_select = Reg; + opb_select = Reg; + end + riscv_instr::SC_W: begin + alu_op = BypassA; + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + ls_amo = AMOSC; + opa_select = Reg; + opb_select = Reg; + end + // Off-load to IPU coprocessor + riscv_instr::MUL, + riscv_instr::MULH, + riscv_instr::MULHSU, + riscv_instr::MULHU, + riscv_instr::DIV, + riscv_instr::DIVU, + riscv_instr::REM, + riscv_instr::REMU, + riscv_instr::MULW, + riscv_instr::DIVW, + riscv_instr::DIVUW, + riscv_instr::REMW, + riscv_instr::REMUW: begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + opb_select = Reg; + acc_register_rd = 1'b1; + end + +/* Xpulpimg extension */ + // Post-increment loads/stores + riscv_instr::P_LB_IRPOST: begin // Xpulpimg: p.lb rd,iimm(rs1!) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + opa_select = Reg; + opb_select = IImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LBU_IRPOST: begin // Xpulpimg: p.lbu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + opa_select = Reg; + opb_select = IImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LH_IRPOST: begin // Xpulpimg: p.lh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = IImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LHU_IRPOST: begin // Xpulpimg: p.lhu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = IImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LW_IRPOST: begin // Xpulpimg: p.lw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = IImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LB_RRPOST: begin // Xpulpimg: p.lb rd,rs2(rs1!) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LBU_RRPOST: begin // Xpulpimg: p.lbu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LH_RRPOST: begin // Xpulpimg: p.lh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LHU_RRPOST: begin // Xpulpimg: p.lhu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LW_RRPOST: begin // Xpulpimg: p.lw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + write_rs1 = 1'b1; + is_load = 1'b1; + is_postincr = 1'b1; + is_signed = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LB_RR: begin // Xpulpimg: p.lb rd,rs2(rs1) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LBU_RR: begin // Xpulpimg: p.lbu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LH_RR: begin // Xpulpimg: p.lh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LHU_RR: begin // Xpulpimg: p.lhu + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_LW_RR: begin // Xpulpimg: p.lw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + is_load = 1'b1; + is_signed = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = Reg; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SB_IRPOST: begin // Xpulpimg: p.sb rs2,simm(rs1!) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + opa_select = Reg; + opb_select = SImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SH_IRPOST: begin // Xpulpimg: p.sh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = SImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SW_IRPOST: begin // Xpulpimg: p.sw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = SImmediate; + end else begin + illegal_inst = 1'b1; + end + end + // opb is usually assigned with the content of rs2; in stores with reg-reg + // addressing mode, however, the offset is stored in rd, so rd content is + // instead assigned to opb: if we cross such signals now (rd -> opb, + // rs2 -> opc) we don't have to do that in the ALU, with bigger muxes + riscv_instr::P_SB_RRPOST: begin // Xpulpimg: p.sb rs2,rs3(rs1!) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + opa_select = Reg; // rs1 base address + opb_select = RegRd; // rs3 (i.e. rd) offset + opc_select = RegRs2; // rs2 source data + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SH_RRPOST: begin // Xpulpimg: p.sh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = RegRd; + opc_select = RegRs2; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SW_RRPOST: begin // Xpulpimg: p.sw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + write_rs1 = 1'b1; + is_store = 1'b1; + is_postincr = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = RegRd; + opc_select = RegRs2; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SB_RR: begin // Xpulpimg: p.sb rs2,rs3(rs1) + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + is_store = 1'b1; + opa_select = Reg; + opb_select = RegRd; + opc_select = RegRs2; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SH_RR: begin // Xpulpimg: p.sh + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + is_store = 1'b1; + ls_size = HalfWord; + opa_select = Reg; + opb_select = RegRd; + opc_select = RegRs2; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_SW_RR: begin // Xpulpimg: p.sw + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + is_store = 1'b1; + ls_size = Word; + opa_select = Reg; + opb_select = RegRd; + opc_select = RegRs2; + end else begin + illegal_inst = 1'b1; + end + end + // Immediate branching + riscv_instr::P_BEQIMM: begin // Xpulpimg: p.beqimm + if (snitch_pkg::XPULPIMG) begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Eq; + opa_select = Reg; + opb_select = PBImmediate; + end else begin + illegal_inst = 1'b1; + end + end + riscv_instr::P_BNEIMM: begin // Xpulpimg: p.bneimm + if (snitch_pkg::XPULPIMG) begin + is_branch = 1'b1; + write_rd = 1'b0; + alu_op = Neq; + opa_select = Reg; + opb_select = PBImmediate; + end else begin + illegal_inst = 1'b1; + end + end + // Off-load to IPU coprocessor + // 1 source register (rs1) + riscv_instr::P_ABS, // Xpulpimg: p.abs + riscv_instr::P_EXTHS, // Xpulpimg: p.exths + riscv_instr::P_EXTHZ, // Xpulpimg: p.exthz + riscv_instr::P_EXTBS, // Xpulpimg: p.extbs + riscv_instr::P_EXTBZ, // Xpulpimg: p.extbz + riscv_instr::P_CLIP, // Xpulpimg: p.clip + riscv_instr::P_CLIPU, // Xpulpimg: p.clipu + riscv_instr::PV_ADD_SCI_H, // Xpulpimg: pv.add.sci.h + riscv_instr::PV_ADD_SCI_B, // Xpulpimg: pv.add.sci.b + riscv_instr::PV_SUB_SCI_H, // Xpulpimg: pv.sub.sci.h + riscv_instr::PV_SUB_SCI_B, // Xpulpimg: pv.sub.sci.b + riscv_instr::PV_AVG_SCI_H, // Xpulpimg: pv.avg.sci.h + riscv_instr::PV_AVG_SCI_B, // Xpulpimg: pv.avg.sci.b + riscv_instr::PV_AVGU_SCI_H, // Xpulpimg: pv.avgu.sci.h + riscv_instr::PV_AVGU_SCI_B, // Xpulpimg: pv.avgu.sci.b + riscv_instr::PV_MIN_SCI_H, // Xpulpimg: pv.min.sci.h + riscv_instr::PV_MIN_SCI_B, // Xpulpimg: pv.min.sci.b + riscv_instr::PV_MINU_SCI_H, // Xpulpimg: pv.minu.sci.h + riscv_instr::PV_MINU_SCI_B, // Xpulpimg: pv.minu.sci.b + riscv_instr::PV_MAX_SCI_H, // Xpulpimg: pv.max.sci.h + riscv_instr::PV_MAX_SCI_B, // Xpulpimg: pv.max.sci.b + riscv_instr::PV_MAXU_SCI_H, // Xpulpimg: pv.maxu.sci.h + riscv_instr::PV_MAXU_SCI_B, // Xpulpimg: pv.maxu.sci.b + riscv_instr::PV_SRL_SCI_H, // Xpulpimg: pv.srl.sci.h + riscv_instr::PV_SRL_SCI_B, // Xpulpimg: pv.srl.sci.b + riscv_instr::PV_SRA_SCI_H, // Xpulpimg: pv.sra.sci.h + riscv_instr::PV_SRA_SCI_B, // Xpulpimg: pv.sra.sci.b + riscv_instr::PV_SLL_SCI_H, // Xpulpimg: pv.sll.sci.h + riscv_instr::PV_SLL_SCI_B, // Xpulpimg: pv.sll.sci.b + riscv_instr::PV_OR_SCI_H, // Xpulpimg: pv.or.sci.h + riscv_instr::PV_OR_SCI_B, // Xpulpimg: pv.or.sci.b + riscv_instr::PV_XOR_SCI_H, // Xpulpimg: pv.xor.sci.h + riscv_instr::PV_XOR_SCI_B, // Xpulpimg: pv.xor.sci.b + riscv_instr::PV_AND_SCI_B, // Xpulpimg: pv.and.sci.b + riscv_instr::PV_AND_SCI_H, // Xpulpimg: pv.and.sci.h + riscv_instr::PV_ABS_H, // Xpulpimg: pv.abs.h + riscv_instr::PV_ABS_B, // Xpulpimg: pv.abs.b + riscv_instr::PV_EXTRACT_H, // Xpulpimg: pv.extract.h + riscv_instr::PV_EXTRACT_B, // Xpulpimg: pv.extract.b + riscv_instr::PV_EXTRACTU_H, // Xpulpimg: pv.extractu.h + riscv_instr::PV_EXTRACTU_B, // Xpulpimg: pv.extractu.b + riscv_instr::PV_DOTUP_SCI_H, // Xpulpimg: pv.dotup.sci.h + riscv_instr::PV_DOTUP_SCI_B, // Xpulpimg: pv.dotup.sci.b + riscv_instr::PV_DOTUSP_SCI_H, // Xpulpimg: pv.dotusp.sci.h + riscv_instr::PV_DOTUSP_SCI_B, // Xpulpimg: pv.dotusp.sci.b + riscv_instr::PV_DOTSP_SCI_H, // Xpulpimg: pv.dotsp.sci.h + riscv_instr::PV_DOTSP_SCI_B: begin // Xpulpimg: pv.dotsp.sci.b + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 2 source registers (rs1, rs2) + riscv_instr::P_SLET, // Xpulpimg: p.slet + riscv_instr::P_SLETU, // Xpulpimg: p.sletu + riscv_instr::P_MIN, // Xpulpimg: p.min + riscv_instr::P_MINU, // Xpulpimg: p.minu + riscv_instr::P_MAX, // Xpulpimg: p.max + riscv_instr::P_MAXU, // Xpulpimg: p.maxu + riscv_instr::P_CLIPR, // Xpulpimg: p.clipr + riscv_instr::P_CLIPUR, // Xpulpimg: p.clipur + riscv_instr::PV_ADD_H, // Xpulpimg: pv.add.h + riscv_instr::PV_ADD_SC_H, // Xpulpimg: pv.add.sc.h + riscv_instr::PV_ADD_B, // Xpulpimg: pv.add.b + riscv_instr::PV_ADD_SC_B, // Xpulpimg: pv.add.sc.b + riscv_instr::PV_SUB_H, // Xpulpimg: pv.sub.h + riscv_instr::PV_SUB_SC_H, // Xpulpimg: pv.sub.sc.h + riscv_instr::PV_SUB_B, // Xpulpimg: pv.sub.b + riscv_instr::PV_SUB_SC_B, // Xpulpimg: pv.sub.sc.b + riscv_instr::PV_AVG_H, // Xpulpimg: pv.avg.h + riscv_instr::PV_AVG_SC_H, // Xpulpimg: pv.avg.sc.h + riscv_instr::PV_AVG_B, // Xpulpimg: pv.avg.b + riscv_instr::PV_AVG_SC_B, // Xpulpimg: pv.avg.sc.b + riscv_instr::PV_AVGU_H, // Xpulpimg: pv.avgu.h + riscv_instr::PV_AVGU_SC_H, // Xpulpimg: pv.avgu.sc.h + riscv_instr::PV_AVGU_B, // Xpulpimg: pv.avgu.b + riscv_instr::PV_AVGU_SC_B, // Xpulpimg: pv.avgu.sc.b + riscv_instr::PV_MIN_H, // Xpulpimg: pv.min.h + riscv_instr::PV_MIN_SC_H, // Xpulpimg: pv.min.sc.h + riscv_instr::PV_MIN_B, // Xpulpimg: pv.min.b + riscv_instr::PV_MIN_SC_B, // Xpulpimg: pv.min.sc.b + riscv_instr::PV_MINU_H, // Xpulpimg: pv.minu.h + riscv_instr::PV_MINU_SC_H, // Xpulpimg: pv.minu.sc.h + riscv_instr::PV_MINU_B, // Xpulpimg: pv.minu.b + riscv_instr::PV_MINU_SC_B, // Xpulpimg: pv.minu.sc.b + riscv_instr::PV_MAX_H, // Xpulpimg: pv.max.h + riscv_instr::PV_MAX_SC_H, // Xpulpimg: pv.max.sc.h + riscv_instr::PV_MAX_B, // Xpulpimg: pv.max.b + riscv_instr::PV_MAX_SC_B, // Xpulpimg: pv.max.sc.b + riscv_instr::PV_MAXU_H, // Xpulpimg: pv.maxu.h + riscv_instr::PV_MAXU_SC_H, // Xpulpimg: pv.maxu.sc.h + riscv_instr::PV_MAXU_B, // Xpulpimg: pv.maxu.b + riscv_instr::PV_MAXU_SC_B, // Xpulpimg: pv.maxu.sc.b + riscv_instr::PV_SRL_H, // Xpulpimg: pv.srl.h + riscv_instr::PV_SRL_SC_H, // Xpulpimg: pv.srl.sc.h + riscv_instr::PV_SRL_B, // Xpulpimg: pv.srl.b + riscv_instr::PV_SRL_SC_B, // Xpulpimg: pv.srl.sc.b + riscv_instr::PV_SRA_H, // Xpulpimg: pv.sra.h + riscv_instr::PV_SRA_SC_H, // Xpulpimg: pv.sra.sc.h + riscv_instr::PV_SRA_B, // Xpulpimg: pv.sra.b + riscv_instr::PV_SRA_SC_B, // Xpulpimg: pv.sra.sc.b + riscv_instr::PV_SLL_H, // Xpulpimg: pv.sll.h + riscv_instr::PV_SLL_SC_H, // Xpulpimg: pv.sll.sc.h + riscv_instr::PV_SLL_B, // Xpulpimg: pv.sll.b + riscv_instr::PV_SLL_SC_B, // Xpulpimg: pv.sll.sc.b + riscv_instr::PV_OR_H, // Xpulpimg: pv.or.h + riscv_instr::PV_OR_SC_H, // Xpulpimg: pv.or.sc.h + riscv_instr::PV_OR_B, // Xpulpimg: pv.or.b + riscv_instr::PV_OR_SC_B, // Xpulpimg: pv.or.sc.b + riscv_instr::PV_XOR_H, // Xpulpimg: pv.xor.h + riscv_instr::PV_XOR_SC_H, // Xpulpimg: pv.xor.sc.h + riscv_instr::PV_XOR_B, // Xpulpimg: pv.xor.b + riscv_instr::PV_XOR_SC_B, // Xpulpimg: pv.xor.sc.b + riscv_instr::PV_AND_H, // Xpulpimg: pv.and.h + riscv_instr::PV_AND_SC_H, // Xpulpimg: pv.and.sc.h + riscv_instr::PV_AND_B, // Xpulpimg: pv.and.b + riscv_instr::PV_AND_SC_B, // Xpulpimg: pv.and.sc.b + riscv_instr::PV_DOTUP_H, // Xpulpimg: pv.dotup.h + riscv_instr::PV_DOTUP_SC_H, // Xpulpimg: pv.dotup.sc.h + riscv_instr::PV_DOTUP_B, // Xpulpimg: pv.dotup.b + riscv_instr::PV_DOTUP_SC_B, // Xpulpimg: pv.dotup.sc.b + riscv_instr::PV_DOTUSP_H, // Xpulpimg: pv.dotusp.h + riscv_instr::PV_DOTUSP_SC_H, // Xpulpimg: pv.dotusp.sc.h + riscv_instr::PV_DOTUSP_B, // Xpulpimg: pv.dotusp.b + riscv_instr::PV_DOTUSP_SC_B, // Xpulpimg: pv.dotusp.sc.b + riscv_instr::PV_DOTSP_H, // Xpulpimg: pv.dotsp.h + riscv_instr::PV_DOTSP_SC_H, // Xpulpimg: pv.dotsp.sc.h + riscv_instr::PV_DOTSP_B, // Xpulpimg: pv.dotsp.b + riscv_instr::PV_DOTSP_SC_B: begin // Xpulpimg: pv.dotsp.sc.b + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + opb_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 2 source registers (rs1, rd) + riscv_instr::PV_INSERT_H, // Xpulpimg: pv.insert.h + riscv_instr::PV_INSERT_B, // Xpulpimg: pv.insert.b + riscv_instr::PV_SDOTUP_SCI_H, // Xpulpimg: pv.sdotup.sci.h + riscv_instr::PV_SDOTUP_SCI_B, // Xpulpimg: pv.sdotup.sci.b + riscv_instr::PV_SDOTUSP_SCI_H, // Xpulpimg: pv.sdotusp.sci.h + riscv_instr::PV_SDOTUSP_SCI_B, // Xpulpimg: pv.sdotusp.sci.b + riscv_instr::PV_SDOTSP_SCI_H, // Xpulpimg: pv.sdotsp.sci.h + riscv_instr::PV_SDOTSP_SCI_B: begin // Xpulpimg: pv.sdotsp.sci.b + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + opc_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end + // 3 source registers (rs1, rs2, rd) + riscv_instr::P_MAC, // Xpulpimg: p.mac + riscv_instr::P_MSU, // Xpulpimg: p.msu + riscv_instr::PV_SDOTUP_H, // Xpulpimg: pv.sdotup.h + riscv_instr::PV_SDOTUP_SC_H, // Xpulpimg: pv.sdotup.sc.h + riscv_instr::PV_SDOTUP_B, // Xpulpimg: pv.sdotup.b + riscv_instr::PV_SDOTUP_SC_B, // Xpulpimg: pv.sdotup.sc.b + riscv_instr::PV_SDOTUSP_H, // Xpulpimg: pv.sdotusp.h + riscv_instr::PV_SDOTUSP_SC_H, // Xpulpimg: pv.sdotusp.sc.h + riscv_instr::PV_SDOTUSP_B, // Xpulpimg: pv.sdotusp.b + riscv_instr::PV_SDOTUSP_SC_B, // Xpulpimg: pv.sdotusp.sc.b + riscv_instr::PV_SDOTSP_H, // Xpulpimg: pv.sdotsp.h + riscv_instr::PV_SDOTSP_SC_H, // Xpulpimg: pv.sdotsp.sc.h + riscv_instr::PV_SDOTSP_B, // Xpulpimg: pv.sdotsp.b + riscv_instr::PV_SDOTSP_SC_B, // Xpulpimg: pv.sdotsp.sc.b + riscv_instr::PV_SHUFFLE2_H, // Xpulpimg: pv.shuffle2.h + riscv_instr::PV_SHUFFLE2_B: begin // Xpulpimg: pv.shuffle2.b + if (snitch_pkg::XPULPIMG) begin + write_rd = 1'b0; + uses_rd = 1'b1; + acc_qvalid_o = valid_instr; + opa_select = Reg; + opb_select = Reg; + opc_select = Reg; + acc_register_rd = 1'b1; + end else begin + illegal_inst = 1'b1; + end + end +/* end of Xpulpimg extension */ + + // TODO(zarubaf): Illegal Instructions + default: begin + illegal_inst = 1'b1; + end + endcase + + // Sanitize illegal instructions so that they don't exert any side-effects. + if (exception) begin + write_rd = 1'b0; + uses_rd = 1'b0; + write_rs1 = 1'b0; + uses_rs1 = 1'b0; + acc_qvalid_o = 1'b0; + next_pc = Exception; + end + end + + assign exception = illegal_inst | ld_addr_misaligned | st_addr_misaligned; + + // pragma translate_off + always_ff @(posedge clk_i or posedge rst_i) begin + if (!rst_i && illegal_inst && inst_valid_o && inst_ready_i) begin + $display("[Illegal Instruction Core %0d] PC: %h Data: %h", hart_id_i, inst_addr_o, inst_data_i); + end + if (!rst_i && wake_up_sync_i && wake_up_q) begin + $display("[Missed wake-up Core %0d] Cycle: %d, Time: %t", hart_id_i, cycle_q, $time); + end + end + // pragma translate_on + + // CSR logic + logic csr_dump; + logic csr_trace_en; + logic csr_trace_q; + + always_comb begin + csr_rvalue = '0; + csr_dump = 1'b0; + csr_trace_en = 1'b0; + + // TODO(zarubaf): Needs some more input handling, like illegal instruction exceptions. + // Right now we skip this due to simplicity. + if (csr_en) begin + unique case (inst_data_i[31:20]) + riscv_instr::CSR_MHARTID: begin + csr_rvalue = hart_id_i; + end + riscv_instr::CSR_TRACE: begin + csr_rvalue = csr_trace_q; + csr_trace_en = 1'b1; + end + `ifdef SNITCH_ENABLE_PERF + riscv_instr::CSR_MCYCLE: begin + csr_rvalue = cycle_q[31:0]; + end + riscv_instr::CSR_MINSTRET: begin + csr_rvalue = instret_q[31:0]; + end + riscv_instr::CSR_MCYCLEH: begin + csr_rvalue = cycle_q[63:32]; + end + riscv_instr::CSR_MINSTRETH: begin + csr_rvalue = instret_q[63:32]; + end + `endif + default: begin + csr_rvalue = '0; + csr_dump = 1'b1; + end + endcase + end + end + + // CSR registers + `FFLAR(csr_trace_q, alu_result, csr_trace_en, '0, clk_i, rst_i); + + // pragma translate_off + always_ff @(posedge clk_i or posedge rst_i) begin + // Display CSR write if the CSR does not exist + if (!rst_i && csr_dump && inst_valid_o && inst_ready_i && !stall) begin + $display("[DUMP] %3d: 0x%3h = %d", hart_id_i, inst_data_i[31:20], alu_result); + end + end + // pragma translate_on + + snitch_regfile #( + .DATA_WIDTH ( 32 ), + .NR_READ_PORTS ( RegNrReadPorts ), + .NR_WRITE_PORTS ( RegNrWritePorts ), + .ZERO_REG_ZERO ( 1 ), + .ADDR_WIDTH ( RegWidth ) + ) i_snitch_regfile ( + .clk_i, + .raddr_i ( gpr_raddr ), + .rdata_o ( gpr_rdata ), + .waddr_i ( gpr_waddr ), + .wdata_i ( gpr_wdata ), + .we_i ( gpr_we ) + ); + + // -------------------- + // Operand Select + // -------------------- + always_comb begin + unique case (opa_select) + None: opa = '0; + Reg: opa = gpr_rdata[0]; + UImmediate: opa = uimm; + JImmediate: opa = jimm; + CSRImmediate: opa = {{{32-RegWidth}{1'b0}}, rs1}; + default: opa = '0; + endcase + end + + always_comb begin + unique case (opb_select) + None: opb = '0; + Reg: opb = gpr_rdata[1]; + IImmediate: opb = iimm; + SFImmediate, SImmediate: opb = simm; + PC: opb = pc_q; + CSR: opb = csr_rvalue; + PBImmediate: opb = pbimm; + RegRd: opb = gpr_rdata[2]; + default: opb = '0; + endcase + end + + assign gpr_raddr[0] = rs1; + assign gpr_raddr[1] = rs2; + // connect third read port only if present + if (RegNrReadPorts >= 3) begin : gpr_raddr_2 + assign gpr_raddr[2] = rd; + end + + // -------------------- + // ALU + // -------------------- + // Main Shifter + logic [31:0] shift_opa, shift_opa_reversed; + logic [31:0] shift_right_result, shift_left_result; + logic [32:0] shift_opa_ext, shift_right_result_ext; + logic shift_left, shift_arithmetic; // shift control + for (genvar i = 0; i < 32; i++) begin : gen_reverse_opa + assign shift_opa_reversed[i] = opa[31-i]; + assign shift_left_result[i] = shift_right_result[31-i]; + end + assign shift_opa = shift_left ? shift_opa_reversed : opa; + assign shift_opa_ext = {shift_opa[31] & shift_arithmetic, shift_opa}; + assign shift_right_result_ext = $unsigned($signed(shift_opa_ext) >>> opb[4:0]); + assign shift_right_result = shift_right_result_ext[31:0]; + + // Main Adder + logic [32:0] alu_opa, alu_opb; + assign adder_result = alu_opa + alu_opb; + + // ALU + /* verilator lint_off WIDTH */ + always_comb begin + alu_opa = $signed(opa); + alu_opb = $signed(opb); + + alu_result = adder_result[31:0]; + shift_left = 1'b0; + shift_arithmetic = 1'b0; + + unique case (alu_op) + // Arithmetical operations + Sub: alu_opb = -$signed(opb); + // Comparisons + Slt: begin + alu_opb = -$signed(opb); + alu_result = {30'b0, adder_result[32]}; + end + Ge: begin + alu_opb = -$signed(opb); + alu_result = {30'b0, ~adder_result[32]}; + end + Sltu: begin + alu_opa = $unsigned(opa); + alu_opb = -$unsigned(opb); + alu_result = {30'b0, adder_result[32]}; + end + Geu: begin + alu_opa = $unsigned(opa); + alu_opb = -$unsigned(opb); + alu_result = {30'b0, ~adder_result[32]}; + end + // Shifts + Sll: begin + shift_left = 1'b1; + alu_result = shift_left_result; + end + Srl: alu_result = shift_right_result; + Sra: begin + shift_arithmetic = 1'b1; + alu_result = shift_right_result; + end + // Logical operations + LXor: alu_result = opa ^ opb; + LAnd: alu_result = opa & opb; + LNAnd: alu_result = (~opa) & opb; + LOr: alu_result = opa | opb; + // Equal, not equal + Eq: begin + alu_opb = -$signed(opb); + alu_result = ~|adder_result; + end + Neq: begin + alu_opb = -$signed(opb); + alu_result = |adder_result; + end + // Miscellaneous + BypassA: begin + alu_result = opa; + end + default: alu_result = adder_result[31:0]; + endcase + end + /* verilator lint_on WIDTH */ + + // -------------------- + // LSU + // -------------------- + snitch_lsu #( + .tag_t ( logic[RegWidth-1:0] ), + .NumOutstandingLoads ( snitch_pkg::NumIntOutstandingLoads ) + ) i_snitch_lsu ( + .clk_i , + .rst_i , + .lsu_qtag_i ( rd ), + .lsu_qwrite ( is_store ), + .lsu_qsigned ( is_signed ), + .lsu_qaddr_i ( lsu_qaddr ), + .lsu_qdata_i ( gpr_rdata[1] ), + .lsu_qsize_i ( ls_size ), + .lsu_qamo_i ( ls_amo ), + .lsu_qvalid_i ( lsu_qvalid ), + .lsu_qready_o ( lsu_qready ), + .lsu_pdata_o ( ld_result ), + .lsu_ptag_o ( lsu_rd ), + .lsu_perror_o ( ), // ignored for the moment + .lsu_pvalid_o ( lsu_pvalid ), + .lsu_pready_i ( lsu_pready ), + .data_qaddr_o , + .data_qwrite_o , + .data_qdata_o , + .data_qamo_o , + .data_qstrb_o , + .data_qid_o , + .data_qvalid_o , + .data_qready_i , + .data_pdata_i , + .data_perror_i , + .data_pid_i , + .data_pvalid_i , + .data_pready_o + ); + + // address can be alu_result (i.e. rs1 + iimm/simm) or rs1 (for post-increment load/stores) + assign lsu_qaddr = is_postincr ? gpr_rdata[0] : alu_result; + + assign lsu_qvalid = valid_instr & (is_load | is_store) & ~(ld_addr_misaligned | st_addr_misaligned); + + // NOTE(smazzola): write-backs "on rd from non-load or non-acc instructions" and "on rs1 from + // post-increment instructions" in the same cycle should be mutually exclusive (currently valid + // assumption since write-back to rs1 happens on the cycle in which the post-increment load/store + // is issued, if that cycle is not a stall, and it is not postponed like offloaded instructions, + // so no other instructions writing back on rd can be issued in the same cycle) + // retire post-incremented address on rs1 if valid postincr instruction and LSU not stalling + assign retire_p = write_rs1 & ~stall & (rs1 != 0); + // we can retire if we are not stalling and if the instruction is writing a register + assign retire_i = write_rd & valid_instr & (rd != 0); + + // ----------------------- + // Unaligned Address Check + // ----------------------- + always_comb begin + ls_misaligned = 1'b0; + unique case (ls_size) + HalfWord: if (alu_result[0] != 1'b0) ls_misaligned = 1'b1; + Word: if (alu_result[1:0] != 2'b00) ls_misaligned = 1'b1; + Double: if (alu_result[2:0] != 3'b000) ls_misaligned = 1'b1; + default: ls_misaligned = 1'b0; + endcase + end + + assign st_addr_misaligned = ls_misaligned & (is_store | is_fp_store); + assign ld_addr_misaligned = ls_misaligned & (is_load | is_fp_load); + + // pragma translate_off + always_ff @(posedge clk_i or posedge rst_i) begin + if (!rst_i && (ld_addr_misaligned || st_addr_misaligned) && valid_instr && inst_ready_i) begin + $display("%t: [Misaligned Load/Store Core %0d] PC: %h Address: %h Data: %h", $time, hart_id_i, inst_addr_o, alu_result, inst_data_i); + end + end + // pragma translate_on + + // -------------------- + // Write-Back + // -------------------- + // Write-back data, can come from: + // 1. ALU/Jump Target/Bypass + // 2. LSU + // 3. Accelerator Bus + logic [31:0] alu_writeback; + always_comb begin + casez (rd_select) + RdAlu: alu_writeback = alu_result; + RdConsecPC: alu_writeback = consec_pc; + RdBypass: alu_writeback = rd_bypass; + default: alu_writeback = alu_result; + endcase + end + + if (RegNrWritePorts == 1) begin + always_comb begin + gpr_we[0] = 1'b0; + // NOTE(smazzola): this works because write-backs on rd and rs1 in the same cycle are mutually + // exclusive; if this should change, the following statement has to be written in another form + gpr_waddr[0] = retire_p ? rs1 : rd; // choose whether to writeback at RF[rs1] for post-increment load/stores + gpr_wdata[0] = alu_writeback; + // external interfaces + lsu_pready = 1'b0; + acc_pready_o = 1'b0; + retire_acc = 1'b0; + retire_load = 1'b0; + + if (retire_i | retire_p) begin + gpr_we[0] = 1'b1; + // if we are not retiring another instruction retire the load now + end else if (lsu_pvalid) begin + retire_load = 1'b1; + gpr_we[0] = 1'b1; + gpr_waddr[0] = lsu_rd; + gpr_wdata[0] = ld_result[31:0]; + lsu_pready = 1'b1; + end else if (acc_pvalid_i) begin + retire_acc = 1'b1; + gpr_we[0] = 1'b1; + gpr_waddr[0] = acc_pid_i; + gpr_wdata[0] = acc_pdata_i[31:0]; + acc_pready_o = 1'b1; + end + end + end else if (RegNrWritePorts == 2) begin + always_comb begin + gpr_we[0] = 1'b0; + // NOTE(smazzola): this works because write-backs on rd and rs1 in the same cycle are mutually + // exclusive; if this should change, the following statement has to be written in another form + gpr_waddr[0] = retire_p ? rs1 : rd; // choose whether to writeback at RF[rs1] for post-increment load/stores + gpr_wdata[0] = alu_writeback; + gpr_we[1] = 1'b0; + gpr_waddr[1] = lsu_rd; + gpr_wdata[1] = ld_result[31:0]; + // external interfaces + lsu_pready = 1'b0; + acc_pready_o = 1'b0; + retire_acc = 1'b0; + retire_load = 1'b0; + + if (retire_i | retire_p) begin + gpr_we[0] = 1'b1; + if (lsu_pvalid) begin + retire_load = 1'b1; + gpr_we[1] = 1'b1; + lsu_pready = 1'b1; + end else if (acc_pvalid_i) begin + retire_acc = 1'b1; + gpr_we[1] = 1'b1; + gpr_waddr[1] = acc_pid_i; + gpr_wdata[1] = acc_pdata_i[31:0]; + acc_pready_o = 1'b1; + end + // if we are not retiring another instruction retire the load now + end else begin + if (acc_pvalid_i) begin + retire_acc = 1'b1; + gpr_we[0] = 1'b1; + gpr_waddr[0] = acc_pid_i; + gpr_wdata[0] = acc_pdata_i[31:0]; + acc_pready_o = 1'b1; + end + if (lsu_pvalid) begin + retire_load = 1'b1; + gpr_we[1] = 1'b1; + lsu_pready = 1'b1; + end + end + end + end else begin + $fatal(1, "[snitch] Unsupported RegNrWritePorts."); + end + + // -------------------------- + // RISC-V Formal Interface + // -------------------------- + `ifdef RISCV_FORMAL + logic instr_addr_misaligned; + logic ld_addr_misaligned_q; + // check that the instruction is a control transfer instruction + assign instr_addr_misaligned = (inst_data_i inside { + riscv_instr::JAL, + riscv_instr::JALR, + riscv_instr::BEQ, + riscv_instr::BNE, + riscv_instr::BLT, + riscv_instr::BLTU, + riscv_instr::BGE, + riscv_instr::BGEU + }) && (pc_d[1:0] != 2'b0); + + + // retire an instruction and increase ordering bit + `FFLAR(rvfi_order[0], rvfi_order[0] + 1, rvfi_valid[0], '0, clk_i, rst_i) + + logic [31:0] ld_instr_q; + logic [31:0] ld_addr_q; + logic [4:0] rs1_q; + logic [31:0] rs1_data_q; + logic [31:0] pc_qq; + // we need to latch the load + `FFLAR(ld_instr_q, inst_data_i, latch_load, '0, clk_i, rst_i) + `FFLAR(ld_addr_q, data_qaddr_o, latch_load, '0, clk_i, rst_i) + `FFLAR(rs1_q, rs1, latch_load, '0, clk_i, rst_i) + `FFLAR(rs1_data_q, gpr_rdata[0], latch_load, '0, clk_i, rst_i) + `FFLAR(pc_qq, pc_d, latch_load, '0, clk_i, rst_i) + `FFLAR(ld_addr_misaligned_q, ld_addr_misaligned, latch_load, '0, clk_i, rst_i) + + // in case we don't retire another instruction on port 1 we can use it for loads + logic retire_load_port1; + + assign retire_load_port1 = retire_load & stall; + // NRET: 1 + assign rvfi_halt[0] = 1'b0; + assign rvfi_mode[0] = 2'b11; + assign rvfi_intr[0] = 1'b0; + assign rvfi_valid[0] = !stall | retire_load; + assign rvfi_insn[0] = retire_load_port1 ? ld_instr_q : (is_load ? '0 : inst_data_i); + assign rvfi_trap[0] = retire_load_port1 ? ld_addr_misaligned_q : illegal_inst + | instr_addr_misaligned + | st_addr_misaligned; + assign rvfi_rs1_addr[0] = (retire_load_port1) ? rs1_q : rs1; + assign rvfi_rs1_rdata[0] = (retire_load_port1) ? rs1_data_q : gpr_rdata[0]; + assign rvfi_rs2_addr[0] = (retire_load_port1) ? '0 : rs2; + assign rvfi_rs2_rdata[0] = (retire_load_port1) ? '0 : gpr_rdata[1]; + assign rvfi_rd_addr[0] = (retire_load_port1) ? lsu_rd : ((gpr_we[0] && write_rd) ? rd : '0); + assign rvfi_rd_wdata[0] = (retire_load_port1) ? (lsu_rd != 0 ? ld_result[31:0] : '0) : (rd != 0 && gpr_we[0] && write_rd) ? gpr_wdata[0] : 0; + assign rvfi_pc_rdata[0] = (retire_load_port1) ? pc_qq : pc_q; + assign rvfi_pc_wdata[0] = (retire_load_port1) ? (pc_qq + 4) : pc_d; + assign rvfi_mem_addr[0] = (retire_load_port1) ? ld_addr_q : data_qaddr_o; + assign rvfi_mem_wmask[0] = (retire_load_port1) ? '0 : ((data_qvalid_o && data_qready_i) ? data_qstrb_o[3:0] : '0); + assign rvfi_mem_rmask[0] = (retire_load_port1) ? 4'hf : '0; + assign rvfi_mem_rdata[0] = (retire_load_port1) ? data_pdata_i[31:0] : '0; + assign rvfi_mem_wdata[0] = (retire_load_port1) ? '0 : data_qdata_o[31:0]; + `endif + + // ---------- + // Assertions + // ---------- + // Make sure the instruction interface is stable. Otherwise, Snitch might violate the protocol at + // the LSU or accelerator interface by withdrawing the valid signal. + `ASSERT(InstructionInterfaceStable, + (inst_valid_o && inst_ready_i) ##1 (inst_valid_o && $stable(inst_addr_o)) + |-> inst_ready_i && $stable(inst_data_i), clk_i, rst_i) + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_axi_adapter.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_axi_adapter.sv new file mode 100644 index 0000000000..6d4cc8e2dd --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_axi_adapter.sv @@ -0,0 +1,221 @@ +// Copyright 2018-2019 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// File: axi_adapter.sv +// Author: Florian Zaruba +// Date: 1.8.2018 +// +// Description: Manages communication with the AXI Bus + +module snitch_axi_adapter #( + parameter int unsigned WriteFIFODepth = 2, + parameter int unsigned ReadFIFODepth = 2, + parameter type addr_t = logic, + parameter type data_t = logic, + parameter type strb_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + // AXI port + input axi_mst_resp_t axi_resp_i, + output axi_mst_req_t axi_req_o, + + input addr_t slv_qaddr_i, + input logic slv_qwrite_i, + input logic [3:0] slv_qamo_i, + input data_t slv_qdata_i, + input logic [2:0] slv_qsize_i, + input strb_t slv_qstrb_i, + input logic [7:0] slv_qrlen_i, + input logic slv_qvalid_i, + output logic slv_qready_o, + output data_t slv_pdata_o, + output logic slv_perror_o, + output logic slv_plast_o, + output logic slv_pvalid_o, + input logic slv_pready_i +); + + localparam DataWidth = $bits(data_t); + localparam StrbWidth = $bits(strb_t); + localparam SlvByteOffset = $clog2($bits(strb_t)); + localparam AxiByteOffset = $clog2($bits(axi_req_o.w.strb)); + + typedef enum logic [3:0] { + AMONone = 4'h0, + AMOSwap = 4'h1, + AMOAdd = 4'h2, + AMOAnd = 4'h3, + AMOOr = 4'h4, + AMOXor = 4'h5, + AMOMax = 4'h6, + AMOMaxu = 4'h7, + AMOMin = 4'h8, + AMOMinu = 4'h9, + AMOLR = 4'hA, + AMOSC = 4'hB + } amo_op_t; + + typedef struct packed { + data_t data; + strb_t strb; + } write_t; + + logic write_full; + logic write_empty; + logic read_full; + write_t write_data_in; + write_t write_data_out; + + assign axi_req_o.aw.addr = slv_qaddr_i; + assign axi_req_o.aw.prot = 3'b0; + assign axi_req_o.aw.region = 4'b0; + assign axi_req_o.aw.size = slv_qsize_i; + assign axi_req_o.aw.len = '0; + assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; + assign axi_req_o.aw.lock = 1'b0; + assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; + assign axi_req_o.aw.qos = 4'b0; + assign axi_req_o.aw.id = '0; + assign axi_req_o.aw.user = '0; + assign axi_req_o.aw_valid = ~write_full & slv_qvalid_i & slv_qwrite_i; + + always_comb begin + write_data_in.data = slv_qdata_i; + write_data_in.strb = slv_qstrb_i; + unique case (amo_op_t'(slv_qamo_i)) + // RISC-V atops have a load semantic + AMOSwap: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ATOMICSWAP}; + AMOAdd: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; + AMOAnd: begin + // in this case we need to invert the data to get a "CLR" + write_data_in.data = ~slv_qdata_i; + axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; + end + AMOOr: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; + AMOXor: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}; + AMOMax: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}; + AMOMaxu: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}; + AMOMin: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}; + AMOMinu: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}; + default: axi_req_o.aw.atop = '0; + endcase + end + + localparam int unsigned ShiftWidth = (SlvByteOffset == AxiByteOffset) ? 1 : AxiByteOffset - SlvByteOffset; + typedef logic [ShiftWidth-1:0] shift_t; + typedef struct packed { + write_t data; + shift_t shift; + } write_ext_t; + + if (SlvByteOffset == AxiByteOffset) begin : gen_w_data + // Write + fifo_v3 #( + .DEPTH ( WriteFIFODepth ), + .dtype ( write_t ) + ) i_fifo_w_data ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( write_full ), + .empty_o ( write_empty ), + .usage_o ( /* NC */ ), + .data_i ( write_data_in ), + .push_i ( slv_qvalid_i & slv_qready_o & slv_qwrite_i ), + .data_o ( write_data_out ), + .pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready ) + ); + assign axi_req_o.w.data = write_data_out.data; + assign axi_req_o.w.strb = write_data_out.strb; + + // Read + assign read_full = 1'b0; + assign slv_pdata_o = axi_resp_i.r.data; + end else begin : gen_w_data + // Write + write_ext_t write_data_ext_in, write_data_ext_out; + + fifo_v3 #( + .DEPTH ( WriteFIFODepth ), + .dtype ( write_ext_t ) + ) i_fifo_w_data ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( write_full ), + .empty_o ( write_empty ), + .usage_o ( /* NC */ ), + .data_i ( write_data_ext_in ), + .push_i ( slv_qvalid_i & slv_qready_o & slv_qwrite_i ), + .data_o ( write_data_ext_out ), + .pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready ) + ); + + assign write_data_ext_in.data = write_data_in; + assign write_data_ext_in.shift = slv_qaddr_i[AxiByteOffset-1:SlvByteOffset]; + assign axi_req_o.w.data = {'0, write_data_ext_out.data.data} << ($bits(data_t) * write_data_ext_out.shift); + assign axi_req_o.w.strb = {'0, write_data_ext_out.data.strb} << ($bits(strb_t) * write_data_ext_out.shift); + + // Read + shift_t read_shift; + + fifo_v3 #( + .DEPTH ( ReadFIFODepth ), + .DATA_WIDTH ( AxiByteOffset-SlvByteOffset ) + ) i_fifo_r_shift ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( read_full ), + .empty_o ( /* NC */ ), + .usage_o ( /* NC */ ), + .data_i ( slv_qaddr_i[AxiByteOffset-1:SlvByteOffset] ), + .push_i ( slv_qvalid_i & slv_qready_o & ~slv_qwrite_i ), + .data_o ( read_shift ), + .pop_i ( axi_resp_i.r_valid & slv_pready_i ) + ); + + assign slv_pdata_o = axi_resp_i.r.data >> ($bits(data_t) * read_shift); + end + assign axi_req_o.w.last = 1'b1; + assign axi_req_o.w.user = '0; + assign axi_req_o.w_valid = ~write_empty; + + assign axi_req_o.b_ready = 1'b1; + + assign axi_req_o.ar.addr = slv_qaddr_i; + assign axi_req_o.ar.prot = 3'b0; + assign axi_req_o.ar.region = 4'b0; + assign axi_req_o.ar.size = slv_qsize_i; + assign axi_req_o.ar.len = slv_qrlen_i; + assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; + assign axi_req_o.ar.lock = 1'b0; + assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE; + assign axi_req_o.ar.qos = 4'b0; + assign axi_req_o.ar.id = '0; + assign axi_req_o.ar.user = '0; + assign axi_req_o.ar_valid = ~read_full & slv_qvalid_i & ~slv_qwrite_i; + + assign slv_perror_o = (axi_resp_i.r.resp inside {axi_pkg::RESP_EXOKAY, axi_pkg::RESP_OKAY}) ? 1'b0 : 1'b1; + assign slv_plast_o = axi_resp_i.r.last; + assign slv_pvalid_o = axi_resp_i.r_valid; + assign axi_req_o.r_ready = slv_pready_i; + + assign slv_qready_o = (axi_resp_i.ar_ready & axi_req_o.ar_valid) + | (axi_resp_i.aw_ready & axi_req_o.aw_valid); + + `ifndef VERILATOR + // pragma translate_off + hot_one : assert property ( + @(posedge clk_i) disable iff (!rst_ni) (slv_qvalid_i & slv_qwrite_i & slv_qready_o) |-> (slv_qrlen_i == 0)) + else $warning("Bursts are not supported for write transactions"); + // pragma translate_on + `endif +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_demux.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_demux.sv new file mode 100644 index 0000000000..cff863e1cd --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_demux.sv @@ -0,0 +1,133 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/// Arbitrates request/response interface +/// Author: Florian Zaruba + +/// Demux based on arbitration +module snitch_demux #( + parameter int unsigned NrPorts = 4, + parameter type req_t = snitch_pkg::dreq_t, + parameter type resp_t = snitch_pkg::dresp_t, + parameter int unsigned RespDepth = 8, + parameter bit [NrPorts-1:0] RegisterReq = '0, + parameter Arbiter = "rr" // "rr" or "prio" +) ( + input logic clk_i, + input logic rst_ni, + // request port + input req_t [NrPorts-1:0] req_payload_i, + input logic [NrPorts-1:0] req_valid_i, + output logic [NrPorts-1:0] req_ready_o, + + output resp_t [NrPorts-1:0] resp_payload_o, + output logic [NrPorts-1:0] resp_last_o, + output logic [NrPorts-1:0] resp_valid_o, + input logic [NrPorts-1:0] resp_ready_i, + // response port + output req_t req_payload_o, + output logic req_valid_o, + input logic req_ready_i, + + input resp_t resp_payload_i, + input logic resp_last_i, + input logic resp_valid_i, + output logic resp_ready_o +); + + localparam LogNrPorts = (NrPorts > 1) ? $clog2(NrPorts) : 1; + + logic [NrPorts-1:0] req_valid_masked; + logic [NrPorts-1:0] req_ready_masked; + logic [LogNrPorts-1:0] idx, idx_rsp; + logic full; + + req_t [NrPorts-1:0] req_payload_q; + logic [NrPorts-1:0] req_valid_q; + logic [NrPorts-1:0] req_ready_q; + + // Cut the incoming path + for (genvar i = 0; i < NrPorts; i++) begin : gen_spill_regs + spill_register #( + .T ( req_t ), + .Bypass ( !RegisterReq[i] ) + ) i_spill_register_tcdm_req ( + .clk_i, + .rst_ni, + .valid_i ( req_valid_i [i] ), + .ready_o ( req_ready_o [i] ), + .data_i ( req_payload_i [i] ), + .valid_o ( req_valid_q [i] ), + .ready_i ( req_ready_masked [i] ), + .data_o ( req_payload_q [i] ) + ); + end + + for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked + assign req_valid_masked[i] = req_valid_q[i] & ~full; + assign req_ready_masked[i] = req_ready_q[i] & ~full; + end + + /// Arbitrate on instruction request port + stream_arbiter #( + .DATA_T ( req_t ), + .N_INP ( NrPorts ), + .ARBITER ( Arbiter ) + ) i_stream_arbiter_req ( + .clk_i, + .rst_ni, + .inp_data_i ( req_payload_q ), + .inp_valid_i ( req_valid_masked ), + .inp_ready_o ( req_ready_q ), + .oup_data_o ( req_payload_o ), + .oup_valid_o ( req_valid_o ), + .oup_ready_i ( req_ready_i ) + ); + + if (NrPorts == 1) begin + assign idx_rsp = 0; + assign full = 1'b0; + end else begin + onehot_to_bin #( + .ONEHOT_WIDTH ( NrPorts ) + ) i_onehot_to_bin ( + .onehot ( req_valid_q & req_ready_q ), + .bin ( idx ) + ); + + fifo_v3 #( + .DATA_WIDTH ( LogNrPorts ), + .DEPTH ( RespDepth ) + ) i_resp_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( full ), + .empty_o ( ), + .usage_o ( ), + .data_i ( idx ), + // only reads will generate a response message + .push_i ( req_valid_o & req_ready_i & ~req_payload_o.write ), + .data_o ( idx_rsp ), + .pop_i ( resp_ready_o & resp_valid_i & resp_last_i ) + ); + end + + stream_demux #( + .N_OUP ( NrPorts ) + ) i_stream_demux_resp ( + .inp_valid_i ( resp_valid_i ), + .inp_ready_o ( resp_ready_o ), + .oup_sel_i ( idx_rsp ), + .oup_valid_o ( resp_valid_o ), + .oup_ready_i ( resp_ready_i ) + ); + + for (genvar i = 0; i < NrPorts; i++) begin + assign resp_payload_o[i] = resp_payload_i; + assign resp_last_o[i] = resp_last_i; + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache.sv new file mode 100644 index 0000000000..870a3e9268 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache.sv @@ -0,0 +1,721 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki +// Florian Zaruba + +`include "common_cells/registers.svh" + +module snitch_icache #( + /// Number of request (fetch) ports + parameter int NR_FETCH_PORTS = -1, + /// L0 Cache Line Count + parameter int L0_LINE_COUNT = -1, + /// Cache Line Width + parameter int LINE_WIDTH = -1, + /// The number of cache lines per set. Power of two; >= 2. + parameter int LINE_COUNT = -1, + /// The set associativity of the cache. Power of two; >= 1. + parameter int SET_COUNT = 1, + /// Fetch interface address width. Same as FILL_AW; >= 1. + parameter int FETCH_AW = -1, + /// Fetch interface data width. Power of two; >= 8. + parameter int FETCH_DW = -1, + /// Fill interface address width. Same as FETCH_AW; >= 1. + parameter int FILL_AW = -1, + /// Fill interface data width. Power of two; >= 8. + parameter int FILL_DW = -1, + /// Replace the L1 tag banks with latch-based SCM. + parameter bit L1_TAG_SCM = 0, + /// This reduces area impact at the cost of + /// increased hassle of having latches in + /// the design. + /// i_snitch_icache/gen_prefetcher*i_snitch_icache_l0/data*/Q + parameter bit EARLY_LATCH = 0, + /// Tag width of the data determining logic, this can reduce the + /// the critical path into the L0 cache when small. The trade-off + /// is a higher miss-rate in case the smaller tag matches more + /// tags. The tag must be smaller than the necessary L0 tag. + /// If configured to `-1` the entire tag is used, effectively + /// disabling this feature. + parameter int L0_EARLY_TAG_WIDTH = -1, + /// Operate L0 cache in slower clock-domain + parameter bit ISO_CROSSING = 1 +) ( + input logic clk_i, + input logic clk_d2_i, + input logic rst_ni, + + input logic [NR_FETCH_PORTS-1:0] enable_prefetching_i, + output snitch_icache_pkg::icache_events_t [NR_FETCH_PORTS-1:0] icache_events_o, + + input logic flush_valid_i, + output logic flush_ready_o, + + input logic [NR_FETCH_PORTS-1:0][FETCH_AW-1:0] inst_addr_i, + output logic [NR_FETCH_PORTS-1:0][FETCH_DW-1:0] inst_data_o, + input logic [NR_FETCH_PORTS-1:0] inst_cacheable_i, + input logic [NR_FETCH_PORTS-1:0] inst_valid_i, + output logic [NR_FETCH_PORTS-1:0] inst_ready_o, + output logic [NR_FETCH_PORTS-1:0] inst_error_o, + // AXI-like read-only interface + output logic [FILL_AW-1:0] refill_qaddr_o, + output logic [7:0] refill_qlen_o, + output logic refill_qvalid_o, + input logic refill_qready_i, + + input logic [FILL_DW-1:0] refill_pdata_i, + input logic refill_perror_i, + input logic refill_pvalid_i, + input logic refill_plast_i, + output logic refill_pready_o +); + + // Bundle the parameters up into a proper configuration struct that we can + // pass to submodules. + localparam PENDING_COUNT = 8; + localparam snitch_icache_pkg::config_t CFG = '{ + NR_FETCH_PORTS: NR_FETCH_PORTS, + LINE_WIDTH: LINE_WIDTH, + LINE_COUNT: LINE_COUNT, + L0_LINE_COUNT: L0_LINE_COUNT, + SET_COUNT: SET_COUNT, + PENDING_COUNT: PENDING_COUNT, + FETCH_AW: FETCH_AW, + FETCH_DW: FETCH_DW, + FILL_AW: FILL_AW, + FILL_DW: FILL_DW, + L1_TAG_SCM: L1_TAG_SCM, + EARLY_LATCH: EARLY_LATCH, + + FETCH_ALIGN: $clog2(FETCH_DW/8), + FILL_ALIGN: $clog2(FILL_DW/8), + LINE_ALIGN: $clog2(LINE_WIDTH/8), + COUNT_ALIGN: $clog2(LINE_COUNT), + SET_ALIGN: $clog2(SET_COUNT), + TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8) - $clog2(LINE_COUNT) + 1, + L0_TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8), + L0_EARLY_TAG_WIDTH: (L0_EARLY_TAG_WIDTH == -1) ? FETCH_AW - $clog2(LINE_WIDTH/8) : L0_EARLY_TAG_WIDTH, + ID_WIDTH_REQ: $clog2(NR_FETCH_PORTS) + 1, + ID_WIDTH_RESP: 2*NR_FETCH_PORTS, + PENDING_IW: $clog2(PENDING_COUNT) + }; + + // pragma translate_off + `ifndef VERILATOR + // Check invariants. + initial begin + assert(L0_LINE_COUNT > 0); + assert(LINE_WIDTH > 0); + assert(LINE_COUNT > 1); + assert(SET_COUNT >= 2) else $warning("Only >= 2 sets are supported"); + assert(FETCH_AW > 0); + assert(FETCH_DW > 0); + assert(FILL_AW > 0); + assert(FILL_DW > 0); + assert(CFG.L0_EARLY_TAG_WIDTH < CFG.L0_TAG_WIDTH); + assert(FETCH_AW == FILL_AW); + assert(2**$clog2(LINE_WIDTH) == LINE_WIDTH); + assert(2**$clog2(LINE_COUNT) == LINE_COUNT); + assert(2**$clog2(SET_COUNT) == SET_COUNT); + assert(2**$clog2(FETCH_DW) == FETCH_DW); + assert(2**$clog2(FILL_DW) == FILL_DW); + end + `endif + // pragma translate_on + + // Instantiate the optional early cache, or bypass it. + logic [NR_FETCH_PORTS-1:0][FETCH_AW-1:0] early_addr; + logic [NR_FETCH_PORTS-1:0][LINE_WIDTH-1:0] early_data; + logic [NR_FETCH_PORTS-1:0] early_valid; + logic [NR_FETCH_PORTS-1:0] early_ready; + logic [NR_FETCH_PORTS-1:0] early_error; + + // The prefetch module is responsible for taking the 1-channel valid/ready + // transaction from the early cache and translate it into a 2-channel + // transaction. Once the actual incoming request has been accepted on the + // `req` channel, the prefetcher issues another low-priority request for the + // next cache line. + typedef struct packed { + logic [CFG.FETCH_AW-1:0] addr; + logic [CFG.ID_WIDTH_REQ-1:0] id; + } prefetch_req_t; + + typedef struct packed { + logic [CFG.LINE_WIDTH-1:0] data; + logic error; + logic [CFG.ID_WIDTH_RESP-1:0] id; + } prefetch_resp_t; + + prefetch_req_t [NR_FETCH_PORTS-1:0] prefetch_req ; + logic [NR_FETCH_PORTS-1:0] prefetch_req_valid ; + logic [NR_FETCH_PORTS-1:0] prefetch_req_ready ; + + prefetch_req_t prefetch_lookup_req ; + logic prefetch_lookup_req_valid ; + logic prefetch_lookup_req_ready ; + + prefetch_resp_t [NR_FETCH_PORTS-1:0] prefetch_rsp ; + logic [NR_FETCH_PORTS-1:0] prefetch_rsp_valid ; + logic [NR_FETCH_PORTS-1:0] prefetch_rsp_ready ; + + prefetch_resp_t prefetch_lookup_rsp ; + logic prefetch_lookup_rsp_valid ; + logic prefetch_lookup_rsp_ready ; + + typedef struct packed { + logic [CFG.FETCH_AW-1:0] addr; + logic [CFG.PENDING_IW-1:0] id; + logic bypass; + } miss_refill_req_t; + miss_refill_req_t handler_req, bypass_req, bypass_req_q, refill_req; + logic handler_req_valid, bypass_req_valid, bypass_req_valid_q, refill_req_valid; + logic handler_req_ready, bypass_req_ready, bypass_req_ready_q, refill_req_ready; + + typedef struct packed { + logic [CFG.LINE_WIDTH-1:0] data; + logic error; + logic [CFG.PENDING_IW-1:0] id; + logic bypass; + } miss_refill_rsp_t; + miss_refill_rsp_t handler_rsp, bypass_rsp, bypass_rsp_q, refill_rsp; + logic handler_rsp_valid, bypass_rsp_valid, bypass_rsp_valid_q, refill_rsp_valid; + logic handler_rsp_ready, bypass_rsp_ready, bypass_rsp_ready_q, refill_rsp_ready; + + logic [NR_FETCH_PORTS-1:0][FETCH_DW-1:0] bypass_data; + logic [NR_FETCH_PORTS-1:0] bypass_error; + logic [NR_FETCH_PORTS-1:0] bypass_valid; + logic [NR_FETCH_PORTS-1:0] bypass_ready; + logic [NR_FETCH_PORTS-1:0][FETCH_AW-1:0] bypass_addr; + + // logic [NR_FETCH_PORTS-1:0] + logic [NR_FETCH_PORTS-1:0] in_cache_valid, in_bypass_valid; + logic [NR_FETCH_PORTS-1:0] in_cache_ready, in_bypass_ready; + logic [NR_FETCH_PORTS-1:0] [FETCH_DW-1:0] in_cache_data, in_bypass_data; + logic [NR_FETCH_PORTS-1:0] in_cache_error, in_bypass_error; + for (genvar i = 0; i < NR_FETCH_PORTS; i++) begin : gen_prefetcher + prefetch_req_t local_prefetch_req; + logic local_prefetch_req_valid; + logic local_prefetch_req_ready; + prefetch_resp_t local_prefetch_rsp; + logic local_prefetch_rsp_valid; + logic local_prefetch_rsp_ready; + + assign in_cache_valid[i] = inst_cacheable_i[i] & inst_valid_i[i]; + assign in_bypass_valid[i] = ~inst_cacheable_i[i] & inst_valid_i[i]; + assign inst_ready_o[i] = (inst_cacheable_i[i] & in_cache_ready [i]) | (~inst_cacheable_i[i] & in_bypass_ready [i]); + // multiplex results + assign {inst_error_o[i], inst_data_o[i]} = ({($bits(in_cache_data[i])+1){inst_cacheable_i[i]}} & {in_cache_error [i], in_cache_data[i]}) + | (~{($bits(in_cache_data[i])+1){inst_cacheable_i[i]}} & {in_bypass_error[i], in_bypass_data[i]}); + + snitch_icache_l0 #( + .CFG ( CFG ), + .L0_ID ( i ) + ) i_snitch_icache_l0 ( + .clk_i ( clk_d2_i ), + .rst_ni, + .flush_valid_i, + .enable_prefetching_i ( enable_prefetching_i [i] ), + .icache_events_o ( icache_events_o [i] ), + .in_addr_i ( inst_addr_i [i] ), + .in_data_o ( in_cache_data [i] ), + .in_error_o ( in_cache_error [i] ), + .in_valid_i ( in_cache_valid [i] ), + .in_ready_o ( in_cache_ready [i] ), + + .out_req_addr_o ( local_prefetch_req.addr ), + .out_req_id_o ( local_prefetch_req.id ), + .out_req_valid_o ( local_prefetch_req_valid ), + .out_req_ready_i ( local_prefetch_req_ready ), + + .out_rsp_data_i ( local_prefetch_rsp.data ), + .out_rsp_error_i ( local_prefetch_rsp.error ), + .out_rsp_id_i ( local_prefetch_rsp.id ), + .out_rsp_valid_i ( local_prefetch_rsp_valid ), + .out_rsp_ready_o ( local_prefetch_rsp_ready ) + ); + + isochronous_spill_register #( + .T ( prefetch_req_t ), + .Bypass ( !ISO_CROSSING ) + ) i_spill_register_prefetch_req ( + .src_clk_i ( clk_d2_i ), + .src_rst_ni ( rst_ni ), + .src_valid_i ( local_prefetch_req_valid ), + .src_ready_o ( local_prefetch_req_ready ), + .src_data_i ( local_prefetch_req ), + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_valid_o ( prefetch_req_valid [i] ), + .dst_ready_i ( prefetch_req_ready [i] ), + .dst_data_o ( prefetch_req [i] ) + ); + + isochronous_spill_register #( + .T ( prefetch_resp_t ), + .Bypass ( !ISO_CROSSING ) + ) i_spill_register_prefetch_resp ( + .src_clk_i ( clk_i ), + .src_rst_ni ( rst_ni ), + .src_valid_i ( prefetch_rsp_valid [i] ), + .src_ready_o ( prefetch_rsp_ready [i] ), + .src_data_i ( prefetch_rsp [i] ), + .dst_clk_i ( clk_d2_i ), + .dst_rst_ni ( rst_ni ), + .dst_valid_o ( local_prefetch_rsp_valid ), + .dst_ready_i ( local_prefetch_rsp_ready ), + .dst_data_o ( local_prefetch_rsp ) + ); + + end + + l0_to_bypass #( + .CFG ( CFG ) + ) i_l0_to_bypass ( + .clk_i ( clk_d2_i ), + .rst_ni, + + .in_valid_i ( in_bypass_valid ), + .in_ready_o ( in_bypass_ready ), + .in_addr_i ( inst_addr_i ), + .in_data_o ( in_bypass_data ), + .in_error_o ( in_bypass_error ), + + .refill_req_addr_o ( bypass_req.addr ), + .refill_req_bypass_o ( bypass_req.bypass ), + .refill_req_valid_o ( bypass_req_valid ), + .refill_req_ready_i ( bypass_req_ready ), + + .refill_rsp_data_i ( bypass_rsp_q.data ), + .refill_rsp_error_i ( bypass_rsp_q.error ), + .refill_rsp_valid_i ( bypass_rsp_valid_q ), + .refill_rsp_ready_o ( bypass_rsp_ready_q ) + ); + + assign bypass_req.id = '0; + + isochronous_spill_register #( + .T ( miss_refill_req_t ), + .Bypass ( !ISO_CROSSING ) + ) i_spill_register_bypass_req ( + .src_clk_i ( clk_d2_i ), + .src_rst_ni ( rst_ni ), + .src_valid_i ( bypass_req_valid ), + .src_ready_o ( bypass_req_ready ), + .src_data_i ( bypass_req ), + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_valid_o ( bypass_req_valid_q ), + .dst_ready_i ( bypass_req_ready_q ), + .dst_data_o ( bypass_req_q ) + ); + + isochronous_spill_register #( + .T ( miss_refill_rsp_t ), + .Bypass ( !ISO_CROSSING ) + ) i_spill_register_bypass_resp ( + .src_clk_i ( clk_i ), + .src_rst_ni ( rst_ni ), + .src_valid_i ( bypass_rsp_valid ), + .src_ready_o ( bypass_rsp_ready ), + .src_data_i ( bypass_rsp ), + .dst_clk_i ( clk_d2_i ), + .dst_rst_ni ( rst_ni ), + .dst_valid_o ( bypass_rsp_valid_q ), + .dst_ready_i ( bypass_rsp_ready_q ), + .dst_data_o ( bypass_rsp_q ) + ); + + /// Arbitrate cache port + // 1. Request Side + stream_arbiter #( + .DATA_T ( prefetch_req_t ), + .N_INP ( NR_FETCH_PORTS ) + ) i_stream_arbiter ( + .clk_i, + .rst_ni, + .inp_data_i ( prefetch_req ), + .inp_valid_i ( prefetch_req_valid ), + .inp_ready_o ( prefetch_req_ready ), + .oup_data_o ( prefetch_lookup_req ), + .oup_valid_o ( prefetch_lookup_req_valid ), + .oup_ready_i ( prefetch_lookup_req_ready ) + ); + + // 2. Response Side + // This breaks if the pre-fetcher would not alway be ready + // which is the case for the moment + for (genvar i = 0; i < NR_FETCH_PORTS; i++) begin : gen_resp + assign prefetch_rsp[i] = prefetch_lookup_rsp; + // check if one of the ID bits is set + assign prefetch_rsp_valid[i] = ((|((prefetch_rsp[i].id >> 2*i) & 2'b11)) & prefetch_lookup_rsp_valid); + end + assign prefetch_lookup_rsp_ready = |prefetch_rsp_ready; + + /// Tag lookup + + // The lookup module contains the actual cache RAMs and performs lookups. + logic [CFG.FETCH_AW-1:0] lookup_addr ; + logic [CFG.ID_WIDTH_REQ-1:0] lookup_id ; + logic [CFG.SET_ALIGN-1:0] lookup_set ; + logic lookup_hit ; + logic [CFG.LINE_WIDTH-1:0] lookup_data ; + logic lookup_error ; + logic lookup_valid ; + logic lookup_ready ; + + logic [CFG.COUNT_ALIGN-1:0] write_addr ; + logic [CFG.SET_ALIGN-1:0] write_set ; + logic [CFG.LINE_WIDTH-1:0] write_data ; + logic [CFG.TAG_WIDTH-1:0] write_tag ; + logic write_error ; + logic write_valid ; + logic write_ready ; + + logic flush_valid, flush_ready; + + // We need to propagate the handshake into the other + // clock domain in case we operate w/ different clocks. + if (ISO_CROSSING) begin : gen_flush_crossing + isochronous_spill_register + i_isochronous_4phase_handshake ( + .src_clk_i ( clk_d2_i ), + .src_rst_ni ( rst_ni ), + .src_valid_i ( flush_valid_i ), + .src_ready_o ( flush_ready_o ), + .src_data_i ( '0 ), + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_valid_o ( flush_valid ), + .dst_ready_i ( flush_ready ), + .dst_data_o ( /* Unused */ ) + ); + end else begin : gen_no_flush_crossing + assign flush_valid = flush_valid_i; + assign flush_ready_o = flush_ready; + end + + snitch_icache_lookup #(CFG) i_lookup ( + .clk_i, + .rst_ni, + + .flush_valid_i (flush_valid), + .flush_ready_o (flush_ready), + + .in_addr_i ( prefetch_lookup_req.addr ), + .in_id_i ( prefetch_lookup_req.id ), + .in_valid_i ( prefetch_lookup_req_valid ), + .in_ready_o ( prefetch_lookup_req_ready ), + + .out_addr_o ( lookup_addr ), + .out_id_o ( lookup_id ), + .out_set_o ( lookup_set ), + .out_hit_o ( lookup_hit ), + .out_data_o ( lookup_data ), + .out_error_o ( lookup_error ), + .out_valid_o ( lookup_valid ), + .out_ready_i ( lookup_ready ), + + .write_addr_i ( write_addr ), + .write_set_i ( write_set ), + .write_data_i ( write_data ), + .write_tag_i ( write_tag ), + .write_error_i ( write_error ), + .write_valid_i ( write_valid ), + .write_ready_o ( write_ready ) + ); + + // The miss handler module deals with the result of the lookup. It also + // keeps track of the pending refills and ensures that no redundant memory + // requests are made. Upon refill completion, it sends a new tag/data item + // to the lookup module and the received data to the prefetch module. + snitch_icache_handler #(CFG) i_handler ( + .clk_i, + .rst_ni, + + .in_req_addr_i ( lookup_addr ), + .in_req_id_i ( lookup_id ), + .in_req_set_i ( lookup_set ), + .in_req_hit_i ( lookup_hit ), + .in_req_data_i ( lookup_data ), + .in_req_error_i ( lookup_error ), + .in_req_valid_i ( lookup_valid ), + .in_req_ready_o ( lookup_ready ), + + .in_rsp_data_o ( prefetch_lookup_rsp.data ), + .in_rsp_error_o ( prefetch_lookup_rsp.error ), + .in_rsp_id_o ( prefetch_lookup_rsp.id ), + .in_rsp_valid_o ( prefetch_lookup_rsp_valid ), + .in_rsp_ready_i ( prefetch_lookup_rsp_ready ), + + .write_addr_o ( write_addr ), + .write_set_o ( write_set ), + .write_data_o ( write_data ), + .write_tag_o ( write_tag ), + .write_error_o ( write_error ), + .write_valid_o ( write_valid ), + .write_ready_i ( write_ready ), + + .out_req_addr_o ( handler_req.addr ), + .out_req_id_o ( handler_req.id ), + .out_req_valid_o ( handler_req_valid ), + .out_req_ready_i ( handler_req_ready ), + + .out_rsp_data_i ( handler_rsp.data ), + .out_rsp_error_i ( handler_rsp.error ), + .out_rsp_id_i ( handler_rsp.id ), + .out_rsp_valid_i ( handler_rsp_valid ), + .out_rsp_ready_o ( handler_rsp_ready ) + ); + assign handler_req.bypass = 1'b0; + // Arbitrate between bypass and cache-refills + stream_arbiter #( + .DATA_T ( miss_refill_req_t ), + .N_INP ( 2 ) + ) i_stream_arbiter_miss_refill ( + .clk_i, + .rst_ni, + .inp_data_i ( {bypass_req_q, handler_req} ), + .inp_valid_i ( {bypass_req_valid_q, handler_req_valid} ), + .inp_ready_o ( {bypass_req_ready_q, handler_req_ready} ), + .oup_data_o ( refill_req ), + .oup_valid_o ( refill_req_valid ), + .oup_ready_i ( refill_req_ready ) + ); + // Response path muxing + stream_demux #( + .N_OUP ( 2 ) + ) i_stream_demux_miss_refill ( + .inp_valid_i ( refill_rsp_valid ), + .inp_ready_o ( refill_rsp_ready ), + + .oup_sel_i ( refill_rsp.bypass ), + + .oup_valid_o ( {{bypass_rsp_valid, handler_rsp_valid}} ), + .oup_ready_i ( {{bypass_rsp_ready, handler_rsp_ready}} ) + ); + + assign handler_rsp = refill_rsp; + assign bypass_rsp = refill_rsp; + + // AXI-like read-only interface + typedef struct packed { + logic [FILL_AW-1:0] addr; + logic [7:0] len; + } extern_req_t; + + typedef struct packed { + logic [FILL_DW-1:0] data; + logic error; + logic last; + } extern_rsp_t; + + extern_req_t extern_req, extern_req_q; + logic extern_qvalid; + logic extern_qready; + + extern_rsp_t extern_rsp, extern_rsp_q; + logic extern_pvalid_q; + logic extern_pready_q; + + // Instantiate the cache refill module which emits AXI transactions. + snitch_icache_refill #(CFG) i_refill ( + .clk_i, + .rst_ni, + + .in_req_addr_i ( refill_req.addr ), + .in_req_id_i ( refill_req.id ), + .in_req_bypass_i ( refill_req.bypass ), + .in_req_valid_i ( refill_req_valid ), + .in_req_ready_o ( refill_req_ready ), + + .in_rsp_data_o ( refill_rsp.data ), + .in_rsp_error_o ( refill_rsp.error ), + .in_rsp_id_o ( refill_rsp.id ), + .in_rsp_bypass_o ( refill_rsp.bypass ), + .in_rsp_valid_o ( refill_rsp_valid ), + .in_rsp_ready_i ( refill_rsp_ready ), + + .refill_qaddr_o ( extern_req.addr ), + .refill_qlen_o ( extern_req.len ), + .refill_qvalid_o ( extern_qvalid ), + .refill_qready_i ( extern_qready ), + .refill_pdata_i ( extern_rsp_q.data ), + .refill_perror_i ( extern_rsp_q.error ), + .refill_plast_i ( extern_rsp_q.last ), + .refill_pvalid_i ( extern_pvalid_q ), + .refill_pready_o ( extern_pready_q ) + ); + + // Insert Slices. + spill_register #(.T(extern_req_t)) i_spill_register_req ( + .clk_i, + .rst_ni, + .valid_i ( extern_qvalid ), + .ready_o ( extern_qready ), + .data_i ( extern_req ), + // Q Output + .valid_o ( refill_qvalid_o ), + .ready_i ( refill_qready_i ), + .data_o ( extern_req_q ) + ); + + assign refill_qaddr_o = extern_req_q.addr; + assign refill_qlen_o = extern_req_q.len; + + spill_register #(.T(extern_rsp_t)) i_spill_register_resp ( + .clk_i, + .rst_ni, + .valid_i ( refill_pvalid_i ), + .ready_o ( refill_pready_o ), + .data_i ( extern_rsp ), + // Q Output + .valid_o ( extern_pvalid_q ), + .ready_i ( extern_pready_q ), + .data_o ( extern_rsp_q ) + ); + + assign extern_rsp.data = refill_pdata_i; + assign extern_rsp.error = refill_perror_i; + assign extern_rsp.last = refill_plast_i; +endmodule + +// Translate register interface to refill requests. +// Used for bypassable accesses. +module l0_to_bypass #( + parameter snitch_icache_pkg::config_t CFG = '0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [CFG.NR_FETCH_PORTS-1:0] in_valid_i, + output logic [CFG.NR_FETCH_PORTS-1:0] in_ready_o, + input logic [CFG.NR_FETCH_PORTS-1:0][CFG.FETCH_AW-1:0] in_addr_i, + output logic [CFG.NR_FETCH_PORTS-1:0][CFG.FETCH_DW-1:0] in_data_o, + output logic [CFG.NR_FETCH_PORTS-1:0] in_error_o, + + output logic [CFG.FETCH_AW-1:0] refill_req_addr_o, + output logic refill_req_bypass_o, + output logic refill_req_valid_o, + input logic refill_req_ready_i, + + input logic [CFG.LINE_WIDTH-1:0] refill_rsp_data_i, + input logic refill_rsp_error_i, + input logic refill_rsp_valid_i, + output logic refill_rsp_ready_o +); + + assign refill_req_bypass_o = 1'b1; + + logic [CFG.NR_FETCH_PORTS-1:0] in_valid; + logic [CFG.NR_FETCH_PORTS-1:0] in_ready; + + enum logic [1:0] { + Idle, RequestData, WaitResponse, PresentResponse + } state_d [CFG.NR_FETCH_PORTS-1:0], state_q [CFG.NR_FETCH_PORTS-1:0]; + + // Mask address so that it is aligned to the cache-line width. + logic [CFG.NR_FETCH_PORTS-1:0][CFG.FETCH_AW-1:0] in_addr_masked; + for (genvar i = 0; i < CFG.NR_FETCH_PORTS; i++) begin + assign in_addr_masked[i] = in_addr_i[i] >> CFG.LINE_ALIGN << CFG.LINE_ALIGN; + end + stream_arbiter #( + .DATA_T ( logic [CFG.FETCH_AW-1:0] ), + .N_INP ( CFG.NR_FETCH_PORTS ) + ) i_stream_arbiter ( + .clk_i, + .rst_ni, + .inp_data_i ( in_addr_masked ), + .inp_valid_i ( in_valid ), + .inp_ready_o ( in_ready ), + .oup_data_o ( refill_req_addr_o ), + .oup_valid_o ( refill_req_valid_o ), + .oup_ready_i ( refill_req_ready_i ) + ); + + localparam int unsigned NR_FETCH_PORTS_BIN = CFG.NR_FETCH_PORTS == 1 ? 1 : $clog2(CFG.NR_FETCH_PORTS); + + logic [CFG.NR_FETCH_PORTS-1:0] rsp_fifo_mux; + logic [NR_FETCH_PORTS_BIN-1:0] onehot_mux; + logic [CFG.NR_FETCH_PORTS-1:0] rsp_fifo_pop; + logic rsp_fifo_full; + + logic [CFG.NR_FETCH_PORTS-1:0] rsp_valid; + logic [CFG.NR_FETCH_PORTS-1:0] rsp_ready; + + fifo_v3 #( + .DATA_WIDTH ( CFG.NR_FETCH_PORTS ), + .DEPTH ( 4 ) + ) rsp_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( rsp_fifo_full ), + .empty_o ( ), + .usage_o ( ), + .data_i ( {in_valid & in_ready} ), + .push_i ( |{in_valid & in_ready}), + .data_o ( rsp_fifo_mux ), + .pop_i ( |rsp_fifo_pop ) + ); + + + onehot_to_bin #( + .ONEHOT_WIDTH (CFG.NR_FETCH_PORTS) + ) i_onehot_to_bin ( + .onehot (rsp_fifo_mux), + .bin (onehot_mux) + ); + + assign rsp_ready = '1; + + stream_demux #( + .N_OUP ( CFG.NR_FETCH_PORTS ) + ) i_stream_mux_miss_refill ( + .inp_valid_i ( refill_rsp_valid_i ), + .inp_ready_o ( refill_rsp_ready_o ), + .oup_sel_i ( onehot_mux ), + .oup_valid_o ( rsp_valid ), + .oup_ready_i ( rsp_ready ) + ); + + for (genvar i = 0; i < CFG.NR_FETCH_PORTS; i++) begin : gen_bypass_request + always_comb begin + state_d[i] = state_q[i]; + in_ready_o[i] = 1'b0; + rsp_fifo_pop[i] = 1'b0; + in_valid[i] = 1'b0; + unique case (state_q[i]) + // latch data when idle + Idle: if (in_valid_i[i]) state_d[i] = RequestData; + RequestData: begin + // check that there is still space for the response to be accepted. + if (!rsp_fifo_full) begin + in_valid[i] = 1'b1; + if (in_ready[i]) state_d[i] = WaitResponse; + end + end + WaitResponse: begin + if (rsp_valid[i]) begin + rsp_fifo_pop[i] = 1'b1; + state_d[i] = PresentResponse; + end + end + // The response will be served from the register and is valid for one cycle. + PresentResponse: begin + state_d[i] = Idle; + in_ready_o[i] = 1'b1; + end + default:; + endcase + end + logic [CFG.FILL_DW-1:0] fill_rsp_data; + assign fill_rsp_data = refill_rsp_data_i >> (in_addr_i[i][CFG.LINE_ALIGN-1:CFG.FETCH_ALIGN] * CFG.FETCH_DW); + `FFLNR({in_data_o[i], in_error_o[i]}, {fill_rsp_data[CFG.FETCH_DW-1:0], refill_rsp_error_i}, rsp_valid[i], clk_i) + end + + `FF(state_q, state_d, '{default: Idle}) + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv new file mode 100644 index 0000000000..b0b75ded21 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv @@ -0,0 +1,314 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki + +module snitch_icache_handler #( + parameter snitch_icache_pkg::config_t CFG = '0 +)( + input logic clk_i, + input logic rst_ni, + + input logic [CFG.FETCH_AW-1:0] in_req_addr_i, + input logic [CFG.ID_WIDTH_REQ-1:0] in_req_id_i, + input logic [CFG.SET_ALIGN-1:0] in_req_set_i, + input logic in_req_hit_i, + input logic [CFG.LINE_WIDTH-1:0] in_req_data_i, + input logic in_req_error_i, + input logic in_req_valid_i, + output logic in_req_ready_o, + + output logic [CFG.LINE_WIDTH-1:0] in_rsp_data_o, + output logic in_rsp_error_o, + output logic [CFG.ID_WIDTH_RESP-1:0] in_rsp_id_o, + output logic in_rsp_valid_o, + input logic in_rsp_ready_i, + + output logic [CFG.COUNT_ALIGN-1:0] write_addr_o, + output logic [CFG.SET_ALIGN-1:0] write_set_o, + output logic [CFG.LINE_WIDTH-1:0] write_data_o, + output logic [CFG.TAG_WIDTH-1:0] write_tag_o, + output logic write_error_o, + output logic write_valid_o, + input logic write_ready_i, + + output logic [CFG.FETCH_AW-1:0] out_req_addr_o, + output logic [CFG.PENDING_IW-1:0] out_req_id_o, + output logic out_req_valid_o, + input logic out_req_ready_i, + + input logic [CFG.LINE_WIDTH-1:0] out_rsp_data_i, + input logic out_rsp_error_i, + input logic [CFG.PENDING_IW-1:0] out_rsp_id_i, + input logic out_rsp_valid_i, + output logic out_rsp_ready_o +); + + `ifndef SYNTHESIS + initial assert(CFG != '0); + `endif + + // The table of pending refills holds the metadata of all refills that are + // currently in flight. The table has a push and a pop interfaces. The push + // interface is used to mark entries as valid and update the mask of request + // IDs that the refill will serve. The pop interface is used to read a value + // from the table and clear its valid flag. + typedef struct packed { + logic valid; + logic [CFG.FETCH_AW-1:0] addr; + logic [CFG.ID_WIDTH_RESP-1:0] idmask; // mask of incoming ids + } pending_t; + pending_t pending_q [CFG.PENDING_COUNT]; + logic [CFG.PENDING_COUNT-1:0] pending_clr; + logic [CFG.PENDING_COUNT-1:0] pending_set; + + logic [CFG.PENDING_IW-1:0] push_index; + logic push_init; // reset the idmask instead of or'ing + logic [CFG.FETCH_AW-1:0] push_addr; + logic [CFG.ID_WIDTH_RESP-1:0] push_idmask; + logic push_enable; + + logic [CFG.PENDING_IW-1:0] pop_index; + logic [CFG.FETCH_AW-1:0] pop_addr; + logic [CFG.ID_WIDTH_RESP-1:0] pop_idmask; + logic pop_enable; + + for (genvar i = 0; i < CFG.PENDING_COUNT; i++) begin : g_pending_row + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + pending_q[i].valid <= 0; + else if (pending_set[i] || pending_clr[i]) + pending_q[i].valid <= pending_set[i] && ~pending_clr[i]; + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + pending_q[i].addr <= '0; + pending_q[i].idmask <= '0; + end else if (pending_set[i]) begin + pending_q[i].addr <= push_addr; + pending_q[i].idmask <= push_init ? push_idmask : push_idmask | pending_q[i].idmask; + end + end + end + + // The bypass logic ensures that if a table entry is pushed and popped at + // the same time, the pop is updated with the push information and the push + // discarded. + always_comb begin : p_pushpop_bypass + pending_set = push_enable ? 'b1 << push_index : '0; + pending_clr = pop_enable ? 'b1 << pop_index : '0; + pop_addr = pending_q[pop_index].addr; + pop_idmask = pending_q[pop_index].idmask; + if (push_enable && pop_enable && push_index == pop_index) begin + pop_addr = push_addr; + pop_idmask |= push_idmask; + end + end + + // Determine the first available entry in the pending table, if any is free. + logic [CFG.PENDING_COUNT-1:0] free_entries; + logic free; + logic [CFG.PENDING_IW-1:0] free_id; + + always_comb begin : p_free_id + for (int i = 0; i < CFG.PENDING_COUNT; i++) + free_entries[i] = ~pending_q[i].valid; + free = |free_entries; + end + + lzc #(.WIDTH(CFG.PENDING_COUNT)) i_lzc_free ( + .in_i ( free_entries ), + .cnt_o ( free_id ), + .empty_o ( ) + ); + + // Determine if the address of the incoming request coincides with any of + // the entries in the pending table. + logic [CFG.PENDING_COUNT-1:0] pending_matches; + logic pending; + logic [CFG.PENDING_IW-1:0] pending_id; + + always_comb begin : p_pending_id + for (int i = 0; i < CFG.PENDING_COUNT; i++) + pending_matches[i] = pending_q[i].valid && pending_q[i].addr == in_req_addr_i; + pending = |pending_matches; + end + + lzc #(.WIDTH(CFG.PENDING_COUNT)) i_lzc_pending ( + .in_i ( pending_matches ), + .cnt_o ( pending_id ), + .empty_o ( ) + ); + + // The miss handler checks if the access into the cache was a hit. If yes, + // the data is forwarded to the response handler. Otherwise the table of + // pending refills is consulted to check if any refills are currently in + // progress which cover the request. If not, a new refill request is issued + // and the next free entry in the table allocated. Otherwise the existing + // table entry is updated. + logic [CFG.ID_WIDTH_RESP-1:0] hit_id; + logic [CFG.LINE_WIDTH-1:0] hit_data; + logic hit_error; + logic hit_valid; + logic hit_ready; + + always_comb begin : p_miss_handler + hit_valid = 0; + hit_id = 'b1 << in_req_id_i; + hit_data = in_req_data_i; + hit_error = in_req_error_i; + + push_index = free_id; + push_init = 0; + push_addr = in_req_addr_i; + push_idmask = 'b1 << in_req_id_i; + push_enable = 0; + + in_req_ready_o = 1; + + out_req_addr_o = in_req_addr_i; + out_req_id_o = free_id; + out_req_valid_o = 0; + + if (in_req_valid_i) begin + // The cache lookup was a hit. + if (in_req_hit_i) begin + hit_valid = 1; + in_req_ready_o = hit_ready; + + // The cache lookup was a miss, but there is already a pending + // refill that covers the line. + end else if (pending) begin + push_index = pending_id; + push_enable = 1; + + // The cache lookup was a miss, there is no pending refill, but + // there are available entries in the table. + end else if (free) begin + out_req_addr_o = in_req_addr_i; + out_req_id_o = free_id; + out_req_valid_o = 1; + in_req_ready_o = out_req_ready_i; + push_index = free_id; + push_init = 1; + push_enable = out_req_ready_i; + + // The cache lookup was a miss, there is no pending refill, and + // there is no room in the table for a new refill at the moment. + end else begin + in_req_ready_o = 0; + end + end + end + + // The cache line eviction LFSR is responsible for picking a cache line for + // replacement at random. Note that we assume that the entire cache is full, + // so no empty cache lines are available. This is the common case since we + // do not support flushing of the cache. + logic [CFG.SET_ALIGN-1:0] evict_index; + logic evict_enable; + + snitch_icache_lfsr #(CFG.SET_ALIGN) i_evict_lfsr ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .value_o ( evict_index ), + .enable_i ( evict_enable ) + ); + + // The response handler deals with incoming refill responses. It queries and + // clears the corresponding entry in the pending table, stores the data in + // the cache via the `write` port, and returns the data to the appropriate + // fetch ports via the `in_rsp` port. It also mixes the data of a cache hit + // into the response stream. + logic write_served_q; + logic in_rsp_served_q; + logic rsp_valid, rsp_ready; + + struct packed { + logic sel; + logic lock; + } arb_q, arb_d; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + arb_q <= '0; + else + arb_q <= arb_d; + end + + always_comb begin : p_response_handler + pop_index = out_rsp_id_i; + pop_enable = 0; + + write_addr_o = pop_addr >> CFG.LINE_ALIGN; + write_set_o = evict_index; + write_data_o = out_rsp_data_i; + write_tag_o = pop_addr >> (CFG.LINE_ALIGN + CFG.COUNT_ALIGN); + write_error_o = out_rsp_error_i; + write_valid_o = 0; + + in_rsp_data_o = out_rsp_data_i; + in_rsp_error_o = out_rsp_error_i; + in_rsp_id_o = pop_idmask; + in_rsp_valid_o = 0; + + hit_ready = 1; + out_rsp_ready_o = 1; + evict_enable = 0; + rsp_valid = 0; + rsp_ready = 1; + + arb_d = arb_q; + if (!arb_q.lock) begin + if (hit_valid) begin + arb_d.sel = 0; + arb_d.lock = 1; + end else if (out_rsp_valid_i) begin + arb_d.sel = 1; + arb_d.lock = 1; + end else begin + arb_d.sel = 0; + arb_d.lock = 0; + end + end + + // Cache hit data is pending. + if (arb_d.sel == 0) begin + if (hit_valid) begin + out_rsp_ready_o = 0; + in_rsp_data_o = hit_data; + in_rsp_error_o = 0; + in_rsp_id_o = hit_id; + in_rsp_valid_o = 1; + hit_ready = in_rsp_ready_i; + end else hit_ready = 1; + if (hit_ready) arb_d.lock = 0; + + // No cache hit is pending, but response data is available. + end else if (arb_d.sel == 1) begin + if (out_rsp_valid_i) begin + rsp_valid = 1; + rsp_ready = (in_rsp_ready_i || in_rsp_served_q) && (write_ready_i || write_served_q); + write_valid_o = 1 && ~write_served_q; + in_rsp_valid_o = 1 && ~in_rsp_served_q; + pop_enable = rsp_ready; + out_rsp_ready_o = rsp_ready; + evict_enable = rsp_ready; + end else rsp_ready = 1; + if (rsp_ready) arb_d.lock = 0; + end + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + write_served_q <= 0; + in_rsp_served_q <= 0; + end else begin + write_served_q <= rsp_valid & ~rsp_ready & (write_served_q | write_ready_i); + in_rsp_served_q <= rsp_valid & ~rsp_ready & (in_rsp_served_q | in_rsp_ready_i); + end + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv new file mode 100644 index 0000000000..63cf03affa --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv @@ -0,0 +1,411 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki +// Florian Zaruba + +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + +/// A simple single-line cache private to each port. +module snitch_icache_l0 import snitch_icache_pkg::*; #( + parameter config_t CFG = '0, + parameter int unsigned L0_ID = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_valid_i, + + input logic enable_prefetching_i, + output icache_events_t icache_events_o, + + input logic [CFG.FETCH_AW-1:0] in_addr_i, + input logic in_valid_i, + output logic [CFG.FETCH_DW-1:0] in_data_o, + output logic in_ready_o, + output logic in_error_o, + + output logic [CFG.FETCH_AW-1:0] out_req_addr_o, + output logic [CFG.ID_WIDTH_REQ-1:0] out_req_id_o, + output logic out_req_valid_o, + input logic out_req_ready_i, + + input logic [CFG.LINE_WIDTH-1:0] out_rsp_data_i, + input logic out_rsp_error_i, + input logic [CFG.ID_WIDTH_RESP-1:0] out_rsp_id_i, + input logic out_rsp_valid_i, + output logic out_rsp_ready_o +); + + typedef logic [CFG.FETCH_AW-1:0] addr_t; + typedef struct packed { + logic [CFG.L0_TAG_WIDTH-1:0] tag; + logic vld; + } tag_t; + + logic [CFG.L0_TAG_WIDTH-1:0] addr_tag, addr_tag_prefetch; + + tag_t [CFG.L0_LINE_COUNT-1:0] tag; + logic [CFG.L0_LINE_COUNT-1:0][CFG.LINE_WIDTH-1:0] data; + + logic [CFG.L0_LINE_COUNT-1:0] hit, hit_early, hit_prefetch; + logic hit_early_is_onehot; + logic hit_any; + logic hit_prefetch_any; + logic miss; + + logic [CFG.L0_LINE_COUNT-1:0] evict_strb; + logic [CFG.L0_LINE_COUNT-1:0] flush_strb; + logic [CFG.L0_LINE_COUNT-1:0] validate_strb; + + typedef struct packed { + logic vld; + logic [CFG.FETCH_AW-1:0] addr; + } prefetch_req_t; + + logic latch_prefetch, last_cycle_was_prefetch_q; + prefetch_req_t prefetch_req_q, prefetch_req_d, prefetcher_out; + + // Holds the onehot signal for the line being refilled at the moment + logic [CFG.L0_LINE_COUNT-1:0] pending_line_refill_q; + logic pending_refill_q, pending_refill_d; + + logic evict_req; + logic last_cycle_was_miss_q; + + `FF(last_cycle_was_miss_q, miss, '0) + `FF(last_cycle_was_prefetch_q, latch_prefetch, '0) + + logic evict_because_miss, evict_because_prefetch; + + typedef struct packed { + logic is_prefetch; + logic [CFG.FETCH_AW-1:0] addr; + } req_t; + + req_t refill, prefetch; + logic refill_valid, prefetch_valid; + logic refill_ready, prefetch_ready; + req_t out_req; + + assign evict_because_miss = miss & ~last_cycle_was_miss_q; + assign evict_because_prefetch = latch_prefetch & ~last_cycle_was_prefetch_q; + + assign evict_req = evict_because_miss | evict_because_prefetch; + + assign addr_tag = in_addr_i >> CFG.LINE_ALIGN; + + // ------------ + // Tag Compare + // ------------ + for (genvar i = 0; i < CFG.L0_LINE_COUNT; i++) begin : gen_cmp_fetch + assign hit_early[i] = tag[i].vld & (tag[i].tag[CFG.L0_EARLY_TAG_WIDTH-1:0] == addr_tag[CFG.L0_EARLY_TAG_WIDTH-1:0]); + // The two signals calculate the same. + if (CFG.L0_TAG_WIDTH == CFG.L0_EARLY_TAG_WIDTH) begin : gen_hit_assign + assign hit[i] = hit_early[i]; + // Compare the rest of the tag. + end else begin : gen_hit + assign hit[i] = hit_early[i] & (tag[i].tag[CFG.L0_TAG_WIDTH-1:CFG.L0_EARLY_TAG_WIDTH] == addr_tag[CFG.L0_TAG_WIDTH-1:CFG.L0_EARLY_TAG_WIDTH]); + end + assign hit_prefetch[i] = tag[i].vld & (tag[i].tag == addr_tag_prefetch); + end + + assign hit_any = |hit; + assign hit_prefetch_any = |hit_prefetch; + assign miss = ~hit_any & in_valid_i & ~pending_refill_q; + + logic clk_inv; + tc_clk_inverter i_clk_inv ( + .clk_i (clk_i), + .clk_o (clk_inv) + ); + + for (genvar i = 0; i < CFG.L0_LINE_COUNT; i++) begin : gen_array + // Tag Array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + tag[i].vld <= 0; + tag[i].tag <= 0; + end else begin + if (evict_strb[i]) begin + tag[i].vld <= 1'b0; + tag[i].tag <= evict_because_prefetch ? addr_tag_prefetch : addr_tag; + end else if (validate_strb[i]) begin + tag[i].vld <= 1'b1; + end + if (flush_strb[i]) begin + tag[i].vld <= 1'b0; + end + end + end + if (CFG.EARLY_LATCH) begin : gen_latch + logic clk_vld; + tc_clk_gating i_clk_gate ( + .clk_i (clk_inv ), + .en_i (validate_strb[i]), + .test_en_i (1'b0 ), + .clk_o (clk_vld ) + ); + // Data Array + /* verilator lint_off NOLATCH */ + always_latch begin + if (clk_vld) begin + data[i] <= out_rsp_data_i; + end + end + /* verilator lint_on NOLATCH */ + end else begin : gen_ff + `FFLNR(data[i], out_rsp_data_i, validate_strb[i], clk_i) + end + end + + // ---- + // HIT + // ---- + // we hit in the cache and there was a unique hit. + assign in_ready_o = hit_any & hit_early_is_onehot; + + logic [CFG.LINE_WIDTH-1:0] ins_data; + always_comb begin : data_muxer + ins_data = '0; + for (int unsigned i = 0; i < CFG.L0_LINE_COUNT; i++) begin + ins_data |= {CFG.LINE_WIDTH{hit_early[i]}} & data[i]; + end + in_data_o = ins_data >> (in_addr_i[CFG.LINE_ALIGN-1:CFG.FETCH_ALIGN] * CFG.FETCH_DW); + end + + // Check whether we had an early multi-hit (e.g., the portion of the tag matched + // multiple entries in the tag array) + if (CFG.L0_TAG_WIDTH != CFG.L0_EARLY_TAG_WIDTH) begin : gen_multihit_detection + onehot #( + .Width (CFG.L0_LINE_COUNT) + ) i_onehot_hit_early ( + .d_i (hit_early), + .is_onehot_o (hit_early_is_onehot) + ); + end else begin : gen_no_multihit_detection + assign hit_early_is_onehot = 1'b1; + end + + // ------- + // Evictor + // ------- + logic [$clog2(CFG.L0_LINE_COUNT)-1:0] cnt_d, cnt_q; + + always_comb begin : evictor + evict_strb = '0; + cnt_d = cnt_q; + + // Round-Robin + if (evict_req) begin + evict_strb = 1 << cnt_q; + cnt_d = cnt_q + 1; + if (evict_strb == hit_early) begin + evict_strb = 1 << cnt_d; + cnt_d = cnt_q + 2; + end + end + end + + always_comb begin : flush + flush_strb = '0; + // Check whether we encountered a multi-hit condition and + // evict the offending entry. + if (hit_any && !hit_early_is_onehot) begin + // We want to evict all entries which hit with the early tag + // but didn't hit in the final comparison. + flush_strb = ~hit & hit_early; + end + if (flush_valid_i) flush_strb = '1; + end + + `FF(cnt_q, cnt_d, '0) + + // ------------- + // Miss Handling + // ------------- + assign refill.addr = addr_tag << CFG.LINE_ALIGN; + assign refill.is_prefetch = 1'b0; + assign refill_valid = miss; + + `FFLNR(pending_line_refill_q, evict_strb, evict_req, clk_i) + `FF(pending_refill_q, pending_refill_d, '0) + + always_comb begin + pending_refill_d = pending_refill_q; + // re-set condition + if (pending_refill_q) begin + if (out_rsp_valid_i & out_rsp_ready_o) begin + pending_refill_d = 1'b0; + end + // set condition + end else begin + if (refill_valid && refill_ready) begin + pending_refill_d = 1'b1; + end + if (latch_prefetch) begin + pending_refill_d = 1'b1; + end + end + end + + assign validate_strb = out_rsp_valid_i ? pending_line_refill_q : '0; + assign out_rsp_ready_o = 1'b1; + + assign in_error_o = '0; + + assign out_req_addr_o = out_req.addr; + assign out_req_id_o = {L0_ID, out_req.is_prefetch}; + + // Priority arbitrate requests. + always_comb begin + out_req = prefetch; + out_req_valid_o = prefetch_valid; + prefetch_ready = out_req_ready_i; + refill_ready = 1'b0; + + if (refill_valid) begin + out_req_valid_o = refill_valid; + out_req = refill; + refill_ready = out_req_ready_i; + prefetch_ready = 1'b0; + end + end + + // ------------- + // Pre-fetching + // ------------- + // Generate a prefetch request if the cache hits and we haven't + // pre-fetched the line yet and there is no other refill in progress. + assign prefetcher_out.vld = enable_prefetching_i & hit_any & ~hit_prefetch_any & ~pending_refill_q; + + localparam FETCH_PKTS = CFG.LINE_WIDTH/32; + logic [FETCH_PKTS-1:0] is_branch_taken; + logic [FETCH_PKTS-1:0] is_jal; + logic [FETCH_PKTS-1:0] mask; + // make sure that we only look at the packets which are of interest to + assign mask = '1 << in_addr_i[CFG.LINE_ALIGN-1:2]; + + // Instruction aware pre-fetching + for (genvar i = 0; i < FETCH_PKTS; i++) begin : gen_pre_decode + // iterate over the fetch packets (32 bits per instruction) + always_comb begin + is_branch_taken[i] = 1'b0; + is_jal[i] = 1'b0; + if (hit_early_is_onehot) begin + unique casez (ins_data[i*32+:32]) + // static prediction + riscv_instr::BEQ, + riscv_instr::BNE, + riscv_instr::BLT, + riscv_instr::BGE, + riscv_instr::BLTU, + riscv_instr::BGEU: begin + // look at the sign bit of the immediate field + // backward branches (immediate negative) taken + // forward branches not taken + is_branch_taken[i] = ins_data[i*32+31]; + end + riscv_instr::JAL: begin + is_jal[i] = 1'b1; + end + // we can't do anything about the JALR case as we don't + // know the destination. + default:; + endcase + end + end + end + + logic [$clog2(FETCH_PKTS)-1:0] taken_idx; + logic no_prefetch; + logic [$clog2(CFG.LINE_WIDTH)-1:0] ins_idx; + assign ins_idx = 32*taken_idx; + // Find first taken branch + lzc #( + .WIDTH(FETCH_PKTS), + .MODE(0) + ) i_lzc_branch ( + // look at branches and jals + .in_i (mask & (is_branch_taken | is_jal)), + .cnt_o (taken_idx), + .empty_o (no_prefetch) + ); + + addr_t base_addr, offset, uj_imm, sb_imm; + logic [CFG.LINE_ALIGN-1:0] base_offset; + assign base_offset = taken_idx << 2; + assign uj_imm = $signed({ins_data[ins_idx+31], ins_data[ins_idx+12+:8], ins_data[ins_idx+20], ins_data[ins_idx+21+:10], 1'b0}); + assign sb_imm = $signed({ins_data[ins_idx+31], ins_data[ins_idx+7], ins_data[ins_idx+25+:6], ins_data[ins_idx+8+:4], 1'b0}); + + // next address calculation + always_comb begin + // default is next line predictor + base_addr = no_prefetch ? in_addr_i : {in_addr_i >> CFG.LINE_ALIGN, base_offset}; + offset = (1 << CFG.LINE_ALIGN); + // If the cache-line contains a taken branch, compute the pre-fetch address with the jump's offset. + unique case ({is_branch_taken[taken_idx] & ~no_prefetch, is_jal[taken_idx] & ~no_prefetch}) + // JAL: UJ Immediate + 2'b01: offset = uj_imm; + // Branch: // SB Immediate + 2'b10: offset = sb_imm; + default:; + endcase + end + + assign prefetcher_out.addr = ($signed(base_addr) + offset) >> CFG.LINE_ALIGN << CFG.LINE_ALIGN; + + // check whether cache-line we want to pre-fetch is already present + assign addr_tag_prefetch = prefetcher_out.addr >> CFG.LINE_ALIGN; + + assign latch_prefetch = prefetcher_out.vld & ~prefetch_req_q.vld; + + always_comb begin + prefetch_req_d = prefetch_req_q; + + if (prefetch_ready) prefetch_req_d.vld = 1'b0; + + if (latch_prefetch) begin + prefetch_req_d.vld = 1'b1; + prefetch_req_d.addr = prefetcher_out.addr; + end + end + + assign prefetch.is_prefetch = 1'b1; + assign prefetch.addr = prefetch_req_q.addr; + assign prefetch_valid = prefetch_req_q.vld; + + `FF(prefetch_req_q.vld, prefetch_req_d.vld, '0) + `FF(prefetch_req_q.addr, prefetch_req_d.addr, '0) + + // ------------------ + // Performance Events + // ------------------ + always_comb begin + icache_events_o = '0; + icache_events_o.l0_miss = miss; + icache_events_o.l0_hit = hit_any & in_valid_i; + icache_events_o.l0_prefetch = prefetcher_out.vld; + icache_events_o.l0_double_hit = hit_any & ~hit_early_is_onehot & in_valid_i; + end + + // ---------- + // Assertions + // ---------- + `ASSERT(HitOnehot, $onehot0(hit)) + // make sure only one signal is high and the conditions are mutual exclusive + `ASSERT(ExclusiveEvict, $onehot0({evict_because_miss, evict_because_prefetch})) + // request must be stable + `ASSERT(InstReqStable, in_valid_i && !in_ready_o |=> in_valid_i) + `ASSERT(InstReqDataStable, in_valid_i && !in_ready_o |=> $stable(in_addr_i)) + + `ASSERT(RefillReqStable, out_req_valid_o && !out_req_ready_i |=> out_req_valid_o) + `ASSERT(RefillReqDataStable, out_req_valid_o && !out_req_ready_i |=> $stable(out_req_addr_o) && $stable(out_req_id_o)) + + `ASSERT(RefillRspStable, out_rsp_valid_i && !out_rsp_ready_o |=> out_rsp_valid_i) + `ASSERT(RefillRspDataStable, out_rsp_valid_i && !out_rsp_ready_o |=> $stable(out_rsp_data_i) && $stable(out_rsp_error_i) && $stable(out_rsp_id_i)) + // make sure we observe a double hit condition + `COVER(HitEarlyNotOnehot, hit |-> $onehot(hit_early)) + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv new file mode 100644 index 0000000000..748cefe59c --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv @@ -0,0 +1,120 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki + +/// A linear feedback shift register. +/// +/// The register provides a maximum length sequence for N <= 32. For larger N, +/// multiple LFSR are instantiated. Note that the generated sequence is forced +/// to include the value 0, making it length 2**N instead of the usual 2**N-1. +module snitch_icache_lfsr #( + parameter int N = -1 +)( + input logic clk_i, + input logic rst_ni, + output logic [N-1:0] value_o, + input logic enable_i +); + + `ifndef SYNTHESIS + initial assert(N > 0); + `endif + + if (N > 32) begin : g_split + + localparam int N0 = N/2; + localparam int N1 = N-N0; + + snitch_icache_lfsr #(N0) i_lo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .value_o ( value_o[N0-1:0] ), + .enable_i ( enable_i ) + ); + + snitch_icache_lfsr #(N1) i_hi ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .value_o ( value_o[N-1:N0] ), + .enable_i ( enable_i && value_o[N0-1:0] == 0 ) + ); + + end else if (N == 1) begin : g_toggle + + logic q; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + q <= 0; + else if (enable_i) + q <= ~q; + end + + assign value_o = q; + + end else begin : g_impl + + logic [N-1:0] q, d, taps; + + assign value_o = q; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + q <= 0; + else if (enable_i) + q <= d; + end + + always_comb begin + if (q == '0) begin + d = '1; + end else begin + d = {1'b0, q[N-1:1]}; + if (q[0]) d ^= taps; + if (d == '1) d = '0; + end + end + + // A lookup table for the taps. + always_comb begin + taps = 1 << (N-1); + case (N) + 2: taps = $unsigned( 1<< 1 | 1<< 0 ); + 3: taps = $unsigned( 1<< 2 | 1<< 1 ); + 4: taps = $unsigned( 1<< 3 | 1<< 2 ); + 5: taps = $unsigned( 1<< 4 | 1<< 2 ); + 6: taps = $unsigned( 1<< 5 | 1<< 4 ); + 7: taps = $unsigned( 1<< 6 | 1<< 5 ); + 8: taps = $unsigned( 1<< 7 | 1<< 5 | 1<< 4 | 1<< 3 ); + 9: taps = $unsigned( 1<< 8 | 1<< 4 ); + 10: taps = $unsigned( 1<< 9 | 1<< 6 ); + 11: taps = $unsigned( 1<<10 | 1<< 8 ); + 12: taps = $unsigned( 1<<11 | 1<<10 | 1<< 9 | 1<< 3 ); + 13: taps = $unsigned( 1<<12 | 1<<11 | 1<<10 | 1<< 7 ); + 14: taps = $unsigned( 1<<13 | 1<<12 | 1<<11 | 1<< 1 ); + 15: taps = $unsigned( 1<<14 | 1<<13 ); + 16: taps = $unsigned( 1<<15 | 1<<14 | 1<<12 | 1<< 3 ); + 17: taps = $unsigned( 1<<16 | 1<<13 ); + 18: taps = $unsigned( 1<<17 | 1<<10 ); + 19: taps = $unsigned( 1<<18 | 1<<17 | 1<<16 | 1<<13 ); + 20: taps = $unsigned( 1<<19 | 1<<16 ); + 21: taps = $unsigned( 1<<20 | 1<<18 ); + 22: taps = $unsigned( 1<<21 | 1<<20 ); + 23: taps = $unsigned( 1<<22 | 1<<17 ); + 24: taps = $unsigned( 1<<23 | 1<<22 | 1<<21 | 1<<16 ); + 25: taps = $unsigned( 1<<24 | 1<<21 ); + 26: taps = $unsigned( 1<<25 | 1<< 5 | 1<< 1 | 1<< 0 ); + 27: taps = $unsigned( 1<<26 | 1<< 4 | 1<< 1 | 1<< 0 ); + 28: taps = $unsigned( 1<<27 | 1<<24 ); + 29: taps = $unsigned( 1<<28 | 1<<26 ); + 30: taps = $unsigned( 1<<29 | 1<< 5 | 1<< 3 | 1<< 0 ); + 31: taps = $unsigned( 1<<30 | 1<<27 ); + 32: taps = $unsigned( 1<<31 | 1<<21 | 1<< 1 | 1<< 0 ); + endcase; + end + + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv new file mode 100644 index 0000000000..962373e9a8 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv @@ -0,0 +1,295 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Samuel Riedel + +`include "common_cells/registers.svh" + +/// An actual cache lookup. +module snitch_icache_lookup #( + parameter snitch_icache_pkg::config_t CFG = '0 +)( + input logic clk_i, + input logic rst_ni, + + input logic flush_valid_i, + output logic flush_ready_o, + + input logic [CFG.FETCH_AW-1:0] in_addr_i, + input logic [CFG.ID_WIDTH_REQ-1:0] in_id_i, + input logic in_valid_i, + output logic in_ready_o, + + output logic [CFG.FETCH_AW-1:0] out_addr_o, + output logic [CFG.ID_WIDTH_REQ-1:0] out_id_o, + output logic [CFG.SET_ALIGN-1:0] out_set_o, + output logic out_hit_o, + output logic [CFG.LINE_WIDTH-1:0] out_data_o, + output logic out_error_o, + output logic out_valid_o, + input logic out_ready_i, + + input logic [CFG.COUNT_ALIGN-1:0] write_addr_i, + input logic [CFG.SET_ALIGN-1:0] write_set_i, + input logic [CFG.LINE_WIDTH-1:0] write_data_i, + input logic [CFG.TAG_WIDTH-1:0] write_tag_i, + input logic write_error_i, + input logic write_valid_i, + output logic write_ready_o +); + + localparam int unsigned DATA_ADDR_WIDTH = $clog2(CFG.SET_COUNT) + CFG.COUNT_ALIGN; + + `ifndef SYNTHESIS + initial assert(CFG != '0); + `endif + + logic [CFG.COUNT_ALIGN:0] init_count_q; + logic init_phase; + + // We are always ready to flush + assign flush_ready_o = 1'b1; + assign init_phase = init_count_q != $unsigned(CFG.LINE_COUNT); + // Initialization and flush FSM + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + init_count_q <= '0; + else if (init_count_q != $unsigned(CFG.LINE_COUNT)) + init_count_q <= init_count_q + 1; + else if (flush_valid_i) + init_count_q <= '0; + end + + // -------------------------------------------------- + // Tag stage + // -------------------------------------------------- + typedef struct packed { + logic [CFG.FETCH_AW-1:0] addr; + logic [CFG.ID_WIDTH_REQ-1:0] id; + } tag_req_t; + + typedef struct packed { + logic [CFG.SET_ALIGN-1:0] cset; + logic hit; + logic error; + } tag_rsp_t; + + logic req_valid, req_ready; + logic req_handshake; + + logic [CFG.COUNT_ALIGN-1:0] tag_addr; + logic [CFG.SET_COUNT-1:0] tag_enable; + logic [CFG.TAG_WIDTH+1:0] tag_wdata, tag_rdata [CFG.SET_COUNT]; + logic tag_write; + + tag_req_t tag_req_d, tag_req_q; + tag_rsp_t tag_rsp_s, tag_rsp_d, tag_rsp_q, tag_rsp; + logic tag_valid, tag_ready; + logic tag_handshake; + + logic [CFG.TAG_WIDTH-1:0] required_tag; + logic [CFG.SET_COUNT-1:0] line_hit; + + logic [DATA_ADDR_WIDTH-1:0] lookup_addr; + logic [DATA_ADDR_WIDTH-1:0] write_addr; + + // Connect input requests to tag stage + assign tag_req_d.addr = in_addr_i; + assign tag_req_d.id = in_id_i; + + // Multiplex read and write access to the tag banks onto one port, prioritizing write accesses + always_comb begin + tag_addr = in_addr_i >> CFG.LINE_ALIGN; + tag_enable = '0; + tag_wdata = {1'b1, write_error_i, write_tag_i}; + tag_write = 1'b0; + + write_ready_o = 1'b0; + in_ready_o = 1'b0; + req_valid = 1'b0; + + if (init_phase) begin + tag_addr = init_count_q; + tag_enable = '1; + tag_wdata = '0; + tag_write = 1'b1; + end else if (write_valid_i) begin + // Write a refill request + tag_addr = write_addr_i; + tag_enable = $unsigned(1 << write_set_i); + tag_write = 1'b1; + write_ready_o = 1'b1; + end else if (in_valid_i) begin + // Check cache + tag_enable = '1; + in_ready_o = req_ready; + // Request to store data in pipeline + req_valid = 1'b1; + end + end + + // Instantiate the tag sets. + for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets + if (CFG.L1_TAG_SCM) begin : gen_scm + latch_scm #( + .ADDR_WIDTH ($clog2(CFG.LINE_COUNT)), + .DATA_WIDTH (CFG.TAG_WIDTH+2 ) + ) i_tag ( + .clk ( clk_i ), + .ReadEnable ( tag_enable[i] && !tag_write ), + .ReadAddr ( tag_addr ), + .ReadData ( tag_rdata[i] ), + .WriteEnable ( tag_enable[i] && tag_write ), + .WriteAddr ( tag_addr ), + .WriteData ( tag_wdata ) + ); + end else begin : gen_sram + tc_sram #( + .DataWidth ( CFG.TAG_WIDTH+2 ), + .NumWords ( CFG.LINE_COUNT ), + .NumPorts ( 1 ) + ) i_tag ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( tag_enable[i] ), + .we_i ( tag_write ), + .addr_i ( tag_addr ), + .wdata_i ( tag_wdata ), + .be_i ( '1 ), + .rdata_o ( tag_rdata[i] ) + ); + end + end + + // Determine which set hit + always_comb begin + automatic logic [CFG.SET_COUNT-1:0] errors; + required_tag = tag_req_q.addr >> (CFG.LINE_ALIGN + CFG.COUNT_ALIGN); + for (int i = 0; i < CFG.SET_COUNT; i++) begin + line_hit[i] = tag_rdata[i][CFG.TAG_WIDTH+1] && tag_rdata[i][CFG.TAG_WIDTH-1:0] == required_tag; + errors[i] = tag_rdata[i][CFG.TAG_WIDTH] && line_hit[i]; + end + tag_rsp_s.hit = |line_hit; + tag_rsp_s.error = |errors; + end + + lzc #(.WIDTH(CFG.SET_COUNT)) i_lzc ( + .in_i ( line_hit ), + .cnt_o ( tag_rsp_s.cset ), + .empty_o ( ) + ); + + // Buffer the metadata on a valid handshake. Stall on write (implicit in req_valid/ready) + `FFL(tag_req_q, tag_req_d, req_valid && req_ready, '0, clk_i, rst_ni) + `FF(tag_valid, req_valid ? 1'b1 : tag_ready ? 1'b0 : tag_valid, '0, clk_i, rst_ni) + // Ready if buffer is empy or downstream is reading. Stall on write + assign req_ready = (!tag_valid || tag_ready) && !tag_write; + + // Register the handshake of the reg stage to buffer the tag output data in the next cycle + `FF(req_handshake, req_valid && req_ready, 1'b0, clk_i, rst_ni) + + // Fall-through buffer the tag data: Store the tag data if the SRAM bank accepted a request in + // the previous cycle and if we actually have to buffer them because the receiver is not ready + `FF(tag_rsp_q, tag_rsp_d, '0, clk_i, rst_ni) + assign tag_rsp = req_handshake ? tag_rsp_s : tag_rsp_q; + always_comb begin + tag_rsp_d = tag_rsp_q; + // Load the FF if new data is incoming and downstream is not ready + if (req_handshake && !tag_ready) begin + tag_rsp_d = tag_rsp_s; + end + // Override the hit if the write that stalled us invalidated the data + if (lookup_addr == write_addr && write_valid_i) begin + tag_rsp_d.hit = 1'b0; + end + end + + // -------------------------------------------------- + // Data stage + // -------------------------------------------------- + + typedef struct packed { + logic [CFG.FETCH_AW-1:0] addr; + logic [CFG.ID_WIDTH_REQ-1:0] id; + logic [CFG.SET_ALIGN-1:0] cset; + logic hit; + logic error; + } data_req_t; + + typedef logic [CFG.LINE_WIDTH-1:0] data_rsp_t; + + logic [DATA_ADDR_WIDTH-1:0] data_addr; + logic data_enable; + data_rsp_t data_wdata, data_rdata; + logic data_write; + + data_req_t data_req_d, data_req_q; + data_rsp_t data_rsp_q; + logic data_valid, data_ready; + + // Connect tag stage response to data stage request + assign data_req_d.addr = tag_req_q.addr; + assign data_req_d.id = tag_req_q.id; + assign data_req_d.cset = tag_rsp.cset; + assign data_req_d.hit = tag_rsp.hit; + assign data_req_d.error = tag_rsp.error; + + assign lookup_addr = {tag_rsp.cset, tag_req_q.addr[CFG.LINE_ALIGN +: CFG.COUNT_ALIGN]}; + assign write_addr = {write_set_i, write_addr_i}; + + // Data bank port mux + always_comb begin + // Default read request + data_addr = lookup_addr; + data_enable = tag_valid && tag_rsp.hit; // Only read data on hit + data_wdata = write_data_i; + data_write = 1'b0; + // Write takes priority + if (!init_phase && write_valid_i) begin + data_addr = write_addr; + data_enable = 1'b1; + data_write = 1'b1; + end + end + + tc_sram #( + .DataWidth ( CFG.LINE_WIDTH ), + .NumWords ( CFG.LINE_COUNT * CFG.SET_COUNT ), + .NumPorts ( 1 ) + ) i_data ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( data_enable ), + .we_i ( data_write ), + .addr_i ( data_addr ), + .wdata_i ( data_wdata ), + .be_i ( '1 ), + .rdata_o ( data_rdata ) + ); + + // Buffer the metadata on a valid handshake. Stall on write (implicit in tag_ready) + `FFL(data_req_q, data_req_d, tag_valid && tag_ready, '0, clk_i, rst_ni) + `FF(data_valid, (tag_valid && !data_write) ? 1'b1 : data_ready ? 1'b0 : data_valid, '0, clk_i, rst_ni) + // Ready if buffer is empy or downstream is reading. Stall on write + assign tag_ready = (!data_valid || data_ready) && !data_write; + + // Register the handshake of the tag stage to buffer the data output data in the next cycle + // but only if it was a hit. Otherwise, the data is not read anyway. + `FF(tag_handshake, tag_valid && tag_ready && data_req_d.hit, 1'b0, clk_i, rst_ni) + + // Fall-through buffer the read data: Store the read data if the SRAM bank accepted a request in + // the previous cycle and if we actually have to buffer them because the receiver is not ready + `FFL(data_rsp_q, data_rdata, tag_handshake && !data_ready, '0, clk_i, rst_ni) + assign out_data_o = tag_handshake ? data_rdata : data_rsp_q; + + // Generate the remaining output signals. + assign out_addr_o = data_req_q.addr; + assign out_id_o = data_req_q.id; + assign out_set_o = data_req_q.cset; + assign out_hit_o = data_req_q.hit; + assign out_error_o = data_req_q.error; + assign out_valid_o = data_valid; + assign data_ready = out_ready_i; + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv new file mode 100644 index 0000000000..4ed2c9101e --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv @@ -0,0 +1,45 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki + +package snitch_icache_pkg; + + typedef struct packed { + logic l0_miss; + logic l0_hit; + logic l0_prefetch; + logic l0_double_hit; + } icache_events_t; + + typedef struct packed { + // Parameters passed to the root module. + int NR_FETCH_PORTS; + int LINE_WIDTH; + int LINE_COUNT; + int SET_COUNT; + int PENDING_COUNT; + int L0_LINE_COUNT; + int FETCH_AW; + int FETCH_DW; + int FILL_AW; + int FILL_DW; + bit L1_TAG_SCM; + bit EARLY_LATCH; + + // Derived values. + int FETCH_ALIGN; + int FILL_ALIGN; + int LINE_ALIGN; + int COUNT_ALIGN; + int SET_ALIGN; + int TAG_WIDTH; + int L0_TAG_WIDTH; + int L0_EARLY_TAG_WIDTH; + int ID_WIDTH_REQ; + int ID_WIDTH_RESP; + int PENDING_IW; // refill ID width + } config_t; + +endpackage diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv new file mode 100644 index 0000000000..7a723c831a --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv @@ -0,0 +1,115 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Fabian Schuiki + +/// A refiller for cache lines. +module snitch_icache_refill #( + parameter snitch_icache_pkg::config_t CFG = '0 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [CFG.FETCH_AW-1:0] in_req_addr_i, + input logic [CFG.PENDING_IW-1:0] in_req_id_i, + input logic in_req_bypass_i, + input logic in_req_valid_i, + output logic in_req_ready_o, + + output logic [CFG.LINE_WIDTH-1:0] in_rsp_data_o, + output logic in_rsp_error_o, + output logic [CFG.PENDING_IW-1:0] in_rsp_id_o, + output logic in_rsp_bypass_o, + output logic in_rsp_valid_o, + input logic in_rsp_ready_i, + + output logic [CFG.FILL_AW-1:0] refill_qaddr_o, + output logic [7:0] refill_qlen_o, + output logic refill_qvalid_o, + input logic refill_qready_i, + + input logic [CFG.FILL_DW-1:0] refill_pdata_i, + input logic refill_perror_i, + input logic refill_plast_i, + input logic refill_pvalid_i, + output logic refill_pready_o +); + + `ifndef SYNTHESIS + initial assert(CFG != '0); + `endif + + // How many response beats are necessary to refill one cache line. + localparam BEATS_PER_REFILL = CFG.LINE_WIDTH >= CFG.FILL_DW ? CFG.LINE_WIDTH/CFG.FILL_DW : 1; + + // The response queue holds metadata for the issued requests in order. + logic queue_full; + logic queue_push; + logic queue_pop; + + fifo_v3 #( + .DEPTH ( 4 ), + .DATA_WIDTH ( CFG.PENDING_IW+1 ) + ) i_fifo_id_queue ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( queue_full ), + .empty_o ( ), + .usage_o ( ), + .data_i ( {in_req_bypass_i, in_req_id_i} ), + .push_i ( queue_push ), + .data_o ( {in_rsp_bypass_o, in_rsp_id_o} ), + .pop_i ( queue_pop ) + ); + + // Accept incoming requests, push the ID into the queue, and issue the + // corresponding request. + assign refill_qaddr_o = in_req_addr_i; + assign refill_qlen_o = $unsigned(BEATS_PER_REFILL-1); + assign refill_qvalid_o = in_req_valid_i & ~queue_full; + assign in_req_ready_o = refill_qready_i & ~queue_full; + assign queue_push = refill_qvalid_o & refill_qready_i; + + // Assemble incoming responses if the cache line is wider than the bus data width. + logic [CFG.LINE_WIDTH-1:0] response_data; + + if (CFG.LINE_WIDTH > CFG.FILL_DW) begin : g_data_concat + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) + response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= '0; + else if (refill_pvalid_i && refill_pready_o) + response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= response_data[CFG.LINE_WIDTH-1:CFG.FILL_DW]; + end + assign response_data[CFG.LINE_WIDTH-1:CFG.LINE_WIDTH-CFG.FILL_DW] = refill_pdata_i; + end else if (CFG.LINE_WIDTH < CFG.FILL_DW) begin : g_data_slice + assign response_data = refill_pdata_i >> (in_req_addr_i[CFG.FILL_ALIGN-1:CFG.LINE_ALIGN] * CFG.LINE_WIDTH); + end else begin : g_data_passthrough + assign response_data = refill_pdata_i; + end + + // Accept response beats. Upon the last beat, pop the ID off the queue + // and return the response. + always_comb begin : p_response + in_rsp_data_o = response_data; + in_rsp_error_o = refill_perror_i; + in_rsp_valid_o = 0; + queue_pop = 0; + refill_pready_o = 0; + + if (refill_pvalid_i) begin + if (!refill_plast_i) begin + refill_pready_o = 1; + end else begin + in_rsp_valid_o = 1; + if (in_rsp_ready_i) begin + refill_pready_o = 1; + queue_pop = 1; + end + end + end + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_ipu.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_ipu.sv new file mode 100644 index 0000000000..50ee87926b --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_ipu.sv @@ -0,0 +1,1544 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/// Integer Processing Unit +/// Based on Snitch Shared Muliplier/Divider +/// Author: Sergio Mazzola, + +module snitch_ipu #( + parameter int unsigned IdWidth = 5 +) ( + input logic clk_i, + input logic rst_i, + // Accelerator Interface - Slave + input logic [31:0] acc_qaddr_i, // unused + input logic [IdWidth-1:0] acc_qid_i, + input logic [31:0] acc_qdata_op_i, // RISC-V instruction + input logic [31:0] acc_qdata_arga_i, + input logic [31:0] acc_qdata_argb_i, + input logic [31:0] acc_qdata_argc_i, + input logic acc_qvalid_i, + output logic acc_qready_o, + output logic [31:0] acc_pdata_o, + output logic [IdWidth-1:0] acc_pid_o, + output logic acc_perror_o, + output logic acc_pvalid_o, + input logic acc_pready_i +); + `include "common_cells/registers.svh" + + typedef struct packed { + logic [31:0] result; + logic [IdWidth-1:0] id; + } result_t; + // input handshake + logic div_valid_op, div_ready_op; + /* verilator lint_off UNDRIVEN */ + logic mul_valid_op, mul_ready_op; + logic dsp_valid_op, dsp_ready_op; + /* verilator lint_on UNDRIVEN */ + // output handshake + logic mul_valid, mul_ready; + logic div_valid, div_ready; + logic dsp_valid, dsp_ready; + result_t div, mul, dsp, oup; + logic illegal_instruction; + + always_comb begin + mul_valid_op = 1'b0; + div_valid_op = 1'b0; + dsp_valid_op = 1'b0; + acc_qready_o = 1'b0; + acc_perror_o = 1'b0; + illegal_instruction = 1'b0; + unique casez (acc_qdata_op_i) + riscv_instr::MUL, + riscv_instr::MULH, + riscv_instr::MULHSU, + riscv_instr::MULHU: begin + if (snitch_pkg::XPULPIMG) begin + dsp_valid_op = acc_qvalid_i; + acc_qready_o = dsp_ready_op; + end else begin + mul_valid_op = acc_qvalid_i; + acc_qready_o = mul_ready_op; + end + end + riscv_instr::DIV, + riscv_instr::DIVU, + riscv_instr::REM, + riscv_instr::REMU: begin + div_valid_op = acc_qvalid_i; + acc_qready_o = div_ready_op; + end + riscv_instr::P_ABS, // Xpulpimg: p.abs + riscv_instr::P_SLET, // Xpulpimg: p.slet + riscv_instr::P_SLETU, // Xpulpimg: p.sletu + riscv_instr::P_MIN, // Xpulpimg: p.min + riscv_instr::P_MINU, // Xpulpimg: p.minu + riscv_instr::P_MAX, // Xpulpimg: p.max + riscv_instr::P_MAXU, // Xpulpimg: p.maxu + riscv_instr::P_EXTHS, // Xpulpimg: p.exths + riscv_instr::P_EXTHZ, // Xpulpimg: p.exthz + riscv_instr::P_EXTBS, // Xpulpimg: p.extbs + riscv_instr::P_EXTBZ, // Xpulpimg: p.extbz + riscv_instr::P_CLIP, // Xpulpimg: p.clip + riscv_instr::P_CLIPU, // Xpulpimg: p.clipu + riscv_instr::P_CLIPR, // Xpulpimg: p.clipr + riscv_instr::P_CLIPUR, // Xpulpimg: p.clipur + riscv_instr::P_MAC, // Xpulpimg: p.mac + riscv_instr::P_MSU, // Xpulpimg: p.msu + riscv_instr::PV_ADD_H, // Xpulpimg: pv.add.h + riscv_instr::PV_ADD_SC_H, // Xpulpimg: pv.add.sc.h + riscv_instr::PV_ADD_SCI_H, // Xpulpimg: pv.add.sci.h + riscv_instr::PV_ADD_B, // Xpulpimg: pv.add.b + riscv_instr::PV_ADD_SC_B, // Xpulpimg: pv.add.sc.b + riscv_instr::PV_ADD_SCI_B, // Xpulpimg: pv.add.sci.b + riscv_instr::PV_SUB_H, // Xpulpimg: pv.sub.h + riscv_instr::PV_SUB_SC_H, // Xpulpimg: pv.sub.sc.h + riscv_instr::PV_SUB_SCI_H, // Xpulpimg: pv.sub.sci.h + riscv_instr::PV_SUB_B, // Xpulpimg: pv.sub.b + riscv_instr::PV_SUB_SC_B, // Xpulpimg: pv.sub.sc.b + riscv_instr::PV_SUB_SCI_B, // Xpulpimg: pv.sub.sci.b + riscv_instr::PV_AVG_H, // Xpulpimg: pv.avg.h + riscv_instr::PV_AVG_SC_H, // Xpulpimg: pv.avg.sc.h + riscv_instr::PV_AVG_SCI_H, // Xpulpimg: pv.avg.sci.h + riscv_instr::PV_AVG_B, // Xpulpimg: pv.avg.b + riscv_instr::PV_AVG_SC_B, // Xpulpimg: pv.avg.sc.b + riscv_instr::PV_AVG_SCI_B, // Xpulpimg: pv.avg.sci.b + riscv_instr::PV_AVGU_H, // Xpulpimg: pv.avgu.h + riscv_instr::PV_AVGU_SC_H, // Xpulpimg: pv.avgu.sc.h + riscv_instr::PV_AVGU_SCI_H, // Xpulpimg: pv.avgu.sci.h + riscv_instr::PV_AVGU_B, // Xpulpimg: pv.avgu.b + riscv_instr::PV_AVGU_SC_B, // Xpulpimg: pv.avgu.sc.b + riscv_instr::PV_AVGU_SCI_B, // Xpulpimg: pv.avgu.sci.b + riscv_instr::PV_MIN_H, // Xpulpimg: pv.min.h + riscv_instr::PV_MIN_SC_H, // Xpulpimg: pv.min.sc.h + riscv_instr::PV_MIN_SCI_H, // Xpulpimg: pv.min.sci.h + riscv_instr::PV_MIN_B, // Xpulpimg: pv.min.b + riscv_instr::PV_MIN_SC_B, // Xpulpimg: pv.min.sc.b + riscv_instr::PV_MIN_SCI_B, // Xpulpimg: pv.min.sci.b + riscv_instr::PV_MINU_H, // Xpulpimg: pv.minu.h + riscv_instr::PV_MINU_SC_H, // Xpulpimg: pv.minu.sc.h + riscv_instr::PV_MINU_SCI_H, // Xpulpimg: pv.minu.sci.h + riscv_instr::PV_MINU_B, // Xpulpimg: pv.minu.b + riscv_instr::PV_MINU_SC_B, // Xpulpimg: pv.minu.sc.b + riscv_instr::PV_MINU_SCI_B, // Xpulpimg: pv.minu.sci.b + riscv_instr::PV_MAX_H, // Xpulpimg: pv.max.h + riscv_instr::PV_MAX_SC_H, // Xpulpimg: pv.max.sc.h + riscv_instr::PV_MAX_SCI_H, // Xpulpimg: pv.max.sci.h + riscv_instr::PV_MAX_B, // Xpulpimg: pv.max.b + riscv_instr::PV_MAX_SC_B, // Xpulpimg: pv.max.sc.b + riscv_instr::PV_MAX_SCI_B, // Xpulpimg: pv.max.sci.b + riscv_instr::PV_MAXU_H, // Xpulpimg: pv.maxu.h + riscv_instr::PV_MAXU_SC_H, // Xpulpimg: pv.maxu.sc.h + riscv_instr::PV_MAXU_SCI_H, // Xpulpimg: pv.maxu.sci.h + riscv_instr::PV_MAXU_B, // Xpulpimg: pv.maxu.b + riscv_instr::PV_MAXU_SC_B, // Xpulpimg: pv.maxu.sc.b + riscv_instr::PV_MAXU_SCI_B, // Xpulpimg: pv.maxu.sci.b + riscv_instr::PV_SRL_H, // Xpulpimg: pv.srl.h + riscv_instr::PV_SRL_SC_H, // Xpulpimg: pv.srl.sc.h + riscv_instr::PV_SRL_SCI_H, // Xpulpimg: pv.srl.sci.h + riscv_instr::PV_SRL_B, // Xpulpimg: pv.srl.b + riscv_instr::PV_SRL_SC_B, // Xpulpimg: pv.srl.sc.b + riscv_instr::PV_SRL_SCI_B, // Xpulpimg: pv.srl.sci.b + riscv_instr::PV_SRA_H, // Xpulpimg: pv.sra.h + riscv_instr::PV_SRA_SC_H, // Xpulpimg: pv.sra.sc.h + riscv_instr::PV_SRA_SCI_H, // Xpulpimg: pv.sra.sci.h + riscv_instr::PV_SRA_B, // Xpulpimg: pv.sra.b + riscv_instr::PV_SRA_SC_B, // Xpulpimg: pv.sra.sc.b + riscv_instr::PV_SRA_SCI_B, // Xpulpimg: pv.sra.sci.b + riscv_instr::PV_SLL_H, // Xpulpimg: pv.sll.h + riscv_instr::PV_SLL_SC_H, // Xpulpimg: pv.sll.sc.h + riscv_instr::PV_SLL_SCI_H, // Xpulpimg: pv.sll.sci.h + riscv_instr::PV_SLL_B, // Xpulpimg: pv.sll.b + riscv_instr::PV_SLL_SC_B, // Xpulpimg: pv.sll.sc.b + riscv_instr::PV_SLL_SCI_B, // Xpulpimg: pv.sll.sci.b + riscv_instr::PV_OR_H, // Xpulpimg: pv.or.h + riscv_instr::PV_OR_SC_H, // Xpulpimg: pv.or.sc.h + riscv_instr::PV_OR_SCI_H, // Xpulpimg: pv.or.sci.h + riscv_instr::PV_OR_B, // Xpulpimg: pv.or.b + riscv_instr::PV_OR_SC_B, // Xpulpimg: pv.or.sc.b + riscv_instr::PV_OR_SCI_B, // Xpulpimg: pv.or.sci.b + riscv_instr::PV_XOR_H, // Xpulpimg: pv.xor.h + riscv_instr::PV_XOR_SC_H, // Xpulpimg: pv.xor.sc.h + riscv_instr::PV_XOR_SCI_H, // Xpulpimg: pv.xor.sci.h + riscv_instr::PV_XOR_B, // Xpulpimg: pv.xor.b + riscv_instr::PV_XOR_SC_B, // Xpulpimg: pv.xor.sc.b + riscv_instr::PV_XOR_SCI_B, // Xpulpimg: pv.xor.sci.b + riscv_instr::PV_AND_H, // Xpulpimg: pv.and.h + riscv_instr::PV_AND_SC_H, // Xpulpimg: pv.and.sc.h + riscv_instr::PV_AND_SCI_H, // Xpulpimg: pv.and.sci.h + riscv_instr::PV_AND_B, // Xpulpimg: pv.and.b + riscv_instr::PV_AND_SC_B, // Xpulpimg: pv.and.sc.b + riscv_instr::PV_AND_SCI_B, // Xpulpimg: pv.and.sci.b + riscv_instr::PV_ABS_H, // Xpulpimg: pv.abs.h + riscv_instr::PV_ABS_B, // Xpulpimg: pv.abs.b + riscv_instr::PV_EXTRACT_H, // Xpulpimg: pv.extract.h + riscv_instr::PV_EXTRACT_B, // Xpulpimg: pv.extract.b + riscv_instr::PV_EXTRACTU_H, // Xpulpimg: pv.extractu.h + riscv_instr::PV_EXTRACTU_B, // Xpulpimg: pv.extractu.b + riscv_instr::PV_INSERT_H, // Xpulpimg: pv.insert.h + riscv_instr::PV_INSERT_B, // Xpulpimg: pv.insert.b + riscv_instr::PV_DOTUP_H, // Xpulpimg: pv.dotup.h + riscv_instr::PV_DOTUP_SC_H, // Xpulpimg: pv.dotup.sc.h + riscv_instr::PV_DOTUP_SCI_H, // Xpulpimg: pv.dotup.sci.h + riscv_instr::PV_DOTUP_B, // Xpulpimg: pv.dotup.b + riscv_instr::PV_DOTUP_SC_B, // Xpulpimg: pv.dotup.sc.b + riscv_instr::PV_DOTUP_SCI_B, // Xpulpimg: pv.dotup.sci.b + riscv_instr::PV_DOTUSP_H, // Xpulpimg: pv.dotusp.h + riscv_instr::PV_DOTUSP_SC_H, // Xpulpimg: pv.dotusp.sc.h + riscv_instr::PV_DOTUSP_SCI_H, // Xpulpimg: pv.dotusp.sci.h + riscv_instr::PV_DOTUSP_B, // Xpulpimg: pv.dotusp.b + riscv_instr::PV_DOTUSP_SC_B, // Xpulpimg: pv.dotusp.sc.b + riscv_instr::PV_DOTUSP_SCI_B, // Xpulpimg: pv.dotusp.sci.b + riscv_instr::PV_DOTSP_H, // Xpulpimg: pv.dotsp.h + riscv_instr::PV_DOTSP_SC_H, // Xpulpimg: pv.dotsp.sc.h + riscv_instr::PV_DOTSP_SCI_H, // Xpulpimg: pv.dotsp.sci.h + riscv_instr::PV_DOTSP_B, // Xpulpimg: pv.dotsp.b + riscv_instr::PV_DOTSP_SC_B, // Xpulpimg: pv.dotsp.sc.b + riscv_instr::PV_DOTSP_SCI_B, // Xpulpimg: pv.dotsp.sci.b + riscv_instr::PV_SDOTUP_H, // Xpulpimg: pv.sdotup.h + riscv_instr::PV_SDOTUP_SC_H, // Xpulpimg: pv.sdotup.sc.h + riscv_instr::PV_SDOTUP_SCI_H, // Xpulpimg: pv.sdotup.sci.h + riscv_instr::PV_SDOTUP_B, // Xpulpimg: pv.sdotup.b + riscv_instr::PV_SDOTUP_SC_B, // Xpulpimg: pv.sdotup.sc.b + riscv_instr::PV_SDOTUP_SCI_B, // Xpulpimg: pv.sdotup.sci.b + riscv_instr::PV_SDOTUSP_H, // Xpulpimg: pv.sdotusp.h + riscv_instr::PV_SDOTUSP_SC_H, // Xpulpimg: pv.sdotusp.sc.h + riscv_instr::PV_SDOTUSP_SCI_H, // Xpulpimg: pv.sdotusp.sci.h + riscv_instr::PV_SDOTUSP_B, // Xpulpimg: pv.sdotusp.b + riscv_instr::PV_SDOTUSP_SC_B, // Xpulpimg: pv.sdotusp.sc.b + riscv_instr::PV_SDOTUSP_SCI_B, // Xpulpimg: pv.sdotusp.sci.b + riscv_instr::PV_SDOTSP_H, // Xpulpimg: pv.sdotsp.h + riscv_instr::PV_SDOTSP_SC_H, // Xpulpimg: pv.sdotsp.sc.h + riscv_instr::PV_SDOTSP_SCI_H, // Xpulpimg: pv.sdotsp.sci.h + riscv_instr::PV_SDOTSP_B, // Xpulpimg: pv.sdotsp.b + riscv_instr::PV_SDOTSP_SC_B, // Xpulpimg: pv.sdotsp.sc.b + riscv_instr::PV_SDOTSP_SCI_B, // Xpulpimg: pv.sdotsp.sci.b + riscv_instr::PV_SHUFFLE2_H, // Xpulpimg: pv.shuffle2.h + riscv_instr::PV_SHUFFLE2_B: begin // Xpulpimg: pv.shuffle2.b + if (snitch_pkg::XPULPIMG) begin + dsp_valid_op = acc_qvalid_i; + acc_qready_o = dsp_ready_op; + end else begin + illegal_instruction = 1'b1; + end + end + default: illegal_instruction = 1'b1; + endcase + end + + // Serial Divider + serdiv #( + .WIDTH ( 32 ), + .IdWidth ( IdWidth ) + ) i_div ( + .clk_i ( clk_i ), + .rst_ni ( ~rst_i ), + .id_i ( acc_qid_i ), + .operator_i ( acc_qdata_op_i ), + .op_a_i ( acc_qdata_arga_i ), + .op_b_i ( acc_qdata_argb_i ), + .in_vld_i ( div_valid_op ), + .in_rdy_o ( div_ready_op ), + .out_vld_o ( div_valid ), + .out_rdy_i ( div_ready ), + .id_o ( div.id ), + .res_o ( div.result ) + ); + + if (snitch_pkg::XPULPIMG) begin : gen_xpulpimg + // DSP Unit + dspu #( + .Width ( 32 ), + .IdWidth ( IdWidth ) + ) i_dspu ( + .clk_i ( clk_i ), + .rst_i ( rst_i ), + .id_i ( acc_qid_i ), + .operator_i ( acc_qdata_op_i ), + .op_a_i ( acc_qdata_arga_i ), + .op_b_i ( acc_qdata_argb_i ), + .op_c_i ( acc_qdata_argc_i ), + .in_valid_i ( dsp_valid_op ), + .in_ready_o ( dsp_ready_op ), + .out_valid_o ( dsp_valid ), + .out_ready_i ( dsp_ready ), + .id_o ( dsp.id ), + .result_o ( dsp.result ) + ); + // Output Arbitration + stream_arbiter #( + .DATA_T ( result_t ), + .N_INP ( 2 ) + ) i_stream_arbiter ( + .clk_i, + .rst_ni ( ~rst_i ), + .inp_data_i ( {div, dsp} ), + .inp_valid_i ( {div_valid, dsp_valid} ), + .inp_ready_o ( {div_ready, dsp_ready} ), + .oup_data_o ( oup ), + .oup_valid_o ( acc_pvalid_o ), + .oup_ready_i ( acc_pready_i ) + ); + end else begin : gen_vanilla + // Multiplication + multiplier #( + .Width ( 32 ), + .IdWidth ( IdWidth ) + ) i_multiplier ( + .clk_i, + .rst_i, + .id_i ( acc_qid_i ), + .operator_i ( acc_qdata_op_i ), + .operand_a_i ( acc_qdata_arga_i ), + .operand_b_i ( acc_qdata_argb_i ), + .valid_i ( mul_valid_op ), + .ready_o ( mul_ready_op ), + .result_o ( mul.result ), + .valid_o ( mul_valid ), + .ready_i ( mul_ready ), + .id_o ( mul.id ) + ); + // Output Arbitration + stream_arbiter #( + .DATA_T ( result_t ), + .N_INP ( 2 ) + ) i_stream_arbiter ( + .clk_i, + .rst_ni ( ~rst_i ), + .inp_data_i ( {div, mul} ), + .inp_valid_i ( {div_valid, mul_valid} ), + .inp_ready_o ( {div_ready, mul_ready} ), + .oup_data_o ( oup ), + .oup_valid_o ( acc_pvalid_o ), + .oup_ready_i ( acc_pready_i ) + ); + end + + assign acc_pdata_o = oup.result; + assign acc_pid_o = oup.id; +endmodule + + +module dspu #( + parameter int unsigned Width = 32, + parameter int unsigned IdWidth = 5 +) ( + input logic clk_i, // unused + input logic rst_i, // unused + input logic [IdWidth-1:0] id_i, + input logic [31:0] operator_i, + input logic [Width-1:0] op_a_i, + input logic [Width-1:0] op_b_i, + input logic [Width-1:0] op_c_i, + input logic in_valid_i, + output logic in_ready_o, + output logic out_valid_o, + input logic out_ready_i, + output logic [IdWidth-1:0] id_o, + output logic [Width-1:0] result_o +); + + // Control signals + assign out_valid_o = in_valid_i; + assign in_ready_o = out_ready_i; + assign id_o = id_i; + + // Decoded fields + logic [4:0] imm5; + logic [5:0] imm6; + assign imm5 = operator_i[24:20]; + assign imm6 = {operator_i[24:20], operator_i[25]}; + + // Internal control signals + logic cmp_signed; // comparator operation is signed + enum logic [1:0] { + None, Reg, Zero, ClipBound + } cmp_op_b_sel; // selection of shared comparator operands + logic clip_unsigned; // clip operation has "0" as lower bound + logic clip_register; // if 1 clip operation uses rs2, else imm5 + enum logic [1:0] { + NoMul, MulLow, MulHigh, MulMac + } mul_op; // type of multiplication operation + logic mac_msu; // multiplication operation is MSU + logic mul_op_a_sign; // sign of multiplier operand a + logic mac_op_b_sign; // sign of multiplier operand b + enum logic [3:0] { + Nop, Abs, Sle, Min, Max, Exths, Exthz, Extbs, Extbz, Clip, Mac, Simd + } res_sel; // result selection + + enum logic [4:0] { + SimdNop, SimdAdd, SimdSub, SimdAvg, SimdMin, SimdMax, SimdSrl, SimdSra, SimdSll, SimdOr, + SimdXor, SimdAnd, SimdAbs, SimdExt, SimdIns, SimdDotp, SimdShuffle + } simd_op; // SIMD operation + enum logic { + HalfWord, Byte + } simd_size; // SIMD granularity + enum logic [1:0] { + Vect, Sc, Sci + } simd_mode; // SIMD mode + logic simd_signed; // SIMD operation is signed and uses sign-extended imm6 + logic simd_dotp_op_a_signed; // signedness of SIMD dotp operand a + logic simd_dotp_op_b_signed; // signedness of SIMD dotp operand b + logic simd_dotp_acc; // accumulate result of SIMD dotp on destination reg + + // -------------------- + // Decoder + // -------------------- + + always_comb begin + cmp_signed = 1'b1; + cmp_op_b_sel = None; + clip_unsigned = 1'b0; + clip_register = 1'b0; + mul_op = NoMul; + mac_msu = 1'b0; + mul_op_a_sign = 1'b0; + mac_op_b_sign = 1'b0; + res_sel = Nop; + simd_op = SimdNop; + simd_size = HalfWord; + simd_mode = Vect; + simd_signed = 1; + simd_dotp_op_a_signed = 1; + simd_dotp_op_b_signed = 1; + simd_dotp_acc = 0; + unique casez (operator_i) + // Multiplications from M extension + riscv_instr::MUL: begin + mul_op = MulLow; + mul_op_a_sign = 1'b1; + mac_op_b_sign = 1'b1; + res_sel = Mac; + end + riscv_instr::MULH: begin + mul_op = MulHigh; + mul_op_a_sign = 1'b1; + mac_op_b_sign = 1'b1; + res_sel = Mac; + end + riscv_instr::MULHSU: begin + mul_op = MulHigh; + mul_op_a_sign = 1'b1; + res_sel = Mac; + end + riscv_instr::MULHU: begin + mul_op = MulHigh; + res_sel = Mac; + end + // Instructions from Xpulpimg + riscv_instr::P_ABS: begin + cmp_op_b_sel = Zero; + res_sel = Abs; + end + riscv_instr::P_SLET: begin + cmp_op_b_sel = Reg; + res_sel = Sle; + end + riscv_instr::P_SLETU: begin + cmp_signed = 1'b0; + cmp_op_b_sel = Reg; + res_sel = Sle; + end + riscv_instr::P_MIN: begin + cmp_op_b_sel = Reg; + res_sel = Min; + end + riscv_instr::P_MINU: begin + cmp_signed = 1'b0; + cmp_op_b_sel = Reg; + res_sel = Min; + end + riscv_instr::P_MAX: begin + cmp_op_b_sel = Reg; + res_sel = Max; + end + riscv_instr::P_MAXU: begin + cmp_signed = 1'b0; + cmp_op_b_sel = Reg; + res_sel = Max; + end + riscv_instr::P_EXTHS: begin + cmp_op_b_sel = Reg; + res_sel = Exths; + end + riscv_instr::P_EXTHZ: begin + cmp_op_b_sel = Reg; + res_sel = Exthz; + end + riscv_instr::P_EXTBS: begin + cmp_op_b_sel = Reg; + res_sel = Extbs; + end + riscv_instr::P_EXTBZ: begin + cmp_op_b_sel = Reg; + res_sel = Extbz; + end + riscv_instr::P_CLIP: begin + cmp_op_b_sel = ClipBound; + res_sel = Clip; + end + riscv_instr::P_CLIPU: begin + clip_unsigned = 1'b1; + cmp_op_b_sel = ClipBound; + res_sel = Clip; + end + riscv_instr::P_CLIPR: begin + clip_register = 1'b1; + cmp_op_b_sel = ClipBound; + res_sel = Clip; + end + riscv_instr::P_CLIPUR: begin + clip_unsigned = 1'b1; + clip_register = 1'b1; + cmp_op_b_sel = ClipBound; + res_sel = Clip; + end + riscv_instr::P_MAC: begin + mul_op = MulMac; + mul_op_a_sign = 1'b1; + mac_op_b_sign = 1'b1; + res_sel = Mac; + end + riscv_instr::P_MSU: begin + mul_op = MulMac; + mac_msu = 1'b1; + mul_op_a_sign = 1'b1; + mac_op_b_sign = 1'b1; + res_sel = Mac; + end + riscv_instr::PV_ADD_H: begin + simd_op = SimdAdd; + res_sel = Simd; + end + riscv_instr::PV_ADD_SC_H: begin + simd_op = SimdAdd; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_ADD_SCI_H: begin + simd_op = SimdAdd; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_ADD_B: begin + simd_op = SimdAdd; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_ADD_SC_B: begin + simd_op = SimdAdd; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_ADD_SCI_B: begin + simd_op = SimdAdd; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SUB_H: begin + simd_op = SimdSub; + res_sel = Simd; + end + riscv_instr::PV_SUB_SC_H: begin + simd_op = SimdSub; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SUB_SCI_H: begin + simd_op = SimdSub; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SUB_B: begin + simd_op = SimdSub; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_SUB_SC_B: begin + simd_op = SimdSub; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SUB_SCI_B: begin + simd_op = SimdSub; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_AVG_H: begin + simd_op = SimdAvg; + res_sel = Simd; + end + riscv_instr::PV_AVG_SC_H: begin + simd_op = SimdAvg; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_AVG_SCI_H: begin + simd_op = SimdAvg; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_AVG_B: begin + simd_op = SimdAvg; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_AVG_SC_B: begin + simd_op = SimdAvg; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_AVG_SCI_B: begin + simd_op = SimdAvg; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_AVGU_H: begin + simd_op = SimdAvg; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_AVGU_SC_H: begin + simd_op = SimdAvg; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_AVGU_SCI_H: begin + simd_op = SimdAvg; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_AVGU_B: begin + simd_op = SimdAvg; + simd_size = Byte; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_AVGU_SC_B: begin + simd_op = SimdAvg; + simd_size = Byte; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_AVGU_SCI_B: begin + simd_op = SimdAvg; + simd_size = Byte; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MIN_H: begin + simd_op = SimdMin; + res_sel = Simd; + end + riscv_instr::PV_MIN_SC_H: begin + simd_op = SimdMin; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_MIN_SCI_H: begin + simd_op = SimdMin; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_MIN_B: begin + simd_op = SimdMin; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_MIN_SC_B: begin + simd_op = SimdMin; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_MIN_SCI_B: begin + simd_op = SimdMin; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_MINU_H: begin + simd_op = SimdMin; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MINU_SC_H: begin + simd_op = SimdMin; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MINU_SCI_H: begin + simd_op = SimdMin; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MINU_B: begin + simd_op = SimdMin; + simd_size = Byte; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MINU_SC_B: begin + simd_op = SimdMin; + simd_size = Byte; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MINU_SCI_B: begin + simd_op = SimdMin; + simd_size = Byte; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAX_H: begin + simd_op = SimdMax; + res_sel = Simd; + end + riscv_instr::PV_MAX_SC_H: begin + simd_op = SimdMax; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_MAX_SCI_H: begin + simd_op = SimdMax; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_MAX_B: begin + simd_op = SimdMax; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_MAX_SC_B: begin + simd_op = SimdMax; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_MAX_SCI_B: begin + simd_op = SimdMax; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_MAXU_H: begin + simd_op = SimdMax; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAXU_SC_H: begin + simd_op = SimdMax; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAXU_SCI_H: begin + simd_op = SimdMax; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAXU_B: begin + simd_op = SimdMax; + simd_size = Byte; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAXU_SC_B: begin + simd_op = SimdMax; + simd_size = Byte; + simd_mode = Sc; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_MAXU_SCI_B: begin + simd_op = SimdMax; + simd_size = Byte; + simd_mode = Sci; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_SRL_H: begin + simd_op = SimdSrl; + res_sel = Simd; + end + riscv_instr::PV_SRL_SC_H: begin + simd_op = SimdSrl; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SRL_SCI_H: begin + simd_op = SimdSrl; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SRL_B: begin + simd_op = SimdSrl; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_SRL_SC_B: begin + simd_op = SimdSrl; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SRL_SCI_B: begin + simd_op = SimdSrl; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SRA_H: begin + simd_op = SimdSra; + res_sel = Simd; + end + riscv_instr::PV_SRA_SC_H: begin + simd_op = SimdSra; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SRA_SCI_H: begin + simd_op = SimdSra; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SRA_B: begin + simd_op = SimdSra; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_SRA_SC_B: begin + simd_op = SimdSra; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SRA_SCI_B: begin + simd_op = SimdSra; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SLL_H: begin + simd_op = SimdSll; + res_sel = Simd; + end + riscv_instr::PV_SLL_SC_H: begin + simd_op = SimdSll; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SLL_SCI_H: begin + simd_op = SimdSll; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SLL_B: begin + simd_op = SimdSll; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_SLL_SC_B: begin + simd_op = SimdSll; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_SLL_SCI_B: begin + simd_op = SimdSll; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_OR_H: begin + simd_op = SimdOr; + res_sel = Simd; + end + riscv_instr::PV_OR_SC_H: begin + simd_op = SimdOr; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_OR_SCI_H: begin + simd_op = SimdOr; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_OR_B: begin + simd_op = SimdOr; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_OR_SC_B: begin + simd_op = SimdOr; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_OR_SCI_B: begin + simd_op = SimdOr; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_XOR_H: begin + simd_op = SimdXor; + res_sel = Simd; + end + riscv_instr::PV_XOR_SC_H: begin + simd_op = SimdXor; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_XOR_SCI_H: begin + simd_op = SimdXor; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_XOR_B: begin + simd_op = SimdXor; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_XOR_SC_B: begin + simd_op = SimdXor; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_XOR_SCI_B: begin + simd_op = SimdXor; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_AND_H: begin + simd_op = SimdAnd; + res_sel = Simd; + end + riscv_instr::PV_AND_SC_H: begin + simd_op = SimdAnd; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_AND_SCI_H: begin + simd_op = SimdAnd; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_AND_B: begin + simd_op = SimdAnd; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_AND_SC_B: begin + simd_op = SimdAnd; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_AND_SCI_B: begin + simd_op = SimdAnd; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_ABS_H: begin + simd_op = SimdAbs; + res_sel = Simd; + end + riscv_instr::PV_ABS_B: begin + simd_op = SimdAbs; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_EXTRACT_H: begin + simd_op = SimdExt; + res_sel = Simd; + end + riscv_instr::PV_EXTRACT_B: begin + simd_op = SimdExt; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_EXTRACTU_H: begin + simd_op = SimdExt; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_EXTRACTU_B: begin + simd_op = SimdExt; + simd_size = Byte; + simd_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_INSERT_H: begin + simd_op = SimdIns; + res_sel = Simd; + end + riscv_instr::PV_INSERT_B: begin + simd_op = SimdIns; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_H: begin + simd_op = SimdDotp; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_H: begin + simd_op = SimdDotp; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTUSP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + simd_dotp_op_a_signed = 0; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_H: begin + simd_op = SimdDotp; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + res_sel = Simd; + end + riscv_instr::PV_DOTSP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_H: begin + simd_op = SimdDotp; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + simd_signed = 0; + simd_dotp_op_a_signed = 0; + simd_dotp_op_b_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_H: begin + simd_op = SimdDotp; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTUSP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + simd_dotp_op_a_signed = 0; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_H: begin + simd_op = SimdDotp; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_SC_H: begin + simd_op = SimdDotp; + simd_mode = Sc; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_SCI_H: begin + simd_op = SimdDotp; + simd_mode = Sci; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_SC_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sc; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SDOTSP_SCI_B: begin + simd_op = SimdDotp; + simd_size = Byte; + simd_mode = Sci; + simd_dotp_acc = 1; + res_sel = Simd; + end + riscv_instr::PV_SHUFFLE2_H: begin + simd_op = SimdShuffle; + res_sel = Simd; + end + riscv_instr::PV_SHUFFLE2_B: begin + simd_op = SimdShuffle; + simd_size = Byte; + res_sel = Simd; + end + default: ; + endcase + end + + // ___ _ _____ _ ___ _ _____ _ _ + // | \ /_\|_ _|/_\ | _ \ /_\|_ _|| || | + // | |) |/ _ \ | | / _ \ | _// _ \ | | | __ | + // |___//_/ \_\|_|/_/ \_\|_| /_/ \_\|_| |_||_| + // + + // -------------------- + // Clips + // -------------------- + logic clip_use_n_bound; + logic [Width-1:0] clip_op_b_n, clip_op_b; // clip lower and upper bounds + logic [Width-1:0] clip_lower; + logic [Width-1:0] clip_comp; + + // Generate -2^(imm5-1), 2^(imm5-1)-1 for clip/clipu and -rs2-1, rs2 for clipr, clipur + assign clip_lower = ({(Width+1){1'b1}} << $unsigned(imm5)) >> 1; + assign clip_op_b_n = clip_unsigned ? 'b0 : (clip_register ? ~op_b_i : clip_lower); + assign clip_op_b = clip_register ? op_b_i : ~clip_lower; + + // is 1 when NOT(rs1 >= 0 AND clip_op_b >= 0), i.e. at least one operand is negative + assign clip_use_n_bound = op_a_i[Width-1] | clip_op_b[Width-1]; + + // Select operand to use in comparison for clip operations: clips would need two comparisons + // to clamp the result between the two bounds; but one comparison is enough if we select the + // second operand basing on op_a and clip_op_b signs (i.e. rs1 and clip upper bound, being + // either rs2 or 2^(imm5-1)-1) + assign clip_comp = clip_use_n_bound ? clip_op_b_n : clip_op_b; + + // -------------------- + // Shared comparator + // -------------------- + logic [Width-1:0] cmp_op_a, cmp_op_b; + logic cmp_result; + + // Comparator operand A assignment + assign cmp_op_a = op_a_i; + // Comparator operand B assignment + always_comb begin + unique case (cmp_op_b_sel) + Reg: cmp_op_b = op_b_i; + Zero: cmp_op_b = '0; + ClipBound: cmp_op_b = clip_comp; + default: cmp_op_b = '0; + endcase + end + + // Instantiate comparator + assign cmp_result = $signed({cmp_op_a[Width-1] & cmp_signed, cmp_op_a}) <= $signed({cmp_op_b[Width-1] & cmp_signed, cmp_op_b}); + + // -------------------- + // Multiplier & acc + // -------------------- + + // 32x32 into 32 bits multiplier & accumulator + logic [Width-1:0] mul_op_a; + logic [2*Width-1:0] mul_result; + logic [Width-1:0] mac_result; + + assign mul_op_a = mac_msu ? -op_a_i : op_a_i; // op_a_i is sign-inverted if mac_msu=1, to have -op_a*op_b + + // 32-bits input, 64-bits output multiplier + assign mul_result = $signed({mul_op_a[Width-1] & mul_op_a_sign, mul_op_a}) * $signed({op_b_i[Width-1] & mac_op_b_sign, op_b_i}); + + always_comb begin + unique case (mul_op) + MulLow: mac_result = mul_result[Width-1:0]; // mul, take lowest 32 bits + MulHigh: mac_result = mul_result[2*Width-1:Width]; // mul high, take highest 32 bits + MulMac: mac_result = op_c_i + mul_result[Width-1:0]; // accumulate + default: mac_result = '0; + endcase + end + + // -------------------- + // SIMD operations + // -------------------- + + logic [3:0][7:0] simd_op_a, simd_op_b, simd_op_c; + logic [1:0][7:0] simd_imm; + logic [3:0][7:0] simd_result; + + // half-word and byte immediate extensions + always_comb + if(simd_signed) simd_imm = $signed(imm6); + else simd_imm = $unsigned(imm6); + + // SIMD operands composition + always_comb begin + simd_op_a = 'b0; + simd_op_b = 'b0; + simd_op_c = 'b0; + unique case (simd_size) + // half-word granularity + HalfWord: + for (int i = 0; i < Width/16; i++) begin + simd_op_a[2*i +: 2] = op_a_i[16*i +: 16]; // operands A are the half-words of op_a_i + // operands B are the half-words of op_b_i, replicated lowest half-word of op_b_i or replicated 6-bit immediate + simd_op_b[2*i +: 2] = (simd_mode == Vect) ? op_b_i[16*i +: 16] : ((simd_mode == Sc) ? op_b_i[15:0] : simd_imm); + simd_op_c[2*i +: 2] = op_c_i[16*i +: 16]; // operands C are the half-words of op_c_i + end + // byte granularity + Byte: + for (int i = 0; i < Width/8; i++) begin + simd_op_a[i] = op_a_i[8*i +: 8]; // operands A are the bytes of op_a_i + // operands B are the bytes of op_b_i, replicated lowest byte of op_b_i or replicated 6-bit immediate + simd_op_b[i] = (simd_mode == Vect) ? op_b_i[8*i +: 8] : ((simd_mode == Sc) ? op_b_i[7:0] : simd_imm[0]); + simd_op_c[i] = op_c_i[8*i +: 8]; // operands C are the bytes of op_c_i + end + default: ; + endcase + end + + // SIMD unit + always_comb begin + simd_result = 'b0; + unique case (simd_size) + // half-word granularity + HalfWord: begin + unique case (simd_op) + SimdAdd: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed(simd_op_a[2*i +: 2]) + $signed(simd_op_b[2*i +: 2]); + SimdSub: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed(simd_op_a[2*i +: 2]) - $signed(simd_op_b[2*i +: 2]); + SimdAvg: + for (int i = 0; i < Width/16; i++) begin + simd_result[2*i +: 2] = $signed(simd_op_a[2*i +: 2]) + $signed(simd_op_b[2*i +: 2]); + simd_result[2*i +: 2] = {simd_result[2*i+1][7] & simd_signed, simd_result[2*i +: 2]} >> 1; + end + SimdMin: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed({simd_op_a[2*i+1][7] & simd_signed, simd_op_a[2*i +: 2]}) <= + $signed({simd_op_b[2*i+1][7] & simd_signed, simd_op_b[2*i +: 2]}) ? + simd_op_a[2*i +: 2] : simd_op_b[2*i +: 2]; + SimdMax: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed({simd_op_a[2*i+1][7] & simd_signed, simd_op_a[2*i +: 2]}) > + $signed({simd_op_b[2*i+1][7] & simd_signed, simd_op_b[2*i +: 2]}) ? + simd_op_a[2*i +: 2] : simd_op_b[2*i +: 2]; + SimdSrl: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $unsigned(simd_op_a[2*i +: 2]) >> simd_op_b[2*i][3:0]; + SimdSra: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed(simd_op_a[2*i +: 2]) >>> simd_op_b[2*i][3:0]; + SimdSll: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $unsigned(simd_op_a[2*i +: 2]) << simd_op_b[2*i][3:0]; + SimdOr: simd_result = simd_op_a | simd_op_b; + SimdXor: simd_result = simd_op_a ^ simd_op_b; + SimdAnd: simd_result = simd_op_a & simd_op_b; + SimdAbs: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = $signed(simd_op_a[2*i +: 2]) > 0 ? simd_op_a[2*i +: 2] : -$signed(simd_op_a[2*i +: 2]); + SimdExt: begin + simd_result[1:0] = simd_op_a[2*imm6[0] +: 2]; + // sign- or zero-extend + simd_result[3:2] = {16{simd_op_a[2*imm6[0]+1][7] & simd_signed}}; + end + SimdIns: begin + simd_result = op_c_i; + simd_result[2*imm6[0] +: 2] = simd_op_a[1:0]; + end + SimdDotp: begin + simd_result = op_c_i & {(Width){simd_dotp_acc}}; // accumulate on rd or start from zero + for (int i = 0; i < Width/16; i++) begin + simd_result = $signed(simd_result) + $signed({simd_op_a[2*i+1][7] & simd_dotp_op_a_signed, simd_op_a[2*i +: 2]}) * + $signed({simd_op_b[2*i+1][7] & simd_dotp_op_b_signed, simd_op_b[2*i +: 2]}); + end + end + SimdShuffle: + for (int i = 0; i < Width/16; i++) + simd_result[2*i +: 2] = simd_op_b[2*i][1] ? simd_op_a[2*simd_op_b[2*i][0] +: 2] : simd_op_c[2*simd_op_b[2*i][0] +: 2]; + default: ; + endcase + end + // byte granularity + Byte: begin + unique case (simd_op) + SimdAdd: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed(simd_op_a[i]) + $signed(simd_op_b[i]); + SimdSub: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed(simd_op_a[i]) - $signed(simd_op_b[i]); + SimdAvg: + for (int i = 0; i < Width/8; i++) begin + simd_result[i] = $signed(simd_op_a[i]) + $signed(simd_op_b[i]); + simd_result[i] = {simd_result[i][7] & simd_signed, simd_result[i]} >> 1; + end + SimdMin: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed({simd_op_a[i][7] & simd_signed, simd_op_a[i]}) <= + $signed({simd_op_b[i][7] & simd_signed, simd_op_b[i]}) ? + simd_op_a[i] : simd_op_b[i]; + SimdMax: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed({simd_op_a[i][7] & simd_signed, simd_op_a[i]}) > + $signed({simd_op_b[i][7] & simd_signed, simd_op_b[i]}) ? + simd_op_a[i] : simd_op_b[i]; + SimdSrl: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $unsigned(simd_op_a[i]) >> simd_op_b[i][2:0]; + SimdSra: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed(simd_op_a[i]) >>> simd_op_b[i][2:0]; + SimdSll: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $unsigned(simd_op_a[i]) << simd_op_b[i][2:0]; + SimdOr: simd_result = simd_op_a | simd_op_b; + SimdXor: simd_result = simd_op_a ^ simd_op_b; + SimdAnd: simd_result = simd_op_a & simd_op_b; + SimdAbs: + for (int i = 0; i < Width/8; i++) + simd_result[i] = $signed(simd_op_a[i]) > 0 ? simd_op_a[i] : -$signed(simd_op_a[i]); + SimdExt: begin + simd_result[0] = simd_op_a[imm6[1:0]]; + // sign- or zero-extend + simd_result[3:1] = {24{simd_op_a[imm6[1:0]][7] & simd_signed}}; + end + SimdIns: begin + simd_result = op_c_i; + simd_result[imm6[1:0]] = simd_op_a[0]; + end + SimdDotp: begin + simd_result = op_c_i & {(Width){simd_dotp_acc}}; // accumulate on rd or start from zero + for (int i = 0; i < Width/8; i++) + simd_result = $signed(simd_result) + $signed({simd_op_a[i][7] & simd_dotp_op_a_signed, simd_op_a[i]}) * + $signed({simd_op_b[i][7] & simd_dotp_op_b_signed, simd_op_b[i]}); + end + SimdShuffle: + for (int i = 0; i < Width/8; i++) + simd_result[i] = simd_op_b[i][2] ? simd_op_a[simd_op_b[i][1:0]] : simd_op_c[simd_op_b[i][1:0]]; + default: ; + endcase + end + default: ; + endcase + end + + // -------------------- + // Result generation + // -------------------- + + always_comb begin + unique case (res_sel) + Abs: result_o = cmp_result ? -$signed(op_a_i) : op_a_i; + Sle: result_o = $unsigned(cmp_result); + Min: result_o = cmp_result ? op_a_i : op_b_i; + Max: result_o = ~cmp_result ? op_a_i : op_b_i; + Exths: result_o = $signed(op_a_i[15:0]); + Exthz: result_o = $unsigned(op_a_i[15:0]); + Extbs: result_o = $signed(op_a_i[7:0]); + Extbz: result_o = $unsigned(op_a_i[7:0]); + // Select the clip output basing on the result of the comparison and on the signs of the operands: + // - if rs1 <= clip_comp (i.e. cmp_result = 1) + // * if clip_comp=clip_op_b_n (i.e. rs1<0 or clip_op_b<0): rs1 is below the lower boundand since + // this check has priority over the others, result_o is clipped to clip_op_b_n + // * if clip_comp=clip_op_b (i.e. rs1>=0 and clip_op_b>=0): since rs1<=clip_op_b, then it is + // clip_op_b_n < 0 <= rs1 <= clip_op_b thus rs1 is already within the clip bounds + // - if rs1 > clip_comp (i.e. cmp_result = 0) + // * if rs1 < 0: clip_comp=clip_op_b_n because clip_use_n_bound=1; since rs1>clip_op_b_n and + // rs1<0 it is clip_op_b_n < rs1 < 0 <= clip_op_b, thus rs1 is already within the clip bounds + // * if rs1 >= 0: then clip_comp might be clip_op_b_n or clip_op_b basing on clip_op_b sign; + // + if clip_op_b < 0: clip_comp=clip_op_b_n, so rs1>clip_op_b_n but also rs1 >= 0, so it is + // clip_op_b < 0 <= clip_op_n <= rs1; then rs1 is not <= clip_ob_n but it is >= clip_op_b, + // so result_o is clipped to clip_op_b + // + if clip_op_b >= 0: clip_comp=clip_op_b (i.e. rs1>=0 and clip_op_b>=0) and the result must + // be clipped to the upper bound since rs1 > clip_op_b + Clip: result_o = cmp_result ? (clip_use_n_bound ? clip_op_b_n : op_a_i) : (op_a_i[Width-1] ? op_a_i : clip_op_b); + Mac: result_o = mac_result; + Simd: result_o = simd_result; + default: result_o = '0; + endcase + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_lsu.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_lsu.sv new file mode 100644 index 0000000000..a961f437b2 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_lsu.sv @@ -0,0 +1,223 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Florian Zaruba +// Description: Load Store Unit (can handle `NumOutstandingLoads` outstanding loads) and +// optionally NaNBox if used in a floating-point setting. +// It supports out-of-order memory responses via metadata linking with IDs. + +module snitch_lsu + import cf_math_pkg::idx_width; +#( + parameter type tag_t = logic [4:0], + parameter int unsigned NumOutstandingLoads = 1, + parameter bit NaNBox = 0, + // Dependent parameters. DO NOT CHANGE. + localparam int unsigned IdWidth = idx_width(NumOutstandingLoads) +) ( + input logic clk_i, + input logic rst_i, + // request channel + input tag_t lsu_qtag_i, + input logic lsu_qwrite, + input logic lsu_qsigned, + input logic [31:0] lsu_qaddr_i, + input logic [31:0] lsu_qdata_i, + input logic [1:0] lsu_qsize_i, + input logic [3:0] lsu_qamo_i, + input logic lsu_qvalid_i, + output logic lsu_qready_o, + // response channel + output logic [31:0] lsu_pdata_o, + output tag_t lsu_ptag_o, + output logic lsu_perror_o, + output logic lsu_pvalid_o, + input logic lsu_pready_i, + // Memory Interface Channel + output logic [31:0] data_qaddr_o, + output logic data_qwrite_o, + output logic [3:0] data_qamo_o, + output logic [31:0] data_qdata_o, + output logic [3:0] data_qstrb_o, + output logic [IdWidth-1:0] data_qid_o, + output logic data_qvalid_o, + input logic data_qready_i, + input logic [31:0] data_pdata_i, + input logic data_perror_i, + input logic [IdWidth-1:0] data_pid_i, + input logic data_pvalid_i, + output logic data_pready_o +); + + // ---------------- + // TYPEDEFS + // ---------------- + + typedef logic [IdWidth-1:0] meta_id_t; + + typedef struct packed { + tag_t tag; + logic sign_ext; + logic [1:0] offset; + logic [1:0] size; + } metadata_t; + + // ---------------- + // SIGNALS + // ---------------- + + // ID Table + logic [NumOutstandingLoads-1:0] id_available_d, id_available_q; + metadata_t [NumOutstandingLoads-1:0] metadata_d, metadata_q; + metadata_t req_metadata; + metadata_t resp_metadata; + meta_id_t req_id; + meta_id_t resp_id; + logic id_table_push; + logic id_table_pop; + logic id_table_full; + + // Response + logic [31:0] ld_result; + + // ---------------- + // ID TABLE + // ---------------- + // Track ID availability and store metadata + always_comb begin + // Default + id_available_d = id_available_q; + metadata_d = metadata_q; + + // Take ID and store metadata + if (id_table_push) begin + id_available_d[req_id] = 1'b0; + metadata_d[req_id] = req_metadata; + end + + // Free ID + if (id_table_pop) begin + id_available_d[resp_id] = 1'b1; + end + end + + assign req_metadata = '{ + tag: lsu_qtag_i, + sign_ext: lsu_qsigned, + offset: lsu_qaddr_i[1:0], + size: lsu_qsize_i + }; + + assign resp_metadata = metadata_q[resp_id]; + + // Search available ID for request + lzc #( + .WIDTH ( NumOutstandingLoads ) + ) i_req_id ( + .in_i ( id_available_q ), + .cnt_o ( req_id ), + .empty_o( id_table_full ) + ); + + // Pop if response accepted + assign id_table_pop = data_pvalid_i & data_pready_o; + + // Push if load request accepted + assign id_table_push = ~lsu_qwrite & data_qready_i & data_qvalid_o; + + // ---------------- + // REQUEST + // ---------------- + // only make a request when we got a valid request and if it is a load + // also check that we can actually store the necessary information to process + // it in the upcoming cycle(s). + assign data_qvalid_o = (lsu_qvalid_i) & (lsu_qwrite | ~id_table_full); + assign data_qwrite_o = lsu_qwrite; + assign data_qaddr_o = {lsu_qaddr_i[31:2], 2'b0}; + assign data_qamo_o = lsu_qamo_i; + assign data_qid_o = req_id; + // generate byte enable mask + always_comb begin + unique case (lsu_qsize_i) + 2'b00: data_qstrb_o = (4'b1 << lsu_qaddr_i[1:0]); + 2'b01: data_qstrb_o = (4'b11 << lsu_qaddr_i[1:0]); + 2'b10: data_qstrb_o = '1; + default: data_qstrb_o = '0; + endcase + end + + // re-align write data + /* verilator lint_off WIDTH */ + always_comb begin + unique case (lsu_qaddr_i[1:0]) + 2'b00: data_qdata_o = lsu_qdata_i; + 2'b01: data_qdata_o = {lsu_qdata_i[23:0], lsu_qdata_i[31:24]}; + 2'b10: data_qdata_o = {lsu_qdata_i[15:0], lsu_qdata_i[31:16]}; + 2'b11: data_qdata_o = {lsu_qdata_i[ 7:0], lsu_qdata_i[31: 8]}; + default: data_qdata_o = lsu_qdata_i; + endcase + end + /* verilator lint_on WIDTH */ + + // the interface didn't accept our request yet + assign lsu_qready_o = ~(data_qvalid_o & ~data_qready_i) & ~id_table_full; + + // ---------------- + // RESPONSE + // ---------------- + // Return Path + // shift the load data back by offset bytes + logic [31:0] shifted_data; + assign shifted_data = data_pdata_i >> {resp_metadata.offset, 3'b000}; + always_comb begin + unique case (resp_metadata.size) + 2'b00: ld_result = {{24{shifted_data[ 7] & resp_metadata.sign_ext}}, shifted_data[7:0]}; + 2'b01: ld_result = {{16{shifted_data[15] & resp_metadata.sign_ext}}, shifted_data[15:0]}; + 2'b10: ld_result = shifted_data; + default: ld_result = shifted_data; + endcase + end + + assign resp_id = data_pid_i; + assign lsu_perror_o = data_perror_i; + assign lsu_pdata_o = ld_result; + assign lsu_ptag_o = resp_metadata.tag; + assign lsu_pvalid_o = data_pvalid_i; + assign data_pready_o = lsu_pready_i; + + // ---------------- + // SEQUENTIAL + // ---------------- + always_ff @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + id_available_q <= '1; + metadata_q <= 'b0; + end else begin + id_available_q <= id_available_d; + metadata_q <= metadata_d; + end + end + + // ---------------- + // ASSERTIONS + // ---------------- + // Check for unsupported parameters + if (NumOutstandingLoads == 0) + $error(1, "[snitch_lsu] NumOutstandingLoads cannot be 0."); + + // pragma translate_off + `ifndef VERILATOR + invalid_req_id : assert property( + @(posedge clk_i) disable iff (rst_i) (!(id_table_push & ~id_available_q[req_id]))) + else $fatal (1, "Request ID is not available."); + `endif + + `ifndef VERILATOR + invalid_resp_id : assert property( + @(posedge clk_i) disable iff (rst_i) (!(id_table_pop & id_available_q[resp_id]))) + else $fatal (1, "Response ID does not match with valid metadata."); + `endif + // pragma translate_on + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_onehot.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_onehot.sv new file mode 100644 index 0000000000..166079b757 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_onehot.sv @@ -0,0 +1,44 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/// Hardware implementation of SystemVerilog's `$onehot()` function. +/// It uses a tree of half adders and a separate +/// or reduction tree for the carry. + +// Author: Florian Zaruba +// Author: Fabian Schuiki +// Author: Stefan Mach +module onehot #( + parameter int unsigned Width = 4 +) ( + input logic [Width-1:0] d_i, + output logic is_onehot_o +); + // trivial base case + if (Width == 1) begin : gen_degenerated_onehot + assign is_onehot_o = d_i; + end else begin : gen_onehot + localparam int LVLS = $clog2(Width) + 1; + + logic [LVLS-1:0][2**(LVLS-1)-1:0] sum, carry; + logic [LVLS-2:0] carry_array; + + // Extend to a power of two. + assign sum[0] = $unsigned(d_i); + + // generate half adders for each lvl + // lvl 0 is the input level + for (genvar i = 1; i < LVLS; i++) begin + localparam LVL_WIDTH = 2**LVLS / 2**i; + for (genvar j = 0; j < LVL_WIDTH; j+=2) begin + assign sum[i][j/2] = sum[i-1][j] ^ sum[i-1][j+1]; + assign carry[i][j/2] = sum[i-1][j] & sum[i-1][j+1]; + end + // generate carry tree + assign carry_array[i-1] = |carry[i][LVL_WIDTH/2-1:0]; + end + assign is_onehot_o = sum[LVLS-1][0] & ~|carry_array; + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_pkg.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_pkg.sv new file mode 100644 index 0000000000..539b479998 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_pkg.sv @@ -0,0 +1,156 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/// Snitch Configuration. +package snitch_pkg; + + import cf_math_pkg::idx_width; + + localparam DataWidth = 32; + localparam StrbWidth = DataWidth/8; + localparam int NumFPOutstandingLoads = 4; + // Use a high number of outstanding loads, if running a latency-throughput analysis + localparam int NumIntOutstandingLoads = `ifdef TRAFFIC_GEN 2048 `else 8 `endif; + localparam MetaIdWidth = idx_width(NumIntOutstandingLoads); + // Xpulpimg extension enabled? + localparam bit XPULPIMG = `ifdef XPULPIMG `XPULPIMG `else 1'bX `endif; + + typedef logic [31:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [MetaIdWidth-1:0] meta_id_t; + + typedef struct packed { + addr_t BootAddress; + int unsigned NrCores; + } SnitchCfg; + + typedef struct packed { + addr_t addr; + meta_id_t id; + logic [3:0] amo; + logic write; + data_t data; + strb_t strb; + } dreq_t; + + typedef struct packed { + data_t data; + meta_id_t id; + logic error; + } dresp_t; + + typedef struct packed { + addr_t addr; + logic [4:0] id; + logic [31:0] data_op; + data_t data_arga; + data_t data_argb; + data_t data_argc; + } acc_req_t; + + typedef struct packed { + logic [4:0] id; + logic error; + data_t data; + } acc_resp_t; + + // Number of instructions the sequencer can hold + localparam int FPUSequencerInstr = 16; + // SSRs + localparam logic [31:0] SSR_ADDR_BASE = 32'h20_4800; + localparam logic [31:0] SSR_ADDR_MASK = 32'hffff_fe00; + localparam logic [11:0] CSR_SSR = 12'h7C0; + localparam int SSRNrCredits = 4; + // Registers which are used as SSRs + localparam [4:0] FT0 = 5'b0; + localparam [4:0] FT1 = 5'b1; + localparam [1:0][4:0] SSRRegs = {FT1, FT0}; + function automatic logic is_ssr(logic [4:0] register); + unique case (register) + FT0, FT1: return 1'b1; + default : return 0; + endcase + endfunction + + // Amount of address bit which should be used for accesses from the SoC side. + // This effectively determines the Address Space of a Snitch Cluster. + localparam logic [31:0] SoCRequestAddrBits = 32; + + // Address Map + // TCDM, everything below 0x4000_0000 + localparam logic [31:0] TCDMStartAddress = 32'h0000_0000; + localparam logic [31:0] TCDMMask = '1 << 28; + + // Slaves on Cluster AXI Bus + typedef enum integer { + TCDM = 0, + ClusterPeripherals = 1, + SoC = 2 + } cluster_slave_e; + + typedef enum integer { + CoreReq = 0, + ICache = 1, + AXISoC = 2 + } cluster_master_e; + + localparam int unsigned NrSlaves = 3; + localparam int unsigned NrMasters = 3; + + localparam int IdWidth = 2; + localparam int IdWidthSlave = $clog2(NrMasters) + IdWidth; + + // 3. SoC 2. Cluster Peripherals 3. TCDM + localparam logic [NrSlaves-1:0][31:0] StartAddress = {32'h8000_0000, 32'h4000_0000, TCDMStartAddress}; + localparam logic [NrSlaves-1:0][31:0] EndAddress = {32'hFFFF_FFFF, 32'h5000_0000, TCDMStartAddress + 32'h1000_0000}; + localparam logic [NrSlaves-1:0] ValidRule = {{NrSlaves}{1'b1}}; + + // Cluster Peripheral Registers + typedef enum logic [31:0] { + TCDMStartAddressReg = 32'h4000_0000, + TCDMEndAddressReg = 32'h4000_0008, + NrCoresReg = 32'h4000_0010, + FetchEnableReg = 32'h4000_0018, + ScratchReg = 32'h4000_0020, + WakeUpReg = 32'h4000_0028, + CycleCountReg = 32'h4000_0030, + BarrierReg = 32'h4000_0038, + TcdmAccessedReg = 32'h4000_FFF0, + TcdmCongestedReg = 32'h4000_FFF8, + PerfCounterBase = 32'h4001_0000 + } cluster_peripheral_addr_e; + + // Offload to shared accelerator + function automatic logic shared_offload (logic [31:0] instr); + logic offload; + unique casez (instr) + riscv_instr::MUL, + riscv_instr::MULH, + riscv_instr::MULHSU, + riscv_instr::MULHU, + riscv_instr::DIV, + riscv_instr::DIVU, + riscv_instr::REM, + riscv_instr::REMU, + riscv_instr::MULW, + riscv_instr::DIVW, + riscv_instr::DIVUW, + riscv_instr::REMW, + riscv_instr::REMUW: offload = 1; + default: offload = 0; + endcase + return offload; + endfunction + + // Event strobes per core, counted by the performance counters in the cluster + // peripherals. + typedef struct packed { + logic issue_fpu; // core operations performed in the FPU + logic issue_fpu_seq; // includes load/store operations + logic issue_core_to_fpu; // instructions issued from core to FPU + logic retired_insts; // number of instructions retired by the core + } core_events_t; + +endpackage diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_regfile_ff.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_regfile_ff.sv new file mode 100644 index 0000000000..8c77011301 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_regfile_ff.sv @@ -0,0 +1,58 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Florian Zaruba +// Description: Variable Register File +module snitch_regfile #( + parameter DATA_WIDTH = 32, + parameter NR_READ_PORTS = 2, + parameter NR_WRITE_PORTS = 1, + parameter ZERO_REG_ZERO = 0, + parameter ADDR_WIDTH = 4 +) ( + // clock and reset + input logic clk_i, + // read port + input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, + output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + // write port + input logic [NR_WRITE_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i, + input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, + input logic [NR_WRITE_PORTS-1:0] we_i +); + + localparam NUM_WORDS = 2**ADDR_WIDTH; + + logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem; + logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:0] we_dec; + + + always_comb begin : we_decoder + for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned i = 0; i < NUM_WORDS; i++) begin + if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; + else we_dec[j][i] = 1'b0; + end + end + end + + // loop from 1 to NUM_WORDS-1 as R0 is nil + always_ff @(posedge clk_i) begin : register_write_behavioral + for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned i = 0; i < NUM_WORDS; i++) begin + if (we_dec[j][i]) begin + mem[i] <= wdata_i[j]; + end + end + if (ZERO_REG_ZERO) begin + mem[0] <= '0; + end + end + end + + for (genvar i = 0; i < NR_READ_PORTS; i++) begin + assign rdata_o[i] = mem[raddr_i[i]]; + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_shared_muldiv.sv b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_shared_muldiv.sv new file mode 100644 index 0000000000..ac51df97b8 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_shared_muldiv.sv @@ -0,0 +1,441 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/// Shared Multiply/Divide a.k.a M Extension +/// Based on Ariane Multiply Divide +/// Author: Michael Schaffner, +/// Author: Florian Zaruba , + +module snitch_shared_muldiv #( + parameter int unsigned IdWidth = 5 +) ( + input logic clk_i, + input logic rst_i, + // Accelerator Interface - Slave + input logic [31:0] acc_qaddr_i, // unused + input logic [IdWidth-1:0] acc_qid_i, + input logic [31:0] acc_qdata_op_i, // RISC-V instruction + input logic [31:0] acc_qdata_arga_i, + input logic [31:0] acc_qdata_argb_i, + input logic [31:0] acc_qdata_argc_i, + input logic acc_qvalid_i, + output logic acc_qready_o, + output logic [31:0] acc_pdata_o, + output logic [IdWidth-1:0] acc_pid_o, + output logic acc_perror_o, + output logic acc_pvalid_o, + input logic acc_pready_i +); + `include "common_cells/registers.svh" + + typedef struct packed { + logic [31:0] result; + logic [IdWidth-1:0] id; + } result_t; + // input handshake + logic div_valid_op, div_ready_op; + logic mul_valid_op, mul_ready_op; + // output handshake + logic mul_valid, mul_ready; + logic div_valid, div_ready; + result_t div, mul, oup; + logic illegal_instruction; + + always_comb begin + mul_valid_op = 1'b0; + div_valid_op = 1'b0; + acc_qready_o = 1'b0; + acc_perror_o = 1'b0; + illegal_instruction = 1'b0; + unique casez (acc_qdata_op_i) + riscv_instr::MUL, + riscv_instr::MULH, + riscv_instr::MULHSU, + riscv_instr::MULHU: begin + mul_valid_op = acc_qvalid_i; + acc_qready_o = mul_ready_op; + end + riscv_instr::DIV, + riscv_instr::DIVU, + riscv_instr::REM, + riscv_instr::REMU: begin + div_valid_op = acc_qvalid_i; + acc_qready_o = div_ready_op; + end + default: illegal_instruction = 1'b1; + endcase + end + + // Multiplication + multiplier #( + .Width ( 32 ), + .IdWidth ( IdWidth ) + ) i_multiplier ( + .clk_i, + .rst_i, + .id_i ( acc_qid_i ), + .operator_i ( acc_qdata_op_i ), + .operand_a_i ( acc_qdata_arga_i ), + .operand_b_i ( acc_qdata_argb_i ), + .valid_i ( mul_valid_op ), + .ready_o ( mul_ready_op ), + .result_o ( mul.result ), + .valid_o ( mul_valid ), + .ready_i ( mul_ready ), + .id_o ( mul.id ) + ); + // Serial Divider + serdiv #( + .WIDTH ( 32 ), + .IdWidth ( IdWidth ) + ) i_div ( + .clk_i ( clk_i ), + .rst_ni ( ~rst_i ), + .id_i ( acc_qid_i ), + .operator_i ( acc_qdata_op_i ), + .op_a_i ( acc_qdata_arga_i ), + .op_b_i ( acc_qdata_argb_i ), + .in_vld_i ( div_valid_op ), + .in_rdy_o ( div_ready_op ), + .out_vld_o ( div_valid ), + .out_rdy_i ( div_ready ), + .id_o ( div.id ), + .res_o ( div.result ) + ); + // Output Arbitration + stream_arbiter #( + .DATA_T ( result_t ), + .N_INP ( 2 ) + ) i_stream_arbiter ( + .clk_i, + .rst_ni ( ~rst_i ), + .inp_data_i ( {div, mul} ), + .inp_valid_i ( {div_valid, mul_valid} ), + .inp_ready_o ( {div_ready, mul_ready} ), + .oup_data_o ( oup ), + .oup_valid_o ( acc_pvalid_o ), + .oup_ready_i ( acc_pready_i ) + ); + assign acc_pdata_o = oup.result; + assign acc_pid_o = oup.id; +endmodule + +module multiplier #( + parameter int unsigned Width = 64, + parameter int unsigned IdWidth = 5 +) ( + input logic clk_i, + input logic rst_i, + input logic [IdWidth-1:0] id_i, + input logic [31:0] operator_i, + input logic [Width-1:0] operand_a_i, + input logic [Width-1:0] operand_b_i, + input logic valid_i, + output logic ready_o, + output logic [Width-1:0] result_o, + output logic valid_o, + input logic ready_i, + output logic [IdWidth-1:0] id_o +); + // Pipeline register + logic [IdWidth-1:0] id_q; + logic valid_d, valid_q; + logic select_upper_q, select_upper_d; + logic [2*Width-1:0] result_d, result_q; + + // control registers + logic sign_a, sign_b; + // control signals + assign ready_o = ~valid_o | ready_i; + // datapath + logic [2*Width-1:0] mult_result; + assign mult_result = $signed({operand_a_i[Width-1] & sign_a, operand_a_i}) * $signed({operand_b_i[Width-1] & sign_b, operand_b_i}); + // Sign Select MUX + always_comb begin + sign_a = 1'b0; + sign_b = 1'b0; + unique casez (operator_i) + riscv_instr::MULH: begin + sign_a = 1'b1; + sign_b = 1'b1; + select_upper_d = 1'b1; + end + riscv_instr::MULHU: begin + select_upper_d = 1'b1; + end + riscv_instr::MULHSU: begin + sign_a = 1'b1; + select_upper_d = 1'b1; + end + // MUL performs an XLEN-bit × XLEN-bit multiplication and places the lower XLEN bits in the destination register + default: begin // including MUL + select_upper_d = 1'b0; + end + endcase + end + // single stage version + assign result_d = $signed({operand_a_i[Width-1] & sign_a, operand_a_i}) * + $signed({operand_b_i[Width-1] & sign_b, operand_b_i}); + // ressult mux + always_comb begin + result_o = result_q[Width-1:0]; + if (select_upper_q) begin + result_o = result_q[2*Width-1:Width]; + end + end + + always_comb begin + valid_d = valid_q; + if (valid_q & ready_i) + valid_d = 0; + if (valid_i & ready_o) + valid_d = 1; + end + `FFAR(valid_q, valid_d, '0, clk_i, rst_i) + // Pipe-line registers + `FFLAR(id_q, id_i, (valid_i & ready_o), '0, clk_i, rst_i) + `FFLAR(result_q, result_d, (valid_i & ready_o), '0, clk_i, rst_i) + `FFLAR(select_upper_q, select_upper_d, (valid_i & ready_o), '0, clk_i, rst_i) + + assign id_o = id_q; + assign valid_o = valid_q; + +endmodule + + +module serdiv #( + parameter WIDTH = 64, + parameter int unsigned IdWidth = 5 +) ( + input logic clk_i, + input logic rst_ni, + // input IF + input logic [IdWidth-1:0] id_i, + input logic [31:0] operator_i, + input logic [WIDTH-1:0] op_a_i, + input logic [WIDTH-1:0] op_b_i, + // handshake + input logic in_vld_i, // there is a cycle delay from in_rdy_o->in_vld_i, see issue_read_operands.sv stage + output logic in_rdy_o, + // output IF + output logic out_vld_o, + input logic out_rdy_i, + output logic [IdWidth-1:0] id_o, + output logic [WIDTH-1:0] res_o +); + + logic signed_op; + logic rem; + + always_comb begin + signed_op = 1'b0; + rem = 1'b0; + unique casez (operator_i) + riscv_instr::DIV: begin + signed_op = 1'b1; + end + riscv_instr::DIVU: begin + end + riscv_instr::REM: begin + signed_op = 1'b1; + rem = 1'b1; + end + riscv_instr::REMU: begin + rem = 1'b1; + end + default:; + endcase + end + + enum logic [1:0] { + IDLE, DIVIDE, FINISH + } state_d, state_q; + + logic [WIDTH-1:0] res_q, res_d; + logic [WIDTH-1:0] op_a_q, op_a_d; + logic [WIDTH-1:0] op_b_q, op_b_d; + logic op_a_sign, op_b_sign; + logic op_b_zero, op_b_zero_q, op_b_zero_d; + + logic [IdWidth-1:0] id_q, id_d; + + logic rem_sel_d, rem_sel_q; + logic comp_inv_d, comp_inv_q; + logic res_inv_d, res_inv_q; + + logic [WIDTH-1:0] add_mux; + logic [WIDTH-1:0] add_out; + logic [WIDTH-1:0] add_tmp; + logic [WIDTH-1:0] b_mux; + logic [WIDTH-1:0] out_mux; + + logic [$clog2(WIDTH+1)-1:0] cnt_q, cnt_d; + logic cnt_zero; + + logic [WIDTH-1:0] lzc_a_input, lzc_b_input, op_b; + logic [$clog2(WIDTH)-1:0] lzc_a_result, lzc_b_result; + logic [$clog2(WIDTH+1)-1:0] shift_a; + logic [$clog2(WIDTH+1):0] div_shift; + + logic a_reg_en, b_reg_en, res_reg_en, ab_comp, pm_sel, load_en; + logic lzc_a_no_one, lzc_b_no_one; + logic div_res_zero_d, div_res_zero_q; + ///////////////////////////////////// + // align the input operands + // for faster division + ///////////////////////////////////// + assign op_b_zero = (op_b_i == 0); + assign op_a_sign = op_a_i[$high(op_a_i)]; + assign op_b_sign = op_b_i[$high(op_b_i)]; + + assign lzc_a_input = (signed_op & op_a_sign) ? {~op_a_i, 1'b0} : op_a_i; + assign lzc_b_input = (signed_op & op_b_sign) ? ~op_b_i : op_b_i; + + lzc #( + .MODE ( 1 ), // count leading zeros + .WIDTH ( WIDTH ) + ) i_lzc_a ( + .in_i ( lzc_a_input ), + .cnt_o ( lzc_a_result ), + .empty_o ( lzc_a_no_one ) + ); + + lzc #( + .MODE ( 1 ), // count leading zeros + .WIDTH ( WIDTH ) + ) i_lzc_b ( + .in_i ( lzc_b_input ), + .cnt_o ( lzc_b_result ), + .empty_o ( lzc_b_no_one ) + ); + + assign shift_a = (lzc_a_no_one) ? WIDTH : lzc_a_result; + assign div_shift = (lzc_b_no_one) ? WIDTH : lzc_b_result-shift_a; + + assign op_b = op_b_i <<< $unsigned(div_shift); + + // the division is zero if |opB| > |opA| and can be terminated + assign div_res_zero_d = (load_en) ? ($signed(div_shift) < 0) : div_res_zero_q; + + ///////////////////////////////////// + // Datapath + ///////////////////////////////////// + + assign pm_sel = load_en & ~(signed_op & (op_a_sign ^ op_b_sign)); + // muxes + assign add_mux = (load_en) ? op_a_i : op_b_q; + // attention: logical shift by one in case of negative operand B! + assign b_mux = (load_en) ? op_b : {comp_inv_q, (op_b_q[$high(op_b_q):1])}; + // in case of bad timing, we could output from regs -> needs a cycle more in the FSM + assign out_mux = (rem_sel_q) ? op_a_q : res_q; + // invert if necessary + assign res_o = (res_inv_q) ? -$signed(out_mux) : out_mux; + // main comparator + assign ab_comp = ((op_a_q == op_b_q) | ((op_a_q > op_b_q) ^ comp_inv_q)) & ((|op_a_q) | op_b_zero_q); + // main adder + assign add_tmp = (load_en) ? 0 : op_a_q; + assign add_out = (pm_sel) ? add_tmp + add_mux : add_tmp - $signed(add_mux); + + ///////////////////////////////////// + // FSM, counter + ///////////////////////////////////// + assign cnt_zero = (cnt_q == 0); + assign cnt_d = (load_en) ? div_shift : + (~cnt_zero) ? cnt_q - 1 : cnt_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + in_rdy_o = 1'b0; + out_vld_o = 1'b0; + load_en = 1'b0; + a_reg_en = 1'b0; + b_reg_en = 1'b0; + res_reg_en = 1'b0; + unique case (state_q) + IDLE: begin + in_rdy_o = 1'b1; + if (in_vld_i) begin + a_reg_en = 1'b1; + b_reg_en = 1'b1; + load_en = 1'b1; + state_d = DIVIDE; + end + end + DIVIDE: begin + if (!div_res_zero_q) begin + a_reg_en = ab_comp; + b_reg_en = 1'b1; + res_reg_en = 1'b1; + end + // can end the division now if the result is clearly 0 + if (div_res_zero_q) begin + out_vld_o = 1'b1; + state_d = FINISH; + if (out_rdy_i) begin + state_d = IDLE; + end + end else if (cnt_zero) begin + state_d = FINISH; + end + end + FINISH: begin + out_vld_o = 1'b1; + + if (out_rdy_i) begin + state_d = IDLE; + end + end + default : state_d = IDLE; + endcase + end + + ///////////////////////////////////// + // regs, flags + ///////////////////////////////////// + + // get flags + assign rem_sel_d = (load_en) ? rem : rem_sel_q; + assign comp_inv_d = (load_en) ? signed_op & op_b_sign : comp_inv_q; + assign op_b_zero_d = (load_en) ? op_b_zero : op_b_zero_q; + assign res_inv_d = (load_en) ? (~op_b_zero | rem) & signed_op & (op_a_sign ^ op_b_sign) : res_inv_q; + + // transaction id + assign id_d = (load_en) ? id_i : id_q; + assign id_o = id_q; + + assign op_a_d = (a_reg_en) ? add_out : op_a_q; + assign op_b_d = (b_reg_en) ? b_mux : op_b_q; + assign res_d = (load_en) ? '0 : + (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + state_q <= IDLE; + op_a_q <= '0; + op_b_q <= '0; + res_q <= '0; + cnt_q <= '0; + id_q <= '0; + rem_sel_q <= 1'b0; + comp_inv_q <= 1'b0; + res_inv_q <= 1'b0; + op_b_zero_q <= 1'b0; + div_res_zero_q <= 1'b0; + end else begin + state_q <= state_d; + op_a_q <= op_a_d; + op_b_q <= op_b_d; + res_q <= res_d; + cnt_q <= cnt_d; + id_q <= id_d; + rem_sel_q <= rem_sel_d; + comp_inv_q <= comp_inv_d; + res_inv_q <= res_inv_d; + op_b_zero_q <= op_b_zero_d; + div_res_zero_q <= div_res_zero_d; + end + end + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/snitch_addr_demux.sv b/flow/designs/src/mempool_group/rtl/snitch_addr_demux.sv new file mode 100644 index 0000000000..7c1617b99b --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch_addr_demux.sv @@ -0,0 +1,117 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Florian Zaruba +// Demux based on address + + +module snitch_addr_demux + import mempool_pkg::address_map_t; + import cf_math_pkg::idx_width; +#( + parameter int unsigned NrOutput = 2 , + parameter int unsigned AddressWidth = 32 , + parameter int unsigned NumRules = 1 , // Routing rules + parameter type req_t = logic, + parameter type resp_t = logic, + /// Dependent parameters, DO NOT OVERRIDE! + localparam integer LogNrOutput = idx_width(NrOutput) +) ( + input logic clk_i, + input logic rst_ni, + // request port + input logic [AddressWidth-1:0] req_addr_i, + input req_t req_payload_i, + input logic req_valid_i, + output logic req_ready_o, + output resp_t resp_payload_o, + output logic resp_valid_o, + input logic resp_ready_i, + // response port + output req_t [NrOutput-1:0] req_payload_o, + output logic [NrOutput-1:0] req_valid_o, + input logic [NrOutput-1:0] req_ready_i, + input resp_t [NrOutput-1:0] resp_payload_i, + input logic [NrOutput-1:0] resp_valid_i, + output logic [NrOutput-1:0] resp_ready_o, + input address_map_t [NumRules-1:0] address_map_i +); + + logic [LogNrOutput-1:0] slave_select; + logic [NumRules-1:0] addr_match; + logic [idx_width(NumRules)-1:0] rule_select; + + assign slave_select = address_map_i[rule_select].slave_idx; + + // Address Decoder + always_comb begin : addr_decoder + for (int i = 0; i < NumRules; i++) begin + addr_match[i] = (req_addr_i & address_map_i[i].mask) == address_map_i[i].value; + end + end + + find_first_one #( + .WIDTH(NumRules) + ) find_slave_select ( + .in_i ( addr_match ), + .first_one_o( rule_select ), + .no_ones_o ( /* Unused */ ) + ); + + // Demux request to correct interconnect + stream_demux #( + .N_OUP ( NrOutput ) + ) i_req_demux ( + .inp_valid_i ( req_valid_i ), + .inp_ready_o ( req_ready_o ), + .oup_sel_i ( slave_select ), + .oup_valid_o ( req_valid_o ), + .oup_ready_i ( req_ready_i ) + ); + + for (genvar i = 0; i < NrOutput; i++) begin : gen_req_outputs + assign req_payload_o[i] = req_payload_i; + end + + // Merge the response streams + logic [idx_width(NrOutput)-1:0] rr_prio; + assign rr_prio = 0; + + rr_arb_tree #( + .DataType (resp_t ), + .NumIn (NrOutput), + .AxiVldRdy(1'b1 ), + .ExtPrio (1'b1 ) + ) i_resp_stream_arbiter ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i(1'b0 ), + .rr_i (rr_prio ), + .req_i (resp_valid_i ), + .data_i (resp_payload_i), + .gnt_o (resp_ready_o ), + .req_o (resp_valid_o ), + .data_o (resp_payload_o), + .gnt_i (resp_ready_i ), + .idx_o (/* Unused */ ) + ); + + /* pragma translate_off */ + `ifdef FORMAL + logic f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + // assert reset in time step zero and deassert + assume property (@(posedge clk_i) !f_past_valid |-> !rst_ni); + // make sure that we get a response for each read we issued + for (genvar i = 0; i < NrOutput; i++) begin + assume property (@(posedge clk_i) disable iff (!rst_ni) (resp_valid_i[i] & resp_ready_o[i]) |-> $past(req_valid_o[i] & req_ready_i[i] & !req_write_i)); + end + `endif + // check that we propagate a downstream request directly (e.g. combinatorial) + assert property (@(posedge clk_i) disable iff (!rst_ni) (req_valid_i & req_ready_o) |-> |(req_valid_o & req_ready_i)); + /* pragma translate_on */ + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/tcdm_adapter.sv b/flow/designs/src/mempool_group/rtl/tcdm_adapter.sv new file mode 100644 index 0000000000..39e31172fd --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tcdm_adapter.sv @@ -0,0 +1,347 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Description: Handles the protocol conversion from valid/ready to req/gnt and correctly returns +// the metadata. Additionally, it handles atomics. Hence, it needs to be instantiated in front of +// an SRAM over which it has exclusive access. +// +// Author: Samuel Riedel + +`include "common_cells/registers.svh" + +module tcdm_adapter #( + parameter int unsigned AddrWidth = 32, + parameter int unsigned DataWidth = 32, + parameter type metadata_t = logic, + parameter bit LrScEnable = 1, + // Cut path between request and response at the cost of increased AMO latency + parameter bit RegisterAmo = 1'b0, + // Dependent parameters. DO NOT CHANGE. + localparam int unsigned BeWidth = DataWidth/8 +) ( + input logic clk_i, + input logic rst_ni, + // master side + input logic in_valid_i, // Bank request + output logic in_ready_o, // Bank grant + input logic [AddrWidth-1:0] in_address_i, // Address + input logic [3:0] in_amo_i, // Atomic Memory Operation + input logic in_write_i, // 1: Store, 0: Load + input logic [DataWidth-1:0] in_wdata_i, // Write data + input metadata_t in_meta_i, // Meta data + input logic [BeWidth-1:0] in_be_i, // Byte enable + output logic in_valid_o, // Read data + input logic in_ready_i, // Read data + output logic [DataWidth-1:0] in_rdata_o, // Read data + output metadata_t in_meta_o, // Meta data + // slave side + output logic out_req_o, // Bank request + output logic [AddrWidth-1:0] out_add_o, // Address + output logic out_write_o, // 1: Store, 0: Load + output logic [DataWidth-1:0] out_wdata_o, // Write data + output logic [BeWidth-1:0] out_be_o, // Bit enable + input logic [DataWidth-1:0] out_rdata_i // Read data +); + + import mempool_pkg::NumCores; + import mempool_pkg::NumGroups; + import mempool_pkg::NumCoresPerTile; + import cf_math_pkg::idx_width; + + typedef enum logic [3:0] { + AMONone = 4'h0, + AMOSwap = 4'h1, + AMOAdd = 4'h2, + AMOAnd = 4'h3, + AMOOr = 4'h4, + AMOXor = 4'h5, + AMOMax = 4'h6, + AMOMaxu = 4'h7, + AMOMin = 4'h8, + AMOMinu = 4'h9, + AMOLR = 4'hA, + AMOSC = 4'hB + } amo_op_t; + + logic meta_valid, meta_ready; + logic rdata_valid, rdata_ready; + + /// read signal before register + logic [DataWidth-1:0] out_rdata; + + logic out_gnt; + logic pop_resp; + + enum logic [1:0] { + Idle, DoAMO, WriteBackAMO + } state_q, state_d; + + logic load_amo; + amo_op_t amo_op_q; + logic [BeWidth-1:0] be_expand; + logic [AddrWidth-1:0] addr_q; + + logic [31:0] amo_operand_a; + logic [31:0] amo_operand_b_q; + logic [31:0] amo_result, amo_result_q; + + // Store the metadata at handshake + spill_register #( + .T (metadata_t), + .Bypass(1'b0 ) + ) i_metadata_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .valid_i(in_valid_i && in_ready_o && !in_write_i), + .ready_o(meta_ready ), + .data_i (in_meta_i ), + .valid_o(meta_valid ), + .ready_i(pop_resp ), + .data_o (in_meta_o ) + ); + + // Store response if it's not accepted immediately + fall_through_register #( + .T(logic[DataWidth-1:0]) + ) i_rdata_register ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .clr_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (out_rdata ), + .valid_i (out_gnt ), + .ready_o (rdata_ready), + .data_o (in_rdata_o ), + .valid_o (rdata_valid), + .ready_i (pop_resp ) + ); + + localparam int unsigned CoreIdWidth = idx_width(NumCores); + localparam int unsigned IniAddrWidth = idx_width(NumCoresPerTile + NumGroups); + + logic sc_successful_d, sc_successful_q; + logic sc_q; + + // In case of a SC we must forward SC result from the cycle earlier. + assign out_rdata = (sc_q && LrScEnable) ? $unsigned(!sc_successful_q) : out_rdata_i; + + // Ready to output data if both meta and read data + // are available (the read data will always be last) + assign in_valid_o = meta_valid && rdata_valid; + // Only pop the data from the registers once both registers are ready + assign pop_resp = in_ready_i && in_valid_o; + + // Generate out_gnt one cycle after sending read request to the bank + `FF(out_gnt, (out_req_o && !out_write_o) || sc_successful_d, 1'b0, clk_i, rst_ni); + + // ---------------- + // LR/SC + // ---------------- + + if (LrScEnable) begin : gen_lrsc + // unique core identifier, does not necessarily match core_id + logic [CoreIdWidth:0] unique_core_id; + + typedef struct packed { + /// Is the reservation valid. + logic valid; + /// On which address is the reservation placed. + /// This address is aligned to the memory size + /// implying that the reservation happen on a set size + /// equal to the word width of the memory (32 or 64 bit). + logic [AddrWidth-1:0] addr; + /// Which core made this reservation. Important to + /// track the reservations from different cores and + /// to prevent any live-locking. + logic [CoreIdWidth:0] core; + } reservation_t; + reservation_t reservation_d, reservation_q; + + `FF(sc_successful_q, sc_successful_d, 1'b0, clk_i, rst_ni); + `FF(reservation_q, reservation_d, 1'b0, clk_i, rst_ni); + `FF(sc_q, in_valid_i && in_ready_o && (amo_op_t'(in_amo_i) == AMOSC), 1'b0, clk_i, rst_ni); + + always_comb begin + // {group_id, tile_id, core_id} + // MSB of ini_addr determines if request is coming from local or remote tile + if (in_meta_i.ini_addr[IniAddrWidth-1] == 0) begin + // Request is coming from the local tile + // take group id of TCDM adapter + unique_core_id = {'0, in_meta_i.tile_id, in_meta_i.ini_addr[IniAddrWidth-2:0]}; + end else begin + // Request is coming from a remote tile + // take group id from ini_addr + // Ignore first bit of IniAddr to obtain the group address + unique_core_id = {in_meta_i.ini_addr[IniAddrWidth-2:0], + in_meta_i.tile_id, in_meta_i.core_id}; + end + + reservation_d = reservation_q; + sc_successful_d = 1'b0; + // new valid transaction + if (in_valid_i && in_ready_o) begin + + // An SC can only pair with the most recent LR in program order. + // Place a reservation on the address if there isn't already a valid reservation. + // We prevent a live-lock by don't throwing away the reservation of a hart unless + // it makes a new reservation in program order or issues any SC. + if (amo_op_t'(in_amo_i) == AMOLR && + (!reservation_q.valid || reservation_q.core == unique_core_id)) begin + reservation_d.valid = 1'b1; + reservation_d.addr = in_address_i; + reservation_d.core = unique_core_id; + end + + // An SC may succeed only if no store from another hart (or other device) to + // the reservation set can be observed to have occurred between + // the LR and the SC, and if there is no other SC between the + // LR and itself in program order. + + // check whether another core has made a write attempt + if ((unique_core_id != reservation_q.core) && + (in_address_i == reservation_q.addr) && + (!(amo_op_t'(in_amo_i) inside {AMONone, AMOLR, AMOSC}) || in_write_i)) begin + reservation_d.valid = 1'b0; + end + + // An SC from the same hart clears any pending reservation. + if (reservation_q.valid && amo_op_t'(in_amo_i) == AMOSC + && reservation_q.core == unique_core_id) begin + reservation_d.valid = 1'b0; + sc_successful_d = (reservation_q.addr == in_address_i); + end + end + end // always_comb + end else begin : disable_lrcs + assign sc_q = 1'b0; + assign sc_successful_d = 1'b0; + assign sc_successful_q = 1'b0; + end + + // ---------------- + // Atomics + // ---------------- + + always_comb begin + // feed-through + in_ready_o = in_valid_o && !in_ready_i ? 1'b0 : 1'b1; + out_req_o = in_valid_i && in_ready_o; + out_add_o = in_address_i; + out_write_o = in_write_i || (sc_successful_d && (amo_op_t'(in_amo_i) == AMOSC)); + out_wdata_o = in_wdata_i; + out_be_o = in_be_i; + + state_d = state_q; + load_amo = 1'b0; + + unique case (state_q) + Idle: begin + if (in_valid_i && in_ready_o && !(amo_op_t'(in_amo_i) inside {AMONone, AMOLR, AMOSC})) begin + load_amo = 1'b1; + state_d = DoAMO; + end + end + // Claim the memory interface + DoAMO, WriteBackAMO: begin + in_ready_o = 1'b0; + state_d = (RegisterAmo && state_q != WriteBackAMO) ? WriteBackAMO : Idle; + // Commit AMO + out_req_o = 1'b1; + out_write_o = 1'b1; + out_add_o = addr_q; + out_be_o = 4'b1111; + // serve from register if we cut the path + if (RegisterAmo) begin + out_wdata_o = amo_result_q; + end else begin + out_wdata_o = amo_result; + end + end + default:; + endcase + end + + if (RegisterAmo) begin : gen_amo_slice + `FFLNR(amo_result_q, amo_result, (state_q == DoAMO), clk_i) + end else begin : gen_amo_slice + assign amo_result_q = '0; + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + state_q <= Idle; + amo_op_q <= amo_op_t'('0); + addr_q <= '0; + amo_operand_b_q <= '0; + end else begin + state_q <= state_d; + if (load_amo) begin + amo_op_q <= amo_op_t'(in_amo_i); + addr_q <= in_address_i; + amo_operand_b_q <= in_wdata_i; + end else begin + amo_op_q <= AMONone; + end + end + end + + // ---------------- + // AMO ALU + // ---------------- + logic [33:0] adder_sum; + logic [32:0] adder_operand_a, adder_operand_b; + + assign amo_operand_a = out_rdata_i; + assign adder_sum = adder_operand_a + adder_operand_b; + /* verilator lint_off WIDTH */ + always_comb begin : amo_alu + + adder_operand_a = $signed(amo_operand_a); + adder_operand_b = $signed(amo_operand_b_q); + + amo_result = amo_operand_b_q; + + unique case (amo_op_q) + // the default is to output operand_b + AMOSwap:; + AMOAdd: amo_result = adder_sum[31:0]; + AMOAnd: amo_result = amo_operand_a & amo_operand_b_q; + AMOOr: amo_result = amo_operand_a | amo_operand_b_q; + AMOXor: amo_result = amo_operand_a ^ amo_operand_b_q; + AMOMax: begin + adder_operand_b = -$signed(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; + end + AMOMin: begin + adder_operand_b = -$signed(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; + end + AMOMaxu: begin + adder_operand_a = $unsigned(amo_operand_a); + adder_operand_b = -$unsigned(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_b_q : amo_operand_a; + end + AMOMinu: begin + adder_operand_a = $unsigned(amo_operand_a); + adder_operand_b = -$unsigned(amo_operand_b_q); + amo_result = adder_sum[32] ? amo_operand_a : amo_operand_b_q; + end + default: amo_result = '0; + endcase + end + + // pragma translate_off + // Check for unsupported parameters + if (DataWidth != 32) begin + $error($sformatf("Module currently only supports DataWidth = 32. DataWidth is currently set to: %0d", DataWidth)); + end + + `ifndef VERILATOR + rdata_full : assert property( + @(posedge clk_i) disable iff (~rst_ni) (out_gnt |-> rdata_ready)) + else $fatal (1, "Trying to push new data although the i_rdata_register is not ready."); + `endif + // pragma translate_on + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/tcdm_shim.sv b/flow/designs/src/mempool_group/rtl/tcdm_shim.sv new file mode 100644 index 0000000000..7da7182d51 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tcdm_shim.sv @@ -0,0 +1,180 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// TCDM Shim + +// Description: Converts propper handshaking (ready/valid) to TCDM signaling +// Author: Florian Zaruba + +module tcdm_shim + import mempool_pkg::address_map_t; + import cf_math_pkg::idx_width; +#( + parameter int unsigned AddrWidth = 32 , + parameter int unsigned DataWidth = 32 , + parameter int unsigned MaxOutStandingReads = 8 , + parameter int unsigned NrTCDM = 2 , + parameter int unsigned NrSoC = 1 , + parameter int unsigned NumRules = 1 , // Routing rules + localparam int unsigned StrbWidth = DataWidth/8 , + localparam int unsigned NumOutput = NrTCDM + NrSoC, + localparam int unsigned MetaIdWidth = idx_width(MaxOutStandingReads) +) ( + input logic clk_i, + input logic rst_ni, + // to TCDM + output logic [NrTCDM-1:0] tcdm_req_valid_o, + output logic [NrTCDM-1:0][AddrWidth-1:0] tcdm_req_tgt_addr_o, + output logic [NrTCDM-1:0] tcdm_req_wen_o, + output logic [NrTCDM-1:0][DataWidth-1:0] tcdm_req_wdata_o, + output logic [NrTCDM-1:0][3:0] tcdm_req_amo_o, + output logic [NrTCDM-1:0][MetaIdWidth-1:0] tcdm_req_id_o, + output logic [NrTCDM-1:0][StrbWidth-1:0] tcdm_req_be_o, + input logic [NrTCDM-1:0] tcdm_req_ready_i, + input logic [NrTCDM-1:0] tcdm_resp_valid_i, + output logic [NrTCDM-1:0] tcdm_resp_ready_o, + input logic [NrTCDM-1:0][DataWidth-1:0] tcdm_resp_rdata_i, + input logic [NrTCDM-1:0][MetaIdWidth-1:0] tcdm_resp_id_i, + // to SoC + output logic [NrSoC-1:0] [AddrWidth-1:0] soc_qaddr_o, + output logic [NrSoC-1:0] soc_qwrite_o, + output logic [NrSoC-1:0] [3:0] soc_qamo_o, + output logic [NrSoC-1:0] [DataWidth-1:0] soc_qdata_o, + output logic [NrSoC-1:0] [StrbWidth-1:0] soc_qstrb_o, + output logic [NrSoC-1:0] soc_qvalid_o, + input logic [NrSoC-1:0] soc_qready_i, + input logic [NrSoC-1:0] [DataWidth-1:0] soc_pdata_i, + input logic [NrSoC-1:0] soc_perror_i, + input logic [NrSoC-1:0] soc_pvalid_i, + output logic [NrSoC-1:0] soc_pready_o, + // from core + input logic [AddrWidth-1:0] data_qaddr_i, + input logic data_qwrite_i, + input logic [3:0] data_qamo_i, + input logic [DataWidth-1:0] data_qdata_i, + input logic [StrbWidth-1:0] data_qstrb_i, + input logic [MetaIdWidth-1:0] data_qid_i, + input logic data_qvalid_i, + output logic data_qready_o, + output logic [DataWidth-1:0] data_pdata_o, + output logic data_perror_o, + output logic [MetaIdWidth-1:0] data_pid_o, + output logic data_pvalid_o, + input logic data_pready_i, + // Address map + input address_map_t [NumRules-1:0] address_map_i +); + + // Imports + import snitch_pkg::dreq_t ; + import snitch_pkg::dresp_t; + + // Includes + `include "common_cells/registers.svh" + + dreq_t data_qpayload ; + dreq_t [NrSoC-1:0] soc_qpayload ; + dreq_t [NrTCDM-1:0] tcdm_qpayload; + dresp_t data_ppayload ; + dresp_t [NrSoC-1:0] soc_ppayload ; + dresp_t [NrTCDM-1:0] tcdm_ppayload; + + for (genvar i = 0; i < NrTCDM; i++) begin : gen_tcdm_ppayload + assign tcdm_ppayload[i].id = tcdm_resp_id_i[i] ; + assign tcdm_ppayload[i].data = tcdm_resp_rdata_i[i]; + assign tcdm_ppayload[i].error = 1'b0 ; + end + + // ROB IDs of the SoC requests (come back in order) + logic [NrSoC-1:0][MetaIdWidth-1:0] soc_meta_id; + + for (genvar i = 0; i < NrSoC; i++) begin: gen_soc_meta_id_fifo + fifo_v3 #( + .DEPTH (MaxOutStandingReads), + .DATA_WIDTH(MetaIdWidth ) + ) i_soc_meta_id_fifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (data_qid_i ), + .push_i (soc_qvalid_o[i] & soc_qready_i[i] &!soc_qwrite_o[i]), + .full_o (/* Unused */ ), + .data_o (soc_meta_id[i] ), + .pop_i (soc_pvalid_i[i] & soc_pready_o[i] ), + .empty_o (/* Unused */ ), + .usage_o (/* Unused */ ) + ); + end: gen_soc_meta_id_fifo + + // Demux according to address + snitch_addr_demux #( + .NrOutput (NumOutput), + .AddressWidth (AddrWidth), + .NumRules (NumRules ), // TODO + .req_t (dreq_t ), + .resp_t (dresp_t ) + ) i_snitch_addr_demux ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_addr_i (data_qaddr_i ), + .req_payload_i (data_qpayload ), + .req_valid_i (data_qvalid_i ), + .req_ready_o (data_qready_o ), + .resp_payload_o(data_ppayload ), + .resp_valid_o (data_pvalid_o ), + .resp_ready_i (data_pready_i ), + .req_payload_o ({soc_qpayload, tcdm_qpayload} ), + .req_valid_o ({soc_qvalid_o, tcdm_req_valid_o} ), + .req_ready_i ({soc_qready_i, tcdm_req_ready_i} ), + .resp_payload_i({soc_ppayload, tcdm_ppayload} ), + .resp_valid_i ({soc_pvalid_i, tcdm_resp_valid_i}), + .resp_ready_o ({soc_pready_o, tcdm_resp_ready_o}), + .address_map_i (address_map_i ) + ); + + // Connect TCDM output ports + for (genvar i = 0; i < NrTCDM; i++) begin : gen_tcdm_con + assign tcdm_req_tgt_addr_o[i] = tcdm_qpayload[i].addr ; + assign tcdm_req_wdata_o[i] = tcdm_qpayload[i].data ; + assign tcdm_req_amo_o[i] = tcdm_qpayload[i].amo ; + assign tcdm_req_id_o[i] = tcdm_qpayload[i].id ; + assign tcdm_req_wen_o[i] = tcdm_qpayload[i].write; + assign tcdm_req_be_o[i] = tcdm_qpayload[i].strb ; + end + + // Connect SOCs + for (genvar i = 0; i < NrSoC; i++) begin : gen_soc_con + assign soc_qaddr_o[i] = soc_qpayload[i].addr ; + assign soc_qwrite_o[i] = soc_qpayload[i].write; + assign soc_qamo_o[i] = soc_qpayload[i].amo ; + assign soc_qdata_o[i] = soc_qpayload[i].data ; + assign soc_qstrb_o[i] = soc_qpayload[i].strb ; + assign soc_ppayload[i].data = soc_pdata_i[i] ; + assign soc_ppayload[i].id = soc_meta_id[i] ; + assign soc_ppayload[i].error = soc_perror_i[i] ; + end + + // Request interface + assign data_qpayload.addr = data_qaddr_i ; + assign data_qpayload.write = data_qwrite_i; + assign data_qpayload.amo = data_qamo_i ; + assign data_qpayload.data = data_qdata_i ; + assign data_qpayload.id = data_qid_i ; + assign data_qpayload.strb = data_qstrb_i ; + + // Response interface + assign data_pdata_o = data_ppayload.data ; + assign data_perror_o = data_ppayload.error; + assign data_pid_o = data_ppayload.id ; + + // Elaboration-time assertions + + if (AddrWidth != 32) + $fatal(1, "[tcdm_shim] Only support 32-bit wide addresses."); + + if (DataWidth != 32) + $fatal(1, "[tcdm_shim] Only support a data width of 32 bits."); + +endmodule diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_clk.sv b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_clk.sv new file mode 100644 index 0000000000..bf0c1a8a75 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_clk.sv @@ -0,0 +1,95 @@ +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +module tc_clk_and2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i & clk1_i; + +endmodule + +module tc_clk_buffer ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = clk_i; + +endmodule + +// Description: Behavioral model of an integrated clock-gating cell (ICG) +module tc_clk_gating ( + input logic clk_i, + input logic en_i, + input logic test_en_i, + output logic clk_o +); + + logic clk_en; + + always_latch begin + if (clk_i == 1'b0) clk_en <= en_i | test_en_i; + end + + assign clk_o = clk_i & clk_en; + +endmodule + +module tc_clk_inverter ( + input logic clk_i, + output logic clk_o +); + + assign clk_o = ~clk_i; + +endmodule + +module tc_clk_mux2 ( + input logic clk0_i, + input logic clk1_i, + input logic clk_sel_i, + output logic clk_o +); + + assign clk_o = (clk_sel_i) ? clk1_i : clk0_i; + +endmodule + +module tc_clk_xor2 ( + input logic clk0_i, + input logic clk1_i, + output logic clk_o +); + + assign clk_o = clk0_i ^ clk1_i; + +endmodule + +`ifndef SYNTHESIS +module tc_clk_delay #( + parameter int unsigned Delay = 300ps +) ( + input logic in_i, + output logic out_o +); + +// pragma translate_off +`ifndef VERILATOR + assign #(Delay) out_o = in_i; +`endif +// pragma translate_on + +endmodule +`endif + + diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_sram.sv b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_sram.sv new file mode 100644 index 0000000000..b69e91cdc7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/tc_sram.sv @@ -0,0 +1,237 @@ +// Copyright (c) 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Wolfgang Roenninger + +// Description: Functional module of a generic SRAM +// +// Parameters: +// - NumWords: Number of words in the macro. Address width can be calculated with: +// `AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1` +// The module issues a warning if there is a request on an address which is +// not in range. +// - DataWidth: Width of the ports `wdata_i` and `rdata_o`. +// - ByteWidth: Width of a byte, the byte enable signal `be_i` can be calculated with the +// ceiling division `ceil(DataWidth, ByteWidth)`. +// - NumPorts: Number of read and write ports. Each is a full port. Ports with a higher +// index read and write after the ones with lower indices. +// - Latency: Read latency, the read data is available this many cycles after a request. +// - SimInit: Macro simulation initialization. Values are: +// "zeros": Each bit gets initialized with 1'b0. +// "ones": Each bit gets initialized with 1'b1. +// "random": Each bit gets random initialized with 1'b0 or 1'b1. +// "none": Each bit gets initialized with 1'bx. (default) +// - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with +// the instantiated parameters and signal widths. +// +// Ports: +// - `clk_i`: Clock +// - `rst_ni`: Asynchronous reset, active low +// - `req_i`: Request, active high +// - `we_i`: Write request, active high +// - `addr_i`: Request address +// - `wdata_i`: Write data, has to be valid on request +// - `be_i`: Byte enable, active high +// - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low. +// +// Behaviour: +// - Address collision: When Ports are making a write access onto the same address, +// the write operation will start at the port with the lowest address +// index, each port will overwrite the changes made by the previous ports +// according how the respective `be_i` signal is set. +// - Read data on write: This implementation will not produce a read data output on the signal +// `rdata_o` when `req_i` and `we_i` are asserted. The output data is stable +// on write requests. + +module tc_sram #( + parameter int unsigned NumWords = 32'd1024, // Number of Words in data array + parameter int unsigned DataWidth = 32'd128, // Data signal width + parameter int unsigned ByteWidth = 32'd8, // Width of a data byte + parameter int unsigned NumPorts = 32'd2, // Number of read and write ports + parameter int unsigned Latency = 32'd1, // Latency when the read data is available + parameter SimInit = "none", // Simulation initialization + parameter bit PrintSimCfg = 1'b0, // Print configuration + // DEPENDENT PARAMETERS, DO NOT OVERWRITE! + parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, + parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div + parameter type addr_t = logic [AddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0], + parameter type be_t = logic [BeWidth-1:0] +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // input ports + input logic [NumPorts-1:0] req_i, // request + input logic [NumPorts-1:0] we_i, // write enable + input addr_t [NumPorts-1:0] addr_i, // request address + input data_t [NumPorts-1:0] wdata_i, // write data + input be_t [NumPorts-1:0] be_i, // write byte enable + // output ports + output data_t [NumPorts-1:0] rdata_o // read data +); + + // memory array + //data_t sram [NumWords-1:0]; + // hold the read address when no read access is made + //addr_t [NumPorts-1:0] r_addr_q; + generate + if (DataWidth == 32 && NumWords == 256) begin + fakeram45_256x32 sram_instance(.rd_out(rdata_o[0]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0])); + end + else if (DataWidth == 256 && NumWords == 64)begin + fakeram45_64x64 fr_sp_instance0(.rd_out(rdata_o[0][63:0]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0][63:0])); + fakeram45_64x64 fr_sp_instance1(.rd_out(rdata_o[0][127:64]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0][127:64])); + fakeram45_64x64 fr_sp_instance2(.rd_out(rdata_o[0][191:128]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0][191:128])); + fakeram45_64x64 fr_sp_instance3(.rd_out(rdata_o[0][255:192]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0][255:192])); + end + else if (DataWidth == 256 && NumWords == 128) begin + fakeram45_128x256 sram_instance(.rd_out(rdata_o[0]), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_i[0])); + end + else if (DataWidth == 23 && NumWords == 128) begin + logic [31:0] wdata_aligned; + logic [31:0] rdata_aligned; + + always_comb begin : p_align + wdata_aligned ='0; + wdata_aligned[22:0] = wdata_i[0]; + rdata_o[0] = rdata_aligned[22:0]; + end + fakeram45_128x32 sram_instance(.rd_out(rdata_aligned), .clk(clk_i), .ce_in(~req_i), .we_in(we_i), .addr_in(addr_i), .wd_in(wdata_aligned)); + end + else begin + // memory array + data_t sram [NumWords-1:0]; + // hold the read address when no read access is made + addr_t [NumPorts-1:0] r_addr_q; + // SRAM simulation initialization + data_t [NumWords-1:0] init_val; + //initial begin : proc_sram_init + // for (int unsigned i = 0; i < NumWords; i++) begin + // for (int unsigned j = 0; j < DataWidth; j++) begin + // case (SimInit) + // "zeros": init_val[i][j] = 1'b0; + // "ones": init_val[i][j] = 1'b1; + // "random": init_val[i][j] = $urandom(); + // default: init_val[i][j] = 1'bx; + // endcase + // end + // end + //end + + // set the read output if requested + // The read data at the highest array index is set combinational. + // It gets then delayed for a number of cycles until it gets available at the output at + // array index 0. + + // read data output assignment + data_t [NumPorts-1:0][Latency-1:0] rdata_q, rdata_d; + if (Latency == 32'd0) begin : gen_no_read_lat + for (genvar i = 0; i < NumPorts; i++) begin : gen_port + assign rdata_o[i] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end else begin : gen_read_lat + + always_comb begin + for (int unsigned i = 0; i < NumPorts; i++) begin + rdata_o[i] = rdata_q[i][0]; + for (int unsigned j = 0; j < (Latency-1); j++) begin + rdata_d[i][j] = rdata_q[i][j+1]; + end + rdata_d[i][Latency-1] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]]; + end + end + end + + // write memory array + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + for (int unsigned i = 0; i < NumWords; i++) begin + sram[i] <= init_val[i]; + end + for (int i = 0; i < NumPorts; i++) begin + r_addr_q[i] <= {AddrWidth{1'b0}}; + // initialize the read output register for each port + if (Latency != 32'd0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= init_val[{AddrWidth{1'b0}}]; + end + end + end + end else begin + // read value latch happens before new data is written to the sram + for (int unsigned i = 0; i < NumPorts; i++) begin + if (Latency != 0) begin + for (int unsigned j = 0; j < Latency; j++) begin + rdata_q[i][j] <= rdata_d[i][j]; + end + end + end + // there is a request for the SRAM, latch the required register + for (int unsigned i = 0; i < NumPorts; i++) begin + if (req_i[i]) begin + if (we_i[i]) begin + // update value when write is set at clock + for (int unsigned j = 0; j < DataWidth; j++) begin + if (be_i[i][j/ByteWidth]) begin + sram[addr_i[i]][j] <= wdata_i[i][j]; + end + end + end else begin + // otherwise update read address for subsequent non request cycles + r_addr_q[i] <= addr_i[i]; + end + end // if req_i + end // for ports + end // if !rst_ni + end + +// Validate parameters. +// pragma translate_off +`ifndef VERILATOR +`ifndef TARGET_SYNTHESYS + initial begin: p_assertions + assert ($bits(addr_i) == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`"); + assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`"); + assert ($bits(be_i) == NumPorts * BeWidth) else $fatal(1, "BeWidth problem on `be_i`" ); + assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`"); + assert (NumWords >= 32'd1) else $fatal(1, "NumWords has to be > 0"); + assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0"); + assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0"); + assert (NumPorts >= 32'd1) else $fatal(1, "The number of ports must be at least 1!"); + end + initial begin: p_sim_hello + if (PrintSimCfg) begin + $display("#################################################################################"); + $display("tc_sram functional instantiated with the configuration:" ); + $display("Instance: %m" ); + $display("Number of ports (dec): %0d", NumPorts ); + $display("Number of words (dec): %0d", NumWords ); + $display("Address width (dec): %0d", AddrWidth ); + $display("Data width (dec): %0d", DataWidth ); + $display("Byte width (dec): %0d", ByteWidth ); + $display("Byte enable width (dec): %0d", BeWidth ); + $display("Latency Cycles (dec): %0d", Latency ); + $display("Simulation init (str): %0s", SimInit ); + $display("#################################################################################"); + end + end + for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions + assert property ( @(posedge clk_i) disable iff (!rst_ni) + (req_i[i] |-> (addr_i[i] < NumWords))) else + $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!", + addr_i[i], i); + end + +`endif +`endif +// pragma translate_on + end +endgenerate +endmodule diff --git a/flow/designs/src/mock-array/.gitignore b/flow/designs/src/mock-array/.gitignore index 03c3bdb759..3e5c0ff96d 100644 --- a/flow/designs/src/mock-array/.gitignore +++ b/flow/designs/src/mock-array/.gitignore @@ -7,3 +7,4 @@ target/ .bloop/ .bsp/ test_run_dir/ +*.f diff --git a/flow/designs/src/mock-array/BUILD.bazel b/flow/designs/src/mock-array/BUILD.bazel new file mode 100644 index 0000000000..fc10b865c2 --- /dev/null +++ b/flow/designs/src/mock-array/BUILD.bazel @@ -0,0 +1,7 @@ +exports_files(["util.tcl"] + glob(["*.v"])) + +filegroup( + name = "verilog", + srcs = glob(["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mock-array/Element.v b/flow/designs/src/mock-array/Element.v index 3d6188a408..bb3256d49d 100644 --- a/flow/designs/src/mock-array/Element.v +++ b/flow/designs/src/mock-array/Element.v @@ -24,6 +24,26 @@ module Element( output io_lsbOuts_6, output io_lsbOuts_7 ); + wire [31:0] io_outs_left_mult_a; + wire [31:0] io_outs_left_mult_b; + wire [31:0] io_outs_left_mult_o; + wire io_outs_left_mult_rst; + wire io_outs_left_mult_clk; + wire [31:0] io_outs_up_mult_a; + wire [31:0] io_outs_up_mult_b; + wire [31:0] io_outs_up_mult_o; + wire io_outs_up_mult_rst; + wire io_outs_up_mult_clk; + wire [31:0] io_outs_right_mult_a; + wire [31:0] io_outs_right_mult_b; + wire [31:0] io_outs_right_mult_o; + wire io_outs_right_mult_rst; + wire io_outs_right_mult_clk; + wire [31:0] io_outs_down_mult_a; + wire [31:0] io_outs_down_mult_b; + wire [31:0] io_outs_down_mult_o; + wire io_outs_down_mult_rst; + wire io_outs_down_mult_clk; reg [63:0] REG; reg [63:0] REG_1; reg [63:0] REG_2; @@ -32,15 +52,43 @@ module Element( reg [63:0] REG_5; reg [63:0] REG_6; reg [63:0] REG_7; - reg [63:0] io_outs_left_REG; - reg [63:0] io_outs_up_REG; - reg [63:0] io_outs_right_REG; - reg [63:0] io_outs_down_REG; + reg [15:0] io_outs_left_REG; + reg [15:0] io_outs_up_REG; + reg [15:0] io_outs_right_REG; + reg [15:0] io_outs_down_REG; reg REG_8; - assign io_outs_down = io_outs_down_REG; - assign io_outs_right = io_outs_right_REG; - assign io_outs_up = io_outs_up_REG; - assign io_outs_left = io_outs_left_REG; + multiplier io_outs_left_mult ( + .a(io_outs_left_mult_a), + .b(io_outs_left_mult_b), + .o(io_outs_left_mult_o), + .rst(io_outs_left_mult_rst), + .clk(io_outs_left_mult_clk) + ); + multiplier io_outs_up_mult ( + .a(io_outs_up_mult_a), + .b(io_outs_up_mult_b), + .o(io_outs_up_mult_o), + .rst(io_outs_up_mult_rst), + .clk(io_outs_up_mult_clk) + ); + multiplier io_outs_right_mult ( + .a(io_outs_right_mult_a), + .b(io_outs_right_mult_b), + .o(io_outs_right_mult_o), + .rst(io_outs_right_mult_rst), + .clk(io_outs_right_mult_clk) + ); + multiplier io_outs_down_mult ( + .a(io_outs_down_mult_a), + .b(io_outs_down_mult_b), + .o(io_outs_down_mult_o), + .rst(io_outs_down_mult_rst), + .clk(io_outs_down_mult_clk) + ); + assign io_outs_down = {{48'd0}, io_outs_down_REG}; + assign io_outs_right = {{48'd0}, io_outs_right_REG}; + assign io_outs_up = {{48'd0}, io_outs_up_REG}; + assign io_outs_left = {{48'd0}, io_outs_left_REG}; assign io_lsbOuts_0 = io_lsbIns_1; assign io_lsbOuts_1 = io_lsbIns_2; assign io_lsbOuts_2 = io_lsbIns_3; @@ -49,6 +97,22 @@ module Element( assign io_lsbOuts_5 = io_lsbIns_6; assign io_lsbOuts_6 = io_lsbIns_7; assign io_lsbOuts_7 = io_outs_left[0]; + assign io_outs_left_mult_a = REG[31:0]; + assign io_outs_left_mult_b = REG_1[31:0]; + assign io_outs_left_mult_rst = 1'h0; + assign io_outs_left_mult_clk = clock; + assign io_outs_up_mult_a = REG_2[31:0]; + assign io_outs_up_mult_b = REG_3[31:0]; + assign io_outs_up_mult_rst = 1'h0; + assign io_outs_up_mult_clk = clock; + assign io_outs_right_mult_a = REG_4[31:0]; + assign io_outs_right_mult_b = REG_5[31:0]; + assign io_outs_right_mult_rst = 1'h0; + assign io_outs_right_mult_clk = clock; + assign io_outs_down_mult_a = REG_6[31:0]; + assign io_outs_down_mult_b = REG_7[31:0]; + assign io_outs_down_mult_rst = 1'h0; + assign io_outs_down_mult_clk = clock; always @(posedge clock) begin REG <= io_ins_down; REG_1 <= io_ins_left; @@ -58,10 +122,10 @@ module Element( REG_5 <= io_ins_right; REG_6 <= io_ins_left; REG_7 <= io_ins_up; - io_outs_left_REG <= REG ^ REG_1; - io_outs_up_REG <= REG_2 ^ REG_3; - io_outs_right_REG <= REG_4 ^ REG_5; - io_outs_down_REG <= REG_6 ^ REG_7; + io_outs_left_REG <= io_outs_left_mult_o[15:0]; + io_outs_up_REG <= io_outs_up_mult_o[15:0]; + io_outs_right_REG <= io_outs_right_mult_o[15:0]; + io_outs_down_REG <= io_outs_down_mult_o[15:0]; REG_8 <= io_lsbIns_4; end endmodule diff --git a/flow/designs/src/mock-array/build.sbt b/flow/designs/src/mock-array/build.sbt index 6954dda226..0c01e6f731 100644 --- a/flow/designs/src/mock-array/build.sbt +++ b/flow/designs/src/mock-array/build.sbt @@ -25,3 +25,5 @@ resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("releases") ) + +resourceDirectory in Compile := baseDirectory.value / "src/main/resources" diff --git a/flow/designs/src/mock-array/multiplier.v b/flow/designs/src/mock-array/multiplier.v new file mode 100644 index 0000000000..03c2f06e14 --- /dev/null +++ b/flow/designs/src/mock-array/multiplier.v @@ -0,0 +1,24740 @@ +/* Generated by Amaranth Yosys 0.40 (PyPI ver 0.40.0.0.post102, git sha1 a1bb0255d) */ + +module multiplier(b, clk, rst, o, a); + wire \$1 ; + wire \$10 ; + wire \$100 ; + wire \$101 ; + wire \$102 ; + wire \$103 ; + wire \$104 ; + wire \$105 ; + wire \$106 ; + wire \$107 ; + wire \$108 ; + wire \$109 ; + wire \$11 ; + wire \$110 ; + wire \$111 ; + wire \$112 ; + wire \$113 ; + wire \$114 ; + wire \$115 ; + wire \$116 ; + wire \$117 ; + wire \$12 ; + wire \$13 ; + wire \$14 ; + wire \$15 ; + wire \$16 ; + wire \$17 ; + wire \$18 ; + wire \$19 ; + wire \$2 ; + wire \$20 ; + wire \$21 ; + wire \$22 ; + wire \$23 ; + wire \$24 ; + wire \$25 ; + wire \$26 ; + wire \$27 ; + wire \$28 ; + wire \$29 ; + wire \$3 ; + wire \$30 ; + wire \$31 ; + wire \$32 ; + wire \$33 ; + wire \$34 ; + wire \$35 ; + wire \$36 ; + wire \$37 ; + wire \$38 ; + wire \$39 ; + wire \$4 ; + wire \$40 ; + wire \$41 ; + wire \$42 ; + wire \$43 ; + wire \$44 ; + wire \$45 ; + wire \$46 ; + wire \$47 ; + wire \$48 ; + wire \$49 ; + wire \$5 ; + wire \$50 ; + wire \$51 ; + wire \$52 ; + wire \$53 ; + wire \$54 ; + wire \$55 ; + wire \$56 ; + wire \$57 ; + wire \$58 ; + wire \$59 ; + wire \$6 ; + wire \$60 ; + wire \$61 ; + wire \$62 ; + wire \$63 ; + wire \$64 ; + wire \$65 ; + wire \$66 ; + wire \$67 ; + wire \$68 ; + wire \$69 ; + wire \$7 ; + wire \$70 ; + wire \$71 ; + wire \$72 ; + wire \$73 ; + wire \$74 ; + wire \$75 ; + wire \$76 ; + wire \$77 ; + wire \$78 ; + wire \$79 ; + wire \$8 ; + wire \$80 ; + wire \$81 ; + wire \$82 ; + wire \$83 ; + wire \$84 ; + wire \$85 ; + wire \$86 ; + wire \$87 ; + wire \$88 ; + wire \$89 ; + wire \$9 ; + wire \$90 ; + wire \$91 ; + wire \$92 ; + wire \$93 ; + wire \$94 ; + wire \$95 ; + wire \$96 ; + wire \$97 ; + wire \$98 ; + wire \$99 ; + input [31:0] a; + wire [31:0] a; + (* init = 64'h0000000000000000 *) + wire [63:0] \a$1971 ; + reg [31:0] a_registered = 32'd0; + input [31:0] b; + wire [31:0] b; + (* init = 64'h0000000000000000 *) + wire [63:0] \b$1972 ; + reg [31:0] b_registered = 32'd0; + wire booth_b0_m0; + wire booth_b0_m1; + wire booth_b0_m10; + wire booth_b0_m11; + wire booth_b0_m12; + wire booth_b0_m13; + wire booth_b0_m14; + wire booth_b0_m15; + wire booth_b0_m16; + wire booth_b0_m17; + wire booth_b0_m18; + wire booth_b0_m19; + wire booth_b0_m2; + wire booth_b0_m20; + wire booth_b0_m21; + wire booth_b0_m22; + wire booth_b0_m23; + wire booth_b0_m24; + wire booth_b0_m25; + wire booth_b0_m26; + wire booth_b0_m27; + wire booth_b0_m28; + wire booth_b0_m29; + wire booth_b0_m3; + wire booth_b0_m30; + wire booth_b0_m31; + wire booth_b0_m32; + wire booth_b0_m4; + wire booth_b0_m5; + wire booth_b0_m6; + wire booth_b0_m7; + wire booth_b0_m8; + wire booth_b0_m9; + wire booth_b10_m0; + wire booth_b10_m1; + wire booth_b10_m10; + wire booth_b10_m11; + wire booth_b10_m12; + wire booth_b10_m13; + wire booth_b10_m14; + wire booth_b10_m15; + wire booth_b10_m16; + wire booth_b10_m17; + wire booth_b10_m18; + wire booth_b10_m19; + wire booth_b10_m2; + wire booth_b10_m20; + wire booth_b10_m21; + wire booth_b10_m22; + wire booth_b10_m23; + wire booth_b10_m24; + wire booth_b10_m25; + wire booth_b10_m26; + wire booth_b10_m27; + wire booth_b10_m28; + wire booth_b10_m29; + wire booth_b10_m3; + wire booth_b10_m30; + wire booth_b10_m31; + wire booth_b10_m32; + wire booth_b10_m4; + wire booth_b10_m5; + wire booth_b10_m6; + wire booth_b10_m7; + wire booth_b10_m8; + wire booth_b10_m9; + wire booth_b12_m0; + wire booth_b12_m1; + wire booth_b12_m10; + wire booth_b12_m11; + wire booth_b12_m12; + wire booth_b12_m13; + wire booth_b12_m14; + wire booth_b12_m15; + wire booth_b12_m16; + wire booth_b12_m17; + wire booth_b12_m18; + wire booth_b12_m19; + wire booth_b12_m2; + wire booth_b12_m20; + wire booth_b12_m21; + wire booth_b12_m22; + wire booth_b12_m23; + wire booth_b12_m24; + wire booth_b12_m25; + wire booth_b12_m26; + wire booth_b12_m27; + wire booth_b12_m28; + wire booth_b12_m29; + wire booth_b12_m3; + wire booth_b12_m30; + wire booth_b12_m31; + wire booth_b12_m32; + wire booth_b12_m4; + wire booth_b12_m5; + wire booth_b12_m6; + wire booth_b12_m7; + wire booth_b12_m8; + wire booth_b12_m9; + wire booth_b14_m0; + wire booth_b14_m1; + wire booth_b14_m10; + wire booth_b14_m11; + wire booth_b14_m12; + wire booth_b14_m13; + wire booth_b14_m14; + wire booth_b14_m15; + wire booth_b14_m16; + wire booth_b14_m17; + wire booth_b14_m18; + wire booth_b14_m19; + wire booth_b14_m2; + wire booth_b14_m20; + wire booth_b14_m21; + wire booth_b14_m22; + wire booth_b14_m23; + wire booth_b14_m24; + wire booth_b14_m25; + wire booth_b14_m26; + wire booth_b14_m27; + wire booth_b14_m28; + wire booth_b14_m29; + wire booth_b14_m3; + wire booth_b14_m30; + wire booth_b14_m31; + wire booth_b14_m32; + wire booth_b14_m4; + wire booth_b14_m5; + wire booth_b14_m6; + wire booth_b14_m7; + wire booth_b14_m8; + wire booth_b14_m9; + wire booth_b16_m0; + wire booth_b16_m1; + wire booth_b16_m10; + wire booth_b16_m11; + wire booth_b16_m12; + wire booth_b16_m13; + wire booth_b16_m14; + wire booth_b16_m15; + wire booth_b16_m16; + wire booth_b16_m17; + wire booth_b16_m18; + wire booth_b16_m19; + wire booth_b16_m2; + wire booth_b16_m20; + wire booth_b16_m21; + wire booth_b16_m22; + wire booth_b16_m23; + wire booth_b16_m24; + wire booth_b16_m25; + wire booth_b16_m26; + wire booth_b16_m27; + wire booth_b16_m28; + wire booth_b16_m29; + wire booth_b16_m3; + wire booth_b16_m30; + wire booth_b16_m31; + wire booth_b16_m32; + wire booth_b16_m4; + wire booth_b16_m5; + wire booth_b16_m6; + wire booth_b16_m7; + wire booth_b16_m8; + wire booth_b16_m9; + wire booth_b18_m0; + wire booth_b18_m1; + wire booth_b18_m10; + wire booth_b18_m11; + wire booth_b18_m12; + wire booth_b18_m13; + wire booth_b18_m14; + wire booth_b18_m15; + wire booth_b18_m16; + wire booth_b18_m17; + wire booth_b18_m18; + wire booth_b18_m19; + wire booth_b18_m2; + wire booth_b18_m20; + wire booth_b18_m21; + wire booth_b18_m22; + wire booth_b18_m23; + wire booth_b18_m24; + wire booth_b18_m25; + wire booth_b18_m26; + wire booth_b18_m27; + wire booth_b18_m28; + wire booth_b18_m29; + wire booth_b18_m3; + wire booth_b18_m30; + wire booth_b18_m31; + wire booth_b18_m32; + wire booth_b18_m4; + wire booth_b18_m5; + wire booth_b18_m6; + wire booth_b18_m7; + wire booth_b18_m8; + wire booth_b18_m9; + wire booth_b20_m0; + wire booth_b20_m1; + wire booth_b20_m10; + wire booth_b20_m11; + wire booth_b20_m12; + wire booth_b20_m13; + wire booth_b20_m14; + wire booth_b20_m15; + wire booth_b20_m16; + wire booth_b20_m17; + wire booth_b20_m18; + wire booth_b20_m19; + wire booth_b20_m2; + wire booth_b20_m20; + wire booth_b20_m21; + wire booth_b20_m22; + wire booth_b20_m23; + wire booth_b20_m24; + wire booth_b20_m25; + wire booth_b20_m26; + wire booth_b20_m27; + wire booth_b20_m28; + wire booth_b20_m29; + wire booth_b20_m3; + wire booth_b20_m30; + wire booth_b20_m31; + wire booth_b20_m32; + wire booth_b20_m4; + wire booth_b20_m5; + wire booth_b20_m6; + wire booth_b20_m7; + wire booth_b20_m8; + wire booth_b20_m9; + wire booth_b22_m0; + wire booth_b22_m1; + wire booth_b22_m10; + wire booth_b22_m11; + wire booth_b22_m12; + wire booth_b22_m13; + wire booth_b22_m14; + wire booth_b22_m15; + wire booth_b22_m16; + wire booth_b22_m17; + wire booth_b22_m18; + wire booth_b22_m19; + wire booth_b22_m2; + wire booth_b22_m20; + wire booth_b22_m21; + wire booth_b22_m22; + wire booth_b22_m23; + wire booth_b22_m24; + wire booth_b22_m25; + wire booth_b22_m26; + wire booth_b22_m27; + wire booth_b22_m28; + wire booth_b22_m29; + wire booth_b22_m3; + wire booth_b22_m30; + wire booth_b22_m31; + wire booth_b22_m32; + wire booth_b22_m4; + wire booth_b22_m5; + wire booth_b22_m6; + wire booth_b22_m7; + wire booth_b22_m8; + wire booth_b22_m9; + wire booth_b24_m0; + wire booth_b24_m1; + wire booth_b24_m10; + wire booth_b24_m11; + wire booth_b24_m12; + wire booth_b24_m13; + wire booth_b24_m14; + wire booth_b24_m15; + wire booth_b24_m16; + wire booth_b24_m17; + wire booth_b24_m18; + wire booth_b24_m19; + wire booth_b24_m2; + wire booth_b24_m20; + wire booth_b24_m21; + wire booth_b24_m22; + wire booth_b24_m23; + wire booth_b24_m24; + wire booth_b24_m25; + wire booth_b24_m26; + wire booth_b24_m27; + wire booth_b24_m28; + wire booth_b24_m29; + wire booth_b24_m3; + wire booth_b24_m30; + wire booth_b24_m31; + wire booth_b24_m32; + wire booth_b24_m4; + wire booth_b24_m5; + wire booth_b24_m6; + wire booth_b24_m7; + wire booth_b24_m8; + wire booth_b24_m9; + wire booth_b26_m0; + wire booth_b26_m1; + wire booth_b26_m10; + wire booth_b26_m11; + wire booth_b26_m12; + wire booth_b26_m13; + wire booth_b26_m14; + wire booth_b26_m15; + wire booth_b26_m16; + wire booth_b26_m17; + wire booth_b26_m18; + wire booth_b26_m19; + wire booth_b26_m2; + wire booth_b26_m20; + wire booth_b26_m21; + wire booth_b26_m22; + wire booth_b26_m23; + wire booth_b26_m24; + wire booth_b26_m25; + wire booth_b26_m26; + wire booth_b26_m27; + wire booth_b26_m28; + wire booth_b26_m29; + wire booth_b26_m3; + wire booth_b26_m30; + wire booth_b26_m31; + wire booth_b26_m32; + wire booth_b26_m4; + wire booth_b26_m5; + wire booth_b26_m6; + wire booth_b26_m7; + wire booth_b26_m8; + wire booth_b26_m9; + wire booth_b28_m0; + wire booth_b28_m1; + wire booth_b28_m10; + wire booth_b28_m11; + wire booth_b28_m12; + wire booth_b28_m13; + wire booth_b28_m14; + wire booth_b28_m15; + wire booth_b28_m16; + wire booth_b28_m17; + wire booth_b28_m18; + wire booth_b28_m19; + wire booth_b28_m2; + wire booth_b28_m20; + wire booth_b28_m21; + wire booth_b28_m22; + wire booth_b28_m23; + wire booth_b28_m24; + wire booth_b28_m25; + wire booth_b28_m26; + wire booth_b28_m27; + wire booth_b28_m28; + wire booth_b28_m29; + wire booth_b28_m3; + wire booth_b28_m30; + wire booth_b28_m31; + wire booth_b28_m32; + wire booth_b28_m4; + wire booth_b28_m5; + wire booth_b28_m6; + wire booth_b28_m7; + wire booth_b28_m8; + wire booth_b28_m9; + wire booth_b2_m0; + wire booth_b2_m1; + wire booth_b2_m10; + wire booth_b2_m11; + wire booth_b2_m12; + wire booth_b2_m13; + wire booth_b2_m14; + wire booth_b2_m15; + wire booth_b2_m16; + wire booth_b2_m17; + wire booth_b2_m18; + wire booth_b2_m19; + wire booth_b2_m2; + wire booth_b2_m20; + wire booth_b2_m21; + wire booth_b2_m22; + wire booth_b2_m23; + wire booth_b2_m24; + wire booth_b2_m25; + wire booth_b2_m26; + wire booth_b2_m27; + wire booth_b2_m28; + wire booth_b2_m29; + wire booth_b2_m3; + wire booth_b2_m30; + wire booth_b2_m31; + wire booth_b2_m32; + wire booth_b2_m4; + wire booth_b2_m5; + wire booth_b2_m6; + wire booth_b2_m7; + wire booth_b2_m8; + wire booth_b2_m9; + wire booth_b30_m0; + wire booth_b30_m1; + wire booth_b30_m10; + wire booth_b30_m11; + wire booth_b30_m12; + wire booth_b30_m13; + wire booth_b30_m14; + wire booth_b30_m15; + wire booth_b30_m16; + wire booth_b30_m17; + wire booth_b30_m18; + wire booth_b30_m19; + wire booth_b30_m2; + wire booth_b30_m20; + wire booth_b30_m21; + wire booth_b30_m22; + wire booth_b30_m23; + wire booth_b30_m24; + wire booth_b30_m25; + wire booth_b30_m26; + wire booth_b30_m27; + wire booth_b30_m28; + wire booth_b30_m29; + wire booth_b30_m3; + wire booth_b30_m30; + wire booth_b30_m31; + wire booth_b30_m32; + wire booth_b30_m4; + wire booth_b30_m5; + wire booth_b30_m6; + wire booth_b30_m7; + wire booth_b30_m8; + wire booth_b30_m9; + wire booth_b32_m0; + wire booth_b32_m1; + wire booth_b32_m10; + wire booth_b32_m11; + wire booth_b32_m12; + wire booth_b32_m13; + wire booth_b32_m14; + wire booth_b32_m15; + wire booth_b32_m16; + wire booth_b32_m17; + wire booth_b32_m18; + wire booth_b32_m19; + wire booth_b32_m2; + wire booth_b32_m20; + wire booth_b32_m21; + wire booth_b32_m22; + wire booth_b32_m23; + wire booth_b32_m24; + wire booth_b32_m25; + wire booth_b32_m26; + wire booth_b32_m27; + wire booth_b32_m28; + wire booth_b32_m29; + wire booth_b32_m3; + wire booth_b32_m30; + wire booth_b32_m31; + wire booth_b32_m32; + wire booth_b32_m4; + wire booth_b32_m5; + wire booth_b32_m6; + wire booth_b32_m7; + wire booth_b32_m8; + wire booth_b32_m9; + wire booth_b4_m0; + wire booth_b4_m1; + wire booth_b4_m10; + wire booth_b4_m11; + wire booth_b4_m12; + wire booth_b4_m13; + wire booth_b4_m14; + wire booth_b4_m15; + wire booth_b4_m16; + wire booth_b4_m17; + wire booth_b4_m18; + wire booth_b4_m19; + wire booth_b4_m2; + wire booth_b4_m20; + wire booth_b4_m21; + wire booth_b4_m22; + wire booth_b4_m23; + wire booth_b4_m24; + wire booth_b4_m25; + wire booth_b4_m26; + wire booth_b4_m27; + wire booth_b4_m28; + wire booth_b4_m29; + wire booth_b4_m3; + wire booth_b4_m30; + wire booth_b4_m31; + wire booth_b4_m32; + wire booth_b4_m4; + wire booth_b4_m5; + wire booth_b4_m6; + wire booth_b4_m7; + wire booth_b4_m8; + wire booth_b4_m9; + wire booth_b6_m0; + wire booth_b6_m1; + wire booth_b6_m10; + wire booth_b6_m11; + wire booth_b6_m12; + wire booth_b6_m13; + wire booth_b6_m14; + wire booth_b6_m15; + wire booth_b6_m16; + wire booth_b6_m17; + wire booth_b6_m18; + wire booth_b6_m19; + wire booth_b6_m2; + wire booth_b6_m20; + wire booth_b6_m21; + wire booth_b6_m22; + wire booth_b6_m23; + wire booth_b6_m24; + wire booth_b6_m25; + wire booth_b6_m26; + wire booth_b6_m27; + wire booth_b6_m28; + wire booth_b6_m29; + wire booth_b6_m3; + wire booth_b6_m30; + wire booth_b6_m31; + wire booth_b6_m32; + wire booth_b6_m4; + wire booth_b6_m5; + wire booth_b6_m6; + wire booth_b6_m7; + wire booth_b6_m8; + wire booth_b6_m9; + wire booth_b8_m0; + wire booth_b8_m1; + wire booth_b8_m10; + wire booth_b8_m11; + wire booth_b8_m12; + wire booth_b8_m13; + wire booth_b8_m14; + wire booth_b8_m15; + wire booth_b8_m16; + wire booth_b8_m17; + wire booth_b8_m18; + wire booth_b8_m19; + wire booth_b8_m2; + wire booth_b8_m20; + wire booth_b8_m21; + wire booth_b8_m22; + wire booth_b8_m23; + wire booth_b8_m24; + wire booth_b8_m25; + wire booth_b8_m26; + wire booth_b8_m27; + wire booth_b8_m28; + wire booth_b8_m29; + wire booth_b8_m3; + wire booth_b8_m30; + wire booth_b8_m31; + wire booth_b8_m32; + wire booth_b8_m4; + wire booth_b8_m5; + wire booth_b8_m6; + wire booth_b8_m7; + wire booth_b8_m8; + wire booth_b8_m9; + wire [2:0] booth_block0; + wire [1:0] booth_block0_mand0; + wire [1:0] booth_block0_mand1; + wire [1:0] booth_block0_mand10; + wire [1:0] booth_block0_mand11; + wire [1:0] booth_block0_mand12; + wire [1:0] booth_block0_mand13; + wire [1:0] booth_block0_mand14; + wire [1:0] booth_block0_mand15; + wire [1:0] booth_block0_mand16; + wire [1:0] booth_block0_mand17; + wire [1:0] booth_block0_mand18; + wire [1:0] booth_block0_mand19; + wire [1:0] booth_block0_mand2; + wire [1:0] booth_block0_mand20; + wire [1:0] booth_block0_mand21; + wire [1:0] booth_block0_mand22; + wire [1:0] booth_block0_mand23; + wire [1:0] booth_block0_mand24; + wire [1:0] booth_block0_mand25; + wire [1:0] booth_block0_mand26; + wire [1:0] booth_block0_mand27; + wire [1:0] booth_block0_mand28; + wire [1:0] booth_block0_mand29; + wire [1:0] booth_block0_mand3; + wire [1:0] booth_block0_mand30; + wire [1:0] booth_block0_mand31; + wire [1:0] booth_block0_mand32; + wire [1:0] booth_block0_mand4; + wire [1:0] booth_block0_mand5; + wire [1:0] booth_block0_mand6; + wire [1:0] booth_block0_mand7; + wire [1:0] booth_block0_mand8; + wire [1:0] booth_block0_mand9; + wire [1:0] booth_block0_sel; + wire booth_block0_sign; + wire [2:0] booth_block10; + wire [1:0] booth_block10_mand0; + wire [1:0] booth_block10_mand1; + wire [1:0] booth_block10_mand10; + wire [1:0] booth_block10_mand11; + wire [1:0] booth_block10_mand12; + wire [1:0] booth_block10_mand13; + wire [1:0] booth_block10_mand14; + wire [1:0] booth_block10_mand15; + wire [1:0] booth_block10_mand16; + wire [1:0] booth_block10_mand17; + wire [1:0] booth_block10_mand18; + wire [1:0] booth_block10_mand19; + wire [1:0] booth_block10_mand2; + wire [1:0] booth_block10_mand20; + wire [1:0] booth_block10_mand21; + wire [1:0] booth_block10_mand22; + wire [1:0] booth_block10_mand23; + wire [1:0] booth_block10_mand24; + wire [1:0] booth_block10_mand25; + wire [1:0] booth_block10_mand26; + wire [1:0] booth_block10_mand27; + wire [1:0] booth_block10_mand28; + wire [1:0] booth_block10_mand29; + wire [1:0] booth_block10_mand3; + wire [1:0] booth_block10_mand30; + wire [1:0] booth_block10_mand31; + wire [1:0] booth_block10_mand32; + wire [1:0] booth_block10_mand4; + wire [1:0] booth_block10_mand5; + wire [1:0] booth_block10_mand6; + wire [1:0] booth_block10_mand7; + wire [1:0] booth_block10_mand8; + wire [1:0] booth_block10_mand9; + wire [1:0] booth_block10_sel; + wire booth_block10_sign; + wire [2:0] booth_block12; + wire [1:0] booth_block12_mand0; + wire [1:0] booth_block12_mand1; + wire [1:0] booth_block12_mand10; + wire [1:0] booth_block12_mand11; + wire [1:0] booth_block12_mand12; + wire [1:0] booth_block12_mand13; + wire [1:0] booth_block12_mand14; + wire [1:0] booth_block12_mand15; + wire [1:0] booth_block12_mand16; + wire [1:0] booth_block12_mand17; + wire [1:0] booth_block12_mand18; + wire [1:0] booth_block12_mand19; + wire [1:0] booth_block12_mand2; + wire [1:0] booth_block12_mand20; + wire [1:0] booth_block12_mand21; + wire [1:0] booth_block12_mand22; + wire [1:0] booth_block12_mand23; + wire [1:0] booth_block12_mand24; + wire [1:0] booth_block12_mand25; + wire [1:0] booth_block12_mand26; + wire [1:0] booth_block12_mand27; + wire [1:0] booth_block12_mand28; + wire [1:0] booth_block12_mand29; + wire [1:0] booth_block12_mand3; + wire [1:0] booth_block12_mand30; + wire [1:0] booth_block12_mand31; + wire [1:0] booth_block12_mand32; + wire [1:0] booth_block12_mand4; + wire [1:0] booth_block12_mand5; + wire [1:0] booth_block12_mand6; + wire [1:0] booth_block12_mand7; + wire [1:0] booth_block12_mand8; + wire [1:0] booth_block12_mand9; + wire [1:0] booth_block12_sel; + wire booth_block12_sign; + wire [2:0] booth_block14; + wire [1:0] booth_block14_mand0; + wire [1:0] booth_block14_mand1; + wire [1:0] booth_block14_mand10; + wire [1:0] booth_block14_mand11; + wire [1:0] booth_block14_mand12; + wire [1:0] booth_block14_mand13; + wire [1:0] booth_block14_mand14; + wire [1:0] booth_block14_mand15; + wire [1:0] booth_block14_mand16; + wire [1:0] booth_block14_mand17; + wire [1:0] booth_block14_mand18; + wire [1:0] booth_block14_mand19; + wire [1:0] booth_block14_mand2; + wire [1:0] booth_block14_mand20; + wire [1:0] booth_block14_mand21; + wire [1:0] booth_block14_mand22; + wire [1:0] booth_block14_mand23; + wire [1:0] booth_block14_mand24; + wire [1:0] booth_block14_mand25; + wire [1:0] booth_block14_mand26; + wire [1:0] booth_block14_mand27; + wire [1:0] booth_block14_mand28; + wire [1:0] booth_block14_mand29; + wire [1:0] booth_block14_mand3; + wire [1:0] booth_block14_mand30; + wire [1:0] booth_block14_mand31; + wire [1:0] booth_block14_mand32; + wire [1:0] booth_block14_mand4; + wire [1:0] booth_block14_mand5; + wire [1:0] booth_block14_mand6; + wire [1:0] booth_block14_mand7; + wire [1:0] booth_block14_mand8; + wire [1:0] booth_block14_mand9; + wire [1:0] booth_block14_sel; + wire booth_block14_sign; + wire [2:0] booth_block16; + wire [1:0] booth_block16_mand0; + wire [1:0] booth_block16_mand1; + wire [1:0] booth_block16_mand10; + wire [1:0] booth_block16_mand11; + wire [1:0] booth_block16_mand12; + wire [1:0] booth_block16_mand13; + wire [1:0] booth_block16_mand14; + wire [1:0] booth_block16_mand15; + wire [1:0] booth_block16_mand16; + wire [1:0] booth_block16_mand17; + wire [1:0] booth_block16_mand18; + wire [1:0] booth_block16_mand19; + wire [1:0] booth_block16_mand2; + wire [1:0] booth_block16_mand20; + wire [1:0] booth_block16_mand21; + wire [1:0] booth_block16_mand22; + wire [1:0] booth_block16_mand23; + wire [1:0] booth_block16_mand24; + wire [1:0] booth_block16_mand25; + wire [1:0] booth_block16_mand26; + wire [1:0] booth_block16_mand27; + wire [1:0] booth_block16_mand28; + wire [1:0] booth_block16_mand29; + wire [1:0] booth_block16_mand3; + wire [1:0] booth_block16_mand30; + wire [1:0] booth_block16_mand31; + wire [1:0] booth_block16_mand32; + wire [1:0] booth_block16_mand4; + wire [1:0] booth_block16_mand5; + wire [1:0] booth_block16_mand6; + wire [1:0] booth_block16_mand7; + wire [1:0] booth_block16_mand8; + wire [1:0] booth_block16_mand9; + wire [1:0] booth_block16_sel; + wire booth_block16_sign; + wire [2:0] booth_block18; + wire [1:0] booth_block18_mand0; + wire [1:0] booth_block18_mand1; + wire [1:0] booth_block18_mand10; + wire [1:0] booth_block18_mand11; + wire [1:0] booth_block18_mand12; + wire [1:0] booth_block18_mand13; + wire [1:0] booth_block18_mand14; + wire [1:0] booth_block18_mand15; + wire [1:0] booth_block18_mand16; + wire [1:0] booth_block18_mand17; + wire [1:0] booth_block18_mand18; + wire [1:0] booth_block18_mand19; + wire [1:0] booth_block18_mand2; + wire [1:0] booth_block18_mand20; + wire [1:0] booth_block18_mand21; + wire [1:0] booth_block18_mand22; + wire [1:0] booth_block18_mand23; + wire [1:0] booth_block18_mand24; + wire [1:0] booth_block18_mand25; + wire [1:0] booth_block18_mand26; + wire [1:0] booth_block18_mand27; + wire [1:0] booth_block18_mand28; + wire [1:0] booth_block18_mand29; + wire [1:0] booth_block18_mand3; + wire [1:0] booth_block18_mand30; + wire [1:0] booth_block18_mand31; + wire [1:0] booth_block18_mand32; + wire [1:0] booth_block18_mand4; + wire [1:0] booth_block18_mand5; + wire [1:0] booth_block18_mand6; + wire [1:0] booth_block18_mand7; + wire [1:0] booth_block18_mand8; + wire [1:0] booth_block18_mand9; + wire [1:0] booth_block18_sel; + wire booth_block18_sign; + wire [2:0] booth_block2; + wire [2:0] booth_block20; + wire [1:0] booth_block20_mand0; + wire [1:0] booth_block20_mand1; + wire [1:0] booth_block20_mand10; + wire [1:0] booth_block20_mand11; + wire [1:0] booth_block20_mand12; + wire [1:0] booth_block20_mand13; + wire [1:0] booth_block20_mand14; + wire [1:0] booth_block20_mand15; + wire [1:0] booth_block20_mand16; + wire [1:0] booth_block20_mand17; + wire [1:0] booth_block20_mand18; + wire [1:0] booth_block20_mand19; + wire [1:0] booth_block20_mand2; + wire [1:0] booth_block20_mand20; + wire [1:0] booth_block20_mand21; + wire [1:0] booth_block20_mand22; + wire [1:0] booth_block20_mand23; + wire [1:0] booth_block20_mand24; + wire [1:0] booth_block20_mand25; + wire [1:0] booth_block20_mand26; + wire [1:0] booth_block20_mand27; + wire [1:0] booth_block20_mand28; + wire [1:0] booth_block20_mand29; + wire [1:0] booth_block20_mand3; + wire [1:0] booth_block20_mand30; + wire [1:0] booth_block20_mand31; + wire [1:0] booth_block20_mand32; + wire [1:0] booth_block20_mand4; + wire [1:0] booth_block20_mand5; + wire [1:0] booth_block20_mand6; + wire [1:0] booth_block20_mand7; + wire [1:0] booth_block20_mand8; + wire [1:0] booth_block20_mand9; + wire [1:0] booth_block20_sel; + wire booth_block20_sign; + wire [2:0] booth_block22; + wire [1:0] booth_block22_mand0; + wire [1:0] booth_block22_mand1; + wire [1:0] booth_block22_mand10; + wire [1:0] booth_block22_mand11; + wire [1:0] booth_block22_mand12; + wire [1:0] booth_block22_mand13; + wire [1:0] booth_block22_mand14; + wire [1:0] booth_block22_mand15; + wire [1:0] booth_block22_mand16; + wire [1:0] booth_block22_mand17; + wire [1:0] booth_block22_mand18; + wire [1:0] booth_block22_mand19; + wire [1:0] booth_block22_mand2; + wire [1:0] booth_block22_mand20; + wire [1:0] booth_block22_mand21; + wire [1:0] booth_block22_mand22; + wire [1:0] booth_block22_mand23; + wire [1:0] booth_block22_mand24; + wire [1:0] booth_block22_mand25; + wire [1:0] booth_block22_mand26; + wire [1:0] booth_block22_mand27; + wire [1:0] booth_block22_mand28; + wire [1:0] booth_block22_mand29; + wire [1:0] booth_block22_mand3; + wire [1:0] booth_block22_mand30; + wire [1:0] booth_block22_mand31; + wire [1:0] booth_block22_mand32; + wire [1:0] booth_block22_mand4; + wire [1:0] booth_block22_mand5; + wire [1:0] booth_block22_mand6; + wire [1:0] booth_block22_mand7; + wire [1:0] booth_block22_mand8; + wire [1:0] booth_block22_mand9; + wire [1:0] booth_block22_sel; + wire booth_block22_sign; + wire [2:0] booth_block24; + wire [1:0] booth_block24_mand0; + wire [1:0] booth_block24_mand1; + wire [1:0] booth_block24_mand10; + wire [1:0] booth_block24_mand11; + wire [1:0] booth_block24_mand12; + wire [1:0] booth_block24_mand13; + wire [1:0] booth_block24_mand14; + wire [1:0] booth_block24_mand15; + wire [1:0] booth_block24_mand16; + wire [1:0] booth_block24_mand17; + wire [1:0] booth_block24_mand18; + wire [1:0] booth_block24_mand19; + wire [1:0] booth_block24_mand2; + wire [1:0] booth_block24_mand20; + wire [1:0] booth_block24_mand21; + wire [1:0] booth_block24_mand22; + wire [1:0] booth_block24_mand23; + wire [1:0] booth_block24_mand24; + wire [1:0] booth_block24_mand25; + wire [1:0] booth_block24_mand26; + wire [1:0] booth_block24_mand27; + wire [1:0] booth_block24_mand28; + wire [1:0] booth_block24_mand29; + wire [1:0] booth_block24_mand3; + wire [1:0] booth_block24_mand30; + wire [1:0] booth_block24_mand31; + wire [1:0] booth_block24_mand32; + wire [1:0] booth_block24_mand4; + wire [1:0] booth_block24_mand5; + wire [1:0] booth_block24_mand6; + wire [1:0] booth_block24_mand7; + wire [1:0] booth_block24_mand8; + wire [1:0] booth_block24_mand9; + wire [1:0] booth_block24_sel; + wire booth_block24_sign; + wire [2:0] booth_block26; + wire [1:0] booth_block26_mand0; + wire [1:0] booth_block26_mand1; + wire [1:0] booth_block26_mand10; + wire [1:0] booth_block26_mand11; + wire [1:0] booth_block26_mand12; + wire [1:0] booth_block26_mand13; + wire [1:0] booth_block26_mand14; + wire [1:0] booth_block26_mand15; + wire [1:0] booth_block26_mand16; + wire [1:0] booth_block26_mand17; + wire [1:0] booth_block26_mand18; + wire [1:0] booth_block26_mand19; + wire [1:0] booth_block26_mand2; + wire [1:0] booth_block26_mand20; + wire [1:0] booth_block26_mand21; + wire [1:0] booth_block26_mand22; + wire [1:0] booth_block26_mand23; + wire [1:0] booth_block26_mand24; + wire [1:0] booth_block26_mand25; + wire [1:0] booth_block26_mand26; + wire [1:0] booth_block26_mand27; + wire [1:0] booth_block26_mand28; + wire [1:0] booth_block26_mand29; + wire [1:0] booth_block26_mand3; + wire [1:0] booth_block26_mand30; + wire [1:0] booth_block26_mand31; + wire [1:0] booth_block26_mand32; + wire [1:0] booth_block26_mand4; + wire [1:0] booth_block26_mand5; + wire [1:0] booth_block26_mand6; + wire [1:0] booth_block26_mand7; + wire [1:0] booth_block26_mand8; + wire [1:0] booth_block26_mand9; + wire [1:0] booth_block26_sel; + wire booth_block26_sign; + wire [2:0] booth_block28; + wire [1:0] booth_block28_mand0; + wire [1:0] booth_block28_mand1; + wire [1:0] booth_block28_mand10; + wire [1:0] booth_block28_mand11; + wire [1:0] booth_block28_mand12; + wire [1:0] booth_block28_mand13; + wire [1:0] booth_block28_mand14; + wire [1:0] booth_block28_mand15; + wire [1:0] booth_block28_mand16; + wire [1:0] booth_block28_mand17; + wire [1:0] booth_block28_mand18; + wire [1:0] booth_block28_mand19; + wire [1:0] booth_block28_mand2; + wire [1:0] booth_block28_mand20; + wire [1:0] booth_block28_mand21; + wire [1:0] booth_block28_mand22; + wire [1:0] booth_block28_mand23; + wire [1:0] booth_block28_mand24; + wire [1:0] booth_block28_mand25; + wire [1:0] booth_block28_mand26; + wire [1:0] booth_block28_mand27; + wire [1:0] booth_block28_mand28; + wire [1:0] booth_block28_mand29; + wire [1:0] booth_block28_mand3; + wire [1:0] booth_block28_mand30; + wire [1:0] booth_block28_mand31; + wire [1:0] booth_block28_mand32; + wire [1:0] booth_block28_mand4; + wire [1:0] booth_block28_mand5; + wire [1:0] booth_block28_mand6; + wire [1:0] booth_block28_mand7; + wire [1:0] booth_block28_mand8; + wire [1:0] booth_block28_mand9; + wire [1:0] booth_block28_sel; + wire booth_block28_sign; + wire [1:0] booth_block2_mand0; + wire [1:0] booth_block2_mand1; + wire [1:0] booth_block2_mand10; + wire [1:0] booth_block2_mand11; + wire [1:0] booth_block2_mand12; + wire [1:0] booth_block2_mand13; + wire [1:0] booth_block2_mand14; + wire [1:0] booth_block2_mand15; + wire [1:0] booth_block2_mand16; + wire [1:0] booth_block2_mand17; + wire [1:0] booth_block2_mand18; + wire [1:0] booth_block2_mand19; + wire [1:0] booth_block2_mand2; + wire [1:0] booth_block2_mand20; + wire [1:0] booth_block2_mand21; + wire [1:0] booth_block2_mand22; + wire [1:0] booth_block2_mand23; + wire [1:0] booth_block2_mand24; + wire [1:0] booth_block2_mand25; + wire [1:0] booth_block2_mand26; + wire [1:0] booth_block2_mand27; + wire [1:0] booth_block2_mand28; + wire [1:0] booth_block2_mand29; + wire [1:0] booth_block2_mand3; + wire [1:0] booth_block2_mand30; + wire [1:0] booth_block2_mand31; + wire [1:0] booth_block2_mand32; + wire [1:0] booth_block2_mand4; + wire [1:0] booth_block2_mand5; + wire [1:0] booth_block2_mand6; + wire [1:0] booth_block2_mand7; + wire [1:0] booth_block2_mand8; + wire [1:0] booth_block2_mand9; + wire [1:0] booth_block2_sel; + wire booth_block2_sign; + wire [2:0] booth_block30; + wire [1:0] booth_block30_mand0; + wire [1:0] booth_block30_mand1; + wire [1:0] booth_block30_mand10; + wire [1:0] booth_block30_mand11; + wire [1:0] booth_block30_mand12; + wire [1:0] booth_block30_mand13; + wire [1:0] booth_block30_mand14; + wire [1:0] booth_block30_mand15; + wire [1:0] booth_block30_mand16; + wire [1:0] booth_block30_mand17; + wire [1:0] booth_block30_mand18; + wire [1:0] booth_block30_mand19; + wire [1:0] booth_block30_mand2; + wire [1:0] booth_block30_mand20; + wire [1:0] booth_block30_mand21; + wire [1:0] booth_block30_mand22; + wire [1:0] booth_block30_mand23; + wire [1:0] booth_block30_mand24; + wire [1:0] booth_block30_mand25; + wire [1:0] booth_block30_mand26; + wire [1:0] booth_block30_mand27; + wire [1:0] booth_block30_mand28; + wire [1:0] booth_block30_mand29; + wire [1:0] booth_block30_mand3; + wire [1:0] booth_block30_mand30; + wire [1:0] booth_block30_mand31; + wire [1:0] booth_block30_mand32; + wire [1:0] booth_block30_mand4; + wire [1:0] booth_block30_mand5; + wire [1:0] booth_block30_mand6; + wire [1:0] booth_block30_mand7; + wire [1:0] booth_block30_mand8; + wire [1:0] booth_block30_mand9; + wire [1:0] booth_block30_sel; + wire booth_block30_sign; + wire [2:0] booth_block32; + wire [1:0] booth_block32_mand0; + wire [1:0] booth_block32_mand1; + wire [1:0] booth_block32_mand10; + wire [1:0] booth_block32_mand11; + wire [1:0] booth_block32_mand12; + wire [1:0] booth_block32_mand13; + wire [1:0] booth_block32_mand14; + wire [1:0] booth_block32_mand15; + wire [1:0] booth_block32_mand16; + wire [1:0] booth_block32_mand17; + wire [1:0] booth_block32_mand18; + wire [1:0] booth_block32_mand19; + wire [1:0] booth_block32_mand2; + wire [1:0] booth_block32_mand20; + wire [1:0] booth_block32_mand21; + wire [1:0] booth_block32_mand22; + wire [1:0] booth_block32_mand23; + wire [1:0] booth_block32_mand24; + wire [1:0] booth_block32_mand25; + wire [1:0] booth_block32_mand26; + wire [1:0] booth_block32_mand27; + wire [1:0] booth_block32_mand28; + wire [1:0] booth_block32_mand29; + wire [1:0] booth_block32_mand3; + wire [1:0] booth_block32_mand30; + wire [1:0] booth_block32_mand31; + wire [1:0] booth_block32_mand32; + wire [1:0] booth_block32_mand4; + wire [1:0] booth_block32_mand5; + wire [1:0] booth_block32_mand6; + wire [1:0] booth_block32_mand7; + wire [1:0] booth_block32_mand8; + wire [1:0] booth_block32_mand9; + wire [1:0] booth_block32_sel; + wire booth_block32_sign; + wire [2:0] booth_block4; + wire [1:0] booth_block4_mand0; + wire [1:0] booth_block4_mand1; + wire [1:0] booth_block4_mand10; + wire [1:0] booth_block4_mand11; + wire [1:0] booth_block4_mand12; + wire [1:0] booth_block4_mand13; + wire [1:0] booth_block4_mand14; + wire [1:0] booth_block4_mand15; + wire [1:0] booth_block4_mand16; + wire [1:0] booth_block4_mand17; + wire [1:0] booth_block4_mand18; + wire [1:0] booth_block4_mand19; + wire [1:0] booth_block4_mand2; + wire [1:0] booth_block4_mand20; + wire [1:0] booth_block4_mand21; + wire [1:0] booth_block4_mand22; + wire [1:0] booth_block4_mand23; + wire [1:0] booth_block4_mand24; + wire [1:0] booth_block4_mand25; + wire [1:0] booth_block4_mand26; + wire [1:0] booth_block4_mand27; + wire [1:0] booth_block4_mand28; + wire [1:0] booth_block4_mand29; + wire [1:0] booth_block4_mand3; + wire [1:0] booth_block4_mand30; + wire [1:0] booth_block4_mand31; + wire [1:0] booth_block4_mand32; + wire [1:0] booth_block4_mand4; + wire [1:0] booth_block4_mand5; + wire [1:0] booth_block4_mand6; + wire [1:0] booth_block4_mand7; + wire [1:0] booth_block4_mand8; + wire [1:0] booth_block4_mand9; + wire [1:0] booth_block4_sel; + wire booth_block4_sign; + wire [2:0] booth_block6; + wire [1:0] booth_block6_mand0; + wire [1:0] booth_block6_mand1; + wire [1:0] booth_block6_mand10; + wire [1:0] booth_block6_mand11; + wire [1:0] booth_block6_mand12; + wire [1:0] booth_block6_mand13; + wire [1:0] booth_block6_mand14; + wire [1:0] booth_block6_mand15; + wire [1:0] booth_block6_mand16; + wire [1:0] booth_block6_mand17; + wire [1:0] booth_block6_mand18; + wire [1:0] booth_block6_mand19; + wire [1:0] booth_block6_mand2; + wire [1:0] booth_block6_mand20; + wire [1:0] booth_block6_mand21; + wire [1:0] booth_block6_mand22; + wire [1:0] booth_block6_mand23; + wire [1:0] booth_block6_mand24; + wire [1:0] booth_block6_mand25; + wire [1:0] booth_block6_mand26; + wire [1:0] booth_block6_mand27; + wire [1:0] booth_block6_mand28; + wire [1:0] booth_block6_mand29; + wire [1:0] booth_block6_mand3; + wire [1:0] booth_block6_mand30; + wire [1:0] booth_block6_mand31; + wire [1:0] booth_block6_mand32; + wire [1:0] booth_block6_mand4; + wire [1:0] booth_block6_mand5; + wire [1:0] booth_block6_mand6; + wire [1:0] booth_block6_mand7; + wire [1:0] booth_block6_mand8; + wire [1:0] booth_block6_mand9; + wire [1:0] booth_block6_sel; + wire booth_block6_sign; + wire [2:0] booth_block8; + wire [1:0] booth_block8_mand0; + wire [1:0] booth_block8_mand1; + wire [1:0] booth_block8_mand10; + wire [1:0] booth_block8_mand11; + wire [1:0] booth_block8_mand12; + wire [1:0] booth_block8_mand13; + wire [1:0] booth_block8_mand14; + wire [1:0] booth_block8_mand15; + wire [1:0] booth_block8_mand16; + wire [1:0] booth_block8_mand17; + wire [1:0] booth_block8_mand18; + wire [1:0] booth_block8_mand19; + wire [1:0] booth_block8_mand2; + wire [1:0] booth_block8_mand20; + wire [1:0] booth_block8_mand21; + wire [1:0] booth_block8_mand22; + wire [1:0] booth_block8_mand23; + wire [1:0] booth_block8_mand24; + wire [1:0] booth_block8_mand25; + wire [1:0] booth_block8_mand26; + wire [1:0] booth_block8_mand27; + wire [1:0] booth_block8_mand28; + wire [1:0] booth_block8_mand29; + wire [1:0] booth_block8_mand3; + wire [1:0] booth_block8_mand30; + wire [1:0] booth_block8_mand31; + wire [1:0] booth_block8_mand32; + wire [1:0] booth_block8_mand4; + wire [1:0] booth_block8_mand5; + wire [1:0] booth_block8_mand6; + wire [1:0] booth_block8_mand7; + wire [1:0] booth_block8_mand8; + wire [1:0] booth_block8_mand9; + wire [1:0] booth_block8_sel; + wire booth_block8_sign; + wire c; + wire \c$1197 ; + wire \c$1198 ; + wire \c$1199 ; + wire \c$1200 ; + wire \c$1201 ; + wire \c$1202 ; + wire \c$1203 ; + wire \c$1204 ; + wire \c$1205 ; + wire \c$1206 ; + wire \c$1207 ; + wire \c$1208 ; + wire \c$1209 ; + wire \c$1210 ; + wire \c$1211 ; + wire \c$1212 ; + wire \c$1213 ; + wire \c$1214 ; + wire \c$1215 ; + wire \c$1216 ; + wire \c$1217 ; + wire \c$1218 ; + wire \c$1219 ; + wire \c$1220 ; + wire \c$1221 ; + wire \c$1222 ; + wire \c$1223 ; + wire \c$1224 ; + wire \c$1225 ; + wire \c$1226 ; + wire \c$1227 ; + wire \c$1228 ; + wire \c$1229 ; + wire \c$1230 ; + wire \c$1231 ; + wire \c$1232 ; + wire \c$1233 ; + wire \c$1234 ; + wire \c$1235 ; + wire \c$1236 ; + wire \c$1237 ; + wire \c$1238 ; + wire \c$1239 ; + wire \c$1240 ; + wire \c$1241 ; + wire \c$1242 ; + wire \c$1243 ; + wire \c$1244 ; + wire \c$1245 ; + wire \c$1246 ; + wire \c$1247 ; + wire \c$1248 ; + wire \c$1249 ; + wire \c$1250 ; + wire \c$1251 ; + wire \c$1252 ; + wire \c$1253 ; + wire \c$1254 ; + wire \c$1255 ; + wire \c$1256 ; + wire \c$1257 ; + wire \c$2553 ; + wire \c$2557 ; + wire \c$2561 ; + wire \c$2565 ; + wire \c$2569 ; + wire \c$2573 ; + wire \c$2577 ; + wire \c$2581 ; + wire \c$2585 ; + wire \c$2589 ; + wire \c$2593 ; + wire \c$2597 ; + wire \c$2601 ; + wire \c$2605 ; + wire \c$2609 ; + wire \c$2613 ; + wire \c$2617 ; + wire \c$2621 ; + wire \c$2625 ; + wire \c$2629 ; + wire \c$2633 ; + wire \c$2637 ; + wire \c$2641 ; + wire \c$2645 ; + wire \c$2649 ; + wire \c$2653 ; + wire \c$2657 ; + wire \c$2661 ; + wire \c$2665 ; + wire \c$2669 ; + wire \c$2673 ; + wire \c$2677 ; + wire \c$2681 ; + wire \c$2685 ; + wire \c$2689 ; + wire \c$2693 ; + wire \c$2697 ; + wire \c$2701 ; + wire \c$2705 ; + wire \c$2709 ; + wire \c$2713 ; + wire \c$2717 ; + wire \c$2721 ; + wire \c$2725 ; + wire \c$2729 ; + wire \c$2733 ; + wire \c$2737 ; + wire \c$2741 ; + wire \c$2745 ; + wire \c$2749 ; + wire \c$2753 ; + wire \c$2757 ; + wire \c$2761 ; + wire \c$2765 ; + wire \c$2769 ; + wire \c$2773 ; + wire \c$2777 ; + wire \c$2781 ; + wire \c$2785 ; + wire \c$2789 ; + wire \c$2793 ; + wire \c$2797 ; + wire \c$2801 ; + wire \c$2805 ; + wire \c$2809 ; + wire \c$2813 ; + wire \c$2817 ; + wire \c$2821 ; + wire \c$2825 ; + wire \c$2829 ; + wire \c$2833 ; + wire \c$2837 ; + wire \c$2841 ; + wire \c$2845 ; + wire \c$2849 ; + wire \c$2853 ; + wire \c$2857 ; + wire \c$2861 ; + wire \c$2865 ; + wire \c$2869 ; + wire \c$2873 ; + wire \c$2877 ; + wire \c$2881 ; + wire \c$2885 ; + wire \c$2889 ; + wire \c$2893 ; + wire \c$2897 ; + wire \c$2901 ; + wire \c$2905 ; + wire \c$2909 ; + wire \c$2913 ; + wire \c$2917 ; + wire \c$2921 ; + wire \c$2925 ; + wire \c$2929 ; + wire \c$2933 ; + wire \c$2937 ; + wire \c$2941 ; + wire \c$2945 ; + wire \c$2949 ; + wire \c$2953 ; + wire \c$2957 ; + wire \c$2961 ; + wire \c$2965 ; + wire \c$2969 ; + wire \c$2973 ; + wire \c$2977 ; + wire \c$2981 ; + wire \c$2985 ; + wire \c$2989 ; + wire \c$2993 ; + wire \c$2997 ; + wire \c$3001 ; + wire \c$3005 ; + wire \c$3009 ; + wire \c$3013 ; + wire \c$3017 ; + wire \c$3021 ; + wire \c$3025 ; + wire \c$3029 ; + wire \c$3033 ; + wire \c$3037 ; + wire \c$3041 ; + wire \c$3045 ; + wire \c$3049 ; + wire \c$3053 ; + wire \c$3057 ; + wire \c$3061 ; + wire \c$3065 ; + wire \c$3069 ; + wire \c$3073 ; + wire \c$3077 ; + wire \c$3081 ; + wire \c$3085 ; + wire \c$3089 ; + wire \c$3093 ; + wire \c$3097 ; + wire \c$3101 ; + wire \c$3105 ; + wire \c$3109 ; + wire \c$3113 ; + wire \c$3117 ; + wire \c$3121 ; + wire \c$3125 ; + wire \c$3129 ; + wire \c$3133 ; + wire \c$3137 ; + wire \c$3141 ; + wire \c$3145 ; + wire \c$3149 ; + wire \c$3153 ; + wire \c$3157 ; + wire \c$3161 ; + wire \c$3165 ; + wire \c$3169 ; + wire \c$3173 ; + wire \c$3177 ; + wire \c$3181 ; + wire \c$3185 ; + wire \c$3189 ; + wire \c$3193 ; + wire \c$3197 ; + wire \c$3201 ; + wire \c$3205 ; + wire \c$3209 ; + wire \c$3213 ; + wire \c$3217 ; + wire \c$3221 ; + wire \c$3225 ; + wire \c$3229 ; + wire \c$3233 ; + wire \c$3237 ; + wire \c$3241 ; + wire \c$3245 ; + wire \c$3249 ; + wire \c$3253 ; + wire \c$3257 ; + wire \c$3261 ; + wire \c$3265 ; + wire \c$3269 ; + wire \c$3273 ; + wire \c$3277 ; + wire \c$3281 ; + wire \c$3285 ; + wire \c$3289 ; + wire \c$3293 ; + wire \c$3297 ; + wire \c$3301 ; + wire \c$3305 ; + wire \c$3309 ; + wire \c$3313 ; + wire \c$3317 ; + wire \c$3321 ; + wire \c$3325 ; + wire \c$3329 ; + wire \c$3333 ; + wire \c$3337 ; + wire \c$3341 ; + wire \c$3345 ; + wire \c$3349 ; + wire \c$3353 ; + wire \c$3357 ; + wire \c$3361 ; + wire \c$3365 ; + wire \c$3369 ; + wire \c$3373 ; + wire \c$3377 ; + wire \c$3381 ; + wire \c$3385 ; + wire \c$3389 ; + wire \c$3393 ; + wire \c$3397 ; + wire \c$3401 ; + wire \c$3405 ; + wire \c$3409 ; + wire \c$3413 ; + wire \c$3417 ; + wire \c$3421 ; + wire \c$3425 ; + wire \c$3429 ; + wire \c$3433 ; + wire \c$3437 ; + wire \c$3441 ; + wire \c$3445 ; + wire \c$3449 ; + wire \c$3453 ; + wire \c$3457 ; + wire \c$3461 ; + wire \c$3465 ; + wire \c$3469 ; + wire \c$3473 ; + wire \c$3477 ; + wire \c$3481 ; + wire \c$3485 ; + wire \c$3489 ; + wire \c$3493 ; + wire \c$3497 ; + wire \c$3501 ; + wire \c$3505 ; + wire \c$3509 ; + wire \c$3513 ; + wire \c$3517 ; + wire \c$3521 ; + wire \c$3525 ; + wire \c$3529 ; + wire \c$3533 ; + wire \c$3537 ; + wire \c$3541 ; + wire \c$3545 ; + wire \c$3549 ; + wire \c$3553 ; + wire \c$3557 ; + wire \c$3561 ; + wire \c$3565 ; + wire \c$3569 ; + wire \c$3573 ; + wire \c$3577 ; + wire \c$3581 ; + wire \c$3585 ; + wire \c$3589 ; + wire \c$3593 ; + wire \c$3597 ; + wire \c$3601 ; + wire \c$3605 ; + wire \c$3609 ; + wire \c$3613 ; + wire \c$3617 ; + wire \c$3621 ; + wire \c$3625 ; + wire \c$3629 ; + wire \c$3633 ; + wire \c$3637 ; + wire \c$3641 ; + wire \c$3645 ; + wire \c$3649 ; + wire \c$3653 ; + wire \c$3657 ; + wire \c$3661 ; + wire \c$3665 ; + wire \c$3669 ; + wire \c$3673 ; + wire \c$3677 ; + wire \c$3681 ; + wire \c$3685 ; + wire \c$3689 ; + wire \c$3693 ; + wire \c$3697 ; + wire \c$3701 ; + wire \c$3705 ; + wire \c$3709 ; + wire \c$3713 ; + wire \c$3717 ; + wire \c$3721 ; + wire \c$3725 ; + wire \c$3729 ; + wire \c$3733 ; + wire \c$3737 ; + wire \c$3741 ; + wire \c$3745 ; + wire \c$3749 ; + wire \c$3753 ; + wire \c$3757 ; + wire \c$3761 ; + wire \c$3765 ; + wire \c$3769 ; + wire \c$3773 ; + wire \c$3777 ; + wire \c$3781 ; + wire \c$3785 ; + wire \c$3789 ; + wire \c$3793 ; + wire \c$3797 ; + wire \c$3801 ; + wire \c$3805 ; + wire \c$3809 ; + wire \c$3813 ; + wire \c$3817 ; + wire \c$3821 ; + wire \c$3825 ; + wire \c$3829 ; + wire \c$3833 ; + wire \c$3837 ; + wire \c$3841 ; + wire \c$3845 ; + wire \c$3849 ; + wire \c$3853 ; + wire \c$3857 ; + wire \c$3861 ; + wire \c$3865 ; + wire \c$3869 ; + wire \c$3873 ; + wire \c$3877 ; + wire \c$3881 ; + wire \c$3885 ; + wire \c$3889 ; + wire \c$3893 ; + wire \c$3897 ; + wire \c$3901 ; + wire \c$3905 ; + wire \c$3909 ; + wire \c$3913 ; + wire \c$3917 ; + wire \c$3921 ; + wire \c$3925 ; + wire \c$3929 ; + wire \c$3933 ; + wire \c$3937 ; + wire \c$3941 ; + wire \c$3945 ; + wire \c$3949 ; + wire \c$3953 ; + wire \c$3957 ; + wire \c$3961 ; + wire \c$3965 ; + wire \c$3969 ; + wire \c$3973 ; + wire \c$3977 ; + wire \c$3981 ; + wire \c$3985 ; + wire \c$3989 ; + wire \c$3993 ; + wire \c$3997 ; + wire \c$4001 ; + wire \c$4005 ; + wire \c$4009 ; + wire \c$4013 ; + wire \c$4017 ; + wire \c$4021 ; + wire \c$4025 ; + wire \c$4029 ; + wire \c$4033 ; + wire \c$4037 ; + wire \c$4041 ; + wire \c$4045 ; + wire \c$4049 ; + wire \c$4053 ; + wire \c$4057 ; + wire \c$4061 ; + wire \c$4065 ; + wire \c$4069 ; + wire \c$4073 ; + wire \c$4077 ; + wire \c$4081 ; + wire \c$4085 ; + wire \c$4089 ; + wire \c$4093 ; + wire \c$4097 ; + wire \c$4101 ; + wire \c$4105 ; + wire \c$4109 ; + wire \c$4113 ; + wire \c$4117 ; + wire \c$4121 ; + wire \c$4125 ; + wire \c$4129 ; + wire \c$4133 ; + wire \c$4137 ; + wire \c$4141 ; + wire \c$4145 ; + wire \c$4149 ; + wire \c$4153 ; + wire \c$4157 ; + wire \c$4161 ; + wire \c$4165 ; + wire \c$4169 ; + wire \c$4173 ; + wire \c$4177 ; + wire \c$4181 ; + wire \c$4185 ; + wire \c$4189 ; + wire \c$4193 ; + wire \c$4197 ; + wire \c$4201 ; + wire \c$4205 ; + wire \c$4209 ; + wire \c$4213 ; + wire \c$4217 ; + wire \c$4221 ; + wire \c$4225 ; + wire \c$4229 ; + wire \c$4233 ; + wire \c$4237 ; + wire \c$4241 ; + wire \c$4245 ; + wire \c$4249 ; + wire \c$4253 ; + wire \c$4257 ; + wire \c$4261 ; + wire \c$4265 ; + wire \c$4269 ; + wire \c$4273 ; + wire \c$4277 ; + wire \c$4281 ; + wire \c$4285 ; + wire \c$4289 ; + wire \c$4293 ; + wire \c$4297 ; + wire \c$4301 ; + wire \c$4305 ; + wire \c$4309 ; + wire \c$4313 ; + wire \c$4317 ; + wire \c$4321 ; + wire \c$4325 ; + wire \c$4329 ; + wire \c$4333 ; + wire \c$4337 ; + wire \c$4341 ; + wire \c$4345 ; + wire \c$4349 ; + wire \c$4353 ; + wire \c$4357 ; + wire \c$4361 ; + wire \c$4365 ; + wire \c$4369 ; + wire \c$4373 ; + wire \c$4377 ; + wire \c$4381 ; + wire \c$4385 ; + wire \c$4389 ; + wire \c$4393 ; + wire \c$4397 ; + input clk; + wire clk; + wire con; + wire \con$2556 ; + wire \con$2560 ; + wire \con$2564 ; + wire \con$2568 ; + wire \con$2572 ; + wire \con$2576 ; + wire \con$2580 ; + wire \con$2584 ; + wire \con$2588 ; + wire \con$2592 ; + wire \con$2596 ; + wire \con$2600 ; + wire \con$2604 ; + wire \con$2608 ; + wire \con$2612 ; + wire \con$2616 ; + wire \con$2620 ; + wire \con$2624 ; + wire \con$2628 ; + wire \con$2632 ; + wire \con$2636 ; + wire \con$2640 ; + wire \con$2644 ; + wire \con$2648 ; + wire \con$2652 ; + wire \con$2656 ; + wire \con$2660 ; + wire \con$2664 ; + wire \con$2668 ; + wire \con$2672 ; + wire \con$2676 ; + wire \con$2680 ; + wire \con$2684 ; + wire \con$2688 ; + wire \con$2692 ; + wire \con$2696 ; + wire \con$2700 ; + wire \con$2704 ; + wire \con$2708 ; + wire \con$2712 ; + wire \con$2716 ; + wire \con$2720 ; + wire \con$2724 ; + wire \con$2728 ; + wire \con$2732 ; + wire \con$2736 ; + wire \con$2740 ; + wire \con$2744 ; + wire \con$2748 ; + wire \con$2752 ; + wire \con$2756 ; + wire \con$2760 ; + wire \con$2764 ; + wire \con$2768 ; + wire \con$2772 ; + wire \con$2776 ; + wire \con$2780 ; + wire \con$2784 ; + wire \con$2788 ; + wire \con$2792 ; + wire \con$2796 ; + wire \con$2800 ; + wire \con$2804 ; + wire \con$2808 ; + wire \con$2812 ; + wire \con$2816 ; + wire \con$2820 ; + wire \con$2824 ; + wire \con$2828 ; + wire \con$2832 ; + wire \con$2836 ; + wire \con$2840 ; + wire \con$2844 ; + wire \con$2848 ; + wire \con$2852 ; + wire \con$2856 ; + wire \con$2860 ; + wire \con$2864 ; + wire \con$2868 ; + wire \con$2872 ; + wire \con$2876 ; + wire \con$2880 ; + wire \con$2884 ; + wire \con$2888 ; + wire \con$2892 ; + wire \con$2896 ; + wire \con$2900 ; + wire \con$2904 ; + wire \con$2908 ; + wire \con$2912 ; + wire \con$2916 ; + wire \con$2920 ; + wire \con$2924 ; + wire \con$2928 ; + wire \con$2932 ; + wire \con$2936 ; + wire \con$2940 ; + wire \con$2944 ; + wire \con$2948 ; + wire \con$2952 ; + wire \con$2956 ; + wire \con$2960 ; + wire \con$2964 ; + wire \con$2968 ; + wire \con$2972 ; + wire \con$2976 ; + wire \con$2980 ; + wire \con$2984 ; + wire \con$2988 ; + wire \con$2992 ; + wire \con$2996 ; + wire \con$3000 ; + wire \con$3004 ; + wire \con$3008 ; + wire \con$3012 ; + wire \con$3016 ; + wire \con$3020 ; + wire \con$3024 ; + wire \con$3028 ; + wire \con$3032 ; + wire \con$3036 ; + wire \con$3040 ; + wire \con$3044 ; + wire \con$3048 ; + wire \con$3052 ; + wire \con$3056 ; + wire \con$3060 ; + wire \con$3064 ; + wire \con$3068 ; + wire \con$3072 ; + wire \con$3076 ; + wire \con$3080 ; + wire \con$3084 ; + wire \con$3088 ; + wire \con$3092 ; + wire \con$3096 ; + wire \con$3100 ; + wire \con$3104 ; + wire \con$3108 ; + wire \con$3112 ; + wire \con$3116 ; + wire \con$3120 ; + wire \con$3124 ; + wire \con$3128 ; + wire \con$3132 ; + wire \con$3136 ; + wire \con$3140 ; + wire \con$3144 ; + wire \con$3148 ; + wire \con$3152 ; + wire \con$3156 ; + wire \con$3160 ; + wire \con$3164 ; + wire \con$3168 ; + wire \con$3172 ; + wire \con$3176 ; + wire \con$3180 ; + wire \con$3184 ; + wire \con$3188 ; + wire \con$3192 ; + wire \con$3196 ; + wire \con$3200 ; + wire \con$3204 ; + wire \con$3208 ; + wire \con$3212 ; + wire \con$3216 ; + wire \con$3220 ; + wire \con$3224 ; + wire \con$3228 ; + wire \con$3232 ; + wire \con$3236 ; + wire \con$3240 ; + wire \con$3244 ; + wire \con$3248 ; + wire \con$3252 ; + wire \con$3256 ; + wire \con$3260 ; + wire \con$3264 ; + wire \con$3268 ; + wire \con$3272 ; + wire \con$3276 ; + wire \con$3280 ; + wire \con$3284 ; + wire \con$3288 ; + wire \con$3292 ; + wire \con$3296 ; + wire \con$3300 ; + wire \con$3304 ; + wire \con$3308 ; + wire \con$3312 ; + wire \con$3316 ; + wire \con$3320 ; + wire \con$3324 ; + wire \con$3328 ; + wire \con$3332 ; + wire \con$3336 ; + wire \con$3340 ; + wire \con$3344 ; + wire \con$3348 ; + wire \con$3352 ; + wire \con$3356 ; + wire \con$3360 ; + wire \con$3364 ; + wire \con$3368 ; + wire \con$3372 ; + wire \con$3376 ; + wire \con$3380 ; + wire \con$3384 ; + wire \con$3388 ; + wire \con$3392 ; + wire \con$3396 ; + wire \con$3400 ; + wire \con$3404 ; + wire \con$3408 ; + wire \con$3412 ; + wire \con$3416 ; + wire \con$3420 ; + wire \con$3424 ; + wire \con$3428 ; + wire \con$3432 ; + wire \con$3436 ; + wire \con$3440 ; + wire \con$3444 ; + wire \con$3448 ; + wire \con$3452 ; + wire \con$3456 ; + wire \con$3460 ; + wire \con$3464 ; + wire \con$3468 ; + wire \con$3472 ; + wire \con$3476 ; + wire \con$3480 ; + wire \con$3484 ; + wire \con$3488 ; + wire \con$3492 ; + wire \con$3496 ; + wire \con$3500 ; + wire \con$3504 ; + wire \con$3508 ; + wire \con$3512 ; + wire \con$3516 ; + wire \con$3520 ; + wire \con$3524 ; + wire \con$3528 ; + wire \con$3532 ; + wire \con$3536 ; + wire \con$3540 ; + wire \con$3544 ; + wire \con$3548 ; + wire \con$3552 ; + wire \con$3556 ; + wire \con$3560 ; + wire \con$3564 ; + wire \con$3568 ; + wire \con$3572 ; + wire \con$3576 ; + wire \con$3580 ; + wire \con$3584 ; + wire \con$3588 ; + wire \con$3592 ; + wire \con$3596 ; + wire \con$3600 ; + wire \con$3604 ; + wire \con$3608 ; + wire \con$3612 ; + wire \con$3616 ; + wire \con$3620 ; + wire \con$3624 ; + wire \con$3628 ; + wire \con$3632 ; + wire \con$3636 ; + wire \con$3640 ; + wire \con$3644 ; + wire \con$3648 ; + wire \con$3652 ; + wire \con$3656 ; + wire \con$3660 ; + wire \con$3664 ; + wire \con$3668 ; + wire \con$3672 ; + wire \con$3676 ; + wire \con$3680 ; + wire \con$3684 ; + wire \con$3688 ; + wire \con$3692 ; + wire \con$3696 ; + wire \con$3700 ; + wire \con$3704 ; + wire \con$3708 ; + wire \con$3712 ; + wire \con$3716 ; + wire \con$3720 ; + wire \con$3724 ; + wire \con$3728 ; + wire \con$3732 ; + wire \con$3736 ; + wire \con$3740 ; + wire \con$3744 ; + wire \con$3748 ; + wire \con$3752 ; + wire \con$3756 ; + wire \con$3760 ; + wire \con$3764 ; + wire \con$3768 ; + wire \con$3772 ; + wire \con$3776 ; + wire \con$3780 ; + wire \con$3784 ; + wire \con$3788 ; + wire \con$3792 ; + wire \con$3796 ; + wire \con$3800 ; + wire \con$3804 ; + wire \con$3808 ; + wire \con$3812 ; + wire \con$3816 ; + wire \con$3820 ; + wire \con$3824 ; + wire \con$3828 ; + wire \con$3832 ; + wire \con$3836 ; + wire \con$3840 ; + wire \con$3844 ; + wire \con$3848 ; + wire \con$3852 ; + wire \con$3856 ; + wire \con$3860 ; + wire \con$3864 ; + wire \con$3868 ; + wire \con$3872 ; + wire \con$3876 ; + wire \con$3880 ; + wire \con$3884 ; + wire \con$3888 ; + wire \con$3892 ; + wire \con$3896 ; + wire \con$3900 ; + wire \con$3904 ; + wire \con$3908 ; + wire \con$3912 ; + wire \con$3916 ; + wire \con$3920 ; + wire \con$3924 ; + wire \con$3928 ; + wire \con$3932 ; + wire \con$3936 ; + wire \con$3940 ; + wire \con$3944 ; + wire \con$3948 ; + wire \con$3952 ; + wire \con$3956 ; + wire \con$3960 ; + wire \con$3964 ; + wire \con$3968 ; + wire \con$3972 ; + wire \con$3976 ; + wire \con$3980 ; + wire \con$3984 ; + wire \con$3988 ; + wire \con$3992 ; + wire \con$3996 ; + wire \con$4000 ; + wire \con$4004 ; + wire \con$4008 ; + wire \con$4012 ; + wire \con$4016 ; + wire \con$4020 ; + wire \con$4024 ; + wire \con$4028 ; + wire \con$4032 ; + wire \con$4036 ; + wire \con$4040 ; + wire \con$4044 ; + wire \con$4048 ; + wire \con$4052 ; + wire \con$4056 ; + wire \con$4060 ; + wire \con$4064 ; + wire \con$4068 ; + wire \con$4072 ; + wire \con$4076 ; + wire \con$4080 ; + wire \con$4084 ; + wire \con$4088 ; + wire \con$4092 ; + wire \con$4096 ; + wire \con$4100 ; + wire \con$4104 ; + wire \con$4108 ; + wire \con$4112 ; + wire \con$4116 ; + wire \con$4120 ; + wire \con$4124 ; + wire \con$4128 ; + wire \con$4132 ; + wire \con$4136 ; + wire \con$4140 ; + wire \con$4144 ; + wire \con$4148 ; + wire \con$4152 ; + wire \con$4156 ; + wire \con$4160 ; + wire \con$4164 ; + wire \con$4168 ; + wire \con$4172 ; + wire \con$4176 ; + wire \con$4180 ; + wire \con$4184 ; + wire \con$4188 ; + wire \con$4192 ; + wire \con$4196 ; + wire \con$4200 ; + wire \con$4204 ; + wire \con$4208 ; + wire \con$4212 ; + wire \con$4216 ; + wire \con$4220 ; + wire \con$4224 ; + wire \con$4228 ; + wire \con$4232 ; + wire \con$4236 ; + wire \con$4240 ; + wire \con$4244 ; + wire \con$4248 ; + wire \con$4252 ; + wire \con$4256 ; + wire \con$4260 ; + wire \con$4264 ; + wire \con$4268 ; + wire \con$4272 ; + wire \con$4276 ; + wire \con$4280 ; + wire \con$4284 ; + wire \con$4288 ; + wire \con$4292 ; + wire \con$4296 ; + wire \con$4300 ; + wire \con$4304 ; + wire \con$4308 ; + wire \con$4312 ; + wire \con$4316 ; + wire \con$4320 ; + wire \con$4324 ; + wire \con$4328 ; + wire \con$4332 ; + wire \con$4336 ; + wire \con$4340 ; + wire \con$4344 ; + wire \con$4348 ; + wire \con$4352 ; + wire \con$4356 ; + wire \con$4360 ; + wire \con$4364 ; + wire \con$4368 ; + wire \con$4372 ; + wire \con$4376 ; + wire \con$4380 ; + wire \con$4384 ; + wire \con$4388 ; + wire \con$4392 ; + wire \con$4396 ; + wire \con$4400 ; + wire \con$4402 ; + wire \con$4404 ; + wire \con$4406 ; + wire \con$4408 ; + wire \con$4410 ; + wire \con$4412 ; + wire \con$4414 ; + wire \con$4416 ; + wire \con$4418 ; + wire \con$4420 ; + wire \con$4422 ; + wire \con$4424 ; + wire \con$4426 ; + wire \con$4428 ; + wire \con$4430 ; + wire \con$4432 ; + wire \con$4434 ; + wire \con$4436 ; + wire \con$4438 ; + wire \con$4440 ; + wire \con$4442 ; + wire \con$4444 ; + wire \con$4446 ; + wire \con$4448 ; + wire \con$4450 ; + wire \con$4452 ; + wire \con$4454 ; + wire \con$4456 ; + wire \con$4458 ; + wire \con$4460 ; + wire \con$4462 ; + wire \con$4464 ; + wire \con$4466 ; + wire \con$4468 ; + wire \con$4470 ; + wire \con$4472 ; + wire \con$4474 ; + wire \con$4476 ; + wire \con$4478 ; + wire \con$4480 ; + wire \con$4482 ; + wire \con$4484 ; + wire \con$4486 ; + wire \con$4488 ; + wire \con$4490 ; + wire \con$4492 ; + wire \con$4494 ; + wire \con$4496 ; + wire \con$4498 ; + wire \con$4500 ; + wire \con$4502 ; + wire \con$4504 ; + wire \con$4506 ; + wire \con$4508 ; + wire \con$4510 ; + wire \con$4512 ; + wire \con$4514 ; + wire \con$4516 ; + wire \con$4518 ; + wire \con$4520 ; + wire \con$4522 ; + wire \con$4524 ; + reg [63:0] final_a_registered = 64'h0000000000000000; + reg [63:0] final_b_registered = 64'h0000000000000000; + wire [33:0] multiplicand; + wire [34:0] multiplier; + wire [2:0] notblock; + wire [2:0] \notblock$2008 ; + wire [2:0] \notblock$2042 ; + wire [2:0] \notblock$2076 ; + wire [2:0] \notblock$2110 ; + wire [2:0] \notblock$2144 ; + wire [2:0] \notblock$2178 ; + wire [2:0] \notblock$2212 ; + wire [2:0] \notblock$2246 ; + wire [2:0] \notblock$2280 ; + wire [2:0] \notblock$2314 ; + wire [2:0] \notblock$2348 ; + wire [2:0] \notblock$2382 ; + wire [2:0] \notblock$2416 ; + wire [2:0] \notblock$2450 ; + wire [2:0] \notblock$2484 ; + wire [2:0] \notblock$2518 ; + wire notsign; + wire \notsign$1036 ; + wire \notsign$1070 ; + wire \notsign$1100 ; + wire \notsign$1126 ; + wire \notsign$1148 ; + wire \notsign$1166 ; + wire \notsign$1180 ; + wire \notsign$1190 ; + wire \notsign$686 ; + wire \notsign$748 ; + wire \notsign$806 ; + wire \notsign$860 ; + wire \notsign$910 ; + wire \notsign$956 ; + wire \notsign$998 ; + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + wire [63:0] \o$1973 ; + reg pp_row0_0 = 1'h0; + reg pp_row0_1 = 1'h0; + reg pp_row10_0 = 1'h0; + reg pp_row10_1 = 1'h0; + reg pp_row10_2 = 1'h0; + reg pp_row10_3 = 1'h0; + reg pp_row10_4 = 1'h0; + reg pp_row10_5 = 1'h0; + reg pp_row10_6 = 1'h0; + reg pp_row11_0 = 1'h0; + reg pp_row11_1 = 1'h0; + reg pp_row11_2 = 1'h0; + reg pp_row11_3 = 1'h0; + reg pp_row11_4 = 1'h0; + reg pp_row11_5 = 1'h0; + reg pp_row12_0 = 1'h0; + reg pp_row12_1 = 1'h0; + reg pp_row12_2 = 1'h0; + reg pp_row12_3 = 1'h0; + reg pp_row12_4 = 1'h0; + reg pp_row12_5 = 1'h0; + reg pp_row12_6 = 1'h0; + reg pp_row12_7 = 1'h0; + reg pp_row13_0 = 1'h0; + reg pp_row13_1 = 1'h0; + reg pp_row13_2 = 1'h0; + reg pp_row13_3 = 1'h0; + reg pp_row13_4 = 1'h0; + reg pp_row13_5 = 1'h0; + reg pp_row13_6 = 1'h0; + reg pp_row14_0 = 1'h0; + reg pp_row14_1 = 1'h0; + reg pp_row14_2 = 1'h0; + reg pp_row14_3 = 1'h0; + reg pp_row14_4 = 1'h0; + reg pp_row14_5 = 1'h0; + reg pp_row14_6 = 1'h0; + reg pp_row14_7 = 1'h0; + reg pp_row14_8 = 1'h0; + reg pp_row15_0 = 1'h0; + reg pp_row15_1 = 1'h0; + reg pp_row15_2 = 1'h0; + reg pp_row15_3 = 1'h0; + reg pp_row15_4 = 1'h0; + reg pp_row15_5 = 1'h0; + reg pp_row15_6 = 1'h0; + reg pp_row15_7 = 1'h0; + reg pp_row16_0 = 1'h0; + reg pp_row16_1 = 1'h0; + reg pp_row16_2 = 1'h0; + reg pp_row16_3 = 1'h0; + reg pp_row16_4 = 1'h0; + reg pp_row16_5 = 1'h0; + reg pp_row16_6 = 1'h0; + reg pp_row16_7 = 1'h0; + reg pp_row16_8 = 1'h0; + reg pp_row16_9 = 1'h0; + reg pp_row17_0 = 1'h0; + reg pp_row17_1 = 1'h0; + reg pp_row17_2 = 1'h0; + reg pp_row17_3 = 1'h0; + reg pp_row17_4 = 1'h0; + reg pp_row17_5 = 1'h0; + reg pp_row17_6 = 1'h0; + reg pp_row17_7 = 1'h0; + reg pp_row17_8 = 1'h0; + reg pp_row18_0 = 1'h0; + reg pp_row18_1 = 1'h0; + reg pp_row18_10 = 1'h0; + reg pp_row18_2 = 1'h0; + reg pp_row18_3 = 1'h0; + reg pp_row18_4 = 1'h0; + reg pp_row18_5 = 1'h0; + reg pp_row18_6 = 1'h0; + reg pp_row18_7 = 1'h0; + reg pp_row18_8 = 1'h0; + reg pp_row18_9 = 1'h0; + reg pp_row19_0 = 1'h0; + reg pp_row19_1 = 1'h0; + reg pp_row19_2 = 1'h0; + reg pp_row19_3 = 1'h0; + reg pp_row19_4 = 1'h0; + reg pp_row19_5 = 1'h0; + reg pp_row19_6 = 1'h0; + reg pp_row19_7 = 1'h0; + reg pp_row19_8 = 1'h0; + reg pp_row19_9 = 1'h0; + reg pp_row1_0 = 1'h0; + reg pp_row20_0 = 1'h0; + reg pp_row20_1 = 1'h0; + reg pp_row20_10 = 1'h0; + reg pp_row20_11 = 1'h0; + reg pp_row20_2 = 1'h0; + reg pp_row20_3 = 1'h0; + reg pp_row20_4 = 1'h0; + reg pp_row20_5 = 1'h0; + reg pp_row20_6 = 1'h0; + reg pp_row20_7 = 1'h0; + reg pp_row20_8 = 1'h0; + reg pp_row20_9 = 1'h0; + reg pp_row21_0 = 1'h0; + reg pp_row21_1 = 1'h0; + reg pp_row21_10 = 1'h0; + reg pp_row21_2 = 1'h0; + reg pp_row21_3 = 1'h0; + reg pp_row21_4 = 1'h0; + reg pp_row21_5 = 1'h0; + reg pp_row21_6 = 1'h0; + reg pp_row21_7 = 1'h0; + reg pp_row21_8 = 1'h0; + reg pp_row21_9 = 1'h0; + reg pp_row22_0 = 1'h0; + reg pp_row22_1 = 1'h0; + reg pp_row22_10 = 1'h0; + reg pp_row22_11 = 1'h0; + reg pp_row22_12 = 1'h0; + reg pp_row22_2 = 1'h0; + reg pp_row22_3 = 1'h0; + reg pp_row22_4 = 1'h0; + reg pp_row22_5 = 1'h0; + reg pp_row22_6 = 1'h0; + reg pp_row22_7 = 1'h0; + reg pp_row22_8 = 1'h0; + reg pp_row22_9 = 1'h0; + reg pp_row23_0 = 1'h0; + reg pp_row23_1 = 1'h0; + reg pp_row23_10 = 1'h0; + reg pp_row23_11 = 1'h0; + reg pp_row23_2 = 1'h0; + reg pp_row23_3 = 1'h0; + reg pp_row23_4 = 1'h0; + reg pp_row23_5 = 1'h0; + reg pp_row23_6 = 1'h0; + reg pp_row23_7 = 1'h0; + reg pp_row23_8 = 1'h0; + reg pp_row23_9 = 1'h0; + reg pp_row24_0 = 1'h0; + reg pp_row24_1 = 1'h0; + reg pp_row24_10 = 1'h0; + reg pp_row24_11 = 1'h0; + reg pp_row24_12 = 1'h0; + reg pp_row24_13 = 1'h0; + reg pp_row24_2 = 1'h0; + reg pp_row24_3 = 1'h0; + reg pp_row24_4 = 1'h0; + reg pp_row24_5 = 1'h0; + reg pp_row24_6 = 1'h0; + reg pp_row24_7 = 1'h0; + reg pp_row24_8 = 1'h0; + reg pp_row24_9 = 1'h0; + reg pp_row25_0 = 1'h0; + reg pp_row25_1 = 1'h0; + reg pp_row25_10 = 1'h0; + reg pp_row25_11 = 1'h0; + reg pp_row25_12 = 1'h0; + reg pp_row25_2 = 1'h0; + reg pp_row25_3 = 1'h0; + reg pp_row25_4 = 1'h0; + reg pp_row25_5 = 1'h0; + reg pp_row25_6 = 1'h0; + reg pp_row25_7 = 1'h0; + reg pp_row25_8 = 1'h0; + reg pp_row25_9 = 1'h0; + reg pp_row26_0 = 1'h0; + reg pp_row26_1 = 1'h0; + reg pp_row26_10 = 1'h0; + reg pp_row26_11 = 1'h0; + reg pp_row26_12 = 1'h0; + reg pp_row26_13 = 1'h0; + reg pp_row26_14 = 1'h0; + reg pp_row26_2 = 1'h0; + reg pp_row26_3 = 1'h0; + reg pp_row26_4 = 1'h0; + reg pp_row26_5 = 1'h0; + reg pp_row26_6 = 1'h0; + reg pp_row26_7 = 1'h0; + reg pp_row26_8 = 1'h0; + reg pp_row26_9 = 1'h0; + reg pp_row27_0 = 1'h0; + reg pp_row27_1 = 1'h0; + reg pp_row27_10 = 1'h0; + reg pp_row27_11 = 1'h0; + reg pp_row27_12 = 1'h0; + reg pp_row27_13 = 1'h0; + reg pp_row27_2 = 1'h0; + reg pp_row27_3 = 1'h0; + reg pp_row27_4 = 1'h0; + reg pp_row27_5 = 1'h0; + reg pp_row27_6 = 1'h0; + reg pp_row27_7 = 1'h0; + reg pp_row27_8 = 1'h0; + reg pp_row27_9 = 1'h0; + reg pp_row28_0 = 1'h0; + reg pp_row28_1 = 1'h0; + reg pp_row28_10 = 1'h0; + reg pp_row28_11 = 1'h0; + reg pp_row28_12 = 1'h0; + reg pp_row28_13 = 1'h0; + reg pp_row28_14 = 1'h0; + reg pp_row28_15 = 1'h0; + reg pp_row28_2 = 1'h0; + reg pp_row28_3 = 1'h0; + reg pp_row28_4 = 1'h0; + reg pp_row28_5 = 1'h0; + reg pp_row28_6 = 1'h0; + reg pp_row28_7 = 1'h0; + reg pp_row28_8 = 1'h0; + reg pp_row28_9 = 1'h0; + reg pp_row29_0 = 1'h0; + reg pp_row29_1 = 1'h0; + reg pp_row29_10 = 1'h0; + reg pp_row29_11 = 1'h0; + reg pp_row29_12 = 1'h0; + reg pp_row29_13 = 1'h0; + reg pp_row29_14 = 1'h0; + reg pp_row29_2 = 1'h0; + reg pp_row29_3 = 1'h0; + reg pp_row29_4 = 1'h0; + reg pp_row29_5 = 1'h0; + reg pp_row29_6 = 1'h0; + reg pp_row29_7 = 1'h0; + reg pp_row29_8 = 1'h0; + reg pp_row29_9 = 1'h0; + reg pp_row2_0 = 1'h0; + reg pp_row2_1 = 1'h0; + reg pp_row2_2 = 1'h0; + reg pp_row30_0 = 1'h0; + reg pp_row30_1 = 1'h0; + reg pp_row30_10 = 1'h0; + reg pp_row30_11 = 1'h0; + reg pp_row30_12 = 1'h0; + reg pp_row30_13 = 1'h0; + reg pp_row30_14 = 1'h0; + reg pp_row30_15 = 1'h0; + reg pp_row30_16 = 1'h0; + reg pp_row30_2 = 1'h0; + reg pp_row30_3 = 1'h0; + reg pp_row30_4 = 1'h0; + reg pp_row30_5 = 1'h0; + reg pp_row30_6 = 1'h0; + reg pp_row30_7 = 1'h0; + reg pp_row30_8 = 1'h0; + reg pp_row30_9 = 1'h0; + reg pp_row31_0 = 1'h0; + reg pp_row31_1 = 1'h0; + reg pp_row31_10 = 1'h0; + reg pp_row31_11 = 1'h0; + reg pp_row31_12 = 1'h0; + reg pp_row31_13 = 1'h0; + reg pp_row31_14 = 1'h0; + reg pp_row31_15 = 1'h0; + reg pp_row31_2 = 1'h0; + reg pp_row31_3 = 1'h0; + reg pp_row31_4 = 1'h0; + reg pp_row31_5 = 1'h0; + reg pp_row31_6 = 1'h0; + reg pp_row31_7 = 1'h0; + reg pp_row31_8 = 1'h0; + reg pp_row31_9 = 1'h0; + reg pp_row32_0 = 1'h0; + reg pp_row32_1 = 1'h0; + reg pp_row32_10 = 1'h0; + reg pp_row32_11 = 1'h0; + reg pp_row32_12 = 1'h0; + reg pp_row32_13 = 1'h0; + reg pp_row32_14 = 1'h0; + reg pp_row32_15 = 1'h0; + reg pp_row32_16 = 1'h0; + reg pp_row32_2 = 1'h0; + reg pp_row32_3 = 1'h0; + reg pp_row32_4 = 1'h0; + reg pp_row32_5 = 1'h0; + reg pp_row32_6 = 1'h0; + reg pp_row32_7 = 1'h0; + reg pp_row32_8 = 1'h0; + reg pp_row32_9 = 1'h0; + reg pp_row33_0 = 1'h0; + reg pp_row33_1 = 1'h0; + reg pp_row33_10 = 1'h0; + reg pp_row33_11 = 1'h0; + reg pp_row33_12 = 1'h0; + reg pp_row33_13 = 1'h0; + reg pp_row33_14 = 1'h0; + reg pp_row33_15 = 1'h0; + reg pp_row33_16 = 1'h0; + reg pp_row33_2 = 1'h0; + reg pp_row33_3 = 1'h0; + reg pp_row33_4 = 1'h0; + reg pp_row33_5 = 1'h0; + reg pp_row33_6 = 1'h0; + reg pp_row33_7 = 1'h0; + reg pp_row33_8 = 1'h0; + reg pp_row33_9 = 1'h0; + reg pp_row34_0 = 1'h0; + reg pp_row34_1 = 1'h0; + reg pp_row34_10 = 1'h0; + reg pp_row34_11 = 1'h0; + reg pp_row34_12 = 1'h0; + reg pp_row34_13 = 1'h0; + reg pp_row34_14 = 1'h0; + reg pp_row34_15 = 1'h0; + reg pp_row34_16 = 1'h0; + reg pp_row34_2 = 1'h0; + reg pp_row34_3 = 1'h0; + reg pp_row34_4 = 1'h0; + reg pp_row34_5 = 1'h0; + reg pp_row34_6 = 1'h0; + reg pp_row34_7 = 1'h0; + reg pp_row34_8 = 1'h0; + reg pp_row34_9 = 1'h0; + reg pp_row35_0 = 1'h0; + reg pp_row35_1 = 1'h0; + reg pp_row35_10 = 1'h0; + reg pp_row35_11 = 1'h0; + reg pp_row35_12 = 1'h0; + reg pp_row35_13 = 1'h0; + reg pp_row35_14 = 1'h0; + reg pp_row35_15 = 1'h0; + reg pp_row35_16 = 1'h0; + reg pp_row35_2 = 1'h0; + reg pp_row35_3 = 1'h0; + reg pp_row35_4 = 1'h0; + reg pp_row35_5 = 1'h0; + reg pp_row35_6 = 1'h0; + reg pp_row35_7 = 1'h0; + reg pp_row35_8 = 1'h0; + reg pp_row35_9 = 1'h0; + wire pp_row36_0; + reg pp_row36_1 = 1'h0; + reg pp_row36_10 = 1'h0; + reg pp_row36_11 = 1'h0; + reg pp_row36_12 = 1'h0; + reg pp_row36_13 = 1'h0; + reg pp_row36_14 = 1'h0; + reg pp_row36_15 = 1'h0; + reg pp_row36_2 = 1'h0; + reg pp_row36_3 = 1'h0; + reg pp_row36_4 = 1'h0; + reg pp_row36_5 = 1'h0; + reg pp_row36_6 = 1'h0; + reg pp_row36_7 = 1'h0; + reg pp_row36_8 = 1'h0; + reg pp_row36_9 = 1'h0; + reg pp_row37_0 = 1'h0; + reg pp_row37_1 = 1'h0; + reg pp_row37_10 = 1'h0; + reg pp_row37_11 = 1'h0; + reg pp_row37_12 = 1'h0; + reg pp_row37_13 = 1'h0; + reg pp_row37_14 = 1'h0; + reg pp_row37_2 = 1'h0; + reg pp_row37_3 = 1'h0; + reg pp_row37_4 = 1'h0; + reg pp_row37_5 = 1'h0; + reg pp_row37_6 = 1'h0; + reg pp_row37_7 = 1'h0; + reg pp_row37_8 = 1'h0; + reg pp_row37_9 = 1'h0; + wire pp_row38_0; + reg pp_row38_1 = 1'h0; + reg pp_row38_10 = 1'h0; + reg pp_row38_11 = 1'h0; + reg pp_row38_12 = 1'h0; + reg pp_row38_13 = 1'h0; + reg pp_row38_14 = 1'h0; + reg pp_row38_2 = 1'h0; + reg pp_row38_3 = 1'h0; + reg pp_row38_4 = 1'h0; + reg pp_row38_5 = 1'h0; + reg pp_row38_6 = 1'h0; + reg pp_row38_7 = 1'h0; + reg pp_row38_8 = 1'h0; + reg pp_row38_9 = 1'h0; + reg pp_row39_0 = 1'h0; + reg pp_row39_1 = 1'h0; + reg pp_row39_10 = 1'h0; + reg pp_row39_11 = 1'h0; + reg pp_row39_12 = 1'h0; + reg pp_row39_13 = 1'h0; + reg pp_row39_2 = 1'h0; + reg pp_row39_3 = 1'h0; + reg pp_row39_4 = 1'h0; + reg pp_row39_5 = 1'h0; + reg pp_row39_6 = 1'h0; + reg pp_row39_7 = 1'h0; + reg pp_row39_8 = 1'h0; + reg pp_row39_9 = 1'h0; + reg pp_row3_0 = 1'h0; + reg pp_row3_1 = 1'h0; + wire pp_row40_0; + reg pp_row40_1 = 1'h0; + reg pp_row40_10 = 1'h0; + reg pp_row40_11 = 1'h0; + reg pp_row40_12 = 1'h0; + reg pp_row40_13 = 1'h0; + reg pp_row40_2 = 1'h0; + reg pp_row40_3 = 1'h0; + reg pp_row40_4 = 1'h0; + reg pp_row40_5 = 1'h0; + reg pp_row40_6 = 1'h0; + reg pp_row40_7 = 1'h0; + reg pp_row40_8 = 1'h0; + reg pp_row40_9 = 1'h0; + reg pp_row41_0 = 1'h0; + reg pp_row41_1 = 1'h0; + reg pp_row41_10 = 1'h0; + reg pp_row41_11 = 1'h0; + reg pp_row41_12 = 1'h0; + reg pp_row41_2 = 1'h0; + reg pp_row41_3 = 1'h0; + reg pp_row41_4 = 1'h0; + reg pp_row41_5 = 1'h0; + reg pp_row41_6 = 1'h0; + reg pp_row41_7 = 1'h0; + reg pp_row41_8 = 1'h0; + reg pp_row41_9 = 1'h0; + wire pp_row42_0; + reg pp_row42_1 = 1'h0; + reg pp_row42_10 = 1'h0; + reg pp_row42_11 = 1'h0; + reg pp_row42_12 = 1'h0; + reg pp_row42_2 = 1'h0; + reg pp_row42_3 = 1'h0; + reg pp_row42_4 = 1'h0; + reg pp_row42_5 = 1'h0; + reg pp_row42_6 = 1'h0; + reg pp_row42_7 = 1'h0; + reg pp_row42_8 = 1'h0; + reg pp_row42_9 = 1'h0; + reg pp_row43_0 = 1'h0; + reg pp_row43_1 = 1'h0; + reg pp_row43_10 = 1'h0; + reg pp_row43_11 = 1'h0; + reg pp_row43_2 = 1'h0; + reg pp_row43_3 = 1'h0; + reg pp_row43_4 = 1'h0; + reg pp_row43_5 = 1'h0; + reg pp_row43_6 = 1'h0; + reg pp_row43_7 = 1'h0; + reg pp_row43_8 = 1'h0; + reg pp_row43_9 = 1'h0; + wire pp_row44_0; + reg pp_row44_1 = 1'h0; + reg pp_row44_10 = 1'h0; + reg pp_row44_11 = 1'h0; + reg pp_row44_2 = 1'h0; + reg pp_row44_3 = 1'h0; + reg pp_row44_4 = 1'h0; + reg pp_row44_5 = 1'h0; + reg pp_row44_6 = 1'h0; + reg pp_row44_7 = 1'h0; + reg pp_row44_8 = 1'h0; + reg pp_row44_9 = 1'h0; + reg pp_row45_0 = 1'h0; + reg pp_row45_1 = 1'h0; + reg pp_row45_10 = 1'h0; + reg pp_row45_2 = 1'h0; + reg pp_row45_3 = 1'h0; + reg pp_row45_4 = 1'h0; + reg pp_row45_5 = 1'h0; + reg pp_row45_6 = 1'h0; + reg pp_row45_7 = 1'h0; + reg pp_row45_8 = 1'h0; + reg pp_row45_9 = 1'h0; + wire pp_row46_0; + reg pp_row46_1 = 1'h0; + reg pp_row46_10 = 1'h0; + reg pp_row46_2 = 1'h0; + reg pp_row46_3 = 1'h0; + reg pp_row46_4 = 1'h0; + reg pp_row46_5 = 1'h0; + reg pp_row46_6 = 1'h0; + reg pp_row46_7 = 1'h0; + reg pp_row46_8 = 1'h0; + reg pp_row46_9 = 1'h0; + reg pp_row47_0 = 1'h0; + reg pp_row47_1 = 1'h0; + reg pp_row47_2 = 1'h0; + reg pp_row47_3 = 1'h0; + reg pp_row47_4 = 1'h0; + reg pp_row47_5 = 1'h0; + reg pp_row47_6 = 1'h0; + reg pp_row47_7 = 1'h0; + reg pp_row47_8 = 1'h0; + reg pp_row47_9 = 1'h0; + wire pp_row48_0; + reg pp_row48_1 = 1'h0; + reg pp_row48_2 = 1'h0; + reg pp_row48_3 = 1'h0; + reg pp_row48_4 = 1'h0; + reg pp_row48_5 = 1'h0; + reg pp_row48_6 = 1'h0; + reg pp_row48_7 = 1'h0; + reg pp_row48_8 = 1'h0; + reg pp_row48_9 = 1'h0; + reg pp_row49_0 = 1'h0; + reg pp_row49_1 = 1'h0; + reg pp_row49_2 = 1'h0; + reg pp_row49_3 = 1'h0; + reg pp_row49_4 = 1'h0; + reg pp_row49_5 = 1'h0; + reg pp_row49_6 = 1'h0; + reg pp_row49_7 = 1'h0; + reg pp_row49_8 = 1'h0; + reg pp_row4_0 = 1'h0; + reg pp_row4_1 = 1'h0; + reg pp_row4_2 = 1'h0; + reg pp_row4_3 = 1'h0; + wire pp_row50_0; + reg pp_row50_1 = 1'h0; + reg pp_row50_2 = 1'h0; + reg pp_row50_3 = 1'h0; + reg pp_row50_4 = 1'h0; + reg pp_row50_5 = 1'h0; + reg pp_row50_6 = 1'h0; + reg pp_row50_7 = 1'h0; + reg pp_row50_8 = 1'h0; + reg pp_row51_0 = 1'h0; + reg pp_row51_1 = 1'h0; + reg pp_row51_2 = 1'h0; + reg pp_row51_3 = 1'h0; + reg pp_row51_4 = 1'h0; + reg pp_row51_5 = 1'h0; + reg pp_row51_6 = 1'h0; + reg pp_row51_7 = 1'h0; + wire pp_row52_0; + reg pp_row52_1 = 1'h0; + reg pp_row52_2 = 1'h0; + reg pp_row52_3 = 1'h0; + reg pp_row52_4 = 1'h0; + reg pp_row52_5 = 1'h0; + reg pp_row52_6 = 1'h0; + reg pp_row52_7 = 1'h0; + reg pp_row53_0 = 1'h0; + reg pp_row53_1 = 1'h0; + reg pp_row53_2 = 1'h0; + reg pp_row53_3 = 1'h0; + reg pp_row53_4 = 1'h0; + reg pp_row53_5 = 1'h0; + reg pp_row53_6 = 1'h0; + wire pp_row54_0; + reg pp_row54_1 = 1'h0; + reg pp_row54_2 = 1'h0; + reg pp_row54_3 = 1'h0; + reg pp_row54_4 = 1'h0; + reg pp_row54_5 = 1'h0; + reg pp_row54_6 = 1'h0; + reg pp_row55_0 = 1'h0; + reg pp_row55_1 = 1'h0; + reg pp_row55_2 = 1'h0; + reg pp_row55_3 = 1'h0; + reg pp_row55_4 = 1'h0; + reg pp_row55_5 = 1'h0; + wire pp_row56_0; + reg pp_row56_1 = 1'h0; + reg pp_row56_2 = 1'h0; + reg pp_row56_3 = 1'h0; + reg pp_row56_4 = 1'h0; + reg pp_row56_5 = 1'h0; + reg pp_row57_0 = 1'h0; + reg pp_row57_1 = 1'h0; + reg pp_row57_2 = 1'h0; + reg pp_row57_3 = 1'h0; + reg pp_row57_4 = 1'h0; + wire pp_row58_0; + reg pp_row58_1 = 1'h0; + reg pp_row58_2 = 1'h0; + reg pp_row58_3 = 1'h0; + reg pp_row58_4 = 1'h0; + reg pp_row59_0 = 1'h0; + reg pp_row59_1 = 1'h0; + reg pp_row59_2 = 1'h0; + reg pp_row59_3 = 1'h0; + reg pp_row5_0 = 1'h0; + reg pp_row5_1 = 1'h0; + reg pp_row5_2 = 1'h0; + wire pp_row60_0; + reg pp_row60_1 = 1'h0; + reg pp_row60_2 = 1'h0; + reg pp_row60_3 = 1'h0; + reg pp_row61_0 = 1'h0; + reg pp_row61_1 = 1'h0; + reg pp_row61_2 = 1'h0; + wire pp_row62_0; + reg pp_row62_1 = 1'h0; + reg pp_row62_2 = 1'h0; + reg pp_row63_0 = 1'h0; + reg pp_row63_1 = 1'h0; + wire pp_row64_0; + reg pp_row64_1 = 1'h0; + reg pp_row6_0 = 1'h0; + reg pp_row6_1 = 1'h0; + reg pp_row6_2 = 1'h0; + reg pp_row6_3 = 1'h0; + reg pp_row6_4 = 1'h0; + reg pp_row7_0 = 1'h0; + reg pp_row7_1 = 1'h0; + reg pp_row7_2 = 1'h0; + reg pp_row7_3 = 1'h0; + reg pp_row8_0 = 1'h0; + reg pp_row8_1 = 1'h0; + reg pp_row8_2 = 1'h0; + reg pp_row8_3 = 1'h0; + reg pp_row8_4 = 1'h0; + reg pp_row8_5 = 1'h0; + reg pp_row9_0 = 1'h0; + reg pp_row9_1 = 1'h0; + reg pp_row9_2 = 1'h0; + reg pp_row9_3 = 1'h0; + reg pp_row9_4 = 1'h0; + wire [63:0] result; + (* init = 64'h0000000000000000 *) + wire [63:0] result_registered; + input rst; + wire rst; + wire s; + wire \s$1260 ; + wire \s$1261 ; + wire \s$1262 ; + wire \s$1263 ; + wire \s$1264 ; + wire \s$1265 ; + wire \s$1266 ; + wire \s$1267 ; + wire \s$1268 ; + wire \s$1269 ; + wire \s$1270 ; + wire \s$1271 ; + wire \s$1272 ; + wire \s$1273 ; + wire \s$1274 ; + wire \s$1275 ; + wire \s$1276 ; + wire \s$1277 ; + wire \s$1278 ; + wire \s$1279 ; + wire \s$1280 ; + wire \s$1281 ; + wire \s$1282 ; + wire \s$1283 ; + wire \s$1284 ; + wire \s$1285 ; + wire \s$1286 ; + wire \s$1287 ; + wire \s$1288 ; + wire \s$1289 ; + wire \s$1290 ; + wire \s$1291 ; + wire \s$1292 ; + wire \s$1293 ; + wire \s$1294 ; + wire \s$1295 ; + wire \s$1296 ; + wire \s$1297 ; + wire \s$1298 ; + wire \s$1299 ; + wire \s$1300 ; + wire \s$1301 ; + wire \s$1302 ; + wire \s$1303 ; + wire \s$1304 ; + wire \s$1305 ; + wire \s$1306 ; + wire \s$1307 ; + wire \s$1308 ; + wire \s$1309 ; + wire \s$1310 ; + wire \s$1311 ; + wire \s$1312 ; + wire \s$1313 ; + wire \s$1314 ; + wire \s$1315 ; + wire \s$1316 ; + wire \s$1317 ; + wire \s$1318 ; + wire \s$1319 ; + wire \s$1320 ; + wire \s$1321 ; + wire \s$2555 ; + wire \s$2559 ; + wire \s$2563 ; + wire \s$2567 ; + wire \s$2571 ; + wire \s$2575 ; + wire \s$2579 ; + wire \s$2583 ; + wire \s$2587 ; + wire \s$2591 ; + wire \s$2595 ; + wire \s$2599 ; + wire \s$2603 ; + wire \s$2607 ; + wire \s$2611 ; + wire \s$2615 ; + wire \s$2619 ; + wire \s$2623 ; + wire \s$2627 ; + wire \s$2631 ; + wire \s$2635 ; + wire \s$2639 ; + wire \s$2643 ; + wire \s$2647 ; + wire \s$2651 ; + wire \s$2655 ; + wire \s$2659 ; + wire \s$2663 ; + wire \s$2667 ; + wire \s$2671 ; + wire \s$2675 ; + wire \s$2679 ; + wire \s$2683 ; + wire \s$2687 ; + wire \s$2691 ; + wire \s$2695 ; + wire \s$2699 ; + wire \s$2703 ; + wire \s$2707 ; + wire \s$2711 ; + wire \s$2715 ; + wire \s$2719 ; + wire \s$2723 ; + wire \s$2727 ; + wire \s$2731 ; + wire \s$2735 ; + wire \s$2739 ; + wire \s$2743 ; + wire \s$2747 ; + wire \s$2751 ; + wire \s$2755 ; + wire \s$2759 ; + wire \s$2763 ; + wire \s$2767 ; + wire \s$2771 ; + wire \s$2775 ; + wire \s$2779 ; + wire \s$2783 ; + wire \s$2787 ; + wire \s$2791 ; + wire \s$2795 ; + wire \s$2799 ; + wire \s$2803 ; + wire \s$2807 ; + wire \s$2811 ; + wire \s$2815 ; + wire \s$2819 ; + wire \s$2823 ; + wire \s$2827 ; + wire \s$2831 ; + wire \s$2835 ; + wire \s$2839 ; + wire \s$2843 ; + wire \s$2847 ; + wire \s$2851 ; + wire \s$2855 ; + wire \s$2859 ; + wire \s$2863 ; + wire \s$2867 ; + wire \s$2871 ; + wire \s$2875 ; + wire \s$2879 ; + wire \s$2883 ; + wire \s$2887 ; + wire \s$2891 ; + wire \s$2895 ; + wire \s$2899 ; + wire \s$2903 ; + wire \s$2907 ; + wire \s$2911 ; + wire \s$2915 ; + wire \s$2919 ; + wire \s$2923 ; + wire \s$2927 ; + wire \s$2931 ; + wire \s$2935 ; + wire \s$2939 ; + wire \s$2943 ; + wire \s$2947 ; + wire \s$2951 ; + wire \s$2955 ; + wire \s$2959 ; + wire \s$2963 ; + wire \s$2967 ; + wire \s$2971 ; + wire \s$2975 ; + wire \s$2979 ; + wire \s$2983 ; + wire \s$2987 ; + wire \s$2991 ; + wire \s$2995 ; + wire \s$2999 ; + wire \s$3003 ; + wire \s$3007 ; + wire \s$3011 ; + wire \s$3015 ; + wire \s$3019 ; + wire \s$3023 ; + wire \s$3027 ; + wire \s$3031 ; + wire \s$3035 ; + wire \s$3039 ; + wire \s$3043 ; + wire \s$3047 ; + wire \s$3051 ; + wire \s$3055 ; + wire \s$3059 ; + wire \s$3063 ; + wire \s$3067 ; + wire \s$3071 ; + wire \s$3075 ; + wire \s$3079 ; + wire \s$3083 ; + wire \s$3087 ; + wire \s$3091 ; + wire \s$3095 ; + wire \s$3099 ; + wire \s$3103 ; + wire \s$3107 ; + wire \s$3111 ; + wire \s$3115 ; + wire \s$3119 ; + wire \s$3123 ; + wire \s$3127 ; + wire \s$3131 ; + wire \s$3135 ; + wire \s$3139 ; + wire \s$3143 ; + wire \s$3147 ; + wire \s$3151 ; + wire \s$3155 ; + wire \s$3159 ; + wire \s$3163 ; + wire \s$3167 ; + wire \s$3171 ; + wire \s$3175 ; + wire \s$3179 ; + wire \s$3183 ; + wire \s$3187 ; + wire \s$3191 ; + wire \s$3195 ; + wire \s$3199 ; + wire \s$3203 ; + wire \s$3207 ; + wire \s$3211 ; + wire \s$3215 ; + wire \s$3219 ; + wire \s$3223 ; + wire \s$3227 ; + wire \s$3231 ; + wire \s$3235 ; + wire \s$3239 ; + wire \s$3243 ; + wire \s$3247 ; + wire \s$3251 ; + wire \s$3255 ; + wire \s$3259 ; + wire \s$3263 ; + wire \s$3267 ; + wire \s$3271 ; + wire \s$3275 ; + wire \s$3279 ; + wire \s$3283 ; + wire \s$3287 ; + wire \s$3291 ; + wire \s$3295 ; + wire \s$3299 ; + wire \s$3303 ; + wire \s$3307 ; + wire \s$3311 ; + wire \s$3315 ; + wire \s$3319 ; + wire \s$3323 ; + wire \s$3327 ; + wire \s$3331 ; + wire \s$3335 ; + wire \s$3339 ; + wire \s$3343 ; + wire \s$3347 ; + wire \s$3351 ; + wire \s$3355 ; + wire \s$3359 ; + wire \s$3363 ; + wire \s$3367 ; + wire \s$3371 ; + wire \s$3375 ; + wire \s$3379 ; + wire \s$3383 ; + wire \s$3387 ; + wire \s$3391 ; + wire \s$3395 ; + wire \s$3399 ; + wire \s$3403 ; + wire \s$3407 ; + wire \s$3411 ; + wire \s$3415 ; + wire \s$3419 ; + wire \s$3423 ; + wire \s$3427 ; + wire \s$3431 ; + wire \s$3435 ; + wire \s$3439 ; + wire \s$3443 ; + wire \s$3447 ; + wire \s$3451 ; + wire \s$3455 ; + wire \s$3459 ; + wire \s$3463 ; + wire \s$3467 ; + wire \s$3471 ; + wire \s$3475 ; + wire \s$3479 ; + wire \s$3483 ; + wire \s$3487 ; + wire \s$3491 ; + wire \s$3495 ; + wire \s$3499 ; + wire \s$3503 ; + wire \s$3507 ; + wire \s$3511 ; + wire \s$3515 ; + wire \s$3519 ; + wire \s$3523 ; + wire \s$3527 ; + wire \s$3531 ; + wire \s$3535 ; + wire \s$3539 ; + wire \s$3543 ; + wire \s$3547 ; + wire \s$3551 ; + wire \s$3555 ; + wire \s$3559 ; + wire \s$3563 ; + wire \s$3567 ; + wire \s$3571 ; + wire \s$3575 ; + wire \s$3579 ; + wire \s$3583 ; + wire \s$3587 ; + wire \s$3591 ; + wire \s$3595 ; + wire \s$3599 ; + wire \s$3603 ; + wire \s$3607 ; + wire \s$3611 ; + wire \s$3615 ; + wire \s$3619 ; + wire \s$3623 ; + wire \s$3627 ; + wire \s$3631 ; + wire \s$3635 ; + wire \s$3639 ; + wire \s$3643 ; + wire \s$3647 ; + wire \s$3651 ; + wire \s$3655 ; + wire \s$3659 ; + wire \s$3663 ; + wire \s$3667 ; + wire \s$3671 ; + wire \s$3675 ; + wire \s$3679 ; + wire \s$3683 ; + wire \s$3687 ; + wire \s$3691 ; + wire \s$3695 ; + wire \s$3699 ; + wire \s$3703 ; + wire \s$3707 ; + wire \s$3711 ; + wire \s$3715 ; + wire \s$3719 ; + wire \s$3723 ; + wire \s$3727 ; + wire \s$3731 ; + wire \s$3735 ; + wire \s$3739 ; + wire \s$3743 ; + wire \s$3747 ; + wire \s$3751 ; + wire \s$3755 ; + wire \s$3759 ; + wire \s$3763 ; + wire \s$3767 ; + wire \s$3771 ; + wire \s$3775 ; + wire \s$3779 ; + wire \s$3783 ; + wire \s$3787 ; + wire \s$3791 ; + wire \s$3795 ; + wire \s$3799 ; + wire \s$3803 ; + wire \s$3807 ; + wire \s$3811 ; + wire \s$3815 ; + wire \s$3819 ; + wire \s$3823 ; + wire \s$3827 ; + wire \s$3831 ; + wire \s$3835 ; + wire \s$3839 ; + wire \s$3843 ; + wire \s$3847 ; + wire \s$3851 ; + wire \s$3855 ; + wire \s$3859 ; + wire \s$3863 ; + wire \s$3867 ; + wire \s$3871 ; + wire \s$3875 ; + wire \s$3879 ; + wire \s$3883 ; + wire \s$3887 ; + wire \s$3891 ; + wire \s$3895 ; + wire \s$3899 ; + wire \s$3903 ; + wire \s$3907 ; + wire \s$3911 ; + wire \s$3915 ; + wire \s$3919 ; + wire \s$3923 ; + wire \s$3927 ; + wire \s$3931 ; + wire \s$3935 ; + wire \s$3939 ; + wire \s$3943 ; + wire \s$3947 ; + wire \s$3951 ; + wire \s$3955 ; + wire \s$3959 ; + wire \s$3963 ; + wire \s$3967 ; + wire \s$3971 ; + wire \s$3975 ; + wire \s$3979 ; + wire \s$3983 ; + wire \s$3987 ; + wire \s$3991 ; + wire \s$3995 ; + wire \s$3999 ; + wire \s$4003 ; + wire \s$4007 ; + wire \s$4011 ; + wire \s$4015 ; + wire \s$4019 ; + wire \s$4023 ; + wire \s$4027 ; + wire \s$4031 ; + wire \s$4035 ; + wire \s$4039 ; + wire \s$4043 ; + wire \s$4047 ; + wire \s$4051 ; + wire \s$4055 ; + wire \s$4059 ; + wire \s$4063 ; + wire \s$4067 ; + wire \s$4071 ; + wire \s$4075 ; + wire \s$4079 ; + wire \s$4083 ; + wire \s$4087 ; + wire \s$4091 ; + wire \s$4095 ; + wire \s$4099 ; + wire \s$4103 ; + wire \s$4107 ; + wire \s$4111 ; + wire \s$4115 ; + wire \s$4119 ; + wire \s$4123 ; + wire \s$4127 ; + wire \s$4131 ; + wire \s$4135 ; + wire \s$4139 ; + wire \s$4143 ; + wire \s$4147 ; + wire \s$4151 ; + wire \s$4155 ; + wire \s$4159 ; + wire \s$4163 ; + wire \s$4167 ; + wire \s$4171 ; + wire \s$4175 ; + wire \s$4179 ; + wire \s$4183 ; + wire \s$4187 ; + wire \s$4191 ; + wire \s$4195 ; + wire \s$4199 ; + wire \s$4203 ; + wire \s$4207 ; + wire \s$4211 ; + wire \s$4215 ; + wire \s$4219 ; + wire \s$4223 ; + wire \s$4227 ; + wire \s$4231 ; + wire \s$4235 ; + wire \s$4239 ; + wire \s$4243 ; + wire \s$4247 ; + wire \s$4251 ; + wire \s$4255 ; + wire \s$4259 ; + wire \s$4263 ; + wire \s$4267 ; + wire \s$4271 ; + wire \s$4275 ; + wire \s$4279 ; + wire \s$4283 ; + wire \s$4287 ; + wire \s$4291 ; + wire \s$4295 ; + wire \s$4299 ; + wire \s$4303 ; + wire \s$4307 ; + wire \s$4311 ; + wire \s$4315 ; + wire \s$4319 ; + wire \s$4323 ; + wire \s$4327 ; + wire \s$4331 ; + wire \s$4335 ; + wire \s$4339 ; + wire \s$4343 ; + wire \s$4347 ; + wire \s$4351 ; + wire \s$4355 ; + wire \s$4359 ; + wire \s$4363 ; + wire \s$4367 ; + wire \s$4371 ; + wire \s$4375 ; + wire \s$4379 ; + wire \s$4383 ; + wire \s$4387 ; + wire \s$4391 ; + wire \s$4395 ; + wire \s$4399 ; + wire sel_0; + wire \sel_0$1365 ; + wire \sel_0$1402 ; + wire \sel_0$1439 ; + wire \sel_0$1476 ; + wire \sel_0$1513 ; + wire \sel_0$1550 ; + wire \sel_0$1587 ; + wire \sel_0$1624 ; + wire \sel_0$1661 ; + wire \sel_0$1698 ; + wire \sel_0$1735 ; + wire \sel_0$1772 ; + wire \sel_0$1809 ; + wire \sel_0$1846 ; + wire \sel_0$1883 ; + wire \sel_0$1921 ; + wire sel_1; + wire \sel_1$1366 ; + wire \sel_1$1403 ; + wire \sel_1$1440 ; + wire \sel_1$1477 ; + wire \sel_1$1514 ; + wire \sel_1$1551 ; + wire \sel_1$1588 ; + wire \sel_1$1625 ; + wire \sel_1$1662 ; + wire \sel_1$1699 ; + wire \sel_1$1736 ; + wire \sel_1$1773 ; + wire \sel_1$1810 ; + wire \sel_1$1847 ; + wire \sel_1$1884 ; + wire \sel_1$1922 ; + wire sn; + wire \sn$2558 ; + wire \sn$2562 ; + wire \sn$2566 ; + wire \sn$2570 ; + wire \sn$2574 ; + wire \sn$2578 ; + wire \sn$2582 ; + wire \sn$2586 ; + wire \sn$2590 ; + wire \sn$2594 ; + wire \sn$2598 ; + wire \sn$2602 ; + wire \sn$2606 ; + wire \sn$2610 ; + wire \sn$2614 ; + wire \sn$2618 ; + wire \sn$2622 ; + wire \sn$2626 ; + wire \sn$2630 ; + wire \sn$2634 ; + wire \sn$2638 ; + wire \sn$2642 ; + wire \sn$2646 ; + wire \sn$2650 ; + wire \sn$2654 ; + wire \sn$2658 ; + wire \sn$2662 ; + wire \sn$2666 ; + wire \sn$2670 ; + wire \sn$2674 ; + wire \sn$2678 ; + wire \sn$2682 ; + wire \sn$2686 ; + wire \sn$2690 ; + wire \sn$2694 ; + wire \sn$2698 ; + wire \sn$2702 ; + wire \sn$2706 ; + wire \sn$2710 ; + wire \sn$2714 ; + wire \sn$2718 ; + wire \sn$2722 ; + wire \sn$2726 ; + wire \sn$2730 ; + wire \sn$2734 ; + wire \sn$2738 ; + wire \sn$2742 ; + wire \sn$2746 ; + wire \sn$2750 ; + wire \sn$2754 ; + wire \sn$2758 ; + wire \sn$2762 ; + wire \sn$2766 ; + wire \sn$2770 ; + wire \sn$2774 ; + wire \sn$2778 ; + wire \sn$2782 ; + wire \sn$2786 ; + wire \sn$2790 ; + wire \sn$2794 ; + wire \sn$2798 ; + wire \sn$2802 ; + wire \sn$2806 ; + wire \sn$2810 ; + wire \sn$2814 ; + wire \sn$2818 ; + wire \sn$2822 ; + wire \sn$2826 ; + wire \sn$2830 ; + wire \sn$2834 ; + wire \sn$2838 ; + wire \sn$2842 ; + wire \sn$2846 ; + wire \sn$2850 ; + wire \sn$2854 ; + wire \sn$2858 ; + wire \sn$2862 ; + wire \sn$2866 ; + wire \sn$2870 ; + wire \sn$2874 ; + wire \sn$2878 ; + wire \sn$2882 ; + wire \sn$2886 ; + wire \sn$2890 ; + wire \sn$2894 ; + wire \sn$2898 ; + wire \sn$2902 ; + wire \sn$2906 ; + wire \sn$2910 ; + wire \sn$2914 ; + wire \sn$2918 ; + wire \sn$2922 ; + wire \sn$2926 ; + wire \sn$2930 ; + wire \sn$2934 ; + wire \sn$2938 ; + wire \sn$2942 ; + wire \sn$2946 ; + wire \sn$2950 ; + wire \sn$2954 ; + wire \sn$2958 ; + wire \sn$2962 ; + wire \sn$2966 ; + wire \sn$2970 ; + wire \sn$2974 ; + wire \sn$2978 ; + wire \sn$2982 ; + wire \sn$2986 ; + wire \sn$2990 ; + wire \sn$2994 ; + wire \sn$2998 ; + wire \sn$3002 ; + wire \sn$3006 ; + wire \sn$3010 ; + wire \sn$3014 ; + wire \sn$3018 ; + wire \sn$3022 ; + wire \sn$3026 ; + wire \sn$3030 ; + wire \sn$3034 ; + wire \sn$3038 ; + wire \sn$3042 ; + wire \sn$3046 ; + wire \sn$3050 ; + wire \sn$3054 ; + wire \sn$3058 ; + wire \sn$3062 ; + wire \sn$3066 ; + wire \sn$3070 ; + wire \sn$3074 ; + wire \sn$3078 ; + wire \sn$3082 ; + wire \sn$3086 ; + wire \sn$3090 ; + wire \sn$3094 ; + wire \sn$3098 ; + wire \sn$3102 ; + wire \sn$3106 ; + wire \sn$3110 ; + wire \sn$3114 ; + wire \sn$3118 ; + wire \sn$3122 ; + wire \sn$3126 ; + wire \sn$3130 ; + wire \sn$3134 ; + wire \sn$3138 ; + wire \sn$3142 ; + wire \sn$3146 ; + wire \sn$3150 ; + wire \sn$3154 ; + wire \sn$3158 ; + wire \sn$3162 ; + wire \sn$3166 ; + wire \sn$3170 ; + wire \sn$3174 ; + wire \sn$3178 ; + wire \sn$3182 ; + wire \sn$3186 ; + wire \sn$3190 ; + wire \sn$3194 ; + wire \sn$3198 ; + wire \sn$3202 ; + wire \sn$3206 ; + wire \sn$3210 ; + wire \sn$3214 ; + wire \sn$3218 ; + wire \sn$3222 ; + wire \sn$3226 ; + wire \sn$3230 ; + wire \sn$3234 ; + wire \sn$3238 ; + wire \sn$3242 ; + wire \sn$3246 ; + wire \sn$3250 ; + wire \sn$3254 ; + wire \sn$3258 ; + wire \sn$3262 ; + wire \sn$3266 ; + wire \sn$3270 ; + wire \sn$3274 ; + wire \sn$3278 ; + wire \sn$3282 ; + wire \sn$3286 ; + wire \sn$3290 ; + wire \sn$3294 ; + wire \sn$3298 ; + wire \sn$3302 ; + wire \sn$3306 ; + wire \sn$3310 ; + wire \sn$3314 ; + wire \sn$3318 ; + wire \sn$3322 ; + wire \sn$3326 ; + wire \sn$3330 ; + wire \sn$3334 ; + wire \sn$3338 ; + wire \sn$3342 ; + wire \sn$3346 ; + wire \sn$3350 ; + wire \sn$3354 ; + wire \sn$3358 ; + wire \sn$3362 ; + wire \sn$3366 ; + wire \sn$3370 ; + wire \sn$3374 ; + wire \sn$3378 ; + wire \sn$3382 ; + wire \sn$3386 ; + wire \sn$3390 ; + wire \sn$3394 ; + wire \sn$3398 ; + wire \sn$3402 ; + wire \sn$3406 ; + wire \sn$3410 ; + wire \sn$3414 ; + wire \sn$3418 ; + wire \sn$3422 ; + wire \sn$3426 ; + wire \sn$3430 ; + wire \sn$3434 ; + wire \sn$3438 ; + wire \sn$3442 ; + wire \sn$3446 ; + wire \sn$3450 ; + wire \sn$3454 ; + wire \sn$3458 ; + wire \sn$3462 ; + wire \sn$3466 ; + wire \sn$3470 ; + wire \sn$3474 ; + wire \sn$3478 ; + wire \sn$3482 ; + wire \sn$3486 ; + wire \sn$3490 ; + wire \sn$3494 ; + wire \sn$3498 ; + wire \sn$3502 ; + wire \sn$3506 ; + wire \sn$3510 ; + wire \sn$3514 ; + wire \sn$3518 ; + wire \sn$3522 ; + wire \sn$3526 ; + wire \sn$3530 ; + wire \sn$3534 ; + wire \sn$3538 ; + wire \sn$3542 ; + wire \sn$3546 ; + wire \sn$3550 ; + wire \sn$3554 ; + wire \sn$3558 ; + wire \sn$3562 ; + wire \sn$3566 ; + wire \sn$3570 ; + wire \sn$3574 ; + wire \sn$3578 ; + wire \sn$3582 ; + wire \sn$3586 ; + wire \sn$3590 ; + wire \sn$3594 ; + wire \sn$3598 ; + wire \sn$3602 ; + wire \sn$3606 ; + wire \sn$3610 ; + wire \sn$3614 ; + wire \sn$3618 ; + wire \sn$3622 ; + wire \sn$3626 ; + wire \sn$3630 ; + wire \sn$3634 ; + wire \sn$3638 ; + wire \sn$3642 ; + wire \sn$3646 ; + wire \sn$3650 ; + wire \sn$3654 ; + wire \sn$3658 ; + wire \sn$3662 ; + wire \sn$3666 ; + wire \sn$3670 ; + wire \sn$3674 ; + wire \sn$3678 ; + wire \sn$3682 ; + wire \sn$3686 ; + wire \sn$3690 ; + wire \sn$3694 ; + wire \sn$3698 ; + wire \sn$3702 ; + wire \sn$3706 ; + wire \sn$3710 ; + wire \sn$3714 ; + wire \sn$3718 ; + wire \sn$3722 ; + wire \sn$3726 ; + wire \sn$3730 ; + wire \sn$3734 ; + wire \sn$3738 ; + wire \sn$3742 ; + wire \sn$3746 ; + wire \sn$3750 ; + wire \sn$3754 ; + wire \sn$3758 ; + wire \sn$3762 ; + wire \sn$3766 ; + wire \sn$3770 ; + wire \sn$3774 ; + wire \sn$3778 ; + wire \sn$3782 ; + wire \sn$3786 ; + wire \sn$3790 ; + wire \sn$3794 ; + wire \sn$3798 ; + wire \sn$3802 ; + wire \sn$3806 ; + wire \sn$3810 ; + wire \sn$3814 ; + wire \sn$3818 ; + wire \sn$3822 ; + wire \sn$3826 ; + wire \sn$3830 ; + wire \sn$3834 ; + wire \sn$3838 ; + wire \sn$3842 ; + wire \sn$3846 ; + wire \sn$3850 ; + wire \sn$3854 ; + wire \sn$3858 ; + wire \sn$3862 ; + wire \sn$3866 ; + wire \sn$3870 ; + wire \sn$3874 ; + wire \sn$3878 ; + wire \sn$3882 ; + wire \sn$3886 ; + wire \sn$3890 ; + wire \sn$3894 ; + wire \sn$3898 ; + wire \sn$3902 ; + wire \sn$3906 ; + wire \sn$3910 ; + wire \sn$3914 ; + wire \sn$3918 ; + wire \sn$3922 ; + wire \sn$3926 ; + wire \sn$3930 ; + wire \sn$3934 ; + wire \sn$3938 ; + wire \sn$3942 ; + wire \sn$3946 ; + wire \sn$3950 ; + wire \sn$3954 ; + wire \sn$3958 ; + wire \sn$3962 ; + wire \sn$3966 ; + wire \sn$3970 ; + wire \sn$3974 ; + wire \sn$3978 ; + wire \sn$3982 ; + wire \sn$3986 ; + wire \sn$3990 ; + wire \sn$3994 ; + wire \sn$3998 ; + wire \sn$4002 ; + wire \sn$4006 ; + wire \sn$4010 ; + wire \sn$4014 ; + wire \sn$4018 ; + wire \sn$4022 ; + wire \sn$4026 ; + wire \sn$4030 ; + wire \sn$4034 ; + wire \sn$4038 ; + wire \sn$4042 ; + wire \sn$4046 ; + wire \sn$4050 ; + wire \sn$4054 ; + wire \sn$4058 ; + wire \sn$4062 ; + wire \sn$4066 ; + wire \sn$4070 ; + wire \sn$4074 ; + wire \sn$4078 ; + wire \sn$4082 ; + wire \sn$4086 ; + wire \sn$4090 ; + wire \sn$4094 ; + wire \sn$4098 ; + wire \sn$4102 ; + wire \sn$4106 ; + wire \sn$4110 ; + wire \sn$4114 ; + wire \sn$4118 ; + wire \sn$4122 ; + wire \sn$4126 ; + wire \sn$4130 ; + wire \sn$4134 ; + wire \sn$4138 ; + wire \sn$4142 ; + wire \sn$4146 ; + wire \sn$4150 ; + wire \sn$4154 ; + wire \sn$4158 ; + wire \sn$4162 ; + wire \sn$4166 ; + wire \sn$4170 ; + wire \sn$4174 ; + wire \sn$4178 ; + wire \sn$4182 ; + wire \sn$4186 ; + wire \sn$4190 ; + wire \sn$4194 ; + wire \sn$4198 ; + wire \sn$4202 ; + wire \sn$4206 ; + wire \sn$4210 ; + wire \sn$4214 ; + wire \sn$4218 ; + wire \sn$4222 ; + wire \sn$4226 ; + wire \sn$4230 ; + wire \sn$4234 ; + wire \sn$4238 ; + wire \sn$4242 ; + wire \sn$4246 ; + wire \sn$4250 ; + wire \sn$4254 ; + wire \sn$4258 ; + wire \sn$4262 ; + wire \sn$4266 ; + wire \sn$4270 ; + wire \sn$4274 ; + wire \sn$4278 ; + wire \sn$4282 ; + wire \sn$4286 ; + wire \sn$4290 ; + wire \sn$4294 ; + wire \sn$4298 ; + wire \sn$4302 ; + wire \sn$4306 ; + wire \sn$4310 ; + wire \sn$4314 ; + wire \sn$4318 ; + wire \sn$4322 ; + wire \sn$4326 ; + wire \sn$4330 ; + wire \sn$4334 ; + wire \sn$4338 ; + wire \sn$4342 ; + wire \sn$4346 ; + wire \sn$4350 ; + wire \sn$4354 ; + wire \sn$4358 ; + wire \sn$4362 ; + wire \sn$4366 ; + wire \sn$4370 ; + wire \sn$4374 ; + wire \sn$4378 ; + wire \sn$4382 ; + wire \sn$4386 ; + wire \sn$4390 ; + wire \sn$4394 ; + wire \sn$4398 ; + wire \sn$4401 ; + wire \sn$4403 ; + wire \sn$4405 ; + wire \sn$4407 ; + wire \sn$4409 ; + wire \sn$4411 ; + wire \sn$4413 ; + wire \sn$4415 ; + wire \sn$4417 ; + wire \sn$4419 ; + wire \sn$4421 ; + wire \sn$4423 ; + wire \sn$4425 ; + wire \sn$4427 ; + wire \sn$4429 ; + wire \sn$4431 ; + wire \sn$4433 ; + wire \sn$4435 ; + wire \sn$4437 ; + wire \sn$4439 ; + wire \sn$4441 ; + wire \sn$4443 ; + wire \sn$4445 ; + wire \sn$4447 ; + wire \sn$4449 ; + wire \sn$4451 ; + wire \sn$4453 ; + wire \sn$4455 ; + wire \sn$4457 ; + wire \sn$4459 ; + wire \sn$4461 ; + wire \sn$4463 ; + wire \sn$4465 ; + wire \sn$4467 ; + wire \sn$4469 ; + wire \sn$4471 ; + wire \sn$4473 ; + wire \sn$4475 ; + wire \sn$4477 ; + wire \sn$4479 ; + wire \sn$4481 ; + wire \sn$4483 ; + wire \sn$4485 ; + wire \sn$4487 ; + wire \sn$4489 ; + wire \sn$4491 ; + wire \sn$4493 ; + wire \sn$4495 ; + wire \sn$4497 ; + wire \sn$4499 ; + wire \sn$4501 ; + wire \sn$4503 ; + wire \sn$4505 ; + wire \sn$4507 ; + wire \sn$4509 ; + wire \sn$4511 ; + wire \sn$4513 ; + wire \sn$4515 ; + wire \sn$4517 ; + wire \sn$4519 ; + wire \sn$4521 ; + wire \sn$4523 ; + wire \sn$4525 ; + wire t; + wire \t$1976 ; + wire \t$1977 ; + wire \t$1978 ; + wire \t$1979 ; + wire \t$1980 ; + wire \t$1981 ; + wire \t$1982 ; + wire \t$1983 ; + wire \t$1984 ; + wire \t$1985 ; + wire \t$1986 ; + wire \t$1987 ; + wire \t$1988 ; + wire \t$1989 ; + wire \t$1990 ; + wire \t$1991 ; + wire \t$1992 ; + wire \t$1993 ; + wire \t$1994 ; + wire \t$1995 ; + wire \t$1996 ; + wire \t$1997 ; + wire \t$1998 ; + wire \t$1999 ; + wire \t$2000 ; + wire \t$2001 ; + wire \t$2002 ; + wire \t$2003 ; + wire \t$2004 ; + wire \t$2005 ; + wire \t$2006 ; + wire \t$2007 ; + wire \t$2009 ; + wire \t$2010 ; + wire \t$2011 ; + wire \t$2012 ; + wire \t$2013 ; + wire \t$2014 ; + wire \t$2015 ; + wire \t$2016 ; + wire \t$2017 ; + wire \t$2018 ; + wire \t$2019 ; + wire \t$2020 ; + wire \t$2021 ; + wire \t$2022 ; + wire \t$2023 ; + wire \t$2024 ; + wire \t$2025 ; + wire \t$2026 ; + wire \t$2027 ; + wire \t$2028 ; + wire \t$2029 ; + wire \t$2030 ; + wire \t$2031 ; + wire \t$2032 ; + wire \t$2033 ; + wire \t$2034 ; + wire \t$2035 ; + wire \t$2036 ; + wire \t$2037 ; + wire \t$2038 ; + wire \t$2039 ; + wire \t$2040 ; + wire \t$2041 ; + wire \t$2043 ; + wire \t$2044 ; + wire \t$2045 ; + wire \t$2046 ; + wire \t$2047 ; + wire \t$2048 ; + wire \t$2049 ; + wire \t$2050 ; + wire \t$2051 ; + wire \t$2052 ; + wire \t$2053 ; + wire \t$2054 ; + wire \t$2055 ; + wire \t$2056 ; + wire \t$2057 ; + wire \t$2058 ; + wire \t$2059 ; + wire \t$2060 ; + wire \t$2061 ; + wire \t$2062 ; + wire \t$2063 ; + wire \t$2064 ; + wire \t$2065 ; + wire \t$2066 ; + wire \t$2067 ; + wire \t$2068 ; + wire \t$2069 ; + wire \t$2070 ; + wire \t$2071 ; + wire \t$2072 ; + wire \t$2073 ; + wire \t$2074 ; + wire \t$2075 ; + wire \t$2077 ; + wire \t$2078 ; + wire \t$2079 ; + wire \t$2080 ; + wire \t$2081 ; + wire \t$2082 ; + wire \t$2083 ; + wire \t$2084 ; + wire \t$2085 ; + wire \t$2086 ; + wire \t$2087 ; + wire \t$2088 ; + wire \t$2089 ; + wire \t$2090 ; + wire \t$2091 ; + wire \t$2092 ; + wire \t$2093 ; + wire \t$2094 ; + wire \t$2095 ; + wire \t$2096 ; + wire \t$2097 ; + wire \t$2098 ; + wire \t$2099 ; + wire \t$2100 ; + wire \t$2101 ; + wire \t$2102 ; + wire \t$2103 ; + wire \t$2104 ; + wire \t$2105 ; + wire \t$2106 ; + wire \t$2107 ; + wire \t$2108 ; + wire \t$2109 ; + wire \t$2111 ; + wire \t$2112 ; + wire \t$2113 ; + wire \t$2114 ; + wire \t$2115 ; + wire \t$2116 ; + wire \t$2117 ; + wire \t$2118 ; + wire \t$2119 ; + wire \t$2120 ; + wire \t$2121 ; + wire \t$2122 ; + wire \t$2123 ; + wire \t$2124 ; + wire \t$2125 ; + wire \t$2126 ; + wire \t$2127 ; + wire \t$2128 ; + wire \t$2129 ; + wire \t$2130 ; + wire \t$2131 ; + wire \t$2132 ; + wire \t$2133 ; + wire \t$2134 ; + wire \t$2135 ; + wire \t$2136 ; + wire \t$2137 ; + wire \t$2138 ; + wire \t$2139 ; + wire \t$2140 ; + wire \t$2141 ; + wire \t$2142 ; + wire \t$2143 ; + wire \t$2145 ; + wire \t$2146 ; + wire \t$2147 ; + wire \t$2148 ; + wire \t$2149 ; + wire \t$2150 ; + wire \t$2151 ; + wire \t$2152 ; + wire \t$2153 ; + wire \t$2154 ; + wire \t$2155 ; + wire \t$2156 ; + wire \t$2157 ; + wire \t$2158 ; + wire \t$2159 ; + wire \t$2160 ; + wire \t$2161 ; + wire \t$2162 ; + wire \t$2163 ; + wire \t$2164 ; + wire \t$2165 ; + wire \t$2166 ; + wire \t$2167 ; + wire \t$2168 ; + wire \t$2169 ; + wire \t$2170 ; + wire \t$2171 ; + wire \t$2172 ; + wire \t$2173 ; + wire \t$2174 ; + wire \t$2175 ; + wire \t$2176 ; + wire \t$2177 ; + wire \t$2179 ; + wire \t$2180 ; + wire \t$2181 ; + wire \t$2182 ; + wire \t$2183 ; + wire \t$2184 ; + wire \t$2185 ; + wire \t$2186 ; + wire \t$2187 ; + wire \t$2188 ; + wire \t$2189 ; + wire \t$2190 ; + wire \t$2191 ; + wire \t$2192 ; + wire \t$2193 ; + wire \t$2194 ; + wire \t$2195 ; + wire \t$2196 ; + wire \t$2197 ; + wire \t$2198 ; + wire \t$2199 ; + wire \t$2200 ; + wire \t$2201 ; + wire \t$2202 ; + wire \t$2203 ; + wire \t$2204 ; + wire \t$2205 ; + wire \t$2206 ; + wire \t$2207 ; + wire \t$2208 ; + wire \t$2209 ; + wire \t$2210 ; + wire \t$2211 ; + wire \t$2213 ; + wire \t$2214 ; + wire \t$2215 ; + wire \t$2216 ; + wire \t$2217 ; + wire \t$2218 ; + wire \t$2219 ; + wire \t$2220 ; + wire \t$2221 ; + wire \t$2222 ; + wire \t$2223 ; + wire \t$2224 ; + wire \t$2225 ; + wire \t$2226 ; + wire \t$2227 ; + wire \t$2228 ; + wire \t$2229 ; + wire \t$2230 ; + wire \t$2231 ; + wire \t$2232 ; + wire \t$2233 ; + wire \t$2234 ; + wire \t$2235 ; + wire \t$2236 ; + wire \t$2237 ; + wire \t$2238 ; + wire \t$2239 ; + wire \t$2240 ; + wire \t$2241 ; + wire \t$2242 ; + wire \t$2243 ; + wire \t$2244 ; + wire \t$2245 ; + wire \t$2247 ; + wire \t$2248 ; + wire \t$2249 ; + wire \t$2250 ; + wire \t$2251 ; + wire \t$2252 ; + wire \t$2253 ; + wire \t$2254 ; + wire \t$2255 ; + wire \t$2256 ; + wire \t$2257 ; + wire \t$2258 ; + wire \t$2259 ; + wire \t$2260 ; + wire \t$2261 ; + wire \t$2262 ; + wire \t$2263 ; + wire \t$2264 ; + wire \t$2265 ; + wire \t$2266 ; + wire \t$2267 ; + wire \t$2268 ; + wire \t$2269 ; + wire \t$2270 ; + wire \t$2271 ; + wire \t$2272 ; + wire \t$2273 ; + wire \t$2274 ; + wire \t$2275 ; + wire \t$2276 ; + wire \t$2277 ; + wire \t$2278 ; + wire \t$2279 ; + wire \t$2281 ; + wire \t$2282 ; + wire \t$2283 ; + wire \t$2284 ; + wire \t$2285 ; + wire \t$2286 ; + wire \t$2287 ; + wire \t$2288 ; + wire \t$2289 ; + wire \t$2290 ; + wire \t$2291 ; + wire \t$2292 ; + wire \t$2293 ; + wire \t$2294 ; + wire \t$2295 ; + wire \t$2296 ; + wire \t$2297 ; + wire \t$2298 ; + wire \t$2299 ; + wire \t$2300 ; + wire \t$2301 ; + wire \t$2302 ; + wire \t$2303 ; + wire \t$2304 ; + wire \t$2305 ; + wire \t$2306 ; + wire \t$2307 ; + wire \t$2308 ; + wire \t$2309 ; + wire \t$2310 ; + wire \t$2311 ; + wire \t$2312 ; + wire \t$2313 ; + wire \t$2315 ; + wire \t$2316 ; + wire \t$2317 ; + wire \t$2318 ; + wire \t$2319 ; + wire \t$2320 ; + wire \t$2321 ; + wire \t$2322 ; + wire \t$2323 ; + wire \t$2324 ; + wire \t$2325 ; + wire \t$2326 ; + wire \t$2327 ; + wire \t$2328 ; + wire \t$2329 ; + wire \t$2330 ; + wire \t$2331 ; + wire \t$2332 ; + wire \t$2333 ; + wire \t$2334 ; + wire \t$2335 ; + wire \t$2336 ; + wire \t$2337 ; + wire \t$2338 ; + wire \t$2339 ; + wire \t$2340 ; + wire \t$2341 ; + wire \t$2342 ; + wire \t$2343 ; + wire \t$2344 ; + wire \t$2345 ; + wire \t$2346 ; + wire \t$2347 ; + wire \t$2349 ; + wire \t$2350 ; + wire \t$2351 ; + wire \t$2352 ; + wire \t$2353 ; + wire \t$2354 ; + wire \t$2355 ; + wire \t$2356 ; + wire \t$2357 ; + wire \t$2358 ; + wire \t$2359 ; + wire \t$2360 ; + wire \t$2361 ; + wire \t$2362 ; + wire \t$2363 ; + wire \t$2364 ; + wire \t$2365 ; + wire \t$2366 ; + wire \t$2367 ; + wire \t$2368 ; + wire \t$2369 ; + wire \t$2370 ; + wire \t$2371 ; + wire \t$2372 ; + wire \t$2373 ; + wire \t$2374 ; + wire \t$2375 ; + wire \t$2376 ; + wire \t$2377 ; + wire \t$2378 ; + wire \t$2379 ; + wire \t$2380 ; + wire \t$2381 ; + wire \t$2383 ; + wire \t$2384 ; + wire \t$2385 ; + wire \t$2386 ; + wire \t$2387 ; + wire \t$2388 ; + wire \t$2389 ; + wire \t$2390 ; + wire \t$2391 ; + wire \t$2392 ; + wire \t$2393 ; + wire \t$2394 ; + wire \t$2395 ; + wire \t$2396 ; + wire \t$2397 ; + wire \t$2398 ; + wire \t$2399 ; + wire \t$2400 ; + wire \t$2401 ; + wire \t$2402 ; + wire \t$2403 ; + wire \t$2404 ; + wire \t$2405 ; + wire \t$2406 ; + wire \t$2407 ; + wire \t$2408 ; + wire \t$2409 ; + wire \t$2410 ; + wire \t$2411 ; + wire \t$2412 ; + wire \t$2413 ; + wire \t$2414 ; + wire \t$2415 ; + wire \t$2417 ; + wire \t$2418 ; + wire \t$2419 ; + wire \t$2420 ; + wire \t$2421 ; + wire \t$2422 ; + wire \t$2423 ; + wire \t$2424 ; + wire \t$2425 ; + wire \t$2426 ; + wire \t$2427 ; + wire \t$2428 ; + wire \t$2429 ; + wire \t$2430 ; + wire \t$2431 ; + wire \t$2432 ; + wire \t$2433 ; + wire \t$2434 ; + wire \t$2435 ; + wire \t$2436 ; + wire \t$2437 ; + wire \t$2438 ; + wire \t$2439 ; + wire \t$2440 ; + wire \t$2441 ; + wire \t$2442 ; + wire \t$2443 ; + wire \t$2444 ; + wire \t$2445 ; + wire \t$2446 ; + wire \t$2447 ; + wire \t$2448 ; + wire \t$2449 ; + wire \t$2451 ; + wire \t$2452 ; + wire \t$2453 ; + wire \t$2454 ; + wire \t$2455 ; + wire \t$2456 ; + wire \t$2457 ; + wire \t$2458 ; + wire \t$2459 ; + wire \t$2460 ; + wire \t$2461 ; + wire \t$2462 ; + wire \t$2463 ; + wire \t$2464 ; + wire \t$2465 ; + wire \t$2466 ; + wire \t$2467 ; + wire \t$2468 ; + wire \t$2469 ; + wire \t$2470 ; + wire \t$2471 ; + wire \t$2472 ; + wire \t$2473 ; + wire \t$2474 ; + wire \t$2475 ; + wire \t$2476 ; + wire \t$2477 ; + wire \t$2478 ; + wire \t$2479 ; + wire \t$2480 ; + wire \t$2481 ; + wire \t$2482 ; + wire \t$2483 ; + wire \t$2485 ; + wire \t$2486 ; + wire \t$2487 ; + wire \t$2488 ; + wire \t$2489 ; + wire \t$2490 ; + wire \t$2491 ; + wire \t$2492 ; + wire \t$2493 ; + wire \t$2494 ; + wire \t$2495 ; + wire \t$2496 ; + wire \t$2497 ; + wire \t$2498 ; + wire \t$2499 ; + wire \t$2500 ; + wire \t$2501 ; + wire \t$2502 ; + wire \t$2503 ; + wire \t$2504 ; + wire \t$2505 ; + wire \t$2506 ; + wire \t$2507 ; + wire \t$2508 ; + wire \t$2509 ; + wire \t$2510 ; + wire \t$2511 ; + wire \t$2512 ; + wire \t$2513 ; + wire \t$2514 ; + wire \t$2515 ; + wire \t$2516 ; + wire \t$2517 ; + wire \t$2519 ; + wire \t$2520 ; + wire \t$2521 ; + wire \t$2522 ; + wire \t$2523 ; + wire \t$2524 ; + wire \t$2525 ; + wire \t$2526 ; + wire \t$2527 ; + wire \t$2528 ; + wire \t$2529 ; + wire \t$2530 ; + wire \t$2531 ; + wire \t$2532 ; + wire \t$2533 ; + wire \t$2534 ; + wire \t$2535 ; + wire \t$2536 ; + wire \t$2537 ; + wire \t$2538 ; + wire \t$2539 ; + wire \t$2540 ; + wire \t$2541 ; + wire \t$2542 ; + wire \t$2543 ; + wire \t$2544 ; + wire \t$2545 ; + wire \t$2546 ; + wire \t$2547 ; + wire \t$2548 ; + wire \t$2549 ; + wire \t$2550 ; + wire \t$2551 ; + always @(posedge clk) + a_registered <= a; + always @(posedge clk) + b_registered <= b; + always @(posedge clk) + pp_row0_0 <= booth_b0_m0; + always @(posedge clk) + pp_row0_1 <= a_registered[1]; + always @(posedge clk) + pp_row1_0 <= booth_b0_m1; + always @(posedge clk) + pp_row2_0 <= booth_b0_m2; + always @(posedge clk) + pp_row2_1 <= booth_b2_m0; + always @(posedge clk) + pp_row2_2 <= a_registered[3]; + always @(posedge clk) + pp_row3_0 <= booth_b0_m3; + always @(posedge clk) + pp_row3_1 <= booth_b2_m1; + always @(posedge clk) + pp_row4_0 <= booth_b0_m4; + always @(posedge clk) + pp_row4_1 <= booth_b2_m2; + always @(posedge clk) + pp_row4_2 <= booth_b4_m0; + always @(posedge clk) + pp_row4_3 <= a_registered[5]; + always @(posedge clk) + pp_row5_0 <= booth_b0_m5; + always @(posedge clk) + pp_row5_1 <= booth_b2_m3; + always @(posedge clk) + pp_row5_2 <= booth_b4_m1; + always @(posedge clk) + pp_row6_0 <= booth_b0_m6; + always @(posedge clk) + pp_row6_1 <= booth_b2_m4; + always @(posedge clk) + pp_row6_2 <= booth_b4_m2; + always @(posedge clk) + pp_row6_3 <= booth_b6_m0; + always @(posedge clk) + pp_row6_4 <= a_registered[7]; + always @(posedge clk) + pp_row7_0 <= booth_b0_m7; + always @(posedge clk) + pp_row7_1 <= booth_b2_m5; + always @(posedge clk) + pp_row7_2 <= booth_b4_m3; + always @(posedge clk) + pp_row7_3 <= booth_b6_m1; + always @(posedge clk) + pp_row8_0 <= booth_b0_m8; + always @(posedge clk) + pp_row8_1 <= booth_b2_m6; + always @(posedge clk) + pp_row8_2 <= booth_b4_m4; + always @(posedge clk) + pp_row8_3 <= booth_b6_m2; + always @(posedge clk) + pp_row8_4 <= booth_b8_m0; + always @(posedge clk) + pp_row8_5 <= a_registered[9]; + always @(posedge clk) + pp_row9_0 <= booth_b0_m9; + always @(posedge clk) + pp_row9_1 <= booth_b2_m7; + always @(posedge clk) + pp_row9_2 <= booth_b4_m5; + always @(posedge clk) + pp_row9_3 <= booth_b6_m3; + always @(posedge clk) + pp_row9_4 <= booth_b8_m1; + always @(posedge clk) + pp_row10_0 <= booth_b0_m10; + always @(posedge clk) + pp_row10_1 <= booth_b2_m8; + always @(posedge clk) + pp_row10_2 <= booth_b4_m6; + always @(posedge clk) + pp_row10_3 <= booth_b6_m4; + always @(posedge clk) + pp_row10_4 <= booth_b8_m2; + always @(posedge clk) + pp_row10_5 <= booth_b10_m0; + always @(posedge clk) + pp_row10_6 <= a_registered[11]; + always @(posedge clk) + pp_row11_0 <= booth_b0_m11; + always @(posedge clk) + pp_row11_1 <= booth_b2_m9; + always @(posedge clk) + pp_row11_2 <= booth_b4_m7; + always @(posedge clk) + pp_row11_3 <= booth_b6_m5; + always @(posedge clk) + pp_row11_4 <= booth_b8_m3; + always @(posedge clk) + pp_row11_5 <= booth_b10_m1; + always @(posedge clk) + pp_row12_0 <= booth_b0_m12; + always @(posedge clk) + pp_row12_1 <= booth_b2_m10; + always @(posedge clk) + pp_row12_2 <= booth_b4_m8; + always @(posedge clk) + pp_row12_3 <= booth_b6_m6; + always @(posedge clk) + pp_row12_4 <= booth_b8_m4; + always @(posedge clk) + pp_row12_5 <= booth_b10_m2; + always @(posedge clk) + pp_row12_6 <= booth_b12_m0; + always @(posedge clk) + pp_row12_7 <= a_registered[13]; + always @(posedge clk) + pp_row13_0 <= booth_b0_m13; + always @(posedge clk) + pp_row13_1 <= booth_b2_m11; + always @(posedge clk) + pp_row13_2 <= booth_b4_m9; + always @(posedge clk) + pp_row13_3 <= booth_b6_m7; + always @(posedge clk) + pp_row13_4 <= booth_b8_m5; + always @(posedge clk) + pp_row13_5 <= booth_b10_m3; + always @(posedge clk) + pp_row13_6 <= booth_b12_m1; + always @(posedge clk) + pp_row14_0 <= booth_b0_m14; + always @(posedge clk) + pp_row14_1 <= booth_b2_m12; + always @(posedge clk) + pp_row14_2 <= booth_b4_m10; + always @(posedge clk) + pp_row14_3 <= booth_b6_m8; + always @(posedge clk) + pp_row14_4 <= booth_b8_m6; + always @(posedge clk) + pp_row14_5 <= booth_b10_m4; + always @(posedge clk) + pp_row14_6 <= booth_b12_m2; + always @(posedge clk) + pp_row14_7 <= booth_b14_m0; + always @(posedge clk) + pp_row14_8 <= a_registered[15]; + always @(posedge clk) + pp_row15_0 <= booth_b0_m15; + always @(posedge clk) + pp_row15_1 <= booth_b2_m13; + always @(posedge clk) + pp_row15_2 <= booth_b4_m11; + always @(posedge clk) + pp_row15_3 <= booth_b6_m9; + always @(posedge clk) + pp_row15_4 <= booth_b8_m7; + always @(posedge clk) + pp_row15_5 <= booth_b10_m5; + always @(posedge clk) + pp_row15_6 <= booth_b12_m3; + always @(posedge clk) + pp_row15_7 <= booth_b14_m1; + always @(posedge clk) + pp_row16_0 <= booth_b0_m16; + always @(posedge clk) + pp_row16_1 <= booth_b2_m14; + always @(posedge clk) + pp_row16_2 <= booth_b4_m12; + always @(posedge clk) + pp_row16_3 <= booth_b6_m10; + always @(posedge clk) + pp_row16_4 <= booth_b8_m8; + always @(posedge clk) + pp_row16_5 <= booth_b10_m6; + always @(posedge clk) + pp_row16_6 <= booth_b12_m4; + always @(posedge clk) + pp_row16_7 <= booth_b14_m2; + always @(posedge clk) + pp_row16_8 <= booth_b16_m0; + always @(posedge clk) + pp_row16_9 <= a_registered[17]; + always @(posedge clk) + pp_row17_0 <= booth_b0_m17; + always @(posedge clk) + pp_row17_1 <= booth_b2_m15; + always @(posedge clk) + pp_row17_2 <= booth_b4_m13; + always @(posedge clk) + pp_row17_3 <= booth_b6_m11; + always @(posedge clk) + pp_row17_4 <= booth_b8_m9; + always @(posedge clk) + pp_row17_5 <= booth_b10_m7; + always @(posedge clk) + pp_row17_6 <= booth_b12_m5; + always @(posedge clk) + pp_row17_7 <= booth_b14_m3; + always @(posedge clk) + pp_row17_8 <= booth_b16_m1; + always @(posedge clk) + pp_row18_0 <= booth_b0_m18; + always @(posedge clk) + pp_row18_1 <= booth_b2_m16; + always @(posedge clk) + pp_row18_2 <= booth_b4_m14; + always @(posedge clk) + pp_row18_3 <= booth_b6_m12; + always @(posedge clk) + pp_row18_4 <= booth_b8_m10; + always @(posedge clk) + pp_row18_5 <= booth_b10_m8; + always @(posedge clk) + pp_row18_6 <= booth_b12_m6; + always @(posedge clk) + pp_row18_7 <= booth_b14_m4; + always @(posedge clk) + pp_row18_8 <= booth_b16_m2; + always @(posedge clk) + pp_row18_9 <= booth_b18_m0; + always @(posedge clk) + pp_row18_10 <= a_registered[19]; + always @(posedge clk) + pp_row19_0 <= booth_b0_m19; + always @(posedge clk) + pp_row19_1 <= booth_b2_m17; + always @(posedge clk) + pp_row19_2 <= booth_b4_m15; + always @(posedge clk) + pp_row19_3 <= booth_b6_m13; + always @(posedge clk) + pp_row19_4 <= booth_b8_m11; + always @(posedge clk) + pp_row19_5 <= booth_b10_m9; + always @(posedge clk) + pp_row19_6 <= booth_b12_m7; + always @(posedge clk) + pp_row19_7 <= booth_b14_m5; + always @(posedge clk) + pp_row19_8 <= booth_b16_m3; + always @(posedge clk) + pp_row19_9 <= booth_b18_m1; + always @(posedge clk) + pp_row20_0 <= booth_b0_m20; + always @(posedge clk) + pp_row20_1 <= booth_b2_m18; + always @(posedge clk) + pp_row20_2 <= booth_b4_m16; + always @(posedge clk) + pp_row20_3 <= booth_b6_m14; + always @(posedge clk) + pp_row20_4 <= booth_b8_m12; + always @(posedge clk) + pp_row20_5 <= booth_b10_m10; + always @(posedge clk) + pp_row20_6 <= booth_b12_m8; + always @(posedge clk) + pp_row20_7 <= booth_b14_m6; + always @(posedge clk) + pp_row20_8 <= booth_b16_m4; + always @(posedge clk) + pp_row20_9 <= booth_b18_m2; + always @(posedge clk) + pp_row20_10 <= booth_b20_m0; + always @(posedge clk) + pp_row20_11 <= a_registered[21]; + always @(posedge clk) + pp_row21_0 <= booth_b0_m21; + always @(posedge clk) + pp_row21_1 <= booth_b2_m19; + always @(posedge clk) + pp_row21_2 <= booth_b4_m17; + always @(posedge clk) + pp_row21_3 <= booth_b6_m15; + always @(posedge clk) + pp_row21_4 <= booth_b8_m13; + always @(posedge clk) + pp_row21_5 <= booth_b10_m11; + always @(posedge clk) + pp_row21_6 <= booth_b12_m9; + always @(posedge clk) + pp_row21_7 <= booth_b14_m7; + always @(posedge clk) + pp_row21_8 <= booth_b16_m5; + always @(posedge clk) + pp_row21_9 <= booth_b18_m3; + always @(posedge clk) + pp_row21_10 <= booth_b20_m1; + always @(posedge clk) + pp_row22_0 <= booth_b0_m22; + always @(posedge clk) + pp_row22_1 <= booth_b2_m20; + always @(posedge clk) + pp_row22_2 <= booth_b4_m18; + always @(posedge clk) + pp_row22_3 <= booth_b6_m16; + always @(posedge clk) + pp_row22_4 <= booth_b8_m14; + always @(posedge clk) + pp_row22_5 <= booth_b10_m12; + always @(posedge clk) + pp_row22_6 <= booth_b12_m10; + always @(posedge clk) + pp_row22_7 <= booth_b14_m8; + always @(posedge clk) + pp_row22_8 <= booth_b16_m6; + always @(posedge clk) + pp_row22_9 <= booth_b18_m4; + always @(posedge clk) + pp_row22_10 <= booth_b20_m2; + always @(posedge clk) + pp_row22_11 <= booth_b22_m0; + always @(posedge clk) + pp_row22_12 <= a_registered[23]; + always @(posedge clk) + pp_row23_0 <= booth_b0_m23; + always @(posedge clk) + pp_row23_1 <= booth_b2_m21; + always @(posedge clk) + pp_row23_2 <= booth_b4_m19; + always @(posedge clk) + pp_row23_3 <= booth_b6_m17; + always @(posedge clk) + pp_row23_4 <= booth_b8_m15; + always @(posedge clk) + pp_row23_5 <= booth_b10_m13; + always @(posedge clk) + pp_row23_6 <= booth_b12_m11; + always @(posedge clk) + pp_row23_7 <= booth_b14_m9; + always @(posedge clk) + pp_row23_8 <= booth_b16_m7; + always @(posedge clk) + pp_row23_9 <= booth_b18_m5; + always @(posedge clk) + pp_row23_10 <= booth_b20_m3; + always @(posedge clk) + pp_row23_11 <= booth_b22_m1; + always @(posedge clk) + pp_row24_0 <= booth_b0_m24; + always @(posedge clk) + pp_row24_1 <= booth_b2_m22; + always @(posedge clk) + pp_row24_2 <= booth_b4_m20; + always @(posedge clk) + pp_row24_3 <= booth_b6_m18; + always @(posedge clk) + pp_row24_4 <= booth_b8_m16; + always @(posedge clk) + pp_row24_5 <= booth_b10_m14; + always @(posedge clk) + pp_row24_6 <= booth_b12_m12; + always @(posedge clk) + pp_row24_7 <= booth_b14_m10; + always @(posedge clk) + pp_row24_8 <= booth_b16_m8; + always @(posedge clk) + pp_row24_9 <= booth_b18_m6; + always @(posedge clk) + pp_row24_10 <= booth_b20_m4; + always @(posedge clk) + pp_row24_11 <= booth_b22_m2; + always @(posedge clk) + pp_row24_12 <= booth_b24_m0; + always @(posedge clk) + pp_row24_13 <= a_registered[25]; + always @(posedge clk) + pp_row25_0 <= booth_b0_m25; + always @(posedge clk) + pp_row25_1 <= booth_b2_m23; + always @(posedge clk) + pp_row25_2 <= booth_b4_m21; + always @(posedge clk) + pp_row25_3 <= booth_b6_m19; + always @(posedge clk) + pp_row25_4 <= booth_b8_m17; + always @(posedge clk) + pp_row25_5 <= booth_b10_m15; + always @(posedge clk) + pp_row25_6 <= booth_b12_m13; + always @(posedge clk) + pp_row25_7 <= booth_b14_m11; + always @(posedge clk) + pp_row25_8 <= booth_b16_m9; + always @(posedge clk) + pp_row25_9 <= booth_b18_m7; + always @(posedge clk) + pp_row25_10 <= booth_b20_m5; + always @(posedge clk) + pp_row25_11 <= booth_b22_m3; + always @(posedge clk) + pp_row25_12 <= booth_b24_m1; + always @(posedge clk) + pp_row26_0 <= booth_b0_m26; + always @(posedge clk) + pp_row26_1 <= booth_b2_m24; + always @(posedge clk) + pp_row26_2 <= booth_b4_m22; + always @(posedge clk) + pp_row26_3 <= booth_b6_m20; + always @(posedge clk) + pp_row26_4 <= booth_b8_m18; + always @(posedge clk) + pp_row26_5 <= booth_b10_m16; + always @(posedge clk) + pp_row26_6 <= booth_b12_m14; + always @(posedge clk) + pp_row26_7 <= booth_b14_m12; + always @(posedge clk) + pp_row26_8 <= booth_b16_m10; + always @(posedge clk) + pp_row26_9 <= booth_b18_m8; + always @(posedge clk) + pp_row26_10 <= booth_b20_m6; + always @(posedge clk) + pp_row26_11 <= booth_b22_m4; + always @(posedge clk) + pp_row26_12 <= booth_b24_m2; + always @(posedge clk) + pp_row26_13 <= booth_b26_m0; + always @(posedge clk) + pp_row26_14 <= a_registered[27]; + always @(posedge clk) + pp_row27_0 <= booth_b0_m27; + always @(posedge clk) + pp_row27_1 <= booth_b2_m25; + always @(posedge clk) + pp_row27_2 <= booth_b4_m23; + always @(posedge clk) + pp_row27_3 <= booth_b6_m21; + always @(posedge clk) + pp_row27_4 <= booth_b8_m19; + always @(posedge clk) + pp_row27_5 <= booth_b10_m17; + always @(posedge clk) + pp_row27_6 <= booth_b12_m15; + always @(posedge clk) + pp_row27_7 <= booth_b14_m13; + always @(posedge clk) + pp_row27_8 <= booth_b16_m11; + always @(posedge clk) + pp_row27_9 <= booth_b18_m9; + always @(posedge clk) + pp_row27_10 <= booth_b20_m7; + always @(posedge clk) + pp_row27_11 <= booth_b22_m5; + always @(posedge clk) + pp_row27_12 <= booth_b24_m3; + always @(posedge clk) + pp_row27_13 <= booth_b26_m1; + always @(posedge clk) + pp_row28_0 <= booth_b0_m28; + always @(posedge clk) + pp_row28_1 <= booth_b2_m26; + always @(posedge clk) + pp_row28_2 <= booth_b4_m24; + always @(posedge clk) + pp_row28_3 <= booth_b6_m22; + always @(posedge clk) + pp_row28_4 <= booth_b8_m20; + always @(posedge clk) + pp_row28_5 <= booth_b10_m18; + always @(posedge clk) + pp_row28_6 <= booth_b12_m16; + always @(posedge clk) + pp_row28_7 <= booth_b14_m14; + always @(posedge clk) + pp_row28_8 <= booth_b16_m12; + always @(posedge clk) + pp_row28_9 <= booth_b18_m10; + always @(posedge clk) + pp_row28_10 <= booth_b20_m8; + always @(posedge clk) + pp_row28_11 <= booth_b22_m6; + always @(posedge clk) + pp_row28_12 <= booth_b24_m4; + always @(posedge clk) + pp_row28_13 <= booth_b26_m2; + always @(posedge clk) + pp_row28_14 <= booth_b28_m0; + always @(posedge clk) + pp_row28_15 <= a_registered[29]; + always @(posedge clk) + pp_row29_0 <= booth_b0_m29; + always @(posedge clk) + pp_row29_1 <= booth_b2_m27; + always @(posedge clk) + pp_row29_2 <= booth_b4_m25; + always @(posedge clk) + pp_row29_3 <= booth_b6_m23; + always @(posedge clk) + pp_row29_4 <= booth_b8_m21; + always @(posedge clk) + pp_row29_5 <= booth_b10_m19; + always @(posedge clk) + pp_row29_6 <= booth_b12_m17; + always @(posedge clk) + pp_row29_7 <= booth_b14_m15; + always @(posedge clk) + pp_row29_8 <= booth_b16_m13; + always @(posedge clk) + pp_row29_9 <= booth_b18_m11; + always @(posedge clk) + pp_row29_10 <= booth_b20_m9; + always @(posedge clk) + pp_row29_11 <= booth_b22_m7; + always @(posedge clk) + pp_row29_12 <= booth_b24_m5; + always @(posedge clk) + pp_row29_13 <= booth_b26_m3; + always @(posedge clk) + pp_row29_14 <= booth_b28_m1; + always @(posedge clk) + pp_row30_0 <= booth_b0_m30; + always @(posedge clk) + pp_row30_1 <= booth_b2_m28; + always @(posedge clk) + pp_row30_2 <= booth_b4_m26; + always @(posedge clk) + pp_row30_3 <= booth_b6_m24; + always @(posedge clk) + pp_row30_4 <= booth_b8_m22; + always @(posedge clk) + pp_row30_5 <= booth_b10_m20; + always @(posedge clk) + pp_row30_6 <= booth_b12_m18; + always @(posedge clk) + pp_row30_7 <= booth_b14_m16; + always @(posedge clk) + pp_row30_8 <= booth_b16_m14; + always @(posedge clk) + pp_row30_9 <= booth_b18_m12; + always @(posedge clk) + pp_row30_10 <= booth_b20_m10; + always @(posedge clk) + pp_row30_11 <= booth_b22_m8; + always @(posedge clk) + pp_row30_12 <= booth_b24_m6; + always @(posedge clk) + pp_row30_13 <= booth_b26_m4; + always @(posedge clk) + pp_row30_14 <= booth_b28_m2; + always @(posedge clk) + pp_row30_15 <= booth_b30_m0; + always @(posedge clk) + pp_row30_16 <= a_registered[31]; + always @(posedge clk) + pp_row31_0 <= booth_b0_m31; + always @(posedge clk) + pp_row31_1 <= booth_b2_m29; + always @(posedge clk) + pp_row31_2 <= booth_b4_m27; + always @(posedge clk) + pp_row31_3 <= booth_b6_m25; + always @(posedge clk) + pp_row31_4 <= booth_b8_m23; + always @(posedge clk) + pp_row31_5 <= booth_b10_m21; + always @(posedge clk) + pp_row31_6 <= booth_b12_m19; + always @(posedge clk) + pp_row31_7 <= booth_b14_m17; + always @(posedge clk) + pp_row31_8 <= booth_b16_m15; + always @(posedge clk) + pp_row31_9 <= booth_b18_m13; + always @(posedge clk) + pp_row31_10 <= booth_b20_m11; + always @(posedge clk) + pp_row31_11 <= booth_b22_m9; + always @(posedge clk) + pp_row31_12 <= booth_b24_m7; + always @(posedge clk) + pp_row31_13 <= booth_b26_m5; + always @(posedge clk) + pp_row31_14 <= booth_b28_m3; + always @(posedge clk) + pp_row31_15 <= booth_b30_m1; + always @(posedge clk) + pp_row32_0 <= booth_b0_m32; + always @(posedge clk) + pp_row32_1 <= booth_b2_m30; + always @(posedge clk) + pp_row32_2 <= booth_b4_m28; + always @(posedge clk) + pp_row32_3 <= booth_b6_m26; + always @(posedge clk) + pp_row32_4 <= booth_b8_m24; + always @(posedge clk) + pp_row32_5 <= booth_b10_m22; + always @(posedge clk) + pp_row32_6 <= booth_b12_m20; + always @(posedge clk) + pp_row32_7 <= booth_b14_m18; + always @(posedge clk) + pp_row32_8 <= booth_b16_m16; + always @(posedge clk) + pp_row32_9 <= booth_b18_m14; + always @(posedge clk) + pp_row32_10 <= booth_b20_m12; + always @(posedge clk) + pp_row32_11 <= booth_b22_m10; + always @(posedge clk) + pp_row32_12 <= booth_b24_m8; + always @(posedge clk) + pp_row32_13 <= booth_b26_m6; + always @(posedge clk) + pp_row32_14 <= booth_b28_m4; + always @(posedge clk) + pp_row32_15 <= booth_b30_m2; + always @(posedge clk) + pp_row32_16 <= booth_b32_m0; + always @(posedge clk) + pp_row33_0 <= a_registered[1]; + always @(posedge clk) + pp_row33_1 <= booth_b2_m31; + always @(posedge clk) + pp_row33_2 <= booth_b4_m29; + always @(posedge clk) + pp_row33_3 <= booth_b6_m27; + always @(posedge clk) + pp_row33_4 <= booth_b8_m25; + always @(posedge clk) + pp_row33_5 <= booth_b10_m23; + always @(posedge clk) + pp_row33_6 <= booth_b12_m21; + always @(posedge clk) + pp_row33_7 <= booth_b14_m19; + always @(posedge clk) + pp_row33_8 <= booth_b16_m17; + always @(posedge clk) + pp_row33_9 <= booth_b18_m15; + always @(posedge clk) + pp_row33_10 <= booth_b20_m13; + always @(posedge clk) + pp_row33_11 <= booth_b22_m11; + always @(posedge clk) + pp_row33_12 <= booth_b24_m9; + always @(posedge clk) + pp_row33_13 <= booth_b26_m7; + always @(posedge clk) + pp_row33_14 <= booth_b28_m5; + always @(posedge clk) + pp_row33_15 <= booth_b30_m3; + always @(posedge clk) + pp_row33_16 <= booth_b32_m1; + always @(posedge clk) + pp_row34_0 <= a_registered[1]; + always @(posedge clk) + pp_row34_1 <= booth_b2_m32; + always @(posedge clk) + pp_row34_2 <= booth_b4_m30; + always @(posedge clk) + pp_row34_3 <= booth_b6_m28; + always @(posedge clk) + pp_row34_4 <= booth_b8_m26; + always @(posedge clk) + pp_row34_5 <= booth_b10_m24; + always @(posedge clk) + pp_row34_6 <= booth_b12_m22; + always @(posedge clk) + pp_row34_7 <= booth_b14_m20; + always @(posedge clk) + pp_row34_8 <= booth_b16_m18; + always @(posedge clk) + pp_row34_9 <= booth_b18_m16; + always @(posedge clk) + pp_row34_10 <= booth_b20_m14; + always @(posedge clk) + pp_row34_11 <= booth_b22_m12; + always @(posedge clk) + pp_row34_12 <= booth_b24_m10; + always @(posedge clk) + pp_row34_13 <= booth_b26_m8; + always @(posedge clk) + pp_row34_14 <= booth_b28_m6; + always @(posedge clk) + pp_row34_15 <= booth_b30_m4; + always @(posedge clk) + pp_row34_16 <= booth_b32_m2; + always @(posedge clk) + pp_row35_0 <= notsign; + always @(posedge clk) + pp_row35_1 <= \notsign$686 ; + always @(posedge clk) + pp_row35_2 <= booth_b4_m31; + always @(posedge clk) + pp_row35_3 <= booth_b6_m29; + always @(posedge clk) + pp_row35_4 <= booth_b8_m27; + always @(posedge clk) + pp_row35_5 <= booth_b10_m25; + always @(posedge clk) + pp_row35_6 <= booth_b12_m23; + always @(posedge clk) + pp_row35_7 <= booth_b14_m21; + always @(posedge clk) + pp_row35_8 <= booth_b16_m19; + always @(posedge clk) + pp_row35_9 <= booth_b18_m17; + always @(posedge clk) + pp_row35_10 <= booth_b20_m15; + always @(posedge clk) + pp_row35_11 <= booth_b22_m13; + always @(posedge clk) + pp_row35_12 <= booth_b24_m11; + always @(posedge clk) + pp_row35_13 <= booth_b26_m9; + always @(posedge clk) + pp_row35_14 <= booth_b28_m7; + always @(posedge clk) + pp_row35_15 <= booth_b30_m5; + always @(posedge clk) + pp_row35_16 <= booth_b32_m3; + always @(posedge clk) + pp_row36_1 <= booth_b4_m32; + always @(posedge clk) + pp_row36_2 <= booth_b6_m30; + always @(posedge clk) + pp_row36_3 <= booth_b8_m28; + always @(posedge clk) + pp_row36_4 <= booth_b10_m26; + always @(posedge clk) + pp_row36_5 <= booth_b12_m24; + always @(posedge clk) + pp_row36_6 <= booth_b14_m22; + always @(posedge clk) + pp_row36_7 <= booth_b16_m20; + always @(posedge clk) + pp_row36_8 <= booth_b18_m18; + always @(posedge clk) + pp_row36_9 <= booth_b20_m16; + always @(posedge clk) + pp_row36_10 <= booth_b22_m14; + always @(posedge clk) + pp_row36_11 <= booth_b24_m12; + always @(posedge clk) + pp_row36_12 <= booth_b26_m10; + always @(posedge clk) + pp_row36_13 <= booth_b28_m8; + always @(posedge clk) + pp_row36_14 <= booth_b30_m6; + always @(posedge clk) + pp_row36_15 <= booth_b32_m4; + always @(posedge clk) + pp_row37_0 <= \notsign$748 ; + always @(posedge clk) + pp_row37_1 <= booth_b6_m31; + always @(posedge clk) + pp_row37_2 <= booth_b8_m29; + always @(posedge clk) + pp_row37_3 <= booth_b10_m27; + always @(posedge clk) + pp_row37_4 <= booth_b12_m25; + always @(posedge clk) + pp_row37_5 <= booth_b14_m23; + always @(posedge clk) + pp_row37_6 <= booth_b16_m21; + always @(posedge clk) + pp_row37_7 <= booth_b18_m19; + always @(posedge clk) + pp_row37_8 <= booth_b20_m17; + always @(posedge clk) + pp_row37_9 <= booth_b22_m15; + always @(posedge clk) + pp_row37_10 <= booth_b24_m13; + always @(posedge clk) + pp_row37_11 <= booth_b26_m11; + always @(posedge clk) + pp_row37_12 <= booth_b28_m9; + always @(posedge clk) + pp_row37_13 <= booth_b30_m7; + always @(posedge clk) + pp_row37_14 <= booth_b32_m5; + always @(posedge clk) + pp_row38_1 <= booth_b6_m32; + always @(posedge clk) + pp_row38_2 <= booth_b8_m30; + always @(posedge clk) + pp_row38_3 <= booth_b10_m28; + always @(posedge clk) + pp_row38_4 <= booth_b12_m26; + always @(posedge clk) + pp_row38_5 <= booth_b14_m24; + always @(posedge clk) + pp_row38_6 <= booth_b16_m22; + always @(posedge clk) + pp_row38_7 <= booth_b18_m20; + always @(posedge clk) + pp_row38_8 <= booth_b20_m18; + always @(posedge clk) + pp_row38_9 <= booth_b22_m16; + always @(posedge clk) + pp_row38_10 <= booth_b24_m14; + always @(posedge clk) + pp_row38_11 <= booth_b26_m12; + always @(posedge clk) + pp_row38_12 <= booth_b28_m10; + always @(posedge clk) + pp_row38_13 <= booth_b30_m8; + always @(posedge clk) + pp_row38_14 <= booth_b32_m6; + always @(posedge clk) + pp_row39_0 <= \notsign$806 ; + always @(posedge clk) + pp_row39_1 <= booth_b8_m31; + always @(posedge clk) + pp_row39_2 <= booth_b10_m29; + always @(posedge clk) + pp_row39_3 <= booth_b12_m27; + always @(posedge clk) + pp_row39_4 <= booth_b14_m25; + always @(posedge clk) + pp_row39_5 <= booth_b16_m23; + always @(posedge clk) + pp_row39_6 <= booth_b18_m21; + always @(posedge clk) + pp_row39_7 <= booth_b20_m19; + always @(posedge clk) + pp_row39_8 <= booth_b22_m17; + always @(posedge clk) + pp_row39_9 <= booth_b24_m15; + always @(posedge clk) + pp_row39_10 <= booth_b26_m13; + always @(posedge clk) + pp_row39_11 <= booth_b28_m11; + always @(posedge clk) + pp_row39_12 <= booth_b30_m9; + always @(posedge clk) + pp_row39_13 <= booth_b32_m7; + always @(posedge clk) + pp_row40_1 <= booth_b8_m32; + always @(posedge clk) + pp_row40_2 <= booth_b10_m30; + always @(posedge clk) + pp_row40_3 <= booth_b12_m28; + always @(posedge clk) + pp_row40_4 <= booth_b14_m26; + always @(posedge clk) + pp_row40_5 <= booth_b16_m24; + always @(posedge clk) + pp_row40_6 <= booth_b18_m22; + always @(posedge clk) + pp_row40_7 <= booth_b20_m20; + always @(posedge clk) + pp_row40_8 <= booth_b22_m18; + always @(posedge clk) + pp_row40_9 <= booth_b24_m16; + always @(posedge clk) + pp_row40_10 <= booth_b26_m14; + always @(posedge clk) + pp_row40_11 <= booth_b28_m12; + always @(posedge clk) + pp_row40_12 <= booth_b30_m10; + always @(posedge clk) + pp_row40_13 <= booth_b32_m8; + always @(posedge clk) + pp_row41_0 <= \notsign$860 ; + always @(posedge clk) + pp_row41_1 <= booth_b10_m31; + always @(posedge clk) + pp_row41_2 <= booth_b12_m29; + always @(posedge clk) + pp_row41_3 <= booth_b14_m27; + always @(posedge clk) + pp_row41_4 <= booth_b16_m25; + always @(posedge clk) + pp_row41_5 <= booth_b18_m23; + always @(posedge clk) + pp_row41_6 <= booth_b20_m21; + always @(posedge clk) + pp_row41_7 <= booth_b22_m19; + always @(posedge clk) + pp_row41_8 <= booth_b24_m17; + always @(posedge clk) + pp_row41_9 <= booth_b26_m15; + always @(posedge clk) + pp_row41_10 <= booth_b28_m13; + always @(posedge clk) + pp_row41_11 <= booth_b30_m11; + always @(posedge clk) + pp_row41_12 <= booth_b32_m9; + always @(posedge clk) + pp_row42_1 <= booth_b10_m32; + always @(posedge clk) + pp_row42_2 <= booth_b12_m30; + always @(posedge clk) + pp_row42_3 <= booth_b14_m28; + always @(posedge clk) + pp_row42_4 <= booth_b16_m26; + always @(posedge clk) + pp_row42_5 <= booth_b18_m24; + always @(posedge clk) + pp_row42_6 <= booth_b20_m22; + always @(posedge clk) + pp_row42_7 <= booth_b22_m20; + always @(posedge clk) + pp_row42_8 <= booth_b24_m18; + always @(posedge clk) + pp_row42_9 <= booth_b26_m16; + always @(posedge clk) + pp_row42_10 <= booth_b28_m14; + always @(posedge clk) + pp_row42_11 <= booth_b30_m12; + always @(posedge clk) + pp_row42_12 <= booth_b32_m10; + always @(posedge clk) + pp_row43_0 <= \notsign$910 ; + always @(posedge clk) + pp_row43_1 <= booth_b12_m31; + always @(posedge clk) + pp_row43_2 <= booth_b14_m29; + always @(posedge clk) + pp_row43_3 <= booth_b16_m27; + always @(posedge clk) + pp_row43_4 <= booth_b18_m25; + always @(posedge clk) + pp_row43_5 <= booth_b20_m23; + always @(posedge clk) + pp_row43_6 <= booth_b22_m21; + always @(posedge clk) + pp_row43_7 <= booth_b24_m19; + always @(posedge clk) + pp_row43_8 <= booth_b26_m17; + always @(posedge clk) + pp_row43_9 <= booth_b28_m15; + always @(posedge clk) + pp_row43_10 <= booth_b30_m13; + always @(posedge clk) + pp_row43_11 <= booth_b32_m11; + always @(posedge clk) + pp_row44_1 <= booth_b12_m32; + always @(posedge clk) + pp_row44_2 <= booth_b14_m30; + always @(posedge clk) + pp_row44_3 <= booth_b16_m28; + always @(posedge clk) + pp_row44_4 <= booth_b18_m26; + always @(posedge clk) + pp_row44_5 <= booth_b20_m24; + always @(posedge clk) + pp_row44_6 <= booth_b22_m22; + always @(posedge clk) + pp_row44_7 <= booth_b24_m20; + always @(posedge clk) + pp_row44_8 <= booth_b26_m18; + always @(posedge clk) + pp_row44_9 <= booth_b28_m16; + always @(posedge clk) + pp_row44_10 <= booth_b30_m14; + always @(posedge clk) + pp_row44_11 <= booth_b32_m12; + always @(posedge clk) + pp_row45_0 <= \notsign$956 ; + always @(posedge clk) + pp_row45_1 <= booth_b14_m31; + always @(posedge clk) + pp_row45_2 <= booth_b16_m29; + always @(posedge clk) + pp_row45_3 <= booth_b18_m27; + always @(posedge clk) + pp_row45_4 <= booth_b20_m25; + always @(posedge clk) + pp_row45_5 <= booth_b22_m23; + always @(posedge clk) + pp_row45_6 <= booth_b24_m21; + always @(posedge clk) + pp_row45_7 <= booth_b26_m19; + always @(posedge clk) + pp_row45_8 <= booth_b28_m17; + always @(posedge clk) + pp_row45_9 <= booth_b30_m15; + always @(posedge clk) + pp_row45_10 <= booth_b32_m13; + always @(posedge clk) + pp_row46_1 <= booth_b14_m32; + always @(posedge clk) + pp_row46_2 <= booth_b16_m30; + always @(posedge clk) + pp_row46_3 <= booth_b18_m28; + always @(posedge clk) + pp_row46_4 <= booth_b20_m26; + always @(posedge clk) + pp_row46_5 <= booth_b22_m24; + always @(posedge clk) + pp_row46_6 <= booth_b24_m22; + always @(posedge clk) + pp_row46_7 <= booth_b26_m20; + always @(posedge clk) + pp_row46_8 <= booth_b28_m18; + always @(posedge clk) + pp_row46_9 <= booth_b30_m16; + always @(posedge clk) + pp_row46_10 <= booth_b32_m14; + always @(posedge clk) + pp_row47_0 <= \notsign$998 ; + always @(posedge clk) + pp_row47_1 <= booth_b16_m31; + always @(posedge clk) + pp_row47_2 <= booth_b18_m29; + always @(posedge clk) + pp_row47_3 <= booth_b20_m27; + always @(posedge clk) + pp_row47_4 <= booth_b22_m25; + always @(posedge clk) + pp_row47_5 <= booth_b24_m23; + always @(posedge clk) + pp_row47_6 <= booth_b26_m21; + always @(posedge clk) + pp_row47_7 <= booth_b28_m19; + always @(posedge clk) + pp_row47_8 <= booth_b30_m17; + always @(posedge clk) + pp_row47_9 <= booth_b32_m15; + always @(posedge clk) + pp_row48_1 <= booth_b16_m32; + always @(posedge clk) + pp_row48_2 <= booth_b18_m30; + always @(posedge clk) + pp_row48_3 <= booth_b20_m28; + always @(posedge clk) + pp_row48_4 <= booth_b22_m26; + always @(posedge clk) + pp_row48_5 <= booth_b24_m24; + always @(posedge clk) + pp_row48_6 <= booth_b26_m22; + always @(posedge clk) + pp_row48_7 <= booth_b28_m20; + always @(posedge clk) + pp_row48_8 <= booth_b30_m18; + always @(posedge clk) + pp_row48_9 <= booth_b32_m16; + always @(posedge clk) + pp_row49_0 <= \notsign$1036 ; + always @(posedge clk) + pp_row49_1 <= booth_b18_m31; + always @(posedge clk) + pp_row49_2 <= booth_b20_m29; + always @(posedge clk) + pp_row49_3 <= booth_b22_m27; + always @(posedge clk) + pp_row49_4 <= booth_b24_m25; + always @(posedge clk) + pp_row49_5 <= booth_b26_m23; + always @(posedge clk) + pp_row49_6 <= booth_b28_m21; + always @(posedge clk) + pp_row49_7 <= booth_b30_m19; + always @(posedge clk) + pp_row49_8 <= booth_b32_m17; + always @(posedge clk) + pp_row50_1 <= booth_b18_m32; + always @(posedge clk) + pp_row50_2 <= booth_b20_m30; + always @(posedge clk) + pp_row50_3 <= booth_b22_m28; + always @(posedge clk) + pp_row50_4 <= booth_b24_m26; + always @(posedge clk) + pp_row50_5 <= booth_b26_m24; + always @(posedge clk) + pp_row50_6 <= booth_b28_m22; + always @(posedge clk) + pp_row50_7 <= booth_b30_m20; + always @(posedge clk) + pp_row50_8 <= booth_b32_m18; + always @(posedge clk) + pp_row51_0 <= \notsign$1070 ; + always @(posedge clk) + pp_row51_1 <= booth_b20_m31; + always @(posedge clk) + pp_row51_2 <= booth_b22_m29; + always @(posedge clk) + pp_row51_3 <= booth_b24_m27; + always @(posedge clk) + pp_row51_4 <= booth_b26_m25; + always @(posedge clk) + pp_row51_5 <= booth_b28_m23; + always @(posedge clk) + pp_row51_6 <= booth_b30_m21; + always @(posedge clk) + pp_row51_7 <= booth_b32_m19; + always @(posedge clk) + pp_row52_1 <= booth_b20_m32; + always @(posedge clk) + pp_row52_2 <= booth_b22_m30; + always @(posedge clk) + pp_row52_3 <= booth_b24_m28; + always @(posedge clk) + pp_row52_4 <= booth_b26_m26; + always @(posedge clk) + pp_row52_5 <= booth_b28_m24; + always @(posedge clk) + pp_row52_6 <= booth_b30_m22; + always @(posedge clk) + pp_row52_7 <= booth_b32_m20; + always @(posedge clk) + pp_row53_0 <= \notsign$1100 ; + always @(posedge clk) + pp_row53_1 <= booth_b22_m31; + always @(posedge clk) + pp_row53_2 <= booth_b24_m29; + always @(posedge clk) + pp_row53_3 <= booth_b26_m27; + always @(posedge clk) + pp_row53_4 <= booth_b28_m25; + always @(posedge clk) + pp_row53_5 <= booth_b30_m23; + always @(posedge clk) + pp_row53_6 <= booth_b32_m21; + always @(posedge clk) + pp_row54_1 <= booth_b22_m32; + always @(posedge clk) + pp_row54_2 <= booth_b24_m30; + always @(posedge clk) + pp_row54_3 <= booth_b26_m28; + always @(posedge clk) + pp_row54_4 <= booth_b28_m26; + always @(posedge clk) + pp_row54_5 <= booth_b30_m24; + always @(posedge clk) + pp_row54_6 <= booth_b32_m22; + always @(posedge clk) + pp_row55_0 <= \notsign$1126 ; + always @(posedge clk) + pp_row55_1 <= booth_b24_m31; + always @(posedge clk) + pp_row55_2 <= booth_b26_m29; + always @(posedge clk) + pp_row55_3 <= booth_b28_m27; + always @(posedge clk) + pp_row55_4 <= booth_b30_m25; + always @(posedge clk) + pp_row55_5 <= booth_b32_m23; + always @(posedge clk) + pp_row56_1 <= booth_b24_m32; + always @(posedge clk) + pp_row56_2 <= booth_b26_m30; + always @(posedge clk) + pp_row56_3 <= booth_b28_m28; + always @(posedge clk) + pp_row56_4 <= booth_b30_m26; + always @(posedge clk) + pp_row56_5 <= booth_b32_m24; + always @(posedge clk) + pp_row57_0 <= \notsign$1148 ; + always @(posedge clk) + pp_row57_1 <= booth_b26_m31; + always @(posedge clk) + pp_row57_2 <= booth_b28_m29; + always @(posedge clk) + pp_row57_3 <= booth_b30_m27; + always @(posedge clk) + pp_row57_4 <= booth_b32_m25; + always @(posedge clk) + pp_row58_1 <= booth_b26_m32; + always @(posedge clk) + pp_row58_2 <= booth_b28_m30; + always @(posedge clk) + pp_row58_3 <= booth_b30_m28; + always @(posedge clk) + pp_row58_4 <= booth_b32_m26; + always @(posedge clk) + pp_row59_0 <= \notsign$1166 ; + always @(posedge clk) + pp_row59_1 <= booth_b28_m31; + always @(posedge clk) + pp_row59_2 <= booth_b30_m29; + always @(posedge clk) + pp_row59_3 <= booth_b32_m27; + always @(posedge clk) + pp_row60_1 <= booth_b28_m32; + always @(posedge clk) + pp_row60_2 <= booth_b30_m30; + always @(posedge clk) + pp_row60_3 <= booth_b32_m28; + always @(posedge clk) + pp_row61_0 <= \notsign$1180 ; + always @(posedge clk) + pp_row61_1 <= booth_b30_m31; + always @(posedge clk) + pp_row61_2 <= booth_b32_m29; + always @(posedge clk) + pp_row62_1 <= booth_b30_m32; + always @(posedge clk) + pp_row62_2 <= booth_b32_m30; + always @(posedge clk) + pp_row63_0 <= \notsign$1190 ; + always @(posedge clk) + pp_row63_1 <= booth_b32_m31; + always @(posedge clk) + pp_row64_1 <= booth_b32_m32; + always @(posedge clk) + final_a_registered <= { \c$1256 , \c$1255 , \c$1254 , \c$1253 , \c$1252 , \c$1251 , \c$1250 , \c$1249 , \c$1248 , \c$1247 , \c$1246 , \c$1245 , \c$1244 , \c$1243 , \c$1242 , \c$1241 , \c$1240 , \c$1239 , \c$1238 , \c$1237 , \c$1236 , \c$1235 , \c$1234 , \c$1233 , \c$1232 , \c$1231 , \c$1230 , \c$1229 , \c$1228 , \c$1227 , \c$1226 , \c$1225 , \c$1224 , \c$1223 , \c$1222 , \c$1221 , \c$1220 , \c$1219 , \c$1218 , \c$1217 , \c$1216 , \c$1215 , \c$1214 , \c$1213 , \c$1212 , \c$1211 , \c$1210 , \c$1209 , \c$1208 , \c$1207 , \c$1206 , \c$1205 , \c$1204 , \c$1203 , \c$1202 , \c$1201 , \c$1200 , \c$1199 , \c$1198 , \c$1197 , c, pp_row2_2, pp_row1_0, pp_row0_0 }; + always @(posedge clk) + final_b_registered <= { \s$1320 , \s$1319 , \s$1318 , \s$1317 , \s$1316 , \s$1315 , \s$1314 , \s$1313 , \s$1312 , \s$1311 , \s$1310 , \s$1309 , \s$1308 , \s$1307 , \s$1306 , \s$1305 , \s$1304 , \s$1303 , \s$1302 , \s$1301 , \s$1300 , \s$1299 , \s$1298 , \s$1297 , \s$1296 , \s$1295 , \s$1294 , \s$1293 , \s$1292 , \s$1291 , \s$1290 , \s$1289 , \s$1288 , \s$1287 , \s$1286 , \s$1285 , \s$1284 , \s$1283 , \s$1282 , \s$1281 , \s$1280 , \s$1279 , \s$1278 , \s$1277 , \s$1276 , \s$1275 , \s$1274 , \s$1273 , \s$1272 , \s$1271 , \s$1270 , \s$1269 , \s$1268 , \s$1267 , \s$1266 , \s$1265 , \s$1264 , \s$1263 , \s$1262 , \s$1261 , \s$1260 , s, 1'h0, pp_row0_1 }; + always @(posedge clk) + o <= { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + XOR2x1_ASAP7_75t_R \U$1000 ( + .A(\t$2197 ), + .B(a_registered[13]), + .Y(booth_b12_m18) + ); + AO22x1_ASAP7_75t_R \U$1001 ( + .A1(b_registered[18]), + .A2(\sel_0$1550 ), + .B1(b_registered[19]), + .B2(\sel_1$1551 ), + .Y(\t$2198 ) + ); + XOR2x1_ASAP7_75t_R \U$1002 ( + .A(\t$2198 ), + .B(a_registered[13]), + .Y(booth_b12_m19) + ); + AO22x1_ASAP7_75t_R \U$1003 ( + .A1(b_registered[19]), + .A2(\sel_0$1550 ), + .B1(b_registered[20]), + .B2(\sel_1$1551 ), + .Y(\t$2199 ) + ); + XOR2x1_ASAP7_75t_R \U$1004 ( + .A(\t$2199 ), + .B(a_registered[13]), + .Y(booth_b12_m20) + ); + AO22x1_ASAP7_75t_R \U$1005 ( + .A1(b_registered[20]), + .A2(\sel_0$1550 ), + .B1(b_registered[21]), + .B2(\sel_1$1551 ), + .Y(\t$2200 ) + ); + XOR2x1_ASAP7_75t_R \U$1006 ( + .A(\t$2200 ), + .B(a_registered[13]), + .Y(booth_b12_m21) + ); + AO22x1_ASAP7_75t_R \U$1007 ( + .A1(b_registered[21]), + .A2(\sel_0$1550 ), + .B1(b_registered[22]), + .B2(\sel_1$1551 ), + .Y(\t$2201 ) + ); + XOR2x1_ASAP7_75t_R \U$1008 ( + .A(\t$2201 ), + .B(a_registered[13]), + .Y(booth_b12_m22) + ); + AO22x1_ASAP7_75t_R \U$1009 ( + .A1(b_registered[22]), + .A2(\sel_0$1550 ), + .B1(b_registered[23]), + .B2(\sel_1$1551 ), + .Y(\t$2202 ) + ); + XOR2x1_ASAP7_75t_R \U$1010 ( + .A(\t$2202 ), + .B(a_registered[13]), + .Y(booth_b12_m23) + ); + AO22x1_ASAP7_75t_R \U$1011 ( + .A1(b_registered[23]), + .A2(\sel_0$1550 ), + .B1(b_registered[24]), + .B2(\sel_1$1551 ), + .Y(\t$2203 ) + ); + XOR2x1_ASAP7_75t_R \U$1012 ( + .A(\t$2203 ), + .B(a_registered[13]), + .Y(booth_b12_m24) + ); + AO22x1_ASAP7_75t_R \U$1013 ( + .A1(b_registered[24]), + .A2(\sel_0$1550 ), + .B1(b_registered[25]), + .B2(\sel_1$1551 ), + .Y(\t$2204 ) + ); + XOR2x1_ASAP7_75t_R \U$1014 ( + .A(\t$2204 ), + .B(a_registered[13]), + .Y(booth_b12_m25) + ); + AO22x1_ASAP7_75t_R \U$1015 ( + .A1(b_registered[25]), + .A2(\sel_0$1550 ), + .B1(b_registered[26]), + .B2(\sel_1$1551 ), + .Y(\t$2205 ) + ); + XOR2x1_ASAP7_75t_R \U$1016 ( + .A(\t$2205 ), + .B(a_registered[13]), + .Y(booth_b12_m26) + ); + AO22x1_ASAP7_75t_R \U$1017 ( + .A1(b_registered[26]), + .A2(\sel_0$1550 ), + .B1(b_registered[27]), + .B2(\sel_1$1551 ), + .Y(\t$2206 ) + ); + XOR2x1_ASAP7_75t_R \U$1018 ( + .A(\t$2206 ), + .B(a_registered[13]), + .Y(booth_b12_m27) + ); + AO22x1_ASAP7_75t_R \U$1019 ( + .A1(b_registered[27]), + .A2(\sel_0$1550 ), + .B1(b_registered[28]), + .B2(\sel_1$1551 ), + .Y(\t$2207 ) + ); + XOR2x1_ASAP7_75t_R \U$1020 ( + .A(\t$2207 ), + .B(a_registered[13]), + .Y(booth_b12_m28) + ); + AO22x1_ASAP7_75t_R \U$1021 ( + .A1(b_registered[28]), + .A2(\sel_0$1550 ), + .B1(b_registered[29]), + .B2(\sel_1$1551 ), + .Y(\t$2208 ) + ); + XOR2x1_ASAP7_75t_R \U$1022 ( + .A(\t$2208 ), + .B(a_registered[13]), + .Y(booth_b12_m29) + ); + AO22x1_ASAP7_75t_R \U$1023 ( + .A1(b_registered[29]), + .A2(\sel_0$1550 ), + .B1(b_registered[30]), + .B2(\sel_1$1551 ), + .Y(\t$2209 ) + ); + XOR2x1_ASAP7_75t_R \U$1024 ( + .A(\t$2209 ), + .B(a_registered[13]), + .Y(booth_b12_m30) + ); + AO22x1_ASAP7_75t_R \U$1025 ( + .A1(b_registered[30]), + .A2(\sel_0$1550 ), + .B1(b_registered[31]), + .B2(\sel_1$1551 ), + .Y(\t$2210 ) + ); + XOR2x1_ASAP7_75t_R \U$1026 ( + .A(\t$2210 ), + .B(a_registered[13]), + .Y(booth_b12_m31) + ); + AO22x1_ASAP7_75t_R \U$1027 ( + .A1(b_registered[31]), + .A2(\sel_0$1550 ), + .B1(1'h0), + .B2(\sel_1$1551 ), + .Y(\t$2211 ) + ); + XOR2x1_ASAP7_75t_R \U$1028 ( + .A(\t$2211 ), + .B(a_registered[13]), + .Y(booth_b12_m32) + ); + INVx1_ASAP7_75t_R \U$1029 ( + .A(a_registered[13]), + .Y(\notsign$956 ) + ); + INVx1_ASAP7_75t_R \U$1030 ( + .A(a_registered[13]), + .Y(\$22 ) + ); + INVx1_ASAP7_75t_R \U$1031 ( + .A(a_registered[14]), + .Y(\$23 ) + ); + INVx1_ASAP7_75t_R \U$1032 ( + .A(a_registered[15]), + .Y(\$24 ) + ); + AO33x2_ASAP7_75t_R \U$1033 ( + .A1(\$24 ), + .A2(a_registered[14]), + .A3(a_registered[13]), + .B1(a_registered[15]), + .B2(\$23 ), + .B3(\$22 ), + .Y(\sel_0$1587 ) + ); + XOR2x1_ASAP7_75t_R \U$1034 ( + .A(a_registered[14]), + .B(a_registered[13]), + .Y(\sel_1$1588 ) + ); + AO22x1_ASAP7_75t_R \U$1035 ( + .A1(1'h0), + .A2(\sel_0$1587 ), + .B1(b_registered[0]), + .B2(\sel_1$1588 ), + .Y(\t$2213 ) + ); + XOR2x1_ASAP7_75t_R \U$1036 ( + .A(\t$2213 ), + .B(a_registered[15]), + .Y(booth_b14_m0) + ); + AO22x1_ASAP7_75t_R \U$1037 ( + .A1(b_registered[0]), + .A2(\sel_0$1587 ), + .B1(b_registered[1]), + .B2(\sel_1$1588 ), + .Y(\t$2214 ) + ); + XOR2x1_ASAP7_75t_R \U$1038 ( + .A(\t$2214 ), + .B(a_registered[15]), + .Y(booth_b14_m1) + ); + AO22x1_ASAP7_75t_R \U$1039 ( + .A1(b_registered[1]), + .A2(\sel_0$1587 ), + .B1(b_registered[2]), + .B2(\sel_1$1588 ), + .Y(\t$2215 ) + ); + XOR2x1_ASAP7_75t_R \U$1040 ( + .A(\t$2215 ), + .B(a_registered[15]), + .Y(booth_b14_m2) + ); + AO22x1_ASAP7_75t_R \U$1041 ( + .A1(b_registered[2]), + .A2(\sel_0$1587 ), + .B1(b_registered[3]), + .B2(\sel_1$1588 ), + .Y(\t$2216 ) + ); + XOR2x1_ASAP7_75t_R \U$1042 ( + .A(\t$2216 ), + .B(a_registered[15]), + .Y(booth_b14_m3) + ); + AO22x1_ASAP7_75t_R \U$1043 ( + .A1(b_registered[3]), + .A2(\sel_0$1587 ), + .B1(b_registered[4]), + .B2(\sel_1$1588 ), + .Y(\t$2217 ) + ); + XOR2x1_ASAP7_75t_R \U$1044 ( + .A(\t$2217 ), + .B(a_registered[15]), + .Y(booth_b14_m4) + ); + AO22x1_ASAP7_75t_R \U$1045 ( + .A1(b_registered[4]), + .A2(\sel_0$1587 ), + .B1(b_registered[5]), + .B2(\sel_1$1588 ), + .Y(\t$2218 ) + ); + XOR2x1_ASAP7_75t_R \U$1046 ( + .A(\t$2218 ), + .B(a_registered[15]), + .Y(booth_b14_m5) + ); + AO22x1_ASAP7_75t_R \U$1047 ( + .A1(b_registered[5]), + .A2(\sel_0$1587 ), + .B1(b_registered[6]), + .B2(\sel_1$1588 ), + .Y(\t$2219 ) + ); + XOR2x1_ASAP7_75t_R \U$1048 ( + .A(\t$2219 ), + .B(a_registered[15]), + .Y(booth_b14_m6) + ); + AO22x1_ASAP7_75t_R \U$1049 ( + .A1(b_registered[6]), + .A2(\sel_0$1587 ), + .B1(b_registered[7]), + .B2(\sel_1$1588 ), + .Y(\t$2220 ) + ); + XOR2x1_ASAP7_75t_R \U$1050 ( + .A(\t$2220 ), + .B(a_registered[15]), + .Y(booth_b14_m7) + ); + AO22x1_ASAP7_75t_R \U$1051 ( + .A1(b_registered[7]), + .A2(\sel_0$1587 ), + .B1(b_registered[8]), + .B2(\sel_1$1588 ), + .Y(\t$2221 ) + ); + XOR2x1_ASAP7_75t_R \U$1052 ( + .A(\t$2221 ), + .B(a_registered[15]), + .Y(booth_b14_m8) + ); + AO22x1_ASAP7_75t_R \U$1053 ( + .A1(b_registered[8]), + .A2(\sel_0$1587 ), + .B1(b_registered[9]), + .B2(\sel_1$1588 ), + .Y(\t$2222 ) + ); + XOR2x1_ASAP7_75t_R \U$1054 ( + .A(\t$2222 ), + .B(a_registered[15]), + .Y(booth_b14_m9) + ); + AO22x1_ASAP7_75t_R \U$1055 ( + .A1(b_registered[9]), + .A2(\sel_0$1587 ), + .B1(b_registered[10]), + .B2(\sel_1$1588 ), + .Y(\t$2223 ) + ); + XOR2x1_ASAP7_75t_R \U$1056 ( + .A(\t$2223 ), + .B(a_registered[15]), + .Y(booth_b14_m10) + ); + AO22x1_ASAP7_75t_R \U$1057 ( + .A1(b_registered[10]), + .A2(\sel_0$1587 ), + .B1(b_registered[11]), + .B2(\sel_1$1588 ), + .Y(\t$2224 ) + ); + XOR2x1_ASAP7_75t_R \U$1058 ( + .A(\t$2224 ), + .B(a_registered[15]), + .Y(booth_b14_m11) + ); + AO22x1_ASAP7_75t_R \U$1059 ( + .A1(b_registered[11]), + .A2(\sel_0$1587 ), + .B1(b_registered[12]), + .B2(\sel_1$1588 ), + .Y(\t$2225 ) + ); + XOR2x1_ASAP7_75t_R \U$1060 ( + .A(\t$2225 ), + .B(a_registered[15]), + .Y(booth_b14_m12) + ); + AO22x1_ASAP7_75t_R \U$1061 ( + .A1(b_registered[12]), + .A2(\sel_0$1587 ), + .B1(b_registered[13]), + .B2(\sel_1$1588 ), + .Y(\t$2226 ) + ); + XOR2x1_ASAP7_75t_R \U$1062 ( + .A(\t$2226 ), + .B(a_registered[15]), + .Y(booth_b14_m13) + ); + AO22x1_ASAP7_75t_R \U$1063 ( + .A1(b_registered[13]), + .A2(\sel_0$1587 ), + .B1(b_registered[14]), + .B2(\sel_1$1588 ), + .Y(\t$2227 ) + ); + XOR2x1_ASAP7_75t_R \U$1064 ( + .A(\t$2227 ), + .B(a_registered[15]), + .Y(booth_b14_m14) + ); + AO22x1_ASAP7_75t_R \U$1065 ( + .A1(b_registered[14]), + .A2(\sel_0$1587 ), + .B1(b_registered[15]), + .B2(\sel_1$1588 ), + .Y(\t$2228 ) + ); + XOR2x1_ASAP7_75t_R \U$1066 ( + .A(\t$2228 ), + .B(a_registered[15]), + .Y(booth_b14_m15) + ); + AO22x1_ASAP7_75t_R \U$1067 ( + .A1(b_registered[15]), + .A2(\sel_0$1587 ), + .B1(b_registered[16]), + .B2(\sel_1$1588 ), + .Y(\t$2229 ) + ); + XOR2x1_ASAP7_75t_R \U$1068 ( + .A(\t$2229 ), + .B(a_registered[15]), + .Y(booth_b14_m16) + ); + AO22x1_ASAP7_75t_R \U$1069 ( + .A1(b_registered[16]), + .A2(\sel_0$1587 ), + .B1(b_registered[17]), + .B2(\sel_1$1588 ), + .Y(\t$2230 ) + ); + XOR2x1_ASAP7_75t_R \U$1070 ( + .A(\t$2230 ), + .B(a_registered[15]), + .Y(booth_b14_m17) + ); + AO22x1_ASAP7_75t_R \U$1071 ( + .A1(b_registered[17]), + .A2(\sel_0$1587 ), + .B1(b_registered[18]), + .B2(\sel_1$1588 ), + .Y(\t$2231 ) + ); + XOR2x1_ASAP7_75t_R \U$1072 ( + .A(\t$2231 ), + .B(a_registered[15]), + .Y(booth_b14_m18) + ); + AO22x1_ASAP7_75t_R \U$1073 ( + .A1(b_registered[18]), + .A2(\sel_0$1587 ), + .B1(b_registered[19]), + .B2(\sel_1$1588 ), + .Y(\t$2232 ) + ); + XOR2x1_ASAP7_75t_R \U$1074 ( + .A(\t$2232 ), + .B(a_registered[15]), + .Y(booth_b14_m19) + ); + AO22x1_ASAP7_75t_R \U$1075 ( + .A1(b_registered[19]), + .A2(\sel_0$1587 ), + .B1(b_registered[20]), + .B2(\sel_1$1588 ), + .Y(\t$2233 ) + ); + XOR2x1_ASAP7_75t_R \U$1076 ( + .A(\t$2233 ), + .B(a_registered[15]), + .Y(booth_b14_m20) + ); + AO22x1_ASAP7_75t_R \U$1077 ( + .A1(b_registered[20]), + .A2(\sel_0$1587 ), + .B1(b_registered[21]), + .B2(\sel_1$1588 ), + .Y(\t$2234 ) + ); + XOR2x1_ASAP7_75t_R \U$1078 ( + .A(\t$2234 ), + .B(a_registered[15]), + .Y(booth_b14_m21) + ); + AO22x1_ASAP7_75t_R \U$1079 ( + .A1(b_registered[21]), + .A2(\sel_0$1587 ), + .B1(b_registered[22]), + .B2(\sel_1$1588 ), + .Y(\t$2235 ) + ); + XOR2x1_ASAP7_75t_R \U$1080 ( + .A(\t$2235 ), + .B(a_registered[15]), + .Y(booth_b14_m22) + ); + AO22x1_ASAP7_75t_R \U$1081 ( + .A1(b_registered[22]), + .A2(\sel_0$1587 ), + .B1(b_registered[23]), + .B2(\sel_1$1588 ), + .Y(\t$2236 ) + ); + XOR2x1_ASAP7_75t_R \U$1082 ( + .A(\t$2236 ), + .B(a_registered[15]), + .Y(booth_b14_m23) + ); + AO22x1_ASAP7_75t_R \U$1083 ( + .A1(b_registered[23]), + .A2(\sel_0$1587 ), + .B1(b_registered[24]), + .B2(\sel_1$1588 ), + .Y(\t$2237 ) + ); + XOR2x1_ASAP7_75t_R \U$1084 ( + .A(\t$2237 ), + .B(a_registered[15]), + .Y(booth_b14_m24) + ); + AO22x1_ASAP7_75t_R \U$1085 ( + .A1(b_registered[24]), + .A2(\sel_0$1587 ), + .B1(b_registered[25]), + .B2(\sel_1$1588 ), + .Y(\t$2238 ) + ); + XOR2x1_ASAP7_75t_R \U$1086 ( + .A(\t$2238 ), + .B(a_registered[15]), + .Y(booth_b14_m25) + ); + AO22x1_ASAP7_75t_R \U$1087 ( + .A1(b_registered[25]), + .A2(\sel_0$1587 ), + .B1(b_registered[26]), + .B2(\sel_1$1588 ), + .Y(\t$2239 ) + ); + XOR2x1_ASAP7_75t_R \U$1088 ( + .A(\t$2239 ), + .B(a_registered[15]), + .Y(booth_b14_m26) + ); + AO22x1_ASAP7_75t_R \U$1089 ( + .A1(b_registered[26]), + .A2(\sel_0$1587 ), + .B1(b_registered[27]), + .B2(\sel_1$1588 ), + .Y(\t$2240 ) + ); + XOR2x1_ASAP7_75t_R \U$1090 ( + .A(\t$2240 ), + .B(a_registered[15]), + .Y(booth_b14_m27) + ); + AO22x1_ASAP7_75t_R \U$1091 ( + .A1(b_registered[27]), + .A2(\sel_0$1587 ), + .B1(b_registered[28]), + .B2(\sel_1$1588 ), + .Y(\t$2241 ) + ); + XOR2x1_ASAP7_75t_R \U$1092 ( + .A(\t$2241 ), + .B(a_registered[15]), + .Y(booth_b14_m28) + ); + AO22x1_ASAP7_75t_R \U$1093 ( + .A1(b_registered[28]), + .A2(\sel_0$1587 ), + .B1(b_registered[29]), + .B2(\sel_1$1588 ), + .Y(\t$2242 ) + ); + XOR2x1_ASAP7_75t_R \U$1094 ( + .A(\t$2242 ), + .B(a_registered[15]), + .Y(booth_b14_m29) + ); + AO22x1_ASAP7_75t_R \U$1095 ( + .A1(b_registered[29]), + .A2(\sel_0$1587 ), + .B1(b_registered[30]), + .B2(\sel_1$1588 ), + .Y(\t$2243 ) + ); + XOR2x1_ASAP7_75t_R \U$1096 ( + .A(\t$2243 ), + .B(a_registered[15]), + .Y(booth_b14_m30) + ); + AO22x1_ASAP7_75t_R \U$1097 ( + .A1(b_registered[30]), + .A2(\sel_0$1587 ), + .B1(b_registered[31]), + .B2(\sel_1$1588 ), + .Y(\t$2244 ) + ); + XOR2x1_ASAP7_75t_R \U$1098 ( + .A(\t$2244 ), + .B(a_registered[15]), + .Y(booth_b14_m31) + ); + AO22x1_ASAP7_75t_R \U$1099 ( + .A1(b_registered[31]), + .A2(\sel_0$1587 ), + .B1(1'h0), + .B2(\sel_1$1588 ), + .Y(\t$2245 ) + ); + XOR2x1_ASAP7_75t_R \U$1100 ( + .A(\t$2245 ), + .B(a_registered[15]), + .Y(booth_b14_m32) + ); + INVx1_ASAP7_75t_R \U$1101 ( + .A(a_registered[15]), + .Y(\notsign$998 ) + ); + INVx1_ASAP7_75t_R \U$1102 ( + .A(a_registered[15]), + .Y(\$25 ) + ); + INVx1_ASAP7_75t_R \U$1103 ( + .A(a_registered[16]), + .Y(\$26 ) + ); + INVx1_ASAP7_75t_R \U$1104 ( + .A(a_registered[17]), + .Y(\$27 ) + ); + AO33x2_ASAP7_75t_R \U$1105 ( + .A1(\$27 ), + .A2(a_registered[16]), + .A3(a_registered[15]), + .B1(a_registered[17]), + .B2(\$26 ), + .B3(\$25 ), + .Y(\sel_0$1624 ) + ); + XOR2x1_ASAP7_75t_R \U$1106 ( + .A(a_registered[16]), + .B(a_registered[15]), + .Y(\sel_1$1625 ) + ); + AO22x1_ASAP7_75t_R \U$1107 ( + .A1(1'h0), + .A2(\sel_0$1624 ), + .B1(b_registered[0]), + .B2(\sel_1$1625 ), + .Y(\t$2247 ) + ); + XOR2x1_ASAP7_75t_R \U$1108 ( + .A(\t$2247 ), + .B(a_registered[17]), + .Y(booth_b16_m0) + ); + AO22x1_ASAP7_75t_R \U$1109 ( + .A1(b_registered[0]), + .A2(\sel_0$1624 ), + .B1(b_registered[1]), + .B2(\sel_1$1625 ), + .Y(\t$2248 ) + ); + XOR2x1_ASAP7_75t_R \U$1110 ( + .A(\t$2248 ), + .B(a_registered[17]), + .Y(booth_b16_m1) + ); + AO22x1_ASAP7_75t_R \U$1111 ( + .A1(b_registered[1]), + .A2(\sel_0$1624 ), + .B1(b_registered[2]), + .B2(\sel_1$1625 ), + .Y(\t$2249 ) + ); + XOR2x1_ASAP7_75t_R \U$1112 ( + .A(\t$2249 ), + .B(a_registered[17]), + .Y(booth_b16_m2) + ); + AO22x1_ASAP7_75t_R \U$1113 ( + .A1(b_registered[2]), + .A2(\sel_0$1624 ), + .B1(b_registered[3]), + .B2(\sel_1$1625 ), + .Y(\t$2250 ) + ); + XOR2x1_ASAP7_75t_R \U$1114 ( + .A(\t$2250 ), + .B(a_registered[17]), + .Y(booth_b16_m3) + ); + AO22x1_ASAP7_75t_R \U$1115 ( + .A1(b_registered[3]), + .A2(\sel_0$1624 ), + .B1(b_registered[4]), + .B2(\sel_1$1625 ), + .Y(\t$2251 ) + ); + XOR2x1_ASAP7_75t_R \U$1116 ( + .A(\t$2251 ), + .B(a_registered[17]), + .Y(booth_b16_m4) + ); + AO22x1_ASAP7_75t_R \U$1117 ( + .A1(b_registered[4]), + .A2(\sel_0$1624 ), + .B1(b_registered[5]), + .B2(\sel_1$1625 ), + .Y(\t$2252 ) + ); + XOR2x1_ASAP7_75t_R \U$1118 ( + .A(\t$2252 ), + .B(a_registered[17]), + .Y(booth_b16_m5) + ); + AO22x1_ASAP7_75t_R \U$1119 ( + .A1(b_registered[5]), + .A2(\sel_0$1624 ), + .B1(b_registered[6]), + .B2(\sel_1$1625 ), + .Y(\t$2253 ) + ); + XOR2x1_ASAP7_75t_R \U$1120 ( + .A(\t$2253 ), + .B(a_registered[17]), + .Y(booth_b16_m6) + ); + AO22x1_ASAP7_75t_R \U$1121 ( + .A1(b_registered[6]), + .A2(\sel_0$1624 ), + .B1(b_registered[7]), + .B2(\sel_1$1625 ), + .Y(\t$2254 ) + ); + XOR2x1_ASAP7_75t_R \U$1122 ( + .A(\t$2254 ), + .B(a_registered[17]), + .Y(booth_b16_m7) + ); + AO22x1_ASAP7_75t_R \U$1123 ( + .A1(b_registered[7]), + .A2(\sel_0$1624 ), + .B1(b_registered[8]), + .B2(\sel_1$1625 ), + .Y(\t$2255 ) + ); + XOR2x1_ASAP7_75t_R \U$1124 ( + .A(\t$2255 ), + .B(a_registered[17]), + .Y(booth_b16_m8) + ); + AO22x1_ASAP7_75t_R \U$1125 ( + .A1(b_registered[8]), + .A2(\sel_0$1624 ), + .B1(b_registered[9]), + .B2(\sel_1$1625 ), + .Y(\t$2256 ) + ); + XOR2x1_ASAP7_75t_R \U$1126 ( + .A(\t$2256 ), + .B(a_registered[17]), + .Y(booth_b16_m9) + ); + AO22x1_ASAP7_75t_R \U$1127 ( + .A1(b_registered[9]), + .A2(\sel_0$1624 ), + .B1(b_registered[10]), + .B2(\sel_1$1625 ), + .Y(\t$2257 ) + ); + XOR2x1_ASAP7_75t_R \U$1128 ( + .A(\t$2257 ), + .B(a_registered[17]), + .Y(booth_b16_m10) + ); + AO22x1_ASAP7_75t_R \U$1129 ( + .A1(b_registered[10]), + .A2(\sel_0$1624 ), + .B1(b_registered[11]), + .B2(\sel_1$1625 ), + .Y(\t$2258 ) + ); + XOR2x1_ASAP7_75t_R \U$1130 ( + .A(\t$2258 ), + .B(a_registered[17]), + .Y(booth_b16_m11) + ); + AO22x1_ASAP7_75t_R \U$1131 ( + .A1(b_registered[11]), + .A2(\sel_0$1624 ), + .B1(b_registered[12]), + .B2(\sel_1$1625 ), + .Y(\t$2259 ) + ); + XOR2x1_ASAP7_75t_R \U$1132 ( + .A(\t$2259 ), + .B(a_registered[17]), + .Y(booth_b16_m12) + ); + AO22x1_ASAP7_75t_R \U$1133 ( + .A1(b_registered[12]), + .A2(\sel_0$1624 ), + .B1(b_registered[13]), + .B2(\sel_1$1625 ), + .Y(\t$2260 ) + ); + XOR2x1_ASAP7_75t_R \U$1134 ( + .A(\t$2260 ), + .B(a_registered[17]), + .Y(booth_b16_m13) + ); + AO22x1_ASAP7_75t_R \U$1135 ( + .A1(b_registered[13]), + .A2(\sel_0$1624 ), + .B1(b_registered[14]), + .B2(\sel_1$1625 ), + .Y(\t$2261 ) + ); + XOR2x1_ASAP7_75t_R \U$1136 ( + .A(\t$2261 ), + .B(a_registered[17]), + .Y(booth_b16_m14) + ); + AO22x1_ASAP7_75t_R \U$1137 ( + .A1(b_registered[14]), + .A2(\sel_0$1624 ), + .B1(b_registered[15]), + .B2(\sel_1$1625 ), + .Y(\t$2262 ) + ); + XOR2x1_ASAP7_75t_R \U$1138 ( + .A(\t$2262 ), + .B(a_registered[17]), + .Y(booth_b16_m15) + ); + AO22x1_ASAP7_75t_R \U$1139 ( + .A1(b_registered[15]), + .A2(\sel_0$1624 ), + .B1(b_registered[16]), + .B2(\sel_1$1625 ), + .Y(\t$2263 ) + ); + XOR2x1_ASAP7_75t_R \U$1140 ( + .A(\t$2263 ), + .B(a_registered[17]), + .Y(booth_b16_m16) + ); + AO22x1_ASAP7_75t_R \U$1141 ( + .A1(b_registered[16]), + .A2(\sel_0$1624 ), + .B1(b_registered[17]), + .B2(\sel_1$1625 ), + .Y(\t$2264 ) + ); + XOR2x1_ASAP7_75t_R \U$1142 ( + .A(\t$2264 ), + .B(a_registered[17]), + .Y(booth_b16_m17) + ); + AO22x1_ASAP7_75t_R \U$1143 ( + .A1(b_registered[17]), + .A2(\sel_0$1624 ), + .B1(b_registered[18]), + .B2(\sel_1$1625 ), + .Y(\t$2265 ) + ); + XOR2x1_ASAP7_75t_R \U$1144 ( + .A(\t$2265 ), + .B(a_registered[17]), + .Y(booth_b16_m18) + ); + AO22x1_ASAP7_75t_R \U$1145 ( + .A1(b_registered[18]), + .A2(\sel_0$1624 ), + .B1(b_registered[19]), + .B2(\sel_1$1625 ), + .Y(\t$2266 ) + ); + XOR2x1_ASAP7_75t_R \U$1146 ( + .A(\t$2266 ), + .B(a_registered[17]), + .Y(booth_b16_m19) + ); + AO22x1_ASAP7_75t_R \U$1147 ( + .A1(b_registered[19]), + .A2(\sel_0$1624 ), + .B1(b_registered[20]), + .B2(\sel_1$1625 ), + .Y(\t$2267 ) + ); + XOR2x1_ASAP7_75t_R \U$1148 ( + .A(\t$2267 ), + .B(a_registered[17]), + .Y(booth_b16_m20) + ); + AO22x1_ASAP7_75t_R \U$1149 ( + .A1(b_registered[20]), + .A2(\sel_0$1624 ), + .B1(b_registered[21]), + .B2(\sel_1$1625 ), + .Y(\t$2268 ) + ); + XOR2x1_ASAP7_75t_R \U$1150 ( + .A(\t$2268 ), + .B(a_registered[17]), + .Y(booth_b16_m21) + ); + AO22x1_ASAP7_75t_R \U$1151 ( + .A1(b_registered[21]), + .A2(\sel_0$1624 ), + .B1(b_registered[22]), + .B2(\sel_1$1625 ), + .Y(\t$2269 ) + ); + XOR2x1_ASAP7_75t_R \U$1152 ( + .A(\t$2269 ), + .B(a_registered[17]), + .Y(booth_b16_m22) + ); + AO22x1_ASAP7_75t_R \U$1153 ( + .A1(b_registered[22]), + .A2(\sel_0$1624 ), + .B1(b_registered[23]), + .B2(\sel_1$1625 ), + .Y(\t$2270 ) + ); + XOR2x1_ASAP7_75t_R \U$1154 ( + .A(\t$2270 ), + .B(a_registered[17]), + .Y(booth_b16_m23) + ); + AO22x1_ASAP7_75t_R \U$1155 ( + .A1(b_registered[23]), + .A2(\sel_0$1624 ), + .B1(b_registered[24]), + .B2(\sel_1$1625 ), + .Y(\t$2271 ) + ); + XOR2x1_ASAP7_75t_R \U$1156 ( + .A(\t$2271 ), + .B(a_registered[17]), + .Y(booth_b16_m24) + ); + AO22x1_ASAP7_75t_R \U$1157 ( + .A1(b_registered[24]), + .A2(\sel_0$1624 ), + .B1(b_registered[25]), + .B2(\sel_1$1625 ), + .Y(\t$2272 ) + ); + XOR2x1_ASAP7_75t_R \U$1158 ( + .A(\t$2272 ), + .B(a_registered[17]), + .Y(booth_b16_m25) + ); + AO22x1_ASAP7_75t_R \U$1159 ( + .A1(b_registered[25]), + .A2(\sel_0$1624 ), + .B1(b_registered[26]), + .B2(\sel_1$1625 ), + .Y(\t$2273 ) + ); + XOR2x1_ASAP7_75t_R \U$1160 ( + .A(\t$2273 ), + .B(a_registered[17]), + .Y(booth_b16_m26) + ); + AO22x1_ASAP7_75t_R \U$1161 ( + .A1(b_registered[26]), + .A2(\sel_0$1624 ), + .B1(b_registered[27]), + .B2(\sel_1$1625 ), + .Y(\t$2274 ) + ); + XOR2x1_ASAP7_75t_R \U$1162 ( + .A(\t$2274 ), + .B(a_registered[17]), + .Y(booth_b16_m27) + ); + AO22x1_ASAP7_75t_R \U$1163 ( + .A1(b_registered[27]), + .A2(\sel_0$1624 ), + .B1(b_registered[28]), + .B2(\sel_1$1625 ), + .Y(\t$2275 ) + ); + XOR2x1_ASAP7_75t_R \U$1164 ( + .A(\t$2275 ), + .B(a_registered[17]), + .Y(booth_b16_m28) + ); + AO22x1_ASAP7_75t_R \U$1165 ( + .A1(b_registered[28]), + .A2(\sel_0$1624 ), + .B1(b_registered[29]), + .B2(\sel_1$1625 ), + .Y(\t$2276 ) + ); + XOR2x1_ASAP7_75t_R \U$1166 ( + .A(\t$2276 ), + .B(a_registered[17]), + .Y(booth_b16_m29) + ); + AO22x1_ASAP7_75t_R \U$1167 ( + .A1(b_registered[29]), + .A2(\sel_0$1624 ), + .B1(b_registered[30]), + .B2(\sel_1$1625 ), + .Y(\t$2277 ) + ); + XOR2x1_ASAP7_75t_R \U$1168 ( + .A(\t$2277 ), + .B(a_registered[17]), + .Y(booth_b16_m30) + ); + AO22x1_ASAP7_75t_R \U$1169 ( + .A1(b_registered[30]), + .A2(\sel_0$1624 ), + .B1(b_registered[31]), + .B2(\sel_1$1625 ), + .Y(\t$2278 ) + ); + XOR2x1_ASAP7_75t_R \U$1170 ( + .A(\t$2278 ), + .B(a_registered[17]), + .Y(booth_b16_m31) + ); + AO22x1_ASAP7_75t_R \U$1171 ( + .A1(b_registered[31]), + .A2(\sel_0$1624 ), + .B1(1'h0), + .B2(\sel_1$1625 ), + .Y(\t$2279 ) + ); + XOR2x1_ASAP7_75t_R \U$1172 ( + .A(\t$2279 ), + .B(a_registered[17]), + .Y(booth_b16_m32) + ); + INVx1_ASAP7_75t_R \U$1173 ( + .A(a_registered[17]), + .Y(\notsign$1036 ) + ); + INVx1_ASAP7_75t_R \U$1174 ( + .A(a_registered[17]), + .Y(\$28 ) + ); + INVx1_ASAP7_75t_R \U$1175 ( + .A(a_registered[18]), + .Y(\$29 ) + ); + INVx1_ASAP7_75t_R \U$1176 ( + .A(a_registered[19]), + .Y(\$30 ) + ); + AO33x2_ASAP7_75t_R \U$1177 ( + .A1(\$30 ), + .A2(a_registered[18]), + .A3(a_registered[17]), + .B1(a_registered[19]), + .B2(\$29 ), + .B3(\$28 ), + .Y(\sel_0$1661 ) + ); + XOR2x1_ASAP7_75t_R \U$1178 ( + .A(a_registered[18]), + .B(a_registered[17]), + .Y(\sel_1$1662 ) + ); + AO22x1_ASAP7_75t_R \U$1179 ( + .A1(1'h0), + .A2(\sel_0$1661 ), + .B1(b_registered[0]), + .B2(\sel_1$1662 ), + .Y(\t$2281 ) + ); + XOR2x1_ASAP7_75t_R \U$1180 ( + .A(\t$2281 ), + .B(a_registered[19]), + .Y(booth_b18_m0) + ); + AO22x1_ASAP7_75t_R \U$1181 ( + .A1(b_registered[0]), + .A2(\sel_0$1661 ), + .B1(b_registered[1]), + .B2(\sel_1$1662 ), + .Y(\t$2282 ) + ); + XOR2x1_ASAP7_75t_R \U$1182 ( + .A(\t$2282 ), + .B(a_registered[19]), + .Y(booth_b18_m1) + ); + AO22x1_ASAP7_75t_R \U$1183 ( + .A1(b_registered[1]), + .A2(\sel_0$1661 ), + .B1(b_registered[2]), + .B2(\sel_1$1662 ), + .Y(\t$2283 ) + ); + XOR2x1_ASAP7_75t_R \U$1184 ( + .A(\t$2283 ), + .B(a_registered[19]), + .Y(booth_b18_m2) + ); + AO22x1_ASAP7_75t_R \U$1185 ( + .A1(b_registered[2]), + .A2(\sel_0$1661 ), + .B1(b_registered[3]), + .B2(\sel_1$1662 ), + .Y(\t$2284 ) + ); + XOR2x1_ASAP7_75t_R \U$1186 ( + .A(\t$2284 ), + .B(a_registered[19]), + .Y(booth_b18_m3) + ); + AO22x1_ASAP7_75t_R \U$1187 ( + .A1(b_registered[3]), + .A2(\sel_0$1661 ), + .B1(b_registered[4]), + .B2(\sel_1$1662 ), + .Y(\t$2285 ) + ); + XOR2x1_ASAP7_75t_R \U$1188 ( + .A(\t$2285 ), + .B(a_registered[19]), + .Y(booth_b18_m4) + ); + AO22x1_ASAP7_75t_R \U$1189 ( + .A1(b_registered[4]), + .A2(\sel_0$1661 ), + .B1(b_registered[5]), + .B2(\sel_1$1662 ), + .Y(\t$2286 ) + ); + XOR2x1_ASAP7_75t_R \U$1190 ( + .A(\t$2286 ), + .B(a_registered[19]), + .Y(booth_b18_m5) + ); + AO22x1_ASAP7_75t_R \U$1191 ( + .A1(b_registered[5]), + .A2(\sel_0$1661 ), + .B1(b_registered[6]), + .B2(\sel_1$1662 ), + .Y(\t$2287 ) + ); + XOR2x1_ASAP7_75t_R \U$1192 ( + .A(\t$2287 ), + .B(a_registered[19]), + .Y(booth_b18_m6) + ); + AO22x1_ASAP7_75t_R \U$1193 ( + .A1(b_registered[6]), + .A2(\sel_0$1661 ), + .B1(b_registered[7]), + .B2(\sel_1$1662 ), + .Y(\t$2288 ) + ); + XOR2x1_ASAP7_75t_R \U$1194 ( + .A(\t$2288 ), + .B(a_registered[19]), + .Y(booth_b18_m7) + ); + AO22x1_ASAP7_75t_R \U$1195 ( + .A1(b_registered[7]), + .A2(\sel_0$1661 ), + .B1(b_registered[8]), + .B2(\sel_1$1662 ), + .Y(\t$2289 ) + ); + XOR2x1_ASAP7_75t_R \U$1196 ( + .A(\t$2289 ), + .B(a_registered[19]), + .Y(booth_b18_m8) + ); + AO22x1_ASAP7_75t_R \U$1197 ( + .A1(b_registered[8]), + .A2(\sel_0$1661 ), + .B1(b_registered[9]), + .B2(\sel_1$1662 ), + .Y(\t$2290 ) + ); + XOR2x1_ASAP7_75t_R \U$1198 ( + .A(\t$2290 ), + .B(a_registered[19]), + .Y(booth_b18_m9) + ); + AO22x1_ASAP7_75t_R \U$1199 ( + .A1(b_registered[9]), + .A2(\sel_0$1661 ), + .B1(b_registered[10]), + .B2(\sel_1$1662 ), + .Y(\t$2291 ) + ); + XOR2x1_ASAP7_75t_R \U$1200 ( + .A(\t$2291 ), + .B(a_registered[19]), + .Y(booth_b18_m10) + ); + AO22x1_ASAP7_75t_R \U$1201 ( + .A1(b_registered[10]), + .A2(\sel_0$1661 ), + .B1(b_registered[11]), + .B2(\sel_1$1662 ), + .Y(\t$2292 ) + ); + XOR2x1_ASAP7_75t_R \U$1202 ( + .A(\t$2292 ), + .B(a_registered[19]), + .Y(booth_b18_m11) + ); + AO22x1_ASAP7_75t_R \U$1203 ( + .A1(b_registered[11]), + .A2(\sel_0$1661 ), + .B1(b_registered[12]), + .B2(\sel_1$1662 ), + .Y(\t$2293 ) + ); + XOR2x1_ASAP7_75t_R \U$1204 ( + .A(\t$2293 ), + .B(a_registered[19]), + .Y(booth_b18_m12) + ); + AO22x1_ASAP7_75t_R \U$1205 ( + .A1(b_registered[12]), + .A2(\sel_0$1661 ), + .B1(b_registered[13]), + .B2(\sel_1$1662 ), + .Y(\t$2294 ) + ); + XOR2x1_ASAP7_75t_R \U$1206 ( + .A(\t$2294 ), + .B(a_registered[19]), + .Y(booth_b18_m13) + ); + AO22x1_ASAP7_75t_R \U$1207 ( + .A1(b_registered[13]), + .A2(\sel_0$1661 ), + .B1(b_registered[14]), + .B2(\sel_1$1662 ), + .Y(\t$2295 ) + ); + XOR2x1_ASAP7_75t_R \U$1208 ( + .A(\t$2295 ), + .B(a_registered[19]), + .Y(booth_b18_m14) + ); + AO22x1_ASAP7_75t_R \U$1209 ( + .A1(b_registered[14]), + .A2(\sel_0$1661 ), + .B1(b_registered[15]), + .B2(\sel_1$1662 ), + .Y(\t$2296 ) + ); + XOR2x1_ASAP7_75t_R \U$1210 ( + .A(\t$2296 ), + .B(a_registered[19]), + .Y(booth_b18_m15) + ); + AO22x1_ASAP7_75t_R \U$1211 ( + .A1(b_registered[15]), + .A2(\sel_0$1661 ), + .B1(b_registered[16]), + .B2(\sel_1$1662 ), + .Y(\t$2297 ) + ); + XOR2x1_ASAP7_75t_R \U$1212 ( + .A(\t$2297 ), + .B(a_registered[19]), + .Y(booth_b18_m16) + ); + AO22x1_ASAP7_75t_R \U$1213 ( + .A1(b_registered[16]), + .A2(\sel_0$1661 ), + .B1(b_registered[17]), + .B2(\sel_1$1662 ), + .Y(\t$2298 ) + ); + XOR2x1_ASAP7_75t_R \U$1214 ( + .A(\t$2298 ), + .B(a_registered[19]), + .Y(booth_b18_m17) + ); + AO22x1_ASAP7_75t_R \U$1215 ( + .A1(b_registered[17]), + .A2(\sel_0$1661 ), + .B1(b_registered[18]), + .B2(\sel_1$1662 ), + .Y(\t$2299 ) + ); + XOR2x1_ASAP7_75t_R \U$1216 ( + .A(\t$2299 ), + .B(a_registered[19]), + .Y(booth_b18_m18) + ); + AO22x1_ASAP7_75t_R \U$1217 ( + .A1(b_registered[18]), + .A2(\sel_0$1661 ), + .B1(b_registered[19]), + .B2(\sel_1$1662 ), + .Y(\t$2300 ) + ); + XOR2x1_ASAP7_75t_R \U$1218 ( + .A(\t$2300 ), + .B(a_registered[19]), + .Y(booth_b18_m19) + ); + AO22x1_ASAP7_75t_R \U$1219 ( + .A1(b_registered[19]), + .A2(\sel_0$1661 ), + .B1(b_registered[20]), + .B2(\sel_1$1662 ), + .Y(\t$2301 ) + ); + XOR2x1_ASAP7_75t_R \U$1220 ( + .A(\t$2301 ), + .B(a_registered[19]), + .Y(booth_b18_m20) + ); + AO22x1_ASAP7_75t_R \U$1221 ( + .A1(b_registered[20]), + .A2(\sel_0$1661 ), + .B1(b_registered[21]), + .B2(\sel_1$1662 ), + .Y(\t$2302 ) + ); + XOR2x1_ASAP7_75t_R \U$1222 ( + .A(\t$2302 ), + .B(a_registered[19]), + .Y(booth_b18_m21) + ); + AO22x1_ASAP7_75t_R \U$1223 ( + .A1(b_registered[21]), + .A2(\sel_0$1661 ), + .B1(b_registered[22]), + .B2(\sel_1$1662 ), + .Y(\t$2303 ) + ); + XOR2x1_ASAP7_75t_R \U$1224 ( + .A(\t$2303 ), + .B(a_registered[19]), + .Y(booth_b18_m22) + ); + AO22x1_ASAP7_75t_R \U$1225 ( + .A1(b_registered[22]), + .A2(\sel_0$1661 ), + .B1(b_registered[23]), + .B2(\sel_1$1662 ), + .Y(\t$2304 ) + ); + XOR2x1_ASAP7_75t_R \U$1226 ( + .A(\t$2304 ), + .B(a_registered[19]), + .Y(booth_b18_m23) + ); + AO22x1_ASAP7_75t_R \U$1227 ( + .A1(b_registered[23]), + .A2(\sel_0$1661 ), + .B1(b_registered[24]), + .B2(\sel_1$1662 ), + .Y(\t$2305 ) + ); + XOR2x1_ASAP7_75t_R \U$1228 ( + .A(\t$2305 ), + .B(a_registered[19]), + .Y(booth_b18_m24) + ); + AO22x1_ASAP7_75t_R \U$1229 ( + .A1(b_registered[24]), + .A2(\sel_0$1661 ), + .B1(b_registered[25]), + .B2(\sel_1$1662 ), + .Y(\t$2306 ) + ); + XOR2x1_ASAP7_75t_R \U$1230 ( + .A(\t$2306 ), + .B(a_registered[19]), + .Y(booth_b18_m25) + ); + AO22x1_ASAP7_75t_R \U$1231 ( + .A1(b_registered[25]), + .A2(\sel_0$1661 ), + .B1(b_registered[26]), + .B2(\sel_1$1662 ), + .Y(\t$2307 ) + ); + XOR2x1_ASAP7_75t_R \U$1232 ( + .A(\t$2307 ), + .B(a_registered[19]), + .Y(booth_b18_m26) + ); + AO22x1_ASAP7_75t_R \U$1233 ( + .A1(b_registered[26]), + .A2(\sel_0$1661 ), + .B1(b_registered[27]), + .B2(\sel_1$1662 ), + .Y(\t$2308 ) + ); + XOR2x1_ASAP7_75t_R \U$1234 ( + .A(\t$2308 ), + .B(a_registered[19]), + .Y(booth_b18_m27) + ); + AO22x1_ASAP7_75t_R \U$1235 ( + .A1(b_registered[27]), + .A2(\sel_0$1661 ), + .B1(b_registered[28]), + .B2(\sel_1$1662 ), + .Y(\t$2309 ) + ); + XOR2x1_ASAP7_75t_R \U$1236 ( + .A(\t$2309 ), + .B(a_registered[19]), + .Y(booth_b18_m28) + ); + AO22x1_ASAP7_75t_R \U$1237 ( + .A1(b_registered[28]), + .A2(\sel_0$1661 ), + .B1(b_registered[29]), + .B2(\sel_1$1662 ), + .Y(\t$2310 ) + ); + XOR2x1_ASAP7_75t_R \U$1238 ( + .A(\t$2310 ), + .B(a_registered[19]), + .Y(booth_b18_m29) + ); + AO22x1_ASAP7_75t_R \U$1239 ( + .A1(b_registered[29]), + .A2(\sel_0$1661 ), + .B1(b_registered[30]), + .B2(\sel_1$1662 ), + .Y(\t$2311 ) + ); + XOR2x1_ASAP7_75t_R \U$1240 ( + .A(\t$2311 ), + .B(a_registered[19]), + .Y(booth_b18_m30) + ); + AO22x1_ASAP7_75t_R \U$1241 ( + .A1(b_registered[30]), + .A2(\sel_0$1661 ), + .B1(b_registered[31]), + .B2(\sel_1$1662 ), + .Y(\t$2312 ) + ); + XOR2x1_ASAP7_75t_R \U$1242 ( + .A(\t$2312 ), + .B(a_registered[19]), + .Y(booth_b18_m31) + ); + AO22x1_ASAP7_75t_R \U$1243 ( + .A1(b_registered[31]), + .A2(\sel_0$1661 ), + .B1(1'h0), + .B2(\sel_1$1662 ), + .Y(\t$2313 ) + ); + XOR2x1_ASAP7_75t_R \U$1244 ( + .A(\t$2313 ), + .B(a_registered[19]), + .Y(booth_b18_m32) + ); + INVx1_ASAP7_75t_R \U$1245 ( + .A(a_registered[19]), + .Y(\notsign$1070 ) + ); + INVx1_ASAP7_75t_R \U$1246 ( + .A(a_registered[19]), + .Y(\$31 ) + ); + INVx1_ASAP7_75t_R \U$1247 ( + .A(a_registered[20]), + .Y(\$32 ) + ); + INVx1_ASAP7_75t_R \U$1248 ( + .A(a_registered[21]), + .Y(\$33 ) + ); + AO33x2_ASAP7_75t_R \U$1249 ( + .A1(\$33 ), + .A2(a_registered[20]), + .A3(a_registered[19]), + .B1(a_registered[21]), + .B2(\$32 ), + .B3(\$31 ), + .Y(\sel_0$1698 ) + ); + XOR2x1_ASAP7_75t_R \U$1250 ( + .A(a_registered[20]), + .B(a_registered[19]), + .Y(\sel_1$1699 ) + ); + AO22x1_ASAP7_75t_R \U$1251 ( + .A1(1'h0), + .A2(\sel_0$1698 ), + .B1(b_registered[0]), + .B2(\sel_1$1699 ), + .Y(\t$2315 ) + ); + XOR2x1_ASAP7_75t_R \U$1252 ( + .A(\t$2315 ), + .B(a_registered[21]), + .Y(booth_b20_m0) + ); + AO22x1_ASAP7_75t_R \U$1253 ( + .A1(b_registered[0]), + .A2(\sel_0$1698 ), + .B1(b_registered[1]), + .B2(\sel_1$1699 ), + .Y(\t$2316 ) + ); + XOR2x1_ASAP7_75t_R \U$1254 ( + .A(\t$2316 ), + .B(a_registered[21]), + .Y(booth_b20_m1) + ); + AO22x1_ASAP7_75t_R \U$1255 ( + .A1(b_registered[1]), + .A2(\sel_0$1698 ), + .B1(b_registered[2]), + .B2(\sel_1$1699 ), + .Y(\t$2317 ) + ); + XOR2x1_ASAP7_75t_R \U$1256 ( + .A(\t$2317 ), + .B(a_registered[21]), + .Y(booth_b20_m2) + ); + AO22x1_ASAP7_75t_R \U$1257 ( + .A1(b_registered[2]), + .A2(\sel_0$1698 ), + .B1(b_registered[3]), + .B2(\sel_1$1699 ), + .Y(\t$2318 ) + ); + XOR2x1_ASAP7_75t_R \U$1258 ( + .A(\t$2318 ), + .B(a_registered[21]), + .Y(booth_b20_m3) + ); + AO22x1_ASAP7_75t_R \U$1259 ( + .A1(b_registered[3]), + .A2(\sel_0$1698 ), + .B1(b_registered[4]), + .B2(\sel_1$1699 ), + .Y(\t$2319 ) + ); + XOR2x1_ASAP7_75t_R \U$1260 ( + .A(\t$2319 ), + .B(a_registered[21]), + .Y(booth_b20_m4) + ); + AO22x1_ASAP7_75t_R \U$1261 ( + .A1(b_registered[4]), + .A2(\sel_0$1698 ), + .B1(b_registered[5]), + .B2(\sel_1$1699 ), + .Y(\t$2320 ) + ); + XOR2x1_ASAP7_75t_R \U$1262 ( + .A(\t$2320 ), + .B(a_registered[21]), + .Y(booth_b20_m5) + ); + AO22x1_ASAP7_75t_R \U$1263 ( + .A1(b_registered[5]), + .A2(\sel_0$1698 ), + .B1(b_registered[6]), + .B2(\sel_1$1699 ), + .Y(\t$2321 ) + ); + XOR2x1_ASAP7_75t_R \U$1264 ( + .A(\t$2321 ), + .B(a_registered[21]), + .Y(booth_b20_m6) + ); + AO22x1_ASAP7_75t_R \U$1265 ( + .A1(b_registered[6]), + .A2(\sel_0$1698 ), + .B1(b_registered[7]), + .B2(\sel_1$1699 ), + .Y(\t$2322 ) + ); + XOR2x1_ASAP7_75t_R \U$1266 ( + .A(\t$2322 ), + .B(a_registered[21]), + .Y(booth_b20_m7) + ); + AO22x1_ASAP7_75t_R \U$1267 ( + .A1(b_registered[7]), + .A2(\sel_0$1698 ), + .B1(b_registered[8]), + .B2(\sel_1$1699 ), + .Y(\t$2323 ) + ); + XOR2x1_ASAP7_75t_R \U$1268 ( + .A(\t$2323 ), + .B(a_registered[21]), + .Y(booth_b20_m8) + ); + AO22x1_ASAP7_75t_R \U$1269 ( + .A1(b_registered[8]), + .A2(\sel_0$1698 ), + .B1(b_registered[9]), + .B2(\sel_1$1699 ), + .Y(\t$2324 ) + ); + XOR2x1_ASAP7_75t_R \U$1270 ( + .A(\t$2324 ), + .B(a_registered[21]), + .Y(booth_b20_m9) + ); + AO22x1_ASAP7_75t_R \U$1271 ( + .A1(b_registered[9]), + .A2(\sel_0$1698 ), + .B1(b_registered[10]), + .B2(\sel_1$1699 ), + .Y(\t$2325 ) + ); + XOR2x1_ASAP7_75t_R \U$1272 ( + .A(\t$2325 ), + .B(a_registered[21]), + .Y(booth_b20_m10) + ); + AO22x1_ASAP7_75t_R \U$1273 ( + .A1(b_registered[10]), + .A2(\sel_0$1698 ), + .B1(b_registered[11]), + .B2(\sel_1$1699 ), + .Y(\t$2326 ) + ); + XOR2x1_ASAP7_75t_R \U$1274 ( + .A(\t$2326 ), + .B(a_registered[21]), + .Y(booth_b20_m11) + ); + AO22x1_ASAP7_75t_R \U$1275 ( + .A1(b_registered[11]), + .A2(\sel_0$1698 ), + .B1(b_registered[12]), + .B2(\sel_1$1699 ), + .Y(\t$2327 ) + ); + XOR2x1_ASAP7_75t_R \U$1276 ( + .A(\t$2327 ), + .B(a_registered[21]), + .Y(booth_b20_m12) + ); + AO22x1_ASAP7_75t_R \U$1277 ( + .A1(b_registered[12]), + .A2(\sel_0$1698 ), + .B1(b_registered[13]), + .B2(\sel_1$1699 ), + .Y(\t$2328 ) + ); + XOR2x1_ASAP7_75t_R \U$1278 ( + .A(\t$2328 ), + .B(a_registered[21]), + .Y(booth_b20_m13) + ); + AO22x1_ASAP7_75t_R \U$1279 ( + .A1(b_registered[13]), + .A2(\sel_0$1698 ), + .B1(b_registered[14]), + .B2(\sel_1$1699 ), + .Y(\t$2329 ) + ); + XOR2x1_ASAP7_75t_R \U$1280 ( + .A(\t$2329 ), + .B(a_registered[21]), + .Y(booth_b20_m14) + ); + AO22x1_ASAP7_75t_R \U$1281 ( + .A1(b_registered[14]), + .A2(\sel_0$1698 ), + .B1(b_registered[15]), + .B2(\sel_1$1699 ), + .Y(\t$2330 ) + ); + XOR2x1_ASAP7_75t_R \U$1282 ( + .A(\t$2330 ), + .B(a_registered[21]), + .Y(booth_b20_m15) + ); + AO22x1_ASAP7_75t_R \U$1283 ( + .A1(b_registered[15]), + .A2(\sel_0$1698 ), + .B1(b_registered[16]), + .B2(\sel_1$1699 ), + .Y(\t$2331 ) + ); + XOR2x1_ASAP7_75t_R \U$1284 ( + .A(\t$2331 ), + .B(a_registered[21]), + .Y(booth_b20_m16) + ); + AO22x1_ASAP7_75t_R \U$1285 ( + .A1(b_registered[16]), + .A2(\sel_0$1698 ), + .B1(b_registered[17]), + .B2(\sel_1$1699 ), + .Y(\t$2332 ) + ); + XOR2x1_ASAP7_75t_R \U$1286 ( + .A(\t$2332 ), + .B(a_registered[21]), + .Y(booth_b20_m17) + ); + AO22x1_ASAP7_75t_R \U$1287 ( + .A1(b_registered[17]), + .A2(\sel_0$1698 ), + .B1(b_registered[18]), + .B2(\sel_1$1699 ), + .Y(\t$2333 ) + ); + XOR2x1_ASAP7_75t_R \U$1288 ( + .A(\t$2333 ), + .B(a_registered[21]), + .Y(booth_b20_m18) + ); + AO22x1_ASAP7_75t_R \U$1289 ( + .A1(b_registered[18]), + .A2(\sel_0$1698 ), + .B1(b_registered[19]), + .B2(\sel_1$1699 ), + .Y(\t$2334 ) + ); + XOR2x1_ASAP7_75t_R \U$1290 ( + .A(\t$2334 ), + .B(a_registered[21]), + .Y(booth_b20_m19) + ); + AO22x1_ASAP7_75t_R \U$1291 ( + .A1(b_registered[19]), + .A2(\sel_0$1698 ), + .B1(b_registered[20]), + .B2(\sel_1$1699 ), + .Y(\t$2335 ) + ); + XOR2x1_ASAP7_75t_R \U$1292 ( + .A(\t$2335 ), + .B(a_registered[21]), + .Y(booth_b20_m20) + ); + AO22x1_ASAP7_75t_R \U$1293 ( + .A1(b_registered[20]), + .A2(\sel_0$1698 ), + .B1(b_registered[21]), + .B2(\sel_1$1699 ), + .Y(\t$2336 ) + ); + XOR2x1_ASAP7_75t_R \U$1294 ( + .A(\t$2336 ), + .B(a_registered[21]), + .Y(booth_b20_m21) + ); + AO22x1_ASAP7_75t_R \U$1295 ( + .A1(b_registered[21]), + .A2(\sel_0$1698 ), + .B1(b_registered[22]), + .B2(\sel_1$1699 ), + .Y(\t$2337 ) + ); + XOR2x1_ASAP7_75t_R \U$1296 ( + .A(\t$2337 ), + .B(a_registered[21]), + .Y(booth_b20_m22) + ); + AO22x1_ASAP7_75t_R \U$1297 ( + .A1(b_registered[22]), + .A2(\sel_0$1698 ), + .B1(b_registered[23]), + .B2(\sel_1$1699 ), + .Y(\t$2338 ) + ); + XOR2x1_ASAP7_75t_R \U$1298 ( + .A(\t$2338 ), + .B(a_registered[21]), + .Y(booth_b20_m23) + ); + AO22x1_ASAP7_75t_R \U$1299 ( + .A1(b_registered[23]), + .A2(\sel_0$1698 ), + .B1(b_registered[24]), + .B2(\sel_1$1699 ), + .Y(\t$2339 ) + ); + XOR2x1_ASAP7_75t_R \U$1300 ( + .A(\t$2339 ), + .B(a_registered[21]), + .Y(booth_b20_m24) + ); + AO22x1_ASAP7_75t_R \U$1301 ( + .A1(b_registered[24]), + .A2(\sel_0$1698 ), + .B1(b_registered[25]), + .B2(\sel_1$1699 ), + .Y(\t$2340 ) + ); + XOR2x1_ASAP7_75t_R \U$1302 ( + .A(\t$2340 ), + .B(a_registered[21]), + .Y(booth_b20_m25) + ); + AO22x1_ASAP7_75t_R \U$1303 ( + .A1(b_registered[25]), + .A2(\sel_0$1698 ), + .B1(b_registered[26]), + .B2(\sel_1$1699 ), + .Y(\t$2341 ) + ); + XOR2x1_ASAP7_75t_R \U$1304 ( + .A(\t$2341 ), + .B(a_registered[21]), + .Y(booth_b20_m26) + ); + AO22x1_ASAP7_75t_R \U$1305 ( + .A1(b_registered[26]), + .A2(\sel_0$1698 ), + .B1(b_registered[27]), + .B2(\sel_1$1699 ), + .Y(\t$2342 ) + ); + XOR2x1_ASAP7_75t_R \U$1306 ( + .A(\t$2342 ), + .B(a_registered[21]), + .Y(booth_b20_m27) + ); + AO22x1_ASAP7_75t_R \U$1307 ( + .A1(b_registered[27]), + .A2(\sel_0$1698 ), + .B1(b_registered[28]), + .B2(\sel_1$1699 ), + .Y(\t$2343 ) + ); + XOR2x1_ASAP7_75t_R \U$1308 ( + .A(\t$2343 ), + .B(a_registered[21]), + .Y(booth_b20_m28) + ); + AO22x1_ASAP7_75t_R \U$1309 ( + .A1(b_registered[28]), + .A2(\sel_0$1698 ), + .B1(b_registered[29]), + .B2(\sel_1$1699 ), + .Y(\t$2344 ) + ); + XOR2x1_ASAP7_75t_R \U$1310 ( + .A(\t$2344 ), + .B(a_registered[21]), + .Y(booth_b20_m29) + ); + AO22x1_ASAP7_75t_R \U$1311 ( + .A1(b_registered[29]), + .A2(\sel_0$1698 ), + .B1(b_registered[30]), + .B2(\sel_1$1699 ), + .Y(\t$2345 ) + ); + XOR2x1_ASAP7_75t_R \U$1312 ( + .A(\t$2345 ), + .B(a_registered[21]), + .Y(booth_b20_m30) + ); + AO22x1_ASAP7_75t_R \U$1313 ( + .A1(b_registered[30]), + .A2(\sel_0$1698 ), + .B1(b_registered[31]), + .B2(\sel_1$1699 ), + .Y(\t$2346 ) + ); + XOR2x1_ASAP7_75t_R \U$1314 ( + .A(\t$2346 ), + .B(a_registered[21]), + .Y(booth_b20_m31) + ); + AO22x1_ASAP7_75t_R \U$1315 ( + .A1(b_registered[31]), + .A2(\sel_0$1698 ), + .B1(1'h0), + .B2(\sel_1$1699 ), + .Y(\t$2347 ) + ); + XOR2x1_ASAP7_75t_R \U$1316 ( + .A(\t$2347 ), + .B(a_registered[21]), + .Y(booth_b20_m32) + ); + INVx1_ASAP7_75t_R \U$1317 ( + .A(a_registered[21]), + .Y(\notsign$1100 ) + ); + INVx1_ASAP7_75t_R \U$1318 ( + .A(a_registered[21]), + .Y(\$34 ) + ); + INVx1_ASAP7_75t_R \U$1319 ( + .A(a_registered[22]), + .Y(\$35 ) + ); + INVx1_ASAP7_75t_R \U$1320 ( + .A(a_registered[23]), + .Y(\$36 ) + ); + AO33x2_ASAP7_75t_R \U$1321 ( + .A1(\$36 ), + .A2(a_registered[22]), + .A3(a_registered[21]), + .B1(a_registered[23]), + .B2(\$35 ), + .B3(\$34 ), + .Y(\sel_0$1735 ) + ); + XOR2x1_ASAP7_75t_R \U$1322 ( + .A(a_registered[22]), + .B(a_registered[21]), + .Y(\sel_1$1736 ) + ); + AO22x1_ASAP7_75t_R \U$1323 ( + .A1(1'h0), + .A2(\sel_0$1735 ), + .B1(b_registered[0]), + .B2(\sel_1$1736 ), + .Y(\t$2349 ) + ); + XOR2x1_ASAP7_75t_R \U$1324 ( + .A(\t$2349 ), + .B(a_registered[23]), + .Y(booth_b22_m0) + ); + AO22x1_ASAP7_75t_R \U$1325 ( + .A1(b_registered[0]), + .A2(\sel_0$1735 ), + .B1(b_registered[1]), + .B2(\sel_1$1736 ), + .Y(\t$2350 ) + ); + XOR2x1_ASAP7_75t_R \U$1326 ( + .A(\t$2350 ), + .B(a_registered[23]), + .Y(booth_b22_m1) + ); + AO22x1_ASAP7_75t_R \U$1327 ( + .A1(b_registered[1]), + .A2(\sel_0$1735 ), + .B1(b_registered[2]), + .B2(\sel_1$1736 ), + .Y(\t$2351 ) + ); + XOR2x1_ASAP7_75t_R \U$1328 ( + .A(\t$2351 ), + .B(a_registered[23]), + .Y(booth_b22_m2) + ); + AO22x1_ASAP7_75t_R \U$1329 ( + .A1(b_registered[2]), + .A2(\sel_0$1735 ), + .B1(b_registered[3]), + .B2(\sel_1$1736 ), + .Y(\t$2352 ) + ); + XOR2x1_ASAP7_75t_R \U$1330 ( + .A(\t$2352 ), + .B(a_registered[23]), + .Y(booth_b22_m3) + ); + AO22x1_ASAP7_75t_R \U$1331 ( + .A1(b_registered[3]), + .A2(\sel_0$1735 ), + .B1(b_registered[4]), + .B2(\sel_1$1736 ), + .Y(\t$2353 ) + ); + XOR2x1_ASAP7_75t_R \U$1332 ( + .A(\t$2353 ), + .B(a_registered[23]), + .Y(booth_b22_m4) + ); + AO22x1_ASAP7_75t_R \U$1333 ( + .A1(b_registered[4]), + .A2(\sel_0$1735 ), + .B1(b_registered[5]), + .B2(\sel_1$1736 ), + .Y(\t$2354 ) + ); + XOR2x1_ASAP7_75t_R \U$1334 ( + .A(\t$2354 ), + .B(a_registered[23]), + .Y(booth_b22_m5) + ); + AO22x1_ASAP7_75t_R \U$1335 ( + .A1(b_registered[5]), + .A2(\sel_0$1735 ), + .B1(b_registered[6]), + .B2(\sel_1$1736 ), + .Y(\t$2355 ) + ); + XOR2x1_ASAP7_75t_R \U$1336 ( + .A(\t$2355 ), + .B(a_registered[23]), + .Y(booth_b22_m6) + ); + AO22x1_ASAP7_75t_R \U$1337 ( + .A1(b_registered[6]), + .A2(\sel_0$1735 ), + .B1(b_registered[7]), + .B2(\sel_1$1736 ), + .Y(\t$2356 ) + ); + XOR2x1_ASAP7_75t_R \U$1338 ( + .A(\t$2356 ), + .B(a_registered[23]), + .Y(booth_b22_m7) + ); + AO22x1_ASAP7_75t_R \U$1339 ( + .A1(b_registered[7]), + .A2(\sel_0$1735 ), + .B1(b_registered[8]), + .B2(\sel_1$1736 ), + .Y(\t$2357 ) + ); + XOR2x1_ASAP7_75t_R \U$1340 ( + .A(\t$2357 ), + .B(a_registered[23]), + .Y(booth_b22_m8) + ); + AO22x1_ASAP7_75t_R \U$1341 ( + .A1(b_registered[8]), + .A2(\sel_0$1735 ), + .B1(b_registered[9]), + .B2(\sel_1$1736 ), + .Y(\t$2358 ) + ); + XOR2x1_ASAP7_75t_R \U$1342 ( + .A(\t$2358 ), + .B(a_registered[23]), + .Y(booth_b22_m9) + ); + AO22x1_ASAP7_75t_R \U$1343 ( + .A1(b_registered[9]), + .A2(\sel_0$1735 ), + .B1(b_registered[10]), + .B2(\sel_1$1736 ), + .Y(\t$2359 ) + ); + XOR2x1_ASAP7_75t_R \U$1344 ( + .A(\t$2359 ), + .B(a_registered[23]), + .Y(booth_b22_m10) + ); + AO22x1_ASAP7_75t_R \U$1345 ( + .A1(b_registered[10]), + .A2(\sel_0$1735 ), + .B1(b_registered[11]), + .B2(\sel_1$1736 ), + .Y(\t$2360 ) + ); + XOR2x1_ASAP7_75t_R \U$1346 ( + .A(\t$2360 ), + .B(a_registered[23]), + .Y(booth_b22_m11) + ); + AO22x1_ASAP7_75t_R \U$1347 ( + .A1(b_registered[11]), + .A2(\sel_0$1735 ), + .B1(b_registered[12]), + .B2(\sel_1$1736 ), + .Y(\t$2361 ) + ); + XOR2x1_ASAP7_75t_R \U$1348 ( + .A(\t$2361 ), + .B(a_registered[23]), + .Y(booth_b22_m12) + ); + AO22x1_ASAP7_75t_R \U$1349 ( + .A1(b_registered[12]), + .A2(\sel_0$1735 ), + .B1(b_registered[13]), + .B2(\sel_1$1736 ), + .Y(\t$2362 ) + ); + XOR2x1_ASAP7_75t_R \U$1350 ( + .A(\t$2362 ), + .B(a_registered[23]), + .Y(booth_b22_m13) + ); + AO22x1_ASAP7_75t_R \U$1351 ( + .A1(b_registered[13]), + .A2(\sel_0$1735 ), + .B1(b_registered[14]), + .B2(\sel_1$1736 ), + .Y(\t$2363 ) + ); + XOR2x1_ASAP7_75t_R \U$1352 ( + .A(\t$2363 ), + .B(a_registered[23]), + .Y(booth_b22_m14) + ); + AO22x1_ASAP7_75t_R \U$1353 ( + .A1(b_registered[14]), + .A2(\sel_0$1735 ), + .B1(b_registered[15]), + .B2(\sel_1$1736 ), + .Y(\t$2364 ) + ); + XOR2x1_ASAP7_75t_R \U$1354 ( + .A(\t$2364 ), + .B(a_registered[23]), + .Y(booth_b22_m15) + ); + AO22x1_ASAP7_75t_R \U$1355 ( + .A1(b_registered[15]), + .A2(\sel_0$1735 ), + .B1(b_registered[16]), + .B2(\sel_1$1736 ), + .Y(\t$2365 ) + ); + XOR2x1_ASAP7_75t_R \U$1356 ( + .A(\t$2365 ), + .B(a_registered[23]), + .Y(booth_b22_m16) + ); + AO22x1_ASAP7_75t_R \U$1357 ( + .A1(b_registered[16]), + .A2(\sel_0$1735 ), + .B1(b_registered[17]), + .B2(\sel_1$1736 ), + .Y(\t$2366 ) + ); + XOR2x1_ASAP7_75t_R \U$1358 ( + .A(\t$2366 ), + .B(a_registered[23]), + .Y(booth_b22_m17) + ); + AO22x1_ASAP7_75t_R \U$1359 ( + .A1(b_registered[17]), + .A2(\sel_0$1735 ), + .B1(b_registered[18]), + .B2(\sel_1$1736 ), + .Y(\t$2367 ) + ); + XOR2x1_ASAP7_75t_R \U$1360 ( + .A(\t$2367 ), + .B(a_registered[23]), + .Y(booth_b22_m18) + ); + AO22x1_ASAP7_75t_R \U$1361 ( + .A1(b_registered[18]), + .A2(\sel_0$1735 ), + .B1(b_registered[19]), + .B2(\sel_1$1736 ), + .Y(\t$2368 ) + ); + XOR2x1_ASAP7_75t_R \U$1362 ( + .A(\t$2368 ), + .B(a_registered[23]), + .Y(booth_b22_m19) + ); + AO22x1_ASAP7_75t_R \U$1363 ( + .A1(b_registered[19]), + .A2(\sel_0$1735 ), + .B1(b_registered[20]), + .B2(\sel_1$1736 ), + .Y(\t$2369 ) + ); + XOR2x1_ASAP7_75t_R \U$1364 ( + .A(\t$2369 ), + .B(a_registered[23]), + .Y(booth_b22_m20) + ); + AO22x1_ASAP7_75t_R \U$1365 ( + .A1(b_registered[20]), + .A2(\sel_0$1735 ), + .B1(b_registered[21]), + .B2(\sel_1$1736 ), + .Y(\t$2370 ) + ); + XOR2x1_ASAP7_75t_R \U$1366 ( + .A(\t$2370 ), + .B(a_registered[23]), + .Y(booth_b22_m21) + ); + AO22x1_ASAP7_75t_R \U$1367 ( + .A1(b_registered[21]), + .A2(\sel_0$1735 ), + .B1(b_registered[22]), + .B2(\sel_1$1736 ), + .Y(\t$2371 ) + ); + XOR2x1_ASAP7_75t_R \U$1368 ( + .A(\t$2371 ), + .B(a_registered[23]), + .Y(booth_b22_m22) + ); + AO22x1_ASAP7_75t_R \U$1369 ( + .A1(b_registered[22]), + .A2(\sel_0$1735 ), + .B1(b_registered[23]), + .B2(\sel_1$1736 ), + .Y(\t$2372 ) + ); + XOR2x1_ASAP7_75t_R \U$1370 ( + .A(\t$2372 ), + .B(a_registered[23]), + .Y(booth_b22_m23) + ); + AO22x1_ASAP7_75t_R \U$1371 ( + .A1(b_registered[23]), + .A2(\sel_0$1735 ), + .B1(b_registered[24]), + .B2(\sel_1$1736 ), + .Y(\t$2373 ) + ); + XOR2x1_ASAP7_75t_R \U$1372 ( + .A(\t$2373 ), + .B(a_registered[23]), + .Y(booth_b22_m24) + ); + AO22x1_ASAP7_75t_R \U$1373 ( + .A1(b_registered[24]), + .A2(\sel_0$1735 ), + .B1(b_registered[25]), + .B2(\sel_1$1736 ), + .Y(\t$2374 ) + ); + XOR2x1_ASAP7_75t_R \U$1374 ( + .A(\t$2374 ), + .B(a_registered[23]), + .Y(booth_b22_m25) + ); + AO22x1_ASAP7_75t_R \U$1375 ( + .A1(b_registered[25]), + .A2(\sel_0$1735 ), + .B1(b_registered[26]), + .B2(\sel_1$1736 ), + .Y(\t$2375 ) + ); + XOR2x1_ASAP7_75t_R \U$1376 ( + .A(\t$2375 ), + .B(a_registered[23]), + .Y(booth_b22_m26) + ); + AO22x1_ASAP7_75t_R \U$1377 ( + .A1(b_registered[26]), + .A2(\sel_0$1735 ), + .B1(b_registered[27]), + .B2(\sel_1$1736 ), + .Y(\t$2376 ) + ); + XOR2x1_ASAP7_75t_R \U$1378 ( + .A(\t$2376 ), + .B(a_registered[23]), + .Y(booth_b22_m27) + ); + AO22x1_ASAP7_75t_R \U$1379 ( + .A1(b_registered[27]), + .A2(\sel_0$1735 ), + .B1(b_registered[28]), + .B2(\sel_1$1736 ), + .Y(\t$2377 ) + ); + XOR2x1_ASAP7_75t_R \U$1380 ( + .A(\t$2377 ), + .B(a_registered[23]), + .Y(booth_b22_m28) + ); + AO22x1_ASAP7_75t_R \U$1381 ( + .A1(b_registered[28]), + .A2(\sel_0$1735 ), + .B1(b_registered[29]), + .B2(\sel_1$1736 ), + .Y(\t$2378 ) + ); + XOR2x1_ASAP7_75t_R \U$1382 ( + .A(\t$2378 ), + .B(a_registered[23]), + .Y(booth_b22_m29) + ); + AO22x1_ASAP7_75t_R \U$1383 ( + .A1(b_registered[29]), + .A2(\sel_0$1735 ), + .B1(b_registered[30]), + .B2(\sel_1$1736 ), + .Y(\t$2379 ) + ); + XOR2x1_ASAP7_75t_R \U$1384 ( + .A(\t$2379 ), + .B(a_registered[23]), + .Y(booth_b22_m30) + ); + AO22x1_ASAP7_75t_R \U$1385 ( + .A1(b_registered[30]), + .A2(\sel_0$1735 ), + .B1(b_registered[31]), + .B2(\sel_1$1736 ), + .Y(\t$2380 ) + ); + XOR2x1_ASAP7_75t_R \U$1386 ( + .A(\t$2380 ), + .B(a_registered[23]), + .Y(booth_b22_m31) + ); + AO22x1_ASAP7_75t_R \U$1387 ( + .A1(b_registered[31]), + .A2(\sel_0$1735 ), + .B1(1'h0), + .B2(\sel_1$1736 ), + .Y(\t$2381 ) + ); + XOR2x1_ASAP7_75t_R \U$1388 ( + .A(\t$2381 ), + .B(a_registered[23]), + .Y(booth_b22_m32) + ); + INVx1_ASAP7_75t_R \U$1389 ( + .A(a_registered[23]), + .Y(\notsign$1126 ) + ); + INVx1_ASAP7_75t_R \U$1390 ( + .A(a_registered[23]), + .Y(\$37 ) + ); + INVx1_ASAP7_75t_R \U$1391 ( + .A(a_registered[24]), + .Y(\$38 ) + ); + INVx1_ASAP7_75t_R \U$1392 ( + .A(a_registered[25]), + .Y(\$39 ) + ); + AO33x2_ASAP7_75t_R \U$1393 ( + .A1(\$39 ), + .A2(a_registered[24]), + .A3(a_registered[23]), + .B1(a_registered[25]), + .B2(\$38 ), + .B3(\$37 ), + .Y(\sel_0$1772 ) + ); + XOR2x1_ASAP7_75t_R \U$1394 ( + .A(a_registered[24]), + .B(a_registered[23]), + .Y(\sel_1$1773 ) + ); + AO22x1_ASAP7_75t_R \U$1395 ( + .A1(1'h0), + .A2(\sel_0$1772 ), + .B1(b_registered[0]), + .B2(\sel_1$1773 ), + .Y(\t$2383 ) + ); + XOR2x1_ASAP7_75t_R \U$1396 ( + .A(\t$2383 ), + .B(a_registered[25]), + .Y(booth_b24_m0) + ); + AO22x1_ASAP7_75t_R \U$1397 ( + .A1(b_registered[0]), + .A2(\sel_0$1772 ), + .B1(b_registered[1]), + .B2(\sel_1$1773 ), + .Y(\t$2384 ) + ); + XOR2x1_ASAP7_75t_R \U$1398 ( + .A(\t$2384 ), + .B(a_registered[25]), + .Y(booth_b24_m1) + ); + AO22x1_ASAP7_75t_R \U$1399 ( + .A1(b_registered[1]), + .A2(\sel_0$1772 ), + .B1(b_registered[2]), + .B2(\sel_1$1773 ), + .Y(\t$2385 ) + ); + XOR2x1_ASAP7_75t_R \U$1400 ( + .A(\t$2385 ), + .B(a_registered[25]), + .Y(booth_b24_m2) + ); + AO22x1_ASAP7_75t_R \U$1401 ( + .A1(b_registered[2]), + .A2(\sel_0$1772 ), + .B1(b_registered[3]), + .B2(\sel_1$1773 ), + .Y(\t$2386 ) + ); + XOR2x1_ASAP7_75t_R \U$1402 ( + .A(\t$2386 ), + .B(a_registered[25]), + .Y(booth_b24_m3) + ); + AO22x1_ASAP7_75t_R \U$1403 ( + .A1(b_registered[3]), + .A2(\sel_0$1772 ), + .B1(b_registered[4]), + .B2(\sel_1$1773 ), + .Y(\t$2387 ) + ); + XOR2x1_ASAP7_75t_R \U$1404 ( + .A(\t$2387 ), + .B(a_registered[25]), + .Y(booth_b24_m4) + ); + AO22x1_ASAP7_75t_R \U$1405 ( + .A1(b_registered[4]), + .A2(\sel_0$1772 ), + .B1(b_registered[5]), + .B2(\sel_1$1773 ), + .Y(\t$2388 ) + ); + XOR2x1_ASAP7_75t_R \U$1406 ( + .A(\t$2388 ), + .B(a_registered[25]), + .Y(booth_b24_m5) + ); + AO22x1_ASAP7_75t_R \U$1407 ( + .A1(b_registered[5]), + .A2(\sel_0$1772 ), + .B1(b_registered[6]), + .B2(\sel_1$1773 ), + .Y(\t$2389 ) + ); + XOR2x1_ASAP7_75t_R \U$1408 ( + .A(\t$2389 ), + .B(a_registered[25]), + .Y(booth_b24_m6) + ); + AO22x1_ASAP7_75t_R \U$1409 ( + .A1(b_registered[6]), + .A2(\sel_0$1772 ), + .B1(b_registered[7]), + .B2(\sel_1$1773 ), + .Y(\t$2390 ) + ); + XOR2x1_ASAP7_75t_R \U$1410 ( + .A(\t$2390 ), + .B(a_registered[25]), + .Y(booth_b24_m7) + ); + AO22x1_ASAP7_75t_R \U$1411 ( + .A1(b_registered[7]), + .A2(\sel_0$1772 ), + .B1(b_registered[8]), + .B2(\sel_1$1773 ), + .Y(\t$2391 ) + ); + XOR2x1_ASAP7_75t_R \U$1412 ( + .A(\t$2391 ), + .B(a_registered[25]), + .Y(booth_b24_m8) + ); + AO22x1_ASAP7_75t_R \U$1413 ( + .A1(b_registered[8]), + .A2(\sel_0$1772 ), + .B1(b_registered[9]), + .B2(\sel_1$1773 ), + .Y(\t$2392 ) + ); + XOR2x1_ASAP7_75t_R \U$1414 ( + .A(\t$2392 ), + .B(a_registered[25]), + .Y(booth_b24_m9) + ); + AO22x1_ASAP7_75t_R \U$1415 ( + .A1(b_registered[9]), + .A2(\sel_0$1772 ), + .B1(b_registered[10]), + .B2(\sel_1$1773 ), + .Y(\t$2393 ) + ); + XOR2x1_ASAP7_75t_R \U$1416 ( + .A(\t$2393 ), + .B(a_registered[25]), + .Y(booth_b24_m10) + ); + AO22x1_ASAP7_75t_R \U$1417 ( + .A1(b_registered[10]), + .A2(\sel_0$1772 ), + .B1(b_registered[11]), + .B2(\sel_1$1773 ), + .Y(\t$2394 ) + ); + XOR2x1_ASAP7_75t_R \U$1418 ( + .A(\t$2394 ), + .B(a_registered[25]), + .Y(booth_b24_m11) + ); + AO22x1_ASAP7_75t_R \U$1419 ( + .A1(b_registered[11]), + .A2(\sel_0$1772 ), + .B1(b_registered[12]), + .B2(\sel_1$1773 ), + .Y(\t$2395 ) + ); + XOR2x1_ASAP7_75t_R \U$1420 ( + .A(\t$2395 ), + .B(a_registered[25]), + .Y(booth_b24_m12) + ); + AO22x1_ASAP7_75t_R \U$1421 ( + .A1(b_registered[12]), + .A2(\sel_0$1772 ), + .B1(b_registered[13]), + .B2(\sel_1$1773 ), + .Y(\t$2396 ) + ); + XOR2x1_ASAP7_75t_R \U$1422 ( + .A(\t$2396 ), + .B(a_registered[25]), + .Y(booth_b24_m13) + ); + AO22x1_ASAP7_75t_R \U$1423 ( + .A1(b_registered[13]), + .A2(\sel_0$1772 ), + .B1(b_registered[14]), + .B2(\sel_1$1773 ), + .Y(\t$2397 ) + ); + XOR2x1_ASAP7_75t_R \U$1424 ( + .A(\t$2397 ), + .B(a_registered[25]), + .Y(booth_b24_m14) + ); + AO22x1_ASAP7_75t_R \U$1425 ( + .A1(b_registered[14]), + .A2(\sel_0$1772 ), + .B1(b_registered[15]), + .B2(\sel_1$1773 ), + .Y(\t$2398 ) + ); + XOR2x1_ASAP7_75t_R \U$1426 ( + .A(\t$2398 ), + .B(a_registered[25]), + .Y(booth_b24_m15) + ); + AO22x1_ASAP7_75t_R \U$1427 ( + .A1(b_registered[15]), + .A2(\sel_0$1772 ), + .B1(b_registered[16]), + .B2(\sel_1$1773 ), + .Y(\t$2399 ) + ); + XOR2x1_ASAP7_75t_R \U$1428 ( + .A(\t$2399 ), + .B(a_registered[25]), + .Y(booth_b24_m16) + ); + AO22x1_ASAP7_75t_R \U$1429 ( + .A1(b_registered[16]), + .A2(\sel_0$1772 ), + .B1(b_registered[17]), + .B2(\sel_1$1773 ), + .Y(\t$2400 ) + ); + XOR2x1_ASAP7_75t_R \U$1430 ( + .A(\t$2400 ), + .B(a_registered[25]), + .Y(booth_b24_m17) + ); + AO22x1_ASAP7_75t_R \U$1431 ( + .A1(b_registered[17]), + .A2(\sel_0$1772 ), + .B1(b_registered[18]), + .B2(\sel_1$1773 ), + .Y(\t$2401 ) + ); + XOR2x1_ASAP7_75t_R \U$1432 ( + .A(\t$2401 ), + .B(a_registered[25]), + .Y(booth_b24_m18) + ); + AO22x1_ASAP7_75t_R \U$1433 ( + .A1(b_registered[18]), + .A2(\sel_0$1772 ), + .B1(b_registered[19]), + .B2(\sel_1$1773 ), + .Y(\t$2402 ) + ); + XOR2x1_ASAP7_75t_R \U$1434 ( + .A(\t$2402 ), + .B(a_registered[25]), + .Y(booth_b24_m19) + ); + AO22x1_ASAP7_75t_R \U$1435 ( + .A1(b_registered[19]), + .A2(\sel_0$1772 ), + .B1(b_registered[20]), + .B2(\sel_1$1773 ), + .Y(\t$2403 ) + ); + XOR2x1_ASAP7_75t_R \U$1436 ( + .A(\t$2403 ), + .B(a_registered[25]), + .Y(booth_b24_m20) + ); + AO22x1_ASAP7_75t_R \U$1437 ( + .A1(b_registered[20]), + .A2(\sel_0$1772 ), + .B1(b_registered[21]), + .B2(\sel_1$1773 ), + .Y(\t$2404 ) + ); + XOR2x1_ASAP7_75t_R \U$1438 ( + .A(\t$2404 ), + .B(a_registered[25]), + .Y(booth_b24_m21) + ); + AO22x1_ASAP7_75t_R \U$1439 ( + .A1(b_registered[21]), + .A2(\sel_0$1772 ), + .B1(b_registered[22]), + .B2(\sel_1$1773 ), + .Y(\t$2405 ) + ); + XOR2x1_ASAP7_75t_R \U$1440 ( + .A(\t$2405 ), + .B(a_registered[25]), + .Y(booth_b24_m22) + ); + AO22x1_ASAP7_75t_R \U$1441 ( + .A1(b_registered[22]), + .A2(\sel_0$1772 ), + .B1(b_registered[23]), + .B2(\sel_1$1773 ), + .Y(\t$2406 ) + ); + XOR2x1_ASAP7_75t_R \U$1442 ( + .A(\t$2406 ), + .B(a_registered[25]), + .Y(booth_b24_m23) + ); + AO22x1_ASAP7_75t_R \U$1443 ( + .A1(b_registered[23]), + .A2(\sel_0$1772 ), + .B1(b_registered[24]), + .B2(\sel_1$1773 ), + .Y(\t$2407 ) + ); + XOR2x1_ASAP7_75t_R \U$1444 ( + .A(\t$2407 ), + .B(a_registered[25]), + .Y(booth_b24_m24) + ); + AO22x1_ASAP7_75t_R \U$1445 ( + .A1(b_registered[24]), + .A2(\sel_0$1772 ), + .B1(b_registered[25]), + .B2(\sel_1$1773 ), + .Y(\t$2408 ) + ); + XOR2x1_ASAP7_75t_R \U$1446 ( + .A(\t$2408 ), + .B(a_registered[25]), + .Y(booth_b24_m25) + ); + AO22x1_ASAP7_75t_R \U$1447 ( + .A1(b_registered[25]), + .A2(\sel_0$1772 ), + .B1(b_registered[26]), + .B2(\sel_1$1773 ), + .Y(\t$2409 ) + ); + XOR2x1_ASAP7_75t_R \U$1448 ( + .A(\t$2409 ), + .B(a_registered[25]), + .Y(booth_b24_m26) + ); + AO22x1_ASAP7_75t_R \U$1449 ( + .A1(b_registered[26]), + .A2(\sel_0$1772 ), + .B1(b_registered[27]), + .B2(\sel_1$1773 ), + .Y(\t$2410 ) + ); + XOR2x1_ASAP7_75t_R \U$1450 ( + .A(\t$2410 ), + .B(a_registered[25]), + .Y(booth_b24_m27) + ); + AO22x1_ASAP7_75t_R \U$1451 ( + .A1(b_registered[27]), + .A2(\sel_0$1772 ), + .B1(b_registered[28]), + .B2(\sel_1$1773 ), + .Y(\t$2411 ) + ); + XOR2x1_ASAP7_75t_R \U$1452 ( + .A(\t$2411 ), + .B(a_registered[25]), + .Y(booth_b24_m28) + ); + AO22x1_ASAP7_75t_R \U$1453 ( + .A1(b_registered[28]), + .A2(\sel_0$1772 ), + .B1(b_registered[29]), + .B2(\sel_1$1773 ), + .Y(\t$2412 ) + ); + XOR2x1_ASAP7_75t_R \U$1454 ( + .A(\t$2412 ), + .B(a_registered[25]), + .Y(booth_b24_m29) + ); + AO22x1_ASAP7_75t_R \U$1455 ( + .A1(b_registered[29]), + .A2(\sel_0$1772 ), + .B1(b_registered[30]), + .B2(\sel_1$1773 ), + .Y(\t$2413 ) + ); + XOR2x1_ASAP7_75t_R \U$1456 ( + .A(\t$2413 ), + .B(a_registered[25]), + .Y(booth_b24_m30) + ); + AO22x1_ASAP7_75t_R \U$1457 ( + .A1(b_registered[30]), + .A2(\sel_0$1772 ), + .B1(b_registered[31]), + .B2(\sel_1$1773 ), + .Y(\t$2414 ) + ); + XOR2x1_ASAP7_75t_R \U$1458 ( + .A(\t$2414 ), + .B(a_registered[25]), + .Y(booth_b24_m31) + ); + AO22x1_ASAP7_75t_R \U$1459 ( + .A1(b_registered[31]), + .A2(\sel_0$1772 ), + .B1(1'h0), + .B2(\sel_1$1773 ), + .Y(\t$2415 ) + ); + XOR2x1_ASAP7_75t_R \U$1460 ( + .A(\t$2415 ), + .B(a_registered[25]), + .Y(booth_b24_m32) + ); + INVx1_ASAP7_75t_R \U$1461 ( + .A(a_registered[25]), + .Y(\notsign$1148 ) + ); + INVx1_ASAP7_75t_R \U$1462 ( + .A(a_registered[25]), + .Y(\$40 ) + ); + INVx1_ASAP7_75t_R \U$1463 ( + .A(a_registered[26]), + .Y(\$41 ) + ); + INVx1_ASAP7_75t_R \U$1464 ( + .A(a_registered[27]), + .Y(\$42 ) + ); + AO33x2_ASAP7_75t_R \U$1465 ( + .A1(\$42 ), + .A2(a_registered[26]), + .A3(a_registered[25]), + .B1(a_registered[27]), + .B2(\$41 ), + .B3(\$40 ), + .Y(\sel_0$1809 ) + ); + XOR2x1_ASAP7_75t_R \U$1466 ( + .A(a_registered[26]), + .B(a_registered[25]), + .Y(\sel_1$1810 ) + ); + AO22x1_ASAP7_75t_R \U$1467 ( + .A1(1'h0), + .A2(\sel_0$1809 ), + .B1(b_registered[0]), + .B2(\sel_1$1810 ), + .Y(\t$2417 ) + ); + XOR2x1_ASAP7_75t_R \U$1468 ( + .A(\t$2417 ), + .B(a_registered[27]), + .Y(booth_b26_m0) + ); + AO22x1_ASAP7_75t_R \U$1469 ( + .A1(b_registered[0]), + .A2(\sel_0$1809 ), + .B1(b_registered[1]), + .B2(\sel_1$1810 ), + .Y(\t$2418 ) + ); + XOR2x1_ASAP7_75t_R \U$1470 ( + .A(\t$2418 ), + .B(a_registered[27]), + .Y(booth_b26_m1) + ); + AO22x1_ASAP7_75t_R \U$1471 ( + .A1(b_registered[1]), + .A2(\sel_0$1809 ), + .B1(b_registered[2]), + .B2(\sel_1$1810 ), + .Y(\t$2419 ) + ); + XOR2x1_ASAP7_75t_R \U$1472 ( + .A(\t$2419 ), + .B(a_registered[27]), + .Y(booth_b26_m2) + ); + AO22x1_ASAP7_75t_R \U$1473 ( + .A1(b_registered[2]), + .A2(\sel_0$1809 ), + .B1(b_registered[3]), + .B2(\sel_1$1810 ), + .Y(\t$2420 ) + ); + XOR2x1_ASAP7_75t_R \U$1474 ( + .A(\t$2420 ), + .B(a_registered[27]), + .Y(booth_b26_m3) + ); + AO22x1_ASAP7_75t_R \U$1475 ( + .A1(b_registered[3]), + .A2(\sel_0$1809 ), + .B1(b_registered[4]), + .B2(\sel_1$1810 ), + .Y(\t$2421 ) + ); + XOR2x1_ASAP7_75t_R \U$1476 ( + .A(\t$2421 ), + .B(a_registered[27]), + .Y(booth_b26_m4) + ); + AO22x1_ASAP7_75t_R \U$1477 ( + .A1(b_registered[4]), + .A2(\sel_0$1809 ), + .B1(b_registered[5]), + .B2(\sel_1$1810 ), + .Y(\t$2422 ) + ); + XOR2x1_ASAP7_75t_R \U$1478 ( + .A(\t$2422 ), + .B(a_registered[27]), + .Y(booth_b26_m5) + ); + AO22x1_ASAP7_75t_R \U$1479 ( + .A1(b_registered[5]), + .A2(\sel_0$1809 ), + .B1(b_registered[6]), + .B2(\sel_1$1810 ), + .Y(\t$2423 ) + ); + XOR2x1_ASAP7_75t_R \U$1480 ( + .A(\t$2423 ), + .B(a_registered[27]), + .Y(booth_b26_m6) + ); + AO22x1_ASAP7_75t_R \U$1481 ( + .A1(b_registered[6]), + .A2(\sel_0$1809 ), + .B1(b_registered[7]), + .B2(\sel_1$1810 ), + .Y(\t$2424 ) + ); + XOR2x1_ASAP7_75t_R \U$1482 ( + .A(\t$2424 ), + .B(a_registered[27]), + .Y(booth_b26_m7) + ); + AO22x1_ASAP7_75t_R \U$1483 ( + .A1(b_registered[7]), + .A2(\sel_0$1809 ), + .B1(b_registered[8]), + .B2(\sel_1$1810 ), + .Y(\t$2425 ) + ); + XOR2x1_ASAP7_75t_R \U$1484 ( + .A(\t$2425 ), + .B(a_registered[27]), + .Y(booth_b26_m8) + ); + AO22x1_ASAP7_75t_R \U$1485 ( + .A1(b_registered[8]), + .A2(\sel_0$1809 ), + .B1(b_registered[9]), + .B2(\sel_1$1810 ), + .Y(\t$2426 ) + ); + XOR2x1_ASAP7_75t_R \U$1486 ( + .A(\t$2426 ), + .B(a_registered[27]), + .Y(booth_b26_m9) + ); + AO22x1_ASAP7_75t_R \U$1487 ( + .A1(b_registered[9]), + .A2(\sel_0$1809 ), + .B1(b_registered[10]), + .B2(\sel_1$1810 ), + .Y(\t$2427 ) + ); + XOR2x1_ASAP7_75t_R \U$1488 ( + .A(\t$2427 ), + .B(a_registered[27]), + .Y(booth_b26_m10) + ); + AO22x1_ASAP7_75t_R \U$1489 ( + .A1(b_registered[10]), + .A2(\sel_0$1809 ), + .B1(b_registered[11]), + .B2(\sel_1$1810 ), + .Y(\t$2428 ) + ); + XOR2x1_ASAP7_75t_R \U$1490 ( + .A(\t$2428 ), + .B(a_registered[27]), + .Y(booth_b26_m11) + ); + AO22x1_ASAP7_75t_R \U$1491 ( + .A1(b_registered[11]), + .A2(\sel_0$1809 ), + .B1(b_registered[12]), + .B2(\sel_1$1810 ), + .Y(\t$2429 ) + ); + XOR2x1_ASAP7_75t_R \U$1492 ( + .A(\t$2429 ), + .B(a_registered[27]), + .Y(booth_b26_m12) + ); + AO22x1_ASAP7_75t_R \U$1493 ( + .A1(b_registered[12]), + .A2(\sel_0$1809 ), + .B1(b_registered[13]), + .B2(\sel_1$1810 ), + .Y(\t$2430 ) + ); + XOR2x1_ASAP7_75t_R \U$1494 ( + .A(\t$2430 ), + .B(a_registered[27]), + .Y(booth_b26_m13) + ); + AO22x1_ASAP7_75t_R \U$1495 ( + .A1(b_registered[13]), + .A2(\sel_0$1809 ), + .B1(b_registered[14]), + .B2(\sel_1$1810 ), + .Y(\t$2431 ) + ); + XOR2x1_ASAP7_75t_R \U$1496 ( + .A(\t$2431 ), + .B(a_registered[27]), + .Y(booth_b26_m14) + ); + AO22x1_ASAP7_75t_R \U$1497 ( + .A1(b_registered[14]), + .A2(\sel_0$1809 ), + .B1(b_registered[15]), + .B2(\sel_1$1810 ), + .Y(\t$2432 ) + ); + XOR2x1_ASAP7_75t_R \U$1498 ( + .A(\t$2432 ), + .B(a_registered[27]), + .Y(booth_b26_m15) + ); + AO22x1_ASAP7_75t_R \U$1499 ( + .A1(b_registered[15]), + .A2(\sel_0$1809 ), + .B1(b_registered[16]), + .B2(\sel_1$1810 ), + .Y(\t$2433 ) + ); + XOR2x1_ASAP7_75t_R \U$1500 ( + .A(\t$2433 ), + .B(a_registered[27]), + .Y(booth_b26_m16) + ); + AO22x1_ASAP7_75t_R \U$1501 ( + .A1(b_registered[16]), + .A2(\sel_0$1809 ), + .B1(b_registered[17]), + .B2(\sel_1$1810 ), + .Y(\t$2434 ) + ); + XOR2x1_ASAP7_75t_R \U$1502 ( + .A(\t$2434 ), + .B(a_registered[27]), + .Y(booth_b26_m17) + ); + AO22x1_ASAP7_75t_R \U$1503 ( + .A1(b_registered[17]), + .A2(\sel_0$1809 ), + .B1(b_registered[18]), + .B2(\sel_1$1810 ), + .Y(\t$2435 ) + ); + XOR2x1_ASAP7_75t_R \U$1504 ( + .A(\t$2435 ), + .B(a_registered[27]), + .Y(booth_b26_m18) + ); + AO22x1_ASAP7_75t_R \U$1505 ( + .A1(b_registered[18]), + .A2(\sel_0$1809 ), + .B1(b_registered[19]), + .B2(\sel_1$1810 ), + .Y(\t$2436 ) + ); + XOR2x1_ASAP7_75t_R \U$1506 ( + .A(\t$2436 ), + .B(a_registered[27]), + .Y(booth_b26_m19) + ); + AO22x1_ASAP7_75t_R \U$1507 ( + .A1(b_registered[19]), + .A2(\sel_0$1809 ), + .B1(b_registered[20]), + .B2(\sel_1$1810 ), + .Y(\t$2437 ) + ); + XOR2x1_ASAP7_75t_R \U$1508 ( + .A(\t$2437 ), + .B(a_registered[27]), + .Y(booth_b26_m20) + ); + AO22x1_ASAP7_75t_R \U$1509 ( + .A1(b_registered[20]), + .A2(\sel_0$1809 ), + .B1(b_registered[21]), + .B2(\sel_1$1810 ), + .Y(\t$2438 ) + ); + XOR2x1_ASAP7_75t_R \U$1510 ( + .A(\t$2438 ), + .B(a_registered[27]), + .Y(booth_b26_m21) + ); + AO22x1_ASAP7_75t_R \U$1511 ( + .A1(b_registered[21]), + .A2(\sel_0$1809 ), + .B1(b_registered[22]), + .B2(\sel_1$1810 ), + .Y(\t$2439 ) + ); + XOR2x1_ASAP7_75t_R \U$1512 ( + .A(\t$2439 ), + .B(a_registered[27]), + .Y(booth_b26_m22) + ); + AO22x1_ASAP7_75t_R \U$1513 ( + .A1(b_registered[22]), + .A2(\sel_0$1809 ), + .B1(b_registered[23]), + .B2(\sel_1$1810 ), + .Y(\t$2440 ) + ); + XOR2x1_ASAP7_75t_R \U$1514 ( + .A(\t$2440 ), + .B(a_registered[27]), + .Y(booth_b26_m23) + ); + AO22x1_ASAP7_75t_R \U$1515 ( + .A1(b_registered[23]), + .A2(\sel_0$1809 ), + .B1(b_registered[24]), + .B2(\sel_1$1810 ), + .Y(\t$2441 ) + ); + XOR2x1_ASAP7_75t_R \U$1516 ( + .A(\t$2441 ), + .B(a_registered[27]), + .Y(booth_b26_m24) + ); + AO22x1_ASAP7_75t_R \U$1517 ( + .A1(b_registered[24]), + .A2(\sel_0$1809 ), + .B1(b_registered[25]), + .B2(\sel_1$1810 ), + .Y(\t$2442 ) + ); + XOR2x1_ASAP7_75t_R \U$1518 ( + .A(\t$2442 ), + .B(a_registered[27]), + .Y(booth_b26_m25) + ); + AO22x1_ASAP7_75t_R \U$1519 ( + .A1(b_registered[25]), + .A2(\sel_0$1809 ), + .B1(b_registered[26]), + .B2(\sel_1$1810 ), + .Y(\t$2443 ) + ); + XOR2x1_ASAP7_75t_R \U$1520 ( + .A(\t$2443 ), + .B(a_registered[27]), + .Y(booth_b26_m26) + ); + AO22x1_ASAP7_75t_R \U$1521 ( + .A1(b_registered[26]), + .A2(\sel_0$1809 ), + .B1(b_registered[27]), + .B2(\sel_1$1810 ), + .Y(\t$2444 ) + ); + XOR2x1_ASAP7_75t_R \U$1522 ( + .A(\t$2444 ), + .B(a_registered[27]), + .Y(booth_b26_m27) + ); + AO22x1_ASAP7_75t_R \U$1523 ( + .A1(b_registered[27]), + .A2(\sel_0$1809 ), + .B1(b_registered[28]), + .B2(\sel_1$1810 ), + .Y(\t$2445 ) + ); + XOR2x1_ASAP7_75t_R \U$1524 ( + .A(\t$2445 ), + .B(a_registered[27]), + .Y(booth_b26_m28) + ); + AO22x1_ASAP7_75t_R \U$1525 ( + .A1(b_registered[28]), + .A2(\sel_0$1809 ), + .B1(b_registered[29]), + .B2(\sel_1$1810 ), + .Y(\t$2446 ) + ); + XOR2x1_ASAP7_75t_R \U$1526 ( + .A(\t$2446 ), + .B(a_registered[27]), + .Y(booth_b26_m29) + ); + AO22x1_ASAP7_75t_R \U$1527 ( + .A1(b_registered[29]), + .A2(\sel_0$1809 ), + .B1(b_registered[30]), + .B2(\sel_1$1810 ), + .Y(\t$2447 ) + ); + XOR2x1_ASAP7_75t_R \U$1528 ( + .A(\t$2447 ), + .B(a_registered[27]), + .Y(booth_b26_m30) + ); + AO22x1_ASAP7_75t_R \U$1529 ( + .A1(b_registered[30]), + .A2(\sel_0$1809 ), + .B1(b_registered[31]), + .B2(\sel_1$1810 ), + .Y(\t$2448 ) + ); + XOR2x1_ASAP7_75t_R \U$1530 ( + .A(\t$2448 ), + .B(a_registered[27]), + .Y(booth_b26_m31) + ); + AO22x1_ASAP7_75t_R \U$1531 ( + .A1(b_registered[31]), + .A2(\sel_0$1809 ), + .B1(1'h0), + .B2(\sel_1$1810 ), + .Y(\t$2449 ) + ); + XOR2x1_ASAP7_75t_R \U$1532 ( + .A(\t$2449 ), + .B(a_registered[27]), + .Y(booth_b26_m32) + ); + INVx1_ASAP7_75t_R \U$1533 ( + .A(a_registered[27]), + .Y(\notsign$1166 ) + ); + INVx1_ASAP7_75t_R \U$1534 ( + .A(a_registered[27]), + .Y(\$43 ) + ); + INVx1_ASAP7_75t_R \U$1535 ( + .A(a_registered[28]), + .Y(\$44 ) + ); + INVx1_ASAP7_75t_R \U$1536 ( + .A(a_registered[29]), + .Y(\$45 ) + ); + AO33x2_ASAP7_75t_R \U$1537 ( + .A1(\$45 ), + .A2(a_registered[28]), + .A3(a_registered[27]), + .B1(a_registered[29]), + .B2(\$44 ), + .B3(\$43 ), + .Y(\sel_0$1846 ) + ); + XOR2x1_ASAP7_75t_R \U$1538 ( + .A(a_registered[28]), + .B(a_registered[27]), + .Y(\sel_1$1847 ) + ); + AO22x1_ASAP7_75t_R \U$1539 ( + .A1(1'h0), + .A2(\sel_0$1846 ), + .B1(b_registered[0]), + .B2(\sel_1$1847 ), + .Y(\t$2451 ) + ); + XOR2x1_ASAP7_75t_R \U$1540 ( + .A(\t$2451 ), + .B(a_registered[29]), + .Y(booth_b28_m0) + ); + AO22x1_ASAP7_75t_R \U$1541 ( + .A1(b_registered[0]), + .A2(\sel_0$1846 ), + .B1(b_registered[1]), + .B2(\sel_1$1847 ), + .Y(\t$2452 ) + ); + XOR2x1_ASAP7_75t_R \U$1542 ( + .A(\t$2452 ), + .B(a_registered[29]), + .Y(booth_b28_m1) + ); + AO22x1_ASAP7_75t_R \U$1543 ( + .A1(b_registered[1]), + .A2(\sel_0$1846 ), + .B1(b_registered[2]), + .B2(\sel_1$1847 ), + .Y(\t$2453 ) + ); + XOR2x1_ASAP7_75t_R \U$1544 ( + .A(\t$2453 ), + .B(a_registered[29]), + .Y(booth_b28_m2) + ); + AO22x1_ASAP7_75t_R \U$1545 ( + .A1(b_registered[2]), + .A2(\sel_0$1846 ), + .B1(b_registered[3]), + .B2(\sel_1$1847 ), + .Y(\t$2454 ) + ); + XOR2x1_ASAP7_75t_R \U$1546 ( + .A(\t$2454 ), + .B(a_registered[29]), + .Y(booth_b28_m3) + ); + AO22x1_ASAP7_75t_R \U$1547 ( + .A1(b_registered[3]), + .A2(\sel_0$1846 ), + .B1(b_registered[4]), + .B2(\sel_1$1847 ), + .Y(\t$2455 ) + ); + XOR2x1_ASAP7_75t_R \U$1548 ( + .A(\t$2455 ), + .B(a_registered[29]), + .Y(booth_b28_m4) + ); + AO22x1_ASAP7_75t_R \U$1549 ( + .A1(b_registered[4]), + .A2(\sel_0$1846 ), + .B1(b_registered[5]), + .B2(\sel_1$1847 ), + .Y(\t$2456 ) + ); + XOR2x1_ASAP7_75t_R \U$1550 ( + .A(\t$2456 ), + .B(a_registered[29]), + .Y(booth_b28_m5) + ); + AO22x1_ASAP7_75t_R \U$1551 ( + .A1(b_registered[5]), + .A2(\sel_0$1846 ), + .B1(b_registered[6]), + .B2(\sel_1$1847 ), + .Y(\t$2457 ) + ); + XOR2x1_ASAP7_75t_R \U$1552 ( + .A(\t$2457 ), + .B(a_registered[29]), + .Y(booth_b28_m6) + ); + AO22x1_ASAP7_75t_R \U$1553 ( + .A1(b_registered[6]), + .A2(\sel_0$1846 ), + .B1(b_registered[7]), + .B2(\sel_1$1847 ), + .Y(\t$2458 ) + ); + XOR2x1_ASAP7_75t_R \U$1554 ( + .A(\t$2458 ), + .B(a_registered[29]), + .Y(booth_b28_m7) + ); + AO22x1_ASAP7_75t_R \U$1555 ( + .A1(b_registered[7]), + .A2(\sel_0$1846 ), + .B1(b_registered[8]), + .B2(\sel_1$1847 ), + .Y(\t$2459 ) + ); + XOR2x1_ASAP7_75t_R \U$1556 ( + .A(\t$2459 ), + .B(a_registered[29]), + .Y(booth_b28_m8) + ); + AO22x1_ASAP7_75t_R \U$1557 ( + .A1(b_registered[8]), + .A2(\sel_0$1846 ), + .B1(b_registered[9]), + .B2(\sel_1$1847 ), + .Y(\t$2460 ) + ); + XOR2x1_ASAP7_75t_R \U$1558 ( + .A(\t$2460 ), + .B(a_registered[29]), + .Y(booth_b28_m9) + ); + AO22x1_ASAP7_75t_R \U$1559 ( + .A1(b_registered[9]), + .A2(\sel_0$1846 ), + .B1(b_registered[10]), + .B2(\sel_1$1847 ), + .Y(\t$2461 ) + ); + XOR2x1_ASAP7_75t_R \U$1560 ( + .A(\t$2461 ), + .B(a_registered[29]), + .Y(booth_b28_m10) + ); + AO22x1_ASAP7_75t_R \U$1561 ( + .A1(b_registered[10]), + .A2(\sel_0$1846 ), + .B1(b_registered[11]), + .B2(\sel_1$1847 ), + .Y(\t$2462 ) + ); + XOR2x1_ASAP7_75t_R \U$1562 ( + .A(\t$2462 ), + .B(a_registered[29]), + .Y(booth_b28_m11) + ); + AO22x1_ASAP7_75t_R \U$1563 ( + .A1(b_registered[11]), + .A2(\sel_0$1846 ), + .B1(b_registered[12]), + .B2(\sel_1$1847 ), + .Y(\t$2463 ) + ); + XOR2x1_ASAP7_75t_R \U$1564 ( + .A(\t$2463 ), + .B(a_registered[29]), + .Y(booth_b28_m12) + ); + AO22x1_ASAP7_75t_R \U$1565 ( + .A1(b_registered[12]), + .A2(\sel_0$1846 ), + .B1(b_registered[13]), + .B2(\sel_1$1847 ), + .Y(\t$2464 ) + ); + XOR2x1_ASAP7_75t_R \U$1566 ( + .A(\t$2464 ), + .B(a_registered[29]), + .Y(booth_b28_m13) + ); + AO22x1_ASAP7_75t_R \U$1567 ( + .A1(b_registered[13]), + .A2(\sel_0$1846 ), + .B1(b_registered[14]), + .B2(\sel_1$1847 ), + .Y(\t$2465 ) + ); + XOR2x1_ASAP7_75t_R \U$1568 ( + .A(\t$2465 ), + .B(a_registered[29]), + .Y(booth_b28_m14) + ); + AO22x1_ASAP7_75t_R \U$1569 ( + .A1(b_registered[14]), + .A2(\sel_0$1846 ), + .B1(b_registered[15]), + .B2(\sel_1$1847 ), + .Y(\t$2466 ) + ); + XOR2x1_ASAP7_75t_R \U$1570 ( + .A(\t$2466 ), + .B(a_registered[29]), + .Y(booth_b28_m15) + ); + AO22x1_ASAP7_75t_R \U$1571 ( + .A1(b_registered[15]), + .A2(\sel_0$1846 ), + .B1(b_registered[16]), + .B2(\sel_1$1847 ), + .Y(\t$2467 ) + ); + XOR2x1_ASAP7_75t_R \U$1572 ( + .A(\t$2467 ), + .B(a_registered[29]), + .Y(booth_b28_m16) + ); + AO22x1_ASAP7_75t_R \U$1573 ( + .A1(b_registered[16]), + .A2(\sel_0$1846 ), + .B1(b_registered[17]), + .B2(\sel_1$1847 ), + .Y(\t$2468 ) + ); + XOR2x1_ASAP7_75t_R \U$1574 ( + .A(\t$2468 ), + .B(a_registered[29]), + .Y(booth_b28_m17) + ); + AO22x1_ASAP7_75t_R \U$1575 ( + .A1(b_registered[17]), + .A2(\sel_0$1846 ), + .B1(b_registered[18]), + .B2(\sel_1$1847 ), + .Y(\t$2469 ) + ); + XOR2x1_ASAP7_75t_R \U$1576 ( + .A(\t$2469 ), + .B(a_registered[29]), + .Y(booth_b28_m18) + ); + AO22x1_ASAP7_75t_R \U$1577 ( + .A1(b_registered[18]), + .A2(\sel_0$1846 ), + .B1(b_registered[19]), + .B2(\sel_1$1847 ), + .Y(\t$2470 ) + ); + XOR2x1_ASAP7_75t_R \U$1578 ( + .A(\t$2470 ), + .B(a_registered[29]), + .Y(booth_b28_m19) + ); + AO22x1_ASAP7_75t_R \U$1579 ( + .A1(b_registered[19]), + .A2(\sel_0$1846 ), + .B1(b_registered[20]), + .B2(\sel_1$1847 ), + .Y(\t$2471 ) + ); + XOR2x1_ASAP7_75t_R \U$1580 ( + .A(\t$2471 ), + .B(a_registered[29]), + .Y(booth_b28_m20) + ); + AO22x1_ASAP7_75t_R \U$1581 ( + .A1(b_registered[20]), + .A2(\sel_0$1846 ), + .B1(b_registered[21]), + .B2(\sel_1$1847 ), + .Y(\t$2472 ) + ); + XOR2x1_ASAP7_75t_R \U$1582 ( + .A(\t$2472 ), + .B(a_registered[29]), + .Y(booth_b28_m21) + ); + AO22x1_ASAP7_75t_R \U$1583 ( + .A1(b_registered[21]), + .A2(\sel_0$1846 ), + .B1(b_registered[22]), + .B2(\sel_1$1847 ), + .Y(\t$2473 ) + ); + XOR2x1_ASAP7_75t_R \U$1584 ( + .A(\t$2473 ), + .B(a_registered[29]), + .Y(booth_b28_m22) + ); + AO22x1_ASAP7_75t_R \U$1585 ( + .A1(b_registered[22]), + .A2(\sel_0$1846 ), + .B1(b_registered[23]), + .B2(\sel_1$1847 ), + .Y(\t$2474 ) + ); + XOR2x1_ASAP7_75t_R \U$1586 ( + .A(\t$2474 ), + .B(a_registered[29]), + .Y(booth_b28_m23) + ); + AO22x1_ASAP7_75t_R \U$1587 ( + .A1(b_registered[23]), + .A2(\sel_0$1846 ), + .B1(b_registered[24]), + .B2(\sel_1$1847 ), + .Y(\t$2475 ) + ); + XOR2x1_ASAP7_75t_R \U$1588 ( + .A(\t$2475 ), + .B(a_registered[29]), + .Y(booth_b28_m24) + ); + AO22x1_ASAP7_75t_R \U$1589 ( + .A1(b_registered[24]), + .A2(\sel_0$1846 ), + .B1(b_registered[25]), + .B2(\sel_1$1847 ), + .Y(\t$2476 ) + ); + XOR2x1_ASAP7_75t_R \U$1590 ( + .A(\t$2476 ), + .B(a_registered[29]), + .Y(booth_b28_m25) + ); + AO22x1_ASAP7_75t_R \U$1591 ( + .A1(b_registered[25]), + .A2(\sel_0$1846 ), + .B1(b_registered[26]), + .B2(\sel_1$1847 ), + .Y(\t$2477 ) + ); + XOR2x1_ASAP7_75t_R \U$1592 ( + .A(\t$2477 ), + .B(a_registered[29]), + .Y(booth_b28_m26) + ); + AO22x1_ASAP7_75t_R \U$1593 ( + .A1(b_registered[26]), + .A2(\sel_0$1846 ), + .B1(b_registered[27]), + .B2(\sel_1$1847 ), + .Y(\t$2478 ) + ); + XOR2x1_ASAP7_75t_R \U$1594 ( + .A(\t$2478 ), + .B(a_registered[29]), + .Y(booth_b28_m27) + ); + AO22x1_ASAP7_75t_R \U$1595 ( + .A1(b_registered[27]), + .A2(\sel_0$1846 ), + .B1(b_registered[28]), + .B2(\sel_1$1847 ), + .Y(\t$2479 ) + ); + XOR2x1_ASAP7_75t_R \U$1596 ( + .A(\t$2479 ), + .B(a_registered[29]), + .Y(booth_b28_m28) + ); + AO22x1_ASAP7_75t_R \U$1597 ( + .A1(b_registered[28]), + .A2(\sel_0$1846 ), + .B1(b_registered[29]), + .B2(\sel_1$1847 ), + .Y(\t$2480 ) + ); + XOR2x1_ASAP7_75t_R \U$1598 ( + .A(\t$2480 ), + .B(a_registered[29]), + .Y(booth_b28_m29) + ); + AO22x1_ASAP7_75t_R \U$1599 ( + .A1(b_registered[29]), + .A2(\sel_0$1846 ), + .B1(b_registered[30]), + .B2(\sel_1$1847 ), + .Y(\t$2481 ) + ); + XOR2x1_ASAP7_75t_R \U$1600 ( + .A(\t$2481 ), + .B(a_registered[29]), + .Y(booth_b28_m30) + ); + AO22x1_ASAP7_75t_R \U$1601 ( + .A1(b_registered[30]), + .A2(\sel_0$1846 ), + .B1(b_registered[31]), + .B2(\sel_1$1847 ), + .Y(\t$2482 ) + ); + XOR2x1_ASAP7_75t_R \U$1602 ( + .A(\t$2482 ), + .B(a_registered[29]), + .Y(booth_b28_m31) + ); + AO22x1_ASAP7_75t_R \U$1603 ( + .A1(b_registered[31]), + .A2(\sel_0$1846 ), + .B1(1'h0), + .B2(\sel_1$1847 ), + .Y(\t$2483 ) + ); + XOR2x1_ASAP7_75t_R \U$1604 ( + .A(\t$2483 ), + .B(a_registered[29]), + .Y(booth_b28_m32) + ); + INVx1_ASAP7_75t_R \U$1605 ( + .A(a_registered[29]), + .Y(\notsign$1180 ) + ); + INVx1_ASAP7_75t_R \U$1606 ( + .A(a_registered[29]), + .Y(\$46 ) + ); + INVx1_ASAP7_75t_R \U$1607 ( + .A(a_registered[30]), + .Y(\$47 ) + ); + INVx1_ASAP7_75t_R \U$1608 ( + .A(a_registered[31]), + .Y(\$48 ) + ); + AO33x2_ASAP7_75t_R \U$1609 ( + .A1(\$48 ), + .A2(a_registered[30]), + .A3(a_registered[29]), + .B1(a_registered[31]), + .B2(\$47 ), + .B3(\$46 ), + .Y(\sel_0$1883 ) + ); + XOR2x1_ASAP7_75t_R \U$1610 ( + .A(a_registered[30]), + .B(a_registered[29]), + .Y(\sel_1$1884 ) + ); + AO22x1_ASAP7_75t_R \U$1611 ( + .A1(1'h0), + .A2(\sel_0$1883 ), + .B1(b_registered[0]), + .B2(\sel_1$1884 ), + .Y(\t$2485 ) + ); + XOR2x1_ASAP7_75t_R \U$1612 ( + .A(\t$2485 ), + .B(a_registered[31]), + .Y(booth_b30_m0) + ); + AO22x1_ASAP7_75t_R \U$1613 ( + .A1(b_registered[0]), + .A2(\sel_0$1883 ), + .B1(b_registered[1]), + .B2(\sel_1$1884 ), + .Y(\t$2486 ) + ); + XOR2x1_ASAP7_75t_R \U$1614 ( + .A(\t$2486 ), + .B(a_registered[31]), + .Y(booth_b30_m1) + ); + AO22x1_ASAP7_75t_R \U$1615 ( + .A1(b_registered[1]), + .A2(\sel_0$1883 ), + .B1(b_registered[2]), + .B2(\sel_1$1884 ), + .Y(\t$2487 ) + ); + XOR2x1_ASAP7_75t_R \U$1616 ( + .A(\t$2487 ), + .B(a_registered[31]), + .Y(booth_b30_m2) + ); + AO22x1_ASAP7_75t_R \U$1617 ( + .A1(b_registered[2]), + .A2(\sel_0$1883 ), + .B1(b_registered[3]), + .B2(\sel_1$1884 ), + .Y(\t$2488 ) + ); + XOR2x1_ASAP7_75t_R \U$1618 ( + .A(\t$2488 ), + .B(a_registered[31]), + .Y(booth_b30_m3) + ); + AO22x1_ASAP7_75t_R \U$1619 ( + .A1(b_registered[3]), + .A2(\sel_0$1883 ), + .B1(b_registered[4]), + .B2(\sel_1$1884 ), + .Y(\t$2489 ) + ); + XOR2x1_ASAP7_75t_R \U$1620 ( + .A(\t$2489 ), + .B(a_registered[31]), + .Y(booth_b30_m4) + ); + AO22x1_ASAP7_75t_R \U$1621 ( + .A1(b_registered[4]), + .A2(\sel_0$1883 ), + .B1(b_registered[5]), + .B2(\sel_1$1884 ), + .Y(\t$2490 ) + ); + XOR2x1_ASAP7_75t_R \U$1622 ( + .A(\t$2490 ), + .B(a_registered[31]), + .Y(booth_b30_m5) + ); + AO22x1_ASAP7_75t_R \U$1623 ( + .A1(b_registered[5]), + .A2(\sel_0$1883 ), + .B1(b_registered[6]), + .B2(\sel_1$1884 ), + .Y(\t$2491 ) + ); + XOR2x1_ASAP7_75t_R \U$1624 ( + .A(\t$2491 ), + .B(a_registered[31]), + .Y(booth_b30_m6) + ); + AO22x1_ASAP7_75t_R \U$1625 ( + .A1(b_registered[6]), + .A2(\sel_0$1883 ), + .B1(b_registered[7]), + .B2(\sel_1$1884 ), + .Y(\t$2492 ) + ); + XOR2x1_ASAP7_75t_R \U$1626 ( + .A(\t$2492 ), + .B(a_registered[31]), + .Y(booth_b30_m7) + ); + AO22x1_ASAP7_75t_R \U$1627 ( + .A1(b_registered[7]), + .A2(\sel_0$1883 ), + .B1(b_registered[8]), + .B2(\sel_1$1884 ), + .Y(\t$2493 ) + ); + XOR2x1_ASAP7_75t_R \U$1628 ( + .A(\t$2493 ), + .B(a_registered[31]), + .Y(booth_b30_m8) + ); + AO22x1_ASAP7_75t_R \U$1629 ( + .A1(b_registered[8]), + .A2(\sel_0$1883 ), + .B1(b_registered[9]), + .B2(\sel_1$1884 ), + .Y(\t$2494 ) + ); + XOR2x1_ASAP7_75t_R \U$1630 ( + .A(\t$2494 ), + .B(a_registered[31]), + .Y(booth_b30_m9) + ); + AO22x1_ASAP7_75t_R \U$1631 ( + .A1(b_registered[9]), + .A2(\sel_0$1883 ), + .B1(b_registered[10]), + .B2(\sel_1$1884 ), + .Y(\t$2495 ) + ); + XOR2x1_ASAP7_75t_R \U$1632 ( + .A(\t$2495 ), + .B(a_registered[31]), + .Y(booth_b30_m10) + ); + AO22x1_ASAP7_75t_R \U$1633 ( + .A1(b_registered[10]), + .A2(\sel_0$1883 ), + .B1(b_registered[11]), + .B2(\sel_1$1884 ), + .Y(\t$2496 ) + ); + XOR2x1_ASAP7_75t_R \U$1634 ( + .A(\t$2496 ), + .B(a_registered[31]), + .Y(booth_b30_m11) + ); + AO22x1_ASAP7_75t_R \U$1635 ( + .A1(b_registered[11]), + .A2(\sel_0$1883 ), + .B1(b_registered[12]), + .B2(\sel_1$1884 ), + .Y(\t$2497 ) + ); + XOR2x1_ASAP7_75t_R \U$1636 ( + .A(\t$2497 ), + .B(a_registered[31]), + .Y(booth_b30_m12) + ); + AO22x1_ASAP7_75t_R \U$1637 ( + .A1(b_registered[12]), + .A2(\sel_0$1883 ), + .B1(b_registered[13]), + .B2(\sel_1$1884 ), + .Y(\t$2498 ) + ); + XOR2x1_ASAP7_75t_R \U$1638 ( + .A(\t$2498 ), + .B(a_registered[31]), + .Y(booth_b30_m13) + ); + AO22x1_ASAP7_75t_R \U$1639 ( + .A1(b_registered[13]), + .A2(\sel_0$1883 ), + .B1(b_registered[14]), + .B2(\sel_1$1884 ), + .Y(\t$2499 ) + ); + XOR2x1_ASAP7_75t_R \U$1640 ( + .A(\t$2499 ), + .B(a_registered[31]), + .Y(booth_b30_m14) + ); + AO22x1_ASAP7_75t_R \U$1641 ( + .A1(b_registered[14]), + .A2(\sel_0$1883 ), + .B1(b_registered[15]), + .B2(\sel_1$1884 ), + .Y(\t$2500 ) + ); + XOR2x1_ASAP7_75t_R \U$1642 ( + .A(\t$2500 ), + .B(a_registered[31]), + .Y(booth_b30_m15) + ); + AO22x1_ASAP7_75t_R \U$1643 ( + .A1(b_registered[15]), + .A2(\sel_0$1883 ), + .B1(b_registered[16]), + .B2(\sel_1$1884 ), + .Y(\t$2501 ) + ); + XOR2x1_ASAP7_75t_R \U$1644 ( + .A(\t$2501 ), + .B(a_registered[31]), + .Y(booth_b30_m16) + ); + AO22x1_ASAP7_75t_R \U$1645 ( + .A1(b_registered[16]), + .A2(\sel_0$1883 ), + .B1(b_registered[17]), + .B2(\sel_1$1884 ), + .Y(\t$2502 ) + ); + XOR2x1_ASAP7_75t_R \U$1646 ( + .A(\t$2502 ), + .B(a_registered[31]), + .Y(booth_b30_m17) + ); + AO22x1_ASAP7_75t_R \U$1647 ( + .A1(b_registered[17]), + .A2(\sel_0$1883 ), + .B1(b_registered[18]), + .B2(\sel_1$1884 ), + .Y(\t$2503 ) + ); + XOR2x1_ASAP7_75t_R \U$1648 ( + .A(\t$2503 ), + .B(a_registered[31]), + .Y(booth_b30_m18) + ); + AO22x1_ASAP7_75t_R \U$1649 ( + .A1(b_registered[18]), + .A2(\sel_0$1883 ), + .B1(b_registered[19]), + .B2(\sel_1$1884 ), + .Y(\t$2504 ) + ); + XOR2x1_ASAP7_75t_R \U$1650 ( + .A(\t$2504 ), + .B(a_registered[31]), + .Y(booth_b30_m19) + ); + AO22x1_ASAP7_75t_R \U$1651 ( + .A1(b_registered[19]), + .A2(\sel_0$1883 ), + .B1(b_registered[20]), + .B2(\sel_1$1884 ), + .Y(\t$2505 ) + ); + XOR2x1_ASAP7_75t_R \U$1652 ( + .A(\t$2505 ), + .B(a_registered[31]), + .Y(booth_b30_m20) + ); + AO22x1_ASAP7_75t_R \U$1653 ( + .A1(b_registered[20]), + .A2(\sel_0$1883 ), + .B1(b_registered[21]), + .B2(\sel_1$1884 ), + .Y(\t$2506 ) + ); + XOR2x1_ASAP7_75t_R \U$1654 ( + .A(\t$2506 ), + .B(a_registered[31]), + .Y(booth_b30_m21) + ); + AO22x1_ASAP7_75t_R \U$1655 ( + .A1(b_registered[21]), + .A2(\sel_0$1883 ), + .B1(b_registered[22]), + .B2(\sel_1$1884 ), + .Y(\t$2507 ) + ); + XOR2x1_ASAP7_75t_R \U$1656 ( + .A(\t$2507 ), + .B(a_registered[31]), + .Y(booth_b30_m22) + ); + AO22x1_ASAP7_75t_R \U$1657 ( + .A1(b_registered[22]), + .A2(\sel_0$1883 ), + .B1(b_registered[23]), + .B2(\sel_1$1884 ), + .Y(\t$2508 ) + ); + XOR2x1_ASAP7_75t_R \U$1658 ( + .A(\t$2508 ), + .B(a_registered[31]), + .Y(booth_b30_m23) + ); + AO22x1_ASAP7_75t_R \U$1659 ( + .A1(b_registered[23]), + .A2(\sel_0$1883 ), + .B1(b_registered[24]), + .B2(\sel_1$1884 ), + .Y(\t$2509 ) + ); + XOR2x1_ASAP7_75t_R \U$1660 ( + .A(\t$2509 ), + .B(a_registered[31]), + .Y(booth_b30_m24) + ); + AO22x1_ASAP7_75t_R \U$1661 ( + .A1(b_registered[24]), + .A2(\sel_0$1883 ), + .B1(b_registered[25]), + .B2(\sel_1$1884 ), + .Y(\t$2510 ) + ); + XOR2x1_ASAP7_75t_R \U$1662 ( + .A(\t$2510 ), + .B(a_registered[31]), + .Y(booth_b30_m25) + ); + AO22x1_ASAP7_75t_R \U$1663 ( + .A1(b_registered[25]), + .A2(\sel_0$1883 ), + .B1(b_registered[26]), + .B2(\sel_1$1884 ), + .Y(\t$2511 ) + ); + XOR2x1_ASAP7_75t_R \U$1664 ( + .A(\t$2511 ), + .B(a_registered[31]), + .Y(booth_b30_m26) + ); + AO22x1_ASAP7_75t_R \U$1665 ( + .A1(b_registered[26]), + .A2(\sel_0$1883 ), + .B1(b_registered[27]), + .B2(\sel_1$1884 ), + .Y(\t$2512 ) + ); + XOR2x1_ASAP7_75t_R \U$1666 ( + .A(\t$2512 ), + .B(a_registered[31]), + .Y(booth_b30_m27) + ); + AO22x1_ASAP7_75t_R \U$1667 ( + .A1(b_registered[27]), + .A2(\sel_0$1883 ), + .B1(b_registered[28]), + .B2(\sel_1$1884 ), + .Y(\t$2513 ) + ); + XOR2x1_ASAP7_75t_R \U$1668 ( + .A(\t$2513 ), + .B(a_registered[31]), + .Y(booth_b30_m28) + ); + AO22x1_ASAP7_75t_R \U$1669 ( + .A1(b_registered[28]), + .A2(\sel_0$1883 ), + .B1(b_registered[29]), + .B2(\sel_1$1884 ), + .Y(\t$2514 ) + ); + XOR2x1_ASAP7_75t_R \U$1670 ( + .A(\t$2514 ), + .B(a_registered[31]), + .Y(booth_b30_m29) + ); + AO22x1_ASAP7_75t_R \U$1671 ( + .A1(b_registered[29]), + .A2(\sel_0$1883 ), + .B1(b_registered[30]), + .B2(\sel_1$1884 ), + .Y(\t$2515 ) + ); + XOR2x1_ASAP7_75t_R \U$1672 ( + .A(\t$2515 ), + .B(a_registered[31]), + .Y(booth_b30_m30) + ); + AO22x1_ASAP7_75t_R \U$1673 ( + .A1(b_registered[30]), + .A2(\sel_0$1883 ), + .B1(b_registered[31]), + .B2(\sel_1$1884 ), + .Y(\t$2516 ) + ); + XOR2x1_ASAP7_75t_R \U$1674 ( + .A(\t$2516 ), + .B(a_registered[31]), + .Y(booth_b30_m31) + ); + AO22x1_ASAP7_75t_R \U$1675 ( + .A1(b_registered[31]), + .A2(\sel_0$1883 ), + .B1(1'h0), + .B2(\sel_1$1884 ), + .Y(\t$2517 ) + ); + XOR2x1_ASAP7_75t_R \U$1676 ( + .A(\t$2517 ), + .B(a_registered[31]), + .Y(booth_b30_m32) + ); + INVx1_ASAP7_75t_R \U$1677 ( + .A(a_registered[31]), + .Y(\notsign$1190 ) + ); + INVx1_ASAP7_75t_R \U$1678 ( + .A(a_registered[31]), + .Y(\$49 ) + ); + INVx1_ASAP7_75t_R \U$1679 ( + .A(1'h0), + .Y(\$50 ) + ); + INVx1_ASAP7_75t_R \U$1680 ( + .A(1'h0), + .Y(\$51 ) + ); + AO33x2_ASAP7_75t_R \U$1681 ( + .A1(\$51 ), + .A2(1'h0), + .A3(a_registered[31]), + .B1(1'h0), + .B2(\$50 ), + .B3(\$49 ), + .Y(\sel_0$1921 ) + ); + XOR2x1_ASAP7_75t_R \U$1682 ( + .A(1'h0), + .B(a_registered[31]), + .Y(\sel_1$1922 ) + ); + AO22x1_ASAP7_75t_R \U$1683 ( + .A1(1'h0), + .A2(\sel_0$1921 ), + .B1(b_registered[0]), + .B2(\sel_1$1922 ), + .Y(\t$2519 ) + ); + XOR2x1_ASAP7_75t_R \U$1684 ( + .A(\t$2519 ), + .B(1'h0), + .Y(booth_b32_m0) + ); + AO22x1_ASAP7_75t_R \U$1685 ( + .A1(b_registered[0]), + .A2(\sel_0$1921 ), + .B1(b_registered[1]), + .B2(\sel_1$1922 ), + .Y(\t$2520 ) + ); + XOR2x1_ASAP7_75t_R \U$1686 ( + .A(\t$2520 ), + .B(1'h0), + .Y(booth_b32_m1) + ); + AO22x1_ASAP7_75t_R \U$1687 ( + .A1(b_registered[1]), + .A2(\sel_0$1921 ), + .B1(b_registered[2]), + .B2(\sel_1$1922 ), + .Y(\t$2521 ) + ); + XOR2x1_ASAP7_75t_R \U$1688 ( + .A(\t$2521 ), + .B(1'h0), + .Y(booth_b32_m2) + ); + AO22x1_ASAP7_75t_R \U$1689 ( + .A1(b_registered[2]), + .A2(\sel_0$1921 ), + .B1(b_registered[3]), + .B2(\sel_1$1922 ), + .Y(\t$2522 ) + ); + XOR2x1_ASAP7_75t_R \U$1690 ( + .A(\t$2522 ), + .B(1'h0), + .Y(booth_b32_m3) + ); + AO22x1_ASAP7_75t_R \U$1691 ( + .A1(b_registered[3]), + .A2(\sel_0$1921 ), + .B1(b_registered[4]), + .B2(\sel_1$1922 ), + .Y(\t$2523 ) + ); + XOR2x1_ASAP7_75t_R \U$1692 ( + .A(\t$2523 ), + .B(1'h0), + .Y(booth_b32_m4) + ); + AO22x1_ASAP7_75t_R \U$1693 ( + .A1(b_registered[4]), + .A2(\sel_0$1921 ), + .B1(b_registered[5]), + .B2(\sel_1$1922 ), + .Y(\t$2524 ) + ); + XOR2x1_ASAP7_75t_R \U$1694 ( + .A(\t$2524 ), + .B(1'h0), + .Y(booth_b32_m5) + ); + AO22x1_ASAP7_75t_R \U$1695 ( + .A1(b_registered[5]), + .A2(\sel_0$1921 ), + .B1(b_registered[6]), + .B2(\sel_1$1922 ), + .Y(\t$2525 ) + ); + XOR2x1_ASAP7_75t_R \U$1696 ( + .A(\t$2525 ), + .B(1'h0), + .Y(booth_b32_m6) + ); + AO22x1_ASAP7_75t_R \U$1697 ( + .A1(b_registered[6]), + .A2(\sel_0$1921 ), + .B1(b_registered[7]), + .B2(\sel_1$1922 ), + .Y(\t$2526 ) + ); + XOR2x1_ASAP7_75t_R \U$1698 ( + .A(\t$2526 ), + .B(1'h0), + .Y(booth_b32_m7) + ); + AO22x1_ASAP7_75t_R \U$1699 ( + .A1(b_registered[7]), + .A2(\sel_0$1921 ), + .B1(b_registered[8]), + .B2(\sel_1$1922 ), + .Y(\t$2527 ) + ); + XOR2x1_ASAP7_75t_R \U$1700 ( + .A(\t$2527 ), + .B(1'h0), + .Y(booth_b32_m8) + ); + AO22x1_ASAP7_75t_R \U$1701 ( + .A1(b_registered[8]), + .A2(\sel_0$1921 ), + .B1(b_registered[9]), + .B2(\sel_1$1922 ), + .Y(\t$2528 ) + ); + XOR2x1_ASAP7_75t_R \U$1702 ( + .A(\t$2528 ), + .B(1'h0), + .Y(booth_b32_m9) + ); + AO22x1_ASAP7_75t_R \U$1703 ( + .A1(b_registered[9]), + .A2(\sel_0$1921 ), + .B1(b_registered[10]), + .B2(\sel_1$1922 ), + .Y(\t$2529 ) + ); + XOR2x1_ASAP7_75t_R \U$1704 ( + .A(\t$2529 ), + .B(1'h0), + .Y(booth_b32_m10) + ); + AO22x1_ASAP7_75t_R \U$1705 ( + .A1(b_registered[10]), + .A2(\sel_0$1921 ), + .B1(b_registered[11]), + .B2(\sel_1$1922 ), + .Y(\t$2530 ) + ); + XOR2x1_ASAP7_75t_R \U$1706 ( + .A(\t$2530 ), + .B(1'h0), + .Y(booth_b32_m11) + ); + AO22x1_ASAP7_75t_R \U$1707 ( + .A1(b_registered[11]), + .A2(\sel_0$1921 ), + .B1(b_registered[12]), + .B2(\sel_1$1922 ), + .Y(\t$2531 ) + ); + XOR2x1_ASAP7_75t_R \U$1708 ( + .A(\t$2531 ), + .B(1'h0), + .Y(booth_b32_m12) + ); + AO22x1_ASAP7_75t_R \U$1709 ( + .A1(b_registered[12]), + .A2(\sel_0$1921 ), + .B1(b_registered[13]), + .B2(\sel_1$1922 ), + .Y(\t$2532 ) + ); + XOR2x1_ASAP7_75t_R \U$1710 ( + .A(\t$2532 ), + .B(1'h0), + .Y(booth_b32_m13) + ); + AO22x1_ASAP7_75t_R \U$1711 ( + .A1(b_registered[13]), + .A2(\sel_0$1921 ), + .B1(b_registered[14]), + .B2(\sel_1$1922 ), + .Y(\t$2533 ) + ); + XOR2x1_ASAP7_75t_R \U$1712 ( + .A(\t$2533 ), + .B(1'h0), + .Y(booth_b32_m14) + ); + AO22x1_ASAP7_75t_R \U$1713 ( + .A1(b_registered[14]), + .A2(\sel_0$1921 ), + .B1(b_registered[15]), + .B2(\sel_1$1922 ), + .Y(\t$2534 ) + ); + XOR2x1_ASAP7_75t_R \U$1714 ( + .A(\t$2534 ), + .B(1'h0), + .Y(booth_b32_m15) + ); + AO22x1_ASAP7_75t_R \U$1715 ( + .A1(b_registered[15]), + .A2(\sel_0$1921 ), + .B1(b_registered[16]), + .B2(\sel_1$1922 ), + .Y(\t$2535 ) + ); + XOR2x1_ASAP7_75t_R \U$1716 ( + .A(\t$2535 ), + .B(1'h0), + .Y(booth_b32_m16) + ); + AO22x1_ASAP7_75t_R \U$1717 ( + .A1(b_registered[16]), + .A2(\sel_0$1921 ), + .B1(b_registered[17]), + .B2(\sel_1$1922 ), + .Y(\t$2536 ) + ); + XOR2x1_ASAP7_75t_R \U$1718 ( + .A(\t$2536 ), + .B(1'h0), + .Y(booth_b32_m17) + ); + AO22x1_ASAP7_75t_R \U$1719 ( + .A1(b_registered[17]), + .A2(\sel_0$1921 ), + .B1(b_registered[18]), + .B2(\sel_1$1922 ), + .Y(\t$2537 ) + ); + XOR2x1_ASAP7_75t_R \U$1720 ( + .A(\t$2537 ), + .B(1'h0), + .Y(booth_b32_m18) + ); + AO22x1_ASAP7_75t_R \U$1721 ( + .A1(b_registered[18]), + .A2(\sel_0$1921 ), + .B1(b_registered[19]), + .B2(\sel_1$1922 ), + .Y(\t$2538 ) + ); + XOR2x1_ASAP7_75t_R \U$1722 ( + .A(\t$2538 ), + .B(1'h0), + .Y(booth_b32_m19) + ); + AO22x1_ASAP7_75t_R \U$1723 ( + .A1(b_registered[19]), + .A2(\sel_0$1921 ), + .B1(b_registered[20]), + .B2(\sel_1$1922 ), + .Y(\t$2539 ) + ); + XOR2x1_ASAP7_75t_R \U$1724 ( + .A(\t$2539 ), + .B(1'h0), + .Y(booth_b32_m20) + ); + AO22x1_ASAP7_75t_R \U$1725 ( + .A1(b_registered[20]), + .A2(\sel_0$1921 ), + .B1(b_registered[21]), + .B2(\sel_1$1922 ), + .Y(\t$2540 ) + ); + XOR2x1_ASAP7_75t_R \U$1726 ( + .A(\t$2540 ), + .B(1'h0), + .Y(booth_b32_m21) + ); + AO22x1_ASAP7_75t_R \U$1727 ( + .A1(b_registered[21]), + .A2(\sel_0$1921 ), + .B1(b_registered[22]), + .B2(\sel_1$1922 ), + .Y(\t$2541 ) + ); + XOR2x1_ASAP7_75t_R \U$1728 ( + .A(\t$2541 ), + .B(1'h0), + .Y(booth_b32_m22) + ); + AO22x1_ASAP7_75t_R \U$1729 ( + .A1(b_registered[22]), + .A2(\sel_0$1921 ), + .B1(b_registered[23]), + .B2(\sel_1$1922 ), + .Y(\t$2542 ) + ); + XOR2x1_ASAP7_75t_R \U$1730 ( + .A(\t$2542 ), + .B(1'h0), + .Y(booth_b32_m23) + ); + AO22x1_ASAP7_75t_R \U$1731 ( + .A1(b_registered[23]), + .A2(\sel_0$1921 ), + .B1(b_registered[24]), + .B2(\sel_1$1922 ), + .Y(\t$2543 ) + ); + XOR2x1_ASAP7_75t_R \U$1732 ( + .A(\t$2543 ), + .B(1'h0), + .Y(booth_b32_m24) + ); + AO22x1_ASAP7_75t_R \U$1733 ( + .A1(b_registered[24]), + .A2(\sel_0$1921 ), + .B1(b_registered[25]), + .B2(\sel_1$1922 ), + .Y(\t$2544 ) + ); + XOR2x1_ASAP7_75t_R \U$1734 ( + .A(\t$2544 ), + .B(1'h0), + .Y(booth_b32_m25) + ); + AO22x1_ASAP7_75t_R \U$1735 ( + .A1(b_registered[25]), + .A2(\sel_0$1921 ), + .B1(b_registered[26]), + .B2(\sel_1$1922 ), + .Y(\t$2545 ) + ); + XOR2x1_ASAP7_75t_R \U$1736 ( + .A(\t$2545 ), + .B(1'h0), + .Y(booth_b32_m26) + ); + AO22x1_ASAP7_75t_R \U$1737 ( + .A1(b_registered[26]), + .A2(\sel_0$1921 ), + .B1(b_registered[27]), + .B2(\sel_1$1922 ), + .Y(\t$2546 ) + ); + XOR2x1_ASAP7_75t_R \U$1738 ( + .A(\t$2546 ), + .B(1'h0), + .Y(booth_b32_m27) + ); + AO22x1_ASAP7_75t_R \U$1739 ( + .A1(b_registered[27]), + .A2(\sel_0$1921 ), + .B1(b_registered[28]), + .B2(\sel_1$1922 ), + .Y(\t$2547 ) + ); + XOR2x1_ASAP7_75t_R \U$1740 ( + .A(\t$2547 ), + .B(1'h0), + .Y(booth_b32_m28) + ); + AO22x1_ASAP7_75t_R \U$1741 ( + .A1(b_registered[28]), + .A2(\sel_0$1921 ), + .B1(b_registered[29]), + .B2(\sel_1$1922 ), + .Y(\t$2548 ) + ); + XOR2x1_ASAP7_75t_R \U$1742 ( + .A(\t$2548 ), + .B(1'h0), + .Y(booth_b32_m29) + ); + AO22x1_ASAP7_75t_R \U$1743 ( + .A1(b_registered[29]), + .A2(\sel_0$1921 ), + .B1(b_registered[30]), + .B2(\sel_1$1922 ), + .Y(\t$2549 ) + ); + XOR2x1_ASAP7_75t_R \U$1744 ( + .A(\t$2549 ), + .B(1'h0), + .Y(booth_b32_m30) + ); + AO22x1_ASAP7_75t_R \U$1745 ( + .A1(b_registered[30]), + .A2(\sel_0$1921 ), + .B1(b_registered[31]), + .B2(\sel_1$1922 ), + .Y(\t$2550 ) + ); + XOR2x1_ASAP7_75t_R \U$1746 ( + .A(\t$2550 ), + .B(1'h0), + .Y(booth_b32_m31) + ); + AO22x1_ASAP7_75t_R \U$1747 ( + .A1(b_registered[31]), + .A2(\sel_0$1921 ), + .B1(1'h0), + .B2(\sel_1$1922 ), + .Y(\t$2551 ) + ); + XOR2x1_ASAP7_75t_R \U$1748 ( + .A(\t$2551 ), + .B(1'h0), + .Y(booth_b32_m32) + ); + INVx1_ASAP7_75t_R \U$1749 ( + .A(1'h0), + .Y(\$52 ) + ); + INVx1_ASAP7_75t_R \U$1750 ( + .A(con), + .Y(\c$2553 ) + ); + INVx1_ASAP7_75t_R \U$1751 ( + .A(sn), + .Y(\s$2555 ) + ); + INVx1_ASAP7_75t_R \U$1752 ( + .A(\con$2556 ), + .Y(\c$2557 ) + ); + INVx1_ASAP7_75t_R \U$1753 ( + .A(\sn$2558 ), + .Y(\s$2559 ) + ); + INVx1_ASAP7_75t_R \U$1754 ( + .A(\con$2560 ), + .Y(\c$2561 ) + ); + INVx1_ASAP7_75t_R \U$1755 ( + .A(\sn$2562 ), + .Y(\s$2563 ) + ); + INVx1_ASAP7_75t_R \U$1756 ( + .A(\con$2564 ), + .Y(\c$2565 ) + ); + INVx1_ASAP7_75t_R \U$1757 ( + .A(\sn$2566 ), + .Y(\s$2567 ) + ); + INVx1_ASAP7_75t_R \U$1758 ( + .A(\con$2568 ), + .Y(\c$2569 ) + ); + INVx1_ASAP7_75t_R \U$1759 ( + .A(\sn$2570 ), + .Y(\s$2571 ) + ); + INVx1_ASAP7_75t_R \U$1760 ( + .A(\con$2572 ), + .Y(\c$2573 ) + ); + INVx1_ASAP7_75t_R \U$1761 ( + .A(\sn$2574 ), + .Y(\s$2575 ) + ); + INVx1_ASAP7_75t_R \U$1762 ( + .A(\con$2576 ), + .Y(\c$2577 ) + ); + INVx1_ASAP7_75t_R \U$1763 ( + .A(\sn$2578 ), + .Y(\s$2579 ) + ); + INVx1_ASAP7_75t_R \U$1764 ( + .A(\con$2580 ), + .Y(\c$2581 ) + ); + INVx1_ASAP7_75t_R \U$1765 ( + .A(\sn$2582 ), + .Y(\s$2583 ) + ); + INVx1_ASAP7_75t_R \U$1766 ( + .A(\con$2584 ), + .Y(\c$2585 ) + ); + INVx1_ASAP7_75t_R \U$1767 ( + .A(\sn$2586 ), + .Y(\s$2587 ) + ); + INVx1_ASAP7_75t_R \U$1768 ( + .A(\con$2588 ), + .Y(\c$2589 ) + ); + INVx1_ASAP7_75t_R \U$1769 ( + .A(\sn$2590 ), + .Y(\s$2591 ) + ); + INVx1_ASAP7_75t_R \U$1770 ( + .A(\con$2592 ), + .Y(\c$2593 ) + ); + INVx1_ASAP7_75t_R \U$1771 ( + .A(\sn$2594 ), + .Y(\s$2595 ) + ); + INVx1_ASAP7_75t_R \U$1772 ( + .A(\con$2596 ), + .Y(\c$2597 ) + ); + INVx1_ASAP7_75t_R \U$1773 ( + .A(\sn$2598 ), + .Y(\s$2599 ) + ); + INVx1_ASAP7_75t_R \U$1774 ( + .A(\con$2600 ), + .Y(\c$2601 ) + ); + INVx1_ASAP7_75t_R \U$1775 ( + .A(\sn$2602 ), + .Y(\s$2603 ) + ); + INVx1_ASAP7_75t_R \U$1776 ( + .A(\con$2604 ), + .Y(\c$2605 ) + ); + INVx1_ASAP7_75t_R \U$1777 ( + .A(\sn$2606 ), + .Y(\s$2607 ) + ); + INVx1_ASAP7_75t_R \U$1778 ( + .A(\con$2608 ), + .Y(\c$2609 ) + ); + INVx1_ASAP7_75t_R \U$1779 ( + .A(\sn$2610 ), + .Y(\s$2611 ) + ); + INVx1_ASAP7_75t_R \U$1780 ( + .A(\con$2612 ), + .Y(\c$2613 ) + ); + INVx1_ASAP7_75t_R \U$1781 ( + .A(\sn$2614 ), + .Y(\s$2615 ) + ); + INVx1_ASAP7_75t_R \U$1782 ( + .A(\con$2616 ), + .Y(\c$2617 ) + ); + INVx1_ASAP7_75t_R \U$1783 ( + .A(\sn$2618 ), + .Y(\s$2619 ) + ); + INVx1_ASAP7_75t_R \U$1784 ( + .A(\con$2620 ), + .Y(\c$2621 ) + ); + INVx1_ASAP7_75t_R \U$1785 ( + .A(\sn$2622 ), + .Y(\s$2623 ) + ); + INVx1_ASAP7_75t_R \U$1786 ( + .A(\con$2624 ), + .Y(\c$2625 ) + ); + INVx1_ASAP7_75t_R \U$1787 ( + .A(\sn$2626 ), + .Y(\s$2627 ) + ); + INVx1_ASAP7_75t_R \U$1788 ( + .A(\con$2628 ), + .Y(\c$2629 ) + ); + INVx1_ASAP7_75t_R \U$1789 ( + .A(\sn$2630 ), + .Y(\s$2631 ) + ); + INVx1_ASAP7_75t_R \U$1790 ( + .A(\con$2632 ), + .Y(\c$2633 ) + ); + INVx1_ASAP7_75t_R \U$1791 ( + .A(\sn$2634 ), + .Y(\s$2635 ) + ); + INVx1_ASAP7_75t_R \U$1792 ( + .A(\con$2636 ), + .Y(\c$2637 ) + ); + INVx1_ASAP7_75t_R \U$1793 ( + .A(\sn$2638 ), + .Y(\s$2639 ) + ); + INVx1_ASAP7_75t_R \U$1794 ( + .A(\con$2640 ), + .Y(\c$2641 ) + ); + INVx1_ASAP7_75t_R \U$1795 ( + .A(\sn$2642 ), + .Y(\s$2643 ) + ); + INVx1_ASAP7_75t_R \U$1796 ( + .A(\con$2644 ), + .Y(\c$2645 ) + ); + INVx1_ASAP7_75t_R \U$1797 ( + .A(\sn$2646 ), + .Y(\s$2647 ) + ); + INVx1_ASAP7_75t_R \U$1798 ( + .A(\con$2648 ), + .Y(\c$2649 ) + ); + INVx1_ASAP7_75t_R \U$1799 ( + .A(\sn$2650 ), + .Y(\s$2651 ) + ); + INVx1_ASAP7_75t_R \U$1800 ( + .A(\con$2652 ), + .Y(\c$2653 ) + ); + INVx1_ASAP7_75t_R \U$1801 ( + .A(\sn$2654 ), + .Y(\s$2655 ) + ); + INVx1_ASAP7_75t_R \U$1802 ( + .A(\con$2656 ), + .Y(\c$2657 ) + ); + INVx1_ASAP7_75t_R \U$1803 ( + .A(\sn$2658 ), + .Y(\s$2659 ) + ); + INVx1_ASAP7_75t_R \U$1804 ( + .A(\con$2660 ), + .Y(\c$2661 ) + ); + INVx1_ASAP7_75t_R \U$1805 ( + .A(\sn$2662 ), + .Y(\s$2663 ) + ); + INVx1_ASAP7_75t_R \U$1806 ( + .A(\con$2664 ), + .Y(\c$2665 ) + ); + INVx1_ASAP7_75t_R \U$1807 ( + .A(\sn$2666 ), + .Y(\s$2667 ) + ); + INVx1_ASAP7_75t_R \U$1808 ( + .A(\con$2668 ), + .Y(\c$2669 ) + ); + INVx1_ASAP7_75t_R \U$1809 ( + .A(\sn$2670 ), + .Y(\s$2671 ) + ); + INVx1_ASAP7_75t_R \U$1810 ( + .A(\con$2672 ), + .Y(\c$2673 ) + ); + INVx1_ASAP7_75t_R \U$1811 ( + .A(\sn$2674 ), + .Y(\s$2675 ) + ); + INVx1_ASAP7_75t_R \U$1812 ( + .A(\con$2676 ), + .Y(\c$2677 ) + ); + INVx1_ASAP7_75t_R \U$1813 ( + .A(\sn$2678 ), + .Y(\s$2679 ) + ); + INVx1_ASAP7_75t_R \U$1814 ( + .A(\con$2680 ), + .Y(\c$2681 ) + ); + INVx1_ASAP7_75t_R \U$1815 ( + .A(\sn$2682 ), + .Y(\s$2683 ) + ); + INVx1_ASAP7_75t_R \U$1816 ( + .A(\con$2684 ), + .Y(\c$2685 ) + ); + INVx1_ASAP7_75t_R \U$1817 ( + .A(\sn$2686 ), + .Y(\s$2687 ) + ); + INVx1_ASAP7_75t_R \U$1818 ( + .A(\con$2688 ), + .Y(\c$2689 ) + ); + INVx1_ASAP7_75t_R \U$1819 ( + .A(\sn$2690 ), + .Y(\s$2691 ) + ); + INVx1_ASAP7_75t_R \U$1820 ( + .A(\con$2692 ), + .Y(\c$2693 ) + ); + INVx1_ASAP7_75t_R \U$1821 ( + .A(\sn$2694 ), + .Y(\s$2695 ) + ); + INVx1_ASAP7_75t_R \U$1822 ( + .A(\con$2696 ), + .Y(\c$2697 ) + ); + INVx1_ASAP7_75t_R \U$1823 ( + .A(\sn$2698 ), + .Y(\s$2699 ) + ); + INVx1_ASAP7_75t_R \U$1824 ( + .A(\con$2700 ), + .Y(\c$2701 ) + ); + INVx1_ASAP7_75t_R \U$1825 ( + .A(\sn$2702 ), + .Y(\s$2703 ) + ); + INVx1_ASAP7_75t_R \U$1826 ( + .A(\con$2704 ), + .Y(\c$2705 ) + ); + INVx1_ASAP7_75t_R \U$1827 ( + .A(\sn$2706 ), + .Y(\s$2707 ) + ); + INVx1_ASAP7_75t_R \U$1828 ( + .A(\con$2708 ), + .Y(\c$2709 ) + ); + INVx1_ASAP7_75t_R \U$1829 ( + .A(\sn$2710 ), + .Y(\s$2711 ) + ); + INVx1_ASAP7_75t_R \U$1830 ( + .A(\con$2712 ), + .Y(\c$2713 ) + ); + INVx1_ASAP7_75t_R \U$1831 ( + .A(\sn$2714 ), + .Y(\s$2715 ) + ); + INVx1_ASAP7_75t_R \U$1832 ( + .A(\con$2716 ), + .Y(\c$2717 ) + ); + INVx1_ASAP7_75t_R \U$1833 ( + .A(\sn$2718 ), + .Y(\s$2719 ) + ); + INVx1_ASAP7_75t_R \U$1834 ( + .A(\con$2720 ), + .Y(\c$2721 ) + ); + INVx1_ASAP7_75t_R \U$1835 ( + .A(\sn$2722 ), + .Y(\s$2723 ) + ); + INVx1_ASAP7_75t_R \U$1836 ( + .A(\con$2724 ), + .Y(\c$2725 ) + ); + INVx1_ASAP7_75t_R \U$1837 ( + .A(\sn$2726 ), + .Y(\s$2727 ) + ); + INVx1_ASAP7_75t_R \U$1838 ( + .A(\con$2728 ), + .Y(\c$2729 ) + ); + INVx1_ASAP7_75t_R \U$1839 ( + .A(\sn$2730 ), + .Y(\s$2731 ) + ); + INVx1_ASAP7_75t_R \U$1840 ( + .A(\con$2732 ), + .Y(\c$2733 ) + ); + INVx1_ASAP7_75t_R \U$1841 ( + .A(\sn$2734 ), + .Y(\s$2735 ) + ); + INVx1_ASAP7_75t_R \U$1842 ( + .A(\con$2736 ), + .Y(\c$2737 ) + ); + INVx1_ASAP7_75t_R \U$1843 ( + .A(\sn$2738 ), + .Y(\s$2739 ) + ); + INVx1_ASAP7_75t_R \U$1844 ( + .A(\con$2740 ), + .Y(\c$2741 ) + ); + INVx1_ASAP7_75t_R \U$1845 ( + .A(\sn$2742 ), + .Y(\s$2743 ) + ); + INVx1_ASAP7_75t_R \U$1846 ( + .A(\con$2744 ), + .Y(\c$2745 ) + ); + INVx1_ASAP7_75t_R \U$1847 ( + .A(\sn$2746 ), + .Y(\s$2747 ) + ); + INVx1_ASAP7_75t_R \U$1848 ( + .A(\con$2748 ), + .Y(\c$2749 ) + ); + INVx1_ASAP7_75t_R \U$1849 ( + .A(\sn$2750 ), + .Y(\s$2751 ) + ); + INVx1_ASAP7_75t_R \U$1850 ( + .A(\con$2752 ), + .Y(\c$2753 ) + ); + INVx1_ASAP7_75t_R \U$1851 ( + .A(\sn$2754 ), + .Y(\s$2755 ) + ); + INVx1_ASAP7_75t_R \U$1852 ( + .A(\con$2756 ), + .Y(\c$2757 ) + ); + INVx1_ASAP7_75t_R \U$1853 ( + .A(\sn$2758 ), + .Y(\s$2759 ) + ); + INVx1_ASAP7_75t_R \U$1854 ( + .A(\con$2760 ), + .Y(\c$2761 ) + ); + INVx1_ASAP7_75t_R \U$1855 ( + .A(\sn$2762 ), + .Y(\s$2763 ) + ); + INVx1_ASAP7_75t_R \U$1856 ( + .A(\con$2764 ), + .Y(\c$2765 ) + ); + INVx1_ASAP7_75t_R \U$1857 ( + .A(\sn$2766 ), + .Y(\s$2767 ) + ); + INVx1_ASAP7_75t_R \U$1858 ( + .A(\con$2768 ), + .Y(\c$2769 ) + ); + INVx1_ASAP7_75t_R \U$1859 ( + .A(\sn$2770 ), + .Y(\s$2771 ) + ); + INVx1_ASAP7_75t_R \U$1860 ( + .A(\con$2772 ), + .Y(\c$2773 ) + ); + INVx1_ASAP7_75t_R \U$1861 ( + .A(\sn$2774 ), + .Y(\s$2775 ) + ); + INVx1_ASAP7_75t_R \U$1862 ( + .A(\con$2776 ), + .Y(\c$2777 ) + ); + INVx1_ASAP7_75t_R \U$1863 ( + .A(\sn$2778 ), + .Y(\s$2779 ) + ); + INVx1_ASAP7_75t_R \U$1864 ( + .A(\con$2780 ), + .Y(\c$2781 ) + ); + INVx1_ASAP7_75t_R \U$1865 ( + .A(\sn$2782 ), + .Y(\s$2783 ) + ); + INVx1_ASAP7_75t_R \U$1866 ( + .A(\con$2784 ), + .Y(\c$2785 ) + ); + INVx1_ASAP7_75t_R \U$1867 ( + .A(\sn$2786 ), + .Y(\s$2787 ) + ); + INVx1_ASAP7_75t_R \U$1868 ( + .A(\con$2788 ), + .Y(\c$2789 ) + ); + INVx1_ASAP7_75t_R \U$1869 ( + .A(\sn$2790 ), + .Y(\s$2791 ) + ); + INVx1_ASAP7_75t_R \U$1870 ( + .A(\con$2792 ), + .Y(\c$2793 ) + ); + INVx1_ASAP7_75t_R \U$1871 ( + .A(\sn$2794 ), + .Y(\s$2795 ) + ); + INVx1_ASAP7_75t_R \U$1872 ( + .A(\con$2796 ), + .Y(\c$2797 ) + ); + INVx1_ASAP7_75t_R \U$1873 ( + .A(\sn$2798 ), + .Y(\s$2799 ) + ); + INVx1_ASAP7_75t_R \U$1874 ( + .A(\con$2800 ), + .Y(\c$2801 ) + ); + INVx1_ASAP7_75t_R \U$1875 ( + .A(\sn$2802 ), + .Y(\s$2803 ) + ); + INVx1_ASAP7_75t_R \U$1876 ( + .A(\con$2804 ), + .Y(\c$2805 ) + ); + INVx1_ASAP7_75t_R \U$1877 ( + .A(\sn$2806 ), + .Y(\s$2807 ) + ); + INVx1_ASAP7_75t_R \U$1878 ( + .A(\con$2808 ), + .Y(\c$2809 ) + ); + INVx1_ASAP7_75t_R \U$1879 ( + .A(\sn$2810 ), + .Y(\s$2811 ) + ); + INVx1_ASAP7_75t_R \U$1880 ( + .A(\con$2812 ), + .Y(\c$2813 ) + ); + INVx1_ASAP7_75t_R \U$1881 ( + .A(\sn$2814 ), + .Y(\s$2815 ) + ); + INVx1_ASAP7_75t_R \U$1882 ( + .A(\con$2816 ), + .Y(\c$2817 ) + ); + INVx1_ASAP7_75t_R \U$1883 ( + .A(\sn$2818 ), + .Y(\s$2819 ) + ); + INVx1_ASAP7_75t_R \U$1884 ( + .A(\con$2820 ), + .Y(\c$2821 ) + ); + INVx1_ASAP7_75t_R \U$1885 ( + .A(\sn$2822 ), + .Y(\s$2823 ) + ); + INVx1_ASAP7_75t_R \U$1886 ( + .A(\con$2824 ), + .Y(\c$2825 ) + ); + INVx1_ASAP7_75t_R \U$1887 ( + .A(\sn$2826 ), + .Y(\s$2827 ) + ); + INVx1_ASAP7_75t_R \U$1888 ( + .A(\con$2828 ), + .Y(\c$2829 ) + ); + INVx1_ASAP7_75t_R \U$1889 ( + .A(\sn$2830 ), + .Y(\s$2831 ) + ); + INVx1_ASAP7_75t_R \U$1890 ( + .A(\con$2832 ), + .Y(\c$2833 ) + ); + INVx1_ASAP7_75t_R \U$1891 ( + .A(\sn$2834 ), + .Y(\s$2835 ) + ); + INVx1_ASAP7_75t_R \U$1892 ( + .A(\con$2836 ), + .Y(\c$2837 ) + ); + INVx1_ASAP7_75t_R \U$1893 ( + .A(\sn$2838 ), + .Y(\s$2839 ) + ); + INVx1_ASAP7_75t_R \U$1894 ( + .A(\con$2840 ), + .Y(\c$2841 ) + ); + INVx1_ASAP7_75t_R \U$1895 ( + .A(\sn$2842 ), + .Y(\s$2843 ) + ); + INVx1_ASAP7_75t_R \U$1896 ( + .A(\con$2844 ), + .Y(\c$2845 ) + ); + INVx1_ASAP7_75t_R \U$1897 ( + .A(\sn$2846 ), + .Y(\s$2847 ) + ); + INVx1_ASAP7_75t_R \U$1898 ( + .A(\con$2848 ), + .Y(\c$2849 ) + ); + INVx1_ASAP7_75t_R \U$1899 ( + .A(\sn$2850 ), + .Y(\s$2851 ) + ); + INVx1_ASAP7_75t_R \U$1900 ( + .A(\con$2852 ), + .Y(\c$2853 ) + ); + INVx1_ASAP7_75t_R \U$1901 ( + .A(\sn$2854 ), + .Y(\s$2855 ) + ); + INVx1_ASAP7_75t_R \U$1902 ( + .A(\con$2856 ), + .Y(\c$2857 ) + ); + INVx1_ASAP7_75t_R \U$1903 ( + .A(\sn$2858 ), + .Y(\s$2859 ) + ); + INVx1_ASAP7_75t_R \U$1904 ( + .A(\con$2860 ), + .Y(\c$2861 ) + ); + INVx1_ASAP7_75t_R \U$1905 ( + .A(\sn$2862 ), + .Y(\s$2863 ) + ); + INVx1_ASAP7_75t_R \U$1906 ( + .A(\con$2864 ), + .Y(\c$2865 ) + ); + INVx1_ASAP7_75t_R \U$1907 ( + .A(\sn$2866 ), + .Y(\s$2867 ) + ); + INVx1_ASAP7_75t_R \U$1908 ( + .A(\con$2868 ), + .Y(\c$2869 ) + ); + INVx1_ASAP7_75t_R \U$1909 ( + .A(\sn$2870 ), + .Y(\s$2871 ) + ); + INVx1_ASAP7_75t_R \U$1910 ( + .A(\con$2872 ), + .Y(\c$2873 ) + ); + INVx1_ASAP7_75t_R \U$1911 ( + .A(\sn$2874 ), + .Y(\s$2875 ) + ); + INVx1_ASAP7_75t_R \U$1912 ( + .A(\con$2876 ), + .Y(\c$2877 ) + ); + INVx1_ASAP7_75t_R \U$1913 ( + .A(\sn$2878 ), + .Y(\s$2879 ) + ); + INVx1_ASAP7_75t_R \U$1914 ( + .A(\con$2880 ), + .Y(\c$2881 ) + ); + INVx1_ASAP7_75t_R \U$1915 ( + .A(\sn$2882 ), + .Y(\s$2883 ) + ); + INVx1_ASAP7_75t_R \U$1916 ( + .A(\con$2884 ), + .Y(\c$2885 ) + ); + INVx1_ASAP7_75t_R \U$1917 ( + .A(\sn$2886 ), + .Y(\s$2887 ) + ); + INVx1_ASAP7_75t_R \U$1918 ( + .A(\con$2888 ), + .Y(\c$2889 ) + ); + INVx1_ASAP7_75t_R \U$1919 ( + .A(\sn$2890 ), + .Y(\s$2891 ) + ); + INVx1_ASAP7_75t_R \U$1920 ( + .A(\con$2892 ), + .Y(\c$2893 ) + ); + INVx1_ASAP7_75t_R \U$1921 ( + .A(\sn$2894 ), + .Y(\s$2895 ) + ); + INVx1_ASAP7_75t_R \U$1922 ( + .A(\con$2896 ), + .Y(\c$2897 ) + ); + INVx1_ASAP7_75t_R \U$1923 ( + .A(\sn$2898 ), + .Y(\s$2899 ) + ); + INVx1_ASAP7_75t_R \U$1924 ( + .A(\con$2900 ), + .Y(\c$2901 ) + ); + INVx1_ASAP7_75t_R \U$1925 ( + .A(\sn$2902 ), + .Y(\s$2903 ) + ); + INVx1_ASAP7_75t_R \U$1926 ( + .A(\con$2904 ), + .Y(\c$2905 ) + ); + INVx1_ASAP7_75t_R \U$1927 ( + .A(\sn$2906 ), + .Y(\s$2907 ) + ); + INVx1_ASAP7_75t_R \U$1928 ( + .A(\con$2908 ), + .Y(\c$2909 ) + ); + INVx1_ASAP7_75t_R \U$1929 ( + .A(\sn$2910 ), + .Y(\s$2911 ) + ); + INVx1_ASAP7_75t_R \U$1930 ( + .A(\con$2912 ), + .Y(\c$2913 ) + ); + INVx1_ASAP7_75t_R \U$1931 ( + .A(\sn$2914 ), + .Y(\s$2915 ) + ); + INVx1_ASAP7_75t_R \U$1932 ( + .A(\con$2916 ), + .Y(\c$2917 ) + ); + INVx1_ASAP7_75t_R \U$1933 ( + .A(\sn$2918 ), + .Y(\s$2919 ) + ); + INVx1_ASAP7_75t_R \U$1934 ( + .A(\con$2920 ), + .Y(\c$2921 ) + ); + INVx1_ASAP7_75t_R \U$1935 ( + .A(\sn$2922 ), + .Y(\s$2923 ) + ); + INVx1_ASAP7_75t_R \U$1936 ( + .A(\con$2924 ), + .Y(\c$2925 ) + ); + INVx1_ASAP7_75t_R \U$1937 ( + .A(\sn$2926 ), + .Y(\s$2927 ) + ); + INVx1_ASAP7_75t_R \U$1938 ( + .A(\con$2928 ), + .Y(\c$2929 ) + ); + INVx1_ASAP7_75t_R \U$1939 ( + .A(\sn$2930 ), + .Y(\s$2931 ) + ); + INVx1_ASAP7_75t_R \U$1940 ( + .A(\con$2932 ), + .Y(\c$2933 ) + ); + INVx1_ASAP7_75t_R \U$1941 ( + .A(\sn$2934 ), + .Y(\s$2935 ) + ); + INVx1_ASAP7_75t_R \U$1942 ( + .A(\con$2936 ), + .Y(\c$2937 ) + ); + INVx1_ASAP7_75t_R \U$1943 ( + .A(\sn$2938 ), + .Y(\s$2939 ) + ); + INVx1_ASAP7_75t_R \U$1944 ( + .A(\con$2940 ), + .Y(\c$2941 ) + ); + INVx1_ASAP7_75t_R \U$1945 ( + .A(\sn$2942 ), + .Y(\s$2943 ) + ); + INVx1_ASAP7_75t_R \U$1946 ( + .A(\con$2944 ), + .Y(\c$2945 ) + ); + INVx1_ASAP7_75t_R \U$1947 ( + .A(\sn$2946 ), + .Y(\s$2947 ) + ); + INVx1_ASAP7_75t_R \U$1948 ( + .A(\con$2948 ), + .Y(\c$2949 ) + ); + INVx1_ASAP7_75t_R \U$1949 ( + .A(\sn$2950 ), + .Y(\s$2951 ) + ); + INVx1_ASAP7_75t_R \U$1950 ( + .A(\con$2952 ), + .Y(\c$2953 ) + ); + INVx1_ASAP7_75t_R \U$1951 ( + .A(\sn$2954 ), + .Y(\s$2955 ) + ); + INVx1_ASAP7_75t_R \U$1952 ( + .A(\con$2956 ), + .Y(\c$2957 ) + ); + INVx1_ASAP7_75t_R \U$1953 ( + .A(\sn$2958 ), + .Y(\s$2959 ) + ); + INVx1_ASAP7_75t_R \U$1954 ( + .A(\con$2960 ), + .Y(\c$2961 ) + ); + INVx1_ASAP7_75t_R \U$1955 ( + .A(\sn$2962 ), + .Y(\s$2963 ) + ); + INVx1_ASAP7_75t_R \U$1956 ( + .A(\con$2964 ), + .Y(\c$2965 ) + ); + INVx1_ASAP7_75t_R \U$1957 ( + .A(\sn$2966 ), + .Y(\s$2967 ) + ); + INVx1_ASAP7_75t_R \U$1958 ( + .A(\con$2968 ), + .Y(\c$2969 ) + ); + INVx1_ASAP7_75t_R \U$1959 ( + .A(\sn$2970 ), + .Y(\s$2971 ) + ); + INVx1_ASAP7_75t_R \U$1960 ( + .A(\con$2972 ), + .Y(\c$2973 ) + ); + INVx1_ASAP7_75t_R \U$1961 ( + .A(\sn$2974 ), + .Y(\s$2975 ) + ); + INVx1_ASAP7_75t_R \U$1962 ( + .A(\con$2976 ), + .Y(\c$2977 ) + ); + INVx1_ASAP7_75t_R \U$1963 ( + .A(\sn$2978 ), + .Y(\s$2979 ) + ); + INVx1_ASAP7_75t_R \U$1964 ( + .A(\con$2980 ), + .Y(\c$2981 ) + ); + INVx1_ASAP7_75t_R \U$1965 ( + .A(\sn$2982 ), + .Y(\s$2983 ) + ); + INVx1_ASAP7_75t_R \U$1966 ( + .A(\con$2984 ), + .Y(\c$2985 ) + ); + INVx1_ASAP7_75t_R \U$1967 ( + .A(\sn$2986 ), + .Y(\s$2987 ) + ); + INVx1_ASAP7_75t_R \U$1968 ( + .A(\con$2988 ), + .Y(\c$2989 ) + ); + INVx1_ASAP7_75t_R \U$1969 ( + .A(\sn$2990 ), + .Y(\s$2991 ) + ); + INVx1_ASAP7_75t_R \U$1970 ( + .A(\con$2992 ), + .Y(\c$2993 ) + ); + INVx1_ASAP7_75t_R \U$1971 ( + .A(\sn$2994 ), + .Y(\s$2995 ) + ); + INVx1_ASAP7_75t_R \U$1972 ( + .A(\con$2996 ), + .Y(\c$2997 ) + ); + INVx1_ASAP7_75t_R \U$1973 ( + .A(\sn$2998 ), + .Y(\s$2999 ) + ); + INVx1_ASAP7_75t_R \U$1974 ( + .A(\con$3000 ), + .Y(\c$3001 ) + ); + INVx1_ASAP7_75t_R \U$1975 ( + .A(\sn$3002 ), + .Y(\s$3003 ) + ); + INVx1_ASAP7_75t_R \U$1976 ( + .A(\con$3004 ), + .Y(\c$3005 ) + ); + INVx1_ASAP7_75t_R \U$1977 ( + .A(\sn$3006 ), + .Y(\s$3007 ) + ); + INVx1_ASAP7_75t_R \U$1978 ( + .A(\con$3008 ), + .Y(\c$3009 ) + ); + INVx1_ASAP7_75t_R \U$1979 ( + .A(\sn$3010 ), + .Y(\s$3011 ) + ); + INVx1_ASAP7_75t_R \U$1980 ( + .A(\con$3012 ), + .Y(\c$3013 ) + ); + INVx1_ASAP7_75t_R \U$1981 ( + .A(\sn$3014 ), + .Y(\s$3015 ) + ); + INVx1_ASAP7_75t_R \U$1982 ( + .A(\con$3016 ), + .Y(\c$3017 ) + ); + INVx1_ASAP7_75t_R \U$1983 ( + .A(\sn$3018 ), + .Y(\s$3019 ) + ); + INVx1_ASAP7_75t_R \U$1984 ( + .A(\con$3020 ), + .Y(\c$3021 ) + ); + INVx1_ASAP7_75t_R \U$1985 ( + .A(\sn$3022 ), + .Y(\s$3023 ) + ); + INVx1_ASAP7_75t_R \U$1986 ( + .A(\con$3024 ), + .Y(\c$3025 ) + ); + INVx1_ASAP7_75t_R \U$1987 ( + .A(\sn$3026 ), + .Y(\s$3027 ) + ); + INVx1_ASAP7_75t_R \U$1988 ( + .A(\con$3028 ), + .Y(\c$3029 ) + ); + INVx1_ASAP7_75t_R \U$1989 ( + .A(\sn$3030 ), + .Y(\s$3031 ) + ); + INVx1_ASAP7_75t_R \U$1990 ( + .A(\con$3032 ), + .Y(\c$3033 ) + ); + INVx1_ASAP7_75t_R \U$1991 ( + .A(\sn$3034 ), + .Y(\s$3035 ) + ); + INVx1_ASAP7_75t_R \U$1992 ( + .A(\con$3036 ), + .Y(\c$3037 ) + ); + INVx1_ASAP7_75t_R \U$1993 ( + .A(\sn$3038 ), + .Y(\s$3039 ) + ); + INVx1_ASAP7_75t_R \U$1994 ( + .A(\con$3040 ), + .Y(\c$3041 ) + ); + INVx1_ASAP7_75t_R \U$1995 ( + .A(\sn$3042 ), + .Y(\s$3043 ) + ); + INVx1_ASAP7_75t_R \U$1996 ( + .A(\con$3044 ), + .Y(\c$3045 ) + ); + INVx1_ASAP7_75t_R \U$1997 ( + .A(\sn$3046 ), + .Y(\s$3047 ) + ); + INVx1_ASAP7_75t_R \U$1998 ( + .A(\con$3048 ), + .Y(\c$3049 ) + ); + INVx1_ASAP7_75t_R \U$1999 ( + .A(\sn$3050 ), + .Y(\s$3051 ) + ); + INVx1_ASAP7_75t_R \U$2000 ( + .A(\con$3052 ), + .Y(\c$3053 ) + ); + INVx1_ASAP7_75t_R \U$2001 ( + .A(\sn$3054 ), + .Y(\s$3055 ) + ); + INVx1_ASAP7_75t_R \U$2002 ( + .A(\con$3056 ), + .Y(\c$3057 ) + ); + INVx1_ASAP7_75t_R \U$2003 ( + .A(\sn$3058 ), + .Y(\s$3059 ) + ); + INVx1_ASAP7_75t_R \U$2004 ( + .A(\con$3060 ), + .Y(\c$3061 ) + ); + INVx1_ASAP7_75t_R \U$2005 ( + .A(\sn$3062 ), + .Y(\s$3063 ) + ); + INVx1_ASAP7_75t_R \U$2006 ( + .A(\con$3064 ), + .Y(\c$3065 ) + ); + INVx1_ASAP7_75t_R \U$2007 ( + .A(\sn$3066 ), + .Y(\s$3067 ) + ); + INVx1_ASAP7_75t_R \U$2008 ( + .A(\con$3068 ), + .Y(\c$3069 ) + ); + INVx1_ASAP7_75t_R \U$2009 ( + .A(\sn$3070 ), + .Y(\s$3071 ) + ); + INVx1_ASAP7_75t_R \U$2010 ( + .A(\con$3072 ), + .Y(\c$3073 ) + ); + INVx1_ASAP7_75t_R \U$2011 ( + .A(\sn$3074 ), + .Y(\s$3075 ) + ); + INVx1_ASAP7_75t_R \U$2012 ( + .A(\con$3076 ), + .Y(\c$3077 ) + ); + INVx1_ASAP7_75t_R \U$2013 ( + .A(\sn$3078 ), + .Y(\s$3079 ) + ); + INVx1_ASAP7_75t_R \U$2014 ( + .A(\con$3080 ), + .Y(\c$3081 ) + ); + INVx1_ASAP7_75t_R \U$2015 ( + .A(\sn$3082 ), + .Y(\s$3083 ) + ); + INVx1_ASAP7_75t_R \U$2016 ( + .A(\con$3084 ), + .Y(\c$3085 ) + ); + INVx1_ASAP7_75t_R \U$2017 ( + .A(\sn$3086 ), + .Y(\s$3087 ) + ); + INVx1_ASAP7_75t_R \U$2018 ( + .A(\con$3088 ), + .Y(\c$3089 ) + ); + INVx1_ASAP7_75t_R \U$2019 ( + .A(\sn$3090 ), + .Y(\s$3091 ) + ); + INVx1_ASAP7_75t_R \U$2020 ( + .A(\con$3092 ), + .Y(\c$3093 ) + ); + INVx1_ASAP7_75t_R \U$2021 ( + .A(\sn$3094 ), + .Y(\s$3095 ) + ); + INVx1_ASAP7_75t_R \U$2022 ( + .A(\con$3096 ), + .Y(\c$3097 ) + ); + INVx1_ASAP7_75t_R \U$2023 ( + .A(\sn$3098 ), + .Y(\s$3099 ) + ); + INVx1_ASAP7_75t_R \U$2024 ( + .A(\con$3100 ), + .Y(\c$3101 ) + ); + INVx1_ASAP7_75t_R \U$2025 ( + .A(\sn$3102 ), + .Y(\s$3103 ) + ); + INVx1_ASAP7_75t_R \U$2026 ( + .A(\con$3104 ), + .Y(\c$3105 ) + ); + INVx1_ASAP7_75t_R \U$2027 ( + .A(\sn$3106 ), + .Y(\s$3107 ) + ); + INVx1_ASAP7_75t_R \U$2028 ( + .A(\con$3108 ), + .Y(\c$3109 ) + ); + INVx1_ASAP7_75t_R \U$2029 ( + .A(\sn$3110 ), + .Y(\s$3111 ) + ); + INVx1_ASAP7_75t_R \U$2030 ( + .A(\con$3112 ), + .Y(\c$3113 ) + ); + INVx1_ASAP7_75t_R \U$2031 ( + .A(\sn$3114 ), + .Y(\s$3115 ) + ); + INVx1_ASAP7_75t_R \U$2032 ( + .A(\con$3116 ), + .Y(\c$3117 ) + ); + INVx1_ASAP7_75t_R \U$2033 ( + .A(\sn$3118 ), + .Y(\s$3119 ) + ); + INVx1_ASAP7_75t_R \U$2034 ( + .A(\con$3120 ), + .Y(\c$3121 ) + ); + INVx1_ASAP7_75t_R \U$2035 ( + .A(\sn$3122 ), + .Y(\s$3123 ) + ); + INVx1_ASAP7_75t_R \U$2036 ( + .A(\con$3124 ), + .Y(\c$3125 ) + ); + INVx1_ASAP7_75t_R \U$2037 ( + .A(\sn$3126 ), + .Y(\s$3127 ) + ); + INVx1_ASAP7_75t_R \U$2038 ( + .A(\con$3128 ), + .Y(\c$3129 ) + ); + INVx1_ASAP7_75t_R \U$2039 ( + .A(\sn$3130 ), + .Y(\s$3131 ) + ); + INVx1_ASAP7_75t_R \U$2040 ( + .A(\con$3132 ), + .Y(\c$3133 ) + ); + INVx1_ASAP7_75t_R \U$2041 ( + .A(\sn$3134 ), + .Y(\s$3135 ) + ); + INVx1_ASAP7_75t_R \U$2042 ( + .A(\con$3136 ), + .Y(\c$3137 ) + ); + INVx1_ASAP7_75t_R \U$2043 ( + .A(\sn$3138 ), + .Y(\s$3139 ) + ); + INVx1_ASAP7_75t_R \U$2044 ( + .A(\con$3140 ), + .Y(\c$3141 ) + ); + INVx1_ASAP7_75t_R \U$2045 ( + .A(\sn$3142 ), + .Y(\s$3143 ) + ); + INVx1_ASAP7_75t_R \U$2046 ( + .A(\con$3144 ), + .Y(\c$3145 ) + ); + INVx1_ASAP7_75t_R \U$2047 ( + .A(\sn$3146 ), + .Y(\s$3147 ) + ); + INVx1_ASAP7_75t_R \U$2048 ( + .A(\con$3148 ), + .Y(\c$3149 ) + ); + INVx1_ASAP7_75t_R \U$2049 ( + .A(\sn$3150 ), + .Y(\s$3151 ) + ); + INVx1_ASAP7_75t_R \U$2050 ( + .A(\con$3152 ), + .Y(\c$3153 ) + ); + INVx1_ASAP7_75t_R \U$2051 ( + .A(\sn$3154 ), + .Y(\s$3155 ) + ); + INVx1_ASAP7_75t_R \U$2052 ( + .A(\con$3156 ), + .Y(\c$3157 ) + ); + INVx1_ASAP7_75t_R \U$2053 ( + .A(\sn$3158 ), + .Y(\s$3159 ) + ); + INVx1_ASAP7_75t_R \U$2054 ( + .A(\con$3160 ), + .Y(\c$3161 ) + ); + INVx1_ASAP7_75t_R \U$2055 ( + .A(\sn$3162 ), + .Y(\s$3163 ) + ); + INVx1_ASAP7_75t_R \U$2056 ( + .A(\con$3164 ), + .Y(\c$3165 ) + ); + INVx1_ASAP7_75t_R \U$2057 ( + .A(\sn$3166 ), + .Y(\s$3167 ) + ); + INVx1_ASAP7_75t_R \U$2058 ( + .A(\con$3168 ), + .Y(\c$3169 ) + ); + INVx1_ASAP7_75t_R \U$2059 ( + .A(\sn$3170 ), + .Y(\s$3171 ) + ); + INVx1_ASAP7_75t_R \U$2060 ( + .A(\con$3172 ), + .Y(\c$3173 ) + ); + INVx1_ASAP7_75t_R \U$2061 ( + .A(\sn$3174 ), + .Y(\s$3175 ) + ); + INVx1_ASAP7_75t_R \U$2062 ( + .A(\con$3176 ), + .Y(\c$3177 ) + ); + INVx1_ASAP7_75t_R \U$2063 ( + .A(\sn$3178 ), + .Y(\s$3179 ) + ); + INVx1_ASAP7_75t_R \U$2064 ( + .A(\con$3180 ), + .Y(\c$3181 ) + ); + INVx1_ASAP7_75t_R \U$2065 ( + .A(\sn$3182 ), + .Y(\s$3183 ) + ); + INVx1_ASAP7_75t_R \U$2066 ( + .A(\con$3184 ), + .Y(\c$3185 ) + ); + INVx1_ASAP7_75t_R \U$2067 ( + .A(\sn$3186 ), + .Y(\s$3187 ) + ); + INVx1_ASAP7_75t_R \U$2068 ( + .A(\con$3188 ), + .Y(\c$3189 ) + ); + INVx1_ASAP7_75t_R \U$2069 ( + .A(\sn$3190 ), + .Y(\s$3191 ) + ); + INVx1_ASAP7_75t_R \U$2070 ( + .A(\con$3192 ), + .Y(\c$3193 ) + ); + INVx1_ASAP7_75t_R \U$2071 ( + .A(\sn$3194 ), + .Y(\s$3195 ) + ); + INVx1_ASAP7_75t_R \U$2072 ( + .A(\con$3196 ), + .Y(\c$3197 ) + ); + INVx1_ASAP7_75t_R \U$2073 ( + .A(\sn$3198 ), + .Y(\s$3199 ) + ); + INVx1_ASAP7_75t_R \U$2074 ( + .A(\con$3200 ), + .Y(\c$3201 ) + ); + INVx1_ASAP7_75t_R \U$2075 ( + .A(\sn$3202 ), + .Y(\s$3203 ) + ); + INVx1_ASAP7_75t_R \U$2076 ( + .A(\con$3204 ), + .Y(\c$3205 ) + ); + INVx1_ASAP7_75t_R \U$2077 ( + .A(\sn$3206 ), + .Y(\s$3207 ) + ); + INVx1_ASAP7_75t_R \U$2078 ( + .A(\con$3208 ), + .Y(\c$3209 ) + ); + INVx1_ASAP7_75t_R \U$2079 ( + .A(\sn$3210 ), + .Y(\s$3211 ) + ); + INVx1_ASAP7_75t_R \U$2080 ( + .A(\con$3212 ), + .Y(\c$3213 ) + ); + INVx1_ASAP7_75t_R \U$2081 ( + .A(\sn$3214 ), + .Y(\s$3215 ) + ); + INVx1_ASAP7_75t_R \U$2082 ( + .A(\con$3216 ), + .Y(\c$3217 ) + ); + INVx1_ASAP7_75t_R \U$2083 ( + .A(\sn$3218 ), + .Y(\s$3219 ) + ); + INVx1_ASAP7_75t_R \U$2084 ( + .A(\con$3220 ), + .Y(\c$3221 ) + ); + INVx1_ASAP7_75t_R \U$2085 ( + .A(\sn$3222 ), + .Y(\s$3223 ) + ); + INVx1_ASAP7_75t_R \U$2086 ( + .A(\con$3224 ), + .Y(\c$3225 ) + ); + INVx1_ASAP7_75t_R \U$2087 ( + .A(\sn$3226 ), + .Y(\s$3227 ) + ); + INVx1_ASAP7_75t_R \U$2088 ( + .A(\con$3228 ), + .Y(\c$3229 ) + ); + INVx1_ASAP7_75t_R \U$2089 ( + .A(\sn$3230 ), + .Y(\s$3231 ) + ); + INVx1_ASAP7_75t_R \U$2090 ( + .A(\con$3232 ), + .Y(\c$3233 ) + ); + INVx1_ASAP7_75t_R \U$2091 ( + .A(\sn$3234 ), + .Y(\s$3235 ) + ); + INVx1_ASAP7_75t_R \U$2092 ( + .A(\con$3236 ), + .Y(\c$3237 ) + ); + INVx1_ASAP7_75t_R \U$2093 ( + .A(\sn$3238 ), + .Y(\s$3239 ) + ); + INVx1_ASAP7_75t_R \U$2094 ( + .A(\con$3240 ), + .Y(\c$3241 ) + ); + INVx1_ASAP7_75t_R \U$2095 ( + .A(\sn$3242 ), + .Y(\s$3243 ) + ); + INVx1_ASAP7_75t_R \U$2096 ( + .A(\con$3244 ), + .Y(\c$3245 ) + ); + INVx1_ASAP7_75t_R \U$2097 ( + .A(\sn$3246 ), + .Y(\s$3247 ) + ); + INVx1_ASAP7_75t_R \U$2098 ( + .A(\con$3248 ), + .Y(\c$3249 ) + ); + INVx1_ASAP7_75t_R \U$2099 ( + .A(\sn$3250 ), + .Y(\s$3251 ) + ); + INVx1_ASAP7_75t_R \U$2100 ( + .A(\con$3252 ), + .Y(\c$3253 ) + ); + INVx1_ASAP7_75t_R \U$2101 ( + .A(\sn$3254 ), + .Y(\s$3255 ) + ); + INVx1_ASAP7_75t_R \U$2102 ( + .A(\con$3256 ), + .Y(\c$3257 ) + ); + INVx1_ASAP7_75t_R \U$2103 ( + .A(\sn$3258 ), + .Y(\s$3259 ) + ); + INVx1_ASAP7_75t_R \U$2104 ( + .A(\con$3260 ), + .Y(\c$3261 ) + ); + INVx1_ASAP7_75t_R \U$2105 ( + .A(\sn$3262 ), + .Y(\s$3263 ) + ); + INVx1_ASAP7_75t_R \U$2106 ( + .A(\con$3264 ), + .Y(\c$3265 ) + ); + INVx1_ASAP7_75t_R \U$2107 ( + .A(\sn$3266 ), + .Y(\s$3267 ) + ); + INVx1_ASAP7_75t_R \U$2108 ( + .A(\con$3268 ), + .Y(\c$3269 ) + ); + INVx1_ASAP7_75t_R \U$2109 ( + .A(\sn$3270 ), + .Y(\s$3271 ) + ); + INVx1_ASAP7_75t_R \U$2110 ( + .A(\con$3272 ), + .Y(\c$3273 ) + ); + INVx1_ASAP7_75t_R \U$2111 ( + .A(\sn$3274 ), + .Y(\s$3275 ) + ); + INVx1_ASAP7_75t_R \U$2112 ( + .A(\con$3276 ), + .Y(\c$3277 ) + ); + INVx1_ASAP7_75t_R \U$2113 ( + .A(\sn$3278 ), + .Y(\s$3279 ) + ); + INVx1_ASAP7_75t_R \U$2114 ( + .A(\con$3280 ), + .Y(\c$3281 ) + ); + INVx1_ASAP7_75t_R \U$2115 ( + .A(\sn$3282 ), + .Y(\s$3283 ) + ); + INVx1_ASAP7_75t_R \U$2116 ( + .A(\con$3284 ), + .Y(\c$3285 ) + ); + INVx1_ASAP7_75t_R \U$2117 ( + .A(\sn$3286 ), + .Y(\s$3287 ) + ); + INVx1_ASAP7_75t_R \U$2118 ( + .A(\con$3288 ), + .Y(\c$3289 ) + ); + INVx1_ASAP7_75t_R \U$2119 ( + .A(\sn$3290 ), + .Y(\s$3291 ) + ); + INVx1_ASAP7_75t_R \U$2120 ( + .A(\con$3292 ), + .Y(\c$3293 ) + ); + INVx1_ASAP7_75t_R \U$2121 ( + .A(\sn$3294 ), + .Y(\s$3295 ) + ); + INVx1_ASAP7_75t_R \U$2122 ( + .A(\con$3296 ), + .Y(\c$3297 ) + ); + INVx1_ASAP7_75t_R \U$2123 ( + .A(\sn$3298 ), + .Y(\s$3299 ) + ); + INVx1_ASAP7_75t_R \U$2124 ( + .A(\con$3300 ), + .Y(\c$3301 ) + ); + INVx1_ASAP7_75t_R \U$2125 ( + .A(\sn$3302 ), + .Y(\s$3303 ) + ); + INVx1_ASAP7_75t_R \U$2126 ( + .A(\con$3304 ), + .Y(\c$3305 ) + ); + INVx1_ASAP7_75t_R \U$2127 ( + .A(\sn$3306 ), + .Y(\s$3307 ) + ); + INVx1_ASAP7_75t_R \U$2128 ( + .A(\con$3308 ), + .Y(\c$3309 ) + ); + INVx1_ASAP7_75t_R \U$2129 ( + .A(\sn$3310 ), + .Y(\s$3311 ) + ); + INVx1_ASAP7_75t_R \U$2130 ( + .A(\con$3312 ), + .Y(\c$3313 ) + ); + INVx1_ASAP7_75t_R \U$2131 ( + .A(\sn$3314 ), + .Y(\s$3315 ) + ); + INVx1_ASAP7_75t_R \U$2132 ( + .A(\con$3316 ), + .Y(\c$3317 ) + ); + INVx1_ASAP7_75t_R \U$2133 ( + .A(\sn$3318 ), + .Y(\s$3319 ) + ); + INVx1_ASAP7_75t_R \U$2134 ( + .A(\con$3320 ), + .Y(\c$3321 ) + ); + INVx1_ASAP7_75t_R \U$2135 ( + .A(\sn$3322 ), + .Y(\s$3323 ) + ); + INVx1_ASAP7_75t_R \U$2136 ( + .A(\con$3324 ), + .Y(\c$3325 ) + ); + INVx1_ASAP7_75t_R \U$2137 ( + .A(\sn$3326 ), + .Y(\s$3327 ) + ); + INVx1_ASAP7_75t_R \U$2138 ( + .A(\con$3328 ), + .Y(\c$3329 ) + ); + INVx1_ASAP7_75t_R \U$2139 ( + .A(\sn$3330 ), + .Y(\s$3331 ) + ); + INVx1_ASAP7_75t_R \U$2140 ( + .A(\con$3332 ), + .Y(\c$3333 ) + ); + INVx1_ASAP7_75t_R \U$2141 ( + .A(\sn$3334 ), + .Y(\s$3335 ) + ); + INVx1_ASAP7_75t_R \U$2142 ( + .A(\con$3336 ), + .Y(\c$3337 ) + ); + INVx1_ASAP7_75t_R \U$2143 ( + .A(\sn$3338 ), + .Y(\s$3339 ) + ); + INVx1_ASAP7_75t_R \U$2144 ( + .A(\con$3340 ), + .Y(\c$3341 ) + ); + INVx1_ASAP7_75t_R \U$2145 ( + .A(\sn$3342 ), + .Y(\s$3343 ) + ); + INVx1_ASAP7_75t_R \U$2146 ( + .A(\con$3344 ), + .Y(\c$3345 ) + ); + INVx1_ASAP7_75t_R \U$2147 ( + .A(\sn$3346 ), + .Y(\s$3347 ) + ); + INVx1_ASAP7_75t_R \U$2148 ( + .A(\con$3348 ), + .Y(\c$3349 ) + ); + INVx1_ASAP7_75t_R \U$2149 ( + .A(\sn$3350 ), + .Y(\s$3351 ) + ); + INVx1_ASAP7_75t_R \U$2150 ( + .A(\con$3352 ), + .Y(\c$3353 ) + ); + INVx1_ASAP7_75t_R \U$2151 ( + .A(\sn$3354 ), + .Y(\s$3355 ) + ); + INVx1_ASAP7_75t_R \U$2152 ( + .A(\con$3356 ), + .Y(\c$3357 ) + ); + INVx1_ASAP7_75t_R \U$2153 ( + .A(\sn$3358 ), + .Y(\s$3359 ) + ); + INVx1_ASAP7_75t_R \U$2154 ( + .A(\con$3360 ), + .Y(\c$3361 ) + ); + INVx1_ASAP7_75t_R \U$2155 ( + .A(\sn$3362 ), + .Y(\s$3363 ) + ); + INVx1_ASAP7_75t_R \U$2156 ( + .A(\con$3364 ), + .Y(\c$3365 ) + ); + INVx1_ASAP7_75t_R \U$2157 ( + .A(\sn$3366 ), + .Y(\s$3367 ) + ); + INVx1_ASAP7_75t_R \U$2158 ( + .A(\con$3368 ), + .Y(\c$3369 ) + ); + INVx1_ASAP7_75t_R \U$2159 ( + .A(\sn$3370 ), + .Y(\s$3371 ) + ); + INVx1_ASAP7_75t_R \U$2160 ( + .A(\con$3372 ), + .Y(\c$3373 ) + ); + INVx1_ASAP7_75t_R \U$2161 ( + .A(\sn$3374 ), + .Y(\s$3375 ) + ); + INVx1_ASAP7_75t_R \U$2162 ( + .A(\con$3376 ), + .Y(\c$3377 ) + ); + INVx1_ASAP7_75t_R \U$2163 ( + .A(\sn$3378 ), + .Y(\s$3379 ) + ); + INVx1_ASAP7_75t_R \U$2164 ( + .A(\con$3380 ), + .Y(\c$3381 ) + ); + INVx1_ASAP7_75t_R \U$2165 ( + .A(\sn$3382 ), + .Y(\s$3383 ) + ); + INVx1_ASAP7_75t_R \U$2166 ( + .A(\con$3384 ), + .Y(\c$3385 ) + ); + INVx1_ASAP7_75t_R \U$2167 ( + .A(\sn$3386 ), + .Y(\s$3387 ) + ); + INVx1_ASAP7_75t_R \U$2168 ( + .A(\con$3388 ), + .Y(\c$3389 ) + ); + INVx1_ASAP7_75t_R \U$2169 ( + .A(\sn$3390 ), + .Y(\s$3391 ) + ); + INVx1_ASAP7_75t_R \U$2170 ( + .A(\con$3392 ), + .Y(\c$3393 ) + ); + INVx1_ASAP7_75t_R \U$2171 ( + .A(\sn$3394 ), + .Y(\s$3395 ) + ); + INVx1_ASAP7_75t_R \U$2172 ( + .A(\con$3396 ), + .Y(\c$3397 ) + ); + INVx1_ASAP7_75t_R \U$2173 ( + .A(\sn$3398 ), + .Y(\s$3399 ) + ); + INVx1_ASAP7_75t_R \U$2174 ( + .A(\con$3400 ), + .Y(\c$3401 ) + ); + INVx1_ASAP7_75t_R \U$2175 ( + .A(\sn$3402 ), + .Y(\s$3403 ) + ); + INVx1_ASAP7_75t_R \U$2176 ( + .A(\con$3404 ), + .Y(\c$3405 ) + ); + INVx1_ASAP7_75t_R \U$2177 ( + .A(\sn$3406 ), + .Y(\s$3407 ) + ); + INVx1_ASAP7_75t_R \U$2178 ( + .A(\con$3408 ), + .Y(\c$3409 ) + ); + INVx1_ASAP7_75t_R \U$2179 ( + .A(\sn$3410 ), + .Y(\s$3411 ) + ); + INVx1_ASAP7_75t_R \U$2180 ( + .A(\con$3412 ), + .Y(\c$3413 ) + ); + INVx1_ASAP7_75t_R \U$2181 ( + .A(\sn$3414 ), + .Y(\s$3415 ) + ); + INVx1_ASAP7_75t_R \U$2182 ( + .A(\con$3416 ), + .Y(\c$3417 ) + ); + INVx1_ASAP7_75t_R \U$2183 ( + .A(\sn$3418 ), + .Y(\s$3419 ) + ); + INVx1_ASAP7_75t_R \U$2184 ( + .A(\con$3420 ), + .Y(\c$3421 ) + ); + INVx1_ASAP7_75t_R \U$2185 ( + .A(\sn$3422 ), + .Y(\s$3423 ) + ); + INVx1_ASAP7_75t_R \U$2186 ( + .A(\con$3424 ), + .Y(\c$3425 ) + ); + INVx1_ASAP7_75t_R \U$2187 ( + .A(\sn$3426 ), + .Y(\s$3427 ) + ); + INVx1_ASAP7_75t_R \U$2188 ( + .A(\con$3428 ), + .Y(\c$3429 ) + ); + INVx1_ASAP7_75t_R \U$2189 ( + .A(\sn$3430 ), + .Y(\s$3431 ) + ); + INVx1_ASAP7_75t_R \U$2190 ( + .A(\con$3432 ), + .Y(\c$3433 ) + ); + INVx1_ASAP7_75t_R \U$2191 ( + .A(\sn$3434 ), + .Y(\s$3435 ) + ); + INVx1_ASAP7_75t_R \U$2192 ( + .A(\con$3436 ), + .Y(\c$3437 ) + ); + INVx1_ASAP7_75t_R \U$2193 ( + .A(\sn$3438 ), + .Y(\s$3439 ) + ); + INVx1_ASAP7_75t_R \U$2194 ( + .A(\con$3440 ), + .Y(\c$3441 ) + ); + INVx1_ASAP7_75t_R \U$2195 ( + .A(\sn$3442 ), + .Y(\s$3443 ) + ); + INVx1_ASAP7_75t_R \U$2196 ( + .A(\con$3444 ), + .Y(\c$3445 ) + ); + INVx1_ASAP7_75t_R \U$2197 ( + .A(\sn$3446 ), + .Y(\s$3447 ) + ); + INVx1_ASAP7_75t_R \U$2198 ( + .A(\con$3448 ), + .Y(\c$3449 ) + ); + INVx1_ASAP7_75t_R \U$2199 ( + .A(\sn$3450 ), + .Y(\s$3451 ) + ); + INVx1_ASAP7_75t_R \U$2200 ( + .A(\con$3452 ), + .Y(\c$3453 ) + ); + INVx1_ASAP7_75t_R \U$2201 ( + .A(\sn$3454 ), + .Y(\s$3455 ) + ); + INVx1_ASAP7_75t_R \U$2202 ( + .A(\con$3456 ), + .Y(\c$3457 ) + ); + INVx1_ASAP7_75t_R \U$2203 ( + .A(\sn$3458 ), + .Y(\s$3459 ) + ); + INVx1_ASAP7_75t_R \U$2204 ( + .A(\con$3460 ), + .Y(\c$3461 ) + ); + INVx1_ASAP7_75t_R \U$2205 ( + .A(\sn$3462 ), + .Y(\s$3463 ) + ); + INVx1_ASAP7_75t_R \U$2206 ( + .A(\con$3464 ), + .Y(\c$3465 ) + ); + INVx1_ASAP7_75t_R \U$2207 ( + .A(\sn$3466 ), + .Y(\s$3467 ) + ); + INVx1_ASAP7_75t_R \U$2208 ( + .A(\con$3468 ), + .Y(\c$3469 ) + ); + INVx1_ASAP7_75t_R \U$2209 ( + .A(\sn$3470 ), + .Y(\s$3471 ) + ); + INVx1_ASAP7_75t_R \U$2210 ( + .A(\con$3472 ), + .Y(\c$3473 ) + ); + INVx1_ASAP7_75t_R \U$2211 ( + .A(\sn$3474 ), + .Y(\s$3475 ) + ); + INVx1_ASAP7_75t_R \U$2212 ( + .A(\con$3476 ), + .Y(\c$3477 ) + ); + INVx1_ASAP7_75t_R \U$2213 ( + .A(\sn$3478 ), + .Y(\s$3479 ) + ); + INVx1_ASAP7_75t_R \U$2214 ( + .A(\con$3480 ), + .Y(\c$3481 ) + ); + INVx1_ASAP7_75t_R \U$2215 ( + .A(\sn$3482 ), + .Y(\s$3483 ) + ); + INVx1_ASAP7_75t_R \U$2216 ( + .A(\con$3484 ), + .Y(\c$3485 ) + ); + INVx1_ASAP7_75t_R \U$2217 ( + .A(\sn$3486 ), + .Y(\s$3487 ) + ); + INVx1_ASAP7_75t_R \U$2218 ( + .A(\con$3488 ), + .Y(\c$3489 ) + ); + INVx1_ASAP7_75t_R \U$2219 ( + .A(\sn$3490 ), + .Y(\s$3491 ) + ); + INVx1_ASAP7_75t_R \U$2220 ( + .A(\con$3492 ), + .Y(\c$3493 ) + ); + INVx1_ASAP7_75t_R \U$2221 ( + .A(\sn$3494 ), + .Y(\s$3495 ) + ); + INVx1_ASAP7_75t_R \U$2222 ( + .A(\con$3496 ), + .Y(\c$3497 ) + ); + INVx1_ASAP7_75t_R \U$2223 ( + .A(\sn$3498 ), + .Y(\s$3499 ) + ); + INVx1_ASAP7_75t_R \U$2224 ( + .A(\con$3500 ), + .Y(\c$3501 ) + ); + INVx1_ASAP7_75t_R \U$2225 ( + .A(\sn$3502 ), + .Y(\s$3503 ) + ); + INVx1_ASAP7_75t_R \U$2226 ( + .A(\con$3504 ), + .Y(\c$3505 ) + ); + INVx1_ASAP7_75t_R \U$2227 ( + .A(\sn$3506 ), + .Y(\s$3507 ) + ); + INVx1_ASAP7_75t_R \U$2228 ( + .A(\con$3508 ), + .Y(\c$3509 ) + ); + INVx1_ASAP7_75t_R \U$2229 ( + .A(\sn$3510 ), + .Y(\s$3511 ) + ); + INVx1_ASAP7_75t_R \U$2230 ( + .A(\con$3512 ), + .Y(\c$3513 ) + ); + INVx1_ASAP7_75t_R \U$2231 ( + .A(\sn$3514 ), + .Y(\s$3515 ) + ); + INVx1_ASAP7_75t_R \U$2232 ( + .A(\con$3516 ), + .Y(\c$3517 ) + ); + INVx1_ASAP7_75t_R \U$2233 ( + .A(\sn$3518 ), + .Y(\s$3519 ) + ); + INVx1_ASAP7_75t_R \U$2234 ( + .A(\con$3520 ), + .Y(\c$3521 ) + ); + INVx1_ASAP7_75t_R \U$2235 ( + .A(\sn$3522 ), + .Y(\s$3523 ) + ); + INVx1_ASAP7_75t_R \U$2236 ( + .A(\con$3524 ), + .Y(\c$3525 ) + ); + INVx1_ASAP7_75t_R \U$2237 ( + .A(\sn$3526 ), + .Y(\s$3527 ) + ); + INVx1_ASAP7_75t_R \U$2238 ( + .A(\con$3528 ), + .Y(\c$3529 ) + ); + INVx1_ASAP7_75t_R \U$2239 ( + .A(\sn$3530 ), + .Y(\s$3531 ) + ); + INVx1_ASAP7_75t_R \U$2240 ( + .A(\con$3532 ), + .Y(\c$3533 ) + ); + INVx1_ASAP7_75t_R \U$2241 ( + .A(\sn$3534 ), + .Y(\s$3535 ) + ); + INVx1_ASAP7_75t_R \U$2242 ( + .A(\con$3536 ), + .Y(\c$3537 ) + ); + INVx1_ASAP7_75t_R \U$2243 ( + .A(\sn$3538 ), + .Y(\s$3539 ) + ); + INVx1_ASAP7_75t_R \U$2244 ( + .A(\con$3540 ), + .Y(\c$3541 ) + ); + INVx1_ASAP7_75t_R \U$2245 ( + .A(\sn$3542 ), + .Y(\s$3543 ) + ); + INVx1_ASAP7_75t_R \U$2246 ( + .A(\con$3544 ), + .Y(\c$3545 ) + ); + INVx1_ASAP7_75t_R \U$2247 ( + .A(\sn$3546 ), + .Y(\s$3547 ) + ); + INVx1_ASAP7_75t_R \U$2248 ( + .A(\con$3548 ), + .Y(\c$3549 ) + ); + INVx1_ASAP7_75t_R \U$2249 ( + .A(\sn$3550 ), + .Y(\s$3551 ) + ); + INVx1_ASAP7_75t_R \U$2250 ( + .A(\con$3552 ), + .Y(\c$3553 ) + ); + INVx1_ASAP7_75t_R \U$2251 ( + .A(\sn$3554 ), + .Y(\s$3555 ) + ); + INVx1_ASAP7_75t_R \U$2252 ( + .A(\con$3556 ), + .Y(\c$3557 ) + ); + INVx1_ASAP7_75t_R \U$2253 ( + .A(\sn$3558 ), + .Y(\s$3559 ) + ); + INVx1_ASAP7_75t_R \U$2254 ( + .A(\con$3560 ), + .Y(\c$3561 ) + ); + INVx1_ASAP7_75t_R \U$2255 ( + .A(\sn$3562 ), + .Y(\s$3563 ) + ); + INVx1_ASAP7_75t_R \U$2256 ( + .A(\con$3564 ), + .Y(\c$3565 ) + ); + INVx1_ASAP7_75t_R \U$2257 ( + .A(\sn$3566 ), + .Y(\s$3567 ) + ); + INVx1_ASAP7_75t_R \U$2258 ( + .A(\con$3568 ), + .Y(\c$3569 ) + ); + INVx1_ASAP7_75t_R \U$2259 ( + .A(\sn$3570 ), + .Y(\s$3571 ) + ); + INVx1_ASAP7_75t_R \U$2260 ( + .A(\con$3572 ), + .Y(\c$3573 ) + ); + INVx1_ASAP7_75t_R \U$2261 ( + .A(\sn$3574 ), + .Y(\s$3575 ) + ); + INVx1_ASAP7_75t_R \U$2262 ( + .A(\con$3576 ), + .Y(\c$3577 ) + ); + INVx1_ASAP7_75t_R \U$2263 ( + .A(\sn$3578 ), + .Y(\s$3579 ) + ); + INVx1_ASAP7_75t_R \U$2264 ( + .A(\con$3580 ), + .Y(\c$3581 ) + ); + INVx1_ASAP7_75t_R \U$2265 ( + .A(\sn$3582 ), + .Y(\s$3583 ) + ); + INVx1_ASAP7_75t_R \U$2266 ( + .A(\con$3584 ), + .Y(\c$3585 ) + ); + INVx1_ASAP7_75t_R \U$2267 ( + .A(\sn$3586 ), + .Y(\s$3587 ) + ); + INVx1_ASAP7_75t_R \U$2268 ( + .A(\con$3588 ), + .Y(\c$3589 ) + ); + INVx1_ASAP7_75t_R \U$2269 ( + .A(\sn$3590 ), + .Y(\s$3591 ) + ); + INVx1_ASAP7_75t_R \U$2270 ( + .A(\con$3592 ), + .Y(\c$3593 ) + ); + INVx1_ASAP7_75t_R \U$2271 ( + .A(\sn$3594 ), + .Y(\s$3595 ) + ); + INVx1_ASAP7_75t_R \U$2272 ( + .A(\con$3596 ), + .Y(\c$3597 ) + ); + INVx1_ASAP7_75t_R \U$2273 ( + .A(\sn$3598 ), + .Y(\s$3599 ) + ); + INVx1_ASAP7_75t_R \U$2274 ( + .A(\con$3600 ), + .Y(\c$3601 ) + ); + INVx1_ASAP7_75t_R \U$2275 ( + .A(\sn$3602 ), + .Y(\s$3603 ) + ); + INVx1_ASAP7_75t_R \U$2276 ( + .A(\con$3604 ), + .Y(\c$3605 ) + ); + INVx1_ASAP7_75t_R \U$2277 ( + .A(\sn$3606 ), + .Y(\s$3607 ) + ); + INVx1_ASAP7_75t_R \U$2278 ( + .A(\con$3608 ), + .Y(\c$3609 ) + ); + INVx1_ASAP7_75t_R \U$2279 ( + .A(\sn$3610 ), + .Y(\s$3611 ) + ); + INVx1_ASAP7_75t_R \U$2280 ( + .A(\con$3612 ), + .Y(\c$3613 ) + ); + INVx1_ASAP7_75t_R \U$2281 ( + .A(\sn$3614 ), + .Y(\s$3615 ) + ); + INVx1_ASAP7_75t_R \U$2282 ( + .A(\con$3616 ), + .Y(\c$3617 ) + ); + INVx1_ASAP7_75t_R \U$2283 ( + .A(\sn$3618 ), + .Y(\s$3619 ) + ); + INVx1_ASAP7_75t_R \U$2284 ( + .A(\con$3620 ), + .Y(\c$3621 ) + ); + INVx1_ASAP7_75t_R \U$2285 ( + .A(\sn$3622 ), + .Y(\s$3623 ) + ); + INVx1_ASAP7_75t_R \U$2286 ( + .A(\con$3624 ), + .Y(\c$3625 ) + ); + INVx1_ASAP7_75t_R \U$2287 ( + .A(\sn$3626 ), + .Y(\s$3627 ) + ); + INVx1_ASAP7_75t_R \U$2288 ( + .A(\con$3628 ), + .Y(\c$3629 ) + ); + INVx1_ASAP7_75t_R \U$2289 ( + .A(\sn$3630 ), + .Y(\s$3631 ) + ); + INVx1_ASAP7_75t_R \U$2290 ( + .A(\con$3632 ), + .Y(\c$3633 ) + ); + INVx1_ASAP7_75t_R \U$2291 ( + .A(\sn$3634 ), + .Y(\s$3635 ) + ); + INVx1_ASAP7_75t_R \U$2292 ( + .A(\con$3636 ), + .Y(\c$3637 ) + ); + INVx1_ASAP7_75t_R \U$2293 ( + .A(\sn$3638 ), + .Y(\s$3639 ) + ); + INVx1_ASAP7_75t_R \U$2294 ( + .A(\con$3640 ), + .Y(\c$3641 ) + ); + INVx1_ASAP7_75t_R \U$2295 ( + .A(\sn$3642 ), + .Y(\s$3643 ) + ); + INVx1_ASAP7_75t_R \U$2296 ( + .A(\con$3644 ), + .Y(\c$3645 ) + ); + INVx1_ASAP7_75t_R \U$2297 ( + .A(\sn$3646 ), + .Y(\s$3647 ) + ); + INVx1_ASAP7_75t_R \U$2298 ( + .A(\con$3648 ), + .Y(\c$3649 ) + ); + INVx1_ASAP7_75t_R \U$2299 ( + .A(\sn$3650 ), + .Y(\s$3651 ) + ); + INVx1_ASAP7_75t_R \U$2300 ( + .A(\con$3652 ), + .Y(\c$3653 ) + ); + INVx1_ASAP7_75t_R \U$2301 ( + .A(\sn$3654 ), + .Y(\s$3655 ) + ); + INVx1_ASAP7_75t_R \U$2302 ( + .A(\con$3656 ), + .Y(\c$3657 ) + ); + INVx1_ASAP7_75t_R \U$2303 ( + .A(\sn$3658 ), + .Y(\s$3659 ) + ); + INVx1_ASAP7_75t_R \U$2304 ( + .A(\con$3660 ), + .Y(\c$3661 ) + ); + INVx1_ASAP7_75t_R \U$2305 ( + .A(\sn$3662 ), + .Y(\s$3663 ) + ); + INVx1_ASAP7_75t_R \U$2306 ( + .A(\con$3664 ), + .Y(\c$3665 ) + ); + INVx1_ASAP7_75t_R \U$2307 ( + .A(\sn$3666 ), + .Y(\s$3667 ) + ); + INVx1_ASAP7_75t_R \U$2308 ( + .A(\con$3668 ), + .Y(\c$3669 ) + ); + INVx1_ASAP7_75t_R \U$2309 ( + .A(\sn$3670 ), + .Y(\s$3671 ) + ); + INVx1_ASAP7_75t_R \U$2310 ( + .A(\con$3672 ), + .Y(\c$3673 ) + ); + INVx1_ASAP7_75t_R \U$2311 ( + .A(\sn$3674 ), + .Y(\s$3675 ) + ); + INVx1_ASAP7_75t_R \U$2312 ( + .A(\con$3676 ), + .Y(\c$3677 ) + ); + INVx1_ASAP7_75t_R \U$2313 ( + .A(\sn$3678 ), + .Y(\s$3679 ) + ); + INVx1_ASAP7_75t_R \U$2314 ( + .A(\con$3680 ), + .Y(\c$3681 ) + ); + INVx1_ASAP7_75t_R \U$2315 ( + .A(\sn$3682 ), + .Y(\s$3683 ) + ); + INVx1_ASAP7_75t_R \U$2316 ( + .A(\con$3684 ), + .Y(\c$3685 ) + ); + INVx1_ASAP7_75t_R \U$2317 ( + .A(\sn$3686 ), + .Y(\s$3687 ) + ); + INVx1_ASAP7_75t_R \U$2318 ( + .A(\con$3688 ), + .Y(\c$3689 ) + ); + INVx1_ASAP7_75t_R \U$2319 ( + .A(\sn$3690 ), + .Y(\s$3691 ) + ); + INVx1_ASAP7_75t_R \U$2320 ( + .A(\con$3692 ), + .Y(\c$3693 ) + ); + INVx1_ASAP7_75t_R \U$2321 ( + .A(\sn$3694 ), + .Y(\s$3695 ) + ); + INVx1_ASAP7_75t_R \U$2322 ( + .A(\con$3696 ), + .Y(\c$3697 ) + ); + INVx1_ASAP7_75t_R \U$2323 ( + .A(\sn$3698 ), + .Y(\s$3699 ) + ); + INVx1_ASAP7_75t_R \U$2324 ( + .A(\con$3700 ), + .Y(\c$3701 ) + ); + INVx1_ASAP7_75t_R \U$2325 ( + .A(\sn$3702 ), + .Y(\s$3703 ) + ); + INVx1_ASAP7_75t_R \U$2326 ( + .A(\con$3704 ), + .Y(\c$3705 ) + ); + INVx1_ASAP7_75t_R \U$2327 ( + .A(\sn$3706 ), + .Y(\s$3707 ) + ); + INVx1_ASAP7_75t_R \U$2328 ( + .A(\con$3708 ), + .Y(\c$3709 ) + ); + INVx1_ASAP7_75t_R \U$2329 ( + .A(\sn$3710 ), + .Y(\s$3711 ) + ); + INVx1_ASAP7_75t_R \U$2330 ( + .A(\con$3712 ), + .Y(\c$3713 ) + ); + INVx1_ASAP7_75t_R \U$2331 ( + .A(\sn$3714 ), + .Y(\s$3715 ) + ); + INVx1_ASAP7_75t_R \U$2332 ( + .A(\con$3716 ), + .Y(\c$3717 ) + ); + INVx1_ASAP7_75t_R \U$2333 ( + .A(\sn$3718 ), + .Y(\s$3719 ) + ); + INVx1_ASAP7_75t_R \U$2334 ( + .A(\con$3720 ), + .Y(\c$3721 ) + ); + INVx1_ASAP7_75t_R \U$2335 ( + .A(\sn$3722 ), + .Y(\s$3723 ) + ); + INVx1_ASAP7_75t_R \U$2336 ( + .A(\con$3724 ), + .Y(\c$3725 ) + ); + INVx1_ASAP7_75t_R \U$2337 ( + .A(\sn$3726 ), + .Y(\s$3727 ) + ); + INVx1_ASAP7_75t_R \U$2338 ( + .A(\con$3728 ), + .Y(\c$3729 ) + ); + INVx1_ASAP7_75t_R \U$2339 ( + .A(\sn$3730 ), + .Y(\s$3731 ) + ); + INVx1_ASAP7_75t_R \U$2340 ( + .A(\con$3732 ), + .Y(\c$3733 ) + ); + INVx1_ASAP7_75t_R \U$2341 ( + .A(\sn$3734 ), + .Y(\s$3735 ) + ); + INVx1_ASAP7_75t_R \U$2342 ( + .A(\con$3736 ), + .Y(\c$3737 ) + ); + INVx1_ASAP7_75t_R \U$2343 ( + .A(\sn$3738 ), + .Y(\s$3739 ) + ); + INVx1_ASAP7_75t_R \U$2344 ( + .A(\con$3740 ), + .Y(\c$3741 ) + ); + INVx1_ASAP7_75t_R \U$2345 ( + .A(\sn$3742 ), + .Y(\s$3743 ) + ); + INVx1_ASAP7_75t_R \U$2346 ( + .A(\con$3744 ), + .Y(\c$3745 ) + ); + INVx1_ASAP7_75t_R \U$2347 ( + .A(\sn$3746 ), + .Y(\s$3747 ) + ); + INVx1_ASAP7_75t_R \U$2348 ( + .A(\con$3748 ), + .Y(\c$3749 ) + ); + INVx1_ASAP7_75t_R \U$2349 ( + .A(\sn$3750 ), + .Y(\s$3751 ) + ); + INVx1_ASAP7_75t_R \U$2350 ( + .A(\con$3752 ), + .Y(\c$3753 ) + ); + INVx1_ASAP7_75t_R \U$2351 ( + .A(\sn$3754 ), + .Y(\s$3755 ) + ); + INVx1_ASAP7_75t_R \U$2352 ( + .A(\con$3756 ), + .Y(\c$3757 ) + ); + INVx1_ASAP7_75t_R \U$2353 ( + .A(\sn$3758 ), + .Y(\s$3759 ) + ); + INVx1_ASAP7_75t_R \U$2354 ( + .A(\con$3760 ), + .Y(\c$3761 ) + ); + INVx1_ASAP7_75t_R \U$2355 ( + .A(\sn$3762 ), + .Y(\s$3763 ) + ); + INVx1_ASAP7_75t_R \U$2356 ( + .A(\con$3764 ), + .Y(\c$3765 ) + ); + INVx1_ASAP7_75t_R \U$2357 ( + .A(\sn$3766 ), + .Y(\s$3767 ) + ); + INVx1_ASAP7_75t_R \U$2358 ( + .A(\con$3768 ), + .Y(\c$3769 ) + ); + INVx1_ASAP7_75t_R \U$2359 ( + .A(\sn$3770 ), + .Y(\s$3771 ) + ); + INVx1_ASAP7_75t_R \U$2360 ( + .A(\con$3772 ), + .Y(\c$3773 ) + ); + INVx1_ASAP7_75t_R \U$2361 ( + .A(\sn$3774 ), + .Y(\s$3775 ) + ); + INVx1_ASAP7_75t_R \U$2362 ( + .A(\con$3776 ), + .Y(\c$3777 ) + ); + INVx1_ASAP7_75t_R \U$2363 ( + .A(\sn$3778 ), + .Y(\s$3779 ) + ); + INVx1_ASAP7_75t_R \U$2364 ( + .A(\con$3780 ), + .Y(\c$3781 ) + ); + INVx1_ASAP7_75t_R \U$2365 ( + .A(\sn$3782 ), + .Y(\s$3783 ) + ); + INVx1_ASAP7_75t_R \U$2366 ( + .A(\con$3784 ), + .Y(\c$3785 ) + ); + INVx1_ASAP7_75t_R \U$2367 ( + .A(\sn$3786 ), + .Y(\s$3787 ) + ); + INVx1_ASAP7_75t_R \U$2368 ( + .A(\con$3788 ), + .Y(\c$3789 ) + ); + INVx1_ASAP7_75t_R \U$2369 ( + .A(\sn$3790 ), + .Y(\s$3791 ) + ); + INVx1_ASAP7_75t_R \U$2370 ( + .A(\con$3792 ), + .Y(\c$3793 ) + ); + INVx1_ASAP7_75t_R \U$2371 ( + .A(\sn$3794 ), + .Y(\s$3795 ) + ); + INVx1_ASAP7_75t_R \U$2372 ( + .A(\con$3796 ), + .Y(\c$3797 ) + ); + INVx1_ASAP7_75t_R \U$2373 ( + .A(\sn$3798 ), + .Y(\s$3799 ) + ); + INVx1_ASAP7_75t_R \U$2374 ( + .A(\con$3800 ), + .Y(\c$3801 ) + ); + INVx1_ASAP7_75t_R \U$2375 ( + .A(\sn$3802 ), + .Y(\s$3803 ) + ); + INVx1_ASAP7_75t_R \U$2376 ( + .A(\con$3804 ), + .Y(\c$3805 ) + ); + INVx1_ASAP7_75t_R \U$2377 ( + .A(\sn$3806 ), + .Y(\s$3807 ) + ); + INVx1_ASAP7_75t_R \U$2378 ( + .A(\con$3808 ), + .Y(\c$3809 ) + ); + INVx1_ASAP7_75t_R \U$2379 ( + .A(\sn$3810 ), + .Y(\s$3811 ) + ); + INVx1_ASAP7_75t_R \U$2380 ( + .A(\con$3812 ), + .Y(\c$3813 ) + ); + INVx1_ASAP7_75t_R \U$2381 ( + .A(\sn$3814 ), + .Y(\s$3815 ) + ); + INVx1_ASAP7_75t_R \U$2382 ( + .A(\con$3816 ), + .Y(\c$3817 ) + ); + INVx1_ASAP7_75t_R \U$2383 ( + .A(\sn$3818 ), + .Y(\s$3819 ) + ); + INVx1_ASAP7_75t_R \U$2384 ( + .A(\con$3820 ), + .Y(\c$3821 ) + ); + INVx1_ASAP7_75t_R \U$2385 ( + .A(\sn$3822 ), + .Y(\s$3823 ) + ); + INVx1_ASAP7_75t_R \U$2386 ( + .A(\con$3824 ), + .Y(\c$3825 ) + ); + INVx1_ASAP7_75t_R \U$2387 ( + .A(\sn$3826 ), + .Y(\s$3827 ) + ); + INVx1_ASAP7_75t_R \U$2388 ( + .A(\con$3828 ), + .Y(\c$3829 ) + ); + INVx1_ASAP7_75t_R \U$2389 ( + .A(\sn$3830 ), + .Y(\s$3831 ) + ); + INVx1_ASAP7_75t_R \U$2390 ( + .A(\con$3832 ), + .Y(\c$3833 ) + ); + INVx1_ASAP7_75t_R \U$2391 ( + .A(\sn$3834 ), + .Y(\s$3835 ) + ); + INVx1_ASAP7_75t_R \U$2392 ( + .A(\con$3836 ), + .Y(\c$3837 ) + ); + INVx1_ASAP7_75t_R \U$2393 ( + .A(\sn$3838 ), + .Y(\s$3839 ) + ); + INVx1_ASAP7_75t_R \U$2394 ( + .A(\con$3840 ), + .Y(\c$3841 ) + ); + INVx1_ASAP7_75t_R \U$2395 ( + .A(\sn$3842 ), + .Y(\s$3843 ) + ); + INVx1_ASAP7_75t_R \U$2396 ( + .A(\con$3844 ), + .Y(\c$3845 ) + ); + INVx1_ASAP7_75t_R \U$2397 ( + .A(\sn$3846 ), + .Y(\s$3847 ) + ); + INVx1_ASAP7_75t_R \U$2398 ( + .A(\con$3848 ), + .Y(\c$3849 ) + ); + INVx1_ASAP7_75t_R \U$2399 ( + .A(\sn$3850 ), + .Y(\s$3851 ) + ); + INVx1_ASAP7_75t_R \U$2400 ( + .A(\con$3852 ), + .Y(\c$3853 ) + ); + INVx1_ASAP7_75t_R \U$2401 ( + .A(\sn$3854 ), + .Y(\s$3855 ) + ); + INVx1_ASAP7_75t_R \U$2402 ( + .A(\con$3856 ), + .Y(\c$3857 ) + ); + INVx1_ASAP7_75t_R \U$2403 ( + .A(\sn$3858 ), + .Y(\s$3859 ) + ); + INVx1_ASAP7_75t_R \U$2404 ( + .A(\con$3860 ), + .Y(\c$3861 ) + ); + INVx1_ASAP7_75t_R \U$2405 ( + .A(\sn$3862 ), + .Y(\s$3863 ) + ); + INVx1_ASAP7_75t_R \U$2406 ( + .A(\con$3864 ), + .Y(\c$3865 ) + ); + INVx1_ASAP7_75t_R \U$2407 ( + .A(\sn$3866 ), + .Y(\s$3867 ) + ); + INVx1_ASAP7_75t_R \U$2408 ( + .A(\con$3868 ), + .Y(\c$3869 ) + ); + INVx1_ASAP7_75t_R \U$2409 ( + .A(\sn$3870 ), + .Y(\s$3871 ) + ); + INVx1_ASAP7_75t_R \U$2410 ( + .A(\con$3872 ), + .Y(\c$3873 ) + ); + INVx1_ASAP7_75t_R \U$2411 ( + .A(\sn$3874 ), + .Y(\s$3875 ) + ); + INVx1_ASAP7_75t_R \U$2412 ( + .A(\con$3876 ), + .Y(\c$3877 ) + ); + INVx1_ASAP7_75t_R \U$2413 ( + .A(\sn$3878 ), + .Y(\s$3879 ) + ); + INVx1_ASAP7_75t_R \U$2414 ( + .A(\con$3880 ), + .Y(\c$3881 ) + ); + INVx1_ASAP7_75t_R \U$2415 ( + .A(\sn$3882 ), + .Y(\s$3883 ) + ); + INVx1_ASAP7_75t_R \U$2416 ( + .A(\con$3884 ), + .Y(\c$3885 ) + ); + INVx1_ASAP7_75t_R \U$2417 ( + .A(\sn$3886 ), + .Y(\s$3887 ) + ); + INVx1_ASAP7_75t_R \U$2418 ( + .A(\con$3888 ), + .Y(\c$3889 ) + ); + INVx1_ASAP7_75t_R \U$2419 ( + .A(\sn$3890 ), + .Y(\s$3891 ) + ); + INVx1_ASAP7_75t_R \U$2420 ( + .A(\con$3892 ), + .Y(\c$3893 ) + ); + INVx1_ASAP7_75t_R \U$2421 ( + .A(\sn$3894 ), + .Y(\s$3895 ) + ); + INVx1_ASAP7_75t_R \U$2422 ( + .A(\con$3896 ), + .Y(\c$3897 ) + ); + INVx1_ASAP7_75t_R \U$2423 ( + .A(\sn$3898 ), + .Y(\s$3899 ) + ); + INVx1_ASAP7_75t_R \U$2424 ( + .A(\con$3900 ), + .Y(\c$3901 ) + ); + INVx1_ASAP7_75t_R \U$2425 ( + .A(\sn$3902 ), + .Y(\s$3903 ) + ); + INVx1_ASAP7_75t_R \U$2426 ( + .A(\con$3904 ), + .Y(\c$3905 ) + ); + INVx1_ASAP7_75t_R \U$2427 ( + .A(\sn$3906 ), + .Y(\s$3907 ) + ); + INVx1_ASAP7_75t_R \U$2428 ( + .A(\con$3908 ), + .Y(\c$3909 ) + ); + INVx1_ASAP7_75t_R \U$2429 ( + .A(\sn$3910 ), + .Y(\s$3911 ) + ); + INVx1_ASAP7_75t_R \U$2430 ( + .A(\con$3912 ), + .Y(\c$3913 ) + ); + INVx1_ASAP7_75t_R \U$2431 ( + .A(\sn$3914 ), + .Y(\s$3915 ) + ); + INVx1_ASAP7_75t_R \U$2432 ( + .A(\con$3916 ), + .Y(\c$3917 ) + ); + INVx1_ASAP7_75t_R \U$2433 ( + .A(\sn$3918 ), + .Y(\s$3919 ) + ); + INVx1_ASAP7_75t_R \U$2434 ( + .A(\con$3920 ), + .Y(\c$3921 ) + ); + INVx1_ASAP7_75t_R \U$2435 ( + .A(\sn$3922 ), + .Y(\s$3923 ) + ); + INVx1_ASAP7_75t_R \U$2436 ( + .A(\con$3924 ), + .Y(\c$3925 ) + ); + INVx1_ASAP7_75t_R \U$2437 ( + .A(\sn$3926 ), + .Y(\s$3927 ) + ); + INVx1_ASAP7_75t_R \U$2438 ( + .A(\con$3928 ), + .Y(\c$3929 ) + ); + INVx1_ASAP7_75t_R \U$2439 ( + .A(\sn$3930 ), + .Y(\s$3931 ) + ); + INVx1_ASAP7_75t_R \U$2440 ( + .A(\con$3932 ), + .Y(\c$3933 ) + ); + INVx1_ASAP7_75t_R \U$2441 ( + .A(\sn$3934 ), + .Y(\s$3935 ) + ); + INVx1_ASAP7_75t_R \U$2442 ( + .A(\con$3936 ), + .Y(\c$3937 ) + ); + INVx1_ASAP7_75t_R \U$2443 ( + .A(\sn$3938 ), + .Y(\s$3939 ) + ); + INVx1_ASAP7_75t_R \U$2444 ( + .A(\con$3940 ), + .Y(\c$3941 ) + ); + INVx1_ASAP7_75t_R \U$2445 ( + .A(\sn$3942 ), + .Y(\s$3943 ) + ); + INVx1_ASAP7_75t_R \U$2446 ( + .A(\con$3944 ), + .Y(\c$3945 ) + ); + INVx1_ASAP7_75t_R \U$2447 ( + .A(\sn$3946 ), + .Y(\s$3947 ) + ); + INVx1_ASAP7_75t_R \U$2448 ( + .A(\con$3948 ), + .Y(\c$3949 ) + ); + INVx1_ASAP7_75t_R \U$2449 ( + .A(\sn$3950 ), + .Y(\s$3951 ) + ); + INVx1_ASAP7_75t_R \U$2450 ( + .A(\con$3952 ), + .Y(\c$3953 ) + ); + INVx1_ASAP7_75t_R \U$2451 ( + .A(\sn$3954 ), + .Y(\s$3955 ) + ); + INVx1_ASAP7_75t_R \U$2452 ( + .A(\con$3956 ), + .Y(\c$3957 ) + ); + INVx1_ASAP7_75t_R \U$2453 ( + .A(\sn$3958 ), + .Y(\s$3959 ) + ); + INVx1_ASAP7_75t_R \U$2454 ( + .A(\con$3960 ), + .Y(\c$3961 ) + ); + INVx1_ASAP7_75t_R \U$2455 ( + .A(\sn$3962 ), + .Y(\s$3963 ) + ); + INVx1_ASAP7_75t_R \U$2456 ( + .A(\con$3964 ), + .Y(\c$3965 ) + ); + INVx1_ASAP7_75t_R \U$2457 ( + .A(\sn$3966 ), + .Y(\s$3967 ) + ); + INVx1_ASAP7_75t_R \U$2458 ( + .A(\con$3968 ), + .Y(\c$3969 ) + ); + INVx1_ASAP7_75t_R \U$2459 ( + .A(\sn$3970 ), + .Y(\s$3971 ) + ); + INVx1_ASAP7_75t_R \U$2460 ( + .A(\con$3972 ), + .Y(\c$3973 ) + ); + INVx1_ASAP7_75t_R \U$2461 ( + .A(\sn$3974 ), + .Y(\s$3975 ) + ); + INVx1_ASAP7_75t_R \U$2462 ( + .A(\con$3976 ), + .Y(\c$3977 ) + ); + INVx1_ASAP7_75t_R \U$2463 ( + .A(\sn$3978 ), + .Y(\s$3979 ) + ); + INVx1_ASAP7_75t_R \U$2464 ( + .A(\con$3980 ), + .Y(\c$3981 ) + ); + INVx1_ASAP7_75t_R \U$2465 ( + .A(\sn$3982 ), + .Y(\s$3983 ) + ); + INVx1_ASAP7_75t_R \U$2466 ( + .A(\con$3984 ), + .Y(\c$3985 ) + ); + INVx1_ASAP7_75t_R \U$2467 ( + .A(\sn$3986 ), + .Y(\s$3987 ) + ); + INVx1_ASAP7_75t_R \U$2468 ( + .A(\con$3988 ), + .Y(\c$3989 ) + ); + INVx1_ASAP7_75t_R \U$2469 ( + .A(\sn$3990 ), + .Y(\s$3991 ) + ); + INVx1_ASAP7_75t_R \U$2470 ( + .A(\con$3992 ), + .Y(\c$3993 ) + ); + INVx1_ASAP7_75t_R \U$2471 ( + .A(\sn$3994 ), + .Y(\s$3995 ) + ); + INVx1_ASAP7_75t_R \U$2472 ( + .A(\con$3996 ), + .Y(\c$3997 ) + ); + INVx1_ASAP7_75t_R \U$2473 ( + .A(\sn$3998 ), + .Y(\s$3999 ) + ); + INVx1_ASAP7_75t_R \U$2474 ( + .A(\con$4000 ), + .Y(\c$4001 ) + ); + INVx1_ASAP7_75t_R \U$2475 ( + .A(\sn$4002 ), + .Y(\s$4003 ) + ); + INVx1_ASAP7_75t_R \U$2476 ( + .A(\con$4004 ), + .Y(\c$4005 ) + ); + INVx1_ASAP7_75t_R \U$2477 ( + .A(\sn$4006 ), + .Y(\s$4007 ) + ); + INVx1_ASAP7_75t_R \U$2478 ( + .A(\con$4008 ), + .Y(\c$4009 ) + ); + INVx1_ASAP7_75t_R \U$2479 ( + .A(\sn$4010 ), + .Y(\s$4011 ) + ); + INVx1_ASAP7_75t_R \U$2480 ( + .A(\con$4012 ), + .Y(\c$4013 ) + ); + INVx1_ASAP7_75t_R \U$2481 ( + .A(\sn$4014 ), + .Y(\s$4015 ) + ); + INVx1_ASAP7_75t_R \U$2482 ( + .A(\con$4016 ), + .Y(\c$4017 ) + ); + INVx1_ASAP7_75t_R \U$2483 ( + .A(\sn$4018 ), + .Y(\s$4019 ) + ); + INVx1_ASAP7_75t_R \U$2484 ( + .A(\con$4020 ), + .Y(\c$4021 ) + ); + INVx1_ASAP7_75t_R \U$2485 ( + .A(\sn$4022 ), + .Y(\s$4023 ) + ); + INVx1_ASAP7_75t_R \U$2486 ( + .A(\con$4024 ), + .Y(\c$4025 ) + ); + INVx1_ASAP7_75t_R \U$2487 ( + .A(\sn$4026 ), + .Y(\s$4027 ) + ); + INVx1_ASAP7_75t_R \U$2488 ( + .A(\con$4028 ), + .Y(\c$4029 ) + ); + INVx1_ASAP7_75t_R \U$2489 ( + .A(\sn$4030 ), + .Y(\s$4031 ) + ); + INVx1_ASAP7_75t_R \U$2490 ( + .A(\con$4032 ), + .Y(\c$4033 ) + ); + INVx1_ASAP7_75t_R \U$2491 ( + .A(\sn$4034 ), + .Y(\s$4035 ) + ); + INVx1_ASAP7_75t_R \U$2492 ( + .A(\con$4036 ), + .Y(\c$4037 ) + ); + INVx1_ASAP7_75t_R \U$2493 ( + .A(\sn$4038 ), + .Y(\s$4039 ) + ); + INVx1_ASAP7_75t_R \U$2494 ( + .A(\con$4040 ), + .Y(\c$4041 ) + ); + INVx1_ASAP7_75t_R \U$2495 ( + .A(\sn$4042 ), + .Y(\s$4043 ) + ); + INVx1_ASAP7_75t_R \U$2496 ( + .A(\con$4044 ), + .Y(\c$4045 ) + ); + INVx1_ASAP7_75t_R \U$2497 ( + .A(\sn$4046 ), + .Y(\s$4047 ) + ); + INVx1_ASAP7_75t_R \U$2498 ( + .A(\con$4048 ), + .Y(\c$4049 ) + ); + INVx1_ASAP7_75t_R \U$2499 ( + .A(\sn$4050 ), + .Y(\s$4051 ) + ); + INVx1_ASAP7_75t_R \U$2500 ( + .A(\con$4052 ), + .Y(\c$4053 ) + ); + INVx1_ASAP7_75t_R \U$2501 ( + .A(\sn$4054 ), + .Y(\s$4055 ) + ); + INVx1_ASAP7_75t_R \U$2502 ( + .A(\con$4056 ), + .Y(\c$4057 ) + ); + INVx1_ASAP7_75t_R \U$2503 ( + .A(\sn$4058 ), + .Y(\s$4059 ) + ); + INVx1_ASAP7_75t_R \U$2504 ( + .A(\con$4060 ), + .Y(\c$4061 ) + ); + INVx1_ASAP7_75t_R \U$2505 ( + .A(\sn$4062 ), + .Y(\s$4063 ) + ); + INVx1_ASAP7_75t_R \U$2506 ( + .A(\con$4064 ), + .Y(\c$4065 ) + ); + INVx1_ASAP7_75t_R \U$2507 ( + .A(\sn$4066 ), + .Y(\s$4067 ) + ); + INVx1_ASAP7_75t_R \U$2508 ( + .A(\con$4068 ), + .Y(\c$4069 ) + ); + INVx1_ASAP7_75t_R \U$2509 ( + .A(\sn$4070 ), + .Y(\s$4071 ) + ); + INVx1_ASAP7_75t_R \U$2510 ( + .A(\con$4072 ), + .Y(\c$4073 ) + ); + INVx1_ASAP7_75t_R \U$2511 ( + .A(\sn$4074 ), + .Y(\s$4075 ) + ); + INVx1_ASAP7_75t_R \U$2512 ( + .A(\con$4076 ), + .Y(\c$4077 ) + ); + INVx1_ASAP7_75t_R \U$2513 ( + .A(\sn$4078 ), + .Y(\s$4079 ) + ); + INVx1_ASAP7_75t_R \U$2514 ( + .A(\con$4080 ), + .Y(\c$4081 ) + ); + INVx1_ASAP7_75t_R \U$2515 ( + .A(\sn$4082 ), + .Y(\s$4083 ) + ); + INVx1_ASAP7_75t_R \U$2516 ( + .A(\con$4084 ), + .Y(\c$4085 ) + ); + INVx1_ASAP7_75t_R \U$2517 ( + .A(\sn$4086 ), + .Y(\s$4087 ) + ); + INVx1_ASAP7_75t_R \U$2518 ( + .A(\con$4088 ), + .Y(\c$4089 ) + ); + INVx1_ASAP7_75t_R \U$2519 ( + .A(\sn$4090 ), + .Y(\s$4091 ) + ); + INVx1_ASAP7_75t_R \U$2520 ( + .A(\con$4092 ), + .Y(\c$4093 ) + ); + INVx1_ASAP7_75t_R \U$2521 ( + .A(\sn$4094 ), + .Y(\s$4095 ) + ); + INVx1_ASAP7_75t_R \U$2522 ( + .A(\con$4096 ), + .Y(\c$4097 ) + ); + INVx1_ASAP7_75t_R \U$2523 ( + .A(\sn$4098 ), + .Y(\s$4099 ) + ); + INVx1_ASAP7_75t_R \U$2524 ( + .A(\con$4100 ), + .Y(\c$4101 ) + ); + INVx1_ASAP7_75t_R \U$2525 ( + .A(\sn$4102 ), + .Y(\s$4103 ) + ); + INVx1_ASAP7_75t_R \U$2526 ( + .A(\con$4104 ), + .Y(\c$4105 ) + ); + INVx1_ASAP7_75t_R \U$2527 ( + .A(\sn$4106 ), + .Y(\s$4107 ) + ); + INVx1_ASAP7_75t_R \U$2528 ( + .A(\con$4108 ), + .Y(\c$4109 ) + ); + INVx1_ASAP7_75t_R \U$2529 ( + .A(\sn$4110 ), + .Y(\s$4111 ) + ); + INVx1_ASAP7_75t_R \U$2530 ( + .A(\con$4112 ), + .Y(\c$4113 ) + ); + INVx1_ASAP7_75t_R \U$2531 ( + .A(\sn$4114 ), + .Y(\s$4115 ) + ); + INVx1_ASAP7_75t_R \U$2532 ( + .A(\con$4116 ), + .Y(\c$4117 ) + ); + INVx1_ASAP7_75t_R \U$2533 ( + .A(\sn$4118 ), + .Y(\s$4119 ) + ); + INVx1_ASAP7_75t_R \U$2534 ( + .A(\con$4120 ), + .Y(\c$4121 ) + ); + INVx1_ASAP7_75t_R \U$2535 ( + .A(\sn$4122 ), + .Y(\s$4123 ) + ); + INVx1_ASAP7_75t_R \U$2536 ( + .A(\con$4124 ), + .Y(\c$4125 ) + ); + INVx1_ASAP7_75t_R \U$2537 ( + .A(\sn$4126 ), + .Y(\s$4127 ) + ); + INVx1_ASAP7_75t_R \U$2538 ( + .A(\con$4128 ), + .Y(\c$4129 ) + ); + INVx1_ASAP7_75t_R \U$2539 ( + .A(\sn$4130 ), + .Y(\s$4131 ) + ); + INVx1_ASAP7_75t_R \U$2540 ( + .A(\con$4132 ), + .Y(\c$4133 ) + ); + INVx1_ASAP7_75t_R \U$2541 ( + .A(\sn$4134 ), + .Y(\s$4135 ) + ); + INVx1_ASAP7_75t_R \U$2542 ( + .A(\con$4136 ), + .Y(\c$4137 ) + ); + INVx1_ASAP7_75t_R \U$2543 ( + .A(\sn$4138 ), + .Y(\s$4139 ) + ); + INVx1_ASAP7_75t_R \U$2544 ( + .A(\con$4140 ), + .Y(\c$4141 ) + ); + INVx1_ASAP7_75t_R \U$2545 ( + .A(\sn$4142 ), + .Y(\s$4143 ) + ); + INVx1_ASAP7_75t_R \U$2546 ( + .A(\con$4144 ), + .Y(\c$4145 ) + ); + INVx1_ASAP7_75t_R \U$2547 ( + .A(\sn$4146 ), + .Y(\s$4147 ) + ); + INVx1_ASAP7_75t_R \U$2548 ( + .A(\con$4148 ), + .Y(\c$4149 ) + ); + INVx1_ASAP7_75t_R \U$2549 ( + .A(\sn$4150 ), + .Y(\s$4151 ) + ); + INVx1_ASAP7_75t_R \U$2550 ( + .A(\con$4152 ), + .Y(\c$4153 ) + ); + INVx1_ASAP7_75t_R \U$2551 ( + .A(\sn$4154 ), + .Y(\s$4155 ) + ); + INVx1_ASAP7_75t_R \U$2552 ( + .A(\con$4156 ), + .Y(\c$4157 ) + ); + INVx1_ASAP7_75t_R \U$2553 ( + .A(\sn$4158 ), + .Y(\s$4159 ) + ); + INVx1_ASAP7_75t_R \U$2554 ( + .A(\con$4160 ), + .Y(\c$4161 ) + ); + INVx1_ASAP7_75t_R \U$2555 ( + .A(\sn$4162 ), + .Y(\s$4163 ) + ); + INVx1_ASAP7_75t_R \U$2556 ( + .A(\con$4164 ), + .Y(\c$4165 ) + ); + INVx1_ASAP7_75t_R \U$2557 ( + .A(\sn$4166 ), + .Y(\s$4167 ) + ); + INVx1_ASAP7_75t_R \U$2558 ( + .A(\con$4168 ), + .Y(\c$4169 ) + ); + INVx1_ASAP7_75t_R \U$2559 ( + .A(\sn$4170 ), + .Y(\s$4171 ) + ); + INVx1_ASAP7_75t_R \U$2560 ( + .A(\con$4172 ), + .Y(\c$4173 ) + ); + INVx1_ASAP7_75t_R \U$2561 ( + .A(\sn$4174 ), + .Y(\s$4175 ) + ); + INVx1_ASAP7_75t_R \U$2562 ( + .A(\con$4176 ), + .Y(\c$4177 ) + ); + INVx1_ASAP7_75t_R \U$2563 ( + .A(\sn$4178 ), + .Y(\s$4179 ) + ); + INVx1_ASAP7_75t_R \U$2564 ( + .A(\con$4180 ), + .Y(\c$4181 ) + ); + INVx1_ASAP7_75t_R \U$2565 ( + .A(\sn$4182 ), + .Y(\s$4183 ) + ); + INVx1_ASAP7_75t_R \U$2566 ( + .A(\con$4184 ), + .Y(\c$4185 ) + ); + INVx1_ASAP7_75t_R \U$2567 ( + .A(\sn$4186 ), + .Y(\s$4187 ) + ); + INVx1_ASAP7_75t_R \U$2568 ( + .A(\con$4188 ), + .Y(\c$4189 ) + ); + INVx1_ASAP7_75t_R \U$2569 ( + .A(\sn$4190 ), + .Y(\s$4191 ) + ); + INVx1_ASAP7_75t_R \U$2570 ( + .A(\con$4192 ), + .Y(\c$4193 ) + ); + INVx1_ASAP7_75t_R \U$2571 ( + .A(\sn$4194 ), + .Y(\s$4195 ) + ); + INVx1_ASAP7_75t_R \U$2572 ( + .A(\con$4196 ), + .Y(\c$4197 ) + ); + INVx1_ASAP7_75t_R \U$2573 ( + .A(\sn$4198 ), + .Y(\s$4199 ) + ); + INVx1_ASAP7_75t_R \U$2574 ( + .A(\con$4200 ), + .Y(\c$4201 ) + ); + INVx1_ASAP7_75t_R \U$2575 ( + .A(\sn$4202 ), + .Y(\s$4203 ) + ); + INVx1_ASAP7_75t_R \U$2576 ( + .A(\con$4204 ), + .Y(\c$4205 ) + ); + INVx1_ASAP7_75t_R \U$2577 ( + .A(\sn$4206 ), + .Y(\s$4207 ) + ); + INVx1_ASAP7_75t_R \U$2578 ( + .A(\con$4208 ), + .Y(\c$4209 ) + ); + INVx1_ASAP7_75t_R \U$2579 ( + .A(\sn$4210 ), + .Y(\s$4211 ) + ); + INVx1_ASAP7_75t_R \U$2580 ( + .A(\con$4212 ), + .Y(\c$4213 ) + ); + INVx1_ASAP7_75t_R \U$2581 ( + .A(\sn$4214 ), + .Y(\s$4215 ) + ); + INVx1_ASAP7_75t_R \U$2582 ( + .A(\con$4216 ), + .Y(\c$4217 ) + ); + INVx1_ASAP7_75t_R \U$2583 ( + .A(\sn$4218 ), + .Y(\s$4219 ) + ); + INVx1_ASAP7_75t_R \U$2584 ( + .A(\con$4220 ), + .Y(\c$4221 ) + ); + INVx1_ASAP7_75t_R \U$2585 ( + .A(\sn$4222 ), + .Y(\s$4223 ) + ); + INVx1_ASAP7_75t_R \U$2586 ( + .A(\con$4224 ), + .Y(\c$4225 ) + ); + INVx1_ASAP7_75t_R \U$2587 ( + .A(\sn$4226 ), + .Y(\s$4227 ) + ); + INVx1_ASAP7_75t_R \U$2588 ( + .A(\con$4228 ), + .Y(\c$4229 ) + ); + INVx1_ASAP7_75t_R \U$2589 ( + .A(\sn$4230 ), + .Y(\s$4231 ) + ); + INVx1_ASAP7_75t_R \U$2590 ( + .A(\con$4232 ), + .Y(\c$4233 ) + ); + INVx1_ASAP7_75t_R \U$2591 ( + .A(\sn$4234 ), + .Y(\s$4235 ) + ); + INVx1_ASAP7_75t_R \U$2592 ( + .A(\con$4236 ), + .Y(\c$4237 ) + ); + INVx1_ASAP7_75t_R \U$2593 ( + .A(\sn$4238 ), + .Y(\s$4239 ) + ); + INVx1_ASAP7_75t_R \U$2594 ( + .A(\con$4240 ), + .Y(\c$4241 ) + ); + INVx1_ASAP7_75t_R \U$2595 ( + .A(\sn$4242 ), + .Y(\s$4243 ) + ); + INVx1_ASAP7_75t_R \U$2596 ( + .A(\con$4244 ), + .Y(\c$4245 ) + ); + INVx1_ASAP7_75t_R \U$2597 ( + .A(\sn$4246 ), + .Y(\s$4247 ) + ); + INVx1_ASAP7_75t_R \U$2598 ( + .A(\con$4248 ), + .Y(\c$4249 ) + ); + INVx1_ASAP7_75t_R \U$2599 ( + .A(\sn$4250 ), + .Y(\s$4251 ) + ); + INVx1_ASAP7_75t_R \U$2600 ( + .A(\con$4252 ), + .Y(\c$4253 ) + ); + INVx1_ASAP7_75t_R \U$2601 ( + .A(\sn$4254 ), + .Y(\s$4255 ) + ); + INVx1_ASAP7_75t_R \U$2602 ( + .A(\con$4256 ), + .Y(\c$4257 ) + ); + INVx1_ASAP7_75t_R \U$2603 ( + .A(\sn$4258 ), + .Y(\s$4259 ) + ); + INVx1_ASAP7_75t_R \U$2604 ( + .A(\con$4260 ), + .Y(\c$4261 ) + ); + INVx1_ASAP7_75t_R \U$2605 ( + .A(\sn$4262 ), + .Y(\s$4263 ) + ); + INVx1_ASAP7_75t_R \U$2606 ( + .A(\con$4264 ), + .Y(\c$4265 ) + ); + INVx1_ASAP7_75t_R \U$2607 ( + .A(\sn$4266 ), + .Y(\s$4267 ) + ); + INVx1_ASAP7_75t_R \U$2608 ( + .A(\con$4268 ), + .Y(\c$4269 ) + ); + INVx1_ASAP7_75t_R \U$2609 ( + .A(\sn$4270 ), + .Y(\s$4271 ) + ); + INVx1_ASAP7_75t_R \U$2610 ( + .A(\con$4272 ), + .Y(\c$4273 ) + ); + INVx1_ASAP7_75t_R \U$2611 ( + .A(\sn$4274 ), + .Y(\s$4275 ) + ); + INVx1_ASAP7_75t_R \U$2612 ( + .A(\con$4276 ), + .Y(\c$4277 ) + ); + INVx1_ASAP7_75t_R \U$2613 ( + .A(\sn$4278 ), + .Y(\s$4279 ) + ); + INVx1_ASAP7_75t_R \U$2614 ( + .A(\con$4280 ), + .Y(\c$4281 ) + ); + INVx1_ASAP7_75t_R \U$2615 ( + .A(\sn$4282 ), + .Y(\s$4283 ) + ); + INVx1_ASAP7_75t_R \U$2616 ( + .A(\con$4284 ), + .Y(\c$4285 ) + ); + INVx1_ASAP7_75t_R \U$2617 ( + .A(\sn$4286 ), + .Y(\s$4287 ) + ); + INVx1_ASAP7_75t_R \U$2618 ( + .A(\con$4288 ), + .Y(\c$4289 ) + ); + INVx1_ASAP7_75t_R \U$2619 ( + .A(\sn$4290 ), + .Y(\s$4291 ) + ); + INVx1_ASAP7_75t_R \U$2620 ( + .A(\con$4292 ), + .Y(\c$4293 ) + ); + INVx1_ASAP7_75t_R \U$2621 ( + .A(\sn$4294 ), + .Y(\s$4295 ) + ); + INVx1_ASAP7_75t_R \U$2622 ( + .A(\con$4296 ), + .Y(\c$4297 ) + ); + INVx1_ASAP7_75t_R \U$2623 ( + .A(\sn$4298 ), + .Y(\s$4299 ) + ); + INVx1_ASAP7_75t_R \U$2624 ( + .A(\con$4300 ), + .Y(\c$4301 ) + ); + INVx1_ASAP7_75t_R \U$2625 ( + .A(\sn$4302 ), + .Y(\s$4303 ) + ); + INVx1_ASAP7_75t_R \U$2626 ( + .A(\con$4304 ), + .Y(\c$4305 ) + ); + INVx1_ASAP7_75t_R \U$2627 ( + .A(\sn$4306 ), + .Y(\s$4307 ) + ); + INVx1_ASAP7_75t_R \U$2628 ( + .A(\con$4308 ), + .Y(\c$4309 ) + ); + INVx1_ASAP7_75t_R \U$2629 ( + .A(\sn$4310 ), + .Y(\s$4311 ) + ); + INVx1_ASAP7_75t_R \U$2630 ( + .A(\con$4312 ), + .Y(\c$4313 ) + ); + INVx1_ASAP7_75t_R \U$2631 ( + .A(\sn$4314 ), + .Y(\s$4315 ) + ); + INVx1_ASAP7_75t_R \U$2632 ( + .A(\con$4316 ), + .Y(\c$4317 ) + ); + INVx1_ASAP7_75t_R \U$2633 ( + .A(\sn$4318 ), + .Y(\s$4319 ) + ); + INVx1_ASAP7_75t_R \U$2634 ( + .A(\con$4320 ), + .Y(\c$4321 ) + ); + INVx1_ASAP7_75t_R \U$2635 ( + .A(\sn$4322 ), + .Y(\s$4323 ) + ); + INVx1_ASAP7_75t_R \U$2636 ( + .A(\con$4324 ), + .Y(\c$4325 ) + ); + INVx1_ASAP7_75t_R \U$2637 ( + .A(\sn$4326 ), + .Y(\s$4327 ) + ); + INVx1_ASAP7_75t_R \U$2638 ( + .A(\con$4328 ), + .Y(\c$4329 ) + ); + INVx1_ASAP7_75t_R \U$2639 ( + .A(\sn$4330 ), + .Y(\s$4331 ) + ); + INVx1_ASAP7_75t_R \U$2640 ( + .A(\con$4332 ), + .Y(\c$4333 ) + ); + INVx1_ASAP7_75t_R \U$2641 ( + .A(\sn$4334 ), + .Y(\s$4335 ) + ); + INVx1_ASAP7_75t_R \U$2642 ( + .A(\con$4336 ), + .Y(\c$4337 ) + ); + INVx1_ASAP7_75t_R \U$2643 ( + .A(\sn$4338 ), + .Y(\s$4339 ) + ); + INVx1_ASAP7_75t_R \U$2644 ( + .A(\con$4340 ), + .Y(\c$4341 ) + ); + INVx1_ASAP7_75t_R \U$2645 ( + .A(\sn$4342 ), + .Y(\s$4343 ) + ); + INVx1_ASAP7_75t_R \U$2646 ( + .A(\con$4344 ), + .Y(\c$4345 ) + ); + INVx1_ASAP7_75t_R \U$2647 ( + .A(\sn$4346 ), + .Y(\s$4347 ) + ); + INVx1_ASAP7_75t_R \U$2648 ( + .A(\con$4348 ), + .Y(\c$4349 ) + ); + INVx1_ASAP7_75t_R \U$2649 ( + .A(\sn$4350 ), + .Y(\s$4351 ) + ); + INVx1_ASAP7_75t_R \U$2650 ( + .A(\con$4352 ), + .Y(\c$4353 ) + ); + INVx1_ASAP7_75t_R \U$2651 ( + .A(\sn$4354 ), + .Y(\s$4355 ) + ); + INVx1_ASAP7_75t_R \U$2652 ( + .A(\con$4356 ), + .Y(\c$4357 ) + ); + INVx1_ASAP7_75t_R \U$2653 ( + .A(\sn$4358 ), + .Y(\s$4359 ) + ); + INVx1_ASAP7_75t_R \U$2654 ( + .A(\con$4360 ), + .Y(\c$4361 ) + ); + INVx1_ASAP7_75t_R \U$2655 ( + .A(\sn$4362 ), + .Y(\s$4363 ) + ); + INVx1_ASAP7_75t_R \U$2656 ( + .A(\con$4364 ), + .Y(\c$4365 ) + ); + INVx1_ASAP7_75t_R \U$2657 ( + .A(\sn$4366 ), + .Y(\s$4367 ) + ); + INVx1_ASAP7_75t_R \U$2658 ( + .A(\con$4368 ), + .Y(\c$4369 ) + ); + INVx1_ASAP7_75t_R \U$2659 ( + .A(\sn$4370 ), + .Y(\s$4371 ) + ); + INVx1_ASAP7_75t_R \U$2660 ( + .A(\con$4372 ), + .Y(\c$4373 ) + ); + INVx1_ASAP7_75t_R \U$2661 ( + .A(\sn$4374 ), + .Y(\s$4375 ) + ); + INVx1_ASAP7_75t_R \U$2662 ( + .A(\con$4376 ), + .Y(\c$4377 ) + ); + INVx1_ASAP7_75t_R \U$2663 ( + .A(\sn$4378 ), + .Y(\s$4379 ) + ); + INVx1_ASAP7_75t_R \U$2664 ( + .A(\con$4380 ), + .Y(\c$4381 ) + ); + INVx1_ASAP7_75t_R \U$2665 ( + .A(\sn$4382 ), + .Y(\s$4383 ) + ); + INVx1_ASAP7_75t_R \U$2666 ( + .A(\con$4384 ), + .Y(\c$4385 ) + ); + INVx1_ASAP7_75t_R \U$2667 ( + .A(\sn$4386 ), + .Y(\s$4387 ) + ); + INVx1_ASAP7_75t_R \U$2668 ( + .A(\con$4388 ), + .Y(\c$4389 ) + ); + INVx1_ASAP7_75t_R \U$2669 ( + .A(\sn$4390 ), + .Y(\s$4391 ) + ); + INVx1_ASAP7_75t_R \U$2670 ( + .A(\con$4392 ), + .Y(\c$4393 ) + ); + INVx1_ASAP7_75t_R \U$2671 ( + .A(\sn$4394 ), + .Y(\s$4395 ) + ); + INVx1_ASAP7_75t_R \U$2672 ( + .A(\con$4396 ), + .Y(\c$4397 ) + ); + INVx1_ASAP7_75t_R \U$2673 ( + .A(\sn$4398 ), + .Y(\s$4399 ) + ); + INVx1_ASAP7_75t_R \U$2674 ( + .A(\con$4400 ), + .Y(c) + ); + INVx1_ASAP7_75t_R \U$2675 ( + .A(\sn$4401 ), + .Y(s) + ); + INVx1_ASAP7_75t_R \U$2676 ( + .A(\con$4402 ), + .Y(\c$1197 ) + ); + INVx1_ASAP7_75t_R \U$2677 ( + .A(\sn$4403 ), + .Y(\s$1260 ) + ); + INVx1_ASAP7_75t_R \U$2678 ( + .A(\con$4404 ), + .Y(\c$1198 ) + ); + INVx1_ASAP7_75t_R \U$2679 ( + .A(\sn$4405 ), + .Y(\s$1261 ) + ); + INVx1_ASAP7_75t_R \U$2680 ( + .A(\con$4406 ), + .Y(\c$1199 ) + ); + INVx1_ASAP7_75t_R \U$2681 ( + .A(\sn$4407 ), + .Y(\s$1262 ) + ); + INVx1_ASAP7_75t_R \U$2682 ( + .A(\con$4408 ), + .Y(\c$1200 ) + ); + INVx1_ASAP7_75t_R \U$2683 ( + .A(\sn$4409 ), + .Y(\s$1263 ) + ); + INVx1_ASAP7_75t_R \U$2684 ( + .A(\con$4410 ), + .Y(\c$1201 ) + ); + INVx1_ASAP7_75t_R \U$2685 ( + .A(\sn$4411 ), + .Y(\s$1264 ) + ); + INVx1_ASAP7_75t_R \U$2686 ( + .A(\con$4412 ), + .Y(\c$1202 ) + ); + INVx1_ASAP7_75t_R \U$2687 ( + .A(\sn$4413 ), + .Y(\s$1265 ) + ); + INVx1_ASAP7_75t_R \U$2688 ( + .A(\con$4414 ), + .Y(\c$1203 ) + ); + INVx1_ASAP7_75t_R \U$2689 ( + .A(\sn$4415 ), + .Y(\s$1266 ) + ); + INVx1_ASAP7_75t_R \U$2690 ( + .A(\con$4416 ), + .Y(\c$1204 ) + ); + INVx1_ASAP7_75t_R \U$2691 ( + .A(\sn$4417 ), + .Y(\s$1267 ) + ); + INVx1_ASAP7_75t_R \U$2692 ( + .A(\con$4418 ), + .Y(\c$1205 ) + ); + INVx1_ASAP7_75t_R \U$2693 ( + .A(\sn$4419 ), + .Y(\s$1268 ) + ); + INVx1_ASAP7_75t_R \U$2694 ( + .A(\con$4420 ), + .Y(\c$1206 ) + ); + INVx1_ASAP7_75t_R \U$2695 ( + .A(\sn$4421 ), + .Y(\s$1269 ) + ); + INVx1_ASAP7_75t_R \U$2696 ( + .A(\con$4422 ), + .Y(\c$1207 ) + ); + INVx1_ASAP7_75t_R \U$2697 ( + .A(\sn$4423 ), + .Y(\s$1270 ) + ); + INVx1_ASAP7_75t_R \U$2698 ( + .A(\con$4424 ), + .Y(\c$1208 ) + ); + INVx1_ASAP7_75t_R \U$2699 ( + .A(\sn$4425 ), + .Y(\s$1271 ) + ); + INVx1_ASAP7_75t_R \U$2700 ( + .A(\con$4426 ), + .Y(\c$1209 ) + ); + INVx1_ASAP7_75t_R \U$2701 ( + .A(\sn$4427 ), + .Y(\s$1272 ) + ); + INVx1_ASAP7_75t_R \U$2702 ( + .A(\con$4428 ), + .Y(\c$1210 ) + ); + INVx1_ASAP7_75t_R \U$2703 ( + .A(\sn$4429 ), + .Y(\s$1273 ) + ); + INVx1_ASAP7_75t_R \U$2704 ( + .A(\con$4430 ), + .Y(\c$1211 ) + ); + INVx1_ASAP7_75t_R \U$2705 ( + .A(\sn$4431 ), + .Y(\s$1274 ) + ); + INVx1_ASAP7_75t_R \U$2706 ( + .A(\con$4432 ), + .Y(\c$1212 ) + ); + INVx1_ASAP7_75t_R \U$2707 ( + .A(\sn$4433 ), + .Y(\s$1275 ) + ); + INVx1_ASAP7_75t_R \U$2708 ( + .A(\con$4434 ), + .Y(\c$1213 ) + ); + INVx1_ASAP7_75t_R \U$2709 ( + .A(\sn$4435 ), + .Y(\s$1276 ) + ); + INVx1_ASAP7_75t_R \U$2710 ( + .A(\con$4436 ), + .Y(\c$1214 ) + ); + INVx1_ASAP7_75t_R \U$2711 ( + .A(\sn$4437 ), + .Y(\s$1277 ) + ); + INVx1_ASAP7_75t_R \U$2712 ( + .A(\con$4438 ), + .Y(\c$1215 ) + ); + INVx1_ASAP7_75t_R \U$2713 ( + .A(\sn$4439 ), + .Y(\s$1278 ) + ); + INVx1_ASAP7_75t_R \U$2714 ( + .A(\con$4440 ), + .Y(\c$1216 ) + ); + INVx1_ASAP7_75t_R \U$2715 ( + .A(\sn$4441 ), + .Y(\s$1279 ) + ); + INVx1_ASAP7_75t_R \U$2716 ( + .A(\con$4442 ), + .Y(\c$1217 ) + ); + INVx1_ASAP7_75t_R \U$2717 ( + .A(\sn$4443 ), + .Y(\s$1280 ) + ); + INVx1_ASAP7_75t_R \U$2718 ( + .A(\con$4444 ), + .Y(\c$1218 ) + ); + INVx1_ASAP7_75t_R \U$2719 ( + .A(\sn$4445 ), + .Y(\s$1281 ) + ); + INVx1_ASAP7_75t_R \U$2720 ( + .A(\con$4446 ), + .Y(\c$1219 ) + ); + INVx1_ASAP7_75t_R \U$2721 ( + .A(\sn$4447 ), + .Y(\s$1282 ) + ); + INVx1_ASAP7_75t_R \U$2722 ( + .A(\con$4448 ), + .Y(\c$1220 ) + ); + INVx1_ASAP7_75t_R \U$2723 ( + .A(\sn$4449 ), + .Y(\s$1283 ) + ); + INVx1_ASAP7_75t_R \U$2724 ( + .A(\con$4450 ), + .Y(\c$1221 ) + ); + INVx1_ASAP7_75t_R \U$2725 ( + .A(\sn$4451 ), + .Y(\s$1284 ) + ); + INVx1_ASAP7_75t_R \U$2726 ( + .A(\con$4452 ), + .Y(\c$1222 ) + ); + INVx1_ASAP7_75t_R \U$2727 ( + .A(\sn$4453 ), + .Y(\s$1285 ) + ); + INVx1_ASAP7_75t_R \U$2728 ( + .A(\con$4454 ), + .Y(\c$1223 ) + ); + INVx1_ASAP7_75t_R \U$2729 ( + .A(\sn$4455 ), + .Y(\s$1286 ) + ); + INVx1_ASAP7_75t_R \U$2730 ( + .A(\con$4456 ), + .Y(\c$1224 ) + ); + INVx1_ASAP7_75t_R \U$2731 ( + .A(\sn$4457 ), + .Y(\s$1287 ) + ); + INVx1_ASAP7_75t_R \U$2732 ( + .A(\con$4458 ), + .Y(\c$1225 ) + ); + INVx1_ASAP7_75t_R \U$2733 ( + .A(\sn$4459 ), + .Y(\s$1288 ) + ); + INVx1_ASAP7_75t_R \U$2734 ( + .A(\con$4460 ), + .Y(\c$1226 ) + ); + INVx1_ASAP7_75t_R \U$2735 ( + .A(\sn$4461 ), + .Y(\s$1289 ) + ); + INVx1_ASAP7_75t_R \U$2736 ( + .A(\con$4462 ), + .Y(\c$1227 ) + ); + INVx1_ASAP7_75t_R \U$2737 ( + .A(\sn$4463 ), + .Y(\s$1290 ) + ); + INVx1_ASAP7_75t_R \U$2738 ( + .A(\con$4464 ), + .Y(\c$1228 ) + ); + INVx1_ASAP7_75t_R \U$2739 ( + .A(\sn$4465 ), + .Y(\s$1291 ) + ); + INVx1_ASAP7_75t_R \U$2740 ( + .A(\con$4466 ), + .Y(\c$1229 ) + ); + INVx1_ASAP7_75t_R \U$2741 ( + .A(\sn$4467 ), + .Y(\s$1292 ) + ); + INVx1_ASAP7_75t_R \U$2742 ( + .A(\con$4468 ), + .Y(\c$1230 ) + ); + INVx1_ASAP7_75t_R \U$2743 ( + .A(\sn$4469 ), + .Y(\s$1293 ) + ); + INVx1_ASAP7_75t_R \U$2744 ( + .A(\con$4470 ), + .Y(\c$1231 ) + ); + INVx1_ASAP7_75t_R \U$2745 ( + .A(\sn$4471 ), + .Y(\s$1294 ) + ); + INVx1_ASAP7_75t_R \U$2746 ( + .A(\con$4472 ), + .Y(\c$1232 ) + ); + INVx1_ASAP7_75t_R \U$2747 ( + .A(\sn$4473 ), + .Y(\s$1295 ) + ); + INVx1_ASAP7_75t_R \U$2748 ( + .A(\con$4474 ), + .Y(\c$1233 ) + ); + INVx1_ASAP7_75t_R \U$2749 ( + .A(\sn$4475 ), + .Y(\s$1296 ) + ); + INVx1_ASAP7_75t_R \U$2750 ( + .A(\con$4476 ), + .Y(\c$1234 ) + ); + INVx1_ASAP7_75t_R \U$2751 ( + .A(\sn$4477 ), + .Y(\s$1297 ) + ); + INVx1_ASAP7_75t_R \U$2752 ( + .A(\con$4478 ), + .Y(\c$1235 ) + ); + INVx1_ASAP7_75t_R \U$2753 ( + .A(\sn$4479 ), + .Y(\s$1298 ) + ); + INVx1_ASAP7_75t_R \U$2754 ( + .A(\con$4480 ), + .Y(\c$1236 ) + ); + INVx1_ASAP7_75t_R \U$2755 ( + .A(\sn$4481 ), + .Y(\s$1299 ) + ); + INVx1_ASAP7_75t_R \U$2756 ( + .A(\con$4482 ), + .Y(\c$1237 ) + ); + INVx1_ASAP7_75t_R \U$2757 ( + .A(\sn$4483 ), + .Y(\s$1300 ) + ); + INVx1_ASAP7_75t_R \U$2758 ( + .A(\con$4484 ), + .Y(\c$1238 ) + ); + INVx1_ASAP7_75t_R \U$2759 ( + .A(\sn$4485 ), + .Y(\s$1301 ) + ); + INVx1_ASAP7_75t_R \U$2760 ( + .A(\con$4486 ), + .Y(\c$1239 ) + ); + INVx1_ASAP7_75t_R \U$2761 ( + .A(\sn$4487 ), + .Y(\s$1302 ) + ); + INVx1_ASAP7_75t_R \U$2762 ( + .A(\con$4488 ), + .Y(\c$1240 ) + ); + INVx1_ASAP7_75t_R \U$2763 ( + .A(\sn$4489 ), + .Y(\s$1303 ) + ); + INVx1_ASAP7_75t_R \U$2764 ( + .A(\con$4490 ), + .Y(\c$1241 ) + ); + INVx1_ASAP7_75t_R \U$2765 ( + .A(\sn$4491 ), + .Y(\s$1304 ) + ); + INVx1_ASAP7_75t_R \U$2766 ( + .A(\con$4492 ), + .Y(\c$1242 ) + ); + INVx1_ASAP7_75t_R \U$2767 ( + .A(\sn$4493 ), + .Y(\s$1305 ) + ); + INVx1_ASAP7_75t_R \U$2768 ( + .A(\con$4494 ), + .Y(\c$1243 ) + ); + INVx1_ASAP7_75t_R \U$2769 ( + .A(\sn$4495 ), + .Y(\s$1306 ) + ); + INVx1_ASAP7_75t_R \U$2770 ( + .A(\con$4496 ), + .Y(\c$1244 ) + ); + INVx1_ASAP7_75t_R \U$2771 ( + .A(\sn$4497 ), + .Y(\s$1307 ) + ); + INVx1_ASAP7_75t_R \U$2772 ( + .A(\con$4498 ), + .Y(\c$1245 ) + ); + INVx1_ASAP7_75t_R \U$2773 ( + .A(\sn$4499 ), + .Y(\s$1308 ) + ); + INVx1_ASAP7_75t_R \U$2774 ( + .A(\con$4500 ), + .Y(\c$1246 ) + ); + INVx1_ASAP7_75t_R \U$2775 ( + .A(\sn$4501 ), + .Y(\s$1309 ) + ); + INVx1_ASAP7_75t_R \U$2776 ( + .A(\con$4502 ), + .Y(\c$1247 ) + ); + INVx1_ASAP7_75t_R \U$2777 ( + .A(\sn$4503 ), + .Y(\s$1310 ) + ); + INVx1_ASAP7_75t_R \U$2778 ( + .A(\con$4504 ), + .Y(\c$1248 ) + ); + INVx1_ASAP7_75t_R \U$2779 ( + .A(\sn$4505 ), + .Y(\s$1311 ) + ); + INVx1_ASAP7_75t_R \U$2780 ( + .A(\con$4506 ), + .Y(\c$1249 ) + ); + INVx1_ASAP7_75t_R \U$2781 ( + .A(\sn$4507 ), + .Y(\s$1312 ) + ); + INVx1_ASAP7_75t_R \U$2782 ( + .A(\con$4508 ), + .Y(\c$1250 ) + ); + INVx1_ASAP7_75t_R \U$2783 ( + .A(\sn$4509 ), + .Y(\s$1313 ) + ); + INVx1_ASAP7_75t_R \U$2784 ( + .A(\con$4510 ), + .Y(\c$1251 ) + ); + INVx1_ASAP7_75t_R \U$2785 ( + .A(\sn$4511 ), + .Y(\s$1314 ) + ); + INVx1_ASAP7_75t_R \U$2786 ( + .A(\con$4512 ), + .Y(\c$1252 ) + ); + INVx1_ASAP7_75t_R \U$2787 ( + .A(\sn$4513 ), + .Y(\s$1315 ) + ); + INVx1_ASAP7_75t_R \U$2788 ( + .A(\con$4514 ), + .Y(\c$1253 ) + ); + INVx1_ASAP7_75t_R \U$2789 ( + .A(\sn$4515 ), + .Y(\s$1316 ) + ); + INVx1_ASAP7_75t_R \U$2790 ( + .A(\con$4516 ), + .Y(\c$1254 ) + ); + INVx1_ASAP7_75t_R \U$2791 ( + .A(\sn$4517 ), + .Y(\s$1317 ) + ); + INVx1_ASAP7_75t_R \U$2792 ( + .A(\con$4518 ), + .Y(\c$1255 ) + ); + INVx1_ASAP7_75t_R \U$2793 ( + .A(\sn$4519 ), + .Y(\s$1318 ) + ); + INVx1_ASAP7_75t_R \U$2794 ( + .A(\con$4520 ), + .Y(\c$1256 ) + ); + INVx1_ASAP7_75t_R \U$2795 ( + .A(\sn$4521 ), + .Y(\s$1319 ) + ); + INVx1_ASAP7_75t_R \U$2796 ( + .A(\con$4522 ), + .Y(\c$1257 ) + ); + INVx1_ASAP7_75t_R \U$2797 ( + .A(\sn$4523 ), + .Y(\s$1320 ) + ); + INVx1_ASAP7_75t_R \U$2798 ( + .A(\con$4524 ), + .Y(\$53 ) + ); + INVx1_ASAP7_75t_R \U$2799 ( + .A(\sn$4525 ), + .Y(\s$1321 ) + ); + INVx1_ASAP7_75t_R \U$526 ( + .A(1'h0), + .Y(\$1 ) + ); + INVx1_ASAP7_75t_R \U$527 ( + .A(a_registered[0]), + .Y(\$2 ) + ); + INVx1_ASAP7_75t_R \U$528 ( + .A(a_registered[1]), + .Y(\$3 ) + ); + AO33x2_ASAP7_75t_R \U$529 ( + .A1(\$3 ), + .A2(a_registered[0]), + .A3(1'h0), + .B1(a_registered[1]), + .B2(\$2 ), + .B3(\$1 ), + .Y(sel_0) + ); + XOR2x1_ASAP7_75t_R \U$530 ( + .A(a_registered[0]), + .B(1'h0), + .Y(sel_1) + ); + AO22x1_ASAP7_75t_R \U$531 ( + .A1(1'h0), + .A2(sel_0), + .B1(b_registered[0]), + .B2(sel_1), + .Y(t) + ); + XOR2x1_ASAP7_75t_R \U$532 ( + .A(t), + .B(a_registered[1]), + .Y(booth_b0_m0) + ); + AO22x1_ASAP7_75t_R \U$533 ( + .A1(b_registered[0]), + .A2(sel_0), + .B1(b_registered[1]), + .B2(sel_1), + .Y(\t$1976 ) + ); + XOR2x1_ASAP7_75t_R \U$534 ( + .A(\t$1976 ), + .B(a_registered[1]), + .Y(booth_b0_m1) + ); + AO22x1_ASAP7_75t_R \U$535 ( + .A1(b_registered[1]), + .A2(sel_0), + .B1(b_registered[2]), + .B2(sel_1), + .Y(\t$1977 ) + ); + XOR2x1_ASAP7_75t_R \U$536 ( + .A(\t$1977 ), + .B(a_registered[1]), + .Y(booth_b0_m2) + ); + AO22x1_ASAP7_75t_R \U$537 ( + .A1(b_registered[2]), + .A2(sel_0), + .B1(b_registered[3]), + .B2(sel_1), + .Y(\t$1978 ) + ); + XOR2x1_ASAP7_75t_R \U$538 ( + .A(\t$1978 ), + .B(a_registered[1]), + .Y(booth_b0_m3) + ); + AO22x1_ASAP7_75t_R \U$539 ( + .A1(b_registered[3]), + .A2(sel_0), + .B1(b_registered[4]), + .B2(sel_1), + .Y(\t$1979 ) + ); + XOR2x1_ASAP7_75t_R \U$540 ( + .A(\t$1979 ), + .B(a_registered[1]), + .Y(booth_b0_m4) + ); + AO22x1_ASAP7_75t_R \U$541 ( + .A1(b_registered[4]), + .A2(sel_0), + .B1(b_registered[5]), + .B2(sel_1), + .Y(\t$1980 ) + ); + XOR2x1_ASAP7_75t_R \U$542 ( + .A(\t$1980 ), + .B(a_registered[1]), + .Y(booth_b0_m5) + ); + AO22x1_ASAP7_75t_R \U$543 ( + .A1(b_registered[5]), + .A2(sel_0), + .B1(b_registered[6]), + .B2(sel_1), + .Y(\t$1981 ) + ); + XOR2x1_ASAP7_75t_R \U$544 ( + .A(\t$1981 ), + .B(a_registered[1]), + .Y(booth_b0_m6) + ); + AO22x1_ASAP7_75t_R \U$545 ( + .A1(b_registered[6]), + .A2(sel_0), + .B1(b_registered[7]), + .B2(sel_1), + .Y(\t$1982 ) + ); + XOR2x1_ASAP7_75t_R \U$546 ( + .A(\t$1982 ), + .B(a_registered[1]), + .Y(booth_b0_m7) + ); + AO22x1_ASAP7_75t_R \U$547 ( + .A1(b_registered[7]), + .A2(sel_0), + .B1(b_registered[8]), + .B2(sel_1), + .Y(\t$1983 ) + ); + XOR2x1_ASAP7_75t_R \U$548 ( + .A(\t$1983 ), + .B(a_registered[1]), + .Y(booth_b0_m8) + ); + AO22x1_ASAP7_75t_R \U$549 ( + .A1(b_registered[8]), + .A2(sel_0), + .B1(b_registered[9]), + .B2(sel_1), + .Y(\t$1984 ) + ); + XOR2x1_ASAP7_75t_R \U$550 ( + .A(\t$1984 ), + .B(a_registered[1]), + .Y(booth_b0_m9) + ); + AO22x1_ASAP7_75t_R \U$551 ( + .A1(b_registered[9]), + .A2(sel_0), + .B1(b_registered[10]), + .B2(sel_1), + .Y(\t$1985 ) + ); + XOR2x1_ASAP7_75t_R \U$552 ( + .A(\t$1985 ), + .B(a_registered[1]), + .Y(booth_b0_m10) + ); + AO22x1_ASAP7_75t_R \U$553 ( + .A1(b_registered[10]), + .A2(sel_0), + .B1(b_registered[11]), + .B2(sel_1), + .Y(\t$1986 ) + ); + XOR2x1_ASAP7_75t_R \U$554 ( + .A(\t$1986 ), + .B(a_registered[1]), + .Y(booth_b0_m11) + ); + AO22x1_ASAP7_75t_R \U$555 ( + .A1(b_registered[11]), + .A2(sel_0), + .B1(b_registered[12]), + .B2(sel_1), + .Y(\t$1987 ) + ); + XOR2x1_ASAP7_75t_R \U$556 ( + .A(\t$1987 ), + .B(a_registered[1]), + .Y(booth_b0_m12) + ); + AO22x1_ASAP7_75t_R \U$557 ( + .A1(b_registered[12]), + .A2(sel_0), + .B1(b_registered[13]), + .B2(sel_1), + .Y(\t$1988 ) + ); + XOR2x1_ASAP7_75t_R \U$558 ( + .A(\t$1988 ), + .B(a_registered[1]), + .Y(booth_b0_m13) + ); + AO22x1_ASAP7_75t_R \U$559 ( + .A1(b_registered[13]), + .A2(sel_0), + .B1(b_registered[14]), + .B2(sel_1), + .Y(\t$1989 ) + ); + XOR2x1_ASAP7_75t_R \U$560 ( + .A(\t$1989 ), + .B(a_registered[1]), + .Y(booth_b0_m14) + ); + AO22x1_ASAP7_75t_R \U$561 ( + .A1(b_registered[14]), + .A2(sel_0), + .B1(b_registered[15]), + .B2(sel_1), + .Y(\t$1990 ) + ); + XOR2x1_ASAP7_75t_R \U$562 ( + .A(\t$1990 ), + .B(a_registered[1]), + .Y(booth_b0_m15) + ); + AO22x1_ASAP7_75t_R \U$563 ( + .A1(b_registered[15]), + .A2(sel_0), + .B1(b_registered[16]), + .B2(sel_1), + .Y(\t$1991 ) + ); + XOR2x1_ASAP7_75t_R \U$564 ( + .A(\t$1991 ), + .B(a_registered[1]), + .Y(booth_b0_m16) + ); + AO22x1_ASAP7_75t_R \U$565 ( + .A1(b_registered[16]), + .A2(sel_0), + .B1(b_registered[17]), + .B2(sel_1), + .Y(\t$1992 ) + ); + XOR2x1_ASAP7_75t_R \U$566 ( + .A(\t$1992 ), + .B(a_registered[1]), + .Y(booth_b0_m17) + ); + AO22x1_ASAP7_75t_R \U$567 ( + .A1(b_registered[17]), + .A2(sel_0), + .B1(b_registered[18]), + .B2(sel_1), + .Y(\t$1993 ) + ); + XOR2x1_ASAP7_75t_R \U$568 ( + .A(\t$1993 ), + .B(a_registered[1]), + .Y(booth_b0_m18) + ); + AO22x1_ASAP7_75t_R \U$569 ( + .A1(b_registered[18]), + .A2(sel_0), + .B1(b_registered[19]), + .B2(sel_1), + .Y(\t$1994 ) + ); + XOR2x1_ASAP7_75t_R \U$570 ( + .A(\t$1994 ), + .B(a_registered[1]), + .Y(booth_b0_m19) + ); + AO22x1_ASAP7_75t_R \U$571 ( + .A1(b_registered[19]), + .A2(sel_0), + .B1(b_registered[20]), + .B2(sel_1), + .Y(\t$1995 ) + ); + XOR2x1_ASAP7_75t_R \U$572 ( + .A(\t$1995 ), + .B(a_registered[1]), + .Y(booth_b0_m20) + ); + AO22x1_ASAP7_75t_R \U$573 ( + .A1(b_registered[20]), + .A2(sel_0), + .B1(b_registered[21]), + .B2(sel_1), + .Y(\t$1996 ) + ); + XOR2x1_ASAP7_75t_R \U$574 ( + .A(\t$1996 ), + .B(a_registered[1]), + .Y(booth_b0_m21) + ); + AO22x1_ASAP7_75t_R \U$575 ( + .A1(b_registered[21]), + .A2(sel_0), + .B1(b_registered[22]), + .B2(sel_1), + .Y(\t$1997 ) + ); + XOR2x1_ASAP7_75t_R \U$576 ( + .A(\t$1997 ), + .B(a_registered[1]), + .Y(booth_b0_m22) + ); + AO22x1_ASAP7_75t_R \U$577 ( + .A1(b_registered[22]), + .A2(sel_0), + .B1(b_registered[23]), + .B2(sel_1), + .Y(\t$1998 ) + ); + XOR2x1_ASAP7_75t_R \U$578 ( + .A(\t$1998 ), + .B(a_registered[1]), + .Y(booth_b0_m23) + ); + AO22x1_ASAP7_75t_R \U$579 ( + .A1(b_registered[23]), + .A2(sel_0), + .B1(b_registered[24]), + .B2(sel_1), + .Y(\t$1999 ) + ); + XOR2x1_ASAP7_75t_R \U$580 ( + .A(\t$1999 ), + .B(a_registered[1]), + .Y(booth_b0_m24) + ); + AO22x1_ASAP7_75t_R \U$581 ( + .A1(b_registered[24]), + .A2(sel_0), + .B1(b_registered[25]), + .B2(sel_1), + .Y(\t$2000 ) + ); + XOR2x1_ASAP7_75t_R \U$582 ( + .A(\t$2000 ), + .B(a_registered[1]), + .Y(booth_b0_m25) + ); + AO22x1_ASAP7_75t_R \U$583 ( + .A1(b_registered[25]), + .A2(sel_0), + .B1(b_registered[26]), + .B2(sel_1), + .Y(\t$2001 ) + ); + XOR2x1_ASAP7_75t_R \U$584 ( + .A(\t$2001 ), + .B(a_registered[1]), + .Y(booth_b0_m26) + ); + AO22x1_ASAP7_75t_R \U$585 ( + .A1(b_registered[26]), + .A2(sel_0), + .B1(b_registered[27]), + .B2(sel_1), + .Y(\t$2002 ) + ); + XOR2x1_ASAP7_75t_R \U$586 ( + .A(\t$2002 ), + .B(a_registered[1]), + .Y(booth_b0_m27) + ); + AO22x1_ASAP7_75t_R \U$587 ( + .A1(b_registered[27]), + .A2(sel_0), + .B1(b_registered[28]), + .B2(sel_1), + .Y(\t$2003 ) + ); + XOR2x1_ASAP7_75t_R \U$588 ( + .A(\t$2003 ), + .B(a_registered[1]), + .Y(booth_b0_m28) + ); + AO22x1_ASAP7_75t_R \U$589 ( + .A1(b_registered[28]), + .A2(sel_0), + .B1(b_registered[29]), + .B2(sel_1), + .Y(\t$2004 ) + ); + XOR2x1_ASAP7_75t_R \U$590 ( + .A(\t$2004 ), + .B(a_registered[1]), + .Y(booth_b0_m29) + ); + AO22x1_ASAP7_75t_R \U$591 ( + .A1(b_registered[29]), + .A2(sel_0), + .B1(b_registered[30]), + .B2(sel_1), + .Y(\t$2005 ) + ); + XOR2x1_ASAP7_75t_R \U$592 ( + .A(\t$2005 ), + .B(a_registered[1]), + .Y(booth_b0_m30) + ); + AO22x1_ASAP7_75t_R \U$593 ( + .A1(b_registered[30]), + .A2(sel_0), + .B1(b_registered[31]), + .B2(sel_1), + .Y(\t$2006 ) + ); + XOR2x1_ASAP7_75t_R \U$594 ( + .A(\t$2006 ), + .B(a_registered[1]), + .Y(booth_b0_m31) + ); + AO22x1_ASAP7_75t_R \U$595 ( + .A1(b_registered[31]), + .A2(sel_0), + .B1(1'h0), + .B2(sel_1), + .Y(\t$2007 ) + ); + XOR2x1_ASAP7_75t_R \U$596 ( + .A(\t$2007 ), + .B(a_registered[1]), + .Y(booth_b0_m32) + ); + INVx1_ASAP7_75t_R \U$597 ( + .A(a_registered[1]), + .Y(notsign) + ); + INVx1_ASAP7_75t_R \U$598 ( + .A(a_registered[1]), + .Y(\$4 ) + ); + INVx1_ASAP7_75t_R \U$599 ( + .A(a_registered[2]), + .Y(\$5 ) + ); + INVx1_ASAP7_75t_R \U$600 ( + .A(a_registered[3]), + .Y(\$6 ) + ); + AO33x2_ASAP7_75t_R \U$601 ( + .A1(\$6 ), + .A2(a_registered[2]), + .A3(a_registered[1]), + .B1(a_registered[3]), + .B2(\$5 ), + .B3(\$4 ), + .Y(\sel_0$1365 ) + ); + XOR2x1_ASAP7_75t_R \U$602 ( + .A(a_registered[2]), + .B(a_registered[1]), + .Y(\sel_1$1366 ) + ); + AO22x1_ASAP7_75t_R \U$603 ( + .A1(1'h0), + .A2(\sel_0$1365 ), + .B1(b_registered[0]), + .B2(\sel_1$1366 ), + .Y(\t$2009 ) + ); + XOR2x1_ASAP7_75t_R \U$604 ( + .A(\t$2009 ), + .B(a_registered[3]), + .Y(booth_b2_m0) + ); + AO22x1_ASAP7_75t_R \U$605 ( + .A1(b_registered[0]), + .A2(\sel_0$1365 ), + .B1(b_registered[1]), + .B2(\sel_1$1366 ), + .Y(\t$2010 ) + ); + XOR2x1_ASAP7_75t_R \U$606 ( + .A(\t$2010 ), + .B(a_registered[3]), + .Y(booth_b2_m1) + ); + AO22x1_ASAP7_75t_R \U$607 ( + .A1(b_registered[1]), + .A2(\sel_0$1365 ), + .B1(b_registered[2]), + .B2(\sel_1$1366 ), + .Y(\t$2011 ) + ); + XOR2x1_ASAP7_75t_R \U$608 ( + .A(\t$2011 ), + .B(a_registered[3]), + .Y(booth_b2_m2) + ); + AO22x1_ASAP7_75t_R \U$609 ( + .A1(b_registered[2]), + .A2(\sel_0$1365 ), + .B1(b_registered[3]), + .B2(\sel_1$1366 ), + .Y(\t$2012 ) + ); + XOR2x1_ASAP7_75t_R \U$610 ( + .A(\t$2012 ), + .B(a_registered[3]), + .Y(booth_b2_m3) + ); + AO22x1_ASAP7_75t_R \U$611 ( + .A1(b_registered[3]), + .A2(\sel_0$1365 ), + .B1(b_registered[4]), + .B2(\sel_1$1366 ), + .Y(\t$2013 ) + ); + XOR2x1_ASAP7_75t_R \U$612 ( + .A(\t$2013 ), + .B(a_registered[3]), + .Y(booth_b2_m4) + ); + AO22x1_ASAP7_75t_R \U$613 ( + .A1(b_registered[4]), + .A2(\sel_0$1365 ), + .B1(b_registered[5]), + .B2(\sel_1$1366 ), + .Y(\t$2014 ) + ); + XOR2x1_ASAP7_75t_R \U$614 ( + .A(\t$2014 ), + .B(a_registered[3]), + .Y(booth_b2_m5) + ); + AO22x1_ASAP7_75t_R \U$615 ( + .A1(b_registered[5]), + .A2(\sel_0$1365 ), + .B1(b_registered[6]), + .B2(\sel_1$1366 ), + .Y(\t$2015 ) + ); + XOR2x1_ASAP7_75t_R \U$616 ( + .A(\t$2015 ), + .B(a_registered[3]), + .Y(booth_b2_m6) + ); + AO22x1_ASAP7_75t_R \U$617 ( + .A1(b_registered[6]), + .A2(\sel_0$1365 ), + .B1(b_registered[7]), + .B2(\sel_1$1366 ), + .Y(\t$2016 ) + ); + XOR2x1_ASAP7_75t_R \U$618 ( + .A(\t$2016 ), + .B(a_registered[3]), + .Y(booth_b2_m7) + ); + AO22x1_ASAP7_75t_R \U$619 ( + .A1(b_registered[7]), + .A2(\sel_0$1365 ), + .B1(b_registered[8]), + .B2(\sel_1$1366 ), + .Y(\t$2017 ) + ); + XOR2x1_ASAP7_75t_R \U$620 ( + .A(\t$2017 ), + .B(a_registered[3]), + .Y(booth_b2_m8) + ); + AO22x1_ASAP7_75t_R \U$621 ( + .A1(b_registered[8]), + .A2(\sel_0$1365 ), + .B1(b_registered[9]), + .B2(\sel_1$1366 ), + .Y(\t$2018 ) + ); + XOR2x1_ASAP7_75t_R \U$622 ( + .A(\t$2018 ), + .B(a_registered[3]), + .Y(booth_b2_m9) + ); + AO22x1_ASAP7_75t_R \U$623 ( + .A1(b_registered[9]), + .A2(\sel_0$1365 ), + .B1(b_registered[10]), + .B2(\sel_1$1366 ), + .Y(\t$2019 ) + ); + XOR2x1_ASAP7_75t_R \U$624 ( + .A(\t$2019 ), + .B(a_registered[3]), + .Y(booth_b2_m10) + ); + AO22x1_ASAP7_75t_R \U$625 ( + .A1(b_registered[10]), + .A2(\sel_0$1365 ), + .B1(b_registered[11]), + .B2(\sel_1$1366 ), + .Y(\t$2020 ) + ); + XOR2x1_ASAP7_75t_R \U$626 ( + .A(\t$2020 ), + .B(a_registered[3]), + .Y(booth_b2_m11) + ); + AO22x1_ASAP7_75t_R \U$627 ( + .A1(b_registered[11]), + .A2(\sel_0$1365 ), + .B1(b_registered[12]), + .B2(\sel_1$1366 ), + .Y(\t$2021 ) + ); + XOR2x1_ASAP7_75t_R \U$628 ( + .A(\t$2021 ), + .B(a_registered[3]), + .Y(booth_b2_m12) + ); + AO22x1_ASAP7_75t_R \U$629 ( + .A1(b_registered[12]), + .A2(\sel_0$1365 ), + .B1(b_registered[13]), + .B2(\sel_1$1366 ), + .Y(\t$2022 ) + ); + XOR2x1_ASAP7_75t_R \U$630 ( + .A(\t$2022 ), + .B(a_registered[3]), + .Y(booth_b2_m13) + ); + AO22x1_ASAP7_75t_R \U$631 ( + .A1(b_registered[13]), + .A2(\sel_0$1365 ), + .B1(b_registered[14]), + .B2(\sel_1$1366 ), + .Y(\t$2023 ) + ); + XOR2x1_ASAP7_75t_R \U$632 ( + .A(\t$2023 ), + .B(a_registered[3]), + .Y(booth_b2_m14) + ); + AO22x1_ASAP7_75t_R \U$633 ( + .A1(b_registered[14]), + .A2(\sel_0$1365 ), + .B1(b_registered[15]), + .B2(\sel_1$1366 ), + .Y(\t$2024 ) + ); + XOR2x1_ASAP7_75t_R \U$634 ( + .A(\t$2024 ), + .B(a_registered[3]), + .Y(booth_b2_m15) + ); + AO22x1_ASAP7_75t_R \U$635 ( + .A1(b_registered[15]), + .A2(\sel_0$1365 ), + .B1(b_registered[16]), + .B2(\sel_1$1366 ), + .Y(\t$2025 ) + ); + XOR2x1_ASAP7_75t_R \U$636 ( + .A(\t$2025 ), + .B(a_registered[3]), + .Y(booth_b2_m16) + ); + AO22x1_ASAP7_75t_R \U$637 ( + .A1(b_registered[16]), + .A2(\sel_0$1365 ), + .B1(b_registered[17]), + .B2(\sel_1$1366 ), + .Y(\t$2026 ) + ); + XOR2x1_ASAP7_75t_R \U$638 ( + .A(\t$2026 ), + .B(a_registered[3]), + .Y(booth_b2_m17) + ); + AO22x1_ASAP7_75t_R \U$639 ( + .A1(b_registered[17]), + .A2(\sel_0$1365 ), + .B1(b_registered[18]), + .B2(\sel_1$1366 ), + .Y(\t$2027 ) + ); + XOR2x1_ASAP7_75t_R \U$640 ( + .A(\t$2027 ), + .B(a_registered[3]), + .Y(booth_b2_m18) + ); + AO22x1_ASAP7_75t_R \U$641 ( + .A1(b_registered[18]), + .A2(\sel_0$1365 ), + .B1(b_registered[19]), + .B2(\sel_1$1366 ), + .Y(\t$2028 ) + ); + XOR2x1_ASAP7_75t_R \U$642 ( + .A(\t$2028 ), + .B(a_registered[3]), + .Y(booth_b2_m19) + ); + AO22x1_ASAP7_75t_R \U$643 ( + .A1(b_registered[19]), + .A2(\sel_0$1365 ), + .B1(b_registered[20]), + .B2(\sel_1$1366 ), + .Y(\t$2029 ) + ); + XOR2x1_ASAP7_75t_R \U$644 ( + .A(\t$2029 ), + .B(a_registered[3]), + .Y(booth_b2_m20) + ); + AO22x1_ASAP7_75t_R \U$645 ( + .A1(b_registered[20]), + .A2(\sel_0$1365 ), + .B1(b_registered[21]), + .B2(\sel_1$1366 ), + .Y(\t$2030 ) + ); + XOR2x1_ASAP7_75t_R \U$646 ( + .A(\t$2030 ), + .B(a_registered[3]), + .Y(booth_b2_m21) + ); + AO22x1_ASAP7_75t_R \U$647 ( + .A1(b_registered[21]), + .A2(\sel_0$1365 ), + .B1(b_registered[22]), + .B2(\sel_1$1366 ), + .Y(\t$2031 ) + ); + XOR2x1_ASAP7_75t_R \U$648 ( + .A(\t$2031 ), + .B(a_registered[3]), + .Y(booth_b2_m22) + ); + AO22x1_ASAP7_75t_R \U$649 ( + .A1(b_registered[22]), + .A2(\sel_0$1365 ), + .B1(b_registered[23]), + .B2(\sel_1$1366 ), + .Y(\t$2032 ) + ); + XOR2x1_ASAP7_75t_R \U$650 ( + .A(\t$2032 ), + .B(a_registered[3]), + .Y(booth_b2_m23) + ); + AO22x1_ASAP7_75t_R \U$651 ( + .A1(b_registered[23]), + .A2(\sel_0$1365 ), + .B1(b_registered[24]), + .B2(\sel_1$1366 ), + .Y(\t$2033 ) + ); + XOR2x1_ASAP7_75t_R \U$652 ( + .A(\t$2033 ), + .B(a_registered[3]), + .Y(booth_b2_m24) + ); + AO22x1_ASAP7_75t_R \U$653 ( + .A1(b_registered[24]), + .A2(\sel_0$1365 ), + .B1(b_registered[25]), + .B2(\sel_1$1366 ), + .Y(\t$2034 ) + ); + XOR2x1_ASAP7_75t_R \U$654 ( + .A(\t$2034 ), + .B(a_registered[3]), + .Y(booth_b2_m25) + ); + AO22x1_ASAP7_75t_R \U$655 ( + .A1(b_registered[25]), + .A2(\sel_0$1365 ), + .B1(b_registered[26]), + .B2(\sel_1$1366 ), + .Y(\t$2035 ) + ); + XOR2x1_ASAP7_75t_R \U$656 ( + .A(\t$2035 ), + .B(a_registered[3]), + .Y(booth_b2_m26) + ); + AO22x1_ASAP7_75t_R \U$657 ( + .A1(b_registered[26]), + .A2(\sel_0$1365 ), + .B1(b_registered[27]), + .B2(\sel_1$1366 ), + .Y(\t$2036 ) + ); + XOR2x1_ASAP7_75t_R \U$658 ( + .A(\t$2036 ), + .B(a_registered[3]), + .Y(booth_b2_m27) + ); + AO22x1_ASAP7_75t_R \U$659 ( + .A1(b_registered[27]), + .A2(\sel_0$1365 ), + .B1(b_registered[28]), + .B2(\sel_1$1366 ), + .Y(\t$2037 ) + ); + XOR2x1_ASAP7_75t_R \U$660 ( + .A(\t$2037 ), + .B(a_registered[3]), + .Y(booth_b2_m28) + ); + AO22x1_ASAP7_75t_R \U$661 ( + .A1(b_registered[28]), + .A2(\sel_0$1365 ), + .B1(b_registered[29]), + .B2(\sel_1$1366 ), + .Y(\t$2038 ) + ); + XOR2x1_ASAP7_75t_R \U$662 ( + .A(\t$2038 ), + .B(a_registered[3]), + .Y(booth_b2_m29) + ); + AO22x1_ASAP7_75t_R \U$663 ( + .A1(b_registered[29]), + .A2(\sel_0$1365 ), + .B1(b_registered[30]), + .B2(\sel_1$1366 ), + .Y(\t$2039 ) + ); + XOR2x1_ASAP7_75t_R \U$664 ( + .A(\t$2039 ), + .B(a_registered[3]), + .Y(booth_b2_m30) + ); + AO22x1_ASAP7_75t_R \U$665 ( + .A1(b_registered[30]), + .A2(\sel_0$1365 ), + .B1(b_registered[31]), + .B2(\sel_1$1366 ), + .Y(\t$2040 ) + ); + XOR2x1_ASAP7_75t_R \U$666 ( + .A(\t$2040 ), + .B(a_registered[3]), + .Y(booth_b2_m31) + ); + AO22x1_ASAP7_75t_R \U$667 ( + .A1(b_registered[31]), + .A2(\sel_0$1365 ), + .B1(1'h0), + .B2(\sel_1$1366 ), + .Y(\t$2041 ) + ); + XOR2x1_ASAP7_75t_R \U$668 ( + .A(\t$2041 ), + .B(a_registered[3]), + .Y(booth_b2_m32) + ); + INVx1_ASAP7_75t_R \U$669 ( + .A(a_registered[3]), + .Y(\notsign$686 ) + ); + INVx1_ASAP7_75t_R \U$670 ( + .A(a_registered[3]), + .Y(\$7 ) + ); + INVx1_ASAP7_75t_R \U$671 ( + .A(a_registered[4]), + .Y(\$8 ) + ); + INVx1_ASAP7_75t_R \U$672 ( + .A(a_registered[5]), + .Y(\$9 ) + ); + AO33x2_ASAP7_75t_R \U$673 ( + .A1(\$9 ), + .A2(a_registered[4]), + .A3(a_registered[3]), + .B1(a_registered[5]), + .B2(\$8 ), + .B3(\$7 ), + .Y(\sel_0$1402 ) + ); + XOR2x1_ASAP7_75t_R \U$674 ( + .A(a_registered[4]), + .B(a_registered[3]), + .Y(\sel_1$1403 ) + ); + AO22x1_ASAP7_75t_R \U$675 ( + .A1(1'h0), + .A2(\sel_0$1402 ), + .B1(b_registered[0]), + .B2(\sel_1$1403 ), + .Y(\t$2043 ) + ); + XOR2x1_ASAP7_75t_R \U$676 ( + .A(\t$2043 ), + .B(a_registered[5]), + .Y(booth_b4_m0) + ); + AO22x1_ASAP7_75t_R \U$677 ( + .A1(b_registered[0]), + .A2(\sel_0$1402 ), + .B1(b_registered[1]), + .B2(\sel_1$1403 ), + .Y(\t$2044 ) + ); + XOR2x1_ASAP7_75t_R \U$678 ( + .A(\t$2044 ), + .B(a_registered[5]), + .Y(booth_b4_m1) + ); + AO22x1_ASAP7_75t_R \U$679 ( + .A1(b_registered[1]), + .A2(\sel_0$1402 ), + .B1(b_registered[2]), + .B2(\sel_1$1403 ), + .Y(\t$2045 ) + ); + XOR2x1_ASAP7_75t_R \U$680 ( + .A(\t$2045 ), + .B(a_registered[5]), + .Y(booth_b4_m2) + ); + AO22x1_ASAP7_75t_R \U$681 ( + .A1(b_registered[2]), + .A2(\sel_0$1402 ), + .B1(b_registered[3]), + .B2(\sel_1$1403 ), + .Y(\t$2046 ) + ); + XOR2x1_ASAP7_75t_R \U$682 ( + .A(\t$2046 ), + .B(a_registered[5]), + .Y(booth_b4_m3) + ); + AO22x1_ASAP7_75t_R \U$683 ( + .A1(b_registered[3]), + .A2(\sel_0$1402 ), + .B1(b_registered[4]), + .B2(\sel_1$1403 ), + .Y(\t$2047 ) + ); + XOR2x1_ASAP7_75t_R \U$684 ( + .A(\t$2047 ), + .B(a_registered[5]), + .Y(booth_b4_m4) + ); + AO22x1_ASAP7_75t_R \U$685 ( + .A1(b_registered[4]), + .A2(\sel_0$1402 ), + .B1(b_registered[5]), + .B2(\sel_1$1403 ), + .Y(\t$2048 ) + ); + XOR2x1_ASAP7_75t_R \U$686 ( + .A(\t$2048 ), + .B(a_registered[5]), + .Y(booth_b4_m5) + ); + AO22x1_ASAP7_75t_R \U$687 ( + .A1(b_registered[5]), + .A2(\sel_0$1402 ), + .B1(b_registered[6]), + .B2(\sel_1$1403 ), + .Y(\t$2049 ) + ); + XOR2x1_ASAP7_75t_R \U$688 ( + .A(\t$2049 ), + .B(a_registered[5]), + .Y(booth_b4_m6) + ); + AO22x1_ASAP7_75t_R \U$689 ( + .A1(b_registered[6]), + .A2(\sel_0$1402 ), + .B1(b_registered[7]), + .B2(\sel_1$1403 ), + .Y(\t$2050 ) + ); + XOR2x1_ASAP7_75t_R \U$690 ( + .A(\t$2050 ), + .B(a_registered[5]), + .Y(booth_b4_m7) + ); + AO22x1_ASAP7_75t_R \U$691 ( + .A1(b_registered[7]), + .A2(\sel_0$1402 ), + .B1(b_registered[8]), + .B2(\sel_1$1403 ), + .Y(\t$2051 ) + ); + XOR2x1_ASAP7_75t_R \U$692 ( + .A(\t$2051 ), + .B(a_registered[5]), + .Y(booth_b4_m8) + ); + AO22x1_ASAP7_75t_R \U$693 ( + .A1(b_registered[8]), + .A2(\sel_0$1402 ), + .B1(b_registered[9]), + .B2(\sel_1$1403 ), + .Y(\t$2052 ) + ); + XOR2x1_ASAP7_75t_R \U$694 ( + .A(\t$2052 ), + .B(a_registered[5]), + .Y(booth_b4_m9) + ); + AO22x1_ASAP7_75t_R \U$695 ( + .A1(b_registered[9]), + .A2(\sel_0$1402 ), + .B1(b_registered[10]), + .B2(\sel_1$1403 ), + .Y(\t$2053 ) + ); + XOR2x1_ASAP7_75t_R \U$696 ( + .A(\t$2053 ), + .B(a_registered[5]), + .Y(booth_b4_m10) + ); + AO22x1_ASAP7_75t_R \U$697 ( + .A1(b_registered[10]), + .A2(\sel_0$1402 ), + .B1(b_registered[11]), + .B2(\sel_1$1403 ), + .Y(\t$2054 ) + ); + XOR2x1_ASAP7_75t_R \U$698 ( + .A(\t$2054 ), + .B(a_registered[5]), + .Y(booth_b4_m11) + ); + AO22x1_ASAP7_75t_R \U$699 ( + .A1(b_registered[11]), + .A2(\sel_0$1402 ), + .B1(b_registered[12]), + .B2(\sel_1$1403 ), + .Y(\t$2055 ) + ); + XOR2x1_ASAP7_75t_R \U$700 ( + .A(\t$2055 ), + .B(a_registered[5]), + .Y(booth_b4_m12) + ); + AO22x1_ASAP7_75t_R \U$701 ( + .A1(b_registered[12]), + .A2(\sel_0$1402 ), + .B1(b_registered[13]), + .B2(\sel_1$1403 ), + .Y(\t$2056 ) + ); + XOR2x1_ASAP7_75t_R \U$702 ( + .A(\t$2056 ), + .B(a_registered[5]), + .Y(booth_b4_m13) + ); + AO22x1_ASAP7_75t_R \U$703 ( + .A1(b_registered[13]), + .A2(\sel_0$1402 ), + .B1(b_registered[14]), + .B2(\sel_1$1403 ), + .Y(\t$2057 ) + ); + XOR2x1_ASAP7_75t_R \U$704 ( + .A(\t$2057 ), + .B(a_registered[5]), + .Y(booth_b4_m14) + ); + AO22x1_ASAP7_75t_R \U$705 ( + .A1(b_registered[14]), + .A2(\sel_0$1402 ), + .B1(b_registered[15]), + .B2(\sel_1$1403 ), + .Y(\t$2058 ) + ); + XOR2x1_ASAP7_75t_R \U$706 ( + .A(\t$2058 ), + .B(a_registered[5]), + .Y(booth_b4_m15) + ); + AO22x1_ASAP7_75t_R \U$707 ( + .A1(b_registered[15]), + .A2(\sel_0$1402 ), + .B1(b_registered[16]), + .B2(\sel_1$1403 ), + .Y(\t$2059 ) + ); + XOR2x1_ASAP7_75t_R \U$708 ( + .A(\t$2059 ), + .B(a_registered[5]), + .Y(booth_b4_m16) + ); + AO22x1_ASAP7_75t_R \U$709 ( + .A1(b_registered[16]), + .A2(\sel_0$1402 ), + .B1(b_registered[17]), + .B2(\sel_1$1403 ), + .Y(\t$2060 ) + ); + XOR2x1_ASAP7_75t_R \U$710 ( + .A(\t$2060 ), + .B(a_registered[5]), + .Y(booth_b4_m17) + ); + AO22x1_ASAP7_75t_R \U$711 ( + .A1(b_registered[17]), + .A2(\sel_0$1402 ), + .B1(b_registered[18]), + .B2(\sel_1$1403 ), + .Y(\t$2061 ) + ); + XOR2x1_ASAP7_75t_R \U$712 ( + .A(\t$2061 ), + .B(a_registered[5]), + .Y(booth_b4_m18) + ); + AO22x1_ASAP7_75t_R \U$713 ( + .A1(b_registered[18]), + .A2(\sel_0$1402 ), + .B1(b_registered[19]), + .B2(\sel_1$1403 ), + .Y(\t$2062 ) + ); + XOR2x1_ASAP7_75t_R \U$714 ( + .A(\t$2062 ), + .B(a_registered[5]), + .Y(booth_b4_m19) + ); + AO22x1_ASAP7_75t_R \U$715 ( + .A1(b_registered[19]), + .A2(\sel_0$1402 ), + .B1(b_registered[20]), + .B2(\sel_1$1403 ), + .Y(\t$2063 ) + ); + XOR2x1_ASAP7_75t_R \U$716 ( + .A(\t$2063 ), + .B(a_registered[5]), + .Y(booth_b4_m20) + ); + AO22x1_ASAP7_75t_R \U$717 ( + .A1(b_registered[20]), + .A2(\sel_0$1402 ), + .B1(b_registered[21]), + .B2(\sel_1$1403 ), + .Y(\t$2064 ) + ); + XOR2x1_ASAP7_75t_R \U$718 ( + .A(\t$2064 ), + .B(a_registered[5]), + .Y(booth_b4_m21) + ); + AO22x1_ASAP7_75t_R \U$719 ( + .A1(b_registered[21]), + .A2(\sel_0$1402 ), + .B1(b_registered[22]), + .B2(\sel_1$1403 ), + .Y(\t$2065 ) + ); + XOR2x1_ASAP7_75t_R \U$720 ( + .A(\t$2065 ), + .B(a_registered[5]), + .Y(booth_b4_m22) + ); + AO22x1_ASAP7_75t_R \U$721 ( + .A1(b_registered[22]), + .A2(\sel_0$1402 ), + .B1(b_registered[23]), + .B2(\sel_1$1403 ), + .Y(\t$2066 ) + ); + XOR2x1_ASAP7_75t_R \U$722 ( + .A(\t$2066 ), + .B(a_registered[5]), + .Y(booth_b4_m23) + ); + AO22x1_ASAP7_75t_R \U$723 ( + .A1(b_registered[23]), + .A2(\sel_0$1402 ), + .B1(b_registered[24]), + .B2(\sel_1$1403 ), + .Y(\t$2067 ) + ); + XOR2x1_ASAP7_75t_R \U$724 ( + .A(\t$2067 ), + .B(a_registered[5]), + .Y(booth_b4_m24) + ); + AO22x1_ASAP7_75t_R \U$725 ( + .A1(b_registered[24]), + .A2(\sel_0$1402 ), + .B1(b_registered[25]), + .B2(\sel_1$1403 ), + .Y(\t$2068 ) + ); + XOR2x1_ASAP7_75t_R \U$726 ( + .A(\t$2068 ), + .B(a_registered[5]), + .Y(booth_b4_m25) + ); + AO22x1_ASAP7_75t_R \U$727 ( + .A1(b_registered[25]), + .A2(\sel_0$1402 ), + .B1(b_registered[26]), + .B2(\sel_1$1403 ), + .Y(\t$2069 ) + ); + XOR2x1_ASAP7_75t_R \U$728 ( + .A(\t$2069 ), + .B(a_registered[5]), + .Y(booth_b4_m26) + ); + AO22x1_ASAP7_75t_R \U$729 ( + .A1(b_registered[26]), + .A2(\sel_0$1402 ), + .B1(b_registered[27]), + .B2(\sel_1$1403 ), + .Y(\t$2070 ) + ); + XOR2x1_ASAP7_75t_R \U$730 ( + .A(\t$2070 ), + .B(a_registered[5]), + .Y(booth_b4_m27) + ); + AO22x1_ASAP7_75t_R \U$731 ( + .A1(b_registered[27]), + .A2(\sel_0$1402 ), + .B1(b_registered[28]), + .B2(\sel_1$1403 ), + .Y(\t$2071 ) + ); + XOR2x1_ASAP7_75t_R \U$732 ( + .A(\t$2071 ), + .B(a_registered[5]), + .Y(booth_b4_m28) + ); + AO22x1_ASAP7_75t_R \U$733 ( + .A1(b_registered[28]), + .A2(\sel_0$1402 ), + .B1(b_registered[29]), + .B2(\sel_1$1403 ), + .Y(\t$2072 ) + ); + XOR2x1_ASAP7_75t_R \U$734 ( + .A(\t$2072 ), + .B(a_registered[5]), + .Y(booth_b4_m29) + ); + AO22x1_ASAP7_75t_R \U$735 ( + .A1(b_registered[29]), + .A2(\sel_0$1402 ), + .B1(b_registered[30]), + .B2(\sel_1$1403 ), + .Y(\t$2073 ) + ); + XOR2x1_ASAP7_75t_R \U$736 ( + .A(\t$2073 ), + .B(a_registered[5]), + .Y(booth_b4_m30) + ); + AO22x1_ASAP7_75t_R \U$737 ( + .A1(b_registered[30]), + .A2(\sel_0$1402 ), + .B1(b_registered[31]), + .B2(\sel_1$1403 ), + .Y(\t$2074 ) + ); + XOR2x1_ASAP7_75t_R \U$738 ( + .A(\t$2074 ), + .B(a_registered[5]), + .Y(booth_b4_m31) + ); + AO22x1_ASAP7_75t_R \U$739 ( + .A1(b_registered[31]), + .A2(\sel_0$1402 ), + .B1(1'h0), + .B2(\sel_1$1403 ), + .Y(\t$2075 ) + ); + XOR2x1_ASAP7_75t_R \U$740 ( + .A(\t$2075 ), + .B(a_registered[5]), + .Y(booth_b4_m32) + ); + INVx1_ASAP7_75t_R \U$741 ( + .A(a_registered[5]), + .Y(\notsign$748 ) + ); + INVx1_ASAP7_75t_R \U$742 ( + .A(a_registered[5]), + .Y(\$10 ) + ); + INVx1_ASAP7_75t_R \U$743 ( + .A(a_registered[6]), + .Y(\$11 ) + ); + INVx1_ASAP7_75t_R \U$744 ( + .A(a_registered[7]), + .Y(\$12 ) + ); + AO33x2_ASAP7_75t_R \U$745 ( + .A1(\$12 ), + .A2(a_registered[6]), + .A3(a_registered[5]), + .B1(a_registered[7]), + .B2(\$11 ), + .B3(\$10 ), + .Y(\sel_0$1439 ) + ); + XOR2x1_ASAP7_75t_R \U$746 ( + .A(a_registered[6]), + .B(a_registered[5]), + .Y(\sel_1$1440 ) + ); + AO22x1_ASAP7_75t_R \U$747 ( + .A1(1'h0), + .A2(\sel_0$1439 ), + .B1(b_registered[0]), + .B2(\sel_1$1440 ), + .Y(\t$2077 ) + ); + XOR2x1_ASAP7_75t_R \U$748 ( + .A(\t$2077 ), + .B(a_registered[7]), + .Y(booth_b6_m0) + ); + AO22x1_ASAP7_75t_R \U$749 ( + .A1(b_registered[0]), + .A2(\sel_0$1439 ), + .B1(b_registered[1]), + .B2(\sel_1$1440 ), + .Y(\t$2078 ) + ); + XOR2x1_ASAP7_75t_R \U$750 ( + .A(\t$2078 ), + .B(a_registered[7]), + .Y(booth_b6_m1) + ); + AO22x1_ASAP7_75t_R \U$751 ( + .A1(b_registered[1]), + .A2(\sel_0$1439 ), + .B1(b_registered[2]), + .B2(\sel_1$1440 ), + .Y(\t$2079 ) + ); + XOR2x1_ASAP7_75t_R \U$752 ( + .A(\t$2079 ), + .B(a_registered[7]), + .Y(booth_b6_m2) + ); + AO22x1_ASAP7_75t_R \U$753 ( + .A1(b_registered[2]), + .A2(\sel_0$1439 ), + .B1(b_registered[3]), + .B2(\sel_1$1440 ), + .Y(\t$2080 ) + ); + XOR2x1_ASAP7_75t_R \U$754 ( + .A(\t$2080 ), + .B(a_registered[7]), + .Y(booth_b6_m3) + ); + AO22x1_ASAP7_75t_R \U$755 ( + .A1(b_registered[3]), + .A2(\sel_0$1439 ), + .B1(b_registered[4]), + .B2(\sel_1$1440 ), + .Y(\t$2081 ) + ); + XOR2x1_ASAP7_75t_R \U$756 ( + .A(\t$2081 ), + .B(a_registered[7]), + .Y(booth_b6_m4) + ); + AO22x1_ASAP7_75t_R \U$757 ( + .A1(b_registered[4]), + .A2(\sel_0$1439 ), + .B1(b_registered[5]), + .B2(\sel_1$1440 ), + .Y(\t$2082 ) + ); + XOR2x1_ASAP7_75t_R \U$758 ( + .A(\t$2082 ), + .B(a_registered[7]), + .Y(booth_b6_m5) + ); + AO22x1_ASAP7_75t_R \U$759 ( + .A1(b_registered[5]), + .A2(\sel_0$1439 ), + .B1(b_registered[6]), + .B2(\sel_1$1440 ), + .Y(\t$2083 ) + ); + XOR2x1_ASAP7_75t_R \U$760 ( + .A(\t$2083 ), + .B(a_registered[7]), + .Y(booth_b6_m6) + ); + AO22x1_ASAP7_75t_R \U$761 ( + .A1(b_registered[6]), + .A2(\sel_0$1439 ), + .B1(b_registered[7]), + .B2(\sel_1$1440 ), + .Y(\t$2084 ) + ); + XOR2x1_ASAP7_75t_R \U$762 ( + .A(\t$2084 ), + .B(a_registered[7]), + .Y(booth_b6_m7) + ); + AO22x1_ASAP7_75t_R \U$763 ( + .A1(b_registered[7]), + .A2(\sel_0$1439 ), + .B1(b_registered[8]), + .B2(\sel_1$1440 ), + .Y(\t$2085 ) + ); + XOR2x1_ASAP7_75t_R \U$764 ( + .A(\t$2085 ), + .B(a_registered[7]), + .Y(booth_b6_m8) + ); + AO22x1_ASAP7_75t_R \U$765 ( + .A1(b_registered[8]), + .A2(\sel_0$1439 ), + .B1(b_registered[9]), + .B2(\sel_1$1440 ), + .Y(\t$2086 ) + ); + XOR2x1_ASAP7_75t_R \U$766 ( + .A(\t$2086 ), + .B(a_registered[7]), + .Y(booth_b6_m9) + ); + AO22x1_ASAP7_75t_R \U$767 ( + .A1(b_registered[9]), + .A2(\sel_0$1439 ), + .B1(b_registered[10]), + .B2(\sel_1$1440 ), + .Y(\t$2087 ) + ); + XOR2x1_ASAP7_75t_R \U$768 ( + .A(\t$2087 ), + .B(a_registered[7]), + .Y(booth_b6_m10) + ); + AO22x1_ASAP7_75t_R \U$769 ( + .A1(b_registered[10]), + .A2(\sel_0$1439 ), + .B1(b_registered[11]), + .B2(\sel_1$1440 ), + .Y(\t$2088 ) + ); + XOR2x1_ASAP7_75t_R \U$770 ( + .A(\t$2088 ), + .B(a_registered[7]), + .Y(booth_b6_m11) + ); + AO22x1_ASAP7_75t_R \U$771 ( + .A1(b_registered[11]), + .A2(\sel_0$1439 ), + .B1(b_registered[12]), + .B2(\sel_1$1440 ), + .Y(\t$2089 ) + ); + XOR2x1_ASAP7_75t_R \U$772 ( + .A(\t$2089 ), + .B(a_registered[7]), + .Y(booth_b6_m12) + ); + AO22x1_ASAP7_75t_R \U$773 ( + .A1(b_registered[12]), + .A2(\sel_0$1439 ), + .B1(b_registered[13]), + .B2(\sel_1$1440 ), + .Y(\t$2090 ) + ); + XOR2x1_ASAP7_75t_R \U$774 ( + .A(\t$2090 ), + .B(a_registered[7]), + .Y(booth_b6_m13) + ); + AO22x1_ASAP7_75t_R \U$775 ( + .A1(b_registered[13]), + .A2(\sel_0$1439 ), + .B1(b_registered[14]), + .B2(\sel_1$1440 ), + .Y(\t$2091 ) + ); + XOR2x1_ASAP7_75t_R \U$776 ( + .A(\t$2091 ), + .B(a_registered[7]), + .Y(booth_b6_m14) + ); + AO22x1_ASAP7_75t_R \U$777 ( + .A1(b_registered[14]), + .A2(\sel_0$1439 ), + .B1(b_registered[15]), + .B2(\sel_1$1440 ), + .Y(\t$2092 ) + ); + XOR2x1_ASAP7_75t_R \U$778 ( + .A(\t$2092 ), + .B(a_registered[7]), + .Y(booth_b6_m15) + ); + AO22x1_ASAP7_75t_R \U$779 ( + .A1(b_registered[15]), + .A2(\sel_0$1439 ), + .B1(b_registered[16]), + .B2(\sel_1$1440 ), + .Y(\t$2093 ) + ); + XOR2x1_ASAP7_75t_R \U$780 ( + .A(\t$2093 ), + .B(a_registered[7]), + .Y(booth_b6_m16) + ); + AO22x1_ASAP7_75t_R \U$781 ( + .A1(b_registered[16]), + .A2(\sel_0$1439 ), + .B1(b_registered[17]), + .B2(\sel_1$1440 ), + .Y(\t$2094 ) + ); + XOR2x1_ASAP7_75t_R \U$782 ( + .A(\t$2094 ), + .B(a_registered[7]), + .Y(booth_b6_m17) + ); + AO22x1_ASAP7_75t_R \U$783 ( + .A1(b_registered[17]), + .A2(\sel_0$1439 ), + .B1(b_registered[18]), + .B2(\sel_1$1440 ), + .Y(\t$2095 ) + ); + XOR2x1_ASAP7_75t_R \U$784 ( + .A(\t$2095 ), + .B(a_registered[7]), + .Y(booth_b6_m18) + ); + AO22x1_ASAP7_75t_R \U$785 ( + .A1(b_registered[18]), + .A2(\sel_0$1439 ), + .B1(b_registered[19]), + .B2(\sel_1$1440 ), + .Y(\t$2096 ) + ); + XOR2x1_ASAP7_75t_R \U$786 ( + .A(\t$2096 ), + .B(a_registered[7]), + .Y(booth_b6_m19) + ); + AO22x1_ASAP7_75t_R \U$787 ( + .A1(b_registered[19]), + .A2(\sel_0$1439 ), + .B1(b_registered[20]), + .B2(\sel_1$1440 ), + .Y(\t$2097 ) + ); + XOR2x1_ASAP7_75t_R \U$788 ( + .A(\t$2097 ), + .B(a_registered[7]), + .Y(booth_b6_m20) + ); + AO22x1_ASAP7_75t_R \U$789 ( + .A1(b_registered[20]), + .A2(\sel_0$1439 ), + .B1(b_registered[21]), + .B2(\sel_1$1440 ), + .Y(\t$2098 ) + ); + XOR2x1_ASAP7_75t_R \U$790 ( + .A(\t$2098 ), + .B(a_registered[7]), + .Y(booth_b6_m21) + ); + AO22x1_ASAP7_75t_R \U$791 ( + .A1(b_registered[21]), + .A2(\sel_0$1439 ), + .B1(b_registered[22]), + .B2(\sel_1$1440 ), + .Y(\t$2099 ) + ); + XOR2x1_ASAP7_75t_R \U$792 ( + .A(\t$2099 ), + .B(a_registered[7]), + .Y(booth_b6_m22) + ); + AO22x1_ASAP7_75t_R \U$793 ( + .A1(b_registered[22]), + .A2(\sel_0$1439 ), + .B1(b_registered[23]), + .B2(\sel_1$1440 ), + .Y(\t$2100 ) + ); + XOR2x1_ASAP7_75t_R \U$794 ( + .A(\t$2100 ), + .B(a_registered[7]), + .Y(booth_b6_m23) + ); + AO22x1_ASAP7_75t_R \U$795 ( + .A1(b_registered[23]), + .A2(\sel_0$1439 ), + .B1(b_registered[24]), + .B2(\sel_1$1440 ), + .Y(\t$2101 ) + ); + XOR2x1_ASAP7_75t_R \U$796 ( + .A(\t$2101 ), + .B(a_registered[7]), + .Y(booth_b6_m24) + ); + AO22x1_ASAP7_75t_R \U$797 ( + .A1(b_registered[24]), + .A2(\sel_0$1439 ), + .B1(b_registered[25]), + .B2(\sel_1$1440 ), + .Y(\t$2102 ) + ); + XOR2x1_ASAP7_75t_R \U$798 ( + .A(\t$2102 ), + .B(a_registered[7]), + .Y(booth_b6_m25) + ); + AO22x1_ASAP7_75t_R \U$799 ( + .A1(b_registered[25]), + .A2(\sel_0$1439 ), + .B1(b_registered[26]), + .B2(\sel_1$1440 ), + .Y(\t$2103 ) + ); + XOR2x1_ASAP7_75t_R \U$800 ( + .A(\t$2103 ), + .B(a_registered[7]), + .Y(booth_b6_m26) + ); + AO22x1_ASAP7_75t_R \U$801 ( + .A1(b_registered[26]), + .A2(\sel_0$1439 ), + .B1(b_registered[27]), + .B2(\sel_1$1440 ), + .Y(\t$2104 ) + ); + XOR2x1_ASAP7_75t_R \U$802 ( + .A(\t$2104 ), + .B(a_registered[7]), + .Y(booth_b6_m27) + ); + AO22x1_ASAP7_75t_R \U$803 ( + .A1(b_registered[27]), + .A2(\sel_0$1439 ), + .B1(b_registered[28]), + .B2(\sel_1$1440 ), + .Y(\t$2105 ) + ); + XOR2x1_ASAP7_75t_R \U$804 ( + .A(\t$2105 ), + .B(a_registered[7]), + .Y(booth_b6_m28) + ); + AO22x1_ASAP7_75t_R \U$805 ( + .A1(b_registered[28]), + .A2(\sel_0$1439 ), + .B1(b_registered[29]), + .B2(\sel_1$1440 ), + .Y(\t$2106 ) + ); + XOR2x1_ASAP7_75t_R \U$806 ( + .A(\t$2106 ), + .B(a_registered[7]), + .Y(booth_b6_m29) + ); + AO22x1_ASAP7_75t_R \U$807 ( + .A1(b_registered[29]), + .A2(\sel_0$1439 ), + .B1(b_registered[30]), + .B2(\sel_1$1440 ), + .Y(\t$2107 ) + ); + XOR2x1_ASAP7_75t_R \U$808 ( + .A(\t$2107 ), + .B(a_registered[7]), + .Y(booth_b6_m30) + ); + AO22x1_ASAP7_75t_R \U$809 ( + .A1(b_registered[30]), + .A2(\sel_0$1439 ), + .B1(b_registered[31]), + .B2(\sel_1$1440 ), + .Y(\t$2108 ) + ); + XOR2x1_ASAP7_75t_R \U$810 ( + .A(\t$2108 ), + .B(a_registered[7]), + .Y(booth_b6_m31) + ); + AO22x1_ASAP7_75t_R \U$811 ( + .A1(b_registered[31]), + .A2(\sel_0$1439 ), + .B1(1'h0), + .B2(\sel_1$1440 ), + .Y(\t$2109 ) + ); + XOR2x1_ASAP7_75t_R \U$812 ( + .A(\t$2109 ), + .B(a_registered[7]), + .Y(booth_b6_m32) + ); + INVx1_ASAP7_75t_R \U$813 ( + .A(a_registered[7]), + .Y(\notsign$806 ) + ); + INVx1_ASAP7_75t_R \U$814 ( + .A(a_registered[7]), + .Y(\$13 ) + ); + INVx1_ASAP7_75t_R \U$815 ( + .A(a_registered[8]), + .Y(\$14 ) + ); + INVx1_ASAP7_75t_R \U$816 ( + .A(a_registered[9]), + .Y(\$15 ) + ); + AO33x2_ASAP7_75t_R \U$817 ( + .A1(\$15 ), + .A2(a_registered[8]), + .A3(a_registered[7]), + .B1(a_registered[9]), + .B2(\$14 ), + .B3(\$13 ), + .Y(\sel_0$1476 ) + ); + XOR2x1_ASAP7_75t_R \U$818 ( + .A(a_registered[8]), + .B(a_registered[7]), + .Y(\sel_1$1477 ) + ); + AO22x1_ASAP7_75t_R \U$819 ( + .A1(1'h0), + .A2(\sel_0$1476 ), + .B1(b_registered[0]), + .B2(\sel_1$1477 ), + .Y(\t$2111 ) + ); + XOR2x1_ASAP7_75t_R \U$820 ( + .A(\t$2111 ), + .B(a_registered[9]), + .Y(booth_b8_m0) + ); + AO22x1_ASAP7_75t_R \U$821 ( + .A1(b_registered[0]), + .A2(\sel_0$1476 ), + .B1(b_registered[1]), + .B2(\sel_1$1477 ), + .Y(\t$2112 ) + ); + XOR2x1_ASAP7_75t_R \U$822 ( + .A(\t$2112 ), + .B(a_registered[9]), + .Y(booth_b8_m1) + ); + AO22x1_ASAP7_75t_R \U$823 ( + .A1(b_registered[1]), + .A2(\sel_0$1476 ), + .B1(b_registered[2]), + .B2(\sel_1$1477 ), + .Y(\t$2113 ) + ); + XOR2x1_ASAP7_75t_R \U$824 ( + .A(\t$2113 ), + .B(a_registered[9]), + .Y(booth_b8_m2) + ); + AO22x1_ASAP7_75t_R \U$825 ( + .A1(b_registered[2]), + .A2(\sel_0$1476 ), + .B1(b_registered[3]), + .B2(\sel_1$1477 ), + .Y(\t$2114 ) + ); + XOR2x1_ASAP7_75t_R \U$826 ( + .A(\t$2114 ), + .B(a_registered[9]), + .Y(booth_b8_m3) + ); + AO22x1_ASAP7_75t_R \U$827 ( + .A1(b_registered[3]), + .A2(\sel_0$1476 ), + .B1(b_registered[4]), + .B2(\sel_1$1477 ), + .Y(\t$2115 ) + ); + XOR2x1_ASAP7_75t_R \U$828 ( + .A(\t$2115 ), + .B(a_registered[9]), + .Y(booth_b8_m4) + ); + AO22x1_ASAP7_75t_R \U$829 ( + .A1(b_registered[4]), + .A2(\sel_0$1476 ), + .B1(b_registered[5]), + .B2(\sel_1$1477 ), + .Y(\t$2116 ) + ); + XOR2x1_ASAP7_75t_R \U$830 ( + .A(\t$2116 ), + .B(a_registered[9]), + .Y(booth_b8_m5) + ); + AO22x1_ASAP7_75t_R \U$831 ( + .A1(b_registered[5]), + .A2(\sel_0$1476 ), + .B1(b_registered[6]), + .B2(\sel_1$1477 ), + .Y(\t$2117 ) + ); + XOR2x1_ASAP7_75t_R \U$832 ( + .A(\t$2117 ), + .B(a_registered[9]), + .Y(booth_b8_m6) + ); + AO22x1_ASAP7_75t_R \U$833 ( + .A1(b_registered[6]), + .A2(\sel_0$1476 ), + .B1(b_registered[7]), + .B2(\sel_1$1477 ), + .Y(\t$2118 ) + ); + XOR2x1_ASAP7_75t_R \U$834 ( + .A(\t$2118 ), + .B(a_registered[9]), + .Y(booth_b8_m7) + ); + AO22x1_ASAP7_75t_R \U$835 ( + .A1(b_registered[7]), + .A2(\sel_0$1476 ), + .B1(b_registered[8]), + .B2(\sel_1$1477 ), + .Y(\t$2119 ) + ); + XOR2x1_ASAP7_75t_R \U$836 ( + .A(\t$2119 ), + .B(a_registered[9]), + .Y(booth_b8_m8) + ); + AO22x1_ASAP7_75t_R \U$837 ( + .A1(b_registered[8]), + .A2(\sel_0$1476 ), + .B1(b_registered[9]), + .B2(\sel_1$1477 ), + .Y(\t$2120 ) + ); + XOR2x1_ASAP7_75t_R \U$838 ( + .A(\t$2120 ), + .B(a_registered[9]), + .Y(booth_b8_m9) + ); + AO22x1_ASAP7_75t_R \U$839 ( + .A1(b_registered[9]), + .A2(\sel_0$1476 ), + .B1(b_registered[10]), + .B2(\sel_1$1477 ), + .Y(\t$2121 ) + ); + XOR2x1_ASAP7_75t_R \U$840 ( + .A(\t$2121 ), + .B(a_registered[9]), + .Y(booth_b8_m10) + ); + AO22x1_ASAP7_75t_R \U$841 ( + .A1(b_registered[10]), + .A2(\sel_0$1476 ), + .B1(b_registered[11]), + .B2(\sel_1$1477 ), + .Y(\t$2122 ) + ); + XOR2x1_ASAP7_75t_R \U$842 ( + .A(\t$2122 ), + .B(a_registered[9]), + .Y(booth_b8_m11) + ); + AO22x1_ASAP7_75t_R \U$843 ( + .A1(b_registered[11]), + .A2(\sel_0$1476 ), + .B1(b_registered[12]), + .B2(\sel_1$1477 ), + .Y(\t$2123 ) + ); + XOR2x1_ASAP7_75t_R \U$844 ( + .A(\t$2123 ), + .B(a_registered[9]), + .Y(booth_b8_m12) + ); + AO22x1_ASAP7_75t_R \U$845 ( + .A1(b_registered[12]), + .A2(\sel_0$1476 ), + .B1(b_registered[13]), + .B2(\sel_1$1477 ), + .Y(\t$2124 ) + ); + XOR2x1_ASAP7_75t_R \U$846 ( + .A(\t$2124 ), + .B(a_registered[9]), + .Y(booth_b8_m13) + ); + AO22x1_ASAP7_75t_R \U$847 ( + .A1(b_registered[13]), + .A2(\sel_0$1476 ), + .B1(b_registered[14]), + .B2(\sel_1$1477 ), + .Y(\t$2125 ) + ); + XOR2x1_ASAP7_75t_R \U$848 ( + .A(\t$2125 ), + .B(a_registered[9]), + .Y(booth_b8_m14) + ); + AO22x1_ASAP7_75t_R \U$849 ( + .A1(b_registered[14]), + .A2(\sel_0$1476 ), + .B1(b_registered[15]), + .B2(\sel_1$1477 ), + .Y(\t$2126 ) + ); + XOR2x1_ASAP7_75t_R \U$850 ( + .A(\t$2126 ), + .B(a_registered[9]), + .Y(booth_b8_m15) + ); + AO22x1_ASAP7_75t_R \U$851 ( + .A1(b_registered[15]), + .A2(\sel_0$1476 ), + .B1(b_registered[16]), + .B2(\sel_1$1477 ), + .Y(\t$2127 ) + ); + XOR2x1_ASAP7_75t_R \U$852 ( + .A(\t$2127 ), + .B(a_registered[9]), + .Y(booth_b8_m16) + ); + AO22x1_ASAP7_75t_R \U$853 ( + .A1(b_registered[16]), + .A2(\sel_0$1476 ), + .B1(b_registered[17]), + .B2(\sel_1$1477 ), + .Y(\t$2128 ) + ); + XOR2x1_ASAP7_75t_R \U$854 ( + .A(\t$2128 ), + .B(a_registered[9]), + .Y(booth_b8_m17) + ); + AO22x1_ASAP7_75t_R \U$855 ( + .A1(b_registered[17]), + .A2(\sel_0$1476 ), + .B1(b_registered[18]), + .B2(\sel_1$1477 ), + .Y(\t$2129 ) + ); + XOR2x1_ASAP7_75t_R \U$856 ( + .A(\t$2129 ), + .B(a_registered[9]), + .Y(booth_b8_m18) + ); + AO22x1_ASAP7_75t_R \U$857 ( + .A1(b_registered[18]), + .A2(\sel_0$1476 ), + .B1(b_registered[19]), + .B2(\sel_1$1477 ), + .Y(\t$2130 ) + ); + XOR2x1_ASAP7_75t_R \U$858 ( + .A(\t$2130 ), + .B(a_registered[9]), + .Y(booth_b8_m19) + ); + AO22x1_ASAP7_75t_R \U$859 ( + .A1(b_registered[19]), + .A2(\sel_0$1476 ), + .B1(b_registered[20]), + .B2(\sel_1$1477 ), + .Y(\t$2131 ) + ); + XOR2x1_ASAP7_75t_R \U$860 ( + .A(\t$2131 ), + .B(a_registered[9]), + .Y(booth_b8_m20) + ); + AO22x1_ASAP7_75t_R \U$861 ( + .A1(b_registered[20]), + .A2(\sel_0$1476 ), + .B1(b_registered[21]), + .B2(\sel_1$1477 ), + .Y(\t$2132 ) + ); + XOR2x1_ASAP7_75t_R \U$862 ( + .A(\t$2132 ), + .B(a_registered[9]), + .Y(booth_b8_m21) + ); + AO22x1_ASAP7_75t_R \U$863 ( + .A1(b_registered[21]), + .A2(\sel_0$1476 ), + .B1(b_registered[22]), + .B2(\sel_1$1477 ), + .Y(\t$2133 ) + ); + XOR2x1_ASAP7_75t_R \U$864 ( + .A(\t$2133 ), + .B(a_registered[9]), + .Y(booth_b8_m22) + ); + AO22x1_ASAP7_75t_R \U$865 ( + .A1(b_registered[22]), + .A2(\sel_0$1476 ), + .B1(b_registered[23]), + .B2(\sel_1$1477 ), + .Y(\t$2134 ) + ); + XOR2x1_ASAP7_75t_R \U$866 ( + .A(\t$2134 ), + .B(a_registered[9]), + .Y(booth_b8_m23) + ); + AO22x1_ASAP7_75t_R \U$867 ( + .A1(b_registered[23]), + .A2(\sel_0$1476 ), + .B1(b_registered[24]), + .B2(\sel_1$1477 ), + .Y(\t$2135 ) + ); + XOR2x1_ASAP7_75t_R \U$868 ( + .A(\t$2135 ), + .B(a_registered[9]), + .Y(booth_b8_m24) + ); + AO22x1_ASAP7_75t_R \U$869 ( + .A1(b_registered[24]), + .A2(\sel_0$1476 ), + .B1(b_registered[25]), + .B2(\sel_1$1477 ), + .Y(\t$2136 ) + ); + XOR2x1_ASAP7_75t_R \U$870 ( + .A(\t$2136 ), + .B(a_registered[9]), + .Y(booth_b8_m25) + ); + AO22x1_ASAP7_75t_R \U$871 ( + .A1(b_registered[25]), + .A2(\sel_0$1476 ), + .B1(b_registered[26]), + .B2(\sel_1$1477 ), + .Y(\t$2137 ) + ); + XOR2x1_ASAP7_75t_R \U$872 ( + .A(\t$2137 ), + .B(a_registered[9]), + .Y(booth_b8_m26) + ); + AO22x1_ASAP7_75t_R \U$873 ( + .A1(b_registered[26]), + .A2(\sel_0$1476 ), + .B1(b_registered[27]), + .B2(\sel_1$1477 ), + .Y(\t$2138 ) + ); + XOR2x1_ASAP7_75t_R \U$874 ( + .A(\t$2138 ), + .B(a_registered[9]), + .Y(booth_b8_m27) + ); + AO22x1_ASAP7_75t_R \U$875 ( + .A1(b_registered[27]), + .A2(\sel_0$1476 ), + .B1(b_registered[28]), + .B2(\sel_1$1477 ), + .Y(\t$2139 ) + ); + XOR2x1_ASAP7_75t_R \U$876 ( + .A(\t$2139 ), + .B(a_registered[9]), + .Y(booth_b8_m28) + ); + AO22x1_ASAP7_75t_R \U$877 ( + .A1(b_registered[28]), + .A2(\sel_0$1476 ), + .B1(b_registered[29]), + .B2(\sel_1$1477 ), + .Y(\t$2140 ) + ); + XOR2x1_ASAP7_75t_R \U$878 ( + .A(\t$2140 ), + .B(a_registered[9]), + .Y(booth_b8_m29) + ); + AO22x1_ASAP7_75t_R \U$879 ( + .A1(b_registered[29]), + .A2(\sel_0$1476 ), + .B1(b_registered[30]), + .B2(\sel_1$1477 ), + .Y(\t$2141 ) + ); + XOR2x1_ASAP7_75t_R \U$880 ( + .A(\t$2141 ), + .B(a_registered[9]), + .Y(booth_b8_m30) + ); + AO22x1_ASAP7_75t_R \U$881 ( + .A1(b_registered[30]), + .A2(\sel_0$1476 ), + .B1(b_registered[31]), + .B2(\sel_1$1477 ), + .Y(\t$2142 ) + ); + XOR2x1_ASAP7_75t_R \U$882 ( + .A(\t$2142 ), + .B(a_registered[9]), + .Y(booth_b8_m31) + ); + AO22x1_ASAP7_75t_R \U$883 ( + .A1(b_registered[31]), + .A2(\sel_0$1476 ), + .B1(1'h0), + .B2(\sel_1$1477 ), + .Y(\t$2143 ) + ); + XOR2x1_ASAP7_75t_R \U$884 ( + .A(\t$2143 ), + .B(a_registered[9]), + .Y(booth_b8_m32) + ); + INVx1_ASAP7_75t_R \U$885 ( + .A(a_registered[9]), + .Y(\notsign$860 ) + ); + INVx1_ASAP7_75t_R \U$886 ( + .A(a_registered[9]), + .Y(\$16 ) + ); + INVx1_ASAP7_75t_R \U$887 ( + .A(a_registered[10]), + .Y(\$17 ) + ); + INVx1_ASAP7_75t_R \U$888 ( + .A(a_registered[11]), + .Y(\$18 ) + ); + AO33x2_ASAP7_75t_R \U$889 ( + .A1(\$18 ), + .A2(a_registered[10]), + .A3(a_registered[9]), + .B1(a_registered[11]), + .B2(\$17 ), + .B3(\$16 ), + .Y(\sel_0$1513 ) + ); + XOR2x1_ASAP7_75t_R \U$890 ( + .A(a_registered[10]), + .B(a_registered[9]), + .Y(\sel_1$1514 ) + ); + AO22x1_ASAP7_75t_R \U$891 ( + .A1(1'h0), + .A2(\sel_0$1513 ), + .B1(b_registered[0]), + .B2(\sel_1$1514 ), + .Y(\t$2145 ) + ); + XOR2x1_ASAP7_75t_R \U$892 ( + .A(\t$2145 ), + .B(a_registered[11]), + .Y(booth_b10_m0) + ); + AO22x1_ASAP7_75t_R \U$893 ( + .A1(b_registered[0]), + .A2(\sel_0$1513 ), + .B1(b_registered[1]), + .B2(\sel_1$1514 ), + .Y(\t$2146 ) + ); + XOR2x1_ASAP7_75t_R \U$894 ( + .A(\t$2146 ), + .B(a_registered[11]), + .Y(booth_b10_m1) + ); + AO22x1_ASAP7_75t_R \U$895 ( + .A1(b_registered[1]), + .A2(\sel_0$1513 ), + .B1(b_registered[2]), + .B2(\sel_1$1514 ), + .Y(\t$2147 ) + ); + XOR2x1_ASAP7_75t_R \U$896 ( + .A(\t$2147 ), + .B(a_registered[11]), + .Y(booth_b10_m2) + ); + AO22x1_ASAP7_75t_R \U$897 ( + .A1(b_registered[2]), + .A2(\sel_0$1513 ), + .B1(b_registered[3]), + .B2(\sel_1$1514 ), + .Y(\t$2148 ) + ); + XOR2x1_ASAP7_75t_R \U$898 ( + .A(\t$2148 ), + .B(a_registered[11]), + .Y(booth_b10_m3) + ); + AO22x1_ASAP7_75t_R \U$899 ( + .A1(b_registered[3]), + .A2(\sel_0$1513 ), + .B1(b_registered[4]), + .B2(\sel_1$1514 ), + .Y(\t$2149 ) + ); + XOR2x1_ASAP7_75t_R \U$900 ( + .A(\t$2149 ), + .B(a_registered[11]), + .Y(booth_b10_m4) + ); + AO22x1_ASAP7_75t_R \U$901 ( + .A1(b_registered[4]), + .A2(\sel_0$1513 ), + .B1(b_registered[5]), + .B2(\sel_1$1514 ), + .Y(\t$2150 ) + ); + XOR2x1_ASAP7_75t_R \U$902 ( + .A(\t$2150 ), + .B(a_registered[11]), + .Y(booth_b10_m5) + ); + AO22x1_ASAP7_75t_R \U$903 ( + .A1(b_registered[5]), + .A2(\sel_0$1513 ), + .B1(b_registered[6]), + .B2(\sel_1$1514 ), + .Y(\t$2151 ) + ); + XOR2x1_ASAP7_75t_R \U$904 ( + .A(\t$2151 ), + .B(a_registered[11]), + .Y(booth_b10_m6) + ); + AO22x1_ASAP7_75t_R \U$905 ( + .A1(b_registered[6]), + .A2(\sel_0$1513 ), + .B1(b_registered[7]), + .B2(\sel_1$1514 ), + .Y(\t$2152 ) + ); + XOR2x1_ASAP7_75t_R \U$906 ( + .A(\t$2152 ), + .B(a_registered[11]), + .Y(booth_b10_m7) + ); + AO22x1_ASAP7_75t_R \U$907 ( + .A1(b_registered[7]), + .A2(\sel_0$1513 ), + .B1(b_registered[8]), + .B2(\sel_1$1514 ), + .Y(\t$2153 ) + ); + XOR2x1_ASAP7_75t_R \U$908 ( + .A(\t$2153 ), + .B(a_registered[11]), + .Y(booth_b10_m8) + ); + AO22x1_ASAP7_75t_R \U$909 ( + .A1(b_registered[8]), + .A2(\sel_0$1513 ), + .B1(b_registered[9]), + .B2(\sel_1$1514 ), + .Y(\t$2154 ) + ); + XOR2x1_ASAP7_75t_R \U$910 ( + .A(\t$2154 ), + .B(a_registered[11]), + .Y(booth_b10_m9) + ); + AO22x1_ASAP7_75t_R \U$911 ( + .A1(b_registered[9]), + .A2(\sel_0$1513 ), + .B1(b_registered[10]), + .B2(\sel_1$1514 ), + .Y(\t$2155 ) + ); + XOR2x1_ASAP7_75t_R \U$912 ( + .A(\t$2155 ), + .B(a_registered[11]), + .Y(booth_b10_m10) + ); + AO22x1_ASAP7_75t_R \U$913 ( + .A1(b_registered[10]), + .A2(\sel_0$1513 ), + .B1(b_registered[11]), + .B2(\sel_1$1514 ), + .Y(\t$2156 ) + ); + XOR2x1_ASAP7_75t_R \U$914 ( + .A(\t$2156 ), + .B(a_registered[11]), + .Y(booth_b10_m11) + ); + AO22x1_ASAP7_75t_R \U$915 ( + .A1(b_registered[11]), + .A2(\sel_0$1513 ), + .B1(b_registered[12]), + .B2(\sel_1$1514 ), + .Y(\t$2157 ) + ); + XOR2x1_ASAP7_75t_R \U$916 ( + .A(\t$2157 ), + .B(a_registered[11]), + .Y(booth_b10_m12) + ); + AO22x1_ASAP7_75t_R \U$917 ( + .A1(b_registered[12]), + .A2(\sel_0$1513 ), + .B1(b_registered[13]), + .B2(\sel_1$1514 ), + .Y(\t$2158 ) + ); + XOR2x1_ASAP7_75t_R \U$918 ( + .A(\t$2158 ), + .B(a_registered[11]), + .Y(booth_b10_m13) + ); + AO22x1_ASAP7_75t_R \U$919 ( + .A1(b_registered[13]), + .A2(\sel_0$1513 ), + .B1(b_registered[14]), + .B2(\sel_1$1514 ), + .Y(\t$2159 ) + ); + XOR2x1_ASAP7_75t_R \U$920 ( + .A(\t$2159 ), + .B(a_registered[11]), + .Y(booth_b10_m14) + ); + AO22x1_ASAP7_75t_R \U$921 ( + .A1(b_registered[14]), + .A2(\sel_0$1513 ), + .B1(b_registered[15]), + .B2(\sel_1$1514 ), + .Y(\t$2160 ) + ); + XOR2x1_ASAP7_75t_R \U$922 ( + .A(\t$2160 ), + .B(a_registered[11]), + .Y(booth_b10_m15) + ); + AO22x1_ASAP7_75t_R \U$923 ( + .A1(b_registered[15]), + .A2(\sel_0$1513 ), + .B1(b_registered[16]), + .B2(\sel_1$1514 ), + .Y(\t$2161 ) + ); + XOR2x1_ASAP7_75t_R \U$924 ( + .A(\t$2161 ), + .B(a_registered[11]), + .Y(booth_b10_m16) + ); + AO22x1_ASAP7_75t_R \U$925 ( + .A1(b_registered[16]), + .A2(\sel_0$1513 ), + .B1(b_registered[17]), + .B2(\sel_1$1514 ), + .Y(\t$2162 ) + ); + XOR2x1_ASAP7_75t_R \U$926 ( + .A(\t$2162 ), + .B(a_registered[11]), + .Y(booth_b10_m17) + ); + AO22x1_ASAP7_75t_R \U$927 ( + .A1(b_registered[17]), + .A2(\sel_0$1513 ), + .B1(b_registered[18]), + .B2(\sel_1$1514 ), + .Y(\t$2163 ) + ); + XOR2x1_ASAP7_75t_R \U$928 ( + .A(\t$2163 ), + .B(a_registered[11]), + .Y(booth_b10_m18) + ); + AO22x1_ASAP7_75t_R \U$929 ( + .A1(b_registered[18]), + .A2(\sel_0$1513 ), + .B1(b_registered[19]), + .B2(\sel_1$1514 ), + .Y(\t$2164 ) + ); + XOR2x1_ASAP7_75t_R \U$930 ( + .A(\t$2164 ), + .B(a_registered[11]), + .Y(booth_b10_m19) + ); + AO22x1_ASAP7_75t_R \U$931 ( + .A1(b_registered[19]), + .A2(\sel_0$1513 ), + .B1(b_registered[20]), + .B2(\sel_1$1514 ), + .Y(\t$2165 ) + ); + XOR2x1_ASAP7_75t_R \U$932 ( + .A(\t$2165 ), + .B(a_registered[11]), + .Y(booth_b10_m20) + ); + AO22x1_ASAP7_75t_R \U$933 ( + .A1(b_registered[20]), + .A2(\sel_0$1513 ), + .B1(b_registered[21]), + .B2(\sel_1$1514 ), + .Y(\t$2166 ) + ); + XOR2x1_ASAP7_75t_R \U$934 ( + .A(\t$2166 ), + .B(a_registered[11]), + .Y(booth_b10_m21) + ); + AO22x1_ASAP7_75t_R \U$935 ( + .A1(b_registered[21]), + .A2(\sel_0$1513 ), + .B1(b_registered[22]), + .B2(\sel_1$1514 ), + .Y(\t$2167 ) + ); + XOR2x1_ASAP7_75t_R \U$936 ( + .A(\t$2167 ), + .B(a_registered[11]), + .Y(booth_b10_m22) + ); + AO22x1_ASAP7_75t_R \U$937 ( + .A1(b_registered[22]), + .A2(\sel_0$1513 ), + .B1(b_registered[23]), + .B2(\sel_1$1514 ), + .Y(\t$2168 ) + ); + XOR2x1_ASAP7_75t_R \U$938 ( + .A(\t$2168 ), + .B(a_registered[11]), + .Y(booth_b10_m23) + ); + AO22x1_ASAP7_75t_R \U$939 ( + .A1(b_registered[23]), + .A2(\sel_0$1513 ), + .B1(b_registered[24]), + .B2(\sel_1$1514 ), + .Y(\t$2169 ) + ); + XOR2x1_ASAP7_75t_R \U$940 ( + .A(\t$2169 ), + .B(a_registered[11]), + .Y(booth_b10_m24) + ); + AO22x1_ASAP7_75t_R \U$941 ( + .A1(b_registered[24]), + .A2(\sel_0$1513 ), + .B1(b_registered[25]), + .B2(\sel_1$1514 ), + .Y(\t$2170 ) + ); + XOR2x1_ASAP7_75t_R \U$942 ( + .A(\t$2170 ), + .B(a_registered[11]), + .Y(booth_b10_m25) + ); + AO22x1_ASAP7_75t_R \U$943 ( + .A1(b_registered[25]), + .A2(\sel_0$1513 ), + .B1(b_registered[26]), + .B2(\sel_1$1514 ), + .Y(\t$2171 ) + ); + XOR2x1_ASAP7_75t_R \U$944 ( + .A(\t$2171 ), + .B(a_registered[11]), + .Y(booth_b10_m26) + ); + AO22x1_ASAP7_75t_R \U$945 ( + .A1(b_registered[26]), + .A2(\sel_0$1513 ), + .B1(b_registered[27]), + .B2(\sel_1$1514 ), + .Y(\t$2172 ) + ); + XOR2x1_ASAP7_75t_R \U$946 ( + .A(\t$2172 ), + .B(a_registered[11]), + .Y(booth_b10_m27) + ); + AO22x1_ASAP7_75t_R \U$947 ( + .A1(b_registered[27]), + .A2(\sel_0$1513 ), + .B1(b_registered[28]), + .B2(\sel_1$1514 ), + .Y(\t$2173 ) + ); + XOR2x1_ASAP7_75t_R \U$948 ( + .A(\t$2173 ), + .B(a_registered[11]), + .Y(booth_b10_m28) + ); + AO22x1_ASAP7_75t_R \U$949 ( + .A1(b_registered[28]), + .A2(\sel_0$1513 ), + .B1(b_registered[29]), + .B2(\sel_1$1514 ), + .Y(\t$2174 ) + ); + XOR2x1_ASAP7_75t_R \U$950 ( + .A(\t$2174 ), + .B(a_registered[11]), + .Y(booth_b10_m29) + ); + AO22x1_ASAP7_75t_R \U$951 ( + .A1(b_registered[29]), + .A2(\sel_0$1513 ), + .B1(b_registered[30]), + .B2(\sel_1$1514 ), + .Y(\t$2175 ) + ); + XOR2x1_ASAP7_75t_R \U$952 ( + .A(\t$2175 ), + .B(a_registered[11]), + .Y(booth_b10_m30) + ); + AO22x1_ASAP7_75t_R \U$953 ( + .A1(b_registered[30]), + .A2(\sel_0$1513 ), + .B1(b_registered[31]), + .B2(\sel_1$1514 ), + .Y(\t$2176 ) + ); + XOR2x1_ASAP7_75t_R \U$954 ( + .A(\t$2176 ), + .B(a_registered[11]), + .Y(booth_b10_m31) + ); + AO22x1_ASAP7_75t_R \U$955 ( + .A1(b_registered[31]), + .A2(\sel_0$1513 ), + .B1(1'h0), + .B2(\sel_1$1514 ), + .Y(\t$2177 ) + ); + XOR2x1_ASAP7_75t_R \U$956 ( + .A(\t$2177 ), + .B(a_registered[11]), + .Y(booth_b10_m32) + ); + INVx1_ASAP7_75t_R \U$957 ( + .A(a_registered[11]), + .Y(\notsign$910 ) + ); + INVx1_ASAP7_75t_R \U$958 ( + .A(a_registered[11]), + .Y(\$19 ) + ); + INVx1_ASAP7_75t_R \U$959 ( + .A(a_registered[12]), + .Y(\$20 ) + ); + INVx1_ASAP7_75t_R \U$960 ( + .A(a_registered[13]), + .Y(\$21 ) + ); + AO33x2_ASAP7_75t_R \U$961 ( + .A1(\$21 ), + .A2(a_registered[12]), + .A3(a_registered[11]), + .B1(a_registered[13]), + .B2(\$20 ), + .B3(\$19 ), + .Y(\sel_0$1550 ) + ); + XOR2x1_ASAP7_75t_R \U$962 ( + .A(a_registered[12]), + .B(a_registered[11]), + .Y(\sel_1$1551 ) + ); + AO22x1_ASAP7_75t_R \U$963 ( + .A1(1'h0), + .A2(\sel_0$1550 ), + .B1(b_registered[0]), + .B2(\sel_1$1551 ), + .Y(\t$2179 ) + ); + XOR2x1_ASAP7_75t_R \U$964 ( + .A(\t$2179 ), + .B(a_registered[13]), + .Y(booth_b12_m0) + ); + AO22x1_ASAP7_75t_R \U$965 ( + .A1(b_registered[0]), + .A2(\sel_0$1550 ), + .B1(b_registered[1]), + .B2(\sel_1$1551 ), + .Y(\t$2180 ) + ); + XOR2x1_ASAP7_75t_R \U$966 ( + .A(\t$2180 ), + .B(a_registered[13]), + .Y(booth_b12_m1) + ); + AO22x1_ASAP7_75t_R \U$967 ( + .A1(b_registered[1]), + .A2(\sel_0$1550 ), + .B1(b_registered[2]), + .B2(\sel_1$1551 ), + .Y(\t$2181 ) + ); + XOR2x1_ASAP7_75t_R \U$968 ( + .A(\t$2181 ), + .B(a_registered[13]), + .Y(booth_b12_m2) + ); + AO22x1_ASAP7_75t_R \U$969 ( + .A1(b_registered[2]), + .A2(\sel_0$1550 ), + .B1(b_registered[3]), + .B2(\sel_1$1551 ), + .Y(\t$2182 ) + ); + XOR2x1_ASAP7_75t_R \U$970 ( + .A(\t$2182 ), + .B(a_registered[13]), + .Y(booth_b12_m3) + ); + AO22x1_ASAP7_75t_R \U$971 ( + .A1(b_registered[3]), + .A2(\sel_0$1550 ), + .B1(b_registered[4]), + .B2(\sel_1$1551 ), + .Y(\t$2183 ) + ); + XOR2x1_ASAP7_75t_R \U$972 ( + .A(\t$2183 ), + .B(a_registered[13]), + .Y(booth_b12_m4) + ); + AO22x1_ASAP7_75t_R \U$973 ( + .A1(b_registered[4]), + .A2(\sel_0$1550 ), + .B1(b_registered[5]), + .B2(\sel_1$1551 ), + .Y(\t$2184 ) + ); + XOR2x1_ASAP7_75t_R \U$974 ( + .A(\t$2184 ), + .B(a_registered[13]), + .Y(booth_b12_m5) + ); + AO22x1_ASAP7_75t_R \U$975 ( + .A1(b_registered[5]), + .A2(\sel_0$1550 ), + .B1(b_registered[6]), + .B2(\sel_1$1551 ), + .Y(\t$2185 ) + ); + XOR2x1_ASAP7_75t_R \U$976 ( + .A(\t$2185 ), + .B(a_registered[13]), + .Y(booth_b12_m6) + ); + AO22x1_ASAP7_75t_R \U$977 ( + .A1(b_registered[6]), + .A2(\sel_0$1550 ), + .B1(b_registered[7]), + .B2(\sel_1$1551 ), + .Y(\t$2186 ) + ); + XOR2x1_ASAP7_75t_R \U$978 ( + .A(\t$2186 ), + .B(a_registered[13]), + .Y(booth_b12_m7) + ); + AO22x1_ASAP7_75t_R \U$979 ( + .A1(b_registered[7]), + .A2(\sel_0$1550 ), + .B1(b_registered[8]), + .B2(\sel_1$1551 ), + .Y(\t$2187 ) + ); + XOR2x1_ASAP7_75t_R \U$980 ( + .A(\t$2187 ), + .B(a_registered[13]), + .Y(booth_b12_m8) + ); + AO22x1_ASAP7_75t_R \U$981 ( + .A1(b_registered[8]), + .A2(\sel_0$1550 ), + .B1(b_registered[9]), + .B2(\sel_1$1551 ), + .Y(\t$2188 ) + ); + XOR2x1_ASAP7_75t_R \U$982 ( + .A(\t$2188 ), + .B(a_registered[13]), + .Y(booth_b12_m9) + ); + AO22x1_ASAP7_75t_R \U$983 ( + .A1(b_registered[9]), + .A2(\sel_0$1550 ), + .B1(b_registered[10]), + .B2(\sel_1$1551 ), + .Y(\t$2189 ) + ); + XOR2x1_ASAP7_75t_R \U$984 ( + .A(\t$2189 ), + .B(a_registered[13]), + .Y(booth_b12_m10) + ); + AO22x1_ASAP7_75t_R \U$985 ( + .A1(b_registered[10]), + .A2(\sel_0$1550 ), + .B1(b_registered[11]), + .B2(\sel_1$1551 ), + .Y(\t$2190 ) + ); + XOR2x1_ASAP7_75t_R \U$986 ( + .A(\t$2190 ), + .B(a_registered[13]), + .Y(booth_b12_m11) + ); + AO22x1_ASAP7_75t_R \U$987 ( + .A1(b_registered[11]), + .A2(\sel_0$1550 ), + .B1(b_registered[12]), + .B2(\sel_1$1551 ), + .Y(\t$2191 ) + ); + XOR2x1_ASAP7_75t_R \U$988 ( + .A(\t$2191 ), + .B(a_registered[13]), + .Y(booth_b12_m12) + ); + AO22x1_ASAP7_75t_R \U$989 ( + .A1(b_registered[12]), + .A2(\sel_0$1550 ), + .B1(b_registered[13]), + .B2(\sel_1$1551 ), + .Y(\t$2192 ) + ); + XOR2x1_ASAP7_75t_R \U$990 ( + .A(\t$2192 ), + .B(a_registered[13]), + .Y(booth_b12_m13) + ); + AO22x1_ASAP7_75t_R \U$991 ( + .A1(b_registered[13]), + .A2(\sel_0$1550 ), + .B1(b_registered[14]), + .B2(\sel_1$1551 ), + .Y(\t$2193 ) + ); + XOR2x1_ASAP7_75t_R \U$992 ( + .A(\t$2193 ), + .B(a_registered[13]), + .Y(booth_b12_m14) + ); + AO22x1_ASAP7_75t_R \U$993 ( + .A1(b_registered[14]), + .A2(\sel_0$1550 ), + .B1(b_registered[15]), + .B2(\sel_1$1551 ), + .Y(\t$2194 ) + ); + XOR2x1_ASAP7_75t_R \U$994 ( + .A(\t$2194 ), + .B(a_registered[13]), + .Y(booth_b12_m15) + ); + AO22x1_ASAP7_75t_R \U$995 ( + .A1(b_registered[15]), + .A2(\sel_0$1550 ), + .B1(b_registered[16]), + .B2(\sel_1$1551 ), + .Y(\t$2195 ) + ); + XOR2x1_ASAP7_75t_R \U$996 ( + .A(\t$2195 ), + .B(a_registered[13]), + .Y(booth_b12_m16) + ); + AO22x1_ASAP7_75t_R \U$997 ( + .A1(b_registered[16]), + .A2(\sel_0$1550 ), + .B1(b_registered[17]), + .B2(\sel_1$1551 ), + .Y(\t$2196 ) + ); + XOR2x1_ASAP7_75t_R \U$998 ( + .A(\t$2196 ), + .B(a_registered[13]), + .Y(booth_b12_m17) + ); + AO22x1_ASAP7_75t_R \U$999 ( + .A1(b_registered[17]), + .A2(\sel_0$1550 ), + .B1(b_registered[18]), + .B2(\sel_1$1551 ), + .Y(\t$2197 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_26_0 ( + .A(pp_row26_0), + .B(pp_row26_1), + .CI(pp_row26_2), + .CON(\con$2560 ), + .SN(\sn$2562 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_27_0 ( + .A(pp_row27_0), + .B(pp_row27_1), + .CI(pp_row27_2), + .CON(\con$2568 ), + .SN(\sn$2570 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_28_0 ( + .A(pp_row28_0), + .B(pp_row28_1), + .CI(pp_row28_2), + .CON(\con$2576 ), + .SN(\sn$2578 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_28_1 ( + .A(pp_row28_3), + .B(pp_row28_4), + .CI(pp_row28_5), + .CON(\con$2580 ), + .SN(\sn$2582 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_29_0 ( + .A(pp_row29_0), + .B(pp_row29_1), + .CI(pp_row29_2), + .CON(\con$2588 ), + .SN(\sn$2590 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_29_1 ( + .A(pp_row29_3), + .B(pp_row29_4), + .CI(pp_row29_5), + .CON(\con$2592 ), + .SN(\sn$2594 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_0 ( + .A(pp_row30_0), + .B(pp_row30_1), + .CI(pp_row30_2), + .CON(\con$2600 ), + .SN(\sn$2602 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_1 ( + .A(pp_row30_3), + .B(pp_row30_4), + .CI(pp_row30_5), + .CON(\con$2604 ), + .SN(\sn$2606 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_2 ( + .A(pp_row30_6), + .B(pp_row30_7), + .CI(pp_row30_8), + .CON(\con$2608 ), + .SN(\sn$2610 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_0 ( + .A(pp_row31_0), + .B(pp_row31_1), + .CI(pp_row31_2), + .CON(\con$2616 ), + .SN(\sn$2618 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_1 ( + .A(pp_row31_3), + .B(pp_row31_4), + .CI(pp_row31_5), + .CON(\con$2620 ), + .SN(\sn$2622 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_2 ( + .A(pp_row31_6), + .B(pp_row31_7), + .CI(pp_row31_8), + .CON(\con$2624 ), + .SN(\sn$2626 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_0 ( + .A(pp_row32_0), + .B(pp_row32_1), + .CI(pp_row32_2), + .CON(\con$2632 ), + .SN(\sn$2634 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_1 ( + .A(pp_row32_3), + .B(pp_row32_4), + .CI(pp_row32_5), + .CON(\con$2636 ), + .SN(\sn$2638 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_2 ( + .A(pp_row32_6), + .B(pp_row32_7), + .CI(pp_row32_8), + .CON(\con$2640 ), + .SN(\sn$2642 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_3 ( + .A(pp_row32_9), + .B(pp_row32_10), + .CI(pp_row32_11), + .CON(\con$2644 ), + .SN(\sn$2646 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_0 ( + .A(pp_row33_0), + .B(pp_row33_1), + .CI(pp_row33_2), + .CON(\con$2648 ), + .SN(\sn$2650 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_1 ( + .A(pp_row33_3), + .B(pp_row33_4), + .CI(pp_row33_5), + .CON(\con$2652 ), + .SN(\sn$2654 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_2 ( + .A(pp_row33_6), + .B(pp_row33_7), + .CI(pp_row33_8), + .CON(\con$2656 ), + .SN(\sn$2658 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_3 ( + .A(pp_row33_9), + .B(pp_row33_10), + .CI(pp_row33_11), + .CON(\con$2660 ), + .SN(\sn$2662 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_0 ( + .A(pp_row34_0), + .B(pp_row34_1), + .CI(pp_row34_2), + .CON(\con$2664 ), + .SN(\sn$2666 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_1 ( + .A(pp_row34_3), + .B(pp_row34_4), + .CI(pp_row34_5), + .CON(\con$2668 ), + .SN(\sn$2670 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_2 ( + .A(pp_row34_6), + .B(pp_row34_7), + .CI(pp_row34_8), + .CON(\con$2672 ), + .SN(\sn$2674 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_3 ( + .A(pp_row34_9), + .B(pp_row34_10), + .CI(pp_row34_11), + .CON(\con$2676 ), + .SN(\sn$2678 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_0 ( + .A(pp_row35_0), + .B(pp_row35_1), + .CI(pp_row35_2), + .CON(\con$2680 ), + .SN(\sn$2682 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_1 ( + .A(pp_row35_3), + .B(pp_row35_4), + .CI(pp_row35_5), + .CON(\con$2684 ), + .SN(\sn$2686 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_2 ( + .A(pp_row35_6), + .B(pp_row35_7), + .CI(pp_row35_8), + .CON(\con$2688 ), + .SN(\sn$2690 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_3 ( + .A(pp_row35_9), + .B(pp_row35_10), + .CI(pp_row35_11), + .CON(\con$2692 ), + .SN(\sn$2694 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_0 ( + .A(1'h1), + .B(pp_row36_1), + .CI(pp_row36_2), + .CON(\con$2696 ), + .SN(\sn$2698 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_1 ( + .A(pp_row36_3), + .B(pp_row36_4), + .CI(pp_row36_5), + .CON(\con$2700 ), + .SN(\sn$2702 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_2 ( + .A(pp_row36_6), + .B(pp_row36_7), + .CI(pp_row36_8), + .CON(\con$2704 ), + .SN(\sn$2706 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_0 ( + .A(pp_row37_0), + .B(pp_row37_1), + .CI(pp_row37_2), + .CON(\con$2712 ), + .SN(\sn$2714 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_1 ( + .A(pp_row37_3), + .B(pp_row37_4), + .CI(pp_row37_5), + .CON(\con$2716 ), + .SN(\sn$2718 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_2 ( + .A(pp_row37_6), + .B(pp_row37_7), + .CI(pp_row37_8), + .CON(\con$2720 ), + .SN(\sn$2722 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_38_0 ( + .A(1'h1), + .B(pp_row38_1), + .CI(pp_row38_2), + .CON(\con$2724 ), + .SN(\sn$2726 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_38_1 ( + .A(pp_row38_3), + .B(pp_row38_4), + .CI(pp_row38_5), + .CON(\con$2728 ), + .SN(\sn$2730 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_39_0 ( + .A(pp_row39_0), + .B(pp_row39_1), + .CI(pp_row39_2), + .CON(\con$2736 ), + .SN(\sn$2738 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_39_1 ( + .A(pp_row39_3), + .B(pp_row39_4), + .CI(pp_row39_5), + .CON(\con$2740 ), + .SN(\sn$2742 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_40_0 ( + .A(1'h1), + .B(pp_row40_1), + .CI(pp_row40_2), + .CON(\con$2744 ), + .SN(\sn$2746 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_41_0 ( + .A(pp_row41_0), + .B(pp_row41_1), + .CI(pp_row41_2), + .CON(\con$2752 ), + .SN(\sn$2754 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_18_0 ( + .A(pp_row18_0), + .B(pp_row18_1), + .CI(pp_row18_2), + .CON(\con$2768 ), + .SN(\sn$2770 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_19_0 ( + .A(pp_row19_0), + .B(pp_row19_1), + .CI(pp_row19_2), + .CON(\con$2776 ), + .SN(\sn$2778 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_20_0 ( + .A(pp_row20_0), + .B(pp_row20_1), + .CI(pp_row20_2), + .CON(\con$2784 ), + .SN(\sn$2786 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_20_1 ( + .A(pp_row20_3), + .B(pp_row20_4), + .CI(pp_row20_5), + .CON(\con$2788 ), + .SN(\sn$2790 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_21_0 ( + .A(pp_row21_0), + .B(pp_row21_1), + .CI(pp_row21_2), + .CON(\con$2796 ), + .SN(\sn$2798 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_21_1 ( + .A(pp_row21_3), + .B(pp_row21_4), + .CI(pp_row21_5), + .CON(\con$2800 ), + .SN(\sn$2802 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_0 ( + .A(pp_row22_0), + .B(pp_row22_1), + .CI(pp_row22_2), + .CON(\con$2808 ), + .SN(\sn$2810 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_1 ( + .A(pp_row22_3), + .B(pp_row22_4), + .CI(pp_row22_5), + .CON(\con$2812 ), + .SN(\sn$2814 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_2 ( + .A(pp_row22_6), + .B(pp_row22_7), + .CI(pp_row22_8), + .CON(\con$2816 ), + .SN(\sn$2818 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_0 ( + .A(pp_row23_0), + .B(pp_row23_1), + .CI(pp_row23_2), + .CON(\con$2824 ), + .SN(\sn$2826 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_1 ( + .A(pp_row23_3), + .B(pp_row23_4), + .CI(pp_row23_5), + .CON(\con$2828 ), + .SN(\sn$2830 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_2 ( + .A(pp_row23_6), + .B(pp_row23_7), + .CI(pp_row23_8), + .CON(\con$2832 ), + .SN(\sn$2834 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_0 ( + .A(pp_row24_2), + .B(pp_row24_3), + .CI(pp_row24_4), + .CON(\con$2840 ), + .SN(\sn$2842 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_1 ( + .A(pp_row24_5), + .B(pp_row24_6), + .CI(pp_row24_7), + .CON(\con$2844 ), + .SN(\sn$2846 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_2 ( + .A(pp_row24_8), + .B(pp_row24_9), + .CI(pp_row24_10), + .CON(\con$2848 ), + .SN(\sn$2850 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_3 ( + .A(pp_row24_11), + .B(pp_row24_12), + .CI(pp_row24_13), + .CON(\con$2852 ), + .SN(\sn$2854 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_0 ( + .A(pp_row25_2), + .B(pp_row25_3), + .CI(pp_row25_4), + .CON(\con$2856 ), + .SN(\sn$2858 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_1 ( + .A(pp_row25_5), + .B(pp_row25_6), + .CI(pp_row25_7), + .CON(\con$2860 ), + .SN(\sn$2862 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_2 ( + .A(pp_row25_8), + .B(pp_row25_9), + .CI(pp_row25_10), + .CON(\con$2864 ), + .SN(\sn$2866 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_3 ( + .A(pp_row25_11), + .B(pp_row25_12), + .CI(\c$2553 ), + .CON(\con$2868 ), + .SN(\sn$2870 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_0 ( + .A(pp_row26_5), + .B(pp_row26_6), + .CI(pp_row26_7), + .CON(\con$2872 ), + .SN(\sn$2874 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_1 ( + .A(pp_row26_8), + .B(pp_row26_9), + .CI(pp_row26_10), + .CON(\con$2876 ), + .SN(\sn$2878 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_2 ( + .A(pp_row26_11), + .B(pp_row26_12), + .CI(pp_row26_13), + .CON(\con$2880 ), + .SN(\sn$2882 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_3 ( + .A(pp_row26_14), + .B(\c$2557 ), + .CI(\s$2563 ), + .CON(\con$2884 ), + .SN(\sn$2886 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_0 ( + .A(pp_row27_5), + .B(pp_row27_6), + .CI(pp_row27_7), + .CON(\con$2888 ), + .SN(\sn$2890 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_1 ( + .A(pp_row27_8), + .B(pp_row27_9), + .CI(pp_row27_10), + .CON(\con$2892 ), + .SN(\sn$2894 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_2 ( + .A(pp_row27_11), + .B(pp_row27_12), + .CI(pp_row27_13), + .CON(\con$2896 ), + .SN(\sn$2898 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_3 ( + .A(\c$2561 ), + .B(\c$2565 ), + .CI(\s$2571 ), + .CON(\con$2900 ), + .SN(\sn$2902 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_0 ( + .A(pp_row28_8), + .B(pp_row28_9), + .CI(pp_row28_10), + .CON(\con$2904 ), + .SN(\sn$2906 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_1 ( + .A(pp_row28_11), + .B(pp_row28_12), + .CI(pp_row28_13), + .CON(\con$2908 ), + .SN(\sn$2910 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_2 ( + .A(pp_row28_14), + .B(pp_row28_15), + .CI(\c$2569 ), + .CON(\con$2912 ), + .SN(\sn$2914 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_3 ( + .A(\c$2573 ), + .B(\s$2579 ), + .CI(\s$2583 ), + .CON(\con$2916 ), + .SN(\sn$2918 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_0 ( + .A(pp_row29_8), + .B(pp_row29_9), + .CI(pp_row29_10), + .CON(\con$2920 ), + .SN(\sn$2922 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_1 ( + .A(pp_row29_11), + .B(pp_row29_12), + .CI(pp_row29_13), + .CON(\con$2924 ), + .SN(\sn$2926 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_2 ( + .A(pp_row29_14), + .B(\c$2577 ), + .CI(\c$2581 ), + .CON(\con$2928 ), + .SN(\sn$2930 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_3 ( + .A(\c$2585 ), + .B(\s$2591 ), + .CI(\s$2595 ), + .CON(\con$2932 ), + .SN(\sn$2934 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_0 ( + .A(pp_row30_11), + .B(pp_row30_12), + .CI(pp_row30_13), + .CON(\con$2936 ), + .SN(\sn$2938 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_1 ( + .A(pp_row30_14), + .B(pp_row30_15), + .CI(pp_row30_16), + .CON(\con$2940 ), + .SN(\sn$2942 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_2 ( + .A(\c$2589 ), + .B(\c$2593 ), + .CI(\c$2597 ), + .CON(\con$2944 ), + .SN(\sn$2946 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_3 ( + .A(\s$2603 ), + .B(\s$2607 ), + .CI(\s$2611 ), + .CON(\con$2948 ), + .SN(\sn$2950 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_0 ( + .A(pp_row31_11), + .B(pp_row31_12), + .CI(pp_row31_13), + .CON(\con$2952 ), + .SN(\sn$2954 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_1 ( + .A(pp_row31_14), + .B(pp_row31_15), + .CI(\c$2601 ), + .CON(\con$2956 ), + .SN(\sn$2958 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_2 ( + .A(\c$2605 ), + .B(\c$2609 ), + .CI(\c$2613 ), + .CON(\con$2960 ), + .SN(\sn$2962 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_3 ( + .A(\s$2619 ), + .B(\s$2623 ), + .CI(\s$2627 ), + .CON(\con$2964 ), + .SN(\sn$2966 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_0 ( + .A(pp_row32_12), + .B(pp_row32_13), + .CI(pp_row32_14), + .CON(\con$2968 ), + .SN(\sn$2970 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_1 ( + .A(pp_row32_15), + .B(pp_row32_16), + .CI(\c$2617 ), + .CON(\con$2972 ), + .SN(\sn$2974 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_2 ( + .A(\c$2621 ), + .B(\c$2625 ), + .CI(\c$2629 ), + .CON(\con$2976 ), + .SN(\sn$2978 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_3 ( + .A(\s$2635 ), + .B(\s$2639 ), + .CI(\s$2643 ), + .CON(\con$2980 ), + .SN(\sn$2982 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_0 ( + .A(pp_row33_12), + .B(pp_row33_13), + .CI(pp_row33_14), + .CON(\con$2984 ), + .SN(\sn$2986 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_1 ( + .A(pp_row33_15), + .B(pp_row33_16), + .CI(\c$2633 ), + .CON(\con$2988 ), + .SN(\sn$2990 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_2 ( + .A(\c$2637 ), + .B(\c$2641 ), + .CI(\c$2645 ), + .CON(\con$2992 ), + .SN(\sn$2994 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_3 ( + .A(\s$2651 ), + .B(\s$2655 ), + .CI(\s$2659 ), + .CON(\con$2996 ), + .SN(\sn$2998 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_0 ( + .A(pp_row34_12), + .B(pp_row34_13), + .CI(pp_row34_14), + .CON(\con$3000 ), + .SN(\sn$3002 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_1 ( + .A(pp_row34_15), + .B(pp_row34_16), + .CI(\c$2649 ), + .CON(\con$3004 ), + .SN(\sn$3006 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_2 ( + .A(\c$2653 ), + .B(\c$2657 ), + .CI(\c$2661 ), + .CON(\con$3008 ), + .SN(\sn$3010 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_3 ( + .A(\s$2667 ), + .B(\s$2671 ), + .CI(\s$2675 ), + .CON(\con$3012 ), + .SN(\sn$3014 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_0 ( + .A(pp_row35_12), + .B(pp_row35_13), + .CI(pp_row35_14), + .CON(\con$3016 ), + .SN(\sn$3018 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_1 ( + .A(pp_row35_15), + .B(pp_row35_16), + .CI(\c$2665 ), + .CON(\con$3020 ), + .SN(\sn$3022 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_2 ( + .A(\c$2669 ), + .B(\c$2673 ), + .CI(\c$2677 ), + .CON(\con$3024 ), + .SN(\sn$3026 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_3 ( + .A(\s$2683 ), + .B(\s$2687 ), + .CI(\s$2691 ), + .CON(\con$3028 ), + .SN(\sn$3030 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_0 ( + .A(pp_row36_11), + .B(pp_row36_12), + .CI(pp_row36_13), + .CON(\con$3032 ), + .SN(\sn$3034 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_1 ( + .A(pp_row36_14), + .B(pp_row36_15), + .CI(\c$2681 ), + .CON(\con$3036 ), + .SN(\sn$3038 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_2 ( + .A(\c$2685 ), + .B(\c$2689 ), + .CI(\c$2693 ), + .CON(\con$3040 ), + .SN(\sn$3042 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_3 ( + .A(\s$2699 ), + .B(\s$2703 ), + .CI(\s$2707 ), + .CON(\con$3044 ), + .SN(\sn$3046 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_0 ( + .A(pp_row37_9), + .B(pp_row37_10), + .CI(pp_row37_11), + .CON(\con$3048 ), + .SN(\sn$3050 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_1 ( + .A(pp_row37_12), + .B(pp_row37_13), + .CI(pp_row37_14), + .CON(\con$3052 ), + .SN(\sn$3054 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_2 ( + .A(\c$2697 ), + .B(\c$2701 ), + .CI(\c$2705 ), + .CON(\con$3056 ), + .SN(\sn$3058 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_3 ( + .A(\c$2709 ), + .B(\s$2715 ), + .CI(\s$2719 ), + .CON(\con$3060 ), + .SN(\sn$3062 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_0 ( + .A(pp_row38_8), + .B(pp_row38_9), + .CI(pp_row38_10), + .CON(\con$3064 ), + .SN(\sn$3066 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_1 ( + .A(pp_row38_11), + .B(pp_row38_12), + .CI(pp_row38_13), + .CON(\con$3068 ), + .SN(\sn$3070 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_2 ( + .A(pp_row38_14), + .B(\c$2713 ), + .CI(\c$2717 ), + .CON(\con$3072 ), + .SN(\sn$3074 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_3 ( + .A(\c$2721 ), + .B(\s$2727 ), + .CI(\s$2731 ), + .CON(\con$3076 ), + .SN(\sn$3078 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_0 ( + .A(pp_row39_6), + .B(pp_row39_7), + .CI(pp_row39_8), + .CON(\con$3080 ), + .SN(\sn$3082 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_1 ( + .A(pp_row39_9), + .B(pp_row39_10), + .CI(pp_row39_11), + .CON(\con$3084 ), + .SN(\sn$3086 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_2 ( + .A(pp_row39_12), + .B(pp_row39_13), + .CI(\c$2725 ), + .CON(\con$3088 ), + .SN(\sn$3090 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_3 ( + .A(\c$2729 ), + .B(\c$2733 ), + .CI(\s$2739 ), + .CON(\con$3092 ), + .SN(\sn$3094 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_0 ( + .A(pp_row40_5), + .B(pp_row40_6), + .CI(pp_row40_7), + .CON(\con$3096 ), + .SN(\sn$3098 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_1 ( + .A(pp_row40_8), + .B(pp_row40_9), + .CI(pp_row40_10), + .CON(\con$3100 ), + .SN(\sn$3102 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_2 ( + .A(pp_row40_11), + .B(pp_row40_12), + .CI(pp_row40_13), + .CON(\con$3104 ), + .SN(\sn$3106 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_3 ( + .A(\c$2737 ), + .B(\c$2741 ), + .CI(\s$2747 ), + .CON(\con$3108 ), + .SN(\sn$3110 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_0 ( + .A(pp_row41_3), + .B(pp_row41_4), + .CI(pp_row41_5), + .CON(\con$3112 ), + .SN(\sn$3114 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_1 ( + .A(pp_row41_6), + .B(pp_row41_7), + .CI(pp_row41_8), + .CON(\con$3116 ), + .SN(\sn$3118 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_2 ( + .A(pp_row41_9), + .B(pp_row41_10), + .CI(pp_row41_11), + .CON(\con$3120 ), + .SN(\sn$3122 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_3 ( + .A(pp_row41_12), + .B(\c$2745 ), + .CI(\c$2749 ), + .CON(\con$3124 ), + .SN(\sn$3126 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_0 ( + .A(pp_row42_2), + .B(pp_row42_3), + .CI(pp_row42_4), + .CON(\con$3128 ), + .SN(\sn$3130 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_1 ( + .A(pp_row42_5), + .B(pp_row42_6), + .CI(pp_row42_7), + .CON(\con$3132 ), + .SN(\sn$3134 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_2 ( + .A(pp_row42_8), + .B(pp_row42_9), + .CI(pp_row42_10), + .CON(\con$3136 ), + .SN(\sn$3138 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_3 ( + .A(pp_row42_11), + .B(pp_row42_12), + .CI(\c$2753 ), + .CON(\con$3140 ), + .SN(\sn$3142 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_0 ( + .A(pp_row43_0), + .B(pp_row43_1), + .CI(pp_row43_2), + .CON(\con$3144 ), + .SN(\sn$3146 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_1 ( + .A(pp_row43_3), + .B(pp_row43_4), + .CI(pp_row43_5), + .CON(\con$3148 ), + .SN(\sn$3150 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_2 ( + .A(pp_row43_6), + .B(pp_row43_7), + .CI(pp_row43_8), + .CON(\con$3152 ), + .SN(\sn$3154 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_3 ( + .A(pp_row43_9), + .B(pp_row43_10), + .CI(pp_row43_11), + .CON(\con$3156 ), + .SN(\sn$3158 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_0 ( + .A(1'h1), + .B(pp_row44_1), + .CI(pp_row44_2), + .CON(\con$3160 ), + .SN(\sn$3162 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_1 ( + .A(pp_row44_3), + .B(pp_row44_4), + .CI(pp_row44_5), + .CON(\con$3164 ), + .SN(\sn$3166 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_2 ( + .A(pp_row44_6), + .B(pp_row44_7), + .CI(pp_row44_8), + .CON(\con$3168 ), + .SN(\sn$3170 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_0 ( + .A(pp_row45_0), + .B(pp_row45_1), + .CI(pp_row45_2), + .CON(\con$3176 ), + .SN(\sn$3178 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_1 ( + .A(pp_row45_3), + .B(pp_row45_4), + .CI(pp_row45_5), + .CON(\con$3180 ), + .SN(\sn$3182 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_2 ( + .A(pp_row45_6), + .B(pp_row45_7), + .CI(pp_row45_8), + .CON(\con$3184 ), + .SN(\sn$3186 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_46_0 ( + .A(1'h1), + .B(pp_row46_1), + .CI(pp_row46_2), + .CON(\con$3188 ), + .SN(\sn$3190 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_46_1 ( + .A(pp_row46_3), + .B(pp_row46_4), + .CI(pp_row46_5), + .CON(\con$3192 ), + .SN(\sn$3194 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_47_0 ( + .A(pp_row47_0), + .B(pp_row47_1), + .CI(pp_row47_2), + .CON(\con$3200 ), + .SN(\sn$3202 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_47_1 ( + .A(pp_row47_3), + .B(pp_row47_4), + .CI(pp_row47_5), + .CON(\con$3204 ), + .SN(\sn$3206 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_48_0 ( + .A(1'h1), + .B(pp_row48_1), + .CI(pp_row48_2), + .CON(\con$3208 ), + .SN(\sn$3210 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_49_0 ( + .A(pp_row49_0), + .B(pp_row49_1), + .CI(pp_row49_2), + .CON(\con$3216 ), + .SN(\sn$3218 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_12_0 ( + .A(pp_row12_0), + .B(pp_row12_1), + .CI(pp_row12_2), + .CON(\con$3232 ), + .SN(\sn$3234 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_13_0 ( + .A(pp_row13_0), + .B(pp_row13_1), + .CI(pp_row13_2), + .CON(\con$3240 ), + .SN(\sn$3242 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_14_0 ( + .A(pp_row14_0), + .B(pp_row14_1), + .CI(pp_row14_2), + .CON(\con$3248 ), + .SN(\sn$3250 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_14_1 ( + .A(pp_row14_3), + .B(pp_row14_4), + .CI(pp_row14_5), + .CON(\con$3252 ), + .SN(\sn$3254 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_15_0 ( + .A(pp_row15_0), + .B(pp_row15_1), + .CI(pp_row15_2), + .CON(\con$3260 ), + .SN(\sn$3262 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_15_1 ( + .A(pp_row15_3), + .B(pp_row15_4), + .CI(pp_row15_5), + .CON(\con$3264 ), + .SN(\sn$3266 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_0 ( + .A(pp_row16_2), + .B(pp_row16_3), + .CI(pp_row16_4), + .CON(\con$3272 ), + .SN(\sn$3274 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_1 ( + .A(pp_row16_5), + .B(pp_row16_6), + .CI(pp_row16_7), + .CON(\con$3276 ), + .SN(\sn$3278 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_2 ( + .A(pp_row16_8), + .B(pp_row16_9), + .CI(\s$2763 ), + .CON(\con$3280 ), + .SN(\sn$3282 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_0 ( + .A(pp_row17_2), + .B(pp_row17_3), + .CI(pp_row17_4), + .CON(\con$3284 ), + .SN(\sn$3286 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_1 ( + .A(pp_row17_5), + .B(pp_row17_6), + .CI(pp_row17_7), + .CON(\con$3288 ), + .SN(\sn$3290 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_2 ( + .A(pp_row17_8), + .B(\c$2761 ), + .CI(\s$2767 ), + .CON(\con$3292 ), + .SN(\sn$3294 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_0 ( + .A(pp_row18_5), + .B(pp_row18_6), + .CI(pp_row18_7), + .CON(\con$3296 ), + .SN(\sn$3298 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_1 ( + .A(pp_row18_8), + .B(pp_row18_9), + .CI(pp_row18_10), + .CON(\con$3300 ), + .SN(\sn$3302 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_2 ( + .A(\c$2765 ), + .B(\s$2771 ), + .CI(\s$2775 ), + .CON(\con$3304 ), + .SN(\sn$3306 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_0 ( + .A(pp_row19_5), + .B(pp_row19_6), + .CI(pp_row19_7), + .CON(\con$3308 ), + .SN(\sn$3310 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_1 ( + .A(pp_row19_8), + .B(pp_row19_9), + .CI(\c$2769 ), + .CON(\con$3312 ), + .SN(\sn$3314 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_2 ( + .A(\c$2773 ), + .B(\s$2779 ), + .CI(\s$2783 ), + .CON(\con$3316 ), + .SN(\sn$3318 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_0 ( + .A(pp_row20_8), + .B(pp_row20_9), + .CI(pp_row20_10), + .CON(\con$3320 ), + .SN(\sn$3322 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_1 ( + .A(pp_row20_11), + .B(\c$2777 ), + .CI(\c$2781 ), + .CON(\con$3324 ), + .SN(\sn$3326 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_2 ( + .A(\s$2787 ), + .B(\s$2791 ), + .CI(\s$2795 ), + .CON(\con$3328 ), + .SN(\sn$3330 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_0 ( + .A(pp_row21_8), + .B(pp_row21_9), + .CI(pp_row21_10), + .CON(\con$3332 ), + .SN(\sn$3334 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_1 ( + .A(\c$2785 ), + .B(\c$2789 ), + .CI(\c$2793 ), + .CON(\con$3336 ), + .SN(\sn$3338 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_2 ( + .A(\s$2799 ), + .B(\s$2803 ), + .CI(\s$2807 ), + .CON(\con$3340 ), + .SN(\sn$3342 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_0 ( + .A(pp_row22_11), + .B(pp_row22_12), + .CI(\c$2797 ), + .CON(\con$3344 ), + .SN(\sn$3346 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_1 ( + .A(\c$2801 ), + .B(\c$2805 ), + .CI(\s$2811 ), + .CON(\con$3348 ), + .SN(\sn$3350 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_2 ( + .A(\s$2815 ), + .B(\s$2819 ), + .CI(\s$2823 ), + .CON(\con$3352 ), + .SN(\sn$3354 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_0 ( + .A(pp_row23_11), + .B(\c$2809 ), + .CI(\c$2813 ), + .CON(\con$3356 ), + .SN(\sn$3358 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_1 ( + .A(\c$2817 ), + .B(\c$2821 ), + .CI(\s$2827 ), + .CON(\con$3360 ), + .SN(\sn$3362 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_2 ( + .A(\s$2831 ), + .B(\s$2835 ), + .CI(\s$2839 ), + .CON(\con$3364 ), + .SN(\sn$3366 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_0 ( + .A(\s$2555 ), + .B(\c$2825 ), + .CI(\c$2829 ), + .CON(\con$3368 ), + .SN(\sn$3370 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_1 ( + .A(\c$2833 ), + .B(\c$2837 ), + .CI(\s$2843 ), + .CON(\con$3372 ), + .SN(\sn$3374 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_2 ( + .A(\s$2847 ), + .B(\s$2851 ), + .CI(\s$2855 ), + .CON(\con$3376 ), + .SN(\sn$3378 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_0 ( + .A(\s$2559 ), + .B(\c$2841 ), + .CI(\c$2845 ), + .CON(\con$3380 ), + .SN(\sn$3382 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_1 ( + .A(\c$2849 ), + .B(\c$2853 ), + .CI(\s$2859 ), + .CON(\con$3384 ), + .SN(\sn$3386 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_2 ( + .A(\s$2863 ), + .B(\s$2867 ), + .CI(\s$2871 ), + .CON(\con$3388 ), + .SN(\sn$3390 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_0 ( + .A(\s$2567 ), + .B(\c$2857 ), + .CI(\c$2861 ), + .CON(\con$3392 ), + .SN(\sn$3394 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_1 ( + .A(\c$2865 ), + .B(\c$2869 ), + .CI(\s$2875 ), + .CON(\con$3396 ), + .SN(\sn$3398 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_2 ( + .A(\s$2879 ), + .B(\s$2883 ), + .CI(\s$2887 ), + .CON(\con$3400 ), + .SN(\sn$3402 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_0 ( + .A(\s$2575 ), + .B(\c$2873 ), + .CI(\c$2877 ), + .CON(\con$3404 ), + .SN(\sn$3406 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_1 ( + .A(\c$2881 ), + .B(\c$2885 ), + .CI(\s$2891 ), + .CON(\con$3408 ), + .SN(\sn$3410 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_2 ( + .A(\s$2895 ), + .B(\s$2899 ), + .CI(\s$2903 ), + .CON(\con$3412 ), + .SN(\sn$3414 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_0 ( + .A(\s$2587 ), + .B(\c$2889 ), + .CI(\c$2893 ), + .CON(\con$3416 ), + .SN(\sn$3418 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_1 ( + .A(\c$2897 ), + .B(\c$2901 ), + .CI(\s$2907 ), + .CON(\con$3420 ), + .SN(\sn$3422 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_2 ( + .A(\s$2911 ), + .B(\s$2915 ), + .CI(\s$2919 ), + .CON(\con$3424 ), + .SN(\sn$3426 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_0 ( + .A(\s$2599 ), + .B(\c$2905 ), + .CI(\c$2909 ), + .CON(\con$3428 ), + .SN(\sn$3430 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_1 ( + .A(\c$2913 ), + .B(\c$2917 ), + .CI(\s$2923 ), + .CON(\con$3432 ), + .SN(\sn$3434 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_2 ( + .A(\s$2927 ), + .B(\s$2931 ), + .CI(\s$2935 ), + .CON(\con$3436 ), + .SN(\sn$3438 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_0 ( + .A(\s$2615 ), + .B(\c$2921 ), + .CI(\c$2925 ), + .CON(\con$3440 ), + .SN(\sn$3442 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_1 ( + .A(\c$2929 ), + .B(\c$2933 ), + .CI(\s$2939 ), + .CON(\con$3444 ), + .SN(\sn$3446 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_2 ( + .A(\s$2943 ), + .B(\s$2947 ), + .CI(\s$2951 ), + .CON(\con$3448 ), + .SN(\sn$3450 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_0 ( + .A(\s$2631 ), + .B(\c$2937 ), + .CI(\c$2941 ), + .CON(\con$3452 ), + .SN(\sn$3454 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_1 ( + .A(\c$2945 ), + .B(\c$2949 ), + .CI(\s$2955 ), + .CON(\con$3456 ), + .SN(\sn$3458 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_2 ( + .A(\s$2959 ), + .B(\s$2963 ), + .CI(\s$2967 ), + .CON(\con$3460 ), + .SN(\sn$3462 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_0 ( + .A(\s$2647 ), + .B(\c$2953 ), + .CI(\c$2957 ), + .CON(\con$3464 ), + .SN(\sn$3466 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_1 ( + .A(\c$2961 ), + .B(\c$2965 ), + .CI(\s$2971 ), + .CON(\con$3468 ), + .SN(\sn$3470 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_2 ( + .A(\s$2975 ), + .B(\s$2979 ), + .CI(\s$2983 ), + .CON(\con$3472 ), + .SN(\sn$3474 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_0 ( + .A(\s$2663 ), + .B(\c$2969 ), + .CI(\c$2973 ), + .CON(\con$3476 ), + .SN(\sn$3478 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_1 ( + .A(\c$2977 ), + .B(\c$2981 ), + .CI(\s$2987 ), + .CON(\con$3480 ), + .SN(\sn$3482 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_2 ( + .A(\s$2991 ), + .B(\s$2995 ), + .CI(\s$2999 ), + .CON(\con$3484 ), + .SN(\sn$3486 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_0 ( + .A(\s$2679 ), + .B(\c$2985 ), + .CI(\c$2989 ), + .CON(\con$3488 ), + .SN(\sn$3490 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_1 ( + .A(\c$2993 ), + .B(\c$2997 ), + .CI(\s$3003 ), + .CON(\con$3492 ), + .SN(\sn$3494 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_2 ( + .A(\s$3007 ), + .B(\s$3011 ), + .CI(\s$3015 ), + .CON(\con$3496 ), + .SN(\sn$3498 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_0 ( + .A(\s$2695 ), + .B(\c$3001 ), + .CI(\c$3005 ), + .CON(\con$3500 ), + .SN(\sn$3502 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_1 ( + .A(\c$3009 ), + .B(\c$3013 ), + .CI(\s$3019 ), + .CON(\con$3504 ), + .SN(\sn$3506 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_2 ( + .A(\s$3023 ), + .B(\s$3027 ), + .CI(\s$3031 ), + .CON(\con$3508 ), + .SN(\sn$3510 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_0 ( + .A(\s$2711 ), + .B(\c$3017 ), + .CI(\c$3021 ), + .CON(\con$3512 ), + .SN(\sn$3514 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_1 ( + .A(\c$3025 ), + .B(\c$3029 ), + .CI(\s$3035 ), + .CON(\con$3516 ), + .SN(\sn$3518 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_2 ( + .A(\s$3039 ), + .B(\s$3043 ), + .CI(\s$3047 ), + .CON(\con$3520 ), + .SN(\sn$3522 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_0 ( + .A(\s$2723 ), + .B(\c$3033 ), + .CI(\c$3037 ), + .CON(\con$3524 ), + .SN(\sn$3526 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_1 ( + .A(\c$3041 ), + .B(\c$3045 ), + .CI(\s$3051 ), + .CON(\con$3528 ), + .SN(\sn$3530 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_2 ( + .A(\s$3055 ), + .B(\s$3059 ), + .CI(\s$3063 ), + .CON(\con$3532 ), + .SN(\sn$3534 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_0 ( + .A(\s$2735 ), + .B(\c$3049 ), + .CI(\c$3053 ), + .CON(\con$3536 ), + .SN(\sn$3538 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_1 ( + .A(\c$3057 ), + .B(\c$3061 ), + .CI(\s$3067 ), + .CON(\con$3540 ), + .SN(\sn$3542 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_2 ( + .A(\s$3071 ), + .B(\s$3075 ), + .CI(\s$3079 ), + .CON(\con$3544 ), + .SN(\sn$3546 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_0 ( + .A(\s$2743 ), + .B(\c$3065 ), + .CI(\c$3069 ), + .CON(\con$3548 ), + .SN(\sn$3550 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_1 ( + .A(\c$3073 ), + .B(\c$3077 ), + .CI(\s$3083 ), + .CON(\con$3552 ), + .SN(\sn$3554 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_2 ( + .A(\s$3087 ), + .B(\s$3091 ), + .CI(\s$3095 ), + .CON(\con$3556 ), + .SN(\sn$3558 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_0 ( + .A(\s$2751 ), + .B(\c$3081 ), + .CI(\c$3085 ), + .CON(\con$3560 ), + .SN(\sn$3562 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_1 ( + .A(\c$3089 ), + .B(\c$3093 ), + .CI(\s$3099 ), + .CON(\con$3564 ), + .SN(\sn$3566 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_2 ( + .A(\s$3103 ), + .B(\s$3107 ), + .CI(\s$3111 ), + .CON(\con$3568 ), + .SN(\sn$3570 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_0 ( + .A(\s$2755 ), + .B(\c$3097 ), + .CI(\c$3101 ), + .CON(\con$3572 ), + .SN(\sn$3574 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_1 ( + .A(\c$3105 ), + .B(\c$3109 ), + .CI(\s$3115 ), + .CON(\con$3576 ), + .SN(\sn$3578 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_2 ( + .A(\s$3119 ), + .B(\s$3123 ), + .CI(\s$3127 ), + .CON(\con$3580 ), + .SN(\sn$3582 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_0 ( + .A(\s$2759 ), + .B(\c$3113 ), + .CI(\c$3117 ), + .CON(\con$3584 ), + .SN(\sn$3586 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_1 ( + .A(\c$3121 ), + .B(\c$3125 ), + .CI(\s$3131 ), + .CON(\con$3588 ), + .SN(\sn$3590 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_2 ( + .A(\s$3135 ), + .B(\s$3139 ), + .CI(\s$3143 ), + .CON(\con$3592 ), + .SN(\sn$3594 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_0 ( + .A(\c$2757 ), + .B(\c$3129 ), + .CI(\c$3133 ), + .CON(\con$3596 ), + .SN(\sn$3598 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_1 ( + .A(\c$3137 ), + .B(\c$3141 ), + .CI(\s$3147 ), + .CON(\con$3600 ), + .SN(\sn$3602 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_2 ( + .A(\s$3151 ), + .B(\s$3155 ), + .CI(\s$3159 ), + .CON(\con$3604 ), + .SN(\sn$3606 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_0 ( + .A(pp_row44_11), + .B(\c$3145 ), + .CI(\c$3149 ), + .CON(\con$3608 ), + .SN(\sn$3610 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_1 ( + .A(\c$3153 ), + .B(\c$3157 ), + .CI(\s$3163 ), + .CON(\con$3612 ), + .SN(\sn$3614 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_2 ( + .A(\s$3167 ), + .B(\s$3171 ), + .CI(\s$3175 ), + .CON(\con$3616 ), + .SN(\sn$3618 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_0 ( + .A(pp_row45_9), + .B(pp_row45_10), + .CI(\c$3161 ), + .CON(\con$3620 ), + .SN(\sn$3622 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_1 ( + .A(\c$3165 ), + .B(\c$3169 ), + .CI(\c$3173 ), + .CON(\con$3624 ), + .SN(\sn$3626 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_2 ( + .A(\s$3179 ), + .B(\s$3183 ), + .CI(\s$3187 ), + .CON(\con$3628 ), + .SN(\sn$3630 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_0 ( + .A(pp_row46_8), + .B(pp_row46_9), + .CI(pp_row46_10), + .CON(\con$3632 ), + .SN(\sn$3634 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_1 ( + .A(\c$3177 ), + .B(\c$3181 ), + .CI(\c$3185 ), + .CON(\con$3636 ), + .SN(\sn$3638 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_2 ( + .A(\s$3191 ), + .B(\s$3195 ), + .CI(\s$3199 ), + .CON(\con$3640 ), + .SN(\sn$3642 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_0 ( + .A(pp_row47_6), + .B(pp_row47_7), + .CI(pp_row47_8), + .CON(\con$3644 ), + .SN(\sn$3646 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_1 ( + .A(pp_row47_9), + .B(\c$3189 ), + .CI(\c$3193 ), + .CON(\con$3648 ), + .SN(\sn$3650 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_2 ( + .A(\c$3197 ), + .B(\s$3203 ), + .CI(\s$3207 ), + .CON(\con$3652 ), + .SN(\sn$3654 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_0 ( + .A(pp_row48_5), + .B(pp_row48_6), + .CI(pp_row48_7), + .CON(\con$3656 ), + .SN(\sn$3658 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_1 ( + .A(pp_row48_8), + .B(pp_row48_9), + .CI(\c$3201 ), + .CON(\con$3660 ), + .SN(\sn$3662 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_2 ( + .A(\c$3205 ), + .B(\s$3211 ), + .CI(\s$3215 ), + .CON(\con$3664 ), + .SN(\sn$3666 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_0 ( + .A(pp_row49_3), + .B(pp_row49_4), + .CI(pp_row49_5), + .CON(\con$3668 ), + .SN(\sn$3670 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_1 ( + .A(pp_row49_6), + .B(pp_row49_7), + .CI(pp_row49_8), + .CON(\con$3672 ), + .SN(\sn$3674 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_2 ( + .A(\c$3209 ), + .B(\c$3213 ), + .CI(\s$3219 ), + .CON(\con$3676 ), + .SN(\sn$3678 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_0 ( + .A(pp_row50_2), + .B(pp_row50_3), + .CI(pp_row50_4), + .CON(\con$3680 ), + .SN(\sn$3682 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_1 ( + .A(pp_row50_5), + .B(pp_row50_6), + .CI(pp_row50_7), + .CON(\con$3684 ), + .SN(\sn$3686 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_2 ( + .A(pp_row50_8), + .B(\c$3217 ), + .CI(\s$3223 ), + .CON(\con$3688 ), + .SN(\sn$3690 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_0 ( + .A(pp_row51_0), + .B(pp_row51_1), + .CI(pp_row51_2), + .CON(\con$3692 ), + .SN(\sn$3694 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_1 ( + .A(pp_row51_3), + .B(pp_row51_4), + .CI(pp_row51_5), + .CON(\con$3696 ), + .SN(\sn$3698 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_2 ( + .A(pp_row51_6), + .B(pp_row51_7), + .CI(\c$3221 ), + .CON(\con$3700 ), + .SN(\sn$3702 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_52_0 ( + .A(1'h1), + .B(pp_row52_1), + .CI(pp_row52_2), + .CON(\con$3704 ), + .SN(\sn$3706 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_52_1 ( + .A(pp_row52_3), + .B(pp_row52_4), + .CI(pp_row52_5), + .CON(\con$3708 ), + .SN(\sn$3710 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_53_0 ( + .A(pp_row53_0), + .B(pp_row53_1), + .CI(pp_row53_2), + .CON(\con$3716 ), + .SN(\sn$3718 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_53_1 ( + .A(pp_row53_3), + .B(pp_row53_4), + .CI(pp_row53_5), + .CON(\con$3720 ), + .SN(\sn$3722 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_54_0 ( + .A(1'h1), + .B(pp_row54_1), + .CI(pp_row54_2), + .CON(\con$3724 ), + .SN(\sn$3726 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_55_0 ( + .A(pp_row55_0), + .B(pp_row55_1), + .CI(pp_row55_2), + .CON(\con$3732 ), + .SN(\sn$3734 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_10_0 ( + .A(pp_row10_2), + .B(pp_row10_3), + .CI(pp_row10_4), + .CON(\con$3764 ), + .SN(\sn$3766 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_10_1 ( + .A(pp_row10_5), + .B(pp_row10_6), + .CI(\s$3227 ), + .CON(\con$3768 ), + .SN(\sn$3770 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_11_0 ( + .A(pp_row11_2), + .B(pp_row11_3), + .CI(pp_row11_4), + .CON(\con$3772 ), + .SN(\sn$3774 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_11_1 ( + .A(pp_row11_5), + .B(\c$3225 ), + .CI(\s$3231 ), + .CON(\con$3776 ), + .SN(\sn$3778 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_12_0 ( + .A(pp_row12_5), + .B(pp_row12_6), + .CI(pp_row12_7), + .CON(\con$3780 ), + .SN(\sn$3782 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_12_1 ( + .A(\c$3229 ), + .B(\s$3235 ), + .CI(\s$3239 ), + .CON(\con$3784 ), + .SN(\sn$3786 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_13_0 ( + .A(pp_row13_5), + .B(pp_row13_6), + .CI(\c$3233 ), + .CON(\con$3788 ), + .SN(\sn$3790 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_13_1 ( + .A(\c$3237 ), + .B(\s$3243 ), + .CI(\s$3247 ), + .CON(\con$3792 ), + .SN(\sn$3794 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_14_0 ( + .A(pp_row14_8), + .B(\c$3241 ), + .CI(\c$3245 ), + .CON(\con$3796 ), + .SN(\sn$3798 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_14_1 ( + .A(\s$3251 ), + .B(\s$3255 ), + .CI(\s$3259 ), + .CON(\con$3800 ), + .SN(\sn$3802 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_15_0 ( + .A(\c$3249 ), + .B(\c$3253 ), + .CI(\c$3257 ), + .CON(\con$3804 ), + .SN(\sn$3806 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_15_1 ( + .A(\s$3263 ), + .B(\s$3267 ), + .CI(\s$3271 ), + .CON(\con$3808 ), + .SN(\sn$3810 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_16_0 ( + .A(\c$3261 ), + .B(\c$3265 ), + .CI(\c$3269 ), + .CON(\con$3812 ), + .SN(\sn$3814 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_16_1 ( + .A(\s$3275 ), + .B(\s$3279 ), + .CI(\s$3283 ), + .CON(\con$3816 ), + .SN(\sn$3818 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_17_0 ( + .A(\c$3273 ), + .B(\c$3277 ), + .CI(\c$3281 ), + .CON(\con$3820 ), + .SN(\sn$3822 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_17_1 ( + .A(\s$3287 ), + .B(\s$3291 ), + .CI(\s$3295 ), + .CON(\con$3824 ), + .SN(\sn$3826 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_18_0 ( + .A(\c$3285 ), + .B(\c$3289 ), + .CI(\c$3293 ), + .CON(\con$3828 ), + .SN(\sn$3830 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_18_1 ( + .A(\s$3299 ), + .B(\s$3303 ), + .CI(\s$3307 ), + .CON(\con$3832 ), + .SN(\sn$3834 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_19_0 ( + .A(\c$3297 ), + .B(\c$3301 ), + .CI(\c$3305 ), + .CON(\con$3836 ), + .SN(\sn$3838 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_19_1 ( + .A(\s$3311 ), + .B(\s$3315 ), + .CI(\s$3319 ), + .CON(\con$3840 ), + .SN(\sn$3842 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_20_0 ( + .A(\c$3309 ), + .B(\c$3313 ), + .CI(\c$3317 ), + .CON(\con$3844 ), + .SN(\sn$3846 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_20_1 ( + .A(\s$3323 ), + .B(\s$3327 ), + .CI(\s$3331 ), + .CON(\con$3848 ), + .SN(\sn$3850 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_21_0 ( + .A(\c$3321 ), + .B(\c$3325 ), + .CI(\c$3329 ), + .CON(\con$3852 ), + .SN(\sn$3854 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_21_1 ( + .A(\s$3335 ), + .B(\s$3339 ), + .CI(\s$3343 ), + .CON(\con$3856 ), + .SN(\sn$3858 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_22_0 ( + .A(\c$3333 ), + .B(\c$3337 ), + .CI(\c$3341 ), + .CON(\con$3860 ), + .SN(\sn$3862 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_22_1 ( + .A(\s$3347 ), + .B(\s$3351 ), + .CI(\s$3355 ), + .CON(\con$3864 ), + .SN(\sn$3866 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_23_0 ( + .A(\c$3345 ), + .B(\c$3349 ), + .CI(\c$3353 ), + .CON(\con$3868 ), + .SN(\sn$3870 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_23_1 ( + .A(\s$3359 ), + .B(\s$3363 ), + .CI(\s$3367 ), + .CON(\con$3872 ), + .SN(\sn$3874 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_24_0 ( + .A(\c$3357 ), + .B(\c$3361 ), + .CI(\c$3365 ), + .CON(\con$3876 ), + .SN(\sn$3878 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_24_1 ( + .A(\s$3371 ), + .B(\s$3375 ), + .CI(\s$3379 ), + .CON(\con$3880 ), + .SN(\sn$3882 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_25_0 ( + .A(\c$3369 ), + .B(\c$3373 ), + .CI(\c$3377 ), + .CON(\con$3884 ), + .SN(\sn$3886 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_25_1 ( + .A(\s$3383 ), + .B(\s$3387 ), + .CI(\s$3391 ), + .CON(\con$3888 ), + .SN(\sn$3890 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_26_0 ( + .A(\c$3381 ), + .B(\c$3385 ), + .CI(\c$3389 ), + .CON(\con$3892 ), + .SN(\sn$3894 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_26_1 ( + .A(\s$3395 ), + .B(\s$3399 ), + .CI(\s$3403 ), + .CON(\con$3896 ), + .SN(\sn$3898 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_27_0 ( + .A(\c$3393 ), + .B(\c$3397 ), + .CI(\c$3401 ), + .CON(\con$3900 ), + .SN(\sn$3902 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_27_1 ( + .A(\s$3407 ), + .B(\s$3411 ), + .CI(\s$3415 ), + .CON(\con$3904 ), + .SN(\sn$3906 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_28_0 ( + .A(\c$3405 ), + .B(\c$3409 ), + .CI(\c$3413 ), + .CON(\con$3908 ), + .SN(\sn$3910 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_28_1 ( + .A(\s$3419 ), + .B(\s$3423 ), + .CI(\s$3427 ), + .CON(\con$3912 ), + .SN(\sn$3914 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_29_0 ( + .A(\c$3417 ), + .B(\c$3421 ), + .CI(\c$3425 ), + .CON(\con$3916 ), + .SN(\sn$3918 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_29_1 ( + .A(\s$3431 ), + .B(\s$3435 ), + .CI(\s$3439 ), + .CON(\con$3920 ), + .SN(\sn$3922 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_30_0 ( + .A(\c$3429 ), + .B(\c$3433 ), + .CI(\c$3437 ), + .CON(\con$3924 ), + .SN(\sn$3926 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_30_1 ( + .A(\s$3443 ), + .B(\s$3447 ), + .CI(\s$3451 ), + .CON(\con$3928 ), + .SN(\sn$3930 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_31_0 ( + .A(\c$3441 ), + .B(\c$3445 ), + .CI(\c$3449 ), + .CON(\con$3932 ), + .SN(\sn$3934 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_31_1 ( + .A(\s$3455 ), + .B(\s$3459 ), + .CI(\s$3463 ), + .CON(\con$3936 ), + .SN(\sn$3938 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_32_0 ( + .A(\c$3453 ), + .B(\c$3457 ), + .CI(\c$3461 ), + .CON(\con$3940 ), + .SN(\sn$3942 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_32_1 ( + .A(\s$3467 ), + .B(\s$3471 ), + .CI(\s$3475 ), + .CON(\con$3944 ), + .SN(\sn$3946 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_33_0 ( + .A(\c$3465 ), + .B(\c$3469 ), + .CI(\c$3473 ), + .CON(\con$3948 ), + .SN(\sn$3950 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_33_1 ( + .A(\s$3479 ), + .B(\s$3483 ), + .CI(\s$3487 ), + .CON(\con$3952 ), + .SN(\sn$3954 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_34_0 ( + .A(\c$3477 ), + .B(\c$3481 ), + .CI(\c$3485 ), + .CON(\con$3956 ), + .SN(\sn$3958 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_34_1 ( + .A(\s$3491 ), + .B(\s$3495 ), + .CI(\s$3499 ), + .CON(\con$3960 ), + .SN(\sn$3962 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_35_0 ( + .A(\c$3489 ), + .B(\c$3493 ), + .CI(\c$3497 ), + .CON(\con$3964 ), + .SN(\sn$3966 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_35_1 ( + .A(\s$3503 ), + .B(\s$3507 ), + .CI(\s$3511 ), + .CON(\con$3968 ), + .SN(\sn$3970 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_36_0 ( + .A(\c$3501 ), + .B(\c$3505 ), + .CI(\c$3509 ), + .CON(\con$3972 ), + .SN(\sn$3974 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_36_1 ( + .A(\s$3515 ), + .B(\s$3519 ), + .CI(\s$3523 ), + .CON(\con$3976 ), + .SN(\sn$3978 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_37_0 ( + .A(\c$3513 ), + .B(\c$3517 ), + .CI(\c$3521 ), + .CON(\con$3980 ), + .SN(\sn$3982 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_37_1 ( + .A(\s$3527 ), + .B(\s$3531 ), + .CI(\s$3535 ), + .CON(\con$3984 ), + .SN(\sn$3986 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_38_0 ( + .A(\c$3525 ), + .B(\c$3529 ), + .CI(\c$3533 ), + .CON(\con$3988 ), + .SN(\sn$3990 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_38_1 ( + .A(\s$3539 ), + .B(\s$3543 ), + .CI(\s$3547 ), + .CON(\con$3992 ), + .SN(\sn$3994 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_39_0 ( + .A(\c$3537 ), + .B(\c$3541 ), + .CI(\c$3545 ), + .CON(\con$3996 ), + .SN(\sn$3998 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_39_1 ( + .A(\s$3551 ), + .B(\s$3555 ), + .CI(\s$3559 ), + .CON(\con$4000 ), + .SN(\sn$4002 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_40_0 ( + .A(\c$3549 ), + .B(\c$3553 ), + .CI(\c$3557 ), + .CON(\con$4004 ), + .SN(\sn$4006 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_40_1 ( + .A(\s$3563 ), + .B(\s$3567 ), + .CI(\s$3571 ), + .CON(\con$4008 ), + .SN(\sn$4010 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_41_0 ( + .A(\c$3561 ), + .B(\c$3565 ), + .CI(\c$3569 ), + .CON(\con$4012 ), + .SN(\sn$4014 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_41_1 ( + .A(\s$3575 ), + .B(\s$3579 ), + .CI(\s$3583 ), + .CON(\con$4016 ), + .SN(\sn$4018 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_42_0 ( + .A(\c$3573 ), + .B(\c$3577 ), + .CI(\c$3581 ), + .CON(\con$4020 ), + .SN(\sn$4022 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_42_1 ( + .A(\s$3587 ), + .B(\s$3591 ), + .CI(\s$3595 ), + .CON(\con$4024 ), + .SN(\sn$4026 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_43_0 ( + .A(\c$3585 ), + .B(\c$3589 ), + .CI(\c$3593 ), + .CON(\con$4028 ), + .SN(\sn$4030 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_43_1 ( + .A(\s$3599 ), + .B(\s$3603 ), + .CI(\s$3607 ), + .CON(\con$4032 ), + .SN(\sn$4034 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_44_0 ( + .A(\c$3597 ), + .B(\c$3601 ), + .CI(\c$3605 ), + .CON(\con$4036 ), + .SN(\sn$4038 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_44_1 ( + .A(\s$3611 ), + .B(\s$3615 ), + .CI(\s$3619 ), + .CON(\con$4040 ), + .SN(\sn$4042 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_45_0 ( + .A(\c$3609 ), + .B(\c$3613 ), + .CI(\c$3617 ), + .CON(\con$4044 ), + .SN(\sn$4046 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_45_1 ( + .A(\s$3623 ), + .B(\s$3627 ), + .CI(\s$3631 ), + .CON(\con$4048 ), + .SN(\sn$4050 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_46_0 ( + .A(\c$3621 ), + .B(\c$3625 ), + .CI(\c$3629 ), + .CON(\con$4052 ), + .SN(\sn$4054 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_46_1 ( + .A(\s$3635 ), + .B(\s$3639 ), + .CI(\s$3643 ), + .CON(\con$4056 ), + .SN(\sn$4058 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_47_0 ( + .A(\c$3633 ), + .B(\c$3637 ), + .CI(\c$3641 ), + .CON(\con$4060 ), + .SN(\sn$4062 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_47_1 ( + .A(\s$3647 ), + .B(\s$3651 ), + .CI(\s$3655 ), + .CON(\con$4064 ), + .SN(\sn$4066 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_48_0 ( + .A(\c$3645 ), + .B(\c$3649 ), + .CI(\c$3653 ), + .CON(\con$4068 ), + .SN(\sn$4070 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_48_1 ( + .A(\s$3659 ), + .B(\s$3663 ), + .CI(\s$3667 ), + .CON(\con$4072 ), + .SN(\sn$4074 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_49_0 ( + .A(\c$3657 ), + .B(\c$3661 ), + .CI(\c$3665 ), + .CON(\con$4076 ), + .SN(\sn$4078 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_49_1 ( + .A(\s$3671 ), + .B(\s$3675 ), + .CI(\s$3679 ), + .CON(\con$4080 ), + .SN(\sn$4082 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_50_0 ( + .A(\c$3669 ), + .B(\c$3673 ), + .CI(\c$3677 ), + .CON(\con$4084 ), + .SN(\sn$4086 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_50_1 ( + .A(\s$3683 ), + .B(\s$3687 ), + .CI(\s$3691 ), + .CON(\con$4088 ), + .SN(\sn$4090 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_51_0 ( + .A(\c$3681 ), + .B(\c$3685 ), + .CI(\c$3689 ), + .CON(\con$4092 ), + .SN(\sn$4094 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_51_1 ( + .A(\s$3695 ), + .B(\s$3699 ), + .CI(\s$3703 ), + .CON(\con$4096 ), + .SN(\sn$4098 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_52_0 ( + .A(\c$3693 ), + .B(\c$3697 ), + .CI(\c$3701 ), + .CON(\con$4100 ), + .SN(\sn$4102 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_52_1 ( + .A(\s$3707 ), + .B(\s$3711 ), + .CI(\s$3715 ), + .CON(\con$4104 ), + .SN(\sn$4106 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_53_0 ( + .A(pp_row53_6), + .B(\c$3705 ), + .CI(\c$3709 ), + .CON(\con$4108 ), + .SN(\sn$4110 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_53_1 ( + .A(\c$3713 ), + .B(\s$3719 ), + .CI(\s$3723 ), + .CON(\con$4112 ), + .SN(\sn$4114 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_54_0 ( + .A(pp_row54_5), + .B(pp_row54_6), + .CI(\c$3717 ), + .CON(\con$4116 ), + .SN(\sn$4118 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_54_1 ( + .A(\c$3721 ), + .B(\s$3727 ), + .CI(\s$3731 ), + .CON(\con$4120 ), + .SN(\sn$4122 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_55_0 ( + .A(pp_row55_3), + .B(pp_row55_4), + .CI(pp_row55_5), + .CON(\con$4124 ), + .SN(\sn$4126 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_55_1 ( + .A(\c$3725 ), + .B(\c$3729 ), + .CI(\s$3735 ), + .CON(\con$4128 ), + .SN(\sn$4130 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_56_0 ( + .A(pp_row56_2), + .B(pp_row56_3), + .CI(pp_row56_4), + .CON(\con$4132 ), + .SN(\sn$4134 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_56_1 ( + .A(pp_row56_5), + .B(\c$3733 ), + .CI(\s$3739 ), + .CON(\con$4136 ), + .SN(\sn$4138 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_57_0 ( + .A(pp_row57_0), + .B(pp_row57_1), + .CI(pp_row57_2), + .CON(\con$4140 ), + .SN(\sn$4142 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_57_1 ( + .A(pp_row57_3), + .B(pp_row57_4), + .CI(\c$3737 ), + .CON(\con$4144 ), + .SN(\sn$4146 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_58_0 ( + .A(1'h1), + .B(pp_row58_1), + .CI(pp_row58_2), + .CON(\con$4148 ), + .SN(\sn$4150 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_59_0 ( + .A(pp_row59_0), + .B(pp_row59_1), + .CI(pp_row59_2), + .CON(\con$4156 ), + .SN(\sn$4158 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_8_0 ( + .A(pp_row8_0), + .B(pp_row8_1), + .CI(pp_row8_2), + .CON(\con$3748 ), + .SN(\sn$3750 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_9_0 ( + .A(pp_row9_0), + .B(pp_row9_1), + .CI(pp_row9_2), + .CON(\con$3756 ), + .SN(\sn$3758 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_10_0 ( + .A(\c$3757 ), + .B(\c$3761 ), + .CI(\s$3767 ), + .CON(\con$4188 ), + .SN(\sn$4190 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_11_0 ( + .A(\c$3765 ), + .B(\c$3769 ), + .CI(\s$3775 ), + .CON(\con$4192 ), + .SN(\sn$4194 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_12_0 ( + .A(\c$3773 ), + .B(\c$3777 ), + .CI(\s$3783 ), + .CON(\con$4196 ), + .SN(\sn$4198 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_13_0 ( + .A(\c$3781 ), + .B(\c$3785 ), + .CI(\s$3791 ), + .CON(\con$4200 ), + .SN(\sn$4202 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_14_0 ( + .A(\c$3789 ), + .B(\c$3793 ), + .CI(\s$3799 ), + .CON(\con$4204 ), + .SN(\sn$4206 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_15_0 ( + .A(\c$3797 ), + .B(\c$3801 ), + .CI(\s$3807 ), + .CON(\con$4208 ), + .SN(\sn$4210 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_16_0 ( + .A(\c$3805 ), + .B(\c$3809 ), + .CI(\s$3815 ), + .CON(\con$4212 ), + .SN(\sn$4214 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_17_0 ( + .A(\c$3813 ), + .B(\c$3817 ), + .CI(\s$3823 ), + .CON(\con$4216 ), + .SN(\sn$4218 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_18_0 ( + .A(\c$3821 ), + .B(\c$3825 ), + .CI(\s$3831 ), + .CON(\con$4220 ), + .SN(\sn$4222 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_19_0 ( + .A(\c$3829 ), + .B(\c$3833 ), + .CI(\s$3839 ), + .CON(\con$4224 ), + .SN(\sn$4226 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_20_0 ( + .A(\c$3837 ), + .B(\c$3841 ), + .CI(\s$3847 ), + .CON(\con$4228 ), + .SN(\sn$4230 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_21_0 ( + .A(\c$3845 ), + .B(\c$3849 ), + .CI(\s$3855 ), + .CON(\con$4232 ), + .SN(\sn$4234 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_22_0 ( + .A(\c$3853 ), + .B(\c$3857 ), + .CI(\s$3863 ), + .CON(\con$4236 ), + .SN(\sn$4238 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_23_0 ( + .A(\c$3861 ), + .B(\c$3865 ), + .CI(\s$3871 ), + .CON(\con$4240 ), + .SN(\sn$4242 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_24_0 ( + .A(\c$3869 ), + .B(\c$3873 ), + .CI(\s$3879 ), + .CON(\con$4244 ), + .SN(\sn$4246 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_25_0 ( + .A(\c$3877 ), + .B(\c$3881 ), + .CI(\s$3887 ), + .CON(\con$4248 ), + .SN(\sn$4250 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_26_0 ( + .A(\c$3885 ), + .B(\c$3889 ), + .CI(\s$3895 ), + .CON(\con$4252 ), + .SN(\sn$4254 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_27_0 ( + .A(\c$3893 ), + .B(\c$3897 ), + .CI(\s$3903 ), + .CON(\con$4256 ), + .SN(\sn$4258 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_28_0 ( + .A(\c$3901 ), + .B(\c$3905 ), + .CI(\s$3911 ), + .CON(\con$4260 ), + .SN(\sn$4262 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_29_0 ( + .A(\c$3909 ), + .B(\c$3913 ), + .CI(\s$3919 ), + .CON(\con$4264 ), + .SN(\sn$4266 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_30_0 ( + .A(\c$3917 ), + .B(\c$3921 ), + .CI(\s$3927 ), + .CON(\con$4268 ), + .SN(\sn$4270 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_31_0 ( + .A(\c$3925 ), + .B(\c$3929 ), + .CI(\s$3935 ), + .CON(\con$4272 ), + .SN(\sn$4274 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_32_0 ( + .A(\c$3933 ), + .B(\c$3937 ), + .CI(\s$3943 ), + .CON(\con$4276 ), + .SN(\sn$4278 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_33_0 ( + .A(\c$3941 ), + .B(\c$3945 ), + .CI(\s$3951 ), + .CON(\con$4280 ), + .SN(\sn$4282 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_34_0 ( + .A(\c$3949 ), + .B(\c$3953 ), + .CI(\s$3959 ), + .CON(\con$4284 ), + .SN(\sn$4286 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_35_0 ( + .A(\c$3957 ), + .B(\c$3961 ), + .CI(\s$3967 ), + .CON(\con$4288 ), + .SN(\sn$4290 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_36_0 ( + .A(\c$3965 ), + .B(\c$3969 ), + .CI(\s$3975 ), + .CON(\con$4292 ), + .SN(\sn$4294 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_37_0 ( + .A(\c$3973 ), + .B(\c$3977 ), + .CI(\s$3983 ), + .CON(\con$4296 ), + .SN(\sn$4298 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_38_0 ( + .A(\c$3981 ), + .B(\c$3985 ), + .CI(\s$3991 ), + .CON(\con$4300 ), + .SN(\sn$4302 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_39_0 ( + .A(\c$3989 ), + .B(\c$3993 ), + .CI(\s$3999 ), + .CON(\con$4304 ), + .SN(\sn$4306 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_40_0 ( + .A(\c$3997 ), + .B(\c$4001 ), + .CI(\s$4007 ), + .CON(\con$4308 ), + .SN(\sn$4310 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_41_0 ( + .A(\c$4005 ), + .B(\c$4009 ), + .CI(\s$4015 ), + .CON(\con$4312 ), + .SN(\sn$4314 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_42_0 ( + .A(\c$4013 ), + .B(\c$4017 ), + .CI(\s$4023 ), + .CON(\con$4316 ), + .SN(\sn$4318 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_43_0 ( + .A(\c$4021 ), + .B(\c$4025 ), + .CI(\s$4031 ), + .CON(\con$4320 ), + .SN(\sn$4322 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_44_0 ( + .A(\c$4029 ), + .B(\c$4033 ), + .CI(\s$4039 ), + .CON(\con$4324 ), + .SN(\sn$4326 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_45_0 ( + .A(\c$4037 ), + .B(\c$4041 ), + .CI(\s$4047 ), + .CON(\con$4328 ), + .SN(\sn$4330 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_46_0 ( + .A(\c$4045 ), + .B(\c$4049 ), + .CI(\s$4055 ), + .CON(\con$4332 ), + .SN(\sn$4334 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_47_0 ( + .A(\c$4053 ), + .B(\c$4057 ), + .CI(\s$4063 ), + .CON(\con$4336 ), + .SN(\sn$4338 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_48_0 ( + .A(\c$4061 ), + .B(\c$4065 ), + .CI(\s$4071 ), + .CON(\con$4340 ), + .SN(\sn$4342 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_49_0 ( + .A(\c$4069 ), + .B(\c$4073 ), + .CI(\s$4079 ), + .CON(\con$4344 ), + .SN(\sn$4346 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_50_0 ( + .A(\c$4077 ), + .B(\c$4081 ), + .CI(\s$4087 ), + .CON(\con$4348 ), + .SN(\sn$4350 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_51_0 ( + .A(\c$4085 ), + .B(\c$4089 ), + .CI(\s$4095 ), + .CON(\con$4352 ), + .SN(\sn$4354 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_52_0 ( + .A(\c$4093 ), + .B(\c$4097 ), + .CI(\s$4103 ), + .CON(\con$4356 ), + .SN(\sn$4358 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_53_0 ( + .A(\c$4101 ), + .B(\c$4105 ), + .CI(\s$4111 ), + .CON(\con$4360 ), + .SN(\sn$4362 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_54_0 ( + .A(\c$4109 ), + .B(\c$4113 ), + .CI(\s$4119 ), + .CON(\con$4364 ), + .SN(\sn$4366 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_55_0 ( + .A(\c$4117 ), + .B(\c$4121 ), + .CI(\s$4127 ), + .CON(\con$4368 ), + .SN(\sn$4370 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_56_0 ( + .A(\c$4125 ), + .B(\c$4129 ), + .CI(\s$4135 ), + .CON(\con$4372 ), + .SN(\sn$4374 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_57_0 ( + .A(\c$4133 ), + .B(\c$4137 ), + .CI(\s$4143 ), + .CON(\con$4376 ), + .SN(\sn$4378 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_58_0 ( + .A(\c$4141 ), + .B(\c$4145 ), + .CI(\s$4151 ), + .CON(\con$4380 ), + .SN(\sn$4382 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_59_0 ( + .A(pp_row59_3), + .B(\c$4149 ), + .CI(\c$4153 ), + .CON(\con$4384 ), + .SN(\sn$4386 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_60_0 ( + .A(pp_row60_2), + .B(pp_row60_3), + .CI(\c$4157 ), + .CON(\con$4388 ), + .SN(\sn$4390 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_61_0 ( + .A(pp_row61_0), + .B(pp_row61_1), + .CI(pp_row61_2), + .CON(\con$4392 ), + .SN(\sn$4394 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_6_0 ( + .A(pp_row6_2), + .B(pp_row6_3), + .CI(pp_row6_4), + .CON(\con$4172 ), + .SN(\sn$4174 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_7_0 ( + .A(pp_row7_2), + .B(pp_row7_3), + .CI(\c$3741 ), + .CON(\con$4176 ), + .SN(\sn$4178 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_8_0 ( + .A(pp_row8_5), + .B(\c$3745 ), + .CI(\s$3751 ), + .CON(\con$4180 ), + .SN(\sn$4182 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_9_0 ( + .A(\c$3749 ), + .B(\c$3753 ), + .CI(\s$3759 ), + .CON(\con$4184 ), + .SN(\sn$4186 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_10_0 ( + .A(\s$3771 ), + .B(\c$4185 ), + .CI(\s$4191 ), + .CON(\con$4416 ), + .SN(\sn$4417 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_11_0 ( + .A(\s$3779 ), + .B(\c$4189 ), + .CI(\s$4195 ), + .CON(\con$4418 ), + .SN(\sn$4419 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_12_0 ( + .A(\s$3787 ), + .B(\c$4193 ), + .CI(\s$4199 ), + .CON(\con$4420 ), + .SN(\sn$4421 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_13_0 ( + .A(\s$3795 ), + .B(\c$4197 ), + .CI(\s$4203 ), + .CON(\con$4422 ), + .SN(\sn$4423 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_14_0 ( + .A(\s$3803 ), + .B(\c$4201 ), + .CI(\s$4207 ), + .CON(\con$4424 ), + .SN(\sn$4425 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_15_0 ( + .A(\s$3811 ), + .B(\c$4205 ), + .CI(\s$4211 ), + .CON(\con$4426 ), + .SN(\sn$4427 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_16_0 ( + .A(\s$3819 ), + .B(\c$4209 ), + .CI(\s$4215 ), + .CON(\con$4428 ), + .SN(\sn$4429 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_17_0 ( + .A(\s$3827 ), + .B(\c$4213 ), + .CI(\s$4219 ), + .CON(\con$4430 ), + .SN(\sn$4431 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_18_0 ( + .A(\s$3835 ), + .B(\c$4217 ), + .CI(\s$4223 ), + .CON(\con$4432 ), + .SN(\sn$4433 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_19_0 ( + .A(\s$3843 ), + .B(\c$4221 ), + .CI(\s$4227 ), + .CON(\con$4434 ), + .SN(\sn$4435 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_20_0 ( + .A(\s$3851 ), + .B(\c$4225 ), + .CI(\s$4231 ), + .CON(\con$4436 ), + .SN(\sn$4437 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_21_0 ( + .A(\s$3859 ), + .B(\c$4229 ), + .CI(\s$4235 ), + .CON(\con$4438 ), + .SN(\sn$4439 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_22_0 ( + .A(\s$3867 ), + .B(\c$4233 ), + .CI(\s$4239 ), + .CON(\con$4440 ), + .SN(\sn$4441 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_23_0 ( + .A(\s$3875 ), + .B(\c$4237 ), + .CI(\s$4243 ), + .CON(\con$4442 ), + .SN(\sn$4443 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_24_0 ( + .A(\s$3883 ), + .B(\c$4241 ), + .CI(\s$4247 ), + .CON(\con$4444 ), + .SN(\sn$4445 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_25_0 ( + .A(\s$3891 ), + .B(\c$4245 ), + .CI(\s$4251 ), + .CON(\con$4446 ), + .SN(\sn$4447 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_26_0 ( + .A(\s$3899 ), + .B(\c$4249 ), + .CI(\s$4255 ), + .CON(\con$4448 ), + .SN(\sn$4449 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_27_0 ( + .A(\s$3907 ), + .B(\c$4253 ), + .CI(\s$4259 ), + .CON(\con$4450 ), + .SN(\sn$4451 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_28_0 ( + .A(\s$3915 ), + .B(\c$4257 ), + .CI(\s$4263 ), + .CON(\con$4452 ), + .SN(\sn$4453 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_29_0 ( + .A(\s$3923 ), + .B(\c$4261 ), + .CI(\s$4267 ), + .CON(\con$4454 ), + .SN(\sn$4455 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_30_0 ( + .A(\s$3931 ), + .B(\c$4265 ), + .CI(\s$4271 ), + .CON(\con$4456 ), + .SN(\sn$4457 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_31_0 ( + .A(\s$3939 ), + .B(\c$4269 ), + .CI(\s$4275 ), + .CON(\con$4458 ), + .SN(\sn$4459 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_32_0 ( + .A(\s$3947 ), + .B(\c$4273 ), + .CI(\s$4279 ), + .CON(\con$4460 ), + .SN(\sn$4461 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_33_0 ( + .A(\s$3955 ), + .B(\c$4277 ), + .CI(\s$4283 ), + .CON(\con$4462 ), + .SN(\sn$4463 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_34_0 ( + .A(\s$3963 ), + .B(\c$4281 ), + .CI(\s$4287 ), + .CON(\con$4464 ), + .SN(\sn$4465 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_35_0 ( + .A(\s$3971 ), + .B(\c$4285 ), + .CI(\s$4291 ), + .CON(\con$4466 ), + .SN(\sn$4467 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_36_0 ( + .A(\s$3979 ), + .B(\c$4289 ), + .CI(\s$4295 ), + .CON(\con$4468 ), + .SN(\sn$4469 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_37_0 ( + .A(\s$3987 ), + .B(\c$4293 ), + .CI(\s$4299 ), + .CON(\con$4470 ), + .SN(\sn$4471 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_38_0 ( + .A(\s$3995 ), + .B(\c$4297 ), + .CI(\s$4303 ), + .CON(\con$4472 ), + .SN(\sn$4473 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_39_0 ( + .A(\s$4003 ), + .B(\c$4301 ), + .CI(\s$4307 ), + .CON(\con$4474 ), + .SN(\sn$4475 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_40_0 ( + .A(\s$4011 ), + .B(\c$4305 ), + .CI(\s$4311 ), + .CON(\con$4476 ), + .SN(\sn$4477 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_41_0 ( + .A(\s$4019 ), + .B(\c$4309 ), + .CI(\s$4315 ), + .CON(\con$4478 ), + .SN(\sn$4479 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_42_0 ( + .A(\s$4027 ), + .B(\c$4313 ), + .CI(\s$4319 ), + .CON(\con$4480 ), + .SN(\sn$4481 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_43_0 ( + .A(\s$4035 ), + .B(\c$4317 ), + .CI(\s$4323 ), + .CON(\con$4482 ), + .SN(\sn$4483 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_44_0 ( + .A(\s$4043 ), + .B(\c$4321 ), + .CI(\s$4327 ), + .CON(\con$4484 ), + .SN(\sn$4485 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_45_0 ( + .A(\s$4051 ), + .B(\c$4325 ), + .CI(\s$4331 ), + .CON(\con$4486 ), + .SN(\sn$4487 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_46_0 ( + .A(\s$4059 ), + .B(\c$4329 ), + .CI(\s$4335 ), + .CON(\con$4488 ), + .SN(\sn$4489 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_47_0 ( + .A(\s$4067 ), + .B(\c$4333 ), + .CI(\s$4339 ), + .CON(\con$4490 ), + .SN(\sn$4491 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_48_0 ( + .A(\s$4075 ), + .B(\c$4337 ), + .CI(\s$4343 ), + .CON(\con$4492 ), + .SN(\sn$4493 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_49_0 ( + .A(\s$4083 ), + .B(\c$4341 ), + .CI(\s$4347 ), + .CON(\con$4494 ), + .SN(\sn$4495 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_4_0 ( + .A(pp_row4_2), + .B(pp_row4_3), + .CI(\s$4167 ), + .CON(\con$4404 ), + .SN(\sn$4405 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_50_0 ( + .A(\s$4091 ), + .B(\c$4345 ), + .CI(\s$4351 ), + .CON(\con$4496 ), + .SN(\sn$4497 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_51_0 ( + .A(\s$4099 ), + .B(\c$4349 ), + .CI(\s$4355 ), + .CON(\con$4498 ), + .SN(\sn$4499 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_52_0 ( + .A(\s$4107 ), + .B(\c$4353 ), + .CI(\s$4359 ), + .CON(\con$4500 ), + .SN(\sn$4501 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_53_0 ( + .A(\s$4115 ), + .B(\c$4357 ), + .CI(\s$4363 ), + .CON(\con$4502 ), + .SN(\sn$4503 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_54_0 ( + .A(\s$4123 ), + .B(\c$4361 ), + .CI(\s$4367 ), + .CON(\con$4504 ), + .SN(\sn$4505 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_55_0 ( + .A(\s$4131 ), + .B(\c$4365 ), + .CI(\s$4371 ), + .CON(\con$4506 ), + .SN(\sn$4507 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_56_0 ( + .A(\s$4139 ), + .B(\c$4369 ), + .CI(\s$4375 ), + .CON(\con$4508 ), + .SN(\sn$4509 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_57_0 ( + .A(\s$4147 ), + .B(\c$4373 ), + .CI(\s$4379 ), + .CON(\con$4510 ), + .SN(\sn$4511 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_58_0 ( + .A(\s$4155 ), + .B(\c$4377 ), + .CI(\s$4383 ), + .CON(\con$4512 ), + .SN(\sn$4513 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_59_0 ( + .A(\s$4159 ), + .B(\c$4381 ), + .CI(\s$4387 ), + .CON(\con$4514 ), + .SN(\sn$4515 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_5_0 ( + .A(pp_row5_2), + .B(\c$4165 ), + .CI(\s$4171 ), + .CON(\con$4406 ), + .SN(\sn$4407 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_60_0 ( + .A(\s$4163 ), + .B(\c$4385 ), + .CI(\s$4391 ), + .CON(\con$4516 ), + .SN(\sn$4517 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_61_0 ( + .A(\c$4161 ), + .B(\c$4389 ), + .CI(\s$4395 ), + .CON(\con$4518 ), + .SN(\sn$4519 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_62_0 ( + .A(pp_row62_2), + .B(\c$4393 ), + .CI(\s$4399 ), + .CON(\con$4520 ), + .SN(\sn$4521 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_63_0 ( + .A(pp_row63_0), + .B(pp_row63_1), + .CI(\c$4397 ), + .CON(\con$4522 ), + .SN(\sn$4523 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_6_0 ( + .A(\s$3743 ), + .B(\c$4169 ), + .CI(\s$4175 ), + .CON(\con$4408 ), + .SN(\sn$4409 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_7_0 ( + .A(\s$3747 ), + .B(\c$4173 ), + .CI(\s$4179 ), + .CON(\con$4410 ), + .SN(\sn$4411 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_8_0 ( + .A(\s$3755 ), + .B(\c$4177 ), + .CI(\s$4183 ), + .CON(\con$4412 ), + .SN(\sn$4413 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_9_0 ( + .A(\s$3763 ), + .B(\c$4181 ), + .CI(\s$4187 ), + .CON(\con$4414 ), + .SN(\sn$4415 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_24_0 ( + .A(pp_row24_0), + .B(pp_row24_1), + .CON(con), + .SN(sn) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_25_0 ( + .A(pp_row25_0), + .B(pp_row25_1), + .CON(\con$2556 ), + .SN(\sn$2558 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_26_1 ( + .A(pp_row26_3), + .B(pp_row26_4), + .CON(\con$2564 ), + .SN(\sn$2566 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_27_1 ( + .A(pp_row27_3), + .B(pp_row27_4), + .CON(\con$2572 ), + .SN(\sn$2574 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_28_2 ( + .A(pp_row28_6), + .B(pp_row28_7), + .CON(\con$2584 ), + .SN(\sn$2586 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_29_2 ( + .A(pp_row29_6), + .B(pp_row29_7), + .CON(\con$2596 ), + .SN(\sn$2598 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_30_3 ( + .A(pp_row30_9), + .B(pp_row30_10), + .CON(\con$2612 ), + .SN(\sn$2614 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_31_3 ( + .A(pp_row31_9), + .B(pp_row31_10), + .CON(\con$2628 ), + .SN(\sn$2630 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_36_3 ( + .A(pp_row36_9), + .B(pp_row36_10), + .CON(\con$2708 ), + .SN(\sn$2710 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_38_2 ( + .A(pp_row38_6), + .B(pp_row38_7), + .CON(\con$2732 ), + .SN(\sn$2734 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_40_1 ( + .A(pp_row40_3), + .B(pp_row40_4), + .CON(\con$2748 ), + .SN(\sn$2750 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_42_0 ( + .A(1'h1), + .B(pp_row42_1), + .CON(\con$2756 ), + .SN(\sn$2758 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_16_0 ( + .A(pp_row16_0), + .B(pp_row16_1), + .CON(\con$2760 ), + .SN(\sn$2762 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_17_0 ( + .A(pp_row17_0), + .B(pp_row17_1), + .CON(\con$2764 ), + .SN(\sn$2766 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_18_1 ( + .A(pp_row18_3), + .B(pp_row18_4), + .CON(\con$2772 ), + .SN(\sn$2774 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_19_1 ( + .A(pp_row19_3), + .B(pp_row19_4), + .CON(\con$2780 ), + .SN(\sn$2782 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_20_2 ( + .A(pp_row20_6), + .B(pp_row20_7), + .CON(\con$2792 ), + .SN(\sn$2794 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_21_2 ( + .A(pp_row21_6), + .B(pp_row21_7), + .CON(\con$2804 ), + .SN(\sn$2806 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_22_3 ( + .A(pp_row22_9), + .B(pp_row22_10), + .CON(\con$2820 ), + .SN(\sn$2822 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_23_3 ( + .A(pp_row23_9), + .B(pp_row23_10), + .CON(\con$2836 ), + .SN(\sn$2838 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_44_3 ( + .A(pp_row44_9), + .B(pp_row44_10), + .CON(\con$3172 ), + .SN(\sn$3174 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_46_2 ( + .A(pp_row46_6), + .B(pp_row46_7), + .CON(\con$3196 ), + .SN(\sn$3198 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_48_1 ( + .A(pp_row48_3), + .B(pp_row48_4), + .CON(\con$3212 ), + .SN(\sn$3214 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_50_0 ( + .A(1'h1), + .B(pp_row50_1), + .CON(\con$3220 ), + .SN(\sn$3222 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_10_0 ( + .A(pp_row10_0), + .B(pp_row10_1), + .CON(\con$3224 ), + .SN(\sn$3226 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_11_0 ( + .A(pp_row11_0), + .B(pp_row11_1), + .CON(\con$3228 ), + .SN(\sn$3230 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_12_1 ( + .A(pp_row12_3), + .B(pp_row12_4), + .CON(\con$3236 ), + .SN(\sn$3238 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_13_1 ( + .A(pp_row13_3), + .B(pp_row13_4), + .CON(\con$3244 ), + .SN(\sn$3246 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_14_2 ( + .A(pp_row14_6), + .B(pp_row14_7), + .CON(\con$3256 ), + .SN(\sn$3258 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_15_2 ( + .A(pp_row15_6), + .B(pp_row15_7), + .CON(\con$3268 ), + .SN(\sn$3270 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_52_2 ( + .A(pp_row52_6), + .B(pp_row52_7), + .CON(\con$3712 ), + .SN(\sn$3714 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_54_1 ( + .A(pp_row54_3), + .B(pp_row54_4), + .CON(\con$3728 ), + .SN(\sn$3730 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_56_0 ( + .A(1'h1), + .B(pp_row56_1), + .CON(\con$3736 ), + .SN(\sn$3738 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_58_1 ( + .A(pp_row58_3), + .B(pp_row58_4), + .CON(\con$4152 ), + .SN(\sn$4154 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_60_0 ( + .A(1'h1), + .B(pp_row60_1), + .CON(\con$4160 ), + .SN(\sn$4162 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_6_0 ( + .A(pp_row6_0), + .B(pp_row6_1), + .CON(\con$3740 ), + .SN(\sn$3742 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_7_0 ( + .A(pp_row7_0), + .B(pp_row7_1), + .CON(\con$3744 ), + .SN(\sn$3746 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_8_1 ( + .A(pp_row8_3), + .B(pp_row8_4), + .CON(\con$3752 ), + .SN(\sn$3754 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_9_1 ( + .A(pp_row9_3), + .B(pp_row9_4), + .CON(\con$3760 ), + .SN(\sn$3762 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_4_0 ( + .A(pp_row4_0), + .B(pp_row4_1), + .CON(\con$4164 ), + .SN(\sn$4166 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_5_0 ( + .A(pp_row5_0), + .B(pp_row5_1), + .CON(\con$4168 ), + .SN(\sn$4170 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_62_0 ( + .A(1'h1), + .B(pp_row62_1), + .CON(\con$4396 ), + .SN(\sn$4398 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_2_0 ( + .A(pp_row2_0), + .B(pp_row2_1), + .CON(\con$4400 ), + .SN(\sn$4401 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_3_0 ( + .A(pp_row3_0), + .B(pp_row3_1), + .CON(\con$4402 ), + .SN(\sn$4403 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_64_0 ( + .A(1'h1), + .B(pp_row64_1), + .CON(\con$4524 ), + .SN(\sn$4525 ) + ); + \multiplier.final_adder final_adder ( + .a(final_a_registered), + .b(final_b_registered), + .\port$901$0 (\$54 ), + .\port$902$0 (\$55 ), + .\port$903$0 (\$56 ), + .\port$904$0 (\$57 ), + .\port$905$0 (\$58 ), + .\port$906$0 (\$59 ), + .\port$907$0 (\$60 ), + .\port$908$0 (\$61 ), + .\port$909$0 (\$62 ), + .\port$910$0 (\$63 ), + .\port$911$0 (\$64 ), + .\port$912$0 (\$65 ), + .\port$913$0 (\$66 ), + .\port$914$0 (\$67 ), + .\port$915$0 (\$68 ), + .\port$916$0 (\$69 ), + .\port$917$0 (\$70 ), + .\port$918$0 (\$71 ), + .\port$919$0 (\$72 ), + .\port$920$0 (\$73 ), + .\port$921$0 (\$74 ), + .\port$922$0 (\$75 ), + .\port$923$0 (\$76 ), + .\port$924$0 (\$77 ), + .\port$925$0 (\$78 ), + .\port$926$0 (\$79 ), + .\port$927$0 (\$80 ), + .\port$928$0 (\$81 ), + .\port$929$0 (\$82 ), + .\port$930$0 (\$83 ), + .\port$931$0 (\$84 ), + .\port$932$0 (\$85 ), + .\port$933$0 (\$86 ), + .\port$934$0 (\$87 ), + .\port$935$0 (\$88 ), + .\port$936$0 (\$89 ), + .\port$937$0 (\$90 ), + .\port$938$0 (\$91 ), + .\port$939$0 (\$92 ), + .\port$940$0 (\$93 ), + .\port$941$0 (\$94 ), + .\port$942$0 (\$95 ), + .\port$943$0 (\$96 ), + .\port$944$0 (\$97 ), + .\port$945$0 (\$98 ), + .\port$946$0 (\$99 ), + .\port$947$0 (\$100 ), + .\port$948$0 (\$101 ), + .\port$949$0 (\$102 ), + .\port$950$0 (\$103 ), + .\port$951$0 (\$104 ), + .\port$952$0 (\$105 ), + .\port$953$0 (\$106 ), + .\port$954$0 (\$107 ), + .\port$955$0 (\$108 ), + .\port$956$0 (\$109 ), + .\port$957$0 (\$110 ), + .\port$958$0 (\$111 ), + .\port$959$0 (\$112 ), + .\port$960$0 (\$113 ), + .\port$961$0 (\$114 ), + .\port$962$0 (\$115 ), + .\port$963$0 (\$116 ), + .\port$964$0 (\$117 ) + ); + assign booth_block0_sign = a_registered[1]; + assign booth_block2_sign = a_registered[3]; + assign booth_block4_sign = a_registered[5]; + assign booth_block6_sign = a_registered[7]; + assign booth_block8_sign = a_registered[9]; + assign booth_block10_sign = a_registered[11]; + assign booth_block12_sign = a_registered[13]; + assign booth_block14_sign = a_registered[15]; + assign booth_block16_sign = a_registered[17]; + assign booth_block18_sign = a_registered[19]; + assign booth_block20_sign = a_registered[21]; + assign booth_block22_sign = a_registered[23]; + assign booth_block24_sign = a_registered[25]; + assign booth_block26_sign = a_registered[27]; + assign booth_block28_sign = a_registered[29]; + assign booth_block30_sign = a_registered[31]; + assign result_registered = o; + assign result = { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + assign multiplier = { 2'h0, a_registered, 1'h0 }; + assign multiplicand = { 1'h0, b_registered, 1'h0 }; + assign booth_block0 = { a_registered[1:0], 1'h0 }; + assign booth_block0_sel = { sel_1, sel_0 }; + assign booth_block0_mand0 = { b_registered[0], 1'h0 }; + assign booth_block0_mand1 = b_registered[1:0]; + assign booth_block0_mand2 = b_registered[2:1]; + assign booth_block0_mand3 = b_registered[3:2]; + assign booth_block0_mand4 = b_registered[4:3]; + assign booth_block0_mand5 = b_registered[5:4]; + assign booth_block0_mand6 = b_registered[6:5]; + assign booth_block0_mand7 = b_registered[7:6]; + assign booth_block0_mand8 = b_registered[8:7]; + assign booth_block0_mand9 = b_registered[9:8]; + assign booth_block0_mand10 = b_registered[10:9]; + assign booth_block0_mand11 = b_registered[11:10]; + assign booth_block0_mand12 = b_registered[12:11]; + assign booth_block0_mand13 = b_registered[13:12]; + assign booth_block0_mand14 = b_registered[14:13]; + assign booth_block0_mand15 = b_registered[15:14]; + assign booth_block0_mand16 = b_registered[16:15]; + assign booth_block0_mand17 = b_registered[17:16]; + assign booth_block0_mand18 = b_registered[18:17]; + assign booth_block0_mand19 = b_registered[19:18]; + assign booth_block0_mand20 = b_registered[20:19]; + assign booth_block0_mand21 = b_registered[21:20]; + assign booth_block0_mand22 = b_registered[22:21]; + assign booth_block0_mand23 = b_registered[23:22]; + assign booth_block0_mand24 = b_registered[24:23]; + assign booth_block0_mand25 = b_registered[25:24]; + assign booth_block0_mand26 = b_registered[26:25]; + assign booth_block0_mand27 = b_registered[27:26]; + assign booth_block0_mand28 = b_registered[28:27]; + assign booth_block0_mand29 = b_registered[29:28]; + assign booth_block0_mand30 = b_registered[30:29]; + assign booth_block0_mand31 = b_registered[31:30]; + assign booth_block0_mand32 = { 1'h0, b_registered[31] }; + assign booth_block2 = a_registered[3:1]; + assign booth_block2_sel = { \sel_1$1366 , \sel_0$1365 }; + assign booth_block2_mand0 = { b_registered[0], 1'h0 }; + assign booth_block2_mand1 = b_registered[1:0]; + assign booth_block2_mand2 = b_registered[2:1]; + assign booth_block2_mand3 = b_registered[3:2]; + assign booth_block2_mand4 = b_registered[4:3]; + assign booth_block2_mand5 = b_registered[5:4]; + assign booth_block2_mand6 = b_registered[6:5]; + assign booth_block2_mand7 = b_registered[7:6]; + assign booth_block2_mand8 = b_registered[8:7]; + assign booth_block2_mand9 = b_registered[9:8]; + assign booth_block2_mand10 = b_registered[10:9]; + assign booth_block2_mand11 = b_registered[11:10]; + assign booth_block2_mand12 = b_registered[12:11]; + assign booth_block2_mand13 = b_registered[13:12]; + assign booth_block2_mand14 = b_registered[14:13]; + assign booth_block2_mand15 = b_registered[15:14]; + assign booth_block2_mand16 = b_registered[16:15]; + assign booth_block2_mand17 = b_registered[17:16]; + assign booth_block2_mand18 = b_registered[18:17]; + assign booth_block2_mand19 = b_registered[19:18]; + assign booth_block2_mand20 = b_registered[20:19]; + assign booth_block2_mand21 = b_registered[21:20]; + assign booth_block2_mand22 = b_registered[22:21]; + assign booth_block2_mand23 = b_registered[23:22]; + assign booth_block2_mand24 = b_registered[24:23]; + assign booth_block2_mand25 = b_registered[25:24]; + assign booth_block2_mand26 = b_registered[26:25]; + assign booth_block2_mand27 = b_registered[27:26]; + assign booth_block2_mand28 = b_registered[28:27]; + assign booth_block2_mand29 = b_registered[29:28]; + assign booth_block2_mand30 = b_registered[30:29]; + assign booth_block2_mand31 = b_registered[31:30]; + assign booth_block2_mand32 = { 1'h0, b_registered[31] }; + assign booth_block4 = a_registered[5:3]; + assign booth_block4_sel = { \sel_1$1403 , \sel_0$1402 }; + assign booth_block4_mand0 = { b_registered[0], 1'h0 }; + assign booth_block4_mand1 = b_registered[1:0]; + assign booth_block4_mand2 = b_registered[2:1]; + assign booth_block4_mand3 = b_registered[3:2]; + assign booth_block4_mand4 = b_registered[4:3]; + assign booth_block4_mand5 = b_registered[5:4]; + assign booth_block4_mand6 = b_registered[6:5]; + assign booth_block4_mand7 = b_registered[7:6]; + assign booth_block4_mand8 = b_registered[8:7]; + assign booth_block4_mand9 = b_registered[9:8]; + assign booth_block4_mand10 = b_registered[10:9]; + assign booth_block4_mand11 = b_registered[11:10]; + assign booth_block4_mand12 = b_registered[12:11]; + assign booth_block4_mand13 = b_registered[13:12]; + assign booth_block4_mand14 = b_registered[14:13]; + assign booth_block4_mand15 = b_registered[15:14]; + assign booth_block4_mand16 = b_registered[16:15]; + assign booth_block4_mand17 = b_registered[17:16]; + assign booth_block4_mand18 = b_registered[18:17]; + assign booth_block4_mand19 = b_registered[19:18]; + assign booth_block4_mand20 = b_registered[20:19]; + assign booth_block4_mand21 = b_registered[21:20]; + assign booth_block4_mand22 = b_registered[22:21]; + assign booth_block4_mand23 = b_registered[23:22]; + assign booth_block4_mand24 = b_registered[24:23]; + assign booth_block4_mand25 = b_registered[25:24]; + assign booth_block4_mand26 = b_registered[26:25]; + assign booth_block4_mand27 = b_registered[27:26]; + assign booth_block4_mand28 = b_registered[28:27]; + assign booth_block4_mand29 = b_registered[29:28]; + assign booth_block4_mand30 = b_registered[30:29]; + assign booth_block4_mand31 = b_registered[31:30]; + assign booth_block4_mand32 = { 1'h0, b_registered[31] }; + assign booth_block6 = a_registered[7:5]; + assign booth_block6_sel = { \sel_1$1440 , \sel_0$1439 }; + assign booth_block6_mand0 = { b_registered[0], 1'h0 }; + assign booth_block6_mand1 = b_registered[1:0]; + assign booth_block6_mand2 = b_registered[2:1]; + assign booth_block6_mand3 = b_registered[3:2]; + assign booth_block6_mand4 = b_registered[4:3]; + assign booth_block6_mand5 = b_registered[5:4]; + assign booth_block6_mand6 = b_registered[6:5]; + assign booth_block6_mand7 = b_registered[7:6]; + assign booth_block6_mand8 = b_registered[8:7]; + assign booth_block6_mand9 = b_registered[9:8]; + assign booth_block6_mand10 = b_registered[10:9]; + assign booth_block6_mand11 = b_registered[11:10]; + assign booth_block6_mand12 = b_registered[12:11]; + assign booth_block6_mand13 = b_registered[13:12]; + assign booth_block6_mand14 = b_registered[14:13]; + assign booth_block6_mand15 = b_registered[15:14]; + assign booth_block6_mand16 = b_registered[16:15]; + assign booth_block6_mand17 = b_registered[17:16]; + assign booth_block6_mand18 = b_registered[18:17]; + assign booth_block6_mand19 = b_registered[19:18]; + assign booth_block6_mand20 = b_registered[20:19]; + assign booth_block6_mand21 = b_registered[21:20]; + assign booth_block6_mand22 = b_registered[22:21]; + assign booth_block6_mand23 = b_registered[23:22]; + assign booth_block6_mand24 = b_registered[24:23]; + assign booth_block6_mand25 = b_registered[25:24]; + assign booth_block6_mand26 = b_registered[26:25]; + assign booth_block6_mand27 = b_registered[27:26]; + assign booth_block6_mand28 = b_registered[28:27]; + assign booth_block6_mand29 = b_registered[29:28]; + assign booth_block6_mand30 = b_registered[30:29]; + assign booth_block6_mand31 = b_registered[31:30]; + assign booth_block6_mand32 = { 1'h0, b_registered[31] }; + assign booth_block8 = a_registered[9:7]; + assign booth_block8_sel = { \sel_1$1477 , \sel_0$1476 }; + assign booth_block8_mand0 = { b_registered[0], 1'h0 }; + assign booth_block8_mand1 = b_registered[1:0]; + assign booth_block8_mand2 = b_registered[2:1]; + assign booth_block8_mand3 = b_registered[3:2]; + assign booth_block8_mand4 = b_registered[4:3]; + assign booth_block8_mand5 = b_registered[5:4]; + assign booth_block8_mand6 = b_registered[6:5]; + assign booth_block8_mand7 = b_registered[7:6]; + assign booth_block8_mand8 = b_registered[8:7]; + assign booth_block8_mand9 = b_registered[9:8]; + assign booth_block8_mand10 = b_registered[10:9]; + assign booth_block8_mand11 = b_registered[11:10]; + assign booth_block8_mand12 = b_registered[12:11]; + assign booth_block8_mand13 = b_registered[13:12]; + assign booth_block8_mand14 = b_registered[14:13]; + assign booth_block8_mand15 = b_registered[15:14]; + assign booth_block8_mand16 = b_registered[16:15]; + assign booth_block8_mand17 = b_registered[17:16]; + assign booth_block8_mand18 = b_registered[18:17]; + assign booth_block8_mand19 = b_registered[19:18]; + assign booth_block8_mand20 = b_registered[20:19]; + assign booth_block8_mand21 = b_registered[21:20]; + assign booth_block8_mand22 = b_registered[22:21]; + assign booth_block8_mand23 = b_registered[23:22]; + assign booth_block8_mand24 = b_registered[24:23]; + assign booth_block8_mand25 = b_registered[25:24]; + assign booth_block8_mand26 = b_registered[26:25]; + assign booth_block8_mand27 = b_registered[27:26]; + assign booth_block8_mand28 = b_registered[28:27]; + assign booth_block8_mand29 = b_registered[29:28]; + assign booth_block8_mand30 = b_registered[30:29]; + assign booth_block8_mand31 = b_registered[31:30]; + assign booth_block8_mand32 = { 1'h0, b_registered[31] }; + assign booth_block10 = a_registered[11:9]; + assign booth_block10_sel = { \sel_1$1514 , \sel_0$1513 }; + assign booth_block10_mand0 = { b_registered[0], 1'h0 }; + assign booth_block10_mand1 = b_registered[1:0]; + assign booth_block10_mand2 = b_registered[2:1]; + assign booth_block10_mand3 = b_registered[3:2]; + assign booth_block10_mand4 = b_registered[4:3]; + assign booth_block10_mand5 = b_registered[5:4]; + assign booth_block10_mand6 = b_registered[6:5]; + assign booth_block10_mand7 = b_registered[7:6]; + assign booth_block10_mand8 = b_registered[8:7]; + assign booth_block10_mand9 = b_registered[9:8]; + assign booth_block10_mand10 = b_registered[10:9]; + assign booth_block10_mand11 = b_registered[11:10]; + assign booth_block10_mand12 = b_registered[12:11]; + assign booth_block10_mand13 = b_registered[13:12]; + assign booth_block10_mand14 = b_registered[14:13]; + assign booth_block10_mand15 = b_registered[15:14]; + assign booth_block10_mand16 = b_registered[16:15]; + assign booth_block10_mand17 = b_registered[17:16]; + assign booth_block10_mand18 = b_registered[18:17]; + assign booth_block10_mand19 = b_registered[19:18]; + assign booth_block10_mand20 = b_registered[20:19]; + assign booth_block10_mand21 = b_registered[21:20]; + assign booth_block10_mand22 = b_registered[22:21]; + assign booth_block10_mand23 = b_registered[23:22]; + assign booth_block10_mand24 = b_registered[24:23]; + assign booth_block10_mand25 = b_registered[25:24]; + assign booth_block10_mand26 = b_registered[26:25]; + assign booth_block10_mand27 = b_registered[27:26]; + assign booth_block10_mand28 = b_registered[28:27]; + assign booth_block10_mand29 = b_registered[29:28]; + assign booth_block10_mand30 = b_registered[30:29]; + assign booth_block10_mand31 = b_registered[31:30]; + assign booth_block10_mand32 = { 1'h0, b_registered[31] }; + assign booth_block12 = a_registered[13:11]; + assign booth_block12_sel = { \sel_1$1551 , \sel_0$1550 }; + assign booth_block12_mand0 = { b_registered[0], 1'h0 }; + assign booth_block12_mand1 = b_registered[1:0]; + assign booth_block12_mand2 = b_registered[2:1]; + assign booth_block12_mand3 = b_registered[3:2]; + assign booth_block12_mand4 = b_registered[4:3]; + assign booth_block12_mand5 = b_registered[5:4]; + assign booth_block12_mand6 = b_registered[6:5]; + assign booth_block12_mand7 = b_registered[7:6]; + assign booth_block12_mand8 = b_registered[8:7]; + assign booth_block12_mand9 = b_registered[9:8]; + assign booth_block12_mand10 = b_registered[10:9]; + assign booth_block12_mand11 = b_registered[11:10]; + assign booth_block12_mand12 = b_registered[12:11]; + assign booth_block12_mand13 = b_registered[13:12]; + assign booth_block12_mand14 = b_registered[14:13]; + assign booth_block12_mand15 = b_registered[15:14]; + assign booth_block12_mand16 = b_registered[16:15]; + assign booth_block12_mand17 = b_registered[17:16]; + assign booth_block12_mand18 = b_registered[18:17]; + assign booth_block12_mand19 = b_registered[19:18]; + assign booth_block12_mand20 = b_registered[20:19]; + assign booth_block12_mand21 = b_registered[21:20]; + assign booth_block12_mand22 = b_registered[22:21]; + assign booth_block12_mand23 = b_registered[23:22]; + assign booth_block12_mand24 = b_registered[24:23]; + assign booth_block12_mand25 = b_registered[25:24]; + assign booth_block12_mand26 = b_registered[26:25]; + assign booth_block12_mand27 = b_registered[27:26]; + assign booth_block12_mand28 = b_registered[28:27]; + assign booth_block12_mand29 = b_registered[29:28]; + assign booth_block12_mand30 = b_registered[30:29]; + assign booth_block12_mand31 = b_registered[31:30]; + assign booth_block12_mand32 = { 1'h0, b_registered[31] }; + assign booth_block14 = a_registered[15:13]; + assign booth_block14_sel = { \sel_1$1588 , \sel_0$1587 }; + assign booth_block14_mand0 = { b_registered[0], 1'h0 }; + assign booth_block14_mand1 = b_registered[1:0]; + assign booth_block14_mand2 = b_registered[2:1]; + assign booth_block14_mand3 = b_registered[3:2]; + assign booth_block14_mand4 = b_registered[4:3]; + assign booth_block14_mand5 = b_registered[5:4]; + assign booth_block14_mand6 = b_registered[6:5]; + assign booth_block14_mand7 = b_registered[7:6]; + assign booth_block14_mand8 = b_registered[8:7]; + assign booth_block14_mand9 = b_registered[9:8]; + assign booth_block14_mand10 = b_registered[10:9]; + assign booth_block14_mand11 = b_registered[11:10]; + assign booth_block14_mand12 = b_registered[12:11]; + assign booth_block14_mand13 = b_registered[13:12]; + assign booth_block14_mand14 = b_registered[14:13]; + assign booth_block14_mand15 = b_registered[15:14]; + assign booth_block14_mand16 = b_registered[16:15]; + assign booth_block14_mand17 = b_registered[17:16]; + assign booth_block14_mand18 = b_registered[18:17]; + assign booth_block14_mand19 = b_registered[19:18]; + assign booth_block14_mand20 = b_registered[20:19]; + assign booth_block14_mand21 = b_registered[21:20]; + assign booth_block14_mand22 = b_registered[22:21]; + assign booth_block14_mand23 = b_registered[23:22]; + assign booth_block14_mand24 = b_registered[24:23]; + assign booth_block14_mand25 = b_registered[25:24]; + assign booth_block14_mand26 = b_registered[26:25]; + assign booth_block14_mand27 = b_registered[27:26]; + assign booth_block14_mand28 = b_registered[28:27]; + assign booth_block14_mand29 = b_registered[29:28]; + assign booth_block14_mand30 = b_registered[30:29]; + assign booth_block14_mand31 = b_registered[31:30]; + assign booth_block14_mand32 = { 1'h0, b_registered[31] }; + assign booth_block16 = a_registered[17:15]; + assign booth_block16_sel = { \sel_1$1625 , \sel_0$1624 }; + assign booth_block16_mand0 = { b_registered[0], 1'h0 }; + assign booth_block16_mand1 = b_registered[1:0]; + assign booth_block16_mand2 = b_registered[2:1]; + assign booth_block16_mand3 = b_registered[3:2]; + assign booth_block16_mand4 = b_registered[4:3]; + assign booth_block16_mand5 = b_registered[5:4]; + assign booth_block16_mand6 = b_registered[6:5]; + assign booth_block16_mand7 = b_registered[7:6]; + assign booth_block16_mand8 = b_registered[8:7]; + assign booth_block16_mand9 = b_registered[9:8]; + assign booth_block16_mand10 = b_registered[10:9]; + assign booth_block16_mand11 = b_registered[11:10]; + assign booth_block16_mand12 = b_registered[12:11]; + assign booth_block16_mand13 = b_registered[13:12]; + assign booth_block16_mand14 = b_registered[14:13]; + assign booth_block16_mand15 = b_registered[15:14]; + assign booth_block16_mand16 = b_registered[16:15]; + assign booth_block16_mand17 = b_registered[17:16]; + assign booth_block16_mand18 = b_registered[18:17]; + assign booth_block16_mand19 = b_registered[19:18]; + assign booth_block16_mand20 = b_registered[20:19]; + assign booth_block16_mand21 = b_registered[21:20]; + assign booth_block16_mand22 = b_registered[22:21]; + assign booth_block16_mand23 = b_registered[23:22]; + assign booth_block16_mand24 = b_registered[24:23]; + assign booth_block16_mand25 = b_registered[25:24]; + assign booth_block16_mand26 = b_registered[26:25]; + assign booth_block16_mand27 = b_registered[27:26]; + assign booth_block16_mand28 = b_registered[28:27]; + assign booth_block16_mand29 = b_registered[29:28]; + assign booth_block16_mand30 = b_registered[30:29]; + assign booth_block16_mand31 = b_registered[31:30]; + assign booth_block16_mand32 = { 1'h0, b_registered[31] }; + assign booth_block18 = a_registered[19:17]; + assign booth_block18_sel = { \sel_1$1662 , \sel_0$1661 }; + assign booth_block18_mand0 = { b_registered[0], 1'h0 }; + assign booth_block18_mand1 = b_registered[1:0]; + assign booth_block18_mand2 = b_registered[2:1]; + assign booth_block18_mand3 = b_registered[3:2]; + assign booth_block18_mand4 = b_registered[4:3]; + assign booth_block18_mand5 = b_registered[5:4]; + assign booth_block18_mand6 = b_registered[6:5]; + assign booth_block18_mand7 = b_registered[7:6]; + assign booth_block18_mand8 = b_registered[8:7]; + assign booth_block18_mand9 = b_registered[9:8]; + assign booth_block18_mand10 = b_registered[10:9]; + assign booth_block18_mand11 = b_registered[11:10]; + assign booth_block18_mand12 = b_registered[12:11]; + assign booth_block18_mand13 = b_registered[13:12]; + assign booth_block18_mand14 = b_registered[14:13]; + assign booth_block18_mand15 = b_registered[15:14]; + assign booth_block18_mand16 = b_registered[16:15]; + assign booth_block18_mand17 = b_registered[17:16]; + assign booth_block18_mand18 = b_registered[18:17]; + assign booth_block18_mand19 = b_registered[19:18]; + assign booth_block18_mand20 = b_registered[20:19]; + assign booth_block18_mand21 = b_registered[21:20]; + assign booth_block18_mand22 = b_registered[22:21]; + assign booth_block18_mand23 = b_registered[23:22]; + assign booth_block18_mand24 = b_registered[24:23]; + assign booth_block18_mand25 = b_registered[25:24]; + assign booth_block18_mand26 = b_registered[26:25]; + assign booth_block18_mand27 = b_registered[27:26]; + assign booth_block18_mand28 = b_registered[28:27]; + assign booth_block18_mand29 = b_registered[29:28]; + assign booth_block18_mand30 = b_registered[30:29]; + assign booth_block18_mand31 = b_registered[31:30]; + assign booth_block18_mand32 = { 1'h0, b_registered[31] }; + assign booth_block20 = a_registered[21:19]; + assign booth_block20_sel = { \sel_1$1699 , \sel_0$1698 }; + assign booth_block20_mand0 = { b_registered[0], 1'h0 }; + assign booth_block20_mand1 = b_registered[1:0]; + assign booth_block20_mand2 = b_registered[2:1]; + assign booth_block20_mand3 = b_registered[3:2]; + assign booth_block20_mand4 = b_registered[4:3]; + assign booth_block20_mand5 = b_registered[5:4]; + assign booth_block20_mand6 = b_registered[6:5]; + assign booth_block20_mand7 = b_registered[7:6]; + assign booth_block20_mand8 = b_registered[8:7]; + assign booth_block20_mand9 = b_registered[9:8]; + assign booth_block20_mand10 = b_registered[10:9]; + assign booth_block20_mand11 = b_registered[11:10]; + assign booth_block20_mand12 = b_registered[12:11]; + assign booth_block20_mand13 = b_registered[13:12]; + assign booth_block20_mand14 = b_registered[14:13]; + assign booth_block20_mand15 = b_registered[15:14]; + assign booth_block20_mand16 = b_registered[16:15]; + assign booth_block20_mand17 = b_registered[17:16]; + assign booth_block20_mand18 = b_registered[18:17]; + assign booth_block20_mand19 = b_registered[19:18]; + assign booth_block20_mand20 = b_registered[20:19]; + assign booth_block20_mand21 = b_registered[21:20]; + assign booth_block20_mand22 = b_registered[22:21]; + assign booth_block20_mand23 = b_registered[23:22]; + assign booth_block20_mand24 = b_registered[24:23]; + assign booth_block20_mand25 = b_registered[25:24]; + assign booth_block20_mand26 = b_registered[26:25]; + assign booth_block20_mand27 = b_registered[27:26]; + assign booth_block20_mand28 = b_registered[28:27]; + assign booth_block20_mand29 = b_registered[29:28]; + assign booth_block20_mand30 = b_registered[30:29]; + assign booth_block20_mand31 = b_registered[31:30]; + assign booth_block20_mand32 = { 1'h0, b_registered[31] }; + assign booth_block22 = a_registered[23:21]; + assign booth_block22_sel = { \sel_1$1736 , \sel_0$1735 }; + assign booth_block22_mand0 = { b_registered[0], 1'h0 }; + assign booth_block22_mand1 = b_registered[1:0]; + assign booth_block22_mand2 = b_registered[2:1]; + assign booth_block22_mand3 = b_registered[3:2]; + assign booth_block22_mand4 = b_registered[4:3]; + assign booth_block22_mand5 = b_registered[5:4]; + assign booth_block22_mand6 = b_registered[6:5]; + assign booth_block22_mand7 = b_registered[7:6]; + assign booth_block22_mand8 = b_registered[8:7]; + assign booth_block22_mand9 = b_registered[9:8]; + assign booth_block22_mand10 = b_registered[10:9]; + assign booth_block22_mand11 = b_registered[11:10]; + assign booth_block22_mand12 = b_registered[12:11]; + assign booth_block22_mand13 = b_registered[13:12]; + assign booth_block22_mand14 = b_registered[14:13]; + assign booth_block22_mand15 = b_registered[15:14]; + assign booth_block22_mand16 = b_registered[16:15]; + assign booth_block22_mand17 = b_registered[17:16]; + assign booth_block22_mand18 = b_registered[18:17]; + assign booth_block22_mand19 = b_registered[19:18]; + assign booth_block22_mand20 = b_registered[20:19]; + assign booth_block22_mand21 = b_registered[21:20]; + assign booth_block22_mand22 = b_registered[22:21]; + assign booth_block22_mand23 = b_registered[23:22]; + assign booth_block22_mand24 = b_registered[24:23]; + assign booth_block22_mand25 = b_registered[25:24]; + assign booth_block22_mand26 = b_registered[26:25]; + assign booth_block22_mand27 = b_registered[27:26]; + assign booth_block22_mand28 = b_registered[28:27]; + assign booth_block22_mand29 = b_registered[29:28]; + assign booth_block22_mand30 = b_registered[30:29]; + assign booth_block22_mand31 = b_registered[31:30]; + assign booth_block22_mand32 = { 1'h0, b_registered[31] }; + assign booth_block24 = a_registered[25:23]; + assign booth_block24_sel = { \sel_1$1773 , \sel_0$1772 }; + assign booth_block24_mand0 = { b_registered[0], 1'h0 }; + assign booth_block24_mand1 = b_registered[1:0]; + assign booth_block24_mand2 = b_registered[2:1]; + assign booth_block24_mand3 = b_registered[3:2]; + assign booth_block24_mand4 = b_registered[4:3]; + assign booth_block24_mand5 = b_registered[5:4]; + assign booth_block24_mand6 = b_registered[6:5]; + assign booth_block24_mand7 = b_registered[7:6]; + assign booth_block24_mand8 = b_registered[8:7]; + assign booth_block24_mand9 = b_registered[9:8]; + assign booth_block24_mand10 = b_registered[10:9]; + assign booth_block24_mand11 = b_registered[11:10]; + assign booth_block24_mand12 = b_registered[12:11]; + assign booth_block24_mand13 = b_registered[13:12]; + assign booth_block24_mand14 = b_registered[14:13]; + assign booth_block24_mand15 = b_registered[15:14]; + assign booth_block24_mand16 = b_registered[16:15]; + assign booth_block24_mand17 = b_registered[17:16]; + assign booth_block24_mand18 = b_registered[18:17]; + assign booth_block24_mand19 = b_registered[19:18]; + assign booth_block24_mand20 = b_registered[20:19]; + assign booth_block24_mand21 = b_registered[21:20]; + assign booth_block24_mand22 = b_registered[22:21]; + assign booth_block24_mand23 = b_registered[23:22]; + assign booth_block24_mand24 = b_registered[24:23]; + assign booth_block24_mand25 = b_registered[25:24]; + assign booth_block24_mand26 = b_registered[26:25]; + assign booth_block24_mand27 = b_registered[27:26]; + assign booth_block24_mand28 = b_registered[28:27]; + assign booth_block24_mand29 = b_registered[29:28]; + assign booth_block24_mand30 = b_registered[30:29]; + assign booth_block24_mand31 = b_registered[31:30]; + assign booth_block24_mand32 = { 1'h0, b_registered[31] }; + assign booth_block26 = a_registered[27:25]; + assign booth_block26_sel = { \sel_1$1810 , \sel_0$1809 }; + assign booth_block26_mand0 = { b_registered[0], 1'h0 }; + assign booth_block26_mand1 = b_registered[1:0]; + assign booth_block26_mand2 = b_registered[2:1]; + assign booth_block26_mand3 = b_registered[3:2]; + assign booth_block26_mand4 = b_registered[4:3]; + assign booth_block26_mand5 = b_registered[5:4]; + assign booth_block26_mand6 = b_registered[6:5]; + assign booth_block26_mand7 = b_registered[7:6]; + assign booth_block26_mand8 = b_registered[8:7]; + assign booth_block26_mand9 = b_registered[9:8]; + assign booth_block26_mand10 = b_registered[10:9]; + assign booth_block26_mand11 = b_registered[11:10]; + assign booth_block26_mand12 = b_registered[12:11]; + assign booth_block26_mand13 = b_registered[13:12]; + assign booth_block26_mand14 = b_registered[14:13]; + assign booth_block26_mand15 = b_registered[15:14]; + assign booth_block26_mand16 = b_registered[16:15]; + assign booth_block26_mand17 = b_registered[17:16]; + assign booth_block26_mand18 = b_registered[18:17]; + assign booth_block26_mand19 = b_registered[19:18]; + assign booth_block26_mand20 = b_registered[20:19]; + assign booth_block26_mand21 = b_registered[21:20]; + assign booth_block26_mand22 = b_registered[22:21]; + assign booth_block26_mand23 = b_registered[23:22]; + assign booth_block26_mand24 = b_registered[24:23]; + assign booth_block26_mand25 = b_registered[25:24]; + assign booth_block26_mand26 = b_registered[26:25]; + assign booth_block26_mand27 = b_registered[27:26]; + assign booth_block26_mand28 = b_registered[28:27]; + assign booth_block26_mand29 = b_registered[29:28]; + assign booth_block26_mand30 = b_registered[30:29]; + assign booth_block26_mand31 = b_registered[31:30]; + assign booth_block26_mand32 = { 1'h0, b_registered[31] }; + assign booth_block28 = a_registered[29:27]; + assign booth_block28_sel = { \sel_1$1847 , \sel_0$1846 }; + assign booth_block28_mand0 = { b_registered[0], 1'h0 }; + assign booth_block28_mand1 = b_registered[1:0]; + assign booth_block28_mand2 = b_registered[2:1]; + assign booth_block28_mand3 = b_registered[3:2]; + assign booth_block28_mand4 = b_registered[4:3]; + assign booth_block28_mand5 = b_registered[5:4]; + assign booth_block28_mand6 = b_registered[6:5]; + assign booth_block28_mand7 = b_registered[7:6]; + assign booth_block28_mand8 = b_registered[8:7]; + assign booth_block28_mand9 = b_registered[9:8]; + assign booth_block28_mand10 = b_registered[10:9]; + assign booth_block28_mand11 = b_registered[11:10]; + assign booth_block28_mand12 = b_registered[12:11]; + assign booth_block28_mand13 = b_registered[13:12]; + assign booth_block28_mand14 = b_registered[14:13]; + assign booth_block28_mand15 = b_registered[15:14]; + assign booth_block28_mand16 = b_registered[16:15]; + assign booth_block28_mand17 = b_registered[17:16]; + assign booth_block28_mand18 = b_registered[18:17]; + assign booth_block28_mand19 = b_registered[19:18]; + assign booth_block28_mand20 = b_registered[20:19]; + assign booth_block28_mand21 = b_registered[21:20]; + assign booth_block28_mand22 = b_registered[22:21]; + assign booth_block28_mand23 = b_registered[23:22]; + assign booth_block28_mand24 = b_registered[24:23]; + assign booth_block28_mand25 = b_registered[25:24]; + assign booth_block28_mand26 = b_registered[26:25]; + assign booth_block28_mand27 = b_registered[27:26]; + assign booth_block28_mand28 = b_registered[28:27]; + assign booth_block28_mand29 = b_registered[29:28]; + assign booth_block28_mand30 = b_registered[30:29]; + assign booth_block28_mand31 = b_registered[31:30]; + assign booth_block28_mand32 = { 1'h0, b_registered[31] }; + assign booth_block30 = a_registered[31:29]; + assign booth_block30_sel = { \sel_1$1884 , \sel_0$1883 }; + assign booth_block30_mand0 = { b_registered[0], 1'h0 }; + assign booth_block30_mand1 = b_registered[1:0]; + assign booth_block30_mand2 = b_registered[2:1]; + assign booth_block30_mand3 = b_registered[3:2]; + assign booth_block30_mand4 = b_registered[4:3]; + assign booth_block30_mand5 = b_registered[5:4]; + assign booth_block30_mand6 = b_registered[6:5]; + assign booth_block30_mand7 = b_registered[7:6]; + assign booth_block30_mand8 = b_registered[8:7]; + assign booth_block30_mand9 = b_registered[9:8]; + assign booth_block30_mand10 = b_registered[10:9]; + assign booth_block30_mand11 = b_registered[11:10]; + assign booth_block30_mand12 = b_registered[12:11]; + assign booth_block30_mand13 = b_registered[13:12]; + assign booth_block30_mand14 = b_registered[14:13]; + assign booth_block30_mand15 = b_registered[15:14]; + assign booth_block30_mand16 = b_registered[16:15]; + assign booth_block30_mand17 = b_registered[17:16]; + assign booth_block30_mand18 = b_registered[18:17]; + assign booth_block30_mand19 = b_registered[19:18]; + assign booth_block30_mand20 = b_registered[20:19]; + assign booth_block30_mand21 = b_registered[21:20]; + assign booth_block30_mand22 = b_registered[22:21]; + assign booth_block30_mand23 = b_registered[23:22]; + assign booth_block30_mand24 = b_registered[24:23]; + assign booth_block30_mand25 = b_registered[25:24]; + assign booth_block30_mand26 = b_registered[26:25]; + assign booth_block30_mand27 = b_registered[27:26]; + assign booth_block30_mand28 = b_registered[28:27]; + assign booth_block30_mand29 = b_registered[29:28]; + assign booth_block30_mand30 = b_registered[30:29]; + assign booth_block30_mand31 = b_registered[31:30]; + assign booth_block30_mand32 = { 1'h0, b_registered[31] }; + assign booth_block32 = { 2'h0, a_registered[31] }; + assign booth_block32_sign = 1'h0; + assign booth_block32_sel = { \sel_1$1922 , \sel_0$1921 }; + assign booth_block32_mand0 = { b_registered[0], 1'h0 }; + assign booth_block32_mand1 = b_registered[1:0]; + assign booth_block32_mand2 = b_registered[2:1]; + assign booth_block32_mand3 = b_registered[3:2]; + assign booth_block32_mand4 = b_registered[4:3]; + assign booth_block32_mand5 = b_registered[5:4]; + assign booth_block32_mand6 = b_registered[6:5]; + assign booth_block32_mand7 = b_registered[7:6]; + assign booth_block32_mand8 = b_registered[8:7]; + assign booth_block32_mand9 = b_registered[9:8]; + assign booth_block32_mand10 = b_registered[10:9]; + assign booth_block32_mand11 = b_registered[11:10]; + assign booth_block32_mand12 = b_registered[12:11]; + assign booth_block32_mand13 = b_registered[13:12]; + assign booth_block32_mand14 = b_registered[14:13]; + assign booth_block32_mand15 = b_registered[15:14]; + assign booth_block32_mand16 = b_registered[16:15]; + assign booth_block32_mand17 = b_registered[17:16]; + assign booth_block32_mand18 = b_registered[18:17]; + assign booth_block32_mand19 = b_registered[19:18]; + assign booth_block32_mand20 = b_registered[20:19]; + assign booth_block32_mand21 = b_registered[21:20]; + assign booth_block32_mand22 = b_registered[22:21]; + assign booth_block32_mand23 = b_registered[23:22]; + assign booth_block32_mand24 = b_registered[24:23]; + assign booth_block32_mand25 = b_registered[25:24]; + assign booth_block32_mand26 = b_registered[26:25]; + assign booth_block32_mand27 = b_registered[27:26]; + assign booth_block32_mand28 = b_registered[28:27]; + assign booth_block32_mand29 = b_registered[29:28]; + assign booth_block32_mand30 = b_registered[30:29]; + assign booth_block32_mand31 = b_registered[31:30]; + assign booth_block32_mand32 = { 1'h0, b_registered[31] }; + assign pp_row36_0 = 1'h1; + assign pp_row38_0 = 1'h1; + assign pp_row40_0 = 1'h1; + assign pp_row42_0 = 1'h1; + assign pp_row44_0 = 1'h1; + assign pp_row46_0 = 1'h1; + assign pp_row48_0 = 1'h1; + assign pp_row50_0 = 1'h1; + assign pp_row52_0 = 1'h1; + assign pp_row54_0 = 1'h1; + assign pp_row56_0 = 1'h1; + assign pp_row58_0 = 1'h1; + assign pp_row60_0 = 1'h1; + assign pp_row62_0 = 1'h1; + assign pp_row64_0 = 1'h1; + assign \a$1971 = final_a_registered; + assign \b$1972 = final_b_registered; + assign \o$1973 = { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + assign notblock = { \$3 , \$2 , \$1 }; + assign \notblock$2008 = { \$6 , \$5 , \$4 }; + assign \notblock$2042 = { \$9 , \$8 , \$7 }; + assign \notblock$2076 = { \$12 , \$11 , \$10 }; + assign \notblock$2110 = { \$15 , \$14 , \$13 }; + assign \notblock$2144 = { \$18 , \$17 , \$16 }; + assign \notblock$2178 = { \$21 , \$20 , \$19 }; + assign \notblock$2212 = { \$24 , \$23 , \$22 }; + assign \notblock$2246 = { \$27 , \$26 , \$25 }; + assign \notblock$2280 = { \$30 , \$29 , \$28 }; + assign \notblock$2314 = { \$33 , \$32 , \$31 }; + assign \notblock$2348 = { \$36 , \$35 , \$34 }; + assign \notblock$2382 = { \$39 , \$38 , \$37 }; + assign \notblock$2416 = { \$42 , \$41 , \$40 }; + assign \notblock$2450 = { \$45 , \$44 , \$43 }; + assign \notblock$2484 = { \$48 , \$47 , \$46 }; + assign \notblock$2518 = { \$51 , \$50 , \$49 }; +endmodule + +module \multiplier.final_adder (\port$902$0 , \port$903$0 , \port$904$0 , \port$905$0 , \port$906$0 , \port$907$0 , \port$908$0 , \port$909$0 , \port$910$0 , \port$911$0 , \port$912$0 , \port$913$0 , \port$914$0 , \port$915$0 , \port$916$0 , \port$917$0 , \port$918$0 , \port$919$0 , \port$920$0 , \port$921$0 , \port$922$0 +, \port$923$0 , \port$924$0 , \port$925$0 , \port$926$0 , \port$927$0 , \port$928$0 , \port$929$0 , \port$930$0 , \port$931$0 , \port$932$0 , \port$933$0 , \port$934$0 , \port$935$0 , \port$936$0 , \port$937$0 , \port$938$0 , \port$939$0 , \port$940$0 , \port$941$0 , \port$942$0 , \port$943$0 +, \port$944$0 , \port$945$0 , \port$946$0 , \port$947$0 , \port$948$0 , \port$949$0 , \port$950$0 , \port$951$0 , \port$952$0 , \port$953$0 , \port$954$0 , \port$955$0 , \port$956$0 , \port$957$0 , \port$958$0 , \port$959$0 , \port$960$0 , \port$961$0 , \port$962$0 , \port$963$0 , \port$964$0 +, a, b, \port$901$0 ); + wire \$1 ; + wire \$10 ; + wire \$11 ; + wire \$12 ; + wire \$13 ; + wire \$14 ; + wire \$15 ; + wire \$16 ; + wire \$17 ; + wire \$18 ; + wire \$19 ; + wire \$2 ; + wire \$20 ; + wire \$21 ; + wire \$22 ; + wire \$23 ; + wire \$24 ; + wire \$25 ; + wire \$26 ; + wire \$27 ; + wire \$28 ; + wire \$29 ; + wire \$3 ; + wire \$30 ; + wire \$31 ; + wire \$32 ; + wire \$33 ; + wire \$34 ; + wire \$35 ; + wire \$36 ; + wire \$37 ; + wire \$38 ; + wire \$39 ; + wire \$4 ; + wire \$40 ; + wire \$41 ; + wire \$42 ; + wire \$43 ; + wire \$44 ; + wire \$45 ; + wire \$46 ; + wire \$47 ; + wire \$48 ; + wire \$49 ; + wire \$5 ; + wire \$50 ; + wire \$51 ; + wire \$52 ; + wire \$53 ; + wire \$54 ; + wire \$55 ; + wire \$56 ; + wire \$57 ; + wire \$58 ; + wire \$59 ; + wire \$6 ; + wire \$60 ; + wire \$61 ; + wire \$62 ; + wire \$63 ; + wire \$64 ; + wire \$65 ; + wire \$66 ; + wire \$7 ; + wire \$8 ; + wire \$9 ; + wire \$signal ; + wire \$signal$10 ; + wire \$signal$100 ; + wire \$signal$101 ; + wire \$signal$102 ; + wire \$signal$103 ; + wire \$signal$104 ; + wire \$signal$105 ; + wire \$signal$106 ; + wire \$signal$107 ; + wire \$signal$108 ; + wire \$signal$109 ; + wire \$signal$11 ; + wire \$signal$110 ; + wire \$signal$111 ; + wire \$signal$112 ; + wire \$signal$113 ; + wire \$signal$114 ; + wire \$signal$115 ; + wire \$signal$116 ; + wire \$signal$117 ; + wire \$signal$118 ; + wire \$signal$119 ; + wire \$signal$12 ; + wire \$signal$120 ; + wire \$signal$121 ; + wire \$signal$122 ; + wire \$signal$123 ; + wire \$signal$124 ; + wire \$signal$125 ; + wire \$signal$126 ; + wire \$signal$127 ; + wire \$signal$128 ; + wire \$signal$129 ; + wire \$signal$13 ; + wire \$signal$130 ; + wire \$signal$131 ; + wire \$signal$14 ; + wire \$signal$15 ; + wire \$signal$16 ; + wire \$signal$17 ; + wire \$signal$18 ; + wire \$signal$19 ; + wire \$signal$20 ; + wire \$signal$21 ; + wire \$signal$22 ; + wire \$signal$23 ; + wire \$signal$24 ; + wire \$signal$25 ; + wire \$signal$26 ; + wire \$signal$263 ; + wire \$signal$264 ; + wire \$signal$265 ; + wire \$signal$266 ; + wire \$signal$267 ; + wire \$signal$268 ; + wire \$signal$269 ; + wire \$signal$27 ; + wire \$signal$270 ; + wire \$signal$271 ; + wire \$signal$272 ; + wire \$signal$273 ; + wire \$signal$274 ; + wire \$signal$275 ; + wire \$signal$276 ; + wire \$signal$277 ; + wire \$signal$278 ; + wire \$signal$279 ; + wire \$signal$28 ; + wire \$signal$280 ; + wire \$signal$281 ; + wire \$signal$282 ; + wire \$signal$283 ; + wire \$signal$284 ; + wire \$signal$285 ; + wire \$signal$286 ; + wire \$signal$287 ; + wire \$signal$288 ; + wire \$signal$289 ; + wire \$signal$29 ; + wire \$signal$290 ; + wire \$signal$291 ; + wire \$signal$292 ; + wire \$signal$293 ; + wire \$signal$294 ; + wire \$signal$295 ; + wire \$signal$296 ; + wire \$signal$297 ; + wire \$signal$298 ; + wire \$signal$299 ; + wire \$signal$30 ; + wire \$signal$300 ; + wire \$signal$301 ; + wire \$signal$302 ; + wire \$signal$303 ; + wire \$signal$304 ; + wire \$signal$305 ; + wire \$signal$306 ; + wire \$signal$307 ; + wire \$signal$308 ; + wire \$signal$309 ; + wire \$signal$31 ; + wire \$signal$310 ; + wire \$signal$311 ; + wire \$signal$312 ; + wire \$signal$313 ; + wire \$signal$314 ; + wire \$signal$315 ; + wire \$signal$316 ; + wire \$signal$317 ; + wire \$signal$318 ; + wire \$signal$319 ; + wire \$signal$32 ; + wire \$signal$320 ; + wire \$signal$321 ; + wire \$signal$322 ; + wire \$signal$323 ; + wire \$signal$324 ; + wire \$signal$325 ; + wire \$signal$326 ; + wire \$signal$33 ; + wire \$signal$34 ; + wire \$signal$35 ; + wire \$signal$36 ; + wire \$signal$37 ; + wire \$signal$38 ; + wire \$signal$39 ; + wire \$signal$40 ; + wire \$signal$41 ; + wire \$signal$42 ; + wire \$signal$43 ; + wire \$signal$44 ; + wire \$signal$45 ; + wire \$signal$46 ; + wire \$signal$47 ; + wire \$signal$48 ; + wire \$signal$49 ; + wire \$signal$5 ; + wire \$signal$50 ; + wire \$signal$51 ; + wire \$signal$52 ; + wire \$signal$53 ; + wire \$signal$54 ; + wire \$signal$55 ; + wire \$signal$56 ; + wire \$signal$57 ; + wire \$signal$58 ; + wire \$signal$59 ; + wire \$signal$6 ; + wire \$signal$60 ; + wire \$signal$61 ; + wire \$signal$62 ; + wire \$signal$63 ; + wire \$signal$64 ; + wire \$signal$65 ; + wire \$signal$66 ; + wire \$signal$67 ; + wire \$signal$68 ; + wire \$signal$69 ; + wire \$signal$7 ; + wire \$signal$70 ; + wire \$signal$71 ; + wire \$signal$72 ; + wire \$signal$73 ; + wire \$signal$74 ; + wire \$signal$75 ; + wire \$signal$76 ; + wire \$signal$77 ; + wire \$signal$78 ; + wire \$signal$79 ; + wire \$signal$8 ; + wire \$signal$80 ; + wire \$signal$81 ; + wire \$signal$82 ; + wire \$signal$83 ; + wire \$signal$84 ; + wire \$signal$85 ; + wire \$signal$86 ; + wire \$signal$87 ; + wire \$signal$88 ; + wire \$signal$89 ; + wire \$signal$9 ; + wire \$signal$90 ; + wire \$signal$91 ; + wire \$signal$92 ; + wire \$signal$93 ; + wire \$signal$94 ; + wire \$signal$95 ; + wire \$signal$96 ; + wire \$signal$97 ; + wire \$signal$98 ; + wire \$signal$99 ; + input [63:0] a; + wire [63:0] a; + wire [63:0] \a$1 ; + input [63:0] b; + wire [63:0] b; + wire [63:0] \b$3 ; + wire con; + wire \con$137 ; + wire \con$139 ; + wire \con$141 ; + wire \con$143 ; + wire \con$145 ; + wire \con$147 ; + wire \con$149 ; + wire \con$151 ; + wire \con$153 ; + wire \con$155 ; + wire \con$157 ; + wire \con$159 ; + wire \con$161 ; + wire \con$163 ; + wire \con$165 ; + wire \con$167 ; + wire \con$169 ; + wire \con$171 ; + wire \con$173 ; + wire \con$175 ; + wire \con$177 ; + wire \con$179 ; + wire \con$181 ; + wire \con$183 ; + wire \con$185 ; + wire \con$187 ; + wire \con$189 ; + wire \con$191 ; + wire \con$193 ; + wire \con$195 ; + wire \con$197 ; + wire \con$199 ; + wire \con$201 ; + wire \con$203 ; + wire \con$205 ; + wire \con$207 ; + wire \con$209 ; + wire \con$211 ; + wire \con$213 ; + wire \con$215 ; + wire \con$217 ; + wire \con$219 ; + wire \con$221 ; + wire \con$223 ; + wire \con$225 ; + wire \con$227 ; + wire \con$229 ; + wire \con$231 ; + wire \con$233 ; + wire \con$235 ; + wire \con$237 ; + wire \con$239 ; + wire \con$241 ; + wire \con$243 ; + wire \con$245 ; + wire \con$247 ; + wire \con$249 ; + wire \con$251 ; + wire \con$253 ; + wire \con$255 ; + wire \con$257 ; + wire \con$259 ; + wire \con$261 ; + wire g_new; + wire \g_new$330 ; + wire \g_new$333 ; + wire \g_new$334 ; + wire \g_new$337 ; + wire \g_new$338 ; + wire \g_new$341 ; + wire \g_new$342 ; + wire \g_new$345 ; + wire \g_new$346 ; + wire \g_new$349 ; + wire \g_new$350 ; + wire \g_new$353 ; + wire \g_new$354 ; + wire \g_new$357 ; + wire \g_new$358 ; + wire \g_new$361 ; + wire \g_new$362 ; + wire \g_new$365 ; + wire \g_new$366 ; + wire \g_new$369 ; + wire \g_new$370 ; + wire \g_new$373 ; + wire \g_new$374 ; + wire \g_new$377 ; + wire \g_new$378 ; + wire \g_new$381 ; + wire \g_new$382 ; + wire \g_new$385 ; + wire \g_new$386 ; + wire \g_new$389 ; + wire \g_new$390 ; + wire \g_new$393 ; + wire \g_new$394 ; + wire \g_new$397 ; + wire \g_new$398 ; + wire \g_new$401 ; + wire \g_new$402 ; + wire \g_new$405 ; + wire \g_new$406 ; + wire \g_new$409 ; + wire \g_new$410 ; + wire \g_new$413 ; + wire \g_new$414 ; + wire \g_new$417 ; + wire \g_new$418 ; + wire \g_new$421 ; + wire \g_new$422 ; + wire \g_new$425 ; + wire \g_new$426 ; + wire \g_new$429 ; + wire \g_new$430 ; + wire \g_new$433 ; + wire \g_new$434 ; + wire \g_new$437 ; + wire \g_new$438 ; + wire \g_new$441 ; + wire \g_new$442 ; + wire \g_new$445 ; + wire \g_new$446 ; + wire \g_new$449 ; + wire \g_new$450 ; + wire \g_new$451 ; + wire \g_new$452 ; + wire \g_new$453 ; + wire \g_new$454 ; + wire \g_new$455 ; + wire \g_new$456 ; + wire \g_new$457 ; + wire \g_new$458 ; + wire \g_new$459 ; + wire \g_new$460 ; + wire \g_new$461 ; + wire \g_new$462 ; + wire \g_new$463 ; + wire \g_new$464 ; + wire \g_new$465 ; + wire \g_new$466 ; + wire \g_new$467 ; + wire \g_new$468 ; + wire \g_new$469 ; + wire \g_new$470 ; + wire \g_new$471 ; + wire \g_new$472 ; + wire \g_new$473 ; + wire \g_new$474 ; + wire \g_new$475 ; + wire \g_new$476 ; + wire \g_new$477 ; + wire \g_new$478 ; + wire \g_new$479 ; + wire \g_new$480 ; + wire \g_new$481 ; + wire \g_new$482 ; + wire \g_new$483 ; + wire \g_new$484 ; + wire \g_new$485 ; + wire \g_new$486 ; + wire \g_new$487 ; + wire \g_new$488 ; + wire \g_new$489 ; + wire \g_new$490 ; + wire \g_new$491 ; + wire \g_new$492 ; + wire \g_new$493 ; + wire \g_new$494 ; + wire \g_new$495 ; + wire \g_new$496 ; + wire \g_new$497 ; + wire \g_new$498 ; + wire \g_new$499 ; + wire \g_new$500 ; + wire \g_new$501 ; + wire \g_new$502 ; + wire \g_new$503 ; + wire \g_new$504 ; + wire \g_new$505 ; + wire \g_new$506 ; + wire \g_new$507 ; + wire [63:0] o; + wire [63:0] \o$134 ; + wire [63:0] o2; + wire p_new; + wire \p_new$328 ; + wire \p_new$331 ; + wire \p_new$332 ; + wire \p_new$335 ; + wire \p_new$336 ; + wire \p_new$339 ; + wire \p_new$340 ; + wire \p_new$343 ; + wire \p_new$344 ; + wire \p_new$347 ; + wire \p_new$348 ; + wire \p_new$351 ; + wire \p_new$352 ; + wire \p_new$355 ; + wire \p_new$356 ; + wire \p_new$359 ; + wire \p_new$360 ; + wire \p_new$363 ; + wire \p_new$364 ; + wire \p_new$367 ; + wire \p_new$368 ; + wire \p_new$371 ; + wire \p_new$372 ; + wire \p_new$375 ; + wire \p_new$376 ; + wire \p_new$379 ; + wire \p_new$380 ; + wire \p_new$383 ; + wire \p_new$384 ; + wire \p_new$387 ; + wire \p_new$388 ; + wire \p_new$391 ; + wire \p_new$392 ; + wire \p_new$395 ; + wire \p_new$396 ; + wire \p_new$399 ; + wire \p_new$400 ; + wire \p_new$403 ; + wire \p_new$404 ; + wire \p_new$407 ; + wire \p_new$408 ; + wire \p_new$411 ; + wire \p_new$412 ; + wire \p_new$415 ; + wire \p_new$416 ; + wire \p_new$419 ; + wire \p_new$420 ; + wire \p_new$423 ; + wire \p_new$424 ; + wire \p_new$427 ; + wire \p_new$428 ; + wire \p_new$431 ; + wire \p_new$432 ; + wire \p_new$435 ; + wire \p_new$436 ; + wire \p_new$439 ; + wire \p_new$440 ; + wire \p_new$443 ; + wire \p_new$444 ; + wire \p_new$447 ; + wire \p_new$448 ; + output \port$901$0 ; + wire \port$901$0 ; + output \port$902$0 ; + wire \port$902$0 ; + output \port$903$0 ; + wire \port$903$0 ; + output \port$904$0 ; + wire \port$904$0 ; + output \port$905$0 ; + wire \port$905$0 ; + output \port$906$0 ; + wire \port$906$0 ; + output \port$907$0 ; + wire \port$907$0 ; + output \port$908$0 ; + wire \port$908$0 ; + output \port$909$0 ; + wire \port$909$0 ; + output \port$910$0 ; + wire \port$910$0 ; + output \port$911$0 ; + wire \port$911$0 ; + output \port$912$0 ; + wire \port$912$0 ; + output \port$913$0 ; + wire \port$913$0 ; + output \port$914$0 ; + wire \port$914$0 ; + output \port$915$0 ; + wire \port$915$0 ; + output \port$916$0 ; + wire \port$916$0 ; + output \port$917$0 ; + wire \port$917$0 ; + output \port$918$0 ; + wire \port$918$0 ; + output \port$919$0 ; + wire \port$919$0 ; + output \port$920$0 ; + wire \port$920$0 ; + output \port$921$0 ; + wire \port$921$0 ; + output \port$922$0 ; + wire \port$922$0 ; + output \port$923$0 ; + wire \port$923$0 ; + output \port$924$0 ; + wire \port$924$0 ; + output \port$925$0 ; + wire \port$925$0 ; + output \port$926$0 ; + wire \port$926$0 ; + output \port$927$0 ; + wire \port$927$0 ; + output \port$928$0 ; + wire \port$928$0 ; + output \port$929$0 ; + wire \port$929$0 ; + output \port$930$0 ; + wire \port$930$0 ; + output \port$931$0 ; + wire \port$931$0 ; + output \port$932$0 ; + wire \port$932$0 ; + output \port$933$0 ; + wire \port$933$0 ; + output \port$934$0 ; + wire \port$934$0 ; + output \port$935$0 ; + wire \port$935$0 ; + output \port$936$0 ; + wire \port$936$0 ; + output \port$937$0 ; + wire \port$937$0 ; + output \port$938$0 ; + wire \port$938$0 ; + output \port$939$0 ; + wire \port$939$0 ; + output \port$940$0 ; + wire \port$940$0 ; + output \port$941$0 ; + wire \port$941$0 ; + output \port$942$0 ; + wire \port$942$0 ; + output \port$943$0 ; + wire \port$943$0 ; + output \port$944$0 ; + wire \port$944$0 ; + output \port$945$0 ; + wire \port$945$0 ; + output \port$946$0 ; + wire \port$946$0 ; + output \port$947$0 ; + wire \port$947$0 ; + output \port$948$0 ; + wire \port$948$0 ; + output \port$949$0 ; + wire \port$949$0 ; + output \port$950$0 ; + wire \port$950$0 ; + output \port$951$0 ; + wire \port$951$0 ; + output \port$952$0 ; + wire \port$952$0 ; + output \port$953$0 ; + wire \port$953$0 ; + output \port$954$0 ; + wire \port$954$0 ; + output \port$955$0 ; + wire \port$955$0 ; + output \port$956$0 ; + wire \port$956$0 ; + output \port$957$0 ; + wire \port$957$0 ; + output \port$958$0 ; + wire \port$958$0 ; + output \port$959$0 ; + wire \port$959$0 ; + output \port$960$0 ; + wire \port$960$0 ; + output \port$961$0 ; + wire \port$961$0 ; + output \port$962$0 ; + wire \port$962$0 ; + output \port$963$0 ; + wire \port$963$0 ; + output \port$964$0 ; + wire \port$964$0 ; + wire sn; + wire \sn$138 ; + wire \sn$140 ; + wire \sn$142 ; + wire \sn$144 ; + wire \sn$146 ; + wire \sn$148 ; + wire \sn$150 ; + wire \sn$152 ; + wire \sn$154 ; + wire \sn$156 ; + wire \sn$158 ; + wire \sn$160 ; + wire \sn$162 ; + wire \sn$164 ; + wire \sn$166 ; + wire \sn$168 ; + wire \sn$170 ; + wire \sn$172 ; + wire \sn$174 ; + wire \sn$176 ; + wire \sn$178 ; + wire \sn$180 ; + wire \sn$182 ; + wire \sn$184 ; + wire \sn$186 ; + wire \sn$188 ; + wire \sn$190 ; + wire \sn$192 ; + wire \sn$194 ; + wire \sn$196 ; + wire \sn$198 ; + wire \sn$200 ; + wire \sn$202 ; + wire \sn$204 ; + wire \sn$206 ; + wire \sn$208 ; + wire \sn$210 ; + wire \sn$212 ; + wire \sn$214 ; + wire \sn$216 ; + wire \sn$218 ; + wire \sn$220 ; + wire \sn$222 ; + wire \sn$224 ; + wire \sn$226 ; + wire \sn$228 ; + wire \sn$230 ; + wire \sn$232 ; + wire \sn$234 ; + wire \sn$236 ; + wire \sn$238 ; + wire \sn$240 ; + wire \sn$242 ; + wire \sn$244 ; + wire \sn$246 ; + wire \sn$248 ; + wire \sn$250 ; + wire \sn$252 ; + wire \sn$254 ; + wire \sn$256 ; + wire \sn$258 ; + wire \sn$260 ; + wire \sn$262 ; + HAxp5_ASAP7_75t_R \U$0 ( + .A(a[0]), + .B(b[0]), + .CON(con), + .SN(sn) + ); + INVx1_ASAP7_75t_R \U$1 ( + .A(con), + .Y(\$signal$263 ) + ); + INVx1_ASAP7_75t_R \U$10 ( + .A(\con$141 ), + .Y(\$signal$266 ) + ); + INVx1_ASAP7_75t_R \U$100 ( + .A(\con$201 ), + .Y(\$signal$296 ) + ); + INVx1_ASAP7_75t_R \U$101 ( + .A(\sn$202 ), + .Y(\$signal$70 ) + ); + HAxp5_ASAP7_75t_R \U$102 ( + .A(a[34]), + .B(b[34]), + .CON(\con$203 ), + .SN(\sn$204 ) + ); + INVx1_ASAP7_75t_R \U$103 ( + .A(\con$203 ), + .Y(\$signal$297 ) + ); + INVx1_ASAP7_75t_R \U$104 ( + .A(\sn$204 ), + .Y(\$signal$72 ) + ); + HAxp5_ASAP7_75t_R \U$105 ( + .A(a[35]), + .B(b[35]), + .CON(\con$205 ), + .SN(\sn$206 ) + ); + INVx1_ASAP7_75t_R \U$106 ( + .A(\con$205 ), + .Y(\$signal$298 ) + ); + INVx1_ASAP7_75t_R \U$107 ( + .A(\sn$206 ), + .Y(\$signal$74 ) + ); + HAxp5_ASAP7_75t_R \U$108 ( + .A(a[36]), + .B(b[36]), + .CON(\con$207 ), + .SN(\sn$208 ) + ); + INVx1_ASAP7_75t_R \U$109 ( + .A(\con$207 ), + .Y(\$signal$299 ) + ); + INVx1_ASAP7_75t_R \U$11 ( + .A(\sn$142 ), + .Y(\$signal$10 ) + ); + INVx1_ASAP7_75t_R \U$110 ( + .A(\sn$208 ), + .Y(\$signal$76 ) + ); + HAxp5_ASAP7_75t_R \U$111 ( + .A(a[37]), + .B(b[37]), + .CON(\con$209 ), + .SN(\sn$210 ) + ); + INVx1_ASAP7_75t_R \U$112 ( + .A(\con$209 ), + .Y(\$signal$300 ) + ); + INVx1_ASAP7_75t_R \U$113 ( + .A(\sn$210 ), + .Y(\$signal$78 ) + ); + HAxp5_ASAP7_75t_R \U$114 ( + .A(a[38]), + .B(b[38]), + .CON(\con$211 ), + .SN(\sn$212 ) + ); + INVx1_ASAP7_75t_R \U$115 ( + .A(\con$211 ), + .Y(\$signal$301 ) + ); + INVx1_ASAP7_75t_R \U$116 ( + .A(\sn$212 ), + .Y(\$signal$80 ) + ); + HAxp5_ASAP7_75t_R \U$117 ( + .A(a[39]), + .B(b[39]), + .CON(\con$213 ), + .SN(\sn$214 ) + ); + INVx1_ASAP7_75t_R \U$118 ( + .A(\con$213 ), + .Y(\$signal$302 ) + ); + INVx1_ASAP7_75t_R \U$119 ( + .A(\sn$214 ), + .Y(\$signal$82 ) + ); + HAxp5_ASAP7_75t_R \U$12 ( + .A(a[4]), + .B(b[4]), + .CON(\con$143 ), + .SN(\sn$144 ) + ); + HAxp5_ASAP7_75t_R \U$120 ( + .A(a[40]), + .B(b[40]), + .CON(\con$215 ), + .SN(\sn$216 ) + ); + INVx1_ASAP7_75t_R \U$121 ( + .A(\con$215 ), + .Y(\$signal$303 ) + ); + INVx1_ASAP7_75t_R \U$122 ( + .A(\sn$216 ), + .Y(\$signal$84 ) + ); + HAxp5_ASAP7_75t_R \U$123 ( + .A(a[41]), + .B(b[41]), + .CON(\con$217 ), + .SN(\sn$218 ) + ); + INVx1_ASAP7_75t_R \U$124 ( + .A(\con$217 ), + .Y(\$signal$304 ) + ); + INVx1_ASAP7_75t_R \U$125 ( + .A(\sn$218 ), + .Y(\$signal$86 ) + ); + HAxp5_ASAP7_75t_R \U$126 ( + .A(a[42]), + .B(b[42]), + .CON(\con$219 ), + .SN(\sn$220 ) + ); + INVx1_ASAP7_75t_R \U$127 ( + .A(\con$219 ), + .Y(\$signal$305 ) + ); + INVx1_ASAP7_75t_R \U$128 ( + .A(\sn$220 ), + .Y(\$signal$88 ) + ); + HAxp5_ASAP7_75t_R \U$129 ( + .A(a[43]), + .B(b[43]), + .CON(\con$221 ), + .SN(\sn$222 ) + ); + INVx1_ASAP7_75t_R \U$13 ( + .A(\con$143 ), + .Y(\$signal$267 ) + ); + INVx1_ASAP7_75t_R \U$130 ( + .A(\con$221 ), + .Y(\$signal$306 ) + ); + INVx1_ASAP7_75t_R \U$131 ( + .A(\sn$222 ), + .Y(\$signal$90 ) + ); + HAxp5_ASAP7_75t_R \U$132 ( + .A(a[44]), + .B(b[44]), + .CON(\con$223 ), + .SN(\sn$224 ) + ); + INVx1_ASAP7_75t_R \U$133 ( + .A(\con$223 ), + .Y(\$signal$307 ) + ); + INVx1_ASAP7_75t_R \U$134 ( + .A(\sn$224 ), + .Y(\$signal$92 ) + ); + HAxp5_ASAP7_75t_R \U$135 ( + .A(a[45]), + .B(b[45]), + .CON(\con$225 ), + .SN(\sn$226 ) + ); + INVx1_ASAP7_75t_R \U$136 ( + .A(\con$225 ), + .Y(\$signal$308 ) + ); + INVx1_ASAP7_75t_R \U$137 ( + .A(\sn$226 ), + .Y(\$signal$94 ) + ); + HAxp5_ASAP7_75t_R \U$138 ( + .A(a[46]), + .B(b[46]), + .CON(\con$227 ), + .SN(\sn$228 ) + ); + INVx1_ASAP7_75t_R \U$139 ( + .A(\con$227 ), + .Y(\$signal$309 ) + ); + INVx1_ASAP7_75t_R \U$14 ( + .A(\sn$144 ), + .Y(\$signal$12 ) + ); + INVx1_ASAP7_75t_R \U$140 ( + .A(\sn$228 ), + .Y(\$signal$96 ) + ); + HAxp5_ASAP7_75t_R \U$141 ( + .A(a[47]), + .B(b[47]), + .CON(\con$229 ), + .SN(\sn$230 ) + ); + INVx1_ASAP7_75t_R \U$142 ( + .A(\con$229 ), + .Y(\$signal$310 ) + ); + INVx1_ASAP7_75t_R \U$143 ( + .A(\sn$230 ), + .Y(\$signal$98 ) + ); + HAxp5_ASAP7_75t_R \U$144 ( + .A(a[48]), + .B(b[48]), + .CON(\con$231 ), + .SN(\sn$232 ) + ); + INVx1_ASAP7_75t_R \U$145 ( + .A(\con$231 ), + .Y(\$signal$311 ) + ); + INVx1_ASAP7_75t_R \U$146 ( + .A(\sn$232 ), + .Y(\$signal$100 ) + ); + HAxp5_ASAP7_75t_R \U$147 ( + .A(a[49]), + .B(b[49]), + .CON(\con$233 ), + .SN(\sn$234 ) + ); + INVx1_ASAP7_75t_R \U$148 ( + .A(\con$233 ), + .Y(\$signal$312 ) + ); + INVx1_ASAP7_75t_R \U$149 ( + .A(\sn$234 ), + .Y(\$signal$102 ) + ); + HAxp5_ASAP7_75t_R \U$15 ( + .A(a[5]), + .B(b[5]), + .CON(\con$145 ), + .SN(\sn$146 ) + ); + HAxp5_ASAP7_75t_R \U$150 ( + .A(a[50]), + .B(b[50]), + .CON(\con$235 ), + .SN(\sn$236 ) + ); + INVx1_ASAP7_75t_R \U$151 ( + .A(\con$235 ), + .Y(\$signal$313 ) + ); + INVx1_ASAP7_75t_R \U$152 ( + .A(\sn$236 ), + .Y(\$signal$104 ) + ); + HAxp5_ASAP7_75t_R \U$153 ( + .A(a[51]), + .B(b[51]), + .CON(\con$237 ), + .SN(\sn$238 ) + ); + INVx1_ASAP7_75t_R \U$154 ( + .A(\con$237 ), + .Y(\$signal$314 ) + ); + INVx1_ASAP7_75t_R \U$155 ( + .A(\sn$238 ), + .Y(\$signal$106 ) + ); + HAxp5_ASAP7_75t_R \U$156 ( + .A(a[52]), + .B(b[52]), + .CON(\con$239 ), + .SN(\sn$240 ) + ); + INVx1_ASAP7_75t_R \U$157 ( + .A(\con$239 ), + .Y(\$signal$315 ) + ); + INVx1_ASAP7_75t_R \U$158 ( + .A(\sn$240 ), + .Y(\$signal$108 ) + ); + HAxp5_ASAP7_75t_R \U$159 ( + .A(a[53]), + .B(b[53]), + .CON(\con$241 ), + .SN(\sn$242 ) + ); + INVx1_ASAP7_75t_R \U$16 ( + .A(\con$145 ), + .Y(\$signal$268 ) + ); + INVx1_ASAP7_75t_R \U$160 ( + .A(\con$241 ), + .Y(\$signal$316 ) + ); + INVx1_ASAP7_75t_R \U$161 ( + .A(\sn$242 ), + .Y(\$signal$110 ) + ); + HAxp5_ASAP7_75t_R \U$162 ( + .A(a[54]), + .B(b[54]), + .CON(\con$243 ), + .SN(\sn$244 ) + ); + INVx1_ASAP7_75t_R \U$163 ( + .A(\con$243 ), + .Y(\$signal$317 ) + ); + INVx1_ASAP7_75t_R \U$164 ( + .A(\sn$244 ), + .Y(\$signal$112 ) + ); + HAxp5_ASAP7_75t_R \U$165 ( + .A(a[55]), + .B(b[55]), + .CON(\con$245 ), + .SN(\sn$246 ) + ); + INVx1_ASAP7_75t_R \U$166 ( + .A(\con$245 ), + .Y(\$signal$318 ) + ); + INVx1_ASAP7_75t_R \U$167 ( + .A(\sn$246 ), + .Y(\$signal$114 ) + ); + HAxp5_ASAP7_75t_R \U$168 ( + .A(a[56]), + .B(b[56]), + .CON(\con$247 ), + .SN(\sn$248 ) + ); + INVx1_ASAP7_75t_R \U$169 ( + .A(\con$247 ), + .Y(\$signal$319 ) + ); + INVx1_ASAP7_75t_R \U$17 ( + .A(\sn$146 ), + .Y(\$signal$14 ) + ); + INVx1_ASAP7_75t_R \U$170 ( + .A(\sn$248 ), + .Y(\$signal$116 ) + ); + HAxp5_ASAP7_75t_R \U$171 ( + .A(a[57]), + .B(b[57]), + .CON(\con$249 ), + .SN(\sn$250 ) + ); + INVx1_ASAP7_75t_R \U$172 ( + .A(\con$249 ), + .Y(\$signal$320 ) + ); + INVx1_ASAP7_75t_R \U$173 ( + .A(\sn$250 ), + .Y(\$signal$118 ) + ); + HAxp5_ASAP7_75t_R \U$174 ( + .A(a[58]), + .B(b[58]), + .CON(\con$251 ), + .SN(\sn$252 ) + ); + INVx1_ASAP7_75t_R \U$175 ( + .A(\con$251 ), + .Y(\$signal$321 ) + ); + INVx1_ASAP7_75t_R \U$176 ( + .A(\sn$252 ), + .Y(\$signal$120 ) + ); + HAxp5_ASAP7_75t_R \U$177 ( + .A(a[59]), + .B(b[59]), + .CON(\con$253 ), + .SN(\sn$254 ) + ); + INVx1_ASAP7_75t_R \U$178 ( + .A(\con$253 ), + .Y(\$signal$322 ) + ); + INVx1_ASAP7_75t_R \U$179 ( + .A(\sn$254 ), + .Y(\$signal$122 ) + ); + HAxp5_ASAP7_75t_R \U$18 ( + .A(a[6]), + .B(b[6]), + .CON(\con$147 ), + .SN(\sn$148 ) + ); + HAxp5_ASAP7_75t_R \U$180 ( + .A(a[60]), + .B(b[60]), + .CON(\con$255 ), + .SN(\sn$256 ) + ); + INVx1_ASAP7_75t_R \U$181 ( + .A(\con$255 ), + .Y(\$signal$323 ) + ); + INVx1_ASAP7_75t_R \U$182 ( + .A(\sn$256 ), + .Y(\$signal$124 ) + ); + HAxp5_ASAP7_75t_R \U$183 ( + .A(a[61]), + .B(b[61]), + .CON(\con$257 ), + .SN(\sn$258 ) + ); + INVx1_ASAP7_75t_R \U$184 ( + .A(\con$257 ), + .Y(\$signal$324 ) + ); + INVx1_ASAP7_75t_R \U$185 ( + .A(\sn$258 ), + .Y(\$signal$126 ) + ); + HAxp5_ASAP7_75t_R \U$186 ( + .A(a[62]), + .B(b[62]), + .CON(\con$259 ), + .SN(\sn$260 ) + ); + INVx1_ASAP7_75t_R \U$187 ( + .A(\con$259 ), + .Y(\$signal$325 ) + ); + INVx1_ASAP7_75t_R \U$188 ( + .A(\sn$260 ), + .Y(\$signal$128 ) + ); + HAxp5_ASAP7_75t_R \U$189 ( + .A(a[63]), + .B(b[63]), + .CON(\con$261 ), + .SN(\sn$262 ) + ); + INVx1_ASAP7_75t_R \U$19 ( + .A(\con$147 ), + .Y(\$signal$269 ) + ); + INVx1_ASAP7_75t_R \U$190 ( + .A(\con$261 ), + .Y(\$signal$326 ) + ); + INVx1_ASAP7_75t_R \U$191 ( + .A(\sn$262 ), + .Y(\$signal$130 ) + ); + AND2x2_ASAP7_75t_R \U$192 ( + .A(\$signal$6 ), + .B(\$signal ), + .Y(\p_new$328 ) + ); + AO21x1_ASAP7_75t_R \U$193 ( + .A1(\$signal$6 ), + .A2(\$signal$263 ), + .B(\$signal$264 ), + .Y(g_new) + ); + AND2x2_ASAP7_75t_R \U$194 ( + .A(\$signal$10 ), + .B(\$signal$8 ), + .Y(p_new) + ); + AO21x1_ASAP7_75t_R \U$195 ( + .A1(\$signal$10 ), + .A2(\$signal$265 ), + .B(\$signal$266 ), + .Y(\g_new$330 ) + ); + AND2x2_ASAP7_75t_R \U$196 ( + .A(\$signal$14 ), + .B(\$signal$12 ), + .Y(\p_new$332 ) + ); + AO21x1_ASAP7_75t_R \U$197 ( + .A1(\$signal$14 ), + .A2(\$signal$267 ), + .B(\$signal$268 ), + .Y(\g_new$333 ) + ); + AND2x2_ASAP7_75t_R \U$198 ( + .A(\$signal$18 ), + .B(\$signal$16 ), + .Y(\p_new$331 ) + ); + AO21x1_ASAP7_75t_R \U$199 ( + .A1(\$signal$18 ), + .A2(\$signal$269 ), + .B(\$signal$270 ), + .Y(\g_new$334 ) + ); + INVx1_ASAP7_75t_R \U$2 ( + .A(sn), + .Y(\$signal ) + ); + INVx1_ASAP7_75t_R \U$20 ( + .A(\sn$148 ), + .Y(\$signal$16 ) + ); + AND2x2_ASAP7_75t_R \U$200 ( + .A(\$signal$22 ), + .B(\$signal$20 ), + .Y(\p_new$336 ) + ); + AO21x1_ASAP7_75t_R \U$201 ( + .A1(\$signal$22 ), + .A2(\$signal$271 ), + .B(\$signal$272 ), + .Y(\g_new$337 ) + ); + AND2x2_ASAP7_75t_R \U$202 ( + .A(\$signal$26 ), + .B(\$signal$24 ), + .Y(\p_new$335 ) + ); + AO21x1_ASAP7_75t_R \U$203 ( + .A1(\$signal$26 ), + .A2(\$signal$273 ), + .B(\$signal$274 ), + .Y(\g_new$338 ) + ); + AND2x2_ASAP7_75t_R \U$204 ( + .A(\$signal$30 ), + .B(\$signal$28 ), + .Y(\p_new$340 ) + ); + AO21x1_ASAP7_75t_R \U$205 ( + .A1(\$signal$30 ), + .A2(\$signal$275 ), + .B(\$signal$276 ), + .Y(\g_new$341 ) + ); + AND2x2_ASAP7_75t_R \U$206 ( + .A(\$signal$34 ), + .B(\$signal$32 ), + .Y(\p_new$339 ) + ); + AO21x1_ASAP7_75t_R \U$207 ( + .A1(\$signal$34 ), + .A2(\$signal$277 ), + .B(\$signal$278 ), + .Y(\g_new$342 ) + ); + AND2x2_ASAP7_75t_R \U$208 ( + .A(\$signal$38 ), + .B(\$signal$36 ), + .Y(\p_new$344 ) + ); + AO21x1_ASAP7_75t_R \U$209 ( + .A1(\$signal$38 ), + .A2(\$signal$279 ), + .B(\$signal$280 ), + .Y(\g_new$345 ) + ); + HAxp5_ASAP7_75t_R \U$21 ( + .A(a[7]), + .B(b[7]), + .CON(\con$149 ), + .SN(\sn$150 ) + ); + AND2x2_ASAP7_75t_R \U$210 ( + .A(\$signal$42 ), + .B(\$signal$40 ), + .Y(\p_new$343 ) + ); + AO21x1_ASAP7_75t_R \U$211 ( + .A1(\$signal$42 ), + .A2(\$signal$281 ), + .B(\$signal$282 ), + .Y(\g_new$346 ) + ); + AND2x2_ASAP7_75t_R \U$212 ( + .A(\$signal$46 ), + .B(\$signal$44 ), + .Y(\p_new$348 ) + ); + AO21x1_ASAP7_75t_R \U$213 ( + .A1(\$signal$46 ), + .A2(\$signal$283 ), + .B(\$signal$284 ), + .Y(\g_new$349 ) + ); + AND2x2_ASAP7_75t_R \U$214 ( + .A(\$signal$50 ), + .B(\$signal$48 ), + .Y(\p_new$347 ) + ); + AO21x1_ASAP7_75t_R \U$215 ( + .A1(\$signal$50 ), + .A2(\$signal$285 ), + .B(\$signal$286 ), + .Y(\g_new$350 ) + ); + AND2x2_ASAP7_75t_R \U$216 ( + .A(\$signal$54 ), + .B(\$signal$52 ), + .Y(\p_new$352 ) + ); + AO21x1_ASAP7_75t_R \U$217 ( + .A1(\$signal$54 ), + .A2(\$signal$287 ), + .B(\$signal$288 ), + .Y(\g_new$353 ) + ); + AND2x2_ASAP7_75t_R \U$218 ( + .A(\$signal$58 ), + .B(\$signal$56 ), + .Y(\p_new$351 ) + ); + AO21x1_ASAP7_75t_R \U$219 ( + .A1(\$signal$58 ), + .A2(\$signal$289 ), + .B(\$signal$290 ), + .Y(\g_new$354 ) + ); + INVx1_ASAP7_75t_R \U$22 ( + .A(\con$149 ), + .Y(\$signal$270 ) + ); + AND2x2_ASAP7_75t_R \U$220 ( + .A(\$signal$62 ), + .B(\$signal$60 ), + .Y(\p_new$356 ) + ); + AO21x1_ASAP7_75t_R \U$221 ( + .A1(\$signal$62 ), + .A2(\$signal$291 ), + .B(\$signal$292 ), + .Y(\g_new$357 ) + ); + AND2x2_ASAP7_75t_R \U$222 ( + .A(\$signal$66 ), + .B(\$signal$64 ), + .Y(\p_new$355 ) + ); + AO21x1_ASAP7_75t_R \U$223 ( + .A1(\$signal$66 ), + .A2(\$signal$293 ), + .B(\$signal$294 ), + .Y(\g_new$358 ) + ); + AND2x2_ASAP7_75t_R \U$224 ( + .A(\$signal$70 ), + .B(\$signal$68 ), + .Y(\p_new$360 ) + ); + AO21x1_ASAP7_75t_R \U$225 ( + .A1(\$signal$70 ), + .A2(\$signal$295 ), + .B(\$signal$296 ), + .Y(\g_new$361 ) + ); + AND2x2_ASAP7_75t_R \U$226 ( + .A(\$signal$74 ), + .B(\$signal$72 ), + .Y(\p_new$359 ) + ); + AO21x1_ASAP7_75t_R \U$227 ( + .A1(\$signal$74 ), + .A2(\$signal$297 ), + .B(\$signal$298 ), + .Y(\g_new$362 ) + ); + AND2x2_ASAP7_75t_R \U$228 ( + .A(\$signal$78 ), + .B(\$signal$76 ), + .Y(\p_new$364 ) + ); + AO21x1_ASAP7_75t_R \U$229 ( + .A1(\$signal$78 ), + .A2(\$signal$299 ), + .B(\$signal$300 ), + .Y(\g_new$365 ) + ); + INVx1_ASAP7_75t_R \U$23 ( + .A(\sn$150 ), + .Y(\$signal$18 ) + ); + AND2x2_ASAP7_75t_R \U$230 ( + .A(\$signal$82 ), + .B(\$signal$80 ), + .Y(\p_new$363 ) + ); + AO21x1_ASAP7_75t_R \U$231 ( + .A1(\$signal$82 ), + .A2(\$signal$301 ), + .B(\$signal$302 ), + .Y(\g_new$366 ) + ); + AND2x2_ASAP7_75t_R \U$232 ( + .A(\$signal$86 ), + .B(\$signal$84 ), + .Y(\p_new$368 ) + ); + AO21x1_ASAP7_75t_R \U$233 ( + .A1(\$signal$86 ), + .A2(\$signal$303 ), + .B(\$signal$304 ), + .Y(\g_new$369 ) + ); + AND2x2_ASAP7_75t_R \U$234 ( + .A(\$signal$90 ), + .B(\$signal$88 ), + .Y(\p_new$367 ) + ); + AO21x1_ASAP7_75t_R \U$235 ( + .A1(\$signal$90 ), + .A2(\$signal$305 ), + .B(\$signal$306 ), + .Y(\g_new$370 ) + ); + AND2x2_ASAP7_75t_R \U$236 ( + .A(\$signal$94 ), + .B(\$signal$92 ), + .Y(\p_new$372 ) + ); + AO21x1_ASAP7_75t_R \U$237 ( + .A1(\$signal$94 ), + .A2(\$signal$307 ), + .B(\$signal$308 ), + .Y(\g_new$373 ) + ); + AND2x2_ASAP7_75t_R \U$238 ( + .A(\$signal$98 ), + .B(\$signal$96 ), + .Y(\p_new$371 ) + ); + AO21x1_ASAP7_75t_R \U$239 ( + .A1(\$signal$98 ), + .A2(\$signal$309 ), + .B(\$signal$310 ), + .Y(\g_new$374 ) + ); + HAxp5_ASAP7_75t_R \U$24 ( + .A(a[8]), + .B(b[8]), + .CON(\con$151 ), + .SN(\sn$152 ) + ); + AND2x2_ASAP7_75t_R \U$240 ( + .A(\$signal$102 ), + .B(\$signal$100 ), + .Y(\p_new$376 ) + ); + AO21x1_ASAP7_75t_R \U$241 ( + .A1(\$signal$102 ), + .A2(\$signal$311 ), + .B(\$signal$312 ), + .Y(\g_new$377 ) + ); + AND2x2_ASAP7_75t_R \U$242 ( + .A(\$signal$106 ), + .B(\$signal$104 ), + .Y(\p_new$375 ) + ); + AO21x1_ASAP7_75t_R \U$243 ( + .A1(\$signal$106 ), + .A2(\$signal$313 ), + .B(\$signal$314 ), + .Y(\g_new$378 ) + ); + AND2x2_ASAP7_75t_R \U$244 ( + .A(\$signal$110 ), + .B(\$signal$108 ), + .Y(\p_new$380 ) + ); + AO21x1_ASAP7_75t_R \U$245 ( + .A1(\$signal$110 ), + .A2(\$signal$315 ), + .B(\$signal$316 ), + .Y(\g_new$381 ) + ); + AND2x2_ASAP7_75t_R \U$246 ( + .A(\$signal$114 ), + .B(\$signal$112 ), + .Y(\p_new$379 ) + ); + AO21x1_ASAP7_75t_R \U$247 ( + .A1(\$signal$114 ), + .A2(\$signal$317 ), + .B(\$signal$318 ), + .Y(\g_new$382 ) + ); + AND2x2_ASAP7_75t_R \U$248 ( + .A(\$signal$118 ), + .B(\$signal$116 ), + .Y(\p_new$384 ) + ); + AO21x1_ASAP7_75t_R \U$249 ( + .A1(\$signal$118 ), + .A2(\$signal$319 ), + .B(\$signal$320 ), + .Y(\g_new$385 ) + ); + INVx1_ASAP7_75t_R \U$25 ( + .A(\con$151 ), + .Y(\$signal$271 ) + ); + AND2x2_ASAP7_75t_R \U$250 ( + .A(\$signal$122 ), + .B(\$signal$120 ), + .Y(\p_new$383 ) + ); + AO21x1_ASAP7_75t_R \U$251 ( + .A1(\$signal$122 ), + .A2(\$signal$321 ), + .B(\$signal$322 ), + .Y(\g_new$386 ) + ); + AND2x2_ASAP7_75t_R \U$252 ( + .A(\$signal$126 ), + .B(\$signal$124 ), + .Y(\p_new$388 ) + ); + AO21x1_ASAP7_75t_R \U$253 ( + .A1(\$signal$126 ), + .A2(\$signal$323 ), + .B(\$signal$324 ), + .Y(\g_new$389 ) + ); + AND2x2_ASAP7_75t_R \U$254 ( + .A(\$signal$130 ), + .B(\$signal$128 ), + .Y(\p_new$387 ) + ); + AO21x1_ASAP7_75t_R \U$255 ( + .A1(\$signal$130 ), + .A2(\$signal$325 ), + .B(\$signal$326 ), + .Y(\g_new$390 ) + ); + AND2x2_ASAP7_75t_R \U$256 ( + .A(p_new), + .B(\p_new$328 ), + .Y(\p_new$392 ) + ); + AO21x1_ASAP7_75t_R \U$257 ( + .A1(p_new), + .A2(g_new), + .B(\g_new$330 ), + .Y(\g_new$393 ) + ); + AND2x2_ASAP7_75t_R \U$258 ( + .A(\p_new$331 ), + .B(\p_new$332 ), + .Y(\p_new$391 ) + ); + AO21x1_ASAP7_75t_R \U$259 ( + .A1(\p_new$331 ), + .A2(\g_new$333 ), + .B(\g_new$334 ), + .Y(\g_new$394 ) + ); + INVx1_ASAP7_75t_R \U$26 ( + .A(\sn$152 ), + .Y(\$signal$20 ) + ); + AND2x2_ASAP7_75t_R \U$260 ( + .A(\p_new$335 ), + .B(\p_new$336 ), + .Y(\p_new$396 ) + ); + AO21x1_ASAP7_75t_R \U$261 ( + .A1(\p_new$335 ), + .A2(\g_new$337 ), + .B(\g_new$338 ), + .Y(\g_new$397 ) + ); + AND2x2_ASAP7_75t_R \U$262 ( + .A(\p_new$339 ), + .B(\p_new$340 ), + .Y(\p_new$395 ) + ); + AO21x1_ASAP7_75t_R \U$263 ( + .A1(\p_new$339 ), + .A2(\g_new$341 ), + .B(\g_new$342 ), + .Y(\g_new$398 ) + ); + AND2x2_ASAP7_75t_R \U$264 ( + .A(\p_new$343 ), + .B(\p_new$344 ), + .Y(\p_new$400 ) + ); + AO21x1_ASAP7_75t_R \U$265 ( + .A1(\p_new$343 ), + .A2(\g_new$345 ), + .B(\g_new$346 ), + .Y(\g_new$401 ) + ); + AND2x2_ASAP7_75t_R \U$266 ( + .A(\p_new$347 ), + .B(\p_new$348 ), + .Y(\p_new$399 ) + ); + AO21x1_ASAP7_75t_R \U$267 ( + .A1(\p_new$347 ), + .A2(\g_new$349 ), + .B(\g_new$350 ), + .Y(\g_new$402 ) + ); + AND2x2_ASAP7_75t_R \U$268 ( + .A(\p_new$351 ), + .B(\p_new$352 ), + .Y(\p_new$404 ) + ); + AO21x1_ASAP7_75t_R \U$269 ( + .A1(\p_new$351 ), + .A2(\g_new$353 ), + .B(\g_new$354 ), + .Y(\g_new$405 ) + ); + HAxp5_ASAP7_75t_R \U$27 ( + .A(a[9]), + .B(b[9]), + .CON(\con$153 ), + .SN(\sn$154 ) + ); + AND2x2_ASAP7_75t_R \U$270 ( + .A(\p_new$355 ), + .B(\p_new$356 ), + .Y(\p_new$403 ) + ); + AO21x1_ASAP7_75t_R \U$271 ( + .A1(\p_new$355 ), + .A2(\g_new$357 ), + .B(\g_new$358 ), + .Y(\g_new$406 ) + ); + AND2x2_ASAP7_75t_R \U$272 ( + .A(\p_new$359 ), + .B(\p_new$360 ), + .Y(\p_new$408 ) + ); + AO21x1_ASAP7_75t_R \U$273 ( + .A1(\p_new$359 ), + .A2(\g_new$361 ), + .B(\g_new$362 ), + .Y(\g_new$409 ) + ); + AND2x2_ASAP7_75t_R \U$274 ( + .A(\p_new$363 ), + .B(\p_new$364 ), + .Y(\p_new$407 ) + ); + AO21x1_ASAP7_75t_R \U$275 ( + .A1(\p_new$363 ), + .A2(\g_new$365 ), + .B(\g_new$366 ), + .Y(\g_new$410 ) + ); + AND2x2_ASAP7_75t_R \U$276 ( + .A(\p_new$367 ), + .B(\p_new$368 ), + .Y(\p_new$412 ) + ); + AO21x1_ASAP7_75t_R \U$277 ( + .A1(\p_new$367 ), + .A2(\g_new$369 ), + .B(\g_new$370 ), + .Y(\g_new$413 ) + ); + AND2x2_ASAP7_75t_R \U$278 ( + .A(\p_new$371 ), + .B(\p_new$372 ), + .Y(\p_new$411 ) + ); + AO21x1_ASAP7_75t_R \U$279 ( + .A1(\p_new$371 ), + .A2(\g_new$373 ), + .B(\g_new$374 ), + .Y(\g_new$414 ) + ); + INVx1_ASAP7_75t_R \U$28 ( + .A(\con$153 ), + .Y(\$signal$272 ) + ); + AND2x2_ASAP7_75t_R \U$280 ( + .A(\p_new$375 ), + .B(\p_new$376 ), + .Y(\p_new$416 ) + ); + AO21x1_ASAP7_75t_R \U$281 ( + .A1(\p_new$375 ), + .A2(\g_new$377 ), + .B(\g_new$378 ), + .Y(\g_new$417 ) + ); + AND2x2_ASAP7_75t_R \U$282 ( + .A(\p_new$379 ), + .B(\p_new$380 ), + .Y(\p_new$415 ) + ); + AO21x1_ASAP7_75t_R \U$283 ( + .A1(\p_new$379 ), + .A2(\g_new$381 ), + .B(\g_new$382 ), + .Y(\g_new$418 ) + ); + AND2x2_ASAP7_75t_R \U$284 ( + .A(\p_new$383 ), + .B(\p_new$384 ), + .Y(\p_new$420 ) + ); + AO21x1_ASAP7_75t_R \U$285 ( + .A1(\p_new$383 ), + .A2(\g_new$385 ), + .B(\g_new$386 ), + .Y(\g_new$421 ) + ); + AND2x2_ASAP7_75t_R \U$286 ( + .A(\p_new$387 ), + .B(\p_new$388 ), + .Y(\p_new$419 ) + ); + AO21x1_ASAP7_75t_R \U$287 ( + .A1(\p_new$387 ), + .A2(\g_new$389 ), + .B(\g_new$390 ), + .Y(\g_new$422 ) + ); + AND2x2_ASAP7_75t_R \U$288 ( + .A(\p_new$391 ), + .B(\p_new$392 ), + .Y(\p_new$424 ) + ); + AO21x1_ASAP7_75t_R \U$289 ( + .A1(\p_new$391 ), + .A2(\g_new$393 ), + .B(\g_new$394 ), + .Y(\g_new$425 ) + ); + INVx1_ASAP7_75t_R \U$29 ( + .A(\sn$154 ), + .Y(\$signal$22 ) + ); + AND2x2_ASAP7_75t_R \U$290 ( + .A(\p_new$395 ), + .B(\p_new$396 ), + .Y(\p_new$423 ) + ); + AO21x1_ASAP7_75t_R \U$291 ( + .A1(\p_new$395 ), + .A2(\g_new$397 ), + .B(\g_new$398 ), + .Y(\g_new$426 ) + ); + AND2x2_ASAP7_75t_R \U$292 ( + .A(\p_new$399 ), + .B(\p_new$400 ), + .Y(\p_new$428 ) + ); + AO21x1_ASAP7_75t_R \U$293 ( + .A1(\p_new$399 ), + .A2(\g_new$401 ), + .B(\g_new$402 ), + .Y(\g_new$429 ) + ); + AND2x2_ASAP7_75t_R \U$294 ( + .A(\p_new$403 ), + .B(\p_new$404 ), + .Y(\p_new$427 ) + ); + AO21x1_ASAP7_75t_R \U$295 ( + .A1(\p_new$403 ), + .A2(\g_new$405 ), + .B(\g_new$406 ), + .Y(\g_new$430 ) + ); + AND2x2_ASAP7_75t_R \U$296 ( + .A(\p_new$407 ), + .B(\p_new$408 ), + .Y(\p_new$432 ) + ); + AO21x1_ASAP7_75t_R \U$297 ( + .A1(\p_new$407 ), + .A2(\g_new$409 ), + .B(\g_new$410 ), + .Y(\g_new$433 ) + ); + AND2x2_ASAP7_75t_R \U$298 ( + .A(\p_new$411 ), + .B(\p_new$412 ), + .Y(\p_new$431 ) + ); + AO21x1_ASAP7_75t_R \U$299 ( + .A1(\p_new$411 ), + .A2(\g_new$413 ), + .B(\g_new$414 ), + .Y(\g_new$434 ) + ); + HAxp5_ASAP7_75t_R \U$3 ( + .A(a[1]), + .B(b[1]), + .CON(\con$137 ), + .SN(\sn$138 ) + ); + HAxp5_ASAP7_75t_R \U$30 ( + .A(a[10]), + .B(b[10]), + .CON(\con$155 ), + .SN(\sn$156 ) + ); + AND2x2_ASAP7_75t_R \U$300 ( + .A(\p_new$415 ), + .B(\p_new$416 ), + .Y(\p_new$436 ) + ); + AO21x1_ASAP7_75t_R \U$301 ( + .A1(\p_new$415 ), + .A2(\g_new$417 ), + .B(\g_new$418 ), + .Y(\g_new$437 ) + ); + AND2x2_ASAP7_75t_R \U$302 ( + .A(\p_new$419 ), + .B(\p_new$420 ), + .Y(\p_new$435 ) + ); + AO21x1_ASAP7_75t_R \U$303 ( + .A1(\p_new$419 ), + .A2(\g_new$421 ), + .B(\g_new$422 ), + .Y(\g_new$438 ) + ); + AND2x2_ASAP7_75t_R \U$304 ( + .A(\p_new$423 ), + .B(\p_new$424 ), + .Y(\p_new$440 ) + ); + AO21x1_ASAP7_75t_R \U$305 ( + .A1(\p_new$423 ), + .A2(\g_new$425 ), + .B(\g_new$426 ), + .Y(\g_new$441 ) + ); + AND2x2_ASAP7_75t_R \U$306 ( + .A(\p_new$427 ), + .B(\p_new$428 ), + .Y(\p_new$439 ) + ); + AO21x1_ASAP7_75t_R \U$307 ( + .A1(\p_new$427 ), + .A2(\g_new$429 ), + .B(\g_new$430 ), + .Y(\g_new$442 ) + ); + AND2x2_ASAP7_75t_R \U$308 ( + .A(\p_new$431 ), + .B(\p_new$432 ), + .Y(\p_new$444 ) + ); + AO21x1_ASAP7_75t_R \U$309 ( + .A1(\p_new$431 ), + .A2(\g_new$433 ), + .B(\g_new$434 ), + .Y(\g_new$445 ) + ); + INVx1_ASAP7_75t_R \U$31 ( + .A(\con$155 ), + .Y(\$signal$273 ) + ); + AND2x2_ASAP7_75t_R \U$310 ( + .A(\p_new$435 ), + .B(\p_new$436 ), + .Y(\p_new$443 ) + ); + AO21x1_ASAP7_75t_R \U$311 ( + .A1(\p_new$435 ), + .A2(\g_new$437 ), + .B(\g_new$438 ), + .Y(\g_new$446 ) + ); + AND2x2_ASAP7_75t_R \U$312 ( + .A(\p_new$439 ), + .B(\p_new$440 ), + .Y(\p_new$448 ) + ); + AO21x1_ASAP7_75t_R \U$313 ( + .A1(\p_new$439 ), + .A2(\g_new$441 ), + .B(\g_new$442 ), + .Y(\g_new$449 ) + ); + AND2x2_ASAP7_75t_R \U$314 ( + .A(\p_new$443 ), + .B(\p_new$444 ), + .Y(\p_new$447 ) + ); + AO21x1_ASAP7_75t_R \U$315 ( + .A1(\p_new$443 ), + .A2(\g_new$445 ), + .B(\g_new$446 ), + .Y(\g_new$450 ) + ); + AND2x2_ASAP7_75t_R \U$316 ( + .A(\p_new$447 ), + .B(\p_new$448 ), + .Y(\$1 ) + ); + AO21x1_ASAP7_75t_R \U$317 ( + .A1(\p_new$447 ), + .A2(\g_new$449 ), + .B(\g_new$450 ), + .Y(\$2 ) + ); + AO21x1_ASAP7_75t_R \U$318 ( + .A1(\p_new$444 ), + .A2(\g_new$449 ), + .B(\g_new$445 ), + .Y(\g_new$451 ) + ); + AO21x1_ASAP7_75t_R \U$319 ( + .A1(\p_new$428 ), + .A2(\g_new$441 ), + .B(\g_new$429 ), + .Y(\g_new$452 ) + ); + INVx1_ASAP7_75t_R \U$32 ( + .A(\sn$156 ), + .Y(\$signal$24 ) + ); + AO21x1_ASAP7_75t_R \U$320 ( + .A1(\p_new$432 ), + .A2(\g_new$449 ), + .B(\g_new$433 ), + .Y(\g_new$453 ) + ); + AO21x1_ASAP7_75t_R \U$321 ( + .A1(\p_new$436 ), + .A2(\g_new$451 ), + .B(\g_new$437 ), + .Y(\g_new$454 ) + ); + AO21x1_ASAP7_75t_R \U$322 ( + .A1(\p_new$396 ), + .A2(\g_new$425 ), + .B(\g_new$397 ), + .Y(\g_new$455 ) + ); + AO21x1_ASAP7_75t_R \U$323 ( + .A1(\p_new$400 ), + .A2(\g_new$441 ), + .B(\g_new$401 ), + .Y(\g_new$456 ) + ); + AO21x1_ASAP7_75t_R \U$324 ( + .A1(\p_new$404 ), + .A2(\g_new$452 ), + .B(\g_new$405 ), + .Y(\g_new$457 ) + ); + AO21x1_ASAP7_75t_R \U$325 ( + .A1(\p_new$408 ), + .A2(\g_new$449 ), + .B(\g_new$409 ), + .Y(\g_new$458 ) + ); + AO21x1_ASAP7_75t_R \U$326 ( + .A1(\p_new$412 ), + .A2(\g_new$453 ), + .B(\g_new$413 ), + .Y(\g_new$459 ) + ); + AO21x1_ASAP7_75t_R \U$327 ( + .A1(\p_new$416 ), + .A2(\g_new$451 ), + .B(\g_new$417 ), + .Y(\g_new$460 ) + ); + AO21x1_ASAP7_75t_R \U$328 ( + .A1(\p_new$420 ), + .A2(\g_new$454 ), + .B(\g_new$421 ), + .Y(\g_new$461 ) + ); + AO21x1_ASAP7_75t_R \U$329 ( + .A1(\p_new$332 ), + .A2(\g_new$393 ), + .B(\g_new$333 ), + .Y(\g_new$462 ) + ); + HAxp5_ASAP7_75t_R \U$33 ( + .A(a[11]), + .B(b[11]), + .CON(\con$157 ), + .SN(\sn$158 ) + ); + AO21x1_ASAP7_75t_R \U$330 ( + .A1(\p_new$336 ), + .A2(\g_new$425 ), + .B(\g_new$337 ), + .Y(\g_new$463 ) + ); + AO21x1_ASAP7_75t_R \U$331 ( + .A1(\p_new$340 ), + .A2(\g_new$455 ), + .B(\g_new$341 ), + .Y(\g_new$464 ) + ); + AO21x1_ASAP7_75t_R \U$332 ( + .A1(\p_new$344 ), + .A2(\g_new$441 ), + .B(\g_new$345 ), + .Y(\g_new$465 ) + ); + AO21x1_ASAP7_75t_R \U$333 ( + .A1(\p_new$348 ), + .A2(\g_new$456 ), + .B(\g_new$349 ), + .Y(\g_new$466 ) + ); + AO21x1_ASAP7_75t_R \U$334 ( + .A1(\p_new$352 ), + .A2(\g_new$452 ), + .B(\g_new$353 ), + .Y(\g_new$467 ) + ); + AO21x1_ASAP7_75t_R \U$335 ( + .A1(\p_new$356 ), + .A2(\g_new$457 ), + .B(\g_new$357 ), + .Y(\g_new$468 ) + ); + AO21x1_ASAP7_75t_R \U$336 ( + .A1(\p_new$360 ), + .A2(\g_new$449 ), + .B(\g_new$361 ), + .Y(\g_new$469 ) + ); + AO21x1_ASAP7_75t_R \U$337 ( + .A1(\p_new$364 ), + .A2(\g_new$458 ), + .B(\g_new$365 ), + .Y(\g_new$470 ) + ); + AO21x1_ASAP7_75t_R \U$338 ( + .A1(\p_new$368 ), + .A2(\g_new$453 ), + .B(\g_new$369 ), + .Y(\g_new$471 ) + ); + AO21x1_ASAP7_75t_R \U$339 ( + .A1(\p_new$372 ), + .A2(\g_new$459 ), + .B(\g_new$373 ), + .Y(\g_new$472 ) + ); + INVx1_ASAP7_75t_R \U$34 ( + .A(\con$157 ), + .Y(\$signal$274 ) + ); + AO21x1_ASAP7_75t_R \U$340 ( + .A1(\p_new$376 ), + .A2(\g_new$451 ), + .B(\g_new$377 ), + .Y(\g_new$473 ) + ); + AO21x1_ASAP7_75t_R \U$341 ( + .A1(\p_new$380 ), + .A2(\g_new$460 ), + .B(\g_new$381 ), + .Y(\g_new$474 ) + ); + AO21x1_ASAP7_75t_R \U$342 ( + .A1(\p_new$384 ), + .A2(\g_new$454 ), + .B(\g_new$385 ), + .Y(\g_new$475 ) + ); + AO21x1_ASAP7_75t_R \U$343 ( + .A1(\p_new$388 ), + .A2(\g_new$461 ), + .B(\g_new$389 ), + .Y(\g_new$476 ) + ); + AO21x1_ASAP7_75t_R \U$344 ( + .A1(\$signal$8 ), + .A2(g_new), + .B(\$signal$265 ), + .Y(\g_new$477 ) + ); + AO21x1_ASAP7_75t_R \U$345 ( + .A1(\$signal$12 ), + .A2(\g_new$393 ), + .B(\$signal$267 ), + .Y(\g_new$478 ) + ); + AO21x1_ASAP7_75t_R \U$346 ( + .A1(\$signal$16 ), + .A2(\g_new$462 ), + .B(\$signal$269 ), + .Y(\g_new$479 ) + ); + AO21x1_ASAP7_75t_R \U$347 ( + .A1(\$signal$20 ), + .A2(\g_new$425 ), + .B(\$signal$271 ), + .Y(\g_new$480 ) + ); + AO21x1_ASAP7_75t_R \U$348 ( + .A1(\$signal$24 ), + .A2(\g_new$463 ), + .B(\$signal$273 ), + .Y(\g_new$481 ) + ); + AO21x1_ASAP7_75t_R \U$349 ( + .A1(\$signal$28 ), + .A2(\g_new$455 ), + .B(\$signal$275 ), + .Y(\g_new$482 ) + ); + INVx1_ASAP7_75t_R \U$35 ( + .A(\sn$158 ), + .Y(\$signal$26 ) + ); + AO21x1_ASAP7_75t_R \U$350 ( + .A1(\$signal$32 ), + .A2(\g_new$464 ), + .B(\$signal$277 ), + .Y(\g_new$483 ) + ); + AO21x1_ASAP7_75t_R \U$351 ( + .A1(\$signal$36 ), + .A2(\g_new$441 ), + .B(\$signal$279 ), + .Y(\g_new$484 ) + ); + AO21x1_ASAP7_75t_R \U$352 ( + .A1(\$signal$40 ), + .A2(\g_new$465 ), + .B(\$signal$281 ), + .Y(\g_new$485 ) + ); + AO21x1_ASAP7_75t_R \U$353 ( + .A1(\$signal$44 ), + .A2(\g_new$456 ), + .B(\$signal$283 ), + .Y(\g_new$486 ) + ); + AO21x1_ASAP7_75t_R \U$354 ( + .A1(\$signal$48 ), + .A2(\g_new$466 ), + .B(\$signal$285 ), + .Y(\g_new$487 ) + ); + AO21x1_ASAP7_75t_R \U$355 ( + .A1(\$signal$52 ), + .A2(\g_new$452 ), + .B(\$signal$287 ), + .Y(\g_new$488 ) + ); + AO21x1_ASAP7_75t_R \U$356 ( + .A1(\$signal$56 ), + .A2(\g_new$467 ), + .B(\$signal$289 ), + .Y(\g_new$489 ) + ); + AO21x1_ASAP7_75t_R \U$357 ( + .A1(\$signal$60 ), + .A2(\g_new$457 ), + .B(\$signal$291 ), + .Y(\g_new$490 ) + ); + AO21x1_ASAP7_75t_R \U$358 ( + .A1(\$signal$64 ), + .A2(\g_new$468 ), + .B(\$signal$293 ), + .Y(\g_new$491 ) + ); + AO21x1_ASAP7_75t_R \U$359 ( + .A1(\$signal$68 ), + .A2(\g_new$449 ), + .B(\$signal$295 ), + .Y(\g_new$492 ) + ); + HAxp5_ASAP7_75t_R \U$36 ( + .A(a[12]), + .B(b[12]), + .CON(\con$159 ), + .SN(\sn$160 ) + ); + AO21x1_ASAP7_75t_R \U$360 ( + .A1(\$signal$72 ), + .A2(\g_new$469 ), + .B(\$signal$297 ), + .Y(\g_new$493 ) + ); + AO21x1_ASAP7_75t_R \U$361 ( + .A1(\$signal$76 ), + .A2(\g_new$458 ), + .B(\$signal$299 ), + .Y(\g_new$494 ) + ); + AO21x1_ASAP7_75t_R \U$362 ( + .A1(\$signal$80 ), + .A2(\g_new$470 ), + .B(\$signal$301 ), + .Y(\g_new$495 ) + ); + AO21x1_ASAP7_75t_R \U$363 ( + .A1(\$signal$84 ), + .A2(\g_new$453 ), + .B(\$signal$303 ), + .Y(\g_new$496 ) + ); + AO21x1_ASAP7_75t_R \U$364 ( + .A1(\$signal$88 ), + .A2(\g_new$471 ), + .B(\$signal$305 ), + .Y(\g_new$497 ) + ); + AO21x1_ASAP7_75t_R \U$365 ( + .A1(\$signal$92 ), + .A2(\g_new$459 ), + .B(\$signal$307 ), + .Y(\g_new$498 ) + ); + AO21x1_ASAP7_75t_R \U$366 ( + .A1(\$signal$96 ), + .A2(\g_new$472 ), + .B(\$signal$309 ), + .Y(\g_new$499 ) + ); + AO21x1_ASAP7_75t_R \U$367 ( + .A1(\$signal$100 ), + .A2(\g_new$451 ), + .B(\$signal$311 ), + .Y(\g_new$500 ) + ); + AO21x1_ASAP7_75t_R \U$368 ( + .A1(\$signal$104 ), + .A2(\g_new$473 ), + .B(\$signal$313 ), + .Y(\g_new$501 ) + ); + AO21x1_ASAP7_75t_R \U$369 ( + .A1(\$signal$108 ), + .A2(\g_new$460 ), + .B(\$signal$315 ), + .Y(\g_new$502 ) + ); + INVx1_ASAP7_75t_R \U$37 ( + .A(\con$159 ), + .Y(\$signal$275 ) + ); + AO21x1_ASAP7_75t_R \U$370 ( + .A1(\$signal$112 ), + .A2(\g_new$474 ), + .B(\$signal$317 ), + .Y(\g_new$503 ) + ); + AO21x1_ASAP7_75t_R \U$371 ( + .A1(\$signal$116 ), + .A2(\g_new$454 ), + .B(\$signal$319 ), + .Y(\g_new$504 ) + ); + AO21x1_ASAP7_75t_R \U$372 ( + .A1(\$signal$120 ), + .A2(\g_new$475 ), + .B(\$signal$321 ), + .Y(\g_new$505 ) + ); + AO21x1_ASAP7_75t_R \U$373 ( + .A1(\$signal$124 ), + .A2(\g_new$461 ), + .B(\$signal$323 ), + .Y(\g_new$506 ) + ); + AO21x1_ASAP7_75t_R \U$374 ( + .A1(\$signal$128 ), + .A2(\g_new$476 ), + .B(\$signal$325 ), + .Y(\g_new$507 ) + ); + XOR2x1_ASAP7_75t_R \U$375 ( + .A(\$signal ), + .B(1'h0), + .Y(\$3 ) + ); + XOR2x1_ASAP7_75t_R \U$376 ( + .A(\$signal$6 ), + .B(\$signal$263 ), + .Y(\$4 ) + ); + XOR2x1_ASAP7_75t_R \U$377 ( + .A(\$signal$8 ), + .B(g_new), + .Y(\$5 ) + ); + XOR2x1_ASAP7_75t_R \U$378 ( + .A(\$signal$10 ), + .B(\g_new$477 ), + .Y(\$6 ) + ); + XOR2x1_ASAP7_75t_R \U$379 ( + .A(\$signal$12 ), + .B(\g_new$393 ), + .Y(\$7 ) + ); + INVx1_ASAP7_75t_R \U$38 ( + .A(\sn$160 ), + .Y(\$signal$28 ) + ); + XOR2x1_ASAP7_75t_R \U$380 ( + .A(\$signal$14 ), + .B(\g_new$478 ), + .Y(\$8 ) + ); + XOR2x1_ASAP7_75t_R \U$381 ( + .A(\$signal$16 ), + .B(\g_new$462 ), + .Y(\$9 ) + ); + XOR2x1_ASAP7_75t_R \U$382 ( + .A(\$signal$18 ), + .B(\g_new$479 ), + .Y(\$10 ) + ); + XOR2x1_ASAP7_75t_R \U$383 ( + .A(\$signal$20 ), + .B(\g_new$425 ), + .Y(\$11 ) + ); + XOR2x1_ASAP7_75t_R \U$384 ( + .A(\$signal$22 ), + .B(\g_new$480 ), + .Y(\$12 ) + ); + XOR2x1_ASAP7_75t_R \U$385 ( + .A(\$signal$24 ), + .B(\g_new$463 ), + .Y(\$13 ) + ); + XOR2x1_ASAP7_75t_R \U$386 ( + .A(\$signal$26 ), + .B(\g_new$481 ), + .Y(\$14 ) + ); + XOR2x1_ASAP7_75t_R \U$387 ( + .A(\$signal$28 ), + .B(\g_new$455 ), + .Y(\$15 ) + ); + XOR2x1_ASAP7_75t_R \U$388 ( + .A(\$signal$30 ), + .B(\g_new$482 ), + .Y(\$16 ) + ); + XOR2x1_ASAP7_75t_R \U$389 ( + .A(\$signal$32 ), + .B(\g_new$464 ), + .Y(\$17 ) + ); + HAxp5_ASAP7_75t_R \U$39 ( + .A(a[13]), + .B(b[13]), + .CON(\con$161 ), + .SN(\sn$162 ) + ); + XOR2x1_ASAP7_75t_R \U$390 ( + .A(\$signal$34 ), + .B(\g_new$483 ), + .Y(\$18 ) + ); + XOR2x1_ASAP7_75t_R \U$391 ( + .A(\$signal$36 ), + .B(\g_new$441 ), + .Y(\$19 ) + ); + XOR2x1_ASAP7_75t_R \U$392 ( + .A(\$signal$38 ), + .B(\g_new$484 ), + .Y(\$20 ) + ); + XOR2x1_ASAP7_75t_R \U$393 ( + .A(\$signal$40 ), + .B(\g_new$465 ), + .Y(\$21 ) + ); + XOR2x1_ASAP7_75t_R \U$394 ( + .A(\$signal$42 ), + .B(\g_new$485 ), + .Y(\$22 ) + ); + XOR2x1_ASAP7_75t_R \U$395 ( + .A(\$signal$44 ), + .B(\g_new$456 ), + .Y(\$23 ) + ); + XOR2x1_ASAP7_75t_R \U$396 ( + .A(\$signal$46 ), + .B(\g_new$486 ), + .Y(\$24 ) + ); + XOR2x1_ASAP7_75t_R \U$397 ( + .A(\$signal$48 ), + .B(\g_new$466 ), + .Y(\$25 ) + ); + XOR2x1_ASAP7_75t_R \U$398 ( + .A(\$signal$50 ), + .B(\g_new$487 ), + .Y(\$26 ) + ); + XOR2x1_ASAP7_75t_R \U$399 ( + .A(\$signal$52 ), + .B(\g_new$452 ), + .Y(\$27 ) + ); + INVx1_ASAP7_75t_R \U$4 ( + .A(\con$137 ), + .Y(\$signal$264 ) + ); + INVx1_ASAP7_75t_R \U$40 ( + .A(\con$161 ), + .Y(\$signal$276 ) + ); + XOR2x1_ASAP7_75t_R \U$400 ( + .A(\$signal$54 ), + .B(\g_new$488 ), + .Y(\$28 ) + ); + XOR2x1_ASAP7_75t_R \U$401 ( + .A(\$signal$56 ), + .B(\g_new$467 ), + .Y(\$29 ) + ); + XOR2x1_ASAP7_75t_R \U$402 ( + .A(\$signal$58 ), + .B(\g_new$489 ), + .Y(\$30 ) + ); + XOR2x1_ASAP7_75t_R \U$403 ( + .A(\$signal$60 ), + .B(\g_new$457 ), + .Y(\$31 ) + ); + XOR2x1_ASAP7_75t_R \U$404 ( + .A(\$signal$62 ), + .B(\g_new$490 ), + .Y(\$32 ) + ); + XOR2x1_ASAP7_75t_R \U$405 ( + .A(\$signal$64 ), + .B(\g_new$468 ), + .Y(\$33 ) + ); + XOR2x1_ASAP7_75t_R \U$406 ( + .A(\$signal$66 ), + .B(\g_new$491 ), + .Y(\$34 ) + ); + XOR2x1_ASAP7_75t_R \U$407 ( + .A(\$signal$68 ), + .B(\g_new$449 ), + .Y(\$35 ) + ); + XOR2x1_ASAP7_75t_R \U$408 ( + .A(\$signal$70 ), + .B(\g_new$492 ), + .Y(\$36 ) + ); + XOR2x1_ASAP7_75t_R \U$409 ( + .A(\$signal$72 ), + .B(\g_new$469 ), + .Y(\$37 ) + ); + INVx1_ASAP7_75t_R \U$41 ( + .A(\sn$162 ), + .Y(\$signal$30 ) + ); + XOR2x1_ASAP7_75t_R \U$410 ( + .A(\$signal$74 ), + .B(\g_new$493 ), + .Y(\$38 ) + ); + XOR2x1_ASAP7_75t_R \U$411 ( + .A(\$signal$76 ), + .B(\g_new$458 ), + .Y(\$39 ) + ); + XOR2x1_ASAP7_75t_R \U$412 ( + .A(\$signal$78 ), + .B(\g_new$494 ), + .Y(\$40 ) + ); + XOR2x1_ASAP7_75t_R \U$413 ( + .A(\$signal$80 ), + .B(\g_new$470 ), + .Y(\$41 ) + ); + XOR2x1_ASAP7_75t_R \U$414 ( + .A(\$signal$82 ), + .B(\g_new$495 ), + .Y(\$42 ) + ); + XOR2x1_ASAP7_75t_R \U$415 ( + .A(\$signal$84 ), + .B(\g_new$453 ), + .Y(\$43 ) + ); + XOR2x1_ASAP7_75t_R \U$416 ( + .A(\$signal$86 ), + .B(\g_new$496 ), + .Y(\$44 ) + ); + XOR2x1_ASAP7_75t_R \U$417 ( + .A(\$signal$88 ), + .B(\g_new$471 ), + .Y(\$45 ) + ); + XOR2x1_ASAP7_75t_R \U$418 ( + .A(\$signal$90 ), + .B(\g_new$497 ), + .Y(\$46 ) + ); + XOR2x1_ASAP7_75t_R \U$419 ( + .A(\$signal$92 ), + .B(\g_new$459 ), + .Y(\$47 ) + ); + HAxp5_ASAP7_75t_R \U$42 ( + .A(a[14]), + .B(b[14]), + .CON(\con$163 ), + .SN(\sn$164 ) + ); + XOR2x1_ASAP7_75t_R \U$420 ( + .A(\$signal$94 ), + .B(\g_new$498 ), + .Y(\$48 ) + ); + XOR2x1_ASAP7_75t_R \U$421 ( + .A(\$signal$96 ), + .B(\g_new$472 ), + .Y(\$49 ) + ); + XOR2x1_ASAP7_75t_R \U$422 ( + .A(\$signal$98 ), + .B(\g_new$499 ), + .Y(\$50 ) + ); + XOR2x1_ASAP7_75t_R \U$423 ( + .A(\$signal$100 ), + .B(\g_new$451 ), + .Y(\$51 ) + ); + XOR2x1_ASAP7_75t_R \U$424 ( + .A(\$signal$102 ), + .B(\g_new$500 ), + .Y(\$52 ) + ); + XOR2x1_ASAP7_75t_R \U$425 ( + .A(\$signal$104 ), + .B(\g_new$473 ), + .Y(\$53 ) + ); + XOR2x1_ASAP7_75t_R \U$426 ( + .A(\$signal$106 ), + .B(\g_new$501 ), + .Y(\$54 ) + ); + XOR2x1_ASAP7_75t_R \U$427 ( + .A(\$signal$108 ), + .B(\g_new$460 ), + .Y(\$55 ) + ); + XOR2x1_ASAP7_75t_R \U$428 ( + .A(\$signal$110 ), + .B(\g_new$502 ), + .Y(\$56 ) + ); + XOR2x1_ASAP7_75t_R \U$429 ( + .A(\$signal$112 ), + .B(\g_new$474 ), + .Y(\$57 ) + ); + INVx1_ASAP7_75t_R \U$43 ( + .A(\con$163 ), + .Y(\$signal$277 ) + ); + XOR2x1_ASAP7_75t_R \U$430 ( + .A(\$signal$114 ), + .B(\g_new$503 ), + .Y(\$58 ) + ); + XOR2x1_ASAP7_75t_R \U$431 ( + .A(\$signal$116 ), + .B(\g_new$454 ), + .Y(\$59 ) + ); + XOR2x1_ASAP7_75t_R \U$432 ( + .A(\$signal$118 ), + .B(\g_new$504 ), + .Y(\$60 ) + ); + XOR2x1_ASAP7_75t_R \U$433 ( + .A(\$signal$120 ), + .B(\g_new$475 ), + .Y(\$61 ) + ); + XOR2x1_ASAP7_75t_R \U$434 ( + .A(\$signal$122 ), + .B(\g_new$505 ), + .Y(\$62 ) + ); + XOR2x1_ASAP7_75t_R \U$435 ( + .A(\$signal$124 ), + .B(\g_new$461 ), + .Y(\$63 ) + ); + XOR2x1_ASAP7_75t_R \U$436 ( + .A(\$signal$126 ), + .B(\g_new$506 ), + .Y(\$64 ) + ); + XOR2x1_ASAP7_75t_R \U$437 ( + .A(\$signal$128 ), + .B(\g_new$476 ), + .Y(\$65 ) + ); + XOR2x1_ASAP7_75t_R \U$438 ( + .A(\$signal$130 ), + .B(\g_new$507 ), + .Y(\$66 ) + ); + INVx1_ASAP7_75t_R \U$44 ( + .A(\sn$164 ), + .Y(\$signal$32 ) + ); + HAxp5_ASAP7_75t_R \U$45 ( + .A(a[15]), + .B(b[15]), + .CON(\con$165 ), + .SN(\sn$166 ) + ); + INVx1_ASAP7_75t_R \U$46 ( + .A(\con$165 ), + .Y(\$signal$278 ) + ); + INVx1_ASAP7_75t_R \U$47 ( + .A(\sn$166 ), + .Y(\$signal$34 ) + ); + HAxp5_ASAP7_75t_R \U$48 ( + .A(a[16]), + .B(b[16]), + .CON(\con$167 ), + .SN(\sn$168 ) + ); + INVx1_ASAP7_75t_R \U$49 ( + .A(\con$167 ), + .Y(\$signal$279 ) + ); + INVx1_ASAP7_75t_R \U$5 ( + .A(\sn$138 ), + .Y(\$signal$6 ) + ); + INVx1_ASAP7_75t_R \U$50 ( + .A(\sn$168 ), + .Y(\$signal$36 ) + ); + HAxp5_ASAP7_75t_R \U$51 ( + .A(a[17]), + .B(b[17]), + .CON(\con$169 ), + .SN(\sn$170 ) + ); + INVx1_ASAP7_75t_R \U$52 ( + .A(\con$169 ), + .Y(\$signal$280 ) + ); + INVx1_ASAP7_75t_R \U$53 ( + .A(\sn$170 ), + .Y(\$signal$38 ) + ); + HAxp5_ASAP7_75t_R \U$54 ( + .A(a[18]), + .B(b[18]), + .CON(\con$171 ), + .SN(\sn$172 ) + ); + INVx1_ASAP7_75t_R \U$55 ( + .A(\con$171 ), + .Y(\$signal$281 ) + ); + INVx1_ASAP7_75t_R \U$56 ( + .A(\sn$172 ), + .Y(\$signal$40 ) + ); + HAxp5_ASAP7_75t_R \U$57 ( + .A(a[19]), + .B(b[19]), + .CON(\con$173 ), + .SN(\sn$174 ) + ); + INVx1_ASAP7_75t_R \U$58 ( + .A(\con$173 ), + .Y(\$signal$282 ) + ); + INVx1_ASAP7_75t_R \U$59 ( + .A(\sn$174 ), + .Y(\$signal$42 ) + ); + HAxp5_ASAP7_75t_R \U$6 ( + .A(a[2]), + .B(b[2]), + .CON(\con$139 ), + .SN(\sn$140 ) + ); + HAxp5_ASAP7_75t_R \U$60 ( + .A(a[20]), + .B(b[20]), + .CON(\con$175 ), + .SN(\sn$176 ) + ); + INVx1_ASAP7_75t_R \U$61 ( + .A(\con$175 ), + .Y(\$signal$283 ) + ); + INVx1_ASAP7_75t_R \U$62 ( + .A(\sn$176 ), + .Y(\$signal$44 ) + ); + HAxp5_ASAP7_75t_R \U$63 ( + .A(a[21]), + .B(b[21]), + .CON(\con$177 ), + .SN(\sn$178 ) + ); + INVx1_ASAP7_75t_R \U$64 ( + .A(\con$177 ), + .Y(\$signal$284 ) + ); + INVx1_ASAP7_75t_R \U$65 ( + .A(\sn$178 ), + .Y(\$signal$46 ) + ); + HAxp5_ASAP7_75t_R \U$66 ( + .A(a[22]), + .B(b[22]), + .CON(\con$179 ), + .SN(\sn$180 ) + ); + INVx1_ASAP7_75t_R \U$67 ( + .A(\con$179 ), + .Y(\$signal$285 ) + ); + INVx1_ASAP7_75t_R \U$68 ( + .A(\sn$180 ), + .Y(\$signal$48 ) + ); + HAxp5_ASAP7_75t_R \U$69 ( + .A(a[23]), + .B(b[23]), + .CON(\con$181 ), + .SN(\sn$182 ) + ); + INVx1_ASAP7_75t_R \U$7 ( + .A(\con$139 ), + .Y(\$signal$265 ) + ); + INVx1_ASAP7_75t_R \U$70 ( + .A(\con$181 ), + .Y(\$signal$286 ) + ); + INVx1_ASAP7_75t_R \U$71 ( + .A(\sn$182 ), + .Y(\$signal$50 ) + ); + HAxp5_ASAP7_75t_R \U$72 ( + .A(a[24]), + .B(b[24]), + .CON(\con$183 ), + .SN(\sn$184 ) + ); + INVx1_ASAP7_75t_R \U$73 ( + .A(\con$183 ), + .Y(\$signal$287 ) + ); + INVx1_ASAP7_75t_R \U$74 ( + .A(\sn$184 ), + .Y(\$signal$52 ) + ); + HAxp5_ASAP7_75t_R \U$75 ( + .A(a[25]), + .B(b[25]), + .CON(\con$185 ), + .SN(\sn$186 ) + ); + INVx1_ASAP7_75t_R \U$76 ( + .A(\con$185 ), + .Y(\$signal$288 ) + ); + INVx1_ASAP7_75t_R \U$77 ( + .A(\sn$186 ), + .Y(\$signal$54 ) + ); + HAxp5_ASAP7_75t_R \U$78 ( + .A(a[26]), + .B(b[26]), + .CON(\con$187 ), + .SN(\sn$188 ) + ); + INVx1_ASAP7_75t_R \U$79 ( + .A(\con$187 ), + .Y(\$signal$289 ) + ); + INVx1_ASAP7_75t_R \U$8 ( + .A(\sn$140 ), + .Y(\$signal$8 ) + ); + INVx1_ASAP7_75t_R \U$80 ( + .A(\sn$188 ), + .Y(\$signal$56 ) + ); + HAxp5_ASAP7_75t_R \U$81 ( + .A(a[27]), + .B(b[27]), + .CON(\con$189 ), + .SN(\sn$190 ) + ); + INVx1_ASAP7_75t_R \U$82 ( + .A(\con$189 ), + .Y(\$signal$290 ) + ); + INVx1_ASAP7_75t_R \U$83 ( + .A(\sn$190 ), + .Y(\$signal$58 ) + ); + HAxp5_ASAP7_75t_R \U$84 ( + .A(a[28]), + .B(b[28]), + .CON(\con$191 ), + .SN(\sn$192 ) + ); + INVx1_ASAP7_75t_R \U$85 ( + .A(\con$191 ), + .Y(\$signal$291 ) + ); + INVx1_ASAP7_75t_R \U$86 ( + .A(\sn$192 ), + .Y(\$signal$60 ) + ); + HAxp5_ASAP7_75t_R \U$87 ( + .A(a[29]), + .B(b[29]), + .CON(\con$193 ), + .SN(\sn$194 ) + ); + INVx1_ASAP7_75t_R \U$88 ( + .A(\con$193 ), + .Y(\$signal$292 ) + ); + INVx1_ASAP7_75t_R \U$89 ( + .A(\sn$194 ), + .Y(\$signal$62 ) + ); + HAxp5_ASAP7_75t_R \U$9 ( + .A(a[3]), + .B(b[3]), + .CON(\con$141 ), + .SN(\sn$142 ) + ); + HAxp5_ASAP7_75t_R \U$90 ( + .A(a[30]), + .B(b[30]), + .CON(\con$195 ), + .SN(\sn$196 ) + ); + INVx1_ASAP7_75t_R \U$91 ( + .A(\con$195 ), + .Y(\$signal$293 ) + ); + INVx1_ASAP7_75t_R \U$92 ( + .A(\sn$196 ), + .Y(\$signal$64 ) + ); + HAxp5_ASAP7_75t_R \U$93 ( + .A(a[31]), + .B(b[31]), + .CON(\con$197 ), + .SN(\sn$198 ) + ); + INVx1_ASAP7_75t_R \U$94 ( + .A(\con$197 ), + .Y(\$signal$294 ) + ); + INVx1_ASAP7_75t_R \U$95 ( + .A(\sn$198 ), + .Y(\$signal$66 ) + ); + HAxp5_ASAP7_75t_R \U$96 ( + .A(a[32]), + .B(b[32]), + .CON(\con$199 ), + .SN(\sn$200 ) + ); + INVx1_ASAP7_75t_R \U$97 ( + .A(\con$199 ), + .Y(\$signal$295 ) + ); + INVx1_ASAP7_75t_R \U$98 ( + .A(\sn$200 ), + .Y(\$signal$68 ) + ); + HAxp5_ASAP7_75t_R \U$99 ( + .A(a[33]), + .B(b[33]), + .CON(\con$201 ), + .SN(\sn$202 ) + ); + assign \a$1 = a; + assign \b$3 = b; + assign \$signal$5 = \$signal ; + assign \$signal$7 = \$signal$6 ; + assign \$signal$9 = \$signal$8 ; + assign \$signal$11 = \$signal$10 ; + assign \$signal$13 = \$signal$12 ; + assign \$signal$15 = \$signal$14 ; + assign \$signal$17 = \$signal$16 ; + assign \$signal$19 = \$signal$18 ; + assign \$signal$21 = \$signal$20 ; + assign \$signal$23 = \$signal$22 ; + assign \$signal$25 = \$signal$24 ; + assign \$signal$27 = \$signal$26 ; + assign \$signal$29 = \$signal$28 ; + assign \$signal$31 = \$signal$30 ; + assign \$signal$33 = \$signal$32 ; + assign \$signal$35 = \$signal$34 ; + assign \$signal$37 = \$signal$36 ; + assign \$signal$39 = \$signal$38 ; + assign \$signal$41 = \$signal$40 ; + assign \$signal$43 = \$signal$42 ; + assign \$signal$45 = \$signal$44 ; + assign \$signal$47 = \$signal$46 ; + assign \$signal$49 = \$signal$48 ; + assign \$signal$51 = \$signal$50 ; + assign \$signal$53 = \$signal$52 ; + assign \$signal$55 = \$signal$54 ; + assign \$signal$57 = \$signal$56 ; + assign \$signal$59 = \$signal$58 ; + assign \$signal$61 = \$signal$60 ; + assign \$signal$63 = \$signal$62 ; + assign \$signal$65 = \$signal$64 ; + assign \$signal$67 = \$signal$66 ; + assign \$signal$69 = \$signal$68 ; + assign \$signal$71 = \$signal$70 ; + assign \$signal$73 = \$signal$72 ; + assign \$signal$75 = \$signal$74 ; + assign \$signal$77 = \$signal$76 ; + assign \$signal$79 = \$signal$78 ; + assign \$signal$81 = \$signal$80 ; + assign \$signal$83 = \$signal$82 ; + assign \$signal$85 = \$signal$84 ; + assign \$signal$87 = \$signal$86 ; + assign \$signal$89 = \$signal$88 ; + assign \$signal$91 = \$signal$90 ; + assign \$signal$93 = \$signal$92 ; + assign \$signal$95 = \$signal$94 ; + assign \$signal$97 = \$signal$96 ; + assign \$signal$99 = \$signal$98 ; + assign \$signal$101 = \$signal$100 ; + assign \$signal$103 = \$signal$102 ; + assign \$signal$105 = \$signal$104 ; + assign \$signal$107 = \$signal$106 ; + assign \$signal$109 = \$signal$108 ; + assign \$signal$111 = \$signal$110 ; + assign \$signal$113 = \$signal$112 ; + assign \$signal$115 = \$signal$114 ; + assign \$signal$117 = \$signal$116 ; + assign \$signal$119 = \$signal$118 ; + assign \$signal$121 = \$signal$120 ; + assign \$signal$123 = \$signal$122 ; + assign \$signal$125 = \$signal$124 ; + assign \$signal$127 = \$signal$126 ; + assign \$signal$129 = \$signal$128 ; + assign \$signal$131 = \$signal$130 ; + assign o2 = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign o = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign \o$134 = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign \port$901$0 = \$3 ; + assign \port$902$0 = \$4 ; + assign \port$903$0 = \$5 ; + assign \port$904$0 = \$6 ; + assign \port$905$0 = \$7 ; + assign \port$906$0 = \$8 ; + assign \port$907$0 = \$9 ; + assign \port$908$0 = \$10 ; + assign \port$909$0 = \$11 ; + assign \port$910$0 = \$12 ; + assign \port$911$0 = \$13 ; + assign \port$912$0 = \$14 ; + assign \port$913$0 = \$15 ; + assign \port$914$0 = \$16 ; + assign \port$915$0 = \$17 ; + assign \port$916$0 = \$18 ; + assign \port$917$0 = \$19 ; + assign \port$918$0 = \$20 ; + assign \port$919$0 = \$21 ; + assign \port$920$0 = \$22 ; + assign \port$921$0 = \$23 ; + assign \port$922$0 = \$24 ; + assign \port$923$0 = \$25 ; + assign \port$924$0 = \$26 ; + assign \port$925$0 = \$27 ; + assign \port$926$0 = \$28 ; + assign \port$927$0 = \$29 ; + assign \port$928$0 = \$30 ; + assign \port$929$0 = \$31 ; + assign \port$930$0 = \$32 ; + assign \port$931$0 = \$33 ; + assign \port$932$0 = \$34 ; + assign \port$933$0 = \$35 ; + assign \port$934$0 = \$36 ; + assign \port$935$0 = \$37 ; + assign \port$936$0 = \$38 ; + assign \port$937$0 = \$39 ; + assign \port$938$0 = \$40 ; + assign \port$939$0 = \$41 ; + assign \port$940$0 = \$42 ; + assign \port$941$0 = \$43 ; + assign \port$942$0 = \$44 ; + assign \port$943$0 = \$45 ; + assign \port$944$0 = \$46 ; + assign \port$945$0 = \$47 ; + assign \port$946$0 = \$48 ; + assign \port$947$0 = \$49 ; + assign \port$948$0 = \$50 ; + assign \port$949$0 = \$51 ; + assign \port$950$0 = \$52 ; + assign \port$951$0 = \$53 ; + assign \port$952$0 = \$54 ; + assign \port$953$0 = \$55 ; + assign \port$954$0 = \$56 ; + assign \port$955$0 = \$57 ; + assign \port$956$0 = \$58 ; + assign \port$957$0 = \$59 ; + assign \port$958$0 = \$60 ; + assign \port$959$0 = \$61 ; + assign \port$960$0 = \$62 ; + assign \port$961$0 = \$63 ; + assign \port$962$0 = \$64 ; + assign \port$963$0 = \$65 ; + assign \port$964$0 = \$66 ; +endmodule diff --git a/flow/designs/src/mock-array/simulate.cpp b/flow/designs/src/mock-array/simulate.cpp index e5a2e78b53..7b2fba8945 100644 --- a/flow/designs/src/mock-array/simulate.cpp +++ b/flow/designs/src/mock-array/simulate.cpp @@ -80,7 +80,7 @@ int main(int argc, char** argv) { for (int k = 0; k < 2; k++) { top->eval(); - vcd->dump(tick++); + vcd->dump(tick++ * 125); top->clock = !top->clock; } } diff --git a/flow/designs/src/mock-array/src/main/resources/multiplier.v b/flow/designs/src/mock-array/src/main/resources/multiplier.v new file mode 100644 index 0000000000..03c2f06e14 --- /dev/null +++ b/flow/designs/src/mock-array/src/main/resources/multiplier.v @@ -0,0 +1,24740 @@ +/* Generated by Amaranth Yosys 0.40 (PyPI ver 0.40.0.0.post102, git sha1 a1bb0255d) */ + +module multiplier(b, clk, rst, o, a); + wire \$1 ; + wire \$10 ; + wire \$100 ; + wire \$101 ; + wire \$102 ; + wire \$103 ; + wire \$104 ; + wire \$105 ; + wire \$106 ; + wire \$107 ; + wire \$108 ; + wire \$109 ; + wire \$11 ; + wire \$110 ; + wire \$111 ; + wire \$112 ; + wire \$113 ; + wire \$114 ; + wire \$115 ; + wire \$116 ; + wire \$117 ; + wire \$12 ; + wire \$13 ; + wire \$14 ; + wire \$15 ; + wire \$16 ; + wire \$17 ; + wire \$18 ; + wire \$19 ; + wire \$2 ; + wire \$20 ; + wire \$21 ; + wire \$22 ; + wire \$23 ; + wire \$24 ; + wire \$25 ; + wire \$26 ; + wire \$27 ; + wire \$28 ; + wire \$29 ; + wire \$3 ; + wire \$30 ; + wire \$31 ; + wire \$32 ; + wire \$33 ; + wire \$34 ; + wire \$35 ; + wire \$36 ; + wire \$37 ; + wire \$38 ; + wire \$39 ; + wire \$4 ; + wire \$40 ; + wire \$41 ; + wire \$42 ; + wire \$43 ; + wire \$44 ; + wire \$45 ; + wire \$46 ; + wire \$47 ; + wire \$48 ; + wire \$49 ; + wire \$5 ; + wire \$50 ; + wire \$51 ; + wire \$52 ; + wire \$53 ; + wire \$54 ; + wire \$55 ; + wire \$56 ; + wire \$57 ; + wire \$58 ; + wire \$59 ; + wire \$6 ; + wire \$60 ; + wire \$61 ; + wire \$62 ; + wire \$63 ; + wire \$64 ; + wire \$65 ; + wire \$66 ; + wire \$67 ; + wire \$68 ; + wire \$69 ; + wire \$7 ; + wire \$70 ; + wire \$71 ; + wire \$72 ; + wire \$73 ; + wire \$74 ; + wire \$75 ; + wire \$76 ; + wire \$77 ; + wire \$78 ; + wire \$79 ; + wire \$8 ; + wire \$80 ; + wire \$81 ; + wire \$82 ; + wire \$83 ; + wire \$84 ; + wire \$85 ; + wire \$86 ; + wire \$87 ; + wire \$88 ; + wire \$89 ; + wire \$9 ; + wire \$90 ; + wire \$91 ; + wire \$92 ; + wire \$93 ; + wire \$94 ; + wire \$95 ; + wire \$96 ; + wire \$97 ; + wire \$98 ; + wire \$99 ; + input [31:0] a; + wire [31:0] a; + (* init = 64'h0000000000000000 *) + wire [63:0] \a$1971 ; + reg [31:0] a_registered = 32'd0; + input [31:0] b; + wire [31:0] b; + (* init = 64'h0000000000000000 *) + wire [63:0] \b$1972 ; + reg [31:0] b_registered = 32'd0; + wire booth_b0_m0; + wire booth_b0_m1; + wire booth_b0_m10; + wire booth_b0_m11; + wire booth_b0_m12; + wire booth_b0_m13; + wire booth_b0_m14; + wire booth_b0_m15; + wire booth_b0_m16; + wire booth_b0_m17; + wire booth_b0_m18; + wire booth_b0_m19; + wire booth_b0_m2; + wire booth_b0_m20; + wire booth_b0_m21; + wire booth_b0_m22; + wire booth_b0_m23; + wire booth_b0_m24; + wire booth_b0_m25; + wire booth_b0_m26; + wire booth_b0_m27; + wire booth_b0_m28; + wire booth_b0_m29; + wire booth_b0_m3; + wire booth_b0_m30; + wire booth_b0_m31; + wire booth_b0_m32; + wire booth_b0_m4; + wire booth_b0_m5; + wire booth_b0_m6; + wire booth_b0_m7; + wire booth_b0_m8; + wire booth_b0_m9; + wire booth_b10_m0; + wire booth_b10_m1; + wire booth_b10_m10; + wire booth_b10_m11; + wire booth_b10_m12; + wire booth_b10_m13; + wire booth_b10_m14; + wire booth_b10_m15; + wire booth_b10_m16; + wire booth_b10_m17; + wire booth_b10_m18; + wire booth_b10_m19; + wire booth_b10_m2; + wire booth_b10_m20; + wire booth_b10_m21; + wire booth_b10_m22; + wire booth_b10_m23; + wire booth_b10_m24; + wire booth_b10_m25; + wire booth_b10_m26; + wire booth_b10_m27; + wire booth_b10_m28; + wire booth_b10_m29; + wire booth_b10_m3; + wire booth_b10_m30; + wire booth_b10_m31; + wire booth_b10_m32; + wire booth_b10_m4; + wire booth_b10_m5; + wire booth_b10_m6; + wire booth_b10_m7; + wire booth_b10_m8; + wire booth_b10_m9; + wire booth_b12_m0; + wire booth_b12_m1; + wire booth_b12_m10; + wire booth_b12_m11; + wire booth_b12_m12; + wire booth_b12_m13; + wire booth_b12_m14; + wire booth_b12_m15; + wire booth_b12_m16; + wire booth_b12_m17; + wire booth_b12_m18; + wire booth_b12_m19; + wire booth_b12_m2; + wire booth_b12_m20; + wire booth_b12_m21; + wire booth_b12_m22; + wire booth_b12_m23; + wire booth_b12_m24; + wire booth_b12_m25; + wire booth_b12_m26; + wire booth_b12_m27; + wire booth_b12_m28; + wire booth_b12_m29; + wire booth_b12_m3; + wire booth_b12_m30; + wire booth_b12_m31; + wire booth_b12_m32; + wire booth_b12_m4; + wire booth_b12_m5; + wire booth_b12_m6; + wire booth_b12_m7; + wire booth_b12_m8; + wire booth_b12_m9; + wire booth_b14_m0; + wire booth_b14_m1; + wire booth_b14_m10; + wire booth_b14_m11; + wire booth_b14_m12; + wire booth_b14_m13; + wire booth_b14_m14; + wire booth_b14_m15; + wire booth_b14_m16; + wire booth_b14_m17; + wire booth_b14_m18; + wire booth_b14_m19; + wire booth_b14_m2; + wire booth_b14_m20; + wire booth_b14_m21; + wire booth_b14_m22; + wire booth_b14_m23; + wire booth_b14_m24; + wire booth_b14_m25; + wire booth_b14_m26; + wire booth_b14_m27; + wire booth_b14_m28; + wire booth_b14_m29; + wire booth_b14_m3; + wire booth_b14_m30; + wire booth_b14_m31; + wire booth_b14_m32; + wire booth_b14_m4; + wire booth_b14_m5; + wire booth_b14_m6; + wire booth_b14_m7; + wire booth_b14_m8; + wire booth_b14_m9; + wire booth_b16_m0; + wire booth_b16_m1; + wire booth_b16_m10; + wire booth_b16_m11; + wire booth_b16_m12; + wire booth_b16_m13; + wire booth_b16_m14; + wire booth_b16_m15; + wire booth_b16_m16; + wire booth_b16_m17; + wire booth_b16_m18; + wire booth_b16_m19; + wire booth_b16_m2; + wire booth_b16_m20; + wire booth_b16_m21; + wire booth_b16_m22; + wire booth_b16_m23; + wire booth_b16_m24; + wire booth_b16_m25; + wire booth_b16_m26; + wire booth_b16_m27; + wire booth_b16_m28; + wire booth_b16_m29; + wire booth_b16_m3; + wire booth_b16_m30; + wire booth_b16_m31; + wire booth_b16_m32; + wire booth_b16_m4; + wire booth_b16_m5; + wire booth_b16_m6; + wire booth_b16_m7; + wire booth_b16_m8; + wire booth_b16_m9; + wire booth_b18_m0; + wire booth_b18_m1; + wire booth_b18_m10; + wire booth_b18_m11; + wire booth_b18_m12; + wire booth_b18_m13; + wire booth_b18_m14; + wire booth_b18_m15; + wire booth_b18_m16; + wire booth_b18_m17; + wire booth_b18_m18; + wire booth_b18_m19; + wire booth_b18_m2; + wire booth_b18_m20; + wire booth_b18_m21; + wire booth_b18_m22; + wire booth_b18_m23; + wire booth_b18_m24; + wire booth_b18_m25; + wire booth_b18_m26; + wire booth_b18_m27; + wire booth_b18_m28; + wire booth_b18_m29; + wire booth_b18_m3; + wire booth_b18_m30; + wire booth_b18_m31; + wire booth_b18_m32; + wire booth_b18_m4; + wire booth_b18_m5; + wire booth_b18_m6; + wire booth_b18_m7; + wire booth_b18_m8; + wire booth_b18_m9; + wire booth_b20_m0; + wire booth_b20_m1; + wire booth_b20_m10; + wire booth_b20_m11; + wire booth_b20_m12; + wire booth_b20_m13; + wire booth_b20_m14; + wire booth_b20_m15; + wire booth_b20_m16; + wire booth_b20_m17; + wire booth_b20_m18; + wire booth_b20_m19; + wire booth_b20_m2; + wire booth_b20_m20; + wire booth_b20_m21; + wire booth_b20_m22; + wire booth_b20_m23; + wire booth_b20_m24; + wire booth_b20_m25; + wire booth_b20_m26; + wire booth_b20_m27; + wire booth_b20_m28; + wire booth_b20_m29; + wire booth_b20_m3; + wire booth_b20_m30; + wire booth_b20_m31; + wire booth_b20_m32; + wire booth_b20_m4; + wire booth_b20_m5; + wire booth_b20_m6; + wire booth_b20_m7; + wire booth_b20_m8; + wire booth_b20_m9; + wire booth_b22_m0; + wire booth_b22_m1; + wire booth_b22_m10; + wire booth_b22_m11; + wire booth_b22_m12; + wire booth_b22_m13; + wire booth_b22_m14; + wire booth_b22_m15; + wire booth_b22_m16; + wire booth_b22_m17; + wire booth_b22_m18; + wire booth_b22_m19; + wire booth_b22_m2; + wire booth_b22_m20; + wire booth_b22_m21; + wire booth_b22_m22; + wire booth_b22_m23; + wire booth_b22_m24; + wire booth_b22_m25; + wire booth_b22_m26; + wire booth_b22_m27; + wire booth_b22_m28; + wire booth_b22_m29; + wire booth_b22_m3; + wire booth_b22_m30; + wire booth_b22_m31; + wire booth_b22_m32; + wire booth_b22_m4; + wire booth_b22_m5; + wire booth_b22_m6; + wire booth_b22_m7; + wire booth_b22_m8; + wire booth_b22_m9; + wire booth_b24_m0; + wire booth_b24_m1; + wire booth_b24_m10; + wire booth_b24_m11; + wire booth_b24_m12; + wire booth_b24_m13; + wire booth_b24_m14; + wire booth_b24_m15; + wire booth_b24_m16; + wire booth_b24_m17; + wire booth_b24_m18; + wire booth_b24_m19; + wire booth_b24_m2; + wire booth_b24_m20; + wire booth_b24_m21; + wire booth_b24_m22; + wire booth_b24_m23; + wire booth_b24_m24; + wire booth_b24_m25; + wire booth_b24_m26; + wire booth_b24_m27; + wire booth_b24_m28; + wire booth_b24_m29; + wire booth_b24_m3; + wire booth_b24_m30; + wire booth_b24_m31; + wire booth_b24_m32; + wire booth_b24_m4; + wire booth_b24_m5; + wire booth_b24_m6; + wire booth_b24_m7; + wire booth_b24_m8; + wire booth_b24_m9; + wire booth_b26_m0; + wire booth_b26_m1; + wire booth_b26_m10; + wire booth_b26_m11; + wire booth_b26_m12; + wire booth_b26_m13; + wire booth_b26_m14; + wire booth_b26_m15; + wire booth_b26_m16; + wire booth_b26_m17; + wire booth_b26_m18; + wire booth_b26_m19; + wire booth_b26_m2; + wire booth_b26_m20; + wire booth_b26_m21; + wire booth_b26_m22; + wire booth_b26_m23; + wire booth_b26_m24; + wire booth_b26_m25; + wire booth_b26_m26; + wire booth_b26_m27; + wire booth_b26_m28; + wire booth_b26_m29; + wire booth_b26_m3; + wire booth_b26_m30; + wire booth_b26_m31; + wire booth_b26_m32; + wire booth_b26_m4; + wire booth_b26_m5; + wire booth_b26_m6; + wire booth_b26_m7; + wire booth_b26_m8; + wire booth_b26_m9; + wire booth_b28_m0; + wire booth_b28_m1; + wire booth_b28_m10; + wire booth_b28_m11; + wire booth_b28_m12; + wire booth_b28_m13; + wire booth_b28_m14; + wire booth_b28_m15; + wire booth_b28_m16; + wire booth_b28_m17; + wire booth_b28_m18; + wire booth_b28_m19; + wire booth_b28_m2; + wire booth_b28_m20; + wire booth_b28_m21; + wire booth_b28_m22; + wire booth_b28_m23; + wire booth_b28_m24; + wire booth_b28_m25; + wire booth_b28_m26; + wire booth_b28_m27; + wire booth_b28_m28; + wire booth_b28_m29; + wire booth_b28_m3; + wire booth_b28_m30; + wire booth_b28_m31; + wire booth_b28_m32; + wire booth_b28_m4; + wire booth_b28_m5; + wire booth_b28_m6; + wire booth_b28_m7; + wire booth_b28_m8; + wire booth_b28_m9; + wire booth_b2_m0; + wire booth_b2_m1; + wire booth_b2_m10; + wire booth_b2_m11; + wire booth_b2_m12; + wire booth_b2_m13; + wire booth_b2_m14; + wire booth_b2_m15; + wire booth_b2_m16; + wire booth_b2_m17; + wire booth_b2_m18; + wire booth_b2_m19; + wire booth_b2_m2; + wire booth_b2_m20; + wire booth_b2_m21; + wire booth_b2_m22; + wire booth_b2_m23; + wire booth_b2_m24; + wire booth_b2_m25; + wire booth_b2_m26; + wire booth_b2_m27; + wire booth_b2_m28; + wire booth_b2_m29; + wire booth_b2_m3; + wire booth_b2_m30; + wire booth_b2_m31; + wire booth_b2_m32; + wire booth_b2_m4; + wire booth_b2_m5; + wire booth_b2_m6; + wire booth_b2_m7; + wire booth_b2_m8; + wire booth_b2_m9; + wire booth_b30_m0; + wire booth_b30_m1; + wire booth_b30_m10; + wire booth_b30_m11; + wire booth_b30_m12; + wire booth_b30_m13; + wire booth_b30_m14; + wire booth_b30_m15; + wire booth_b30_m16; + wire booth_b30_m17; + wire booth_b30_m18; + wire booth_b30_m19; + wire booth_b30_m2; + wire booth_b30_m20; + wire booth_b30_m21; + wire booth_b30_m22; + wire booth_b30_m23; + wire booth_b30_m24; + wire booth_b30_m25; + wire booth_b30_m26; + wire booth_b30_m27; + wire booth_b30_m28; + wire booth_b30_m29; + wire booth_b30_m3; + wire booth_b30_m30; + wire booth_b30_m31; + wire booth_b30_m32; + wire booth_b30_m4; + wire booth_b30_m5; + wire booth_b30_m6; + wire booth_b30_m7; + wire booth_b30_m8; + wire booth_b30_m9; + wire booth_b32_m0; + wire booth_b32_m1; + wire booth_b32_m10; + wire booth_b32_m11; + wire booth_b32_m12; + wire booth_b32_m13; + wire booth_b32_m14; + wire booth_b32_m15; + wire booth_b32_m16; + wire booth_b32_m17; + wire booth_b32_m18; + wire booth_b32_m19; + wire booth_b32_m2; + wire booth_b32_m20; + wire booth_b32_m21; + wire booth_b32_m22; + wire booth_b32_m23; + wire booth_b32_m24; + wire booth_b32_m25; + wire booth_b32_m26; + wire booth_b32_m27; + wire booth_b32_m28; + wire booth_b32_m29; + wire booth_b32_m3; + wire booth_b32_m30; + wire booth_b32_m31; + wire booth_b32_m32; + wire booth_b32_m4; + wire booth_b32_m5; + wire booth_b32_m6; + wire booth_b32_m7; + wire booth_b32_m8; + wire booth_b32_m9; + wire booth_b4_m0; + wire booth_b4_m1; + wire booth_b4_m10; + wire booth_b4_m11; + wire booth_b4_m12; + wire booth_b4_m13; + wire booth_b4_m14; + wire booth_b4_m15; + wire booth_b4_m16; + wire booth_b4_m17; + wire booth_b4_m18; + wire booth_b4_m19; + wire booth_b4_m2; + wire booth_b4_m20; + wire booth_b4_m21; + wire booth_b4_m22; + wire booth_b4_m23; + wire booth_b4_m24; + wire booth_b4_m25; + wire booth_b4_m26; + wire booth_b4_m27; + wire booth_b4_m28; + wire booth_b4_m29; + wire booth_b4_m3; + wire booth_b4_m30; + wire booth_b4_m31; + wire booth_b4_m32; + wire booth_b4_m4; + wire booth_b4_m5; + wire booth_b4_m6; + wire booth_b4_m7; + wire booth_b4_m8; + wire booth_b4_m9; + wire booth_b6_m0; + wire booth_b6_m1; + wire booth_b6_m10; + wire booth_b6_m11; + wire booth_b6_m12; + wire booth_b6_m13; + wire booth_b6_m14; + wire booth_b6_m15; + wire booth_b6_m16; + wire booth_b6_m17; + wire booth_b6_m18; + wire booth_b6_m19; + wire booth_b6_m2; + wire booth_b6_m20; + wire booth_b6_m21; + wire booth_b6_m22; + wire booth_b6_m23; + wire booth_b6_m24; + wire booth_b6_m25; + wire booth_b6_m26; + wire booth_b6_m27; + wire booth_b6_m28; + wire booth_b6_m29; + wire booth_b6_m3; + wire booth_b6_m30; + wire booth_b6_m31; + wire booth_b6_m32; + wire booth_b6_m4; + wire booth_b6_m5; + wire booth_b6_m6; + wire booth_b6_m7; + wire booth_b6_m8; + wire booth_b6_m9; + wire booth_b8_m0; + wire booth_b8_m1; + wire booth_b8_m10; + wire booth_b8_m11; + wire booth_b8_m12; + wire booth_b8_m13; + wire booth_b8_m14; + wire booth_b8_m15; + wire booth_b8_m16; + wire booth_b8_m17; + wire booth_b8_m18; + wire booth_b8_m19; + wire booth_b8_m2; + wire booth_b8_m20; + wire booth_b8_m21; + wire booth_b8_m22; + wire booth_b8_m23; + wire booth_b8_m24; + wire booth_b8_m25; + wire booth_b8_m26; + wire booth_b8_m27; + wire booth_b8_m28; + wire booth_b8_m29; + wire booth_b8_m3; + wire booth_b8_m30; + wire booth_b8_m31; + wire booth_b8_m32; + wire booth_b8_m4; + wire booth_b8_m5; + wire booth_b8_m6; + wire booth_b8_m7; + wire booth_b8_m8; + wire booth_b8_m9; + wire [2:0] booth_block0; + wire [1:0] booth_block0_mand0; + wire [1:0] booth_block0_mand1; + wire [1:0] booth_block0_mand10; + wire [1:0] booth_block0_mand11; + wire [1:0] booth_block0_mand12; + wire [1:0] booth_block0_mand13; + wire [1:0] booth_block0_mand14; + wire [1:0] booth_block0_mand15; + wire [1:0] booth_block0_mand16; + wire [1:0] booth_block0_mand17; + wire [1:0] booth_block0_mand18; + wire [1:0] booth_block0_mand19; + wire [1:0] booth_block0_mand2; + wire [1:0] booth_block0_mand20; + wire [1:0] booth_block0_mand21; + wire [1:0] booth_block0_mand22; + wire [1:0] booth_block0_mand23; + wire [1:0] booth_block0_mand24; + wire [1:0] booth_block0_mand25; + wire [1:0] booth_block0_mand26; + wire [1:0] booth_block0_mand27; + wire [1:0] booth_block0_mand28; + wire [1:0] booth_block0_mand29; + wire [1:0] booth_block0_mand3; + wire [1:0] booth_block0_mand30; + wire [1:0] booth_block0_mand31; + wire [1:0] booth_block0_mand32; + wire [1:0] booth_block0_mand4; + wire [1:0] booth_block0_mand5; + wire [1:0] booth_block0_mand6; + wire [1:0] booth_block0_mand7; + wire [1:0] booth_block0_mand8; + wire [1:0] booth_block0_mand9; + wire [1:0] booth_block0_sel; + wire booth_block0_sign; + wire [2:0] booth_block10; + wire [1:0] booth_block10_mand0; + wire [1:0] booth_block10_mand1; + wire [1:0] booth_block10_mand10; + wire [1:0] booth_block10_mand11; + wire [1:0] booth_block10_mand12; + wire [1:0] booth_block10_mand13; + wire [1:0] booth_block10_mand14; + wire [1:0] booth_block10_mand15; + wire [1:0] booth_block10_mand16; + wire [1:0] booth_block10_mand17; + wire [1:0] booth_block10_mand18; + wire [1:0] booth_block10_mand19; + wire [1:0] booth_block10_mand2; + wire [1:0] booth_block10_mand20; + wire [1:0] booth_block10_mand21; + wire [1:0] booth_block10_mand22; + wire [1:0] booth_block10_mand23; + wire [1:0] booth_block10_mand24; + wire [1:0] booth_block10_mand25; + wire [1:0] booth_block10_mand26; + wire [1:0] booth_block10_mand27; + wire [1:0] booth_block10_mand28; + wire [1:0] booth_block10_mand29; + wire [1:0] booth_block10_mand3; + wire [1:0] booth_block10_mand30; + wire [1:0] booth_block10_mand31; + wire [1:0] booth_block10_mand32; + wire [1:0] booth_block10_mand4; + wire [1:0] booth_block10_mand5; + wire [1:0] booth_block10_mand6; + wire [1:0] booth_block10_mand7; + wire [1:0] booth_block10_mand8; + wire [1:0] booth_block10_mand9; + wire [1:0] booth_block10_sel; + wire booth_block10_sign; + wire [2:0] booth_block12; + wire [1:0] booth_block12_mand0; + wire [1:0] booth_block12_mand1; + wire [1:0] booth_block12_mand10; + wire [1:0] booth_block12_mand11; + wire [1:0] booth_block12_mand12; + wire [1:0] booth_block12_mand13; + wire [1:0] booth_block12_mand14; + wire [1:0] booth_block12_mand15; + wire [1:0] booth_block12_mand16; + wire [1:0] booth_block12_mand17; + wire [1:0] booth_block12_mand18; + wire [1:0] booth_block12_mand19; + wire [1:0] booth_block12_mand2; + wire [1:0] booth_block12_mand20; + wire [1:0] booth_block12_mand21; + wire [1:0] booth_block12_mand22; + wire [1:0] booth_block12_mand23; + wire [1:0] booth_block12_mand24; + wire [1:0] booth_block12_mand25; + wire [1:0] booth_block12_mand26; + wire [1:0] booth_block12_mand27; + wire [1:0] booth_block12_mand28; + wire [1:0] booth_block12_mand29; + wire [1:0] booth_block12_mand3; + wire [1:0] booth_block12_mand30; + wire [1:0] booth_block12_mand31; + wire [1:0] booth_block12_mand32; + wire [1:0] booth_block12_mand4; + wire [1:0] booth_block12_mand5; + wire [1:0] booth_block12_mand6; + wire [1:0] booth_block12_mand7; + wire [1:0] booth_block12_mand8; + wire [1:0] booth_block12_mand9; + wire [1:0] booth_block12_sel; + wire booth_block12_sign; + wire [2:0] booth_block14; + wire [1:0] booth_block14_mand0; + wire [1:0] booth_block14_mand1; + wire [1:0] booth_block14_mand10; + wire [1:0] booth_block14_mand11; + wire [1:0] booth_block14_mand12; + wire [1:0] booth_block14_mand13; + wire [1:0] booth_block14_mand14; + wire [1:0] booth_block14_mand15; + wire [1:0] booth_block14_mand16; + wire [1:0] booth_block14_mand17; + wire [1:0] booth_block14_mand18; + wire [1:0] booth_block14_mand19; + wire [1:0] booth_block14_mand2; + wire [1:0] booth_block14_mand20; + wire [1:0] booth_block14_mand21; + wire [1:0] booth_block14_mand22; + wire [1:0] booth_block14_mand23; + wire [1:0] booth_block14_mand24; + wire [1:0] booth_block14_mand25; + wire [1:0] booth_block14_mand26; + wire [1:0] booth_block14_mand27; + wire [1:0] booth_block14_mand28; + wire [1:0] booth_block14_mand29; + wire [1:0] booth_block14_mand3; + wire [1:0] booth_block14_mand30; + wire [1:0] booth_block14_mand31; + wire [1:0] booth_block14_mand32; + wire [1:0] booth_block14_mand4; + wire [1:0] booth_block14_mand5; + wire [1:0] booth_block14_mand6; + wire [1:0] booth_block14_mand7; + wire [1:0] booth_block14_mand8; + wire [1:0] booth_block14_mand9; + wire [1:0] booth_block14_sel; + wire booth_block14_sign; + wire [2:0] booth_block16; + wire [1:0] booth_block16_mand0; + wire [1:0] booth_block16_mand1; + wire [1:0] booth_block16_mand10; + wire [1:0] booth_block16_mand11; + wire [1:0] booth_block16_mand12; + wire [1:0] booth_block16_mand13; + wire [1:0] booth_block16_mand14; + wire [1:0] booth_block16_mand15; + wire [1:0] booth_block16_mand16; + wire [1:0] booth_block16_mand17; + wire [1:0] booth_block16_mand18; + wire [1:0] booth_block16_mand19; + wire [1:0] booth_block16_mand2; + wire [1:0] booth_block16_mand20; + wire [1:0] booth_block16_mand21; + wire [1:0] booth_block16_mand22; + wire [1:0] booth_block16_mand23; + wire [1:0] booth_block16_mand24; + wire [1:0] booth_block16_mand25; + wire [1:0] booth_block16_mand26; + wire [1:0] booth_block16_mand27; + wire [1:0] booth_block16_mand28; + wire [1:0] booth_block16_mand29; + wire [1:0] booth_block16_mand3; + wire [1:0] booth_block16_mand30; + wire [1:0] booth_block16_mand31; + wire [1:0] booth_block16_mand32; + wire [1:0] booth_block16_mand4; + wire [1:0] booth_block16_mand5; + wire [1:0] booth_block16_mand6; + wire [1:0] booth_block16_mand7; + wire [1:0] booth_block16_mand8; + wire [1:0] booth_block16_mand9; + wire [1:0] booth_block16_sel; + wire booth_block16_sign; + wire [2:0] booth_block18; + wire [1:0] booth_block18_mand0; + wire [1:0] booth_block18_mand1; + wire [1:0] booth_block18_mand10; + wire [1:0] booth_block18_mand11; + wire [1:0] booth_block18_mand12; + wire [1:0] booth_block18_mand13; + wire [1:0] booth_block18_mand14; + wire [1:0] booth_block18_mand15; + wire [1:0] booth_block18_mand16; + wire [1:0] booth_block18_mand17; + wire [1:0] booth_block18_mand18; + wire [1:0] booth_block18_mand19; + wire [1:0] booth_block18_mand2; + wire [1:0] booth_block18_mand20; + wire [1:0] booth_block18_mand21; + wire [1:0] booth_block18_mand22; + wire [1:0] booth_block18_mand23; + wire [1:0] booth_block18_mand24; + wire [1:0] booth_block18_mand25; + wire [1:0] booth_block18_mand26; + wire [1:0] booth_block18_mand27; + wire [1:0] booth_block18_mand28; + wire [1:0] booth_block18_mand29; + wire [1:0] booth_block18_mand3; + wire [1:0] booth_block18_mand30; + wire [1:0] booth_block18_mand31; + wire [1:0] booth_block18_mand32; + wire [1:0] booth_block18_mand4; + wire [1:0] booth_block18_mand5; + wire [1:0] booth_block18_mand6; + wire [1:0] booth_block18_mand7; + wire [1:0] booth_block18_mand8; + wire [1:0] booth_block18_mand9; + wire [1:0] booth_block18_sel; + wire booth_block18_sign; + wire [2:0] booth_block2; + wire [2:0] booth_block20; + wire [1:0] booth_block20_mand0; + wire [1:0] booth_block20_mand1; + wire [1:0] booth_block20_mand10; + wire [1:0] booth_block20_mand11; + wire [1:0] booth_block20_mand12; + wire [1:0] booth_block20_mand13; + wire [1:0] booth_block20_mand14; + wire [1:0] booth_block20_mand15; + wire [1:0] booth_block20_mand16; + wire [1:0] booth_block20_mand17; + wire [1:0] booth_block20_mand18; + wire [1:0] booth_block20_mand19; + wire [1:0] booth_block20_mand2; + wire [1:0] booth_block20_mand20; + wire [1:0] booth_block20_mand21; + wire [1:0] booth_block20_mand22; + wire [1:0] booth_block20_mand23; + wire [1:0] booth_block20_mand24; + wire [1:0] booth_block20_mand25; + wire [1:0] booth_block20_mand26; + wire [1:0] booth_block20_mand27; + wire [1:0] booth_block20_mand28; + wire [1:0] booth_block20_mand29; + wire [1:0] booth_block20_mand3; + wire [1:0] booth_block20_mand30; + wire [1:0] booth_block20_mand31; + wire [1:0] booth_block20_mand32; + wire [1:0] booth_block20_mand4; + wire [1:0] booth_block20_mand5; + wire [1:0] booth_block20_mand6; + wire [1:0] booth_block20_mand7; + wire [1:0] booth_block20_mand8; + wire [1:0] booth_block20_mand9; + wire [1:0] booth_block20_sel; + wire booth_block20_sign; + wire [2:0] booth_block22; + wire [1:0] booth_block22_mand0; + wire [1:0] booth_block22_mand1; + wire [1:0] booth_block22_mand10; + wire [1:0] booth_block22_mand11; + wire [1:0] booth_block22_mand12; + wire [1:0] booth_block22_mand13; + wire [1:0] booth_block22_mand14; + wire [1:0] booth_block22_mand15; + wire [1:0] booth_block22_mand16; + wire [1:0] booth_block22_mand17; + wire [1:0] booth_block22_mand18; + wire [1:0] booth_block22_mand19; + wire [1:0] booth_block22_mand2; + wire [1:0] booth_block22_mand20; + wire [1:0] booth_block22_mand21; + wire [1:0] booth_block22_mand22; + wire [1:0] booth_block22_mand23; + wire [1:0] booth_block22_mand24; + wire [1:0] booth_block22_mand25; + wire [1:0] booth_block22_mand26; + wire [1:0] booth_block22_mand27; + wire [1:0] booth_block22_mand28; + wire [1:0] booth_block22_mand29; + wire [1:0] booth_block22_mand3; + wire [1:0] booth_block22_mand30; + wire [1:0] booth_block22_mand31; + wire [1:0] booth_block22_mand32; + wire [1:0] booth_block22_mand4; + wire [1:0] booth_block22_mand5; + wire [1:0] booth_block22_mand6; + wire [1:0] booth_block22_mand7; + wire [1:0] booth_block22_mand8; + wire [1:0] booth_block22_mand9; + wire [1:0] booth_block22_sel; + wire booth_block22_sign; + wire [2:0] booth_block24; + wire [1:0] booth_block24_mand0; + wire [1:0] booth_block24_mand1; + wire [1:0] booth_block24_mand10; + wire [1:0] booth_block24_mand11; + wire [1:0] booth_block24_mand12; + wire [1:0] booth_block24_mand13; + wire [1:0] booth_block24_mand14; + wire [1:0] booth_block24_mand15; + wire [1:0] booth_block24_mand16; + wire [1:0] booth_block24_mand17; + wire [1:0] booth_block24_mand18; + wire [1:0] booth_block24_mand19; + wire [1:0] booth_block24_mand2; + wire [1:0] booth_block24_mand20; + wire [1:0] booth_block24_mand21; + wire [1:0] booth_block24_mand22; + wire [1:0] booth_block24_mand23; + wire [1:0] booth_block24_mand24; + wire [1:0] booth_block24_mand25; + wire [1:0] booth_block24_mand26; + wire [1:0] booth_block24_mand27; + wire [1:0] booth_block24_mand28; + wire [1:0] booth_block24_mand29; + wire [1:0] booth_block24_mand3; + wire [1:0] booth_block24_mand30; + wire [1:0] booth_block24_mand31; + wire [1:0] booth_block24_mand32; + wire [1:0] booth_block24_mand4; + wire [1:0] booth_block24_mand5; + wire [1:0] booth_block24_mand6; + wire [1:0] booth_block24_mand7; + wire [1:0] booth_block24_mand8; + wire [1:0] booth_block24_mand9; + wire [1:0] booth_block24_sel; + wire booth_block24_sign; + wire [2:0] booth_block26; + wire [1:0] booth_block26_mand0; + wire [1:0] booth_block26_mand1; + wire [1:0] booth_block26_mand10; + wire [1:0] booth_block26_mand11; + wire [1:0] booth_block26_mand12; + wire [1:0] booth_block26_mand13; + wire [1:0] booth_block26_mand14; + wire [1:0] booth_block26_mand15; + wire [1:0] booth_block26_mand16; + wire [1:0] booth_block26_mand17; + wire [1:0] booth_block26_mand18; + wire [1:0] booth_block26_mand19; + wire [1:0] booth_block26_mand2; + wire [1:0] booth_block26_mand20; + wire [1:0] booth_block26_mand21; + wire [1:0] booth_block26_mand22; + wire [1:0] booth_block26_mand23; + wire [1:0] booth_block26_mand24; + wire [1:0] booth_block26_mand25; + wire [1:0] booth_block26_mand26; + wire [1:0] booth_block26_mand27; + wire [1:0] booth_block26_mand28; + wire [1:0] booth_block26_mand29; + wire [1:0] booth_block26_mand3; + wire [1:0] booth_block26_mand30; + wire [1:0] booth_block26_mand31; + wire [1:0] booth_block26_mand32; + wire [1:0] booth_block26_mand4; + wire [1:0] booth_block26_mand5; + wire [1:0] booth_block26_mand6; + wire [1:0] booth_block26_mand7; + wire [1:0] booth_block26_mand8; + wire [1:0] booth_block26_mand9; + wire [1:0] booth_block26_sel; + wire booth_block26_sign; + wire [2:0] booth_block28; + wire [1:0] booth_block28_mand0; + wire [1:0] booth_block28_mand1; + wire [1:0] booth_block28_mand10; + wire [1:0] booth_block28_mand11; + wire [1:0] booth_block28_mand12; + wire [1:0] booth_block28_mand13; + wire [1:0] booth_block28_mand14; + wire [1:0] booth_block28_mand15; + wire [1:0] booth_block28_mand16; + wire [1:0] booth_block28_mand17; + wire [1:0] booth_block28_mand18; + wire [1:0] booth_block28_mand19; + wire [1:0] booth_block28_mand2; + wire [1:0] booth_block28_mand20; + wire [1:0] booth_block28_mand21; + wire [1:0] booth_block28_mand22; + wire [1:0] booth_block28_mand23; + wire [1:0] booth_block28_mand24; + wire [1:0] booth_block28_mand25; + wire [1:0] booth_block28_mand26; + wire [1:0] booth_block28_mand27; + wire [1:0] booth_block28_mand28; + wire [1:0] booth_block28_mand29; + wire [1:0] booth_block28_mand3; + wire [1:0] booth_block28_mand30; + wire [1:0] booth_block28_mand31; + wire [1:0] booth_block28_mand32; + wire [1:0] booth_block28_mand4; + wire [1:0] booth_block28_mand5; + wire [1:0] booth_block28_mand6; + wire [1:0] booth_block28_mand7; + wire [1:0] booth_block28_mand8; + wire [1:0] booth_block28_mand9; + wire [1:0] booth_block28_sel; + wire booth_block28_sign; + wire [1:0] booth_block2_mand0; + wire [1:0] booth_block2_mand1; + wire [1:0] booth_block2_mand10; + wire [1:0] booth_block2_mand11; + wire [1:0] booth_block2_mand12; + wire [1:0] booth_block2_mand13; + wire [1:0] booth_block2_mand14; + wire [1:0] booth_block2_mand15; + wire [1:0] booth_block2_mand16; + wire [1:0] booth_block2_mand17; + wire [1:0] booth_block2_mand18; + wire [1:0] booth_block2_mand19; + wire [1:0] booth_block2_mand2; + wire [1:0] booth_block2_mand20; + wire [1:0] booth_block2_mand21; + wire [1:0] booth_block2_mand22; + wire [1:0] booth_block2_mand23; + wire [1:0] booth_block2_mand24; + wire [1:0] booth_block2_mand25; + wire [1:0] booth_block2_mand26; + wire [1:0] booth_block2_mand27; + wire [1:0] booth_block2_mand28; + wire [1:0] booth_block2_mand29; + wire [1:0] booth_block2_mand3; + wire [1:0] booth_block2_mand30; + wire [1:0] booth_block2_mand31; + wire [1:0] booth_block2_mand32; + wire [1:0] booth_block2_mand4; + wire [1:0] booth_block2_mand5; + wire [1:0] booth_block2_mand6; + wire [1:0] booth_block2_mand7; + wire [1:0] booth_block2_mand8; + wire [1:0] booth_block2_mand9; + wire [1:0] booth_block2_sel; + wire booth_block2_sign; + wire [2:0] booth_block30; + wire [1:0] booth_block30_mand0; + wire [1:0] booth_block30_mand1; + wire [1:0] booth_block30_mand10; + wire [1:0] booth_block30_mand11; + wire [1:0] booth_block30_mand12; + wire [1:0] booth_block30_mand13; + wire [1:0] booth_block30_mand14; + wire [1:0] booth_block30_mand15; + wire [1:0] booth_block30_mand16; + wire [1:0] booth_block30_mand17; + wire [1:0] booth_block30_mand18; + wire [1:0] booth_block30_mand19; + wire [1:0] booth_block30_mand2; + wire [1:0] booth_block30_mand20; + wire [1:0] booth_block30_mand21; + wire [1:0] booth_block30_mand22; + wire [1:0] booth_block30_mand23; + wire [1:0] booth_block30_mand24; + wire [1:0] booth_block30_mand25; + wire [1:0] booth_block30_mand26; + wire [1:0] booth_block30_mand27; + wire [1:0] booth_block30_mand28; + wire [1:0] booth_block30_mand29; + wire [1:0] booth_block30_mand3; + wire [1:0] booth_block30_mand30; + wire [1:0] booth_block30_mand31; + wire [1:0] booth_block30_mand32; + wire [1:0] booth_block30_mand4; + wire [1:0] booth_block30_mand5; + wire [1:0] booth_block30_mand6; + wire [1:0] booth_block30_mand7; + wire [1:0] booth_block30_mand8; + wire [1:0] booth_block30_mand9; + wire [1:0] booth_block30_sel; + wire booth_block30_sign; + wire [2:0] booth_block32; + wire [1:0] booth_block32_mand0; + wire [1:0] booth_block32_mand1; + wire [1:0] booth_block32_mand10; + wire [1:0] booth_block32_mand11; + wire [1:0] booth_block32_mand12; + wire [1:0] booth_block32_mand13; + wire [1:0] booth_block32_mand14; + wire [1:0] booth_block32_mand15; + wire [1:0] booth_block32_mand16; + wire [1:0] booth_block32_mand17; + wire [1:0] booth_block32_mand18; + wire [1:0] booth_block32_mand19; + wire [1:0] booth_block32_mand2; + wire [1:0] booth_block32_mand20; + wire [1:0] booth_block32_mand21; + wire [1:0] booth_block32_mand22; + wire [1:0] booth_block32_mand23; + wire [1:0] booth_block32_mand24; + wire [1:0] booth_block32_mand25; + wire [1:0] booth_block32_mand26; + wire [1:0] booth_block32_mand27; + wire [1:0] booth_block32_mand28; + wire [1:0] booth_block32_mand29; + wire [1:0] booth_block32_mand3; + wire [1:0] booth_block32_mand30; + wire [1:0] booth_block32_mand31; + wire [1:0] booth_block32_mand32; + wire [1:0] booth_block32_mand4; + wire [1:0] booth_block32_mand5; + wire [1:0] booth_block32_mand6; + wire [1:0] booth_block32_mand7; + wire [1:0] booth_block32_mand8; + wire [1:0] booth_block32_mand9; + wire [1:0] booth_block32_sel; + wire booth_block32_sign; + wire [2:0] booth_block4; + wire [1:0] booth_block4_mand0; + wire [1:0] booth_block4_mand1; + wire [1:0] booth_block4_mand10; + wire [1:0] booth_block4_mand11; + wire [1:0] booth_block4_mand12; + wire [1:0] booth_block4_mand13; + wire [1:0] booth_block4_mand14; + wire [1:0] booth_block4_mand15; + wire [1:0] booth_block4_mand16; + wire [1:0] booth_block4_mand17; + wire [1:0] booth_block4_mand18; + wire [1:0] booth_block4_mand19; + wire [1:0] booth_block4_mand2; + wire [1:0] booth_block4_mand20; + wire [1:0] booth_block4_mand21; + wire [1:0] booth_block4_mand22; + wire [1:0] booth_block4_mand23; + wire [1:0] booth_block4_mand24; + wire [1:0] booth_block4_mand25; + wire [1:0] booth_block4_mand26; + wire [1:0] booth_block4_mand27; + wire [1:0] booth_block4_mand28; + wire [1:0] booth_block4_mand29; + wire [1:0] booth_block4_mand3; + wire [1:0] booth_block4_mand30; + wire [1:0] booth_block4_mand31; + wire [1:0] booth_block4_mand32; + wire [1:0] booth_block4_mand4; + wire [1:0] booth_block4_mand5; + wire [1:0] booth_block4_mand6; + wire [1:0] booth_block4_mand7; + wire [1:0] booth_block4_mand8; + wire [1:0] booth_block4_mand9; + wire [1:0] booth_block4_sel; + wire booth_block4_sign; + wire [2:0] booth_block6; + wire [1:0] booth_block6_mand0; + wire [1:0] booth_block6_mand1; + wire [1:0] booth_block6_mand10; + wire [1:0] booth_block6_mand11; + wire [1:0] booth_block6_mand12; + wire [1:0] booth_block6_mand13; + wire [1:0] booth_block6_mand14; + wire [1:0] booth_block6_mand15; + wire [1:0] booth_block6_mand16; + wire [1:0] booth_block6_mand17; + wire [1:0] booth_block6_mand18; + wire [1:0] booth_block6_mand19; + wire [1:0] booth_block6_mand2; + wire [1:0] booth_block6_mand20; + wire [1:0] booth_block6_mand21; + wire [1:0] booth_block6_mand22; + wire [1:0] booth_block6_mand23; + wire [1:0] booth_block6_mand24; + wire [1:0] booth_block6_mand25; + wire [1:0] booth_block6_mand26; + wire [1:0] booth_block6_mand27; + wire [1:0] booth_block6_mand28; + wire [1:0] booth_block6_mand29; + wire [1:0] booth_block6_mand3; + wire [1:0] booth_block6_mand30; + wire [1:0] booth_block6_mand31; + wire [1:0] booth_block6_mand32; + wire [1:0] booth_block6_mand4; + wire [1:0] booth_block6_mand5; + wire [1:0] booth_block6_mand6; + wire [1:0] booth_block6_mand7; + wire [1:0] booth_block6_mand8; + wire [1:0] booth_block6_mand9; + wire [1:0] booth_block6_sel; + wire booth_block6_sign; + wire [2:0] booth_block8; + wire [1:0] booth_block8_mand0; + wire [1:0] booth_block8_mand1; + wire [1:0] booth_block8_mand10; + wire [1:0] booth_block8_mand11; + wire [1:0] booth_block8_mand12; + wire [1:0] booth_block8_mand13; + wire [1:0] booth_block8_mand14; + wire [1:0] booth_block8_mand15; + wire [1:0] booth_block8_mand16; + wire [1:0] booth_block8_mand17; + wire [1:0] booth_block8_mand18; + wire [1:0] booth_block8_mand19; + wire [1:0] booth_block8_mand2; + wire [1:0] booth_block8_mand20; + wire [1:0] booth_block8_mand21; + wire [1:0] booth_block8_mand22; + wire [1:0] booth_block8_mand23; + wire [1:0] booth_block8_mand24; + wire [1:0] booth_block8_mand25; + wire [1:0] booth_block8_mand26; + wire [1:0] booth_block8_mand27; + wire [1:0] booth_block8_mand28; + wire [1:0] booth_block8_mand29; + wire [1:0] booth_block8_mand3; + wire [1:0] booth_block8_mand30; + wire [1:0] booth_block8_mand31; + wire [1:0] booth_block8_mand32; + wire [1:0] booth_block8_mand4; + wire [1:0] booth_block8_mand5; + wire [1:0] booth_block8_mand6; + wire [1:0] booth_block8_mand7; + wire [1:0] booth_block8_mand8; + wire [1:0] booth_block8_mand9; + wire [1:0] booth_block8_sel; + wire booth_block8_sign; + wire c; + wire \c$1197 ; + wire \c$1198 ; + wire \c$1199 ; + wire \c$1200 ; + wire \c$1201 ; + wire \c$1202 ; + wire \c$1203 ; + wire \c$1204 ; + wire \c$1205 ; + wire \c$1206 ; + wire \c$1207 ; + wire \c$1208 ; + wire \c$1209 ; + wire \c$1210 ; + wire \c$1211 ; + wire \c$1212 ; + wire \c$1213 ; + wire \c$1214 ; + wire \c$1215 ; + wire \c$1216 ; + wire \c$1217 ; + wire \c$1218 ; + wire \c$1219 ; + wire \c$1220 ; + wire \c$1221 ; + wire \c$1222 ; + wire \c$1223 ; + wire \c$1224 ; + wire \c$1225 ; + wire \c$1226 ; + wire \c$1227 ; + wire \c$1228 ; + wire \c$1229 ; + wire \c$1230 ; + wire \c$1231 ; + wire \c$1232 ; + wire \c$1233 ; + wire \c$1234 ; + wire \c$1235 ; + wire \c$1236 ; + wire \c$1237 ; + wire \c$1238 ; + wire \c$1239 ; + wire \c$1240 ; + wire \c$1241 ; + wire \c$1242 ; + wire \c$1243 ; + wire \c$1244 ; + wire \c$1245 ; + wire \c$1246 ; + wire \c$1247 ; + wire \c$1248 ; + wire \c$1249 ; + wire \c$1250 ; + wire \c$1251 ; + wire \c$1252 ; + wire \c$1253 ; + wire \c$1254 ; + wire \c$1255 ; + wire \c$1256 ; + wire \c$1257 ; + wire \c$2553 ; + wire \c$2557 ; + wire \c$2561 ; + wire \c$2565 ; + wire \c$2569 ; + wire \c$2573 ; + wire \c$2577 ; + wire \c$2581 ; + wire \c$2585 ; + wire \c$2589 ; + wire \c$2593 ; + wire \c$2597 ; + wire \c$2601 ; + wire \c$2605 ; + wire \c$2609 ; + wire \c$2613 ; + wire \c$2617 ; + wire \c$2621 ; + wire \c$2625 ; + wire \c$2629 ; + wire \c$2633 ; + wire \c$2637 ; + wire \c$2641 ; + wire \c$2645 ; + wire \c$2649 ; + wire \c$2653 ; + wire \c$2657 ; + wire \c$2661 ; + wire \c$2665 ; + wire \c$2669 ; + wire \c$2673 ; + wire \c$2677 ; + wire \c$2681 ; + wire \c$2685 ; + wire \c$2689 ; + wire \c$2693 ; + wire \c$2697 ; + wire \c$2701 ; + wire \c$2705 ; + wire \c$2709 ; + wire \c$2713 ; + wire \c$2717 ; + wire \c$2721 ; + wire \c$2725 ; + wire \c$2729 ; + wire \c$2733 ; + wire \c$2737 ; + wire \c$2741 ; + wire \c$2745 ; + wire \c$2749 ; + wire \c$2753 ; + wire \c$2757 ; + wire \c$2761 ; + wire \c$2765 ; + wire \c$2769 ; + wire \c$2773 ; + wire \c$2777 ; + wire \c$2781 ; + wire \c$2785 ; + wire \c$2789 ; + wire \c$2793 ; + wire \c$2797 ; + wire \c$2801 ; + wire \c$2805 ; + wire \c$2809 ; + wire \c$2813 ; + wire \c$2817 ; + wire \c$2821 ; + wire \c$2825 ; + wire \c$2829 ; + wire \c$2833 ; + wire \c$2837 ; + wire \c$2841 ; + wire \c$2845 ; + wire \c$2849 ; + wire \c$2853 ; + wire \c$2857 ; + wire \c$2861 ; + wire \c$2865 ; + wire \c$2869 ; + wire \c$2873 ; + wire \c$2877 ; + wire \c$2881 ; + wire \c$2885 ; + wire \c$2889 ; + wire \c$2893 ; + wire \c$2897 ; + wire \c$2901 ; + wire \c$2905 ; + wire \c$2909 ; + wire \c$2913 ; + wire \c$2917 ; + wire \c$2921 ; + wire \c$2925 ; + wire \c$2929 ; + wire \c$2933 ; + wire \c$2937 ; + wire \c$2941 ; + wire \c$2945 ; + wire \c$2949 ; + wire \c$2953 ; + wire \c$2957 ; + wire \c$2961 ; + wire \c$2965 ; + wire \c$2969 ; + wire \c$2973 ; + wire \c$2977 ; + wire \c$2981 ; + wire \c$2985 ; + wire \c$2989 ; + wire \c$2993 ; + wire \c$2997 ; + wire \c$3001 ; + wire \c$3005 ; + wire \c$3009 ; + wire \c$3013 ; + wire \c$3017 ; + wire \c$3021 ; + wire \c$3025 ; + wire \c$3029 ; + wire \c$3033 ; + wire \c$3037 ; + wire \c$3041 ; + wire \c$3045 ; + wire \c$3049 ; + wire \c$3053 ; + wire \c$3057 ; + wire \c$3061 ; + wire \c$3065 ; + wire \c$3069 ; + wire \c$3073 ; + wire \c$3077 ; + wire \c$3081 ; + wire \c$3085 ; + wire \c$3089 ; + wire \c$3093 ; + wire \c$3097 ; + wire \c$3101 ; + wire \c$3105 ; + wire \c$3109 ; + wire \c$3113 ; + wire \c$3117 ; + wire \c$3121 ; + wire \c$3125 ; + wire \c$3129 ; + wire \c$3133 ; + wire \c$3137 ; + wire \c$3141 ; + wire \c$3145 ; + wire \c$3149 ; + wire \c$3153 ; + wire \c$3157 ; + wire \c$3161 ; + wire \c$3165 ; + wire \c$3169 ; + wire \c$3173 ; + wire \c$3177 ; + wire \c$3181 ; + wire \c$3185 ; + wire \c$3189 ; + wire \c$3193 ; + wire \c$3197 ; + wire \c$3201 ; + wire \c$3205 ; + wire \c$3209 ; + wire \c$3213 ; + wire \c$3217 ; + wire \c$3221 ; + wire \c$3225 ; + wire \c$3229 ; + wire \c$3233 ; + wire \c$3237 ; + wire \c$3241 ; + wire \c$3245 ; + wire \c$3249 ; + wire \c$3253 ; + wire \c$3257 ; + wire \c$3261 ; + wire \c$3265 ; + wire \c$3269 ; + wire \c$3273 ; + wire \c$3277 ; + wire \c$3281 ; + wire \c$3285 ; + wire \c$3289 ; + wire \c$3293 ; + wire \c$3297 ; + wire \c$3301 ; + wire \c$3305 ; + wire \c$3309 ; + wire \c$3313 ; + wire \c$3317 ; + wire \c$3321 ; + wire \c$3325 ; + wire \c$3329 ; + wire \c$3333 ; + wire \c$3337 ; + wire \c$3341 ; + wire \c$3345 ; + wire \c$3349 ; + wire \c$3353 ; + wire \c$3357 ; + wire \c$3361 ; + wire \c$3365 ; + wire \c$3369 ; + wire \c$3373 ; + wire \c$3377 ; + wire \c$3381 ; + wire \c$3385 ; + wire \c$3389 ; + wire \c$3393 ; + wire \c$3397 ; + wire \c$3401 ; + wire \c$3405 ; + wire \c$3409 ; + wire \c$3413 ; + wire \c$3417 ; + wire \c$3421 ; + wire \c$3425 ; + wire \c$3429 ; + wire \c$3433 ; + wire \c$3437 ; + wire \c$3441 ; + wire \c$3445 ; + wire \c$3449 ; + wire \c$3453 ; + wire \c$3457 ; + wire \c$3461 ; + wire \c$3465 ; + wire \c$3469 ; + wire \c$3473 ; + wire \c$3477 ; + wire \c$3481 ; + wire \c$3485 ; + wire \c$3489 ; + wire \c$3493 ; + wire \c$3497 ; + wire \c$3501 ; + wire \c$3505 ; + wire \c$3509 ; + wire \c$3513 ; + wire \c$3517 ; + wire \c$3521 ; + wire \c$3525 ; + wire \c$3529 ; + wire \c$3533 ; + wire \c$3537 ; + wire \c$3541 ; + wire \c$3545 ; + wire \c$3549 ; + wire \c$3553 ; + wire \c$3557 ; + wire \c$3561 ; + wire \c$3565 ; + wire \c$3569 ; + wire \c$3573 ; + wire \c$3577 ; + wire \c$3581 ; + wire \c$3585 ; + wire \c$3589 ; + wire \c$3593 ; + wire \c$3597 ; + wire \c$3601 ; + wire \c$3605 ; + wire \c$3609 ; + wire \c$3613 ; + wire \c$3617 ; + wire \c$3621 ; + wire \c$3625 ; + wire \c$3629 ; + wire \c$3633 ; + wire \c$3637 ; + wire \c$3641 ; + wire \c$3645 ; + wire \c$3649 ; + wire \c$3653 ; + wire \c$3657 ; + wire \c$3661 ; + wire \c$3665 ; + wire \c$3669 ; + wire \c$3673 ; + wire \c$3677 ; + wire \c$3681 ; + wire \c$3685 ; + wire \c$3689 ; + wire \c$3693 ; + wire \c$3697 ; + wire \c$3701 ; + wire \c$3705 ; + wire \c$3709 ; + wire \c$3713 ; + wire \c$3717 ; + wire \c$3721 ; + wire \c$3725 ; + wire \c$3729 ; + wire \c$3733 ; + wire \c$3737 ; + wire \c$3741 ; + wire \c$3745 ; + wire \c$3749 ; + wire \c$3753 ; + wire \c$3757 ; + wire \c$3761 ; + wire \c$3765 ; + wire \c$3769 ; + wire \c$3773 ; + wire \c$3777 ; + wire \c$3781 ; + wire \c$3785 ; + wire \c$3789 ; + wire \c$3793 ; + wire \c$3797 ; + wire \c$3801 ; + wire \c$3805 ; + wire \c$3809 ; + wire \c$3813 ; + wire \c$3817 ; + wire \c$3821 ; + wire \c$3825 ; + wire \c$3829 ; + wire \c$3833 ; + wire \c$3837 ; + wire \c$3841 ; + wire \c$3845 ; + wire \c$3849 ; + wire \c$3853 ; + wire \c$3857 ; + wire \c$3861 ; + wire \c$3865 ; + wire \c$3869 ; + wire \c$3873 ; + wire \c$3877 ; + wire \c$3881 ; + wire \c$3885 ; + wire \c$3889 ; + wire \c$3893 ; + wire \c$3897 ; + wire \c$3901 ; + wire \c$3905 ; + wire \c$3909 ; + wire \c$3913 ; + wire \c$3917 ; + wire \c$3921 ; + wire \c$3925 ; + wire \c$3929 ; + wire \c$3933 ; + wire \c$3937 ; + wire \c$3941 ; + wire \c$3945 ; + wire \c$3949 ; + wire \c$3953 ; + wire \c$3957 ; + wire \c$3961 ; + wire \c$3965 ; + wire \c$3969 ; + wire \c$3973 ; + wire \c$3977 ; + wire \c$3981 ; + wire \c$3985 ; + wire \c$3989 ; + wire \c$3993 ; + wire \c$3997 ; + wire \c$4001 ; + wire \c$4005 ; + wire \c$4009 ; + wire \c$4013 ; + wire \c$4017 ; + wire \c$4021 ; + wire \c$4025 ; + wire \c$4029 ; + wire \c$4033 ; + wire \c$4037 ; + wire \c$4041 ; + wire \c$4045 ; + wire \c$4049 ; + wire \c$4053 ; + wire \c$4057 ; + wire \c$4061 ; + wire \c$4065 ; + wire \c$4069 ; + wire \c$4073 ; + wire \c$4077 ; + wire \c$4081 ; + wire \c$4085 ; + wire \c$4089 ; + wire \c$4093 ; + wire \c$4097 ; + wire \c$4101 ; + wire \c$4105 ; + wire \c$4109 ; + wire \c$4113 ; + wire \c$4117 ; + wire \c$4121 ; + wire \c$4125 ; + wire \c$4129 ; + wire \c$4133 ; + wire \c$4137 ; + wire \c$4141 ; + wire \c$4145 ; + wire \c$4149 ; + wire \c$4153 ; + wire \c$4157 ; + wire \c$4161 ; + wire \c$4165 ; + wire \c$4169 ; + wire \c$4173 ; + wire \c$4177 ; + wire \c$4181 ; + wire \c$4185 ; + wire \c$4189 ; + wire \c$4193 ; + wire \c$4197 ; + wire \c$4201 ; + wire \c$4205 ; + wire \c$4209 ; + wire \c$4213 ; + wire \c$4217 ; + wire \c$4221 ; + wire \c$4225 ; + wire \c$4229 ; + wire \c$4233 ; + wire \c$4237 ; + wire \c$4241 ; + wire \c$4245 ; + wire \c$4249 ; + wire \c$4253 ; + wire \c$4257 ; + wire \c$4261 ; + wire \c$4265 ; + wire \c$4269 ; + wire \c$4273 ; + wire \c$4277 ; + wire \c$4281 ; + wire \c$4285 ; + wire \c$4289 ; + wire \c$4293 ; + wire \c$4297 ; + wire \c$4301 ; + wire \c$4305 ; + wire \c$4309 ; + wire \c$4313 ; + wire \c$4317 ; + wire \c$4321 ; + wire \c$4325 ; + wire \c$4329 ; + wire \c$4333 ; + wire \c$4337 ; + wire \c$4341 ; + wire \c$4345 ; + wire \c$4349 ; + wire \c$4353 ; + wire \c$4357 ; + wire \c$4361 ; + wire \c$4365 ; + wire \c$4369 ; + wire \c$4373 ; + wire \c$4377 ; + wire \c$4381 ; + wire \c$4385 ; + wire \c$4389 ; + wire \c$4393 ; + wire \c$4397 ; + input clk; + wire clk; + wire con; + wire \con$2556 ; + wire \con$2560 ; + wire \con$2564 ; + wire \con$2568 ; + wire \con$2572 ; + wire \con$2576 ; + wire \con$2580 ; + wire \con$2584 ; + wire \con$2588 ; + wire \con$2592 ; + wire \con$2596 ; + wire \con$2600 ; + wire \con$2604 ; + wire \con$2608 ; + wire \con$2612 ; + wire \con$2616 ; + wire \con$2620 ; + wire \con$2624 ; + wire \con$2628 ; + wire \con$2632 ; + wire \con$2636 ; + wire \con$2640 ; + wire \con$2644 ; + wire \con$2648 ; + wire \con$2652 ; + wire \con$2656 ; + wire \con$2660 ; + wire \con$2664 ; + wire \con$2668 ; + wire \con$2672 ; + wire \con$2676 ; + wire \con$2680 ; + wire \con$2684 ; + wire \con$2688 ; + wire \con$2692 ; + wire \con$2696 ; + wire \con$2700 ; + wire \con$2704 ; + wire \con$2708 ; + wire \con$2712 ; + wire \con$2716 ; + wire \con$2720 ; + wire \con$2724 ; + wire \con$2728 ; + wire \con$2732 ; + wire \con$2736 ; + wire \con$2740 ; + wire \con$2744 ; + wire \con$2748 ; + wire \con$2752 ; + wire \con$2756 ; + wire \con$2760 ; + wire \con$2764 ; + wire \con$2768 ; + wire \con$2772 ; + wire \con$2776 ; + wire \con$2780 ; + wire \con$2784 ; + wire \con$2788 ; + wire \con$2792 ; + wire \con$2796 ; + wire \con$2800 ; + wire \con$2804 ; + wire \con$2808 ; + wire \con$2812 ; + wire \con$2816 ; + wire \con$2820 ; + wire \con$2824 ; + wire \con$2828 ; + wire \con$2832 ; + wire \con$2836 ; + wire \con$2840 ; + wire \con$2844 ; + wire \con$2848 ; + wire \con$2852 ; + wire \con$2856 ; + wire \con$2860 ; + wire \con$2864 ; + wire \con$2868 ; + wire \con$2872 ; + wire \con$2876 ; + wire \con$2880 ; + wire \con$2884 ; + wire \con$2888 ; + wire \con$2892 ; + wire \con$2896 ; + wire \con$2900 ; + wire \con$2904 ; + wire \con$2908 ; + wire \con$2912 ; + wire \con$2916 ; + wire \con$2920 ; + wire \con$2924 ; + wire \con$2928 ; + wire \con$2932 ; + wire \con$2936 ; + wire \con$2940 ; + wire \con$2944 ; + wire \con$2948 ; + wire \con$2952 ; + wire \con$2956 ; + wire \con$2960 ; + wire \con$2964 ; + wire \con$2968 ; + wire \con$2972 ; + wire \con$2976 ; + wire \con$2980 ; + wire \con$2984 ; + wire \con$2988 ; + wire \con$2992 ; + wire \con$2996 ; + wire \con$3000 ; + wire \con$3004 ; + wire \con$3008 ; + wire \con$3012 ; + wire \con$3016 ; + wire \con$3020 ; + wire \con$3024 ; + wire \con$3028 ; + wire \con$3032 ; + wire \con$3036 ; + wire \con$3040 ; + wire \con$3044 ; + wire \con$3048 ; + wire \con$3052 ; + wire \con$3056 ; + wire \con$3060 ; + wire \con$3064 ; + wire \con$3068 ; + wire \con$3072 ; + wire \con$3076 ; + wire \con$3080 ; + wire \con$3084 ; + wire \con$3088 ; + wire \con$3092 ; + wire \con$3096 ; + wire \con$3100 ; + wire \con$3104 ; + wire \con$3108 ; + wire \con$3112 ; + wire \con$3116 ; + wire \con$3120 ; + wire \con$3124 ; + wire \con$3128 ; + wire \con$3132 ; + wire \con$3136 ; + wire \con$3140 ; + wire \con$3144 ; + wire \con$3148 ; + wire \con$3152 ; + wire \con$3156 ; + wire \con$3160 ; + wire \con$3164 ; + wire \con$3168 ; + wire \con$3172 ; + wire \con$3176 ; + wire \con$3180 ; + wire \con$3184 ; + wire \con$3188 ; + wire \con$3192 ; + wire \con$3196 ; + wire \con$3200 ; + wire \con$3204 ; + wire \con$3208 ; + wire \con$3212 ; + wire \con$3216 ; + wire \con$3220 ; + wire \con$3224 ; + wire \con$3228 ; + wire \con$3232 ; + wire \con$3236 ; + wire \con$3240 ; + wire \con$3244 ; + wire \con$3248 ; + wire \con$3252 ; + wire \con$3256 ; + wire \con$3260 ; + wire \con$3264 ; + wire \con$3268 ; + wire \con$3272 ; + wire \con$3276 ; + wire \con$3280 ; + wire \con$3284 ; + wire \con$3288 ; + wire \con$3292 ; + wire \con$3296 ; + wire \con$3300 ; + wire \con$3304 ; + wire \con$3308 ; + wire \con$3312 ; + wire \con$3316 ; + wire \con$3320 ; + wire \con$3324 ; + wire \con$3328 ; + wire \con$3332 ; + wire \con$3336 ; + wire \con$3340 ; + wire \con$3344 ; + wire \con$3348 ; + wire \con$3352 ; + wire \con$3356 ; + wire \con$3360 ; + wire \con$3364 ; + wire \con$3368 ; + wire \con$3372 ; + wire \con$3376 ; + wire \con$3380 ; + wire \con$3384 ; + wire \con$3388 ; + wire \con$3392 ; + wire \con$3396 ; + wire \con$3400 ; + wire \con$3404 ; + wire \con$3408 ; + wire \con$3412 ; + wire \con$3416 ; + wire \con$3420 ; + wire \con$3424 ; + wire \con$3428 ; + wire \con$3432 ; + wire \con$3436 ; + wire \con$3440 ; + wire \con$3444 ; + wire \con$3448 ; + wire \con$3452 ; + wire \con$3456 ; + wire \con$3460 ; + wire \con$3464 ; + wire \con$3468 ; + wire \con$3472 ; + wire \con$3476 ; + wire \con$3480 ; + wire \con$3484 ; + wire \con$3488 ; + wire \con$3492 ; + wire \con$3496 ; + wire \con$3500 ; + wire \con$3504 ; + wire \con$3508 ; + wire \con$3512 ; + wire \con$3516 ; + wire \con$3520 ; + wire \con$3524 ; + wire \con$3528 ; + wire \con$3532 ; + wire \con$3536 ; + wire \con$3540 ; + wire \con$3544 ; + wire \con$3548 ; + wire \con$3552 ; + wire \con$3556 ; + wire \con$3560 ; + wire \con$3564 ; + wire \con$3568 ; + wire \con$3572 ; + wire \con$3576 ; + wire \con$3580 ; + wire \con$3584 ; + wire \con$3588 ; + wire \con$3592 ; + wire \con$3596 ; + wire \con$3600 ; + wire \con$3604 ; + wire \con$3608 ; + wire \con$3612 ; + wire \con$3616 ; + wire \con$3620 ; + wire \con$3624 ; + wire \con$3628 ; + wire \con$3632 ; + wire \con$3636 ; + wire \con$3640 ; + wire \con$3644 ; + wire \con$3648 ; + wire \con$3652 ; + wire \con$3656 ; + wire \con$3660 ; + wire \con$3664 ; + wire \con$3668 ; + wire \con$3672 ; + wire \con$3676 ; + wire \con$3680 ; + wire \con$3684 ; + wire \con$3688 ; + wire \con$3692 ; + wire \con$3696 ; + wire \con$3700 ; + wire \con$3704 ; + wire \con$3708 ; + wire \con$3712 ; + wire \con$3716 ; + wire \con$3720 ; + wire \con$3724 ; + wire \con$3728 ; + wire \con$3732 ; + wire \con$3736 ; + wire \con$3740 ; + wire \con$3744 ; + wire \con$3748 ; + wire \con$3752 ; + wire \con$3756 ; + wire \con$3760 ; + wire \con$3764 ; + wire \con$3768 ; + wire \con$3772 ; + wire \con$3776 ; + wire \con$3780 ; + wire \con$3784 ; + wire \con$3788 ; + wire \con$3792 ; + wire \con$3796 ; + wire \con$3800 ; + wire \con$3804 ; + wire \con$3808 ; + wire \con$3812 ; + wire \con$3816 ; + wire \con$3820 ; + wire \con$3824 ; + wire \con$3828 ; + wire \con$3832 ; + wire \con$3836 ; + wire \con$3840 ; + wire \con$3844 ; + wire \con$3848 ; + wire \con$3852 ; + wire \con$3856 ; + wire \con$3860 ; + wire \con$3864 ; + wire \con$3868 ; + wire \con$3872 ; + wire \con$3876 ; + wire \con$3880 ; + wire \con$3884 ; + wire \con$3888 ; + wire \con$3892 ; + wire \con$3896 ; + wire \con$3900 ; + wire \con$3904 ; + wire \con$3908 ; + wire \con$3912 ; + wire \con$3916 ; + wire \con$3920 ; + wire \con$3924 ; + wire \con$3928 ; + wire \con$3932 ; + wire \con$3936 ; + wire \con$3940 ; + wire \con$3944 ; + wire \con$3948 ; + wire \con$3952 ; + wire \con$3956 ; + wire \con$3960 ; + wire \con$3964 ; + wire \con$3968 ; + wire \con$3972 ; + wire \con$3976 ; + wire \con$3980 ; + wire \con$3984 ; + wire \con$3988 ; + wire \con$3992 ; + wire \con$3996 ; + wire \con$4000 ; + wire \con$4004 ; + wire \con$4008 ; + wire \con$4012 ; + wire \con$4016 ; + wire \con$4020 ; + wire \con$4024 ; + wire \con$4028 ; + wire \con$4032 ; + wire \con$4036 ; + wire \con$4040 ; + wire \con$4044 ; + wire \con$4048 ; + wire \con$4052 ; + wire \con$4056 ; + wire \con$4060 ; + wire \con$4064 ; + wire \con$4068 ; + wire \con$4072 ; + wire \con$4076 ; + wire \con$4080 ; + wire \con$4084 ; + wire \con$4088 ; + wire \con$4092 ; + wire \con$4096 ; + wire \con$4100 ; + wire \con$4104 ; + wire \con$4108 ; + wire \con$4112 ; + wire \con$4116 ; + wire \con$4120 ; + wire \con$4124 ; + wire \con$4128 ; + wire \con$4132 ; + wire \con$4136 ; + wire \con$4140 ; + wire \con$4144 ; + wire \con$4148 ; + wire \con$4152 ; + wire \con$4156 ; + wire \con$4160 ; + wire \con$4164 ; + wire \con$4168 ; + wire \con$4172 ; + wire \con$4176 ; + wire \con$4180 ; + wire \con$4184 ; + wire \con$4188 ; + wire \con$4192 ; + wire \con$4196 ; + wire \con$4200 ; + wire \con$4204 ; + wire \con$4208 ; + wire \con$4212 ; + wire \con$4216 ; + wire \con$4220 ; + wire \con$4224 ; + wire \con$4228 ; + wire \con$4232 ; + wire \con$4236 ; + wire \con$4240 ; + wire \con$4244 ; + wire \con$4248 ; + wire \con$4252 ; + wire \con$4256 ; + wire \con$4260 ; + wire \con$4264 ; + wire \con$4268 ; + wire \con$4272 ; + wire \con$4276 ; + wire \con$4280 ; + wire \con$4284 ; + wire \con$4288 ; + wire \con$4292 ; + wire \con$4296 ; + wire \con$4300 ; + wire \con$4304 ; + wire \con$4308 ; + wire \con$4312 ; + wire \con$4316 ; + wire \con$4320 ; + wire \con$4324 ; + wire \con$4328 ; + wire \con$4332 ; + wire \con$4336 ; + wire \con$4340 ; + wire \con$4344 ; + wire \con$4348 ; + wire \con$4352 ; + wire \con$4356 ; + wire \con$4360 ; + wire \con$4364 ; + wire \con$4368 ; + wire \con$4372 ; + wire \con$4376 ; + wire \con$4380 ; + wire \con$4384 ; + wire \con$4388 ; + wire \con$4392 ; + wire \con$4396 ; + wire \con$4400 ; + wire \con$4402 ; + wire \con$4404 ; + wire \con$4406 ; + wire \con$4408 ; + wire \con$4410 ; + wire \con$4412 ; + wire \con$4414 ; + wire \con$4416 ; + wire \con$4418 ; + wire \con$4420 ; + wire \con$4422 ; + wire \con$4424 ; + wire \con$4426 ; + wire \con$4428 ; + wire \con$4430 ; + wire \con$4432 ; + wire \con$4434 ; + wire \con$4436 ; + wire \con$4438 ; + wire \con$4440 ; + wire \con$4442 ; + wire \con$4444 ; + wire \con$4446 ; + wire \con$4448 ; + wire \con$4450 ; + wire \con$4452 ; + wire \con$4454 ; + wire \con$4456 ; + wire \con$4458 ; + wire \con$4460 ; + wire \con$4462 ; + wire \con$4464 ; + wire \con$4466 ; + wire \con$4468 ; + wire \con$4470 ; + wire \con$4472 ; + wire \con$4474 ; + wire \con$4476 ; + wire \con$4478 ; + wire \con$4480 ; + wire \con$4482 ; + wire \con$4484 ; + wire \con$4486 ; + wire \con$4488 ; + wire \con$4490 ; + wire \con$4492 ; + wire \con$4494 ; + wire \con$4496 ; + wire \con$4498 ; + wire \con$4500 ; + wire \con$4502 ; + wire \con$4504 ; + wire \con$4506 ; + wire \con$4508 ; + wire \con$4510 ; + wire \con$4512 ; + wire \con$4514 ; + wire \con$4516 ; + wire \con$4518 ; + wire \con$4520 ; + wire \con$4522 ; + wire \con$4524 ; + reg [63:0] final_a_registered = 64'h0000000000000000; + reg [63:0] final_b_registered = 64'h0000000000000000; + wire [33:0] multiplicand; + wire [34:0] multiplier; + wire [2:0] notblock; + wire [2:0] \notblock$2008 ; + wire [2:0] \notblock$2042 ; + wire [2:0] \notblock$2076 ; + wire [2:0] \notblock$2110 ; + wire [2:0] \notblock$2144 ; + wire [2:0] \notblock$2178 ; + wire [2:0] \notblock$2212 ; + wire [2:0] \notblock$2246 ; + wire [2:0] \notblock$2280 ; + wire [2:0] \notblock$2314 ; + wire [2:0] \notblock$2348 ; + wire [2:0] \notblock$2382 ; + wire [2:0] \notblock$2416 ; + wire [2:0] \notblock$2450 ; + wire [2:0] \notblock$2484 ; + wire [2:0] \notblock$2518 ; + wire notsign; + wire \notsign$1036 ; + wire \notsign$1070 ; + wire \notsign$1100 ; + wire \notsign$1126 ; + wire \notsign$1148 ; + wire \notsign$1166 ; + wire \notsign$1180 ; + wire \notsign$1190 ; + wire \notsign$686 ; + wire \notsign$748 ; + wire \notsign$806 ; + wire \notsign$860 ; + wire \notsign$910 ; + wire \notsign$956 ; + wire \notsign$998 ; + output [63:0] o; + reg [63:0] o = 64'h0000000000000000; + wire [63:0] \o$1973 ; + reg pp_row0_0 = 1'h0; + reg pp_row0_1 = 1'h0; + reg pp_row10_0 = 1'h0; + reg pp_row10_1 = 1'h0; + reg pp_row10_2 = 1'h0; + reg pp_row10_3 = 1'h0; + reg pp_row10_4 = 1'h0; + reg pp_row10_5 = 1'h0; + reg pp_row10_6 = 1'h0; + reg pp_row11_0 = 1'h0; + reg pp_row11_1 = 1'h0; + reg pp_row11_2 = 1'h0; + reg pp_row11_3 = 1'h0; + reg pp_row11_4 = 1'h0; + reg pp_row11_5 = 1'h0; + reg pp_row12_0 = 1'h0; + reg pp_row12_1 = 1'h0; + reg pp_row12_2 = 1'h0; + reg pp_row12_3 = 1'h0; + reg pp_row12_4 = 1'h0; + reg pp_row12_5 = 1'h0; + reg pp_row12_6 = 1'h0; + reg pp_row12_7 = 1'h0; + reg pp_row13_0 = 1'h0; + reg pp_row13_1 = 1'h0; + reg pp_row13_2 = 1'h0; + reg pp_row13_3 = 1'h0; + reg pp_row13_4 = 1'h0; + reg pp_row13_5 = 1'h0; + reg pp_row13_6 = 1'h0; + reg pp_row14_0 = 1'h0; + reg pp_row14_1 = 1'h0; + reg pp_row14_2 = 1'h0; + reg pp_row14_3 = 1'h0; + reg pp_row14_4 = 1'h0; + reg pp_row14_5 = 1'h0; + reg pp_row14_6 = 1'h0; + reg pp_row14_7 = 1'h0; + reg pp_row14_8 = 1'h0; + reg pp_row15_0 = 1'h0; + reg pp_row15_1 = 1'h0; + reg pp_row15_2 = 1'h0; + reg pp_row15_3 = 1'h0; + reg pp_row15_4 = 1'h0; + reg pp_row15_5 = 1'h0; + reg pp_row15_6 = 1'h0; + reg pp_row15_7 = 1'h0; + reg pp_row16_0 = 1'h0; + reg pp_row16_1 = 1'h0; + reg pp_row16_2 = 1'h0; + reg pp_row16_3 = 1'h0; + reg pp_row16_4 = 1'h0; + reg pp_row16_5 = 1'h0; + reg pp_row16_6 = 1'h0; + reg pp_row16_7 = 1'h0; + reg pp_row16_8 = 1'h0; + reg pp_row16_9 = 1'h0; + reg pp_row17_0 = 1'h0; + reg pp_row17_1 = 1'h0; + reg pp_row17_2 = 1'h0; + reg pp_row17_3 = 1'h0; + reg pp_row17_4 = 1'h0; + reg pp_row17_5 = 1'h0; + reg pp_row17_6 = 1'h0; + reg pp_row17_7 = 1'h0; + reg pp_row17_8 = 1'h0; + reg pp_row18_0 = 1'h0; + reg pp_row18_1 = 1'h0; + reg pp_row18_10 = 1'h0; + reg pp_row18_2 = 1'h0; + reg pp_row18_3 = 1'h0; + reg pp_row18_4 = 1'h0; + reg pp_row18_5 = 1'h0; + reg pp_row18_6 = 1'h0; + reg pp_row18_7 = 1'h0; + reg pp_row18_8 = 1'h0; + reg pp_row18_9 = 1'h0; + reg pp_row19_0 = 1'h0; + reg pp_row19_1 = 1'h0; + reg pp_row19_2 = 1'h0; + reg pp_row19_3 = 1'h0; + reg pp_row19_4 = 1'h0; + reg pp_row19_5 = 1'h0; + reg pp_row19_6 = 1'h0; + reg pp_row19_7 = 1'h0; + reg pp_row19_8 = 1'h0; + reg pp_row19_9 = 1'h0; + reg pp_row1_0 = 1'h0; + reg pp_row20_0 = 1'h0; + reg pp_row20_1 = 1'h0; + reg pp_row20_10 = 1'h0; + reg pp_row20_11 = 1'h0; + reg pp_row20_2 = 1'h0; + reg pp_row20_3 = 1'h0; + reg pp_row20_4 = 1'h0; + reg pp_row20_5 = 1'h0; + reg pp_row20_6 = 1'h0; + reg pp_row20_7 = 1'h0; + reg pp_row20_8 = 1'h0; + reg pp_row20_9 = 1'h0; + reg pp_row21_0 = 1'h0; + reg pp_row21_1 = 1'h0; + reg pp_row21_10 = 1'h0; + reg pp_row21_2 = 1'h0; + reg pp_row21_3 = 1'h0; + reg pp_row21_4 = 1'h0; + reg pp_row21_5 = 1'h0; + reg pp_row21_6 = 1'h0; + reg pp_row21_7 = 1'h0; + reg pp_row21_8 = 1'h0; + reg pp_row21_9 = 1'h0; + reg pp_row22_0 = 1'h0; + reg pp_row22_1 = 1'h0; + reg pp_row22_10 = 1'h0; + reg pp_row22_11 = 1'h0; + reg pp_row22_12 = 1'h0; + reg pp_row22_2 = 1'h0; + reg pp_row22_3 = 1'h0; + reg pp_row22_4 = 1'h0; + reg pp_row22_5 = 1'h0; + reg pp_row22_6 = 1'h0; + reg pp_row22_7 = 1'h0; + reg pp_row22_8 = 1'h0; + reg pp_row22_9 = 1'h0; + reg pp_row23_0 = 1'h0; + reg pp_row23_1 = 1'h0; + reg pp_row23_10 = 1'h0; + reg pp_row23_11 = 1'h0; + reg pp_row23_2 = 1'h0; + reg pp_row23_3 = 1'h0; + reg pp_row23_4 = 1'h0; + reg pp_row23_5 = 1'h0; + reg pp_row23_6 = 1'h0; + reg pp_row23_7 = 1'h0; + reg pp_row23_8 = 1'h0; + reg pp_row23_9 = 1'h0; + reg pp_row24_0 = 1'h0; + reg pp_row24_1 = 1'h0; + reg pp_row24_10 = 1'h0; + reg pp_row24_11 = 1'h0; + reg pp_row24_12 = 1'h0; + reg pp_row24_13 = 1'h0; + reg pp_row24_2 = 1'h0; + reg pp_row24_3 = 1'h0; + reg pp_row24_4 = 1'h0; + reg pp_row24_5 = 1'h0; + reg pp_row24_6 = 1'h0; + reg pp_row24_7 = 1'h0; + reg pp_row24_8 = 1'h0; + reg pp_row24_9 = 1'h0; + reg pp_row25_0 = 1'h0; + reg pp_row25_1 = 1'h0; + reg pp_row25_10 = 1'h0; + reg pp_row25_11 = 1'h0; + reg pp_row25_12 = 1'h0; + reg pp_row25_2 = 1'h0; + reg pp_row25_3 = 1'h0; + reg pp_row25_4 = 1'h0; + reg pp_row25_5 = 1'h0; + reg pp_row25_6 = 1'h0; + reg pp_row25_7 = 1'h0; + reg pp_row25_8 = 1'h0; + reg pp_row25_9 = 1'h0; + reg pp_row26_0 = 1'h0; + reg pp_row26_1 = 1'h0; + reg pp_row26_10 = 1'h0; + reg pp_row26_11 = 1'h0; + reg pp_row26_12 = 1'h0; + reg pp_row26_13 = 1'h0; + reg pp_row26_14 = 1'h0; + reg pp_row26_2 = 1'h0; + reg pp_row26_3 = 1'h0; + reg pp_row26_4 = 1'h0; + reg pp_row26_5 = 1'h0; + reg pp_row26_6 = 1'h0; + reg pp_row26_7 = 1'h0; + reg pp_row26_8 = 1'h0; + reg pp_row26_9 = 1'h0; + reg pp_row27_0 = 1'h0; + reg pp_row27_1 = 1'h0; + reg pp_row27_10 = 1'h0; + reg pp_row27_11 = 1'h0; + reg pp_row27_12 = 1'h0; + reg pp_row27_13 = 1'h0; + reg pp_row27_2 = 1'h0; + reg pp_row27_3 = 1'h0; + reg pp_row27_4 = 1'h0; + reg pp_row27_5 = 1'h0; + reg pp_row27_6 = 1'h0; + reg pp_row27_7 = 1'h0; + reg pp_row27_8 = 1'h0; + reg pp_row27_9 = 1'h0; + reg pp_row28_0 = 1'h0; + reg pp_row28_1 = 1'h0; + reg pp_row28_10 = 1'h0; + reg pp_row28_11 = 1'h0; + reg pp_row28_12 = 1'h0; + reg pp_row28_13 = 1'h0; + reg pp_row28_14 = 1'h0; + reg pp_row28_15 = 1'h0; + reg pp_row28_2 = 1'h0; + reg pp_row28_3 = 1'h0; + reg pp_row28_4 = 1'h0; + reg pp_row28_5 = 1'h0; + reg pp_row28_6 = 1'h0; + reg pp_row28_7 = 1'h0; + reg pp_row28_8 = 1'h0; + reg pp_row28_9 = 1'h0; + reg pp_row29_0 = 1'h0; + reg pp_row29_1 = 1'h0; + reg pp_row29_10 = 1'h0; + reg pp_row29_11 = 1'h0; + reg pp_row29_12 = 1'h0; + reg pp_row29_13 = 1'h0; + reg pp_row29_14 = 1'h0; + reg pp_row29_2 = 1'h0; + reg pp_row29_3 = 1'h0; + reg pp_row29_4 = 1'h0; + reg pp_row29_5 = 1'h0; + reg pp_row29_6 = 1'h0; + reg pp_row29_7 = 1'h0; + reg pp_row29_8 = 1'h0; + reg pp_row29_9 = 1'h0; + reg pp_row2_0 = 1'h0; + reg pp_row2_1 = 1'h0; + reg pp_row2_2 = 1'h0; + reg pp_row30_0 = 1'h0; + reg pp_row30_1 = 1'h0; + reg pp_row30_10 = 1'h0; + reg pp_row30_11 = 1'h0; + reg pp_row30_12 = 1'h0; + reg pp_row30_13 = 1'h0; + reg pp_row30_14 = 1'h0; + reg pp_row30_15 = 1'h0; + reg pp_row30_16 = 1'h0; + reg pp_row30_2 = 1'h0; + reg pp_row30_3 = 1'h0; + reg pp_row30_4 = 1'h0; + reg pp_row30_5 = 1'h0; + reg pp_row30_6 = 1'h0; + reg pp_row30_7 = 1'h0; + reg pp_row30_8 = 1'h0; + reg pp_row30_9 = 1'h0; + reg pp_row31_0 = 1'h0; + reg pp_row31_1 = 1'h0; + reg pp_row31_10 = 1'h0; + reg pp_row31_11 = 1'h0; + reg pp_row31_12 = 1'h0; + reg pp_row31_13 = 1'h0; + reg pp_row31_14 = 1'h0; + reg pp_row31_15 = 1'h0; + reg pp_row31_2 = 1'h0; + reg pp_row31_3 = 1'h0; + reg pp_row31_4 = 1'h0; + reg pp_row31_5 = 1'h0; + reg pp_row31_6 = 1'h0; + reg pp_row31_7 = 1'h0; + reg pp_row31_8 = 1'h0; + reg pp_row31_9 = 1'h0; + reg pp_row32_0 = 1'h0; + reg pp_row32_1 = 1'h0; + reg pp_row32_10 = 1'h0; + reg pp_row32_11 = 1'h0; + reg pp_row32_12 = 1'h0; + reg pp_row32_13 = 1'h0; + reg pp_row32_14 = 1'h0; + reg pp_row32_15 = 1'h0; + reg pp_row32_16 = 1'h0; + reg pp_row32_2 = 1'h0; + reg pp_row32_3 = 1'h0; + reg pp_row32_4 = 1'h0; + reg pp_row32_5 = 1'h0; + reg pp_row32_6 = 1'h0; + reg pp_row32_7 = 1'h0; + reg pp_row32_8 = 1'h0; + reg pp_row32_9 = 1'h0; + reg pp_row33_0 = 1'h0; + reg pp_row33_1 = 1'h0; + reg pp_row33_10 = 1'h0; + reg pp_row33_11 = 1'h0; + reg pp_row33_12 = 1'h0; + reg pp_row33_13 = 1'h0; + reg pp_row33_14 = 1'h0; + reg pp_row33_15 = 1'h0; + reg pp_row33_16 = 1'h0; + reg pp_row33_2 = 1'h0; + reg pp_row33_3 = 1'h0; + reg pp_row33_4 = 1'h0; + reg pp_row33_5 = 1'h0; + reg pp_row33_6 = 1'h0; + reg pp_row33_7 = 1'h0; + reg pp_row33_8 = 1'h0; + reg pp_row33_9 = 1'h0; + reg pp_row34_0 = 1'h0; + reg pp_row34_1 = 1'h0; + reg pp_row34_10 = 1'h0; + reg pp_row34_11 = 1'h0; + reg pp_row34_12 = 1'h0; + reg pp_row34_13 = 1'h0; + reg pp_row34_14 = 1'h0; + reg pp_row34_15 = 1'h0; + reg pp_row34_16 = 1'h0; + reg pp_row34_2 = 1'h0; + reg pp_row34_3 = 1'h0; + reg pp_row34_4 = 1'h0; + reg pp_row34_5 = 1'h0; + reg pp_row34_6 = 1'h0; + reg pp_row34_7 = 1'h0; + reg pp_row34_8 = 1'h0; + reg pp_row34_9 = 1'h0; + reg pp_row35_0 = 1'h0; + reg pp_row35_1 = 1'h0; + reg pp_row35_10 = 1'h0; + reg pp_row35_11 = 1'h0; + reg pp_row35_12 = 1'h0; + reg pp_row35_13 = 1'h0; + reg pp_row35_14 = 1'h0; + reg pp_row35_15 = 1'h0; + reg pp_row35_16 = 1'h0; + reg pp_row35_2 = 1'h0; + reg pp_row35_3 = 1'h0; + reg pp_row35_4 = 1'h0; + reg pp_row35_5 = 1'h0; + reg pp_row35_6 = 1'h0; + reg pp_row35_7 = 1'h0; + reg pp_row35_8 = 1'h0; + reg pp_row35_9 = 1'h0; + wire pp_row36_0; + reg pp_row36_1 = 1'h0; + reg pp_row36_10 = 1'h0; + reg pp_row36_11 = 1'h0; + reg pp_row36_12 = 1'h0; + reg pp_row36_13 = 1'h0; + reg pp_row36_14 = 1'h0; + reg pp_row36_15 = 1'h0; + reg pp_row36_2 = 1'h0; + reg pp_row36_3 = 1'h0; + reg pp_row36_4 = 1'h0; + reg pp_row36_5 = 1'h0; + reg pp_row36_6 = 1'h0; + reg pp_row36_7 = 1'h0; + reg pp_row36_8 = 1'h0; + reg pp_row36_9 = 1'h0; + reg pp_row37_0 = 1'h0; + reg pp_row37_1 = 1'h0; + reg pp_row37_10 = 1'h0; + reg pp_row37_11 = 1'h0; + reg pp_row37_12 = 1'h0; + reg pp_row37_13 = 1'h0; + reg pp_row37_14 = 1'h0; + reg pp_row37_2 = 1'h0; + reg pp_row37_3 = 1'h0; + reg pp_row37_4 = 1'h0; + reg pp_row37_5 = 1'h0; + reg pp_row37_6 = 1'h0; + reg pp_row37_7 = 1'h0; + reg pp_row37_8 = 1'h0; + reg pp_row37_9 = 1'h0; + wire pp_row38_0; + reg pp_row38_1 = 1'h0; + reg pp_row38_10 = 1'h0; + reg pp_row38_11 = 1'h0; + reg pp_row38_12 = 1'h0; + reg pp_row38_13 = 1'h0; + reg pp_row38_14 = 1'h0; + reg pp_row38_2 = 1'h0; + reg pp_row38_3 = 1'h0; + reg pp_row38_4 = 1'h0; + reg pp_row38_5 = 1'h0; + reg pp_row38_6 = 1'h0; + reg pp_row38_7 = 1'h0; + reg pp_row38_8 = 1'h0; + reg pp_row38_9 = 1'h0; + reg pp_row39_0 = 1'h0; + reg pp_row39_1 = 1'h0; + reg pp_row39_10 = 1'h0; + reg pp_row39_11 = 1'h0; + reg pp_row39_12 = 1'h0; + reg pp_row39_13 = 1'h0; + reg pp_row39_2 = 1'h0; + reg pp_row39_3 = 1'h0; + reg pp_row39_4 = 1'h0; + reg pp_row39_5 = 1'h0; + reg pp_row39_6 = 1'h0; + reg pp_row39_7 = 1'h0; + reg pp_row39_8 = 1'h0; + reg pp_row39_9 = 1'h0; + reg pp_row3_0 = 1'h0; + reg pp_row3_1 = 1'h0; + wire pp_row40_0; + reg pp_row40_1 = 1'h0; + reg pp_row40_10 = 1'h0; + reg pp_row40_11 = 1'h0; + reg pp_row40_12 = 1'h0; + reg pp_row40_13 = 1'h0; + reg pp_row40_2 = 1'h0; + reg pp_row40_3 = 1'h0; + reg pp_row40_4 = 1'h0; + reg pp_row40_5 = 1'h0; + reg pp_row40_6 = 1'h0; + reg pp_row40_7 = 1'h0; + reg pp_row40_8 = 1'h0; + reg pp_row40_9 = 1'h0; + reg pp_row41_0 = 1'h0; + reg pp_row41_1 = 1'h0; + reg pp_row41_10 = 1'h0; + reg pp_row41_11 = 1'h0; + reg pp_row41_12 = 1'h0; + reg pp_row41_2 = 1'h0; + reg pp_row41_3 = 1'h0; + reg pp_row41_4 = 1'h0; + reg pp_row41_5 = 1'h0; + reg pp_row41_6 = 1'h0; + reg pp_row41_7 = 1'h0; + reg pp_row41_8 = 1'h0; + reg pp_row41_9 = 1'h0; + wire pp_row42_0; + reg pp_row42_1 = 1'h0; + reg pp_row42_10 = 1'h0; + reg pp_row42_11 = 1'h0; + reg pp_row42_12 = 1'h0; + reg pp_row42_2 = 1'h0; + reg pp_row42_3 = 1'h0; + reg pp_row42_4 = 1'h0; + reg pp_row42_5 = 1'h0; + reg pp_row42_6 = 1'h0; + reg pp_row42_7 = 1'h0; + reg pp_row42_8 = 1'h0; + reg pp_row42_9 = 1'h0; + reg pp_row43_0 = 1'h0; + reg pp_row43_1 = 1'h0; + reg pp_row43_10 = 1'h0; + reg pp_row43_11 = 1'h0; + reg pp_row43_2 = 1'h0; + reg pp_row43_3 = 1'h0; + reg pp_row43_4 = 1'h0; + reg pp_row43_5 = 1'h0; + reg pp_row43_6 = 1'h0; + reg pp_row43_7 = 1'h0; + reg pp_row43_8 = 1'h0; + reg pp_row43_9 = 1'h0; + wire pp_row44_0; + reg pp_row44_1 = 1'h0; + reg pp_row44_10 = 1'h0; + reg pp_row44_11 = 1'h0; + reg pp_row44_2 = 1'h0; + reg pp_row44_3 = 1'h0; + reg pp_row44_4 = 1'h0; + reg pp_row44_5 = 1'h0; + reg pp_row44_6 = 1'h0; + reg pp_row44_7 = 1'h0; + reg pp_row44_8 = 1'h0; + reg pp_row44_9 = 1'h0; + reg pp_row45_0 = 1'h0; + reg pp_row45_1 = 1'h0; + reg pp_row45_10 = 1'h0; + reg pp_row45_2 = 1'h0; + reg pp_row45_3 = 1'h0; + reg pp_row45_4 = 1'h0; + reg pp_row45_5 = 1'h0; + reg pp_row45_6 = 1'h0; + reg pp_row45_7 = 1'h0; + reg pp_row45_8 = 1'h0; + reg pp_row45_9 = 1'h0; + wire pp_row46_0; + reg pp_row46_1 = 1'h0; + reg pp_row46_10 = 1'h0; + reg pp_row46_2 = 1'h0; + reg pp_row46_3 = 1'h0; + reg pp_row46_4 = 1'h0; + reg pp_row46_5 = 1'h0; + reg pp_row46_6 = 1'h0; + reg pp_row46_7 = 1'h0; + reg pp_row46_8 = 1'h0; + reg pp_row46_9 = 1'h0; + reg pp_row47_0 = 1'h0; + reg pp_row47_1 = 1'h0; + reg pp_row47_2 = 1'h0; + reg pp_row47_3 = 1'h0; + reg pp_row47_4 = 1'h0; + reg pp_row47_5 = 1'h0; + reg pp_row47_6 = 1'h0; + reg pp_row47_7 = 1'h0; + reg pp_row47_8 = 1'h0; + reg pp_row47_9 = 1'h0; + wire pp_row48_0; + reg pp_row48_1 = 1'h0; + reg pp_row48_2 = 1'h0; + reg pp_row48_3 = 1'h0; + reg pp_row48_4 = 1'h0; + reg pp_row48_5 = 1'h0; + reg pp_row48_6 = 1'h0; + reg pp_row48_7 = 1'h0; + reg pp_row48_8 = 1'h0; + reg pp_row48_9 = 1'h0; + reg pp_row49_0 = 1'h0; + reg pp_row49_1 = 1'h0; + reg pp_row49_2 = 1'h0; + reg pp_row49_3 = 1'h0; + reg pp_row49_4 = 1'h0; + reg pp_row49_5 = 1'h0; + reg pp_row49_6 = 1'h0; + reg pp_row49_7 = 1'h0; + reg pp_row49_8 = 1'h0; + reg pp_row4_0 = 1'h0; + reg pp_row4_1 = 1'h0; + reg pp_row4_2 = 1'h0; + reg pp_row4_3 = 1'h0; + wire pp_row50_0; + reg pp_row50_1 = 1'h0; + reg pp_row50_2 = 1'h0; + reg pp_row50_3 = 1'h0; + reg pp_row50_4 = 1'h0; + reg pp_row50_5 = 1'h0; + reg pp_row50_6 = 1'h0; + reg pp_row50_7 = 1'h0; + reg pp_row50_8 = 1'h0; + reg pp_row51_0 = 1'h0; + reg pp_row51_1 = 1'h0; + reg pp_row51_2 = 1'h0; + reg pp_row51_3 = 1'h0; + reg pp_row51_4 = 1'h0; + reg pp_row51_5 = 1'h0; + reg pp_row51_6 = 1'h0; + reg pp_row51_7 = 1'h0; + wire pp_row52_0; + reg pp_row52_1 = 1'h0; + reg pp_row52_2 = 1'h0; + reg pp_row52_3 = 1'h0; + reg pp_row52_4 = 1'h0; + reg pp_row52_5 = 1'h0; + reg pp_row52_6 = 1'h0; + reg pp_row52_7 = 1'h0; + reg pp_row53_0 = 1'h0; + reg pp_row53_1 = 1'h0; + reg pp_row53_2 = 1'h0; + reg pp_row53_3 = 1'h0; + reg pp_row53_4 = 1'h0; + reg pp_row53_5 = 1'h0; + reg pp_row53_6 = 1'h0; + wire pp_row54_0; + reg pp_row54_1 = 1'h0; + reg pp_row54_2 = 1'h0; + reg pp_row54_3 = 1'h0; + reg pp_row54_4 = 1'h0; + reg pp_row54_5 = 1'h0; + reg pp_row54_6 = 1'h0; + reg pp_row55_0 = 1'h0; + reg pp_row55_1 = 1'h0; + reg pp_row55_2 = 1'h0; + reg pp_row55_3 = 1'h0; + reg pp_row55_4 = 1'h0; + reg pp_row55_5 = 1'h0; + wire pp_row56_0; + reg pp_row56_1 = 1'h0; + reg pp_row56_2 = 1'h0; + reg pp_row56_3 = 1'h0; + reg pp_row56_4 = 1'h0; + reg pp_row56_5 = 1'h0; + reg pp_row57_0 = 1'h0; + reg pp_row57_1 = 1'h0; + reg pp_row57_2 = 1'h0; + reg pp_row57_3 = 1'h0; + reg pp_row57_4 = 1'h0; + wire pp_row58_0; + reg pp_row58_1 = 1'h0; + reg pp_row58_2 = 1'h0; + reg pp_row58_3 = 1'h0; + reg pp_row58_4 = 1'h0; + reg pp_row59_0 = 1'h0; + reg pp_row59_1 = 1'h0; + reg pp_row59_2 = 1'h0; + reg pp_row59_3 = 1'h0; + reg pp_row5_0 = 1'h0; + reg pp_row5_1 = 1'h0; + reg pp_row5_2 = 1'h0; + wire pp_row60_0; + reg pp_row60_1 = 1'h0; + reg pp_row60_2 = 1'h0; + reg pp_row60_3 = 1'h0; + reg pp_row61_0 = 1'h0; + reg pp_row61_1 = 1'h0; + reg pp_row61_2 = 1'h0; + wire pp_row62_0; + reg pp_row62_1 = 1'h0; + reg pp_row62_2 = 1'h0; + reg pp_row63_0 = 1'h0; + reg pp_row63_1 = 1'h0; + wire pp_row64_0; + reg pp_row64_1 = 1'h0; + reg pp_row6_0 = 1'h0; + reg pp_row6_1 = 1'h0; + reg pp_row6_2 = 1'h0; + reg pp_row6_3 = 1'h0; + reg pp_row6_4 = 1'h0; + reg pp_row7_0 = 1'h0; + reg pp_row7_1 = 1'h0; + reg pp_row7_2 = 1'h0; + reg pp_row7_3 = 1'h0; + reg pp_row8_0 = 1'h0; + reg pp_row8_1 = 1'h0; + reg pp_row8_2 = 1'h0; + reg pp_row8_3 = 1'h0; + reg pp_row8_4 = 1'h0; + reg pp_row8_5 = 1'h0; + reg pp_row9_0 = 1'h0; + reg pp_row9_1 = 1'h0; + reg pp_row9_2 = 1'h0; + reg pp_row9_3 = 1'h0; + reg pp_row9_4 = 1'h0; + wire [63:0] result; + (* init = 64'h0000000000000000 *) + wire [63:0] result_registered; + input rst; + wire rst; + wire s; + wire \s$1260 ; + wire \s$1261 ; + wire \s$1262 ; + wire \s$1263 ; + wire \s$1264 ; + wire \s$1265 ; + wire \s$1266 ; + wire \s$1267 ; + wire \s$1268 ; + wire \s$1269 ; + wire \s$1270 ; + wire \s$1271 ; + wire \s$1272 ; + wire \s$1273 ; + wire \s$1274 ; + wire \s$1275 ; + wire \s$1276 ; + wire \s$1277 ; + wire \s$1278 ; + wire \s$1279 ; + wire \s$1280 ; + wire \s$1281 ; + wire \s$1282 ; + wire \s$1283 ; + wire \s$1284 ; + wire \s$1285 ; + wire \s$1286 ; + wire \s$1287 ; + wire \s$1288 ; + wire \s$1289 ; + wire \s$1290 ; + wire \s$1291 ; + wire \s$1292 ; + wire \s$1293 ; + wire \s$1294 ; + wire \s$1295 ; + wire \s$1296 ; + wire \s$1297 ; + wire \s$1298 ; + wire \s$1299 ; + wire \s$1300 ; + wire \s$1301 ; + wire \s$1302 ; + wire \s$1303 ; + wire \s$1304 ; + wire \s$1305 ; + wire \s$1306 ; + wire \s$1307 ; + wire \s$1308 ; + wire \s$1309 ; + wire \s$1310 ; + wire \s$1311 ; + wire \s$1312 ; + wire \s$1313 ; + wire \s$1314 ; + wire \s$1315 ; + wire \s$1316 ; + wire \s$1317 ; + wire \s$1318 ; + wire \s$1319 ; + wire \s$1320 ; + wire \s$1321 ; + wire \s$2555 ; + wire \s$2559 ; + wire \s$2563 ; + wire \s$2567 ; + wire \s$2571 ; + wire \s$2575 ; + wire \s$2579 ; + wire \s$2583 ; + wire \s$2587 ; + wire \s$2591 ; + wire \s$2595 ; + wire \s$2599 ; + wire \s$2603 ; + wire \s$2607 ; + wire \s$2611 ; + wire \s$2615 ; + wire \s$2619 ; + wire \s$2623 ; + wire \s$2627 ; + wire \s$2631 ; + wire \s$2635 ; + wire \s$2639 ; + wire \s$2643 ; + wire \s$2647 ; + wire \s$2651 ; + wire \s$2655 ; + wire \s$2659 ; + wire \s$2663 ; + wire \s$2667 ; + wire \s$2671 ; + wire \s$2675 ; + wire \s$2679 ; + wire \s$2683 ; + wire \s$2687 ; + wire \s$2691 ; + wire \s$2695 ; + wire \s$2699 ; + wire \s$2703 ; + wire \s$2707 ; + wire \s$2711 ; + wire \s$2715 ; + wire \s$2719 ; + wire \s$2723 ; + wire \s$2727 ; + wire \s$2731 ; + wire \s$2735 ; + wire \s$2739 ; + wire \s$2743 ; + wire \s$2747 ; + wire \s$2751 ; + wire \s$2755 ; + wire \s$2759 ; + wire \s$2763 ; + wire \s$2767 ; + wire \s$2771 ; + wire \s$2775 ; + wire \s$2779 ; + wire \s$2783 ; + wire \s$2787 ; + wire \s$2791 ; + wire \s$2795 ; + wire \s$2799 ; + wire \s$2803 ; + wire \s$2807 ; + wire \s$2811 ; + wire \s$2815 ; + wire \s$2819 ; + wire \s$2823 ; + wire \s$2827 ; + wire \s$2831 ; + wire \s$2835 ; + wire \s$2839 ; + wire \s$2843 ; + wire \s$2847 ; + wire \s$2851 ; + wire \s$2855 ; + wire \s$2859 ; + wire \s$2863 ; + wire \s$2867 ; + wire \s$2871 ; + wire \s$2875 ; + wire \s$2879 ; + wire \s$2883 ; + wire \s$2887 ; + wire \s$2891 ; + wire \s$2895 ; + wire \s$2899 ; + wire \s$2903 ; + wire \s$2907 ; + wire \s$2911 ; + wire \s$2915 ; + wire \s$2919 ; + wire \s$2923 ; + wire \s$2927 ; + wire \s$2931 ; + wire \s$2935 ; + wire \s$2939 ; + wire \s$2943 ; + wire \s$2947 ; + wire \s$2951 ; + wire \s$2955 ; + wire \s$2959 ; + wire \s$2963 ; + wire \s$2967 ; + wire \s$2971 ; + wire \s$2975 ; + wire \s$2979 ; + wire \s$2983 ; + wire \s$2987 ; + wire \s$2991 ; + wire \s$2995 ; + wire \s$2999 ; + wire \s$3003 ; + wire \s$3007 ; + wire \s$3011 ; + wire \s$3015 ; + wire \s$3019 ; + wire \s$3023 ; + wire \s$3027 ; + wire \s$3031 ; + wire \s$3035 ; + wire \s$3039 ; + wire \s$3043 ; + wire \s$3047 ; + wire \s$3051 ; + wire \s$3055 ; + wire \s$3059 ; + wire \s$3063 ; + wire \s$3067 ; + wire \s$3071 ; + wire \s$3075 ; + wire \s$3079 ; + wire \s$3083 ; + wire \s$3087 ; + wire \s$3091 ; + wire \s$3095 ; + wire \s$3099 ; + wire \s$3103 ; + wire \s$3107 ; + wire \s$3111 ; + wire \s$3115 ; + wire \s$3119 ; + wire \s$3123 ; + wire \s$3127 ; + wire \s$3131 ; + wire \s$3135 ; + wire \s$3139 ; + wire \s$3143 ; + wire \s$3147 ; + wire \s$3151 ; + wire \s$3155 ; + wire \s$3159 ; + wire \s$3163 ; + wire \s$3167 ; + wire \s$3171 ; + wire \s$3175 ; + wire \s$3179 ; + wire \s$3183 ; + wire \s$3187 ; + wire \s$3191 ; + wire \s$3195 ; + wire \s$3199 ; + wire \s$3203 ; + wire \s$3207 ; + wire \s$3211 ; + wire \s$3215 ; + wire \s$3219 ; + wire \s$3223 ; + wire \s$3227 ; + wire \s$3231 ; + wire \s$3235 ; + wire \s$3239 ; + wire \s$3243 ; + wire \s$3247 ; + wire \s$3251 ; + wire \s$3255 ; + wire \s$3259 ; + wire \s$3263 ; + wire \s$3267 ; + wire \s$3271 ; + wire \s$3275 ; + wire \s$3279 ; + wire \s$3283 ; + wire \s$3287 ; + wire \s$3291 ; + wire \s$3295 ; + wire \s$3299 ; + wire \s$3303 ; + wire \s$3307 ; + wire \s$3311 ; + wire \s$3315 ; + wire \s$3319 ; + wire \s$3323 ; + wire \s$3327 ; + wire \s$3331 ; + wire \s$3335 ; + wire \s$3339 ; + wire \s$3343 ; + wire \s$3347 ; + wire \s$3351 ; + wire \s$3355 ; + wire \s$3359 ; + wire \s$3363 ; + wire \s$3367 ; + wire \s$3371 ; + wire \s$3375 ; + wire \s$3379 ; + wire \s$3383 ; + wire \s$3387 ; + wire \s$3391 ; + wire \s$3395 ; + wire \s$3399 ; + wire \s$3403 ; + wire \s$3407 ; + wire \s$3411 ; + wire \s$3415 ; + wire \s$3419 ; + wire \s$3423 ; + wire \s$3427 ; + wire \s$3431 ; + wire \s$3435 ; + wire \s$3439 ; + wire \s$3443 ; + wire \s$3447 ; + wire \s$3451 ; + wire \s$3455 ; + wire \s$3459 ; + wire \s$3463 ; + wire \s$3467 ; + wire \s$3471 ; + wire \s$3475 ; + wire \s$3479 ; + wire \s$3483 ; + wire \s$3487 ; + wire \s$3491 ; + wire \s$3495 ; + wire \s$3499 ; + wire \s$3503 ; + wire \s$3507 ; + wire \s$3511 ; + wire \s$3515 ; + wire \s$3519 ; + wire \s$3523 ; + wire \s$3527 ; + wire \s$3531 ; + wire \s$3535 ; + wire \s$3539 ; + wire \s$3543 ; + wire \s$3547 ; + wire \s$3551 ; + wire \s$3555 ; + wire \s$3559 ; + wire \s$3563 ; + wire \s$3567 ; + wire \s$3571 ; + wire \s$3575 ; + wire \s$3579 ; + wire \s$3583 ; + wire \s$3587 ; + wire \s$3591 ; + wire \s$3595 ; + wire \s$3599 ; + wire \s$3603 ; + wire \s$3607 ; + wire \s$3611 ; + wire \s$3615 ; + wire \s$3619 ; + wire \s$3623 ; + wire \s$3627 ; + wire \s$3631 ; + wire \s$3635 ; + wire \s$3639 ; + wire \s$3643 ; + wire \s$3647 ; + wire \s$3651 ; + wire \s$3655 ; + wire \s$3659 ; + wire \s$3663 ; + wire \s$3667 ; + wire \s$3671 ; + wire \s$3675 ; + wire \s$3679 ; + wire \s$3683 ; + wire \s$3687 ; + wire \s$3691 ; + wire \s$3695 ; + wire \s$3699 ; + wire \s$3703 ; + wire \s$3707 ; + wire \s$3711 ; + wire \s$3715 ; + wire \s$3719 ; + wire \s$3723 ; + wire \s$3727 ; + wire \s$3731 ; + wire \s$3735 ; + wire \s$3739 ; + wire \s$3743 ; + wire \s$3747 ; + wire \s$3751 ; + wire \s$3755 ; + wire \s$3759 ; + wire \s$3763 ; + wire \s$3767 ; + wire \s$3771 ; + wire \s$3775 ; + wire \s$3779 ; + wire \s$3783 ; + wire \s$3787 ; + wire \s$3791 ; + wire \s$3795 ; + wire \s$3799 ; + wire \s$3803 ; + wire \s$3807 ; + wire \s$3811 ; + wire \s$3815 ; + wire \s$3819 ; + wire \s$3823 ; + wire \s$3827 ; + wire \s$3831 ; + wire \s$3835 ; + wire \s$3839 ; + wire \s$3843 ; + wire \s$3847 ; + wire \s$3851 ; + wire \s$3855 ; + wire \s$3859 ; + wire \s$3863 ; + wire \s$3867 ; + wire \s$3871 ; + wire \s$3875 ; + wire \s$3879 ; + wire \s$3883 ; + wire \s$3887 ; + wire \s$3891 ; + wire \s$3895 ; + wire \s$3899 ; + wire \s$3903 ; + wire \s$3907 ; + wire \s$3911 ; + wire \s$3915 ; + wire \s$3919 ; + wire \s$3923 ; + wire \s$3927 ; + wire \s$3931 ; + wire \s$3935 ; + wire \s$3939 ; + wire \s$3943 ; + wire \s$3947 ; + wire \s$3951 ; + wire \s$3955 ; + wire \s$3959 ; + wire \s$3963 ; + wire \s$3967 ; + wire \s$3971 ; + wire \s$3975 ; + wire \s$3979 ; + wire \s$3983 ; + wire \s$3987 ; + wire \s$3991 ; + wire \s$3995 ; + wire \s$3999 ; + wire \s$4003 ; + wire \s$4007 ; + wire \s$4011 ; + wire \s$4015 ; + wire \s$4019 ; + wire \s$4023 ; + wire \s$4027 ; + wire \s$4031 ; + wire \s$4035 ; + wire \s$4039 ; + wire \s$4043 ; + wire \s$4047 ; + wire \s$4051 ; + wire \s$4055 ; + wire \s$4059 ; + wire \s$4063 ; + wire \s$4067 ; + wire \s$4071 ; + wire \s$4075 ; + wire \s$4079 ; + wire \s$4083 ; + wire \s$4087 ; + wire \s$4091 ; + wire \s$4095 ; + wire \s$4099 ; + wire \s$4103 ; + wire \s$4107 ; + wire \s$4111 ; + wire \s$4115 ; + wire \s$4119 ; + wire \s$4123 ; + wire \s$4127 ; + wire \s$4131 ; + wire \s$4135 ; + wire \s$4139 ; + wire \s$4143 ; + wire \s$4147 ; + wire \s$4151 ; + wire \s$4155 ; + wire \s$4159 ; + wire \s$4163 ; + wire \s$4167 ; + wire \s$4171 ; + wire \s$4175 ; + wire \s$4179 ; + wire \s$4183 ; + wire \s$4187 ; + wire \s$4191 ; + wire \s$4195 ; + wire \s$4199 ; + wire \s$4203 ; + wire \s$4207 ; + wire \s$4211 ; + wire \s$4215 ; + wire \s$4219 ; + wire \s$4223 ; + wire \s$4227 ; + wire \s$4231 ; + wire \s$4235 ; + wire \s$4239 ; + wire \s$4243 ; + wire \s$4247 ; + wire \s$4251 ; + wire \s$4255 ; + wire \s$4259 ; + wire \s$4263 ; + wire \s$4267 ; + wire \s$4271 ; + wire \s$4275 ; + wire \s$4279 ; + wire \s$4283 ; + wire \s$4287 ; + wire \s$4291 ; + wire \s$4295 ; + wire \s$4299 ; + wire \s$4303 ; + wire \s$4307 ; + wire \s$4311 ; + wire \s$4315 ; + wire \s$4319 ; + wire \s$4323 ; + wire \s$4327 ; + wire \s$4331 ; + wire \s$4335 ; + wire \s$4339 ; + wire \s$4343 ; + wire \s$4347 ; + wire \s$4351 ; + wire \s$4355 ; + wire \s$4359 ; + wire \s$4363 ; + wire \s$4367 ; + wire \s$4371 ; + wire \s$4375 ; + wire \s$4379 ; + wire \s$4383 ; + wire \s$4387 ; + wire \s$4391 ; + wire \s$4395 ; + wire \s$4399 ; + wire sel_0; + wire \sel_0$1365 ; + wire \sel_0$1402 ; + wire \sel_0$1439 ; + wire \sel_0$1476 ; + wire \sel_0$1513 ; + wire \sel_0$1550 ; + wire \sel_0$1587 ; + wire \sel_0$1624 ; + wire \sel_0$1661 ; + wire \sel_0$1698 ; + wire \sel_0$1735 ; + wire \sel_0$1772 ; + wire \sel_0$1809 ; + wire \sel_0$1846 ; + wire \sel_0$1883 ; + wire \sel_0$1921 ; + wire sel_1; + wire \sel_1$1366 ; + wire \sel_1$1403 ; + wire \sel_1$1440 ; + wire \sel_1$1477 ; + wire \sel_1$1514 ; + wire \sel_1$1551 ; + wire \sel_1$1588 ; + wire \sel_1$1625 ; + wire \sel_1$1662 ; + wire \sel_1$1699 ; + wire \sel_1$1736 ; + wire \sel_1$1773 ; + wire \sel_1$1810 ; + wire \sel_1$1847 ; + wire \sel_1$1884 ; + wire \sel_1$1922 ; + wire sn; + wire \sn$2558 ; + wire \sn$2562 ; + wire \sn$2566 ; + wire \sn$2570 ; + wire \sn$2574 ; + wire \sn$2578 ; + wire \sn$2582 ; + wire \sn$2586 ; + wire \sn$2590 ; + wire \sn$2594 ; + wire \sn$2598 ; + wire \sn$2602 ; + wire \sn$2606 ; + wire \sn$2610 ; + wire \sn$2614 ; + wire \sn$2618 ; + wire \sn$2622 ; + wire \sn$2626 ; + wire \sn$2630 ; + wire \sn$2634 ; + wire \sn$2638 ; + wire \sn$2642 ; + wire \sn$2646 ; + wire \sn$2650 ; + wire \sn$2654 ; + wire \sn$2658 ; + wire \sn$2662 ; + wire \sn$2666 ; + wire \sn$2670 ; + wire \sn$2674 ; + wire \sn$2678 ; + wire \sn$2682 ; + wire \sn$2686 ; + wire \sn$2690 ; + wire \sn$2694 ; + wire \sn$2698 ; + wire \sn$2702 ; + wire \sn$2706 ; + wire \sn$2710 ; + wire \sn$2714 ; + wire \sn$2718 ; + wire \sn$2722 ; + wire \sn$2726 ; + wire \sn$2730 ; + wire \sn$2734 ; + wire \sn$2738 ; + wire \sn$2742 ; + wire \sn$2746 ; + wire \sn$2750 ; + wire \sn$2754 ; + wire \sn$2758 ; + wire \sn$2762 ; + wire \sn$2766 ; + wire \sn$2770 ; + wire \sn$2774 ; + wire \sn$2778 ; + wire \sn$2782 ; + wire \sn$2786 ; + wire \sn$2790 ; + wire \sn$2794 ; + wire \sn$2798 ; + wire \sn$2802 ; + wire \sn$2806 ; + wire \sn$2810 ; + wire \sn$2814 ; + wire \sn$2818 ; + wire \sn$2822 ; + wire \sn$2826 ; + wire \sn$2830 ; + wire \sn$2834 ; + wire \sn$2838 ; + wire \sn$2842 ; + wire \sn$2846 ; + wire \sn$2850 ; + wire \sn$2854 ; + wire \sn$2858 ; + wire \sn$2862 ; + wire \sn$2866 ; + wire \sn$2870 ; + wire \sn$2874 ; + wire \sn$2878 ; + wire \sn$2882 ; + wire \sn$2886 ; + wire \sn$2890 ; + wire \sn$2894 ; + wire \sn$2898 ; + wire \sn$2902 ; + wire \sn$2906 ; + wire \sn$2910 ; + wire \sn$2914 ; + wire \sn$2918 ; + wire \sn$2922 ; + wire \sn$2926 ; + wire \sn$2930 ; + wire \sn$2934 ; + wire \sn$2938 ; + wire \sn$2942 ; + wire \sn$2946 ; + wire \sn$2950 ; + wire \sn$2954 ; + wire \sn$2958 ; + wire \sn$2962 ; + wire \sn$2966 ; + wire \sn$2970 ; + wire \sn$2974 ; + wire \sn$2978 ; + wire \sn$2982 ; + wire \sn$2986 ; + wire \sn$2990 ; + wire \sn$2994 ; + wire \sn$2998 ; + wire \sn$3002 ; + wire \sn$3006 ; + wire \sn$3010 ; + wire \sn$3014 ; + wire \sn$3018 ; + wire \sn$3022 ; + wire \sn$3026 ; + wire \sn$3030 ; + wire \sn$3034 ; + wire \sn$3038 ; + wire \sn$3042 ; + wire \sn$3046 ; + wire \sn$3050 ; + wire \sn$3054 ; + wire \sn$3058 ; + wire \sn$3062 ; + wire \sn$3066 ; + wire \sn$3070 ; + wire \sn$3074 ; + wire \sn$3078 ; + wire \sn$3082 ; + wire \sn$3086 ; + wire \sn$3090 ; + wire \sn$3094 ; + wire \sn$3098 ; + wire \sn$3102 ; + wire \sn$3106 ; + wire \sn$3110 ; + wire \sn$3114 ; + wire \sn$3118 ; + wire \sn$3122 ; + wire \sn$3126 ; + wire \sn$3130 ; + wire \sn$3134 ; + wire \sn$3138 ; + wire \sn$3142 ; + wire \sn$3146 ; + wire \sn$3150 ; + wire \sn$3154 ; + wire \sn$3158 ; + wire \sn$3162 ; + wire \sn$3166 ; + wire \sn$3170 ; + wire \sn$3174 ; + wire \sn$3178 ; + wire \sn$3182 ; + wire \sn$3186 ; + wire \sn$3190 ; + wire \sn$3194 ; + wire \sn$3198 ; + wire \sn$3202 ; + wire \sn$3206 ; + wire \sn$3210 ; + wire \sn$3214 ; + wire \sn$3218 ; + wire \sn$3222 ; + wire \sn$3226 ; + wire \sn$3230 ; + wire \sn$3234 ; + wire \sn$3238 ; + wire \sn$3242 ; + wire \sn$3246 ; + wire \sn$3250 ; + wire \sn$3254 ; + wire \sn$3258 ; + wire \sn$3262 ; + wire \sn$3266 ; + wire \sn$3270 ; + wire \sn$3274 ; + wire \sn$3278 ; + wire \sn$3282 ; + wire \sn$3286 ; + wire \sn$3290 ; + wire \sn$3294 ; + wire \sn$3298 ; + wire \sn$3302 ; + wire \sn$3306 ; + wire \sn$3310 ; + wire \sn$3314 ; + wire \sn$3318 ; + wire \sn$3322 ; + wire \sn$3326 ; + wire \sn$3330 ; + wire \sn$3334 ; + wire \sn$3338 ; + wire \sn$3342 ; + wire \sn$3346 ; + wire \sn$3350 ; + wire \sn$3354 ; + wire \sn$3358 ; + wire \sn$3362 ; + wire \sn$3366 ; + wire \sn$3370 ; + wire \sn$3374 ; + wire \sn$3378 ; + wire \sn$3382 ; + wire \sn$3386 ; + wire \sn$3390 ; + wire \sn$3394 ; + wire \sn$3398 ; + wire \sn$3402 ; + wire \sn$3406 ; + wire \sn$3410 ; + wire \sn$3414 ; + wire \sn$3418 ; + wire \sn$3422 ; + wire \sn$3426 ; + wire \sn$3430 ; + wire \sn$3434 ; + wire \sn$3438 ; + wire \sn$3442 ; + wire \sn$3446 ; + wire \sn$3450 ; + wire \sn$3454 ; + wire \sn$3458 ; + wire \sn$3462 ; + wire \sn$3466 ; + wire \sn$3470 ; + wire \sn$3474 ; + wire \sn$3478 ; + wire \sn$3482 ; + wire \sn$3486 ; + wire \sn$3490 ; + wire \sn$3494 ; + wire \sn$3498 ; + wire \sn$3502 ; + wire \sn$3506 ; + wire \sn$3510 ; + wire \sn$3514 ; + wire \sn$3518 ; + wire \sn$3522 ; + wire \sn$3526 ; + wire \sn$3530 ; + wire \sn$3534 ; + wire \sn$3538 ; + wire \sn$3542 ; + wire \sn$3546 ; + wire \sn$3550 ; + wire \sn$3554 ; + wire \sn$3558 ; + wire \sn$3562 ; + wire \sn$3566 ; + wire \sn$3570 ; + wire \sn$3574 ; + wire \sn$3578 ; + wire \sn$3582 ; + wire \sn$3586 ; + wire \sn$3590 ; + wire \sn$3594 ; + wire \sn$3598 ; + wire \sn$3602 ; + wire \sn$3606 ; + wire \sn$3610 ; + wire \sn$3614 ; + wire \sn$3618 ; + wire \sn$3622 ; + wire \sn$3626 ; + wire \sn$3630 ; + wire \sn$3634 ; + wire \sn$3638 ; + wire \sn$3642 ; + wire \sn$3646 ; + wire \sn$3650 ; + wire \sn$3654 ; + wire \sn$3658 ; + wire \sn$3662 ; + wire \sn$3666 ; + wire \sn$3670 ; + wire \sn$3674 ; + wire \sn$3678 ; + wire \sn$3682 ; + wire \sn$3686 ; + wire \sn$3690 ; + wire \sn$3694 ; + wire \sn$3698 ; + wire \sn$3702 ; + wire \sn$3706 ; + wire \sn$3710 ; + wire \sn$3714 ; + wire \sn$3718 ; + wire \sn$3722 ; + wire \sn$3726 ; + wire \sn$3730 ; + wire \sn$3734 ; + wire \sn$3738 ; + wire \sn$3742 ; + wire \sn$3746 ; + wire \sn$3750 ; + wire \sn$3754 ; + wire \sn$3758 ; + wire \sn$3762 ; + wire \sn$3766 ; + wire \sn$3770 ; + wire \sn$3774 ; + wire \sn$3778 ; + wire \sn$3782 ; + wire \sn$3786 ; + wire \sn$3790 ; + wire \sn$3794 ; + wire \sn$3798 ; + wire \sn$3802 ; + wire \sn$3806 ; + wire \sn$3810 ; + wire \sn$3814 ; + wire \sn$3818 ; + wire \sn$3822 ; + wire \sn$3826 ; + wire \sn$3830 ; + wire \sn$3834 ; + wire \sn$3838 ; + wire \sn$3842 ; + wire \sn$3846 ; + wire \sn$3850 ; + wire \sn$3854 ; + wire \sn$3858 ; + wire \sn$3862 ; + wire \sn$3866 ; + wire \sn$3870 ; + wire \sn$3874 ; + wire \sn$3878 ; + wire \sn$3882 ; + wire \sn$3886 ; + wire \sn$3890 ; + wire \sn$3894 ; + wire \sn$3898 ; + wire \sn$3902 ; + wire \sn$3906 ; + wire \sn$3910 ; + wire \sn$3914 ; + wire \sn$3918 ; + wire \sn$3922 ; + wire \sn$3926 ; + wire \sn$3930 ; + wire \sn$3934 ; + wire \sn$3938 ; + wire \sn$3942 ; + wire \sn$3946 ; + wire \sn$3950 ; + wire \sn$3954 ; + wire \sn$3958 ; + wire \sn$3962 ; + wire \sn$3966 ; + wire \sn$3970 ; + wire \sn$3974 ; + wire \sn$3978 ; + wire \sn$3982 ; + wire \sn$3986 ; + wire \sn$3990 ; + wire \sn$3994 ; + wire \sn$3998 ; + wire \sn$4002 ; + wire \sn$4006 ; + wire \sn$4010 ; + wire \sn$4014 ; + wire \sn$4018 ; + wire \sn$4022 ; + wire \sn$4026 ; + wire \sn$4030 ; + wire \sn$4034 ; + wire \sn$4038 ; + wire \sn$4042 ; + wire \sn$4046 ; + wire \sn$4050 ; + wire \sn$4054 ; + wire \sn$4058 ; + wire \sn$4062 ; + wire \sn$4066 ; + wire \sn$4070 ; + wire \sn$4074 ; + wire \sn$4078 ; + wire \sn$4082 ; + wire \sn$4086 ; + wire \sn$4090 ; + wire \sn$4094 ; + wire \sn$4098 ; + wire \sn$4102 ; + wire \sn$4106 ; + wire \sn$4110 ; + wire \sn$4114 ; + wire \sn$4118 ; + wire \sn$4122 ; + wire \sn$4126 ; + wire \sn$4130 ; + wire \sn$4134 ; + wire \sn$4138 ; + wire \sn$4142 ; + wire \sn$4146 ; + wire \sn$4150 ; + wire \sn$4154 ; + wire \sn$4158 ; + wire \sn$4162 ; + wire \sn$4166 ; + wire \sn$4170 ; + wire \sn$4174 ; + wire \sn$4178 ; + wire \sn$4182 ; + wire \sn$4186 ; + wire \sn$4190 ; + wire \sn$4194 ; + wire \sn$4198 ; + wire \sn$4202 ; + wire \sn$4206 ; + wire \sn$4210 ; + wire \sn$4214 ; + wire \sn$4218 ; + wire \sn$4222 ; + wire \sn$4226 ; + wire \sn$4230 ; + wire \sn$4234 ; + wire \sn$4238 ; + wire \sn$4242 ; + wire \sn$4246 ; + wire \sn$4250 ; + wire \sn$4254 ; + wire \sn$4258 ; + wire \sn$4262 ; + wire \sn$4266 ; + wire \sn$4270 ; + wire \sn$4274 ; + wire \sn$4278 ; + wire \sn$4282 ; + wire \sn$4286 ; + wire \sn$4290 ; + wire \sn$4294 ; + wire \sn$4298 ; + wire \sn$4302 ; + wire \sn$4306 ; + wire \sn$4310 ; + wire \sn$4314 ; + wire \sn$4318 ; + wire \sn$4322 ; + wire \sn$4326 ; + wire \sn$4330 ; + wire \sn$4334 ; + wire \sn$4338 ; + wire \sn$4342 ; + wire \sn$4346 ; + wire \sn$4350 ; + wire \sn$4354 ; + wire \sn$4358 ; + wire \sn$4362 ; + wire \sn$4366 ; + wire \sn$4370 ; + wire \sn$4374 ; + wire \sn$4378 ; + wire \sn$4382 ; + wire \sn$4386 ; + wire \sn$4390 ; + wire \sn$4394 ; + wire \sn$4398 ; + wire \sn$4401 ; + wire \sn$4403 ; + wire \sn$4405 ; + wire \sn$4407 ; + wire \sn$4409 ; + wire \sn$4411 ; + wire \sn$4413 ; + wire \sn$4415 ; + wire \sn$4417 ; + wire \sn$4419 ; + wire \sn$4421 ; + wire \sn$4423 ; + wire \sn$4425 ; + wire \sn$4427 ; + wire \sn$4429 ; + wire \sn$4431 ; + wire \sn$4433 ; + wire \sn$4435 ; + wire \sn$4437 ; + wire \sn$4439 ; + wire \sn$4441 ; + wire \sn$4443 ; + wire \sn$4445 ; + wire \sn$4447 ; + wire \sn$4449 ; + wire \sn$4451 ; + wire \sn$4453 ; + wire \sn$4455 ; + wire \sn$4457 ; + wire \sn$4459 ; + wire \sn$4461 ; + wire \sn$4463 ; + wire \sn$4465 ; + wire \sn$4467 ; + wire \sn$4469 ; + wire \sn$4471 ; + wire \sn$4473 ; + wire \sn$4475 ; + wire \sn$4477 ; + wire \sn$4479 ; + wire \sn$4481 ; + wire \sn$4483 ; + wire \sn$4485 ; + wire \sn$4487 ; + wire \sn$4489 ; + wire \sn$4491 ; + wire \sn$4493 ; + wire \sn$4495 ; + wire \sn$4497 ; + wire \sn$4499 ; + wire \sn$4501 ; + wire \sn$4503 ; + wire \sn$4505 ; + wire \sn$4507 ; + wire \sn$4509 ; + wire \sn$4511 ; + wire \sn$4513 ; + wire \sn$4515 ; + wire \sn$4517 ; + wire \sn$4519 ; + wire \sn$4521 ; + wire \sn$4523 ; + wire \sn$4525 ; + wire t; + wire \t$1976 ; + wire \t$1977 ; + wire \t$1978 ; + wire \t$1979 ; + wire \t$1980 ; + wire \t$1981 ; + wire \t$1982 ; + wire \t$1983 ; + wire \t$1984 ; + wire \t$1985 ; + wire \t$1986 ; + wire \t$1987 ; + wire \t$1988 ; + wire \t$1989 ; + wire \t$1990 ; + wire \t$1991 ; + wire \t$1992 ; + wire \t$1993 ; + wire \t$1994 ; + wire \t$1995 ; + wire \t$1996 ; + wire \t$1997 ; + wire \t$1998 ; + wire \t$1999 ; + wire \t$2000 ; + wire \t$2001 ; + wire \t$2002 ; + wire \t$2003 ; + wire \t$2004 ; + wire \t$2005 ; + wire \t$2006 ; + wire \t$2007 ; + wire \t$2009 ; + wire \t$2010 ; + wire \t$2011 ; + wire \t$2012 ; + wire \t$2013 ; + wire \t$2014 ; + wire \t$2015 ; + wire \t$2016 ; + wire \t$2017 ; + wire \t$2018 ; + wire \t$2019 ; + wire \t$2020 ; + wire \t$2021 ; + wire \t$2022 ; + wire \t$2023 ; + wire \t$2024 ; + wire \t$2025 ; + wire \t$2026 ; + wire \t$2027 ; + wire \t$2028 ; + wire \t$2029 ; + wire \t$2030 ; + wire \t$2031 ; + wire \t$2032 ; + wire \t$2033 ; + wire \t$2034 ; + wire \t$2035 ; + wire \t$2036 ; + wire \t$2037 ; + wire \t$2038 ; + wire \t$2039 ; + wire \t$2040 ; + wire \t$2041 ; + wire \t$2043 ; + wire \t$2044 ; + wire \t$2045 ; + wire \t$2046 ; + wire \t$2047 ; + wire \t$2048 ; + wire \t$2049 ; + wire \t$2050 ; + wire \t$2051 ; + wire \t$2052 ; + wire \t$2053 ; + wire \t$2054 ; + wire \t$2055 ; + wire \t$2056 ; + wire \t$2057 ; + wire \t$2058 ; + wire \t$2059 ; + wire \t$2060 ; + wire \t$2061 ; + wire \t$2062 ; + wire \t$2063 ; + wire \t$2064 ; + wire \t$2065 ; + wire \t$2066 ; + wire \t$2067 ; + wire \t$2068 ; + wire \t$2069 ; + wire \t$2070 ; + wire \t$2071 ; + wire \t$2072 ; + wire \t$2073 ; + wire \t$2074 ; + wire \t$2075 ; + wire \t$2077 ; + wire \t$2078 ; + wire \t$2079 ; + wire \t$2080 ; + wire \t$2081 ; + wire \t$2082 ; + wire \t$2083 ; + wire \t$2084 ; + wire \t$2085 ; + wire \t$2086 ; + wire \t$2087 ; + wire \t$2088 ; + wire \t$2089 ; + wire \t$2090 ; + wire \t$2091 ; + wire \t$2092 ; + wire \t$2093 ; + wire \t$2094 ; + wire \t$2095 ; + wire \t$2096 ; + wire \t$2097 ; + wire \t$2098 ; + wire \t$2099 ; + wire \t$2100 ; + wire \t$2101 ; + wire \t$2102 ; + wire \t$2103 ; + wire \t$2104 ; + wire \t$2105 ; + wire \t$2106 ; + wire \t$2107 ; + wire \t$2108 ; + wire \t$2109 ; + wire \t$2111 ; + wire \t$2112 ; + wire \t$2113 ; + wire \t$2114 ; + wire \t$2115 ; + wire \t$2116 ; + wire \t$2117 ; + wire \t$2118 ; + wire \t$2119 ; + wire \t$2120 ; + wire \t$2121 ; + wire \t$2122 ; + wire \t$2123 ; + wire \t$2124 ; + wire \t$2125 ; + wire \t$2126 ; + wire \t$2127 ; + wire \t$2128 ; + wire \t$2129 ; + wire \t$2130 ; + wire \t$2131 ; + wire \t$2132 ; + wire \t$2133 ; + wire \t$2134 ; + wire \t$2135 ; + wire \t$2136 ; + wire \t$2137 ; + wire \t$2138 ; + wire \t$2139 ; + wire \t$2140 ; + wire \t$2141 ; + wire \t$2142 ; + wire \t$2143 ; + wire \t$2145 ; + wire \t$2146 ; + wire \t$2147 ; + wire \t$2148 ; + wire \t$2149 ; + wire \t$2150 ; + wire \t$2151 ; + wire \t$2152 ; + wire \t$2153 ; + wire \t$2154 ; + wire \t$2155 ; + wire \t$2156 ; + wire \t$2157 ; + wire \t$2158 ; + wire \t$2159 ; + wire \t$2160 ; + wire \t$2161 ; + wire \t$2162 ; + wire \t$2163 ; + wire \t$2164 ; + wire \t$2165 ; + wire \t$2166 ; + wire \t$2167 ; + wire \t$2168 ; + wire \t$2169 ; + wire \t$2170 ; + wire \t$2171 ; + wire \t$2172 ; + wire \t$2173 ; + wire \t$2174 ; + wire \t$2175 ; + wire \t$2176 ; + wire \t$2177 ; + wire \t$2179 ; + wire \t$2180 ; + wire \t$2181 ; + wire \t$2182 ; + wire \t$2183 ; + wire \t$2184 ; + wire \t$2185 ; + wire \t$2186 ; + wire \t$2187 ; + wire \t$2188 ; + wire \t$2189 ; + wire \t$2190 ; + wire \t$2191 ; + wire \t$2192 ; + wire \t$2193 ; + wire \t$2194 ; + wire \t$2195 ; + wire \t$2196 ; + wire \t$2197 ; + wire \t$2198 ; + wire \t$2199 ; + wire \t$2200 ; + wire \t$2201 ; + wire \t$2202 ; + wire \t$2203 ; + wire \t$2204 ; + wire \t$2205 ; + wire \t$2206 ; + wire \t$2207 ; + wire \t$2208 ; + wire \t$2209 ; + wire \t$2210 ; + wire \t$2211 ; + wire \t$2213 ; + wire \t$2214 ; + wire \t$2215 ; + wire \t$2216 ; + wire \t$2217 ; + wire \t$2218 ; + wire \t$2219 ; + wire \t$2220 ; + wire \t$2221 ; + wire \t$2222 ; + wire \t$2223 ; + wire \t$2224 ; + wire \t$2225 ; + wire \t$2226 ; + wire \t$2227 ; + wire \t$2228 ; + wire \t$2229 ; + wire \t$2230 ; + wire \t$2231 ; + wire \t$2232 ; + wire \t$2233 ; + wire \t$2234 ; + wire \t$2235 ; + wire \t$2236 ; + wire \t$2237 ; + wire \t$2238 ; + wire \t$2239 ; + wire \t$2240 ; + wire \t$2241 ; + wire \t$2242 ; + wire \t$2243 ; + wire \t$2244 ; + wire \t$2245 ; + wire \t$2247 ; + wire \t$2248 ; + wire \t$2249 ; + wire \t$2250 ; + wire \t$2251 ; + wire \t$2252 ; + wire \t$2253 ; + wire \t$2254 ; + wire \t$2255 ; + wire \t$2256 ; + wire \t$2257 ; + wire \t$2258 ; + wire \t$2259 ; + wire \t$2260 ; + wire \t$2261 ; + wire \t$2262 ; + wire \t$2263 ; + wire \t$2264 ; + wire \t$2265 ; + wire \t$2266 ; + wire \t$2267 ; + wire \t$2268 ; + wire \t$2269 ; + wire \t$2270 ; + wire \t$2271 ; + wire \t$2272 ; + wire \t$2273 ; + wire \t$2274 ; + wire \t$2275 ; + wire \t$2276 ; + wire \t$2277 ; + wire \t$2278 ; + wire \t$2279 ; + wire \t$2281 ; + wire \t$2282 ; + wire \t$2283 ; + wire \t$2284 ; + wire \t$2285 ; + wire \t$2286 ; + wire \t$2287 ; + wire \t$2288 ; + wire \t$2289 ; + wire \t$2290 ; + wire \t$2291 ; + wire \t$2292 ; + wire \t$2293 ; + wire \t$2294 ; + wire \t$2295 ; + wire \t$2296 ; + wire \t$2297 ; + wire \t$2298 ; + wire \t$2299 ; + wire \t$2300 ; + wire \t$2301 ; + wire \t$2302 ; + wire \t$2303 ; + wire \t$2304 ; + wire \t$2305 ; + wire \t$2306 ; + wire \t$2307 ; + wire \t$2308 ; + wire \t$2309 ; + wire \t$2310 ; + wire \t$2311 ; + wire \t$2312 ; + wire \t$2313 ; + wire \t$2315 ; + wire \t$2316 ; + wire \t$2317 ; + wire \t$2318 ; + wire \t$2319 ; + wire \t$2320 ; + wire \t$2321 ; + wire \t$2322 ; + wire \t$2323 ; + wire \t$2324 ; + wire \t$2325 ; + wire \t$2326 ; + wire \t$2327 ; + wire \t$2328 ; + wire \t$2329 ; + wire \t$2330 ; + wire \t$2331 ; + wire \t$2332 ; + wire \t$2333 ; + wire \t$2334 ; + wire \t$2335 ; + wire \t$2336 ; + wire \t$2337 ; + wire \t$2338 ; + wire \t$2339 ; + wire \t$2340 ; + wire \t$2341 ; + wire \t$2342 ; + wire \t$2343 ; + wire \t$2344 ; + wire \t$2345 ; + wire \t$2346 ; + wire \t$2347 ; + wire \t$2349 ; + wire \t$2350 ; + wire \t$2351 ; + wire \t$2352 ; + wire \t$2353 ; + wire \t$2354 ; + wire \t$2355 ; + wire \t$2356 ; + wire \t$2357 ; + wire \t$2358 ; + wire \t$2359 ; + wire \t$2360 ; + wire \t$2361 ; + wire \t$2362 ; + wire \t$2363 ; + wire \t$2364 ; + wire \t$2365 ; + wire \t$2366 ; + wire \t$2367 ; + wire \t$2368 ; + wire \t$2369 ; + wire \t$2370 ; + wire \t$2371 ; + wire \t$2372 ; + wire \t$2373 ; + wire \t$2374 ; + wire \t$2375 ; + wire \t$2376 ; + wire \t$2377 ; + wire \t$2378 ; + wire \t$2379 ; + wire \t$2380 ; + wire \t$2381 ; + wire \t$2383 ; + wire \t$2384 ; + wire \t$2385 ; + wire \t$2386 ; + wire \t$2387 ; + wire \t$2388 ; + wire \t$2389 ; + wire \t$2390 ; + wire \t$2391 ; + wire \t$2392 ; + wire \t$2393 ; + wire \t$2394 ; + wire \t$2395 ; + wire \t$2396 ; + wire \t$2397 ; + wire \t$2398 ; + wire \t$2399 ; + wire \t$2400 ; + wire \t$2401 ; + wire \t$2402 ; + wire \t$2403 ; + wire \t$2404 ; + wire \t$2405 ; + wire \t$2406 ; + wire \t$2407 ; + wire \t$2408 ; + wire \t$2409 ; + wire \t$2410 ; + wire \t$2411 ; + wire \t$2412 ; + wire \t$2413 ; + wire \t$2414 ; + wire \t$2415 ; + wire \t$2417 ; + wire \t$2418 ; + wire \t$2419 ; + wire \t$2420 ; + wire \t$2421 ; + wire \t$2422 ; + wire \t$2423 ; + wire \t$2424 ; + wire \t$2425 ; + wire \t$2426 ; + wire \t$2427 ; + wire \t$2428 ; + wire \t$2429 ; + wire \t$2430 ; + wire \t$2431 ; + wire \t$2432 ; + wire \t$2433 ; + wire \t$2434 ; + wire \t$2435 ; + wire \t$2436 ; + wire \t$2437 ; + wire \t$2438 ; + wire \t$2439 ; + wire \t$2440 ; + wire \t$2441 ; + wire \t$2442 ; + wire \t$2443 ; + wire \t$2444 ; + wire \t$2445 ; + wire \t$2446 ; + wire \t$2447 ; + wire \t$2448 ; + wire \t$2449 ; + wire \t$2451 ; + wire \t$2452 ; + wire \t$2453 ; + wire \t$2454 ; + wire \t$2455 ; + wire \t$2456 ; + wire \t$2457 ; + wire \t$2458 ; + wire \t$2459 ; + wire \t$2460 ; + wire \t$2461 ; + wire \t$2462 ; + wire \t$2463 ; + wire \t$2464 ; + wire \t$2465 ; + wire \t$2466 ; + wire \t$2467 ; + wire \t$2468 ; + wire \t$2469 ; + wire \t$2470 ; + wire \t$2471 ; + wire \t$2472 ; + wire \t$2473 ; + wire \t$2474 ; + wire \t$2475 ; + wire \t$2476 ; + wire \t$2477 ; + wire \t$2478 ; + wire \t$2479 ; + wire \t$2480 ; + wire \t$2481 ; + wire \t$2482 ; + wire \t$2483 ; + wire \t$2485 ; + wire \t$2486 ; + wire \t$2487 ; + wire \t$2488 ; + wire \t$2489 ; + wire \t$2490 ; + wire \t$2491 ; + wire \t$2492 ; + wire \t$2493 ; + wire \t$2494 ; + wire \t$2495 ; + wire \t$2496 ; + wire \t$2497 ; + wire \t$2498 ; + wire \t$2499 ; + wire \t$2500 ; + wire \t$2501 ; + wire \t$2502 ; + wire \t$2503 ; + wire \t$2504 ; + wire \t$2505 ; + wire \t$2506 ; + wire \t$2507 ; + wire \t$2508 ; + wire \t$2509 ; + wire \t$2510 ; + wire \t$2511 ; + wire \t$2512 ; + wire \t$2513 ; + wire \t$2514 ; + wire \t$2515 ; + wire \t$2516 ; + wire \t$2517 ; + wire \t$2519 ; + wire \t$2520 ; + wire \t$2521 ; + wire \t$2522 ; + wire \t$2523 ; + wire \t$2524 ; + wire \t$2525 ; + wire \t$2526 ; + wire \t$2527 ; + wire \t$2528 ; + wire \t$2529 ; + wire \t$2530 ; + wire \t$2531 ; + wire \t$2532 ; + wire \t$2533 ; + wire \t$2534 ; + wire \t$2535 ; + wire \t$2536 ; + wire \t$2537 ; + wire \t$2538 ; + wire \t$2539 ; + wire \t$2540 ; + wire \t$2541 ; + wire \t$2542 ; + wire \t$2543 ; + wire \t$2544 ; + wire \t$2545 ; + wire \t$2546 ; + wire \t$2547 ; + wire \t$2548 ; + wire \t$2549 ; + wire \t$2550 ; + wire \t$2551 ; + always @(posedge clk) + a_registered <= a; + always @(posedge clk) + b_registered <= b; + always @(posedge clk) + pp_row0_0 <= booth_b0_m0; + always @(posedge clk) + pp_row0_1 <= a_registered[1]; + always @(posedge clk) + pp_row1_0 <= booth_b0_m1; + always @(posedge clk) + pp_row2_0 <= booth_b0_m2; + always @(posedge clk) + pp_row2_1 <= booth_b2_m0; + always @(posedge clk) + pp_row2_2 <= a_registered[3]; + always @(posedge clk) + pp_row3_0 <= booth_b0_m3; + always @(posedge clk) + pp_row3_1 <= booth_b2_m1; + always @(posedge clk) + pp_row4_0 <= booth_b0_m4; + always @(posedge clk) + pp_row4_1 <= booth_b2_m2; + always @(posedge clk) + pp_row4_2 <= booth_b4_m0; + always @(posedge clk) + pp_row4_3 <= a_registered[5]; + always @(posedge clk) + pp_row5_0 <= booth_b0_m5; + always @(posedge clk) + pp_row5_1 <= booth_b2_m3; + always @(posedge clk) + pp_row5_2 <= booth_b4_m1; + always @(posedge clk) + pp_row6_0 <= booth_b0_m6; + always @(posedge clk) + pp_row6_1 <= booth_b2_m4; + always @(posedge clk) + pp_row6_2 <= booth_b4_m2; + always @(posedge clk) + pp_row6_3 <= booth_b6_m0; + always @(posedge clk) + pp_row6_4 <= a_registered[7]; + always @(posedge clk) + pp_row7_0 <= booth_b0_m7; + always @(posedge clk) + pp_row7_1 <= booth_b2_m5; + always @(posedge clk) + pp_row7_2 <= booth_b4_m3; + always @(posedge clk) + pp_row7_3 <= booth_b6_m1; + always @(posedge clk) + pp_row8_0 <= booth_b0_m8; + always @(posedge clk) + pp_row8_1 <= booth_b2_m6; + always @(posedge clk) + pp_row8_2 <= booth_b4_m4; + always @(posedge clk) + pp_row8_3 <= booth_b6_m2; + always @(posedge clk) + pp_row8_4 <= booth_b8_m0; + always @(posedge clk) + pp_row8_5 <= a_registered[9]; + always @(posedge clk) + pp_row9_0 <= booth_b0_m9; + always @(posedge clk) + pp_row9_1 <= booth_b2_m7; + always @(posedge clk) + pp_row9_2 <= booth_b4_m5; + always @(posedge clk) + pp_row9_3 <= booth_b6_m3; + always @(posedge clk) + pp_row9_4 <= booth_b8_m1; + always @(posedge clk) + pp_row10_0 <= booth_b0_m10; + always @(posedge clk) + pp_row10_1 <= booth_b2_m8; + always @(posedge clk) + pp_row10_2 <= booth_b4_m6; + always @(posedge clk) + pp_row10_3 <= booth_b6_m4; + always @(posedge clk) + pp_row10_4 <= booth_b8_m2; + always @(posedge clk) + pp_row10_5 <= booth_b10_m0; + always @(posedge clk) + pp_row10_6 <= a_registered[11]; + always @(posedge clk) + pp_row11_0 <= booth_b0_m11; + always @(posedge clk) + pp_row11_1 <= booth_b2_m9; + always @(posedge clk) + pp_row11_2 <= booth_b4_m7; + always @(posedge clk) + pp_row11_3 <= booth_b6_m5; + always @(posedge clk) + pp_row11_4 <= booth_b8_m3; + always @(posedge clk) + pp_row11_5 <= booth_b10_m1; + always @(posedge clk) + pp_row12_0 <= booth_b0_m12; + always @(posedge clk) + pp_row12_1 <= booth_b2_m10; + always @(posedge clk) + pp_row12_2 <= booth_b4_m8; + always @(posedge clk) + pp_row12_3 <= booth_b6_m6; + always @(posedge clk) + pp_row12_4 <= booth_b8_m4; + always @(posedge clk) + pp_row12_5 <= booth_b10_m2; + always @(posedge clk) + pp_row12_6 <= booth_b12_m0; + always @(posedge clk) + pp_row12_7 <= a_registered[13]; + always @(posedge clk) + pp_row13_0 <= booth_b0_m13; + always @(posedge clk) + pp_row13_1 <= booth_b2_m11; + always @(posedge clk) + pp_row13_2 <= booth_b4_m9; + always @(posedge clk) + pp_row13_3 <= booth_b6_m7; + always @(posedge clk) + pp_row13_4 <= booth_b8_m5; + always @(posedge clk) + pp_row13_5 <= booth_b10_m3; + always @(posedge clk) + pp_row13_6 <= booth_b12_m1; + always @(posedge clk) + pp_row14_0 <= booth_b0_m14; + always @(posedge clk) + pp_row14_1 <= booth_b2_m12; + always @(posedge clk) + pp_row14_2 <= booth_b4_m10; + always @(posedge clk) + pp_row14_3 <= booth_b6_m8; + always @(posedge clk) + pp_row14_4 <= booth_b8_m6; + always @(posedge clk) + pp_row14_5 <= booth_b10_m4; + always @(posedge clk) + pp_row14_6 <= booth_b12_m2; + always @(posedge clk) + pp_row14_7 <= booth_b14_m0; + always @(posedge clk) + pp_row14_8 <= a_registered[15]; + always @(posedge clk) + pp_row15_0 <= booth_b0_m15; + always @(posedge clk) + pp_row15_1 <= booth_b2_m13; + always @(posedge clk) + pp_row15_2 <= booth_b4_m11; + always @(posedge clk) + pp_row15_3 <= booth_b6_m9; + always @(posedge clk) + pp_row15_4 <= booth_b8_m7; + always @(posedge clk) + pp_row15_5 <= booth_b10_m5; + always @(posedge clk) + pp_row15_6 <= booth_b12_m3; + always @(posedge clk) + pp_row15_7 <= booth_b14_m1; + always @(posedge clk) + pp_row16_0 <= booth_b0_m16; + always @(posedge clk) + pp_row16_1 <= booth_b2_m14; + always @(posedge clk) + pp_row16_2 <= booth_b4_m12; + always @(posedge clk) + pp_row16_3 <= booth_b6_m10; + always @(posedge clk) + pp_row16_4 <= booth_b8_m8; + always @(posedge clk) + pp_row16_5 <= booth_b10_m6; + always @(posedge clk) + pp_row16_6 <= booth_b12_m4; + always @(posedge clk) + pp_row16_7 <= booth_b14_m2; + always @(posedge clk) + pp_row16_8 <= booth_b16_m0; + always @(posedge clk) + pp_row16_9 <= a_registered[17]; + always @(posedge clk) + pp_row17_0 <= booth_b0_m17; + always @(posedge clk) + pp_row17_1 <= booth_b2_m15; + always @(posedge clk) + pp_row17_2 <= booth_b4_m13; + always @(posedge clk) + pp_row17_3 <= booth_b6_m11; + always @(posedge clk) + pp_row17_4 <= booth_b8_m9; + always @(posedge clk) + pp_row17_5 <= booth_b10_m7; + always @(posedge clk) + pp_row17_6 <= booth_b12_m5; + always @(posedge clk) + pp_row17_7 <= booth_b14_m3; + always @(posedge clk) + pp_row17_8 <= booth_b16_m1; + always @(posedge clk) + pp_row18_0 <= booth_b0_m18; + always @(posedge clk) + pp_row18_1 <= booth_b2_m16; + always @(posedge clk) + pp_row18_2 <= booth_b4_m14; + always @(posedge clk) + pp_row18_3 <= booth_b6_m12; + always @(posedge clk) + pp_row18_4 <= booth_b8_m10; + always @(posedge clk) + pp_row18_5 <= booth_b10_m8; + always @(posedge clk) + pp_row18_6 <= booth_b12_m6; + always @(posedge clk) + pp_row18_7 <= booth_b14_m4; + always @(posedge clk) + pp_row18_8 <= booth_b16_m2; + always @(posedge clk) + pp_row18_9 <= booth_b18_m0; + always @(posedge clk) + pp_row18_10 <= a_registered[19]; + always @(posedge clk) + pp_row19_0 <= booth_b0_m19; + always @(posedge clk) + pp_row19_1 <= booth_b2_m17; + always @(posedge clk) + pp_row19_2 <= booth_b4_m15; + always @(posedge clk) + pp_row19_3 <= booth_b6_m13; + always @(posedge clk) + pp_row19_4 <= booth_b8_m11; + always @(posedge clk) + pp_row19_5 <= booth_b10_m9; + always @(posedge clk) + pp_row19_6 <= booth_b12_m7; + always @(posedge clk) + pp_row19_7 <= booth_b14_m5; + always @(posedge clk) + pp_row19_8 <= booth_b16_m3; + always @(posedge clk) + pp_row19_9 <= booth_b18_m1; + always @(posedge clk) + pp_row20_0 <= booth_b0_m20; + always @(posedge clk) + pp_row20_1 <= booth_b2_m18; + always @(posedge clk) + pp_row20_2 <= booth_b4_m16; + always @(posedge clk) + pp_row20_3 <= booth_b6_m14; + always @(posedge clk) + pp_row20_4 <= booth_b8_m12; + always @(posedge clk) + pp_row20_5 <= booth_b10_m10; + always @(posedge clk) + pp_row20_6 <= booth_b12_m8; + always @(posedge clk) + pp_row20_7 <= booth_b14_m6; + always @(posedge clk) + pp_row20_8 <= booth_b16_m4; + always @(posedge clk) + pp_row20_9 <= booth_b18_m2; + always @(posedge clk) + pp_row20_10 <= booth_b20_m0; + always @(posedge clk) + pp_row20_11 <= a_registered[21]; + always @(posedge clk) + pp_row21_0 <= booth_b0_m21; + always @(posedge clk) + pp_row21_1 <= booth_b2_m19; + always @(posedge clk) + pp_row21_2 <= booth_b4_m17; + always @(posedge clk) + pp_row21_3 <= booth_b6_m15; + always @(posedge clk) + pp_row21_4 <= booth_b8_m13; + always @(posedge clk) + pp_row21_5 <= booth_b10_m11; + always @(posedge clk) + pp_row21_6 <= booth_b12_m9; + always @(posedge clk) + pp_row21_7 <= booth_b14_m7; + always @(posedge clk) + pp_row21_8 <= booth_b16_m5; + always @(posedge clk) + pp_row21_9 <= booth_b18_m3; + always @(posedge clk) + pp_row21_10 <= booth_b20_m1; + always @(posedge clk) + pp_row22_0 <= booth_b0_m22; + always @(posedge clk) + pp_row22_1 <= booth_b2_m20; + always @(posedge clk) + pp_row22_2 <= booth_b4_m18; + always @(posedge clk) + pp_row22_3 <= booth_b6_m16; + always @(posedge clk) + pp_row22_4 <= booth_b8_m14; + always @(posedge clk) + pp_row22_5 <= booth_b10_m12; + always @(posedge clk) + pp_row22_6 <= booth_b12_m10; + always @(posedge clk) + pp_row22_7 <= booth_b14_m8; + always @(posedge clk) + pp_row22_8 <= booth_b16_m6; + always @(posedge clk) + pp_row22_9 <= booth_b18_m4; + always @(posedge clk) + pp_row22_10 <= booth_b20_m2; + always @(posedge clk) + pp_row22_11 <= booth_b22_m0; + always @(posedge clk) + pp_row22_12 <= a_registered[23]; + always @(posedge clk) + pp_row23_0 <= booth_b0_m23; + always @(posedge clk) + pp_row23_1 <= booth_b2_m21; + always @(posedge clk) + pp_row23_2 <= booth_b4_m19; + always @(posedge clk) + pp_row23_3 <= booth_b6_m17; + always @(posedge clk) + pp_row23_4 <= booth_b8_m15; + always @(posedge clk) + pp_row23_5 <= booth_b10_m13; + always @(posedge clk) + pp_row23_6 <= booth_b12_m11; + always @(posedge clk) + pp_row23_7 <= booth_b14_m9; + always @(posedge clk) + pp_row23_8 <= booth_b16_m7; + always @(posedge clk) + pp_row23_9 <= booth_b18_m5; + always @(posedge clk) + pp_row23_10 <= booth_b20_m3; + always @(posedge clk) + pp_row23_11 <= booth_b22_m1; + always @(posedge clk) + pp_row24_0 <= booth_b0_m24; + always @(posedge clk) + pp_row24_1 <= booth_b2_m22; + always @(posedge clk) + pp_row24_2 <= booth_b4_m20; + always @(posedge clk) + pp_row24_3 <= booth_b6_m18; + always @(posedge clk) + pp_row24_4 <= booth_b8_m16; + always @(posedge clk) + pp_row24_5 <= booth_b10_m14; + always @(posedge clk) + pp_row24_6 <= booth_b12_m12; + always @(posedge clk) + pp_row24_7 <= booth_b14_m10; + always @(posedge clk) + pp_row24_8 <= booth_b16_m8; + always @(posedge clk) + pp_row24_9 <= booth_b18_m6; + always @(posedge clk) + pp_row24_10 <= booth_b20_m4; + always @(posedge clk) + pp_row24_11 <= booth_b22_m2; + always @(posedge clk) + pp_row24_12 <= booth_b24_m0; + always @(posedge clk) + pp_row24_13 <= a_registered[25]; + always @(posedge clk) + pp_row25_0 <= booth_b0_m25; + always @(posedge clk) + pp_row25_1 <= booth_b2_m23; + always @(posedge clk) + pp_row25_2 <= booth_b4_m21; + always @(posedge clk) + pp_row25_3 <= booth_b6_m19; + always @(posedge clk) + pp_row25_4 <= booth_b8_m17; + always @(posedge clk) + pp_row25_5 <= booth_b10_m15; + always @(posedge clk) + pp_row25_6 <= booth_b12_m13; + always @(posedge clk) + pp_row25_7 <= booth_b14_m11; + always @(posedge clk) + pp_row25_8 <= booth_b16_m9; + always @(posedge clk) + pp_row25_9 <= booth_b18_m7; + always @(posedge clk) + pp_row25_10 <= booth_b20_m5; + always @(posedge clk) + pp_row25_11 <= booth_b22_m3; + always @(posedge clk) + pp_row25_12 <= booth_b24_m1; + always @(posedge clk) + pp_row26_0 <= booth_b0_m26; + always @(posedge clk) + pp_row26_1 <= booth_b2_m24; + always @(posedge clk) + pp_row26_2 <= booth_b4_m22; + always @(posedge clk) + pp_row26_3 <= booth_b6_m20; + always @(posedge clk) + pp_row26_4 <= booth_b8_m18; + always @(posedge clk) + pp_row26_5 <= booth_b10_m16; + always @(posedge clk) + pp_row26_6 <= booth_b12_m14; + always @(posedge clk) + pp_row26_7 <= booth_b14_m12; + always @(posedge clk) + pp_row26_8 <= booth_b16_m10; + always @(posedge clk) + pp_row26_9 <= booth_b18_m8; + always @(posedge clk) + pp_row26_10 <= booth_b20_m6; + always @(posedge clk) + pp_row26_11 <= booth_b22_m4; + always @(posedge clk) + pp_row26_12 <= booth_b24_m2; + always @(posedge clk) + pp_row26_13 <= booth_b26_m0; + always @(posedge clk) + pp_row26_14 <= a_registered[27]; + always @(posedge clk) + pp_row27_0 <= booth_b0_m27; + always @(posedge clk) + pp_row27_1 <= booth_b2_m25; + always @(posedge clk) + pp_row27_2 <= booth_b4_m23; + always @(posedge clk) + pp_row27_3 <= booth_b6_m21; + always @(posedge clk) + pp_row27_4 <= booth_b8_m19; + always @(posedge clk) + pp_row27_5 <= booth_b10_m17; + always @(posedge clk) + pp_row27_6 <= booth_b12_m15; + always @(posedge clk) + pp_row27_7 <= booth_b14_m13; + always @(posedge clk) + pp_row27_8 <= booth_b16_m11; + always @(posedge clk) + pp_row27_9 <= booth_b18_m9; + always @(posedge clk) + pp_row27_10 <= booth_b20_m7; + always @(posedge clk) + pp_row27_11 <= booth_b22_m5; + always @(posedge clk) + pp_row27_12 <= booth_b24_m3; + always @(posedge clk) + pp_row27_13 <= booth_b26_m1; + always @(posedge clk) + pp_row28_0 <= booth_b0_m28; + always @(posedge clk) + pp_row28_1 <= booth_b2_m26; + always @(posedge clk) + pp_row28_2 <= booth_b4_m24; + always @(posedge clk) + pp_row28_3 <= booth_b6_m22; + always @(posedge clk) + pp_row28_4 <= booth_b8_m20; + always @(posedge clk) + pp_row28_5 <= booth_b10_m18; + always @(posedge clk) + pp_row28_6 <= booth_b12_m16; + always @(posedge clk) + pp_row28_7 <= booth_b14_m14; + always @(posedge clk) + pp_row28_8 <= booth_b16_m12; + always @(posedge clk) + pp_row28_9 <= booth_b18_m10; + always @(posedge clk) + pp_row28_10 <= booth_b20_m8; + always @(posedge clk) + pp_row28_11 <= booth_b22_m6; + always @(posedge clk) + pp_row28_12 <= booth_b24_m4; + always @(posedge clk) + pp_row28_13 <= booth_b26_m2; + always @(posedge clk) + pp_row28_14 <= booth_b28_m0; + always @(posedge clk) + pp_row28_15 <= a_registered[29]; + always @(posedge clk) + pp_row29_0 <= booth_b0_m29; + always @(posedge clk) + pp_row29_1 <= booth_b2_m27; + always @(posedge clk) + pp_row29_2 <= booth_b4_m25; + always @(posedge clk) + pp_row29_3 <= booth_b6_m23; + always @(posedge clk) + pp_row29_4 <= booth_b8_m21; + always @(posedge clk) + pp_row29_5 <= booth_b10_m19; + always @(posedge clk) + pp_row29_6 <= booth_b12_m17; + always @(posedge clk) + pp_row29_7 <= booth_b14_m15; + always @(posedge clk) + pp_row29_8 <= booth_b16_m13; + always @(posedge clk) + pp_row29_9 <= booth_b18_m11; + always @(posedge clk) + pp_row29_10 <= booth_b20_m9; + always @(posedge clk) + pp_row29_11 <= booth_b22_m7; + always @(posedge clk) + pp_row29_12 <= booth_b24_m5; + always @(posedge clk) + pp_row29_13 <= booth_b26_m3; + always @(posedge clk) + pp_row29_14 <= booth_b28_m1; + always @(posedge clk) + pp_row30_0 <= booth_b0_m30; + always @(posedge clk) + pp_row30_1 <= booth_b2_m28; + always @(posedge clk) + pp_row30_2 <= booth_b4_m26; + always @(posedge clk) + pp_row30_3 <= booth_b6_m24; + always @(posedge clk) + pp_row30_4 <= booth_b8_m22; + always @(posedge clk) + pp_row30_5 <= booth_b10_m20; + always @(posedge clk) + pp_row30_6 <= booth_b12_m18; + always @(posedge clk) + pp_row30_7 <= booth_b14_m16; + always @(posedge clk) + pp_row30_8 <= booth_b16_m14; + always @(posedge clk) + pp_row30_9 <= booth_b18_m12; + always @(posedge clk) + pp_row30_10 <= booth_b20_m10; + always @(posedge clk) + pp_row30_11 <= booth_b22_m8; + always @(posedge clk) + pp_row30_12 <= booth_b24_m6; + always @(posedge clk) + pp_row30_13 <= booth_b26_m4; + always @(posedge clk) + pp_row30_14 <= booth_b28_m2; + always @(posedge clk) + pp_row30_15 <= booth_b30_m0; + always @(posedge clk) + pp_row30_16 <= a_registered[31]; + always @(posedge clk) + pp_row31_0 <= booth_b0_m31; + always @(posedge clk) + pp_row31_1 <= booth_b2_m29; + always @(posedge clk) + pp_row31_2 <= booth_b4_m27; + always @(posedge clk) + pp_row31_3 <= booth_b6_m25; + always @(posedge clk) + pp_row31_4 <= booth_b8_m23; + always @(posedge clk) + pp_row31_5 <= booth_b10_m21; + always @(posedge clk) + pp_row31_6 <= booth_b12_m19; + always @(posedge clk) + pp_row31_7 <= booth_b14_m17; + always @(posedge clk) + pp_row31_8 <= booth_b16_m15; + always @(posedge clk) + pp_row31_9 <= booth_b18_m13; + always @(posedge clk) + pp_row31_10 <= booth_b20_m11; + always @(posedge clk) + pp_row31_11 <= booth_b22_m9; + always @(posedge clk) + pp_row31_12 <= booth_b24_m7; + always @(posedge clk) + pp_row31_13 <= booth_b26_m5; + always @(posedge clk) + pp_row31_14 <= booth_b28_m3; + always @(posedge clk) + pp_row31_15 <= booth_b30_m1; + always @(posedge clk) + pp_row32_0 <= booth_b0_m32; + always @(posedge clk) + pp_row32_1 <= booth_b2_m30; + always @(posedge clk) + pp_row32_2 <= booth_b4_m28; + always @(posedge clk) + pp_row32_3 <= booth_b6_m26; + always @(posedge clk) + pp_row32_4 <= booth_b8_m24; + always @(posedge clk) + pp_row32_5 <= booth_b10_m22; + always @(posedge clk) + pp_row32_6 <= booth_b12_m20; + always @(posedge clk) + pp_row32_7 <= booth_b14_m18; + always @(posedge clk) + pp_row32_8 <= booth_b16_m16; + always @(posedge clk) + pp_row32_9 <= booth_b18_m14; + always @(posedge clk) + pp_row32_10 <= booth_b20_m12; + always @(posedge clk) + pp_row32_11 <= booth_b22_m10; + always @(posedge clk) + pp_row32_12 <= booth_b24_m8; + always @(posedge clk) + pp_row32_13 <= booth_b26_m6; + always @(posedge clk) + pp_row32_14 <= booth_b28_m4; + always @(posedge clk) + pp_row32_15 <= booth_b30_m2; + always @(posedge clk) + pp_row32_16 <= booth_b32_m0; + always @(posedge clk) + pp_row33_0 <= a_registered[1]; + always @(posedge clk) + pp_row33_1 <= booth_b2_m31; + always @(posedge clk) + pp_row33_2 <= booth_b4_m29; + always @(posedge clk) + pp_row33_3 <= booth_b6_m27; + always @(posedge clk) + pp_row33_4 <= booth_b8_m25; + always @(posedge clk) + pp_row33_5 <= booth_b10_m23; + always @(posedge clk) + pp_row33_6 <= booth_b12_m21; + always @(posedge clk) + pp_row33_7 <= booth_b14_m19; + always @(posedge clk) + pp_row33_8 <= booth_b16_m17; + always @(posedge clk) + pp_row33_9 <= booth_b18_m15; + always @(posedge clk) + pp_row33_10 <= booth_b20_m13; + always @(posedge clk) + pp_row33_11 <= booth_b22_m11; + always @(posedge clk) + pp_row33_12 <= booth_b24_m9; + always @(posedge clk) + pp_row33_13 <= booth_b26_m7; + always @(posedge clk) + pp_row33_14 <= booth_b28_m5; + always @(posedge clk) + pp_row33_15 <= booth_b30_m3; + always @(posedge clk) + pp_row33_16 <= booth_b32_m1; + always @(posedge clk) + pp_row34_0 <= a_registered[1]; + always @(posedge clk) + pp_row34_1 <= booth_b2_m32; + always @(posedge clk) + pp_row34_2 <= booth_b4_m30; + always @(posedge clk) + pp_row34_3 <= booth_b6_m28; + always @(posedge clk) + pp_row34_4 <= booth_b8_m26; + always @(posedge clk) + pp_row34_5 <= booth_b10_m24; + always @(posedge clk) + pp_row34_6 <= booth_b12_m22; + always @(posedge clk) + pp_row34_7 <= booth_b14_m20; + always @(posedge clk) + pp_row34_8 <= booth_b16_m18; + always @(posedge clk) + pp_row34_9 <= booth_b18_m16; + always @(posedge clk) + pp_row34_10 <= booth_b20_m14; + always @(posedge clk) + pp_row34_11 <= booth_b22_m12; + always @(posedge clk) + pp_row34_12 <= booth_b24_m10; + always @(posedge clk) + pp_row34_13 <= booth_b26_m8; + always @(posedge clk) + pp_row34_14 <= booth_b28_m6; + always @(posedge clk) + pp_row34_15 <= booth_b30_m4; + always @(posedge clk) + pp_row34_16 <= booth_b32_m2; + always @(posedge clk) + pp_row35_0 <= notsign; + always @(posedge clk) + pp_row35_1 <= \notsign$686 ; + always @(posedge clk) + pp_row35_2 <= booth_b4_m31; + always @(posedge clk) + pp_row35_3 <= booth_b6_m29; + always @(posedge clk) + pp_row35_4 <= booth_b8_m27; + always @(posedge clk) + pp_row35_5 <= booth_b10_m25; + always @(posedge clk) + pp_row35_6 <= booth_b12_m23; + always @(posedge clk) + pp_row35_7 <= booth_b14_m21; + always @(posedge clk) + pp_row35_8 <= booth_b16_m19; + always @(posedge clk) + pp_row35_9 <= booth_b18_m17; + always @(posedge clk) + pp_row35_10 <= booth_b20_m15; + always @(posedge clk) + pp_row35_11 <= booth_b22_m13; + always @(posedge clk) + pp_row35_12 <= booth_b24_m11; + always @(posedge clk) + pp_row35_13 <= booth_b26_m9; + always @(posedge clk) + pp_row35_14 <= booth_b28_m7; + always @(posedge clk) + pp_row35_15 <= booth_b30_m5; + always @(posedge clk) + pp_row35_16 <= booth_b32_m3; + always @(posedge clk) + pp_row36_1 <= booth_b4_m32; + always @(posedge clk) + pp_row36_2 <= booth_b6_m30; + always @(posedge clk) + pp_row36_3 <= booth_b8_m28; + always @(posedge clk) + pp_row36_4 <= booth_b10_m26; + always @(posedge clk) + pp_row36_5 <= booth_b12_m24; + always @(posedge clk) + pp_row36_6 <= booth_b14_m22; + always @(posedge clk) + pp_row36_7 <= booth_b16_m20; + always @(posedge clk) + pp_row36_8 <= booth_b18_m18; + always @(posedge clk) + pp_row36_9 <= booth_b20_m16; + always @(posedge clk) + pp_row36_10 <= booth_b22_m14; + always @(posedge clk) + pp_row36_11 <= booth_b24_m12; + always @(posedge clk) + pp_row36_12 <= booth_b26_m10; + always @(posedge clk) + pp_row36_13 <= booth_b28_m8; + always @(posedge clk) + pp_row36_14 <= booth_b30_m6; + always @(posedge clk) + pp_row36_15 <= booth_b32_m4; + always @(posedge clk) + pp_row37_0 <= \notsign$748 ; + always @(posedge clk) + pp_row37_1 <= booth_b6_m31; + always @(posedge clk) + pp_row37_2 <= booth_b8_m29; + always @(posedge clk) + pp_row37_3 <= booth_b10_m27; + always @(posedge clk) + pp_row37_4 <= booth_b12_m25; + always @(posedge clk) + pp_row37_5 <= booth_b14_m23; + always @(posedge clk) + pp_row37_6 <= booth_b16_m21; + always @(posedge clk) + pp_row37_7 <= booth_b18_m19; + always @(posedge clk) + pp_row37_8 <= booth_b20_m17; + always @(posedge clk) + pp_row37_9 <= booth_b22_m15; + always @(posedge clk) + pp_row37_10 <= booth_b24_m13; + always @(posedge clk) + pp_row37_11 <= booth_b26_m11; + always @(posedge clk) + pp_row37_12 <= booth_b28_m9; + always @(posedge clk) + pp_row37_13 <= booth_b30_m7; + always @(posedge clk) + pp_row37_14 <= booth_b32_m5; + always @(posedge clk) + pp_row38_1 <= booth_b6_m32; + always @(posedge clk) + pp_row38_2 <= booth_b8_m30; + always @(posedge clk) + pp_row38_3 <= booth_b10_m28; + always @(posedge clk) + pp_row38_4 <= booth_b12_m26; + always @(posedge clk) + pp_row38_5 <= booth_b14_m24; + always @(posedge clk) + pp_row38_6 <= booth_b16_m22; + always @(posedge clk) + pp_row38_7 <= booth_b18_m20; + always @(posedge clk) + pp_row38_8 <= booth_b20_m18; + always @(posedge clk) + pp_row38_9 <= booth_b22_m16; + always @(posedge clk) + pp_row38_10 <= booth_b24_m14; + always @(posedge clk) + pp_row38_11 <= booth_b26_m12; + always @(posedge clk) + pp_row38_12 <= booth_b28_m10; + always @(posedge clk) + pp_row38_13 <= booth_b30_m8; + always @(posedge clk) + pp_row38_14 <= booth_b32_m6; + always @(posedge clk) + pp_row39_0 <= \notsign$806 ; + always @(posedge clk) + pp_row39_1 <= booth_b8_m31; + always @(posedge clk) + pp_row39_2 <= booth_b10_m29; + always @(posedge clk) + pp_row39_3 <= booth_b12_m27; + always @(posedge clk) + pp_row39_4 <= booth_b14_m25; + always @(posedge clk) + pp_row39_5 <= booth_b16_m23; + always @(posedge clk) + pp_row39_6 <= booth_b18_m21; + always @(posedge clk) + pp_row39_7 <= booth_b20_m19; + always @(posedge clk) + pp_row39_8 <= booth_b22_m17; + always @(posedge clk) + pp_row39_9 <= booth_b24_m15; + always @(posedge clk) + pp_row39_10 <= booth_b26_m13; + always @(posedge clk) + pp_row39_11 <= booth_b28_m11; + always @(posedge clk) + pp_row39_12 <= booth_b30_m9; + always @(posedge clk) + pp_row39_13 <= booth_b32_m7; + always @(posedge clk) + pp_row40_1 <= booth_b8_m32; + always @(posedge clk) + pp_row40_2 <= booth_b10_m30; + always @(posedge clk) + pp_row40_3 <= booth_b12_m28; + always @(posedge clk) + pp_row40_4 <= booth_b14_m26; + always @(posedge clk) + pp_row40_5 <= booth_b16_m24; + always @(posedge clk) + pp_row40_6 <= booth_b18_m22; + always @(posedge clk) + pp_row40_7 <= booth_b20_m20; + always @(posedge clk) + pp_row40_8 <= booth_b22_m18; + always @(posedge clk) + pp_row40_9 <= booth_b24_m16; + always @(posedge clk) + pp_row40_10 <= booth_b26_m14; + always @(posedge clk) + pp_row40_11 <= booth_b28_m12; + always @(posedge clk) + pp_row40_12 <= booth_b30_m10; + always @(posedge clk) + pp_row40_13 <= booth_b32_m8; + always @(posedge clk) + pp_row41_0 <= \notsign$860 ; + always @(posedge clk) + pp_row41_1 <= booth_b10_m31; + always @(posedge clk) + pp_row41_2 <= booth_b12_m29; + always @(posedge clk) + pp_row41_3 <= booth_b14_m27; + always @(posedge clk) + pp_row41_4 <= booth_b16_m25; + always @(posedge clk) + pp_row41_5 <= booth_b18_m23; + always @(posedge clk) + pp_row41_6 <= booth_b20_m21; + always @(posedge clk) + pp_row41_7 <= booth_b22_m19; + always @(posedge clk) + pp_row41_8 <= booth_b24_m17; + always @(posedge clk) + pp_row41_9 <= booth_b26_m15; + always @(posedge clk) + pp_row41_10 <= booth_b28_m13; + always @(posedge clk) + pp_row41_11 <= booth_b30_m11; + always @(posedge clk) + pp_row41_12 <= booth_b32_m9; + always @(posedge clk) + pp_row42_1 <= booth_b10_m32; + always @(posedge clk) + pp_row42_2 <= booth_b12_m30; + always @(posedge clk) + pp_row42_3 <= booth_b14_m28; + always @(posedge clk) + pp_row42_4 <= booth_b16_m26; + always @(posedge clk) + pp_row42_5 <= booth_b18_m24; + always @(posedge clk) + pp_row42_6 <= booth_b20_m22; + always @(posedge clk) + pp_row42_7 <= booth_b22_m20; + always @(posedge clk) + pp_row42_8 <= booth_b24_m18; + always @(posedge clk) + pp_row42_9 <= booth_b26_m16; + always @(posedge clk) + pp_row42_10 <= booth_b28_m14; + always @(posedge clk) + pp_row42_11 <= booth_b30_m12; + always @(posedge clk) + pp_row42_12 <= booth_b32_m10; + always @(posedge clk) + pp_row43_0 <= \notsign$910 ; + always @(posedge clk) + pp_row43_1 <= booth_b12_m31; + always @(posedge clk) + pp_row43_2 <= booth_b14_m29; + always @(posedge clk) + pp_row43_3 <= booth_b16_m27; + always @(posedge clk) + pp_row43_4 <= booth_b18_m25; + always @(posedge clk) + pp_row43_5 <= booth_b20_m23; + always @(posedge clk) + pp_row43_6 <= booth_b22_m21; + always @(posedge clk) + pp_row43_7 <= booth_b24_m19; + always @(posedge clk) + pp_row43_8 <= booth_b26_m17; + always @(posedge clk) + pp_row43_9 <= booth_b28_m15; + always @(posedge clk) + pp_row43_10 <= booth_b30_m13; + always @(posedge clk) + pp_row43_11 <= booth_b32_m11; + always @(posedge clk) + pp_row44_1 <= booth_b12_m32; + always @(posedge clk) + pp_row44_2 <= booth_b14_m30; + always @(posedge clk) + pp_row44_3 <= booth_b16_m28; + always @(posedge clk) + pp_row44_4 <= booth_b18_m26; + always @(posedge clk) + pp_row44_5 <= booth_b20_m24; + always @(posedge clk) + pp_row44_6 <= booth_b22_m22; + always @(posedge clk) + pp_row44_7 <= booth_b24_m20; + always @(posedge clk) + pp_row44_8 <= booth_b26_m18; + always @(posedge clk) + pp_row44_9 <= booth_b28_m16; + always @(posedge clk) + pp_row44_10 <= booth_b30_m14; + always @(posedge clk) + pp_row44_11 <= booth_b32_m12; + always @(posedge clk) + pp_row45_0 <= \notsign$956 ; + always @(posedge clk) + pp_row45_1 <= booth_b14_m31; + always @(posedge clk) + pp_row45_2 <= booth_b16_m29; + always @(posedge clk) + pp_row45_3 <= booth_b18_m27; + always @(posedge clk) + pp_row45_4 <= booth_b20_m25; + always @(posedge clk) + pp_row45_5 <= booth_b22_m23; + always @(posedge clk) + pp_row45_6 <= booth_b24_m21; + always @(posedge clk) + pp_row45_7 <= booth_b26_m19; + always @(posedge clk) + pp_row45_8 <= booth_b28_m17; + always @(posedge clk) + pp_row45_9 <= booth_b30_m15; + always @(posedge clk) + pp_row45_10 <= booth_b32_m13; + always @(posedge clk) + pp_row46_1 <= booth_b14_m32; + always @(posedge clk) + pp_row46_2 <= booth_b16_m30; + always @(posedge clk) + pp_row46_3 <= booth_b18_m28; + always @(posedge clk) + pp_row46_4 <= booth_b20_m26; + always @(posedge clk) + pp_row46_5 <= booth_b22_m24; + always @(posedge clk) + pp_row46_6 <= booth_b24_m22; + always @(posedge clk) + pp_row46_7 <= booth_b26_m20; + always @(posedge clk) + pp_row46_8 <= booth_b28_m18; + always @(posedge clk) + pp_row46_9 <= booth_b30_m16; + always @(posedge clk) + pp_row46_10 <= booth_b32_m14; + always @(posedge clk) + pp_row47_0 <= \notsign$998 ; + always @(posedge clk) + pp_row47_1 <= booth_b16_m31; + always @(posedge clk) + pp_row47_2 <= booth_b18_m29; + always @(posedge clk) + pp_row47_3 <= booth_b20_m27; + always @(posedge clk) + pp_row47_4 <= booth_b22_m25; + always @(posedge clk) + pp_row47_5 <= booth_b24_m23; + always @(posedge clk) + pp_row47_6 <= booth_b26_m21; + always @(posedge clk) + pp_row47_7 <= booth_b28_m19; + always @(posedge clk) + pp_row47_8 <= booth_b30_m17; + always @(posedge clk) + pp_row47_9 <= booth_b32_m15; + always @(posedge clk) + pp_row48_1 <= booth_b16_m32; + always @(posedge clk) + pp_row48_2 <= booth_b18_m30; + always @(posedge clk) + pp_row48_3 <= booth_b20_m28; + always @(posedge clk) + pp_row48_4 <= booth_b22_m26; + always @(posedge clk) + pp_row48_5 <= booth_b24_m24; + always @(posedge clk) + pp_row48_6 <= booth_b26_m22; + always @(posedge clk) + pp_row48_7 <= booth_b28_m20; + always @(posedge clk) + pp_row48_8 <= booth_b30_m18; + always @(posedge clk) + pp_row48_9 <= booth_b32_m16; + always @(posedge clk) + pp_row49_0 <= \notsign$1036 ; + always @(posedge clk) + pp_row49_1 <= booth_b18_m31; + always @(posedge clk) + pp_row49_2 <= booth_b20_m29; + always @(posedge clk) + pp_row49_3 <= booth_b22_m27; + always @(posedge clk) + pp_row49_4 <= booth_b24_m25; + always @(posedge clk) + pp_row49_5 <= booth_b26_m23; + always @(posedge clk) + pp_row49_6 <= booth_b28_m21; + always @(posedge clk) + pp_row49_7 <= booth_b30_m19; + always @(posedge clk) + pp_row49_8 <= booth_b32_m17; + always @(posedge clk) + pp_row50_1 <= booth_b18_m32; + always @(posedge clk) + pp_row50_2 <= booth_b20_m30; + always @(posedge clk) + pp_row50_3 <= booth_b22_m28; + always @(posedge clk) + pp_row50_4 <= booth_b24_m26; + always @(posedge clk) + pp_row50_5 <= booth_b26_m24; + always @(posedge clk) + pp_row50_6 <= booth_b28_m22; + always @(posedge clk) + pp_row50_7 <= booth_b30_m20; + always @(posedge clk) + pp_row50_8 <= booth_b32_m18; + always @(posedge clk) + pp_row51_0 <= \notsign$1070 ; + always @(posedge clk) + pp_row51_1 <= booth_b20_m31; + always @(posedge clk) + pp_row51_2 <= booth_b22_m29; + always @(posedge clk) + pp_row51_3 <= booth_b24_m27; + always @(posedge clk) + pp_row51_4 <= booth_b26_m25; + always @(posedge clk) + pp_row51_5 <= booth_b28_m23; + always @(posedge clk) + pp_row51_6 <= booth_b30_m21; + always @(posedge clk) + pp_row51_7 <= booth_b32_m19; + always @(posedge clk) + pp_row52_1 <= booth_b20_m32; + always @(posedge clk) + pp_row52_2 <= booth_b22_m30; + always @(posedge clk) + pp_row52_3 <= booth_b24_m28; + always @(posedge clk) + pp_row52_4 <= booth_b26_m26; + always @(posedge clk) + pp_row52_5 <= booth_b28_m24; + always @(posedge clk) + pp_row52_6 <= booth_b30_m22; + always @(posedge clk) + pp_row52_7 <= booth_b32_m20; + always @(posedge clk) + pp_row53_0 <= \notsign$1100 ; + always @(posedge clk) + pp_row53_1 <= booth_b22_m31; + always @(posedge clk) + pp_row53_2 <= booth_b24_m29; + always @(posedge clk) + pp_row53_3 <= booth_b26_m27; + always @(posedge clk) + pp_row53_4 <= booth_b28_m25; + always @(posedge clk) + pp_row53_5 <= booth_b30_m23; + always @(posedge clk) + pp_row53_6 <= booth_b32_m21; + always @(posedge clk) + pp_row54_1 <= booth_b22_m32; + always @(posedge clk) + pp_row54_2 <= booth_b24_m30; + always @(posedge clk) + pp_row54_3 <= booth_b26_m28; + always @(posedge clk) + pp_row54_4 <= booth_b28_m26; + always @(posedge clk) + pp_row54_5 <= booth_b30_m24; + always @(posedge clk) + pp_row54_6 <= booth_b32_m22; + always @(posedge clk) + pp_row55_0 <= \notsign$1126 ; + always @(posedge clk) + pp_row55_1 <= booth_b24_m31; + always @(posedge clk) + pp_row55_2 <= booth_b26_m29; + always @(posedge clk) + pp_row55_3 <= booth_b28_m27; + always @(posedge clk) + pp_row55_4 <= booth_b30_m25; + always @(posedge clk) + pp_row55_5 <= booth_b32_m23; + always @(posedge clk) + pp_row56_1 <= booth_b24_m32; + always @(posedge clk) + pp_row56_2 <= booth_b26_m30; + always @(posedge clk) + pp_row56_3 <= booth_b28_m28; + always @(posedge clk) + pp_row56_4 <= booth_b30_m26; + always @(posedge clk) + pp_row56_5 <= booth_b32_m24; + always @(posedge clk) + pp_row57_0 <= \notsign$1148 ; + always @(posedge clk) + pp_row57_1 <= booth_b26_m31; + always @(posedge clk) + pp_row57_2 <= booth_b28_m29; + always @(posedge clk) + pp_row57_3 <= booth_b30_m27; + always @(posedge clk) + pp_row57_4 <= booth_b32_m25; + always @(posedge clk) + pp_row58_1 <= booth_b26_m32; + always @(posedge clk) + pp_row58_2 <= booth_b28_m30; + always @(posedge clk) + pp_row58_3 <= booth_b30_m28; + always @(posedge clk) + pp_row58_4 <= booth_b32_m26; + always @(posedge clk) + pp_row59_0 <= \notsign$1166 ; + always @(posedge clk) + pp_row59_1 <= booth_b28_m31; + always @(posedge clk) + pp_row59_2 <= booth_b30_m29; + always @(posedge clk) + pp_row59_3 <= booth_b32_m27; + always @(posedge clk) + pp_row60_1 <= booth_b28_m32; + always @(posedge clk) + pp_row60_2 <= booth_b30_m30; + always @(posedge clk) + pp_row60_3 <= booth_b32_m28; + always @(posedge clk) + pp_row61_0 <= \notsign$1180 ; + always @(posedge clk) + pp_row61_1 <= booth_b30_m31; + always @(posedge clk) + pp_row61_2 <= booth_b32_m29; + always @(posedge clk) + pp_row62_1 <= booth_b30_m32; + always @(posedge clk) + pp_row62_2 <= booth_b32_m30; + always @(posedge clk) + pp_row63_0 <= \notsign$1190 ; + always @(posedge clk) + pp_row63_1 <= booth_b32_m31; + always @(posedge clk) + pp_row64_1 <= booth_b32_m32; + always @(posedge clk) + final_a_registered <= { \c$1256 , \c$1255 , \c$1254 , \c$1253 , \c$1252 , \c$1251 , \c$1250 , \c$1249 , \c$1248 , \c$1247 , \c$1246 , \c$1245 , \c$1244 , \c$1243 , \c$1242 , \c$1241 , \c$1240 , \c$1239 , \c$1238 , \c$1237 , \c$1236 , \c$1235 , \c$1234 , \c$1233 , \c$1232 , \c$1231 , \c$1230 , \c$1229 , \c$1228 , \c$1227 , \c$1226 , \c$1225 , \c$1224 , \c$1223 , \c$1222 , \c$1221 , \c$1220 , \c$1219 , \c$1218 , \c$1217 , \c$1216 , \c$1215 , \c$1214 , \c$1213 , \c$1212 , \c$1211 , \c$1210 , \c$1209 , \c$1208 , \c$1207 , \c$1206 , \c$1205 , \c$1204 , \c$1203 , \c$1202 , \c$1201 , \c$1200 , \c$1199 , \c$1198 , \c$1197 , c, pp_row2_2, pp_row1_0, pp_row0_0 }; + always @(posedge clk) + final_b_registered <= { \s$1320 , \s$1319 , \s$1318 , \s$1317 , \s$1316 , \s$1315 , \s$1314 , \s$1313 , \s$1312 , \s$1311 , \s$1310 , \s$1309 , \s$1308 , \s$1307 , \s$1306 , \s$1305 , \s$1304 , \s$1303 , \s$1302 , \s$1301 , \s$1300 , \s$1299 , \s$1298 , \s$1297 , \s$1296 , \s$1295 , \s$1294 , \s$1293 , \s$1292 , \s$1291 , \s$1290 , \s$1289 , \s$1288 , \s$1287 , \s$1286 , \s$1285 , \s$1284 , \s$1283 , \s$1282 , \s$1281 , \s$1280 , \s$1279 , \s$1278 , \s$1277 , \s$1276 , \s$1275 , \s$1274 , \s$1273 , \s$1272 , \s$1271 , \s$1270 , \s$1269 , \s$1268 , \s$1267 , \s$1266 , \s$1265 , \s$1264 , \s$1263 , \s$1262 , \s$1261 , \s$1260 , s, 1'h0, pp_row0_1 }; + always @(posedge clk) + o <= { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + XOR2x1_ASAP7_75t_R \U$1000 ( + .A(\t$2197 ), + .B(a_registered[13]), + .Y(booth_b12_m18) + ); + AO22x1_ASAP7_75t_R \U$1001 ( + .A1(b_registered[18]), + .A2(\sel_0$1550 ), + .B1(b_registered[19]), + .B2(\sel_1$1551 ), + .Y(\t$2198 ) + ); + XOR2x1_ASAP7_75t_R \U$1002 ( + .A(\t$2198 ), + .B(a_registered[13]), + .Y(booth_b12_m19) + ); + AO22x1_ASAP7_75t_R \U$1003 ( + .A1(b_registered[19]), + .A2(\sel_0$1550 ), + .B1(b_registered[20]), + .B2(\sel_1$1551 ), + .Y(\t$2199 ) + ); + XOR2x1_ASAP7_75t_R \U$1004 ( + .A(\t$2199 ), + .B(a_registered[13]), + .Y(booth_b12_m20) + ); + AO22x1_ASAP7_75t_R \U$1005 ( + .A1(b_registered[20]), + .A2(\sel_0$1550 ), + .B1(b_registered[21]), + .B2(\sel_1$1551 ), + .Y(\t$2200 ) + ); + XOR2x1_ASAP7_75t_R \U$1006 ( + .A(\t$2200 ), + .B(a_registered[13]), + .Y(booth_b12_m21) + ); + AO22x1_ASAP7_75t_R \U$1007 ( + .A1(b_registered[21]), + .A2(\sel_0$1550 ), + .B1(b_registered[22]), + .B2(\sel_1$1551 ), + .Y(\t$2201 ) + ); + XOR2x1_ASAP7_75t_R \U$1008 ( + .A(\t$2201 ), + .B(a_registered[13]), + .Y(booth_b12_m22) + ); + AO22x1_ASAP7_75t_R \U$1009 ( + .A1(b_registered[22]), + .A2(\sel_0$1550 ), + .B1(b_registered[23]), + .B2(\sel_1$1551 ), + .Y(\t$2202 ) + ); + XOR2x1_ASAP7_75t_R \U$1010 ( + .A(\t$2202 ), + .B(a_registered[13]), + .Y(booth_b12_m23) + ); + AO22x1_ASAP7_75t_R \U$1011 ( + .A1(b_registered[23]), + .A2(\sel_0$1550 ), + .B1(b_registered[24]), + .B2(\sel_1$1551 ), + .Y(\t$2203 ) + ); + XOR2x1_ASAP7_75t_R \U$1012 ( + .A(\t$2203 ), + .B(a_registered[13]), + .Y(booth_b12_m24) + ); + AO22x1_ASAP7_75t_R \U$1013 ( + .A1(b_registered[24]), + .A2(\sel_0$1550 ), + .B1(b_registered[25]), + .B2(\sel_1$1551 ), + .Y(\t$2204 ) + ); + XOR2x1_ASAP7_75t_R \U$1014 ( + .A(\t$2204 ), + .B(a_registered[13]), + .Y(booth_b12_m25) + ); + AO22x1_ASAP7_75t_R \U$1015 ( + .A1(b_registered[25]), + .A2(\sel_0$1550 ), + .B1(b_registered[26]), + .B2(\sel_1$1551 ), + .Y(\t$2205 ) + ); + XOR2x1_ASAP7_75t_R \U$1016 ( + .A(\t$2205 ), + .B(a_registered[13]), + .Y(booth_b12_m26) + ); + AO22x1_ASAP7_75t_R \U$1017 ( + .A1(b_registered[26]), + .A2(\sel_0$1550 ), + .B1(b_registered[27]), + .B2(\sel_1$1551 ), + .Y(\t$2206 ) + ); + XOR2x1_ASAP7_75t_R \U$1018 ( + .A(\t$2206 ), + .B(a_registered[13]), + .Y(booth_b12_m27) + ); + AO22x1_ASAP7_75t_R \U$1019 ( + .A1(b_registered[27]), + .A2(\sel_0$1550 ), + .B1(b_registered[28]), + .B2(\sel_1$1551 ), + .Y(\t$2207 ) + ); + XOR2x1_ASAP7_75t_R \U$1020 ( + .A(\t$2207 ), + .B(a_registered[13]), + .Y(booth_b12_m28) + ); + AO22x1_ASAP7_75t_R \U$1021 ( + .A1(b_registered[28]), + .A2(\sel_0$1550 ), + .B1(b_registered[29]), + .B2(\sel_1$1551 ), + .Y(\t$2208 ) + ); + XOR2x1_ASAP7_75t_R \U$1022 ( + .A(\t$2208 ), + .B(a_registered[13]), + .Y(booth_b12_m29) + ); + AO22x1_ASAP7_75t_R \U$1023 ( + .A1(b_registered[29]), + .A2(\sel_0$1550 ), + .B1(b_registered[30]), + .B2(\sel_1$1551 ), + .Y(\t$2209 ) + ); + XOR2x1_ASAP7_75t_R \U$1024 ( + .A(\t$2209 ), + .B(a_registered[13]), + .Y(booth_b12_m30) + ); + AO22x1_ASAP7_75t_R \U$1025 ( + .A1(b_registered[30]), + .A2(\sel_0$1550 ), + .B1(b_registered[31]), + .B2(\sel_1$1551 ), + .Y(\t$2210 ) + ); + XOR2x1_ASAP7_75t_R \U$1026 ( + .A(\t$2210 ), + .B(a_registered[13]), + .Y(booth_b12_m31) + ); + AO22x1_ASAP7_75t_R \U$1027 ( + .A1(b_registered[31]), + .A2(\sel_0$1550 ), + .B1(1'h0), + .B2(\sel_1$1551 ), + .Y(\t$2211 ) + ); + XOR2x1_ASAP7_75t_R \U$1028 ( + .A(\t$2211 ), + .B(a_registered[13]), + .Y(booth_b12_m32) + ); + INVx1_ASAP7_75t_R \U$1029 ( + .A(a_registered[13]), + .Y(\notsign$956 ) + ); + INVx1_ASAP7_75t_R \U$1030 ( + .A(a_registered[13]), + .Y(\$22 ) + ); + INVx1_ASAP7_75t_R \U$1031 ( + .A(a_registered[14]), + .Y(\$23 ) + ); + INVx1_ASAP7_75t_R \U$1032 ( + .A(a_registered[15]), + .Y(\$24 ) + ); + AO33x2_ASAP7_75t_R \U$1033 ( + .A1(\$24 ), + .A2(a_registered[14]), + .A3(a_registered[13]), + .B1(a_registered[15]), + .B2(\$23 ), + .B3(\$22 ), + .Y(\sel_0$1587 ) + ); + XOR2x1_ASAP7_75t_R \U$1034 ( + .A(a_registered[14]), + .B(a_registered[13]), + .Y(\sel_1$1588 ) + ); + AO22x1_ASAP7_75t_R \U$1035 ( + .A1(1'h0), + .A2(\sel_0$1587 ), + .B1(b_registered[0]), + .B2(\sel_1$1588 ), + .Y(\t$2213 ) + ); + XOR2x1_ASAP7_75t_R \U$1036 ( + .A(\t$2213 ), + .B(a_registered[15]), + .Y(booth_b14_m0) + ); + AO22x1_ASAP7_75t_R \U$1037 ( + .A1(b_registered[0]), + .A2(\sel_0$1587 ), + .B1(b_registered[1]), + .B2(\sel_1$1588 ), + .Y(\t$2214 ) + ); + XOR2x1_ASAP7_75t_R \U$1038 ( + .A(\t$2214 ), + .B(a_registered[15]), + .Y(booth_b14_m1) + ); + AO22x1_ASAP7_75t_R \U$1039 ( + .A1(b_registered[1]), + .A2(\sel_0$1587 ), + .B1(b_registered[2]), + .B2(\sel_1$1588 ), + .Y(\t$2215 ) + ); + XOR2x1_ASAP7_75t_R \U$1040 ( + .A(\t$2215 ), + .B(a_registered[15]), + .Y(booth_b14_m2) + ); + AO22x1_ASAP7_75t_R \U$1041 ( + .A1(b_registered[2]), + .A2(\sel_0$1587 ), + .B1(b_registered[3]), + .B2(\sel_1$1588 ), + .Y(\t$2216 ) + ); + XOR2x1_ASAP7_75t_R \U$1042 ( + .A(\t$2216 ), + .B(a_registered[15]), + .Y(booth_b14_m3) + ); + AO22x1_ASAP7_75t_R \U$1043 ( + .A1(b_registered[3]), + .A2(\sel_0$1587 ), + .B1(b_registered[4]), + .B2(\sel_1$1588 ), + .Y(\t$2217 ) + ); + XOR2x1_ASAP7_75t_R \U$1044 ( + .A(\t$2217 ), + .B(a_registered[15]), + .Y(booth_b14_m4) + ); + AO22x1_ASAP7_75t_R \U$1045 ( + .A1(b_registered[4]), + .A2(\sel_0$1587 ), + .B1(b_registered[5]), + .B2(\sel_1$1588 ), + .Y(\t$2218 ) + ); + XOR2x1_ASAP7_75t_R \U$1046 ( + .A(\t$2218 ), + .B(a_registered[15]), + .Y(booth_b14_m5) + ); + AO22x1_ASAP7_75t_R \U$1047 ( + .A1(b_registered[5]), + .A2(\sel_0$1587 ), + .B1(b_registered[6]), + .B2(\sel_1$1588 ), + .Y(\t$2219 ) + ); + XOR2x1_ASAP7_75t_R \U$1048 ( + .A(\t$2219 ), + .B(a_registered[15]), + .Y(booth_b14_m6) + ); + AO22x1_ASAP7_75t_R \U$1049 ( + .A1(b_registered[6]), + .A2(\sel_0$1587 ), + .B1(b_registered[7]), + .B2(\sel_1$1588 ), + .Y(\t$2220 ) + ); + XOR2x1_ASAP7_75t_R \U$1050 ( + .A(\t$2220 ), + .B(a_registered[15]), + .Y(booth_b14_m7) + ); + AO22x1_ASAP7_75t_R \U$1051 ( + .A1(b_registered[7]), + .A2(\sel_0$1587 ), + .B1(b_registered[8]), + .B2(\sel_1$1588 ), + .Y(\t$2221 ) + ); + XOR2x1_ASAP7_75t_R \U$1052 ( + .A(\t$2221 ), + .B(a_registered[15]), + .Y(booth_b14_m8) + ); + AO22x1_ASAP7_75t_R \U$1053 ( + .A1(b_registered[8]), + .A2(\sel_0$1587 ), + .B1(b_registered[9]), + .B2(\sel_1$1588 ), + .Y(\t$2222 ) + ); + XOR2x1_ASAP7_75t_R \U$1054 ( + .A(\t$2222 ), + .B(a_registered[15]), + .Y(booth_b14_m9) + ); + AO22x1_ASAP7_75t_R \U$1055 ( + .A1(b_registered[9]), + .A2(\sel_0$1587 ), + .B1(b_registered[10]), + .B2(\sel_1$1588 ), + .Y(\t$2223 ) + ); + XOR2x1_ASAP7_75t_R \U$1056 ( + .A(\t$2223 ), + .B(a_registered[15]), + .Y(booth_b14_m10) + ); + AO22x1_ASAP7_75t_R \U$1057 ( + .A1(b_registered[10]), + .A2(\sel_0$1587 ), + .B1(b_registered[11]), + .B2(\sel_1$1588 ), + .Y(\t$2224 ) + ); + XOR2x1_ASAP7_75t_R \U$1058 ( + .A(\t$2224 ), + .B(a_registered[15]), + .Y(booth_b14_m11) + ); + AO22x1_ASAP7_75t_R \U$1059 ( + .A1(b_registered[11]), + .A2(\sel_0$1587 ), + .B1(b_registered[12]), + .B2(\sel_1$1588 ), + .Y(\t$2225 ) + ); + XOR2x1_ASAP7_75t_R \U$1060 ( + .A(\t$2225 ), + .B(a_registered[15]), + .Y(booth_b14_m12) + ); + AO22x1_ASAP7_75t_R \U$1061 ( + .A1(b_registered[12]), + .A2(\sel_0$1587 ), + .B1(b_registered[13]), + .B2(\sel_1$1588 ), + .Y(\t$2226 ) + ); + XOR2x1_ASAP7_75t_R \U$1062 ( + .A(\t$2226 ), + .B(a_registered[15]), + .Y(booth_b14_m13) + ); + AO22x1_ASAP7_75t_R \U$1063 ( + .A1(b_registered[13]), + .A2(\sel_0$1587 ), + .B1(b_registered[14]), + .B2(\sel_1$1588 ), + .Y(\t$2227 ) + ); + XOR2x1_ASAP7_75t_R \U$1064 ( + .A(\t$2227 ), + .B(a_registered[15]), + .Y(booth_b14_m14) + ); + AO22x1_ASAP7_75t_R \U$1065 ( + .A1(b_registered[14]), + .A2(\sel_0$1587 ), + .B1(b_registered[15]), + .B2(\sel_1$1588 ), + .Y(\t$2228 ) + ); + XOR2x1_ASAP7_75t_R \U$1066 ( + .A(\t$2228 ), + .B(a_registered[15]), + .Y(booth_b14_m15) + ); + AO22x1_ASAP7_75t_R \U$1067 ( + .A1(b_registered[15]), + .A2(\sel_0$1587 ), + .B1(b_registered[16]), + .B2(\sel_1$1588 ), + .Y(\t$2229 ) + ); + XOR2x1_ASAP7_75t_R \U$1068 ( + .A(\t$2229 ), + .B(a_registered[15]), + .Y(booth_b14_m16) + ); + AO22x1_ASAP7_75t_R \U$1069 ( + .A1(b_registered[16]), + .A2(\sel_0$1587 ), + .B1(b_registered[17]), + .B2(\sel_1$1588 ), + .Y(\t$2230 ) + ); + XOR2x1_ASAP7_75t_R \U$1070 ( + .A(\t$2230 ), + .B(a_registered[15]), + .Y(booth_b14_m17) + ); + AO22x1_ASAP7_75t_R \U$1071 ( + .A1(b_registered[17]), + .A2(\sel_0$1587 ), + .B1(b_registered[18]), + .B2(\sel_1$1588 ), + .Y(\t$2231 ) + ); + XOR2x1_ASAP7_75t_R \U$1072 ( + .A(\t$2231 ), + .B(a_registered[15]), + .Y(booth_b14_m18) + ); + AO22x1_ASAP7_75t_R \U$1073 ( + .A1(b_registered[18]), + .A2(\sel_0$1587 ), + .B1(b_registered[19]), + .B2(\sel_1$1588 ), + .Y(\t$2232 ) + ); + XOR2x1_ASAP7_75t_R \U$1074 ( + .A(\t$2232 ), + .B(a_registered[15]), + .Y(booth_b14_m19) + ); + AO22x1_ASAP7_75t_R \U$1075 ( + .A1(b_registered[19]), + .A2(\sel_0$1587 ), + .B1(b_registered[20]), + .B2(\sel_1$1588 ), + .Y(\t$2233 ) + ); + XOR2x1_ASAP7_75t_R \U$1076 ( + .A(\t$2233 ), + .B(a_registered[15]), + .Y(booth_b14_m20) + ); + AO22x1_ASAP7_75t_R \U$1077 ( + .A1(b_registered[20]), + .A2(\sel_0$1587 ), + .B1(b_registered[21]), + .B2(\sel_1$1588 ), + .Y(\t$2234 ) + ); + XOR2x1_ASAP7_75t_R \U$1078 ( + .A(\t$2234 ), + .B(a_registered[15]), + .Y(booth_b14_m21) + ); + AO22x1_ASAP7_75t_R \U$1079 ( + .A1(b_registered[21]), + .A2(\sel_0$1587 ), + .B1(b_registered[22]), + .B2(\sel_1$1588 ), + .Y(\t$2235 ) + ); + XOR2x1_ASAP7_75t_R \U$1080 ( + .A(\t$2235 ), + .B(a_registered[15]), + .Y(booth_b14_m22) + ); + AO22x1_ASAP7_75t_R \U$1081 ( + .A1(b_registered[22]), + .A2(\sel_0$1587 ), + .B1(b_registered[23]), + .B2(\sel_1$1588 ), + .Y(\t$2236 ) + ); + XOR2x1_ASAP7_75t_R \U$1082 ( + .A(\t$2236 ), + .B(a_registered[15]), + .Y(booth_b14_m23) + ); + AO22x1_ASAP7_75t_R \U$1083 ( + .A1(b_registered[23]), + .A2(\sel_0$1587 ), + .B1(b_registered[24]), + .B2(\sel_1$1588 ), + .Y(\t$2237 ) + ); + XOR2x1_ASAP7_75t_R \U$1084 ( + .A(\t$2237 ), + .B(a_registered[15]), + .Y(booth_b14_m24) + ); + AO22x1_ASAP7_75t_R \U$1085 ( + .A1(b_registered[24]), + .A2(\sel_0$1587 ), + .B1(b_registered[25]), + .B2(\sel_1$1588 ), + .Y(\t$2238 ) + ); + XOR2x1_ASAP7_75t_R \U$1086 ( + .A(\t$2238 ), + .B(a_registered[15]), + .Y(booth_b14_m25) + ); + AO22x1_ASAP7_75t_R \U$1087 ( + .A1(b_registered[25]), + .A2(\sel_0$1587 ), + .B1(b_registered[26]), + .B2(\sel_1$1588 ), + .Y(\t$2239 ) + ); + XOR2x1_ASAP7_75t_R \U$1088 ( + .A(\t$2239 ), + .B(a_registered[15]), + .Y(booth_b14_m26) + ); + AO22x1_ASAP7_75t_R \U$1089 ( + .A1(b_registered[26]), + .A2(\sel_0$1587 ), + .B1(b_registered[27]), + .B2(\sel_1$1588 ), + .Y(\t$2240 ) + ); + XOR2x1_ASAP7_75t_R \U$1090 ( + .A(\t$2240 ), + .B(a_registered[15]), + .Y(booth_b14_m27) + ); + AO22x1_ASAP7_75t_R \U$1091 ( + .A1(b_registered[27]), + .A2(\sel_0$1587 ), + .B1(b_registered[28]), + .B2(\sel_1$1588 ), + .Y(\t$2241 ) + ); + XOR2x1_ASAP7_75t_R \U$1092 ( + .A(\t$2241 ), + .B(a_registered[15]), + .Y(booth_b14_m28) + ); + AO22x1_ASAP7_75t_R \U$1093 ( + .A1(b_registered[28]), + .A2(\sel_0$1587 ), + .B1(b_registered[29]), + .B2(\sel_1$1588 ), + .Y(\t$2242 ) + ); + XOR2x1_ASAP7_75t_R \U$1094 ( + .A(\t$2242 ), + .B(a_registered[15]), + .Y(booth_b14_m29) + ); + AO22x1_ASAP7_75t_R \U$1095 ( + .A1(b_registered[29]), + .A2(\sel_0$1587 ), + .B1(b_registered[30]), + .B2(\sel_1$1588 ), + .Y(\t$2243 ) + ); + XOR2x1_ASAP7_75t_R \U$1096 ( + .A(\t$2243 ), + .B(a_registered[15]), + .Y(booth_b14_m30) + ); + AO22x1_ASAP7_75t_R \U$1097 ( + .A1(b_registered[30]), + .A2(\sel_0$1587 ), + .B1(b_registered[31]), + .B2(\sel_1$1588 ), + .Y(\t$2244 ) + ); + XOR2x1_ASAP7_75t_R \U$1098 ( + .A(\t$2244 ), + .B(a_registered[15]), + .Y(booth_b14_m31) + ); + AO22x1_ASAP7_75t_R \U$1099 ( + .A1(b_registered[31]), + .A2(\sel_0$1587 ), + .B1(1'h0), + .B2(\sel_1$1588 ), + .Y(\t$2245 ) + ); + XOR2x1_ASAP7_75t_R \U$1100 ( + .A(\t$2245 ), + .B(a_registered[15]), + .Y(booth_b14_m32) + ); + INVx1_ASAP7_75t_R \U$1101 ( + .A(a_registered[15]), + .Y(\notsign$998 ) + ); + INVx1_ASAP7_75t_R \U$1102 ( + .A(a_registered[15]), + .Y(\$25 ) + ); + INVx1_ASAP7_75t_R \U$1103 ( + .A(a_registered[16]), + .Y(\$26 ) + ); + INVx1_ASAP7_75t_R \U$1104 ( + .A(a_registered[17]), + .Y(\$27 ) + ); + AO33x2_ASAP7_75t_R \U$1105 ( + .A1(\$27 ), + .A2(a_registered[16]), + .A3(a_registered[15]), + .B1(a_registered[17]), + .B2(\$26 ), + .B3(\$25 ), + .Y(\sel_0$1624 ) + ); + XOR2x1_ASAP7_75t_R \U$1106 ( + .A(a_registered[16]), + .B(a_registered[15]), + .Y(\sel_1$1625 ) + ); + AO22x1_ASAP7_75t_R \U$1107 ( + .A1(1'h0), + .A2(\sel_0$1624 ), + .B1(b_registered[0]), + .B2(\sel_1$1625 ), + .Y(\t$2247 ) + ); + XOR2x1_ASAP7_75t_R \U$1108 ( + .A(\t$2247 ), + .B(a_registered[17]), + .Y(booth_b16_m0) + ); + AO22x1_ASAP7_75t_R \U$1109 ( + .A1(b_registered[0]), + .A2(\sel_0$1624 ), + .B1(b_registered[1]), + .B2(\sel_1$1625 ), + .Y(\t$2248 ) + ); + XOR2x1_ASAP7_75t_R \U$1110 ( + .A(\t$2248 ), + .B(a_registered[17]), + .Y(booth_b16_m1) + ); + AO22x1_ASAP7_75t_R \U$1111 ( + .A1(b_registered[1]), + .A2(\sel_0$1624 ), + .B1(b_registered[2]), + .B2(\sel_1$1625 ), + .Y(\t$2249 ) + ); + XOR2x1_ASAP7_75t_R \U$1112 ( + .A(\t$2249 ), + .B(a_registered[17]), + .Y(booth_b16_m2) + ); + AO22x1_ASAP7_75t_R \U$1113 ( + .A1(b_registered[2]), + .A2(\sel_0$1624 ), + .B1(b_registered[3]), + .B2(\sel_1$1625 ), + .Y(\t$2250 ) + ); + XOR2x1_ASAP7_75t_R \U$1114 ( + .A(\t$2250 ), + .B(a_registered[17]), + .Y(booth_b16_m3) + ); + AO22x1_ASAP7_75t_R \U$1115 ( + .A1(b_registered[3]), + .A2(\sel_0$1624 ), + .B1(b_registered[4]), + .B2(\sel_1$1625 ), + .Y(\t$2251 ) + ); + XOR2x1_ASAP7_75t_R \U$1116 ( + .A(\t$2251 ), + .B(a_registered[17]), + .Y(booth_b16_m4) + ); + AO22x1_ASAP7_75t_R \U$1117 ( + .A1(b_registered[4]), + .A2(\sel_0$1624 ), + .B1(b_registered[5]), + .B2(\sel_1$1625 ), + .Y(\t$2252 ) + ); + XOR2x1_ASAP7_75t_R \U$1118 ( + .A(\t$2252 ), + .B(a_registered[17]), + .Y(booth_b16_m5) + ); + AO22x1_ASAP7_75t_R \U$1119 ( + .A1(b_registered[5]), + .A2(\sel_0$1624 ), + .B1(b_registered[6]), + .B2(\sel_1$1625 ), + .Y(\t$2253 ) + ); + XOR2x1_ASAP7_75t_R \U$1120 ( + .A(\t$2253 ), + .B(a_registered[17]), + .Y(booth_b16_m6) + ); + AO22x1_ASAP7_75t_R \U$1121 ( + .A1(b_registered[6]), + .A2(\sel_0$1624 ), + .B1(b_registered[7]), + .B2(\sel_1$1625 ), + .Y(\t$2254 ) + ); + XOR2x1_ASAP7_75t_R \U$1122 ( + .A(\t$2254 ), + .B(a_registered[17]), + .Y(booth_b16_m7) + ); + AO22x1_ASAP7_75t_R \U$1123 ( + .A1(b_registered[7]), + .A2(\sel_0$1624 ), + .B1(b_registered[8]), + .B2(\sel_1$1625 ), + .Y(\t$2255 ) + ); + XOR2x1_ASAP7_75t_R \U$1124 ( + .A(\t$2255 ), + .B(a_registered[17]), + .Y(booth_b16_m8) + ); + AO22x1_ASAP7_75t_R \U$1125 ( + .A1(b_registered[8]), + .A2(\sel_0$1624 ), + .B1(b_registered[9]), + .B2(\sel_1$1625 ), + .Y(\t$2256 ) + ); + XOR2x1_ASAP7_75t_R \U$1126 ( + .A(\t$2256 ), + .B(a_registered[17]), + .Y(booth_b16_m9) + ); + AO22x1_ASAP7_75t_R \U$1127 ( + .A1(b_registered[9]), + .A2(\sel_0$1624 ), + .B1(b_registered[10]), + .B2(\sel_1$1625 ), + .Y(\t$2257 ) + ); + XOR2x1_ASAP7_75t_R \U$1128 ( + .A(\t$2257 ), + .B(a_registered[17]), + .Y(booth_b16_m10) + ); + AO22x1_ASAP7_75t_R \U$1129 ( + .A1(b_registered[10]), + .A2(\sel_0$1624 ), + .B1(b_registered[11]), + .B2(\sel_1$1625 ), + .Y(\t$2258 ) + ); + XOR2x1_ASAP7_75t_R \U$1130 ( + .A(\t$2258 ), + .B(a_registered[17]), + .Y(booth_b16_m11) + ); + AO22x1_ASAP7_75t_R \U$1131 ( + .A1(b_registered[11]), + .A2(\sel_0$1624 ), + .B1(b_registered[12]), + .B2(\sel_1$1625 ), + .Y(\t$2259 ) + ); + XOR2x1_ASAP7_75t_R \U$1132 ( + .A(\t$2259 ), + .B(a_registered[17]), + .Y(booth_b16_m12) + ); + AO22x1_ASAP7_75t_R \U$1133 ( + .A1(b_registered[12]), + .A2(\sel_0$1624 ), + .B1(b_registered[13]), + .B2(\sel_1$1625 ), + .Y(\t$2260 ) + ); + XOR2x1_ASAP7_75t_R \U$1134 ( + .A(\t$2260 ), + .B(a_registered[17]), + .Y(booth_b16_m13) + ); + AO22x1_ASAP7_75t_R \U$1135 ( + .A1(b_registered[13]), + .A2(\sel_0$1624 ), + .B1(b_registered[14]), + .B2(\sel_1$1625 ), + .Y(\t$2261 ) + ); + XOR2x1_ASAP7_75t_R \U$1136 ( + .A(\t$2261 ), + .B(a_registered[17]), + .Y(booth_b16_m14) + ); + AO22x1_ASAP7_75t_R \U$1137 ( + .A1(b_registered[14]), + .A2(\sel_0$1624 ), + .B1(b_registered[15]), + .B2(\sel_1$1625 ), + .Y(\t$2262 ) + ); + XOR2x1_ASAP7_75t_R \U$1138 ( + .A(\t$2262 ), + .B(a_registered[17]), + .Y(booth_b16_m15) + ); + AO22x1_ASAP7_75t_R \U$1139 ( + .A1(b_registered[15]), + .A2(\sel_0$1624 ), + .B1(b_registered[16]), + .B2(\sel_1$1625 ), + .Y(\t$2263 ) + ); + XOR2x1_ASAP7_75t_R \U$1140 ( + .A(\t$2263 ), + .B(a_registered[17]), + .Y(booth_b16_m16) + ); + AO22x1_ASAP7_75t_R \U$1141 ( + .A1(b_registered[16]), + .A2(\sel_0$1624 ), + .B1(b_registered[17]), + .B2(\sel_1$1625 ), + .Y(\t$2264 ) + ); + XOR2x1_ASAP7_75t_R \U$1142 ( + .A(\t$2264 ), + .B(a_registered[17]), + .Y(booth_b16_m17) + ); + AO22x1_ASAP7_75t_R \U$1143 ( + .A1(b_registered[17]), + .A2(\sel_0$1624 ), + .B1(b_registered[18]), + .B2(\sel_1$1625 ), + .Y(\t$2265 ) + ); + XOR2x1_ASAP7_75t_R \U$1144 ( + .A(\t$2265 ), + .B(a_registered[17]), + .Y(booth_b16_m18) + ); + AO22x1_ASAP7_75t_R \U$1145 ( + .A1(b_registered[18]), + .A2(\sel_0$1624 ), + .B1(b_registered[19]), + .B2(\sel_1$1625 ), + .Y(\t$2266 ) + ); + XOR2x1_ASAP7_75t_R \U$1146 ( + .A(\t$2266 ), + .B(a_registered[17]), + .Y(booth_b16_m19) + ); + AO22x1_ASAP7_75t_R \U$1147 ( + .A1(b_registered[19]), + .A2(\sel_0$1624 ), + .B1(b_registered[20]), + .B2(\sel_1$1625 ), + .Y(\t$2267 ) + ); + XOR2x1_ASAP7_75t_R \U$1148 ( + .A(\t$2267 ), + .B(a_registered[17]), + .Y(booth_b16_m20) + ); + AO22x1_ASAP7_75t_R \U$1149 ( + .A1(b_registered[20]), + .A2(\sel_0$1624 ), + .B1(b_registered[21]), + .B2(\sel_1$1625 ), + .Y(\t$2268 ) + ); + XOR2x1_ASAP7_75t_R \U$1150 ( + .A(\t$2268 ), + .B(a_registered[17]), + .Y(booth_b16_m21) + ); + AO22x1_ASAP7_75t_R \U$1151 ( + .A1(b_registered[21]), + .A2(\sel_0$1624 ), + .B1(b_registered[22]), + .B2(\sel_1$1625 ), + .Y(\t$2269 ) + ); + XOR2x1_ASAP7_75t_R \U$1152 ( + .A(\t$2269 ), + .B(a_registered[17]), + .Y(booth_b16_m22) + ); + AO22x1_ASAP7_75t_R \U$1153 ( + .A1(b_registered[22]), + .A2(\sel_0$1624 ), + .B1(b_registered[23]), + .B2(\sel_1$1625 ), + .Y(\t$2270 ) + ); + XOR2x1_ASAP7_75t_R \U$1154 ( + .A(\t$2270 ), + .B(a_registered[17]), + .Y(booth_b16_m23) + ); + AO22x1_ASAP7_75t_R \U$1155 ( + .A1(b_registered[23]), + .A2(\sel_0$1624 ), + .B1(b_registered[24]), + .B2(\sel_1$1625 ), + .Y(\t$2271 ) + ); + XOR2x1_ASAP7_75t_R \U$1156 ( + .A(\t$2271 ), + .B(a_registered[17]), + .Y(booth_b16_m24) + ); + AO22x1_ASAP7_75t_R \U$1157 ( + .A1(b_registered[24]), + .A2(\sel_0$1624 ), + .B1(b_registered[25]), + .B2(\sel_1$1625 ), + .Y(\t$2272 ) + ); + XOR2x1_ASAP7_75t_R \U$1158 ( + .A(\t$2272 ), + .B(a_registered[17]), + .Y(booth_b16_m25) + ); + AO22x1_ASAP7_75t_R \U$1159 ( + .A1(b_registered[25]), + .A2(\sel_0$1624 ), + .B1(b_registered[26]), + .B2(\sel_1$1625 ), + .Y(\t$2273 ) + ); + XOR2x1_ASAP7_75t_R \U$1160 ( + .A(\t$2273 ), + .B(a_registered[17]), + .Y(booth_b16_m26) + ); + AO22x1_ASAP7_75t_R \U$1161 ( + .A1(b_registered[26]), + .A2(\sel_0$1624 ), + .B1(b_registered[27]), + .B2(\sel_1$1625 ), + .Y(\t$2274 ) + ); + XOR2x1_ASAP7_75t_R \U$1162 ( + .A(\t$2274 ), + .B(a_registered[17]), + .Y(booth_b16_m27) + ); + AO22x1_ASAP7_75t_R \U$1163 ( + .A1(b_registered[27]), + .A2(\sel_0$1624 ), + .B1(b_registered[28]), + .B2(\sel_1$1625 ), + .Y(\t$2275 ) + ); + XOR2x1_ASAP7_75t_R \U$1164 ( + .A(\t$2275 ), + .B(a_registered[17]), + .Y(booth_b16_m28) + ); + AO22x1_ASAP7_75t_R \U$1165 ( + .A1(b_registered[28]), + .A2(\sel_0$1624 ), + .B1(b_registered[29]), + .B2(\sel_1$1625 ), + .Y(\t$2276 ) + ); + XOR2x1_ASAP7_75t_R \U$1166 ( + .A(\t$2276 ), + .B(a_registered[17]), + .Y(booth_b16_m29) + ); + AO22x1_ASAP7_75t_R \U$1167 ( + .A1(b_registered[29]), + .A2(\sel_0$1624 ), + .B1(b_registered[30]), + .B2(\sel_1$1625 ), + .Y(\t$2277 ) + ); + XOR2x1_ASAP7_75t_R \U$1168 ( + .A(\t$2277 ), + .B(a_registered[17]), + .Y(booth_b16_m30) + ); + AO22x1_ASAP7_75t_R \U$1169 ( + .A1(b_registered[30]), + .A2(\sel_0$1624 ), + .B1(b_registered[31]), + .B2(\sel_1$1625 ), + .Y(\t$2278 ) + ); + XOR2x1_ASAP7_75t_R \U$1170 ( + .A(\t$2278 ), + .B(a_registered[17]), + .Y(booth_b16_m31) + ); + AO22x1_ASAP7_75t_R \U$1171 ( + .A1(b_registered[31]), + .A2(\sel_0$1624 ), + .B1(1'h0), + .B2(\sel_1$1625 ), + .Y(\t$2279 ) + ); + XOR2x1_ASAP7_75t_R \U$1172 ( + .A(\t$2279 ), + .B(a_registered[17]), + .Y(booth_b16_m32) + ); + INVx1_ASAP7_75t_R \U$1173 ( + .A(a_registered[17]), + .Y(\notsign$1036 ) + ); + INVx1_ASAP7_75t_R \U$1174 ( + .A(a_registered[17]), + .Y(\$28 ) + ); + INVx1_ASAP7_75t_R \U$1175 ( + .A(a_registered[18]), + .Y(\$29 ) + ); + INVx1_ASAP7_75t_R \U$1176 ( + .A(a_registered[19]), + .Y(\$30 ) + ); + AO33x2_ASAP7_75t_R \U$1177 ( + .A1(\$30 ), + .A2(a_registered[18]), + .A3(a_registered[17]), + .B1(a_registered[19]), + .B2(\$29 ), + .B3(\$28 ), + .Y(\sel_0$1661 ) + ); + XOR2x1_ASAP7_75t_R \U$1178 ( + .A(a_registered[18]), + .B(a_registered[17]), + .Y(\sel_1$1662 ) + ); + AO22x1_ASAP7_75t_R \U$1179 ( + .A1(1'h0), + .A2(\sel_0$1661 ), + .B1(b_registered[0]), + .B2(\sel_1$1662 ), + .Y(\t$2281 ) + ); + XOR2x1_ASAP7_75t_R \U$1180 ( + .A(\t$2281 ), + .B(a_registered[19]), + .Y(booth_b18_m0) + ); + AO22x1_ASAP7_75t_R \U$1181 ( + .A1(b_registered[0]), + .A2(\sel_0$1661 ), + .B1(b_registered[1]), + .B2(\sel_1$1662 ), + .Y(\t$2282 ) + ); + XOR2x1_ASAP7_75t_R \U$1182 ( + .A(\t$2282 ), + .B(a_registered[19]), + .Y(booth_b18_m1) + ); + AO22x1_ASAP7_75t_R \U$1183 ( + .A1(b_registered[1]), + .A2(\sel_0$1661 ), + .B1(b_registered[2]), + .B2(\sel_1$1662 ), + .Y(\t$2283 ) + ); + XOR2x1_ASAP7_75t_R \U$1184 ( + .A(\t$2283 ), + .B(a_registered[19]), + .Y(booth_b18_m2) + ); + AO22x1_ASAP7_75t_R \U$1185 ( + .A1(b_registered[2]), + .A2(\sel_0$1661 ), + .B1(b_registered[3]), + .B2(\sel_1$1662 ), + .Y(\t$2284 ) + ); + XOR2x1_ASAP7_75t_R \U$1186 ( + .A(\t$2284 ), + .B(a_registered[19]), + .Y(booth_b18_m3) + ); + AO22x1_ASAP7_75t_R \U$1187 ( + .A1(b_registered[3]), + .A2(\sel_0$1661 ), + .B1(b_registered[4]), + .B2(\sel_1$1662 ), + .Y(\t$2285 ) + ); + XOR2x1_ASAP7_75t_R \U$1188 ( + .A(\t$2285 ), + .B(a_registered[19]), + .Y(booth_b18_m4) + ); + AO22x1_ASAP7_75t_R \U$1189 ( + .A1(b_registered[4]), + .A2(\sel_0$1661 ), + .B1(b_registered[5]), + .B2(\sel_1$1662 ), + .Y(\t$2286 ) + ); + XOR2x1_ASAP7_75t_R \U$1190 ( + .A(\t$2286 ), + .B(a_registered[19]), + .Y(booth_b18_m5) + ); + AO22x1_ASAP7_75t_R \U$1191 ( + .A1(b_registered[5]), + .A2(\sel_0$1661 ), + .B1(b_registered[6]), + .B2(\sel_1$1662 ), + .Y(\t$2287 ) + ); + XOR2x1_ASAP7_75t_R \U$1192 ( + .A(\t$2287 ), + .B(a_registered[19]), + .Y(booth_b18_m6) + ); + AO22x1_ASAP7_75t_R \U$1193 ( + .A1(b_registered[6]), + .A2(\sel_0$1661 ), + .B1(b_registered[7]), + .B2(\sel_1$1662 ), + .Y(\t$2288 ) + ); + XOR2x1_ASAP7_75t_R \U$1194 ( + .A(\t$2288 ), + .B(a_registered[19]), + .Y(booth_b18_m7) + ); + AO22x1_ASAP7_75t_R \U$1195 ( + .A1(b_registered[7]), + .A2(\sel_0$1661 ), + .B1(b_registered[8]), + .B2(\sel_1$1662 ), + .Y(\t$2289 ) + ); + XOR2x1_ASAP7_75t_R \U$1196 ( + .A(\t$2289 ), + .B(a_registered[19]), + .Y(booth_b18_m8) + ); + AO22x1_ASAP7_75t_R \U$1197 ( + .A1(b_registered[8]), + .A2(\sel_0$1661 ), + .B1(b_registered[9]), + .B2(\sel_1$1662 ), + .Y(\t$2290 ) + ); + XOR2x1_ASAP7_75t_R \U$1198 ( + .A(\t$2290 ), + .B(a_registered[19]), + .Y(booth_b18_m9) + ); + AO22x1_ASAP7_75t_R \U$1199 ( + .A1(b_registered[9]), + .A2(\sel_0$1661 ), + .B1(b_registered[10]), + .B2(\sel_1$1662 ), + .Y(\t$2291 ) + ); + XOR2x1_ASAP7_75t_R \U$1200 ( + .A(\t$2291 ), + .B(a_registered[19]), + .Y(booth_b18_m10) + ); + AO22x1_ASAP7_75t_R \U$1201 ( + .A1(b_registered[10]), + .A2(\sel_0$1661 ), + .B1(b_registered[11]), + .B2(\sel_1$1662 ), + .Y(\t$2292 ) + ); + XOR2x1_ASAP7_75t_R \U$1202 ( + .A(\t$2292 ), + .B(a_registered[19]), + .Y(booth_b18_m11) + ); + AO22x1_ASAP7_75t_R \U$1203 ( + .A1(b_registered[11]), + .A2(\sel_0$1661 ), + .B1(b_registered[12]), + .B2(\sel_1$1662 ), + .Y(\t$2293 ) + ); + XOR2x1_ASAP7_75t_R \U$1204 ( + .A(\t$2293 ), + .B(a_registered[19]), + .Y(booth_b18_m12) + ); + AO22x1_ASAP7_75t_R \U$1205 ( + .A1(b_registered[12]), + .A2(\sel_0$1661 ), + .B1(b_registered[13]), + .B2(\sel_1$1662 ), + .Y(\t$2294 ) + ); + XOR2x1_ASAP7_75t_R \U$1206 ( + .A(\t$2294 ), + .B(a_registered[19]), + .Y(booth_b18_m13) + ); + AO22x1_ASAP7_75t_R \U$1207 ( + .A1(b_registered[13]), + .A2(\sel_0$1661 ), + .B1(b_registered[14]), + .B2(\sel_1$1662 ), + .Y(\t$2295 ) + ); + XOR2x1_ASAP7_75t_R \U$1208 ( + .A(\t$2295 ), + .B(a_registered[19]), + .Y(booth_b18_m14) + ); + AO22x1_ASAP7_75t_R \U$1209 ( + .A1(b_registered[14]), + .A2(\sel_0$1661 ), + .B1(b_registered[15]), + .B2(\sel_1$1662 ), + .Y(\t$2296 ) + ); + XOR2x1_ASAP7_75t_R \U$1210 ( + .A(\t$2296 ), + .B(a_registered[19]), + .Y(booth_b18_m15) + ); + AO22x1_ASAP7_75t_R \U$1211 ( + .A1(b_registered[15]), + .A2(\sel_0$1661 ), + .B1(b_registered[16]), + .B2(\sel_1$1662 ), + .Y(\t$2297 ) + ); + XOR2x1_ASAP7_75t_R \U$1212 ( + .A(\t$2297 ), + .B(a_registered[19]), + .Y(booth_b18_m16) + ); + AO22x1_ASAP7_75t_R \U$1213 ( + .A1(b_registered[16]), + .A2(\sel_0$1661 ), + .B1(b_registered[17]), + .B2(\sel_1$1662 ), + .Y(\t$2298 ) + ); + XOR2x1_ASAP7_75t_R \U$1214 ( + .A(\t$2298 ), + .B(a_registered[19]), + .Y(booth_b18_m17) + ); + AO22x1_ASAP7_75t_R \U$1215 ( + .A1(b_registered[17]), + .A2(\sel_0$1661 ), + .B1(b_registered[18]), + .B2(\sel_1$1662 ), + .Y(\t$2299 ) + ); + XOR2x1_ASAP7_75t_R \U$1216 ( + .A(\t$2299 ), + .B(a_registered[19]), + .Y(booth_b18_m18) + ); + AO22x1_ASAP7_75t_R \U$1217 ( + .A1(b_registered[18]), + .A2(\sel_0$1661 ), + .B1(b_registered[19]), + .B2(\sel_1$1662 ), + .Y(\t$2300 ) + ); + XOR2x1_ASAP7_75t_R \U$1218 ( + .A(\t$2300 ), + .B(a_registered[19]), + .Y(booth_b18_m19) + ); + AO22x1_ASAP7_75t_R \U$1219 ( + .A1(b_registered[19]), + .A2(\sel_0$1661 ), + .B1(b_registered[20]), + .B2(\sel_1$1662 ), + .Y(\t$2301 ) + ); + XOR2x1_ASAP7_75t_R \U$1220 ( + .A(\t$2301 ), + .B(a_registered[19]), + .Y(booth_b18_m20) + ); + AO22x1_ASAP7_75t_R \U$1221 ( + .A1(b_registered[20]), + .A2(\sel_0$1661 ), + .B1(b_registered[21]), + .B2(\sel_1$1662 ), + .Y(\t$2302 ) + ); + XOR2x1_ASAP7_75t_R \U$1222 ( + .A(\t$2302 ), + .B(a_registered[19]), + .Y(booth_b18_m21) + ); + AO22x1_ASAP7_75t_R \U$1223 ( + .A1(b_registered[21]), + .A2(\sel_0$1661 ), + .B1(b_registered[22]), + .B2(\sel_1$1662 ), + .Y(\t$2303 ) + ); + XOR2x1_ASAP7_75t_R \U$1224 ( + .A(\t$2303 ), + .B(a_registered[19]), + .Y(booth_b18_m22) + ); + AO22x1_ASAP7_75t_R \U$1225 ( + .A1(b_registered[22]), + .A2(\sel_0$1661 ), + .B1(b_registered[23]), + .B2(\sel_1$1662 ), + .Y(\t$2304 ) + ); + XOR2x1_ASAP7_75t_R \U$1226 ( + .A(\t$2304 ), + .B(a_registered[19]), + .Y(booth_b18_m23) + ); + AO22x1_ASAP7_75t_R \U$1227 ( + .A1(b_registered[23]), + .A2(\sel_0$1661 ), + .B1(b_registered[24]), + .B2(\sel_1$1662 ), + .Y(\t$2305 ) + ); + XOR2x1_ASAP7_75t_R \U$1228 ( + .A(\t$2305 ), + .B(a_registered[19]), + .Y(booth_b18_m24) + ); + AO22x1_ASAP7_75t_R \U$1229 ( + .A1(b_registered[24]), + .A2(\sel_0$1661 ), + .B1(b_registered[25]), + .B2(\sel_1$1662 ), + .Y(\t$2306 ) + ); + XOR2x1_ASAP7_75t_R \U$1230 ( + .A(\t$2306 ), + .B(a_registered[19]), + .Y(booth_b18_m25) + ); + AO22x1_ASAP7_75t_R \U$1231 ( + .A1(b_registered[25]), + .A2(\sel_0$1661 ), + .B1(b_registered[26]), + .B2(\sel_1$1662 ), + .Y(\t$2307 ) + ); + XOR2x1_ASAP7_75t_R \U$1232 ( + .A(\t$2307 ), + .B(a_registered[19]), + .Y(booth_b18_m26) + ); + AO22x1_ASAP7_75t_R \U$1233 ( + .A1(b_registered[26]), + .A2(\sel_0$1661 ), + .B1(b_registered[27]), + .B2(\sel_1$1662 ), + .Y(\t$2308 ) + ); + XOR2x1_ASAP7_75t_R \U$1234 ( + .A(\t$2308 ), + .B(a_registered[19]), + .Y(booth_b18_m27) + ); + AO22x1_ASAP7_75t_R \U$1235 ( + .A1(b_registered[27]), + .A2(\sel_0$1661 ), + .B1(b_registered[28]), + .B2(\sel_1$1662 ), + .Y(\t$2309 ) + ); + XOR2x1_ASAP7_75t_R \U$1236 ( + .A(\t$2309 ), + .B(a_registered[19]), + .Y(booth_b18_m28) + ); + AO22x1_ASAP7_75t_R \U$1237 ( + .A1(b_registered[28]), + .A2(\sel_0$1661 ), + .B1(b_registered[29]), + .B2(\sel_1$1662 ), + .Y(\t$2310 ) + ); + XOR2x1_ASAP7_75t_R \U$1238 ( + .A(\t$2310 ), + .B(a_registered[19]), + .Y(booth_b18_m29) + ); + AO22x1_ASAP7_75t_R \U$1239 ( + .A1(b_registered[29]), + .A2(\sel_0$1661 ), + .B1(b_registered[30]), + .B2(\sel_1$1662 ), + .Y(\t$2311 ) + ); + XOR2x1_ASAP7_75t_R \U$1240 ( + .A(\t$2311 ), + .B(a_registered[19]), + .Y(booth_b18_m30) + ); + AO22x1_ASAP7_75t_R \U$1241 ( + .A1(b_registered[30]), + .A2(\sel_0$1661 ), + .B1(b_registered[31]), + .B2(\sel_1$1662 ), + .Y(\t$2312 ) + ); + XOR2x1_ASAP7_75t_R \U$1242 ( + .A(\t$2312 ), + .B(a_registered[19]), + .Y(booth_b18_m31) + ); + AO22x1_ASAP7_75t_R \U$1243 ( + .A1(b_registered[31]), + .A2(\sel_0$1661 ), + .B1(1'h0), + .B2(\sel_1$1662 ), + .Y(\t$2313 ) + ); + XOR2x1_ASAP7_75t_R \U$1244 ( + .A(\t$2313 ), + .B(a_registered[19]), + .Y(booth_b18_m32) + ); + INVx1_ASAP7_75t_R \U$1245 ( + .A(a_registered[19]), + .Y(\notsign$1070 ) + ); + INVx1_ASAP7_75t_R \U$1246 ( + .A(a_registered[19]), + .Y(\$31 ) + ); + INVx1_ASAP7_75t_R \U$1247 ( + .A(a_registered[20]), + .Y(\$32 ) + ); + INVx1_ASAP7_75t_R \U$1248 ( + .A(a_registered[21]), + .Y(\$33 ) + ); + AO33x2_ASAP7_75t_R \U$1249 ( + .A1(\$33 ), + .A2(a_registered[20]), + .A3(a_registered[19]), + .B1(a_registered[21]), + .B2(\$32 ), + .B3(\$31 ), + .Y(\sel_0$1698 ) + ); + XOR2x1_ASAP7_75t_R \U$1250 ( + .A(a_registered[20]), + .B(a_registered[19]), + .Y(\sel_1$1699 ) + ); + AO22x1_ASAP7_75t_R \U$1251 ( + .A1(1'h0), + .A2(\sel_0$1698 ), + .B1(b_registered[0]), + .B2(\sel_1$1699 ), + .Y(\t$2315 ) + ); + XOR2x1_ASAP7_75t_R \U$1252 ( + .A(\t$2315 ), + .B(a_registered[21]), + .Y(booth_b20_m0) + ); + AO22x1_ASAP7_75t_R \U$1253 ( + .A1(b_registered[0]), + .A2(\sel_0$1698 ), + .B1(b_registered[1]), + .B2(\sel_1$1699 ), + .Y(\t$2316 ) + ); + XOR2x1_ASAP7_75t_R \U$1254 ( + .A(\t$2316 ), + .B(a_registered[21]), + .Y(booth_b20_m1) + ); + AO22x1_ASAP7_75t_R \U$1255 ( + .A1(b_registered[1]), + .A2(\sel_0$1698 ), + .B1(b_registered[2]), + .B2(\sel_1$1699 ), + .Y(\t$2317 ) + ); + XOR2x1_ASAP7_75t_R \U$1256 ( + .A(\t$2317 ), + .B(a_registered[21]), + .Y(booth_b20_m2) + ); + AO22x1_ASAP7_75t_R \U$1257 ( + .A1(b_registered[2]), + .A2(\sel_0$1698 ), + .B1(b_registered[3]), + .B2(\sel_1$1699 ), + .Y(\t$2318 ) + ); + XOR2x1_ASAP7_75t_R \U$1258 ( + .A(\t$2318 ), + .B(a_registered[21]), + .Y(booth_b20_m3) + ); + AO22x1_ASAP7_75t_R \U$1259 ( + .A1(b_registered[3]), + .A2(\sel_0$1698 ), + .B1(b_registered[4]), + .B2(\sel_1$1699 ), + .Y(\t$2319 ) + ); + XOR2x1_ASAP7_75t_R \U$1260 ( + .A(\t$2319 ), + .B(a_registered[21]), + .Y(booth_b20_m4) + ); + AO22x1_ASAP7_75t_R \U$1261 ( + .A1(b_registered[4]), + .A2(\sel_0$1698 ), + .B1(b_registered[5]), + .B2(\sel_1$1699 ), + .Y(\t$2320 ) + ); + XOR2x1_ASAP7_75t_R \U$1262 ( + .A(\t$2320 ), + .B(a_registered[21]), + .Y(booth_b20_m5) + ); + AO22x1_ASAP7_75t_R \U$1263 ( + .A1(b_registered[5]), + .A2(\sel_0$1698 ), + .B1(b_registered[6]), + .B2(\sel_1$1699 ), + .Y(\t$2321 ) + ); + XOR2x1_ASAP7_75t_R \U$1264 ( + .A(\t$2321 ), + .B(a_registered[21]), + .Y(booth_b20_m6) + ); + AO22x1_ASAP7_75t_R \U$1265 ( + .A1(b_registered[6]), + .A2(\sel_0$1698 ), + .B1(b_registered[7]), + .B2(\sel_1$1699 ), + .Y(\t$2322 ) + ); + XOR2x1_ASAP7_75t_R \U$1266 ( + .A(\t$2322 ), + .B(a_registered[21]), + .Y(booth_b20_m7) + ); + AO22x1_ASAP7_75t_R \U$1267 ( + .A1(b_registered[7]), + .A2(\sel_0$1698 ), + .B1(b_registered[8]), + .B2(\sel_1$1699 ), + .Y(\t$2323 ) + ); + XOR2x1_ASAP7_75t_R \U$1268 ( + .A(\t$2323 ), + .B(a_registered[21]), + .Y(booth_b20_m8) + ); + AO22x1_ASAP7_75t_R \U$1269 ( + .A1(b_registered[8]), + .A2(\sel_0$1698 ), + .B1(b_registered[9]), + .B2(\sel_1$1699 ), + .Y(\t$2324 ) + ); + XOR2x1_ASAP7_75t_R \U$1270 ( + .A(\t$2324 ), + .B(a_registered[21]), + .Y(booth_b20_m9) + ); + AO22x1_ASAP7_75t_R \U$1271 ( + .A1(b_registered[9]), + .A2(\sel_0$1698 ), + .B1(b_registered[10]), + .B2(\sel_1$1699 ), + .Y(\t$2325 ) + ); + XOR2x1_ASAP7_75t_R \U$1272 ( + .A(\t$2325 ), + .B(a_registered[21]), + .Y(booth_b20_m10) + ); + AO22x1_ASAP7_75t_R \U$1273 ( + .A1(b_registered[10]), + .A2(\sel_0$1698 ), + .B1(b_registered[11]), + .B2(\sel_1$1699 ), + .Y(\t$2326 ) + ); + XOR2x1_ASAP7_75t_R \U$1274 ( + .A(\t$2326 ), + .B(a_registered[21]), + .Y(booth_b20_m11) + ); + AO22x1_ASAP7_75t_R \U$1275 ( + .A1(b_registered[11]), + .A2(\sel_0$1698 ), + .B1(b_registered[12]), + .B2(\sel_1$1699 ), + .Y(\t$2327 ) + ); + XOR2x1_ASAP7_75t_R \U$1276 ( + .A(\t$2327 ), + .B(a_registered[21]), + .Y(booth_b20_m12) + ); + AO22x1_ASAP7_75t_R \U$1277 ( + .A1(b_registered[12]), + .A2(\sel_0$1698 ), + .B1(b_registered[13]), + .B2(\sel_1$1699 ), + .Y(\t$2328 ) + ); + XOR2x1_ASAP7_75t_R \U$1278 ( + .A(\t$2328 ), + .B(a_registered[21]), + .Y(booth_b20_m13) + ); + AO22x1_ASAP7_75t_R \U$1279 ( + .A1(b_registered[13]), + .A2(\sel_0$1698 ), + .B1(b_registered[14]), + .B2(\sel_1$1699 ), + .Y(\t$2329 ) + ); + XOR2x1_ASAP7_75t_R \U$1280 ( + .A(\t$2329 ), + .B(a_registered[21]), + .Y(booth_b20_m14) + ); + AO22x1_ASAP7_75t_R \U$1281 ( + .A1(b_registered[14]), + .A2(\sel_0$1698 ), + .B1(b_registered[15]), + .B2(\sel_1$1699 ), + .Y(\t$2330 ) + ); + XOR2x1_ASAP7_75t_R \U$1282 ( + .A(\t$2330 ), + .B(a_registered[21]), + .Y(booth_b20_m15) + ); + AO22x1_ASAP7_75t_R \U$1283 ( + .A1(b_registered[15]), + .A2(\sel_0$1698 ), + .B1(b_registered[16]), + .B2(\sel_1$1699 ), + .Y(\t$2331 ) + ); + XOR2x1_ASAP7_75t_R \U$1284 ( + .A(\t$2331 ), + .B(a_registered[21]), + .Y(booth_b20_m16) + ); + AO22x1_ASAP7_75t_R \U$1285 ( + .A1(b_registered[16]), + .A2(\sel_0$1698 ), + .B1(b_registered[17]), + .B2(\sel_1$1699 ), + .Y(\t$2332 ) + ); + XOR2x1_ASAP7_75t_R \U$1286 ( + .A(\t$2332 ), + .B(a_registered[21]), + .Y(booth_b20_m17) + ); + AO22x1_ASAP7_75t_R \U$1287 ( + .A1(b_registered[17]), + .A2(\sel_0$1698 ), + .B1(b_registered[18]), + .B2(\sel_1$1699 ), + .Y(\t$2333 ) + ); + XOR2x1_ASAP7_75t_R \U$1288 ( + .A(\t$2333 ), + .B(a_registered[21]), + .Y(booth_b20_m18) + ); + AO22x1_ASAP7_75t_R \U$1289 ( + .A1(b_registered[18]), + .A2(\sel_0$1698 ), + .B1(b_registered[19]), + .B2(\sel_1$1699 ), + .Y(\t$2334 ) + ); + XOR2x1_ASAP7_75t_R \U$1290 ( + .A(\t$2334 ), + .B(a_registered[21]), + .Y(booth_b20_m19) + ); + AO22x1_ASAP7_75t_R \U$1291 ( + .A1(b_registered[19]), + .A2(\sel_0$1698 ), + .B1(b_registered[20]), + .B2(\sel_1$1699 ), + .Y(\t$2335 ) + ); + XOR2x1_ASAP7_75t_R \U$1292 ( + .A(\t$2335 ), + .B(a_registered[21]), + .Y(booth_b20_m20) + ); + AO22x1_ASAP7_75t_R \U$1293 ( + .A1(b_registered[20]), + .A2(\sel_0$1698 ), + .B1(b_registered[21]), + .B2(\sel_1$1699 ), + .Y(\t$2336 ) + ); + XOR2x1_ASAP7_75t_R \U$1294 ( + .A(\t$2336 ), + .B(a_registered[21]), + .Y(booth_b20_m21) + ); + AO22x1_ASAP7_75t_R \U$1295 ( + .A1(b_registered[21]), + .A2(\sel_0$1698 ), + .B1(b_registered[22]), + .B2(\sel_1$1699 ), + .Y(\t$2337 ) + ); + XOR2x1_ASAP7_75t_R \U$1296 ( + .A(\t$2337 ), + .B(a_registered[21]), + .Y(booth_b20_m22) + ); + AO22x1_ASAP7_75t_R \U$1297 ( + .A1(b_registered[22]), + .A2(\sel_0$1698 ), + .B1(b_registered[23]), + .B2(\sel_1$1699 ), + .Y(\t$2338 ) + ); + XOR2x1_ASAP7_75t_R \U$1298 ( + .A(\t$2338 ), + .B(a_registered[21]), + .Y(booth_b20_m23) + ); + AO22x1_ASAP7_75t_R \U$1299 ( + .A1(b_registered[23]), + .A2(\sel_0$1698 ), + .B1(b_registered[24]), + .B2(\sel_1$1699 ), + .Y(\t$2339 ) + ); + XOR2x1_ASAP7_75t_R \U$1300 ( + .A(\t$2339 ), + .B(a_registered[21]), + .Y(booth_b20_m24) + ); + AO22x1_ASAP7_75t_R \U$1301 ( + .A1(b_registered[24]), + .A2(\sel_0$1698 ), + .B1(b_registered[25]), + .B2(\sel_1$1699 ), + .Y(\t$2340 ) + ); + XOR2x1_ASAP7_75t_R \U$1302 ( + .A(\t$2340 ), + .B(a_registered[21]), + .Y(booth_b20_m25) + ); + AO22x1_ASAP7_75t_R \U$1303 ( + .A1(b_registered[25]), + .A2(\sel_0$1698 ), + .B1(b_registered[26]), + .B2(\sel_1$1699 ), + .Y(\t$2341 ) + ); + XOR2x1_ASAP7_75t_R \U$1304 ( + .A(\t$2341 ), + .B(a_registered[21]), + .Y(booth_b20_m26) + ); + AO22x1_ASAP7_75t_R \U$1305 ( + .A1(b_registered[26]), + .A2(\sel_0$1698 ), + .B1(b_registered[27]), + .B2(\sel_1$1699 ), + .Y(\t$2342 ) + ); + XOR2x1_ASAP7_75t_R \U$1306 ( + .A(\t$2342 ), + .B(a_registered[21]), + .Y(booth_b20_m27) + ); + AO22x1_ASAP7_75t_R \U$1307 ( + .A1(b_registered[27]), + .A2(\sel_0$1698 ), + .B1(b_registered[28]), + .B2(\sel_1$1699 ), + .Y(\t$2343 ) + ); + XOR2x1_ASAP7_75t_R \U$1308 ( + .A(\t$2343 ), + .B(a_registered[21]), + .Y(booth_b20_m28) + ); + AO22x1_ASAP7_75t_R \U$1309 ( + .A1(b_registered[28]), + .A2(\sel_0$1698 ), + .B1(b_registered[29]), + .B2(\sel_1$1699 ), + .Y(\t$2344 ) + ); + XOR2x1_ASAP7_75t_R \U$1310 ( + .A(\t$2344 ), + .B(a_registered[21]), + .Y(booth_b20_m29) + ); + AO22x1_ASAP7_75t_R \U$1311 ( + .A1(b_registered[29]), + .A2(\sel_0$1698 ), + .B1(b_registered[30]), + .B2(\sel_1$1699 ), + .Y(\t$2345 ) + ); + XOR2x1_ASAP7_75t_R \U$1312 ( + .A(\t$2345 ), + .B(a_registered[21]), + .Y(booth_b20_m30) + ); + AO22x1_ASAP7_75t_R \U$1313 ( + .A1(b_registered[30]), + .A2(\sel_0$1698 ), + .B1(b_registered[31]), + .B2(\sel_1$1699 ), + .Y(\t$2346 ) + ); + XOR2x1_ASAP7_75t_R \U$1314 ( + .A(\t$2346 ), + .B(a_registered[21]), + .Y(booth_b20_m31) + ); + AO22x1_ASAP7_75t_R \U$1315 ( + .A1(b_registered[31]), + .A2(\sel_0$1698 ), + .B1(1'h0), + .B2(\sel_1$1699 ), + .Y(\t$2347 ) + ); + XOR2x1_ASAP7_75t_R \U$1316 ( + .A(\t$2347 ), + .B(a_registered[21]), + .Y(booth_b20_m32) + ); + INVx1_ASAP7_75t_R \U$1317 ( + .A(a_registered[21]), + .Y(\notsign$1100 ) + ); + INVx1_ASAP7_75t_R \U$1318 ( + .A(a_registered[21]), + .Y(\$34 ) + ); + INVx1_ASAP7_75t_R \U$1319 ( + .A(a_registered[22]), + .Y(\$35 ) + ); + INVx1_ASAP7_75t_R \U$1320 ( + .A(a_registered[23]), + .Y(\$36 ) + ); + AO33x2_ASAP7_75t_R \U$1321 ( + .A1(\$36 ), + .A2(a_registered[22]), + .A3(a_registered[21]), + .B1(a_registered[23]), + .B2(\$35 ), + .B3(\$34 ), + .Y(\sel_0$1735 ) + ); + XOR2x1_ASAP7_75t_R \U$1322 ( + .A(a_registered[22]), + .B(a_registered[21]), + .Y(\sel_1$1736 ) + ); + AO22x1_ASAP7_75t_R \U$1323 ( + .A1(1'h0), + .A2(\sel_0$1735 ), + .B1(b_registered[0]), + .B2(\sel_1$1736 ), + .Y(\t$2349 ) + ); + XOR2x1_ASAP7_75t_R \U$1324 ( + .A(\t$2349 ), + .B(a_registered[23]), + .Y(booth_b22_m0) + ); + AO22x1_ASAP7_75t_R \U$1325 ( + .A1(b_registered[0]), + .A2(\sel_0$1735 ), + .B1(b_registered[1]), + .B2(\sel_1$1736 ), + .Y(\t$2350 ) + ); + XOR2x1_ASAP7_75t_R \U$1326 ( + .A(\t$2350 ), + .B(a_registered[23]), + .Y(booth_b22_m1) + ); + AO22x1_ASAP7_75t_R \U$1327 ( + .A1(b_registered[1]), + .A2(\sel_0$1735 ), + .B1(b_registered[2]), + .B2(\sel_1$1736 ), + .Y(\t$2351 ) + ); + XOR2x1_ASAP7_75t_R \U$1328 ( + .A(\t$2351 ), + .B(a_registered[23]), + .Y(booth_b22_m2) + ); + AO22x1_ASAP7_75t_R \U$1329 ( + .A1(b_registered[2]), + .A2(\sel_0$1735 ), + .B1(b_registered[3]), + .B2(\sel_1$1736 ), + .Y(\t$2352 ) + ); + XOR2x1_ASAP7_75t_R \U$1330 ( + .A(\t$2352 ), + .B(a_registered[23]), + .Y(booth_b22_m3) + ); + AO22x1_ASAP7_75t_R \U$1331 ( + .A1(b_registered[3]), + .A2(\sel_0$1735 ), + .B1(b_registered[4]), + .B2(\sel_1$1736 ), + .Y(\t$2353 ) + ); + XOR2x1_ASAP7_75t_R \U$1332 ( + .A(\t$2353 ), + .B(a_registered[23]), + .Y(booth_b22_m4) + ); + AO22x1_ASAP7_75t_R \U$1333 ( + .A1(b_registered[4]), + .A2(\sel_0$1735 ), + .B1(b_registered[5]), + .B2(\sel_1$1736 ), + .Y(\t$2354 ) + ); + XOR2x1_ASAP7_75t_R \U$1334 ( + .A(\t$2354 ), + .B(a_registered[23]), + .Y(booth_b22_m5) + ); + AO22x1_ASAP7_75t_R \U$1335 ( + .A1(b_registered[5]), + .A2(\sel_0$1735 ), + .B1(b_registered[6]), + .B2(\sel_1$1736 ), + .Y(\t$2355 ) + ); + XOR2x1_ASAP7_75t_R \U$1336 ( + .A(\t$2355 ), + .B(a_registered[23]), + .Y(booth_b22_m6) + ); + AO22x1_ASAP7_75t_R \U$1337 ( + .A1(b_registered[6]), + .A2(\sel_0$1735 ), + .B1(b_registered[7]), + .B2(\sel_1$1736 ), + .Y(\t$2356 ) + ); + XOR2x1_ASAP7_75t_R \U$1338 ( + .A(\t$2356 ), + .B(a_registered[23]), + .Y(booth_b22_m7) + ); + AO22x1_ASAP7_75t_R \U$1339 ( + .A1(b_registered[7]), + .A2(\sel_0$1735 ), + .B1(b_registered[8]), + .B2(\sel_1$1736 ), + .Y(\t$2357 ) + ); + XOR2x1_ASAP7_75t_R \U$1340 ( + .A(\t$2357 ), + .B(a_registered[23]), + .Y(booth_b22_m8) + ); + AO22x1_ASAP7_75t_R \U$1341 ( + .A1(b_registered[8]), + .A2(\sel_0$1735 ), + .B1(b_registered[9]), + .B2(\sel_1$1736 ), + .Y(\t$2358 ) + ); + XOR2x1_ASAP7_75t_R \U$1342 ( + .A(\t$2358 ), + .B(a_registered[23]), + .Y(booth_b22_m9) + ); + AO22x1_ASAP7_75t_R \U$1343 ( + .A1(b_registered[9]), + .A2(\sel_0$1735 ), + .B1(b_registered[10]), + .B2(\sel_1$1736 ), + .Y(\t$2359 ) + ); + XOR2x1_ASAP7_75t_R \U$1344 ( + .A(\t$2359 ), + .B(a_registered[23]), + .Y(booth_b22_m10) + ); + AO22x1_ASAP7_75t_R \U$1345 ( + .A1(b_registered[10]), + .A2(\sel_0$1735 ), + .B1(b_registered[11]), + .B2(\sel_1$1736 ), + .Y(\t$2360 ) + ); + XOR2x1_ASAP7_75t_R \U$1346 ( + .A(\t$2360 ), + .B(a_registered[23]), + .Y(booth_b22_m11) + ); + AO22x1_ASAP7_75t_R \U$1347 ( + .A1(b_registered[11]), + .A2(\sel_0$1735 ), + .B1(b_registered[12]), + .B2(\sel_1$1736 ), + .Y(\t$2361 ) + ); + XOR2x1_ASAP7_75t_R \U$1348 ( + .A(\t$2361 ), + .B(a_registered[23]), + .Y(booth_b22_m12) + ); + AO22x1_ASAP7_75t_R \U$1349 ( + .A1(b_registered[12]), + .A2(\sel_0$1735 ), + .B1(b_registered[13]), + .B2(\sel_1$1736 ), + .Y(\t$2362 ) + ); + XOR2x1_ASAP7_75t_R \U$1350 ( + .A(\t$2362 ), + .B(a_registered[23]), + .Y(booth_b22_m13) + ); + AO22x1_ASAP7_75t_R \U$1351 ( + .A1(b_registered[13]), + .A2(\sel_0$1735 ), + .B1(b_registered[14]), + .B2(\sel_1$1736 ), + .Y(\t$2363 ) + ); + XOR2x1_ASAP7_75t_R \U$1352 ( + .A(\t$2363 ), + .B(a_registered[23]), + .Y(booth_b22_m14) + ); + AO22x1_ASAP7_75t_R \U$1353 ( + .A1(b_registered[14]), + .A2(\sel_0$1735 ), + .B1(b_registered[15]), + .B2(\sel_1$1736 ), + .Y(\t$2364 ) + ); + XOR2x1_ASAP7_75t_R \U$1354 ( + .A(\t$2364 ), + .B(a_registered[23]), + .Y(booth_b22_m15) + ); + AO22x1_ASAP7_75t_R \U$1355 ( + .A1(b_registered[15]), + .A2(\sel_0$1735 ), + .B1(b_registered[16]), + .B2(\sel_1$1736 ), + .Y(\t$2365 ) + ); + XOR2x1_ASAP7_75t_R \U$1356 ( + .A(\t$2365 ), + .B(a_registered[23]), + .Y(booth_b22_m16) + ); + AO22x1_ASAP7_75t_R \U$1357 ( + .A1(b_registered[16]), + .A2(\sel_0$1735 ), + .B1(b_registered[17]), + .B2(\sel_1$1736 ), + .Y(\t$2366 ) + ); + XOR2x1_ASAP7_75t_R \U$1358 ( + .A(\t$2366 ), + .B(a_registered[23]), + .Y(booth_b22_m17) + ); + AO22x1_ASAP7_75t_R \U$1359 ( + .A1(b_registered[17]), + .A2(\sel_0$1735 ), + .B1(b_registered[18]), + .B2(\sel_1$1736 ), + .Y(\t$2367 ) + ); + XOR2x1_ASAP7_75t_R \U$1360 ( + .A(\t$2367 ), + .B(a_registered[23]), + .Y(booth_b22_m18) + ); + AO22x1_ASAP7_75t_R \U$1361 ( + .A1(b_registered[18]), + .A2(\sel_0$1735 ), + .B1(b_registered[19]), + .B2(\sel_1$1736 ), + .Y(\t$2368 ) + ); + XOR2x1_ASAP7_75t_R \U$1362 ( + .A(\t$2368 ), + .B(a_registered[23]), + .Y(booth_b22_m19) + ); + AO22x1_ASAP7_75t_R \U$1363 ( + .A1(b_registered[19]), + .A2(\sel_0$1735 ), + .B1(b_registered[20]), + .B2(\sel_1$1736 ), + .Y(\t$2369 ) + ); + XOR2x1_ASAP7_75t_R \U$1364 ( + .A(\t$2369 ), + .B(a_registered[23]), + .Y(booth_b22_m20) + ); + AO22x1_ASAP7_75t_R \U$1365 ( + .A1(b_registered[20]), + .A2(\sel_0$1735 ), + .B1(b_registered[21]), + .B2(\sel_1$1736 ), + .Y(\t$2370 ) + ); + XOR2x1_ASAP7_75t_R \U$1366 ( + .A(\t$2370 ), + .B(a_registered[23]), + .Y(booth_b22_m21) + ); + AO22x1_ASAP7_75t_R \U$1367 ( + .A1(b_registered[21]), + .A2(\sel_0$1735 ), + .B1(b_registered[22]), + .B2(\sel_1$1736 ), + .Y(\t$2371 ) + ); + XOR2x1_ASAP7_75t_R \U$1368 ( + .A(\t$2371 ), + .B(a_registered[23]), + .Y(booth_b22_m22) + ); + AO22x1_ASAP7_75t_R \U$1369 ( + .A1(b_registered[22]), + .A2(\sel_0$1735 ), + .B1(b_registered[23]), + .B2(\sel_1$1736 ), + .Y(\t$2372 ) + ); + XOR2x1_ASAP7_75t_R \U$1370 ( + .A(\t$2372 ), + .B(a_registered[23]), + .Y(booth_b22_m23) + ); + AO22x1_ASAP7_75t_R \U$1371 ( + .A1(b_registered[23]), + .A2(\sel_0$1735 ), + .B1(b_registered[24]), + .B2(\sel_1$1736 ), + .Y(\t$2373 ) + ); + XOR2x1_ASAP7_75t_R \U$1372 ( + .A(\t$2373 ), + .B(a_registered[23]), + .Y(booth_b22_m24) + ); + AO22x1_ASAP7_75t_R \U$1373 ( + .A1(b_registered[24]), + .A2(\sel_0$1735 ), + .B1(b_registered[25]), + .B2(\sel_1$1736 ), + .Y(\t$2374 ) + ); + XOR2x1_ASAP7_75t_R \U$1374 ( + .A(\t$2374 ), + .B(a_registered[23]), + .Y(booth_b22_m25) + ); + AO22x1_ASAP7_75t_R \U$1375 ( + .A1(b_registered[25]), + .A2(\sel_0$1735 ), + .B1(b_registered[26]), + .B2(\sel_1$1736 ), + .Y(\t$2375 ) + ); + XOR2x1_ASAP7_75t_R \U$1376 ( + .A(\t$2375 ), + .B(a_registered[23]), + .Y(booth_b22_m26) + ); + AO22x1_ASAP7_75t_R \U$1377 ( + .A1(b_registered[26]), + .A2(\sel_0$1735 ), + .B1(b_registered[27]), + .B2(\sel_1$1736 ), + .Y(\t$2376 ) + ); + XOR2x1_ASAP7_75t_R \U$1378 ( + .A(\t$2376 ), + .B(a_registered[23]), + .Y(booth_b22_m27) + ); + AO22x1_ASAP7_75t_R \U$1379 ( + .A1(b_registered[27]), + .A2(\sel_0$1735 ), + .B1(b_registered[28]), + .B2(\sel_1$1736 ), + .Y(\t$2377 ) + ); + XOR2x1_ASAP7_75t_R \U$1380 ( + .A(\t$2377 ), + .B(a_registered[23]), + .Y(booth_b22_m28) + ); + AO22x1_ASAP7_75t_R \U$1381 ( + .A1(b_registered[28]), + .A2(\sel_0$1735 ), + .B1(b_registered[29]), + .B2(\sel_1$1736 ), + .Y(\t$2378 ) + ); + XOR2x1_ASAP7_75t_R \U$1382 ( + .A(\t$2378 ), + .B(a_registered[23]), + .Y(booth_b22_m29) + ); + AO22x1_ASAP7_75t_R \U$1383 ( + .A1(b_registered[29]), + .A2(\sel_0$1735 ), + .B1(b_registered[30]), + .B2(\sel_1$1736 ), + .Y(\t$2379 ) + ); + XOR2x1_ASAP7_75t_R \U$1384 ( + .A(\t$2379 ), + .B(a_registered[23]), + .Y(booth_b22_m30) + ); + AO22x1_ASAP7_75t_R \U$1385 ( + .A1(b_registered[30]), + .A2(\sel_0$1735 ), + .B1(b_registered[31]), + .B2(\sel_1$1736 ), + .Y(\t$2380 ) + ); + XOR2x1_ASAP7_75t_R \U$1386 ( + .A(\t$2380 ), + .B(a_registered[23]), + .Y(booth_b22_m31) + ); + AO22x1_ASAP7_75t_R \U$1387 ( + .A1(b_registered[31]), + .A2(\sel_0$1735 ), + .B1(1'h0), + .B2(\sel_1$1736 ), + .Y(\t$2381 ) + ); + XOR2x1_ASAP7_75t_R \U$1388 ( + .A(\t$2381 ), + .B(a_registered[23]), + .Y(booth_b22_m32) + ); + INVx1_ASAP7_75t_R \U$1389 ( + .A(a_registered[23]), + .Y(\notsign$1126 ) + ); + INVx1_ASAP7_75t_R \U$1390 ( + .A(a_registered[23]), + .Y(\$37 ) + ); + INVx1_ASAP7_75t_R \U$1391 ( + .A(a_registered[24]), + .Y(\$38 ) + ); + INVx1_ASAP7_75t_R \U$1392 ( + .A(a_registered[25]), + .Y(\$39 ) + ); + AO33x2_ASAP7_75t_R \U$1393 ( + .A1(\$39 ), + .A2(a_registered[24]), + .A3(a_registered[23]), + .B1(a_registered[25]), + .B2(\$38 ), + .B3(\$37 ), + .Y(\sel_0$1772 ) + ); + XOR2x1_ASAP7_75t_R \U$1394 ( + .A(a_registered[24]), + .B(a_registered[23]), + .Y(\sel_1$1773 ) + ); + AO22x1_ASAP7_75t_R \U$1395 ( + .A1(1'h0), + .A2(\sel_0$1772 ), + .B1(b_registered[0]), + .B2(\sel_1$1773 ), + .Y(\t$2383 ) + ); + XOR2x1_ASAP7_75t_R \U$1396 ( + .A(\t$2383 ), + .B(a_registered[25]), + .Y(booth_b24_m0) + ); + AO22x1_ASAP7_75t_R \U$1397 ( + .A1(b_registered[0]), + .A2(\sel_0$1772 ), + .B1(b_registered[1]), + .B2(\sel_1$1773 ), + .Y(\t$2384 ) + ); + XOR2x1_ASAP7_75t_R \U$1398 ( + .A(\t$2384 ), + .B(a_registered[25]), + .Y(booth_b24_m1) + ); + AO22x1_ASAP7_75t_R \U$1399 ( + .A1(b_registered[1]), + .A2(\sel_0$1772 ), + .B1(b_registered[2]), + .B2(\sel_1$1773 ), + .Y(\t$2385 ) + ); + XOR2x1_ASAP7_75t_R \U$1400 ( + .A(\t$2385 ), + .B(a_registered[25]), + .Y(booth_b24_m2) + ); + AO22x1_ASAP7_75t_R \U$1401 ( + .A1(b_registered[2]), + .A2(\sel_0$1772 ), + .B1(b_registered[3]), + .B2(\sel_1$1773 ), + .Y(\t$2386 ) + ); + XOR2x1_ASAP7_75t_R \U$1402 ( + .A(\t$2386 ), + .B(a_registered[25]), + .Y(booth_b24_m3) + ); + AO22x1_ASAP7_75t_R \U$1403 ( + .A1(b_registered[3]), + .A2(\sel_0$1772 ), + .B1(b_registered[4]), + .B2(\sel_1$1773 ), + .Y(\t$2387 ) + ); + XOR2x1_ASAP7_75t_R \U$1404 ( + .A(\t$2387 ), + .B(a_registered[25]), + .Y(booth_b24_m4) + ); + AO22x1_ASAP7_75t_R \U$1405 ( + .A1(b_registered[4]), + .A2(\sel_0$1772 ), + .B1(b_registered[5]), + .B2(\sel_1$1773 ), + .Y(\t$2388 ) + ); + XOR2x1_ASAP7_75t_R \U$1406 ( + .A(\t$2388 ), + .B(a_registered[25]), + .Y(booth_b24_m5) + ); + AO22x1_ASAP7_75t_R \U$1407 ( + .A1(b_registered[5]), + .A2(\sel_0$1772 ), + .B1(b_registered[6]), + .B2(\sel_1$1773 ), + .Y(\t$2389 ) + ); + XOR2x1_ASAP7_75t_R \U$1408 ( + .A(\t$2389 ), + .B(a_registered[25]), + .Y(booth_b24_m6) + ); + AO22x1_ASAP7_75t_R \U$1409 ( + .A1(b_registered[6]), + .A2(\sel_0$1772 ), + .B1(b_registered[7]), + .B2(\sel_1$1773 ), + .Y(\t$2390 ) + ); + XOR2x1_ASAP7_75t_R \U$1410 ( + .A(\t$2390 ), + .B(a_registered[25]), + .Y(booth_b24_m7) + ); + AO22x1_ASAP7_75t_R \U$1411 ( + .A1(b_registered[7]), + .A2(\sel_0$1772 ), + .B1(b_registered[8]), + .B2(\sel_1$1773 ), + .Y(\t$2391 ) + ); + XOR2x1_ASAP7_75t_R \U$1412 ( + .A(\t$2391 ), + .B(a_registered[25]), + .Y(booth_b24_m8) + ); + AO22x1_ASAP7_75t_R \U$1413 ( + .A1(b_registered[8]), + .A2(\sel_0$1772 ), + .B1(b_registered[9]), + .B2(\sel_1$1773 ), + .Y(\t$2392 ) + ); + XOR2x1_ASAP7_75t_R \U$1414 ( + .A(\t$2392 ), + .B(a_registered[25]), + .Y(booth_b24_m9) + ); + AO22x1_ASAP7_75t_R \U$1415 ( + .A1(b_registered[9]), + .A2(\sel_0$1772 ), + .B1(b_registered[10]), + .B2(\sel_1$1773 ), + .Y(\t$2393 ) + ); + XOR2x1_ASAP7_75t_R \U$1416 ( + .A(\t$2393 ), + .B(a_registered[25]), + .Y(booth_b24_m10) + ); + AO22x1_ASAP7_75t_R \U$1417 ( + .A1(b_registered[10]), + .A2(\sel_0$1772 ), + .B1(b_registered[11]), + .B2(\sel_1$1773 ), + .Y(\t$2394 ) + ); + XOR2x1_ASAP7_75t_R \U$1418 ( + .A(\t$2394 ), + .B(a_registered[25]), + .Y(booth_b24_m11) + ); + AO22x1_ASAP7_75t_R \U$1419 ( + .A1(b_registered[11]), + .A2(\sel_0$1772 ), + .B1(b_registered[12]), + .B2(\sel_1$1773 ), + .Y(\t$2395 ) + ); + XOR2x1_ASAP7_75t_R \U$1420 ( + .A(\t$2395 ), + .B(a_registered[25]), + .Y(booth_b24_m12) + ); + AO22x1_ASAP7_75t_R \U$1421 ( + .A1(b_registered[12]), + .A2(\sel_0$1772 ), + .B1(b_registered[13]), + .B2(\sel_1$1773 ), + .Y(\t$2396 ) + ); + XOR2x1_ASAP7_75t_R \U$1422 ( + .A(\t$2396 ), + .B(a_registered[25]), + .Y(booth_b24_m13) + ); + AO22x1_ASAP7_75t_R \U$1423 ( + .A1(b_registered[13]), + .A2(\sel_0$1772 ), + .B1(b_registered[14]), + .B2(\sel_1$1773 ), + .Y(\t$2397 ) + ); + XOR2x1_ASAP7_75t_R \U$1424 ( + .A(\t$2397 ), + .B(a_registered[25]), + .Y(booth_b24_m14) + ); + AO22x1_ASAP7_75t_R \U$1425 ( + .A1(b_registered[14]), + .A2(\sel_0$1772 ), + .B1(b_registered[15]), + .B2(\sel_1$1773 ), + .Y(\t$2398 ) + ); + XOR2x1_ASAP7_75t_R \U$1426 ( + .A(\t$2398 ), + .B(a_registered[25]), + .Y(booth_b24_m15) + ); + AO22x1_ASAP7_75t_R \U$1427 ( + .A1(b_registered[15]), + .A2(\sel_0$1772 ), + .B1(b_registered[16]), + .B2(\sel_1$1773 ), + .Y(\t$2399 ) + ); + XOR2x1_ASAP7_75t_R \U$1428 ( + .A(\t$2399 ), + .B(a_registered[25]), + .Y(booth_b24_m16) + ); + AO22x1_ASAP7_75t_R \U$1429 ( + .A1(b_registered[16]), + .A2(\sel_0$1772 ), + .B1(b_registered[17]), + .B2(\sel_1$1773 ), + .Y(\t$2400 ) + ); + XOR2x1_ASAP7_75t_R \U$1430 ( + .A(\t$2400 ), + .B(a_registered[25]), + .Y(booth_b24_m17) + ); + AO22x1_ASAP7_75t_R \U$1431 ( + .A1(b_registered[17]), + .A2(\sel_0$1772 ), + .B1(b_registered[18]), + .B2(\sel_1$1773 ), + .Y(\t$2401 ) + ); + XOR2x1_ASAP7_75t_R \U$1432 ( + .A(\t$2401 ), + .B(a_registered[25]), + .Y(booth_b24_m18) + ); + AO22x1_ASAP7_75t_R \U$1433 ( + .A1(b_registered[18]), + .A2(\sel_0$1772 ), + .B1(b_registered[19]), + .B2(\sel_1$1773 ), + .Y(\t$2402 ) + ); + XOR2x1_ASAP7_75t_R \U$1434 ( + .A(\t$2402 ), + .B(a_registered[25]), + .Y(booth_b24_m19) + ); + AO22x1_ASAP7_75t_R \U$1435 ( + .A1(b_registered[19]), + .A2(\sel_0$1772 ), + .B1(b_registered[20]), + .B2(\sel_1$1773 ), + .Y(\t$2403 ) + ); + XOR2x1_ASAP7_75t_R \U$1436 ( + .A(\t$2403 ), + .B(a_registered[25]), + .Y(booth_b24_m20) + ); + AO22x1_ASAP7_75t_R \U$1437 ( + .A1(b_registered[20]), + .A2(\sel_0$1772 ), + .B1(b_registered[21]), + .B2(\sel_1$1773 ), + .Y(\t$2404 ) + ); + XOR2x1_ASAP7_75t_R \U$1438 ( + .A(\t$2404 ), + .B(a_registered[25]), + .Y(booth_b24_m21) + ); + AO22x1_ASAP7_75t_R \U$1439 ( + .A1(b_registered[21]), + .A2(\sel_0$1772 ), + .B1(b_registered[22]), + .B2(\sel_1$1773 ), + .Y(\t$2405 ) + ); + XOR2x1_ASAP7_75t_R \U$1440 ( + .A(\t$2405 ), + .B(a_registered[25]), + .Y(booth_b24_m22) + ); + AO22x1_ASAP7_75t_R \U$1441 ( + .A1(b_registered[22]), + .A2(\sel_0$1772 ), + .B1(b_registered[23]), + .B2(\sel_1$1773 ), + .Y(\t$2406 ) + ); + XOR2x1_ASAP7_75t_R \U$1442 ( + .A(\t$2406 ), + .B(a_registered[25]), + .Y(booth_b24_m23) + ); + AO22x1_ASAP7_75t_R \U$1443 ( + .A1(b_registered[23]), + .A2(\sel_0$1772 ), + .B1(b_registered[24]), + .B2(\sel_1$1773 ), + .Y(\t$2407 ) + ); + XOR2x1_ASAP7_75t_R \U$1444 ( + .A(\t$2407 ), + .B(a_registered[25]), + .Y(booth_b24_m24) + ); + AO22x1_ASAP7_75t_R \U$1445 ( + .A1(b_registered[24]), + .A2(\sel_0$1772 ), + .B1(b_registered[25]), + .B2(\sel_1$1773 ), + .Y(\t$2408 ) + ); + XOR2x1_ASAP7_75t_R \U$1446 ( + .A(\t$2408 ), + .B(a_registered[25]), + .Y(booth_b24_m25) + ); + AO22x1_ASAP7_75t_R \U$1447 ( + .A1(b_registered[25]), + .A2(\sel_0$1772 ), + .B1(b_registered[26]), + .B2(\sel_1$1773 ), + .Y(\t$2409 ) + ); + XOR2x1_ASAP7_75t_R \U$1448 ( + .A(\t$2409 ), + .B(a_registered[25]), + .Y(booth_b24_m26) + ); + AO22x1_ASAP7_75t_R \U$1449 ( + .A1(b_registered[26]), + .A2(\sel_0$1772 ), + .B1(b_registered[27]), + .B2(\sel_1$1773 ), + .Y(\t$2410 ) + ); + XOR2x1_ASAP7_75t_R \U$1450 ( + .A(\t$2410 ), + .B(a_registered[25]), + .Y(booth_b24_m27) + ); + AO22x1_ASAP7_75t_R \U$1451 ( + .A1(b_registered[27]), + .A2(\sel_0$1772 ), + .B1(b_registered[28]), + .B2(\sel_1$1773 ), + .Y(\t$2411 ) + ); + XOR2x1_ASAP7_75t_R \U$1452 ( + .A(\t$2411 ), + .B(a_registered[25]), + .Y(booth_b24_m28) + ); + AO22x1_ASAP7_75t_R \U$1453 ( + .A1(b_registered[28]), + .A2(\sel_0$1772 ), + .B1(b_registered[29]), + .B2(\sel_1$1773 ), + .Y(\t$2412 ) + ); + XOR2x1_ASAP7_75t_R \U$1454 ( + .A(\t$2412 ), + .B(a_registered[25]), + .Y(booth_b24_m29) + ); + AO22x1_ASAP7_75t_R \U$1455 ( + .A1(b_registered[29]), + .A2(\sel_0$1772 ), + .B1(b_registered[30]), + .B2(\sel_1$1773 ), + .Y(\t$2413 ) + ); + XOR2x1_ASAP7_75t_R \U$1456 ( + .A(\t$2413 ), + .B(a_registered[25]), + .Y(booth_b24_m30) + ); + AO22x1_ASAP7_75t_R \U$1457 ( + .A1(b_registered[30]), + .A2(\sel_0$1772 ), + .B1(b_registered[31]), + .B2(\sel_1$1773 ), + .Y(\t$2414 ) + ); + XOR2x1_ASAP7_75t_R \U$1458 ( + .A(\t$2414 ), + .B(a_registered[25]), + .Y(booth_b24_m31) + ); + AO22x1_ASAP7_75t_R \U$1459 ( + .A1(b_registered[31]), + .A2(\sel_0$1772 ), + .B1(1'h0), + .B2(\sel_1$1773 ), + .Y(\t$2415 ) + ); + XOR2x1_ASAP7_75t_R \U$1460 ( + .A(\t$2415 ), + .B(a_registered[25]), + .Y(booth_b24_m32) + ); + INVx1_ASAP7_75t_R \U$1461 ( + .A(a_registered[25]), + .Y(\notsign$1148 ) + ); + INVx1_ASAP7_75t_R \U$1462 ( + .A(a_registered[25]), + .Y(\$40 ) + ); + INVx1_ASAP7_75t_R \U$1463 ( + .A(a_registered[26]), + .Y(\$41 ) + ); + INVx1_ASAP7_75t_R \U$1464 ( + .A(a_registered[27]), + .Y(\$42 ) + ); + AO33x2_ASAP7_75t_R \U$1465 ( + .A1(\$42 ), + .A2(a_registered[26]), + .A3(a_registered[25]), + .B1(a_registered[27]), + .B2(\$41 ), + .B3(\$40 ), + .Y(\sel_0$1809 ) + ); + XOR2x1_ASAP7_75t_R \U$1466 ( + .A(a_registered[26]), + .B(a_registered[25]), + .Y(\sel_1$1810 ) + ); + AO22x1_ASAP7_75t_R \U$1467 ( + .A1(1'h0), + .A2(\sel_0$1809 ), + .B1(b_registered[0]), + .B2(\sel_1$1810 ), + .Y(\t$2417 ) + ); + XOR2x1_ASAP7_75t_R \U$1468 ( + .A(\t$2417 ), + .B(a_registered[27]), + .Y(booth_b26_m0) + ); + AO22x1_ASAP7_75t_R \U$1469 ( + .A1(b_registered[0]), + .A2(\sel_0$1809 ), + .B1(b_registered[1]), + .B2(\sel_1$1810 ), + .Y(\t$2418 ) + ); + XOR2x1_ASAP7_75t_R \U$1470 ( + .A(\t$2418 ), + .B(a_registered[27]), + .Y(booth_b26_m1) + ); + AO22x1_ASAP7_75t_R \U$1471 ( + .A1(b_registered[1]), + .A2(\sel_0$1809 ), + .B1(b_registered[2]), + .B2(\sel_1$1810 ), + .Y(\t$2419 ) + ); + XOR2x1_ASAP7_75t_R \U$1472 ( + .A(\t$2419 ), + .B(a_registered[27]), + .Y(booth_b26_m2) + ); + AO22x1_ASAP7_75t_R \U$1473 ( + .A1(b_registered[2]), + .A2(\sel_0$1809 ), + .B1(b_registered[3]), + .B2(\sel_1$1810 ), + .Y(\t$2420 ) + ); + XOR2x1_ASAP7_75t_R \U$1474 ( + .A(\t$2420 ), + .B(a_registered[27]), + .Y(booth_b26_m3) + ); + AO22x1_ASAP7_75t_R \U$1475 ( + .A1(b_registered[3]), + .A2(\sel_0$1809 ), + .B1(b_registered[4]), + .B2(\sel_1$1810 ), + .Y(\t$2421 ) + ); + XOR2x1_ASAP7_75t_R \U$1476 ( + .A(\t$2421 ), + .B(a_registered[27]), + .Y(booth_b26_m4) + ); + AO22x1_ASAP7_75t_R \U$1477 ( + .A1(b_registered[4]), + .A2(\sel_0$1809 ), + .B1(b_registered[5]), + .B2(\sel_1$1810 ), + .Y(\t$2422 ) + ); + XOR2x1_ASAP7_75t_R \U$1478 ( + .A(\t$2422 ), + .B(a_registered[27]), + .Y(booth_b26_m5) + ); + AO22x1_ASAP7_75t_R \U$1479 ( + .A1(b_registered[5]), + .A2(\sel_0$1809 ), + .B1(b_registered[6]), + .B2(\sel_1$1810 ), + .Y(\t$2423 ) + ); + XOR2x1_ASAP7_75t_R \U$1480 ( + .A(\t$2423 ), + .B(a_registered[27]), + .Y(booth_b26_m6) + ); + AO22x1_ASAP7_75t_R \U$1481 ( + .A1(b_registered[6]), + .A2(\sel_0$1809 ), + .B1(b_registered[7]), + .B2(\sel_1$1810 ), + .Y(\t$2424 ) + ); + XOR2x1_ASAP7_75t_R \U$1482 ( + .A(\t$2424 ), + .B(a_registered[27]), + .Y(booth_b26_m7) + ); + AO22x1_ASAP7_75t_R \U$1483 ( + .A1(b_registered[7]), + .A2(\sel_0$1809 ), + .B1(b_registered[8]), + .B2(\sel_1$1810 ), + .Y(\t$2425 ) + ); + XOR2x1_ASAP7_75t_R \U$1484 ( + .A(\t$2425 ), + .B(a_registered[27]), + .Y(booth_b26_m8) + ); + AO22x1_ASAP7_75t_R \U$1485 ( + .A1(b_registered[8]), + .A2(\sel_0$1809 ), + .B1(b_registered[9]), + .B2(\sel_1$1810 ), + .Y(\t$2426 ) + ); + XOR2x1_ASAP7_75t_R \U$1486 ( + .A(\t$2426 ), + .B(a_registered[27]), + .Y(booth_b26_m9) + ); + AO22x1_ASAP7_75t_R \U$1487 ( + .A1(b_registered[9]), + .A2(\sel_0$1809 ), + .B1(b_registered[10]), + .B2(\sel_1$1810 ), + .Y(\t$2427 ) + ); + XOR2x1_ASAP7_75t_R \U$1488 ( + .A(\t$2427 ), + .B(a_registered[27]), + .Y(booth_b26_m10) + ); + AO22x1_ASAP7_75t_R \U$1489 ( + .A1(b_registered[10]), + .A2(\sel_0$1809 ), + .B1(b_registered[11]), + .B2(\sel_1$1810 ), + .Y(\t$2428 ) + ); + XOR2x1_ASAP7_75t_R \U$1490 ( + .A(\t$2428 ), + .B(a_registered[27]), + .Y(booth_b26_m11) + ); + AO22x1_ASAP7_75t_R \U$1491 ( + .A1(b_registered[11]), + .A2(\sel_0$1809 ), + .B1(b_registered[12]), + .B2(\sel_1$1810 ), + .Y(\t$2429 ) + ); + XOR2x1_ASAP7_75t_R \U$1492 ( + .A(\t$2429 ), + .B(a_registered[27]), + .Y(booth_b26_m12) + ); + AO22x1_ASAP7_75t_R \U$1493 ( + .A1(b_registered[12]), + .A2(\sel_0$1809 ), + .B1(b_registered[13]), + .B2(\sel_1$1810 ), + .Y(\t$2430 ) + ); + XOR2x1_ASAP7_75t_R \U$1494 ( + .A(\t$2430 ), + .B(a_registered[27]), + .Y(booth_b26_m13) + ); + AO22x1_ASAP7_75t_R \U$1495 ( + .A1(b_registered[13]), + .A2(\sel_0$1809 ), + .B1(b_registered[14]), + .B2(\sel_1$1810 ), + .Y(\t$2431 ) + ); + XOR2x1_ASAP7_75t_R \U$1496 ( + .A(\t$2431 ), + .B(a_registered[27]), + .Y(booth_b26_m14) + ); + AO22x1_ASAP7_75t_R \U$1497 ( + .A1(b_registered[14]), + .A2(\sel_0$1809 ), + .B1(b_registered[15]), + .B2(\sel_1$1810 ), + .Y(\t$2432 ) + ); + XOR2x1_ASAP7_75t_R \U$1498 ( + .A(\t$2432 ), + .B(a_registered[27]), + .Y(booth_b26_m15) + ); + AO22x1_ASAP7_75t_R \U$1499 ( + .A1(b_registered[15]), + .A2(\sel_0$1809 ), + .B1(b_registered[16]), + .B2(\sel_1$1810 ), + .Y(\t$2433 ) + ); + XOR2x1_ASAP7_75t_R \U$1500 ( + .A(\t$2433 ), + .B(a_registered[27]), + .Y(booth_b26_m16) + ); + AO22x1_ASAP7_75t_R \U$1501 ( + .A1(b_registered[16]), + .A2(\sel_0$1809 ), + .B1(b_registered[17]), + .B2(\sel_1$1810 ), + .Y(\t$2434 ) + ); + XOR2x1_ASAP7_75t_R \U$1502 ( + .A(\t$2434 ), + .B(a_registered[27]), + .Y(booth_b26_m17) + ); + AO22x1_ASAP7_75t_R \U$1503 ( + .A1(b_registered[17]), + .A2(\sel_0$1809 ), + .B1(b_registered[18]), + .B2(\sel_1$1810 ), + .Y(\t$2435 ) + ); + XOR2x1_ASAP7_75t_R \U$1504 ( + .A(\t$2435 ), + .B(a_registered[27]), + .Y(booth_b26_m18) + ); + AO22x1_ASAP7_75t_R \U$1505 ( + .A1(b_registered[18]), + .A2(\sel_0$1809 ), + .B1(b_registered[19]), + .B2(\sel_1$1810 ), + .Y(\t$2436 ) + ); + XOR2x1_ASAP7_75t_R \U$1506 ( + .A(\t$2436 ), + .B(a_registered[27]), + .Y(booth_b26_m19) + ); + AO22x1_ASAP7_75t_R \U$1507 ( + .A1(b_registered[19]), + .A2(\sel_0$1809 ), + .B1(b_registered[20]), + .B2(\sel_1$1810 ), + .Y(\t$2437 ) + ); + XOR2x1_ASAP7_75t_R \U$1508 ( + .A(\t$2437 ), + .B(a_registered[27]), + .Y(booth_b26_m20) + ); + AO22x1_ASAP7_75t_R \U$1509 ( + .A1(b_registered[20]), + .A2(\sel_0$1809 ), + .B1(b_registered[21]), + .B2(\sel_1$1810 ), + .Y(\t$2438 ) + ); + XOR2x1_ASAP7_75t_R \U$1510 ( + .A(\t$2438 ), + .B(a_registered[27]), + .Y(booth_b26_m21) + ); + AO22x1_ASAP7_75t_R \U$1511 ( + .A1(b_registered[21]), + .A2(\sel_0$1809 ), + .B1(b_registered[22]), + .B2(\sel_1$1810 ), + .Y(\t$2439 ) + ); + XOR2x1_ASAP7_75t_R \U$1512 ( + .A(\t$2439 ), + .B(a_registered[27]), + .Y(booth_b26_m22) + ); + AO22x1_ASAP7_75t_R \U$1513 ( + .A1(b_registered[22]), + .A2(\sel_0$1809 ), + .B1(b_registered[23]), + .B2(\sel_1$1810 ), + .Y(\t$2440 ) + ); + XOR2x1_ASAP7_75t_R \U$1514 ( + .A(\t$2440 ), + .B(a_registered[27]), + .Y(booth_b26_m23) + ); + AO22x1_ASAP7_75t_R \U$1515 ( + .A1(b_registered[23]), + .A2(\sel_0$1809 ), + .B1(b_registered[24]), + .B2(\sel_1$1810 ), + .Y(\t$2441 ) + ); + XOR2x1_ASAP7_75t_R \U$1516 ( + .A(\t$2441 ), + .B(a_registered[27]), + .Y(booth_b26_m24) + ); + AO22x1_ASAP7_75t_R \U$1517 ( + .A1(b_registered[24]), + .A2(\sel_0$1809 ), + .B1(b_registered[25]), + .B2(\sel_1$1810 ), + .Y(\t$2442 ) + ); + XOR2x1_ASAP7_75t_R \U$1518 ( + .A(\t$2442 ), + .B(a_registered[27]), + .Y(booth_b26_m25) + ); + AO22x1_ASAP7_75t_R \U$1519 ( + .A1(b_registered[25]), + .A2(\sel_0$1809 ), + .B1(b_registered[26]), + .B2(\sel_1$1810 ), + .Y(\t$2443 ) + ); + XOR2x1_ASAP7_75t_R \U$1520 ( + .A(\t$2443 ), + .B(a_registered[27]), + .Y(booth_b26_m26) + ); + AO22x1_ASAP7_75t_R \U$1521 ( + .A1(b_registered[26]), + .A2(\sel_0$1809 ), + .B1(b_registered[27]), + .B2(\sel_1$1810 ), + .Y(\t$2444 ) + ); + XOR2x1_ASAP7_75t_R \U$1522 ( + .A(\t$2444 ), + .B(a_registered[27]), + .Y(booth_b26_m27) + ); + AO22x1_ASAP7_75t_R \U$1523 ( + .A1(b_registered[27]), + .A2(\sel_0$1809 ), + .B1(b_registered[28]), + .B2(\sel_1$1810 ), + .Y(\t$2445 ) + ); + XOR2x1_ASAP7_75t_R \U$1524 ( + .A(\t$2445 ), + .B(a_registered[27]), + .Y(booth_b26_m28) + ); + AO22x1_ASAP7_75t_R \U$1525 ( + .A1(b_registered[28]), + .A2(\sel_0$1809 ), + .B1(b_registered[29]), + .B2(\sel_1$1810 ), + .Y(\t$2446 ) + ); + XOR2x1_ASAP7_75t_R \U$1526 ( + .A(\t$2446 ), + .B(a_registered[27]), + .Y(booth_b26_m29) + ); + AO22x1_ASAP7_75t_R \U$1527 ( + .A1(b_registered[29]), + .A2(\sel_0$1809 ), + .B1(b_registered[30]), + .B2(\sel_1$1810 ), + .Y(\t$2447 ) + ); + XOR2x1_ASAP7_75t_R \U$1528 ( + .A(\t$2447 ), + .B(a_registered[27]), + .Y(booth_b26_m30) + ); + AO22x1_ASAP7_75t_R \U$1529 ( + .A1(b_registered[30]), + .A2(\sel_0$1809 ), + .B1(b_registered[31]), + .B2(\sel_1$1810 ), + .Y(\t$2448 ) + ); + XOR2x1_ASAP7_75t_R \U$1530 ( + .A(\t$2448 ), + .B(a_registered[27]), + .Y(booth_b26_m31) + ); + AO22x1_ASAP7_75t_R \U$1531 ( + .A1(b_registered[31]), + .A2(\sel_0$1809 ), + .B1(1'h0), + .B2(\sel_1$1810 ), + .Y(\t$2449 ) + ); + XOR2x1_ASAP7_75t_R \U$1532 ( + .A(\t$2449 ), + .B(a_registered[27]), + .Y(booth_b26_m32) + ); + INVx1_ASAP7_75t_R \U$1533 ( + .A(a_registered[27]), + .Y(\notsign$1166 ) + ); + INVx1_ASAP7_75t_R \U$1534 ( + .A(a_registered[27]), + .Y(\$43 ) + ); + INVx1_ASAP7_75t_R \U$1535 ( + .A(a_registered[28]), + .Y(\$44 ) + ); + INVx1_ASAP7_75t_R \U$1536 ( + .A(a_registered[29]), + .Y(\$45 ) + ); + AO33x2_ASAP7_75t_R \U$1537 ( + .A1(\$45 ), + .A2(a_registered[28]), + .A3(a_registered[27]), + .B1(a_registered[29]), + .B2(\$44 ), + .B3(\$43 ), + .Y(\sel_0$1846 ) + ); + XOR2x1_ASAP7_75t_R \U$1538 ( + .A(a_registered[28]), + .B(a_registered[27]), + .Y(\sel_1$1847 ) + ); + AO22x1_ASAP7_75t_R \U$1539 ( + .A1(1'h0), + .A2(\sel_0$1846 ), + .B1(b_registered[0]), + .B2(\sel_1$1847 ), + .Y(\t$2451 ) + ); + XOR2x1_ASAP7_75t_R \U$1540 ( + .A(\t$2451 ), + .B(a_registered[29]), + .Y(booth_b28_m0) + ); + AO22x1_ASAP7_75t_R \U$1541 ( + .A1(b_registered[0]), + .A2(\sel_0$1846 ), + .B1(b_registered[1]), + .B2(\sel_1$1847 ), + .Y(\t$2452 ) + ); + XOR2x1_ASAP7_75t_R \U$1542 ( + .A(\t$2452 ), + .B(a_registered[29]), + .Y(booth_b28_m1) + ); + AO22x1_ASAP7_75t_R \U$1543 ( + .A1(b_registered[1]), + .A2(\sel_0$1846 ), + .B1(b_registered[2]), + .B2(\sel_1$1847 ), + .Y(\t$2453 ) + ); + XOR2x1_ASAP7_75t_R \U$1544 ( + .A(\t$2453 ), + .B(a_registered[29]), + .Y(booth_b28_m2) + ); + AO22x1_ASAP7_75t_R \U$1545 ( + .A1(b_registered[2]), + .A2(\sel_0$1846 ), + .B1(b_registered[3]), + .B2(\sel_1$1847 ), + .Y(\t$2454 ) + ); + XOR2x1_ASAP7_75t_R \U$1546 ( + .A(\t$2454 ), + .B(a_registered[29]), + .Y(booth_b28_m3) + ); + AO22x1_ASAP7_75t_R \U$1547 ( + .A1(b_registered[3]), + .A2(\sel_0$1846 ), + .B1(b_registered[4]), + .B2(\sel_1$1847 ), + .Y(\t$2455 ) + ); + XOR2x1_ASAP7_75t_R \U$1548 ( + .A(\t$2455 ), + .B(a_registered[29]), + .Y(booth_b28_m4) + ); + AO22x1_ASAP7_75t_R \U$1549 ( + .A1(b_registered[4]), + .A2(\sel_0$1846 ), + .B1(b_registered[5]), + .B2(\sel_1$1847 ), + .Y(\t$2456 ) + ); + XOR2x1_ASAP7_75t_R \U$1550 ( + .A(\t$2456 ), + .B(a_registered[29]), + .Y(booth_b28_m5) + ); + AO22x1_ASAP7_75t_R \U$1551 ( + .A1(b_registered[5]), + .A2(\sel_0$1846 ), + .B1(b_registered[6]), + .B2(\sel_1$1847 ), + .Y(\t$2457 ) + ); + XOR2x1_ASAP7_75t_R \U$1552 ( + .A(\t$2457 ), + .B(a_registered[29]), + .Y(booth_b28_m6) + ); + AO22x1_ASAP7_75t_R \U$1553 ( + .A1(b_registered[6]), + .A2(\sel_0$1846 ), + .B1(b_registered[7]), + .B2(\sel_1$1847 ), + .Y(\t$2458 ) + ); + XOR2x1_ASAP7_75t_R \U$1554 ( + .A(\t$2458 ), + .B(a_registered[29]), + .Y(booth_b28_m7) + ); + AO22x1_ASAP7_75t_R \U$1555 ( + .A1(b_registered[7]), + .A2(\sel_0$1846 ), + .B1(b_registered[8]), + .B2(\sel_1$1847 ), + .Y(\t$2459 ) + ); + XOR2x1_ASAP7_75t_R \U$1556 ( + .A(\t$2459 ), + .B(a_registered[29]), + .Y(booth_b28_m8) + ); + AO22x1_ASAP7_75t_R \U$1557 ( + .A1(b_registered[8]), + .A2(\sel_0$1846 ), + .B1(b_registered[9]), + .B2(\sel_1$1847 ), + .Y(\t$2460 ) + ); + XOR2x1_ASAP7_75t_R \U$1558 ( + .A(\t$2460 ), + .B(a_registered[29]), + .Y(booth_b28_m9) + ); + AO22x1_ASAP7_75t_R \U$1559 ( + .A1(b_registered[9]), + .A2(\sel_0$1846 ), + .B1(b_registered[10]), + .B2(\sel_1$1847 ), + .Y(\t$2461 ) + ); + XOR2x1_ASAP7_75t_R \U$1560 ( + .A(\t$2461 ), + .B(a_registered[29]), + .Y(booth_b28_m10) + ); + AO22x1_ASAP7_75t_R \U$1561 ( + .A1(b_registered[10]), + .A2(\sel_0$1846 ), + .B1(b_registered[11]), + .B2(\sel_1$1847 ), + .Y(\t$2462 ) + ); + XOR2x1_ASAP7_75t_R \U$1562 ( + .A(\t$2462 ), + .B(a_registered[29]), + .Y(booth_b28_m11) + ); + AO22x1_ASAP7_75t_R \U$1563 ( + .A1(b_registered[11]), + .A2(\sel_0$1846 ), + .B1(b_registered[12]), + .B2(\sel_1$1847 ), + .Y(\t$2463 ) + ); + XOR2x1_ASAP7_75t_R \U$1564 ( + .A(\t$2463 ), + .B(a_registered[29]), + .Y(booth_b28_m12) + ); + AO22x1_ASAP7_75t_R \U$1565 ( + .A1(b_registered[12]), + .A2(\sel_0$1846 ), + .B1(b_registered[13]), + .B2(\sel_1$1847 ), + .Y(\t$2464 ) + ); + XOR2x1_ASAP7_75t_R \U$1566 ( + .A(\t$2464 ), + .B(a_registered[29]), + .Y(booth_b28_m13) + ); + AO22x1_ASAP7_75t_R \U$1567 ( + .A1(b_registered[13]), + .A2(\sel_0$1846 ), + .B1(b_registered[14]), + .B2(\sel_1$1847 ), + .Y(\t$2465 ) + ); + XOR2x1_ASAP7_75t_R \U$1568 ( + .A(\t$2465 ), + .B(a_registered[29]), + .Y(booth_b28_m14) + ); + AO22x1_ASAP7_75t_R \U$1569 ( + .A1(b_registered[14]), + .A2(\sel_0$1846 ), + .B1(b_registered[15]), + .B2(\sel_1$1847 ), + .Y(\t$2466 ) + ); + XOR2x1_ASAP7_75t_R \U$1570 ( + .A(\t$2466 ), + .B(a_registered[29]), + .Y(booth_b28_m15) + ); + AO22x1_ASAP7_75t_R \U$1571 ( + .A1(b_registered[15]), + .A2(\sel_0$1846 ), + .B1(b_registered[16]), + .B2(\sel_1$1847 ), + .Y(\t$2467 ) + ); + XOR2x1_ASAP7_75t_R \U$1572 ( + .A(\t$2467 ), + .B(a_registered[29]), + .Y(booth_b28_m16) + ); + AO22x1_ASAP7_75t_R \U$1573 ( + .A1(b_registered[16]), + .A2(\sel_0$1846 ), + .B1(b_registered[17]), + .B2(\sel_1$1847 ), + .Y(\t$2468 ) + ); + XOR2x1_ASAP7_75t_R \U$1574 ( + .A(\t$2468 ), + .B(a_registered[29]), + .Y(booth_b28_m17) + ); + AO22x1_ASAP7_75t_R \U$1575 ( + .A1(b_registered[17]), + .A2(\sel_0$1846 ), + .B1(b_registered[18]), + .B2(\sel_1$1847 ), + .Y(\t$2469 ) + ); + XOR2x1_ASAP7_75t_R \U$1576 ( + .A(\t$2469 ), + .B(a_registered[29]), + .Y(booth_b28_m18) + ); + AO22x1_ASAP7_75t_R \U$1577 ( + .A1(b_registered[18]), + .A2(\sel_0$1846 ), + .B1(b_registered[19]), + .B2(\sel_1$1847 ), + .Y(\t$2470 ) + ); + XOR2x1_ASAP7_75t_R \U$1578 ( + .A(\t$2470 ), + .B(a_registered[29]), + .Y(booth_b28_m19) + ); + AO22x1_ASAP7_75t_R \U$1579 ( + .A1(b_registered[19]), + .A2(\sel_0$1846 ), + .B1(b_registered[20]), + .B2(\sel_1$1847 ), + .Y(\t$2471 ) + ); + XOR2x1_ASAP7_75t_R \U$1580 ( + .A(\t$2471 ), + .B(a_registered[29]), + .Y(booth_b28_m20) + ); + AO22x1_ASAP7_75t_R \U$1581 ( + .A1(b_registered[20]), + .A2(\sel_0$1846 ), + .B1(b_registered[21]), + .B2(\sel_1$1847 ), + .Y(\t$2472 ) + ); + XOR2x1_ASAP7_75t_R \U$1582 ( + .A(\t$2472 ), + .B(a_registered[29]), + .Y(booth_b28_m21) + ); + AO22x1_ASAP7_75t_R \U$1583 ( + .A1(b_registered[21]), + .A2(\sel_0$1846 ), + .B1(b_registered[22]), + .B2(\sel_1$1847 ), + .Y(\t$2473 ) + ); + XOR2x1_ASAP7_75t_R \U$1584 ( + .A(\t$2473 ), + .B(a_registered[29]), + .Y(booth_b28_m22) + ); + AO22x1_ASAP7_75t_R \U$1585 ( + .A1(b_registered[22]), + .A2(\sel_0$1846 ), + .B1(b_registered[23]), + .B2(\sel_1$1847 ), + .Y(\t$2474 ) + ); + XOR2x1_ASAP7_75t_R \U$1586 ( + .A(\t$2474 ), + .B(a_registered[29]), + .Y(booth_b28_m23) + ); + AO22x1_ASAP7_75t_R \U$1587 ( + .A1(b_registered[23]), + .A2(\sel_0$1846 ), + .B1(b_registered[24]), + .B2(\sel_1$1847 ), + .Y(\t$2475 ) + ); + XOR2x1_ASAP7_75t_R \U$1588 ( + .A(\t$2475 ), + .B(a_registered[29]), + .Y(booth_b28_m24) + ); + AO22x1_ASAP7_75t_R \U$1589 ( + .A1(b_registered[24]), + .A2(\sel_0$1846 ), + .B1(b_registered[25]), + .B2(\sel_1$1847 ), + .Y(\t$2476 ) + ); + XOR2x1_ASAP7_75t_R \U$1590 ( + .A(\t$2476 ), + .B(a_registered[29]), + .Y(booth_b28_m25) + ); + AO22x1_ASAP7_75t_R \U$1591 ( + .A1(b_registered[25]), + .A2(\sel_0$1846 ), + .B1(b_registered[26]), + .B2(\sel_1$1847 ), + .Y(\t$2477 ) + ); + XOR2x1_ASAP7_75t_R \U$1592 ( + .A(\t$2477 ), + .B(a_registered[29]), + .Y(booth_b28_m26) + ); + AO22x1_ASAP7_75t_R \U$1593 ( + .A1(b_registered[26]), + .A2(\sel_0$1846 ), + .B1(b_registered[27]), + .B2(\sel_1$1847 ), + .Y(\t$2478 ) + ); + XOR2x1_ASAP7_75t_R \U$1594 ( + .A(\t$2478 ), + .B(a_registered[29]), + .Y(booth_b28_m27) + ); + AO22x1_ASAP7_75t_R \U$1595 ( + .A1(b_registered[27]), + .A2(\sel_0$1846 ), + .B1(b_registered[28]), + .B2(\sel_1$1847 ), + .Y(\t$2479 ) + ); + XOR2x1_ASAP7_75t_R \U$1596 ( + .A(\t$2479 ), + .B(a_registered[29]), + .Y(booth_b28_m28) + ); + AO22x1_ASAP7_75t_R \U$1597 ( + .A1(b_registered[28]), + .A2(\sel_0$1846 ), + .B1(b_registered[29]), + .B2(\sel_1$1847 ), + .Y(\t$2480 ) + ); + XOR2x1_ASAP7_75t_R \U$1598 ( + .A(\t$2480 ), + .B(a_registered[29]), + .Y(booth_b28_m29) + ); + AO22x1_ASAP7_75t_R \U$1599 ( + .A1(b_registered[29]), + .A2(\sel_0$1846 ), + .B1(b_registered[30]), + .B2(\sel_1$1847 ), + .Y(\t$2481 ) + ); + XOR2x1_ASAP7_75t_R \U$1600 ( + .A(\t$2481 ), + .B(a_registered[29]), + .Y(booth_b28_m30) + ); + AO22x1_ASAP7_75t_R \U$1601 ( + .A1(b_registered[30]), + .A2(\sel_0$1846 ), + .B1(b_registered[31]), + .B2(\sel_1$1847 ), + .Y(\t$2482 ) + ); + XOR2x1_ASAP7_75t_R \U$1602 ( + .A(\t$2482 ), + .B(a_registered[29]), + .Y(booth_b28_m31) + ); + AO22x1_ASAP7_75t_R \U$1603 ( + .A1(b_registered[31]), + .A2(\sel_0$1846 ), + .B1(1'h0), + .B2(\sel_1$1847 ), + .Y(\t$2483 ) + ); + XOR2x1_ASAP7_75t_R \U$1604 ( + .A(\t$2483 ), + .B(a_registered[29]), + .Y(booth_b28_m32) + ); + INVx1_ASAP7_75t_R \U$1605 ( + .A(a_registered[29]), + .Y(\notsign$1180 ) + ); + INVx1_ASAP7_75t_R \U$1606 ( + .A(a_registered[29]), + .Y(\$46 ) + ); + INVx1_ASAP7_75t_R \U$1607 ( + .A(a_registered[30]), + .Y(\$47 ) + ); + INVx1_ASAP7_75t_R \U$1608 ( + .A(a_registered[31]), + .Y(\$48 ) + ); + AO33x2_ASAP7_75t_R \U$1609 ( + .A1(\$48 ), + .A2(a_registered[30]), + .A3(a_registered[29]), + .B1(a_registered[31]), + .B2(\$47 ), + .B3(\$46 ), + .Y(\sel_0$1883 ) + ); + XOR2x1_ASAP7_75t_R \U$1610 ( + .A(a_registered[30]), + .B(a_registered[29]), + .Y(\sel_1$1884 ) + ); + AO22x1_ASAP7_75t_R \U$1611 ( + .A1(1'h0), + .A2(\sel_0$1883 ), + .B1(b_registered[0]), + .B2(\sel_1$1884 ), + .Y(\t$2485 ) + ); + XOR2x1_ASAP7_75t_R \U$1612 ( + .A(\t$2485 ), + .B(a_registered[31]), + .Y(booth_b30_m0) + ); + AO22x1_ASAP7_75t_R \U$1613 ( + .A1(b_registered[0]), + .A2(\sel_0$1883 ), + .B1(b_registered[1]), + .B2(\sel_1$1884 ), + .Y(\t$2486 ) + ); + XOR2x1_ASAP7_75t_R \U$1614 ( + .A(\t$2486 ), + .B(a_registered[31]), + .Y(booth_b30_m1) + ); + AO22x1_ASAP7_75t_R \U$1615 ( + .A1(b_registered[1]), + .A2(\sel_0$1883 ), + .B1(b_registered[2]), + .B2(\sel_1$1884 ), + .Y(\t$2487 ) + ); + XOR2x1_ASAP7_75t_R \U$1616 ( + .A(\t$2487 ), + .B(a_registered[31]), + .Y(booth_b30_m2) + ); + AO22x1_ASAP7_75t_R \U$1617 ( + .A1(b_registered[2]), + .A2(\sel_0$1883 ), + .B1(b_registered[3]), + .B2(\sel_1$1884 ), + .Y(\t$2488 ) + ); + XOR2x1_ASAP7_75t_R \U$1618 ( + .A(\t$2488 ), + .B(a_registered[31]), + .Y(booth_b30_m3) + ); + AO22x1_ASAP7_75t_R \U$1619 ( + .A1(b_registered[3]), + .A2(\sel_0$1883 ), + .B1(b_registered[4]), + .B2(\sel_1$1884 ), + .Y(\t$2489 ) + ); + XOR2x1_ASAP7_75t_R \U$1620 ( + .A(\t$2489 ), + .B(a_registered[31]), + .Y(booth_b30_m4) + ); + AO22x1_ASAP7_75t_R \U$1621 ( + .A1(b_registered[4]), + .A2(\sel_0$1883 ), + .B1(b_registered[5]), + .B2(\sel_1$1884 ), + .Y(\t$2490 ) + ); + XOR2x1_ASAP7_75t_R \U$1622 ( + .A(\t$2490 ), + .B(a_registered[31]), + .Y(booth_b30_m5) + ); + AO22x1_ASAP7_75t_R \U$1623 ( + .A1(b_registered[5]), + .A2(\sel_0$1883 ), + .B1(b_registered[6]), + .B2(\sel_1$1884 ), + .Y(\t$2491 ) + ); + XOR2x1_ASAP7_75t_R \U$1624 ( + .A(\t$2491 ), + .B(a_registered[31]), + .Y(booth_b30_m6) + ); + AO22x1_ASAP7_75t_R \U$1625 ( + .A1(b_registered[6]), + .A2(\sel_0$1883 ), + .B1(b_registered[7]), + .B2(\sel_1$1884 ), + .Y(\t$2492 ) + ); + XOR2x1_ASAP7_75t_R \U$1626 ( + .A(\t$2492 ), + .B(a_registered[31]), + .Y(booth_b30_m7) + ); + AO22x1_ASAP7_75t_R \U$1627 ( + .A1(b_registered[7]), + .A2(\sel_0$1883 ), + .B1(b_registered[8]), + .B2(\sel_1$1884 ), + .Y(\t$2493 ) + ); + XOR2x1_ASAP7_75t_R \U$1628 ( + .A(\t$2493 ), + .B(a_registered[31]), + .Y(booth_b30_m8) + ); + AO22x1_ASAP7_75t_R \U$1629 ( + .A1(b_registered[8]), + .A2(\sel_0$1883 ), + .B1(b_registered[9]), + .B2(\sel_1$1884 ), + .Y(\t$2494 ) + ); + XOR2x1_ASAP7_75t_R \U$1630 ( + .A(\t$2494 ), + .B(a_registered[31]), + .Y(booth_b30_m9) + ); + AO22x1_ASAP7_75t_R \U$1631 ( + .A1(b_registered[9]), + .A2(\sel_0$1883 ), + .B1(b_registered[10]), + .B2(\sel_1$1884 ), + .Y(\t$2495 ) + ); + XOR2x1_ASAP7_75t_R \U$1632 ( + .A(\t$2495 ), + .B(a_registered[31]), + .Y(booth_b30_m10) + ); + AO22x1_ASAP7_75t_R \U$1633 ( + .A1(b_registered[10]), + .A2(\sel_0$1883 ), + .B1(b_registered[11]), + .B2(\sel_1$1884 ), + .Y(\t$2496 ) + ); + XOR2x1_ASAP7_75t_R \U$1634 ( + .A(\t$2496 ), + .B(a_registered[31]), + .Y(booth_b30_m11) + ); + AO22x1_ASAP7_75t_R \U$1635 ( + .A1(b_registered[11]), + .A2(\sel_0$1883 ), + .B1(b_registered[12]), + .B2(\sel_1$1884 ), + .Y(\t$2497 ) + ); + XOR2x1_ASAP7_75t_R \U$1636 ( + .A(\t$2497 ), + .B(a_registered[31]), + .Y(booth_b30_m12) + ); + AO22x1_ASAP7_75t_R \U$1637 ( + .A1(b_registered[12]), + .A2(\sel_0$1883 ), + .B1(b_registered[13]), + .B2(\sel_1$1884 ), + .Y(\t$2498 ) + ); + XOR2x1_ASAP7_75t_R \U$1638 ( + .A(\t$2498 ), + .B(a_registered[31]), + .Y(booth_b30_m13) + ); + AO22x1_ASAP7_75t_R \U$1639 ( + .A1(b_registered[13]), + .A2(\sel_0$1883 ), + .B1(b_registered[14]), + .B2(\sel_1$1884 ), + .Y(\t$2499 ) + ); + XOR2x1_ASAP7_75t_R \U$1640 ( + .A(\t$2499 ), + .B(a_registered[31]), + .Y(booth_b30_m14) + ); + AO22x1_ASAP7_75t_R \U$1641 ( + .A1(b_registered[14]), + .A2(\sel_0$1883 ), + .B1(b_registered[15]), + .B2(\sel_1$1884 ), + .Y(\t$2500 ) + ); + XOR2x1_ASAP7_75t_R \U$1642 ( + .A(\t$2500 ), + .B(a_registered[31]), + .Y(booth_b30_m15) + ); + AO22x1_ASAP7_75t_R \U$1643 ( + .A1(b_registered[15]), + .A2(\sel_0$1883 ), + .B1(b_registered[16]), + .B2(\sel_1$1884 ), + .Y(\t$2501 ) + ); + XOR2x1_ASAP7_75t_R \U$1644 ( + .A(\t$2501 ), + .B(a_registered[31]), + .Y(booth_b30_m16) + ); + AO22x1_ASAP7_75t_R \U$1645 ( + .A1(b_registered[16]), + .A2(\sel_0$1883 ), + .B1(b_registered[17]), + .B2(\sel_1$1884 ), + .Y(\t$2502 ) + ); + XOR2x1_ASAP7_75t_R \U$1646 ( + .A(\t$2502 ), + .B(a_registered[31]), + .Y(booth_b30_m17) + ); + AO22x1_ASAP7_75t_R \U$1647 ( + .A1(b_registered[17]), + .A2(\sel_0$1883 ), + .B1(b_registered[18]), + .B2(\sel_1$1884 ), + .Y(\t$2503 ) + ); + XOR2x1_ASAP7_75t_R \U$1648 ( + .A(\t$2503 ), + .B(a_registered[31]), + .Y(booth_b30_m18) + ); + AO22x1_ASAP7_75t_R \U$1649 ( + .A1(b_registered[18]), + .A2(\sel_0$1883 ), + .B1(b_registered[19]), + .B2(\sel_1$1884 ), + .Y(\t$2504 ) + ); + XOR2x1_ASAP7_75t_R \U$1650 ( + .A(\t$2504 ), + .B(a_registered[31]), + .Y(booth_b30_m19) + ); + AO22x1_ASAP7_75t_R \U$1651 ( + .A1(b_registered[19]), + .A2(\sel_0$1883 ), + .B1(b_registered[20]), + .B2(\sel_1$1884 ), + .Y(\t$2505 ) + ); + XOR2x1_ASAP7_75t_R \U$1652 ( + .A(\t$2505 ), + .B(a_registered[31]), + .Y(booth_b30_m20) + ); + AO22x1_ASAP7_75t_R \U$1653 ( + .A1(b_registered[20]), + .A2(\sel_0$1883 ), + .B1(b_registered[21]), + .B2(\sel_1$1884 ), + .Y(\t$2506 ) + ); + XOR2x1_ASAP7_75t_R \U$1654 ( + .A(\t$2506 ), + .B(a_registered[31]), + .Y(booth_b30_m21) + ); + AO22x1_ASAP7_75t_R \U$1655 ( + .A1(b_registered[21]), + .A2(\sel_0$1883 ), + .B1(b_registered[22]), + .B2(\sel_1$1884 ), + .Y(\t$2507 ) + ); + XOR2x1_ASAP7_75t_R \U$1656 ( + .A(\t$2507 ), + .B(a_registered[31]), + .Y(booth_b30_m22) + ); + AO22x1_ASAP7_75t_R \U$1657 ( + .A1(b_registered[22]), + .A2(\sel_0$1883 ), + .B1(b_registered[23]), + .B2(\sel_1$1884 ), + .Y(\t$2508 ) + ); + XOR2x1_ASAP7_75t_R \U$1658 ( + .A(\t$2508 ), + .B(a_registered[31]), + .Y(booth_b30_m23) + ); + AO22x1_ASAP7_75t_R \U$1659 ( + .A1(b_registered[23]), + .A2(\sel_0$1883 ), + .B1(b_registered[24]), + .B2(\sel_1$1884 ), + .Y(\t$2509 ) + ); + XOR2x1_ASAP7_75t_R \U$1660 ( + .A(\t$2509 ), + .B(a_registered[31]), + .Y(booth_b30_m24) + ); + AO22x1_ASAP7_75t_R \U$1661 ( + .A1(b_registered[24]), + .A2(\sel_0$1883 ), + .B1(b_registered[25]), + .B2(\sel_1$1884 ), + .Y(\t$2510 ) + ); + XOR2x1_ASAP7_75t_R \U$1662 ( + .A(\t$2510 ), + .B(a_registered[31]), + .Y(booth_b30_m25) + ); + AO22x1_ASAP7_75t_R \U$1663 ( + .A1(b_registered[25]), + .A2(\sel_0$1883 ), + .B1(b_registered[26]), + .B2(\sel_1$1884 ), + .Y(\t$2511 ) + ); + XOR2x1_ASAP7_75t_R \U$1664 ( + .A(\t$2511 ), + .B(a_registered[31]), + .Y(booth_b30_m26) + ); + AO22x1_ASAP7_75t_R \U$1665 ( + .A1(b_registered[26]), + .A2(\sel_0$1883 ), + .B1(b_registered[27]), + .B2(\sel_1$1884 ), + .Y(\t$2512 ) + ); + XOR2x1_ASAP7_75t_R \U$1666 ( + .A(\t$2512 ), + .B(a_registered[31]), + .Y(booth_b30_m27) + ); + AO22x1_ASAP7_75t_R \U$1667 ( + .A1(b_registered[27]), + .A2(\sel_0$1883 ), + .B1(b_registered[28]), + .B2(\sel_1$1884 ), + .Y(\t$2513 ) + ); + XOR2x1_ASAP7_75t_R \U$1668 ( + .A(\t$2513 ), + .B(a_registered[31]), + .Y(booth_b30_m28) + ); + AO22x1_ASAP7_75t_R \U$1669 ( + .A1(b_registered[28]), + .A2(\sel_0$1883 ), + .B1(b_registered[29]), + .B2(\sel_1$1884 ), + .Y(\t$2514 ) + ); + XOR2x1_ASAP7_75t_R \U$1670 ( + .A(\t$2514 ), + .B(a_registered[31]), + .Y(booth_b30_m29) + ); + AO22x1_ASAP7_75t_R \U$1671 ( + .A1(b_registered[29]), + .A2(\sel_0$1883 ), + .B1(b_registered[30]), + .B2(\sel_1$1884 ), + .Y(\t$2515 ) + ); + XOR2x1_ASAP7_75t_R \U$1672 ( + .A(\t$2515 ), + .B(a_registered[31]), + .Y(booth_b30_m30) + ); + AO22x1_ASAP7_75t_R \U$1673 ( + .A1(b_registered[30]), + .A2(\sel_0$1883 ), + .B1(b_registered[31]), + .B2(\sel_1$1884 ), + .Y(\t$2516 ) + ); + XOR2x1_ASAP7_75t_R \U$1674 ( + .A(\t$2516 ), + .B(a_registered[31]), + .Y(booth_b30_m31) + ); + AO22x1_ASAP7_75t_R \U$1675 ( + .A1(b_registered[31]), + .A2(\sel_0$1883 ), + .B1(1'h0), + .B2(\sel_1$1884 ), + .Y(\t$2517 ) + ); + XOR2x1_ASAP7_75t_R \U$1676 ( + .A(\t$2517 ), + .B(a_registered[31]), + .Y(booth_b30_m32) + ); + INVx1_ASAP7_75t_R \U$1677 ( + .A(a_registered[31]), + .Y(\notsign$1190 ) + ); + INVx1_ASAP7_75t_R \U$1678 ( + .A(a_registered[31]), + .Y(\$49 ) + ); + INVx1_ASAP7_75t_R \U$1679 ( + .A(1'h0), + .Y(\$50 ) + ); + INVx1_ASAP7_75t_R \U$1680 ( + .A(1'h0), + .Y(\$51 ) + ); + AO33x2_ASAP7_75t_R \U$1681 ( + .A1(\$51 ), + .A2(1'h0), + .A3(a_registered[31]), + .B1(1'h0), + .B2(\$50 ), + .B3(\$49 ), + .Y(\sel_0$1921 ) + ); + XOR2x1_ASAP7_75t_R \U$1682 ( + .A(1'h0), + .B(a_registered[31]), + .Y(\sel_1$1922 ) + ); + AO22x1_ASAP7_75t_R \U$1683 ( + .A1(1'h0), + .A2(\sel_0$1921 ), + .B1(b_registered[0]), + .B2(\sel_1$1922 ), + .Y(\t$2519 ) + ); + XOR2x1_ASAP7_75t_R \U$1684 ( + .A(\t$2519 ), + .B(1'h0), + .Y(booth_b32_m0) + ); + AO22x1_ASAP7_75t_R \U$1685 ( + .A1(b_registered[0]), + .A2(\sel_0$1921 ), + .B1(b_registered[1]), + .B2(\sel_1$1922 ), + .Y(\t$2520 ) + ); + XOR2x1_ASAP7_75t_R \U$1686 ( + .A(\t$2520 ), + .B(1'h0), + .Y(booth_b32_m1) + ); + AO22x1_ASAP7_75t_R \U$1687 ( + .A1(b_registered[1]), + .A2(\sel_0$1921 ), + .B1(b_registered[2]), + .B2(\sel_1$1922 ), + .Y(\t$2521 ) + ); + XOR2x1_ASAP7_75t_R \U$1688 ( + .A(\t$2521 ), + .B(1'h0), + .Y(booth_b32_m2) + ); + AO22x1_ASAP7_75t_R \U$1689 ( + .A1(b_registered[2]), + .A2(\sel_0$1921 ), + .B1(b_registered[3]), + .B2(\sel_1$1922 ), + .Y(\t$2522 ) + ); + XOR2x1_ASAP7_75t_R \U$1690 ( + .A(\t$2522 ), + .B(1'h0), + .Y(booth_b32_m3) + ); + AO22x1_ASAP7_75t_R \U$1691 ( + .A1(b_registered[3]), + .A2(\sel_0$1921 ), + .B1(b_registered[4]), + .B2(\sel_1$1922 ), + .Y(\t$2523 ) + ); + XOR2x1_ASAP7_75t_R \U$1692 ( + .A(\t$2523 ), + .B(1'h0), + .Y(booth_b32_m4) + ); + AO22x1_ASAP7_75t_R \U$1693 ( + .A1(b_registered[4]), + .A2(\sel_0$1921 ), + .B1(b_registered[5]), + .B2(\sel_1$1922 ), + .Y(\t$2524 ) + ); + XOR2x1_ASAP7_75t_R \U$1694 ( + .A(\t$2524 ), + .B(1'h0), + .Y(booth_b32_m5) + ); + AO22x1_ASAP7_75t_R \U$1695 ( + .A1(b_registered[5]), + .A2(\sel_0$1921 ), + .B1(b_registered[6]), + .B2(\sel_1$1922 ), + .Y(\t$2525 ) + ); + XOR2x1_ASAP7_75t_R \U$1696 ( + .A(\t$2525 ), + .B(1'h0), + .Y(booth_b32_m6) + ); + AO22x1_ASAP7_75t_R \U$1697 ( + .A1(b_registered[6]), + .A2(\sel_0$1921 ), + .B1(b_registered[7]), + .B2(\sel_1$1922 ), + .Y(\t$2526 ) + ); + XOR2x1_ASAP7_75t_R \U$1698 ( + .A(\t$2526 ), + .B(1'h0), + .Y(booth_b32_m7) + ); + AO22x1_ASAP7_75t_R \U$1699 ( + .A1(b_registered[7]), + .A2(\sel_0$1921 ), + .B1(b_registered[8]), + .B2(\sel_1$1922 ), + .Y(\t$2527 ) + ); + XOR2x1_ASAP7_75t_R \U$1700 ( + .A(\t$2527 ), + .B(1'h0), + .Y(booth_b32_m8) + ); + AO22x1_ASAP7_75t_R \U$1701 ( + .A1(b_registered[8]), + .A2(\sel_0$1921 ), + .B1(b_registered[9]), + .B2(\sel_1$1922 ), + .Y(\t$2528 ) + ); + XOR2x1_ASAP7_75t_R \U$1702 ( + .A(\t$2528 ), + .B(1'h0), + .Y(booth_b32_m9) + ); + AO22x1_ASAP7_75t_R \U$1703 ( + .A1(b_registered[9]), + .A2(\sel_0$1921 ), + .B1(b_registered[10]), + .B2(\sel_1$1922 ), + .Y(\t$2529 ) + ); + XOR2x1_ASAP7_75t_R \U$1704 ( + .A(\t$2529 ), + .B(1'h0), + .Y(booth_b32_m10) + ); + AO22x1_ASAP7_75t_R \U$1705 ( + .A1(b_registered[10]), + .A2(\sel_0$1921 ), + .B1(b_registered[11]), + .B2(\sel_1$1922 ), + .Y(\t$2530 ) + ); + XOR2x1_ASAP7_75t_R \U$1706 ( + .A(\t$2530 ), + .B(1'h0), + .Y(booth_b32_m11) + ); + AO22x1_ASAP7_75t_R \U$1707 ( + .A1(b_registered[11]), + .A2(\sel_0$1921 ), + .B1(b_registered[12]), + .B2(\sel_1$1922 ), + .Y(\t$2531 ) + ); + XOR2x1_ASAP7_75t_R \U$1708 ( + .A(\t$2531 ), + .B(1'h0), + .Y(booth_b32_m12) + ); + AO22x1_ASAP7_75t_R \U$1709 ( + .A1(b_registered[12]), + .A2(\sel_0$1921 ), + .B1(b_registered[13]), + .B2(\sel_1$1922 ), + .Y(\t$2532 ) + ); + XOR2x1_ASAP7_75t_R \U$1710 ( + .A(\t$2532 ), + .B(1'h0), + .Y(booth_b32_m13) + ); + AO22x1_ASAP7_75t_R \U$1711 ( + .A1(b_registered[13]), + .A2(\sel_0$1921 ), + .B1(b_registered[14]), + .B2(\sel_1$1922 ), + .Y(\t$2533 ) + ); + XOR2x1_ASAP7_75t_R \U$1712 ( + .A(\t$2533 ), + .B(1'h0), + .Y(booth_b32_m14) + ); + AO22x1_ASAP7_75t_R \U$1713 ( + .A1(b_registered[14]), + .A2(\sel_0$1921 ), + .B1(b_registered[15]), + .B2(\sel_1$1922 ), + .Y(\t$2534 ) + ); + XOR2x1_ASAP7_75t_R \U$1714 ( + .A(\t$2534 ), + .B(1'h0), + .Y(booth_b32_m15) + ); + AO22x1_ASAP7_75t_R \U$1715 ( + .A1(b_registered[15]), + .A2(\sel_0$1921 ), + .B1(b_registered[16]), + .B2(\sel_1$1922 ), + .Y(\t$2535 ) + ); + XOR2x1_ASAP7_75t_R \U$1716 ( + .A(\t$2535 ), + .B(1'h0), + .Y(booth_b32_m16) + ); + AO22x1_ASAP7_75t_R \U$1717 ( + .A1(b_registered[16]), + .A2(\sel_0$1921 ), + .B1(b_registered[17]), + .B2(\sel_1$1922 ), + .Y(\t$2536 ) + ); + XOR2x1_ASAP7_75t_R \U$1718 ( + .A(\t$2536 ), + .B(1'h0), + .Y(booth_b32_m17) + ); + AO22x1_ASAP7_75t_R \U$1719 ( + .A1(b_registered[17]), + .A2(\sel_0$1921 ), + .B1(b_registered[18]), + .B2(\sel_1$1922 ), + .Y(\t$2537 ) + ); + XOR2x1_ASAP7_75t_R \U$1720 ( + .A(\t$2537 ), + .B(1'h0), + .Y(booth_b32_m18) + ); + AO22x1_ASAP7_75t_R \U$1721 ( + .A1(b_registered[18]), + .A2(\sel_0$1921 ), + .B1(b_registered[19]), + .B2(\sel_1$1922 ), + .Y(\t$2538 ) + ); + XOR2x1_ASAP7_75t_R \U$1722 ( + .A(\t$2538 ), + .B(1'h0), + .Y(booth_b32_m19) + ); + AO22x1_ASAP7_75t_R \U$1723 ( + .A1(b_registered[19]), + .A2(\sel_0$1921 ), + .B1(b_registered[20]), + .B2(\sel_1$1922 ), + .Y(\t$2539 ) + ); + XOR2x1_ASAP7_75t_R \U$1724 ( + .A(\t$2539 ), + .B(1'h0), + .Y(booth_b32_m20) + ); + AO22x1_ASAP7_75t_R \U$1725 ( + .A1(b_registered[20]), + .A2(\sel_0$1921 ), + .B1(b_registered[21]), + .B2(\sel_1$1922 ), + .Y(\t$2540 ) + ); + XOR2x1_ASAP7_75t_R \U$1726 ( + .A(\t$2540 ), + .B(1'h0), + .Y(booth_b32_m21) + ); + AO22x1_ASAP7_75t_R \U$1727 ( + .A1(b_registered[21]), + .A2(\sel_0$1921 ), + .B1(b_registered[22]), + .B2(\sel_1$1922 ), + .Y(\t$2541 ) + ); + XOR2x1_ASAP7_75t_R \U$1728 ( + .A(\t$2541 ), + .B(1'h0), + .Y(booth_b32_m22) + ); + AO22x1_ASAP7_75t_R \U$1729 ( + .A1(b_registered[22]), + .A2(\sel_0$1921 ), + .B1(b_registered[23]), + .B2(\sel_1$1922 ), + .Y(\t$2542 ) + ); + XOR2x1_ASAP7_75t_R \U$1730 ( + .A(\t$2542 ), + .B(1'h0), + .Y(booth_b32_m23) + ); + AO22x1_ASAP7_75t_R \U$1731 ( + .A1(b_registered[23]), + .A2(\sel_0$1921 ), + .B1(b_registered[24]), + .B2(\sel_1$1922 ), + .Y(\t$2543 ) + ); + XOR2x1_ASAP7_75t_R \U$1732 ( + .A(\t$2543 ), + .B(1'h0), + .Y(booth_b32_m24) + ); + AO22x1_ASAP7_75t_R \U$1733 ( + .A1(b_registered[24]), + .A2(\sel_0$1921 ), + .B1(b_registered[25]), + .B2(\sel_1$1922 ), + .Y(\t$2544 ) + ); + XOR2x1_ASAP7_75t_R \U$1734 ( + .A(\t$2544 ), + .B(1'h0), + .Y(booth_b32_m25) + ); + AO22x1_ASAP7_75t_R \U$1735 ( + .A1(b_registered[25]), + .A2(\sel_0$1921 ), + .B1(b_registered[26]), + .B2(\sel_1$1922 ), + .Y(\t$2545 ) + ); + XOR2x1_ASAP7_75t_R \U$1736 ( + .A(\t$2545 ), + .B(1'h0), + .Y(booth_b32_m26) + ); + AO22x1_ASAP7_75t_R \U$1737 ( + .A1(b_registered[26]), + .A2(\sel_0$1921 ), + .B1(b_registered[27]), + .B2(\sel_1$1922 ), + .Y(\t$2546 ) + ); + XOR2x1_ASAP7_75t_R \U$1738 ( + .A(\t$2546 ), + .B(1'h0), + .Y(booth_b32_m27) + ); + AO22x1_ASAP7_75t_R \U$1739 ( + .A1(b_registered[27]), + .A2(\sel_0$1921 ), + .B1(b_registered[28]), + .B2(\sel_1$1922 ), + .Y(\t$2547 ) + ); + XOR2x1_ASAP7_75t_R \U$1740 ( + .A(\t$2547 ), + .B(1'h0), + .Y(booth_b32_m28) + ); + AO22x1_ASAP7_75t_R \U$1741 ( + .A1(b_registered[28]), + .A2(\sel_0$1921 ), + .B1(b_registered[29]), + .B2(\sel_1$1922 ), + .Y(\t$2548 ) + ); + XOR2x1_ASAP7_75t_R \U$1742 ( + .A(\t$2548 ), + .B(1'h0), + .Y(booth_b32_m29) + ); + AO22x1_ASAP7_75t_R \U$1743 ( + .A1(b_registered[29]), + .A2(\sel_0$1921 ), + .B1(b_registered[30]), + .B2(\sel_1$1922 ), + .Y(\t$2549 ) + ); + XOR2x1_ASAP7_75t_R \U$1744 ( + .A(\t$2549 ), + .B(1'h0), + .Y(booth_b32_m30) + ); + AO22x1_ASAP7_75t_R \U$1745 ( + .A1(b_registered[30]), + .A2(\sel_0$1921 ), + .B1(b_registered[31]), + .B2(\sel_1$1922 ), + .Y(\t$2550 ) + ); + XOR2x1_ASAP7_75t_R \U$1746 ( + .A(\t$2550 ), + .B(1'h0), + .Y(booth_b32_m31) + ); + AO22x1_ASAP7_75t_R \U$1747 ( + .A1(b_registered[31]), + .A2(\sel_0$1921 ), + .B1(1'h0), + .B2(\sel_1$1922 ), + .Y(\t$2551 ) + ); + XOR2x1_ASAP7_75t_R \U$1748 ( + .A(\t$2551 ), + .B(1'h0), + .Y(booth_b32_m32) + ); + INVx1_ASAP7_75t_R \U$1749 ( + .A(1'h0), + .Y(\$52 ) + ); + INVx1_ASAP7_75t_R \U$1750 ( + .A(con), + .Y(\c$2553 ) + ); + INVx1_ASAP7_75t_R \U$1751 ( + .A(sn), + .Y(\s$2555 ) + ); + INVx1_ASAP7_75t_R \U$1752 ( + .A(\con$2556 ), + .Y(\c$2557 ) + ); + INVx1_ASAP7_75t_R \U$1753 ( + .A(\sn$2558 ), + .Y(\s$2559 ) + ); + INVx1_ASAP7_75t_R \U$1754 ( + .A(\con$2560 ), + .Y(\c$2561 ) + ); + INVx1_ASAP7_75t_R \U$1755 ( + .A(\sn$2562 ), + .Y(\s$2563 ) + ); + INVx1_ASAP7_75t_R \U$1756 ( + .A(\con$2564 ), + .Y(\c$2565 ) + ); + INVx1_ASAP7_75t_R \U$1757 ( + .A(\sn$2566 ), + .Y(\s$2567 ) + ); + INVx1_ASAP7_75t_R \U$1758 ( + .A(\con$2568 ), + .Y(\c$2569 ) + ); + INVx1_ASAP7_75t_R \U$1759 ( + .A(\sn$2570 ), + .Y(\s$2571 ) + ); + INVx1_ASAP7_75t_R \U$1760 ( + .A(\con$2572 ), + .Y(\c$2573 ) + ); + INVx1_ASAP7_75t_R \U$1761 ( + .A(\sn$2574 ), + .Y(\s$2575 ) + ); + INVx1_ASAP7_75t_R \U$1762 ( + .A(\con$2576 ), + .Y(\c$2577 ) + ); + INVx1_ASAP7_75t_R \U$1763 ( + .A(\sn$2578 ), + .Y(\s$2579 ) + ); + INVx1_ASAP7_75t_R \U$1764 ( + .A(\con$2580 ), + .Y(\c$2581 ) + ); + INVx1_ASAP7_75t_R \U$1765 ( + .A(\sn$2582 ), + .Y(\s$2583 ) + ); + INVx1_ASAP7_75t_R \U$1766 ( + .A(\con$2584 ), + .Y(\c$2585 ) + ); + INVx1_ASAP7_75t_R \U$1767 ( + .A(\sn$2586 ), + .Y(\s$2587 ) + ); + INVx1_ASAP7_75t_R \U$1768 ( + .A(\con$2588 ), + .Y(\c$2589 ) + ); + INVx1_ASAP7_75t_R \U$1769 ( + .A(\sn$2590 ), + .Y(\s$2591 ) + ); + INVx1_ASAP7_75t_R \U$1770 ( + .A(\con$2592 ), + .Y(\c$2593 ) + ); + INVx1_ASAP7_75t_R \U$1771 ( + .A(\sn$2594 ), + .Y(\s$2595 ) + ); + INVx1_ASAP7_75t_R \U$1772 ( + .A(\con$2596 ), + .Y(\c$2597 ) + ); + INVx1_ASAP7_75t_R \U$1773 ( + .A(\sn$2598 ), + .Y(\s$2599 ) + ); + INVx1_ASAP7_75t_R \U$1774 ( + .A(\con$2600 ), + .Y(\c$2601 ) + ); + INVx1_ASAP7_75t_R \U$1775 ( + .A(\sn$2602 ), + .Y(\s$2603 ) + ); + INVx1_ASAP7_75t_R \U$1776 ( + .A(\con$2604 ), + .Y(\c$2605 ) + ); + INVx1_ASAP7_75t_R \U$1777 ( + .A(\sn$2606 ), + .Y(\s$2607 ) + ); + INVx1_ASAP7_75t_R \U$1778 ( + .A(\con$2608 ), + .Y(\c$2609 ) + ); + INVx1_ASAP7_75t_R \U$1779 ( + .A(\sn$2610 ), + .Y(\s$2611 ) + ); + INVx1_ASAP7_75t_R \U$1780 ( + .A(\con$2612 ), + .Y(\c$2613 ) + ); + INVx1_ASAP7_75t_R \U$1781 ( + .A(\sn$2614 ), + .Y(\s$2615 ) + ); + INVx1_ASAP7_75t_R \U$1782 ( + .A(\con$2616 ), + .Y(\c$2617 ) + ); + INVx1_ASAP7_75t_R \U$1783 ( + .A(\sn$2618 ), + .Y(\s$2619 ) + ); + INVx1_ASAP7_75t_R \U$1784 ( + .A(\con$2620 ), + .Y(\c$2621 ) + ); + INVx1_ASAP7_75t_R \U$1785 ( + .A(\sn$2622 ), + .Y(\s$2623 ) + ); + INVx1_ASAP7_75t_R \U$1786 ( + .A(\con$2624 ), + .Y(\c$2625 ) + ); + INVx1_ASAP7_75t_R \U$1787 ( + .A(\sn$2626 ), + .Y(\s$2627 ) + ); + INVx1_ASAP7_75t_R \U$1788 ( + .A(\con$2628 ), + .Y(\c$2629 ) + ); + INVx1_ASAP7_75t_R \U$1789 ( + .A(\sn$2630 ), + .Y(\s$2631 ) + ); + INVx1_ASAP7_75t_R \U$1790 ( + .A(\con$2632 ), + .Y(\c$2633 ) + ); + INVx1_ASAP7_75t_R \U$1791 ( + .A(\sn$2634 ), + .Y(\s$2635 ) + ); + INVx1_ASAP7_75t_R \U$1792 ( + .A(\con$2636 ), + .Y(\c$2637 ) + ); + INVx1_ASAP7_75t_R \U$1793 ( + .A(\sn$2638 ), + .Y(\s$2639 ) + ); + INVx1_ASAP7_75t_R \U$1794 ( + .A(\con$2640 ), + .Y(\c$2641 ) + ); + INVx1_ASAP7_75t_R \U$1795 ( + .A(\sn$2642 ), + .Y(\s$2643 ) + ); + INVx1_ASAP7_75t_R \U$1796 ( + .A(\con$2644 ), + .Y(\c$2645 ) + ); + INVx1_ASAP7_75t_R \U$1797 ( + .A(\sn$2646 ), + .Y(\s$2647 ) + ); + INVx1_ASAP7_75t_R \U$1798 ( + .A(\con$2648 ), + .Y(\c$2649 ) + ); + INVx1_ASAP7_75t_R \U$1799 ( + .A(\sn$2650 ), + .Y(\s$2651 ) + ); + INVx1_ASAP7_75t_R \U$1800 ( + .A(\con$2652 ), + .Y(\c$2653 ) + ); + INVx1_ASAP7_75t_R \U$1801 ( + .A(\sn$2654 ), + .Y(\s$2655 ) + ); + INVx1_ASAP7_75t_R \U$1802 ( + .A(\con$2656 ), + .Y(\c$2657 ) + ); + INVx1_ASAP7_75t_R \U$1803 ( + .A(\sn$2658 ), + .Y(\s$2659 ) + ); + INVx1_ASAP7_75t_R \U$1804 ( + .A(\con$2660 ), + .Y(\c$2661 ) + ); + INVx1_ASAP7_75t_R \U$1805 ( + .A(\sn$2662 ), + .Y(\s$2663 ) + ); + INVx1_ASAP7_75t_R \U$1806 ( + .A(\con$2664 ), + .Y(\c$2665 ) + ); + INVx1_ASAP7_75t_R \U$1807 ( + .A(\sn$2666 ), + .Y(\s$2667 ) + ); + INVx1_ASAP7_75t_R \U$1808 ( + .A(\con$2668 ), + .Y(\c$2669 ) + ); + INVx1_ASAP7_75t_R \U$1809 ( + .A(\sn$2670 ), + .Y(\s$2671 ) + ); + INVx1_ASAP7_75t_R \U$1810 ( + .A(\con$2672 ), + .Y(\c$2673 ) + ); + INVx1_ASAP7_75t_R \U$1811 ( + .A(\sn$2674 ), + .Y(\s$2675 ) + ); + INVx1_ASAP7_75t_R \U$1812 ( + .A(\con$2676 ), + .Y(\c$2677 ) + ); + INVx1_ASAP7_75t_R \U$1813 ( + .A(\sn$2678 ), + .Y(\s$2679 ) + ); + INVx1_ASAP7_75t_R \U$1814 ( + .A(\con$2680 ), + .Y(\c$2681 ) + ); + INVx1_ASAP7_75t_R \U$1815 ( + .A(\sn$2682 ), + .Y(\s$2683 ) + ); + INVx1_ASAP7_75t_R \U$1816 ( + .A(\con$2684 ), + .Y(\c$2685 ) + ); + INVx1_ASAP7_75t_R \U$1817 ( + .A(\sn$2686 ), + .Y(\s$2687 ) + ); + INVx1_ASAP7_75t_R \U$1818 ( + .A(\con$2688 ), + .Y(\c$2689 ) + ); + INVx1_ASAP7_75t_R \U$1819 ( + .A(\sn$2690 ), + .Y(\s$2691 ) + ); + INVx1_ASAP7_75t_R \U$1820 ( + .A(\con$2692 ), + .Y(\c$2693 ) + ); + INVx1_ASAP7_75t_R \U$1821 ( + .A(\sn$2694 ), + .Y(\s$2695 ) + ); + INVx1_ASAP7_75t_R \U$1822 ( + .A(\con$2696 ), + .Y(\c$2697 ) + ); + INVx1_ASAP7_75t_R \U$1823 ( + .A(\sn$2698 ), + .Y(\s$2699 ) + ); + INVx1_ASAP7_75t_R \U$1824 ( + .A(\con$2700 ), + .Y(\c$2701 ) + ); + INVx1_ASAP7_75t_R \U$1825 ( + .A(\sn$2702 ), + .Y(\s$2703 ) + ); + INVx1_ASAP7_75t_R \U$1826 ( + .A(\con$2704 ), + .Y(\c$2705 ) + ); + INVx1_ASAP7_75t_R \U$1827 ( + .A(\sn$2706 ), + .Y(\s$2707 ) + ); + INVx1_ASAP7_75t_R \U$1828 ( + .A(\con$2708 ), + .Y(\c$2709 ) + ); + INVx1_ASAP7_75t_R \U$1829 ( + .A(\sn$2710 ), + .Y(\s$2711 ) + ); + INVx1_ASAP7_75t_R \U$1830 ( + .A(\con$2712 ), + .Y(\c$2713 ) + ); + INVx1_ASAP7_75t_R \U$1831 ( + .A(\sn$2714 ), + .Y(\s$2715 ) + ); + INVx1_ASAP7_75t_R \U$1832 ( + .A(\con$2716 ), + .Y(\c$2717 ) + ); + INVx1_ASAP7_75t_R \U$1833 ( + .A(\sn$2718 ), + .Y(\s$2719 ) + ); + INVx1_ASAP7_75t_R \U$1834 ( + .A(\con$2720 ), + .Y(\c$2721 ) + ); + INVx1_ASAP7_75t_R \U$1835 ( + .A(\sn$2722 ), + .Y(\s$2723 ) + ); + INVx1_ASAP7_75t_R \U$1836 ( + .A(\con$2724 ), + .Y(\c$2725 ) + ); + INVx1_ASAP7_75t_R \U$1837 ( + .A(\sn$2726 ), + .Y(\s$2727 ) + ); + INVx1_ASAP7_75t_R \U$1838 ( + .A(\con$2728 ), + .Y(\c$2729 ) + ); + INVx1_ASAP7_75t_R \U$1839 ( + .A(\sn$2730 ), + .Y(\s$2731 ) + ); + INVx1_ASAP7_75t_R \U$1840 ( + .A(\con$2732 ), + .Y(\c$2733 ) + ); + INVx1_ASAP7_75t_R \U$1841 ( + .A(\sn$2734 ), + .Y(\s$2735 ) + ); + INVx1_ASAP7_75t_R \U$1842 ( + .A(\con$2736 ), + .Y(\c$2737 ) + ); + INVx1_ASAP7_75t_R \U$1843 ( + .A(\sn$2738 ), + .Y(\s$2739 ) + ); + INVx1_ASAP7_75t_R \U$1844 ( + .A(\con$2740 ), + .Y(\c$2741 ) + ); + INVx1_ASAP7_75t_R \U$1845 ( + .A(\sn$2742 ), + .Y(\s$2743 ) + ); + INVx1_ASAP7_75t_R \U$1846 ( + .A(\con$2744 ), + .Y(\c$2745 ) + ); + INVx1_ASAP7_75t_R \U$1847 ( + .A(\sn$2746 ), + .Y(\s$2747 ) + ); + INVx1_ASAP7_75t_R \U$1848 ( + .A(\con$2748 ), + .Y(\c$2749 ) + ); + INVx1_ASAP7_75t_R \U$1849 ( + .A(\sn$2750 ), + .Y(\s$2751 ) + ); + INVx1_ASAP7_75t_R \U$1850 ( + .A(\con$2752 ), + .Y(\c$2753 ) + ); + INVx1_ASAP7_75t_R \U$1851 ( + .A(\sn$2754 ), + .Y(\s$2755 ) + ); + INVx1_ASAP7_75t_R \U$1852 ( + .A(\con$2756 ), + .Y(\c$2757 ) + ); + INVx1_ASAP7_75t_R \U$1853 ( + .A(\sn$2758 ), + .Y(\s$2759 ) + ); + INVx1_ASAP7_75t_R \U$1854 ( + .A(\con$2760 ), + .Y(\c$2761 ) + ); + INVx1_ASAP7_75t_R \U$1855 ( + .A(\sn$2762 ), + .Y(\s$2763 ) + ); + INVx1_ASAP7_75t_R \U$1856 ( + .A(\con$2764 ), + .Y(\c$2765 ) + ); + INVx1_ASAP7_75t_R \U$1857 ( + .A(\sn$2766 ), + .Y(\s$2767 ) + ); + INVx1_ASAP7_75t_R \U$1858 ( + .A(\con$2768 ), + .Y(\c$2769 ) + ); + INVx1_ASAP7_75t_R \U$1859 ( + .A(\sn$2770 ), + .Y(\s$2771 ) + ); + INVx1_ASAP7_75t_R \U$1860 ( + .A(\con$2772 ), + .Y(\c$2773 ) + ); + INVx1_ASAP7_75t_R \U$1861 ( + .A(\sn$2774 ), + .Y(\s$2775 ) + ); + INVx1_ASAP7_75t_R \U$1862 ( + .A(\con$2776 ), + .Y(\c$2777 ) + ); + INVx1_ASAP7_75t_R \U$1863 ( + .A(\sn$2778 ), + .Y(\s$2779 ) + ); + INVx1_ASAP7_75t_R \U$1864 ( + .A(\con$2780 ), + .Y(\c$2781 ) + ); + INVx1_ASAP7_75t_R \U$1865 ( + .A(\sn$2782 ), + .Y(\s$2783 ) + ); + INVx1_ASAP7_75t_R \U$1866 ( + .A(\con$2784 ), + .Y(\c$2785 ) + ); + INVx1_ASAP7_75t_R \U$1867 ( + .A(\sn$2786 ), + .Y(\s$2787 ) + ); + INVx1_ASAP7_75t_R \U$1868 ( + .A(\con$2788 ), + .Y(\c$2789 ) + ); + INVx1_ASAP7_75t_R \U$1869 ( + .A(\sn$2790 ), + .Y(\s$2791 ) + ); + INVx1_ASAP7_75t_R \U$1870 ( + .A(\con$2792 ), + .Y(\c$2793 ) + ); + INVx1_ASAP7_75t_R \U$1871 ( + .A(\sn$2794 ), + .Y(\s$2795 ) + ); + INVx1_ASAP7_75t_R \U$1872 ( + .A(\con$2796 ), + .Y(\c$2797 ) + ); + INVx1_ASAP7_75t_R \U$1873 ( + .A(\sn$2798 ), + .Y(\s$2799 ) + ); + INVx1_ASAP7_75t_R \U$1874 ( + .A(\con$2800 ), + .Y(\c$2801 ) + ); + INVx1_ASAP7_75t_R \U$1875 ( + .A(\sn$2802 ), + .Y(\s$2803 ) + ); + INVx1_ASAP7_75t_R \U$1876 ( + .A(\con$2804 ), + .Y(\c$2805 ) + ); + INVx1_ASAP7_75t_R \U$1877 ( + .A(\sn$2806 ), + .Y(\s$2807 ) + ); + INVx1_ASAP7_75t_R \U$1878 ( + .A(\con$2808 ), + .Y(\c$2809 ) + ); + INVx1_ASAP7_75t_R \U$1879 ( + .A(\sn$2810 ), + .Y(\s$2811 ) + ); + INVx1_ASAP7_75t_R \U$1880 ( + .A(\con$2812 ), + .Y(\c$2813 ) + ); + INVx1_ASAP7_75t_R \U$1881 ( + .A(\sn$2814 ), + .Y(\s$2815 ) + ); + INVx1_ASAP7_75t_R \U$1882 ( + .A(\con$2816 ), + .Y(\c$2817 ) + ); + INVx1_ASAP7_75t_R \U$1883 ( + .A(\sn$2818 ), + .Y(\s$2819 ) + ); + INVx1_ASAP7_75t_R \U$1884 ( + .A(\con$2820 ), + .Y(\c$2821 ) + ); + INVx1_ASAP7_75t_R \U$1885 ( + .A(\sn$2822 ), + .Y(\s$2823 ) + ); + INVx1_ASAP7_75t_R \U$1886 ( + .A(\con$2824 ), + .Y(\c$2825 ) + ); + INVx1_ASAP7_75t_R \U$1887 ( + .A(\sn$2826 ), + .Y(\s$2827 ) + ); + INVx1_ASAP7_75t_R \U$1888 ( + .A(\con$2828 ), + .Y(\c$2829 ) + ); + INVx1_ASAP7_75t_R \U$1889 ( + .A(\sn$2830 ), + .Y(\s$2831 ) + ); + INVx1_ASAP7_75t_R \U$1890 ( + .A(\con$2832 ), + .Y(\c$2833 ) + ); + INVx1_ASAP7_75t_R \U$1891 ( + .A(\sn$2834 ), + .Y(\s$2835 ) + ); + INVx1_ASAP7_75t_R \U$1892 ( + .A(\con$2836 ), + .Y(\c$2837 ) + ); + INVx1_ASAP7_75t_R \U$1893 ( + .A(\sn$2838 ), + .Y(\s$2839 ) + ); + INVx1_ASAP7_75t_R \U$1894 ( + .A(\con$2840 ), + .Y(\c$2841 ) + ); + INVx1_ASAP7_75t_R \U$1895 ( + .A(\sn$2842 ), + .Y(\s$2843 ) + ); + INVx1_ASAP7_75t_R \U$1896 ( + .A(\con$2844 ), + .Y(\c$2845 ) + ); + INVx1_ASAP7_75t_R \U$1897 ( + .A(\sn$2846 ), + .Y(\s$2847 ) + ); + INVx1_ASAP7_75t_R \U$1898 ( + .A(\con$2848 ), + .Y(\c$2849 ) + ); + INVx1_ASAP7_75t_R \U$1899 ( + .A(\sn$2850 ), + .Y(\s$2851 ) + ); + INVx1_ASAP7_75t_R \U$1900 ( + .A(\con$2852 ), + .Y(\c$2853 ) + ); + INVx1_ASAP7_75t_R \U$1901 ( + .A(\sn$2854 ), + .Y(\s$2855 ) + ); + INVx1_ASAP7_75t_R \U$1902 ( + .A(\con$2856 ), + .Y(\c$2857 ) + ); + INVx1_ASAP7_75t_R \U$1903 ( + .A(\sn$2858 ), + .Y(\s$2859 ) + ); + INVx1_ASAP7_75t_R \U$1904 ( + .A(\con$2860 ), + .Y(\c$2861 ) + ); + INVx1_ASAP7_75t_R \U$1905 ( + .A(\sn$2862 ), + .Y(\s$2863 ) + ); + INVx1_ASAP7_75t_R \U$1906 ( + .A(\con$2864 ), + .Y(\c$2865 ) + ); + INVx1_ASAP7_75t_R \U$1907 ( + .A(\sn$2866 ), + .Y(\s$2867 ) + ); + INVx1_ASAP7_75t_R \U$1908 ( + .A(\con$2868 ), + .Y(\c$2869 ) + ); + INVx1_ASAP7_75t_R \U$1909 ( + .A(\sn$2870 ), + .Y(\s$2871 ) + ); + INVx1_ASAP7_75t_R \U$1910 ( + .A(\con$2872 ), + .Y(\c$2873 ) + ); + INVx1_ASAP7_75t_R \U$1911 ( + .A(\sn$2874 ), + .Y(\s$2875 ) + ); + INVx1_ASAP7_75t_R \U$1912 ( + .A(\con$2876 ), + .Y(\c$2877 ) + ); + INVx1_ASAP7_75t_R \U$1913 ( + .A(\sn$2878 ), + .Y(\s$2879 ) + ); + INVx1_ASAP7_75t_R \U$1914 ( + .A(\con$2880 ), + .Y(\c$2881 ) + ); + INVx1_ASAP7_75t_R \U$1915 ( + .A(\sn$2882 ), + .Y(\s$2883 ) + ); + INVx1_ASAP7_75t_R \U$1916 ( + .A(\con$2884 ), + .Y(\c$2885 ) + ); + INVx1_ASAP7_75t_R \U$1917 ( + .A(\sn$2886 ), + .Y(\s$2887 ) + ); + INVx1_ASAP7_75t_R \U$1918 ( + .A(\con$2888 ), + .Y(\c$2889 ) + ); + INVx1_ASAP7_75t_R \U$1919 ( + .A(\sn$2890 ), + .Y(\s$2891 ) + ); + INVx1_ASAP7_75t_R \U$1920 ( + .A(\con$2892 ), + .Y(\c$2893 ) + ); + INVx1_ASAP7_75t_R \U$1921 ( + .A(\sn$2894 ), + .Y(\s$2895 ) + ); + INVx1_ASAP7_75t_R \U$1922 ( + .A(\con$2896 ), + .Y(\c$2897 ) + ); + INVx1_ASAP7_75t_R \U$1923 ( + .A(\sn$2898 ), + .Y(\s$2899 ) + ); + INVx1_ASAP7_75t_R \U$1924 ( + .A(\con$2900 ), + .Y(\c$2901 ) + ); + INVx1_ASAP7_75t_R \U$1925 ( + .A(\sn$2902 ), + .Y(\s$2903 ) + ); + INVx1_ASAP7_75t_R \U$1926 ( + .A(\con$2904 ), + .Y(\c$2905 ) + ); + INVx1_ASAP7_75t_R \U$1927 ( + .A(\sn$2906 ), + .Y(\s$2907 ) + ); + INVx1_ASAP7_75t_R \U$1928 ( + .A(\con$2908 ), + .Y(\c$2909 ) + ); + INVx1_ASAP7_75t_R \U$1929 ( + .A(\sn$2910 ), + .Y(\s$2911 ) + ); + INVx1_ASAP7_75t_R \U$1930 ( + .A(\con$2912 ), + .Y(\c$2913 ) + ); + INVx1_ASAP7_75t_R \U$1931 ( + .A(\sn$2914 ), + .Y(\s$2915 ) + ); + INVx1_ASAP7_75t_R \U$1932 ( + .A(\con$2916 ), + .Y(\c$2917 ) + ); + INVx1_ASAP7_75t_R \U$1933 ( + .A(\sn$2918 ), + .Y(\s$2919 ) + ); + INVx1_ASAP7_75t_R \U$1934 ( + .A(\con$2920 ), + .Y(\c$2921 ) + ); + INVx1_ASAP7_75t_R \U$1935 ( + .A(\sn$2922 ), + .Y(\s$2923 ) + ); + INVx1_ASAP7_75t_R \U$1936 ( + .A(\con$2924 ), + .Y(\c$2925 ) + ); + INVx1_ASAP7_75t_R \U$1937 ( + .A(\sn$2926 ), + .Y(\s$2927 ) + ); + INVx1_ASAP7_75t_R \U$1938 ( + .A(\con$2928 ), + .Y(\c$2929 ) + ); + INVx1_ASAP7_75t_R \U$1939 ( + .A(\sn$2930 ), + .Y(\s$2931 ) + ); + INVx1_ASAP7_75t_R \U$1940 ( + .A(\con$2932 ), + .Y(\c$2933 ) + ); + INVx1_ASAP7_75t_R \U$1941 ( + .A(\sn$2934 ), + .Y(\s$2935 ) + ); + INVx1_ASAP7_75t_R \U$1942 ( + .A(\con$2936 ), + .Y(\c$2937 ) + ); + INVx1_ASAP7_75t_R \U$1943 ( + .A(\sn$2938 ), + .Y(\s$2939 ) + ); + INVx1_ASAP7_75t_R \U$1944 ( + .A(\con$2940 ), + .Y(\c$2941 ) + ); + INVx1_ASAP7_75t_R \U$1945 ( + .A(\sn$2942 ), + .Y(\s$2943 ) + ); + INVx1_ASAP7_75t_R \U$1946 ( + .A(\con$2944 ), + .Y(\c$2945 ) + ); + INVx1_ASAP7_75t_R \U$1947 ( + .A(\sn$2946 ), + .Y(\s$2947 ) + ); + INVx1_ASAP7_75t_R \U$1948 ( + .A(\con$2948 ), + .Y(\c$2949 ) + ); + INVx1_ASAP7_75t_R \U$1949 ( + .A(\sn$2950 ), + .Y(\s$2951 ) + ); + INVx1_ASAP7_75t_R \U$1950 ( + .A(\con$2952 ), + .Y(\c$2953 ) + ); + INVx1_ASAP7_75t_R \U$1951 ( + .A(\sn$2954 ), + .Y(\s$2955 ) + ); + INVx1_ASAP7_75t_R \U$1952 ( + .A(\con$2956 ), + .Y(\c$2957 ) + ); + INVx1_ASAP7_75t_R \U$1953 ( + .A(\sn$2958 ), + .Y(\s$2959 ) + ); + INVx1_ASAP7_75t_R \U$1954 ( + .A(\con$2960 ), + .Y(\c$2961 ) + ); + INVx1_ASAP7_75t_R \U$1955 ( + .A(\sn$2962 ), + .Y(\s$2963 ) + ); + INVx1_ASAP7_75t_R \U$1956 ( + .A(\con$2964 ), + .Y(\c$2965 ) + ); + INVx1_ASAP7_75t_R \U$1957 ( + .A(\sn$2966 ), + .Y(\s$2967 ) + ); + INVx1_ASAP7_75t_R \U$1958 ( + .A(\con$2968 ), + .Y(\c$2969 ) + ); + INVx1_ASAP7_75t_R \U$1959 ( + .A(\sn$2970 ), + .Y(\s$2971 ) + ); + INVx1_ASAP7_75t_R \U$1960 ( + .A(\con$2972 ), + .Y(\c$2973 ) + ); + INVx1_ASAP7_75t_R \U$1961 ( + .A(\sn$2974 ), + .Y(\s$2975 ) + ); + INVx1_ASAP7_75t_R \U$1962 ( + .A(\con$2976 ), + .Y(\c$2977 ) + ); + INVx1_ASAP7_75t_R \U$1963 ( + .A(\sn$2978 ), + .Y(\s$2979 ) + ); + INVx1_ASAP7_75t_R \U$1964 ( + .A(\con$2980 ), + .Y(\c$2981 ) + ); + INVx1_ASAP7_75t_R \U$1965 ( + .A(\sn$2982 ), + .Y(\s$2983 ) + ); + INVx1_ASAP7_75t_R \U$1966 ( + .A(\con$2984 ), + .Y(\c$2985 ) + ); + INVx1_ASAP7_75t_R \U$1967 ( + .A(\sn$2986 ), + .Y(\s$2987 ) + ); + INVx1_ASAP7_75t_R \U$1968 ( + .A(\con$2988 ), + .Y(\c$2989 ) + ); + INVx1_ASAP7_75t_R \U$1969 ( + .A(\sn$2990 ), + .Y(\s$2991 ) + ); + INVx1_ASAP7_75t_R \U$1970 ( + .A(\con$2992 ), + .Y(\c$2993 ) + ); + INVx1_ASAP7_75t_R \U$1971 ( + .A(\sn$2994 ), + .Y(\s$2995 ) + ); + INVx1_ASAP7_75t_R \U$1972 ( + .A(\con$2996 ), + .Y(\c$2997 ) + ); + INVx1_ASAP7_75t_R \U$1973 ( + .A(\sn$2998 ), + .Y(\s$2999 ) + ); + INVx1_ASAP7_75t_R \U$1974 ( + .A(\con$3000 ), + .Y(\c$3001 ) + ); + INVx1_ASAP7_75t_R \U$1975 ( + .A(\sn$3002 ), + .Y(\s$3003 ) + ); + INVx1_ASAP7_75t_R \U$1976 ( + .A(\con$3004 ), + .Y(\c$3005 ) + ); + INVx1_ASAP7_75t_R \U$1977 ( + .A(\sn$3006 ), + .Y(\s$3007 ) + ); + INVx1_ASAP7_75t_R \U$1978 ( + .A(\con$3008 ), + .Y(\c$3009 ) + ); + INVx1_ASAP7_75t_R \U$1979 ( + .A(\sn$3010 ), + .Y(\s$3011 ) + ); + INVx1_ASAP7_75t_R \U$1980 ( + .A(\con$3012 ), + .Y(\c$3013 ) + ); + INVx1_ASAP7_75t_R \U$1981 ( + .A(\sn$3014 ), + .Y(\s$3015 ) + ); + INVx1_ASAP7_75t_R \U$1982 ( + .A(\con$3016 ), + .Y(\c$3017 ) + ); + INVx1_ASAP7_75t_R \U$1983 ( + .A(\sn$3018 ), + .Y(\s$3019 ) + ); + INVx1_ASAP7_75t_R \U$1984 ( + .A(\con$3020 ), + .Y(\c$3021 ) + ); + INVx1_ASAP7_75t_R \U$1985 ( + .A(\sn$3022 ), + .Y(\s$3023 ) + ); + INVx1_ASAP7_75t_R \U$1986 ( + .A(\con$3024 ), + .Y(\c$3025 ) + ); + INVx1_ASAP7_75t_R \U$1987 ( + .A(\sn$3026 ), + .Y(\s$3027 ) + ); + INVx1_ASAP7_75t_R \U$1988 ( + .A(\con$3028 ), + .Y(\c$3029 ) + ); + INVx1_ASAP7_75t_R \U$1989 ( + .A(\sn$3030 ), + .Y(\s$3031 ) + ); + INVx1_ASAP7_75t_R \U$1990 ( + .A(\con$3032 ), + .Y(\c$3033 ) + ); + INVx1_ASAP7_75t_R \U$1991 ( + .A(\sn$3034 ), + .Y(\s$3035 ) + ); + INVx1_ASAP7_75t_R \U$1992 ( + .A(\con$3036 ), + .Y(\c$3037 ) + ); + INVx1_ASAP7_75t_R \U$1993 ( + .A(\sn$3038 ), + .Y(\s$3039 ) + ); + INVx1_ASAP7_75t_R \U$1994 ( + .A(\con$3040 ), + .Y(\c$3041 ) + ); + INVx1_ASAP7_75t_R \U$1995 ( + .A(\sn$3042 ), + .Y(\s$3043 ) + ); + INVx1_ASAP7_75t_R \U$1996 ( + .A(\con$3044 ), + .Y(\c$3045 ) + ); + INVx1_ASAP7_75t_R \U$1997 ( + .A(\sn$3046 ), + .Y(\s$3047 ) + ); + INVx1_ASAP7_75t_R \U$1998 ( + .A(\con$3048 ), + .Y(\c$3049 ) + ); + INVx1_ASAP7_75t_R \U$1999 ( + .A(\sn$3050 ), + .Y(\s$3051 ) + ); + INVx1_ASAP7_75t_R \U$2000 ( + .A(\con$3052 ), + .Y(\c$3053 ) + ); + INVx1_ASAP7_75t_R \U$2001 ( + .A(\sn$3054 ), + .Y(\s$3055 ) + ); + INVx1_ASAP7_75t_R \U$2002 ( + .A(\con$3056 ), + .Y(\c$3057 ) + ); + INVx1_ASAP7_75t_R \U$2003 ( + .A(\sn$3058 ), + .Y(\s$3059 ) + ); + INVx1_ASAP7_75t_R \U$2004 ( + .A(\con$3060 ), + .Y(\c$3061 ) + ); + INVx1_ASAP7_75t_R \U$2005 ( + .A(\sn$3062 ), + .Y(\s$3063 ) + ); + INVx1_ASAP7_75t_R \U$2006 ( + .A(\con$3064 ), + .Y(\c$3065 ) + ); + INVx1_ASAP7_75t_R \U$2007 ( + .A(\sn$3066 ), + .Y(\s$3067 ) + ); + INVx1_ASAP7_75t_R \U$2008 ( + .A(\con$3068 ), + .Y(\c$3069 ) + ); + INVx1_ASAP7_75t_R \U$2009 ( + .A(\sn$3070 ), + .Y(\s$3071 ) + ); + INVx1_ASAP7_75t_R \U$2010 ( + .A(\con$3072 ), + .Y(\c$3073 ) + ); + INVx1_ASAP7_75t_R \U$2011 ( + .A(\sn$3074 ), + .Y(\s$3075 ) + ); + INVx1_ASAP7_75t_R \U$2012 ( + .A(\con$3076 ), + .Y(\c$3077 ) + ); + INVx1_ASAP7_75t_R \U$2013 ( + .A(\sn$3078 ), + .Y(\s$3079 ) + ); + INVx1_ASAP7_75t_R \U$2014 ( + .A(\con$3080 ), + .Y(\c$3081 ) + ); + INVx1_ASAP7_75t_R \U$2015 ( + .A(\sn$3082 ), + .Y(\s$3083 ) + ); + INVx1_ASAP7_75t_R \U$2016 ( + .A(\con$3084 ), + .Y(\c$3085 ) + ); + INVx1_ASAP7_75t_R \U$2017 ( + .A(\sn$3086 ), + .Y(\s$3087 ) + ); + INVx1_ASAP7_75t_R \U$2018 ( + .A(\con$3088 ), + .Y(\c$3089 ) + ); + INVx1_ASAP7_75t_R \U$2019 ( + .A(\sn$3090 ), + .Y(\s$3091 ) + ); + INVx1_ASAP7_75t_R \U$2020 ( + .A(\con$3092 ), + .Y(\c$3093 ) + ); + INVx1_ASAP7_75t_R \U$2021 ( + .A(\sn$3094 ), + .Y(\s$3095 ) + ); + INVx1_ASAP7_75t_R \U$2022 ( + .A(\con$3096 ), + .Y(\c$3097 ) + ); + INVx1_ASAP7_75t_R \U$2023 ( + .A(\sn$3098 ), + .Y(\s$3099 ) + ); + INVx1_ASAP7_75t_R \U$2024 ( + .A(\con$3100 ), + .Y(\c$3101 ) + ); + INVx1_ASAP7_75t_R \U$2025 ( + .A(\sn$3102 ), + .Y(\s$3103 ) + ); + INVx1_ASAP7_75t_R \U$2026 ( + .A(\con$3104 ), + .Y(\c$3105 ) + ); + INVx1_ASAP7_75t_R \U$2027 ( + .A(\sn$3106 ), + .Y(\s$3107 ) + ); + INVx1_ASAP7_75t_R \U$2028 ( + .A(\con$3108 ), + .Y(\c$3109 ) + ); + INVx1_ASAP7_75t_R \U$2029 ( + .A(\sn$3110 ), + .Y(\s$3111 ) + ); + INVx1_ASAP7_75t_R \U$2030 ( + .A(\con$3112 ), + .Y(\c$3113 ) + ); + INVx1_ASAP7_75t_R \U$2031 ( + .A(\sn$3114 ), + .Y(\s$3115 ) + ); + INVx1_ASAP7_75t_R \U$2032 ( + .A(\con$3116 ), + .Y(\c$3117 ) + ); + INVx1_ASAP7_75t_R \U$2033 ( + .A(\sn$3118 ), + .Y(\s$3119 ) + ); + INVx1_ASAP7_75t_R \U$2034 ( + .A(\con$3120 ), + .Y(\c$3121 ) + ); + INVx1_ASAP7_75t_R \U$2035 ( + .A(\sn$3122 ), + .Y(\s$3123 ) + ); + INVx1_ASAP7_75t_R \U$2036 ( + .A(\con$3124 ), + .Y(\c$3125 ) + ); + INVx1_ASAP7_75t_R \U$2037 ( + .A(\sn$3126 ), + .Y(\s$3127 ) + ); + INVx1_ASAP7_75t_R \U$2038 ( + .A(\con$3128 ), + .Y(\c$3129 ) + ); + INVx1_ASAP7_75t_R \U$2039 ( + .A(\sn$3130 ), + .Y(\s$3131 ) + ); + INVx1_ASAP7_75t_R \U$2040 ( + .A(\con$3132 ), + .Y(\c$3133 ) + ); + INVx1_ASAP7_75t_R \U$2041 ( + .A(\sn$3134 ), + .Y(\s$3135 ) + ); + INVx1_ASAP7_75t_R \U$2042 ( + .A(\con$3136 ), + .Y(\c$3137 ) + ); + INVx1_ASAP7_75t_R \U$2043 ( + .A(\sn$3138 ), + .Y(\s$3139 ) + ); + INVx1_ASAP7_75t_R \U$2044 ( + .A(\con$3140 ), + .Y(\c$3141 ) + ); + INVx1_ASAP7_75t_R \U$2045 ( + .A(\sn$3142 ), + .Y(\s$3143 ) + ); + INVx1_ASAP7_75t_R \U$2046 ( + .A(\con$3144 ), + .Y(\c$3145 ) + ); + INVx1_ASAP7_75t_R \U$2047 ( + .A(\sn$3146 ), + .Y(\s$3147 ) + ); + INVx1_ASAP7_75t_R \U$2048 ( + .A(\con$3148 ), + .Y(\c$3149 ) + ); + INVx1_ASAP7_75t_R \U$2049 ( + .A(\sn$3150 ), + .Y(\s$3151 ) + ); + INVx1_ASAP7_75t_R \U$2050 ( + .A(\con$3152 ), + .Y(\c$3153 ) + ); + INVx1_ASAP7_75t_R \U$2051 ( + .A(\sn$3154 ), + .Y(\s$3155 ) + ); + INVx1_ASAP7_75t_R \U$2052 ( + .A(\con$3156 ), + .Y(\c$3157 ) + ); + INVx1_ASAP7_75t_R \U$2053 ( + .A(\sn$3158 ), + .Y(\s$3159 ) + ); + INVx1_ASAP7_75t_R \U$2054 ( + .A(\con$3160 ), + .Y(\c$3161 ) + ); + INVx1_ASAP7_75t_R \U$2055 ( + .A(\sn$3162 ), + .Y(\s$3163 ) + ); + INVx1_ASAP7_75t_R \U$2056 ( + .A(\con$3164 ), + .Y(\c$3165 ) + ); + INVx1_ASAP7_75t_R \U$2057 ( + .A(\sn$3166 ), + .Y(\s$3167 ) + ); + INVx1_ASAP7_75t_R \U$2058 ( + .A(\con$3168 ), + .Y(\c$3169 ) + ); + INVx1_ASAP7_75t_R \U$2059 ( + .A(\sn$3170 ), + .Y(\s$3171 ) + ); + INVx1_ASAP7_75t_R \U$2060 ( + .A(\con$3172 ), + .Y(\c$3173 ) + ); + INVx1_ASAP7_75t_R \U$2061 ( + .A(\sn$3174 ), + .Y(\s$3175 ) + ); + INVx1_ASAP7_75t_R \U$2062 ( + .A(\con$3176 ), + .Y(\c$3177 ) + ); + INVx1_ASAP7_75t_R \U$2063 ( + .A(\sn$3178 ), + .Y(\s$3179 ) + ); + INVx1_ASAP7_75t_R \U$2064 ( + .A(\con$3180 ), + .Y(\c$3181 ) + ); + INVx1_ASAP7_75t_R \U$2065 ( + .A(\sn$3182 ), + .Y(\s$3183 ) + ); + INVx1_ASAP7_75t_R \U$2066 ( + .A(\con$3184 ), + .Y(\c$3185 ) + ); + INVx1_ASAP7_75t_R \U$2067 ( + .A(\sn$3186 ), + .Y(\s$3187 ) + ); + INVx1_ASAP7_75t_R \U$2068 ( + .A(\con$3188 ), + .Y(\c$3189 ) + ); + INVx1_ASAP7_75t_R \U$2069 ( + .A(\sn$3190 ), + .Y(\s$3191 ) + ); + INVx1_ASAP7_75t_R \U$2070 ( + .A(\con$3192 ), + .Y(\c$3193 ) + ); + INVx1_ASAP7_75t_R \U$2071 ( + .A(\sn$3194 ), + .Y(\s$3195 ) + ); + INVx1_ASAP7_75t_R \U$2072 ( + .A(\con$3196 ), + .Y(\c$3197 ) + ); + INVx1_ASAP7_75t_R \U$2073 ( + .A(\sn$3198 ), + .Y(\s$3199 ) + ); + INVx1_ASAP7_75t_R \U$2074 ( + .A(\con$3200 ), + .Y(\c$3201 ) + ); + INVx1_ASAP7_75t_R \U$2075 ( + .A(\sn$3202 ), + .Y(\s$3203 ) + ); + INVx1_ASAP7_75t_R \U$2076 ( + .A(\con$3204 ), + .Y(\c$3205 ) + ); + INVx1_ASAP7_75t_R \U$2077 ( + .A(\sn$3206 ), + .Y(\s$3207 ) + ); + INVx1_ASAP7_75t_R \U$2078 ( + .A(\con$3208 ), + .Y(\c$3209 ) + ); + INVx1_ASAP7_75t_R \U$2079 ( + .A(\sn$3210 ), + .Y(\s$3211 ) + ); + INVx1_ASAP7_75t_R \U$2080 ( + .A(\con$3212 ), + .Y(\c$3213 ) + ); + INVx1_ASAP7_75t_R \U$2081 ( + .A(\sn$3214 ), + .Y(\s$3215 ) + ); + INVx1_ASAP7_75t_R \U$2082 ( + .A(\con$3216 ), + .Y(\c$3217 ) + ); + INVx1_ASAP7_75t_R \U$2083 ( + .A(\sn$3218 ), + .Y(\s$3219 ) + ); + INVx1_ASAP7_75t_R \U$2084 ( + .A(\con$3220 ), + .Y(\c$3221 ) + ); + INVx1_ASAP7_75t_R \U$2085 ( + .A(\sn$3222 ), + .Y(\s$3223 ) + ); + INVx1_ASAP7_75t_R \U$2086 ( + .A(\con$3224 ), + .Y(\c$3225 ) + ); + INVx1_ASAP7_75t_R \U$2087 ( + .A(\sn$3226 ), + .Y(\s$3227 ) + ); + INVx1_ASAP7_75t_R \U$2088 ( + .A(\con$3228 ), + .Y(\c$3229 ) + ); + INVx1_ASAP7_75t_R \U$2089 ( + .A(\sn$3230 ), + .Y(\s$3231 ) + ); + INVx1_ASAP7_75t_R \U$2090 ( + .A(\con$3232 ), + .Y(\c$3233 ) + ); + INVx1_ASAP7_75t_R \U$2091 ( + .A(\sn$3234 ), + .Y(\s$3235 ) + ); + INVx1_ASAP7_75t_R \U$2092 ( + .A(\con$3236 ), + .Y(\c$3237 ) + ); + INVx1_ASAP7_75t_R \U$2093 ( + .A(\sn$3238 ), + .Y(\s$3239 ) + ); + INVx1_ASAP7_75t_R \U$2094 ( + .A(\con$3240 ), + .Y(\c$3241 ) + ); + INVx1_ASAP7_75t_R \U$2095 ( + .A(\sn$3242 ), + .Y(\s$3243 ) + ); + INVx1_ASAP7_75t_R \U$2096 ( + .A(\con$3244 ), + .Y(\c$3245 ) + ); + INVx1_ASAP7_75t_R \U$2097 ( + .A(\sn$3246 ), + .Y(\s$3247 ) + ); + INVx1_ASAP7_75t_R \U$2098 ( + .A(\con$3248 ), + .Y(\c$3249 ) + ); + INVx1_ASAP7_75t_R \U$2099 ( + .A(\sn$3250 ), + .Y(\s$3251 ) + ); + INVx1_ASAP7_75t_R \U$2100 ( + .A(\con$3252 ), + .Y(\c$3253 ) + ); + INVx1_ASAP7_75t_R \U$2101 ( + .A(\sn$3254 ), + .Y(\s$3255 ) + ); + INVx1_ASAP7_75t_R \U$2102 ( + .A(\con$3256 ), + .Y(\c$3257 ) + ); + INVx1_ASAP7_75t_R \U$2103 ( + .A(\sn$3258 ), + .Y(\s$3259 ) + ); + INVx1_ASAP7_75t_R \U$2104 ( + .A(\con$3260 ), + .Y(\c$3261 ) + ); + INVx1_ASAP7_75t_R \U$2105 ( + .A(\sn$3262 ), + .Y(\s$3263 ) + ); + INVx1_ASAP7_75t_R \U$2106 ( + .A(\con$3264 ), + .Y(\c$3265 ) + ); + INVx1_ASAP7_75t_R \U$2107 ( + .A(\sn$3266 ), + .Y(\s$3267 ) + ); + INVx1_ASAP7_75t_R \U$2108 ( + .A(\con$3268 ), + .Y(\c$3269 ) + ); + INVx1_ASAP7_75t_R \U$2109 ( + .A(\sn$3270 ), + .Y(\s$3271 ) + ); + INVx1_ASAP7_75t_R \U$2110 ( + .A(\con$3272 ), + .Y(\c$3273 ) + ); + INVx1_ASAP7_75t_R \U$2111 ( + .A(\sn$3274 ), + .Y(\s$3275 ) + ); + INVx1_ASAP7_75t_R \U$2112 ( + .A(\con$3276 ), + .Y(\c$3277 ) + ); + INVx1_ASAP7_75t_R \U$2113 ( + .A(\sn$3278 ), + .Y(\s$3279 ) + ); + INVx1_ASAP7_75t_R \U$2114 ( + .A(\con$3280 ), + .Y(\c$3281 ) + ); + INVx1_ASAP7_75t_R \U$2115 ( + .A(\sn$3282 ), + .Y(\s$3283 ) + ); + INVx1_ASAP7_75t_R \U$2116 ( + .A(\con$3284 ), + .Y(\c$3285 ) + ); + INVx1_ASAP7_75t_R \U$2117 ( + .A(\sn$3286 ), + .Y(\s$3287 ) + ); + INVx1_ASAP7_75t_R \U$2118 ( + .A(\con$3288 ), + .Y(\c$3289 ) + ); + INVx1_ASAP7_75t_R \U$2119 ( + .A(\sn$3290 ), + .Y(\s$3291 ) + ); + INVx1_ASAP7_75t_R \U$2120 ( + .A(\con$3292 ), + .Y(\c$3293 ) + ); + INVx1_ASAP7_75t_R \U$2121 ( + .A(\sn$3294 ), + .Y(\s$3295 ) + ); + INVx1_ASAP7_75t_R \U$2122 ( + .A(\con$3296 ), + .Y(\c$3297 ) + ); + INVx1_ASAP7_75t_R \U$2123 ( + .A(\sn$3298 ), + .Y(\s$3299 ) + ); + INVx1_ASAP7_75t_R \U$2124 ( + .A(\con$3300 ), + .Y(\c$3301 ) + ); + INVx1_ASAP7_75t_R \U$2125 ( + .A(\sn$3302 ), + .Y(\s$3303 ) + ); + INVx1_ASAP7_75t_R \U$2126 ( + .A(\con$3304 ), + .Y(\c$3305 ) + ); + INVx1_ASAP7_75t_R \U$2127 ( + .A(\sn$3306 ), + .Y(\s$3307 ) + ); + INVx1_ASAP7_75t_R \U$2128 ( + .A(\con$3308 ), + .Y(\c$3309 ) + ); + INVx1_ASAP7_75t_R \U$2129 ( + .A(\sn$3310 ), + .Y(\s$3311 ) + ); + INVx1_ASAP7_75t_R \U$2130 ( + .A(\con$3312 ), + .Y(\c$3313 ) + ); + INVx1_ASAP7_75t_R \U$2131 ( + .A(\sn$3314 ), + .Y(\s$3315 ) + ); + INVx1_ASAP7_75t_R \U$2132 ( + .A(\con$3316 ), + .Y(\c$3317 ) + ); + INVx1_ASAP7_75t_R \U$2133 ( + .A(\sn$3318 ), + .Y(\s$3319 ) + ); + INVx1_ASAP7_75t_R \U$2134 ( + .A(\con$3320 ), + .Y(\c$3321 ) + ); + INVx1_ASAP7_75t_R \U$2135 ( + .A(\sn$3322 ), + .Y(\s$3323 ) + ); + INVx1_ASAP7_75t_R \U$2136 ( + .A(\con$3324 ), + .Y(\c$3325 ) + ); + INVx1_ASAP7_75t_R \U$2137 ( + .A(\sn$3326 ), + .Y(\s$3327 ) + ); + INVx1_ASAP7_75t_R \U$2138 ( + .A(\con$3328 ), + .Y(\c$3329 ) + ); + INVx1_ASAP7_75t_R \U$2139 ( + .A(\sn$3330 ), + .Y(\s$3331 ) + ); + INVx1_ASAP7_75t_R \U$2140 ( + .A(\con$3332 ), + .Y(\c$3333 ) + ); + INVx1_ASAP7_75t_R \U$2141 ( + .A(\sn$3334 ), + .Y(\s$3335 ) + ); + INVx1_ASAP7_75t_R \U$2142 ( + .A(\con$3336 ), + .Y(\c$3337 ) + ); + INVx1_ASAP7_75t_R \U$2143 ( + .A(\sn$3338 ), + .Y(\s$3339 ) + ); + INVx1_ASAP7_75t_R \U$2144 ( + .A(\con$3340 ), + .Y(\c$3341 ) + ); + INVx1_ASAP7_75t_R \U$2145 ( + .A(\sn$3342 ), + .Y(\s$3343 ) + ); + INVx1_ASAP7_75t_R \U$2146 ( + .A(\con$3344 ), + .Y(\c$3345 ) + ); + INVx1_ASAP7_75t_R \U$2147 ( + .A(\sn$3346 ), + .Y(\s$3347 ) + ); + INVx1_ASAP7_75t_R \U$2148 ( + .A(\con$3348 ), + .Y(\c$3349 ) + ); + INVx1_ASAP7_75t_R \U$2149 ( + .A(\sn$3350 ), + .Y(\s$3351 ) + ); + INVx1_ASAP7_75t_R \U$2150 ( + .A(\con$3352 ), + .Y(\c$3353 ) + ); + INVx1_ASAP7_75t_R \U$2151 ( + .A(\sn$3354 ), + .Y(\s$3355 ) + ); + INVx1_ASAP7_75t_R \U$2152 ( + .A(\con$3356 ), + .Y(\c$3357 ) + ); + INVx1_ASAP7_75t_R \U$2153 ( + .A(\sn$3358 ), + .Y(\s$3359 ) + ); + INVx1_ASAP7_75t_R \U$2154 ( + .A(\con$3360 ), + .Y(\c$3361 ) + ); + INVx1_ASAP7_75t_R \U$2155 ( + .A(\sn$3362 ), + .Y(\s$3363 ) + ); + INVx1_ASAP7_75t_R \U$2156 ( + .A(\con$3364 ), + .Y(\c$3365 ) + ); + INVx1_ASAP7_75t_R \U$2157 ( + .A(\sn$3366 ), + .Y(\s$3367 ) + ); + INVx1_ASAP7_75t_R \U$2158 ( + .A(\con$3368 ), + .Y(\c$3369 ) + ); + INVx1_ASAP7_75t_R \U$2159 ( + .A(\sn$3370 ), + .Y(\s$3371 ) + ); + INVx1_ASAP7_75t_R \U$2160 ( + .A(\con$3372 ), + .Y(\c$3373 ) + ); + INVx1_ASAP7_75t_R \U$2161 ( + .A(\sn$3374 ), + .Y(\s$3375 ) + ); + INVx1_ASAP7_75t_R \U$2162 ( + .A(\con$3376 ), + .Y(\c$3377 ) + ); + INVx1_ASAP7_75t_R \U$2163 ( + .A(\sn$3378 ), + .Y(\s$3379 ) + ); + INVx1_ASAP7_75t_R \U$2164 ( + .A(\con$3380 ), + .Y(\c$3381 ) + ); + INVx1_ASAP7_75t_R \U$2165 ( + .A(\sn$3382 ), + .Y(\s$3383 ) + ); + INVx1_ASAP7_75t_R \U$2166 ( + .A(\con$3384 ), + .Y(\c$3385 ) + ); + INVx1_ASAP7_75t_R \U$2167 ( + .A(\sn$3386 ), + .Y(\s$3387 ) + ); + INVx1_ASAP7_75t_R \U$2168 ( + .A(\con$3388 ), + .Y(\c$3389 ) + ); + INVx1_ASAP7_75t_R \U$2169 ( + .A(\sn$3390 ), + .Y(\s$3391 ) + ); + INVx1_ASAP7_75t_R \U$2170 ( + .A(\con$3392 ), + .Y(\c$3393 ) + ); + INVx1_ASAP7_75t_R \U$2171 ( + .A(\sn$3394 ), + .Y(\s$3395 ) + ); + INVx1_ASAP7_75t_R \U$2172 ( + .A(\con$3396 ), + .Y(\c$3397 ) + ); + INVx1_ASAP7_75t_R \U$2173 ( + .A(\sn$3398 ), + .Y(\s$3399 ) + ); + INVx1_ASAP7_75t_R \U$2174 ( + .A(\con$3400 ), + .Y(\c$3401 ) + ); + INVx1_ASAP7_75t_R \U$2175 ( + .A(\sn$3402 ), + .Y(\s$3403 ) + ); + INVx1_ASAP7_75t_R \U$2176 ( + .A(\con$3404 ), + .Y(\c$3405 ) + ); + INVx1_ASAP7_75t_R \U$2177 ( + .A(\sn$3406 ), + .Y(\s$3407 ) + ); + INVx1_ASAP7_75t_R \U$2178 ( + .A(\con$3408 ), + .Y(\c$3409 ) + ); + INVx1_ASAP7_75t_R \U$2179 ( + .A(\sn$3410 ), + .Y(\s$3411 ) + ); + INVx1_ASAP7_75t_R \U$2180 ( + .A(\con$3412 ), + .Y(\c$3413 ) + ); + INVx1_ASAP7_75t_R \U$2181 ( + .A(\sn$3414 ), + .Y(\s$3415 ) + ); + INVx1_ASAP7_75t_R \U$2182 ( + .A(\con$3416 ), + .Y(\c$3417 ) + ); + INVx1_ASAP7_75t_R \U$2183 ( + .A(\sn$3418 ), + .Y(\s$3419 ) + ); + INVx1_ASAP7_75t_R \U$2184 ( + .A(\con$3420 ), + .Y(\c$3421 ) + ); + INVx1_ASAP7_75t_R \U$2185 ( + .A(\sn$3422 ), + .Y(\s$3423 ) + ); + INVx1_ASAP7_75t_R \U$2186 ( + .A(\con$3424 ), + .Y(\c$3425 ) + ); + INVx1_ASAP7_75t_R \U$2187 ( + .A(\sn$3426 ), + .Y(\s$3427 ) + ); + INVx1_ASAP7_75t_R \U$2188 ( + .A(\con$3428 ), + .Y(\c$3429 ) + ); + INVx1_ASAP7_75t_R \U$2189 ( + .A(\sn$3430 ), + .Y(\s$3431 ) + ); + INVx1_ASAP7_75t_R \U$2190 ( + .A(\con$3432 ), + .Y(\c$3433 ) + ); + INVx1_ASAP7_75t_R \U$2191 ( + .A(\sn$3434 ), + .Y(\s$3435 ) + ); + INVx1_ASAP7_75t_R \U$2192 ( + .A(\con$3436 ), + .Y(\c$3437 ) + ); + INVx1_ASAP7_75t_R \U$2193 ( + .A(\sn$3438 ), + .Y(\s$3439 ) + ); + INVx1_ASAP7_75t_R \U$2194 ( + .A(\con$3440 ), + .Y(\c$3441 ) + ); + INVx1_ASAP7_75t_R \U$2195 ( + .A(\sn$3442 ), + .Y(\s$3443 ) + ); + INVx1_ASAP7_75t_R \U$2196 ( + .A(\con$3444 ), + .Y(\c$3445 ) + ); + INVx1_ASAP7_75t_R \U$2197 ( + .A(\sn$3446 ), + .Y(\s$3447 ) + ); + INVx1_ASAP7_75t_R \U$2198 ( + .A(\con$3448 ), + .Y(\c$3449 ) + ); + INVx1_ASAP7_75t_R \U$2199 ( + .A(\sn$3450 ), + .Y(\s$3451 ) + ); + INVx1_ASAP7_75t_R \U$2200 ( + .A(\con$3452 ), + .Y(\c$3453 ) + ); + INVx1_ASAP7_75t_R \U$2201 ( + .A(\sn$3454 ), + .Y(\s$3455 ) + ); + INVx1_ASAP7_75t_R \U$2202 ( + .A(\con$3456 ), + .Y(\c$3457 ) + ); + INVx1_ASAP7_75t_R \U$2203 ( + .A(\sn$3458 ), + .Y(\s$3459 ) + ); + INVx1_ASAP7_75t_R \U$2204 ( + .A(\con$3460 ), + .Y(\c$3461 ) + ); + INVx1_ASAP7_75t_R \U$2205 ( + .A(\sn$3462 ), + .Y(\s$3463 ) + ); + INVx1_ASAP7_75t_R \U$2206 ( + .A(\con$3464 ), + .Y(\c$3465 ) + ); + INVx1_ASAP7_75t_R \U$2207 ( + .A(\sn$3466 ), + .Y(\s$3467 ) + ); + INVx1_ASAP7_75t_R \U$2208 ( + .A(\con$3468 ), + .Y(\c$3469 ) + ); + INVx1_ASAP7_75t_R \U$2209 ( + .A(\sn$3470 ), + .Y(\s$3471 ) + ); + INVx1_ASAP7_75t_R \U$2210 ( + .A(\con$3472 ), + .Y(\c$3473 ) + ); + INVx1_ASAP7_75t_R \U$2211 ( + .A(\sn$3474 ), + .Y(\s$3475 ) + ); + INVx1_ASAP7_75t_R \U$2212 ( + .A(\con$3476 ), + .Y(\c$3477 ) + ); + INVx1_ASAP7_75t_R \U$2213 ( + .A(\sn$3478 ), + .Y(\s$3479 ) + ); + INVx1_ASAP7_75t_R \U$2214 ( + .A(\con$3480 ), + .Y(\c$3481 ) + ); + INVx1_ASAP7_75t_R \U$2215 ( + .A(\sn$3482 ), + .Y(\s$3483 ) + ); + INVx1_ASAP7_75t_R \U$2216 ( + .A(\con$3484 ), + .Y(\c$3485 ) + ); + INVx1_ASAP7_75t_R \U$2217 ( + .A(\sn$3486 ), + .Y(\s$3487 ) + ); + INVx1_ASAP7_75t_R \U$2218 ( + .A(\con$3488 ), + .Y(\c$3489 ) + ); + INVx1_ASAP7_75t_R \U$2219 ( + .A(\sn$3490 ), + .Y(\s$3491 ) + ); + INVx1_ASAP7_75t_R \U$2220 ( + .A(\con$3492 ), + .Y(\c$3493 ) + ); + INVx1_ASAP7_75t_R \U$2221 ( + .A(\sn$3494 ), + .Y(\s$3495 ) + ); + INVx1_ASAP7_75t_R \U$2222 ( + .A(\con$3496 ), + .Y(\c$3497 ) + ); + INVx1_ASAP7_75t_R \U$2223 ( + .A(\sn$3498 ), + .Y(\s$3499 ) + ); + INVx1_ASAP7_75t_R \U$2224 ( + .A(\con$3500 ), + .Y(\c$3501 ) + ); + INVx1_ASAP7_75t_R \U$2225 ( + .A(\sn$3502 ), + .Y(\s$3503 ) + ); + INVx1_ASAP7_75t_R \U$2226 ( + .A(\con$3504 ), + .Y(\c$3505 ) + ); + INVx1_ASAP7_75t_R \U$2227 ( + .A(\sn$3506 ), + .Y(\s$3507 ) + ); + INVx1_ASAP7_75t_R \U$2228 ( + .A(\con$3508 ), + .Y(\c$3509 ) + ); + INVx1_ASAP7_75t_R \U$2229 ( + .A(\sn$3510 ), + .Y(\s$3511 ) + ); + INVx1_ASAP7_75t_R \U$2230 ( + .A(\con$3512 ), + .Y(\c$3513 ) + ); + INVx1_ASAP7_75t_R \U$2231 ( + .A(\sn$3514 ), + .Y(\s$3515 ) + ); + INVx1_ASAP7_75t_R \U$2232 ( + .A(\con$3516 ), + .Y(\c$3517 ) + ); + INVx1_ASAP7_75t_R \U$2233 ( + .A(\sn$3518 ), + .Y(\s$3519 ) + ); + INVx1_ASAP7_75t_R \U$2234 ( + .A(\con$3520 ), + .Y(\c$3521 ) + ); + INVx1_ASAP7_75t_R \U$2235 ( + .A(\sn$3522 ), + .Y(\s$3523 ) + ); + INVx1_ASAP7_75t_R \U$2236 ( + .A(\con$3524 ), + .Y(\c$3525 ) + ); + INVx1_ASAP7_75t_R \U$2237 ( + .A(\sn$3526 ), + .Y(\s$3527 ) + ); + INVx1_ASAP7_75t_R \U$2238 ( + .A(\con$3528 ), + .Y(\c$3529 ) + ); + INVx1_ASAP7_75t_R \U$2239 ( + .A(\sn$3530 ), + .Y(\s$3531 ) + ); + INVx1_ASAP7_75t_R \U$2240 ( + .A(\con$3532 ), + .Y(\c$3533 ) + ); + INVx1_ASAP7_75t_R \U$2241 ( + .A(\sn$3534 ), + .Y(\s$3535 ) + ); + INVx1_ASAP7_75t_R \U$2242 ( + .A(\con$3536 ), + .Y(\c$3537 ) + ); + INVx1_ASAP7_75t_R \U$2243 ( + .A(\sn$3538 ), + .Y(\s$3539 ) + ); + INVx1_ASAP7_75t_R \U$2244 ( + .A(\con$3540 ), + .Y(\c$3541 ) + ); + INVx1_ASAP7_75t_R \U$2245 ( + .A(\sn$3542 ), + .Y(\s$3543 ) + ); + INVx1_ASAP7_75t_R \U$2246 ( + .A(\con$3544 ), + .Y(\c$3545 ) + ); + INVx1_ASAP7_75t_R \U$2247 ( + .A(\sn$3546 ), + .Y(\s$3547 ) + ); + INVx1_ASAP7_75t_R \U$2248 ( + .A(\con$3548 ), + .Y(\c$3549 ) + ); + INVx1_ASAP7_75t_R \U$2249 ( + .A(\sn$3550 ), + .Y(\s$3551 ) + ); + INVx1_ASAP7_75t_R \U$2250 ( + .A(\con$3552 ), + .Y(\c$3553 ) + ); + INVx1_ASAP7_75t_R \U$2251 ( + .A(\sn$3554 ), + .Y(\s$3555 ) + ); + INVx1_ASAP7_75t_R \U$2252 ( + .A(\con$3556 ), + .Y(\c$3557 ) + ); + INVx1_ASAP7_75t_R \U$2253 ( + .A(\sn$3558 ), + .Y(\s$3559 ) + ); + INVx1_ASAP7_75t_R \U$2254 ( + .A(\con$3560 ), + .Y(\c$3561 ) + ); + INVx1_ASAP7_75t_R \U$2255 ( + .A(\sn$3562 ), + .Y(\s$3563 ) + ); + INVx1_ASAP7_75t_R \U$2256 ( + .A(\con$3564 ), + .Y(\c$3565 ) + ); + INVx1_ASAP7_75t_R \U$2257 ( + .A(\sn$3566 ), + .Y(\s$3567 ) + ); + INVx1_ASAP7_75t_R \U$2258 ( + .A(\con$3568 ), + .Y(\c$3569 ) + ); + INVx1_ASAP7_75t_R \U$2259 ( + .A(\sn$3570 ), + .Y(\s$3571 ) + ); + INVx1_ASAP7_75t_R \U$2260 ( + .A(\con$3572 ), + .Y(\c$3573 ) + ); + INVx1_ASAP7_75t_R \U$2261 ( + .A(\sn$3574 ), + .Y(\s$3575 ) + ); + INVx1_ASAP7_75t_R \U$2262 ( + .A(\con$3576 ), + .Y(\c$3577 ) + ); + INVx1_ASAP7_75t_R \U$2263 ( + .A(\sn$3578 ), + .Y(\s$3579 ) + ); + INVx1_ASAP7_75t_R \U$2264 ( + .A(\con$3580 ), + .Y(\c$3581 ) + ); + INVx1_ASAP7_75t_R \U$2265 ( + .A(\sn$3582 ), + .Y(\s$3583 ) + ); + INVx1_ASAP7_75t_R \U$2266 ( + .A(\con$3584 ), + .Y(\c$3585 ) + ); + INVx1_ASAP7_75t_R \U$2267 ( + .A(\sn$3586 ), + .Y(\s$3587 ) + ); + INVx1_ASAP7_75t_R \U$2268 ( + .A(\con$3588 ), + .Y(\c$3589 ) + ); + INVx1_ASAP7_75t_R \U$2269 ( + .A(\sn$3590 ), + .Y(\s$3591 ) + ); + INVx1_ASAP7_75t_R \U$2270 ( + .A(\con$3592 ), + .Y(\c$3593 ) + ); + INVx1_ASAP7_75t_R \U$2271 ( + .A(\sn$3594 ), + .Y(\s$3595 ) + ); + INVx1_ASAP7_75t_R \U$2272 ( + .A(\con$3596 ), + .Y(\c$3597 ) + ); + INVx1_ASAP7_75t_R \U$2273 ( + .A(\sn$3598 ), + .Y(\s$3599 ) + ); + INVx1_ASAP7_75t_R \U$2274 ( + .A(\con$3600 ), + .Y(\c$3601 ) + ); + INVx1_ASAP7_75t_R \U$2275 ( + .A(\sn$3602 ), + .Y(\s$3603 ) + ); + INVx1_ASAP7_75t_R \U$2276 ( + .A(\con$3604 ), + .Y(\c$3605 ) + ); + INVx1_ASAP7_75t_R \U$2277 ( + .A(\sn$3606 ), + .Y(\s$3607 ) + ); + INVx1_ASAP7_75t_R \U$2278 ( + .A(\con$3608 ), + .Y(\c$3609 ) + ); + INVx1_ASAP7_75t_R \U$2279 ( + .A(\sn$3610 ), + .Y(\s$3611 ) + ); + INVx1_ASAP7_75t_R \U$2280 ( + .A(\con$3612 ), + .Y(\c$3613 ) + ); + INVx1_ASAP7_75t_R \U$2281 ( + .A(\sn$3614 ), + .Y(\s$3615 ) + ); + INVx1_ASAP7_75t_R \U$2282 ( + .A(\con$3616 ), + .Y(\c$3617 ) + ); + INVx1_ASAP7_75t_R \U$2283 ( + .A(\sn$3618 ), + .Y(\s$3619 ) + ); + INVx1_ASAP7_75t_R \U$2284 ( + .A(\con$3620 ), + .Y(\c$3621 ) + ); + INVx1_ASAP7_75t_R \U$2285 ( + .A(\sn$3622 ), + .Y(\s$3623 ) + ); + INVx1_ASAP7_75t_R \U$2286 ( + .A(\con$3624 ), + .Y(\c$3625 ) + ); + INVx1_ASAP7_75t_R \U$2287 ( + .A(\sn$3626 ), + .Y(\s$3627 ) + ); + INVx1_ASAP7_75t_R \U$2288 ( + .A(\con$3628 ), + .Y(\c$3629 ) + ); + INVx1_ASAP7_75t_R \U$2289 ( + .A(\sn$3630 ), + .Y(\s$3631 ) + ); + INVx1_ASAP7_75t_R \U$2290 ( + .A(\con$3632 ), + .Y(\c$3633 ) + ); + INVx1_ASAP7_75t_R \U$2291 ( + .A(\sn$3634 ), + .Y(\s$3635 ) + ); + INVx1_ASAP7_75t_R \U$2292 ( + .A(\con$3636 ), + .Y(\c$3637 ) + ); + INVx1_ASAP7_75t_R \U$2293 ( + .A(\sn$3638 ), + .Y(\s$3639 ) + ); + INVx1_ASAP7_75t_R \U$2294 ( + .A(\con$3640 ), + .Y(\c$3641 ) + ); + INVx1_ASAP7_75t_R \U$2295 ( + .A(\sn$3642 ), + .Y(\s$3643 ) + ); + INVx1_ASAP7_75t_R \U$2296 ( + .A(\con$3644 ), + .Y(\c$3645 ) + ); + INVx1_ASAP7_75t_R \U$2297 ( + .A(\sn$3646 ), + .Y(\s$3647 ) + ); + INVx1_ASAP7_75t_R \U$2298 ( + .A(\con$3648 ), + .Y(\c$3649 ) + ); + INVx1_ASAP7_75t_R \U$2299 ( + .A(\sn$3650 ), + .Y(\s$3651 ) + ); + INVx1_ASAP7_75t_R \U$2300 ( + .A(\con$3652 ), + .Y(\c$3653 ) + ); + INVx1_ASAP7_75t_R \U$2301 ( + .A(\sn$3654 ), + .Y(\s$3655 ) + ); + INVx1_ASAP7_75t_R \U$2302 ( + .A(\con$3656 ), + .Y(\c$3657 ) + ); + INVx1_ASAP7_75t_R \U$2303 ( + .A(\sn$3658 ), + .Y(\s$3659 ) + ); + INVx1_ASAP7_75t_R \U$2304 ( + .A(\con$3660 ), + .Y(\c$3661 ) + ); + INVx1_ASAP7_75t_R \U$2305 ( + .A(\sn$3662 ), + .Y(\s$3663 ) + ); + INVx1_ASAP7_75t_R \U$2306 ( + .A(\con$3664 ), + .Y(\c$3665 ) + ); + INVx1_ASAP7_75t_R \U$2307 ( + .A(\sn$3666 ), + .Y(\s$3667 ) + ); + INVx1_ASAP7_75t_R \U$2308 ( + .A(\con$3668 ), + .Y(\c$3669 ) + ); + INVx1_ASAP7_75t_R \U$2309 ( + .A(\sn$3670 ), + .Y(\s$3671 ) + ); + INVx1_ASAP7_75t_R \U$2310 ( + .A(\con$3672 ), + .Y(\c$3673 ) + ); + INVx1_ASAP7_75t_R \U$2311 ( + .A(\sn$3674 ), + .Y(\s$3675 ) + ); + INVx1_ASAP7_75t_R \U$2312 ( + .A(\con$3676 ), + .Y(\c$3677 ) + ); + INVx1_ASAP7_75t_R \U$2313 ( + .A(\sn$3678 ), + .Y(\s$3679 ) + ); + INVx1_ASAP7_75t_R \U$2314 ( + .A(\con$3680 ), + .Y(\c$3681 ) + ); + INVx1_ASAP7_75t_R \U$2315 ( + .A(\sn$3682 ), + .Y(\s$3683 ) + ); + INVx1_ASAP7_75t_R \U$2316 ( + .A(\con$3684 ), + .Y(\c$3685 ) + ); + INVx1_ASAP7_75t_R \U$2317 ( + .A(\sn$3686 ), + .Y(\s$3687 ) + ); + INVx1_ASAP7_75t_R \U$2318 ( + .A(\con$3688 ), + .Y(\c$3689 ) + ); + INVx1_ASAP7_75t_R \U$2319 ( + .A(\sn$3690 ), + .Y(\s$3691 ) + ); + INVx1_ASAP7_75t_R \U$2320 ( + .A(\con$3692 ), + .Y(\c$3693 ) + ); + INVx1_ASAP7_75t_R \U$2321 ( + .A(\sn$3694 ), + .Y(\s$3695 ) + ); + INVx1_ASAP7_75t_R \U$2322 ( + .A(\con$3696 ), + .Y(\c$3697 ) + ); + INVx1_ASAP7_75t_R \U$2323 ( + .A(\sn$3698 ), + .Y(\s$3699 ) + ); + INVx1_ASAP7_75t_R \U$2324 ( + .A(\con$3700 ), + .Y(\c$3701 ) + ); + INVx1_ASAP7_75t_R \U$2325 ( + .A(\sn$3702 ), + .Y(\s$3703 ) + ); + INVx1_ASAP7_75t_R \U$2326 ( + .A(\con$3704 ), + .Y(\c$3705 ) + ); + INVx1_ASAP7_75t_R \U$2327 ( + .A(\sn$3706 ), + .Y(\s$3707 ) + ); + INVx1_ASAP7_75t_R \U$2328 ( + .A(\con$3708 ), + .Y(\c$3709 ) + ); + INVx1_ASAP7_75t_R \U$2329 ( + .A(\sn$3710 ), + .Y(\s$3711 ) + ); + INVx1_ASAP7_75t_R \U$2330 ( + .A(\con$3712 ), + .Y(\c$3713 ) + ); + INVx1_ASAP7_75t_R \U$2331 ( + .A(\sn$3714 ), + .Y(\s$3715 ) + ); + INVx1_ASAP7_75t_R \U$2332 ( + .A(\con$3716 ), + .Y(\c$3717 ) + ); + INVx1_ASAP7_75t_R \U$2333 ( + .A(\sn$3718 ), + .Y(\s$3719 ) + ); + INVx1_ASAP7_75t_R \U$2334 ( + .A(\con$3720 ), + .Y(\c$3721 ) + ); + INVx1_ASAP7_75t_R \U$2335 ( + .A(\sn$3722 ), + .Y(\s$3723 ) + ); + INVx1_ASAP7_75t_R \U$2336 ( + .A(\con$3724 ), + .Y(\c$3725 ) + ); + INVx1_ASAP7_75t_R \U$2337 ( + .A(\sn$3726 ), + .Y(\s$3727 ) + ); + INVx1_ASAP7_75t_R \U$2338 ( + .A(\con$3728 ), + .Y(\c$3729 ) + ); + INVx1_ASAP7_75t_R \U$2339 ( + .A(\sn$3730 ), + .Y(\s$3731 ) + ); + INVx1_ASAP7_75t_R \U$2340 ( + .A(\con$3732 ), + .Y(\c$3733 ) + ); + INVx1_ASAP7_75t_R \U$2341 ( + .A(\sn$3734 ), + .Y(\s$3735 ) + ); + INVx1_ASAP7_75t_R \U$2342 ( + .A(\con$3736 ), + .Y(\c$3737 ) + ); + INVx1_ASAP7_75t_R \U$2343 ( + .A(\sn$3738 ), + .Y(\s$3739 ) + ); + INVx1_ASAP7_75t_R \U$2344 ( + .A(\con$3740 ), + .Y(\c$3741 ) + ); + INVx1_ASAP7_75t_R \U$2345 ( + .A(\sn$3742 ), + .Y(\s$3743 ) + ); + INVx1_ASAP7_75t_R \U$2346 ( + .A(\con$3744 ), + .Y(\c$3745 ) + ); + INVx1_ASAP7_75t_R \U$2347 ( + .A(\sn$3746 ), + .Y(\s$3747 ) + ); + INVx1_ASAP7_75t_R \U$2348 ( + .A(\con$3748 ), + .Y(\c$3749 ) + ); + INVx1_ASAP7_75t_R \U$2349 ( + .A(\sn$3750 ), + .Y(\s$3751 ) + ); + INVx1_ASAP7_75t_R \U$2350 ( + .A(\con$3752 ), + .Y(\c$3753 ) + ); + INVx1_ASAP7_75t_R \U$2351 ( + .A(\sn$3754 ), + .Y(\s$3755 ) + ); + INVx1_ASAP7_75t_R \U$2352 ( + .A(\con$3756 ), + .Y(\c$3757 ) + ); + INVx1_ASAP7_75t_R \U$2353 ( + .A(\sn$3758 ), + .Y(\s$3759 ) + ); + INVx1_ASAP7_75t_R \U$2354 ( + .A(\con$3760 ), + .Y(\c$3761 ) + ); + INVx1_ASAP7_75t_R \U$2355 ( + .A(\sn$3762 ), + .Y(\s$3763 ) + ); + INVx1_ASAP7_75t_R \U$2356 ( + .A(\con$3764 ), + .Y(\c$3765 ) + ); + INVx1_ASAP7_75t_R \U$2357 ( + .A(\sn$3766 ), + .Y(\s$3767 ) + ); + INVx1_ASAP7_75t_R \U$2358 ( + .A(\con$3768 ), + .Y(\c$3769 ) + ); + INVx1_ASAP7_75t_R \U$2359 ( + .A(\sn$3770 ), + .Y(\s$3771 ) + ); + INVx1_ASAP7_75t_R \U$2360 ( + .A(\con$3772 ), + .Y(\c$3773 ) + ); + INVx1_ASAP7_75t_R \U$2361 ( + .A(\sn$3774 ), + .Y(\s$3775 ) + ); + INVx1_ASAP7_75t_R \U$2362 ( + .A(\con$3776 ), + .Y(\c$3777 ) + ); + INVx1_ASAP7_75t_R \U$2363 ( + .A(\sn$3778 ), + .Y(\s$3779 ) + ); + INVx1_ASAP7_75t_R \U$2364 ( + .A(\con$3780 ), + .Y(\c$3781 ) + ); + INVx1_ASAP7_75t_R \U$2365 ( + .A(\sn$3782 ), + .Y(\s$3783 ) + ); + INVx1_ASAP7_75t_R \U$2366 ( + .A(\con$3784 ), + .Y(\c$3785 ) + ); + INVx1_ASAP7_75t_R \U$2367 ( + .A(\sn$3786 ), + .Y(\s$3787 ) + ); + INVx1_ASAP7_75t_R \U$2368 ( + .A(\con$3788 ), + .Y(\c$3789 ) + ); + INVx1_ASAP7_75t_R \U$2369 ( + .A(\sn$3790 ), + .Y(\s$3791 ) + ); + INVx1_ASAP7_75t_R \U$2370 ( + .A(\con$3792 ), + .Y(\c$3793 ) + ); + INVx1_ASAP7_75t_R \U$2371 ( + .A(\sn$3794 ), + .Y(\s$3795 ) + ); + INVx1_ASAP7_75t_R \U$2372 ( + .A(\con$3796 ), + .Y(\c$3797 ) + ); + INVx1_ASAP7_75t_R \U$2373 ( + .A(\sn$3798 ), + .Y(\s$3799 ) + ); + INVx1_ASAP7_75t_R \U$2374 ( + .A(\con$3800 ), + .Y(\c$3801 ) + ); + INVx1_ASAP7_75t_R \U$2375 ( + .A(\sn$3802 ), + .Y(\s$3803 ) + ); + INVx1_ASAP7_75t_R \U$2376 ( + .A(\con$3804 ), + .Y(\c$3805 ) + ); + INVx1_ASAP7_75t_R \U$2377 ( + .A(\sn$3806 ), + .Y(\s$3807 ) + ); + INVx1_ASAP7_75t_R \U$2378 ( + .A(\con$3808 ), + .Y(\c$3809 ) + ); + INVx1_ASAP7_75t_R \U$2379 ( + .A(\sn$3810 ), + .Y(\s$3811 ) + ); + INVx1_ASAP7_75t_R \U$2380 ( + .A(\con$3812 ), + .Y(\c$3813 ) + ); + INVx1_ASAP7_75t_R \U$2381 ( + .A(\sn$3814 ), + .Y(\s$3815 ) + ); + INVx1_ASAP7_75t_R \U$2382 ( + .A(\con$3816 ), + .Y(\c$3817 ) + ); + INVx1_ASAP7_75t_R \U$2383 ( + .A(\sn$3818 ), + .Y(\s$3819 ) + ); + INVx1_ASAP7_75t_R \U$2384 ( + .A(\con$3820 ), + .Y(\c$3821 ) + ); + INVx1_ASAP7_75t_R \U$2385 ( + .A(\sn$3822 ), + .Y(\s$3823 ) + ); + INVx1_ASAP7_75t_R \U$2386 ( + .A(\con$3824 ), + .Y(\c$3825 ) + ); + INVx1_ASAP7_75t_R \U$2387 ( + .A(\sn$3826 ), + .Y(\s$3827 ) + ); + INVx1_ASAP7_75t_R \U$2388 ( + .A(\con$3828 ), + .Y(\c$3829 ) + ); + INVx1_ASAP7_75t_R \U$2389 ( + .A(\sn$3830 ), + .Y(\s$3831 ) + ); + INVx1_ASAP7_75t_R \U$2390 ( + .A(\con$3832 ), + .Y(\c$3833 ) + ); + INVx1_ASAP7_75t_R \U$2391 ( + .A(\sn$3834 ), + .Y(\s$3835 ) + ); + INVx1_ASAP7_75t_R \U$2392 ( + .A(\con$3836 ), + .Y(\c$3837 ) + ); + INVx1_ASAP7_75t_R \U$2393 ( + .A(\sn$3838 ), + .Y(\s$3839 ) + ); + INVx1_ASAP7_75t_R \U$2394 ( + .A(\con$3840 ), + .Y(\c$3841 ) + ); + INVx1_ASAP7_75t_R \U$2395 ( + .A(\sn$3842 ), + .Y(\s$3843 ) + ); + INVx1_ASAP7_75t_R \U$2396 ( + .A(\con$3844 ), + .Y(\c$3845 ) + ); + INVx1_ASAP7_75t_R \U$2397 ( + .A(\sn$3846 ), + .Y(\s$3847 ) + ); + INVx1_ASAP7_75t_R \U$2398 ( + .A(\con$3848 ), + .Y(\c$3849 ) + ); + INVx1_ASAP7_75t_R \U$2399 ( + .A(\sn$3850 ), + .Y(\s$3851 ) + ); + INVx1_ASAP7_75t_R \U$2400 ( + .A(\con$3852 ), + .Y(\c$3853 ) + ); + INVx1_ASAP7_75t_R \U$2401 ( + .A(\sn$3854 ), + .Y(\s$3855 ) + ); + INVx1_ASAP7_75t_R \U$2402 ( + .A(\con$3856 ), + .Y(\c$3857 ) + ); + INVx1_ASAP7_75t_R \U$2403 ( + .A(\sn$3858 ), + .Y(\s$3859 ) + ); + INVx1_ASAP7_75t_R \U$2404 ( + .A(\con$3860 ), + .Y(\c$3861 ) + ); + INVx1_ASAP7_75t_R \U$2405 ( + .A(\sn$3862 ), + .Y(\s$3863 ) + ); + INVx1_ASAP7_75t_R \U$2406 ( + .A(\con$3864 ), + .Y(\c$3865 ) + ); + INVx1_ASAP7_75t_R \U$2407 ( + .A(\sn$3866 ), + .Y(\s$3867 ) + ); + INVx1_ASAP7_75t_R \U$2408 ( + .A(\con$3868 ), + .Y(\c$3869 ) + ); + INVx1_ASAP7_75t_R \U$2409 ( + .A(\sn$3870 ), + .Y(\s$3871 ) + ); + INVx1_ASAP7_75t_R \U$2410 ( + .A(\con$3872 ), + .Y(\c$3873 ) + ); + INVx1_ASAP7_75t_R \U$2411 ( + .A(\sn$3874 ), + .Y(\s$3875 ) + ); + INVx1_ASAP7_75t_R \U$2412 ( + .A(\con$3876 ), + .Y(\c$3877 ) + ); + INVx1_ASAP7_75t_R \U$2413 ( + .A(\sn$3878 ), + .Y(\s$3879 ) + ); + INVx1_ASAP7_75t_R \U$2414 ( + .A(\con$3880 ), + .Y(\c$3881 ) + ); + INVx1_ASAP7_75t_R \U$2415 ( + .A(\sn$3882 ), + .Y(\s$3883 ) + ); + INVx1_ASAP7_75t_R \U$2416 ( + .A(\con$3884 ), + .Y(\c$3885 ) + ); + INVx1_ASAP7_75t_R \U$2417 ( + .A(\sn$3886 ), + .Y(\s$3887 ) + ); + INVx1_ASAP7_75t_R \U$2418 ( + .A(\con$3888 ), + .Y(\c$3889 ) + ); + INVx1_ASAP7_75t_R \U$2419 ( + .A(\sn$3890 ), + .Y(\s$3891 ) + ); + INVx1_ASAP7_75t_R \U$2420 ( + .A(\con$3892 ), + .Y(\c$3893 ) + ); + INVx1_ASAP7_75t_R \U$2421 ( + .A(\sn$3894 ), + .Y(\s$3895 ) + ); + INVx1_ASAP7_75t_R \U$2422 ( + .A(\con$3896 ), + .Y(\c$3897 ) + ); + INVx1_ASAP7_75t_R \U$2423 ( + .A(\sn$3898 ), + .Y(\s$3899 ) + ); + INVx1_ASAP7_75t_R \U$2424 ( + .A(\con$3900 ), + .Y(\c$3901 ) + ); + INVx1_ASAP7_75t_R \U$2425 ( + .A(\sn$3902 ), + .Y(\s$3903 ) + ); + INVx1_ASAP7_75t_R \U$2426 ( + .A(\con$3904 ), + .Y(\c$3905 ) + ); + INVx1_ASAP7_75t_R \U$2427 ( + .A(\sn$3906 ), + .Y(\s$3907 ) + ); + INVx1_ASAP7_75t_R \U$2428 ( + .A(\con$3908 ), + .Y(\c$3909 ) + ); + INVx1_ASAP7_75t_R \U$2429 ( + .A(\sn$3910 ), + .Y(\s$3911 ) + ); + INVx1_ASAP7_75t_R \U$2430 ( + .A(\con$3912 ), + .Y(\c$3913 ) + ); + INVx1_ASAP7_75t_R \U$2431 ( + .A(\sn$3914 ), + .Y(\s$3915 ) + ); + INVx1_ASAP7_75t_R \U$2432 ( + .A(\con$3916 ), + .Y(\c$3917 ) + ); + INVx1_ASAP7_75t_R \U$2433 ( + .A(\sn$3918 ), + .Y(\s$3919 ) + ); + INVx1_ASAP7_75t_R \U$2434 ( + .A(\con$3920 ), + .Y(\c$3921 ) + ); + INVx1_ASAP7_75t_R \U$2435 ( + .A(\sn$3922 ), + .Y(\s$3923 ) + ); + INVx1_ASAP7_75t_R \U$2436 ( + .A(\con$3924 ), + .Y(\c$3925 ) + ); + INVx1_ASAP7_75t_R \U$2437 ( + .A(\sn$3926 ), + .Y(\s$3927 ) + ); + INVx1_ASAP7_75t_R \U$2438 ( + .A(\con$3928 ), + .Y(\c$3929 ) + ); + INVx1_ASAP7_75t_R \U$2439 ( + .A(\sn$3930 ), + .Y(\s$3931 ) + ); + INVx1_ASAP7_75t_R \U$2440 ( + .A(\con$3932 ), + .Y(\c$3933 ) + ); + INVx1_ASAP7_75t_R \U$2441 ( + .A(\sn$3934 ), + .Y(\s$3935 ) + ); + INVx1_ASAP7_75t_R \U$2442 ( + .A(\con$3936 ), + .Y(\c$3937 ) + ); + INVx1_ASAP7_75t_R \U$2443 ( + .A(\sn$3938 ), + .Y(\s$3939 ) + ); + INVx1_ASAP7_75t_R \U$2444 ( + .A(\con$3940 ), + .Y(\c$3941 ) + ); + INVx1_ASAP7_75t_R \U$2445 ( + .A(\sn$3942 ), + .Y(\s$3943 ) + ); + INVx1_ASAP7_75t_R \U$2446 ( + .A(\con$3944 ), + .Y(\c$3945 ) + ); + INVx1_ASAP7_75t_R \U$2447 ( + .A(\sn$3946 ), + .Y(\s$3947 ) + ); + INVx1_ASAP7_75t_R \U$2448 ( + .A(\con$3948 ), + .Y(\c$3949 ) + ); + INVx1_ASAP7_75t_R \U$2449 ( + .A(\sn$3950 ), + .Y(\s$3951 ) + ); + INVx1_ASAP7_75t_R \U$2450 ( + .A(\con$3952 ), + .Y(\c$3953 ) + ); + INVx1_ASAP7_75t_R \U$2451 ( + .A(\sn$3954 ), + .Y(\s$3955 ) + ); + INVx1_ASAP7_75t_R \U$2452 ( + .A(\con$3956 ), + .Y(\c$3957 ) + ); + INVx1_ASAP7_75t_R \U$2453 ( + .A(\sn$3958 ), + .Y(\s$3959 ) + ); + INVx1_ASAP7_75t_R \U$2454 ( + .A(\con$3960 ), + .Y(\c$3961 ) + ); + INVx1_ASAP7_75t_R \U$2455 ( + .A(\sn$3962 ), + .Y(\s$3963 ) + ); + INVx1_ASAP7_75t_R \U$2456 ( + .A(\con$3964 ), + .Y(\c$3965 ) + ); + INVx1_ASAP7_75t_R \U$2457 ( + .A(\sn$3966 ), + .Y(\s$3967 ) + ); + INVx1_ASAP7_75t_R \U$2458 ( + .A(\con$3968 ), + .Y(\c$3969 ) + ); + INVx1_ASAP7_75t_R \U$2459 ( + .A(\sn$3970 ), + .Y(\s$3971 ) + ); + INVx1_ASAP7_75t_R \U$2460 ( + .A(\con$3972 ), + .Y(\c$3973 ) + ); + INVx1_ASAP7_75t_R \U$2461 ( + .A(\sn$3974 ), + .Y(\s$3975 ) + ); + INVx1_ASAP7_75t_R \U$2462 ( + .A(\con$3976 ), + .Y(\c$3977 ) + ); + INVx1_ASAP7_75t_R \U$2463 ( + .A(\sn$3978 ), + .Y(\s$3979 ) + ); + INVx1_ASAP7_75t_R \U$2464 ( + .A(\con$3980 ), + .Y(\c$3981 ) + ); + INVx1_ASAP7_75t_R \U$2465 ( + .A(\sn$3982 ), + .Y(\s$3983 ) + ); + INVx1_ASAP7_75t_R \U$2466 ( + .A(\con$3984 ), + .Y(\c$3985 ) + ); + INVx1_ASAP7_75t_R \U$2467 ( + .A(\sn$3986 ), + .Y(\s$3987 ) + ); + INVx1_ASAP7_75t_R \U$2468 ( + .A(\con$3988 ), + .Y(\c$3989 ) + ); + INVx1_ASAP7_75t_R \U$2469 ( + .A(\sn$3990 ), + .Y(\s$3991 ) + ); + INVx1_ASAP7_75t_R \U$2470 ( + .A(\con$3992 ), + .Y(\c$3993 ) + ); + INVx1_ASAP7_75t_R \U$2471 ( + .A(\sn$3994 ), + .Y(\s$3995 ) + ); + INVx1_ASAP7_75t_R \U$2472 ( + .A(\con$3996 ), + .Y(\c$3997 ) + ); + INVx1_ASAP7_75t_R \U$2473 ( + .A(\sn$3998 ), + .Y(\s$3999 ) + ); + INVx1_ASAP7_75t_R \U$2474 ( + .A(\con$4000 ), + .Y(\c$4001 ) + ); + INVx1_ASAP7_75t_R \U$2475 ( + .A(\sn$4002 ), + .Y(\s$4003 ) + ); + INVx1_ASAP7_75t_R \U$2476 ( + .A(\con$4004 ), + .Y(\c$4005 ) + ); + INVx1_ASAP7_75t_R \U$2477 ( + .A(\sn$4006 ), + .Y(\s$4007 ) + ); + INVx1_ASAP7_75t_R \U$2478 ( + .A(\con$4008 ), + .Y(\c$4009 ) + ); + INVx1_ASAP7_75t_R \U$2479 ( + .A(\sn$4010 ), + .Y(\s$4011 ) + ); + INVx1_ASAP7_75t_R \U$2480 ( + .A(\con$4012 ), + .Y(\c$4013 ) + ); + INVx1_ASAP7_75t_R \U$2481 ( + .A(\sn$4014 ), + .Y(\s$4015 ) + ); + INVx1_ASAP7_75t_R \U$2482 ( + .A(\con$4016 ), + .Y(\c$4017 ) + ); + INVx1_ASAP7_75t_R \U$2483 ( + .A(\sn$4018 ), + .Y(\s$4019 ) + ); + INVx1_ASAP7_75t_R \U$2484 ( + .A(\con$4020 ), + .Y(\c$4021 ) + ); + INVx1_ASAP7_75t_R \U$2485 ( + .A(\sn$4022 ), + .Y(\s$4023 ) + ); + INVx1_ASAP7_75t_R \U$2486 ( + .A(\con$4024 ), + .Y(\c$4025 ) + ); + INVx1_ASAP7_75t_R \U$2487 ( + .A(\sn$4026 ), + .Y(\s$4027 ) + ); + INVx1_ASAP7_75t_R \U$2488 ( + .A(\con$4028 ), + .Y(\c$4029 ) + ); + INVx1_ASAP7_75t_R \U$2489 ( + .A(\sn$4030 ), + .Y(\s$4031 ) + ); + INVx1_ASAP7_75t_R \U$2490 ( + .A(\con$4032 ), + .Y(\c$4033 ) + ); + INVx1_ASAP7_75t_R \U$2491 ( + .A(\sn$4034 ), + .Y(\s$4035 ) + ); + INVx1_ASAP7_75t_R \U$2492 ( + .A(\con$4036 ), + .Y(\c$4037 ) + ); + INVx1_ASAP7_75t_R \U$2493 ( + .A(\sn$4038 ), + .Y(\s$4039 ) + ); + INVx1_ASAP7_75t_R \U$2494 ( + .A(\con$4040 ), + .Y(\c$4041 ) + ); + INVx1_ASAP7_75t_R \U$2495 ( + .A(\sn$4042 ), + .Y(\s$4043 ) + ); + INVx1_ASAP7_75t_R \U$2496 ( + .A(\con$4044 ), + .Y(\c$4045 ) + ); + INVx1_ASAP7_75t_R \U$2497 ( + .A(\sn$4046 ), + .Y(\s$4047 ) + ); + INVx1_ASAP7_75t_R \U$2498 ( + .A(\con$4048 ), + .Y(\c$4049 ) + ); + INVx1_ASAP7_75t_R \U$2499 ( + .A(\sn$4050 ), + .Y(\s$4051 ) + ); + INVx1_ASAP7_75t_R \U$2500 ( + .A(\con$4052 ), + .Y(\c$4053 ) + ); + INVx1_ASAP7_75t_R \U$2501 ( + .A(\sn$4054 ), + .Y(\s$4055 ) + ); + INVx1_ASAP7_75t_R \U$2502 ( + .A(\con$4056 ), + .Y(\c$4057 ) + ); + INVx1_ASAP7_75t_R \U$2503 ( + .A(\sn$4058 ), + .Y(\s$4059 ) + ); + INVx1_ASAP7_75t_R \U$2504 ( + .A(\con$4060 ), + .Y(\c$4061 ) + ); + INVx1_ASAP7_75t_R \U$2505 ( + .A(\sn$4062 ), + .Y(\s$4063 ) + ); + INVx1_ASAP7_75t_R \U$2506 ( + .A(\con$4064 ), + .Y(\c$4065 ) + ); + INVx1_ASAP7_75t_R \U$2507 ( + .A(\sn$4066 ), + .Y(\s$4067 ) + ); + INVx1_ASAP7_75t_R \U$2508 ( + .A(\con$4068 ), + .Y(\c$4069 ) + ); + INVx1_ASAP7_75t_R \U$2509 ( + .A(\sn$4070 ), + .Y(\s$4071 ) + ); + INVx1_ASAP7_75t_R \U$2510 ( + .A(\con$4072 ), + .Y(\c$4073 ) + ); + INVx1_ASAP7_75t_R \U$2511 ( + .A(\sn$4074 ), + .Y(\s$4075 ) + ); + INVx1_ASAP7_75t_R \U$2512 ( + .A(\con$4076 ), + .Y(\c$4077 ) + ); + INVx1_ASAP7_75t_R \U$2513 ( + .A(\sn$4078 ), + .Y(\s$4079 ) + ); + INVx1_ASAP7_75t_R \U$2514 ( + .A(\con$4080 ), + .Y(\c$4081 ) + ); + INVx1_ASAP7_75t_R \U$2515 ( + .A(\sn$4082 ), + .Y(\s$4083 ) + ); + INVx1_ASAP7_75t_R \U$2516 ( + .A(\con$4084 ), + .Y(\c$4085 ) + ); + INVx1_ASAP7_75t_R \U$2517 ( + .A(\sn$4086 ), + .Y(\s$4087 ) + ); + INVx1_ASAP7_75t_R \U$2518 ( + .A(\con$4088 ), + .Y(\c$4089 ) + ); + INVx1_ASAP7_75t_R \U$2519 ( + .A(\sn$4090 ), + .Y(\s$4091 ) + ); + INVx1_ASAP7_75t_R \U$2520 ( + .A(\con$4092 ), + .Y(\c$4093 ) + ); + INVx1_ASAP7_75t_R \U$2521 ( + .A(\sn$4094 ), + .Y(\s$4095 ) + ); + INVx1_ASAP7_75t_R \U$2522 ( + .A(\con$4096 ), + .Y(\c$4097 ) + ); + INVx1_ASAP7_75t_R \U$2523 ( + .A(\sn$4098 ), + .Y(\s$4099 ) + ); + INVx1_ASAP7_75t_R \U$2524 ( + .A(\con$4100 ), + .Y(\c$4101 ) + ); + INVx1_ASAP7_75t_R \U$2525 ( + .A(\sn$4102 ), + .Y(\s$4103 ) + ); + INVx1_ASAP7_75t_R \U$2526 ( + .A(\con$4104 ), + .Y(\c$4105 ) + ); + INVx1_ASAP7_75t_R \U$2527 ( + .A(\sn$4106 ), + .Y(\s$4107 ) + ); + INVx1_ASAP7_75t_R \U$2528 ( + .A(\con$4108 ), + .Y(\c$4109 ) + ); + INVx1_ASAP7_75t_R \U$2529 ( + .A(\sn$4110 ), + .Y(\s$4111 ) + ); + INVx1_ASAP7_75t_R \U$2530 ( + .A(\con$4112 ), + .Y(\c$4113 ) + ); + INVx1_ASAP7_75t_R \U$2531 ( + .A(\sn$4114 ), + .Y(\s$4115 ) + ); + INVx1_ASAP7_75t_R \U$2532 ( + .A(\con$4116 ), + .Y(\c$4117 ) + ); + INVx1_ASAP7_75t_R \U$2533 ( + .A(\sn$4118 ), + .Y(\s$4119 ) + ); + INVx1_ASAP7_75t_R \U$2534 ( + .A(\con$4120 ), + .Y(\c$4121 ) + ); + INVx1_ASAP7_75t_R \U$2535 ( + .A(\sn$4122 ), + .Y(\s$4123 ) + ); + INVx1_ASAP7_75t_R \U$2536 ( + .A(\con$4124 ), + .Y(\c$4125 ) + ); + INVx1_ASAP7_75t_R \U$2537 ( + .A(\sn$4126 ), + .Y(\s$4127 ) + ); + INVx1_ASAP7_75t_R \U$2538 ( + .A(\con$4128 ), + .Y(\c$4129 ) + ); + INVx1_ASAP7_75t_R \U$2539 ( + .A(\sn$4130 ), + .Y(\s$4131 ) + ); + INVx1_ASAP7_75t_R \U$2540 ( + .A(\con$4132 ), + .Y(\c$4133 ) + ); + INVx1_ASAP7_75t_R \U$2541 ( + .A(\sn$4134 ), + .Y(\s$4135 ) + ); + INVx1_ASAP7_75t_R \U$2542 ( + .A(\con$4136 ), + .Y(\c$4137 ) + ); + INVx1_ASAP7_75t_R \U$2543 ( + .A(\sn$4138 ), + .Y(\s$4139 ) + ); + INVx1_ASAP7_75t_R \U$2544 ( + .A(\con$4140 ), + .Y(\c$4141 ) + ); + INVx1_ASAP7_75t_R \U$2545 ( + .A(\sn$4142 ), + .Y(\s$4143 ) + ); + INVx1_ASAP7_75t_R \U$2546 ( + .A(\con$4144 ), + .Y(\c$4145 ) + ); + INVx1_ASAP7_75t_R \U$2547 ( + .A(\sn$4146 ), + .Y(\s$4147 ) + ); + INVx1_ASAP7_75t_R \U$2548 ( + .A(\con$4148 ), + .Y(\c$4149 ) + ); + INVx1_ASAP7_75t_R \U$2549 ( + .A(\sn$4150 ), + .Y(\s$4151 ) + ); + INVx1_ASAP7_75t_R \U$2550 ( + .A(\con$4152 ), + .Y(\c$4153 ) + ); + INVx1_ASAP7_75t_R \U$2551 ( + .A(\sn$4154 ), + .Y(\s$4155 ) + ); + INVx1_ASAP7_75t_R \U$2552 ( + .A(\con$4156 ), + .Y(\c$4157 ) + ); + INVx1_ASAP7_75t_R \U$2553 ( + .A(\sn$4158 ), + .Y(\s$4159 ) + ); + INVx1_ASAP7_75t_R \U$2554 ( + .A(\con$4160 ), + .Y(\c$4161 ) + ); + INVx1_ASAP7_75t_R \U$2555 ( + .A(\sn$4162 ), + .Y(\s$4163 ) + ); + INVx1_ASAP7_75t_R \U$2556 ( + .A(\con$4164 ), + .Y(\c$4165 ) + ); + INVx1_ASAP7_75t_R \U$2557 ( + .A(\sn$4166 ), + .Y(\s$4167 ) + ); + INVx1_ASAP7_75t_R \U$2558 ( + .A(\con$4168 ), + .Y(\c$4169 ) + ); + INVx1_ASAP7_75t_R \U$2559 ( + .A(\sn$4170 ), + .Y(\s$4171 ) + ); + INVx1_ASAP7_75t_R \U$2560 ( + .A(\con$4172 ), + .Y(\c$4173 ) + ); + INVx1_ASAP7_75t_R \U$2561 ( + .A(\sn$4174 ), + .Y(\s$4175 ) + ); + INVx1_ASAP7_75t_R \U$2562 ( + .A(\con$4176 ), + .Y(\c$4177 ) + ); + INVx1_ASAP7_75t_R \U$2563 ( + .A(\sn$4178 ), + .Y(\s$4179 ) + ); + INVx1_ASAP7_75t_R \U$2564 ( + .A(\con$4180 ), + .Y(\c$4181 ) + ); + INVx1_ASAP7_75t_R \U$2565 ( + .A(\sn$4182 ), + .Y(\s$4183 ) + ); + INVx1_ASAP7_75t_R \U$2566 ( + .A(\con$4184 ), + .Y(\c$4185 ) + ); + INVx1_ASAP7_75t_R \U$2567 ( + .A(\sn$4186 ), + .Y(\s$4187 ) + ); + INVx1_ASAP7_75t_R \U$2568 ( + .A(\con$4188 ), + .Y(\c$4189 ) + ); + INVx1_ASAP7_75t_R \U$2569 ( + .A(\sn$4190 ), + .Y(\s$4191 ) + ); + INVx1_ASAP7_75t_R \U$2570 ( + .A(\con$4192 ), + .Y(\c$4193 ) + ); + INVx1_ASAP7_75t_R \U$2571 ( + .A(\sn$4194 ), + .Y(\s$4195 ) + ); + INVx1_ASAP7_75t_R \U$2572 ( + .A(\con$4196 ), + .Y(\c$4197 ) + ); + INVx1_ASAP7_75t_R \U$2573 ( + .A(\sn$4198 ), + .Y(\s$4199 ) + ); + INVx1_ASAP7_75t_R \U$2574 ( + .A(\con$4200 ), + .Y(\c$4201 ) + ); + INVx1_ASAP7_75t_R \U$2575 ( + .A(\sn$4202 ), + .Y(\s$4203 ) + ); + INVx1_ASAP7_75t_R \U$2576 ( + .A(\con$4204 ), + .Y(\c$4205 ) + ); + INVx1_ASAP7_75t_R \U$2577 ( + .A(\sn$4206 ), + .Y(\s$4207 ) + ); + INVx1_ASAP7_75t_R \U$2578 ( + .A(\con$4208 ), + .Y(\c$4209 ) + ); + INVx1_ASAP7_75t_R \U$2579 ( + .A(\sn$4210 ), + .Y(\s$4211 ) + ); + INVx1_ASAP7_75t_R \U$2580 ( + .A(\con$4212 ), + .Y(\c$4213 ) + ); + INVx1_ASAP7_75t_R \U$2581 ( + .A(\sn$4214 ), + .Y(\s$4215 ) + ); + INVx1_ASAP7_75t_R \U$2582 ( + .A(\con$4216 ), + .Y(\c$4217 ) + ); + INVx1_ASAP7_75t_R \U$2583 ( + .A(\sn$4218 ), + .Y(\s$4219 ) + ); + INVx1_ASAP7_75t_R \U$2584 ( + .A(\con$4220 ), + .Y(\c$4221 ) + ); + INVx1_ASAP7_75t_R \U$2585 ( + .A(\sn$4222 ), + .Y(\s$4223 ) + ); + INVx1_ASAP7_75t_R \U$2586 ( + .A(\con$4224 ), + .Y(\c$4225 ) + ); + INVx1_ASAP7_75t_R \U$2587 ( + .A(\sn$4226 ), + .Y(\s$4227 ) + ); + INVx1_ASAP7_75t_R \U$2588 ( + .A(\con$4228 ), + .Y(\c$4229 ) + ); + INVx1_ASAP7_75t_R \U$2589 ( + .A(\sn$4230 ), + .Y(\s$4231 ) + ); + INVx1_ASAP7_75t_R \U$2590 ( + .A(\con$4232 ), + .Y(\c$4233 ) + ); + INVx1_ASAP7_75t_R \U$2591 ( + .A(\sn$4234 ), + .Y(\s$4235 ) + ); + INVx1_ASAP7_75t_R \U$2592 ( + .A(\con$4236 ), + .Y(\c$4237 ) + ); + INVx1_ASAP7_75t_R \U$2593 ( + .A(\sn$4238 ), + .Y(\s$4239 ) + ); + INVx1_ASAP7_75t_R \U$2594 ( + .A(\con$4240 ), + .Y(\c$4241 ) + ); + INVx1_ASAP7_75t_R \U$2595 ( + .A(\sn$4242 ), + .Y(\s$4243 ) + ); + INVx1_ASAP7_75t_R \U$2596 ( + .A(\con$4244 ), + .Y(\c$4245 ) + ); + INVx1_ASAP7_75t_R \U$2597 ( + .A(\sn$4246 ), + .Y(\s$4247 ) + ); + INVx1_ASAP7_75t_R \U$2598 ( + .A(\con$4248 ), + .Y(\c$4249 ) + ); + INVx1_ASAP7_75t_R \U$2599 ( + .A(\sn$4250 ), + .Y(\s$4251 ) + ); + INVx1_ASAP7_75t_R \U$2600 ( + .A(\con$4252 ), + .Y(\c$4253 ) + ); + INVx1_ASAP7_75t_R \U$2601 ( + .A(\sn$4254 ), + .Y(\s$4255 ) + ); + INVx1_ASAP7_75t_R \U$2602 ( + .A(\con$4256 ), + .Y(\c$4257 ) + ); + INVx1_ASAP7_75t_R \U$2603 ( + .A(\sn$4258 ), + .Y(\s$4259 ) + ); + INVx1_ASAP7_75t_R \U$2604 ( + .A(\con$4260 ), + .Y(\c$4261 ) + ); + INVx1_ASAP7_75t_R \U$2605 ( + .A(\sn$4262 ), + .Y(\s$4263 ) + ); + INVx1_ASAP7_75t_R \U$2606 ( + .A(\con$4264 ), + .Y(\c$4265 ) + ); + INVx1_ASAP7_75t_R \U$2607 ( + .A(\sn$4266 ), + .Y(\s$4267 ) + ); + INVx1_ASAP7_75t_R \U$2608 ( + .A(\con$4268 ), + .Y(\c$4269 ) + ); + INVx1_ASAP7_75t_R \U$2609 ( + .A(\sn$4270 ), + .Y(\s$4271 ) + ); + INVx1_ASAP7_75t_R \U$2610 ( + .A(\con$4272 ), + .Y(\c$4273 ) + ); + INVx1_ASAP7_75t_R \U$2611 ( + .A(\sn$4274 ), + .Y(\s$4275 ) + ); + INVx1_ASAP7_75t_R \U$2612 ( + .A(\con$4276 ), + .Y(\c$4277 ) + ); + INVx1_ASAP7_75t_R \U$2613 ( + .A(\sn$4278 ), + .Y(\s$4279 ) + ); + INVx1_ASAP7_75t_R \U$2614 ( + .A(\con$4280 ), + .Y(\c$4281 ) + ); + INVx1_ASAP7_75t_R \U$2615 ( + .A(\sn$4282 ), + .Y(\s$4283 ) + ); + INVx1_ASAP7_75t_R \U$2616 ( + .A(\con$4284 ), + .Y(\c$4285 ) + ); + INVx1_ASAP7_75t_R \U$2617 ( + .A(\sn$4286 ), + .Y(\s$4287 ) + ); + INVx1_ASAP7_75t_R \U$2618 ( + .A(\con$4288 ), + .Y(\c$4289 ) + ); + INVx1_ASAP7_75t_R \U$2619 ( + .A(\sn$4290 ), + .Y(\s$4291 ) + ); + INVx1_ASAP7_75t_R \U$2620 ( + .A(\con$4292 ), + .Y(\c$4293 ) + ); + INVx1_ASAP7_75t_R \U$2621 ( + .A(\sn$4294 ), + .Y(\s$4295 ) + ); + INVx1_ASAP7_75t_R \U$2622 ( + .A(\con$4296 ), + .Y(\c$4297 ) + ); + INVx1_ASAP7_75t_R \U$2623 ( + .A(\sn$4298 ), + .Y(\s$4299 ) + ); + INVx1_ASAP7_75t_R \U$2624 ( + .A(\con$4300 ), + .Y(\c$4301 ) + ); + INVx1_ASAP7_75t_R \U$2625 ( + .A(\sn$4302 ), + .Y(\s$4303 ) + ); + INVx1_ASAP7_75t_R \U$2626 ( + .A(\con$4304 ), + .Y(\c$4305 ) + ); + INVx1_ASAP7_75t_R \U$2627 ( + .A(\sn$4306 ), + .Y(\s$4307 ) + ); + INVx1_ASAP7_75t_R \U$2628 ( + .A(\con$4308 ), + .Y(\c$4309 ) + ); + INVx1_ASAP7_75t_R \U$2629 ( + .A(\sn$4310 ), + .Y(\s$4311 ) + ); + INVx1_ASAP7_75t_R \U$2630 ( + .A(\con$4312 ), + .Y(\c$4313 ) + ); + INVx1_ASAP7_75t_R \U$2631 ( + .A(\sn$4314 ), + .Y(\s$4315 ) + ); + INVx1_ASAP7_75t_R \U$2632 ( + .A(\con$4316 ), + .Y(\c$4317 ) + ); + INVx1_ASAP7_75t_R \U$2633 ( + .A(\sn$4318 ), + .Y(\s$4319 ) + ); + INVx1_ASAP7_75t_R \U$2634 ( + .A(\con$4320 ), + .Y(\c$4321 ) + ); + INVx1_ASAP7_75t_R \U$2635 ( + .A(\sn$4322 ), + .Y(\s$4323 ) + ); + INVx1_ASAP7_75t_R \U$2636 ( + .A(\con$4324 ), + .Y(\c$4325 ) + ); + INVx1_ASAP7_75t_R \U$2637 ( + .A(\sn$4326 ), + .Y(\s$4327 ) + ); + INVx1_ASAP7_75t_R \U$2638 ( + .A(\con$4328 ), + .Y(\c$4329 ) + ); + INVx1_ASAP7_75t_R \U$2639 ( + .A(\sn$4330 ), + .Y(\s$4331 ) + ); + INVx1_ASAP7_75t_R \U$2640 ( + .A(\con$4332 ), + .Y(\c$4333 ) + ); + INVx1_ASAP7_75t_R \U$2641 ( + .A(\sn$4334 ), + .Y(\s$4335 ) + ); + INVx1_ASAP7_75t_R \U$2642 ( + .A(\con$4336 ), + .Y(\c$4337 ) + ); + INVx1_ASAP7_75t_R \U$2643 ( + .A(\sn$4338 ), + .Y(\s$4339 ) + ); + INVx1_ASAP7_75t_R \U$2644 ( + .A(\con$4340 ), + .Y(\c$4341 ) + ); + INVx1_ASAP7_75t_R \U$2645 ( + .A(\sn$4342 ), + .Y(\s$4343 ) + ); + INVx1_ASAP7_75t_R \U$2646 ( + .A(\con$4344 ), + .Y(\c$4345 ) + ); + INVx1_ASAP7_75t_R \U$2647 ( + .A(\sn$4346 ), + .Y(\s$4347 ) + ); + INVx1_ASAP7_75t_R \U$2648 ( + .A(\con$4348 ), + .Y(\c$4349 ) + ); + INVx1_ASAP7_75t_R \U$2649 ( + .A(\sn$4350 ), + .Y(\s$4351 ) + ); + INVx1_ASAP7_75t_R \U$2650 ( + .A(\con$4352 ), + .Y(\c$4353 ) + ); + INVx1_ASAP7_75t_R \U$2651 ( + .A(\sn$4354 ), + .Y(\s$4355 ) + ); + INVx1_ASAP7_75t_R \U$2652 ( + .A(\con$4356 ), + .Y(\c$4357 ) + ); + INVx1_ASAP7_75t_R \U$2653 ( + .A(\sn$4358 ), + .Y(\s$4359 ) + ); + INVx1_ASAP7_75t_R \U$2654 ( + .A(\con$4360 ), + .Y(\c$4361 ) + ); + INVx1_ASAP7_75t_R \U$2655 ( + .A(\sn$4362 ), + .Y(\s$4363 ) + ); + INVx1_ASAP7_75t_R \U$2656 ( + .A(\con$4364 ), + .Y(\c$4365 ) + ); + INVx1_ASAP7_75t_R \U$2657 ( + .A(\sn$4366 ), + .Y(\s$4367 ) + ); + INVx1_ASAP7_75t_R \U$2658 ( + .A(\con$4368 ), + .Y(\c$4369 ) + ); + INVx1_ASAP7_75t_R \U$2659 ( + .A(\sn$4370 ), + .Y(\s$4371 ) + ); + INVx1_ASAP7_75t_R \U$2660 ( + .A(\con$4372 ), + .Y(\c$4373 ) + ); + INVx1_ASAP7_75t_R \U$2661 ( + .A(\sn$4374 ), + .Y(\s$4375 ) + ); + INVx1_ASAP7_75t_R \U$2662 ( + .A(\con$4376 ), + .Y(\c$4377 ) + ); + INVx1_ASAP7_75t_R \U$2663 ( + .A(\sn$4378 ), + .Y(\s$4379 ) + ); + INVx1_ASAP7_75t_R \U$2664 ( + .A(\con$4380 ), + .Y(\c$4381 ) + ); + INVx1_ASAP7_75t_R \U$2665 ( + .A(\sn$4382 ), + .Y(\s$4383 ) + ); + INVx1_ASAP7_75t_R \U$2666 ( + .A(\con$4384 ), + .Y(\c$4385 ) + ); + INVx1_ASAP7_75t_R \U$2667 ( + .A(\sn$4386 ), + .Y(\s$4387 ) + ); + INVx1_ASAP7_75t_R \U$2668 ( + .A(\con$4388 ), + .Y(\c$4389 ) + ); + INVx1_ASAP7_75t_R \U$2669 ( + .A(\sn$4390 ), + .Y(\s$4391 ) + ); + INVx1_ASAP7_75t_R \U$2670 ( + .A(\con$4392 ), + .Y(\c$4393 ) + ); + INVx1_ASAP7_75t_R \U$2671 ( + .A(\sn$4394 ), + .Y(\s$4395 ) + ); + INVx1_ASAP7_75t_R \U$2672 ( + .A(\con$4396 ), + .Y(\c$4397 ) + ); + INVx1_ASAP7_75t_R \U$2673 ( + .A(\sn$4398 ), + .Y(\s$4399 ) + ); + INVx1_ASAP7_75t_R \U$2674 ( + .A(\con$4400 ), + .Y(c) + ); + INVx1_ASAP7_75t_R \U$2675 ( + .A(\sn$4401 ), + .Y(s) + ); + INVx1_ASAP7_75t_R \U$2676 ( + .A(\con$4402 ), + .Y(\c$1197 ) + ); + INVx1_ASAP7_75t_R \U$2677 ( + .A(\sn$4403 ), + .Y(\s$1260 ) + ); + INVx1_ASAP7_75t_R \U$2678 ( + .A(\con$4404 ), + .Y(\c$1198 ) + ); + INVx1_ASAP7_75t_R \U$2679 ( + .A(\sn$4405 ), + .Y(\s$1261 ) + ); + INVx1_ASAP7_75t_R \U$2680 ( + .A(\con$4406 ), + .Y(\c$1199 ) + ); + INVx1_ASAP7_75t_R \U$2681 ( + .A(\sn$4407 ), + .Y(\s$1262 ) + ); + INVx1_ASAP7_75t_R \U$2682 ( + .A(\con$4408 ), + .Y(\c$1200 ) + ); + INVx1_ASAP7_75t_R \U$2683 ( + .A(\sn$4409 ), + .Y(\s$1263 ) + ); + INVx1_ASAP7_75t_R \U$2684 ( + .A(\con$4410 ), + .Y(\c$1201 ) + ); + INVx1_ASAP7_75t_R \U$2685 ( + .A(\sn$4411 ), + .Y(\s$1264 ) + ); + INVx1_ASAP7_75t_R \U$2686 ( + .A(\con$4412 ), + .Y(\c$1202 ) + ); + INVx1_ASAP7_75t_R \U$2687 ( + .A(\sn$4413 ), + .Y(\s$1265 ) + ); + INVx1_ASAP7_75t_R \U$2688 ( + .A(\con$4414 ), + .Y(\c$1203 ) + ); + INVx1_ASAP7_75t_R \U$2689 ( + .A(\sn$4415 ), + .Y(\s$1266 ) + ); + INVx1_ASAP7_75t_R \U$2690 ( + .A(\con$4416 ), + .Y(\c$1204 ) + ); + INVx1_ASAP7_75t_R \U$2691 ( + .A(\sn$4417 ), + .Y(\s$1267 ) + ); + INVx1_ASAP7_75t_R \U$2692 ( + .A(\con$4418 ), + .Y(\c$1205 ) + ); + INVx1_ASAP7_75t_R \U$2693 ( + .A(\sn$4419 ), + .Y(\s$1268 ) + ); + INVx1_ASAP7_75t_R \U$2694 ( + .A(\con$4420 ), + .Y(\c$1206 ) + ); + INVx1_ASAP7_75t_R \U$2695 ( + .A(\sn$4421 ), + .Y(\s$1269 ) + ); + INVx1_ASAP7_75t_R \U$2696 ( + .A(\con$4422 ), + .Y(\c$1207 ) + ); + INVx1_ASAP7_75t_R \U$2697 ( + .A(\sn$4423 ), + .Y(\s$1270 ) + ); + INVx1_ASAP7_75t_R \U$2698 ( + .A(\con$4424 ), + .Y(\c$1208 ) + ); + INVx1_ASAP7_75t_R \U$2699 ( + .A(\sn$4425 ), + .Y(\s$1271 ) + ); + INVx1_ASAP7_75t_R \U$2700 ( + .A(\con$4426 ), + .Y(\c$1209 ) + ); + INVx1_ASAP7_75t_R \U$2701 ( + .A(\sn$4427 ), + .Y(\s$1272 ) + ); + INVx1_ASAP7_75t_R \U$2702 ( + .A(\con$4428 ), + .Y(\c$1210 ) + ); + INVx1_ASAP7_75t_R \U$2703 ( + .A(\sn$4429 ), + .Y(\s$1273 ) + ); + INVx1_ASAP7_75t_R \U$2704 ( + .A(\con$4430 ), + .Y(\c$1211 ) + ); + INVx1_ASAP7_75t_R \U$2705 ( + .A(\sn$4431 ), + .Y(\s$1274 ) + ); + INVx1_ASAP7_75t_R \U$2706 ( + .A(\con$4432 ), + .Y(\c$1212 ) + ); + INVx1_ASAP7_75t_R \U$2707 ( + .A(\sn$4433 ), + .Y(\s$1275 ) + ); + INVx1_ASAP7_75t_R \U$2708 ( + .A(\con$4434 ), + .Y(\c$1213 ) + ); + INVx1_ASAP7_75t_R \U$2709 ( + .A(\sn$4435 ), + .Y(\s$1276 ) + ); + INVx1_ASAP7_75t_R \U$2710 ( + .A(\con$4436 ), + .Y(\c$1214 ) + ); + INVx1_ASAP7_75t_R \U$2711 ( + .A(\sn$4437 ), + .Y(\s$1277 ) + ); + INVx1_ASAP7_75t_R \U$2712 ( + .A(\con$4438 ), + .Y(\c$1215 ) + ); + INVx1_ASAP7_75t_R \U$2713 ( + .A(\sn$4439 ), + .Y(\s$1278 ) + ); + INVx1_ASAP7_75t_R \U$2714 ( + .A(\con$4440 ), + .Y(\c$1216 ) + ); + INVx1_ASAP7_75t_R \U$2715 ( + .A(\sn$4441 ), + .Y(\s$1279 ) + ); + INVx1_ASAP7_75t_R \U$2716 ( + .A(\con$4442 ), + .Y(\c$1217 ) + ); + INVx1_ASAP7_75t_R \U$2717 ( + .A(\sn$4443 ), + .Y(\s$1280 ) + ); + INVx1_ASAP7_75t_R \U$2718 ( + .A(\con$4444 ), + .Y(\c$1218 ) + ); + INVx1_ASAP7_75t_R \U$2719 ( + .A(\sn$4445 ), + .Y(\s$1281 ) + ); + INVx1_ASAP7_75t_R \U$2720 ( + .A(\con$4446 ), + .Y(\c$1219 ) + ); + INVx1_ASAP7_75t_R \U$2721 ( + .A(\sn$4447 ), + .Y(\s$1282 ) + ); + INVx1_ASAP7_75t_R \U$2722 ( + .A(\con$4448 ), + .Y(\c$1220 ) + ); + INVx1_ASAP7_75t_R \U$2723 ( + .A(\sn$4449 ), + .Y(\s$1283 ) + ); + INVx1_ASAP7_75t_R \U$2724 ( + .A(\con$4450 ), + .Y(\c$1221 ) + ); + INVx1_ASAP7_75t_R \U$2725 ( + .A(\sn$4451 ), + .Y(\s$1284 ) + ); + INVx1_ASAP7_75t_R \U$2726 ( + .A(\con$4452 ), + .Y(\c$1222 ) + ); + INVx1_ASAP7_75t_R \U$2727 ( + .A(\sn$4453 ), + .Y(\s$1285 ) + ); + INVx1_ASAP7_75t_R \U$2728 ( + .A(\con$4454 ), + .Y(\c$1223 ) + ); + INVx1_ASAP7_75t_R \U$2729 ( + .A(\sn$4455 ), + .Y(\s$1286 ) + ); + INVx1_ASAP7_75t_R \U$2730 ( + .A(\con$4456 ), + .Y(\c$1224 ) + ); + INVx1_ASAP7_75t_R \U$2731 ( + .A(\sn$4457 ), + .Y(\s$1287 ) + ); + INVx1_ASAP7_75t_R \U$2732 ( + .A(\con$4458 ), + .Y(\c$1225 ) + ); + INVx1_ASAP7_75t_R \U$2733 ( + .A(\sn$4459 ), + .Y(\s$1288 ) + ); + INVx1_ASAP7_75t_R \U$2734 ( + .A(\con$4460 ), + .Y(\c$1226 ) + ); + INVx1_ASAP7_75t_R \U$2735 ( + .A(\sn$4461 ), + .Y(\s$1289 ) + ); + INVx1_ASAP7_75t_R \U$2736 ( + .A(\con$4462 ), + .Y(\c$1227 ) + ); + INVx1_ASAP7_75t_R \U$2737 ( + .A(\sn$4463 ), + .Y(\s$1290 ) + ); + INVx1_ASAP7_75t_R \U$2738 ( + .A(\con$4464 ), + .Y(\c$1228 ) + ); + INVx1_ASAP7_75t_R \U$2739 ( + .A(\sn$4465 ), + .Y(\s$1291 ) + ); + INVx1_ASAP7_75t_R \U$2740 ( + .A(\con$4466 ), + .Y(\c$1229 ) + ); + INVx1_ASAP7_75t_R \U$2741 ( + .A(\sn$4467 ), + .Y(\s$1292 ) + ); + INVx1_ASAP7_75t_R \U$2742 ( + .A(\con$4468 ), + .Y(\c$1230 ) + ); + INVx1_ASAP7_75t_R \U$2743 ( + .A(\sn$4469 ), + .Y(\s$1293 ) + ); + INVx1_ASAP7_75t_R \U$2744 ( + .A(\con$4470 ), + .Y(\c$1231 ) + ); + INVx1_ASAP7_75t_R \U$2745 ( + .A(\sn$4471 ), + .Y(\s$1294 ) + ); + INVx1_ASAP7_75t_R \U$2746 ( + .A(\con$4472 ), + .Y(\c$1232 ) + ); + INVx1_ASAP7_75t_R \U$2747 ( + .A(\sn$4473 ), + .Y(\s$1295 ) + ); + INVx1_ASAP7_75t_R \U$2748 ( + .A(\con$4474 ), + .Y(\c$1233 ) + ); + INVx1_ASAP7_75t_R \U$2749 ( + .A(\sn$4475 ), + .Y(\s$1296 ) + ); + INVx1_ASAP7_75t_R \U$2750 ( + .A(\con$4476 ), + .Y(\c$1234 ) + ); + INVx1_ASAP7_75t_R \U$2751 ( + .A(\sn$4477 ), + .Y(\s$1297 ) + ); + INVx1_ASAP7_75t_R \U$2752 ( + .A(\con$4478 ), + .Y(\c$1235 ) + ); + INVx1_ASAP7_75t_R \U$2753 ( + .A(\sn$4479 ), + .Y(\s$1298 ) + ); + INVx1_ASAP7_75t_R \U$2754 ( + .A(\con$4480 ), + .Y(\c$1236 ) + ); + INVx1_ASAP7_75t_R \U$2755 ( + .A(\sn$4481 ), + .Y(\s$1299 ) + ); + INVx1_ASAP7_75t_R \U$2756 ( + .A(\con$4482 ), + .Y(\c$1237 ) + ); + INVx1_ASAP7_75t_R \U$2757 ( + .A(\sn$4483 ), + .Y(\s$1300 ) + ); + INVx1_ASAP7_75t_R \U$2758 ( + .A(\con$4484 ), + .Y(\c$1238 ) + ); + INVx1_ASAP7_75t_R \U$2759 ( + .A(\sn$4485 ), + .Y(\s$1301 ) + ); + INVx1_ASAP7_75t_R \U$2760 ( + .A(\con$4486 ), + .Y(\c$1239 ) + ); + INVx1_ASAP7_75t_R \U$2761 ( + .A(\sn$4487 ), + .Y(\s$1302 ) + ); + INVx1_ASAP7_75t_R \U$2762 ( + .A(\con$4488 ), + .Y(\c$1240 ) + ); + INVx1_ASAP7_75t_R \U$2763 ( + .A(\sn$4489 ), + .Y(\s$1303 ) + ); + INVx1_ASAP7_75t_R \U$2764 ( + .A(\con$4490 ), + .Y(\c$1241 ) + ); + INVx1_ASAP7_75t_R \U$2765 ( + .A(\sn$4491 ), + .Y(\s$1304 ) + ); + INVx1_ASAP7_75t_R \U$2766 ( + .A(\con$4492 ), + .Y(\c$1242 ) + ); + INVx1_ASAP7_75t_R \U$2767 ( + .A(\sn$4493 ), + .Y(\s$1305 ) + ); + INVx1_ASAP7_75t_R \U$2768 ( + .A(\con$4494 ), + .Y(\c$1243 ) + ); + INVx1_ASAP7_75t_R \U$2769 ( + .A(\sn$4495 ), + .Y(\s$1306 ) + ); + INVx1_ASAP7_75t_R \U$2770 ( + .A(\con$4496 ), + .Y(\c$1244 ) + ); + INVx1_ASAP7_75t_R \U$2771 ( + .A(\sn$4497 ), + .Y(\s$1307 ) + ); + INVx1_ASAP7_75t_R \U$2772 ( + .A(\con$4498 ), + .Y(\c$1245 ) + ); + INVx1_ASAP7_75t_R \U$2773 ( + .A(\sn$4499 ), + .Y(\s$1308 ) + ); + INVx1_ASAP7_75t_R \U$2774 ( + .A(\con$4500 ), + .Y(\c$1246 ) + ); + INVx1_ASAP7_75t_R \U$2775 ( + .A(\sn$4501 ), + .Y(\s$1309 ) + ); + INVx1_ASAP7_75t_R \U$2776 ( + .A(\con$4502 ), + .Y(\c$1247 ) + ); + INVx1_ASAP7_75t_R \U$2777 ( + .A(\sn$4503 ), + .Y(\s$1310 ) + ); + INVx1_ASAP7_75t_R \U$2778 ( + .A(\con$4504 ), + .Y(\c$1248 ) + ); + INVx1_ASAP7_75t_R \U$2779 ( + .A(\sn$4505 ), + .Y(\s$1311 ) + ); + INVx1_ASAP7_75t_R \U$2780 ( + .A(\con$4506 ), + .Y(\c$1249 ) + ); + INVx1_ASAP7_75t_R \U$2781 ( + .A(\sn$4507 ), + .Y(\s$1312 ) + ); + INVx1_ASAP7_75t_R \U$2782 ( + .A(\con$4508 ), + .Y(\c$1250 ) + ); + INVx1_ASAP7_75t_R \U$2783 ( + .A(\sn$4509 ), + .Y(\s$1313 ) + ); + INVx1_ASAP7_75t_R \U$2784 ( + .A(\con$4510 ), + .Y(\c$1251 ) + ); + INVx1_ASAP7_75t_R \U$2785 ( + .A(\sn$4511 ), + .Y(\s$1314 ) + ); + INVx1_ASAP7_75t_R \U$2786 ( + .A(\con$4512 ), + .Y(\c$1252 ) + ); + INVx1_ASAP7_75t_R \U$2787 ( + .A(\sn$4513 ), + .Y(\s$1315 ) + ); + INVx1_ASAP7_75t_R \U$2788 ( + .A(\con$4514 ), + .Y(\c$1253 ) + ); + INVx1_ASAP7_75t_R \U$2789 ( + .A(\sn$4515 ), + .Y(\s$1316 ) + ); + INVx1_ASAP7_75t_R \U$2790 ( + .A(\con$4516 ), + .Y(\c$1254 ) + ); + INVx1_ASAP7_75t_R \U$2791 ( + .A(\sn$4517 ), + .Y(\s$1317 ) + ); + INVx1_ASAP7_75t_R \U$2792 ( + .A(\con$4518 ), + .Y(\c$1255 ) + ); + INVx1_ASAP7_75t_R \U$2793 ( + .A(\sn$4519 ), + .Y(\s$1318 ) + ); + INVx1_ASAP7_75t_R \U$2794 ( + .A(\con$4520 ), + .Y(\c$1256 ) + ); + INVx1_ASAP7_75t_R \U$2795 ( + .A(\sn$4521 ), + .Y(\s$1319 ) + ); + INVx1_ASAP7_75t_R \U$2796 ( + .A(\con$4522 ), + .Y(\c$1257 ) + ); + INVx1_ASAP7_75t_R \U$2797 ( + .A(\sn$4523 ), + .Y(\s$1320 ) + ); + INVx1_ASAP7_75t_R \U$2798 ( + .A(\con$4524 ), + .Y(\$53 ) + ); + INVx1_ASAP7_75t_R \U$2799 ( + .A(\sn$4525 ), + .Y(\s$1321 ) + ); + INVx1_ASAP7_75t_R \U$526 ( + .A(1'h0), + .Y(\$1 ) + ); + INVx1_ASAP7_75t_R \U$527 ( + .A(a_registered[0]), + .Y(\$2 ) + ); + INVx1_ASAP7_75t_R \U$528 ( + .A(a_registered[1]), + .Y(\$3 ) + ); + AO33x2_ASAP7_75t_R \U$529 ( + .A1(\$3 ), + .A2(a_registered[0]), + .A3(1'h0), + .B1(a_registered[1]), + .B2(\$2 ), + .B3(\$1 ), + .Y(sel_0) + ); + XOR2x1_ASAP7_75t_R \U$530 ( + .A(a_registered[0]), + .B(1'h0), + .Y(sel_1) + ); + AO22x1_ASAP7_75t_R \U$531 ( + .A1(1'h0), + .A2(sel_0), + .B1(b_registered[0]), + .B2(sel_1), + .Y(t) + ); + XOR2x1_ASAP7_75t_R \U$532 ( + .A(t), + .B(a_registered[1]), + .Y(booth_b0_m0) + ); + AO22x1_ASAP7_75t_R \U$533 ( + .A1(b_registered[0]), + .A2(sel_0), + .B1(b_registered[1]), + .B2(sel_1), + .Y(\t$1976 ) + ); + XOR2x1_ASAP7_75t_R \U$534 ( + .A(\t$1976 ), + .B(a_registered[1]), + .Y(booth_b0_m1) + ); + AO22x1_ASAP7_75t_R \U$535 ( + .A1(b_registered[1]), + .A2(sel_0), + .B1(b_registered[2]), + .B2(sel_1), + .Y(\t$1977 ) + ); + XOR2x1_ASAP7_75t_R \U$536 ( + .A(\t$1977 ), + .B(a_registered[1]), + .Y(booth_b0_m2) + ); + AO22x1_ASAP7_75t_R \U$537 ( + .A1(b_registered[2]), + .A2(sel_0), + .B1(b_registered[3]), + .B2(sel_1), + .Y(\t$1978 ) + ); + XOR2x1_ASAP7_75t_R \U$538 ( + .A(\t$1978 ), + .B(a_registered[1]), + .Y(booth_b0_m3) + ); + AO22x1_ASAP7_75t_R \U$539 ( + .A1(b_registered[3]), + .A2(sel_0), + .B1(b_registered[4]), + .B2(sel_1), + .Y(\t$1979 ) + ); + XOR2x1_ASAP7_75t_R \U$540 ( + .A(\t$1979 ), + .B(a_registered[1]), + .Y(booth_b0_m4) + ); + AO22x1_ASAP7_75t_R \U$541 ( + .A1(b_registered[4]), + .A2(sel_0), + .B1(b_registered[5]), + .B2(sel_1), + .Y(\t$1980 ) + ); + XOR2x1_ASAP7_75t_R \U$542 ( + .A(\t$1980 ), + .B(a_registered[1]), + .Y(booth_b0_m5) + ); + AO22x1_ASAP7_75t_R \U$543 ( + .A1(b_registered[5]), + .A2(sel_0), + .B1(b_registered[6]), + .B2(sel_1), + .Y(\t$1981 ) + ); + XOR2x1_ASAP7_75t_R \U$544 ( + .A(\t$1981 ), + .B(a_registered[1]), + .Y(booth_b0_m6) + ); + AO22x1_ASAP7_75t_R \U$545 ( + .A1(b_registered[6]), + .A2(sel_0), + .B1(b_registered[7]), + .B2(sel_1), + .Y(\t$1982 ) + ); + XOR2x1_ASAP7_75t_R \U$546 ( + .A(\t$1982 ), + .B(a_registered[1]), + .Y(booth_b0_m7) + ); + AO22x1_ASAP7_75t_R \U$547 ( + .A1(b_registered[7]), + .A2(sel_0), + .B1(b_registered[8]), + .B2(sel_1), + .Y(\t$1983 ) + ); + XOR2x1_ASAP7_75t_R \U$548 ( + .A(\t$1983 ), + .B(a_registered[1]), + .Y(booth_b0_m8) + ); + AO22x1_ASAP7_75t_R \U$549 ( + .A1(b_registered[8]), + .A2(sel_0), + .B1(b_registered[9]), + .B2(sel_1), + .Y(\t$1984 ) + ); + XOR2x1_ASAP7_75t_R \U$550 ( + .A(\t$1984 ), + .B(a_registered[1]), + .Y(booth_b0_m9) + ); + AO22x1_ASAP7_75t_R \U$551 ( + .A1(b_registered[9]), + .A2(sel_0), + .B1(b_registered[10]), + .B2(sel_1), + .Y(\t$1985 ) + ); + XOR2x1_ASAP7_75t_R \U$552 ( + .A(\t$1985 ), + .B(a_registered[1]), + .Y(booth_b0_m10) + ); + AO22x1_ASAP7_75t_R \U$553 ( + .A1(b_registered[10]), + .A2(sel_0), + .B1(b_registered[11]), + .B2(sel_1), + .Y(\t$1986 ) + ); + XOR2x1_ASAP7_75t_R \U$554 ( + .A(\t$1986 ), + .B(a_registered[1]), + .Y(booth_b0_m11) + ); + AO22x1_ASAP7_75t_R \U$555 ( + .A1(b_registered[11]), + .A2(sel_0), + .B1(b_registered[12]), + .B2(sel_1), + .Y(\t$1987 ) + ); + XOR2x1_ASAP7_75t_R \U$556 ( + .A(\t$1987 ), + .B(a_registered[1]), + .Y(booth_b0_m12) + ); + AO22x1_ASAP7_75t_R \U$557 ( + .A1(b_registered[12]), + .A2(sel_0), + .B1(b_registered[13]), + .B2(sel_1), + .Y(\t$1988 ) + ); + XOR2x1_ASAP7_75t_R \U$558 ( + .A(\t$1988 ), + .B(a_registered[1]), + .Y(booth_b0_m13) + ); + AO22x1_ASAP7_75t_R \U$559 ( + .A1(b_registered[13]), + .A2(sel_0), + .B1(b_registered[14]), + .B2(sel_1), + .Y(\t$1989 ) + ); + XOR2x1_ASAP7_75t_R \U$560 ( + .A(\t$1989 ), + .B(a_registered[1]), + .Y(booth_b0_m14) + ); + AO22x1_ASAP7_75t_R \U$561 ( + .A1(b_registered[14]), + .A2(sel_0), + .B1(b_registered[15]), + .B2(sel_1), + .Y(\t$1990 ) + ); + XOR2x1_ASAP7_75t_R \U$562 ( + .A(\t$1990 ), + .B(a_registered[1]), + .Y(booth_b0_m15) + ); + AO22x1_ASAP7_75t_R \U$563 ( + .A1(b_registered[15]), + .A2(sel_0), + .B1(b_registered[16]), + .B2(sel_1), + .Y(\t$1991 ) + ); + XOR2x1_ASAP7_75t_R \U$564 ( + .A(\t$1991 ), + .B(a_registered[1]), + .Y(booth_b0_m16) + ); + AO22x1_ASAP7_75t_R \U$565 ( + .A1(b_registered[16]), + .A2(sel_0), + .B1(b_registered[17]), + .B2(sel_1), + .Y(\t$1992 ) + ); + XOR2x1_ASAP7_75t_R \U$566 ( + .A(\t$1992 ), + .B(a_registered[1]), + .Y(booth_b0_m17) + ); + AO22x1_ASAP7_75t_R \U$567 ( + .A1(b_registered[17]), + .A2(sel_0), + .B1(b_registered[18]), + .B2(sel_1), + .Y(\t$1993 ) + ); + XOR2x1_ASAP7_75t_R \U$568 ( + .A(\t$1993 ), + .B(a_registered[1]), + .Y(booth_b0_m18) + ); + AO22x1_ASAP7_75t_R \U$569 ( + .A1(b_registered[18]), + .A2(sel_0), + .B1(b_registered[19]), + .B2(sel_1), + .Y(\t$1994 ) + ); + XOR2x1_ASAP7_75t_R \U$570 ( + .A(\t$1994 ), + .B(a_registered[1]), + .Y(booth_b0_m19) + ); + AO22x1_ASAP7_75t_R \U$571 ( + .A1(b_registered[19]), + .A2(sel_0), + .B1(b_registered[20]), + .B2(sel_1), + .Y(\t$1995 ) + ); + XOR2x1_ASAP7_75t_R \U$572 ( + .A(\t$1995 ), + .B(a_registered[1]), + .Y(booth_b0_m20) + ); + AO22x1_ASAP7_75t_R \U$573 ( + .A1(b_registered[20]), + .A2(sel_0), + .B1(b_registered[21]), + .B2(sel_1), + .Y(\t$1996 ) + ); + XOR2x1_ASAP7_75t_R \U$574 ( + .A(\t$1996 ), + .B(a_registered[1]), + .Y(booth_b0_m21) + ); + AO22x1_ASAP7_75t_R \U$575 ( + .A1(b_registered[21]), + .A2(sel_0), + .B1(b_registered[22]), + .B2(sel_1), + .Y(\t$1997 ) + ); + XOR2x1_ASAP7_75t_R \U$576 ( + .A(\t$1997 ), + .B(a_registered[1]), + .Y(booth_b0_m22) + ); + AO22x1_ASAP7_75t_R \U$577 ( + .A1(b_registered[22]), + .A2(sel_0), + .B1(b_registered[23]), + .B2(sel_1), + .Y(\t$1998 ) + ); + XOR2x1_ASAP7_75t_R \U$578 ( + .A(\t$1998 ), + .B(a_registered[1]), + .Y(booth_b0_m23) + ); + AO22x1_ASAP7_75t_R \U$579 ( + .A1(b_registered[23]), + .A2(sel_0), + .B1(b_registered[24]), + .B2(sel_1), + .Y(\t$1999 ) + ); + XOR2x1_ASAP7_75t_R \U$580 ( + .A(\t$1999 ), + .B(a_registered[1]), + .Y(booth_b0_m24) + ); + AO22x1_ASAP7_75t_R \U$581 ( + .A1(b_registered[24]), + .A2(sel_0), + .B1(b_registered[25]), + .B2(sel_1), + .Y(\t$2000 ) + ); + XOR2x1_ASAP7_75t_R \U$582 ( + .A(\t$2000 ), + .B(a_registered[1]), + .Y(booth_b0_m25) + ); + AO22x1_ASAP7_75t_R \U$583 ( + .A1(b_registered[25]), + .A2(sel_0), + .B1(b_registered[26]), + .B2(sel_1), + .Y(\t$2001 ) + ); + XOR2x1_ASAP7_75t_R \U$584 ( + .A(\t$2001 ), + .B(a_registered[1]), + .Y(booth_b0_m26) + ); + AO22x1_ASAP7_75t_R \U$585 ( + .A1(b_registered[26]), + .A2(sel_0), + .B1(b_registered[27]), + .B2(sel_1), + .Y(\t$2002 ) + ); + XOR2x1_ASAP7_75t_R \U$586 ( + .A(\t$2002 ), + .B(a_registered[1]), + .Y(booth_b0_m27) + ); + AO22x1_ASAP7_75t_R \U$587 ( + .A1(b_registered[27]), + .A2(sel_0), + .B1(b_registered[28]), + .B2(sel_1), + .Y(\t$2003 ) + ); + XOR2x1_ASAP7_75t_R \U$588 ( + .A(\t$2003 ), + .B(a_registered[1]), + .Y(booth_b0_m28) + ); + AO22x1_ASAP7_75t_R \U$589 ( + .A1(b_registered[28]), + .A2(sel_0), + .B1(b_registered[29]), + .B2(sel_1), + .Y(\t$2004 ) + ); + XOR2x1_ASAP7_75t_R \U$590 ( + .A(\t$2004 ), + .B(a_registered[1]), + .Y(booth_b0_m29) + ); + AO22x1_ASAP7_75t_R \U$591 ( + .A1(b_registered[29]), + .A2(sel_0), + .B1(b_registered[30]), + .B2(sel_1), + .Y(\t$2005 ) + ); + XOR2x1_ASAP7_75t_R \U$592 ( + .A(\t$2005 ), + .B(a_registered[1]), + .Y(booth_b0_m30) + ); + AO22x1_ASAP7_75t_R \U$593 ( + .A1(b_registered[30]), + .A2(sel_0), + .B1(b_registered[31]), + .B2(sel_1), + .Y(\t$2006 ) + ); + XOR2x1_ASAP7_75t_R \U$594 ( + .A(\t$2006 ), + .B(a_registered[1]), + .Y(booth_b0_m31) + ); + AO22x1_ASAP7_75t_R \U$595 ( + .A1(b_registered[31]), + .A2(sel_0), + .B1(1'h0), + .B2(sel_1), + .Y(\t$2007 ) + ); + XOR2x1_ASAP7_75t_R \U$596 ( + .A(\t$2007 ), + .B(a_registered[1]), + .Y(booth_b0_m32) + ); + INVx1_ASAP7_75t_R \U$597 ( + .A(a_registered[1]), + .Y(notsign) + ); + INVx1_ASAP7_75t_R \U$598 ( + .A(a_registered[1]), + .Y(\$4 ) + ); + INVx1_ASAP7_75t_R \U$599 ( + .A(a_registered[2]), + .Y(\$5 ) + ); + INVx1_ASAP7_75t_R \U$600 ( + .A(a_registered[3]), + .Y(\$6 ) + ); + AO33x2_ASAP7_75t_R \U$601 ( + .A1(\$6 ), + .A2(a_registered[2]), + .A3(a_registered[1]), + .B1(a_registered[3]), + .B2(\$5 ), + .B3(\$4 ), + .Y(\sel_0$1365 ) + ); + XOR2x1_ASAP7_75t_R \U$602 ( + .A(a_registered[2]), + .B(a_registered[1]), + .Y(\sel_1$1366 ) + ); + AO22x1_ASAP7_75t_R \U$603 ( + .A1(1'h0), + .A2(\sel_0$1365 ), + .B1(b_registered[0]), + .B2(\sel_1$1366 ), + .Y(\t$2009 ) + ); + XOR2x1_ASAP7_75t_R \U$604 ( + .A(\t$2009 ), + .B(a_registered[3]), + .Y(booth_b2_m0) + ); + AO22x1_ASAP7_75t_R \U$605 ( + .A1(b_registered[0]), + .A2(\sel_0$1365 ), + .B1(b_registered[1]), + .B2(\sel_1$1366 ), + .Y(\t$2010 ) + ); + XOR2x1_ASAP7_75t_R \U$606 ( + .A(\t$2010 ), + .B(a_registered[3]), + .Y(booth_b2_m1) + ); + AO22x1_ASAP7_75t_R \U$607 ( + .A1(b_registered[1]), + .A2(\sel_0$1365 ), + .B1(b_registered[2]), + .B2(\sel_1$1366 ), + .Y(\t$2011 ) + ); + XOR2x1_ASAP7_75t_R \U$608 ( + .A(\t$2011 ), + .B(a_registered[3]), + .Y(booth_b2_m2) + ); + AO22x1_ASAP7_75t_R \U$609 ( + .A1(b_registered[2]), + .A2(\sel_0$1365 ), + .B1(b_registered[3]), + .B2(\sel_1$1366 ), + .Y(\t$2012 ) + ); + XOR2x1_ASAP7_75t_R \U$610 ( + .A(\t$2012 ), + .B(a_registered[3]), + .Y(booth_b2_m3) + ); + AO22x1_ASAP7_75t_R \U$611 ( + .A1(b_registered[3]), + .A2(\sel_0$1365 ), + .B1(b_registered[4]), + .B2(\sel_1$1366 ), + .Y(\t$2013 ) + ); + XOR2x1_ASAP7_75t_R \U$612 ( + .A(\t$2013 ), + .B(a_registered[3]), + .Y(booth_b2_m4) + ); + AO22x1_ASAP7_75t_R \U$613 ( + .A1(b_registered[4]), + .A2(\sel_0$1365 ), + .B1(b_registered[5]), + .B2(\sel_1$1366 ), + .Y(\t$2014 ) + ); + XOR2x1_ASAP7_75t_R \U$614 ( + .A(\t$2014 ), + .B(a_registered[3]), + .Y(booth_b2_m5) + ); + AO22x1_ASAP7_75t_R \U$615 ( + .A1(b_registered[5]), + .A2(\sel_0$1365 ), + .B1(b_registered[6]), + .B2(\sel_1$1366 ), + .Y(\t$2015 ) + ); + XOR2x1_ASAP7_75t_R \U$616 ( + .A(\t$2015 ), + .B(a_registered[3]), + .Y(booth_b2_m6) + ); + AO22x1_ASAP7_75t_R \U$617 ( + .A1(b_registered[6]), + .A2(\sel_0$1365 ), + .B1(b_registered[7]), + .B2(\sel_1$1366 ), + .Y(\t$2016 ) + ); + XOR2x1_ASAP7_75t_R \U$618 ( + .A(\t$2016 ), + .B(a_registered[3]), + .Y(booth_b2_m7) + ); + AO22x1_ASAP7_75t_R \U$619 ( + .A1(b_registered[7]), + .A2(\sel_0$1365 ), + .B1(b_registered[8]), + .B2(\sel_1$1366 ), + .Y(\t$2017 ) + ); + XOR2x1_ASAP7_75t_R \U$620 ( + .A(\t$2017 ), + .B(a_registered[3]), + .Y(booth_b2_m8) + ); + AO22x1_ASAP7_75t_R \U$621 ( + .A1(b_registered[8]), + .A2(\sel_0$1365 ), + .B1(b_registered[9]), + .B2(\sel_1$1366 ), + .Y(\t$2018 ) + ); + XOR2x1_ASAP7_75t_R \U$622 ( + .A(\t$2018 ), + .B(a_registered[3]), + .Y(booth_b2_m9) + ); + AO22x1_ASAP7_75t_R \U$623 ( + .A1(b_registered[9]), + .A2(\sel_0$1365 ), + .B1(b_registered[10]), + .B2(\sel_1$1366 ), + .Y(\t$2019 ) + ); + XOR2x1_ASAP7_75t_R \U$624 ( + .A(\t$2019 ), + .B(a_registered[3]), + .Y(booth_b2_m10) + ); + AO22x1_ASAP7_75t_R \U$625 ( + .A1(b_registered[10]), + .A2(\sel_0$1365 ), + .B1(b_registered[11]), + .B2(\sel_1$1366 ), + .Y(\t$2020 ) + ); + XOR2x1_ASAP7_75t_R \U$626 ( + .A(\t$2020 ), + .B(a_registered[3]), + .Y(booth_b2_m11) + ); + AO22x1_ASAP7_75t_R \U$627 ( + .A1(b_registered[11]), + .A2(\sel_0$1365 ), + .B1(b_registered[12]), + .B2(\sel_1$1366 ), + .Y(\t$2021 ) + ); + XOR2x1_ASAP7_75t_R \U$628 ( + .A(\t$2021 ), + .B(a_registered[3]), + .Y(booth_b2_m12) + ); + AO22x1_ASAP7_75t_R \U$629 ( + .A1(b_registered[12]), + .A2(\sel_0$1365 ), + .B1(b_registered[13]), + .B2(\sel_1$1366 ), + .Y(\t$2022 ) + ); + XOR2x1_ASAP7_75t_R \U$630 ( + .A(\t$2022 ), + .B(a_registered[3]), + .Y(booth_b2_m13) + ); + AO22x1_ASAP7_75t_R \U$631 ( + .A1(b_registered[13]), + .A2(\sel_0$1365 ), + .B1(b_registered[14]), + .B2(\sel_1$1366 ), + .Y(\t$2023 ) + ); + XOR2x1_ASAP7_75t_R \U$632 ( + .A(\t$2023 ), + .B(a_registered[3]), + .Y(booth_b2_m14) + ); + AO22x1_ASAP7_75t_R \U$633 ( + .A1(b_registered[14]), + .A2(\sel_0$1365 ), + .B1(b_registered[15]), + .B2(\sel_1$1366 ), + .Y(\t$2024 ) + ); + XOR2x1_ASAP7_75t_R \U$634 ( + .A(\t$2024 ), + .B(a_registered[3]), + .Y(booth_b2_m15) + ); + AO22x1_ASAP7_75t_R \U$635 ( + .A1(b_registered[15]), + .A2(\sel_0$1365 ), + .B1(b_registered[16]), + .B2(\sel_1$1366 ), + .Y(\t$2025 ) + ); + XOR2x1_ASAP7_75t_R \U$636 ( + .A(\t$2025 ), + .B(a_registered[3]), + .Y(booth_b2_m16) + ); + AO22x1_ASAP7_75t_R \U$637 ( + .A1(b_registered[16]), + .A2(\sel_0$1365 ), + .B1(b_registered[17]), + .B2(\sel_1$1366 ), + .Y(\t$2026 ) + ); + XOR2x1_ASAP7_75t_R \U$638 ( + .A(\t$2026 ), + .B(a_registered[3]), + .Y(booth_b2_m17) + ); + AO22x1_ASAP7_75t_R \U$639 ( + .A1(b_registered[17]), + .A2(\sel_0$1365 ), + .B1(b_registered[18]), + .B2(\sel_1$1366 ), + .Y(\t$2027 ) + ); + XOR2x1_ASAP7_75t_R \U$640 ( + .A(\t$2027 ), + .B(a_registered[3]), + .Y(booth_b2_m18) + ); + AO22x1_ASAP7_75t_R \U$641 ( + .A1(b_registered[18]), + .A2(\sel_0$1365 ), + .B1(b_registered[19]), + .B2(\sel_1$1366 ), + .Y(\t$2028 ) + ); + XOR2x1_ASAP7_75t_R \U$642 ( + .A(\t$2028 ), + .B(a_registered[3]), + .Y(booth_b2_m19) + ); + AO22x1_ASAP7_75t_R \U$643 ( + .A1(b_registered[19]), + .A2(\sel_0$1365 ), + .B1(b_registered[20]), + .B2(\sel_1$1366 ), + .Y(\t$2029 ) + ); + XOR2x1_ASAP7_75t_R \U$644 ( + .A(\t$2029 ), + .B(a_registered[3]), + .Y(booth_b2_m20) + ); + AO22x1_ASAP7_75t_R \U$645 ( + .A1(b_registered[20]), + .A2(\sel_0$1365 ), + .B1(b_registered[21]), + .B2(\sel_1$1366 ), + .Y(\t$2030 ) + ); + XOR2x1_ASAP7_75t_R \U$646 ( + .A(\t$2030 ), + .B(a_registered[3]), + .Y(booth_b2_m21) + ); + AO22x1_ASAP7_75t_R \U$647 ( + .A1(b_registered[21]), + .A2(\sel_0$1365 ), + .B1(b_registered[22]), + .B2(\sel_1$1366 ), + .Y(\t$2031 ) + ); + XOR2x1_ASAP7_75t_R \U$648 ( + .A(\t$2031 ), + .B(a_registered[3]), + .Y(booth_b2_m22) + ); + AO22x1_ASAP7_75t_R \U$649 ( + .A1(b_registered[22]), + .A2(\sel_0$1365 ), + .B1(b_registered[23]), + .B2(\sel_1$1366 ), + .Y(\t$2032 ) + ); + XOR2x1_ASAP7_75t_R \U$650 ( + .A(\t$2032 ), + .B(a_registered[3]), + .Y(booth_b2_m23) + ); + AO22x1_ASAP7_75t_R \U$651 ( + .A1(b_registered[23]), + .A2(\sel_0$1365 ), + .B1(b_registered[24]), + .B2(\sel_1$1366 ), + .Y(\t$2033 ) + ); + XOR2x1_ASAP7_75t_R \U$652 ( + .A(\t$2033 ), + .B(a_registered[3]), + .Y(booth_b2_m24) + ); + AO22x1_ASAP7_75t_R \U$653 ( + .A1(b_registered[24]), + .A2(\sel_0$1365 ), + .B1(b_registered[25]), + .B2(\sel_1$1366 ), + .Y(\t$2034 ) + ); + XOR2x1_ASAP7_75t_R \U$654 ( + .A(\t$2034 ), + .B(a_registered[3]), + .Y(booth_b2_m25) + ); + AO22x1_ASAP7_75t_R \U$655 ( + .A1(b_registered[25]), + .A2(\sel_0$1365 ), + .B1(b_registered[26]), + .B2(\sel_1$1366 ), + .Y(\t$2035 ) + ); + XOR2x1_ASAP7_75t_R \U$656 ( + .A(\t$2035 ), + .B(a_registered[3]), + .Y(booth_b2_m26) + ); + AO22x1_ASAP7_75t_R \U$657 ( + .A1(b_registered[26]), + .A2(\sel_0$1365 ), + .B1(b_registered[27]), + .B2(\sel_1$1366 ), + .Y(\t$2036 ) + ); + XOR2x1_ASAP7_75t_R \U$658 ( + .A(\t$2036 ), + .B(a_registered[3]), + .Y(booth_b2_m27) + ); + AO22x1_ASAP7_75t_R \U$659 ( + .A1(b_registered[27]), + .A2(\sel_0$1365 ), + .B1(b_registered[28]), + .B2(\sel_1$1366 ), + .Y(\t$2037 ) + ); + XOR2x1_ASAP7_75t_R \U$660 ( + .A(\t$2037 ), + .B(a_registered[3]), + .Y(booth_b2_m28) + ); + AO22x1_ASAP7_75t_R \U$661 ( + .A1(b_registered[28]), + .A2(\sel_0$1365 ), + .B1(b_registered[29]), + .B2(\sel_1$1366 ), + .Y(\t$2038 ) + ); + XOR2x1_ASAP7_75t_R \U$662 ( + .A(\t$2038 ), + .B(a_registered[3]), + .Y(booth_b2_m29) + ); + AO22x1_ASAP7_75t_R \U$663 ( + .A1(b_registered[29]), + .A2(\sel_0$1365 ), + .B1(b_registered[30]), + .B2(\sel_1$1366 ), + .Y(\t$2039 ) + ); + XOR2x1_ASAP7_75t_R \U$664 ( + .A(\t$2039 ), + .B(a_registered[3]), + .Y(booth_b2_m30) + ); + AO22x1_ASAP7_75t_R \U$665 ( + .A1(b_registered[30]), + .A2(\sel_0$1365 ), + .B1(b_registered[31]), + .B2(\sel_1$1366 ), + .Y(\t$2040 ) + ); + XOR2x1_ASAP7_75t_R \U$666 ( + .A(\t$2040 ), + .B(a_registered[3]), + .Y(booth_b2_m31) + ); + AO22x1_ASAP7_75t_R \U$667 ( + .A1(b_registered[31]), + .A2(\sel_0$1365 ), + .B1(1'h0), + .B2(\sel_1$1366 ), + .Y(\t$2041 ) + ); + XOR2x1_ASAP7_75t_R \U$668 ( + .A(\t$2041 ), + .B(a_registered[3]), + .Y(booth_b2_m32) + ); + INVx1_ASAP7_75t_R \U$669 ( + .A(a_registered[3]), + .Y(\notsign$686 ) + ); + INVx1_ASAP7_75t_R \U$670 ( + .A(a_registered[3]), + .Y(\$7 ) + ); + INVx1_ASAP7_75t_R \U$671 ( + .A(a_registered[4]), + .Y(\$8 ) + ); + INVx1_ASAP7_75t_R \U$672 ( + .A(a_registered[5]), + .Y(\$9 ) + ); + AO33x2_ASAP7_75t_R \U$673 ( + .A1(\$9 ), + .A2(a_registered[4]), + .A3(a_registered[3]), + .B1(a_registered[5]), + .B2(\$8 ), + .B3(\$7 ), + .Y(\sel_0$1402 ) + ); + XOR2x1_ASAP7_75t_R \U$674 ( + .A(a_registered[4]), + .B(a_registered[3]), + .Y(\sel_1$1403 ) + ); + AO22x1_ASAP7_75t_R \U$675 ( + .A1(1'h0), + .A2(\sel_0$1402 ), + .B1(b_registered[0]), + .B2(\sel_1$1403 ), + .Y(\t$2043 ) + ); + XOR2x1_ASAP7_75t_R \U$676 ( + .A(\t$2043 ), + .B(a_registered[5]), + .Y(booth_b4_m0) + ); + AO22x1_ASAP7_75t_R \U$677 ( + .A1(b_registered[0]), + .A2(\sel_0$1402 ), + .B1(b_registered[1]), + .B2(\sel_1$1403 ), + .Y(\t$2044 ) + ); + XOR2x1_ASAP7_75t_R \U$678 ( + .A(\t$2044 ), + .B(a_registered[5]), + .Y(booth_b4_m1) + ); + AO22x1_ASAP7_75t_R \U$679 ( + .A1(b_registered[1]), + .A2(\sel_0$1402 ), + .B1(b_registered[2]), + .B2(\sel_1$1403 ), + .Y(\t$2045 ) + ); + XOR2x1_ASAP7_75t_R \U$680 ( + .A(\t$2045 ), + .B(a_registered[5]), + .Y(booth_b4_m2) + ); + AO22x1_ASAP7_75t_R \U$681 ( + .A1(b_registered[2]), + .A2(\sel_0$1402 ), + .B1(b_registered[3]), + .B2(\sel_1$1403 ), + .Y(\t$2046 ) + ); + XOR2x1_ASAP7_75t_R \U$682 ( + .A(\t$2046 ), + .B(a_registered[5]), + .Y(booth_b4_m3) + ); + AO22x1_ASAP7_75t_R \U$683 ( + .A1(b_registered[3]), + .A2(\sel_0$1402 ), + .B1(b_registered[4]), + .B2(\sel_1$1403 ), + .Y(\t$2047 ) + ); + XOR2x1_ASAP7_75t_R \U$684 ( + .A(\t$2047 ), + .B(a_registered[5]), + .Y(booth_b4_m4) + ); + AO22x1_ASAP7_75t_R \U$685 ( + .A1(b_registered[4]), + .A2(\sel_0$1402 ), + .B1(b_registered[5]), + .B2(\sel_1$1403 ), + .Y(\t$2048 ) + ); + XOR2x1_ASAP7_75t_R \U$686 ( + .A(\t$2048 ), + .B(a_registered[5]), + .Y(booth_b4_m5) + ); + AO22x1_ASAP7_75t_R \U$687 ( + .A1(b_registered[5]), + .A2(\sel_0$1402 ), + .B1(b_registered[6]), + .B2(\sel_1$1403 ), + .Y(\t$2049 ) + ); + XOR2x1_ASAP7_75t_R \U$688 ( + .A(\t$2049 ), + .B(a_registered[5]), + .Y(booth_b4_m6) + ); + AO22x1_ASAP7_75t_R \U$689 ( + .A1(b_registered[6]), + .A2(\sel_0$1402 ), + .B1(b_registered[7]), + .B2(\sel_1$1403 ), + .Y(\t$2050 ) + ); + XOR2x1_ASAP7_75t_R \U$690 ( + .A(\t$2050 ), + .B(a_registered[5]), + .Y(booth_b4_m7) + ); + AO22x1_ASAP7_75t_R \U$691 ( + .A1(b_registered[7]), + .A2(\sel_0$1402 ), + .B1(b_registered[8]), + .B2(\sel_1$1403 ), + .Y(\t$2051 ) + ); + XOR2x1_ASAP7_75t_R \U$692 ( + .A(\t$2051 ), + .B(a_registered[5]), + .Y(booth_b4_m8) + ); + AO22x1_ASAP7_75t_R \U$693 ( + .A1(b_registered[8]), + .A2(\sel_0$1402 ), + .B1(b_registered[9]), + .B2(\sel_1$1403 ), + .Y(\t$2052 ) + ); + XOR2x1_ASAP7_75t_R \U$694 ( + .A(\t$2052 ), + .B(a_registered[5]), + .Y(booth_b4_m9) + ); + AO22x1_ASAP7_75t_R \U$695 ( + .A1(b_registered[9]), + .A2(\sel_0$1402 ), + .B1(b_registered[10]), + .B2(\sel_1$1403 ), + .Y(\t$2053 ) + ); + XOR2x1_ASAP7_75t_R \U$696 ( + .A(\t$2053 ), + .B(a_registered[5]), + .Y(booth_b4_m10) + ); + AO22x1_ASAP7_75t_R \U$697 ( + .A1(b_registered[10]), + .A2(\sel_0$1402 ), + .B1(b_registered[11]), + .B2(\sel_1$1403 ), + .Y(\t$2054 ) + ); + XOR2x1_ASAP7_75t_R \U$698 ( + .A(\t$2054 ), + .B(a_registered[5]), + .Y(booth_b4_m11) + ); + AO22x1_ASAP7_75t_R \U$699 ( + .A1(b_registered[11]), + .A2(\sel_0$1402 ), + .B1(b_registered[12]), + .B2(\sel_1$1403 ), + .Y(\t$2055 ) + ); + XOR2x1_ASAP7_75t_R \U$700 ( + .A(\t$2055 ), + .B(a_registered[5]), + .Y(booth_b4_m12) + ); + AO22x1_ASAP7_75t_R \U$701 ( + .A1(b_registered[12]), + .A2(\sel_0$1402 ), + .B1(b_registered[13]), + .B2(\sel_1$1403 ), + .Y(\t$2056 ) + ); + XOR2x1_ASAP7_75t_R \U$702 ( + .A(\t$2056 ), + .B(a_registered[5]), + .Y(booth_b4_m13) + ); + AO22x1_ASAP7_75t_R \U$703 ( + .A1(b_registered[13]), + .A2(\sel_0$1402 ), + .B1(b_registered[14]), + .B2(\sel_1$1403 ), + .Y(\t$2057 ) + ); + XOR2x1_ASAP7_75t_R \U$704 ( + .A(\t$2057 ), + .B(a_registered[5]), + .Y(booth_b4_m14) + ); + AO22x1_ASAP7_75t_R \U$705 ( + .A1(b_registered[14]), + .A2(\sel_0$1402 ), + .B1(b_registered[15]), + .B2(\sel_1$1403 ), + .Y(\t$2058 ) + ); + XOR2x1_ASAP7_75t_R \U$706 ( + .A(\t$2058 ), + .B(a_registered[5]), + .Y(booth_b4_m15) + ); + AO22x1_ASAP7_75t_R \U$707 ( + .A1(b_registered[15]), + .A2(\sel_0$1402 ), + .B1(b_registered[16]), + .B2(\sel_1$1403 ), + .Y(\t$2059 ) + ); + XOR2x1_ASAP7_75t_R \U$708 ( + .A(\t$2059 ), + .B(a_registered[5]), + .Y(booth_b4_m16) + ); + AO22x1_ASAP7_75t_R \U$709 ( + .A1(b_registered[16]), + .A2(\sel_0$1402 ), + .B1(b_registered[17]), + .B2(\sel_1$1403 ), + .Y(\t$2060 ) + ); + XOR2x1_ASAP7_75t_R \U$710 ( + .A(\t$2060 ), + .B(a_registered[5]), + .Y(booth_b4_m17) + ); + AO22x1_ASAP7_75t_R \U$711 ( + .A1(b_registered[17]), + .A2(\sel_0$1402 ), + .B1(b_registered[18]), + .B2(\sel_1$1403 ), + .Y(\t$2061 ) + ); + XOR2x1_ASAP7_75t_R \U$712 ( + .A(\t$2061 ), + .B(a_registered[5]), + .Y(booth_b4_m18) + ); + AO22x1_ASAP7_75t_R \U$713 ( + .A1(b_registered[18]), + .A2(\sel_0$1402 ), + .B1(b_registered[19]), + .B2(\sel_1$1403 ), + .Y(\t$2062 ) + ); + XOR2x1_ASAP7_75t_R \U$714 ( + .A(\t$2062 ), + .B(a_registered[5]), + .Y(booth_b4_m19) + ); + AO22x1_ASAP7_75t_R \U$715 ( + .A1(b_registered[19]), + .A2(\sel_0$1402 ), + .B1(b_registered[20]), + .B2(\sel_1$1403 ), + .Y(\t$2063 ) + ); + XOR2x1_ASAP7_75t_R \U$716 ( + .A(\t$2063 ), + .B(a_registered[5]), + .Y(booth_b4_m20) + ); + AO22x1_ASAP7_75t_R \U$717 ( + .A1(b_registered[20]), + .A2(\sel_0$1402 ), + .B1(b_registered[21]), + .B2(\sel_1$1403 ), + .Y(\t$2064 ) + ); + XOR2x1_ASAP7_75t_R \U$718 ( + .A(\t$2064 ), + .B(a_registered[5]), + .Y(booth_b4_m21) + ); + AO22x1_ASAP7_75t_R \U$719 ( + .A1(b_registered[21]), + .A2(\sel_0$1402 ), + .B1(b_registered[22]), + .B2(\sel_1$1403 ), + .Y(\t$2065 ) + ); + XOR2x1_ASAP7_75t_R \U$720 ( + .A(\t$2065 ), + .B(a_registered[5]), + .Y(booth_b4_m22) + ); + AO22x1_ASAP7_75t_R \U$721 ( + .A1(b_registered[22]), + .A2(\sel_0$1402 ), + .B1(b_registered[23]), + .B2(\sel_1$1403 ), + .Y(\t$2066 ) + ); + XOR2x1_ASAP7_75t_R \U$722 ( + .A(\t$2066 ), + .B(a_registered[5]), + .Y(booth_b4_m23) + ); + AO22x1_ASAP7_75t_R \U$723 ( + .A1(b_registered[23]), + .A2(\sel_0$1402 ), + .B1(b_registered[24]), + .B2(\sel_1$1403 ), + .Y(\t$2067 ) + ); + XOR2x1_ASAP7_75t_R \U$724 ( + .A(\t$2067 ), + .B(a_registered[5]), + .Y(booth_b4_m24) + ); + AO22x1_ASAP7_75t_R \U$725 ( + .A1(b_registered[24]), + .A2(\sel_0$1402 ), + .B1(b_registered[25]), + .B2(\sel_1$1403 ), + .Y(\t$2068 ) + ); + XOR2x1_ASAP7_75t_R \U$726 ( + .A(\t$2068 ), + .B(a_registered[5]), + .Y(booth_b4_m25) + ); + AO22x1_ASAP7_75t_R \U$727 ( + .A1(b_registered[25]), + .A2(\sel_0$1402 ), + .B1(b_registered[26]), + .B2(\sel_1$1403 ), + .Y(\t$2069 ) + ); + XOR2x1_ASAP7_75t_R \U$728 ( + .A(\t$2069 ), + .B(a_registered[5]), + .Y(booth_b4_m26) + ); + AO22x1_ASAP7_75t_R \U$729 ( + .A1(b_registered[26]), + .A2(\sel_0$1402 ), + .B1(b_registered[27]), + .B2(\sel_1$1403 ), + .Y(\t$2070 ) + ); + XOR2x1_ASAP7_75t_R \U$730 ( + .A(\t$2070 ), + .B(a_registered[5]), + .Y(booth_b4_m27) + ); + AO22x1_ASAP7_75t_R \U$731 ( + .A1(b_registered[27]), + .A2(\sel_0$1402 ), + .B1(b_registered[28]), + .B2(\sel_1$1403 ), + .Y(\t$2071 ) + ); + XOR2x1_ASAP7_75t_R \U$732 ( + .A(\t$2071 ), + .B(a_registered[5]), + .Y(booth_b4_m28) + ); + AO22x1_ASAP7_75t_R \U$733 ( + .A1(b_registered[28]), + .A2(\sel_0$1402 ), + .B1(b_registered[29]), + .B2(\sel_1$1403 ), + .Y(\t$2072 ) + ); + XOR2x1_ASAP7_75t_R \U$734 ( + .A(\t$2072 ), + .B(a_registered[5]), + .Y(booth_b4_m29) + ); + AO22x1_ASAP7_75t_R \U$735 ( + .A1(b_registered[29]), + .A2(\sel_0$1402 ), + .B1(b_registered[30]), + .B2(\sel_1$1403 ), + .Y(\t$2073 ) + ); + XOR2x1_ASAP7_75t_R \U$736 ( + .A(\t$2073 ), + .B(a_registered[5]), + .Y(booth_b4_m30) + ); + AO22x1_ASAP7_75t_R \U$737 ( + .A1(b_registered[30]), + .A2(\sel_0$1402 ), + .B1(b_registered[31]), + .B2(\sel_1$1403 ), + .Y(\t$2074 ) + ); + XOR2x1_ASAP7_75t_R \U$738 ( + .A(\t$2074 ), + .B(a_registered[5]), + .Y(booth_b4_m31) + ); + AO22x1_ASAP7_75t_R \U$739 ( + .A1(b_registered[31]), + .A2(\sel_0$1402 ), + .B1(1'h0), + .B2(\sel_1$1403 ), + .Y(\t$2075 ) + ); + XOR2x1_ASAP7_75t_R \U$740 ( + .A(\t$2075 ), + .B(a_registered[5]), + .Y(booth_b4_m32) + ); + INVx1_ASAP7_75t_R \U$741 ( + .A(a_registered[5]), + .Y(\notsign$748 ) + ); + INVx1_ASAP7_75t_R \U$742 ( + .A(a_registered[5]), + .Y(\$10 ) + ); + INVx1_ASAP7_75t_R \U$743 ( + .A(a_registered[6]), + .Y(\$11 ) + ); + INVx1_ASAP7_75t_R \U$744 ( + .A(a_registered[7]), + .Y(\$12 ) + ); + AO33x2_ASAP7_75t_R \U$745 ( + .A1(\$12 ), + .A2(a_registered[6]), + .A3(a_registered[5]), + .B1(a_registered[7]), + .B2(\$11 ), + .B3(\$10 ), + .Y(\sel_0$1439 ) + ); + XOR2x1_ASAP7_75t_R \U$746 ( + .A(a_registered[6]), + .B(a_registered[5]), + .Y(\sel_1$1440 ) + ); + AO22x1_ASAP7_75t_R \U$747 ( + .A1(1'h0), + .A2(\sel_0$1439 ), + .B1(b_registered[0]), + .B2(\sel_1$1440 ), + .Y(\t$2077 ) + ); + XOR2x1_ASAP7_75t_R \U$748 ( + .A(\t$2077 ), + .B(a_registered[7]), + .Y(booth_b6_m0) + ); + AO22x1_ASAP7_75t_R \U$749 ( + .A1(b_registered[0]), + .A2(\sel_0$1439 ), + .B1(b_registered[1]), + .B2(\sel_1$1440 ), + .Y(\t$2078 ) + ); + XOR2x1_ASAP7_75t_R \U$750 ( + .A(\t$2078 ), + .B(a_registered[7]), + .Y(booth_b6_m1) + ); + AO22x1_ASAP7_75t_R \U$751 ( + .A1(b_registered[1]), + .A2(\sel_0$1439 ), + .B1(b_registered[2]), + .B2(\sel_1$1440 ), + .Y(\t$2079 ) + ); + XOR2x1_ASAP7_75t_R \U$752 ( + .A(\t$2079 ), + .B(a_registered[7]), + .Y(booth_b6_m2) + ); + AO22x1_ASAP7_75t_R \U$753 ( + .A1(b_registered[2]), + .A2(\sel_0$1439 ), + .B1(b_registered[3]), + .B2(\sel_1$1440 ), + .Y(\t$2080 ) + ); + XOR2x1_ASAP7_75t_R \U$754 ( + .A(\t$2080 ), + .B(a_registered[7]), + .Y(booth_b6_m3) + ); + AO22x1_ASAP7_75t_R \U$755 ( + .A1(b_registered[3]), + .A2(\sel_0$1439 ), + .B1(b_registered[4]), + .B2(\sel_1$1440 ), + .Y(\t$2081 ) + ); + XOR2x1_ASAP7_75t_R \U$756 ( + .A(\t$2081 ), + .B(a_registered[7]), + .Y(booth_b6_m4) + ); + AO22x1_ASAP7_75t_R \U$757 ( + .A1(b_registered[4]), + .A2(\sel_0$1439 ), + .B1(b_registered[5]), + .B2(\sel_1$1440 ), + .Y(\t$2082 ) + ); + XOR2x1_ASAP7_75t_R \U$758 ( + .A(\t$2082 ), + .B(a_registered[7]), + .Y(booth_b6_m5) + ); + AO22x1_ASAP7_75t_R \U$759 ( + .A1(b_registered[5]), + .A2(\sel_0$1439 ), + .B1(b_registered[6]), + .B2(\sel_1$1440 ), + .Y(\t$2083 ) + ); + XOR2x1_ASAP7_75t_R \U$760 ( + .A(\t$2083 ), + .B(a_registered[7]), + .Y(booth_b6_m6) + ); + AO22x1_ASAP7_75t_R \U$761 ( + .A1(b_registered[6]), + .A2(\sel_0$1439 ), + .B1(b_registered[7]), + .B2(\sel_1$1440 ), + .Y(\t$2084 ) + ); + XOR2x1_ASAP7_75t_R \U$762 ( + .A(\t$2084 ), + .B(a_registered[7]), + .Y(booth_b6_m7) + ); + AO22x1_ASAP7_75t_R \U$763 ( + .A1(b_registered[7]), + .A2(\sel_0$1439 ), + .B1(b_registered[8]), + .B2(\sel_1$1440 ), + .Y(\t$2085 ) + ); + XOR2x1_ASAP7_75t_R \U$764 ( + .A(\t$2085 ), + .B(a_registered[7]), + .Y(booth_b6_m8) + ); + AO22x1_ASAP7_75t_R \U$765 ( + .A1(b_registered[8]), + .A2(\sel_0$1439 ), + .B1(b_registered[9]), + .B2(\sel_1$1440 ), + .Y(\t$2086 ) + ); + XOR2x1_ASAP7_75t_R \U$766 ( + .A(\t$2086 ), + .B(a_registered[7]), + .Y(booth_b6_m9) + ); + AO22x1_ASAP7_75t_R \U$767 ( + .A1(b_registered[9]), + .A2(\sel_0$1439 ), + .B1(b_registered[10]), + .B2(\sel_1$1440 ), + .Y(\t$2087 ) + ); + XOR2x1_ASAP7_75t_R \U$768 ( + .A(\t$2087 ), + .B(a_registered[7]), + .Y(booth_b6_m10) + ); + AO22x1_ASAP7_75t_R \U$769 ( + .A1(b_registered[10]), + .A2(\sel_0$1439 ), + .B1(b_registered[11]), + .B2(\sel_1$1440 ), + .Y(\t$2088 ) + ); + XOR2x1_ASAP7_75t_R \U$770 ( + .A(\t$2088 ), + .B(a_registered[7]), + .Y(booth_b6_m11) + ); + AO22x1_ASAP7_75t_R \U$771 ( + .A1(b_registered[11]), + .A2(\sel_0$1439 ), + .B1(b_registered[12]), + .B2(\sel_1$1440 ), + .Y(\t$2089 ) + ); + XOR2x1_ASAP7_75t_R \U$772 ( + .A(\t$2089 ), + .B(a_registered[7]), + .Y(booth_b6_m12) + ); + AO22x1_ASAP7_75t_R \U$773 ( + .A1(b_registered[12]), + .A2(\sel_0$1439 ), + .B1(b_registered[13]), + .B2(\sel_1$1440 ), + .Y(\t$2090 ) + ); + XOR2x1_ASAP7_75t_R \U$774 ( + .A(\t$2090 ), + .B(a_registered[7]), + .Y(booth_b6_m13) + ); + AO22x1_ASAP7_75t_R \U$775 ( + .A1(b_registered[13]), + .A2(\sel_0$1439 ), + .B1(b_registered[14]), + .B2(\sel_1$1440 ), + .Y(\t$2091 ) + ); + XOR2x1_ASAP7_75t_R \U$776 ( + .A(\t$2091 ), + .B(a_registered[7]), + .Y(booth_b6_m14) + ); + AO22x1_ASAP7_75t_R \U$777 ( + .A1(b_registered[14]), + .A2(\sel_0$1439 ), + .B1(b_registered[15]), + .B2(\sel_1$1440 ), + .Y(\t$2092 ) + ); + XOR2x1_ASAP7_75t_R \U$778 ( + .A(\t$2092 ), + .B(a_registered[7]), + .Y(booth_b6_m15) + ); + AO22x1_ASAP7_75t_R \U$779 ( + .A1(b_registered[15]), + .A2(\sel_0$1439 ), + .B1(b_registered[16]), + .B2(\sel_1$1440 ), + .Y(\t$2093 ) + ); + XOR2x1_ASAP7_75t_R \U$780 ( + .A(\t$2093 ), + .B(a_registered[7]), + .Y(booth_b6_m16) + ); + AO22x1_ASAP7_75t_R \U$781 ( + .A1(b_registered[16]), + .A2(\sel_0$1439 ), + .B1(b_registered[17]), + .B2(\sel_1$1440 ), + .Y(\t$2094 ) + ); + XOR2x1_ASAP7_75t_R \U$782 ( + .A(\t$2094 ), + .B(a_registered[7]), + .Y(booth_b6_m17) + ); + AO22x1_ASAP7_75t_R \U$783 ( + .A1(b_registered[17]), + .A2(\sel_0$1439 ), + .B1(b_registered[18]), + .B2(\sel_1$1440 ), + .Y(\t$2095 ) + ); + XOR2x1_ASAP7_75t_R \U$784 ( + .A(\t$2095 ), + .B(a_registered[7]), + .Y(booth_b6_m18) + ); + AO22x1_ASAP7_75t_R \U$785 ( + .A1(b_registered[18]), + .A2(\sel_0$1439 ), + .B1(b_registered[19]), + .B2(\sel_1$1440 ), + .Y(\t$2096 ) + ); + XOR2x1_ASAP7_75t_R \U$786 ( + .A(\t$2096 ), + .B(a_registered[7]), + .Y(booth_b6_m19) + ); + AO22x1_ASAP7_75t_R \U$787 ( + .A1(b_registered[19]), + .A2(\sel_0$1439 ), + .B1(b_registered[20]), + .B2(\sel_1$1440 ), + .Y(\t$2097 ) + ); + XOR2x1_ASAP7_75t_R \U$788 ( + .A(\t$2097 ), + .B(a_registered[7]), + .Y(booth_b6_m20) + ); + AO22x1_ASAP7_75t_R \U$789 ( + .A1(b_registered[20]), + .A2(\sel_0$1439 ), + .B1(b_registered[21]), + .B2(\sel_1$1440 ), + .Y(\t$2098 ) + ); + XOR2x1_ASAP7_75t_R \U$790 ( + .A(\t$2098 ), + .B(a_registered[7]), + .Y(booth_b6_m21) + ); + AO22x1_ASAP7_75t_R \U$791 ( + .A1(b_registered[21]), + .A2(\sel_0$1439 ), + .B1(b_registered[22]), + .B2(\sel_1$1440 ), + .Y(\t$2099 ) + ); + XOR2x1_ASAP7_75t_R \U$792 ( + .A(\t$2099 ), + .B(a_registered[7]), + .Y(booth_b6_m22) + ); + AO22x1_ASAP7_75t_R \U$793 ( + .A1(b_registered[22]), + .A2(\sel_0$1439 ), + .B1(b_registered[23]), + .B2(\sel_1$1440 ), + .Y(\t$2100 ) + ); + XOR2x1_ASAP7_75t_R \U$794 ( + .A(\t$2100 ), + .B(a_registered[7]), + .Y(booth_b6_m23) + ); + AO22x1_ASAP7_75t_R \U$795 ( + .A1(b_registered[23]), + .A2(\sel_0$1439 ), + .B1(b_registered[24]), + .B2(\sel_1$1440 ), + .Y(\t$2101 ) + ); + XOR2x1_ASAP7_75t_R \U$796 ( + .A(\t$2101 ), + .B(a_registered[7]), + .Y(booth_b6_m24) + ); + AO22x1_ASAP7_75t_R \U$797 ( + .A1(b_registered[24]), + .A2(\sel_0$1439 ), + .B1(b_registered[25]), + .B2(\sel_1$1440 ), + .Y(\t$2102 ) + ); + XOR2x1_ASAP7_75t_R \U$798 ( + .A(\t$2102 ), + .B(a_registered[7]), + .Y(booth_b6_m25) + ); + AO22x1_ASAP7_75t_R \U$799 ( + .A1(b_registered[25]), + .A2(\sel_0$1439 ), + .B1(b_registered[26]), + .B2(\sel_1$1440 ), + .Y(\t$2103 ) + ); + XOR2x1_ASAP7_75t_R \U$800 ( + .A(\t$2103 ), + .B(a_registered[7]), + .Y(booth_b6_m26) + ); + AO22x1_ASAP7_75t_R \U$801 ( + .A1(b_registered[26]), + .A2(\sel_0$1439 ), + .B1(b_registered[27]), + .B2(\sel_1$1440 ), + .Y(\t$2104 ) + ); + XOR2x1_ASAP7_75t_R \U$802 ( + .A(\t$2104 ), + .B(a_registered[7]), + .Y(booth_b6_m27) + ); + AO22x1_ASAP7_75t_R \U$803 ( + .A1(b_registered[27]), + .A2(\sel_0$1439 ), + .B1(b_registered[28]), + .B2(\sel_1$1440 ), + .Y(\t$2105 ) + ); + XOR2x1_ASAP7_75t_R \U$804 ( + .A(\t$2105 ), + .B(a_registered[7]), + .Y(booth_b6_m28) + ); + AO22x1_ASAP7_75t_R \U$805 ( + .A1(b_registered[28]), + .A2(\sel_0$1439 ), + .B1(b_registered[29]), + .B2(\sel_1$1440 ), + .Y(\t$2106 ) + ); + XOR2x1_ASAP7_75t_R \U$806 ( + .A(\t$2106 ), + .B(a_registered[7]), + .Y(booth_b6_m29) + ); + AO22x1_ASAP7_75t_R \U$807 ( + .A1(b_registered[29]), + .A2(\sel_0$1439 ), + .B1(b_registered[30]), + .B2(\sel_1$1440 ), + .Y(\t$2107 ) + ); + XOR2x1_ASAP7_75t_R \U$808 ( + .A(\t$2107 ), + .B(a_registered[7]), + .Y(booth_b6_m30) + ); + AO22x1_ASAP7_75t_R \U$809 ( + .A1(b_registered[30]), + .A2(\sel_0$1439 ), + .B1(b_registered[31]), + .B2(\sel_1$1440 ), + .Y(\t$2108 ) + ); + XOR2x1_ASAP7_75t_R \U$810 ( + .A(\t$2108 ), + .B(a_registered[7]), + .Y(booth_b6_m31) + ); + AO22x1_ASAP7_75t_R \U$811 ( + .A1(b_registered[31]), + .A2(\sel_0$1439 ), + .B1(1'h0), + .B2(\sel_1$1440 ), + .Y(\t$2109 ) + ); + XOR2x1_ASAP7_75t_R \U$812 ( + .A(\t$2109 ), + .B(a_registered[7]), + .Y(booth_b6_m32) + ); + INVx1_ASAP7_75t_R \U$813 ( + .A(a_registered[7]), + .Y(\notsign$806 ) + ); + INVx1_ASAP7_75t_R \U$814 ( + .A(a_registered[7]), + .Y(\$13 ) + ); + INVx1_ASAP7_75t_R \U$815 ( + .A(a_registered[8]), + .Y(\$14 ) + ); + INVx1_ASAP7_75t_R \U$816 ( + .A(a_registered[9]), + .Y(\$15 ) + ); + AO33x2_ASAP7_75t_R \U$817 ( + .A1(\$15 ), + .A2(a_registered[8]), + .A3(a_registered[7]), + .B1(a_registered[9]), + .B2(\$14 ), + .B3(\$13 ), + .Y(\sel_0$1476 ) + ); + XOR2x1_ASAP7_75t_R \U$818 ( + .A(a_registered[8]), + .B(a_registered[7]), + .Y(\sel_1$1477 ) + ); + AO22x1_ASAP7_75t_R \U$819 ( + .A1(1'h0), + .A2(\sel_0$1476 ), + .B1(b_registered[0]), + .B2(\sel_1$1477 ), + .Y(\t$2111 ) + ); + XOR2x1_ASAP7_75t_R \U$820 ( + .A(\t$2111 ), + .B(a_registered[9]), + .Y(booth_b8_m0) + ); + AO22x1_ASAP7_75t_R \U$821 ( + .A1(b_registered[0]), + .A2(\sel_0$1476 ), + .B1(b_registered[1]), + .B2(\sel_1$1477 ), + .Y(\t$2112 ) + ); + XOR2x1_ASAP7_75t_R \U$822 ( + .A(\t$2112 ), + .B(a_registered[9]), + .Y(booth_b8_m1) + ); + AO22x1_ASAP7_75t_R \U$823 ( + .A1(b_registered[1]), + .A2(\sel_0$1476 ), + .B1(b_registered[2]), + .B2(\sel_1$1477 ), + .Y(\t$2113 ) + ); + XOR2x1_ASAP7_75t_R \U$824 ( + .A(\t$2113 ), + .B(a_registered[9]), + .Y(booth_b8_m2) + ); + AO22x1_ASAP7_75t_R \U$825 ( + .A1(b_registered[2]), + .A2(\sel_0$1476 ), + .B1(b_registered[3]), + .B2(\sel_1$1477 ), + .Y(\t$2114 ) + ); + XOR2x1_ASAP7_75t_R \U$826 ( + .A(\t$2114 ), + .B(a_registered[9]), + .Y(booth_b8_m3) + ); + AO22x1_ASAP7_75t_R \U$827 ( + .A1(b_registered[3]), + .A2(\sel_0$1476 ), + .B1(b_registered[4]), + .B2(\sel_1$1477 ), + .Y(\t$2115 ) + ); + XOR2x1_ASAP7_75t_R \U$828 ( + .A(\t$2115 ), + .B(a_registered[9]), + .Y(booth_b8_m4) + ); + AO22x1_ASAP7_75t_R \U$829 ( + .A1(b_registered[4]), + .A2(\sel_0$1476 ), + .B1(b_registered[5]), + .B2(\sel_1$1477 ), + .Y(\t$2116 ) + ); + XOR2x1_ASAP7_75t_R \U$830 ( + .A(\t$2116 ), + .B(a_registered[9]), + .Y(booth_b8_m5) + ); + AO22x1_ASAP7_75t_R \U$831 ( + .A1(b_registered[5]), + .A2(\sel_0$1476 ), + .B1(b_registered[6]), + .B2(\sel_1$1477 ), + .Y(\t$2117 ) + ); + XOR2x1_ASAP7_75t_R \U$832 ( + .A(\t$2117 ), + .B(a_registered[9]), + .Y(booth_b8_m6) + ); + AO22x1_ASAP7_75t_R \U$833 ( + .A1(b_registered[6]), + .A2(\sel_0$1476 ), + .B1(b_registered[7]), + .B2(\sel_1$1477 ), + .Y(\t$2118 ) + ); + XOR2x1_ASAP7_75t_R \U$834 ( + .A(\t$2118 ), + .B(a_registered[9]), + .Y(booth_b8_m7) + ); + AO22x1_ASAP7_75t_R \U$835 ( + .A1(b_registered[7]), + .A2(\sel_0$1476 ), + .B1(b_registered[8]), + .B2(\sel_1$1477 ), + .Y(\t$2119 ) + ); + XOR2x1_ASAP7_75t_R \U$836 ( + .A(\t$2119 ), + .B(a_registered[9]), + .Y(booth_b8_m8) + ); + AO22x1_ASAP7_75t_R \U$837 ( + .A1(b_registered[8]), + .A2(\sel_0$1476 ), + .B1(b_registered[9]), + .B2(\sel_1$1477 ), + .Y(\t$2120 ) + ); + XOR2x1_ASAP7_75t_R \U$838 ( + .A(\t$2120 ), + .B(a_registered[9]), + .Y(booth_b8_m9) + ); + AO22x1_ASAP7_75t_R \U$839 ( + .A1(b_registered[9]), + .A2(\sel_0$1476 ), + .B1(b_registered[10]), + .B2(\sel_1$1477 ), + .Y(\t$2121 ) + ); + XOR2x1_ASAP7_75t_R \U$840 ( + .A(\t$2121 ), + .B(a_registered[9]), + .Y(booth_b8_m10) + ); + AO22x1_ASAP7_75t_R \U$841 ( + .A1(b_registered[10]), + .A2(\sel_0$1476 ), + .B1(b_registered[11]), + .B2(\sel_1$1477 ), + .Y(\t$2122 ) + ); + XOR2x1_ASAP7_75t_R \U$842 ( + .A(\t$2122 ), + .B(a_registered[9]), + .Y(booth_b8_m11) + ); + AO22x1_ASAP7_75t_R \U$843 ( + .A1(b_registered[11]), + .A2(\sel_0$1476 ), + .B1(b_registered[12]), + .B2(\sel_1$1477 ), + .Y(\t$2123 ) + ); + XOR2x1_ASAP7_75t_R \U$844 ( + .A(\t$2123 ), + .B(a_registered[9]), + .Y(booth_b8_m12) + ); + AO22x1_ASAP7_75t_R \U$845 ( + .A1(b_registered[12]), + .A2(\sel_0$1476 ), + .B1(b_registered[13]), + .B2(\sel_1$1477 ), + .Y(\t$2124 ) + ); + XOR2x1_ASAP7_75t_R \U$846 ( + .A(\t$2124 ), + .B(a_registered[9]), + .Y(booth_b8_m13) + ); + AO22x1_ASAP7_75t_R \U$847 ( + .A1(b_registered[13]), + .A2(\sel_0$1476 ), + .B1(b_registered[14]), + .B2(\sel_1$1477 ), + .Y(\t$2125 ) + ); + XOR2x1_ASAP7_75t_R \U$848 ( + .A(\t$2125 ), + .B(a_registered[9]), + .Y(booth_b8_m14) + ); + AO22x1_ASAP7_75t_R \U$849 ( + .A1(b_registered[14]), + .A2(\sel_0$1476 ), + .B1(b_registered[15]), + .B2(\sel_1$1477 ), + .Y(\t$2126 ) + ); + XOR2x1_ASAP7_75t_R \U$850 ( + .A(\t$2126 ), + .B(a_registered[9]), + .Y(booth_b8_m15) + ); + AO22x1_ASAP7_75t_R \U$851 ( + .A1(b_registered[15]), + .A2(\sel_0$1476 ), + .B1(b_registered[16]), + .B2(\sel_1$1477 ), + .Y(\t$2127 ) + ); + XOR2x1_ASAP7_75t_R \U$852 ( + .A(\t$2127 ), + .B(a_registered[9]), + .Y(booth_b8_m16) + ); + AO22x1_ASAP7_75t_R \U$853 ( + .A1(b_registered[16]), + .A2(\sel_0$1476 ), + .B1(b_registered[17]), + .B2(\sel_1$1477 ), + .Y(\t$2128 ) + ); + XOR2x1_ASAP7_75t_R \U$854 ( + .A(\t$2128 ), + .B(a_registered[9]), + .Y(booth_b8_m17) + ); + AO22x1_ASAP7_75t_R \U$855 ( + .A1(b_registered[17]), + .A2(\sel_0$1476 ), + .B1(b_registered[18]), + .B2(\sel_1$1477 ), + .Y(\t$2129 ) + ); + XOR2x1_ASAP7_75t_R \U$856 ( + .A(\t$2129 ), + .B(a_registered[9]), + .Y(booth_b8_m18) + ); + AO22x1_ASAP7_75t_R \U$857 ( + .A1(b_registered[18]), + .A2(\sel_0$1476 ), + .B1(b_registered[19]), + .B2(\sel_1$1477 ), + .Y(\t$2130 ) + ); + XOR2x1_ASAP7_75t_R \U$858 ( + .A(\t$2130 ), + .B(a_registered[9]), + .Y(booth_b8_m19) + ); + AO22x1_ASAP7_75t_R \U$859 ( + .A1(b_registered[19]), + .A2(\sel_0$1476 ), + .B1(b_registered[20]), + .B2(\sel_1$1477 ), + .Y(\t$2131 ) + ); + XOR2x1_ASAP7_75t_R \U$860 ( + .A(\t$2131 ), + .B(a_registered[9]), + .Y(booth_b8_m20) + ); + AO22x1_ASAP7_75t_R \U$861 ( + .A1(b_registered[20]), + .A2(\sel_0$1476 ), + .B1(b_registered[21]), + .B2(\sel_1$1477 ), + .Y(\t$2132 ) + ); + XOR2x1_ASAP7_75t_R \U$862 ( + .A(\t$2132 ), + .B(a_registered[9]), + .Y(booth_b8_m21) + ); + AO22x1_ASAP7_75t_R \U$863 ( + .A1(b_registered[21]), + .A2(\sel_0$1476 ), + .B1(b_registered[22]), + .B2(\sel_1$1477 ), + .Y(\t$2133 ) + ); + XOR2x1_ASAP7_75t_R \U$864 ( + .A(\t$2133 ), + .B(a_registered[9]), + .Y(booth_b8_m22) + ); + AO22x1_ASAP7_75t_R \U$865 ( + .A1(b_registered[22]), + .A2(\sel_0$1476 ), + .B1(b_registered[23]), + .B2(\sel_1$1477 ), + .Y(\t$2134 ) + ); + XOR2x1_ASAP7_75t_R \U$866 ( + .A(\t$2134 ), + .B(a_registered[9]), + .Y(booth_b8_m23) + ); + AO22x1_ASAP7_75t_R \U$867 ( + .A1(b_registered[23]), + .A2(\sel_0$1476 ), + .B1(b_registered[24]), + .B2(\sel_1$1477 ), + .Y(\t$2135 ) + ); + XOR2x1_ASAP7_75t_R \U$868 ( + .A(\t$2135 ), + .B(a_registered[9]), + .Y(booth_b8_m24) + ); + AO22x1_ASAP7_75t_R \U$869 ( + .A1(b_registered[24]), + .A2(\sel_0$1476 ), + .B1(b_registered[25]), + .B2(\sel_1$1477 ), + .Y(\t$2136 ) + ); + XOR2x1_ASAP7_75t_R \U$870 ( + .A(\t$2136 ), + .B(a_registered[9]), + .Y(booth_b8_m25) + ); + AO22x1_ASAP7_75t_R \U$871 ( + .A1(b_registered[25]), + .A2(\sel_0$1476 ), + .B1(b_registered[26]), + .B2(\sel_1$1477 ), + .Y(\t$2137 ) + ); + XOR2x1_ASAP7_75t_R \U$872 ( + .A(\t$2137 ), + .B(a_registered[9]), + .Y(booth_b8_m26) + ); + AO22x1_ASAP7_75t_R \U$873 ( + .A1(b_registered[26]), + .A2(\sel_0$1476 ), + .B1(b_registered[27]), + .B2(\sel_1$1477 ), + .Y(\t$2138 ) + ); + XOR2x1_ASAP7_75t_R \U$874 ( + .A(\t$2138 ), + .B(a_registered[9]), + .Y(booth_b8_m27) + ); + AO22x1_ASAP7_75t_R \U$875 ( + .A1(b_registered[27]), + .A2(\sel_0$1476 ), + .B1(b_registered[28]), + .B2(\sel_1$1477 ), + .Y(\t$2139 ) + ); + XOR2x1_ASAP7_75t_R \U$876 ( + .A(\t$2139 ), + .B(a_registered[9]), + .Y(booth_b8_m28) + ); + AO22x1_ASAP7_75t_R \U$877 ( + .A1(b_registered[28]), + .A2(\sel_0$1476 ), + .B1(b_registered[29]), + .B2(\sel_1$1477 ), + .Y(\t$2140 ) + ); + XOR2x1_ASAP7_75t_R \U$878 ( + .A(\t$2140 ), + .B(a_registered[9]), + .Y(booth_b8_m29) + ); + AO22x1_ASAP7_75t_R \U$879 ( + .A1(b_registered[29]), + .A2(\sel_0$1476 ), + .B1(b_registered[30]), + .B2(\sel_1$1477 ), + .Y(\t$2141 ) + ); + XOR2x1_ASAP7_75t_R \U$880 ( + .A(\t$2141 ), + .B(a_registered[9]), + .Y(booth_b8_m30) + ); + AO22x1_ASAP7_75t_R \U$881 ( + .A1(b_registered[30]), + .A2(\sel_0$1476 ), + .B1(b_registered[31]), + .B2(\sel_1$1477 ), + .Y(\t$2142 ) + ); + XOR2x1_ASAP7_75t_R \U$882 ( + .A(\t$2142 ), + .B(a_registered[9]), + .Y(booth_b8_m31) + ); + AO22x1_ASAP7_75t_R \U$883 ( + .A1(b_registered[31]), + .A2(\sel_0$1476 ), + .B1(1'h0), + .B2(\sel_1$1477 ), + .Y(\t$2143 ) + ); + XOR2x1_ASAP7_75t_R \U$884 ( + .A(\t$2143 ), + .B(a_registered[9]), + .Y(booth_b8_m32) + ); + INVx1_ASAP7_75t_R \U$885 ( + .A(a_registered[9]), + .Y(\notsign$860 ) + ); + INVx1_ASAP7_75t_R \U$886 ( + .A(a_registered[9]), + .Y(\$16 ) + ); + INVx1_ASAP7_75t_R \U$887 ( + .A(a_registered[10]), + .Y(\$17 ) + ); + INVx1_ASAP7_75t_R \U$888 ( + .A(a_registered[11]), + .Y(\$18 ) + ); + AO33x2_ASAP7_75t_R \U$889 ( + .A1(\$18 ), + .A2(a_registered[10]), + .A3(a_registered[9]), + .B1(a_registered[11]), + .B2(\$17 ), + .B3(\$16 ), + .Y(\sel_0$1513 ) + ); + XOR2x1_ASAP7_75t_R \U$890 ( + .A(a_registered[10]), + .B(a_registered[9]), + .Y(\sel_1$1514 ) + ); + AO22x1_ASAP7_75t_R \U$891 ( + .A1(1'h0), + .A2(\sel_0$1513 ), + .B1(b_registered[0]), + .B2(\sel_1$1514 ), + .Y(\t$2145 ) + ); + XOR2x1_ASAP7_75t_R \U$892 ( + .A(\t$2145 ), + .B(a_registered[11]), + .Y(booth_b10_m0) + ); + AO22x1_ASAP7_75t_R \U$893 ( + .A1(b_registered[0]), + .A2(\sel_0$1513 ), + .B1(b_registered[1]), + .B2(\sel_1$1514 ), + .Y(\t$2146 ) + ); + XOR2x1_ASAP7_75t_R \U$894 ( + .A(\t$2146 ), + .B(a_registered[11]), + .Y(booth_b10_m1) + ); + AO22x1_ASAP7_75t_R \U$895 ( + .A1(b_registered[1]), + .A2(\sel_0$1513 ), + .B1(b_registered[2]), + .B2(\sel_1$1514 ), + .Y(\t$2147 ) + ); + XOR2x1_ASAP7_75t_R \U$896 ( + .A(\t$2147 ), + .B(a_registered[11]), + .Y(booth_b10_m2) + ); + AO22x1_ASAP7_75t_R \U$897 ( + .A1(b_registered[2]), + .A2(\sel_0$1513 ), + .B1(b_registered[3]), + .B2(\sel_1$1514 ), + .Y(\t$2148 ) + ); + XOR2x1_ASAP7_75t_R \U$898 ( + .A(\t$2148 ), + .B(a_registered[11]), + .Y(booth_b10_m3) + ); + AO22x1_ASAP7_75t_R \U$899 ( + .A1(b_registered[3]), + .A2(\sel_0$1513 ), + .B1(b_registered[4]), + .B2(\sel_1$1514 ), + .Y(\t$2149 ) + ); + XOR2x1_ASAP7_75t_R \U$900 ( + .A(\t$2149 ), + .B(a_registered[11]), + .Y(booth_b10_m4) + ); + AO22x1_ASAP7_75t_R \U$901 ( + .A1(b_registered[4]), + .A2(\sel_0$1513 ), + .B1(b_registered[5]), + .B2(\sel_1$1514 ), + .Y(\t$2150 ) + ); + XOR2x1_ASAP7_75t_R \U$902 ( + .A(\t$2150 ), + .B(a_registered[11]), + .Y(booth_b10_m5) + ); + AO22x1_ASAP7_75t_R \U$903 ( + .A1(b_registered[5]), + .A2(\sel_0$1513 ), + .B1(b_registered[6]), + .B2(\sel_1$1514 ), + .Y(\t$2151 ) + ); + XOR2x1_ASAP7_75t_R \U$904 ( + .A(\t$2151 ), + .B(a_registered[11]), + .Y(booth_b10_m6) + ); + AO22x1_ASAP7_75t_R \U$905 ( + .A1(b_registered[6]), + .A2(\sel_0$1513 ), + .B1(b_registered[7]), + .B2(\sel_1$1514 ), + .Y(\t$2152 ) + ); + XOR2x1_ASAP7_75t_R \U$906 ( + .A(\t$2152 ), + .B(a_registered[11]), + .Y(booth_b10_m7) + ); + AO22x1_ASAP7_75t_R \U$907 ( + .A1(b_registered[7]), + .A2(\sel_0$1513 ), + .B1(b_registered[8]), + .B2(\sel_1$1514 ), + .Y(\t$2153 ) + ); + XOR2x1_ASAP7_75t_R \U$908 ( + .A(\t$2153 ), + .B(a_registered[11]), + .Y(booth_b10_m8) + ); + AO22x1_ASAP7_75t_R \U$909 ( + .A1(b_registered[8]), + .A2(\sel_0$1513 ), + .B1(b_registered[9]), + .B2(\sel_1$1514 ), + .Y(\t$2154 ) + ); + XOR2x1_ASAP7_75t_R \U$910 ( + .A(\t$2154 ), + .B(a_registered[11]), + .Y(booth_b10_m9) + ); + AO22x1_ASAP7_75t_R \U$911 ( + .A1(b_registered[9]), + .A2(\sel_0$1513 ), + .B1(b_registered[10]), + .B2(\sel_1$1514 ), + .Y(\t$2155 ) + ); + XOR2x1_ASAP7_75t_R \U$912 ( + .A(\t$2155 ), + .B(a_registered[11]), + .Y(booth_b10_m10) + ); + AO22x1_ASAP7_75t_R \U$913 ( + .A1(b_registered[10]), + .A2(\sel_0$1513 ), + .B1(b_registered[11]), + .B2(\sel_1$1514 ), + .Y(\t$2156 ) + ); + XOR2x1_ASAP7_75t_R \U$914 ( + .A(\t$2156 ), + .B(a_registered[11]), + .Y(booth_b10_m11) + ); + AO22x1_ASAP7_75t_R \U$915 ( + .A1(b_registered[11]), + .A2(\sel_0$1513 ), + .B1(b_registered[12]), + .B2(\sel_1$1514 ), + .Y(\t$2157 ) + ); + XOR2x1_ASAP7_75t_R \U$916 ( + .A(\t$2157 ), + .B(a_registered[11]), + .Y(booth_b10_m12) + ); + AO22x1_ASAP7_75t_R \U$917 ( + .A1(b_registered[12]), + .A2(\sel_0$1513 ), + .B1(b_registered[13]), + .B2(\sel_1$1514 ), + .Y(\t$2158 ) + ); + XOR2x1_ASAP7_75t_R \U$918 ( + .A(\t$2158 ), + .B(a_registered[11]), + .Y(booth_b10_m13) + ); + AO22x1_ASAP7_75t_R \U$919 ( + .A1(b_registered[13]), + .A2(\sel_0$1513 ), + .B1(b_registered[14]), + .B2(\sel_1$1514 ), + .Y(\t$2159 ) + ); + XOR2x1_ASAP7_75t_R \U$920 ( + .A(\t$2159 ), + .B(a_registered[11]), + .Y(booth_b10_m14) + ); + AO22x1_ASAP7_75t_R \U$921 ( + .A1(b_registered[14]), + .A2(\sel_0$1513 ), + .B1(b_registered[15]), + .B2(\sel_1$1514 ), + .Y(\t$2160 ) + ); + XOR2x1_ASAP7_75t_R \U$922 ( + .A(\t$2160 ), + .B(a_registered[11]), + .Y(booth_b10_m15) + ); + AO22x1_ASAP7_75t_R \U$923 ( + .A1(b_registered[15]), + .A2(\sel_0$1513 ), + .B1(b_registered[16]), + .B2(\sel_1$1514 ), + .Y(\t$2161 ) + ); + XOR2x1_ASAP7_75t_R \U$924 ( + .A(\t$2161 ), + .B(a_registered[11]), + .Y(booth_b10_m16) + ); + AO22x1_ASAP7_75t_R \U$925 ( + .A1(b_registered[16]), + .A2(\sel_0$1513 ), + .B1(b_registered[17]), + .B2(\sel_1$1514 ), + .Y(\t$2162 ) + ); + XOR2x1_ASAP7_75t_R \U$926 ( + .A(\t$2162 ), + .B(a_registered[11]), + .Y(booth_b10_m17) + ); + AO22x1_ASAP7_75t_R \U$927 ( + .A1(b_registered[17]), + .A2(\sel_0$1513 ), + .B1(b_registered[18]), + .B2(\sel_1$1514 ), + .Y(\t$2163 ) + ); + XOR2x1_ASAP7_75t_R \U$928 ( + .A(\t$2163 ), + .B(a_registered[11]), + .Y(booth_b10_m18) + ); + AO22x1_ASAP7_75t_R \U$929 ( + .A1(b_registered[18]), + .A2(\sel_0$1513 ), + .B1(b_registered[19]), + .B2(\sel_1$1514 ), + .Y(\t$2164 ) + ); + XOR2x1_ASAP7_75t_R \U$930 ( + .A(\t$2164 ), + .B(a_registered[11]), + .Y(booth_b10_m19) + ); + AO22x1_ASAP7_75t_R \U$931 ( + .A1(b_registered[19]), + .A2(\sel_0$1513 ), + .B1(b_registered[20]), + .B2(\sel_1$1514 ), + .Y(\t$2165 ) + ); + XOR2x1_ASAP7_75t_R \U$932 ( + .A(\t$2165 ), + .B(a_registered[11]), + .Y(booth_b10_m20) + ); + AO22x1_ASAP7_75t_R \U$933 ( + .A1(b_registered[20]), + .A2(\sel_0$1513 ), + .B1(b_registered[21]), + .B2(\sel_1$1514 ), + .Y(\t$2166 ) + ); + XOR2x1_ASAP7_75t_R \U$934 ( + .A(\t$2166 ), + .B(a_registered[11]), + .Y(booth_b10_m21) + ); + AO22x1_ASAP7_75t_R \U$935 ( + .A1(b_registered[21]), + .A2(\sel_0$1513 ), + .B1(b_registered[22]), + .B2(\sel_1$1514 ), + .Y(\t$2167 ) + ); + XOR2x1_ASAP7_75t_R \U$936 ( + .A(\t$2167 ), + .B(a_registered[11]), + .Y(booth_b10_m22) + ); + AO22x1_ASAP7_75t_R \U$937 ( + .A1(b_registered[22]), + .A2(\sel_0$1513 ), + .B1(b_registered[23]), + .B2(\sel_1$1514 ), + .Y(\t$2168 ) + ); + XOR2x1_ASAP7_75t_R \U$938 ( + .A(\t$2168 ), + .B(a_registered[11]), + .Y(booth_b10_m23) + ); + AO22x1_ASAP7_75t_R \U$939 ( + .A1(b_registered[23]), + .A2(\sel_0$1513 ), + .B1(b_registered[24]), + .B2(\sel_1$1514 ), + .Y(\t$2169 ) + ); + XOR2x1_ASAP7_75t_R \U$940 ( + .A(\t$2169 ), + .B(a_registered[11]), + .Y(booth_b10_m24) + ); + AO22x1_ASAP7_75t_R \U$941 ( + .A1(b_registered[24]), + .A2(\sel_0$1513 ), + .B1(b_registered[25]), + .B2(\sel_1$1514 ), + .Y(\t$2170 ) + ); + XOR2x1_ASAP7_75t_R \U$942 ( + .A(\t$2170 ), + .B(a_registered[11]), + .Y(booth_b10_m25) + ); + AO22x1_ASAP7_75t_R \U$943 ( + .A1(b_registered[25]), + .A2(\sel_0$1513 ), + .B1(b_registered[26]), + .B2(\sel_1$1514 ), + .Y(\t$2171 ) + ); + XOR2x1_ASAP7_75t_R \U$944 ( + .A(\t$2171 ), + .B(a_registered[11]), + .Y(booth_b10_m26) + ); + AO22x1_ASAP7_75t_R \U$945 ( + .A1(b_registered[26]), + .A2(\sel_0$1513 ), + .B1(b_registered[27]), + .B2(\sel_1$1514 ), + .Y(\t$2172 ) + ); + XOR2x1_ASAP7_75t_R \U$946 ( + .A(\t$2172 ), + .B(a_registered[11]), + .Y(booth_b10_m27) + ); + AO22x1_ASAP7_75t_R \U$947 ( + .A1(b_registered[27]), + .A2(\sel_0$1513 ), + .B1(b_registered[28]), + .B2(\sel_1$1514 ), + .Y(\t$2173 ) + ); + XOR2x1_ASAP7_75t_R \U$948 ( + .A(\t$2173 ), + .B(a_registered[11]), + .Y(booth_b10_m28) + ); + AO22x1_ASAP7_75t_R \U$949 ( + .A1(b_registered[28]), + .A2(\sel_0$1513 ), + .B1(b_registered[29]), + .B2(\sel_1$1514 ), + .Y(\t$2174 ) + ); + XOR2x1_ASAP7_75t_R \U$950 ( + .A(\t$2174 ), + .B(a_registered[11]), + .Y(booth_b10_m29) + ); + AO22x1_ASAP7_75t_R \U$951 ( + .A1(b_registered[29]), + .A2(\sel_0$1513 ), + .B1(b_registered[30]), + .B2(\sel_1$1514 ), + .Y(\t$2175 ) + ); + XOR2x1_ASAP7_75t_R \U$952 ( + .A(\t$2175 ), + .B(a_registered[11]), + .Y(booth_b10_m30) + ); + AO22x1_ASAP7_75t_R \U$953 ( + .A1(b_registered[30]), + .A2(\sel_0$1513 ), + .B1(b_registered[31]), + .B2(\sel_1$1514 ), + .Y(\t$2176 ) + ); + XOR2x1_ASAP7_75t_R \U$954 ( + .A(\t$2176 ), + .B(a_registered[11]), + .Y(booth_b10_m31) + ); + AO22x1_ASAP7_75t_R \U$955 ( + .A1(b_registered[31]), + .A2(\sel_0$1513 ), + .B1(1'h0), + .B2(\sel_1$1514 ), + .Y(\t$2177 ) + ); + XOR2x1_ASAP7_75t_R \U$956 ( + .A(\t$2177 ), + .B(a_registered[11]), + .Y(booth_b10_m32) + ); + INVx1_ASAP7_75t_R \U$957 ( + .A(a_registered[11]), + .Y(\notsign$910 ) + ); + INVx1_ASAP7_75t_R \U$958 ( + .A(a_registered[11]), + .Y(\$19 ) + ); + INVx1_ASAP7_75t_R \U$959 ( + .A(a_registered[12]), + .Y(\$20 ) + ); + INVx1_ASAP7_75t_R \U$960 ( + .A(a_registered[13]), + .Y(\$21 ) + ); + AO33x2_ASAP7_75t_R \U$961 ( + .A1(\$21 ), + .A2(a_registered[12]), + .A3(a_registered[11]), + .B1(a_registered[13]), + .B2(\$20 ), + .B3(\$19 ), + .Y(\sel_0$1550 ) + ); + XOR2x1_ASAP7_75t_R \U$962 ( + .A(a_registered[12]), + .B(a_registered[11]), + .Y(\sel_1$1551 ) + ); + AO22x1_ASAP7_75t_R \U$963 ( + .A1(1'h0), + .A2(\sel_0$1550 ), + .B1(b_registered[0]), + .B2(\sel_1$1551 ), + .Y(\t$2179 ) + ); + XOR2x1_ASAP7_75t_R \U$964 ( + .A(\t$2179 ), + .B(a_registered[13]), + .Y(booth_b12_m0) + ); + AO22x1_ASAP7_75t_R \U$965 ( + .A1(b_registered[0]), + .A2(\sel_0$1550 ), + .B1(b_registered[1]), + .B2(\sel_1$1551 ), + .Y(\t$2180 ) + ); + XOR2x1_ASAP7_75t_R \U$966 ( + .A(\t$2180 ), + .B(a_registered[13]), + .Y(booth_b12_m1) + ); + AO22x1_ASAP7_75t_R \U$967 ( + .A1(b_registered[1]), + .A2(\sel_0$1550 ), + .B1(b_registered[2]), + .B2(\sel_1$1551 ), + .Y(\t$2181 ) + ); + XOR2x1_ASAP7_75t_R \U$968 ( + .A(\t$2181 ), + .B(a_registered[13]), + .Y(booth_b12_m2) + ); + AO22x1_ASAP7_75t_R \U$969 ( + .A1(b_registered[2]), + .A2(\sel_0$1550 ), + .B1(b_registered[3]), + .B2(\sel_1$1551 ), + .Y(\t$2182 ) + ); + XOR2x1_ASAP7_75t_R \U$970 ( + .A(\t$2182 ), + .B(a_registered[13]), + .Y(booth_b12_m3) + ); + AO22x1_ASAP7_75t_R \U$971 ( + .A1(b_registered[3]), + .A2(\sel_0$1550 ), + .B1(b_registered[4]), + .B2(\sel_1$1551 ), + .Y(\t$2183 ) + ); + XOR2x1_ASAP7_75t_R \U$972 ( + .A(\t$2183 ), + .B(a_registered[13]), + .Y(booth_b12_m4) + ); + AO22x1_ASAP7_75t_R \U$973 ( + .A1(b_registered[4]), + .A2(\sel_0$1550 ), + .B1(b_registered[5]), + .B2(\sel_1$1551 ), + .Y(\t$2184 ) + ); + XOR2x1_ASAP7_75t_R \U$974 ( + .A(\t$2184 ), + .B(a_registered[13]), + .Y(booth_b12_m5) + ); + AO22x1_ASAP7_75t_R \U$975 ( + .A1(b_registered[5]), + .A2(\sel_0$1550 ), + .B1(b_registered[6]), + .B2(\sel_1$1551 ), + .Y(\t$2185 ) + ); + XOR2x1_ASAP7_75t_R \U$976 ( + .A(\t$2185 ), + .B(a_registered[13]), + .Y(booth_b12_m6) + ); + AO22x1_ASAP7_75t_R \U$977 ( + .A1(b_registered[6]), + .A2(\sel_0$1550 ), + .B1(b_registered[7]), + .B2(\sel_1$1551 ), + .Y(\t$2186 ) + ); + XOR2x1_ASAP7_75t_R \U$978 ( + .A(\t$2186 ), + .B(a_registered[13]), + .Y(booth_b12_m7) + ); + AO22x1_ASAP7_75t_R \U$979 ( + .A1(b_registered[7]), + .A2(\sel_0$1550 ), + .B1(b_registered[8]), + .B2(\sel_1$1551 ), + .Y(\t$2187 ) + ); + XOR2x1_ASAP7_75t_R \U$980 ( + .A(\t$2187 ), + .B(a_registered[13]), + .Y(booth_b12_m8) + ); + AO22x1_ASAP7_75t_R \U$981 ( + .A1(b_registered[8]), + .A2(\sel_0$1550 ), + .B1(b_registered[9]), + .B2(\sel_1$1551 ), + .Y(\t$2188 ) + ); + XOR2x1_ASAP7_75t_R \U$982 ( + .A(\t$2188 ), + .B(a_registered[13]), + .Y(booth_b12_m9) + ); + AO22x1_ASAP7_75t_R \U$983 ( + .A1(b_registered[9]), + .A2(\sel_0$1550 ), + .B1(b_registered[10]), + .B2(\sel_1$1551 ), + .Y(\t$2189 ) + ); + XOR2x1_ASAP7_75t_R \U$984 ( + .A(\t$2189 ), + .B(a_registered[13]), + .Y(booth_b12_m10) + ); + AO22x1_ASAP7_75t_R \U$985 ( + .A1(b_registered[10]), + .A2(\sel_0$1550 ), + .B1(b_registered[11]), + .B2(\sel_1$1551 ), + .Y(\t$2190 ) + ); + XOR2x1_ASAP7_75t_R \U$986 ( + .A(\t$2190 ), + .B(a_registered[13]), + .Y(booth_b12_m11) + ); + AO22x1_ASAP7_75t_R \U$987 ( + .A1(b_registered[11]), + .A2(\sel_0$1550 ), + .B1(b_registered[12]), + .B2(\sel_1$1551 ), + .Y(\t$2191 ) + ); + XOR2x1_ASAP7_75t_R \U$988 ( + .A(\t$2191 ), + .B(a_registered[13]), + .Y(booth_b12_m12) + ); + AO22x1_ASAP7_75t_R \U$989 ( + .A1(b_registered[12]), + .A2(\sel_0$1550 ), + .B1(b_registered[13]), + .B2(\sel_1$1551 ), + .Y(\t$2192 ) + ); + XOR2x1_ASAP7_75t_R \U$990 ( + .A(\t$2192 ), + .B(a_registered[13]), + .Y(booth_b12_m13) + ); + AO22x1_ASAP7_75t_R \U$991 ( + .A1(b_registered[13]), + .A2(\sel_0$1550 ), + .B1(b_registered[14]), + .B2(\sel_1$1551 ), + .Y(\t$2193 ) + ); + XOR2x1_ASAP7_75t_R \U$992 ( + .A(\t$2193 ), + .B(a_registered[13]), + .Y(booth_b12_m14) + ); + AO22x1_ASAP7_75t_R \U$993 ( + .A1(b_registered[14]), + .A2(\sel_0$1550 ), + .B1(b_registered[15]), + .B2(\sel_1$1551 ), + .Y(\t$2194 ) + ); + XOR2x1_ASAP7_75t_R \U$994 ( + .A(\t$2194 ), + .B(a_registered[13]), + .Y(booth_b12_m15) + ); + AO22x1_ASAP7_75t_R \U$995 ( + .A1(b_registered[15]), + .A2(\sel_0$1550 ), + .B1(b_registered[16]), + .B2(\sel_1$1551 ), + .Y(\t$2195 ) + ); + XOR2x1_ASAP7_75t_R \U$996 ( + .A(\t$2195 ), + .B(a_registered[13]), + .Y(booth_b12_m16) + ); + AO22x1_ASAP7_75t_R \U$997 ( + .A1(b_registered[16]), + .A2(\sel_0$1550 ), + .B1(b_registered[17]), + .B2(\sel_1$1551 ), + .Y(\t$2196 ) + ); + XOR2x1_ASAP7_75t_R \U$998 ( + .A(\t$2196 ), + .B(a_registered[13]), + .Y(booth_b12_m17) + ); + AO22x1_ASAP7_75t_R \U$999 ( + .A1(b_registered[17]), + .A2(\sel_0$1550 ), + .B1(b_registered[18]), + .B2(\sel_1$1551 ), + .Y(\t$2197 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_26_0 ( + .A(pp_row26_0), + .B(pp_row26_1), + .CI(pp_row26_2), + .CON(\con$2560 ), + .SN(\sn$2562 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_27_0 ( + .A(pp_row27_0), + .B(pp_row27_1), + .CI(pp_row27_2), + .CON(\con$2568 ), + .SN(\sn$2570 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_28_0 ( + .A(pp_row28_0), + .B(pp_row28_1), + .CI(pp_row28_2), + .CON(\con$2576 ), + .SN(\sn$2578 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_28_1 ( + .A(pp_row28_3), + .B(pp_row28_4), + .CI(pp_row28_5), + .CON(\con$2580 ), + .SN(\sn$2582 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_29_0 ( + .A(pp_row29_0), + .B(pp_row29_1), + .CI(pp_row29_2), + .CON(\con$2588 ), + .SN(\sn$2590 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_29_1 ( + .A(pp_row29_3), + .B(pp_row29_4), + .CI(pp_row29_5), + .CON(\con$2592 ), + .SN(\sn$2594 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_0 ( + .A(pp_row30_0), + .B(pp_row30_1), + .CI(pp_row30_2), + .CON(\con$2600 ), + .SN(\sn$2602 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_1 ( + .A(pp_row30_3), + .B(pp_row30_4), + .CI(pp_row30_5), + .CON(\con$2604 ), + .SN(\sn$2606 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_30_2 ( + .A(pp_row30_6), + .B(pp_row30_7), + .CI(pp_row30_8), + .CON(\con$2608 ), + .SN(\sn$2610 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_0 ( + .A(pp_row31_0), + .B(pp_row31_1), + .CI(pp_row31_2), + .CON(\con$2616 ), + .SN(\sn$2618 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_1 ( + .A(pp_row31_3), + .B(pp_row31_4), + .CI(pp_row31_5), + .CON(\con$2620 ), + .SN(\sn$2622 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_31_2 ( + .A(pp_row31_6), + .B(pp_row31_7), + .CI(pp_row31_8), + .CON(\con$2624 ), + .SN(\sn$2626 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_0 ( + .A(pp_row32_0), + .B(pp_row32_1), + .CI(pp_row32_2), + .CON(\con$2632 ), + .SN(\sn$2634 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_1 ( + .A(pp_row32_3), + .B(pp_row32_4), + .CI(pp_row32_5), + .CON(\con$2636 ), + .SN(\sn$2638 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_2 ( + .A(pp_row32_6), + .B(pp_row32_7), + .CI(pp_row32_8), + .CON(\con$2640 ), + .SN(\sn$2642 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_32_3 ( + .A(pp_row32_9), + .B(pp_row32_10), + .CI(pp_row32_11), + .CON(\con$2644 ), + .SN(\sn$2646 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_0 ( + .A(pp_row33_0), + .B(pp_row33_1), + .CI(pp_row33_2), + .CON(\con$2648 ), + .SN(\sn$2650 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_1 ( + .A(pp_row33_3), + .B(pp_row33_4), + .CI(pp_row33_5), + .CON(\con$2652 ), + .SN(\sn$2654 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_2 ( + .A(pp_row33_6), + .B(pp_row33_7), + .CI(pp_row33_8), + .CON(\con$2656 ), + .SN(\sn$2658 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_33_3 ( + .A(pp_row33_9), + .B(pp_row33_10), + .CI(pp_row33_11), + .CON(\con$2660 ), + .SN(\sn$2662 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_0 ( + .A(pp_row34_0), + .B(pp_row34_1), + .CI(pp_row34_2), + .CON(\con$2664 ), + .SN(\sn$2666 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_1 ( + .A(pp_row34_3), + .B(pp_row34_4), + .CI(pp_row34_5), + .CON(\con$2668 ), + .SN(\sn$2670 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_2 ( + .A(pp_row34_6), + .B(pp_row34_7), + .CI(pp_row34_8), + .CON(\con$2672 ), + .SN(\sn$2674 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_34_3 ( + .A(pp_row34_9), + .B(pp_row34_10), + .CI(pp_row34_11), + .CON(\con$2676 ), + .SN(\sn$2678 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_0 ( + .A(pp_row35_0), + .B(pp_row35_1), + .CI(pp_row35_2), + .CON(\con$2680 ), + .SN(\sn$2682 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_1 ( + .A(pp_row35_3), + .B(pp_row35_4), + .CI(pp_row35_5), + .CON(\con$2684 ), + .SN(\sn$2686 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_2 ( + .A(pp_row35_6), + .B(pp_row35_7), + .CI(pp_row35_8), + .CON(\con$2688 ), + .SN(\sn$2690 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_35_3 ( + .A(pp_row35_9), + .B(pp_row35_10), + .CI(pp_row35_11), + .CON(\con$2692 ), + .SN(\sn$2694 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_0 ( + .A(1'h1), + .B(pp_row36_1), + .CI(pp_row36_2), + .CON(\con$2696 ), + .SN(\sn$2698 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_1 ( + .A(pp_row36_3), + .B(pp_row36_4), + .CI(pp_row36_5), + .CON(\con$2700 ), + .SN(\sn$2702 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_36_2 ( + .A(pp_row36_6), + .B(pp_row36_7), + .CI(pp_row36_8), + .CON(\con$2704 ), + .SN(\sn$2706 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_0 ( + .A(pp_row37_0), + .B(pp_row37_1), + .CI(pp_row37_2), + .CON(\con$2712 ), + .SN(\sn$2714 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_1 ( + .A(pp_row37_3), + .B(pp_row37_4), + .CI(pp_row37_5), + .CON(\con$2716 ), + .SN(\sn$2718 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_37_2 ( + .A(pp_row37_6), + .B(pp_row37_7), + .CI(pp_row37_8), + .CON(\con$2720 ), + .SN(\sn$2722 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_38_0 ( + .A(1'h1), + .B(pp_row38_1), + .CI(pp_row38_2), + .CON(\con$2724 ), + .SN(\sn$2726 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_38_1 ( + .A(pp_row38_3), + .B(pp_row38_4), + .CI(pp_row38_5), + .CON(\con$2728 ), + .SN(\sn$2730 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_39_0 ( + .A(pp_row39_0), + .B(pp_row39_1), + .CI(pp_row39_2), + .CON(\con$2736 ), + .SN(\sn$2738 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_39_1 ( + .A(pp_row39_3), + .B(pp_row39_4), + .CI(pp_row39_5), + .CON(\con$2740 ), + .SN(\sn$2742 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_40_0 ( + .A(1'h1), + .B(pp_row40_1), + .CI(pp_row40_2), + .CON(\con$2744 ), + .SN(\sn$2746 ) + ); + FAx1_ASAP7_75t_R dadda_fa_0_41_0 ( + .A(pp_row41_0), + .B(pp_row41_1), + .CI(pp_row41_2), + .CON(\con$2752 ), + .SN(\sn$2754 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_18_0 ( + .A(pp_row18_0), + .B(pp_row18_1), + .CI(pp_row18_2), + .CON(\con$2768 ), + .SN(\sn$2770 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_19_0 ( + .A(pp_row19_0), + .B(pp_row19_1), + .CI(pp_row19_2), + .CON(\con$2776 ), + .SN(\sn$2778 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_20_0 ( + .A(pp_row20_0), + .B(pp_row20_1), + .CI(pp_row20_2), + .CON(\con$2784 ), + .SN(\sn$2786 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_20_1 ( + .A(pp_row20_3), + .B(pp_row20_4), + .CI(pp_row20_5), + .CON(\con$2788 ), + .SN(\sn$2790 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_21_0 ( + .A(pp_row21_0), + .B(pp_row21_1), + .CI(pp_row21_2), + .CON(\con$2796 ), + .SN(\sn$2798 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_21_1 ( + .A(pp_row21_3), + .B(pp_row21_4), + .CI(pp_row21_5), + .CON(\con$2800 ), + .SN(\sn$2802 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_0 ( + .A(pp_row22_0), + .B(pp_row22_1), + .CI(pp_row22_2), + .CON(\con$2808 ), + .SN(\sn$2810 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_1 ( + .A(pp_row22_3), + .B(pp_row22_4), + .CI(pp_row22_5), + .CON(\con$2812 ), + .SN(\sn$2814 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_22_2 ( + .A(pp_row22_6), + .B(pp_row22_7), + .CI(pp_row22_8), + .CON(\con$2816 ), + .SN(\sn$2818 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_0 ( + .A(pp_row23_0), + .B(pp_row23_1), + .CI(pp_row23_2), + .CON(\con$2824 ), + .SN(\sn$2826 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_1 ( + .A(pp_row23_3), + .B(pp_row23_4), + .CI(pp_row23_5), + .CON(\con$2828 ), + .SN(\sn$2830 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_23_2 ( + .A(pp_row23_6), + .B(pp_row23_7), + .CI(pp_row23_8), + .CON(\con$2832 ), + .SN(\sn$2834 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_0 ( + .A(pp_row24_2), + .B(pp_row24_3), + .CI(pp_row24_4), + .CON(\con$2840 ), + .SN(\sn$2842 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_1 ( + .A(pp_row24_5), + .B(pp_row24_6), + .CI(pp_row24_7), + .CON(\con$2844 ), + .SN(\sn$2846 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_2 ( + .A(pp_row24_8), + .B(pp_row24_9), + .CI(pp_row24_10), + .CON(\con$2848 ), + .SN(\sn$2850 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_24_3 ( + .A(pp_row24_11), + .B(pp_row24_12), + .CI(pp_row24_13), + .CON(\con$2852 ), + .SN(\sn$2854 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_0 ( + .A(pp_row25_2), + .B(pp_row25_3), + .CI(pp_row25_4), + .CON(\con$2856 ), + .SN(\sn$2858 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_1 ( + .A(pp_row25_5), + .B(pp_row25_6), + .CI(pp_row25_7), + .CON(\con$2860 ), + .SN(\sn$2862 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_2 ( + .A(pp_row25_8), + .B(pp_row25_9), + .CI(pp_row25_10), + .CON(\con$2864 ), + .SN(\sn$2866 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_25_3 ( + .A(pp_row25_11), + .B(pp_row25_12), + .CI(\c$2553 ), + .CON(\con$2868 ), + .SN(\sn$2870 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_0 ( + .A(pp_row26_5), + .B(pp_row26_6), + .CI(pp_row26_7), + .CON(\con$2872 ), + .SN(\sn$2874 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_1 ( + .A(pp_row26_8), + .B(pp_row26_9), + .CI(pp_row26_10), + .CON(\con$2876 ), + .SN(\sn$2878 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_2 ( + .A(pp_row26_11), + .B(pp_row26_12), + .CI(pp_row26_13), + .CON(\con$2880 ), + .SN(\sn$2882 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_26_3 ( + .A(pp_row26_14), + .B(\c$2557 ), + .CI(\s$2563 ), + .CON(\con$2884 ), + .SN(\sn$2886 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_0 ( + .A(pp_row27_5), + .B(pp_row27_6), + .CI(pp_row27_7), + .CON(\con$2888 ), + .SN(\sn$2890 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_1 ( + .A(pp_row27_8), + .B(pp_row27_9), + .CI(pp_row27_10), + .CON(\con$2892 ), + .SN(\sn$2894 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_2 ( + .A(pp_row27_11), + .B(pp_row27_12), + .CI(pp_row27_13), + .CON(\con$2896 ), + .SN(\sn$2898 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_27_3 ( + .A(\c$2561 ), + .B(\c$2565 ), + .CI(\s$2571 ), + .CON(\con$2900 ), + .SN(\sn$2902 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_0 ( + .A(pp_row28_8), + .B(pp_row28_9), + .CI(pp_row28_10), + .CON(\con$2904 ), + .SN(\sn$2906 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_1 ( + .A(pp_row28_11), + .B(pp_row28_12), + .CI(pp_row28_13), + .CON(\con$2908 ), + .SN(\sn$2910 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_2 ( + .A(pp_row28_14), + .B(pp_row28_15), + .CI(\c$2569 ), + .CON(\con$2912 ), + .SN(\sn$2914 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_28_3 ( + .A(\c$2573 ), + .B(\s$2579 ), + .CI(\s$2583 ), + .CON(\con$2916 ), + .SN(\sn$2918 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_0 ( + .A(pp_row29_8), + .B(pp_row29_9), + .CI(pp_row29_10), + .CON(\con$2920 ), + .SN(\sn$2922 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_1 ( + .A(pp_row29_11), + .B(pp_row29_12), + .CI(pp_row29_13), + .CON(\con$2924 ), + .SN(\sn$2926 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_2 ( + .A(pp_row29_14), + .B(\c$2577 ), + .CI(\c$2581 ), + .CON(\con$2928 ), + .SN(\sn$2930 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_29_3 ( + .A(\c$2585 ), + .B(\s$2591 ), + .CI(\s$2595 ), + .CON(\con$2932 ), + .SN(\sn$2934 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_0 ( + .A(pp_row30_11), + .B(pp_row30_12), + .CI(pp_row30_13), + .CON(\con$2936 ), + .SN(\sn$2938 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_1 ( + .A(pp_row30_14), + .B(pp_row30_15), + .CI(pp_row30_16), + .CON(\con$2940 ), + .SN(\sn$2942 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_2 ( + .A(\c$2589 ), + .B(\c$2593 ), + .CI(\c$2597 ), + .CON(\con$2944 ), + .SN(\sn$2946 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_30_3 ( + .A(\s$2603 ), + .B(\s$2607 ), + .CI(\s$2611 ), + .CON(\con$2948 ), + .SN(\sn$2950 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_0 ( + .A(pp_row31_11), + .B(pp_row31_12), + .CI(pp_row31_13), + .CON(\con$2952 ), + .SN(\sn$2954 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_1 ( + .A(pp_row31_14), + .B(pp_row31_15), + .CI(\c$2601 ), + .CON(\con$2956 ), + .SN(\sn$2958 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_2 ( + .A(\c$2605 ), + .B(\c$2609 ), + .CI(\c$2613 ), + .CON(\con$2960 ), + .SN(\sn$2962 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_31_3 ( + .A(\s$2619 ), + .B(\s$2623 ), + .CI(\s$2627 ), + .CON(\con$2964 ), + .SN(\sn$2966 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_0 ( + .A(pp_row32_12), + .B(pp_row32_13), + .CI(pp_row32_14), + .CON(\con$2968 ), + .SN(\sn$2970 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_1 ( + .A(pp_row32_15), + .B(pp_row32_16), + .CI(\c$2617 ), + .CON(\con$2972 ), + .SN(\sn$2974 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_2 ( + .A(\c$2621 ), + .B(\c$2625 ), + .CI(\c$2629 ), + .CON(\con$2976 ), + .SN(\sn$2978 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_32_3 ( + .A(\s$2635 ), + .B(\s$2639 ), + .CI(\s$2643 ), + .CON(\con$2980 ), + .SN(\sn$2982 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_0 ( + .A(pp_row33_12), + .B(pp_row33_13), + .CI(pp_row33_14), + .CON(\con$2984 ), + .SN(\sn$2986 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_1 ( + .A(pp_row33_15), + .B(pp_row33_16), + .CI(\c$2633 ), + .CON(\con$2988 ), + .SN(\sn$2990 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_2 ( + .A(\c$2637 ), + .B(\c$2641 ), + .CI(\c$2645 ), + .CON(\con$2992 ), + .SN(\sn$2994 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_33_3 ( + .A(\s$2651 ), + .B(\s$2655 ), + .CI(\s$2659 ), + .CON(\con$2996 ), + .SN(\sn$2998 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_0 ( + .A(pp_row34_12), + .B(pp_row34_13), + .CI(pp_row34_14), + .CON(\con$3000 ), + .SN(\sn$3002 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_1 ( + .A(pp_row34_15), + .B(pp_row34_16), + .CI(\c$2649 ), + .CON(\con$3004 ), + .SN(\sn$3006 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_2 ( + .A(\c$2653 ), + .B(\c$2657 ), + .CI(\c$2661 ), + .CON(\con$3008 ), + .SN(\sn$3010 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_34_3 ( + .A(\s$2667 ), + .B(\s$2671 ), + .CI(\s$2675 ), + .CON(\con$3012 ), + .SN(\sn$3014 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_0 ( + .A(pp_row35_12), + .B(pp_row35_13), + .CI(pp_row35_14), + .CON(\con$3016 ), + .SN(\sn$3018 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_1 ( + .A(pp_row35_15), + .B(pp_row35_16), + .CI(\c$2665 ), + .CON(\con$3020 ), + .SN(\sn$3022 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_2 ( + .A(\c$2669 ), + .B(\c$2673 ), + .CI(\c$2677 ), + .CON(\con$3024 ), + .SN(\sn$3026 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_35_3 ( + .A(\s$2683 ), + .B(\s$2687 ), + .CI(\s$2691 ), + .CON(\con$3028 ), + .SN(\sn$3030 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_0 ( + .A(pp_row36_11), + .B(pp_row36_12), + .CI(pp_row36_13), + .CON(\con$3032 ), + .SN(\sn$3034 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_1 ( + .A(pp_row36_14), + .B(pp_row36_15), + .CI(\c$2681 ), + .CON(\con$3036 ), + .SN(\sn$3038 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_2 ( + .A(\c$2685 ), + .B(\c$2689 ), + .CI(\c$2693 ), + .CON(\con$3040 ), + .SN(\sn$3042 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_36_3 ( + .A(\s$2699 ), + .B(\s$2703 ), + .CI(\s$2707 ), + .CON(\con$3044 ), + .SN(\sn$3046 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_0 ( + .A(pp_row37_9), + .B(pp_row37_10), + .CI(pp_row37_11), + .CON(\con$3048 ), + .SN(\sn$3050 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_1 ( + .A(pp_row37_12), + .B(pp_row37_13), + .CI(pp_row37_14), + .CON(\con$3052 ), + .SN(\sn$3054 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_2 ( + .A(\c$2697 ), + .B(\c$2701 ), + .CI(\c$2705 ), + .CON(\con$3056 ), + .SN(\sn$3058 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_37_3 ( + .A(\c$2709 ), + .B(\s$2715 ), + .CI(\s$2719 ), + .CON(\con$3060 ), + .SN(\sn$3062 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_0 ( + .A(pp_row38_8), + .B(pp_row38_9), + .CI(pp_row38_10), + .CON(\con$3064 ), + .SN(\sn$3066 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_1 ( + .A(pp_row38_11), + .B(pp_row38_12), + .CI(pp_row38_13), + .CON(\con$3068 ), + .SN(\sn$3070 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_2 ( + .A(pp_row38_14), + .B(\c$2713 ), + .CI(\c$2717 ), + .CON(\con$3072 ), + .SN(\sn$3074 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_38_3 ( + .A(\c$2721 ), + .B(\s$2727 ), + .CI(\s$2731 ), + .CON(\con$3076 ), + .SN(\sn$3078 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_0 ( + .A(pp_row39_6), + .B(pp_row39_7), + .CI(pp_row39_8), + .CON(\con$3080 ), + .SN(\sn$3082 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_1 ( + .A(pp_row39_9), + .B(pp_row39_10), + .CI(pp_row39_11), + .CON(\con$3084 ), + .SN(\sn$3086 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_2 ( + .A(pp_row39_12), + .B(pp_row39_13), + .CI(\c$2725 ), + .CON(\con$3088 ), + .SN(\sn$3090 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_39_3 ( + .A(\c$2729 ), + .B(\c$2733 ), + .CI(\s$2739 ), + .CON(\con$3092 ), + .SN(\sn$3094 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_0 ( + .A(pp_row40_5), + .B(pp_row40_6), + .CI(pp_row40_7), + .CON(\con$3096 ), + .SN(\sn$3098 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_1 ( + .A(pp_row40_8), + .B(pp_row40_9), + .CI(pp_row40_10), + .CON(\con$3100 ), + .SN(\sn$3102 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_2 ( + .A(pp_row40_11), + .B(pp_row40_12), + .CI(pp_row40_13), + .CON(\con$3104 ), + .SN(\sn$3106 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_40_3 ( + .A(\c$2737 ), + .B(\c$2741 ), + .CI(\s$2747 ), + .CON(\con$3108 ), + .SN(\sn$3110 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_0 ( + .A(pp_row41_3), + .B(pp_row41_4), + .CI(pp_row41_5), + .CON(\con$3112 ), + .SN(\sn$3114 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_1 ( + .A(pp_row41_6), + .B(pp_row41_7), + .CI(pp_row41_8), + .CON(\con$3116 ), + .SN(\sn$3118 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_2 ( + .A(pp_row41_9), + .B(pp_row41_10), + .CI(pp_row41_11), + .CON(\con$3120 ), + .SN(\sn$3122 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_41_3 ( + .A(pp_row41_12), + .B(\c$2745 ), + .CI(\c$2749 ), + .CON(\con$3124 ), + .SN(\sn$3126 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_0 ( + .A(pp_row42_2), + .B(pp_row42_3), + .CI(pp_row42_4), + .CON(\con$3128 ), + .SN(\sn$3130 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_1 ( + .A(pp_row42_5), + .B(pp_row42_6), + .CI(pp_row42_7), + .CON(\con$3132 ), + .SN(\sn$3134 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_2 ( + .A(pp_row42_8), + .B(pp_row42_9), + .CI(pp_row42_10), + .CON(\con$3136 ), + .SN(\sn$3138 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_42_3 ( + .A(pp_row42_11), + .B(pp_row42_12), + .CI(\c$2753 ), + .CON(\con$3140 ), + .SN(\sn$3142 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_0 ( + .A(pp_row43_0), + .B(pp_row43_1), + .CI(pp_row43_2), + .CON(\con$3144 ), + .SN(\sn$3146 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_1 ( + .A(pp_row43_3), + .B(pp_row43_4), + .CI(pp_row43_5), + .CON(\con$3148 ), + .SN(\sn$3150 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_2 ( + .A(pp_row43_6), + .B(pp_row43_7), + .CI(pp_row43_8), + .CON(\con$3152 ), + .SN(\sn$3154 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_43_3 ( + .A(pp_row43_9), + .B(pp_row43_10), + .CI(pp_row43_11), + .CON(\con$3156 ), + .SN(\sn$3158 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_0 ( + .A(1'h1), + .B(pp_row44_1), + .CI(pp_row44_2), + .CON(\con$3160 ), + .SN(\sn$3162 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_1 ( + .A(pp_row44_3), + .B(pp_row44_4), + .CI(pp_row44_5), + .CON(\con$3164 ), + .SN(\sn$3166 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_44_2 ( + .A(pp_row44_6), + .B(pp_row44_7), + .CI(pp_row44_8), + .CON(\con$3168 ), + .SN(\sn$3170 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_0 ( + .A(pp_row45_0), + .B(pp_row45_1), + .CI(pp_row45_2), + .CON(\con$3176 ), + .SN(\sn$3178 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_1 ( + .A(pp_row45_3), + .B(pp_row45_4), + .CI(pp_row45_5), + .CON(\con$3180 ), + .SN(\sn$3182 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_45_2 ( + .A(pp_row45_6), + .B(pp_row45_7), + .CI(pp_row45_8), + .CON(\con$3184 ), + .SN(\sn$3186 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_46_0 ( + .A(1'h1), + .B(pp_row46_1), + .CI(pp_row46_2), + .CON(\con$3188 ), + .SN(\sn$3190 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_46_1 ( + .A(pp_row46_3), + .B(pp_row46_4), + .CI(pp_row46_5), + .CON(\con$3192 ), + .SN(\sn$3194 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_47_0 ( + .A(pp_row47_0), + .B(pp_row47_1), + .CI(pp_row47_2), + .CON(\con$3200 ), + .SN(\sn$3202 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_47_1 ( + .A(pp_row47_3), + .B(pp_row47_4), + .CI(pp_row47_5), + .CON(\con$3204 ), + .SN(\sn$3206 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_48_0 ( + .A(1'h1), + .B(pp_row48_1), + .CI(pp_row48_2), + .CON(\con$3208 ), + .SN(\sn$3210 ) + ); + FAx1_ASAP7_75t_R dadda_fa_1_49_0 ( + .A(pp_row49_0), + .B(pp_row49_1), + .CI(pp_row49_2), + .CON(\con$3216 ), + .SN(\sn$3218 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_12_0 ( + .A(pp_row12_0), + .B(pp_row12_1), + .CI(pp_row12_2), + .CON(\con$3232 ), + .SN(\sn$3234 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_13_0 ( + .A(pp_row13_0), + .B(pp_row13_1), + .CI(pp_row13_2), + .CON(\con$3240 ), + .SN(\sn$3242 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_14_0 ( + .A(pp_row14_0), + .B(pp_row14_1), + .CI(pp_row14_2), + .CON(\con$3248 ), + .SN(\sn$3250 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_14_1 ( + .A(pp_row14_3), + .B(pp_row14_4), + .CI(pp_row14_5), + .CON(\con$3252 ), + .SN(\sn$3254 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_15_0 ( + .A(pp_row15_0), + .B(pp_row15_1), + .CI(pp_row15_2), + .CON(\con$3260 ), + .SN(\sn$3262 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_15_1 ( + .A(pp_row15_3), + .B(pp_row15_4), + .CI(pp_row15_5), + .CON(\con$3264 ), + .SN(\sn$3266 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_0 ( + .A(pp_row16_2), + .B(pp_row16_3), + .CI(pp_row16_4), + .CON(\con$3272 ), + .SN(\sn$3274 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_1 ( + .A(pp_row16_5), + .B(pp_row16_6), + .CI(pp_row16_7), + .CON(\con$3276 ), + .SN(\sn$3278 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_16_2 ( + .A(pp_row16_8), + .B(pp_row16_9), + .CI(\s$2763 ), + .CON(\con$3280 ), + .SN(\sn$3282 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_0 ( + .A(pp_row17_2), + .B(pp_row17_3), + .CI(pp_row17_4), + .CON(\con$3284 ), + .SN(\sn$3286 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_1 ( + .A(pp_row17_5), + .B(pp_row17_6), + .CI(pp_row17_7), + .CON(\con$3288 ), + .SN(\sn$3290 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_17_2 ( + .A(pp_row17_8), + .B(\c$2761 ), + .CI(\s$2767 ), + .CON(\con$3292 ), + .SN(\sn$3294 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_0 ( + .A(pp_row18_5), + .B(pp_row18_6), + .CI(pp_row18_7), + .CON(\con$3296 ), + .SN(\sn$3298 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_1 ( + .A(pp_row18_8), + .B(pp_row18_9), + .CI(pp_row18_10), + .CON(\con$3300 ), + .SN(\sn$3302 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_18_2 ( + .A(\c$2765 ), + .B(\s$2771 ), + .CI(\s$2775 ), + .CON(\con$3304 ), + .SN(\sn$3306 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_0 ( + .A(pp_row19_5), + .B(pp_row19_6), + .CI(pp_row19_7), + .CON(\con$3308 ), + .SN(\sn$3310 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_1 ( + .A(pp_row19_8), + .B(pp_row19_9), + .CI(\c$2769 ), + .CON(\con$3312 ), + .SN(\sn$3314 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_19_2 ( + .A(\c$2773 ), + .B(\s$2779 ), + .CI(\s$2783 ), + .CON(\con$3316 ), + .SN(\sn$3318 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_0 ( + .A(pp_row20_8), + .B(pp_row20_9), + .CI(pp_row20_10), + .CON(\con$3320 ), + .SN(\sn$3322 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_1 ( + .A(pp_row20_11), + .B(\c$2777 ), + .CI(\c$2781 ), + .CON(\con$3324 ), + .SN(\sn$3326 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_20_2 ( + .A(\s$2787 ), + .B(\s$2791 ), + .CI(\s$2795 ), + .CON(\con$3328 ), + .SN(\sn$3330 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_0 ( + .A(pp_row21_8), + .B(pp_row21_9), + .CI(pp_row21_10), + .CON(\con$3332 ), + .SN(\sn$3334 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_1 ( + .A(\c$2785 ), + .B(\c$2789 ), + .CI(\c$2793 ), + .CON(\con$3336 ), + .SN(\sn$3338 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_21_2 ( + .A(\s$2799 ), + .B(\s$2803 ), + .CI(\s$2807 ), + .CON(\con$3340 ), + .SN(\sn$3342 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_0 ( + .A(pp_row22_11), + .B(pp_row22_12), + .CI(\c$2797 ), + .CON(\con$3344 ), + .SN(\sn$3346 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_1 ( + .A(\c$2801 ), + .B(\c$2805 ), + .CI(\s$2811 ), + .CON(\con$3348 ), + .SN(\sn$3350 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_22_2 ( + .A(\s$2815 ), + .B(\s$2819 ), + .CI(\s$2823 ), + .CON(\con$3352 ), + .SN(\sn$3354 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_0 ( + .A(pp_row23_11), + .B(\c$2809 ), + .CI(\c$2813 ), + .CON(\con$3356 ), + .SN(\sn$3358 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_1 ( + .A(\c$2817 ), + .B(\c$2821 ), + .CI(\s$2827 ), + .CON(\con$3360 ), + .SN(\sn$3362 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_23_2 ( + .A(\s$2831 ), + .B(\s$2835 ), + .CI(\s$2839 ), + .CON(\con$3364 ), + .SN(\sn$3366 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_0 ( + .A(\s$2555 ), + .B(\c$2825 ), + .CI(\c$2829 ), + .CON(\con$3368 ), + .SN(\sn$3370 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_1 ( + .A(\c$2833 ), + .B(\c$2837 ), + .CI(\s$2843 ), + .CON(\con$3372 ), + .SN(\sn$3374 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_24_2 ( + .A(\s$2847 ), + .B(\s$2851 ), + .CI(\s$2855 ), + .CON(\con$3376 ), + .SN(\sn$3378 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_0 ( + .A(\s$2559 ), + .B(\c$2841 ), + .CI(\c$2845 ), + .CON(\con$3380 ), + .SN(\sn$3382 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_1 ( + .A(\c$2849 ), + .B(\c$2853 ), + .CI(\s$2859 ), + .CON(\con$3384 ), + .SN(\sn$3386 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_25_2 ( + .A(\s$2863 ), + .B(\s$2867 ), + .CI(\s$2871 ), + .CON(\con$3388 ), + .SN(\sn$3390 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_0 ( + .A(\s$2567 ), + .B(\c$2857 ), + .CI(\c$2861 ), + .CON(\con$3392 ), + .SN(\sn$3394 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_1 ( + .A(\c$2865 ), + .B(\c$2869 ), + .CI(\s$2875 ), + .CON(\con$3396 ), + .SN(\sn$3398 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_26_2 ( + .A(\s$2879 ), + .B(\s$2883 ), + .CI(\s$2887 ), + .CON(\con$3400 ), + .SN(\sn$3402 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_0 ( + .A(\s$2575 ), + .B(\c$2873 ), + .CI(\c$2877 ), + .CON(\con$3404 ), + .SN(\sn$3406 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_1 ( + .A(\c$2881 ), + .B(\c$2885 ), + .CI(\s$2891 ), + .CON(\con$3408 ), + .SN(\sn$3410 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_27_2 ( + .A(\s$2895 ), + .B(\s$2899 ), + .CI(\s$2903 ), + .CON(\con$3412 ), + .SN(\sn$3414 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_0 ( + .A(\s$2587 ), + .B(\c$2889 ), + .CI(\c$2893 ), + .CON(\con$3416 ), + .SN(\sn$3418 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_1 ( + .A(\c$2897 ), + .B(\c$2901 ), + .CI(\s$2907 ), + .CON(\con$3420 ), + .SN(\sn$3422 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_28_2 ( + .A(\s$2911 ), + .B(\s$2915 ), + .CI(\s$2919 ), + .CON(\con$3424 ), + .SN(\sn$3426 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_0 ( + .A(\s$2599 ), + .B(\c$2905 ), + .CI(\c$2909 ), + .CON(\con$3428 ), + .SN(\sn$3430 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_1 ( + .A(\c$2913 ), + .B(\c$2917 ), + .CI(\s$2923 ), + .CON(\con$3432 ), + .SN(\sn$3434 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_29_2 ( + .A(\s$2927 ), + .B(\s$2931 ), + .CI(\s$2935 ), + .CON(\con$3436 ), + .SN(\sn$3438 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_0 ( + .A(\s$2615 ), + .B(\c$2921 ), + .CI(\c$2925 ), + .CON(\con$3440 ), + .SN(\sn$3442 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_1 ( + .A(\c$2929 ), + .B(\c$2933 ), + .CI(\s$2939 ), + .CON(\con$3444 ), + .SN(\sn$3446 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_30_2 ( + .A(\s$2943 ), + .B(\s$2947 ), + .CI(\s$2951 ), + .CON(\con$3448 ), + .SN(\sn$3450 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_0 ( + .A(\s$2631 ), + .B(\c$2937 ), + .CI(\c$2941 ), + .CON(\con$3452 ), + .SN(\sn$3454 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_1 ( + .A(\c$2945 ), + .B(\c$2949 ), + .CI(\s$2955 ), + .CON(\con$3456 ), + .SN(\sn$3458 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_31_2 ( + .A(\s$2959 ), + .B(\s$2963 ), + .CI(\s$2967 ), + .CON(\con$3460 ), + .SN(\sn$3462 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_0 ( + .A(\s$2647 ), + .B(\c$2953 ), + .CI(\c$2957 ), + .CON(\con$3464 ), + .SN(\sn$3466 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_1 ( + .A(\c$2961 ), + .B(\c$2965 ), + .CI(\s$2971 ), + .CON(\con$3468 ), + .SN(\sn$3470 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_32_2 ( + .A(\s$2975 ), + .B(\s$2979 ), + .CI(\s$2983 ), + .CON(\con$3472 ), + .SN(\sn$3474 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_0 ( + .A(\s$2663 ), + .B(\c$2969 ), + .CI(\c$2973 ), + .CON(\con$3476 ), + .SN(\sn$3478 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_1 ( + .A(\c$2977 ), + .B(\c$2981 ), + .CI(\s$2987 ), + .CON(\con$3480 ), + .SN(\sn$3482 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_33_2 ( + .A(\s$2991 ), + .B(\s$2995 ), + .CI(\s$2999 ), + .CON(\con$3484 ), + .SN(\sn$3486 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_0 ( + .A(\s$2679 ), + .B(\c$2985 ), + .CI(\c$2989 ), + .CON(\con$3488 ), + .SN(\sn$3490 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_1 ( + .A(\c$2993 ), + .B(\c$2997 ), + .CI(\s$3003 ), + .CON(\con$3492 ), + .SN(\sn$3494 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_34_2 ( + .A(\s$3007 ), + .B(\s$3011 ), + .CI(\s$3015 ), + .CON(\con$3496 ), + .SN(\sn$3498 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_0 ( + .A(\s$2695 ), + .B(\c$3001 ), + .CI(\c$3005 ), + .CON(\con$3500 ), + .SN(\sn$3502 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_1 ( + .A(\c$3009 ), + .B(\c$3013 ), + .CI(\s$3019 ), + .CON(\con$3504 ), + .SN(\sn$3506 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_35_2 ( + .A(\s$3023 ), + .B(\s$3027 ), + .CI(\s$3031 ), + .CON(\con$3508 ), + .SN(\sn$3510 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_0 ( + .A(\s$2711 ), + .B(\c$3017 ), + .CI(\c$3021 ), + .CON(\con$3512 ), + .SN(\sn$3514 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_1 ( + .A(\c$3025 ), + .B(\c$3029 ), + .CI(\s$3035 ), + .CON(\con$3516 ), + .SN(\sn$3518 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_36_2 ( + .A(\s$3039 ), + .B(\s$3043 ), + .CI(\s$3047 ), + .CON(\con$3520 ), + .SN(\sn$3522 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_0 ( + .A(\s$2723 ), + .B(\c$3033 ), + .CI(\c$3037 ), + .CON(\con$3524 ), + .SN(\sn$3526 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_1 ( + .A(\c$3041 ), + .B(\c$3045 ), + .CI(\s$3051 ), + .CON(\con$3528 ), + .SN(\sn$3530 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_37_2 ( + .A(\s$3055 ), + .B(\s$3059 ), + .CI(\s$3063 ), + .CON(\con$3532 ), + .SN(\sn$3534 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_0 ( + .A(\s$2735 ), + .B(\c$3049 ), + .CI(\c$3053 ), + .CON(\con$3536 ), + .SN(\sn$3538 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_1 ( + .A(\c$3057 ), + .B(\c$3061 ), + .CI(\s$3067 ), + .CON(\con$3540 ), + .SN(\sn$3542 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_38_2 ( + .A(\s$3071 ), + .B(\s$3075 ), + .CI(\s$3079 ), + .CON(\con$3544 ), + .SN(\sn$3546 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_0 ( + .A(\s$2743 ), + .B(\c$3065 ), + .CI(\c$3069 ), + .CON(\con$3548 ), + .SN(\sn$3550 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_1 ( + .A(\c$3073 ), + .B(\c$3077 ), + .CI(\s$3083 ), + .CON(\con$3552 ), + .SN(\sn$3554 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_39_2 ( + .A(\s$3087 ), + .B(\s$3091 ), + .CI(\s$3095 ), + .CON(\con$3556 ), + .SN(\sn$3558 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_0 ( + .A(\s$2751 ), + .B(\c$3081 ), + .CI(\c$3085 ), + .CON(\con$3560 ), + .SN(\sn$3562 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_1 ( + .A(\c$3089 ), + .B(\c$3093 ), + .CI(\s$3099 ), + .CON(\con$3564 ), + .SN(\sn$3566 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_40_2 ( + .A(\s$3103 ), + .B(\s$3107 ), + .CI(\s$3111 ), + .CON(\con$3568 ), + .SN(\sn$3570 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_0 ( + .A(\s$2755 ), + .B(\c$3097 ), + .CI(\c$3101 ), + .CON(\con$3572 ), + .SN(\sn$3574 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_1 ( + .A(\c$3105 ), + .B(\c$3109 ), + .CI(\s$3115 ), + .CON(\con$3576 ), + .SN(\sn$3578 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_41_2 ( + .A(\s$3119 ), + .B(\s$3123 ), + .CI(\s$3127 ), + .CON(\con$3580 ), + .SN(\sn$3582 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_0 ( + .A(\s$2759 ), + .B(\c$3113 ), + .CI(\c$3117 ), + .CON(\con$3584 ), + .SN(\sn$3586 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_1 ( + .A(\c$3121 ), + .B(\c$3125 ), + .CI(\s$3131 ), + .CON(\con$3588 ), + .SN(\sn$3590 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_42_2 ( + .A(\s$3135 ), + .B(\s$3139 ), + .CI(\s$3143 ), + .CON(\con$3592 ), + .SN(\sn$3594 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_0 ( + .A(\c$2757 ), + .B(\c$3129 ), + .CI(\c$3133 ), + .CON(\con$3596 ), + .SN(\sn$3598 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_1 ( + .A(\c$3137 ), + .B(\c$3141 ), + .CI(\s$3147 ), + .CON(\con$3600 ), + .SN(\sn$3602 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_43_2 ( + .A(\s$3151 ), + .B(\s$3155 ), + .CI(\s$3159 ), + .CON(\con$3604 ), + .SN(\sn$3606 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_0 ( + .A(pp_row44_11), + .B(\c$3145 ), + .CI(\c$3149 ), + .CON(\con$3608 ), + .SN(\sn$3610 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_1 ( + .A(\c$3153 ), + .B(\c$3157 ), + .CI(\s$3163 ), + .CON(\con$3612 ), + .SN(\sn$3614 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_44_2 ( + .A(\s$3167 ), + .B(\s$3171 ), + .CI(\s$3175 ), + .CON(\con$3616 ), + .SN(\sn$3618 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_0 ( + .A(pp_row45_9), + .B(pp_row45_10), + .CI(\c$3161 ), + .CON(\con$3620 ), + .SN(\sn$3622 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_1 ( + .A(\c$3165 ), + .B(\c$3169 ), + .CI(\c$3173 ), + .CON(\con$3624 ), + .SN(\sn$3626 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_45_2 ( + .A(\s$3179 ), + .B(\s$3183 ), + .CI(\s$3187 ), + .CON(\con$3628 ), + .SN(\sn$3630 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_0 ( + .A(pp_row46_8), + .B(pp_row46_9), + .CI(pp_row46_10), + .CON(\con$3632 ), + .SN(\sn$3634 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_1 ( + .A(\c$3177 ), + .B(\c$3181 ), + .CI(\c$3185 ), + .CON(\con$3636 ), + .SN(\sn$3638 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_46_2 ( + .A(\s$3191 ), + .B(\s$3195 ), + .CI(\s$3199 ), + .CON(\con$3640 ), + .SN(\sn$3642 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_0 ( + .A(pp_row47_6), + .B(pp_row47_7), + .CI(pp_row47_8), + .CON(\con$3644 ), + .SN(\sn$3646 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_1 ( + .A(pp_row47_9), + .B(\c$3189 ), + .CI(\c$3193 ), + .CON(\con$3648 ), + .SN(\sn$3650 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_47_2 ( + .A(\c$3197 ), + .B(\s$3203 ), + .CI(\s$3207 ), + .CON(\con$3652 ), + .SN(\sn$3654 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_0 ( + .A(pp_row48_5), + .B(pp_row48_6), + .CI(pp_row48_7), + .CON(\con$3656 ), + .SN(\sn$3658 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_1 ( + .A(pp_row48_8), + .B(pp_row48_9), + .CI(\c$3201 ), + .CON(\con$3660 ), + .SN(\sn$3662 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_48_2 ( + .A(\c$3205 ), + .B(\s$3211 ), + .CI(\s$3215 ), + .CON(\con$3664 ), + .SN(\sn$3666 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_0 ( + .A(pp_row49_3), + .B(pp_row49_4), + .CI(pp_row49_5), + .CON(\con$3668 ), + .SN(\sn$3670 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_1 ( + .A(pp_row49_6), + .B(pp_row49_7), + .CI(pp_row49_8), + .CON(\con$3672 ), + .SN(\sn$3674 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_49_2 ( + .A(\c$3209 ), + .B(\c$3213 ), + .CI(\s$3219 ), + .CON(\con$3676 ), + .SN(\sn$3678 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_0 ( + .A(pp_row50_2), + .B(pp_row50_3), + .CI(pp_row50_4), + .CON(\con$3680 ), + .SN(\sn$3682 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_1 ( + .A(pp_row50_5), + .B(pp_row50_6), + .CI(pp_row50_7), + .CON(\con$3684 ), + .SN(\sn$3686 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_50_2 ( + .A(pp_row50_8), + .B(\c$3217 ), + .CI(\s$3223 ), + .CON(\con$3688 ), + .SN(\sn$3690 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_0 ( + .A(pp_row51_0), + .B(pp_row51_1), + .CI(pp_row51_2), + .CON(\con$3692 ), + .SN(\sn$3694 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_1 ( + .A(pp_row51_3), + .B(pp_row51_4), + .CI(pp_row51_5), + .CON(\con$3696 ), + .SN(\sn$3698 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_51_2 ( + .A(pp_row51_6), + .B(pp_row51_7), + .CI(\c$3221 ), + .CON(\con$3700 ), + .SN(\sn$3702 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_52_0 ( + .A(1'h1), + .B(pp_row52_1), + .CI(pp_row52_2), + .CON(\con$3704 ), + .SN(\sn$3706 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_52_1 ( + .A(pp_row52_3), + .B(pp_row52_4), + .CI(pp_row52_5), + .CON(\con$3708 ), + .SN(\sn$3710 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_53_0 ( + .A(pp_row53_0), + .B(pp_row53_1), + .CI(pp_row53_2), + .CON(\con$3716 ), + .SN(\sn$3718 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_53_1 ( + .A(pp_row53_3), + .B(pp_row53_4), + .CI(pp_row53_5), + .CON(\con$3720 ), + .SN(\sn$3722 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_54_0 ( + .A(1'h1), + .B(pp_row54_1), + .CI(pp_row54_2), + .CON(\con$3724 ), + .SN(\sn$3726 ) + ); + FAx1_ASAP7_75t_R dadda_fa_2_55_0 ( + .A(pp_row55_0), + .B(pp_row55_1), + .CI(pp_row55_2), + .CON(\con$3732 ), + .SN(\sn$3734 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_10_0 ( + .A(pp_row10_2), + .B(pp_row10_3), + .CI(pp_row10_4), + .CON(\con$3764 ), + .SN(\sn$3766 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_10_1 ( + .A(pp_row10_5), + .B(pp_row10_6), + .CI(\s$3227 ), + .CON(\con$3768 ), + .SN(\sn$3770 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_11_0 ( + .A(pp_row11_2), + .B(pp_row11_3), + .CI(pp_row11_4), + .CON(\con$3772 ), + .SN(\sn$3774 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_11_1 ( + .A(pp_row11_5), + .B(\c$3225 ), + .CI(\s$3231 ), + .CON(\con$3776 ), + .SN(\sn$3778 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_12_0 ( + .A(pp_row12_5), + .B(pp_row12_6), + .CI(pp_row12_7), + .CON(\con$3780 ), + .SN(\sn$3782 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_12_1 ( + .A(\c$3229 ), + .B(\s$3235 ), + .CI(\s$3239 ), + .CON(\con$3784 ), + .SN(\sn$3786 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_13_0 ( + .A(pp_row13_5), + .B(pp_row13_6), + .CI(\c$3233 ), + .CON(\con$3788 ), + .SN(\sn$3790 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_13_1 ( + .A(\c$3237 ), + .B(\s$3243 ), + .CI(\s$3247 ), + .CON(\con$3792 ), + .SN(\sn$3794 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_14_0 ( + .A(pp_row14_8), + .B(\c$3241 ), + .CI(\c$3245 ), + .CON(\con$3796 ), + .SN(\sn$3798 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_14_1 ( + .A(\s$3251 ), + .B(\s$3255 ), + .CI(\s$3259 ), + .CON(\con$3800 ), + .SN(\sn$3802 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_15_0 ( + .A(\c$3249 ), + .B(\c$3253 ), + .CI(\c$3257 ), + .CON(\con$3804 ), + .SN(\sn$3806 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_15_1 ( + .A(\s$3263 ), + .B(\s$3267 ), + .CI(\s$3271 ), + .CON(\con$3808 ), + .SN(\sn$3810 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_16_0 ( + .A(\c$3261 ), + .B(\c$3265 ), + .CI(\c$3269 ), + .CON(\con$3812 ), + .SN(\sn$3814 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_16_1 ( + .A(\s$3275 ), + .B(\s$3279 ), + .CI(\s$3283 ), + .CON(\con$3816 ), + .SN(\sn$3818 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_17_0 ( + .A(\c$3273 ), + .B(\c$3277 ), + .CI(\c$3281 ), + .CON(\con$3820 ), + .SN(\sn$3822 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_17_1 ( + .A(\s$3287 ), + .B(\s$3291 ), + .CI(\s$3295 ), + .CON(\con$3824 ), + .SN(\sn$3826 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_18_0 ( + .A(\c$3285 ), + .B(\c$3289 ), + .CI(\c$3293 ), + .CON(\con$3828 ), + .SN(\sn$3830 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_18_1 ( + .A(\s$3299 ), + .B(\s$3303 ), + .CI(\s$3307 ), + .CON(\con$3832 ), + .SN(\sn$3834 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_19_0 ( + .A(\c$3297 ), + .B(\c$3301 ), + .CI(\c$3305 ), + .CON(\con$3836 ), + .SN(\sn$3838 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_19_1 ( + .A(\s$3311 ), + .B(\s$3315 ), + .CI(\s$3319 ), + .CON(\con$3840 ), + .SN(\sn$3842 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_20_0 ( + .A(\c$3309 ), + .B(\c$3313 ), + .CI(\c$3317 ), + .CON(\con$3844 ), + .SN(\sn$3846 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_20_1 ( + .A(\s$3323 ), + .B(\s$3327 ), + .CI(\s$3331 ), + .CON(\con$3848 ), + .SN(\sn$3850 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_21_0 ( + .A(\c$3321 ), + .B(\c$3325 ), + .CI(\c$3329 ), + .CON(\con$3852 ), + .SN(\sn$3854 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_21_1 ( + .A(\s$3335 ), + .B(\s$3339 ), + .CI(\s$3343 ), + .CON(\con$3856 ), + .SN(\sn$3858 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_22_0 ( + .A(\c$3333 ), + .B(\c$3337 ), + .CI(\c$3341 ), + .CON(\con$3860 ), + .SN(\sn$3862 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_22_1 ( + .A(\s$3347 ), + .B(\s$3351 ), + .CI(\s$3355 ), + .CON(\con$3864 ), + .SN(\sn$3866 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_23_0 ( + .A(\c$3345 ), + .B(\c$3349 ), + .CI(\c$3353 ), + .CON(\con$3868 ), + .SN(\sn$3870 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_23_1 ( + .A(\s$3359 ), + .B(\s$3363 ), + .CI(\s$3367 ), + .CON(\con$3872 ), + .SN(\sn$3874 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_24_0 ( + .A(\c$3357 ), + .B(\c$3361 ), + .CI(\c$3365 ), + .CON(\con$3876 ), + .SN(\sn$3878 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_24_1 ( + .A(\s$3371 ), + .B(\s$3375 ), + .CI(\s$3379 ), + .CON(\con$3880 ), + .SN(\sn$3882 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_25_0 ( + .A(\c$3369 ), + .B(\c$3373 ), + .CI(\c$3377 ), + .CON(\con$3884 ), + .SN(\sn$3886 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_25_1 ( + .A(\s$3383 ), + .B(\s$3387 ), + .CI(\s$3391 ), + .CON(\con$3888 ), + .SN(\sn$3890 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_26_0 ( + .A(\c$3381 ), + .B(\c$3385 ), + .CI(\c$3389 ), + .CON(\con$3892 ), + .SN(\sn$3894 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_26_1 ( + .A(\s$3395 ), + .B(\s$3399 ), + .CI(\s$3403 ), + .CON(\con$3896 ), + .SN(\sn$3898 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_27_0 ( + .A(\c$3393 ), + .B(\c$3397 ), + .CI(\c$3401 ), + .CON(\con$3900 ), + .SN(\sn$3902 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_27_1 ( + .A(\s$3407 ), + .B(\s$3411 ), + .CI(\s$3415 ), + .CON(\con$3904 ), + .SN(\sn$3906 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_28_0 ( + .A(\c$3405 ), + .B(\c$3409 ), + .CI(\c$3413 ), + .CON(\con$3908 ), + .SN(\sn$3910 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_28_1 ( + .A(\s$3419 ), + .B(\s$3423 ), + .CI(\s$3427 ), + .CON(\con$3912 ), + .SN(\sn$3914 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_29_0 ( + .A(\c$3417 ), + .B(\c$3421 ), + .CI(\c$3425 ), + .CON(\con$3916 ), + .SN(\sn$3918 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_29_1 ( + .A(\s$3431 ), + .B(\s$3435 ), + .CI(\s$3439 ), + .CON(\con$3920 ), + .SN(\sn$3922 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_30_0 ( + .A(\c$3429 ), + .B(\c$3433 ), + .CI(\c$3437 ), + .CON(\con$3924 ), + .SN(\sn$3926 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_30_1 ( + .A(\s$3443 ), + .B(\s$3447 ), + .CI(\s$3451 ), + .CON(\con$3928 ), + .SN(\sn$3930 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_31_0 ( + .A(\c$3441 ), + .B(\c$3445 ), + .CI(\c$3449 ), + .CON(\con$3932 ), + .SN(\sn$3934 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_31_1 ( + .A(\s$3455 ), + .B(\s$3459 ), + .CI(\s$3463 ), + .CON(\con$3936 ), + .SN(\sn$3938 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_32_0 ( + .A(\c$3453 ), + .B(\c$3457 ), + .CI(\c$3461 ), + .CON(\con$3940 ), + .SN(\sn$3942 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_32_1 ( + .A(\s$3467 ), + .B(\s$3471 ), + .CI(\s$3475 ), + .CON(\con$3944 ), + .SN(\sn$3946 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_33_0 ( + .A(\c$3465 ), + .B(\c$3469 ), + .CI(\c$3473 ), + .CON(\con$3948 ), + .SN(\sn$3950 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_33_1 ( + .A(\s$3479 ), + .B(\s$3483 ), + .CI(\s$3487 ), + .CON(\con$3952 ), + .SN(\sn$3954 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_34_0 ( + .A(\c$3477 ), + .B(\c$3481 ), + .CI(\c$3485 ), + .CON(\con$3956 ), + .SN(\sn$3958 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_34_1 ( + .A(\s$3491 ), + .B(\s$3495 ), + .CI(\s$3499 ), + .CON(\con$3960 ), + .SN(\sn$3962 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_35_0 ( + .A(\c$3489 ), + .B(\c$3493 ), + .CI(\c$3497 ), + .CON(\con$3964 ), + .SN(\sn$3966 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_35_1 ( + .A(\s$3503 ), + .B(\s$3507 ), + .CI(\s$3511 ), + .CON(\con$3968 ), + .SN(\sn$3970 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_36_0 ( + .A(\c$3501 ), + .B(\c$3505 ), + .CI(\c$3509 ), + .CON(\con$3972 ), + .SN(\sn$3974 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_36_1 ( + .A(\s$3515 ), + .B(\s$3519 ), + .CI(\s$3523 ), + .CON(\con$3976 ), + .SN(\sn$3978 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_37_0 ( + .A(\c$3513 ), + .B(\c$3517 ), + .CI(\c$3521 ), + .CON(\con$3980 ), + .SN(\sn$3982 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_37_1 ( + .A(\s$3527 ), + .B(\s$3531 ), + .CI(\s$3535 ), + .CON(\con$3984 ), + .SN(\sn$3986 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_38_0 ( + .A(\c$3525 ), + .B(\c$3529 ), + .CI(\c$3533 ), + .CON(\con$3988 ), + .SN(\sn$3990 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_38_1 ( + .A(\s$3539 ), + .B(\s$3543 ), + .CI(\s$3547 ), + .CON(\con$3992 ), + .SN(\sn$3994 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_39_0 ( + .A(\c$3537 ), + .B(\c$3541 ), + .CI(\c$3545 ), + .CON(\con$3996 ), + .SN(\sn$3998 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_39_1 ( + .A(\s$3551 ), + .B(\s$3555 ), + .CI(\s$3559 ), + .CON(\con$4000 ), + .SN(\sn$4002 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_40_0 ( + .A(\c$3549 ), + .B(\c$3553 ), + .CI(\c$3557 ), + .CON(\con$4004 ), + .SN(\sn$4006 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_40_1 ( + .A(\s$3563 ), + .B(\s$3567 ), + .CI(\s$3571 ), + .CON(\con$4008 ), + .SN(\sn$4010 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_41_0 ( + .A(\c$3561 ), + .B(\c$3565 ), + .CI(\c$3569 ), + .CON(\con$4012 ), + .SN(\sn$4014 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_41_1 ( + .A(\s$3575 ), + .B(\s$3579 ), + .CI(\s$3583 ), + .CON(\con$4016 ), + .SN(\sn$4018 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_42_0 ( + .A(\c$3573 ), + .B(\c$3577 ), + .CI(\c$3581 ), + .CON(\con$4020 ), + .SN(\sn$4022 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_42_1 ( + .A(\s$3587 ), + .B(\s$3591 ), + .CI(\s$3595 ), + .CON(\con$4024 ), + .SN(\sn$4026 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_43_0 ( + .A(\c$3585 ), + .B(\c$3589 ), + .CI(\c$3593 ), + .CON(\con$4028 ), + .SN(\sn$4030 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_43_1 ( + .A(\s$3599 ), + .B(\s$3603 ), + .CI(\s$3607 ), + .CON(\con$4032 ), + .SN(\sn$4034 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_44_0 ( + .A(\c$3597 ), + .B(\c$3601 ), + .CI(\c$3605 ), + .CON(\con$4036 ), + .SN(\sn$4038 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_44_1 ( + .A(\s$3611 ), + .B(\s$3615 ), + .CI(\s$3619 ), + .CON(\con$4040 ), + .SN(\sn$4042 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_45_0 ( + .A(\c$3609 ), + .B(\c$3613 ), + .CI(\c$3617 ), + .CON(\con$4044 ), + .SN(\sn$4046 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_45_1 ( + .A(\s$3623 ), + .B(\s$3627 ), + .CI(\s$3631 ), + .CON(\con$4048 ), + .SN(\sn$4050 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_46_0 ( + .A(\c$3621 ), + .B(\c$3625 ), + .CI(\c$3629 ), + .CON(\con$4052 ), + .SN(\sn$4054 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_46_1 ( + .A(\s$3635 ), + .B(\s$3639 ), + .CI(\s$3643 ), + .CON(\con$4056 ), + .SN(\sn$4058 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_47_0 ( + .A(\c$3633 ), + .B(\c$3637 ), + .CI(\c$3641 ), + .CON(\con$4060 ), + .SN(\sn$4062 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_47_1 ( + .A(\s$3647 ), + .B(\s$3651 ), + .CI(\s$3655 ), + .CON(\con$4064 ), + .SN(\sn$4066 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_48_0 ( + .A(\c$3645 ), + .B(\c$3649 ), + .CI(\c$3653 ), + .CON(\con$4068 ), + .SN(\sn$4070 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_48_1 ( + .A(\s$3659 ), + .B(\s$3663 ), + .CI(\s$3667 ), + .CON(\con$4072 ), + .SN(\sn$4074 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_49_0 ( + .A(\c$3657 ), + .B(\c$3661 ), + .CI(\c$3665 ), + .CON(\con$4076 ), + .SN(\sn$4078 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_49_1 ( + .A(\s$3671 ), + .B(\s$3675 ), + .CI(\s$3679 ), + .CON(\con$4080 ), + .SN(\sn$4082 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_50_0 ( + .A(\c$3669 ), + .B(\c$3673 ), + .CI(\c$3677 ), + .CON(\con$4084 ), + .SN(\sn$4086 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_50_1 ( + .A(\s$3683 ), + .B(\s$3687 ), + .CI(\s$3691 ), + .CON(\con$4088 ), + .SN(\sn$4090 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_51_0 ( + .A(\c$3681 ), + .B(\c$3685 ), + .CI(\c$3689 ), + .CON(\con$4092 ), + .SN(\sn$4094 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_51_1 ( + .A(\s$3695 ), + .B(\s$3699 ), + .CI(\s$3703 ), + .CON(\con$4096 ), + .SN(\sn$4098 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_52_0 ( + .A(\c$3693 ), + .B(\c$3697 ), + .CI(\c$3701 ), + .CON(\con$4100 ), + .SN(\sn$4102 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_52_1 ( + .A(\s$3707 ), + .B(\s$3711 ), + .CI(\s$3715 ), + .CON(\con$4104 ), + .SN(\sn$4106 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_53_0 ( + .A(pp_row53_6), + .B(\c$3705 ), + .CI(\c$3709 ), + .CON(\con$4108 ), + .SN(\sn$4110 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_53_1 ( + .A(\c$3713 ), + .B(\s$3719 ), + .CI(\s$3723 ), + .CON(\con$4112 ), + .SN(\sn$4114 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_54_0 ( + .A(pp_row54_5), + .B(pp_row54_6), + .CI(\c$3717 ), + .CON(\con$4116 ), + .SN(\sn$4118 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_54_1 ( + .A(\c$3721 ), + .B(\s$3727 ), + .CI(\s$3731 ), + .CON(\con$4120 ), + .SN(\sn$4122 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_55_0 ( + .A(pp_row55_3), + .B(pp_row55_4), + .CI(pp_row55_5), + .CON(\con$4124 ), + .SN(\sn$4126 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_55_1 ( + .A(\c$3725 ), + .B(\c$3729 ), + .CI(\s$3735 ), + .CON(\con$4128 ), + .SN(\sn$4130 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_56_0 ( + .A(pp_row56_2), + .B(pp_row56_3), + .CI(pp_row56_4), + .CON(\con$4132 ), + .SN(\sn$4134 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_56_1 ( + .A(pp_row56_5), + .B(\c$3733 ), + .CI(\s$3739 ), + .CON(\con$4136 ), + .SN(\sn$4138 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_57_0 ( + .A(pp_row57_0), + .B(pp_row57_1), + .CI(pp_row57_2), + .CON(\con$4140 ), + .SN(\sn$4142 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_57_1 ( + .A(pp_row57_3), + .B(pp_row57_4), + .CI(\c$3737 ), + .CON(\con$4144 ), + .SN(\sn$4146 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_58_0 ( + .A(1'h1), + .B(pp_row58_1), + .CI(pp_row58_2), + .CON(\con$4148 ), + .SN(\sn$4150 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_59_0 ( + .A(pp_row59_0), + .B(pp_row59_1), + .CI(pp_row59_2), + .CON(\con$4156 ), + .SN(\sn$4158 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_8_0 ( + .A(pp_row8_0), + .B(pp_row8_1), + .CI(pp_row8_2), + .CON(\con$3748 ), + .SN(\sn$3750 ) + ); + FAx1_ASAP7_75t_R dadda_fa_3_9_0 ( + .A(pp_row9_0), + .B(pp_row9_1), + .CI(pp_row9_2), + .CON(\con$3756 ), + .SN(\sn$3758 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_10_0 ( + .A(\c$3757 ), + .B(\c$3761 ), + .CI(\s$3767 ), + .CON(\con$4188 ), + .SN(\sn$4190 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_11_0 ( + .A(\c$3765 ), + .B(\c$3769 ), + .CI(\s$3775 ), + .CON(\con$4192 ), + .SN(\sn$4194 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_12_0 ( + .A(\c$3773 ), + .B(\c$3777 ), + .CI(\s$3783 ), + .CON(\con$4196 ), + .SN(\sn$4198 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_13_0 ( + .A(\c$3781 ), + .B(\c$3785 ), + .CI(\s$3791 ), + .CON(\con$4200 ), + .SN(\sn$4202 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_14_0 ( + .A(\c$3789 ), + .B(\c$3793 ), + .CI(\s$3799 ), + .CON(\con$4204 ), + .SN(\sn$4206 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_15_0 ( + .A(\c$3797 ), + .B(\c$3801 ), + .CI(\s$3807 ), + .CON(\con$4208 ), + .SN(\sn$4210 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_16_0 ( + .A(\c$3805 ), + .B(\c$3809 ), + .CI(\s$3815 ), + .CON(\con$4212 ), + .SN(\sn$4214 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_17_0 ( + .A(\c$3813 ), + .B(\c$3817 ), + .CI(\s$3823 ), + .CON(\con$4216 ), + .SN(\sn$4218 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_18_0 ( + .A(\c$3821 ), + .B(\c$3825 ), + .CI(\s$3831 ), + .CON(\con$4220 ), + .SN(\sn$4222 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_19_0 ( + .A(\c$3829 ), + .B(\c$3833 ), + .CI(\s$3839 ), + .CON(\con$4224 ), + .SN(\sn$4226 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_20_0 ( + .A(\c$3837 ), + .B(\c$3841 ), + .CI(\s$3847 ), + .CON(\con$4228 ), + .SN(\sn$4230 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_21_0 ( + .A(\c$3845 ), + .B(\c$3849 ), + .CI(\s$3855 ), + .CON(\con$4232 ), + .SN(\sn$4234 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_22_0 ( + .A(\c$3853 ), + .B(\c$3857 ), + .CI(\s$3863 ), + .CON(\con$4236 ), + .SN(\sn$4238 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_23_0 ( + .A(\c$3861 ), + .B(\c$3865 ), + .CI(\s$3871 ), + .CON(\con$4240 ), + .SN(\sn$4242 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_24_0 ( + .A(\c$3869 ), + .B(\c$3873 ), + .CI(\s$3879 ), + .CON(\con$4244 ), + .SN(\sn$4246 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_25_0 ( + .A(\c$3877 ), + .B(\c$3881 ), + .CI(\s$3887 ), + .CON(\con$4248 ), + .SN(\sn$4250 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_26_0 ( + .A(\c$3885 ), + .B(\c$3889 ), + .CI(\s$3895 ), + .CON(\con$4252 ), + .SN(\sn$4254 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_27_0 ( + .A(\c$3893 ), + .B(\c$3897 ), + .CI(\s$3903 ), + .CON(\con$4256 ), + .SN(\sn$4258 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_28_0 ( + .A(\c$3901 ), + .B(\c$3905 ), + .CI(\s$3911 ), + .CON(\con$4260 ), + .SN(\sn$4262 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_29_0 ( + .A(\c$3909 ), + .B(\c$3913 ), + .CI(\s$3919 ), + .CON(\con$4264 ), + .SN(\sn$4266 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_30_0 ( + .A(\c$3917 ), + .B(\c$3921 ), + .CI(\s$3927 ), + .CON(\con$4268 ), + .SN(\sn$4270 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_31_0 ( + .A(\c$3925 ), + .B(\c$3929 ), + .CI(\s$3935 ), + .CON(\con$4272 ), + .SN(\sn$4274 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_32_0 ( + .A(\c$3933 ), + .B(\c$3937 ), + .CI(\s$3943 ), + .CON(\con$4276 ), + .SN(\sn$4278 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_33_0 ( + .A(\c$3941 ), + .B(\c$3945 ), + .CI(\s$3951 ), + .CON(\con$4280 ), + .SN(\sn$4282 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_34_0 ( + .A(\c$3949 ), + .B(\c$3953 ), + .CI(\s$3959 ), + .CON(\con$4284 ), + .SN(\sn$4286 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_35_0 ( + .A(\c$3957 ), + .B(\c$3961 ), + .CI(\s$3967 ), + .CON(\con$4288 ), + .SN(\sn$4290 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_36_0 ( + .A(\c$3965 ), + .B(\c$3969 ), + .CI(\s$3975 ), + .CON(\con$4292 ), + .SN(\sn$4294 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_37_0 ( + .A(\c$3973 ), + .B(\c$3977 ), + .CI(\s$3983 ), + .CON(\con$4296 ), + .SN(\sn$4298 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_38_0 ( + .A(\c$3981 ), + .B(\c$3985 ), + .CI(\s$3991 ), + .CON(\con$4300 ), + .SN(\sn$4302 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_39_0 ( + .A(\c$3989 ), + .B(\c$3993 ), + .CI(\s$3999 ), + .CON(\con$4304 ), + .SN(\sn$4306 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_40_0 ( + .A(\c$3997 ), + .B(\c$4001 ), + .CI(\s$4007 ), + .CON(\con$4308 ), + .SN(\sn$4310 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_41_0 ( + .A(\c$4005 ), + .B(\c$4009 ), + .CI(\s$4015 ), + .CON(\con$4312 ), + .SN(\sn$4314 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_42_0 ( + .A(\c$4013 ), + .B(\c$4017 ), + .CI(\s$4023 ), + .CON(\con$4316 ), + .SN(\sn$4318 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_43_0 ( + .A(\c$4021 ), + .B(\c$4025 ), + .CI(\s$4031 ), + .CON(\con$4320 ), + .SN(\sn$4322 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_44_0 ( + .A(\c$4029 ), + .B(\c$4033 ), + .CI(\s$4039 ), + .CON(\con$4324 ), + .SN(\sn$4326 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_45_0 ( + .A(\c$4037 ), + .B(\c$4041 ), + .CI(\s$4047 ), + .CON(\con$4328 ), + .SN(\sn$4330 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_46_0 ( + .A(\c$4045 ), + .B(\c$4049 ), + .CI(\s$4055 ), + .CON(\con$4332 ), + .SN(\sn$4334 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_47_0 ( + .A(\c$4053 ), + .B(\c$4057 ), + .CI(\s$4063 ), + .CON(\con$4336 ), + .SN(\sn$4338 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_48_0 ( + .A(\c$4061 ), + .B(\c$4065 ), + .CI(\s$4071 ), + .CON(\con$4340 ), + .SN(\sn$4342 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_49_0 ( + .A(\c$4069 ), + .B(\c$4073 ), + .CI(\s$4079 ), + .CON(\con$4344 ), + .SN(\sn$4346 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_50_0 ( + .A(\c$4077 ), + .B(\c$4081 ), + .CI(\s$4087 ), + .CON(\con$4348 ), + .SN(\sn$4350 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_51_0 ( + .A(\c$4085 ), + .B(\c$4089 ), + .CI(\s$4095 ), + .CON(\con$4352 ), + .SN(\sn$4354 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_52_0 ( + .A(\c$4093 ), + .B(\c$4097 ), + .CI(\s$4103 ), + .CON(\con$4356 ), + .SN(\sn$4358 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_53_0 ( + .A(\c$4101 ), + .B(\c$4105 ), + .CI(\s$4111 ), + .CON(\con$4360 ), + .SN(\sn$4362 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_54_0 ( + .A(\c$4109 ), + .B(\c$4113 ), + .CI(\s$4119 ), + .CON(\con$4364 ), + .SN(\sn$4366 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_55_0 ( + .A(\c$4117 ), + .B(\c$4121 ), + .CI(\s$4127 ), + .CON(\con$4368 ), + .SN(\sn$4370 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_56_0 ( + .A(\c$4125 ), + .B(\c$4129 ), + .CI(\s$4135 ), + .CON(\con$4372 ), + .SN(\sn$4374 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_57_0 ( + .A(\c$4133 ), + .B(\c$4137 ), + .CI(\s$4143 ), + .CON(\con$4376 ), + .SN(\sn$4378 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_58_0 ( + .A(\c$4141 ), + .B(\c$4145 ), + .CI(\s$4151 ), + .CON(\con$4380 ), + .SN(\sn$4382 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_59_0 ( + .A(pp_row59_3), + .B(\c$4149 ), + .CI(\c$4153 ), + .CON(\con$4384 ), + .SN(\sn$4386 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_60_0 ( + .A(pp_row60_2), + .B(pp_row60_3), + .CI(\c$4157 ), + .CON(\con$4388 ), + .SN(\sn$4390 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_61_0 ( + .A(pp_row61_0), + .B(pp_row61_1), + .CI(pp_row61_2), + .CON(\con$4392 ), + .SN(\sn$4394 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_6_0 ( + .A(pp_row6_2), + .B(pp_row6_3), + .CI(pp_row6_4), + .CON(\con$4172 ), + .SN(\sn$4174 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_7_0 ( + .A(pp_row7_2), + .B(pp_row7_3), + .CI(\c$3741 ), + .CON(\con$4176 ), + .SN(\sn$4178 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_8_0 ( + .A(pp_row8_5), + .B(\c$3745 ), + .CI(\s$3751 ), + .CON(\con$4180 ), + .SN(\sn$4182 ) + ); + FAx1_ASAP7_75t_R dadda_fa_4_9_0 ( + .A(\c$3749 ), + .B(\c$3753 ), + .CI(\s$3759 ), + .CON(\con$4184 ), + .SN(\sn$4186 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_10_0 ( + .A(\s$3771 ), + .B(\c$4185 ), + .CI(\s$4191 ), + .CON(\con$4416 ), + .SN(\sn$4417 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_11_0 ( + .A(\s$3779 ), + .B(\c$4189 ), + .CI(\s$4195 ), + .CON(\con$4418 ), + .SN(\sn$4419 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_12_0 ( + .A(\s$3787 ), + .B(\c$4193 ), + .CI(\s$4199 ), + .CON(\con$4420 ), + .SN(\sn$4421 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_13_0 ( + .A(\s$3795 ), + .B(\c$4197 ), + .CI(\s$4203 ), + .CON(\con$4422 ), + .SN(\sn$4423 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_14_0 ( + .A(\s$3803 ), + .B(\c$4201 ), + .CI(\s$4207 ), + .CON(\con$4424 ), + .SN(\sn$4425 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_15_0 ( + .A(\s$3811 ), + .B(\c$4205 ), + .CI(\s$4211 ), + .CON(\con$4426 ), + .SN(\sn$4427 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_16_0 ( + .A(\s$3819 ), + .B(\c$4209 ), + .CI(\s$4215 ), + .CON(\con$4428 ), + .SN(\sn$4429 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_17_0 ( + .A(\s$3827 ), + .B(\c$4213 ), + .CI(\s$4219 ), + .CON(\con$4430 ), + .SN(\sn$4431 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_18_0 ( + .A(\s$3835 ), + .B(\c$4217 ), + .CI(\s$4223 ), + .CON(\con$4432 ), + .SN(\sn$4433 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_19_0 ( + .A(\s$3843 ), + .B(\c$4221 ), + .CI(\s$4227 ), + .CON(\con$4434 ), + .SN(\sn$4435 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_20_0 ( + .A(\s$3851 ), + .B(\c$4225 ), + .CI(\s$4231 ), + .CON(\con$4436 ), + .SN(\sn$4437 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_21_0 ( + .A(\s$3859 ), + .B(\c$4229 ), + .CI(\s$4235 ), + .CON(\con$4438 ), + .SN(\sn$4439 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_22_0 ( + .A(\s$3867 ), + .B(\c$4233 ), + .CI(\s$4239 ), + .CON(\con$4440 ), + .SN(\sn$4441 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_23_0 ( + .A(\s$3875 ), + .B(\c$4237 ), + .CI(\s$4243 ), + .CON(\con$4442 ), + .SN(\sn$4443 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_24_0 ( + .A(\s$3883 ), + .B(\c$4241 ), + .CI(\s$4247 ), + .CON(\con$4444 ), + .SN(\sn$4445 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_25_0 ( + .A(\s$3891 ), + .B(\c$4245 ), + .CI(\s$4251 ), + .CON(\con$4446 ), + .SN(\sn$4447 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_26_0 ( + .A(\s$3899 ), + .B(\c$4249 ), + .CI(\s$4255 ), + .CON(\con$4448 ), + .SN(\sn$4449 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_27_0 ( + .A(\s$3907 ), + .B(\c$4253 ), + .CI(\s$4259 ), + .CON(\con$4450 ), + .SN(\sn$4451 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_28_0 ( + .A(\s$3915 ), + .B(\c$4257 ), + .CI(\s$4263 ), + .CON(\con$4452 ), + .SN(\sn$4453 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_29_0 ( + .A(\s$3923 ), + .B(\c$4261 ), + .CI(\s$4267 ), + .CON(\con$4454 ), + .SN(\sn$4455 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_30_0 ( + .A(\s$3931 ), + .B(\c$4265 ), + .CI(\s$4271 ), + .CON(\con$4456 ), + .SN(\sn$4457 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_31_0 ( + .A(\s$3939 ), + .B(\c$4269 ), + .CI(\s$4275 ), + .CON(\con$4458 ), + .SN(\sn$4459 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_32_0 ( + .A(\s$3947 ), + .B(\c$4273 ), + .CI(\s$4279 ), + .CON(\con$4460 ), + .SN(\sn$4461 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_33_0 ( + .A(\s$3955 ), + .B(\c$4277 ), + .CI(\s$4283 ), + .CON(\con$4462 ), + .SN(\sn$4463 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_34_0 ( + .A(\s$3963 ), + .B(\c$4281 ), + .CI(\s$4287 ), + .CON(\con$4464 ), + .SN(\sn$4465 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_35_0 ( + .A(\s$3971 ), + .B(\c$4285 ), + .CI(\s$4291 ), + .CON(\con$4466 ), + .SN(\sn$4467 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_36_0 ( + .A(\s$3979 ), + .B(\c$4289 ), + .CI(\s$4295 ), + .CON(\con$4468 ), + .SN(\sn$4469 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_37_0 ( + .A(\s$3987 ), + .B(\c$4293 ), + .CI(\s$4299 ), + .CON(\con$4470 ), + .SN(\sn$4471 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_38_0 ( + .A(\s$3995 ), + .B(\c$4297 ), + .CI(\s$4303 ), + .CON(\con$4472 ), + .SN(\sn$4473 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_39_0 ( + .A(\s$4003 ), + .B(\c$4301 ), + .CI(\s$4307 ), + .CON(\con$4474 ), + .SN(\sn$4475 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_40_0 ( + .A(\s$4011 ), + .B(\c$4305 ), + .CI(\s$4311 ), + .CON(\con$4476 ), + .SN(\sn$4477 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_41_0 ( + .A(\s$4019 ), + .B(\c$4309 ), + .CI(\s$4315 ), + .CON(\con$4478 ), + .SN(\sn$4479 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_42_0 ( + .A(\s$4027 ), + .B(\c$4313 ), + .CI(\s$4319 ), + .CON(\con$4480 ), + .SN(\sn$4481 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_43_0 ( + .A(\s$4035 ), + .B(\c$4317 ), + .CI(\s$4323 ), + .CON(\con$4482 ), + .SN(\sn$4483 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_44_0 ( + .A(\s$4043 ), + .B(\c$4321 ), + .CI(\s$4327 ), + .CON(\con$4484 ), + .SN(\sn$4485 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_45_0 ( + .A(\s$4051 ), + .B(\c$4325 ), + .CI(\s$4331 ), + .CON(\con$4486 ), + .SN(\sn$4487 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_46_0 ( + .A(\s$4059 ), + .B(\c$4329 ), + .CI(\s$4335 ), + .CON(\con$4488 ), + .SN(\sn$4489 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_47_0 ( + .A(\s$4067 ), + .B(\c$4333 ), + .CI(\s$4339 ), + .CON(\con$4490 ), + .SN(\sn$4491 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_48_0 ( + .A(\s$4075 ), + .B(\c$4337 ), + .CI(\s$4343 ), + .CON(\con$4492 ), + .SN(\sn$4493 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_49_0 ( + .A(\s$4083 ), + .B(\c$4341 ), + .CI(\s$4347 ), + .CON(\con$4494 ), + .SN(\sn$4495 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_4_0 ( + .A(pp_row4_2), + .B(pp_row4_3), + .CI(\s$4167 ), + .CON(\con$4404 ), + .SN(\sn$4405 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_50_0 ( + .A(\s$4091 ), + .B(\c$4345 ), + .CI(\s$4351 ), + .CON(\con$4496 ), + .SN(\sn$4497 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_51_0 ( + .A(\s$4099 ), + .B(\c$4349 ), + .CI(\s$4355 ), + .CON(\con$4498 ), + .SN(\sn$4499 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_52_0 ( + .A(\s$4107 ), + .B(\c$4353 ), + .CI(\s$4359 ), + .CON(\con$4500 ), + .SN(\sn$4501 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_53_0 ( + .A(\s$4115 ), + .B(\c$4357 ), + .CI(\s$4363 ), + .CON(\con$4502 ), + .SN(\sn$4503 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_54_0 ( + .A(\s$4123 ), + .B(\c$4361 ), + .CI(\s$4367 ), + .CON(\con$4504 ), + .SN(\sn$4505 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_55_0 ( + .A(\s$4131 ), + .B(\c$4365 ), + .CI(\s$4371 ), + .CON(\con$4506 ), + .SN(\sn$4507 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_56_0 ( + .A(\s$4139 ), + .B(\c$4369 ), + .CI(\s$4375 ), + .CON(\con$4508 ), + .SN(\sn$4509 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_57_0 ( + .A(\s$4147 ), + .B(\c$4373 ), + .CI(\s$4379 ), + .CON(\con$4510 ), + .SN(\sn$4511 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_58_0 ( + .A(\s$4155 ), + .B(\c$4377 ), + .CI(\s$4383 ), + .CON(\con$4512 ), + .SN(\sn$4513 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_59_0 ( + .A(\s$4159 ), + .B(\c$4381 ), + .CI(\s$4387 ), + .CON(\con$4514 ), + .SN(\sn$4515 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_5_0 ( + .A(pp_row5_2), + .B(\c$4165 ), + .CI(\s$4171 ), + .CON(\con$4406 ), + .SN(\sn$4407 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_60_0 ( + .A(\s$4163 ), + .B(\c$4385 ), + .CI(\s$4391 ), + .CON(\con$4516 ), + .SN(\sn$4517 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_61_0 ( + .A(\c$4161 ), + .B(\c$4389 ), + .CI(\s$4395 ), + .CON(\con$4518 ), + .SN(\sn$4519 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_62_0 ( + .A(pp_row62_2), + .B(\c$4393 ), + .CI(\s$4399 ), + .CON(\con$4520 ), + .SN(\sn$4521 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_63_0 ( + .A(pp_row63_0), + .B(pp_row63_1), + .CI(\c$4397 ), + .CON(\con$4522 ), + .SN(\sn$4523 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_6_0 ( + .A(\s$3743 ), + .B(\c$4169 ), + .CI(\s$4175 ), + .CON(\con$4408 ), + .SN(\sn$4409 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_7_0 ( + .A(\s$3747 ), + .B(\c$4173 ), + .CI(\s$4179 ), + .CON(\con$4410 ), + .SN(\sn$4411 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_8_0 ( + .A(\s$3755 ), + .B(\c$4177 ), + .CI(\s$4183 ), + .CON(\con$4412 ), + .SN(\sn$4413 ) + ); + FAx1_ASAP7_75t_R dadda_fa_5_9_0 ( + .A(\s$3763 ), + .B(\c$4181 ), + .CI(\s$4187 ), + .CON(\con$4414 ), + .SN(\sn$4415 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_24_0 ( + .A(pp_row24_0), + .B(pp_row24_1), + .CON(con), + .SN(sn) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_25_0 ( + .A(pp_row25_0), + .B(pp_row25_1), + .CON(\con$2556 ), + .SN(\sn$2558 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_26_1 ( + .A(pp_row26_3), + .B(pp_row26_4), + .CON(\con$2564 ), + .SN(\sn$2566 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_27_1 ( + .A(pp_row27_3), + .B(pp_row27_4), + .CON(\con$2572 ), + .SN(\sn$2574 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_28_2 ( + .A(pp_row28_6), + .B(pp_row28_7), + .CON(\con$2584 ), + .SN(\sn$2586 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_29_2 ( + .A(pp_row29_6), + .B(pp_row29_7), + .CON(\con$2596 ), + .SN(\sn$2598 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_30_3 ( + .A(pp_row30_9), + .B(pp_row30_10), + .CON(\con$2612 ), + .SN(\sn$2614 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_31_3 ( + .A(pp_row31_9), + .B(pp_row31_10), + .CON(\con$2628 ), + .SN(\sn$2630 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_36_3 ( + .A(pp_row36_9), + .B(pp_row36_10), + .CON(\con$2708 ), + .SN(\sn$2710 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_38_2 ( + .A(pp_row38_6), + .B(pp_row38_7), + .CON(\con$2732 ), + .SN(\sn$2734 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_40_1 ( + .A(pp_row40_3), + .B(pp_row40_4), + .CON(\con$2748 ), + .SN(\sn$2750 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_0_42_0 ( + .A(1'h1), + .B(pp_row42_1), + .CON(\con$2756 ), + .SN(\sn$2758 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_16_0 ( + .A(pp_row16_0), + .B(pp_row16_1), + .CON(\con$2760 ), + .SN(\sn$2762 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_17_0 ( + .A(pp_row17_0), + .B(pp_row17_1), + .CON(\con$2764 ), + .SN(\sn$2766 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_18_1 ( + .A(pp_row18_3), + .B(pp_row18_4), + .CON(\con$2772 ), + .SN(\sn$2774 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_19_1 ( + .A(pp_row19_3), + .B(pp_row19_4), + .CON(\con$2780 ), + .SN(\sn$2782 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_20_2 ( + .A(pp_row20_6), + .B(pp_row20_7), + .CON(\con$2792 ), + .SN(\sn$2794 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_21_2 ( + .A(pp_row21_6), + .B(pp_row21_7), + .CON(\con$2804 ), + .SN(\sn$2806 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_22_3 ( + .A(pp_row22_9), + .B(pp_row22_10), + .CON(\con$2820 ), + .SN(\sn$2822 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_23_3 ( + .A(pp_row23_9), + .B(pp_row23_10), + .CON(\con$2836 ), + .SN(\sn$2838 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_44_3 ( + .A(pp_row44_9), + .B(pp_row44_10), + .CON(\con$3172 ), + .SN(\sn$3174 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_46_2 ( + .A(pp_row46_6), + .B(pp_row46_7), + .CON(\con$3196 ), + .SN(\sn$3198 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_48_1 ( + .A(pp_row48_3), + .B(pp_row48_4), + .CON(\con$3212 ), + .SN(\sn$3214 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_1_50_0 ( + .A(1'h1), + .B(pp_row50_1), + .CON(\con$3220 ), + .SN(\sn$3222 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_10_0 ( + .A(pp_row10_0), + .B(pp_row10_1), + .CON(\con$3224 ), + .SN(\sn$3226 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_11_0 ( + .A(pp_row11_0), + .B(pp_row11_1), + .CON(\con$3228 ), + .SN(\sn$3230 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_12_1 ( + .A(pp_row12_3), + .B(pp_row12_4), + .CON(\con$3236 ), + .SN(\sn$3238 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_13_1 ( + .A(pp_row13_3), + .B(pp_row13_4), + .CON(\con$3244 ), + .SN(\sn$3246 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_14_2 ( + .A(pp_row14_6), + .B(pp_row14_7), + .CON(\con$3256 ), + .SN(\sn$3258 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_15_2 ( + .A(pp_row15_6), + .B(pp_row15_7), + .CON(\con$3268 ), + .SN(\sn$3270 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_52_2 ( + .A(pp_row52_6), + .B(pp_row52_7), + .CON(\con$3712 ), + .SN(\sn$3714 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_54_1 ( + .A(pp_row54_3), + .B(pp_row54_4), + .CON(\con$3728 ), + .SN(\sn$3730 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_2_56_0 ( + .A(1'h1), + .B(pp_row56_1), + .CON(\con$3736 ), + .SN(\sn$3738 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_58_1 ( + .A(pp_row58_3), + .B(pp_row58_4), + .CON(\con$4152 ), + .SN(\sn$4154 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_60_0 ( + .A(1'h1), + .B(pp_row60_1), + .CON(\con$4160 ), + .SN(\sn$4162 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_6_0 ( + .A(pp_row6_0), + .B(pp_row6_1), + .CON(\con$3740 ), + .SN(\sn$3742 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_7_0 ( + .A(pp_row7_0), + .B(pp_row7_1), + .CON(\con$3744 ), + .SN(\sn$3746 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_8_1 ( + .A(pp_row8_3), + .B(pp_row8_4), + .CON(\con$3752 ), + .SN(\sn$3754 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_3_9_1 ( + .A(pp_row9_3), + .B(pp_row9_4), + .CON(\con$3760 ), + .SN(\sn$3762 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_4_0 ( + .A(pp_row4_0), + .B(pp_row4_1), + .CON(\con$4164 ), + .SN(\sn$4166 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_5_0 ( + .A(pp_row5_0), + .B(pp_row5_1), + .CON(\con$4168 ), + .SN(\sn$4170 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_4_62_0 ( + .A(1'h1), + .B(pp_row62_1), + .CON(\con$4396 ), + .SN(\sn$4398 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_2_0 ( + .A(pp_row2_0), + .B(pp_row2_1), + .CON(\con$4400 ), + .SN(\sn$4401 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_3_0 ( + .A(pp_row3_0), + .B(pp_row3_1), + .CON(\con$4402 ), + .SN(\sn$4403 ) + ); + HAxp5_ASAP7_75t_R dadda_ha_5_64_0 ( + .A(1'h1), + .B(pp_row64_1), + .CON(\con$4524 ), + .SN(\sn$4525 ) + ); + \multiplier.final_adder final_adder ( + .a(final_a_registered), + .b(final_b_registered), + .\port$901$0 (\$54 ), + .\port$902$0 (\$55 ), + .\port$903$0 (\$56 ), + .\port$904$0 (\$57 ), + .\port$905$0 (\$58 ), + .\port$906$0 (\$59 ), + .\port$907$0 (\$60 ), + .\port$908$0 (\$61 ), + .\port$909$0 (\$62 ), + .\port$910$0 (\$63 ), + .\port$911$0 (\$64 ), + .\port$912$0 (\$65 ), + .\port$913$0 (\$66 ), + .\port$914$0 (\$67 ), + .\port$915$0 (\$68 ), + .\port$916$0 (\$69 ), + .\port$917$0 (\$70 ), + .\port$918$0 (\$71 ), + .\port$919$0 (\$72 ), + .\port$920$0 (\$73 ), + .\port$921$0 (\$74 ), + .\port$922$0 (\$75 ), + .\port$923$0 (\$76 ), + .\port$924$0 (\$77 ), + .\port$925$0 (\$78 ), + .\port$926$0 (\$79 ), + .\port$927$0 (\$80 ), + .\port$928$0 (\$81 ), + .\port$929$0 (\$82 ), + .\port$930$0 (\$83 ), + .\port$931$0 (\$84 ), + .\port$932$0 (\$85 ), + .\port$933$0 (\$86 ), + .\port$934$0 (\$87 ), + .\port$935$0 (\$88 ), + .\port$936$0 (\$89 ), + .\port$937$0 (\$90 ), + .\port$938$0 (\$91 ), + .\port$939$0 (\$92 ), + .\port$940$0 (\$93 ), + .\port$941$0 (\$94 ), + .\port$942$0 (\$95 ), + .\port$943$0 (\$96 ), + .\port$944$0 (\$97 ), + .\port$945$0 (\$98 ), + .\port$946$0 (\$99 ), + .\port$947$0 (\$100 ), + .\port$948$0 (\$101 ), + .\port$949$0 (\$102 ), + .\port$950$0 (\$103 ), + .\port$951$0 (\$104 ), + .\port$952$0 (\$105 ), + .\port$953$0 (\$106 ), + .\port$954$0 (\$107 ), + .\port$955$0 (\$108 ), + .\port$956$0 (\$109 ), + .\port$957$0 (\$110 ), + .\port$958$0 (\$111 ), + .\port$959$0 (\$112 ), + .\port$960$0 (\$113 ), + .\port$961$0 (\$114 ), + .\port$962$0 (\$115 ), + .\port$963$0 (\$116 ), + .\port$964$0 (\$117 ) + ); + assign booth_block0_sign = a_registered[1]; + assign booth_block2_sign = a_registered[3]; + assign booth_block4_sign = a_registered[5]; + assign booth_block6_sign = a_registered[7]; + assign booth_block8_sign = a_registered[9]; + assign booth_block10_sign = a_registered[11]; + assign booth_block12_sign = a_registered[13]; + assign booth_block14_sign = a_registered[15]; + assign booth_block16_sign = a_registered[17]; + assign booth_block18_sign = a_registered[19]; + assign booth_block20_sign = a_registered[21]; + assign booth_block22_sign = a_registered[23]; + assign booth_block24_sign = a_registered[25]; + assign booth_block26_sign = a_registered[27]; + assign booth_block28_sign = a_registered[29]; + assign booth_block30_sign = a_registered[31]; + assign result_registered = o; + assign result = { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + assign multiplier = { 2'h0, a_registered, 1'h0 }; + assign multiplicand = { 1'h0, b_registered, 1'h0 }; + assign booth_block0 = { a_registered[1:0], 1'h0 }; + assign booth_block0_sel = { sel_1, sel_0 }; + assign booth_block0_mand0 = { b_registered[0], 1'h0 }; + assign booth_block0_mand1 = b_registered[1:0]; + assign booth_block0_mand2 = b_registered[2:1]; + assign booth_block0_mand3 = b_registered[3:2]; + assign booth_block0_mand4 = b_registered[4:3]; + assign booth_block0_mand5 = b_registered[5:4]; + assign booth_block0_mand6 = b_registered[6:5]; + assign booth_block0_mand7 = b_registered[7:6]; + assign booth_block0_mand8 = b_registered[8:7]; + assign booth_block0_mand9 = b_registered[9:8]; + assign booth_block0_mand10 = b_registered[10:9]; + assign booth_block0_mand11 = b_registered[11:10]; + assign booth_block0_mand12 = b_registered[12:11]; + assign booth_block0_mand13 = b_registered[13:12]; + assign booth_block0_mand14 = b_registered[14:13]; + assign booth_block0_mand15 = b_registered[15:14]; + assign booth_block0_mand16 = b_registered[16:15]; + assign booth_block0_mand17 = b_registered[17:16]; + assign booth_block0_mand18 = b_registered[18:17]; + assign booth_block0_mand19 = b_registered[19:18]; + assign booth_block0_mand20 = b_registered[20:19]; + assign booth_block0_mand21 = b_registered[21:20]; + assign booth_block0_mand22 = b_registered[22:21]; + assign booth_block0_mand23 = b_registered[23:22]; + assign booth_block0_mand24 = b_registered[24:23]; + assign booth_block0_mand25 = b_registered[25:24]; + assign booth_block0_mand26 = b_registered[26:25]; + assign booth_block0_mand27 = b_registered[27:26]; + assign booth_block0_mand28 = b_registered[28:27]; + assign booth_block0_mand29 = b_registered[29:28]; + assign booth_block0_mand30 = b_registered[30:29]; + assign booth_block0_mand31 = b_registered[31:30]; + assign booth_block0_mand32 = { 1'h0, b_registered[31] }; + assign booth_block2 = a_registered[3:1]; + assign booth_block2_sel = { \sel_1$1366 , \sel_0$1365 }; + assign booth_block2_mand0 = { b_registered[0], 1'h0 }; + assign booth_block2_mand1 = b_registered[1:0]; + assign booth_block2_mand2 = b_registered[2:1]; + assign booth_block2_mand3 = b_registered[3:2]; + assign booth_block2_mand4 = b_registered[4:3]; + assign booth_block2_mand5 = b_registered[5:4]; + assign booth_block2_mand6 = b_registered[6:5]; + assign booth_block2_mand7 = b_registered[7:6]; + assign booth_block2_mand8 = b_registered[8:7]; + assign booth_block2_mand9 = b_registered[9:8]; + assign booth_block2_mand10 = b_registered[10:9]; + assign booth_block2_mand11 = b_registered[11:10]; + assign booth_block2_mand12 = b_registered[12:11]; + assign booth_block2_mand13 = b_registered[13:12]; + assign booth_block2_mand14 = b_registered[14:13]; + assign booth_block2_mand15 = b_registered[15:14]; + assign booth_block2_mand16 = b_registered[16:15]; + assign booth_block2_mand17 = b_registered[17:16]; + assign booth_block2_mand18 = b_registered[18:17]; + assign booth_block2_mand19 = b_registered[19:18]; + assign booth_block2_mand20 = b_registered[20:19]; + assign booth_block2_mand21 = b_registered[21:20]; + assign booth_block2_mand22 = b_registered[22:21]; + assign booth_block2_mand23 = b_registered[23:22]; + assign booth_block2_mand24 = b_registered[24:23]; + assign booth_block2_mand25 = b_registered[25:24]; + assign booth_block2_mand26 = b_registered[26:25]; + assign booth_block2_mand27 = b_registered[27:26]; + assign booth_block2_mand28 = b_registered[28:27]; + assign booth_block2_mand29 = b_registered[29:28]; + assign booth_block2_mand30 = b_registered[30:29]; + assign booth_block2_mand31 = b_registered[31:30]; + assign booth_block2_mand32 = { 1'h0, b_registered[31] }; + assign booth_block4 = a_registered[5:3]; + assign booth_block4_sel = { \sel_1$1403 , \sel_0$1402 }; + assign booth_block4_mand0 = { b_registered[0], 1'h0 }; + assign booth_block4_mand1 = b_registered[1:0]; + assign booth_block4_mand2 = b_registered[2:1]; + assign booth_block4_mand3 = b_registered[3:2]; + assign booth_block4_mand4 = b_registered[4:3]; + assign booth_block4_mand5 = b_registered[5:4]; + assign booth_block4_mand6 = b_registered[6:5]; + assign booth_block4_mand7 = b_registered[7:6]; + assign booth_block4_mand8 = b_registered[8:7]; + assign booth_block4_mand9 = b_registered[9:8]; + assign booth_block4_mand10 = b_registered[10:9]; + assign booth_block4_mand11 = b_registered[11:10]; + assign booth_block4_mand12 = b_registered[12:11]; + assign booth_block4_mand13 = b_registered[13:12]; + assign booth_block4_mand14 = b_registered[14:13]; + assign booth_block4_mand15 = b_registered[15:14]; + assign booth_block4_mand16 = b_registered[16:15]; + assign booth_block4_mand17 = b_registered[17:16]; + assign booth_block4_mand18 = b_registered[18:17]; + assign booth_block4_mand19 = b_registered[19:18]; + assign booth_block4_mand20 = b_registered[20:19]; + assign booth_block4_mand21 = b_registered[21:20]; + assign booth_block4_mand22 = b_registered[22:21]; + assign booth_block4_mand23 = b_registered[23:22]; + assign booth_block4_mand24 = b_registered[24:23]; + assign booth_block4_mand25 = b_registered[25:24]; + assign booth_block4_mand26 = b_registered[26:25]; + assign booth_block4_mand27 = b_registered[27:26]; + assign booth_block4_mand28 = b_registered[28:27]; + assign booth_block4_mand29 = b_registered[29:28]; + assign booth_block4_mand30 = b_registered[30:29]; + assign booth_block4_mand31 = b_registered[31:30]; + assign booth_block4_mand32 = { 1'h0, b_registered[31] }; + assign booth_block6 = a_registered[7:5]; + assign booth_block6_sel = { \sel_1$1440 , \sel_0$1439 }; + assign booth_block6_mand0 = { b_registered[0], 1'h0 }; + assign booth_block6_mand1 = b_registered[1:0]; + assign booth_block6_mand2 = b_registered[2:1]; + assign booth_block6_mand3 = b_registered[3:2]; + assign booth_block6_mand4 = b_registered[4:3]; + assign booth_block6_mand5 = b_registered[5:4]; + assign booth_block6_mand6 = b_registered[6:5]; + assign booth_block6_mand7 = b_registered[7:6]; + assign booth_block6_mand8 = b_registered[8:7]; + assign booth_block6_mand9 = b_registered[9:8]; + assign booth_block6_mand10 = b_registered[10:9]; + assign booth_block6_mand11 = b_registered[11:10]; + assign booth_block6_mand12 = b_registered[12:11]; + assign booth_block6_mand13 = b_registered[13:12]; + assign booth_block6_mand14 = b_registered[14:13]; + assign booth_block6_mand15 = b_registered[15:14]; + assign booth_block6_mand16 = b_registered[16:15]; + assign booth_block6_mand17 = b_registered[17:16]; + assign booth_block6_mand18 = b_registered[18:17]; + assign booth_block6_mand19 = b_registered[19:18]; + assign booth_block6_mand20 = b_registered[20:19]; + assign booth_block6_mand21 = b_registered[21:20]; + assign booth_block6_mand22 = b_registered[22:21]; + assign booth_block6_mand23 = b_registered[23:22]; + assign booth_block6_mand24 = b_registered[24:23]; + assign booth_block6_mand25 = b_registered[25:24]; + assign booth_block6_mand26 = b_registered[26:25]; + assign booth_block6_mand27 = b_registered[27:26]; + assign booth_block6_mand28 = b_registered[28:27]; + assign booth_block6_mand29 = b_registered[29:28]; + assign booth_block6_mand30 = b_registered[30:29]; + assign booth_block6_mand31 = b_registered[31:30]; + assign booth_block6_mand32 = { 1'h0, b_registered[31] }; + assign booth_block8 = a_registered[9:7]; + assign booth_block8_sel = { \sel_1$1477 , \sel_0$1476 }; + assign booth_block8_mand0 = { b_registered[0], 1'h0 }; + assign booth_block8_mand1 = b_registered[1:0]; + assign booth_block8_mand2 = b_registered[2:1]; + assign booth_block8_mand3 = b_registered[3:2]; + assign booth_block8_mand4 = b_registered[4:3]; + assign booth_block8_mand5 = b_registered[5:4]; + assign booth_block8_mand6 = b_registered[6:5]; + assign booth_block8_mand7 = b_registered[7:6]; + assign booth_block8_mand8 = b_registered[8:7]; + assign booth_block8_mand9 = b_registered[9:8]; + assign booth_block8_mand10 = b_registered[10:9]; + assign booth_block8_mand11 = b_registered[11:10]; + assign booth_block8_mand12 = b_registered[12:11]; + assign booth_block8_mand13 = b_registered[13:12]; + assign booth_block8_mand14 = b_registered[14:13]; + assign booth_block8_mand15 = b_registered[15:14]; + assign booth_block8_mand16 = b_registered[16:15]; + assign booth_block8_mand17 = b_registered[17:16]; + assign booth_block8_mand18 = b_registered[18:17]; + assign booth_block8_mand19 = b_registered[19:18]; + assign booth_block8_mand20 = b_registered[20:19]; + assign booth_block8_mand21 = b_registered[21:20]; + assign booth_block8_mand22 = b_registered[22:21]; + assign booth_block8_mand23 = b_registered[23:22]; + assign booth_block8_mand24 = b_registered[24:23]; + assign booth_block8_mand25 = b_registered[25:24]; + assign booth_block8_mand26 = b_registered[26:25]; + assign booth_block8_mand27 = b_registered[27:26]; + assign booth_block8_mand28 = b_registered[28:27]; + assign booth_block8_mand29 = b_registered[29:28]; + assign booth_block8_mand30 = b_registered[30:29]; + assign booth_block8_mand31 = b_registered[31:30]; + assign booth_block8_mand32 = { 1'h0, b_registered[31] }; + assign booth_block10 = a_registered[11:9]; + assign booth_block10_sel = { \sel_1$1514 , \sel_0$1513 }; + assign booth_block10_mand0 = { b_registered[0], 1'h0 }; + assign booth_block10_mand1 = b_registered[1:0]; + assign booth_block10_mand2 = b_registered[2:1]; + assign booth_block10_mand3 = b_registered[3:2]; + assign booth_block10_mand4 = b_registered[4:3]; + assign booth_block10_mand5 = b_registered[5:4]; + assign booth_block10_mand6 = b_registered[6:5]; + assign booth_block10_mand7 = b_registered[7:6]; + assign booth_block10_mand8 = b_registered[8:7]; + assign booth_block10_mand9 = b_registered[9:8]; + assign booth_block10_mand10 = b_registered[10:9]; + assign booth_block10_mand11 = b_registered[11:10]; + assign booth_block10_mand12 = b_registered[12:11]; + assign booth_block10_mand13 = b_registered[13:12]; + assign booth_block10_mand14 = b_registered[14:13]; + assign booth_block10_mand15 = b_registered[15:14]; + assign booth_block10_mand16 = b_registered[16:15]; + assign booth_block10_mand17 = b_registered[17:16]; + assign booth_block10_mand18 = b_registered[18:17]; + assign booth_block10_mand19 = b_registered[19:18]; + assign booth_block10_mand20 = b_registered[20:19]; + assign booth_block10_mand21 = b_registered[21:20]; + assign booth_block10_mand22 = b_registered[22:21]; + assign booth_block10_mand23 = b_registered[23:22]; + assign booth_block10_mand24 = b_registered[24:23]; + assign booth_block10_mand25 = b_registered[25:24]; + assign booth_block10_mand26 = b_registered[26:25]; + assign booth_block10_mand27 = b_registered[27:26]; + assign booth_block10_mand28 = b_registered[28:27]; + assign booth_block10_mand29 = b_registered[29:28]; + assign booth_block10_mand30 = b_registered[30:29]; + assign booth_block10_mand31 = b_registered[31:30]; + assign booth_block10_mand32 = { 1'h0, b_registered[31] }; + assign booth_block12 = a_registered[13:11]; + assign booth_block12_sel = { \sel_1$1551 , \sel_0$1550 }; + assign booth_block12_mand0 = { b_registered[0], 1'h0 }; + assign booth_block12_mand1 = b_registered[1:0]; + assign booth_block12_mand2 = b_registered[2:1]; + assign booth_block12_mand3 = b_registered[3:2]; + assign booth_block12_mand4 = b_registered[4:3]; + assign booth_block12_mand5 = b_registered[5:4]; + assign booth_block12_mand6 = b_registered[6:5]; + assign booth_block12_mand7 = b_registered[7:6]; + assign booth_block12_mand8 = b_registered[8:7]; + assign booth_block12_mand9 = b_registered[9:8]; + assign booth_block12_mand10 = b_registered[10:9]; + assign booth_block12_mand11 = b_registered[11:10]; + assign booth_block12_mand12 = b_registered[12:11]; + assign booth_block12_mand13 = b_registered[13:12]; + assign booth_block12_mand14 = b_registered[14:13]; + assign booth_block12_mand15 = b_registered[15:14]; + assign booth_block12_mand16 = b_registered[16:15]; + assign booth_block12_mand17 = b_registered[17:16]; + assign booth_block12_mand18 = b_registered[18:17]; + assign booth_block12_mand19 = b_registered[19:18]; + assign booth_block12_mand20 = b_registered[20:19]; + assign booth_block12_mand21 = b_registered[21:20]; + assign booth_block12_mand22 = b_registered[22:21]; + assign booth_block12_mand23 = b_registered[23:22]; + assign booth_block12_mand24 = b_registered[24:23]; + assign booth_block12_mand25 = b_registered[25:24]; + assign booth_block12_mand26 = b_registered[26:25]; + assign booth_block12_mand27 = b_registered[27:26]; + assign booth_block12_mand28 = b_registered[28:27]; + assign booth_block12_mand29 = b_registered[29:28]; + assign booth_block12_mand30 = b_registered[30:29]; + assign booth_block12_mand31 = b_registered[31:30]; + assign booth_block12_mand32 = { 1'h0, b_registered[31] }; + assign booth_block14 = a_registered[15:13]; + assign booth_block14_sel = { \sel_1$1588 , \sel_0$1587 }; + assign booth_block14_mand0 = { b_registered[0], 1'h0 }; + assign booth_block14_mand1 = b_registered[1:0]; + assign booth_block14_mand2 = b_registered[2:1]; + assign booth_block14_mand3 = b_registered[3:2]; + assign booth_block14_mand4 = b_registered[4:3]; + assign booth_block14_mand5 = b_registered[5:4]; + assign booth_block14_mand6 = b_registered[6:5]; + assign booth_block14_mand7 = b_registered[7:6]; + assign booth_block14_mand8 = b_registered[8:7]; + assign booth_block14_mand9 = b_registered[9:8]; + assign booth_block14_mand10 = b_registered[10:9]; + assign booth_block14_mand11 = b_registered[11:10]; + assign booth_block14_mand12 = b_registered[12:11]; + assign booth_block14_mand13 = b_registered[13:12]; + assign booth_block14_mand14 = b_registered[14:13]; + assign booth_block14_mand15 = b_registered[15:14]; + assign booth_block14_mand16 = b_registered[16:15]; + assign booth_block14_mand17 = b_registered[17:16]; + assign booth_block14_mand18 = b_registered[18:17]; + assign booth_block14_mand19 = b_registered[19:18]; + assign booth_block14_mand20 = b_registered[20:19]; + assign booth_block14_mand21 = b_registered[21:20]; + assign booth_block14_mand22 = b_registered[22:21]; + assign booth_block14_mand23 = b_registered[23:22]; + assign booth_block14_mand24 = b_registered[24:23]; + assign booth_block14_mand25 = b_registered[25:24]; + assign booth_block14_mand26 = b_registered[26:25]; + assign booth_block14_mand27 = b_registered[27:26]; + assign booth_block14_mand28 = b_registered[28:27]; + assign booth_block14_mand29 = b_registered[29:28]; + assign booth_block14_mand30 = b_registered[30:29]; + assign booth_block14_mand31 = b_registered[31:30]; + assign booth_block14_mand32 = { 1'h0, b_registered[31] }; + assign booth_block16 = a_registered[17:15]; + assign booth_block16_sel = { \sel_1$1625 , \sel_0$1624 }; + assign booth_block16_mand0 = { b_registered[0], 1'h0 }; + assign booth_block16_mand1 = b_registered[1:0]; + assign booth_block16_mand2 = b_registered[2:1]; + assign booth_block16_mand3 = b_registered[3:2]; + assign booth_block16_mand4 = b_registered[4:3]; + assign booth_block16_mand5 = b_registered[5:4]; + assign booth_block16_mand6 = b_registered[6:5]; + assign booth_block16_mand7 = b_registered[7:6]; + assign booth_block16_mand8 = b_registered[8:7]; + assign booth_block16_mand9 = b_registered[9:8]; + assign booth_block16_mand10 = b_registered[10:9]; + assign booth_block16_mand11 = b_registered[11:10]; + assign booth_block16_mand12 = b_registered[12:11]; + assign booth_block16_mand13 = b_registered[13:12]; + assign booth_block16_mand14 = b_registered[14:13]; + assign booth_block16_mand15 = b_registered[15:14]; + assign booth_block16_mand16 = b_registered[16:15]; + assign booth_block16_mand17 = b_registered[17:16]; + assign booth_block16_mand18 = b_registered[18:17]; + assign booth_block16_mand19 = b_registered[19:18]; + assign booth_block16_mand20 = b_registered[20:19]; + assign booth_block16_mand21 = b_registered[21:20]; + assign booth_block16_mand22 = b_registered[22:21]; + assign booth_block16_mand23 = b_registered[23:22]; + assign booth_block16_mand24 = b_registered[24:23]; + assign booth_block16_mand25 = b_registered[25:24]; + assign booth_block16_mand26 = b_registered[26:25]; + assign booth_block16_mand27 = b_registered[27:26]; + assign booth_block16_mand28 = b_registered[28:27]; + assign booth_block16_mand29 = b_registered[29:28]; + assign booth_block16_mand30 = b_registered[30:29]; + assign booth_block16_mand31 = b_registered[31:30]; + assign booth_block16_mand32 = { 1'h0, b_registered[31] }; + assign booth_block18 = a_registered[19:17]; + assign booth_block18_sel = { \sel_1$1662 , \sel_0$1661 }; + assign booth_block18_mand0 = { b_registered[0], 1'h0 }; + assign booth_block18_mand1 = b_registered[1:0]; + assign booth_block18_mand2 = b_registered[2:1]; + assign booth_block18_mand3 = b_registered[3:2]; + assign booth_block18_mand4 = b_registered[4:3]; + assign booth_block18_mand5 = b_registered[5:4]; + assign booth_block18_mand6 = b_registered[6:5]; + assign booth_block18_mand7 = b_registered[7:6]; + assign booth_block18_mand8 = b_registered[8:7]; + assign booth_block18_mand9 = b_registered[9:8]; + assign booth_block18_mand10 = b_registered[10:9]; + assign booth_block18_mand11 = b_registered[11:10]; + assign booth_block18_mand12 = b_registered[12:11]; + assign booth_block18_mand13 = b_registered[13:12]; + assign booth_block18_mand14 = b_registered[14:13]; + assign booth_block18_mand15 = b_registered[15:14]; + assign booth_block18_mand16 = b_registered[16:15]; + assign booth_block18_mand17 = b_registered[17:16]; + assign booth_block18_mand18 = b_registered[18:17]; + assign booth_block18_mand19 = b_registered[19:18]; + assign booth_block18_mand20 = b_registered[20:19]; + assign booth_block18_mand21 = b_registered[21:20]; + assign booth_block18_mand22 = b_registered[22:21]; + assign booth_block18_mand23 = b_registered[23:22]; + assign booth_block18_mand24 = b_registered[24:23]; + assign booth_block18_mand25 = b_registered[25:24]; + assign booth_block18_mand26 = b_registered[26:25]; + assign booth_block18_mand27 = b_registered[27:26]; + assign booth_block18_mand28 = b_registered[28:27]; + assign booth_block18_mand29 = b_registered[29:28]; + assign booth_block18_mand30 = b_registered[30:29]; + assign booth_block18_mand31 = b_registered[31:30]; + assign booth_block18_mand32 = { 1'h0, b_registered[31] }; + assign booth_block20 = a_registered[21:19]; + assign booth_block20_sel = { \sel_1$1699 , \sel_0$1698 }; + assign booth_block20_mand0 = { b_registered[0], 1'h0 }; + assign booth_block20_mand1 = b_registered[1:0]; + assign booth_block20_mand2 = b_registered[2:1]; + assign booth_block20_mand3 = b_registered[3:2]; + assign booth_block20_mand4 = b_registered[4:3]; + assign booth_block20_mand5 = b_registered[5:4]; + assign booth_block20_mand6 = b_registered[6:5]; + assign booth_block20_mand7 = b_registered[7:6]; + assign booth_block20_mand8 = b_registered[8:7]; + assign booth_block20_mand9 = b_registered[9:8]; + assign booth_block20_mand10 = b_registered[10:9]; + assign booth_block20_mand11 = b_registered[11:10]; + assign booth_block20_mand12 = b_registered[12:11]; + assign booth_block20_mand13 = b_registered[13:12]; + assign booth_block20_mand14 = b_registered[14:13]; + assign booth_block20_mand15 = b_registered[15:14]; + assign booth_block20_mand16 = b_registered[16:15]; + assign booth_block20_mand17 = b_registered[17:16]; + assign booth_block20_mand18 = b_registered[18:17]; + assign booth_block20_mand19 = b_registered[19:18]; + assign booth_block20_mand20 = b_registered[20:19]; + assign booth_block20_mand21 = b_registered[21:20]; + assign booth_block20_mand22 = b_registered[22:21]; + assign booth_block20_mand23 = b_registered[23:22]; + assign booth_block20_mand24 = b_registered[24:23]; + assign booth_block20_mand25 = b_registered[25:24]; + assign booth_block20_mand26 = b_registered[26:25]; + assign booth_block20_mand27 = b_registered[27:26]; + assign booth_block20_mand28 = b_registered[28:27]; + assign booth_block20_mand29 = b_registered[29:28]; + assign booth_block20_mand30 = b_registered[30:29]; + assign booth_block20_mand31 = b_registered[31:30]; + assign booth_block20_mand32 = { 1'h0, b_registered[31] }; + assign booth_block22 = a_registered[23:21]; + assign booth_block22_sel = { \sel_1$1736 , \sel_0$1735 }; + assign booth_block22_mand0 = { b_registered[0], 1'h0 }; + assign booth_block22_mand1 = b_registered[1:0]; + assign booth_block22_mand2 = b_registered[2:1]; + assign booth_block22_mand3 = b_registered[3:2]; + assign booth_block22_mand4 = b_registered[4:3]; + assign booth_block22_mand5 = b_registered[5:4]; + assign booth_block22_mand6 = b_registered[6:5]; + assign booth_block22_mand7 = b_registered[7:6]; + assign booth_block22_mand8 = b_registered[8:7]; + assign booth_block22_mand9 = b_registered[9:8]; + assign booth_block22_mand10 = b_registered[10:9]; + assign booth_block22_mand11 = b_registered[11:10]; + assign booth_block22_mand12 = b_registered[12:11]; + assign booth_block22_mand13 = b_registered[13:12]; + assign booth_block22_mand14 = b_registered[14:13]; + assign booth_block22_mand15 = b_registered[15:14]; + assign booth_block22_mand16 = b_registered[16:15]; + assign booth_block22_mand17 = b_registered[17:16]; + assign booth_block22_mand18 = b_registered[18:17]; + assign booth_block22_mand19 = b_registered[19:18]; + assign booth_block22_mand20 = b_registered[20:19]; + assign booth_block22_mand21 = b_registered[21:20]; + assign booth_block22_mand22 = b_registered[22:21]; + assign booth_block22_mand23 = b_registered[23:22]; + assign booth_block22_mand24 = b_registered[24:23]; + assign booth_block22_mand25 = b_registered[25:24]; + assign booth_block22_mand26 = b_registered[26:25]; + assign booth_block22_mand27 = b_registered[27:26]; + assign booth_block22_mand28 = b_registered[28:27]; + assign booth_block22_mand29 = b_registered[29:28]; + assign booth_block22_mand30 = b_registered[30:29]; + assign booth_block22_mand31 = b_registered[31:30]; + assign booth_block22_mand32 = { 1'h0, b_registered[31] }; + assign booth_block24 = a_registered[25:23]; + assign booth_block24_sel = { \sel_1$1773 , \sel_0$1772 }; + assign booth_block24_mand0 = { b_registered[0], 1'h0 }; + assign booth_block24_mand1 = b_registered[1:0]; + assign booth_block24_mand2 = b_registered[2:1]; + assign booth_block24_mand3 = b_registered[3:2]; + assign booth_block24_mand4 = b_registered[4:3]; + assign booth_block24_mand5 = b_registered[5:4]; + assign booth_block24_mand6 = b_registered[6:5]; + assign booth_block24_mand7 = b_registered[7:6]; + assign booth_block24_mand8 = b_registered[8:7]; + assign booth_block24_mand9 = b_registered[9:8]; + assign booth_block24_mand10 = b_registered[10:9]; + assign booth_block24_mand11 = b_registered[11:10]; + assign booth_block24_mand12 = b_registered[12:11]; + assign booth_block24_mand13 = b_registered[13:12]; + assign booth_block24_mand14 = b_registered[14:13]; + assign booth_block24_mand15 = b_registered[15:14]; + assign booth_block24_mand16 = b_registered[16:15]; + assign booth_block24_mand17 = b_registered[17:16]; + assign booth_block24_mand18 = b_registered[18:17]; + assign booth_block24_mand19 = b_registered[19:18]; + assign booth_block24_mand20 = b_registered[20:19]; + assign booth_block24_mand21 = b_registered[21:20]; + assign booth_block24_mand22 = b_registered[22:21]; + assign booth_block24_mand23 = b_registered[23:22]; + assign booth_block24_mand24 = b_registered[24:23]; + assign booth_block24_mand25 = b_registered[25:24]; + assign booth_block24_mand26 = b_registered[26:25]; + assign booth_block24_mand27 = b_registered[27:26]; + assign booth_block24_mand28 = b_registered[28:27]; + assign booth_block24_mand29 = b_registered[29:28]; + assign booth_block24_mand30 = b_registered[30:29]; + assign booth_block24_mand31 = b_registered[31:30]; + assign booth_block24_mand32 = { 1'h0, b_registered[31] }; + assign booth_block26 = a_registered[27:25]; + assign booth_block26_sel = { \sel_1$1810 , \sel_0$1809 }; + assign booth_block26_mand0 = { b_registered[0], 1'h0 }; + assign booth_block26_mand1 = b_registered[1:0]; + assign booth_block26_mand2 = b_registered[2:1]; + assign booth_block26_mand3 = b_registered[3:2]; + assign booth_block26_mand4 = b_registered[4:3]; + assign booth_block26_mand5 = b_registered[5:4]; + assign booth_block26_mand6 = b_registered[6:5]; + assign booth_block26_mand7 = b_registered[7:6]; + assign booth_block26_mand8 = b_registered[8:7]; + assign booth_block26_mand9 = b_registered[9:8]; + assign booth_block26_mand10 = b_registered[10:9]; + assign booth_block26_mand11 = b_registered[11:10]; + assign booth_block26_mand12 = b_registered[12:11]; + assign booth_block26_mand13 = b_registered[13:12]; + assign booth_block26_mand14 = b_registered[14:13]; + assign booth_block26_mand15 = b_registered[15:14]; + assign booth_block26_mand16 = b_registered[16:15]; + assign booth_block26_mand17 = b_registered[17:16]; + assign booth_block26_mand18 = b_registered[18:17]; + assign booth_block26_mand19 = b_registered[19:18]; + assign booth_block26_mand20 = b_registered[20:19]; + assign booth_block26_mand21 = b_registered[21:20]; + assign booth_block26_mand22 = b_registered[22:21]; + assign booth_block26_mand23 = b_registered[23:22]; + assign booth_block26_mand24 = b_registered[24:23]; + assign booth_block26_mand25 = b_registered[25:24]; + assign booth_block26_mand26 = b_registered[26:25]; + assign booth_block26_mand27 = b_registered[27:26]; + assign booth_block26_mand28 = b_registered[28:27]; + assign booth_block26_mand29 = b_registered[29:28]; + assign booth_block26_mand30 = b_registered[30:29]; + assign booth_block26_mand31 = b_registered[31:30]; + assign booth_block26_mand32 = { 1'h0, b_registered[31] }; + assign booth_block28 = a_registered[29:27]; + assign booth_block28_sel = { \sel_1$1847 , \sel_0$1846 }; + assign booth_block28_mand0 = { b_registered[0], 1'h0 }; + assign booth_block28_mand1 = b_registered[1:0]; + assign booth_block28_mand2 = b_registered[2:1]; + assign booth_block28_mand3 = b_registered[3:2]; + assign booth_block28_mand4 = b_registered[4:3]; + assign booth_block28_mand5 = b_registered[5:4]; + assign booth_block28_mand6 = b_registered[6:5]; + assign booth_block28_mand7 = b_registered[7:6]; + assign booth_block28_mand8 = b_registered[8:7]; + assign booth_block28_mand9 = b_registered[9:8]; + assign booth_block28_mand10 = b_registered[10:9]; + assign booth_block28_mand11 = b_registered[11:10]; + assign booth_block28_mand12 = b_registered[12:11]; + assign booth_block28_mand13 = b_registered[13:12]; + assign booth_block28_mand14 = b_registered[14:13]; + assign booth_block28_mand15 = b_registered[15:14]; + assign booth_block28_mand16 = b_registered[16:15]; + assign booth_block28_mand17 = b_registered[17:16]; + assign booth_block28_mand18 = b_registered[18:17]; + assign booth_block28_mand19 = b_registered[19:18]; + assign booth_block28_mand20 = b_registered[20:19]; + assign booth_block28_mand21 = b_registered[21:20]; + assign booth_block28_mand22 = b_registered[22:21]; + assign booth_block28_mand23 = b_registered[23:22]; + assign booth_block28_mand24 = b_registered[24:23]; + assign booth_block28_mand25 = b_registered[25:24]; + assign booth_block28_mand26 = b_registered[26:25]; + assign booth_block28_mand27 = b_registered[27:26]; + assign booth_block28_mand28 = b_registered[28:27]; + assign booth_block28_mand29 = b_registered[29:28]; + assign booth_block28_mand30 = b_registered[30:29]; + assign booth_block28_mand31 = b_registered[31:30]; + assign booth_block28_mand32 = { 1'h0, b_registered[31] }; + assign booth_block30 = a_registered[31:29]; + assign booth_block30_sel = { \sel_1$1884 , \sel_0$1883 }; + assign booth_block30_mand0 = { b_registered[0], 1'h0 }; + assign booth_block30_mand1 = b_registered[1:0]; + assign booth_block30_mand2 = b_registered[2:1]; + assign booth_block30_mand3 = b_registered[3:2]; + assign booth_block30_mand4 = b_registered[4:3]; + assign booth_block30_mand5 = b_registered[5:4]; + assign booth_block30_mand6 = b_registered[6:5]; + assign booth_block30_mand7 = b_registered[7:6]; + assign booth_block30_mand8 = b_registered[8:7]; + assign booth_block30_mand9 = b_registered[9:8]; + assign booth_block30_mand10 = b_registered[10:9]; + assign booth_block30_mand11 = b_registered[11:10]; + assign booth_block30_mand12 = b_registered[12:11]; + assign booth_block30_mand13 = b_registered[13:12]; + assign booth_block30_mand14 = b_registered[14:13]; + assign booth_block30_mand15 = b_registered[15:14]; + assign booth_block30_mand16 = b_registered[16:15]; + assign booth_block30_mand17 = b_registered[17:16]; + assign booth_block30_mand18 = b_registered[18:17]; + assign booth_block30_mand19 = b_registered[19:18]; + assign booth_block30_mand20 = b_registered[20:19]; + assign booth_block30_mand21 = b_registered[21:20]; + assign booth_block30_mand22 = b_registered[22:21]; + assign booth_block30_mand23 = b_registered[23:22]; + assign booth_block30_mand24 = b_registered[24:23]; + assign booth_block30_mand25 = b_registered[25:24]; + assign booth_block30_mand26 = b_registered[26:25]; + assign booth_block30_mand27 = b_registered[27:26]; + assign booth_block30_mand28 = b_registered[28:27]; + assign booth_block30_mand29 = b_registered[29:28]; + assign booth_block30_mand30 = b_registered[30:29]; + assign booth_block30_mand31 = b_registered[31:30]; + assign booth_block30_mand32 = { 1'h0, b_registered[31] }; + assign booth_block32 = { 2'h0, a_registered[31] }; + assign booth_block32_sign = 1'h0; + assign booth_block32_sel = { \sel_1$1922 , \sel_0$1921 }; + assign booth_block32_mand0 = { b_registered[0], 1'h0 }; + assign booth_block32_mand1 = b_registered[1:0]; + assign booth_block32_mand2 = b_registered[2:1]; + assign booth_block32_mand3 = b_registered[3:2]; + assign booth_block32_mand4 = b_registered[4:3]; + assign booth_block32_mand5 = b_registered[5:4]; + assign booth_block32_mand6 = b_registered[6:5]; + assign booth_block32_mand7 = b_registered[7:6]; + assign booth_block32_mand8 = b_registered[8:7]; + assign booth_block32_mand9 = b_registered[9:8]; + assign booth_block32_mand10 = b_registered[10:9]; + assign booth_block32_mand11 = b_registered[11:10]; + assign booth_block32_mand12 = b_registered[12:11]; + assign booth_block32_mand13 = b_registered[13:12]; + assign booth_block32_mand14 = b_registered[14:13]; + assign booth_block32_mand15 = b_registered[15:14]; + assign booth_block32_mand16 = b_registered[16:15]; + assign booth_block32_mand17 = b_registered[17:16]; + assign booth_block32_mand18 = b_registered[18:17]; + assign booth_block32_mand19 = b_registered[19:18]; + assign booth_block32_mand20 = b_registered[20:19]; + assign booth_block32_mand21 = b_registered[21:20]; + assign booth_block32_mand22 = b_registered[22:21]; + assign booth_block32_mand23 = b_registered[23:22]; + assign booth_block32_mand24 = b_registered[24:23]; + assign booth_block32_mand25 = b_registered[25:24]; + assign booth_block32_mand26 = b_registered[26:25]; + assign booth_block32_mand27 = b_registered[27:26]; + assign booth_block32_mand28 = b_registered[28:27]; + assign booth_block32_mand29 = b_registered[29:28]; + assign booth_block32_mand30 = b_registered[30:29]; + assign booth_block32_mand31 = b_registered[31:30]; + assign booth_block32_mand32 = { 1'h0, b_registered[31] }; + assign pp_row36_0 = 1'h1; + assign pp_row38_0 = 1'h1; + assign pp_row40_0 = 1'h1; + assign pp_row42_0 = 1'h1; + assign pp_row44_0 = 1'h1; + assign pp_row46_0 = 1'h1; + assign pp_row48_0 = 1'h1; + assign pp_row50_0 = 1'h1; + assign pp_row52_0 = 1'h1; + assign pp_row54_0 = 1'h1; + assign pp_row56_0 = 1'h1; + assign pp_row58_0 = 1'h1; + assign pp_row60_0 = 1'h1; + assign pp_row62_0 = 1'h1; + assign pp_row64_0 = 1'h1; + assign \a$1971 = final_a_registered; + assign \b$1972 = final_b_registered; + assign \o$1973 = { \$117 , \$116 , \$115 , \$114 , \$113 , \$112 , \$111 , \$110 , \$109 , \$108 , \$107 , \$106 , \$105 , \$104 , \$103 , \$102 , \$101 , \$100 , \$99 , \$98 , \$97 , \$96 , \$95 , \$94 , \$93 , \$92 , \$91 , \$90 , \$89 , \$88 , \$87 , \$86 , \$85 , \$84 , \$83 , \$82 , \$81 , \$80 , \$79 , \$78 , \$77 , \$76 , \$75 , \$74 , \$73 , \$72 , \$71 , \$70 , \$69 , \$68 , \$67 , \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 }; + assign notblock = { \$3 , \$2 , \$1 }; + assign \notblock$2008 = { \$6 , \$5 , \$4 }; + assign \notblock$2042 = { \$9 , \$8 , \$7 }; + assign \notblock$2076 = { \$12 , \$11 , \$10 }; + assign \notblock$2110 = { \$15 , \$14 , \$13 }; + assign \notblock$2144 = { \$18 , \$17 , \$16 }; + assign \notblock$2178 = { \$21 , \$20 , \$19 }; + assign \notblock$2212 = { \$24 , \$23 , \$22 }; + assign \notblock$2246 = { \$27 , \$26 , \$25 }; + assign \notblock$2280 = { \$30 , \$29 , \$28 }; + assign \notblock$2314 = { \$33 , \$32 , \$31 }; + assign \notblock$2348 = { \$36 , \$35 , \$34 }; + assign \notblock$2382 = { \$39 , \$38 , \$37 }; + assign \notblock$2416 = { \$42 , \$41 , \$40 }; + assign \notblock$2450 = { \$45 , \$44 , \$43 }; + assign \notblock$2484 = { \$48 , \$47 , \$46 }; + assign \notblock$2518 = { \$51 , \$50 , \$49 }; +endmodule + +module \multiplier.final_adder (\port$902$0 , \port$903$0 , \port$904$0 , \port$905$0 , \port$906$0 , \port$907$0 , \port$908$0 , \port$909$0 , \port$910$0 , \port$911$0 , \port$912$0 , \port$913$0 , \port$914$0 , \port$915$0 , \port$916$0 , \port$917$0 , \port$918$0 , \port$919$0 , \port$920$0 , \port$921$0 , \port$922$0 +, \port$923$0 , \port$924$0 , \port$925$0 , \port$926$0 , \port$927$0 , \port$928$0 , \port$929$0 , \port$930$0 , \port$931$0 , \port$932$0 , \port$933$0 , \port$934$0 , \port$935$0 , \port$936$0 , \port$937$0 , \port$938$0 , \port$939$0 , \port$940$0 , \port$941$0 , \port$942$0 , \port$943$0 +, \port$944$0 , \port$945$0 , \port$946$0 , \port$947$0 , \port$948$0 , \port$949$0 , \port$950$0 , \port$951$0 , \port$952$0 , \port$953$0 , \port$954$0 , \port$955$0 , \port$956$0 , \port$957$0 , \port$958$0 , \port$959$0 , \port$960$0 , \port$961$0 , \port$962$0 , \port$963$0 , \port$964$0 +, a, b, \port$901$0 ); + wire \$1 ; + wire \$10 ; + wire \$11 ; + wire \$12 ; + wire \$13 ; + wire \$14 ; + wire \$15 ; + wire \$16 ; + wire \$17 ; + wire \$18 ; + wire \$19 ; + wire \$2 ; + wire \$20 ; + wire \$21 ; + wire \$22 ; + wire \$23 ; + wire \$24 ; + wire \$25 ; + wire \$26 ; + wire \$27 ; + wire \$28 ; + wire \$29 ; + wire \$3 ; + wire \$30 ; + wire \$31 ; + wire \$32 ; + wire \$33 ; + wire \$34 ; + wire \$35 ; + wire \$36 ; + wire \$37 ; + wire \$38 ; + wire \$39 ; + wire \$4 ; + wire \$40 ; + wire \$41 ; + wire \$42 ; + wire \$43 ; + wire \$44 ; + wire \$45 ; + wire \$46 ; + wire \$47 ; + wire \$48 ; + wire \$49 ; + wire \$5 ; + wire \$50 ; + wire \$51 ; + wire \$52 ; + wire \$53 ; + wire \$54 ; + wire \$55 ; + wire \$56 ; + wire \$57 ; + wire \$58 ; + wire \$59 ; + wire \$6 ; + wire \$60 ; + wire \$61 ; + wire \$62 ; + wire \$63 ; + wire \$64 ; + wire \$65 ; + wire \$66 ; + wire \$7 ; + wire \$8 ; + wire \$9 ; + wire \$signal ; + wire \$signal$10 ; + wire \$signal$100 ; + wire \$signal$101 ; + wire \$signal$102 ; + wire \$signal$103 ; + wire \$signal$104 ; + wire \$signal$105 ; + wire \$signal$106 ; + wire \$signal$107 ; + wire \$signal$108 ; + wire \$signal$109 ; + wire \$signal$11 ; + wire \$signal$110 ; + wire \$signal$111 ; + wire \$signal$112 ; + wire \$signal$113 ; + wire \$signal$114 ; + wire \$signal$115 ; + wire \$signal$116 ; + wire \$signal$117 ; + wire \$signal$118 ; + wire \$signal$119 ; + wire \$signal$12 ; + wire \$signal$120 ; + wire \$signal$121 ; + wire \$signal$122 ; + wire \$signal$123 ; + wire \$signal$124 ; + wire \$signal$125 ; + wire \$signal$126 ; + wire \$signal$127 ; + wire \$signal$128 ; + wire \$signal$129 ; + wire \$signal$13 ; + wire \$signal$130 ; + wire \$signal$131 ; + wire \$signal$14 ; + wire \$signal$15 ; + wire \$signal$16 ; + wire \$signal$17 ; + wire \$signal$18 ; + wire \$signal$19 ; + wire \$signal$20 ; + wire \$signal$21 ; + wire \$signal$22 ; + wire \$signal$23 ; + wire \$signal$24 ; + wire \$signal$25 ; + wire \$signal$26 ; + wire \$signal$263 ; + wire \$signal$264 ; + wire \$signal$265 ; + wire \$signal$266 ; + wire \$signal$267 ; + wire \$signal$268 ; + wire \$signal$269 ; + wire \$signal$27 ; + wire \$signal$270 ; + wire \$signal$271 ; + wire \$signal$272 ; + wire \$signal$273 ; + wire \$signal$274 ; + wire \$signal$275 ; + wire \$signal$276 ; + wire \$signal$277 ; + wire \$signal$278 ; + wire \$signal$279 ; + wire \$signal$28 ; + wire \$signal$280 ; + wire \$signal$281 ; + wire \$signal$282 ; + wire \$signal$283 ; + wire \$signal$284 ; + wire \$signal$285 ; + wire \$signal$286 ; + wire \$signal$287 ; + wire \$signal$288 ; + wire \$signal$289 ; + wire \$signal$29 ; + wire \$signal$290 ; + wire \$signal$291 ; + wire \$signal$292 ; + wire \$signal$293 ; + wire \$signal$294 ; + wire \$signal$295 ; + wire \$signal$296 ; + wire \$signal$297 ; + wire \$signal$298 ; + wire \$signal$299 ; + wire \$signal$30 ; + wire \$signal$300 ; + wire \$signal$301 ; + wire \$signal$302 ; + wire \$signal$303 ; + wire \$signal$304 ; + wire \$signal$305 ; + wire \$signal$306 ; + wire \$signal$307 ; + wire \$signal$308 ; + wire \$signal$309 ; + wire \$signal$31 ; + wire \$signal$310 ; + wire \$signal$311 ; + wire \$signal$312 ; + wire \$signal$313 ; + wire \$signal$314 ; + wire \$signal$315 ; + wire \$signal$316 ; + wire \$signal$317 ; + wire \$signal$318 ; + wire \$signal$319 ; + wire \$signal$32 ; + wire \$signal$320 ; + wire \$signal$321 ; + wire \$signal$322 ; + wire \$signal$323 ; + wire \$signal$324 ; + wire \$signal$325 ; + wire \$signal$326 ; + wire \$signal$33 ; + wire \$signal$34 ; + wire \$signal$35 ; + wire \$signal$36 ; + wire \$signal$37 ; + wire \$signal$38 ; + wire \$signal$39 ; + wire \$signal$40 ; + wire \$signal$41 ; + wire \$signal$42 ; + wire \$signal$43 ; + wire \$signal$44 ; + wire \$signal$45 ; + wire \$signal$46 ; + wire \$signal$47 ; + wire \$signal$48 ; + wire \$signal$49 ; + wire \$signal$5 ; + wire \$signal$50 ; + wire \$signal$51 ; + wire \$signal$52 ; + wire \$signal$53 ; + wire \$signal$54 ; + wire \$signal$55 ; + wire \$signal$56 ; + wire \$signal$57 ; + wire \$signal$58 ; + wire \$signal$59 ; + wire \$signal$6 ; + wire \$signal$60 ; + wire \$signal$61 ; + wire \$signal$62 ; + wire \$signal$63 ; + wire \$signal$64 ; + wire \$signal$65 ; + wire \$signal$66 ; + wire \$signal$67 ; + wire \$signal$68 ; + wire \$signal$69 ; + wire \$signal$7 ; + wire \$signal$70 ; + wire \$signal$71 ; + wire \$signal$72 ; + wire \$signal$73 ; + wire \$signal$74 ; + wire \$signal$75 ; + wire \$signal$76 ; + wire \$signal$77 ; + wire \$signal$78 ; + wire \$signal$79 ; + wire \$signal$8 ; + wire \$signal$80 ; + wire \$signal$81 ; + wire \$signal$82 ; + wire \$signal$83 ; + wire \$signal$84 ; + wire \$signal$85 ; + wire \$signal$86 ; + wire \$signal$87 ; + wire \$signal$88 ; + wire \$signal$89 ; + wire \$signal$9 ; + wire \$signal$90 ; + wire \$signal$91 ; + wire \$signal$92 ; + wire \$signal$93 ; + wire \$signal$94 ; + wire \$signal$95 ; + wire \$signal$96 ; + wire \$signal$97 ; + wire \$signal$98 ; + wire \$signal$99 ; + input [63:0] a; + wire [63:0] a; + wire [63:0] \a$1 ; + input [63:0] b; + wire [63:0] b; + wire [63:0] \b$3 ; + wire con; + wire \con$137 ; + wire \con$139 ; + wire \con$141 ; + wire \con$143 ; + wire \con$145 ; + wire \con$147 ; + wire \con$149 ; + wire \con$151 ; + wire \con$153 ; + wire \con$155 ; + wire \con$157 ; + wire \con$159 ; + wire \con$161 ; + wire \con$163 ; + wire \con$165 ; + wire \con$167 ; + wire \con$169 ; + wire \con$171 ; + wire \con$173 ; + wire \con$175 ; + wire \con$177 ; + wire \con$179 ; + wire \con$181 ; + wire \con$183 ; + wire \con$185 ; + wire \con$187 ; + wire \con$189 ; + wire \con$191 ; + wire \con$193 ; + wire \con$195 ; + wire \con$197 ; + wire \con$199 ; + wire \con$201 ; + wire \con$203 ; + wire \con$205 ; + wire \con$207 ; + wire \con$209 ; + wire \con$211 ; + wire \con$213 ; + wire \con$215 ; + wire \con$217 ; + wire \con$219 ; + wire \con$221 ; + wire \con$223 ; + wire \con$225 ; + wire \con$227 ; + wire \con$229 ; + wire \con$231 ; + wire \con$233 ; + wire \con$235 ; + wire \con$237 ; + wire \con$239 ; + wire \con$241 ; + wire \con$243 ; + wire \con$245 ; + wire \con$247 ; + wire \con$249 ; + wire \con$251 ; + wire \con$253 ; + wire \con$255 ; + wire \con$257 ; + wire \con$259 ; + wire \con$261 ; + wire g_new; + wire \g_new$330 ; + wire \g_new$333 ; + wire \g_new$334 ; + wire \g_new$337 ; + wire \g_new$338 ; + wire \g_new$341 ; + wire \g_new$342 ; + wire \g_new$345 ; + wire \g_new$346 ; + wire \g_new$349 ; + wire \g_new$350 ; + wire \g_new$353 ; + wire \g_new$354 ; + wire \g_new$357 ; + wire \g_new$358 ; + wire \g_new$361 ; + wire \g_new$362 ; + wire \g_new$365 ; + wire \g_new$366 ; + wire \g_new$369 ; + wire \g_new$370 ; + wire \g_new$373 ; + wire \g_new$374 ; + wire \g_new$377 ; + wire \g_new$378 ; + wire \g_new$381 ; + wire \g_new$382 ; + wire \g_new$385 ; + wire \g_new$386 ; + wire \g_new$389 ; + wire \g_new$390 ; + wire \g_new$393 ; + wire \g_new$394 ; + wire \g_new$397 ; + wire \g_new$398 ; + wire \g_new$401 ; + wire \g_new$402 ; + wire \g_new$405 ; + wire \g_new$406 ; + wire \g_new$409 ; + wire \g_new$410 ; + wire \g_new$413 ; + wire \g_new$414 ; + wire \g_new$417 ; + wire \g_new$418 ; + wire \g_new$421 ; + wire \g_new$422 ; + wire \g_new$425 ; + wire \g_new$426 ; + wire \g_new$429 ; + wire \g_new$430 ; + wire \g_new$433 ; + wire \g_new$434 ; + wire \g_new$437 ; + wire \g_new$438 ; + wire \g_new$441 ; + wire \g_new$442 ; + wire \g_new$445 ; + wire \g_new$446 ; + wire \g_new$449 ; + wire \g_new$450 ; + wire \g_new$451 ; + wire \g_new$452 ; + wire \g_new$453 ; + wire \g_new$454 ; + wire \g_new$455 ; + wire \g_new$456 ; + wire \g_new$457 ; + wire \g_new$458 ; + wire \g_new$459 ; + wire \g_new$460 ; + wire \g_new$461 ; + wire \g_new$462 ; + wire \g_new$463 ; + wire \g_new$464 ; + wire \g_new$465 ; + wire \g_new$466 ; + wire \g_new$467 ; + wire \g_new$468 ; + wire \g_new$469 ; + wire \g_new$470 ; + wire \g_new$471 ; + wire \g_new$472 ; + wire \g_new$473 ; + wire \g_new$474 ; + wire \g_new$475 ; + wire \g_new$476 ; + wire \g_new$477 ; + wire \g_new$478 ; + wire \g_new$479 ; + wire \g_new$480 ; + wire \g_new$481 ; + wire \g_new$482 ; + wire \g_new$483 ; + wire \g_new$484 ; + wire \g_new$485 ; + wire \g_new$486 ; + wire \g_new$487 ; + wire \g_new$488 ; + wire \g_new$489 ; + wire \g_new$490 ; + wire \g_new$491 ; + wire \g_new$492 ; + wire \g_new$493 ; + wire \g_new$494 ; + wire \g_new$495 ; + wire \g_new$496 ; + wire \g_new$497 ; + wire \g_new$498 ; + wire \g_new$499 ; + wire \g_new$500 ; + wire \g_new$501 ; + wire \g_new$502 ; + wire \g_new$503 ; + wire \g_new$504 ; + wire \g_new$505 ; + wire \g_new$506 ; + wire \g_new$507 ; + wire [63:0] o; + wire [63:0] \o$134 ; + wire [63:0] o2; + wire p_new; + wire \p_new$328 ; + wire \p_new$331 ; + wire \p_new$332 ; + wire \p_new$335 ; + wire \p_new$336 ; + wire \p_new$339 ; + wire \p_new$340 ; + wire \p_new$343 ; + wire \p_new$344 ; + wire \p_new$347 ; + wire \p_new$348 ; + wire \p_new$351 ; + wire \p_new$352 ; + wire \p_new$355 ; + wire \p_new$356 ; + wire \p_new$359 ; + wire \p_new$360 ; + wire \p_new$363 ; + wire \p_new$364 ; + wire \p_new$367 ; + wire \p_new$368 ; + wire \p_new$371 ; + wire \p_new$372 ; + wire \p_new$375 ; + wire \p_new$376 ; + wire \p_new$379 ; + wire \p_new$380 ; + wire \p_new$383 ; + wire \p_new$384 ; + wire \p_new$387 ; + wire \p_new$388 ; + wire \p_new$391 ; + wire \p_new$392 ; + wire \p_new$395 ; + wire \p_new$396 ; + wire \p_new$399 ; + wire \p_new$400 ; + wire \p_new$403 ; + wire \p_new$404 ; + wire \p_new$407 ; + wire \p_new$408 ; + wire \p_new$411 ; + wire \p_new$412 ; + wire \p_new$415 ; + wire \p_new$416 ; + wire \p_new$419 ; + wire \p_new$420 ; + wire \p_new$423 ; + wire \p_new$424 ; + wire \p_new$427 ; + wire \p_new$428 ; + wire \p_new$431 ; + wire \p_new$432 ; + wire \p_new$435 ; + wire \p_new$436 ; + wire \p_new$439 ; + wire \p_new$440 ; + wire \p_new$443 ; + wire \p_new$444 ; + wire \p_new$447 ; + wire \p_new$448 ; + output \port$901$0 ; + wire \port$901$0 ; + output \port$902$0 ; + wire \port$902$0 ; + output \port$903$0 ; + wire \port$903$0 ; + output \port$904$0 ; + wire \port$904$0 ; + output \port$905$0 ; + wire \port$905$0 ; + output \port$906$0 ; + wire \port$906$0 ; + output \port$907$0 ; + wire \port$907$0 ; + output \port$908$0 ; + wire \port$908$0 ; + output \port$909$0 ; + wire \port$909$0 ; + output \port$910$0 ; + wire \port$910$0 ; + output \port$911$0 ; + wire \port$911$0 ; + output \port$912$0 ; + wire \port$912$0 ; + output \port$913$0 ; + wire \port$913$0 ; + output \port$914$0 ; + wire \port$914$0 ; + output \port$915$0 ; + wire \port$915$0 ; + output \port$916$0 ; + wire \port$916$0 ; + output \port$917$0 ; + wire \port$917$0 ; + output \port$918$0 ; + wire \port$918$0 ; + output \port$919$0 ; + wire \port$919$0 ; + output \port$920$0 ; + wire \port$920$0 ; + output \port$921$0 ; + wire \port$921$0 ; + output \port$922$0 ; + wire \port$922$0 ; + output \port$923$0 ; + wire \port$923$0 ; + output \port$924$0 ; + wire \port$924$0 ; + output \port$925$0 ; + wire \port$925$0 ; + output \port$926$0 ; + wire \port$926$0 ; + output \port$927$0 ; + wire \port$927$0 ; + output \port$928$0 ; + wire \port$928$0 ; + output \port$929$0 ; + wire \port$929$0 ; + output \port$930$0 ; + wire \port$930$0 ; + output \port$931$0 ; + wire \port$931$0 ; + output \port$932$0 ; + wire \port$932$0 ; + output \port$933$0 ; + wire \port$933$0 ; + output \port$934$0 ; + wire \port$934$0 ; + output \port$935$0 ; + wire \port$935$0 ; + output \port$936$0 ; + wire \port$936$0 ; + output \port$937$0 ; + wire \port$937$0 ; + output \port$938$0 ; + wire \port$938$0 ; + output \port$939$0 ; + wire \port$939$0 ; + output \port$940$0 ; + wire \port$940$0 ; + output \port$941$0 ; + wire \port$941$0 ; + output \port$942$0 ; + wire \port$942$0 ; + output \port$943$0 ; + wire \port$943$0 ; + output \port$944$0 ; + wire \port$944$0 ; + output \port$945$0 ; + wire \port$945$0 ; + output \port$946$0 ; + wire \port$946$0 ; + output \port$947$0 ; + wire \port$947$0 ; + output \port$948$0 ; + wire \port$948$0 ; + output \port$949$0 ; + wire \port$949$0 ; + output \port$950$0 ; + wire \port$950$0 ; + output \port$951$0 ; + wire \port$951$0 ; + output \port$952$0 ; + wire \port$952$0 ; + output \port$953$0 ; + wire \port$953$0 ; + output \port$954$0 ; + wire \port$954$0 ; + output \port$955$0 ; + wire \port$955$0 ; + output \port$956$0 ; + wire \port$956$0 ; + output \port$957$0 ; + wire \port$957$0 ; + output \port$958$0 ; + wire \port$958$0 ; + output \port$959$0 ; + wire \port$959$0 ; + output \port$960$0 ; + wire \port$960$0 ; + output \port$961$0 ; + wire \port$961$0 ; + output \port$962$0 ; + wire \port$962$0 ; + output \port$963$0 ; + wire \port$963$0 ; + output \port$964$0 ; + wire \port$964$0 ; + wire sn; + wire \sn$138 ; + wire \sn$140 ; + wire \sn$142 ; + wire \sn$144 ; + wire \sn$146 ; + wire \sn$148 ; + wire \sn$150 ; + wire \sn$152 ; + wire \sn$154 ; + wire \sn$156 ; + wire \sn$158 ; + wire \sn$160 ; + wire \sn$162 ; + wire \sn$164 ; + wire \sn$166 ; + wire \sn$168 ; + wire \sn$170 ; + wire \sn$172 ; + wire \sn$174 ; + wire \sn$176 ; + wire \sn$178 ; + wire \sn$180 ; + wire \sn$182 ; + wire \sn$184 ; + wire \sn$186 ; + wire \sn$188 ; + wire \sn$190 ; + wire \sn$192 ; + wire \sn$194 ; + wire \sn$196 ; + wire \sn$198 ; + wire \sn$200 ; + wire \sn$202 ; + wire \sn$204 ; + wire \sn$206 ; + wire \sn$208 ; + wire \sn$210 ; + wire \sn$212 ; + wire \sn$214 ; + wire \sn$216 ; + wire \sn$218 ; + wire \sn$220 ; + wire \sn$222 ; + wire \sn$224 ; + wire \sn$226 ; + wire \sn$228 ; + wire \sn$230 ; + wire \sn$232 ; + wire \sn$234 ; + wire \sn$236 ; + wire \sn$238 ; + wire \sn$240 ; + wire \sn$242 ; + wire \sn$244 ; + wire \sn$246 ; + wire \sn$248 ; + wire \sn$250 ; + wire \sn$252 ; + wire \sn$254 ; + wire \sn$256 ; + wire \sn$258 ; + wire \sn$260 ; + wire \sn$262 ; + HAxp5_ASAP7_75t_R \U$0 ( + .A(a[0]), + .B(b[0]), + .CON(con), + .SN(sn) + ); + INVx1_ASAP7_75t_R \U$1 ( + .A(con), + .Y(\$signal$263 ) + ); + INVx1_ASAP7_75t_R \U$10 ( + .A(\con$141 ), + .Y(\$signal$266 ) + ); + INVx1_ASAP7_75t_R \U$100 ( + .A(\con$201 ), + .Y(\$signal$296 ) + ); + INVx1_ASAP7_75t_R \U$101 ( + .A(\sn$202 ), + .Y(\$signal$70 ) + ); + HAxp5_ASAP7_75t_R \U$102 ( + .A(a[34]), + .B(b[34]), + .CON(\con$203 ), + .SN(\sn$204 ) + ); + INVx1_ASAP7_75t_R \U$103 ( + .A(\con$203 ), + .Y(\$signal$297 ) + ); + INVx1_ASAP7_75t_R \U$104 ( + .A(\sn$204 ), + .Y(\$signal$72 ) + ); + HAxp5_ASAP7_75t_R \U$105 ( + .A(a[35]), + .B(b[35]), + .CON(\con$205 ), + .SN(\sn$206 ) + ); + INVx1_ASAP7_75t_R \U$106 ( + .A(\con$205 ), + .Y(\$signal$298 ) + ); + INVx1_ASAP7_75t_R \U$107 ( + .A(\sn$206 ), + .Y(\$signal$74 ) + ); + HAxp5_ASAP7_75t_R \U$108 ( + .A(a[36]), + .B(b[36]), + .CON(\con$207 ), + .SN(\sn$208 ) + ); + INVx1_ASAP7_75t_R \U$109 ( + .A(\con$207 ), + .Y(\$signal$299 ) + ); + INVx1_ASAP7_75t_R \U$11 ( + .A(\sn$142 ), + .Y(\$signal$10 ) + ); + INVx1_ASAP7_75t_R \U$110 ( + .A(\sn$208 ), + .Y(\$signal$76 ) + ); + HAxp5_ASAP7_75t_R \U$111 ( + .A(a[37]), + .B(b[37]), + .CON(\con$209 ), + .SN(\sn$210 ) + ); + INVx1_ASAP7_75t_R \U$112 ( + .A(\con$209 ), + .Y(\$signal$300 ) + ); + INVx1_ASAP7_75t_R \U$113 ( + .A(\sn$210 ), + .Y(\$signal$78 ) + ); + HAxp5_ASAP7_75t_R \U$114 ( + .A(a[38]), + .B(b[38]), + .CON(\con$211 ), + .SN(\sn$212 ) + ); + INVx1_ASAP7_75t_R \U$115 ( + .A(\con$211 ), + .Y(\$signal$301 ) + ); + INVx1_ASAP7_75t_R \U$116 ( + .A(\sn$212 ), + .Y(\$signal$80 ) + ); + HAxp5_ASAP7_75t_R \U$117 ( + .A(a[39]), + .B(b[39]), + .CON(\con$213 ), + .SN(\sn$214 ) + ); + INVx1_ASAP7_75t_R \U$118 ( + .A(\con$213 ), + .Y(\$signal$302 ) + ); + INVx1_ASAP7_75t_R \U$119 ( + .A(\sn$214 ), + .Y(\$signal$82 ) + ); + HAxp5_ASAP7_75t_R \U$12 ( + .A(a[4]), + .B(b[4]), + .CON(\con$143 ), + .SN(\sn$144 ) + ); + HAxp5_ASAP7_75t_R \U$120 ( + .A(a[40]), + .B(b[40]), + .CON(\con$215 ), + .SN(\sn$216 ) + ); + INVx1_ASAP7_75t_R \U$121 ( + .A(\con$215 ), + .Y(\$signal$303 ) + ); + INVx1_ASAP7_75t_R \U$122 ( + .A(\sn$216 ), + .Y(\$signal$84 ) + ); + HAxp5_ASAP7_75t_R \U$123 ( + .A(a[41]), + .B(b[41]), + .CON(\con$217 ), + .SN(\sn$218 ) + ); + INVx1_ASAP7_75t_R \U$124 ( + .A(\con$217 ), + .Y(\$signal$304 ) + ); + INVx1_ASAP7_75t_R \U$125 ( + .A(\sn$218 ), + .Y(\$signal$86 ) + ); + HAxp5_ASAP7_75t_R \U$126 ( + .A(a[42]), + .B(b[42]), + .CON(\con$219 ), + .SN(\sn$220 ) + ); + INVx1_ASAP7_75t_R \U$127 ( + .A(\con$219 ), + .Y(\$signal$305 ) + ); + INVx1_ASAP7_75t_R \U$128 ( + .A(\sn$220 ), + .Y(\$signal$88 ) + ); + HAxp5_ASAP7_75t_R \U$129 ( + .A(a[43]), + .B(b[43]), + .CON(\con$221 ), + .SN(\sn$222 ) + ); + INVx1_ASAP7_75t_R \U$13 ( + .A(\con$143 ), + .Y(\$signal$267 ) + ); + INVx1_ASAP7_75t_R \U$130 ( + .A(\con$221 ), + .Y(\$signal$306 ) + ); + INVx1_ASAP7_75t_R \U$131 ( + .A(\sn$222 ), + .Y(\$signal$90 ) + ); + HAxp5_ASAP7_75t_R \U$132 ( + .A(a[44]), + .B(b[44]), + .CON(\con$223 ), + .SN(\sn$224 ) + ); + INVx1_ASAP7_75t_R \U$133 ( + .A(\con$223 ), + .Y(\$signal$307 ) + ); + INVx1_ASAP7_75t_R \U$134 ( + .A(\sn$224 ), + .Y(\$signal$92 ) + ); + HAxp5_ASAP7_75t_R \U$135 ( + .A(a[45]), + .B(b[45]), + .CON(\con$225 ), + .SN(\sn$226 ) + ); + INVx1_ASAP7_75t_R \U$136 ( + .A(\con$225 ), + .Y(\$signal$308 ) + ); + INVx1_ASAP7_75t_R \U$137 ( + .A(\sn$226 ), + .Y(\$signal$94 ) + ); + HAxp5_ASAP7_75t_R \U$138 ( + .A(a[46]), + .B(b[46]), + .CON(\con$227 ), + .SN(\sn$228 ) + ); + INVx1_ASAP7_75t_R \U$139 ( + .A(\con$227 ), + .Y(\$signal$309 ) + ); + INVx1_ASAP7_75t_R \U$14 ( + .A(\sn$144 ), + .Y(\$signal$12 ) + ); + INVx1_ASAP7_75t_R \U$140 ( + .A(\sn$228 ), + .Y(\$signal$96 ) + ); + HAxp5_ASAP7_75t_R \U$141 ( + .A(a[47]), + .B(b[47]), + .CON(\con$229 ), + .SN(\sn$230 ) + ); + INVx1_ASAP7_75t_R \U$142 ( + .A(\con$229 ), + .Y(\$signal$310 ) + ); + INVx1_ASAP7_75t_R \U$143 ( + .A(\sn$230 ), + .Y(\$signal$98 ) + ); + HAxp5_ASAP7_75t_R \U$144 ( + .A(a[48]), + .B(b[48]), + .CON(\con$231 ), + .SN(\sn$232 ) + ); + INVx1_ASAP7_75t_R \U$145 ( + .A(\con$231 ), + .Y(\$signal$311 ) + ); + INVx1_ASAP7_75t_R \U$146 ( + .A(\sn$232 ), + .Y(\$signal$100 ) + ); + HAxp5_ASAP7_75t_R \U$147 ( + .A(a[49]), + .B(b[49]), + .CON(\con$233 ), + .SN(\sn$234 ) + ); + INVx1_ASAP7_75t_R \U$148 ( + .A(\con$233 ), + .Y(\$signal$312 ) + ); + INVx1_ASAP7_75t_R \U$149 ( + .A(\sn$234 ), + .Y(\$signal$102 ) + ); + HAxp5_ASAP7_75t_R \U$15 ( + .A(a[5]), + .B(b[5]), + .CON(\con$145 ), + .SN(\sn$146 ) + ); + HAxp5_ASAP7_75t_R \U$150 ( + .A(a[50]), + .B(b[50]), + .CON(\con$235 ), + .SN(\sn$236 ) + ); + INVx1_ASAP7_75t_R \U$151 ( + .A(\con$235 ), + .Y(\$signal$313 ) + ); + INVx1_ASAP7_75t_R \U$152 ( + .A(\sn$236 ), + .Y(\$signal$104 ) + ); + HAxp5_ASAP7_75t_R \U$153 ( + .A(a[51]), + .B(b[51]), + .CON(\con$237 ), + .SN(\sn$238 ) + ); + INVx1_ASAP7_75t_R \U$154 ( + .A(\con$237 ), + .Y(\$signal$314 ) + ); + INVx1_ASAP7_75t_R \U$155 ( + .A(\sn$238 ), + .Y(\$signal$106 ) + ); + HAxp5_ASAP7_75t_R \U$156 ( + .A(a[52]), + .B(b[52]), + .CON(\con$239 ), + .SN(\sn$240 ) + ); + INVx1_ASAP7_75t_R \U$157 ( + .A(\con$239 ), + .Y(\$signal$315 ) + ); + INVx1_ASAP7_75t_R \U$158 ( + .A(\sn$240 ), + .Y(\$signal$108 ) + ); + HAxp5_ASAP7_75t_R \U$159 ( + .A(a[53]), + .B(b[53]), + .CON(\con$241 ), + .SN(\sn$242 ) + ); + INVx1_ASAP7_75t_R \U$16 ( + .A(\con$145 ), + .Y(\$signal$268 ) + ); + INVx1_ASAP7_75t_R \U$160 ( + .A(\con$241 ), + .Y(\$signal$316 ) + ); + INVx1_ASAP7_75t_R \U$161 ( + .A(\sn$242 ), + .Y(\$signal$110 ) + ); + HAxp5_ASAP7_75t_R \U$162 ( + .A(a[54]), + .B(b[54]), + .CON(\con$243 ), + .SN(\sn$244 ) + ); + INVx1_ASAP7_75t_R \U$163 ( + .A(\con$243 ), + .Y(\$signal$317 ) + ); + INVx1_ASAP7_75t_R \U$164 ( + .A(\sn$244 ), + .Y(\$signal$112 ) + ); + HAxp5_ASAP7_75t_R \U$165 ( + .A(a[55]), + .B(b[55]), + .CON(\con$245 ), + .SN(\sn$246 ) + ); + INVx1_ASAP7_75t_R \U$166 ( + .A(\con$245 ), + .Y(\$signal$318 ) + ); + INVx1_ASAP7_75t_R \U$167 ( + .A(\sn$246 ), + .Y(\$signal$114 ) + ); + HAxp5_ASAP7_75t_R \U$168 ( + .A(a[56]), + .B(b[56]), + .CON(\con$247 ), + .SN(\sn$248 ) + ); + INVx1_ASAP7_75t_R \U$169 ( + .A(\con$247 ), + .Y(\$signal$319 ) + ); + INVx1_ASAP7_75t_R \U$17 ( + .A(\sn$146 ), + .Y(\$signal$14 ) + ); + INVx1_ASAP7_75t_R \U$170 ( + .A(\sn$248 ), + .Y(\$signal$116 ) + ); + HAxp5_ASAP7_75t_R \U$171 ( + .A(a[57]), + .B(b[57]), + .CON(\con$249 ), + .SN(\sn$250 ) + ); + INVx1_ASAP7_75t_R \U$172 ( + .A(\con$249 ), + .Y(\$signal$320 ) + ); + INVx1_ASAP7_75t_R \U$173 ( + .A(\sn$250 ), + .Y(\$signal$118 ) + ); + HAxp5_ASAP7_75t_R \U$174 ( + .A(a[58]), + .B(b[58]), + .CON(\con$251 ), + .SN(\sn$252 ) + ); + INVx1_ASAP7_75t_R \U$175 ( + .A(\con$251 ), + .Y(\$signal$321 ) + ); + INVx1_ASAP7_75t_R \U$176 ( + .A(\sn$252 ), + .Y(\$signal$120 ) + ); + HAxp5_ASAP7_75t_R \U$177 ( + .A(a[59]), + .B(b[59]), + .CON(\con$253 ), + .SN(\sn$254 ) + ); + INVx1_ASAP7_75t_R \U$178 ( + .A(\con$253 ), + .Y(\$signal$322 ) + ); + INVx1_ASAP7_75t_R \U$179 ( + .A(\sn$254 ), + .Y(\$signal$122 ) + ); + HAxp5_ASAP7_75t_R \U$18 ( + .A(a[6]), + .B(b[6]), + .CON(\con$147 ), + .SN(\sn$148 ) + ); + HAxp5_ASAP7_75t_R \U$180 ( + .A(a[60]), + .B(b[60]), + .CON(\con$255 ), + .SN(\sn$256 ) + ); + INVx1_ASAP7_75t_R \U$181 ( + .A(\con$255 ), + .Y(\$signal$323 ) + ); + INVx1_ASAP7_75t_R \U$182 ( + .A(\sn$256 ), + .Y(\$signal$124 ) + ); + HAxp5_ASAP7_75t_R \U$183 ( + .A(a[61]), + .B(b[61]), + .CON(\con$257 ), + .SN(\sn$258 ) + ); + INVx1_ASAP7_75t_R \U$184 ( + .A(\con$257 ), + .Y(\$signal$324 ) + ); + INVx1_ASAP7_75t_R \U$185 ( + .A(\sn$258 ), + .Y(\$signal$126 ) + ); + HAxp5_ASAP7_75t_R \U$186 ( + .A(a[62]), + .B(b[62]), + .CON(\con$259 ), + .SN(\sn$260 ) + ); + INVx1_ASAP7_75t_R \U$187 ( + .A(\con$259 ), + .Y(\$signal$325 ) + ); + INVx1_ASAP7_75t_R \U$188 ( + .A(\sn$260 ), + .Y(\$signal$128 ) + ); + HAxp5_ASAP7_75t_R \U$189 ( + .A(a[63]), + .B(b[63]), + .CON(\con$261 ), + .SN(\sn$262 ) + ); + INVx1_ASAP7_75t_R \U$19 ( + .A(\con$147 ), + .Y(\$signal$269 ) + ); + INVx1_ASAP7_75t_R \U$190 ( + .A(\con$261 ), + .Y(\$signal$326 ) + ); + INVx1_ASAP7_75t_R \U$191 ( + .A(\sn$262 ), + .Y(\$signal$130 ) + ); + AND2x2_ASAP7_75t_R \U$192 ( + .A(\$signal$6 ), + .B(\$signal ), + .Y(\p_new$328 ) + ); + AO21x1_ASAP7_75t_R \U$193 ( + .A1(\$signal$6 ), + .A2(\$signal$263 ), + .B(\$signal$264 ), + .Y(g_new) + ); + AND2x2_ASAP7_75t_R \U$194 ( + .A(\$signal$10 ), + .B(\$signal$8 ), + .Y(p_new) + ); + AO21x1_ASAP7_75t_R \U$195 ( + .A1(\$signal$10 ), + .A2(\$signal$265 ), + .B(\$signal$266 ), + .Y(\g_new$330 ) + ); + AND2x2_ASAP7_75t_R \U$196 ( + .A(\$signal$14 ), + .B(\$signal$12 ), + .Y(\p_new$332 ) + ); + AO21x1_ASAP7_75t_R \U$197 ( + .A1(\$signal$14 ), + .A2(\$signal$267 ), + .B(\$signal$268 ), + .Y(\g_new$333 ) + ); + AND2x2_ASAP7_75t_R \U$198 ( + .A(\$signal$18 ), + .B(\$signal$16 ), + .Y(\p_new$331 ) + ); + AO21x1_ASAP7_75t_R \U$199 ( + .A1(\$signal$18 ), + .A2(\$signal$269 ), + .B(\$signal$270 ), + .Y(\g_new$334 ) + ); + INVx1_ASAP7_75t_R \U$2 ( + .A(sn), + .Y(\$signal ) + ); + INVx1_ASAP7_75t_R \U$20 ( + .A(\sn$148 ), + .Y(\$signal$16 ) + ); + AND2x2_ASAP7_75t_R \U$200 ( + .A(\$signal$22 ), + .B(\$signal$20 ), + .Y(\p_new$336 ) + ); + AO21x1_ASAP7_75t_R \U$201 ( + .A1(\$signal$22 ), + .A2(\$signal$271 ), + .B(\$signal$272 ), + .Y(\g_new$337 ) + ); + AND2x2_ASAP7_75t_R \U$202 ( + .A(\$signal$26 ), + .B(\$signal$24 ), + .Y(\p_new$335 ) + ); + AO21x1_ASAP7_75t_R \U$203 ( + .A1(\$signal$26 ), + .A2(\$signal$273 ), + .B(\$signal$274 ), + .Y(\g_new$338 ) + ); + AND2x2_ASAP7_75t_R \U$204 ( + .A(\$signal$30 ), + .B(\$signal$28 ), + .Y(\p_new$340 ) + ); + AO21x1_ASAP7_75t_R \U$205 ( + .A1(\$signal$30 ), + .A2(\$signal$275 ), + .B(\$signal$276 ), + .Y(\g_new$341 ) + ); + AND2x2_ASAP7_75t_R \U$206 ( + .A(\$signal$34 ), + .B(\$signal$32 ), + .Y(\p_new$339 ) + ); + AO21x1_ASAP7_75t_R \U$207 ( + .A1(\$signal$34 ), + .A2(\$signal$277 ), + .B(\$signal$278 ), + .Y(\g_new$342 ) + ); + AND2x2_ASAP7_75t_R \U$208 ( + .A(\$signal$38 ), + .B(\$signal$36 ), + .Y(\p_new$344 ) + ); + AO21x1_ASAP7_75t_R \U$209 ( + .A1(\$signal$38 ), + .A2(\$signal$279 ), + .B(\$signal$280 ), + .Y(\g_new$345 ) + ); + HAxp5_ASAP7_75t_R \U$21 ( + .A(a[7]), + .B(b[7]), + .CON(\con$149 ), + .SN(\sn$150 ) + ); + AND2x2_ASAP7_75t_R \U$210 ( + .A(\$signal$42 ), + .B(\$signal$40 ), + .Y(\p_new$343 ) + ); + AO21x1_ASAP7_75t_R \U$211 ( + .A1(\$signal$42 ), + .A2(\$signal$281 ), + .B(\$signal$282 ), + .Y(\g_new$346 ) + ); + AND2x2_ASAP7_75t_R \U$212 ( + .A(\$signal$46 ), + .B(\$signal$44 ), + .Y(\p_new$348 ) + ); + AO21x1_ASAP7_75t_R \U$213 ( + .A1(\$signal$46 ), + .A2(\$signal$283 ), + .B(\$signal$284 ), + .Y(\g_new$349 ) + ); + AND2x2_ASAP7_75t_R \U$214 ( + .A(\$signal$50 ), + .B(\$signal$48 ), + .Y(\p_new$347 ) + ); + AO21x1_ASAP7_75t_R \U$215 ( + .A1(\$signal$50 ), + .A2(\$signal$285 ), + .B(\$signal$286 ), + .Y(\g_new$350 ) + ); + AND2x2_ASAP7_75t_R \U$216 ( + .A(\$signal$54 ), + .B(\$signal$52 ), + .Y(\p_new$352 ) + ); + AO21x1_ASAP7_75t_R \U$217 ( + .A1(\$signal$54 ), + .A2(\$signal$287 ), + .B(\$signal$288 ), + .Y(\g_new$353 ) + ); + AND2x2_ASAP7_75t_R \U$218 ( + .A(\$signal$58 ), + .B(\$signal$56 ), + .Y(\p_new$351 ) + ); + AO21x1_ASAP7_75t_R \U$219 ( + .A1(\$signal$58 ), + .A2(\$signal$289 ), + .B(\$signal$290 ), + .Y(\g_new$354 ) + ); + INVx1_ASAP7_75t_R \U$22 ( + .A(\con$149 ), + .Y(\$signal$270 ) + ); + AND2x2_ASAP7_75t_R \U$220 ( + .A(\$signal$62 ), + .B(\$signal$60 ), + .Y(\p_new$356 ) + ); + AO21x1_ASAP7_75t_R \U$221 ( + .A1(\$signal$62 ), + .A2(\$signal$291 ), + .B(\$signal$292 ), + .Y(\g_new$357 ) + ); + AND2x2_ASAP7_75t_R \U$222 ( + .A(\$signal$66 ), + .B(\$signal$64 ), + .Y(\p_new$355 ) + ); + AO21x1_ASAP7_75t_R \U$223 ( + .A1(\$signal$66 ), + .A2(\$signal$293 ), + .B(\$signal$294 ), + .Y(\g_new$358 ) + ); + AND2x2_ASAP7_75t_R \U$224 ( + .A(\$signal$70 ), + .B(\$signal$68 ), + .Y(\p_new$360 ) + ); + AO21x1_ASAP7_75t_R \U$225 ( + .A1(\$signal$70 ), + .A2(\$signal$295 ), + .B(\$signal$296 ), + .Y(\g_new$361 ) + ); + AND2x2_ASAP7_75t_R \U$226 ( + .A(\$signal$74 ), + .B(\$signal$72 ), + .Y(\p_new$359 ) + ); + AO21x1_ASAP7_75t_R \U$227 ( + .A1(\$signal$74 ), + .A2(\$signal$297 ), + .B(\$signal$298 ), + .Y(\g_new$362 ) + ); + AND2x2_ASAP7_75t_R \U$228 ( + .A(\$signal$78 ), + .B(\$signal$76 ), + .Y(\p_new$364 ) + ); + AO21x1_ASAP7_75t_R \U$229 ( + .A1(\$signal$78 ), + .A2(\$signal$299 ), + .B(\$signal$300 ), + .Y(\g_new$365 ) + ); + INVx1_ASAP7_75t_R \U$23 ( + .A(\sn$150 ), + .Y(\$signal$18 ) + ); + AND2x2_ASAP7_75t_R \U$230 ( + .A(\$signal$82 ), + .B(\$signal$80 ), + .Y(\p_new$363 ) + ); + AO21x1_ASAP7_75t_R \U$231 ( + .A1(\$signal$82 ), + .A2(\$signal$301 ), + .B(\$signal$302 ), + .Y(\g_new$366 ) + ); + AND2x2_ASAP7_75t_R \U$232 ( + .A(\$signal$86 ), + .B(\$signal$84 ), + .Y(\p_new$368 ) + ); + AO21x1_ASAP7_75t_R \U$233 ( + .A1(\$signal$86 ), + .A2(\$signal$303 ), + .B(\$signal$304 ), + .Y(\g_new$369 ) + ); + AND2x2_ASAP7_75t_R \U$234 ( + .A(\$signal$90 ), + .B(\$signal$88 ), + .Y(\p_new$367 ) + ); + AO21x1_ASAP7_75t_R \U$235 ( + .A1(\$signal$90 ), + .A2(\$signal$305 ), + .B(\$signal$306 ), + .Y(\g_new$370 ) + ); + AND2x2_ASAP7_75t_R \U$236 ( + .A(\$signal$94 ), + .B(\$signal$92 ), + .Y(\p_new$372 ) + ); + AO21x1_ASAP7_75t_R \U$237 ( + .A1(\$signal$94 ), + .A2(\$signal$307 ), + .B(\$signal$308 ), + .Y(\g_new$373 ) + ); + AND2x2_ASAP7_75t_R \U$238 ( + .A(\$signal$98 ), + .B(\$signal$96 ), + .Y(\p_new$371 ) + ); + AO21x1_ASAP7_75t_R \U$239 ( + .A1(\$signal$98 ), + .A2(\$signal$309 ), + .B(\$signal$310 ), + .Y(\g_new$374 ) + ); + HAxp5_ASAP7_75t_R \U$24 ( + .A(a[8]), + .B(b[8]), + .CON(\con$151 ), + .SN(\sn$152 ) + ); + AND2x2_ASAP7_75t_R \U$240 ( + .A(\$signal$102 ), + .B(\$signal$100 ), + .Y(\p_new$376 ) + ); + AO21x1_ASAP7_75t_R \U$241 ( + .A1(\$signal$102 ), + .A2(\$signal$311 ), + .B(\$signal$312 ), + .Y(\g_new$377 ) + ); + AND2x2_ASAP7_75t_R \U$242 ( + .A(\$signal$106 ), + .B(\$signal$104 ), + .Y(\p_new$375 ) + ); + AO21x1_ASAP7_75t_R \U$243 ( + .A1(\$signal$106 ), + .A2(\$signal$313 ), + .B(\$signal$314 ), + .Y(\g_new$378 ) + ); + AND2x2_ASAP7_75t_R \U$244 ( + .A(\$signal$110 ), + .B(\$signal$108 ), + .Y(\p_new$380 ) + ); + AO21x1_ASAP7_75t_R \U$245 ( + .A1(\$signal$110 ), + .A2(\$signal$315 ), + .B(\$signal$316 ), + .Y(\g_new$381 ) + ); + AND2x2_ASAP7_75t_R \U$246 ( + .A(\$signal$114 ), + .B(\$signal$112 ), + .Y(\p_new$379 ) + ); + AO21x1_ASAP7_75t_R \U$247 ( + .A1(\$signal$114 ), + .A2(\$signal$317 ), + .B(\$signal$318 ), + .Y(\g_new$382 ) + ); + AND2x2_ASAP7_75t_R \U$248 ( + .A(\$signal$118 ), + .B(\$signal$116 ), + .Y(\p_new$384 ) + ); + AO21x1_ASAP7_75t_R \U$249 ( + .A1(\$signal$118 ), + .A2(\$signal$319 ), + .B(\$signal$320 ), + .Y(\g_new$385 ) + ); + INVx1_ASAP7_75t_R \U$25 ( + .A(\con$151 ), + .Y(\$signal$271 ) + ); + AND2x2_ASAP7_75t_R \U$250 ( + .A(\$signal$122 ), + .B(\$signal$120 ), + .Y(\p_new$383 ) + ); + AO21x1_ASAP7_75t_R \U$251 ( + .A1(\$signal$122 ), + .A2(\$signal$321 ), + .B(\$signal$322 ), + .Y(\g_new$386 ) + ); + AND2x2_ASAP7_75t_R \U$252 ( + .A(\$signal$126 ), + .B(\$signal$124 ), + .Y(\p_new$388 ) + ); + AO21x1_ASAP7_75t_R \U$253 ( + .A1(\$signal$126 ), + .A2(\$signal$323 ), + .B(\$signal$324 ), + .Y(\g_new$389 ) + ); + AND2x2_ASAP7_75t_R \U$254 ( + .A(\$signal$130 ), + .B(\$signal$128 ), + .Y(\p_new$387 ) + ); + AO21x1_ASAP7_75t_R \U$255 ( + .A1(\$signal$130 ), + .A2(\$signal$325 ), + .B(\$signal$326 ), + .Y(\g_new$390 ) + ); + AND2x2_ASAP7_75t_R \U$256 ( + .A(p_new), + .B(\p_new$328 ), + .Y(\p_new$392 ) + ); + AO21x1_ASAP7_75t_R \U$257 ( + .A1(p_new), + .A2(g_new), + .B(\g_new$330 ), + .Y(\g_new$393 ) + ); + AND2x2_ASAP7_75t_R \U$258 ( + .A(\p_new$331 ), + .B(\p_new$332 ), + .Y(\p_new$391 ) + ); + AO21x1_ASAP7_75t_R \U$259 ( + .A1(\p_new$331 ), + .A2(\g_new$333 ), + .B(\g_new$334 ), + .Y(\g_new$394 ) + ); + INVx1_ASAP7_75t_R \U$26 ( + .A(\sn$152 ), + .Y(\$signal$20 ) + ); + AND2x2_ASAP7_75t_R \U$260 ( + .A(\p_new$335 ), + .B(\p_new$336 ), + .Y(\p_new$396 ) + ); + AO21x1_ASAP7_75t_R \U$261 ( + .A1(\p_new$335 ), + .A2(\g_new$337 ), + .B(\g_new$338 ), + .Y(\g_new$397 ) + ); + AND2x2_ASAP7_75t_R \U$262 ( + .A(\p_new$339 ), + .B(\p_new$340 ), + .Y(\p_new$395 ) + ); + AO21x1_ASAP7_75t_R \U$263 ( + .A1(\p_new$339 ), + .A2(\g_new$341 ), + .B(\g_new$342 ), + .Y(\g_new$398 ) + ); + AND2x2_ASAP7_75t_R \U$264 ( + .A(\p_new$343 ), + .B(\p_new$344 ), + .Y(\p_new$400 ) + ); + AO21x1_ASAP7_75t_R \U$265 ( + .A1(\p_new$343 ), + .A2(\g_new$345 ), + .B(\g_new$346 ), + .Y(\g_new$401 ) + ); + AND2x2_ASAP7_75t_R \U$266 ( + .A(\p_new$347 ), + .B(\p_new$348 ), + .Y(\p_new$399 ) + ); + AO21x1_ASAP7_75t_R \U$267 ( + .A1(\p_new$347 ), + .A2(\g_new$349 ), + .B(\g_new$350 ), + .Y(\g_new$402 ) + ); + AND2x2_ASAP7_75t_R \U$268 ( + .A(\p_new$351 ), + .B(\p_new$352 ), + .Y(\p_new$404 ) + ); + AO21x1_ASAP7_75t_R \U$269 ( + .A1(\p_new$351 ), + .A2(\g_new$353 ), + .B(\g_new$354 ), + .Y(\g_new$405 ) + ); + HAxp5_ASAP7_75t_R \U$27 ( + .A(a[9]), + .B(b[9]), + .CON(\con$153 ), + .SN(\sn$154 ) + ); + AND2x2_ASAP7_75t_R \U$270 ( + .A(\p_new$355 ), + .B(\p_new$356 ), + .Y(\p_new$403 ) + ); + AO21x1_ASAP7_75t_R \U$271 ( + .A1(\p_new$355 ), + .A2(\g_new$357 ), + .B(\g_new$358 ), + .Y(\g_new$406 ) + ); + AND2x2_ASAP7_75t_R \U$272 ( + .A(\p_new$359 ), + .B(\p_new$360 ), + .Y(\p_new$408 ) + ); + AO21x1_ASAP7_75t_R \U$273 ( + .A1(\p_new$359 ), + .A2(\g_new$361 ), + .B(\g_new$362 ), + .Y(\g_new$409 ) + ); + AND2x2_ASAP7_75t_R \U$274 ( + .A(\p_new$363 ), + .B(\p_new$364 ), + .Y(\p_new$407 ) + ); + AO21x1_ASAP7_75t_R \U$275 ( + .A1(\p_new$363 ), + .A2(\g_new$365 ), + .B(\g_new$366 ), + .Y(\g_new$410 ) + ); + AND2x2_ASAP7_75t_R \U$276 ( + .A(\p_new$367 ), + .B(\p_new$368 ), + .Y(\p_new$412 ) + ); + AO21x1_ASAP7_75t_R \U$277 ( + .A1(\p_new$367 ), + .A2(\g_new$369 ), + .B(\g_new$370 ), + .Y(\g_new$413 ) + ); + AND2x2_ASAP7_75t_R \U$278 ( + .A(\p_new$371 ), + .B(\p_new$372 ), + .Y(\p_new$411 ) + ); + AO21x1_ASAP7_75t_R \U$279 ( + .A1(\p_new$371 ), + .A2(\g_new$373 ), + .B(\g_new$374 ), + .Y(\g_new$414 ) + ); + INVx1_ASAP7_75t_R \U$28 ( + .A(\con$153 ), + .Y(\$signal$272 ) + ); + AND2x2_ASAP7_75t_R \U$280 ( + .A(\p_new$375 ), + .B(\p_new$376 ), + .Y(\p_new$416 ) + ); + AO21x1_ASAP7_75t_R \U$281 ( + .A1(\p_new$375 ), + .A2(\g_new$377 ), + .B(\g_new$378 ), + .Y(\g_new$417 ) + ); + AND2x2_ASAP7_75t_R \U$282 ( + .A(\p_new$379 ), + .B(\p_new$380 ), + .Y(\p_new$415 ) + ); + AO21x1_ASAP7_75t_R \U$283 ( + .A1(\p_new$379 ), + .A2(\g_new$381 ), + .B(\g_new$382 ), + .Y(\g_new$418 ) + ); + AND2x2_ASAP7_75t_R \U$284 ( + .A(\p_new$383 ), + .B(\p_new$384 ), + .Y(\p_new$420 ) + ); + AO21x1_ASAP7_75t_R \U$285 ( + .A1(\p_new$383 ), + .A2(\g_new$385 ), + .B(\g_new$386 ), + .Y(\g_new$421 ) + ); + AND2x2_ASAP7_75t_R \U$286 ( + .A(\p_new$387 ), + .B(\p_new$388 ), + .Y(\p_new$419 ) + ); + AO21x1_ASAP7_75t_R \U$287 ( + .A1(\p_new$387 ), + .A2(\g_new$389 ), + .B(\g_new$390 ), + .Y(\g_new$422 ) + ); + AND2x2_ASAP7_75t_R \U$288 ( + .A(\p_new$391 ), + .B(\p_new$392 ), + .Y(\p_new$424 ) + ); + AO21x1_ASAP7_75t_R \U$289 ( + .A1(\p_new$391 ), + .A2(\g_new$393 ), + .B(\g_new$394 ), + .Y(\g_new$425 ) + ); + INVx1_ASAP7_75t_R \U$29 ( + .A(\sn$154 ), + .Y(\$signal$22 ) + ); + AND2x2_ASAP7_75t_R \U$290 ( + .A(\p_new$395 ), + .B(\p_new$396 ), + .Y(\p_new$423 ) + ); + AO21x1_ASAP7_75t_R \U$291 ( + .A1(\p_new$395 ), + .A2(\g_new$397 ), + .B(\g_new$398 ), + .Y(\g_new$426 ) + ); + AND2x2_ASAP7_75t_R \U$292 ( + .A(\p_new$399 ), + .B(\p_new$400 ), + .Y(\p_new$428 ) + ); + AO21x1_ASAP7_75t_R \U$293 ( + .A1(\p_new$399 ), + .A2(\g_new$401 ), + .B(\g_new$402 ), + .Y(\g_new$429 ) + ); + AND2x2_ASAP7_75t_R \U$294 ( + .A(\p_new$403 ), + .B(\p_new$404 ), + .Y(\p_new$427 ) + ); + AO21x1_ASAP7_75t_R \U$295 ( + .A1(\p_new$403 ), + .A2(\g_new$405 ), + .B(\g_new$406 ), + .Y(\g_new$430 ) + ); + AND2x2_ASAP7_75t_R \U$296 ( + .A(\p_new$407 ), + .B(\p_new$408 ), + .Y(\p_new$432 ) + ); + AO21x1_ASAP7_75t_R \U$297 ( + .A1(\p_new$407 ), + .A2(\g_new$409 ), + .B(\g_new$410 ), + .Y(\g_new$433 ) + ); + AND2x2_ASAP7_75t_R \U$298 ( + .A(\p_new$411 ), + .B(\p_new$412 ), + .Y(\p_new$431 ) + ); + AO21x1_ASAP7_75t_R \U$299 ( + .A1(\p_new$411 ), + .A2(\g_new$413 ), + .B(\g_new$414 ), + .Y(\g_new$434 ) + ); + HAxp5_ASAP7_75t_R \U$3 ( + .A(a[1]), + .B(b[1]), + .CON(\con$137 ), + .SN(\sn$138 ) + ); + HAxp5_ASAP7_75t_R \U$30 ( + .A(a[10]), + .B(b[10]), + .CON(\con$155 ), + .SN(\sn$156 ) + ); + AND2x2_ASAP7_75t_R \U$300 ( + .A(\p_new$415 ), + .B(\p_new$416 ), + .Y(\p_new$436 ) + ); + AO21x1_ASAP7_75t_R \U$301 ( + .A1(\p_new$415 ), + .A2(\g_new$417 ), + .B(\g_new$418 ), + .Y(\g_new$437 ) + ); + AND2x2_ASAP7_75t_R \U$302 ( + .A(\p_new$419 ), + .B(\p_new$420 ), + .Y(\p_new$435 ) + ); + AO21x1_ASAP7_75t_R \U$303 ( + .A1(\p_new$419 ), + .A2(\g_new$421 ), + .B(\g_new$422 ), + .Y(\g_new$438 ) + ); + AND2x2_ASAP7_75t_R \U$304 ( + .A(\p_new$423 ), + .B(\p_new$424 ), + .Y(\p_new$440 ) + ); + AO21x1_ASAP7_75t_R \U$305 ( + .A1(\p_new$423 ), + .A2(\g_new$425 ), + .B(\g_new$426 ), + .Y(\g_new$441 ) + ); + AND2x2_ASAP7_75t_R \U$306 ( + .A(\p_new$427 ), + .B(\p_new$428 ), + .Y(\p_new$439 ) + ); + AO21x1_ASAP7_75t_R \U$307 ( + .A1(\p_new$427 ), + .A2(\g_new$429 ), + .B(\g_new$430 ), + .Y(\g_new$442 ) + ); + AND2x2_ASAP7_75t_R \U$308 ( + .A(\p_new$431 ), + .B(\p_new$432 ), + .Y(\p_new$444 ) + ); + AO21x1_ASAP7_75t_R \U$309 ( + .A1(\p_new$431 ), + .A2(\g_new$433 ), + .B(\g_new$434 ), + .Y(\g_new$445 ) + ); + INVx1_ASAP7_75t_R \U$31 ( + .A(\con$155 ), + .Y(\$signal$273 ) + ); + AND2x2_ASAP7_75t_R \U$310 ( + .A(\p_new$435 ), + .B(\p_new$436 ), + .Y(\p_new$443 ) + ); + AO21x1_ASAP7_75t_R \U$311 ( + .A1(\p_new$435 ), + .A2(\g_new$437 ), + .B(\g_new$438 ), + .Y(\g_new$446 ) + ); + AND2x2_ASAP7_75t_R \U$312 ( + .A(\p_new$439 ), + .B(\p_new$440 ), + .Y(\p_new$448 ) + ); + AO21x1_ASAP7_75t_R \U$313 ( + .A1(\p_new$439 ), + .A2(\g_new$441 ), + .B(\g_new$442 ), + .Y(\g_new$449 ) + ); + AND2x2_ASAP7_75t_R \U$314 ( + .A(\p_new$443 ), + .B(\p_new$444 ), + .Y(\p_new$447 ) + ); + AO21x1_ASAP7_75t_R \U$315 ( + .A1(\p_new$443 ), + .A2(\g_new$445 ), + .B(\g_new$446 ), + .Y(\g_new$450 ) + ); + AND2x2_ASAP7_75t_R \U$316 ( + .A(\p_new$447 ), + .B(\p_new$448 ), + .Y(\$1 ) + ); + AO21x1_ASAP7_75t_R \U$317 ( + .A1(\p_new$447 ), + .A2(\g_new$449 ), + .B(\g_new$450 ), + .Y(\$2 ) + ); + AO21x1_ASAP7_75t_R \U$318 ( + .A1(\p_new$444 ), + .A2(\g_new$449 ), + .B(\g_new$445 ), + .Y(\g_new$451 ) + ); + AO21x1_ASAP7_75t_R \U$319 ( + .A1(\p_new$428 ), + .A2(\g_new$441 ), + .B(\g_new$429 ), + .Y(\g_new$452 ) + ); + INVx1_ASAP7_75t_R \U$32 ( + .A(\sn$156 ), + .Y(\$signal$24 ) + ); + AO21x1_ASAP7_75t_R \U$320 ( + .A1(\p_new$432 ), + .A2(\g_new$449 ), + .B(\g_new$433 ), + .Y(\g_new$453 ) + ); + AO21x1_ASAP7_75t_R \U$321 ( + .A1(\p_new$436 ), + .A2(\g_new$451 ), + .B(\g_new$437 ), + .Y(\g_new$454 ) + ); + AO21x1_ASAP7_75t_R \U$322 ( + .A1(\p_new$396 ), + .A2(\g_new$425 ), + .B(\g_new$397 ), + .Y(\g_new$455 ) + ); + AO21x1_ASAP7_75t_R \U$323 ( + .A1(\p_new$400 ), + .A2(\g_new$441 ), + .B(\g_new$401 ), + .Y(\g_new$456 ) + ); + AO21x1_ASAP7_75t_R \U$324 ( + .A1(\p_new$404 ), + .A2(\g_new$452 ), + .B(\g_new$405 ), + .Y(\g_new$457 ) + ); + AO21x1_ASAP7_75t_R \U$325 ( + .A1(\p_new$408 ), + .A2(\g_new$449 ), + .B(\g_new$409 ), + .Y(\g_new$458 ) + ); + AO21x1_ASAP7_75t_R \U$326 ( + .A1(\p_new$412 ), + .A2(\g_new$453 ), + .B(\g_new$413 ), + .Y(\g_new$459 ) + ); + AO21x1_ASAP7_75t_R \U$327 ( + .A1(\p_new$416 ), + .A2(\g_new$451 ), + .B(\g_new$417 ), + .Y(\g_new$460 ) + ); + AO21x1_ASAP7_75t_R \U$328 ( + .A1(\p_new$420 ), + .A2(\g_new$454 ), + .B(\g_new$421 ), + .Y(\g_new$461 ) + ); + AO21x1_ASAP7_75t_R \U$329 ( + .A1(\p_new$332 ), + .A2(\g_new$393 ), + .B(\g_new$333 ), + .Y(\g_new$462 ) + ); + HAxp5_ASAP7_75t_R \U$33 ( + .A(a[11]), + .B(b[11]), + .CON(\con$157 ), + .SN(\sn$158 ) + ); + AO21x1_ASAP7_75t_R \U$330 ( + .A1(\p_new$336 ), + .A2(\g_new$425 ), + .B(\g_new$337 ), + .Y(\g_new$463 ) + ); + AO21x1_ASAP7_75t_R \U$331 ( + .A1(\p_new$340 ), + .A2(\g_new$455 ), + .B(\g_new$341 ), + .Y(\g_new$464 ) + ); + AO21x1_ASAP7_75t_R \U$332 ( + .A1(\p_new$344 ), + .A2(\g_new$441 ), + .B(\g_new$345 ), + .Y(\g_new$465 ) + ); + AO21x1_ASAP7_75t_R \U$333 ( + .A1(\p_new$348 ), + .A2(\g_new$456 ), + .B(\g_new$349 ), + .Y(\g_new$466 ) + ); + AO21x1_ASAP7_75t_R \U$334 ( + .A1(\p_new$352 ), + .A2(\g_new$452 ), + .B(\g_new$353 ), + .Y(\g_new$467 ) + ); + AO21x1_ASAP7_75t_R \U$335 ( + .A1(\p_new$356 ), + .A2(\g_new$457 ), + .B(\g_new$357 ), + .Y(\g_new$468 ) + ); + AO21x1_ASAP7_75t_R \U$336 ( + .A1(\p_new$360 ), + .A2(\g_new$449 ), + .B(\g_new$361 ), + .Y(\g_new$469 ) + ); + AO21x1_ASAP7_75t_R \U$337 ( + .A1(\p_new$364 ), + .A2(\g_new$458 ), + .B(\g_new$365 ), + .Y(\g_new$470 ) + ); + AO21x1_ASAP7_75t_R \U$338 ( + .A1(\p_new$368 ), + .A2(\g_new$453 ), + .B(\g_new$369 ), + .Y(\g_new$471 ) + ); + AO21x1_ASAP7_75t_R \U$339 ( + .A1(\p_new$372 ), + .A2(\g_new$459 ), + .B(\g_new$373 ), + .Y(\g_new$472 ) + ); + INVx1_ASAP7_75t_R \U$34 ( + .A(\con$157 ), + .Y(\$signal$274 ) + ); + AO21x1_ASAP7_75t_R \U$340 ( + .A1(\p_new$376 ), + .A2(\g_new$451 ), + .B(\g_new$377 ), + .Y(\g_new$473 ) + ); + AO21x1_ASAP7_75t_R \U$341 ( + .A1(\p_new$380 ), + .A2(\g_new$460 ), + .B(\g_new$381 ), + .Y(\g_new$474 ) + ); + AO21x1_ASAP7_75t_R \U$342 ( + .A1(\p_new$384 ), + .A2(\g_new$454 ), + .B(\g_new$385 ), + .Y(\g_new$475 ) + ); + AO21x1_ASAP7_75t_R \U$343 ( + .A1(\p_new$388 ), + .A2(\g_new$461 ), + .B(\g_new$389 ), + .Y(\g_new$476 ) + ); + AO21x1_ASAP7_75t_R \U$344 ( + .A1(\$signal$8 ), + .A2(g_new), + .B(\$signal$265 ), + .Y(\g_new$477 ) + ); + AO21x1_ASAP7_75t_R \U$345 ( + .A1(\$signal$12 ), + .A2(\g_new$393 ), + .B(\$signal$267 ), + .Y(\g_new$478 ) + ); + AO21x1_ASAP7_75t_R \U$346 ( + .A1(\$signal$16 ), + .A2(\g_new$462 ), + .B(\$signal$269 ), + .Y(\g_new$479 ) + ); + AO21x1_ASAP7_75t_R \U$347 ( + .A1(\$signal$20 ), + .A2(\g_new$425 ), + .B(\$signal$271 ), + .Y(\g_new$480 ) + ); + AO21x1_ASAP7_75t_R \U$348 ( + .A1(\$signal$24 ), + .A2(\g_new$463 ), + .B(\$signal$273 ), + .Y(\g_new$481 ) + ); + AO21x1_ASAP7_75t_R \U$349 ( + .A1(\$signal$28 ), + .A2(\g_new$455 ), + .B(\$signal$275 ), + .Y(\g_new$482 ) + ); + INVx1_ASAP7_75t_R \U$35 ( + .A(\sn$158 ), + .Y(\$signal$26 ) + ); + AO21x1_ASAP7_75t_R \U$350 ( + .A1(\$signal$32 ), + .A2(\g_new$464 ), + .B(\$signal$277 ), + .Y(\g_new$483 ) + ); + AO21x1_ASAP7_75t_R \U$351 ( + .A1(\$signal$36 ), + .A2(\g_new$441 ), + .B(\$signal$279 ), + .Y(\g_new$484 ) + ); + AO21x1_ASAP7_75t_R \U$352 ( + .A1(\$signal$40 ), + .A2(\g_new$465 ), + .B(\$signal$281 ), + .Y(\g_new$485 ) + ); + AO21x1_ASAP7_75t_R \U$353 ( + .A1(\$signal$44 ), + .A2(\g_new$456 ), + .B(\$signal$283 ), + .Y(\g_new$486 ) + ); + AO21x1_ASAP7_75t_R \U$354 ( + .A1(\$signal$48 ), + .A2(\g_new$466 ), + .B(\$signal$285 ), + .Y(\g_new$487 ) + ); + AO21x1_ASAP7_75t_R \U$355 ( + .A1(\$signal$52 ), + .A2(\g_new$452 ), + .B(\$signal$287 ), + .Y(\g_new$488 ) + ); + AO21x1_ASAP7_75t_R \U$356 ( + .A1(\$signal$56 ), + .A2(\g_new$467 ), + .B(\$signal$289 ), + .Y(\g_new$489 ) + ); + AO21x1_ASAP7_75t_R \U$357 ( + .A1(\$signal$60 ), + .A2(\g_new$457 ), + .B(\$signal$291 ), + .Y(\g_new$490 ) + ); + AO21x1_ASAP7_75t_R \U$358 ( + .A1(\$signal$64 ), + .A2(\g_new$468 ), + .B(\$signal$293 ), + .Y(\g_new$491 ) + ); + AO21x1_ASAP7_75t_R \U$359 ( + .A1(\$signal$68 ), + .A2(\g_new$449 ), + .B(\$signal$295 ), + .Y(\g_new$492 ) + ); + HAxp5_ASAP7_75t_R \U$36 ( + .A(a[12]), + .B(b[12]), + .CON(\con$159 ), + .SN(\sn$160 ) + ); + AO21x1_ASAP7_75t_R \U$360 ( + .A1(\$signal$72 ), + .A2(\g_new$469 ), + .B(\$signal$297 ), + .Y(\g_new$493 ) + ); + AO21x1_ASAP7_75t_R \U$361 ( + .A1(\$signal$76 ), + .A2(\g_new$458 ), + .B(\$signal$299 ), + .Y(\g_new$494 ) + ); + AO21x1_ASAP7_75t_R \U$362 ( + .A1(\$signal$80 ), + .A2(\g_new$470 ), + .B(\$signal$301 ), + .Y(\g_new$495 ) + ); + AO21x1_ASAP7_75t_R \U$363 ( + .A1(\$signal$84 ), + .A2(\g_new$453 ), + .B(\$signal$303 ), + .Y(\g_new$496 ) + ); + AO21x1_ASAP7_75t_R \U$364 ( + .A1(\$signal$88 ), + .A2(\g_new$471 ), + .B(\$signal$305 ), + .Y(\g_new$497 ) + ); + AO21x1_ASAP7_75t_R \U$365 ( + .A1(\$signal$92 ), + .A2(\g_new$459 ), + .B(\$signal$307 ), + .Y(\g_new$498 ) + ); + AO21x1_ASAP7_75t_R \U$366 ( + .A1(\$signal$96 ), + .A2(\g_new$472 ), + .B(\$signal$309 ), + .Y(\g_new$499 ) + ); + AO21x1_ASAP7_75t_R \U$367 ( + .A1(\$signal$100 ), + .A2(\g_new$451 ), + .B(\$signal$311 ), + .Y(\g_new$500 ) + ); + AO21x1_ASAP7_75t_R \U$368 ( + .A1(\$signal$104 ), + .A2(\g_new$473 ), + .B(\$signal$313 ), + .Y(\g_new$501 ) + ); + AO21x1_ASAP7_75t_R \U$369 ( + .A1(\$signal$108 ), + .A2(\g_new$460 ), + .B(\$signal$315 ), + .Y(\g_new$502 ) + ); + INVx1_ASAP7_75t_R \U$37 ( + .A(\con$159 ), + .Y(\$signal$275 ) + ); + AO21x1_ASAP7_75t_R \U$370 ( + .A1(\$signal$112 ), + .A2(\g_new$474 ), + .B(\$signal$317 ), + .Y(\g_new$503 ) + ); + AO21x1_ASAP7_75t_R \U$371 ( + .A1(\$signal$116 ), + .A2(\g_new$454 ), + .B(\$signal$319 ), + .Y(\g_new$504 ) + ); + AO21x1_ASAP7_75t_R \U$372 ( + .A1(\$signal$120 ), + .A2(\g_new$475 ), + .B(\$signal$321 ), + .Y(\g_new$505 ) + ); + AO21x1_ASAP7_75t_R \U$373 ( + .A1(\$signal$124 ), + .A2(\g_new$461 ), + .B(\$signal$323 ), + .Y(\g_new$506 ) + ); + AO21x1_ASAP7_75t_R \U$374 ( + .A1(\$signal$128 ), + .A2(\g_new$476 ), + .B(\$signal$325 ), + .Y(\g_new$507 ) + ); + XOR2x1_ASAP7_75t_R \U$375 ( + .A(\$signal ), + .B(1'h0), + .Y(\$3 ) + ); + XOR2x1_ASAP7_75t_R \U$376 ( + .A(\$signal$6 ), + .B(\$signal$263 ), + .Y(\$4 ) + ); + XOR2x1_ASAP7_75t_R \U$377 ( + .A(\$signal$8 ), + .B(g_new), + .Y(\$5 ) + ); + XOR2x1_ASAP7_75t_R \U$378 ( + .A(\$signal$10 ), + .B(\g_new$477 ), + .Y(\$6 ) + ); + XOR2x1_ASAP7_75t_R \U$379 ( + .A(\$signal$12 ), + .B(\g_new$393 ), + .Y(\$7 ) + ); + INVx1_ASAP7_75t_R \U$38 ( + .A(\sn$160 ), + .Y(\$signal$28 ) + ); + XOR2x1_ASAP7_75t_R \U$380 ( + .A(\$signal$14 ), + .B(\g_new$478 ), + .Y(\$8 ) + ); + XOR2x1_ASAP7_75t_R \U$381 ( + .A(\$signal$16 ), + .B(\g_new$462 ), + .Y(\$9 ) + ); + XOR2x1_ASAP7_75t_R \U$382 ( + .A(\$signal$18 ), + .B(\g_new$479 ), + .Y(\$10 ) + ); + XOR2x1_ASAP7_75t_R \U$383 ( + .A(\$signal$20 ), + .B(\g_new$425 ), + .Y(\$11 ) + ); + XOR2x1_ASAP7_75t_R \U$384 ( + .A(\$signal$22 ), + .B(\g_new$480 ), + .Y(\$12 ) + ); + XOR2x1_ASAP7_75t_R \U$385 ( + .A(\$signal$24 ), + .B(\g_new$463 ), + .Y(\$13 ) + ); + XOR2x1_ASAP7_75t_R \U$386 ( + .A(\$signal$26 ), + .B(\g_new$481 ), + .Y(\$14 ) + ); + XOR2x1_ASAP7_75t_R \U$387 ( + .A(\$signal$28 ), + .B(\g_new$455 ), + .Y(\$15 ) + ); + XOR2x1_ASAP7_75t_R \U$388 ( + .A(\$signal$30 ), + .B(\g_new$482 ), + .Y(\$16 ) + ); + XOR2x1_ASAP7_75t_R \U$389 ( + .A(\$signal$32 ), + .B(\g_new$464 ), + .Y(\$17 ) + ); + HAxp5_ASAP7_75t_R \U$39 ( + .A(a[13]), + .B(b[13]), + .CON(\con$161 ), + .SN(\sn$162 ) + ); + XOR2x1_ASAP7_75t_R \U$390 ( + .A(\$signal$34 ), + .B(\g_new$483 ), + .Y(\$18 ) + ); + XOR2x1_ASAP7_75t_R \U$391 ( + .A(\$signal$36 ), + .B(\g_new$441 ), + .Y(\$19 ) + ); + XOR2x1_ASAP7_75t_R \U$392 ( + .A(\$signal$38 ), + .B(\g_new$484 ), + .Y(\$20 ) + ); + XOR2x1_ASAP7_75t_R \U$393 ( + .A(\$signal$40 ), + .B(\g_new$465 ), + .Y(\$21 ) + ); + XOR2x1_ASAP7_75t_R \U$394 ( + .A(\$signal$42 ), + .B(\g_new$485 ), + .Y(\$22 ) + ); + XOR2x1_ASAP7_75t_R \U$395 ( + .A(\$signal$44 ), + .B(\g_new$456 ), + .Y(\$23 ) + ); + XOR2x1_ASAP7_75t_R \U$396 ( + .A(\$signal$46 ), + .B(\g_new$486 ), + .Y(\$24 ) + ); + XOR2x1_ASAP7_75t_R \U$397 ( + .A(\$signal$48 ), + .B(\g_new$466 ), + .Y(\$25 ) + ); + XOR2x1_ASAP7_75t_R \U$398 ( + .A(\$signal$50 ), + .B(\g_new$487 ), + .Y(\$26 ) + ); + XOR2x1_ASAP7_75t_R \U$399 ( + .A(\$signal$52 ), + .B(\g_new$452 ), + .Y(\$27 ) + ); + INVx1_ASAP7_75t_R \U$4 ( + .A(\con$137 ), + .Y(\$signal$264 ) + ); + INVx1_ASAP7_75t_R \U$40 ( + .A(\con$161 ), + .Y(\$signal$276 ) + ); + XOR2x1_ASAP7_75t_R \U$400 ( + .A(\$signal$54 ), + .B(\g_new$488 ), + .Y(\$28 ) + ); + XOR2x1_ASAP7_75t_R \U$401 ( + .A(\$signal$56 ), + .B(\g_new$467 ), + .Y(\$29 ) + ); + XOR2x1_ASAP7_75t_R \U$402 ( + .A(\$signal$58 ), + .B(\g_new$489 ), + .Y(\$30 ) + ); + XOR2x1_ASAP7_75t_R \U$403 ( + .A(\$signal$60 ), + .B(\g_new$457 ), + .Y(\$31 ) + ); + XOR2x1_ASAP7_75t_R \U$404 ( + .A(\$signal$62 ), + .B(\g_new$490 ), + .Y(\$32 ) + ); + XOR2x1_ASAP7_75t_R \U$405 ( + .A(\$signal$64 ), + .B(\g_new$468 ), + .Y(\$33 ) + ); + XOR2x1_ASAP7_75t_R \U$406 ( + .A(\$signal$66 ), + .B(\g_new$491 ), + .Y(\$34 ) + ); + XOR2x1_ASAP7_75t_R \U$407 ( + .A(\$signal$68 ), + .B(\g_new$449 ), + .Y(\$35 ) + ); + XOR2x1_ASAP7_75t_R \U$408 ( + .A(\$signal$70 ), + .B(\g_new$492 ), + .Y(\$36 ) + ); + XOR2x1_ASAP7_75t_R \U$409 ( + .A(\$signal$72 ), + .B(\g_new$469 ), + .Y(\$37 ) + ); + INVx1_ASAP7_75t_R \U$41 ( + .A(\sn$162 ), + .Y(\$signal$30 ) + ); + XOR2x1_ASAP7_75t_R \U$410 ( + .A(\$signal$74 ), + .B(\g_new$493 ), + .Y(\$38 ) + ); + XOR2x1_ASAP7_75t_R \U$411 ( + .A(\$signal$76 ), + .B(\g_new$458 ), + .Y(\$39 ) + ); + XOR2x1_ASAP7_75t_R \U$412 ( + .A(\$signal$78 ), + .B(\g_new$494 ), + .Y(\$40 ) + ); + XOR2x1_ASAP7_75t_R \U$413 ( + .A(\$signal$80 ), + .B(\g_new$470 ), + .Y(\$41 ) + ); + XOR2x1_ASAP7_75t_R \U$414 ( + .A(\$signal$82 ), + .B(\g_new$495 ), + .Y(\$42 ) + ); + XOR2x1_ASAP7_75t_R \U$415 ( + .A(\$signal$84 ), + .B(\g_new$453 ), + .Y(\$43 ) + ); + XOR2x1_ASAP7_75t_R \U$416 ( + .A(\$signal$86 ), + .B(\g_new$496 ), + .Y(\$44 ) + ); + XOR2x1_ASAP7_75t_R \U$417 ( + .A(\$signal$88 ), + .B(\g_new$471 ), + .Y(\$45 ) + ); + XOR2x1_ASAP7_75t_R \U$418 ( + .A(\$signal$90 ), + .B(\g_new$497 ), + .Y(\$46 ) + ); + XOR2x1_ASAP7_75t_R \U$419 ( + .A(\$signal$92 ), + .B(\g_new$459 ), + .Y(\$47 ) + ); + HAxp5_ASAP7_75t_R \U$42 ( + .A(a[14]), + .B(b[14]), + .CON(\con$163 ), + .SN(\sn$164 ) + ); + XOR2x1_ASAP7_75t_R \U$420 ( + .A(\$signal$94 ), + .B(\g_new$498 ), + .Y(\$48 ) + ); + XOR2x1_ASAP7_75t_R \U$421 ( + .A(\$signal$96 ), + .B(\g_new$472 ), + .Y(\$49 ) + ); + XOR2x1_ASAP7_75t_R \U$422 ( + .A(\$signal$98 ), + .B(\g_new$499 ), + .Y(\$50 ) + ); + XOR2x1_ASAP7_75t_R \U$423 ( + .A(\$signal$100 ), + .B(\g_new$451 ), + .Y(\$51 ) + ); + XOR2x1_ASAP7_75t_R \U$424 ( + .A(\$signal$102 ), + .B(\g_new$500 ), + .Y(\$52 ) + ); + XOR2x1_ASAP7_75t_R \U$425 ( + .A(\$signal$104 ), + .B(\g_new$473 ), + .Y(\$53 ) + ); + XOR2x1_ASAP7_75t_R \U$426 ( + .A(\$signal$106 ), + .B(\g_new$501 ), + .Y(\$54 ) + ); + XOR2x1_ASAP7_75t_R \U$427 ( + .A(\$signal$108 ), + .B(\g_new$460 ), + .Y(\$55 ) + ); + XOR2x1_ASAP7_75t_R \U$428 ( + .A(\$signal$110 ), + .B(\g_new$502 ), + .Y(\$56 ) + ); + XOR2x1_ASAP7_75t_R \U$429 ( + .A(\$signal$112 ), + .B(\g_new$474 ), + .Y(\$57 ) + ); + INVx1_ASAP7_75t_R \U$43 ( + .A(\con$163 ), + .Y(\$signal$277 ) + ); + XOR2x1_ASAP7_75t_R \U$430 ( + .A(\$signal$114 ), + .B(\g_new$503 ), + .Y(\$58 ) + ); + XOR2x1_ASAP7_75t_R \U$431 ( + .A(\$signal$116 ), + .B(\g_new$454 ), + .Y(\$59 ) + ); + XOR2x1_ASAP7_75t_R \U$432 ( + .A(\$signal$118 ), + .B(\g_new$504 ), + .Y(\$60 ) + ); + XOR2x1_ASAP7_75t_R \U$433 ( + .A(\$signal$120 ), + .B(\g_new$475 ), + .Y(\$61 ) + ); + XOR2x1_ASAP7_75t_R \U$434 ( + .A(\$signal$122 ), + .B(\g_new$505 ), + .Y(\$62 ) + ); + XOR2x1_ASAP7_75t_R \U$435 ( + .A(\$signal$124 ), + .B(\g_new$461 ), + .Y(\$63 ) + ); + XOR2x1_ASAP7_75t_R \U$436 ( + .A(\$signal$126 ), + .B(\g_new$506 ), + .Y(\$64 ) + ); + XOR2x1_ASAP7_75t_R \U$437 ( + .A(\$signal$128 ), + .B(\g_new$476 ), + .Y(\$65 ) + ); + XOR2x1_ASAP7_75t_R \U$438 ( + .A(\$signal$130 ), + .B(\g_new$507 ), + .Y(\$66 ) + ); + INVx1_ASAP7_75t_R \U$44 ( + .A(\sn$164 ), + .Y(\$signal$32 ) + ); + HAxp5_ASAP7_75t_R \U$45 ( + .A(a[15]), + .B(b[15]), + .CON(\con$165 ), + .SN(\sn$166 ) + ); + INVx1_ASAP7_75t_R \U$46 ( + .A(\con$165 ), + .Y(\$signal$278 ) + ); + INVx1_ASAP7_75t_R \U$47 ( + .A(\sn$166 ), + .Y(\$signal$34 ) + ); + HAxp5_ASAP7_75t_R \U$48 ( + .A(a[16]), + .B(b[16]), + .CON(\con$167 ), + .SN(\sn$168 ) + ); + INVx1_ASAP7_75t_R \U$49 ( + .A(\con$167 ), + .Y(\$signal$279 ) + ); + INVx1_ASAP7_75t_R \U$5 ( + .A(\sn$138 ), + .Y(\$signal$6 ) + ); + INVx1_ASAP7_75t_R \U$50 ( + .A(\sn$168 ), + .Y(\$signal$36 ) + ); + HAxp5_ASAP7_75t_R \U$51 ( + .A(a[17]), + .B(b[17]), + .CON(\con$169 ), + .SN(\sn$170 ) + ); + INVx1_ASAP7_75t_R \U$52 ( + .A(\con$169 ), + .Y(\$signal$280 ) + ); + INVx1_ASAP7_75t_R \U$53 ( + .A(\sn$170 ), + .Y(\$signal$38 ) + ); + HAxp5_ASAP7_75t_R \U$54 ( + .A(a[18]), + .B(b[18]), + .CON(\con$171 ), + .SN(\sn$172 ) + ); + INVx1_ASAP7_75t_R \U$55 ( + .A(\con$171 ), + .Y(\$signal$281 ) + ); + INVx1_ASAP7_75t_R \U$56 ( + .A(\sn$172 ), + .Y(\$signal$40 ) + ); + HAxp5_ASAP7_75t_R \U$57 ( + .A(a[19]), + .B(b[19]), + .CON(\con$173 ), + .SN(\sn$174 ) + ); + INVx1_ASAP7_75t_R \U$58 ( + .A(\con$173 ), + .Y(\$signal$282 ) + ); + INVx1_ASAP7_75t_R \U$59 ( + .A(\sn$174 ), + .Y(\$signal$42 ) + ); + HAxp5_ASAP7_75t_R \U$6 ( + .A(a[2]), + .B(b[2]), + .CON(\con$139 ), + .SN(\sn$140 ) + ); + HAxp5_ASAP7_75t_R \U$60 ( + .A(a[20]), + .B(b[20]), + .CON(\con$175 ), + .SN(\sn$176 ) + ); + INVx1_ASAP7_75t_R \U$61 ( + .A(\con$175 ), + .Y(\$signal$283 ) + ); + INVx1_ASAP7_75t_R \U$62 ( + .A(\sn$176 ), + .Y(\$signal$44 ) + ); + HAxp5_ASAP7_75t_R \U$63 ( + .A(a[21]), + .B(b[21]), + .CON(\con$177 ), + .SN(\sn$178 ) + ); + INVx1_ASAP7_75t_R \U$64 ( + .A(\con$177 ), + .Y(\$signal$284 ) + ); + INVx1_ASAP7_75t_R \U$65 ( + .A(\sn$178 ), + .Y(\$signal$46 ) + ); + HAxp5_ASAP7_75t_R \U$66 ( + .A(a[22]), + .B(b[22]), + .CON(\con$179 ), + .SN(\sn$180 ) + ); + INVx1_ASAP7_75t_R \U$67 ( + .A(\con$179 ), + .Y(\$signal$285 ) + ); + INVx1_ASAP7_75t_R \U$68 ( + .A(\sn$180 ), + .Y(\$signal$48 ) + ); + HAxp5_ASAP7_75t_R \U$69 ( + .A(a[23]), + .B(b[23]), + .CON(\con$181 ), + .SN(\sn$182 ) + ); + INVx1_ASAP7_75t_R \U$7 ( + .A(\con$139 ), + .Y(\$signal$265 ) + ); + INVx1_ASAP7_75t_R \U$70 ( + .A(\con$181 ), + .Y(\$signal$286 ) + ); + INVx1_ASAP7_75t_R \U$71 ( + .A(\sn$182 ), + .Y(\$signal$50 ) + ); + HAxp5_ASAP7_75t_R \U$72 ( + .A(a[24]), + .B(b[24]), + .CON(\con$183 ), + .SN(\sn$184 ) + ); + INVx1_ASAP7_75t_R \U$73 ( + .A(\con$183 ), + .Y(\$signal$287 ) + ); + INVx1_ASAP7_75t_R \U$74 ( + .A(\sn$184 ), + .Y(\$signal$52 ) + ); + HAxp5_ASAP7_75t_R \U$75 ( + .A(a[25]), + .B(b[25]), + .CON(\con$185 ), + .SN(\sn$186 ) + ); + INVx1_ASAP7_75t_R \U$76 ( + .A(\con$185 ), + .Y(\$signal$288 ) + ); + INVx1_ASAP7_75t_R \U$77 ( + .A(\sn$186 ), + .Y(\$signal$54 ) + ); + HAxp5_ASAP7_75t_R \U$78 ( + .A(a[26]), + .B(b[26]), + .CON(\con$187 ), + .SN(\sn$188 ) + ); + INVx1_ASAP7_75t_R \U$79 ( + .A(\con$187 ), + .Y(\$signal$289 ) + ); + INVx1_ASAP7_75t_R \U$8 ( + .A(\sn$140 ), + .Y(\$signal$8 ) + ); + INVx1_ASAP7_75t_R \U$80 ( + .A(\sn$188 ), + .Y(\$signal$56 ) + ); + HAxp5_ASAP7_75t_R \U$81 ( + .A(a[27]), + .B(b[27]), + .CON(\con$189 ), + .SN(\sn$190 ) + ); + INVx1_ASAP7_75t_R \U$82 ( + .A(\con$189 ), + .Y(\$signal$290 ) + ); + INVx1_ASAP7_75t_R \U$83 ( + .A(\sn$190 ), + .Y(\$signal$58 ) + ); + HAxp5_ASAP7_75t_R \U$84 ( + .A(a[28]), + .B(b[28]), + .CON(\con$191 ), + .SN(\sn$192 ) + ); + INVx1_ASAP7_75t_R \U$85 ( + .A(\con$191 ), + .Y(\$signal$291 ) + ); + INVx1_ASAP7_75t_R \U$86 ( + .A(\sn$192 ), + .Y(\$signal$60 ) + ); + HAxp5_ASAP7_75t_R \U$87 ( + .A(a[29]), + .B(b[29]), + .CON(\con$193 ), + .SN(\sn$194 ) + ); + INVx1_ASAP7_75t_R \U$88 ( + .A(\con$193 ), + .Y(\$signal$292 ) + ); + INVx1_ASAP7_75t_R \U$89 ( + .A(\sn$194 ), + .Y(\$signal$62 ) + ); + HAxp5_ASAP7_75t_R \U$9 ( + .A(a[3]), + .B(b[3]), + .CON(\con$141 ), + .SN(\sn$142 ) + ); + HAxp5_ASAP7_75t_R \U$90 ( + .A(a[30]), + .B(b[30]), + .CON(\con$195 ), + .SN(\sn$196 ) + ); + INVx1_ASAP7_75t_R \U$91 ( + .A(\con$195 ), + .Y(\$signal$293 ) + ); + INVx1_ASAP7_75t_R \U$92 ( + .A(\sn$196 ), + .Y(\$signal$64 ) + ); + HAxp5_ASAP7_75t_R \U$93 ( + .A(a[31]), + .B(b[31]), + .CON(\con$197 ), + .SN(\sn$198 ) + ); + INVx1_ASAP7_75t_R \U$94 ( + .A(\con$197 ), + .Y(\$signal$294 ) + ); + INVx1_ASAP7_75t_R \U$95 ( + .A(\sn$198 ), + .Y(\$signal$66 ) + ); + HAxp5_ASAP7_75t_R \U$96 ( + .A(a[32]), + .B(b[32]), + .CON(\con$199 ), + .SN(\sn$200 ) + ); + INVx1_ASAP7_75t_R \U$97 ( + .A(\con$199 ), + .Y(\$signal$295 ) + ); + INVx1_ASAP7_75t_R \U$98 ( + .A(\sn$200 ), + .Y(\$signal$68 ) + ); + HAxp5_ASAP7_75t_R \U$99 ( + .A(a[33]), + .B(b[33]), + .CON(\con$201 ), + .SN(\sn$202 ) + ); + assign \a$1 = a; + assign \b$3 = b; + assign \$signal$5 = \$signal ; + assign \$signal$7 = \$signal$6 ; + assign \$signal$9 = \$signal$8 ; + assign \$signal$11 = \$signal$10 ; + assign \$signal$13 = \$signal$12 ; + assign \$signal$15 = \$signal$14 ; + assign \$signal$17 = \$signal$16 ; + assign \$signal$19 = \$signal$18 ; + assign \$signal$21 = \$signal$20 ; + assign \$signal$23 = \$signal$22 ; + assign \$signal$25 = \$signal$24 ; + assign \$signal$27 = \$signal$26 ; + assign \$signal$29 = \$signal$28 ; + assign \$signal$31 = \$signal$30 ; + assign \$signal$33 = \$signal$32 ; + assign \$signal$35 = \$signal$34 ; + assign \$signal$37 = \$signal$36 ; + assign \$signal$39 = \$signal$38 ; + assign \$signal$41 = \$signal$40 ; + assign \$signal$43 = \$signal$42 ; + assign \$signal$45 = \$signal$44 ; + assign \$signal$47 = \$signal$46 ; + assign \$signal$49 = \$signal$48 ; + assign \$signal$51 = \$signal$50 ; + assign \$signal$53 = \$signal$52 ; + assign \$signal$55 = \$signal$54 ; + assign \$signal$57 = \$signal$56 ; + assign \$signal$59 = \$signal$58 ; + assign \$signal$61 = \$signal$60 ; + assign \$signal$63 = \$signal$62 ; + assign \$signal$65 = \$signal$64 ; + assign \$signal$67 = \$signal$66 ; + assign \$signal$69 = \$signal$68 ; + assign \$signal$71 = \$signal$70 ; + assign \$signal$73 = \$signal$72 ; + assign \$signal$75 = \$signal$74 ; + assign \$signal$77 = \$signal$76 ; + assign \$signal$79 = \$signal$78 ; + assign \$signal$81 = \$signal$80 ; + assign \$signal$83 = \$signal$82 ; + assign \$signal$85 = \$signal$84 ; + assign \$signal$87 = \$signal$86 ; + assign \$signal$89 = \$signal$88 ; + assign \$signal$91 = \$signal$90 ; + assign \$signal$93 = \$signal$92 ; + assign \$signal$95 = \$signal$94 ; + assign \$signal$97 = \$signal$96 ; + assign \$signal$99 = \$signal$98 ; + assign \$signal$101 = \$signal$100 ; + assign \$signal$103 = \$signal$102 ; + assign \$signal$105 = \$signal$104 ; + assign \$signal$107 = \$signal$106 ; + assign \$signal$109 = \$signal$108 ; + assign \$signal$111 = \$signal$110 ; + assign \$signal$113 = \$signal$112 ; + assign \$signal$115 = \$signal$114 ; + assign \$signal$117 = \$signal$116 ; + assign \$signal$119 = \$signal$118 ; + assign \$signal$121 = \$signal$120 ; + assign \$signal$123 = \$signal$122 ; + assign \$signal$125 = \$signal$124 ; + assign \$signal$127 = \$signal$126 ; + assign \$signal$129 = \$signal$128 ; + assign \$signal$131 = \$signal$130 ; + assign o2 = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign o = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign \o$134 = { \$66 , \$65 , \$64 , \$63 , \$62 , \$61 , \$60 , \$59 , \$58 , \$57 , \$56 , \$55 , \$54 , \$53 , \$52 , \$51 , \$50 , \$49 , \$48 , \$47 , \$46 , \$45 , \$44 , \$43 , \$42 , \$41 , \$40 , \$39 , \$38 , \$37 , \$36 , \$35 , \$34 , \$33 , \$32 , \$31 , \$30 , \$29 , \$28 , \$27 , \$26 , \$25 , \$24 , \$23 , \$22 , \$21 , \$20 , \$19 , \$18 , \$17 , \$16 , \$15 , \$14 , \$13 , \$12 , \$11 , \$10 , \$9 , \$8 , \$7 , \$6 , \$5 , \$4 , \$3 }; + assign \port$901$0 = \$3 ; + assign \port$902$0 = \$4 ; + assign \port$903$0 = \$5 ; + assign \port$904$0 = \$6 ; + assign \port$905$0 = \$7 ; + assign \port$906$0 = \$8 ; + assign \port$907$0 = \$9 ; + assign \port$908$0 = \$10 ; + assign \port$909$0 = \$11 ; + assign \port$910$0 = \$12 ; + assign \port$911$0 = \$13 ; + assign \port$912$0 = \$14 ; + assign \port$913$0 = \$15 ; + assign \port$914$0 = \$16 ; + assign \port$915$0 = \$17 ; + assign \port$916$0 = \$18 ; + assign \port$917$0 = \$19 ; + assign \port$918$0 = \$20 ; + assign \port$919$0 = \$21 ; + assign \port$920$0 = \$22 ; + assign \port$921$0 = \$23 ; + assign \port$922$0 = \$24 ; + assign \port$923$0 = \$25 ; + assign \port$924$0 = \$26 ; + assign \port$925$0 = \$27 ; + assign \port$926$0 = \$28 ; + assign \port$927$0 = \$29 ; + assign \port$928$0 = \$30 ; + assign \port$929$0 = \$31 ; + assign \port$930$0 = \$32 ; + assign \port$931$0 = \$33 ; + assign \port$932$0 = \$34 ; + assign \port$933$0 = \$35 ; + assign \port$934$0 = \$36 ; + assign \port$935$0 = \$37 ; + assign \port$936$0 = \$38 ; + assign \port$937$0 = \$39 ; + assign \port$938$0 = \$40 ; + assign \port$939$0 = \$41 ; + assign \port$940$0 = \$42 ; + assign \port$941$0 = \$43 ; + assign \port$942$0 = \$44 ; + assign \port$943$0 = \$45 ; + assign \port$944$0 = \$46 ; + assign \port$945$0 = \$47 ; + assign \port$946$0 = \$48 ; + assign \port$947$0 = \$49 ; + assign \port$948$0 = \$50 ; + assign \port$949$0 = \$51 ; + assign \port$950$0 = \$52 ; + assign \port$951$0 = \$53 ; + assign \port$952$0 = \$54 ; + assign \port$953$0 = \$55 ; + assign \port$954$0 = \$56 ; + assign \port$955$0 = \$57 ; + assign \port$956$0 = \$58 ; + assign \port$957$0 = \$59 ; + assign \port$958$0 = \$60 ; + assign \port$959$0 = \$61 ; + assign \port$960$0 = \$62 ; + assign \port$961$0 = \$63 ; + assign \port$962$0 = \$64 ; + assign \port$963$0 = \$65 ; + assign \port$964$0 = \$66 ; +endmodule diff --git a/flow/designs/src/mock-array/src/main/scala/MockArray.scala b/flow/designs/src/mock-array/src/main/scala/MockArray.scala index 502af0acec..c499a734da 100644 --- a/flow/designs/src/mock-array/src/main/scala/MockArray.scala +++ b/flow/designs/src/mock-array/src/main/scala/MockArray.scala @@ -13,6 +13,7 @@ import chisel3._ import chisel3.util._ import chisel3.stage._ import chisel3.experimental._ +import chisel3.util.HasBlackBoxResource import scopt.OParser import System.err import scopt.RenderingMode @@ -55,6 +56,21 @@ class MockArrayBundle(width: Int, height: Int, singleElementWidth: Int) extends val lsbs = Output(Vec(width * height, Bool())) } +// Generated with: +// +// vlsi-multiplier --register-input --register-post-ppg --register-post-ppa --register-output --bits=32 --algorithm=brentkung --tech=asap7 --output=multiplier.v +class Multiplier extends BlackBox with HasBlackBoxResource { + override def desiredName = "multiplier" + val io = IO(new Bundle { + val a = Input(UInt(32.W)) + val b = Input(UInt(32.W)) + val o = Output(UInt(32.W)) + val rst = Input(Bool()) + val clk = Input(Clock()) + }) + addResource("/multiplier.v") +} + class MockArray(width: Int, height: Int, singleElementWidth: Int) extends Module { val io = IO(new MockArrayBundle(width, height, singleElementWidth)) @@ -74,7 +90,16 @@ class MockArray(width: Int, height: Int, singleElementWidth: Int) // up <-> right (io.outs.asSeq zip (io.ins.asSeq ++ Seq(io.ins.asSeq.head)) .sliding(2).toSeq.reverse.map(_.map(RegNext(_)))).foreach { - case (a, b) => a := RegNext(b(0) ^ b(1)) + case (a, b) => a := RegNext({ + val mult = Module(new Multiplier()) + mult.io.a := b(0) + mult.io.b := b(1) + // save some area and complexity by not having reset + mult.io.rst := false.B + mult.io.clk := clock + // reduce output bit-width until we slight negative slack + mult.io.o(15, 0) + }) } // Combinational logic, but a maximum flight path of 4 elements diff --git a/flow/designs/src/mock-array/util.tcl b/flow/designs/src/mock-array/util.tcl index 960a3dffdb..a219929c6d 100644 --- a/flow/designs/src/mock-array/util.tcl +++ b/flow/designs/src/mock-array/util.tcl @@ -1,56 +1,56 @@ # Helper function to split a string into a list of strings and numbers -proc split_strings_and_numbers {str} { - set result {} - foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { - if {$letters ne ""} { - lappend result $letters - } - if {$numbers ne ""} { - lappend result [expr {$numbers + 0}] ;# Convert to integer - } +proc split_strings_and_numbers { str } { + set result {} + foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { + if { $letters ne "" } { + lappend result $letters } - return $result + if { $numbers ne "" } { + lappend result [expr { $numbers + 0 }] ;# Convert to integer + } + } + return $result } # Custom comparison function -proc natural_compare {str1 str2} { - set list1 [split_strings_and_numbers $str1] - set list2 [split_strings_and_numbers $str2] - set len [expr {min([llength $list1], [llength $list2])}] - for {set i 0} {$i < $len} {incr i} { - set part1 [lindex $list1 $i] - set part2 [lindex $list2 $i] - if {$part1 ne $part2} { - if {[string is integer -strict $part1] && [string is integer -strict $part2]} { - return [expr {$part1 - $part2}] - } else { - return [string compare $part1 $part2] - } - } +proc natural_compare { str1 str2 } { + set list1 [split_strings_and_numbers $str1] + set list2 [split_strings_and_numbers $str2] + set len [expr { min([llength $list1], [llength $list2]) }] + for { set i 0 } { $i < $len } { incr i } { + set part1 [lindex $list1 $i] + set part2 [lindex $list2 $i] + if { $part1 ne $part2 } { + if { [string is integer -strict $part1] && [string is integer -strict $part2] } { + return [expr { $part1 - $part2 }] + } else { + return [string compare $part1 $part2] + } } - return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length + } + return [expr { [llength $list1] - [llength $list2] }] ;# If all parts are equal, compare by length } -proc natural_sort {list} { - return [lsort -command natural_compare $list] +proc natural_sort { list } { + return [lsort -command natural_compare $list] } -proc match_pins { regex {direction .*} {is_clock 0}} { - set pins {} - # The regex for get_ports is not the tcl regex - foreach pin [get_ports -regex .*] { - set input [get_property $pin name] - # We want the Tcl regex - if {![regexp $regex $input]} { - continue - } - if {![regexp $direction [get_property $pin direction]]} { - continue - } - if {[expr $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]]]} { - continue - } - lappend pins [get_property $pin name] +proc match_pins { regex { direction .* } { is_clock 0 } } { + set pins {} + # The regex for get_ports is not the tcl regex + foreach pin [get_ports -regex .*] { + set input [get_property $pin name] + # We want the Tcl regex + if { ![regexp $regex $input] } { + continue + } + if { ![regexp $direction [get_property $pin direction]] } { + continue + } + if { $is_clock != [sta::is_clock_src [sta::get_port_pin $pin]] } { + continue } - return [natural_sort $pins] + lappend pins [get_property $pin name] + } + return [natural_sort $pins] } diff --git a/flow/designs/src/swerv/BUILD.bazel b/flow/designs/src/swerv/BUILD.bazel new file mode 100644 index 0000000000..1639cf0a3b --- /dev/null +++ b/flow/designs/src/swerv/BUILD.bazel @@ -0,0 +1,5 @@ +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/vanilla5/README.md b/flow/designs/src/vanilla5/README.md deleted file mode 100644 index b84126e4ba..0000000000 --- a/flow/designs/src/vanilla5/README.md +++ /dev/null @@ -1,12 +0,0 @@ -# Summary - -`bsg_manycore` tile derived from [here](http://opencelerity.org/). - -# Source - -See more at [this website](https://bitbucket.org/taylor-bsg/bsg_manycore/src). - -# Modifications - -- Added sdc timing constraints. -- Converted to verilog using `bsg_sv2v`. diff --git a/flow/designs/src/vanilla5/bsg_manycore_tile.sv2v.v b/flow/designs/src/vanilla5/bsg_manycore_tile.sv2v.v deleted file mode 100644 index 82c2fa5aeb..0000000000 --- a/flow/designs/src/vanilla5/bsg_manycore_tile.sv2v.v +++ /dev/null @@ -1,20901 +0,0 @@ - - -module bsg_mem_1r1w_synth_width_p76_els_p2_read_write_same_addr_p0_harden_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [0:0] w_addr_i; - input [75:0] w_data_i; - input [0:0] r_addr_i; - output [75:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [75:0] r_data_o; - wire N0,N1,N2,N3,N4,N5,N7,N8; - reg [151:0] mem; - assign r_data_o[75] = (N3)? mem[75] : - (N0)? mem[151] : 1'b0; - assign N0 = r_addr_i[0]; - assign r_data_o[74] = (N3)? mem[74] : - (N0)? mem[150] : 1'b0; - assign r_data_o[73] = (N3)? mem[73] : - (N0)? mem[149] : 1'b0; - assign r_data_o[72] = (N3)? mem[72] : - (N0)? mem[148] : 1'b0; - assign r_data_o[71] = (N3)? mem[71] : - (N0)? mem[147] : 1'b0; - assign r_data_o[70] = (N3)? mem[70] : - (N0)? mem[146] : 1'b0; - assign r_data_o[69] = (N3)? mem[69] : - (N0)? mem[145] : 1'b0; - assign r_data_o[68] = (N3)? mem[68] : - (N0)? mem[144] : 1'b0; - assign r_data_o[67] = (N3)? mem[67] : - (N0)? mem[143] : 1'b0; - assign r_data_o[66] = (N3)? mem[66] : - (N0)? mem[142] : 1'b0; - assign r_data_o[65] = (N3)? mem[65] : - (N0)? mem[141] : 1'b0; - assign r_data_o[64] = (N3)? mem[64] : - (N0)? mem[140] : 1'b0; - assign r_data_o[63] = (N3)? mem[63] : - (N0)? mem[139] : 1'b0; - assign r_data_o[62] = (N3)? mem[62] : - (N0)? mem[138] : 1'b0; - assign r_data_o[61] = (N3)? mem[61] : - (N0)? mem[137] : 1'b0; - assign r_data_o[60] = (N3)? mem[60] : - (N0)? mem[136] : 1'b0; - assign r_data_o[59] = (N3)? mem[59] : - (N0)? mem[135] : 1'b0; - assign r_data_o[58] = (N3)? mem[58] : - (N0)? mem[134] : 1'b0; - assign r_data_o[57] = (N3)? mem[57] : - (N0)? mem[133] : 1'b0; - assign r_data_o[56] = (N3)? mem[56] : - (N0)? mem[132] : 1'b0; - assign r_data_o[55] = (N3)? mem[55] : - (N0)? mem[131] : 1'b0; - assign r_data_o[54] = (N3)? mem[54] : - (N0)? mem[130] : 1'b0; - assign r_data_o[53] = (N3)? mem[53] : - (N0)? mem[129] : 1'b0; - assign r_data_o[52] = (N3)? mem[52] : - (N0)? mem[128] : 1'b0; - assign r_data_o[51] = (N3)? mem[51] : - (N0)? mem[127] : 1'b0; - assign r_data_o[50] = (N3)? mem[50] : - (N0)? mem[126] : 1'b0; - assign r_data_o[49] = (N3)? mem[49] : - (N0)? mem[125] : 1'b0; - assign r_data_o[48] = (N3)? mem[48] : - (N0)? mem[124] : 1'b0; - assign r_data_o[47] = (N3)? mem[47] : - (N0)? mem[123] : 1'b0; - assign r_data_o[46] = (N3)? mem[46] : - (N0)? mem[122] : 1'b0; - assign r_data_o[45] = (N3)? mem[45] : - (N0)? mem[121] : 1'b0; - assign r_data_o[44] = (N3)? mem[44] : - (N0)? mem[120] : 1'b0; - assign r_data_o[43] = (N3)? mem[43] : - (N0)? mem[119] : 1'b0; - assign r_data_o[42] = (N3)? mem[42] : - (N0)? mem[118] : 1'b0; - assign r_data_o[41] = (N3)? mem[41] : - (N0)? mem[117] : 1'b0; - assign r_data_o[40] = (N3)? mem[40] : - (N0)? mem[116] : 1'b0; - assign r_data_o[39] = (N3)? mem[39] : - (N0)? mem[115] : 1'b0; - assign r_data_o[38] = (N3)? mem[38] : - (N0)? mem[114] : 1'b0; - assign r_data_o[37] = (N3)? mem[37] : - (N0)? mem[113] : 1'b0; - assign r_data_o[36] = (N3)? mem[36] : - (N0)? mem[112] : 1'b0; - assign r_data_o[35] = (N3)? mem[35] : - (N0)? mem[111] : 1'b0; - assign r_data_o[34] = (N3)? mem[34] : - (N0)? mem[110] : 1'b0; - assign r_data_o[33] = (N3)? mem[33] : - (N0)? mem[109] : 1'b0; - assign r_data_o[32] = (N3)? mem[32] : - (N0)? mem[108] : 1'b0; - assign r_data_o[31] = (N3)? mem[31] : - (N0)? mem[107] : 1'b0; - assign r_data_o[30] = (N3)? mem[30] : - (N0)? mem[106] : 1'b0; - assign r_data_o[29] = (N3)? mem[29] : - (N0)? mem[105] : 1'b0; - assign r_data_o[28] = (N3)? mem[28] : - (N0)? mem[104] : 1'b0; - assign r_data_o[27] = (N3)? mem[27] : - (N0)? mem[103] : 1'b0; - assign r_data_o[26] = (N3)? mem[26] : - (N0)? mem[102] : 1'b0; - assign r_data_o[25] = (N3)? mem[25] : - (N0)? mem[101] : 1'b0; - assign r_data_o[24] = (N3)? mem[24] : - (N0)? mem[100] : 1'b0; - assign r_data_o[23] = (N3)? mem[23] : - (N0)? mem[99] : 1'b0; - assign r_data_o[22] = (N3)? mem[22] : - (N0)? mem[98] : 1'b0; - assign r_data_o[21] = (N3)? mem[21] : - (N0)? mem[97] : 1'b0; - assign r_data_o[20] = (N3)? mem[20] : - (N0)? mem[96] : 1'b0; - assign r_data_o[19] = (N3)? mem[19] : - (N0)? mem[95] : 1'b0; - assign r_data_o[18] = (N3)? mem[18] : - (N0)? mem[94] : 1'b0; - assign r_data_o[17] = (N3)? mem[17] : - (N0)? mem[93] : 1'b0; - assign r_data_o[16] = (N3)? mem[16] : - (N0)? mem[92] : 1'b0; - assign r_data_o[15] = (N3)? mem[15] : - (N0)? mem[91] : 1'b0; - assign r_data_o[14] = (N3)? mem[14] : - (N0)? mem[90] : 1'b0; - assign r_data_o[13] = (N3)? mem[13] : - (N0)? mem[89] : 1'b0; - assign r_data_o[12] = (N3)? mem[12] : - (N0)? mem[88] : 1'b0; - assign r_data_o[11] = (N3)? mem[11] : - (N0)? mem[87] : 1'b0; - assign r_data_o[10] = (N3)? mem[10] : - (N0)? mem[86] : 1'b0; - assign r_data_o[9] = (N3)? mem[9] : - (N0)? mem[85] : 1'b0; - assign r_data_o[8] = (N3)? mem[8] : - (N0)? mem[84] : 1'b0; - assign r_data_o[7] = (N3)? mem[7] : - (N0)? mem[83] : 1'b0; - assign r_data_o[6] = (N3)? mem[6] : - (N0)? mem[82] : 1'b0; - assign r_data_o[5] = (N3)? mem[5] : - (N0)? mem[81] : 1'b0; - assign r_data_o[4] = (N3)? mem[4] : - (N0)? mem[80] : 1'b0; - assign r_data_o[3] = (N3)? mem[3] : - (N0)? mem[79] : 1'b0; - assign r_data_o[2] = (N3)? mem[2] : - (N0)? mem[78] : 1'b0; - assign r_data_o[1] = (N3)? mem[1] : - (N0)? mem[77] : 1'b0; - assign r_data_o[0] = (N3)? mem[0] : - (N0)? mem[76] : 1'b0; - - always @(posedge w_clk_i) begin - if(N8) begin - mem[151] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[150] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[149] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[148] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[147] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[146] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[145] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[144] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[143] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[142] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[141] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[140] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[139] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[138] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[137] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[136] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[135] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[134] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[133] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[132] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[131] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[130] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[129] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[128] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[127] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[126] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[125] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[124] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[123] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[122] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[121] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[120] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[119] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[118] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[117] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[116] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[115] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[114] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[113] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[112] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[111] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[110] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[109] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[108] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[107] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[106] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[105] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[104] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[103] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[102] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[101] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[100] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[99] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[98] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[97] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[96] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[95] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[94] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[93] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[92] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[91] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[90] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[89] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[88] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[87] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[86] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[85] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[84] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[83] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[82] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[81] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[80] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[79] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[78] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[77] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[76] <= w_data_i[0]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[75] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[74] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[73] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[72] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[71] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[70] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[69] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[68] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[67] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[66] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[65] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[64] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[63] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[62] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[61] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[60] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[59] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[58] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[57] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[56] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[55] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[54] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[53] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[52] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[51] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[50] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[49] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[48] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[47] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[46] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[45] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[44] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[43] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[42] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[41] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[40] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[39] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[38] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[37] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[36] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[35] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[34] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[33] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[32] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[31] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[30] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[29] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[28] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[27] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[26] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[25] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[24] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[23] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[22] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[21] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[20] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[19] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[18] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[17] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[16] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[15] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[14] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[13] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[12] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[11] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[10] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[9] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[8] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[7] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[6] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[5] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[4] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[3] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[2] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[1] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[0] <= w_data_i[0]; - end - end - - assign N5 = ~w_addr_i[0]; - assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } : - (N2)? { 1'b0, 1'b0 } : 1'b0; - assign N1 = w_v_i; - assign N2 = N4; - assign N3 = ~r_addr_i[0]; - assign N4 = ~w_v_i; - -endmodule - - - -module bsg_mem_1r1w_width_p76_els_p2_read_write_same_addr_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [0:0] w_addr_i; - input [75:0] w_data_i; - input [0:0] r_addr_i; - output [75:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [75:0] r_data_o; - - bsg_mem_1r1w_synth_width_p76_els_p2_read_write_same_addr_p0_harden_p0 - synth - ( - .w_clk_i(w_clk_i), - .w_reset_i(w_reset_i), - .w_v_i(w_v_i), - .w_addr_i(w_addr_i[0]), - .w_data_i(w_data_i), - .r_v_i(r_v_i), - .r_addr_i(r_addr_i[0]), - .r_data_o(r_data_o) - ); - - -endmodule - - - -module bsg_two_fifo_width_p76 -( - clk_i, - reset_i, - ready_o, - data_i, - v_i, - v_o, - data_o, - yumi_i -); - - input [75:0] data_i; - output [75:0] data_o; - input clk_i; - input reset_i; - input v_i; - input yumi_i; - output ready_o; - output v_o; - wire [75:0] data_o; - wire ready_o,v_o,N0,N1,enq_i,n_0_net_,n_cse_4,n_cse_6,n_cse_7,N2,N3,N4,N5,N6,N7,N8, - N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21; - reg full_r,tail_r,head_r,empty_r; - - bsg_mem_1r1w_width_p76_els_p2_read_write_same_addr_p0 - mem_1r1w - ( - .w_clk_i(clk_i), - .w_reset_i(reset_i), - .w_v_i(enq_i), - .w_addr_i(tail_r), - .w_data_i(data_i), - .r_v_i(n_0_net_), - .r_addr_i(head_r), - .r_data_o(data_o) - ); - - - always @(posedge clk_i) begin - if(1'b1) begin - full_r <= N14; - end - end - - - always @(posedge clk_i) begin - if(N9) begin - tail_r <= N10; - end - end - - - always @(posedge clk_i) begin - if(N11) begin - head_r <= N12; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - empty_r <= N13; - end - end - - assign N9 = (N0)? 1'b1 : - (N1)? N5 : 1'b0; - assign N0 = N3; - assign N1 = N2; - assign N10 = (N0)? 1'b0 : - (N1)? N4 : 1'b0; - assign N11 = (N0)? 1'b1 : - (N1)? yumi_i : 1'b0; - assign N12 = (N0)? 1'b0 : - (N1)? N6 : 1'b0; - assign N13 = (N0)? 1'b1 : - (N1)? N7 : 1'b0; - assign N14 = (N0)? 1'b0 : - (N1)? N8 : 1'b0; - assign n_0_net_ = ~empty_r; - assign v_o = ~empty_r; - assign ready_o = ~full_r; - assign enq_i = v_i & N15; - assign N15 = ~full_r; - assign n_cse_4 = ~enq_i; - assign n_cse_6 = ~yumi_i; - assign n_cse_7 = N17 & n_cse_6; - assign N17 = N16 & enq_i; - assign N16 = ~empty_r; - assign N2 = ~reset_i; - assign N3 = reset_i; - assign N5 = enq_i; - assign N4 = ~tail_r; - assign N6 = ~head_r; - assign N7 = N18 | N20; - assign N18 = empty_r & n_cse_4; - assign N20 = N19 & n_cse_4; - assign N19 = N15 & yumi_i; - assign N8 = n_cse_7 | N21; - assign N21 = full_r & n_cse_6; - -endmodule - - - -module bsg_mesh_router_dor_decoder_4_5_5_1 -( - clk_i, - v_i, - x_dirs_i, - y_dirs_i, - my_x_i, - my_y_i, - req_o -); - - input [4:0] v_i; - input [19:0] x_dirs_i; - input [24:0] y_dirs_i; - input [3:0] my_x_i; - input [4:0] my_y_i; - output [24:0] req_o; - input clk_i; - wire [24:0] req_o; - wire x_eq_4,x_gt_0,NS_req_4__weird_route,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12, - N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; - wire [2:0] x_eq,y_gt,y_lt; - wire [4:0] y_eq; - wire [4:3] x_gt; - wire [0:0] x_lt; - assign req_o[24] = 1'b0; - assign req_o[18] = 1'b0; - assign req_o[12] = 1'b0; - assign req_o[6] = 1'b0; - assign x_eq[0] = x_dirs_i[3:0] == my_x_i; - assign y_eq[0] = y_dirs_i[4:0] == my_y_i; - assign x_gt_0 = x_dirs_i[3:0] > my_x_i; - assign y_gt[0] = y_dirs_i[4:0] > my_y_i; - assign x_eq[1] = x_dirs_i[7:4] == my_x_i; - assign y_eq[1] = y_dirs_i[9:5] == my_y_i; - assign y_gt[1] = y_dirs_i[9:5] > my_y_i; - assign x_eq[2] = x_dirs_i[11:8] == my_x_i; - assign y_eq[2] = y_dirs_i[14:10] == my_y_i; - assign y_gt[2] = y_dirs_i[14:10] > my_y_i; - assign y_eq[3] = y_dirs_i[19:15] == my_y_i; - assign x_gt[3] = x_dirs_i[15:12] > my_x_i; - assign x_eq_4 = x_dirs_i[19:16] == my_x_i; - assign y_eq[4] = y_dirs_i[24:20] == my_y_i; - assign x_gt[4] = x_dirs_i[19:16] > my_x_i; - assign x_lt[0] = N0 & N1; - assign N0 = ~x_gt_0; - assign N1 = ~x_eq[0]; - assign y_lt[0] = N2 & N3; - assign N2 = ~y_gt[0]; - assign N3 = ~y_eq[0]; - assign y_lt[1] = N4 & N5; - assign N4 = ~y_gt[1]; - assign N5 = ~y_eq[1]; - assign y_lt[2] = N6 & N7; - assign N6 = ~y_gt[2]; - assign N7 = ~y_eq[2]; - assign req_o[7] = v_i[1] & N8; - assign N8 = ~x_eq[1]; - assign req_o[5] = N9 & y_eq[1]; - assign N9 = v_i[1] & x_eq[1]; - assign req_o[9] = N10 & y_gt[1]; - assign N10 = v_i[1] & x_eq[1]; - assign req_o[8] = N11 & y_lt[1]; - assign N11 = v_i[1] & x_eq[1]; - assign req_o[11] = v_i[2] & N12; - assign N12 = ~x_eq[2]; - assign req_o[10] = N13 & y_eq[2]; - assign N13 = v_i[2] & x_eq[2]; - assign req_o[14] = N14 & y_gt[2]; - assign N14 = v_i[2] & x_eq[2]; - assign req_o[13] = N15 & y_lt[2]; - assign N15 = v_i[2] & x_eq[2]; - assign req_o[19] = N17 & N18; - assign N17 = v_i[3] & N16; - assign N16 = ~y_eq[3]; - assign N18 = ~1'b0; - assign req_o[15] = N19 & N18; - assign N19 = v_i[3] & y_eq[3]; - assign req_o[16] = N20 & N21; - assign N20 = v_i[3] & 1'b0; - assign N21 = ~x_gt[3]; - assign req_o[17] = N22 & x_gt[3]; - assign N22 = v_i[3] & 1'b0; - assign NS_req_4__weird_route = ~x_eq_4; - assign req_o[23] = N24 & N25; - assign N24 = v_i[4] & N23; - assign N23 = ~y_eq[4]; - assign N25 = ~NS_req_4__weird_route; - assign req_o[20] = N26 & N25; - assign N26 = v_i[4] & y_eq[4]; - assign req_o[21] = N27 & N28; - assign N27 = v_i[4] & NS_req_4__weird_route; - assign N28 = ~x_gt[4]; - assign req_o[22] = N29 & x_gt[4]; - assign N29 = v_i[4] & NS_req_4__weird_route; - assign req_o[2] = v_i[0] & x_gt_0; - assign req_o[1] = v_i[0] & x_lt[0]; - assign req_o[4] = N30 & y_gt[0]; - assign N30 = v_i[0] & x_eq[0]; - assign req_o[3] = N31 & y_lt[0]; - assign N31 = v_i[0] & x_eq[0]; - assign req_o[0] = N32 & y_eq[0]; - assign N32 = v_i[0] & x_eq[0]; - -endmodule - - - -module bsg_round_robin_arb_inputs_p3 -( - clk_i, - reset_i, - grants_en_i, - reqs_i, - grants_o, - v_o, - tag_o, - yumi_i -); - - input [2:0] reqs_i; - output [2:0] grants_o; - output [1:0] tag_o; - input clk_i; - input reset_i; - input grants_en_i; - input yumi_i; - output v_o; - wire [2:0] grants_o; - wire [1:0] tag_o; - wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20, - N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40, - N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60, - N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75; - reg [1:0] last_r; - assign N10 = grants_en_i & N8; - assign N11 = N9 & N46; - assign N12 = N10 & N11; - assign N15 = grants_en_i & N13; - assign N16 = N14 & reqs_i[1]; - assign N17 = N15 & N16; - assign N18 = N7 | last_r[1]; - assign N19 = last_r[0] | N8; - assign N20 = N18 | N19; - assign N21 = N20 | reqs_i[1]; - assign N23 = N7 | last_r[1]; - assign N24 = last_r[0] | reqs_i[2]; - assign N25 = reqs_i[1] | N46; - assign N26 = N23 | N24; - assign N27 = N26 | N25; - assign N29 = N7 | last_r[1]; - assign N30 = N14 | N8; - assign N31 = N29 | N30; - assign N33 = grants_en_i & N13; - assign N34 = last_r[0] & N8; - assign N35 = N33 & N34; - assign N36 = N35 & reqs_i[0]; - assign N37 = N7 | last_r[1]; - assign N38 = N14 | reqs_i[2]; - assign N39 = N9 | reqs_i[0]; - assign N40 = N37 | N38; - assign N41 = N40 | N39; - assign N43 = grants_en_i & last_r[1]; - assign N44 = N14 & reqs_i[0]; - assign N45 = N43 & N44; - assign N47 = grants_en_i & last_r[1]; - assign N48 = N14 & reqs_i[1]; - assign N49 = N47 & N48; - assign N50 = N49 & N46; - assign N51 = N7 | N13; - assign N52 = last_r[0] | N8; - assign N53 = reqs_i[1] | reqs_i[0]; - assign N54 = N51 | N52; - assign N55 = N54 | N53; - assign N57 = grants_en_i & last_r[1]; - assign N58 = last_r[0] & reqs_i[2]; - assign N59 = N57 & N58; - assign N60 = grants_en_i & last_r[1]; - assign N61 = last_r[0] & reqs_i[0]; - assign N62 = N60 & N61; - assign N63 = grants_en_i & last_r[1]; - assign N64 = last_r[0] & reqs_i[1]; - assign N65 = N63 & N64; - - always @(posedge clk_i) begin - if(N72) begin - last_r[1] <= N70; - end - end - - - always @(posedge clk_i) begin - if(N72) begin - last_r[0] <= N69; - end - end - - assign grants_o = (N7)? { 1'b0, 1'b0, 1'b0 } : - (N0)? { 1'b0, 1'b0, 1'b0 } : - (N1)? { 1'b0, 1'b1, 1'b0 } : - (N22)? { 1'b1, 1'b0, 1'b0 } : - (N28)? { 1'b0, 1'b0, 1'b1 } : - (N32)? { 1'b1, 1'b0, 1'b0 } : - (N2)? { 1'b0, 1'b0, 1'b1 } : - (N42)? { 1'b0, 1'b1, 1'b0 } : - (N3)? { 1'b0, 1'b0, 1'b1 } : - (N4)? { 1'b0, 1'b1, 1'b0 } : - (N56)? { 1'b1, 1'b0, 1'b0 } : 1'b0; - assign N0 = N12; - assign N1 = N17; - assign N2 = N36; - assign N3 = N45; - assign N4 = N50; - assign tag_o = (N7)? { 1'b0, 1'b0 } : - (N0)? { 1'b0, 1'b0 } : - (N1)? { 1'b0, 1'b1 } : - (N22)? { 1'b1, 1'b0 } : - (N28)? { 1'b0, 1'b0 } : - (N32)? { 1'b1, 1'b0 } : - (N2)? { 1'b0, 1'b0 } : - (N42)? { 1'b0, 1'b1 } : - (N3)? { 1'b0, 1'b0 } : - (N4)? { 1'b0, 1'b1 } : - (N56)? { 1'b1, 1'b0 } : - (N66)? { 1'b0, 1'b0 } : 1'b0; - assign { N70, N69 } = (N5)? { 1'b0, 1'b0 } : - (N6)? tag_o : 1'b0; - assign N5 = reset_i; - assign N6 = N68; - assign N7 = ~grants_en_i; - assign N8 = ~reqs_i[2]; - assign N9 = ~reqs_i[1]; - assign N13 = ~last_r[1]; - assign N14 = ~last_r[0]; - assign N22 = ~N21; - assign N28 = ~N27; - assign N32 = ~N31; - assign N42 = ~N41; - assign N46 = ~reqs_i[0]; - assign N56 = ~N55; - assign N66 = N59 | N73; - assign N73 = N62 | N65; - assign v_o = N75 & grants_en_i; - assign N75 = N74 | reqs_i[0]; - assign N74 = reqs_i[2] | reqs_i[1]; - assign N67 = ~yumi_i; - assign N68 = ~reset_i; - assign N71 = N67 & N68; - assign N72 = ~N71; - -endmodule - - - -module bsg_round_robin_arb_inputs_p4 -( - clk_i, - reset_i, - grants_en_i, - reqs_i, - grants_o, - v_o, - tag_o, - yumi_i -); - - input [3:0] reqs_i; - output [3:0] grants_o; - output [1:0] tag_o; - input clk_i; - input reset_i; - input grants_en_i; - input yumi_i; - output v_o; - wire [3:0] grants_o; - wire [1:0] tag_o; - wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20, - N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40, - N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60, - N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80, - N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100, - N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116, - N117,N118,N119,N120,N121,N122,N123,N124,N125,N126; - reg [1:0] last_r; - - always @(posedge clk_i) begin - if(N123) begin - last_r[1] <= N121; - end - end - - - always @(posedge clk_i) begin - if(N123) begin - last_r[0] <= N120; - end - end - - assign N100 = ~grants_en_i; - assign N101 = grants_en_i & N0 & (N1 & N2) & N3; - assign N0 = ~reqs_i[0]; - assign N1 = ~reqs_i[1]; - assign N2 = ~reqs_i[2]; - assign N3 = ~reqs_i[3]; - assign N102 = grants_en_i & reqs_i[1] & (N4 & N5); - assign N4 = ~last_r[0]; - assign N5 = ~last_r[1]; - assign N103 = grants_en_i & N6 & (N7 & reqs_i[2]) & N8; - assign N6 = ~reqs_i[1]; - assign N7 = ~last_r[0]; - assign N8 = ~last_r[1]; - assign N9 = grants_en_i & N13; - assign N10 = N9 & N14; - assign N11 = N10 & N15; - assign N12 = N11 & N16; - assign N104 = N12 & reqs_i[3]; - assign N13 = ~reqs_i[1]; - assign N14 = ~last_r[0]; - assign N15 = ~reqs_i[2]; - assign N16 = ~last_r[1]; - assign N17 = grants_en_i & reqs_i[0]; - assign N18 = N17 & N22; - assign N19 = N18 & N23; - assign N20 = N19 & N24; - assign N21 = N20 & N25; - assign N105 = N21 & N26; - assign N22 = ~reqs_i[1]; - assign N23 = ~last_r[0]; - assign N24 = ~reqs_i[2]; - assign N25 = ~last_r[1]; - assign N26 = ~reqs_i[3]; - assign N106 = grants_en_i & last_r[0] & (reqs_i[2] & N27); - assign N27 = ~last_r[1]; - assign N107 = grants_en_i & last_r[0] & (N28 & N29) & reqs_i[3]; - assign N28 = ~reqs_i[2]; - assign N29 = ~last_r[1]; - assign N30 = grants_en_i & reqs_i[0]; - assign N31 = N30 & last_r[0]; - assign N32 = N31 & N34; - assign N33 = N32 & N35; - assign N108 = N33 & N36; - assign N34 = ~reqs_i[2]; - assign N35 = ~last_r[1]; - assign N36 = ~reqs_i[3]; - assign N37 = grants_en_i & N42; - assign N38 = N37 & reqs_i[1]; - assign N39 = N38 & last_r[0]; - assign N40 = N39 & N43; - assign N41 = N40 & N44; - assign N109 = N41 & N45; - assign N42 = ~reqs_i[0]; - assign N43 = ~reqs_i[2]; - assign N44 = ~last_r[1]; - assign N45 = ~reqs_i[3]; - assign N110 = grants_en_i & N46 & (last_r[1] & reqs_i[3]); - assign N46 = ~last_r[0]; - assign N111 = grants_en_i & reqs_i[0] & (N47 & last_r[1]) & N48; - assign N47 = ~last_r[0]; - assign N48 = ~reqs_i[3]; - assign N49 = grants_en_i & N53; - assign N50 = N49 & reqs_i[1]; - assign N51 = N50 & N54; - assign N52 = N51 & last_r[1]; - assign N112 = N52 & N55; - assign N53 = ~reqs_i[0]; - assign N54 = ~last_r[0]; - assign N55 = ~reqs_i[3]; - assign N56 = grants_en_i & N61; - assign N57 = N56 & N62; - assign N58 = N57 & N63; - assign N59 = N58 & reqs_i[2]; - assign N60 = N59 & last_r[1]; - assign N113 = N60 & N64; - assign N61 = ~reqs_i[0]; - assign N62 = ~reqs_i[1]; - assign N63 = ~last_r[0]; - assign N64 = ~reqs_i[3]; - assign N114 = grants_en_i & reqs_i[0] & (last_r[0] & last_r[1]); - assign N115 = grants_en_i & N65 & (reqs_i[1] & last_r[0]) & last_r[1]; - assign N65 = ~reqs_i[0]; - assign N66 = grants_en_i & N70; - assign N67 = N66 & N71; - assign N68 = N67 & last_r[0]; - assign N69 = N68 & reqs_i[2]; - assign N116 = N69 & last_r[1]; - assign N70 = ~reqs_i[0]; - assign N71 = ~reqs_i[1]; - assign N72 = grants_en_i & N77; - assign N73 = N72 & N78; - assign N74 = N73 & last_r[0]; - assign N75 = N74 & N79; - assign N76 = N75 & last_r[1]; - assign N117 = N76 & reqs_i[3]; - assign N77 = ~reqs_i[0]; - assign N78 = ~reqs_i[1]; - assign N79 = ~reqs_i[2]; - assign grants_o = (N80)? { 1'b0, 1'b0, 1'b0, 1'b0 } : - (N81)? { 1'b0, 1'b0, 1'b0, 1'b0 } : - (N82)? { 1'b0, 1'b0, 1'b1, 1'b0 } : - (N83)? { 1'b0, 1'b1, 1'b0, 1'b0 } : - (N84)? { 1'b1, 1'b0, 1'b0, 1'b0 } : - (N85)? { 1'b0, 1'b0, 1'b0, 1'b1 } : - (N86)? { 1'b0, 1'b1, 1'b0, 1'b0 } : - (N87)? { 1'b1, 1'b0, 1'b0, 1'b0 } : - (N88)? { 1'b0, 1'b0, 1'b0, 1'b1 } : - (N89)? { 1'b0, 1'b0, 1'b1, 1'b0 } : - (N90)? { 1'b1, 1'b0, 1'b0, 1'b0 } : - (N91)? { 1'b0, 1'b0, 1'b0, 1'b1 } : - (N92)? { 1'b0, 1'b0, 1'b1, 1'b0 } : - (N93)? { 1'b0, 1'b1, 1'b0, 1'b0 } : - (N94)? { 1'b0, 1'b0, 1'b0, 1'b1 } : - (N95)? { 1'b0, 1'b0, 1'b1, 1'b0 } : - (N96)? { 1'b0, 1'b1, 1'b0, 1'b0 } : - (N97)? { 1'b1, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N80 = N100; - assign N81 = N101; - assign N82 = N102; - assign N83 = N103; - assign N84 = N104; - assign N85 = N105; - assign N86 = N106; - assign N87 = N107; - assign N88 = N108; - assign N89 = N109; - assign N90 = N110; - assign N91 = N111; - assign N92 = N112; - assign N93 = N113; - assign N94 = N114; - assign N95 = N115; - assign N96 = N116; - assign N97 = N117; - assign tag_o = (N80)? { 1'b0, 1'b0 } : - (N81)? { 1'b0, 1'b0 } : - (N82)? { 1'b0, 1'b1 } : - (N83)? { 1'b1, 1'b0 } : - (N84)? { 1'b1, 1'b1 } : - (N85)? { 1'b0, 1'b0 } : - (N86)? { 1'b1, 1'b0 } : - (N87)? { 1'b1, 1'b1 } : - (N88)? { 1'b0, 1'b0 } : - (N89)? { 1'b0, 1'b1 } : - (N90)? { 1'b1, 1'b1 } : - (N91)? { 1'b0, 1'b0 } : - (N92)? { 1'b0, 1'b1 } : - (N93)? { 1'b1, 1'b0 } : - (N94)? { 1'b0, 1'b0 } : - (N95)? { 1'b0, 1'b1 } : - (N96)? { 1'b1, 1'b0 } : - (N97)? { 1'b1, 1'b1 } : 1'b0; - assign { N121, N120 } = (N98)? { 1'b0, 1'b0 } : - (N99)? tag_o : 1'b0; - assign N98 = reset_i; - assign N99 = N119; - assign v_o = N126 & grants_en_i; - assign N126 = N125 | reqs_i[0]; - assign N125 = N124 | reqs_i[1]; - assign N124 = reqs_i[3] | reqs_i[2]; - assign N118 = ~yumi_i; - assign N119 = ~reset_i; - assign N122 = N118 & N119; - assign N123 = ~N122; - -endmodule - - - -module bsg_round_robin_arb_inputs_p5 -( - clk_i, - reset_i, - grants_en_i, - reqs_i, - grants_o, - v_o, - tag_o, - yumi_i -); - - input [4:0] reqs_i; - output [4:0] grants_o; - output [2:0] tag_o; - input clk_i; - input reset_i; - input grants_en_i; - input yumi_i; - output v_o; - wire [4:0] grants_o; - wire [2:0] tag_o; - wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20, - N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40, - N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60, - N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80, - N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100, - N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116, - N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132, - N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148, - N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164, - N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180, - N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196, - N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212, - N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224; - reg [2:0] last_r; - assign N23 = grants_en_i & N119; - assign N24 = N20 & N64; - assign N25 = N21 & N22; - assign N26 = N23 & N24; - assign N27 = N26 & N25; - assign N31 = grants_en_i & N28; - assign N32 = N29 & N30; - assign N33 = N31 & N32; - assign N34 = N33 & reqs_i[1]; - assign N35 = grants_en_i & N28; - assign N36 = N29 & N30; - assign N37 = reqs_i[2] & N21; - assign N38 = N35 & N36; - assign N39 = N38 & N37; - assign N40 = grants_en_i & N28; - assign N41 = N29 & N30; - assign N42 = N40 & N41; - assign N43 = N67 & N21; - assign N44 = N42 & N43; - assign N45 = N19 | last_r[2]; - assign N46 = last_r[1] | last_r[0]; - assign N47 = reqs_i[2] | reqs_i[1]; - assign N48 = N45 | N46; - assign N49 = N97 | N47; - assign N50 = N48 | N49; - assign N52 = N19 | last_r[2]; - assign N53 = last_r[1] | last_r[0]; - assign N54 = reqs_i[4] | reqs_i[3]; - assign N55 = N52 | N53; - assign N56 = N54 | N47; - assign N57 = N55 | N56; - assign N58 = N57 | N22; - assign N60 = grants_en_i & N28; - assign N61 = N29 & last_r[0]; - assign N62 = N60 & N61; - assign N63 = N62 & reqs_i[2]; - assign N65 = grants_en_i & N28; - assign N66 = N29 & last_r[0]; - assign N67 = reqs_i[3] & N64; - assign N68 = N65 & N66; - assign N69 = N68 & N67; - assign N70 = N19 | last_r[2]; - assign N71 = last_r[1] | N30; - assign N72 = N70 | N71; - assign N73 = N97 | reqs_i[2]; - assign N74 = N72 | N73; - assign N76 = grants_en_i & N28; - assign N77 = N29 & last_r[0]; - assign N78 = N119 & N20; - assign N79 = N64 & reqs_i[0]; - assign N80 = N76 & N77; - assign N81 = N78 & N79; - assign N82 = N80 & N81; - assign N83 = N19 | last_r[2]; - assign N84 = last_r[1] | N30; - assign N85 = reqs_i[2] | N21; - assign N86 = N83 | N84; - assign N87 = N54 | N85; - assign N88 = N86 | N87; - assign N89 = N88 | reqs_i[0]; - assign N91 = grants_en_i & N28; - assign N92 = last_r[1] & N30; - assign N93 = N91 & N92; - assign N94 = N93 & reqs_i[3]; - assign N95 = N19 | last_r[2]; - assign N96 = N29 | last_r[0]; - assign N97 = N119 | reqs_i[3]; - assign N98 = N95 | N96; - assign N99 = N98 | N97; - assign N101 = grants_en_i & N28; - assign N102 = last_r[1] & N30; - assign N103 = N101 & N102; - assign N104 = N78 & reqs_i[0]; - assign N105 = N103 & N104; - assign N106 = grants_en_i & N28; - assign N107 = last_r[1] & N30; - assign N108 = N106 & N107; - assign N109 = N78 & N156; - assign N110 = N108 & N109; - assign N111 = N19 | last_r[2]; - assign N112 = N29 | last_r[0]; - assign N113 = N64 | reqs_i[1]; - assign N114 = N111 | N112; - assign N115 = N54 | N113; - assign N116 = N114 | N115; - assign N117 = N116 | reqs_i[0]; - assign N120 = N19 | last_r[2]; - assign N121 = N29 | N30; - assign N122 = N120 | N121; - assign N123 = N122 | N119; - assign N125 = grants_en_i & N28; - assign N126 = last_r[1] & last_r[0]; - assign N127 = N119 & reqs_i[0]; - assign N128 = N125 & N126; - assign N129 = N128 & N127; - assign N130 = grants_en_i & N28; - assign N131 = last_r[1] & last_r[0]; - assign N132 = N119 & reqs_i[1]; - assign N133 = N130 & N131; - assign N134 = N132 & N22; - assign N135 = N133 & N134; - assign N136 = grants_en_i & N28; - assign N137 = last_r[1] & last_r[0]; - assign N138 = N119 & reqs_i[2]; - assign N139 = N136 & N137; - assign N140 = N138 & N25; - assign N141 = N139 & N140; - assign N142 = N19 | last_r[2]; - assign N143 = N29 | N30; - assign N144 = reqs_i[4] | N20; - assign N145 = N142 | N143; - assign N146 = N144 | N47; - assign N147 = N145 | N146; - assign N148 = N147 | reqs_i[0]; - assign N150 = grants_en_i & last_r[2]; - assign N151 = N29 & N30; - assign N152 = N150 & N151; - assign N153 = N152 & reqs_i[0]; - assign N154 = grants_en_i & last_r[2]; - assign N155 = N29 & N30; - assign N156 = reqs_i[1] & N22; - assign N157 = N154 & N155; - assign N158 = N157 & N156; - assign N159 = grants_en_i & last_r[2]; - assign N160 = N29 & N30; - assign N161 = N159 & N160; - assign N162 = N37 & N22; - assign N163 = N161 & N162; - assign N164 = grants_en_i & last_r[2]; - assign N165 = N29 & N30; - assign N166 = N164 & N165; - assign N167 = N67 & N25; - assign N168 = N166 & N167; - assign N169 = N19 | N28; - assign N170 = last_r[1] | last_r[0]; - assign N171 = N169 | N170; - assign N172 = N171 | N49; - assign N173 = N172 | reqs_i[0]; - assign N175 = grants_en_i & last_r[2]; - assign N176 = last_r[0] & reqs_i[2]; - assign N177 = N175 & N176; - assign N178 = grants_en_i & last_r[2]; - assign N179 = last_r[0] & reqs_i[3]; - assign N180 = N178 & N179; - assign N181 = grants_en_i & last_r[2]; - assign N182 = last_r[0] & reqs_i[4]; - assign N183 = N181 & N182; - assign N184 = grants_en_i & last_r[2]; - assign N185 = last_r[0] & reqs_i[0]; - assign N186 = N184 & N185; - assign N187 = grants_en_i & last_r[2]; - assign N188 = last_r[0] & reqs_i[1]; - assign N189 = N187 & N188; - assign N190 = grants_en_i & last_r[2]; - assign N191 = last_r[1] & reqs_i[3]; - assign N192 = N190 & N191; - assign N193 = grants_en_i & last_r[2]; - assign N194 = last_r[1] & reqs_i[4]; - assign N195 = N193 & N194; - assign N196 = grants_en_i & last_r[2]; - assign N197 = last_r[1] & reqs_i[0]; - assign N198 = N196 & N197; - assign N199 = grants_en_i & last_r[2]; - assign N200 = last_r[1] & reqs_i[1]; - assign N201 = N199 & N200; - assign N202 = grants_en_i & last_r[2]; - assign N203 = last_r[1] & reqs_i[2]; - assign N204 = N202 & N203; - - always @(posedge clk_i) begin - if(N212) begin - last_r[2] <= N210; - end - end - - - always @(posedge clk_i) begin - if(N212) begin - last_r[1] <= N209; - end - end - - - always @(posedge clk_i) begin - if(N212) begin - last_r[0] <= N208; - end - end - - assign grants_o = (N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N3)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N51)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N59)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N4)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N75)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N90)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N7)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N100)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N8)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N9)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N118)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N124)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N10)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N11)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N12)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N149)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N13)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N14)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N15)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N16)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N174)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N0 = N27; - assign N1 = N34; - assign N2 = N39; - assign N3 = N44; - assign N4 = N63; - assign N5 = N69; - assign N6 = N82; - assign N7 = N94; - assign N8 = N105; - assign N9 = N110; - assign N10 = N129; - assign N11 = N135; - assign N12 = N141; - assign N13 = N153; - assign N14 = N158; - assign N15 = N163; - assign N16 = N168; - assign tag_o = (N19)? { 1'b0, 1'b0, 1'b0 } : - (N0)? { 1'b0, 1'b0, 1'b0 } : - (N1)? { 1'b0, 1'b0, 1'b1 } : - (N2)? { 1'b0, 1'b1, 1'b0 } : - (N3)? { 1'b0, 1'b1, 1'b1 } : - (N51)? { 1'b1, 1'b0, 1'b0 } : - (N59)? { 1'b0, 1'b0, 1'b0 } : - (N4)? { 1'b0, 1'b1, 1'b0 } : - (N5)? { 1'b0, 1'b1, 1'b1 } : - (N75)? { 1'b1, 1'b0, 1'b0 } : - (N6)? { 1'b0, 1'b0, 1'b0 } : - (N90)? { 1'b0, 1'b0, 1'b1 } : - (N7)? { 1'b0, 1'b1, 1'b1 } : - (N100)? { 1'b1, 1'b0, 1'b0 } : - (N8)? { 1'b0, 1'b0, 1'b0 } : - (N9)? { 1'b0, 1'b0, 1'b1 } : - (N118)? { 1'b0, 1'b1, 1'b0 } : - (N124)? { 1'b1, 1'b0, 1'b0 } : - (N10)? { 1'b0, 1'b0, 1'b0 } : - (N11)? { 1'b0, 1'b0, 1'b1 } : - (N12)? { 1'b0, 1'b1, 1'b0 } : - (N149)? { 1'b0, 1'b1, 1'b1 } : - (N13)? { 1'b0, 1'b0, 1'b0 } : - (N14)? { 1'b0, 1'b0, 1'b1 } : - (N15)? { 1'b0, 1'b1, 1'b0 } : - (N16)? { 1'b0, 1'b1, 1'b1 } : - (N174)? { 1'b1, 1'b0, 1'b0 } : - (N205)? { 1'b0, 1'b0, 1'b0 } : 1'b0; - assign { N210, N209, N208 } = (N17)? { 1'b0, 1'b0, 1'b0 } : - (N18)? tag_o : 1'b0; - assign N17 = reset_i; - assign N18 = N207; - assign N19 = ~grants_en_i; - assign N20 = ~reqs_i[3]; - assign N21 = ~reqs_i[1]; - assign N22 = ~reqs_i[0]; - assign N28 = ~last_r[2]; - assign N29 = ~last_r[1]; - assign N30 = ~last_r[0]; - assign N51 = ~N50; - assign N59 = ~N58; - assign N64 = ~reqs_i[2]; - assign N75 = ~N74; - assign N90 = ~N89; - assign N100 = ~N99; - assign N118 = ~N117; - assign N119 = ~reqs_i[4]; - assign N124 = ~N123; - assign N149 = ~N148; - assign N174 = ~N173; - assign N205 = N177 | N220; - assign N220 = N180 | N219; - assign N219 = N183 | N218; - assign N218 = N186 | N217; - assign N217 = N189 | N216; - assign N216 = N192 | N215; - assign N215 = N195 | N214; - assign N214 = N198 | N213; - assign N213 = N201 | N204; - assign v_o = N224 & grants_en_i; - assign N224 = N223 | reqs_i[0]; - assign N223 = N222 | reqs_i[1]; - assign N222 = N221 | reqs_i[2]; - assign N221 = reqs_i[4] | reqs_i[3]; - assign N206 = ~yumi_i; - assign N207 = ~reset_i; - assign N211 = N206 & N207; - assign N212 = ~N211; - -endmodule - - - -module bsg_mux_one_hot_width_p76_els_p3 -( - data_i, - sel_one_hot_i, - data_o -); - - input [227:0] data_i; - input [2:0] sel_one_hot_i; - output [75:0] data_o; - wire [75:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41, - N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61, - N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75; - wire [227:0] data_masked; - assign data_masked[75] = data_i[75] & sel_one_hot_i[0]; - assign data_masked[74] = data_i[74] & sel_one_hot_i[0]; - assign data_masked[73] = data_i[73] & sel_one_hot_i[0]; - assign data_masked[72] = data_i[72] & sel_one_hot_i[0]; - assign data_masked[71] = data_i[71] & sel_one_hot_i[0]; - assign data_masked[70] = data_i[70] & sel_one_hot_i[0]; - assign data_masked[69] = data_i[69] & sel_one_hot_i[0]; - assign data_masked[68] = data_i[68] & sel_one_hot_i[0]; - assign data_masked[67] = data_i[67] & sel_one_hot_i[0]; - assign data_masked[66] = data_i[66] & sel_one_hot_i[0]; - assign data_masked[65] = data_i[65] & sel_one_hot_i[0]; - assign data_masked[64] = data_i[64] & sel_one_hot_i[0]; - assign data_masked[63] = data_i[63] & sel_one_hot_i[0]; - assign data_masked[62] = data_i[62] & sel_one_hot_i[0]; - assign data_masked[61] = data_i[61] & sel_one_hot_i[0]; - assign data_masked[60] = data_i[60] & sel_one_hot_i[0]; - assign data_masked[59] = data_i[59] & sel_one_hot_i[0]; - assign data_masked[58] = data_i[58] & sel_one_hot_i[0]; - assign data_masked[57] = data_i[57] & sel_one_hot_i[0]; - assign data_masked[56] = data_i[56] & sel_one_hot_i[0]; - assign data_masked[55] = data_i[55] & sel_one_hot_i[0]; - assign data_masked[54] = data_i[54] & sel_one_hot_i[0]; - assign data_masked[53] = data_i[53] & sel_one_hot_i[0]; - assign data_masked[52] = data_i[52] & sel_one_hot_i[0]; - assign data_masked[51] = data_i[51] & sel_one_hot_i[0]; - assign data_masked[50] = data_i[50] & sel_one_hot_i[0]; - assign data_masked[49] = data_i[49] & sel_one_hot_i[0]; - assign data_masked[48] = data_i[48] & sel_one_hot_i[0]; - assign data_masked[47] = data_i[47] & sel_one_hot_i[0]; - assign data_masked[46] = data_i[46] & sel_one_hot_i[0]; - assign data_masked[45] = data_i[45] & sel_one_hot_i[0]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[0]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[0]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[0]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[0]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[0]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[0]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[0]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[0]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[0]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[0]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[0]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[0]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[0]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[0]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[0]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[0]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[0]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[0]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[0]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[0]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[0]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[0]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[0]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[0]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[0]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[0]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[0]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[0]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[0]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[0]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[0]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[0]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[0]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[151] = data_i[151] & sel_one_hot_i[1]; - assign data_masked[150] = data_i[150] & sel_one_hot_i[1]; - assign data_masked[149] = data_i[149] & sel_one_hot_i[1]; - assign data_masked[148] = data_i[148] & sel_one_hot_i[1]; - assign data_masked[147] = data_i[147] & sel_one_hot_i[1]; - assign data_masked[146] = data_i[146] & sel_one_hot_i[1]; - assign data_masked[145] = data_i[145] & sel_one_hot_i[1]; - assign data_masked[144] = data_i[144] & sel_one_hot_i[1]; - assign data_masked[143] = data_i[143] & sel_one_hot_i[1]; - assign data_masked[142] = data_i[142] & sel_one_hot_i[1]; - assign data_masked[141] = data_i[141] & sel_one_hot_i[1]; - assign data_masked[140] = data_i[140] & sel_one_hot_i[1]; - assign data_masked[139] = data_i[139] & sel_one_hot_i[1]; - assign data_masked[138] = data_i[138] & sel_one_hot_i[1]; - assign data_masked[137] = data_i[137] & sel_one_hot_i[1]; - assign data_masked[136] = data_i[136] & sel_one_hot_i[1]; - assign data_masked[135] = data_i[135] & sel_one_hot_i[1]; - assign data_masked[134] = data_i[134] & sel_one_hot_i[1]; - assign data_masked[133] = data_i[133] & sel_one_hot_i[1]; - assign data_masked[132] = data_i[132] & sel_one_hot_i[1]; - assign data_masked[131] = data_i[131] & sel_one_hot_i[1]; - assign data_masked[130] = data_i[130] & sel_one_hot_i[1]; - assign data_masked[129] = data_i[129] & sel_one_hot_i[1]; - assign data_masked[128] = data_i[128] & sel_one_hot_i[1]; - assign data_masked[127] = data_i[127] & sel_one_hot_i[1]; - assign data_masked[126] = data_i[126] & sel_one_hot_i[1]; - assign data_masked[125] = data_i[125] & sel_one_hot_i[1]; - assign data_masked[124] = data_i[124] & sel_one_hot_i[1]; - assign data_masked[123] = data_i[123] & sel_one_hot_i[1]; - assign data_masked[122] = data_i[122] & sel_one_hot_i[1]; - assign data_masked[121] = data_i[121] & sel_one_hot_i[1]; - assign data_masked[120] = data_i[120] & sel_one_hot_i[1]; - assign data_masked[119] = data_i[119] & sel_one_hot_i[1]; - assign data_masked[118] = data_i[118] & sel_one_hot_i[1]; - assign data_masked[117] = data_i[117] & sel_one_hot_i[1]; - assign data_masked[116] = data_i[116] & sel_one_hot_i[1]; - assign data_masked[115] = data_i[115] & sel_one_hot_i[1]; - assign data_masked[114] = data_i[114] & sel_one_hot_i[1]; - assign data_masked[113] = data_i[113] & sel_one_hot_i[1]; - assign data_masked[112] = data_i[112] & sel_one_hot_i[1]; - assign data_masked[111] = data_i[111] & sel_one_hot_i[1]; - assign data_masked[110] = data_i[110] & sel_one_hot_i[1]; - assign data_masked[109] = data_i[109] & sel_one_hot_i[1]; - assign data_masked[108] = data_i[108] & sel_one_hot_i[1]; - assign data_masked[107] = data_i[107] & sel_one_hot_i[1]; - assign data_masked[106] = data_i[106] & sel_one_hot_i[1]; - assign data_masked[105] = data_i[105] & sel_one_hot_i[1]; - assign data_masked[104] = data_i[104] & sel_one_hot_i[1]; - assign data_masked[103] = data_i[103] & sel_one_hot_i[1]; - assign data_masked[102] = data_i[102] & sel_one_hot_i[1]; - assign data_masked[101] = data_i[101] & sel_one_hot_i[1]; - assign data_masked[100] = data_i[100] & sel_one_hot_i[1]; - assign data_masked[99] = data_i[99] & sel_one_hot_i[1]; - assign data_masked[98] = data_i[98] & sel_one_hot_i[1]; - assign data_masked[97] = data_i[97] & sel_one_hot_i[1]; - assign data_masked[96] = data_i[96] & sel_one_hot_i[1]; - assign data_masked[95] = data_i[95] & sel_one_hot_i[1]; - assign data_masked[94] = data_i[94] & sel_one_hot_i[1]; - assign data_masked[93] = data_i[93] & sel_one_hot_i[1]; - assign data_masked[92] = data_i[92] & sel_one_hot_i[1]; - assign data_masked[91] = data_i[91] & sel_one_hot_i[1]; - assign data_masked[90] = data_i[90] & sel_one_hot_i[1]; - assign data_masked[89] = data_i[89] & sel_one_hot_i[1]; - assign data_masked[88] = data_i[88] & sel_one_hot_i[1]; - assign data_masked[87] = data_i[87] & sel_one_hot_i[1]; - assign data_masked[86] = data_i[86] & sel_one_hot_i[1]; - assign data_masked[85] = data_i[85] & sel_one_hot_i[1]; - assign data_masked[84] = data_i[84] & sel_one_hot_i[1]; - assign data_masked[83] = data_i[83] & sel_one_hot_i[1]; - assign data_masked[82] = data_i[82] & sel_one_hot_i[1]; - assign data_masked[81] = data_i[81] & sel_one_hot_i[1]; - assign data_masked[80] = data_i[80] & sel_one_hot_i[1]; - assign data_masked[79] = data_i[79] & sel_one_hot_i[1]; - assign data_masked[78] = data_i[78] & sel_one_hot_i[1]; - assign data_masked[77] = data_i[77] & sel_one_hot_i[1]; - assign data_masked[76] = data_i[76] & sel_one_hot_i[1]; - assign data_masked[227] = data_i[227] & sel_one_hot_i[2]; - assign data_masked[226] = data_i[226] & sel_one_hot_i[2]; - assign data_masked[225] = data_i[225] & sel_one_hot_i[2]; - assign data_masked[224] = data_i[224] & sel_one_hot_i[2]; - assign data_masked[223] = data_i[223] & sel_one_hot_i[2]; - assign data_masked[222] = data_i[222] & sel_one_hot_i[2]; - assign data_masked[221] = data_i[221] & sel_one_hot_i[2]; - assign data_masked[220] = data_i[220] & sel_one_hot_i[2]; - assign data_masked[219] = data_i[219] & sel_one_hot_i[2]; - assign data_masked[218] = data_i[218] & sel_one_hot_i[2]; - assign data_masked[217] = data_i[217] & sel_one_hot_i[2]; - assign data_masked[216] = data_i[216] & sel_one_hot_i[2]; - assign data_masked[215] = data_i[215] & sel_one_hot_i[2]; - assign data_masked[214] = data_i[214] & sel_one_hot_i[2]; - assign data_masked[213] = data_i[213] & sel_one_hot_i[2]; - assign data_masked[212] = data_i[212] & sel_one_hot_i[2]; - assign data_masked[211] = data_i[211] & sel_one_hot_i[2]; - assign data_masked[210] = data_i[210] & sel_one_hot_i[2]; - assign data_masked[209] = data_i[209] & sel_one_hot_i[2]; - assign data_masked[208] = data_i[208] & sel_one_hot_i[2]; - assign data_masked[207] = data_i[207] & sel_one_hot_i[2]; - assign data_masked[206] = data_i[206] & sel_one_hot_i[2]; - assign data_masked[205] = data_i[205] & sel_one_hot_i[2]; - assign data_masked[204] = data_i[204] & sel_one_hot_i[2]; - assign data_masked[203] = data_i[203] & sel_one_hot_i[2]; - assign data_masked[202] = data_i[202] & sel_one_hot_i[2]; - assign data_masked[201] = data_i[201] & sel_one_hot_i[2]; - assign data_masked[200] = data_i[200] & sel_one_hot_i[2]; - assign data_masked[199] = data_i[199] & sel_one_hot_i[2]; - assign data_masked[198] = data_i[198] & sel_one_hot_i[2]; - assign data_masked[197] = data_i[197] & sel_one_hot_i[2]; - assign data_masked[196] = data_i[196] & sel_one_hot_i[2]; - assign data_masked[195] = data_i[195] & sel_one_hot_i[2]; - assign data_masked[194] = data_i[194] & sel_one_hot_i[2]; - assign data_masked[193] = data_i[193] & sel_one_hot_i[2]; - assign data_masked[192] = data_i[192] & sel_one_hot_i[2]; - assign data_masked[191] = data_i[191] & sel_one_hot_i[2]; - assign data_masked[190] = data_i[190] & sel_one_hot_i[2]; - assign data_masked[189] = data_i[189] & sel_one_hot_i[2]; - assign data_masked[188] = data_i[188] & sel_one_hot_i[2]; - assign data_masked[187] = data_i[187] & sel_one_hot_i[2]; - assign data_masked[186] = data_i[186] & sel_one_hot_i[2]; - assign data_masked[185] = data_i[185] & sel_one_hot_i[2]; - assign data_masked[184] = data_i[184] & sel_one_hot_i[2]; - assign data_masked[183] = data_i[183] & sel_one_hot_i[2]; - assign data_masked[182] = data_i[182] & sel_one_hot_i[2]; - assign data_masked[181] = data_i[181] & sel_one_hot_i[2]; - assign data_masked[180] = data_i[180] & sel_one_hot_i[2]; - assign data_masked[179] = data_i[179] & sel_one_hot_i[2]; - assign data_masked[178] = data_i[178] & sel_one_hot_i[2]; - assign data_masked[177] = data_i[177] & sel_one_hot_i[2]; - assign data_masked[176] = data_i[176] & sel_one_hot_i[2]; - assign data_masked[175] = data_i[175] & sel_one_hot_i[2]; - assign data_masked[174] = data_i[174] & sel_one_hot_i[2]; - assign data_masked[173] = data_i[173] & sel_one_hot_i[2]; - assign data_masked[172] = data_i[172] & sel_one_hot_i[2]; - assign data_masked[171] = data_i[171] & sel_one_hot_i[2]; - assign data_masked[170] = data_i[170] & sel_one_hot_i[2]; - assign data_masked[169] = data_i[169] & sel_one_hot_i[2]; - assign data_masked[168] = data_i[168] & sel_one_hot_i[2]; - assign data_masked[167] = data_i[167] & sel_one_hot_i[2]; - assign data_masked[166] = data_i[166] & sel_one_hot_i[2]; - assign data_masked[165] = data_i[165] & sel_one_hot_i[2]; - assign data_masked[164] = data_i[164] & sel_one_hot_i[2]; - assign data_masked[163] = data_i[163] & sel_one_hot_i[2]; - assign data_masked[162] = data_i[162] & sel_one_hot_i[2]; - assign data_masked[161] = data_i[161] & sel_one_hot_i[2]; - assign data_masked[160] = data_i[160] & sel_one_hot_i[2]; - assign data_masked[159] = data_i[159] & sel_one_hot_i[2]; - assign data_masked[158] = data_i[158] & sel_one_hot_i[2]; - assign data_masked[157] = data_i[157] & sel_one_hot_i[2]; - assign data_masked[156] = data_i[156] & sel_one_hot_i[2]; - assign data_masked[155] = data_i[155] & sel_one_hot_i[2]; - assign data_masked[154] = data_i[154] & sel_one_hot_i[2]; - assign data_masked[153] = data_i[153] & sel_one_hot_i[2]; - assign data_masked[152] = data_i[152] & sel_one_hot_i[2]; - assign data_o[0] = N0 | data_masked[0]; - assign N0 = data_masked[152] | data_masked[76]; - assign data_o[1] = N1 | data_masked[1]; - assign N1 = data_masked[153] | data_masked[77]; - assign data_o[2] = N2 | data_masked[2]; - assign N2 = data_masked[154] | data_masked[78]; - assign data_o[3] = N3 | data_masked[3]; - assign N3 = data_masked[155] | data_masked[79]; - assign data_o[4] = N4 | data_masked[4]; - assign N4 = data_masked[156] | data_masked[80]; - assign data_o[5] = N5 | data_masked[5]; - assign N5 = data_masked[157] | data_masked[81]; - assign data_o[6] = N6 | data_masked[6]; - assign N6 = data_masked[158] | data_masked[82]; - assign data_o[7] = N7 | data_masked[7]; - assign N7 = data_masked[159] | data_masked[83]; - assign data_o[8] = N8 | data_masked[8]; - assign N8 = data_masked[160] | data_masked[84]; - assign data_o[9] = N9 | data_masked[9]; - assign N9 = data_masked[161] | data_masked[85]; - assign data_o[10] = N10 | data_masked[10]; - assign N10 = data_masked[162] | data_masked[86]; - assign data_o[11] = N11 | data_masked[11]; - assign N11 = data_masked[163] | data_masked[87]; - assign data_o[12] = N12 | data_masked[12]; - assign N12 = data_masked[164] | data_masked[88]; - assign data_o[13] = N13 | data_masked[13]; - assign N13 = data_masked[165] | data_masked[89]; - assign data_o[14] = N14 | data_masked[14]; - assign N14 = data_masked[166] | data_masked[90]; - assign data_o[15] = N15 | data_masked[15]; - assign N15 = data_masked[167] | data_masked[91]; - assign data_o[16] = N16 | data_masked[16]; - assign N16 = data_masked[168] | data_masked[92]; - assign data_o[17] = N17 | data_masked[17]; - assign N17 = data_masked[169] | data_masked[93]; - assign data_o[18] = N18 | data_masked[18]; - assign N18 = data_masked[170] | data_masked[94]; - assign data_o[19] = N19 | data_masked[19]; - assign N19 = data_masked[171] | data_masked[95]; - assign data_o[20] = N20 | data_masked[20]; - assign N20 = data_masked[172] | data_masked[96]; - assign data_o[21] = N21 | data_masked[21]; - assign N21 = data_masked[173] | data_masked[97]; - assign data_o[22] = N22 | data_masked[22]; - assign N22 = data_masked[174] | data_masked[98]; - assign data_o[23] = N23 | data_masked[23]; - assign N23 = data_masked[175] | data_masked[99]; - assign data_o[24] = N24 | data_masked[24]; - assign N24 = data_masked[176] | data_masked[100]; - assign data_o[25] = N25 | data_masked[25]; - assign N25 = data_masked[177] | data_masked[101]; - assign data_o[26] = N26 | data_masked[26]; - assign N26 = data_masked[178] | data_masked[102]; - assign data_o[27] = N27 | data_masked[27]; - assign N27 = data_masked[179] | data_masked[103]; - assign data_o[28] = N28 | data_masked[28]; - assign N28 = data_masked[180] | data_masked[104]; - assign data_o[29] = N29 | data_masked[29]; - assign N29 = data_masked[181] | data_masked[105]; - assign data_o[30] = N30 | data_masked[30]; - assign N30 = data_masked[182] | data_masked[106]; - assign data_o[31] = N31 | data_masked[31]; - assign N31 = data_masked[183] | data_masked[107]; - assign data_o[32] = N32 | data_masked[32]; - assign N32 = data_masked[184] | data_masked[108]; - assign data_o[33] = N33 | data_masked[33]; - assign N33 = data_masked[185] | data_masked[109]; - assign data_o[34] = N34 | data_masked[34]; - assign N34 = data_masked[186] | data_masked[110]; - assign data_o[35] = N35 | data_masked[35]; - assign N35 = data_masked[187] | data_masked[111]; - assign data_o[36] = N36 | data_masked[36]; - assign N36 = data_masked[188] | data_masked[112]; - assign data_o[37] = N37 | data_masked[37]; - assign N37 = data_masked[189] | data_masked[113]; - assign data_o[38] = N38 | data_masked[38]; - assign N38 = data_masked[190] | data_masked[114]; - assign data_o[39] = N39 | data_masked[39]; - assign N39 = data_masked[191] | data_masked[115]; - assign data_o[40] = N40 | data_masked[40]; - assign N40 = data_masked[192] | data_masked[116]; - assign data_o[41] = N41 | data_masked[41]; - assign N41 = data_masked[193] | data_masked[117]; - assign data_o[42] = N42 | data_masked[42]; - assign N42 = data_masked[194] | data_masked[118]; - assign data_o[43] = N43 | data_masked[43]; - assign N43 = data_masked[195] | data_masked[119]; - assign data_o[44] = N44 | data_masked[44]; - assign N44 = data_masked[196] | data_masked[120]; - assign data_o[45] = N45 | data_masked[45]; - assign N45 = data_masked[197] | data_masked[121]; - assign data_o[46] = N46 | data_masked[46]; - assign N46 = data_masked[198] | data_masked[122]; - assign data_o[47] = N47 | data_masked[47]; - assign N47 = data_masked[199] | data_masked[123]; - assign data_o[48] = N48 | data_masked[48]; - assign N48 = data_masked[200] | data_masked[124]; - assign data_o[49] = N49 | data_masked[49]; - assign N49 = data_masked[201] | data_masked[125]; - assign data_o[50] = N50 | data_masked[50]; - assign N50 = data_masked[202] | data_masked[126]; - assign data_o[51] = N51 | data_masked[51]; - assign N51 = data_masked[203] | data_masked[127]; - assign data_o[52] = N52 | data_masked[52]; - assign N52 = data_masked[204] | data_masked[128]; - assign data_o[53] = N53 | data_masked[53]; - assign N53 = data_masked[205] | data_masked[129]; - assign data_o[54] = N54 | data_masked[54]; - assign N54 = data_masked[206] | data_masked[130]; - assign data_o[55] = N55 | data_masked[55]; - assign N55 = data_masked[207] | data_masked[131]; - assign data_o[56] = N56 | data_masked[56]; - assign N56 = data_masked[208] | data_masked[132]; - assign data_o[57] = N57 | data_masked[57]; - assign N57 = data_masked[209] | data_masked[133]; - assign data_o[58] = N58 | data_masked[58]; - assign N58 = data_masked[210] | data_masked[134]; - assign data_o[59] = N59 | data_masked[59]; - assign N59 = data_masked[211] | data_masked[135]; - assign data_o[60] = N60 | data_masked[60]; - assign N60 = data_masked[212] | data_masked[136]; - assign data_o[61] = N61 | data_masked[61]; - assign N61 = data_masked[213] | data_masked[137]; - assign data_o[62] = N62 | data_masked[62]; - assign N62 = data_masked[214] | data_masked[138]; - assign data_o[63] = N63 | data_masked[63]; - assign N63 = data_masked[215] | data_masked[139]; - assign data_o[64] = N64 | data_masked[64]; - assign N64 = data_masked[216] | data_masked[140]; - assign data_o[65] = N65 | data_masked[65]; - assign N65 = data_masked[217] | data_masked[141]; - assign data_o[66] = N66 | data_masked[66]; - assign N66 = data_masked[218] | data_masked[142]; - assign data_o[67] = N67 | data_masked[67]; - assign N67 = data_masked[219] | data_masked[143]; - assign data_o[68] = N68 | data_masked[68]; - assign N68 = data_masked[220] | data_masked[144]; - assign data_o[69] = N69 | data_masked[69]; - assign N69 = data_masked[221] | data_masked[145]; - assign data_o[70] = N70 | data_masked[70]; - assign N70 = data_masked[222] | data_masked[146]; - assign data_o[71] = N71 | data_masked[71]; - assign N71 = data_masked[223] | data_masked[147]; - assign data_o[72] = N72 | data_masked[72]; - assign N72 = data_masked[224] | data_masked[148]; - assign data_o[73] = N73 | data_masked[73]; - assign N73 = data_masked[225] | data_masked[149]; - assign data_o[74] = N74 | data_masked[74]; - assign N74 = data_masked[226] | data_masked[150]; - assign data_o[75] = N75 | data_masked[75]; - assign N75 = data_masked[227] | data_masked[151]; - -endmodule - - - -module bsg_mux_one_hot_width_p76_els_p5 -( - data_i, - sel_one_hot_i, - data_o -); - - input [379:0] data_i; - input [4:0] sel_one_hot_i; - output [75:0] data_o; - wire [75:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41, - N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61, - N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81, - N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101, - N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117, - N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133, - N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149, - N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165, - N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181, - N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197, - N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213, - N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227; - wire [379:0] data_masked; - assign data_masked[75] = data_i[75] & sel_one_hot_i[0]; - assign data_masked[74] = data_i[74] & sel_one_hot_i[0]; - assign data_masked[73] = data_i[73] & sel_one_hot_i[0]; - assign data_masked[72] = data_i[72] & sel_one_hot_i[0]; - assign data_masked[71] = data_i[71] & sel_one_hot_i[0]; - assign data_masked[70] = data_i[70] & sel_one_hot_i[0]; - assign data_masked[69] = data_i[69] & sel_one_hot_i[0]; - assign data_masked[68] = data_i[68] & sel_one_hot_i[0]; - assign data_masked[67] = data_i[67] & sel_one_hot_i[0]; - assign data_masked[66] = data_i[66] & sel_one_hot_i[0]; - assign data_masked[65] = data_i[65] & sel_one_hot_i[0]; - assign data_masked[64] = data_i[64] & sel_one_hot_i[0]; - assign data_masked[63] = data_i[63] & sel_one_hot_i[0]; - assign data_masked[62] = data_i[62] & sel_one_hot_i[0]; - assign data_masked[61] = data_i[61] & sel_one_hot_i[0]; - assign data_masked[60] = data_i[60] & sel_one_hot_i[0]; - assign data_masked[59] = data_i[59] & sel_one_hot_i[0]; - assign data_masked[58] = data_i[58] & sel_one_hot_i[0]; - assign data_masked[57] = data_i[57] & sel_one_hot_i[0]; - assign data_masked[56] = data_i[56] & sel_one_hot_i[0]; - assign data_masked[55] = data_i[55] & sel_one_hot_i[0]; - assign data_masked[54] = data_i[54] & sel_one_hot_i[0]; - assign data_masked[53] = data_i[53] & sel_one_hot_i[0]; - assign data_masked[52] = data_i[52] & sel_one_hot_i[0]; - assign data_masked[51] = data_i[51] & sel_one_hot_i[0]; - assign data_masked[50] = data_i[50] & sel_one_hot_i[0]; - assign data_masked[49] = data_i[49] & sel_one_hot_i[0]; - assign data_masked[48] = data_i[48] & sel_one_hot_i[0]; - assign data_masked[47] = data_i[47] & sel_one_hot_i[0]; - assign data_masked[46] = data_i[46] & sel_one_hot_i[0]; - assign data_masked[45] = data_i[45] & sel_one_hot_i[0]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[0]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[0]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[0]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[0]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[0]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[0]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[0]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[0]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[0]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[0]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[0]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[0]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[0]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[0]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[0]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[0]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[0]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[0]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[0]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[0]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[0]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[0]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[0]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[0]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[0]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[0]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[0]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[0]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[0]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[0]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[0]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[0]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[0]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[151] = data_i[151] & sel_one_hot_i[1]; - assign data_masked[150] = data_i[150] & sel_one_hot_i[1]; - assign data_masked[149] = data_i[149] & sel_one_hot_i[1]; - assign data_masked[148] = data_i[148] & sel_one_hot_i[1]; - assign data_masked[147] = data_i[147] & sel_one_hot_i[1]; - assign data_masked[146] = data_i[146] & sel_one_hot_i[1]; - assign data_masked[145] = data_i[145] & sel_one_hot_i[1]; - assign data_masked[144] = data_i[144] & sel_one_hot_i[1]; - assign data_masked[143] = data_i[143] & sel_one_hot_i[1]; - assign data_masked[142] = data_i[142] & sel_one_hot_i[1]; - assign data_masked[141] = data_i[141] & sel_one_hot_i[1]; - assign data_masked[140] = data_i[140] & sel_one_hot_i[1]; - assign data_masked[139] = data_i[139] & sel_one_hot_i[1]; - assign data_masked[138] = data_i[138] & sel_one_hot_i[1]; - assign data_masked[137] = data_i[137] & sel_one_hot_i[1]; - assign data_masked[136] = data_i[136] & sel_one_hot_i[1]; - assign data_masked[135] = data_i[135] & sel_one_hot_i[1]; - assign data_masked[134] = data_i[134] & sel_one_hot_i[1]; - assign data_masked[133] = data_i[133] & sel_one_hot_i[1]; - assign data_masked[132] = data_i[132] & sel_one_hot_i[1]; - assign data_masked[131] = data_i[131] & sel_one_hot_i[1]; - assign data_masked[130] = data_i[130] & sel_one_hot_i[1]; - assign data_masked[129] = data_i[129] & sel_one_hot_i[1]; - assign data_masked[128] = data_i[128] & sel_one_hot_i[1]; - assign data_masked[127] = data_i[127] & sel_one_hot_i[1]; - assign data_masked[126] = data_i[126] & sel_one_hot_i[1]; - assign data_masked[125] = data_i[125] & sel_one_hot_i[1]; - assign data_masked[124] = data_i[124] & sel_one_hot_i[1]; - assign data_masked[123] = data_i[123] & sel_one_hot_i[1]; - assign data_masked[122] = data_i[122] & sel_one_hot_i[1]; - assign data_masked[121] = data_i[121] & sel_one_hot_i[1]; - assign data_masked[120] = data_i[120] & sel_one_hot_i[1]; - assign data_masked[119] = data_i[119] & sel_one_hot_i[1]; - assign data_masked[118] = data_i[118] & sel_one_hot_i[1]; - assign data_masked[117] = data_i[117] & sel_one_hot_i[1]; - assign data_masked[116] = data_i[116] & sel_one_hot_i[1]; - assign data_masked[115] = data_i[115] & sel_one_hot_i[1]; - assign data_masked[114] = data_i[114] & sel_one_hot_i[1]; - assign data_masked[113] = data_i[113] & sel_one_hot_i[1]; - assign data_masked[112] = data_i[112] & sel_one_hot_i[1]; - assign data_masked[111] = data_i[111] & sel_one_hot_i[1]; - assign data_masked[110] = data_i[110] & sel_one_hot_i[1]; - assign data_masked[109] = data_i[109] & sel_one_hot_i[1]; - assign data_masked[108] = data_i[108] & sel_one_hot_i[1]; - assign data_masked[107] = data_i[107] & sel_one_hot_i[1]; - assign data_masked[106] = data_i[106] & sel_one_hot_i[1]; - assign data_masked[105] = data_i[105] & sel_one_hot_i[1]; - assign data_masked[104] = data_i[104] & sel_one_hot_i[1]; - assign data_masked[103] = data_i[103] & sel_one_hot_i[1]; - assign data_masked[102] = data_i[102] & sel_one_hot_i[1]; - assign data_masked[101] = data_i[101] & sel_one_hot_i[1]; - assign data_masked[100] = data_i[100] & sel_one_hot_i[1]; - assign data_masked[99] = data_i[99] & sel_one_hot_i[1]; - assign data_masked[98] = data_i[98] & sel_one_hot_i[1]; - assign data_masked[97] = data_i[97] & sel_one_hot_i[1]; - assign data_masked[96] = data_i[96] & sel_one_hot_i[1]; - assign data_masked[95] = data_i[95] & sel_one_hot_i[1]; - assign data_masked[94] = data_i[94] & sel_one_hot_i[1]; - assign data_masked[93] = data_i[93] & sel_one_hot_i[1]; - assign data_masked[92] = data_i[92] & sel_one_hot_i[1]; - assign data_masked[91] = data_i[91] & sel_one_hot_i[1]; - assign data_masked[90] = data_i[90] & sel_one_hot_i[1]; - assign data_masked[89] = data_i[89] & sel_one_hot_i[1]; - assign data_masked[88] = data_i[88] & sel_one_hot_i[1]; - assign data_masked[87] = data_i[87] & sel_one_hot_i[1]; - assign data_masked[86] = data_i[86] & sel_one_hot_i[1]; - assign data_masked[85] = data_i[85] & sel_one_hot_i[1]; - assign data_masked[84] = data_i[84] & sel_one_hot_i[1]; - assign data_masked[83] = data_i[83] & sel_one_hot_i[1]; - assign data_masked[82] = data_i[82] & sel_one_hot_i[1]; - assign data_masked[81] = data_i[81] & sel_one_hot_i[1]; - assign data_masked[80] = data_i[80] & sel_one_hot_i[1]; - assign data_masked[79] = data_i[79] & sel_one_hot_i[1]; - assign data_masked[78] = data_i[78] & sel_one_hot_i[1]; - assign data_masked[77] = data_i[77] & sel_one_hot_i[1]; - assign data_masked[76] = data_i[76] & sel_one_hot_i[1]; - assign data_masked[227] = data_i[227] & sel_one_hot_i[2]; - assign data_masked[226] = data_i[226] & sel_one_hot_i[2]; - assign data_masked[225] = data_i[225] & sel_one_hot_i[2]; - assign data_masked[224] = data_i[224] & sel_one_hot_i[2]; - assign data_masked[223] = data_i[223] & sel_one_hot_i[2]; - assign data_masked[222] = data_i[222] & sel_one_hot_i[2]; - assign data_masked[221] = data_i[221] & sel_one_hot_i[2]; - assign data_masked[220] = data_i[220] & sel_one_hot_i[2]; - assign data_masked[219] = data_i[219] & sel_one_hot_i[2]; - assign data_masked[218] = data_i[218] & sel_one_hot_i[2]; - assign data_masked[217] = data_i[217] & sel_one_hot_i[2]; - assign data_masked[216] = data_i[216] & sel_one_hot_i[2]; - assign data_masked[215] = data_i[215] & sel_one_hot_i[2]; - assign data_masked[214] = data_i[214] & sel_one_hot_i[2]; - assign data_masked[213] = data_i[213] & sel_one_hot_i[2]; - assign data_masked[212] = data_i[212] & sel_one_hot_i[2]; - assign data_masked[211] = data_i[211] & sel_one_hot_i[2]; - assign data_masked[210] = data_i[210] & sel_one_hot_i[2]; - assign data_masked[209] = data_i[209] & sel_one_hot_i[2]; - assign data_masked[208] = data_i[208] & sel_one_hot_i[2]; - assign data_masked[207] = data_i[207] & sel_one_hot_i[2]; - assign data_masked[206] = data_i[206] & sel_one_hot_i[2]; - assign data_masked[205] = data_i[205] & sel_one_hot_i[2]; - assign data_masked[204] = data_i[204] & sel_one_hot_i[2]; - assign data_masked[203] = data_i[203] & sel_one_hot_i[2]; - assign data_masked[202] = data_i[202] & sel_one_hot_i[2]; - assign data_masked[201] = data_i[201] & sel_one_hot_i[2]; - assign data_masked[200] = data_i[200] & sel_one_hot_i[2]; - assign data_masked[199] = data_i[199] & sel_one_hot_i[2]; - assign data_masked[198] = data_i[198] & sel_one_hot_i[2]; - assign data_masked[197] = data_i[197] & sel_one_hot_i[2]; - assign data_masked[196] = data_i[196] & sel_one_hot_i[2]; - assign data_masked[195] = data_i[195] & sel_one_hot_i[2]; - assign data_masked[194] = data_i[194] & sel_one_hot_i[2]; - assign data_masked[193] = data_i[193] & sel_one_hot_i[2]; - assign data_masked[192] = data_i[192] & sel_one_hot_i[2]; - assign data_masked[191] = data_i[191] & sel_one_hot_i[2]; - assign data_masked[190] = data_i[190] & sel_one_hot_i[2]; - assign data_masked[189] = data_i[189] & sel_one_hot_i[2]; - assign data_masked[188] = data_i[188] & sel_one_hot_i[2]; - assign data_masked[187] = data_i[187] & sel_one_hot_i[2]; - assign data_masked[186] = data_i[186] & sel_one_hot_i[2]; - assign data_masked[185] = data_i[185] & sel_one_hot_i[2]; - assign data_masked[184] = data_i[184] & sel_one_hot_i[2]; - assign data_masked[183] = data_i[183] & sel_one_hot_i[2]; - assign data_masked[182] = data_i[182] & sel_one_hot_i[2]; - assign data_masked[181] = data_i[181] & sel_one_hot_i[2]; - assign data_masked[180] = data_i[180] & sel_one_hot_i[2]; - assign data_masked[179] = data_i[179] & sel_one_hot_i[2]; - assign data_masked[178] = data_i[178] & sel_one_hot_i[2]; - assign data_masked[177] = data_i[177] & sel_one_hot_i[2]; - assign data_masked[176] = data_i[176] & sel_one_hot_i[2]; - assign data_masked[175] = data_i[175] & sel_one_hot_i[2]; - assign data_masked[174] = data_i[174] & sel_one_hot_i[2]; - assign data_masked[173] = data_i[173] & sel_one_hot_i[2]; - assign data_masked[172] = data_i[172] & sel_one_hot_i[2]; - assign data_masked[171] = data_i[171] & sel_one_hot_i[2]; - assign data_masked[170] = data_i[170] & sel_one_hot_i[2]; - assign data_masked[169] = data_i[169] & sel_one_hot_i[2]; - assign data_masked[168] = data_i[168] & sel_one_hot_i[2]; - assign data_masked[167] = data_i[167] & sel_one_hot_i[2]; - assign data_masked[166] = data_i[166] & sel_one_hot_i[2]; - assign data_masked[165] = data_i[165] & sel_one_hot_i[2]; - assign data_masked[164] = data_i[164] & sel_one_hot_i[2]; - assign data_masked[163] = data_i[163] & sel_one_hot_i[2]; - assign data_masked[162] = data_i[162] & sel_one_hot_i[2]; - assign data_masked[161] = data_i[161] & sel_one_hot_i[2]; - assign data_masked[160] = data_i[160] & sel_one_hot_i[2]; - assign data_masked[159] = data_i[159] & sel_one_hot_i[2]; - assign data_masked[158] = data_i[158] & sel_one_hot_i[2]; - assign data_masked[157] = data_i[157] & sel_one_hot_i[2]; - assign data_masked[156] = data_i[156] & sel_one_hot_i[2]; - assign data_masked[155] = data_i[155] & sel_one_hot_i[2]; - assign data_masked[154] = data_i[154] & sel_one_hot_i[2]; - assign data_masked[153] = data_i[153] & sel_one_hot_i[2]; - assign data_masked[152] = data_i[152] & sel_one_hot_i[2]; - assign data_masked[303] = data_i[303] & sel_one_hot_i[3]; - assign data_masked[302] = data_i[302] & sel_one_hot_i[3]; - assign data_masked[301] = data_i[301] & sel_one_hot_i[3]; - assign data_masked[300] = data_i[300] & sel_one_hot_i[3]; - assign data_masked[299] = data_i[299] & sel_one_hot_i[3]; - assign data_masked[298] = data_i[298] & sel_one_hot_i[3]; - assign data_masked[297] = data_i[297] & sel_one_hot_i[3]; - assign data_masked[296] = data_i[296] & sel_one_hot_i[3]; - assign data_masked[295] = data_i[295] & sel_one_hot_i[3]; - assign data_masked[294] = data_i[294] & sel_one_hot_i[3]; - assign data_masked[293] = data_i[293] & sel_one_hot_i[3]; - assign data_masked[292] = data_i[292] & sel_one_hot_i[3]; - assign data_masked[291] = data_i[291] & sel_one_hot_i[3]; - assign data_masked[290] = data_i[290] & sel_one_hot_i[3]; - assign data_masked[289] = data_i[289] & sel_one_hot_i[3]; - assign data_masked[288] = data_i[288] & sel_one_hot_i[3]; - assign data_masked[287] = data_i[287] & sel_one_hot_i[3]; - assign data_masked[286] = data_i[286] & sel_one_hot_i[3]; - assign data_masked[285] = data_i[285] & sel_one_hot_i[3]; - assign data_masked[284] = data_i[284] & sel_one_hot_i[3]; - assign data_masked[283] = data_i[283] & sel_one_hot_i[3]; - assign data_masked[282] = data_i[282] & sel_one_hot_i[3]; - assign data_masked[281] = data_i[281] & sel_one_hot_i[3]; - assign data_masked[280] = data_i[280] & sel_one_hot_i[3]; - assign data_masked[279] = data_i[279] & sel_one_hot_i[3]; - assign data_masked[278] = data_i[278] & sel_one_hot_i[3]; - assign data_masked[277] = data_i[277] & sel_one_hot_i[3]; - assign data_masked[276] = data_i[276] & sel_one_hot_i[3]; - assign data_masked[275] = data_i[275] & sel_one_hot_i[3]; - assign data_masked[274] = data_i[274] & sel_one_hot_i[3]; - assign data_masked[273] = data_i[273] & sel_one_hot_i[3]; - assign data_masked[272] = data_i[272] & sel_one_hot_i[3]; - assign data_masked[271] = data_i[271] & sel_one_hot_i[3]; - assign data_masked[270] = data_i[270] & sel_one_hot_i[3]; - assign data_masked[269] = data_i[269] & sel_one_hot_i[3]; - assign data_masked[268] = data_i[268] & sel_one_hot_i[3]; - assign data_masked[267] = data_i[267] & sel_one_hot_i[3]; - assign data_masked[266] = data_i[266] & sel_one_hot_i[3]; - assign data_masked[265] = data_i[265] & sel_one_hot_i[3]; - assign data_masked[264] = data_i[264] & sel_one_hot_i[3]; - assign data_masked[263] = data_i[263] & sel_one_hot_i[3]; - assign data_masked[262] = data_i[262] & sel_one_hot_i[3]; - assign data_masked[261] = data_i[261] & sel_one_hot_i[3]; - assign data_masked[260] = data_i[260] & sel_one_hot_i[3]; - assign data_masked[259] = data_i[259] & sel_one_hot_i[3]; - assign data_masked[258] = data_i[258] & sel_one_hot_i[3]; - assign data_masked[257] = data_i[257] & sel_one_hot_i[3]; - assign data_masked[256] = data_i[256] & sel_one_hot_i[3]; - assign data_masked[255] = data_i[255] & sel_one_hot_i[3]; - assign data_masked[254] = data_i[254] & sel_one_hot_i[3]; - assign data_masked[253] = data_i[253] & sel_one_hot_i[3]; - assign data_masked[252] = data_i[252] & sel_one_hot_i[3]; - assign data_masked[251] = data_i[251] & sel_one_hot_i[3]; - assign data_masked[250] = data_i[250] & sel_one_hot_i[3]; - assign data_masked[249] = data_i[249] & sel_one_hot_i[3]; - assign data_masked[248] = data_i[248] & sel_one_hot_i[3]; - assign data_masked[247] = data_i[247] & sel_one_hot_i[3]; - assign data_masked[246] = data_i[246] & sel_one_hot_i[3]; - assign data_masked[245] = data_i[245] & sel_one_hot_i[3]; - assign data_masked[244] = data_i[244] & sel_one_hot_i[3]; - assign data_masked[243] = data_i[243] & sel_one_hot_i[3]; - assign data_masked[242] = data_i[242] & sel_one_hot_i[3]; - assign data_masked[241] = data_i[241] & sel_one_hot_i[3]; - assign data_masked[240] = data_i[240] & sel_one_hot_i[3]; - assign data_masked[239] = data_i[239] & sel_one_hot_i[3]; - assign data_masked[238] = data_i[238] & sel_one_hot_i[3]; - assign data_masked[237] = data_i[237] & sel_one_hot_i[3]; - assign data_masked[236] = data_i[236] & sel_one_hot_i[3]; - assign data_masked[235] = data_i[235] & sel_one_hot_i[3]; - assign data_masked[234] = data_i[234] & sel_one_hot_i[3]; - assign data_masked[233] = data_i[233] & sel_one_hot_i[3]; - assign data_masked[232] = data_i[232] & sel_one_hot_i[3]; - assign data_masked[231] = data_i[231] & sel_one_hot_i[3]; - assign data_masked[230] = data_i[230] & sel_one_hot_i[3]; - assign data_masked[229] = data_i[229] & sel_one_hot_i[3]; - assign data_masked[228] = data_i[228] & sel_one_hot_i[3]; - assign data_masked[379] = data_i[379] & sel_one_hot_i[4]; - assign data_masked[378] = data_i[378] & sel_one_hot_i[4]; - assign data_masked[377] = data_i[377] & sel_one_hot_i[4]; - assign data_masked[376] = data_i[376] & sel_one_hot_i[4]; - assign data_masked[375] = data_i[375] & sel_one_hot_i[4]; - assign data_masked[374] = data_i[374] & sel_one_hot_i[4]; - assign data_masked[373] = data_i[373] & sel_one_hot_i[4]; - assign data_masked[372] = data_i[372] & sel_one_hot_i[4]; - assign data_masked[371] = data_i[371] & sel_one_hot_i[4]; - assign data_masked[370] = data_i[370] & sel_one_hot_i[4]; - assign data_masked[369] = data_i[369] & sel_one_hot_i[4]; - assign data_masked[368] = data_i[368] & sel_one_hot_i[4]; - assign data_masked[367] = data_i[367] & sel_one_hot_i[4]; - assign data_masked[366] = data_i[366] & sel_one_hot_i[4]; - assign data_masked[365] = data_i[365] & sel_one_hot_i[4]; - assign data_masked[364] = data_i[364] & sel_one_hot_i[4]; - assign data_masked[363] = data_i[363] & sel_one_hot_i[4]; - assign data_masked[362] = data_i[362] & sel_one_hot_i[4]; - assign data_masked[361] = data_i[361] & sel_one_hot_i[4]; - assign data_masked[360] = data_i[360] & sel_one_hot_i[4]; - assign data_masked[359] = data_i[359] & sel_one_hot_i[4]; - assign data_masked[358] = data_i[358] & sel_one_hot_i[4]; - assign data_masked[357] = data_i[357] & sel_one_hot_i[4]; - assign data_masked[356] = data_i[356] & sel_one_hot_i[4]; - assign data_masked[355] = data_i[355] & sel_one_hot_i[4]; - assign data_masked[354] = data_i[354] & sel_one_hot_i[4]; - assign data_masked[353] = data_i[353] & sel_one_hot_i[4]; - assign data_masked[352] = data_i[352] & sel_one_hot_i[4]; - assign data_masked[351] = data_i[351] & sel_one_hot_i[4]; - assign data_masked[350] = data_i[350] & sel_one_hot_i[4]; - assign data_masked[349] = data_i[349] & sel_one_hot_i[4]; - assign data_masked[348] = data_i[348] & sel_one_hot_i[4]; - assign data_masked[347] = data_i[347] & sel_one_hot_i[4]; - assign data_masked[346] = data_i[346] & sel_one_hot_i[4]; - assign data_masked[345] = data_i[345] & sel_one_hot_i[4]; - assign data_masked[344] = data_i[344] & sel_one_hot_i[4]; - assign data_masked[343] = data_i[343] & sel_one_hot_i[4]; - assign data_masked[342] = data_i[342] & sel_one_hot_i[4]; - assign data_masked[341] = data_i[341] & sel_one_hot_i[4]; - assign data_masked[340] = data_i[340] & sel_one_hot_i[4]; - assign data_masked[339] = data_i[339] & sel_one_hot_i[4]; - assign data_masked[338] = data_i[338] & sel_one_hot_i[4]; - assign data_masked[337] = data_i[337] & sel_one_hot_i[4]; - assign data_masked[336] = data_i[336] & sel_one_hot_i[4]; - assign data_masked[335] = data_i[335] & sel_one_hot_i[4]; - assign data_masked[334] = data_i[334] & sel_one_hot_i[4]; - assign data_masked[333] = data_i[333] & sel_one_hot_i[4]; - assign data_masked[332] = data_i[332] & sel_one_hot_i[4]; - assign data_masked[331] = data_i[331] & sel_one_hot_i[4]; - assign data_masked[330] = data_i[330] & sel_one_hot_i[4]; - assign data_masked[329] = data_i[329] & sel_one_hot_i[4]; - assign data_masked[328] = data_i[328] & sel_one_hot_i[4]; - assign data_masked[327] = data_i[327] & sel_one_hot_i[4]; - assign data_masked[326] = data_i[326] & sel_one_hot_i[4]; - assign data_masked[325] = data_i[325] & sel_one_hot_i[4]; - assign data_masked[324] = data_i[324] & sel_one_hot_i[4]; - assign data_masked[323] = data_i[323] & sel_one_hot_i[4]; - assign data_masked[322] = data_i[322] & sel_one_hot_i[4]; - assign data_masked[321] = data_i[321] & sel_one_hot_i[4]; - assign data_masked[320] = data_i[320] & sel_one_hot_i[4]; - assign data_masked[319] = data_i[319] & sel_one_hot_i[4]; - assign data_masked[318] = data_i[318] & sel_one_hot_i[4]; - assign data_masked[317] = data_i[317] & sel_one_hot_i[4]; - assign data_masked[316] = data_i[316] & sel_one_hot_i[4]; - assign data_masked[315] = data_i[315] & sel_one_hot_i[4]; - assign data_masked[314] = data_i[314] & sel_one_hot_i[4]; - assign data_masked[313] = data_i[313] & sel_one_hot_i[4]; - assign data_masked[312] = data_i[312] & sel_one_hot_i[4]; - assign data_masked[311] = data_i[311] & sel_one_hot_i[4]; - assign data_masked[310] = data_i[310] & sel_one_hot_i[4]; - assign data_masked[309] = data_i[309] & sel_one_hot_i[4]; - assign data_masked[308] = data_i[308] & sel_one_hot_i[4]; - assign data_masked[307] = data_i[307] & sel_one_hot_i[4]; - assign data_masked[306] = data_i[306] & sel_one_hot_i[4]; - assign data_masked[305] = data_i[305] & sel_one_hot_i[4]; - assign data_masked[304] = data_i[304] & sel_one_hot_i[4]; - assign data_o[0] = N2 | data_masked[0]; - assign N2 = N1 | data_masked[76]; - assign N1 = N0 | data_masked[152]; - assign N0 = data_masked[304] | data_masked[228]; - assign data_o[1] = N5 | data_masked[1]; - assign N5 = N4 | data_masked[77]; - assign N4 = N3 | data_masked[153]; - assign N3 = data_masked[305] | data_masked[229]; - assign data_o[2] = N8 | data_masked[2]; - assign N8 = N7 | data_masked[78]; - assign N7 = N6 | data_masked[154]; - assign N6 = data_masked[306] | data_masked[230]; - assign data_o[3] = N11 | data_masked[3]; - assign N11 = N10 | data_masked[79]; - assign N10 = N9 | data_masked[155]; - assign N9 = data_masked[307] | data_masked[231]; - assign data_o[4] = N14 | data_masked[4]; - assign N14 = N13 | data_masked[80]; - assign N13 = N12 | data_masked[156]; - assign N12 = data_masked[308] | data_masked[232]; - assign data_o[5] = N17 | data_masked[5]; - assign N17 = N16 | data_masked[81]; - assign N16 = N15 | data_masked[157]; - assign N15 = data_masked[309] | data_masked[233]; - assign data_o[6] = N20 | data_masked[6]; - assign N20 = N19 | data_masked[82]; - assign N19 = N18 | data_masked[158]; - assign N18 = data_masked[310] | data_masked[234]; - assign data_o[7] = N23 | data_masked[7]; - assign N23 = N22 | data_masked[83]; - assign N22 = N21 | data_masked[159]; - assign N21 = data_masked[311] | data_masked[235]; - assign data_o[8] = N26 | data_masked[8]; - assign N26 = N25 | data_masked[84]; - assign N25 = N24 | data_masked[160]; - assign N24 = data_masked[312] | data_masked[236]; - assign data_o[9] = N29 | data_masked[9]; - assign N29 = N28 | data_masked[85]; - assign N28 = N27 | data_masked[161]; - assign N27 = data_masked[313] | data_masked[237]; - assign data_o[10] = N32 | data_masked[10]; - assign N32 = N31 | data_masked[86]; - assign N31 = N30 | data_masked[162]; - assign N30 = data_masked[314] | data_masked[238]; - assign data_o[11] = N35 | data_masked[11]; - assign N35 = N34 | data_masked[87]; - assign N34 = N33 | data_masked[163]; - assign N33 = data_masked[315] | data_masked[239]; - assign data_o[12] = N38 | data_masked[12]; - assign N38 = N37 | data_masked[88]; - assign N37 = N36 | data_masked[164]; - assign N36 = data_masked[316] | data_masked[240]; - assign data_o[13] = N41 | data_masked[13]; - assign N41 = N40 | data_masked[89]; - assign N40 = N39 | data_masked[165]; - assign N39 = data_masked[317] | data_masked[241]; - assign data_o[14] = N44 | data_masked[14]; - assign N44 = N43 | data_masked[90]; - assign N43 = N42 | data_masked[166]; - assign N42 = data_masked[318] | data_masked[242]; - assign data_o[15] = N47 | data_masked[15]; - assign N47 = N46 | data_masked[91]; - assign N46 = N45 | data_masked[167]; - assign N45 = data_masked[319] | data_masked[243]; - assign data_o[16] = N50 | data_masked[16]; - assign N50 = N49 | data_masked[92]; - assign N49 = N48 | data_masked[168]; - assign N48 = data_masked[320] | data_masked[244]; - assign data_o[17] = N53 | data_masked[17]; - assign N53 = N52 | data_masked[93]; - assign N52 = N51 | data_masked[169]; - assign N51 = data_masked[321] | data_masked[245]; - assign data_o[18] = N56 | data_masked[18]; - assign N56 = N55 | data_masked[94]; - assign N55 = N54 | data_masked[170]; - assign N54 = data_masked[322] | data_masked[246]; - assign data_o[19] = N59 | data_masked[19]; - assign N59 = N58 | data_masked[95]; - assign N58 = N57 | data_masked[171]; - assign N57 = data_masked[323] | data_masked[247]; - assign data_o[20] = N62 | data_masked[20]; - assign N62 = N61 | data_masked[96]; - assign N61 = N60 | data_masked[172]; - assign N60 = data_masked[324] | data_masked[248]; - assign data_o[21] = N65 | data_masked[21]; - assign N65 = N64 | data_masked[97]; - assign N64 = N63 | data_masked[173]; - assign N63 = data_masked[325] | data_masked[249]; - assign data_o[22] = N68 | data_masked[22]; - assign N68 = N67 | data_masked[98]; - assign N67 = N66 | data_masked[174]; - assign N66 = data_masked[326] | data_masked[250]; - assign data_o[23] = N71 | data_masked[23]; - assign N71 = N70 | data_masked[99]; - assign N70 = N69 | data_masked[175]; - assign N69 = data_masked[327] | data_masked[251]; - assign data_o[24] = N74 | data_masked[24]; - assign N74 = N73 | data_masked[100]; - assign N73 = N72 | data_masked[176]; - assign N72 = data_masked[328] | data_masked[252]; - assign data_o[25] = N77 | data_masked[25]; - assign N77 = N76 | data_masked[101]; - assign N76 = N75 | data_masked[177]; - assign N75 = data_masked[329] | data_masked[253]; - assign data_o[26] = N80 | data_masked[26]; - assign N80 = N79 | data_masked[102]; - assign N79 = N78 | data_masked[178]; - assign N78 = data_masked[330] | data_masked[254]; - assign data_o[27] = N83 | data_masked[27]; - assign N83 = N82 | data_masked[103]; - assign N82 = N81 | data_masked[179]; - assign N81 = data_masked[331] | data_masked[255]; - assign data_o[28] = N86 | data_masked[28]; - assign N86 = N85 | data_masked[104]; - assign N85 = N84 | data_masked[180]; - assign N84 = data_masked[332] | data_masked[256]; - assign data_o[29] = N89 | data_masked[29]; - assign N89 = N88 | data_masked[105]; - assign N88 = N87 | data_masked[181]; - assign N87 = data_masked[333] | data_masked[257]; - assign data_o[30] = N92 | data_masked[30]; - assign N92 = N91 | data_masked[106]; - assign N91 = N90 | data_masked[182]; - assign N90 = data_masked[334] | data_masked[258]; - assign data_o[31] = N95 | data_masked[31]; - assign N95 = N94 | data_masked[107]; - assign N94 = N93 | data_masked[183]; - assign N93 = data_masked[335] | data_masked[259]; - assign data_o[32] = N98 | data_masked[32]; - assign N98 = N97 | data_masked[108]; - assign N97 = N96 | data_masked[184]; - assign N96 = data_masked[336] | data_masked[260]; - assign data_o[33] = N101 | data_masked[33]; - assign N101 = N100 | data_masked[109]; - assign N100 = N99 | data_masked[185]; - assign N99 = data_masked[337] | data_masked[261]; - assign data_o[34] = N104 | data_masked[34]; - assign N104 = N103 | data_masked[110]; - assign N103 = N102 | data_masked[186]; - assign N102 = data_masked[338] | data_masked[262]; - assign data_o[35] = N107 | data_masked[35]; - assign N107 = N106 | data_masked[111]; - assign N106 = N105 | data_masked[187]; - assign N105 = data_masked[339] | data_masked[263]; - assign data_o[36] = N110 | data_masked[36]; - assign N110 = N109 | data_masked[112]; - assign N109 = N108 | data_masked[188]; - assign N108 = data_masked[340] | data_masked[264]; - assign data_o[37] = N113 | data_masked[37]; - assign N113 = N112 | data_masked[113]; - assign N112 = N111 | data_masked[189]; - assign N111 = data_masked[341] | data_masked[265]; - assign data_o[38] = N116 | data_masked[38]; - assign N116 = N115 | data_masked[114]; - assign N115 = N114 | data_masked[190]; - assign N114 = data_masked[342] | data_masked[266]; - assign data_o[39] = N119 | data_masked[39]; - assign N119 = N118 | data_masked[115]; - assign N118 = N117 | data_masked[191]; - assign N117 = data_masked[343] | data_masked[267]; - assign data_o[40] = N122 | data_masked[40]; - assign N122 = N121 | data_masked[116]; - assign N121 = N120 | data_masked[192]; - assign N120 = data_masked[344] | data_masked[268]; - assign data_o[41] = N125 | data_masked[41]; - assign N125 = N124 | data_masked[117]; - assign N124 = N123 | data_masked[193]; - assign N123 = data_masked[345] | data_masked[269]; - assign data_o[42] = N128 | data_masked[42]; - assign N128 = N127 | data_masked[118]; - assign N127 = N126 | data_masked[194]; - assign N126 = data_masked[346] | data_masked[270]; - assign data_o[43] = N131 | data_masked[43]; - assign N131 = N130 | data_masked[119]; - assign N130 = N129 | data_masked[195]; - assign N129 = data_masked[347] | data_masked[271]; - assign data_o[44] = N134 | data_masked[44]; - assign N134 = N133 | data_masked[120]; - assign N133 = N132 | data_masked[196]; - assign N132 = data_masked[348] | data_masked[272]; - assign data_o[45] = N137 | data_masked[45]; - assign N137 = N136 | data_masked[121]; - assign N136 = N135 | data_masked[197]; - assign N135 = data_masked[349] | data_masked[273]; - assign data_o[46] = N140 | data_masked[46]; - assign N140 = N139 | data_masked[122]; - assign N139 = N138 | data_masked[198]; - assign N138 = data_masked[350] | data_masked[274]; - assign data_o[47] = N143 | data_masked[47]; - assign N143 = N142 | data_masked[123]; - assign N142 = N141 | data_masked[199]; - assign N141 = data_masked[351] | data_masked[275]; - assign data_o[48] = N146 | data_masked[48]; - assign N146 = N145 | data_masked[124]; - assign N145 = N144 | data_masked[200]; - assign N144 = data_masked[352] | data_masked[276]; - assign data_o[49] = N149 | data_masked[49]; - assign N149 = N148 | data_masked[125]; - assign N148 = N147 | data_masked[201]; - assign N147 = data_masked[353] | data_masked[277]; - assign data_o[50] = N152 | data_masked[50]; - assign N152 = N151 | data_masked[126]; - assign N151 = N150 | data_masked[202]; - assign N150 = data_masked[354] | data_masked[278]; - assign data_o[51] = N155 | data_masked[51]; - assign N155 = N154 | data_masked[127]; - assign N154 = N153 | data_masked[203]; - assign N153 = data_masked[355] | data_masked[279]; - assign data_o[52] = N158 | data_masked[52]; - assign N158 = N157 | data_masked[128]; - assign N157 = N156 | data_masked[204]; - assign N156 = data_masked[356] | data_masked[280]; - assign data_o[53] = N161 | data_masked[53]; - assign N161 = N160 | data_masked[129]; - assign N160 = N159 | data_masked[205]; - assign N159 = data_masked[357] | data_masked[281]; - assign data_o[54] = N164 | data_masked[54]; - assign N164 = N163 | data_masked[130]; - assign N163 = N162 | data_masked[206]; - assign N162 = data_masked[358] | data_masked[282]; - assign data_o[55] = N167 | data_masked[55]; - assign N167 = N166 | data_masked[131]; - assign N166 = N165 | data_masked[207]; - assign N165 = data_masked[359] | data_masked[283]; - assign data_o[56] = N170 | data_masked[56]; - assign N170 = N169 | data_masked[132]; - assign N169 = N168 | data_masked[208]; - assign N168 = data_masked[360] | data_masked[284]; - assign data_o[57] = N173 | data_masked[57]; - assign N173 = N172 | data_masked[133]; - assign N172 = N171 | data_masked[209]; - assign N171 = data_masked[361] | data_masked[285]; - assign data_o[58] = N176 | data_masked[58]; - assign N176 = N175 | data_masked[134]; - assign N175 = N174 | data_masked[210]; - assign N174 = data_masked[362] | data_masked[286]; - assign data_o[59] = N179 | data_masked[59]; - assign N179 = N178 | data_masked[135]; - assign N178 = N177 | data_masked[211]; - assign N177 = data_masked[363] | data_masked[287]; - assign data_o[60] = N182 | data_masked[60]; - assign N182 = N181 | data_masked[136]; - assign N181 = N180 | data_masked[212]; - assign N180 = data_masked[364] | data_masked[288]; - assign data_o[61] = N185 | data_masked[61]; - assign N185 = N184 | data_masked[137]; - assign N184 = N183 | data_masked[213]; - assign N183 = data_masked[365] | data_masked[289]; - assign data_o[62] = N188 | data_masked[62]; - assign N188 = N187 | data_masked[138]; - assign N187 = N186 | data_masked[214]; - assign N186 = data_masked[366] | data_masked[290]; - assign data_o[63] = N191 | data_masked[63]; - assign N191 = N190 | data_masked[139]; - assign N190 = N189 | data_masked[215]; - assign N189 = data_masked[367] | data_masked[291]; - assign data_o[64] = N194 | data_masked[64]; - assign N194 = N193 | data_masked[140]; - assign N193 = N192 | data_masked[216]; - assign N192 = data_masked[368] | data_masked[292]; - assign data_o[65] = N197 | data_masked[65]; - assign N197 = N196 | data_masked[141]; - assign N196 = N195 | data_masked[217]; - assign N195 = data_masked[369] | data_masked[293]; - assign data_o[66] = N200 | data_masked[66]; - assign N200 = N199 | data_masked[142]; - assign N199 = N198 | data_masked[218]; - assign N198 = data_masked[370] | data_masked[294]; - assign data_o[67] = N203 | data_masked[67]; - assign N203 = N202 | data_masked[143]; - assign N202 = N201 | data_masked[219]; - assign N201 = data_masked[371] | data_masked[295]; - assign data_o[68] = N206 | data_masked[68]; - assign N206 = N205 | data_masked[144]; - assign N205 = N204 | data_masked[220]; - assign N204 = data_masked[372] | data_masked[296]; - assign data_o[69] = N209 | data_masked[69]; - assign N209 = N208 | data_masked[145]; - assign N208 = N207 | data_masked[221]; - assign N207 = data_masked[373] | data_masked[297]; - assign data_o[70] = N212 | data_masked[70]; - assign N212 = N211 | data_masked[146]; - assign N211 = N210 | data_masked[222]; - assign N210 = data_masked[374] | data_masked[298]; - assign data_o[71] = N215 | data_masked[71]; - assign N215 = N214 | data_masked[147]; - assign N214 = N213 | data_masked[223]; - assign N213 = data_masked[375] | data_masked[299]; - assign data_o[72] = N218 | data_masked[72]; - assign N218 = N217 | data_masked[148]; - assign N217 = N216 | data_masked[224]; - assign N216 = data_masked[376] | data_masked[300]; - assign data_o[73] = N221 | data_masked[73]; - assign N221 = N220 | data_masked[149]; - assign N220 = N219 | data_masked[225]; - assign N219 = data_masked[377] | data_masked[301]; - assign data_o[74] = N224 | data_masked[74]; - assign N224 = N223 | data_masked[150]; - assign N223 = N222 | data_masked[226]; - assign N222 = data_masked[378] | data_masked[302]; - assign data_o[75] = N227 | data_masked[75]; - assign N227 = N226 | data_masked[151]; - assign N226 = N225 | data_masked[227]; - assign N225 = data_masked[379] | data_masked[303]; - -endmodule - - - -module bsg_mux_one_hot_width_p76_els_p4 -( - data_i, - sel_one_hot_i, - data_o -); - - input [303:0] data_i; - input [3:0] sel_one_hot_i; - output [75:0] data_o; - wire [75:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41, - N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61, - N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81, - N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101, - N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117, - N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133, - N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149, - N150,N151; - wire [303:0] data_masked; - assign data_masked[75] = data_i[75] & sel_one_hot_i[0]; - assign data_masked[74] = data_i[74] & sel_one_hot_i[0]; - assign data_masked[73] = data_i[73] & sel_one_hot_i[0]; - assign data_masked[72] = data_i[72] & sel_one_hot_i[0]; - assign data_masked[71] = data_i[71] & sel_one_hot_i[0]; - assign data_masked[70] = data_i[70] & sel_one_hot_i[0]; - assign data_masked[69] = data_i[69] & sel_one_hot_i[0]; - assign data_masked[68] = data_i[68] & sel_one_hot_i[0]; - assign data_masked[67] = data_i[67] & sel_one_hot_i[0]; - assign data_masked[66] = data_i[66] & sel_one_hot_i[0]; - assign data_masked[65] = data_i[65] & sel_one_hot_i[0]; - assign data_masked[64] = data_i[64] & sel_one_hot_i[0]; - assign data_masked[63] = data_i[63] & sel_one_hot_i[0]; - assign data_masked[62] = data_i[62] & sel_one_hot_i[0]; - assign data_masked[61] = data_i[61] & sel_one_hot_i[0]; - assign data_masked[60] = data_i[60] & sel_one_hot_i[0]; - assign data_masked[59] = data_i[59] & sel_one_hot_i[0]; - assign data_masked[58] = data_i[58] & sel_one_hot_i[0]; - assign data_masked[57] = data_i[57] & sel_one_hot_i[0]; - assign data_masked[56] = data_i[56] & sel_one_hot_i[0]; - assign data_masked[55] = data_i[55] & sel_one_hot_i[0]; - assign data_masked[54] = data_i[54] & sel_one_hot_i[0]; - assign data_masked[53] = data_i[53] & sel_one_hot_i[0]; - assign data_masked[52] = data_i[52] & sel_one_hot_i[0]; - assign data_masked[51] = data_i[51] & sel_one_hot_i[0]; - assign data_masked[50] = data_i[50] & sel_one_hot_i[0]; - assign data_masked[49] = data_i[49] & sel_one_hot_i[0]; - assign data_masked[48] = data_i[48] & sel_one_hot_i[0]; - assign data_masked[47] = data_i[47] & sel_one_hot_i[0]; - assign data_masked[46] = data_i[46] & sel_one_hot_i[0]; - assign data_masked[45] = data_i[45] & sel_one_hot_i[0]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[0]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[0]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[0]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[0]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[0]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[0]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[0]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[0]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[0]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[0]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[0]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[0]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[0]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[0]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[0]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[0]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[0]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[0]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[0]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[0]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[0]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[0]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[0]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[0]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[0]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[0]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[0]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[0]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[0]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[0]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[0]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[0]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[0]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[151] = data_i[151] & sel_one_hot_i[1]; - assign data_masked[150] = data_i[150] & sel_one_hot_i[1]; - assign data_masked[149] = data_i[149] & sel_one_hot_i[1]; - assign data_masked[148] = data_i[148] & sel_one_hot_i[1]; - assign data_masked[147] = data_i[147] & sel_one_hot_i[1]; - assign data_masked[146] = data_i[146] & sel_one_hot_i[1]; - assign data_masked[145] = data_i[145] & sel_one_hot_i[1]; - assign data_masked[144] = data_i[144] & sel_one_hot_i[1]; - assign data_masked[143] = data_i[143] & sel_one_hot_i[1]; - assign data_masked[142] = data_i[142] & sel_one_hot_i[1]; - assign data_masked[141] = data_i[141] & sel_one_hot_i[1]; - assign data_masked[140] = data_i[140] & sel_one_hot_i[1]; - assign data_masked[139] = data_i[139] & sel_one_hot_i[1]; - assign data_masked[138] = data_i[138] & sel_one_hot_i[1]; - assign data_masked[137] = data_i[137] & sel_one_hot_i[1]; - assign data_masked[136] = data_i[136] & sel_one_hot_i[1]; - assign data_masked[135] = data_i[135] & sel_one_hot_i[1]; - assign data_masked[134] = data_i[134] & sel_one_hot_i[1]; - assign data_masked[133] = data_i[133] & sel_one_hot_i[1]; - assign data_masked[132] = data_i[132] & sel_one_hot_i[1]; - assign data_masked[131] = data_i[131] & sel_one_hot_i[1]; - assign data_masked[130] = data_i[130] & sel_one_hot_i[1]; - assign data_masked[129] = data_i[129] & sel_one_hot_i[1]; - assign data_masked[128] = data_i[128] & sel_one_hot_i[1]; - assign data_masked[127] = data_i[127] & sel_one_hot_i[1]; - assign data_masked[126] = data_i[126] & sel_one_hot_i[1]; - assign data_masked[125] = data_i[125] & sel_one_hot_i[1]; - assign data_masked[124] = data_i[124] & sel_one_hot_i[1]; - assign data_masked[123] = data_i[123] & sel_one_hot_i[1]; - assign data_masked[122] = data_i[122] & sel_one_hot_i[1]; - assign data_masked[121] = data_i[121] & sel_one_hot_i[1]; - assign data_masked[120] = data_i[120] & sel_one_hot_i[1]; - assign data_masked[119] = data_i[119] & sel_one_hot_i[1]; - assign data_masked[118] = data_i[118] & sel_one_hot_i[1]; - assign data_masked[117] = data_i[117] & sel_one_hot_i[1]; - assign data_masked[116] = data_i[116] & sel_one_hot_i[1]; - assign data_masked[115] = data_i[115] & sel_one_hot_i[1]; - assign data_masked[114] = data_i[114] & sel_one_hot_i[1]; - assign data_masked[113] = data_i[113] & sel_one_hot_i[1]; - assign data_masked[112] = data_i[112] & sel_one_hot_i[1]; - assign data_masked[111] = data_i[111] & sel_one_hot_i[1]; - assign data_masked[110] = data_i[110] & sel_one_hot_i[1]; - assign data_masked[109] = data_i[109] & sel_one_hot_i[1]; - assign data_masked[108] = data_i[108] & sel_one_hot_i[1]; - assign data_masked[107] = data_i[107] & sel_one_hot_i[1]; - assign data_masked[106] = data_i[106] & sel_one_hot_i[1]; - assign data_masked[105] = data_i[105] & sel_one_hot_i[1]; - assign data_masked[104] = data_i[104] & sel_one_hot_i[1]; - assign data_masked[103] = data_i[103] & sel_one_hot_i[1]; - assign data_masked[102] = data_i[102] & sel_one_hot_i[1]; - assign data_masked[101] = data_i[101] & sel_one_hot_i[1]; - assign data_masked[100] = data_i[100] & sel_one_hot_i[1]; - assign data_masked[99] = data_i[99] & sel_one_hot_i[1]; - assign data_masked[98] = data_i[98] & sel_one_hot_i[1]; - assign data_masked[97] = data_i[97] & sel_one_hot_i[1]; - assign data_masked[96] = data_i[96] & sel_one_hot_i[1]; - assign data_masked[95] = data_i[95] & sel_one_hot_i[1]; - assign data_masked[94] = data_i[94] & sel_one_hot_i[1]; - assign data_masked[93] = data_i[93] & sel_one_hot_i[1]; - assign data_masked[92] = data_i[92] & sel_one_hot_i[1]; - assign data_masked[91] = data_i[91] & sel_one_hot_i[1]; - assign data_masked[90] = data_i[90] & sel_one_hot_i[1]; - assign data_masked[89] = data_i[89] & sel_one_hot_i[1]; - assign data_masked[88] = data_i[88] & sel_one_hot_i[1]; - assign data_masked[87] = data_i[87] & sel_one_hot_i[1]; - assign data_masked[86] = data_i[86] & sel_one_hot_i[1]; - assign data_masked[85] = data_i[85] & sel_one_hot_i[1]; - assign data_masked[84] = data_i[84] & sel_one_hot_i[1]; - assign data_masked[83] = data_i[83] & sel_one_hot_i[1]; - assign data_masked[82] = data_i[82] & sel_one_hot_i[1]; - assign data_masked[81] = data_i[81] & sel_one_hot_i[1]; - assign data_masked[80] = data_i[80] & sel_one_hot_i[1]; - assign data_masked[79] = data_i[79] & sel_one_hot_i[1]; - assign data_masked[78] = data_i[78] & sel_one_hot_i[1]; - assign data_masked[77] = data_i[77] & sel_one_hot_i[1]; - assign data_masked[76] = data_i[76] & sel_one_hot_i[1]; - assign data_masked[227] = data_i[227] & sel_one_hot_i[2]; - assign data_masked[226] = data_i[226] & sel_one_hot_i[2]; - assign data_masked[225] = data_i[225] & sel_one_hot_i[2]; - assign data_masked[224] = data_i[224] & sel_one_hot_i[2]; - assign data_masked[223] = data_i[223] & sel_one_hot_i[2]; - assign data_masked[222] = data_i[222] & sel_one_hot_i[2]; - assign data_masked[221] = data_i[221] & sel_one_hot_i[2]; - assign data_masked[220] = data_i[220] & sel_one_hot_i[2]; - assign data_masked[219] = data_i[219] & sel_one_hot_i[2]; - assign data_masked[218] = data_i[218] & sel_one_hot_i[2]; - assign data_masked[217] = data_i[217] & sel_one_hot_i[2]; - assign data_masked[216] = data_i[216] & sel_one_hot_i[2]; - assign data_masked[215] = data_i[215] & sel_one_hot_i[2]; - assign data_masked[214] = data_i[214] & sel_one_hot_i[2]; - assign data_masked[213] = data_i[213] & sel_one_hot_i[2]; - assign data_masked[212] = data_i[212] & sel_one_hot_i[2]; - assign data_masked[211] = data_i[211] & sel_one_hot_i[2]; - assign data_masked[210] = data_i[210] & sel_one_hot_i[2]; - assign data_masked[209] = data_i[209] & sel_one_hot_i[2]; - assign data_masked[208] = data_i[208] & sel_one_hot_i[2]; - assign data_masked[207] = data_i[207] & sel_one_hot_i[2]; - assign data_masked[206] = data_i[206] & sel_one_hot_i[2]; - assign data_masked[205] = data_i[205] & sel_one_hot_i[2]; - assign data_masked[204] = data_i[204] & sel_one_hot_i[2]; - assign data_masked[203] = data_i[203] & sel_one_hot_i[2]; - assign data_masked[202] = data_i[202] & sel_one_hot_i[2]; - assign data_masked[201] = data_i[201] & sel_one_hot_i[2]; - assign data_masked[200] = data_i[200] & sel_one_hot_i[2]; - assign data_masked[199] = data_i[199] & sel_one_hot_i[2]; - assign data_masked[198] = data_i[198] & sel_one_hot_i[2]; - assign data_masked[197] = data_i[197] & sel_one_hot_i[2]; - assign data_masked[196] = data_i[196] & sel_one_hot_i[2]; - assign data_masked[195] = data_i[195] & sel_one_hot_i[2]; - assign data_masked[194] = data_i[194] & sel_one_hot_i[2]; - assign data_masked[193] = data_i[193] & sel_one_hot_i[2]; - assign data_masked[192] = data_i[192] & sel_one_hot_i[2]; - assign data_masked[191] = data_i[191] & sel_one_hot_i[2]; - assign data_masked[190] = data_i[190] & sel_one_hot_i[2]; - assign data_masked[189] = data_i[189] & sel_one_hot_i[2]; - assign data_masked[188] = data_i[188] & sel_one_hot_i[2]; - assign data_masked[187] = data_i[187] & sel_one_hot_i[2]; - assign data_masked[186] = data_i[186] & sel_one_hot_i[2]; - assign data_masked[185] = data_i[185] & sel_one_hot_i[2]; - assign data_masked[184] = data_i[184] & sel_one_hot_i[2]; - assign data_masked[183] = data_i[183] & sel_one_hot_i[2]; - assign data_masked[182] = data_i[182] & sel_one_hot_i[2]; - assign data_masked[181] = data_i[181] & sel_one_hot_i[2]; - assign data_masked[180] = data_i[180] & sel_one_hot_i[2]; - assign data_masked[179] = data_i[179] & sel_one_hot_i[2]; - assign data_masked[178] = data_i[178] & sel_one_hot_i[2]; - assign data_masked[177] = data_i[177] & sel_one_hot_i[2]; - assign data_masked[176] = data_i[176] & sel_one_hot_i[2]; - assign data_masked[175] = data_i[175] & sel_one_hot_i[2]; - assign data_masked[174] = data_i[174] & sel_one_hot_i[2]; - assign data_masked[173] = data_i[173] & sel_one_hot_i[2]; - assign data_masked[172] = data_i[172] & sel_one_hot_i[2]; - assign data_masked[171] = data_i[171] & sel_one_hot_i[2]; - assign data_masked[170] = data_i[170] & sel_one_hot_i[2]; - assign data_masked[169] = data_i[169] & sel_one_hot_i[2]; - assign data_masked[168] = data_i[168] & sel_one_hot_i[2]; - assign data_masked[167] = data_i[167] & sel_one_hot_i[2]; - assign data_masked[166] = data_i[166] & sel_one_hot_i[2]; - assign data_masked[165] = data_i[165] & sel_one_hot_i[2]; - assign data_masked[164] = data_i[164] & sel_one_hot_i[2]; - assign data_masked[163] = data_i[163] & sel_one_hot_i[2]; - assign data_masked[162] = data_i[162] & sel_one_hot_i[2]; - assign data_masked[161] = data_i[161] & sel_one_hot_i[2]; - assign data_masked[160] = data_i[160] & sel_one_hot_i[2]; - assign data_masked[159] = data_i[159] & sel_one_hot_i[2]; - assign data_masked[158] = data_i[158] & sel_one_hot_i[2]; - assign data_masked[157] = data_i[157] & sel_one_hot_i[2]; - assign data_masked[156] = data_i[156] & sel_one_hot_i[2]; - assign data_masked[155] = data_i[155] & sel_one_hot_i[2]; - assign data_masked[154] = data_i[154] & sel_one_hot_i[2]; - assign data_masked[153] = data_i[153] & sel_one_hot_i[2]; - assign data_masked[152] = data_i[152] & sel_one_hot_i[2]; - assign data_masked[303] = data_i[303] & sel_one_hot_i[3]; - assign data_masked[302] = data_i[302] & sel_one_hot_i[3]; - assign data_masked[301] = data_i[301] & sel_one_hot_i[3]; - assign data_masked[300] = data_i[300] & sel_one_hot_i[3]; - assign data_masked[299] = data_i[299] & sel_one_hot_i[3]; - assign data_masked[298] = data_i[298] & sel_one_hot_i[3]; - assign data_masked[297] = data_i[297] & sel_one_hot_i[3]; - assign data_masked[296] = data_i[296] & sel_one_hot_i[3]; - assign data_masked[295] = data_i[295] & sel_one_hot_i[3]; - assign data_masked[294] = data_i[294] & sel_one_hot_i[3]; - assign data_masked[293] = data_i[293] & sel_one_hot_i[3]; - assign data_masked[292] = data_i[292] & sel_one_hot_i[3]; - assign data_masked[291] = data_i[291] & sel_one_hot_i[3]; - assign data_masked[290] = data_i[290] & sel_one_hot_i[3]; - assign data_masked[289] = data_i[289] & sel_one_hot_i[3]; - assign data_masked[288] = data_i[288] & sel_one_hot_i[3]; - assign data_masked[287] = data_i[287] & sel_one_hot_i[3]; - assign data_masked[286] = data_i[286] & sel_one_hot_i[3]; - assign data_masked[285] = data_i[285] & sel_one_hot_i[3]; - assign data_masked[284] = data_i[284] & sel_one_hot_i[3]; - assign data_masked[283] = data_i[283] & sel_one_hot_i[3]; - assign data_masked[282] = data_i[282] & sel_one_hot_i[3]; - assign data_masked[281] = data_i[281] & sel_one_hot_i[3]; - assign data_masked[280] = data_i[280] & sel_one_hot_i[3]; - assign data_masked[279] = data_i[279] & sel_one_hot_i[3]; - assign data_masked[278] = data_i[278] & sel_one_hot_i[3]; - assign data_masked[277] = data_i[277] & sel_one_hot_i[3]; - assign data_masked[276] = data_i[276] & sel_one_hot_i[3]; - assign data_masked[275] = data_i[275] & sel_one_hot_i[3]; - assign data_masked[274] = data_i[274] & sel_one_hot_i[3]; - assign data_masked[273] = data_i[273] & sel_one_hot_i[3]; - assign data_masked[272] = data_i[272] & sel_one_hot_i[3]; - assign data_masked[271] = data_i[271] & sel_one_hot_i[3]; - assign data_masked[270] = data_i[270] & sel_one_hot_i[3]; - assign data_masked[269] = data_i[269] & sel_one_hot_i[3]; - assign data_masked[268] = data_i[268] & sel_one_hot_i[3]; - assign data_masked[267] = data_i[267] & sel_one_hot_i[3]; - assign data_masked[266] = data_i[266] & sel_one_hot_i[3]; - assign data_masked[265] = data_i[265] & sel_one_hot_i[3]; - assign data_masked[264] = data_i[264] & sel_one_hot_i[3]; - assign data_masked[263] = data_i[263] & sel_one_hot_i[3]; - assign data_masked[262] = data_i[262] & sel_one_hot_i[3]; - assign data_masked[261] = data_i[261] & sel_one_hot_i[3]; - assign data_masked[260] = data_i[260] & sel_one_hot_i[3]; - assign data_masked[259] = data_i[259] & sel_one_hot_i[3]; - assign data_masked[258] = data_i[258] & sel_one_hot_i[3]; - assign data_masked[257] = data_i[257] & sel_one_hot_i[3]; - assign data_masked[256] = data_i[256] & sel_one_hot_i[3]; - assign data_masked[255] = data_i[255] & sel_one_hot_i[3]; - assign data_masked[254] = data_i[254] & sel_one_hot_i[3]; - assign data_masked[253] = data_i[253] & sel_one_hot_i[3]; - assign data_masked[252] = data_i[252] & sel_one_hot_i[3]; - assign data_masked[251] = data_i[251] & sel_one_hot_i[3]; - assign data_masked[250] = data_i[250] & sel_one_hot_i[3]; - assign data_masked[249] = data_i[249] & sel_one_hot_i[3]; - assign data_masked[248] = data_i[248] & sel_one_hot_i[3]; - assign data_masked[247] = data_i[247] & sel_one_hot_i[3]; - assign data_masked[246] = data_i[246] & sel_one_hot_i[3]; - assign data_masked[245] = data_i[245] & sel_one_hot_i[3]; - assign data_masked[244] = data_i[244] & sel_one_hot_i[3]; - assign data_masked[243] = data_i[243] & sel_one_hot_i[3]; - assign data_masked[242] = data_i[242] & sel_one_hot_i[3]; - assign data_masked[241] = data_i[241] & sel_one_hot_i[3]; - assign data_masked[240] = data_i[240] & sel_one_hot_i[3]; - assign data_masked[239] = data_i[239] & sel_one_hot_i[3]; - assign data_masked[238] = data_i[238] & sel_one_hot_i[3]; - assign data_masked[237] = data_i[237] & sel_one_hot_i[3]; - assign data_masked[236] = data_i[236] & sel_one_hot_i[3]; - assign data_masked[235] = data_i[235] & sel_one_hot_i[3]; - assign data_masked[234] = data_i[234] & sel_one_hot_i[3]; - assign data_masked[233] = data_i[233] & sel_one_hot_i[3]; - assign data_masked[232] = data_i[232] & sel_one_hot_i[3]; - assign data_masked[231] = data_i[231] & sel_one_hot_i[3]; - assign data_masked[230] = data_i[230] & sel_one_hot_i[3]; - assign data_masked[229] = data_i[229] & sel_one_hot_i[3]; - assign data_masked[228] = data_i[228] & sel_one_hot_i[3]; - assign data_o[0] = N1 | data_masked[0]; - assign N1 = N0 | data_masked[76]; - assign N0 = data_masked[228] | data_masked[152]; - assign data_o[1] = N3 | data_masked[1]; - assign N3 = N2 | data_masked[77]; - assign N2 = data_masked[229] | data_masked[153]; - assign data_o[2] = N5 | data_masked[2]; - assign N5 = N4 | data_masked[78]; - assign N4 = data_masked[230] | data_masked[154]; - assign data_o[3] = N7 | data_masked[3]; - assign N7 = N6 | data_masked[79]; - assign N6 = data_masked[231] | data_masked[155]; - assign data_o[4] = N9 | data_masked[4]; - assign N9 = N8 | data_masked[80]; - assign N8 = data_masked[232] | data_masked[156]; - assign data_o[5] = N11 | data_masked[5]; - assign N11 = N10 | data_masked[81]; - assign N10 = data_masked[233] | data_masked[157]; - assign data_o[6] = N13 | data_masked[6]; - assign N13 = N12 | data_masked[82]; - assign N12 = data_masked[234] | data_masked[158]; - assign data_o[7] = N15 | data_masked[7]; - assign N15 = N14 | data_masked[83]; - assign N14 = data_masked[235] | data_masked[159]; - assign data_o[8] = N17 | data_masked[8]; - assign N17 = N16 | data_masked[84]; - assign N16 = data_masked[236] | data_masked[160]; - assign data_o[9] = N19 | data_masked[9]; - assign N19 = N18 | data_masked[85]; - assign N18 = data_masked[237] | data_masked[161]; - assign data_o[10] = N21 | data_masked[10]; - assign N21 = N20 | data_masked[86]; - assign N20 = data_masked[238] | data_masked[162]; - assign data_o[11] = N23 | data_masked[11]; - assign N23 = N22 | data_masked[87]; - assign N22 = data_masked[239] | data_masked[163]; - assign data_o[12] = N25 | data_masked[12]; - assign N25 = N24 | data_masked[88]; - assign N24 = data_masked[240] | data_masked[164]; - assign data_o[13] = N27 | data_masked[13]; - assign N27 = N26 | data_masked[89]; - assign N26 = data_masked[241] | data_masked[165]; - assign data_o[14] = N29 | data_masked[14]; - assign N29 = N28 | data_masked[90]; - assign N28 = data_masked[242] | data_masked[166]; - assign data_o[15] = N31 | data_masked[15]; - assign N31 = N30 | data_masked[91]; - assign N30 = data_masked[243] | data_masked[167]; - assign data_o[16] = N33 | data_masked[16]; - assign N33 = N32 | data_masked[92]; - assign N32 = data_masked[244] | data_masked[168]; - assign data_o[17] = N35 | data_masked[17]; - assign N35 = N34 | data_masked[93]; - assign N34 = data_masked[245] | data_masked[169]; - assign data_o[18] = N37 | data_masked[18]; - assign N37 = N36 | data_masked[94]; - assign N36 = data_masked[246] | data_masked[170]; - assign data_o[19] = N39 | data_masked[19]; - assign N39 = N38 | data_masked[95]; - assign N38 = data_masked[247] | data_masked[171]; - assign data_o[20] = N41 | data_masked[20]; - assign N41 = N40 | data_masked[96]; - assign N40 = data_masked[248] | data_masked[172]; - assign data_o[21] = N43 | data_masked[21]; - assign N43 = N42 | data_masked[97]; - assign N42 = data_masked[249] | data_masked[173]; - assign data_o[22] = N45 | data_masked[22]; - assign N45 = N44 | data_masked[98]; - assign N44 = data_masked[250] | data_masked[174]; - assign data_o[23] = N47 | data_masked[23]; - assign N47 = N46 | data_masked[99]; - assign N46 = data_masked[251] | data_masked[175]; - assign data_o[24] = N49 | data_masked[24]; - assign N49 = N48 | data_masked[100]; - assign N48 = data_masked[252] | data_masked[176]; - assign data_o[25] = N51 | data_masked[25]; - assign N51 = N50 | data_masked[101]; - assign N50 = data_masked[253] | data_masked[177]; - assign data_o[26] = N53 | data_masked[26]; - assign N53 = N52 | data_masked[102]; - assign N52 = data_masked[254] | data_masked[178]; - assign data_o[27] = N55 | data_masked[27]; - assign N55 = N54 | data_masked[103]; - assign N54 = data_masked[255] | data_masked[179]; - assign data_o[28] = N57 | data_masked[28]; - assign N57 = N56 | data_masked[104]; - assign N56 = data_masked[256] | data_masked[180]; - assign data_o[29] = N59 | data_masked[29]; - assign N59 = N58 | data_masked[105]; - assign N58 = data_masked[257] | data_masked[181]; - assign data_o[30] = N61 | data_masked[30]; - assign N61 = N60 | data_masked[106]; - assign N60 = data_masked[258] | data_masked[182]; - assign data_o[31] = N63 | data_masked[31]; - assign N63 = N62 | data_masked[107]; - assign N62 = data_masked[259] | data_masked[183]; - assign data_o[32] = N65 | data_masked[32]; - assign N65 = N64 | data_masked[108]; - assign N64 = data_masked[260] | data_masked[184]; - assign data_o[33] = N67 | data_masked[33]; - assign N67 = N66 | data_masked[109]; - assign N66 = data_masked[261] | data_masked[185]; - assign data_o[34] = N69 | data_masked[34]; - assign N69 = N68 | data_masked[110]; - assign N68 = data_masked[262] | data_masked[186]; - assign data_o[35] = N71 | data_masked[35]; - assign N71 = N70 | data_masked[111]; - assign N70 = data_masked[263] | data_masked[187]; - assign data_o[36] = N73 | data_masked[36]; - assign N73 = N72 | data_masked[112]; - assign N72 = data_masked[264] | data_masked[188]; - assign data_o[37] = N75 | data_masked[37]; - assign N75 = N74 | data_masked[113]; - assign N74 = data_masked[265] | data_masked[189]; - assign data_o[38] = N77 | data_masked[38]; - assign N77 = N76 | data_masked[114]; - assign N76 = data_masked[266] | data_masked[190]; - assign data_o[39] = N79 | data_masked[39]; - assign N79 = N78 | data_masked[115]; - assign N78 = data_masked[267] | data_masked[191]; - assign data_o[40] = N81 | data_masked[40]; - assign N81 = N80 | data_masked[116]; - assign N80 = data_masked[268] | data_masked[192]; - assign data_o[41] = N83 | data_masked[41]; - assign N83 = N82 | data_masked[117]; - assign N82 = data_masked[269] | data_masked[193]; - assign data_o[42] = N85 | data_masked[42]; - assign N85 = N84 | data_masked[118]; - assign N84 = data_masked[270] | data_masked[194]; - assign data_o[43] = N87 | data_masked[43]; - assign N87 = N86 | data_masked[119]; - assign N86 = data_masked[271] | data_masked[195]; - assign data_o[44] = N89 | data_masked[44]; - assign N89 = N88 | data_masked[120]; - assign N88 = data_masked[272] | data_masked[196]; - assign data_o[45] = N91 | data_masked[45]; - assign N91 = N90 | data_masked[121]; - assign N90 = data_masked[273] | data_masked[197]; - assign data_o[46] = N93 | data_masked[46]; - assign N93 = N92 | data_masked[122]; - assign N92 = data_masked[274] | data_masked[198]; - assign data_o[47] = N95 | data_masked[47]; - assign N95 = N94 | data_masked[123]; - assign N94 = data_masked[275] | data_masked[199]; - assign data_o[48] = N97 | data_masked[48]; - assign N97 = N96 | data_masked[124]; - assign N96 = data_masked[276] | data_masked[200]; - assign data_o[49] = N99 | data_masked[49]; - assign N99 = N98 | data_masked[125]; - assign N98 = data_masked[277] | data_masked[201]; - assign data_o[50] = N101 | data_masked[50]; - assign N101 = N100 | data_masked[126]; - assign N100 = data_masked[278] | data_masked[202]; - assign data_o[51] = N103 | data_masked[51]; - assign N103 = N102 | data_masked[127]; - assign N102 = data_masked[279] | data_masked[203]; - assign data_o[52] = N105 | data_masked[52]; - assign N105 = N104 | data_masked[128]; - assign N104 = data_masked[280] | data_masked[204]; - assign data_o[53] = N107 | data_masked[53]; - assign N107 = N106 | data_masked[129]; - assign N106 = data_masked[281] | data_masked[205]; - assign data_o[54] = N109 | data_masked[54]; - assign N109 = N108 | data_masked[130]; - assign N108 = data_masked[282] | data_masked[206]; - assign data_o[55] = N111 | data_masked[55]; - assign N111 = N110 | data_masked[131]; - assign N110 = data_masked[283] | data_masked[207]; - assign data_o[56] = N113 | data_masked[56]; - assign N113 = N112 | data_masked[132]; - assign N112 = data_masked[284] | data_masked[208]; - assign data_o[57] = N115 | data_masked[57]; - assign N115 = N114 | data_masked[133]; - assign N114 = data_masked[285] | data_masked[209]; - assign data_o[58] = N117 | data_masked[58]; - assign N117 = N116 | data_masked[134]; - assign N116 = data_masked[286] | data_masked[210]; - assign data_o[59] = N119 | data_masked[59]; - assign N119 = N118 | data_masked[135]; - assign N118 = data_masked[287] | data_masked[211]; - assign data_o[60] = N121 | data_masked[60]; - assign N121 = N120 | data_masked[136]; - assign N120 = data_masked[288] | data_masked[212]; - assign data_o[61] = N123 | data_masked[61]; - assign N123 = N122 | data_masked[137]; - assign N122 = data_masked[289] | data_masked[213]; - assign data_o[62] = N125 | data_masked[62]; - assign N125 = N124 | data_masked[138]; - assign N124 = data_masked[290] | data_masked[214]; - assign data_o[63] = N127 | data_masked[63]; - assign N127 = N126 | data_masked[139]; - assign N126 = data_masked[291] | data_masked[215]; - assign data_o[64] = N129 | data_masked[64]; - assign N129 = N128 | data_masked[140]; - assign N128 = data_masked[292] | data_masked[216]; - assign data_o[65] = N131 | data_masked[65]; - assign N131 = N130 | data_masked[141]; - assign N130 = data_masked[293] | data_masked[217]; - assign data_o[66] = N133 | data_masked[66]; - assign N133 = N132 | data_masked[142]; - assign N132 = data_masked[294] | data_masked[218]; - assign data_o[67] = N135 | data_masked[67]; - assign N135 = N134 | data_masked[143]; - assign N134 = data_masked[295] | data_masked[219]; - assign data_o[68] = N137 | data_masked[68]; - assign N137 = N136 | data_masked[144]; - assign N136 = data_masked[296] | data_masked[220]; - assign data_o[69] = N139 | data_masked[69]; - assign N139 = N138 | data_masked[145]; - assign N138 = data_masked[297] | data_masked[221]; - assign data_o[70] = N141 | data_masked[70]; - assign N141 = N140 | data_masked[146]; - assign N140 = data_masked[298] | data_masked[222]; - assign data_o[71] = N143 | data_masked[71]; - assign N143 = N142 | data_masked[147]; - assign N142 = data_masked[299] | data_masked[223]; - assign data_o[72] = N145 | data_masked[72]; - assign N145 = N144 | data_masked[148]; - assign N144 = data_masked[300] | data_masked[224]; - assign data_o[73] = N147 | data_masked[73]; - assign N147 = N146 | data_masked[149]; - assign N146 = data_masked[301] | data_masked[225]; - assign data_o[74] = N149 | data_masked[74]; - assign N149 = N148 | data_masked[150]; - assign N148 = data_masked[302] | data_masked[226]; - assign data_o[75] = N151 | data_masked[75]; - assign N151 = N150 | data_masked[151]; - assign N150 = data_masked[303] | data_masked[227]; - -endmodule - - - -module bsg_mesh_router_76_4_5_0_00_1 -( - clk_i, - reset_i, - data_i, - v_i, - yumi_o, - ready_i, - data_o, - v_o, - my_x_i, - my_y_i -); - - input [379:0] data_i; - input [4:0] v_i; - output [4:0] yumi_o; - input [4:0] ready_i; - output [379:0] data_o; - output [4:0] v_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [4:0] yumi_o,v_o; - wire [379:0] data_o; - wire W_gnt_e,W_gnt_p,W_gnt_s,E_gnt_w,E_gnt_p,E_gnt_s,N_gnt_s,N_gnt_e,N_gnt_w,N_gnt_p, - S_gnt_n,S_gnt_e,S_gnt_w,S_gnt_p,P_gnt_s,P_gnt_n,P_gnt_e,P_gnt_w,P_gnt_p,N0,N1, - N2,N3,N4,N5,N6,N7,N8,SV2V_UNCONNECTED_1,SV2V_UNCONNECTED_2, - SV2V_UNCONNECTED_3,SV2V_UNCONNECTED_4,SV2V_UNCONNECTED_5,SV2V_UNCONNECTED_6, - SV2V_UNCONNECTED_7,SV2V_UNCONNECTED_8,SV2V_UNCONNECTED_9, - SV2V_UNCONNECTED_10,SV2V_UNCONNECTED_11; - wire [24:0] req; - - bsg_mesh_router_dor_decoder_4_5_5_1 - dor_decoder - ( - .clk_i(clk_i), - .v_i(v_i), - .x_dirs_i({ data_i[307:304], data_i[231:228], data_i[155:152], data_i[79:76], data_i[3:0] }), - .y_dirs_i({ data_i[312:308], data_i[236:232], data_i[160:156], data_i[84:80], data_i[8:4] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .req_o(req) - ); - - - bsg_round_robin_arb_inputs_p3 - fi_west_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[1]), - .reqs_i({ req[11:11], req[1:1], req[21:21] }), - .grants_o({ W_gnt_e, W_gnt_p, W_gnt_s }), - .v_o(v_o[1]), - .tag_o({ SV2V_UNCONNECTED_1, SV2V_UNCONNECTED_2 }), - .yumi_i(v_o[1]) - ); - - - bsg_round_robin_arb_inputs_p3 - fi_east_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[2]), - .reqs_i({ req[7:7], req[2:2], req[22:22] }), - .grants_o({ E_gnt_w, E_gnt_p, E_gnt_s }), - .v_o(v_o[2]), - .tag_o({ SV2V_UNCONNECTED_3, SV2V_UNCONNECTED_4 }), - .yumi_i(v_o[2]) - ); - - - bsg_round_robin_arb_inputs_p4 - north_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[3]), - .reqs_i({ req[23:23], req[13:13], req[8:8], req[3:3] }), - .grants_o({ N_gnt_s, N_gnt_e, N_gnt_w, N_gnt_p }), - .v_o(v_o[3]), - .tag_o({ SV2V_UNCONNECTED_5, SV2V_UNCONNECTED_6 }), - .yumi_i(v_o[3]) - ); - - - bsg_round_robin_arb_inputs_p4 - south_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[4]), - .reqs_i({ req[19:19], req[14:14], req[9:9], req[4:4] }), - .grants_o({ S_gnt_n, S_gnt_e, S_gnt_w, S_gnt_p }), - .v_o(v_o[4]), - .tag_o({ SV2V_UNCONNECTED_7, SV2V_UNCONNECTED_8 }), - .yumi_i(v_o[4]) - ); - - - bsg_round_robin_arb_inputs_p5 - proc_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[0]), - .reqs_i({ req[20:20], req[15:15], req[10:10], req[5:5], req[0:0] }), - .grants_o({ P_gnt_s, P_gnt_n, P_gnt_e, P_gnt_w, P_gnt_p }), - .v_o(v_o[0]), - .tag_o({ SV2V_UNCONNECTED_9, SV2V_UNCONNECTED_10, SV2V_UNCONNECTED_11 }), - .yumi_i(v_o[0]) - ); - - - bsg_mux_one_hot_width_p76_els_p3 - genblk3_mux_data_west - ( - .data_i({ data_i[75:0], data_i[227:152], data_i[379:304] }), - .sel_one_hot_i({ W_gnt_p, W_gnt_e, W_gnt_s }), - .data_o(data_o[151:76]) - ); - - - bsg_mux_one_hot_width_p76_els_p3 - genblk3_mux_data_east - ( - .data_i({ data_i[75:0], data_i[151:76], data_i[379:304] }), - .sel_one_hot_i({ E_gnt_p, E_gnt_w, E_gnt_s }), - .data_o(data_o[227:152]) - ); - - - bsg_mux_one_hot_width_p76_els_p5 - mux_data_proc - ( - .data_i({ data_i[75:0], data_i[227:152], data_i[379:304], data_i[151:76], data_i[303:228] }), - .sel_one_hot_i({ P_gnt_p, P_gnt_e, P_gnt_s, P_gnt_w, P_gnt_n }), - .data_o(data_o[75:0]) - ); - - - bsg_mux_one_hot_width_p76_els_p4 - mux_data_north - ( - .data_i({ data_i[75:0], data_i[227:152], data_i[379:304], data_i[151:76] }), - .sel_one_hot_i({ N_gnt_p, N_gnt_e, N_gnt_s, N_gnt_w }), - .data_o(data_o[303:228]) - ); - - - bsg_mux_one_hot_width_p76_els_p4 - mux_data_south - ( - .data_i({ data_i[75:0], data_i[227:152], data_i[303:228], data_i[151:76] }), - .sel_one_hot_i({ S_gnt_p, S_gnt_e, S_gnt_n, S_gnt_w }), - .data_o(data_o[379:304]) - ); - - assign yumi_o[1] = N1 | P_gnt_w; - assign N1 = N0 | S_gnt_w; - assign N0 = E_gnt_w | N_gnt_w; - assign yumi_o[2] = N3 | P_gnt_e; - assign N3 = N2 | S_gnt_e; - assign N2 = W_gnt_e | N_gnt_e; - assign yumi_o[0] = N6 | W_gnt_p; - assign N6 = N5 | P_gnt_p; - assign N5 = N4 | S_gnt_p; - assign N4 = E_gnt_p | N_gnt_p; - assign yumi_o[3] = S_gnt_n | P_gnt_n; - assign yumi_o[4] = N8 | E_gnt_s; - assign N8 = N7 | W_gnt_s; - assign N7 = N_gnt_s | P_gnt_s; - -endmodule - - - -module bsg_mesh_router_buffered_76_4_5_0_00_1_00 -( - clk_i, - reset_i, - link_i, - link_o, - my_x_i, - my_y_i -); - - input [389:0] link_i; - output [389:0] link_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [389:0] link_o; - wire [4:0] fifo_valid,fifo_yumi; - wire [379:0] fifo_data; - - bsg_two_fifo_width_p76 - rof_0__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[76]), - .data_i(link_i[75:0]), - .v_i(link_i[77]), - .v_o(fifo_valid[0]), - .data_o(fifo_data[75:0]), - .yumi_i(fifo_yumi[0]) - ); - - - bsg_two_fifo_width_p76 - rof_1__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[154]), - .data_i(link_i[153:78]), - .v_i(link_i[155]), - .v_o(fifo_valid[1]), - .data_o(fifo_data[151:76]), - .yumi_i(fifo_yumi[1]) - ); - - - bsg_two_fifo_width_p76 - rof_2__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[232]), - .data_i(link_i[231:156]), - .v_i(link_i[233]), - .v_o(fifo_valid[2]), - .data_o(fifo_data[227:152]), - .yumi_i(fifo_yumi[2]) - ); - - - bsg_two_fifo_width_p76 - rof_3__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[310]), - .data_i(link_i[309:234]), - .v_i(link_i[311]), - .v_o(fifo_valid[3]), - .data_o(fifo_data[303:228]), - .yumi_i(fifo_yumi[3]) - ); - - - bsg_two_fifo_width_p76 - rof_4__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[388]), - .data_i(link_i[387:312]), - .v_i(link_i[389]), - .v_o(fifo_valid[4]), - .data_o(fifo_data[379:304]), - .yumi_i(fifo_yumi[4]) - ); - - - bsg_mesh_router_76_4_5_0_00_1 - bmr - ( - .clk_i(clk_i), - .reset_i(reset_i), - .data_i(fifo_data), - .v_i(fifo_valid), - .yumi_o(fifo_yumi), - .ready_i({ link_i[388:388], link_i[310:310], link_i[232:232], link_i[154:154], link_i[76:76] }), - .data_o({ link_o[387:312], link_o[309:234], link_o[231:156], link_o[153:78], link_o[75:0] }), - .v_o({ link_o[389:389], link_o[311:311], link_o[233:233], link_o[155:155], link_o[77:77] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - -endmodule - - - -module bsg_mem_1r1w_synth_width_p9_els_p2_read_write_same_addr_p0_harden_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [0:0] w_addr_i; - input [8:0] w_data_i; - input [0:0] r_addr_i; - output [8:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [8:0] r_data_o; - wire N0,N1,N2,N3,N4,N5,N7,N8; - reg [17:0] mem; - assign r_data_o[8] = (N3)? mem[8] : - (N0)? mem[17] : 1'b0; - assign N0 = r_addr_i[0]; - assign r_data_o[7] = (N3)? mem[7] : - (N0)? mem[16] : 1'b0; - assign r_data_o[6] = (N3)? mem[6] : - (N0)? mem[15] : 1'b0; - assign r_data_o[5] = (N3)? mem[5] : - (N0)? mem[14] : 1'b0; - assign r_data_o[4] = (N3)? mem[4] : - (N0)? mem[13] : 1'b0; - assign r_data_o[3] = (N3)? mem[3] : - (N0)? mem[12] : 1'b0; - assign r_data_o[2] = (N3)? mem[2] : - (N0)? mem[11] : 1'b0; - assign r_data_o[1] = (N3)? mem[1] : - (N0)? mem[10] : 1'b0; - assign r_data_o[0] = (N3)? mem[0] : - (N0)? mem[9] : 1'b0; - - always @(posedge w_clk_i) begin - if(N8) begin - mem[17] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[16] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[15] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[14] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[13] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[12] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[11] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[10] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N8) begin - mem[9] <= w_data_i[0]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[8] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[7] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[6] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[5] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[4] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[3] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[2] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[1] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N7) begin - mem[0] <= w_data_i[0]; - end - end - - assign N5 = ~w_addr_i[0]; - assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } : - (N2)? { 1'b0, 1'b0 } : 1'b0; - assign N1 = w_v_i; - assign N2 = N4; - assign N3 = ~r_addr_i[0]; - assign N4 = ~w_v_i; - -endmodule - - - -module bsg_mem_1r1w_width_p9_els_p2_read_write_same_addr_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [0:0] w_addr_i; - input [8:0] w_data_i; - input [0:0] r_addr_i; - output [8:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [8:0] r_data_o; - - bsg_mem_1r1w_synth_width_p9_els_p2_read_write_same_addr_p0_harden_p0 - synth - ( - .w_clk_i(w_clk_i), - .w_reset_i(w_reset_i), - .w_v_i(w_v_i), - .w_addr_i(w_addr_i[0]), - .w_data_i(w_data_i), - .r_v_i(r_v_i), - .r_addr_i(r_addr_i[0]), - .r_data_o(r_data_o) - ); - - -endmodule - - - -module bsg_two_fifo_width_p9 -( - clk_i, - reset_i, - ready_o, - data_i, - v_i, - v_o, - data_o, - yumi_i -); - - input [8:0] data_i; - output [8:0] data_o; - input clk_i; - input reset_i; - input v_i; - input yumi_i; - output ready_o; - output v_o; - wire [8:0] data_o; - wire ready_o,v_o,N0,N1,enq_i,n_0_net_,n_cse_4,n_cse_6,n_cse_7,N2,N3,N4,N5,N6,N7,N8, - N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21; - reg full_r,tail_r,head_r,empty_r; - - bsg_mem_1r1w_width_p9_els_p2_read_write_same_addr_p0 - mem_1r1w - ( - .w_clk_i(clk_i), - .w_reset_i(reset_i), - .w_v_i(enq_i), - .w_addr_i(tail_r), - .w_data_i(data_i), - .r_v_i(n_0_net_), - .r_addr_i(head_r), - .r_data_o(data_o) - ); - - - always @(posedge clk_i) begin - if(1'b1) begin - full_r <= N14; - end - end - - - always @(posedge clk_i) begin - if(N9) begin - tail_r <= N10; - end - end - - - always @(posedge clk_i) begin - if(N11) begin - head_r <= N12; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - empty_r <= N13; - end - end - - assign N9 = (N0)? 1'b1 : - (N1)? N5 : 1'b0; - assign N0 = N3; - assign N1 = N2; - assign N10 = (N0)? 1'b0 : - (N1)? N4 : 1'b0; - assign N11 = (N0)? 1'b1 : - (N1)? yumi_i : 1'b0; - assign N12 = (N0)? 1'b0 : - (N1)? N6 : 1'b0; - assign N13 = (N0)? 1'b1 : - (N1)? N7 : 1'b0; - assign N14 = (N0)? 1'b0 : - (N1)? N8 : 1'b0; - assign n_0_net_ = ~empty_r; - assign v_o = ~empty_r; - assign ready_o = ~full_r; - assign enq_i = v_i & N15; - assign N15 = ~full_r; - assign n_cse_4 = ~enq_i; - assign n_cse_6 = ~yumi_i; - assign n_cse_7 = N17 & n_cse_6; - assign N17 = N16 & enq_i; - assign N16 = ~empty_r; - assign N2 = ~reset_i; - assign N3 = reset_i; - assign N5 = enq_i; - assign N4 = ~tail_r; - assign N6 = ~head_r; - assign N7 = N18 | N20; - assign N18 = empty_r & n_cse_4; - assign N20 = N19 & n_cse_4; - assign N19 = N15 & yumi_i; - assign N8 = n_cse_7 | N21; - assign N21 = full_r & n_cse_6; - -endmodule - - - -module bsg_mux_one_hot_width_p9_els_p3 -( - data_i, - sel_one_hot_i, - data_o -); - - input [26:0] data_i; - input [2:0] sel_one_hot_i; - output [8:0] data_o; - wire [8:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8; - wire [26:0] data_masked; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[1]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[1]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[1]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[1]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[1]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[1]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[1]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[1]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[1]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[2]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[2]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[2]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[2]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[2]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[2]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[2]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[2]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[2]; - assign data_o[0] = N0 | data_masked[0]; - assign N0 = data_masked[18] | data_masked[9]; - assign data_o[1] = N1 | data_masked[1]; - assign N1 = data_masked[19] | data_masked[10]; - assign data_o[2] = N2 | data_masked[2]; - assign N2 = data_masked[20] | data_masked[11]; - assign data_o[3] = N3 | data_masked[3]; - assign N3 = data_masked[21] | data_masked[12]; - assign data_o[4] = N4 | data_masked[4]; - assign N4 = data_masked[22] | data_masked[13]; - assign data_o[5] = N5 | data_masked[5]; - assign N5 = data_masked[23] | data_masked[14]; - assign data_o[6] = N6 | data_masked[6]; - assign N6 = data_masked[24] | data_masked[15]; - assign data_o[7] = N7 | data_masked[7]; - assign N7 = data_masked[25] | data_masked[16]; - assign data_o[8] = N8 | data_masked[8]; - assign N8 = data_masked[26] | data_masked[17]; - -endmodule - - - -module bsg_mux_one_hot_width_p9_els_p5 -( - data_i, - sel_one_hot_i, - data_o -); - - input [44:0] data_i; - input [4:0] sel_one_hot_i; - output [8:0] data_o; - wire [8:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26; - wire [44:0] data_masked; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[1]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[1]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[1]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[1]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[1]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[1]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[1]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[1]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[1]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[2]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[2]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[2]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[2]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[2]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[2]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[2]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[2]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[2]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[3]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[3]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[3]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[3]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[3]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[3]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[3]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[3]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[3]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[4]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[4]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[4]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[4]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[4]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[4]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[4]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[4]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[4]; - assign data_o[0] = N2 | data_masked[0]; - assign N2 = N1 | data_masked[9]; - assign N1 = N0 | data_masked[18]; - assign N0 = data_masked[36] | data_masked[27]; - assign data_o[1] = N5 | data_masked[1]; - assign N5 = N4 | data_masked[10]; - assign N4 = N3 | data_masked[19]; - assign N3 = data_masked[37] | data_masked[28]; - assign data_o[2] = N8 | data_masked[2]; - assign N8 = N7 | data_masked[11]; - assign N7 = N6 | data_masked[20]; - assign N6 = data_masked[38] | data_masked[29]; - assign data_o[3] = N11 | data_masked[3]; - assign N11 = N10 | data_masked[12]; - assign N10 = N9 | data_masked[21]; - assign N9 = data_masked[39] | data_masked[30]; - assign data_o[4] = N14 | data_masked[4]; - assign N14 = N13 | data_masked[13]; - assign N13 = N12 | data_masked[22]; - assign N12 = data_masked[40] | data_masked[31]; - assign data_o[5] = N17 | data_masked[5]; - assign N17 = N16 | data_masked[14]; - assign N16 = N15 | data_masked[23]; - assign N15 = data_masked[41] | data_masked[32]; - assign data_o[6] = N20 | data_masked[6]; - assign N20 = N19 | data_masked[15]; - assign N19 = N18 | data_masked[24]; - assign N18 = data_masked[42] | data_masked[33]; - assign data_o[7] = N23 | data_masked[7]; - assign N23 = N22 | data_masked[16]; - assign N22 = N21 | data_masked[25]; - assign N21 = data_masked[43] | data_masked[34]; - assign data_o[8] = N26 | data_masked[8]; - assign N26 = N25 | data_masked[17]; - assign N25 = N24 | data_masked[26]; - assign N24 = data_masked[44] | data_masked[35]; - -endmodule - - - -module bsg_mux_one_hot_width_p9_els_p4 -( - data_i, - sel_one_hot_i, - data_o -); - - input [35:0] data_i; - input [3:0] sel_one_hot_i; - output [8:0] data_o; - wire [8:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17; - wire [35:0] data_masked; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[1]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[1]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[1]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[1]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[1]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[1]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[1]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[1]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[1]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[2]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[2]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[2]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[2]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[2]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[2]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[2]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[2]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[2]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[3]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[3]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[3]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[3]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[3]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[3]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[3]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[3]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[3]; - assign data_o[0] = N1 | data_masked[0]; - assign N1 = N0 | data_masked[9]; - assign N0 = data_masked[27] | data_masked[18]; - assign data_o[1] = N3 | data_masked[1]; - assign N3 = N2 | data_masked[10]; - assign N2 = data_masked[28] | data_masked[19]; - assign data_o[2] = N5 | data_masked[2]; - assign N5 = N4 | data_masked[11]; - assign N4 = data_masked[29] | data_masked[20]; - assign data_o[3] = N7 | data_masked[3]; - assign N7 = N6 | data_masked[12]; - assign N6 = data_masked[30] | data_masked[21]; - assign data_o[4] = N9 | data_masked[4]; - assign N9 = N8 | data_masked[13]; - assign N8 = data_masked[31] | data_masked[22]; - assign data_o[5] = N11 | data_masked[5]; - assign N11 = N10 | data_masked[14]; - assign N10 = data_masked[32] | data_masked[23]; - assign data_o[6] = N13 | data_masked[6]; - assign N13 = N12 | data_masked[15]; - assign N12 = data_masked[33] | data_masked[24]; - assign data_o[7] = N15 | data_masked[7]; - assign N15 = N14 | data_masked[16]; - assign N14 = data_masked[34] | data_masked[25]; - assign data_o[8] = N17 | data_masked[8]; - assign N17 = N16 | data_masked[17]; - assign N16 = data_masked[35] | data_masked[26]; - -endmodule - - - -module bsg_mesh_router_9_4_5_0_00_1 -( - clk_i, - reset_i, - data_i, - v_i, - yumi_o, - ready_i, - data_o, - v_o, - my_x_i, - my_y_i -); - - input [44:0] data_i; - input [4:0] v_i; - output [4:0] yumi_o; - input [4:0] ready_i; - output [44:0] data_o; - output [4:0] v_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [4:0] yumi_o,v_o; - wire [44:0] data_o; - wire W_gnt_e,W_gnt_p,W_gnt_s,E_gnt_w,E_gnt_p,E_gnt_s,N_gnt_s,N_gnt_e,N_gnt_w,N_gnt_p, - S_gnt_n,S_gnt_e,S_gnt_w,S_gnt_p,P_gnt_s,P_gnt_n,P_gnt_e,P_gnt_w,P_gnt_p,N0,N1, - N2,N3,N4,N5,N6,N7,N8,SV2V_UNCONNECTED_1,SV2V_UNCONNECTED_2, - SV2V_UNCONNECTED_3,SV2V_UNCONNECTED_4,SV2V_UNCONNECTED_5,SV2V_UNCONNECTED_6, - SV2V_UNCONNECTED_7,SV2V_UNCONNECTED_8,SV2V_UNCONNECTED_9, - SV2V_UNCONNECTED_10,SV2V_UNCONNECTED_11; - wire [24:0] req; - - bsg_mesh_router_dor_decoder_4_5_5_1 - dor_decoder - ( - .clk_i(clk_i), - .v_i(v_i), - .x_dirs_i({ data_i[39:36], data_i[30:27], data_i[21:18], data_i[12:9], data_i[3:0] }), - .y_dirs_i({ data_i[44:40], data_i[35:31], data_i[26:22], data_i[17:13], data_i[8:4] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .req_o(req) - ); - - - bsg_round_robin_arb_inputs_p3 - fi_west_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[1]), - .reqs_i({ req[11:11], req[1:1], req[21:21] }), - .grants_o({ W_gnt_e, W_gnt_p, W_gnt_s }), - .v_o(v_o[1]), - .tag_o({ SV2V_UNCONNECTED_1, SV2V_UNCONNECTED_2 }), - .yumi_i(v_o[1]) - ); - - - bsg_round_robin_arb_inputs_p3 - fi_east_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[2]), - .reqs_i({ req[7:7], req[2:2], req[22:22] }), - .grants_o({ E_gnt_w, E_gnt_p, E_gnt_s }), - .v_o(v_o[2]), - .tag_o({ SV2V_UNCONNECTED_3, SV2V_UNCONNECTED_4 }), - .yumi_i(v_o[2]) - ); - - - bsg_round_robin_arb_inputs_p4 - north_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[3]), - .reqs_i({ req[23:23], req[13:13], req[8:8], req[3:3] }), - .grants_o({ N_gnt_s, N_gnt_e, N_gnt_w, N_gnt_p }), - .v_o(v_o[3]), - .tag_o({ SV2V_UNCONNECTED_5, SV2V_UNCONNECTED_6 }), - .yumi_i(v_o[3]) - ); - - - bsg_round_robin_arb_inputs_p4 - south_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[4]), - .reqs_i({ req[19:19], req[14:14], req[9:9], req[4:4] }), - .grants_o({ S_gnt_n, S_gnt_e, S_gnt_w, S_gnt_p }), - .v_o(v_o[4]), - .tag_o({ SV2V_UNCONNECTED_7, SV2V_UNCONNECTED_8 }), - .yumi_i(v_o[4]) - ); - - - bsg_round_robin_arb_inputs_p5 - proc_rr_arb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .grants_en_i(ready_i[0]), - .reqs_i({ req[20:20], req[15:15], req[10:10], req[5:5], req[0:0] }), - .grants_o({ P_gnt_s, P_gnt_n, P_gnt_e, P_gnt_w, P_gnt_p }), - .v_o(v_o[0]), - .tag_o({ SV2V_UNCONNECTED_9, SV2V_UNCONNECTED_10, SV2V_UNCONNECTED_11 }), - .yumi_i(v_o[0]) - ); - - - bsg_mux_one_hot_width_p9_els_p3 - genblk3_mux_data_west - ( - .data_i({ data_i[8:0], data_i[26:18], data_i[44:36] }), - .sel_one_hot_i({ W_gnt_p, W_gnt_e, W_gnt_s }), - .data_o(data_o[17:9]) - ); - - - bsg_mux_one_hot_width_p9_els_p3 - genblk3_mux_data_east - ( - .data_i({ data_i[8:0], data_i[17:9], data_i[44:36] }), - .sel_one_hot_i({ E_gnt_p, E_gnt_w, E_gnt_s }), - .data_o(data_o[26:18]) - ); - - - bsg_mux_one_hot_width_p9_els_p5 - mux_data_proc - ( - .data_i({ data_i[8:0], data_i[26:18], data_i[44:36], data_i[17:9], data_i[35:27] }), - .sel_one_hot_i({ P_gnt_p, P_gnt_e, P_gnt_s, P_gnt_w, P_gnt_n }), - .data_o(data_o[8:0]) - ); - - - bsg_mux_one_hot_width_p9_els_p4 - mux_data_north - ( - .data_i({ data_i[8:0], data_i[26:18], data_i[44:36], data_i[17:9] }), - .sel_one_hot_i({ N_gnt_p, N_gnt_e, N_gnt_s, N_gnt_w }), - .data_o(data_o[35:27]) - ); - - - bsg_mux_one_hot_width_p9_els_p4 - mux_data_south - ( - .data_i({ data_i[8:0], data_i[26:18], data_i[35:27], data_i[17:9] }), - .sel_one_hot_i({ S_gnt_p, S_gnt_e, S_gnt_n, S_gnt_w }), - .data_o(data_o[44:36]) - ); - - assign yumi_o[1] = N1 | P_gnt_w; - assign N1 = N0 | S_gnt_w; - assign N0 = E_gnt_w | N_gnt_w; - assign yumi_o[2] = N3 | P_gnt_e; - assign N3 = N2 | S_gnt_e; - assign N2 = W_gnt_e | N_gnt_e; - assign yumi_o[0] = N6 | W_gnt_p; - assign N6 = N5 | P_gnt_p; - assign N5 = N4 | S_gnt_p; - assign N4 = E_gnt_p | N_gnt_p; - assign yumi_o[3] = S_gnt_n | P_gnt_n; - assign yumi_o[4] = N8 | E_gnt_s; - assign N8 = N7 | W_gnt_s; - assign N7 = N_gnt_s | P_gnt_s; - -endmodule - - - -module bsg_mesh_router_buffered_9_4_5_0_00_1_00 -( - clk_i, - reset_i, - link_i, - link_o, - my_x_i, - my_y_i -); - - input [54:0] link_i; - output [54:0] link_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [54:0] link_o; - wire [4:0] fifo_valid,fifo_yumi; - wire [44:0] fifo_data; - - bsg_two_fifo_width_p9 - rof_0__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[9]), - .data_i(link_i[8:0]), - .v_i(link_i[10]), - .v_o(fifo_valid[0]), - .data_o(fifo_data[8:0]), - .yumi_i(fifo_yumi[0]) - ); - - - bsg_two_fifo_width_p9 - rof_1__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[20]), - .data_i(link_i[19:11]), - .v_i(link_i[21]), - .v_o(fifo_valid[1]), - .data_o(fifo_data[17:9]), - .yumi_i(fifo_yumi[1]) - ); - - - bsg_two_fifo_width_p9 - rof_2__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[31]), - .data_i(link_i[30:22]), - .v_i(link_i[32]), - .v_o(fifo_valid[2]), - .data_o(fifo_data[26:18]), - .yumi_i(fifo_yumi[2]) - ); - - - bsg_two_fifo_width_p9 - rof_3__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[42]), - .data_i(link_i[41:33]), - .v_i(link_i[43]), - .v_o(fifo_valid[3]), - .data_o(fifo_data[35:27]), - .yumi_i(fifo_yumi[3]) - ); - - - bsg_two_fifo_width_p9 - rof_4__fi_twofer - ( - .clk_i(clk_i), - .reset_i(reset_i), - .ready_o(link_o[53]), - .data_i(link_i[52:44]), - .v_i(link_i[54]), - .v_o(fifo_valid[4]), - .data_o(fifo_data[44:36]), - .yumi_i(fifo_yumi[4]) - ); - - - bsg_mesh_router_9_4_5_0_00_1 - bmr - ( - .clk_i(clk_i), - .reset_i(reset_i), - .data_i(fifo_data), - .v_i(fifo_valid), - .yumi_o(fifo_yumi), - .ready_i({ link_i[53:53], link_i[42:42], link_i[31:31], link_i[20:20], link_i[9:9] }), - .data_o({ link_o[52:44], link_o[41:33], link_o[30:22], link_o[19:11], link_o[8:0] }), - .v_o({ link_o[54:54], link_o[43:43], link_o[32:32], link_o[21:21], link_o[10:10] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - -endmodule - - - -module bsg_manycore_mesh_node_4_5_32_20_0_0_0 -( - clk_i, - reset_i, - links_sif_i, - links_sif_o, - proc_link_sif_i, - proc_link_sif_o, - my_x_i, - my_y_i -); - - input [355:0] links_sif_i; - output [355:0] links_sif_o; - input [88:0] proc_link_sif_i; - output [88:0] proc_link_sif_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [355:0] links_sif_o; - wire [88:0] proc_link_sif_o; - - bsg_mesh_router_buffered_76_4_5_0_00_1_00 - rof_0__bmrb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .link_i({ links_sif_i[355:278], links_sif_i[266:189], links_sif_i[177:100], links_sif_i[88:11], proc_link_sif_i[88:11] }), - .link_o({ links_sif_o[355:278], links_sif_o[266:189], links_sif_o[177:100], links_sif_o[88:11], proc_link_sif_o[88:11] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - - bsg_mesh_router_buffered_9_4_5_0_00_1_00 - rof_1__bmrb - ( - .clk_i(clk_i), - .reset_i(reset_i), - .link_i({ links_sif_i[277:267], links_sif_i[188:178], links_sif_i[99:89], links_sif_i[10:0], proc_link_sif_i[10:0] }), - .link_o({ links_sif_o[277:267], links_sif_o[188:178], links_sif_o[99:89], links_sif_o[10:0], proc_link_sif_o[10:0] }), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - -endmodule - - - -module bsg_circular_ptr_slots_p4_max_add_p1 -( - clk, - reset_i, - add_i, - o -); - - input [0:0] add_i; - output [1:0] o; - input clk; - input reset_i; - wire N0,N1,N2,N3,N4,N5,N6,N7; - wire [1:0] genblk1_genblk1_ptr_r_p1; - reg [1:0] o; - - always @(posedge clk) begin - if(N7) begin - o[1] <= N4; - end - end - - - always @(posedge clk) begin - if(N7) begin - o[0] <= N3; - end - end - - assign genblk1_genblk1_ptr_r_p1 = o + 1'b1; - assign { N4, N3 } = (N0)? { 1'b0, 1'b0 } : - (N1)? genblk1_genblk1_ptr_r_p1 : 1'b0; - assign N0 = reset_i; - assign N1 = N2; - assign N2 = ~reset_i; - assign N5 = ~add_i[0]; - assign N6 = N5 & N2; - assign N7 = ~N6; - -endmodule - - - -module bsg_fifo_tracker_els_p4 -( - clk_i, - reset_i, - enq_i, - deq_i, - wptr_r_o, - rptr_r_o, - full_o, - empty_o -); - - output [1:0] wptr_r_o; - output [1:0] rptr_r_o; - input clk_i; - input reset_i; - input enq_i; - input deq_i; - output full_o; - output empty_o; - wire [1:0] wptr_r_o,rptr_r_o; - wire full_o,empty_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,equal_ptrs; - reg deq_r,enq_r; - - bsg_circular_ptr_slots_p4_max_add_p1 - rptr - ( - .clk(clk_i), - .reset_i(reset_i), - .add_i(deq_i), - .o(rptr_r_o) - ); - - - bsg_circular_ptr_slots_p4_max_add_p1 - wptr - ( - .clk(clk_i), - .reset_i(reset_i), - .add_i(enq_i), - .o(wptr_r_o) - ); - - - always @(posedge clk_i) begin - if(N5) begin - deq_r <= N7; - end - end - - - always @(posedge clk_i) begin - if(N5) begin - enq_r <= N6; - end - end - - assign equal_ptrs = rptr_r_o == wptr_r_o; - assign N5 = (N0)? 1'b1 : - (N9)? 1'b1 : - (N4)? 1'b0 : 1'b0; - assign N0 = N2; - assign N6 = (N0)? 1'b0 : - (N9)? enq_i : 1'b0; - assign N7 = (N0)? 1'b1 : - (N9)? deq_i : 1'b0; - assign N1 = enq_i | deq_i; - assign N2 = reset_i; - assign N3 = N1 | N2; - assign N4 = ~N3; - assign N8 = ~N2; - assign N9 = N1 & N8; - assign empty_o = equal_ptrs & deq_r; - assign full_o = equal_ptrs & enq_r; - -endmodule - - - -module bsg_mem_1r1w_synth_width_p76_els_p4_read_write_same_addr_p0_harden_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [1:0] w_addr_i; - input [75:0] w_data_i; - input [1:0] r_addr_i; - output [75:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [75:0] r_data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20; - reg [303:0] mem; - assign r_data_o[75] = (N8)? mem[75] : - (N10)? mem[151] : - (N9)? mem[227] : - (N11)? mem[303] : 1'b0; - assign r_data_o[74] = (N8)? mem[74] : - (N10)? mem[150] : - (N9)? mem[226] : - (N11)? mem[302] : 1'b0; - assign r_data_o[73] = (N8)? mem[73] : - (N10)? mem[149] : - (N9)? mem[225] : - (N11)? mem[301] : 1'b0; - assign r_data_o[72] = (N8)? mem[72] : - (N10)? mem[148] : - (N9)? mem[224] : - (N11)? mem[300] : 1'b0; - assign r_data_o[71] = (N8)? mem[71] : - (N10)? mem[147] : - (N9)? mem[223] : - (N11)? mem[299] : 1'b0; - assign r_data_o[70] = (N8)? mem[70] : - (N10)? mem[146] : - (N9)? mem[222] : - (N11)? mem[298] : 1'b0; - assign r_data_o[69] = (N8)? mem[69] : - (N10)? mem[145] : - (N9)? mem[221] : - (N11)? mem[297] : 1'b0; - assign r_data_o[68] = (N8)? mem[68] : - (N10)? mem[144] : - (N9)? mem[220] : - (N11)? mem[296] : 1'b0; - assign r_data_o[67] = (N8)? mem[67] : - (N10)? mem[143] : - (N9)? mem[219] : - (N11)? mem[295] : 1'b0; - assign r_data_o[66] = (N8)? mem[66] : - (N10)? mem[142] : - (N9)? mem[218] : - (N11)? mem[294] : 1'b0; - assign r_data_o[65] = (N8)? mem[65] : - (N10)? mem[141] : - (N9)? mem[217] : - (N11)? mem[293] : 1'b0; - assign r_data_o[64] = (N8)? mem[64] : - (N10)? mem[140] : - (N9)? mem[216] : - (N11)? mem[292] : 1'b0; - assign r_data_o[63] = (N8)? mem[63] : - (N10)? mem[139] : - (N9)? mem[215] : - (N11)? mem[291] : 1'b0; - assign r_data_o[62] = (N8)? mem[62] : - (N10)? mem[138] : - (N9)? mem[214] : - (N11)? mem[290] : 1'b0; - assign r_data_o[61] = (N8)? mem[61] : - (N10)? mem[137] : - (N9)? mem[213] : - (N11)? mem[289] : 1'b0; - assign r_data_o[60] = (N8)? mem[60] : - (N10)? mem[136] : - (N9)? mem[212] : - (N11)? mem[288] : 1'b0; - assign r_data_o[59] = (N8)? mem[59] : - (N10)? mem[135] : - (N9)? mem[211] : - (N11)? mem[287] : 1'b0; - assign r_data_o[58] = (N8)? mem[58] : - (N10)? mem[134] : - (N9)? mem[210] : - (N11)? mem[286] : 1'b0; - assign r_data_o[57] = (N8)? mem[57] : - (N10)? mem[133] : - (N9)? mem[209] : - (N11)? mem[285] : 1'b0; - assign r_data_o[56] = (N8)? mem[56] : - (N10)? mem[132] : - (N9)? mem[208] : - (N11)? mem[284] : 1'b0; - assign r_data_o[55] = (N8)? mem[55] : - (N10)? mem[131] : - (N9)? mem[207] : - (N11)? mem[283] : 1'b0; - assign r_data_o[54] = (N8)? mem[54] : - (N10)? mem[130] : - (N9)? mem[206] : - (N11)? mem[282] : 1'b0; - assign r_data_o[53] = (N8)? mem[53] : - (N10)? mem[129] : - (N9)? mem[205] : - (N11)? mem[281] : 1'b0; - assign r_data_o[52] = (N8)? mem[52] : - (N10)? mem[128] : - (N9)? mem[204] : - (N11)? mem[280] : 1'b0; - assign r_data_o[51] = (N8)? mem[51] : - (N10)? mem[127] : - (N9)? mem[203] : - (N11)? mem[279] : 1'b0; - assign r_data_o[50] = (N8)? mem[50] : - (N10)? mem[126] : - (N9)? mem[202] : - (N11)? mem[278] : 1'b0; - assign r_data_o[49] = (N8)? mem[49] : - (N10)? mem[125] : - (N9)? mem[201] : - (N11)? mem[277] : 1'b0; - assign r_data_o[48] = (N8)? mem[48] : - (N10)? mem[124] : - (N9)? mem[200] : - (N11)? mem[276] : 1'b0; - assign r_data_o[47] = (N8)? mem[47] : - (N10)? mem[123] : - (N9)? mem[199] : - (N11)? mem[275] : 1'b0; - assign r_data_o[46] = (N8)? mem[46] : - (N10)? mem[122] : - (N9)? mem[198] : - (N11)? mem[274] : 1'b0; - assign r_data_o[45] = (N8)? mem[45] : - (N10)? mem[121] : - (N9)? mem[197] : - (N11)? mem[273] : 1'b0; - assign r_data_o[44] = (N8)? mem[44] : - (N10)? mem[120] : - (N9)? mem[196] : - (N11)? mem[272] : 1'b0; - assign r_data_o[43] = (N8)? mem[43] : - (N10)? mem[119] : - (N9)? mem[195] : - (N11)? mem[271] : 1'b0; - assign r_data_o[42] = (N8)? mem[42] : - (N10)? mem[118] : - (N9)? mem[194] : - (N11)? mem[270] : 1'b0; - assign r_data_o[41] = (N8)? mem[41] : - (N10)? mem[117] : - (N9)? mem[193] : - (N11)? mem[269] : 1'b0; - assign r_data_o[40] = (N8)? mem[40] : - (N10)? mem[116] : - (N9)? mem[192] : - (N11)? mem[268] : 1'b0; - assign r_data_o[39] = (N8)? mem[39] : - (N10)? mem[115] : - (N9)? mem[191] : - (N11)? mem[267] : 1'b0; - assign r_data_o[38] = (N8)? mem[38] : - (N10)? mem[114] : - (N9)? mem[190] : - (N11)? mem[266] : 1'b0; - assign r_data_o[37] = (N8)? mem[37] : - (N10)? mem[113] : - (N9)? mem[189] : - (N11)? mem[265] : 1'b0; - assign r_data_o[36] = (N8)? mem[36] : - (N10)? mem[112] : - (N9)? mem[188] : - (N11)? mem[264] : 1'b0; - assign r_data_o[35] = (N8)? mem[35] : - (N10)? mem[111] : - (N9)? mem[187] : - (N11)? mem[263] : 1'b0; - assign r_data_o[34] = (N8)? mem[34] : - (N10)? mem[110] : - (N9)? mem[186] : - (N11)? mem[262] : 1'b0; - assign r_data_o[33] = (N8)? mem[33] : - (N10)? mem[109] : - (N9)? mem[185] : - (N11)? mem[261] : 1'b0; - assign r_data_o[32] = (N8)? mem[32] : - (N10)? mem[108] : - (N9)? mem[184] : - (N11)? mem[260] : 1'b0; - assign r_data_o[31] = (N8)? mem[31] : - (N10)? mem[107] : - (N9)? mem[183] : - (N11)? mem[259] : 1'b0; - assign r_data_o[30] = (N8)? mem[30] : - (N10)? mem[106] : - (N9)? mem[182] : - (N11)? mem[258] : 1'b0; - assign r_data_o[29] = (N8)? mem[29] : - (N10)? mem[105] : - (N9)? mem[181] : - (N11)? mem[257] : 1'b0; - assign r_data_o[28] = (N8)? mem[28] : - (N10)? mem[104] : - (N9)? mem[180] : - (N11)? mem[256] : 1'b0; - assign r_data_o[27] = (N8)? mem[27] : - (N10)? mem[103] : - (N9)? mem[179] : - (N11)? mem[255] : 1'b0; - assign r_data_o[26] = (N8)? mem[26] : - (N10)? mem[102] : - (N9)? mem[178] : - (N11)? mem[254] : 1'b0; - assign r_data_o[25] = (N8)? mem[25] : - (N10)? mem[101] : - (N9)? mem[177] : - (N11)? mem[253] : 1'b0; - assign r_data_o[24] = (N8)? mem[24] : - (N10)? mem[100] : - (N9)? mem[176] : - (N11)? mem[252] : 1'b0; - assign r_data_o[23] = (N8)? mem[23] : - (N10)? mem[99] : - (N9)? mem[175] : - (N11)? mem[251] : 1'b0; - assign r_data_o[22] = (N8)? mem[22] : - (N10)? mem[98] : - (N9)? mem[174] : - (N11)? mem[250] : 1'b0; - assign r_data_o[21] = (N8)? mem[21] : - (N10)? mem[97] : - (N9)? mem[173] : - (N11)? mem[249] : 1'b0; - assign r_data_o[20] = (N8)? mem[20] : - (N10)? mem[96] : - (N9)? mem[172] : - (N11)? mem[248] : 1'b0; - assign r_data_o[19] = (N8)? mem[19] : - (N10)? mem[95] : - (N9)? mem[171] : - (N11)? mem[247] : 1'b0; - assign r_data_o[18] = (N8)? mem[18] : - (N10)? mem[94] : - (N9)? mem[170] : - (N11)? mem[246] : 1'b0; - assign r_data_o[17] = (N8)? mem[17] : - (N10)? mem[93] : - (N9)? mem[169] : - (N11)? mem[245] : 1'b0; - assign r_data_o[16] = (N8)? mem[16] : - (N10)? mem[92] : - (N9)? mem[168] : - (N11)? mem[244] : 1'b0; - assign r_data_o[15] = (N8)? mem[15] : - (N10)? mem[91] : - (N9)? mem[167] : - (N11)? mem[243] : 1'b0; - assign r_data_o[14] = (N8)? mem[14] : - (N10)? mem[90] : - (N9)? mem[166] : - (N11)? mem[242] : 1'b0; - assign r_data_o[13] = (N8)? mem[13] : - (N10)? mem[89] : - (N9)? mem[165] : - (N11)? mem[241] : 1'b0; - assign r_data_o[12] = (N8)? mem[12] : - (N10)? mem[88] : - (N9)? mem[164] : - (N11)? mem[240] : 1'b0; - assign r_data_o[11] = (N8)? mem[11] : - (N10)? mem[87] : - (N9)? mem[163] : - (N11)? mem[239] : 1'b0; - assign r_data_o[10] = (N8)? mem[10] : - (N10)? mem[86] : - (N9)? mem[162] : - (N11)? mem[238] : 1'b0; - assign r_data_o[9] = (N8)? mem[9] : - (N10)? mem[85] : - (N9)? mem[161] : - (N11)? mem[237] : 1'b0; - assign r_data_o[8] = (N8)? mem[8] : - (N10)? mem[84] : - (N9)? mem[160] : - (N11)? mem[236] : 1'b0; - assign r_data_o[7] = (N8)? mem[7] : - (N10)? mem[83] : - (N9)? mem[159] : - (N11)? mem[235] : 1'b0; - assign r_data_o[6] = (N8)? mem[6] : - (N10)? mem[82] : - (N9)? mem[158] : - (N11)? mem[234] : 1'b0; - assign r_data_o[5] = (N8)? mem[5] : - (N10)? mem[81] : - (N9)? mem[157] : - (N11)? mem[233] : 1'b0; - assign r_data_o[4] = (N8)? mem[4] : - (N10)? mem[80] : - (N9)? mem[156] : - (N11)? mem[232] : 1'b0; - assign r_data_o[3] = (N8)? mem[3] : - (N10)? mem[79] : - (N9)? mem[155] : - (N11)? mem[231] : 1'b0; - assign r_data_o[2] = (N8)? mem[2] : - (N10)? mem[78] : - (N9)? mem[154] : - (N11)? mem[230] : 1'b0; - assign r_data_o[1] = (N8)? mem[1] : - (N10)? mem[77] : - (N9)? mem[153] : - (N11)? mem[229] : 1'b0; - assign r_data_o[0] = (N8)? mem[0] : - (N10)? mem[76] : - (N9)? mem[152] : - (N11)? mem[228] : 1'b0; - - always @(posedge w_clk_i) begin - if(N20) begin - mem[303] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[302] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[301] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[300] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[299] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[298] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[297] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[296] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[295] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[294] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[293] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[292] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[291] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[290] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[289] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[288] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[287] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[286] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[285] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[284] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[283] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[282] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[281] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[280] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[279] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[278] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[277] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[276] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[275] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[274] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[273] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[272] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[271] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[270] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[269] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[268] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[267] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[266] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[265] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[264] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[263] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[262] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[261] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[260] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[259] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[258] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[257] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[256] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[255] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[254] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[253] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[252] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[251] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[250] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[249] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[248] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[247] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[246] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[245] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[244] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[243] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[242] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[241] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[240] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[239] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[238] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[237] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[236] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[235] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[234] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[233] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[232] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[231] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[230] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[229] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N20) begin - mem[228] <= w_data_i[0]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[227] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[226] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[225] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[224] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[223] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[222] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[221] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[220] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[219] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[218] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[217] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[216] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[215] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[214] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[213] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[212] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[211] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[210] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[209] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[208] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[207] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[206] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[205] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[204] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[203] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[202] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[201] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[200] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[199] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[198] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[197] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[196] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[195] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[194] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[193] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[192] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[191] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[190] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[189] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[188] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[187] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[186] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[185] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[184] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[183] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[182] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[181] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[180] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[179] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[178] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[177] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[176] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[175] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[174] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[173] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[172] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[171] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[170] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[169] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[168] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[167] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[166] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[165] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[164] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[163] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[162] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[161] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[160] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[159] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[158] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[157] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[156] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[155] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[154] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[153] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N19) begin - mem[152] <= w_data_i[0]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[151] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[150] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[149] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[148] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[147] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[146] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[145] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[144] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[143] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[142] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[141] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[140] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[139] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[138] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[137] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[136] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[135] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[134] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[133] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[132] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[131] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[130] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[129] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[128] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[127] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[126] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[125] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[124] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[123] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[122] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[121] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[120] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[119] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[118] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[117] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[116] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[115] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[114] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[113] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[112] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[111] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[110] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[109] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[108] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[107] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[106] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[105] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[104] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[103] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[102] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[101] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[100] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[99] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[98] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[97] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[96] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[95] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[94] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[93] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[92] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[91] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[90] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[89] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[88] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[87] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[86] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[85] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[84] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[83] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[82] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[81] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[80] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[79] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[78] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[77] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N18) begin - mem[76] <= w_data_i[0]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[75] <= w_data_i[75]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[74] <= w_data_i[74]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[73] <= w_data_i[73]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[72] <= w_data_i[72]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[71] <= w_data_i[71]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[70] <= w_data_i[70]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[69] <= w_data_i[69]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[68] <= w_data_i[68]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[67] <= w_data_i[67]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[66] <= w_data_i[66]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[65] <= w_data_i[65]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[64] <= w_data_i[64]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[63] <= w_data_i[63]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[62] <= w_data_i[62]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[61] <= w_data_i[61]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[60] <= w_data_i[60]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[59] <= w_data_i[59]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[58] <= w_data_i[58]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[57] <= w_data_i[57]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[56] <= w_data_i[56]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[55] <= w_data_i[55]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[54] <= w_data_i[54]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[53] <= w_data_i[53]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[52] <= w_data_i[52]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[51] <= w_data_i[51]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[50] <= w_data_i[50]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[49] <= w_data_i[49]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[48] <= w_data_i[48]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[47] <= w_data_i[47]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[46] <= w_data_i[46]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[45] <= w_data_i[45]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[44] <= w_data_i[44]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[43] <= w_data_i[43]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[42] <= w_data_i[42]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[41] <= w_data_i[41]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[40] <= w_data_i[40]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[39] <= w_data_i[39]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[38] <= w_data_i[38]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[37] <= w_data_i[37]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[36] <= w_data_i[36]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[35] <= w_data_i[35]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[34] <= w_data_i[34]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[33] <= w_data_i[33]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[32] <= w_data_i[32]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[31] <= w_data_i[31]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[30] <= w_data_i[30]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[29] <= w_data_i[29]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[28] <= w_data_i[28]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[27] <= w_data_i[27]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[26] <= w_data_i[26]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[25] <= w_data_i[25]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[24] <= w_data_i[24]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[23] <= w_data_i[23]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[22] <= w_data_i[22]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[21] <= w_data_i[21]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[20] <= w_data_i[20]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[19] <= w_data_i[19]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[18] <= w_data_i[18]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[17] <= w_data_i[17]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[16] <= w_data_i[16]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[15] <= w_data_i[15]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[14] <= w_data_i[14]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[13] <= w_data_i[13]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[12] <= w_data_i[12]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[11] <= w_data_i[11]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[10] <= w_data_i[10]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[9] <= w_data_i[9]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[8] <= w_data_i[8]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[7] <= w_data_i[7]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[6] <= w_data_i[6]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[5] <= w_data_i[5]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[4] <= w_data_i[4]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[3] <= w_data_i[3]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[2] <= w_data_i[2]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[1] <= w_data_i[1]; - end - end - - - always @(posedge w_clk_i) begin - if(N17) begin - mem[0] <= w_data_i[0]; - end - end - - assign N16 = w_addr_i[0] & w_addr_i[1]; - assign N15 = N0 & w_addr_i[1]; - assign N0 = ~w_addr_i[0]; - assign N14 = w_addr_i[0] & N1; - assign N1 = ~w_addr_i[1]; - assign N13 = N2 & N3; - assign N2 = ~w_addr_i[0]; - assign N3 = ~w_addr_i[1]; - assign { N20, N19, N18, N17 } = (N4)? { N16, N15, N14, N13 } : - (N5)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N4 = w_v_i; - assign N5 = N12; - assign N6 = ~r_addr_i[0]; - assign N7 = ~r_addr_i[1]; - assign N8 = N6 & N7; - assign N9 = N6 & r_addr_i[1]; - assign N10 = r_addr_i[0] & N7; - assign N11 = r_addr_i[0] & r_addr_i[1]; - assign N12 = ~w_v_i; - -endmodule - - - -module bsg_mem_1r1w_width_p76_els_p4_read_write_same_addr_p0 -( - w_clk_i, - w_reset_i, - w_v_i, - w_addr_i, - w_data_i, - r_v_i, - r_addr_i, - r_data_o -); - - input [1:0] w_addr_i; - input [75:0] w_data_i; - input [1:0] r_addr_i; - output [75:0] r_data_o; - input w_clk_i; - input w_reset_i; - input w_v_i; - input r_v_i; - wire [75:0] r_data_o; - - bsg_mem_1r1w_synth_width_p76_els_p4_read_write_same_addr_p0_harden_p0 - synth - ( - .w_clk_i(w_clk_i), - .w_reset_i(w_reset_i), - .w_v_i(w_v_i), - .w_addr_i(w_addr_i), - .w_data_i(w_data_i), - .r_v_i(r_v_i), - .r_addr_i(r_addr_i), - .r_data_o(r_data_o) - ); - - -endmodule - - - -module bsg_fifo_1r1w_small_width_p76_els_p4 -( - clk_i, - reset_i, - v_i, - ready_o, - data_i, - v_o, - data_o, - yumi_i -); - - input [75:0] data_i; - output [75:0] data_o; - input clk_i; - input reset_i; - input v_i; - input yumi_i; - output ready_o; - output v_o; - wire [75:0] data_o; - wire ready_o,v_o,enque,full,empty,N0,N1; - wire [1:0] wptr_r,rptr_r; - - bsg_fifo_tracker_els_p4 - ft - ( - .clk_i(clk_i), - .reset_i(reset_i), - .enq_i(enque), - .deq_i(yumi_i), - .wptr_r_o(wptr_r), - .rptr_r_o(rptr_r), - .full_o(full), - .empty_o(empty) - ); - - - bsg_mem_1r1w_width_p76_els_p4_read_write_same_addr_p0 - mem_1r1w - ( - .w_clk_i(clk_i), - .w_reset_i(reset_i), - .w_v_i(enque), - .w_addr_i(wptr_r), - .w_data_i(data_i), - .r_v_i(v_o), - .r_addr_i(rptr_r), - .r_data_o(data_o) - ); - - assign enque = v_i & ready_o; - assign ready_o = N0 & N1; - assign N0 = ~full; - assign N1 = ~reset_i; - assign v_o = ~empty; - -endmodule - - - -module bsg_manycore_endpoint_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20 -( - clk_i, - reset_i, - link_sif_i, - link_sif_o, - fifo_data_o, - fifo_v_o, - fifo_yumi_i, - out_packet_i, - out_v_i, - out_ready_o, - credit_v_r_o, - in_fifo_full_o -); - - input [88:0] link_sif_i; - output [88:0] link_sif_o; - output [75:0] fifo_data_o; - input [75:0] out_packet_i; - input clk_i; - input reset_i; - input fifo_yumi_i; - input out_v_i; - output fifo_v_o; - output out_ready_o; - output credit_v_r_o; - output in_fifo_full_o; - wire [88:0] link_sif_o; - wire [75:0] fifo_data_o; - wire fifo_v_o,out_ready_o,in_fifo_full_o,out_v_i,fifo_yumi_i,fifo_v; - reg credit_v_r_o; - assign link_sif_o[9] = 1'b1; - assign out_ready_o = link_sif_i[87]; - assign link_sif_o[88] = out_v_i; - assign link_sif_o[86] = out_packet_i[75]; - assign link_sif_o[85] = out_packet_i[74]; - assign link_sif_o[84] = out_packet_i[73]; - assign link_sif_o[83] = out_packet_i[72]; - assign link_sif_o[82] = out_packet_i[71]; - assign link_sif_o[81] = out_packet_i[70]; - assign link_sif_o[80] = out_packet_i[69]; - assign link_sif_o[79] = out_packet_i[68]; - assign link_sif_o[78] = out_packet_i[67]; - assign link_sif_o[77] = out_packet_i[66]; - assign link_sif_o[76] = out_packet_i[65]; - assign link_sif_o[75] = out_packet_i[64]; - assign link_sif_o[74] = out_packet_i[63]; - assign link_sif_o[73] = out_packet_i[62]; - assign link_sif_o[72] = out_packet_i[61]; - assign link_sif_o[71] = out_packet_i[60]; - assign link_sif_o[70] = out_packet_i[59]; - assign link_sif_o[69] = out_packet_i[58]; - assign link_sif_o[68] = out_packet_i[57]; - assign link_sif_o[67] = out_packet_i[56]; - assign link_sif_o[66] = out_packet_i[55]; - assign link_sif_o[65] = out_packet_i[54]; - assign link_sif_o[64] = out_packet_i[53]; - assign link_sif_o[63] = out_packet_i[52]; - assign link_sif_o[62] = out_packet_i[51]; - assign link_sif_o[61] = out_packet_i[50]; - assign link_sif_o[60] = out_packet_i[49]; - assign link_sif_o[59] = out_packet_i[48]; - assign link_sif_o[58] = out_packet_i[47]; - assign link_sif_o[57] = out_packet_i[46]; - assign link_sif_o[56] = out_packet_i[45]; - assign link_sif_o[55] = out_packet_i[44]; - assign link_sif_o[54] = out_packet_i[43]; - assign link_sif_o[53] = out_packet_i[42]; - assign link_sif_o[52] = out_packet_i[41]; - assign link_sif_o[51] = out_packet_i[40]; - assign link_sif_o[50] = out_packet_i[39]; - assign link_sif_o[49] = out_packet_i[38]; - assign link_sif_o[48] = out_packet_i[37]; - assign link_sif_o[47] = out_packet_i[36]; - assign link_sif_o[46] = out_packet_i[35]; - assign link_sif_o[45] = out_packet_i[34]; - assign link_sif_o[44] = out_packet_i[33]; - assign link_sif_o[43] = out_packet_i[32]; - assign link_sif_o[42] = out_packet_i[31]; - assign link_sif_o[41] = out_packet_i[30]; - assign link_sif_o[40] = out_packet_i[29]; - assign link_sif_o[39] = out_packet_i[28]; - assign link_sif_o[38] = out_packet_i[27]; - assign link_sif_o[37] = out_packet_i[26]; - assign link_sif_o[36] = out_packet_i[25]; - assign link_sif_o[35] = out_packet_i[24]; - assign link_sif_o[34] = out_packet_i[23]; - assign link_sif_o[33] = out_packet_i[22]; - assign link_sif_o[32] = out_packet_i[21]; - assign link_sif_o[31] = out_packet_i[20]; - assign link_sif_o[30] = out_packet_i[19]; - assign link_sif_o[29] = out_packet_i[18]; - assign link_sif_o[28] = out_packet_i[17]; - assign link_sif_o[27] = out_packet_i[16]; - assign link_sif_o[26] = out_packet_i[15]; - assign link_sif_o[25] = out_packet_i[14]; - assign link_sif_o[24] = out_packet_i[13]; - assign link_sif_o[23] = out_packet_i[12]; - assign link_sif_o[22] = out_packet_i[11]; - assign link_sif_o[21] = out_packet_i[10]; - assign link_sif_o[20] = out_packet_i[9]; - assign link_sif_o[19] = out_packet_i[8]; - assign link_sif_o[18] = out_packet_i[7]; - assign link_sif_o[17] = out_packet_i[6]; - assign link_sif_o[16] = out_packet_i[5]; - assign link_sif_o[15] = out_packet_i[4]; - assign link_sif_o[14] = out_packet_i[3]; - assign link_sif_o[13] = out_packet_i[2]; - assign link_sif_o[12] = out_packet_i[1]; - assign link_sif_o[11] = out_packet_i[0]; - assign link_sif_o[10] = fifo_yumi_i; - assign link_sif_o[8] = fifo_data_o[17]; - assign link_sif_o[7] = fifo_data_o[16]; - assign link_sif_o[6] = fifo_data_o[15]; - assign link_sif_o[5] = fifo_data_o[14]; - assign link_sif_o[4] = fifo_data_o[13]; - assign link_sif_o[3] = fifo_data_o[12]; - assign link_sif_o[2] = fifo_data_o[11]; - assign link_sif_o[1] = fifo_data_o[10]; - assign link_sif_o[0] = fifo_data_o[9]; - - bsg_fifo_1r1w_small_width_p76_els_p4 - fifo - ( - .clk_i(clk_i), - .reset_i(reset_i), - .v_i(link_sif_i[88]), - .ready_o(link_sif_o[87]), - .data_i(link_sif_i[86:11]), - .v_o(fifo_v), - .data_o(fifo_data_o), - .yumi_i(fifo_yumi_i) - ); - - - always @(posedge clk_i) begin - if(1'b1) begin - credit_v_r_o <= link_sif_i[10]; - end - end - - assign fifo_v_o = fifo_v & link_sif_i[9]; - assign in_fifo_full_o = ~link_sif_o[87]; - -endmodule - - - -module bsg_counter_up_down_max_val_p200_init_val_p200 -( - clk_i, - reset_i, - up_i, - down_i, - count_o -); - - output [7:0] count_o; - input clk_i; - input reset_i; - input up_i; - input down_i; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26; - reg [7:0] count_o; - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[7] <= N26; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[6] <= N25; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[5] <= N24; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[4] <= N23; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[3] <= N22; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[2] <= N21; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[1] <= N20; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - count_o[0] <= N19; - end - end - - assign { N10, N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i; - assign { N18, N17, N16, N15, N14, N13, N12, N11 } = { N10, N9, N8, N7, N6, N5, N4, N3 } + up_i; - assign { N26, N25, N24, N23, N22, N21, N20, N19 } = (N0)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N1)? { N18, N17, N16, N15, N14, N13, N12, N11 } : 1'b0; - assign N0 = reset_i; - assign N1 = N2; - assign N2 = ~reset_i; - -endmodule - - - -module bsg_manycore_pkt_decode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 -( - v_i, - data_i, - pkt_freeze_o, - pkt_unfreeze_o, - pkt_arb_cfg_o, - pkt_unknown_o, - pkt_remote_store_o, - data_o, - addr_o, - mask_o -); - - input [75:0] data_i; - output [31:0] data_o; - output [19:0] addr_o; - output [3:0] mask_o; - input v_i; - output pkt_freeze_o; - output pkt_unfreeze_o; - output pkt_arb_cfg_o; - output pkt_unknown_o; - output pkt_remote_store_o; - wire [31:0] data_o; - wire [19:0] addr_o; - wire [3:0] mask_o; - wire pkt_freeze_o,pkt_unfreeze_o,pkt_arb_cfg_o,pkt_unknown_o,pkt_remote_store_o,N0, - N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22, - N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42, - N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62, - N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75; - assign addr_o[19] = data_i[75]; - assign addr_o[18] = data_i[74]; - assign addr_o[17] = data_i[73]; - assign addr_o[16] = data_i[72]; - assign addr_o[15] = data_i[71]; - assign addr_o[14] = data_i[70]; - assign addr_o[13] = data_i[69]; - assign addr_o[12] = data_i[68]; - assign addr_o[11] = data_i[67]; - assign addr_o[10] = data_i[66]; - assign addr_o[9] = data_i[65]; - assign addr_o[8] = data_i[64]; - assign addr_o[7] = data_i[63]; - assign addr_o[6] = data_i[62]; - assign addr_o[5] = data_i[61]; - assign addr_o[4] = data_i[60]; - assign addr_o[3] = data_i[59]; - assign addr_o[2] = data_i[58]; - assign addr_o[1] = data_i[57]; - assign addr_o[0] = data_i[56]; - assign data_o[31] = data_i[49]; - assign data_o[30] = data_i[48]; - assign data_o[29] = data_i[47]; - assign data_o[28] = data_i[46]; - assign data_o[27] = data_i[45]; - assign data_o[26] = data_i[44]; - assign data_o[25] = data_i[43]; - assign data_o[24] = data_i[42]; - assign data_o[23] = data_i[41]; - assign data_o[22] = data_i[40]; - assign data_o[21] = data_i[39]; - assign data_o[20] = data_i[38]; - assign data_o[19] = data_i[37]; - assign data_o[18] = data_i[36]; - assign data_o[17] = data_i[35]; - assign data_o[16] = data_i[34]; - assign data_o[15] = data_i[33]; - assign data_o[14] = data_i[32]; - assign data_o[13] = data_i[31]; - assign data_o[12] = data_i[30]; - assign data_o[11] = data_i[29]; - assign data_o[10] = data_i[28]; - assign data_o[9] = data_i[27]; - assign data_o[8] = data_i[26]; - assign data_o[7] = data_i[25]; - assign data_o[6] = data_i[24]; - assign data_o[5] = data_i[23]; - assign data_o[4] = data_i[22]; - assign data_o[3] = data_i[21]; - assign data_o[2] = data_i[20]; - assign data_o[1] = data_i[19]; - assign data_o[0] = data_i[18]; - assign N11 = data_i[55] | N10; - assign N14 = N13 | data_i[54]; - assign N16 = data_i[55] & data_i[54]; - assign N17 = N13 & N10; - assign N36 = ~data_i[56]; - assign N37 = data_i[74] | data_i[75]; - assign N38 = data_i[73] | N37; - assign N39 = data_i[72] | N38; - assign N40 = data_i[71] | N39; - assign N41 = data_i[70] | N40; - assign N42 = data_i[69] | N41; - assign N43 = data_i[68] | N42; - assign N44 = data_i[67] | N43; - assign N45 = data_i[66] | N44; - assign N46 = data_i[65] | N45; - assign N47 = data_i[64] | N46; - assign N48 = data_i[63] | N47; - assign N49 = data_i[62] | N48; - assign N50 = data_i[61] | N49; - assign N51 = data_i[60] | N50; - assign N52 = data_i[59] | N51; - assign N53 = data_i[58] | N52; - assign N54 = data_i[57] | N53; - assign N55 = N36 | N54; - assign N56 = ~N55; - assign N23 = (N0)? data_i[18] : - (N1)? 1'b0 : - (N2)? 1'b0 : 1'b0; - assign N0 = N19; - assign N1 = N75; - assign N2 = 1'b0; - assign N24 = (N0)? N22 : - (N1)? 1'b0 : - (N2)? 1'b0 : 1'b0; - assign N25 = (N0)? 1'b0 : - (N3)? 1'b1 : - (N21)? 1'b0 : 1'b0; - assign N3 = N56; - assign N26 = (N0)? 1'b0 : - (N3)? 1'b0 : - (N21)? 1'b1 : 1'b0; - assign N27 = (N4)? 1'b1 : - (N5)? 1'b0 : - (N6)? 1'b0 : 1'b0; - assign N4 = N12; - assign N5 = N15; - assign N6 = N18; - assign { N31, N30, N29, N28 } = (N4)? data_i[53:50] : - (N5)? { 1'b0, 1'b0, 1'b0, 1'b0 } : - (N6)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N32 = (N4)? 1'b0 : - (N5)? N26 : - (N6)? 1'b1 : 1'b0; - assign N33 = (N4)? 1'b0 : - (N5)? N23 : - (N6)? 1'b0 : 1'b0; - assign N34 = (N4)? 1'b0 : - (N5)? N24 : - (N6)? 1'b0 : 1'b0; - assign N35 = (N4)? 1'b0 : - (N5)? N25 : - (N6)? 1'b0 : 1'b0; - assign pkt_freeze_o = (N7)? N33 : - (N8)? 1'b0 : 1'b0; - assign N7 = v_i; - assign N8 = N9; - assign pkt_unfreeze_o = (N7)? N34 : - (N8)? 1'b0 : 1'b0; - assign pkt_arb_cfg_o = (N7)? N35 : - (N8)? 1'b0 : 1'b0; - assign pkt_remote_store_o = (N7)? N27 : - (N8)? 1'b0 : 1'b0; - assign mask_o = (N7)? { N31, N30, N29, N28 } : - (N8)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign pkt_unknown_o = (N7)? N32 : - (N8)? 1'b0 : 1'b0; - assign N9 = ~v_i; - assign N10 = ~data_i[54]; - assign N12 = ~N11; - assign N13 = ~data_i[55]; - assign N15 = ~N14; - assign N18 = N16 | N17; - assign N19 = ~N75; - assign N75 = N74 | data_i[56]; - assign N74 = N73 | data_i[57]; - assign N73 = N72 | data_i[58]; - assign N72 = N71 | data_i[59]; - assign N71 = N70 | data_i[60]; - assign N70 = N69 | data_i[61]; - assign N69 = N68 | data_i[62]; - assign N68 = N67 | data_i[63]; - assign N67 = N66 | data_i[64]; - assign N66 = N65 | data_i[65]; - assign N65 = N64 | data_i[66]; - assign N64 = N63 | data_i[67]; - assign N63 = N62 | data_i[68]; - assign N62 = N61 | data_i[69]; - assign N61 = N60 | data_i[70]; - assign N60 = N59 | data_i[71]; - assign N59 = N58 | data_i[72]; - assign N58 = N57 | data_i[73]; - assign N57 = data_i[75] | data_i[74]; - assign N20 = N56 | N19; - assign N21 = ~N20; - assign N22 = ~data_i[18]; - -endmodule - - - -module bsg_manycore_endpoint_standard_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20_max_out_credits_p200_debug_p0 -( - clk_i, - reset_i, - link_sif_i, - link_sif_o, - in_v_o, - in_yumi_i, - in_data_o, - in_mask_o, - in_addr_o, - out_v_i, - out_packet_i, - out_ready_o, - out_credits_o, - my_x_i, - my_y_i, - freeze_r_o, - reverse_arb_pr_o -); - - input [88:0] link_sif_i; - output [88:0] link_sif_o; - output [31:0] in_data_o; - output [3:0] in_mask_o; - output [19:0] in_addr_o; - input [75:0] out_packet_i; - output [7:0] out_credits_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - input in_yumi_i; - input out_v_i; - output in_v_o; - output out_ready_o; - output freeze_r_o; - output reverse_arb_pr_o; - wire [88:0] link_sif_o; - wire [31:0] in_data_o; - wire [3:0] in_mask_o; - wire [19:0] in_addr_o; - wire [7:0] out_credits_o; - wire in_v_o,out_ready_o,reverse_arb_pr_o,N0,N1,cgni_v,cgni_yumi,in_fifo_full, - credit_return_lo,launching_out,pkt_freeze,pkt_unfreeze,pkt_arb_cfg,pkt_unknown,N2,N3,N4, - N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18; - wire [75:0] cgni_data; - reg freeze_r_o,arb_cfg_r; - - bsg_manycore_endpoint_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20 - bme - ( - .clk_i(clk_i), - .reset_i(reset_i), - .link_sif_i(link_sif_i), - .link_sif_o(link_sif_o), - .fifo_data_o(cgni_data), - .fifo_v_o(cgni_v), - .fifo_yumi_i(cgni_yumi), - .out_packet_i(out_packet_i), - .out_v_i(out_v_i), - .out_ready_o(out_ready_o), - .credit_v_r_o(credit_return_lo), - .in_fifo_full_o(in_fifo_full) - ); - - - bsg_counter_up_down_max_val_p200_init_val_p200 - out_credit_ctr - ( - .clk_i(clk_i), - .reset_i(reset_i), - .up_i(credit_return_lo), - .down_i(launching_out), - .count_o(out_credits_o) - ); - - - bsg_manycore_pkt_decode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 - pkt_decode - ( - .v_i(cgni_v), - .data_i(cgni_data), - .pkt_freeze_o(pkt_freeze), - .pkt_unfreeze_o(pkt_unfreeze), - .pkt_arb_cfg_o(pkt_arb_cfg), - .pkt_unknown_o(pkt_unknown), - .pkt_remote_store_o(in_v_o), - .data_o(in_data_o), - .addr_o(in_addr_o), - .mask_o(in_mask_o) - ); - - - always @(posedge clk_i) begin - if(N6) begin - freeze_r_o <= N7; - end - end - - - always @(posedge clk_i) begin - if(N13) begin - arb_cfg_r <= N14; - end - end - - assign N6 = (N0)? 1'b1 : - (N9)? 1'b1 : - (N5)? 1'b0 : 1'b0; - assign N0 = N3; - assign N7 = (N0)? 1'b1 : - (N9)? pkt_freeze : 1'b0; - assign N13 = (N1)? 1'b1 : - (N16)? 1'b1 : - (N12)? 1'b0 : 1'b0; - assign N1 = N10; - assign N14 = (N1)? 1'b1 : - (N16)? in_data_o[0] : 1'b0; - assign launching_out = out_v_i & out_ready_o; - assign cgni_yumi = N18 | pkt_arb_cfg; - assign N18 = N17 | pkt_unfreeze; - assign N17 = in_yumi_i | pkt_freeze; - assign N2 = pkt_freeze | pkt_unfreeze; - assign N3 = reset_i; - assign N4 = N2 | N3; - assign N5 = ~N4; - assign N8 = ~N3; - assign N9 = N2 & N8; - assign N10 = reset_i; - assign N11 = pkt_arb_cfg | N10; - assign N12 = ~N11; - assign N15 = ~N10; - assign N16 = pkt_arb_cfg & N15; - assign reverse_arb_pr_o = arb_cfg_r & in_fifo_full; - -endmodule - - - -module bsg_mem_1rw_sync_width_p32_els_p1024 -( - clk_i, - reset_i, - data_i, - addr_i, - v_i, - w_i, - data_o -); - - input [31:0] data_i; - input [9:0] addr_i; - output [31:0] data_o; - input clk_i; - input reset_i; - input v_i; - input w_i; - wire [31:0] data_o; - wire n_0_net_; - - tsmc65lp_1rf_lg10_w32_all - macro_mem - ( - .CLK(clk_i), - .Q(data_o), - .CEN(n_0_net_), - .A(addr_i), - .D(data_i), - .EMA({ 1'b0, 1'b1, 1'b1 }), - .EMAW({ 1'b0, 1'b1 }), - .RET1N(1'b1) - ); - - assign n_0_net_ = ~v_i; - -endmodule - - - -module cl_decode -( - instruction_i, - decode_o_op_writes_rf_, - decode_o_is_load_op_, - decode_o_is_store_op_, - decode_o_is_mem_op_, - decode_o_is_byte_op_, - decode_o_is_hex_op_, - decode_o_is_load_unsigned_, - decode_o_is_branch_op_, - decode_o_is_jump_op_, - decode_o_op_reads_rf1_, - decode_o_op_reads_rf2_, - decode_o_op_is_auipc_, - decode_o_is_md_instr_, - decode_o_is_fence_op_, - decode_o_is_fence_i_op_, - decode_o_op_is_load_reservation_, - decode_o_op_is_lr_acq_ -); - - input [31:0] instruction_i; - output decode_o_op_writes_rf_; - output decode_o_is_load_op_; - output decode_o_is_store_op_; - output decode_o_is_mem_op_; - output decode_o_is_byte_op_; - output decode_o_is_hex_op_; - output decode_o_is_load_unsigned_; - output decode_o_is_branch_op_; - output decode_o_is_jump_op_; - output decode_o_op_reads_rf1_; - output decode_o_op_reads_rf2_; - output decode_o_op_is_auipc_; - output decode_o_is_md_instr_; - output decode_o_is_fence_op_; - output decode_o_is_fence_i_op_; - output decode_o_op_is_load_reservation_; - output decode_o_op_is_lr_acq_; - wire decode_o_op_writes_rf_,decode_o_is_load_op_,decode_o_is_store_op_, - decode_o_is_mem_op_,decode_o_is_byte_op_,decode_o_is_hex_op_,decode_o_is_load_unsigned_, - decode_o_is_branch_op_,decode_o_is_jump_op_,decode_o_op_reads_rf1_, - decode_o_op_reads_rf2_,decode_o_op_is_auipc_,decode_o_is_md_instr_,decode_o_is_fence_op_, - decode_o_is_fence_i_op_,decode_o_op_is_load_reservation_,decode_o_op_is_lr_acq_,N0,N1,N2, - N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24, - N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44, - N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64, - N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84, - N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103, - N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119, - N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135, - N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,N151, - N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,N166,N167, - N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,N182,N183, - N184,N185,N186,N187,N188,N189,N190; - assign N9 = instruction_i[1] & instruction_i[0]; - assign N11 = instruction_i[6] | N89; - assign N12 = N90 | instruction_i[3]; - assign N13 = N11 | N12; - assign N14 = N13 | N106; - assign N15 = instruction_i[6] | instruction_i[5]; - assign N16 = N15 | N12; - assign N17 = N16 | N106; - assign N18 = N84 | N89; - assign N19 = instruction_i[4] | N105; - assign N20 = N18 | N19; - assign N21 = N20 | N106; - assign N22 = instruction_i[4] | instruction_i[3]; - assign N23 = N18 | N22; - assign N24 = N23 | N106; - assign N25 = N84 & N89; - assign N26 = N90 & N105; - assign N27 = N25 & N26; - assign N28 = N27 & N106; - assign N29 = N13 | instruction_i[2]; - assign N30 = N16 | instruction_i[2]; - assign N31 = N11 | N19; - assign N32 = N31 | N106; - assign N34 = N84 & N90; - assign N35 = N34 & N9; - assign N37 = N89 & N105; - assign N38 = N37 & N106; - assign N39 = N89 | instruction_i[3]; - assign N40 = N39 | instruction_i[2]; - assign N41 = instruction_i[5] & instruction_i[3]; - assign N42 = N41 & instruction_i[2]; - assign N45 = N44 & N131; - assign N47 = instruction_i[13] | N131; - assign N51 = N11 | N22; - assign N52 = N55 | N92; - assign N53 = N51 | N52; - assign N55 = instruction_i[2] | N91; - assign N56 = N23 | N55; - assign N58 = instruction_i[6] & instruction_i[5]; - assign N59 = N90 & instruction_i[2]; - assign N60 = N58 & N59; - assign N61 = N60 & N9; - assign N62 = N106 | N92; - assign N63 = N23 | N62; - assign N64 = N58 & N26; - assign N65 = N64 & N106; - assign N66 = instruction_i[2] | N92; - assign N67 = N15 | N22; - assign N68 = N67 | N66; - assign N69 = N51 | N66; - assign N70 = N13 | N66; - assign N71 = N16 | N66; - assign N72 = N31 | N62; - assign N74 = instruction_i[5] & N105; - assign N75 = N106 & instruction_i[1]; - assign N76 = N74 & N75; - assign N78 = instruction_i[6] & N90; - assign N79 = instruction_i[6] | instruction_i[4]; - assign N80 = N79 | N92; - assign N81 = instruction_i[6] | N90; - assign N82 = N81 | N92; - assign N85 = N106 | N91; - assign N86 = N85 | N92; - assign N87 = N16 | N86; - assign N89 = ~instruction_i[5]; - assign N90 = ~instruction_i[4]; - assign N91 = ~instruction_i[1]; - assign N92 = ~instruction_i[0]; - assign N93 = N89 | instruction_i[6]; - assign N94 = N90 | N93; - assign N95 = instruction_i[3] | N94; - assign N96 = instruction_i[2] | N95; - assign N97 = N91 | N96; - assign N98 = N92 | N97; - assign N99 = ~N98; - assign N100 = ~instruction_i[25]; - assign N101 = instruction_i[27] | N129; - assign N102 = instruction_i[26] | N101; - assign N103 = N100 | N102; - assign N104 = ~N103; - assign N105 = ~instruction_i[3]; - assign N106 = ~instruction_i[2]; - assign N107 = instruction_i[5] | instruction_i[6]; - assign N108 = instruction_i[4] | N107; - assign N109 = N105 | N108; - assign N110 = N106 | N109; - assign N111 = N91 | N110; - assign N112 = N92 | N111; - assign N113 = ~N112; - assign N114 = instruction_i[13] | instruction_i[14]; - assign N115 = instruction_i[12] | N114; - assign N116 = ~N115; - assign N117 = instruction_i[18] | instruction_i[19]; - assign N118 = instruction_i[17] | N117; - assign N119 = instruction_i[16] | N118; - assign N120 = instruction_i[15] | N119; - assign N121 = ~N120; - assign N122 = instruction_i[10] | instruction_i[11]; - assign N123 = instruction_i[9] | N122; - assign N124 = instruction_i[8] | N123; - assign N125 = instruction_i[7] | N124; - assign N126 = ~N125; - assign N127 = instruction_i[30] | instruction_i[31]; - assign N128 = instruction_i[29] | N127; - assign N129 = instruction_i[28] | N128; - assign N130 = ~N129; - assign N131 = ~instruction_i[12]; - assign N132 = N131 | N114; - assign N133 = ~N132; - assign N134 = instruction_i[25] | N102; - assign N135 = instruction_i[24] | N134; - assign N136 = instruction_i[23] | N135; - assign N137 = instruction_i[22] | N136; - assign N138 = instruction_i[21] | N137; - assign N139 = instruction_i[20] | N138; - assign N140 = ~N139; - assign decode_o_op_writes_rf_ = (N0)? N33 : - (N10)? 1'b0 : 1'b0; - assign N0 = N9; - assign decode_o_is_mem_op_ = (N1)? N43 : - (N36)? 1'b0 : 1'b0; - assign N1 = N35; - assign decode_o_is_byte_op_ = (N2)? decode_o_is_mem_op_ : - (N46)? 1'b0 : 1'b0; - assign N2 = N45; - assign decode_o_is_hex_op_ = (N3)? decode_o_is_mem_op_ : - (N4)? 1'b0 : 1'b0; - assign N3 = N48; - assign N4 = N47; - assign decode_o_is_load_op_ = (N1)? N49 : - (N36)? 1'b0 : 1'b0; - assign decode_o_is_load_unsigned_ = (N5)? decode_o_is_load_op_ : - (N50)? 1'b0 : 1'b0; - assign N5 = instruction_i[14]; - assign decode_o_op_reads_rf1_ = (N6)? N73 : - (N7)? 1'b0 : 1'b0; - assign N6 = instruction_i[1]; - assign N7 = N91; - assign decode_o_op_reads_rf2_ = (N8)? N83 : - (N77)? 1'b0 : 1'b0; - assign N8 = N76; - assign N10 = ~N9; - assign N33 = N152 | N153; - assign N152 = N150 | N151; - assign N150 = N148 | N149; - assign N148 = N147 | N28; - assign N147 = N145 | N146; - assign N145 = N143 | N144; - assign N143 = N141 | N142; - assign N141 = ~N14; - assign N142 = ~N17; - assign N144 = ~N21; - assign N146 = ~N24; - assign N149 = ~N29; - assign N151 = ~N30; - assign N153 = ~N32; - assign N36 = ~N35; - assign N43 = N155 | N42; - assign N155 = N38 | N154; - assign N154 = ~N40; - assign N44 = ~instruction_i[13]; - assign N46 = ~N45; - assign N48 = ~N47; - assign N49 = N38 | N42; - assign N50 = ~instruction_i[14]; - assign N54 = ~N53; - assign decode_o_is_store_op_ = N54; - assign N57 = ~N56; - assign decode_o_is_branch_op_ = N57; - assign decode_o_is_jump_op_ = N61; - assign N73 = N165 | N166; - assign N165 = N163 | N164; - assign N163 = N161 | N162; - assign N161 = N159 | N160; - assign N159 = N157 | N158; - assign N157 = N156 | N65; - assign N156 = ~N63; - assign N158 = ~N68; - assign N160 = ~N69; - assign N162 = ~N70; - assign N164 = ~N71; - assign N166 = ~N72; - assign N77 = ~N76; - assign N83 = N168 | N169; - assign N168 = N78 | N167; - assign N167 = ~N80; - assign N169 = ~N82; - assign N84 = ~instruction_i[6]; - assign N88 = ~N87; - assign decode_o_op_is_auipc_ = N88; - assign decode_o_is_md_instr_ = N99 & N104; - assign decode_o_op_is_load_reservation_ = ~N184; - assign N184 = N183 | N92; - assign N183 = N182 | N91; - assign N182 = N181 | N106; - assign N181 = N180 | N105; - assign N180 = N179 | instruction_i[4]; - assign N179 = N178 | N89; - assign N178 = N177 | instruction_i[6]; - assign N177 = N176 | instruction_i[12]; - assign N176 = N175 | N44; - assign N175 = N174 | instruction_i[14]; - assign N174 = N173 | instruction_i[27]; - assign N173 = N171 | N172; - assign N171 = N170 | instruction_i[29]; - assign N170 = instruction_i[31] | instruction_i[30]; - assign N172 = ~instruction_i[28]; - assign decode_o_op_is_lr_acq_ = decode_o_op_is_load_reservation_ & instruction_i[26]; - assign decode_o_is_fence_op_ = N187 & N130; - assign N187 = N186 & N126; - assign N186 = N185 & N121; - assign N185 = N113 & N116; - assign decode_o_is_fence_i_op_ = N190 & N140; - assign N190 = N189 & N126; - assign N189 = N188 & N121; - assign N188 = N113 & N133; - -endmodule - - - -module bsg_mem_2r1w_sync_32_32_0_5_0 -( - clk_i, - reset_i, - w_v_i, - w_addr_i, - w_data_i, - r0_v_i, - r0_addr_i, - r0_data_o, - r1_v_i, - r1_addr_i, - r1_data_o -); - - input [4:0] w_addr_i; - input [31:0] w_data_i; - input [4:0] r0_addr_i; - output [31:0] r0_data_o; - input [4:0] r1_addr_i; - output [31:0] r1_data_o; - input clk_i; - input reset_i; - input w_v_i; - input r0_v_i; - input r1_v_i; - wire [31:0] r0_data_o,r1_data_o; - wire n_0_net_,n_1_net_,n_5_net_,n_6_net_; - - tsmc65lp_2rf_lg5_w32_all - macro_mem0 - ( - .CLKA(clk_i), - .AA(r0_addr_i), - .CENA(n_0_net_), - .QA(r0_data_o), - .CLKB(clk_i), - .AB(w_addr_i), - .DB(w_data_i), - .CENB(n_1_net_), - .EMAA({ 1'b0, 1'b1, 1'b1 }), - .EMAB({ 1'b0, 1'b1, 1'b1 }), - .RET1N(1'b1) - ); - - - tsmc65lp_2rf_lg5_w32_all - macro_mem1 - ( - .CLKA(clk_i), - .AA(r1_addr_i), - .CENA(n_5_net_), - .QA(r1_data_o), - .CLKB(clk_i), - .AB(w_addr_i), - .DB(w_data_i), - .CENB(n_6_net_), - .EMAA({ 1'b0, 1'b1, 1'b1 }), - .EMAB({ 1'b0, 1'b1, 1'b1 }), - .RET1N(1'b1) - ); - - assign n_1_net_ = ~w_v_i; - assign n_0_net_ = ~r0_v_i; - assign n_6_net_ = ~w_v_i; - assign n_5_net_ = ~r1_v_i; - -endmodule - - - -module rf_2r1w_sync_wrapper_width_p32_els_p32 -( - clk_i, - reset_i, - w_v_i, - w_addr_i, - w_data_i, - r0_v_i, - r0_addr_i, - r0_data_o, - r1_v_i, - r1_addr_i, - r1_data_o -); - - input [4:0] w_addr_i; - input [31:0] w_data_i; - input [4:0] r0_addr_i; - output [31:0] r0_data_o; - input [4:0] r1_addr_i; - output [31:0] r1_data_o; - input clk_i; - input reset_i; - input w_v_i; - input r0_v_i; - input r1_v_i; - wire [31:0] r0_data_o,r1_data_o,r0_mem_data,r1_mem_data,r0_data_safe,r1_data_safe; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19, - r0_rw_same_addr,N20,r1_rw_same_addr,N21,r0_wrapper_v,N22,r1_wrapper_v,N23,N24,N25,N26,N27, - N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47, - N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67, - N68,update_hold_reg0,N69,update_hold_reg1,N70,N71,N72,N73,N74,N75,N76,N77,N78, - N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98, - N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114, - N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130, - N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141; - reg r1_rw_same_addr_r,r0_rw_same_addr_r,r0_v_r,r1_v_r; - reg [31:0] w_data_r,r0_data_r,r1_data_r; - reg [4:0] r0_addr_r,r1_addr_r; - assign N19 = w_addr_i == r0_addr_i; - assign N20 = w_addr_i == r1_addr_i; - - bsg_mem_2r1w_sync_32_32_0_5_0 - rf_mem - ( - .clk_i(clk_i), - .reset_i(reset_i), - .w_v_i(w_v_i), - .w_addr_i(w_addr_i), - .w_data_i(w_data_i), - .r0_v_i(r0_wrapper_v), - .r0_addr_i(r0_addr_i), - .r0_data_o(r0_mem_data), - .r1_v_i(r1_wrapper_v), - .r1_addr_i(r1_addr_i), - .r1_data_o(r1_mem_data) - ); - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_rw_same_addr_r <= N26; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_rw_same_addr_r <= N25; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[31] <= N63; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[30] <= N62; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[29] <= N61; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[28] <= N60; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[27] <= N59; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[26] <= N58; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[25] <= N57; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[24] <= N56; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[23] <= N55; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[22] <= N54; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[21] <= N53; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[20] <= N52; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[19] <= N51; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[18] <= N50; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[17] <= N49; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[16] <= N48; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[15] <= N47; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[14] <= N46; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[13] <= N45; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[12] <= N44; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[11] <= N43; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[10] <= N42; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[9] <= N41; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[8] <= N40; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[7] <= N39; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[6] <= N38; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[5] <= N37; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[4] <= N36; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[3] <= N35; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[2] <= N34; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[1] <= N33; - end - end - - - always @(posedge clk_i) begin - if(N31) begin - w_data_r[0] <= N32; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_addr_r[4] <= r0_addr_i[4]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_addr_r[3] <= r0_addr_i[3]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_addr_r[2] <= r0_addr_i[2]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_addr_r[1] <= r0_addr_i[1]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_addr_r[0] <= r0_addr_i[0]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_addr_r[4] <= r1_addr_i[4]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_addr_r[3] <= r1_addr_i[3]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_addr_r[2] <= r1_addr_i[2]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_addr_r[1] <= r1_addr_i[1]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_addr_r[0] <= r1_addr_i[0]; - end - end - - assign N68 = r0_addr_r == w_addr_i; - assign N69 = r1_addr_r == w_addr_i; - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[31] <= N102; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[30] <= N101; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[29] <= N100; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[28] <= N99; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[27] <= N98; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[26] <= N97; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[25] <= N96; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[24] <= N95; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[23] <= N94; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[22] <= N93; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[21] <= N92; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[20] <= N91; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[19] <= N90; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[18] <= N89; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[17] <= N88; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[16] <= N87; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[15] <= N86; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[14] <= N85; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[13] <= N84; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[12] <= N83; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[11] <= N82; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[10] <= N81; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[9] <= N80; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[8] <= N79; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[7] <= N78; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[6] <= N77; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[5] <= N76; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[4] <= N75; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[3] <= N74; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[2] <= N73; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[1] <= N72; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_data_r[0] <= N71; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[31] <= N135; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[30] <= N134; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[29] <= N133; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[28] <= N132; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[27] <= N131; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[26] <= N130; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[25] <= N129; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[24] <= N128; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[23] <= N127; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[22] <= N126; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[21] <= N125; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[20] <= N124; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[19] <= N123; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[18] <= N122; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[17] <= N121; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[16] <= N120; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[15] <= N119; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[14] <= N118; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[13] <= N117; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[12] <= N116; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[11] <= N115; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[10] <= N114; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[9] <= N113; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[8] <= N112; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[7] <= N111; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[6] <= N110; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[5] <= N109; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[4] <= N108; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[3] <= N107; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[2] <= N106; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[1] <= N105; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_data_r[0] <= N104; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r0_v_r <= r0_v_i; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - r1_v_r <= r1_v_i; - end - end - - assign r0_wrapper_v = (N0)? 1'b0 : - (N1)? r0_v_i : 1'b0; - assign N0 = r0_rw_same_addr; - assign N1 = N21; - assign r1_wrapper_v = (N2)? 1'b0 : - (N3)? r1_v_i : 1'b0; - assign N2 = r1_rw_same_addr; - assign N3 = N22; - assign N25 = (N4)? 1'b0 : - (N5)? r0_rw_same_addr : 1'b0; - assign N4 = N24; - assign N5 = N23; - assign N26 = (N4)? 1'b0 : - (N5)? r1_rw_same_addr : 1'b0; - assign N31 = (N6)? 1'b1 : - (N65)? 1'b1 : - (N30)? 1'b0 : 1'b0; - assign N6 = N27; - assign { N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32 } = (N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N65)? w_data_i : 1'b0; - assign r0_data_safe = (N7)? w_data_r : - (N8)? r0_mem_data : 1'b0; - assign N7 = r0_rw_same_addr_r; - assign N8 = N66; - assign r1_data_safe = (N9)? w_data_r : - (N10)? r1_mem_data : 1'b0; - assign N9 = r1_rw_same_addr_r; - assign N10 = N67; - assign { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } = (N11)? w_data_i : - (N12)? r0_data_o : 1'b0; - assign N11 = update_hold_reg0; - assign N12 = N70; - assign { N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104 } = (N13)? w_data_i : - (N14)? r1_data_o : 1'b0; - assign N13 = update_hold_reg1; - assign N14 = N103; - assign r0_data_o = (N15)? r0_data_safe : - (N16)? r0_data_r : 1'b0; - assign N15 = r0_v_r; - assign N16 = N136; - assign r1_data_o = (N17)? r1_data_safe : - (N18)? r1_data_r : 1'b0; - assign N17 = r1_v_r; - assign N18 = N137; - assign r0_rw_same_addr = N138 & N19; - assign N138 = w_v_i & r0_v_i; - assign r1_rw_same_addr = N139 & N20; - assign N139 = w_v_i & r1_v_i; - assign N21 = ~r0_rw_same_addr; - assign N22 = ~r1_rw_same_addr; - assign N23 = ~reset_i; - assign N24 = reset_i; - assign N27 = reset_i; - assign N28 = w_v_i; - assign N29 = N28 | N27; - assign N30 = ~N29; - assign N64 = ~N27; - assign N65 = N28 & N64; - assign N66 = ~r0_rw_same_addr_r; - assign N67 = ~r1_rw_same_addr_r; - assign update_hold_reg0 = N140 & N68; - assign N140 = r0_v_r & w_v_i; - assign update_hold_reg1 = N141 & N69; - assign N141 = r1_v_r & w_v_i; - assign N70 = ~update_hold_reg0; - assign N103 = ~update_hold_reg1; - assign N136 = ~r0_v_r; - assign N137 = ~r1_v_r; - -endmodule - - - -module bsg_imul_iterative_width_p32 -( - reset_i, - clk_i, - v_i, - ready_o, - opA_i, - signed_opA_i, - opB_i, - signed_opB_i, - gets_high_part_i, - v_o, - result_o, - yumi_i -); - - input [31:0] opA_i; - input [31:0] opB_i; - output [31:0] result_o; - input reset_i; - input clk_i; - input v_i; - input signed_opA_i; - input signed_opB_i; - input gets_high_part_i; - input yumi_i; - output ready_o; - output v_o; - wire ready_o,v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18, - N19,N20,N21,N22,N23,N24,N25,N26,shift_counter_full,N27,N28,N29,N30,N31,N32,N33, - N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53, - N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73, - N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93, - N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110, - N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126, - N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142, - N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158, - N159,N160,N161,N162,N163,N164,N165,N166,adder_neg_op,N167,latch_input,signed_opA, - signed_opB,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181, - N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197, - N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213, - N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229, - N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245, - N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,N260,N261, - N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,N274,N275,N276,N277, - N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,N290,N291,N292,N293, - N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309, - shifted_lsb,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323, - N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,N338,N339, - N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,N354,N355, - N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,N370,N371, - N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,N385,N386,N387, - N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,N401,N402,N403, - N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,N417,N418,N419, - N420,N421,N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,N433,N434,N435, - N436,N437,N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,N449,N450,N451, - N453,N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,N465,N466,N467,N468, - N469,N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,N481,N482,N483,N484, - N485,N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,N497,N498,N499,N500, - N501,N502,N503,N504,N505,N506,N507,N509,N510,N511,N512,N513,N514,N515,N516,N517, - N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,N529; - wire [2:0] next_state; - wire [31:0] adder_a,adder_b; - wire [32:0] adder_result; - reg [2:0] curr_state_r; - reg [5:0] shift_counter_r; - reg signed_opA_r,signed_opB_r,need_neg_result_r,gets_high_part_r,all_sh_lsb_zero_r; - reg [31:0] opA_r,opB_r,result_o; - - always @(posedge clk_i) begin - if(reset_i) begin - curr_state_r[2] <= 1'b0; - end else if(1'b1) begin - curr_state_r[2] <= next_state[2]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - curr_state_r[1] <= 1'b0; - end else if(1'b1) begin - curr_state_r[1] <= next_state[1]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - curr_state_r[0] <= 1'b0; - end else if(1'b1) begin - curr_state_r[0] <= next_state[0]; - end - end - - assign N27 = N448 & N453; - assign N28 = N27 & N449; - assign N29 = curr_state_r[2] | curr_state_r[1]; - assign N30 = N29 | N449; - assign N32 = curr_state_r[2] | N453; - assign N33 = N32 | curr_state_r[0]; - assign N35 = curr_state_r[2] | N453; - assign N36 = N35 | N449; - assign N38 = N448 | curr_state_r[1]; - assign N39 = N38 | curr_state_r[0]; - assign N41 = N448 | curr_state_r[1]; - assign N42 = N41 | N449; - assign N44 = curr_state_r[2] & curr_state_r[1]; - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[5] <= 1'b0; - end else if(N59) begin - shift_counter_r[5] <= N65; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[4] <= 1'b0; - end else if(N59) begin - shift_counter_r[4] <= N64; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[3] <= 1'b0; - end else if(N59) begin - shift_counter_r[3] <= N63; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[2] <= 1'b0; - end else if(N59) begin - shift_counter_r[2] <= N62; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[1] <= 1'b0; - end else if(N59) begin - shift_counter_r[1] <= N61; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - shift_counter_r[0] <= 1'b0; - end else if(N59) begin - shift_counter_r[0] <= N60; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - signed_opA_r <= 1'b0; - end else if(latch_input) begin - signed_opA_r <= signed_opA; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - signed_opB_r <= 1'b0; - end else if(latch_input) begin - signed_opB_r <= signed_opB; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - need_neg_result_r <= 1'b0; - end else if(latch_input) begin - need_neg_result_r <= N168; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - gets_high_part_r <= 1'b0; - end else if(latch_input) begin - gets_high_part_r <= gets_high_part_i; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[31] <= 1'b0; - end else if(N207) begin - opA_r[31] <= N239; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[30] <= 1'b0; - end else if(N207) begin - opA_r[30] <= N238; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[29] <= 1'b0; - end else if(N207) begin - opA_r[29] <= N237; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[28] <= 1'b0; - end else if(N207) begin - opA_r[28] <= N236; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[27] <= 1'b0; - end else if(N207) begin - opA_r[27] <= N235; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[26] <= 1'b0; - end else if(N207) begin - opA_r[26] <= N234; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[25] <= 1'b0; - end else if(N207) begin - opA_r[25] <= N233; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[24] <= 1'b0; - end else if(N207) begin - opA_r[24] <= N232; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[23] <= 1'b0; - end else if(N207) begin - opA_r[23] <= N231; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[22] <= 1'b0; - end else if(N207) begin - opA_r[22] <= N230; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[21] <= 1'b0; - end else if(N207) begin - opA_r[21] <= N229; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[20] <= 1'b0; - end else if(N207) begin - opA_r[20] <= N228; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[19] <= 1'b0; - end else if(N207) begin - opA_r[19] <= N227; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[18] <= 1'b0; - end else if(N207) begin - opA_r[18] <= N226; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[17] <= 1'b0; - end else if(N207) begin - opA_r[17] <= N225; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[16] <= 1'b0; - end else if(N207) begin - opA_r[16] <= N224; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[15] <= 1'b0; - end else if(N207) begin - opA_r[15] <= N223; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[14] <= 1'b0; - end else if(N207) begin - opA_r[14] <= N222; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[13] <= 1'b0; - end else if(N207) begin - opA_r[13] <= N221; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[12] <= 1'b0; - end else if(N207) begin - opA_r[12] <= N220; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[11] <= 1'b0; - end else if(N207) begin - opA_r[11] <= N219; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[10] <= 1'b0; - end else if(N207) begin - opA_r[10] <= N218; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[9] <= 1'b0; - end else if(N207) begin - opA_r[9] <= N217; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[8] <= 1'b0; - end else if(N207) begin - opA_r[8] <= N216; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[7] <= 1'b0; - end else if(N207) begin - opA_r[7] <= N215; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[6] <= 1'b0; - end else if(N207) begin - opA_r[6] <= N214; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[5] <= 1'b0; - end else if(N207) begin - opA_r[5] <= N213; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[4] <= 1'b0; - end else if(N207) begin - opA_r[4] <= N212; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[3] <= 1'b0; - end else if(N207) begin - opA_r[3] <= N211; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[2] <= 1'b0; - end else if(N207) begin - opA_r[2] <= N210; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[1] <= 1'b0; - end else if(N207) begin - opA_r[1] <= N209; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opA_r[0] <= 1'b0; - end else if(N207) begin - opA_r[0] <= N208; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[31] <= 1'b0; - end else if(N276) begin - opB_r[31] <= N308; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[30] <= 1'b0; - end else if(N276) begin - opB_r[30] <= N307; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[29] <= 1'b0; - end else if(N276) begin - opB_r[29] <= N306; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[28] <= 1'b0; - end else if(N276) begin - opB_r[28] <= N305; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[27] <= 1'b0; - end else if(N276) begin - opB_r[27] <= N304; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[26] <= 1'b0; - end else if(N276) begin - opB_r[26] <= N303; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[25] <= 1'b0; - end else if(N276) begin - opB_r[25] <= N302; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[24] <= 1'b0; - end else if(N276) begin - opB_r[24] <= N301; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[23] <= 1'b0; - end else if(N276) begin - opB_r[23] <= N300; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[22] <= 1'b0; - end else if(N276) begin - opB_r[22] <= N299; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[21] <= 1'b0; - end else if(N276) begin - opB_r[21] <= N298; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[20] <= 1'b0; - end else if(N276) begin - opB_r[20] <= N297; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[19] <= 1'b0; - end else if(N276) begin - opB_r[19] <= N296; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[18] <= 1'b0; - end else if(N276) begin - opB_r[18] <= N295; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[17] <= 1'b0; - end else if(N276) begin - opB_r[17] <= N294; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[16] <= 1'b0; - end else if(N276) begin - opB_r[16] <= N293; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[15] <= 1'b0; - end else if(N276) begin - opB_r[15] <= N292; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[14] <= 1'b0; - end else if(N276) begin - opB_r[14] <= N291; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[13] <= 1'b0; - end else if(N276) begin - opB_r[13] <= N290; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[12] <= 1'b0; - end else if(N276) begin - opB_r[12] <= N289; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[11] <= 1'b0; - end else if(N276) begin - opB_r[11] <= N288; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[10] <= 1'b0; - end else if(N276) begin - opB_r[10] <= N287; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[9] <= 1'b0; - end else if(N276) begin - opB_r[9] <= N286; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[8] <= 1'b0; - end else if(N276) begin - opB_r[8] <= N285; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[7] <= 1'b0; - end else if(N276) begin - opB_r[7] <= N284; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[6] <= 1'b0; - end else if(N276) begin - opB_r[6] <= N283; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[5] <= 1'b0; - end else if(N276) begin - opB_r[5] <= N282; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[4] <= 1'b0; - end else if(N276) begin - opB_r[4] <= N281; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[3] <= 1'b0; - end else if(N276) begin - opB_r[3] <= N280; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[2] <= 1'b0; - end else if(N276) begin - opB_r[2] <= N279; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[1] <= 1'b0; - end else if(N276) begin - opB_r[1] <= N278; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - opB_r[0] <= 1'b0; - end else if(N276) begin - opB_r[0] <= N277; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - all_sh_lsb_zero_r <= 1'b0; - end else if(latch_input) begin - all_sh_lsb_zero_r <= 1'b1; - end else if(N456) begin - all_sh_lsb_zero_r <= N310; - end - end - - - always @(posedge clk_i) begin - if(N416) begin - result_o[31] <= 1'b0; - end else if(N383) begin - result_o[31] <= N415; - end - end - - - always @(posedge clk_i) begin - if(N447) begin - result_o[30] <= 1'b0; - end else if(N383) begin - result_o[30] <= N414; - end - end - - - always @(posedge clk_i) begin - if(N446) begin - result_o[29] <= 1'b0; - end else if(N383) begin - result_o[29] <= N413; - end - end - - - always @(posedge clk_i) begin - if(N445) begin - result_o[28] <= 1'b0; - end else if(N383) begin - result_o[28] <= N412; - end - end - - - always @(posedge clk_i) begin - if(N444) begin - result_o[27] <= 1'b0; - end else if(N383) begin - result_o[27] <= N411; - end - end - - - always @(posedge clk_i) begin - if(N443) begin - result_o[26] <= 1'b0; - end else if(N383) begin - result_o[26] <= N410; - end - end - - - always @(posedge clk_i) begin - if(N442) begin - result_o[25] <= 1'b0; - end else if(N383) begin - result_o[25] <= N409; - end - end - - - always @(posedge clk_i) begin - if(N441) begin - result_o[24] <= 1'b0; - end else if(N383) begin - result_o[24] <= N408; - end - end - - - always @(posedge clk_i) begin - if(N440) begin - result_o[23] <= 1'b0; - end else if(N383) begin - result_o[23] <= N407; - end - end - - - always @(posedge clk_i) begin - if(N439) begin - result_o[22] <= 1'b0; - end else if(N383) begin - result_o[22] <= N406; - end - end - - - always @(posedge clk_i) begin - if(N438) begin - result_o[21] <= 1'b0; - end else if(N383) begin - result_o[21] <= N405; - end - end - - - always @(posedge clk_i) begin - if(N437) begin - result_o[20] <= 1'b0; - end else if(N383) begin - result_o[20] <= N404; - end - end - - - always @(posedge clk_i) begin - if(N436) begin - result_o[19] <= 1'b0; - end else if(N383) begin - result_o[19] <= N403; - end - end - - - always @(posedge clk_i) begin - if(N435) begin - result_o[18] <= 1'b0; - end else if(N383) begin - result_o[18] <= N402; - end - end - - - always @(posedge clk_i) begin - if(N434) begin - result_o[17] <= 1'b0; - end else if(N383) begin - result_o[17] <= N401; - end - end - - - always @(posedge clk_i) begin - if(N433) begin - result_o[16] <= 1'b0; - end else if(N383) begin - result_o[16] <= N400; - end - end - - - always @(posedge clk_i) begin - if(N432) begin - result_o[15] <= 1'b0; - end else if(N383) begin - result_o[15] <= N399; - end - end - - - always @(posedge clk_i) begin - if(N431) begin - result_o[14] <= 1'b0; - end else if(N383) begin - result_o[14] <= N398; - end - end - - - always @(posedge clk_i) begin - if(N430) begin - result_o[13] <= 1'b0; - end else if(N383) begin - result_o[13] <= N397; - end - end - - - always @(posedge clk_i) begin - if(N429) begin - result_o[12] <= 1'b0; - end else if(N383) begin - result_o[12] <= N396; - end - end - - - always @(posedge clk_i) begin - if(N428) begin - result_o[11] <= 1'b0; - end else if(N383) begin - result_o[11] <= N395; - end - end - - - always @(posedge clk_i) begin - if(N427) begin - result_o[10] <= 1'b0; - end else if(N383) begin - result_o[10] <= N394; - end - end - - - always @(posedge clk_i) begin - if(N426) begin - result_o[9] <= 1'b0; - end else if(N383) begin - result_o[9] <= N393; - end - end - - - always @(posedge clk_i) begin - if(N425) begin - result_o[8] <= 1'b0; - end else if(N383) begin - result_o[8] <= N392; - end - end - - - always @(posedge clk_i) begin - if(N424) begin - result_o[7] <= 1'b0; - end else if(N383) begin - result_o[7] <= N391; - end - end - - - always @(posedge clk_i) begin - if(N423) begin - result_o[6] <= 1'b0; - end else if(N383) begin - result_o[6] <= N390; - end - end - - - always @(posedge clk_i) begin - if(N422) begin - result_o[5] <= 1'b0; - end else if(N383) begin - result_o[5] <= N389; - end - end - - - always @(posedge clk_i) begin - if(N421) begin - result_o[4] <= 1'b0; - end else if(N383) begin - result_o[4] <= N388; - end - end - - - always @(posedge clk_i) begin - if(N420) begin - result_o[3] <= 1'b0; - end else if(N383) begin - result_o[3] <= N387; - end - end - - - always @(posedge clk_i) begin - if(N419) begin - result_o[2] <= 1'b0; - end else if(N383) begin - result_o[2] <= N386; - end - end - - - always @(posedge clk_i) begin - if(N418) begin - result_o[1] <= 1'b0; - end else if(N383) begin - result_o[1] <= N385; - end - end - - - always @(posedge clk_i) begin - if(N417) begin - result_o[0] <= 1'b0; - end else if(N383) begin - result_o[0] <= N384; - end - end - - assign N416 = reset_i | latch_input; - assign N417 = reset_i | latch_input; - assign N418 = reset_i | latch_input; - assign N419 = reset_i | latch_input; - assign N420 = reset_i | latch_input; - assign N421 = reset_i | latch_input; - assign N422 = reset_i | latch_input; - assign N423 = reset_i | latch_input; - assign N424 = reset_i | latch_input; - assign N425 = reset_i | latch_input; - assign N426 = reset_i | latch_input; - assign N427 = reset_i | latch_input; - assign N428 = reset_i | latch_input; - assign N429 = reset_i | latch_input; - assign N430 = reset_i | latch_input; - assign N431 = reset_i | latch_input; - assign N432 = reset_i | latch_input; - assign N433 = reset_i | latch_input; - assign N434 = reset_i | latch_input; - assign N435 = reset_i | latch_input; - assign N436 = reset_i | latch_input; - assign N437 = reset_i | latch_input; - assign N438 = reset_i | latch_input; - assign N439 = reset_i | latch_input; - assign N440 = reset_i | latch_input; - assign N441 = reset_i | latch_input; - assign N442 = reset_i | latch_input; - assign N443 = reset_i | latch_input; - assign N444 = reset_i | latch_input; - assign N445 = reset_i | latch_input; - assign N446 = reset_i | latch_input; - assign N447 = reset_i | latch_input; - assign N448 = ~curr_state_r[2]; - assign N449 = ~curr_state_r[0]; - assign N450 = curr_state_r[1] | N448; - assign N451 = N449 | N450; - assign v_o = ~N451; - assign N453 = ~curr_state_r[1]; - assign N454 = N453 | curr_state_r[2]; - assign N455 = N449 | N454; - assign N456 = ~N455; - assign N457 = N453 | curr_state_r[2]; - assign N458 = N449 | N457; - assign N459 = ~N458; - assign N460 = N453 | curr_state_r[2]; - assign N461 = N449 | N460; - assign N462 = ~N461; - assign N463 = N453 | curr_state_r[2]; - assign N464 = N449 | N463; - assign N465 = ~N464; - assign N466 = curr_state_r[1] | curr_state_r[2]; - assign N467 = N449 | N466; - assign N468 = ~N467; - assign N469 = N453 | curr_state_r[2]; - assign N470 = N449 | N469; - assign N471 = ~N470; - assign N472 = N453 | curr_state_r[2]; - assign N473 = curr_state_r[0] | N472; - assign N474 = ~N473; - assign N475 = N453 | curr_state_r[2]; - assign N476 = N449 | N475; - assign N477 = ~N476; - assign N478 = curr_state_r[1] | N448; - assign N479 = curr_state_r[0] | N478; - assign N480 = ~N479; - assign N481 = N453 | curr_state_r[2]; - assign N482 = N449 | N481; - assign N483 = ~next_state[1]; - assign N484 = ~next_state[0]; - assign N485 = N483 | next_state[2]; - assign N486 = N484 | N485; - assign N487 = ~N486; - assign N488 = curr_state_r[1] | N448; - assign N489 = curr_state_r[0] | N488; - assign N490 = ~N489; - assign N491 = curr_state_r[1] | curr_state_r[2]; - assign N492 = N449 | N491; - assign N493 = ~N492; - assign N494 = N453 | curr_state_r[2]; - assign N495 = curr_state_r[0] | N494; - assign N496 = ~N495; - assign N497 = curr_state_r[1] | N448; - assign N498 = curr_state_r[0] | N497; - assign N499 = ~N498; - assign N500 = N453 | curr_state_r[2]; - assign N501 = curr_state_r[0] | N500; - assign N502 = ~N501; - assign N503 = curr_state_r[1] | curr_state_r[2]; - assign N504 = N449 | N503; - assign N505 = ~N504; - assign N506 = curr_state_r[1] | curr_state_r[2]; - assign N507 = curr_state_r[0] | N506; - assign ready_o = ~N507; - assign N509 = ~shift_counter_r[4]; - assign N510 = ~shift_counter_r[3]; - assign N511 = ~shift_counter_r[2]; - assign N512 = ~shift_counter_r[1]; - assign N513 = ~shift_counter_r[0]; - assign N514 = N509 | shift_counter_r[5]; - assign N515 = N510 | N514; - assign N516 = N511 | N515; - assign N517 = N512 | N516; - assign N518 = N513 | N517; - assign N519 = ~N518; - assign N520 = ~shift_counter_r[5]; - assign N521 = shift_counter_r[4] | N520; - assign N522 = shift_counter_r[3] | N521; - assign N523 = shift_counter_r[2] | N522; - assign N524 = shift_counter_r[1] | N523; - assign N525 = shift_counter_r[0] | N524; - assign N526 = ~N525; - assign adder_result = adder_a + adder_b; - assign { N58, N57, N56, N55, N54, N53 } = shift_counter_r + 1'b1; - assign shift_counter_full = (N0)? N519 : - (N1)? N526 : 1'b0; - assign N0 = gets_high_part_r; - assign N1 = N26; - assign next_state = (N2)? { 1'b0, 1'b0, v_i } : - (N3)? { 1'b0, 1'b1, 1'b0 } : - (N4)? { 1'b0, 1'b1, 1'b1 } : - (N5)? { shift_counter_full, N45, N45 } : - (N6)? { 1'b1, 1'b0, 1'b1 } : - (N7)? { N46, 1'b0, N46 } : - (N8)? { 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N2 = N28; - assign N3 = N31; - assign N4 = N34; - assign N5 = N37; - assign N6 = N40; - assign N7 = N43; - assign N8 = N44; - assign N59 = (N9)? 1'b1 : - (N67)? 1'b1 : - (N51)? 1'b0 : 1'b0; - assign N9 = N49; - assign { N65, N64, N63, N62, N61, N60 } = (N9)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N67)? { N58, N57, N56, N55, N54, N53 } : 1'b0; - assign adder_a = (N10)? { N71, N72, N73, N74, N75, N76, N77, N78, N79, N80, N81, N82, N83, N84, N85, N86, N87, N88, N89, N90, N91, N92, N93, N94, N95, N96, N97, N98, N99, N100, N101, N102 } : - (N11)? { N103, N104, N105, N106, N107, N108, N109, N110, N111, N112, N113, N114, N115, N116, N117, N118, N119, N120, N121, N122, N123, N124, N125, N126, N127, N128, N129, N130, N131, N132, N133, N134 } : - (N12)? { N135, N136, N137, N138, N139, N140, N141, N142, N143, N144, N145, N146, N147, N148, N149, N150, N151, N152, N153, N154, N155, N156, N157, N158, N159, N160, N161, N162, N163, N164, N165, N166 } : - (N70)? result_o : 1'b0; - assign N10 = N505; - assign N11 = N502; - assign N12 = N490; - assign adder_b = (N13)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N14)? opA_r : 1'b0; - assign N13 = adder_neg_op; - assign N14 = N167; - assign N174 = (N15)? 1'b1 : - (N16)? 1'b1 : - (N173)? 1'b0 : 1'b0; - assign N15 = N170; - assign N16 = N171; - assign { N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175 } = (N15)? { opA_r[30:0], 1'b0 } : - (N16)? adder_result[31:0] : 1'b0; - assign N207 = (N17)? 1'b1 : - (N18)? N174 : 1'b0; - assign N17 = latch_input; - assign N18 = N169; - assign { N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208 } = (N17)? opA_i : - (N18)? { N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175 } : 1'b0; - assign N243 = (N19)? 1'b1 : - (N20)? 1'b1 : - (N242)? 1'b0 : 1'b0; - assign N19 = N459; - assign N20 = N240; - assign { N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244 } = (N19)? { 1'b0, opB_r[31:1] } : - (N20)? adder_result[31:0] : 1'b0; - assign N276 = (N17)? 1'b1 : - (N18)? N243 : 1'b0; - assign { N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277 } = (N17)? opB_i : - (N18)? { N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244 } : 1'b0; - assign shifted_lsb = (N21)? adder_result[0] : - (N309)? result_o[0] : 1'b0; - assign N21 = opB_r[0]; - assign { N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319 } = (N22)? { N135, N136, N137, N138, N139, N140, N141, N142, N143, N144, N145, N146, N147, N148, N149, N150, N151, N152, N153, N154, N155, N156, N157, N158, N159, N160, N161, N162, N163, N164, N165, N166 } : - (N318)? adder_result[31:0] : 1'b0; - assign N22 = N317; - assign { N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351 } = (N0)? adder_result[32:1] : - (N1)? adder_result[31:0] : 1'b0; - assign N383 = (N23)? 1'b1 : - (N24)? 1'b1 : - (N25)? gets_high_part_r : - (N316)? 1'b0 : 1'b0; - assign N23 = N311; - assign N24 = N312; - assign N25 = N313; - assign { N415, N414, N413, N412, N411, N410, N409, N408, N407, N406, N405, N404, N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384 } = (N23)? { N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319 } : - (N24)? { N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351 } : - (N25)? { 1'b0, result_o[31:1] } : 1'b0; - assign N26 = ~gets_high_part_r; - assign N31 = ~N30; - assign N34 = ~N33; - assign N37 = ~N36; - assign N40 = ~N39; - assign N43 = ~N42; - assign N45 = ~shift_counter_full; - assign N46 = ~yumi_i; - assign N47 = ~reset_i; - assign N48 = N47; - assign N49 = N482 & N487; - assign N50 = N465 | N49; - assign N51 = ~N50; - assign N52 = N48 & N67; - assign N66 = ~N49; - assign N67 = N465 & N66; - assign N68 = N502 | N505; - assign N69 = N490 | N68; - assign N70 = ~N69; - assign N71 = ~opA_r[31]; - assign N72 = ~opA_r[30]; - assign N73 = ~opA_r[29]; - assign N74 = ~opA_r[28]; - assign N75 = ~opA_r[27]; - assign N76 = ~opA_r[26]; - assign N77 = ~opA_r[25]; - assign N78 = ~opA_r[24]; - assign N79 = ~opA_r[23]; - assign N80 = ~opA_r[22]; - assign N81 = ~opA_r[21]; - assign N82 = ~opA_r[20]; - assign N83 = ~opA_r[19]; - assign N84 = ~opA_r[18]; - assign N85 = ~opA_r[17]; - assign N86 = ~opA_r[16]; - assign N87 = ~opA_r[15]; - assign N88 = ~opA_r[14]; - assign N89 = ~opA_r[13]; - assign N90 = ~opA_r[12]; - assign N91 = ~opA_r[11]; - assign N92 = ~opA_r[10]; - assign N93 = ~opA_r[9]; - assign N94 = ~opA_r[8]; - assign N95 = ~opA_r[7]; - assign N96 = ~opA_r[6]; - assign N97 = ~opA_r[5]; - assign N98 = ~opA_r[4]; - assign N99 = ~opA_r[3]; - assign N100 = ~opA_r[2]; - assign N101 = ~opA_r[1]; - assign N102 = ~opA_r[0]; - assign N103 = ~opB_r[31]; - assign N104 = ~opB_r[30]; - assign N105 = ~opB_r[29]; - assign N106 = ~opB_r[28]; - assign N107 = ~opB_r[27]; - assign N108 = ~opB_r[26]; - assign N109 = ~opB_r[25]; - assign N110 = ~opB_r[24]; - assign N111 = ~opB_r[23]; - assign N112 = ~opB_r[22]; - assign N113 = ~opB_r[21]; - assign N114 = ~opB_r[20]; - assign N115 = ~opB_r[19]; - assign N116 = ~opB_r[18]; - assign N117 = ~opB_r[17]; - assign N118 = ~opB_r[16]; - assign N119 = ~opB_r[15]; - assign N120 = ~opB_r[14]; - assign N121 = ~opB_r[13]; - assign N122 = ~opB_r[12]; - assign N123 = ~opB_r[11]; - assign N124 = ~opB_r[10]; - assign N125 = ~opB_r[9]; - assign N126 = ~opB_r[8]; - assign N127 = ~opB_r[7]; - assign N128 = ~opB_r[6]; - assign N129 = ~opB_r[5]; - assign N130 = ~opB_r[4]; - assign N131 = ~opB_r[3]; - assign N132 = ~opB_r[2]; - assign N133 = ~opB_r[1]; - assign N134 = ~opB_r[0]; - assign N135 = ~result_o[31]; - assign N136 = ~result_o[30]; - assign N137 = ~result_o[29]; - assign N138 = ~result_o[28]; - assign N139 = ~result_o[27]; - assign N140 = ~result_o[26]; - assign N141 = ~result_o[25]; - assign N142 = ~result_o[24]; - assign N143 = ~result_o[23]; - assign N144 = ~result_o[22]; - assign N145 = ~result_o[21]; - assign N146 = ~result_o[20]; - assign N147 = ~result_o[19]; - assign N148 = ~result_o[18]; - assign N149 = ~result_o[17]; - assign N150 = ~result_o[16]; - assign N151 = ~result_o[15]; - assign N152 = ~result_o[14]; - assign N153 = ~result_o[13]; - assign N154 = ~result_o[12]; - assign N155 = ~result_o[11]; - assign N156 = ~result_o[10]; - assign N157 = ~result_o[9]; - assign N158 = ~result_o[8]; - assign N159 = ~result_o[7]; - assign N160 = ~result_o[6]; - assign N161 = ~result_o[5]; - assign N162 = ~result_o[4]; - assign N163 = ~result_o[3]; - assign N164 = ~result_o[2]; - assign N165 = ~result_o[1]; - assign N166 = ~result_o[0]; - assign adder_neg_op = N527 | N499; - assign N527 = N493 | N496; - assign N167 = ~adder_neg_op; - assign latch_input = v_i & ready_o; - assign signed_opA = signed_opA_i & opA_i[31]; - assign signed_opB = signed_opB_i & opB_i[31]; - assign N168 = signed_opA ^ signed_opB; - assign N169 = ~latch_input; - assign N170 = N471 & N26; - assign N171 = N468 & signed_opA_r; - assign N172 = N171 | N170; - assign N173 = ~N172; - assign N240 = N474 & signed_opB_r; - assign N241 = N240 | N459; - assign N242 = ~N241; - assign N309 = ~opB_r[0]; - assign N310 = all_sh_lsb_zero_r & N528; - assign N528 = ~shifted_lsb; - assign N311 = N480 & need_neg_result_r; - assign N312 = N477 & opB_r[0]; - assign N313 = N462 & N134; - assign N314 = N312 | N311; - assign N315 = N313 | N314; - assign N316 = ~N315; - assign N317 = gets_high_part_r & N529; - assign N529 = ~all_sh_lsb_zero_r; - assign N318 = ~N317; - -endmodule - - - -module bsg_buf_width_p32 -( - i, - o -); - - input [31:0] i; - output [31:0] o; - wire [31:0] o; - assign o[31] = i[31]; - assign o[30] = i[30]; - assign o[29] = i[29]; - assign o[28] = i[28]; - assign o[27] = i[27]; - assign o[26] = i[26]; - assign o[25] = i[25]; - assign o[24] = i[24]; - assign o[23] = i[23]; - assign o[22] = i[22]; - assign o[21] = i[21]; - assign o[20] = i[20]; - assign o[19] = i[19]; - assign o[18] = i[18]; - assign o[17] = i[17]; - assign o[16] = i[16]; - assign o[15] = i[15]; - assign o[14] = i[14]; - assign o[13] = i[13]; - assign o[12] = i[12]; - assign o[11] = i[11]; - assign o[10] = i[10]; - assign o[9] = i[9]; - assign o[8] = i[8]; - assign o[7] = i[7]; - assign o[6] = i[6]; - assign o[5] = i[5]; - assign o[4] = i[4]; - assign o[3] = i[3]; - assign o[2] = i[2]; - assign o[1] = i[1]; - assign o[0] = i[0]; - -endmodule - - - -module bsg_dff_en_width_p1 -( - clock_i, - data_i, - en_i, - data_o -); - - input [0:0] data_i; - output [0:0] data_o; - input clock_i; - input en_i; - reg [0:0] data_o; - - always @(posedge clock_i) begin - if(en_i) begin - data_o[0] <= data_i[0]; - end - end - - -endmodule - - - -module bsg_dff_en_width_p32 -( - clock_i, - data_i, - en_i, - data_o -); - - input [31:0] data_i; - output [31:0] data_o; - input clock_i; - input en_i; - reg [31:0] data_o; - - always @(posedge clock_i) begin - if(en_i) begin - data_o[31] <= data_i[31]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[30] <= data_i[30]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[29] <= data_i[29]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[28] <= data_i[28]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[27] <= data_i[27]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[26] <= data_i[26]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[25] <= data_i[25]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[24] <= data_i[24]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[23] <= data_i[23]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[22] <= data_i[22]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[21] <= data_i[21]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[20] <= data_i[20]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[19] <= data_i[19]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[18] <= data_i[18]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[17] <= data_i[17]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[16] <= data_i[16]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[15] <= data_i[15]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[14] <= data_i[14]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[13] <= data_i[13]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[12] <= data_i[12]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[11] <= data_i[11]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[10] <= data_i[10]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[9] <= data_i[9]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[8] <= data_i[8]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[7] <= data_i[7]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[6] <= data_i[6]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[5] <= data_i[5]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[4] <= data_i[4]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[3] <= data_i[3]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[2] <= data_i[2]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[1] <= data_i[1]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[0] <= data_i[0]; - end - end - - -endmodule - - - -module bsg_mux_width_p33_els_p2 -( - data_i, - sel_i, - data_o -); - - input [65:0] data_i; - input [0:0] sel_i; - output [32:0] data_o; - wire [32:0] data_o; - wire N0,N1; - assign data_o[32] = (N1)? data_i[32] : - (N0)? data_i[65] : 1'b0; - assign N0 = sel_i[0]; - assign data_o[31] = (N1)? data_i[31] : - (N0)? data_i[64] : 1'b0; - assign data_o[30] = (N1)? data_i[30] : - (N0)? data_i[63] : 1'b0; - assign data_o[29] = (N1)? data_i[29] : - (N0)? data_i[62] : 1'b0; - assign data_o[28] = (N1)? data_i[28] : - (N0)? data_i[61] : 1'b0; - assign data_o[27] = (N1)? data_i[27] : - (N0)? data_i[60] : 1'b0; - assign data_o[26] = (N1)? data_i[26] : - (N0)? data_i[59] : 1'b0; - assign data_o[25] = (N1)? data_i[25] : - (N0)? data_i[58] : 1'b0; - assign data_o[24] = (N1)? data_i[24] : - (N0)? data_i[57] : 1'b0; - assign data_o[23] = (N1)? data_i[23] : - (N0)? data_i[56] : 1'b0; - assign data_o[22] = (N1)? data_i[22] : - (N0)? data_i[55] : 1'b0; - assign data_o[21] = (N1)? data_i[21] : - (N0)? data_i[54] : 1'b0; - assign data_o[20] = (N1)? data_i[20] : - (N0)? data_i[53] : 1'b0; - assign data_o[19] = (N1)? data_i[19] : - (N0)? data_i[52] : 1'b0; - assign data_o[18] = (N1)? data_i[18] : - (N0)? data_i[51] : 1'b0; - assign data_o[17] = (N1)? data_i[17] : - (N0)? data_i[50] : 1'b0; - assign data_o[16] = (N1)? data_i[16] : - (N0)? data_i[49] : 1'b0; - assign data_o[15] = (N1)? data_i[15] : - (N0)? data_i[48] : 1'b0; - assign data_o[14] = (N1)? data_i[14] : - (N0)? data_i[47] : 1'b0; - assign data_o[13] = (N1)? data_i[13] : - (N0)? data_i[46] : 1'b0; - assign data_o[12] = (N1)? data_i[12] : - (N0)? data_i[45] : 1'b0; - assign data_o[11] = (N1)? data_i[11] : - (N0)? data_i[44] : 1'b0; - assign data_o[10] = (N1)? data_i[10] : - (N0)? data_i[43] : 1'b0; - assign data_o[9] = (N1)? data_i[9] : - (N0)? data_i[42] : 1'b0; - assign data_o[8] = (N1)? data_i[8] : - (N0)? data_i[41] : 1'b0; - assign data_o[7] = (N1)? data_i[7] : - (N0)? data_i[40] : 1'b0; - assign data_o[6] = (N1)? data_i[6] : - (N0)? data_i[39] : 1'b0; - assign data_o[5] = (N1)? data_i[5] : - (N0)? data_i[38] : 1'b0; - assign data_o[4] = (N1)? data_i[4] : - (N0)? data_i[37] : 1'b0; - assign data_o[3] = (N1)? data_i[3] : - (N0)? data_i[36] : 1'b0; - assign data_o[2] = (N1)? data_i[2] : - (N0)? data_i[35] : 1'b0; - assign data_o[1] = (N1)? data_i[1] : - (N0)? data_i[34] : 1'b0; - assign data_o[0] = (N1)? data_i[0] : - (N0)? data_i[33] : 1'b0; - assign N1 = ~sel_i[0]; - -endmodule - - - -module bsg_mux_one_hot_width_p33_els_p3 -( - data_i, - sel_one_hot_i, - data_o -); - - input [98:0] data_i; - input [2:0] sel_one_hot_i; - output [32:0] data_o; - wire [32:0] data_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; - wire [98:0] data_masked; - assign data_masked[32] = data_i[32] & sel_one_hot_i[0]; - assign data_masked[31] = data_i[31] & sel_one_hot_i[0]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[0]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[0]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[0]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[0]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[0]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[0]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[0]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[0]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[0]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[0]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[0]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[0]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[0]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[0]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[0]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[0]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[0]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[0]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[0]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[65] = data_i[65] & sel_one_hot_i[1]; - assign data_masked[64] = data_i[64] & sel_one_hot_i[1]; - assign data_masked[63] = data_i[63] & sel_one_hot_i[1]; - assign data_masked[62] = data_i[62] & sel_one_hot_i[1]; - assign data_masked[61] = data_i[61] & sel_one_hot_i[1]; - assign data_masked[60] = data_i[60] & sel_one_hot_i[1]; - assign data_masked[59] = data_i[59] & sel_one_hot_i[1]; - assign data_masked[58] = data_i[58] & sel_one_hot_i[1]; - assign data_masked[57] = data_i[57] & sel_one_hot_i[1]; - assign data_masked[56] = data_i[56] & sel_one_hot_i[1]; - assign data_masked[55] = data_i[55] & sel_one_hot_i[1]; - assign data_masked[54] = data_i[54] & sel_one_hot_i[1]; - assign data_masked[53] = data_i[53] & sel_one_hot_i[1]; - assign data_masked[52] = data_i[52] & sel_one_hot_i[1]; - assign data_masked[51] = data_i[51] & sel_one_hot_i[1]; - assign data_masked[50] = data_i[50] & sel_one_hot_i[1]; - assign data_masked[49] = data_i[49] & sel_one_hot_i[1]; - assign data_masked[48] = data_i[48] & sel_one_hot_i[1]; - assign data_masked[47] = data_i[47] & sel_one_hot_i[1]; - assign data_masked[46] = data_i[46] & sel_one_hot_i[1]; - assign data_masked[45] = data_i[45] & sel_one_hot_i[1]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[1]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[1]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[1]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[1]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[1]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[1]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[1]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[1]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[1]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[1]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[1]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[1]; - assign data_masked[98] = data_i[98] & sel_one_hot_i[2]; - assign data_masked[97] = data_i[97] & sel_one_hot_i[2]; - assign data_masked[96] = data_i[96] & sel_one_hot_i[2]; - assign data_masked[95] = data_i[95] & sel_one_hot_i[2]; - assign data_masked[94] = data_i[94] & sel_one_hot_i[2]; - assign data_masked[93] = data_i[93] & sel_one_hot_i[2]; - assign data_masked[92] = data_i[92] & sel_one_hot_i[2]; - assign data_masked[91] = data_i[91] & sel_one_hot_i[2]; - assign data_masked[90] = data_i[90] & sel_one_hot_i[2]; - assign data_masked[89] = data_i[89] & sel_one_hot_i[2]; - assign data_masked[88] = data_i[88] & sel_one_hot_i[2]; - assign data_masked[87] = data_i[87] & sel_one_hot_i[2]; - assign data_masked[86] = data_i[86] & sel_one_hot_i[2]; - assign data_masked[85] = data_i[85] & sel_one_hot_i[2]; - assign data_masked[84] = data_i[84] & sel_one_hot_i[2]; - assign data_masked[83] = data_i[83] & sel_one_hot_i[2]; - assign data_masked[82] = data_i[82] & sel_one_hot_i[2]; - assign data_masked[81] = data_i[81] & sel_one_hot_i[2]; - assign data_masked[80] = data_i[80] & sel_one_hot_i[2]; - assign data_masked[79] = data_i[79] & sel_one_hot_i[2]; - assign data_masked[78] = data_i[78] & sel_one_hot_i[2]; - assign data_masked[77] = data_i[77] & sel_one_hot_i[2]; - assign data_masked[76] = data_i[76] & sel_one_hot_i[2]; - assign data_masked[75] = data_i[75] & sel_one_hot_i[2]; - assign data_masked[74] = data_i[74] & sel_one_hot_i[2]; - assign data_masked[73] = data_i[73] & sel_one_hot_i[2]; - assign data_masked[72] = data_i[72] & sel_one_hot_i[2]; - assign data_masked[71] = data_i[71] & sel_one_hot_i[2]; - assign data_masked[70] = data_i[70] & sel_one_hot_i[2]; - assign data_masked[69] = data_i[69] & sel_one_hot_i[2]; - assign data_masked[68] = data_i[68] & sel_one_hot_i[2]; - assign data_masked[67] = data_i[67] & sel_one_hot_i[2]; - assign data_masked[66] = data_i[66] & sel_one_hot_i[2]; - assign data_o[0] = N0 | data_masked[0]; - assign N0 = data_masked[66] | data_masked[33]; - assign data_o[1] = N1 | data_masked[1]; - assign N1 = data_masked[67] | data_masked[34]; - assign data_o[2] = N2 | data_masked[2]; - assign N2 = data_masked[68] | data_masked[35]; - assign data_o[3] = N3 | data_masked[3]; - assign N3 = data_masked[69] | data_masked[36]; - assign data_o[4] = N4 | data_masked[4]; - assign N4 = data_masked[70] | data_masked[37]; - assign data_o[5] = N5 | data_masked[5]; - assign N5 = data_masked[71] | data_masked[38]; - assign data_o[6] = N6 | data_masked[6]; - assign N6 = data_masked[72] | data_masked[39]; - assign data_o[7] = N7 | data_masked[7]; - assign N7 = data_masked[73] | data_masked[40]; - assign data_o[8] = N8 | data_masked[8]; - assign N8 = data_masked[74] | data_masked[41]; - assign data_o[9] = N9 | data_masked[9]; - assign N9 = data_masked[75] | data_masked[42]; - assign data_o[10] = N10 | data_masked[10]; - assign N10 = data_masked[76] | data_masked[43]; - assign data_o[11] = N11 | data_masked[11]; - assign N11 = data_masked[77] | data_masked[44]; - assign data_o[12] = N12 | data_masked[12]; - assign N12 = data_masked[78] | data_masked[45]; - assign data_o[13] = N13 | data_masked[13]; - assign N13 = data_masked[79] | data_masked[46]; - assign data_o[14] = N14 | data_masked[14]; - assign N14 = data_masked[80] | data_masked[47]; - assign data_o[15] = N15 | data_masked[15]; - assign N15 = data_masked[81] | data_masked[48]; - assign data_o[16] = N16 | data_masked[16]; - assign N16 = data_masked[82] | data_masked[49]; - assign data_o[17] = N17 | data_masked[17]; - assign N17 = data_masked[83] | data_masked[50]; - assign data_o[18] = N18 | data_masked[18]; - assign N18 = data_masked[84] | data_masked[51]; - assign data_o[19] = N19 | data_masked[19]; - assign N19 = data_masked[85] | data_masked[52]; - assign data_o[20] = N20 | data_masked[20]; - assign N20 = data_masked[86] | data_masked[53]; - assign data_o[21] = N21 | data_masked[21]; - assign N21 = data_masked[87] | data_masked[54]; - assign data_o[22] = N22 | data_masked[22]; - assign N22 = data_masked[88] | data_masked[55]; - assign data_o[23] = N23 | data_masked[23]; - assign N23 = data_masked[89] | data_masked[56]; - assign data_o[24] = N24 | data_masked[24]; - assign N24 = data_masked[90] | data_masked[57]; - assign data_o[25] = N25 | data_masked[25]; - assign N25 = data_masked[91] | data_masked[58]; - assign data_o[26] = N26 | data_masked[26]; - assign N26 = data_masked[92] | data_masked[59]; - assign data_o[27] = N27 | data_masked[27]; - assign N27 = data_masked[93] | data_masked[60]; - assign data_o[28] = N28 | data_masked[28]; - assign N28 = data_masked[94] | data_masked[61]; - assign data_o[29] = N29 | data_masked[29]; - assign N29 = data_masked[95] | data_masked[62]; - assign data_o[30] = N30 | data_masked[30]; - assign N30 = data_masked[96] | data_masked[63]; - assign data_o[31] = N31 | data_masked[31]; - assign N31 = data_masked[97] | data_masked[64]; - assign data_o[32] = N32 | data_masked[32]; - assign N32 = data_masked[98] | data_masked[65]; - -endmodule - - - -module bsg_dff_en_width_p33 -( - clock_i, - data_i, - en_i, - data_o -); - - input [32:0] data_i; - output [32:0] data_o; - input clock_i; - input en_i; - reg [32:0] data_o; - - always @(posedge clock_i) begin - if(en_i) begin - data_o[32] <= data_i[32]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[31] <= data_i[31]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[30] <= data_i[30]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[29] <= data_i[29]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[28] <= data_i[28]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[27] <= data_i[27]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[26] <= data_i[26]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[25] <= data_i[25]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[24] <= data_i[24]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[23] <= data_i[23]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[22] <= data_i[22]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[21] <= data_i[21]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[20] <= data_i[20]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[19] <= data_i[19]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[18] <= data_i[18]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[17] <= data_i[17]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[16] <= data_i[16]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[15] <= data_i[15]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[14] <= data_i[14]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[13] <= data_i[13]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[12] <= data_i[12]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[11] <= data_i[11]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[10] <= data_i[10]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[9] <= data_i[9]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[8] <= data_i[8]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[7] <= data_i[7]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[6] <= data_i[6]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[5] <= data_i[5]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[4] <= data_i[4]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[3] <= data_i[3]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[2] <= data_i[2]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[1] <= data_i[1]; - end - end - - - always @(posedge clock_i) begin - if(en_i) begin - data_o[0] <= data_i[0]; - end - end - - -endmodule - - - -module bsg_buf_ctrl_width_p33 -( - i, - o -); - - output [32:0] o; - input i; - wire [32:0] o; - wire i; - assign o[0] = i; - assign o[1] = i; - assign o[2] = i; - assign o[3] = i; - assign o[4] = i; - assign o[5] = i; - assign o[6] = i; - assign o[7] = i; - assign o[8] = i; - assign o[9] = i; - assign o[10] = i; - assign o[11] = i; - assign o[12] = i; - assign o[13] = i; - assign o[14] = i; - assign o[15] = i; - assign o[16] = i; - assign o[17] = i; - assign o[18] = i; - assign o[19] = i; - assign o[20] = i; - assign o[21] = i; - assign o[22] = i; - assign o[23] = i; - assign o[24] = i; - assign o[25] = i; - assign o[26] = i; - assign o[27] = i; - assign o[28] = i; - assign o[29] = i; - assign o[30] = i; - assign o[31] = i; - assign o[32] = i; - -endmodule - - - -module bsg_xnor_width_p33 -( - a_i, - b_i, - o -); - - input [32:0] a_i; - input [32:0] b_i; - output [32:0] o; - wire [32:0] o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; - assign o[32] = ~N0; - assign N0 = a_i[32] ^ b_i[32]; - assign o[31] = ~N1; - assign N1 = a_i[31] ^ b_i[31]; - assign o[30] = ~N2; - assign N2 = a_i[30] ^ b_i[30]; - assign o[29] = ~N3; - assign N3 = a_i[29] ^ b_i[29]; - assign o[28] = ~N4; - assign N4 = a_i[28] ^ b_i[28]; - assign o[27] = ~N5; - assign N5 = a_i[27] ^ b_i[27]; - assign o[26] = ~N6; - assign N6 = a_i[26] ^ b_i[26]; - assign o[25] = ~N7; - assign N7 = a_i[25] ^ b_i[25]; - assign o[24] = ~N8; - assign N8 = a_i[24] ^ b_i[24]; - assign o[23] = ~N9; - assign N9 = a_i[23] ^ b_i[23]; - assign o[22] = ~N10; - assign N10 = a_i[22] ^ b_i[22]; - assign o[21] = ~N11; - assign N11 = a_i[21] ^ b_i[21]; - assign o[20] = ~N12; - assign N12 = a_i[20] ^ b_i[20]; - assign o[19] = ~N13; - assign N13 = a_i[19] ^ b_i[19]; - assign o[18] = ~N14; - assign N14 = a_i[18] ^ b_i[18]; - assign o[17] = ~N15; - assign N15 = a_i[17] ^ b_i[17]; - assign o[16] = ~N16; - assign N16 = a_i[16] ^ b_i[16]; - assign o[15] = ~N17; - assign N17 = a_i[15] ^ b_i[15]; - assign o[14] = ~N18; - assign N18 = a_i[14] ^ b_i[14]; - assign o[13] = ~N19; - assign N19 = a_i[13] ^ b_i[13]; - assign o[12] = ~N20; - assign N20 = a_i[12] ^ b_i[12]; - assign o[11] = ~N21; - assign N21 = a_i[11] ^ b_i[11]; - assign o[10] = ~N22; - assign N22 = a_i[10] ^ b_i[10]; - assign o[9] = ~N23; - assign N23 = a_i[9] ^ b_i[9]; - assign o[8] = ~N24; - assign N24 = a_i[8] ^ b_i[8]; - assign o[7] = ~N25; - assign N25 = a_i[7] ^ b_i[7]; - assign o[6] = ~N26; - assign N26 = a_i[6] ^ b_i[6]; - assign o[5] = ~N27; - assign N27 = a_i[5] ^ b_i[5]; - assign o[4] = ~N28; - assign N28 = a_i[4] ^ b_i[4]; - assign o[3] = ~N29; - assign N29 = a_i[3] ^ b_i[3]; - assign o[2] = ~N30; - assign N30 = a_i[2] ^ b_i[2]; - assign o[1] = ~N31; - assign N31 = a_i[1] ^ b_i[1]; - assign o[0] = ~N32; - assign N32 = a_i[0] ^ b_i[0]; - -endmodule - - - -module bsg_nor2_width_p33 -( - a_i, - b_i, - o -); - - input [32:0] a_i; - input [32:0] b_i; - output [32:0] o; - wire [32:0] o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; - assign o[32] = ~N0; - assign N0 = a_i[32] | b_i[32]; - assign o[31] = ~N1; - assign N1 = a_i[31] | b_i[31]; - assign o[30] = ~N2; - assign N2 = a_i[30] | b_i[30]; - assign o[29] = ~N3; - assign N3 = a_i[29] | b_i[29]; - assign o[28] = ~N4; - assign N4 = a_i[28] | b_i[28]; - assign o[27] = ~N5; - assign N5 = a_i[27] | b_i[27]; - assign o[26] = ~N6; - assign N6 = a_i[26] | b_i[26]; - assign o[25] = ~N7; - assign N7 = a_i[25] | b_i[25]; - assign o[24] = ~N8; - assign N8 = a_i[24] | b_i[24]; - assign o[23] = ~N9; - assign N9 = a_i[23] | b_i[23]; - assign o[22] = ~N10; - assign N10 = a_i[22] | b_i[22]; - assign o[21] = ~N11; - assign N11 = a_i[21] | b_i[21]; - assign o[20] = ~N12; - assign N12 = a_i[20] | b_i[20]; - assign o[19] = ~N13; - assign N13 = a_i[19] | b_i[19]; - assign o[18] = ~N14; - assign N14 = a_i[18] | b_i[18]; - assign o[17] = ~N15; - assign N15 = a_i[17] | b_i[17]; - assign o[16] = ~N16; - assign N16 = a_i[16] | b_i[16]; - assign o[15] = ~N17; - assign N17 = a_i[15] | b_i[15]; - assign o[14] = ~N18; - assign N18 = a_i[14] | b_i[14]; - assign o[13] = ~N19; - assign N19 = a_i[13] | b_i[13]; - assign o[12] = ~N20; - assign N20 = a_i[12] | b_i[12]; - assign o[11] = ~N21; - assign N21 = a_i[11] | b_i[11]; - assign o[10] = ~N22; - assign N22 = a_i[10] | b_i[10]; - assign o[9] = ~N23; - assign N23 = a_i[9] | b_i[9]; - assign o[8] = ~N24; - assign N24 = a_i[8] | b_i[8]; - assign o[7] = ~N25; - assign N25 = a_i[7] | b_i[7]; - assign o[6] = ~N26; - assign N26 = a_i[6] | b_i[6]; - assign o[5] = ~N27; - assign N27 = a_i[5] | b_i[5]; - assign o[4] = ~N28; - assign N28 = a_i[4] | b_i[4]; - assign o[3] = ~N29; - assign N29 = a_i[3] | b_i[3]; - assign o[2] = ~N30; - assign N30 = a_i[2] | b_i[2]; - assign o[1] = ~N31; - assign N31 = a_i[1] | b_i[1]; - assign o[0] = ~N32; - assign N32 = a_i[0] | b_i[0]; - -endmodule - - - -module bsg_adder_cin_width_p33 -( - a_i, - b_i, - cin_i, - o -); - - input [32:0] a_i; - input [32:0] b_i; - output [32:0] o; - input cin_i; - wire [32:0] o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; - assign { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } = a_i + b_i; - assign o = { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } + cin_i; - -endmodule - - - -module bsg_idiv_iterative_controller -( - clk_i, - reset_i, - v_i, - ready_o, - signed_div_r_i, - adder_result_is_neg_i, - opA_is_neg_i, - opC_is_neg_i, - opA_sel_o, - opA_ld_o, - opA_inv_o, - opA_clr_l_o, - opB_sel_o, - opB_ld_o, - opB_inv_o, - opB_clr_l_o, - opC_sel_o, - opC_ld_o, - latch_inputs_o, - adder_cin_o, - v_o, - yumi_i -); - - output [2:0] opB_sel_o; - output [2:0] opC_sel_o; - input clk_i; - input reset_i; - input v_i; - input signed_div_r_i; - input adder_result_is_neg_i; - input opA_is_neg_i; - input opC_is_neg_i; - input yumi_i; - output ready_o; - output opA_sel_o; - output opA_ld_o; - output opA_inv_o; - output opA_clr_l_o; - output opB_ld_o; - output opB_inv_o; - output opB_clr_l_o; - output opC_ld_o; - output latch_inputs_o; - output adder_cin_o; - output v_o; - wire [2:0] opB_sel_o,opC_sel_o; - wire ready_o,opA_sel_o,opA_ld_o,opA_inv_o,opA_clr_l_o,opB_ld_o,opB_inv_o,opB_clr_l_o, - opC_ld_o,latch_inputs_o,adder_cin_o,v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11, - N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31, - N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,neg_ld,N42,N43,N44,N45,N46,N47,N48,N49, - N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69, - N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89, - N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107, - N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123, - N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139, - N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155, - N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171, - N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187, - N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203, - N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219, - N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235, - N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251, - N252,N253,N254,N255,N256,N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267, - N268,N269,N270,N271,N272,N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283, - N284,N285,N286,N287,N288,N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299, - N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315, - N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331, - N332,N333,N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347, - N349,N350,N351,N352,N353,N354,N355,N356,N358; - wire [5:0] next_state; - reg add_neg_last,r_neg,q_neg; - reg [5:0] state; - - always @(posedge clk_i) begin - if(1'b1) begin - add_neg_last <= adder_result_is_neg_i; - end - end - - - always @(posedge clk_i) begin - if(neg_ld) begin - r_neg <= N299; - end - end - - - always @(posedge clk_i) begin - if(neg_ld) begin - q_neg <= N42; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[5] <= 1'b0; - end else if(1'b1) begin - state[5] <= next_state[5]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[4] <= 1'b0; - end else if(1'b1) begin - state[4] <= next_state[4]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[3] <= 1'b0; - end else if(1'b1) begin - state[3] <= next_state[3]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[2] <= 1'b0; - end else if(1'b1) begin - state[2] <= next_state[2]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[1] <= 1'b0; - end else if(1'b1) begin - state[1] <= next_state[1]; - end - end - - - always @(posedge clk_i) begin - if(reset_i) begin - state[0] <= 1'b0; - end else if(1'b1) begin - state[0] <= next_state[0]; - end - end - - assign N47 = N349 & N44; - assign N48 = N350 & N45; - assign N49 = N46 & N351; - assign N50 = N47 & N48; - assign N51 = N50 & N49; - assign N52 = state[5] | state[4]; - assign N53 = state[3] | state[2]; - assign N54 = state[1] | N351; - assign N55 = N52 | N53; - assign N56 = N55 | N54; - assign N58 = state[5] | state[4]; - assign N59 = state[3] | state[2]; - assign N60 = N46 | state[0]; - assign N61 = N58 | N59; - assign N62 = N61 | N60; - assign N64 = state[5] | state[4]; - assign N65 = state[3] | state[2]; - assign N66 = N46 | N351; - assign N67 = N64 | N65; - assign N68 = N67 | N66; - assign N70 = state[5] | state[4]; - assign N71 = state[3] | N45; - assign N72 = state[1] | state[0]; - assign N73 = N70 | N71; - assign N74 = N73 | N72; - assign N76 = state[5] | state[4]; - assign N77 = state[3] | N45; - assign N78 = state[1] | N351; - assign N79 = N76 | N77; - assign N80 = N79 | N78; - assign N82 = state[5] | state[4]; - assign N83 = state[3] | N45; - assign N84 = N46 | state[0]; - assign N85 = N82 | N83; - assign N86 = N85 | N84; - assign N88 = state[5] | state[4]; - assign N89 = state[3] | N45; - assign N90 = N46 | N351; - assign N91 = N88 | N89; - assign N92 = N91 | N90; - assign N94 = state[5] | state[4]; - assign N95 = N350 | state[2]; - assign N96 = state[1] | state[0]; - assign N97 = N94 | N95; - assign N98 = N97 | N96; - assign N100 = state[5] | state[4]; - assign N101 = N350 | state[2]; - assign N102 = state[1] | N351; - assign N103 = N100 | N101; - assign N104 = N103 | N102; - assign N106 = state[5] | state[4]; - assign N107 = N350 | state[2]; - assign N108 = N46 | state[0]; - assign N109 = N106 | N107; - assign N110 = N109 | N108; - assign N112 = state[5] | state[4]; - assign N113 = N350 | state[2]; - assign N114 = N46 | N351; - assign N115 = N112 | N113; - assign N116 = N115 | N114; - assign N118 = state[5] | state[4]; - assign N119 = N350 | N45; - assign N120 = state[1] | state[0]; - assign N121 = N118 | N119; - assign N122 = N121 | N120; - assign N124 = state[5] | state[4]; - assign N125 = N350 | N45; - assign N126 = state[1] | N351; - assign N127 = N124 | N125; - assign N128 = N127 | N126; - assign N130 = state[5] | state[4]; - assign N131 = N350 | N45; - assign N132 = N46 | state[0]; - assign N133 = N130 | N131; - assign N134 = N133 | N132; - assign N136 = state[5] | state[4]; - assign N137 = N350 | N45; - assign N138 = N46 | N351; - assign N139 = N136 | N137; - assign N140 = N139 | N138; - assign N142 = state[5] | N44; - assign N143 = state[3] | state[2]; - assign N144 = state[1] | state[0]; - assign N145 = N142 | N143; - assign N146 = N145 | N144; - assign N148 = state[5] | N44; - assign N149 = state[3] | state[2]; - assign N150 = state[1] | N351; - assign N151 = N148 | N149; - assign N152 = N151 | N150; - assign N154 = state[5] | N44; - assign N155 = state[3] | state[2]; - assign N156 = N46 | state[0]; - assign N157 = N154 | N155; - assign N158 = N157 | N156; - assign N160 = state[5] | N44; - assign N161 = state[3] | state[2]; - assign N162 = N46 | N351; - assign N163 = N160 | N161; - assign N164 = N163 | N162; - assign N166 = state[5] | N44; - assign N167 = state[3] | N45; - assign N168 = state[1] | state[0]; - assign N169 = N166 | N167; - assign N170 = N169 | N168; - assign N172 = state[5] | N44; - assign N173 = state[3] | N45; - assign N174 = state[1] | N351; - assign N175 = N172 | N173; - assign N176 = N175 | N174; - assign N178 = state[5] | N44; - assign N179 = state[3] | N45; - assign N180 = N46 | state[0]; - assign N181 = N178 | N179; - assign N182 = N181 | N180; - assign N184 = state[5] | N44; - assign N185 = state[3] | N45; - assign N186 = N46 | N351; - assign N187 = N184 | N185; - assign N188 = N187 | N186; - assign N190 = state[5] | N44; - assign N191 = N350 | state[2]; - assign N192 = state[1] | state[0]; - assign N193 = N190 | N191; - assign N194 = N193 | N192; - assign N196 = state[5] | N44; - assign N197 = N350 | state[2]; - assign N198 = state[1] | N351; - assign N199 = N196 | N197; - assign N200 = N199 | N198; - assign N202 = state[5] | N44; - assign N203 = N350 | state[2]; - assign N204 = N46 | state[0]; - assign N205 = N202 | N203; - assign N206 = N205 | N204; - assign N208 = state[5] | N44; - assign N209 = N350 | state[2]; - assign N210 = N46 | N351; - assign N211 = N208 | N209; - assign N212 = N211 | N210; - assign N214 = state[5] | N44; - assign N215 = N350 | N45; - assign N216 = state[1] | state[0]; - assign N217 = N214 | N215; - assign N218 = N217 | N216; - assign N220 = state[5] | N44; - assign N221 = N350 | N45; - assign N222 = state[1] | N351; - assign N223 = N220 | N221; - assign N224 = N223 | N222; - assign N226 = state[5] | N44; - assign N227 = N350 | N45; - assign N228 = N46 | state[0]; - assign N229 = N226 | N227; - assign N230 = N229 | N228; - assign N232 = state[5] | N44; - assign N233 = N350 | N45; - assign N234 = N46 | N351; - assign N235 = N232 | N233; - assign N236 = N235 | N234; - assign N238 = N349 | state[4]; - assign N239 = state[3] | state[2]; - assign N240 = state[1] | state[0]; - assign N241 = N238 | N239; - assign N242 = N241 | N240; - assign N244 = N349 | state[4]; - assign N245 = state[3] | state[2]; - assign N246 = state[1] | N351; - assign N247 = N244 | N245; - assign N248 = N247 | N246; - assign N250 = N349 | state[4]; - assign N251 = state[3] | state[2]; - assign N252 = N46 | state[0]; - assign N253 = N250 | N251; - assign N254 = N253 | N252; - assign N256 = N349 | state[4]; - assign N257 = state[3] | state[2]; - assign N258 = N46 | N351; - assign N259 = N256 | N257; - assign N260 = N259 | N258; - assign N262 = N349 | state[4]; - assign N263 = state[3] | N45; - assign N264 = state[1] | state[0]; - assign N265 = N262 | N263; - assign N266 = N265 | N264; - assign N268 = N349 | state[4]; - assign N269 = state[3] | N45; - assign N270 = state[1] | N351; - assign N271 = N268 | N269; - assign N272 = N271 | N270; - assign N274 = N349 | state[4]; - assign N275 = state[3] | N45; - assign N276 = N46 | state[0]; - assign N277 = N274 | N275; - assign N278 = N277 | N276; - assign N280 = N349 | state[4]; - assign N281 = state[3] | N45; - assign N282 = N46 | N351; - assign N283 = N280 | N281; - assign N284 = N283 | N282; - assign N286 = N349 | state[4]; - assign N287 = N350 | state[2]; - assign N288 = state[1] | state[0]; - assign N289 = N286 | N287; - assign N290 = N289 | N288; - assign N292 = N349 | state[4]; - assign N293 = N350 | state[2]; - assign N294 = state[1] | N351; - assign N295 = N292 | N293; - assign N296 = N295 | N294; - assign N343 = state[4] | state[5]; - assign N344 = state[3] | N343; - assign N345 = state[2] | N344; - assign N346 = state[1] | N345; - assign N347 = state[0] | N346; - assign ready_o = ~N347; - assign N349 = ~state[5]; - assign N350 = ~state[3]; - assign N351 = ~state[0]; - assign N352 = state[4] | N349; - assign N353 = N350 | N352; - assign N354 = state[2] | N353; - assign N355 = state[1] | N354; - assign N356 = N351 | N355; - assign v_o = ~N356; - assign next_state = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, v_i } : - (N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N2)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } : - (N3)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N4)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } : - (N5)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 } : - (N6)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 } : - (N7)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N8)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } : - (N9)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 } : - (N10)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } : - (N11)? { 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0 } : - (N12)? { 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b1 } : - (N13)? { 1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0 } : - (N14)? { 1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1 } : - (N15)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N16)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N17)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N18)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } : - (N19)? { 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N20)? { 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1 } : - (N21)? { 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0 } : - (N22)? { 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 } : - (N23)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N24)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1 } : - (N25)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0 } : - (N26)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } : - (N27)? { 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0 } : - (N28)? { 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1 } : - (N29)? { 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } : - (N30)? { 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 } : - (N31)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N32)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } : - (N33)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : - (N34)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } : - (N35)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : - (N36)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } : - (N37)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 } : - (N38)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 } : - (N39)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } : - (N40)? { N300, 1'b0, N300, 1'b0, 1'b0, N300 } : - (N41)? { N300, 1'b0, N300, 1'b0, 1'b0, N300 } : - (N342)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N0 = N51; - assign N1 = opC_sel_o[2]; - assign N2 = N63; - assign N3 = N69; - assign N4 = N75; - assign N5 = N81; - assign N6 = N87; - assign N7 = N93; - assign N8 = N99; - assign N9 = N105; - assign N10 = N111; - assign N11 = N117; - assign N12 = N123; - assign N13 = N129; - assign N14 = N135; - assign N15 = N141; - assign N16 = N147; - assign N17 = N153; - assign N18 = N159; - assign N19 = N165; - assign N20 = N171; - assign N21 = N177; - assign N22 = N183; - assign N23 = N189; - assign N24 = N195; - assign N25 = N201; - assign N26 = N207; - assign N27 = N213; - assign N28 = N219; - assign N29 = N225; - assign N30 = N231; - assign N31 = N237; - assign N32 = N243; - assign N33 = N249; - assign N34 = N255; - assign N35 = N261; - assign N36 = N267; - assign N37 = N273; - assign N38 = N279; - assign N39 = N285; - assign N40 = N291; - assign N41 = N297; - assign latch_inputs_o = (N0)? 1'b1 : - (N1)? 1'b0 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : - (N8)? 1'b0 : - (N9)? 1'b0 : - (N10)? 1'b0 : - (N11)? 1'b0 : - (N12)? 1'b0 : - (N13)? 1'b0 : - (N14)? 1'b0 : - (N15)? 1'b0 : - (N16)? 1'b0 : - (N17)? 1'b0 : - (N18)? 1'b0 : - (N19)? 1'b0 : - (N20)? 1'b0 : - (N21)? 1'b0 : - (N22)? 1'b0 : - (N23)? 1'b0 : - (N24)? 1'b0 : - (N25)? 1'b0 : - (N26)? 1'b0 : - (N27)? 1'b0 : - (N28)? 1'b0 : - (N29)? 1'b0 : - (N30)? 1'b0 : - (N31)? 1'b0 : - (N32)? 1'b0 : - (N33)? 1'b0 : - (N34)? 1'b0 : - (N35)? 1'b0 : - (N36)? 1'b0 : - (N37)? 1'b0 : - (N38)? 1'b0 : - (N39)? 1'b0 : - (N40)? 1'b0 : - (N41)? 1'b0 : - (N342)? 1'b0 : 1'b0; - assign opA_ld_o = (N0)? 1'b0 : - (N1)? 1'b1 : - (N2)? N298 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : - (N8)? 1'b0 : - (N9)? 1'b0 : - (N10)? 1'b0 : - (N11)? 1'b0 : - (N12)? 1'b0 : - (N13)? 1'b0 : - (N14)? 1'b0 : - (N15)? 1'b0 : - (N16)? 1'b0 : - (N17)? 1'b0 : - (N18)? 1'b0 : - (N19)? 1'b0 : - (N20)? 1'b0 : - (N21)? 1'b0 : - (N22)? 1'b0 : - (N23)? 1'b0 : - (N24)? 1'b0 : - (N25)? 1'b0 : - (N26)? 1'b0 : - (N27)? 1'b0 : - (N28)? 1'b0 : - (N29)? 1'b0 : - (N30)? 1'b0 : - (N31)? 1'b0 : - (N32)? 1'b0 : - (N33)? 1'b0 : - (N34)? 1'b0 : - (N35)? 1'b0 : - (N36)? 1'b0 : - (N37)? 1'b0 : - (N38)? 1'b0 : - (N39)? 1'b1 : - (N40)? 1'b0 : - (N41)? 1'b0 : - (N342)? 1'b0 : 1'b0; - assign opC_ld_o = (N0)? 1'b1 : - (N1)? 1'b1 : - (N2)? 1'b0 : - (N3)? N299 : - (N4)? 1'b1 : - (N5)? 1'b1 : - (N6)? 1'b1 : - (N7)? 1'b1 : - (N8)? 1'b1 : - (N9)? 1'b1 : - (N10)? 1'b1 : - (N11)? 1'b1 : - (N12)? 1'b1 : - (N13)? 1'b1 : - (N14)? 1'b1 : - (N15)? 1'b1 : - (N16)? 1'b1 : - (N17)? 1'b1 : - (N18)? 1'b1 : - (N19)? 1'b1 : - (N20)? 1'b1 : - (N21)? 1'b1 : - (N22)? 1'b1 : - (N23)? 1'b1 : - (N24)? 1'b1 : - (N25)? 1'b1 : - (N26)? 1'b1 : - (N27)? 1'b1 : - (N28)? 1'b1 : - (N29)? 1'b1 : - (N30)? 1'b1 : - (N31)? 1'b1 : - (N32)? 1'b1 : - (N33)? 1'b1 : - (N34)? 1'b1 : - (N35)? 1'b1 : - (N36)? 1'b1 : - (N37)? 1'b1 : - (N38)? 1'b0 : - (N39)? 1'b0 : - (N40)? q_neg : - (N41)? 1'b0 : - (N342)? 1'b1 : 1'b0; - assign opA_sel_o = (N0)? 1'b0 : - (N1)? 1'b1 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : - (N8)? 1'b0 : - (N9)? 1'b0 : - (N10)? 1'b0 : - (N11)? 1'b0 : - (N12)? 1'b0 : - (N13)? 1'b0 : - (N14)? 1'b0 : - (N15)? 1'b0 : - (N16)? 1'b0 : - (N17)? 1'b0 : - (N18)? 1'b0 : - (N19)? 1'b0 : - (N20)? 1'b0 : - (N21)? 1'b0 : - (N22)? 1'b0 : - (N23)? 1'b0 : - (N24)? 1'b0 : - (N25)? 1'b0 : - (N26)? 1'b0 : - (N27)? 1'b0 : - (N28)? 1'b0 : - (N29)? 1'b0 : - (N30)? 1'b0 : - (N31)? 1'b0 : - (N32)? 1'b0 : - (N33)? 1'b0 : - (N34)? 1'b0 : - (N35)? 1'b0 : - (N36)? 1'b0 : - (N37)? 1'b0 : - (N38)? 1'b0 : - (N39)? 1'b0 : - (N40)? 1'b0 : - (N41)? 1'b0 : - (N342)? 1'b0 : 1'b0; - assign opC_sel_o[1:0] = (N0)? { 1'b0, 1'b1 } : - (N1)? { 1'b0, 1'b0 } : - (N2)? { 1'b0, 1'b1 } : - (N3)? { 1'b1, 1'b0 } : - (N4)? { 1'b0, 1'b1 } : - (N5)? { 1'b0, 1'b1 } : - (N6)? { 1'b0, 1'b1 } : - (N7)? { 1'b0, 1'b1 } : - (N8)? { 1'b0, 1'b1 } : - (N9)? { 1'b0, 1'b1 } : - (N10)? { 1'b0, 1'b1 } : - (N11)? { 1'b0, 1'b1 } : - (N12)? { 1'b0, 1'b1 } : - (N13)? { 1'b0, 1'b1 } : - (N14)? { 1'b0, 1'b1 } : - (N15)? { 1'b0, 1'b1 } : - (N16)? { 1'b0, 1'b1 } : - (N17)? { 1'b0, 1'b1 } : - (N18)? { 1'b0, 1'b1 } : - (N19)? { 1'b0, 1'b1 } : - (N20)? { 1'b0, 1'b1 } : - (N21)? { 1'b0, 1'b1 } : - (N22)? { 1'b0, 1'b1 } : - (N23)? { 1'b0, 1'b1 } : - (N24)? { 1'b0, 1'b1 } : - (N25)? { 1'b0, 1'b1 } : - (N26)? { 1'b0, 1'b1 } : - (N27)? { 1'b0, 1'b1 } : - (N28)? { 1'b0, 1'b1 } : - (N29)? { 1'b0, 1'b1 } : - (N30)? { 1'b0, 1'b1 } : - (N31)? { 1'b0, 1'b1 } : - (N32)? { 1'b0, 1'b1 } : - (N33)? { 1'b0, 1'b1 } : - (N34)? { 1'b0, 1'b1 } : - (N35)? { 1'b0, 1'b1 } : - (N36)? { 1'b0, 1'b1 } : - (N37)? { 1'b0, 1'b1 } : - (N38)? { 1'b0, 1'b1 } : - (N39)? { 1'b0, 1'b1 } : - (N40)? { 1'b1, 1'b0 } : - (N41)? { 1'b0, 1'b1 } : - (N342)? { 1'b0, 1'b1 } : 1'b0; - assign opB_ld_o = (N0)? 1'b1 : - (N1)? 1'b0 : - (N2)? 1'b1 : - (N3)? 1'b0 : - (N4)? 1'b1 : - (N5)? 1'b1 : - (N6)? 1'b1 : - (N7)? 1'b1 : - (N8)? 1'b1 : - (N9)? 1'b1 : - (N10)? 1'b1 : - (N11)? 1'b1 : - (N12)? 1'b1 : - (N13)? 1'b1 : - (N14)? 1'b1 : - (N15)? 1'b1 : - (N16)? 1'b1 : - (N17)? 1'b1 : - (N18)? 1'b1 : - (N19)? 1'b1 : - (N20)? 1'b1 : - (N21)? 1'b1 : - (N22)? 1'b1 : - (N23)? 1'b1 : - (N24)? 1'b1 : - (N25)? 1'b1 : - (N26)? 1'b1 : - (N27)? 1'b1 : - (N28)? 1'b1 : - (N29)? 1'b1 : - (N30)? 1'b1 : - (N31)? 1'b1 : - (N32)? 1'b1 : - (N33)? 1'b1 : - (N34)? 1'b1 : - (N35)? 1'b1 : - (N36)? 1'b1 : - (N37)? 1'b1 : - (N38)? add_neg_last : - (N39)? 1'b1 : - (N40)? 1'b0 : - (N41)? 1'b0 : - (N342)? 1'b1 : 1'b0; - assign opA_inv_o = (N0)? N43 : - (N1)? N43 : - (N2)? 1'b1 : - (N3)? N43 : - (N4)? N43 : - (N5)? N43 : - (N6)? N43 : - (N7)? N43 : - (N8)? N43 : - (N9)? N43 : - (N10)? N43 : - (N11)? N43 : - (N12)? N43 : - (N13)? N43 : - (N14)? N43 : - (N15)? N43 : - (N16)? N43 : - (N17)? N43 : - (N18)? N43 : - (N19)? N43 : - (N20)? N43 : - (N21)? N43 : - (N22)? N43 : - (N23)? N43 : - (N24)? N43 : - (N25)? N43 : - (N26)? N43 : - (N27)? N43 : - (N28)? N43 : - (N29)? N43 : - (N30)? N43 : - (N31)? N43 : - (N32)? N43 : - (N33)? N43 : - (N34)? N43 : - (N35)? N43 : - (N36)? N43 : - (N37)? N43 : - (N38)? 1'b0 : - (N39)? N43 : - (N40)? N43 : - (N41)? N43 : - (N342)? N43 : 1'b0; - assign opB_clr_l_o = (N0)? 1'b1 : - (N1)? 1'b1 : - (N2)? 1'b0 : - (N3)? 1'b1 : - (N4)? 1'b0 : - (N5)? 1'b1 : - (N6)? 1'b1 : - (N7)? 1'b1 : - (N8)? 1'b1 : - (N9)? 1'b1 : - (N10)? 1'b1 : - (N11)? 1'b1 : - (N12)? 1'b1 : - (N13)? 1'b1 : - (N14)? 1'b1 : - (N15)? 1'b1 : - (N16)? 1'b1 : - (N17)? 1'b1 : - (N18)? 1'b1 : - (N19)? 1'b1 : - (N20)? 1'b1 : - (N21)? 1'b1 : - (N22)? 1'b1 : - (N23)? 1'b1 : - (N24)? 1'b1 : - (N25)? 1'b1 : - (N26)? 1'b1 : - (N27)? 1'b1 : - (N28)? 1'b1 : - (N29)? 1'b1 : - (N30)? 1'b1 : - (N31)? 1'b1 : - (N32)? 1'b1 : - (N33)? 1'b1 : - (N34)? 1'b1 : - (N35)? 1'b1 : - (N36)? 1'b1 : - (N37)? 1'b1 : - (N38)? 1'b1 : - (N39)? 1'b1 : - (N40)? 1'b1 : - (N41)? 1'b1 : - (N342)? 1'b1 : 1'b0; - assign opB_sel_o = (N0)? { 1'b0, 1'b0, 1'b1 } : - (N1)? { 1'b0, 1'b0, 1'b1 } : - (N2)? { 1'b1, 1'b0, 1'b0 } : - (N3)? { 1'b0, 1'b0, 1'b1 } : - (N4)? { 1'b0, 1'b0, 1'b1 } : - (N5)? { 1'b0, 1'b0, 1'b1 } : - (N6)? { 1'b0, 1'b0, 1'b1 } : - (N7)? { 1'b0, 1'b0, 1'b1 } : - (N8)? { 1'b0, 1'b0, 1'b1 } : - (N9)? { 1'b0, 1'b0, 1'b1 } : - (N10)? { 1'b0, 1'b0, 1'b1 } : - (N11)? { 1'b0, 1'b0, 1'b1 } : - (N12)? { 1'b0, 1'b0, 1'b1 } : - (N13)? { 1'b0, 1'b0, 1'b1 } : - (N14)? { 1'b0, 1'b0, 1'b1 } : - (N15)? { 1'b0, 1'b0, 1'b1 } : - (N16)? { 1'b0, 1'b0, 1'b1 } : - (N17)? { 1'b0, 1'b0, 1'b1 } : - (N18)? { 1'b0, 1'b0, 1'b1 } : - (N19)? { 1'b0, 1'b0, 1'b1 } : - (N20)? { 1'b0, 1'b0, 1'b1 } : - (N21)? { 1'b0, 1'b0, 1'b1 } : - (N22)? { 1'b0, 1'b0, 1'b1 } : - (N23)? { 1'b0, 1'b0, 1'b1 } : - (N24)? { 1'b0, 1'b0, 1'b1 } : - (N25)? { 1'b0, 1'b0, 1'b1 } : - (N26)? { 1'b0, 1'b0, 1'b1 } : - (N27)? { 1'b0, 1'b0, 1'b1 } : - (N28)? { 1'b0, 1'b0, 1'b1 } : - (N29)? { 1'b0, 1'b0, 1'b1 } : - (N30)? { 1'b0, 1'b0, 1'b1 } : - (N31)? { 1'b0, 1'b0, 1'b1 } : - (N32)? { 1'b0, 1'b0, 1'b1 } : - (N33)? { 1'b0, 1'b0, 1'b1 } : - (N34)? { 1'b0, 1'b0, 1'b1 } : - (N35)? { 1'b0, 1'b0, 1'b1 } : - (N36)? { 1'b0, 1'b0, 1'b1 } : - (N37)? { 1'b0, 1'b1, 1'b0 } : - (N38)? { 1'b0, 1'b1, 1'b0 } : - (N39)? { 1'b1, 1'b0, 1'b0 } : - (N40)? { 1'b0, 1'b0, 1'b1 } : - (N41)? { 1'b0, 1'b0, 1'b1 } : - (N342)? { 1'b0, 1'b0, 1'b1 } : 1'b0; - assign neg_ld = (N0)? 1'b0 : - (N1)? 1'b0 : - (N2)? 1'b1 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : - (N8)? 1'b0 : - (N9)? 1'b0 : - (N10)? 1'b0 : - (N11)? 1'b0 : - (N12)? 1'b0 : - (N13)? 1'b0 : - (N14)? 1'b0 : - (N15)? 1'b0 : - (N16)? 1'b0 : - (N17)? 1'b0 : - (N18)? 1'b0 : - (N19)? 1'b0 : - (N20)? 1'b0 : - (N21)? 1'b0 : - (N22)? 1'b0 : - (N23)? 1'b0 : - (N24)? 1'b0 : - (N25)? 1'b0 : - (N26)? 1'b0 : - (N27)? 1'b0 : - (N28)? 1'b0 : - (N29)? 1'b0 : - (N30)? 1'b0 : - (N31)? 1'b0 : - (N32)? 1'b0 : - (N33)? 1'b0 : - (N34)? 1'b0 : - (N35)? 1'b0 : - (N36)? 1'b0 : - (N37)? 1'b0 : - (N38)? 1'b0 : - (N39)? 1'b0 : - (N40)? 1'b0 : - (N41)? 1'b0 : - (N342)? 1'b0 : 1'b0; - assign adder_cin_o = (N0)? N43 : - (N1)? N43 : - (N2)? 1'b1 : - (N3)? 1'b1 : - (N4)? 1'b0 : - (N5)? N43 : - (N6)? N43 : - (N7)? N43 : - (N8)? N43 : - (N9)? N43 : - (N10)? N43 : - (N11)? N43 : - (N12)? N43 : - (N13)? N43 : - (N14)? N43 : - (N15)? N43 : - (N16)? N43 : - (N17)? N43 : - (N18)? N43 : - (N19)? N43 : - (N20)? N43 : - (N21)? N43 : - (N22)? N43 : - (N23)? N43 : - (N24)? N43 : - (N25)? N43 : - (N26)? N43 : - (N27)? N43 : - (N28)? N43 : - (N29)? N43 : - (N30)? N43 : - (N31)? N43 : - (N32)? N43 : - (N33)? N43 : - (N34)? N43 : - (N35)? N43 : - (N36)? N43 : - (N37)? N43 : - (N38)? 1'b0 : - (N39)? r_neg : - (N40)? 1'b1 : - (N41)? N43 : - (N342)? N43 : 1'b0; - assign opA_clr_l_o = (N0)? 1'b1 : - (N1)? 1'b1 : - (N2)? 1'b1 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b1 : - (N6)? 1'b1 : - (N7)? 1'b1 : - (N8)? 1'b1 : - (N9)? 1'b1 : - (N10)? 1'b1 : - (N11)? 1'b1 : - (N12)? 1'b1 : - (N13)? 1'b1 : - (N14)? 1'b1 : - (N15)? 1'b1 : - (N16)? 1'b1 : - (N17)? 1'b1 : - (N18)? 1'b1 : - (N19)? 1'b1 : - (N20)? 1'b1 : - (N21)? 1'b1 : - (N22)? 1'b1 : - (N23)? 1'b1 : - (N24)? 1'b1 : - (N25)? 1'b1 : - (N26)? 1'b1 : - (N27)? 1'b1 : - (N28)? 1'b1 : - (N29)? 1'b1 : - (N30)? 1'b1 : - (N31)? 1'b1 : - (N32)? 1'b1 : - (N33)? 1'b1 : - (N34)? 1'b1 : - (N35)? 1'b1 : - (N36)? 1'b1 : - (N37)? 1'b1 : - (N38)? 1'b1 : - (N39)? 1'b0 : - (N40)? 1'b0 : - (N41)? 1'b1 : - (N342)? 1'b1 : 1'b0; - assign opB_inv_o = (N0)? 1'b0 : - (N1)? 1'b0 : - (N2)? 1'b0 : - (N3)? 1'b1 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : - (N8)? 1'b0 : - (N9)? 1'b0 : - (N10)? 1'b0 : - (N11)? 1'b0 : - (N12)? 1'b0 : - (N13)? 1'b0 : - (N14)? 1'b0 : - (N15)? 1'b0 : - (N16)? 1'b0 : - (N17)? 1'b0 : - (N18)? 1'b0 : - (N19)? 1'b0 : - (N20)? 1'b0 : - (N21)? 1'b0 : - (N22)? 1'b0 : - (N23)? 1'b0 : - (N24)? 1'b0 : - (N25)? 1'b0 : - (N26)? 1'b0 : - (N27)? 1'b0 : - (N28)? 1'b0 : - (N29)? 1'b0 : - (N30)? 1'b0 : - (N31)? 1'b0 : - (N32)? 1'b0 : - (N33)? 1'b0 : - (N34)? 1'b0 : - (N35)? 1'b0 : - (N36)? 1'b0 : - (N37)? 1'b0 : - (N38)? 1'b0 : - (N39)? r_neg : - (N40)? 1'b1 : - (N41)? 1'b0 : - (N342)? 1'b0 : 1'b0; - assign N42 = N358 & signed_div_r_i; - assign N358 = opA_is_neg_i ^ opC_is_neg_i; - assign N43 = ~add_neg_last; - assign N44 = ~state[4]; - assign N45 = ~state[2]; - assign N46 = ~state[1]; - assign N57 = ~N56; - assign N63 = ~N62; - assign N69 = ~N68; - assign N75 = ~N74; - assign N81 = ~N80; - assign N87 = ~N86; - assign N93 = ~N92; - assign N99 = ~N98; - assign N105 = ~N104; - assign N111 = ~N110; - assign N117 = ~N116; - assign N123 = ~N122; - assign N129 = ~N128; - assign N135 = ~N134; - assign N141 = ~N140; - assign N147 = ~N146; - assign N153 = ~N152; - assign N159 = ~N158; - assign N165 = ~N164; - assign N171 = ~N170; - assign N177 = ~N176; - assign N183 = ~N182; - assign N189 = ~N188; - assign N195 = ~N194; - assign N201 = ~N200; - assign N207 = ~N206; - assign N213 = ~N212; - assign N219 = ~N218; - assign N225 = ~N224; - assign N231 = ~N230; - assign N237 = ~N236; - assign N243 = ~N242; - assign N249 = ~N248; - assign N255 = ~N254; - assign N261 = ~N260; - assign N267 = ~N266; - assign N273 = ~N272; - assign N279 = ~N278; - assign N285 = ~N284; - assign N291 = ~N290; - assign N297 = ~N296; - assign opC_sel_o[2] = N57; - assign N298 = opA_is_neg_i & signed_div_r_i; - assign N299 = opC_is_neg_i & signed_div_r_i; - assign N300 = ~yumi_i; - assign N301 = opC_sel_o[2] | N51; - assign N302 = N63 | N301; - assign N303 = N69 | N302; - assign N304 = N75 | N303; - assign N305 = N81 | N304; - assign N306 = N87 | N305; - assign N307 = N93 | N306; - assign N308 = N99 | N307; - assign N309 = N105 | N308; - assign N310 = N111 | N309; - assign N311 = N117 | N310; - assign N312 = N123 | N311; - assign N313 = N129 | N312; - assign N314 = N135 | N313; - assign N315 = N141 | N314; - assign N316 = N147 | N315; - assign N317 = N153 | N316; - assign N318 = N159 | N317; - assign N319 = N165 | N318; - assign N320 = N171 | N319; - assign N321 = N177 | N320; - assign N322 = N183 | N321; - assign N323 = N189 | N322; - assign N324 = N195 | N323; - assign N325 = N201 | N324; - assign N326 = N207 | N325; - assign N327 = N213 | N326; - assign N328 = N219 | N327; - assign N329 = N225 | N328; - assign N330 = N231 | N329; - assign N331 = N237 | N330; - assign N332 = N243 | N331; - assign N333 = N249 | N332; - assign N334 = N255 | N333; - assign N335 = N261 | N334; - assign N336 = N267 | N335; - assign N337 = N273 | N336; - assign N338 = N279 | N337; - assign N339 = N285 | N338; - assign N340 = N291 | N339; - assign N341 = N297 | N340; - assign N342 = ~N341; - -endmodule - - - -module bsg_idiv_iterative -( - reset_i, - clk_i, - v_i, - ready_o, - dividend_i, - divisor_i, - signed_div_i, - v_o, - quotient_o, - remainder_o, - yumi_i -); - - input [31:0] dividend_i; - input [31:0] divisor_i; - output [31:0] quotient_o; - output [31:0] remainder_o; - input reset_i; - input clk_i; - input v_i; - input signed_div_i; - input yumi_i; - output ready_o; - output v_o; - wire [31:0] quotient_o,remainder_o,divisor_r,dividend_r; - wire ready_o,v_o,signed_div_r,divisor_msb,dividend_msb,latch_inputs,opA_sel, - n_2_net__0_,opA_ld,opB_ld,opC_ld,opA_inv,opB_inv,n_3_net_,opA_clr_l,n_4_net_,opB_clr_l, - adder_cin; - wire [32:0] opA,opC,opA_mux,add_out,opB_mux,opC_mux,opB,opA_inv_buf,opB_inv_buf,opA_clr_buf, - opB_clr_buf,opA_xnor,opB_xnor,add_in0,add_in1; - wire [2:0] opB_sel,opC_sel; - - bsg_buf_width_p32 - remainder_buf - ( - .i(opA[31:0]), - .o(remainder_o) - ); - - - bsg_buf_width_p32 - quotient_buf - ( - .i(opC[31:0]), - .o(quotient_o) - ); - - - bsg_dff_en_width_p1 - req_reg - ( - .clock_i(clk_i), - .data_i(signed_div_i), - .en_i(latch_inputs), - .data_o(signed_div_r) - ); - - - bsg_dff_en_width_p32 - dividend_reg - ( - .clock_i(clk_i), - .data_i(dividend_i), - .en_i(latch_inputs), - .data_o(dividend_r) - ); - - - bsg_dff_en_width_p32 - divisor_reg - ( - .clock_i(clk_i), - .data_i(divisor_i), - .en_i(latch_inputs), - .data_o(divisor_r) - ); - - - bsg_mux_width_p33_els_p2 - muxA - ( - .data_i({ divisor_msb, divisor_r, add_out }), - .sel_i(opA_sel), - .data_o(opA_mux) - ); - - - bsg_mux_one_hot_width_p33_els_p3 - muxB - ( - .data_i({ opC, add_out, add_out[31:0], opC[32:32] }), - .sel_one_hot_i(opB_sel), - .data_o(opB_mux) - ); - - - bsg_mux_one_hot_width_p33_els_p3 - muxC - ( - .data_i({ dividend_msb, dividend_r, add_out, opC[31:0], n_2_net__0_ }), - .sel_one_hot_i(opC_sel), - .data_o(opC_mux) - ); - - - bsg_dff_en_width_p33 - opA_reg - ( - .clock_i(clk_i), - .data_i(opA_mux), - .en_i(opA_ld), - .data_o(opA) - ); - - - bsg_dff_en_width_p33 - opB_reg - ( - .clock_i(clk_i), - .data_i(opB_mux), - .en_i(opB_ld), - .data_o(opB) - ); - - - bsg_dff_en_width_p33 - opC_reg - ( - .clock_i(clk_i), - .data_i(opC_mux), - .en_i(opC_ld), - .data_o(opC) - ); - - - bsg_buf_ctrl_width_p33 - buf_opA_inv - ( - .i(opA_inv), - .o(opA_inv_buf) - ); - - - bsg_buf_ctrl_width_p33 - buf_opB_inv - ( - .i(opB_inv), - .o(opB_inv_buf) - ); - - - bsg_buf_ctrl_width_p33 - buf_opA_clr - ( - .i(n_3_net_), - .o(opA_clr_buf) - ); - - - bsg_buf_ctrl_width_p33 - buf_opB_clr - ( - .i(n_4_net_), - .o(opB_clr_buf) - ); - - - bsg_xnor_width_p33 - xnor_opA - ( - .a_i(opA_inv_buf), - .b_i(opA), - .o(opA_xnor) - ); - - - bsg_xnor_width_p33 - xnor_opB - ( - .a_i(opB_inv_buf), - .b_i(opB), - .o(opB_xnor) - ); - - - bsg_nor2_width_p33 - nor_opA - ( - .a_i(opA_xnor), - .b_i(opA_clr_buf), - .o(add_in0) - ); - - - bsg_nor2_width_p33 - nor_opB - ( - .a_i(opB_xnor), - .b_i(opB_clr_buf), - .o(add_in1) - ); - - - bsg_adder_cin_width_p33 - adder - ( - .a_i(add_in0), - .b_i(add_in1), - .cin_i(adder_cin), - .o(add_out) - ); - - - bsg_idiv_iterative_controller - control - ( - .clk_i(clk_i), - .reset_i(reset_i), - .v_i(v_i), - .ready_o(ready_o), - .signed_div_r_i(signed_div_r), - .adder_result_is_neg_i(add_out[32]), - .opA_is_neg_i(opA[32]), - .opC_is_neg_i(opC[32]), - .opA_sel_o(opA_sel), - .opA_ld_o(opA_ld), - .opA_inv_o(opA_inv), - .opA_clr_l_o(opA_clr_l), - .opB_sel_o(opB_sel), - .opB_ld_o(opB_ld), - .opB_inv_o(opB_inv), - .opB_clr_l_o(opB_clr_l), - .opC_sel_o(opC_sel), - .opC_ld_o(opC_ld), - .latch_inputs_o(latch_inputs), - .adder_cin_o(adder_cin), - .v_o(v_o), - .yumi_i(yumi_i) - ); - - assign divisor_msb = signed_div_r & divisor_r[31]; - assign dividend_msb = signed_div_r & dividend_r[31]; - assign n_2_net__0_ = ~add_out[32]; - assign n_3_net_ = ~opA_clr_l; - assign n_4_net_ = ~opB_clr_l; - -endmodule - - - -module imul_idiv_iterative -( - reset_i, - clk_i, - v_i, - ready_o, - opA_i, - opB_i, - funct3, - v_o, - result_o, - yumi_i -); - - input [31:0] opA_i; - input [31:0] opB_i; - input [2:0] funct3; - output [31:0] result_o; - input reset_i; - input clk_i; - input v_i; - input yumi_i; - output ready_o; - output v_o; - wire [31:0] result_o,imul_result,quotient,remainder; - wire ready_o,v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,imul_v,signed_opA,signed_opB, - gets_high_part,idiv_v,signed_div,gets_quotient,N11,N12,N13,N14,N15,N16,N17,N18,N19, - N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,imul_ready,imul_v_o, - idiv_ready,idiv_v_o,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44; - reg gets_quotient_r; - assign N14 = N11 & N12; - assign N15 = N14 & N13; - assign N16 = funct3[2] | funct3[1]; - assign N17 = N16 | N13; - assign N19 = funct3[2] | N12; - assign N20 = N19 | funct3[0]; - assign N22 = N19 | N13; - assign N24 = N11 | funct3[1]; - assign N25 = N24 | funct3[0]; - assign N27 = N24 | N13; - assign N29 = N11 | N12; - assign N30 = N29 | funct3[0]; - assign N32 = funct3[2] & funct3[1]; - assign N33 = N32 & funct3[0]; - - bsg_imul_iterative_width_p32 - imul - ( - .reset_i(reset_i), - .clk_i(clk_i), - .v_i(imul_v), - .ready_o(imul_ready), - .opA_i(opA_i), - .signed_opA_i(signed_opA), - .opB_i(opB_i), - .signed_opB_i(signed_opB), - .gets_high_part_i(gets_high_part), - .v_o(imul_v_o), - .result_o(imul_result), - .yumi_i(yumi_i) - ); - - - bsg_idiv_iterative - idiv - ( - .reset_i(reset_i), - .clk_i(clk_i), - .v_i(idiv_v), - .ready_o(idiv_ready), - .dividend_i(opA_i), - .divisor_i(opB_i), - .signed_div_i(signed_div), - .v_o(idiv_v_o), - .quotient_o(quotient), - .remainder_o(remainder), - .yumi_i(yumi_i) - ); - - - always @(posedge clk_i) begin - if(N38) begin - gets_quotient_r <= N39; - end - end - - assign imul_v = (N0)? v_i : - (N1)? v_i : - (N2)? v_i : - (N3)? v_i : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : 1'b0; - assign N0 = N15; - assign N1 = N18; - assign N2 = N21; - assign N3 = N23; - assign N4 = N26; - assign N5 = N28; - assign N6 = N31; - assign N7 = N33; - assign signed_opA = (N0)? 1'b1 : - (N1)? 1'b1 : - (N2)? 1'b1 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : 1'b0; - assign signed_opB = (N0)? 1'b1 : - (N1)? 1'b1 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : 1'b0; - assign gets_high_part = (N0)? 1'b0 : - (N1)? 1'b1 : - (N2)? 1'b1 : - (N3)? 1'b1 : - (N4)? 1'b0 : - (N5)? 1'b0 : - (N6)? 1'b0 : - (N7)? 1'b0 : 1'b0; - assign idiv_v = (N0)? 1'b0 : - (N1)? 1'b0 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? v_i : - (N5)? v_i : - (N6)? v_i : - (N7)? v_i : 1'b0; - assign signed_div = (N0)? 1'b0 : - (N1)? 1'b0 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? 1'b1 : - (N5)? 1'b0 : - (N6)? 1'b1 : - (N7)? 1'b0 : 1'b0; - assign gets_quotient = (N0)? 1'b0 : - (N1)? 1'b0 : - (N2)? 1'b0 : - (N3)? 1'b0 : - (N4)? 1'b1 : - (N5)? 1'b1 : - (N6)? 1'b0 : - (N7)? 1'b0 : 1'b0; - assign N38 = (N8)? 1'b1 : - (N41)? 1'b1 : - (N37)? 1'b0 : 1'b0; - assign N8 = N35; - assign N39 = (N8)? 1'b0 : - (N41)? gets_quotient : 1'b0; - assign result_o = (N9)? imul_result : - (N10)? quotient : - (N44)? remainder : 1'b0; - assign N9 = imul_v_o; - assign N10 = N42; - assign N11 = ~funct3[2]; - assign N12 = ~funct3[1]; - assign N13 = ~funct3[0]; - assign N18 = ~N17; - assign N21 = ~N20; - assign N23 = ~N22; - assign N26 = ~N25; - assign N28 = ~N27; - assign N31 = ~N30; - assign N34 = idiv_v & idiv_ready; - assign N35 = reset_i; - assign N36 = N34 | N35; - assign N37 = ~N36; - assign N40 = ~N35; - assign N41 = N34 & N40; - assign N42 = idiv_v_o & gets_quotient_r; - assign N43 = N42 | imul_v_o; - assign N44 = ~N43; - assign v_o = idiv_v_o | imul_v_o; - assign ready_o = idiv_ready & imul_ready; - -endmodule - - - -module bsg_mux_width_p32_els_p2 -( - data_i, - sel_i, - data_o -); - - input [63:0] data_i; - input [0:0] sel_i; - output [31:0] data_o; - wire [31:0] data_o; - wire N0,N1; - assign data_o[31] = (N1)? data_i[31] : - (N0)? data_i[63] : 1'b0; - assign N0 = sel_i[0]; - assign data_o[30] = (N1)? data_i[30] : - (N0)? data_i[62] : 1'b0; - assign data_o[29] = (N1)? data_i[29] : - (N0)? data_i[61] : 1'b0; - assign data_o[28] = (N1)? data_i[28] : - (N0)? data_i[60] : 1'b0; - assign data_o[27] = (N1)? data_i[27] : - (N0)? data_i[59] : 1'b0; - assign data_o[26] = (N1)? data_i[26] : - (N0)? data_i[58] : 1'b0; - assign data_o[25] = (N1)? data_i[25] : - (N0)? data_i[57] : 1'b0; - assign data_o[24] = (N1)? data_i[24] : - (N0)? data_i[56] : 1'b0; - assign data_o[23] = (N1)? data_i[23] : - (N0)? data_i[55] : 1'b0; - assign data_o[22] = (N1)? data_i[22] : - (N0)? data_i[54] : 1'b0; - assign data_o[21] = (N1)? data_i[21] : - (N0)? data_i[53] : 1'b0; - assign data_o[20] = (N1)? data_i[20] : - (N0)? data_i[52] : 1'b0; - assign data_o[19] = (N1)? data_i[19] : - (N0)? data_i[51] : 1'b0; - assign data_o[18] = (N1)? data_i[18] : - (N0)? data_i[50] : 1'b0; - assign data_o[17] = (N1)? data_i[17] : - (N0)? data_i[49] : 1'b0; - assign data_o[16] = (N1)? data_i[16] : - (N0)? data_i[48] : 1'b0; - assign data_o[15] = (N1)? data_i[15] : - (N0)? data_i[47] : 1'b0; - assign data_o[14] = (N1)? data_i[14] : - (N0)? data_i[46] : 1'b0; - assign data_o[13] = (N1)? data_i[13] : - (N0)? data_i[45] : 1'b0; - assign data_o[12] = (N1)? data_i[12] : - (N0)? data_i[44] : 1'b0; - assign data_o[11] = (N1)? data_i[11] : - (N0)? data_i[43] : 1'b0; - assign data_o[10] = (N1)? data_i[10] : - (N0)? data_i[42] : 1'b0; - assign data_o[9] = (N1)? data_i[9] : - (N0)? data_i[41] : 1'b0; - assign data_o[8] = (N1)? data_i[8] : - (N0)? data_i[40] : 1'b0; - assign data_o[7] = (N1)? data_i[7] : - (N0)? data_i[39] : 1'b0; - assign data_o[6] = (N1)? data_i[6] : - (N0)? data_i[38] : 1'b0; - assign data_o[5] = (N1)? data_i[5] : - (N0)? data_i[37] : 1'b0; - assign data_o[4] = (N1)? data_i[4] : - (N0)? data_i[36] : 1'b0; - assign data_o[3] = (N1)? data_i[3] : - (N0)? data_i[35] : 1'b0; - assign data_o[2] = (N1)? data_i[2] : - (N0)? data_i[34] : 1'b0; - assign data_o[1] = (N1)? data_i[1] : - (N0)? data_i[33] : 1'b0; - assign data_o[0] = (N1)? data_i[0] : - (N0)? data_i[32] : 1'b0; - assign N1 = ~sel_i[0]; - -endmodule - - - -module alu_imem_addr_width_p10 -( - rs1_i, - rs2_i, - pc_plus4_i, - op_i, - result_o, - jalr_addr_o, - jump_now_o -); - - input [31:0] rs1_i; - input [31:0] rs2_i; - input [31:0] pc_plus4_i; - input [31:0] op_i; - output [31:0] result_o; - output [9:0] jalr_addr_o; - output jump_now_o; - wire [31:0] result_o,op2,adder_input,shr_out,shl_out,xor_out,and_out,or_out; - wire [9:0] jalr_addr_o; - wire jump_now_o,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26, - N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,is_imm_op,N37,sub_not_add,N38,N39,N40, - N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60, - N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80, - N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100, - N101,N102,N103,N104,carry,sign_ex_or_zero,N105,N106,N107,N108,N109,N110,N111,N112, - N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128, - N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144, - N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160, - N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176, - N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192, - N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208, - N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224, - N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240, - N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256, - N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272, - N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288, - N289,N290,N291,N292,N293,rs1_eq_rs2,rs1_lt_rs2_unsigned,rs1_lt_rs2_signed,N294, - N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,N310, - N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,N326, - N327,N328,N329,N330,N331,N332,N333,N334,N335,SV2V_UNCONNECTED_1; - wire [4:0] sh_amount; - wire [32:0] sum; - assign { SV2V_UNCONNECTED_1, shr_out } = $signed({ sign_ex_or_zero, rs1_i }) >>> sh_amount; - assign shl_out = rs1_i << sh_amount; - assign N106 = N326 & op_i[5]; - assign N107 = op_i[4] & N105; - assign N108 = op_i[2] & op_i[1]; - assign N109 = N106 & N107; - assign N110 = N108 & op_i[0]; - assign N111 = N109 & N110; - assign N112 = N326 & N327; - assign N113 = N112 & N107; - assign N114 = N113 & N110; - assign N115 = N301 & N147; - assign N116 = N115 & N152; - assign N117 = N116 & N150; - assign N118 = N193 & N167; - assign N119 = N118 & op_i[0]; - assign N125 = N121 & N122; - assign N126 = N123 & op_i[28]; - assign N127 = N124 & N310; - assign N128 = op_i[13] & N300; - assign N129 = N125 & N126; - assign N130 = N127 & N128; - assign N131 = N106 & N226; - assign N132 = N129 & N130; - assign N133 = N131 & N110; - assign N134 = N132 & N133; - assign N135 = N311 & N147; - assign N136 = N135 & N152; - assign N137 = N136 & N150; - assign N138 = N193 & N175; - assign N139 = N138 & op_i[0]; - assign N141 = N311 & N179; - assign N142 = N141 & N152; - assign N143 = N142 & N150; - assign N144 = N193 & N185; - assign N145 = N144 & op_i[0]; - assign N147 = N300 & N326; - assign N148 = N327 & op_i[4]; - assign N149 = N105 & N331; - assign N150 = op_i[1] & op_i[0]; - assign N151 = N304 & N147; - assign N152 = N148 & N149; - assign N153 = N151 & N152; - assign N154 = N153 & N150; - assign N158 = N123 & N155; - assign N159 = N124 & N156; - assign N160 = N157 & op_i[14]; - assign N161 = N299 & N300; - assign N162 = N125 & N158; - assign N163 = N159 & N160; - assign N164 = N161 & N106; - assign N165 = N107 & N295; - assign N166 = N162 & N163; - assign N167 = N164 & N165; - assign N168 = N166 & N167; - assign N169 = N168 & op_i[0]; - assign N171 = N307 & N147; - assign N172 = N171 & N152; - assign N173 = N172 & N150; - assign N174 = N128 & N106; - assign N175 = N174 & N165; - assign N176 = N166 & N175; - assign N177 = N176 & op_i[0]; - assign N179 = op_i[12] & N326; - assign N180 = N307 & N179; - assign N181 = N180 & N152; - assign N182 = N181 & N150; - assign N183 = op_i[13] & op_i[12]; - assign N184 = N183 & N106; - assign N185 = N184 & N165; - assign N186 = N166 & N185; - assign N187 = N186 & op_i[0]; - assign N189 = N157 & N310; - assign N190 = N299 & op_i[12]; - assign N191 = N159 & N189; - assign N192 = N190 & N112; - assign N193 = N162 & N191; - assign N194 = N192 & N165; - assign N195 = N193 & N194; - assign N196 = N195 & op_i[0]; - assign N197 = N190 & N106; - assign N198 = N197 & N165; - assign N199 = N193 & N198; - assign N200 = N199 & op_i[0]; - assign N202 = N166 & N194; - assign N203 = N202 & op_i[0]; - assign N204 = N166 & N198; - assign N205 = N204 & op_i[0]; - assign N207 = N121 & op_i[30]; - assign N208 = N207 & N158; - assign N209 = N208 & N163; - assign N210 = N209 & N194; - assign N211 = N210 & op_i[0]; - assign N212 = N209 & N198; - assign N213 = N212 & op_i[0]; - assign N215 = N208 & N191; - assign N216 = N215 & N167; - assign N217 = N216 & op_i[0]; - assign N218 = N300 & op_i[6]; - assign N219 = op_i[5] & N317; - assign N220 = N105 & op_i[2]; - assign N221 = N301 & N218; - assign N222 = N219 & N220; - assign N223 = N221 & N222; - assign N224 = N223 & N150; - assign N225 = op_i[6] & op_i[5]; - assign N226 = N317 & op_i[3]; - assign N227 = N225 & N226; - assign N228 = N227 & N110; - assign rs1_eq_rs2 = rs1_i == rs2_i; - assign rs1_lt_rs2_unsigned = rs1_i < rs2_i; - assign rs1_lt_rs2_signed = $signed(rs1_i) < $signed(rs2_i); - assign N294 = N317 & N105; - assign N295 = N331 & op_i[1]; - assign N296 = N225 & N294; - assign N297 = N296 & N295; - assign N301 = N310 & N299; - assign N302 = N301 & N300; - assign N303 = N301 & op_i[12]; - assign N304 = op_i[14] & N299; - assign N305 = N304 & N300; - assign N306 = N304 & op_i[12]; - assign N307 = op_i[14] & op_i[13]; - assign N308 = N307 & N300; - assign N309 = N307 & op_i[12]; - assign N311 = N310 & op_i[13]; - assign { N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229 } = { op_i[31:12], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } + pc_plus4_i; - assign { N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261 } = { N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229 } - { 1'b1, 1'b0, 1'b0 }; - assign { N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } = { rs1_i[31:31], rs1_i } + { adder_input[31:31], adder_input }; - assign { carry, sum } = { N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } + sub_not_add; - assign jalr_addr_o[0] = sum[2]; - assign jalr_addr_o[1] = sum[3]; - assign jalr_addr_o[2] = sum[4]; - assign jalr_addr_o[3] = sum[5]; - assign jalr_addr_o[4] = sum[6]; - assign jalr_addr_o[5] = sum[7]; - assign jalr_addr_o[6] = sum[8]; - assign jalr_addr_o[7] = sum[9]; - assign jalr_addr_o[8] = sum[10]; - assign jalr_addr_o[9] = sum[11]; - assign op2 = (N10)? { op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:20] } : - (N11)? rs2_i : 1'b0; - assign N10 = is_imm_op; - assign N11 = N37; - assign adder_input = (N12)? { N39, N40, N41, N42, N43, N44, N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70 } : - (N13)? op2 : 1'b0; - assign N12 = sub_not_add; - assign N13 = N38; - assign sh_amount = (N10)? op_i[24:20] : - (N11)? rs2_i[4:0] : 1'b0; - assign result_o = (N14)? { op_i[31:12], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N15)? { N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261 } : - (N16)? sum[31:0] : - (N17)? rs1_i : - (N18)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, sum[32:32] } : - (N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N293 } : - (N20)? xor_out : - (N21)? or_out : - (N22)? and_out : - (N23)? shl_out : - (N24)? shr_out : - (N25)? shr_out : - (N26)? sum[31:0] : - (N27)? pc_plus4_i : - (N28)? pc_plus4_i : 1'b0; - assign N14 = N111; - assign N15 = N114; - assign N16 = N120; - assign N17 = N134; - assign N18 = N140; - assign N19 = N146; - assign N20 = N170; - assign N21 = N178; - assign N22 = N188; - assign N23 = N201; - assign N24 = N206; - assign N25 = N214; - assign N26 = N217; - assign N27 = N224; - assign N28 = N228; - assign sub_not_add = (N16)? 1'b0 : - (N18)? 1'b1 : - (N19)? 1'b1 : - (N26)? 1'b1 : - (N27)? 1'b0 : 1'b0; - assign sign_ex_or_zero = (N24)? 1'b0 : - (N25)? rs1_i[31] : 1'b0; - assign N315 = (N29)? rs1_eq_rs2 : - (N30)? N312 : - (N31)? rs1_lt_rs2_signed : - (N32)? N313 : - (N33)? rs1_lt_rs2_unsigned : - (N34)? N314 : - (N35)? 1'b0 : 1'b0; - assign N29 = N302; - assign N30 = N303; - assign N31 = N305; - assign N32 = N306; - assign N33 = N308; - assign N34 = N309; - assign N35 = N311; - assign jump_now_o = (N36)? N315 : - (N298)? 1'b0 : 1'b0; - assign N36 = N297; - assign is_imm_op = N325 | N335; - assign N325 = ~N324; - assign N324 = N322 | N323; - assign N322 = N320 | N321; - assign N320 = N319 | op_i[2]; - assign N319 = N318 | op_i[3]; - assign N318 = N316 | N317; - assign N316 = op_i[6] | op_i[5]; - assign N317 = ~op_i[4]; - assign N321 = ~op_i[1]; - assign N323 = ~op_i[0]; - assign N335 = ~N334; - assign N334 = N333 | N323; - assign N333 = N332 | N321; - assign N332 = N330 | N331; - assign N330 = N329 | op_i[3]; - assign N329 = N328 | op_i[4]; - assign N328 = N326 | N327; - assign N326 = ~op_i[6]; - assign N327 = ~op_i[5]; - assign N331 = ~op_i[2]; - assign N37 = ~is_imm_op; - assign N38 = ~sub_not_add; - assign N39 = ~op2[31]; - assign N40 = ~op2[30]; - assign N41 = ~op2[29]; - assign N42 = ~op2[28]; - assign N43 = ~op2[27]; - assign N44 = ~op2[26]; - assign N45 = ~op2[25]; - assign N46 = ~op2[24]; - assign N47 = ~op2[23]; - assign N48 = ~op2[22]; - assign N49 = ~op2[21]; - assign N50 = ~op2[20]; - assign N51 = ~op2[19]; - assign N52 = ~op2[18]; - assign N53 = ~op2[17]; - assign N54 = ~op2[16]; - assign N55 = ~op2[15]; - assign N56 = ~op2[14]; - assign N57 = ~op2[13]; - assign N58 = ~op2[12]; - assign N59 = ~op2[11]; - assign N60 = ~op2[10]; - assign N61 = ~op2[9]; - assign N62 = ~op2[8]; - assign N63 = ~op2[7]; - assign N64 = ~op2[6]; - assign N65 = ~op2[5]; - assign N66 = ~op2[4]; - assign N67 = ~op2[3]; - assign N68 = ~op2[2]; - assign N69 = ~op2[1]; - assign N70 = ~op2[0]; - assign xor_out[31] = rs1_i[31] ^ op2[31]; - assign xor_out[30] = rs1_i[30] ^ op2[30]; - assign xor_out[29] = rs1_i[29] ^ op2[29]; - assign xor_out[28] = rs1_i[28] ^ op2[28]; - assign xor_out[27] = rs1_i[27] ^ op2[27]; - assign xor_out[26] = rs1_i[26] ^ op2[26]; - assign xor_out[25] = rs1_i[25] ^ op2[25]; - assign xor_out[24] = rs1_i[24] ^ op2[24]; - assign xor_out[23] = rs1_i[23] ^ op2[23]; - assign xor_out[22] = rs1_i[22] ^ op2[22]; - assign xor_out[21] = rs1_i[21] ^ op2[21]; - assign xor_out[20] = rs1_i[20] ^ op2[20]; - assign xor_out[19] = rs1_i[19] ^ op2[19]; - assign xor_out[18] = rs1_i[18] ^ op2[18]; - assign xor_out[17] = rs1_i[17] ^ op2[17]; - assign xor_out[16] = rs1_i[16] ^ op2[16]; - assign xor_out[15] = rs1_i[15] ^ op2[15]; - assign xor_out[14] = rs1_i[14] ^ op2[14]; - assign xor_out[13] = rs1_i[13] ^ op2[13]; - assign xor_out[12] = rs1_i[12] ^ op2[12]; - assign xor_out[11] = rs1_i[11] ^ op2[11]; - assign xor_out[10] = rs1_i[10] ^ op2[10]; - assign xor_out[9] = rs1_i[9] ^ op2[9]; - assign xor_out[8] = rs1_i[8] ^ op2[8]; - assign xor_out[7] = rs1_i[7] ^ op2[7]; - assign xor_out[6] = rs1_i[6] ^ op2[6]; - assign xor_out[5] = rs1_i[5] ^ op2[5]; - assign xor_out[4] = rs1_i[4] ^ op2[4]; - assign xor_out[3] = rs1_i[3] ^ op2[3]; - assign xor_out[2] = rs1_i[2] ^ op2[2]; - assign xor_out[1] = rs1_i[1] ^ op2[1]; - assign xor_out[0] = rs1_i[0] ^ op2[0]; - assign and_out[31] = rs1_i[31] & op2[31]; - assign and_out[30] = rs1_i[30] & op2[30]; - assign and_out[29] = rs1_i[29] & op2[29]; - assign and_out[28] = rs1_i[28] & op2[28]; - assign and_out[27] = rs1_i[27] & op2[27]; - assign and_out[26] = rs1_i[26] & op2[26]; - assign and_out[25] = rs1_i[25] & op2[25]; - assign and_out[24] = rs1_i[24] & op2[24]; - assign and_out[23] = rs1_i[23] & op2[23]; - assign and_out[22] = rs1_i[22] & op2[22]; - assign and_out[21] = rs1_i[21] & op2[21]; - assign and_out[20] = rs1_i[20] & op2[20]; - assign and_out[19] = rs1_i[19] & op2[19]; - assign and_out[18] = rs1_i[18] & op2[18]; - assign and_out[17] = rs1_i[17] & op2[17]; - assign and_out[16] = rs1_i[16] & op2[16]; - assign and_out[15] = rs1_i[15] & op2[15]; - assign and_out[14] = rs1_i[14] & op2[14]; - assign and_out[13] = rs1_i[13] & op2[13]; - assign and_out[12] = rs1_i[12] & op2[12]; - assign and_out[11] = rs1_i[11] & op2[11]; - assign and_out[10] = rs1_i[10] & op2[10]; - assign and_out[9] = rs1_i[9] & op2[9]; - assign and_out[8] = rs1_i[8] & op2[8]; - assign and_out[7] = rs1_i[7] & op2[7]; - assign and_out[6] = rs1_i[6] & op2[6]; - assign and_out[5] = rs1_i[5] & op2[5]; - assign and_out[4] = rs1_i[4] & op2[4]; - assign and_out[3] = rs1_i[3] & op2[3]; - assign and_out[2] = rs1_i[2] & op2[2]; - assign and_out[1] = rs1_i[1] & op2[1]; - assign and_out[0] = rs1_i[0] & op2[0]; - assign or_out[31] = rs1_i[31] | op2[31]; - assign or_out[30] = rs1_i[30] | op2[30]; - assign or_out[29] = rs1_i[29] | op2[29]; - assign or_out[28] = rs1_i[28] | op2[28]; - assign or_out[27] = rs1_i[27] | op2[27]; - assign or_out[26] = rs1_i[26] | op2[26]; - assign or_out[25] = rs1_i[25] | op2[25]; - assign or_out[24] = rs1_i[24] | op2[24]; - assign or_out[23] = rs1_i[23] | op2[23]; - assign or_out[22] = rs1_i[22] | op2[22]; - assign or_out[21] = rs1_i[21] | op2[21]; - assign or_out[20] = rs1_i[20] | op2[20]; - assign or_out[19] = rs1_i[19] | op2[19]; - assign or_out[18] = rs1_i[18] | op2[18]; - assign or_out[17] = rs1_i[17] | op2[17]; - assign or_out[16] = rs1_i[16] | op2[16]; - assign or_out[15] = rs1_i[15] | op2[15]; - assign or_out[14] = rs1_i[14] | op2[14]; - assign or_out[13] = rs1_i[13] | op2[13]; - assign or_out[12] = rs1_i[12] | op2[12]; - assign or_out[11] = rs1_i[11] | op2[11]; - assign or_out[10] = rs1_i[10] | op2[10]; - assign or_out[9] = rs1_i[9] | op2[9]; - assign or_out[8] = rs1_i[8] | op2[8]; - assign or_out[7] = rs1_i[7] | op2[7]; - assign or_out[6] = rs1_i[6] | op2[6]; - assign or_out[5] = rs1_i[5] | op2[5]; - assign or_out[4] = rs1_i[4] | op2[4]; - assign or_out[3] = rs1_i[3] | op2[3]; - assign or_out[2] = rs1_i[2] | op2[2]; - assign or_out[1] = rs1_i[1] | op2[1]; - assign or_out[0] = rs1_i[0] | op2[0]; - assign N105 = ~op_i[3]; - assign N120 = N117 | N119; - assign N121 = ~op_i[31]; - assign N122 = ~op_i[30]; - assign N123 = ~op_i[29]; - assign N124 = ~op_i[27]; - assign N140 = N137 | N139; - assign N146 = N143 | N145; - assign N155 = ~op_i[28]; - assign N156 = ~op_i[26]; - assign N157 = ~op_i[25]; - assign N170 = N154 | N169; - assign N178 = N173 | N177; - assign N188 = N182 | N187; - assign N201 = N196 | N200; - assign N206 = N203 | N205; - assign N214 = N211 | N213; - assign N293 = ~carry; - assign N298 = ~N297; - assign N299 = ~op_i[13]; - assign N300 = ~op_i[12]; - assign N310 = ~op_i[14]; - assign N312 = ~rs1_eq_rs2; - assign N313 = ~rs1_lt_rs2_signed; - assign N314 = ~rs1_lt_rs2_unsigned; - -endmodule - - - -module cl_state_machine -( - instruction_i, - state_i, - net_pc_write_cmd_idle_i, - stall_i, - state_o -); - - input [31:0] instruction_i; - input [1:0] state_i; - output [1:0] state_o; - input net_pc_write_cmd_idle_i; - input stall_i; - wire [1:0] state_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11; - assign N6 = N4 & N5; - assign N7 = state_i[1] | N5; - assign N9 = state_i[1] & state_i[0]; - assign N10 = N4 | state_i[0]; - assign state_o = (N0)? { 1'b0, net_pc_write_cmd_idle_i } : - (N1)? { 1'b0, 1'b1 } : - (N2)? { 1'b1, 1'b1 } : - (N3)? { 1'b1, 1'b1 } : 1'b0; - assign N0 = N6; - assign N1 = N8; - assign N2 = N9; - assign N3 = N11; - assign N4 = ~state_i[1]; - assign N5 = ~state_i[0]; - assign N8 = ~N7; - assign N11 = ~N10; - -endmodule - - - -module bsg_dff_reset_width_p32_harden_p1 -( - clock_i, - data_i, - reset_i, - data_o -); - - input [31:0] data_i; - output [31:0] data_o; - input clock_i; - input reset_i; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34; - reg [31:0] data_o; - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[31] <= N34; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[30] <= N33; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[29] <= N32; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[28] <= N31; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[27] <= N30; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[26] <= N29; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[25] <= N28; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[24] <= N27; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[23] <= N26; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[22] <= N25; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[21] <= N24; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[20] <= N23; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[19] <= N22; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[18] <= N21; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[17] <= N20; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[16] <= N19; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[15] <= N18; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[14] <= N17; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[13] <= N16; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[12] <= N15; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[11] <= N14; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[10] <= N13; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[9] <= N12; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[8] <= N11; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[7] <= N10; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[6] <= N9; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[5] <= N8; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[4] <= N7; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[3] <= N6; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[2] <= N5; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[1] <= N4; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[0] <= N3; - end - end - - assign { N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N1)? data_i : 1'b0; - assign N0 = reset_i; - assign N1 = N2; - assign N2 = ~reset_i; - -endmodule - - - -module bsg_dff_reset_width_p65_harden_p0 -( - clock_i, - data_i, - reset_i, - data_o -); - - input [64:0] data_i; - output [64:0] data_o; - input clock_i; - input reset_i; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21, - N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41, - N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61, - N62,N63,N64,N65,N66,N67; - reg [64:0] data_o; - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[64] <= N67; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[63] <= N66; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[62] <= N65; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[61] <= N64; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[60] <= N63; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[59] <= N62; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[58] <= N61; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[57] <= N60; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[56] <= N59; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[55] <= N58; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[54] <= N57; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[53] <= N56; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[52] <= N55; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[51] <= N54; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[50] <= N53; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[49] <= N52; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[48] <= N51; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[47] <= N50; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[46] <= N49; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[45] <= N48; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[44] <= N47; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[43] <= N46; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[42] <= N45; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[41] <= N44; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[40] <= N43; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[39] <= N42; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[38] <= N41; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[37] <= N40; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[36] <= N39; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[35] <= N38; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[34] <= N37; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[33] <= N36; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[32] <= N35; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[31] <= N34; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[30] <= N33; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[29] <= N32; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[28] <= N31; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[27] <= N30; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[26] <= N29; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[25] <= N28; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[24] <= N27; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[23] <= N26; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[22] <= N25; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[21] <= N24; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[20] <= N23; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[19] <= N22; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[18] <= N21; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[17] <= N20; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[16] <= N19; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[15] <= N18; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[14] <= N17; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[13] <= N16; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[12] <= N15; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[11] <= N14; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[10] <= N13; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[9] <= N12; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[8] <= N11; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[7] <= N10; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[6] <= N9; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[5] <= N8; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[4] <= N7; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[3] <= N6; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[2] <= N5; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[1] <= N4; - end - end - - - always @(posedge clock_i) begin - if(1'b1) begin - data_o[0] <= N3; - end - end - - assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N1)? data_i : 1'b0; - assign N0 = reset_i; - assign N1 = N2; - assign N2 = ~reset_i; - -endmodule - - - -module bsg_dff_reset_en_width_p10_harden_p1 -( - clock_i, - reset_i, - en_i, - data_i, - data_o -); - - input [9:0] data_i; - output [9:0] data_o; - input clock_i; - input reset_i; - input en_i; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15; - reg [9:0] data_o; - - always @(posedge clock_i) begin - if(N3) begin - data_o[9] <= N13; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[8] <= N12; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[7] <= N11; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[6] <= N10; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[5] <= N9; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[4] <= N8; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[3] <= N7; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[2] <= N6; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[1] <= N5; - end - end - - - always @(posedge clock_i) begin - if(N3) begin - data_o[0] <= N4; - end - end - - assign N3 = (N0)? 1'b1 : - (N15)? 1'b1 : - (N2)? 1'b0 : 1'b0; - assign N0 = reset_i; - assign { N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N15)? data_i : 1'b0; - assign N1 = en_i | reset_i; - assign N2 = ~N1; - assign N14 = ~reset_i; - assign N15 = en_i & N14; - -endmodule - - - -module hobbit_imem_addr_width_p10_gw_ID_p0_ring_ID_p0_x_cord_width_p4_y_cord_width_p5 -( - clk, - reset, - net_packet_i, - from_mem_i, - to_mem_o, - reservation_i, - reserve_1_o, - my_x_i, - my_y_i, - outstanding_stores_i -); - - input [64:0] net_packet_i; - input [33:0] from_mem_i; - output [70:0] to_mem_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk; - input reset; - input reservation_i; - input outstanding_stores_i; - output reserve_1_o; - wire reserve_1_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18, - N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38, - N39,N40,N41,N42,net_packet_r_valid_,net_packet_r_header__bc_, - net_packet_r_header__external_,net_packet_r_header__gw_ID__2_,net_packet_r_header__gw_ID__1_, - net_packet_r_header__gw_ID__0_,net_packet_r_header__ring_ID__4_, - net_packet_r_header__ring_ID__3_,net_packet_r_header__ring_ID__2_,net_packet_r_header__ring_ID__1_, - net_packet_r_header__ring_ID__0_,net_packet_r_header__net_op__1_, - net_packet_r_header__net_op__0_,net_packet_r_header__mask__3_,net_packet_r_header__mask__2_, - net_packet_r_header__mask__1_,net_packet_r_header__mask__0_, - net_packet_r_header__reserved__1_,net_packet_r_header__reserved__0_,net_packet_r_header__addr__13_, - net_packet_r_header__addr__12_,net_packet_r_header__addr__11_, - net_packet_r_header__addr__10_,net_packet_r_header__addr__9_,net_packet_r_header__addr__8_, - net_packet_r_header__addr__7_,net_packet_r_header__addr__6_,net_packet_r_header__addr__5_, - net_packet_r_header__addr__4_,net_packet_r_header__addr__3_, - net_packet_r_header__addr__2_,net_packet_r_header__addr__1_,net_packet_r_header__addr__0_, - net_id_match_valid,exec_net_packet,net_pc_write_cmd,net_imem_write_cmd,net_reg_write_cmd, - net_pc_write_cmd_idle,data_mem_valid,stall_md,stall_non_mem,stall_fence,stall_lrw, - stall_mem,stall,N43,id_exe_rs1_match,N44,id_exe_rs2_match,depend_stall,N45,N46,N47, - N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67, - N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87, - N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105, - N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121, - N122,N123,N124,N125,jump_now,branch_under_predict,branch_over_predict, - branch_mispredict,N126,jalr_mispredict,flush,pc_wen,instruction_rs1__4_,instruction_rs1__3_, - instruction_rs1__2_,instruction_rs1__1_,instruction_rs1__0_, - instruction_funct3__2_,instruction_funct3__1_,instruction_op__6_,instruction_op__5_, - instruction_op__4_,instruction_op__3_,instruction_op__2_,instruction_op__1_,instruction_op__0_, - JImm_extract_11,JImm_extract_10,decode_op_writes_rf_,decode_is_load_op_, - decode_is_store_op_,decode_is_mem_op_,decode_is_byte_op_,decode_is_hex_op_, - decode_is_load_unsigned_,decode_is_branch_op_,decode_is_jump_op_,decode_op_reads_rf1_, - decode_op_reads_rf2_,decode_op_is_auipc_,decode_is_md_instr_,decode_is_fence_op_, - decode_is_fence_i_op_,decode_op_is_load_reservation_,decode_op_is_lr_acq_,N127,N128,N129, - N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145, - N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161, - N162,N163,N164,N165,N166,imem_cen,BImm_sign_ext_31,JImm_sign_ext_4, - JImm_sign_ext_3,JImm_sign_ext_2,JImm_sign_ext_1,instr_cast_op__6_,instr_cast_op__5_, - instr_cast_op__4_,instr_cast_op__3_,instr_cast_op__2_,instr_cast_op__1_, - instr_cast_op__0_,write_branch_instr,write_jal_instr,N167,inject_pc_rel_9,N168,N169, - imem_w_data_0,N170,N171,N172,rf_wen,N173,rf_cen,md_ready,md_valid,md_resp_valid,n_3_net_, - rs1_is_forward,rs2_is_forward,N174,n_cse_43,N175,N176,N177,id_wb_rs1_forward,N178, - id_wb_rs2_forward,N179,N180,N181,N182,N183,exe_rs1_in_mem,N184,exe_rs1_in_wb,N185, - exe_rs2_in_mem,N186,exe_rs2_in_wb,n_cse_62,N187,N188,N189,N190,N191,N192,N193, - N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209, - N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225, - N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241, - N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257, - N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273, - N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289, - N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305, - N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321, - N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337, - N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353, - N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369, - N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,N385, - N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,N401, - N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,N417, - N418,N419,N420,N421,N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,N433, - N434,N435,N436,N437,N438,N439,N440,N441,N442; - wire [31:0] rs2_to_alu,mem_addr_op2,rs1_to_alu,jalr_prediction_rr,jalr_prediction_n, - jalr_prediction_r,imem_out,instruction_r,rf_wd,rf_rs1_val,rf_rs2_val,md_result, - rs1_forward_val,rs2_forward_val,basic_comp_result,alu_result,rf_rs1_index0_fix, - rf_rs2_index0_fix,rs1_to_exe,rs2_to_exe,loaded_data,mem_loaded_data,rf_data; - wire [9:0] jalr_addr,pc_r,pc_plus4,pc_n,imem_addr,inject_pc_value; - wire [11:0] BImm_extract; - wire [3:0] JImm_extract,pc_jump_addr; - wire [11:1] BImm_sign_ext; - wire [19:11] JImm_sign_ext; - wire [2:0] inject_pc_rel; - wire [31:7] imem_w_data; - wire [4:0] rf_wa; - wire [1:0] state_n; - wire [7:0] loaded_byte; - wire [15:0] loaded_hex; - reg pc_wen_r,id_pc_plus4__31_,id_pc_plus4__30_,id_pc_plus4__29_,id_pc_plus4__28_, - id_pc_plus4__27_,id_pc_plus4__26_,id_pc_plus4__25_,id_pc_plus4__24_, - id_pc_plus4__23_,id_pc_plus4__22_,id_pc_plus4__21_,id_pc_plus4__20_,id_pc_plus4__19_, - id_pc_plus4__18_,id_pc_plus4__17_,id_pc_plus4__16_,id_pc_plus4__15_,id_pc_plus4__14_, - id_pc_plus4__13_,id_pc_plus4__12_,id_pc_plus4__11_,id_pc_plus4__10_,id_pc_plus4__9_, - id_pc_plus4__8_,id_pc_plus4__7_,id_pc_plus4__6_,id_pc_plus4__5_,id_pc_plus4__4_, - id_pc_plus4__3_,id_pc_plus4__2_,id_pc_plus4__1_,id_pc_plus4__0_, - id_pc_jump_addr__11_,id_pc_jump_addr__10_,id_pc_jump_addr__9_,id_pc_jump_addr__8_, - id_pc_jump_addr__7_,id_pc_jump_addr__6_,id_pc_jump_addr__5_,id_pc_jump_addr__4_, - id_pc_jump_addr__3_,id_pc_jump_addr__2_,id_instruction__funct7__6_,id_instruction__funct7__5_, - id_instruction__funct7__4_,id_instruction__funct7__3_,id_instruction__funct7__2_, - id_instruction__funct7__1_,id_instruction__funct7__0_,id_instruction__rs2__4_, - id_instruction__rs2__3_,id_instruction__rs2__2_,id_instruction__rs2__1_, - id_instruction__rs2__0_,id_instruction__rs1__4_,id_instruction__rs1__3_, - id_instruction__rs1__2_,id_instruction__rs1__1_,id_instruction__rs1__0_, - id_instruction__funct3__2_,id_instruction__funct3__1_,id_instruction__funct3__0_,id_instruction__rd__4_, - id_instruction__rd__3_,id_instruction__rd__2_,id_instruction__rd__1_, - id_instruction__rd__0_,id_instruction__op__6_,id_instruction__op__5_,id_instruction__op__4_, - id_instruction__op__3_,id_instruction__op__2_,id_instruction__op__1_, - id_instruction__op__0_,id_decode__op_writes_rf_,id_decode__is_load_op_, - id_decode__is_store_op_,id_decode__is_mem_op_,id_decode__is_byte_op_,id_decode__is_hex_op_, - id_decode__is_load_unsigned_,id_decode__is_branch_op_,id_decode__is_jump_op_, - id_decode__op_reads_rf1_,id_decode__op_reads_rf2_,id_decode__is_md_instr_, - id_decode__is_fence_op_,id_decode__op_is_load_reservation_,id_decode__op_is_lr_acq_, - exe_pc_plus4__31_,exe_pc_plus4__30_,exe_pc_plus4__29_,exe_pc_plus4__28_,exe_pc_plus4__27_, - exe_pc_plus4__26_,exe_pc_plus4__25_,exe_pc_plus4__24_,exe_pc_plus4__23_, - exe_pc_plus4__22_,exe_pc_plus4__21_,exe_pc_plus4__20_,exe_pc_plus4__19_,exe_pc_plus4__18_, - exe_pc_plus4__17_,exe_pc_plus4__16_,exe_pc_plus4__15_,exe_pc_plus4__14_, - exe_pc_plus4__13_,exe_pc_plus4__12_,exe_pc_plus4__11_,exe_pc_plus4__10_,exe_pc_plus4__9_, - exe_pc_plus4__8_,exe_pc_plus4__7_,exe_pc_plus4__6_,exe_pc_plus4__5_, - exe_pc_plus4__4_,exe_pc_plus4__3_,exe_pc_plus4__2_,exe_pc_plus4__1_,exe_pc_plus4__0_, - exe_pc_jump_addr__11_,exe_pc_jump_addr__10_,exe_pc_jump_addr__9_,exe_pc_jump_addr__8_, - exe_pc_jump_addr__7_,exe_pc_jump_addr__6_,exe_pc_jump_addr__5_, - exe_pc_jump_addr__4_,exe_pc_jump_addr__3_,exe_pc_jump_addr__2_,exe_instruction__funct7__6_, - exe_instruction__funct7__5_,exe_instruction__funct7__4_,exe_instruction__funct7__3_, - exe_instruction__funct7__2_,exe_instruction__funct7__1_,exe_instruction__funct7__0_, - exe_instruction__rs2__4_,exe_instruction__rs2__3_,exe_instruction__rs2__2_, - exe_instruction__rs2__1_,exe_instruction__rs2__0_,exe_instruction__rs1__4_, - exe_instruction__rs1__3_,exe_instruction__rs1__2_,exe_instruction__rs1__1_, - exe_instruction__rs1__0_,exe_instruction__funct3__2_,exe_instruction__funct3__1_, - exe_instruction__funct3__0_,exe_instruction__rd__4_,exe_instruction__rd__3_, - exe_instruction__rd__2_,exe_instruction__rd__1_,exe_instruction__rd__0_,exe_instruction__op__6_, - exe_instruction__op__5_,exe_instruction__op__4_,exe_instruction__op__3_, - exe_instruction__op__2_,exe_instruction__op__1_,exe_instruction__op__0_, - exe_decode__op_writes_rf_,exe_decode__is_load_op_,exe_decode__is_mem_op_,exe_decode__is_byte_op_, - exe_decode__is_hex_op_,exe_decode__is_load_unsigned_,exe_decode__is_branch_op_, - exe_decode__is_jump_op_,exe_decode__is_md_instr_,exe_decode__is_fence_op_, - exe_decode__op_is_load_reservation_,exe_decode__op_is_lr_acq_,exe_rs1_val__31_, - exe_rs1_val__30_,exe_rs1_val__29_,exe_rs1_val__28_,exe_rs1_val__27_,exe_rs1_val__26_, - exe_rs1_val__25_,exe_rs1_val__24_,exe_rs1_val__23_,exe_rs1_val__22_,exe_rs1_val__21_, - exe_rs1_val__20_,exe_rs1_val__19_,exe_rs1_val__18_,exe_rs1_val__17_, - exe_rs1_val__16_,exe_rs1_val__15_,exe_rs1_val__14_,exe_rs1_val__13_,exe_rs1_val__12_, - exe_rs1_val__11_,exe_rs1_val__10_,exe_rs1_val__9_,exe_rs1_val__8_,exe_rs1_val__7_, - exe_rs1_val__6_,exe_rs1_val__5_,exe_rs1_val__4_,exe_rs1_val__3_,exe_rs1_val__2_, - exe_rs1_val__1_,exe_rs1_val__0_,exe_rs2_val__31_,exe_rs2_val__30_,exe_rs2_val__29_, - exe_rs2_val__28_,exe_rs2_val__27_,exe_rs2_val__26_,exe_rs2_val__25_, - exe_rs2_val__24_,exe_rs2_val__23_,exe_rs2_val__22_,exe_rs2_val__21_,exe_rs2_val__20_, - exe_rs2_val__19_,exe_rs2_val__18_,exe_rs2_val__17_,exe_rs2_val__16_,exe_rs2_val__15_, - exe_rs2_val__14_,exe_rs2_val__13_,exe_rs2_val__12_,exe_rs2_val__11_, - exe_rs2_val__10_,exe_rs2_val__9_,exe_rs2_val__8_,exe_rs2_val__7_,exe_rs2_val__6_, - exe_rs2_val__5_,exe_rs2_val__4_,exe_rs2_val__3_,exe_rs2_val__2_,exe_rs2_val__1_, - exe_rs2_val__0_,exe_mem_addr_op2__31_,exe_mem_addr_op2__30_,exe_mem_addr_op2__29_, - exe_mem_addr_op2__28_,exe_mem_addr_op2__27_,exe_mem_addr_op2__26_,exe_mem_addr_op2__25_, - exe_mem_addr_op2__24_,exe_mem_addr_op2__23_,exe_mem_addr_op2__22_, - exe_mem_addr_op2__21_,exe_mem_addr_op2__20_,exe_mem_addr_op2__19_,exe_mem_addr_op2__18_, - exe_mem_addr_op2__17_,exe_mem_addr_op2__16_,exe_mem_addr_op2__15_,exe_mem_addr_op2__14_, - exe_mem_addr_op2__13_,exe_mem_addr_op2__12_,exe_mem_addr_op2__11_, - exe_mem_addr_op2__10_,exe_mem_addr_op2__9_,exe_mem_addr_op2__8_,exe_mem_addr_op2__7_, - exe_mem_addr_op2__6_,exe_mem_addr_op2__5_,exe_mem_addr_op2__4_,exe_mem_addr_op2__3_, - exe_mem_addr_op2__2_,exe_mem_addr_op2__1_,exe_mem_addr_op2__0_,exe_rs1_in_mem_, - exe_rs1_in_wb_,exe_rs2_in_mem_,exe_rs2_in_wb_,mem_rd_addr__4_,mem_rd_addr__3_, - mem_rd_addr__2_,mem_rd_addr__1_,mem_rd_addr__0_,mem_decode__op_writes_rf_, - mem_decode__is_load_op_,mem_decode__is_mem_op_,mem_decode__is_byte_op_,mem_decode__is_hex_op_, - mem_decode__is_load_unsigned_,mem_alu_result__31_,mem_alu_result__30_, - mem_alu_result__29_,mem_alu_result__28_,mem_alu_result__27_,mem_alu_result__26_, - mem_alu_result__25_,mem_alu_result__24_,mem_alu_result__23_,mem_alu_result__22_, - mem_alu_result__21_,mem_alu_result__20_,mem_alu_result__19_,mem_alu_result__18_, - mem_alu_result__17_,mem_alu_result__16_,mem_alu_result__15_,mem_alu_result__14_, - mem_alu_result__13_,mem_alu_result__12_,mem_alu_result__11_,mem_alu_result__10_, - mem_alu_result__9_,mem_alu_result__8_,mem_alu_result__7_,mem_alu_result__6_, - mem_alu_result__5_,mem_alu_result__4_,mem_alu_result__3_,mem_alu_result__2_,mem_alu_result__1_, - mem_alu_result__0_,mem_mem_addr_send__1_,mem_mem_addr_send__0_, - is_load_buffer_valid; - reg [1:0] state_r; - reg [70:0] to_mem_o; - reg [31:0] load_buffer_data; - reg [37:0] wb; - assign N43 = { id_instruction__rs1__4_, id_instruction__rs1__3_, id_instruction__rs1__2_, id_instruction__rs1__1_, id_instruction__rs1__0_ } == { exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_ }; - assign N44 = { id_instruction__rs2__4_, id_instruction__rs2__3_, id_instruction__rs2__2_, id_instruction__rs2__1_, id_instruction__rs2__0_ } == { exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_ }; - assign { N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, rs2_to_alu[7:0] } << { to_mem_o[34:33], 1'b0, 1'b0, 1'b0 }; - assign { N82, N81, N80, N79 } = { 1'b0, 1'b0, 1'b0, 1'b1 } << to_mem_o[34:33]; - assign { N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, rs2_to_alu[15:0] } << { to_mem_o[34:33], 1'b0, 1'b0, 1'b0 }; - assign { N119, N118, N117, N116 } = { 1'b0, 1'b0, 1'b1, 1'b1 } << to_mem_o[34:33]; - assign N126 = jalr_addr != jalr_prediction_rr; - - bsg_mem_1rw_sync_width_p32_els_p1024 - imem_0 - ( - .clk_i(clk), - .reset_i(reset), - .data_i({ imem_w_data, instr_cast_op__6_, instr_cast_op__5_, instr_cast_op__4_, instr_cast_op__3_, instr_cast_op__2_, instr_cast_op__1_, imem_w_data_0 }), - .addr_i(imem_addr), - .v_i(imem_cen), - .w_i(net_imem_write_cmd), - .data_o(imem_out) - ); - - - cl_decode - cl_decode_0 - ( - .instruction_i({ BImm_extract[11:11], BImm_extract[9:4], JImm_extract, JImm_extract_10, instruction_rs1__4_, instruction_rs1__3_, instruction_rs1__2_, instruction_rs1__1_, instruction_rs1__0_, instruction_funct3__2_, instruction_funct3__1_, JImm_extract_11, BImm_extract[3:0], BImm_extract[10:10], instruction_op__6_, instruction_op__5_, instruction_op__4_, instruction_op__3_, instruction_op__2_, instruction_op__1_, instruction_op__0_ }), - .decode_o_op_writes_rf_(decode_op_writes_rf_), - .decode_o_is_load_op_(decode_is_load_op_), - .decode_o_is_store_op_(decode_is_store_op_), - .decode_o_is_mem_op_(decode_is_mem_op_), - .decode_o_is_byte_op_(decode_is_byte_op_), - .decode_o_is_hex_op_(decode_is_hex_op_), - .decode_o_is_load_unsigned_(decode_is_load_unsigned_), - .decode_o_is_branch_op_(decode_is_branch_op_), - .decode_o_is_jump_op_(decode_is_jump_op_), - .decode_o_op_reads_rf1_(decode_op_reads_rf1_), - .decode_o_op_reads_rf2_(decode_op_reads_rf2_), - .decode_o_op_is_auipc_(decode_op_is_auipc_), - .decode_o_is_md_instr_(decode_is_md_instr_), - .decode_o_is_fence_op_(decode_is_fence_op_), - .decode_o_is_fence_i_op_(decode_is_fence_i_op_), - .decode_o_op_is_load_reservation_(decode_op_is_load_reservation_), - .decode_o_op_is_lr_acq_(decode_op_is_lr_acq_) - ); - - - rf_2r1w_sync_wrapper_width_p32_els_p32 - rf_0 - ( - .clk_i(clk), - .reset_i(reset), - .w_v_i(rf_wen), - .w_addr_i(rf_wa), - .w_data_i(rf_wd), - .r0_v_i(rf_cen), - .r0_addr_i({ instruction_rs1__4_, instruction_rs1__3_, instruction_rs1__2_, instruction_rs1__1_, instruction_rs1__0_ }), - .r0_data_o(rf_rs1_val), - .r1_v_i(rf_cen), - .r1_addr_i({ JImm_extract, JImm_extract_10 }), - .r1_data_o(rf_rs2_val) - ); - - - imul_idiv_iterative - md_0 - ( - .reset_i(reset), - .clk_i(clk), - .v_i(md_valid), - .ready_o(md_ready), - .opA_i(rs1_to_alu), - .opB_i(rs2_to_alu), - .funct3({ exe_instruction__funct3__2_, exe_instruction__funct3__1_, exe_instruction__funct3__0_ }), - .v_o(md_resp_valid), - .result_o(md_result), - .yumi_i(n_3_net_) - ); - - - bsg_mux_width_p32_els_p2 - rs1_forward_mux - ( - .data_i({ mem_alu_result__31_, mem_alu_result__30_, mem_alu_result__29_, mem_alu_result__28_, mem_alu_result__27_, mem_alu_result__26_, mem_alu_result__25_, mem_alu_result__24_, mem_alu_result__23_, mem_alu_result__22_, mem_alu_result__21_, mem_alu_result__20_, mem_alu_result__19_, mem_alu_result__18_, mem_alu_result__17_, mem_alu_result__16_, mem_alu_result__15_, mem_alu_result__14_, mem_alu_result__13_, mem_alu_result__12_, mem_alu_result__11_, mem_alu_result__10_, mem_alu_result__9_, mem_alu_result__8_, mem_alu_result__7_, mem_alu_result__6_, mem_alu_result__5_, mem_alu_result__4_, mem_alu_result__3_, mem_alu_result__2_, mem_alu_result__1_, mem_alu_result__0_, wb[31:0] }), - .sel_i(exe_rs1_in_mem_), - .data_o(rs1_forward_val) - ); - - - bsg_mux_width_p32_els_p2 - rs2_forward_mux - ( - .data_i({ mem_alu_result__31_, mem_alu_result__30_, mem_alu_result__29_, mem_alu_result__28_, mem_alu_result__27_, mem_alu_result__26_, mem_alu_result__25_, mem_alu_result__24_, mem_alu_result__23_, mem_alu_result__22_, mem_alu_result__21_, mem_alu_result__20_, mem_alu_result__19_, mem_alu_result__18_, mem_alu_result__17_, mem_alu_result__16_, mem_alu_result__15_, mem_alu_result__14_, mem_alu_result__13_, mem_alu_result__12_, mem_alu_result__11_, mem_alu_result__10_, mem_alu_result__9_, mem_alu_result__8_, mem_alu_result__7_, mem_alu_result__6_, mem_alu_result__5_, mem_alu_result__4_, mem_alu_result__3_, mem_alu_result__2_, mem_alu_result__1_, mem_alu_result__0_, wb[31:0] }), - .sel_i(exe_rs2_in_mem_), - .data_o(rs2_forward_val) - ); - - - bsg_mux_width_p32_els_p2 - rs1_alu_mux - ( - .data_i({ rs1_forward_val, exe_rs1_val__31_, exe_rs1_val__30_, exe_rs1_val__29_, exe_rs1_val__28_, exe_rs1_val__27_, exe_rs1_val__26_, exe_rs1_val__25_, exe_rs1_val__24_, exe_rs1_val__23_, exe_rs1_val__22_, exe_rs1_val__21_, exe_rs1_val__20_, exe_rs1_val__19_, exe_rs1_val__18_, exe_rs1_val__17_, exe_rs1_val__16_, exe_rs1_val__15_, exe_rs1_val__14_, exe_rs1_val__13_, exe_rs1_val__12_, exe_rs1_val__11_, exe_rs1_val__10_, exe_rs1_val__9_, exe_rs1_val__8_, exe_rs1_val__7_, exe_rs1_val__6_, exe_rs1_val__5_, exe_rs1_val__4_, exe_rs1_val__3_, exe_rs1_val__2_, exe_rs1_val__1_, exe_rs1_val__0_ }), - .sel_i(rs1_is_forward), - .data_o(rs1_to_alu) - ); - - - bsg_mux_width_p32_els_p2 - rs2_alu_mux - ( - .data_i({ rs2_forward_val, exe_rs2_val__31_, exe_rs2_val__30_, exe_rs2_val__29_, exe_rs2_val__28_, exe_rs2_val__27_, exe_rs2_val__26_, exe_rs2_val__25_, exe_rs2_val__24_, exe_rs2_val__23_, exe_rs2_val__22_, exe_rs2_val__21_, exe_rs2_val__20_, exe_rs2_val__19_, exe_rs2_val__18_, exe_rs2_val__17_, exe_rs2_val__16_, exe_rs2_val__15_, exe_rs2_val__14_, exe_rs2_val__13_, exe_rs2_val__12_, exe_rs2_val__11_, exe_rs2_val__10_, exe_rs2_val__9_, exe_rs2_val__8_, exe_rs2_val__7_, exe_rs2_val__6_, exe_rs2_val__5_, exe_rs2_val__4_, exe_rs2_val__3_, exe_rs2_val__2_, exe_rs2_val__1_, exe_rs2_val__0_ }), - .sel_i(rs2_is_forward), - .data_o(rs2_to_alu) - ); - - - alu_imem_addr_width_p10 - alu_0 - ( - .rs1_i(rs1_to_alu), - .rs2_i(rs2_to_alu), - .pc_plus4_i({ exe_pc_plus4__31_, exe_pc_plus4__30_, exe_pc_plus4__29_, exe_pc_plus4__28_, exe_pc_plus4__27_, exe_pc_plus4__26_, exe_pc_plus4__25_, exe_pc_plus4__24_, exe_pc_plus4__23_, exe_pc_plus4__22_, exe_pc_plus4__21_, exe_pc_plus4__20_, exe_pc_plus4__19_, exe_pc_plus4__18_, exe_pc_plus4__17_, exe_pc_plus4__16_, exe_pc_plus4__15_, exe_pc_plus4__14_, exe_pc_plus4__13_, exe_pc_plus4__12_, exe_pc_plus4__11_, exe_pc_plus4__10_, exe_pc_plus4__9_, exe_pc_plus4__8_, exe_pc_plus4__7_, exe_pc_plus4__6_, exe_pc_plus4__5_, exe_pc_plus4__4_, exe_pc_plus4__3_, exe_pc_plus4__2_, exe_pc_plus4__1_, exe_pc_plus4__0_ }), - .op_i({ exe_instruction__funct7__6_, exe_instruction__funct7__5_, exe_instruction__funct7__4_, exe_instruction__funct7__3_, exe_instruction__funct7__2_, exe_instruction__funct7__1_, exe_instruction__funct7__0_, exe_instruction__rs2__4_, exe_instruction__rs2__3_, exe_instruction__rs2__2_, exe_instruction__rs2__1_, exe_instruction__rs2__0_, exe_instruction__rs1__4_, exe_instruction__rs1__3_, exe_instruction__rs1__2_, exe_instruction__rs1__1_, exe_instruction__rs1__0_, exe_instruction__funct3__2_, exe_instruction__funct3__1_, exe_instruction__funct3__0_, exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_, exe_instruction__op__6_, exe_instruction__op__5_, exe_instruction__op__4_, exe_instruction__op__3_, exe_instruction__op__2_, exe_instruction__op__1_, exe_instruction__op__0_ }), - .result_o(basic_comp_result), - .jalr_addr_o(jalr_addr), - .jump_now_o(jump_now) - ); - - - cl_state_machine - state_machine - ( - .instruction_i({ exe_instruction__funct7__6_, exe_instruction__funct7__5_, exe_instruction__funct7__4_, exe_instruction__funct7__3_, exe_instruction__funct7__2_, exe_instruction__funct7__1_, exe_instruction__funct7__0_, exe_instruction__rs2__4_, exe_instruction__rs2__3_, exe_instruction__rs2__2_, exe_instruction__rs2__1_, exe_instruction__rs2__0_, exe_instruction__rs1__4_, exe_instruction__rs1__3_, exe_instruction__rs1__2_, exe_instruction__rs1__1_, exe_instruction__rs1__0_, exe_instruction__funct3__2_, exe_instruction__funct3__1_, exe_instruction__funct3__0_, exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_, exe_instruction__op__6_, exe_instruction__op__5_, exe_instruction__op__4_, exe_instruction__op__3_, exe_instruction__op__2_, exe_instruction__op__1_, exe_instruction__op__0_ }), - .state_i(state_r), - .net_pc_write_cmd_idle_i(net_pc_write_cmd_idle), - .stall_i(stall), - .state_o(state_n) - ); - - - always @(posedge clk) begin - if(reset) begin - pc_wen_r <= 1'b0; - end else if(1'b1) begin - pc_wen_r <= pc_wen; - end - end - - - always @(posedge clk) begin - if(reset) begin - state_r[1] <= 1'b0; - end else if(1'b1) begin - state_r[1] <= state_n[1]; - end - end - - - always @(posedge clk) begin - if(reset) begin - state_r[0] <= 1'b0; - end else if(1'b1) begin - state_r[0] <= state_n[0]; - end - end - - - bsg_dff_reset_width_p32_harden_p1 - jalr_prediction_r_reg - ( - .clock_i(clk), - .data_i(jalr_prediction_n), - .reset_i(reset), - .data_o(jalr_prediction_r) - ); - - - bsg_dff_reset_width_p32_harden_p1 - jalr_prediction_rr_reg - ( - .clock_i(clk), - .data_i(jalr_prediction_r), - .reset_i(reset), - .data_o(jalr_prediction_rr) - ); - - - bsg_dff_reset_width_p65_harden_p0 - net_packet_r_reg - ( - .clock_i(clk), - .data_i(net_packet_i), - .reset_i(reset), - .data_o({ net_packet_r_valid_, net_packet_r_header__bc_, net_packet_r_header__external_, net_packet_r_header__gw_ID__2_, net_packet_r_header__gw_ID__1_, net_packet_r_header__gw_ID__0_, net_packet_r_header__ring_ID__4_, net_packet_r_header__ring_ID__3_, net_packet_r_header__ring_ID__2_, net_packet_r_header__ring_ID__1_, net_packet_r_header__ring_ID__0_, net_packet_r_header__net_op__1_, net_packet_r_header__net_op__0_, net_packet_r_header__mask__3_, net_packet_r_header__mask__2_, net_packet_r_header__mask__1_, net_packet_r_header__mask__0_, net_packet_r_header__reserved__1_, net_packet_r_header__reserved__0_, net_packet_r_header__addr__13_, net_packet_r_header__addr__12_, net_packet_r_header__addr__11_, net_packet_r_header__addr__10_, net_packet_r_header__addr__9_, net_packet_r_header__addr__8_, net_packet_r_header__addr__7_, net_packet_r_header__addr__6_, net_packet_r_header__addr__5_, net_packet_r_header__addr__4_, net_packet_r_header__addr__3_, net_packet_r_header__addr__2_, net_packet_r_header__addr__1_, net_packet_r_header__addr__0_, BImm_sign_ext_31, BImm_sign_ext[10:5], JImm_sign_ext_4, JImm_sign_ext_3, JImm_sign_ext_2, JImm_sign_ext_1, JImm_sign_ext[11:11], JImm_sign_ext[19:12], BImm_sign_ext[4:1], BImm_sign_ext[11:11], instr_cast_op__6_, instr_cast_op__5_, instr_cast_op__4_, instr_cast_op__3_, instr_cast_op__2_, instr_cast_op__1_, instr_cast_op__0_ }) - ); - - - bsg_dff_reset_width_p32_harden_p1 - instruction_r_reg - ( - .clock_i(clk), - .data_i({ BImm_extract[11:11], BImm_extract[9:4], JImm_extract, JImm_extract_10, instruction_rs1__4_, instruction_rs1__3_, instruction_rs1__2_, instruction_rs1__1_, instruction_rs1__0_, instruction_funct3__2_, instruction_funct3__1_, JImm_extract_11, BImm_extract[3:0], BImm_extract[10:10], instruction_op__6_, instruction_op__5_, instruction_op__4_, instruction_op__3_, instruction_op__2_, instruction_op__1_, instruction_op__0_ }), - .reset_i(reset), - .data_o(instruction_r) - ); - - - bsg_dff_reset_en_width_p10_harden_p1 - pc_r_reg - ( - .clock_i(clk), - .reset_i(reset), - .en_i(pc_wen), - .data_i(pc_n), - .data_o(pc_r) - ); - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__31_ <= 1'b0; - end else begin - id_pc_plus4__31_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__30_ <= 1'b0; - end else begin - id_pc_plus4__30_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__29_ <= 1'b0; - end else begin - id_pc_plus4__29_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__28_ <= 1'b0; - end else begin - id_pc_plus4__28_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__27_ <= 1'b0; - end else begin - id_pc_plus4__27_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__26_ <= 1'b0; - end else begin - id_pc_plus4__26_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__25_ <= 1'b0; - end else begin - id_pc_plus4__25_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__24_ <= 1'b0; - end else begin - id_pc_plus4__24_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__23_ <= 1'b0; - end else begin - id_pc_plus4__23_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__22_ <= 1'b0; - end else begin - id_pc_plus4__22_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__21_ <= 1'b0; - end else begin - id_pc_plus4__21_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__20_ <= 1'b0; - end else begin - id_pc_plus4__20_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__19_ <= 1'b0; - end else begin - id_pc_plus4__19_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__18_ <= 1'b0; - end else begin - id_pc_plus4__18_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__17_ <= 1'b0; - end else begin - id_pc_plus4__17_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__16_ <= 1'b0; - end else begin - id_pc_plus4__16_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__15_ <= 1'b0; - end else begin - id_pc_plus4__15_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__14_ <= 1'b0; - end else begin - id_pc_plus4__14_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__13_ <= 1'b0; - end else begin - id_pc_plus4__13_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__12_ <= 1'b0; - end else begin - id_pc_plus4__12_ <= N42; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__11_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__11_ <= pc_plus4[9]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__10_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__10_ <= pc_plus4[8]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__9_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__9_ <= pc_plus4[7]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__8_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__8_ <= pc_plus4[6]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__7_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__7_ <= pc_plus4[5]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__6_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__6_ <= pc_plus4[4]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__5_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__5_ <= pc_plus4[3]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__4_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__4_ <= pc_plus4[2]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__3_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__3_ <= pc_plus4[1]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_plus4__2_ <= 1'b0; - end else if(N176) begin - id_pc_plus4__2_ <= pc_plus4[0]; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__1_ <= 1'b0; - end else begin - id_pc_plus4__1_ <= N42; - end - end - - - always @(posedge clk) begin - if(N261) begin - id_pc_plus4__0_ <= 1'b0; - end else begin - id_pc_plus4__0_ <= N42; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__11_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__11_ <= BImm_extract[9]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__10_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__10_ <= BImm_extract[8]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__9_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__9_ <= BImm_extract[7]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__8_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__8_ <= BImm_extract[6]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__7_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__7_ <= BImm_extract[5]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__6_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__6_ <= BImm_extract[4]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__5_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__5_ <= pc_jump_addr[3]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__4_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__4_ <= pc_jump_addr[2]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__3_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__3_ <= pc_jump_addr[1]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_pc_jump_addr__2_ <= 1'b0; - end else if(N176) begin - id_pc_jump_addr__2_ <= pc_jump_addr[0]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__6_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__6_ <= BImm_extract[11]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__5_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__5_ <= BImm_extract[9]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__4_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__4_ <= BImm_extract[8]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__3_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__3_ <= BImm_extract[7]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__2_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__2_ <= BImm_extract[6]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__1_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__1_ <= BImm_extract[5]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct7__0_ <= 1'b0; - end else if(N176) begin - id_instruction__funct7__0_ <= BImm_extract[4]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs2__4_ <= 1'b0; - end else if(N176) begin - id_instruction__rs2__4_ <= JImm_extract[3]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs2__3_ <= 1'b0; - end else if(N176) begin - id_instruction__rs2__3_ <= JImm_extract[2]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs2__2_ <= 1'b0; - end else if(N176) begin - id_instruction__rs2__2_ <= JImm_extract[1]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs2__1_ <= 1'b0; - end else if(N176) begin - id_instruction__rs2__1_ <= JImm_extract[0]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs2__0_ <= 1'b0; - end else if(N176) begin - id_instruction__rs2__0_ <= JImm_extract_10; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs1__4_ <= 1'b0; - end else if(N176) begin - id_instruction__rs1__4_ <= instruction_rs1__4_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs1__3_ <= 1'b0; - end else if(N176) begin - id_instruction__rs1__3_ <= instruction_rs1__3_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs1__2_ <= 1'b0; - end else if(N176) begin - id_instruction__rs1__2_ <= instruction_rs1__2_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs1__1_ <= 1'b0; - end else if(N176) begin - id_instruction__rs1__1_ <= instruction_rs1__1_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rs1__0_ <= 1'b0; - end else if(N176) begin - id_instruction__rs1__0_ <= instruction_rs1__0_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct3__2_ <= 1'b0; - end else if(N176) begin - id_instruction__funct3__2_ <= instruction_funct3__2_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct3__1_ <= 1'b0; - end else if(N176) begin - id_instruction__funct3__1_ <= instruction_funct3__1_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__funct3__0_ <= 1'b0; - end else if(N176) begin - id_instruction__funct3__0_ <= JImm_extract_11; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rd__4_ <= 1'b0; - end else if(N176) begin - id_instruction__rd__4_ <= BImm_extract[3]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rd__3_ <= 1'b0; - end else if(N176) begin - id_instruction__rd__3_ <= BImm_extract[2]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rd__2_ <= 1'b0; - end else if(N176) begin - id_instruction__rd__2_ <= BImm_extract[1]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rd__1_ <= 1'b0; - end else if(N176) begin - id_instruction__rd__1_ <= BImm_extract[0]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__rd__0_ <= 1'b0; - end else if(N176) begin - id_instruction__rd__0_ <= BImm_extract[10]; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__6_ <= 1'b0; - end else if(N176) begin - id_instruction__op__6_ <= instruction_op__6_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__5_ <= 1'b0; - end else if(N176) begin - id_instruction__op__5_ <= instruction_op__5_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__4_ <= 1'b0; - end else if(N176) begin - id_instruction__op__4_ <= instruction_op__4_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__3_ <= 1'b0; - end else if(N176) begin - id_instruction__op__3_ <= instruction_op__3_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__2_ <= 1'b0; - end else if(N176) begin - id_instruction__op__2_ <= instruction_op__2_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__1_ <= 1'b0; - end else if(N176) begin - id_instruction__op__1_ <= instruction_op__1_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_instruction__op__0_ <= 1'b0; - end else if(N176) begin - id_instruction__op__0_ <= instruction_op__0_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__op_writes_rf_ <= 1'b0; - end else if(N176) begin - id_decode__op_writes_rf_ <= decode_op_writes_rf_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_load_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_load_op_ <= decode_is_load_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_store_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_store_op_ <= decode_is_store_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_mem_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_mem_op_ <= decode_is_mem_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_byte_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_byte_op_ <= decode_is_byte_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_hex_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_hex_op_ <= decode_is_hex_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_load_unsigned_ <= 1'b0; - end else if(N176) begin - id_decode__is_load_unsigned_ <= decode_is_load_unsigned_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_branch_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_branch_op_ <= decode_is_branch_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_jump_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_jump_op_ <= decode_is_jump_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__op_reads_rf1_ <= 1'b0; - end else if(N176) begin - id_decode__op_reads_rf1_ <= decode_op_reads_rf1_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__op_reads_rf2_ <= 1'b0; - end else if(N176) begin - id_decode__op_reads_rf2_ <= decode_op_reads_rf2_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_md_instr_ <= 1'b0; - end else if(N176) begin - id_decode__is_md_instr_ <= decode_is_md_instr_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__is_fence_op_ <= 1'b0; - end else if(N176) begin - id_decode__is_fence_op_ <= decode_is_fence_op_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__op_is_load_reservation_ <= 1'b0; - end else if(N176) begin - id_decode__op_is_load_reservation_ <= decode_op_is_load_reservation_; - end - end - - - always @(posedge clk) begin - if(N175) begin - id_decode__op_is_lr_acq_ <= 1'b0; - end else if(N176) begin - id_decode__op_is_lr_acq_ <= decode_op_is_lr_acq_; - end - end - - assign N177 = { id_instruction__rs1__4_, id_instruction__rs1__3_, id_instruction__rs1__2_, id_instruction__rs1__1_, id_instruction__rs1__0_ } == wb[36:32]; - assign N178 = { id_instruction__rs2__4_, id_instruction__rs2__3_, id_instruction__rs2__2_, id_instruction__rs2__1_, id_instruction__rs2__0_ } == wb[36:32]; - assign N183 = { id_instruction__rs1__4_, id_instruction__rs1__3_, id_instruction__rs1__2_, id_instruction__rs1__1_, id_instruction__rs1__0_ } == { exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_ }; - assign N184 = { id_instruction__rs1__4_, id_instruction__rs1__3_, id_instruction__rs1__2_, id_instruction__rs1__1_, id_instruction__rs1__0_ } == { mem_rd_addr__4_, mem_rd_addr__3_, mem_rd_addr__2_, mem_rd_addr__1_, mem_rd_addr__0_ }; - assign N185 = { id_instruction__rs2__4_, id_instruction__rs2__3_, id_instruction__rs2__2_, id_instruction__rs2__1_, id_instruction__rs2__0_ } == { exe_instruction__rd__4_, exe_instruction__rd__3_, exe_instruction__rd__2_, exe_instruction__rd__1_, exe_instruction__rd__0_ }; - assign N186 = { id_instruction__rs2__4_, id_instruction__rs2__3_, id_instruction__rs2__2_, id_instruction__rs2__1_, id_instruction__rs2__0_ } == { mem_rd_addr__4_, mem_rd_addr__3_, mem_rd_addr__2_, mem_rd_addr__1_, mem_rd_addr__0_ }; - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__31_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__31_ <= id_pc_plus4__31_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__30_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__30_ <= id_pc_plus4__30_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__29_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__29_ <= id_pc_plus4__29_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__28_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__28_ <= id_pc_plus4__28_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__27_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__27_ <= id_pc_plus4__27_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__26_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__26_ <= id_pc_plus4__26_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__25_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__25_ <= id_pc_plus4__25_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__24_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__24_ <= id_pc_plus4__24_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__23_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__23_ <= id_pc_plus4__23_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__22_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__22_ <= id_pc_plus4__22_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__21_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__21_ <= id_pc_plus4__21_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__20_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__20_ <= id_pc_plus4__20_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__19_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__19_ <= id_pc_plus4__19_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__18_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__18_ <= id_pc_plus4__18_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__17_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__17_ <= id_pc_plus4__17_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__16_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__16_ <= id_pc_plus4__16_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__15_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__15_ <= id_pc_plus4__15_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__14_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__14_ <= id_pc_plus4__14_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__13_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__13_ <= id_pc_plus4__13_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__12_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__12_ <= id_pc_plus4__12_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__11_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__11_ <= id_pc_plus4__11_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__10_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__10_ <= id_pc_plus4__10_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__9_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__9_ <= id_pc_plus4__9_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__8_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__8_ <= id_pc_plus4__8_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__7_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__7_ <= id_pc_plus4__7_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__6_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__6_ <= id_pc_plus4__6_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__5_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__5_ <= id_pc_plus4__5_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__4_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__4_ <= id_pc_plus4__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__3_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__3_ <= id_pc_plus4__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__2_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__2_ <= id_pc_plus4__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__1_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__1_ <= id_pc_plus4__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_plus4__0_ <= 1'b0; - end else if(N190) begin - exe_pc_plus4__0_ <= id_pc_plus4__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__11_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__11_ <= id_pc_jump_addr__11_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__10_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__10_ <= id_pc_jump_addr__10_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__9_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__9_ <= id_pc_jump_addr__9_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__8_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__8_ <= id_pc_jump_addr__8_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__7_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__7_ <= id_pc_jump_addr__7_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__6_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__6_ <= id_pc_jump_addr__6_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__5_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__5_ <= id_pc_jump_addr__5_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__4_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__4_ <= id_pc_jump_addr__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__3_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__3_ <= id_pc_jump_addr__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_pc_jump_addr__2_ <= 1'b0; - end else if(N190) begin - exe_pc_jump_addr__2_ <= id_pc_jump_addr__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__6_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__6_ <= id_instruction__funct7__6_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__5_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__5_ <= id_instruction__funct7__5_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__4_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__4_ <= id_instruction__funct7__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__3_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__3_ <= id_instruction__funct7__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__2_ <= id_instruction__funct7__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__1_ <= id_instruction__funct7__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct7__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct7__0_ <= id_instruction__funct7__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs2__4_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs2__4_ <= id_instruction__rs2__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs2__3_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs2__3_ <= id_instruction__rs2__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs2__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs2__2_ <= id_instruction__rs2__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs2__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs2__1_ <= id_instruction__rs2__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs2__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs2__0_ <= id_instruction__rs2__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs1__4_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs1__4_ <= id_instruction__rs1__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs1__3_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs1__3_ <= id_instruction__rs1__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs1__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs1__2_ <= id_instruction__rs1__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs1__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs1__1_ <= id_instruction__rs1__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rs1__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__rs1__0_ <= id_instruction__rs1__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct3__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct3__2_ <= id_instruction__funct3__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct3__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct3__1_ <= id_instruction__funct3__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__funct3__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__funct3__0_ <= id_instruction__funct3__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rd__4_ <= 1'b0; - end else if(N190) begin - exe_instruction__rd__4_ <= id_instruction__rd__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rd__3_ <= 1'b0; - end else if(N190) begin - exe_instruction__rd__3_ <= id_instruction__rd__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rd__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__rd__2_ <= id_instruction__rd__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rd__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__rd__1_ <= id_instruction__rd__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__rd__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__rd__0_ <= id_instruction__rd__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__6_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__6_ <= id_instruction__op__6_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__5_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__5_ <= id_instruction__op__5_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__4_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__4_ <= id_instruction__op__4_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__3_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__3_ <= id_instruction__op__3_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__2_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__2_ <= id_instruction__op__2_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__1_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__1_ <= id_instruction__op__1_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_instruction__op__0_ <= 1'b0; - end else if(N190) begin - exe_instruction__op__0_ <= id_instruction__op__0_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__op_writes_rf_ <= 1'b0; - end else if(N190) begin - exe_decode__op_writes_rf_ <= id_decode__op_writes_rf_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_load_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_load_op_ <= id_decode__is_load_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - to_mem_o[69] <= 1'b0; - end else if(N190) begin - to_mem_o[69] <= id_decode__is_store_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_mem_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_mem_op_ <= id_decode__is_mem_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_byte_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_byte_op_ <= id_decode__is_byte_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_hex_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_hex_op_ <= id_decode__is_hex_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_load_unsigned_ <= 1'b0; - end else if(N190) begin - exe_decode__is_load_unsigned_ <= id_decode__is_load_unsigned_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_branch_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_branch_op_ <= id_decode__is_branch_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_jump_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_jump_op_ <= id_decode__is_jump_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_md_instr_ <= 1'b0; - end else if(N190) begin - exe_decode__is_md_instr_ <= id_decode__is_md_instr_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__is_fence_op_ <= 1'b0; - end else if(N190) begin - exe_decode__is_fence_op_ <= id_decode__is_fence_op_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__op_is_load_reservation_ <= 1'b0; - end else if(N190) begin - exe_decode__op_is_load_reservation_ <= id_decode__op_is_load_reservation_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_decode__op_is_lr_acq_ <= 1'b0; - end else if(N190) begin - exe_decode__op_is_lr_acq_ <= id_decode__op_is_lr_acq_; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__31_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__31_ <= rs1_to_exe[31]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__30_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__30_ <= rs1_to_exe[30]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__29_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__29_ <= rs1_to_exe[29]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__28_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__28_ <= rs1_to_exe[28]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__27_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__27_ <= rs1_to_exe[27]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__26_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__26_ <= rs1_to_exe[26]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__25_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__25_ <= rs1_to_exe[25]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__24_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__24_ <= rs1_to_exe[24]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__23_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__23_ <= rs1_to_exe[23]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__22_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__22_ <= rs1_to_exe[22]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__21_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__21_ <= rs1_to_exe[21]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__20_ <= 1'b0; - end else if(N190) begin - exe_rs1_val__20_ <= rs1_to_exe[20]; - end - end - - - always @(posedge clk) begin - if(N262) begin - exe_rs1_val__19_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__19_ <= rs1_to_exe[19]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__18_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__18_ <= rs1_to_exe[18]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__17_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__17_ <= rs1_to_exe[17]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__16_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__16_ <= rs1_to_exe[16]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__15_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__15_ <= rs1_to_exe[15]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__14_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__14_ <= rs1_to_exe[14]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__13_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__13_ <= rs1_to_exe[13]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__12_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__12_ <= rs1_to_exe[12]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__11_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__11_ <= rs1_to_exe[11]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__10_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__10_ <= rs1_to_exe[10]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__9_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__9_ <= rs1_to_exe[9]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__8_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__8_ <= rs1_to_exe[8]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__7_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__7_ <= rs1_to_exe[7]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__6_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__6_ <= rs1_to_exe[6]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__5_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__5_ <= rs1_to_exe[5]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__4_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__4_ <= rs1_to_exe[4]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__3_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__3_ <= rs1_to_exe[3]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__2_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__2_ <= rs1_to_exe[2]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__1_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__1_ <= rs1_to_exe[1]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_val__0_ <= 1'b0; - end else if(N191) begin - exe_rs1_val__0_ <= rs1_to_exe[0]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__31_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__31_ <= rs2_to_exe[31]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__30_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__30_ <= rs2_to_exe[30]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__29_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__29_ <= rs2_to_exe[29]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__28_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__28_ <= rs2_to_exe[28]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__27_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__27_ <= rs2_to_exe[27]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__26_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__26_ <= rs2_to_exe[26]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__25_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__25_ <= rs2_to_exe[25]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__24_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__24_ <= rs2_to_exe[24]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__23_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__23_ <= rs2_to_exe[23]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__22_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__22_ <= rs2_to_exe[22]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__21_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__21_ <= rs2_to_exe[21]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__20_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__20_ <= rs2_to_exe[20]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__19_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__19_ <= rs2_to_exe[19]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__18_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__18_ <= rs2_to_exe[18]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__17_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__17_ <= rs2_to_exe[17]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__16_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__16_ <= rs2_to_exe[16]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__15_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__15_ <= rs2_to_exe[15]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__14_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__14_ <= rs2_to_exe[14]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__13_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__13_ <= rs2_to_exe[13]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__12_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__12_ <= rs2_to_exe[12]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__11_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__11_ <= rs2_to_exe[11]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__10_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__10_ <= rs2_to_exe[10]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__9_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__9_ <= rs2_to_exe[9]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__8_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__8_ <= rs2_to_exe[8]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__7_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__7_ <= rs2_to_exe[7]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__6_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__6_ <= rs2_to_exe[6]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__5_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__5_ <= rs2_to_exe[5]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__4_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__4_ <= rs2_to_exe[4]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__3_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__3_ <= rs2_to_exe[3]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__2_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__2_ <= rs2_to_exe[2]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__1_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__1_ <= rs2_to_exe[1]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_val__0_ <= 1'b0; - end else if(N191) begin - exe_rs2_val__0_ <= rs2_to_exe[0]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__31_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__31_ <= mem_addr_op2[31]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__30_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__30_ <= mem_addr_op2[30]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__29_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__29_ <= mem_addr_op2[29]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__28_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__28_ <= mem_addr_op2[28]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__27_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__27_ <= mem_addr_op2[27]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__26_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__26_ <= mem_addr_op2[26]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__25_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__25_ <= mem_addr_op2[25]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__24_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__24_ <= mem_addr_op2[24]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__23_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__23_ <= mem_addr_op2[23]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__22_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__22_ <= mem_addr_op2[22]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__21_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__21_ <= mem_addr_op2[21]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__20_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__20_ <= mem_addr_op2[20]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__19_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__19_ <= mem_addr_op2[19]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__18_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__18_ <= mem_addr_op2[18]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__17_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__17_ <= mem_addr_op2[17]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__16_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__16_ <= mem_addr_op2[16]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__15_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__15_ <= mem_addr_op2[15]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__14_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__14_ <= mem_addr_op2[14]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__13_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__13_ <= mem_addr_op2[13]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__12_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__12_ <= mem_addr_op2[12]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__11_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__11_ <= mem_addr_op2[11]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__10_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__10_ <= mem_addr_op2[10]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__9_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__9_ <= mem_addr_op2[9]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__8_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__8_ <= mem_addr_op2[8]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__7_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__7_ <= mem_addr_op2[7]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__6_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__6_ <= mem_addr_op2[6]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__5_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__5_ <= mem_addr_op2[5]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__4_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__4_ <= mem_addr_op2[4]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__3_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__3_ <= mem_addr_op2[3]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__2_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__2_ <= mem_addr_op2[2]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__1_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__1_ <= mem_addr_op2[1]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_mem_addr_op2__0_ <= 1'b0; - end else if(N191) begin - exe_mem_addr_op2__0_ <= mem_addr_op2[0]; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_in_mem_ <= 1'b0; - end else if(N191) begin - exe_rs1_in_mem_ <= exe_rs1_in_mem; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs1_in_wb_ <= 1'b0; - end else if(N191) begin - exe_rs1_in_wb_ <= exe_rs1_in_wb; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_in_mem_ <= 1'b0; - end else if(N191) begin - exe_rs2_in_mem_ <= exe_rs2_in_mem; - end - end - - - always @(posedge clk) begin - if(N263) begin - exe_rs2_in_wb_ <= 1'b0; - end else if(N190) begin - exe_rs2_in_wb_ <= exe_rs2_in_wb; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_rd_addr__4_ <= 1'b0; - end else if(N195) begin - mem_rd_addr__4_ <= exe_instruction__rd__4_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_rd_addr__3_ <= 1'b0; - end else if(N195) begin - mem_rd_addr__3_ <= exe_instruction__rd__3_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_rd_addr__2_ <= 1'b0; - end else if(N195) begin - mem_rd_addr__2_ <= exe_instruction__rd__2_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_rd_addr__1_ <= 1'b0; - end else if(N195) begin - mem_rd_addr__1_ <= exe_instruction__rd__1_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_rd_addr__0_ <= 1'b0; - end else if(N195) begin - mem_rd_addr__0_ <= exe_instruction__rd__0_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__op_writes_rf_ <= 1'b0; - end else if(N195) begin - mem_decode__op_writes_rf_ <= exe_decode__op_writes_rf_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__is_load_op_ <= 1'b0; - end else if(N195) begin - mem_decode__is_load_op_ <= exe_decode__is_load_op_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__is_mem_op_ <= 1'b0; - end else if(N195) begin - mem_decode__is_mem_op_ <= exe_decode__is_mem_op_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__is_byte_op_ <= 1'b0; - end else if(N195) begin - mem_decode__is_byte_op_ <= exe_decode__is_byte_op_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__is_hex_op_ <= 1'b0; - end else if(N195) begin - mem_decode__is_hex_op_ <= exe_decode__is_hex_op_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_decode__is_load_unsigned_ <= 1'b0; - end else if(N195) begin - mem_decode__is_load_unsigned_ <= exe_decode__is_load_unsigned_; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__31_ <= 1'b0; - end else if(N195) begin - mem_alu_result__31_ <= alu_result[31]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__30_ <= 1'b0; - end else if(N195) begin - mem_alu_result__30_ <= alu_result[30]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__29_ <= 1'b0; - end else if(N195) begin - mem_alu_result__29_ <= alu_result[29]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__28_ <= 1'b0; - end else if(N195) begin - mem_alu_result__28_ <= alu_result[28]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__27_ <= 1'b0; - end else if(N195) begin - mem_alu_result__27_ <= alu_result[27]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__26_ <= 1'b0; - end else if(N195) begin - mem_alu_result__26_ <= alu_result[26]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__25_ <= 1'b0; - end else if(N195) begin - mem_alu_result__25_ <= alu_result[25]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__24_ <= 1'b0; - end else if(N195) begin - mem_alu_result__24_ <= alu_result[24]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__23_ <= 1'b0; - end else if(N195) begin - mem_alu_result__23_ <= alu_result[23]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__22_ <= 1'b0; - end else if(N195) begin - mem_alu_result__22_ <= alu_result[22]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__21_ <= 1'b0; - end else if(N195) begin - mem_alu_result__21_ <= alu_result[21]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__20_ <= 1'b0; - end else if(N195) begin - mem_alu_result__20_ <= alu_result[20]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__19_ <= 1'b0; - end else if(N195) begin - mem_alu_result__19_ <= alu_result[19]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__18_ <= 1'b0; - end else if(N195) begin - mem_alu_result__18_ <= alu_result[18]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__17_ <= 1'b0; - end else if(N195) begin - mem_alu_result__17_ <= alu_result[17]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__16_ <= 1'b0; - end else if(N195) begin - mem_alu_result__16_ <= alu_result[16]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__15_ <= 1'b0; - end else if(N195) begin - mem_alu_result__15_ <= alu_result[15]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__14_ <= 1'b0; - end else if(N195) begin - mem_alu_result__14_ <= alu_result[14]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__13_ <= 1'b0; - end else if(N195) begin - mem_alu_result__13_ <= alu_result[13]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__12_ <= 1'b0; - end else if(N195) begin - mem_alu_result__12_ <= alu_result[12]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__11_ <= 1'b0; - end else if(N195) begin - mem_alu_result__11_ <= alu_result[11]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__10_ <= 1'b0; - end else if(N195) begin - mem_alu_result__10_ <= alu_result[10]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__9_ <= 1'b0; - end else if(N195) begin - mem_alu_result__9_ <= alu_result[9]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__8_ <= 1'b0; - end else if(N195) begin - mem_alu_result__8_ <= alu_result[8]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__7_ <= 1'b0; - end else if(N195) begin - mem_alu_result__7_ <= alu_result[7]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__6_ <= 1'b0; - end else if(N195) begin - mem_alu_result__6_ <= alu_result[6]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__5_ <= 1'b0; - end else if(N195) begin - mem_alu_result__5_ <= alu_result[5]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__4_ <= 1'b0; - end else if(N195) begin - mem_alu_result__4_ <= alu_result[4]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__3_ <= 1'b0; - end else if(N195) begin - mem_alu_result__3_ <= alu_result[3]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__2_ <= 1'b0; - end else if(N195) begin - mem_alu_result__2_ <= alu_result[2]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__1_ <= 1'b0; - end else if(N195) begin - mem_alu_result__1_ <= alu_result[1]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_alu_result__0_ <= 1'b0; - end else if(N195) begin - mem_alu_result__0_ <= alu_result[0]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_mem_addr_send__1_ <= 1'b0; - end else if(N195) begin - mem_mem_addr_send__1_ <= to_mem_o[34]; - end - end - - - always @(posedge clk) begin - if(N192) begin - mem_mem_addr_send__0_ <= 1'b0; - end else if(N195) begin - mem_mem_addr_send__0_ <= to_mem_o[33]; - end - end - - - always @(posedge clk) begin - if(N264) begin - load_buffer_data[31] <= 1'b0; - end else if(N199) begin - load_buffer_data[31] <= from_mem_i[32]; - end - end - - - always @(posedge clk) begin - if(N296) begin - load_buffer_data[30] <= 1'b0; - end else if(N199) begin - load_buffer_data[30] <= from_mem_i[31]; - end - end - - - always @(posedge clk) begin - if(N295) begin - load_buffer_data[29] <= 1'b0; - end else if(N199) begin - load_buffer_data[29] <= from_mem_i[30]; - end - end - - - always @(posedge clk) begin - if(N294) begin - load_buffer_data[28] <= 1'b0; - end else if(N199) begin - load_buffer_data[28] <= from_mem_i[29]; - end - end - - - always @(posedge clk) begin - if(N293) begin - load_buffer_data[27] <= 1'b0; - end else if(N199) begin - load_buffer_data[27] <= from_mem_i[28]; - end - end - - - always @(posedge clk) begin - if(N292) begin - load_buffer_data[26] <= 1'b0; - end else if(N199) begin - load_buffer_data[26] <= from_mem_i[27]; - end - end - - - always @(posedge clk) begin - if(N291) begin - load_buffer_data[25] <= 1'b0; - end else if(N199) begin - load_buffer_data[25] <= from_mem_i[26]; - end - end - - - always @(posedge clk) begin - if(N290) begin - load_buffer_data[24] <= 1'b0; - end else if(N199) begin - load_buffer_data[24] <= from_mem_i[25]; - end - end - - - always @(posedge clk) begin - if(N289) begin - load_buffer_data[23] <= 1'b0; - end else if(N199) begin - load_buffer_data[23] <= from_mem_i[24]; - end - end - - - always @(posedge clk) begin - if(N288) begin - load_buffer_data[22] <= 1'b0; - end else if(N199) begin - load_buffer_data[22] <= from_mem_i[23]; - end - end - - - always @(posedge clk) begin - if(N287) begin - load_buffer_data[21] <= 1'b0; - end else if(N199) begin - load_buffer_data[21] <= from_mem_i[22]; - end - end - - - always @(posedge clk) begin - if(N286) begin - load_buffer_data[20] <= 1'b0; - end else if(N199) begin - load_buffer_data[20] <= from_mem_i[21]; - end - end - - - always @(posedge clk) begin - if(N285) begin - load_buffer_data[19] <= 1'b0; - end else if(N199) begin - load_buffer_data[19] <= from_mem_i[20]; - end - end - - - always @(posedge clk) begin - if(N284) begin - load_buffer_data[18] <= 1'b0; - end else if(N199) begin - load_buffer_data[18] <= from_mem_i[19]; - end - end - - - always @(posedge clk) begin - if(N283) begin - load_buffer_data[17] <= 1'b0; - end else if(N199) begin - load_buffer_data[17] <= from_mem_i[18]; - end - end - - - always @(posedge clk) begin - if(N282) begin - load_buffer_data[16] <= 1'b0; - end else if(N199) begin - load_buffer_data[16] <= from_mem_i[17]; - end - end - - - always @(posedge clk) begin - if(N281) begin - load_buffer_data[15] <= 1'b0; - end else if(N199) begin - load_buffer_data[15] <= from_mem_i[16]; - end - end - - - always @(posedge clk) begin - if(N280) begin - load_buffer_data[14] <= 1'b0; - end else if(N199) begin - load_buffer_data[14] <= from_mem_i[15]; - end - end - - - always @(posedge clk) begin - if(N279) begin - load_buffer_data[13] <= 1'b0; - end else if(N199) begin - load_buffer_data[13] <= from_mem_i[14]; - end - end - - - always @(posedge clk) begin - if(N278) begin - load_buffer_data[12] <= 1'b0; - end else if(N199) begin - load_buffer_data[12] <= from_mem_i[13]; - end - end - - - always @(posedge clk) begin - if(N277) begin - load_buffer_data[11] <= 1'b0; - end else if(N199) begin - load_buffer_data[11] <= from_mem_i[12]; - end - end - - - always @(posedge clk) begin - if(N276) begin - load_buffer_data[10] <= 1'b0; - end else if(N199) begin - load_buffer_data[10] <= from_mem_i[11]; - end - end - - - always @(posedge clk) begin - if(N275) begin - load_buffer_data[9] <= 1'b0; - end else if(N199) begin - load_buffer_data[9] <= from_mem_i[10]; - end - end - - - always @(posedge clk) begin - if(N274) begin - load_buffer_data[8] <= 1'b0; - end else if(N199) begin - load_buffer_data[8] <= from_mem_i[9]; - end - end - - - always @(posedge clk) begin - if(N273) begin - load_buffer_data[7] <= 1'b0; - end else if(N199) begin - load_buffer_data[7] <= from_mem_i[8]; - end - end - - - always @(posedge clk) begin - if(N272) begin - load_buffer_data[6] <= 1'b0; - end else if(N199) begin - load_buffer_data[6] <= from_mem_i[7]; - end - end - - - always @(posedge clk) begin - if(N271) begin - load_buffer_data[5] <= 1'b0; - end else if(N199) begin - load_buffer_data[5] <= from_mem_i[6]; - end - end - - - always @(posedge clk) begin - if(N270) begin - load_buffer_data[4] <= 1'b0; - end else if(N199) begin - load_buffer_data[4] <= from_mem_i[5]; - end - end - - - always @(posedge clk) begin - if(N269) begin - load_buffer_data[3] <= 1'b0; - end else if(N199) begin - load_buffer_data[3] <= from_mem_i[4]; - end - end - - - always @(posedge clk) begin - if(N268) begin - load_buffer_data[2] <= 1'b0; - end else if(N199) begin - load_buffer_data[2] <= from_mem_i[3]; - end - end - - - always @(posedge clk) begin - if(N267) begin - load_buffer_data[1] <= 1'b0; - end else if(N199) begin - load_buffer_data[1] <= from_mem_i[2]; - end - end - - - always @(posedge clk) begin - if(N266) begin - load_buffer_data[0] <= 1'b0; - end else if(N199) begin - load_buffer_data[0] <= from_mem_i[1]; - end - end - - - always @(posedge clk) begin - if(N265) begin - is_load_buffer_valid <= 1'b0; - end else if(N199) begin - is_load_buffer_valid <= 1'b1; - end - end - - assign N203 = N201 & N202; - assign N204 = mem_mem_addr_send__1_ | N202; - assign N206 = N201 | mem_mem_addr_send__0_; - assign N208 = mem_mem_addr_send__1_ & mem_mem_addr_send__0_; - - always @(posedge clk) begin - if(N257) begin - wb[37] <= 1'b0; - end else if(N260) begin - wb[37] <= mem_decode__op_writes_rf_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[36] <= 1'b0; - end else if(N260) begin - wb[36] <= mem_rd_addr__4_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[35] <= 1'b0; - end else if(N260) begin - wb[35] <= mem_rd_addr__3_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[34] <= 1'b0; - end else if(N260) begin - wb[34] <= mem_rd_addr__2_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[33] <= 1'b0; - end else if(N260) begin - wb[33] <= mem_rd_addr__1_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[32] <= 1'b0; - end else if(N260) begin - wb[32] <= mem_rd_addr__0_; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[31] <= 1'b0; - end else if(N260) begin - wb[31] <= rf_data[31]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[30] <= 1'b0; - end else if(N260) begin - wb[30] <= rf_data[30]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[29] <= 1'b0; - end else if(N260) begin - wb[29] <= rf_data[29]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[28] <= 1'b0; - end else if(N260) begin - wb[28] <= rf_data[28]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[27] <= 1'b0; - end else if(N260) begin - wb[27] <= rf_data[27]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[26] <= 1'b0; - end else if(N260) begin - wb[26] <= rf_data[26]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[25] <= 1'b0; - end else if(N260) begin - wb[25] <= rf_data[25]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[24] <= 1'b0; - end else if(N260) begin - wb[24] <= rf_data[24]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[23] <= 1'b0; - end else if(N260) begin - wb[23] <= rf_data[23]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[22] <= 1'b0; - end else if(N260) begin - wb[22] <= rf_data[22]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[21] <= 1'b0; - end else if(N260) begin - wb[21] <= rf_data[21]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[20] <= 1'b0; - end else if(N260) begin - wb[20] <= rf_data[20]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[19] <= 1'b0; - end else if(N260) begin - wb[19] <= rf_data[19]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[18] <= 1'b0; - end else if(N260) begin - wb[18] <= rf_data[18]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[17] <= 1'b0; - end else if(N260) begin - wb[17] <= rf_data[17]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[16] <= 1'b0; - end else if(N260) begin - wb[16] <= rf_data[16]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[15] <= 1'b0; - end else if(N260) begin - wb[15] <= rf_data[15]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[14] <= 1'b0; - end else if(N260) begin - wb[14] <= rf_data[14]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[13] <= 1'b0; - end else if(N260) begin - wb[13] <= rf_data[13]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[12] <= 1'b0; - end else if(N260) begin - wb[12] <= rf_data[12]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[11] <= 1'b0; - end else if(N260) begin - wb[11] <= rf_data[11]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[10] <= 1'b0; - end else if(N260) begin - wb[10] <= rf_data[10]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[9] <= 1'b0; - end else if(N260) begin - wb[9] <= rf_data[9]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[8] <= 1'b0; - end else if(N260) begin - wb[8] <= rf_data[8]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[7] <= 1'b0; - end else if(N260) begin - wb[7] <= rf_data[7]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[6] <= 1'b0; - end else if(N260) begin - wb[6] <= rf_data[6]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[5] <= 1'b0; - end else if(N260) begin - wb[5] <= rf_data[5]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[4] <= 1'b0; - end else if(N260) begin - wb[4] <= rf_data[4]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[3] <= 1'b0; - end else if(N260) begin - wb[3] <= rf_data[3]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[2] <= 1'b0; - end else if(N260) begin - wb[2] <= rf_data[2]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[1] <= 1'b0; - end else if(N260) begin - wb[1] <= rf_data[1]; - end - end - - - always @(posedge clk) begin - if(N257) begin - wb[0] <= 1'b0; - end else if(N260) begin - wb[0] <= rf_data[0]; - end - end - - assign N261 = N175 | n_cse_43; - assign N262 = N187 | N188; - assign N263 = N187 | N188; - assign N264 = reset | N197; - assign N265 = reset | N197; - assign N266 = reset | N197; - assign N267 = reset | N197; - assign N268 = reset | N197; - assign N269 = reset | N197; - assign N270 = reset | N197; - assign N271 = reset | N197; - assign N272 = reset | N197; - assign N273 = reset | N197; - assign N274 = reset | N197; - assign N275 = reset | N197; - assign N276 = reset | N197; - assign N277 = reset | N197; - assign N278 = reset | N197; - assign N279 = reset | N197; - assign N280 = reset | N197; - assign N281 = reset | N197; - assign N282 = reset | N197; - assign N283 = reset | N197; - assign N284 = reset | N197; - assign N285 = reset | N197; - assign N286 = reset | N197; - assign N287 = reset | N197; - assign N288 = reset | N197; - assign N289 = reset | N197; - assign N290 = reset | N197; - assign N291 = reset | N197; - assign N292 = reset | N197; - assign N293 = reset | N197; - assign N294 = reset | N197; - assign N295 = reset | N197; - assign N296 = reset | N197; - assign N297 = ~state_r[0]; - assign N298 = N297 | state_r[1]; - assign N299 = ~instruction_op__6_; - assign N300 = ~instruction_op__5_; - assign N301 = ~instruction_op__3_; - assign N302 = ~instruction_op__2_; - assign N303 = ~instruction_op__1_; - assign N304 = ~instruction_op__0_; - assign N305 = N300 | N299; - assign N306 = instruction_op__4_ | N305; - assign N307 = N301 | N306; - assign N308 = N302 | N307; - assign N309 = N303 | N308; - assign N310 = N304 | N309; - assign N311 = ~N310; - assign N312 = ~net_packet_r_header__net_op__0_; - assign N313 = N312 | net_packet_r_header__net_op__1_; - assign N314 = ~N313; - assign N315 = ~net_packet_r_header__net_op__1_; - assign N316 = net_packet_r_header__net_op__0_ | N315; - assign N317 = ~N316; - assign N318 = state_r[0] | state_r[1]; - assign N319 = ~N318; - assign N320 = net_packet_r_header__net_op__0_ & net_packet_r_header__net_op__1_; - assign N321 = net_packet_r_header__ring_ID__3_ | net_packet_r_header__ring_ID__4_; - assign N322 = net_packet_r_header__ring_ID__2_ | N321; - assign N323 = net_packet_r_header__ring_ID__1_ | N322; - assign N324 = net_packet_r_header__ring_ID__0_ | N323; - assign N325 = ~N324; - assign to_mem_o[64:33] = rs1_to_alu + { exe_mem_addr_op2__31_, exe_mem_addr_op2__30_, exe_mem_addr_op2__29_, exe_mem_addr_op2__28_, exe_mem_addr_op2__27_, exe_mem_addr_op2__26_, exe_mem_addr_op2__25_, exe_mem_addr_op2__24_, exe_mem_addr_op2__23_, exe_mem_addr_op2__22_, exe_mem_addr_op2__21_, exe_mem_addr_op2__20_, exe_mem_addr_op2__19_, exe_mem_addr_op2__18_, exe_mem_addr_op2__17_, exe_mem_addr_op2__16_, exe_mem_addr_op2__15_, exe_mem_addr_op2__14_, exe_mem_addr_op2__13_, exe_mem_addr_op2__12_, exe_mem_addr_op2__11_, exe_mem_addr_op2__10_, exe_mem_addr_op2__9_, exe_mem_addr_op2__8_, exe_mem_addr_op2__7_, exe_mem_addr_op2__6_, exe_mem_addr_op2__5_, exe_mem_addr_op2__4_, exe_mem_addr_op2__3_, exe_mem_addr_op2__2_, exe_mem_addr_op2__1_, exe_mem_addr_op2__0_ }; - assign pc_plus4 = pc_r + 1'b1; - assign inject_pc_value = $signed({ net_packet_r_header__addr__11_, net_packet_r_header__addr__10_, net_packet_r_header__addr__9_, net_packet_r_header__addr__8_, net_packet_r_header__addr__7_, net_packet_r_header__addr__6_, net_packet_r_header__addr__5_, net_packet_r_header__addr__4_, net_packet_r_header__addr__3_, net_packet_r_header__addr__2_ }) + $signed({ inject_pc_rel_9, BImm_sign_ext[10:5], inject_pc_rel }); - assign to_mem_o[32:1] = (N0)? { N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47 } : - (N121)? { N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84 } : - (N46)? rs2_to_alu : 1'b0; - assign N0 = exe_decode__is_byte_op_; - assign to_mem_o[68:65] = (N0)? { N82, N81, N80, N79 } : - (N121)? { N119, N118, N117, N116 } : - (N46)? { 1'b1, 1'b1, 1'b1, 1'b1 } : 1'b0; - assign mem_addr_op2 = (N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N125)? { id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__5_, id_instruction__funct7__4_, id_instruction__funct7__3_, id_instruction__funct7__2_, id_instruction__funct7__1_, id_instruction__funct7__0_, id_instruction__rd__4_, id_instruction__rd__3_, id_instruction__rd__2_, id_instruction__rd__1_, id_instruction__rd__0_ } : - (N123)? { id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__6_, id_instruction__funct7__5_, id_instruction__funct7__4_, id_instruction__funct7__3_, id_instruction__funct7__2_, id_instruction__funct7__1_, id_instruction__funct7__0_, id_instruction__rs2__4_, id_instruction__rs2__3_, id_instruction__rs2__2_, id_instruction__rs2__1_, id_instruction__rs2__0_ } : 1'b0; - assign N1 = id_decode__op_is_load_reservation_; - assign pc_jump_addr = (N2)? BImm_extract[3:0] : - (N127)? JImm_extract : 1'b0; - assign N2 = decode_is_branch_op_; - assign jalr_prediction_n = (N3)? { exe_pc_plus4__31_, exe_pc_plus4__30_, exe_pc_plus4__29_, exe_pc_plus4__28_, exe_pc_plus4__27_, exe_pc_plus4__26_, exe_pc_plus4__25_, exe_pc_plus4__24_, exe_pc_plus4__23_, exe_pc_plus4__22_, exe_pc_plus4__21_, exe_pc_plus4__20_, exe_pc_plus4__19_, exe_pc_plus4__18_, exe_pc_plus4__17_, exe_pc_plus4__16_, exe_pc_plus4__15_, exe_pc_plus4__14_, exe_pc_plus4__13_, exe_pc_plus4__12_, exe_pc_plus4__11_, exe_pc_plus4__10_, exe_pc_plus4__9_, exe_pc_plus4__8_, exe_pc_plus4__7_, exe_pc_plus4__6_, exe_pc_plus4__5_, exe_pc_plus4__4_, exe_pc_plus4__3_, exe_pc_plus4__2_, exe_pc_plus4__1_, exe_pc_plus4__0_ } : - (N128)? jalr_prediction_r : 1'b0; - assign N3 = exe_decode__is_jump_op_; - assign { N146, N145, N144, N143, N142, N141, N140, N139, N138, N137 } = (N4)? { exe_pc_jump_addr__11_, exe_pc_jump_addr__10_, exe_pc_jump_addr__9_, exe_pc_jump_addr__8_, exe_pc_jump_addr__7_, exe_pc_jump_addr__6_, exe_pc_jump_addr__5_, exe_pc_jump_addr__4_, exe_pc_jump_addr__3_, exe_pc_jump_addr__2_ } : - (N5)? { exe_pc_plus4__11_, exe_pc_plus4__10_, exe_pc_plus4__9_, exe_pc_plus4__8_, exe_pc_plus4__7_, exe_pc_plus4__6_, exe_pc_plus4__5_, exe_pc_plus4__4_, exe_pc_plus4__3_, exe_pc_plus4__2_ } : 1'b0; - assign N4 = branch_under_predict; - assign N5 = N136; - assign { N156, N155, N154, N153, N152, N151, N150, N149, N148, N147 } = (N6)? { N146, N145, N144, N143, N142, N141, N140, N139, N138, N137 } : - (N158)? jalr_addr : - (N161)? { BImm_extract[9:4], pc_jump_addr } : - (N164)? jalr_prediction_n[9:0] : - (N135)? pc_plus4 : 1'b0; - assign N6 = branch_mispredict; - assign pc_n = (N7)? { net_packet_r_header__addr__11_, net_packet_r_header__addr__10_, net_packet_r_header__addr__9_, net_packet_r_header__addr__8_, net_packet_r_header__addr__7_, net_packet_r_header__addr__6_, net_packet_r_header__addr__5_, net_packet_r_header__addr__4_, net_packet_r_header__addr__3_, net_packet_r_header__addr__2_ } : - (N8)? { N156, N155, N154, N153, N152, N151, N150, N149, N148, N147 } : 1'b0; - assign N7 = N130; - assign N8 = N129; - assign imem_addr = (N9)? { net_packet_r_header__addr__11_, net_packet_r_header__addr__10_, net_packet_r_header__addr__9_, net_packet_r_header__addr__8_, net_packet_r_header__addr__7_, net_packet_r_header__addr__6_, net_packet_r_header__addr__5_, net_packet_r_header__addr__4_, net_packet_r_header__addr__3_, net_packet_r_header__addr__2_ } : - (N10)? pc_n : 1'b0; - assign N9 = N166; - assign N10 = N165; - assign { inject_pc_rel_9, inject_pc_rel } = (N11)? { BImm_sign_ext[11:11], BImm_sign_ext[4:2] } : - (N12)? { JImm_sign_ext[11:11], JImm_sign_ext_4, JImm_sign_ext_3, JImm_sign_ext_2 } : 1'b0; - assign N11 = write_branch_instr; - assign N12 = N167; - assign { imem_w_data, imem_w_data_0 } = (N11)? { 1'b0, inject_pc_value[9:4], JImm_sign_ext_4, JImm_sign_ext_3, JImm_sign_ext_2, JImm_sign_ext_1, JImm_sign_ext[11:11], JImm_sign_ext[19:12], inject_pc_value[3:0], 1'b0, BImm_sign_ext_31 } : - (N171)? { 1'b0, inject_pc_value, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, BImm_sign_ext[4:1], BImm_sign_ext[11:11], instr_cast_op__0_ } : - (N169)? { BImm_sign_ext_31, BImm_sign_ext[10:5], JImm_sign_ext_4, JImm_sign_ext_3, JImm_sign_ext_2, JImm_sign_ext_1, JImm_sign_ext[11:11], JImm_sign_ext[19:12], BImm_sign_ext[4:1], BImm_sign_ext[11:11], instr_cast_op__0_ } : 1'b0; - assign { BImm_extract[11:11], BImm_extract[9:4], JImm_extract, JImm_extract_10, instruction_rs1__4_, instruction_rs1__3_, instruction_rs1__2_, instruction_rs1__1_, instruction_rs1__0_, instruction_funct3__2_, instruction_funct3__1_, JImm_extract_11, BImm_extract[3:0], BImm_extract[10:10], instruction_op__6_, instruction_op__5_, instruction_op__4_, instruction_op__3_, instruction_op__2_, instruction_op__1_, instruction_op__0_ } = (N13)? imem_out : - (N14)? instruction_r : 1'b0; - assign N13 = pc_wen_r; - assign N14 = N172; - assign rf_wa = (N15)? { net_packet_r_header__addr__4_, net_packet_r_header__addr__3_, net_packet_r_header__addr__2_, net_packet_r_header__addr__1_, net_packet_r_header__addr__0_ } : - (N16)? wb[36:32] : 1'b0; - assign N15 = net_reg_write_cmd; - assign N16 = N173; - assign rf_wd = (N15)? { BImm_sign_ext_31, BImm_sign_ext[10:5], JImm_sign_ext_4, JImm_sign_ext_3, JImm_sign_ext_2, JImm_sign_ext_1, JImm_sign_ext[11:11], JImm_sign_ext[19:12], BImm_sign_ext[4:1], BImm_sign_ext[11:11], instr_cast_op__6_, instr_cast_op__5_, instr_cast_op__4_, instr_cast_op__3_, instr_cast_op__2_, instr_cast_op__1_, instr_cast_op__0_ } : - (N16)? wb[31:0] : 1'b0; - assign alu_result = (N17)? md_result : - (N174)? basic_comp_result : 1'b0; - assign N17 = exe_decode__is_md_instr_; - assign N176 = (N18)? 1'b1 : - (N19)? 1'b0 : 1'b0; - assign N18 = n_cse_43; - assign N19 = N395; - assign rf_rs1_index0_fix = (N20)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N21)? rf_rs1_val : 1'b0; - assign N20 = N179; - assign N21 = N413; - assign rf_rs2_index0_fix = (N22)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N23)? rf_rs2_val : 1'b0; - assign N22 = N180; - assign N23 = N417; - assign rs1_to_exe = (N24)? wb[31:0] : - (N25)? rf_rs1_index0_fix : 1'b0; - assign N24 = id_wb_rs1_forward; - assign N25 = N181; - assign rs2_to_exe = (N26)? wb[31:0] : - (N27)? rf_rs2_index0_fix : 1'b0; - assign N26 = id_wb_rs2_forward; - assign N27 = N182; - assign { N191, N190 } = (N28)? { 1'b1, 1'b1 } : - (N189)? { 1'b0, 1'b0 } : 1'b0; - assign N28 = n_cse_62; - assign N195 = (N29)? 1'b1 : - (N194)? 1'b0 : 1'b0; - assign N29 = N193; - assign N199 = (N30)? 1'b1 : - (N198)? 1'b0 : 1'b0; - assign N30 = N196; - assign loaded_data = (N31)? load_buffer_data : - (N32)? from_mem_i[32:1] : 1'b0; - assign N31 = is_load_buffer_valid; - assign N32 = N200; - assign loaded_byte = (N33)? loaded_data[7:0] : - (N34)? loaded_data[15:8] : - (N35)? loaded_data[23:16] : - (N36)? loaded_data[31:24] : 1'b0; - assign N33 = N203; - assign N34 = N205; - assign N35 = N207; - assign N36 = N208; - assign loaded_hex = (N37)? loaded_data[31:16] : - (N210)? loaded_data[15:0] : 1'b0; - assign N37 = N209; - assign { N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214 } = (N38)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N213)? { loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7], loaded_byte[7:7] } : 1'b0; - assign N38 = mem_decode__is_load_unsigned_; - assign { N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238 } = (N38)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : - (N213)? { loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15], loaded_hex[15:15] } : 1'b0; - assign mem_loaded_data = (N39)? { N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, loaded_byte } : - (N255)? { N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, loaded_hex } : - (N212)? loaded_data : 1'b0; - assign N39 = mem_decode__is_byte_op_; - assign rf_data = (N40)? mem_loaded_data : - (N256)? { mem_alu_result__31_, mem_alu_result__30_, mem_alu_result__29_, mem_alu_result__28_, mem_alu_result__27_, mem_alu_result__26_, mem_alu_result__25_, mem_alu_result__24_, mem_alu_result__23_, mem_alu_result__22_, mem_alu_result__21_, mem_alu_result__20_, mem_alu_result__19_, mem_alu_result__18_, mem_alu_result__17_, mem_alu_result__16_, mem_alu_result__15_, mem_alu_result__14_, mem_alu_result__13_, mem_alu_result__12_, mem_alu_result__11_, mem_alu_result__10_, mem_alu_result__9_, mem_alu_result__8_, mem_alu_result__7_, mem_alu_result__6_, mem_alu_result__5_, mem_alu_result__4_, mem_alu_result__3_, mem_alu_result__2_, mem_alu_result__1_, mem_alu_result__0_ } : 1'b0; - assign N40 = mem_decode__is_load_op_; - assign N260 = (N41)? 1'b1 : - (N259)? 1'b0 : 1'b0; - assign N41 = N258; - assign N42 = 1'b0; - assign net_id_match_valid = N327 & net_packet_r_valid_; - assign N327 = N325 & N326; - assign N326 = ~net_packet_r_header__external_; - assign exec_net_packet = N329 | N333; - assign N329 = net_id_match_valid & N328; - assign N328 = ~net_packet_r_header__bc_; - assign N333 = N332 & N326; - assign N332 = N331 & net_packet_r_valid_; - assign N331 = N330 & net_packet_r_header__bc_; - assign N330 = ~net_id_match_valid; - assign net_pc_write_cmd = exec_net_packet & N320; - assign net_imem_write_cmd = exec_net_packet & N314; - assign net_reg_write_cmd = exec_net_packet & N317; - assign net_pc_write_cmd_idle = net_pc_write_cmd & N319; - assign data_mem_valid = is_load_buffer_valid | from_mem_i[33]; - assign stall_non_mem = N337 | stall_md; - assign N337 = N336 | N298; - assign N336 = N335 | net_reg_write_cmd; - assign N335 = net_imem_write_cmd | N334; - assign N334 = net_reg_write_cmd & wb[37]; - assign stall_fence = exe_decode__is_fence_op_ & outstanding_stores_i; - assign stall_mem = N343 | stall_lrw; - assign N343 = N342 | stall_fence; - assign N342 = N339 | N341; - assign N339 = exe_decode__is_mem_op_ & N338; - assign N338 = ~from_mem_i[0]; - assign N341 = mem_decode__is_load_op_ & N340; - assign N340 = ~data_mem_valid; - assign stall = stall_non_mem | stall_mem; - assign id_exe_rs1_match = id_decode__op_reads_rf1_ & N43; - assign id_exe_rs2_match = id_decode__op_reads_rf2_ & N44; - assign depend_stall = N345 & exe_decode__op_writes_rf_; - assign N345 = N344 & exe_decode__is_load_op_; - assign N344 = id_exe_rs1_match | id_exe_rs2_match; - assign N45 = exe_decode__is_hex_op_ | exe_decode__is_byte_op_; - assign N46 = ~N45; - assign N83 = N121; - assign N120 = ~exe_decode__is_byte_op_; - assign N121 = exe_decode__is_hex_op_ & N120; - assign N122 = id_decode__is_store_op_ | id_decode__op_is_load_reservation_; - assign N123 = ~N122; - assign N124 = ~id_decode__op_is_load_reservation_; - assign N125 = id_decode__is_store_op_ & N124; - assign branch_under_predict = N346 & jump_now; - assign N346 = ~exe_instruction__op__0_; - assign branch_over_predict = exe_instruction__op__0_ & N347; - assign N347 = ~jump_now; - assign branch_mispredict = exe_decode__is_branch_op_ & N348; - assign N348 = branch_under_predict | branch_over_predict; - assign jalr_mispredict = N360 & N126; - assign N360 = ~N359; - assign N359 = N357 | N358; - assign N357 = N355 | N356; - assign N355 = N353 | N354; - assign N353 = N352 | exe_instruction__op__3_; - assign N352 = N351 | exe_instruction__op__4_; - assign N351 = N349 | N350; - assign N349 = ~exe_instruction__op__6_; - assign N350 = ~exe_instruction__op__5_; - assign N354 = ~exe_instruction__op__2_; - assign N356 = ~exe_instruction__op__1_; - assign N358 = ~exe_instruction__op__0_; - assign flush = branch_mispredict | jalr_mispredict; - assign pc_wen = net_pc_write_cmd_idle | N362; - assign N362 = ~N361; - assign N361 = stall | depend_stall; - assign N127 = ~decode_is_branch_op_; - assign N128 = ~exe_decode__is_jump_op_; - assign N129 = ~net_pc_write_cmd_idle; - assign N130 = net_pc_write_cmd_idle; - assign N131 = N363 | N311; - assign N363 = decode_is_branch_op_ & instruction_op__0_; - assign N132 = jalr_mispredict | branch_mispredict; - assign N133 = N131 | N132; - assign N134 = decode_is_jump_op_ | N133; - assign N135 = ~N134; - assign N136 = ~branch_under_predict; - assign N157 = ~branch_mispredict; - assign N158 = jalr_mispredict & N157; - assign N159 = ~jalr_mispredict; - assign N160 = N157 & N159; - assign N161 = N131 & N160; - assign N162 = ~N131; - assign N163 = N160 & N162; - assign N164 = decode_is_jump_op_ & N163; - assign N165 = ~net_imem_write_cmd; - assign N166 = net_imem_write_cmd; - assign imem_cen = N365 | N366; - assign N365 = ~N364; - assign N364 = stall | depend_stall; - assign N366 = net_imem_write_cmd | net_pc_write_cmd_idle; - assign write_branch_instr = ~N374; - assign N374 = N372 | N373; - assign N372 = N371 | instr_cast_op__2_; - assign N371 = N370 | instr_cast_op__3_; - assign N370 = N369 | instr_cast_op__4_; - assign N369 = N367 | N368; - assign N367 = ~instr_cast_op__6_; - assign N368 = ~instr_cast_op__5_; - assign N373 = ~instr_cast_op__1_; - assign write_jal_instr = ~N386; - assign N386 = N384 | N385; - assign N384 = N382 | N383; - assign N382 = N380 | N381; - assign N380 = N378 | N379; - assign N378 = N377 | instr_cast_op__4_; - assign N377 = N375 | N376; - assign N375 = ~instr_cast_op__6_; - assign N376 = ~instr_cast_op__5_; - assign N379 = ~instr_cast_op__3_; - assign N381 = ~instr_cast_op__2_; - assign N383 = ~instr_cast_op__1_; - assign N385 = ~instr_cast_op__0_; - assign N167 = ~write_branch_instr; - assign N168 = write_jal_instr | write_branch_instr; - assign N169 = ~N168; - assign N170 = ~write_branch_instr; - assign N171 = write_jal_instr & N170; - assign N172 = ~pc_wen_r; - assign rf_wen = net_reg_write_cmd | N388; - assign N388 = wb[37] & N387; - assign N387 = ~stall; - assign N173 = ~net_reg_write_cmd; - assign rf_cen = ~N389; - assign N389 = stall | depend_stall; - assign md_valid = exe_decode__is_md_instr_ & md_ready; - assign stall_md = exe_decode__is_md_instr_ & N390; - assign N390 = ~md_resp_valid; - assign n_3_net_ = ~stall_non_mem; - assign rs1_is_forward = exe_rs1_in_mem_ | exe_rs1_in_wb_; - assign rs2_is_forward = exe_rs2_in_mem_ | exe_rs2_in_wb_; - assign N174 = ~exe_decode__is_md_instr_; - assign to_mem_o[70] = N392 & N393; - assign N392 = exe_decode__is_mem_op_ & N391; - assign N391 = ~stall_non_mem; - assign N393 = ~stall_lrw; - assign to_mem_o[0] = mem_decode__is_mem_op_ & from_mem_i[33]; - assign stall_lrw = exe_decode__op_is_lr_acq_ & reservation_i; - assign reserve_1_o = exe_decode__op_is_load_reservation_ & N394; - assign N394 = ~exe_decode__op_is_lr_acq_; - assign n_cse_43 = ~N395; - assign N395 = stall | depend_stall; - assign N175 = N396 | N397; - assign N396 = reset | net_pc_write_cmd_idle; - assign N397 = flush & n_cse_43; - assign id_wb_rs1_forward = N399 & N403; - assign N399 = N398 & wb[37]; - assign N398 = id_decode__op_reads_rf1_ & N177; - assign N403 = N402 | id_instruction__rs1__0_; - assign N402 = N401 | id_instruction__rs1__1_; - assign N401 = N400 | id_instruction__rs1__2_; - assign N400 = id_instruction__rs1__4_ | id_instruction__rs1__3_; - assign id_wb_rs2_forward = N405 & N409; - assign N405 = N404 & wb[37]; - assign N404 = id_decode__op_reads_rf2_ & N178; - assign N409 = N408 | id_instruction__rs2__0_; - assign N408 = N407 | id_instruction__rs2__1_; - assign N407 = N406 | id_instruction__rs2__2_; - assign N406 = id_instruction__rs2__4_ | id_instruction__rs2__3_; - assign N179 = ~N413; - assign N413 = N412 | id_instruction__rs1__0_; - assign N412 = N411 | id_instruction__rs1__1_; - assign N411 = N410 | id_instruction__rs1__2_; - assign N410 = id_instruction__rs1__4_ | id_instruction__rs1__3_; - assign N180 = ~N417; - assign N417 = N416 | id_instruction__rs2__0_; - assign N416 = N415 | id_instruction__rs2__1_; - assign N415 = N414 | id_instruction__rs2__2_; - assign N414 = id_instruction__rs2__4_ | id_instruction__rs2__3_; - assign N181 = ~id_wb_rs1_forward; - assign N182 = ~id_wb_rs2_forward; - assign exe_rs1_in_mem = N418 & N422; - assign N418 = exe_decode__op_writes_rf_ & N183; - assign N422 = N421 | id_instruction__rs1__0_; - assign N421 = N420 | id_instruction__rs1__1_; - assign N420 = N419 | id_instruction__rs1__2_; - assign N419 = id_instruction__rs1__4_ | id_instruction__rs1__3_; - assign exe_rs1_in_wb = N423 & N427; - assign N423 = mem_decode__op_writes_rf_ & N184; - assign N427 = N426 | id_instruction__rs1__0_; - assign N426 = N425 | id_instruction__rs1__1_; - assign N425 = N424 | id_instruction__rs1__2_; - assign N424 = id_instruction__rs1__4_ | id_instruction__rs1__3_; - assign exe_rs2_in_mem = N428 & N432; - assign N428 = exe_decode__op_writes_rf_ & N185; - assign N432 = N431 | id_instruction__rs2__0_; - assign N431 = N430 | id_instruction__rs2__1_; - assign N430 = N429 | id_instruction__rs2__2_; - assign N429 = id_instruction__rs2__4_ | id_instruction__rs2__3_; - assign exe_rs2_in_wb = N433 & N437; - assign N433 = mem_decode__op_writes_rf_ & N186; - assign N437 = N436 | id_instruction__rs2__0_; - assign N436 = N435 | id_instruction__rs2__1_; - assign N435 = N434 | id_instruction__rs2__2_; - assign N434 = id_instruction__rs2__4_ | id_instruction__rs2__3_; - assign n_cse_62 = ~stall; - assign N187 = N438 | N441; - assign N438 = reset | net_pc_write_cmd_idle; - assign N441 = flush & N440; - assign N440 = ~N439; - assign N439 = stall | depend_stall; - assign N188 = depend_stall & n_cse_62; - assign N189 = ~n_cse_62; - assign N192 = reset | net_pc_write_cmd_idle; - assign N193 = ~stall; - assign N194 = ~N193; - assign N196 = N442 & from_mem_i[33]; - assign N442 = stall & mem_decode__is_load_op_; - assign N197 = ~stall; - assign N198 = ~N196; - assign N200 = ~is_load_buffer_valid; - assign N201 = ~mem_mem_addr_send__1_; - assign N202 = ~mem_mem_addr_send__0_; - assign N205 = ~N204; - assign N207 = ~N206; - assign N209 = mem_mem_addr_send__1_ | mem_mem_addr_send__0_; - assign N210 = ~N209; - assign N211 = mem_decode__is_hex_op_ | mem_decode__is_byte_op_; - assign N212 = ~N211; - assign N213 = ~mem_decode__is_load_unsigned_; - assign N254 = ~mem_decode__is_byte_op_; - assign N255 = mem_decode__is_hex_op_ & N254; - assign N256 = ~mem_decode__is_load_op_; - assign N257 = reset | net_pc_write_cmd_idle; - assign N258 = ~stall; - assign N259 = ~N258; - -endmodule - - - -module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 -( - clk_i, - v_i, - addr_i, - data_i, - mask_i, - we_i, - my_x_i, - my_y_i, - v_o, - data_o -); - - input [31:0] addr_i; - input [31:0] data_i; - input [3:0] mask_i; - input [3:0] my_x_i; - input [4:0] my_y_i; - output [75:0] data_o; - input clk_i; - input v_i; - input we_i; - output v_o; - wire [75:0] data_o; - wire v_o,N0; - assign data_o[75] = 1'b0; - assign data_o[74] = addr_i[20]; - assign data_o[73] = addr_i[19]; - assign data_o[72] = addr_i[18]; - assign data_o[71] = addr_i[17]; - assign data_o[70] = addr_i[16]; - assign data_o[69] = addr_i[15]; - assign data_o[68] = addr_i[14]; - assign data_o[67] = addr_i[13]; - assign data_o[66] = addr_i[12]; - assign data_o[65] = addr_i[11]; - assign data_o[64] = addr_i[10]; - assign data_o[63] = addr_i[9]; - assign data_o[62] = addr_i[8]; - assign data_o[61] = addr_i[7]; - assign data_o[60] = addr_i[6]; - assign data_o[59] = addr_i[5]; - assign data_o[58] = addr_i[4]; - assign data_o[57] = addr_i[3]; - assign data_o[56] = addr_i[2]; - assign data_o[8] = addr_i[30]; - assign data_o[7] = addr_i[29]; - assign data_o[6] = addr_i[28]; - assign data_o[5] = addr_i[27]; - assign data_o[4] = addr_i[26]; - assign data_o[3] = addr_i[25]; - assign data_o[2] = addr_i[24]; - assign data_o[1] = addr_i[23]; - assign data_o[0] = addr_i[22]; - assign data_o[53] = mask_i[3]; - assign data_o[52] = mask_i[2]; - assign data_o[51] = mask_i[1]; - assign data_o[50] = mask_i[0]; - assign data_o[49] = data_i[31]; - assign data_o[48] = data_i[30]; - assign data_o[47] = data_i[29]; - assign data_o[46] = data_i[28]; - assign data_o[45] = data_i[27]; - assign data_o[44] = data_i[26]; - assign data_o[43] = data_i[25]; - assign data_o[42] = data_i[24]; - assign data_o[41] = data_i[23]; - assign data_o[40] = data_i[22]; - assign data_o[39] = data_i[21]; - assign data_o[38] = data_i[20]; - assign data_o[37] = data_i[19]; - assign data_o[36] = data_i[18]; - assign data_o[35] = data_i[17]; - assign data_o[34] = data_i[16]; - assign data_o[33] = data_i[15]; - assign data_o[32] = data_i[14]; - assign data_o[31] = data_i[13]; - assign data_o[30] = data_i[12]; - assign data_o[29] = data_i[11]; - assign data_o[28] = data_i[10]; - assign data_o[27] = data_i[9]; - assign data_o[26] = data_i[8]; - assign data_o[25] = data_i[7]; - assign data_o[24] = data_i[6]; - assign data_o[23] = data_i[5]; - assign data_o[22] = data_i[4]; - assign data_o[21] = data_i[3]; - assign data_o[20] = data_i[2]; - assign data_o[19] = data_i[1]; - assign data_o[18] = data_i[0]; - assign data_o[17] = my_y_i[4]; - assign data_o[16] = my_y_i[3]; - assign data_o[15] = my_y_i[2]; - assign data_o[14] = my_y_i[1]; - assign data_o[13] = my_y_i[0]; - assign data_o[12] = my_x_i[3]; - assign data_o[11] = my_x_i[2]; - assign data_o[10] = my_x_i[1]; - assign data_o[9] = my_x_i[0]; - assign data_o[54] = ~data_o[55]; - assign data_o[55] = addr_i[21]; - assign v_o = N0 & v_i; - assign N0 = addr_i[31] & we_i; - -endmodule - - - -module bsg_transpose_width_p1_els_p2 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - assign o[1] = i[1]; - assign o[0] = i[0]; - -endmodule - - - -module bsg_scan_2_1_0 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - assign o[1] = i[1] | 1'b0; - assign o[0] = i[0] | i[1]; - -endmodule - - - -module bsg_priority_encode_one_hot_out_2_0 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - wire N0; - wire [0:0] scan_lo; - - bsg_scan_2_1_0 - scan - ( - .i(i), - .o({ o[1:1], scan_lo[0:0] }) - ); - - assign o[0] = scan_lo[0] & N0; - assign N0 = ~o[1]; - -endmodule - - - -module bsg_arb_fixed_2_0 -( - ready_i, - reqs_i, - grants_o -); - - input [1:0] reqs_i; - output [1:0] grants_o; - input ready_i; - wire [1:0] grants_o,grants_unmasked_lo; - - bsg_priority_encode_one_hot_out_2_0 - enc - ( - .i(reqs_i), - .o(grants_unmasked_lo) - ); - - assign grants_o[1] = grants_unmasked_lo[1] & ready_i; - assign grants_o[0] = grants_unmasked_lo[0] & ready_i; - -endmodule - - - -module bsg_scan_2_1_1 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - assign o[0] = i[0] | 1'b0; - assign o[1] = i[1] | i[0]; - -endmodule - - - -module bsg_priority_encode_one_hot_out_2_1 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - wire N0; - wire [1:1] scan_lo; - - bsg_scan_2_1_1 - scan - ( - .i(i), - .o({ scan_lo[1:1], o[0:0] }) - ); - - assign o[1] = scan_lo[1] & N0; - assign N0 = ~o[0]; - -endmodule - - - -module bsg_arb_fixed_2_1 -( - ready_i, - reqs_i, - grants_o -); - - input [1:0] reqs_i; - output [1:0] grants_o; - input ready_i; - wire [1:0] grants_o,grants_unmasked_lo; - - bsg_priority_encode_one_hot_out_2_1 - enc - ( - .i(reqs_i), - .o(grants_unmasked_lo) - ); - - assign grants_o[1] = grants_unmasked_lo[1] & ready_i; - assign grants_o[0] = grants_unmasked_lo[0] & ready_i; - -endmodule - - - -module bsg_transpose_width_p2_els_p1 -( - i, - o -); - - input [1:0] i; - output [1:0] o; - wire [1:0] o; - assign o[1] = i[1]; - assign o[0] = i[0]; - -endmodule - - - -module bsg_crossbar_control_o_by_i_i_els_p2_o_els_p1_rr_lo_hi_p5 -( - clk_i, - reset_i, - reverse_pr_i, - valid_i, - sel_io_i, - yumi_o, - ready_i, - valid_o, - grants_oi_one_hot_o -); - - input [1:0] valid_i; - input [1:0] sel_io_i; - output [1:0] yumi_o; - input [0:0] ready_i; - output [0:0] valid_o; - output [1:0] grants_oi_one_hot_o; - input clk_i; - input reset_i; - input reverse_pr_i; - wire [1:0] yumi_o,grants_oi_one_hot_o,sel_io_one_hot,sel_oi_one_hot,grants_io_one_hot; - wire [0:0] valid_o; - wire N0,N1,N2,N3,N4,N5,N6,N7,N8; - wire [3:0] arb_0__dynamic_grants_oi_one_hot; - - bsg_transpose_width_p1_els_p2 - transpose0 - ( - .i(sel_io_one_hot), - .o(sel_oi_one_hot) - ); - - - bsg_arb_fixed_2_0 - arb_0__dynamic_fixed_arb_low - ( - .ready_i(ready_i[0]), - .reqs_i(sel_oi_one_hot), - .grants_o(arb_0__dynamic_grants_oi_one_hot[1:0]) - ); - - - bsg_arb_fixed_2_1 - arb_0__dynamic_fixed_arb_high - ( - .ready_i(ready_i[0]), - .reqs_i(sel_oi_one_hot), - .grants_o(arb_0__dynamic_grants_oi_one_hot[3:2]) - ); - - - bsg_transpose_width_p2_els_p1 - transpose1 - ( - .i(grants_oi_one_hot_o), - .o(grants_io_one_hot) - ); - - assign sel_io_one_hot[0] = (N0)? N5 : - (N4)? 1'b0 : 1'b0; - assign N0 = valid_i[0]; - assign sel_io_one_hot[1] = (N1)? N7 : - (N6)? 1'b0 : 1'b0; - assign N1 = valid_i[1]; - assign grants_oi_one_hot_o = (N2)? arb_0__dynamic_grants_oi_one_hot[3:2] : - (N3)? arb_0__dynamic_grants_oi_one_hot[1:0] : 1'b0; - assign N2 = reverse_pr_i; - assign N3 = N8; - assign N4 = ~valid_i[0]; - assign N6 = ~valid_i[1]; - assign N8 = ~reverse_pr_i; - assign valid_o[0] = grants_oi_one_hot_o[1] | grants_oi_one_hot_o[0]; - assign yumi_o[0] = valid_i[0] & grants_io_one_hot[0]; - assign yumi_o[1] = valid_i[1] & grants_io_one_hot[1]; - assign N7 = ~sel_io_i[1]; - assign N5 = ~sel_io_i[0]; - -endmodule - - - -module bsg_mux_one_hot_width_p32_els_p2 -( - data_i, - sel_one_hot_i, - data_o -); - - input [63:0] data_i; - input [1:0] sel_one_hot_i; - output [31:0] data_o; - wire [31:0] data_o; - wire [63:0] data_masked; - assign data_masked[31] = data_i[31] & sel_one_hot_i[0]; - assign data_masked[30] = data_i[30] & sel_one_hot_i[0]; - assign data_masked[29] = data_i[29] & sel_one_hot_i[0]; - assign data_masked[28] = data_i[28] & sel_one_hot_i[0]; - assign data_masked[27] = data_i[27] & sel_one_hot_i[0]; - assign data_masked[26] = data_i[26] & sel_one_hot_i[0]; - assign data_masked[25] = data_i[25] & sel_one_hot_i[0]; - assign data_masked[24] = data_i[24] & sel_one_hot_i[0]; - assign data_masked[23] = data_i[23] & sel_one_hot_i[0]; - assign data_masked[22] = data_i[22] & sel_one_hot_i[0]; - assign data_masked[21] = data_i[21] & sel_one_hot_i[0]; - assign data_masked[20] = data_i[20] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[0]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[0]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[0]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[0]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[0]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[0]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[0]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[0]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[0]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[0]; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[63] = data_i[63] & sel_one_hot_i[1]; - assign data_masked[62] = data_i[62] & sel_one_hot_i[1]; - assign data_masked[61] = data_i[61] & sel_one_hot_i[1]; - assign data_masked[60] = data_i[60] & sel_one_hot_i[1]; - assign data_masked[59] = data_i[59] & sel_one_hot_i[1]; - assign data_masked[58] = data_i[58] & sel_one_hot_i[1]; - assign data_masked[57] = data_i[57] & sel_one_hot_i[1]; - assign data_masked[56] = data_i[56] & sel_one_hot_i[1]; - assign data_masked[55] = data_i[55] & sel_one_hot_i[1]; - assign data_masked[54] = data_i[54] & sel_one_hot_i[1]; - assign data_masked[53] = data_i[53] & sel_one_hot_i[1]; - assign data_masked[52] = data_i[52] & sel_one_hot_i[1]; - assign data_masked[51] = data_i[51] & sel_one_hot_i[1]; - assign data_masked[50] = data_i[50] & sel_one_hot_i[1]; - assign data_masked[49] = data_i[49] & sel_one_hot_i[1]; - assign data_masked[48] = data_i[48] & sel_one_hot_i[1]; - assign data_masked[47] = data_i[47] & sel_one_hot_i[1]; - assign data_masked[46] = data_i[46] & sel_one_hot_i[1]; - assign data_masked[45] = data_i[45] & sel_one_hot_i[1]; - assign data_masked[44] = data_i[44] & sel_one_hot_i[1]; - assign data_masked[43] = data_i[43] & sel_one_hot_i[1]; - assign data_masked[42] = data_i[42] & sel_one_hot_i[1]; - assign data_masked[41] = data_i[41] & sel_one_hot_i[1]; - assign data_masked[40] = data_i[40] & sel_one_hot_i[1]; - assign data_masked[39] = data_i[39] & sel_one_hot_i[1]; - assign data_masked[38] = data_i[38] & sel_one_hot_i[1]; - assign data_masked[37] = data_i[37] & sel_one_hot_i[1]; - assign data_masked[36] = data_i[36] & sel_one_hot_i[1]; - assign data_masked[35] = data_i[35] & sel_one_hot_i[1]; - assign data_masked[34] = data_i[34] & sel_one_hot_i[1]; - assign data_masked[33] = data_i[33] & sel_one_hot_i[1]; - assign data_masked[32] = data_i[32] & sel_one_hot_i[1]; - assign data_o[0] = data_masked[32] | data_masked[0]; - assign data_o[1] = data_masked[33] | data_masked[1]; - assign data_o[2] = data_masked[34] | data_masked[2]; - assign data_o[3] = data_masked[35] | data_masked[3]; - assign data_o[4] = data_masked[36] | data_masked[4]; - assign data_o[5] = data_masked[37] | data_masked[5]; - assign data_o[6] = data_masked[38] | data_masked[6]; - assign data_o[7] = data_masked[39] | data_masked[7]; - assign data_o[8] = data_masked[40] | data_masked[8]; - assign data_o[9] = data_masked[41] | data_masked[9]; - assign data_o[10] = data_masked[42] | data_masked[10]; - assign data_o[11] = data_masked[43] | data_masked[11]; - assign data_o[12] = data_masked[44] | data_masked[12]; - assign data_o[13] = data_masked[45] | data_masked[13]; - assign data_o[14] = data_masked[46] | data_masked[14]; - assign data_o[15] = data_masked[47] | data_masked[15]; - assign data_o[16] = data_masked[48] | data_masked[16]; - assign data_o[17] = data_masked[49] | data_masked[17]; - assign data_o[18] = data_masked[50] | data_masked[18]; - assign data_o[19] = data_masked[51] | data_masked[19]; - assign data_o[20] = data_masked[52] | data_masked[20]; - assign data_o[21] = data_masked[53] | data_masked[21]; - assign data_o[22] = data_masked[54] | data_masked[22]; - assign data_o[23] = data_masked[55] | data_masked[23]; - assign data_o[24] = data_masked[56] | data_masked[24]; - assign data_o[25] = data_masked[57] | data_masked[25]; - assign data_o[26] = data_masked[58] | data_masked[26]; - assign data_o[27] = data_masked[59] | data_masked[27]; - assign data_o[28] = data_masked[60] | data_masked[28]; - assign data_o[29] = data_masked[61] | data_masked[29]; - assign data_o[30] = data_masked[62] | data_masked[30]; - assign data_o[31] = data_masked[63] | data_masked[31]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p32 -( - i, - sel_oi_one_hot_i, - o -); - - input [63:0] i; - input [1:0] sel_oi_one_hot_i; - output [31:0] o; - wire [31:0] o; - - bsg_mux_one_hot_width_p32_els_p2 - genblk1_0__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i), - .data_o(o) - ); - - -endmodule - - - -module bsg_mux_one_hot_width_p10_els_p2 -( - data_i, - sel_one_hot_i, - data_o -); - - input [19:0] data_i; - input [1:0] sel_one_hot_i; - output [9:0] data_o; - wire [9:0] data_o; - wire [19:0] data_masked; - assign data_masked[9] = data_i[9] & sel_one_hot_i[0]; - assign data_masked[8] = data_i[8] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[0]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[0]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[0]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[0]; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[19] = data_i[19] & sel_one_hot_i[1]; - assign data_masked[18] = data_i[18] & sel_one_hot_i[1]; - assign data_masked[17] = data_i[17] & sel_one_hot_i[1]; - assign data_masked[16] = data_i[16] & sel_one_hot_i[1]; - assign data_masked[15] = data_i[15] & sel_one_hot_i[1]; - assign data_masked[14] = data_i[14] & sel_one_hot_i[1]; - assign data_masked[13] = data_i[13] & sel_one_hot_i[1]; - assign data_masked[12] = data_i[12] & sel_one_hot_i[1]; - assign data_masked[11] = data_i[11] & sel_one_hot_i[1]; - assign data_masked[10] = data_i[10] & sel_one_hot_i[1]; - assign data_o[0] = data_masked[10] | data_masked[0]; - assign data_o[1] = data_masked[11] | data_masked[1]; - assign data_o[2] = data_masked[12] | data_masked[2]; - assign data_o[3] = data_masked[13] | data_masked[3]; - assign data_o[4] = data_masked[14] | data_masked[4]; - assign data_o[5] = data_masked[15] | data_masked[5]; - assign data_o[6] = data_masked[16] | data_masked[6]; - assign data_o[7] = data_masked[17] | data_masked[7]; - assign data_o[8] = data_masked[18] | data_masked[8]; - assign data_o[9] = data_masked[19] | data_masked[9]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p10 -( - i, - sel_oi_one_hot_i, - o -); - - input [19:0] i; - input [1:0] sel_oi_one_hot_i; - output [9:0] o; - wire [9:0] o; - - bsg_mux_one_hot_width_p10_els_p2 - genblk1_0__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i), - .data_o(o) - ); - - -endmodule - - - -module bsg_mux_one_hot_width_p1_els_p2 -( - data_i, - sel_one_hot_i, - data_o -); - - input [1:0] data_i; - input [1:0] sel_one_hot_i; - output [0:0] data_o; - wire [0:0] data_o; - wire [1:0] data_masked; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[1]; - assign data_o[0] = data_masked[1] | data_masked[0]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p1 -( - i, - sel_oi_one_hot_i, - o -); - - input [1:0] i; - input [1:0] sel_oi_one_hot_i; - output [0:0] o; - wire [0:0] o; - - bsg_mux_one_hot_width_p1_els_p2 - genblk1_0__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i), - .data_o(o[0]) - ); - - -endmodule - - - -module bsg_mux_one_hot_width_p4_els_p2 -( - data_i, - sel_one_hot_i, - data_o -); - - input [7:0] data_i; - input [1:0] sel_one_hot_i; - output [3:0] data_o; - wire [3:0] data_o; - wire [7:0] data_masked; - assign data_masked[3] = data_i[3] & sel_one_hot_i[0]; - assign data_masked[2] = data_i[2] & sel_one_hot_i[0]; - assign data_masked[1] = data_i[1] & sel_one_hot_i[0]; - assign data_masked[0] = data_i[0] & sel_one_hot_i[0]; - assign data_masked[7] = data_i[7] & sel_one_hot_i[1]; - assign data_masked[6] = data_i[6] & sel_one_hot_i[1]; - assign data_masked[5] = data_i[5] & sel_one_hot_i[1]; - assign data_masked[4] = data_i[4] & sel_one_hot_i[1]; - assign data_o[0] = data_masked[4] | data_masked[0]; - assign data_o[1] = data_masked[5] | data_masked[1]; - assign data_o[2] = data_masked[6] | data_masked[2]; - assign data_o[3] = data_masked[7] | data_masked[3]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p4 -( - i, - sel_oi_one_hot_i, - o -); - - input [7:0] i; - input [1:0] sel_oi_one_hot_i; - output [3:0] o; - wire [3:0] o; - - bsg_mux_one_hot_width_p4_els_p2 - genblk1_0__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i), - .data_o(o) - ); - - -endmodule - - - -module bsg_mem_1rw_sync_mask_write_byte_els_p1024_data_width_p32 -( - clk_i, - reset_i, - v_i, - w_i, - addr_i, - data_i, - write_mask_i, - data_o -); - - input [9:0] addr_i; - input [31:0] data_i; - input [3:0] write_mask_i; - output [31:0] data_o; - input clk_i; - input reset_i; - input v_i; - input w_i; - wire [31:0] data_o,macro_wen; - wire n_0_net_,n_1_net_; - - tsmc65lp_1rf_lg10_w32_byte - macro_mem - ( - .CLK(clk_i), - .Q(data_o), - .CEN(n_0_net_), - .WEN(macro_wen), - .GWEN(n_1_net_), - .A(addr_i), - .D(data_i), - .EMA({ 1'b0, 1'b1, 1'b1 }), - .EMAW({ 1'b0, 1'b1 }), - .RET1N(1'b1) - ); - - assign macro_wen[31] = ~write_mask_i[3]; - assign macro_wen[30] = ~write_mask_i[3]; - assign macro_wen[29] = ~write_mask_i[3]; - assign macro_wen[28] = ~write_mask_i[3]; - assign macro_wen[27] = ~write_mask_i[3]; - assign macro_wen[26] = ~write_mask_i[3]; - assign macro_wen[25] = ~write_mask_i[3]; - assign macro_wen[24] = ~write_mask_i[3]; - assign macro_wen[23] = ~write_mask_i[2]; - assign macro_wen[22] = ~write_mask_i[2]; - assign macro_wen[21] = ~write_mask_i[2]; - assign macro_wen[20] = ~write_mask_i[2]; - assign macro_wen[19] = ~write_mask_i[2]; - assign macro_wen[18] = ~write_mask_i[2]; - assign macro_wen[17] = ~write_mask_i[2]; - assign macro_wen[16] = ~write_mask_i[2]; - assign macro_wen[15] = ~write_mask_i[1]; - assign macro_wen[14] = ~write_mask_i[1]; - assign macro_wen[13] = ~write_mask_i[1]; - assign macro_wen[12] = ~write_mask_i[1]; - assign macro_wen[11] = ~write_mask_i[1]; - assign macro_wen[10] = ~write_mask_i[1]; - assign macro_wen[9] = ~write_mask_i[1]; - assign macro_wen[8] = ~write_mask_i[1]; - assign macro_wen[7] = ~write_mask_i[0]; - assign macro_wen[6] = ~write_mask_i[0]; - assign macro_wen[5] = ~write_mask_i[0]; - assign macro_wen[4] = ~write_mask_i[0]; - assign macro_wen[3] = ~write_mask_i[0]; - assign macro_wen[2] = ~write_mask_i[0]; - assign macro_wen[1] = ~write_mask_i[0]; - assign macro_wen[0] = ~write_mask_i[0]; - assign n_1_net_ = ~w_i; - assign n_0_net_ = ~v_i; - -endmodule - - - -module bsg_mux_one_hot_width_p32_els_p1 -( - data_i, - sel_one_hot_i, - data_o -); - - input [31:0] data_i; - input [0:0] sel_one_hot_i; - output [31:0] data_o; - wire [31:0] data_o; - assign data_o[31] = data_i[31] & sel_one_hot_i[0]; - assign data_o[30] = data_i[30] & sel_one_hot_i[0]; - assign data_o[29] = data_i[29] & sel_one_hot_i[0]; - assign data_o[28] = data_i[28] & sel_one_hot_i[0]; - assign data_o[27] = data_i[27] & sel_one_hot_i[0]; - assign data_o[26] = data_i[26] & sel_one_hot_i[0]; - assign data_o[25] = data_i[25] & sel_one_hot_i[0]; - assign data_o[24] = data_i[24] & sel_one_hot_i[0]; - assign data_o[23] = data_i[23] & sel_one_hot_i[0]; - assign data_o[22] = data_i[22] & sel_one_hot_i[0]; - assign data_o[21] = data_i[21] & sel_one_hot_i[0]; - assign data_o[20] = data_i[20] & sel_one_hot_i[0]; - assign data_o[19] = data_i[19] & sel_one_hot_i[0]; - assign data_o[18] = data_i[18] & sel_one_hot_i[0]; - assign data_o[17] = data_i[17] & sel_one_hot_i[0]; - assign data_o[16] = data_i[16] & sel_one_hot_i[0]; - assign data_o[15] = data_i[15] & sel_one_hot_i[0]; - assign data_o[14] = data_i[14] & sel_one_hot_i[0]; - assign data_o[13] = data_i[13] & sel_one_hot_i[0]; - assign data_o[12] = data_i[12] & sel_one_hot_i[0]; - assign data_o[11] = data_i[11] & sel_one_hot_i[0]; - assign data_o[10] = data_i[10] & sel_one_hot_i[0]; - assign data_o[9] = data_i[9] & sel_one_hot_i[0]; - assign data_o[8] = data_i[8] & sel_one_hot_i[0]; - assign data_o[7] = data_i[7] & sel_one_hot_i[0]; - assign data_o[6] = data_i[6] & sel_one_hot_i[0]; - assign data_o[5] = data_i[5] & sel_one_hot_i[0]; - assign data_o[4] = data_i[4] & sel_one_hot_i[0]; - assign data_o[3] = data_i[3] & sel_one_hot_i[0]; - assign data_o[2] = data_i[2] & sel_one_hot_i[0]; - assign data_o[1] = data_i[1] & sel_one_hot_i[0]; - assign data_o[0] = data_i[0] & sel_one_hot_i[0]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p1_o_els_p2_width_p32 -( - i, - sel_oi_one_hot_i, - o -); - - input [31:0] i; - input [1:0] sel_oi_one_hot_i; - output [63:0] o; - wire [63:0] o; - - bsg_mux_one_hot_width_p32_els_p1 - genblk1_0__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i[0]), - .data_o(o[31:0]) - ); - - - bsg_mux_one_hot_width_p32_els_p1 - genblk1_1__mux_one_hot - ( - .data_i(i), - .sel_one_hot_i(sel_oi_one_hot_i[1]), - .data_o(o[63:32]) - ); - - -endmodule - - - -module bsg_mux_one_hot_width_p1_els_p1 -( - data_i, - sel_one_hot_i, - data_o -); - - input [0:0] data_i; - input [0:0] sel_one_hot_i; - output [0:0] data_o; - wire [0:0] data_o; - assign data_o[0] = data_i[0] & sel_one_hot_i[0]; - -endmodule - - - -module bsg_crossbar_o_by_i_i_els_p1_o_els_p2_width_p1 -( - i, - sel_oi_one_hot_i, - o -); - - input [0:0] i; - input [1:0] sel_oi_one_hot_i; - output [1:0] o; - wire [1:0] o; - - bsg_mux_one_hot_width_p1_els_p1 - genblk1_0__mux_one_hot - ( - .data_i(i[0]), - .sel_one_hot_i(sel_oi_one_hot_i[0]), - .data_o(o[0]) - ); - - - bsg_mux_one_hot_width_p1_els_p1 - genblk1_1__mux_one_hot - ( - .data_i(i[0]), - .sel_one_hot_i(sel_oi_one_hot_i[1]), - .data_o(o[1]) - ); - - -endmodule - - - -module bsg_mem_banked_crossbar_num_ports_p2_num_banks_p1_bank_size_p1024_rr_lo_hi_p5_data_width_p32 -( - clk_i, - reset_i, - reverse_pr_i, - v_i, - w_i, - addr_i, - data_i, - mask_i, - yumi_o, - v_o, - data_o -); - - input [1:0] v_i; - input [1:0] w_i; - input [19:0] addr_i; - input [63:0] data_i; - input [7:0] mask_i; - output [1:0] yumi_o; - output [1:0] v_o; - output [63:0] data_o; - input clk_i; - input reset_i; - input reverse_pr_i; - wire [1:0] yumi_o,v_o,bank_port_grants_one_hot,port_bank_grants_one_hot; - wire [63:0] data_o; - wire n_1_net__0_,N0; - wire [0:0] bank_v,bank_w; - wire [31:0] bank_data,bank_data_out; - wire [9:0] bank_addr; - wire [3:0] bank_mask; - reg [1:0] bank_port_grants_one_hot_r; - reg [0:0] bank_w_r,bank_v_r; - - bsg_crossbar_control_o_by_i_i_els_p2_o_els_p1_rr_lo_hi_p5 - crossbar_control - ( - .clk_i(clk_i), - .reset_i(reset_i), - .reverse_pr_i(reverse_pr_i), - .valid_i(v_i), - .sel_io_i({ 1'b0, 1'b0 }), - .yumi_o(yumi_o), - .ready_i(1'b1), - .valid_o(bank_v[0]), - .grants_oi_one_hot_o(bank_port_grants_one_hot) - ); - - - bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p32 - port_bank_data_crossbar - ( - .i(data_i), - .sel_oi_one_hot_i(bank_port_grants_one_hot), - .o(bank_data) - ); - - - bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p10 - port_bank_addr_crossbar - ( - .i(addr_i), - .sel_oi_one_hot_i(bank_port_grants_one_hot), - .o(bank_addr) - ); - - - bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p1 - port_bank_w_crossbar - ( - .i(w_i), - .sel_oi_one_hot_i(bank_port_grants_one_hot), - .o(bank_w[0]) - ); - - - bsg_crossbar_o_by_i_i_els_p2_o_els_p1_width_p4 - port_bank_mask_crossbar - ( - .i(mask_i), - .sel_oi_one_hot_i(bank_port_grants_one_hot), - .o(bank_mask) - ); - - - bsg_mem_1rw_sync_mask_write_byte_els_p1024_data_width_p32 - z_0__m1rw_mask - ( - .clk_i(clk_i), - .reset_i(reset_i), - .v_i(bank_v[0]), - .w_i(bank_w[0]), - .addr_i(bank_addr), - .data_i(bank_data), - .write_mask_i(bank_mask), - .data_o(bank_data_out) - ); - - - always @(posedge clk_i) begin - if(1'b1) begin - bank_port_grants_one_hot_r[1] <= bank_port_grants_one_hot[1]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - bank_port_grants_one_hot_r[0] <= bank_port_grants_one_hot[0]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - bank_w_r[0] <= bank_w[0]; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - bank_v_r[0] <= bank_v[0]; - end - end - - - bsg_transpose_width_p2_els_p1 - grants_transpose - ( - .i(bank_port_grants_one_hot_r), - .o(port_bank_grants_one_hot) - ); - - - bsg_crossbar_o_by_i_i_els_p1_o_els_p2_width_p32 - bank_port_data_crossbar - ( - .i(bank_data_out), - .sel_oi_one_hot_i(port_bank_grants_one_hot), - .o(data_o) - ); - - - bsg_crossbar_o_by_i_i_els_p1_o_els_p2_width_p1 - bank_port_v_crossbar - ( - .i(n_1_net__0_), - .sel_oi_one_hot_i(port_bank_grants_one_hot), - .o(v_o) - ); - - assign n_1_net__0_ = bank_v_r[0] & N0; - assign N0 = ~bank_w_r[0]; - -endmodule - - - -module bsg_manycore_proc_vanilla_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_num_banks_p1_imem_size_p1024_max_out_credits_p200_hetero_type_p0 -( - clk_i, - reset_i, - link_sif_i, - link_sif_o, - my_x_i, - my_y_i, - freeze_o -); - - input [88:0] link_sif_i; - output [88:0] link_sif_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - output freeze_o; - wire [88:0] link_sif_o; - wire freeze_o,N0,N1,N2,N3,N4,N5,N6,in_v_lo,in_yumi_li,out_v_li,out_ready_lo, - reverse_arb_pr,core_mem_reserve_1,N7,N8,N9,N10,N11,N12,N13,N14,launching_out, - non_imem_bits_set,remote_store_imem_not_dmem,N15,N16,N17,pkt_unfreeze,pkt_freeze,n_0_net_, - core_net_pkt_valid_,core_net_pkt_header__net_op__1_,core_net_pkt_header__mask__3_, - core_net_pkt_header__mask__2_,core_net_pkt_header__mask__1_, - core_net_pkt_header__mask__0_,core_net_pkt_header__addr__13_,core_net_pkt_header__addr__12_, - core_net_pkt_header__addr__11_,core_net_pkt_header__addr__10_, - core_net_pkt_header__addr__9_,core_net_pkt_header__addr__8_,core_net_pkt_header__addr__7_, - core_net_pkt_header__addr__6_,core_net_pkt_header__addr__5_,core_net_pkt_header__addr__4_, - core_net_pkt_header__addr__3_,core_net_pkt_header__addr__2_,core_net_pkt_data__31_, - core_net_pkt_data__30_,core_net_pkt_data__29_,core_net_pkt_data__28_, - core_net_pkt_data__27_,core_net_pkt_data__26_,core_net_pkt_data__25_,core_net_pkt_data__24_, - core_net_pkt_data__23_,core_net_pkt_data__22_,core_net_pkt_data__21_, - core_net_pkt_data__20_,core_net_pkt_data__19_,core_net_pkt_data__18_,core_net_pkt_data__17_, - core_net_pkt_data__16_,core_net_pkt_data__15_,core_net_pkt_data__14_, - core_net_pkt_data__13_,core_net_pkt_data__12_,core_net_pkt_data__11_,core_net_pkt_data__10_, - core_net_pkt_data__9_,core_net_pkt_data__8_,core_net_pkt_data__7_, - core_net_pkt_data__6_,core_net_pkt_data__5_,core_net_pkt_data__4_,core_net_pkt_data__3_, - core_net_pkt_data__2_,core_net_pkt_data__1_,core_net_pkt_data__0_,N18,out_request, - unused_valid,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35, - N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49; - wire [31:0] in_data_lo,unused_data; - wire [3:0] in_mask_lo; - wire [19:0] in_addr_lo; - wire [75:0] out_packet_li; - wire [7:0] out_credits_lo; - wire [33:0] mem_to_core; - wire [70:0] core_to_mem; - wire [1:0] xbar_port_v_in,xbar_port_yumi_out; - reg [19:0] core_mem_reserve_addr_r; - reg core_mem_reservation_r,freeze_r_r; - - bsg_manycore_endpoint_standard_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20_max_out_credits_p200_debug_p0 - endp - ( - .clk_i(clk_i), - .reset_i(reset_i), - .link_sif_i(link_sif_i), - .link_sif_o(link_sif_o), - .in_v_o(in_v_lo), - .in_yumi_i(in_yumi_li), - .in_data_o(in_data_lo), - .in_mask_o(in_mask_lo), - .in_addr_o(in_addr_lo), - .out_v_i(out_v_li), - .out_packet_i(out_packet_li), - .out_ready_o(out_ready_lo), - .out_credits_o(out_credits_lo), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .freeze_r_o(freeze_o), - .reverse_arb_pr_o(reverse_arb_pr) - ); - - assign N8 = core_mem_reserve_addr_r == in_addr_lo; - - always @(posedge clk_i) begin - if(N7) begin - core_mem_reserve_addr_r[19] <= 1'b0; - end else begin - core_mem_reserve_addr_r[19] <= 1'b0; - end - end - - - always @(posedge clk_i) begin - if(N7) begin - core_mem_reserve_addr_r[18] <= 1'b0; - end else begin - core_mem_reserve_addr_r[18] <= 1'b0; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[17] <= core_to_mem[52]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[16] <= core_to_mem[51]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[15] <= core_to_mem[50]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[14] <= core_to_mem[49]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[13] <= core_to_mem[48]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[12] <= core_to_mem[47]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[11] <= core_to_mem[46]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[10] <= core_to_mem[45]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[9] <= core_to_mem[44]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[8] <= core_to_mem[43]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[7] <= core_to_mem[42]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[6] <= core_to_mem[41]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[5] <= core_to_mem[40]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[4] <= core_to_mem[39]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[3] <= core_to_mem[38]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[2] <= core_to_mem[37]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[1] <= core_to_mem[36]; - end - end - - - always @(posedge clk_i) begin - if(N12) begin - core_mem_reserve_addr_r[0] <= core_to_mem[35]; - end - end - - - always @(posedge clk_i) begin - if(N9) begin - core_mem_reservation_r <= 1'b0; - end else if(N7) begin - core_mem_reservation_r <= 1'b1; - end else begin - core_mem_reservation_r <= N6; - end - end - - - always @(posedge clk_i) begin - if(1'b1) begin - freeze_r_r <= N17; - end - end - - - hobbit_imem_addr_width_p10_gw_ID_p0_ring_ID_p0_x_cord_width_p4_y_cord_width_p5 - vanilla_core - ( - .clk(clk_i), - .reset(n_0_net_), - .net_packet_i({ core_net_pkt_valid_, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, core_net_pkt_header__net_op__1_, 1'b1, core_net_pkt_header__mask__3_, core_net_pkt_header__mask__2_, core_net_pkt_header__mask__1_, core_net_pkt_header__mask__0_, 1'b0, 1'b0, core_net_pkt_header__addr__13_, core_net_pkt_header__addr__12_, core_net_pkt_header__addr__11_, core_net_pkt_header__addr__10_, core_net_pkt_header__addr__9_, core_net_pkt_header__addr__8_, core_net_pkt_header__addr__7_, core_net_pkt_header__addr__6_, core_net_pkt_header__addr__5_, core_net_pkt_header__addr__4_, core_net_pkt_header__addr__3_, core_net_pkt_header__addr__2_, 1'b0, 1'b0, core_net_pkt_data__31_, core_net_pkt_data__30_, core_net_pkt_data__29_, core_net_pkt_data__28_, core_net_pkt_data__27_, core_net_pkt_data__26_, core_net_pkt_data__25_, core_net_pkt_data__24_, core_net_pkt_data__23_, core_net_pkt_data__22_, core_net_pkt_data__21_, core_net_pkt_data__20_, core_net_pkt_data__19_, core_net_pkt_data__18_, core_net_pkt_data__17_, core_net_pkt_data__16_, core_net_pkt_data__15_, core_net_pkt_data__14_, core_net_pkt_data__13_, core_net_pkt_data__12_, core_net_pkt_data__11_, core_net_pkt_data__10_, core_net_pkt_data__9_, core_net_pkt_data__8_, core_net_pkt_data__7_, core_net_pkt_data__6_, core_net_pkt_data__5_, core_net_pkt_data__4_, core_net_pkt_data__3_, core_net_pkt_data__2_, core_net_pkt_data__1_, core_net_pkt_data__0_ }), - .from_mem_i(mem_to_core), - .to_mem_o(core_to_mem), - .reservation_i(core_mem_reservation_r), - .reserve_1_o(core_mem_reserve_1), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .outstanding_stores_i(N28) - ); - - - bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 - pkt_encode - ( - .clk_i(clk_i), - .v_i(core_to_mem[70]), - .addr_i(core_to_mem[64:33]), - .data_i(core_to_mem[32:1]), - .mask_i(core_to_mem[68:65]), - .we_i(core_to_mem[69]), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .v_o(out_request), - .data_o(out_packet_li) - ); - - - bsg_mem_banked_crossbar_num_ports_p2_num_banks_p1_bank_size_p1024_rr_lo_hi_p5_data_width_p32 - bnkd_xbar - ( - .clk_i(clk_i), - .reset_i(reset_i), - .reverse_pr_i(reverse_arb_pr), - .v_i(xbar_port_v_in), - .w_i({ core_to_mem[69:69], 1'b1 }), - .addr_i({ core_to_mem[44:35], in_addr_lo[9:0] }), - .data_i({ core_to_mem[32:1], in_data_lo }), - .mask_i({ core_to_mem[68:65], in_mask_lo }), - .yumi_o(xbar_port_yumi_out), - .v_o({ mem_to_core[33:33], unused_valid }), - .data_o({ mem_to_core[32:1], unused_data }) - ); - - assign N19 = ~out_credits_lo[7]; - assign N20 = ~out_credits_lo[6]; - assign N21 = ~out_credits_lo[3]; - assign N22 = N20 | N19; - assign N23 = out_credits_lo[5] | N22; - assign N24 = out_credits_lo[4] | N23; - assign N25 = N21 | N24; - assign N26 = out_credits_lo[2] | N25; - assign N27 = out_credits_lo[1] | N26; - assign N28 = out_credits_lo[0] | N27; - assign N29 = ~freeze_r_r; - assign N30 = ~freeze_o; - assign N12 = (N0)? 1'b1 : - (N14)? 1'b0 : - (N11)? 1'b0 : 1'b0; - assign N0 = N7; - assign N17 = (N1)? 1'b0 : - (N2)? freeze_o : 1'b0; - assign N1 = N16; - assign N2 = N15; - assign { core_net_pkt_header__mask__3_, core_net_pkt_header__mask__2_, core_net_pkt_header__mask__1_, core_net_pkt_header__mask__0_, core_net_pkt_header__addr__13_, core_net_pkt_header__addr__12_, core_net_pkt_header__addr__11_, core_net_pkt_header__addr__10_, core_net_pkt_header__addr__9_, core_net_pkt_header__addr__8_, core_net_pkt_header__addr__7_, core_net_pkt_header__addr__6_, core_net_pkt_header__addr__5_, core_net_pkt_header__addr__4_, core_net_pkt_header__addr__3_, core_net_pkt_header__addr__2_ } = (N3)? { in_mask_lo, in_addr_lo[11:0] } : - (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N3 = remote_store_imem_not_dmem; - assign N4 = core_net_pkt_header__net_op__1_; - assign { core_net_pkt_data__31_, core_net_pkt_data__30_, core_net_pkt_data__29_, core_net_pkt_data__28_, core_net_pkt_data__27_, core_net_pkt_data__26_, core_net_pkt_data__25_, core_net_pkt_data__24_, core_net_pkt_data__23_, core_net_pkt_data__22_, core_net_pkt_data__21_, core_net_pkt_data__20_, core_net_pkt_data__19_, core_net_pkt_data__18_, core_net_pkt_data__17_, core_net_pkt_data__16_, core_net_pkt_data__15_, core_net_pkt_data__14_, core_net_pkt_data__13_, core_net_pkt_data__12_, core_net_pkt_data__11_, core_net_pkt_data__10_, core_net_pkt_data__9_, core_net_pkt_data__8_, core_net_pkt_data__7_, core_net_pkt_data__6_, core_net_pkt_data__5_, core_net_pkt_data__4_, core_net_pkt_data__3_, core_net_pkt_data__2_, core_net_pkt_data__1_, core_net_pkt_data__0_ } = (N3)? in_data_lo : - (N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0; - assign N5 = N18; - assign N6 = 1'b0; - assign N7 = N31 & xbar_port_yumi_out[1]; - assign N31 = core_to_mem[70] & core_mem_reserve_1; - assign N9 = N32 & in_yumi_li; - assign N32 = in_v_lo & N8; - assign N10 = N9 | N7; - assign N11 = ~N10; - assign N13 = ~N7; - assign N14 = N9 & N13; - assign launching_out = out_v_li & out_ready_lo; - assign non_imem_bits_set = N40 | in_addr_lo[10]; - assign N40 = N39 | in_addr_lo[11]; - assign N39 = N38 | in_addr_lo[12]; - assign N38 = N37 | in_addr_lo[13]; - assign N37 = N36 | in_addr_lo[14]; - assign N36 = N35 | in_addr_lo[15]; - assign N35 = N34 | in_addr_lo[16]; - assign N34 = N33 | in_addr_lo[17]; - assign N33 = in_addr_lo[19] | in_addr_lo[18]; - assign remote_store_imem_not_dmem = in_v_lo & N41; - assign N41 = ~non_imem_bits_set; - assign xbar_port_v_in[0] = in_v_lo & non_imem_bits_set; - assign N15 = ~reset_i; - assign N16 = reset_i; - assign pkt_unfreeze = N30 & freeze_r_r; - assign pkt_freeze = freeze_o & N29; - assign n_0_net_ = reset_i | pkt_freeze; - assign core_net_pkt_valid_ = remote_store_imem_not_dmem | pkt_unfreeze; - assign N18 = ~remote_store_imem_not_dmem; - assign core_net_pkt_header__net_op__1_ = N18; - assign out_v_li = out_request & N48; - assign N48 = N47 | out_credits_lo[0]; - assign N47 = N46 | out_credits_lo[1]; - assign N46 = N45 | out_credits_lo[2]; - assign N45 = N44 | out_credits_lo[3]; - assign N44 = N43 | out_credits_lo[4]; - assign N43 = N42 | out_credits_lo[5]; - assign N42 = out_credits_lo[7] | out_credits_lo[6]; - assign xbar_port_v_in[1] = core_to_mem[70] & N49; - assign N49 = ~core_to_mem[64]; - assign in_yumi_li = xbar_port_yumi_out[0] | remote_store_imem_not_dmem; - assign mem_to_core[0] = xbar_port_yumi_out[1] | launching_out; - -endmodule - - - -module bsg_manycore_hetero_socket_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_imem_size_p1024_num_banks_p1_hetero_type_p0 -( - clk_i, - reset_i, - link_sif_i, - link_sif_o, - my_x_i, - my_y_i, - freeze_o -); - - input [88:0] link_sif_i; - output [88:0] link_sif_o; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - output freeze_o; - wire [88:0] link_sif_o; - wire freeze_o; - - bsg_manycore_proc_vanilla_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_num_banks_p1_imem_size_p1024_max_out_credits_p200_hetero_type_p0 - h_z - ( - .clk_i(clk_i), - .reset_i(reset_i), - .link_sif_i(link_sif_i), - .link_sif_o(link_sif_o), - .my_x_i(my_x_i), - .my_y_i(my_y_i), - .freeze_o(freeze_o) - ); - - -endmodule - - - -module bsg_manycore_tile -( - clk_i, - reset_i, - link_in, - link_out, - my_x_i, - my_y_i -); - - input [355:0] link_in; - output [355:0] link_out; - input [3:0] my_x_i; - input [4:0] my_y_i; - input clk_i; - input reset_i; - wire [355:0] link_out; - wire [88:0] proc_link_sif_li,proc_link_sif_lo; - reg reset_r; - - always @(posedge clk_i) begin - if(1'b1) begin - reset_r <= reset_i; - end - end - - - bsg_manycore_mesh_node_4_5_32_20_0_0_0 - rtr - ( - .clk_i(clk_i), - .reset_i(reset_r), - .links_sif_i(link_in), - .links_sif_o(link_out), - .proc_link_sif_i(proc_link_sif_li), - .proc_link_sif_o(proc_link_sif_lo), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - - bsg_manycore_hetero_socket_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_imem_size_p1024_num_banks_p1_hetero_type_p0 - proc - ( - .clk_i(clk_i), - .reset_i(reset_r), - .link_sif_i(proc_link_sif_lo), - .link_sif_o(proc_link_sif_li), - .my_x_i(my_x_i), - .my_y_i(my_y_i) - ); - - -endmodule - diff --git a/flow/designs/tsmc65lp/aes/config.mk b/flow/designs/tsmc65lp/aes/config.mk deleted file mode 100644 index d8ed07c577..0000000000 --- a/flow/designs/tsmc65lp/aes/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -export DESIGN_NICKNAME = aes -export DESIGN_NAME = aes_cipher_top -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export ABC_AREA = 1 - -export CORE_UTILIZATION = 40 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 5 - -export PLACE_DENSITY = 0.70 -export RECOVER_POWER = 100 diff --git a/flow/designs/tsmc65lp/aes/constraint.sdc b/flow/designs/tsmc65lp/aes/constraint.sdc deleted file mode 100644 index 3986c9cf36..0000000000 --- a/flow/designs/tsmc65lp/aes/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design aes_cipher_top - -set clk_name clk -set clk_port_name clk -set clk_period 1.8 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/aes/metadata-base-ok.json b/flow/designs/tsmc65lp/aes/metadata-base-ok.json deleted file mode 100644 index b8493f67d6..0000000000 --- a/flow/designs/tsmc65lp/aes/metadata-base-ok.json +++ /dev/null @@ -1,304 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 1.8000" - ], - "cts__clock__skew__hold": 0.0383465, - "cts__clock__skew__setup": 0.0383465, - "cts__cpu__total": 51.02, - "cts__design__core__area": 154289, - "cts__design__die__area": 163596, - "cts__design__instance__area": 78966.7, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__stdcell": 78966.7, - "cts__design__instance__count": 14956, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__setup_buffer": 303, - "cts__design__instance__count__stdcell": 14956, - "cts__design__instance__displacement__max": 13, - "cts__design__instance__displacement__mean": 0.227, - "cts__design__instance__displacement__total": 3396.84, - "cts__design__instance__utilization": 0.51181, - "cts__design__instance__utilization__stdcell": 0.51181, - "cts__design__io": 388, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 425056.0, - "cts__power__internal__total": 0.154649, - "cts__power__leakage__total": 6.81011e-05, - "cts__power__switching__total": 0.213565, - "cts__power__total": 0.368282, - "cts__route__wirelength__estimated": 317733, - "cts__runtime__total": "1:23.21", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 1, - "cts__timing__drv__max_cap_limit": -0.087661, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew_limit": 0.130682, - "cts__timing__drv__setup_violation_count": 147, - "cts__timing__setup__tns": -55.9387, - "cts__timing__setup__ws": -0.487, - "design__io__hpwl": 98809354, - "detailedplace__cpu__total": 18.3, - "detailedplace__design__core__area": 154289, - "detailedplace__design__die__area": 163596, - "detailedplace__design__instance__area": 76131.4, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 76131.4, - "detailedplace__design__instance__count": 14536, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 14536, - "detailedplace__design__instance__displacement__max": 36.7, - "detailedplace__design__instance__displacement__mean": 1.7745, - "detailedplace__design__instance__displacement__total": 25797.4, - "detailedplace__design__instance__utilization": 0.493433, - "detailedplace__design__instance__utilization__stdcell": 0.493433, - "detailedplace__design__io": 388, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 385536.0, - "detailedplace__power__internal__total": 0.147522, - "detailedplace__power__leakage__total": 5.87999e-05, - "detailedplace__power__switching__total": 0.20907, - "detailedplace__power__total": 0.356651, - "detailedplace__route__wirelength__estimated": 307145, - "detailedplace__runtime__total": "0:34.08", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 1, - "detailedplace__timing__drv__max_cap_limit": -0.00147187, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 38, - "detailedplace__timing__drv__max_slew_limit": -0.0461483, - "detailedplace__timing__drv__setup_violation_count": 180, - "detailedplace__timing__setup__tns": -144.855, - "detailedplace__timing__setup__ws": -1.49348, - "detailedroute__cpu__total": 786.33, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 2937020.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 5480, - "detailedroute__route__drc_errors__iter:2": 208, - "detailedroute__route__drc_errors__iter:3": 64, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 14745, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 95710, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 95710, - "detailedroute__route__wirelength": 396210, - "detailedroute__route__wirelength__iter:1": 398740, - "detailedroute__route__wirelength__iter:2": 396704, - "detailedroute__route__wirelength__iter:3": 396234, - "detailedroute__route__wirelength__iter:4": 396210, - "detailedroute__runtime__total": "1:11.90", - "fillcell__cpu__total": 4.28, - "fillcell__mem__peak": 355808.0, - "fillcell__runtime__total": "0:04.74", - "finish__clock__skew__hold": 0.0236677, - "finish__clock__skew__setup": 0.0236677, - "finish__cpu__total": 21.1, - "finish__design__core__area": 154289, - "finish__design__die__area": 163596, - "finish__design__instance__area": 81241, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 81241, - "finish__design__instance__count": 15420, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 15420, - "finish__design__instance__utilization": 0.52655, - "finish__design__instance__utilization__stdcell": 0.52655, - "finish__design__io": 388, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 587652.0, - "finish__power__internal__total": 0.161344, - "finish__power__leakage__total": 7.13449e-05, - "finish__power__switching__total": 0.191976, - "finish__power__total": 0.353392, - "finish__runtime__total": "0:21.73", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.411262, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.147704, - "finish__timing__drv__setup_violation_count": 130, - "finish__timing__setup__tns": -10.7126, - "finish__timing__setup__ws": -0.21969, - "finish__timing__wns_percent_delay": -9.819872, - "finish_merge__cpu__total": 8.52, - "finish_merge__mem__peak": 592368.0, - "finish_merge__runtime__total": "0:10.27", - "floorplan__cpu__total": 5.7, - "floorplan__design__core__area": 154289, - "floorplan__design__die__area": 163596, - "floorplan__design__instance__area": 58814.9, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 58814.9, - "floorplan__design__instance__count": 13234, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 13234, - "floorplan__design__instance__utilization": 0.381199, - "floorplan__design__instance__utilization__stdcell": 0.381199, - "floorplan__design__io": 388, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 367780.0, - "floorplan__power__internal__total": 0.112551, - "floorplan__power__leakage__total": 3.97004e-05, - "floorplan__power__switching__total": 0.102712, - "floorplan__power__total": 0.215303, - "floorplan__runtime__total": "0:05.93", - "floorplan__timing__setup__tns": -223.723, - "floorplan__timing__setup__ws": -2.26445, - "floorplan_io__cpu__total": 3.3, - "floorplan_io__mem__peak": 330976.0, - "floorplan_io__runtime__total": "0:03.53", - "floorplan_macro__cpu__total": 3.21, - "floorplan_macro__mem__peak": 332748.0, - "floorplan_macro__runtime__total": "0:03.46", - "floorplan_pdn__cpu__total": 3.36, - "floorplan_pdn__mem__peak": 334328.0, - "floorplan_pdn__runtime__total": "0:03.58", - "floorplan_tap__cpu__total": 3.24, - "floorplan_tap__mem__peak": 320552.0, - "floorplan_tap__runtime__total": "0:03.43", - "floorplan_tdms__cpu__total": 3.29, - "floorplan_tdms__mem__peak": 330816.0, - "floorplan_tdms__runtime__total": "0:03.54", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 7326.68, - "globalplace__design__core__area": 154289, - "globalplace__design__die__area": 163596, - "globalplace__design__instance__area": 59681.8, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 59681.8, - "globalplace__design__instance__count": 14137, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 14137, - "globalplace__design__instance__utilization": 0.386817, - "globalplace__design__instance__utilization__stdcell": 0.386817, - "globalplace__design__io": 388, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 469224.0, - "globalplace__power__internal__total": 0.115387, - "globalplace__power__leakage__total": 3.97004e-05, - "globalplace__power__switching__total": 0.178637, - "globalplace__power__total": 0.294064, - "globalplace__runtime__total": "7:18.50", - "globalplace__timing__setup__tns": -617.877, - "globalplace__timing__setup__ws": -5.27851, - "globalplace_io__cpu__total": 3.26, - "globalplace_io__mem__peak": 332680.0, - "globalplace_io__runtime__total": "0:03.46", - "globalplace_skip_io__cpu__total": 7.4, - "globalplace_skip_io__mem__peak": 347964.0, - "globalplace_skip_io__runtime__total": "0:07.67", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.0410146, - "globalroute__clock__skew__setup": 0.0410146, - "globalroute__cpu__total": 522.77, - "globalroute__design__core__area": 154289, - "globalroute__design__die__area": 163596, - "globalroute__design__instance__area": 81241, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 81241, - "globalroute__design__instance__count": 15420, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 406, - "globalroute__design__instance__count__stdcell": 15420, - "globalroute__design__instance__displacement__max": 26.2, - "globalroute__design__instance__displacement__mean": 0.45, - "globalroute__design__instance__displacement__total": 6944.8, - "globalroute__design__instance__utilization": 0.52655, - "globalroute__design__instance__utilization__stdcell": 0.52655, - "globalroute__design__io": 388, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 867444.0, - "globalroute__power__internal__total": 0.16141, - "globalroute__power__leakage__total": 7.13449e-05, - "globalroute__power__switching__total": 0.241, - "globalroute__power__total": 0.402481, - "globalroute__route__wirelength__estimated": 338962, - "globalroute__runtime__total": "21:45.36", - "globalroute__timing__clock__slack": -0.529, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 2, - "globalroute__timing__drv__max_cap_limit": -0.182694, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 136, - "globalroute__timing__drv__max_slew_limit": -0.115382, - "globalroute__timing__drv__setup_violation_count": 164, - "globalroute__timing__setup__tns": -61.8786, - "globalroute__timing__setup__ws": -0.528738, - "placeopt__cpu__total": 14.65, - "placeopt__design__core__area": 154289, - "placeopt__design__die__area": 163596, - "placeopt__design__instance__area": 76131.4, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__stdcell": 76131.4, - "placeopt__design__instance__count": 14536, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__stdcell": 14536, - "placeopt__design__instance__utilization": 0.493433, - "placeopt__design__instance__utilization__stdcell": 0.493433, - "placeopt__design__io": 388, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 407484.0, - "placeopt__power__internal__total": 0.147527, - "placeopt__power__leakage__total": 5.87999e-05, - "placeopt__power__switching__total": 0.209136, - "placeopt__power__total": 0.356721, - "placeopt__runtime__total": "0:45.30", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.00638702, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0219881, - "placeopt__timing__drv__setup_violation_count": 180, - "placeopt__timing__setup__tns": -138.244, - "placeopt__timing__setup__ws": -1.40307, - "run__flow__design": "aes", - "run__flow__generate_date": "2024-06-12 20:48", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-14189-g54a6a251c", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "e8072ca1312ab1e9e6a7be8513064a05f42e694f", - "run__flow__scripts_commit": "950f50d2d858fb6f8e766c1c1726961ecbdf1389", - "run__flow__uuid": "8d558f29-be19-409d-a99f-67707c0e5350", - "run__flow__variant": "base", - "synth__cpu__total": 25.81, - "synth__design__instance__area__stdcell": 62242.56, - "synth__design__instance__count__stdcell": 14091.0, - "synth__mem__peak": 424944.0, - "synth__runtime__total": "0:26.63", - "total_time": "0:34:36.320000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/aes/rules-base.json b/flow/designs/tsmc65lp/aes/rules-base.json deleted file mode 100644 index 8678b7bbcf..0000000000 --- a/flow/designs/tsmc65lp/aes/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 71578.95, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 87551, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 16716, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 1454, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 1454, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 455641, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.3, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 93427, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 727, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -15.33, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/ariane/config.mk b/flow/designs/tsmc65lp/ariane/config.mk deleted file mode 100644 index 2d97789c52..0000000000 --- a/flow/designs/tsmc65lp/ariane/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -export DESIGN_NAME = ariane -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w64_byte.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w64_byte_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg8_w64_byte.gds2 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 2000 1560 -export CORE_AREA = 10 12 1990 1550.4 -export PLACE_PINS_ARGS = -exclude left:0-500 -exclude left:800-1560 -exclude right:* -exclude top:* -exclude bottom:* - -export PLACE_DENSITY_LB_ADDON = 0.10 -export SKIP_PIN_SWAP = 1 - - diff --git a/flow/designs/tsmc65lp/ariane/constraint.sdc b/flow/designs/tsmc65lp/ariane/constraint.sdc deleted file mode 100644 index d37b5bb328..0000000000 --- a/flow/designs/tsmc65lp/ariane/constraint.sdc +++ /dev/null @@ -1,496 +0,0 @@ -create_clock [get_ports clk_i] -name core_clock -period 7.6 -waveform {0 3.8} -set_input_delay -clock core_clock 1.6 [get_ports clk_i] -set_input_delay -clock core_clock 1.6 [get_ports rst_ni] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[63]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[62]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[61]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[60]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[59]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[58]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[57]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[56]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[55]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[54]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[53]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[52]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[51]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[50]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[49]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[48]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[47]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[46]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[45]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[44]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[43]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[42]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[41]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[40]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[39]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[38]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[37]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[36]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[35]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[34]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[33]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[32]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[31]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[30]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[29]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[28]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[27]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[26]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[25]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[24]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[23]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[22]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[21]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[20]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[19]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[18]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[17]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[16]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[15]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[14]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[13]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[12]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[11]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[10]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[9]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[8]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[7]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[6]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[5]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[4]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[3]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[2]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[1]}] -set_input_delay -clock core_clock 1.6 [get_ports {boot_addr_i[0]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[63]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[62]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[61]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[60]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[59]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[58]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[57]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[56]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[55]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[54]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[53]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[52]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[51]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[50]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[49]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[48]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[47]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[46]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[45]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[44]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[43]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[42]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[41]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[40]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[39]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[38]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[37]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[36]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[35]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[34]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[33]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[32]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[31]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[30]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[29]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[28]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[27]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[26]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[25]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[24]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[23]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[22]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[21]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[20]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[19]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[18]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[17]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[16]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[15]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[14]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[13]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[12]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[11]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[10]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[9]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[8]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[7]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[6]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[5]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[4]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[3]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[2]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[1]}] -set_input_delay -clock core_clock 1.6 [get_ports {hart_id_i[0]}] -set_input_delay -clock core_clock 1.6 [get_ports {irq_i[1]}] -set_input_delay -clock core_clock 1.6 [get_ports {irq_i[0]}] -set_input_delay -clock core_clock 1.6 [get_ports ipi_i] -set_input_delay -clock core_clock 1.6 [get_ports time_irq_i] -set_input_delay -clock core_clock 1.6 [get_ports debug_req_i] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[81]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[80]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[79]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[78]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[77]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[76]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[75]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[74]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[73]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[72]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[71]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[70]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[69]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[68]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[67]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[66]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[65]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[64]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[63]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[62]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[61]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[60]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[59]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[58]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[57]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[56]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[55]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[54]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[53]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[52]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[51]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[50]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[49]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[48]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[47]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[46]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[45]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[44]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[43]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[42]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[41]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[40]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[39]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[38]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[37]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[36]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[35]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[34]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[33]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[32]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[31]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[30]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[29]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[28]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[27]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[26]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[25]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[24]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[23]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[22]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[21]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[20]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[19]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[18]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[17]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[16]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[15]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[14]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[13]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[12]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[11]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[10]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[9]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[8]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[7]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[6]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[5]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[4]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[3]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[2]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[1]}] -set_input_delay -clock core_clock 1.6 [get_ports {axi_resp_i[0]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[277]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[276]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[275]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[274]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[273]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[272]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[271]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[270]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[269]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[268]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[267]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[266]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[265]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[264]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[263]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[262]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[261]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[260]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[259]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[258]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[257]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[256]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[255]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[254]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[253]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[252]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[251]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[250]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[249]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[248]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[247]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[246]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[245]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[244]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[243]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[242]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[241]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[240]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[239]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[238]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[237]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[236]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[235]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[234]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[233]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[232]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[231]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[230]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[229]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[228]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[227]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[226]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[225]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[224]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[223]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[222]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[221]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[220]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[219]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[218]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[217]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[216]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[215]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[214]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[213]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[212]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[211]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[210]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[209]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[208]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[207]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[206]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[205]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[204]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[203]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[202]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[201]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[200]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[199]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[198]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[197]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[196]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[195]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[194]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[193]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[192]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[191]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[190]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[189]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[188]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[187]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[186]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[185]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[184]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[183]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[182]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[181]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[180]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[179]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[178]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[177]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[176]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[175]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[174]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[173]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[172]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[171]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[170]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[169]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[168]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[167]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[166]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[165]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[164]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[163]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[162]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[161]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[160]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[159]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[158]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[157]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[156]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[155]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[154]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[153]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[152]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[151]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[150]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[149]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[148]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[147]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[146]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[145]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[144]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[143]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[142]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[141]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[140]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[139]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[138]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[137]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[136]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[135]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[134]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[133]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[132]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[131]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[130]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[129]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[128]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[127]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[126]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[125]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[124]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[123]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[122]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[121]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[120]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[119]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[118]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[117]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[116]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[115]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[114]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[113]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[112]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[111]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[110]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[109]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[108]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[107]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[106]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[105]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[104]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[103]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[102]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[101]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[100]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[99]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[98]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[97]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[96]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[95]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[94]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[93]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[92]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[91]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[90]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[89]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[88]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[87]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[86]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[85]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[84]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[83]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[82]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[81]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[80]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[79]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[78]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[77]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[76]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[75]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[74]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[73]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[72]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[71]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[70]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[69]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[68]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[67]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[66]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[65]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[64]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[63]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[62]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[61]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[60]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[59]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[58]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[57]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[56]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[55]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[54]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[53]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[52]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[51]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[50]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[49]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[48]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[47]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[46]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[45]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[44]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[43]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[42]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[41]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[40]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[39]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[38]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[37]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[36]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[35]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[34]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[33]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[32]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[31]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[30]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[29]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[28]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[27]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[26]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[25]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[24]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[23]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[22]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[21]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[20]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[19]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[18]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[17]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[16]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[15]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[14]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[13]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[12]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[11]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[10]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[9]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[8]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[7]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[6]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[5]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[4]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[3]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[2]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[1]}] -set_output_delay -clock core_clock 1.6 [get_ports {axi_req_o[0]}] diff --git a/flow/designs/tsmc65lp/ariane/macros.v b/flow/designs/tsmc65lp/ariane/macros.v deleted file mode 100644 index 2e2b08b7cc..0000000000 --- a/flow/designs/tsmc65lp/ariane/macros.v +++ /dev/null @@ -1,42 +0,0 @@ -module SyncSpRamBeNx64_00000008_00000100_0_2 -( - Clk_CI, - Rst_RBI, - CSel_SI, - WrEn_SI, - BEn_SI, - WrData_DI, - Addr_DI, - RdData_DO -); - - input [7:0] BEn_SI; - input [63:0] WrData_DI; - input [7:0] Addr_DI; - output [63:0] RdData_DO; - input Clk_CI; - input Rst_RBI; - input CSel_SI; - input WrEn_SI; - wire [63:0] RdData_DO; - wire n_0_net_,n_1_net_; - - tsmc65lp_1rf_lg8_w64_byte - macro_mem - ( - .CLK(Clk_CI), - .Q(RdData_DO), - .CEN(n_0_net_), - .WEN({ BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:7], BEn_SI[7:6], BEn_SI[6:6], BEn_SI[6:6], BEn_SI[6:6], BEn_SI[6:6], BEn_SI[6:6], BEn_SI[6:6], BEn_SI[6:5], BEn_SI[5:5], BEn_SI[5:5], BEn_SI[5:5], BEn_SI[5:5], BEn_SI[5:5], BEn_SI[5:5], BEn_SI[5:4], BEn_SI[4:4], BEn_SI[4:4], BEn_SI[4:4], BEn_SI[4:4], BEn_SI[4:4], BEn_SI[4:4], BEn_SI[4:3], BEn_SI[3:3], BEn_SI[3:3], BEn_SI[3:3], BEn_SI[3:3], BEn_SI[3:3], BEn_SI[3:3], BEn_SI[3:2], BEn_SI[2:2], BEn_SI[2:2], BEn_SI[2:2], BEn_SI[2:2], BEn_SI[2:2], BEn_SI[2:2], BEn_SI[2:1], BEn_SI[1:1], BEn_SI[1:1], BEn_SI[1:1], BEn_SI[1:1], BEn_SI[1:1], BEn_SI[1:1], BEn_SI[1:0], BEn_SI[0:0], BEn_SI[0:0], BEn_SI[0:0], BEn_SI[0:0], BEn_SI[0:0], BEn_SI[0:0], BEn_SI[0:0] }), - .GWEN(n_1_net_), - .A(Addr_DI), - .D(WrData_DI), - .EMA({ 1'b0, 1'b1, 1'b1 }), - .EMAW({ 1'b0, 1'b1 }), - .RET1N(1'b1) - ); - - assign n_1_net_ = ~WrEn_SI; - assign n_0_net_ = ~CSel_SI; - -endmodule diff --git a/flow/designs/tsmc65lp/ariane/metadata-base-ok.json b/flow/designs/tsmc65lp/ariane/metadata-base-ok.json deleted file mode 100644 index 0ef57f9293..0000000000 --- a/flow/designs/tsmc65lp/ariane/metadata-base-ok.json +++ /dev/null @@ -1,309 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 7.6000" - ], - "cts__clock__skew__hold": 2.4306, - "cts__clock__skew__setup": 6.48716, - "cts__cpu__total": 31336.47, - "cts__design__core__area": 3046030.0, - "cts__design__die__area": 3120000.0, - "cts__design__instance__area": 1904640.0, - "cts__design__instance__area__macros": 665405, - "cts__design__instance__area__stdcell": 1239240.0, - "cts__design__instance__count": 163758, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 37, - "cts__design__instance__count__setup_buffer": 517, - "cts__design__instance__count__stdcell": 163721, - "cts__design__instance__displacement__max": 26.9595, - "cts__design__instance__displacement__mean": 0.073, - "cts__design__instance__displacement__total": 12031.5, - "cts__design__instance__utilization": 0.625287, - "cts__design__instance__utilization__stdcell": 0.520552, - "cts__design__io": 495, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 1434528.0, - "cts__power__internal__total": 0.0940442, - "cts__power__leakage__total": 0.00115445, - "cts__power__switching__total": 0.0953247, - "cts__power__total": 0.190523, - "cts__route__wirelength__estimated": 6766280.0, - "cts__runtime__total": "8:43:10", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.00457863, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 6, - "cts__timing__drv__max_slew_limit": -0.00159176, - "cts__timing__drv__setup_violation_count": 6173, - "cts__timing__setup__tns": -5178.92, - "cts__timing__setup__ws": -2.14609, - "design__io__hpwl": 617014750, - "detailedplace__cpu__total": 178.64, - "detailedplace__design__core__area": 3046030.0, - "detailedplace__design__die__area": 3120000.0, - "detailedplace__design__instance__area": 1874420.0, - "detailedplace__design__instance__area__macros": 665405, - "detailedplace__design__instance__area__stdcell": 1209020.0, - "detailedplace__design__instance__count": 160911, - "detailedplace__design__instance__count__macros": 37, - "detailedplace__design__instance__count__stdcell": 160874, - "detailedplace__design__instance__displacement__max": 117.555, - "detailedplace__design__instance__displacement__mean": 2.67, - "detailedplace__design__instance__displacement__total": 429701, - "detailedplace__design__instance__utilization": 0.615365, - "detailedplace__design__instance__utilization__stdcell": 0.507857, - "detailedplace__design__io": 495, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 1376528.0, - "detailedplace__power__internal__total": 0.0788767, - "detailedplace__power__leakage__total": 0.000956605, - "detailedplace__power__switching__total": 0.0788735, - "detailedplace__power__total": 0.158707, - "detailedplace__route__wirelength__estimated": 6630190.0, - "detailedplace__runtime__total": "3:02.22", - "detailedplace__timing__drv__hold_violation_count": 51, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.00527835, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 71, - "detailedplace__timing__drv__max_slew_limit": -0.396561, - "detailedplace__timing__drv__setup_violation_count": 8107, - "detailedplace__timing__setup__tns": -25796.7, - "detailedplace__timing__setup__ws": -8.54829, - "detailedroute__cpu__total": 8604.12, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 10805572.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 76117, - "detailedroute__route__drc_errors__iter:2": 1862, - "detailedroute__route__drc_errors__iter:3": 646, - "detailedroute__route__drc_errors__iter:4": 21, - "detailedroute__route__drc_errors__iter:5": 2, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 0, - "detailedroute__route__net": 151351, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1246081, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1246081, - "detailedroute__route__wirelength": 8538822, - "detailedroute__route__wirelength__iter:1": 8562178, - "detailedroute__route__wirelength__iter:2": 8541035, - "detailedroute__route__wirelength__iter:3": 8538864, - "detailedroute__route__wirelength__iter:4": 8538832, - "detailedroute__route__wirelength__iter:5": 8538823, - "detailedroute__route__wirelength__iter:6": 8538822, - "detailedroute__route__wirelength__iter:7": 8538822, - "detailedroute__route__wirelength__iter:8": 8538822, - "detailedroute__runtime__total": "5:09.24", - "fillcell__cpu__total": 6.26, - "fillcell__mem__peak": 973680.0, - "fillcell__runtime__total": "0:07.00", - "finish__clock__skew__hold": 2.35245, - "finish__clock__skew__setup": 5.52697, - "finish__cpu__total": 298.28, - "finish__design__core__area": 3046030.0, - "finish__design__die__area": 3120000.0, - "finish__design__instance__area": 1906740.0, - "finish__design__instance__area__macros": 665405, - "finish__design__instance__area__stdcell": 1241330.0, - "finish__design__instance__count": 163903, - "finish__design__instance__count__macros": 37, - "finish__design__instance__count__stdcell": 163866, - "finish__design__instance__utilization": 0.625974, - "finish__design__instance__utilization__stdcell": 0.52143, - "finish__design__io": 495, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 2660108.0, - "finish__power__internal__total": 0.0940152, - "finish__power__leakage__total": 0.00115833, - "finish__power__switching__total": 0.0775181, - "finish__power__total": 0.172692, - "finish__runtime__total": "5:02.22", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.224209, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.246257, - "finish__timing__drv__setup_violation_count": 5154, - "finish__timing__setup__tns": -3916.91, - "finish__timing__setup__ws": -2.23193, - "finish__timing__wns_percent_delay": -20.701585, - "finish_merge__cpu__total": 40.45, - "finish_merge__mem__peak": 1972604.0, - "finish_merge__runtime__total": "0:41.76", - "floorplan__cpu__total": 50.13, - "floorplan__design__core__area": 3046030.0, - "floorplan__design__die__area": 3120000.0, - "floorplan__design__instance__area": 1585000.0, - "floorplan__design__instance__area__macros": 665405, - "floorplan__design__instance__area__stdcell": 919592, - "floorplan__design__instance__count": 138036, - "floorplan__design__instance__count__macros": 37, - "floorplan__design__instance__count__stdcell": 137999, - "floorplan__design__instance__utilization": 0.520348, - "floorplan__design__instance__utilization__stdcell": 0.386281, - "floorplan__design__io": 495, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 1, - "floorplan__mem__peak": 974648.0, - "floorplan__power__internal__total": 0.0695563, - "floorplan__power__leakage__total": 0.000765879, - "floorplan__power__switching__total": 0.0243343, - "floorplan__power__total": 0.0946564, - "floorplan__runtime__total": "0:51.53", - "floorplan__timing__setup__tns": -637531, - "floorplan__timing__setup__ws": -49.0027, - "floorplan_io__cpu__total": 3.87, - "floorplan_io__mem__peak": 561908.0, - "floorplan_io__runtime__total": "0:04.28", - "floorplan_macro__cpu__total": 1658.06, - "floorplan_macro__mem__peak": 1261356.0, - "floorplan_macro__runtime__total": "4:48.33", - "floorplan_pdn__cpu__total": 15.45, - "floorplan_pdn__mem__peak": 944760.0, - "floorplan_pdn__runtime__total": "0:16.21", - "floorplan_tap__cpu__total": 7.72, - "floorplan_tap__mem__peak": 466948.0, - "floorplan_tap__runtime__total": "0:08.11", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 15287.46, - "globalplace__design__core__area": 3046030.0, - "globalplace__design__die__area": 3120000.0, - "globalplace__design__instance__area": 1598650.0, - "globalplace__design__instance__area__macros": 665405, - "globalplace__design__instance__area__stdcell": 933249, - "globalplace__design__instance__count": 152262, - "globalplace__design__instance__count__macros": 37, - "globalplace__design__instance__count__stdcell": 152225, - "globalplace__design__instance__utilization": 0.524832, - "globalplace__design__instance__utilization__stdcell": 0.392018, - "globalplace__design__io": 495, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 2303888.0, - "globalplace__power__internal__total": 0.0835031, - "globalplace__power__leakage__total": 0.000765879, - "globalplace__power__switching__total": 0.0648692, - "globalplace__power__total": 0.149138, - "globalplace__runtime__total": "20:59.04", - "globalplace__timing__setup__tns": -1987960.0, - "globalplace__timing__setup__ws": -154.445, - "globalplace_io__cpu__total": 4.13, - "globalplace_io__mem__peak": 590636.0, - "globalplace_io__runtime__total": "0:04.55", - "globalplace_skip_io__cpu__total": 3.77, - "globalplace_skip_io__mem__peak": 473796.0, - "globalplace_skip_io__runtime__total": "0:04.11", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 2.45999, - "globalroute__clock__skew__setup": 6.77853, - "globalroute__cpu__total": 658.66, - "globalroute__design__core__area": 3046030.0, - "globalroute__design__die__area": 3120000.0, - "globalroute__design__instance__area": 1906740.0, - "globalroute__design__instance__area__macros": 665405, - "globalroute__design__instance__area__stdcell": 1241330.0, - "globalroute__design__instance__count": 163903, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 37, - "globalroute__design__instance__count__setup_buffer": 8, - "globalroute__design__instance__count__stdcell": 163866, - "globalroute__design__instance__displacement__max": 19.8, - "globalroute__design__instance__displacement__mean": 0.01, - "globalroute__design__instance__displacement__total": 1694.2, - "globalroute__design__instance__utilization": 0.625974, - "globalroute__design__instance__utilization__stdcell": 0.52143, - "globalroute__design__io": 495, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 3918248.0, - "globalroute__power__internal__total": 0.0943184, - "globalroute__power__leakage__total": 0.00115833, - "globalroute__power__switching__total": 0.101089, - "globalroute__power__total": 0.196566, - "globalroute__route__wirelength__estimated": 6795620.0, - "globalroute__runtime__total": "11:03.68", - "globalroute__timing__clock__slack": -3.416, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.00944054, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 18, - "globalroute__timing__drv__max_slew_limit": -0.0153172, - "globalroute__timing__drv__setup_violation_count": 7722, - "globalroute__timing__setup__tns": -13199.7, - "globalroute__timing__setup__ws": -3.41587, - "placeopt__cpu__total": 139.83, - "placeopt__design__core__area": 3046030.0, - "placeopt__design__die__area": 3120000.0, - "placeopt__design__instance__area": 1874420.0, - "placeopt__design__instance__area__macros": 665405, - "placeopt__design__instance__area__stdcell": 1209020.0, - "placeopt__design__instance__count": 160911, - "placeopt__design__instance__count__macros": 37, - "placeopt__design__instance__count__stdcell": 160874, - "placeopt__design__instance__utilization": 0.615365, - "placeopt__design__instance__utilization__stdcell": 0.507857, - "placeopt__design__io": 495, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 1146232.0, - "placeopt__power__internal__total": 0.0788831, - "placeopt__power__leakage__total": 0.000956605, - "placeopt__power__switching__total": 0.0779795, - "placeopt__power__total": 0.157819, - "placeopt__runtime__total": "2:21.59", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 67, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0287868, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.000551724, - "placeopt__timing__drv__setup_violation_count": 7947, - "placeopt__timing__setup__tns": -25208.9, - "placeopt__timing__setup__ws": -8.44209, - "run__flow__design": "ariane", - "run__flow__generate_date": "2024-06-03 23:11", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-14005-gf37c24a6c", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "e8072ca1312ab1e9e6a7be8513064a05f42e694f", - "run__flow__scripts_commit": "15f799d73dad9cc97797c14e936a80aa0582d658", - "run__flow__uuid": "6fa11163-d25b-4ffc-91bb-6f8d9e8a32a9", - "run__flow__variant": "base", - "synth__cpu__total": 1190.18, - "synth__design__instance__area__stdcell": 1655787.305, - "synth__design__instance__count__stdcell": 155654.0, - "synth__mem__peak": 1437000.0, - "synth__runtime__total": "21:43.32", - "total_time": "9:59:37.190000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/ariane/metadata-hier_rtlmp-ok.json b/flow/designs/tsmc65lp/ariane/metadata-hier_rtlmp-ok.json deleted file mode 100644 index 16833a910c..0000000000 --- a/flow/designs/tsmc65lp/ariane/metadata-hier_rtlmp-ok.json +++ /dev/null @@ -1,300 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 7.6000" - ], - "cts__clock__skew__hold": 1.6248, - "cts__clock__skew__hold__post_repair": 0.7765, - "cts__clock__skew__hold__pre_repair": 0.7765, - "cts__clock__skew__setup": 6.7333, - "cts__clock__skew__setup__post_repair": 6.7725, - "cts__clock__skew__setup__pre_repair": 6.7725, - "cts__design__instance__area": 1906294.0, - "cts__design__instance__area__macros": 665405.25, - "cts__design__instance__area__macros__post_repair": 665405.25, - "cts__design__instance__area__macros__pre_repair": 665405.25, - "cts__design__instance__area__post_repair": 1890883.125, - "cts__design__instance__area__pre_repair": 1890866.875, - "cts__design__instance__area__stdcell": 1240888.75, - "cts__design__instance__area__stdcell__post_repair": 1225477.875, - "cts__design__instance__area__stdcell__pre_repair": 1225461.625, - "cts__design__instance__count": 164351, - "cts__design__instance__count__hold_buffer": 1984.0, - "cts__design__instance__count__macros": 37, - "cts__design__instance__count__macros__post_repair": 37, - "cts__design__instance__count__macros__pre_repair": 37, - "cts__design__instance__count__post_repair": 162159, - "cts__design__instance__count__pre_repair": 162158, - "cts__design__instance__count__setup_buffer": 208.0, - "cts__design__instance__count__stdcell": 164314, - "cts__design__instance__count__stdcell__post_repair": 162122, - "cts__design__instance__count__stdcell__pre_repair": 162121, - "cts__design__instance__displacement__max": 108.2, - "cts__design__instance__displacement__mean": 0.6715, - "cts__design__instance__displacement__total": 110433.7195, - "cts__design__instance__utilization": 0.643, - "cts__design__instance__utilization__post_repair": 0.6378, - "cts__design__instance__utilization__pre_repair": 0.6378, - "cts__design__instance__utilization__stdcell": 0.5397, - "cts__design__instance__utilization__stdcell__post_repair": 0.533, - "cts__design__instance__utilization__stdcell__pre_repair": 0.533, - "cts__design__io": 495, - "cts__design__io__post_repair": 495, - "cts__design__io__pre_repair": 495, - "cts__design__violations": 0, - "cts__power__internal__total": 0.0667, - "cts__power__internal__total__post_repair": 0.0664, - "cts__power__internal__total__pre_repair": 0.0663, - "cts__power__leakage__total": 0.0009, - "cts__power__leakage__total__post_repair": 0.0009, - "cts__power__leakage__total__pre_repair": 0.0009, - "cts__power__switching__total": 0.0548, - "cts__power__switching__total__post_repair": 0.0544, - "cts__power__switching__total__pre_repair": 0.0544, - "cts__power__total": 0.1225, - "cts__power__total__post_repair": 0.1216, - "cts__power__total__pre_repair": 0.1216, - "cts__route__wirelength__estimated": 7146400.682, - "cts__timing__drv__hold_violation_count": 1, - "cts__timing__drv__hold_violation_count__post_repair": 2, - "cts__timing__drv__hold_violation_count__pre_repair": 2, - "cts__timing__drv__max_cap": 6, - "cts__timing__drv__max_cap__post_repair": 6, - "cts__timing__drv__max_cap__pre_repair": 6, - "cts__timing__drv__max_cap_limit": -0.068, - "cts__timing__drv__max_cap_limit__post_repair": -0.0584, - "cts__timing__drv__max_cap_limit__pre_repair": -0.0584, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 1.0000000150474662e+30, - "cts__timing__drv__max_fanout_limit__post_repair": 1.0000000150474662e+30, - "cts__timing__drv__max_fanout_limit__pre_repair": 1.0000000150474662e+30, - "cts__timing__drv__max_slew": 150, - "cts__timing__drv__max_slew__post_repair": 90, - "cts__timing__drv__max_slew__pre_repair": 90, - "cts__timing__drv__max_slew_limit": -0.0509, - "cts__timing__drv__max_slew_limit__post_repair": -0.0385, - "cts__timing__drv__max_slew_limit__pre_repair": -0.0385, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__drv__setup_violation_count__post_repair": 1, - "cts__timing__drv__setup_violation_count__pre_repair": 1, - "cts__timing__setup__tns": -8901.4004, - "cts__timing__setup__tns__post_repair": -34720.3984, - "cts__timing__setup__tns__pre_repair": -34719.5703, - "cts__timing__setup__ws": -3.35, - "cts__timing__setup__ws__post_repair": -9.53, - "cts__timing__setup__ws__pre_repair": -9.53, - "detailedplace__cpu__total": 135.12, - "detailedplace__design__instance__area": 1885620.375, - "detailedplace__design__instance__area__macros": 665405.25, - "detailedplace__design__instance__area__stdcell": 1220215.25, - "detailedplace__design__instance__count": 161065, - "detailedplace__design__instance__count__macros": 37, - "detailedplace__design__instance__count__stdcell": 161028, - "detailedplace__design__instance__displacement__max": 68.9, - "detailedplace__design__instance__displacement__mean": 3.2385, - "detailedplace__design__instance__displacement__total": 521637.6915, - "detailedplace__design__instance__utilization": 0.6361, - "detailedplace__design__instance__utilization__stdcell": 0.5307, - "detailedplace__design__io": 495, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 1326264.0, - "detailedplace__power__internal__total": 0.0644, - "detailedplace__power__leakage__total": 0.0009, - "detailedplace__power__switching__total": 0.0425, - "detailedplace__power__total": 0.1078, - "detailedplace__route__wirelength__estimated": 6969952.983, - "detailedplace__runtime__total": "2:17.84", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 6, - "detailedplace__timing__drv__max_cap_limit": -0.0584, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 1.0000000150474662e+30, - "detailedplace__timing__drv__max_slew": 90, - "detailedplace__timing__drv__max_slew_limit": -0.0385, - "detailedplace__timing__drv__setup_violation_count": 1, - "detailedplace__timing__setup__tns": -33815.8086, - "detailedplace__timing__setup__ws": -9.5, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 99277, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 17011, - "detailedroute__route__drc_errors__iter:3": 15686, - "detailedroute__route__drc_errors__iter:4": 357, - "detailedroute__route__drc_errors__iter:5": 95, - "detailedroute__route__drc_errors__iter:6": 33, - "detailedroute__route__drc_errors__iter:7": 16, - "detailedroute__route__drc_errors__iter:8": 8, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 153036, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1310388, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1310388, - "detailedroute__route__wirelength": 9066497, - "detailedroute__route__wirelength__iter:1": 9111302, - "detailedroute__route__wirelength__iter:10": 9066497, - "detailedroute__route__wirelength__iter:11": 9066497, - "detailedroute__route__wirelength__iter:2": 9079867, - "detailedroute__route__wirelength__iter:3": 9066986, - "detailedroute__route__wirelength__iter:4": 9066542, - "detailedroute__route__wirelength__iter:5": 9066510, - "detailedroute__route__wirelength__iter:6": 9066505, - "detailedroute__route__wirelength__iter:7": 9066496, - "detailedroute__route__wirelength__iter:8": 9066497, - "detailedroute__route__wirelength__iter:9": 9066497, - "finish__clock__skew__hold": 1.5339, - "finish__clock__skew__setup": 4.9475, - "finish__cpu__total": 302.22, - "finish__design__instance__area": 1906294.0, - "finish__design__instance__area__macros": 665405.25, - "finish__design__instance__area__stdcell": 1240888.75, - "finish__design__instance__count": 164351, - "finish__design__instance__count__macros": 37, - "finish__design__instance__count__stdcell": 164314, - "finish__design__instance__utilization": 0.643, - "finish__design__instance__utilization__stdcell": 0.5397, - "finish__design__io": 495, - "finish__mem__peak": 3228916.0, - "finish__power__internal__total": 0.067, - "finish__power__leakage__total": 0.0009, - "finish__power__switching__total": 0.0358, - "finish__power__total": 0.1037, - "finish__runtime__total": "5:05.19", - "finish__timing__drv__hold_violation_count": 1.0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.1608, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 1.0000000150474662e+30, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.0847, - "finish__timing__drv__setup_violation_count": 1.0, - "finish__timing__setup__tns": -4772.8701, - "finish__timing__setup__ws": -2.23, - "finish__timing__wns_percent_delay": -19.818674, - "floorplan__cpu__total": 5430.03, - "floorplan__design__instance__area": 1618176.875, - "floorplan__design__instance__area__macros": 665405.25, - "floorplan__design__instance__area__stdcell": 952771.6875, - "floorplan__design__instance__count": 138131, - "floorplan__design__instance__count__macros": 37, - "floorplan__design__instance__count__stdcell": 138094, - "floorplan__design__instance__utilization": 0.5459, - "floorplan__design__instance__utilization__stdcell": 0.4144, - "floorplan__design__io": 495, - "floorplan__mem__peak": 27500544.0, - "floorplan__power__internal__total": 0.0655, - "floorplan__power__leakage__total": 0.0007, - "floorplan__power__switching__total": 0.0129, - "floorplan__power__total": 0.0791, - "floorplan__runtime__total": "15:35.93", - "floorplan__timing__setup__tns": -403388.1875, - "floorplan__timing__setup__ws": -43.37, - "globalplace__design__instance__area": 1631485.375, - "globalplace__design__instance__area__macros": 665405.25, - "globalplace__design__instance__area__stdcell": 966080.1875, - "globalplace__design__instance__count": 151994, - "globalplace__design__instance__count__macros": 37, - "globalplace__design__instance__count__stdcell": 151957, - "globalplace__design__instance__utilization": 0.5503, - "globalplace__design__instance__utilization__stdcell": 0.4202, - "globalplace__design__io": 495, - "globalplace__power__internal__total": 0.0735, - "globalplace__power__leakage__total": 0.0007, - "globalplace__power__switching__total": 0.0369, - "globalplace__power__total": 0.1111, - "globalplace__timing__setup__tns": -1086792.875, - "globalplace__timing__setup__ws": -113.65, - "globalroute__clock__skew__hold": 1.6847, - "globalroute__clock__skew__setup": 6.9806, - "globalroute__design__instance__area": 1906294.0, - "globalroute__design__instance__area__macros": 665405.25, - "globalroute__design__instance__area__stdcell": 1240888.75, - "globalroute__design__instance__count": 164351, - "globalroute__design__instance__count__macros": 37, - "globalroute__design__instance__count__stdcell": 164314, - "globalroute__design__instance__utilization": 0.643, - "globalroute__design__instance__utilization__stdcell": 0.5397, - "globalroute__design__io": 495, - "globalroute__power__internal__total": 0.0671, - "globalroute__power__leakage__total": 0.0009, - "globalroute__power__switching__total": 0.0579, - "globalroute__power__total": 0.1259, - "globalroute__timing__clock__slack": -4.414, - "globalroute__timing__drv__hold_violation_count": 1, - "globalroute__timing__drv__max_cap": 6, - "globalroute__timing__drv__max_cap_limit": -0.0387, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 1.0000000150474662e+30, - "globalroute__timing__drv__max_slew": 450, - "globalroute__timing__drv__max_slew_limit": -0.2216, - "globalroute__timing__drv__setup_violation_count": 1, - "globalroute__timing__setup__tns": -13993.8604, - "globalroute__timing__setup__ws": -4.41, - "placeopt__cpu__total": 140.63, - "placeopt__design__instance__area": 1885620.375, - "placeopt__design__instance__area__macros": 665405.25, - "placeopt__design__instance__area__macros__pre_opt": 665405.25, - "placeopt__design__instance__area__pre_opt": 1631485.375, - "placeopt__design__instance__area__stdcell": 1220215.25, - "placeopt__design__instance__area__stdcell__pre_opt": 966080.1875, - "placeopt__design__instance__count": 161065, - "placeopt__design__instance__count__macros": 37, - "placeopt__design__instance__count__macros__pre_opt": 37, - "placeopt__design__instance__count__pre_opt": 151994, - "placeopt__design__instance__count__stdcell": 161028, - "placeopt__design__instance__count__stdcell__pre_opt": 151957, - "placeopt__design__instance__utilization": 0.6361, - "placeopt__design__instance__utilization__pre_opt": 0.5503, - "placeopt__design__instance__utilization__stdcell": 0.5307, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.4202, - "placeopt__design__io": 495, - "placeopt__design__io__pre_opt": 495, - "placeopt__mem__peak": 1259136.0, - "placeopt__power__internal__total": 0.0635, - "placeopt__power__internal__total__pre_opt": 0.0735, - "placeopt__power__leakage__total": 0.0009, - "placeopt__power__leakage__total__pre_opt": 0.0007, - "placeopt__power__switching__total": 0.0382, - "placeopt__power__switching__total__pre_opt": 0.0369, - "placeopt__power__total": 0.1026, - "placeopt__power__total__pre_opt": 0.1111, - "placeopt__runtime__total": "2:22.38", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0007, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 1.0000000150474662e+30, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0021, - "placeopt__timing__drv__setup_violation_count": 1, - "placeopt__timing__setup__tns": -31636.3691, - "placeopt__timing__setup__tns__pre_opt": -1086792.875, - "placeopt__timing__setup__ws": -9.09, - "placeopt__timing__setup__ws__pre_opt": -113.65, - "run__flow__design": "ariane", - "run__flow__generate_date": "2022-11-02 07:24", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-5470-g36e6d5d7d", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "b25f2daf0825d34d8053a13141d30ac3424479e7", - "run__flow__scripts_commit": "cdf11e99ffd6466ed81395e3cda971f5a1caffbd", - "run__flow__uuid": "d2508eeb-760c-4560-aaaa-96bcfab0ac3f", - "run__flow__variant": "hier_rtlmp", - "synth__cpu__total": 927.5, - "synth__design__instance__area__stdcell": 45412.8, - "synth__design__instance__count__stdcell": 159924.0, - "synth__mem__peak": 1480468.0, - "synth__runtime__total": "15:49.35", - "total_time": "0:41:10.690000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/ariane/rules-base.json b/flow/designs/tsmc65lp/ariane/rules-base.json deleted file mode 100644 index 7783abee8a..0000000000 --- a/flow/designs/tsmc65lp/ariane/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 1872474.47, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 2107640, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 177053, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 15396, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 15396, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 9571622, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -2.61, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 2140978, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 7698, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -26.97, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/black_parrot/config.mk b/flow/designs/tsmc65lp/black_parrot/config.mk deleted file mode 100644 index 62c0998b62..0000000000 --- a/flow/designs/tsmc65lp/black_parrot/config.mk +++ /dev/null @@ -1,43 +0,0 @@ -export DESIGN_NICKNAME = bp -export DESIGN_NAME = black_parrot -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 -# -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w96_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_all.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w16_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w8_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w96_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w96_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_all_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w16_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w8_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w96_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg8_w96_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_all.gds2 - -export DIE_AREA = 0 0 1800 1600.8 -export CORE_AREA = 10 12 1790 1591.2 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.10 diff --git a/flow/designs/tsmc65lp/black_parrot/constraint.sdc b/flow/designs/tsmc65lp/black_parrot/constraint.sdc deleted file mode 100644 index c07e539358..0000000000 --- a/flow/designs/tsmc65lp/black_parrot/constraint.sdc +++ /dev/null @@ -1,2405 +0,0 @@ -set clk_name CLK -set clk_port_name clk_i -set clk_period 6.84 -set clk_io_pct 0.2 - -set offset [expr $clk_period * $clk_io_pct] - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port_name - -set_input_delay -clock CLK -max 3.42 [get_ports reset_i] -set_input_delay -clock CLK -min $offset [get_ports reset_i] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min $offset [get_ports {mem_data_resp_v_i[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 3.42 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min $offset [get_ports {mem_data_resp_ready_o[0]}] diff --git a/flow/designs/tsmc65lp/black_parrot/macros.v b/flow/designs/tsmc65lp/black_parrot/macros.v deleted file mode 100644 index b00c1c0a97..0000000000 --- a/flow/designs/tsmc65lp/black_parrot/macros.v +++ /dev/null @@ -1,292 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w15_wrapper #( parameter width_p = 15 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w15 - // mem - // ( ... - // ); - - wire [15:0] Q; - wire [15:0] D; - wire [15:0] WEN; - - assign data_o = Q[14:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w16_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN ), - .GWEN (~w_i ), // lo true - .A (addr_i), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w7_wrapper #( parameter width_p = 7 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w7 - // mem - // ( ... - // ); - - wire [7:0] Q; - wire [7:0] D; - wire [7:0] WEN; - - assign data_o = Q[6:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w8_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w96 - // mem - // ( ... - // ); - - - tsmc65lp_1rf_lg6_w96_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (w_mask_i), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_byte_mask_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - , parameter write_mask_width_lp = width_p>>3 - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [write_mask_width_lp-1:0] write_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_byte_mask_d512_w64 - // mem - // ( ... - // ); - - wire [63:0] wen = ~{{8{write_mask_i[7]}} - ,{8{write_mask_i[6]}} - ,{8{write_mask_i[5]}} - ,{8{write_mask_i[4]}} - ,{8{write_mask_i[3]}} - ,{8{write_mask_i[2]}} - ,{8{write_mask_i[1]}} - ,{8{write_mask_i[0]}}}; - - tsmc65lp_1rf_lg9_w64_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (wen), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_d256_w95_wrapper #( parameter width_p = 95 - , parameter els_p = 256 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input v_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_d256_w95 - // mem - // ( ... - // ); - - - wire [95:0] Q; - wire [95:0] D; - wire [95:0] WEN; - - assign data_o = Q[94:0]; - assign D = {1'b0,data_i}; - - tsmc65lp_1rf_lg8_w96_all mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (~w_i ), // lo true - .A (addr_i ), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input v_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_d512_w64 - // mem - // ( ... - // ); - - tsmc65lp_1rf_lg9_w64_all mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - diff --git a/flow/designs/tsmc65lp/black_parrot/metadata-base-ok.json b/flow/designs/tsmc65lp/black_parrot/metadata-base-ok.json deleted file mode 100644 index 77aae4a0c8..0000000000 --- a/flow/designs/tsmc65lp/black_parrot/metadata-base-ok.json +++ /dev/null @@ -1,364 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 6.8400" - ], - "cts__clock__skew__hold": 0.18527, - "cts__clock__skew__hold__post_repair": 0.22374, - "cts__clock__skew__hold__pre_repair": 0.22374, - "cts__clock__skew__setup": 0.18527, - "cts__clock__skew__setup__post_repair": 0.22374, - "cts__clock__skew__setup__pre_repair": 0.22374, - "cts__cpu__total": 535.24, - "cts__design__core__area": 2810980.0, - "cts__design__core__area__post_repair": 2810980.0, - "cts__design__core__area__pre_repair": 2810980.0, - "cts__design__die__area": 2881440.0, - "cts__design__die__area__post_repair": 2881440.0, - "cts__design__die__area__pre_repair": 2881440.0, - "cts__design__instance__area": 1853440.0, - "cts__design__instance__area__macros": 561468, - "cts__design__instance__area__macros__post_repair": 561468, - "cts__design__instance__area__macros__pre_repair": 561468, - "cts__design__instance__area__post_repair": 1850810.0, - "cts__design__instance__area__pre_repair": 1850790.0, - "cts__design__instance__area__stdcell": 1291970.0, - "cts__design__instance__area__stdcell__post_repair": 1289340.0, - "cts__design__instance__area__stdcell__pre_repair": 1289330.0, - "cts__design__instance__count": 159819, - "cts__design__instance__count__hold_buffer": 133, - "cts__design__instance__count__macros": 24, - "cts__design__instance__count__macros__post_repair": 24, - "cts__design__instance__count__macros__pre_repair": 24, - "cts__design__instance__count__post_repair": 159452, - "cts__design__instance__count__pre_repair": 159451, - "cts__design__instance__count__setup_buffer": 142, - "cts__design__instance__count__stdcell": 159795, - "cts__design__instance__count__stdcell__post_repair": 159428, - "cts__design__instance__count__stdcell__pre_repair": 159427, - "cts__design__instance__displacement__max": 36.4, - "cts__design__instance__displacement__mean": 0.0415, - "cts__design__instance__displacement__total": 6697.66, - "cts__design__instance__utilization": 0.659359, - "cts__design__instance__utilization__post_repair": 0.658423, - "cts__design__instance__utilization__pre_repair": 0.658417, - "cts__design__instance__utilization__stdcell": 0.574336, - "cts__design__instance__utilization__stdcell__post_repair": 0.573166, - "cts__design__instance__utilization__stdcell__pre_repair": 0.573159, - "cts__design__io": 1198, - "cts__design__io__post_repair": 1198, - "cts__design__io__pre_repair": 1198, - "cts__design__violations": 0, - "cts__mem__peak": 1484044.0, - "cts__power__internal__total": 0.071152, - "cts__power__internal__total__post_repair": 0.0711602, - "cts__power__internal__total__pre_repair": 0.071158, - "cts__power__leakage__total": 0.0011528, - "cts__power__leakage__total__post_repair": 0.00115026, - "cts__power__leakage__total__pre_repair": 0.00115023, - "cts__power__switching__total": 0.029804, - "cts__power__switching__total__post_repair": 0.0296314, - "cts__power__switching__total__pre_repair": 0.0295944, - "cts__power__total": 0.102109, - "cts__power__total__post_repair": 0.101942, - "cts__power__total__pre_repair": 0.101903, - "cts__route__wirelength__estimated": 7194930.0, - "cts__runtime__total": "8:59.28", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 193, - "cts__timing__drv__hold_violation_count__pre_repair": 193, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.0222132, - "cts__timing__drv__max_cap_limit__post_repair": 0.0222281, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0222281, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.0104695, - "cts__timing__drv__max_slew_limit__post_repair": 0.00898528, - "cts__timing__drv__max_slew_limit__pre_repair": 0.00898528, - "cts__timing__drv__setup_violation_count": 51, - "cts__timing__drv__setup_violation_count__post_repair": 4180, - "cts__timing__drv__setup_violation_count__pre_repair": 4086, - "cts__timing__setup__tns": -1.75126, - "cts__timing__setup__tns__post_repair": -4269.72, - "cts__timing__setup__tns__pre_repair": -4235.19, - "cts__timing__setup__ws": -0.130712, - "cts__timing__setup__ws__post_repair": -2.29722, - "cts__timing__setup__ws__pre_repair": -2.29724, - "design__io__hpwl": 2289315288, - "detailedplace__cpu__total": 145.06, - "detailedplace__design__core__area": 2810980.0, - "detailedplace__design__die__area": 2881440.0, - "detailedplace__design__instance__area": 1823200.0, - "detailedplace__design__instance__area__macros": 561468, - "detailedplace__design__instance__area__stdcell": 1261730.0, - "detailedplace__design__instance__count": 157760, - "detailedplace__design__instance__count__macros": 24, - "detailedplace__design__instance__count__stdcell": 157736, - "detailedplace__design__instance__displacement__max": 54.3125, - "detailedplace__design__instance__displacement__mean": 3.0675, - "detailedplace__design__instance__displacement__total": 483950, - "detailedplace__design__instance__utilization": 0.648599, - "detailedplace__design__instance__utilization__stdcell": 0.560891, - "detailedplace__design__io": 1198, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 1372020.0, - "detailedplace__power__internal__total": 0.0505857, - "detailedplace__power__leakage__total": 0.000898809, - "detailedplace__power__switching__total": 0.00610378, - "detailedplace__power__total": 0.0575883, - "detailedplace__route__wirelength__estimated": 7152670.0, - "detailedplace__runtime__total": "2:27.93", - "detailedplace__timing__drv__hold_violation_count": 119, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0222281, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.00902498, - "detailedplace__timing__drv__setup_violation_count": 7055, - "detailedplace__timing__setup__tns": -6416.49, - "detailedplace__timing__setup__ws": -2.25301, - "detailedroute__cpu__total": 12282.55, - "detailedroute__mem__peak": 10898036.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 74876, - "detailedroute__route__drc_errors__iter:2": 5131, - "detailedroute__route__drc_errors__iter:3": 3089, - "detailedroute__route__drc_errors__iter:4": 27, - "detailedroute__route__drc_errors__iter:5": 6, - "detailedroute__route__drc_errors__iter:6": 2, - "detailedroute__route__drc_errors__iter:7": 2, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 149650, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 1155737, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 1155737, - "detailedroute__route__wirelength": 8922460, - "detailedroute__route__wirelength__iter:1": 8946240, - "detailedroute__route__wirelength__iter:2": 8927650, - "detailedroute__route__wirelength__iter:3": 8922846, - "detailedroute__route__wirelength__iter:4": 8922464, - "detailedroute__route__wirelength__iter:5": 8922460, - "detailedroute__route__wirelength__iter:6": 8922461, - "detailedroute__route__wirelength__iter:7": 8922460, - "detailedroute__route__wirelength__iter:8": 8922460, - "detailedroute__route__wirelength__iter:9": 8922460, - "detailedroute__runtime__total": "6:15.79", - "fillcell__cpu__total": 6.46, - "fillcell__mem__peak": 1003068.0, - "fillcell__runtime__total": "0:07.24", - "finish__clock__skew__hold": 0.168891, - "finish__clock__skew__setup": 0.168891, - "finish__cpu__total": 199.47, - "finish__design__core__area": 2810980.0, - "finish__design__die__area": 2881440.0, - "finish__design__instance__area": 1884610.0, - "finish__design__instance__area__macros": 561468, - "finish__design__instance__area__stdcell": 1323140.0, - "finish__design__instance__count": 160166, - "finish__design__instance__count__macros": 24, - "finish__design__instance__count__stdcell": 160142, - "finish__design__instance__utilization": 0.670446, - "finish__design__instance__utilization__stdcell": 0.588191, - "finish__design__io": 1198, - "finish__mem__peak": 2877872.0, - "finish__power__internal__total": 0.0711599, - "finish__power__leakage__total": 0.00117411, - "finish__power__switching__total": 0.0248554, - "finish__power__total": 0.0971894, - "finish__runtime__total": "3:22.54", - "finish__timing__drv__hold_violation_count": 182, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.359342, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.228515, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.35941, - "finish__timing__wns_percent_delay": 5.177182, - "finish_merge__cpu__total": 45.78, - "finish_merge__mem__peak": 2014920.0, - "finish_merge__runtime__total": "0:47.11", - "floorplan__cpu__total": 38.09, - "floorplan__design__core__area": 2810980.0, - "floorplan__design__die__area": 2881440.0, - "floorplan__design__instance__area": 1507950.0, - "floorplan__design__instance__area__macros": 561468, - "floorplan__design__instance__area__stdcell": 946480, - "floorplan__design__instance__count": 133066, - "floorplan__design__instance__count__macros": 24, - "floorplan__design__instance__count__stdcell": 133042, - "floorplan__design__instance__utilization": 0.53645, - "floorplan__design__instance__utilization__stdcell": 0.42075, - "floorplan__design__io": 1198, - "floorplan__mem__peak": 964288.0, - "floorplan__power__internal__total": 0.05588, - "floorplan__power__leakage__total": 0.000679272, - "floorplan__power__switching__total": 0.00196912, - "floorplan__power__total": 0.0585284, - "floorplan__runtime__total": "0:39.00", - "floorplan__timing__setup__tns": -187900, - "floorplan__timing__setup__ws": -21.9418, - "floorplan_io__cpu__total": 4.05, - "floorplan_io__mem__peak": 562276.0, - "floorplan_io__runtime__total": "0:04.46", - "floorplan_macro__cpu__total": 1447.06, - "floorplan_macro__mem__peak": 783216.0, - "floorplan_macro__runtime__total": "0:56.84", - "floorplan_pdn__cpu__total": 18.12, - "floorplan_pdn__mem__peak": 878460.0, - "floorplan_pdn__runtime__total": "0:18.87", - "floorplan_tap__cpu__total": 6.44, - "floorplan_tap__mem__peak": 471360.0, - "floorplan_tap__runtime__total": "0:06.77", - "globalplace__cpu__total": 14134.19, - "globalplace__design__core__area": 2810980.0, - "globalplace__design__die__area": 2881440.0, - "globalplace__design__instance__area": 1520120.0, - "globalplace__design__instance__area__macros": 561468, - "globalplace__design__instance__area__stdcell": 958656, - "globalplace__design__instance__count": 145750, - "globalplace__design__instance__count__macros": 24, - "globalplace__design__instance__count__stdcell": 145726, - "globalplace__design__instance__utilization": 0.540782, - "globalplace__design__instance__utilization__stdcell": 0.426163, - "globalplace__design__io": 1198, - "globalplace__mem__peak": 2284132.0, - "globalplace__power__internal__total": 0.0664584, - "globalplace__power__leakage__total": 0.000679272, - "globalplace__power__switching__total": 0.00474272, - "globalplace__power__total": 0.0718804, - "globalplace__runtime__total": "17:58.90", - "globalplace__timing__setup__tns": -849073, - "globalplace__timing__setup__ws": -108.966, - "globalplace_io__cpu__total": 4.21, - "globalplace_io__mem__peak": 596316.0, - "globalplace_io__runtime__total": "0:04.62", - "globalplace_skip_io__cpu__total": 63.28, - "globalplace_skip_io__mem__peak": 798080.0, - "globalplace_skip_io__runtime__total": "1:04.03", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.23787, - "globalroute__clock__skew__setup": 0.23787, - "globalroute__cpu__total": 1237.34, - "globalroute__design__core__area": 2810980.0, - "globalroute__design__die__area": 2881440.0, - "globalroute__design__instance__area": 1884610.0, - "globalroute__design__instance__area__macros": 561468, - "globalroute__design__instance__area__stdcell": 1323140.0, - "globalroute__design__instance__count": 160166, - "globalroute__design__instance__count__hold_buffer": 7, - "globalroute__design__instance__count__macros": 24, - "globalroute__design__instance__count__setup_buffer": 33, - "globalroute__design__instance__count__stdcell": 160142, - "globalroute__design__instance__displacement__max": 26.4, - "globalroute__design__instance__displacement__mean": 0.013, - "globalroute__design__instance__displacement__total": 2083, - "globalroute__design__instance__utilization": 0.670446, - "globalroute__design__instance__utilization__stdcell": 0.588191, - "globalroute__design__io": 1198, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 3985364.0, - "globalroute__power__internal__total": 0.0712958, - "globalroute__power__leakage__total": 0.00117388, - "globalroute__power__switching__total": 0.0321855, - "globalroute__power__total": 0.104655, - "globalroute__route__wirelength__estimated": 7302290.0, - "globalroute__runtime__total": "20:47.43", - "globalroute__timing__clock__slack": -0.764, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0077939, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 230, - "globalroute__timing__drv__max_slew_limit": -0.0943247, - "globalroute__timing__drv__setup_violation_count": 1558, - "globalroute__timing__setup__tns": -482.306, - "globalroute__timing__setup__ws": -0.764392, - "placeopt__cpu__total": 144.25, - "placeopt__design__core__area": 2810980.0, - "placeopt__design__core__area__pre_opt": 2810980.0, - "placeopt__design__die__area": 2881440.0, - "placeopt__design__die__area__pre_opt": 2881440.0, - "placeopt__design__instance__area": 1823200.0, - "placeopt__design__instance__area__macros": 561468, - "placeopt__design__instance__area__macros__pre_opt": 561468, - "placeopt__design__instance__area__pre_opt": 1520120.0, - "placeopt__design__instance__area__stdcell": 1261730.0, - "placeopt__design__instance__area__stdcell__pre_opt": 958656, - "placeopt__design__instance__count": 157760, - "placeopt__design__instance__count__macros": 24, - "placeopt__design__instance__count__macros__pre_opt": 24, - "placeopt__design__instance__count__pre_opt": 145750, - "placeopt__design__instance__count__stdcell": 157736, - "placeopt__design__instance__count__stdcell__pre_opt": 145726, - "placeopt__design__instance__utilization": 0.648599, - "placeopt__design__instance__utilization__pre_opt": 0.540782, - "placeopt__design__instance__utilization__stdcell": 0.560891, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.426163, - "placeopt__design__io": 1198, - "placeopt__design__io__pre_opt": 1198, - "placeopt__mem__peak": 1220564.0, - "placeopt__power__internal__total": 0.0496301, - "placeopt__power__internal__total__pre_opt": 0.0664584, - "placeopt__power__leakage__total": 0.000893053, - "placeopt__power__leakage__total__pre_opt": 0.000679272, - "placeopt__power__switching__total": 0.00179824, - "placeopt__power__switching__total__pre_opt": 0.00474272, - "placeopt__power__total": 0.0523214, - "placeopt__power__total__pre_opt": 0.0718804, - "placeopt__runtime__total": "2:28.81", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 119, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0103516, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0122543, - "placeopt__timing__drv__setup_violation_count": 6922, - "placeopt__timing__setup__tns": -6362.48, - "placeopt__timing__setup__tns__pre_opt": -849073, - "placeopt__timing__setup__ws": -2.27057, - "placeopt__timing__setup__ws__pre_opt": -108.966, - "run__flow__design": "bp", - "run__flow__generate_date": "2024-03-05 04:13", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-12398-gfd99002fc", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "730fc586e5c9b66fa3a4f855f18f25797b654914", - "run__flow__scripts_commit": "d2c18462ebdc019becda3570043b2ccb0ca625e2", - "run__flow__uuid": "9906d3da-84ec-438e-b0c3-d6098b850e66", - "run__flow__variant": "base", - "synth__cpu__total": 768.84, - "synth__design__instance__area__stdcell": 1588124.171, - "synth__design__instance__count__stdcell": 152225.0, - "synth__mem__peak": 2693876.0, - "synth__runtime__total": "13:18.95", - "total_time": "1:19:48.570000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/black_parrot/rules-base.json b/flow/designs/tsmc65lp/black_parrot/rules-base.json deleted file mode 100644 index 9423a8a84a..0000000000 --- a/flow/designs/tsmc65lp/black_parrot/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 1826342.8, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 2096680, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 181396, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 15774, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 15774, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 10260829, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 2138954, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 7887, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 328, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/bp_be_top/config.mk b/flow/designs/tsmc65lp/bp_be_top/config.mk deleted file mode 100644 index 937ffce750..0000000000 --- a/flow/designs/tsmc65lp/bp_be_top/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -export DESIGN_NICKNAME = bp_be -export DESIGN_NAME = bp_be_top -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 -# -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_bit.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w16_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w96_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_bit_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w16_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w96_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_bit.gds2 - -export DIE_AREA = 0 0 1000 900 -export CORE_AREA = 10 12 990 890 -export PLACE_PINS_ARGS = -exclude left:0-500 -exclude right:0-500 -exclude bottom:* - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.05 diff --git a/flow/designs/tsmc65lp/bp_be_top/constraint.sdc b/flow/designs/tsmc65lp/bp_be_top/constraint.sdc deleted file mode 100644 index 615a8ed279..0000000000 --- a/flow/designs/tsmc65lp/bp_be_top/constraint.sdc +++ /dev/null @@ -1,6058 +0,0 @@ - -create_clock [get_ports clk_i] -name CLK -period 5.4 -waveform {0 2.7} -set_input_delay -clock CLK -max 0.6 [get_ports reset_i] -set_input_delay -clock CLK -min 1.2 [get_ports reset_i] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {fe_queue_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -min 1.2 [get_ports fe_queue_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -min 1.2 [get_ports fe_cmd_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_req_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_data_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[539]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_data_cmd_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_data_cmd_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[538]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[537]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[536]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[535]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[534]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[533]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[532]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[531]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[530]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[529]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[528]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[527]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[526]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[525]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[524]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[523]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[522]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[521]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[520]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[519]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[518]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[517]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[516]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[515]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[514]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[513]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[512]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[511]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[510]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[509]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[508]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[507]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[506]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[505]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[504]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[503]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[502]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[501]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[500]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[499]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[498]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[497]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[496]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[495]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[494]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[493]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[492]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[491]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[490]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[489]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[488]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[487]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[486]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[485]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[484]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[483]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[482]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[481]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[480]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[479]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[478]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[477]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[476]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[475]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[474]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[473]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[472]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[471]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[470]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[469]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[468]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[467]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[466]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[465]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[464]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[463]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[462]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[461]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[460]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[459]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[458]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[457]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[456]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[455]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[454]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[453]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[452]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[451]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[450]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[449]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[448]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[447]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[446]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[445]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[444]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[443]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[442]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[441]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[440]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[439]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[438]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[437]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[436]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[435]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[434]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[433]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[432]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[431]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[430]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[429]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[428]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[427]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[426]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[425]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[424]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[423]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[422]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[421]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[420]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[419]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[418]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[417]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[416]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[415]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[414]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[413]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[412]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[411]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[410]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[409]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[408]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[407]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[406]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[405]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[404]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[403]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[402]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[401]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[400]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[399]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[398]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[397]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[396]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[395]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[394]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[393]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[392]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[391]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[390]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[389]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[388]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[387]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[386]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[385]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[384]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[383]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[382]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[381]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[380]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[379]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[378]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[377]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[376]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[375]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[374]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[373]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[372]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[371]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[370]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[369]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[368]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[367]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[366]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[365]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[364]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[363]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[362]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[361]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[360]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[359]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[358]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[357]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[356]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[355]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[354]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[353]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[352]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[351]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[350]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[349]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[348]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[347]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[346]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[345]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[344]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[343]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[342]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[341]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[340]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[339]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[338]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[337]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[336]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[335]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[334]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[333]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[332]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[331]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[330]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[329]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[328]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[327]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[326]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[325]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[324]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[323]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[322]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[321]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[320]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[319]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[318]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[317]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[316]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[315]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[314]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[313]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[312]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[311]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[310]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[309]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[308]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[307]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[306]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[305]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[304]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[303]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[302]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[301]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[300]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[299]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[298]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[297]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[296]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[295]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[294]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[293]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[292]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[291]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[290]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[289]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[288]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[287]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[286]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[285]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[284]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[283]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[282]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[281]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[280]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[279]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[278]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[277]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[276]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[275]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[274]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[273]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[272]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[271]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[270]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[269]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[268]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[267]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[266]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[265]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[264]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[263]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[262]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[261]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[260]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[259]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[258]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[257]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[256]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[255]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[254]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[253]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[252]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[251]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[250]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[249]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[248]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[247]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[246]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[245]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[244]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[243]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[242]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[241]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[240]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[239]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[238]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[237]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[236]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[235]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[234]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[233]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[232]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[231]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[230]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[229]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[228]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[227]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[226]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[225]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[224]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[223]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[222]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[221]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[220]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[219]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[218]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[217]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[216]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[215]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[214]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[213]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[212]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[211]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[210]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[209]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[208]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[207]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[206]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[205]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[204]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[203]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[202]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[201]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[200]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[199]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[198]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[197]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[196]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[195]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[194]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[193]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[192]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[191]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[190]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[189]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[188]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[187]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[186]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[185]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[184]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[183]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[182]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[181]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[180]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[179]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[178]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[177]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[176]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[175]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[174]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[173]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[172]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[171]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[170]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[169]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[168]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[167]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[166]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[165]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[164]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[163]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[162]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[161]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[160]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[159]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[158]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[157]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[156]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[155]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[154]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[153]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[152]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[151]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[150]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[149]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[148]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[147]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[146]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[145]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[144]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[143]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[142]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[141]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[140]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[139]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[138]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[137]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[136]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[135]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[134]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[133]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[132]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[131]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[130]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[129]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[128]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[127]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[126]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[125]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[124]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[123]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[122]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[121]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[120]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[119]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[118]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[117]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[116]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[115]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[114]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[113]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[112]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[111]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[110]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[109]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[108]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[107]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[106]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[105]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[104]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[103]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[102]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[101]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[100]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[99]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[98]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[97]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[96]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[95]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[94]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[93]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[92]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[91]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[90]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[89]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[88]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[87]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[86]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[85]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[84]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[83]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[82]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[81]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[80]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[79]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[78]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[77]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[76]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[75]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[74]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[73]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[72]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[71]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[70]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[69]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[68]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[67]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[66]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[65]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[64]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[63]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[62]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[61]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[60]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[59]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[58]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[57]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[56]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[55]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[54]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[53]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[52]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[51]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[50]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[49]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[48]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[47]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[46]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[45]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[44]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[43]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[42]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[41]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[40]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[39]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[38]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[37]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[36]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[35]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[34]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[33]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[32]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[31]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[30]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[29]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[28]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[27]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[26]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[25]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[24]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[23]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[22]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[21]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[20]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[19]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[18]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[17]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[16]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[15]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[14]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[13]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[12]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[11]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[10]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[9]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[8]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[7]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[6]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[5]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[4]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[3]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_i[0]}] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_tr_resp_v_i] -set_input_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -min 1.2 [get_ports lce_tr_resp_ready_i] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {proc_cfg_i[2]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {proc_cfg_i[1]}] -set_input_delay -clock CLK -max 0.6 [get_ports {proc_cfg_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {proc_cfg_i[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -min 1.2 [get_ports fe_queue_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -min 1.2 [get_ports fe_queue_clr_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -min 1.2 [get_ports fe_queue_dequeue_o] -set_output_delay -clock CLK -max 0.6 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -min 1.2 [get_ports fe_queue_rollback_o] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {fe_cmd_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -min 1.2 [get_ports fe_cmd_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_req_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_req_v_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_req_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_data_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_data_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_data_cmd_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_tr_resp_ready_o] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[538]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[537]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[536]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[535]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[534]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[533]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[532]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[531]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[530]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[529]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[528]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[527]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[526]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[525]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[524]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[523]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[522]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[521]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[520]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[519]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[518]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[517]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[516]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[515]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[514]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[513]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[512]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[511]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[510]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[509]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[508]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[507]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[506]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[505]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[504]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[503]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[502]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[501]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[500]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[499]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[498]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[497]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[496]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[495]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[494]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[493]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[492]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[491]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[490]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[489]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[488]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[487]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[486]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[485]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[484]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[483]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[482]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[481]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[480]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[479]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[478]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[477]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[476]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[475]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[474]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[473]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[472]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[471]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[470]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[469]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[468]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[467]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[466]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[465]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[464]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[463]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[462]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[461]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[460]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[459]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[458]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[457]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[456]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[455]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[454]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[453]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[452]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[451]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[450]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[449]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[448]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[447]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[446]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[445]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[444]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[443]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[442]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[441]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[440]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[439]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[438]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[437]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[436]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[435]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[434]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[433]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[432]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[431]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[430]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[429]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[428]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[427]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[426]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[425]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[424]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[423]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[422]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[421]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[420]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[419]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[418]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[417]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[416]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[415]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[414]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[413]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[412]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[411]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[410]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[409]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[408]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[407]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[406]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[405]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[404]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[403]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[402]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[401]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[400]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[399]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[398]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[397]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[396]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[395]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[394]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[393]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[392]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[391]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[390]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[389]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[388]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[387]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[386]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[385]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[384]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[383]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[382]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[381]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[380]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[379]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[378]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {lce_tr_resp_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -min 1.2 [get_ports lce_tr_resp_v_o] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[377]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[376]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[375]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[374]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[373]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[372]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[371]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[370]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[369]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[368]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[367]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[366]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[365]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[364]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[363]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[362]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[361]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[360]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[359]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[358]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[357]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[356]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[355]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[354]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[353]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[352]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[351]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[350]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[349]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[348]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[347]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[346]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[345]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[344]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[343]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[342]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[341]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[340]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[339]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[338]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[337]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[336]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[335]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[334]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[333]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[332]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[331]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[330]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[329]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[328]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[327]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[326]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[325]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[324]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[323]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[322]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[321]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[320]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[319]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[318]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[317]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[316]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[315]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[314]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[313]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[312]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[311]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[310]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[309]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[308]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[307]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[306]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[305]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[304]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[303]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[302]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[301]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[300]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[299]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[298]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[297]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[296]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[295]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[294]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[293]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[292]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[291]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[290]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[289]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[288]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[287]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[286]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[285]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[284]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[283]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[282]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[281]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[280]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[279]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[278]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[277]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[276]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[275]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[274]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[273]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[272]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[271]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[270]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[269]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[268]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[267]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[266]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[265]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[264]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[263]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[262]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[261]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[260]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[259]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[258]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[257]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[256]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[255]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[254]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[253]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[252]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[251]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[250]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[249]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[248]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[247]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[246]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[245]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[244]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[243]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[242]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[241]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[240]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[239]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[238]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[237]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[236]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[235]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[234]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[233]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[232]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[231]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[230]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[229]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[228]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[227]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[226]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[225]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[224]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[223]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[222]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[221]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[220]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[219]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[218]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[217]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[216]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[215]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[214]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[213]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[212]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[211]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[210]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[209]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[208]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[207]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[206]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[205]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[204]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[203]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[202]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[201]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[200]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[199]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[198]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[197]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[196]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[195]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[194]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[193]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[192]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[191]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[190]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[189]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[188]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[187]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[186]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[185]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[184]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[183]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[182]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[181]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[180]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[179]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[178]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[177]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[176]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[175]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[174]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[173]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[172]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[171]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[170]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[169]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[168]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[167]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[166]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[165]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[164]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[163]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[162]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[161]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[160]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[159]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[158]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[157]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[156]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[155]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[154]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[153]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[152]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[151]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[150]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[149]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[148]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[147]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[146]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[145]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[144]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[143]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[142]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[141]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[140]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[139]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[138]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[137]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[136]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[135]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[134]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[133]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[132]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[131]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[130]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[129]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[128]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_stage_reg_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[127]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[126]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[125]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[124]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[123]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[122]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[121]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[120]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[119]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[118]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[117]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[116]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[115]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[114]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[113]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[112]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[111]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[110]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[109]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[108]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[107]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[106]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[105]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[104]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[103]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[102]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[101]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[100]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[99]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[98]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[97]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[96]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[95]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[94]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[93]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[92]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[91]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[90]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[89]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[88]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[87]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[86]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[85]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[84]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[83]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[82]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[81]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[80]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[79]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[78]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[77]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[76]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[75]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[74]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[73]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[72]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[71]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[70]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[69]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[68]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[67]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[66]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[65]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[64]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[63]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[62]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[61]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[60]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[59]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[58]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[57]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[56]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[55]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[54]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[53]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[52]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[51]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[50]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[49]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[48]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[47]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[46]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[45]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[44]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[43]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[42]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[41]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[40]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[39]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[38]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[37]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[36]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[35]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[34]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[33]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[32]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[31]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[30]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[29]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[28]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[27]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[26]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[25]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[24]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[23]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[22]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[21]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[20]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[19]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[18]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[17]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[16]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[15]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[14]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[13]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[12]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[11]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[10]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[9]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[8]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[7]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_result_o[0]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[6]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[5]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[4]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[3]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[2]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[1]}] -set_output_delay -clock CLK -max 0.6 [get_ports {cmt_trace_exc_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_trace_exc_o[0]}] diff --git a/flow/designs/tsmc65lp/bp_be_top/macros.v b/flow/designs/tsmc65lp/bp_be_top/macros.v deleted file mode 100644 index f893bb165c..0000000000 --- a/flow/designs/tsmc65lp/bp_be_top/macros.v +++ /dev/null @@ -1,152 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w15_wrapper #( parameter width_p = 15 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w15 - // mem - // ( ... - // ); - - wire [15:0] Q; - wire [15:0] D; - wire [15:0] WEN; - - assign data_o = Q[14:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w16_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN ), - .GWEN (~w_i ), // lo true - .A (addr_i), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w96 - // mem - // ( ... - // ); - - - tsmc65lp_1rf_lg6_w96_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (w_mask_i), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_byte_mask_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - , parameter write_mask_width_lp = width_p>>3 - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [write_mask_width_lp-1:0] write_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_byte_mask_d512_w64 - // mem - // ( ... - // ); - - wire [63:0] wen = ~{{8{write_mask_i[7]}} - ,{8{write_mask_i[6]}} - ,{8{write_mask_i[5]}} - ,{8{write_mask_i[4]}} - ,{8{write_mask_i[3]}} - ,{8{write_mask_i[2]}} - ,{8{write_mask_i[1]}} - ,{8{write_mask_i[0]}}}; - - tsmc65lp_1rf_lg9_w64_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (wen), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - diff --git a/flow/designs/tsmc65lp/bp_be_top/metadata-base-ok.json b/flow/designs/tsmc65lp/bp_be_top/metadata-base-ok.json deleted file mode 100644 index 12df46f069..0000000000 --- a/flow/designs/tsmc65lp/bp_be_top/metadata-base-ok.json +++ /dev/null @@ -1,315 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 5.4000" - ], - "cts__clock__skew__hold": 0.238986, - "cts__clock__skew__setup": 0.238986, - "cts__cpu__total": 629.99, - "cts__design__core__area": 858480, - "cts__design__die__area": 900000, - "cts__design__instance__area": 605674, - "cts__design__instance__area__macros": 244110, - "cts__design__instance__area__stdcell": 361565, - "cts__design__instance__count": 45576, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 10, - "cts__design__instance__count__setup_buffer": 146, - "cts__design__instance__count__stdcell": 45566, - "cts__design__instance__displacement__max": 48.2, - "cts__design__instance__displacement__mean": 0.135, - "cts__design__instance__displacement__total": 6170.29, - "cts__design__instance__utilization": 0.705519, - "cts__design__instance__utilization__stdcell": 0.588513, - "cts__design__io": 3029, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 669604.0, - "cts__power__internal__total": 0.0479907, - "cts__power__leakage__total": 0.000360922, - "cts__power__switching__total": 0.0407844, - "cts__power__total": 0.089136, - "cts__route__wirelength__estimated": -1073740.0, - "cts__runtime__total": "10:34.38", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap_limit": 0.0518793, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_slew": 5, - "cts__timing__drv__max_slew_limit": -0.00290621, - "cts__timing__drv__setup_violation_count": 254, - "cts__timing__setup__tns": -54.7816, - "cts__timing__setup__ws": -0.436431, - "design__io__hpwl": 1791291174, - "detailedplace__cpu__total": 58.96, - "detailedplace__design__core__area": 858480, - "detailedplace__design__die__area": 900000, - "detailedplace__design__instance__area": 595811, - "detailedplace__design__instance__area__macros": 244110, - "detailedplace__design__instance__area__stdcell": 351702, - "detailedplace__design__instance__count": 44661, - "detailedplace__design__instance__count__macros": 10, - "detailedplace__design__instance__count__stdcell": 44651, - "detailedplace__design__instance__displacement__max": 81.5, - "detailedplace__design__instance__displacement__mean": 5.3015, - "detailedplace__design__instance__displacement__total": 236775, - "detailedplace__design__instance__utilization": 0.69403, - "detailedplace__design__instance__utilization__stdcell": 0.572459, - "detailedplace__design__io": 3029, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 638592.0, - "detailedplace__power__internal__total": 0.04072, - "detailedplace__power__leakage__total": 0.000293078, - "detailedplace__power__switching__total": 0.0327246, - "detailedplace__power__total": 0.0737376, - "detailedplace__route__wirelength__estimated": -1073740.0, - "detailedplace__runtime__total": "1:00.84", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.058699, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 2, - "detailedplace__timing__drv__max_slew_limit": -0.000936037, - "detailedplace__timing__drv__setup_violation_count": 1800, - "detailedplace__timing__setup__tns": -1322, - "detailedplace__timing__setup__ws": -2.00857, - "detailedroute__cpu__total": 3212.76, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 6255260.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 19874, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 777, - "detailedroute__route__drc_errors__iter:3": 312, - "detailedroute__route__drc_errors__iter:4": 14, - "detailedroute__route__drc_errors__iter:5": 5, - "detailedroute__route__drc_errors__iter:6": 4, - "detailedroute__route__drc_errors__iter:7": 2, - "detailedroute__route__drc_errors__iter:8": 2, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 43238, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 349367, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 349367, - "detailedroute__route__wirelength": 3134890, - "detailedroute__route__wirelength__iter:1": 3142309, - "detailedroute__route__wirelength__iter:10": 3134888, - "detailedroute__route__wirelength__iter:11": 3134890, - "detailedroute__route__wirelength__iter:2": 3135980, - "detailedroute__route__wirelength__iter:3": 3134921, - "detailedroute__route__wirelength__iter:4": 3134881, - "detailedroute__route__wirelength__iter:5": 3134887, - "detailedroute__route__wirelength__iter:6": 3134889, - "detailedroute__route__wirelength__iter:7": 3134890, - "detailedroute__route__wirelength__iter:8": 3134890, - "detailedroute__route__wirelength__iter:9": 3134890, - "detailedroute__runtime__total": "2:41.66", - "fillcell__cpu__total": 4.34, - "fillcell__mem__peak": 501896.0, - "fillcell__runtime__total": "0:04.72", - "finish__clock__skew__hold": 0.216571, - "finish__clock__skew__setup": 0.2341, - "finish__cpu__total": 61.85, - "finish__design__core__area": 858480, - "finish__design__die__area": 900000, - "finish__design__instance__area": 606273, - "finish__design__instance__area__macros": 244110, - "finish__design__instance__area__stdcell": 362164, - "finish__design__instance__count": 45634, - "finish__design__instance__count__macros": 10, - "finish__design__instance__count__stdcell": 45624, - "finish__design__instance__utilization": 0.706217, - "finish__design__instance__utilization__stdcell": 0.589488, - "finish__design__io": 3029, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 1110280.0, - "finish__power__internal__total": 0.0480145, - "finish__power__leakage__total": 0.000361822, - "finish__power__switching__total": 0.0322693, - "finish__power__total": 0.0806457, - "finish__runtime__total": "1:03.14", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.260192, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.305956, - "finish__timing__drv__setup_violation_count": 72, - "finish__timing__setup__tns": -1.74384, - "finish__timing__setup__ws": -0.0733347, - "finish__timing__wns_percent_delay": -1.504114, - "finish_merge__cpu__total": 15.66, - "finish_merge__mem__peak": 904908.0, - "finish_merge__runtime__total": "0:16.42", - "floorplan__cpu__total": 24.54, - "floorplan__design__core__area": 858480, - "floorplan__design__die__area": 900000, - "floorplan__design__instance__area": 488600, - "floorplan__design__instance__area__macros": 244110, - "floorplan__design__instance__area__stdcell": 244491, - "floorplan__design__instance__count": 37000, - "floorplan__design__instance__count__macros": 10, - "floorplan__design__instance__count__stdcell": 36990, - "floorplan__design__instance__utilization": 0.569146, - "floorplan__design__instance__utilization__stdcell": 0.397953, - "floorplan__design__io": 3029, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 0, - "floorplan__mem__peak": 505232.0, - "floorplan__power__internal__total": 0.0395996, - "floorplan__power__leakage__total": 0.000208817, - "floorplan__power__switching__total": 0.00745188, - "floorplan__power__total": 0.0472603, - "floorplan__runtime__total": "0:35.67", - "floorplan__timing__setup__tns": -37429.1, - "floorplan__timing__setup__ws": -24.5969, - "floorplan_io__cpu__total": 5.27, - "floorplan_io__mem__peak": 389308.0, - "floorplan_io__runtime__total": "0:06.31", - "floorplan_macro__cpu__total": 1272.18, - "floorplan_macro__mem__peak": 546500.0, - "floorplan_macro__runtime__total": "7:14.00", - "floorplan_pdn__cpu__total": 7.54, - "floorplan_pdn__mem__peak": 524792.0, - "floorplan_pdn__runtime__total": "0:08.07", - "floorplan_tap__cpu__total": 5.19, - "floorplan_tap__mem__peak": 360620.0, - "floorplan_tap__runtime__total": "0:05.71", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 15136.22, - "globalplace__design__core__area": 858480, - "globalplace__design__die__area": 900000, - "globalplace__design__instance__area": 492390, - "globalplace__design__instance__area__macros": 244110, - "globalplace__design__instance__area__stdcell": 248280, - "globalplace__design__instance__count": 40947, - "globalplace__design__instance__count__macros": 10, - "globalplace__design__instance__count__stdcell": 40937, - "globalplace__design__instance__utilization": 0.57356, - "globalplace__design__instance__utilization__stdcell": 0.404121, - "globalplace__design__io": 3029, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 925220.0, - "globalplace__power__internal__total": 0.0436079, - "globalplace__power__leakage__total": 0.000208817, - "globalplace__power__switching__total": 0.0272509, - "globalplace__power__total": 0.0710677, - "globalplace__runtime__total": "11:23.26", - "globalplace__timing__setup__tns": -102730, - "globalplace__timing__setup__ws": -66.2567, - "globalplace_io__cpu__total": 5.21, - "globalplace_io__mem__peak": 400916.0, - "globalplace_io__runtime__total": "0:05.67", - "globalplace_skip_io__cpu__total": 4.64, - "globalplace_skip_io__mem__peak": 362668.0, - "globalplace_skip_io__runtime__total": "0:05.01", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.250674, - "globalroute__clock__skew__setup": 0.255728, - "globalroute__cpu__total": 122.84, - "globalroute__design__core__area": 858480, - "globalroute__design__die__area": 900000, - "globalroute__design__instance__area": 606273, - "globalroute__design__instance__area__macros": 244110, - "globalroute__design__instance__area__stdcell": 362164, - "globalroute__design__instance__count": 45634, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 10, - "globalroute__design__instance__count__setup_buffer": 23, - "globalroute__design__instance__count__stdcell": 45624, - "globalroute__design__instance__displacement__max": 19.8, - "globalroute__design__instance__displacement__mean": 0.019, - "globalroute__design__instance__displacement__total": 874.6, - "globalroute__design__instance__utilization": 0.706217, - "globalroute__design__instance__utilization__stdcell": 0.589488, - "globalroute__design__io": 3029, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 1461740.0, - "globalroute__power__internal__total": 0.0480622, - "globalroute__power__leakage__total": 0.000361822, - "globalroute__power__switching__total": 0.0431558, - "globalroute__power__total": 0.0915799, - "globalroute__route__wirelength__estimated": -1073740.0, - "globalroute__runtime__total": "2:06.65", - "globalroute__timing__clock__slack": -0.677, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0718607, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.112093, - "globalroute__timing__drv__setup_violation_count": 494, - "globalroute__timing__setup__tns": -106.41, - "globalroute__timing__setup__ws": -0.676672, - "placeopt__cpu__total": 50.31, - "placeopt__design__core__area": 858480, - "placeopt__design__die__area": 900000, - "placeopt__design__instance__area": 595811, - "placeopt__design__instance__area__macros": 244110, - "placeopt__design__instance__area__stdcell": 351702, - "placeopt__design__instance__count": 44661, - "placeopt__design__instance__count__macros": 10, - "placeopt__design__instance__count__stdcell": 44651, - "placeopt__design__instance__utilization": 0.69403, - "placeopt__design__instance__utilization__stdcell": 0.572459, - "placeopt__design__io": 3029, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 578960.0, - "placeopt__power__internal__total": 0.0407192, - "placeopt__power__leakage__total": 0.000293078, - "placeopt__power__switching__total": 0.0321844, - "placeopt__power__total": 0.0731966, - "placeopt__runtime__total": "0:51.52", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 7, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0573613, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.000328802, - "placeopt__timing__drv__setup_violation_count": 1771, - "placeopt__timing__setup__tns": -1223.16, - "placeopt__timing__setup__ws": -1.99281, - "run__flow__design": "bp_be", - "run__flow__generate_date": "2024-05-10 15:53", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-13712-g8734b32f3", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "e8072ca1312ab1e9e6a7be8513064a05f42e694f", - "run__flow__scripts_commit": "8032f8d0da8d167151eae1440f331a49a9f154e1", - "run__flow__uuid": "f23d49d0-311e-40db-97a2-3deab7622211", - "run__flow__variant": "base", - "synth__cpu__total": 230.35, - "synth__design__instance__area__stdcell": 504042.946, - "synth__design__instance__count__stdcell": 41204.0, - "synth__mem__peak": 292896.0, - "synth__runtime__total": "5:40.76", - "total_time": "0:44:03.790000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/bp_be_top/rules-base.json b/flow/designs/tsmc65lp/bp_be_top/rules-base.json deleted file mode 100644 index af25ca19ff..0000000000 --- a/flow/designs/tsmc65lp/bp_be_top/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 573320.16, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 672980, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 49739, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 4325, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 4325, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 3605123, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.34, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 680109, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 2163, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk deleted file mode 100644 index 5b5161a467..0000000000 --- a/flow/designs/tsmc65lp/bp_fe_top/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -export DESIGN_NICKNAME = bp_fe -export DESIGN_NAME = bp_fe_top -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_all.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w8_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w96_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_all_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w8_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w96_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_all.gds2 - -export DIE_AREA = 0 0 880 780 -export CORE_AREA = 10 12 870 770 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:0-400 -exclude bottom:* - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.05 diff --git a/flow/designs/tsmc65lp/bp_fe_top/constraint.sdc b/flow/designs/tsmc65lp/bp_fe_top/constraint.sdc deleted file mode 100644 index f7a6caab6c..0000000000 --- a/flow/designs/tsmc65lp/bp_fe_top/constraint.sdc +++ /dev/null @@ -1,13 +0,0 @@ -current_design bp_fe_top -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name CLK -period 5.4 -waveform {0 2.7} [get_ports {clk_i}] - -set clk_name CLK -set clk_port [get_ports CLK] -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay -max 0.6 -clock $clk_name $non_clock_inputs -set_input_delay -min 1.2 -clock $clk_name $non_clock_inputs -set_output_delay 0.6 -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/bp_fe_top/macros.v b/flow/designs/tsmc65lp/bp_fe_top/macros.v deleted file mode 100644 index 88ff987863..0000000000 --- a/flow/designs/tsmc65lp/bp_fe_top/macros.v +++ /dev/null @@ -1,192 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w7_wrapper #( parameter width_p = 7 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w7 - // mem - // ( ... - // ); - - wire [7:0] Q; - wire [7:0] D; - wire [7:0] WEN; - - assign data_o = Q[6:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w8_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w96 - // mem - // ( ... - // ); - - - tsmc65lp_1rf_lg6_w96_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (w_mask_i), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_byte_mask_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - , parameter write_mask_width_lp = width_p>>3 - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [write_mask_width_lp-1:0] write_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_byte_mask_d512_w64 - // mem - // ( ... - // ); - - wire [63:0] wen = ~{{8{write_mask_i[7]}} - ,{8{write_mask_i[6]}} - ,{8{write_mask_i[5]}} - ,{8{write_mask_i[4]}} - ,{8{write_mask_i[3]}} - ,{8{write_mask_i[2]}} - ,{8{write_mask_i[1]}} - ,{8{write_mask_i[0]}}}; - - tsmc65lp_1rf_lg9_w64_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (wen), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input v_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_d512_w64 - // mem - // ( ... - // ); - - tsmc65lp_1rf_lg9_w64_all mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - diff --git a/flow/designs/tsmc65lp/bp_fe_top/metadata-base-ok.json b/flow/designs/tsmc65lp/bp_fe_top/metadata-base-ok.json deleted file mode 100644 index e9f66a521f..0000000000 --- a/flow/designs/tsmc65lp/bp_fe_top/metadata-base-ok.json +++ /dev/null @@ -1,366 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 5.4000" - ], - "cts__clock__skew__hold": 0.343192, - "cts__clock__skew__hold__post_repair": 0.309956, - "cts__clock__skew__hold__pre_repair": 0.309956, - "cts__clock__skew__setup": 0.343192, - "cts__clock__skew__setup__post_repair": 0.309956, - "cts__clock__skew__setup__pre_repair": 0.309956, - "cts__cpu__total": 43.88, - "cts__design__core__area": 650160, - "cts__design__core__area__post_repair": 650160, - "cts__design__core__area__pre_repair": 650160, - "cts__design__die__area": 686400, - "cts__design__die__area__post_repair": 686400, - "cts__design__die__area__pre_repair": 686400, - "cts__design__instance__area": 484915, - "cts__design__instance__area__macros": 269524, - "cts__design__instance__area__macros__post_repair": 269524, - "cts__design__instance__area__macros__pre_repair": 269524, - "cts__design__instance__area__post_repair": 484425, - "cts__design__instance__area__pre_repair": 484425, - "cts__design__instance__area__stdcell": 215391, - "cts__design__instance__area__stdcell__post_repair": 214901, - "cts__design__instance__area__stdcell__pre_repair": 214901, - "cts__design__instance__count": 28101, - "cts__design__instance__count__hold_buffer": 65, - "cts__design__instance__count__macros": 11, - "cts__design__instance__count__macros__post_repair": 11, - "cts__design__instance__count__macros__pre_repair": 11, - "cts__design__instance__count__post_repair": 28028, - "cts__design__instance__count__pre_repair": 28028, - "cts__design__instance__count__setup_buffer": 5, - "cts__design__instance__count__stdcell": 28090, - "cts__design__instance__count__stdcell__post_repair": 28017, - "cts__design__instance__count__stdcell__pre_repair": 28017, - "cts__design__instance__displacement__max": 41.6, - "cts__design__instance__displacement__mean": 0.182, - "cts__design__instance__displacement__total": 5118.94, - "cts__design__instance__utilization": 0.74584, - "cts__design__instance__utilization__post_repair": 0.745086, - "cts__design__instance__utilization__pre_repair": 0.745086, - "cts__design__instance__utilization__stdcell": 0.565872, - "cts__design__instance__utilization__stdcell__post_repair": 0.564585, - "cts__design__instance__utilization__stdcell__pre_repair": 0.564585, - "cts__design__io": 2511, - "cts__design__io__post_repair": 2511, - "cts__design__io__pre_repair": 2511, - "cts__design__violations": 0, - "cts__mem__peak": 534800.0, - "cts__power__internal__total": 0.0204451, - "cts__power__internal__total__post_repair": 0.0204304, - "cts__power__internal__total__pre_repair": 0.0204304, - "cts__power__leakage__total": 0.000173227, - "cts__power__leakage__total__post_repair": 0.000172979, - "cts__power__leakage__total__pre_repair": 0.000172979, - "cts__power__switching__total": 0.0220747, - "cts__power__switching__total__post_repair": 0.0219532, - "cts__power__switching__total__pre_repair": 0.0219532, - "cts__power__total": 0.0426931, - "cts__power__total__post_repair": 0.0425565, - "cts__power__total__pre_repair": 0.0425565, - "cts__route__wirelength__estimated": 2019410.0, - "cts__runtime__total": "0:54.58", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 64, - "cts__timing__drv__hold_violation_count__pre_repair": 64, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.168477, - "cts__timing__drv__max_cap_limit__post_repair": 0.095465, - "cts__timing__drv__max_cap_limit__pre_repair": 0.095465, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.275219, - "cts__timing__drv__max_slew_limit__post_repair": 0.150523, - "cts__timing__drv__max_slew_limit__pre_repair": 0.150523, - "cts__timing__drv__setup_violation_count": 1, - "cts__timing__drv__setup_violation_count__post_repair": 49, - "cts__timing__drv__setup_violation_count__pre_repair": 49, - "cts__timing__setup__tns": -0.134825, - "cts__timing__setup__tns__post_repair": -23.3407, - "cts__timing__setup__tns__pre_repair": -23.3407, - "cts__timing__setup__ws": -0.134808, - "cts__timing__setup__ws__post_repair": -0.897497, - "cts__timing__setup__ws__pre_repair": -0.897497, - "cts_fill__cpu__total": 4.43, - "cts_fill__mem__peak": 437448.0, - "cts_fill__runtime__total": "0:04.80", - "design__io__hpwl": 1853651500, - "detailedplace__cpu__total": 24.1, - "detailedplace__design__core__area": 650160, - "detailedplace__design__die__area": 686400, - "detailedplace__design__instance__area": 483561, - "detailedplace__design__instance__area__macros": 269524, - "detailedplace__design__instance__area__stdcell": 214037, - "detailedplace__design__instance__count": 27848, - "detailedplace__design__instance__count__macros": 11, - "detailedplace__design__instance__count__stdcell": 27837, - "detailedplace__design__instance__displacement__max": 259.2, - "detailedplace__design__instance__displacement__mean": 9.5065, - "detailedplace__design__instance__displacement__total": 264738, - "detailedplace__design__instance__utilization": 0.743757, - "detailedplace__design__instance__utilization__stdcell": 0.562315, - "detailedplace__design__io": 2511, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 498608.0, - "detailedplace__power__internal__total": 0.0200101, - "detailedplace__power__leakage__total": 0.000171929, - "detailedplace__power__switching__total": 0.0189467, - "detailedplace__power__total": 0.0391287, - "detailedplace__route__wirelength__estimated": 2038550.0, - "detailedplace__runtime__total": "0:30.23", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.095465, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.150523, - "detailedplace__timing__drv__setup_violation_count": 37, - "detailedplace__timing__setup__tns": -17.6137, - "detailedplace__timing__setup__ws": -0.728329, - "detailedroute__cpu__total": 1788.43, - "detailedroute__mem__peak": 4882216.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 18914, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 1, - "detailedroute__route__drc_errors__iter:13": 0, - "detailedroute__route__drc_errors__iter:2": 3204, - "detailedroute__route__drc_errors__iter:3": 2726, - "detailedroute__route__drc_errors__iter:4": 17, - "detailedroute__route__drc_errors__iter:5": 5, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 27036, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 214241, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 214241, - "detailedroute__route__wirelength": 2206027, - "detailedroute__route__wirelength__iter:1": 2211859, - "detailedroute__route__wirelength__iter:10": 2206030, - "detailedroute__route__wirelength__iter:11": 2206030, - "detailedroute__route__wirelength__iter:12": 2206027, - "detailedroute__route__wirelength__iter:13": 2206027, - "detailedroute__route__wirelength__iter:2": 2207933, - "detailedroute__route__wirelength__iter:3": 2206152, - "detailedroute__route__wirelength__iter:4": 2206034, - "detailedroute__route__wirelength__iter:5": 2206030, - "detailedroute__route__wirelength__iter:6": 2206030, - "detailedroute__route__wirelength__iter:7": 2206030, - "detailedroute__route__wirelength__iter:8": 2206030, - "detailedroute__route__wirelength__iter:9": 2206030, - "detailedroute__runtime__total": "4:24.73", - "finish__clock__skew__hold": 0.238928, - "finish__clock__skew__setup": 0.238928, - "finish__cpu__total": 48.21, - "finish__design__core__area": 650160, - "finish__design__die__area": 686400, - "finish__design__instance__area": 484915, - "finish__design__instance__area__macros": 269524, - "finish__design__instance__area__stdcell": 215391, - "finish__design__instance__count": 28101, - "finish__design__instance__count__macros": 11, - "finish__design__instance__count__stdcell": 28090, - "finish__design__instance__utilization": 0.74584, - "finish__design__instance__utilization__stdcell": 0.565872, - "finish__design__io": 2511, - "finish__mem__peak": 819032.0, - "finish__power__internal__total": 0.0204761, - "finish__power__leakage__total": 0.000173227, - "finish__power__switching__total": 0.0170778, - "finish__power__total": 0.0377272, - "finish__runtime__total": "0:54.44", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.232957, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.271265, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.360714, - "finish__timing__wns_percent_delay": 6.107969, - "finish_merge__cpu__total": 11.9, - "finish_merge__mem__peak": 757824.0, - "finish_merge__runtime__total": "0:14.52", - "floorplan__cpu__total": 10.23, - "floorplan__design__core__area": 650160, - "floorplan__design__die__area": 686400, - "floorplan__design__instance__area": 409278, - "floorplan__design__instance__area__macros": 269524, - "floorplan__design__instance__area__stdcell": 139754, - "floorplan__design__instance__count": 21419, - "floorplan__design__instance__count__macros": 11, - "floorplan__design__instance__count__stdcell": 21408, - "floorplan__design__instance__utilization": 0.629503, - "floorplan__design__instance__utilization__stdcell": 0.367159, - "floorplan__design__io": 2511, - "floorplan__mem__peak": 420680.0, - "floorplan__power__internal__total": 0.0214733, - "floorplan__power__leakage__total": 0.000112458, - "floorplan__power__switching__total": 0.00354227, - "floorplan__power__total": 0.0251281, - "floorplan__runtime__total": "0:12.77", - "floorplan__timing__setup__tns": -37008.3, - "floorplan__timing__setup__ws": -25.3674, - "floorplan_io__cpu__total": 3.74, - "floorplan_io__mem__peak": 353084.0, - "floorplan_io__runtime__total": "0:04.03", - "floorplan_macro__cpu__total": 337.51, - "floorplan_macro__mem__peak": 433744.0, - "floorplan_macro__runtime__total": "2:09.63", - "floorplan_pdn__cpu__total": 7.27, - "floorplan_pdn__mem__peak": 477576.0, - "floorplan_pdn__runtime__total": "0:07.79", - "floorplan_tap__cpu__total": 3.71, - "floorplan_tap__mem__peak": 338092.0, - "floorplan_tap__runtime__total": "0:03.95", - "floorplan_tdms__cpu__total": 3.83, - "floorplan_tdms__mem__peak": 350796.0, - "floorplan_tdms__runtime__total": "0:04.11", - "globalplace__cpu__total": 116.18, - "globalplace__design__core__area": 650160, - "globalplace__design__die__area": 686400, - "globalplace__design__instance__area": 412129, - "globalplace__design__instance__area__macros": 269524, - "globalplace__design__instance__area__stdcell": 142605, - "globalplace__design__instance__count": 24389, - "globalplace__design__instance__count__macros": 11, - "globalplace__design__instance__count__stdcell": 24378, - "globalplace__design__instance__utilization": 0.633889, - "globalplace__design__instance__utilization__stdcell": 0.37465, - "globalplace__design__io": 2511, - "globalplace__mem__peak": 643836.0, - "globalplace__power__internal__total": 0.0252728, - "globalplace__power__leakage__total": 0.000112458, - "globalplace__power__switching__total": 0.0148337, - "globalplace__power__total": 0.0402189, - "globalplace__runtime__total": "2:10.39", - "globalplace__timing__setup__tns": -88956.7, - "globalplace__timing__setup__ws": -64.5382, - "globalplace_io__cpu__total": 4.67, - "globalplace_io__mem__peak": 363356.0, - "globalplace_io__runtime__total": "0:05.04", - "globalplace_skip_io__cpu__total": 11.64, - "globalplace_skip_io__mem__peak": 392824.0, - "globalplace_skip_io__runtime__total": "0:12.05", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.347584, - "globalroute__clock__skew__setup": 0.347584, - "globalroute__cpu__total": 34.49, - "globalroute__design__core__area": 650160, - "globalroute__design__die__area": 686400, - "globalroute__design__instance__area": 484915, - "globalroute__design__instance__area__macros": 269524, - "globalroute__design__instance__area__stdcell": 215391, - "globalroute__design__instance__count": 28101, - "globalroute__design__instance__count__macros": 11, - "globalroute__design__instance__count__stdcell": 28090, - "globalroute__design__instance__utilization": 0.74584, - "globalroute__design__instance__utilization__stdcell": 0.565872, - "globalroute__design__io": 2511, - "globalroute__mem__peak": 886492.0, - "globalroute__power__internal__total": 0.0204426, - "globalroute__power__leakage__total": 0.000173227, - "globalroute__power__switching__total": 0.023399, - "globalroute__power__total": 0.0440148, - "globalroute__runtime__total": "0:45.87", - "globalroute__timing__clock__slack": -0.635, - "globalroute__timing__drv__hold_violation_count": 30, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.143338, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.186732, - "globalroute__timing__drv__setup_violation_count": 48, - "globalroute__timing__setup__tns": -10.7952, - "globalroute__timing__setup__ws": -0.63457, - "placeopt__cpu__total": 28.27, - "placeopt__design__core__area": 650160, - "placeopt__design__core__area__pre_opt": 650160, - "placeopt__design__die__area": 686400, - "placeopt__design__die__area__pre_opt": 686400, - "placeopt__design__instance__area": 483561, - "placeopt__design__instance__area__macros": 269524, - "placeopt__design__instance__area__macros__pre_opt": 269524, - "placeopt__design__instance__area__pre_opt": 412129, - "placeopt__design__instance__area__stdcell": 214037, - "placeopt__design__instance__area__stdcell__pre_opt": 142605, - "placeopt__design__instance__count": 27848, - "placeopt__design__instance__count__macros": 11, - "placeopt__design__instance__count__macros__pre_opt": 11, - "placeopt__design__instance__count__pre_opt": 24389, - "placeopt__design__instance__count__stdcell": 27837, - "placeopt__design__instance__count__stdcell__pre_opt": 24378, - "placeopt__design__instance__utilization": 0.743757, - "placeopt__design__instance__utilization__pre_opt": 0.633889, - "placeopt__design__instance__utilization__stdcell": 0.562315, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.37465, - "placeopt__design__io": 2511, - "placeopt__design__io__pre_opt": 2511, - "placeopt__mem__peak": 483644.0, - "placeopt__power__internal__total": 0.0195994, - "placeopt__power__internal__total__pre_opt": 0.0252728, - "placeopt__power__leakage__total": 0.000171929, - "placeopt__power__leakage__total__pre_opt": 0.000112458, - "placeopt__power__switching__total": 0.0164641, - "placeopt__power__switching__total__pre_opt": 0.0148337, - "placeopt__power__total": 0.0362354, - "placeopt__power__total__pre_opt": 0.0402189, - "placeopt__runtime__total": "0:28.91", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0652392, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.122783, - "placeopt__timing__drv__setup_violation_count": 35, - "placeopt__timing__setup__tns": -17.9209, - "placeopt__timing__setup__tns__pre_opt": -88956.7, - "placeopt__timing__setup__ws": -0.766891, - "placeopt__timing__setup__ws__pre_opt": -64.5382, - "run__flow__design": "bp_fe", - "run__flow__generate_date": "2023-08-01 13:11", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9491-g3aee924c6", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "0f508c2255c5b75b9a9388ad26548583a1b38ec0", - "run__flow__uuid": "0a1d3a19-30af-46f8-8309-48f63914e25c", - "run__flow__variant": "base", - "synth__cpu__total": 115.64, - "synth__design__instance__area__stdcell": 419141.009, - "synth__design__instance__count__stdcell": 24371.0, - "synth__mem__peak": 263580.0, - "synth__runtime__total": "1:59.53", - "total_time": "0:15:27.370000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/bp_multi_top/config.mk b/flow/designs/tsmc65lp/bp_multi_top/config.mk deleted file mode 100644 index 9e4d4aebad..0000000000 --- a/flow/designs/tsmc65lp/bp_multi_top/config.mk +++ /dev/null @@ -1,47 +0,0 @@ -export DESIGN_NICKNAME = bp_multi -export DESIGN_NAME = bp_multi_top -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 -# -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w16_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w8_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w96_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w96_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg9_w64_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg5_w64_all.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w16_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w8_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w96_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w96_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg9_w64_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_2rf_lg5_w64_all_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w16_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w8_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w96_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg8_w96_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg9_w64_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg5_w64_all.gds2 - -export DIE_AREA = 0 0 1800 1600 -export CORE_AREA = 10 12 1790 1590 - -export PLACE_PINS_ARGS = -exclude left:0-1400 -exclude right:0-1400 -exclude bottom:* -exclude top:0-100 -exclude top:1500-1600 - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.10 diff --git a/flow/designs/tsmc65lp/bp_multi_top/constraint.sdc b/flow/designs/tsmc65lp/bp_multi_top/constraint.sdc deleted file mode 100644 index e033c9cc88..0000000000 --- a/flow/designs/tsmc65lp/bp_multi_top/constraint.sdc +++ /dev/null @@ -1,2906 +0,0 @@ - -create_clock [get_ports clk_i] -name CLK -period 4.8 -waveform {0 2.4} -set_input_delay -clock CLK -max 1.8 [get_ports reset_i] -set_input_delay -clock CLK -min 1.2 [get_ports reset_i] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_data_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[541]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[540]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[539]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[538]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[537]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[536]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[535]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[534]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[533]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[532]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[531]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[530]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[529]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[528]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[527]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[526]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[525]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[524]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[523]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[522]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[521]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[520]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[519]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[518]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[517]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[516]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[515]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[514]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[513]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[512]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[511]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[510]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[509]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[508]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[507]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[506]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[505]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[504]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[503]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[502]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[501]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[500]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[499]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[498]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[497]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[496]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[495]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[494]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[493]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[492]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[491]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[490]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[489]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[488]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[487]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[486]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[485]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[484]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[483]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[482]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[481]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[480]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[479]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[478]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[477]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[476]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[475]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[474]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[473]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[472]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[471]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[470]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[469]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[468]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[467]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[466]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[465]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[464]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[463]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[462]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[461]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[460]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[459]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[458]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[457]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[456]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[455]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[454]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[453]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[452]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[451]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[450]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[449]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[448]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[447]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[446]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[445]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[444]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[443]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[442]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[441]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[440]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[439]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[438]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[437]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[436]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[435]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[434]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[433]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[432]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[431]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[430]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[429]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[428]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[427]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[426]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[425]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[424]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[423]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[422]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[421]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[420]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[419]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[418]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[417]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[416]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[415]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[414]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[413]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[412]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[411]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[410]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[409]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[408]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[407]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[406]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[405]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[404]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[403]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[402]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[401]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[400]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[399]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[398]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[397]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[396]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[395]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[394]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[393]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[392]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[391]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[390]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[389]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[388]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[387]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[386]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[385]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[384]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[383]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[382]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[381]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[380]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[379]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[378]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[377]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[376]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[375]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[374]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[373]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[372]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[371]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[370]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[369]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[368]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[367]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[366]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[365]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[364]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[363]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[362]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[361]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[360]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[359]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[358]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[357]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[356]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[355]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[354]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[353]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[352]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[351]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[350]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[349]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[348]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[347]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[346]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[345]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[344]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[343]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[342]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[341]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[340]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[339]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[338]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[337]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[336]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[335]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[334]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[333]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[332]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[331]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[330]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[329]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[328]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[327]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[326]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[325]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[324]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[323]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[322]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[321]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[320]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[319]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[318]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[317]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[316]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[315]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[314]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[313]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[312]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[311]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[310]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[309]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[308]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[307]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[306]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[305]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[304]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[303]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[302]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[301]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[300]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[299]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[298]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[297]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[296]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[295]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[294]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[293]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[292]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[291]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[290]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[289]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[288]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[287]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[286]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[285]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[284]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[283]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[282]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[281]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[280]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[279]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[278]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[277]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[276]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[275]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[274]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[273]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[272]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[271]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[270]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[269]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[268]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[267]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[266]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[265]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[264]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[263]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[262]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[261]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[260]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[259]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[258]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[257]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[256]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[255]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[254]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[253]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[252]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[251]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[250]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[249]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[248]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[247]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[246]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[245]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[244]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[243]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[242]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[241]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[240]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[239]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[238]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[237]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[236]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[235]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[234]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[233]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[232]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[231]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[230]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[229]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[228]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[227]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[226]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[225]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[224]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[223]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[222]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[221]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[220]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[219]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[218]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[217]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[216]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[215]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[214]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[213]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[212]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[211]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[210]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[209]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[208]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[207]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[206]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[205]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[204]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[203]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[202]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[201]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[200]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[199]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[198]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[197]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[196]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[195]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[194]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[193]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[192]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[191]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[190]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[189]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[188]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[187]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[186]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[185]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[184]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[183]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[182]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[181]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[180]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[179]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[178]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[177]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[176]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[175]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[174]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[173]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[172]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[171]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[170]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[169]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[168]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[167]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[166]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[165]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[164]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[163]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[162]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[161]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[160]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[159]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[158]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[157]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[156]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[155]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[154]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[153]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[152]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[151]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[150]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[149]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[148]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[147]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[146]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[145]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[144]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[143]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[142]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[141]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[140]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[139]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[138]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[137]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[136]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[135]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[134]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[133]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[132]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[131]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[130]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[129]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[128]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[127]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[126]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[125]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[124]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[123]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[122]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[121]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[120]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[119]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[118]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[117]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[116]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[115]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[114]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[113]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[112]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[111]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[110]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[109]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[108]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[107]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[106]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[105]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[104]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[103]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[102]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[101]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[100]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[99]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[98]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[97]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[96]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[95]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[94]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[93]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[92]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[91]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[90]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[89]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[88]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[87]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[86]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[85]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[84]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[83]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[82]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[81]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[80]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[79]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[78]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[77]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[76]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[75]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[74]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[73]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[72]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[71]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[70]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[69]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[68]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[67]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[66]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[65]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[64]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[63]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[62]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[61]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[60]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[59]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[58]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[57]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[56]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[55]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[54]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[53]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[52]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[51]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[50]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[49]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[48]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[47]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[46]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[45]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[44]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[43]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[42]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[41]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[40]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[39]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[38]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[37]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[36]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[35]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[34]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[33]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[32]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[31]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[30]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[29]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[28]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[27]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[26]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[25]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[24]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[23]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[22]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[21]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[20]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[19]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[18]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[17]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[16]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[15]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[14]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[13]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[12]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[11]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[10]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[9]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[8]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[7]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[6]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[5]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[4]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[3]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[2]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[1]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_v_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_cmd_yumi_i[0]}] -set_input_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_yumi_i[0]}] -set_input_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_yumi_i[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cce_inst_boot_rom_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_resp_ready_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[569]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[568]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[567]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[566]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[565]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[564]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[563]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[562]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[561]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[560]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[559]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[558]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[557]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[556]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[555]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[554]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[553]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[552]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[551]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[550]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[549]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[548]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[547]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[546]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[545]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[544]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[543]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[542]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[541]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[540]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[539]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[538]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[537]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[536]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[535]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[534]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[533]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[532]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[531]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[530]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[529]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[528]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[527]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[526]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[525]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[524]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[523]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[522]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[521]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[520]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[519]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[518]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[517]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[516]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[515]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[514]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[513]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[512]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[511]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[510]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[509]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[508]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[507]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[506]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[505]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[504]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[503]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[502]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[501]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[500]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[499]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[498]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[497]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[496]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[495]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[494]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[493]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[492]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[491]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[490]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[489]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[488]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[487]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[486]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[485]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[484]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[483]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[482]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[481]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[480]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[479]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[478]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[477]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[476]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[475]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[474]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[473]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[472]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[471]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[470]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[469]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[468]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[467]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[466]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[465]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[464]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[463]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[462]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[461]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[460]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[459]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[458]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[457]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[456]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[455]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[454]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[453]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[452]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[451]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[450]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[449]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[448]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[447]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[446]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[445]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[444]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[443]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[442]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[441]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[440]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[439]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[438]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[437]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[436]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[435]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[434]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[433]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[432]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[431]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[430]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[429]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[428]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[427]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[426]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[425]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[424]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[423]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[422]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[421]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[420]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[419]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[418]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[417]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[416]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[415]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[414]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[413]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[412]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[411]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[410]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[409]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[408]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[407]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[406]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[405]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[404]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[403]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[402]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[401]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[400]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[399]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[398]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[397]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[396]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[395]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[394]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[393]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[392]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[391]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[390]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[389]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[388]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[387]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[386]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[385]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[384]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[383]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[382]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[381]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[380]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[379]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[378]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[377]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[376]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[375]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[374]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[373]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[372]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[371]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[370]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[369]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[368]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[367]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[366]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[365]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[364]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[363]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[362]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[361]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[360]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[359]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[358]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[357]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[356]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[355]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[354]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[353]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[352]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[351]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[350]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[349]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[348]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[347]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[346]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[345]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[344]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[343]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[342]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[341]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[340]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[339]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[338]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[337]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[336]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[335]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[334]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[333]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[332]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[331]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[330]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[329]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[328]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[327]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[326]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[325]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[324]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[323]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[322]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[321]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[320]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[319]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[318]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[317]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[316]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[315]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[314]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[313]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[312]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[311]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[310]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[309]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[308]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[307]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[306]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[305]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[304]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[303]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[302]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[301]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[300]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[299]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[298]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[297]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[296]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[295]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[294]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[293]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[292]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[291]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[290]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[289]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[288]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[287]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[286]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[285]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[284]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[283]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[282]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[281]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[280]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[279]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[278]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[277]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[276]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[275]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[274]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[273]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[272]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[271]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[270]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[269]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[268]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[267]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[266]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[265]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[264]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[263]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[262]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[261]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[260]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[259]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[258]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[257]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[256]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[255]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[254]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[253]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[252]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[251]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[250]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[249]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[248]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[247]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[246]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[245]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[244]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[243]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[242]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[241]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[240]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[239]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[238]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[237]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[236]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[235]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[234]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[233]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[232]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[231]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[230]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[229]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[228]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[227]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[226]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[225]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[224]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[223]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[222]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[221]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[220]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[219]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[218]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[217]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[216]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[215]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[214]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[213]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[212]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[211]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[210]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[209]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[208]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[207]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[206]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[205]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[204]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[203]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[202]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[201]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[200]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[199]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[198]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[197]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[196]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[195]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[194]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[193]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[192]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[191]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[190]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[189]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[188]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[187]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[186]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[185]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[184]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[183]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[182]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[181]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[180]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[179]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[178]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[177]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[176]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[175]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[174]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[173]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[172]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[171]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[170]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[169]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[168]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[167]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[166]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[165]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[164]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[163]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[162]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[161]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[160]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[159]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[158]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[157]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[156]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[155]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[154]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[153]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[152]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[151]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[150]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[149]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[148]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[147]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[146]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[145]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[144]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[143]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[142]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[141]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[140]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[139]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[138]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[137]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[136]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[135]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[134]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[133]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[132]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[131]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[130]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[129]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[128]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[127]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[126]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[125]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[124]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[123]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[122]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[121]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[120]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[119]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[118]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[117]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[116]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[115]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[114]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[113]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[112]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[111]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[110]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[109]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[108]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[107]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[106]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[105]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[104]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[103]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[102]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[101]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[100]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[99]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[98]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[97]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[96]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[95]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[94]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[93]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[92]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[91]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[90]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[89]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[88]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[87]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[86]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[85]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[84]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[83]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[82]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[81]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[80]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[79]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[78]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[77]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[76]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[75]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[74]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[73]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[72]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[71]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[70]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[69]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[68]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[67]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[66]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[65]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[64]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {mem_data_cmd_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_rd_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_w_v_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_addr_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_op_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_op_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_op_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_mem_op_o[0]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[63]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[62]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[61]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[60]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[59]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[58]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[57]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[56]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[55]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[54]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[53]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[52]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[51]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[50]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[49]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[48]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[47]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[46]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[45]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[44]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[43]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[42]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[41]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[40]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[39]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[38]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[37]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[36]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[35]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[34]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[33]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[32]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[31]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[30]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[29]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[28]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[27]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[26]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[25]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[24]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[23]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[22]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[21]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[20]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[19]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[18]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[17]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[16]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[15]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[14]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[13]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[12]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[11]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[10]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[9]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[8]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[7]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[6]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[5]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[4]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[3]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[2]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[1]}] -set_output_delay -clock CLK -max 1.8 [get_ports {cmt_data_o[0]}] -set_output_delay -clock CLK -min 1.2 [get_ports {cmt_data_o[0]}] diff --git a/flow/designs/tsmc65lp/bp_multi_top/macros.v b/flow/designs/tsmc65lp/bp_multi_top/macros.v deleted file mode 100644 index c5b8038f78..0000000000 --- a/flow/designs/tsmc65lp/bp_multi_top/macros.v +++ /dev/null @@ -1,334 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w15_wrapper #( parameter width_p = 15 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w15 - // mem - // ( ... - // ); - - wire [15:0] Q; - wire [15:0] D; - wire [15:0] WEN; - - assign data_o = Q[14:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w16_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN ), - .GWEN (~w_i ), // lo true - .A (addr_i), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w7_wrapper #( parameter width_p = 7 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w7 - // mem - // ( ... - // ); - - wire [7:0] Q; - wire [7:0] D; - wire [7:0] WEN; - - assign data_o = Q[6:0]; - assign D = {1'b0,data_i}; - assign WEN = {1'b0,w_mask_i}; - - tsmc65lp_1rf_lg6_w8_bit mem ( - .CLK (clk_i ), - .Q (Q ), // out - .CEN (~v_i ), // lo true - .WEN (WEN), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (D ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_bit_mask_d64_w96_wrapper #( parameter width_p = 96 - , parameter els_p = 64 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [width_p-1:0] w_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_bit_mask_d64_w96 - // mem - // ( ... - // ); - - - tsmc65lp_1rf_lg6_w96_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (w_mask_i), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_byte_mask_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - , parameter write_mask_width_lp = width_p>>3 - ) - ( input clk_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input v_i - , input [write_mask_width_lp-1:0] write_mask_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_byte_mask_d512_w64 - // mem - // ( ... - // ); - - wire [63:0] wen = ~{{8{write_mask_i[7]}} - ,{8{write_mask_i[6]}} - ,{8{write_mask_i[5]}} - ,{8{write_mask_i[4]}} - ,{8{write_mask_i[3]}} - ,{8{write_mask_i[2]}} - ,{8{write_mask_i[1]}} - ,{8{write_mask_i[0]}}}; - - tsmc65lp_1rf_lg9_w64_bit mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (wen), - .GWEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_d256_w96_wrapper #( parameter width_p = 96 - , parameter els_p = 256 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input v_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_d256_w96 - // mem - // ( ... - // ); - - tsmc65lp_1rf_lg8_w96_all mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1rw_d512_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 512 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input v_i - , input reset_i - , input [width_p-1:0] data_i - , input [addr_width_lp-1:0] addr_i - , input w_i - , output wire [width_p-1:0] data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1rw_d512_w64 - // mem - // ( ... - // ); - - tsmc65lp_1rf_lg9_w64_all mem ( - .CLK (clk_i ), - .Q (data_o ), // out - .CEN (~v_i ), // lo true - .WEN (~w_i ), // lo true - .A (addr_i ), // in - .D (data_i ), // in - // - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module hard_mem_1r1w_d32_w64_wrapper #( parameter width_p = 64 - , parameter els_p = 32 - , parameter addr_width_lp = $clog2(els_p) - ) - ( input clk_i - , input reset_i - , input w_v_i - , input [addr_width_lp-1:0] w_addr_i - , input [width_p-1:0] w_data_i - , input r_v_i - , input [addr_width_lp-1:0] r_addr_i - , output wire [width_p-1:0] r_data_o - ); - - // TODO: Replace the sythesizable RTL model below with the hardened - // equivilant. Use the RTL model to check the sematics of the harden block - // match. - // - // NOTE: The instance name of the hardened block is expected to be "mem". - - //hard_mem_1r1w_d32_w64 - // mem - // ( ... - // ); - - tsmc65lp_2rf_lg5_w64_all mem - ( - // read port - .CLKA (clk_i) - ,.AA (r_addr_i) - ,.CENA(~r_v_i) - - // output - ,.QA (r_data_o) - - // write port - ,.CLKB(clk_i) - ,.AB (w_addr_i) - ,.DB (w_data_i) - ,.CENB(~w_v_i) - - ,.EMAA (3'd3 ) // Extra Margin Adjustment - default value - ,.EMAB (3'd3 ) // Extra Margin Adjustment - default value - ,.RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////// - diff --git a/flow/designs/tsmc65lp/bp_multi_top/metadata-base-ok.json b/flow/designs/tsmc65lp/bp_multi_top/metadata-base-ok.json deleted file mode 100644 index c9ec97457c..0000000000 --- a/flow/designs/tsmc65lp/bp_multi_top/metadata-base-ok.json +++ /dev/null @@ -1,364 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "CLK: 4.8000" - ], - "cts__clock__skew__hold": 0.212472, - "cts__clock__skew__hold__post_repair": 0.183855, - "cts__clock__skew__hold__pre_repair": 0.183855, - "cts__clock__skew__setup": 0.212472, - "cts__clock__skew__setup__post_repair": 0.183855, - "cts__clock__skew__setup__pre_repair": 0.183855, - "cts__cpu__total": 379.18, - "cts__design__core__area": 2806700.0, - "cts__design__core__area__post_repair": 2806700.0, - "cts__design__core__area__pre_repair": 2806700.0, - "cts__design__die__area": 2880000.0, - "cts__design__die__area__post_repair": 2880000.0, - "cts__design__die__area__pre_repair": 2880000.0, - "cts__design__instance__area": 1252540.0, - "cts__design__instance__area__macros": 581231, - "cts__design__instance__area__macros__post_repair": 581231, - "cts__design__instance__area__macros__pre_repair": 581231, - "cts__design__instance__area__post_repair": 1248310.0, - "cts__design__instance__area__pre_repair": 1248290.0, - "cts__design__instance__area__stdcell": 671304, - "cts__design__instance__area__stdcell__post_repair": 667077, - "cts__design__instance__area__stdcell__pre_repair": 667060, - "cts__design__instance__count": 88641, - "cts__design__instance__count__hold_buffer": 162, - "cts__design__instance__count__macros": 26, - "cts__design__instance__count__macros__post_repair": 26, - "cts__design__instance__count__macros__pre_repair": 26, - "cts__design__instance__count__post_repair": 88010, - "cts__design__instance__count__pre_repair": 88009, - "cts__design__instance__count__setup_buffer": 367, - "cts__design__instance__count__stdcell": 88615, - "cts__design__instance__count__stdcell__post_repair": 87984, - "cts__design__instance__count__stdcell__pre_repair": 87983, - "cts__design__instance__displacement__max": 48.5935, - "cts__design__instance__displacement__mean": 0.05, - "cts__design__instance__displacement__total": 4442.21, - "cts__design__instance__utilization": 0.446266, - "cts__design__instance__utilization__post_repair": 0.444759, - "cts__design__instance__utilization__pre_repair": 0.444754, - "cts__design__instance__utilization__stdcell": 0.301646, - "cts__design__instance__utilization__stdcell__post_repair": 0.299746, - "cts__design__instance__utilization__stdcell__pre_repair": 0.299739, - "cts__design__io": 1453, - "cts__design__io__post_repair": 1453, - "cts__design__io__pre_repair": 1453, - "cts__design__violations": 0, - "cts__mem__peak": 1071892.0, - "cts__power__internal__total": 0.0537262, - "cts__power__internal__total__post_repair": 0.0537021, - "cts__power__internal__total__pre_repair": 0.0536954, - "cts__power__leakage__total": 0.000713031, - "cts__power__leakage__total__post_repair": 0.000708373, - "cts__power__leakage__total__pre_repair": 0.000708339, - "cts__power__switching__total": 0.023271, - "cts__power__switching__total__post_repair": 0.0233918, - "cts__power__switching__total__pre_repair": 0.0233385, - "cts__power__total": 0.0777102, - "cts__power__total__post_repair": 0.0778022, - "cts__power__total__pre_repair": 0.0777422, - "cts__route__wirelength__estimated": 4611530.0, - "cts__runtime__total": "6:26.64", - "cts__timing__drv__hold_violation_count": 2, - "cts__timing__drv__hold_violation_count__post_repair": 235, - "cts__timing__drv__hold_violation_count__pre_repair": 235, - "cts__timing__drv__max_cap": 1, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": -0.0416603, - "cts__timing__drv__max_cap_limit__post_repair": 0.026849, - "cts__timing__drv__max_cap_limit__pre_repair": 0.026849, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 26, - "cts__timing__drv__max_slew__post_repair": 26, - "cts__timing__drv__max_slew__pre_repair": 26, - "cts__timing__drv__max_slew_limit": -0.0134579, - "cts__timing__drv__max_slew_limit__post_repair": -0.0103169, - "cts__timing__drv__max_slew_limit__pre_repair": -0.0103169, - "cts__timing__drv__setup_violation_count": 334, - "cts__timing__drv__setup_violation_count__post_repair": 8721, - "cts__timing__drv__setup_violation_count__pre_repair": 8653, - "cts__timing__setup__tns": -45.5209, - "cts__timing__setup__tns__post_repair": -8599.7, - "cts__timing__setup__tns__pre_repair": -8461.64, - "cts__timing__setup__ws": -0.434722, - "cts__timing__setup__ws__post_repair": -2.40634, - "cts__timing__setup__ws__pre_repair": -2.40634, - "design__io__hpwl": 2088683570, - "detailedplace__cpu__total": 76.16, - "detailedplace__design__core__area": 2806700.0, - "detailedplace__design__die__area": 2880000.0, - "detailedplace__design__instance__area": 1232850.0, - "detailedplace__design__instance__area__macros": 581231, - "detailedplace__design__instance__area__stdcell": 651622, - "detailedplace__design__instance__count": 87063, - "detailedplace__design__instance__count__macros": 26, - "detailedplace__design__instance__count__stdcell": 87037, - "detailedplace__design__instance__displacement__max": 49.325, - "detailedplace__design__instance__displacement__mean": 1.853, - "detailedplace__design__instance__displacement__total": 161348, - "detailedplace__design__instance__utilization": 0.439253, - "detailedplace__design__instance__utilization__stdcell": 0.292801, - "detailedplace__design__io": 1453, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 1011600.0, - "detailedplace__power__internal__total": 0.0370636, - "detailedplace__power__leakage__total": 0.000567649, - "detailedplace__power__switching__total": 0.00383749, - "detailedplace__power__total": 0.0414688, - "detailedplace__route__wirelength__estimated": 4511200.0, - "detailedplace__runtime__total": "1:18.87", - "detailedplace__timing__drv__hold_violation_count": 229, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.026849, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 26, - "detailedplace__timing__drv__max_slew_limit": -0.0103169, - "detailedplace__timing__drv__setup_violation_count": 9615, - "detailedplace__timing__setup__tns": -12428.4, - "detailedplace__timing__setup__ws": -3.44776, - "detailedroute__cpu__total": 4881.17, - "detailedroute__mem__peak": 7302180.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 36745, - "detailedroute__route__drc_errors__iter:2": 1868, - "detailedroute__route__drc_errors__iter:3": 965, - "detailedroute__route__drc_errors__iter:4": 18, - "detailedroute__route__drc_errors__iter:5": 5, - "detailedroute__route__drc_errors__iter:6": 3, - "detailedroute__route__drc_errors__iter:7": 2, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 78957, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 567343, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 567343, - "detailedroute__route__wirelength": 5207856, - "detailedroute__route__wirelength__iter:1": 5218187, - "detailedroute__route__wirelength__iter:2": 5208742, - "detailedroute__route__wirelength__iter:3": 5207956, - "detailedroute__route__wirelength__iter:4": 5207848, - "detailedroute__route__wirelength__iter:5": 5207851, - "detailedroute__route__wirelength__iter:6": 5207856, - "detailedroute__route__wirelength__iter:7": 5207856, - "detailedroute__route__wirelength__iter:8": 5207856, - "detailedroute__route__wirelength__iter:9": 5207856, - "detailedroute__runtime__total": "4:01.55", - "fillcell__cpu__total": 5.75, - "fillcell__mem__peak": 853264.0, - "fillcell__runtime__total": "0:06.44", - "finish__clock__skew__hold": 0.135461, - "finish__clock__skew__setup": 0.135461, - "finish__cpu__total": 147.63, - "finish__design__core__area": 2806700.0, - "finish__design__die__area": 2880000.0, - "finish__design__instance__area": 1267520.0, - "finish__design__instance__area__macros": 581231, - "finish__design__instance__area__stdcell": 686291, - "finish__design__instance__count": 88881, - "finish__design__instance__count__macros": 26, - "finish__design__instance__count__stdcell": 88855, - "finish__design__instance__utilization": 0.451605, - "finish__design__instance__utilization__stdcell": 0.30838, - "finish__design__io": 1453, - "finish__mem__peak": 1701440.0, - "finish__power__internal__total": 0.0538086, - "finish__power__leakage__total": 0.00073012, - "finish__power__switching__total": 0.0186891, - "finish__power__total": 0.0732278, - "finish__runtime__total": "2:30.11", - "finish__timing__drv__hold_violation_count": 47, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.244559, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.212449, - "finish__timing__drv__setup_violation_count": 463, - "finish__timing__setup__tns": -53.7282, - "finish__timing__setup__ws": -0.591192, - "finish__timing__wns_percent_delay": -10.454095, - "finish_merge__cpu__total": 29.28, - "finish_merge__mem__peak": 1400700.0, - "finish_merge__runtime__total": "0:30.33", - "floorplan__cpu__total": 19.07, - "floorplan__design__core__area": 2806700.0, - "floorplan__design__die__area": 2880000.0, - "floorplan__design__instance__area": 1054210.0, - "floorplan__design__instance__area__macros": 581231, - "floorplan__design__instance__area__stdcell": 472978, - "floorplan__design__instance__count": 70711, - "floorplan__design__instance__count__macros": 26, - "floorplan__design__instance__count__stdcell": 70685, - "floorplan__design__instance__utilization": 0.375604, - "floorplan__design__instance__utilization__stdcell": 0.212529, - "floorplan__design__io": 1453, - "floorplan__mem__peak": 654428.0, - "floorplan__power__internal__total": 0.0380715, - "floorplan__power__leakage__total": 0.000440195, - "floorplan__power__switching__total": 0.001384, - "floorplan__power__total": 0.0398957, - "floorplan__runtime__total": "0:19.67", - "floorplan__timing__setup__tns": -80282.3, - "floorplan__timing__setup__ws": -18.4129, - "floorplan_io__cpu__total": 3.7, - "floorplan_io__mem__peak": 437332.0, - "floorplan_io__runtime__total": "0:04.01", - "floorplan_macro__cpu__total": 1655.12, - "floorplan_macro__mem__peak": 626852.0, - "floorplan_macro__runtime__total": "1:10.06", - "floorplan_pdn__cpu__total": 20.08, - "floorplan_pdn__mem__peak": 731748.0, - "floorplan_pdn__runtime__total": "0:21.54", - "floorplan_tap__cpu__total": 6.67, - "floorplan_tap__mem__peak": 393668.0, - "floorplan_tap__runtime__total": "0:07.19", - "globalplace__cpu__total": 13458.22, - "globalplace__design__core__area": 2806700.0, - "globalplace__design__die__area": 2880000.0, - "globalplace__design__instance__area": 1066040.0, - "globalplace__design__instance__area__macros": 581231, - "globalplace__design__instance__area__stdcell": 484805, - "globalplace__design__instance__count": 83031, - "globalplace__design__instance__count__macros": 26, - "globalplace__design__instance__count__stdcell": 83005, - "globalplace__design__instance__utilization": 0.379818, - "globalplace__design__instance__utilization__stdcell": 0.217844, - "globalplace__design__io": 1453, - "globalplace__mem__peak": 1356068.0, - "globalplace__power__internal__total": 0.0402897, - "globalplace__power__leakage__total": 0.000440195, - "globalplace__power__switching__total": 0.0029983, - "globalplace__power__total": 0.0437282, - "globalplace__runtime__total": "8:21.83", - "globalplace__timing__setup__tns": -401988, - "globalplace__timing__setup__ws": -72.6701, - "globalplace_io__cpu__total": 3.9, - "globalplace_io__mem__peak": 465308.0, - "globalplace_io__runtime__total": "0:04.27", - "globalplace_skip_io__cpu__total": 35.6, - "globalplace_skip_io__mem__peak": 604968.0, - "globalplace_skip_io__runtime__total": "0:36.15", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.235088, - "globalroute__clock__skew__setup": 0.235088, - "globalroute__cpu__total": 612.33, - "globalroute__design__core__area": 2806700.0, - "globalroute__design__die__area": 2880000.0, - "globalroute__design__instance__area": 1267520.0, - "globalroute__design__instance__area__macros": 581231, - "globalroute__design__instance__area__stdcell": 686291, - "globalroute__design__instance__count": 88881, - "globalroute__design__instance__count__hold_buffer": 148, - "globalroute__design__instance__count__macros": 26, - "globalroute__design__instance__count__setup_buffer": 1, - "globalroute__design__instance__count__stdcell": 88855, - "globalroute__design__instance__displacement__max": 7.2, - "globalroute__design__instance__displacement__mean": 0.005, - "globalroute__design__instance__displacement__total": 480.2, - "globalroute__design__instance__utilization": 0.451605, - "globalroute__design__instance__utilization__stdcell": 0.30838, - "globalroute__design__io": 1453, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 2387508.0, - "globalroute__power__internal__total": 0.0539415, - "globalroute__power__leakage__total": 0.000730022, - "globalroute__power__switching__total": 0.0254052, - "globalroute__power__total": 0.0800768, - "globalroute__route__wirelength__estimated": 4627500.0, - "globalroute__runtime__total": "11:58.94", - "globalroute__timing__clock__slack": -1.308, - "globalroute__timing__drv__hold_violation_count": 2, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.127797, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0364321, - "globalroute__timing__drv__setup_violation_count": 4885, - "globalroute__timing__setup__tns": -2078.65, - "globalroute__timing__setup__ws": -1.3084, - "placeopt__cpu__total": 60.29, - "placeopt__design__core__area": 2806700.0, - "placeopt__design__core__area__pre_opt": 2806700.0, - "placeopt__design__die__area": 2880000.0, - "placeopt__design__die__area__pre_opt": 2880000.0, - "placeopt__design__instance__area": 1232850.0, - "placeopt__design__instance__area__macros": 581231, - "placeopt__design__instance__area__macros__pre_opt": 581231, - "placeopt__design__instance__area__pre_opt": 1066040.0, - "placeopt__design__instance__area__stdcell": 651622, - "placeopt__design__instance__area__stdcell__pre_opt": 484805, - "placeopt__design__instance__count": 87063, - "placeopt__design__instance__count__macros": 26, - "placeopt__design__instance__count__macros__pre_opt": 26, - "placeopt__design__instance__count__pre_opt": 83031, - "placeopt__design__instance__count__stdcell": 87037, - "placeopt__design__instance__count__stdcell__pre_opt": 83005, - "placeopt__design__instance__utilization": 0.439253, - "placeopt__design__instance__utilization__pre_opt": 0.379818, - "placeopt__design__instance__utilization__stdcell": 0.292801, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.217844, - "placeopt__design__io": 1453, - "placeopt__design__io__pre_opt": 1453, - "placeopt__mem__peak": 827536.0, - "placeopt__power__internal__total": 0.0365806, - "placeopt__power__internal__total__pre_opt": 0.0402897, - "placeopt__power__leakage__total": 0.000566101, - "placeopt__power__leakage__total__pre_opt": 0.000440195, - "placeopt__power__switching__total": 0.0018335, - "placeopt__power__switching__total__pre_opt": 0.0029983, - "placeopt__power__total": 0.0389802, - "placeopt__power__total__pre_opt": 0.0437282, - "placeopt__runtime__total": "1:01.60", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 2, - "placeopt__timing__drv__hold_violation_count": 229, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0442099, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0017036, - "placeopt__timing__drv__setup_violation_count": 9608, - "placeopt__timing__setup__tns": -12345.6, - "placeopt__timing__setup__tns__pre_opt": -401988, - "placeopt__timing__setup__ws": -3.44465, - "placeopt__timing__setup__ws__pre_opt": -72.6701, - "run__flow__design": "bp_multi", - "run__flow__generate_date": "2023-12-26 04:26", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-11590-g6ce3a8169", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "730fc586e5c9b66fa3a4f855f18f25797b654914", - "run__flow__scripts_commit": "9071cd835d9f42b4549f61a9cf98d3e28cb4a46e", - "run__flow__uuid": "7b0cb54d-b29b-47c3-b8d2-85622ec0bff3", - "run__flow__variant": "base", - "synth__cpu__total": 416.79, - "synth__design__instance__area__stdcell": 1088314.00035, - "synth__design__instance__count__stdcell": 78845.0, - "synth__mem__peak": 1467024.0, - "synth__runtime__total": "7:23.66", - "total_time": "0:46:22.860000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/bp_multi_top/rules-base.json b/flow/designs/tsmc65lp/bp_multi_top/rules-base.json deleted file mode 100644 index 753bbc19ea..0000000000 --- a/flow/designs/tsmc65lp/bp_multi_top/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 1244073.78, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 1417778, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 99288, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 8634, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 8634, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 5989034, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.83, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 1447770, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 4317, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 122, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -14.84, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/coyote/config.mk b/flow/designs/tsmc65lp/coyote/config.mk deleted file mode 100644 index 2d52982f86..0000000000 --- a/flow/designs/tsmc65lp/coyote/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -export DESIGN_NICKNAME = coyote -export DESIGN_NAME = bsg_rocket_node_client_rocc -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 - - -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 10 -export RTLMP_MIN_MACRO = 5 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v -#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_hier.sdc -export ABC_AREA = 1 - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w80_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w128_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg6_w44_bit.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg8_w64_bit.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w80_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w128_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_2rf_lg6_w44_bit_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_2rf_lg8_w64_bit_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w80_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg8_w128_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg6_w44_bit.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg8_w64_bit.gds2 - -export DIE_AREA = 0 0 2250 2250 -export CORE_AREA = 5 5 2245 2245 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:0-700 -exclude right:1500-2250 -exclude top:* -exclude bottom:* - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.10 -export REMOVE_BUFFER_TREE = 1 diff --git a/flow/designs/tsmc65lp/coyote/constraint.sdc b/flow/designs/tsmc65lp/coyote/constraint.sdc deleted file mode 100644 index 554a3d814a..0000000000 --- a/flow/designs/tsmc65lp/coyote/constraint.sdc +++ /dev/null @@ -1,2114 +0,0 @@ -############################################################################### -# Created by write_sdc -# Fri May 7 18:45:23 2021 -############################################################################### -current_design bsg_rocket_node_client_rocc -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name core_clk -period 16.8860 -waveform {0.0000 8.4430} [get_ports {clk_i}] -set_clock_transition 0.1500 [get_clocks {core_clk}] -set_clock_uncertainty -setup 0.2000 core_clk -set_clock_uncertainty -hold 0.2700 core_clk -set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 3.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] -############################################################################### -# Environment -############################################################################### -set_load -pin_load 3.0000 [get_ports {fsb_node_ready_o}] -set_load -pin_load 3.0000 [get_ports {fsb_node_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_exception_}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_host_id_}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_s_}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_req_ready_o}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_resp_ready_o}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[0]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[159]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[158]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[157]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[156]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[155]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[154]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[153]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[152]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[151]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[150]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[149]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[148]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[147]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[146]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[145]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[144]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[143]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[142]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[141]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[140]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[139]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[138]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[137]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[136]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[135]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[134]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[133]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[132]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[131]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[130]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[129]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[128]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[127]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[126]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[125]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[124]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[123]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[122]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[121]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[120]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[119]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[118]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[117]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[116]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[115]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[114]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[113]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[112]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[111]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[110]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[109]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[108]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[107]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[106]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[105]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[104]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[103]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[102]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[101]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[100]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[99]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[98]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[97]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[96]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[95]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[94]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[93]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[92]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[91]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[90]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[89]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[88]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[87]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[86]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[85]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[84]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[83]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[82]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[81]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[80]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[0]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[252]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[251]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[250]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[249]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[248]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[247]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[246]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[245]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[244]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[243]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[242]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[241]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[240]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[239]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[238]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[237]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[236]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[235]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[234]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[233]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[232]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[231]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[230]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[229]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[228]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[227]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[226]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[225]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[224]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[223]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[222]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[221]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[220]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[219]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[218]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[217]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[216]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[215]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[214]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[213]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[212]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[211]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[210]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[209]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[208]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[207]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[206]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[205]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[204]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[203]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[202]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[201]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[200]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[199]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[198]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[197]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[196]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[195]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[194]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[193]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[192]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[191]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[190]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[189]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[188]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[187]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[186]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[185]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[184]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[183]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[182]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[181]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[180]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[179]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[178]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[177]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[176]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[175]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[174]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[173]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[172]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[171]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[170]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[169]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[168]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[167]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[166]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[165]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[164]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[163]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[162]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[161]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[160]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[159]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[158]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[157]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[156]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[155]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[154]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[153]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[152]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[151]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[150]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[149]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[148]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[147]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[146]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[145]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[144]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[143]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[142]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[141]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[140]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[139]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[138]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[137]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[136]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[135]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[134]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[133]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[132]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[131]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[130]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[129]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[128]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[127]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[126]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[125]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[124]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[123]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[122]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[121]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[120]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[119]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[118]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[117]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[116]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[115]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[114]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[113]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[112]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[111]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[110]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[109]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[108]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[107]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[106]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[105]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[104]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[103]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[102]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[101]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[100]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[99]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[98]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[97]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[96]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[95]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[94]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[93]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[92]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[91]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[90]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[89]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[88]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[87]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[86]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[85]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[84]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[83]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[82]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[81]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[80]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[0]}] -set_input_transition 0.1500 [get_ports {clk_i}] -set_input_transition 0.1500 [get_ports {en_i}] -set_input_transition 0.1500 [get_ports {fsb_node_v_i}] -set_input_transition 0.1500 [get_ports {fsb_node_yumi_i}] -set_input_transition 0.1500 [get_ports {reset_i}] -set_input_transition 0.1500 [get_ports {rocc_cmd_ready_i}] -set_input_transition 0.1500 [get_ports {rocc_ctrl_i_busy_}] -set_input_transition 0.1500 [get_ports {rocc_ctrl_i_interrupt_}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_v_i}] -set_input_transition 0.1500 [get_ports {rocc_resp_v_i}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[79]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[78]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[77]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[76]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[75]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[74]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[73]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[72]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[71]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[70]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[69]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[68]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[67]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[66]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[65]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[64]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[63]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[62]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[61]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[60]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[59]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[58]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[57]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[56]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[55]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[54]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[53]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[52]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[51]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[50]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[49]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[48]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[47]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[46]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[45]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[44]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[43]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[42]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[41]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[40]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[39]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[38]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[37]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[36]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[35]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[34]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[33]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[32]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[31]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[30]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[29]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[28]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[27]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[26]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[25]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[24]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[23]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[22]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[21]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[20]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[19]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[18]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[17]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[16]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[15]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[14]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[13]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[12]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[11]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[10]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[9]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[8]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[7]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[6]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[5]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[4]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[3]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[2]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[1]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[0]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[122]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[121]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[120]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[119]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[118]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[117]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[116]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[115]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[114]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[113]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[112]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[111]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[110]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[109]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[108]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[107]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[106]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[105]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[104]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[103]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[102]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[101]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[100]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[99]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[98]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[97]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[96]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[95]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[94]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[93]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[92]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[91]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[90]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[89]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[88]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[87]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[86]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[85]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[84]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[83]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[82]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[81]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[80]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[79]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[78]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[77]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[76]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[75]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[74]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[73]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[72]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[71]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[70]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[69]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[68]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[67]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[66]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[65]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[64]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[63]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[62]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[61]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[60]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[59]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[58]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[57]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[56]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[55]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[54]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[53]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[52]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[51]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[50]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[49]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[48]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[47]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[46]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[45]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[44]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[43]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[42]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[41]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[40]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[39]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[38]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[37]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[36]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[35]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[34]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[33]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[32]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[68]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[67]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[66]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[65]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[64]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[63]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[62]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[61]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[60]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[59]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[58]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[57]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[56]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[55]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[54]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[53]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[52]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[51]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[50]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[49]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[48]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[47]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[46]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[45]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[44]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[43]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[42]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[41]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[40]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[39]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[38]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[37]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[36]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[35]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[34]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[33]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[32]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[31]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[30]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[29]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[28]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[27]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[26]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[25]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[24]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[23]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[22]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[21]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[20]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[19]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[18]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[17]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[16]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[15]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[14]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[13]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[12]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[11]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[10]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[9]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[8]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[7]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[6]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[5]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[4]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[3]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[2]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[1]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[0]}] -############################################################################### -# Design Rules -############################################################################### -set_max_transition 0.2000 [current_design] -set_max_transition 0.1500 [get_ports {fsb_node_ready_o}] -set_max_transition 0.1500 [get_ports {fsb_node_v_o}] -set_max_transition 0.1500 [get_ports {rocc_cmd_v_o}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_exception_}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_host_id_}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_s_}] -set_max_transition 0.1500 [get_ports {rocc_mem_req_ready_o}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_v_o}] -set_max_transition 0.1500 [get_ports {rocc_resp_ready_o}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[79]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[78]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[77]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[76]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[75]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[74]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[73]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[72]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[71]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[70]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[69]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[68]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[67]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[66]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[65]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[64]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[63]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[62]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[61]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[60]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[59]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[58]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[57]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[56]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[55]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[54]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[53]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[52]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[51]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[50]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[49]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[48]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[47]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[46]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[45]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[44]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[43]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[42]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[41]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[40]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[39]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[38]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[37]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[36]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[35]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[34]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[33]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[32]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[31]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[30]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[29]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[28]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[27]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[26]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[25]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[24]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[23]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[22]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[21]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[20]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[19]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[18]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[17]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[16]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[15]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[14]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[13]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[12]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[11]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[10]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[9]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[8]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[7]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[6]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[5]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[4]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[3]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[2]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[1]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[0]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[159]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[158]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[157]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[156]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[155]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[154]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[153]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[152]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[151]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[150]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[149]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[148]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[147]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[146]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[145]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[144]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[143]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[142]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[141]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[140]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[139]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[138]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[137]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[136]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[135]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[134]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[133]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[132]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[131]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[130]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[129]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[128]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[127]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[126]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[125]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[124]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[123]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[122]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[121]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[120]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[119]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[118]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[117]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[116]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[115]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[114]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[113]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[112]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[111]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[110]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[109]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[108]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[107]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[106]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[105]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[104]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[103]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[102]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[101]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[100]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[99]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[98]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[97]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[96]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[95]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[94]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[93]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[92]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[91]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[90]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[89]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[88]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[87]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[86]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[85]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[84]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[83]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[82]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[81]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[80]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[79]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[78]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[77]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[76]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[75]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[74]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[73]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[72]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[71]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[70]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[69]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[68]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[67]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[66]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[65]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[64]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[63]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[62]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[61]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[60]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[59]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[58]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[57]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[56]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[55]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[54]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[53]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[52]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[51]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[50]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[49]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[48]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[47]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[46]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[45]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[44]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[43]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[42]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[41]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[40]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[39]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[38]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[37]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[36]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[35]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[34]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[33]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[32]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[31]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[30]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[29]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[28]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[27]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[26]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[25]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[24]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[23]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[22]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[21]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[20]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[19]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[18]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[17]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[16]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[15]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[14]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[13]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[12]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[11]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[10]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[9]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[8]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[7]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[6]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[5]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[4]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[3]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[2]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[1]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[0]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[252]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[251]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[250]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[249]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[248]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[247]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[246]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[245]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[244]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[243]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[242]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[241]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[240]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[239]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[238]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[237]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[236]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[235]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[234]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[233]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[232]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[231]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[230]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[229]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[228]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[227]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[226]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[225]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[224]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[223]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[222]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[221]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[220]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[219]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[218]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[217]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[216]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[215]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[214]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[213]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[212]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[211]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[210]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[209]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[208]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[207]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[206]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[205]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[204]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[203]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[202]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[201]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[200]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[199]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[198]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[197]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[196]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[195]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[194]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[193]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[192]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[191]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[190]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[189]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[188]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[187]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[186]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[185]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[184]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[183]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[182]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[181]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[180]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[179]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[178]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[177]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[176]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[175]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[174]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[173]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[172]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[171]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[170]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[169]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[168]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[167]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[166]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[165]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[164]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[163]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[162]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[161]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[160]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[159]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[158]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[157]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[156]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[155]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[154]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[153]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[152]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[151]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[150]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[149]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[148]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[147]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[146]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[145]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[144]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[143]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[142]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[141]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[140]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[139]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[138]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[137]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[136]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[135]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[134]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[133]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[132]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[131]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[130]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[129]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[128]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[127]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[126]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[125]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[124]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[123]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[122]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[121]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[120]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[119]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[118]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[117]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[116]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[115]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[114]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[113]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[112]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[111]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[110]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[109]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[108]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[107]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[106]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[105]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[104]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[103]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[102]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[101]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[100]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[99]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[98]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[97]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[96]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[95]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[94]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[93]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[92]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[91]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[90]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[89]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[88]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[87]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[86]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[85]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[84]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[83]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[82]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[81]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[80]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[79]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[78]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[77]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[76]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[75]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[74]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[73]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[72]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[71]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[70]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[69]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[68]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[67]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[66]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[65]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[64]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[63]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[62]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[61]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[60]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[59]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[58]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[57]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[56]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[55]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[54]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[53]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[52]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[51]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[50]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[49]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[48]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[47]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[46]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[45]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[44]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[43]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[42]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[41]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[40]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[39]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[38]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[37]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[36]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[35]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[34]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[33]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[32]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[31]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[30]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[29]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[28]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[27]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[26]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[25]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[24]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[23]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[22]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[21]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[20]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[19]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[18]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[17]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[16]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[15]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[14]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[13]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[12]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[11]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[10]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[9]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[8]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[7]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[6]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[5]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[4]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[3]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[2]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[1]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[0]}] -set_max_fanout 10.0000 [current_design] diff --git a/flow/designs/tsmc65lp/coyote/constraint_hier.sdc b/flow/designs/tsmc65lp/coyote/constraint_hier.sdc deleted file mode 100644 index 554a3d814a..0000000000 --- a/flow/designs/tsmc65lp/coyote/constraint_hier.sdc +++ /dev/null @@ -1,2114 +0,0 @@ -############################################################################### -# Created by write_sdc -# Fri May 7 18:45:23 2021 -############################################################################### -current_design bsg_rocket_node_client_rocc -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name core_clk -period 16.8860 -waveform {0.0000 8.4430} [get_ports {clk_i}] -set_clock_transition 0.1500 [get_clocks {core_clk}] -set_clock_uncertainty -setup 0.2000 core_clk -set_clock_uncertainty -hold 0.2700 core_clk -set_clock_latency -source 0.0000 [get_clocks {core_clk}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {en_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {reset_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 3.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 5.2600 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 5.0100 -clock [get_clocks {core_clk}] -add_delay [get_ports {rocc_resp_ready_o}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T112/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T42/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T79/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/data/T9/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem0/macro_mem0}] -set_disable_timing -from {CLKA} -to {CLKB} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_disable_timing -from {CLKB} -to {CLKA} [get_cells {r2f/rocket/RocketTile/dcache/meta/tag_arr/mem/macro_mem1/macro_mem0}] -set_false_path\ - -to [list [get_ports {rocc_ctrl_o_exception_}]\ - [get_ports {rocc_ctrl_o_host_id_}]\ - [get_ports {rocc_ctrl_o_s_}]] -############################################################################### -# Environment -############################################################################### -set_load -pin_load 3.0000 [get_ports {fsb_node_ready_o}] -set_load -pin_load 3.0000 [get_ports {fsb_node_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_exception_}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_host_id_}] -set_load -pin_load 3.0000 [get_ports {rocc_ctrl_o_s_}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_req_ready_o}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_v_o}] -set_load -pin_load 3.0000 [get_ports {rocc_resp_ready_o}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {fsb_node_data_o[0]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[159]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[158]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[157]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[156]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[155]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[154]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[153]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[152]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[151]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[150]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[149]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[148]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[147]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[146]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[145]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[144]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[143]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[142]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[141]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[140]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[139]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[138]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[137]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[136]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[135]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[134]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[133]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[132]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[131]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[130]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[129]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[128]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[127]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[126]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[125]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[124]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[123]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[122]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[121]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[120]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[119]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[118]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[117]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[116]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[115]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[114]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[113]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[112]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[111]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[110]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[109]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[108]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[107]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[106]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[105]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[104]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[103]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[102]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[101]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[100]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[99]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[98]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[97]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[96]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[95]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[94]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[93]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[92]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[91]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[90]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[89]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[88]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[87]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[86]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[85]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[84]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[83]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[82]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[81]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[80]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {rocc_cmd_data_o[0]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[252]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[251]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[250]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[249]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[248]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[247]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[246]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[245]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[244]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[243]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[242]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[241]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[240]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[239]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[238]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[237]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[236]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[235]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[234]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[233]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[232]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[231]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[230]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[229]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[228]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[227]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[226]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[225]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[224]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[223]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[222]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[221]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[220]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[219]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[218]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[217]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[216]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[215]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[214]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[213]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[212]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[211]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[210]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[209]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[208]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[207]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[206]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[205]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[204]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[203]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[202]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[201]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[200]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[199]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[198]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[197]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[196]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[195]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[194]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[193]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[192]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[191]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[190]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[189]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[188]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[187]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[186]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[185]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[184]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[183]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[182]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[181]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[180]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[179]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[178]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[177]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[176]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[175]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[174]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[173]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[172]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[171]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[170]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[169]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[168]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[167]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[166]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[165]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[164]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[163]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[162]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[161]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[160]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[159]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[158]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[157]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[156]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[155]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[154]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[153]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[152]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[151]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[150]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[149]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[148]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[147]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[146]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[145]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[144]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[143]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[142]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[141]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[140]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[139]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[138]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[137]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[136]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[135]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[134]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[133]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[132]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[131]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[130]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[129]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[128]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[127]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[126]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[125]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[124]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[123]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[122]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[121]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[120]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[119]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[118]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[117]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[116]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[115]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[114]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[113]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[112]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[111]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[110]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[109]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[108]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[107]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[106]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[105]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[104]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[103]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[102]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[101]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[100]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[99]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[98]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[97]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[96]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[95]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[94]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[93]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[92]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[91]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[90]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[89]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[88]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[87]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[86]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[85]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[84]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[83]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[82]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[81]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[80]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[79]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[78]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[77]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[76]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[75]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[74]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[73]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[72]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[71]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[70]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[69]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[68]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[67]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[66]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[65]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[64]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[63]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[62]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[61]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[60]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[59]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[58]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[57]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[56]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[55]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[54]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[53]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[52]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[51]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[50]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[49]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[48]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[47]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[46]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[45]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[44]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[43]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[42]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[41]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[40]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[39]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[38]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[37]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[36]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[35]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[34]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[33]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[32]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[31]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[30]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[29]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[28]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[27]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[26]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[25]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[24]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[23]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[22]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[21]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[20]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[19]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[18]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[17]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[16]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[15]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[14]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[13]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[12]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[11]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[10]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[9]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[8]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[7]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[6]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[5]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[4]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[3]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[2]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[1]}] -set_load -pin_load 3.0000 [get_ports {rocc_mem_resp_data_o[0]}] -set_input_transition 0.1500 [get_ports {clk_i}] -set_input_transition 0.1500 [get_ports {en_i}] -set_input_transition 0.1500 [get_ports {fsb_node_v_i}] -set_input_transition 0.1500 [get_ports {fsb_node_yumi_i}] -set_input_transition 0.1500 [get_ports {reset_i}] -set_input_transition 0.1500 [get_ports {rocc_cmd_ready_i}] -set_input_transition 0.1500 [get_ports {rocc_ctrl_i_busy_}] -set_input_transition 0.1500 [get_ports {rocc_ctrl_i_interrupt_}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_v_i}] -set_input_transition 0.1500 [get_ports {rocc_resp_v_i}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[79]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[78]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[77]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[76]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[75]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[74]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[73]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[72]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[71]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[70]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[69]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[68]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[67]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[66]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[65]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[64]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[63]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[62]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[61]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[60]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[59]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[58]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[57]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[56]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[55]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[54]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[53]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[52]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[51]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[50]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[49]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[48]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[47]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[46]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[45]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[44]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[43]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[42]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[41]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[40]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[39]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[38]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[37]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[36]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[35]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[34]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[33]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[32]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[31]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[30]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[29]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[28]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[27]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[26]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[25]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[24]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[23]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[22]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[21]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[20]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[19]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[18]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[17]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[16]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[15]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[14]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[13]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[12]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[11]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[10]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[9]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[8]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[7]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[6]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[5]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[4]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[3]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[2]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[1]}] -set_input_transition 0.1500 [get_ports {fsb_node_data_i[0]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[122]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[121]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[120]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[119]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[118]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[117]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[116]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[115]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[114]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[113]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[112]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[111]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[110]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[109]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[108]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[107]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[106]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[105]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[104]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[103]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[102]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[101]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[100]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[99]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[98]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[97]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[96]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[95]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[94]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[93]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[92]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[91]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[90]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[89]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[88]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[87]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[86]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[85]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[84]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[83]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[82]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[81]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[80]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[79]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[78]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[77]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[76]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[75]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[74]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[73]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[72]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[71]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[70]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[69]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[68]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[67]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[66]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[65]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[64]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[63]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[62]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[61]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[60]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[59]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[58]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[57]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[56]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[55]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[54]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[53]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[52]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[51]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[50]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[49]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[48]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[47]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[46]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[45]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[44]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[43]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[42]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[41]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[40]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[39]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[38]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[37]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[36]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[35]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[34]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[33]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[32]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[31]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[30]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[29]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[28]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[27]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[26]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[25]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[24]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[23]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[22]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[21]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[20]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[19]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[18]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[17]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[16]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[15]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[14]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[13]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[12]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[11]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[10]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[9]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[8]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[7]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[6]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[5]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[4]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[3]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[2]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[1]}] -set_input_transition 0.1500 [get_ports {rocc_mem_req_data_i[0]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[68]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[67]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[66]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[65]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[64]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[63]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[62]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[61]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[60]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[59]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[58]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[57]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[56]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[55]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[54]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[53]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[52]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[51]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[50]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[49]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[48]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[47]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[46]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[45]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[44]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[43]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[42]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[41]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[40]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[39]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[38]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[37]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[36]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[35]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[34]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[33]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[32]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[31]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[30]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[29]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[28]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[27]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[26]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[25]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[24]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[23]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[22]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[21]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[20]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[19]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[18]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[17]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[16]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[15]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[14]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[13]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[12]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[11]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[10]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[9]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[8]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[7]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[6]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[5]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[4]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[3]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[2]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[1]}] -set_input_transition 0.1500 [get_ports {rocc_resp_data_i[0]}] -############################################################################### -# Design Rules -############################################################################### -set_max_transition 0.2000 [current_design] -set_max_transition 0.1500 [get_ports {fsb_node_ready_o}] -set_max_transition 0.1500 [get_ports {fsb_node_v_o}] -set_max_transition 0.1500 [get_ports {rocc_cmd_v_o}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_exception_}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_host_id_}] -set_max_transition 0.1500 [get_ports {rocc_ctrl_o_s_}] -set_max_transition 0.1500 [get_ports {rocc_mem_req_ready_o}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_v_o}] -set_max_transition 0.1500 [get_ports {rocc_resp_ready_o}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[79]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[78]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[77]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[76]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[75]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[74]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[73]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[72]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[71]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[70]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[69]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[68]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[67]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[66]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[65]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[64]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[63]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[62]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[61]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[60]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[59]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[58]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[57]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[56]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[55]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[54]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[53]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[52]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[51]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[50]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[49]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[48]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[47]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[46]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[45]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[44]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[43]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[42]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[41]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[40]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[39]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[38]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[37]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[36]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[35]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[34]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[33]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[32]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[31]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[30]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[29]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[28]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[27]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[26]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[25]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[24]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[23]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[22]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[21]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[20]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[19]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[18]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[17]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[16]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[15]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[14]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[13]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[12]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[11]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[10]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[9]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[8]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[7]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[6]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[5]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[4]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[3]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[2]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[1]}] -set_max_transition 0.1500 [get_ports {fsb_node_data_o[0]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[159]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[158]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[157]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[156]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[155]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[154]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[153]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[152]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[151]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[150]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[149]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[148]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[147]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[146]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[145]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[144]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[143]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[142]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[141]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[140]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[139]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[138]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[137]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[136]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[135]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[134]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[133]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[132]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[131]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[130]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[129]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[128]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[127]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[126]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[125]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[124]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[123]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[122]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[121]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[120]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[119]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[118]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[117]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[116]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[115]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[114]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[113]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[112]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[111]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[110]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[109]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[108]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[107]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[106]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[105]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[104]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[103]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[102]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[101]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[100]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[99]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[98]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[97]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[96]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[95]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[94]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[93]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[92]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[91]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[90]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[89]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[88]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[87]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[86]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[85]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[84]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[83]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[82]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[81]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[80]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[79]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[78]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[77]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[76]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[75]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[74]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[73]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[72]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[71]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[70]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[69]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[68]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[67]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[66]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[65]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[64]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[63]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[62]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[61]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[60]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[59]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[58]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[57]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[56]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[55]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[54]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[53]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[52]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[51]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[50]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[49]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[48]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[47]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[46]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[45]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[44]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[43]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[42]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[41]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[40]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[39]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[38]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[37]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[36]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[35]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[34]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[33]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[32]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[31]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[30]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[29]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[28]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[27]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[26]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[25]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[24]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[23]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[22]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[21]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[20]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[19]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[18]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[17]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[16]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[15]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[14]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[13]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[12]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[11]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[10]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[9]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[8]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[7]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[6]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[5]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[4]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[3]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[2]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[1]}] -set_max_transition 0.1500 [get_ports {rocc_cmd_data_o[0]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[252]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[251]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[250]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[249]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[248]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[247]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[246]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[245]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[244]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[243]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[242]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[241]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[240]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[239]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[238]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[237]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[236]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[235]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[234]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[233]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[232]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[231]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[230]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[229]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[228]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[227]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[226]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[225]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[224]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[223]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[222]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[221]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[220]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[219]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[218]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[217]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[216]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[215]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[214]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[213]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[212]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[211]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[210]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[209]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[208]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[207]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[206]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[205]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[204]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[203]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[202]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[201]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[200]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[199]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[198]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[197]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[196]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[195]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[194]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[193]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[192]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[191]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[190]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[189]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[188]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[187]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[186]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[185]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[184]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[183]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[182]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[181]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[180]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[179]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[178]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[177]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[176]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[175]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[174]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[173]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[172]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[171]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[170]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[169]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[168]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[167]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[166]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[165]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[164]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[163]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[162]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[161]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[160]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[159]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[158]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[157]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[156]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[155]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[154]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[153]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[152]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[151]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[150]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[149]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[148]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[147]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[146]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[145]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[144]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[143]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[142]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[141]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[140]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[139]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[138]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[137]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[136]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[135]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[134]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[133]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[132]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[131]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[130]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[129]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[128]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[127]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[126]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[125]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[124]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[123]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[122]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[121]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[120]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[119]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[118]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[117]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[116]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[115]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[114]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[113]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[112]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[111]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[110]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[109]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[108]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[107]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[106]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[105]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[104]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[103]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[102]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[101]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[100]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[99]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[98]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[97]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[96]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[95]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[94]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[93]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[92]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[91]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[90]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[89]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[88]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[87]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[86]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[85]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[84]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[83]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[82]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[81]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[80]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[79]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[78]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[77]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[76]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[75]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[74]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[73]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[72]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[71]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[70]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[69]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[68]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[67]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[66]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[65]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[64]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[63]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[62]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[61]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[60]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[59]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[58]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[57]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[56]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[55]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[54]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[53]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[52]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[51]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[50]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[49]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[48]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[47]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[46]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[45]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[44]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[43]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[42]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[41]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[40]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[39]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[38]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[37]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[36]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[35]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[34]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[33]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[32]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[31]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[30]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[29]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[28]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[27]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[26]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[25]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[24]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[23]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[22]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[21]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[20]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[19]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[18]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[17]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[16]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[15]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[14]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[13]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[12]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[11]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[10]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[9]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[8]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[7]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[6]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[5]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[4]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[3]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[2]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[1]}] -set_max_transition 0.1500 [get_ports {rocc_mem_resp_data_o[0]}] -set_max_fanout 10.0000 [current_design] diff --git a/flow/designs/tsmc65lp/coyote/macros.v b/flow/designs/tsmc65lp/coyote/macros.v deleted file mode 100644 index fe9e2c1c8d..0000000000 --- a/flow/designs/tsmc65lp/coyote/macros.v +++ /dev/null @@ -1,125 +0,0 @@ -module mem_1rf_lg6_w80_bit (Q, CLK, CEN, WEN, A, D, EMA, EMAW, GWEN, RET1N); - - output [79:0] Q; - input CLK; - input CEN; - input [79:0] WEN; - input [5:0] A; - input [79:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input GWEN; - input RET1N; - - tsmc65lp_1rf_lg6_w80_bit - macro_mem - ( - .Q(Q), - .CLK(CLK), - .CEN(CEN), - .WEN(WEN), - .A(A), - .D(D), - .EMA(EMA), - .EMAW(EMAW), - .GWEN(GWEN), - .RET1N(RET1N) - ); - -endmodule - -module mem_1rf_lg8_w128_all (Q, CLK, CEN, WEN, A, D, EMA, EMAW, RET1N); - - output [127:0] Q; - input CLK; - input CEN; - input WEN; - input [7:0] A; - input [127:0] D; - input [2:0] EMA; - input [1:0] EMAW; - input RET1N; - - - tsmc65lp_1rf_lg8_w128_all - macro_mem - ( - .Q(Q), - .CLK(CLK), - .CEN(CEN), - .WEN(WEN), - .A(A), - .D(D), - .EMA(EMA), - .EMAW(EMAW), - .RET1N(RET1N) - ); -endmodule - -module mem_2rf_lg6_w44_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [43:0] QA; - input CLKA; - input CENA; - input [5:0] AA; - input CLKB; - input CENB; - input [43:0] WENB; - input [5:0] AB; - input [43:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - tsmc65lp_2rf_lg6_w44_bit - macro_mem0 - ( - .CLKA(CLKA), - .CLKB(CLKB), - .AA(AA), - .CENA(CENA), - .QA(QA), - .AB(AB), - .DB(DB), - .CENB(CENB), - .WENB(WENB), - .EMAA(EMAA), - .EMAB(EMAB), - .RET1N(RET1N) - ); - -endmodule - -module mem_2rf_lg8_w64_bit (QA, CLKA, CENA, AA, CLKB, CENB, WENB, AB, DB, EMAA, EMAB, RET1N); - - output [63:0] QA; - input CLKA; - input CENA; - input [7:0] AA; - input CLKB; - input CENB; - input [63:0] WENB; - input [7:0] AB; - input [63:0] DB; - input [2:0] EMAA; - input [2:0] EMAB; - input RET1N; - - tsmc65lp_2rf_lg8_w64_bit - macro_mem0 - ( - .CLKA(CLKA), - .CLKB(CLKB), - .AA(AA), - .CENA(CENA), - .QA(QA), - .AB(AB), - .DB(DB), - .CENB(CENB), - .WENB(WENB), - .EMAA(EMAA), - .EMAB(EMAB), - .RET1N(RET1N) - ); - -endmodule diff --git a/flow/designs/tsmc65lp/coyote/metadata-base-ok.json b/flow/designs/tsmc65lp/coyote/metadata-base-ok.json deleted file mode 100644 index 4b201f71ef..0000000000 --- a/flow/designs/tsmc65lp/coyote/metadata-base-ok.json +++ /dev/null @@ -1,354 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clk: 16.8860" - ], - "cts__clock__skew__hold": 0.345091, - "cts__clock__skew__hold__post_repair": 0.320757, - "cts__clock__skew__hold__pre_repair": 0.320757, - "cts__clock__skew__setup": 0.345091, - "cts__clock__skew__setup__post_repair": 0.320757, - "cts__clock__skew__setup__pre_repair": 0.320757, - "cts__cpu__total": 548.61, - "cts__design__core__area": 5010430.0, - "cts__design__core__area__post_repair": 5010430.0, - "cts__design__core__area__pre_repair": 5010430.0, - "cts__design__die__area": 5062500.0, - "cts__design__die__area__post_repair": 5062500.0, - "cts__design__die__area__pre_repair": 5062500.0, - "cts__design__instance__area": 2639190.0, - "cts__design__instance__area__macros": 390312, - "cts__design__instance__area__macros__post_repair": 390312, - "cts__design__instance__area__macros__pre_repair": 390312, - "cts__design__instance__area__post_repair": 2635600.0, - "cts__design__instance__area__pre_repair": 2635550.0, - "cts__design__instance__area__stdcell": 2248880.0, - "cts__design__instance__area__stdcell__post_repair": 2245290.0, - "cts__design__instance__area__stdcell__pre_repair": 2245240.0, - "cts__design__instance__count": 332264, - "cts__design__instance__count__hold_buffer": 529, - "cts__design__instance__count__macros": 15, - "cts__design__instance__count__macros__post_repair": 15, - "cts__design__instance__count__macros__pre_repair": 15, - "cts__design__instance__count__post_repair": 331735, - "cts__design__instance__count__pre_repair": 331732, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 332249, - "cts__design__instance__count__stdcell__post_repair": 331720, - "cts__design__instance__count__stdcell__pre_repair": 331717, - "cts__design__instance__displacement__max": 33.382, - "cts__design__instance__displacement__mean": 0.011, - "cts__design__instance__displacement__total": 3668.03, - "cts__design__instance__utilization": 0.526739, - "cts__design__instance__utilization__post_repair": 0.526023, - "cts__design__instance__utilization__pre_repair": 0.526014, - "cts__design__instance__utilization__stdcell": 0.486758, - "cts__design__instance__utilization__stdcell__post_repair": 0.485981, - "cts__design__instance__utilization__stdcell__pre_repair": 0.485971, - "cts__design__io": 784, - "cts__design__io__post_repair": 784, - "cts__design__io__pre_repair": 784, - "cts__design__violations": 0, - "cts__mem__peak": 2222612.0, - "cts__power__internal__total": 0.614182, - "cts__power__internal__total__post_repair": 0.614197, - "cts__power__internal__total__pre_repair": 0.614182, - "cts__power__leakage__total": 0.00178513, - "cts__power__leakage__total__post_repair": 0.00178267, - "cts__power__leakage__total__pre_repair": 0.00178256, - "cts__power__switching__total": 0.598558, - "cts__power__switching__total__post_repair": 0.59529, - "cts__power__switching__total__pre_repair": 0.595268, - "cts__power__total": 1.21453, - "cts__power__total__post_repair": 1.21127, - "cts__power__total__pre_repair": 1.21123, - "cts__route__wirelength__estimated": 12225000.0, - "cts__runtime__total": "9:34.17", - "cts__timing__drv__hold_violation_count": 20, - "cts__timing__drv__hold_violation_count__post_repair": 1352, - "cts__timing__drv__hold_violation_count__pre_repair": 1352, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.939481, - "cts__timing__drv__max_cap_limit__post_repair": 0.939481, - "cts__timing__drv__max_cap_limit__pre_repair": 0.939481, - "cts__timing__drv__max_fanout": 1709, - "cts__timing__drv__max_fanout__post_repair": 1709, - "cts__timing__drv__max_fanout__pre_repair": 1709, - "cts__timing__drv__max_fanout_limit": 10, - "cts__timing__drv__max_fanout_limit__post_repair": 10, - "cts__timing__drv__max_fanout_limit__pre_repair": 10, - "cts__timing__drv__max_slew": 2052, - "cts__timing__drv__max_slew__post_repair": 2032, - "cts__timing__drv__max_slew__pre_repair": 2033, - "cts__timing__drv__max_slew_limit": -8.58651, - "cts__timing__drv__max_slew_limit__post_repair": -8.58647, - "cts__timing__drv__max_slew_limit__pre_repair": -8.58647, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 0, - "cts__timing__drv__setup_violation_count__pre_repair": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__tns__post_repair": 0, - "cts__timing__setup__tns__pre_repair": 0, - "cts__timing__setup__ws": 2.29997, - "cts__timing__setup__ws__post_repair": 2.32103, - "cts__timing__setup__ws__pre_repair": 2.32103, - "cts_fill__cpu__total": 10.15, - "cts_fill__mem__peak": 1493768.0, - "cts_fill__runtime__total": "0:12.07", - "design__io__hpwl": 2287976068, - "detailedplace__cpu__total": 240.97, - "detailedplace__design__core__area": 5010430.0, - "detailedplace__design__die__area": 5062500.0, - "detailedplace__design__instance__area": 2625060.0, - "detailedplace__design__instance__area__macros": 390312, - "detailedplace__design__instance__area__stdcell": 2234750.0, - "detailedplace__design__instance__count": 329545, - "detailedplace__design__instance__count__macros": 15, - "detailedplace__design__instance__count__stdcell": 329530, - "detailedplace__design__instance__displacement__max": 92.3, - "detailedplace__design__instance__displacement__mean": 2.2065, - "detailedplace__design__instance__displacement__total": 727275, - "detailedplace__design__instance__utilization": 0.523918, - "detailedplace__design__instance__utilization__stdcell": 0.483699, - "detailedplace__design__io": 784, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 2050944.0, - "detailedplace__power__internal__total": 0.611755, - "detailedplace__power__leakage__total": 0.00176983, - "detailedplace__power__switching__total": 0.583757, - "detailedplace__power__total": 1.19728, - "detailedplace__route__wirelength__estimated": 12283400.0, - "detailedplace__runtime__total": "4:09.90", - "detailedplace__timing__drv__hold_violation_count": 1409, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.939481, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 10, - "detailedplace__timing__drv__max_slew": 1556, - "detailedplace__timing__drv__max_slew_limit": -8.58688, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 2.35224, - "detailedroute__cpu__total": 11731.9, - "detailedroute__mem__peak": 14635880.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 119826, - "detailedroute__route__drc_errors__iter:2": 26826, - "detailedroute__route__drc_errors__iter:3": 23579, - "detailedroute__route__drc_errors__iter:4": 65, - "detailedroute__route__drc_errors__iter:5": 5, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 311761, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2018704, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2018704, - "detailedroute__route__wirelength": 13638840, - "detailedroute__route__wirelength__iter:1": 13678593, - "detailedroute__route__wirelength__iter:2": 13649031, - "detailedroute__route__wirelength__iter:3": 13639575, - "detailedroute__route__wirelength__iter:4": 13638848, - "detailedroute__route__wirelength__iter:5": 13638841, - "detailedroute__route__wirelength__iter:6": 13638840, - "detailedroute__route__wirelength__iter:7": 13638840, - "detailedroute__runtime__total": "14:59.99", - "finish__clock__skew__hold": 0.260648, - "finish__clock__skew__setup": 0.260648, - "finish__cpu__total": 477.91, - "finish__design__core__area": 5010430.0, - "finish__design__die__area": 5062500.0, - "finish__design__instance__area": 2639190.0, - "finish__design__instance__area__macros": 390312, - "finish__design__instance__area__stdcell": 2248880.0, - "finish__design__instance__count": 332264, - "finish__design__instance__count__macros": 15, - "finish__design__instance__count__stdcell": 332249, - "finish__design__instance__utilization": 0.526739, - "finish__design__instance__utilization__stdcell": 0.486758, - "finish__design__io": 784, - "finish__mem__peak": 4834156.0, - "finish__power__internal__total": 0.615561, - "finish__power__leakage__total": 0.00178513, - "finish__power__switching__total": 0.504874, - "finish__power__total": 1.12222, - "finish__runtime__total": "8:01.82", - "finish__timing__drv__hold_violation_count": 599, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.942543, - "finish__timing__drv__max_fanout": 1709, - "finish__timing__drv__max_fanout_limit": 10, - "finish__timing__drv__max_slew": 964, - "finish__timing__drv__max_slew_limit": -9.0327, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 3.36519, - "finish__timing__wns_percent_delay": 22.085133, - "finish_merge__cpu__total": 84.89, - "finish_merge__mem__peak": 3483560.0, - "finish_merge__runtime__total": "1:28.74", - "floorplan__cpu__total": 59.45, - "floorplan__design__core__area": 5010430.0, - "floorplan__design__die__area": 5062500.0, - "floorplan__design__instance__area": 1973060.0, - "floorplan__design__instance__area__macros": 390312, - "floorplan__design__instance__area__stdcell": 1582750.0, - "floorplan__design__instance__count": 267249, - "floorplan__design__instance__count__macros": 15, - "floorplan__design__instance__count__stdcell": 267234, - "floorplan__design__instance__utilization": 0.393791, - "floorplan__design__instance__utilization__stdcell": 0.342578, - "floorplan__design__io": 784, - "floorplan__mem__peak": 1391824.0, - "floorplan__power__internal__total": 0.488011, - "floorplan__power__leakage__total": 0.000976359, - "floorplan__power__switching__total": 0.331844, - "floorplan__power__total": 0.820832, - "floorplan__runtime__total": "1:01.49", - "floorplan__timing__setup__tns": -48458.2, - "floorplan__timing__setup__ws": -42.2539, - "floorplan_io__cpu__total": 6.08, - "floorplan_io__mem__peak": 764312.0, - "floorplan_io__runtime__total": "0:06.88", - "floorplan_macro__cpu__total": 209.37, - "floorplan_macro__mem__peak": 1362024.0, - "floorplan_macro__runtime__total": "1:23.23", - "floorplan_pdn__cpu__total": 19.94, - "floorplan_pdn__mem__peak": 1031316.0, - "floorplan_pdn__runtime__total": "0:22.99", - "floorplan_tap__cpu__total": 5.78, - "floorplan_tap__mem__peak": 590060.0, - "floorplan_tap__runtime__total": "0:06.59", - "floorplan_tdms__cpu__total": 6.67, - "floorplan_tdms__mem__peak": 745796.0, - "floorplan_tdms__runtime__total": "0:09.13", - "globalplace__cpu__total": 1725.02, - "globalplace__design__core__area": 5010430.0, - "globalplace__design__die__area": 5062500.0, - "globalplace__design__instance__area": 1994150.0, - "globalplace__design__instance__area__macros": 390312, - "globalplace__design__instance__area__stdcell": 1603840.0, - "globalplace__design__instance__count": 289211, - "globalplace__design__instance__count__macros": 15, - "globalplace__design__instance__count__stdcell": 289196, - "globalplace__design__instance__utilization": 0.397999, - "globalplace__design__instance__utilization__stdcell": 0.347142, - "globalplace__design__io": 784, - "globalplace__mem__peak": 3490440.0, - "globalplace__power__internal__total": 0.509181, - "globalplace__power__leakage__total": 0.000976359, - "globalplace__power__switching__total": 0.554881, - "globalplace__power__total": 1.06504, - "globalplace__runtime__total": "30:06.54", - "globalplace__timing__setup__tns": -75959.8, - "globalplace__timing__setup__ws": -42.484, - "globalplace_io__cpu__total": 5.4, - "globalplace_io__mem__peak": 824172.0, - "globalplace_io__runtime__total": "0:06.02", - "globalplace_skip_io__cpu__total": 149.58, - "globalplace_skip_io__mem__peak": 1194784.0, - "globalplace_skip_io__runtime__total": "2:42.49", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.350762, - "globalroute__clock__skew__setup": 0.350762, - "globalroute__cpu__total": 282.31, - "globalroute__design__core__area": 5010430.0, - "globalroute__design__die__area": 5062500.0, - "globalroute__design__instance__area": 2639190.0, - "globalroute__design__instance__area__macros": 390312, - "globalroute__design__instance__area__stdcell": 2248880.0, - "globalroute__design__instance__count": 332264, - "globalroute__design__instance__count__macros": 15, - "globalroute__design__instance__count__stdcell": 332249, - "globalroute__design__instance__utilization": 0.526739, - "globalroute__design__instance__utilization__stdcell": 0.486758, - "globalroute__design__io": 784, - "globalroute__mem__peak": 5153452.0, - "globalroute__power__internal__total": 0.614033, - "globalroute__power__leakage__total": 0.00178513, - "globalroute__power__switching__total": 0.643915, - "globalroute__power__total": 1.25973, - "globalroute__runtime__total": "5:13.54", - "globalroute__timing__clock__slack": 1.647, - "globalroute__timing__drv__hold_violation_count": 29, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.924137, - "globalroute__timing__drv__max_fanout": 1709, - "globalroute__timing__drv__max_fanout_limit": 10, - "globalroute__timing__drv__max_slew": 2642, - "globalroute__timing__drv__max_slew_limit": -9.37165, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 1.64746, - "placeopt__cpu__total": 194.06, - "placeopt__design__core__area": 5010430.0, - "placeopt__design__core__area__pre_opt": 5010430.0, - "placeopt__design__die__area": 5062500.0, - "placeopt__design__die__area__pre_opt": 5062500.0, - "placeopt__design__instance__area": 2625060.0, - "placeopt__design__instance__area__macros": 390312, - "placeopt__design__instance__area__macros__pre_opt": 390312, - "placeopt__design__instance__area__pre_opt": 1994150.0, - "placeopt__design__instance__area__stdcell": 2234750.0, - "placeopt__design__instance__area__stdcell__pre_opt": 1603840.0, - "placeopt__design__instance__count": 329545, - "placeopt__design__instance__count__macros": 15, - "placeopt__design__instance__count__macros__pre_opt": 15, - "placeopt__design__instance__count__pre_opt": 289211, - "placeopt__design__instance__count__stdcell": 329530, - "placeopt__design__instance__count__stdcell__pre_opt": 289196, - "placeopt__design__instance__utilization": 0.523918, - "placeopt__design__instance__utilization__pre_opt": 0.397999, - "placeopt__design__instance__utilization__stdcell": 0.483699, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.347142, - "placeopt__design__io": 784, - "placeopt__design__io__pre_opt": 784, - "placeopt__mem__peak": 1874600.0, - "placeopt__power__internal__total": 0.513531, - "placeopt__power__internal__total__pre_opt": 0.509181, - "placeopt__power__leakage__total": 0.00176983, - "placeopt__power__leakage__total__pre_opt": 0.000976359, - "placeopt__power__switching__total": 0.420742, - "placeopt__power__switching__total__pre_opt": 0.554881, - "placeopt__power__total": 0.936043, - "placeopt__power__total__pre_opt": 1.06504, - "placeopt__runtime__total": "3:16.65", - "placeopt__timing__drv__hold_violation_count": 1398, - "placeopt__timing__drv__max_cap": 4, - "placeopt__timing__drv__max_cap_limit": -6.66736, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 10, - "placeopt__timing__drv__max_slew": 1534, - "placeopt__timing__drv__max_slew_limit": -7.87999, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0, - "placeopt__timing__setup__tns__pre_opt": -75959.8, - "placeopt__timing__setup__ws": 2.34198, - "placeopt__timing__setup__ws__pre_opt": -42.484, - "run__flow__design": "coyote", - "run__flow__generate_date": "2023-07-27 09:29", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9523-g486364f18", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "ec589188ee778f884d4a18de3c3ba924914eac86", - "run__flow__uuid": "ab730258-178e-41a8-9828-2e4562ee91d3", - "run__flow__variant": "base", - "synth__cpu__total": 1259.79, - "synth__design__instance__area__stdcell": 2074172.3765, - "synth__design__instance__count__stdcell": 290340.0, - "synth__mem__peak": 4300528.0, - "synth__runtime__total": "23:23.03", - "total_time": "1:46:25.270000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/coyote/metadata-hier_rtlmp-ok.json b/flow/designs/tsmc65lp/coyote/metadata-hier_rtlmp-ok.json deleted file mode 100644 index 7f0b79139c..0000000000 --- a/flow/designs/tsmc65lp/coyote/metadata-hier_rtlmp-ok.json +++ /dev/null @@ -1,302 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clk: 16.8860" - ], - "cts__clock__skew__hold": 0.3941, - "cts__clock__skew__hold__post_repair": 0.367, - "cts__clock__skew__hold__pre_repair": 0.367, - "cts__clock__skew__setup": 0.3941, - "cts__clock__skew__setup__post_repair": 0.367, - "cts__clock__skew__setup__pre_repair": 0.367, - "cts__design__instance__area": 3012692.75, - "cts__design__instance__area__macros": 390311.75, - "cts__design__instance__area__macros__post_repair": 390311.75, - "cts__design__instance__area__macros__pre_repair": 390311.75, - "cts__design__instance__area__post_repair": 3006656.75, - "cts__design__instance__area__pre_repair": 3006608.0, - "cts__design__instance__area__stdcell": 2622381.0, - "cts__design__instance__area__stdcell__post_repair": 2616345.0, - "cts__design__instance__area__stdcell__pre_repair": 2616296.25, - "cts__design__instance__count": 414228, - "cts__design__instance__count__hold_buffer": 898.0, - "cts__design__instance__count__macros": 15, - "cts__design__instance__count__macros__post_repair": 15, - "cts__design__instance__count__macros__pre_repair": 15, - "cts__design__instance__count__post_repair": 413330, - "cts__design__instance__count__pre_repair": 413327, - "cts__design__instance__count__setup_buffer": 3.0, - "cts__design__instance__count__stdcell": 414213, - "cts__design__instance__count__stdcell__post_repair": 413315, - "cts__design__instance__count__stdcell__pre_repair": 413312, - "cts__design__instance__displacement__max": 58.029, - "cts__design__instance__displacement__mean": 0.0295, - "cts__design__instance__displacement__total": 12355.549, - "cts__design__instance__utilization": 0.6013, - "cts__design__instance__utilization__post_repair": 0.6001, - "cts__design__instance__utilization__pre_repair": 0.6001, - "cts__design__instance__utilization__stdcell": 0.5676, - "cts__design__instance__utilization__stdcell__post_repair": 0.5663, - "cts__design__instance__utilization__stdcell__pre_repair": 0.5663, - "cts__design__io": 784, - "cts__design__io__post_repair": 784, - "cts__design__io__pre_repair": 784, - "cts__design__violations": 0, - "cts__power__internal__total": 0.5845, - "cts__power__internal__total__post_repair": 0.5845, - "cts__power__internal__total__pre_repair": 0.5845, - "cts__power__leakage__total": 0.0021, - "cts__power__leakage__total__post_repair": 0.0021, - "cts__power__leakage__total__pre_repair": 0.0021, - "cts__power__switching__total": 0.617, - "cts__power__switching__total__post_repair": 0.6134, - "cts__power__switching__total__pre_repair": 0.6134, - "cts__power__total": 1.2036, - "cts__power__total__post_repair": 1.2, - "cts__power__total__pre_repair": 1.2, - "cts__route__wirelength__estimated": 13819568.7955, - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 1, - "cts__timing__drv__hold_violation_count__pre_repair": 1, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.9118, - "cts__timing__drv__max_cap_limit__post_repair": 0.914, - "cts__timing__drv__max_cap_limit__pre_repair": 0.914, - "cts__timing__drv__max_fanout": 1845, - "cts__timing__drv__max_fanout__post_repair": 1845, - "cts__timing__drv__max_fanout__pre_repair": 1845, - "cts__timing__drv__max_fanout_limit": 10.0, - "cts__timing__drv__max_fanout_limit__post_repair": 10.0, - "cts__timing__drv__max_fanout_limit__pre_repair": 10.0, - "cts__timing__drv__max_slew": 3284, - "cts__timing__drv__max_slew__post_repair": 3221, - "cts__timing__drv__max_slew__pre_repair": 3222, - "cts__timing__drv__max_slew_limit": -8.9005, - "cts__timing__drv__max_slew_limit__post_repair": -8.9028, - "cts__timing__drv__max_slew_limit__pre_repair": -8.9028, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 0, - "cts__timing__drv__setup_violation_count__pre_repair": 0, - "cts__timing__setup__tns": 0.0, - "cts__timing__setup__tns__post_repair": 0.0, - "cts__timing__setup__tns__pre_repair": 0.0, - "cts__timing__setup__ws": 3.13, - "cts__timing__setup__ws__post_repair": 3.19, - "cts__timing__setup__ws__pre_repair": 3.19, - "detailedplace__cpu__total": 326.85, - "detailedplace__design__instance__area": 2994723.0, - "detailedplace__design__instance__area__macros": 390311.75, - "detailedplace__design__instance__area__stdcell": 2604411.25, - "detailedplace__design__instance__count": 410851, - "detailedplace__design__instance__count__macros": 15, - "detailedplace__design__instance__count__stdcell": 410836, - "detailedplace__design__instance__displacement__max": 131.3, - "detailedplace__design__instance__displacement__mean": 2.713, - "detailedplace__design__instance__displacement__total": 1114822.404, - "detailedplace__design__instance__utilization": 0.5977, - "detailedplace__design__instance__utilization__stdcell": 0.5637, - "detailedplace__design__io": 784, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 2284096.0, - "detailedplace__power__internal__total": 0.5818, - "detailedplace__power__leakage__total": 0.002, - "detailedplace__power__switching__total": 0.6003, - "detailedplace__power__total": 1.1841, - "detailedplace__route__wirelength__estimated": 13979121.9265, - "detailedplace__runtime__total": "5:39.83", - "detailedplace__timing__drv__hold_violation_count": 1, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.914, - "detailedplace__timing__drv__max_fanout": 1, - "detailedplace__timing__drv__max_fanout_limit": 10.0, - "detailedplace__timing__drv__max_slew": 1712, - "detailedplace__timing__drv__max_slew_limit": -8.9028, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0.0, - "detailedplace__timing__setup__ws": 3.29, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 138740, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 1, - "detailedroute__route__drc_errors__iter:12": 0, - "detailedroute__route__drc_errors__iter:2": 28015, - "detailedroute__route__drc_errors__iter:3": 25830, - "detailedroute__route__drc_errors__iter:4": 6, - "detailedroute__route__drc_errors__iter:5": 3, - "detailedroute__route__drc_errors__iter:6": 1, - "detailedroute__route__drc_errors__iter:7": 1, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 393640, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2554026, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2554026, - "detailedroute__route__wirelength": 15565867, - "detailedroute__route__wirelength__iter:1": 15632638, - "detailedroute__route__wirelength__iter:10": 15565867, - "detailedroute__route__wirelength__iter:11": 15565867, - "detailedroute__route__wirelength__iter:12": 15565867, - "detailedroute__route__wirelength__iter:2": 15583032, - "detailedroute__route__wirelength__iter:3": 15566037, - "detailedroute__route__wirelength__iter:4": 15565868, - "detailedroute__route__wirelength__iter:5": 15565868, - "detailedroute__route__wirelength__iter:6": 15565867, - "detailedroute__route__wirelength__iter:7": 15565867, - "detailedroute__route__wirelength__iter:8": 15565867, - "detailedroute__route__wirelength__iter:9": 15565867, - "finish__clock__skew__hold": 0.3184, - "finish__clock__skew__setup": 0.3184, - "finish__cpu__total": 462.49, - "finish__design__instance__area": 3012692.75, - "finish__design__instance__area__macros": 390311.75, - "finish__design__instance__area__stdcell": 2622381.0, - "finish__design__instance__count": 414228, - "finish__design__instance__count__macros": 15, - "finish__design__instance__count__stdcell": 414213, - "finish__design__instance__utilization": 0.6013, - "finish__design__instance__utilization__stdcell": 0.5676, - "finish__design__io": 784, - "finish__mem__peak": 6484524.0, - "finish__power__internal__total": 0.5886, - "finish__power__leakage__total": 0.0021, - "finish__power__switching__total": 0.4062, - "finish__power__total": 0.9968, - "finish__runtime__total": "7:52.27", - "finish__timing__drv__hold_violation_count": 0.0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.9572, - "finish__timing__drv__max_fanout": 1845, - "finish__timing__drv__max_fanout_limit": 10.0, - "finish__timing__drv__max_slew": 994, - "finish__timing__drv__max_slew_limit": -9.7677, - "finish__timing__drv__setup_violation_count": 1.0, - "finish__timing__setup__tns": 0.0, - "finish__timing__setup__ws": 4.98, - "finish__timing__wns_percent_delay": 37.063593, - "floorplan__cpu__total": 3468.73, - "floorplan__design__instance__area": 2247668.5, - "floorplan__design__instance__area__macros": 390311.75, - "floorplan__design__instance__area__stdcell": 1857356.625, - "floorplan__design__instance__count": 330925, - "floorplan__design__instance__count__macros": 15, - "floorplan__design__instance__count__stdcell": 330910, - "floorplan__design__instance__utilization": 0.4486, - "floorplan__design__instance__utilization__stdcell": 0.402, - "floorplan__design__io": 784, - "floorplan__mem__peak": 10150388.0, - "floorplan__power__internal__total": 0.4385, - "floorplan__power__leakage__total": 0.0011, - "floorplan__power__switching__total": 0.2933, - "floorplan__power__total": 0.7329, - "floorplan__runtime__total": "7:16.54", - "floorplan__timing__setup__tns": -30278.6094, - "floorplan__timing__setup__ws": -42.25, - "globalplace__design__instance__area": 2268833.5, - "globalplace__design__instance__area__macros": 390311.75, - "globalplace__design__instance__area__stdcell": 1878521.75, - "globalplace__design__instance__count": 352972, - "globalplace__design__instance__count__macros": 15, - "globalplace__design__instance__count__stdcell": 352957, - "globalplace__design__instance__utilization": 0.4528, - "globalplace__design__instance__utilization__stdcell": 0.4066, - "globalplace__design__io": 784, - "globalplace__power__internal__total": 0.4516, - "globalplace__power__leakage__total": 0.0011, - "globalplace__power__switching__total": 0.5471, - "globalplace__power__total": 0.9999, - "globalplace__timing__setup__tns": -159959.2969, - "globalplace__timing__setup__ws": -41.03, - "globalroute__clock__skew__hold": 0.396, - "globalroute__clock__skew__setup": 0.396, - "globalroute__design__instance__area": 3012692.75, - "globalroute__design__instance__area__macros": 390311.75, - "globalroute__design__instance__area__stdcell": 2622381.0, - "globalroute__design__instance__count": 414228, - "globalroute__design__instance__count__macros": 15, - "globalroute__design__instance__count__stdcell": 414213, - "globalroute__design__instance__utilization": 0.6013, - "globalroute__design__instance__utilization__stdcell": 0.5676, - "globalroute__design__io": 784, - "globalroute__power__internal__total": 0.5861, - "globalroute__power__leakage__total": 0.0021, - "globalroute__power__switching__total": 0.6585, - "globalroute__power__total": 1.2467, - "globalroute__timing__clock__slack": 2.548, - "globalroute__timing__drv__hold_violation_count": 1, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.908, - "globalroute__timing__drv__max_fanout": 1845, - "globalroute__timing__drv__max_fanout_limit": 10.0, - "globalroute__timing__drv__max_slew": 3865, - "globalroute__timing__drv__max_slew_limit": -9.6194, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0.0, - "globalroute__timing__setup__ws": 2.55, - "placeopt__cpu__total": 286.29, - "placeopt__design__instance__area": 2994723.0, - "placeopt__design__instance__area__macros": 390311.75, - "placeopt__design__instance__area__macros__pre_opt": 390311.75, - "placeopt__design__instance__area__pre_opt": 2268833.5, - "placeopt__design__instance__area__stdcell": 2604411.25, - "placeopt__design__instance__area__stdcell__pre_opt": 1878521.75, - "placeopt__design__instance__count": 410851, - "placeopt__design__instance__count__macros": 15, - "placeopt__design__instance__count__macros__pre_opt": 15, - "placeopt__design__instance__count__pre_opt": 352972, - "placeopt__design__instance__count__stdcell": 410836, - "placeopt__design__instance__count__stdcell__pre_opt": 352957, - "placeopt__design__instance__utilization": 0.5977, - "placeopt__design__instance__utilization__pre_opt": 0.4528, - "placeopt__design__instance__utilization__stdcell": 0.5637, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.4066, - "placeopt__design__io": 784, - "placeopt__design__io__pre_opt": 784, - "placeopt__mem__peak": 2155916.0, - "placeopt__power__internal__total": 0.4958, - "placeopt__power__internal__total__pre_opt": 0.4516, - "placeopt__power__leakage__total": 0.002, - "placeopt__power__leakage__total__pre_opt": 0.0011, - "placeopt__power__switching__total": 0.4608, - "placeopt__power__switching__total__pre_opt": 0.5471, - "placeopt__power__total": 0.9586, - "placeopt__power__total__pre_opt": 0.9999, - "placeopt__runtime__total": "4:53.95", - "placeopt__timing__drv__hold_violation_count": 1, - "placeopt__timing__drv__max_cap": 3, - "placeopt__timing__drv__max_cap_limit": -6.6674, - "placeopt__timing__drv__max_fanout": 1, - "placeopt__timing__drv__max_fanout_limit": 10.0, - "placeopt__timing__drv__max_slew": 1618, - "placeopt__timing__drv__max_slew_limit": -7.9687, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": 0.0, - "placeopt__timing__setup__tns__pre_opt": -159959.2969, - "placeopt__timing__setup__ws": 3.35, - "placeopt__timing__setup__ws__pre_opt": -41.03, - "run__flow__design": "coyote", - "run__flow__generate_date": "2022-10-15 06:37", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-5282-g0ef0b33c9", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "b25f2daf0825d34d8053a13141d30ac3424479e7", - "run__flow__scripts_commit": "60c202001de3eed3110c499e69e7d6de2f8b5420", - "run__flow__uuid": "c883cbe0-02ad-425c-b9c7-741e86d67f01", - "run__flow__variant": "hier_rtlmp", - "synth__cpu__total": 1228.91, - "synth__design__instance__area__stdcell": 15014.88, - "synth__design__instance__count__stdcell": 362746.0, - "synth__mem__peak": 4247164.0, - "synth__runtime__total": "21:33.94", - "total_time": "0:47:16.530000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/coyote/rtlmp_config.txt b/flow/designs/tsmc65lp/coyote/rtlmp_config.txt deleted file mode 100644 index 33c8322385..0000000000 --- a/flow/designs/tsmc65lp/coyote/rtlmp_config.txt +++ /dev/null @@ -1,38 +0,0 @@ -min_aspect_ratio = 0.40 -dead_space = 0.05 -halo_width = 10.0 - -num_thread = 10 -num_run = 10 - -heat_rate = 0.5 -num_level = 2 -num_worker = 10 - -learning_rate = 0.0 - -alpha = 0.01 -beta = 54.70 -gamma = 74.71 -boundary_weight = 100.0 -macro_blockage_weight = 50.0 -location_weight = 100.0 -notch_weight = 100.0 - -shrink_factor = 0.999 -shrink_freq = 0.1 - - -resize_prob = 0.1 -pos_swap_prob = 0.3 -neg_swap_prob = 0.3 -double_swap_prob = 0.3 - -init_prob = 0.95 -rej_ratio = 0.95 -k = 5000000 -c = 1000.0 -max_num_step = 4000 -perturb_per_step = 1000 - -snap_layer = 4 diff --git a/flow/designs/tsmc65lp/coyote/rules-base.json b/flow/designs/tsmc65lp/coyote/rules-base.json deleted file mode 100644 index deddd76724..0000000000 --- a/flow/designs/tsmc65lp/coyote/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 2385298.24, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 3018819, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 378959, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 32953, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 32953, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 15684666, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 3035068, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 16476, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 849, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/dynamic_node/config.mk b/flow/designs/tsmc65lp/dynamic_node/config.mk deleted file mode 100644 index 973945e928..0000000000 --- a/flow/designs/tsmc65lp/dynamic_node/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -export DESIGN_NICKNAME = dynamic_node -export DESIGN_NAME = dynamic_node_top_wrap -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -# These values must be multiples of placement site -export DIE_AREA = 0 0 500 501.6 -export CORE_AREA = 10 12 490 492 diff --git a/flow/designs/tsmc65lp/dynamic_node/constraint.sdc b/flow/designs/tsmc65lp/dynamic_node/constraint.sdc deleted file mode 100644 index 96f39c12c7..0000000000 --- a/flow/designs/tsmc65lp/dynamic_node/constraint.sdc +++ /dev/null @@ -1,1388 +0,0 @@ - -create_clock [get_ports clk] -period 7 -waveform {0 3} -set_input_delay -clock clk -max 5.1 [get_ports clk] -set_input_delay -clock clk -min 4.02 [get_ports clk] -set_input_delay -clock clk -max 5.1 [get_ports reset_in] -set_input_delay -clock clk -min 4.02 [get_ports reset_in] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[63]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[63]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[62]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[62]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[61]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[61]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[60]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[60]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[59]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[59]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[58]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[58]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[57]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[57]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[56]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[56]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[55]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[55]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[54]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[54]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[53]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[53]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[52]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[52]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[51]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[51]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[50]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[50]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[49]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[49]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[48]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[48]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[47]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[47]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[46]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[46]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[45]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[45]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[44]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[44]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[43]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[43]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[42]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[42]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[41]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[41]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[40]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[40]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[39]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[39]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[38]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[38]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[37]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[37]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[36]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[36]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[35]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[35]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[34]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[34]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[33]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[33]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[32]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[32]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[31]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[31]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[30]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[30]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[29]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[29]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[28]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[28]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[27]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[27]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[26]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[26]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[25]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[25]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[24]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[24]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[23]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[23]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[22]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[22]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[21]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[21]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[20]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[20]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[19]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[19]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[18]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[18]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[17]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[17]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[16]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[16]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[15]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[15]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[14]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[14]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[63]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[63]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[62]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[62]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[61]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[61]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[60]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[60]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[59]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[59]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[58]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[58]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[57]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[57]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[56]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[56]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[55]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[55]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[54]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[54]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[53]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[53]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[52]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[52]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[51]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[51]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[50]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[50]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[49]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[49]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[48]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[48]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[47]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[47]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[46]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[46]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[45]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[45]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[44]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[44]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[43]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[43]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[42]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[42]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[41]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[41]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[40]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[40]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[39]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[39]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[38]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[38]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[37]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[37]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[36]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[36]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[35]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[35]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[34]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[34]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[33]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[33]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[32]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[32]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[31]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[31]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[30]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[30]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[29]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[29]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[28]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[28]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[27]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[27]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[26]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[26]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[25]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[25]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[24]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[24]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[23]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[23]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[22]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[22]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[21]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[21]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[20]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[20]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[19]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[19]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[18]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[18]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[17]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[17]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[16]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[16]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[15]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[15]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[14]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[14]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_E[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_E[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[63]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[63]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[62]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[62]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[61]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[61]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[60]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[60]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[59]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[59]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[58]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[58]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[57]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[57]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[56]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[56]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[55]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[55]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[54]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[54]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[53]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[53]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[52]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[52]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[51]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[51]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[50]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[50]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[49]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[49]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[48]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[48]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[47]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[47]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[46]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[46]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[45]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[45]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[44]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[44]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[43]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[43]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[42]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[42]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[41]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[41]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[40]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[40]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[39]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[39]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[38]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[38]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[37]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[37]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[36]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[36]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[35]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[35]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[34]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[34]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[33]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[33]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[32]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[32]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[31]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[31]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[30]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[30]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[29]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[29]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[28]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[28]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[27]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[27]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[26]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[26]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[25]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[25]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[24]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[24]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[23]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[23]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[22]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[22]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[21]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[21]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[20]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[20]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[19]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[19]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[18]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[18]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[17]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[17]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[16]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[16]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[15]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[15]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[14]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[14]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_S[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_S[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[63]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[63]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[62]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[62]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[61]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[61]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[60]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[60]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[59]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[59]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[58]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[58]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[57]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[57]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[56]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[56]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[55]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[55]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[54]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[54]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[53]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[53]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[52]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[52]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[51]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[51]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[50]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[50]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[49]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[49]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[48]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[48]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[47]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[47]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[46]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[46]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[45]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[45]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[44]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[44]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[43]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[43]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[42]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[42]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[41]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[41]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[40]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[40]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[39]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[39]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[38]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[38]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[37]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[37]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[36]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[36]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[35]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[35]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[34]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[34]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[33]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[33]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[32]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[32]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[31]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[31]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[30]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[30]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[29]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[29]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[28]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[28]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[27]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[27]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[26]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[26]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[25]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[25]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[24]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[24]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[23]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[23]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[22]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[22]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[21]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[21]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[20]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[20]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[19]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[19]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[18]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[18]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[17]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[17]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[16]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[16]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[15]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[15]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[14]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[14]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_W[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_W[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[63]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[63]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[62]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[62]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[61]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[61]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[60]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[60]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[59]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[59]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[58]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[58]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[57]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[57]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[56]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[56]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[55]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[55]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[54]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[54]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[53]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[53]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[52]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[52]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[51]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[51]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[50]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[50]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[49]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[49]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[48]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[48]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[47]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[47]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[46]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[46]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[45]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[45]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[44]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[44]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[43]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[43]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[42]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[42]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[41]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[41]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[40]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[40]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[39]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[39]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[38]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[38]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[37]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[37]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[36]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[36]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[35]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[35]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[34]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[34]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[33]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[33]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[32]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[32]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[31]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[31]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[30]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[30]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[29]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[29]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[28]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[28]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[27]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[27]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[26]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[26]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[25]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[25]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[24]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[24]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[23]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[23]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[22]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[22]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[21]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[21]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[20]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[20]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[19]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[19]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[18]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[18]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[17]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[17]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[16]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[16]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[15]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[15]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[14]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[14]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {dataIn_P[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {dataIn_P[0]}] -set_input_delay -clock clk -max 5.1 [get_ports validIn_N] -set_input_delay -clock clk -min 4.02 [get_ports validIn_N] -set_input_delay -clock clk -max 5.1 [get_ports validIn_E] -set_input_delay -clock clk -min 4.02 [get_ports validIn_E] -set_input_delay -clock clk -max 5.1 [get_ports validIn_S] -set_input_delay -clock clk -min 4.02 [get_ports validIn_S] -set_input_delay -clock clk -max 5.1 [get_ports validIn_W] -set_input_delay -clock clk -min 4.02 [get_ports validIn_W] -set_input_delay -clock clk -max 5.1 [get_ports validIn_P] -set_input_delay -clock clk -min 4.02 [get_ports validIn_P] -set_input_delay -clock clk -max 5.1 [get_ports yummyIn_N] -set_input_delay -clock clk -min 4.02 [get_ports yummyIn_N] -set_input_delay -clock clk -max 5.1 [get_ports yummyIn_E] -set_input_delay -clock clk -min 4.02 [get_ports yummyIn_E] -set_input_delay -clock clk -max 5.1 [get_ports yummyIn_S] -set_input_delay -clock clk -min 4.02 [get_ports yummyIn_S] -set_input_delay -clock clk -max 5.1 [get_ports yummyIn_W] -set_input_delay -clock clk -min 4.02 [get_ports yummyIn_W] -set_input_delay -clock clk -max 5.1 [get_ports yummyIn_P] -set_input_delay -clock clk -min 4.02 [get_ports yummyIn_P] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocX[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocX[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {myLocY[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {myLocY[0]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[13]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[13]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[12]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[12]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[11]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[11]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[10]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[10]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[9]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[9]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[8]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[8]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[7]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[7]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[6]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[6]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[5]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[5]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[4]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[4]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[3]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[3]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[2]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[2]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[1]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[1]}] -set_input_delay -clock clk -max 5.1 [get_ports {myChipID[0]}] -set_input_delay -clock clk -min 4.02 [get_ports {myChipID[0]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[63]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[63]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[62]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[62]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[61]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[61]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[60]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[60]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[59]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[59]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[58]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[58]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[57]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[57]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[56]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[56]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[55]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[55]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[54]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[54]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[53]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[53]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[52]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[52]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[51]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[51]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[50]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[50]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[49]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[49]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[48]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[48]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[47]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[47]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[46]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[46]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[45]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[45]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[44]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[44]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[43]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[43]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[42]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[42]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[41]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[41]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[40]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[40]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[39]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[39]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[38]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[38]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[37]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[37]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[36]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[36]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[35]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[35]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[34]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[34]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[33]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[33]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[32]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[32]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[31]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[31]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[30]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[30]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[29]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[29]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[28]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[28]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[27]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[27]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[26]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[26]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[25]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[25]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[24]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[24]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[23]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[23]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[22]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[22]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[21]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[21]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[20]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[20]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[19]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[19]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[18]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[18]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[17]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[17]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[16]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[16]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[15]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[15]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[14]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[14]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[13]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[13]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[12]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[12]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[11]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[11]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[10]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[10]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[9]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[9]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[8]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[8]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[7]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[7]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[6]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[6]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[5]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[5]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[4]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[4]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[3]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[3]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[2]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[2]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[1]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[1]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_N[0]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_N[0]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[63]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[63]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[62]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[62]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[61]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[61]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[60]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[60]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[59]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[59]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[58]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[58]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[57]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[57]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[56]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[56]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[55]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[55]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[54]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[54]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[53]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[53]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[52]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[52]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[51]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[51]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[50]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[50]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[49]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[49]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[48]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[48]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[47]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[47]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[46]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[46]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[45]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[45]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[44]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[44]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[43]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[43]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[42]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[42]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[41]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[41]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[40]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[40]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[39]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[39]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[38]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[38]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[37]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[37]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[36]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[36]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[35]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[35]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[34]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[34]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[33]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[33]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[32]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[32]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[31]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[31]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[30]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[30]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[29]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[29]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[28]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[28]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[27]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[27]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[26]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[26]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[25]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[25]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[24]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[24]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[23]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[23]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[22]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[22]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[21]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[21]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[20]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[20]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[19]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[19]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[18]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[18]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[17]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[17]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[16]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[16]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[15]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[15]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[14]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[14]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[13]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[13]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[12]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[12]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[11]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[11]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[10]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[10]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[9]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[9]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[8]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[8]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[7]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[7]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[6]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[6]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[5]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[5]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[4]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[4]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[3]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[3]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[2]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[2]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[1]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[1]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_E[0]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_E[0]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[63]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[63]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[62]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[62]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[61]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[61]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[60]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[60]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[59]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[59]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[58]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[58]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[57]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[57]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[56]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[56]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[55]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[55]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[54]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[54]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[53]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[53]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[52]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[52]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[51]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[51]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[50]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[50]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[49]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[49]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[48]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[48]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[47]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[47]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[46]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[46]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[45]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[45]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[44]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[44]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[43]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[43]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[42]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[42]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[41]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[41]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[40]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[40]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[39]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[39]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[38]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[38]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[37]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[37]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[36]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[36]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[35]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[35]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[34]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[34]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[33]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[33]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[32]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[32]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[31]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[31]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[30]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[30]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[29]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[29]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[28]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[28]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[27]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[27]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[26]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[26]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[25]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[25]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[24]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[24]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[23]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[23]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[22]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[22]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[21]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[21]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[20]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[20]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[19]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[19]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[18]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[18]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[17]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[17]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[16]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[16]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[15]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[15]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[14]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[14]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[13]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[13]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[12]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[12]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[11]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[11]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[10]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[10]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[9]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[9]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[8]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[8]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[7]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[7]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[6]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[6]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[5]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[5]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[4]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[4]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[3]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[3]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[2]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[2]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[1]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[1]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_S[0]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_S[0]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[63]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[63]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[62]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[62]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[61]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[61]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[60]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[60]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[59]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[59]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[58]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[58]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[57]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[57]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[56]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[56]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[55]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[55]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[54]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[54]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[53]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[53]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[52]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[52]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[51]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[51]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[50]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[50]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[49]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[49]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[48]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[48]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[47]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[47]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[46]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[46]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[45]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[45]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[44]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[44]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[43]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[43]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[42]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[42]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[41]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[41]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[40]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[40]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[39]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[39]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[38]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[38]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[37]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[37]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[36]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[36]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[35]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[35]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[34]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[34]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[33]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[33]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[32]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[32]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[31]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[31]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[30]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[30]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[29]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[29]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[28]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[28]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[27]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[27]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[26]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[26]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[25]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[25]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[24]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[24]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[23]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[23]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[22]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[22]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[21]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[21]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[20]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[20]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[19]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[19]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[18]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[18]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[17]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[17]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[16]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[16]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[15]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[15]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[14]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[14]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[13]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[13]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[12]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[12]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[11]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[11]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[10]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[10]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[9]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[9]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[8]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[8]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[7]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[7]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[6]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[6]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[5]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[5]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[4]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[4]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[3]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[3]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[2]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[2]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[1]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[1]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_W[0]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_W[0]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[63]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[63]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[62]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[62]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[61]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[61]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[60]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[60]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[59]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[59]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[58]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[58]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[57]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[57]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[56]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[56]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[55]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[55]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[54]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[54]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[53]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[53]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[52]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[52]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[51]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[51]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[50]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[50]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[49]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[49]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[48]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[48]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[47]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[47]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[46]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[46]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[45]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[45]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[44]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[44]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[43]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[43]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[42]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[42]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[41]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[41]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[40]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[40]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[39]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[39]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[38]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[38]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[37]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[37]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[36]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[36]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[35]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[35]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[34]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[34]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[33]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[33]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[32]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[32]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[31]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[31]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[30]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[30]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[29]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[29]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[28]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[28]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[27]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[27]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[26]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[26]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[25]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[25]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[24]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[24]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[23]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[23]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[22]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[22]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[21]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[21]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[20]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[20]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[19]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[19]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[18]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[18]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[17]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[17]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[16]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[16]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[15]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[15]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[14]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[14]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[13]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[13]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[12]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[12]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[11]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[11]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[10]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[10]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[9]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[9]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[8]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[8]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[7]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[7]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[6]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[6]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[5]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[5]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[4]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[4]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[3]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[3]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[2]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[2]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[1]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[1]}] -set_output_delay -clock clk -max 5.1 [get_ports {dataOut_P[0]}] -set_output_delay -clock clk -min 4.02 [get_ports {dataOut_P[0]}] -set_output_delay -clock clk -max 5.1 [get_ports validOut_N] -set_output_delay -clock clk -min 4.02 [get_ports validOut_N] -set_output_delay -clock clk -max 5.1 [get_ports validOut_E] -set_output_delay -clock clk -min 4.02 [get_ports validOut_E] -set_output_delay -clock clk -max 5.1 [get_ports validOut_S] -set_output_delay -clock clk -min 4.02 [get_ports validOut_S] -set_output_delay -clock clk -max 5.1 [get_ports validOut_W] -set_output_delay -clock clk -min 4.02 [get_ports validOut_W] -set_output_delay -clock clk -max 5.1 [get_ports validOut_P] -set_output_delay -clock clk -min 4.02 [get_ports validOut_P] -set_output_delay -clock clk -max 5.1 [get_ports yummyOut_N] -set_output_delay -clock clk -min 4.02 [get_ports yummyOut_N] -set_output_delay -clock clk -max 5.1 [get_ports yummyOut_E] -set_output_delay -clock clk -min 4.02 [get_ports yummyOut_E] -set_output_delay -clock clk -max 5.1 [get_ports yummyOut_S] -set_output_delay -clock clk -min 4.02 [get_ports yummyOut_S] -set_output_delay -clock clk -max 5.1 [get_ports yummyOut_W] -set_output_delay -clock clk -min 4.02 [get_ports yummyOut_W] -set_output_delay -clock clk -max 5.1 [get_ports yummyOut_P] -set_output_delay -clock clk -min 4.02 [get_ports yummyOut_P] -set_output_delay -clock clk -max 5.1 [get_ports thanksIn_P] -set_output_delay -clock clk -min 4.02 [get_ports thanksIn_P] diff --git a/flow/designs/tsmc65lp/dynamic_node/metadata-base-ok.json b/flow/designs/tsmc65lp/dynamic_node/metadata-base-ok.json deleted file mode 100644 index f0a74818d7..0000000000 --- a/flow/designs/tsmc65lp/dynamic_node/metadata-base-ok.json +++ /dev/null @@ -1,347 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 7.0000" - ], - "cts__clock__skew__hold": 0.121963, - "cts__clock__skew__hold__post_repair": 0.132466, - "cts__clock__skew__hold__pre_repair": 0.132466, - "cts__clock__skew__setup": 0.121963, - "cts__clock__skew__setup__post_repair": 0.132466, - "cts__clock__skew__setup__pre_repair": 0.132466, - "cts__cpu__total": 508.99, - "cts__design__core__area": 230400, - "cts__design__core__area__post_repair": 230400, - "cts__design__core__area__pre_repair": 230400, - "cts__design__die__area": 250800, - "cts__design__die__area__post_repair": 250800, - "cts__design__die__area__pre_repair": 250800, - "cts__design__instance__area": 76103.5, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 73724.6, - "cts__design__instance__area__pre_repair": 73724.6, - "cts__design__instance__area__stdcell": 76103.5, - "cts__design__instance__area__stdcell__post_repair": 73724.6, - "cts__design__instance__area__stdcell__pre_repair": 73724.6, - "cts__design__instance__count": 10265, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 9947, - "cts__design__instance__count__pre_repair": 9947, - "cts__design__instance__count__setup_buffer": 318, - "cts__design__instance__count__stdcell": 10265, - "cts__design__instance__count__stdcell__post_repair": 9947, - "cts__design__instance__count__stdcell__pre_repair": 9947, - "cts__design__instance__displacement__max": 14.4, - "cts__design__instance__displacement__mean": 0.1375, - "cts__design__instance__displacement__total": 1416.54, - "cts__design__instance__utilization": 0.33031, - "cts__design__instance__utilization__post_repair": 0.319985, - "cts__design__instance__utilization__pre_repair": 0.319985, - "cts__design__instance__utilization__stdcell": 0.33031, - "cts__design__instance__utilization__stdcell__post_repair": 0.319985, - "cts__design__instance__utilization__stdcell__pre_repair": 0.319985, - "cts__design__io": 693, - "cts__design__io__post_repair": 693, - "cts__design__io__pre_repair": 693, - "cts__design__violations": 0, - "cts__mem__peak": 401284.0, - "cts__power__internal__total": 0.0114645, - "cts__power__internal__total__post_repair": 0.0114611, - "cts__power__internal__total__pre_repair": 0.0114611, - "cts__power__leakage__total": 4.52215e-05, - "cts__power__leakage__total__post_repair": 4.13096e-05, - "cts__power__leakage__total__pre_repair": 4.13096e-05, - "cts__power__switching__total": 0.00861594, - "cts__power__switching__total__post_repair": 0.00931309, - "cts__power__switching__total__pre_repair": 0.00931309, - "cts__power__total": 0.0201257, - "cts__power__total__post_repair": 0.0208155, - "cts__power__total__pre_repair": 0.0208155, - "cts__route__wirelength__estimated": 272423, - "cts__runtime__total": "9:43.09", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.900836, - "cts__timing__drv__max_cap_limit__post_repair": 0.0658769, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0658769, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.182127, - "cts__timing__drv__max_slew_limit__post_repair": 0.03083, - "cts__timing__drv__max_slew_limit__pre_repair": 0.03083, - "cts__timing__drv__setup_violation_count": 326, - "cts__timing__drv__setup_violation_count__post_repair": 326, - "cts__timing__drv__setup_violation_count__pre_repair": 326, - "cts__timing__setup__tns": -128.278, - "cts__timing__setup__tns__post_repair": -304.059, - "cts__timing__setup__tns__pre_repair": -304.059, - "cts__timing__setup__ws": -0.785851, - "cts__timing__setup__ws__post_repair": -1.99153, - "cts__timing__setup__ws__pre_repair": -1.99153, - "cts_fill__cpu__total": 3.9, - "cts_fill__mem__peak": 348700.0, - "cts_fill__runtime__total": "0:06.74", - "detailedplace__cpu__total": 10.48, - "detailedplace__design__core__area": 230400, - "detailedplace__design__die__area": 250800, - "detailedplace__design__instance__area": 73239.8, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 73239.8, - "detailedplace__design__instance__count": 9846, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 9846, - "detailedplace__design__instance__displacement__max": 15.5, - "detailedplace__design__instance__displacement__mean": 2.3235, - "detailedplace__design__instance__displacement__total": 22879.5, - "detailedplace__design__instance__utilization": 0.317881, - "detailedplace__design__instance__utilization__stdcell": 0.317881, - "detailedplace__design__io": 693, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 369008.0, - "detailedplace__power__internal__total": 0.011275, - "detailedplace__power__leakage__total": 4.07206e-05, - "detailedplace__power__switching__total": 0.008048, - "detailedplace__power__total": 0.0193637, - "detailedplace__route__wirelength__estimated": 238011, - "detailedplace__runtime__total": "0:10.97", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0658769, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0302657, - "detailedplace__timing__drv__setup_violation_count": 234, - "detailedplace__timing__setup__tns": -33.1103, - "detailedplace__timing__setup__ws": -1.132, - "detailedroute__cpu__total": 532.31, - "detailedroute__mem__peak": 2292436.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 3962, - "detailedroute__route__drc_errors__iter:2": 848, - "detailedroute__route__drc_errors__iter:3": 633, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 9318, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 66304, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 66304, - "detailedroute__route__wirelength": 389357, - "detailedroute__route__wirelength__iter:1": 390568, - "detailedroute__route__wirelength__iter:2": 389693, - "detailedroute__route__wirelength__iter:3": 389378, - "detailedroute__route__wirelength__iter:4": 389357, - "detailedroute__runtime__total": "1:14.94", - "finish__clock__skew__hold": 0.0839669, - "finish__clock__skew__setup": 0.0839669, - "finish__cpu__total": 18.93, - "finish__design__core__area": 230400, - "finish__design__die__area": 250800, - "finish__design__instance__area": 76103.5, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 76103.5, - "finish__design__instance__count": 10265, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 10265, - "finish__design__instance__utilization": 0.33031, - "finish__design__instance__utilization__stdcell": 0.33031, - "finish__design__io": 693, - "finish__mem__peak": 552176.0, - "finish__power__internal__total": 0.0119841, - "finish__power__leakage__total": 4.52215e-05, - "finish__power__switching__total": 0.00769704, - "finish__power__total": 0.0197264, - "finish__runtime__total": "0:20.27", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.903604, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.35501, - "finish__timing__drv__setup_violation_count": 173, - "finish__timing__setup__tns": -8.0003, - "finish__timing__setup__ws": -0.433461, - "finish__timing__wns_percent_delay": -18.577244, - "finish_merge__cpu__total": 5.25, - "finish_merge__mem__peak": 568540.0, - "finish_merge__runtime__total": "0:07.20", - "floorplan__cpu__total": 6.74, - "floorplan__design__core__area": 230400, - "floorplan__design__die__area": 250800, - "floorplan__design__instance__area": 59614.6, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 59614.6, - "floorplan__design__instance__count": 7827, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 7827, - "floorplan__design__instance__utilization": 0.258744, - "floorplan__design__instance__utilization__stdcell": 0.258744, - "floorplan__design__io": 693, - "floorplan__mem__peak": 343800.0, - "floorplan__power__internal__total": 0.00943304, - "floorplan__power__leakage__total": 3.56291e-05, - "floorplan__power__switching__total": 0.00285004, - "floorplan__power__total": 0.0123187, - "floorplan__runtime__total": "0:07.05", - "floorplan__timing__setup__tns": -247.637, - "floorplan__timing__setup__ws": -1.18852, - "floorplan_io__cpu__total": 3.63, - "floorplan_io__mem__peak": 315840.0, - "floorplan_io__runtime__total": "0:03.86", - "floorplan_macro__cpu__total": 3.63, - "floorplan_macro__mem__peak": 315036.0, - "floorplan_macro__runtime__total": "0:03.86", - "floorplan_pdn__cpu__total": 3.76, - "floorplan_pdn__mem__peak": 318976.0, - "floorplan_pdn__runtime__total": "0:03.97", - "floorplan_tap__cpu__total": 3.63, - "floorplan_tap__mem__peak": 308836.0, - "floorplan_tap__runtime__total": "0:03.85", - "floorplan_tdms__cpu__total": 3.65, - "floorplan_tdms__mem__peak": 315416.0, - "floorplan_tdms__runtime__total": "0:03.87", - "globalplace__cpu__total": 45.09, - "globalplace__design__core__area": 230400, - "globalplace__design__die__area": 250800, - "globalplace__design__instance__area": 60871.2, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 60871.2, - "globalplace__design__instance__count": 9136, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 9136, - "globalplace__design__instance__utilization": 0.264198, - "globalplace__design__instance__utilization__stdcell": 0.264198, - "globalplace__design__io": 693, - "globalplace__mem__peak": 487860.0, - "globalplace__power__internal__total": 0.00993794, - "globalplace__power__leakage__total": 3.56291e-05, - "globalplace__power__switching__total": 0.00679167, - "globalplace__power__total": 0.0167652, - "globalplace__runtime__total": "0:45.85", - "globalplace__timing__setup__tns": -4337.5, - "globalplace__timing__setup__ws": -4.52054, - "globalplace_io__cpu__total": 3.66, - "globalplace_io__mem__peak": 318516.0, - "globalplace_io__runtime__total": "0:03.89", - "globalplace_skip_io__cpu__total": 5.78, - "globalplace_skip_io__mem__peak": 326856.0, - "globalplace_skip_io__runtime__total": "0:06.07", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.126594, - "globalroute__clock__skew__setup": 0.126594, - "globalroute__cpu__total": 17.83, - "globalroute__design__core__area": 230400, - "globalroute__design__die__area": 250800, - "globalroute__design__instance__area": 76103.5, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 76103.5, - "globalroute__design__instance__count": 10265, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 10265, - "globalroute__design__instance__utilization": 0.33031, - "globalroute__design__instance__utilization__stdcell": 0.33031, - "globalroute__design__io": 693, - "globalroute__mem__peak": 555156.0, - "globalroute__power__internal__total": 0.0119755, - "globalroute__power__leakage__total": 4.52215e-05, - "globalroute__power__switching__total": 0.0106469, - "globalroute__power__total": 0.0226676, - "globalroute__runtime__total": "0:18.51", - "globalroute__timing__clock__slack": -0.856, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.893513, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 17, - "globalroute__timing__drv__max_slew_limit": -0.0489929, - "globalroute__timing__drv__setup_violation_count": 326, - "globalroute__timing__setup__tns": -151.319, - "globalroute__timing__setup__ws": -0.856276, - "placeopt__cpu__total": 13.96, - "placeopt__design__core__area": 230400, - "placeopt__design__core__area__pre_opt": 230400, - "placeopt__design__die__area": 250800, - "placeopt__design__die__area__pre_opt": 250800, - "placeopt__design__instance__area": 73239.8, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 60871.2, - "placeopt__design__instance__area__stdcell": 73239.8, - "placeopt__design__instance__area__stdcell__pre_opt": 60871.2, - "placeopt__design__instance__count": 9846, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 9136, - "placeopt__design__instance__count__stdcell": 9846, - "placeopt__design__instance__count__stdcell__pre_opt": 9136, - "placeopt__design__instance__utilization": 0.317881, - "placeopt__design__instance__utilization__pre_opt": 0.264198, - "placeopt__design__instance__utilization__stdcell": 0.317881, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.264198, - "placeopt__design__io": 693, - "placeopt__design__io__pre_opt": 693, - "placeopt__mem__peak": 374628.0, - "placeopt__power__internal__total": 0.0108648, - "placeopt__power__internal__total__pre_opt": 0.00993794, - "placeopt__power__leakage__total": 4.07206e-05, - "placeopt__power__leakage__total__pre_opt": 3.56291e-05, - "placeopt__power__switching__total": 0.00754522, - "placeopt__power__switching__total__pre_opt": 0.00679167, - "placeopt__power__total": 0.0184507, - "placeopt__power__total__pre_opt": 0.0167652, - "placeopt__runtime__total": "0:14.32", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.071902, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0341407, - "placeopt__timing__drv__setup_violation_count": 242, - "placeopt__timing__setup__tns": -30.6207, - "placeopt__timing__setup__tns__pre_opt": -4337.5, - "placeopt__timing__setup__ws": -1.12065, - "placeopt__timing__setup__ws__pre_opt": -4.52054, - "run__flow__design": "dynamic_node", - "run__flow__generate_date": "2023-07-15 15:41", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9070-gbb341ffb9", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "42ca04d0df7aa58eb296a6d96b4dd4ecb6cf0469", - "run__flow__uuid": "1420faf5-c1ac-4fcb-84c3-86d1086f7122", - "run__flow__variant": "base", - "synth__cpu__total": 34.18, - "synth__design__instance__area__stdcell": 63246.72, - "synth__design__instance__count__stdcell": 8802.0, - "synth__mem__peak": 195404.0, - "synth__runtime__total": "0:35.76", - "total_time": "0:14:14.070000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/dynamic_node/rules-base.json b/flow/designs/tsmc65lp/dynamic_node/rules-base.json deleted file mode 100644 index 82d5fff93f..0000000000 --- a/flow/designs/tsmc65lp/dynamic_node/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 72733.73, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 84226, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 11323, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 985, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 985, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 447761, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.78, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 87519, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 492, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -32.29, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/gcd/config.mk b/flow/designs/tsmc65lp/gcd/config.mk deleted file mode 100644 index aad84150d4..0000000000 --- a/flow/designs/tsmc65lp/gcd/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -export DESIGN_NAME = gcd -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc -export ABC_AREA = 1 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 100 100.8 -export CORE_AREA = 10 12 90 91.2 - -export PLACE_DENSITY = 0.50 diff --git a/flow/designs/tsmc65lp/gcd/constraint.sdc b/flow/designs/tsmc65lp/gcd/constraint.sdc deleted file mode 100644 index 98ab807b4d..0000000000 --- a/flow/designs/tsmc65lp/gcd/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design gcd - -set clk_name core_clock -set clk_port_name clk -set clk_period 1.20 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/gcd/metadata-base-ok.json b/flow/designs/tsmc65lp/gcd/metadata-base-ok.json deleted file mode 100644 index ebff126ce5..0000000000 --- a/flow/designs/tsmc65lp/gcd/metadata-base-ok.json +++ /dev/null @@ -1,373 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 1.2000" - ], - "cts__clock__skew__hold": 0.0130801, - "cts__clock__skew__hold__post_repair": 0.011371, - "cts__clock__skew__hold__pre_repair": 0.011371, - "cts__clock__skew__setup": 0.0130801, - "cts__clock__skew__setup__post_repair": 0.011371, - "cts__clock__skew__setup__pre_repair": 0.011371, - "cts__cpu__total": 24.84, - "cts__design__core__area": 6336, - "cts__design__core__area__post_repair": 6336, - "cts__design__core__area__pre_repair": 6336, - "cts__design__die__area": 10080, - "cts__design__die__area__post_repair": 10080, - "cts__design__die__area__pre_repair": 10080, - "cts__design__instance__area": 2897.28, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 2496.48, - "cts__design__instance__area__pre_repair": 2496.48, - "cts__design__instance__area__stdcell": 2897.28, - "cts__design__instance__area__stdcell__post_repair": 2496.48, - "cts__design__instance__area__stdcell__pre_repair": 2496.48, - "cts__design__instance__count": 625, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 555, - "cts__design__instance__count__pre_repair": 555, - "cts__design__instance__count__setup_buffer": 70, - "cts__design__instance__count__stdcell": 625, - "cts__design__instance__count__stdcell__post_repair": 555, - "cts__design__instance__count__stdcell__pre_repair": 555, - "cts__design__instance__displacement__max": 8.6215, - "cts__design__instance__displacement__mean": 0.5955, - "cts__design__instance__displacement__total": 372.447, - "cts__design__instance__utilization": 0.457273, - "cts__design__instance__utilization__post_repair": 0.394015, - "cts__design__instance__utilization__pre_repair": 0.394015, - "cts__design__instance__utilization__stdcell": 0.457273, - "cts__design__instance__utilization__stdcell__post_repair": 0.394015, - "cts__design__instance__utilization__stdcell__pre_repair": 0.394015, - "cts__design__io": 54, - "cts__design__io__post_repair": 54, - "cts__design__io__pre_repair": 54, - "cts__design__violations": 0, - "cts__flow__errors__count": 0, - "cts__flow__warnings__count": 1, - "cts__mem__peak": 350044.0, - "cts__power__internal__total": 0.00141299, - "cts__power__internal__total__post_repair": 0.00128651, - "cts__power__internal__total__pre_repair": 0.00128651, - "cts__power__leakage__total": 2.20649e-06, - "cts__power__leakage__total__post_repair": 1.78069e-06, - "cts__power__leakage__total__pre_repair": 1.78069e-06, - "cts__power__switching__total": 0.0011129, - "cts__power__switching__total__post_repair": 0.00106034, - "cts__power__switching__total__pre_repair": 0.00106034, - "cts__power__total": 0.0025281, - "cts__power__total__post_repair": 0.00234862, - "cts__power__total__pre_repair": 0.00234862, - "cts__route__wirelength__estimated": 6874.42, - "cts__runtime__total": "0:31.78", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.970929, - "cts__timing__drv__max_cap_limit__post_repair": 0.971811, - "cts__timing__drv__max_cap_limit__pre_repair": 0.971811, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.914909, - "cts__timing__drv__max_slew_limit__post_repair": 0.917395, - "cts__timing__drv__max_slew_limit__pre_repair": 0.917395, - "cts__timing__drv__setup_violation_count": 38, - "cts__timing__drv__setup_violation_count__post_repair": 40, - "cts__timing__drv__setup_violation_count__pre_repair": 40, - "cts__timing__setup__tns": -2.6867, - "cts__timing__setup__tns__post_repair": -4.1914, - "cts__timing__setup__tns__pre_repair": -4.1914, - "cts__timing__setup__ws": -0.0999207, - "cts__timing__setup__ws__post_repair": -0.265603, - "cts__timing__setup__ws__pre_repair": -0.265603, - "design__io__hpwl": 3127954, - "detailedplace__cpu__total": 4.34, - "detailedplace__design__core__area": 6336, - "detailedplace__design__die__area": 10080, - "detailedplace__design__instance__area": 2477.28, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 2477.28, - "detailedplace__design__instance__count": 550, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 550, - "detailedplace__design__instance__displacement__max": 5.9, - "detailedplace__design__instance__displacement__mean": 1.358, - "detailedplace__design__instance__displacement__total": 747.11, - "detailedplace__design__instance__utilization": 0.390985, - "detailedplace__design__instance__utilization__stdcell": 0.390985, - "detailedplace__design__io": 54, - "detailedplace__design__violations": 0, - "detailedplace__flow__errors__count": 0, - "detailedplace__flow__warnings__count": 0, - "detailedplace__mem__peak": 310108.0, - "detailedplace__power__internal__total": 0.00122513, - "detailedplace__power__leakage__total": 1.71033e-06, - "detailedplace__power__switching__total": 0.000921024, - "detailedplace__power__total": 0.00214786, - "detailedplace__route__wirelength__estimated": 6560.49, - "detailedplace__runtime__total": "0:04.67", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.971811, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.861029, - "detailedplace__timing__drv__setup_violation_count": 32, - "detailedplace__timing__setup__tns": -2.14895, - "detailedplace__timing__setup__ws": -0.0979581, - "detailedroute__cpu__total": 107.03, - "detailedroute__flow__errors__count": 0, - "detailedroute__flow__warnings__count": 15, - "detailedroute__mem__peak": 1096260.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 95, - "detailedroute__route__drc_errors__iter:2": 3, - "detailedroute__route__drc_errors__iter:3": 0, - "detailedroute__route__net": 600, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 2895, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 2895, - "detailedroute__route__wirelength": 8201, - "detailedroute__route__wirelength__iter:1": 8296, - "detailedroute__route__wirelength__iter:2": 8213, - "detailedroute__route__wirelength__iter:3": 8201, - "detailedroute__runtime__total": "0:24.05", - "fillcell__cpu__total": 5.68, - "fillcell__mem__peak": 308512.0, - "fillcell__runtime__total": "0:14.88", - "finish__clock__skew__hold": 0.0118581, - "finish__clock__skew__setup": 0.0118581, - "finish__cpu__total": 8.03, - "finish__design__core__area": 6336, - "finish__design__die__area": 10080, - "finish__design__instance__area": 3027.36, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 3027.36, - "finish__design__instance__count": 647, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 647, - "finish__design__instance__utilization": 0.477803, - "finish__design__instance__utilization__stdcell": 0.477803, - "finish__design__io": 54, - "finish__flow__errors__count": 0, - "finish__flow__warnings__count": 0, - "finish__mem__peak": 398216.0, - "finish__power__internal__total": 0.0015803, - "finish__power__leakage__total": 2.31622e-06, - "finish__power__switching__total": 0.0010806, - "finish__power__total": 0.00266322, - "finish__runtime__total": "0:09.70", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.974729, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.934034, - "finish__timing__drv__setup_violation_count": 19, - "finish__timing__setup__tns": -0.466335, - "finish__timing__setup__ws": -0.0911951, - "finish__timing__wns_percent_delay": -6.420275, - "finish_merge__cpu__total": 4.63, - "finish_merge__mem__peak": 473596.0, - "finish_merge__runtime__total": "0:05.95", - "floorplan__cpu__total": 4.5, - "floorplan__design__core__area": 6336, - "floorplan__design__die__area": 10080, - "floorplan__design__instance__area": 2063.04, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 2063.04, - "floorplan__design__instance__count": 414, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 414, - "floorplan__design__instance__utilization": 0.325606, - "floorplan__design__instance__utilization__stdcell": 0.325606, - "floorplan__design__io": 54, - "floorplan__flow__errors__count": 0, - "floorplan__flow__warnings__count": 0, - "floorplan__mem__peak": 311432.0, - "floorplan__power__internal__total": 0.000978045, - "floorplan__power__leakage__total": 1.39863e-06, - "floorplan__power__switching__total": 0.000563921, - "floorplan__power__total": 0.00154336, - "floorplan__runtime__total": "0:04.80", - "floorplan__timing__setup__tns": 0, - "floorplan__timing__setup__ws": 0.104567, - "floorplan_io__cpu__total": 4.09, - "floorplan_io__mem__peak": 305944.0, - "floorplan_io__runtime__total": "0:04.40", - "floorplan_macro__cpu__total": 4.19, - "floorplan_macro__mem__peak": 307140.0, - "floorplan_macro__runtime__total": "0:04.48", - "floorplan_pdn__cpu__total": 4.44, - "floorplan_pdn__mem__peak": 309220.0, - "floorplan_pdn__runtime__total": "0:04.72", - "floorplan_tap__cpu__total": 4.6, - "floorplan_tap__mem__peak": 305584.0, - "floorplan_tap__runtime__total": "0:04.88", - "floorplan_tdms__cpu__total": 4.32, - "floorplan_tdms__mem__peak": 306596.0, - "floorplan_tdms__runtime__total": "0:04.62", - "flow__errors__count": 0, - "flow__warnings__count": 0, - "globalplace__cpu__total": 5.19, - "globalplace__design__core__area": 6336, - "globalplace__design__die__area": 10080, - "globalplace__design__instance__area": 2142.72, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 2142.72, - "globalplace__design__instance__count": 497, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 497, - "globalplace__design__instance__utilization": 0.338182, - "globalplace__design__instance__utilization__stdcell": 0.338182, - "globalplace__design__io": 54, - "globalplace__flow__errors__count": 0, - "globalplace__flow__warnings__count": 0, - "globalplace__mem__peak": 400632.0, - "globalplace__power__internal__total": 0.000976122, - "globalplace__power__leakage__total": 1.39863e-06, - "globalplace__power__switching__total": 0.000842172, - "globalplace__power__total": 0.00181969, - "globalplace__runtime__total": "0:05.49", - "globalplace__timing__setup__tns": -3.78823, - "globalplace__timing__setup__ws": -0.200349, - "globalplace_io__cpu__total": 4.2, - "globalplace_io__mem__peak": 306356.0, - "globalplace_io__runtime__total": "0:04.54", - "globalplace_skip_io__cpu__total": 4.35, - "globalplace_skip_io__mem__peak": 306516.0, - "globalplace_skip_io__runtime__total": "0:04.62", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.0120769, - "globalroute__clock__skew__setup": 0.0120769, - "globalroute__cpu__total": 9.27, - "globalroute__design__core__area": 6336, - "globalroute__design__die__area": 10080, - "globalroute__design__instance__area": 3027.36, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 3027.36, - "globalroute__design__instance__count": 647, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 21, - "globalroute__design__instance__count__stdcell": 647, - "globalroute__design__instance__displacement__max": 9.8, - "globalroute__design__instance__displacement__mean": 0.3945, - "globalroute__design__instance__displacement__total": 255.4, - "globalroute__design__instance__utilization": 0.477803, - "globalroute__design__instance__utilization__stdcell": 0.477803, - "globalroute__design__io": 54, - "globalroute__design__violations": 0, - "globalroute__flow__errors__count": 0, - "globalroute__flow__warnings__count": 0, - "globalroute__mem__peak": 403744.0, - "globalroute__power__internal__total": 0.0015584, - "globalroute__power__leakage__total": 2.31581e-06, - "globalroute__power__switching__total": 0.00136829, - "globalroute__power__total": 0.00292901, - "globalroute__route__wirelength__estimated": 7292.76, - "globalroute__runtime__total": "0:13.05", - "globalroute__timing__clock__slack": -0.181, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.965314, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.911392, - "globalroute__timing__drv__setup_violation_count": 39, - "globalroute__timing__setup__tns": -4.39264, - "globalroute__timing__setup__ws": -0.181396, - "placeopt__cpu__total": 4.96, - "placeopt__design__core__area": 6336, - "placeopt__design__core__area__pre_opt": 6336, - "placeopt__design__die__area": 10080, - "placeopt__design__die__area__pre_opt": 10080, - "placeopt__design__instance__area": 2477.28, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 2142.72, - "placeopt__design__instance__area__stdcell": 2477.28, - "placeopt__design__instance__area__stdcell__pre_opt": 2142.72, - "placeopt__design__instance__count": 550, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 497, - "placeopt__design__instance__count__stdcell": 550, - "placeopt__design__instance__count__stdcell__pre_opt": 497, - "placeopt__design__instance__utilization": 0.390985, - "placeopt__design__instance__utilization__pre_opt": 0.338182, - "placeopt__design__instance__utilization__stdcell": 0.390985, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.338182, - "placeopt__design__io": 54, - "placeopt__design__io__pre_opt": 54, - "placeopt__flow__errors__count": 0, - "placeopt__flow__warnings__count": 0, - "placeopt__mem__peak": 328468.0, - "placeopt__power__internal__total": 0.00113872, - "placeopt__power__internal__total__pre_opt": 0.000976122, - "placeopt__power__leakage__total": 1.72669e-06, - "placeopt__power__leakage__total__pre_opt": 1.39863e-06, - "placeopt__power__switching__total": 0.000882608, - "placeopt__power__switching__total__pre_opt": 0.000842172, - "placeopt__power__total": 0.00202306, - "placeopt__power__total__pre_opt": 0.00181969, - "placeopt__runtime__total": "0:05.31", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.970237, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.861898, - "placeopt__timing__drv__setup_violation_count": 31, - "placeopt__timing__setup__tns": -1.63194, - "placeopt__timing__setup__tns__pre_opt": -3.78823, - "placeopt__timing__setup__ws": -0.0752369, - "placeopt__timing__setup__ws__pre_opt": -0.200349, - "run__flow__design": "gcd", - "run__flow__generate_date": "2024-04-22 10:56", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-13363-g5aef95740", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "e8072ca1312ab1e9e6a7be8513064a05f42e694f", - "run__flow__scripts_commit": "2c7954aab840678143914048d53dec3846026794", - "run__flow__uuid": "770e5435-8219-4ded-98e3-2eaf132dc92d", - "run__flow__variant": "base", - "synth__cpu__total": 8.29, - "synth__design__instance__area__stdcell": 2168.16, - "synth__design__instance__count__stdcell": 432.0, - "synth__mem__peak": 170220.0, - "synth__runtime__total": "0:08.90", - "total_time": "0:02:40.840000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/ibex/config.mk b/flow/designs/tsmc65lp/ibex/config.mk deleted file mode 100644 index 16405a538a..0000000000 --- a/flow/designs/tsmc65lp/ibex/config.mk +++ /dev/null @@ -1,51 +0,0 @@ -export DESIGN_NICKNAME = ibex -export DESIGN_NAME = ibex_core -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v - - - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export CORE_UTILIZATION = 40 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 5 - -export PLACE_DENSITY = 0.70 diff --git a/flow/designs/tsmc65lp/ibex/constraint.sdc b/flow/designs/tsmc65lp/ibex/constraint.sdc deleted file mode 100644 index f040747cc2..0000000000 --- a/flow/designs/tsmc65lp/ibex/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design ibex_core - -set clk_name core_clock -set clk_port_name clk_i -set clk_period 5.1 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/ibex/metadata-base-ok.json b/flow/designs/tsmc65lp/ibex/metadata-base-ok.json deleted file mode 100644 index a84f3d2aea..0000000000 --- a/flow/designs/tsmc65lp/ibex/metadata-base-ok.json +++ /dev/null @@ -1,359 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 5.1000" - ], - "cts__clock__skew__hold": 0.647425, - "cts__clock__skew__hold__post_repair": 0.649998, - "cts__clock__skew__hold__pre_repair": 0.649998, - "cts__clock__skew__setup": 0.647432, - "cts__clock__skew__setup__post_repair": 0.650004, - "cts__clock__skew__setup__pre_repair": 0.650004, - "cts__cpu__total": 466.6, - "cts__design__core__area": 225620, - "cts__design__core__area__post_repair": 225620, - "cts__design__core__area__pre_repair": 225620, - "cts__design__die__area": 237515, - "cts__design__die__area__post_repair": 237515, - "cts__design__die__area__pre_repair": 237515, - "cts__design__instance__area": 119315, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 115429, - "cts__design__instance__area__pre_repair": 115429, - "cts__design__instance__area__stdcell": 119315, - "cts__design__instance__area__stdcell__post_repair": 115429, - "cts__design__instance__area__stdcell__pre_repair": 115429, - "cts__design__instance__count": 15023, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 14500, - "cts__design__instance__count__pre_repair": 14500, - "cts__design__instance__count__setup_buffer": 405, - "cts__design__instance__count__stdcell": 15023, - "cts__design__instance__count__stdcell__post_repair": 14500, - "cts__design__instance__count__stdcell__pre_repair": 14500, - "cts__design__instance__displacement__max": 47.3685, - "cts__design__instance__displacement__mean": 0.868, - "cts__design__instance__displacement__total": 13047.1, - "cts__design__instance__utilization": 0.528831, - "cts__design__instance__utilization__post_repair": 0.511607, - "cts__design__instance__utilization__pre_repair": 0.511607, - "cts__design__instance__utilization__stdcell": 0.528831, - "cts__design__instance__utilization__stdcell__post_repair": 0.511607, - "cts__design__instance__utilization__stdcell__pre_repair": 0.511607, - "cts__design__io": 264, - "cts__design__io__post_repair": 264, - "cts__design__io__pre_repair": 264, - "cts__design__violations": 0, - "cts__mem__peak": 386976.0, - "cts__power__internal__total": 0.104514, - "cts__power__internal__total__post_repair": 0.101899, - "cts__power__internal__total__pre_repair": 0.101899, - "cts__power__leakage__total": 0.000113298, - "cts__power__leakage__total__post_repair": 0.000108316, - "cts__power__leakage__total__pre_repair": 0.000108316, - "cts__power__switching__total": 0.0937996, - "cts__power__switching__total__post_repair": 0.0956379, - "cts__power__switching__total__pre_repair": 0.0956379, - "cts__power__total": 0.198427, - "cts__power__total__post_repair": 0.197645, - "cts__power__total__pre_repair": 0.197645, - "cts__route__wirelength__estimated": 430444, - "cts__runtime__total": "7:52.20", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 0, - "cts__timing__drv__hold_violation_count__pre_repair": 0, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.0661567, - "cts__timing__drv__max_cap_limit__post_repair": 0.0675806, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0675806, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.100063, - "cts__timing__drv__max_slew_limit__post_repair": 0.101393, - "cts__timing__drv__max_slew_limit__pre_repair": 0.101393, - "cts__timing__drv__setup_violation_count": 212, - "cts__timing__drv__setup_violation_count__post_repair": 1417, - "cts__timing__drv__setup_violation_count__pre_repair": 1417, - "cts__timing__setup__tns": -28.2432, - "cts__timing__setup__tns__post_repair": -1191.62, - "cts__timing__setup__tns__pre_repair": -1191.62, - "cts__timing__setup__ws": -0.353791, - "cts__timing__setup__ws__post_repair": -2.02556, - "cts__timing__setup__ws__pre_repair": -2.02556, - "design__io__hpwl": 75002692, - "detailedplace__cpu__total": 13.41, - "detailedplace__design__core__area": 225620, - "detailedplace__design__die__area": 237515, - "detailedplace__design__instance__area": 111218, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 111218, - "detailedplace__design__instance__count": 14242, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 14242, - "detailedplace__design__instance__displacement__max": 41.265, - "detailedplace__design__instance__displacement__mean": 2.337, - "detailedplace__design__instance__displacement__total": 33283.7, - "detailedplace__design__instance__utilization": 0.492945, - "detailedplace__design__instance__utilization__stdcell": 0.492945, - "detailedplace__design__io": 264, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 359428.0, - "detailedplace__power__internal__total": 0.0976673, - "detailedplace__power__leakage__total": 6.99549e-05, - "detailedplace__power__switching__total": 0.0932149, - "detailedplace__power__total": 0.190952, - "detailedplace__route__wirelength__estimated": 365429, - "detailedplace__runtime__total": "0:14.96", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0675806, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.101393, - "detailedplace__timing__drv__setup_violation_count": 1364, - "detailedplace__timing__setup__tns": -842.68, - "detailedplace__timing__setup__ws": -1.70144, - "detailedroute__cpu__total": 1369.2, - "detailedroute__mem__peak": 2164848.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 8090, - "detailedroute__route__drc_errors__iter:2": 430, - "detailedroute__route__drc_errors__iter:3": 267, - "detailedroute__route__drc_errors__iter:4": 3, - "detailedroute__route__drc_errors__iter:5": 0, - "detailedroute__route__net": 14042, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 116774, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 116774, - "detailedroute__route__wirelength": 598923, - "detailedroute__route__wirelength__iter:1": 601606, - "detailedroute__route__wirelength__iter:2": 599593, - "detailedroute__route__wirelength__iter:3": 598987, - "detailedroute__route__wirelength__iter:4": 598926, - "detailedroute__route__wirelength__iter:5": 598923, - "detailedroute__runtime__total": "1:12.97", - "fillcell__cpu__total": 3.38, - "fillcell__mem__peak": 331472.0, - "fillcell__runtime__total": "0:03.86", - "finish__clock__skew__hold": 0.558615, - "finish__clock__skew__setup": 0.558625, - "finish__cpu__total": 47.35, - "finish__design__core__area": 225620, - "finish__design__die__area": 237515, - "finish__design__instance__area": 124509, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 124509, - "finish__design__instance__count": 15173, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 15173, - "finish__design__instance__utilization": 0.551853, - "finish__design__instance__utilization__stdcell": 0.551853, - "finish__design__io": 264, - "finish__mem__peak": 1436780.0, - "finish__power__internal__total": 0.102683, - "finish__power__leakage__total": 0.000119454, - "finish__power__switching__total": 0.0784521, - "finish__power__total": 0.181254, - "finish__runtime__total": "0:50.51", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.182329, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.229282, - "finish__timing__drv__setup_violation_count": 6, - "finish__timing__setup__tns": -0.123078, - "finish__timing__setup__ws": -0.0344227, - "finish__timing__wns_percent_delay": -0.836088, - "finish_merge__cpu__total": 7.8, - "finish_merge__mem__peak": 468728.0, - "finish_merge__runtime__total": "0:09.72", - "floorplan__cpu__total": 8.05, - "floorplan__design__core__area": 225620, - "floorplan__design__die__area": 237515, - "floorplan__design__instance__area": 85956, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 85956, - "floorplan__design__instance__count": 12661, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 12661, - "floorplan__design__instance__utilization": 0.380977, - "floorplan__design__instance__utilization__stdcell": 0.380977, - "floorplan__design__io": 264, - "floorplan__mem__peak": 334028.0, - "floorplan__power__internal__total": 0.0791751, - "floorplan__power__leakage__total": 5.57928e-05, - "floorplan__power__switching__total": 0.0344279, - "floorplan__power__total": 0.113659, - "floorplan__runtime__total": "0:09.26", - "floorplan__timing__setup__tns": -11260.1, - "floorplan__timing__setup__ws": -4.64408, - "floorplan_io__cpu__total": 3.11, - "floorplan_io__mem__peak": 293292.0, - "floorplan_io__runtime__total": "0:03.47", - "floorplan_macro__cpu__total": 3.2, - "floorplan_macro__mem__peak": 293820.0, - "floorplan_macro__runtime__total": "0:03.58", - "floorplan_pdn__cpu__total": 3.41, - "floorplan_pdn__mem__peak": 295196.0, - "floorplan_pdn__runtime__total": "0:03.72", - "floorplan_tap__cpu__total": 3.35, - "floorplan_tap__mem__peak": 285064.0, - "floorplan_tap__runtime__total": "0:03.74", - "floorplan_tdms__cpu__total": 3.37, - "floorplan_tdms__mem__peak": 293084.0, - "floorplan_tdms__runtime__total": "0:03.76", - "globalplace__cpu__total": 85.0, - "globalplace__design__core__area": 225620, - "globalplace__design__die__area": 237515, - "globalplace__design__instance__area": 87193.4, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 87193.4, - "globalplace__design__instance__count": 13950, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 13950, - "globalplace__design__instance__utilization": 0.386461, - "globalplace__design__instance__utilization__stdcell": 0.386461, - "globalplace__design__io": 264, - "globalplace__mem__peak": 535028.0, - "globalplace__power__internal__total": 0.0806074, - "globalplace__power__leakage__total": 5.57928e-05, - "globalplace__power__switching__total": 0.0805885, - "globalplace__power__total": 0.161252, - "globalplace__runtime__total": "0:55.25", - "globalplace__timing__setup__tns": -36418.1, - "globalplace__timing__setup__ws": -14.0594, - "globalplace_io__cpu__total": 3.28, - "globalplace_io__mem__peak": 294828.0, - "globalplace_io__runtime__total": "0:03.63", - "globalplace_skip_io__cpu__total": 7.47, - "globalplace_skip_io__mem__peak": 313252.0, - "globalplace_skip_io__runtime__total": "0:07.84", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.649684, - "globalroute__clock__skew__setup": 0.649686, - "globalroute__cpu__total": 276.64, - "globalroute__design__core__area": 225620, - "globalroute__design__die__area": 237515, - "globalroute__design__instance__area": 124509, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 124509, - "globalroute__design__instance__count": 15173, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__setup_buffer": 131, - "globalroute__design__instance__count__stdcell": 15173, - "globalroute__design__instance__displacement__max": 69, - "globalroute__design__instance__displacement__mean": 1.0245, - "globalroute__design__instance__displacement__total": 15549.6, - "globalroute__design__instance__utilization": 0.551853, - "globalroute__design__instance__utilization__stdcell": 0.551853, - "globalroute__design__io": 264, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 720944.0, - "globalroute__power__internal__total": 0.101975, - "globalroute__power__leakage__total": 0.000119369, - "globalroute__power__switching__total": 0.102253, - "globalroute__power__total": 0.204347, - "globalroute__route__wirelength__estimated": 485474, - "globalroute__runtime__total": "4:43.83", - "globalroute__timing__clock__slack": -0.65, - "globalroute__timing__drv__hold_violation_count": 0, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0509953, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.109241, - "globalroute__timing__drv__setup_violation_count": 426, - "globalroute__timing__setup__tns": -106.265, - "globalroute__timing__setup__ws": -0.649757, - "placeopt__cpu__total": 17.42, - "placeopt__design__core__area": 225620, - "placeopt__design__core__area__pre_opt": 225620, - "placeopt__design__die__area": 237515, - "placeopt__design__die__area__pre_opt": 237515, - "placeopt__design__instance__area": 111218, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 87193.4, - "placeopt__design__instance__area__stdcell": 111218, - "placeopt__design__instance__area__stdcell__pre_opt": 87193.4, - "placeopt__design__instance__count": 14242, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 13950, - "placeopt__design__instance__count__stdcell": 14242, - "placeopt__design__instance__count__stdcell__pre_opt": 13950, - "placeopt__design__instance__utilization": 0.492945, - "placeopt__design__instance__utilization__pre_opt": 0.386461, - "placeopt__design__instance__utilization__stdcell": 0.492945, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.386461, - "placeopt__design__io": 264, - "placeopt__design__io__pre_opt": 264, - "placeopt__mem__peak": 381172.0, - "placeopt__power__internal__total": 0.0967359, - "placeopt__power__internal__total__pre_opt": 0.0806074, - "placeopt__power__leakage__total": 6.98846e-05, - "placeopt__power__leakage__total__pre_opt": 5.57928e-05, - "placeopt__power__switching__total": 0.0909615, - "placeopt__power__switching__total__pre_opt": 0.0805885, - "placeopt__power__total": 0.187767, - "placeopt__power__total__pre_opt": 0.161252, - "placeopt__runtime__total": "0:20.17", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 0, - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0556316, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0900055, - "placeopt__timing__drv__setup_violation_count": 1351, - "placeopt__timing__setup__tns": -797.195, - "placeopt__timing__setup__tns__pre_opt": -36418.1, - "placeopt__timing__setup__ws": -1.68717, - "placeopt__timing__setup__ws__pre_opt": -14.0594, - "run__flow__design": "ibex", - "run__flow__generate_date": "2024-01-25 05:43", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-11995-g7e7e83500", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "730fc586e5c9b66fa3a4f855f18f25797b654914", - "run__flow__scripts_commit": "bdf0e94c27fb849bd6466e55ca3962863c35d431", - "run__flow__uuid": "5cc95cf4-1bcc-420b-86ad-a98812c9ed9c", - "run__flow__variant": "base", - "synth__cpu__total": 107.96, - "synth__design__instance__area__stdcell": 91147.2, - "synth__design__instance__count__stdcell": 13902.0, - "synth__mem__peak": 254832.0, - "synth__runtime__total": "1:49.81", - "total_time": "0:18:52.280000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/ibex/rules-base.json b/flow/designs/tsmc65lp/ibex/rules-base.json deleted file mode 100644 index 51c362c1ac..0000000000 --- a/flow/designs/tsmc65lp/ibex/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 100571.09, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 122160, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 15569, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 1354, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 1354, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 688761, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.28, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 129165, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 677, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -11.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/jpeg/config.mk b/flow/designs/tsmc65lp/jpeg/config.mk deleted file mode 100644 index 65077f3e2f..0000000000 --- a/flow/designs/tsmc65lp/jpeg/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -export DESIGN_NICKNAME = jpeg -export DESIGN_NAME = jpeg_encoder -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v)) -export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc -export ABC_AREA = 1 - -export CORE_UTILIZATION = 40 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 5 - -export PLACE_DENSITY = 0.70 diff --git a/flow/designs/tsmc65lp/jpeg/constraint.sdc b/flow/designs/tsmc65lp/jpeg/constraint.sdc deleted file mode 100644 index ba4cb6213a..0000000000 --- a/flow/designs/tsmc65lp/jpeg/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design jpeg_encoder - -set clk_name clk -set clk_port_name clk -set clk_period 3.2 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json b/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json deleted file mode 100644 index 06b21a0391..0000000000 --- a/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json +++ /dev/null @@ -1,354 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "clk: 3.2000" - ], - "cts__clock__skew__hold": 0.29481, - "cts__clock__skew__hold__post_repair": 0.294476, - "cts__clock__skew__hold__pre_repair": 0.294476, - "cts__clock__skew__setup": 0.29481, - "cts__clock__skew__setup__post_repair": 0.294476, - "cts__clock__skew__setup__pre_repair": 0.294476, - "cts__cpu__total": 1650.15, - "cts__design__core__area": 851558, - "cts__design__core__area__post_repair": 851558, - "cts__design__core__area__pre_repair": 851558, - "cts__design__die__area": 872590, - "cts__design__die__area__post_repair": 872590, - "cts__design__die__area__pre_repair": 872590, - "cts__design__instance__area": 418366, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 413476, - "cts__design__instance__area__pre_repair": 413476, - "cts__design__instance__area__stdcell": 418366, - "cts__design__instance__area__stdcell__post_repair": 413476, - "cts__design__instance__area__stdcell__pre_repair": 413476, - "cts__design__instance__count": 65274, - "cts__design__instance__count__hold_buffer": 406, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 64653, - "cts__design__instance__count__pre_repair": 64653, - "cts__design__instance__count__setup_buffer": 131, - "cts__design__instance__count__stdcell": 65274, - "cts__design__instance__count__stdcell__post_repair": 64653, - "cts__design__instance__count__stdcell__pre_repair": 64653, - "cts__design__instance__displacement__max": 32.295, - "cts__design__instance__displacement__mean": 0.1095, - "cts__design__instance__displacement__total": 7162.9, - "cts__design__instance__utilization": 0.491294, - "cts__design__instance__utilization__post_repair": 0.485552, - "cts__design__instance__utilization__pre_repair": 0.485552, - "cts__design__instance__utilization__stdcell": 0.491294, - "cts__design__instance__utilization__stdcell__post_repair": 0.485552, - "cts__design__instance__utilization__stdcell__pre_repair": 0.485552, - "cts__design__io": 47, - "cts__design__io__post_repair": 47, - "cts__design__io__pre_repair": 47, - "cts__design__violations": 0, - "cts__mem__peak": 677876.0, - "cts__power__internal__total": 0.462799, - "cts__power__internal__total__post_repair": 0.458481, - "cts__power__internal__total__pre_repair": 0.458481, - "cts__power__leakage__total": 0.000374005, - "cts__power__leakage__total__post_repair": 0.000369577, - "cts__power__leakage__total__pre_repair": 0.000369577, - "cts__power__switching__total": 0.318035, - "cts__power__switching__total__post_repair": 0.311752, - "cts__power__switching__total__pre_repair": 0.311752, - "cts__power__total": 0.781209, - "cts__power__total__post_repair": 0.770602, - "cts__power__total__pre_repair": 0.770602, - "cts__route__wirelength__estimated": 1137010.0, - "cts__runtime__total": "32:15.04", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 1055, - "cts__timing__drv__hold_violation_count__pre_repair": 1055, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.893917, - "cts__timing__drv__max_cap_limit__post_repair": 0.379496, - "cts__timing__drv__max_cap_limit__pre_repair": 0.379496, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.70433, - "cts__timing__drv__max_slew_limit__post_repair": 0.706738, - "cts__timing__drv__max_slew_limit__pre_repair": 0.706738, - "cts__timing__drv__setup_violation_count": 283, - "cts__timing__drv__setup_violation_count__post_repair": 598, - "cts__timing__drv__setup_violation_count__pre_repair": 598, - "cts__timing__setup__tns": -37.001, - "cts__timing__setup__tns__post_repair": -373.066, - "cts__timing__setup__tns__pre_repair": -373.066, - "cts__timing__setup__ws": -0.41448, - "cts__timing__setup__ws__post_repair": -1.45297, - "cts__timing__setup__ws__pre_repair": -1.45297, - "cts_fill__cpu__total": 4.64, - "cts_fill__mem__peak": 506416.0, - "cts_fill__runtime__total": "0:05.34", - "design__io__hpwl": 20784763, - "detailedplace__cpu__total": 44.22, - "detailedplace__design__core__area": 851558, - "detailedplace__design__die__area": 872590, - "detailedplace__design__instance__area": 412333, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 412333, - "detailedplace__design__instance__count": 64415, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 64415, - "detailedplace__design__instance__displacement__max": 33.31, - "detailedplace__design__instance__displacement__mean": 1.8865, - "detailedplace__design__instance__displacement__total": 121545, - "detailedplace__design__instance__utilization": 0.48421, - "detailedplace__design__instance__utilization__stdcell": 0.48421, - "detailedplace__design__io": 47, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 616716.0, - "detailedplace__power__internal__total": 0.457463, - "detailedplace__power__leakage__total": 0.000368192, - "detailedplace__power__switching__total": 0.305846, - "detailedplace__power__total": 0.763677, - "detailedplace__route__wirelength__estimated": 1099920.0, - "detailedplace__runtime__total": "0:52.19", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.379496, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.520309, - "detailedplace__timing__drv__setup_violation_count": 748, - "detailedplace__timing__setup__tns": -441.402, - "detailedplace__timing__setup__ws": -1.39438, - "detailedroute__cpu__total": 1896.39, - "detailedroute__mem__peak": 5385136.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 16473, - "detailedroute__route__drc_errors__iter:2": 3614, - "detailedroute__route__drc_errors__iter:3": 3318, - "detailedroute__route__drc_errors__iter:4": 9, - "detailedroute__route__drc_errors__iter:5": 3, - "detailedroute__route__drc_errors__iter:6": 3, - "detailedroute__route__drc_errors__iter:7": 0, - "detailedroute__route__net": 61061, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 352515, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 352515, - "detailedroute__route__wirelength": 1254986, - "detailedroute__route__wirelength__iter:1": 1263031, - "detailedroute__route__wirelength__iter:2": 1256415, - "detailedroute__route__wirelength__iter:3": 1255071, - "detailedroute__route__wirelength__iter:4": 1254992, - "detailedroute__route__wirelength__iter:5": 1254990, - "detailedroute__route__wirelength__iter:6": 1254988, - "detailedroute__route__wirelength__iter:7": 1254986, - "detailedroute__runtime__total": "2:35.68", - "finish__clock__skew__hold": 0.220416, - "finish__clock__skew__setup": 0.220416, - "finish__cpu__total": 66.17, - "finish__design__core__area": 851558, - "finish__design__die__area": 872590, - "finish__design__instance__area": 418366, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 418366, - "finish__design__instance__count": 65274, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 65274, - "finish__design__instance__utilization": 0.491294, - "finish__design__instance__utilization__stdcell": 0.491294, - "finish__design__io": 47, - "finish__mem__peak": 1177636.0, - "finish__power__internal__total": 0.463657, - "finish__power__leakage__total": 0.000374005, - "finish__power__switching__total": 0.274611, - "finish__power__total": 0.738642, - "finish__runtime__total": "1:07.38", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.955989, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.801705, - "finish__timing__drv__setup_violation_count": 4, - "finish__timing__setup__tns": -0.108871, - "finish__timing__setup__ws": -0.0396967, - "finish__timing__wns_percent_delay": -0.974329, - "finish_merge__cpu__total": 14.56, - "finish_merge__mem__peak": 987632.0, - "finish_merge__runtime__total": "0:16.62", - "floorplan__cpu__total": 14.91, - "floorplan__design__core__area": 851558, - "floorplan__design__die__area": 872590, - "floorplan__design__instance__area": 332575, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 332575, - "floorplan__design__instance__count": 59878, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 59878, - "floorplan__design__instance__utilization": 0.390549, - "floorplan__design__instance__utilization__stdcell": 0.390549, - "floorplan__design__io": 47, - "floorplan__mem__peak": 522332.0, - "floorplan__power__internal__total": 0.406883, - "floorplan__power__leakage__total": 0.000264106, - "floorplan__power__switching__total": 0.194444, - "floorplan__power__total": 0.601591, - "floorplan__runtime__total": "0:15.56", - "floorplan__timing__setup__tns": -98443.2, - "floorplan__timing__setup__ws": -43.1878, - "floorplan_io__cpu__total": 3.91, - "floorplan_io__mem__peak": 392528.0, - "floorplan_io__runtime__total": "0:04.24", - "floorplan_macro__cpu__total": 3.81, - "floorplan_macro__mem__peak": 391144.0, - "floorplan_macro__runtime__total": "0:04.09", - "floorplan_pdn__cpu__total": 4.35, - "floorplan_pdn__mem__peak": 397420.0, - "floorplan_pdn__runtime__total": "0:04.82", - "floorplan_tap__cpu__total": 3.66, - "floorplan_tap__mem__peak": 349328.0, - "floorplan_tap__runtime__total": "0:03.90", - "floorplan_tdms__cpu__total": 3.94, - "floorplan_tdms__mem__peak": 392292.0, - "floorplan_tdms__runtime__total": "0:04.35", - "globalplace__cpu__total": 211.39, - "globalplace__design__core__area": 851558, - "globalplace__design__die__area": 872590, - "globalplace__design__instance__area": 336648, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 336648, - "globalplace__design__instance__count": 64120, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 64120, - "globalplace__design__instance__utilization": 0.395331, - "globalplace__design__instance__utilization__stdcell": 0.395331, - "globalplace__design__io": 47, - "globalplace__mem__peak": 961384.0, - "globalplace__power__internal__total": 0.416877, - "globalplace__power__leakage__total": 0.000264106, - "globalplace__power__switching__total": 0.279911, - "globalplace__power__total": 0.697052, - "globalplace__runtime__total": "4:34.05", - "globalplace__timing__setup__tns": -180571, - "globalplace__timing__setup__ws": -96.3078, - "globalplace_io__cpu__total": 3.87, - "globalplace_io__mem__peak": 398368.0, - "globalplace_io__runtime__total": "0:04.21", - "globalplace_skip_io__cpu__total": 28.74, - "globalplace_skip_io__mem__peak": 469916.0, - "globalplace_skip_io__runtime__total": "0:29.18", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.313374, - "globalroute__clock__skew__setup": 0.313374, - "globalroute__cpu__total": 33.02, - "globalroute__design__core__area": 851558, - "globalroute__design__die__area": 872590, - "globalroute__design__instance__area": 418366, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 418366, - "globalroute__design__instance__count": 65274, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 65274, - "globalroute__design__instance__utilization": 0.491294, - "globalroute__design__instance__utilization__stdcell": 0.491294, - "globalroute__design__io": 47, - "globalroute__mem__peak": 1232536.0, - "globalroute__power__internal__total": 0.462737, - "globalroute__power__leakage__total": 0.000374005, - "globalroute__power__switching__total": 0.353287, - "globalroute__power__total": 0.816398, - "globalroute__runtime__total": "0:34.37", - "globalroute__timing__clock__slack": -0.709, - "globalroute__timing__drv__hold_violation_count": 3, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.29525, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.319501, - "globalroute__timing__drv__setup_violation_count": 518, - "globalroute__timing__setup__tns": -136.808, - "globalroute__timing__setup__ws": -0.708531, - "placeopt__cpu__total": 44.16, - "placeopt__design__core__area": 851558, - "placeopt__design__core__area__pre_opt": 851558, - "placeopt__design__die__area": 872590, - "placeopt__design__die__area__pre_opt": 872590, - "placeopt__design__instance__area": 412333, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 336648, - "placeopt__design__instance__area__stdcell": 412333, - "placeopt__design__instance__area__stdcell__pre_opt": 336648, - "placeopt__design__instance__count": 64415, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 64120, - "placeopt__design__instance__count__stdcell": 64415, - "placeopt__design__instance__count__stdcell__pre_opt": 64120, - "placeopt__design__instance__utilization": 0.48421, - "placeopt__design__instance__utilization__pre_opt": 0.395331, - "placeopt__design__instance__utilization__stdcell": 0.48421, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.395331, - "placeopt__design__io": 47, - "placeopt__design__io__pre_opt": 47, - "placeopt__mem__peak": 592532.0, - "placeopt__power__internal__total": 0.457204, - "placeopt__power__internal__total__pre_opt": 0.416877, - "placeopt__power__leakage__total": 0.000368192, - "placeopt__power__leakage__total__pre_opt": 0.000264106, - "placeopt__power__switching__total": 0.299922, - "placeopt__power__switching__total__pre_opt": 0.279911, - "placeopt__power__total": 0.757495, - "placeopt__power__total__pre_opt": 0.697052, - "placeopt__runtime__total": "1:09.97", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.385241, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.518978, - "placeopt__timing__drv__setup_violation_count": 774, - "placeopt__timing__setup__tns": -445.447, - "placeopt__timing__setup__tns__pre_opt": -180571, - "placeopt__timing__setup__ws": -1.42461, - "placeopt__timing__setup__ws__pre_opt": -96.3078, - "run__flow__design": "jpeg", - "run__flow__generate_date": "2023-08-01 13:41", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9491-g3aee924c6", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "0f508c2255c5b75b9a9388ad26548583a1b38ec0", - "run__flow__uuid": "16b31f45-3eb7-4736-b3e0-264307403b90", - "run__flow__variant": "base", - "synth__cpu__total": 177.63, - "synth__design__instance__area__stdcell": 341603.04, - "synth__design__instance__count__stdcell": 61842.0, - "synth__mem__peak": 858932.0, - "synth__runtime__total": "3:04.29", - "total_time": "0:47:45.280000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/jpeg/rules-base.json b/flow/designs/tsmc65lp/jpeg/rules-base.json deleted file mode 100644 index 062e0b109e..0000000000 --- a/flow/designs/tsmc65lp/jpeg/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 392843.5, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 1, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 474183, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 74077, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 6442, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 6442, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 1443234, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": -0.19, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 481121, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 3221, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 100, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -11.16, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/swerv/config.mk b/flow/designs/tsmc65lp/swerv/config.mk deleted file mode 100644 index 52cd636c16..0000000000 --- a/flow/designs/tsmc65lp/swerv/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -export DESIGN_NAME = swerv -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -# These values must be multiples of placement site -export DIE_AREA = 0 0 1550 1341.6 -export CORE_AREA = 10 12 1540 1332 diff --git a/flow/designs/tsmc65lp/swerv/constraint.sdc b/flow/designs/tsmc65lp/swerv/constraint.sdc deleted file mode 100644 index c634e454ee..0000000000 --- a/flow/designs/tsmc65lp/swerv/constraint.sdc +++ /dev/null @@ -1,13 +0,0 @@ -set clk_name core_clock -set clk_port_name clk -set clk_period 7.4 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/swerv/metadata-base-ok.json b/flow/designs/tsmc65lp/swerv/metadata-base-ok.json deleted file mode 100644 index 908d3d497c..0000000000 --- a/flow/designs/tsmc65lp/swerv/metadata-base-ok.json +++ /dev/null @@ -1,358 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 7.4000" - ], - "cts__clock__skew__hold": 0.329568, - "cts__clock__skew__hold__post_repair": 0.321714, - "cts__clock__skew__hold__pre_repair": 0.38867, - "cts__clock__skew__setup": 0.329568, - "cts__clock__skew__setup__post_repair": 0.321714, - "cts__clock__skew__setup__pre_repair": 0.38867, - "cts__cpu__total": 295.44, - "cts__design__core__area": 2019600.0, - "cts__design__core__area__post_repair": 2019600.0, - "cts__design__core__area__pre_repair": 2019600.0, - "cts__design__die__area": 2079480.0, - "cts__design__die__area__post_repair": 2079480.0, - "cts__design__die__area__pre_repair": 2079480.0, - "cts__design__instance__area": 638253, - "cts__design__instance__area__macros": 0, - "cts__design__instance__area__macros__post_repair": 0, - "cts__design__instance__area__macros__pre_repair": 0, - "cts__design__instance__area__post_repair": 628705, - "cts__design__instance__area__pre_repair": 628689, - "cts__design__instance__area__stdcell": 638253, - "cts__design__instance__area__stdcell__post_repair": 628705, - "cts__design__instance__area__stdcell__pre_repair": 628689, - "cts__design__instance__count": 82281, - "cts__design__instance__count__hold_buffer": 1313, - "cts__design__instance__count__macros": 0, - "cts__design__instance__count__macros__post_repair": 0, - "cts__design__instance__count__macros__pre_repair": 0, - "cts__design__instance__count__post_repair": 80873, - "cts__design__instance__count__pre_repair": 80872, - "cts__design__instance__count__setup_buffer": 67, - "cts__design__instance__count__stdcell": 82281, - "cts__design__instance__count__stdcell__post_repair": 80873, - "cts__design__instance__count__stdcell__pre_repair": 80872, - "cts__design__instance__displacement__max": 56.4, - "cts__design__instance__displacement__mean": 0.431, - "cts__design__instance__displacement__total": 35463.7, - "cts__design__instance__utilization": 0.316029, - "cts__design__instance__utilization__post_repair": 0.311302, - "cts__design__instance__utilization__pre_repair": 0.311294, - "cts__design__instance__utilization__stdcell": 0.316029, - "cts__design__instance__utilization__stdcell__post_repair": 0.311302, - "cts__design__instance__utilization__stdcell__pre_repair": 0.311294, - "cts__design__io": 2039, - "cts__design__io__post_repair": 2039, - "cts__design__io__pre_repair": 2039, - "cts__design__violations": 0, - "cts__mem__peak": 897692.0, - "cts__power__internal__total": 0.062205, - "cts__power__internal__total__post_repair": 0.0619545, - "cts__power__internal__total__pre_repair": 0.0619435, - "cts__power__leakage__total": 0.000405226, - "cts__power__leakage__total__post_repair": 0.000400598, - "cts__power__leakage__total__pre_repair": 0.000400564, - "cts__power__switching__total": 0.065899, - "cts__power__switching__total__post_repair": 0.0656431, - "cts__power__switching__total__pre_repair": 0.0656114, - "cts__power__total": 0.128509, - "cts__power__total__post_repair": 0.127998, - "cts__power__total__pre_repair": 0.127955, - "cts__route__wirelength__estimated": 3552200.0, - "cts__runtime__total": "5:25.47", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 1422, - "cts__timing__drv__hold_violation_count__pre_repair": 1816, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.109215, - "cts__timing__drv__max_cap_limit__post_repair": 0.0662517, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0662517, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.0313695, - "cts__timing__drv__max_slew_limit__post_repair": 0.0411454, - "cts__timing__drv__max_slew_limit__pre_repair": 0.0411454, - "cts__timing__drv__setup_violation_count": 3, - "cts__timing__drv__setup_violation_count__post_repair": 666, - "cts__timing__drv__setup_violation_count__pre_repair": 667, - "cts__timing__setup__tns": -0.525373, - "cts__timing__setup__tns__post_repair": -395.714, - "cts__timing__setup__tns__pre_repair": -397.237, - "cts__timing__setup__ws": -0.175827, - "cts__timing__setup__ws__post_repair": -2.12297, - "cts__timing__setup__ws__pre_repair": -2.18993, - "cts_fill__cpu__total": 5.3, - "cts_fill__mem__peak": 687764.0, - "cts_fill__runtime__total": "0:06.29", - "design__io__hpwl": 1128162890, - "detailedplace__cpu__total": 77.79, - "detailedplace__design__core__area": 2019600.0, - "detailedplace__design__die__area": 2079480.0, - "detailedplace__design__instance__area": 625881, - "detailedplace__design__instance__area__macros": 0, - "detailedplace__design__instance__area__stdcell": 625881, - "detailedplace__design__instance__count": 80287, - "detailedplace__design__instance__count__macros": 0, - "detailedplace__design__instance__count__stdcell": 80287, - "detailedplace__design__instance__displacement__max": 27.9, - "detailedplace__design__instance__displacement__mean": 1.5755, - "detailedplace__design__instance__displacement__total": 126528, - "detailedplace__design__instance__utilization": 0.309904, - "detailedplace__design__instance__utilization__stdcell": 0.309904, - "detailedplace__design__io": 2039, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 836232.0, - "detailedplace__power__internal__total": 0.0608631, - "detailedplace__power__leakage__total": 0.000397159, - "detailedplace__power__switching__total": 0.0588243, - "detailedplace__power__total": 0.120085, - "detailedplace__route__wirelength__estimated": 3487480.0, - "detailedplace__runtime__total": "1:30.47", - "detailedplace__timing__drv__hold_violation_count": 0, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0662517, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0411454, - "detailedplace__timing__drv__setup_violation_count": 635, - "detailedplace__timing__setup__tns": -343.563, - "detailedplace__timing__setup__ws": -1.29517, - "detailedroute__cpu__total": 3971.5, - "detailedroute__mem__peak": 7493348.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 40289, - "detailedroute__route__drc_errors__iter:2": 8073, - "detailedroute__route__drc_errors__iter:3": 7180, - "detailedroute__route__drc_errors__iter:4": 26, - "detailedroute__route__drc_errors__iter:5": 6, - "detailedroute__route__drc_errors__iter:6": 2, - "detailedroute__route__drc_errors__iter:7": 2, - "detailedroute__route__drc_errors__iter:8": 2, - "detailedroute__route__drc_errors__iter:9": 0, - "detailedroute__route__net": 73674, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 611531, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 611531, - "detailedroute__route__wirelength": 4589355, - "detailedroute__route__wirelength__iter:1": 4602075, - "detailedroute__route__wirelength__iter:2": 4592947, - "detailedroute__route__wirelength__iter:3": 4589626, - "detailedroute__route__wirelength__iter:4": 4589357, - "detailedroute__route__wirelength__iter:5": 4589355, - "detailedroute__route__wirelength__iter:6": 4589355, - "detailedroute__route__wirelength__iter:7": 4589355, - "detailedroute__route__wirelength__iter:8": 4589357, - "detailedroute__route__wirelength__iter:9": 4589355, - "detailedroute__runtime__total": "5:06.81", - "finish__clock__skew__hold": 0.350095, - "finish__clock__skew__setup": 0.350095, - "finish__cpu__total": 150.82, - "finish__design__core__area": 2019600.0, - "finish__design__die__area": 2079480.0, - "finish__design__instance__area": 638253, - "finish__design__instance__area__macros": 0, - "finish__design__instance__area__stdcell": 638253, - "finish__design__instance__count": 82281, - "finish__design__instance__count__macros": 0, - "finish__design__instance__count__stdcell": 82281, - "finish__design__instance__utilization": 0.316029, - "finish__design__instance__utilization__stdcell": 0.316029, - "finish__design__io": 2039, - "finish__mem__peak": 1660288.0, - "finish__power__internal__total": 0.0625005, - "finish__power__leakage__total": 0.000405226, - "finish__power__switching__total": 0.0525994, - "finish__power__total": 0.115505, - "finish__runtime__total": "2:36.95", - "finish__timing__drv__hold_violation_count": 0, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.294017, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.191298, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.551193, - "finish__timing__wns_percent_delay": 10.266726, - "finish_merge__cpu__total": 23.32, - "finish_merge__mem__peak": 1266100.0, - "finish_merge__runtime__total": "0:24.42", - "floorplan__cpu__total": 26.71, - "floorplan__design__core__area": 2019600.0, - "floorplan__design__die__area": 2079480.0, - "floorplan__design__instance__area": 456378, - "floorplan__design__instance__area__macros": 0, - "floorplan__design__instance__area__stdcell": 456378, - "floorplan__design__instance__count": 68448, - "floorplan__design__instance__count__macros": 0, - "floorplan__design__instance__count__stdcell": 68448, - "floorplan__design__instance__utilization": 0.225974, - "floorplan__design__instance__utilization__stdcell": 0.225974, - "floorplan__design__io": 2039, - "floorplan__mem__peak": 619748.0, - "floorplan__power__internal__total": 0.0746046, - "floorplan__power__leakage__total": 0.000257094, - "floorplan__power__switching__total": 0.0169612, - "floorplan__power__total": 0.0918229, - "floorplan__runtime__total": "0:29.68", - "floorplan__timing__setup__tns": -830657, - "floorplan__timing__setup__ws": -92.1604, - "floorplan_io__cpu__total": 4.06, - "floorplan_io__mem__peak": 419504.0, - "floorplan_io__runtime__total": "0:06.36", - "floorplan_macro__cpu__total": 3.82, - "floorplan_macro__mem__peak": 416224.0, - "floorplan_macro__runtime__total": "0:04.10", - "floorplan_pdn__cpu__total": 4.9, - "floorplan_pdn__mem__peak": 426460.0, - "floorplan_pdn__runtime__total": "0:05.53", - "floorplan_tap__cpu__total": 3.67, - "floorplan_tap__mem__peak": 369104.0, - "floorplan_tap__runtime__total": "0:03.88", - "floorplan_tdms__cpu__total": 4.09, - "floorplan_tdms__mem__peak": 417768.0, - "floorplan_tdms__runtime__total": "0:04.40", - "globalplace__cpu__total": 396.47, - "globalplace__design__core__area": 2019600.0, - "globalplace__design__die__area": 2079480.0, - "globalplace__design__instance__area": 465383, - "globalplace__design__instance__area__macros": 0, - "globalplace__design__instance__area__stdcell": 465383, - "globalplace__design__instance__count": 77828, - "globalplace__design__instance__count__macros": 0, - "globalplace__design__instance__count__stdcell": 77828, - "globalplace__design__instance__utilization": 0.230433, - "globalplace__design__instance__utilization__stdcell": 0.230433, - "globalplace__design__io": 2039, - "globalplace__mem__peak": 1199952.0, - "globalplace__power__internal__total": 0.101693, - "globalplace__power__leakage__total": 0.000257094, - "globalplace__power__switching__total": 0.0493149, - "globalplace__power__total": 0.151265, - "globalplace__runtime__total": "7:41.77", - "globalplace__timing__setup__tns": -1885340.0, - "globalplace__timing__setup__ws": -183.298, - "globalplace_io__cpu__total": 4.31, - "globalplace_io__mem__peak": 431992.0, - "globalplace_io__runtime__total": "0:04.83", - "globalplace_skip_io__cpu__total": 41.9, - "globalplace_skip_io__mem__peak": 522460.0, - "globalplace_skip_io__runtime__total": "0:43.32", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.342178, - "globalroute__clock__skew__setup": 0.342178, - "globalroute__cpu__total": 85.38, - "globalroute__design__core__area": 2019600.0, - "globalroute__design__die__area": 2079480.0, - "globalroute__design__instance__area": 638253, - "globalroute__design__instance__area__macros": 0, - "globalroute__design__instance__area__stdcell": 638253, - "globalroute__design__instance__count": 82281, - "globalroute__design__instance__count__macros": 0, - "globalroute__design__instance__count__stdcell": 82281, - "globalroute__design__instance__utilization": 0.316029, - "globalroute__design__instance__utilization__stdcell": 0.316029, - "globalroute__design__io": 2039, - "globalroute__mem__peak": 1782084.0, - "globalroute__power__internal__total": 0.0626149, - "globalroute__power__leakage__total": 0.000405226, - "globalroute__power__switching__total": 0.0710369, - "globalroute__power__total": 0.134057, - "globalroute__runtime__total": "1:27.57", - "globalroute__timing__clock__slack": -0.676, - "globalroute__timing__drv__hold_violation_count": 13, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.0297508, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 32, - "globalroute__timing__drv__max_slew_limit": -0.0364853, - "globalroute__timing__drv__setup_violation_count": 45, - "globalroute__timing__setup__tns": -6.73746, - "globalroute__timing__setup__ws": -0.675905, - "placeopt__cpu__total": 86.75, - "placeopt__design__core__area": 2019600.0, - "placeopt__design__core__area__pre_opt": 2019600.0, - "placeopt__design__die__area": 2079480.0, - "placeopt__design__die__area__pre_opt": 2079480.0, - "placeopt__design__instance__area": 625881, - "placeopt__design__instance__area__macros": 0, - "placeopt__design__instance__area__macros__pre_opt": 0, - "placeopt__design__instance__area__pre_opt": 465383, - "placeopt__design__instance__area__stdcell": 625881, - "placeopt__design__instance__area__stdcell__pre_opt": 465383, - "placeopt__design__instance__count": 80287, - "placeopt__design__instance__count__macros": 0, - "placeopt__design__instance__count__macros__pre_opt": 0, - "placeopt__design__instance__count__pre_opt": 77828, - "placeopt__design__instance__count__stdcell": 80287, - "placeopt__design__instance__count__stdcell__pre_opt": 77828, - "placeopt__design__instance__utilization": 0.309904, - "placeopt__design__instance__utilization__pre_opt": 0.230433, - "placeopt__design__instance__utilization__stdcell": 0.309904, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.230433, - "placeopt__design__io": 2039, - "placeopt__design__io__pre_opt": 2039, - "placeopt__mem__peak": 748112.0, - "placeopt__power__internal__total": 0.0600132, - "placeopt__power__internal__total__pre_opt": 0.101693, - "placeopt__power__leakage__total": 0.000397159, - "placeopt__power__leakage__total__pre_opt": 0.000257094, - "placeopt__power__switching__total": 0.0574003, - "placeopt__power__switching__total__pre_opt": 0.0493149, - "placeopt__power__total": 0.117811, - "placeopt__power__total__pre_opt": 0.151265, - "placeopt__runtime__total": "1:52.02", - "placeopt__timing__drv__hold_violation_count": 0, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0613162, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.0127814, - "placeopt__timing__drv__setup_violation_count": 633, - "placeopt__timing__setup__tns": -303.619, - "placeopt__timing__setup__tns__pre_opt": -1885340.0, - "placeopt__timing__setup__ws": -1.28198, - "placeopt__timing__setup__ws__pre_opt": -183.298, - "run__flow__design": "swerv", - "run__flow__generate_date": "2023-08-01 13:39", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9491-g3aee924c6", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "0f508c2255c5b75b9a9388ad26548583a1b38ec0", - "run__flow__uuid": "0f2e542d-f0a8-4fee-8619-9814a52ea3c5", - "run__flow__variant": "base", - "synth__cpu__total": 975.81, - "synth__design__instance__area__stdcell": 485918.88, - "synth__design__instance__count__stdcell": 76786.0, - "synth__mem__peak": 3216416.0, - "synth__runtime__total": "18:25.99", - "total_time": "0:46:19.860000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/swerv_wrapper/config.mk b/flow/designs/tsmc65lp/swerv_wrapper/config.mk deleted file mode 100644 index 0b2ea6472b..0000000000 --- a/flow/designs/tsmc65lp/swerv_wrapper/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -export DESIGN_NAME = swerv_wrapper -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 - -# RTL_MP Settings -export RTLMP_MAX_INST = 30000 -export RTLMP_MIN_INST = 5000 -export RTLMP_MAX_MACRO = 12 -export RTLMP_MIN_MACRO = 4 - -export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg11_w40_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w22_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg8_w34_all.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg11_w40_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w22_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg8_w34_all_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg11_w40_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w22_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg8_w34_all.gds2 - -export REMOVE_BUFFER_TREE = 1 - -export DIE_AREA = 0 0 1610 1360 -export CORE_AREA = 5 5 1605 1355 -export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-300 -exclude bottom:1300-1600 - -export MACRO_PLACE_HALO = 10 10 -export MACRO_PLACE_CHANNEL = 20 20 - -export PLACE_DENSITY_LB_ADDON = 0.10 diff --git a/flow/designs/tsmc65lp/swerv_wrapper/constraint.sdc b/flow/designs/tsmc65lp/swerv_wrapper/constraint.sdc deleted file mode 100644 index aca09c5ae5..0000000000 --- a/flow/designs/tsmc65lp/swerv_wrapper/constraint.sdc +++ /dev/null @@ -1,66 +0,0 @@ -############################################################################### -# Created by write_sdc -# Sat Nov 7 14:46:58 2020 -############################################################################### -current_design swerv_wrapper -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name core_clock -period 8.0000 -waveform {0.0000 4.0000} [get_ports {clk}] -set_clock_uncertainty -setup .250 core_clock -set_clock_uncertainty -hold .250 core_clock -#set_propagated_clock [get_clocks {core_clock}] -create_clock -name jtag_clock -period 8.0000 -waveform {0.0000 4.0000} [get_ports {jtag_tck}] -set_clock_uncertainty -setup .250 jtag_clock -set_clock_uncertainty -hold .250 jtag_clock -#set_propagated_clock [get_clocks {jtag_clock}] - -# There is sync logic between jtag and core_clock -#set_clock_groups -logically_exclusive -group {core_clock} -group {jtag_clock} - -############################################################################### -# Environment -############################################################################### -############################################################################### -# Design Rules -############################################################################### -set clock_ports "jtag_tck clk" -set jtag_ports "jtag_id* jtag_tdi jtag_tms jtag_trst_n" -#set input_not_jtag_ports [remove_from_collection [all_inputs] "$jtag_ports $clock_ports"] -set input_not_jtag_ports [list] -foreach input [all_inputs] { - set addFlag 1 - foreach s [get_ports "$clock_ports $jtag_ports"] { - if { $s == $input } { - set addFlag 0 - break - } - } - if { $addFlag } { - lappend input_not_jtag_ports $input - } -} -set_input_delay 2.500 -clock jtag_clock $jtag_ports -set_output_delay 2.500 -clock jtag_clock [get_ports "jtag_tdo"] -set_input_delay 4.000 -clock core_clock $input_not_jtag_ports -#set_output_delay 7500 -clock core_clock [remove_from_collection [all_outputs] "jtag_tdo"] -set ports_list [list] -foreach output [all_outputs] { - set addFlag 1 - foreach s [get_ports "jtag_tdo"] { - if { $s == $output } { - set addFlag 0 - break - } - } - if { $addFlag } { - lappend ports_list $output - } -} -set_output_delay 4.000 -clock core_clock $ports_list - -set_driving_cell -lib_cell BUFH_X2M_A12TR [all_inputs] - -set_load 0 [all_inputs] - - diff --git a/flow/designs/tsmc65lp/swerv_wrapper/macros.v b/flow/designs/tsmc65lp/swerv_wrapper/macros.v deleted file mode 100644 index 69696e4345..0000000000 --- a/flow/designs/tsmc65lp/swerv_wrapper/macros.v +++ /dev/null @@ -1,49 +0,0 @@ -module ram_2048x39(CLK, ADR, D, Q, WE); - input CLK, WE; - input [10:0] ADR; - input [38:0] D; - output [38:0] Q; - wire CLK, WE; - wire [10:0] ADR; - wire [38:0] D; - wire [38:0] Q; - wire [39:0] Q_int; - wire n_21; - tsmc65lp_1rf_lg11_w40_all mem(.CLK (CLK), .Q ({Q_int[39], Q}), .CEN - (1'b1), .WEN (n_21), .A (ADR), .D ({1'b0, D}), .EMA (3'b011), - .EMAW (2'b01), .RET1N (1'b1)); - assign n_21 = ~(WE); -endmodule - -module ram_64x21(CLK, ADR, D, Q, WE); - input CLK, WE; - input [5:0] ADR; - input [20:0] D; - output [20:0] Q; - wire CLK, WE; - wire [5:0] ADR; - wire [20:0] D; - wire [20:0] Q; - wire [21:0] Q_int; - wire n_16; - tsmc65lp_1rf_lg6_w22_all mem(.CLK (CLK), .Q ({Q_int[21], Q}), .CEN - (1'b1), .WEN (n_16), .A (ADR), .D ({1'b0, D}), .EMA (3'b011), - .EMAW (2'b01), .RET1N (1'b1)); - assign n_16 = ~(WE); -endmodule - -module ram_256x34(CLK, ADR, D, Q, WE); - input CLK, WE; - input [7:0] ADR; - input [33:0] D; - output [33:0] Q; - wire CLK, WE; - wire [7:0] ADR; - wire [33:0] D; - wire [33:0] Q; - wire n_51; - tsmc65lp_1rf_lg8_w34_all mem(.CLK (CLK), .Q (Q), .CEN (1'b1), .WEN - (n_51), .A (ADR), .D (D), .EMA (3'b011), .EMAW (2'b01), .RET1N - (1'b1)); - assign n_51 = ~(WE); -endmodule diff --git a/flow/designs/tsmc65lp/swerv_wrapper/metadata-base-ok.json b/flow/designs/tsmc65lp/swerv_wrapper/metadata-base-ok.json deleted file mode 100644 index eb9591a8c2..0000000000 --- a/flow/designs/tsmc65lp/swerv_wrapper/metadata-base-ok.json +++ /dev/null @@ -1,363 +0,0 @@ -{ - "constraints__clocks__count": 2, - "constraints__clocks__details": [ - "core_clock: 8.0000", - "jtag_clock: 8.0000" - ], - "cts__clock__skew__hold": 0.358019, - "cts__clock__skew__hold__post_repair": 0.394966, - "cts__clock__skew__hold__pre_repair": 0.394966, - "cts__clock__skew__setup": 0.358019, - "cts__clock__skew__setup__post_repair": 0.394966, - "cts__clock__skew__setup__pre_repair": 0.394966, - "cts__cpu__total": 188.94, - "cts__design__core__area": 2154240.0, - "cts__design__core__area__post_repair": 2154240.0, - "cts__design__core__area__pre_repair": 2154240.0, - "cts__design__die__area": 2189600.0, - "cts__design__die__area__post_repair": 2189600.0, - "cts__design__die__area__pre_repair": 2189600.0, - "cts__design__instance__area": 1335300.0, - "cts__design__instance__area__macros": 631737, - "cts__design__instance__area__macros__post_repair": 631737, - "cts__design__instance__area__macros__pre_repair": 631737, - "cts__design__instance__area__post_repair": 1322570.0, - "cts__design__instance__area__pre_repair": 1322550.0, - "cts__design__instance__area__stdcell": 703566, - "cts__design__instance__area__stdcell__post_repair": 690832, - "cts__design__instance__area__stdcell__pre_repair": 690816, - "cts__design__instance__count": 90998, - "cts__design__instance__count__hold_buffer": 1845, - "cts__design__instance__count__macros": 28, - "cts__design__instance__count__macros__post_repair": 28, - "cts__design__instance__count__macros__pre_repair": 28, - "cts__design__instance__count__post_repair": 89098, - "cts__design__instance__count__pre_repair": 89097, - "cts__design__instance__count__setup_buffer": 50, - "cts__design__instance__count__stdcell": 90970, - "cts__design__instance__count__stdcell__post_repair": 89070, - "cts__design__instance__count__stdcell__pre_repair": 89069, - "cts__design__instance__displacement__max": 88.8, - "cts__design__instance__displacement__mean": 0.227, - "cts__design__instance__displacement__total": 20666.6, - "cts__design__instance__utilization": 0.619849, - "cts__design__instance__utilization__post_repair": 0.613938, - "cts__design__instance__utilization__pre_repair": 0.61393, - "cts__design__instance__utilization__stdcell": 0.462112, - "cts__design__instance__utilization__stdcell__post_repair": 0.453747, - "cts__design__instance__utilization__stdcell__pre_repair": 0.453737, - "cts__design__io": 1416, - "cts__design__io__post_repair": 1416, - "cts__design__io__pre_repair": 1416, - "cts__design__violations": 0, - "cts__mem__peak": 980952.0, - "cts__power__internal__total": 0.0959598, - "cts__power__internal__total__post_repair": 0.0956861, - "cts__power__internal__total__pre_repair": 0.0956761, - "cts__power__leakage__total": 0.00052797, - "cts__power__leakage__total__post_repair": 0.000522222, - "cts__power__leakage__total__pre_repair": 0.000522188, - "cts__power__switching__total": 0.095099, - "cts__power__switching__total__post_repair": 0.0951358, - "cts__power__switching__total__pre_repair": 0.0951068, - "cts__power__total": 0.191587, - "cts__power__total__post_repair": 0.191344, - "cts__power__total__pre_repair": 0.191305, - "cts__route__wirelength__estimated": 4415420.0, - "cts__runtime__total": "3:10.53", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 1816, - "cts__timing__drv__hold_violation_count__pre_repair": 1816, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.0199013, - "cts__timing__drv__max_cap_limit__post_repair": 0.0177606, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0177606, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 65, - "cts__timing__drv__max_slew__pre_repair": 65, - "cts__timing__drv__max_slew_limit": 0.00556065, - "cts__timing__drv__max_slew_limit__post_repair": -0.0725642, - "cts__timing__drv__max_slew_limit__pre_repair": -0.072643, - "cts__timing__drv__setup_violation_count": 2, - "cts__timing__drv__setup_violation_count__post_repair": 18, - "cts__timing__drv__setup_violation_count__pre_repair": 75, - "cts__timing__setup__tns": -0.0814597, - "cts__timing__setup__tns__post_repair": -1.7874, - "cts__timing__setup__tns__pre_repair": -23.857, - "cts__timing__setup__ws": -0.0797686, - "cts__timing__setup__ws__post_repair": -0.511323, - "cts__timing__setup__ws__pre_repair": -0.854263, - "cts_fill__cpu__total": 5.45, - "cts_fill__mem__peak": 718928.0, - "cts_fill__runtime__total": "0:05.98", - "design__io__hpwl": 2251853000, - "detailedplace__cpu__total": 68.73, - "detailedplace__design__core__area": 2154240.0, - "detailedplace__design__die__area": 2189600.0, - "detailedplace__design__instance__area": 1320180.0, - "detailedplace__design__instance__area__macros": 631737, - "detailedplace__design__instance__area__stdcell": 688440, - "detailedplace__design__instance__count": 88602, - "detailedplace__design__instance__count__macros": 28, - "detailedplace__design__instance__count__stdcell": 88574, - "detailedplace__design__instance__displacement__max": 81.356, - "detailedplace__design__instance__displacement__mean": 2.303, - "detailedplace__design__instance__displacement__total": 204080, - "detailedplace__design__instance__utilization": 0.612827, - "detailedplace__design__instance__utilization__stdcell": 0.452176, - "detailedplace__design__io": 1416, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 897568.0, - "detailedplace__power__internal__total": 0.0949237, - "detailedplace__power__leakage__total": 0.000519307, - "detailedplace__power__switching__total": 0.0891704, - "detailedplace__power__total": 0.184613, - "detailedplace__route__wirelength__estimated": 4382630.0, - "detailedplace__runtime__total": "1:09.70", - "detailedplace__timing__drv__hold_violation_count": 1744, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0177606, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 65, - "detailedplace__timing__drv__max_slew_limit": -0.0725642, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 0.270749, - "detailedroute__cpu__total": 4691.14, - "detailedroute__mem__peak": 8622720.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 48980, - "detailedroute__route__drc_errors__iter:10": 1, - "detailedroute__route__drc_errors__iter:11": 0, - "detailedroute__route__drc_errors__iter:2": 9499, - "detailedroute__route__drc_errors__iter:3": 8408, - "detailedroute__route__drc_errors__iter:4": 36, - "detailedroute__route__drc_errors__iter:5": 6, - "detailedroute__route__drc_errors__iter:6": 5, - "detailedroute__route__drc_errors__iter:7": 4, - "detailedroute__route__drc_errors__iter:8": 1, - "detailedroute__route__drc_errors__iter:9": 1, - "detailedroute__route__net": 82790, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 698334, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 698334, - "detailedroute__route__wirelength": 5459937, - "detailedroute__route__wirelength__iter:1": 5476026, - "detailedroute__route__wirelength__iter:10": 5459938, - "detailedroute__route__wirelength__iter:11": 5459937, - "detailedroute__route__wirelength__iter:2": 5464647, - "detailedroute__route__wirelength__iter:3": 5460169, - "detailedroute__route__wirelength__iter:4": 5459936, - "detailedroute__route__wirelength__iter:5": 5459936, - "detailedroute__route__wirelength__iter:6": 5459933, - "detailedroute__route__wirelength__iter:7": 5459934, - "detailedroute__route__wirelength__iter:8": 5459936, - "detailedroute__route__wirelength__iter:9": 5459936, - "detailedroute__runtime__total": "5:20.42", - "finish__clock__skew__hold": 0.29809, - "finish__clock__skew__setup": 0.29809, - "finish__cpu__total": 173.05, - "finish__design__core__area": 2154240.0, - "finish__design__die__area": 2189600.0, - "finish__design__instance__area": 1335300.0, - "finish__design__instance__area__macros": 631737, - "finish__design__instance__area__stdcell": 703566, - "finish__design__instance__count": 90998, - "finish__design__instance__count__macros": 28, - "finish__design__instance__count__stdcell": 90970, - "finish__design__instance__utilization": 0.619849, - "finish__design__instance__utilization__stdcell": 0.462112, - "finish__design__io": 1416, - "finish__mem__peak": 1769024.0, - "finish__power__internal__total": 0.0968642, - "finish__power__leakage__total": 0.00052797, - "finish__power__switching__total": 0.0743369, - "finish__power__total": 0.171729, - "finish__runtime__total": "3:05.85", - "finish__timing__drv__hold_violation_count": 200, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.19195, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.14988, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.510855, - "finish__timing__wns_percent_delay": 15.7729, - "finish_merge__cpu__total": 30.59, - "finish_merge__mem__peak": 1339220.0, - "finish_merge__runtime__total": "0:33.17", - "floorplan__cpu__total": 27.92, - "floorplan__design__core__area": 2154240.0, - "floorplan__design__die__area": 2189600.0, - "floorplan__design__instance__area": 1131950.0, - "floorplan__design__instance__area__macros": 631737, - "floorplan__design__instance__area__stdcell": 500216, - "floorplan__design__instance__count": 76300, - "floorplan__design__instance__count__macros": 28, - "floorplan__design__instance__count__stdcell": 76272, - "floorplan__design__instance__utilization": 0.525453, - "floorplan__design__instance__utilization__stdcell": 0.328548, - "floorplan__design__io": 1416, - "floorplan__mem__peak": 659932.0, - "floorplan__power__internal__total": 0.0789691, - "floorplan__power__leakage__total": 0.000357924, - "floorplan__power__switching__total": 0.0217307, - "floorplan__power__total": 0.101058, - "floorplan__runtime__total": "0:29.57", - "floorplan__timing__setup__tns": -179528, - "floorplan__timing__setup__ws": -23.9251, - "floorplan_io__cpu__total": 4.05, - "floorplan_io__mem__peak": 437888.0, - "floorplan_io__runtime__total": "0:05.07", - "floorplan_macro__cpu__total": 51.66, - "floorplan_macro__mem__peak": 778364.0, - "floorplan_macro__runtime__total": "0:23.70", - "floorplan_pdn__cpu__total": 16.44, - "floorplan_pdn__mem__peak": 758184.0, - "floorplan_pdn__runtime__total": "0:17.93", - "floorplan_tap__cpu__total": 3.76, - "floorplan_tap__mem__peak": 390704.0, - "floorplan_tap__runtime__total": "0:04.03", - "floorplan_tdms__cpu__total": 4.17, - "floorplan_tdms__mem__peak": 434892.0, - "floorplan_tdms__runtime__total": "0:04.97", - "globalplace__cpu__total": 386.26, - "globalplace__design__core__area": 2154240.0, - "globalplace__design__die__area": 2189600.0, - "globalplace__design__instance__area": 1141230.0, - "globalplace__design__instance__area__macros": 631737, - "globalplace__design__instance__area__stdcell": 509495, - "globalplace__design__instance__count": 85966, - "globalplace__design__instance__count__macros": 28, - "globalplace__design__instance__count__stdcell": 85938, - "globalplace__design__instance__utilization": 0.529761, - "globalplace__design__instance__utilization__stdcell": 0.334643, - "globalplace__design__io": 1416, - "globalplace__mem__peak": 1461820.0, - "globalplace__power__internal__total": 0.0862643, - "globalplace__power__leakage__total": 0.000357924, - "globalplace__power__switching__total": 0.0768396, - "globalplace__power__total": 0.163462, - "globalplace__runtime__total": "6:34.15", - "globalplace__timing__setup__tns": -491050, - "globalplace__timing__setup__ws": -63.3297, - "globalplace_io__cpu__total": 4.24, - "globalplace_io__mem__peak": 463040.0, - "globalplace_io__runtime__total": "0:04.88", - "globalplace_skip_io__cpu__total": 3.83, - "globalplace_skip_io__mem__peak": 395752.0, - "globalplace_skip_io__runtime__total": "0:04.10", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.367048, - "globalroute__clock__skew__setup": 0.367048, - "globalroute__cpu__total": 102.63, - "globalroute__design__core__area": 2154240.0, - "globalroute__design__die__area": 2189600.0, - "globalroute__design__instance__area": 1335300.0, - "globalroute__design__instance__area__macros": 631737, - "globalroute__design__instance__area__stdcell": 703566, - "globalroute__design__instance__count": 90998, - "globalroute__design__instance__count__macros": 28, - "globalroute__design__instance__count__stdcell": 90970, - "globalroute__design__instance__utilization": 0.619849, - "globalroute__design__instance__utilization__stdcell": 0.462112, - "globalroute__design__io": 1416, - "globalroute__mem__peak": 1968164.0, - "globalroute__power__internal__total": 0.0969751, - "globalroute__power__leakage__total": 0.00052797, - "globalroute__power__switching__total": 0.10186, - "globalroute__power__total": 0.199363, - "globalroute__runtime__total": "1:44.36", - "globalroute__timing__clock__slack": "N/A", - "globalroute__timing__drv__hold_violation_count": 7, - "globalroute__timing__drv__max_cap": 2, - "globalroute__timing__drv__max_cap_limit": -0.0109445, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 98, - "globalroute__timing__drv__max_slew_limit": -0.0827188, - "globalroute__timing__drv__setup_violation_count": 55, - "globalroute__timing__setup__tns": -4.03154, - "globalroute__timing__setup__ws": -0.461758, - "placeopt__cpu__total": 81.56, - "placeopt__design__core__area": 2154240.0, - "placeopt__design__core__area__pre_opt": 2154240.0, - "placeopt__design__die__area": 2189600.0, - "placeopt__design__die__area__pre_opt": 2189600.0, - "placeopt__design__instance__area": 1320180.0, - "placeopt__design__instance__area__macros": 631737, - "placeopt__design__instance__area__macros__pre_opt": 631737, - "placeopt__design__instance__area__pre_opt": 1141230.0, - "placeopt__design__instance__area__stdcell": 688440, - "placeopt__design__instance__area__stdcell__pre_opt": 509495, - "placeopt__design__instance__count": 88602, - "placeopt__design__instance__count__macros": 28, - "placeopt__design__instance__count__macros__pre_opt": 28, - "placeopt__design__instance__count__pre_opt": 85966, - "placeopt__design__instance__count__stdcell": 88574, - "placeopt__design__instance__count__stdcell__pre_opt": 85938, - "placeopt__design__instance__utilization": 0.612827, - "placeopt__design__instance__utilization__pre_opt": 0.529761, - "placeopt__design__instance__utilization__stdcell": 0.452176, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.334643, - "placeopt__design__io": 1416, - "placeopt__design__io__pre_opt": 1416, - "placeopt__mem__peak": 820076.0, - "placeopt__power__internal__total": 0.0914652, - "placeopt__power__internal__total__pre_opt": 0.0862643, - "placeopt__power__leakage__total": 0.000519307, - "placeopt__power__leakage__total__pre_opt": 0.000357924, - "placeopt__power__switching__total": 0.0802365, - "placeopt__power__switching__total__pre_opt": 0.0768396, - "placeopt__power__total": 0.172221, - "placeopt__power__total__pre_opt": 0.163462, - "placeopt__runtime__total": "1:22.74", - "placeopt__timing__drv__hold_violation_count": 1746, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0324288, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.00899143, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": -0.54692, - "placeopt__timing__setup__tns__pre_opt": -491050, - "placeopt__timing__setup__ws": 0.309463, - "placeopt__timing__setup__ws__pre_opt": -63.3297, - "run__flow__design": "swerv_wrapper", - "run__flow__generate_date": "2023-08-01 14:05", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9491-g3aee924c6", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "0f508c2255c5b75b9a9388ad26548583a1b38ec0", - "run__flow__uuid": "60e951cf-7e63-4a3d-b692-5b21f616fd6e", - "run__flow__variant": "base", - "synth__cpu__total": 771.43, - "synth__design__instance__area__stdcell": 1168552.112, - "synth__design__instance__count__stdcell": 85920.0, - "synth__mem__peak": 2136384.0, - "synth__runtime__total": "14:07.60", - "total_time": "0:38:48.750000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/swerv_wrapper/rules-base.json b/flow/designs/tsmc65lp/swerv_wrapper/rules-base.json deleted file mode 100644 index ad625b4adf..0000000000 --- a/flow/designs/tsmc65lp/swerv_wrapper/rules-base.json +++ /dev/null @@ -1,58 +0,0 @@ -{ - "synth__design__instance__area__stdcell": { - "value": 1343834.93, - "compare": "<=" - }, - "constraints__clocks__count": { - "value": 2, - "compare": "==" - }, - "placeopt__design__instance__area": { - "value": 1518207, - "compare": "<=" - }, - "placeopt__design__instance__count__stdcell": { - "value": 101860, - "compare": "<=" - }, - "detailedplace__design__violations": { - "value": 0, - "compare": "==" - }, - "cts__design__instance__count__setup_buffer": { - "value": 8857, - "compare": "<=" - }, - "cts__design__instance__count__hold_buffer": { - "value": 8857, - "compare": "<=" - }, - "detailedroute__route__wirelength": { - "value": 6278928, - "compare": "<=" - }, - "detailedroute__route__drc_errors": { - "value": 0, - "compare": "<=" - }, - "finish__timing__setup__ws": { - "value": 0.0, - "compare": ">=" - }, - "finish__design__instance__area": { - "value": 1535595, - "compare": "<=" - }, - "finish__timing__drv__setup_violation_count": { - "value": 4429, - "compare": "<=" - }, - "finish__timing__drv__hold_violation_count": { - "value": 350, - "compare": "<=" - }, - "finish__timing__wns_percent_delay": { - "value": -10.0, - "compare": ">=" - } -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/tinyRocket/config.mk b/flow/designs/tsmc65lp/tinyRocket/config.mk deleted file mode 100644 index 9d43e434da..0000000000 --- a/flow/designs/tsmc65lp/tinyRocket/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -export DESIGN_NICKNAME = tinyRocket -export DESIGN_NAME = RocketTile -export PLATFORM = tsmc65lp - -export SYNTH_HIERARCHICAL = 1 -export MAX_UNGROUP_SIZE ?= 5000 - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider2.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ClockDivider3.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/plusarg_reader.v \ - $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/freechips.rocketchip.system.TinyConfig.v \ - $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v - -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_byte.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg6_w32_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg10_w32_bit.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w32_byte_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg6_w32_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_2rf_lg10_w32_bit_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w32_byte.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w32_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg10_w32_bit.gds2 - -# These values must be multiples of placement site -export DIE_AREA = 0 0 925 806.4 -export CORE_AREA = 10 12 915 796.8 diff --git a/flow/designs/tsmc65lp/tinyRocket/constraint.sdc b/flow/designs/tsmc65lp/tinyRocket/constraint.sdc deleted file mode 100644 index 05e3e26c90..0000000000 --- a/flow/designs/tsmc65lp/tinyRocket/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design RocketTile - -set clk_name core_clock -set clk_port_name clock -set clk_period 5.6 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/flow/designs/tsmc65lp/tinyRocket/macros.v b/flow/designs/tsmc65lp/tinyRocket/macros.v deleted file mode 100644 index 74e9561a50..0000000000 --- a/flow/designs/tsmc65lp/tinyRocket/macros.v +++ /dev/null @@ -1,148 +0,0 @@ - -module data_arrays_0_ext( - input RW0_clk, - input [5:0] RW0_addr, - input RW0_en, - input RW0_wmode, - input [3:0] RW0_wmask, - input [31:0] RW0_wdata, - output [31:0] RW0_rdata -); - - wire [31:0] wen = ~ { {8{RW0_wmask[3]}} - ,{8{RW0_wmask[2]}} - ,{8{RW0_wmask[1]}} - ,{8{RW0_wmask[0]}}}; - - tsmc65lp_1rf_lg6_w32_byte mem ( - .CLK (RW0_clk ), - .Q (RW0_rdata ), // out - .CEN (~RW0_en ), // lo true - .WEN (wen ), // lo true - .GWEN (~RW0_wmode), // lo true - .A (RW0_addr ), // in - .D (RW0_wdata ), // in - .EMA (3'd3 ), // Extra Margin Adjustment - default value - .EMAW (2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N(1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - - -// # This is a very small array. Leaving is as synthesized - -module tag_array_ext( - input RW0_clk, - input [1:0] RW0_addr, - input RW0_en, - input RW0_wmode, - input [0:0] RW0_wmask, - input [24:0] RW0_wdata, - output [24:0] RW0_rdata -); - - reg reg_RW0_ren; - reg [1:0] reg_RW0_addr; - reg [24:0] ram [3:0]; - `ifdef RANDOMIZE_MEM_INIT - integer initvar; - initial begin - #`RANDOMIZE_DELAY begin end - for (initvar = 0; initvar < 4; initvar = initvar+1) - ram[initvar] = {1 {$random}}; - reg_RW0_addr = {1 {$random}}; - end - `endif - integer i; - always @(posedge RW0_clk) - reg_RW0_ren <= RW0_en && !RW0_wmode; - always @(posedge RW0_clk) - if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; - always @(posedge RW0_clk) - if (RW0_en && RW0_wmode) begin - for(i=0;i<1;i=i+1) begin - if(RW0_wmask[i]) begin - ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25]; - end - end - end - `ifdef RANDOMIZE_GARBAGE_ASSIGN - reg [31:0] RW0_random; - `ifdef RANDOMIZE_MEM_INIT - initial begin - #`RANDOMIZE_DELAY begin end - RW0_random = {$random}; - reg_RW0_ren = RW0_random[0]; - end - `endif - always @(posedge RW0_clk) RW0_random <= {$random}; - assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[24:0]; - `else - assign RW0_rdata = ram[reg_RW0_addr]; - `endif - -endmodule - -module data_arrays_0_0_ext( - input RW0_clk, - input [5:0] RW0_addr, - input RW0_en, - input RW0_wmode, - input [0:0] RW0_wmask, - input [31:0] RW0_wdata, - output [31:0] RW0_rdata -); - - tsmc65lp_1rf_lg6_w32_all mem ( - .CLK ( RW0_clk ), - .Q ( RW0_rdata), // out - .CEN (~RW0_en ), // lo true - .WEN (~RW0_wmode), // lo true - .A ( RW0_addr ), // in - .D ( RW0_wdata), // in - .EMA ( 3'd3 ), // Extra Margin Adjustment - default value - .EMAW ( 2'd1 ), // Extra Margin Adjustment Write - default value - .RET1N( 1'b1 ) // Retention Mode (active low) - disabled - ); - -endmodule - -module mem_ext( - input W0_clk, - input [9:0] W0_addr, - input W0_en, - input [31:0] W0_data, - input [3:0] W0_mask, - input R0_clk, - input [9:0] R0_addr, - input R0_en, - output [31:0] R0_data -); - - wire [31:0] wen = ~ { {8{W0_mask[3]}} - ,{8{W0_mask[2]}} - ,{8{W0_mask[1]}} - ,{8{W0_mask[0]}}}; - - tsmc65lp_2rf_lg10_w32_bit mem ( - .CLKA (W0_clk) - ,.CLKB (W0_clk) - /// Read port - ,.AA (R0_addr) - ,.CENA (~R0_en) - ,.QA (R0_data) - - /// Write port - ,.AB (W0_addr) - ,.DB (W0_data) - ,.CENB (~W0_en) - ,.WENB (~wen) - - ,.EMAA (3'd3 ) - ,.EMAB (3'd3 ) - ,.RET1N (1'b1 ) - ); - - -endmodule diff --git a/flow/designs/tsmc65lp/tinyRocket/metadata-base-ok.json b/flow/designs/tsmc65lp/tinyRocket/metadata-base-ok.json deleted file mode 100644 index d5afff35ba..0000000000 --- a/flow/designs/tsmc65lp/tinyRocket/metadata-base-ok.json +++ /dev/null @@ -1,348 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clock: 5.6000" - ], - "cts__clock__skew__hold": 0.283591, - "cts__clock__skew__hold__post_repair": 0.292246, - "cts__clock__skew__hold__pre_repair": 0.292246, - "cts__clock__skew__setup": 0.283591, - "cts__clock__skew__setup__post_repair": 0.292246, - "cts__clock__skew__setup__pre_repair": 0.292246, - "cts__cpu__total": 51.28, - "cts__design__core__area": 710244, - "cts__design__core__area__post_repair": 710244, - "cts__design__core__area__pre_repair": 710244, - "cts__design__die__area": 745920, - "cts__design__die__area__post_repair": 745920, - "cts__design__die__area__pre_repair": 745920, - "cts__design__instance__area": 208115, - "cts__design__instance__area__macros": 10379.2, - "cts__design__instance__area__macros__post_repair": 10379.2, - "cts__design__instance__area__macros__pre_repair": 10379.2, - "cts__design__instance__area__post_repair": 207212, - "cts__design__instance__area__pre_repair": 207212, - "cts__design__instance__area__stdcell": 197736, - "cts__design__instance__area__stdcell__post_repair": 196833, - "cts__design__instance__area__stdcell__pre_repair": 196833, - "cts__design__instance__count": 27307, - "cts__design__instance__count__hold_buffer": 132, - "cts__design__instance__count__macros": 2, - "cts__design__instance__count__macros__post_repair": 2, - "cts__design__instance__count__macros__pre_repair": 2, - "cts__design__instance__count__post_repair": 27174, - "cts__design__instance__count__pre_repair": 27174, - "cts__design__instance__count__setup_buffer": 1, - "cts__design__instance__count__stdcell": 27305, - "cts__design__instance__count__stdcell__post_repair": 27172, - "cts__design__instance__count__stdcell__pre_repair": 27172, - "cts__design__instance__displacement__max": 14.872, - "cts__design__instance__displacement__mean": 0.03, - "cts__design__instance__displacement__total": 826.295, - "cts__design__instance__utilization": 0.293019, - "cts__design__instance__utilization__post_repair": 0.291747, - "cts__design__instance__utilization__pre_repair": 0.291747, - "cts__design__instance__utilization__stdcell": 0.282535, - "cts__design__instance__utilization__stdcell__post_repair": 0.281244, - "cts__design__instance__utilization__stdcell__pre_repair": 0.281244, - "cts__design__io": 269, - "cts__design__io__post_repair": 269, - "cts__design__io__pre_repair": 269, - "cts__design__violations": 0, - "cts__mem__peak": 539540.0, - "cts__power__internal__total": 0.0928524, - "cts__power__internal__total__post_repair": 0.0928494, - "cts__power__internal__total__pre_repair": 0.0928494, - "cts__power__leakage__total": 0.000128693, - "cts__power__leakage__total__post_repair": 0.000128282, - "cts__power__leakage__total__pre_repair": 0.000128282, - "cts__power__switching__total": 0.0803065, - "cts__power__switching__total__post_repair": 0.0795879, - "cts__power__switching__total__pre_repair": 0.0795879, - "cts__power__total": 0.173288, - "cts__power__total__post_repair": 0.172566, - "cts__power__total__pre_repair": 0.172566, - "cts__route__wirelength__estimated": 840922, - "cts__runtime__total": "0:54.41", - "cts__timing__drv__hold_violation_count": 0, - "cts__timing__drv__hold_violation_count__post_repair": 183, - "cts__timing__drv__hold_violation_count__pre_repair": 183, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.0326332, - "cts__timing__drv__max_cap_limit__post_repair": 0.0337628, - "cts__timing__drv__max_cap_limit__pre_repair": 0.0337628, - "cts__timing__drv__max_fanout": 0, - "cts__timing__drv__max_fanout__post_repair": 0, - "cts__timing__drv__max_fanout__pre_repair": 0, - "cts__timing__drv__max_fanout_limit": 0, - "cts__timing__drv__max_fanout_limit__post_repair": 0, - "cts__timing__drv__max_fanout_limit__pre_repair": 0, - "cts__timing__drv__max_slew": 0, - "cts__timing__drv__max_slew__post_repair": 0, - "cts__timing__drv__max_slew__pre_repair": 0, - "cts__timing__drv__max_slew_limit": 0.0790889, - "cts__timing__drv__max_slew_limit__post_repair": 0.07856, - "cts__timing__drv__max_slew_limit__pre_repair": 0.07856, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 66, - "cts__timing__drv__setup_violation_count__pre_repair": 66, - "cts__timing__setup__tns": 0, - "cts__timing__setup__tns__post_repair": -5.33811, - "cts__timing__setup__tns__pre_repair": -5.33811, - "cts__timing__setup__ws": 0.14805, - "cts__timing__setup__ws__post_repair": -0.174781, - "cts__timing__setup__ws__pre_repair": -0.174781, - "cts_fill__cpu__total": 4.35, - "cts_fill__mem__peak": 442728.0, - "cts_fill__runtime__total": "0:05.29", - "design__io__hpwl": 88734510, - "detailedplace__cpu__total": 23.97, - "detailedplace__design__core__area": 710244, - "detailedplace__design__die__area": 745920, - "detailedplace__design__instance__area": 206329, - "detailedplace__design__instance__area__macros": 10379.2, - "detailedplace__design__instance__area__stdcell": 195949, - "detailedplace__design__instance__count": 26990, - "detailedplace__design__instance__count__macros": 2, - "detailedplace__design__instance__count__stdcell": 26988, - "detailedplace__design__instance__displacement__max": 12.923, - "detailedplace__design__instance__displacement__mean": 1.602, - "detailedplace__design__instance__displacement__total": 43238.2, - "detailedplace__design__instance__utilization": 0.290504, - "detailedplace__design__instance__utilization__stdcell": 0.279982, - "detailedplace__design__io": 269, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 487064.0, - "detailedplace__power__internal__total": 0.0924586, - "detailedplace__power__leakage__total": 0.000127208, - "detailedplace__power__switching__total": 0.0763685, - "detailedplace__power__total": 0.168954, - "detailedplace__route__wirelength__estimated": 833528, - "detailedplace__runtime__total": "0:34.17", - "detailedplace__timing__drv__hold_violation_count": 64, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.0337628, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 0, - "detailedplace__timing__drv__max_slew": 0, - "detailedplace__timing__drv__max_slew_limit": 0.0785664, - "detailedplace__timing__drv__setup_violation_count": 64, - "detailedplace__timing__setup__tns": -3.92273, - "detailedplace__timing__setup__ws": -0.109784, - "detailedroute__cpu__total": 1118.78, - "detailedroute__mem__peak": 3891732.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 10508, - "detailedroute__route__drc_errors__iter:2": 2130, - "detailedroute__route__drc_errors__iter:3": 1744, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 23833, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 174769, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 174769, - "detailedroute__route__wirelength": 1094789, - "detailedroute__route__wirelength__iter:1": 1098274, - "detailedroute__route__wirelength__iter:2": 1095734, - "detailedroute__route__wirelength__iter:3": 1094799, - "detailedroute__route__wirelength__iter:4": 1094789, - "detailedroute__runtime__total": "2:52.65", - "finish__clock__skew__hold": 0.235777, - "finish__clock__skew__setup": 0.235777, - "finish__cpu__total": 45.02, - "finish__design__core__area": 710244, - "finish__design__die__area": 745920, - "finish__design__instance__area": 208115, - "finish__design__instance__area__macros": 10379.2, - "finish__design__instance__area__stdcell": 197736, - "finish__design__instance__count": 27307, - "finish__design__instance__count__macros": 2, - "finish__design__instance__count__stdcell": 27305, - "finish__design__instance__utilization": 0.293019, - "finish__design__instance__utilization__stdcell": 0.282535, - "finish__design__io": 269, - "finish__mem__peak": 788644.0, - "finish__power__internal__total": 0.0927515, - "finish__power__leakage__total": 0.000128693, - "finish__power__switching__total": 0.064621, - "finish__power__total": 0.157501, - "finish__runtime__total": "0:50.88", - "finish__timing__drv__hold_violation_count": 44, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.157883, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 0, - "finish__timing__drv__max_slew": 0, - "finish__timing__drv__max_slew_limit": 0.194159, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 0.650171, - "finish__timing__wns_percent_delay": 11.302519, - "finish_merge__cpu__total": 10.04, - "finish_merge__mem__peak": 746332.0, - "finish_merge__runtime__total": "0:10.75", - "floorplan__cpu__total": 11.45, - "floorplan__design__core__area": 710244, - "floorplan__design__die__area": 745920, - "floorplan__design__instance__area": 164623, - "floorplan__design__instance__area__macros": 10379.2, - "floorplan__design__instance__area__stdcell": 154244, - "floorplan__design__instance__count": 22872, - "floorplan__design__instance__count__macros": 2, - "floorplan__design__instance__count__stdcell": 22870, - "floorplan__design__instance__utilization": 0.231784, - "floorplan__design__instance__utilization__stdcell": 0.220391, - "floorplan__design__io": 269, - "floorplan__mem__peak": 410572.0, - "floorplan__power__internal__total": 0.0821972, - "floorplan__power__leakage__total": 0.000106739, - "floorplan__power__switching__total": 0.0305766, - "floorplan__power__total": 0.112881, - "floorplan__runtime__total": "0:12.59", - "floorplan__timing__setup__tns": -1398.91, - "floorplan__timing__setup__ws": -3.21813, - "floorplan_io__cpu__total": 3.77, - "floorplan_io__mem__peak": 343284.0, - "floorplan_io__runtime__total": "0:04.58", - "floorplan_macro__cpu__total": 227.54, - "floorplan_macro__mem__peak": 393392.0, - "floorplan_macro__runtime__total": "1:01.62", - "floorplan_pdn__cpu__total": 4.49, - "floorplan_pdn__mem__peak": 366544.0, - "floorplan_pdn__runtime__total": "0:04.90", - "floorplan_tap__cpu__total": 3.7, - "floorplan_tap__mem__peak": 329244.0, - "floorplan_tap__runtime__total": "0:03.99", - "floorplan_tdms__cpu__total": 3.8, - "floorplan_tdms__mem__peak": 343196.0, - "floorplan_tdms__runtime__total": "0:04.46", - "globalplace__cpu__total": 107.94, - "globalplace__design__core__area": 710244, - "globalplace__design__die__area": 745920, - "globalplace__design__instance__area": 168149, - "globalplace__design__instance__area__macros": 10379.2, - "globalplace__design__instance__area__stdcell": 157770, - "globalplace__design__instance__count": 26545, - "globalplace__design__instance__count__macros": 2, - "globalplace__design__instance__count__stdcell": 26543, - "globalplace__design__instance__utilization": 0.236748, - "globalplace__design__instance__utilization__stdcell": 0.225429, - "globalplace__design__io": 269, - "globalplace__mem__peak": 695432.0, - "globalplace__power__internal__total": 0.0906838, - "globalplace__power__leakage__total": 0.000106739, - "globalplace__power__switching__total": 0.0657249, - "globalplace__power__total": 0.156515, - "globalplace__runtime__total": "2:08.45", - "globalplace__timing__setup__tns": -7246.08, - "globalplace__timing__setup__ws": -9.32741, - "globalplace_io__cpu__total": 3.77, - "globalplace_io__mem__peak": 350692.0, - "globalplace_io__runtime__total": "0:04.10", - "globalplace_skip_io__cpu__total": 11.61, - "globalplace_skip_io__mem__peak": 377436.0, - "globalplace_skip_io__runtime__total": "0:12.20", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.304604, - "globalroute__clock__skew__setup": 0.304604, - "globalroute__cpu__total": 26.16, - "globalroute__design__core__area": 710244, - "globalroute__design__die__area": 745920, - "globalroute__design__instance__area": 208115, - "globalroute__design__instance__area__macros": 10379.2, - "globalroute__design__instance__area__stdcell": 197736, - "globalroute__design__instance__count": 27307, - "globalroute__design__instance__count__macros": 2, - "globalroute__design__instance__count__stdcell": 27305, - "globalroute__design__instance__utilization": 0.293019, - "globalroute__design__instance__utilization__stdcell": 0.282535, - "globalroute__design__io": 269, - "globalroute__mem__peak": 819984.0, - "globalroute__power__internal__total": 0.0930128, - "globalroute__power__leakage__total": 0.000128693, - "globalroute__power__switching__total": 0.0861238, - "globalroute__power__total": 0.179265, - "globalroute__runtime__total": "0:40.05", - "globalroute__timing__clock__slack": -0.027, - "globalroute__timing__drv__hold_violation_count": 44, - "globalroute__timing__drv__max_cap": 2, - "globalroute__timing__drv__max_cap_limit": -0.0394115, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 0, - "globalroute__timing__drv__max_slew": 0, - "globalroute__timing__drv__max_slew_limit": 0.0119528, - "globalroute__timing__drv__setup_violation_count": 10, - "globalroute__timing__setup__tns": -0.163829, - "globalroute__timing__setup__ws": -0.0267653, - "placeopt__cpu__total": 26.37, - "placeopt__design__core__area": 710244, - "placeopt__design__core__area__pre_opt": 710244, - "placeopt__design__die__area": 745920, - "placeopt__design__die__area__pre_opt": 745920, - "placeopt__design__instance__area": 206329, - "placeopt__design__instance__area__macros": 10379.2, - "placeopt__design__instance__area__macros__pre_opt": 10379.2, - "placeopt__design__instance__area__pre_opt": 168149, - "placeopt__design__instance__area__stdcell": 195949, - "placeopt__design__instance__area__stdcell__pre_opt": 157770, - "placeopt__design__instance__count": 26990, - "placeopt__design__instance__count__macros": 2, - "placeopt__design__instance__count__macros__pre_opt": 2, - "placeopt__design__instance__count__pre_opt": 26545, - "placeopt__design__instance__count__stdcell": 26988, - "placeopt__design__instance__count__stdcell__pre_opt": 26543, - "placeopt__design__instance__utilization": 0.290504, - "placeopt__design__instance__utilization__pre_opt": 0.236748, - "placeopt__design__instance__utilization__stdcell": 0.279982, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.225429, - "placeopt__design__io": 269, - "placeopt__design__io__pre_opt": 269, - "placeopt__mem__peak": 464600.0, - "placeopt__power__internal__total": 0.0913703, - "placeopt__power__internal__total__pre_opt": 0.0906838, - "placeopt__power__leakage__total": 0.000127208, - "placeopt__power__leakage__total__pre_opt": 0.000106739, - "placeopt__power__switching__total": 0.0724769, - "placeopt__power__switching__total__pre_opt": 0.0657249, - "placeopt__power__total": 0.163974, - "placeopt__power__total__pre_opt": 0.156515, - "placeopt__runtime__total": "0:37.81", - "placeopt__timing__drv__hold_violation_count": 64, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.0223315, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 0, - "placeopt__timing__drv__max_slew": 0, - "placeopt__timing__drv__max_slew_limit": 0.069573, - "placeopt__timing__drv__setup_violation_count": 41, - "placeopt__timing__setup__tns": -1.81857, - "placeopt__timing__setup__tns__pre_opt": -7246.08, - "placeopt__timing__setup__ws": -0.0661378, - "placeopt__timing__setup__ws__pre_opt": -9.32741, - "run__flow__design": "tinyRocket", - "run__flow__generate_date": "2023-07-27 07:27", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-9523-g486364f18", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "0e8ccac8a84d32bc40211e4193212d8c25ba7ace", - "run__flow__scripts_commit": "ec589188ee778f884d4a18de3c3ba924914eac86", - "run__flow__uuid": "c4f346c1-25be-4045-a0ec-882a4a88fdd2", - "run__flow__variant": "base", - "synth__cpu__total": 130.19, - "synth__design__instance__area__stdcell": 175980.147, - "synth__design__instance__count__stdcell": 25263.0, - "synth__mem__peak": 276964.0, - "synth__runtime__total": "2:16.42", - "total_time": "0:12:59.320000" -} \ No newline at end of file diff --git a/flow/designs/tsmc65lp/vanilla5/config.mk b/flow/designs/tsmc65lp/vanilla5/config.mk deleted file mode 100644 index 80122d2091..0000000000 --- a/flow/designs/tsmc65lp/vanilla5/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -export DESIGN_NICKNAME = vanilla5 -export DESIGN_NAME = bsg_manycore_tile -export PLATFORM = tsmc65lp - -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/bsg_manycore_tile.sv2v.v -export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc - -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg10_w32_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_2rf_lg5_w32_all.lef \ - $(PLATFORM_DIR)/lef/tsmc65lp_1rf_lg10_w32_byte.lef -export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg10_w32_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_2rf_lg5_w32_all_ss_1p08v_1p08v_125c.lib \ - $(PLATFORM_DIR)/lib/tsmc65lp_1rf_lg10_w32_byte_ss_1p08v_1p08v_125c.lib -export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg5_w32_all.gds2 \ - $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_byte.gds2 - -export SYNTH_HIERARCHICAL = 1 - - -# These values must be multiples of placement site -export DIE_AREA = 0 0 1100 400.8 -export CORE_AREA = 10 12 1090 391.2 diff --git a/flow/designs/tsmc65lp/vanilla5/constraint.sdc b/flow/designs/tsmc65lp/vanilla5/constraint.sdc deleted file mode 100644 index 8757e815b5..0000000000 --- a/flow/designs/tsmc65lp/vanilla5/constraint.sdc +++ /dev/null @@ -1,1459 +0,0 @@ - -set_max_fanout 12 [current_design] -set_max_transition 0.1 [current_design] -set_load -pin_load 3 [get_ports {link_out[355]}] -set_load -pin_load 3 [get_ports {link_out[354]}] -set_load -pin_load 3 [get_ports {link_out[353]}] -set_load -pin_load 3 [get_ports {link_out[352]}] -set_load -pin_load 3 [get_ports {link_out[351]}] -set_load -pin_load 3 [get_ports {link_out[350]}] -set_load -pin_load 3 [get_ports {link_out[349]}] -set_load -pin_load 3 [get_ports {link_out[348]}] -set_load -pin_load 3 [get_ports {link_out[347]}] -set_load -pin_load 3 [get_ports {link_out[346]}] -set_load -pin_load 3 [get_ports {link_out[345]}] -set_load -pin_load 3 [get_ports {link_out[344]}] -set_load -pin_load 3 [get_ports {link_out[343]}] -set_load -pin_load 3 [get_ports {link_out[342]}] -set_load -pin_load 3 [get_ports {link_out[341]}] -set_load -pin_load 3 [get_ports {link_out[340]}] -set_load -pin_load 3 [get_ports {link_out[339]}] -set_load -pin_load 3 [get_ports {link_out[338]}] -set_load -pin_load 3 [get_ports {link_out[337]}] -set_load -pin_load 3 [get_ports {link_out[336]}] -set_load -pin_load 3 [get_ports {link_out[335]}] -set_load -pin_load 3 [get_ports {link_out[334]}] -set_load -pin_load 3 [get_ports {link_out[333]}] -set_load -pin_load 3 [get_ports {link_out[332]}] -set_load -pin_load 3 [get_ports {link_out[331]}] -set_load -pin_load 3 [get_ports {link_out[330]}] -set_load -pin_load 3 [get_ports {link_out[329]}] -set_load -pin_load 3 [get_ports {link_out[328]}] -set_load -pin_load 3 [get_ports {link_out[327]}] -set_load -pin_load 3 [get_ports {link_out[326]}] -set_load -pin_load 3 [get_ports {link_out[325]}] -set_load -pin_load 3 [get_ports {link_out[324]}] -set_load -pin_load 3 [get_ports {link_out[323]}] -set_load -pin_load 3 [get_ports {link_out[322]}] -set_load -pin_load 3 [get_ports {link_out[321]}] -set_load -pin_load 3 [get_ports {link_out[320]}] -set_load -pin_load 3 [get_ports {link_out[319]}] -set_load -pin_load 3 [get_ports {link_out[318]}] -set_load -pin_load 3 [get_ports {link_out[317]}] -set_load -pin_load 3 [get_ports {link_out[316]}] -set_load -pin_load 3 [get_ports {link_out[315]}] -set_load -pin_load 3 [get_ports {link_out[314]}] -set_load -pin_load 3 [get_ports {link_out[313]}] -set_load -pin_load 3 [get_ports {link_out[312]}] -set_load -pin_load 3 [get_ports {link_out[311]}] -set_load -pin_load 3 [get_ports {link_out[310]}] -set_load -pin_load 3 [get_ports {link_out[309]}] -set_load -pin_load 3 [get_ports {link_out[308]}] -set_load -pin_load 3 [get_ports {link_out[307]}] -set_load -pin_load 3 [get_ports {link_out[306]}] -set_load -pin_load 3 [get_ports {link_out[305]}] -set_load -pin_load 3 [get_ports {link_out[304]}] -set_load -pin_load 3 [get_ports {link_out[303]}] -set_load -pin_load 3 [get_ports {link_out[302]}] -set_load -pin_load 3 [get_ports {link_out[301]}] -set_load -pin_load 3 [get_ports {link_out[300]}] -set_load -pin_load 3 [get_ports {link_out[299]}] -set_load -pin_load 3 [get_ports {link_out[298]}] -set_load -pin_load 3 [get_ports {link_out[297]}] -set_load -pin_load 3 [get_ports {link_out[296]}] -set_load -pin_load 3 [get_ports {link_out[295]}] -set_load -pin_load 3 [get_ports {link_out[294]}] -set_load -pin_load 3 [get_ports {link_out[293]}] -set_load -pin_load 3 [get_ports {link_out[292]}] -set_load -pin_load 3 [get_ports {link_out[291]}] -set_load -pin_load 3 [get_ports {link_out[290]}] -set_load -pin_load 3 [get_ports {link_out[289]}] -set_load -pin_load 3 [get_ports {link_out[288]}] -set_load -pin_load 3 [get_ports {link_out[287]}] -set_load -pin_load 3 [get_ports {link_out[286]}] -set_load -pin_load 3 [get_ports {link_out[285]}] -set_load -pin_load 3 [get_ports {link_out[284]}] -set_load -pin_load 3 [get_ports {link_out[283]}] -set_load -pin_load 3 [get_ports {link_out[282]}] -set_load -pin_load 3 [get_ports {link_out[281]}] -set_load -pin_load 3 [get_ports {link_out[280]}] -set_load -pin_load 3 [get_ports {link_out[279]}] -set_load -pin_load 3 [get_ports {link_out[278]}] -set_load -pin_load 3 [get_ports {link_out[277]}] -set_load -pin_load 3 [get_ports {link_out[276]}] -set_load -pin_load 3 [get_ports {link_out[275]}] -set_load -pin_load 3 [get_ports {link_out[274]}] -set_load -pin_load 3 [get_ports {link_out[273]}] -set_load -pin_load 3 [get_ports {link_out[272]}] -set_load -pin_load 3 [get_ports {link_out[271]}] -set_load -pin_load 3 [get_ports {link_out[270]}] -set_load -pin_load 3 [get_ports {link_out[269]}] -set_load -pin_load 3 [get_ports {link_out[268]}] -set_load -pin_load 3 [get_ports {link_out[267]}] -set_load -pin_load 3 [get_ports {link_out[266]}] -set_load -pin_load 3 [get_ports {link_out[265]}] -set_load -pin_load 3 [get_ports {link_out[264]}] -set_load -pin_load 3 [get_ports {link_out[263]}] -set_load -pin_load 3 [get_ports {link_out[262]}] -set_load -pin_load 3 [get_ports {link_out[261]}] -set_load -pin_load 3 [get_ports {link_out[260]}] -set_load -pin_load 3 [get_ports {link_out[259]}] -set_load -pin_load 3 [get_ports {link_out[258]}] -set_load -pin_load 3 [get_ports {link_out[257]}] -set_load -pin_load 3 [get_ports {link_out[256]}] -set_load -pin_load 3 [get_ports {link_out[255]}] -set_load -pin_load 3 [get_ports {link_out[254]}] -set_load -pin_load 3 [get_ports {link_out[253]}] -set_load -pin_load 3 [get_ports {link_out[252]}] -set_load -pin_load 3 [get_ports {link_out[251]}] -set_load -pin_load 3 [get_ports {link_out[250]}] -set_load -pin_load 3 [get_ports {link_out[249]}] -set_load -pin_load 3 [get_ports {link_out[248]}] -set_load -pin_load 3 [get_ports {link_out[247]}] -set_load -pin_load 3 [get_ports {link_out[246]}] -set_load -pin_load 3 [get_ports {link_out[245]}] -set_load -pin_load 3 [get_ports {link_out[244]}] -set_load -pin_load 3 [get_ports {link_out[243]}] -set_load -pin_load 3 [get_ports {link_out[242]}] -set_load -pin_load 3 [get_ports {link_out[241]}] -set_load -pin_load 3 [get_ports {link_out[240]}] -set_load -pin_load 3 [get_ports {link_out[239]}] -set_load -pin_load 3 [get_ports {link_out[238]}] -set_load -pin_load 3 [get_ports {link_out[237]}] -set_load -pin_load 3 [get_ports {link_out[236]}] -set_load -pin_load 3 [get_ports {link_out[235]}] -set_load -pin_load 3 [get_ports {link_out[234]}] -set_load -pin_load 3 [get_ports {link_out[233]}] -set_load -pin_load 3 [get_ports {link_out[232]}] -set_load -pin_load 3 [get_ports {link_out[231]}] -set_load -pin_load 3 [get_ports {link_out[230]}] -set_load -pin_load 3 [get_ports {link_out[229]}] -set_load -pin_load 3 [get_ports {link_out[228]}] -set_load -pin_load 3 [get_ports {link_out[227]}] -set_load -pin_load 3 [get_ports {link_out[226]}] -set_load -pin_load 3 [get_ports {link_out[225]}] -set_load -pin_load 3 [get_ports {link_out[224]}] -set_load -pin_load 3 [get_ports {link_out[223]}] -set_load -pin_load 3 [get_ports {link_out[222]}] -set_load -pin_load 3 [get_ports {link_out[221]}] -set_load -pin_load 3 [get_ports {link_out[220]}] -set_load -pin_load 3 [get_ports {link_out[219]}] -set_load -pin_load 3 [get_ports {link_out[218]}] -set_load -pin_load 3 [get_ports {link_out[217]}] -set_load -pin_load 3 [get_ports {link_out[216]}] -set_load -pin_load 3 [get_ports {link_out[215]}] -set_load -pin_load 3 [get_ports {link_out[214]}] -set_load -pin_load 3 [get_ports {link_out[213]}] -set_load -pin_load 3 [get_ports {link_out[212]}] -set_load -pin_load 3 [get_ports {link_out[211]}] -set_load -pin_load 3 [get_ports {link_out[210]}] -set_load -pin_load 3 [get_ports {link_out[209]}] -set_load -pin_load 3 [get_ports {link_out[208]}] -set_load -pin_load 3 [get_ports {link_out[207]}] -set_load -pin_load 3 [get_ports {link_out[206]}] -set_load -pin_load 3 [get_ports {link_out[205]}] -set_load -pin_load 3 [get_ports {link_out[204]}] -set_load -pin_load 3 [get_ports {link_out[203]}] -set_load -pin_load 3 [get_ports {link_out[202]}] -set_load -pin_load 3 [get_ports {link_out[201]}] -set_load -pin_load 3 [get_ports {link_out[200]}] -set_load -pin_load 3 [get_ports {link_out[199]}] -set_load -pin_load 3 [get_ports {link_out[198]}] -set_load -pin_load 3 [get_ports {link_out[197]}] -set_load -pin_load 3 [get_ports {link_out[196]}] -set_load -pin_load 3 [get_ports {link_out[195]}] -set_load -pin_load 3 [get_ports {link_out[194]}] -set_load -pin_load 3 [get_ports {link_out[193]}] -set_load -pin_load 3 [get_ports {link_out[192]}] -set_load -pin_load 3 [get_ports {link_out[191]}] -set_load -pin_load 3 [get_ports {link_out[190]}] -set_load -pin_load 3 [get_ports {link_out[189]}] -set_load -pin_load 3 [get_ports {link_out[188]}] -set_load -pin_load 3 [get_ports {link_out[187]}] -set_load -pin_load 3 [get_ports {link_out[186]}] -set_load -pin_load 3 [get_ports {link_out[185]}] -set_load -pin_load 3 [get_ports {link_out[184]}] -set_load -pin_load 3 [get_ports {link_out[183]}] -set_load -pin_load 3 [get_ports {link_out[182]}] -set_load -pin_load 3 [get_ports {link_out[181]}] -set_load -pin_load 3 [get_ports {link_out[180]}] -set_load -pin_load 3 [get_ports {link_out[179]}] -set_load -pin_load 3 [get_ports {link_out[178]}] -set_load -pin_load 3 [get_ports {link_out[177]}] -set_load -pin_load 3 [get_ports {link_out[176]}] -set_load -pin_load 3 [get_ports {link_out[175]}] -set_load -pin_load 3 [get_ports {link_out[174]}] -set_load -pin_load 3 [get_ports {link_out[173]}] -set_load -pin_load 3 [get_ports {link_out[172]}] -set_load -pin_load 3 [get_ports {link_out[171]}] -set_load -pin_load 3 [get_ports {link_out[170]}] -set_load -pin_load 3 [get_ports {link_out[169]}] -set_load -pin_load 3 [get_ports {link_out[168]}] -set_load -pin_load 3 [get_ports {link_out[167]}] -set_load -pin_load 3 [get_ports {link_out[166]}] -set_load -pin_load 3 [get_ports {link_out[165]}] -set_load -pin_load 3 [get_ports {link_out[164]}] -set_load -pin_load 3 [get_ports {link_out[163]}] -set_load -pin_load 3 [get_ports {link_out[162]}] -set_load -pin_load 3 [get_ports {link_out[161]}] -set_load -pin_load 3 [get_ports {link_out[160]}] -set_load -pin_load 3 [get_ports {link_out[159]}] -set_load -pin_load 3 [get_ports {link_out[158]}] -set_load -pin_load 3 [get_ports {link_out[157]}] -set_load -pin_load 3 [get_ports {link_out[156]}] -set_load -pin_load 3 [get_ports {link_out[155]}] -set_load -pin_load 3 [get_ports {link_out[154]}] -set_load -pin_load 3 [get_ports {link_out[153]}] -set_load -pin_load 3 [get_ports {link_out[152]}] -set_load -pin_load 3 [get_ports {link_out[151]}] -set_load -pin_load 3 [get_ports {link_out[150]}] -set_load -pin_load 3 [get_ports {link_out[149]}] -set_load -pin_load 3 [get_ports {link_out[148]}] -set_load -pin_load 3 [get_ports {link_out[147]}] -set_load -pin_load 3 [get_ports {link_out[146]}] -set_load -pin_load 3 [get_ports {link_out[145]}] -set_load -pin_load 3 [get_ports {link_out[144]}] -set_load -pin_load 3 [get_ports {link_out[143]}] -set_load -pin_load 3 [get_ports {link_out[142]}] -set_load -pin_load 3 [get_ports {link_out[141]}] -set_load -pin_load 3 [get_ports {link_out[140]}] -set_load -pin_load 3 [get_ports {link_out[139]}] -set_load -pin_load 3 [get_ports {link_out[138]}] -set_load -pin_load 3 [get_ports {link_out[137]}] -set_load -pin_load 3 [get_ports {link_out[136]}] -set_load -pin_load 3 [get_ports {link_out[135]}] -set_load -pin_load 3 [get_ports {link_out[134]}] -set_load -pin_load 3 [get_ports {link_out[133]}] -set_load -pin_load 3 [get_ports {link_out[132]}] -set_load -pin_load 3 [get_ports {link_out[131]}] -set_load -pin_load 3 [get_ports {link_out[130]}] -set_load -pin_load 3 [get_ports {link_out[129]}] -set_load -pin_load 3 [get_ports {link_out[128]}] -set_load -pin_load 3 [get_ports {link_out[127]}] -set_load -pin_load 3 [get_ports {link_out[126]}] -set_load -pin_load 3 [get_ports {link_out[125]}] -set_load -pin_load 3 [get_ports {link_out[124]}] -set_load -pin_load 3 [get_ports {link_out[123]}] -set_load -pin_load 3 [get_ports {link_out[122]}] -set_load -pin_load 3 [get_ports {link_out[121]}] -set_load -pin_load 3 [get_ports {link_out[120]}] -set_load -pin_load 3 [get_ports {link_out[119]}] -set_load -pin_load 3 [get_ports {link_out[118]}] -set_load -pin_load 3 [get_ports {link_out[117]}] -set_load -pin_load 3 [get_ports {link_out[116]}] -set_load -pin_load 3 [get_ports {link_out[115]}] -set_load -pin_load 3 [get_ports {link_out[114]}] -set_load -pin_load 3 [get_ports {link_out[113]}] -set_load -pin_load 3 [get_ports {link_out[112]}] -set_load -pin_load 3 [get_ports {link_out[111]}] -set_load -pin_load 3 [get_ports {link_out[110]}] -set_load -pin_load 3 [get_ports {link_out[109]}] -set_load -pin_load 3 [get_ports {link_out[108]}] -set_load -pin_load 3 [get_ports {link_out[107]}] -set_load -pin_load 3 [get_ports {link_out[106]}] -set_load -pin_load 3 [get_ports {link_out[105]}] -set_load -pin_load 3 [get_ports {link_out[104]}] -set_load -pin_load 3 [get_ports {link_out[103]}] -set_load -pin_load 3 [get_ports {link_out[102]}] -set_load -pin_load 3 [get_ports {link_out[101]}] -set_load -pin_load 3 [get_ports {link_out[100]}] -set_load -pin_load 3 [get_ports {link_out[99]}] -set_load -pin_load 3 [get_ports {link_out[98]}] -set_load -pin_load 3 [get_ports {link_out[97]}] -set_load -pin_load 3 [get_ports {link_out[96]}] -set_load -pin_load 3 [get_ports {link_out[95]}] -set_load -pin_load 3 [get_ports {link_out[94]}] -set_load -pin_load 3 [get_ports {link_out[93]}] -set_load -pin_load 3 [get_ports {link_out[92]}] -set_load -pin_load 3 [get_ports {link_out[91]}] -set_load -pin_load 3 [get_ports {link_out[90]}] -set_load -pin_load 3 [get_ports {link_out[89]}] -set_load -pin_load 3 [get_ports {link_out[88]}] -set_load -pin_load 3 [get_ports {link_out[87]}] -set_load -pin_load 3 [get_ports {link_out[86]}] -set_load -pin_load 3 [get_ports {link_out[85]}] -set_load -pin_load 3 [get_ports {link_out[84]}] -set_load -pin_load 3 [get_ports {link_out[83]}] -set_load -pin_load 3 [get_ports {link_out[82]}] -set_load -pin_load 3 [get_ports {link_out[81]}] -set_load -pin_load 3 [get_ports {link_out[80]}] -set_load -pin_load 3 [get_ports {link_out[79]}] -set_load -pin_load 3 [get_ports {link_out[78]}] -set_load -pin_load 3 [get_ports {link_out[77]}] -set_load -pin_load 3 [get_ports {link_out[76]}] -set_load -pin_load 3 [get_ports {link_out[75]}] -set_load -pin_load 3 [get_ports {link_out[74]}] -set_load -pin_load 3 [get_ports {link_out[73]}] -set_load -pin_load 3 [get_ports {link_out[72]}] -set_load -pin_load 3 [get_ports {link_out[71]}] -set_load -pin_load 3 [get_ports {link_out[70]}] -set_load -pin_load 3 [get_ports {link_out[69]}] -set_load -pin_load 3 [get_ports {link_out[68]}] -set_load -pin_load 3 [get_ports {link_out[67]}] -set_load -pin_load 3 [get_ports {link_out[66]}] -set_load -pin_load 3 [get_ports {link_out[65]}] -set_load -pin_load 3 [get_ports {link_out[64]}] -set_load -pin_load 3 [get_ports {link_out[63]}] -set_load -pin_load 3 [get_ports {link_out[62]}] -set_load -pin_load 3 [get_ports {link_out[61]}] -set_load -pin_load 3 [get_ports {link_out[60]}] -set_load -pin_load 3 [get_ports {link_out[59]}] -set_load -pin_load 3 [get_ports {link_out[58]}] -set_load -pin_load 3 [get_ports {link_out[57]}] -set_load -pin_load 3 [get_ports {link_out[56]}] -set_load -pin_load 3 [get_ports {link_out[55]}] -set_load -pin_load 3 [get_ports {link_out[54]}] -set_load -pin_load 3 [get_ports {link_out[53]}] -set_load -pin_load 3 [get_ports {link_out[52]}] -set_load -pin_load 3 [get_ports {link_out[51]}] -set_load -pin_load 3 [get_ports {link_out[50]}] -set_load -pin_load 3 [get_ports {link_out[49]}] -set_load -pin_load 3 [get_ports {link_out[48]}] -set_load -pin_load 3 [get_ports {link_out[47]}] -set_load -pin_load 3 [get_ports {link_out[46]}] -set_load -pin_load 3 [get_ports {link_out[45]}] -set_load -pin_load 3 [get_ports {link_out[44]}] -set_load -pin_load 3 [get_ports {link_out[43]}] -set_load -pin_load 3 [get_ports {link_out[42]}] -set_load -pin_load 3 [get_ports {link_out[41]}] -set_load -pin_load 3 [get_ports {link_out[40]}] -set_load -pin_load 3 [get_ports {link_out[39]}] -set_load -pin_load 3 [get_ports {link_out[38]}] -set_load -pin_load 3 [get_ports {link_out[37]}] -set_load -pin_load 3 [get_ports {link_out[36]}] -set_load -pin_load 3 [get_ports {link_out[35]}] -set_load -pin_load 3 [get_ports {link_out[34]}] -set_load -pin_load 3 [get_ports {link_out[33]}] -set_load -pin_load 3 [get_ports {link_out[32]}] -set_load -pin_load 3 [get_ports {link_out[31]}] -set_load -pin_load 3 [get_ports {link_out[30]}] -set_load -pin_load 3 [get_ports {link_out[29]}] -set_load -pin_load 3 [get_ports {link_out[28]}] -set_load -pin_load 3 [get_ports {link_out[27]}] -set_load -pin_load 3 [get_ports {link_out[26]}] -set_load -pin_load 3 [get_ports {link_out[25]}] -set_load -pin_load 3 [get_ports {link_out[24]}] -set_load -pin_load 3 [get_ports {link_out[23]}] -set_load -pin_load 3 [get_ports {link_out[22]}] -set_load -pin_load 3 [get_ports {link_out[21]}] -set_load -pin_load 3 [get_ports {link_out[20]}] -set_load -pin_load 3 [get_ports {link_out[19]}] -set_load -pin_load 3 [get_ports {link_out[18]}] -set_load -pin_load 3 [get_ports {link_out[17]}] -set_load -pin_load 3 [get_ports {link_out[16]}] -set_load -pin_load 3 [get_ports {link_out[15]}] -set_load -pin_load 3 [get_ports {link_out[14]}] -set_load -pin_load 3 [get_ports {link_out[13]}] -set_load -pin_load 3 [get_ports {link_out[12]}] -set_load -pin_load 3 [get_ports {link_out[11]}] -set_load -pin_load 3 [get_ports {link_out[10]}] -set_load -pin_load 3 [get_ports {link_out[9]}] -set_load -pin_load 3 [get_ports {link_out[8]}] -set_load -pin_load 3 [get_ports {link_out[7]}] -set_load -pin_load 3 [get_ports {link_out[6]}] -set_load -pin_load 3 [get_ports {link_out[5]}] -set_load -pin_load 3 [get_ports {link_out[4]}] -set_load -pin_load 3 [get_ports {link_out[3]}] -set_load -pin_load 3 [get_ports {link_out[2]}] -set_load -pin_load 3 [get_ports {link_out[1]}] -set_load -pin_load 3 [get_ports {link_out[0]}] -set_max_transition 0.069 [get_ports {link_out[355]}] -set_max_transition 0.069 [get_ports {link_out[354]}] -set_max_transition 0.069 [get_ports {link_out[353]}] -set_max_transition 0.069 [get_ports {link_out[352]}] -set_max_transition 0.069 [get_ports {link_out[351]}] -set_max_transition 0.069 [get_ports {link_out[350]}] -set_max_transition 0.069 [get_ports {link_out[349]}] -set_max_transition 0.069 [get_ports {link_out[348]}] -set_max_transition 0.069 [get_ports {link_out[347]}] -set_max_transition 0.069 [get_ports {link_out[346]}] -set_max_transition 0.069 [get_ports {link_out[345]}] -set_max_transition 0.069 [get_ports {link_out[344]}] -set_max_transition 0.069 [get_ports {link_out[343]}] -set_max_transition 0.069 [get_ports {link_out[342]}] -set_max_transition 0.069 [get_ports {link_out[341]}] -set_max_transition 0.069 [get_ports {link_out[340]}] -set_max_transition 0.069 [get_ports {link_out[339]}] -set_max_transition 0.069 [get_ports {link_out[338]}] -set_max_transition 0.069 [get_ports {link_out[337]}] -set_max_transition 0.069 [get_ports {link_out[336]}] -set_max_transition 0.069 [get_ports {link_out[335]}] -set_max_transition 0.069 [get_ports {link_out[334]}] -set_max_transition 0.069 [get_ports {link_out[333]}] -set_max_transition 0.069 [get_ports {link_out[332]}] -set_max_transition 0.069 [get_ports {link_out[331]}] -set_max_transition 0.069 [get_ports {link_out[330]}] -set_max_transition 0.069 [get_ports {link_out[329]}] -set_max_transition 0.069 [get_ports {link_out[328]}] -set_max_transition 0.069 [get_ports {link_out[327]}] -set_max_transition 0.069 [get_ports {link_out[326]}] -set_max_transition 0.069 [get_ports {link_out[325]}] -set_max_transition 0.069 [get_ports {link_out[324]}] -set_max_transition 0.069 [get_ports {link_out[323]}] -set_max_transition 0.069 [get_ports {link_out[322]}] -set_max_transition 0.069 [get_ports {link_out[321]}] -set_max_transition 0.069 [get_ports {link_out[320]}] -set_max_transition 0.069 [get_ports {link_out[319]}] -set_max_transition 0.069 [get_ports {link_out[318]}] -set_max_transition 0.069 [get_ports {link_out[317]}] -set_max_transition 0.069 [get_ports {link_out[316]}] -set_max_transition 0.069 [get_ports {link_out[315]}] -set_max_transition 0.069 [get_ports {link_out[314]}] -set_max_transition 0.069 [get_ports {link_out[313]}] -set_max_transition 0.069 [get_ports {link_out[312]}] -set_max_transition 0.069 [get_ports {link_out[311]}] -set_max_transition 0.069 [get_ports {link_out[310]}] -set_max_transition 0.069 [get_ports {link_out[309]}] -set_max_transition 0.069 [get_ports {link_out[308]}] -set_max_transition 0.069 [get_ports {link_out[307]}] -set_max_transition 0.069 [get_ports {link_out[306]}] -set_max_transition 0.069 [get_ports {link_out[305]}] -set_max_transition 0.069 [get_ports {link_out[304]}] -set_max_transition 0.069 [get_ports {link_out[303]}] -set_max_transition 0.069 [get_ports {link_out[302]}] -set_max_transition 0.069 [get_ports {link_out[301]}] -set_max_transition 0.069 [get_ports {link_out[300]}] -set_max_transition 0.069 [get_ports {link_out[299]}] -set_max_transition 0.069 [get_ports {link_out[298]}] -set_max_transition 0.069 [get_ports {link_out[297]}] -set_max_transition 0.069 [get_ports {link_out[296]}] -set_max_transition 0.069 [get_ports {link_out[295]}] -set_max_transition 0.069 [get_ports {link_out[294]}] -set_max_transition 0.069 [get_ports {link_out[293]}] -set_max_transition 0.069 [get_ports {link_out[292]}] -set_max_transition 0.069 [get_ports {link_out[291]}] -set_max_transition 0.069 [get_ports {link_out[290]}] -set_max_transition 0.069 [get_ports {link_out[289]}] -set_max_transition 0.069 [get_ports {link_out[288]}] -set_max_transition 0.069 [get_ports {link_out[287]}] -set_max_transition 0.069 [get_ports {link_out[286]}] -set_max_transition 0.069 [get_ports {link_out[285]}] -set_max_transition 0.069 [get_ports {link_out[284]}] -set_max_transition 0.069 [get_ports {link_out[283]}] -set_max_transition 0.069 [get_ports {link_out[282]}] -set_max_transition 0.069 [get_ports {link_out[281]}] -set_max_transition 0.069 [get_ports {link_out[280]}] -set_max_transition 0.069 [get_ports {link_out[279]}] -set_max_transition 0.069 [get_ports {link_out[278]}] -set_max_transition 0.069 [get_ports {link_out[277]}] -set_max_transition 0.069 [get_ports {link_out[276]}] -set_max_transition 0.069 [get_ports {link_out[275]}] -set_max_transition 0.069 [get_ports {link_out[274]}] -set_max_transition 0.069 [get_ports {link_out[273]}] -set_max_transition 0.069 [get_ports {link_out[272]}] -set_max_transition 0.069 [get_ports {link_out[271]}] -set_max_transition 0.069 [get_ports {link_out[270]}] -set_max_transition 0.069 [get_ports {link_out[269]}] -set_max_transition 0.069 [get_ports {link_out[268]}] -set_max_transition 0.069 [get_ports {link_out[267]}] -set_max_transition 0.069 [get_ports {link_out[266]}] -set_max_transition 0.069 [get_ports {link_out[265]}] -set_max_transition 0.069 [get_ports {link_out[264]}] -set_max_transition 0.069 [get_ports {link_out[263]}] -set_max_transition 0.069 [get_ports {link_out[262]}] -set_max_transition 0.069 [get_ports {link_out[261]}] -set_max_transition 0.069 [get_ports {link_out[260]}] -set_max_transition 0.069 [get_ports {link_out[259]}] -set_max_transition 0.069 [get_ports {link_out[258]}] -set_max_transition 0.069 [get_ports {link_out[257]}] -set_max_transition 0.069 [get_ports {link_out[256]}] -set_max_transition 0.069 [get_ports {link_out[255]}] -set_max_transition 0.069 [get_ports {link_out[254]}] -set_max_transition 0.069 [get_ports {link_out[253]}] -set_max_transition 0.069 [get_ports {link_out[252]}] -set_max_transition 0.069 [get_ports {link_out[251]}] -set_max_transition 0.069 [get_ports {link_out[250]}] -set_max_transition 0.069 [get_ports {link_out[249]}] -set_max_transition 0.069 [get_ports {link_out[248]}] -set_max_transition 0.069 [get_ports {link_out[247]}] -set_max_transition 0.069 [get_ports {link_out[246]}] -set_max_transition 0.069 [get_ports {link_out[245]}] -set_max_transition 0.069 [get_ports {link_out[244]}] -set_max_transition 0.069 [get_ports {link_out[243]}] -set_max_transition 0.069 [get_ports {link_out[242]}] -set_max_transition 0.069 [get_ports {link_out[241]}] -set_max_transition 0.069 [get_ports {link_out[240]}] -set_max_transition 0.069 [get_ports {link_out[239]}] -set_max_transition 0.069 [get_ports {link_out[238]}] -set_max_transition 0.069 [get_ports {link_out[237]}] -set_max_transition 0.069 [get_ports {link_out[236]}] -set_max_transition 0.069 [get_ports {link_out[235]}] -set_max_transition 0.069 [get_ports {link_out[234]}] -set_max_transition 0.069 [get_ports {link_out[233]}] -set_max_transition 0.069 [get_ports {link_out[232]}] -set_max_transition 0.069 [get_ports {link_out[231]}] -set_max_transition 0.069 [get_ports {link_out[230]}] -set_max_transition 0.069 [get_ports {link_out[229]}] -set_max_transition 0.069 [get_ports {link_out[228]}] -set_max_transition 0.069 [get_ports {link_out[227]}] -set_max_transition 0.069 [get_ports {link_out[226]}] -set_max_transition 0.069 [get_ports {link_out[225]}] -set_max_transition 0.069 [get_ports {link_out[224]}] -set_max_transition 0.069 [get_ports {link_out[223]}] -set_max_transition 0.069 [get_ports {link_out[222]}] -set_max_transition 0.069 [get_ports {link_out[221]}] -set_max_transition 0.069 [get_ports {link_out[220]}] -set_max_transition 0.069 [get_ports {link_out[219]}] -set_max_transition 0.069 [get_ports {link_out[218]}] -set_max_transition 0.069 [get_ports {link_out[217]}] -set_max_transition 0.069 [get_ports {link_out[216]}] -set_max_transition 0.069 [get_ports {link_out[215]}] -set_max_transition 0.069 [get_ports {link_out[214]}] -set_max_transition 0.069 [get_ports {link_out[213]}] -set_max_transition 0.069 [get_ports {link_out[212]}] -set_max_transition 0.069 [get_ports {link_out[211]}] -set_max_transition 0.069 [get_ports {link_out[210]}] -set_max_transition 0.069 [get_ports {link_out[209]}] -set_max_transition 0.069 [get_ports {link_out[208]}] -set_max_transition 0.069 [get_ports {link_out[207]}] -set_max_transition 0.069 [get_ports {link_out[206]}] -set_max_transition 0.069 [get_ports {link_out[205]}] -set_max_transition 0.069 [get_ports {link_out[204]}] -set_max_transition 0.069 [get_ports {link_out[203]}] -set_max_transition 0.069 [get_ports {link_out[202]}] -set_max_transition 0.069 [get_ports {link_out[201]}] -set_max_transition 0.069 [get_ports {link_out[200]}] -set_max_transition 0.069 [get_ports {link_out[199]}] -set_max_transition 0.069 [get_ports {link_out[198]}] -set_max_transition 0.069 [get_ports {link_out[197]}] -set_max_transition 0.069 [get_ports {link_out[196]}] -set_max_transition 0.069 [get_ports {link_out[195]}] -set_max_transition 0.069 [get_ports {link_out[194]}] -set_max_transition 0.069 [get_ports {link_out[193]}] -set_max_transition 0.069 [get_ports {link_out[192]}] -set_max_transition 0.069 [get_ports {link_out[191]}] -set_max_transition 0.069 [get_ports {link_out[190]}] -set_max_transition 0.069 [get_ports {link_out[189]}] -set_max_transition 0.069 [get_ports {link_out[188]}] -set_max_transition 0.069 [get_ports {link_out[187]}] -set_max_transition 0.069 [get_ports {link_out[186]}] -set_max_transition 0.069 [get_ports {link_out[185]}] -set_max_transition 0.069 [get_ports {link_out[184]}] -set_max_transition 0.069 [get_ports {link_out[183]}] -set_max_transition 0.069 [get_ports {link_out[182]}] -set_max_transition 0.069 [get_ports {link_out[181]}] -set_max_transition 0.069 [get_ports {link_out[180]}] -set_max_transition 0.069 [get_ports {link_out[179]}] -set_max_transition 0.069 [get_ports {link_out[178]}] -set_max_transition 0.069 [get_ports {link_out[177]}] -set_max_transition 0.069 [get_ports {link_out[176]}] -set_max_transition 0.069 [get_ports {link_out[175]}] -set_max_transition 0.069 [get_ports {link_out[174]}] -set_max_transition 0.069 [get_ports {link_out[173]}] -set_max_transition 0.069 [get_ports {link_out[172]}] -set_max_transition 0.069 [get_ports {link_out[171]}] -set_max_transition 0.069 [get_ports {link_out[170]}] -set_max_transition 0.069 [get_ports {link_out[169]}] -set_max_transition 0.069 [get_ports {link_out[168]}] -set_max_transition 0.069 [get_ports {link_out[167]}] -set_max_transition 0.069 [get_ports {link_out[166]}] -set_max_transition 0.069 [get_ports {link_out[165]}] -set_max_transition 0.069 [get_ports {link_out[164]}] -set_max_transition 0.069 [get_ports {link_out[163]}] -set_max_transition 0.069 [get_ports {link_out[162]}] -set_max_transition 0.069 [get_ports {link_out[161]}] -set_max_transition 0.069 [get_ports {link_out[160]}] -set_max_transition 0.069 [get_ports {link_out[159]}] -set_max_transition 0.069 [get_ports {link_out[158]}] -set_max_transition 0.069 [get_ports {link_out[157]}] -set_max_transition 0.069 [get_ports {link_out[156]}] -set_max_transition 0.069 [get_ports {link_out[155]}] -set_max_transition 0.069 [get_ports {link_out[154]}] -set_max_transition 0.069 [get_ports {link_out[153]}] -set_max_transition 0.069 [get_ports {link_out[152]}] -set_max_transition 0.069 [get_ports {link_out[151]}] -set_max_transition 0.069 [get_ports {link_out[150]}] -set_max_transition 0.069 [get_ports {link_out[149]}] -set_max_transition 0.069 [get_ports {link_out[148]}] -set_max_transition 0.069 [get_ports {link_out[147]}] -set_max_transition 0.069 [get_ports {link_out[146]}] -set_max_transition 0.069 [get_ports {link_out[145]}] -set_max_transition 0.069 [get_ports {link_out[144]}] -set_max_transition 0.069 [get_ports {link_out[143]}] -set_max_transition 0.069 [get_ports {link_out[142]}] -set_max_transition 0.069 [get_ports {link_out[141]}] -set_max_transition 0.069 [get_ports {link_out[140]}] -set_max_transition 0.069 [get_ports {link_out[139]}] -set_max_transition 0.069 [get_ports {link_out[138]}] -set_max_transition 0.069 [get_ports {link_out[137]}] -set_max_transition 0.069 [get_ports {link_out[136]}] -set_max_transition 0.069 [get_ports {link_out[135]}] -set_max_transition 0.069 [get_ports {link_out[134]}] -set_max_transition 0.069 [get_ports {link_out[133]}] -set_max_transition 0.069 [get_ports {link_out[132]}] -set_max_transition 0.069 [get_ports {link_out[131]}] -set_max_transition 0.069 [get_ports {link_out[130]}] -set_max_transition 0.069 [get_ports {link_out[129]}] -set_max_transition 0.069 [get_ports {link_out[128]}] -set_max_transition 0.069 [get_ports {link_out[127]}] -set_max_transition 0.069 [get_ports {link_out[126]}] -set_max_transition 0.069 [get_ports {link_out[125]}] -set_max_transition 0.069 [get_ports {link_out[124]}] -set_max_transition 0.069 [get_ports {link_out[123]}] -set_max_transition 0.069 [get_ports {link_out[122]}] -set_max_transition 0.069 [get_ports {link_out[121]}] -set_max_transition 0.069 [get_ports {link_out[120]}] -set_max_transition 0.069 [get_ports {link_out[119]}] -set_max_transition 0.069 [get_ports {link_out[118]}] -set_max_transition 0.069 [get_ports {link_out[117]}] -set_max_transition 0.069 [get_ports {link_out[116]}] -set_max_transition 0.069 [get_ports {link_out[115]}] -set_max_transition 0.069 [get_ports {link_out[114]}] -set_max_transition 0.069 [get_ports {link_out[113]}] -set_max_transition 0.069 [get_ports {link_out[112]}] -set_max_transition 0.069 [get_ports {link_out[111]}] -set_max_transition 0.069 [get_ports {link_out[110]}] -set_max_transition 0.069 [get_ports {link_out[109]}] -set_max_transition 0.069 [get_ports {link_out[108]}] -set_max_transition 0.069 [get_ports {link_out[107]}] -set_max_transition 0.069 [get_ports {link_out[106]}] -set_max_transition 0.069 [get_ports {link_out[105]}] -set_max_transition 0.069 [get_ports {link_out[104]}] -set_max_transition 0.069 [get_ports {link_out[103]}] -set_max_transition 0.069 [get_ports {link_out[102]}] -set_max_transition 0.069 [get_ports {link_out[101]}] -set_max_transition 0.069 [get_ports {link_out[100]}] -set_max_transition 0.069 [get_ports {link_out[99]}] -set_max_transition 0.069 [get_ports {link_out[98]}] -set_max_transition 0.069 [get_ports {link_out[97]}] -set_max_transition 0.069 [get_ports {link_out[96]}] -set_max_transition 0.069 [get_ports {link_out[95]}] -set_max_transition 0.069 [get_ports {link_out[94]}] -set_max_transition 0.069 [get_ports {link_out[93]}] -set_max_transition 0.069 [get_ports {link_out[92]}] -set_max_transition 0.069 [get_ports {link_out[91]}] -set_max_transition 0.069 [get_ports {link_out[90]}] -set_max_transition 0.069 [get_ports {link_out[89]}] -set_max_transition 0.069 [get_ports {link_out[88]}] -set_max_transition 0.069 [get_ports {link_out[87]}] -set_max_transition 0.069 [get_ports {link_out[86]}] -set_max_transition 0.069 [get_ports {link_out[85]}] -set_max_transition 0.069 [get_ports {link_out[84]}] -set_max_transition 0.069 [get_ports {link_out[83]}] -set_max_transition 0.069 [get_ports {link_out[82]}] -set_max_transition 0.069 [get_ports {link_out[81]}] -set_max_transition 0.069 [get_ports {link_out[80]}] -set_max_transition 0.069 [get_ports {link_out[79]}] -set_max_transition 0.069 [get_ports {link_out[78]}] -set_max_transition 0.069 [get_ports {link_out[77]}] -set_max_transition 0.069 [get_ports {link_out[76]}] -set_max_transition 0.069 [get_ports {link_out[75]}] -set_max_transition 0.069 [get_ports {link_out[74]}] -set_max_transition 0.069 [get_ports {link_out[73]}] -set_max_transition 0.069 [get_ports {link_out[72]}] -set_max_transition 0.069 [get_ports {link_out[71]}] -set_max_transition 0.069 [get_ports {link_out[70]}] -set_max_transition 0.069 [get_ports {link_out[69]}] -set_max_transition 0.069 [get_ports {link_out[68]}] -set_max_transition 0.069 [get_ports {link_out[67]}] -set_max_transition 0.069 [get_ports {link_out[66]}] -set_max_transition 0.069 [get_ports {link_out[65]}] -set_max_transition 0.069 [get_ports {link_out[64]}] -set_max_transition 0.069 [get_ports {link_out[63]}] -set_max_transition 0.069 [get_ports {link_out[62]}] -set_max_transition 0.069 [get_ports {link_out[61]}] -set_max_transition 0.069 [get_ports {link_out[60]}] -set_max_transition 0.069 [get_ports {link_out[59]}] -set_max_transition 0.069 [get_ports {link_out[58]}] -set_max_transition 0.069 [get_ports {link_out[57]}] -set_max_transition 0.069 [get_ports {link_out[56]}] -set_max_transition 0.069 [get_ports {link_out[55]}] -set_max_transition 0.069 [get_ports {link_out[54]}] -set_max_transition 0.069 [get_ports {link_out[53]}] -set_max_transition 0.069 [get_ports {link_out[52]}] -set_max_transition 0.069 [get_ports {link_out[51]}] -set_max_transition 0.069 [get_ports {link_out[50]}] -set_max_transition 0.069 [get_ports {link_out[49]}] -set_max_transition 0.069 [get_ports {link_out[48]}] -set_max_transition 0.069 [get_ports {link_out[47]}] -set_max_transition 0.069 [get_ports {link_out[46]}] -set_max_transition 0.069 [get_ports {link_out[45]}] -set_max_transition 0.069 [get_ports {link_out[44]}] -set_max_transition 0.069 [get_ports {link_out[43]}] -set_max_transition 0.069 [get_ports {link_out[42]}] -set_max_transition 0.069 [get_ports {link_out[41]}] -set_max_transition 0.069 [get_ports {link_out[40]}] -set_max_transition 0.069 [get_ports {link_out[39]}] -set_max_transition 0.069 [get_ports {link_out[38]}] -set_max_transition 0.069 [get_ports {link_out[37]}] -set_max_transition 0.069 [get_ports {link_out[36]}] -set_max_transition 0.069 [get_ports {link_out[35]}] -set_max_transition 0.069 [get_ports {link_out[34]}] -set_max_transition 0.069 [get_ports {link_out[33]}] -set_max_transition 0.069 [get_ports {link_out[32]}] -set_max_transition 0.069 [get_ports {link_out[31]}] -set_max_transition 0.069 [get_ports {link_out[30]}] -set_max_transition 0.069 [get_ports {link_out[29]}] -set_max_transition 0.069 [get_ports {link_out[28]}] -set_max_transition 0.069 [get_ports {link_out[27]}] -set_max_transition 0.069 [get_ports {link_out[26]}] -set_max_transition 0.069 [get_ports {link_out[25]}] -set_max_transition 0.069 [get_ports {link_out[24]}] -set_max_transition 0.069 [get_ports {link_out[23]}] -set_max_transition 0.069 [get_ports {link_out[22]}] -set_max_transition 0.069 [get_ports {link_out[21]}] -set_max_transition 0.069 [get_ports {link_out[20]}] -set_max_transition 0.069 [get_ports {link_out[19]}] -set_max_transition 0.069 [get_ports {link_out[18]}] -set_max_transition 0.069 [get_ports {link_out[17]}] -set_max_transition 0.069 [get_ports {link_out[16]}] -set_max_transition 0.069 [get_ports {link_out[15]}] -set_max_transition 0.069 [get_ports {link_out[14]}] -set_max_transition 0.069 [get_ports {link_out[13]}] -set_max_transition 0.069 [get_ports {link_out[12]}] -set_max_transition 0.069 [get_ports {link_out[11]}] -set_max_transition 0.069 [get_ports {link_out[10]}] -set_max_transition 0.069 [get_ports {link_out[9]}] -set_max_transition 0.069 [get_ports {link_out[8]}] -set_max_transition 0.069 [get_ports {link_out[7]}] -set_max_transition 0.069 [get_ports {link_out[6]}] -set_max_transition 0.069 [get_ports {link_out[5]}] -set_max_transition 0.069 [get_ports {link_out[4]}] -set_max_transition 0.069 [get_ports {link_out[3]}] -set_max_transition 0.069 [get_ports {link_out[2]}] -set_max_transition 0.069 [get_ports {link_out[1]}] -set_max_transition 0.069 [get_ports {link_out[0]}] -create_clock [get_ports clk_i] -name core_clk -period 8 -waveform {0 4} -set_clock_latency -source 0 [get_clocks core_clk] -set_clock_uncertainty 0.02 [get_clocks core_clk] -set_clock_transition -min -fall 0.069 [get_clocks core_clk] -set_clock_transition -min -rise 0.069 [get_clocks core_clk] -set_clock_transition -max -fall 0.069 [get_clocks core_clk] -set_clock_transition -max -rise 0.069 [get_clocks core_clk] -set_false_path -from [list [get_ports {my_x_i[3]}] [get_ports {my_x_i[2]}] [get_ports {my_x_i[1]}] [get_ports {my_x_i[0]}] [get_ports {my_y_i[4]}] [get_ports {my_y_i[3]}] [get_ports {my_y_i[2]}] [get_ports {my_y_i[1]}] [get_ports {my_y_i[0]}]] -set_false_path -hold -to [list [get_pins proc.h_z.vanilla_core.rf_0.rf_mem.macro_mem0/CLKA] [get_pins proc.h_z.vanilla_core.rf_0.rf_mem.macro_mem0/CLKB] [get_pins proc.h_z.vanilla_core.rf_0.rf_mem.macro_mem1/CLKA] [get_pins proc.h_z.vanilla_core.rf_0.rf_mem.macro_mem1/CLKB]] -set_input_delay -clock core_clk 6.01 [get_ports reset_i] -set_input_transition -max 0.069 [get_ports clk_i] -set_input_transition -min 0.069 [get_ports clk_i] -set_input_transition -max 0.069 [get_ports reset_i] -set_input_transition -min 0.069 [get_ports reset_i] -set_input_transition -max 0.069 [get_ports {link_in[355]}] -set_input_transition -min 0.069 [get_ports {link_in[355]}] -set_input_transition -max 0.069 [get_ports {link_in[354]}] -set_input_transition -min 0.069 [get_ports {link_in[354]}] -set_input_transition -max 0.069 [get_ports {link_in[353]}] -set_input_transition -min 0.069 [get_ports {link_in[353]}] -set_input_transition -max 0.069 [get_ports {link_in[352]}] -set_input_transition -min 0.069 [get_ports {link_in[352]}] -set_input_transition -max 0.069 [get_ports {link_in[351]}] -set_input_transition -min 0.069 [get_ports {link_in[351]}] -set_input_transition -max 0.069 [get_ports {link_in[350]}] -set_input_transition -min 0.069 [get_ports {link_in[350]}] -set_input_transition -max 0.069 [get_ports {link_in[349]}] -set_input_transition -min 0.069 [get_ports {link_in[349]}] -set_input_transition -max 0.069 [get_ports {link_in[348]}] -set_input_transition -min 0.069 [get_ports {link_in[348]}] -set_input_transition -max 0.069 [get_ports {link_in[347]}] -set_input_transition -min 0.069 [get_ports {link_in[347]}] -set_input_transition -max 0.069 [get_ports {link_in[346]}] -set_input_transition -min 0.069 [get_ports {link_in[346]}] -set_input_transition -max 0.069 [get_ports {link_in[345]}] -set_input_transition -min 0.069 [get_ports {link_in[345]}] -set_input_transition -max 0.069 [get_ports {link_in[344]}] -set_input_transition -min 0.069 [get_ports {link_in[344]}] -set_input_transition -max 0.069 [get_ports {link_in[343]}] -set_input_transition -min 0.069 [get_ports {link_in[343]}] -set_input_transition -max 0.069 [get_ports {link_in[342]}] -set_input_transition -min 0.069 [get_ports {link_in[342]}] -set_input_transition -max 0.069 [get_ports {link_in[341]}] -set_input_transition -min 0.069 [get_ports {link_in[341]}] -set_input_transition -max 0.069 [get_ports {link_in[340]}] -set_input_transition -min 0.069 [get_ports {link_in[340]}] -set_input_transition -max 0.069 [get_ports {link_in[339]}] -set_input_transition -min 0.069 [get_ports {link_in[339]}] -set_input_transition -max 0.069 [get_ports {link_in[338]}] -set_input_transition -min 0.069 [get_ports {link_in[338]}] -set_input_transition -max 0.069 [get_ports {link_in[337]}] -set_input_transition -min 0.069 [get_ports {link_in[337]}] -set_input_transition -max 0.069 [get_ports {link_in[336]}] -set_input_transition -min 0.069 [get_ports {link_in[336]}] -set_input_transition -max 0.069 [get_ports {link_in[335]}] -set_input_transition -min 0.069 [get_ports {link_in[335]}] -set_input_transition -max 0.069 [get_ports {link_in[334]}] -set_input_transition -min 0.069 [get_ports {link_in[334]}] -set_input_transition -max 0.069 [get_ports {link_in[333]}] -set_input_transition -min 0.069 [get_ports {link_in[333]}] -set_input_transition -max 0.069 [get_ports {link_in[332]}] -set_input_transition -min 0.069 [get_ports {link_in[332]}] -set_input_transition -max 0.069 [get_ports {link_in[331]}] -set_input_transition -min 0.069 [get_ports {link_in[331]}] -set_input_transition -max 0.069 [get_ports {link_in[330]}] -set_input_transition -min 0.069 [get_ports {link_in[330]}] -set_input_transition -max 0.069 [get_ports {link_in[329]}] -set_input_transition -min 0.069 [get_ports {link_in[329]}] -set_input_transition -max 0.069 [get_ports {link_in[328]}] -set_input_transition -min 0.069 [get_ports {link_in[328]}] -set_input_transition -max 0.069 [get_ports {link_in[327]}] -set_input_transition -min 0.069 [get_ports {link_in[327]}] -set_input_transition -max 0.069 [get_ports {link_in[326]}] -set_input_transition -min 0.069 [get_ports {link_in[326]}] -set_input_transition -max 0.069 [get_ports {link_in[325]}] -set_input_transition -min 0.069 [get_ports {link_in[325]}] -set_input_transition -max 0.069 [get_ports {link_in[324]}] -set_input_transition -min 0.069 [get_ports {link_in[324]}] -set_input_transition -max 0.069 [get_ports {link_in[323]}] -set_input_transition -min 0.069 [get_ports {link_in[323]}] -set_input_transition -max 0.069 [get_ports {link_in[322]}] -set_input_transition -min 0.069 [get_ports {link_in[322]}] -set_input_transition -max 0.069 [get_ports {link_in[321]}] -set_input_transition -min 0.069 [get_ports {link_in[321]}] -set_input_transition -max 0.069 [get_ports {link_in[320]}] -set_input_transition -min 0.069 [get_ports {link_in[320]}] -set_input_transition -max 0.069 [get_ports {link_in[319]}] -set_input_transition -min 0.069 [get_ports {link_in[319]}] -set_input_transition -max 0.069 [get_ports {link_in[318]}] -set_input_transition -min 0.069 [get_ports {link_in[318]}] -set_input_transition -max 0.069 [get_ports {link_in[317]}] -set_input_transition -min 0.069 [get_ports {link_in[317]}] -set_input_transition -max 0.069 [get_ports {link_in[316]}] -set_input_transition -min 0.069 [get_ports {link_in[316]}] -set_input_transition -max 0.069 [get_ports {link_in[315]}] -set_input_transition -min 0.069 [get_ports {link_in[315]}] -set_input_transition -max 0.069 [get_ports {link_in[314]}] -set_input_transition -min 0.069 [get_ports {link_in[314]}] -set_input_transition -max 0.069 [get_ports {link_in[313]}] -set_input_transition -min 0.069 [get_ports {link_in[313]}] -set_input_transition -max 0.069 [get_ports {link_in[312]}] -set_input_transition -min 0.069 [get_ports {link_in[312]}] -set_input_transition -max 0.069 [get_ports {link_in[311]}] -set_input_transition -min 0.069 [get_ports {link_in[311]}] -set_input_transition -max 0.069 [get_ports {link_in[310]}] -set_input_transition -min 0.069 [get_ports {link_in[310]}] -set_input_transition -max 0.069 [get_ports {link_in[309]}] -set_input_transition -min 0.069 [get_ports {link_in[309]}] -set_input_transition -max 0.069 [get_ports {link_in[308]}] -set_input_transition -min 0.069 [get_ports {link_in[308]}] -set_input_transition -max 0.069 [get_ports {link_in[307]}] -set_input_transition -min 0.069 [get_ports {link_in[307]}] -set_input_transition -max 0.069 [get_ports {link_in[306]}] -set_input_transition -min 0.069 [get_ports {link_in[306]}] -set_input_transition -max 0.069 [get_ports {link_in[305]}] -set_input_transition -min 0.069 [get_ports {link_in[305]}] -set_input_transition -max 0.069 [get_ports {link_in[304]}] -set_input_transition -min 0.069 [get_ports {link_in[304]}] -set_input_transition -max 0.069 [get_ports {link_in[303]}] -set_input_transition -min 0.069 [get_ports {link_in[303]}] -set_input_transition -max 0.069 [get_ports {link_in[302]}] -set_input_transition -min 0.069 [get_ports {link_in[302]}] -set_input_transition -max 0.069 [get_ports {link_in[301]}] -set_input_transition -min 0.069 [get_ports {link_in[301]}] -set_input_transition -max 0.069 [get_ports {link_in[300]}] -set_input_transition -min 0.069 [get_ports {link_in[300]}] -set_input_transition -max 0.069 [get_ports {link_in[299]}] -set_input_transition -min 0.069 [get_ports {link_in[299]}] -set_input_transition -max 0.069 [get_ports {link_in[298]}] -set_input_transition -min 0.069 [get_ports {link_in[298]}] -set_input_transition -max 0.069 [get_ports {link_in[297]}] -set_input_transition -min 0.069 [get_ports {link_in[297]}] -set_input_transition -max 0.069 [get_ports {link_in[296]}] -set_input_transition -min 0.069 [get_ports {link_in[296]}] -set_input_transition -max 0.069 [get_ports {link_in[295]}] -set_input_transition -min 0.069 [get_ports {link_in[295]}] -set_input_transition -max 0.069 [get_ports {link_in[294]}] -set_input_transition -min 0.069 [get_ports {link_in[294]}] -set_input_transition -max 0.069 [get_ports {link_in[293]}] -set_input_transition -min 0.069 [get_ports {link_in[293]}] -set_input_transition -max 0.069 [get_ports {link_in[292]}] -set_input_transition -min 0.069 [get_ports {link_in[292]}] -set_input_transition -max 0.069 [get_ports {link_in[291]}] -set_input_transition -min 0.069 [get_ports {link_in[291]}] -set_input_transition -max 0.069 [get_ports {link_in[290]}] -set_input_transition -min 0.069 [get_ports {link_in[290]}] -set_input_transition -max 0.069 [get_ports {link_in[289]}] -set_input_transition -min 0.069 [get_ports {link_in[289]}] -set_input_transition -max 0.069 [get_ports {link_in[288]}] -set_input_transition -min 0.069 [get_ports {link_in[288]}] -set_input_transition -max 0.069 [get_ports {link_in[287]}] -set_input_transition -min 0.069 [get_ports {link_in[287]}] -set_input_transition -max 0.069 [get_ports {link_in[286]}] -set_input_transition -min 0.069 [get_ports {link_in[286]}] -set_input_transition -max 0.069 [get_ports {link_in[285]}] -set_input_transition -min 0.069 [get_ports {link_in[285]}] -set_input_transition -max 0.069 [get_ports {link_in[284]}] -set_input_transition -min 0.069 [get_ports {link_in[284]}] -set_input_transition -max 0.069 [get_ports {link_in[283]}] -set_input_transition -min 0.069 [get_ports {link_in[283]}] -set_input_transition -max 0.069 [get_ports {link_in[282]}] -set_input_transition -min 0.069 [get_ports {link_in[282]}] -set_input_transition -max 0.069 [get_ports {link_in[281]}] -set_input_transition -min 0.069 [get_ports {link_in[281]}] -set_input_transition -max 0.069 [get_ports {link_in[280]}] -set_input_transition -min 0.069 [get_ports {link_in[280]}] -set_input_transition -max 0.069 [get_ports {link_in[279]}] -set_input_transition -min 0.069 [get_ports {link_in[279]}] -set_input_transition -max 0.069 [get_ports {link_in[278]}] -set_input_transition -min 0.069 [get_ports {link_in[278]}] -set_input_transition -max 0.069 [get_ports {link_in[277]}] -set_input_transition -min 0.069 [get_ports {link_in[277]}] -set_input_transition -max 0.069 [get_ports {link_in[276]}] -set_input_transition -min 0.069 [get_ports {link_in[276]}] -set_input_transition -max 0.069 [get_ports {link_in[275]}] -set_input_transition -min 0.069 [get_ports {link_in[275]}] -set_input_transition -max 0.069 [get_ports {link_in[274]}] -set_input_transition -min 0.069 [get_ports {link_in[274]}] -set_input_transition -max 0.069 [get_ports {link_in[273]}] -set_input_transition -min 0.069 [get_ports {link_in[273]}] -set_input_transition -max 0.069 [get_ports {link_in[272]}] -set_input_transition -min 0.069 [get_ports {link_in[272]}] -set_input_transition -max 0.069 [get_ports {link_in[271]}] -set_input_transition -min 0.069 [get_ports {link_in[271]}] -set_input_transition -max 0.069 [get_ports {link_in[270]}] -set_input_transition -min 0.069 [get_ports {link_in[270]}] -set_input_transition -max 0.069 [get_ports {link_in[269]}] -set_input_transition -min 0.069 [get_ports {link_in[269]}] -set_input_transition -max 0.069 [get_ports {link_in[268]}] -set_input_transition -min 0.069 [get_ports {link_in[268]}] -set_input_transition -max 0.069 [get_ports {link_in[267]}] -set_input_transition -min 0.069 [get_ports {link_in[267]}] -set_input_transition -max 0.069 [get_ports {link_in[266]}] -set_input_transition -min 0.069 [get_ports {link_in[266]}] -set_input_transition -max 0.069 [get_ports {link_in[265]}] -set_input_transition -min 0.069 [get_ports {link_in[265]}] -set_input_transition -max 0.069 [get_ports {link_in[264]}] -set_input_transition -min 0.069 [get_ports {link_in[264]}] -set_input_transition -max 0.069 [get_ports {link_in[263]}] -set_input_transition -min 0.069 [get_ports {link_in[263]}] -set_input_transition -max 0.069 [get_ports {link_in[262]}] -set_input_transition -min 0.069 [get_ports {link_in[262]}] -set_input_transition -max 0.069 [get_ports {link_in[261]}] -set_input_transition -min 0.069 [get_ports {link_in[261]}] -set_input_transition -max 0.069 [get_ports {link_in[260]}] -set_input_transition -min 0.069 [get_ports {link_in[260]}] -set_input_transition -max 0.069 [get_ports {link_in[259]}] -set_input_transition -min 0.069 [get_ports {link_in[259]}] -set_input_transition -max 0.069 [get_ports {link_in[258]}] -set_input_transition -min 0.069 [get_ports {link_in[258]}] -set_input_transition -max 0.069 [get_ports {link_in[257]}] -set_input_transition -min 0.069 [get_ports {link_in[257]}] -set_input_transition -max 0.069 [get_ports {link_in[256]}] -set_input_transition -min 0.069 [get_ports {link_in[256]}] -set_input_transition -max 0.069 [get_ports {link_in[255]}] -set_input_transition -min 0.069 [get_ports {link_in[255]}] -set_input_transition -max 0.069 [get_ports {link_in[254]}] -set_input_transition -min 0.069 [get_ports {link_in[254]}] -set_input_transition -max 0.069 [get_ports {link_in[253]}] -set_input_transition -min 0.069 [get_ports {link_in[253]}] -set_input_transition -max 0.069 [get_ports {link_in[252]}] -set_input_transition -min 0.069 [get_ports {link_in[252]}] -set_input_transition -max 0.069 [get_ports {link_in[251]}] -set_input_transition -min 0.069 [get_ports {link_in[251]}] -set_input_transition -max 0.069 [get_ports {link_in[250]}] -set_input_transition -min 0.069 [get_ports {link_in[250]}] -set_input_transition -max 0.069 [get_ports {link_in[249]}] -set_input_transition -min 0.069 [get_ports {link_in[249]}] -set_input_transition -max 0.069 [get_ports {link_in[248]}] -set_input_transition -min 0.069 [get_ports {link_in[248]}] -set_input_transition -max 0.069 [get_ports {link_in[247]}] -set_input_transition -min 0.069 [get_ports {link_in[247]}] -set_input_transition -max 0.069 [get_ports {link_in[246]}] -set_input_transition -min 0.069 [get_ports {link_in[246]}] -set_input_transition -max 0.069 [get_ports {link_in[245]}] -set_input_transition -min 0.069 [get_ports {link_in[245]}] -set_input_transition -max 0.069 [get_ports {link_in[244]}] -set_input_transition -min 0.069 [get_ports {link_in[244]}] -set_input_transition -max 0.069 [get_ports {link_in[243]}] -set_input_transition -min 0.069 [get_ports {link_in[243]}] -set_input_transition -max 0.069 [get_ports {link_in[242]}] -set_input_transition -min 0.069 [get_ports {link_in[242]}] -set_input_transition -max 0.069 [get_ports {link_in[241]}] -set_input_transition -min 0.069 [get_ports {link_in[241]}] -set_input_transition -max 0.069 [get_ports {link_in[240]}] -set_input_transition -min 0.069 [get_ports {link_in[240]}] -set_input_transition -max 0.069 [get_ports {link_in[239]}] -set_input_transition -min 0.069 [get_ports {link_in[239]}] -set_input_transition -max 0.069 [get_ports {link_in[238]}] -set_input_transition -min 0.069 [get_ports {link_in[238]}] -set_input_transition -max 0.069 [get_ports {link_in[237]}] -set_input_transition -min 0.069 [get_ports {link_in[237]}] -set_input_transition -max 0.069 [get_ports {link_in[236]}] -set_input_transition -min 0.069 [get_ports {link_in[236]}] -set_input_transition -max 0.069 [get_ports {link_in[235]}] -set_input_transition -min 0.069 [get_ports {link_in[235]}] -set_input_transition -max 0.069 [get_ports {link_in[234]}] -set_input_transition -min 0.069 [get_ports {link_in[234]}] -set_input_transition -max 0.069 [get_ports {link_in[233]}] -set_input_transition -min 0.069 [get_ports {link_in[233]}] -set_input_transition -max 0.069 [get_ports {link_in[232]}] -set_input_transition -min 0.069 [get_ports {link_in[232]}] -set_input_transition -max 0.069 [get_ports {link_in[231]}] -set_input_transition -min 0.069 [get_ports {link_in[231]}] -set_input_transition -max 0.069 [get_ports {link_in[230]}] -set_input_transition -min 0.069 [get_ports {link_in[230]}] -set_input_transition -max 0.069 [get_ports {link_in[229]}] -set_input_transition -min 0.069 [get_ports {link_in[229]}] -set_input_transition -max 0.069 [get_ports {link_in[228]}] -set_input_transition -min 0.069 [get_ports {link_in[228]}] -set_input_transition -max 0.069 [get_ports {link_in[227]}] -set_input_transition -min 0.069 [get_ports {link_in[227]}] -set_input_transition -max 0.069 [get_ports {link_in[226]}] -set_input_transition -min 0.069 [get_ports {link_in[226]}] -set_input_transition -max 0.069 [get_ports {link_in[225]}] -set_input_transition -min 0.069 [get_ports {link_in[225]}] -set_input_transition -max 0.069 [get_ports {link_in[224]}] -set_input_transition -min 0.069 [get_ports {link_in[224]}] -set_input_transition -max 0.069 [get_ports {link_in[223]}] -set_input_transition -min 0.069 [get_ports {link_in[223]}] -set_input_transition -max 0.069 [get_ports {link_in[222]}] -set_input_transition -min 0.069 [get_ports {link_in[222]}] -set_input_transition -max 0.069 [get_ports {link_in[221]}] -set_input_transition -min 0.069 [get_ports {link_in[221]}] -set_input_transition -max 0.069 [get_ports {link_in[220]}] -set_input_transition -min 0.069 [get_ports {link_in[220]}] -set_input_transition -max 0.069 [get_ports {link_in[219]}] -set_input_transition -min 0.069 [get_ports {link_in[219]}] -set_input_transition -max 0.069 [get_ports {link_in[218]}] -set_input_transition -min 0.069 [get_ports {link_in[218]}] -set_input_transition -max 0.069 [get_ports {link_in[217]}] -set_input_transition -min 0.069 [get_ports {link_in[217]}] -set_input_transition -max 0.069 [get_ports {link_in[216]}] -set_input_transition -min 0.069 [get_ports {link_in[216]}] -set_input_transition -max 0.069 [get_ports {link_in[215]}] -set_input_transition -min 0.069 [get_ports {link_in[215]}] -set_input_transition -max 0.069 [get_ports {link_in[214]}] -set_input_transition -min 0.069 [get_ports {link_in[214]}] -set_input_transition -max 0.069 [get_ports {link_in[213]}] -set_input_transition -min 0.069 [get_ports {link_in[213]}] -set_input_transition -max 0.069 [get_ports {link_in[212]}] -set_input_transition -min 0.069 [get_ports {link_in[212]}] -set_input_transition -max 0.069 [get_ports {link_in[211]}] -set_input_transition -min 0.069 [get_ports {link_in[211]}] -set_input_transition -max 0.069 [get_ports {link_in[210]}] -set_input_transition -min 0.069 [get_ports {link_in[210]}] -set_input_transition -max 0.069 [get_ports {link_in[209]}] -set_input_transition -min 0.069 [get_ports {link_in[209]}] -set_input_transition -max 0.069 [get_ports {link_in[208]}] -set_input_transition -min 0.069 [get_ports {link_in[208]}] -set_input_transition -max 0.069 [get_ports {link_in[207]}] -set_input_transition -min 0.069 [get_ports {link_in[207]}] -set_input_transition -max 0.069 [get_ports {link_in[206]}] -set_input_transition -min 0.069 [get_ports {link_in[206]}] -set_input_transition -max 0.069 [get_ports {link_in[205]}] -set_input_transition -min 0.069 [get_ports {link_in[205]}] -set_input_transition -max 0.069 [get_ports {link_in[204]}] -set_input_transition -min 0.069 [get_ports {link_in[204]}] -set_input_transition -max 0.069 [get_ports {link_in[203]}] -set_input_transition -min 0.069 [get_ports {link_in[203]}] -set_input_transition -max 0.069 [get_ports {link_in[202]}] -set_input_transition -min 0.069 [get_ports {link_in[202]}] -set_input_transition -max 0.069 [get_ports {link_in[201]}] -set_input_transition -min 0.069 [get_ports {link_in[201]}] -set_input_transition -max 0.069 [get_ports {link_in[200]}] -set_input_transition -min 0.069 [get_ports {link_in[200]}] -set_input_transition -max 0.069 [get_ports {link_in[199]}] -set_input_transition -min 0.069 [get_ports {link_in[199]}] -set_input_transition -max 0.069 [get_ports {link_in[198]}] -set_input_transition -min 0.069 [get_ports {link_in[198]}] -set_input_transition -max 0.069 [get_ports {link_in[197]}] -set_input_transition -min 0.069 [get_ports {link_in[197]}] -set_input_transition -max 0.069 [get_ports {link_in[196]}] -set_input_transition -min 0.069 [get_ports {link_in[196]}] -set_input_transition -max 0.069 [get_ports {link_in[195]}] -set_input_transition -min 0.069 [get_ports {link_in[195]}] -set_input_transition -max 0.069 [get_ports {link_in[194]}] -set_input_transition -min 0.069 [get_ports {link_in[194]}] -set_input_transition -max 0.069 [get_ports {link_in[193]}] -set_input_transition -min 0.069 [get_ports {link_in[193]}] -set_input_transition -max 0.069 [get_ports {link_in[192]}] -set_input_transition -min 0.069 [get_ports {link_in[192]}] -set_input_transition -max 0.069 [get_ports {link_in[191]}] -set_input_transition -min 0.069 [get_ports {link_in[191]}] -set_input_transition -max 0.069 [get_ports {link_in[190]}] -set_input_transition -min 0.069 [get_ports {link_in[190]}] -set_input_transition -max 0.069 [get_ports {link_in[189]}] -set_input_transition -min 0.069 [get_ports {link_in[189]}] -set_input_transition -max 0.069 [get_ports {link_in[188]}] -set_input_transition -min 0.069 [get_ports {link_in[188]}] -set_input_transition -max 0.069 [get_ports {link_in[187]}] -set_input_transition -min 0.069 [get_ports {link_in[187]}] -set_input_transition -max 0.069 [get_ports {link_in[186]}] -set_input_transition -min 0.069 [get_ports {link_in[186]}] -set_input_transition -max 0.069 [get_ports {link_in[185]}] -set_input_transition -min 0.069 [get_ports {link_in[185]}] -set_input_transition -max 0.069 [get_ports {link_in[184]}] -set_input_transition -min 0.069 [get_ports {link_in[184]}] -set_input_transition -max 0.069 [get_ports {link_in[183]}] -set_input_transition -min 0.069 [get_ports {link_in[183]}] -set_input_transition -max 0.069 [get_ports {link_in[182]}] -set_input_transition -min 0.069 [get_ports {link_in[182]}] -set_input_transition -max 0.069 [get_ports {link_in[181]}] -set_input_transition -min 0.069 [get_ports {link_in[181]}] -set_input_transition -max 0.069 [get_ports {link_in[180]}] -set_input_transition -min 0.069 [get_ports {link_in[180]}] -set_input_transition -max 0.069 [get_ports {link_in[179]}] -set_input_transition -min 0.069 [get_ports {link_in[179]}] -set_input_transition -max 0.069 [get_ports {link_in[178]}] -set_input_transition -min 0.069 [get_ports {link_in[178]}] -set_input_transition -max 0.069 [get_ports {link_in[177]}] -set_input_transition -min 0.069 [get_ports {link_in[177]}] -set_input_transition -max 0.069 [get_ports {link_in[176]}] -set_input_transition -min 0.069 [get_ports {link_in[176]}] -set_input_transition -max 0.069 [get_ports {link_in[175]}] -set_input_transition -min 0.069 [get_ports {link_in[175]}] -set_input_transition -max 0.069 [get_ports {link_in[174]}] -set_input_transition -min 0.069 [get_ports {link_in[174]}] -set_input_transition -max 0.069 [get_ports {link_in[173]}] -set_input_transition -min 0.069 [get_ports {link_in[173]}] -set_input_transition -max 0.069 [get_ports {link_in[172]}] -set_input_transition -min 0.069 [get_ports {link_in[172]}] -set_input_transition -max 0.069 [get_ports {link_in[171]}] -set_input_transition -min 0.069 [get_ports {link_in[171]}] -set_input_transition -max 0.069 [get_ports {link_in[170]}] -set_input_transition -min 0.069 [get_ports {link_in[170]}] -set_input_transition -max 0.069 [get_ports {link_in[169]}] -set_input_transition -min 0.069 [get_ports {link_in[169]}] -set_input_transition -max 0.069 [get_ports {link_in[168]}] -set_input_transition -min 0.069 [get_ports {link_in[168]}] -set_input_transition -max 0.069 [get_ports {link_in[167]}] -set_input_transition -min 0.069 [get_ports {link_in[167]}] -set_input_transition -max 0.069 [get_ports {link_in[166]}] -set_input_transition -min 0.069 [get_ports {link_in[166]}] -set_input_transition -max 0.069 [get_ports {link_in[165]}] -set_input_transition -min 0.069 [get_ports {link_in[165]}] -set_input_transition -max 0.069 [get_ports {link_in[164]}] -set_input_transition -min 0.069 [get_ports {link_in[164]}] -set_input_transition -max 0.069 [get_ports {link_in[163]}] -set_input_transition -min 0.069 [get_ports {link_in[163]}] -set_input_transition -max 0.069 [get_ports {link_in[162]}] -set_input_transition -min 0.069 [get_ports {link_in[162]}] -set_input_transition -max 0.069 [get_ports {link_in[161]}] -set_input_transition -min 0.069 [get_ports {link_in[161]}] -set_input_transition -max 0.069 [get_ports {link_in[160]}] -set_input_transition -min 0.069 [get_ports {link_in[160]}] -set_input_transition -max 0.069 [get_ports {link_in[159]}] -set_input_transition -min 0.069 [get_ports {link_in[159]}] -set_input_transition -max 0.069 [get_ports {link_in[158]}] -set_input_transition -min 0.069 [get_ports {link_in[158]}] -set_input_transition -max 0.069 [get_ports {link_in[157]}] -set_input_transition -min 0.069 [get_ports {link_in[157]}] -set_input_transition -max 0.069 [get_ports {link_in[156]}] -set_input_transition -min 0.069 [get_ports {link_in[156]}] -set_input_transition -max 0.069 [get_ports {link_in[155]}] -set_input_transition -min 0.069 [get_ports {link_in[155]}] -set_input_transition -max 0.069 [get_ports {link_in[154]}] -set_input_transition -min 0.069 [get_ports {link_in[154]}] -set_input_transition -max 0.069 [get_ports {link_in[153]}] -set_input_transition -min 0.069 [get_ports {link_in[153]}] -set_input_transition -max 0.069 [get_ports {link_in[152]}] -set_input_transition -min 0.069 [get_ports {link_in[152]}] -set_input_transition -max 0.069 [get_ports {link_in[151]}] -set_input_transition -min 0.069 [get_ports {link_in[151]}] -set_input_transition -max 0.069 [get_ports {link_in[150]}] -set_input_transition -min 0.069 [get_ports {link_in[150]}] -set_input_transition -max 0.069 [get_ports {link_in[149]}] -set_input_transition -min 0.069 [get_ports {link_in[149]}] -set_input_transition -max 0.069 [get_ports {link_in[148]}] -set_input_transition -min 0.069 [get_ports {link_in[148]}] -set_input_transition -max 0.069 [get_ports {link_in[147]}] -set_input_transition -min 0.069 [get_ports {link_in[147]}] -set_input_transition -max 0.069 [get_ports {link_in[146]}] -set_input_transition -min 0.069 [get_ports {link_in[146]}] -set_input_transition -max 0.069 [get_ports {link_in[145]}] -set_input_transition -min 0.069 [get_ports {link_in[145]}] -set_input_transition -max 0.069 [get_ports {link_in[144]}] -set_input_transition -min 0.069 [get_ports {link_in[144]}] -set_input_transition -max 0.069 [get_ports {link_in[143]}] -set_input_transition -min 0.069 [get_ports {link_in[143]}] -set_input_transition -max 0.069 [get_ports {link_in[142]}] -set_input_transition -min 0.069 [get_ports {link_in[142]}] -set_input_transition -max 0.069 [get_ports {link_in[141]}] -set_input_transition -min 0.069 [get_ports {link_in[141]}] -set_input_transition -max 0.069 [get_ports {link_in[140]}] -set_input_transition -min 0.069 [get_ports {link_in[140]}] -set_input_transition -max 0.069 [get_ports {link_in[139]}] -set_input_transition -min 0.069 [get_ports {link_in[139]}] -set_input_transition -max 0.069 [get_ports {link_in[138]}] -set_input_transition -min 0.069 [get_ports {link_in[138]}] -set_input_transition -max 0.069 [get_ports {link_in[137]}] -set_input_transition -min 0.069 [get_ports {link_in[137]}] -set_input_transition -max 0.069 [get_ports {link_in[136]}] -set_input_transition -min 0.069 [get_ports {link_in[136]}] -set_input_transition -max 0.069 [get_ports {link_in[135]}] -set_input_transition -min 0.069 [get_ports {link_in[135]}] -set_input_transition -max 0.069 [get_ports {link_in[134]}] -set_input_transition -min 0.069 [get_ports {link_in[134]}] -set_input_transition -max 0.069 [get_ports {link_in[133]}] -set_input_transition -min 0.069 [get_ports {link_in[133]}] -set_input_transition -max 0.069 [get_ports {link_in[132]}] -set_input_transition -min 0.069 [get_ports {link_in[132]}] -set_input_transition -max 0.069 [get_ports {link_in[131]}] -set_input_transition -min 0.069 [get_ports {link_in[131]}] -set_input_transition -max 0.069 [get_ports {link_in[130]}] -set_input_transition -min 0.069 [get_ports {link_in[130]}] -set_input_transition -max 0.069 [get_ports {link_in[129]}] -set_input_transition -min 0.069 [get_ports {link_in[129]}] -set_input_transition -max 0.069 [get_ports {link_in[128]}] -set_input_transition -min 0.069 [get_ports {link_in[128]}] -set_input_transition -max 0.069 [get_ports {link_in[127]}] -set_input_transition -min 0.069 [get_ports {link_in[127]}] -set_input_transition -max 0.069 [get_ports {link_in[126]}] -set_input_transition -min 0.069 [get_ports {link_in[126]}] -set_input_transition -max 0.069 [get_ports {link_in[125]}] -set_input_transition -min 0.069 [get_ports {link_in[125]}] -set_input_transition -max 0.069 [get_ports {link_in[124]}] -set_input_transition -min 0.069 [get_ports {link_in[124]}] -set_input_transition -max 0.069 [get_ports {link_in[123]}] -set_input_transition -min 0.069 [get_ports {link_in[123]}] -set_input_transition -max 0.069 [get_ports {link_in[122]}] -set_input_transition -min 0.069 [get_ports {link_in[122]}] -set_input_transition -max 0.069 [get_ports {link_in[121]}] -set_input_transition -min 0.069 [get_ports {link_in[121]}] -set_input_transition -max 0.069 [get_ports {link_in[120]}] -set_input_transition -min 0.069 [get_ports {link_in[120]}] -set_input_transition -max 0.069 [get_ports {link_in[119]}] -set_input_transition -min 0.069 [get_ports {link_in[119]}] -set_input_transition -max 0.069 [get_ports {link_in[118]}] -set_input_transition -min 0.069 [get_ports {link_in[118]}] -set_input_transition -max 0.069 [get_ports {link_in[117]}] -set_input_transition -min 0.069 [get_ports {link_in[117]}] -set_input_transition -max 0.069 [get_ports {link_in[116]}] -set_input_transition -min 0.069 [get_ports {link_in[116]}] -set_input_transition -max 0.069 [get_ports {link_in[115]}] -set_input_transition -min 0.069 [get_ports {link_in[115]}] -set_input_transition -max 0.069 [get_ports {link_in[114]}] -set_input_transition -min 0.069 [get_ports {link_in[114]}] -set_input_transition -max 0.069 [get_ports {link_in[113]}] -set_input_transition -min 0.069 [get_ports {link_in[113]}] -set_input_transition -max 0.069 [get_ports {link_in[112]}] -set_input_transition -min 0.069 [get_ports {link_in[112]}] -set_input_transition -max 0.069 [get_ports {link_in[111]}] -set_input_transition -min 0.069 [get_ports {link_in[111]}] -set_input_transition -max 0.069 [get_ports {link_in[110]}] -set_input_transition -min 0.069 [get_ports {link_in[110]}] -set_input_transition -max 0.069 [get_ports {link_in[109]}] -set_input_transition -min 0.069 [get_ports {link_in[109]}] -set_input_transition -max 0.069 [get_ports {link_in[108]}] -set_input_transition -min 0.069 [get_ports {link_in[108]}] -set_input_transition -max 0.069 [get_ports {link_in[107]}] -set_input_transition -min 0.069 [get_ports {link_in[107]}] -set_input_transition -max 0.069 [get_ports {link_in[106]}] -set_input_transition -min 0.069 [get_ports {link_in[106]}] -set_input_transition -max 0.069 [get_ports {link_in[105]}] -set_input_transition -min 0.069 [get_ports {link_in[105]}] -set_input_transition -max 0.069 [get_ports {link_in[104]}] -set_input_transition -min 0.069 [get_ports {link_in[104]}] -set_input_transition -max 0.069 [get_ports {link_in[103]}] -set_input_transition -min 0.069 [get_ports {link_in[103]}] -set_input_transition -max 0.069 [get_ports {link_in[102]}] -set_input_transition -min 0.069 [get_ports {link_in[102]}] -set_input_transition -max 0.069 [get_ports {link_in[101]}] -set_input_transition -min 0.069 [get_ports {link_in[101]}] -set_input_transition -max 0.069 [get_ports {link_in[100]}] -set_input_transition -min 0.069 [get_ports {link_in[100]}] -set_input_transition -max 0.069 [get_ports {link_in[99]}] -set_input_transition -min 0.069 [get_ports {link_in[99]}] -set_input_transition -max 0.069 [get_ports {link_in[98]}] -set_input_transition -min 0.069 [get_ports {link_in[98]}] -set_input_transition -max 0.069 [get_ports {link_in[97]}] -set_input_transition -min 0.069 [get_ports {link_in[97]}] -set_input_transition -max 0.069 [get_ports {link_in[96]}] -set_input_transition -min 0.069 [get_ports {link_in[96]}] -set_input_transition -max 0.069 [get_ports {link_in[95]}] -set_input_transition -min 0.069 [get_ports {link_in[95]}] -set_input_transition -max 0.069 [get_ports {link_in[94]}] -set_input_transition -min 0.069 [get_ports {link_in[94]}] -set_input_transition -max 0.069 [get_ports {link_in[93]}] -set_input_transition -min 0.069 [get_ports {link_in[93]}] -set_input_transition -max 0.069 [get_ports {link_in[92]}] -set_input_transition -min 0.069 [get_ports {link_in[92]}] -set_input_transition -max 0.069 [get_ports {link_in[91]}] -set_input_transition -min 0.069 [get_ports {link_in[91]}] -set_input_transition -max 0.069 [get_ports {link_in[90]}] -set_input_transition -min 0.069 [get_ports {link_in[90]}] -set_input_transition -max 0.069 [get_ports {link_in[89]}] -set_input_transition -min 0.069 [get_ports {link_in[89]}] -set_input_transition -max 0.069 [get_ports {link_in[88]}] -set_input_transition -min 0.069 [get_ports {link_in[88]}] -set_input_transition -max 0.069 [get_ports {link_in[87]}] -set_input_transition -min 0.069 [get_ports {link_in[87]}] -set_input_transition -max 0.069 [get_ports {link_in[86]}] -set_input_transition -min 0.069 [get_ports {link_in[86]}] -set_input_transition -max 0.069 [get_ports {link_in[85]}] -set_input_transition -min 0.069 [get_ports {link_in[85]}] -set_input_transition -max 0.069 [get_ports {link_in[84]}] -set_input_transition -min 0.069 [get_ports {link_in[84]}] -set_input_transition -max 0.069 [get_ports {link_in[83]}] -set_input_transition -min 0.069 [get_ports {link_in[83]}] -set_input_transition -max 0.069 [get_ports {link_in[82]}] -set_input_transition -min 0.069 [get_ports {link_in[82]}] -set_input_transition -max 0.069 [get_ports {link_in[81]}] -set_input_transition -min 0.069 [get_ports {link_in[81]}] -set_input_transition -max 0.069 [get_ports {link_in[80]}] -set_input_transition -min 0.069 [get_ports {link_in[80]}] -set_input_transition -max 0.069 [get_ports {link_in[79]}] -set_input_transition -min 0.069 [get_ports {link_in[79]}] -set_input_transition -max 0.069 [get_ports {link_in[78]}] -set_input_transition -min 0.069 [get_ports {link_in[78]}] -set_input_transition -max 0.069 [get_ports {link_in[77]}] -set_input_transition -min 0.069 [get_ports {link_in[77]}] -set_input_transition -max 0.069 [get_ports {link_in[76]}] -set_input_transition -min 0.069 [get_ports {link_in[76]}] -set_input_transition -max 0.069 [get_ports {link_in[75]}] -set_input_transition -min 0.069 [get_ports {link_in[75]}] -set_input_transition -max 0.069 [get_ports {link_in[74]}] -set_input_transition -min 0.069 [get_ports {link_in[74]}] -set_input_transition -max 0.069 [get_ports {link_in[73]}] -set_input_transition -min 0.069 [get_ports {link_in[73]}] -set_input_transition -max 0.069 [get_ports {link_in[72]}] -set_input_transition -min 0.069 [get_ports {link_in[72]}] -set_input_transition -max 0.069 [get_ports {link_in[71]}] -set_input_transition -min 0.069 [get_ports {link_in[71]}] -set_input_transition -max 0.069 [get_ports {link_in[70]}] -set_input_transition -min 0.069 [get_ports {link_in[70]}] -set_input_transition -max 0.069 [get_ports {link_in[69]}] -set_input_transition -min 0.069 [get_ports {link_in[69]}] -set_input_transition -max 0.069 [get_ports {link_in[68]}] -set_input_transition -min 0.069 [get_ports {link_in[68]}] -set_input_transition -max 0.069 [get_ports {link_in[67]}] -set_input_transition -min 0.069 [get_ports {link_in[67]}] -set_input_transition -max 0.069 [get_ports {link_in[66]}] -set_input_transition -min 0.069 [get_ports {link_in[66]}] -set_input_transition -max 0.069 [get_ports {link_in[65]}] -set_input_transition -min 0.069 [get_ports {link_in[65]}] -set_input_transition -max 0.069 [get_ports {link_in[64]}] -set_input_transition -min 0.069 [get_ports {link_in[64]}] -set_input_transition -max 0.069 [get_ports {link_in[63]}] -set_input_transition -min 0.069 [get_ports {link_in[63]}] -set_input_transition -max 0.069 [get_ports {link_in[62]}] -set_input_transition -min 0.069 [get_ports {link_in[62]}] -set_input_transition -max 0.069 [get_ports {link_in[61]}] -set_input_transition -min 0.069 [get_ports {link_in[61]}] -set_input_transition -max 0.069 [get_ports {link_in[60]}] -set_input_transition -min 0.069 [get_ports {link_in[60]}] -set_input_transition -max 0.069 [get_ports {link_in[59]}] -set_input_transition -min 0.069 [get_ports {link_in[59]}] -set_input_transition -max 0.069 [get_ports {link_in[58]}] -set_input_transition -min 0.069 [get_ports {link_in[58]}] -set_input_transition -max 0.069 [get_ports {link_in[57]}] -set_input_transition -min 0.069 [get_ports {link_in[57]}] -set_input_transition -max 0.069 [get_ports {link_in[56]}] -set_input_transition -min 0.069 [get_ports {link_in[56]}] -set_input_transition -max 0.069 [get_ports {link_in[55]}] -set_input_transition -min 0.069 [get_ports {link_in[55]}] -set_input_transition -max 0.069 [get_ports {link_in[54]}] -set_input_transition -min 0.069 [get_ports {link_in[54]}] -set_input_transition -max 0.069 [get_ports {link_in[53]}] -set_input_transition -min 0.069 [get_ports {link_in[53]}] -set_input_transition -max 0.069 [get_ports {link_in[52]}] -set_input_transition -min 0.069 [get_ports {link_in[52]}] -set_input_transition -max 0.069 [get_ports {link_in[51]}] -set_input_transition -min 0.069 [get_ports {link_in[51]}] -set_input_transition -max 0.069 [get_ports {link_in[50]}] -set_input_transition -min 0.069 [get_ports {link_in[50]}] -set_input_transition -max 0.069 [get_ports {link_in[49]}] -set_input_transition -min 0.069 [get_ports {link_in[49]}] -set_input_transition -max 0.069 [get_ports {link_in[48]}] -set_input_transition -min 0.069 [get_ports {link_in[48]}] -set_input_transition -max 0.069 [get_ports {link_in[47]}] -set_input_transition -min 0.069 [get_ports {link_in[47]}] -set_input_transition -max 0.069 [get_ports {link_in[46]}] -set_input_transition -min 0.069 [get_ports {link_in[46]}] -set_input_transition -max 0.069 [get_ports {link_in[45]}] -set_input_transition -min 0.069 [get_ports {link_in[45]}] -set_input_transition -max 0.069 [get_ports {link_in[44]}] -set_input_transition -min 0.069 [get_ports {link_in[44]}] -set_input_transition -max 0.069 [get_ports {link_in[43]}] -set_input_transition -min 0.069 [get_ports {link_in[43]}] -set_input_transition -max 0.069 [get_ports {link_in[42]}] -set_input_transition -min 0.069 [get_ports {link_in[42]}] -set_input_transition -max 0.069 [get_ports {link_in[41]}] -set_input_transition -min 0.069 [get_ports {link_in[41]}] -set_input_transition -max 0.069 [get_ports {link_in[40]}] -set_input_transition -min 0.069 [get_ports {link_in[40]}] -set_input_transition -max 0.069 [get_ports {link_in[39]}] -set_input_transition -min 0.069 [get_ports {link_in[39]}] -set_input_transition -max 0.069 [get_ports {link_in[38]}] -set_input_transition -min 0.069 [get_ports {link_in[38]}] -set_input_transition -max 0.069 [get_ports {link_in[37]}] -set_input_transition -min 0.069 [get_ports {link_in[37]}] -set_input_transition -max 0.069 [get_ports {link_in[36]}] -set_input_transition -min 0.069 [get_ports {link_in[36]}] -set_input_transition -max 0.069 [get_ports {link_in[35]}] -set_input_transition -min 0.069 [get_ports {link_in[35]}] -set_input_transition -max 0.069 [get_ports {link_in[34]}] -set_input_transition -min 0.069 [get_ports {link_in[34]}] -set_input_transition -max 0.069 [get_ports {link_in[33]}] -set_input_transition -min 0.069 [get_ports {link_in[33]}] -set_input_transition -max 0.069 [get_ports {link_in[32]}] -set_input_transition -min 0.069 [get_ports {link_in[32]}] -set_input_transition -max 0.069 [get_ports {link_in[31]}] -set_input_transition -min 0.069 [get_ports {link_in[31]}] -set_input_transition -max 0.069 [get_ports {link_in[30]}] -set_input_transition -min 0.069 [get_ports {link_in[30]}] -set_input_transition -max 0.069 [get_ports {link_in[29]}] -set_input_transition -min 0.069 [get_ports {link_in[29]}] -set_input_transition -max 0.069 [get_ports {link_in[28]}] -set_input_transition -min 0.069 [get_ports {link_in[28]}] -set_input_transition -max 0.069 [get_ports {link_in[27]}] -set_input_transition -min 0.069 [get_ports {link_in[27]}] -set_input_transition -max 0.069 [get_ports {link_in[26]}] -set_input_transition -min 0.069 [get_ports {link_in[26]}] -set_input_transition -max 0.069 [get_ports {link_in[25]}] -set_input_transition -min 0.069 [get_ports {link_in[25]}] -set_input_transition -max 0.069 [get_ports {link_in[24]}] -set_input_transition -min 0.069 [get_ports {link_in[24]}] -set_input_transition -max 0.069 [get_ports {link_in[23]}] -set_input_transition -min 0.069 [get_ports {link_in[23]}] -set_input_transition -max 0.069 [get_ports {link_in[22]}] -set_input_transition -min 0.069 [get_ports {link_in[22]}] -set_input_transition -max 0.069 [get_ports {link_in[21]}] -set_input_transition -min 0.069 [get_ports {link_in[21]}] -set_input_transition -max 0.069 [get_ports {link_in[20]}] -set_input_transition -min 0.069 [get_ports {link_in[20]}] -set_input_transition -max 0.069 [get_ports {link_in[19]}] -set_input_transition -min 0.069 [get_ports {link_in[19]}] -set_input_transition -max 0.069 [get_ports {link_in[18]}] -set_input_transition -min 0.069 [get_ports {link_in[18]}] -set_input_transition -max 0.069 [get_ports {link_in[17]}] -set_input_transition -min 0.069 [get_ports {link_in[17]}] -set_input_transition -max 0.069 [get_ports {link_in[16]}] -set_input_transition -min 0.069 [get_ports {link_in[16]}] -set_input_transition -max 0.069 [get_ports {link_in[15]}] -set_input_transition -min 0.069 [get_ports {link_in[15]}] -set_input_transition -max 0.069 [get_ports {link_in[14]}] -set_input_transition -min 0.069 [get_ports {link_in[14]}] -set_input_transition -max 0.069 [get_ports {link_in[13]}] -set_input_transition -min 0.069 [get_ports {link_in[13]}] -set_input_transition -max 0.069 [get_ports {link_in[12]}] -set_input_transition -min 0.069 [get_ports {link_in[12]}] -set_input_transition -max 0.069 [get_ports {link_in[11]}] -set_input_transition -min 0.069 [get_ports {link_in[11]}] -set_input_transition -max 0.069 [get_ports {link_in[10]}] -set_input_transition -min 0.069 [get_ports {link_in[10]}] -set_input_transition -max 0.069 [get_ports {link_in[9]}] -set_input_transition -min 0.069 [get_ports {link_in[9]}] -set_input_transition -max 0.069 [get_ports {link_in[8]}] -set_input_transition -min 0.069 [get_ports {link_in[8]}] -set_input_transition -max 0.069 [get_ports {link_in[7]}] -set_input_transition -min 0.069 [get_ports {link_in[7]}] -set_input_transition -max 0.069 [get_ports {link_in[6]}] -set_input_transition -min 0.069 [get_ports {link_in[6]}] -set_input_transition -max 0.069 [get_ports {link_in[5]}] -set_input_transition -min 0.069 [get_ports {link_in[5]}] -set_input_transition -max 0.069 [get_ports {link_in[4]}] -set_input_transition -min 0.069 [get_ports {link_in[4]}] -set_input_transition -max 0.069 [get_ports {link_in[3]}] -set_input_transition -min 0.069 [get_ports {link_in[3]}] -set_input_transition -max 0.069 [get_ports {link_in[2]}] -set_input_transition -min 0.069 [get_ports {link_in[2]}] -set_input_transition -max 0.069 [get_ports {link_in[1]}] -set_input_transition -min 0.069 [get_ports {link_in[1]}] -set_input_transition -max 0.069 [get_ports {link_in[0]}] -set_input_transition -min 0.069 [get_ports {link_in[0]}] -set_input_transition -max 0.069 [get_ports {my_x_i[3]}] -set_input_transition -min 0.069 [get_ports {my_x_i[3]}] -set_input_transition -max 0.069 [get_ports {my_x_i[2]}] -set_input_transition -min 0.069 [get_ports {my_x_i[2]}] -set_input_transition -max 0.069 [get_ports {my_x_i[1]}] -set_input_transition -min 0.069 [get_ports {my_x_i[1]}] -set_input_transition -max 0.069 [get_ports {my_x_i[0]}] -set_input_transition -min 0.069 [get_ports {my_x_i[0]}] -set_input_transition -max 0.069 [get_ports {my_y_i[4]}] -set_input_transition -min 0.069 [get_ports {my_y_i[4]}] -set_input_transition -max 0.069 [get_ports {my_y_i[3]}] -set_input_transition -min 0.069 [get_ports {my_y_i[3]}] -set_input_transition -max 0.069 [get_ports {my_y_i[2]}] -set_input_transition -min 0.069 [get_ports {my_y_i[2]}] -set_input_transition -max 0.069 [get_ports {my_y_i[1]}] -set_input_transition -min 0.069 [get_ports {my_y_i[1]}] -set_input_transition -max 0.069 [get_ports {my_y_i[0]}] -set_input_transition -min 0.069 [get_ports {my_y_i[0]}] diff --git a/flow/designs/tsmc65lp/vanilla5/metadata-base-ok.json b/flow/designs/tsmc65lp/vanilla5/metadata-base-ok.json deleted file mode 100644 index 4a11661cee..0000000000 --- a/flow/designs/tsmc65lp/vanilla5/metadata-base-ok.json +++ /dev/null @@ -1,354 +0,0 @@ -{ - "constraints__clocks__count": 1, - "constraints__clocks__details": [ - "core_clk: 8.0000" - ], - "cts__clock__skew__hold": 0.155967, - "cts__clock__skew__hold__post_repair": 0.156257, - "cts__clock__skew__hold__pre_repair": 0.156257, - "cts__clock__skew__setup": 0.27008, - "cts__clock__skew__setup__post_repair": 0.27037, - "cts__clock__skew__setup__pre_repair": 0.27037, - "cts__cpu__total": 18.03, - "cts__design__core__area": 409536, - "cts__design__core__area__post_repair": 409536, - "cts__design__core__area__pre_repair": 409536, - "cts__design__die__area": 440880, - "cts__design__die__area__post_repair": 440880, - "cts__design__die__area__pre_repair": 440880, - "cts__design__instance__area": 192986, - "cts__design__instance__area__macros": 64603.9, - "cts__design__instance__area__macros__post_repair": 64603.9, - "cts__design__instance__area__macros__pre_repair": 64603.9, - "cts__design__instance__area__post_repair": 192986, - "cts__design__instance__area__pre_repair": 192986, - "cts__design__instance__area__stdcell": 128382, - "cts__design__instance__area__stdcell__post_repair": 128382, - "cts__design__instance__area__stdcell__pre_repair": 128382, - "cts__design__instance__count": 18446, - "cts__design__instance__count__hold_buffer": 0, - "cts__design__instance__count__macros": 4, - "cts__design__instance__count__macros__post_repair": 4, - "cts__design__instance__count__macros__pre_repair": 4, - "cts__design__instance__count__post_repair": 18446, - "cts__design__instance__count__pre_repair": 18446, - "cts__design__instance__count__setup_buffer": 0, - "cts__design__instance__count__stdcell": 18442, - "cts__design__instance__count__stdcell__post_repair": 18442, - "cts__design__instance__count__stdcell__pre_repair": 18442, - "cts__design__instance__displacement__max": 0, - "cts__design__instance__displacement__mean": 0, - "cts__design__instance__displacement__total": 0, - "cts__design__instance__utilization": 0.47123, - "cts__design__instance__utilization__post_repair": 0.47123, - "cts__design__instance__utilization__pre_repair": 0.47123, - "cts__design__instance__utilization__stdcell": 0.372194, - "cts__design__instance__utilization__stdcell__post_repair": 0.372194, - "cts__design__instance__utilization__stdcell__pre_repair": 0.372194, - "cts__design__io": 723, - "cts__design__io__post_repair": 723, - "cts__design__io__pre_repair": 723, - "cts__design__violations": 0, - "cts__mem__peak": 449176.0, - "cts__power__internal__total": 9.79332e-05, - "cts__power__internal__total__post_repair": 9.79335e-05, - "cts__power__internal__total__pre_repair": 9.79335e-05, - "cts__power__leakage__total": 0.000140348, - "cts__power__leakage__total__post_repair": 0.000140348, - "cts__power__leakage__total__pre_repair": 0.000140348, - "cts__power__switching__total": 7.8039e-05, - "cts__power__switching__total__post_repair": 7.80356e-05, - "cts__power__switching__total__pre_repair": 7.80356e-05, - "cts__power__total": 0.00031632, - "cts__power__total__post_repair": 0.000316317, - "cts__power__total__pre_repair": 0.000316317, - "cts__route__wirelength__estimated": 562635, - "cts__runtime__total": "0:18.46", - "cts__timing__drv__hold_violation_count": 3, - "cts__timing__drv__hold_violation_count__post_repair": 3, - "cts__timing__drv__hold_violation_count__pre_repair": 3, - "cts__timing__drv__max_cap": 0, - "cts__timing__drv__max_cap__post_repair": 0, - "cts__timing__drv__max_cap__pre_repair": 0, - "cts__timing__drv__max_cap_limit": 0.945326, - "cts__timing__drv__max_cap_limit__post_repair": 0.947111, - "cts__timing__drv__max_cap_limit__pre_repair": 0.947111, - "cts__timing__drv__max_fanout": 83, - "cts__timing__drv__max_fanout__post_repair": 83, - "cts__timing__drv__max_fanout__pre_repair": 83, - "cts__timing__drv__max_fanout_limit": 12, - "cts__timing__drv__max_fanout_limit__post_repair": 12, - "cts__timing__drv__max_fanout_limit__pre_repair": 12, - "cts__timing__drv__max_slew": 3160, - "cts__timing__drv__max_slew__post_repair": 3081, - "cts__timing__drv__max_slew__pre_repair": 3081, - "cts__timing__drv__max_slew_limit": -19.8425, - "cts__timing__drv__max_slew_limit__post_repair": -19.841, - "cts__timing__drv__max_slew_limit__pre_repair": -19.841, - "cts__timing__drv__setup_violation_count": 0, - "cts__timing__drv__setup_violation_count__post_repair": 0, - "cts__timing__drv__setup_violation_count__pre_repair": 0, - "cts__timing__setup__tns": 0, - "cts__timing__setup__tns__post_repair": 0, - "cts__timing__setup__tns__pre_repair": 0, - "cts__timing__setup__ws": 3.2267, - "cts__timing__setup__ws__post_repair": 3.23799, - "cts__timing__setup__ws__pre_repair": 3.23799, - "design__io__hpwl": 156676237, - "detailedplace__cpu__total": 14.28, - "detailedplace__design__core__area": 409536, - "detailedplace__design__die__area": 440880, - "detailedplace__design__instance__area": 191386, - "detailedplace__design__instance__area__macros": 64603.9, - "detailedplace__design__instance__area__stdcell": 126782, - "detailedplace__design__instance__count": 18348, - "detailedplace__design__instance__count__macros": 4, - "detailedplace__design__instance__count__stdcell": 18344, - "detailedplace__design__instance__displacement__max": 48.5, - "detailedplace__design__instance__displacement__mean": 3.0425, - "detailedplace__design__instance__displacement__total": 55826.9, - "detailedplace__design__instance__utilization": 0.467325, - "detailedplace__design__instance__utilization__stdcell": 0.367558, - "detailedplace__design__io": 723, - "detailedplace__design__violations": 0, - "detailedplace__mem__peak": 419900.0, - "detailedplace__power__internal__total": 0.00411216, - "detailedplace__power__leakage__total": 0.000125683, - "detailedplace__power__switching__total": 0.0136291, - "detailedplace__power__total": 0.0178669, - "detailedplace__route__wirelength__estimated": 573262, - "detailedplace__runtime__total": "0:14.59", - "detailedplace__timing__drv__hold_violation_count": 6, - "detailedplace__timing__drv__max_cap": 0, - "detailedplace__timing__drv__max_cap_limit": 0.947111, - "detailedplace__timing__drv__max_fanout": 0, - "detailedplace__timing__drv__max_fanout_limit": 12, - "detailedplace__timing__drv__max_slew": 2987, - "detailedplace__timing__drv__max_slew_limit": -19.841, - "detailedplace__timing__drv__setup_violation_count": 0, - "detailedplace__timing__setup__tns": 0, - "detailedplace__timing__setup__ws": 1.84568, - "detailedroute__cpu__total": 702.82, - "detailedroute__mem__peak": 2388560.0, - "detailedroute__route__drc_errors": 0, - "detailedroute__route__drc_errors__iter:1": 3997, - "detailedroute__route__drc_errors__iter:2": 127, - "detailedroute__route__drc_errors__iter:3": 35, - "detailedroute__route__drc_errors__iter:4": 0, - "detailedroute__route__net": 17557, - "detailedroute__route__net__special": 2, - "detailedroute__route__vias": 111924, - "detailedroute__route__vias__multicut": 0, - "detailedroute__route__vias__singlecut": 111924, - "detailedroute__route__wirelength": 631800, - "detailedroute__route__wirelength__iter:1": 633853, - "detailedroute__route__wirelength__iter:2": 631885, - "detailedroute__route__wirelength__iter:3": 631809, - "detailedroute__route__wirelength__iter:4": 631800, - "detailedroute__runtime__total": "0:39.31", - "fillcell__cpu__total": 3.21, - "fillcell__mem__peak": 389072.0, - "fillcell__runtime__total": "0:03.47", - "finish__clock__skew__hold": 0.114112, - "finish__clock__skew__setup": 0.191697, - "finish__cpu__total": 16.76, - "finish__design__core__area": 409536, - "finish__design__die__area": 440880, - "finish__design__instance__area": 196370, - "finish__design__instance__area__macros": 64603.9, - "finish__design__instance__area__stdcell": 131766, - "finish__design__instance__count": 19156, - "finish__design__instance__count__macros": 4, - "finish__design__instance__count__stdcell": 19152, - "finish__design__instance__utilization": 0.479494, - "finish__design__instance__utilization__stdcell": 0.382006, - "finish__design__io": 723, - "finish__mem__peak": 697536.0, - "finish__power__internal__total": 9.66525e-05, - "finish__power__leakage__total": 0.000144127, - "finish__power__switching__total": 4.95536e-05, - "finish__power__total": 0.000290333, - "finish__runtime__total": "0:18.00", - "finish__timing__drv__hold_violation_count": 4, - "finish__timing__drv__max_cap": 0, - "finish__timing__drv__max_cap_limit": 0.964667, - "finish__timing__drv__max_fanout": 0, - "finish__timing__drv__max_fanout_limit": 12, - "finish__timing__drv__max_slew": 3454, - "finish__timing__drv__max_slew_limit": -21.0255, - "finish__timing__drv__setup_violation_count": 0, - "finish__timing__setup__tns": 0, - "finish__timing__setup__ws": 3.38196, - "finish__timing__wns_percent_delay": 79.185203, - "finish_merge__cpu__total": 6.43, - "finish_merge__mem__peak": 661132.0, - "finish_merge__runtime__total": "0:06.93", - "floorplan__cpu__total": 5.85, - "floorplan__design__core__area": 409536, - "floorplan__design__die__area": 440880, - "floorplan__design__instance__area": 137079, - "floorplan__design__instance__area__macros": 64603.9, - "floorplan__design__instance__area__stdcell": 72474.7, - "floorplan__design__instance__count": 11145, - "floorplan__design__instance__count__macros": 4, - "floorplan__design__instance__count__stdcell": 11141, - "floorplan__design__instance__utilization": 0.334717, - "floorplan__design__instance__utilization__stdcell": 0.210113, - "floorplan__design__io": 723, - "floorplan__mem__peak": 364784.0, - "floorplan__power__internal__total": 0.0032858, - "floorplan__power__leakage__total": 6.49171e-05, - "floorplan__power__switching__total": 0.0127637, - "floorplan__power__total": 0.0161144, - "floorplan__runtime__total": "0:06.10", - "floorplan__timing__setup__tns": -1019.09, - "floorplan__timing__setup__ws": -8.40701, - "floorplan_io__cpu__total": 2.99, - "floorplan_io__mem__peak": 330564.0, - "floorplan_io__runtime__total": "0:03.18", - "floorplan_macro__cpu__total": 598.52, - "floorplan_macro__mem__peak": 443868.0, - "floorplan_macro__runtime__total": "6:47.98", - "floorplan_pdn__cpu__total": 3.52, - "floorplan_pdn__mem__peak": 360868.0, - "floorplan_pdn__runtime__total": "0:03.72", - "floorplan_tap__cpu__total": 3.04, - "floorplan_tap__mem__peak": 323240.0, - "floorplan_tap__runtime__total": "0:03.22", - "globalplace__cpu__total": 94.04, - "globalplace__design__core__area": 409536, - "globalplace__design__die__area": 440880, - "globalplace__design__instance__area": 139085, - "globalplace__design__instance__area__macros": 64603.9, - "globalplace__design__instance__area__stdcell": 74481.1, - "globalplace__design__instance__count": 13235, - "globalplace__design__instance__count__macros": 4, - "globalplace__design__instance__count__stdcell": 13231, - "globalplace__design__instance__utilization": 0.339616, - "globalplace__design__instance__utilization__stdcell": 0.21593, - "globalplace__design__io": 723, - "globalplace__mem__peak": 585184.0, - "globalplace__power__internal__total": 0.00335339, - "globalplace__power__leakage__total": 6.49171e-05, - "globalplace__power__switching__total": 0.0131306, - "globalplace__power__total": 0.0165489, - "globalplace__runtime__total": "1:04.45", - "globalplace__timing__setup__tns": -2118.93, - "globalplace__timing__setup__ws": -8.73259, - "globalplace_io__cpu__total": 3.0, - "globalplace_io__mem__peak": 336168.0, - "globalplace_io__runtime__total": "0:03.22", - "globalplace_skip_io__cpu__total": 5.84, - "globalplace_skip_io__mem__peak": 347672.0, - "globalplace_skip_io__runtime__total": "0:06.11", - "globalroute__antenna__violating__nets": 0, - "globalroute__antenna__violating__pins": 0, - "globalroute__clock__skew__hold": 0.157952, - "globalroute__clock__skew__setup": 0.272065, - "globalroute__cpu__total": 34.71, - "globalroute__design__core__area": 409536, - "globalroute__design__die__area": 440880, - "globalroute__design__instance__area": 196370, - "globalroute__design__instance__area__macros": 64603.9, - "globalroute__design__instance__area__stdcell": 131766, - "globalroute__design__instance__count": 19156, - "globalroute__design__instance__count__hold_buffer": 0, - "globalroute__design__instance__count__macros": 4, - "globalroute__design__instance__count__setup_buffer": 0, - "globalroute__design__instance__count__stdcell": 19152, - "globalroute__design__instance__displacement__max": 0, - "globalroute__design__instance__displacement__mean": 0, - "globalroute__design__instance__displacement__total": 0, - "globalroute__design__instance__utilization": 0.479494, - "globalroute__design__instance__utilization__stdcell": 0.382006, - "globalroute__design__io": 723, - "globalroute__design__violations": 0, - "globalroute__mem__peak": 755772.0, - "globalroute__power__internal__total": 9.76494e-05, - "globalroute__power__leakage__total": 0.000144103, - "globalroute__power__switching__total": 7.96264e-05, - "globalroute__power__total": 0.000321379, - "globalroute__route__wirelength__estimated": 578734, - "globalroute__runtime__total": "0:39.76", - "globalroute__timing__clock__slack": 3.166, - "globalroute__timing__drv__hold_violation_count": 4, - "globalroute__timing__drv__max_cap": 0, - "globalroute__timing__drv__max_cap_limit": 0.957725, - "globalroute__timing__drv__max_fanout": 0, - "globalroute__timing__drv__max_fanout_limit": 12, - "globalroute__timing__drv__max_slew": 4770, - "globalroute__timing__drv__max_slew_limit": -21.603, - "globalroute__timing__drv__setup_violation_count": 0, - "globalroute__timing__setup__tns": 0, - "globalroute__timing__setup__ws": 3.16597, - "placeopt__cpu__total": 15.78, - "placeopt__design__core__area": 409536, - "placeopt__design__core__area__pre_opt": 409536, - "placeopt__design__die__area": 440880, - "placeopt__design__die__area__pre_opt": 440880, - "placeopt__design__instance__area": 191386, - "placeopt__design__instance__area__macros": 64603.9, - "placeopt__design__instance__area__macros__pre_opt": 64603.9, - "placeopt__design__instance__area__pre_opt": 139085, - "placeopt__design__instance__area__stdcell": 126782, - "placeopt__design__instance__area__stdcell__pre_opt": 74481.1, - "placeopt__design__instance__count": 18348, - "placeopt__design__instance__count__macros": 4, - "placeopt__design__instance__count__macros__pre_opt": 4, - "placeopt__design__instance__count__pre_opt": 13235, - "placeopt__design__instance__count__stdcell": 18344, - "placeopt__design__instance__count__stdcell__pre_opt": 13231, - "placeopt__design__instance__utilization": 0.467325, - "placeopt__design__instance__utilization__pre_opt": 0.339616, - "placeopt__design__instance__utilization__stdcell": 0.367558, - "placeopt__design__instance__utilization__stdcell__pre_opt": 0.21593, - "placeopt__design__io": 723, - "placeopt__design__io__pre_opt": 723, - "placeopt__mem__peak": 414840.0, - "placeopt__power__internal__total": 0.00372039, - "placeopt__power__internal__total__pre_opt": 0.00335339, - "placeopt__power__leakage__total": 0.000124698, - "placeopt__power__leakage__total__pre_opt": 6.49171e-05, - "placeopt__power__switching__total": 0.000769801, - "placeopt__power__switching__total__pre_opt": 0.0131306, - "placeopt__power__total": 0.00461489, - "placeopt__power__total__pre_opt": 0.0165489, - "placeopt__runtime__total": "0:16.18", - "placeopt__timing__drv__floating__nets": 0, - "placeopt__timing__drv__floating__pins": 3, - "placeopt__timing__drv__hold_violation_count": 6, - "placeopt__timing__drv__max_cap": 0, - "placeopt__timing__drv__max_cap_limit": 0.9643, - "placeopt__timing__drv__max_fanout": 0, - "placeopt__timing__drv__max_fanout_limit": 12, - "placeopt__timing__drv__max_slew": 2869, - "placeopt__timing__drv__max_slew_limit": -19.2127, - "placeopt__timing__drv__setup_violation_count": 0, - "placeopt__timing__setup__tns": -0.00219913, - "placeopt__timing__setup__tns__pre_opt": -2118.93, - "placeopt__timing__setup__ws": 1.84617, - "placeopt__timing__setup__ws__pre_opt": -8.73259, - "run__flow__design": "vanilla5", - "run__flow__generate_date": "2024-03-17 22:44", - "run__flow__metrics_version": "Metrics_2.1.2", - "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-12608-g50753a4c5", - "run__flow__platform": "tsmc65lp", - "run__flow__platform__capacitance_units": "1pF", - "run__flow__platform__current_units": "1mA", - "run__flow__platform__distance_units": "1um", - "run__flow__platform__power_units": "1uW", - "run__flow__platform__resistance_units": "1kohm", - "run__flow__platform__time_units": "1ns", - "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "730fc586e5c9b66fa3a4f855f18f25797b654914", - "run__flow__scripts_commit": "12c7d2e07c59991900627e30a4c3ed0a657448f8", - "run__flow__uuid": "00dcc2f8-5fd4-4b5a-b5cd-84916072f40f", - "run__flow__variant": "base", - "synth__cpu__total": 54.15, - "synth__design__instance__area__stdcell": 142008.6506, - "synth__design__instance__count__stdcell": 12354.0, - "synth__mem__peak": 275552.0, - "synth__runtime__total": "0:54.81", - "total_time": "0:11:49.490000" -} \ No newline at end of file diff --git a/flow/platforms/asap7/config.mk b/flow/platforms/asap7/config.mk index 3e4d965336..2b5c568fec 100644 --- a/flow/platforms/asap7/config.mk +++ b/flow/platforms/asap7/config.mk @@ -1,68 +1,16 @@ export PLATFORM = asap7 export PROCESS = 7 +export ASAP7_USE_VT ?= RVT ifeq ($(LIB_MODEL),) export LIB_MODEL = NLDM endif export LIB_DIR ?= $(PLATFORM_DIR)/lib/$(LIB_MODEL) +export PLATFORM_TCL = $(PLATFORM_DIR)/liberty_suppressions.tcl + #Library Setup variable export TECH_LEF = $(PLATFORM_DIR)/lef/asap7_tech_1x_201209.lef -export SC_LEF = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_R_1x_220121a.lef - -export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_R_220121a.gds \ - $(ADDITIONAL_GDS) - -export BC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib \ - $(BC_ADDITIONAL_LIBS) - -export BC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib - -export BC_CCS_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_RVT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_FF_ccs_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_FF_ccs_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib \ - $(BC_ADDITIONAL_LIBS) - -export BC_CCS_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_FF_ccs_220123.lib - -export WC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_RVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_SS_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz \ - $(WC_ADDITIONAL_LIBS) - -export WC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib - -export TC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_RVT_TT_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_RVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz \ - $(TC_ADDITIONAL_LIBS) - -export TC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib - -ifdef CLUSTER_FLOPS - # Add the multi-bit FF for clustering. These are single corner libraries. - export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_RVT_TT_nldm_FAKE.lib \ - $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_RVT_TT_nldm_FAKE.lib -# $(LIB_DIR)/asap7sc7p5t_DFFHQNV4X_RVT_TT_nldm_FAKE.lib - - export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \ - $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef -# $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV4X.lef - export ADDITIONAL_SITES += asap7sc7p5t_pg - export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].* -endif - - export BC_TEMPERATURE = 25C export TC_TEMPERATURE = 0C @@ -77,24 +25,11 @@ export WC_VOLTAGE = 0.63 export DONT_USE_CELLS = *x1p*_ASAP7* *xp*_ASAP7* export DONT_USE_CELLS += SDF* ICG* -# Yosys mapping files -export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_R.v -export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_R.v -export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_R.v -export MAX_UNGROUP_SIZE ?= 100 - -export ABC_DRIVER_CELL = BUFx2_ASAP7_75t_R +export SYNTH_MINIMUM_KEEP_SIZE ?= 1000 # BUF_X1, pin (A) = 0.974659. Arbitrarily multiply by 4 export ABC_LOAD_IN_FF = 3.898 -# Set the TIEHI/TIELO cells -# These are used in yosys synthesis to avoid logical 1/0's in the netlist -export TIEHI_CELL_AND_PORT = TIEHIx1_ASAP7_75t_R H -export TIELO_CELL_AND_PORT = TIELOx1_ASAP7_75t_R L - -# Used in synthesis -export MIN_BUF_CELL_AND_PORTS = BUFx2_ASAP7_75t_R A Y # Placement site for core cells # This can be found in the technology lef @@ -115,36 +50,31 @@ export IO_PLACER_H ?= M4 export IO_PLACER_V ?= M5 export MACRO_PLACE_HALO ?= 10 10 -export MACRO_PLACE_CHANNEL ?= 12 12 # the followings create a keep out / halo between # macro and core rows -export MACRO_HALO_X ?= 2 -export MACRO_HALO_Y ?= 2 +export MACRO_ROWS_HALO_X ?= 2 +export MACRO_ROWS_HALO_Y ?= 2 export PLACE_DENSITY ?= 0.60 # Endcap and Welltie cells export TAPCELL_TCL ?= $(PLATFORM_DIR)/openRoad/tapcell.tcl -# Fill cells used in fill cell insertion -export FILL_CELLS ?= FILLERxp5_ASAP7_75t_R \ - FILLER_ASAP7_75t_R \ - DECAPx1_ASAP7_75t_R \ - DECAPx2_ASAP7_75t_R \ - DECAPx4_ASAP7_75t_R \ - DECAPx6_ASAP7_75t_R \ - DECAPx10_ASAP7_75t_R - -export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_R - export SET_RC_TCL = $(PLATFORM_DIR)/setRC.tcl # Route options export MIN_ROUTING_LAYER ?= M2 -#export MIN_CLOCK_ROUTING_LAYER = M4 +export MIN_CLK_ROUTING_LAYER ?= M4 export MAX_ROUTING_LAYER ?= M7 +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 + +# Define fastRoute tcl +export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl + # KLayout technology file export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/KLayout/asap7.lyt @@ -154,104 +84,113 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc # OpenRCX extRules export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules -# XS - defining function for using LVT -ifeq ($(ASAP7_USELVT), 1) - export TIEHI_CELL_AND_PORT = TIEHIx1_ASAP7_75t_L H - export TIELO_CELL_AND_PORT = TIELOx1_ASAP7_75t_L L - - export MIN_BUF_CELL_AND_PORTS = BUFx2_ASAP7_75t_L A Y - - export HOLD_BUF_CELL = BUFx2_ASAP7_75t_L - - export ABC_DRIVER_CELL = BUFx2_ASAP7_75t_L - - export FILL_CELLS ?= "FILLERxp5_ASAP7_75t_L" - - export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_L - - export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds \ - $(ADDITIONAL_GDS) - - export SC_LEF = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef +# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates +export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib +export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib +export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib +export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib +export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz +export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \ + $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \ + $(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz +export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \ + FILLER_ASAP7_75t_ \ + DECAPx1_ASAP7_75t_ \ + DECAPx2_ASAP7_75t_ \ + DECAPx4_ASAP7_75t_ \ + DECAPx6_ASAP7_75t_ \ + DECAPx10_ASAP7_75t_ + +# Default to RVT if unset +export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT) + +# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT +export PRIMARY_VT = $(word 1, $(VT_LIST)) +export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT))) +export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST)) + +## Set cells based on the primary VT first +# Set the TIEHI/TIELO cells +# These are used in yosys synthesis to avoid logical 1/0's in the netlist +export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H +export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L - export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_L.v - export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_L.v - export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_L.v +# Used in synthesis +export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y - export BC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib +export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) - export BC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib +export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) - export WC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_SS_nldm_220123.lib +# Fill cells used in fill cell insertion +export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T)) - export WC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_LVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_SS_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_SS_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_SS_nldm_211120.lib.gz +export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG) - export TC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_TT_nldm_220123.lib +# GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile +export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds - export TC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_LVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_TT_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_LVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_TT_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_TT_nldm_211120.lib.gz +export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef +# Yosys mapping files +export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v +export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v +export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v + +export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T)) +export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T)) +export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \ + $(BC_ADDITIONAL_LIBS) +export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T)) + +export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T)) +export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T)) + +export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T)) +export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T)) + +ifeq ($(CLUSTER_FLOPS),1) + # Add the multi-bit FF for clustering. These are single corner libraries. + export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \ + $(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib + + export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \ + $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef + export ADDITIONAL_SITES += asap7sc7p5t_pg + export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].* endif -ifeq ($(ASAP7_USESLVT), 1) - export TIEHI_CELL_AND_PORT = TIEHIx1_ASAP7_75t_SL H - export TIELO_CELL_AND_PORT = TIELOx1_ASAP7_75t_SL L - - export MIN_BUF_CELL_AND_PORTS = BUFx2_ASAP7_75t_SL A Y - - export HOLD_BUF_CELL = BUFx2_ASAP7_75t_SL - - export ABC_DRIVER_CELL = BUFx2_ASAP7_75t_SL - - export FILL_CELLS ?= "FILLERxp5_ASAP7_75t_SL" - - export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_SL - - export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_SL_220121a.gds \ - $(ADDITIONAL_GDS) - - export SC_LEF = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_SL_1x_220121a.lef - - export LATCH_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_latch_SL.v - export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/yoSys/cells_clkgate_SL.v - export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_SL.v - - export BC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib - - export BC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_SLVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_SLVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib - - export WC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_SS_nldm_220123.lib - - export WC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_SLVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_SLVT_SS_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_SLVT_SS_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_SS_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_SLVT_SS_nldm_211120.lib.gz - - export TC_NLDM_DFF_LIB_FILE = $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_TT_nldm_220123.lib - - export TC_NLDM_LIB_FILES = $(LIB_DIR)/asap7sc7p5t_AO_SLVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_INVBUF_SLVT_TT_nldm_220122.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_OA_SLVT_TT_nldm_211120.lib.gz \ - $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_TT_nldm_220123.lib \ - $(LIB_DIR)/asap7sc7p5t_SIMPLE_SLVT_TT_nldm_211120.lib.gz - -endif +### Add additional files to the variables based on the OTHER_VT list +$(foreach vt_type,$(OTHER_VT),\ + $(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \ + $(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \ + $(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \ + $(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \ + $(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \ + $(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \ + $(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \ + $(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \ + $(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \ + $(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \ + $(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \ +) # Dont use SC library based on CORNER selection # @@ -261,9 +200,14 @@ endif export CORNER ?= BC export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES) export LIB_FILES += $(ADDITIONAL_LIBS) +export GDS_FILES += $(ADDITIONAL_GDS) export DB_FILES += $(realpath $($(CORNER)_DB_FILES)) export TEMPERATURE = $($(CORNER)_TEMPERATURE) export VOLTAGE = $($(CORNER)_VOLTAGE) + +# FIXME Need merged.lib for now, but ideally it shouldn't be necessary: +# +# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/2139 export DONT_USE_SC_LIB = $(OBJECTS_DIR)/lib/merged.lib # --------------------------------------------------------- @@ -272,8 +216,8 @@ export DONT_USE_SC_LIB = $(OBJECTS_DIR)/lib/merged.lib # IR drop estimation supply net name to be analyzed and supply voltage variable # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD $(VOLTAGE)" -export GND_NETS_VOLTAGES ?= "VSS 0.0" +export PWR_NETS_VOLTAGES ?= VDD $(VOLTAGE) +export GND_NETS_VOLTAGES ?= VSS 0.0 export IR_DROP_LAYER ?= M1 # Allow empty GDS cell diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc index e7ca24cb2b..2cf14c10c8 100644 --- a/flow/platforms/asap7/constraints.sdc +++ b/flow/platforms/asap7/constraints.sdc @@ -1,6 +1,6 @@ # A minimal generic constraints.sdc for architectural exploration of macros # ------------------------------------------------------------------------- -# +# # Used in designs/asap7/mock-array, for example. # # From the following observations, all else follows: the only thing @@ -8,7 +8,7 @@ # other constraints give the flow an optimization target. Failure # to meet the timing constraint of an optimization target constraint # is not a timing closure failure. -# +# # Note that ORFS regression checks do not have the ability to distinguish # between timing closure failures(register to register paths) and # optimization constraints violations. @@ -17,26 +17,26 @@ # in mock-array Element, such as maximum transit time for a combinational path # through mock-array Element, may or may not cause timing # violations later on higher up in mock-array on register to register paths. -# +# # For the Element, the only register to register path # are within the Element and no lower level macros are # involved. Register to register paths within Element have to be checked # at the Element level as they are invisible higher up in mock-array. -# +# # As for the remaining optimization constraints for Element, they # should be for combinational through paths(io-io) and # from input pins to register(io-reg) and from register to output pins(reg-io): -# +# # This constraints.sdc file is designed such that the clock latency & tree # can be ignored as far constraints go; # it is not part of the optimization constraints. The clock tree latency # is accounted for in register to register paths and not visible outside # of the macro that use this constraints.sdc. -# +# # All non reg-reg paths in Element are part of reg-reg paths in mock-array # and timing closure in which those take part are checked at the mock-array # level. -# +# # With this in mind, the constraints.sdc file for the Element becomes # quite general and simple. set_max_delay is used exclusively for # optimization constraints and the clock period is used to check timing @@ -51,13 +51,13 @@ # the time at the clock pin for the macro, which makes it impossible to articulate # the number that is passed in to set_input/output_delay without taking # clock network insertion latency into account. -# +# # Since set_input_delay is not used and set_max_delay is used instead, then # no hold cells are inserted, which is what is desired here. # # Details such as clock uncertainty, max transition time, load, etc. # is beyond the scope of this generic constraints.sdc file. -# +# # Beware of [path segmentation](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation), which # can occur with OpenSTA. @@ -69,17 +69,21 @@ set sdc_version 2.0 set clk_port [get_ports $clk_port_name] create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port -set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] -set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] +set non_clk_inputs [all_inputs -no_clocks] # Optimization targets: overconstrain by default and # leave refinements to a more design specific constraints.sdc file. # -# Minimum time for io-io, io-reg, reg-io paths in macro is on -# the order of 80ps for a small macro on ASAP7. -set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] -set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] -set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] +# Minimum time, excluding clock latency, for io-io, io-reg, reg-io +# paths in macro is on the order of 80ps for a small macro on ASAP7. +set_max_delay -ignore_clock_latency \ + [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs \ + -to [all_registers] +set_max_delay -ignore_clock_latency \ + [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] \ + -to [all_outputs] +set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs \ + -to [all_outputs] # This allows us to view the different groups # in the histogram in the GUI and also includes these diff --git a/flow/platforms/asap7/fastroute.tcl b/flow/platforms/asap7/fastroute.tcl new file mode 100644 index 0000000000..51c8403b1c --- /dev/null +++ b/flow/platforms/asap7/fastroute.tcl @@ -0,0 +1,3 @@ +set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) +set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/asap7/lef/fakeram7_128x64.lef b/flow/platforms/asap7/lef/fakeram7_128x64.lef new file mode 100644 index 0000000000..8b0977f4b9 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_128x64.lef @@ -0,0 +1,1341 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_128x64 + PROPERTY width 64 ; + PROPERTY depth 128 ; + PROPERTY banks 2 ; + FOREIGN fakeram7_128x64 0 0 ; + SYMMETRY X Y R90 ; + SIZE 16.720 BY 21.600 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.024 9.816 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.024 9.960 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.024 10.104 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.024 10.248 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.024 10.392 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.024 10.536 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.024 10.680 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.024 10.824 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.024 10.968 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.024 11.112 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.024 11.256 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.024 11.400 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.024 11.544 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.024 11.688 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.024 11.832 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.024 11.976 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.024 12.120 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.024 12.264 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.384 0.024 12.408 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.528 0.024 12.552 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.672 0.024 12.696 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.816 0.024 12.840 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.960 0.024 12.984 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.104 0.024 13.128 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.248 0.024 13.272 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.392 0.024 13.416 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.536 0.024 13.560 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.680 0.024 13.704 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.824 0.024 13.848 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.968 0.024 13.992 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.112 0.024 14.136 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.256 0.024 14.280 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.400 0.024 14.424 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.544 0.024 14.568 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.688 0.024 14.712 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.832 0.024 14.856 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.976 0.024 15.000 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.120 0.024 15.144 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.264 0.024 15.288 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.408 0.024 15.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.552 0.024 15.576 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.696 0.024 15.720 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.840 0.024 15.864 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.984 0.024 16.008 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.128 0.024 16.152 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.272 0.024 16.296 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.416 0.024 16.440 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.560 0.024 16.584 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.704 0.024 16.728 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.848 0.024 16.872 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.992 0.024 17.016 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.136 0.024 17.160 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.280 0.024 17.304 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.424 0.024 17.448 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.568 0.024 17.592 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.712 0.024 17.736 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.856 0.024 17.880 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.000 0.024 18.024 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.144 0.024 18.168 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.288 0.024 18.312 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.432 0.024 18.456 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.576 0.024 18.600 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.720 0.024 18.744 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.864 0.024 18.888 ; + END + END wd_in[63] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.024 19.560 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.024 19.704 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.024 19.848 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.024 19.992 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.024 20.136 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.024 20.280 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.024 20.424 ; + END + END addr_in[6] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 16.672 0.096 ; + RECT 0.048 0.768 16.672 0.864 ; + RECT 0.048 1.536 16.672 1.632 ; + RECT 0.048 2.304 16.672 2.400 ; + RECT 0.048 3.072 16.672 3.168 ; + RECT 0.048 3.840 16.672 3.936 ; + RECT 0.048 4.608 16.672 4.704 ; + RECT 0.048 5.376 16.672 5.472 ; + RECT 0.048 6.144 16.672 6.240 ; + RECT 0.048 6.912 16.672 7.008 ; + RECT 0.048 7.680 16.672 7.776 ; + RECT 0.048 8.448 16.672 8.544 ; + RECT 0.048 9.216 16.672 9.312 ; + RECT 0.048 9.984 16.672 10.080 ; + RECT 0.048 10.752 16.672 10.848 ; + RECT 0.048 11.520 16.672 11.616 ; + RECT 0.048 12.288 16.672 12.384 ; + RECT 0.048 13.056 16.672 13.152 ; + RECT 0.048 13.824 16.672 13.920 ; + RECT 0.048 14.592 16.672 14.688 ; + RECT 0.048 15.360 16.672 15.456 ; + RECT 0.048 16.128 16.672 16.224 ; + RECT 0.048 16.896 16.672 16.992 ; + RECT 0.048 17.664 16.672 17.760 ; + RECT 0.048 18.432 16.672 18.528 ; + RECT 0.048 19.200 16.672 19.296 ; + RECT 0.048 19.968 16.672 20.064 ; + RECT 0.048 20.736 16.672 20.832 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 16.672 0.480 ; + RECT 0.048 1.152 16.672 1.248 ; + RECT 0.048 1.920 16.672 2.016 ; + RECT 0.048 2.688 16.672 2.784 ; + RECT 0.048 3.456 16.672 3.552 ; + RECT 0.048 4.224 16.672 4.320 ; + RECT 0.048 4.992 16.672 5.088 ; + RECT 0.048 5.760 16.672 5.856 ; + RECT 0.048 6.528 16.672 6.624 ; + RECT 0.048 7.296 16.672 7.392 ; + RECT 0.048 8.064 16.672 8.160 ; + RECT 0.048 8.832 16.672 8.928 ; + RECT 0.048 9.600 16.672 9.696 ; + RECT 0.048 10.368 16.672 10.464 ; + RECT 0.048 11.136 16.672 11.232 ; + RECT 0.048 11.904 16.672 12.000 ; + RECT 0.048 12.672 16.672 12.768 ; + RECT 0.048 13.440 16.672 13.536 ; + RECT 0.048 14.208 16.672 14.304 ; + RECT 0.048 14.976 16.672 15.072 ; + RECT 0.048 15.744 16.672 15.840 ; + RECT 0.048 16.512 16.672 16.608 ; + RECT 0.048 17.280 16.672 17.376 ; + RECT 0.048 18.048 16.672 18.144 ; + RECT 0.048 18.816 16.672 18.912 ; + RECT 0.048 19.584 16.672 19.680 ; + RECT 0.048 20.352 16.672 20.448 ; + RECT 0.048 21.120 16.672 21.216 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 16.720 21.600 ; + LAYER M2 ; + RECT 0 0 16.720 21.600 ; + LAYER M3 ; + RECT 0 0 16.720 21.600 ; + LAYER M4 ; + RECT 0 0 16.720 21.600 ; + END +END fakeram7_128x64 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_256x256.lef b/flow/platforms/asap7/lef/fakeram7_256x256.lef new file mode 100644 index 0000000000..448fa36cef --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_256x256.lef @@ -0,0 +1,4969 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_256x256 + PROPERTY width 256 ; + PROPERTY depth 256 ; + PROPERTY banks 1 ; + FOREIGN fakeram7_256x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 84.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.432 0.024 12.456 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.864 0.024 12.888 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.152 0.024 13.176 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.440 0.024 13.464 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.584 0.024 13.608 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.160 0.024 14.184 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.592 0.024 14.616 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.880 0.024 14.904 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.168 0.024 15.192 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.312 0.024 15.336 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.744 0.024 15.768 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.032 0.024 16.056 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.320 0.024 16.344 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.464 0.024 16.488 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.608 0.024 16.632 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.040 0.024 17.064 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.184 0.024 17.208 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.472 0.024 17.496 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.616 0.024 17.640 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.760 0.024 17.784 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.048 0.024 18.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.192 0.024 18.216 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.336 0.024 18.360 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.480 0.024 18.504 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.624 0.024 18.648 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.768 0.024 18.792 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.912 0.024 18.936 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.056 0.024 19.080 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.200 0.024 19.224 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.344 0.024 19.368 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.488 0.024 19.512 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.024 19.656 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.024 19.800 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.024 19.944 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.024 20.088 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.024 20.232 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.024 20.376 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.024 20.520 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.024 20.664 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.024 20.952 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.024 21.096 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.024 21.240 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.024 21.528 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.024 21.672 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.024 21.816 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.024 22.104 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.024 22.248 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.024 22.392 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.024 22.536 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.024 22.680 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.024 22.824 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.024 22.968 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.024 23.112 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.024 23.256 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.024 23.400 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.024 23.544 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.024 23.832 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.024 23.976 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.024 24.120 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.024 24.408 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.024 24.552 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.024 24.696 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.024 24.984 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.024 25.128 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.024 25.272 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.024 25.560 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.024 25.704 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.024 25.848 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.024 26.136 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.024 26.280 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.024 26.424 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.024 26.712 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.024 26.856 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.024 27.000 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.024 27.288 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.024 27.432 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.024 27.576 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.024 27.864 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.024 28.008 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.024 28.152 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.024 28.440 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.024 28.584 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.024 28.728 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.024 29.016 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.024 29.160 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.024 29.304 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.024 29.592 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.024 29.736 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.024 29.880 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.024 30.168 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.024 30.312 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.024 30.456 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.024 30.744 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.024 30.888 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.024 31.032 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.024 31.320 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.024 31.464 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.024 31.608 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.872 0.024 31.896 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.016 0.024 32.040 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.160 0.024 32.184 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.448 0.024 32.472 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.592 0.024 32.616 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.736 0.024 32.760 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.024 0.024 33.048 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.168 0.024 33.192 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.312 0.024 33.336 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.600 0.024 33.624 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.744 0.024 33.768 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.888 0.024 33.912 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.176 0.024 34.200 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.320 0.024 34.344 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.464 0.024 34.488 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.752 0.024 34.776 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.896 0.024 34.920 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.040 0.024 35.064 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.328 0.024 35.352 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.472 0.024 35.496 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.616 0.024 35.640 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.904 0.024 35.928 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.048 0.024 36.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.192 0.024 36.216 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.336 0.024 36.360 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.480 0.024 36.504 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.624 0.024 36.648 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.768 0.024 36.792 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.744 0.024 39.768 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.888 0.024 39.912 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.032 0.024 40.056 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.176 0.024 40.200 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.320 0.024 40.344 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.464 0.024 40.488 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.608 0.024 40.632 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.752 0.024 40.776 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.896 0.024 40.920 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.040 0.024 41.064 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.184 0.024 41.208 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.328 0.024 41.352 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.472 0.024 41.496 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.616 0.024 41.640 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.760 0.024 41.784 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.904 0.024 41.928 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.048 0.024 42.072 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.192 0.024 42.216 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.336 0.024 42.360 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.480 0.024 42.504 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.624 0.024 42.648 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.768 0.024 42.792 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.912 0.024 42.936 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.056 0.024 43.080 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.200 0.024 43.224 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.344 0.024 43.368 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.488 0.024 43.512 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.632 0.024 43.656 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.776 0.024 43.800 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.920 0.024 43.944 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.064 0.024 44.088 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.208 0.024 44.232 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.352 0.024 44.376 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.496 0.024 44.520 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.640 0.024 44.664 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.784 0.024 44.808 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.928 0.024 44.952 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.072 0.024 45.096 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.216 0.024 45.240 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.360 0.024 45.384 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.504 0.024 45.528 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.648 0.024 45.672 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.792 0.024 45.816 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.936 0.024 45.960 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.080 0.024 46.104 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.224 0.024 46.248 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.368 0.024 46.392 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.024 46.536 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.656 0.024 46.680 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.800 0.024 46.824 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.944 0.024 46.968 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.088 0.024 47.112 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.232 0.024 47.256 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.376 0.024 47.400 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.520 0.024 47.544 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.664 0.024 47.688 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.808 0.024 47.832 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.952 0.024 47.976 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.096 0.024 48.120 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.240 0.024 48.264 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.384 0.024 48.408 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.528 0.024 48.552 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.672 0.024 48.696 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.816 0.024 48.840 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.960 0.024 48.984 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.104 0.024 49.128 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.248 0.024 49.272 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.392 0.024 49.416 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.536 0.024 49.560 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.680 0.024 49.704 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.824 0.024 49.848 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.968 0.024 49.992 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.112 0.024 50.136 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.256 0.024 50.280 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.400 0.024 50.424 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.544 0.024 50.568 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.688 0.024 50.712 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.832 0.024 50.856 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.976 0.024 51.000 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.120 0.024 51.144 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.264 0.024 51.288 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.408 0.024 51.432 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.552 0.024 51.576 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.696 0.024 51.720 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.840 0.024 51.864 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.984 0.024 52.008 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.128 0.024 52.152 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.272 0.024 52.296 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.416 0.024 52.440 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.560 0.024 52.584 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.704 0.024 52.728 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.848 0.024 52.872 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.992 0.024 53.016 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.136 0.024 53.160 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.280 0.024 53.304 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.424 0.024 53.448 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.568 0.024 53.592 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.712 0.024 53.736 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.856 0.024 53.880 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.000 0.024 54.024 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.144 0.024 54.168 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.288 0.024 54.312 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.432 0.024 54.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.576 0.024 54.600 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.720 0.024 54.744 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.864 0.024 54.888 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.008 0.024 55.032 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.152 0.024 55.176 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.296 0.024 55.320 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.440 0.024 55.464 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.584 0.024 55.608 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.728 0.024 55.752 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.872 0.024 55.896 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.016 0.024 56.040 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.160 0.024 56.184 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.304 0.024 56.328 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.448 0.024 56.472 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.592 0.024 56.616 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.736 0.024 56.760 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.880 0.024 56.904 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.024 0.024 57.048 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.168 0.024 57.192 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.312 0.024 57.336 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.456 0.024 57.480 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.600 0.024 57.624 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.744 0.024 57.768 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.888 0.024 57.912 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.032 0.024 58.056 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.176 0.024 58.200 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.320 0.024 58.344 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.464 0.024 58.488 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.608 0.024 58.632 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.752 0.024 58.776 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.896 0.024 58.920 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.040 0.024 59.064 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.184 0.024 59.208 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.328 0.024 59.352 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.472 0.024 59.496 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.616 0.024 59.640 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.760 0.024 59.784 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.904 0.024 59.928 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.048 0.024 60.072 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.192 0.024 60.216 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.336 0.024 60.360 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.480 0.024 60.504 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.624 0.024 60.648 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.768 0.024 60.792 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.912 0.024 60.936 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.056 0.024 61.080 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.200 0.024 61.224 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.344 0.024 61.368 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.488 0.024 61.512 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.632 0.024 61.656 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.776 0.024 61.800 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.920 0.024 61.944 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.064 0.024 62.088 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.208 0.024 62.232 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.352 0.024 62.376 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.496 0.024 62.520 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.640 0.024 62.664 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.784 0.024 62.808 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.928 0.024 62.952 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.072 0.024 63.096 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.216 0.024 63.240 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.360 0.024 63.384 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.504 0.024 63.528 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.648 0.024 63.672 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.792 0.024 63.816 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.936 0.024 63.960 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.080 0.024 64.104 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.224 0.024 64.248 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.368 0.024 64.392 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.512 0.024 64.536 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.656 0.024 64.680 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.800 0.024 64.824 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.944 0.024 64.968 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.088 0.024 65.112 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.232 0.024 65.256 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.376 0.024 65.400 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.520 0.024 65.544 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.664 0.024 65.688 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.808 0.024 65.832 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.952 0.024 65.976 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.096 0.024 66.120 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.240 0.024 66.264 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.384 0.024 66.408 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.528 0.024 66.552 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.672 0.024 66.696 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.816 0.024 66.840 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.960 0.024 66.984 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.104 0.024 67.128 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.248 0.024 67.272 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.392 0.024 67.416 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.536 0.024 67.560 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.680 0.024 67.704 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.824 0.024 67.848 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.968 0.024 67.992 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.112 0.024 68.136 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.256 0.024 68.280 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.400 0.024 68.424 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.544 0.024 68.568 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.688 0.024 68.712 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.832 0.024 68.856 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.976 0.024 69.000 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.120 0.024 69.144 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.264 0.024 69.288 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.408 0.024 69.432 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.552 0.024 69.576 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.696 0.024 69.720 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.840 0.024 69.864 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.984 0.024 70.008 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.128 0.024 70.152 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.272 0.024 70.296 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.416 0.024 70.440 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.560 0.024 70.584 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.704 0.024 70.728 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.848 0.024 70.872 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.992 0.024 71.016 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.136 0.024 71.160 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.280 0.024 71.304 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.424 0.024 71.448 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.568 0.024 71.592 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.712 0.024 71.736 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.856 0.024 71.880 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.000 0.024 72.024 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.144 0.024 72.168 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.288 0.024 72.312 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.432 0.024 72.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.576 0.024 72.600 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.720 0.024 72.744 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.864 0.024 72.888 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.008 0.024 73.032 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.152 0.024 73.176 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.296 0.024 73.320 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.440 0.024 73.464 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.584 0.024 73.608 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.728 0.024 73.752 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.872 0.024 73.896 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.016 0.024 74.040 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.160 0.024 74.184 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.304 0.024 74.328 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.448 0.024 74.472 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.592 0.024 74.616 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.736 0.024 74.760 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.880 0.024 74.904 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.024 0.024 75.048 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.168 0.024 75.192 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.312 0.024 75.336 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.456 0.024 75.480 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.600 0.024 75.624 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.744 0.024 75.768 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.888 0.024 75.912 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.032 0.024 76.056 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.176 0.024 76.200 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.320 0.024 76.344 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.464 0.024 76.488 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.440 0.024 79.464 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.584 0.024 79.608 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.728 0.024 79.752 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.872 0.024 79.896 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.016 0.024 80.040 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.160 0.024 80.184 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.304 0.024 80.328 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.448 0.024 80.472 ; + END + END addr_in[7] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.424 0.024 83.448 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.568 0.024 83.592 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.712 0.024 83.736 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 33.202 0.096 ; + RECT 0.048 0.768 33.202 0.864 ; + RECT 0.048 1.536 33.202 1.632 ; + RECT 0.048 2.304 33.202 2.400 ; + RECT 0.048 3.072 33.202 3.168 ; + RECT 0.048 3.840 33.202 3.936 ; + RECT 0.048 4.608 33.202 4.704 ; + RECT 0.048 5.376 33.202 5.472 ; + RECT 0.048 6.144 33.202 6.240 ; + RECT 0.048 6.912 33.202 7.008 ; + RECT 0.048 7.680 33.202 7.776 ; + RECT 0.048 8.448 33.202 8.544 ; + RECT 0.048 9.216 33.202 9.312 ; + RECT 0.048 9.984 33.202 10.080 ; + RECT 0.048 10.752 33.202 10.848 ; + RECT 0.048 11.520 33.202 11.616 ; + RECT 0.048 12.288 33.202 12.384 ; + RECT 0.048 13.056 33.202 13.152 ; + RECT 0.048 13.824 33.202 13.920 ; + RECT 0.048 14.592 33.202 14.688 ; + RECT 0.048 15.360 33.202 15.456 ; + RECT 0.048 16.128 33.202 16.224 ; + RECT 0.048 16.896 33.202 16.992 ; + RECT 0.048 17.664 33.202 17.760 ; + RECT 0.048 18.432 33.202 18.528 ; + RECT 0.048 19.200 33.202 19.296 ; + RECT 0.048 19.968 33.202 20.064 ; + RECT 0.048 20.736 33.202 20.832 ; + RECT 0.048 21.504 33.202 21.600 ; + RECT 0.048 22.272 33.202 22.368 ; + RECT 0.048 23.040 33.202 23.136 ; + RECT 0.048 23.808 33.202 23.904 ; + RECT 0.048 24.576 33.202 24.672 ; + RECT 0.048 25.344 33.202 25.440 ; + RECT 0.048 26.112 33.202 26.208 ; + RECT 0.048 26.880 33.202 26.976 ; + RECT 0.048 27.648 33.202 27.744 ; + RECT 0.048 28.416 33.202 28.512 ; + RECT 0.048 29.184 33.202 29.280 ; + RECT 0.048 29.952 33.202 30.048 ; + RECT 0.048 30.720 33.202 30.816 ; + RECT 0.048 31.488 33.202 31.584 ; + RECT 0.048 32.256 33.202 32.352 ; + RECT 0.048 33.024 33.202 33.120 ; + RECT 0.048 33.792 33.202 33.888 ; + RECT 0.048 34.560 33.202 34.656 ; + RECT 0.048 35.328 33.202 35.424 ; + RECT 0.048 36.096 33.202 36.192 ; + RECT 0.048 36.864 33.202 36.960 ; + RECT 0.048 37.632 33.202 37.728 ; + RECT 0.048 38.400 33.202 38.496 ; + RECT 0.048 39.168 33.202 39.264 ; + RECT 0.048 39.936 33.202 40.032 ; + RECT 0.048 40.704 33.202 40.800 ; + RECT 0.048 41.472 33.202 41.568 ; + RECT 0.048 42.240 33.202 42.336 ; + RECT 0.048 43.008 33.202 43.104 ; + RECT 0.048 43.776 33.202 43.872 ; + RECT 0.048 44.544 33.202 44.640 ; + RECT 0.048 45.312 33.202 45.408 ; + RECT 0.048 46.080 33.202 46.176 ; + RECT 0.048 46.848 33.202 46.944 ; + RECT 0.048 47.616 33.202 47.712 ; + RECT 0.048 48.384 33.202 48.480 ; + RECT 0.048 49.152 33.202 49.248 ; + RECT 0.048 49.920 33.202 50.016 ; + RECT 0.048 50.688 33.202 50.784 ; + RECT 0.048 51.456 33.202 51.552 ; + RECT 0.048 52.224 33.202 52.320 ; + RECT 0.048 52.992 33.202 53.088 ; + RECT 0.048 53.760 33.202 53.856 ; + RECT 0.048 54.528 33.202 54.624 ; + RECT 0.048 55.296 33.202 55.392 ; + RECT 0.048 56.064 33.202 56.160 ; + RECT 0.048 56.832 33.202 56.928 ; + RECT 0.048 57.600 33.202 57.696 ; + RECT 0.048 58.368 33.202 58.464 ; + RECT 0.048 59.136 33.202 59.232 ; + RECT 0.048 59.904 33.202 60.000 ; + RECT 0.048 60.672 33.202 60.768 ; + RECT 0.048 61.440 33.202 61.536 ; + RECT 0.048 62.208 33.202 62.304 ; + RECT 0.048 62.976 33.202 63.072 ; + RECT 0.048 63.744 33.202 63.840 ; + RECT 0.048 64.512 33.202 64.608 ; + RECT 0.048 65.280 33.202 65.376 ; + RECT 0.048 66.048 33.202 66.144 ; + RECT 0.048 66.816 33.202 66.912 ; + RECT 0.048 67.584 33.202 67.680 ; + RECT 0.048 68.352 33.202 68.448 ; + RECT 0.048 69.120 33.202 69.216 ; + RECT 0.048 69.888 33.202 69.984 ; + RECT 0.048 70.656 33.202 70.752 ; + RECT 0.048 71.424 33.202 71.520 ; + RECT 0.048 72.192 33.202 72.288 ; + RECT 0.048 72.960 33.202 73.056 ; + RECT 0.048 73.728 33.202 73.824 ; + RECT 0.048 74.496 33.202 74.592 ; + RECT 0.048 75.264 33.202 75.360 ; + RECT 0.048 76.032 33.202 76.128 ; + RECT 0.048 76.800 33.202 76.896 ; + RECT 0.048 77.568 33.202 77.664 ; + RECT 0.048 78.336 33.202 78.432 ; + RECT 0.048 79.104 33.202 79.200 ; + RECT 0.048 79.872 33.202 79.968 ; + RECT 0.048 80.640 33.202 80.736 ; + RECT 0.048 81.408 33.202 81.504 ; + RECT 0.048 82.176 33.202 82.272 ; + RECT 0.048 82.944 33.202 83.040 ; + RECT 0.048 83.712 33.202 83.808 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 33.202 0.480 ; + RECT 0.048 1.152 33.202 1.248 ; + RECT 0.048 1.920 33.202 2.016 ; + RECT 0.048 2.688 33.202 2.784 ; + RECT 0.048 3.456 33.202 3.552 ; + RECT 0.048 4.224 33.202 4.320 ; + RECT 0.048 4.992 33.202 5.088 ; + RECT 0.048 5.760 33.202 5.856 ; + RECT 0.048 6.528 33.202 6.624 ; + RECT 0.048 7.296 33.202 7.392 ; + RECT 0.048 8.064 33.202 8.160 ; + RECT 0.048 8.832 33.202 8.928 ; + RECT 0.048 9.600 33.202 9.696 ; + RECT 0.048 10.368 33.202 10.464 ; + RECT 0.048 11.136 33.202 11.232 ; + RECT 0.048 11.904 33.202 12.000 ; + RECT 0.048 12.672 33.202 12.768 ; + RECT 0.048 13.440 33.202 13.536 ; + RECT 0.048 14.208 33.202 14.304 ; + RECT 0.048 14.976 33.202 15.072 ; + RECT 0.048 15.744 33.202 15.840 ; + RECT 0.048 16.512 33.202 16.608 ; + RECT 0.048 17.280 33.202 17.376 ; + RECT 0.048 18.048 33.202 18.144 ; + RECT 0.048 18.816 33.202 18.912 ; + RECT 0.048 19.584 33.202 19.680 ; + RECT 0.048 20.352 33.202 20.448 ; + RECT 0.048 21.120 33.202 21.216 ; + RECT 0.048 21.888 33.202 21.984 ; + RECT 0.048 22.656 33.202 22.752 ; + RECT 0.048 23.424 33.202 23.520 ; + RECT 0.048 24.192 33.202 24.288 ; + RECT 0.048 24.960 33.202 25.056 ; + RECT 0.048 25.728 33.202 25.824 ; + RECT 0.048 26.496 33.202 26.592 ; + RECT 0.048 27.264 33.202 27.360 ; + RECT 0.048 28.032 33.202 28.128 ; + RECT 0.048 28.800 33.202 28.896 ; + RECT 0.048 29.568 33.202 29.664 ; + RECT 0.048 30.336 33.202 30.432 ; + RECT 0.048 31.104 33.202 31.200 ; + RECT 0.048 31.872 33.202 31.968 ; + RECT 0.048 32.640 33.202 32.736 ; + RECT 0.048 33.408 33.202 33.504 ; + RECT 0.048 34.176 33.202 34.272 ; + RECT 0.048 34.944 33.202 35.040 ; + RECT 0.048 35.712 33.202 35.808 ; + RECT 0.048 36.480 33.202 36.576 ; + RECT 0.048 37.248 33.202 37.344 ; + RECT 0.048 38.016 33.202 38.112 ; + RECT 0.048 38.784 33.202 38.880 ; + RECT 0.048 39.552 33.202 39.648 ; + RECT 0.048 40.320 33.202 40.416 ; + RECT 0.048 41.088 33.202 41.184 ; + RECT 0.048 41.856 33.202 41.952 ; + RECT 0.048 42.624 33.202 42.720 ; + RECT 0.048 43.392 33.202 43.488 ; + RECT 0.048 44.160 33.202 44.256 ; + RECT 0.048 44.928 33.202 45.024 ; + RECT 0.048 45.696 33.202 45.792 ; + RECT 0.048 46.464 33.202 46.560 ; + RECT 0.048 47.232 33.202 47.328 ; + RECT 0.048 48.000 33.202 48.096 ; + RECT 0.048 48.768 33.202 48.864 ; + RECT 0.048 49.536 33.202 49.632 ; + RECT 0.048 50.304 33.202 50.400 ; + RECT 0.048 51.072 33.202 51.168 ; + RECT 0.048 51.840 33.202 51.936 ; + RECT 0.048 52.608 33.202 52.704 ; + RECT 0.048 53.376 33.202 53.472 ; + RECT 0.048 54.144 33.202 54.240 ; + RECT 0.048 54.912 33.202 55.008 ; + RECT 0.048 55.680 33.202 55.776 ; + RECT 0.048 56.448 33.202 56.544 ; + RECT 0.048 57.216 33.202 57.312 ; + RECT 0.048 57.984 33.202 58.080 ; + RECT 0.048 58.752 33.202 58.848 ; + RECT 0.048 59.520 33.202 59.616 ; + RECT 0.048 60.288 33.202 60.384 ; + RECT 0.048 61.056 33.202 61.152 ; + RECT 0.048 61.824 33.202 61.920 ; + RECT 0.048 62.592 33.202 62.688 ; + RECT 0.048 63.360 33.202 63.456 ; + RECT 0.048 64.128 33.202 64.224 ; + RECT 0.048 64.896 33.202 64.992 ; + RECT 0.048 65.664 33.202 65.760 ; + RECT 0.048 66.432 33.202 66.528 ; + RECT 0.048 67.200 33.202 67.296 ; + RECT 0.048 67.968 33.202 68.064 ; + RECT 0.048 68.736 33.202 68.832 ; + RECT 0.048 69.504 33.202 69.600 ; + RECT 0.048 70.272 33.202 70.368 ; + RECT 0.048 71.040 33.202 71.136 ; + RECT 0.048 71.808 33.202 71.904 ; + RECT 0.048 72.576 33.202 72.672 ; + RECT 0.048 73.344 33.202 73.440 ; + RECT 0.048 74.112 33.202 74.208 ; + RECT 0.048 74.880 33.202 74.976 ; + RECT 0.048 75.648 33.202 75.744 ; + RECT 0.048 76.416 33.202 76.512 ; + RECT 0.048 77.184 33.202 77.280 ; + RECT 0.048 77.952 33.202 78.048 ; + RECT 0.048 78.720 33.202 78.816 ; + RECT 0.048 79.488 33.202 79.584 ; + RECT 0.048 80.256 33.202 80.352 ; + RECT 0.048 81.024 33.202 81.120 ; + RECT 0.048 81.792 33.202 81.888 ; + RECT 0.048 82.560 33.202 82.656 ; + RECT 0.048 83.328 33.202 83.424 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 84.000 ; + LAYER M2 ; + RECT 0 0 33.250 84.000 ; + LAYER M3 ; + RECT 0 0 33.250 84.000 ; + LAYER M4 ; + RECT 0 0 33.250 84.000 ; + END +END fakeram7_256x256 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x25.lef b/flow/platforms/asap7/lef/fakeram7_64x25.lef new file mode 100644 index 0000000000..70cb255428 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x25.lef @@ -0,0 +1,590 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x25 + PROPERTY width 25 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x25 0 0 ; + SYMMETRY X Y R90 ; + SIZE 13.110 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.024 0.168 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.024 0.264 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.024 0.456 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.024 0.552 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.024 0.744 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.024 0.840 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.024 1.032 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.024 1.128 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.024 1.320 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.024 1.416 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.024 1.608 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.024 1.704 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.024 1.896 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.024 1.992 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.024 2.184 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.024 2.280 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[24] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.024 2.616 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.024 2.712 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.024 2.904 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.024 3.000 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.024 3.192 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.024 3.288 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.024 3.480 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.024 3.576 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.024 3.768 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.024 3.864 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.024 4.056 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.024 4.152 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.024 4.344 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.024 4.440 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.024 4.632 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.024 4.728 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END wd_in[24] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.024 5.064 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.024 5.160 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.024 5.352 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.024 5.448 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.024 5.592 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.024 5.784 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 13.062 0.096 ; + RECT 0.048 0.768 13.062 0.864 ; + RECT 0.048 1.536 13.062 1.632 ; + RECT 0.048 2.304 13.062 2.400 ; + RECT 0.048 3.072 13.062 3.168 ; + RECT 0.048 3.840 13.062 3.936 ; + RECT 0.048 4.608 13.062 4.704 ; + RECT 0.048 5.376 13.062 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 13.062 0.480 ; + RECT 0.048 1.152 13.062 1.248 ; + RECT 0.048 1.920 13.062 2.016 ; + RECT 0.048 2.688 13.062 2.784 ; + RECT 0.048 3.456 13.062 3.552 ; + RECT 0.048 4.224 13.062 4.320 ; + RECT 0.048 4.992 13.062 5.088 ; + RECT 0.048 5.760 13.062 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 13.110 6.000 ; + LAYER M2 ; + RECT 0 0 13.110 6.000 ; + LAYER M3 ; + RECT 0 0 13.110 6.000 ; + LAYER M4 ; + RECT 0 0 13.110 6.000 ; + END +END fakeram7_64x25 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x256.lef b/flow/platforms/asap7/lef/fakeram7_64x256.lef new file mode 100644 index 0000000000..d1b8f95fee --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x256.lef @@ -0,0 +1,4854 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x256 + PROPERTY width 256 ; + PROPERTY depth 64 ; + PROPERTY banks 1 ; + FOREIGN fakeram7_64x256 0 0 ; + SYMMETRY X Y R90 ; + SIZE 33.250 BY 46.800 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.392 0.036 1.416 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.440 0.036 1.464 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.036 1.512 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.536 0.036 1.560 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.584 0.036 1.608 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.036 1.656 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.680 0.036 1.704 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.728 0.036 1.752 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.036 1.800 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.824 0.036 1.848 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.872 0.036 1.896 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.036 1.944 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.968 0.036 1.992 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.016 0.036 2.040 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.036 2.088 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.112 0.036 2.136 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.160 0.036 2.184 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.036 2.232 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.256 0.036 2.280 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.036 3.672 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.696 0.036 3.720 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.744 0.036 3.768 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.036 3.816 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.840 0.036 3.864 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.888 0.036 3.912 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.036 3.960 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.984 0.036 4.008 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.032 0.036 4.056 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.036 4.104 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.128 0.036 4.152 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.176 0.036 4.200 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.036 4.248 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.272 0.036 4.296 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.320 0.036 4.344 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.036 4.392 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.416 0.036 4.440 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.464 0.036 4.488 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.036 4.536 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.848 0.036 4.872 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.896 0.036 4.920 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.036 4.968 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.992 0.036 5.016 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.040 0.036 5.064 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.036 5.112 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.136 0.036 5.160 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.184 0.036 5.208 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.036 5.256 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.280 0.036 5.304 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.328 0.036 5.352 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.036 5.400 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.424 0.036 5.448 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.472 0.036 5.496 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.036 5.544 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.568 0.036 5.592 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.616 0.036 5.640 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.036 5.688 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.712 0.036 5.736 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.904 0.036 5.928 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.036 5.976 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.000 0.036 6.024 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.048 0.036 6.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.036 6.120 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.144 0.036 6.168 ; + END + END rd_out[127] + PIN rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.192 0.036 6.216 ; + END + END rd_out[128] + PIN rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.036 6.264 ; + END + END rd_out[129] + PIN rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.288 0.036 6.312 ; + END + END rd_out[130] + PIN rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.336 0.036 6.360 ; + END + END rd_out[131] + PIN rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.036 6.408 ; + END + END rd_out[132] + PIN rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.432 0.036 6.456 ; + END + END rd_out[133] + PIN rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.480 0.036 6.504 ; + END + END rd_out[134] + PIN rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.036 6.552 ; + END + END rd_out[135] + PIN rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.576 0.036 6.600 ; + END + END rd_out[136] + PIN rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.624 0.036 6.648 ; + END + END rd_out[137] + PIN rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.036 6.696 ; + END + END rd_out[138] + PIN rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.720 0.036 6.744 ; + END + END rd_out[139] + PIN rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.768 0.036 6.792 ; + END + END rd_out[140] + PIN rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.036 6.840 ; + END + END rd_out[141] + PIN rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.864 0.036 6.888 ; + END + END rd_out[142] + PIN rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.912 0.036 6.936 ; + END + END rd_out[143] + PIN rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.036 6.984 ; + END + END rd_out[144] + PIN rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.008 0.036 7.032 ; + END + END rd_out[145] + PIN rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.056 0.036 7.080 ; + END + END rd_out[146] + PIN rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.036 7.128 ; + END + END rd_out[147] + PIN rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.152 0.036 7.176 ; + END + END rd_out[148] + PIN rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.200 0.036 7.224 ; + END + END rd_out[149] + PIN rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.036 7.272 ; + END + END rd_out[150] + PIN rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.296 0.036 7.320 ; + END + END rd_out[151] + PIN rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.344 0.036 7.368 ; + END + END rd_out[152] + PIN rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.036 7.416 ; + END + END rd_out[153] + PIN rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.440 0.036 7.464 ; + END + END rd_out[154] + PIN rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.488 0.036 7.512 ; + END + END rd_out[155] + PIN rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.036 7.560 ; + END + END rd_out[156] + PIN rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.584 0.036 7.608 ; + END + END rd_out[157] + PIN rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.632 0.036 7.656 ; + END + END rd_out[158] + PIN rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.036 7.704 ; + END + END rd_out[159] + PIN rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.728 0.036 7.752 ; + END + END rd_out[160] + PIN rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.776 0.036 7.800 ; + END + END rd_out[161] + PIN rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.036 7.848 ; + END + END rd_out[162] + PIN rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.872 0.036 7.896 ; + END + END rd_out[163] + PIN rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.920 0.036 7.944 ; + END + END rd_out[164] + PIN rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.036 7.992 ; + END + END rd_out[165] + PIN rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.016 0.036 8.040 ; + END + END rd_out[166] + PIN rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.064 0.036 8.088 ; + END + END rd_out[167] + PIN rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.036 8.136 ; + END + END rd_out[168] + PIN rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.160 0.036 8.184 ; + END + END rd_out[169] + PIN rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.208 0.036 8.232 ; + END + END rd_out[170] + PIN rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.036 8.280 ; + END + END rd_out[171] + PIN rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.304 0.036 8.328 ; + END + END rd_out[172] + PIN rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.352 0.036 8.376 ; + END + END rd_out[173] + PIN rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.036 8.424 ; + END + END rd_out[174] + PIN rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.448 0.036 8.472 ; + END + END rd_out[175] + PIN rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.496 0.036 8.520 ; + END + END rd_out[176] + PIN rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.036 8.568 ; + END + END rd_out[177] + PIN rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.592 0.036 8.616 ; + END + END rd_out[178] + PIN rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.640 0.036 8.664 ; + END + END rd_out[179] + PIN rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.036 8.712 ; + END + END rd_out[180] + PIN rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.736 0.036 8.760 ; + END + END rd_out[181] + PIN rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.784 0.036 8.808 ; + END + END rd_out[182] + PIN rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.036 8.856 ; + END + END rd_out[183] + PIN rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.880 0.036 8.904 ; + END + END rd_out[184] + PIN rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.928 0.036 8.952 ; + END + END rd_out[185] + PIN rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.036 9.000 ; + END + END rd_out[186] + PIN rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.024 0.036 9.048 ; + END + END rd_out[187] + PIN rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.072 0.036 9.096 ; + END + END rd_out[188] + PIN rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.036 9.144 ; + END + END rd_out[189] + PIN rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.168 0.036 9.192 ; + END + END rd_out[190] + PIN rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.216 0.036 9.240 ; + END + END rd_out[191] + PIN rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.036 9.288 ; + END + END rd_out[192] + PIN rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.312 0.036 9.336 ; + END + END rd_out[193] + PIN rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.360 0.036 9.384 ; + END + END rd_out[194] + PIN rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.036 9.432 ; + END + END rd_out[195] + PIN rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.456 0.036 9.480 ; + END + END rd_out[196] + PIN rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.504 0.036 9.528 ; + END + END rd_out[197] + PIN rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.036 9.576 ; + END + END rd_out[198] + PIN rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.600 0.036 9.624 ; + END + END rd_out[199] + PIN rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.648 0.036 9.672 ; + END + END rd_out[200] + PIN rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.036 9.720 ; + END + END rd_out[201] + PIN rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.744 0.036 9.768 ; + END + END rd_out[202] + PIN rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.792 0.036 9.816 ; + END + END rd_out[203] + PIN rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.036 9.864 ; + END + END rd_out[204] + PIN rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.888 0.036 9.912 ; + END + END rd_out[205] + PIN rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.936 0.036 9.960 ; + END + END rd_out[206] + PIN rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.036 10.008 ; + END + END rd_out[207] + PIN rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.032 0.036 10.056 ; + END + END rd_out[208] + PIN rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.080 0.036 10.104 ; + END + END rd_out[209] + PIN rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.036 10.152 ; + END + END rd_out[210] + PIN rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.176 0.036 10.200 ; + END + END rd_out[211] + PIN rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.224 0.036 10.248 ; + END + END rd_out[212] + PIN rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.036 10.296 ; + END + END rd_out[213] + PIN rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.320 0.036 10.344 ; + END + END rd_out[214] + PIN rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.368 0.036 10.392 ; + END + END rd_out[215] + PIN rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.036 10.440 ; + END + END rd_out[216] + PIN rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.464 0.036 10.488 ; + END + END rd_out[217] + PIN rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.512 0.036 10.536 ; + END + END rd_out[218] + PIN rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.036 10.584 ; + END + END rd_out[219] + PIN rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.608 0.036 10.632 ; + END + END rd_out[220] + PIN rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.656 0.036 10.680 ; + END + END rd_out[221] + PIN rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.036 10.728 ; + END + END rd_out[222] + PIN rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.752 0.036 10.776 ; + END + END rd_out[223] + PIN rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.800 0.036 10.824 ; + END + END rd_out[224] + PIN rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.036 10.872 ; + END + END rd_out[225] + PIN rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.896 0.036 10.920 ; + END + END rd_out[226] + PIN rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.944 0.036 10.968 ; + END + END rd_out[227] + PIN rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.036 11.016 ; + END + END rd_out[228] + PIN rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.040 0.036 11.064 ; + END + END rd_out[229] + PIN rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.088 0.036 11.112 ; + END + END rd_out[230] + PIN rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.036 11.160 ; + END + END rd_out[231] + PIN rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.184 0.036 11.208 ; + END + END rd_out[232] + PIN rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.232 0.036 11.256 ; + END + END rd_out[233] + PIN rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.036 11.304 ; + END + END rd_out[234] + PIN rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.328 0.036 11.352 ; + END + END rd_out[235] + PIN rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.376 0.036 11.400 ; + END + END rd_out[236] + PIN rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.036 11.448 ; + END + END rd_out[237] + PIN rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.472 0.036 11.496 ; + END + END rd_out[238] + PIN rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.520 0.036 11.544 ; + END + END rd_out[239] + PIN rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.036 11.592 ; + END + END rd_out[240] + PIN rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.616 0.036 11.640 ; + END + END rd_out[241] + PIN rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.664 0.036 11.688 ; + END + END rd_out[242] + PIN rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.036 11.736 ; + END + END rd_out[243] + PIN rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.760 0.036 11.784 ; + END + END rd_out[244] + PIN rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.808 0.036 11.832 ; + END + END rd_out[245] + PIN rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.036 11.880 ; + END + END rd_out[246] + PIN rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.904 0.036 11.928 ; + END + END rd_out[247] + PIN rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.952 0.036 11.976 ; + END + END rd_out[248] + PIN rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.036 12.024 ; + END + END rd_out[249] + PIN rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.048 0.036 12.072 ; + END + END rd_out[250] + PIN rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.096 0.036 12.120 ; + END + END rd_out[251] + PIN rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.036 12.168 ; + END + END rd_out[252] + PIN rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.192 0.036 12.216 ; + END + END rd_out[253] + PIN rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.240 0.036 12.264 ; + END + END rd_out[254] + PIN rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.036 12.312 ; + END + END rd_out[255] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.536 0.036 19.560 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.584 0.036 19.608 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.036 19.656 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.680 0.036 19.704 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.728 0.036 19.752 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.776 0.036 19.800 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.824 0.036 19.848 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.872 0.036 19.896 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.920 0.036 19.944 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.968 0.036 19.992 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.016 0.036 20.040 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.064 0.036 20.088 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.112 0.036 20.136 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.160 0.036 20.184 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.036 20.232 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.256 0.036 20.280 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.036 20.328 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.352 0.036 20.376 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.400 0.036 20.424 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.448 0.036 20.472 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.496 0.036 20.520 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.544 0.036 20.568 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.592 0.036 20.616 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.640 0.036 20.664 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.688 0.036 20.712 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.736 0.036 20.760 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.036 20.808 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.832 0.036 20.856 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.880 0.036 20.904 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.928 0.036 20.952 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.976 0.036 21.000 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.036 21.048 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.072 0.036 21.096 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.120 0.036 21.144 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.168 0.036 21.192 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.216 0.036 21.240 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.264 0.036 21.288 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.312 0.036 21.336 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.036 21.384 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.408 0.036 21.432 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.456 0.036 21.480 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.504 0.036 21.528 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.552 0.036 21.576 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.600 0.036 21.624 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.648 0.036 21.672 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.696 0.036 21.720 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.744 0.036 21.768 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.792 0.036 21.816 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.840 0.036 21.864 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.888 0.036 21.912 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.036 21.960 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.984 0.036 22.008 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.032 0.036 22.056 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.080 0.036 22.104 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.128 0.036 22.152 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.176 0.036 22.200 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.224 0.036 22.248 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.272 0.036 22.296 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.320 0.036 22.344 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.368 0.036 22.392 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.416 0.036 22.440 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.464 0.036 22.488 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.036 22.536 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.560 0.036 22.584 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.608 0.036 22.632 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.656 0.036 22.680 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.704 0.036 22.728 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.752 0.036 22.776 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.800 0.036 22.824 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.848 0.036 22.872 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.896 0.036 22.920 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.944 0.036 22.968 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.992 0.036 23.016 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.040 0.036 23.064 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.036 23.112 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.136 0.036 23.160 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.184 0.036 23.208 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.232 0.036 23.256 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.280 0.036 23.304 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.328 0.036 23.352 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.376 0.036 23.400 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.424 0.036 23.448 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.472 0.036 23.496 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.520 0.036 23.544 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.568 0.036 23.592 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.036 23.640 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.036 23.688 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.712 0.036 23.736 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.036 23.784 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.808 0.036 23.832 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.856 0.036 23.880 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.036 23.928 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.952 0.036 23.976 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.000 0.036 24.024 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.036 24.072 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.096 0.036 24.120 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.144 0.036 24.168 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.036 24.216 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.036 24.264 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.288 0.036 24.312 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.036 24.360 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.384 0.036 24.408 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.432 0.036 24.456 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.036 24.504 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.528 0.036 24.552 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.576 0.036 24.600 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.036 24.648 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.672 0.036 24.696 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.720 0.036 24.744 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.036 24.792 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.036 24.840 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.864 0.036 24.888 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.036 24.936 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.960 0.036 24.984 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.008 0.036 25.032 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.036 25.080 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.104 0.036 25.128 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.152 0.036 25.176 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.036 25.224 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.248 0.036 25.272 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.296 0.036 25.320 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.036 25.368 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.036 25.416 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.440 0.036 25.464 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.036 25.512 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.536 0.036 25.560 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.584 0.036 25.608 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.036 25.656 ; + END + END wd_in[127] + PIN wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.680 0.036 25.704 ; + END + END wd_in[128] + PIN wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.728 0.036 25.752 ; + END + END wd_in[129] + PIN wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.036 25.800 ; + END + END wd_in[130] + PIN wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.824 0.036 25.848 ; + END + END wd_in[131] + PIN wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.872 0.036 25.896 ; + END + END wd_in[132] + PIN wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.036 25.944 ; + END + END wd_in[133] + PIN wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.036 25.992 ; + END + END wd_in[134] + PIN wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.016 0.036 26.040 ; + END + END wd_in[135] + PIN wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.036 26.088 ; + END + END wd_in[136] + PIN wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.112 0.036 26.136 ; + END + END wd_in[137] + PIN wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.160 0.036 26.184 ; + END + END wd_in[138] + PIN wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.036 26.232 ; + END + END wd_in[139] + PIN wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.256 0.036 26.280 ; + END + END wd_in[140] + PIN wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.304 0.036 26.328 ; + END + END wd_in[141] + PIN wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.036 26.376 ; + END + END wd_in[142] + PIN wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.400 0.036 26.424 ; + END + END wd_in[143] + PIN wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.448 0.036 26.472 ; + END + END wd_in[144] + PIN wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.036 26.520 ; + END + END wd_in[145] + PIN wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.036 26.568 ; + END + END wd_in[146] + PIN wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.592 0.036 26.616 ; + END + END wd_in[147] + PIN wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.036 26.664 ; + END + END wd_in[148] + PIN wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.688 0.036 26.712 ; + END + END wd_in[149] + PIN wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.736 0.036 26.760 ; + END + END wd_in[150] + PIN wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.036 26.808 ; + END + END wd_in[151] + PIN wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.832 0.036 26.856 ; + END + END wd_in[152] + PIN wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.880 0.036 26.904 ; + END + END wd_in[153] + PIN wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.036 26.952 ; + END + END wd_in[154] + PIN wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.976 0.036 27.000 ; + END + END wd_in[155] + PIN wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.024 0.036 27.048 ; + END + END wd_in[156] + PIN wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.036 27.096 ; + END + END wd_in[157] + PIN wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.036 27.144 ; + END + END wd_in[158] + PIN wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.168 0.036 27.192 ; + END + END wd_in[159] + PIN wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.036 27.240 ; + END + END wd_in[160] + PIN wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.264 0.036 27.288 ; + END + END wd_in[161] + PIN wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.312 0.036 27.336 ; + END + END wd_in[162] + PIN wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.036 27.384 ; + END + END wd_in[163] + PIN wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.408 0.036 27.432 ; + END + END wd_in[164] + PIN wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.456 0.036 27.480 ; + END + END wd_in[165] + PIN wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.036 27.528 ; + END + END wd_in[166] + PIN wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.552 0.036 27.576 ; + END + END wd_in[167] + PIN wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.600 0.036 27.624 ; + END + END wd_in[168] + PIN wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.036 27.672 ; + END + END wd_in[169] + PIN wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.036 27.720 ; + END + END wd_in[170] + PIN wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.744 0.036 27.768 ; + END + END wd_in[171] + PIN wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.036 27.816 ; + END + END wd_in[172] + PIN wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.840 0.036 27.864 ; + END + END wd_in[173] + PIN wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.888 0.036 27.912 ; + END + END wd_in[174] + PIN wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.036 27.960 ; + END + END wd_in[175] + PIN wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.984 0.036 28.008 ; + END + END wd_in[176] + PIN wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.032 0.036 28.056 ; + END + END wd_in[177] + PIN wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.036 28.104 ; + END + END wd_in[178] + PIN wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.128 0.036 28.152 ; + END + END wd_in[179] + PIN wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.176 0.036 28.200 ; + END + END wd_in[180] + PIN wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.036 28.248 ; + END + END wd_in[181] + PIN wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.036 28.296 ; + END + END wd_in[182] + PIN wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.320 0.036 28.344 ; + END + END wd_in[183] + PIN wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.036 28.392 ; + END + END wd_in[184] + PIN wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.416 0.036 28.440 ; + END + END wd_in[185] + PIN wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.464 0.036 28.488 ; + END + END wd_in[186] + PIN wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.036 28.536 ; + END + END wd_in[187] + PIN wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.560 0.036 28.584 ; + END + END wd_in[188] + PIN wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.608 0.036 28.632 ; + END + END wd_in[189] + PIN wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.036 28.680 ; + END + END wd_in[190] + PIN wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.704 0.036 28.728 ; + END + END wd_in[191] + PIN wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.752 0.036 28.776 ; + END + END wd_in[192] + PIN wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.036 28.824 ; + END + END wd_in[193] + PIN wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.036 28.872 ; + END + END wd_in[194] + PIN wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.896 0.036 28.920 ; + END + END wd_in[195] + PIN wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.036 28.968 ; + END + END wd_in[196] + PIN wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.992 0.036 29.016 ; + END + END wd_in[197] + PIN wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.040 0.036 29.064 ; + END + END wd_in[198] + PIN wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.036 29.112 ; + END + END wd_in[199] + PIN wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.136 0.036 29.160 ; + END + END wd_in[200] + PIN wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.184 0.036 29.208 ; + END + END wd_in[201] + PIN wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.036 29.256 ; + END + END wd_in[202] + PIN wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.280 0.036 29.304 ; + END + END wd_in[203] + PIN wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.328 0.036 29.352 ; + END + END wd_in[204] + PIN wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.036 29.400 ; + END + END wd_in[205] + PIN wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.036 29.448 ; + END + END wd_in[206] + PIN wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.472 0.036 29.496 ; + END + END wd_in[207] + PIN wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.036 29.544 ; + END + END wd_in[208] + PIN wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.568 0.036 29.592 ; + END + END wd_in[209] + PIN wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.616 0.036 29.640 ; + END + END wd_in[210] + PIN wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.036 29.688 ; + END + END wd_in[211] + PIN wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.712 0.036 29.736 ; + END + END wd_in[212] + PIN wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.760 0.036 29.784 ; + END + END wd_in[213] + PIN wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.036 29.832 ; + END + END wd_in[214] + PIN wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.856 0.036 29.880 ; + END + END wd_in[215] + PIN wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.904 0.036 29.928 ; + END + END wd_in[216] + PIN wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.036 29.976 ; + END + END wd_in[217] + PIN wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.036 30.024 ; + END + END wd_in[218] + PIN wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.048 0.036 30.072 ; + END + END wd_in[219] + PIN wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.036 30.120 ; + END + END wd_in[220] + PIN wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.144 0.036 30.168 ; + END + END wd_in[221] + PIN wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.192 0.036 30.216 ; + END + END wd_in[222] + PIN wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.036 30.264 ; + END + END wd_in[223] + PIN wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.288 0.036 30.312 ; + END + END wd_in[224] + PIN wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.336 0.036 30.360 ; + END + END wd_in[225] + PIN wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.036 30.408 ; + END + END wd_in[226] + PIN wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.432 0.036 30.456 ; + END + END wd_in[227] + PIN wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.480 0.036 30.504 ; + END + END wd_in[228] + PIN wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.036 30.552 ; + END + END wd_in[229] + PIN wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.036 30.600 ; + END + END wd_in[230] + PIN wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.624 0.036 30.648 ; + END + END wd_in[231] + PIN wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.036 30.696 ; + END + END wd_in[232] + PIN wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.720 0.036 30.744 ; + END + END wd_in[233] + PIN wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.768 0.036 30.792 ; + END + END wd_in[234] + PIN wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.036 30.840 ; + END + END wd_in[235] + PIN wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.864 0.036 30.888 ; + END + END wd_in[236] + PIN wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.912 0.036 30.936 ; + END + END wd_in[237] + PIN wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.036 30.984 ; + END + END wd_in[238] + PIN wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.008 0.036 31.032 ; + END + END wd_in[239] + PIN wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.056 0.036 31.080 ; + END + END wd_in[240] + PIN wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.036 31.128 ; + END + END wd_in[241] + PIN wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.036 31.176 ; + END + END wd_in[242] + PIN wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.200 0.036 31.224 ; + END + END wd_in[243] + PIN wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.036 31.272 ; + END + END wd_in[244] + PIN wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.296 0.036 31.320 ; + END + END wd_in[245] + PIN wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.344 0.036 31.368 ; + END + END wd_in[246] + PIN wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.036 31.416 ; + END + END wd_in[247] + PIN wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.440 0.036 31.464 ; + END + END wd_in[248] + PIN wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.488 0.036 31.512 ; + END + END wd_in[249] + PIN wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.036 31.560 ; + END + END wd_in[250] + PIN wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.584 0.036 31.608 ; + END + END wd_in[251] + PIN wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.632 0.036 31.656 ; + END + END wd_in[252] + PIN wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.036 31.704 ; + END + END wd_in[253] + PIN wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.036 31.752 ; + END + END wd_in[254] + PIN wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.776 0.036 31.800 ; + END + END wd_in[255] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.024 0.036 39.048 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.072 0.036 39.096 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.036 39.144 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.168 0.036 39.192 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.216 0.036 39.240 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.264 0.036 39.288 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.512 0.036 46.536 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.560 0.036 46.584 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.608 0.036 46.632 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 33.154 0.096 ; + RECT 0.096 0.768 33.154 0.864 ; + RECT 0.096 1.536 33.154 1.632 ; + RECT 0.096 2.304 33.154 2.400 ; + RECT 0.096 3.072 33.154 3.168 ; + RECT 0.096 3.840 33.154 3.936 ; + RECT 0.096 4.608 33.154 4.704 ; + RECT 0.096 5.376 33.154 5.472 ; + RECT 0.096 6.144 33.154 6.240 ; + RECT 0.096 6.912 33.154 7.008 ; + RECT 0.096 7.680 33.154 7.776 ; + RECT 0.096 8.448 33.154 8.544 ; + RECT 0.096 9.216 33.154 9.312 ; + RECT 0.096 9.984 33.154 10.080 ; + RECT 0.096 10.752 33.154 10.848 ; + RECT 0.096 11.520 33.154 11.616 ; + RECT 0.096 12.288 33.154 12.384 ; + RECT 0.096 13.056 33.154 13.152 ; + RECT 0.096 13.824 33.154 13.920 ; + RECT 0.096 14.592 33.154 14.688 ; + RECT 0.096 15.360 33.154 15.456 ; + RECT 0.096 16.128 33.154 16.224 ; + RECT 0.096 16.896 33.154 16.992 ; + RECT 0.096 17.664 33.154 17.760 ; + RECT 0.096 18.432 33.154 18.528 ; + RECT 0.096 19.200 33.154 19.296 ; + RECT 0.096 19.968 33.154 20.064 ; + RECT 0.096 20.736 33.154 20.832 ; + RECT 0.096 21.504 33.154 21.600 ; + RECT 0.096 22.272 33.154 22.368 ; + RECT 0.096 23.040 33.154 23.136 ; + RECT 0.096 23.808 33.154 23.904 ; + RECT 0.096 24.576 33.154 24.672 ; + RECT 0.096 25.344 33.154 25.440 ; + RECT 0.096 26.112 33.154 26.208 ; + RECT 0.096 26.880 33.154 26.976 ; + RECT 0.096 27.648 33.154 27.744 ; + RECT 0.096 28.416 33.154 28.512 ; + RECT 0.096 29.184 33.154 29.280 ; + RECT 0.096 29.952 33.154 30.048 ; + RECT 0.096 30.720 33.154 30.816 ; + RECT 0.096 31.488 33.154 31.584 ; + RECT 0.096 32.256 33.154 32.352 ; + RECT 0.096 33.024 33.154 33.120 ; + RECT 0.096 33.792 33.154 33.888 ; + RECT 0.096 34.560 33.154 34.656 ; + RECT 0.096 35.328 33.154 35.424 ; + RECT 0.096 36.096 33.154 36.192 ; + RECT 0.096 36.864 33.154 36.960 ; + RECT 0.096 37.632 33.154 37.728 ; + RECT 0.096 38.400 33.154 38.496 ; + RECT 0.096 39.168 33.154 39.264 ; + RECT 0.096 39.936 33.154 40.032 ; + RECT 0.096 40.704 33.154 40.800 ; + RECT 0.096 41.472 33.154 41.568 ; + RECT 0.096 42.240 33.154 42.336 ; + RECT 0.096 43.008 33.154 43.104 ; + RECT 0.096 43.776 33.154 43.872 ; + RECT 0.096 44.544 33.154 44.640 ; + RECT 0.096 45.312 33.154 45.408 ; + RECT 0.096 46.080 33.154 46.176 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 33.154 0.480 ; + RECT 0.096 1.152 33.154 1.248 ; + RECT 0.096 1.920 33.154 2.016 ; + RECT 0.096 2.688 33.154 2.784 ; + RECT 0.096 3.456 33.154 3.552 ; + RECT 0.096 4.224 33.154 4.320 ; + RECT 0.096 4.992 33.154 5.088 ; + RECT 0.096 5.760 33.154 5.856 ; + RECT 0.096 6.528 33.154 6.624 ; + RECT 0.096 7.296 33.154 7.392 ; + RECT 0.096 8.064 33.154 8.160 ; + RECT 0.096 8.832 33.154 8.928 ; + RECT 0.096 9.600 33.154 9.696 ; + RECT 0.096 10.368 33.154 10.464 ; + RECT 0.096 11.136 33.154 11.232 ; + RECT 0.096 11.904 33.154 12.000 ; + RECT 0.096 12.672 33.154 12.768 ; + RECT 0.096 13.440 33.154 13.536 ; + RECT 0.096 14.208 33.154 14.304 ; + RECT 0.096 14.976 33.154 15.072 ; + RECT 0.096 15.744 33.154 15.840 ; + RECT 0.096 16.512 33.154 16.608 ; + RECT 0.096 17.280 33.154 17.376 ; + RECT 0.096 18.048 33.154 18.144 ; + RECT 0.096 18.816 33.154 18.912 ; + RECT 0.096 19.584 33.154 19.680 ; + RECT 0.096 20.352 33.154 20.448 ; + RECT 0.096 21.120 33.154 21.216 ; + RECT 0.096 21.888 33.154 21.984 ; + RECT 0.096 22.656 33.154 22.752 ; + RECT 0.096 23.424 33.154 23.520 ; + RECT 0.096 24.192 33.154 24.288 ; + RECT 0.096 24.960 33.154 25.056 ; + RECT 0.096 25.728 33.154 25.824 ; + RECT 0.096 26.496 33.154 26.592 ; + RECT 0.096 27.264 33.154 27.360 ; + RECT 0.096 28.032 33.154 28.128 ; + RECT 0.096 28.800 33.154 28.896 ; + RECT 0.096 29.568 33.154 29.664 ; + RECT 0.096 30.336 33.154 30.432 ; + RECT 0.096 31.104 33.154 31.200 ; + RECT 0.096 31.872 33.154 31.968 ; + RECT 0.096 32.640 33.154 32.736 ; + RECT 0.096 33.408 33.154 33.504 ; + RECT 0.096 34.176 33.154 34.272 ; + RECT 0.096 34.944 33.154 35.040 ; + RECT 0.096 35.712 33.154 35.808 ; + RECT 0.096 36.480 33.154 36.576 ; + RECT 0.096 37.248 33.154 37.344 ; + RECT 0.096 38.016 33.154 38.112 ; + RECT 0.096 38.784 33.154 38.880 ; + RECT 0.096 39.552 33.154 39.648 ; + RECT 0.096 40.320 33.154 40.416 ; + RECT 0.096 41.088 33.154 41.184 ; + RECT 0.096 41.856 33.154 41.952 ; + RECT 0.096 42.624 33.154 42.720 ; + RECT 0.096 43.392 33.154 43.488 ; + RECT 0.096 44.160 33.154 44.256 ; + RECT 0.096 44.928 33.154 45.024 ; + RECT 0.096 45.696 33.154 45.792 ; + RECT 0.096 46.464 33.154 46.560 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 33.250 46.800 ; + LAYER M2 ; + RECT 0 0 33.250 46.800 ; + LAYER M3 ; + RECT 0 0 33.250 46.800 ; + LAYER M4 ; + RECT 0 0 33.250 46.800 ; + END +END fakeram7_64x256 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram7_64x28.lef b/flow/platforms/asap7/lef/fakeram7_64x28.lef new file mode 100644 index 0000000000..725ac02163 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram7_64x28.lef @@ -0,0 +1,644 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram7_64x28 + PROPERTY width 28 ; + PROPERTY depth 64 ; + PROPERTY banks 4 ; + FOREIGN fakeram7_64x28 0 0 ; + SYMMETRY X Y R90 ; + SIZE 14.630 BY 6.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.036 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.096 0.036 0.120 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.144 0.036 0.168 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.036 0.216 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.240 0.036 0.264 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.288 0.036 0.312 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.036 0.360 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.384 0.036 0.408 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.432 0.036 0.456 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.036 0.504 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.528 0.036 0.552 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.576 0.036 0.600 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.036 0.648 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.672 0.036 0.696 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.720 0.036 0.744 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.036 0.792 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.816 0.036 0.840 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.864 0.036 0.888 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.036 0.936 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.960 0.036 0.984 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.008 0.036 1.032 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.036 1.080 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.104 0.036 1.128 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.152 0.036 1.176 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.036 1.224 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.248 0.036 1.272 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.296 0.036 1.320 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.036 1.368 ; + END + END rd_out[27] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.304 0.036 2.328 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.036 2.376 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.400 0.036 2.424 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.448 0.036 2.472 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.036 2.520 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.544 0.036 2.568 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.592 0.036 2.616 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.036 2.664 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.688 0.036 2.712 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.736 0.036 2.760 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.036 2.808 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.832 0.036 2.856 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.880 0.036 2.904 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.036 2.952 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.976 0.036 3.000 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.024 0.036 3.048 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.036 3.096 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.120 0.036 3.144 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.168 0.036 3.192 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.036 3.240 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.264 0.036 3.288 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.312 0.036 3.336 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.036 3.384 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.408 0.036 3.432 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.456 0.036 3.480 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.036 3.528 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.552 0.036 3.576 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.600 0.036 3.624 ; + END + END wd_in[27] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.560 0.036 4.584 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.608 0.036 4.632 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.036 4.680 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.704 0.036 4.728 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.752 0.036 4.776 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.036 4.824 ; + END + END addr_in[5] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.760 0.036 5.784 ; + END + END we_in + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.036 5.832 ; + END + END ce_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.856 0.036 5.880 ; + END + END clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.096 0.000 14.534 0.096 ; + RECT 0.096 0.768 14.534 0.864 ; + RECT 0.096 1.536 14.534 1.632 ; + RECT 0.096 2.304 14.534 2.400 ; + RECT 0.096 3.072 14.534 3.168 ; + RECT 0.096 3.840 14.534 3.936 ; + RECT 0.096 4.608 14.534 4.704 ; + RECT 0.096 5.376 14.534 5.472 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.096 0.384 14.534 0.480 ; + RECT 0.096 1.152 14.534 1.248 ; + RECT 0.096 1.920 14.534 2.016 ; + RECT 0.096 2.688 14.534 2.784 ; + RECT 0.096 3.456 14.534 3.552 ; + RECT 0.096 4.224 14.534 4.320 ; + RECT 0.096 4.992 14.534 5.088 ; + RECT 0.096 5.760 14.534 5.856 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 14.630 6.000 ; + LAYER M2 ; + RECT 0 0 14.630 6.000 ; + LAYER M3 ; + RECT 0 0 14.630 6.000 ; + LAYER M4 ; + RECT 0 0 14.630 6.000 ; + END +END fakeram7_64x28 + +END LIBRARY diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib new file mode 100644 index 0000000000..8bcf2d6ae7 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_128x64.lib @@ -0,0 +1,389 @@ +library(fakeram7_128x64) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_128x64_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_128x64_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_128x64_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_128x64_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_128x64_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_128x64) { + area : 343.985; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 64; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_128x64_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_128x64_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_128x64_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_128x64_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_128x64_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_128x64_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_128x64_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_128x64_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib new file mode 100644 index 0000000000..c7cc1a8a94 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_256x256.lib @@ -0,0 +1,389 @@ +library(fakeram7_256x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-05-22 17:24:46Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_256x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_256x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_256x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_256x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_256x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_256x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_256x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_256x256) { + area : 2751.883; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_256x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_256x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_256x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_256x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_256x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_256x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_256x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_256x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib new file mode 100644 index 0000000000..1afa95f09b --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x25.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x25) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x25_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x25_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x25_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x25_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 25; + bit_from : 24; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x25_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x25) { + area : 67.185; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 25; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x25_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x25_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x25_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x25_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x25_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x25_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x25_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x25_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib new file mode 100644 index 0000000000..8282373b44 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x256.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x256) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-12 00:08:06Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x256_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x256_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x256_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x256_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x256_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x256) { + area : 1517.411; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 256; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x256_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x256_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x256_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x256_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x256_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x256_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x256_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x256_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib new file mode 100644 index 0000000000..1681b2bf1f --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram7_64x28.lib @@ -0,0 +1,389 @@ +library(fakeram7_64x28) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-06-10 17:10:26Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram7_64x28_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram7_64x28_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram7_64x28_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram7_64x28_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 28; + bit_from : 27; + bit_to : 0 ; + downto : true ; + } + type (fakeram7_64x28_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram7_64x28) { + area : 75.247; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 28; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram7_64x28_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram7_64x28_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram7_64x28_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram7_64x28_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram7_64x28_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram7_64x28_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram7_64x28_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram7_64x28_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/liberty_suppressions.tcl b/flow/platforms/asap7/liberty_suppressions.tcl new file mode 100644 index 0000000000..c1526671c0 --- /dev/null +++ b/flow/platforms/asap7/liberty_suppressions.tcl @@ -0,0 +1,5 @@ +# To remove [WARNING STA-1212] from the logs for ASAP7. +# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz +# line 13178, timing group from output port. +# Added following suppress_message +suppress_message STA 1212 diff --git a/flow/platforms/asap7/openRoad/make_tracks.tcl b/flow/platforms/asap7/openRoad/make_tracks.tcl index f404ab2209..ffd85fc94b 100644 --- a/flow/platforms/asap7/openRoad/make_tracks.tcl +++ b/flow/platforms/asap7/openRoad/make_tracks.tcl @@ -1,18 +1,18 @@ make_tracks Pad -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 -make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 -make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 -make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 -make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 -make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080 +make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064 +make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064 +make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048 +make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048 +make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 -make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270 +make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270 -make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 +make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036 diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl index 802b7340a9..d26c62c64b 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl @@ -18,10 +18,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} define_pdn_grid -name {top} -voltage_domains {CORE} add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504} +add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} \ + -core_offset {0.504} -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.50} -extend_to_core_ring -add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} -offset {1.504} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} \ + -offset {1.50} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M6} -width {0.288} -spacing {0.096} -pitch {4.32} \ + -offset {1.504} -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} @@ -40,8 +43,10 @@ foreach macro [find_macros] { } set macro_names [dict keys $macro_names] +set halo_x $::env(MACRO_ROWS_HALO_X) +set halo_y $::env(MACRO_ROWS_HALO_Y) define_pdn_grid -macro -cells $macro_names \ - -halo "$::env(MACRO_HALO_X) $::env(MACRO_HALO_Y) $::env(MACRO_HALO_X) $::env(MACRO_HALO_Y)" \ - -voltage_domains {CORE} -name ElementGrid + -halo "$halo_x $halo_y $halo_x $halo_y" \ + -voltage_domains {CORE} -name ElementGrid add_pdn_connect -grid {ElementGrid} -layers {M5 M6} diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl index 26234aae64..a5cb2dd041 100644 --- a/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl +++ b/flow/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl @@ -20,14 +20,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} #################################### define_pdn_grid -name {top} -voltage_domains {CORE} -add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} +add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} -add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins +add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins -add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring +add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} \ + -extend_to_core_ring add_pdn_connect -grid {top} -layers {M1 M2} add_pdn_connect -grid {top} -layers {M2 M5} add_pdn_connect -grid {top} -layers {M4 M5} - diff --git a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl index 0b19e5d69a..d3bcfa8a67 100644 --- a/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl +++ b/flow/platforms/asap7/openRoad/pdn/grid_strategy-M1-M2-M5-M6.tcl @@ -28,10 +28,12 @@ add_pdn_connect -grid {top} -layers {M5 M6} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_1} -layers {M4 M5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_connect -grid {CORE_macro_grid_2} -layers {M4 M5} diff --git a/flow/platforms/asap7/openRoad/tapcell.tcl b/flow/platforms/asap7/openRoad/tapcell.tcl index 6a14638ef6..809d6952aa 100644 --- a/flow/platforms/asap7/openRoad/tapcell.tcl +++ b/flow/platforms/asap7/openRoad/tapcell.tcl @@ -1,13 +1,14 @@ puts "Tap and End Cap cell insertion" puts " TAP Cell : $::env(TAP_CELL_NAME)" puts " ENDCAP Cell : $::env(TAP_CELL_NAME)" -puts " Halo Around Macro : $::env(MACRO_HALO_X) $::env(MACRO_HALO_Y)" +puts " Halo Around Macro : $::env(MACRO_ROWS_HALO_X) $::env(MACRO_ROWS_HALO_Y)" puts " TAP Cell Distance : 25" -# allow user to set the halo around macro with MACRO_HALO_? +# allow user to set the distance between the edges of the macros +# and the beginning of the core rows with MACRO_ROW_HALO_? tapcell \ -distance 25 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ - -endcap_master "$::env(TAP_CELL_NAME)" \ - -halo_width_x $::env(MACRO_HALO_X) \ - -halo_width_y $::env(MACRO_HALO_Y) + -endcap_master "$::env(TAP_CELL_NAME)" \ + -halo_width_x $::env(MACRO_ROWS_HALO_X) \ + -halo_width_y $::env(MACRO_ROWS_HALO_Y) diff --git a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl index 28c2da3eed..4751010d48 100644 --- a/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl +++ b/flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + set current_folder [file dirname [file normalize [info script]]] # Technology lib @@ -11,9 +13,9 @@ set ::env(LIB_SLOWEST) "" set lib_path "$libs_ref/lib" foreach lib {"AO" "INVBUF" "OA" "SEQ" "SIMPLE"} { - append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " - append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " - append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " + append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib " + append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib " + append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib " } set ::env(LIB_SYNTH) $::env(LIB_TYPICAL) @@ -36,7 +38,7 @@ set ::env(FP_ENDCAP_CELL) "TAPCELL_ASAP7_75t_R" # defaults (can be overridden by designs): set ::env(SYNTH_DRIVING_CELL) "BUFx2_ASAP7_75t_R" set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "4.61057" ; # femtofarad INVx8_ASAP7_75t_R pin A cap +set ::env(SYNTH_CAP_LOAD) "4.61057" ;# femtofarad INVx8_ASAP7_75t_R pin A cap set ::env(SYNTH_MIN_BUF_PORT) "BUFx2_ASAP7_75t_R A Y" set ::env(SYNTH_TIEHI_PORT) "TIEHIx1_ASAP7_75t_R H" set ::env(SYNTH_TIELO_PORT) "TIELOx1_ASAP7_75t_R L" diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl index d7a4ee0bd1..8724cdef98 100755 --- a/flow/platforms/asap7/openlane/config.tcl +++ b/flow/platforms/asap7/openlane/config.tcl @@ -1,3 +1,5 @@ +# tclint-disable line-length + # Process node set ::env(PROCESS) 7 set ::env(DEF_UNITS_PER_MICRON) 1000 @@ -15,7 +17,7 @@ set ::env(STD_CELL_GROUND_PINS) "VSS" set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef" set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"] set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" +set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl" set ::env(GPIO_PADS_LEF) "" @@ -25,7 +27,7 @@ set ::env(GPIO_PADS_VERILOG) "" set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef" set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"] set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"] -set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" +set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl" # Optimization library slowest corner diff --git a/flow/platforms/asap7/ram/cva6.cfg b/flow/platforms/asap7/ram/cva6.cfg new file mode 100644 index 0000000000..a7d378fa0e --- /dev/null +++ b/flow/platforms/asap7/ram/cva6.cfg @@ -0,0 +1,50 @@ +#SAMPLE INPUT FILE; VALUES NOT REALISTIC +{ + # The process node. + "tech_nm": 7, + + # The operating voltage. + "voltage": 0.7, + + # String to add in front of every metal layer number for the layer name. + "metal_prefix": "M", + + # Horizontal Metal layer for macro pins + "metal_layer": "M4", + + # The pin width for signal pins. + "pin_width_nm": 24, + + # The minimum pin pitch for signal pins + "pin_pitch_nm": 48, + + # Metal track pitch + "metal_track_pitch_nm": 48, + + # Manufacturing Grid + "manufacturing_grid_nm": 1, + + # Contacted Poly Pitch + "contacted_poly_pitch_nm": 54, + + #column mux factor + "column_mux_factor": 1, + + # Fin pitch + "fin_pitch_nm" : 27, + + # Optional snap the width and height of the sram to a multiple value. + "snap_width_nm": 190, + "snap_height_nm": 1200, + + # List of SRAM configurations (name width depth and banks) + "srams": [ + {"name": "fakeram7_64x28", "width": 28, "depth": 64, "banks": 4}, + {"name": "fakeram7_128x64", "width": 64, "depth": 128, "banks": 2}, + {"name": "fakeram7_64x25", "width": 25, "depth": 64, "banks": 4}, + {"name": "fakeram7_64x256", "width": 256, "depth": 64, "banks": 1, + "additional_height": 25} + ] + + # TENTATIVE PARAMETERS +} diff --git a/flow/platforms/asap7/setRC.tcl b/flow/platforms/asap7/setRC.tcl index 2a741ef815..d1d988b362 100644 --- a/flow/platforms/asap7/setRC.tcl +++ b/flow/platforms/asap7/setRC.tcl @@ -1,13 +1,14 @@ -# Liberty units are fF,kOhm -set_layer_rc -layer M1 -capacitance 1.1368e-01 -resistance 1.3889e-01 -set_layer_rc -layer M2 -capacitance 1.3426e-01 -resistance 2.4222e-02 -set_layer_rc -layer M3 -capacitance 1.2918e-01 -resistance 2.4222e-02 -set_layer_rc -layer M4 -capacitance 1.1396e-01 -resistance 1.6778e-02 -set_layer_rc -layer M5 -capacitance 1.3323e-01 -resistance 1.4677e-02 -set_layer_rc -layer M6 -capacitance 1.1575e-01 -resistance 1.0371e-02 -set_layer_rc -layer M7 -capacitance 1.3293e-01 -resistance 9.6720e-03 -set_layer_rc -layer M8 -capacitance 1.1822e-01 -resistance 7.4310e-03 -set_layer_rc -layer M9 -capacitance 1.3497e-01 -resistance 6.8740e-03 +# correlation result (aes, cva6, ibex, riscv32i) +# M1 capacitance fixed up from -4.8e-02 to 1e-10 as a minuscule positive value +set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance 1e-10 +set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01 +set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01 +set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01 +set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01 +set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01 +set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01 +set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01 +set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01 set_layer_rc -via V1 -resistance 1.72E-02 set_layer_rc -via V2 -resistance 1.72E-02 @@ -17,5 +18,3 @@ set_layer_rc -via V5 -resistance 1.18E-02 set_layer_rc -via V6 -resistance 8.20E-03 set_layer_rc -via V7 -resistance 8.20E-03 set_layer_rc -via V8 -resistance 6.30E-03 - -set_wire_rc -layer M3 diff --git a/flow/platforms/asap7/verilog/fakeram7_128x64.sv b/flow/platforms/asap7/verilog/fakeram7_128x64.sv new file mode 100644 index 0000000000..d7353e1c65 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_128x64.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_128x64 ( + output reg [63:0] rd_out, + input [6:0] addr_in, + input we_in, + input [63:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_256x256.sv b/flow/platforms/asap7/verilog/fakeram7_256x256.sv new file mode 100644 index 0000000000..8f440cbf49 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_256x256.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_256x256 ( + output reg [255:0] rd_out, + input [7:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_256x256.v b/flow/platforms/asap7/verilog/fakeram7_256x256.v new file mode 100644 index 0000000000..864f474766 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_256x256.v @@ -0,0 +1,70 @@ +module fakeram7_256x256 +( + rd_out, + addr_in, + we_in, + wd_in, + clk, + ce_in +); + parameter BITS = 256; + parameter WORD_DEPTH = 256; + parameter ADDR_WIDTH = 8; + parameter corrupt_mem_on_X_p = 1; + + output reg [BITS-1:0] rd_out; + input [ADDR_WIDTH-1:0] addr_in; + input we_in; + input [BITS-1:0] wd_in; + input clk; + input ce_in; + + reg [BITS-1:0] mem [0:WORD_DEPTH-1]; + + integer j; + + always @(posedge clk) + begin + if (ce_in) + begin + //if ((we_in !== 1'b1 && we_in !== 1'b0) && corrupt_mem_on_X_p) + if (corrupt_mem_on_X_p && + ((^we_in === 1'bx) || (^addr_in === 1'bx)) + ) + begin + // WEN or ADDR is unknown, so corrupt entire array (using unsynthesizeable for loop) + for (j = 0; j < WORD_DEPTH; j = j + 1) + mem[j] <= 'x; + $display("warning: ce_in=1, we_in is %b, addr_in = %x in fakeram7_256x256", we_in, addr_in); + end + else if (we_in) + begin + mem[addr_in] <= (wd_in) | (mem[addr_in]); + end + // read + rd_out <= mem[addr_in]; + end + else + begin + // Make sure read fails if ce_in is low + rd_out <= 'x; + end + end + + // Timing check placeholders (will be replaced during SDF back-annotation) + reg notifier; + specify + // Delay from clk to rd_out + (posedge clk *> rd_out) = (0, 0); + + // Timing checks + $width (posedge clk, 0, 0, notifier); + $width (negedge clk, 0, 0, notifier); + $period (posedge clk, 0, notifier); + $setuphold (posedge clk, we_in, 0, 0, notifier); + $setuphold (posedge clk, ce_in, 0, 0, notifier); + $setuphold (posedge clk, addr_in, 0, 0, notifier); + $setuphold (posedge clk, wd_in, 0, 0, notifier); + endspecify + +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_256x32.sv b/flow/platforms/asap7/verilog/fakeram7_256x32.sv new file mode 100644 index 0000000000..30383411ba --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_256x32.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_256x32 ( + output reg [31:0] rd_out, + input [7:0] addr_in, + input we_in, + input [31:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x25.sv b/flow/platforms/asap7/verilog/fakeram7_64x25.sv new file mode 100644 index 0000000000..4d2c60724d --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x25.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x25 ( + output reg [24:0] rd_out, + input [5:0] addr_in, + input we_in, + input [24:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x256.sv b/flow/platforms/asap7/verilog/fakeram7_64x256.sv new file mode 100644 index 0000000000..b87ffae7d7 --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x256.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x256 ( + output reg [255:0] rd_out, + input [5:0] addr_in, + input we_in, + input [255:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram7_64x28.sv b/flow/platforms/asap7/verilog/fakeram7_64x28.sv new file mode 100644 index 0000000000..7ed704addd --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram7_64x28.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram7_64x28 ( + output reg [27:0] rd_out, + input [5:0] addr_in, + input we_in, + input [27:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc6t_INVBUF_RVT_FF_210930.v b/flow/platforms/asap7/work_around_yosys/asap7sc6t_INVBUF_RVT_FF_210930.v deleted file mode 100644 index 4ccad4900b..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc6t_INVBUF_RVT_FF_210930.v +++ /dev/null @@ -1,475 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2021 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc6T_INVBUF_RVT_FF_210905 created by Liberate 18.1.0.293 on Thu Sep 16 23:50:24 MST 2021 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx10_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx12_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx12q_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx16q_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx24_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx2_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx3_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx4_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx4q_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx5_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx6q_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx8_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB1x1_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB2x1_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB3x1_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB4x1_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx11_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx13_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx1_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx2_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx3_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx4_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx5_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx6_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx8_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVxp5_ASAP7_6t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_RVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_RVT_TT_201020.v deleted file mode 100644 index 1831fce7da..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_AO_RVT_TT_201020.v +++ /dev/null @@ -1,3627 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_AO_RVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 03:36:02 MST 2020 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module A2O1A1Ixp33_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar); - or (Y, int_fwire_1, int_fwire_0, C__bar); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module A2O1A1O1Ixp25_ASAP7_75t_R (Y, A1, A2, B, C, D); - output Y; - input A1, A2, B, C, D; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, D__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2; - - not (D__bar, D); - not (C__bar, C); - and (int_fwire_0, C__bar, D__bar); - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_1, A2__bar, B__bar, D__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B__bar, D__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO211x2_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire int_fwire_0; - - and (int_fwire_0, A1, A2); - or (Y, int_fwire_0, B, C); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO21x1_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire int_fwire_0; - - and (int_fwire_0, A1, A2); - or (Y, int_fwire_0, B); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO21x2_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire int_fwire_0; - - and (int_fwire_0, A1, A2); - or (Y, int_fwire_0, B); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO221x1_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2); - or (Y, int_fwire_1, int_fwire_0, C); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO221x2_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2); - or (Y, int_fwire_1, int_fwire_0, C); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO222x2_ASAP7_75t_R (Y, A1, A2, B1, B2, C1, C2); - output Y; - input A1, A2, B1, B2, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2); - and (int_fwire_1, B1, B2); - and (int_fwire_2, A1, A2); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO22x1_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2); - or (Y, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO22x2_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2); - or (Y, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO31x2_ASAP7_75t_R (Y, A1, A2, A3, B); - output Y; - input A1, A2, A3, B; - - // Function - wire int_fwire_0; - - and (int_fwire_0, A1, A2, A3); - or (Y, int_fwire_0, B); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO322x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, C1, C2); - output Y; - input A1, A2, A3, B1, B2, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2); - and (int_fwire_1, B1, B2); - and (int_fwire_2, A1, A2, A3); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO32x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2); - output Y; - input A1, A2, A3, B1, B2; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2, A3); - or (Y, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO32x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2); - output Y; - input A1, A2, A3, B1, B2; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2); - and (int_fwire_1, A1, A2, A3); - or (Y, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO331x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C); - output Y; - input A1, A2, A3, B1, B2, B3, C; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2, B3); - and (int_fwire_1, A1, A2, A3); - or (Y, int_fwire_1, int_fwire_0, C); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO331x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C); - output Y; - input A1, A2, A3, B1, B2, B3, C; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2, B3); - and (int_fwire_1, A1, A2, A3); - or (Y, int_fwire_1, int_fwire_0, C); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO332x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2); - and (int_fwire_1, B1, B2, B3); - and (int_fwire_2, A1, A2, A3); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO332x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2); - and (int_fwire_1, B1, B2, B3); - and (int_fwire_2, A1, A2, A3); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO333x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2, C3); - and (int_fwire_1, B1, B2, B3); - and (int_fwire_2, A1, A2, A3); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO333x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, C1, C2, C3); - and (int_fwire_1, B1, B2, B3); - and (int_fwire_2, A1, A2, A3); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AO33x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3); - output Y; - input A1, A2, A3, B1, B2, B3; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, B1, B2, B3); - and (int_fwire_1, A1, A2, A3); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3) | (~A1 & ~A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3) | (~A1 & ~A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2) | (~A1 & ~A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI211x1_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar, C__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & ~C)) - (B => Y) = 0; - if ((~A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & ~B)) - (C => Y) = 0; - if ((~A1 & A2 & ~B)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI211xp5_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar, C__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & ~C)) - (B => Y) = 0; - if ((~A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & ~B)) - (C => Y) = 0; - if ((~A1 & A2 & ~B)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI21x1_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0, int_fwire_1; - - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - if ((~A1 & ~A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI21xp33_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0, int_fwire_1; - - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - if ((~A1 & ~A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI21xp5_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0, int_fwire_1; - - not (B__bar, B); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - if ((~A1 & ~A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI221x1_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, C__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2, int_fwire_3; - - not (C__bar, C); - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar, C__bar); - not (B1__bar, B1); - and (int_fwire_1, A2__bar, B1__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B2__bar, C__bar); - and (int_fwire_3, A1__bar, B1__bar, C__bar); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & ~B2) | (~A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI221xp5_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, C__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2, int_fwire_3; - - not (C__bar, C); - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar, C__bar); - not (B1__bar, B1); - and (int_fwire_1, A2__bar, B1__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B2__bar, C__bar); - and (int_fwire_3, A1__bar, B1__bar, C__bar); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2 & ~C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI222xp33_ASAP7_75t_R (Y, A1, A2, B1, B2, C1, C2); - output Y; - input A1, A2, B1, B2, C1, C2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, C1__bar, C2__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7; - - not (C2__bar, C2); - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar, C2__bar); - not (C1__bar, C1); - and (int_fwire_1, A2__bar, B2__bar, C1__bar); - not (B1__bar, B1); - and (int_fwire_2, A2__bar, B1__bar, C2__bar); - and (int_fwire_3, A2__bar, B1__bar, C1__bar); - not (A1__bar, A1); - and (int_fwire_4, A1__bar, B2__bar, C2__bar); - and (int_fwire_5, A1__bar, B2__bar, C1__bar); - and (int_fwire_6, A1__bar, B1__bar, C2__bar); - and (int_fwire_7, A1__bar, B1__bar, C1__bar); - or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & B1 & ~B2 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2 & ~C1 & ~C2) | (A2 & ~B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & B1 & ~B2 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2 & ~C1 & ~C2) | (A1 & ~B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI22x1_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2, int_fwire_3; - - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar); - not (B1__bar, B1); - and (int_fwire_1, A2__bar, B1__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B2__bar); - and (int_fwire_3, A1__bar, B1__bar); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI22xp33_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2, int_fwire_3; - - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar); - not (B1__bar, B1); - and (int_fwire_1, A2__bar, B1__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B2__bar); - and (int_fwire_3, A1__bar, B1__bar); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI22xp5_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2, int_fwire_3; - - not (B2__bar, B2); - not (A2__bar, A2); - and (int_fwire_0, A2__bar, B2__bar); - not (B1__bar, B1); - and (int_fwire_1, A2__bar, B1__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B2__bar); - and (int_fwire_3, A1__bar, B1__bar); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((A2 & ~B1 & ~B2)) - (A1 => Y) = 0; - if ((A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & ~B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & B2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & B1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI311xp33_ASAP7_75t_R (Y, A1, A2, A3, B, C); - output Y; - input A1, A2, A3, B, C; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B__bar, C__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2; - - not (C__bar, C); - not (B__bar, B); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B__bar, C__bar); - not (A2__bar, A2); - and (int_fwire_1, A2__bar, B__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B__bar, C__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & A3 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & A3 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & ~A3 & ~C) | (~A1 & ~A2 & A3 & ~C)) - (B => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~C)) - (B => Y) = 0; - if ((A1 & A2 & ~A3 & ~B)) - (C => Y) = 0; - if ((A1 & ~A2 & A3 & ~B)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & ~B)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B) | (~A1 & ~A2 & A3 & ~B)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI31xp33_ASAP7_75t_R (Y, A1, A2, A3, B); - output Y; - input A1, A2, A3, B; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2; - - not (B__bar, B); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B__bar); - not (A2__bar, A2); - and (int_fwire_1, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & ~A3)) - (B => Y) = 0; - if ((A1 & ~A2 & A3)) - (B => Y) = 0; - if ((A1 & ~A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & A2 & A3)) - (B => Y) = 0; - if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) - (B => Y) = 0; - if ((~A1 & ~A2 & ~A3)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI31xp67_ASAP7_75t_R (Y, A1, A2, A3, B); - output Y; - input A1, A2, A3, B; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2; - - not (B__bar, B); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B__bar); - not (A2__bar, A2); - and (int_fwire_1, A2__bar, B__bar); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, B__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & ~A3)) - (B => Y) = 0; - if ((A1 & ~A2 & A3)) - (B => Y) = 0; - if ((A1 & ~A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & A2 & A3)) - (B => Y) = 0; - if ((~A1 & A2 & ~A3) | (~A1 & ~A2 & A3)) - (B => Y) = 0; - if ((~A1 & ~A2 & ~A3)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI321xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, C); - output Y; - input A1, A2, A3, B1, B2, C; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, C__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - - not (C__bar, C); - not (B2__bar, B2); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B2__bar, C__bar); - not (B1__bar, B1); - and (int_fwire_1, A3__bar, B1__bar, C__bar); - not (A2__bar, A2); - and (int_fwire_2, A2__bar, B2__bar, C__bar); - and (int_fwire_3, A2__bar, B1__bar, C__bar); - not (A1__bar, A1); - and (int_fwire_4, A1__bar, B2__bar, C__bar); - and (int_fwire_5, A1__bar, B1__bar, C__bar); - or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~C)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~C)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~C)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~C)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & ~C) | (~A1 & ~A2 & A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & ~C)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~C) | (~A1 & ~A2 & A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~C)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2) | (~A1 & ~A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2) | (~A1 & ~A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2) | (~A1 & ~A2 & A3 & ~B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI322xp5_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, C1, C2); - output Y; - input A1, A2, A3, B1, B2, C1, C2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, C1__bar; - wire C2__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2, int_fwire_3, int_fwire_4; - wire int_fwire_5, int_fwire_6, int_fwire_7; - wire int_fwire_8, int_fwire_9, int_fwire_10; - wire int_fwire_11; - - not (C2__bar, C2); - not (B2__bar, B2); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B2__bar, C2__bar); - not (C1__bar, C1); - and (int_fwire_1, A3__bar, B2__bar, C1__bar); - not (B1__bar, B1); - and (int_fwire_2, A3__bar, B1__bar, C2__bar); - and (int_fwire_3, A3__bar, B1__bar, C1__bar); - not (A2__bar, A2); - and (int_fwire_4, A2__bar, B2__bar, C2__bar); - and (int_fwire_5, A2__bar, B2__bar, C1__bar); - and (int_fwire_6, A2__bar, B1__bar, C2__bar); - and (int_fwire_7, A2__bar, B1__bar, C1__bar); - not (A1__bar, A1); - and (int_fwire_8, A1__bar, B2__bar, C2__bar); - and (int_fwire_9, A1__bar, B2__bar, C1__bar); - and (int_fwire_10, A1__bar, B1__bar, C2__bar); - and (int_fwire_11, A1__bar, B1__bar, C1__bar); - or (Y, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI32xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2); - output Y; - input A1, A2, A3, B1, B2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2, int_fwire_3; - wire int_fwire_4, int_fwire_5; - - not (B2__bar, B2); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B2__bar); - not (B1__bar, B1); - and (int_fwire_1, A3__bar, B1__bar); - not (A2__bar, A2); - and (int_fwire_2, A2__bar, B2__bar); - and (int_fwire_3, A2__bar, B1__bar); - not (A1__bar, A1); - and (int_fwire_4, A1__bar, B2__bar); - and (int_fwire_5, A1__bar, B1__bar); - or (Y, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & ~B2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & ~B2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2) | (~A1 & ~A2 & A3 & B2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1) | (~A1 & ~A2 & A3 & B1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI331xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1); - output Y; - input A1, A2, A3, B1, B2, B3, C1; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2, int_fwire_3, int_fwire_4; - wire int_fwire_5, int_fwire_6, int_fwire_7; - wire int_fwire_8; - - not (C1__bar, C1); - not (B3__bar, B3); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B3__bar, C1__bar); - not (B2__bar, B2); - and (int_fwire_1, A3__bar, B2__bar, C1__bar); - not (B1__bar, B1); - and (int_fwire_2, A3__bar, B1__bar, C1__bar); - not (A2__bar, A2); - and (int_fwire_3, A2__bar, B3__bar, C1__bar); - and (int_fwire_4, A2__bar, B2__bar, C1__bar); - and (int_fwire_5, A2__bar, B1__bar, C1__bar); - not (A1__bar, A1); - and (int_fwire_6, A1__bar, B3__bar, C1__bar); - and (int_fwire_7, A1__bar, B2__bar, C1__bar); - and (int_fwire_8, A1__bar, B1__bar, C1__bar); - or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI332xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, C2__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2, int_fwire_3; - wire int_fwire_4, int_fwire_5, int_fwire_6; - wire int_fwire_7, int_fwire_8, int_fwire_9; - wire int_fwire_10, int_fwire_11, int_fwire_12; - wire int_fwire_13, int_fwire_14, int_fwire_15; - wire int_fwire_16, int_fwire_17; - - not (C2__bar, C2); - not (B3__bar, B3); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B3__bar, C2__bar); - not (C1__bar, C1); - and (int_fwire_1, A3__bar, B3__bar, C1__bar); - not (B2__bar, B2); - and (int_fwire_2, A3__bar, B2__bar, C2__bar); - and (int_fwire_3, A3__bar, B2__bar, C1__bar); - not (B1__bar, B1); - and (int_fwire_4, A3__bar, B1__bar, C2__bar); - and (int_fwire_5, A3__bar, B1__bar, C1__bar); - not (A2__bar, A2); - and (int_fwire_6, A2__bar, B3__bar, C2__bar); - and (int_fwire_7, A2__bar, B3__bar, C1__bar); - and (int_fwire_8, A2__bar, B2__bar, C2__bar); - and (int_fwire_9, A2__bar, B2__bar, C1__bar); - and (int_fwire_10, A2__bar, B1__bar, C2__bar); - and (int_fwire_11, A2__bar, B1__bar, C1__bar); - not (A1__bar, A1); - and (int_fwire_12, A1__bar, B3__bar, C2__bar); - and (int_fwire_13, A1__bar, B3__bar, C1__bar); - and (int_fwire_14, A1__bar, B2__bar, C2__bar); - and (int_fwire_15, A1__bar, B2__bar, C1__bar); - and (int_fwire_16, A1__bar, B1__bar, C2__bar); - and (int_fwire_17, A1__bar, B1__bar, C1__bar); - or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI333xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, C2__bar, C3__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - wire int_fwire_9, int_fwire_10, int_fwire_11; - wire int_fwire_12, int_fwire_13, int_fwire_14; - wire int_fwire_15, int_fwire_16, int_fwire_17; - wire int_fwire_18, int_fwire_19, int_fwire_20; - wire int_fwire_21, int_fwire_22, int_fwire_23; - wire int_fwire_24, int_fwire_25, int_fwire_26; - - not (C3__bar, C3); - not (B3__bar, B3); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B3__bar, C3__bar); - not (C2__bar, C2); - and (int_fwire_1, A3__bar, B3__bar, C2__bar); - not (C1__bar, C1); - and (int_fwire_2, A3__bar, B3__bar, C1__bar); - not (B2__bar, B2); - and (int_fwire_3, A3__bar, B2__bar, C3__bar); - and (int_fwire_4, A3__bar, B2__bar, C2__bar); - and (int_fwire_5, A3__bar, B2__bar, C1__bar); - not (B1__bar, B1); - and (int_fwire_6, A3__bar, B1__bar, C3__bar); - and (int_fwire_7, A3__bar, B1__bar, C2__bar); - and (int_fwire_8, A3__bar, B1__bar, C1__bar); - not (A2__bar, A2); - and (int_fwire_9, A2__bar, B3__bar, C3__bar); - and (int_fwire_10, A2__bar, B3__bar, C2__bar); - and (int_fwire_11, A2__bar, B3__bar, C1__bar); - and (int_fwire_12, A2__bar, B2__bar, C3__bar); - and (int_fwire_13, A2__bar, B2__bar, C2__bar); - and (int_fwire_14, A2__bar, B2__bar, C1__bar); - and (int_fwire_15, A2__bar, B1__bar, C3__bar); - and (int_fwire_16, A2__bar, B1__bar, C2__bar); - and (int_fwire_17, A2__bar, B1__bar, C1__bar); - not (A1__bar, A1); - and (int_fwire_18, A1__bar, B3__bar, C3__bar); - and (int_fwire_19, A1__bar, B3__bar, C2__bar); - and (int_fwire_20, A1__bar, B3__bar, C1__bar); - and (int_fwire_21, A1__bar, B2__bar, C3__bar); - and (int_fwire_22, A1__bar, B2__bar, C2__bar); - and (int_fwire_23, A1__bar, B2__bar, C1__bar); - and (int_fwire_24, A1__bar, B1__bar, C3__bar); - and (int_fwire_25, A1__bar, B1__bar, C2__bar); - and (int_fwire_26, A1__bar, B1__bar, C1__bar); - or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3 & ~C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3 & ~C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3 & ~C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C2 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C2 & C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C2 & C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C3) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~B3 & C1 & C2)) - (C3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AOI33xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3); - output Y; - input A1, A2, A3, B1, B2, B3; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - - not (B3__bar, B3); - not (A3__bar, A3); - and (int_fwire_0, A3__bar, B3__bar); - not (B2__bar, B2); - and (int_fwire_1, A3__bar, B2__bar); - not (B1__bar, B1); - and (int_fwire_2, A3__bar, B1__bar); - not (A2__bar, A2); - and (int_fwire_3, A2__bar, B3__bar); - and (int_fwire_4, A2__bar, B2__bar); - and (int_fwire_5, A2__bar, B1__bar); - not (A1__bar, A1); - and (int_fwire_6, A1__bar, B3__bar); - and (int_fwire_7, A1__bar, B2__bar); - and (int_fwire_8, A1__bar, B1__bar); - or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((A2 & A3 & B1 & B2 & ~B3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & B2 & ~B3) | (A2 & A3 & ~B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((A2 & A3 & ~B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((A1 & A3 & B1 & B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & B2 & ~B3) | (A1 & A3 & ~B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((A1 & A3 & ~B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~B3) | (A1 & A2 & ~B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((A1 & A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B2 & B3) | (~A1 & A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B2 & B3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B2 & B3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B3) | (~A1 & A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2) | (~A1 & A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & ~A3 & B1 & B2)) - (B3 => Y) = 0; - endspecify -endmodule -`endcelldefine - diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_RVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_RVT_TT_201020.v deleted file mode 100644 index 58b0e4fa71..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_INVBUF_RVT_TT_201020.v +++ /dev/null @@ -1,663 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_INVBUF_RVT_TT_201020 created by Liberate 18.1.0.293 on Mon Dec 7 13:57:05 MST 2020 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx10_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx12_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx12f_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx16f_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx24_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx2_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx3_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx4_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx4f_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx5_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx6f_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module BUFx8_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx10_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx11_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx12_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx14_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx16_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx20_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx5p33_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx6p67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx8_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module CKINVDCx9p33_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB1xp67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB2xp67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB3xp67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HB4xp67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - buf (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx11_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx13_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx1_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx2_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx3_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx4_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx5_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx6_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVx8_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVxp33_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module INVxp67_ASAP7_75t_R (Y, A); - output Y; - input A; - - // Function - not (Y, A); - - // Timing - specify - (A => Y) = 0; - endspecify -endmodule -`endcelldefine - - diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_RVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_RVT_TT_201020.v deleted file mode 100644 index 513c34a526..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_OA_RVT_TT_201020.v +++ /dev/null @@ -1,5243 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_OA_RVT_TT_201020 created by Liberate 18.1.0.293 on Sat Nov 28 13:55:21 MST 2020 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module O2A1O1Ixp33_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B__bar, B); - and (int_fwire_0, B__bar, C__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, C__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & ~C)) - (B => Y) = 0; - if ((A1 & A2 & ~B)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B)) - (C => Y) = 0; - if ((~A1 & A2 & ~B)) - (C => Y) = 0; - if ((~A1 & ~A2 & B)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module O2A1O1Ixp5_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B__bar, B); - and (int_fwire_0, B__bar, C__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, C__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2 & ~C)) - (B => Y) = 0; - if ((A1 & ~A2 & ~C)) - (B => Y) = 0; - if ((~A1 & A2 & ~C)) - (B => Y) = 0; - if ((A2 & ~B)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B)) - (C => Y) = 0; - if ((~A1 & ~A2 & B)) - (C => Y) = 0; - if ((~A1 & ~A2 & ~B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA211x2_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, A2, B, C); - and (int_fwire_1, A1, B, C); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2 & C)) - (B => Y) = 0; - if ((A1 & ~A2 & C)) - (B => Y) = 0; - if ((~A1 & A2 & C)) - (B => Y) = 0; - if ((A1 & A2 & B)) - (C => Y) = 0; - if ((A1 & ~A2 & B)) - (C => Y) = 0; - if ((~A1 & A2 & B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA21x2_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire int_fwire_0, int_fwire_1; - - and (int_fwire_0, A2, B); - and (int_fwire_1, A1, B); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2)) - (B => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA221x2_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3; - - and (int_fwire_0, A2, B2, C); - and (int_fwire_1, A2, B1, C); - and (int_fwire_2, A1, B2, C); - and (int_fwire_3, A1, B1, C); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & C)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2 & C)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & C)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & A2 & B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & A2 & ~B1 & B2) | (~A1 & A2 & B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA222x2_ASAP7_75t_R (Y, A1, A2, B1, B2, C1, C2); - output Y; - input A1, A2, B1, B2, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7; - - and (int_fwire_0, A2, B2, C2); - and (int_fwire_1, A2, B2, C1); - and (int_fwire_2, A2, B1, C2); - and (int_fwire_3, A2, B1, C1); - and (int_fwire_4, A1, B2, C2); - and (int_fwire_5, A1, B2, C1); - and (int_fwire_6, A1, B1, C2); - and (int_fwire_7, A1, B1, C1); - or (Y, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA22x2_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3; - - and (int_fwire_0, A2, B2); - and (int_fwire_1, A2, B1); - and (int_fwire_2, A1, B2); - and (int_fwire_3, A1, B1); - or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA31x2_ASAP7_75t_R (Y, A1, A2, A3, B1); - output Y; - input A1, A2, A3, B1; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, A3, B1); - and (int_fwire_1, A2, B1); - and (int_fwire_2, A1, B1); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & A3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3) | (~A1 & A2 & A3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3)) - (B1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA331x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1); - output Y; - input A1, A2, A3, B1, B2, B3, C1; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - - and (int_fwire_0, A3, B3, C1); - and (int_fwire_1, A3, B2, C1); - and (int_fwire_2, A3, B1, C1); - and (int_fwire_3, A2, B3, C1); - and (int_fwire_4, A2, B2, C1); - and (int_fwire_5, A2, B1, C1); - and (int_fwire_6, A1, B3, C1); - and (int_fwire_7, A1, B2, C1); - and (int_fwire_8, A1, B1, C1); - or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA331x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1); - output Y; - input A1, A2, A3, B1, B2, B3, C1; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - - and (int_fwire_0, A3, B3, C1); - and (int_fwire_1, A3, B2, C1); - and (int_fwire_2, A3, B1, C1); - and (int_fwire_3, A2, B3, C1); - and (int_fwire_4, A2, B2, C1); - and (int_fwire_5, A2, B1, C1); - and (int_fwire_6, A1, B3, C1); - and (int_fwire_7, A1, B2, C1); - and (int_fwire_8, A1, B1, C1); - or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA332x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - wire int_fwire_9, int_fwire_10, int_fwire_11; - wire int_fwire_12, int_fwire_13, int_fwire_14; - wire int_fwire_15, int_fwire_16, int_fwire_17; - - and (int_fwire_0, A3, B3, C2); - and (int_fwire_1, A3, B3, C1); - and (int_fwire_2, A3, B2, C2); - and (int_fwire_3, A3, B2, C1); - and (int_fwire_4, A3, B1, C2); - and (int_fwire_5, A3, B1, C1); - and (int_fwire_6, A2, B3, C2); - and (int_fwire_7, A2, B3, C1); - and (int_fwire_8, A2, B2, C2); - and (int_fwire_9, A2, B2, C1); - and (int_fwire_10, A2, B1, C2); - and (int_fwire_11, A2, B1, C1); - and (int_fwire_12, A1, B3, C2); - and (int_fwire_13, A1, B3, C1); - and (int_fwire_14, A1, B2, C2); - and (int_fwire_15, A1, B2, C1); - and (int_fwire_16, A1, B1, C2); - and (int_fwire_17, A1, B1, C1); - or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA332x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - wire int_fwire_9, int_fwire_10, int_fwire_11; - wire int_fwire_12, int_fwire_13, int_fwire_14; - wire int_fwire_15, int_fwire_16, int_fwire_17; - - and (int_fwire_0, A3, B3, C2); - and (int_fwire_1, A3, B3, C1); - and (int_fwire_2, A3, B2, C2); - and (int_fwire_3, A3, B2, C1); - and (int_fwire_4, A3, B1, C2); - and (int_fwire_5, A3, B1, C1); - and (int_fwire_6, A2, B3, C2); - and (int_fwire_7, A2, B3, C1); - and (int_fwire_8, A2, B2, C2); - and (int_fwire_9, A2, B2, C1); - and (int_fwire_10, A2, B1, C2); - and (int_fwire_11, A2, B1, C1); - and (int_fwire_12, A1, B3, C2); - and (int_fwire_13, A1, B3, C1); - and (int_fwire_14, A1, B2, C2); - and (int_fwire_15, A1, B2, C1); - and (int_fwire_16, A1, B1, C2); - and (int_fwire_17, A1, B1, C1); - or (Y, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA333x1_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - wire int_fwire_9, int_fwire_10, int_fwire_11; - wire int_fwire_12, int_fwire_13, int_fwire_14; - wire int_fwire_15, int_fwire_16, int_fwire_17; - wire int_fwire_18, int_fwire_19, int_fwire_20; - wire int_fwire_21, int_fwire_22, int_fwire_23; - wire int_fwire_24, int_fwire_25, int_fwire_26; - - and (int_fwire_0, A3, B3, C3); - and (int_fwire_1, A3, B3, C2); - and (int_fwire_2, A3, B3, C1); - and (int_fwire_3, A3, B2, C3); - and (int_fwire_4, A3, B2, C2); - and (int_fwire_5, A3, B2, C1); - and (int_fwire_6, A3, B1, C3); - and (int_fwire_7, A3, B1, C2); - and (int_fwire_8, A3, B1, C1); - and (int_fwire_9, A2, B3, C3); - and (int_fwire_10, A2, B3, C2); - and (int_fwire_11, A2, B3, C1); - and (int_fwire_12, A2, B2, C3); - and (int_fwire_13, A2, B2, C2); - and (int_fwire_14, A2, B2, C1); - and (int_fwire_15, A2, B1, C3); - and (int_fwire_16, A2, B1, C2); - and (int_fwire_17, A2, B1, C1); - and (int_fwire_18, A1, B3, C3); - and (int_fwire_19, A1, B3, C2); - and (int_fwire_20, A1, B3, C1); - and (int_fwire_21, A1, B2, C3); - and (int_fwire_22, A1, B2, C2); - and (int_fwire_23, A1, B2, C1); - and (int_fwire_24, A1, B1, C3); - and (int_fwire_25, A1, B1, C2); - and (int_fwire_26, A1, B1, C1); - or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA333x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - wire int_fwire_9, int_fwire_10, int_fwire_11; - wire int_fwire_12, int_fwire_13, int_fwire_14; - wire int_fwire_15, int_fwire_16, int_fwire_17; - wire int_fwire_18, int_fwire_19, int_fwire_20; - wire int_fwire_21, int_fwire_22, int_fwire_23; - wire int_fwire_24, int_fwire_25, int_fwire_26; - - and (int_fwire_0, A3, B3, C3); - and (int_fwire_1, A3, B3, C2); - and (int_fwire_2, A3, B3, C1); - and (int_fwire_3, A3, B2, C3); - and (int_fwire_4, A3, B2, C2); - and (int_fwire_5, A3, B2, C1); - and (int_fwire_6, A3, B1, C3); - and (int_fwire_7, A3, B1, C2); - and (int_fwire_8, A3, B1, C1); - and (int_fwire_9, A2, B3, C3); - and (int_fwire_10, A2, B3, C2); - and (int_fwire_11, A2, B3, C1); - and (int_fwire_12, A2, B2, C3); - and (int_fwire_13, A2, B2, C2); - and (int_fwire_14, A2, B2, C1); - and (int_fwire_15, A2, B1, C3); - and (int_fwire_16, A2, B1, C2); - and (int_fwire_17, A2, B1, C1); - and (int_fwire_18, A1, B3, C3); - and (int_fwire_19, A1, B3, C2); - and (int_fwire_20, A1, B3, C1); - and (int_fwire_21, A1, B2, C3); - and (int_fwire_22, A1, B2, C2); - and (int_fwire_23, A1, B2, C1); - and (int_fwire_24, A1, B1, C3); - and (int_fwire_25, A1, B1, C2); - and (int_fwire_26, A1, B1, C1); - or (Y, int_fwire_26, int_fwire_25, int_fwire_24, int_fwire_23, int_fwire_22, int_fwire_21, int_fwire_20, int_fwire_19, int_fwire_18, int_fwire_17, int_fwire_16, int_fwire_15, int_fwire_14, int_fwire_13, int_fwire_12, int_fwire_11, int_fwire_10, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OA33x2_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3); - output Y; - input A1, A2, A3, B1, B2, B3; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6, int_fwire_7, int_fwire_8; - - and (int_fwire_0, A3, B3); - and (int_fwire_1, A3, B2); - and (int_fwire_2, A3, B1); - and (int_fwire_3, A2, B3); - and (int_fwire_4, A2, B2); - and (int_fwire_5, A2, B1); - and (int_fwire_6, A1, B3); - and (int_fwire_7, A1, B2); - and (int_fwire_8, A1, B1); - or (Y, int_fwire_8, int_fwire_7, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & B3) | (~A2 & ~A3 & ~B1 & B2 & B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & B3) | (~A1 & ~A3 & ~B1 & B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & B3) | (~A1 & ~A2 & ~B1 & B2 & B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI211xp5_ASAP7_75t_R (Y, A1, A2, B, C); - output Y; - input A1, A2, B, C; - - // Function - wire A1__bar, A2__bar, B__bar; - wire C__bar, int_fwire_0; - - not (C__bar, C); - not (B__bar, B); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar); - or (Y, int_fwire_0, B__bar, C__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2 & C)) - (B => Y) = 0; - if ((A1 & ~A2 & C)) - (B => Y) = 0; - if ((~A1 & A2 & C)) - (B => Y) = 0; - if ((A1 & A2 & B)) - (C => Y) = 0; - if ((A1 & ~A2 & B)) - (C => Y) = 0; - if ((~A1 & A2 & B)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI21x1_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0; - - not (B__bar, B); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar); - or (Y, int_fwire_0, B__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2)) - (B => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI21xp33_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0; - - not (B__bar, B); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar); - or (Y, int_fwire_0, B__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2)) - (B => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI21xp5_ASAP7_75t_R (Y, A1, A2, B); - output Y; - input A1, A2, B; - - // Function - wire A1__bar, A2__bar, B__bar; - wire int_fwire_0; - - not (B__bar, B); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar); - or (Y, int_fwire_0, B__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - if ((A1 & A2)) - (B => Y) = 0; - if ((A1 & ~A2)) - (B => Y) = 0; - if ((~A1 & A2)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI221xp5_ASAP7_75t_R (Y, A1, A2, B1, B2, C); - output Y; - input A1, A2, B1, B2, C; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, C__bar, int_fwire_0; - wire int_fwire_1; - - not (C__bar, C); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar); - or (Y, int_fwire_1, int_fwire_0, C__bar); - - // Timing - specify - if ((~A2 & B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & C)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2 & C)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & C)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & A2 & B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & A2 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~B1 & B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI222xp33_ASAP7_75t_R (Y, A1, A2, B1, B2, C1, C2); - output Y; - input A1, A2, B1, B2, C1, C2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, C1__bar, C2__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - - not (C2__bar, C2); - not (C1__bar, C1); - and (int_fwire_0, C1__bar, C2__bar); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_1, B1__bar, B2__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, A2__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & B2 & C1 & ~C2) | (~A2 & B1 & ~B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & B2 & C1 & ~C2) | (~A1 & B1 & ~B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI22x1_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI22xp33_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI22xp5_ASAP7_75t_R (Y, A1, A2, B1, B2); - output Y; - input A1, A2, B1, B2; - - // Function - wire A1__bar, A2__bar, B1__bar; - wire B2__bar, int_fwire_0, int_fwire_1; - - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & B1 & B2)) - (A1 => Y) = 0; - if ((~A2 & B1 & ~B2)) - (A1 => Y) = 0; - if ((~A2 & ~B1 & B2)) - (A1 => Y) = 0; - if ((~A1 & B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & B1 & ~B2)) - (A2 => Y) = 0; - if ((~A1 & ~B1 & B2)) - (A2 => Y) = 0; - if ((A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI311xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, C1); - output Y; - input A1, A2, A3, B1, C1; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, C1__bar, int_fwire_0; - - not (C1__bar, C1); - not (B1__bar, B1); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_0, B1__bar, C1__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & A3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & C1) | (A1 & ~A2 & A3 & C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & C1)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & B1)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1) | (A1 & ~A2 & A3 & B1)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1)) - (C1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI31xp33_ASAP7_75t_R (Y, A1, A2, A3, B); - output Y; - input A1, A2, A3, B; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B__bar, int_fwire_0; - - not (B__bar, B); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_0, B__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & A3)) - (B => Y) = 0; - if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) - (B => Y) = 0; - if ((A1 & ~A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & A2 & A3)) - (B => Y) = 0; - if ((~A1 & A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & ~A2 & A3)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI31xp67_ASAP7_75t_R (Y, A1, A2, A3, B); - output Y; - input A1, A2, A3, B; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B__bar, int_fwire_0; - - not (B__bar, B); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_0, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_0, B__bar); - - // Timing - specify - (A1 => Y) = 0; - (A2 => Y) = 0; - (A3 => Y) = 0; - if ((A1 & A2 & A3)) - (B => Y) = 0; - if ((A1 & A2 & ~A3) | (A1 & ~A2 & A3)) - (B => Y) = 0; - if ((A1 & ~A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & A2 & A3)) - (B => Y) = 0; - if ((~A1 & A2 & ~A3)) - (B => Y) = 0; - if ((~A1 & ~A2 & A3)) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI321xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, C); - output Y; - input A1, A2, A3, B1, B2, C; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, C__bar; - wire int_fwire_0, int_fwire_1; - - not (C__bar, C); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_1, int_fwire_0, C__bar); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & C)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & C)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & C)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & C)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & C)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & C)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & C)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & C)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & C) | (A1 & ~A2 & A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & C)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & C) | (A1 & ~A2 & A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & C)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2) | (A1 & ~A2 & A3 & B1 & B2)) - (C => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2) | (A1 & ~A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2) | (A1 & ~A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2)) - (C => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2)) - (C => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2)) - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI322xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, C1, C2); - output Y; - input A1, A2, A3, B1, B2, C1, C2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, C1__bar; - wire C2__bar, int_fwire_0, int_fwire_1; - wire int_fwire_2; - - not (C2__bar, C2); - not (C1__bar, C1); - and (int_fwire_0, C1__bar, C2__bar); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_1, B1__bar, B2__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI32xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2); - output Y; - input A1, A2, A3, B1, B2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, int_fwire_0; - wire int_fwire_1; - - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2) | (A1 & ~A2 & A3 & ~B2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1) | (A1 & ~A2 & A3 & ~B1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1)) - (B2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI331xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1); - output Y; - input A1, A2, A3, B1, B2, B3, C1; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, int_fwire_0, int_fwire_1; - - not (C1__bar, C1); - not (B3__bar, B3); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar, B3__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_1, int_fwire_0, C1__bar); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3) | (A1 & A2 & A3 & B1 & ~B2 & B3) | (A1 & A2 & ~A3 & B1 & B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3) | (~A1 & A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3)) - (C1 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI332xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, C2__bar, int_fwire_0; - wire int_fwire_1, int_fwire_2; - - not (C2__bar, C2); - not (C1__bar, C1); - and (int_fwire_0, C1__bar, C2__bar); - not (B3__bar, B3); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_1, B1__bar, B2__bar, B3__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1) | (A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1) | (~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1)) - (C2 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI333xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3, C1, C2, C3); - output Y; - input A1, A2, A3, B1, B2, B3, C1, C2, C3; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire C1__bar, C2__bar, C3__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - - not (C3__bar, C3); - not (C2__bar, C2); - not (C1__bar, C1); - and (int_fwire_0, C1__bar, C2__bar, C3__bar); - not (B3__bar, B3); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_1, B1__bar, B2__bar, B3__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_2, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3 & ~C1 & ~C2 & C3) | (~A1 & ~A2 & B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & C1 & ~C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & C1 & ~C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & C2 & ~C3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3 & ~C1 & ~C2 & C3)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & C1 & ~C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & C2 & ~C3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3 & ~C1 & ~C2 & C3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & C1 & ~C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & C2 & ~C3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3 & ~C1 & ~C2 & C3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & C2 & ~C3) | (~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & C1 & ~C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & C2 & ~C3)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & ~C1 & ~C2 & C3)) - (B3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C2 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C2 & ~C3)) - (C1 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C3) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C3)) - (C2 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2) | (A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (A1 & ~A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & A2 & ~A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & B2 & ~B3 & ~C1 & ~C2) | (~A1 & ~A2 & A3 & B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & B1 & ~B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & B2 & ~B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2 & B3 & ~C1 & ~C2)) - (C3 => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OAI33xp33_ASAP7_75t_R (Y, A1, A2, A3, B1, B2, B3); - output Y; - input A1, A2, A3, B1, B2, B3; - - // Function - wire A1__bar, A2__bar, A3__bar; - wire B1__bar, B2__bar, B3__bar; - wire int_fwire_0, int_fwire_1; - - not (B3__bar, B3); - not (B2__bar, B2); - not (B1__bar, B1); - and (int_fwire_0, B1__bar, B2__bar, B3__bar); - not (A3__bar, A3); - not (A2__bar, A2); - not (A1__bar, A1); - and (int_fwire_1, A1__bar, A2__bar, A3__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if ((~A2 & ~A3 & B1 & B2 & B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & B2 & ~B3) | (~A2 & ~A3 & B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & B1 & ~B2 & ~B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & B2 & ~B3)) - (A1 => Y) = 0; - if ((~A2 & ~A3 & ~B1 & ~B2 & B3)) - (A1 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & B2 & ~B3) | (~A1 & ~A3 & B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & B1 & ~B2 & ~B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & B2 & ~B3)) - (A2 => Y) = 0; - if ((~A1 & ~A3 & ~B1 & ~B2 & B3)) - (A2 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & B2 & ~B3) | (~A1 & ~A2 & B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & B1 & ~B2 & ~B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & B2 & ~B3)) - (A3 => Y) = 0; - if ((~A1 & ~A2 & ~B1 & ~B2 & B3)) - (A3 => Y) = 0; - if ((A1 & A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B2 & ~B3) | (~A1 & A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B2 & ~B3)) - (B1 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B3) | (~A1 & A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B3)) - (B2 => Y) = 0; - if ((A1 & A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & A3 & ~B1 & ~B2) | (~A1 & A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((A1 & ~A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((~A1 & A2 & ~A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - if ((~A1 & ~A2 & A3 & ~B1 & ~B2)) - (B3 => Y) = 0; - endspecify -endmodule -`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_RVT_TT_220101.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_RVT_TT_220101.v deleted file mode 100644 index 30ece337bd..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_RVT_TT_220101.v +++ /dev/null @@ -1,1173 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2022 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/anolas19/Liberate/Verilog/asap7sc7p5t_SEQ_RVT_TT_211229_pex created by Liberate 18.1.0.293 on Fri Dec 31 22:59:44 MST 2021 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module DFFASRHQNx1_ASAP7_75t_R (QN, D, RESETN, SETN, CLK); - output QN; - input D, RESETN, SETN, CLK; - reg notifier; - wire delayed_D, delayed_RESETN, delayed_SETN, delayed_CLK; - - // Function - wire int_fwire_d, int_fwire_IQN, int_fwire_r; - wire int_fwire_s, xcr_0; - - not (int_fwire_d, delayed_D); - not (int_fwire_s, delayed_RESETN); - not (int_fwire_r, delayed_SETN); - //altos_dff_sr_err (xcr_0, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r); - // altos_dff_sr_0 (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, int_fwire_s, int_fwire_r, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, adacond8; - wire CLK__bar, D__bar; - - - // Additional timing gates - and (adacond0, RESETN, SETN); - and (adacond1, D, SETN); - and (adacond2, CLK, SETN); - not (CLK__bar, CLK); - and (adacond3, CLK__bar, SETN); - not (D__bar, D); - and (adacond4, D__bar, RESETN); - and (adacond5, CLK, RESETN); - and (adacond6, CLK__bar, RESETN); - and (adacond7, D, RESETN, SETN); - and (adacond8, D__bar, RESETN, SETN); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFHQNx1_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (int_fwire_d, delayed_D); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFHQNx2_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (int_fwire_d, delayed_D); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFHQNx3_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (int_fwire_d, delayed_D); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFHQx4_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_IQ, xcr_0; - - //altos_dff_err (xcr_0, delayed_CLK, delayed_D); - //altos_dff (int_fwire_IQ, notifier, delayed_CLK, delayed_D, xcr_0); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFLQNx1_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (int_fwire_d, delayed_D); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFLQNx2_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (int_fwire_d, delayed_D); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFLQNx3_ASAP7_75t_R (QN, D, CLK); - output QN; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (int_fwire_d, delayed_D); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DFFLQx4_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, xcr_0; - - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, delayed_D); - //altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DHLx1_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_IQ; - - //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DHLx2_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_IQ; - - //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DHLx3_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_IQ; - - //altos_latch (int_fwire_IQ, notifier, delayed_CLK, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DLLx1_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ; - - not (int_fwire_clk, delayed_CLK); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DLLx2_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ; - - not (int_fwire_clk, delayed_CLK); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module DLLx3_ASAP7_75t_R (Q, D, CLK); - output Q; - input D, CLK; - reg notifier; - wire delayed_D, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ; - - not (int_fwire_clk, delayed_CLK); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, delayed_D); - buf (Q, int_fwire_IQ); - - // Timing -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx1_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx2_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx2p67DC_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx3_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx4DC_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx4_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx5_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx5p33DC_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx6p67DC_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module ICGx8DC_ASAP7_75t_R (GCLK, ENA, SE, CLK); - output GCLK; - input ENA, SE, CLK; - reg notifier; - wire delayed_ENA, delayed_SE, delayed_CLK; - - // Function - wire int_fwire_clk, int_fwire_IQ, int_fwire_test; - - not (int_fwire_clk, delayed_CLK); - or (int_fwire_test, delayed_ENA, delayed_SE); - //altos_latch (int_fwire_IQ, notifier, int_fwire_clk, int_fwire_test); - and (GCLK, delayed_CLK, int_fwire_IQ); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, ENA__bar; - wire int_twire_0, SE__bar; - - - // Additional timing gates - not (ENA__bar, ENA); - and (int_twire_0, ENA__bar, SE); - or (adacond0, ENA, int_twire_0); - not (SE__bar, SE); - and (adacond1, ENA__bar, SE__bar); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFHx1_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFHx2_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFHx3_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFHx4_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_d, int_fwire_IQN, xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - //altos_dff_err (xcr_0, delayed_CLK, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, delayed_CLK, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFLx1_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFLx2_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFLx3_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module SDFLx4_ASAP7_75t_R (QN, D, SE, SI, CLK); - output QN; - input D, SE, SI, CLK; - reg notifier; - wire delayed_D, delayed_SE, delayed_SI, delayed_CLK; - - // Function - wire delayed_D__bar, delayed_SE__bar, delayed_SI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_clk, int_fwire_d, int_fwire_IQN; - wire xcr_0; - - not (delayed_SI__bar, delayed_SI); - and (int_fwire_0, delayed_SE, delayed_SI__bar); - not (delayed_D__bar, delayed_D); - and (int_fwire_1, delayed_D__bar, delayed_SI__bar); - not (delayed_SE__bar, delayed_SE); - and (int_fwire_2, delayed_D__bar, delayed_SE__bar); - or (int_fwire_d, int_fwire_2, int_fwire_1, int_fwire_0); - not (int_fwire_clk, delayed_CLK); - //altos_dff_err (xcr_0, int_fwire_clk, int_fwire_d); - //altos_dff (int_fwire_IQN, notifier, int_fwire_clk, int_fwire_d, xcr_0); - buf (QN, int_fwire_IQN); - - // Timing - - // Additional timing wires - wire adacond0, adacond1, adacond2; - wire adacond3, adacond4, adacond5; - wire adacond6, adacond7, D__bar; - wire int_twire_0, int_twire_1, int_twire_2; - wire int_twire_3, int_twire_4, int_twire_5; - wire SE__bar, SI__bar; - - - // Additional timing gates - not (SE__bar, SE); - and (adacond0, SE__bar, SI); - not (SI__bar, SI); - and (adacond1, SE__bar, SI__bar); - and (adacond2, D, SI__bar); - not (D__bar, D); - and (adacond3, D__bar, SI); - and (adacond4, D, SE); - and (adacond5, D__bar, SE); - and (int_twire_0, D__bar, SE, SI); - and (int_twire_1, D, SE__bar); - and (int_twire_2, D, SE, SI); - or (adacond6, int_twire_2, int_twire_1, int_twire_0); - and (int_twire_3, D__bar, SE__bar); - and (int_twire_4, D__bar, SE, SI__bar); - and (int_twire_5, D, SE, SI__bar); - or (adacond7, int_twire_5, int_twire_4, int_twire_3); - -endmodule -`endcelldefine diff --git a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_RVT_TT_201020.v b/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_RVT_TT_201020.v deleted file mode 100644 index 76fbc6b1fd..0000000000 --- a/flow/platforms/asap7/work_around_yosys/asap7sc7p5t_SIMPLE_RVT_TT_201020.v +++ /dev/null @@ -1,1303 +0,0 @@ -// BSD 3-Clause License -// -// Copyright 2020 Lawrence T. Clark, Vinay Vashishtha, or Arizona State -// University -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Verilog for library /home/ltclark/ASAP7/LIB2/Liberate_2/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_201020 created by Liberate 18.1.0.293 on Fri Nov 27 12:35:46 MST 2020 for SDF version 2.1 - -// type: -`timescale 1ns/10ps -`celldefine -module AND2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - and (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND2x4_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - and (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND2x6_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - and (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND3x1_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - and (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND3x2_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - and (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND3x4_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - and (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND4x1_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - and (Y, A, B, C, D); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND4x2_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - and (Y, A, B, C, D); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND5x1_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - and (Y, A, B, C, D, E); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module AND5x2_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - and (Y, A, B, C, D, E); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module FAx1_ASAP7_75t_R (CON, SN, A, B, CI); - output CON, SN; - input A, B, CI; - - // Function - wire A__bar, B__bar, CI__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - wire int_fwire_3, int_fwire_4, int_fwire_5; - wire int_fwire_6; - - not (CI__bar, CI); - not (B__bar, B); - and (int_fwire_0, B__bar, CI__bar); - not (A__bar, A); - and (int_fwire_1, A__bar, CI__bar); - and (int_fwire_2, A__bar, B__bar); - or (CON, int_fwire_2, int_fwire_1, int_fwire_0); - and (int_fwire_3, A__bar, B__bar, CI__bar); - and (int_fwire_4, A__bar, B, CI); - and (int_fwire_5, A, B__bar, CI); - and (int_fwire_6, A, B, CI__bar); - or (SN, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module HAxp5_ASAP7_75t_R (CON, SN, A, B); - output CON, SN; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (B__bar, B); - not (A__bar, A); - or (CON, A__bar, B__bar); - and (int_fwire_0, A__bar, B__bar); - and (int_fwire_1, A, B); - or (SN, int_fwire_1, int_fwire_0); - - // Timing - specify - (A => CON) = 0; - (B => CON) = 0; - if (B) - (A => SN) = 0; - if (~B) - (A => SN) = 0; - if (A) - (B => SN) = 0; - if (~A) - (B => SN) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module MAJIxp5_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - wire int_fwire_0, int_fwire_1, int_fwire_2; - - not (C__bar, C); - not (B__bar, B); - and (int_fwire_0, B__bar, C__bar); - not (A__bar, A); - and (int_fwire_1, A__bar, C__bar); - and (int_fwire_2, A__bar, B__bar); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module MAJx2_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, B, C); - and (int_fwire_1, A, C); - and (int_fwire_2, A, B); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module MAJx3_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire int_fwire_0, int_fwire_1, int_fwire_2; - - and (int_fwire_0, B, C); - and (int_fwire_1, A, C); - and (int_fwire_2, A, B); - or (Y, int_fwire_2, int_fwire_1, int_fwire_0); -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2x1_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2x1p5_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2xp33_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2xp5_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND2xp67_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND3x1_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND3x2_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND3xp33_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND4xp25_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar; - - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar, D__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND4xp75_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar; - - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar, D__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NAND5xp2_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar, E__bar; - - not (E__bar, E); - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - or (Y, A__bar, B__bar, C__bar, D__bar, E__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR2x1_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR2x1p5_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR2xp33_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR2xp67_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar; - - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR3x1_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR3x2_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR3xp33_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - wire A__bar, B__bar, C__bar; - - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR4xp25_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar; - - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar, D__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR4xp75_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar; - - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar, D__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module NOR5xp2_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - wire A__bar, B__bar, C__bar; - wire D__bar, E__bar; - - not (E__bar, E); - not (D__bar, D); - not (C__bar, C); - not (B__bar, B); - not (A__bar, A); - and (Y, A__bar, B__bar, C__bar, D__bar, E__bar); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - or (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR2x4_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - or (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR2x6_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - or (Y, A, B); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR3x1_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - or (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR3x2_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - or (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR3x4_ASAP7_75t_R (Y, A, B, C); - output Y; - input A, B, C; - - // Function - or (Y, A, B, C); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR4x1_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - or (Y, A, B, C, D); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR4x2_ASAP7_75t_R (Y, A, B, C, D); - output Y; - input A, B, C, D; - - // Function - or (Y, A, B, C, D); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR5x1_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - or (Y, A, B, C, D, E); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module OR5x2_ASAP7_75t_R (Y, A, B, C, D, E); - output Y; - input A, B, C, D, E; - - // Function - or (Y, A, B, C, D, E); - - // Timing - specify - (A => Y) = 0; - (B => Y) = 0; - (C => Y) = 0; - (D => Y) = 0; - (E => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module TIEHIx1_ASAP7_75t_R (H); - output H; - - // Function - buf (H, 1'b1); - - // Timing - specify - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module TIELOx1_ASAP7_75t_R (L); - output L; - - // Function - buf (L, 1'b0); - - // Timing - specify - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XNOR2x1_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (B__bar, B); - not (A__bar, A); - and (int_fwire_0, A__bar, B__bar); - and (int_fwire_1, A, B); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (B) - (A => Y) = 0; - if (~B) - (A => Y) = 0; - if (A) - (B => Y) = 0; - if (~A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XNOR2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (B__bar, B); - not (A__bar, A); - and (int_fwire_0, A__bar, B__bar); - and (int_fwire_1, A, B); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (B) - (A => Y) = 0; - if (~B) - (A => Y) = 0; - if (A) - (B => Y) = 0; - if (~A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XNOR2xp5_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (B__bar, B); - not (A__bar, A); - and (int_fwire_0, A__bar, B__bar); - and (int_fwire_1, A, B); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (B) - (A => Y) = 0; - if (~B) - (A => Y) = 0; - if (A) - (B => Y) = 0; - if (~A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XOR2x1_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (A__bar, A); - and (int_fwire_0, A__bar, B); - not (B__bar, B); - and (int_fwire_1, A, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (~B) - (A => Y) = 0; - if (B) - (A => Y) = 0; - if (~A) - (B => Y) = 0; - if (A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XOR2x2_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (A__bar, A); - and (int_fwire_0, A__bar, B); - not (B__bar, B); - and (int_fwire_1, A, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (~B) - (A => Y) = 0; - if (B) - (A => Y) = 0; - if (~A) - (B => Y) = 0; - if (A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine - -// type: -`timescale 1ns/10ps -`celldefine -module XOR2xp5_ASAP7_75t_R (Y, A, B); - output Y; - input A, B; - - // Function - wire A__bar, B__bar, int_fwire_0; - wire int_fwire_1; - - not (A__bar, A); - and (int_fwire_0, A__bar, B); - not (B__bar, B); - and (int_fwire_1, A, B__bar); - or (Y, int_fwire_1, int_fwire_0); - - // Timing - specify - if (~B) - (A => Y) = 0; - if (B) - (A => Y) = 0; - if (~A) - (B => Y) = 0; - if (A) - (B => Y) = 0; - endspecify -endmodule -`endcelldefine diff --git a/flow/platforms/gf180/config.mk b/flow/platforms/gf180/config.mk index 1d2769dba7..a4c9c9beda 100644 --- a/flow/platforms/gf180/config.mk +++ b/flow/platforms/gf180/config.mk @@ -79,7 +79,6 @@ export TAPCELL_TCL ?= $(PLATFORM_DIR)/openROAD/tapcell # macro planning export MACRO_PLACE_HALO ?= 10 10 -export MACRO_PLACE_CHANNEL ?= 20.16 20.16 #--------------------------------------------------------- # Place @@ -94,6 +93,10 @@ export MIN_ROUTING_LAYER ?= Metal2 export MAX_ROUTING_LAYER ?= Metal5 export DISABLE_VIA_GEN ?= 1 +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 + # Define fastRoute tcl export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl @@ -121,20 +124,29 @@ export RCX_RC_CORNER = $($(CORNER)_RCX_RC_CORNER) #---------------------------------------------------------------------------------------------------- export BC_LIB_FILES = $(abspath $(PLATFORM_DIR)/lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION)$(POWER_OPTION)__ff_n40C_5v50.lib.gz) export BC_TEMPERATURE = -40c +export BC_VOLTAGE = 5.5 export WC_LIB_FILES = $(abspath $(PLATFORM_DIR)/lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION)$(POWER_OPTION)__ss_125C_4v50.lib.gz) export WC_TEMPERATURE = 125c +export WC_VOLTAGE = 4.5 export TC_LIB_FILES = $(abspath $(PLATFORM_DIR)/lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION)$(POWER_OPTION)__tt_025C_5v00.lib.gz) export TC_TEMPERATURE = 25c +export TC_VOLTAGE = 5.0 # ---------------------------------------------------------------------------------------------------- # now, set files from user setting CORNER # ---------------------------------------------------------------------------------------------------- export TEMPERATURE = $($(CORNER)_TEMPERATURE) +export VOLTAGE = $($(CORNER)_VOLTAGE) export LIB_FILES = $($(CORNER)_LIB_FILES) \ $(ADDITIONAL_LIBS) +# IR drop estimation supply net name to be analyzed and supply voltage variable +export PWR_NETS_VOLTAGES ?= VDD $(VOLTAGE) +export GND_NETS_VOLTAGES ?= VSS 0.0 +export IR_DROP_LAYER ?= Metal1 + # For proprietary tool enablements that are not public export GF180_PRIVATE_DIR ?= ../../gf180-private -include $(GF180_PRIVATE_DIR)/private.mk diff --git a/flow/platforms/gf180/fastroute.tcl b/flow/platforms/gf180/fastroute.tcl index d91e3b4dcc..42e6b5996b 100644 --- a/flow/platforms/gf180/fastroute.tcl +++ b/flow/platforms/gf180/fastroute.tcl @@ -1,3 +1,2 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.25 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/gf180/openROAD/tapcell.tcl b/flow/platforms/gf180/openROAD/tapcell.tcl index fecbde985a..24ebce5587 100644 --- a/flow/platforms/gf180/openROAD/tapcell.tcl +++ b/flow/platforms/gf180/openROAD/tapcell.tcl @@ -1,5 +1,5 @@ - tapcell \ - -endcap_cpp "12" \ - -distance 100 \ - -tapcell_master $::env(TIE_CELL) \ - -endcap_master $::env(ENDCAP_CELL) +tapcell \ + -endcap_cpp "12" \ + -distance 100 \ + -tapcell_master $::env(TIE_CELL) \ + -endcap_master $::env(ENDCAP_CELL) diff --git a/flow/platforms/gf180/setRC.tcl b/flow/platforms/gf180/setRC.tcl index 7c6828b1de..33ae86856a 100644 --- a/flow/platforms/gf180/setRC.tcl +++ b/flow/platforms/gf180/setRC.tcl @@ -17,14 +17,12 @@ set_layer_rc -layer Metal5 -resistance 7.92778E-05 -capacitance 1.55595E-04 regexp {(\d+)} $::env(METAL_OPTION) metal if { $metal == "6" } { - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal5 - -} elseif { $metal == "5" } { + set_wire_rc -clock -layer Metal5 +} elseif { $metal == "5" } { # TC matches LEF. These are the temperature adjusted values. # The other stacks are likely similar but I haven't checked yet. - if {$::env(CORNER) == "WC"} { + if { $::env(CORNER) == "WC" } { set_layer_rc -via Via1 -resistance 16.845 set_layer_rc -via Via2 -resistance 16.845 set_layer_rc -via Via3 -resistance 16.845 @@ -32,11 +30,11 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 16.845 } } - } elseif {$::env(CORNER) == "BC"} { + } elseif { $::env(CORNER) == "BC" } { set_layer_rc -via Via1 -resistance 4.23 set_layer_rc -via Via2 -resistance 4.23 set_layer_rc -via Via3 -resistance 4.23 @@ -44,27 +42,21 @@ if { $metal == "6" } { set tech [ord::get_db_tech] foreach via [$tech getVias] { - if {[$via getResistance] == 4.5} { + if { [$via getResistance] == 4.5 } { $via setResistance 4.23 } } } - - set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal4 - -} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal3 - -} elseif { $metal == "3" } { - + set_wire_rc -clock -layer Metal4 +} elseif { $metal == "4" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 - -} elseif { $metal == "2" } { - + set_wire_rc -clock -layer Metal3 +} elseif { $metal == "3" } { + set_wire_rc -signal -layer Metal2 + set_wire_rc -clock -layer Metal2 +} elseif { $metal == "2" } { set_wire_rc -signal -layer Metal2 - set_wire_rc -clock -layer Metal2 + set_wire_rc -clock -layer Metal2 } diff --git a/flow/platforms/ihp-sg13g2/cells_latch.v b/flow/platforms/ihp-sg13g2/cells_latch.v index 7b216e5e03..46537fbde8 100644 --- a/flow/platforms/ihp-sg13g2/cells_latch.v +++ b/flow/platforms/ihp-sg13g2/cells_latch.v @@ -6,3 +6,11 @@ module $_DLATCH_P_(input E, input D, output Q); ); endmodule +module $_DLATCH_N_(input E, input D, output Q); + sg13g2_dllrq_1 _TECHMAP_REPLACE_ ( + .D(D), + .GATE_N(E), + .RESET_B(1'b1), + .Q(Q) + ); +endmodule diff --git a/flow/platforms/ihp-sg13g2/config.mk b/flow/platforms/ihp-sg13g2/config.mk index 90be2e80e3..01fa6e88e3 100644 --- a/flow/platforms/ihp-sg13g2/config.mk +++ b/flow/platforms/ihp-sg13g2/config.mk @@ -6,20 +6,30 @@ export PROCESS = ihp-sg13g2 # ---------------------------------------------------- # Add IO related files when a TCL script is assigned to 'FOOTPRINT_TCL'. # This variable is used to pass IO information. -ifdef FOOTPRINT_TCL - export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ - $(PLATFORM_DIR)/lef/bondpad_70x70.lef - export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib - export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ - $(PLATFORM_DIR)/gds/bondpad_70x70.gds +export LOAD_ADDITIONAL_FILES ?= 1 +ifneq ($(FOOTPRINT_TCL),) + ifeq ($(LOAD_ADDITIONAL_FILES),1) + export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \ + $(PLATFORM_DIR)/lef/bondpad_70x70.lef + export ADDITIONAL_SLOW_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib + export ADDITIONAL_FAST_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib + export ADDITIONAL_TYP_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib + export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds \ + $(PLATFORM_DIR)/gds/bondpad_70x70.gds + endif endif -export TECH_LEF = $(PLATFORM_DIR)/lef/sg13g2_tech.lef -export SC_LEF = $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef - -export LIB_FILES = $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ - $(ADDITIONAL_LIBS) -export GDS_FILES = $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \ - $(ADDITIONAL_GDS) +export TECH_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_tech.lef +export SC_LEF ?= $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef + +export SLOW_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_slow_1p08V_125C.lib \ + $(ADDITIONAL_SLOW_LIBS) +export FAST_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_fast_1p32V_m40C.lib \ + $(ADDITIONAL_FAST_LIBS) +export TYP_LIB_FILES ?= $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \ + $(ADDITIONAL_TYP_LIBS) +export LIB_FILES ?= $(TYP_LIB_FILES) +export GDS_FILES ?= $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \ + $(ADDITIONAL_GDS) # Dont use cells to ease congestion # Specify at least one filler cell if none @@ -54,8 +64,19 @@ export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v # Define ABC driver and load export ABC_DRIVER_CELL = sg13g2_buf_4 export ABC_LOAD_IN_FF = 6.0 -# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file -export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') +ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) + ifneq ($(wildcard $(SDC_FILE)),) + # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file + export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}') + endif +endif + +# ----------------------------------------------------- +# Sizing +# ----------------------------------------------------- + +export MATCH_CELL_FOOTPRINT = 1 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- @@ -65,8 +86,8 @@ export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -per export PLACE_SITE = CoreSite # IO Placer pin layers -export IO_PLACER_H = Metal2 -export IO_PLACER_V = Metal3 +export IO_PLACER_H ?= Metal2 +export IO_PLACER_V ?= Metal3 # Define default PDN config export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl @@ -79,7 +100,6 @@ export CORE_MARGIN ?= 16.5 export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl export MACRO_PLACE_HALO ?= 40 40 -export MACRO_PLACE_CHANNEL ?= 80 80 #--------------------------------------------------------- # Place @@ -95,7 +115,11 @@ export MAX_ROUTING_LAYER ?= Metal5 #export VIA_IN_PIN_MIN_LAYER ?= Metal1 #export VIA_IN_PIN_MAX_LAYER ?= Metal1 #export DISABLE_VIA_GEN ?= 1 -# + +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 + # Define fastRoute tcl export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl @@ -117,8 +141,8 @@ export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules # IR drop estimation supply net name to be analyzed and supply voltage variable # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD 1.2" -export GND_NETS_VOLTAGES ?= "VSS 0.0" +export PWR_NETS_VOLTAGES ?= VDD 1.2 +export GND_NETS_VOLTAGES ?= VSS 0.0 export IR_DROP_LAYER ?= Metal1 # DRC Check @@ -128,5 +152,10 @@ export KLAYOUT_DRC_FILE ?= $(PLATFORM_DIR)/drc/sg13g2_minimal.lydrc export CDL_FILE ?= $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl #export KLAYOUT_LVS_FILE = $(PLATFORM_DIR)/lvs/$(PLATFORM).lylvs -#Temporary: skip post-DRT repair antennas -export SKIP_ANTENNA_REPAIR_POST_DRT = 1 +# --------------------------------------------------------- +# Final +# --------------------------------------------------------- + +# SRAM macros have empty placeholder cells included. Just ignore them to not +# thrown an error. +export GDS_ALLOW_EMPTY = RM_IHPSG13_1P_BITKIT_16x2_(CORNER|EDGE_TB|LE_con_corner|LE_con_edge_lr|LE_con_tap_lr|POWER_ramtap|TAP|TAP_LR) diff --git a/flow/platforms/ihp-sg13g2/fastroute.tcl b/flow/platforms/ihp-sg13g2/fastroute.tcl index 079fa662e8..e386fefda4 100644 --- a/flow/platforms/ihp-sg13g2/fastroute.tcl +++ b/flow/platforms/ihp-sg13g2/fastroute.tcl @@ -1,4 +1,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.05 set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/ihp-sg13g2/make_tracks.tcl b/flow/platforms/ihp-sg13g2/make_tracks.tcl index 4b6c63fd52..b3380eb7ef 100644 --- a/flow/platforms/ihp-sg13g2/make_tracks.tcl +++ b/flow/platforms/ihp-sg13g2/make_tracks.tcl @@ -1,7 +1,7 @@ -make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 -make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 -make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal1 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal2 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal3 -x_offset 0.0 -x_pitch 0.48 -y_offset 0.0 -y_pitch 0.48 +make_tracks Metal4 -x_offset 0.0 -x_pitch 0.42 -y_offset 0.0 -y_pitch 0.42 +make_tracks Metal5 -x_offset 0.0 -x_pitch 3.48 -y_offset 0.0 -y_pitch 0.48 make_tracks TopMetal1 -x_offset 1.46 -x_pitch 2.28 -y_offset 1.46 -y_pitch 2.28 -make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 +make_tracks TopMetal2 -x_offset 2.0 -x_pitch 4.0 -y_offset 2.0 -y_pitch 4.0 diff --git a/flow/platforms/ihp-sg13g2/pdn.tcl b/flow/platforms/ihp-sg13g2/pdn.tcl index 99d911feae..dcff94630e 100644 --- a/flow/platforms/ihp-sg13g2/pdn.tcl +++ b/flow/platforms/ihp-sg13g2/pdn.tcl @@ -19,13 +19,14 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} # standard cell grid #################################### define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads -add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring -add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_core_ring +add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} \ + -core_offsets {4.5} -connect_to_pads +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} \ + -extend_to_core_ring +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} \ + -extend_to_core_ring add_pdn_connect -grid {grid} -layers {Metal1 Metal5} add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} -# I/O pads -add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2} -add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2} #################################### diff --git a/flow/platforms/ihp-sg13g2/setRC.tcl b/flow/platforms/ihp-sg13g2/setRC.tcl index ee17153aee..35bfff7693 100644 --- a/flow/platforms/ihp-sg13g2/setRC.tcl +++ b/flow/platforms/ihp-sg13g2/setRC.tcl @@ -1,20 +1,16 @@ -# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier -# cap units pf/um -set_layer_rc -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03 -set_layer_rc -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03 -set_layer_rc -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03 -set_layer_rc -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03 -set_layer_rc -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03 -set_layer_rc -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03 -# end correlate +# correlation result (aes, gcd, ibex, riscv32i, spi) +# Metal1 capacitance fixed up from -1.1e-05 to 1e-10 as a minuscule positive value +set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance 1e-10 +set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04 +set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04 +set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04 +set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 +set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 +set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 -set_layer_rc -via Via1 -resistance 2.0E-3 -set_layer_rc -via Via2 -resistance 2.0E-3 -set_layer_rc -via Via3 -resistance 2.0E-3 -set_layer_rc -via Via4 -resistance 2.0E-3 +set_layer_rc -via Via1 -resistance 2.0E-3 +set_layer_rc -via Via2 -resistance 2.0E-3 +set_layer_rc -via Via3 -resistance 2.0E-3 +set_layer_rc -via Via4 -resistance 2.0E-3 set_layer_rc -via TopVia1 -resistance 0.4E-3 set_layer_rc -via TopVia2 -resistance 0.22E-3 - -set_wire_rc -signal -layer Metal2 -set_wire_rc -clock -layer Metal5 diff --git a/flow/platforms/ihp-sg13g2/sg13g2.map b/flow/platforms/ihp-sg13g2/sg13g2.map index 2614374122..fbb201c83d 100644 --- a/flow/platforms/ihp-sg13g2/sg13g2.map +++ b/flow/platforms/ihp-sg13g2/sg13g2.map @@ -29,13 +29,10 @@ #EDI Layer Name EDI Layer Type GDS Layer Number GDS Layer Type #============== ============== ================ ============== -Metal1 NET 8 0 -Metal1 SPNET 8 0 -Metal1 PIN 8 2 -Metal1 LEFPIN 8 2 -Metal1 FILL 8 22 -Metal1 LEFOBS 8 4 -Metal1 VIA 8 0 +Metal1 NET,SPNET,PIN,LEFPIN,VIA 8 0 +Metal1 PIN,LEFPIN 8 2 +Metal1 FILL 8 22 +Metal1 LEFOBS 8 4 #NAME Metal1/NET 20 0 #NAME Metal1/SPNET 20 0 @@ -46,13 +43,10 @@ Via1 PIN 19 0 Via1 LEFPIN 19 0 Via1 VIA 19 0 -Metal2 NET 10 0 -Metal2 SPNET 10 0 -Metal2 PIN 10 2 -Metal2 LEFPIN 10 2 -Metal2 FILL 10 22 -Metal2 VIA 10 0 -Metal2 LEFOBS 10 4 +Metal2 NET,SPNET,PIN,LEFPIN,VIA 10 0 +Metal2 PIN,LEFPIN 10 2 +Metal2 FILL 10 22 +Metal2 LEFOBS 10 4 #NAME Metal2/NET 21 0 #NAME Metal2/SPNET 21 0 @@ -64,13 +58,10 @@ Via2 LEFPIN 29 0 Via2 VIA 29 0 -Metal3 NET 30 0 -Metal3 SPNET 30 0 -Metal3 PIN 30 2 -Metal3 LEFPIN 30 2 -Metal3 FILL 30 22 -Metal3 VIA 30 0 -Metal3 LEFOBS 30 4 +Metal3 NET,SPNET,PIN,LEFPIN,VIA 30 0 +Metal3 PIN,LEFPIN 30 2 +Metal3 FILL 30 22 +Metal3 LEFOBS 30 4 #NAME Metal3/NET 22 0 #NAME Metal3/SPNET 22 0 @@ -82,13 +73,10 @@ Via3 LEFPIN 49 0 Via3 VIA 49 0 -Metal4 NET 50 0 -Metal4 SPNET 50 0 -Metal4 PIN 50 2 -Metal4 LEFPIN 50 2 -Metal4 FILL 50 22 -Metal4 VIA 50 0 -Metal4 LEFOBS 50 4 +Metal4 NET,SPNET,PIN,LEFPIN,VIA 50 0 +Metal4 PIN,LEFPIN 50 2 +Metal4 FILL 50 22 +Metal4 LEFOBS 50 4 #NAME Metal4/NET 23 0 #NAME Metal4/SPNET 23 0 @@ -100,13 +88,10 @@ Via4 LEFPIN 66 0 Via4 VIA 66 0 -Metal5 NET 67 0 -Metal5 SPNET 67 0 -Metal5 PIN 67 2 -Metal5 LEFPIN 67 2 -Metal5 FILL 67 22 -Metal5 VIA 67 0 -Metal5 LEFOBS 67 4 +Metal5 NET,SPNET,PIN,LEFPIN,VIA 67 0 +Metal5 PIN,LEFPIN 67 2 +Metal5 FILL 67 22 +Metal5 LEFOBS 67 4 #NAME Metal5/NET 70 0 #NAME Metal5/SPNET 70 0 @@ -117,13 +102,10 @@ TopVia1 PIN 125 0 TopVia1 LEFPIN 125 0 TopVia1 VIA 125 0 -TopMetal1 NET 126 0 -TopMetal1 SPNET 126 0 -TopMetal1 PIN 126 2 -TopMetal1 LEFPIN 126 2 -TopMetal1 FILL 126 22 -TopMetal1 VIA 126 0 -TopMetal1 LEFOBS 126 4 +TopMetal1 NET,SPNET,PIN,LEFPIN,VIA 126 0 +TopMetal1 PIN,LEFPIN 126 2 +TopMetal1 FILL 126 22 +TopMetal1 LEFOBS 126 4 #NAME TopMetal1/NET 130 0 #NAME TopMetal1/SPNET 130 0 @@ -134,13 +116,10 @@ TopVia2 PIN 133 0 TopVia2 LEFPIN 133 0 TopVia2 VIA 133 0 -TopMetal2 NET 134 0 -TopMetal2 SPNET 134 0 -TopMetal2 PIN 134 2 -TopMetal2 LEFPIN 134 2 -TopMetal2 FILL 134 22 -TopMetal2 VIA 134 0 -TopMetal2 LEFOBS 135 4 +TopMetal2 NET,SPNET,PIN,LEFPIN,VIA 134 0 +TopMetal2 PIN,LEFPIN 134 2 +TopMetal2 FILL 134 22 +TopMetal2 LEFOBS 134 4 #NAME TopMetal2/NET 137 0 #NAME TopMetal2/SPNET 137 0 @@ -149,6 +128,6 @@ NAME TopMetal2/PIN 134 25 NAME COMP 63 0 -COMP ALL 235 0 +COMP ALL 189 0 -DIEAREA ALL 235 4 +DIEAREA ALL 189 4 diff --git a/flow/platforms/nangate45/config.mk b/flow/platforms/nangate45/config.mk index 919217f716..ad2da77320 100644 --- a/flow/platforms/nangate45/config.mk +++ b/flow/platforms/nangate45/config.mk @@ -22,7 +22,7 @@ export FILL_CELLS ?= FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X1 # Yosys # ---------------------------------------------------- # Ungroup size for hierarchical synthesis -export MAX_UNGROUP_SIZE ?= 10000 +export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 # Set the TIEHI/TIELO cells # These are used in yosys synthesis to avoid logical 1/0's in the netlist export TIEHI_CELL_AND_PORT = LOGIC1_X1 Z @@ -50,8 +50,8 @@ export ABC_LOAD_IN_FF = 3.898 export PLACE_SITE = FreePDK45_38x28_10R_NP_162NW_34O # IO Placer pin layers -export IO_PLACER_H = metal5 -export IO_PLACER_V = metal6 +export IO_PLACER_H ?= metal5 +export IO_PLACER_V ?= metal6 # Define default PDN config export PDN_TCL ?= $(PLATFORM_DIR)/grid_strategy-M1-M4-M7.tcl @@ -61,7 +61,6 @@ export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl export TAP_CELL_NAME = TAPCELL_X1 export MACRO_PLACE_HALO ?= 22.4 15.12 -export MACRO_PLACE_CHANNEL ?= 18.8 19.95 #--------------------------------------------------------- # Place @@ -73,8 +72,13 @@ export PLACE_DENSITY ?= 0.30 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = metal2 +export MIN_CLK_ROUTING_LAYER = metal4 export MAX_ROUTING_LAYER = metal10 +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 + # Define fastRoute tcl export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl @@ -103,6 +107,6 @@ export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules # IR drop estimation supply net name to be analyzed and supply voltage variable # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD 1.1" -export GND_NETS_VOLTAGES ?= "VSS 0.0" +export PWR_NETS_VOLTAGES ?= VDD 1.1 +export GND_NETS_VOLTAGES ?= VSS 0.0 export IR_DROP_LAYER ?= metal1 diff --git a/flow/platforms/nangate45/fakeram.tcl b/flow/platforms/nangate45/fakeram.tcl index 4c8f9997e6..68d548e689 100644 --- a/flow/platforms/nangate45/fakeram.tcl +++ b/flow/platforms/nangate45/fakeram.tcl @@ -1,4 +1,3 @@ - set design_rams { swerv {2048x39 256x34 64x21} bp_be_top {64x96 512x64 64x15} @@ -11,7 +10,7 @@ set design_rams { set results_dir "~/import/fakeram/results" set flow_dir "~/import/flow/flow/platforms/nangate45" -proc make_fakeram_links {} { +proc make_fakeram_links { } { global design_rams flow_dir foreach {design sizes} $design_rams { @@ -27,13 +26,15 @@ proc make_fakeram_links {} { } } -proc copy_fakeram_results {} { +proc copy_fakeram_results { } { global design_rams results_dir flow_dir foreach {design sizes} $design_rams { foreach size $sizes { - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib - file copy -force $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lib $flow_dir/lib/fakeram45_$size.lib + file copy -force \ + $results_dir/fakeram45_$size/fakeram45_$size.lef $flow_dir/lef/fakeram45_$size.lef } } } diff --git a/flow/platforms/nangate45/fastroute.tcl b/flow/platforms/nangate45/fastroute.tcl index 2ec285bd96..7f6d9a242f 100644 --- a/flow/platforms/nangate45/fastroute.tcl +++ b/flow/platforms/nangate45/fastroute.tcl @@ -1,4 +1,5 @@ set_global_routing_layer_adjustment metal2-metal3 0.5 set_global_routing_layer_adjustment metal4-$::env(MAX_ROUTING_LAYER) 0.25 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl index a124d25802..02af27999c 100644 --- a/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl +++ b/flow/platforms/nangate45/grid_strategy-M1-M4-M7.tcl @@ -26,7 +26,8 @@ add_pdn_connect -grid {grid} -layers {metal4 metal7} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal5} -width {0.93} -pitch {10.0} -offset {2} add_pdn_stripe -grid {CORE_macro_grid_1} -layer {metal6} -width {0.93} -pitch {10.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal4 metal5} @@ -35,7 +36,8 @@ add_pdn_connect -grid {CORE_macro_grid_1} -layers {metal6 metal7} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -cells {.*} add_pdn_stripe -grid {CORE_macro_grid_2} -layer {metal6} -width {0.93} -pitch {40.0} -offset {2} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal4 metal6} add_pdn_connect -grid {CORE_macro_grid_2} -layers {metal6 metal7} diff --git a/flow/platforms/nangate45/make_tracks.tcl b/flow/platforms/nangate45/make_tracks.tcl index 923d6a1fda..0411a74b72 100644 --- a/flow/platforms/nangate45/make_tracks.tcl +++ b/flow/platforms/nangate45/make_tracks.tcl @@ -1,10 +1,10 @@ make_tracks metal1 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 -make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 -make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 -make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 +make_tracks metal2 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal3 -x_offset 0.095 -x_pitch 0.19 -y_offset 0.07 -y_pitch 0.14 +make_tracks metal4 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal5 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal6 -x_offset 0.095 -x_pitch 0.28 -y_offset 0.07 -y_pitch 0.28 +make_tracks metal7 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal8 -x_offset 0.095 -x_pitch 0.8 -y_offset 0.07 -y_pitch 0.8 +make_tracks metal9 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 make_tracks metal10 -x_offset 0.095 -x_pitch 1.6 -y_offset 0.07 -y_pitch 1.6 diff --git a/flow/platforms/nangate45/setRC.tcl b/flow/platforms/nangate45/setRC.tcl index d52baaa67d..f39d456de7 100644 --- a/flow/platforms/nangate45/setRC.tcl +++ b/flow/platforms/nangate45/setRC.tcl @@ -12,4 +12,4 @@ set_layer_rc -layer metal8 -resistance 1.8750e-04 -capacitance 9.69714E-02 #set_layer_rc -layer metal10 -resistance 3.7500e-05 -capacitance 2.8042e-02 set_wire_rc -signal -layer metal3 -set_wire_rc -clock -layer metal5 +set_wire_rc -clock -layer metal5 diff --git a/flow/platforms/nangate45/tapcell.tcl b/flow/platforms/nangate45/tapcell.tcl index 9057b795cd..edd4e1d15b 100644 --- a/flow/platforms/nangate45/tapcell.tcl +++ b/flow/platforms/nangate45/tapcell.tcl @@ -2,4 +2,3 @@ tapcell \ -distance 120 \ -tapcell_master "$::env(TAP_CELL_NAME)" \ -endcap_master "$::env(TAP_CELL_NAME)" - diff --git a/flow/platforms/nangate45/work_around_yosys/cells.v b/flow/platforms/nangate45/work_around_yosys/cells.v deleted file mode 100644 index 993a474cbf..0000000000 --- a/flow/platforms/nangate45/work_around_yosys/cells.v +++ /dev/null @@ -1,946 +0,0 @@ -module AND2_X1 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 & A2); -endmodule // AND2_X1 - -module AND2_X2 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 & A2); -endmodule // AND2_X2 - -module AND2_X4 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 & A2); -endmodule // AND2_X4 - -module AND3_X1 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 & A2 & A3); -endmodule // AND3_X1 - -module AND3_X2 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 & A2 & A3); -endmodule // AND3_X2 - -module AND3_X4 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 & A2 & A3); -endmodule // AND3_X4 - -module AND4_X1 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 & A2 & A3 & A4); -endmodule // AND4_X1 - -module AND4_X2 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 & A2 & A3 & A4); -endmodule // AND4_X2 - -module AND4_X4 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 & A2 & A3 & A4); -endmodule // AND4_X4 - -module AOI211_X1 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI211_X1 - -module AOI211_X2 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI211_X2 - -module AOI211_X4 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI211_X4 - -module AOI21_X1 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule // AOI21_X1 - -module AOI21_X2 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule // AOI21_X2 - -module AOI21_X4 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule // AOI21_X4 - -module AOI221_X1 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI221_X1 - -module AOI221_X2 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI221_X2 - -module AOI221_X4 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI221_X4 - -module AOI222_X1 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI222_X1 - -module AOI222_X2 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI222_X2 - -module AOI222_X4 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign C = (C1 & C2); - assign ZN = ~(A|B|C); -endmodule // AOI222_X4 - -module AOI22_X1 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule // AOI22_X1 - -module AOI22_X2 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule // AOI22_X2 - -module AOI22_X4 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1 & A2); - assign B = (B1 & B2); - assign ZN = ~(A|B); -endmodule - -module BUF_X1 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X1 - -module BUF_X2 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X2 - -module BUF_X4 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X4 - -module BUF_X8 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X8 - -module BUF_X16 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X16 - -module BUF_X32 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // BUF_X32 - -module CLKBUF_X1 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // CLKBUF_X1 - -module CLKBUF_X2 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // CLKBUF_X2 - -module CLKBUF_X3 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // CLKBUF_X3 - -module CLKBUF_X4 (A, Z); - input A; - output Z; - assign Z = (A); -endmodule // CLKBUF_X4 - -module DFF_X1 (CK, D, Q, QN); - input CK; - input D; - output Q; - output QN; - always @(posedge CK) begin - Q <= D; - QN <= ~D; - end -endmodule // DFF_X1 - -module DFF_X2 (CK, D, Q, QN); - input CK; - input D; - output Q; - output QN; - always @(posedge CK) begin - Q <= D; - QN <= ~D; - end -endmodule // DFF_X2 - -module DFFR_X1 (CK, D, RN, Q, QN); - input CK; - input D; - input RN; - output Q; - output QN; - always @(posedge CK or negedge RN) - if (RN==1'b0) - Q <= 0; - else - Q <= D; - assign QN = ~Q; -endmodule // DFF_X1 - -module DFFR_X2 (CK, D, RN, Q, QN); - input CK; - input D; - input RN; - output Q; - output QN; - always @(posedge CK or negedge RN) - if (RN==1'b0) - Q <= 0; - else - Q <= D; - assign QN = ~Q; -endmodule // DFF_X2 - -module DFFS_X1 (D, SN, CK, Q, QN); - input D; - input SN; - input CK; - output Q; - output QN; - always @(posedge CK or negedge SN) - if (SN==1'b0) - Q <= 1; - else - Q <= D; - assign QN = ~Q; -endmodule - -module DFFS_X2 (D, SN, CK, Q, QN); - input D; - input SN; - input CK; - output Q; - output QN; - always @(posedge CK or negedge SN) - if (SN==1'b0) - Q <= 1; - else - Q <= D; - assign QN = ~Q; -endmodule - -module HA_X1 (A, B, CO, S); - input A; - input B; - output CO; - output S; - assign S = A ^ B; // Dataflow expression for sum - assign CO = A & B; // Dataflow expression for carry -endmodule // HA_X1 - -module FA_X1 (A, B, CI, CO, S); - input A; - input B; - input CI; - output CO; - output S; - assign S = (A ^ B) ^ CI; - assign CO = (A & B) | (A & CI) | (B & CI); -endmodule - -module INV_X1 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X1 - -module INV_X16 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X16 - -module INV_X2 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X2 - -module INV_X32 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X32 - -module INV_X4 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X4 - -module INV_X8 (A, ZN); - input A; - output ZN; - assign ZN = ~A; -endmodule // INV_X8 - -module LOGIC0_X1 (Z); - output Z; - assign Z = 0; -endmodule // LOGIC0_X1 - -module LOGIC1_X1 (Z); - output Z; - assign Z = 1; -endmodule // LOGIC1_X1 - -module MUX2_X1 (A, B, S, Z); - input A, B, S; - output Z; - // assign one of the inputs to the output based upon select line input - assign Z = S ? B : A; -endmodule // MUX2_X1 - -module MUX2_X2 (A, B, S, Z); - input A, B, S; - output Z; - // assign one of the inputs to the output based upon select line input - assign Z = S ? B : A; -endmodule // MUX2_X2 - -module NAND2_X1 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~(A1 & A2); -endmodule // NAND2_X1 - -module NAND2_X2 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~(A1 & A2); -endmodule // NAND2_X2 - -module NAND2_X4 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~(A1 & A2); -endmodule // NAND2_X4 - -module NAND3_X1 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 & A2 & A3); -endmodule // NAND3_X1 - -module NAND3_X2 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 & A2 & A3); -endmodule // NAND3_X2 - -module NAND3_X4 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 & A2 & A3); -endmodule // NAND3_X4 - -module NAND4_X1 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 & A2 & A3 & A4); -endmodule // NAND4_X1 - -module NAND4_X2 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 & A2 & A3 & A4); -endmodule // NAND4_X2 - -module NAND4_X4 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 & A2 & A3 & A4); -endmodule // NAND4_X4 - -module NOR2_X1 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~(A1 | A2); -endmodule // NOR2_X1 - -module NOR2_X2 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~ (A1 | A2); -endmodule // NOR2_X2 - -module NOR2_X4 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = ~(A1 | A2); -endmodule // NOR2_X4 - -module NOR3_X1 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 | A2 | A3); -endmodule // NOR3_X1 - -module NOR3_X2 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 | A2 | A3); -endmodule // NOR3_X2 - -module NOR3_X4 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = ~(A1 | A2 | A3); -endmodule // NOR3_X4 - -module NOR4_X1 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 | A2 | A3 | A4); -endmodule // NOR4_X1 - -module NOR4_X2 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 | A2 | A3 | A4); -endmodule // NOR4_X2 - -module NOR4_X4 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = ~(A1 | A2 | A3 | A4); -endmodule // NOR4_X4 - -module OAI211_X1 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI211_X1 - -module OAI211_X2 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI211_X2 - -module OAI211_X4 (A, B, C1, C2, ZN); - input A; - input B; - input C1; - input C2; - output ZN; - wire C; - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI211_X4 - -module OAI21_X1 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI21_X1 - -module OAI21_X2 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI21_X2 - -module OAI21_X4 (A, B1, B2, ZN); - input A; - input B1; - input B2; - output ZN; - wire B; - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI21_X4 - -module OAI221_X1 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI221_X1 - -module OAI221_X2 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI221_X2 - -module OAI221_X4 (A, B1, B2, C1, C2, ZN); - input A; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire B; - wire C; - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI221_X4 - -module OAI222_X1 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1|A2); - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI222_X1 - -module OAI222_X2 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1|A2); - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI222_X2 - -module OAI222_X4 (A1, A2, B1, B2, C1, C2, ZN); - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - output ZN; - wire A; - wire B; - wire C; - assign A = (A1|A2); - assign B = (B1|B2); - assign C = (C1|C2); - assign ZN = ~(A & B & C); -endmodule // OAI222_X4 - -module OAI22_X1 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1|A2); - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI22_X1 - -module OAI22_X2 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1|A2); - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI22_X2 - -module OAI22_X4 (A1, A2, B1, B2, ZN); - input A1; - input A2; - input B1; - input B2; - output ZN; - wire A; - wire B; - assign A = (A1|A2); - assign B = (B1|B2); - assign ZN = ~(A & B); -endmodule // OAI22_X4 - -module OAI33_X1 (A1, A2, A3, B1, B2, B3, ZN); - input A1; - input A2; - input A3; - input B1; - input B2; - input B3; - output ZN; - wire A; - wire B; - assign A = (A1|A2|A3); - assign B = (B1|B2|B3); - assign ZN = ~(A & B); -endmodule // OAI33_X1 - -module OR2_X1 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 | A2); -endmodule // OR2_X1 - -module OR2_X2 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 | A2); -endmodule // OR2_X2 - -module OR2_X4 (A1, A2, ZN); - input A1; - input A2; - output ZN; - assign ZN = (A1 | A2); -endmodule // OR2_X4 - -module OR3_X1 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 | A2 | A3); -endmodule // OR3_X1 - -module OR3_X2 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 | A2 | A3); -endmodule // OR3_X2 - -module OR3_X4 (A1, A2, A3, ZN); - input A1; - input A2; - input A3; - output ZN; - assign ZN = (A1 | A2 | A3); -endmodule // OR3_X4 - -module OR4_X1 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 | A2 | A3 | A4); -endmodule // OR4_X1 - -module OR4_X2 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 | A2 | A3 | A4); -endmodule // OR4_X2 - -module OR4_X4 (A1, A2, A3, A4, ZN); - input A1; - input A2; - input A3; - input A4; - output ZN; - assign ZN = (A1 | A2 | A3 | A4); -endmodule // OR4_X4 - -module XNOR2_X1 (A, B, ZN); - input A; - input B; - output ZN; - assign ZN = (A ^~ B); -endmodule // XNOR_X1 - -module XNOR2_X2 (A, B, ZN); - input A; - input B; - output ZN; - assign ZN = (A ^~ B); -endmodule // XNOR_X2 - -module XNOR2_X4 (A, B, ZN); - input A; - input B; - output ZN; - assign ZN = (A ^~ B); -endmodule // XNOR_X4 - -module XOR2_X1 (A, B, Z); - input A; - input B; - output Z; - assign Z = (A ^ B); -endmodule // XOR2_X1 - -module XOR2_X2 (A, B, Z); - input A; - input B; - output Z; - assign Z = (A ^ B); -endmodule // XOR2_X2 - - diff --git a/flow/platforms/sky130hd/config.mk b/flow/platforms/sky130hd/config.mk index 165cf2f3dc..abd98c615a 100644 --- a/flow/platforms/sky130hd/config.mk +++ b/flow/platforms/sky130hd/config.mk @@ -77,6 +77,13 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hd.v # Define ABC driver and load export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 export ABC_LOAD_IN_FF = 5 + +# ----------------------------------------------------- +# Sizing +# ----------------------------------------------------- + +export MATCH_CELL_FOOTPRINT = 1 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- @@ -86,8 +93,8 @@ export ABC_LOAD_IN_FF = 5 export PLACE_SITE = unithd # IO Placer pin layers -export IO_PLACER_H = met3 -export IO_PLACER_V = met2 +export IO_PLACER_H ?= met3 +export IO_PLACER_V ?= met2 # Define default PDN config export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl @@ -97,7 +104,6 @@ export TAP_CELL_NAME = sky130_fd_sc_hd__tapvpwrvgnd_1 export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl export MACRO_PLACE_HALO ?= 40 40 -export MACRO_PLACE_CHANNEL ?= 80 80 #--------------------------------------------------------- # Place @@ -112,6 +118,10 @@ export MIN_ROUTING_LAYER ?= met1 export MIN_CLK_ROUTING_LAYER ?= met3 export MAX_ROUTING_LAYER ?= met5 # +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 +# # Define fastRoute tcl export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl @@ -133,8 +143,8 @@ export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules # IR drop estimation supply net name to be analyzed and supply voltage variable # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD 1.8" -export GND_NETS_VOLTAGES ?= "VSS 0.0" +export PWR_NETS_VOLTAGES ?= VDD 1.8 +export GND_NETS_VOLTAGES ?= VSS 0.0 export IR_DROP_LAYER ?= met1 # DRC Check diff --git a/flow/platforms/sky130hd/fastroute.tcl b/flow/platforms/sky130hd/fastroute.tcl index 24af379c99..76f9321967 100644 --- a/flow/platforms/sky130hd/fastroute.tcl +++ b/flow/platforms/sky130hd/fastroute.tcl @@ -2,4 +2,3 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - diff --git a/flow/platforms/sky130hd/pdn.tcl b/flow/platforms/sky130hd/pdn.tcl index 1901913015..cb158996c8 100644 --- a/flow/platforms/sky130hd/pdn.tcl +++ b/flow/platforms/sky130hd/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/platforms/sky130hd/work_around_yosys/formal_pdk.v b/flow/platforms/sky130hd/work_around_yosys/formal_pdk.v deleted file mode 100644 index 06bf4c1400..0000000000 --- a/flow/platforms/sky130hd/work_around_yosys/formal_pdk.v +++ /dev/null @@ -1,13411 +0,0 @@ -(* noblackbox *) module sky130_ef_sc_hd__decap_12 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_ef_sc_hd__fakediode_2 (DIODE); - - - input DIODE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__diode base ( - .DIODE(DIODE) - ); - - -endmodule -(* noblackbox *) module sky130_ef_sc_hd__fill_8 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - -endmodule -(* noblackbox *) module sky130_ef_sc_hd__fill_12 (); - - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fill base ( - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dff$NSR (Q,SET,RESET,CLK_N,D); -output Q; -input SET; -input RESET; -input CLK_N; -input D; -reg Q; -wire AD = SET; -wire AL = SET | RESET; -always @(negedge CLK_N or posedge AL) - if (AL) Q <= AD; - else Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dff$P (Q,D,CLK); -output Q; -input D; -input CLK; -reg Q; -always @(posedge CLK) Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dff$PR (Q,D,CLK,RESET); -output Q; -input D; -input CLK; -input RESET; -reg Q; -always @(posedge CLK or posedge RESET) - if (RESET) Q <= 1'b0; - else Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dff$PS (Q,D,CLK,SET); -output Q; -input D; -input CLK; -input SET; -reg Q; -always @(posedge CLK or posedge SET) - if (SET) Q <= 1'b1; - else Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dlatch$lP (Q,D,GATE); -output Q; -input D; -input GATE; -reg Q; -always @(GATE or D) - if (GATE) Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dlatch$P (Q,D,GATE); -output Q; -input D; -input GATE; -reg Q; -always @(GATE or D) - if (GATE) Q <= D; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_dlatch$PR (Q,D,GATE,RESET); -output Q; -input D; -input GATE; -input RESET; -reg Q; -wire AG = GATE | RESET; -wire AD = (~RESET) & D; -always @(AG or AD) - if (AG) Q <= AD; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_mux_2to1 (X,A0,A1,S); -output X; -reg X; -input A0; -input A1; -input S; -always @* casez ({A0,A1,S}) - 3'b00?: {X} = 1'b0; - 3'b11?: {X} = 1'b1; - 3'b0?0: {X} = 1'b0; - 3'b1?0: {X} = 1'b1; - 3'b?01: {X} = 1'b0; - 3'b?11: {X} = 1'b1; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_mux_2to1_N (Y,A0,A1,S); -output Y; -reg Y; -input A0; -input A1; -input S; -always @* casez ({A0,A1,S}) - 3'b0?0: {Y} = 1'b1; - 3'b1?0: {Y} = 1'b0; - 3'b?01: {Y} = 1'b1; - 3'b?11: {Y} = 1'b0; - 3'b00?: {Y} = 1'b1; - 3'b11?: {Y} = 1'b0; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_mux_4to2 (X,A0,A1,A2,A3,S0,S1); -output X; -reg X; -input A0; -input A1; -input A2; -input A3; -input S0; -input S1; -always @* casez ({A0,A1,A2,A3,S0,S1}) - 6'b0???00: {X} = 1'b0; - 6'b1???00: {X} = 1'b1; - 6'b?0??10: {X} = 1'b0; - 6'b?1??10: {X} = 1'b1; - 6'b??0?01: {X} = 1'b0; - 6'b??1?01: {X} = 1'b1; - 6'b???011: {X} = 1'b0; - 6'b???111: {X} = 1'b1; - 6'b0000??: {X} = 1'b0; - 6'b1111??: {X} = 1'b1; - 6'b00???0: {X} = 1'b0; - 6'b11???0: {X} = 1'b1; - 6'b??00?1: {X} = 1'b0; - 6'b??11?1: {X} = 1'b1; - 6'b0?0?0?: {X} = 1'b0; - 6'b1?1?0?: {X} = 1'b1; - 6'b?0?01?: {X} = 1'b0; - 6'b?1?11?: {X} = 1'b1; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_pwrgood$l_pp$G (UDP_OUT,UDP_IN,VGND); -output UDP_OUT; -input UDP_IN; -input VGND; -assign UDP_OUT = UDP_IN; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_pwrgood_pp$G (UDP_OUT,UDP_IN,VGND); -output UDP_OUT; -input UDP_IN; -input VGND; -assign UDP_OUT = UDP_IN; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__udp_pwrgood_pp$P (UDP_OUT,UDP_IN,VPWR); -output UDP_OUT; -input UDP_IN; -input VPWR; -assign UDP_OUT = UDP_IN; -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2o (X,A1_N,A2_N,B1,B2); - - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire and0_out ; - wire nor0_out ; - wire or0_out_X; - - - and and0 (and0_out , B1, B2 ); - nor nor0 (nor0_out , A1_N, A2_N ); - or or0 (or0_out_X, nor0_out, and0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2o_1 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2o_2 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2o_4 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2oi (Y,A1_N,A2_N,B1,B2); - - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire and0_out ; - wire nor0_out ; - wire nor1_out_Y; - - - and and0 (and0_out , B1, B2 ); - nor nor0 (nor0_out , A1_N, A2_N ); - nor nor1 (nor1_out_Y, nor0_out, and0_out); - buf buf0 (Y , nor1_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2oi_1 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2oi_2 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2bb2oi_4 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21bo (X,A1,A2,B1_N); - - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - wire nand0_out ; - wire nand1_out_X; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out_X, B1_N, nand0_out); - buf buf0 (X , nand1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21bo_1 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21bo_2 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21bo_4 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21boi (Y,A1,A2,B1_N); - - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - wire b ; - wire and0_out ; - wire nor0_out_Y; - - - not not0 (b , B1_N ); - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, b, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21boi_0 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21boi_1 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21boi_2 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21boi_4 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21o (X,A1,A2,B1); - - - - output X ; - input A1; - input A2; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21o_1 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21o_2 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21o_4 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21oi (Y,A1,A2,B1); - - - - output Y ; - input A1; - input A2; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21oi_1 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21oi_2 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a21oi_4 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22o (X,A1,A2,B1,B2); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - or or0 (or0_out_X, and1_out, and0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22o_1 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22o_2 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22o_4 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22oi (Y,A1,A2,B1,B2); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - wire nand0_out ; - wire nand1_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out , B2, B1 ); - and and0 (and0_out_Y, nand0_out, nand1_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22oi_1 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22oi_2 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a22oi_4 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31o (X,A1,A2,A3,B1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A3, A1, A2 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31o_1 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31o_2 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31o_4 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31oi (Y,A1,A2,A3,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A3, A1, A2 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31oi_1 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31oi_2 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a31oi_4 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32o (X,A1,A2,A3,B1,B2); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , A3, A1, A2 ); - and and1 (and1_out , B1, B2 ); - or or0 (or0_out_X, and1_out, and0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32o_1 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32o_2 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32o_4 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32oi (Y,A1,A2,A3,B1,B2); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire nand0_out ; - wire nand1_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1, A3 ); - nand nand1 (nand1_out , B2, B1 ); - and and0 (and0_out_Y, nand0_out, nand1_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32oi_1 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32oi_2 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a32oi_4 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41o (X,A1,A2,A3,A4,B1); - - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2, A3, A4 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41o_1 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41o_2 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41o_4 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41oi (Y,A1,A2,A3,A4,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2, A3, A4 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41oi_1 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41oi_2 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a41oi_4 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211o (X,A1,A2,B1,C1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, and0_out, C1, B1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211o_1 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211o_2 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211o_4 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211oi (Y,A1,A2,B1,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, B1, C1); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211oi_1 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211oi_2 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a211oi_4 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221o (X,A1,A2,B1,B2,C1); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - or or0 (or0_out_X, and1_out, and0_out, C1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221o_1 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221o_2 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221o_4 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221oi (Y,A1,A2,B1,B2,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire and0_out ; - wire and1_out ; - wire nor0_out_Y; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, C1, and1_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221oi_1 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221oi_2 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a221oi_4 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a222oi (Y,A1,A2,B1,B2,C1,C2); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - wire nand0_out ; - wire nand1_out ; - wire nand2_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out , B2, B1 ); - nand nand2 (nand2_out , C2, C1 ); - and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a222oi_1 (Y,A1,A2,B1,B2,C1,C2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a222oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1), - .C2(C2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311o (X,A1,A2,A3,B1,C1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A3, A1, A2 ); - or or0 (or0_out_X, and0_out, C1, B1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311o_1 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311o_2 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311o_4 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311oi (Y,A1,A2,A3,B1,C1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A3, A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, B1, C1); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311oi_1 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311oi_2 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a311oi_4 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111o (X,A1,A2,B1,C1,D1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, C1, B1, and0_out, D1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111o_1 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111o_2 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111o_4 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111oi (Y,A1,A2,B1,C1,D1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, B1, C1, D1, and0_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111oi_0 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111oi_1 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111oi_2 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__a2111oi_4 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2 (X,A,B); - - - - output X; - input A; - input B; - - - wire and0_out_X; - - - and and0 (and0_out_X, A, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2_0 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2b (X,A_N,B); - - - - output X ; - input A_N; - input B ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, not0_out, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2b_1 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2b_2 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and2b_4 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire and0_out_X; - - - and and0 (and0_out_X, C, A, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3b (X,A_N,B,C); - - - - output X ; - input A_N; - input B ; - input C ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, C, not0_out, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3b_1 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3b_2 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and3b_4 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4 (X,A,B,C,D); - - - - output X; - input A; - input B; - input C; - input D; - - - wire and0_out_X; - - - and and0 (and0_out_X, A, B, C, D ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4_1 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4_2 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4_4 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4b (X,A_N,B,C,D); - - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, not0_out, B, C, D); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4b_1 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4b_2 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4b_4 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4bb (X,A_N,B_N,C,D); - - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - wire nor0_out ; - wire and0_out_X; - - - nor nor0 (nor0_out , A_N, B_N ); - and and0 (and0_out_X, nor0_out, C, D ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4bb_1 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4bb_2 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__and4bb_4 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_4 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_6 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_12 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__buf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufbuf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufbuf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__bufbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufbuf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__bufbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufinv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufinv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__bufinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__bufinv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__bufinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf_4 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkbuf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s15 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s15_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s15 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s15_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s15 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s18 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s18_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s18 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s18_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s18 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s25 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s25_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s25 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s25_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s25 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s50 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s50_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s50 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkdlybuf4s50_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkdlybuf4s50 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv_1 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinvlp (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinvlp_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinvlp base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__clkinvlp_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__clkinvlp base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__conb (HI,LO); - - - - output HI; - output LO; - - - mod_pullup pullup0 (HI ); - mod_pulldown pulldown0 (LO ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__conb_1 (HI,LO); - - - output HI; - output LO; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__conb base ( - .HI(HI), - .LO(LO) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap_3 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap_4 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap_6 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap_8 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__decap_12 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfbbn (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - wire RESET; - wire SET ; - wire CLK ; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - not not2 (CLK , CLK_N ); - sky130_fd_sc_hd__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, D); - buf buf0 (Q , buf_Q ); - not not3 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfbbn_1 (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfbbn_2 (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfbbp (Q,Q_N,D,CLK,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input CLK ; - input SET_B ; - input RESET_B; - - - wire RESET; - wire SET ; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - sky130_fd_sc_hd__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, D); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfbbp_1 (Q,Q_N,D,CLK,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfbbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK(CLK), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrbp (Q,Q_N,CLK,D,RESET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - wire buf_Q; - wire RESET; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , D, CLK, RESET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrbp_1 (Q,Q_N,CLK,D,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrbp_2 (Q,Q_N,CLK,D,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtn (Q,CLK_N,D,RESET_B); - - - - output Q ; - input CLK_N ; - input D ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire intclk; - - - not not0 (RESET , RESET_B ); - not not1 (intclk, CLK_N ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , D, intclk, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtn_1 (Q,CLK_N,D,RESET_B); - - - output Q ; - input CLK_N ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrtn base ( - .Q(Q), - .CLK_N(CLK_N), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtp (Q,CLK,D,RESET_B); - - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - wire buf_Q; - wire RESET; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , D, CLK, RESET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtp_1 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtp_2 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfrtp_4 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfsbp (Q,Q_N,CLK,D,SET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - wire buf_Q; - wire SET ; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hd__udp_dff$PS dff0 (buf_Q , D, CLK, SET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfsbp_1 (Q,Q_N,CLK,D,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfsbp_2 (Q,Q_N,CLK,D,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfstp (Q,CLK,D,SET_B); - - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - wire buf_Q; - wire SET ; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hd__udp_dff$PS dff0 (buf_Q , D, CLK, SET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfstp_1 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfstp_2 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfstp_4 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxbp (Q,Q_N,CLK,D); - - - - output Q ; - output Q_N; - input CLK; - input D ; - - - wire buf_Q; - - - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , D, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxbp_1 (Q,Q_N,CLK,D); - - - output Q ; - output Q_N; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxbp_2 (Q,Q_N,CLK,D); - - - output Q ; - output Q_N; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxtp (Q,CLK,D); - - - - output Q ; - input CLK; - input D ; - - - wire buf_Q; - - - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , D, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxtp_1 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxtp_2 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dfxtp_4 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__diode (DIODE); - - - - input DIODE; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__diode_2 (DIODE); - - - input DIODE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__diode base ( - .DIODE(DIODE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlclkp (GCLK,GATE,CLK); - - - - output GCLK; - input GATE; - input CLK ; - - - wire m0 ; - wire clkn; - - - not not0 (clkn , CLK ); - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn ); - and and0 (GCLK , m0, CLK ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlclkp_1 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlclkp_2 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlclkp_4 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbn (Q,Q_N,RESET_B,D,GATE_N); - - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - wire RESET ; - wire intgate; - wire buf_Q ; - - - not not0 (RESET , RESET_B ); - not not1 (intgate, GATE_N ); - sky130_fd_sc_hd__udp_dlatch$PR dlatch0 (buf_Q , D, intgate, RESET); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbn_1 (Q,Q_N,RESET_B,D,GATE_N); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrbn base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbn_2 (Q,Q_N,RESET_B,D,GATE_N); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrbn base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbp (Q,Q_N,RESET_B,D,GATE); - - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - wire RESET; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_dlatch$PR dlatch0 (buf_Q , D, GATE, RESET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbp_1 (Q,Q_N,RESET_B,D,GATE); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrbp base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrbp_2 (Q,Q_N,RESET_B,D,GATE); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrbp base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtn (Q,RESET_B,D,GATE_N); - - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - wire RESET ; - wire intgate; - wire buf_Q ; - - - not not0 (RESET , RESET_B ); - not not1 (intgate, GATE_N ); - sky130_fd_sc_hd__udp_dlatch$PR dlatch0 (buf_Q , D, intgate, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtn_1 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtn_2 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtn_4 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtp (Q,RESET_B,D,GATE); - - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - wire RESET; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_dlatch$PR dlatch0 (buf_Q , D, GATE, RESET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtp_1 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtp_2 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlrtp_4 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxbn (Q,Q_N,D,GATE_N); - - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - wire GATE ; - wire buf_Q; - - - not not0 (GATE , GATE_N ); - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxbn_1 (Q,Q_N,D,GATE_N); - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxbn_2 (Q,Q_N,D,GATE_N); - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxbp (Q,Q_N,D,GATE); - - - - output Q ; - output Q_N ; - input D ; - input GATE; - - - wire buf_Q; - - - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxbp_1 (Q,Q_N,D,GATE); - - - output Q ; - output Q_N ; - input D ; - input GATE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtn (Q,D,GATE_N); - - - - output Q ; - input D ; - input GATE_N; - - - wire GATE ; - wire buf_Q; - - - not not0 (GATE , GATE_N ); - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtn_1 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtn_2 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtn_4 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtp (Q,D,GATE); - - - - output Q ; - input D ; - input GATE; - - - wire buf_Q; - - - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlxtp_1 (Q,D,GATE); - - - output Q ; - input D ; - input GATE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlxtp base ( - .Q(Q), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd1 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd1_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlygate4sd1 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd2 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd2_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlygate4sd2 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd3 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlygate4sd3_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlygate4sd3 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s2s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s2s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlymetal6s2s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s4s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s4s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlymetal6s4s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s6s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__dlymetal6s6s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__dlymetal6s6s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ebufn (Z,A,TE_B); - - - - output Z ; - input A ; - input TE_B; - - - bufif0 bufif00 (Z , A, TE_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ebufn_1 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ebufn_2 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ebufn_4 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ebufn_8 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__edfxbp (Q,Q_N,CLK,D,DE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__edfxbp_1 (Q,Q_N,CLK,D,DE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__edfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__edfxtp (Q,CLK,D,DE); - - - - output Q ; - input CLK; - input D ; - input DE ; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__edfxtp_1 (Q,CLK,D,DE); - - - output Q ; - input CLK; - input D ; - input DE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__edfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn (Z,A,TE_B); - - - - output Z ; - input A ; - input TE_B; - - - notif0 notif00 (Z , A, TE_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn_0 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn_1 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn_2 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn_4 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvn_8 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvp (Z,A,TE); - - - - output Z ; - input A ; - input TE; - - - notif1 notif10 (Z , A, TE ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvp_1 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvp_2 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvp_4 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__einvp_8 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fa (COUT,SUM,A,B,CIN); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - wire or0_out ; - wire and0_out ; - wire and1_out ; - wire and2_out ; - wire nor0_out ; - wire nor1_out ; - wire or1_out_COUT; - wire or2_out_SUM ; - - - or or0 (or0_out , CIN, B ); - and and0 (and0_out , or0_out, A ); - and and1 (and1_out , B, CIN ); - or or1 (or1_out_COUT, and1_out, and0_out); - buf buf0 (COUT , or1_out_COUT ); - and and2 (and2_out , CIN, A, B ); - nor nor0 (nor0_out , A, or0_out ); - nor nor1 (nor1_out , nor0_out, COUT ); - or or2 (or2_out_SUM , nor1_out, and2_out); - buf buf1 (SUM , or2_out_SUM ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fa_1 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fa_2 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fa_4 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fah (COUT,SUM,A,B,CI); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CI ; - - - wire xor0_out_SUM; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_COUT; - - - xor xor0 (xor0_out_SUM, A, B, CI ); - buf buf0 (SUM , xor0_out_SUM ); - and and0 (a_b , A, B ); - and and1 (a_ci , A, CI ); - and and2 (b_ci , B, CI ); - or or0 (or0_out_COUT, a_b, a_ci, b_ci); - buf buf1 (COUT , or0_out_COUT ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fah_1 (COUT,SUM,A,B,CI); - - - output COUT; - output SUM ; - input A ; - input B ; - input CI ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fah base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CI(CI) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fahcin (COUT,SUM,A,B,CIN); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - wire ci ; - wire xor0_out_SUM; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_COUT; - - - not not0 (ci , CIN ); - xor xor0 (xor0_out_SUM, A, B, ci ); - buf buf0 (SUM , xor0_out_SUM ); - and and0 (a_b , A, B ); - and and1 (a_ci , A, ci ); - and and2 (b_ci , B, ci ); - or or0 (or0_out_COUT, a_b, a_ci, b_ci); - buf buf1 (COUT , or0_out_COUT ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fahcin_1 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fahcin base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fahcon (COUT_N,SUM,A,B,CI); - - - - output COUT_N; - output SUM ; - input A ; - input B ; - input CI ; - - - wire xor0_out_SUM ; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_coutn; - - - xor xor0 (xor0_out_SUM , A, B, CI ); - buf buf0 (SUM , xor0_out_SUM ); - nor nor0 (a_b , A, B ); - nor nor1 (a_ci , A, CI ); - nor nor2 (b_ci , B, CI ); - or or0 (or0_out_coutn, a_b, a_ci, b_ci); - buf buf1 (COUT_N , or0_out_coutn ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fahcon_1 (COUT_N,SUM,A,B,CI); - - - output COUT_N; - output SUM ; - input A ; - input B ; - input CI ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fahcon base ( - .COUT_N(COUT_N), - .SUM(SUM), - .A(A), - .B(B), - .CI(CI) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fill (); - - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fill_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fill_2 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fill_4 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__fill_8 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ha (COUT,SUM,A,B); - - - - output COUT; - output SUM ; - input A ; - input B ; - - - wire and0_out_COUT; - wire xor0_out_SUM ; - - - and and0 (and0_out_COUT, A, B ); - buf buf0 (COUT , and0_out_COUT ); - xor xor0 (xor0_out_SUM , B, A ); - buf buf1 (SUM , xor0_out_SUM ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ha_1 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ha_2 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__ha_4 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_1 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_6 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_12 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__inv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_bleeder (SHORT); - - - input SHORT; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_bleeder_1 (SHORT); - - - input SHORT; - - - wire VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_bleeder base ( - .SHORT(SHORT) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr_1 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkbufkapwr_16 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr_1 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr_2 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr_4 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr_3 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr_4 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr_6 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr_8 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_decapkapwr_12 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso0n (X,A,SLEEP_B); - - - - output X ; - input A ; - input SLEEP_B; - - - and and0 (X , A, SLEEP_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso0n_1 (X,A,SLEEP_B); - - - output X ; - input A ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_inputiso0n base ( - .X(X), - .A(A), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso0p (X,A,SLEEP); - - - - output X ; - input A ; - input SLEEP; - - - wire sleepn; - - - not not0 (sleepn, SLEEP ); - and and0 (X , A, sleepn ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso0p_1 (X,A,SLEEP); - - - output X ; - input A ; - input SLEEP; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_inputiso0p base ( - .X(X), - .A(A), - .SLEEP(SLEEP) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso1n (X,A,SLEEP_B); - - - - output X ; - input A ; - input SLEEP_B; - - - wire SLEEP; - - - not not0 (SLEEP , SLEEP_B ); - or or0 (X , A, SLEEP ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso1n_1 (X,A,SLEEP_B); - - - output X ; - input A ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_inputiso1n base ( - .X(X), - .A(A), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso1p (X,A,SLEEP); - - - - output X ; - input A ; - input SLEEP; - - - or or0 (X , A, SLEEP ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputiso1p_1 (X,A,SLEEP); - - - output X ; - input A ; - input SLEEP; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_inputiso1p base ( - .X(X), - .A(A), - .SLEEP(SLEEP) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputisolatch (Q,D,SLEEP_B); - - - - output Q ; - input D ; - input SLEEP_B; - - - wire buf_Q; - - - sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_inputisolatch_1 (Q,D,SLEEP_B); - - - output Q ; - input D ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_inputisolatch base ( - .Q(Q), - .D(D), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc (X,SLEEP,A); - - - - output X ; - input SLEEP; - input A ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , SLEEP ); - and and0 (and0_out_X, not0_out, A ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc_1 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc_2 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc_4 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc_8 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrc_16 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrckapwr (X,SLEEP,A); - - - - output X ; - input SLEEP; - input A ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , SLEEP ); - and and0 (and0_out_X, not0_out, A ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_isobufsrckapwr base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__macro_sparecell (LO); - - - - output LO; - - - wire nor2left ; - wire invleft ; - wire nor2right; - wire invright ; - wire nd2left ; - wire nd2right ; - wire tielo ; - wire net7 ; - - - sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) ); - sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) ); - sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) ); - sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right)); - sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) ); - sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) ); - sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) ); - buf buf0 (LO , tielo ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__maj3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire or0_out ; - wire and0_out ; - wire and1_out ; - wire or1_out_X; - - - or or0 (or0_out , B, A ); - and and0 (and0_out , or0_out, C ); - and and1 (and1_out , A, B ); - or or1 (or1_out_X, and1_out, and0_out); - buf buf0 (X , or1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__maj3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__maj3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__maj3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2 (X,A0,A1,S); - - - - output X ; - input A0; - input A1; - input S ; - - - wire mux_2to10_out_X; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S ); - buf buf0 (X , mux_2to10_out_X); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2_1 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2_2 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2_4 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2_8 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2i (Y,A0,A1,S); - - - - output Y ; - input A0; - input A1; - input S ; - - - wire mux_2to1_n0_out_Y; - - - sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S ); - buf buf0 (Y , mux_2to1_n0_out_Y); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2i_1 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2i_2 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux2i_4 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux4 (X,A0,A1,A2,A3,S0,S1); - - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - wire mux_4to20_out_X; - - - sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1); - buf buf0 (X , mux_4to20_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux4_1 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux4_2 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__mux4_4 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, B, A ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2_8 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2b (Y,A_N,B); - - - - output Y ; - input A_N; - input B ; - - - wire not0_out ; - wire or0_out_Y; - - - not not0 (not0_out , B ); - or or0 (or0_out_Y, not0_out, A_N ); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2b_1 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2b_2 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand2b_4 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3 (Y,A,B,C); - - - - output Y; - input A; - input B; - input C; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, B, A, C ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3_1 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3_2 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3_4 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3b (Y,A_N,B,C); - - - - output Y ; - input A_N; - input B ; - input C ; - - - wire not0_out ; - wire nand0_out_Y; - - - not not0 (not0_out , A_N ); - nand nand0 (nand0_out_Y, B, not0_out, C ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3b_1 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3b_2 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand3b_4 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4 (Y,A,B,C,D); - - - - output Y; - input A; - input B; - input C; - input D; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, D, C, B, A ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4_1 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4_2 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4_4 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4b (Y,A_N,B,C,D); - - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - wire not0_out ; - wire nand0_out_Y; - - - not not0 (not0_out , A_N ); - nand nand0 (nand0_out_Y, D, C, B, not0_out); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4b_1 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4b_2 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4b_4 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4bb (Y,A_N,B_N,C,D); - - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - wire nand0_out; - wire or0_out_Y; - - - nand nand0 (nand0_out, D, C ); - or or0 (or0_out_Y, B_N, A_N, nand0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4bb_1 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4bb_2 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nand4bb_4 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, A, B ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2_8 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2b (Y,A,B_N); - - - - output Y ; - input A ; - input B_N; - - - wire not0_out ; - wire and0_out_Y; - - - not not0 (not0_out , A ); - and and0 (and0_out_Y, not0_out, B_N ); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2b_1 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2b_2 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor2b_4 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3 (Y,A,B,C); - - - - output Y; - input A; - input B; - input C; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, C, A, B ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3_1 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3_2 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3_4 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3b (Y,A,B,C_N); - - - - output Y ; - input A ; - input B ; - input C_N; - - - wire nor0_out ; - wire and0_out_Y; - - - nor nor0 (nor0_out , A, B ); - and and0 (and0_out_Y, C_N, nor0_out ); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3b_1 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3b_2 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor3b_4 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4 (Y,A,B,C,D); - - - - output Y; - input A; - input B; - input C; - input D; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, A, B, C, D ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4_1 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4_2 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4_4 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4b (Y,A,B,C,D_N); - - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - wire not0_out ; - wire nor0_out_Y; - - - not not0 (not0_out , D_N ); - nor nor0 (nor0_out_Y, A, B, C, not0_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4b_1 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4b_2 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4b_4 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4bb (Y,A,B,C_N,D_N); - - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - wire nor0_out ; - wire and0_out_Y; - - - nor nor0 (nor0_out , A, B ); - and and0 (and0_out_Y, nor0_out, C_N, D_N); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4bb_1 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4bb_2 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__nor4bb_4 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2a (X,A1_N,A2_N,B1,B2); - - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire nand0_out ; - wire or0_out ; - wire and0_out_X; - - - nand nand0 (nand0_out , A2_N, A1_N ); - or or0 (or0_out , B2, B1 ); - and and0 (and0_out_X, nand0_out, or0_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2a_1 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2a_2 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2a_4 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2ai (Y,A1_N,A2_N,B1,B2); - - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire nand0_out ; - wire or0_out ; - wire nand1_out_Y; - - - nand nand0 (nand0_out , A2_N, A1_N ); - or or0 (or0_out , B2, B1 ); - nand nand1 (nand1_out_Y, nand0_out, or0_out); - buf buf0 (Y , nand1_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2ai_1 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2ai_2 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2bb2ai_4 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21a (X,A1,A2,B1); - - - - output X ; - input A1; - input A2; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21a_1 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21a_2 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21a_4 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ai (Y,A1,A2,B1); - - - - output Y ; - input A1; - input A2; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ai_0 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ai_1 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ai_2 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ai_4 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ba (X,A1,A2,B1_N); - - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - wire nor0_out ; - wire nor1_out_X; - - - nor nor0 (nor0_out , A1, A2 ); - nor nor1 (nor1_out_X, B1_N, nor0_out ); - buf buf0 (X , nor1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ba_1 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ba_2 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21ba_4 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21bai (Y,A1,A2,B1_N); - - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - wire b ; - wire or0_out ; - wire nand0_out_Y; - - - not not0 (b , B1_N ); - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, b, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21bai_1 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21bai_2 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o21bai_4 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22a (X,A1,A2,B1,B2); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - or or1 (or1_out , B2, B1 ); - and and0 (and0_out_X, or0_out, or1_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22a_1 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22a_2 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22a_4 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22ai (Y,A1,A2,B1,B2); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - wire nor0_out ; - wire nor1_out ; - wire or0_out_Y; - - - nor nor0 (nor0_out , B1, B2 ); - nor nor1 (nor1_out , A1, A2 ); - or or0 (or0_out_Y, nor1_out, nor0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22ai_1 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22ai_2 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o22ai_4 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31a (X,A1,A2,A3,B1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31a_1 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31a_2 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31a_4 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31ai (Y,A1,A2,A3,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1, A3 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31ai_1 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31ai_2 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o31ai_4 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32a (X,A1,A2,A3,B1,B2); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - or or1 (or1_out , B2, B1 ); - and and0 (and0_out_X, or0_out, or1_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32a_1 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32a_2 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32a_4 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32ai (Y,A1,A2,A3,B1,B2); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire nor0_out ; - wire nor1_out ; - wire or0_out_Y; - - - nor nor0 (nor0_out , A3, A1, A2 ); - nor nor1 (nor1_out , B1, B2 ); - or or0 (or0_out_Y, nor1_out, nor0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32ai_1 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32ai_2 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o32ai_4 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41a (X,A1,A2,A3,A4,B1); - - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A4, A3, A2, A1 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41a_1 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41a_2 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41a_4 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41ai (Y,A1,A2,A3,A4,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A4, A3, A2, A1 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41ai_1 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41ai_2 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o41ai_4 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211a (X,A1,A2,B1,C1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, or0_out, B1, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211a_1 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211a_2 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211a_4 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211ai (Y,A1,A2,B1,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, C1, or0_out, B1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211ai_1 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211ai_2 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o211ai_4 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221a (X,A1,A2,B1,B2,C1); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , B2, B1 ); - or or1 (or1_out , A2, A1 ); - and and0 (and0_out_X, or0_out, or1_out, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221a_1 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221a_2 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221a_4 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221ai (Y,A1,A2,B1,B2,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire or0_out ; - wire or1_out ; - wire nand0_out_Y; - - - or or0 (or0_out , B2, B1 ); - or or1 (or1_out , A2, A1 ); - nand nand0 (nand0_out_Y, or1_out, or0_out, C1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221ai_1 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221ai_2 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o221ai_4 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311a (X,A1,A2,A3,B1,C1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - and and0 (and0_out_X, or0_out, B1, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311a_1 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311a_2 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311a_4 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311ai (Y,A1,A2,A3,B1,C1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1, A3 ); - nand nand0 (nand0_out_Y, C1, or0_out, B1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311ai_0 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311ai_1 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311ai_2 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o311ai_4 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111a (X,A1,A2,B1,C1,D1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, B1, C1, or0_out, D1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111a_1 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111a_2 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111a_4 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111ai (Y,A1,A2,B1,C1,D1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, C1, B1, D1, or0_out); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111ai_1 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111ai_2 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__o2111ai_4 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2 (X,A,B); - - - - output X; - input A; - input B; - - - wire or0_out_X; - - - or or0 (or0_out_X, B, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2_0 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2b (X,A,B_N); - - - - output X ; - input A ; - input B_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , B_N ); - or or0 (or0_out_X, not0_out, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2b_1 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2b_2 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or2b_4 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire or0_out_X; - - - or or0 (or0_out_X, B, A, C ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3b (X,A,B,C_N); - - - - output X ; - input A ; - input B ; - input C_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , C_N ); - or or0 (or0_out_X, B, A, not0_out ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3b_1 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3b_2 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or3b_4 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4 (X,A,B,C,D); - - - - output X; - input A; - input B; - input C; - input D; - - - wire or0_out_X; - - - or or0 (or0_out_X, D, C, B, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4_1 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4_2 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4_4 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4b (X,A,B,C,D_N); - - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , D_N ); - or or0 (or0_out_X, not0_out, C, B, A); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4b_1 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4b_2 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4b_4 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4bb (X,A,B,C_N,D_N); - - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - wire nand0_out; - wire or0_out_X; - - - nand nand0 (nand0_out, D_N, C_N ); - or or0 (or0_out_X, B, A, nand0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4bb_1 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4bb_2 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__or4bb_4 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__probe_p (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__probe_p_8 (X,A); - - - output X; - input A; - - - supply0 VGND; - supply0 VNB ; - supply1 VPB ; - supply1 VPWR; - - sky130_fd_sc_hd__probe_p base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__probec_p (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__probec_p_8 (X,A); - - - output X; - input A; - - - supply0 VGND; - supply0 VNB ; - supply1 VPB ; - supply1 VPWR; - - sky130_fd_sc_hd__probec_p base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfbbn (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - wire RESET ; - wire SET ; - wire CLK ; - wire buf_Q ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - not not2 (CLK , CLK_N ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, mux_out); - buf buf0 (Q , buf_Q ); - not not3 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfbbn_1 (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfbbn_2 (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfbbp (Q,Q_N,D,SCD,SCE,CLK,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK ; - input SET_B ; - input RESET_B; - - - wire RESET ; - wire SET ; - wire buf_Q ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, mux_out); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfbbp_1 (Q,Q_N,D,SCD,SCE,CLK,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfbbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK(CLK), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrbp (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , mux_out, CLK, RESET); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrbp_1 (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrbp_2 (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtn (Q,CLK_N,D,SCD,SCE,RESET_B); - - - - output Q ; - input CLK_N ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire intclk ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (intclk , CLK_N ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , mux_out, intclk, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtn_1 (Q,CLK_N,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK_N ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrtn base ( - .Q(Q), - .CLK_N(CLK_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtp (Q,CLK,D,SCD,SCE,RESET_B); - - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$PR dff0 (buf_Q , mux_out, CLK, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtp_1 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtp_2 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfrtp_4 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfsbp (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - wire buf_Q ; - wire SET ; - wire mux_out; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$PS dff0 (buf_Q , mux_out, CLK, SET); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfsbp_1 (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfsbp_2 (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfstp (Q,CLK,D,SCD,SCE,SET_B); - - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - wire buf_Q ; - wire SET ; - wire mux_out; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$PS dff0 (buf_Q , mux_out, CLK, SET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfstp_1 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfstp_2 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfstp_4 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxbp (Q,Q_N,CLK,D,SCD,SCE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxbp_1 (Q,Q_N,CLK,D,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxbp_2 (Q,Q_N,CLK,D,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxtp (Q,CLK,D,SCD,SCE); - - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxtp_1 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxtp_2 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdfxtp_4 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdlclkp (GCLK,SCE,GATE,CLK); - - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - wire m0 ; - wire m0n ; - wire clkn ; - wire SCE_GATE; - - - not not0 (m0n , m0 ); - not not1 (clkn , CLK ); - nor nor0 (SCE_GATE, GATE, SCE ); - sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn ); - and and0 (GCLK , m0n, CLK ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdlclkp_1 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdlclkp_2 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sdlclkp_4 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxbp (Q,Q_N,CLK,D,DE,SCD,SCE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - wire de_d ; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxbp_1 (Q,Q_N,CLK,D,DE,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sedfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxbp_2 (Q,Q_N,CLK,D,DE,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sedfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxtp (Q,CLK,D,DE,SCD,SCE); - - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - wire de_d ; - - - sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); - sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); - sky130_fd_sc_hd__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxtp_1 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxtp_2 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__sedfxtp_4 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tap (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tap_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__tap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tap_2 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__tap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvgnd2 (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvgnd2_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__tapvgnd2 base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvgnd (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvgnd_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__tapvgnd base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvpwrvgnd (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__tapvpwrvgnd_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__tapvpwrvgnd base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire xnor0_out_Y; - - - xnor xnor0 (xnor0_out_Y, A, B ); - buf buf0 (Y , xnor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire xnor0_out_X; - - - xnor xnor0 (xnor0_out_X, A, B, C ); - buf buf0 (X , xnor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xnor3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor2 (X,A,B); - - - - output X; - input A; - input B; - - - wire xor0_out_X; - - - xor xor0 (xor0_out_X, B, A ); - buf buf0 (X , xor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire xor0_out_X; - - - xor xor0 (xor0_out_X, A, B, C ); - buf buf0 (X , xor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hd__xor3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hd__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module mod_pullup (Y); -output Y; -assign Y = 1'b1; -endmodule -(* noblackbox *) module mod_pulldown (Y); -output Y; -assign Y = 1'b0; -endmodule diff --git a/flow/platforms/sky130hd_fakestack/README.md b/flow/platforms/sky130hd_fakestack/README.md deleted file mode 100644 index 46f94da2df..0000000000 --- a/flow/platforms/sky130hd_fakestack/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# Summary -The SKY130HD library has a 5 layer metal stack. As a result, it is very difficult to Place and route designs that contain large number of hard macros. To enable the use of the library for research purposes, we have extended the layer stack to 9 metal layers. The only change is the tech lef and the OpenROAD config files to use the additional layers. diff --git a/flow/platforms/sky130hd_fakestack/cells_adders_hd.v b/flow/platforms/sky130hd_fakestack/cells_adders_hd.v deleted file mode 100644 index 736d0f0dde..0000000000 --- a/flow/platforms/sky130hd_fakestack/cells_adders_hd.v +++ /dev/null @@ -1,48 +0,0 @@ - -(* techmap_celltype = "$fa" *) -module _tech_fa (A, B, C, X, Y); - parameter WIDTH = 1; - (* force_downto *) - input [WIDTH-1 : 0] A, B, C; - (* force_downto *) - output [WIDTH-1 : 0] X, Y; - - parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx; - parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx; - parameter _TECHMAP_CONSTVAL_C_ = WIDTH'bx; - - genvar i; - generate for (i = 0; i < WIDTH; i = i + 1) begin - if (_TECHMAP_CONSTVAL_A_[i] === 1'b0 || _TECHMAP_CONSTVAL_B_[i] === 1'b0 || _TECHMAP_CONSTVAL_C_[i] === 1'b0) begin - if (_TECHMAP_CONSTVAL_C_[i] === 1'b0) begin - sky130_fd_sc_hd__ha_1 halfadder_Cconst ( - .A(A[i]), - .B(B[i]), - .COUT(X[i]), .SUM(Y[i]) - ); - end - else begin - if (_TECHMAP_CONSTVAL_B_[i] === 1'b0) begin - sky130_fd_sc_hd__ha_1 halfadder_Bconst ( - .A(A[i]), - .B(C[i]), - .COUT(X[i]), .SUM(Y[i]) - ); - end - else begin - sky130_fd_sc_hd__ha_1 halfadder_Aconst ( - .A(B[i]), - .B(C[i]), - .COUT(X[i]), .SUM(Y[i]) - ); - end - end - end - else begin - sky130_fd_sc_hd__fa_1 fulladder ( - .A(A[i]), .B(B[i]), .CIN(C[i]), .COUT(X[i]), .SUM(Y[i]) - ); - end - end endgenerate - -endmodule diff --git a/flow/platforms/sky130hd_fakestack/cells_clkgate_hd.v b/flow/platforms/sky130hd_fakestack/cells_clkgate_hd.v deleted file mode 100644 index 589abda4f7..0000000000 --- a/flow/platforms/sky130hd_fakestack/cells_clkgate_hd.v +++ /dev/null @@ -1,16 +0,0 @@ -module OPENROAD_CLKGATE (CK, E, GCK); - input CK; - input E; - output GCK; - -`ifdef OPENROAD_CLKGATE - -sky130_fd_sc_hd__dlclkp_1 latch (.CLK (CK), .GATE(E), .GCLK(GCK)); - -`else - -assign GCK = CK; - -`endif - -endmodule diff --git a/flow/platforms/sky130hd_fakestack/cells_latch_hd.v b/flow/platforms/sky130hd_fakestack/cells_latch_hd.v deleted file mode 100644 index 60a929d706..0000000000 --- a/flow/platforms/sky130hd_fakestack/cells_latch_hd.v +++ /dev/null @@ -1,15 +0,0 @@ -module $_DLATCH_P_(input E, input D, output Q); - sky130_fd_sc_hd__dlxtp_1 _TECHMAP_REPLACE_ ( - .D(D), - .GATE(E), - .Q(Q) - ); -endmodule - -module $_DLATCH_N_(input E, input D, output Q); - sky130_fd_sc_hd__dlxtn_1 _TECHMAP_REPLACE_ ( - .D(D), - .GATE_N(E), - .Q(Q) - ); -endmodule diff --git a/flow/platforms/sky130hd_fakestack/config.mk b/flow/platforms/sky130hd_fakestack/config.mk deleted file mode 100644 index 0fc23ebb85..0000000000 --- a/flow/platforms/sky130hd_fakestack/config.mk +++ /dev/null @@ -1,136 +0,0 @@ -# Process node -export PROCESS = 130 - -#----------------------------------------------------- -# Tech/Libs -# ---------------------------------------------------- -export TECH_LEF = $(PLATFORM_DIR)/lef/9M_li_2Ma_2Mb_2Mc_2Md_1Me.tlef -export SC_LEF = $(PLATFORM_DIR)/lef/sky130_fd_sc_hd_merged.lef - -export LIB_FILES = $(PLATFORM_DIR)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib \ - $(ADDITIONAL_LIBS) -export GDS_FILES = $(wildcard $(PLATFORM_DIR)/gds/*.gds) \ - $(ADDITIONAL_GDS_FILES) - -# Dont use cells to ease congestion -# Specify at least one filler cell if none - -# The *probe* are for inserting probe points and have metal shapes -# on all layers. -# *lpflow* cells are for multi-power domains -export DONT_USE_CELLS += \ - sky130_fd_sc_hd__probe_p_8 sky130_fd_sc_hd__probec_p_8 \ - sky130_fd_sc_hd__lpflow_bleeder_1 \ - sky130_fd_sc_hd__lpflow_clkbufkapwr_1 \ - sky130_fd_sc_hd__lpflow_clkbufkapwr_16 \ - sky130_fd_sc_hd__lpflow_clkbufkapwr_2 \ - sky130_fd_sc_hd__lpflow_clkbufkapwr_4 \ - sky130_fd_sc_hd__lpflow_clkbufkapwr_8 \ - sky130_fd_sc_hd__lpflow_clkinvkapwr_1 \ - sky130_fd_sc_hd__lpflow_clkinvkapwr_16 \ - sky130_fd_sc_hd__lpflow_clkinvkapwr_2 \ - sky130_fd_sc_hd__lpflow_clkinvkapwr_4 \ - sky130_fd_sc_hd__lpflow_clkinvkapwr_8 \ - sky130_fd_sc_hd__lpflow_decapkapwr_12 \ - sky130_fd_sc_hd__lpflow_decapkapwr_3 \ - sky130_fd_sc_hd__lpflow_decapkapwr_4 \ - sky130_fd_sc_hd__lpflow_decapkapwr_6 \ - sky130_fd_sc_hd__lpflow_decapkapwr_8 \ - sky130_fd_sc_hd__lpflow_inputiso0n_1 \ - sky130_fd_sc_hd__lpflow_inputiso0p_1 \ - sky130_fd_sc_hd__lpflow_inputiso1n_1 \ - sky130_fd_sc_hd__lpflow_inputiso1p_1 \ - sky130_fd_sc_hd__lpflow_inputisolatch_1 \ - sky130_fd_sc_hd__lpflow_isobufsrc_1 \ - sky130_fd_sc_hd__lpflow_isobufsrc_16 \ - sky130_fd_sc_hd__lpflow_isobufsrc_2 \ - sky130_fd_sc_hd__lpflow_isobufsrc_4 \ - sky130_fd_sc_hd__lpflow_isobufsrc_8 \ - sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 \ - sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 -# -# Define fill cells -export FILL_CELLS ?= sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8 - -# ----------------------------------------------------- -# Yosys -# ---------------------------------------------------- -# Set the TIEHI/TIELO cells -# These are used in yosys synthesis to avoid logical 1/0's in the netlist -export TIEHI_CELL_AND_PORT = sky130_fd_sc_hd__conb_1 HI -export TIELO_CELL_AND_PORT = sky130_fd_sc_hd__conb_1 LO - -# Used in synthesis -export MIN_BUF_CELL_AND_PORTS = sky130_fd_sc_hd__buf_4 A X - - -# Yosys mapping files -export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch_hd.v -export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate_hd.v -export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hd.v -# -# Define ABC driver and load -export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1 -export ABC_LOAD_IN_FF = 5 -#-------------------------------------------------------- -# Floorplan -# ------------------------------------------------------- - -# Placement site for core cells -# This can be found in the technology lef -export PLACE_SITE = unithd - -# IO Placer pin layers -export IO_PLACER_H = met3 -export IO_PLACER_V = met2 - -# Define default PDN config -export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl - -# Endcap and Welltie cells -export TAP_CELL_NAME = sky130_fd_sc_hd__tapvpwrvgnd_1 -export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl - -export MACRO_PLACE_HALO ?= 40 40 -export MACRO_PLACE_CHANNEL ?= 80 80 - -#--------------------------------------------------------- -# Place -# -------------------------------------------------------- -export PLACE_DENSITY ?= 0.60 - -# --------------------------------------------------------- -# Route -# --------------------------------------------------------- -# FastRoute options -export MIN_ROUTING_LAYER = met1 -export MAX_ROUTING_LAYER = met9 -# -# Define fastRoute tcl -export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl - -# KLayout technology file -export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/$(PLATFORM).lyt -# -# Rules for metal fill -export FILL_CONFIG = $(PLATFORM_DIR)/fill.json -# -# Template definition for power grid analysis -export TEMPLATE_PGA_CFG ?= $(PLATFORM_DIR)/template_pga.cfg - -# OpenRCX extRules -export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules -# --------------------------------------------------------- -# IR Drop -# --------------------------------------------------------- - -# IR drop estimation supply net name to be analyzed and supply voltage variable -# For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD 1.8" -export GND_NETS_VOLTAGES ?= "VSS 0.0" diff --git a/flow/platforms/sky130hd_fakestack/fill.json b/flow/platforms/sky130hd_fakestack/fill.json deleted file mode 100644 index 3efce0109b..0000000000 --- a/flow/platforms/sky130hd_fakestack/fill.json +++ /dev/null @@ -1,83 +0,0 @@ -{ - "layers" : { - "met1" : { - "layer": 36, - "name": "met1", - "dir": "H", - "datatype": 0, - "space_to_outline": 70, - "non-opc": { - "datatype": 0, - "width": [2.00, 1.00, 0.58, 0.3], - "height": [2.00, 1.00, 0.58, 0.3], - "space_to_fill": 0.3, - "space_to_non_fill": 3 - } - }, - - "met2" : { - "layer": 41, - "name": "met2", - "dir": "V", - "datatype": 0, - "space_to_outline": 70, - "non-opc": { - "datatype": 0, - "width": [2.00, 1.00, 0.58, 0.3], - "height": [2.00, 1.00, 0.58, 0.3], - "space_to_fill": 0.3, - "space_to_non_fill": 3 - } - }, - - "met3" : { - "layer": 34, - "name": "met3", - "dir": "H", - "datatype": 0, - "space_to_outline": 70, - "non-opc": { - "datatype": 0, - "width": [2.00, 1.00, 0.58, 0.4], - "height": [2.00, 1.00, 0.58, 0.4], - "space_to_fill": 0.3, - "space_to_non_fill": 3 - } - }, - - "met4" : { - "layer": 51, - "name": "met4", - "dir": "V", - "datatype": 0, - "space_to_outline": 70, - "non-opc": { - "datatype": 0, - "width": [2.00, 1.00, 0.58, 0.4], - "height": [2.00, 1.00, 0.58, 0.4], - "space_to_fill": 0.3, - "space_to_non_fill": 3.3 - } - }, - - "met5" : { - "layer": 59, - "name": "met5", - "dir": "H", - "datatype": 0, - "space_to_outline": 70, - "non-opc": { - "datatype": 0, - "width": [2.00, 1.00, 0.58, 0.4], - "height": [2.00, 1.00, 0.58, 0.4], - "space_to_fill": 0.3, - "space_to_non_fill": 3.3 - } - } - }, - "outline" : { - "layer": 237, - "datatype": 0 - } -} - diff --git a/flow/platforms/sky130hd_fakestack/gds/sky130_fd_sc_hd.gds b/flow/platforms/sky130hd_fakestack/gds/sky130_fd_sc_hd.gds deleted file mode 100644 index ceb2106cd0..0000000000 Binary files a/flow/platforms/sky130hd_fakestack/gds/sky130_fd_sc_hd.gds and /dev/null differ diff --git a/flow/platforms/sky130hd_fakestack/lef/9M_li_2Ma_2Mb_2Mc_2Md_1Me.tlef b/flow/platforms/sky130hd_fakestack/lef/9M_li_2Ma_2Mb_2Mc_2Md_1Me.tlef deleted file mode 100644 index 5be36e6a19..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/9M_li_2Ma_2Mb_2Mc_2Md_1Me.tlef +++ /dev/null @@ -1,1304 +0,0 @@ -VERSION 5.7 ; - -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; -USEMINSPACING OBS OFF ; - -UNITS - TIME NANOSECONDS 1 ; - CAPACITANCE PICOFARADS 1 ; - RESISTANCE OHMS 1 ; - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -PROPERTYDEFINITIONS - LAYER LEF58_TYPE STRING ; -END PROPERTYDEFINITIONS - -SITE unithd - SYMMETRY Y ; - CLASS CORE ; - SIZE 0.46 BY 2.72 ; -END unithd - -SITE unithddbl - SYMMETRY Y ; - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -LAYER nwell - TYPE MASTERSLICE ; - PROPERTY LEF58_TYPE "TYPE NWELL ;" ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; - PROPERTY LEF58_TYPE "TYPE PWELL ;" ; -END pwell - -LAYER Gate - TYPE MASTERSLICE ; -END Gate - -LAYER Active - TYPE MASTERSLICE ; -END Active - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.46 0.34 ; - OFFSET 0.23 0.17 ; - - WIDTH 0.17 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.17 ; - AREA 0.0561 ; - THICKNESS 0.1 ; - EDGECAPACITANCE 40.697E-6 ; - CAPACITANCE CPERSQDIST 36.9866E-6 ; - RESISTANCE RPERSQ 12.2 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ; -END li1 - -LAYER mcon - TYPE CUT ; - - WIDTH 0.17 ; - SPACING 0.19 ; - ENCLOSURE BELOW 0 0 ; - ENCLOSURE ABOVE 0.03 0.06 ; - - ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ; - DCCURRENTDENSITY AVERAGE 0.36 ; - -END mcon -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 0.34 ; - OFFSET 0.17 ; - - WIDTH 0.14 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.083 ; - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - EDGECAPACITANCE 40.567E-6 ; - CAPACITANCE CPERSQDIST 25.7784E-6 ; - DCCURRENTDENSITY AVERAGE 2.8 ; - ACCURRENTDENSITY RMS 6.1 ; - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; - - RESISTANCE RPERSQ 0.125 ; -END met1 -LAYER via - TYPE CUT ; - WIDTH 0.15 ; - SPACING 0.17 ; - ENCLOSURE BELOW 0.055 0.085 ; - ENCLOSURE ABOVE 0.055 0.085 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.29 ; -END via -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.34 ; - OFFSET 0.17 ; - - WIDTH 0.14 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.083 ; - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - EDGECAPACITANCE 40.567E-6 ; - CAPACITANCE CPERSQDIST 25.7784E-6 ; - DCCURRENTDENSITY AVERAGE 2.8 ; - ACCURRENTDENSITY RMS 6.1 ; - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; - - RESISTANCE RPERSQ 0.125 ; -END met2 -LAYER via2 - TYPE CUT ; - WIDTH 0.15 ; - SPACING 0.17 ; - ENCLOSURE BELOW 0.055 0.085 ; - ENCLOSURE ABOVE 0.055 0.085 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.29 ; -END via2 -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 0.46 ; - OFFSET 0.23 ; - - WIDTH 0.14 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.0676 ; - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - EDGECAPACITANCE 37.759E-6 ; - CAPACITANCE CPERSQDIST 16.9423E-6 ; - RESISTANCE RPERSQ 0.125 ; - DCCURRENTDENSITY AVERAGE 2.8 ; - ACCURRENTDENSITY RMS 6.1 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met3 -LAYER via3 - TYPE CUT ; - WIDTH 0.2 ; - SPACING 0.2 ; - ENCLOSURE BELOW 0.04 0.085 ; - ENCLOSURE ABOVE 0.065 0.065 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; -END via3 -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.46 ; - OFFSET 0.23 ; - - WIDTH 0.14 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.0676 ; - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - EDGECAPACITANCE 37.759E-6 ; - CAPACITANCE CPERSQDIST 16.9423E-6 ; - RESISTANCE RPERSQ 0.125 ; - DCCURRENTDENSITY AVERAGE 2.8 ; - ACCURRENTDENSITY RMS 6.1 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met4 -LAYER via4 - TYPE CUT ; - WIDTH 0.2 ; - SPACING 0.2 ; - ENCLOSURE BELOW 0.04 0.085 ; - ENCLOSURE ABOVE 0.065 0.065 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; -END via4 -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 0.68 ; - OFFSET 0.34 ; - - WIDTH 0.3 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; # Met3 6 - THICKNESS 0.8 ; - - EDGECAPACITANCE 40.989E-6 ; - CAPACITANCE CPERSQDIST 12.3729E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; - ACCURRENTDENSITY RMS 14.9 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met5 -LAYER via5 - TYPE CUT ; - WIDTH 0.2 ; - SPACING 0.2 ; - ENCLOSURE BELOW 0.06 0.09 ; - ENCLOSURE ABOVE 0.065 0.065 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; -END via5 -LAYER met6 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.68 ; - OFFSET 0.34 ; - - WIDTH 0.3 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; # Met3 6 - THICKNESS 0.8 ; - - EDGECAPACITANCE 40.989E-6 ; - CAPACITANCE CPERSQDIST 12.3729E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; - ACCURRENTDENSITY RMS 14.9 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met6 -LAYER via6 - TYPE CUT ; - WIDTH 0.2 ; - SPACING 0.2 ; - ENCLOSURE BELOW 0.06 0.09 ; - ENCLOSURE ABOVE 0.065 0.065 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; -END via6 -LAYER met7 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - - PITCH 0.92 ; - OFFSET 0.46 ; - - WIDTH 0.3 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; - - THICKNESS 0.8 ; - - EDGECAPACITANCE 36.676E-6 ; - CAPACITANCE CPERSQDIST 8.41537E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; - ACCURRENTDENSITY RMS 14.9 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met7 -LAYER via7 - TYPE CUT ; - WIDTH 0.8 ; - SPACING 0.8 ; - ENCLOSURE BELOW 0.19 0.19 ; - ENCLOSURE ABOVE 0.31 0.31 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 2.49 ; -END via7 -LAYER met8 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - - PITCH 0.92 ; - OFFSET 0.46 ; - - WIDTH 0.3 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; - - THICKNESS 0.8 ; - - EDGECAPACITANCE 36.676E-6 ; - CAPACITANCE CPERSQDIST 8.41537E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; - ACCURRENTDENSITY RMS 14.9 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met8 -LAYER via8 - TYPE CUT ; - WIDTH 0.8 ; - SPACING 0.8 ; - ENCLOSURE BELOW 0.19 0.19 ; - ENCLOSURE ABOVE 0.31 0.31 ; - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 2.49 ; -END via8 -LAYER met9 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - - PITCH 3.4 ; - OFFSET 1.7 ; - - WIDTH 1.6 ; - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 1.6 ; - AREA 4 ; - - THICKNESS 1.2 ; - - EDGECAPACITANCE 38.851E-6 ; - CAPACITANCE CPERSQDIST 6.32063E-6 ; - RESISTANCE RPERSQ 0.0285 ; - DCCURRENTDENSITY AVERAGE 10.17 ; - ACCURRENTDENSITY RMS 22.34 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; -END met9 -### Routing via cells section ### -# Plus via rule, metals are along the prefered direction -VIA L1M1_PR DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIARULE L1M1_PR GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.03 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR - -# Plus via rule, metals are along the non prefered direction -VIA L1M1_PR_R DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIARULE L1M1_PR_R GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.03 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA L1M1_PR_M DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIARULE L1M1_PR_M GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.03 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA L1M1_PR_MR DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIARULE L1M1_PR_MR GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.03 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_MR - -# Centered via rule, we really do not want to use it -VIA L1M1_PR_C DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIARULE L1M1_PR_C GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_C -# Plus via rule, metals are along the prefered direction -VIA M1M2_PR DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.160 -0.130 0.160 0.130 ; - LAYER met2 ; - RECT -0.130 -0.160 0.130 0.160 ; -END M1M2_PR - -VIARULE M1M2_PR GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.055 ; - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR - -# Plus via rule, metals are along the non prefered direction -VIA M1M2_PR_R DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.130 -0.160 0.130 0.160 ; - LAYER met2 ; - RECT -0.160 -0.130 0.160 0.130 ; -END M1M2_PR_R - -VIARULE M1M2_PR_R GENERATE - LAYER met1 ; - ENCLOSURE 0.055 0.085 ; - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M1M2_PR_M DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.160 -0.130 0.160 0.130 ; - LAYER met2 ; - RECT -0.160 -0.130 0.160 0.130 ; -END M1M2_PR_M - -VIARULE M1M2_PR_M GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.055 ; - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M1M2_PR_MR DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.130 -0.160 0.130 0.160 ; - LAYER met2 ; - RECT -0.130 -0.160 0.130 0.160 ; -END M1M2_PR_MR - -VIARULE M1M2_PR_MR GENERATE - LAYER met1 ; - ENCLOSURE 0.055 0.085 ; - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_MR - -# Centered via rule, we really do not want to use it -VIA M1M2_PR_C DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.160 -0.160 0.160 0.160 ; - LAYER met2 ; - RECT -0.160 -0.160 0.160 0.160 ; -END M1M2_PR_C - -VIARULE M1M2_PR_C GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.085 ; - LAYER met2 ; - ENCLOSURE 0.085 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_C -# Plus via rule, metals are along the prefered direction -VIA M2M3_PR DEFAULT - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.160 -0.130 0.160 0.130 ; - LAYER met3 ; - RECT -0.130 -0.160 0.130 0.160 ; -END M2M3_PR - -VIARULE M2M3_PR GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER met3 ; - ENCLOSURE 0.055 0.085 ; - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M2M3_PR - -# Plus via rule, metals are along the non prefered direction -VIA M2M3_PR_R DEFAULT - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.130 -0.160 0.130 0.160 ; - LAYER met3 ; - RECT -0.160 -0.130 0.160 0.130 ; -END M2M3_PR_R - -VIARULE M2M3_PR_R GENERATE - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER met3 ; - ENCLOSURE 0.085 0.055 ; - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M2M3_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M2M3_PR_M DEFAULT - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.160 -0.130 0.160 0.130 ; - LAYER met3 ; - RECT -0.160 -0.130 0.160 0.130 ; -END M2M3_PR_M - -VIARULE M2M3_PR_M GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER met3 ; - ENCLOSURE 0.085 0.055 ; - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M2M3_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M2M3_PR_MR DEFAULT - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.130 -0.160 0.130 0.160 ; - LAYER met3 ; - RECT -0.130 -0.160 0.130 0.160 ; -END M2M3_PR_MR - -VIARULE M2M3_PR_MR GENERATE - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER met3 ; - ENCLOSURE 0.055 0.085 ; - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M2M3_PR_MR - -# Centered via rule, we really do not want to use it -VIA M2M3_PR_C DEFAULT - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.160 -0.160 0.160 0.160 ; - LAYER met3 ; - RECT -0.160 -0.160 0.160 0.160 ; -END M2M3_PR_C - -VIARULE M2M3_PR_C GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.085 ; - LAYER met3 ; - ENCLOSURE 0.085 0.085 ; - LAYER via2 ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M2M3_PR_C -# Plus via rule, metals are along the prefered direction -VIA M3M4_PR DEFAULT - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met3 ; - RECT -0.185 -0.140 0.185 0.140 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIARULE M3M4_PR GENERATE - LAYER met3 ; - ENCLOSURE 0.085 0.04 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR - -# Plus via rule, metals are along the non prefered direction -VIA M3M4_PR_R DEFAULT - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met3 ; - RECT -0.140 -0.185 0.140 0.185 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIARULE M3M4_PR_R GENERATE - LAYER met3 ; - ENCLOSURE 0.04 0.085 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M3M4_PR_M DEFAULT - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met3 ; - RECT -0.185 -0.140 0.185 0.140 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIARULE M3M4_PR_M GENERATE - LAYER met3 ; - ENCLOSURE 0.085 0.04 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M3M4_PR_MR DEFAULT - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met3 ; - RECT -0.140 -0.185 0.140 0.185 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIARULE M3M4_PR_MR GENERATE - LAYER met3 ; - ENCLOSURE 0.04 0.085 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_MR - -# Centered via rule, we really do not want to use it -VIA M3M4_PR_C DEFAULT - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met3 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIARULE M3M4_PR_C GENERATE - LAYER met3 ; - ENCLOSURE 0.085 0.085 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_C -# Plus via rule, metals are along the prefered direction -VIA M4M5_PR DEFAULT - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met4 ; - RECT -0.185 -0.140 0.185 0.140 ; - LAYER met5 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M4M5_PR - -VIARULE M4M5_PR GENERATE - LAYER met4 ; - ENCLOSURE 0.085 0.04 ; - LAYER met5 ; - ENCLOSURE 0.065 0.065 ; - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M4M5_PR - -# Plus via rule, metals are along the non prefered direction -VIA M4M5_PR_R DEFAULT - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met4 ; - RECT -0.140 -0.185 0.140 0.185 ; - LAYER met5 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M4M5_PR_R - -VIARULE M4M5_PR_R GENERATE - LAYER met4 ; - ENCLOSURE 0.04 0.085 ; - LAYER met5 ; - ENCLOSURE 0.065 0.065 ; - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M4M5_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M4M5_PR_M DEFAULT - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met4 ; - RECT -0.185 -0.140 0.185 0.140 ; - LAYER met5 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M4M5_PR_M - -VIARULE M4M5_PR_M GENERATE - LAYER met4 ; - ENCLOSURE 0.085 0.04 ; - LAYER met5 ; - ENCLOSURE 0.065 0.065 ; - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M4M5_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M4M5_PR_MR DEFAULT - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met4 ; - RECT -0.140 -0.185 0.140 0.185 ; - LAYER met5 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M4M5_PR_MR - -VIARULE M4M5_PR_MR GENERATE - LAYER met4 ; - ENCLOSURE 0.04 0.085 ; - LAYER met5 ; - ENCLOSURE 0.065 0.065 ; - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M4M5_PR_MR - -# Centered via rule, we really do not want to use it -VIA M4M5_PR_C DEFAULT - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met4 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER met5 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M4M5_PR_C - -VIARULE M4M5_PR_C GENERATE - LAYER met4 ; - ENCLOSURE 0.085 0.085 ; - LAYER met5 ; - ENCLOSURE 0.065 0.065 ; - LAYER via4 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M4M5_PR_C -# Plus via rule, metals are along the prefered direction -VIA M5M6_PR DEFAULT - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met5 ; - RECT -0.190 -0.160 0.190 0.160 ; - LAYER met6 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M5M6_PR - -VIARULE M5M6_PR GENERATE - LAYER met5 ; - ENCLOSURE 0.09 0.06 ; - LAYER met6 ; - ENCLOSURE 0.065 0.065 ; - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M5M6_PR - -# Plus via rule, metals are along the non prefered direction -VIA M5M6_PR_R DEFAULT - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met5 ; - RECT -0.160 -0.190 0.160 0.190 ; - LAYER met6 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M5M6_PR_R - -VIARULE M5M6_PR_R GENERATE - LAYER met5 ; - ENCLOSURE 0.06 0.09 ; - LAYER met6 ; - ENCLOSURE 0.065 0.065 ; - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M5M6_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M5M6_PR_M DEFAULT - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met5 ; - RECT -0.190 -0.160 0.190 0.160 ; - LAYER met6 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M5M6_PR_M - -VIARULE M5M6_PR_M GENERATE - LAYER met5 ; - ENCLOSURE 0.09 0.06 ; - LAYER met6 ; - ENCLOSURE 0.065 0.065 ; - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M5M6_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M5M6_PR_MR DEFAULT - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met5 ; - RECT -0.160 -0.190 0.160 0.190 ; - LAYER met6 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M5M6_PR_MR - -VIARULE M5M6_PR_MR GENERATE - LAYER met5 ; - ENCLOSURE 0.06 0.09 ; - LAYER met6 ; - ENCLOSURE 0.065 0.065 ; - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M5M6_PR_MR - -# Centered via rule, we really do not want to use it -VIA M5M6_PR_C DEFAULT - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met5 ; - RECT -0.190 -0.190 0.190 0.190 ; - LAYER met6 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M5M6_PR_C - -VIARULE M5M6_PR_C GENERATE - LAYER met5 ; - ENCLOSURE 0.09 0.09 ; - LAYER met6 ; - ENCLOSURE 0.065 0.065 ; - LAYER via5 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M5M6_PR_C -# Plus via rule, metals are along the prefered direction -VIA M6M7_PR DEFAULT - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met6 ; - RECT -0.190 -0.160 0.190 0.160 ; - LAYER met7 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M6M7_PR - -VIARULE M6M7_PR GENERATE - LAYER met6 ; - ENCLOSURE 0.09 0.06 ; - LAYER met7 ; - ENCLOSURE 0.065 0.065 ; - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M6M7_PR - -# Plus via rule, metals are along the non prefered direction -VIA M6M7_PR_R DEFAULT - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met6 ; - RECT -0.160 -0.190 0.160 0.190 ; - LAYER met7 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M6M7_PR_R - -VIARULE M6M7_PR_R GENERATE - LAYER met6 ; - ENCLOSURE 0.06 0.09 ; - LAYER met7 ; - ENCLOSURE 0.065 0.065 ; - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M6M7_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M6M7_PR_M DEFAULT - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met6 ; - RECT -0.190 -0.160 0.190 0.160 ; - LAYER met7 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M6M7_PR_M - -VIARULE M6M7_PR_M GENERATE - LAYER met6 ; - ENCLOSURE 0.09 0.06 ; - LAYER met7 ; - ENCLOSURE 0.065 0.065 ; - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M6M7_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M6M7_PR_MR DEFAULT - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met6 ; - RECT -0.160 -0.190 0.160 0.190 ; - LAYER met7 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M6M7_PR_MR - -VIARULE M6M7_PR_MR GENERATE - LAYER met6 ; - ENCLOSURE 0.06 0.09 ; - LAYER met7 ; - ENCLOSURE 0.065 0.065 ; - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M6M7_PR_MR - -# Centered via rule, we really do not want to use it -VIA M6M7_PR_C DEFAULT - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - LAYER met6 ; - RECT -0.190 -0.190 0.190 0.190 ; - LAYER met7 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M6M7_PR_C - -VIARULE M6M7_PR_C GENERATE - LAYER met6 ; - ENCLOSURE 0.09 0.09 ; - LAYER met7 ; - ENCLOSURE 0.065 0.065 ; - LAYER via6 ; - RECT -0.100 -0.100 0.100 0.100 ; - SPACING 0.4 BY 0.4 ; -END M6M7_PR_C -# Plus via rule, metals are along the prefered direction -VIA M7M8_PR DEFAULT - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met7 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met8 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M7M8_PR - -VIARULE M7M8_PR GENERATE - LAYER met7 ; - ENCLOSURE 0.19 0.19 ; - LAYER met8 ; - ENCLOSURE 0.31 0.31 ; - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M7M8_PR - -# Plus via rule, metals are along the non prefered direction -VIA M7M8_PR_R DEFAULT - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met7 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met8 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M7M8_PR_R - -VIARULE M7M8_PR_R GENERATE - LAYER met7 ; - ENCLOSURE 0.19 0.19 ; - LAYER met8 ; - ENCLOSURE 0.31 0.31 ; - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M7M8_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M7M8_PR_M DEFAULT - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met7 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met8 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M7M8_PR_M - -VIARULE M7M8_PR_M GENERATE - LAYER met7 ; - ENCLOSURE 0.19 0.19 ; - LAYER met8 ; - ENCLOSURE 0.31 0.31 ; - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M7M8_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M7M8_PR_MR DEFAULT - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met7 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met8 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M7M8_PR_MR - -VIARULE M7M8_PR_MR GENERATE - LAYER met7 ; - ENCLOSURE 0.19 0.19 ; - LAYER met8 ; - ENCLOSURE 0.31 0.31 ; - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M7M8_PR_MR - -# Centered via rule, we really do not want to use it -VIA M7M8_PR_C DEFAULT - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met7 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met8 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M7M8_PR_C - -VIARULE M7M8_PR_C GENERATE - LAYER met7 ; - ENCLOSURE 0.19 0.19 ; - LAYER met8 ; - ENCLOSURE 0.31 0.31 ; - LAYER via7 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M7M8_PR_C -# Plus via rule, metals are along the prefered direction -VIA M8M9_PR DEFAULT - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met8 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met9 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M8M9_PR - -VIARULE M8M9_PR GENERATE - LAYER met8 ; - ENCLOSURE 0.19 0.19 ; - LAYER met9 ; - ENCLOSURE 0.31 0.31 ; - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M8M9_PR - -# Plus via rule, metals are along the non prefered direction -VIA M8M9_PR_R DEFAULT - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met8 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met9 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M8M9_PR_R - -VIARULE M8M9_PR_R GENERATE - LAYER met8 ; - ENCLOSURE 0.19 0.19 ; - LAYER met9 ; - ENCLOSURE 0.31 0.31 ; - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M8M9_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M8M9_PR_M DEFAULT - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met8 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met9 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M8M9_PR_M - -VIARULE M8M9_PR_M GENERATE - LAYER met8 ; - ENCLOSURE 0.19 0.19 ; - LAYER met9 ; - ENCLOSURE 0.31 0.31 ; - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M8M9_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M8M9_PR_MR DEFAULT - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met8 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met9 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M8M9_PR_MR - -VIARULE M8M9_PR_MR GENERATE - LAYER met8 ; - ENCLOSURE 0.19 0.19 ; - LAYER met9 ; - ENCLOSURE 0.31 0.31 ; - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M8M9_PR_MR - -# Centered via rule, we really do not want to use it -VIA M8M9_PR_C DEFAULT - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - LAYER met8 ; - RECT -0.590 -0.590 0.590 0.590 ; - LAYER met9 ; - RECT -0.710 -0.710 0.710 0.710 ; -END M8M9_PR_C - -VIARULE M8M9_PR_C GENERATE - LAYER met8 ; - ENCLOSURE 0.19 0.19 ; - LAYER met9 ; - ENCLOSURE 0.31 0.31 ; - LAYER via8 ; - RECT -0.400 -0.400 0.400 0.400 ; - SPACING 1.6 BY 1.6 ; -END M8M9_PR_C -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x16.lef b/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x16.lef deleted file mode 100644 index d3485f6c42..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x16.lef +++ /dev/null @@ -1,779 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram130_256x16 - FOREIGN fakeram130_256x16 0 0 ; - SYMMETRY X Y ; - SIZE 285.660 BY 187.680 ; - CLASS BLOCK ; - PIN w_mask_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.370 0.460 4.830 ; - END - END w_mask_in[0] - PIN w_mask_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.130 0.460 7.590 ; - END - END w_mask_in[1] - PIN w_mask_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.890 0.460 10.350 ; - END - END w_mask_in[2] - PIN w_mask_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.650 0.460 13.110 ; - END - END w_mask_in[3] - PIN w_mask_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.410 0.460 15.870 ; - END - END w_mask_in[4] - PIN w_mask_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.170 0.460 18.630 ; - END - END w_mask_in[5] - PIN w_mask_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.930 0.460 21.390 ; - END - END w_mask_in[6] - PIN w_mask_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.690 0.460 24.150 ; - END - END w_mask_in[7] - PIN w_mask_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.450 0.460 26.910 ; - END - END w_mask_in[8] - PIN w_mask_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.210 0.460 29.670 ; - END - END w_mask_in[9] - PIN w_mask_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.970 0.460 32.430 ; - END - END w_mask_in[10] - PIN w_mask_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 34.730 0.460 35.190 ; - END - END w_mask_in[11] - PIN w_mask_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.490 0.460 37.950 ; - END - END w_mask_in[12] - PIN w_mask_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 40.250 0.460 40.710 ; - END - END w_mask_in[13] - PIN w_mask_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.010 0.460 43.470 ; - END - END w_mask_in[14] - PIN w_mask_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 45.770 0.460 46.230 ; - END - END w_mask_in[15] - PIN rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.450 0.460 49.910 ; - END - END rd_out[0] - PIN rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.210 0.460 52.670 ; - END - END rd_out[1] - PIN rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.970 0.460 55.430 ; - END - END rd_out[2] - PIN rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.730 0.460 58.190 ; - END - END rd_out[3] - PIN rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.490 0.460 60.950 ; - END - END rd_out[4] - PIN rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 63.250 0.460 63.710 ; - END - END rd_out[5] - PIN rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.010 0.460 66.470 ; - END - END rd_out[6] - PIN rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 68.770 0.460 69.230 ; - END - END rd_out[7] - PIN rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.530 0.460 71.990 ; - END - END rd_out[8] - PIN rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.290 0.460 74.750 ; - END - END rd_out[9] - PIN rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.050 0.460 77.510 ; - END - END rd_out[10] - PIN rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 79.810 0.460 80.270 ; - END - END rd_out[11] - PIN rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 82.570 0.460 83.030 ; - END - END rd_out[12] - PIN rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 85.330 0.460 85.790 ; - END - END rd_out[13] - PIN rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 88.090 0.460 88.550 ; - END - END rd_out[14] - PIN rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 90.850 0.460 91.310 ; - END - END rd_out[15] - PIN wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.530 0.460 94.990 ; - END - END wd_in[0] - PIN wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.290 0.460 97.750 ; - END - END wd_in[1] - PIN wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.050 0.460 100.510 ; - END - END wd_in[2] - PIN wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.810 0.460 103.270 ; - END - END wd_in[3] - PIN wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.570 0.460 106.030 ; - END - END wd_in[4] - PIN wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.330 0.460 108.790 ; - END - END wd_in[5] - PIN wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.090 0.460 111.550 ; - END - END wd_in[6] - PIN wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.850 0.460 114.310 ; - END - END wd_in[7] - PIN wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.610 0.460 117.070 ; - END - END wd_in[8] - PIN wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.370 0.460 119.830 ; - END - END wd_in[9] - PIN wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 122.130 0.460 122.590 ; - END - END wd_in[10] - PIN wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 124.890 0.460 125.350 ; - END - END wd_in[11] - PIN wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 127.650 0.460 128.110 ; - END - END wd_in[12] - PIN wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 130.410 0.460 130.870 ; - END - END wd_in[13] - PIN wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 133.170 0.460 133.630 ; - END - END wd_in[14] - PIN wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.930 0.460 136.390 ; - END - END wd_in[15] - PIN addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 139.610 0.460 140.070 ; - END - END addr_in[0] - PIN addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 142.370 0.460 142.830 ; - END - END addr_in[1] - PIN addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 145.130 0.460 145.590 ; - END - END addr_in[2] - PIN addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 147.890 0.460 148.350 ; - END - END addr_in[3] - PIN addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 150.650 0.460 151.110 ; - END - END addr_in[4] - PIN addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 153.410 0.460 153.870 ; - END - END addr_in[5] - PIN addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 156.170 0.460 156.630 ; - END - END addr_in[6] - PIN addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.930 0.460 159.390 ; - END - END addr_in[7] - PIN we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 162.610 0.460 163.070 ; - END - END we_in - PIN ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 165.370 0.460 165.830 ; - END - END ce_in - PIN clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 168.130 0.460 168.590 ; - END - END clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 3.680 4.600 5.520 183.080 ; - RECT 11.040 4.600 12.880 183.080 ; - RECT 18.400 4.600 20.240 183.080 ; - RECT 25.760 4.600 27.600 183.080 ; - RECT 33.120 4.600 34.960 183.080 ; - RECT 40.480 4.600 42.320 183.080 ; - RECT 47.840 4.600 49.680 183.080 ; - RECT 55.200 4.600 57.040 183.080 ; - RECT 62.560 4.600 64.400 183.080 ; - RECT 69.920 4.600 71.760 183.080 ; - RECT 77.280 4.600 79.120 183.080 ; - RECT 84.640 4.600 86.480 183.080 ; - RECT 92.000 4.600 93.840 183.080 ; - RECT 99.360 4.600 101.200 183.080 ; - RECT 106.720 4.600 108.560 183.080 ; - RECT 114.080 4.600 115.920 183.080 ; - RECT 121.440 4.600 123.280 183.080 ; - RECT 128.800 4.600 130.640 183.080 ; - RECT 136.160 4.600 138.000 183.080 ; - RECT 143.520 4.600 145.360 183.080 ; - RECT 150.880 4.600 152.720 183.080 ; - RECT 158.240 4.600 160.080 183.080 ; - RECT 165.600 4.600 167.440 183.080 ; - RECT 172.960 4.600 174.800 183.080 ; - RECT 180.320 4.600 182.160 183.080 ; - RECT 187.680 4.600 189.520 183.080 ; - RECT 195.040 4.600 196.880 183.080 ; - RECT 202.400 4.600 204.240 183.080 ; - RECT 209.760 4.600 211.600 183.080 ; - RECT 217.120 4.600 218.960 183.080 ; - RECT 224.480 4.600 226.320 183.080 ; - RECT 231.840 4.600 233.680 183.080 ; - RECT 239.200 4.600 241.040 183.080 ; - RECT 246.560 4.600 248.400 183.080 ; - RECT 253.920 4.600 255.760 183.080 ; - RECT 261.280 4.600 263.120 183.080 ; - RECT 268.640 4.600 270.480 183.080 ; - RECT 276.000 4.600 277.840 183.080 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 7.360 4.600 9.200 183.080 ; - RECT 14.720 4.600 16.560 183.080 ; - RECT 22.080 4.600 23.920 183.080 ; - RECT 29.440 4.600 31.280 183.080 ; - RECT 36.800 4.600 38.640 183.080 ; - RECT 44.160 4.600 46.000 183.080 ; - RECT 51.520 4.600 53.360 183.080 ; - RECT 58.880 4.600 60.720 183.080 ; - RECT 66.240 4.600 68.080 183.080 ; - RECT 73.600 4.600 75.440 183.080 ; - RECT 80.960 4.600 82.800 183.080 ; - RECT 88.320 4.600 90.160 183.080 ; - RECT 95.680 4.600 97.520 183.080 ; - RECT 103.040 4.600 104.880 183.080 ; - RECT 110.400 4.600 112.240 183.080 ; - RECT 117.760 4.600 119.600 183.080 ; - RECT 125.120 4.600 126.960 183.080 ; - RECT 132.480 4.600 134.320 183.080 ; - RECT 139.840 4.600 141.680 183.080 ; - RECT 147.200 4.600 149.040 183.080 ; - RECT 154.560 4.600 156.400 183.080 ; - RECT 161.920 4.600 163.760 183.080 ; - RECT 169.280 4.600 171.120 183.080 ; - RECT 176.640 4.600 178.480 183.080 ; - RECT 184.000 4.600 185.840 183.080 ; - RECT 191.360 4.600 193.200 183.080 ; - RECT 198.720 4.600 200.560 183.080 ; - RECT 206.080 4.600 207.920 183.080 ; - RECT 213.440 4.600 215.280 183.080 ; - RECT 220.800 4.600 222.640 183.080 ; - RECT 228.160 4.600 230.000 183.080 ; - RECT 235.520 4.600 237.360 183.080 ; - RECT 242.880 4.600 244.720 183.080 ; - RECT 250.240 4.600 252.080 183.080 ; - RECT 257.600 4.600 259.440 183.080 ; - RECT 264.960 4.600 266.800 183.080 ; - RECT 272.320 4.600 274.160 183.080 ; - RECT 279.680 4.600 281.520 183.080 ; - END - END VDD - OBS - LAYER met1 ; - RECT 0 0 285.660 187.680 ; - LAYER met2 ; - RECT 0 0 285.660 187.680 ; - LAYER met3 ; - RECT 0.460 0 285.660 187.680 ; - RECT 0 0.000 0.460 4.370 ; - RECT 0 4.830 0.460 7.130 ; - RECT 0 7.590 0.460 9.890 ; - RECT 0 10.350 0.460 12.650 ; - RECT 0 13.110 0.460 15.410 ; - RECT 0 15.870 0.460 18.170 ; - RECT 0 18.630 0.460 20.930 ; - RECT 0 21.390 0.460 23.690 ; - RECT 0 24.150 0.460 26.450 ; - RECT 0 26.910 0.460 29.210 ; - RECT 0 29.670 0.460 31.970 ; - RECT 0 32.430 0.460 34.730 ; - RECT 0 35.190 0.460 37.490 ; - RECT 0 37.950 0.460 40.250 ; - RECT 0 40.710 0.460 43.010 ; - RECT 0 43.470 0.460 45.770 ; - RECT 0 46.230 0.460 49.450 ; - RECT 0 49.910 0.460 52.210 ; - RECT 0 52.670 0.460 54.970 ; - RECT 0 55.430 0.460 57.730 ; - RECT 0 58.190 0.460 60.490 ; - RECT 0 60.950 0.460 63.250 ; - RECT 0 63.710 0.460 66.010 ; - RECT 0 66.470 0.460 68.770 ; - RECT 0 69.230 0.460 71.530 ; - RECT 0 71.990 0.460 74.290 ; - RECT 0 74.750 0.460 77.050 ; - RECT 0 77.510 0.460 79.810 ; - RECT 0 80.270 0.460 82.570 ; - RECT 0 83.030 0.460 85.330 ; - RECT 0 85.790 0.460 88.090 ; - RECT 0 88.550 0.460 90.850 ; - RECT 0 91.310 0.460 94.530 ; - RECT 0 94.990 0.460 97.290 ; - RECT 0 97.750 0.460 100.050 ; - RECT 0 100.510 0.460 102.810 ; - RECT 0 103.270 0.460 105.570 ; - RECT 0 106.030 0.460 108.330 ; - RECT 0 108.790 0.460 111.090 ; - RECT 0 111.550 0.460 113.850 ; - RECT 0 114.310 0.460 116.610 ; - RECT 0 117.070 0.460 119.370 ; - RECT 0 119.830 0.460 122.130 ; - RECT 0 122.590 0.460 124.890 ; - RECT 0 125.350 0.460 127.650 ; - RECT 0 128.110 0.460 130.410 ; - RECT 0 130.870 0.460 133.170 ; - RECT 0 133.630 0.460 135.930 ; - RECT 0 136.390 0.460 139.610 ; - RECT 0 140.070 0.460 142.370 ; - RECT 0 142.830 0.460 145.130 ; - RECT 0 145.590 0.460 147.890 ; - RECT 0 148.350 0.460 150.650 ; - RECT 0 151.110 0.460 153.410 ; - RECT 0 153.870 0.460 156.170 ; - RECT 0 156.630 0.460 158.930 ; - RECT 0 159.390 0.460 162.610 ; - RECT 0 163.070 0.460 165.370 ; - RECT 0 165.830 0.460 168.130 ; - RECT 0 168.590 0.460 187.680 ; - LAYER met4 ; - RECT 0 0 285.660 4.600 ; - RECT 0 183.080 285.660 187.680 ; - RECT 0.000 4.600 3.680 183.080 ; - RECT 5.520 4.600 7.360 183.080 ; - RECT 9.200 4.600 11.040 183.080 ; - RECT 12.880 4.600 14.720 183.080 ; - RECT 16.560 4.600 18.400 183.080 ; - RECT 20.240 4.600 22.080 183.080 ; - RECT 23.920 4.600 25.760 183.080 ; - RECT 27.600 4.600 29.440 183.080 ; - RECT 31.280 4.600 33.120 183.080 ; - RECT 34.960 4.600 36.800 183.080 ; - RECT 38.640 4.600 40.480 183.080 ; - RECT 42.320 4.600 44.160 183.080 ; - RECT 46.000 4.600 47.840 183.080 ; - RECT 49.680 4.600 51.520 183.080 ; - RECT 53.360 4.600 55.200 183.080 ; - RECT 57.040 4.600 58.880 183.080 ; - RECT 60.720 4.600 62.560 183.080 ; - RECT 64.400 4.600 66.240 183.080 ; - RECT 68.080 4.600 69.920 183.080 ; - RECT 71.760 4.600 73.600 183.080 ; - RECT 75.440 4.600 77.280 183.080 ; - RECT 79.120 4.600 80.960 183.080 ; - RECT 82.800 4.600 84.640 183.080 ; - RECT 86.480 4.600 88.320 183.080 ; - RECT 90.160 4.600 92.000 183.080 ; - RECT 93.840 4.600 95.680 183.080 ; - RECT 97.520 4.600 99.360 183.080 ; - RECT 101.200 4.600 103.040 183.080 ; - RECT 104.880 4.600 106.720 183.080 ; - RECT 108.560 4.600 110.400 183.080 ; - RECT 112.240 4.600 114.080 183.080 ; - RECT 115.920 4.600 117.760 183.080 ; - RECT 119.600 4.600 121.440 183.080 ; - RECT 123.280 4.600 125.120 183.080 ; - RECT 126.960 4.600 128.800 183.080 ; - RECT 130.640 4.600 132.480 183.080 ; - RECT 134.320 4.600 136.160 183.080 ; - RECT 138.000 4.600 139.840 183.080 ; - RECT 141.680 4.600 143.520 183.080 ; - RECT 145.360 4.600 147.200 183.080 ; - RECT 149.040 4.600 150.880 183.080 ; - RECT 152.720 4.600 154.560 183.080 ; - RECT 156.400 4.600 158.240 183.080 ; - RECT 160.080 4.600 161.920 183.080 ; - RECT 163.760 4.600 165.600 183.080 ; - RECT 167.440 4.600 169.280 183.080 ; - RECT 171.120 4.600 172.960 183.080 ; - RECT 174.800 4.600 176.640 183.080 ; - RECT 178.480 4.600 180.320 183.080 ; - RECT 182.160 4.600 184.000 183.080 ; - RECT 185.840 4.600 187.680 183.080 ; - RECT 189.520 4.600 191.360 183.080 ; - RECT 193.200 4.600 195.040 183.080 ; - RECT 196.880 4.600 198.720 183.080 ; - RECT 200.560 4.600 202.400 183.080 ; - RECT 204.240 4.600 206.080 183.080 ; - RECT 207.920 4.600 209.760 183.080 ; - RECT 211.600 4.600 213.440 183.080 ; - RECT 215.280 4.600 217.120 183.080 ; - RECT 218.960 4.600 220.800 183.080 ; - RECT 222.640 4.600 224.480 183.080 ; - RECT 226.320 4.600 228.160 183.080 ; - RECT 230.000 4.600 231.840 183.080 ; - RECT 233.680 4.600 235.520 183.080 ; - RECT 237.360 4.600 239.200 183.080 ; - RECT 241.040 4.600 242.880 183.080 ; - RECT 244.720 4.600 246.560 183.080 ; - RECT 248.400 4.600 250.240 183.080 ; - RECT 252.080 4.600 253.920 183.080 ; - RECT 255.760 4.600 257.600 183.080 ; - RECT 259.440 4.600 261.280 183.080 ; - RECT 263.120 4.600 264.960 183.080 ; - RECT 266.800 4.600 268.640 183.080 ; - RECT 270.480 4.600 272.320 183.080 ; - RECT 274.160 4.600 276.000 183.080 ; - RECT 277.840 4.600 279.680 183.080 ; - RECT 281.520 4.600 285.660 183.080 ; - END -END fakeram130_256x16 - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x32.lef b/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x32.lef deleted file mode 100644 index 24a0a4c751..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x32.lef +++ /dev/null @@ -1,1263 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram130_256x32 - FOREIGN fakeram130_256x32 0 0 ; - SYMMETRY X Y ; - SIZE 293.940 BY 349.520 ; - CLASS BLOCK ; - PIN w_mask_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.370 0.460 4.830 ; - END - END w_mask_in[0] - PIN w_mask_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.130 0.460 7.590 ; - END - END w_mask_in[1] - PIN w_mask_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.890 0.460 10.350 ; - END - END w_mask_in[2] - PIN w_mask_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.650 0.460 13.110 ; - END - END w_mask_in[3] - PIN w_mask_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.410 0.460 15.870 ; - END - END w_mask_in[4] - PIN w_mask_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.170 0.460 18.630 ; - END - END w_mask_in[5] - PIN w_mask_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.930 0.460 21.390 ; - END - END w_mask_in[6] - PIN w_mask_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.690 0.460 24.150 ; - END - END w_mask_in[7] - PIN w_mask_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.450 0.460 26.910 ; - END - END w_mask_in[8] - PIN w_mask_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.210 0.460 29.670 ; - END - END w_mask_in[9] - PIN w_mask_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.970 0.460 32.430 ; - END - END w_mask_in[10] - PIN w_mask_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 34.730 0.460 35.190 ; - END - END w_mask_in[11] - PIN w_mask_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.490 0.460 37.950 ; - END - END w_mask_in[12] - PIN w_mask_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 40.250 0.460 40.710 ; - END - END w_mask_in[13] - PIN w_mask_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.010 0.460 43.470 ; - END - END w_mask_in[14] - PIN w_mask_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 45.770 0.460 46.230 ; - END - END w_mask_in[15] - PIN w_mask_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.530 0.460 48.990 ; - END - END w_mask_in[16] - PIN w_mask_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.290 0.460 51.750 ; - END - END w_mask_in[17] - PIN w_mask_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.050 0.460 54.510 ; - END - END w_mask_in[18] - PIN w_mask_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.810 0.460 57.270 ; - END - END w_mask_in[19] - PIN w_mask_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.570 0.460 60.030 ; - END - END w_mask_in[20] - PIN w_mask_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.330 0.460 62.790 ; - END - END w_mask_in[21] - PIN w_mask_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 65.090 0.460 65.550 ; - END - END w_mask_in[22] - PIN w_mask_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 67.850 0.460 68.310 ; - END - END w_mask_in[23] - PIN w_mask_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 70.610 0.460 71.070 ; - END - END w_mask_in[24] - PIN w_mask_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.370 0.460 73.830 ; - END - END w_mask_in[25] - PIN w_mask_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.130 0.460 76.590 ; - END - END w_mask_in[26] - PIN w_mask_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 78.890 0.460 79.350 ; - END - END w_mask_in[27] - PIN w_mask_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 81.650 0.460 82.110 ; - END - END w_mask_in[28] - PIN w_mask_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 84.410 0.460 84.870 ; - END - END w_mask_in[29] - PIN w_mask_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 87.170 0.460 87.630 ; - END - END w_mask_in[30] - PIN w_mask_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.930 0.460 90.390 ; - END - END w_mask_in[31] - PIN rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.970 0.460 101.430 ; - END - END rd_out[0] - PIN rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.730 0.460 104.190 ; - END - END rd_out[1] - PIN rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.490 0.460 106.950 ; - END - END rd_out[2] - PIN rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.250 0.460 109.710 ; - END - END rd_out[3] - PIN rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.010 0.460 112.470 ; - END - END rd_out[4] - PIN rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.770 0.460 115.230 ; - END - END rd_out[5] - PIN rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.530 0.460 117.990 ; - END - END rd_out[6] - PIN rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 120.290 0.460 120.750 ; - END - END rd_out[7] - PIN rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.050 0.460 123.510 ; - END - END rd_out[8] - PIN rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 125.810 0.460 126.270 ; - END - END rd_out[9] - PIN rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 128.570 0.460 129.030 ; - END - END rd_out[10] - PIN rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 131.330 0.460 131.790 ; - END - END rd_out[11] - PIN rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 134.090 0.460 134.550 ; - END - END rd_out[12] - PIN rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 136.850 0.460 137.310 ; - END - END rd_out[13] - PIN rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 139.610 0.460 140.070 ; - END - END rd_out[14] - PIN rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 142.370 0.460 142.830 ; - END - END rd_out[15] - PIN rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 145.130 0.460 145.590 ; - END - END rd_out[16] - PIN rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 147.890 0.460 148.350 ; - END - END rd_out[17] - PIN rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 150.650 0.460 151.110 ; - END - END rd_out[18] - PIN rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 153.410 0.460 153.870 ; - END - END rd_out[19] - PIN rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 156.170 0.460 156.630 ; - END - END rd_out[20] - PIN rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.930 0.460 159.390 ; - END - END rd_out[21] - PIN rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 161.690 0.460 162.150 ; - END - END rd_out[22] - PIN rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 164.450 0.460 164.910 ; - END - END rd_out[23] - PIN rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 167.210 0.460 167.670 ; - END - END rd_out[24] - PIN rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.970 0.460 170.430 ; - END - END rd_out[25] - PIN rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 172.730 0.460 173.190 ; - END - END rd_out[26] - PIN rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 175.490 0.460 175.950 ; - END - END rd_out[27] - PIN rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 178.250 0.460 178.710 ; - END - END rd_out[28] - PIN rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.010 0.460 181.470 ; - END - END rd_out[29] - PIN rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 183.770 0.460 184.230 ; - END - END rd_out[30] - PIN rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 186.530 0.460 186.990 ; - END - END rd_out[31] - PIN wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 197.570 0.460 198.030 ; - END - END wd_in[0] - PIN wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 200.330 0.460 200.790 ; - END - END wd_in[1] - PIN wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 203.090 0.460 203.550 ; - END - END wd_in[2] - PIN wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 205.850 0.460 206.310 ; - END - END wd_in[3] - PIN wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 208.610 0.460 209.070 ; - END - END wd_in[4] - PIN wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 211.370 0.460 211.830 ; - END - END wd_in[5] - PIN wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 214.130 0.460 214.590 ; - END - END wd_in[6] - PIN wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 216.890 0.460 217.350 ; - END - END wd_in[7] - PIN wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 219.650 0.460 220.110 ; - END - END wd_in[8] - PIN wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 222.410 0.460 222.870 ; - END - END wd_in[9] - PIN wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 225.170 0.460 225.630 ; - END - END wd_in[10] - PIN wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 227.930 0.460 228.390 ; - END - END wd_in[11] - PIN wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 230.690 0.460 231.150 ; - END - END wd_in[12] - PIN wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 233.450 0.460 233.910 ; - END - END wd_in[13] - PIN wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 236.210 0.460 236.670 ; - END - END wd_in[14] - PIN wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 238.970 0.460 239.430 ; - END - END wd_in[15] - PIN wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 241.730 0.460 242.190 ; - END - END wd_in[16] - PIN wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 244.490 0.460 244.950 ; - END - END wd_in[17] - PIN wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 247.250 0.460 247.710 ; - END - END wd_in[18] - PIN wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 250.010 0.460 250.470 ; - END - END wd_in[19] - PIN wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 252.770 0.460 253.230 ; - END - END wd_in[20] - PIN wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 255.530 0.460 255.990 ; - END - END wd_in[21] - PIN wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 258.290 0.460 258.750 ; - END - END wd_in[22] - PIN wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 261.050 0.460 261.510 ; - END - END wd_in[23] - PIN wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 263.810 0.460 264.270 ; - END - END wd_in[24] - PIN wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 266.570 0.460 267.030 ; - END - END wd_in[25] - PIN wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 269.330 0.460 269.790 ; - END - END wd_in[26] - PIN wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 272.090 0.460 272.550 ; - END - END wd_in[27] - PIN wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 274.850 0.460 275.310 ; - END - END wd_in[28] - PIN wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 277.610 0.460 278.070 ; - END - END wd_in[29] - PIN wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 280.370 0.460 280.830 ; - END - END wd_in[30] - PIN wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 283.130 0.460 283.590 ; - END - END wd_in[31] - PIN addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 294.170 0.460 294.630 ; - END - END addr_in[0] - PIN addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 296.930 0.460 297.390 ; - END - END addr_in[1] - PIN addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 299.690 0.460 300.150 ; - END - END addr_in[2] - PIN addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 302.450 0.460 302.910 ; - END - END addr_in[3] - PIN addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 305.210 0.460 305.670 ; - END - END addr_in[4] - PIN addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 307.970 0.460 308.430 ; - END - END addr_in[5] - PIN addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 310.730 0.460 311.190 ; - END - END addr_in[6] - PIN addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 313.490 0.460 313.950 ; - END - END addr_in[7] - PIN we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 324.530 0.460 324.990 ; - END - END we_in - PIN ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 327.290 0.460 327.750 ; - END - END ce_in - PIN clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 330.050 0.460 330.510 ; - END - END clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 3.680 4.600 5.520 344.920 ; - RECT 11.040 4.600 12.880 344.920 ; - RECT 18.400 4.600 20.240 344.920 ; - RECT 25.760 4.600 27.600 344.920 ; - RECT 33.120 4.600 34.960 344.920 ; - RECT 40.480 4.600 42.320 344.920 ; - RECT 47.840 4.600 49.680 344.920 ; - RECT 55.200 4.600 57.040 344.920 ; - RECT 62.560 4.600 64.400 344.920 ; - RECT 69.920 4.600 71.760 344.920 ; - RECT 77.280 4.600 79.120 344.920 ; - RECT 84.640 4.600 86.480 344.920 ; - RECT 92.000 4.600 93.840 344.920 ; - RECT 99.360 4.600 101.200 344.920 ; - RECT 106.720 4.600 108.560 344.920 ; - RECT 114.080 4.600 115.920 344.920 ; - RECT 121.440 4.600 123.280 344.920 ; - RECT 128.800 4.600 130.640 344.920 ; - RECT 136.160 4.600 138.000 344.920 ; - RECT 143.520 4.600 145.360 344.920 ; - RECT 150.880 4.600 152.720 344.920 ; - RECT 158.240 4.600 160.080 344.920 ; - RECT 165.600 4.600 167.440 344.920 ; - RECT 172.960 4.600 174.800 344.920 ; - RECT 180.320 4.600 182.160 344.920 ; - RECT 187.680 4.600 189.520 344.920 ; - RECT 195.040 4.600 196.880 344.920 ; - RECT 202.400 4.600 204.240 344.920 ; - RECT 209.760 4.600 211.600 344.920 ; - RECT 217.120 4.600 218.960 344.920 ; - RECT 224.480 4.600 226.320 344.920 ; - RECT 231.840 4.600 233.680 344.920 ; - RECT 239.200 4.600 241.040 344.920 ; - RECT 246.560 4.600 248.400 344.920 ; - RECT 253.920 4.600 255.760 344.920 ; - RECT 261.280 4.600 263.120 344.920 ; - RECT 268.640 4.600 270.480 344.920 ; - RECT 276.000 4.600 277.840 344.920 ; - RECT 283.360 4.600 285.200 344.920 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 7.360 4.600 9.200 344.920 ; - RECT 14.720 4.600 16.560 344.920 ; - RECT 22.080 4.600 23.920 344.920 ; - RECT 29.440 4.600 31.280 344.920 ; - RECT 36.800 4.600 38.640 344.920 ; - RECT 44.160 4.600 46.000 344.920 ; - RECT 51.520 4.600 53.360 344.920 ; - RECT 58.880 4.600 60.720 344.920 ; - RECT 66.240 4.600 68.080 344.920 ; - RECT 73.600 4.600 75.440 344.920 ; - RECT 80.960 4.600 82.800 344.920 ; - RECT 88.320 4.600 90.160 344.920 ; - RECT 95.680 4.600 97.520 344.920 ; - RECT 103.040 4.600 104.880 344.920 ; - RECT 110.400 4.600 112.240 344.920 ; - RECT 117.760 4.600 119.600 344.920 ; - RECT 125.120 4.600 126.960 344.920 ; - RECT 132.480 4.600 134.320 344.920 ; - RECT 139.840 4.600 141.680 344.920 ; - RECT 147.200 4.600 149.040 344.920 ; - RECT 154.560 4.600 156.400 344.920 ; - RECT 161.920 4.600 163.760 344.920 ; - RECT 169.280 4.600 171.120 344.920 ; - RECT 176.640 4.600 178.480 344.920 ; - RECT 184.000 4.600 185.840 344.920 ; - RECT 191.360 4.600 193.200 344.920 ; - RECT 198.720 4.600 200.560 344.920 ; - RECT 206.080 4.600 207.920 344.920 ; - RECT 213.440 4.600 215.280 344.920 ; - RECT 220.800 4.600 222.640 344.920 ; - RECT 228.160 4.600 230.000 344.920 ; - RECT 235.520 4.600 237.360 344.920 ; - RECT 242.880 4.600 244.720 344.920 ; - RECT 250.240 4.600 252.080 344.920 ; - RECT 257.600 4.600 259.440 344.920 ; - RECT 264.960 4.600 266.800 344.920 ; - RECT 272.320 4.600 274.160 344.920 ; - RECT 279.680 4.600 281.520 344.920 ; - RECT 287.040 4.600 288.880 344.920 ; - END - END VDD - OBS - LAYER met1 ; - RECT 0 0 293.940 349.520 ; - LAYER met2 ; - RECT 0 0 293.940 349.520 ; - LAYER met3 ; - RECT 0.460 0 293.940 349.520 ; - RECT 0 0.000 0.460 4.370 ; - RECT 0 4.830 0.460 7.130 ; - RECT 0 7.590 0.460 9.890 ; - RECT 0 10.350 0.460 12.650 ; - RECT 0 13.110 0.460 15.410 ; - RECT 0 15.870 0.460 18.170 ; - RECT 0 18.630 0.460 20.930 ; - RECT 0 21.390 0.460 23.690 ; - RECT 0 24.150 0.460 26.450 ; - RECT 0 26.910 0.460 29.210 ; - RECT 0 29.670 0.460 31.970 ; - RECT 0 32.430 0.460 34.730 ; - RECT 0 35.190 0.460 37.490 ; - RECT 0 37.950 0.460 40.250 ; - RECT 0 40.710 0.460 43.010 ; - RECT 0 43.470 0.460 45.770 ; - RECT 0 46.230 0.460 48.530 ; - RECT 0 48.990 0.460 51.290 ; - RECT 0 51.750 0.460 54.050 ; - RECT 0 54.510 0.460 56.810 ; - RECT 0 57.270 0.460 59.570 ; - RECT 0 60.030 0.460 62.330 ; - RECT 0 62.790 0.460 65.090 ; - RECT 0 65.550 0.460 67.850 ; - RECT 0 68.310 0.460 70.610 ; - RECT 0 71.070 0.460 73.370 ; - RECT 0 73.830 0.460 76.130 ; - RECT 0 76.590 0.460 78.890 ; - RECT 0 79.350 0.460 81.650 ; - RECT 0 82.110 0.460 84.410 ; - RECT 0 84.870 0.460 87.170 ; - RECT 0 87.630 0.460 89.930 ; - RECT 0 90.390 0.460 100.970 ; - RECT 0 101.430 0.460 103.730 ; - RECT 0 104.190 0.460 106.490 ; - RECT 0 106.950 0.460 109.250 ; - RECT 0 109.710 0.460 112.010 ; - RECT 0 112.470 0.460 114.770 ; - RECT 0 115.230 0.460 117.530 ; - RECT 0 117.990 0.460 120.290 ; - RECT 0 120.750 0.460 123.050 ; - RECT 0 123.510 0.460 125.810 ; - RECT 0 126.270 0.460 128.570 ; - RECT 0 129.030 0.460 131.330 ; - RECT 0 131.790 0.460 134.090 ; - RECT 0 134.550 0.460 136.850 ; - RECT 0 137.310 0.460 139.610 ; - RECT 0 140.070 0.460 142.370 ; - RECT 0 142.830 0.460 145.130 ; - RECT 0 145.590 0.460 147.890 ; - RECT 0 148.350 0.460 150.650 ; - RECT 0 151.110 0.460 153.410 ; - RECT 0 153.870 0.460 156.170 ; - RECT 0 156.630 0.460 158.930 ; - RECT 0 159.390 0.460 161.690 ; - RECT 0 162.150 0.460 164.450 ; - RECT 0 164.910 0.460 167.210 ; - RECT 0 167.670 0.460 169.970 ; - RECT 0 170.430 0.460 172.730 ; - RECT 0 173.190 0.460 175.490 ; - RECT 0 175.950 0.460 178.250 ; - RECT 0 178.710 0.460 181.010 ; - RECT 0 181.470 0.460 183.770 ; - RECT 0 184.230 0.460 186.530 ; - RECT 0 186.990 0.460 197.570 ; - RECT 0 198.030 0.460 200.330 ; - RECT 0 200.790 0.460 203.090 ; - RECT 0 203.550 0.460 205.850 ; - RECT 0 206.310 0.460 208.610 ; - RECT 0 209.070 0.460 211.370 ; - RECT 0 211.830 0.460 214.130 ; - RECT 0 214.590 0.460 216.890 ; - RECT 0 217.350 0.460 219.650 ; - RECT 0 220.110 0.460 222.410 ; - RECT 0 222.870 0.460 225.170 ; - RECT 0 225.630 0.460 227.930 ; - RECT 0 228.390 0.460 230.690 ; - RECT 0 231.150 0.460 233.450 ; - RECT 0 233.910 0.460 236.210 ; - RECT 0 236.670 0.460 238.970 ; - RECT 0 239.430 0.460 241.730 ; - RECT 0 242.190 0.460 244.490 ; - RECT 0 244.950 0.460 247.250 ; - RECT 0 247.710 0.460 250.010 ; - RECT 0 250.470 0.460 252.770 ; - RECT 0 253.230 0.460 255.530 ; - RECT 0 255.990 0.460 258.290 ; - RECT 0 258.750 0.460 261.050 ; - RECT 0 261.510 0.460 263.810 ; - RECT 0 264.270 0.460 266.570 ; - RECT 0 267.030 0.460 269.330 ; - RECT 0 269.790 0.460 272.090 ; - RECT 0 272.550 0.460 274.850 ; - RECT 0 275.310 0.460 277.610 ; - RECT 0 278.070 0.460 280.370 ; - RECT 0 280.830 0.460 283.130 ; - RECT 0 283.590 0.460 294.170 ; - RECT 0 294.630 0.460 296.930 ; - RECT 0 297.390 0.460 299.690 ; - RECT 0 300.150 0.460 302.450 ; - RECT 0 302.910 0.460 305.210 ; - RECT 0 305.670 0.460 307.970 ; - RECT 0 308.430 0.460 310.730 ; - RECT 0 311.190 0.460 313.490 ; - RECT 0 313.950 0.460 324.530 ; - RECT 0 324.990 0.460 327.290 ; - RECT 0 327.750 0.460 330.050 ; - RECT 0 330.510 0.460 349.520 ; - LAYER met4 ; - RECT 0 0 293.940 4.600 ; - RECT 0 344.920 293.940 349.520 ; - RECT 0.000 4.600 3.680 344.920 ; - RECT 5.520 4.600 7.360 344.920 ; - RECT 9.200 4.600 11.040 344.920 ; - RECT 12.880 4.600 14.720 344.920 ; - RECT 16.560 4.600 18.400 344.920 ; - RECT 20.240 4.600 22.080 344.920 ; - RECT 23.920 4.600 25.760 344.920 ; - RECT 27.600 4.600 29.440 344.920 ; - RECT 31.280 4.600 33.120 344.920 ; - RECT 34.960 4.600 36.800 344.920 ; - RECT 38.640 4.600 40.480 344.920 ; - RECT 42.320 4.600 44.160 344.920 ; - RECT 46.000 4.600 47.840 344.920 ; - RECT 49.680 4.600 51.520 344.920 ; - RECT 53.360 4.600 55.200 344.920 ; - RECT 57.040 4.600 58.880 344.920 ; - RECT 60.720 4.600 62.560 344.920 ; - RECT 64.400 4.600 66.240 344.920 ; - RECT 68.080 4.600 69.920 344.920 ; - RECT 71.760 4.600 73.600 344.920 ; - RECT 75.440 4.600 77.280 344.920 ; - RECT 79.120 4.600 80.960 344.920 ; - RECT 82.800 4.600 84.640 344.920 ; - RECT 86.480 4.600 88.320 344.920 ; - RECT 90.160 4.600 92.000 344.920 ; - RECT 93.840 4.600 95.680 344.920 ; - RECT 97.520 4.600 99.360 344.920 ; - RECT 101.200 4.600 103.040 344.920 ; - RECT 104.880 4.600 106.720 344.920 ; - RECT 108.560 4.600 110.400 344.920 ; - RECT 112.240 4.600 114.080 344.920 ; - RECT 115.920 4.600 117.760 344.920 ; - RECT 119.600 4.600 121.440 344.920 ; - RECT 123.280 4.600 125.120 344.920 ; - RECT 126.960 4.600 128.800 344.920 ; - RECT 130.640 4.600 132.480 344.920 ; - RECT 134.320 4.600 136.160 344.920 ; - RECT 138.000 4.600 139.840 344.920 ; - RECT 141.680 4.600 143.520 344.920 ; - RECT 145.360 4.600 147.200 344.920 ; - RECT 149.040 4.600 150.880 344.920 ; - RECT 152.720 4.600 154.560 344.920 ; - RECT 156.400 4.600 158.240 344.920 ; - RECT 160.080 4.600 161.920 344.920 ; - RECT 163.760 4.600 165.600 344.920 ; - RECT 167.440 4.600 169.280 344.920 ; - RECT 171.120 4.600 172.960 344.920 ; - RECT 174.800 4.600 176.640 344.920 ; - RECT 178.480 4.600 180.320 344.920 ; - RECT 182.160 4.600 184.000 344.920 ; - RECT 185.840 4.600 187.680 344.920 ; - RECT 189.520 4.600 191.360 344.920 ; - RECT 193.200 4.600 195.040 344.920 ; - RECT 196.880 4.600 198.720 344.920 ; - RECT 200.560 4.600 202.400 344.920 ; - RECT 204.240 4.600 206.080 344.920 ; - RECT 207.920 4.600 209.760 344.920 ; - RECT 211.600 4.600 213.440 344.920 ; - RECT 215.280 4.600 217.120 344.920 ; - RECT 218.960 4.600 220.800 344.920 ; - RECT 222.640 4.600 224.480 344.920 ; - RECT 226.320 4.600 228.160 344.920 ; - RECT 230.000 4.600 231.840 344.920 ; - RECT 233.680 4.600 235.520 344.920 ; - RECT 237.360 4.600 239.200 344.920 ; - RECT 241.040 4.600 242.880 344.920 ; - RECT 244.720 4.600 246.560 344.920 ; - RECT 248.400 4.600 250.240 344.920 ; - RECT 252.080 4.600 253.920 344.920 ; - RECT 255.760 4.600 257.600 344.920 ; - RECT 259.440 4.600 261.280 344.920 ; - RECT 263.120 4.600 264.960 344.920 ; - RECT 266.800 4.600 268.640 344.920 ; - RECT 270.480 4.600 272.320 344.920 ; - RECT 274.160 4.600 276.000 344.920 ; - RECT 277.840 4.600 279.680 344.920 ; - RECT 281.520 4.600 283.360 344.920 ; - RECT 285.200 4.600 287.040 344.920 ; - RECT 288.880 4.600 293.940 344.920 ; - END -END fakeram130_256x32 - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x512.lef b/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x512.lef deleted file mode 100644 index 25b33f0887..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x512.lef +++ /dev/null @@ -1,15957 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram130_256x512 - FOREIGN fakeram130_256x512 0 0 ; - SYMMETRY X Y ; - SIZE 834.440 BY 1052.640 ; - CLASS BLOCK ; - PIN w_mask_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.370 0.460 4.830 ; - END - END w_mask_in[0] - PIN w_mask_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.830 0.460 5.290 ; - END - END w_mask_in[1] - PIN w_mask_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 5.290 0.460 5.750 ; - END - END w_mask_in[2] - PIN w_mask_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 5.750 0.460 6.210 ; - END - END w_mask_in[3] - PIN w_mask_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 6.210 0.460 6.670 ; - END - END w_mask_in[4] - PIN w_mask_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 6.670 0.460 7.130 ; - END - END w_mask_in[5] - PIN w_mask_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.130 0.460 7.590 ; - END - END w_mask_in[6] - PIN w_mask_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.590 0.460 8.050 ; - END - END w_mask_in[7] - PIN w_mask_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.050 0.460 8.510 ; - END - END w_mask_in[8] - PIN w_mask_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.510 0.460 8.970 ; - END - END w_mask_in[9] - PIN w_mask_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.970 0.460 9.430 ; - END - END w_mask_in[10] - PIN w_mask_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.430 0.460 9.890 ; - END - END w_mask_in[11] - PIN w_mask_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.890 0.460 10.350 ; - END - END w_mask_in[12] - PIN w_mask_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 10.350 0.460 10.810 ; - END - END w_mask_in[13] - PIN w_mask_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 10.810 0.460 11.270 ; - END - END w_mask_in[14] - PIN w_mask_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 11.270 0.460 11.730 ; - END - END w_mask_in[15] - PIN w_mask_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 11.730 0.460 12.190 ; - END - END w_mask_in[16] - PIN w_mask_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.190 0.460 12.650 ; - END - END w_mask_in[17] - PIN w_mask_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.650 0.460 13.110 ; - END - END w_mask_in[18] - PIN w_mask_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 13.110 0.460 13.570 ; - END - END w_mask_in[19] - PIN w_mask_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 13.570 0.460 14.030 ; - END - END w_mask_in[20] - PIN w_mask_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.030 0.460 14.490 ; - END - END w_mask_in[21] - PIN w_mask_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.490 0.460 14.950 ; - END - END w_mask_in[22] - PIN w_mask_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.950 0.460 15.410 ; - END - END w_mask_in[23] - PIN w_mask_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.410 0.460 15.870 ; - END - END w_mask_in[24] - PIN w_mask_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.870 0.460 16.330 ; - END - END w_mask_in[25] - PIN w_mask_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 16.330 0.460 16.790 ; - END - END w_mask_in[26] - PIN w_mask_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 16.790 0.460 17.250 ; - END - END w_mask_in[27] - PIN w_mask_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 17.250 0.460 17.710 ; - END - END w_mask_in[28] - PIN w_mask_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 17.710 0.460 18.170 ; - END - END w_mask_in[29] - PIN w_mask_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.170 0.460 18.630 ; - END - END w_mask_in[30] - PIN w_mask_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.630 0.460 19.090 ; - END - END w_mask_in[31] - PIN w_mask_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 19.090 0.460 19.550 ; - END - END w_mask_in[32] - PIN w_mask_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 19.550 0.460 20.010 ; - END - END w_mask_in[33] - PIN w_mask_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.010 0.460 20.470 ; - END - END w_mask_in[34] - PIN w_mask_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.470 0.460 20.930 ; - END - END w_mask_in[35] - PIN w_mask_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.930 0.460 21.390 ; - END - END w_mask_in[36] - PIN w_mask_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 21.390 0.460 21.850 ; - END - END w_mask_in[37] - PIN w_mask_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 21.850 0.460 22.310 ; - END - END w_mask_in[38] - PIN w_mask_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 22.310 0.460 22.770 ; - END - END w_mask_in[39] - PIN w_mask_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 22.770 0.460 23.230 ; - END - END w_mask_in[40] - PIN w_mask_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.230 0.460 23.690 ; - END - END w_mask_in[41] - PIN w_mask_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.690 0.460 24.150 ; - END - END w_mask_in[42] - PIN w_mask_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 24.150 0.460 24.610 ; - END - END w_mask_in[43] - PIN w_mask_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 24.610 0.460 25.070 ; - END - END w_mask_in[44] - PIN w_mask_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.070 0.460 25.530 ; - END - END w_mask_in[45] - PIN w_mask_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.530 0.460 25.990 ; - END - END w_mask_in[46] - PIN w_mask_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.990 0.460 26.450 ; - END - END w_mask_in[47] - PIN w_mask_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.450 0.460 26.910 ; - END - END w_mask_in[48] - PIN w_mask_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.910 0.460 27.370 ; - END - END w_mask_in[49] - PIN w_mask_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 27.370 0.460 27.830 ; - END - END w_mask_in[50] - PIN w_mask_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 27.830 0.460 28.290 ; - END - END w_mask_in[51] - PIN w_mask_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 28.290 0.460 28.750 ; - END - END w_mask_in[52] - PIN w_mask_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 28.750 0.460 29.210 ; - END - END w_mask_in[53] - PIN w_mask_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.210 0.460 29.670 ; - END - END w_mask_in[54] - PIN w_mask_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.670 0.460 30.130 ; - END - END w_mask_in[55] - PIN w_mask_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 30.130 0.460 30.590 ; - END - END w_mask_in[56] - PIN w_mask_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 30.590 0.460 31.050 ; - END - END w_mask_in[57] - PIN w_mask_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.050 0.460 31.510 ; - END - END w_mask_in[58] - PIN w_mask_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.510 0.460 31.970 ; - END - END w_mask_in[59] - PIN w_mask_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.970 0.460 32.430 ; - END - END w_mask_in[60] - PIN w_mask_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 32.430 0.460 32.890 ; - END - END w_mask_in[61] - PIN w_mask_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 32.890 0.460 33.350 ; - END - END w_mask_in[62] - PIN w_mask_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 33.350 0.460 33.810 ; - END - END w_mask_in[63] - PIN w_mask_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 33.810 0.460 34.270 ; - END - END w_mask_in[64] - PIN w_mask_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 34.270 0.460 34.730 ; - END - END w_mask_in[65] - PIN w_mask_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 34.730 0.460 35.190 ; - END - END w_mask_in[66] - PIN w_mask_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 35.190 0.460 35.650 ; - END - END w_mask_in[67] - PIN w_mask_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 35.650 0.460 36.110 ; - END - END w_mask_in[68] - PIN w_mask_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 36.110 0.460 36.570 ; - END - END w_mask_in[69] - PIN w_mask_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 36.570 0.460 37.030 ; - END - END w_mask_in[70] - PIN w_mask_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.030 0.460 37.490 ; - END - END w_mask_in[71] - PIN w_mask_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.490 0.460 37.950 ; - END - END w_mask_in[72] - PIN w_mask_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.950 0.460 38.410 ; - END - END w_mask_in[73] - PIN w_mask_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 38.410 0.460 38.870 ; - END - END w_mask_in[74] - PIN w_mask_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 38.870 0.460 39.330 ; - END - END w_mask_in[75] - PIN w_mask_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 39.330 0.460 39.790 ; - END - END w_mask_in[76] - PIN w_mask_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 39.790 0.460 40.250 ; - END - END w_mask_in[77] - PIN w_mask_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 40.250 0.460 40.710 ; - END - END w_mask_in[78] - PIN w_mask_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 40.710 0.460 41.170 ; - END - END w_mask_in[79] - PIN w_mask_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 41.170 0.460 41.630 ; - END - END w_mask_in[80] - PIN w_mask_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 41.630 0.460 42.090 ; - END - END w_mask_in[81] - PIN w_mask_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 42.090 0.460 42.550 ; - END - END w_mask_in[82] - PIN w_mask_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 42.550 0.460 43.010 ; - END - END w_mask_in[83] - PIN w_mask_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.010 0.460 43.470 ; - END - END w_mask_in[84] - PIN w_mask_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.470 0.460 43.930 ; - END - END w_mask_in[85] - PIN w_mask_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.930 0.460 44.390 ; - END - END w_mask_in[86] - PIN w_mask_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 44.390 0.460 44.850 ; - END - END w_mask_in[87] - PIN w_mask_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 44.850 0.460 45.310 ; - END - END w_mask_in[88] - PIN w_mask_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 45.310 0.460 45.770 ; - END - END w_mask_in[89] - PIN w_mask_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 45.770 0.460 46.230 ; - END - END w_mask_in[90] - PIN w_mask_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 46.230 0.460 46.690 ; - END - END w_mask_in[91] - PIN w_mask_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 46.690 0.460 47.150 ; - END - END w_mask_in[92] - PIN w_mask_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 47.150 0.460 47.610 ; - END - END w_mask_in[93] - PIN w_mask_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 47.610 0.460 48.070 ; - END - END w_mask_in[94] - PIN w_mask_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.070 0.460 48.530 ; - END - END w_mask_in[95] - PIN w_mask_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.530 0.460 48.990 ; - END - END w_mask_in[96] - PIN w_mask_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.990 0.460 49.450 ; - END - END w_mask_in[97] - PIN w_mask_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.450 0.460 49.910 ; - END - END w_mask_in[98] - PIN w_mask_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.910 0.460 50.370 ; - END - END w_mask_in[99] - PIN w_mask_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 50.370 0.460 50.830 ; - END - END w_mask_in[100] - PIN w_mask_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 50.830 0.460 51.290 ; - END - END w_mask_in[101] - PIN w_mask_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.290 0.460 51.750 ; - END - END w_mask_in[102] - PIN w_mask_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.750 0.460 52.210 ; - END - END w_mask_in[103] - PIN w_mask_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.210 0.460 52.670 ; - END - END w_mask_in[104] - PIN w_mask_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.670 0.460 53.130 ; - END - END w_mask_in[105] - PIN w_mask_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 53.130 0.460 53.590 ; - END - END w_mask_in[106] - PIN w_mask_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 53.590 0.460 54.050 ; - END - END w_mask_in[107] - PIN w_mask_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.050 0.460 54.510 ; - END - END w_mask_in[108] - PIN w_mask_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.510 0.460 54.970 ; - END - END w_mask_in[109] - PIN w_mask_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.970 0.460 55.430 ; - END - END w_mask_in[110] - PIN w_mask_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 55.430 0.460 55.890 ; - END - END w_mask_in[111] - PIN w_mask_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 55.890 0.460 56.350 ; - END - END w_mask_in[112] - PIN w_mask_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.350 0.460 56.810 ; - END - END w_mask_in[113] - PIN w_mask_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.810 0.460 57.270 ; - END - END w_mask_in[114] - PIN w_mask_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.270 0.460 57.730 ; - END - END w_mask_in[115] - PIN w_mask_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.730 0.460 58.190 ; - END - END w_mask_in[116] - PIN w_mask_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 58.190 0.460 58.650 ; - END - END w_mask_in[117] - PIN w_mask_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 58.650 0.460 59.110 ; - END - END w_mask_in[118] - PIN w_mask_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.110 0.460 59.570 ; - END - END w_mask_in[119] - PIN w_mask_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.570 0.460 60.030 ; - END - END w_mask_in[120] - PIN w_mask_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.030 0.460 60.490 ; - END - END w_mask_in[121] - PIN w_mask_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.490 0.460 60.950 ; - END - END w_mask_in[122] - PIN w_mask_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.950 0.460 61.410 ; - END - END w_mask_in[123] - PIN w_mask_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 61.410 0.460 61.870 ; - END - END w_mask_in[124] - PIN w_mask_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 61.870 0.460 62.330 ; - END - END w_mask_in[125] - PIN w_mask_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.330 0.460 62.790 ; - END - END w_mask_in[126] - PIN w_mask_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.790 0.460 63.250 ; - END - END w_mask_in[127] - PIN w_mask_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 63.250 0.460 63.710 ; - END - END w_mask_in[128] - PIN w_mask_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 63.710 0.460 64.170 ; - END - END w_mask_in[129] - PIN w_mask_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 64.170 0.460 64.630 ; - END - END w_mask_in[130] - PIN w_mask_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 64.630 0.460 65.090 ; - END - END w_mask_in[131] - PIN w_mask_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 65.090 0.460 65.550 ; - END - END w_mask_in[132] - PIN w_mask_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 65.550 0.460 66.010 ; - END - END w_mask_in[133] - PIN w_mask_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.010 0.460 66.470 ; - END - END w_mask_in[134] - PIN w_mask_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.470 0.460 66.930 ; - END - END w_mask_in[135] - PIN w_mask_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.930 0.460 67.390 ; - END - END w_mask_in[136] - PIN w_mask_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 67.390 0.460 67.850 ; - END - END w_mask_in[137] - PIN w_mask_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 67.850 0.460 68.310 ; - END - END w_mask_in[138] - PIN w_mask_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 68.310 0.460 68.770 ; - END - END w_mask_in[139] - PIN w_mask_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 68.770 0.460 69.230 ; - END - END w_mask_in[140] - PIN w_mask_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 69.230 0.460 69.690 ; - END - END w_mask_in[141] - PIN w_mask_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 69.690 0.460 70.150 ; - END - END w_mask_in[142] - PIN w_mask_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 70.150 0.460 70.610 ; - END - END w_mask_in[143] - PIN w_mask_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 70.610 0.460 71.070 ; - END - END w_mask_in[144] - PIN w_mask_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.070 0.460 71.530 ; - END - END w_mask_in[145] - PIN w_mask_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.530 0.460 71.990 ; - END - END w_mask_in[146] - PIN w_mask_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.990 0.460 72.450 ; - END - END w_mask_in[147] - PIN w_mask_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 72.450 0.460 72.910 ; - END - END w_mask_in[148] - PIN w_mask_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 72.910 0.460 73.370 ; - END - END w_mask_in[149] - PIN w_mask_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.370 0.460 73.830 ; - END - END w_mask_in[150] - PIN w_mask_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.830 0.460 74.290 ; - END - END w_mask_in[151] - PIN w_mask_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.290 0.460 74.750 ; - END - END w_mask_in[152] - PIN w_mask_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.750 0.460 75.210 ; - END - END w_mask_in[153] - PIN w_mask_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 75.210 0.460 75.670 ; - END - END w_mask_in[154] - PIN w_mask_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 75.670 0.460 76.130 ; - END - END w_mask_in[155] - PIN w_mask_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.130 0.460 76.590 ; - END - END w_mask_in[156] - PIN w_mask_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.590 0.460 77.050 ; - END - END w_mask_in[157] - PIN w_mask_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.050 0.460 77.510 ; - END - END w_mask_in[158] - PIN w_mask_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.510 0.460 77.970 ; - END - END w_mask_in[159] - PIN w_mask_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.970 0.460 78.430 ; - END - END w_mask_in[160] - PIN w_mask_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 78.430 0.460 78.890 ; - END - END w_mask_in[161] - PIN w_mask_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 78.890 0.460 79.350 ; - END - END w_mask_in[162] - PIN w_mask_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 79.350 0.460 79.810 ; - END - END w_mask_in[163] - PIN w_mask_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 79.810 0.460 80.270 ; - END - END w_mask_in[164] - PIN w_mask_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 80.270 0.460 80.730 ; - END - END w_mask_in[165] - PIN w_mask_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 80.730 0.460 81.190 ; - END - END w_mask_in[166] - PIN w_mask_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 81.190 0.460 81.650 ; - END - END w_mask_in[167] - PIN w_mask_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 81.650 0.460 82.110 ; - END - END w_mask_in[168] - PIN w_mask_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 82.110 0.460 82.570 ; - END - END w_mask_in[169] - PIN w_mask_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 82.570 0.460 83.030 ; - END - END w_mask_in[170] - PIN w_mask_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 83.030 0.460 83.490 ; - END - END w_mask_in[171] - PIN w_mask_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 83.490 0.460 83.950 ; - END - END w_mask_in[172] - PIN w_mask_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 83.950 0.460 84.410 ; - END - END w_mask_in[173] - PIN w_mask_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 84.410 0.460 84.870 ; - END - END w_mask_in[174] - PIN w_mask_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 84.870 0.460 85.330 ; - END - END w_mask_in[175] - PIN w_mask_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 85.330 0.460 85.790 ; - END - END w_mask_in[176] - PIN w_mask_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 85.790 0.460 86.250 ; - END - END w_mask_in[177] - PIN w_mask_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 86.250 0.460 86.710 ; - END - END w_mask_in[178] - PIN w_mask_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 86.710 0.460 87.170 ; - END - END w_mask_in[179] - PIN w_mask_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 87.170 0.460 87.630 ; - END - END w_mask_in[180] - PIN w_mask_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 87.630 0.460 88.090 ; - END - END w_mask_in[181] - PIN w_mask_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 88.090 0.460 88.550 ; - END - END w_mask_in[182] - PIN w_mask_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 88.550 0.460 89.010 ; - END - END w_mask_in[183] - PIN w_mask_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.010 0.460 89.470 ; - END - END w_mask_in[184] - PIN w_mask_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.470 0.460 89.930 ; - END - END w_mask_in[185] - PIN w_mask_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.930 0.460 90.390 ; - END - END w_mask_in[186] - PIN w_mask_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 90.390 0.460 90.850 ; - END - END w_mask_in[187] - PIN w_mask_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 90.850 0.460 91.310 ; - END - END w_mask_in[188] - PIN w_mask_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 91.310 0.460 91.770 ; - END - END w_mask_in[189] - PIN w_mask_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 91.770 0.460 92.230 ; - END - END w_mask_in[190] - PIN w_mask_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 92.230 0.460 92.690 ; - END - END w_mask_in[191] - PIN w_mask_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 92.690 0.460 93.150 ; - END - END w_mask_in[192] - PIN w_mask_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 93.150 0.460 93.610 ; - END - END w_mask_in[193] - PIN w_mask_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 93.610 0.460 94.070 ; - END - END w_mask_in[194] - PIN w_mask_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.070 0.460 94.530 ; - END - END w_mask_in[195] - PIN w_mask_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.530 0.460 94.990 ; - END - END w_mask_in[196] - PIN w_mask_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.990 0.460 95.450 ; - END - END w_mask_in[197] - PIN w_mask_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 95.450 0.460 95.910 ; - END - END w_mask_in[198] - PIN w_mask_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 95.910 0.460 96.370 ; - END - END w_mask_in[199] - PIN w_mask_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 96.370 0.460 96.830 ; - END - END w_mask_in[200] - PIN w_mask_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 96.830 0.460 97.290 ; - END - END w_mask_in[201] - PIN w_mask_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.290 0.460 97.750 ; - END - END w_mask_in[202] - PIN w_mask_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.750 0.460 98.210 ; - END - END w_mask_in[203] - PIN w_mask_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 98.210 0.460 98.670 ; - END - END w_mask_in[204] - PIN w_mask_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 98.670 0.460 99.130 ; - END - END w_mask_in[205] - PIN w_mask_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 99.130 0.460 99.590 ; - END - END w_mask_in[206] - PIN w_mask_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 99.590 0.460 100.050 ; - END - END w_mask_in[207] - PIN w_mask_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.050 0.460 100.510 ; - END - END w_mask_in[208] - PIN w_mask_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.510 0.460 100.970 ; - END - END w_mask_in[209] - PIN w_mask_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.970 0.460 101.430 ; - END - END w_mask_in[210] - PIN w_mask_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 101.430 0.460 101.890 ; - END - END w_mask_in[211] - PIN w_mask_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 101.890 0.460 102.350 ; - END - END w_mask_in[212] - PIN w_mask_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.350 0.460 102.810 ; - END - END w_mask_in[213] - PIN w_mask_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.810 0.460 103.270 ; - END - END w_mask_in[214] - PIN w_mask_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.270 0.460 103.730 ; - END - END w_mask_in[215] - PIN w_mask_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.730 0.460 104.190 ; - END - END w_mask_in[216] - PIN w_mask_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 104.190 0.460 104.650 ; - END - END w_mask_in[217] - PIN w_mask_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 104.650 0.460 105.110 ; - END - END w_mask_in[218] - PIN w_mask_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.110 0.460 105.570 ; - END - END w_mask_in[219] - PIN w_mask_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.570 0.460 106.030 ; - END - END w_mask_in[220] - PIN w_mask_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.030 0.460 106.490 ; - END - END w_mask_in[221] - PIN w_mask_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.490 0.460 106.950 ; - END - END w_mask_in[222] - PIN w_mask_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.950 0.460 107.410 ; - END - END w_mask_in[223] - PIN w_mask_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 107.410 0.460 107.870 ; - END - END w_mask_in[224] - PIN w_mask_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 107.870 0.460 108.330 ; - END - END w_mask_in[225] - PIN w_mask_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.330 0.460 108.790 ; - END - END w_mask_in[226] - PIN w_mask_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.790 0.460 109.250 ; - END - END w_mask_in[227] - PIN w_mask_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.250 0.460 109.710 ; - END - END w_mask_in[228] - PIN w_mask_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.710 0.460 110.170 ; - END - END w_mask_in[229] - PIN w_mask_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 110.170 0.460 110.630 ; - END - END w_mask_in[230] - PIN w_mask_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 110.630 0.460 111.090 ; - END - END w_mask_in[231] - PIN w_mask_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.090 0.460 111.550 ; - END - END w_mask_in[232] - PIN w_mask_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.550 0.460 112.010 ; - END - END w_mask_in[233] - PIN w_mask_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.010 0.460 112.470 ; - END - END w_mask_in[234] - PIN w_mask_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.470 0.460 112.930 ; - END - END w_mask_in[235] - PIN w_mask_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.930 0.460 113.390 ; - END - END w_mask_in[236] - PIN w_mask_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.390 0.460 113.850 ; - END - END w_mask_in[237] - PIN w_mask_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.850 0.460 114.310 ; - END - END w_mask_in[238] - PIN w_mask_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.310 0.460 114.770 ; - END - END w_mask_in[239] - PIN w_mask_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.770 0.460 115.230 ; - END - END w_mask_in[240] - PIN w_mask_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 115.230 0.460 115.690 ; - END - END w_mask_in[241] - PIN w_mask_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 115.690 0.460 116.150 ; - END - END w_mask_in[242] - PIN w_mask_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.150 0.460 116.610 ; - END - END w_mask_in[243] - PIN w_mask_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.610 0.460 117.070 ; - END - END w_mask_in[244] - PIN w_mask_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.070 0.460 117.530 ; - END - END w_mask_in[245] - PIN w_mask_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.530 0.460 117.990 ; - END - END w_mask_in[246] - PIN w_mask_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.990 0.460 118.450 ; - END - END w_mask_in[247] - PIN w_mask_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 118.450 0.460 118.910 ; - END - END w_mask_in[248] - PIN w_mask_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 118.910 0.460 119.370 ; - END - END w_mask_in[249] - PIN w_mask_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.370 0.460 119.830 ; - END - END w_mask_in[250] - PIN w_mask_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.830 0.460 120.290 ; - END - END w_mask_in[251] - PIN w_mask_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 120.290 0.460 120.750 ; - END - END w_mask_in[252] - PIN w_mask_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 120.750 0.460 121.210 ; - END - END w_mask_in[253] - PIN w_mask_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 121.210 0.460 121.670 ; - END - END w_mask_in[254] - PIN w_mask_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 121.670 0.460 122.130 ; - END - END w_mask_in[255] - PIN w_mask_in[256] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 122.130 0.460 122.590 ; - END - END w_mask_in[256] - PIN w_mask_in[257] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 122.590 0.460 123.050 ; - END - END w_mask_in[257] - PIN w_mask_in[258] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.050 0.460 123.510 ; - END - END w_mask_in[258] - PIN w_mask_in[259] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.510 0.460 123.970 ; - END - END w_mask_in[259] - PIN w_mask_in[260] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.970 0.460 124.430 ; - END - END w_mask_in[260] - PIN w_mask_in[261] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 124.430 0.460 124.890 ; - END - END w_mask_in[261] - PIN w_mask_in[262] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 124.890 0.460 125.350 ; - END - END w_mask_in[262] - PIN w_mask_in[263] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 125.350 0.460 125.810 ; - END - END w_mask_in[263] - PIN w_mask_in[264] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 125.810 0.460 126.270 ; - END - END w_mask_in[264] - PIN w_mask_in[265] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 126.270 0.460 126.730 ; - END - END w_mask_in[265] - PIN w_mask_in[266] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 126.730 0.460 127.190 ; - END - END w_mask_in[266] - PIN w_mask_in[267] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 127.190 0.460 127.650 ; - END - END w_mask_in[267] - PIN w_mask_in[268] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 127.650 0.460 128.110 ; - END - END w_mask_in[268] - PIN w_mask_in[269] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 128.110 0.460 128.570 ; - END - END w_mask_in[269] - PIN w_mask_in[270] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 128.570 0.460 129.030 ; - END - END w_mask_in[270] - PIN w_mask_in[271] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 129.030 0.460 129.490 ; - END - END w_mask_in[271] - PIN w_mask_in[272] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 129.490 0.460 129.950 ; - END - END w_mask_in[272] - PIN w_mask_in[273] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 129.950 0.460 130.410 ; - END - END w_mask_in[273] - PIN w_mask_in[274] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 130.410 0.460 130.870 ; - END - END w_mask_in[274] - PIN w_mask_in[275] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 130.870 0.460 131.330 ; - END - END w_mask_in[275] - PIN w_mask_in[276] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 131.330 0.460 131.790 ; - END - END w_mask_in[276] - PIN w_mask_in[277] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 131.790 0.460 132.250 ; - END - END w_mask_in[277] - PIN w_mask_in[278] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 132.250 0.460 132.710 ; - END - END w_mask_in[278] - PIN w_mask_in[279] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 132.710 0.460 133.170 ; - END - END w_mask_in[279] - PIN w_mask_in[280] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 133.170 0.460 133.630 ; - END - END w_mask_in[280] - PIN w_mask_in[281] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 133.630 0.460 134.090 ; - END - END w_mask_in[281] - PIN w_mask_in[282] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 134.090 0.460 134.550 ; - END - END w_mask_in[282] - PIN w_mask_in[283] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 134.550 0.460 135.010 ; - END - END w_mask_in[283] - PIN w_mask_in[284] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.010 0.460 135.470 ; - END - END w_mask_in[284] - PIN w_mask_in[285] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.470 0.460 135.930 ; - END - END w_mask_in[285] - PIN w_mask_in[286] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.930 0.460 136.390 ; - END - END w_mask_in[286] - PIN w_mask_in[287] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 136.390 0.460 136.850 ; - END - END w_mask_in[287] - PIN w_mask_in[288] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 136.850 0.460 137.310 ; - END - END w_mask_in[288] - PIN w_mask_in[289] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 137.310 0.460 137.770 ; - END - END w_mask_in[289] - PIN w_mask_in[290] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 137.770 0.460 138.230 ; - END - END w_mask_in[290] - PIN w_mask_in[291] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 138.230 0.460 138.690 ; - END - END w_mask_in[291] - PIN w_mask_in[292] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 138.690 0.460 139.150 ; - END - END w_mask_in[292] - PIN w_mask_in[293] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 139.150 0.460 139.610 ; - END - END w_mask_in[293] - PIN w_mask_in[294] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 139.610 0.460 140.070 ; - END - END w_mask_in[294] - PIN w_mask_in[295] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 140.070 0.460 140.530 ; - END - END w_mask_in[295] - PIN w_mask_in[296] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 140.530 0.460 140.990 ; - END - END w_mask_in[296] - PIN w_mask_in[297] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 140.990 0.460 141.450 ; - END - END w_mask_in[297] - PIN w_mask_in[298] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 141.450 0.460 141.910 ; - END - END w_mask_in[298] - PIN w_mask_in[299] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 141.910 0.460 142.370 ; - END - END w_mask_in[299] - PIN w_mask_in[300] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 142.370 0.460 142.830 ; - END - END w_mask_in[300] - PIN w_mask_in[301] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 142.830 0.460 143.290 ; - END - END w_mask_in[301] - PIN w_mask_in[302] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 143.290 0.460 143.750 ; - END - END w_mask_in[302] - PIN w_mask_in[303] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 143.750 0.460 144.210 ; - END - END w_mask_in[303] - PIN w_mask_in[304] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 144.210 0.460 144.670 ; - END - END w_mask_in[304] - PIN w_mask_in[305] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 144.670 0.460 145.130 ; - END - END w_mask_in[305] - PIN w_mask_in[306] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 145.130 0.460 145.590 ; - END - END w_mask_in[306] - PIN w_mask_in[307] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 145.590 0.460 146.050 ; - END - END w_mask_in[307] - PIN w_mask_in[308] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 146.050 0.460 146.510 ; - END - END w_mask_in[308] - PIN w_mask_in[309] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 146.510 0.460 146.970 ; - END - END w_mask_in[309] - PIN w_mask_in[310] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 146.970 0.460 147.430 ; - END - END w_mask_in[310] - PIN w_mask_in[311] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 147.430 0.460 147.890 ; - END - END w_mask_in[311] - PIN w_mask_in[312] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 147.890 0.460 148.350 ; - END - END w_mask_in[312] - PIN w_mask_in[313] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 148.350 0.460 148.810 ; - END - END w_mask_in[313] - PIN w_mask_in[314] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 148.810 0.460 149.270 ; - END - END w_mask_in[314] - PIN w_mask_in[315] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 149.270 0.460 149.730 ; - END - END w_mask_in[315] - PIN w_mask_in[316] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 149.730 0.460 150.190 ; - END - END w_mask_in[316] - PIN w_mask_in[317] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 150.190 0.460 150.650 ; - END - END w_mask_in[317] - PIN w_mask_in[318] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 150.650 0.460 151.110 ; - END - END w_mask_in[318] - PIN w_mask_in[319] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 151.110 0.460 151.570 ; - END - END w_mask_in[319] - PIN w_mask_in[320] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 151.570 0.460 152.030 ; - END - END w_mask_in[320] - PIN w_mask_in[321] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.030 0.460 152.490 ; - END - END w_mask_in[321] - PIN w_mask_in[322] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.490 0.460 152.950 ; - END - END w_mask_in[322] - PIN w_mask_in[323] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.950 0.460 153.410 ; - END - END w_mask_in[323] - PIN w_mask_in[324] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 153.410 0.460 153.870 ; - END - END w_mask_in[324] - PIN w_mask_in[325] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 153.870 0.460 154.330 ; - END - END w_mask_in[325] - PIN w_mask_in[326] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 154.330 0.460 154.790 ; - END - END w_mask_in[326] - PIN w_mask_in[327] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 154.790 0.460 155.250 ; - END - END w_mask_in[327] - PIN w_mask_in[328] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 155.250 0.460 155.710 ; - END - END w_mask_in[328] - PIN w_mask_in[329] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 155.710 0.460 156.170 ; - END - END w_mask_in[329] - PIN w_mask_in[330] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 156.170 0.460 156.630 ; - END - END w_mask_in[330] - PIN w_mask_in[331] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 156.630 0.460 157.090 ; - END - END w_mask_in[331] - PIN w_mask_in[332] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 157.090 0.460 157.550 ; - END - END w_mask_in[332] - PIN w_mask_in[333] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 157.550 0.460 158.010 ; - END - END w_mask_in[333] - PIN w_mask_in[334] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.010 0.460 158.470 ; - END - END w_mask_in[334] - PIN w_mask_in[335] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.470 0.460 158.930 ; - END - END w_mask_in[335] - PIN w_mask_in[336] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.930 0.460 159.390 ; - END - END w_mask_in[336] - PIN w_mask_in[337] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 159.390 0.460 159.850 ; - END - END w_mask_in[337] - PIN w_mask_in[338] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 159.850 0.460 160.310 ; - END - END w_mask_in[338] - PIN w_mask_in[339] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 160.310 0.460 160.770 ; - END - END w_mask_in[339] - PIN w_mask_in[340] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 160.770 0.460 161.230 ; - END - END w_mask_in[340] - PIN w_mask_in[341] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 161.230 0.460 161.690 ; - END - END w_mask_in[341] - PIN w_mask_in[342] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 161.690 0.460 162.150 ; - END - END w_mask_in[342] - PIN w_mask_in[343] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 162.150 0.460 162.610 ; - END - END w_mask_in[343] - PIN w_mask_in[344] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 162.610 0.460 163.070 ; - END - END w_mask_in[344] - PIN w_mask_in[345] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 163.070 0.460 163.530 ; - END - END w_mask_in[345] - PIN w_mask_in[346] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 163.530 0.460 163.990 ; - END - END w_mask_in[346] - PIN w_mask_in[347] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 163.990 0.460 164.450 ; - END - END w_mask_in[347] - PIN w_mask_in[348] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 164.450 0.460 164.910 ; - END - END w_mask_in[348] - PIN w_mask_in[349] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 164.910 0.460 165.370 ; - END - END w_mask_in[349] - PIN w_mask_in[350] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 165.370 0.460 165.830 ; - END - END w_mask_in[350] - PIN w_mask_in[351] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 165.830 0.460 166.290 ; - END - END w_mask_in[351] - PIN w_mask_in[352] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 166.290 0.460 166.750 ; - END - END w_mask_in[352] - PIN w_mask_in[353] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 166.750 0.460 167.210 ; - END - END w_mask_in[353] - PIN w_mask_in[354] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 167.210 0.460 167.670 ; - END - END w_mask_in[354] - PIN w_mask_in[355] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 167.670 0.460 168.130 ; - END - END w_mask_in[355] - PIN w_mask_in[356] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 168.130 0.460 168.590 ; - END - END w_mask_in[356] - PIN w_mask_in[357] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 168.590 0.460 169.050 ; - END - END w_mask_in[357] - PIN w_mask_in[358] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.050 0.460 169.510 ; - END - END w_mask_in[358] - PIN w_mask_in[359] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.510 0.460 169.970 ; - END - END w_mask_in[359] - PIN w_mask_in[360] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.970 0.460 170.430 ; - END - END w_mask_in[360] - PIN w_mask_in[361] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 170.430 0.460 170.890 ; - END - END w_mask_in[361] - PIN w_mask_in[362] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 170.890 0.460 171.350 ; - END - END w_mask_in[362] - PIN w_mask_in[363] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 171.350 0.460 171.810 ; - END - END w_mask_in[363] - PIN w_mask_in[364] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 171.810 0.460 172.270 ; - END - END w_mask_in[364] - PIN w_mask_in[365] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 172.270 0.460 172.730 ; - END - END w_mask_in[365] - PIN w_mask_in[366] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 172.730 0.460 173.190 ; - END - END w_mask_in[366] - PIN w_mask_in[367] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 173.190 0.460 173.650 ; - END - END w_mask_in[367] - PIN w_mask_in[368] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 173.650 0.460 174.110 ; - END - END w_mask_in[368] - PIN w_mask_in[369] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 174.110 0.460 174.570 ; - END - END w_mask_in[369] - PIN w_mask_in[370] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 174.570 0.460 175.030 ; - END - END w_mask_in[370] - PIN w_mask_in[371] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 175.030 0.460 175.490 ; - END - END w_mask_in[371] - PIN w_mask_in[372] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 175.490 0.460 175.950 ; - END - END w_mask_in[372] - PIN w_mask_in[373] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 175.950 0.460 176.410 ; - END - END w_mask_in[373] - PIN w_mask_in[374] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 176.410 0.460 176.870 ; - END - END w_mask_in[374] - PIN w_mask_in[375] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 176.870 0.460 177.330 ; - END - END w_mask_in[375] - PIN w_mask_in[376] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 177.330 0.460 177.790 ; - END - END w_mask_in[376] - PIN w_mask_in[377] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 177.790 0.460 178.250 ; - END - END w_mask_in[377] - PIN w_mask_in[378] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 178.250 0.460 178.710 ; - END - END w_mask_in[378] - PIN w_mask_in[379] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 178.710 0.460 179.170 ; - END - END w_mask_in[379] - PIN w_mask_in[380] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 179.170 0.460 179.630 ; - END - END w_mask_in[380] - PIN w_mask_in[381] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 179.630 0.460 180.090 ; - END - END w_mask_in[381] - PIN w_mask_in[382] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 180.090 0.460 180.550 ; - END - END w_mask_in[382] - PIN w_mask_in[383] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 180.550 0.460 181.010 ; - END - END w_mask_in[383] - PIN w_mask_in[384] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.010 0.460 181.470 ; - END - END w_mask_in[384] - PIN w_mask_in[385] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.470 0.460 181.930 ; - END - END w_mask_in[385] - PIN w_mask_in[386] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.930 0.460 182.390 ; - END - END w_mask_in[386] - PIN w_mask_in[387] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 182.390 0.460 182.850 ; - END - END w_mask_in[387] - PIN w_mask_in[388] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 182.850 0.460 183.310 ; - END - END w_mask_in[388] - PIN w_mask_in[389] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 183.310 0.460 183.770 ; - END - END w_mask_in[389] - PIN w_mask_in[390] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 183.770 0.460 184.230 ; - END - END w_mask_in[390] - PIN w_mask_in[391] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 184.230 0.460 184.690 ; - END - END w_mask_in[391] - PIN w_mask_in[392] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 184.690 0.460 185.150 ; - END - END w_mask_in[392] - PIN w_mask_in[393] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 185.150 0.460 185.610 ; - END - END w_mask_in[393] - PIN w_mask_in[394] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 185.610 0.460 186.070 ; - END - END w_mask_in[394] - PIN w_mask_in[395] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 186.070 0.460 186.530 ; - END - END w_mask_in[395] - PIN w_mask_in[396] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 186.530 0.460 186.990 ; - END - END w_mask_in[396] - PIN w_mask_in[397] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 186.990 0.460 187.450 ; - END - END w_mask_in[397] - PIN w_mask_in[398] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 187.450 0.460 187.910 ; - END - END w_mask_in[398] - PIN w_mask_in[399] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 187.910 0.460 188.370 ; - END - END w_mask_in[399] - PIN w_mask_in[400] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 188.370 0.460 188.830 ; - END - END w_mask_in[400] - PIN w_mask_in[401] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 188.830 0.460 189.290 ; - END - END w_mask_in[401] - PIN w_mask_in[402] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 189.290 0.460 189.750 ; - END - END w_mask_in[402] - PIN w_mask_in[403] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 189.750 0.460 190.210 ; - END - END w_mask_in[403] - PIN w_mask_in[404] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 190.210 0.460 190.670 ; - END - END w_mask_in[404] - PIN w_mask_in[405] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 190.670 0.460 191.130 ; - END - END w_mask_in[405] - PIN w_mask_in[406] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 191.130 0.460 191.590 ; - END - END w_mask_in[406] - PIN w_mask_in[407] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 191.590 0.460 192.050 ; - END - END w_mask_in[407] - PIN w_mask_in[408] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 192.050 0.460 192.510 ; - END - END w_mask_in[408] - PIN w_mask_in[409] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 192.510 0.460 192.970 ; - END - END w_mask_in[409] - PIN w_mask_in[410] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 192.970 0.460 193.430 ; - END - END w_mask_in[410] - PIN w_mask_in[411] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 193.430 0.460 193.890 ; - END - END w_mask_in[411] - PIN w_mask_in[412] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 193.890 0.460 194.350 ; - END - END w_mask_in[412] - PIN w_mask_in[413] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 194.350 0.460 194.810 ; - END - END w_mask_in[413] - PIN w_mask_in[414] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 194.810 0.460 195.270 ; - END - END w_mask_in[414] - PIN w_mask_in[415] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 195.270 0.460 195.730 ; - END - END w_mask_in[415] - PIN w_mask_in[416] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 195.730 0.460 196.190 ; - END - END w_mask_in[416] - PIN w_mask_in[417] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 196.190 0.460 196.650 ; - END - END w_mask_in[417] - PIN w_mask_in[418] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 196.650 0.460 197.110 ; - END - END w_mask_in[418] - PIN w_mask_in[419] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 197.110 0.460 197.570 ; - END - END w_mask_in[419] - PIN w_mask_in[420] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 197.570 0.460 198.030 ; - END - END w_mask_in[420] - PIN w_mask_in[421] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 198.030 0.460 198.490 ; - END - END w_mask_in[421] - PIN w_mask_in[422] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 198.490 0.460 198.950 ; - END - END w_mask_in[422] - PIN w_mask_in[423] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 198.950 0.460 199.410 ; - END - END w_mask_in[423] - PIN w_mask_in[424] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 199.410 0.460 199.870 ; - END - END w_mask_in[424] - PIN w_mask_in[425] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 199.870 0.460 200.330 ; - END - END w_mask_in[425] - PIN w_mask_in[426] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 200.330 0.460 200.790 ; - END - END w_mask_in[426] - PIN w_mask_in[427] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 200.790 0.460 201.250 ; - END - END w_mask_in[427] - PIN w_mask_in[428] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 201.250 0.460 201.710 ; - END - END w_mask_in[428] - PIN w_mask_in[429] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 201.710 0.460 202.170 ; - END - END w_mask_in[429] - PIN w_mask_in[430] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 202.170 0.460 202.630 ; - END - END w_mask_in[430] - PIN w_mask_in[431] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 202.630 0.460 203.090 ; - END - END w_mask_in[431] - PIN w_mask_in[432] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 203.090 0.460 203.550 ; - END - END w_mask_in[432] - PIN w_mask_in[433] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 203.550 0.460 204.010 ; - END - END w_mask_in[433] - PIN w_mask_in[434] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 204.010 0.460 204.470 ; - END - END w_mask_in[434] - PIN w_mask_in[435] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 204.470 0.460 204.930 ; - END - END w_mask_in[435] - PIN w_mask_in[436] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 204.930 0.460 205.390 ; - END - END w_mask_in[436] - PIN w_mask_in[437] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 205.390 0.460 205.850 ; - END - END w_mask_in[437] - PIN w_mask_in[438] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 205.850 0.460 206.310 ; - END - END w_mask_in[438] - PIN w_mask_in[439] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 206.310 0.460 206.770 ; - END - END w_mask_in[439] - PIN w_mask_in[440] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 206.770 0.460 207.230 ; - END - END w_mask_in[440] - PIN w_mask_in[441] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 207.230 0.460 207.690 ; - END - END w_mask_in[441] - PIN w_mask_in[442] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 207.690 0.460 208.150 ; - END - END w_mask_in[442] - PIN w_mask_in[443] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 208.150 0.460 208.610 ; - END - END w_mask_in[443] - PIN w_mask_in[444] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 208.610 0.460 209.070 ; - END - END w_mask_in[444] - PIN w_mask_in[445] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 209.070 0.460 209.530 ; - END - END w_mask_in[445] - PIN w_mask_in[446] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 209.530 0.460 209.990 ; - END - END w_mask_in[446] - PIN w_mask_in[447] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 209.990 0.460 210.450 ; - END - END w_mask_in[447] - PIN w_mask_in[448] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 210.450 0.460 210.910 ; - END - END w_mask_in[448] - PIN w_mask_in[449] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 210.910 0.460 211.370 ; - END - END w_mask_in[449] - PIN w_mask_in[450] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 211.370 0.460 211.830 ; - END - END w_mask_in[450] - PIN w_mask_in[451] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 211.830 0.460 212.290 ; - END - END w_mask_in[451] - PIN w_mask_in[452] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 212.290 0.460 212.750 ; - END - END w_mask_in[452] - PIN w_mask_in[453] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 212.750 0.460 213.210 ; - END - END w_mask_in[453] - PIN w_mask_in[454] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 213.210 0.460 213.670 ; - END - END w_mask_in[454] - PIN w_mask_in[455] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 213.670 0.460 214.130 ; - END - END w_mask_in[455] - PIN w_mask_in[456] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 214.130 0.460 214.590 ; - END - END w_mask_in[456] - PIN w_mask_in[457] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 214.590 0.460 215.050 ; - END - END w_mask_in[457] - PIN w_mask_in[458] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 215.050 0.460 215.510 ; - END - END w_mask_in[458] - PIN w_mask_in[459] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 215.510 0.460 215.970 ; - END - END w_mask_in[459] - PIN w_mask_in[460] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 215.970 0.460 216.430 ; - END - END w_mask_in[460] - PIN w_mask_in[461] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 216.430 0.460 216.890 ; - END - END w_mask_in[461] - PIN w_mask_in[462] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 216.890 0.460 217.350 ; - END - END w_mask_in[462] - PIN w_mask_in[463] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 217.350 0.460 217.810 ; - END - END w_mask_in[463] - PIN w_mask_in[464] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 217.810 0.460 218.270 ; - END - END w_mask_in[464] - PIN w_mask_in[465] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 218.270 0.460 218.730 ; - END - END w_mask_in[465] - PIN w_mask_in[466] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 218.730 0.460 219.190 ; - END - END w_mask_in[466] - PIN w_mask_in[467] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 219.190 0.460 219.650 ; - END - END w_mask_in[467] - PIN w_mask_in[468] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 219.650 0.460 220.110 ; - END - END w_mask_in[468] - PIN w_mask_in[469] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 220.110 0.460 220.570 ; - END - END w_mask_in[469] - PIN w_mask_in[470] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 220.570 0.460 221.030 ; - END - END w_mask_in[470] - PIN w_mask_in[471] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 221.030 0.460 221.490 ; - END - END w_mask_in[471] - PIN w_mask_in[472] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 221.490 0.460 221.950 ; - END - END w_mask_in[472] - PIN w_mask_in[473] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 221.950 0.460 222.410 ; - END - END w_mask_in[473] - PIN w_mask_in[474] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 222.410 0.460 222.870 ; - END - END w_mask_in[474] - PIN w_mask_in[475] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 222.870 0.460 223.330 ; - END - END w_mask_in[475] - PIN w_mask_in[476] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 223.330 0.460 223.790 ; - END - END w_mask_in[476] - PIN w_mask_in[477] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 223.790 0.460 224.250 ; - END - END w_mask_in[477] - PIN w_mask_in[478] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 224.250 0.460 224.710 ; - END - END w_mask_in[478] - PIN w_mask_in[479] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 224.710 0.460 225.170 ; - END - END w_mask_in[479] - PIN w_mask_in[480] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 225.170 0.460 225.630 ; - END - END w_mask_in[480] - PIN w_mask_in[481] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 225.630 0.460 226.090 ; - END - END w_mask_in[481] - PIN w_mask_in[482] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 226.090 0.460 226.550 ; - END - END w_mask_in[482] - PIN w_mask_in[483] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 226.550 0.460 227.010 ; - END - END w_mask_in[483] - PIN w_mask_in[484] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 227.010 0.460 227.470 ; - END - END w_mask_in[484] - PIN w_mask_in[485] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 227.470 0.460 227.930 ; - END - END w_mask_in[485] - PIN w_mask_in[486] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 227.930 0.460 228.390 ; - END - END w_mask_in[486] - PIN w_mask_in[487] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 228.390 0.460 228.850 ; - END - END w_mask_in[487] - PIN w_mask_in[488] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 228.850 0.460 229.310 ; - END - END w_mask_in[488] - PIN w_mask_in[489] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 229.310 0.460 229.770 ; - END - END w_mask_in[489] - PIN w_mask_in[490] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 229.770 0.460 230.230 ; - END - END w_mask_in[490] - PIN w_mask_in[491] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 230.230 0.460 230.690 ; - END - END w_mask_in[491] - PIN w_mask_in[492] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 230.690 0.460 231.150 ; - END - END w_mask_in[492] - PIN w_mask_in[493] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 231.150 0.460 231.610 ; - END - END w_mask_in[493] - PIN w_mask_in[494] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 231.610 0.460 232.070 ; - END - END w_mask_in[494] - PIN w_mask_in[495] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 232.070 0.460 232.530 ; - END - END w_mask_in[495] - PIN w_mask_in[496] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 232.530 0.460 232.990 ; - END - END w_mask_in[496] - PIN w_mask_in[497] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 232.990 0.460 233.450 ; - END - END w_mask_in[497] - PIN w_mask_in[498] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 233.450 0.460 233.910 ; - END - END w_mask_in[498] - PIN w_mask_in[499] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 233.910 0.460 234.370 ; - END - END w_mask_in[499] - PIN w_mask_in[500] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 234.370 0.460 234.830 ; - END - END w_mask_in[500] - PIN w_mask_in[501] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 234.830 0.460 235.290 ; - END - END w_mask_in[501] - PIN w_mask_in[502] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 235.290 0.460 235.750 ; - END - END w_mask_in[502] - PIN w_mask_in[503] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 235.750 0.460 236.210 ; - END - END w_mask_in[503] - PIN w_mask_in[504] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 236.210 0.460 236.670 ; - END - END w_mask_in[504] - PIN w_mask_in[505] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 236.670 0.460 237.130 ; - END - END w_mask_in[505] - PIN w_mask_in[506] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 237.130 0.460 237.590 ; - END - END w_mask_in[506] - PIN w_mask_in[507] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 237.590 0.460 238.050 ; - END - END w_mask_in[507] - PIN w_mask_in[508] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 238.050 0.460 238.510 ; - END - END w_mask_in[508] - PIN w_mask_in[509] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 238.510 0.460 238.970 ; - END - END w_mask_in[509] - PIN w_mask_in[510] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 238.970 0.460 239.430 ; - END - END w_mask_in[510] - PIN w_mask_in[511] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 239.430 0.460 239.890 ; - END - END w_mask_in[511] - PIN rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 322.230 0.460 322.690 ; - END - END rd_out[0] - PIN rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 322.690 0.460 323.150 ; - END - END rd_out[1] - PIN rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 323.150 0.460 323.610 ; - END - END rd_out[2] - PIN rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 323.610 0.460 324.070 ; - END - END rd_out[3] - PIN rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 324.070 0.460 324.530 ; - END - END rd_out[4] - PIN rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 324.530 0.460 324.990 ; - END - END rd_out[5] - PIN rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 324.990 0.460 325.450 ; - END - END rd_out[6] - PIN rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 325.450 0.460 325.910 ; - END - END rd_out[7] - PIN rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 325.910 0.460 326.370 ; - END - END rd_out[8] - PIN rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 326.370 0.460 326.830 ; - END - END rd_out[9] - PIN rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 326.830 0.460 327.290 ; - END - END rd_out[10] - PIN rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 327.290 0.460 327.750 ; - END - END rd_out[11] - PIN rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 327.750 0.460 328.210 ; - END - END rd_out[12] - PIN rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 328.210 0.460 328.670 ; - END - END rd_out[13] - PIN rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 328.670 0.460 329.130 ; - END - END rd_out[14] - PIN rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 329.130 0.460 329.590 ; - END - END rd_out[15] - PIN rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 329.590 0.460 330.050 ; - END - END rd_out[16] - PIN rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 330.050 0.460 330.510 ; - END - END rd_out[17] - PIN rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 330.510 0.460 330.970 ; - END - END rd_out[18] - PIN rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 330.970 0.460 331.430 ; - END - END rd_out[19] - PIN rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 331.430 0.460 331.890 ; - END - END rd_out[20] - PIN rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 331.890 0.460 332.350 ; - END - END rd_out[21] - PIN rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 332.350 0.460 332.810 ; - END - END rd_out[22] - PIN rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 332.810 0.460 333.270 ; - END - END rd_out[23] - PIN rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 333.270 0.460 333.730 ; - END - END rd_out[24] - PIN rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 333.730 0.460 334.190 ; - END - END rd_out[25] - PIN rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 334.190 0.460 334.650 ; - END - END rd_out[26] - PIN rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 334.650 0.460 335.110 ; - END - END rd_out[27] - PIN rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 335.110 0.460 335.570 ; - END - END rd_out[28] - PIN rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 335.570 0.460 336.030 ; - END - END rd_out[29] - PIN rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 336.030 0.460 336.490 ; - END - END rd_out[30] - PIN rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 336.490 0.460 336.950 ; - END - END rd_out[31] - PIN rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 336.950 0.460 337.410 ; - END - END rd_out[32] - PIN rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 337.410 0.460 337.870 ; - END - END rd_out[33] - PIN rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 337.870 0.460 338.330 ; - END - END rd_out[34] - PIN rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 338.330 0.460 338.790 ; - END - END rd_out[35] - PIN rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 338.790 0.460 339.250 ; - END - END rd_out[36] - PIN rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 339.250 0.460 339.710 ; - END - END rd_out[37] - PIN rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 339.710 0.460 340.170 ; - END - END rd_out[38] - PIN rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 340.170 0.460 340.630 ; - END - END rd_out[39] - PIN rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 340.630 0.460 341.090 ; - END - END rd_out[40] - PIN rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 341.090 0.460 341.550 ; - END - END rd_out[41] - PIN rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 341.550 0.460 342.010 ; - END - END rd_out[42] - PIN rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 342.010 0.460 342.470 ; - END - END rd_out[43] - PIN rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 342.470 0.460 342.930 ; - END - END rd_out[44] - PIN rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 342.930 0.460 343.390 ; - END - END rd_out[45] - PIN rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 343.390 0.460 343.850 ; - END - END rd_out[46] - PIN rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 343.850 0.460 344.310 ; - END - END rd_out[47] - PIN rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 344.310 0.460 344.770 ; - END - END rd_out[48] - PIN rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 344.770 0.460 345.230 ; - END - END rd_out[49] - PIN rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 345.230 0.460 345.690 ; - END - END rd_out[50] - PIN rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 345.690 0.460 346.150 ; - END - END rd_out[51] - PIN rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 346.150 0.460 346.610 ; - END - END rd_out[52] - PIN rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 346.610 0.460 347.070 ; - END - END rd_out[53] - PIN rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 347.070 0.460 347.530 ; - END - END rd_out[54] - PIN rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 347.530 0.460 347.990 ; - END - END rd_out[55] - PIN rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 347.990 0.460 348.450 ; - END - END rd_out[56] - PIN rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 348.450 0.460 348.910 ; - END - END rd_out[57] - PIN rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 348.910 0.460 349.370 ; - END - END rd_out[58] - PIN rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 349.370 0.460 349.830 ; - END - END rd_out[59] - PIN rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 349.830 0.460 350.290 ; - END - END rd_out[60] - PIN rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 350.290 0.460 350.750 ; - END - END rd_out[61] - PIN rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 350.750 0.460 351.210 ; - END - END rd_out[62] - PIN rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 351.210 0.460 351.670 ; - END - END rd_out[63] - PIN rd_out[64] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 351.670 0.460 352.130 ; - END - END rd_out[64] - PIN rd_out[65] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 352.130 0.460 352.590 ; - END - END rd_out[65] - PIN rd_out[66] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 352.590 0.460 353.050 ; - END - END rd_out[66] - PIN rd_out[67] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 353.050 0.460 353.510 ; - END - END rd_out[67] - PIN rd_out[68] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 353.510 0.460 353.970 ; - END - END rd_out[68] - PIN rd_out[69] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 353.970 0.460 354.430 ; - END - END rd_out[69] - PIN rd_out[70] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 354.430 0.460 354.890 ; - END - END rd_out[70] - PIN rd_out[71] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 354.890 0.460 355.350 ; - END - END rd_out[71] - PIN rd_out[72] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 355.350 0.460 355.810 ; - END - END rd_out[72] - PIN rd_out[73] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 355.810 0.460 356.270 ; - END - END rd_out[73] - PIN rd_out[74] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 356.270 0.460 356.730 ; - END - END rd_out[74] - PIN rd_out[75] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 356.730 0.460 357.190 ; - END - END rd_out[75] - PIN rd_out[76] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 357.190 0.460 357.650 ; - END - END rd_out[76] - PIN rd_out[77] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 357.650 0.460 358.110 ; - END - END rd_out[77] - PIN rd_out[78] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 358.110 0.460 358.570 ; - END - END rd_out[78] - PIN rd_out[79] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 358.570 0.460 359.030 ; - END - END rd_out[79] - PIN rd_out[80] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 359.030 0.460 359.490 ; - END - END rd_out[80] - PIN rd_out[81] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 359.490 0.460 359.950 ; - END - END rd_out[81] - PIN rd_out[82] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 359.950 0.460 360.410 ; - END - END rd_out[82] - PIN rd_out[83] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 360.410 0.460 360.870 ; - END - END rd_out[83] - PIN rd_out[84] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 360.870 0.460 361.330 ; - END - END rd_out[84] - PIN rd_out[85] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 361.330 0.460 361.790 ; - END - END rd_out[85] - PIN rd_out[86] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 361.790 0.460 362.250 ; - END - END rd_out[86] - PIN rd_out[87] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 362.250 0.460 362.710 ; - END - END rd_out[87] - PIN rd_out[88] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 362.710 0.460 363.170 ; - END - END rd_out[88] - PIN rd_out[89] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 363.170 0.460 363.630 ; - END - END rd_out[89] - PIN rd_out[90] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 363.630 0.460 364.090 ; - END - END rd_out[90] - PIN rd_out[91] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 364.090 0.460 364.550 ; - END - END rd_out[91] - PIN rd_out[92] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 364.550 0.460 365.010 ; - END - END rd_out[92] - PIN rd_out[93] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 365.010 0.460 365.470 ; - END - END rd_out[93] - PIN rd_out[94] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 365.470 0.460 365.930 ; - END - END rd_out[94] - PIN rd_out[95] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 365.930 0.460 366.390 ; - END - END rd_out[95] - PIN rd_out[96] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 366.390 0.460 366.850 ; - END - END rd_out[96] - PIN rd_out[97] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 366.850 0.460 367.310 ; - END - END rd_out[97] - PIN rd_out[98] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 367.310 0.460 367.770 ; - END - END rd_out[98] - PIN rd_out[99] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 367.770 0.460 368.230 ; - END - END rd_out[99] - PIN rd_out[100] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 368.230 0.460 368.690 ; - END - END rd_out[100] - PIN rd_out[101] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 368.690 0.460 369.150 ; - END - END rd_out[101] - PIN rd_out[102] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 369.150 0.460 369.610 ; - END - END rd_out[102] - PIN rd_out[103] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 369.610 0.460 370.070 ; - END - END rd_out[103] - PIN rd_out[104] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 370.070 0.460 370.530 ; - END - END rd_out[104] - PIN rd_out[105] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 370.530 0.460 370.990 ; - END - END rd_out[105] - PIN rd_out[106] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 370.990 0.460 371.450 ; - END - END rd_out[106] - PIN rd_out[107] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 371.450 0.460 371.910 ; - END - END rd_out[107] - PIN rd_out[108] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 371.910 0.460 372.370 ; - END - END rd_out[108] - PIN rd_out[109] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 372.370 0.460 372.830 ; - END - END rd_out[109] - PIN rd_out[110] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 372.830 0.460 373.290 ; - END - END rd_out[110] - PIN rd_out[111] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 373.290 0.460 373.750 ; - END - END rd_out[111] - PIN rd_out[112] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 373.750 0.460 374.210 ; - END - END rd_out[112] - PIN rd_out[113] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 374.210 0.460 374.670 ; - END - END rd_out[113] - PIN rd_out[114] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 374.670 0.460 375.130 ; - END - END rd_out[114] - PIN rd_out[115] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 375.130 0.460 375.590 ; - END - END rd_out[115] - PIN rd_out[116] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 375.590 0.460 376.050 ; - END - END rd_out[116] - PIN rd_out[117] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 376.050 0.460 376.510 ; - END - END rd_out[117] - PIN rd_out[118] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 376.510 0.460 376.970 ; - END - END rd_out[118] - PIN rd_out[119] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 376.970 0.460 377.430 ; - END - END rd_out[119] - PIN rd_out[120] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 377.430 0.460 377.890 ; - END - END rd_out[120] - PIN rd_out[121] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 377.890 0.460 378.350 ; - END - END rd_out[121] - PIN rd_out[122] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 378.350 0.460 378.810 ; - END - END rd_out[122] - PIN rd_out[123] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 378.810 0.460 379.270 ; - END - END rd_out[123] - PIN rd_out[124] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 379.270 0.460 379.730 ; - END - END rd_out[124] - PIN rd_out[125] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 379.730 0.460 380.190 ; - END - END rd_out[125] - PIN rd_out[126] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 380.190 0.460 380.650 ; - END - END rd_out[126] - PIN rd_out[127] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 380.650 0.460 381.110 ; - END - END rd_out[127] - PIN rd_out[128] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 381.110 0.460 381.570 ; - END - END rd_out[128] - PIN rd_out[129] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 381.570 0.460 382.030 ; - END - END rd_out[129] - PIN rd_out[130] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 382.030 0.460 382.490 ; - END - END rd_out[130] - PIN rd_out[131] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 382.490 0.460 382.950 ; - END - END rd_out[131] - PIN rd_out[132] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 382.950 0.460 383.410 ; - END - END rd_out[132] - PIN rd_out[133] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 383.410 0.460 383.870 ; - END - END rd_out[133] - PIN rd_out[134] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 383.870 0.460 384.330 ; - END - END rd_out[134] - PIN rd_out[135] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 384.330 0.460 384.790 ; - END - END rd_out[135] - PIN rd_out[136] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 384.790 0.460 385.250 ; - END - END rd_out[136] - PIN rd_out[137] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 385.250 0.460 385.710 ; - END - END rd_out[137] - PIN rd_out[138] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 385.710 0.460 386.170 ; - END - END rd_out[138] - PIN rd_out[139] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 386.170 0.460 386.630 ; - END - END rd_out[139] - PIN rd_out[140] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 386.630 0.460 387.090 ; - END - END rd_out[140] - PIN rd_out[141] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 387.090 0.460 387.550 ; - END - END rd_out[141] - PIN rd_out[142] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 387.550 0.460 388.010 ; - END - END rd_out[142] - PIN rd_out[143] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 388.010 0.460 388.470 ; - END - END rd_out[143] - PIN rd_out[144] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 388.470 0.460 388.930 ; - END - END rd_out[144] - PIN rd_out[145] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 388.930 0.460 389.390 ; - END - END rd_out[145] - PIN rd_out[146] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 389.390 0.460 389.850 ; - END - END rd_out[146] - PIN rd_out[147] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 389.850 0.460 390.310 ; - END - END rd_out[147] - PIN rd_out[148] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 390.310 0.460 390.770 ; - END - END rd_out[148] - PIN rd_out[149] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 390.770 0.460 391.230 ; - END - END rd_out[149] - PIN rd_out[150] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 391.230 0.460 391.690 ; - END - END rd_out[150] - PIN rd_out[151] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 391.690 0.460 392.150 ; - END - END rd_out[151] - PIN rd_out[152] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 392.150 0.460 392.610 ; - END - END rd_out[152] - PIN rd_out[153] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 392.610 0.460 393.070 ; - END - END rd_out[153] - PIN rd_out[154] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 393.070 0.460 393.530 ; - END - END rd_out[154] - PIN rd_out[155] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 393.530 0.460 393.990 ; - END - END rd_out[155] - PIN rd_out[156] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 393.990 0.460 394.450 ; - END - END rd_out[156] - PIN rd_out[157] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 394.450 0.460 394.910 ; - END - END rd_out[157] - PIN rd_out[158] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 394.910 0.460 395.370 ; - END - END rd_out[158] - PIN rd_out[159] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 395.370 0.460 395.830 ; - END - END rd_out[159] - PIN rd_out[160] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 395.830 0.460 396.290 ; - END - END rd_out[160] - PIN rd_out[161] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 396.290 0.460 396.750 ; - END - END rd_out[161] - PIN rd_out[162] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 396.750 0.460 397.210 ; - END - END rd_out[162] - PIN rd_out[163] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 397.210 0.460 397.670 ; - END - END rd_out[163] - PIN rd_out[164] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 397.670 0.460 398.130 ; - END - END rd_out[164] - PIN rd_out[165] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 398.130 0.460 398.590 ; - END - END rd_out[165] - PIN rd_out[166] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 398.590 0.460 399.050 ; - END - END rd_out[166] - PIN rd_out[167] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 399.050 0.460 399.510 ; - END - END rd_out[167] - PIN rd_out[168] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 399.510 0.460 399.970 ; - END - END rd_out[168] - PIN rd_out[169] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 399.970 0.460 400.430 ; - END - END rd_out[169] - PIN rd_out[170] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 400.430 0.460 400.890 ; - END - END rd_out[170] - PIN rd_out[171] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 400.890 0.460 401.350 ; - END - END rd_out[171] - PIN rd_out[172] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 401.350 0.460 401.810 ; - END - END rd_out[172] - PIN rd_out[173] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 401.810 0.460 402.270 ; - END - END rd_out[173] - PIN rd_out[174] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 402.270 0.460 402.730 ; - END - END rd_out[174] - PIN rd_out[175] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 402.730 0.460 403.190 ; - END - END rd_out[175] - PIN rd_out[176] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 403.190 0.460 403.650 ; - END - END rd_out[176] - PIN rd_out[177] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 403.650 0.460 404.110 ; - END - END rd_out[177] - PIN rd_out[178] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 404.110 0.460 404.570 ; - END - END rd_out[178] - PIN rd_out[179] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 404.570 0.460 405.030 ; - END - END rd_out[179] - PIN rd_out[180] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 405.030 0.460 405.490 ; - END - END rd_out[180] - PIN rd_out[181] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 405.490 0.460 405.950 ; - END - END rd_out[181] - PIN rd_out[182] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 405.950 0.460 406.410 ; - END - END rd_out[182] - PIN rd_out[183] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 406.410 0.460 406.870 ; - END - END rd_out[183] - PIN rd_out[184] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 406.870 0.460 407.330 ; - END - END rd_out[184] - PIN rd_out[185] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 407.330 0.460 407.790 ; - END - END rd_out[185] - PIN rd_out[186] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 407.790 0.460 408.250 ; - END - END rd_out[186] - PIN rd_out[187] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 408.250 0.460 408.710 ; - END - END rd_out[187] - PIN rd_out[188] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 408.710 0.460 409.170 ; - END - END rd_out[188] - PIN rd_out[189] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 409.170 0.460 409.630 ; - END - END rd_out[189] - PIN rd_out[190] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 409.630 0.460 410.090 ; - END - END rd_out[190] - PIN rd_out[191] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 410.090 0.460 410.550 ; - END - END rd_out[191] - PIN rd_out[192] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 410.550 0.460 411.010 ; - END - END rd_out[192] - PIN rd_out[193] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 411.010 0.460 411.470 ; - END - END rd_out[193] - PIN rd_out[194] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 411.470 0.460 411.930 ; - END - END rd_out[194] - PIN rd_out[195] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 411.930 0.460 412.390 ; - END - END rd_out[195] - PIN rd_out[196] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 412.390 0.460 412.850 ; - END - END rd_out[196] - PIN rd_out[197] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 412.850 0.460 413.310 ; - END - END rd_out[197] - PIN rd_out[198] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 413.310 0.460 413.770 ; - END - END rd_out[198] - PIN rd_out[199] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 413.770 0.460 414.230 ; - END - END rd_out[199] - PIN rd_out[200] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 414.230 0.460 414.690 ; - END - END rd_out[200] - PIN rd_out[201] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 414.690 0.460 415.150 ; - END - END rd_out[201] - PIN rd_out[202] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 415.150 0.460 415.610 ; - END - END rd_out[202] - PIN rd_out[203] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 415.610 0.460 416.070 ; - END - END rd_out[203] - PIN rd_out[204] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 416.070 0.460 416.530 ; - END - END rd_out[204] - PIN rd_out[205] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 416.530 0.460 416.990 ; - END - END rd_out[205] - PIN rd_out[206] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 416.990 0.460 417.450 ; - END - END rd_out[206] - PIN rd_out[207] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 417.450 0.460 417.910 ; - END - END rd_out[207] - PIN rd_out[208] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 417.910 0.460 418.370 ; - END - END rd_out[208] - PIN rd_out[209] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 418.370 0.460 418.830 ; - END - END rd_out[209] - PIN rd_out[210] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 418.830 0.460 419.290 ; - END - END rd_out[210] - PIN rd_out[211] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 419.290 0.460 419.750 ; - END - END rd_out[211] - PIN rd_out[212] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 419.750 0.460 420.210 ; - END - END rd_out[212] - PIN rd_out[213] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 420.210 0.460 420.670 ; - END - END rd_out[213] - PIN rd_out[214] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 420.670 0.460 421.130 ; - END - END rd_out[214] - PIN rd_out[215] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 421.130 0.460 421.590 ; - END - END rd_out[215] - PIN rd_out[216] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 421.590 0.460 422.050 ; - END - END rd_out[216] - PIN rd_out[217] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 422.050 0.460 422.510 ; - END - END rd_out[217] - PIN rd_out[218] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 422.510 0.460 422.970 ; - END - END rd_out[218] - PIN rd_out[219] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 422.970 0.460 423.430 ; - END - END rd_out[219] - PIN rd_out[220] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 423.430 0.460 423.890 ; - END - END rd_out[220] - PIN rd_out[221] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 423.890 0.460 424.350 ; - END - END rd_out[221] - PIN rd_out[222] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 424.350 0.460 424.810 ; - END - END rd_out[222] - PIN rd_out[223] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 424.810 0.460 425.270 ; - END - END rd_out[223] - PIN rd_out[224] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 425.270 0.460 425.730 ; - END - END rd_out[224] - PIN rd_out[225] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 425.730 0.460 426.190 ; - END - END rd_out[225] - PIN rd_out[226] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 426.190 0.460 426.650 ; - END - END rd_out[226] - PIN rd_out[227] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 426.650 0.460 427.110 ; - END - END rd_out[227] - PIN rd_out[228] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 427.110 0.460 427.570 ; - END - END rd_out[228] - PIN rd_out[229] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 427.570 0.460 428.030 ; - END - END rd_out[229] - PIN rd_out[230] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 428.030 0.460 428.490 ; - END - END rd_out[230] - PIN rd_out[231] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 428.490 0.460 428.950 ; - END - END rd_out[231] - PIN rd_out[232] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 428.950 0.460 429.410 ; - END - END rd_out[232] - PIN rd_out[233] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 429.410 0.460 429.870 ; - END - END rd_out[233] - PIN rd_out[234] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 429.870 0.460 430.330 ; - END - END rd_out[234] - PIN rd_out[235] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 430.330 0.460 430.790 ; - END - END rd_out[235] - PIN rd_out[236] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 430.790 0.460 431.250 ; - END - END rd_out[236] - PIN rd_out[237] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 431.250 0.460 431.710 ; - END - END rd_out[237] - PIN rd_out[238] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 431.710 0.460 432.170 ; - END - END rd_out[238] - PIN rd_out[239] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 432.170 0.460 432.630 ; - END - END rd_out[239] - PIN rd_out[240] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 432.630 0.460 433.090 ; - END - END rd_out[240] - PIN rd_out[241] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 433.090 0.460 433.550 ; - END - END rd_out[241] - PIN rd_out[242] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 433.550 0.460 434.010 ; - END - END rd_out[242] - PIN rd_out[243] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 434.010 0.460 434.470 ; - END - END rd_out[243] - PIN rd_out[244] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 434.470 0.460 434.930 ; - END - END rd_out[244] - PIN rd_out[245] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 434.930 0.460 435.390 ; - END - END rd_out[245] - PIN rd_out[246] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 435.390 0.460 435.850 ; - END - END rd_out[246] - PIN rd_out[247] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 435.850 0.460 436.310 ; - END - END rd_out[247] - PIN rd_out[248] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 436.310 0.460 436.770 ; - END - END rd_out[248] - PIN rd_out[249] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 436.770 0.460 437.230 ; - END - END rd_out[249] - PIN rd_out[250] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 437.230 0.460 437.690 ; - END - END rd_out[250] - PIN rd_out[251] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 437.690 0.460 438.150 ; - END - END rd_out[251] - PIN rd_out[252] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 438.150 0.460 438.610 ; - END - END rd_out[252] - PIN rd_out[253] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 438.610 0.460 439.070 ; - END - END rd_out[253] - PIN rd_out[254] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 439.070 0.460 439.530 ; - END - END rd_out[254] - PIN rd_out[255] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 439.530 0.460 439.990 ; - END - END rd_out[255] - PIN rd_out[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 439.990 0.460 440.450 ; - END - END rd_out[256] - PIN rd_out[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 440.450 0.460 440.910 ; - END - END rd_out[257] - PIN rd_out[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 440.910 0.460 441.370 ; - END - END rd_out[258] - PIN rd_out[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 441.370 0.460 441.830 ; - END - END rd_out[259] - PIN rd_out[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 441.830 0.460 442.290 ; - END - END rd_out[260] - PIN rd_out[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 442.290 0.460 442.750 ; - END - END rd_out[261] - PIN rd_out[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 442.750 0.460 443.210 ; - END - END rd_out[262] - PIN rd_out[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 443.210 0.460 443.670 ; - END - END rd_out[263] - PIN rd_out[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 443.670 0.460 444.130 ; - END - END rd_out[264] - PIN rd_out[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 444.130 0.460 444.590 ; - END - END rd_out[265] - PIN rd_out[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 444.590 0.460 445.050 ; - END - END rd_out[266] - PIN rd_out[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 445.050 0.460 445.510 ; - END - END rd_out[267] - PIN rd_out[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 445.510 0.460 445.970 ; - END - END rd_out[268] - PIN rd_out[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 445.970 0.460 446.430 ; - END - END rd_out[269] - PIN rd_out[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 446.430 0.460 446.890 ; - END - END rd_out[270] - PIN rd_out[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 446.890 0.460 447.350 ; - END - END rd_out[271] - PIN rd_out[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 447.350 0.460 447.810 ; - END - END rd_out[272] - PIN rd_out[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 447.810 0.460 448.270 ; - END - END rd_out[273] - PIN rd_out[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 448.270 0.460 448.730 ; - END - END rd_out[274] - PIN rd_out[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 448.730 0.460 449.190 ; - END - END rd_out[275] - PIN rd_out[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 449.190 0.460 449.650 ; - END - END rd_out[276] - PIN rd_out[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 449.650 0.460 450.110 ; - END - END rd_out[277] - PIN rd_out[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 450.110 0.460 450.570 ; - END - END rd_out[278] - PIN rd_out[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 450.570 0.460 451.030 ; - END - END rd_out[279] - PIN rd_out[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 451.030 0.460 451.490 ; - END - END rd_out[280] - PIN rd_out[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 451.490 0.460 451.950 ; - END - END rd_out[281] - PIN rd_out[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 451.950 0.460 452.410 ; - END - END rd_out[282] - PIN rd_out[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 452.410 0.460 452.870 ; - END - END rd_out[283] - PIN rd_out[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 452.870 0.460 453.330 ; - END - END rd_out[284] - PIN rd_out[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 453.330 0.460 453.790 ; - END - END rd_out[285] - PIN rd_out[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 453.790 0.460 454.250 ; - END - END rd_out[286] - PIN rd_out[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 454.250 0.460 454.710 ; - END - END rd_out[287] - PIN rd_out[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 454.710 0.460 455.170 ; - END - END rd_out[288] - PIN rd_out[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 455.170 0.460 455.630 ; - END - END rd_out[289] - PIN rd_out[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 455.630 0.460 456.090 ; - END - END rd_out[290] - PIN rd_out[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 456.090 0.460 456.550 ; - END - END rd_out[291] - PIN rd_out[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 456.550 0.460 457.010 ; - END - END rd_out[292] - PIN rd_out[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 457.010 0.460 457.470 ; - END - END rd_out[293] - PIN rd_out[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 457.470 0.460 457.930 ; - END - END rd_out[294] - PIN rd_out[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 457.930 0.460 458.390 ; - END - END rd_out[295] - PIN rd_out[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 458.390 0.460 458.850 ; - END - END rd_out[296] - PIN rd_out[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 458.850 0.460 459.310 ; - END - END rd_out[297] - PIN rd_out[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 459.310 0.460 459.770 ; - END - END rd_out[298] - PIN rd_out[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 459.770 0.460 460.230 ; - END - END rd_out[299] - PIN rd_out[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 460.230 0.460 460.690 ; - END - END rd_out[300] - PIN rd_out[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 460.690 0.460 461.150 ; - END - END rd_out[301] - PIN rd_out[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 461.150 0.460 461.610 ; - END - END rd_out[302] - PIN rd_out[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 461.610 0.460 462.070 ; - END - END rd_out[303] - PIN rd_out[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 462.070 0.460 462.530 ; - END - END rd_out[304] - PIN rd_out[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 462.530 0.460 462.990 ; - END - END rd_out[305] - PIN rd_out[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 462.990 0.460 463.450 ; - END - END rd_out[306] - PIN rd_out[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 463.450 0.460 463.910 ; - END - END rd_out[307] - PIN rd_out[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 463.910 0.460 464.370 ; - END - END rd_out[308] - PIN rd_out[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 464.370 0.460 464.830 ; - END - END rd_out[309] - PIN rd_out[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 464.830 0.460 465.290 ; - END - END rd_out[310] - PIN rd_out[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 465.290 0.460 465.750 ; - END - END rd_out[311] - PIN rd_out[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 465.750 0.460 466.210 ; - END - END rd_out[312] - PIN rd_out[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 466.210 0.460 466.670 ; - END - END rd_out[313] - PIN rd_out[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 466.670 0.460 467.130 ; - END - END rd_out[314] - PIN rd_out[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 467.130 0.460 467.590 ; - END - END rd_out[315] - PIN rd_out[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 467.590 0.460 468.050 ; - END - END rd_out[316] - PIN rd_out[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 468.050 0.460 468.510 ; - END - END rd_out[317] - PIN rd_out[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 468.510 0.460 468.970 ; - END - END rd_out[318] - PIN rd_out[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 468.970 0.460 469.430 ; - END - END rd_out[319] - PIN rd_out[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 469.430 0.460 469.890 ; - END - END rd_out[320] - PIN rd_out[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 469.890 0.460 470.350 ; - END - END rd_out[321] - PIN rd_out[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 470.350 0.460 470.810 ; - END - END rd_out[322] - PIN rd_out[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 470.810 0.460 471.270 ; - END - END rd_out[323] - PIN rd_out[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 471.270 0.460 471.730 ; - END - END rd_out[324] - PIN rd_out[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 471.730 0.460 472.190 ; - END - END rd_out[325] - PIN rd_out[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 472.190 0.460 472.650 ; - END - END rd_out[326] - PIN rd_out[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 472.650 0.460 473.110 ; - END - END rd_out[327] - PIN rd_out[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 473.110 0.460 473.570 ; - END - END rd_out[328] - PIN rd_out[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 473.570 0.460 474.030 ; - END - END rd_out[329] - PIN rd_out[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 474.030 0.460 474.490 ; - END - END rd_out[330] - PIN rd_out[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 474.490 0.460 474.950 ; - END - END rd_out[331] - PIN rd_out[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 474.950 0.460 475.410 ; - END - END rd_out[332] - PIN rd_out[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 475.410 0.460 475.870 ; - END - END rd_out[333] - PIN rd_out[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 475.870 0.460 476.330 ; - END - END rd_out[334] - PIN rd_out[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 476.330 0.460 476.790 ; - END - END rd_out[335] - PIN rd_out[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 476.790 0.460 477.250 ; - END - END rd_out[336] - PIN rd_out[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 477.250 0.460 477.710 ; - END - END rd_out[337] - PIN rd_out[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 477.710 0.460 478.170 ; - END - END rd_out[338] - PIN rd_out[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 478.170 0.460 478.630 ; - END - END rd_out[339] - PIN rd_out[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 478.630 0.460 479.090 ; - END - END rd_out[340] - PIN rd_out[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 479.090 0.460 479.550 ; - END - END rd_out[341] - PIN rd_out[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 479.550 0.460 480.010 ; - END - END rd_out[342] - PIN rd_out[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 480.010 0.460 480.470 ; - END - END rd_out[343] - PIN rd_out[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 480.470 0.460 480.930 ; - END - END rd_out[344] - PIN rd_out[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 480.930 0.460 481.390 ; - END - END rd_out[345] - PIN rd_out[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 481.390 0.460 481.850 ; - END - END rd_out[346] - PIN rd_out[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 481.850 0.460 482.310 ; - END - END rd_out[347] - PIN rd_out[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 482.310 0.460 482.770 ; - END - END rd_out[348] - PIN rd_out[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 482.770 0.460 483.230 ; - END - END rd_out[349] - PIN rd_out[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 483.230 0.460 483.690 ; - END - END rd_out[350] - PIN rd_out[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 483.690 0.460 484.150 ; - END - END rd_out[351] - PIN rd_out[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 484.150 0.460 484.610 ; - END - END rd_out[352] - PIN rd_out[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 484.610 0.460 485.070 ; - END - END rd_out[353] - PIN rd_out[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 485.070 0.460 485.530 ; - END - END rd_out[354] - PIN rd_out[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 485.530 0.460 485.990 ; - END - END rd_out[355] - PIN rd_out[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 485.990 0.460 486.450 ; - END - END rd_out[356] - PIN rd_out[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 486.450 0.460 486.910 ; - END - END rd_out[357] - PIN rd_out[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 486.910 0.460 487.370 ; - END - END rd_out[358] - PIN rd_out[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 487.370 0.460 487.830 ; - END - END rd_out[359] - PIN rd_out[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 487.830 0.460 488.290 ; - END - END rd_out[360] - PIN rd_out[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 488.290 0.460 488.750 ; - END - END rd_out[361] - PIN rd_out[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 488.750 0.460 489.210 ; - END - END rd_out[362] - PIN rd_out[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 489.210 0.460 489.670 ; - END - END rd_out[363] - PIN rd_out[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 489.670 0.460 490.130 ; - END - END rd_out[364] - PIN rd_out[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 490.130 0.460 490.590 ; - END - END rd_out[365] - PIN rd_out[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 490.590 0.460 491.050 ; - END - END rd_out[366] - PIN rd_out[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 491.050 0.460 491.510 ; - END - END rd_out[367] - PIN rd_out[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 491.510 0.460 491.970 ; - END - END rd_out[368] - PIN rd_out[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 491.970 0.460 492.430 ; - END - END rd_out[369] - PIN rd_out[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 492.430 0.460 492.890 ; - END - END rd_out[370] - PIN rd_out[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 492.890 0.460 493.350 ; - END - END rd_out[371] - PIN rd_out[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 493.350 0.460 493.810 ; - END - END rd_out[372] - PIN rd_out[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 493.810 0.460 494.270 ; - END - END rd_out[373] - PIN rd_out[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 494.270 0.460 494.730 ; - END - END rd_out[374] - PIN rd_out[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 494.730 0.460 495.190 ; - END - END rd_out[375] - PIN rd_out[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 495.190 0.460 495.650 ; - END - END rd_out[376] - PIN rd_out[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 495.650 0.460 496.110 ; - END - END rd_out[377] - PIN rd_out[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 496.110 0.460 496.570 ; - END - END rd_out[378] - PIN rd_out[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 496.570 0.460 497.030 ; - END - END rd_out[379] - PIN rd_out[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 497.030 0.460 497.490 ; - END - END rd_out[380] - PIN rd_out[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 497.490 0.460 497.950 ; - END - END rd_out[381] - PIN rd_out[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 497.950 0.460 498.410 ; - END - END rd_out[382] - PIN rd_out[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 498.410 0.460 498.870 ; - END - END rd_out[383] - PIN rd_out[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 498.870 0.460 499.330 ; - END - END rd_out[384] - PIN rd_out[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 499.330 0.460 499.790 ; - END - END rd_out[385] - PIN rd_out[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 499.790 0.460 500.250 ; - END - END rd_out[386] - PIN rd_out[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 500.250 0.460 500.710 ; - END - END rd_out[387] - PIN rd_out[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 500.710 0.460 501.170 ; - END - END rd_out[388] - PIN rd_out[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 501.170 0.460 501.630 ; - END - END rd_out[389] - PIN rd_out[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 501.630 0.460 502.090 ; - END - END rd_out[390] - PIN rd_out[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 502.090 0.460 502.550 ; - END - END rd_out[391] - PIN rd_out[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 502.550 0.460 503.010 ; - END - END rd_out[392] - PIN rd_out[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 503.010 0.460 503.470 ; - END - END rd_out[393] - PIN rd_out[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 503.470 0.460 503.930 ; - END - END rd_out[394] - PIN rd_out[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 503.930 0.460 504.390 ; - END - END rd_out[395] - PIN rd_out[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 504.390 0.460 504.850 ; - END - END rd_out[396] - PIN rd_out[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 504.850 0.460 505.310 ; - END - END rd_out[397] - PIN rd_out[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 505.310 0.460 505.770 ; - END - END rd_out[398] - PIN rd_out[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 505.770 0.460 506.230 ; - END - END rd_out[399] - PIN rd_out[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 506.230 0.460 506.690 ; - END - END rd_out[400] - PIN rd_out[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 506.690 0.460 507.150 ; - END - END rd_out[401] - PIN rd_out[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 507.150 0.460 507.610 ; - END - END rd_out[402] - PIN rd_out[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 507.610 0.460 508.070 ; - END - END rd_out[403] - PIN rd_out[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 508.070 0.460 508.530 ; - END - END rd_out[404] - PIN rd_out[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 508.530 0.460 508.990 ; - END - END rd_out[405] - PIN rd_out[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 508.990 0.460 509.450 ; - END - END rd_out[406] - PIN rd_out[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 509.450 0.460 509.910 ; - END - END rd_out[407] - PIN rd_out[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 509.910 0.460 510.370 ; - END - END rd_out[408] - PIN rd_out[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 510.370 0.460 510.830 ; - END - END rd_out[409] - PIN rd_out[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 510.830 0.460 511.290 ; - END - END rd_out[410] - PIN rd_out[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 511.290 0.460 511.750 ; - END - END rd_out[411] - PIN rd_out[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 511.750 0.460 512.210 ; - END - END rd_out[412] - PIN rd_out[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 512.210 0.460 512.670 ; - END - END rd_out[413] - PIN rd_out[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 512.670 0.460 513.130 ; - END - END rd_out[414] - PIN rd_out[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 513.130 0.460 513.590 ; - END - END rd_out[415] - PIN rd_out[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 513.590 0.460 514.050 ; - END - END rd_out[416] - PIN rd_out[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 514.050 0.460 514.510 ; - END - END rd_out[417] - PIN rd_out[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 514.510 0.460 514.970 ; - END - END rd_out[418] - PIN rd_out[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 514.970 0.460 515.430 ; - END - END rd_out[419] - PIN rd_out[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 515.430 0.460 515.890 ; - END - END rd_out[420] - PIN rd_out[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 515.890 0.460 516.350 ; - END - END rd_out[421] - PIN rd_out[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 516.350 0.460 516.810 ; - END - END rd_out[422] - PIN rd_out[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 516.810 0.460 517.270 ; - END - END rd_out[423] - PIN rd_out[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 517.270 0.460 517.730 ; - END - END rd_out[424] - PIN rd_out[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 517.730 0.460 518.190 ; - END - END rd_out[425] - PIN rd_out[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 518.190 0.460 518.650 ; - END - END rd_out[426] - PIN rd_out[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 518.650 0.460 519.110 ; - END - END rd_out[427] - PIN rd_out[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 519.110 0.460 519.570 ; - END - END rd_out[428] - PIN rd_out[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 519.570 0.460 520.030 ; - END - END rd_out[429] - PIN rd_out[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 520.030 0.460 520.490 ; - END - END rd_out[430] - PIN rd_out[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 520.490 0.460 520.950 ; - END - END rd_out[431] - PIN rd_out[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 520.950 0.460 521.410 ; - END - END rd_out[432] - PIN rd_out[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 521.410 0.460 521.870 ; - END - END rd_out[433] - PIN rd_out[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 521.870 0.460 522.330 ; - END - END rd_out[434] - PIN rd_out[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 522.330 0.460 522.790 ; - END - END rd_out[435] - PIN rd_out[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 522.790 0.460 523.250 ; - END - END rd_out[436] - PIN rd_out[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 523.250 0.460 523.710 ; - END - END rd_out[437] - PIN rd_out[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 523.710 0.460 524.170 ; - END - END rd_out[438] - PIN rd_out[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 524.170 0.460 524.630 ; - END - END rd_out[439] - PIN rd_out[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 524.630 0.460 525.090 ; - END - END rd_out[440] - PIN rd_out[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 525.090 0.460 525.550 ; - END - END rd_out[441] - PIN rd_out[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 525.550 0.460 526.010 ; - END - END rd_out[442] - PIN rd_out[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 526.010 0.460 526.470 ; - END - END rd_out[443] - PIN rd_out[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 526.470 0.460 526.930 ; - END - END rd_out[444] - PIN rd_out[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 526.930 0.460 527.390 ; - END - END rd_out[445] - PIN rd_out[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 527.390 0.460 527.850 ; - END - END rd_out[446] - PIN rd_out[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 527.850 0.460 528.310 ; - END - END rd_out[447] - PIN rd_out[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 528.310 0.460 528.770 ; - END - END rd_out[448] - PIN rd_out[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 528.770 0.460 529.230 ; - END - END rd_out[449] - PIN rd_out[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 529.230 0.460 529.690 ; - END - END rd_out[450] - PIN rd_out[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 529.690 0.460 530.150 ; - END - END rd_out[451] - PIN rd_out[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 530.150 0.460 530.610 ; - END - END rd_out[452] - PIN rd_out[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 530.610 0.460 531.070 ; - END - END rd_out[453] - PIN rd_out[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 531.070 0.460 531.530 ; - END - END rd_out[454] - PIN rd_out[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 531.530 0.460 531.990 ; - END - END rd_out[455] - PIN rd_out[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 531.990 0.460 532.450 ; - END - END rd_out[456] - PIN rd_out[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 532.450 0.460 532.910 ; - END - END rd_out[457] - PIN rd_out[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 532.910 0.460 533.370 ; - END - END rd_out[458] - PIN rd_out[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 533.370 0.460 533.830 ; - END - END rd_out[459] - PIN rd_out[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 533.830 0.460 534.290 ; - END - END rd_out[460] - PIN rd_out[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 534.290 0.460 534.750 ; - END - END rd_out[461] - PIN rd_out[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 534.750 0.460 535.210 ; - END - END rd_out[462] - PIN rd_out[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 535.210 0.460 535.670 ; - END - END rd_out[463] - PIN rd_out[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 535.670 0.460 536.130 ; - END - END rd_out[464] - PIN rd_out[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 536.130 0.460 536.590 ; - END - END rd_out[465] - PIN rd_out[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 536.590 0.460 537.050 ; - END - END rd_out[466] - PIN rd_out[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 537.050 0.460 537.510 ; - END - END rd_out[467] - PIN rd_out[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 537.510 0.460 537.970 ; - END - END rd_out[468] - PIN rd_out[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 537.970 0.460 538.430 ; - END - END rd_out[469] - PIN rd_out[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 538.430 0.460 538.890 ; - END - END rd_out[470] - PIN rd_out[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 538.890 0.460 539.350 ; - END - END rd_out[471] - PIN rd_out[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 539.350 0.460 539.810 ; - END - END rd_out[472] - PIN rd_out[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 539.810 0.460 540.270 ; - END - END rd_out[473] - PIN rd_out[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 540.270 0.460 540.730 ; - END - END rd_out[474] - PIN rd_out[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 540.730 0.460 541.190 ; - END - END rd_out[475] - PIN rd_out[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 541.190 0.460 541.650 ; - END - END rd_out[476] - PIN rd_out[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 541.650 0.460 542.110 ; - END - END rd_out[477] - PIN rd_out[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 542.110 0.460 542.570 ; - END - END rd_out[478] - PIN rd_out[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 542.570 0.460 543.030 ; - END - END rd_out[479] - PIN rd_out[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 543.030 0.460 543.490 ; - END - END rd_out[480] - PIN rd_out[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 543.490 0.460 543.950 ; - END - END rd_out[481] - PIN rd_out[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 543.950 0.460 544.410 ; - END - END rd_out[482] - PIN rd_out[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 544.410 0.460 544.870 ; - END - END rd_out[483] - PIN rd_out[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 544.870 0.460 545.330 ; - END - END rd_out[484] - PIN rd_out[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 545.330 0.460 545.790 ; - END - END rd_out[485] - PIN rd_out[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 545.790 0.460 546.250 ; - END - END rd_out[486] - PIN rd_out[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 546.250 0.460 546.710 ; - END - END rd_out[487] - PIN rd_out[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 546.710 0.460 547.170 ; - END - END rd_out[488] - PIN rd_out[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 547.170 0.460 547.630 ; - END - END rd_out[489] - PIN rd_out[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 547.630 0.460 548.090 ; - END - END rd_out[490] - PIN rd_out[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 548.090 0.460 548.550 ; - END - END rd_out[491] - PIN rd_out[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 548.550 0.460 549.010 ; - END - END rd_out[492] - PIN rd_out[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 549.010 0.460 549.470 ; - END - END rd_out[493] - PIN rd_out[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 549.470 0.460 549.930 ; - END - END rd_out[494] - PIN rd_out[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 549.930 0.460 550.390 ; - END - END rd_out[495] - PIN rd_out[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 550.390 0.460 550.850 ; - END - END rd_out[496] - PIN rd_out[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 550.850 0.460 551.310 ; - END - END rd_out[497] - PIN rd_out[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 551.310 0.460 551.770 ; - END - END rd_out[498] - PIN rd_out[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 551.770 0.460 552.230 ; - END - END rd_out[499] - PIN rd_out[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 552.230 0.460 552.690 ; - END - END rd_out[500] - PIN rd_out[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 552.690 0.460 553.150 ; - END - END rd_out[501] - PIN rd_out[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 553.150 0.460 553.610 ; - END - END rd_out[502] - PIN rd_out[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 553.610 0.460 554.070 ; - END - END rd_out[503] - PIN rd_out[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 554.070 0.460 554.530 ; - END - END rd_out[504] - PIN rd_out[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 554.530 0.460 554.990 ; - END - END rd_out[505] - PIN rd_out[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 554.990 0.460 555.450 ; - END - END rd_out[506] - PIN rd_out[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 555.450 0.460 555.910 ; - END - END rd_out[507] - PIN rd_out[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 555.910 0.460 556.370 ; - END - END rd_out[508] - PIN rd_out[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 556.370 0.460 556.830 ; - END - END rd_out[509] - PIN rd_out[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 556.830 0.460 557.290 ; - END - END rd_out[510] - PIN rd_out[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 557.290 0.460 557.750 ; - END - END rd_out[511] - PIN wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 640.090 0.460 640.550 ; - END - END wd_in[0] - PIN wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 640.550 0.460 641.010 ; - END - END wd_in[1] - PIN wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 641.010 0.460 641.470 ; - END - END wd_in[2] - PIN wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 641.470 0.460 641.930 ; - END - END wd_in[3] - PIN wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 641.930 0.460 642.390 ; - END - END wd_in[4] - PIN wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 642.390 0.460 642.850 ; - END - END wd_in[5] - PIN wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 642.850 0.460 643.310 ; - END - END wd_in[6] - PIN wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 643.310 0.460 643.770 ; - END - END wd_in[7] - PIN wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 643.770 0.460 644.230 ; - END - END wd_in[8] - PIN wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 644.230 0.460 644.690 ; - END - END wd_in[9] - PIN wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 644.690 0.460 645.150 ; - END - END wd_in[10] - PIN wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 645.150 0.460 645.610 ; - END - END wd_in[11] - PIN wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 645.610 0.460 646.070 ; - END - END wd_in[12] - PIN wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 646.070 0.460 646.530 ; - END - END wd_in[13] - PIN wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 646.530 0.460 646.990 ; - END - END wd_in[14] - PIN wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 646.990 0.460 647.450 ; - END - END wd_in[15] - PIN wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 647.450 0.460 647.910 ; - END - END wd_in[16] - PIN wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 647.910 0.460 648.370 ; - END - END wd_in[17] - PIN wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 648.370 0.460 648.830 ; - END - END wd_in[18] - PIN wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 648.830 0.460 649.290 ; - END - END wd_in[19] - PIN wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 649.290 0.460 649.750 ; - END - END wd_in[20] - PIN wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 649.750 0.460 650.210 ; - END - END wd_in[21] - PIN wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 650.210 0.460 650.670 ; - END - END wd_in[22] - PIN wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 650.670 0.460 651.130 ; - END - END wd_in[23] - PIN wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 651.130 0.460 651.590 ; - END - END wd_in[24] - PIN wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 651.590 0.460 652.050 ; - END - END wd_in[25] - PIN wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 652.050 0.460 652.510 ; - END - END wd_in[26] - PIN wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 652.510 0.460 652.970 ; - END - END wd_in[27] - PIN wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 652.970 0.460 653.430 ; - END - END wd_in[28] - PIN wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 653.430 0.460 653.890 ; - END - END wd_in[29] - PIN wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 653.890 0.460 654.350 ; - END - END wd_in[30] - PIN wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 654.350 0.460 654.810 ; - END - END wd_in[31] - PIN wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 654.810 0.460 655.270 ; - END - END wd_in[32] - PIN wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 655.270 0.460 655.730 ; - END - END wd_in[33] - PIN wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 655.730 0.460 656.190 ; - END - END wd_in[34] - PIN wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 656.190 0.460 656.650 ; - END - END wd_in[35] - PIN wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 656.650 0.460 657.110 ; - END - END wd_in[36] - PIN wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 657.110 0.460 657.570 ; - END - END wd_in[37] - PIN wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 657.570 0.460 658.030 ; - END - END wd_in[38] - PIN wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 658.030 0.460 658.490 ; - END - END wd_in[39] - PIN wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 658.490 0.460 658.950 ; - END - END wd_in[40] - PIN wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 658.950 0.460 659.410 ; - END - END wd_in[41] - PIN wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 659.410 0.460 659.870 ; - END - END wd_in[42] - PIN wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 659.870 0.460 660.330 ; - END - END wd_in[43] - PIN wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 660.330 0.460 660.790 ; - END - END wd_in[44] - PIN wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 660.790 0.460 661.250 ; - END - END wd_in[45] - PIN wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 661.250 0.460 661.710 ; - END - END wd_in[46] - PIN wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 661.710 0.460 662.170 ; - END - END wd_in[47] - PIN wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 662.170 0.460 662.630 ; - END - END wd_in[48] - PIN wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 662.630 0.460 663.090 ; - END - END wd_in[49] - PIN wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 663.090 0.460 663.550 ; - END - END wd_in[50] - PIN wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 663.550 0.460 664.010 ; - END - END wd_in[51] - PIN wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 664.010 0.460 664.470 ; - END - END wd_in[52] - PIN wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 664.470 0.460 664.930 ; - END - END wd_in[53] - PIN wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 664.930 0.460 665.390 ; - END - END wd_in[54] - PIN wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 665.390 0.460 665.850 ; - END - END wd_in[55] - PIN wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 665.850 0.460 666.310 ; - END - END wd_in[56] - PIN wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 666.310 0.460 666.770 ; - END - END wd_in[57] - PIN wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 666.770 0.460 667.230 ; - END - END wd_in[58] - PIN wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 667.230 0.460 667.690 ; - END - END wd_in[59] - PIN wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 667.690 0.460 668.150 ; - END - END wd_in[60] - PIN wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 668.150 0.460 668.610 ; - END - END wd_in[61] - PIN wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 668.610 0.460 669.070 ; - END - END wd_in[62] - PIN wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 669.070 0.460 669.530 ; - END - END wd_in[63] - PIN wd_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 669.530 0.460 669.990 ; - END - END wd_in[64] - PIN wd_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 669.990 0.460 670.450 ; - END - END wd_in[65] - PIN wd_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 670.450 0.460 670.910 ; - END - END wd_in[66] - PIN wd_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 670.910 0.460 671.370 ; - END - END wd_in[67] - PIN wd_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 671.370 0.460 671.830 ; - END - END wd_in[68] - PIN wd_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 671.830 0.460 672.290 ; - END - END wd_in[69] - PIN wd_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 672.290 0.460 672.750 ; - END - END wd_in[70] - PIN wd_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 672.750 0.460 673.210 ; - END - END wd_in[71] - PIN wd_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 673.210 0.460 673.670 ; - END - END wd_in[72] - PIN wd_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 673.670 0.460 674.130 ; - END - END wd_in[73] - PIN wd_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 674.130 0.460 674.590 ; - END - END wd_in[74] - PIN wd_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 674.590 0.460 675.050 ; - END - END wd_in[75] - PIN wd_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 675.050 0.460 675.510 ; - END - END wd_in[76] - PIN wd_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 675.510 0.460 675.970 ; - END - END wd_in[77] - PIN wd_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 675.970 0.460 676.430 ; - END - END wd_in[78] - PIN wd_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 676.430 0.460 676.890 ; - END - END wd_in[79] - PIN wd_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 676.890 0.460 677.350 ; - END - END wd_in[80] - PIN wd_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 677.350 0.460 677.810 ; - END - END wd_in[81] - PIN wd_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 677.810 0.460 678.270 ; - END - END wd_in[82] - PIN wd_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 678.270 0.460 678.730 ; - END - END wd_in[83] - PIN wd_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 678.730 0.460 679.190 ; - END - END wd_in[84] - PIN wd_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 679.190 0.460 679.650 ; - END - END wd_in[85] - PIN wd_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 679.650 0.460 680.110 ; - END - END wd_in[86] - PIN wd_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 680.110 0.460 680.570 ; - END - END wd_in[87] - PIN wd_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 680.570 0.460 681.030 ; - END - END wd_in[88] - PIN wd_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 681.030 0.460 681.490 ; - END - END wd_in[89] - PIN wd_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 681.490 0.460 681.950 ; - END - END wd_in[90] - PIN wd_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 681.950 0.460 682.410 ; - END - END wd_in[91] - PIN wd_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 682.410 0.460 682.870 ; - END - END wd_in[92] - PIN wd_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 682.870 0.460 683.330 ; - END - END wd_in[93] - PIN wd_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 683.330 0.460 683.790 ; - END - END wd_in[94] - PIN wd_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 683.790 0.460 684.250 ; - END - END wd_in[95] - PIN wd_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 684.250 0.460 684.710 ; - END - END wd_in[96] - PIN wd_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 684.710 0.460 685.170 ; - END - END wd_in[97] - PIN wd_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 685.170 0.460 685.630 ; - END - END wd_in[98] - PIN wd_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 685.630 0.460 686.090 ; - END - END wd_in[99] - PIN wd_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 686.090 0.460 686.550 ; - END - END wd_in[100] - PIN wd_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 686.550 0.460 687.010 ; - END - END wd_in[101] - PIN wd_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 687.010 0.460 687.470 ; - END - END wd_in[102] - PIN wd_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 687.470 0.460 687.930 ; - END - END wd_in[103] - PIN wd_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 687.930 0.460 688.390 ; - END - END wd_in[104] - PIN wd_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 688.390 0.460 688.850 ; - END - END wd_in[105] - PIN wd_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 688.850 0.460 689.310 ; - END - END wd_in[106] - PIN wd_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 689.310 0.460 689.770 ; - END - END wd_in[107] - PIN wd_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 689.770 0.460 690.230 ; - END - END wd_in[108] - PIN wd_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 690.230 0.460 690.690 ; - END - END wd_in[109] - PIN wd_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 690.690 0.460 691.150 ; - END - END wd_in[110] - PIN wd_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 691.150 0.460 691.610 ; - END - END wd_in[111] - PIN wd_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 691.610 0.460 692.070 ; - END - END wd_in[112] - PIN wd_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 692.070 0.460 692.530 ; - END - END wd_in[113] - PIN wd_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 692.530 0.460 692.990 ; - END - END wd_in[114] - PIN wd_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 692.990 0.460 693.450 ; - END - END wd_in[115] - PIN wd_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 693.450 0.460 693.910 ; - END - END wd_in[116] - PIN wd_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 693.910 0.460 694.370 ; - END - END wd_in[117] - PIN wd_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 694.370 0.460 694.830 ; - END - END wd_in[118] - PIN wd_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 694.830 0.460 695.290 ; - END - END wd_in[119] - PIN wd_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 695.290 0.460 695.750 ; - END - END wd_in[120] - PIN wd_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 695.750 0.460 696.210 ; - END - END wd_in[121] - PIN wd_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 696.210 0.460 696.670 ; - END - END wd_in[122] - PIN wd_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 696.670 0.460 697.130 ; - END - END wd_in[123] - PIN wd_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 697.130 0.460 697.590 ; - END - END wd_in[124] - PIN wd_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 697.590 0.460 698.050 ; - END - END wd_in[125] - PIN wd_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 698.050 0.460 698.510 ; - END - END wd_in[126] - PIN wd_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 698.510 0.460 698.970 ; - END - END wd_in[127] - PIN wd_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 698.970 0.460 699.430 ; - END - END wd_in[128] - PIN wd_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 699.430 0.460 699.890 ; - END - END wd_in[129] - PIN wd_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 699.890 0.460 700.350 ; - END - END wd_in[130] - PIN wd_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 700.350 0.460 700.810 ; - END - END wd_in[131] - PIN wd_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 700.810 0.460 701.270 ; - END - END wd_in[132] - PIN wd_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 701.270 0.460 701.730 ; - END - END wd_in[133] - PIN wd_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 701.730 0.460 702.190 ; - END - END wd_in[134] - PIN wd_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 702.190 0.460 702.650 ; - END - END wd_in[135] - PIN wd_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 702.650 0.460 703.110 ; - END - END wd_in[136] - PIN wd_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 703.110 0.460 703.570 ; - END - END wd_in[137] - PIN wd_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 703.570 0.460 704.030 ; - END - END wd_in[138] - PIN wd_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 704.030 0.460 704.490 ; - END - END wd_in[139] - PIN wd_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 704.490 0.460 704.950 ; - END - END wd_in[140] - PIN wd_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 704.950 0.460 705.410 ; - END - END wd_in[141] - PIN wd_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 705.410 0.460 705.870 ; - END - END wd_in[142] - PIN wd_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 705.870 0.460 706.330 ; - END - END wd_in[143] - PIN wd_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 706.330 0.460 706.790 ; - END - END wd_in[144] - PIN wd_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 706.790 0.460 707.250 ; - END - END wd_in[145] - PIN wd_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 707.250 0.460 707.710 ; - END - END wd_in[146] - PIN wd_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 707.710 0.460 708.170 ; - END - END wd_in[147] - PIN wd_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 708.170 0.460 708.630 ; - END - END wd_in[148] - PIN wd_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 708.630 0.460 709.090 ; - END - END wd_in[149] - PIN wd_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 709.090 0.460 709.550 ; - END - END wd_in[150] - PIN wd_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 709.550 0.460 710.010 ; - END - END wd_in[151] - PIN wd_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 710.010 0.460 710.470 ; - END - END wd_in[152] - PIN wd_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 710.470 0.460 710.930 ; - END - END wd_in[153] - PIN wd_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 710.930 0.460 711.390 ; - END - END wd_in[154] - PIN wd_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 711.390 0.460 711.850 ; - END - END wd_in[155] - PIN wd_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 711.850 0.460 712.310 ; - END - END wd_in[156] - PIN wd_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 712.310 0.460 712.770 ; - END - END wd_in[157] - PIN wd_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 712.770 0.460 713.230 ; - END - END wd_in[158] - PIN wd_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 713.230 0.460 713.690 ; - END - END wd_in[159] - PIN wd_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 713.690 0.460 714.150 ; - END - END wd_in[160] - PIN wd_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 714.150 0.460 714.610 ; - END - END wd_in[161] - PIN wd_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 714.610 0.460 715.070 ; - END - END wd_in[162] - PIN wd_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 715.070 0.460 715.530 ; - END - END wd_in[163] - PIN wd_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 715.530 0.460 715.990 ; - END - END wd_in[164] - PIN wd_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 715.990 0.460 716.450 ; - END - END wd_in[165] - PIN wd_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 716.450 0.460 716.910 ; - END - END wd_in[166] - PIN wd_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 716.910 0.460 717.370 ; - END - END wd_in[167] - PIN wd_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 717.370 0.460 717.830 ; - END - END wd_in[168] - PIN wd_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 717.830 0.460 718.290 ; - END - END wd_in[169] - PIN wd_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 718.290 0.460 718.750 ; - END - END wd_in[170] - PIN wd_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 718.750 0.460 719.210 ; - END - END wd_in[171] - PIN wd_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 719.210 0.460 719.670 ; - END - END wd_in[172] - PIN wd_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 719.670 0.460 720.130 ; - END - END wd_in[173] - PIN wd_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 720.130 0.460 720.590 ; - END - END wd_in[174] - PIN wd_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 720.590 0.460 721.050 ; - END - END wd_in[175] - PIN wd_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 721.050 0.460 721.510 ; - END - END wd_in[176] - PIN wd_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 721.510 0.460 721.970 ; - END - END wd_in[177] - PIN wd_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 721.970 0.460 722.430 ; - END - END wd_in[178] - PIN wd_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 722.430 0.460 722.890 ; - END - END wd_in[179] - PIN wd_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 722.890 0.460 723.350 ; - END - END wd_in[180] - PIN wd_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 723.350 0.460 723.810 ; - END - END wd_in[181] - PIN wd_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 723.810 0.460 724.270 ; - END - END wd_in[182] - PIN wd_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 724.270 0.460 724.730 ; - END - END wd_in[183] - PIN wd_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 724.730 0.460 725.190 ; - END - END wd_in[184] - PIN wd_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 725.190 0.460 725.650 ; - END - END wd_in[185] - PIN wd_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 725.650 0.460 726.110 ; - END - END wd_in[186] - PIN wd_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 726.110 0.460 726.570 ; - END - END wd_in[187] - PIN wd_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 726.570 0.460 727.030 ; - END - END wd_in[188] - PIN wd_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 727.030 0.460 727.490 ; - END - END wd_in[189] - PIN wd_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 727.490 0.460 727.950 ; - END - END wd_in[190] - PIN wd_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 727.950 0.460 728.410 ; - END - END wd_in[191] - PIN wd_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 728.410 0.460 728.870 ; - END - END wd_in[192] - PIN wd_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 728.870 0.460 729.330 ; - END - END wd_in[193] - PIN wd_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 729.330 0.460 729.790 ; - END - END wd_in[194] - PIN wd_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 729.790 0.460 730.250 ; - END - END wd_in[195] - PIN wd_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 730.250 0.460 730.710 ; - END - END wd_in[196] - PIN wd_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 730.710 0.460 731.170 ; - END - END wd_in[197] - PIN wd_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 731.170 0.460 731.630 ; - END - END wd_in[198] - PIN wd_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 731.630 0.460 732.090 ; - END - END wd_in[199] - PIN wd_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 732.090 0.460 732.550 ; - END - END wd_in[200] - PIN wd_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 732.550 0.460 733.010 ; - END - END wd_in[201] - PIN wd_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 733.010 0.460 733.470 ; - END - END wd_in[202] - PIN wd_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 733.470 0.460 733.930 ; - END - END wd_in[203] - PIN wd_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 733.930 0.460 734.390 ; - END - END wd_in[204] - PIN wd_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 734.390 0.460 734.850 ; - END - END wd_in[205] - PIN wd_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 734.850 0.460 735.310 ; - END - END wd_in[206] - PIN wd_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 735.310 0.460 735.770 ; - END - END wd_in[207] - PIN wd_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 735.770 0.460 736.230 ; - END - END wd_in[208] - PIN wd_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 736.230 0.460 736.690 ; - END - END wd_in[209] - PIN wd_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 736.690 0.460 737.150 ; - END - END wd_in[210] - PIN wd_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 737.150 0.460 737.610 ; - END - END wd_in[211] - PIN wd_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 737.610 0.460 738.070 ; - END - END wd_in[212] - PIN wd_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 738.070 0.460 738.530 ; - END - END wd_in[213] - PIN wd_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 738.530 0.460 738.990 ; - END - END wd_in[214] - PIN wd_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 738.990 0.460 739.450 ; - END - END wd_in[215] - PIN wd_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 739.450 0.460 739.910 ; - END - END wd_in[216] - PIN wd_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 739.910 0.460 740.370 ; - END - END wd_in[217] - PIN wd_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 740.370 0.460 740.830 ; - END - END wd_in[218] - PIN wd_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 740.830 0.460 741.290 ; - END - END wd_in[219] - PIN wd_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 741.290 0.460 741.750 ; - END - END wd_in[220] - PIN wd_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 741.750 0.460 742.210 ; - END - END wd_in[221] - PIN wd_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 742.210 0.460 742.670 ; - END - END wd_in[222] - PIN wd_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 742.670 0.460 743.130 ; - END - END wd_in[223] - PIN wd_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 743.130 0.460 743.590 ; - END - END wd_in[224] - PIN wd_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 743.590 0.460 744.050 ; - END - END wd_in[225] - PIN wd_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 744.050 0.460 744.510 ; - END - END wd_in[226] - PIN wd_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 744.510 0.460 744.970 ; - END - END wd_in[227] - PIN wd_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 744.970 0.460 745.430 ; - END - END wd_in[228] - PIN wd_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 745.430 0.460 745.890 ; - END - END wd_in[229] - PIN wd_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 745.890 0.460 746.350 ; - END - END wd_in[230] - PIN wd_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 746.350 0.460 746.810 ; - END - END wd_in[231] - PIN wd_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 746.810 0.460 747.270 ; - END - END wd_in[232] - PIN wd_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 747.270 0.460 747.730 ; - END - END wd_in[233] - PIN wd_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 747.730 0.460 748.190 ; - END - END wd_in[234] - PIN wd_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 748.190 0.460 748.650 ; - END - END wd_in[235] - PIN wd_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 748.650 0.460 749.110 ; - END - END wd_in[236] - PIN wd_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 749.110 0.460 749.570 ; - END - END wd_in[237] - PIN wd_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 749.570 0.460 750.030 ; - END - END wd_in[238] - PIN wd_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 750.030 0.460 750.490 ; - END - END wd_in[239] - PIN wd_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 750.490 0.460 750.950 ; - END - END wd_in[240] - PIN wd_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 750.950 0.460 751.410 ; - END - END wd_in[241] - PIN wd_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 751.410 0.460 751.870 ; - END - END wd_in[242] - PIN wd_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 751.870 0.460 752.330 ; - END - END wd_in[243] - PIN wd_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 752.330 0.460 752.790 ; - END - END wd_in[244] - PIN wd_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 752.790 0.460 753.250 ; - END - END wd_in[245] - PIN wd_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 753.250 0.460 753.710 ; - END - END wd_in[246] - PIN wd_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 753.710 0.460 754.170 ; - END - END wd_in[247] - PIN wd_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 754.170 0.460 754.630 ; - END - END wd_in[248] - PIN wd_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 754.630 0.460 755.090 ; - END - END wd_in[249] - PIN wd_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 755.090 0.460 755.550 ; - END - END wd_in[250] - PIN wd_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 755.550 0.460 756.010 ; - END - END wd_in[251] - PIN wd_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 756.010 0.460 756.470 ; - END - END wd_in[252] - PIN wd_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 756.470 0.460 756.930 ; - END - END wd_in[253] - PIN wd_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 756.930 0.460 757.390 ; - END - END wd_in[254] - PIN wd_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 757.390 0.460 757.850 ; - END - END wd_in[255] - PIN wd_in[256] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 757.850 0.460 758.310 ; - END - END wd_in[256] - PIN wd_in[257] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 758.310 0.460 758.770 ; - END - END wd_in[257] - PIN wd_in[258] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 758.770 0.460 759.230 ; - END - END wd_in[258] - PIN wd_in[259] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 759.230 0.460 759.690 ; - END - END wd_in[259] - PIN wd_in[260] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 759.690 0.460 760.150 ; - END - END wd_in[260] - PIN wd_in[261] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 760.150 0.460 760.610 ; - END - END wd_in[261] - PIN wd_in[262] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 760.610 0.460 761.070 ; - END - END wd_in[262] - PIN wd_in[263] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 761.070 0.460 761.530 ; - END - END wd_in[263] - PIN wd_in[264] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 761.530 0.460 761.990 ; - END - END wd_in[264] - PIN wd_in[265] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 761.990 0.460 762.450 ; - END - END wd_in[265] - PIN wd_in[266] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 762.450 0.460 762.910 ; - END - END wd_in[266] - PIN wd_in[267] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 762.910 0.460 763.370 ; - END - END wd_in[267] - PIN wd_in[268] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 763.370 0.460 763.830 ; - END - END wd_in[268] - PIN wd_in[269] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 763.830 0.460 764.290 ; - END - END wd_in[269] - PIN wd_in[270] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 764.290 0.460 764.750 ; - END - END wd_in[270] - PIN wd_in[271] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 764.750 0.460 765.210 ; - END - END wd_in[271] - PIN wd_in[272] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 765.210 0.460 765.670 ; - END - END wd_in[272] - PIN wd_in[273] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 765.670 0.460 766.130 ; - END - END wd_in[273] - PIN wd_in[274] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 766.130 0.460 766.590 ; - END - END wd_in[274] - PIN wd_in[275] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 766.590 0.460 767.050 ; - END - END wd_in[275] - PIN wd_in[276] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 767.050 0.460 767.510 ; - END - END wd_in[276] - PIN wd_in[277] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 767.510 0.460 767.970 ; - END - END wd_in[277] - PIN wd_in[278] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 767.970 0.460 768.430 ; - END - END wd_in[278] - PIN wd_in[279] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 768.430 0.460 768.890 ; - END - END wd_in[279] - PIN wd_in[280] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 768.890 0.460 769.350 ; - END - END wd_in[280] - PIN wd_in[281] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 769.350 0.460 769.810 ; - END - END wd_in[281] - PIN wd_in[282] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 769.810 0.460 770.270 ; - END - END wd_in[282] - PIN wd_in[283] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 770.270 0.460 770.730 ; - END - END wd_in[283] - PIN wd_in[284] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 770.730 0.460 771.190 ; - END - END wd_in[284] - PIN wd_in[285] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 771.190 0.460 771.650 ; - END - END wd_in[285] - PIN wd_in[286] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 771.650 0.460 772.110 ; - END - END wd_in[286] - PIN wd_in[287] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 772.110 0.460 772.570 ; - END - END wd_in[287] - PIN wd_in[288] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 772.570 0.460 773.030 ; - END - END wd_in[288] - PIN wd_in[289] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 773.030 0.460 773.490 ; - END - END wd_in[289] - PIN wd_in[290] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 773.490 0.460 773.950 ; - END - END wd_in[290] - PIN wd_in[291] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 773.950 0.460 774.410 ; - END - END wd_in[291] - PIN wd_in[292] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 774.410 0.460 774.870 ; - END - END wd_in[292] - PIN wd_in[293] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 774.870 0.460 775.330 ; - END - END wd_in[293] - PIN wd_in[294] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 775.330 0.460 775.790 ; - END - END wd_in[294] - PIN wd_in[295] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 775.790 0.460 776.250 ; - END - END wd_in[295] - PIN wd_in[296] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 776.250 0.460 776.710 ; - END - END wd_in[296] - PIN wd_in[297] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 776.710 0.460 777.170 ; - END - END wd_in[297] - PIN wd_in[298] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 777.170 0.460 777.630 ; - END - END wd_in[298] - PIN wd_in[299] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 777.630 0.460 778.090 ; - END - END wd_in[299] - PIN wd_in[300] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 778.090 0.460 778.550 ; - END - END wd_in[300] - PIN wd_in[301] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 778.550 0.460 779.010 ; - END - END wd_in[301] - PIN wd_in[302] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 779.010 0.460 779.470 ; - END - END wd_in[302] - PIN wd_in[303] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 779.470 0.460 779.930 ; - END - END wd_in[303] - PIN wd_in[304] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 779.930 0.460 780.390 ; - END - END wd_in[304] - PIN wd_in[305] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 780.390 0.460 780.850 ; - END - END wd_in[305] - PIN wd_in[306] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 780.850 0.460 781.310 ; - END - END wd_in[306] - PIN wd_in[307] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 781.310 0.460 781.770 ; - END - END wd_in[307] - PIN wd_in[308] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 781.770 0.460 782.230 ; - END - END wd_in[308] - PIN wd_in[309] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 782.230 0.460 782.690 ; - END - END wd_in[309] - PIN wd_in[310] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 782.690 0.460 783.150 ; - END - END wd_in[310] - PIN wd_in[311] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 783.150 0.460 783.610 ; - END - END wd_in[311] - PIN wd_in[312] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 783.610 0.460 784.070 ; - END - END wd_in[312] - PIN wd_in[313] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 784.070 0.460 784.530 ; - END - END wd_in[313] - PIN wd_in[314] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 784.530 0.460 784.990 ; - END - END wd_in[314] - PIN wd_in[315] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 784.990 0.460 785.450 ; - END - END wd_in[315] - PIN wd_in[316] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 785.450 0.460 785.910 ; - END - END wd_in[316] - PIN wd_in[317] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 785.910 0.460 786.370 ; - END - END wd_in[317] - PIN wd_in[318] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 786.370 0.460 786.830 ; - END - END wd_in[318] - PIN wd_in[319] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 786.830 0.460 787.290 ; - END - END wd_in[319] - PIN wd_in[320] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 787.290 0.460 787.750 ; - END - END wd_in[320] - PIN wd_in[321] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 787.750 0.460 788.210 ; - END - END wd_in[321] - PIN wd_in[322] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 788.210 0.460 788.670 ; - END - END wd_in[322] - PIN wd_in[323] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 788.670 0.460 789.130 ; - END - END wd_in[323] - PIN wd_in[324] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 789.130 0.460 789.590 ; - END - END wd_in[324] - PIN wd_in[325] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 789.590 0.460 790.050 ; - END - END wd_in[325] - PIN wd_in[326] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 790.050 0.460 790.510 ; - END - END wd_in[326] - PIN wd_in[327] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 790.510 0.460 790.970 ; - END - END wd_in[327] - PIN wd_in[328] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 790.970 0.460 791.430 ; - END - END wd_in[328] - PIN wd_in[329] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 791.430 0.460 791.890 ; - END - END wd_in[329] - PIN wd_in[330] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 791.890 0.460 792.350 ; - END - END wd_in[330] - PIN wd_in[331] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 792.350 0.460 792.810 ; - END - END wd_in[331] - PIN wd_in[332] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 792.810 0.460 793.270 ; - END - END wd_in[332] - PIN wd_in[333] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 793.270 0.460 793.730 ; - END - END wd_in[333] - PIN wd_in[334] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 793.730 0.460 794.190 ; - END - END wd_in[334] - PIN wd_in[335] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 794.190 0.460 794.650 ; - END - END wd_in[335] - PIN wd_in[336] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 794.650 0.460 795.110 ; - END - END wd_in[336] - PIN wd_in[337] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 795.110 0.460 795.570 ; - END - END wd_in[337] - PIN wd_in[338] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 795.570 0.460 796.030 ; - END - END wd_in[338] - PIN wd_in[339] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 796.030 0.460 796.490 ; - END - END wd_in[339] - PIN wd_in[340] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 796.490 0.460 796.950 ; - END - END wd_in[340] - PIN wd_in[341] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 796.950 0.460 797.410 ; - END - END wd_in[341] - PIN wd_in[342] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 797.410 0.460 797.870 ; - END - END wd_in[342] - PIN wd_in[343] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 797.870 0.460 798.330 ; - END - END wd_in[343] - PIN wd_in[344] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 798.330 0.460 798.790 ; - END - END wd_in[344] - PIN wd_in[345] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 798.790 0.460 799.250 ; - END - END wd_in[345] - PIN wd_in[346] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 799.250 0.460 799.710 ; - END - END wd_in[346] - PIN wd_in[347] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 799.710 0.460 800.170 ; - END - END wd_in[347] - PIN wd_in[348] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 800.170 0.460 800.630 ; - END - END wd_in[348] - PIN wd_in[349] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 800.630 0.460 801.090 ; - END - END wd_in[349] - PIN wd_in[350] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 801.090 0.460 801.550 ; - END - END wd_in[350] - PIN wd_in[351] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 801.550 0.460 802.010 ; - END - END wd_in[351] - PIN wd_in[352] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 802.010 0.460 802.470 ; - END - END wd_in[352] - PIN wd_in[353] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 802.470 0.460 802.930 ; - END - END wd_in[353] - PIN wd_in[354] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 802.930 0.460 803.390 ; - END - END wd_in[354] - PIN wd_in[355] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 803.390 0.460 803.850 ; - END - END wd_in[355] - PIN wd_in[356] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 803.850 0.460 804.310 ; - END - END wd_in[356] - PIN wd_in[357] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 804.310 0.460 804.770 ; - END - END wd_in[357] - PIN wd_in[358] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 804.770 0.460 805.230 ; - END - END wd_in[358] - PIN wd_in[359] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 805.230 0.460 805.690 ; - END - END wd_in[359] - PIN wd_in[360] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 805.690 0.460 806.150 ; - END - END wd_in[360] - PIN wd_in[361] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 806.150 0.460 806.610 ; - END - END wd_in[361] - PIN wd_in[362] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 806.610 0.460 807.070 ; - END - END wd_in[362] - PIN wd_in[363] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 807.070 0.460 807.530 ; - END - END wd_in[363] - PIN wd_in[364] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 807.530 0.460 807.990 ; - END - END wd_in[364] - PIN wd_in[365] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 807.990 0.460 808.450 ; - END - END wd_in[365] - PIN wd_in[366] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 808.450 0.460 808.910 ; - END - END wd_in[366] - PIN wd_in[367] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 808.910 0.460 809.370 ; - END - END wd_in[367] - PIN wd_in[368] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 809.370 0.460 809.830 ; - END - END wd_in[368] - PIN wd_in[369] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 809.830 0.460 810.290 ; - END - END wd_in[369] - PIN wd_in[370] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 810.290 0.460 810.750 ; - END - END wd_in[370] - PIN wd_in[371] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 810.750 0.460 811.210 ; - END - END wd_in[371] - PIN wd_in[372] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 811.210 0.460 811.670 ; - END - END wd_in[372] - PIN wd_in[373] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 811.670 0.460 812.130 ; - END - END wd_in[373] - PIN wd_in[374] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 812.130 0.460 812.590 ; - END - END wd_in[374] - PIN wd_in[375] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 812.590 0.460 813.050 ; - END - END wd_in[375] - PIN wd_in[376] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 813.050 0.460 813.510 ; - END - END wd_in[376] - PIN wd_in[377] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 813.510 0.460 813.970 ; - END - END wd_in[377] - PIN wd_in[378] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 813.970 0.460 814.430 ; - END - END wd_in[378] - PIN wd_in[379] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 814.430 0.460 814.890 ; - END - END wd_in[379] - PIN wd_in[380] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 814.890 0.460 815.350 ; - END - END wd_in[380] - PIN wd_in[381] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 815.350 0.460 815.810 ; - END - END wd_in[381] - PIN wd_in[382] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 815.810 0.460 816.270 ; - END - END wd_in[382] - PIN wd_in[383] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 816.270 0.460 816.730 ; - END - END wd_in[383] - PIN wd_in[384] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 816.730 0.460 817.190 ; - END - END wd_in[384] - PIN wd_in[385] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 817.190 0.460 817.650 ; - END - END wd_in[385] - PIN wd_in[386] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 817.650 0.460 818.110 ; - END - END wd_in[386] - PIN wd_in[387] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 818.110 0.460 818.570 ; - END - END wd_in[387] - PIN wd_in[388] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 818.570 0.460 819.030 ; - END - END wd_in[388] - PIN wd_in[389] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 819.030 0.460 819.490 ; - END - END wd_in[389] - PIN wd_in[390] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 819.490 0.460 819.950 ; - END - END wd_in[390] - PIN wd_in[391] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 819.950 0.460 820.410 ; - END - END wd_in[391] - PIN wd_in[392] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 820.410 0.460 820.870 ; - END - END wd_in[392] - PIN wd_in[393] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 820.870 0.460 821.330 ; - END - END wd_in[393] - PIN wd_in[394] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 821.330 0.460 821.790 ; - END - END wd_in[394] - PIN wd_in[395] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 821.790 0.460 822.250 ; - END - END wd_in[395] - PIN wd_in[396] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 822.250 0.460 822.710 ; - END - END wd_in[396] - PIN wd_in[397] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 822.710 0.460 823.170 ; - END - END wd_in[397] - PIN wd_in[398] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 823.170 0.460 823.630 ; - END - END wd_in[398] - PIN wd_in[399] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 823.630 0.460 824.090 ; - END - END wd_in[399] - PIN wd_in[400] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 824.090 0.460 824.550 ; - END - END wd_in[400] - PIN wd_in[401] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 824.550 0.460 825.010 ; - END - END wd_in[401] - PIN wd_in[402] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 825.010 0.460 825.470 ; - END - END wd_in[402] - PIN wd_in[403] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 825.470 0.460 825.930 ; - END - END wd_in[403] - PIN wd_in[404] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 825.930 0.460 826.390 ; - END - END wd_in[404] - PIN wd_in[405] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 826.390 0.460 826.850 ; - END - END wd_in[405] - PIN wd_in[406] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 826.850 0.460 827.310 ; - END - END wd_in[406] - PIN wd_in[407] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 827.310 0.460 827.770 ; - END - END wd_in[407] - PIN wd_in[408] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 827.770 0.460 828.230 ; - END - END wd_in[408] - PIN wd_in[409] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 828.230 0.460 828.690 ; - END - END wd_in[409] - PIN wd_in[410] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 828.690 0.460 829.150 ; - END - END wd_in[410] - PIN wd_in[411] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 829.150 0.460 829.610 ; - END - END wd_in[411] - PIN wd_in[412] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 829.610 0.460 830.070 ; - END - END wd_in[412] - PIN wd_in[413] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 830.070 0.460 830.530 ; - END - END wd_in[413] - PIN wd_in[414] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 830.530 0.460 830.990 ; - END - END wd_in[414] - PIN wd_in[415] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 830.990 0.460 831.450 ; - END - END wd_in[415] - PIN wd_in[416] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 831.450 0.460 831.910 ; - END - END wd_in[416] - PIN wd_in[417] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 831.910 0.460 832.370 ; - END - END wd_in[417] - PIN wd_in[418] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 832.370 0.460 832.830 ; - END - END wd_in[418] - PIN wd_in[419] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 832.830 0.460 833.290 ; - END - END wd_in[419] - PIN wd_in[420] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 833.290 0.460 833.750 ; - END - END wd_in[420] - PIN wd_in[421] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 833.750 0.460 834.210 ; - END - END wd_in[421] - PIN wd_in[422] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 834.210 0.460 834.670 ; - END - END wd_in[422] - PIN wd_in[423] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 834.670 0.460 835.130 ; - END - END wd_in[423] - PIN wd_in[424] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 835.130 0.460 835.590 ; - END - END wd_in[424] - PIN wd_in[425] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 835.590 0.460 836.050 ; - END - END wd_in[425] - PIN wd_in[426] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 836.050 0.460 836.510 ; - END - END wd_in[426] - PIN wd_in[427] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 836.510 0.460 836.970 ; - END - END wd_in[427] - PIN wd_in[428] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 836.970 0.460 837.430 ; - END - END wd_in[428] - PIN wd_in[429] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 837.430 0.460 837.890 ; - END - END wd_in[429] - PIN wd_in[430] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 837.890 0.460 838.350 ; - END - END wd_in[430] - PIN wd_in[431] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 838.350 0.460 838.810 ; - END - END wd_in[431] - PIN wd_in[432] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 838.810 0.460 839.270 ; - END - END wd_in[432] - PIN wd_in[433] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 839.270 0.460 839.730 ; - END - END wd_in[433] - PIN wd_in[434] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 839.730 0.460 840.190 ; - END - END wd_in[434] - PIN wd_in[435] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 840.190 0.460 840.650 ; - END - END wd_in[435] - PIN wd_in[436] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 840.650 0.460 841.110 ; - END - END wd_in[436] - PIN wd_in[437] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 841.110 0.460 841.570 ; - END - END wd_in[437] - PIN wd_in[438] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 841.570 0.460 842.030 ; - END - END wd_in[438] - PIN wd_in[439] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 842.030 0.460 842.490 ; - END - END wd_in[439] - PIN wd_in[440] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 842.490 0.460 842.950 ; - END - END wd_in[440] - PIN wd_in[441] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 842.950 0.460 843.410 ; - END - END wd_in[441] - PIN wd_in[442] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 843.410 0.460 843.870 ; - END - END wd_in[442] - PIN wd_in[443] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 843.870 0.460 844.330 ; - END - END wd_in[443] - PIN wd_in[444] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 844.330 0.460 844.790 ; - END - END wd_in[444] - PIN wd_in[445] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 844.790 0.460 845.250 ; - END - END wd_in[445] - PIN wd_in[446] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 845.250 0.460 845.710 ; - END - END wd_in[446] - PIN wd_in[447] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 845.710 0.460 846.170 ; - END - END wd_in[447] - PIN wd_in[448] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 846.170 0.460 846.630 ; - END - END wd_in[448] - PIN wd_in[449] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 846.630 0.460 847.090 ; - END - END wd_in[449] - PIN wd_in[450] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 847.090 0.460 847.550 ; - END - END wd_in[450] - PIN wd_in[451] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 847.550 0.460 848.010 ; - END - END wd_in[451] - PIN wd_in[452] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 848.010 0.460 848.470 ; - END - END wd_in[452] - PIN wd_in[453] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 848.470 0.460 848.930 ; - END - END wd_in[453] - PIN wd_in[454] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 848.930 0.460 849.390 ; - END - END wd_in[454] - PIN wd_in[455] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 849.390 0.460 849.850 ; - END - END wd_in[455] - PIN wd_in[456] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 849.850 0.460 850.310 ; - END - END wd_in[456] - PIN wd_in[457] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 850.310 0.460 850.770 ; - END - END wd_in[457] - PIN wd_in[458] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 850.770 0.460 851.230 ; - END - END wd_in[458] - PIN wd_in[459] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 851.230 0.460 851.690 ; - END - END wd_in[459] - PIN wd_in[460] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 851.690 0.460 852.150 ; - END - END wd_in[460] - PIN wd_in[461] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 852.150 0.460 852.610 ; - END - END wd_in[461] - PIN wd_in[462] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 852.610 0.460 853.070 ; - END - END wd_in[462] - PIN wd_in[463] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 853.070 0.460 853.530 ; - END - END wd_in[463] - PIN wd_in[464] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 853.530 0.460 853.990 ; - END - END wd_in[464] - PIN wd_in[465] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 853.990 0.460 854.450 ; - END - END wd_in[465] - PIN wd_in[466] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 854.450 0.460 854.910 ; - END - END wd_in[466] - PIN wd_in[467] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 854.910 0.460 855.370 ; - END - END wd_in[467] - PIN wd_in[468] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 855.370 0.460 855.830 ; - END - END wd_in[468] - PIN wd_in[469] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 855.830 0.460 856.290 ; - END - END wd_in[469] - PIN wd_in[470] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 856.290 0.460 856.750 ; - END - END wd_in[470] - PIN wd_in[471] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 856.750 0.460 857.210 ; - END - END wd_in[471] - PIN wd_in[472] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 857.210 0.460 857.670 ; - END - END wd_in[472] - PIN wd_in[473] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 857.670 0.460 858.130 ; - END - END wd_in[473] - PIN wd_in[474] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 858.130 0.460 858.590 ; - END - END wd_in[474] - PIN wd_in[475] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 858.590 0.460 859.050 ; - END - END wd_in[475] - PIN wd_in[476] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 859.050 0.460 859.510 ; - END - END wd_in[476] - PIN wd_in[477] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 859.510 0.460 859.970 ; - END - END wd_in[477] - PIN wd_in[478] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 859.970 0.460 860.430 ; - END - END wd_in[478] - PIN wd_in[479] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 860.430 0.460 860.890 ; - END - END wd_in[479] - PIN wd_in[480] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 860.890 0.460 861.350 ; - END - END wd_in[480] - PIN wd_in[481] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 861.350 0.460 861.810 ; - END - END wd_in[481] - PIN wd_in[482] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 861.810 0.460 862.270 ; - END - END wd_in[482] - PIN wd_in[483] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 862.270 0.460 862.730 ; - END - END wd_in[483] - PIN wd_in[484] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 862.730 0.460 863.190 ; - END - END wd_in[484] - PIN wd_in[485] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 863.190 0.460 863.650 ; - END - END wd_in[485] - PIN wd_in[486] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 863.650 0.460 864.110 ; - END - END wd_in[486] - PIN wd_in[487] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 864.110 0.460 864.570 ; - END - END wd_in[487] - PIN wd_in[488] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 864.570 0.460 865.030 ; - END - END wd_in[488] - PIN wd_in[489] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 865.030 0.460 865.490 ; - END - END wd_in[489] - PIN wd_in[490] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 865.490 0.460 865.950 ; - END - END wd_in[490] - PIN wd_in[491] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 865.950 0.460 866.410 ; - END - END wd_in[491] - PIN wd_in[492] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 866.410 0.460 866.870 ; - END - END wd_in[492] - PIN wd_in[493] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 866.870 0.460 867.330 ; - END - END wd_in[493] - PIN wd_in[494] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 867.330 0.460 867.790 ; - END - END wd_in[494] - PIN wd_in[495] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 867.790 0.460 868.250 ; - END - END wd_in[495] - PIN wd_in[496] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 868.250 0.460 868.710 ; - END - END wd_in[496] - PIN wd_in[497] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 868.710 0.460 869.170 ; - END - END wd_in[497] - PIN wd_in[498] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 869.170 0.460 869.630 ; - END - END wd_in[498] - PIN wd_in[499] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 869.630 0.460 870.090 ; - END - END wd_in[499] - PIN wd_in[500] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 870.090 0.460 870.550 ; - END - END wd_in[500] - PIN wd_in[501] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 870.550 0.460 871.010 ; - END - END wd_in[501] - PIN wd_in[502] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 871.010 0.460 871.470 ; - END - END wd_in[502] - PIN wd_in[503] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 871.470 0.460 871.930 ; - END - END wd_in[503] - PIN wd_in[504] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 871.930 0.460 872.390 ; - END - END wd_in[504] - PIN wd_in[505] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 872.390 0.460 872.850 ; - END - END wd_in[505] - PIN wd_in[506] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 872.850 0.460 873.310 ; - END - END wd_in[506] - PIN wd_in[507] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 873.310 0.460 873.770 ; - END - END wd_in[507] - PIN wd_in[508] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 873.770 0.460 874.230 ; - END - END wd_in[508] - PIN wd_in[509] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 874.230 0.460 874.690 ; - END - END wd_in[509] - PIN wd_in[510] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 874.690 0.460 875.150 ; - END - END wd_in[510] - PIN wd_in[511] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 875.150 0.460 875.610 ; - END - END wd_in[511] - PIN addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 957.950 0.460 958.410 ; - END - END addr_in[0] - PIN addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 958.410 0.460 958.870 ; - END - END addr_in[1] - PIN addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 958.870 0.460 959.330 ; - END - END addr_in[2] - PIN addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 959.330 0.460 959.790 ; - END - END addr_in[3] - PIN addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 959.790 0.460 960.250 ; - END - END addr_in[4] - PIN addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 960.250 0.460 960.710 ; - END - END addr_in[5] - PIN addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 960.710 0.460 961.170 ; - END - END addr_in[6] - PIN addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 961.170 0.460 961.630 ; - END - END addr_in[7] - PIN we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 1043.970 0.460 1044.430 ; - END - END we_in - PIN ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 1044.430 0.460 1044.890 ; - END - END ce_in - PIN clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 1044.890 0.460 1045.350 ; - END - END clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 3.680 4.600 5.520 1048.040 ; - RECT 11.040 4.600 12.880 1048.040 ; - RECT 18.400 4.600 20.240 1048.040 ; - RECT 25.760 4.600 27.600 1048.040 ; - RECT 33.120 4.600 34.960 1048.040 ; - RECT 40.480 4.600 42.320 1048.040 ; - RECT 47.840 4.600 49.680 1048.040 ; - RECT 55.200 4.600 57.040 1048.040 ; - RECT 62.560 4.600 64.400 1048.040 ; - RECT 69.920 4.600 71.760 1048.040 ; - RECT 77.280 4.600 79.120 1048.040 ; - RECT 84.640 4.600 86.480 1048.040 ; - RECT 92.000 4.600 93.840 1048.040 ; - RECT 99.360 4.600 101.200 1048.040 ; - RECT 106.720 4.600 108.560 1048.040 ; - RECT 114.080 4.600 115.920 1048.040 ; - RECT 121.440 4.600 123.280 1048.040 ; - RECT 128.800 4.600 130.640 1048.040 ; - RECT 136.160 4.600 138.000 1048.040 ; - RECT 143.520 4.600 145.360 1048.040 ; - RECT 150.880 4.600 152.720 1048.040 ; - RECT 158.240 4.600 160.080 1048.040 ; - RECT 165.600 4.600 167.440 1048.040 ; - RECT 172.960 4.600 174.800 1048.040 ; - RECT 180.320 4.600 182.160 1048.040 ; - RECT 187.680 4.600 189.520 1048.040 ; - RECT 195.040 4.600 196.880 1048.040 ; - RECT 202.400 4.600 204.240 1048.040 ; - RECT 209.760 4.600 211.600 1048.040 ; - RECT 217.120 4.600 218.960 1048.040 ; - RECT 224.480 4.600 226.320 1048.040 ; - RECT 231.840 4.600 233.680 1048.040 ; - RECT 239.200 4.600 241.040 1048.040 ; - RECT 246.560 4.600 248.400 1048.040 ; - RECT 253.920 4.600 255.760 1048.040 ; - RECT 261.280 4.600 263.120 1048.040 ; - RECT 268.640 4.600 270.480 1048.040 ; - RECT 276.000 4.600 277.840 1048.040 ; - RECT 283.360 4.600 285.200 1048.040 ; - RECT 290.720 4.600 292.560 1048.040 ; - RECT 298.080 4.600 299.920 1048.040 ; - RECT 305.440 4.600 307.280 1048.040 ; - RECT 312.800 4.600 314.640 1048.040 ; - RECT 320.160 4.600 322.000 1048.040 ; - RECT 327.520 4.600 329.360 1048.040 ; - RECT 334.880 4.600 336.720 1048.040 ; - RECT 342.240 4.600 344.080 1048.040 ; - RECT 349.600 4.600 351.440 1048.040 ; - RECT 356.960 4.600 358.800 1048.040 ; - RECT 364.320 4.600 366.160 1048.040 ; - RECT 371.680 4.600 373.520 1048.040 ; - RECT 379.040 4.600 380.880 1048.040 ; - RECT 386.400 4.600 388.240 1048.040 ; - RECT 393.760 4.600 395.600 1048.040 ; - RECT 401.120 4.600 402.960 1048.040 ; - RECT 408.480 4.600 410.320 1048.040 ; - RECT 415.840 4.600 417.680 1048.040 ; - RECT 423.200 4.600 425.040 1048.040 ; - RECT 430.560 4.600 432.400 1048.040 ; - RECT 437.920 4.600 439.760 1048.040 ; - RECT 445.280 4.600 447.120 1048.040 ; - RECT 452.640 4.600 454.480 1048.040 ; - RECT 460.000 4.600 461.840 1048.040 ; - RECT 467.360 4.600 469.200 1048.040 ; - RECT 474.720 4.600 476.560 1048.040 ; - RECT 482.080 4.600 483.920 1048.040 ; - RECT 489.440 4.600 491.280 1048.040 ; - RECT 496.800 4.600 498.640 1048.040 ; - RECT 504.160 4.600 506.000 1048.040 ; - RECT 511.520 4.600 513.360 1048.040 ; - RECT 518.880 4.600 520.720 1048.040 ; - RECT 526.240 4.600 528.080 1048.040 ; - RECT 533.600 4.600 535.440 1048.040 ; - RECT 540.960 4.600 542.800 1048.040 ; - RECT 548.320 4.600 550.160 1048.040 ; - RECT 555.680 4.600 557.520 1048.040 ; - RECT 563.040 4.600 564.880 1048.040 ; - RECT 570.400 4.600 572.240 1048.040 ; - RECT 577.760 4.600 579.600 1048.040 ; - RECT 585.120 4.600 586.960 1048.040 ; - RECT 592.480 4.600 594.320 1048.040 ; - RECT 599.840 4.600 601.680 1048.040 ; - RECT 607.200 4.600 609.040 1048.040 ; - RECT 614.560 4.600 616.400 1048.040 ; - RECT 621.920 4.600 623.760 1048.040 ; - RECT 629.280 4.600 631.120 1048.040 ; - RECT 636.640 4.600 638.480 1048.040 ; - RECT 644.000 4.600 645.840 1048.040 ; - RECT 651.360 4.600 653.200 1048.040 ; - RECT 658.720 4.600 660.560 1048.040 ; - RECT 666.080 4.600 667.920 1048.040 ; - RECT 673.440 4.600 675.280 1048.040 ; - RECT 680.800 4.600 682.640 1048.040 ; - RECT 688.160 4.600 690.000 1048.040 ; - RECT 695.520 4.600 697.360 1048.040 ; - RECT 702.880 4.600 704.720 1048.040 ; - RECT 710.240 4.600 712.080 1048.040 ; - RECT 717.600 4.600 719.440 1048.040 ; - RECT 724.960 4.600 726.800 1048.040 ; - RECT 732.320 4.600 734.160 1048.040 ; - RECT 739.680 4.600 741.520 1048.040 ; - RECT 747.040 4.600 748.880 1048.040 ; - RECT 754.400 4.600 756.240 1048.040 ; - RECT 761.760 4.600 763.600 1048.040 ; - RECT 769.120 4.600 770.960 1048.040 ; - RECT 776.480 4.600 778.320 1048.040 ; - RECT 783.840 4.600 785.680 1048.040 ; - RECT 791.200 4.600 793.040 1048.040 ; - RECT 798.560 4.600 800.400 1048.040 ; - RECT 805.920 4.600 807.760 1048.040 ; - RECT 813.280 4.600 815.120 1048.040 ; - RECT 820.640 4.600 822.480 1048.040 ; - RECT 828.000 4.600 829.840 1048.040 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 7.360 4.600 9.200 1048.040 ; - RECT 14.720 4.600 16.560 1048.040 ; - RECT 22.080 4.600 23.920 1048.040 ; - RECT 29.440 4.600 31.280 1048.040 ; - RECT 36.800 4.600 38.640 1048.040 ; - RECT 44.160 4.600 46.000 1048.040 ; - RECT 51.520 4.600 53.360 1048.040 ; - RECT 58.880 4.600 60.720 1048.040 ; - RECT 66.240 4.600 68.080 1048.040 ; - RECT 73.600 4.600 75.440 1048.040 ; - RECT 80.960 4.600 82.800 1048.040 ; - RECT 88.320 4.600 90.160 1048.040 ; - RECT 95.680 4.600 97.520 1048.040 ; - RECT 103.040 4.600 104.880 1048.040 ; - RECT 110.400 4.600 112.240 1048.040 ; - RECT 117.760 4.600 119.600 1048.040 ; - RECT 125.120 4.600 126.960 1048.040 ; - RECT 132.480 4.600 134.320 1048.040 ; - RECT 139.840 4.600 141.680 1048.040 ; - RECT 147.200 4.600 149.040 1048.040 ; - RECT 154.560 4.600 156.400 1048.040 ; - RECT 161.920 4.600 163.760 1048.040 ; - RECT 169.280 4.600 171.120 1048.040 ; - RECT 176.640 4.600 178.480 1048.040 ; - RECT 184.000 4.600 185.840 1048.040 ; - RECT 191.360 4.600 193.200 1048.040 ; - RECT 198.720 4.600 200.560 1048.040 ; - RECT 206.080 4.600 207.920 1048.040 ; - RECT 213.440 4.600 215.280 1048.040 ; - RECT 220.800 4.600 222.640 1048.040 ; - RECT 228.160 4.600 230.000 1048.040 ; - RECT 235.520 4.600 237.360 1048.040 ; - RECT 242.880 4.600 244.720 1048.040 ; - RECT 250.240 4.600 252.080 1048.040 ; - RECT 257.600 4.600 259.440 1048.040 ; - RECT 264.960 4.600 266.800 1048.040 ; - RECT 272.320 4.600 274.160 1048.040 ; - RECT 279.680 4.600 281.520 1048.040 ; - RECT 287.040 4.600 288.880 1048.040 ; - RECT 294.400 4.600 296.240 1048.040 ; - RECT 301.760 4.600 303.600 1048.040 ; - RECT 309.120 4.600 310.960 1048.040 ; - RECT 316.480 4.600 318.320 1048.040 ; - RECT 323.840 4.600 325.680 1048.040 ; - RECT 331.200 4.600 333.040 1048.040 ; - RECT 338.560 4.600 340.400 1048.040 ; - RECT 345.920 4.600 347.760 1048.040 ; - RECT 353.280 4.600 355.120 1048.040 ; - RECT 360.640 4.600 362.480 1048.040 ; - RECT 368.000 4.600 369.840 1048.040 ; - RECT 375.360 4.600 377.200 1048.040 ; - RECT 382.720 4.600 384.560 1048.040 ; - RECT 390.080 4.600 391.920 1048.040 ; - RECT 397.440 4.600 399.280 1048.040 ; - RECT 404.800 4.600 406.640 1048.040 ; - RECT 412.160 4.600 414.000 1048.040 ; - RECT 419.520 4.600 421.360 1048.040 ; - RECT 426.880 4.600 428.720 1048.040 ; - RECT 434.240 4.600 436.080 1048.040 ; - RECT 441.600 4.600 443.440 1048.040 ; - RECT 448.960 4.600 450.800 1048.040 ; - RECT 456.320 4.600 458.160 1048.040 ; - RECT 463.680 4.600 465.520 1048.040 ; - RECT 471.040 4.600 472.880 1048.040 ; - RECT 478.400 4.600 480.240 1048.040 ; - RECT 485.760 4.600 487.600 1048.040 ; - RECT 493.120 4.600 494.960 1048.040 ; - RECT 500.480 4.600 502.320 1048.040 ; - RECT 507.840 4.600 509.680 1048.040 ; - RECT 515.200 4.600 517.040 1048.040 ; - RECT 522.560 4.600 524.400 1048.040 ; - RECT 529.920 4.600 531.760 1048.040 ; - RECT 537.280 4.600 539.120 1048.040 ; - RECT 544.640 4.600 546.480 1048.040 ; - RECT 552.000 4.600 553.840 1048.040 ; - RECT 559.360 4.600 561.200 1048.040 ; - RECT 566.720 4.600 568.560 1048.040 ; - RECT 574.080 4.600 575.920 1048.040 ; - RECT 581.440 4.600 583.280 1048.040 ; - RECT 588.800 4.600 590.640 1048.040 ; - RECT 596.160 4.600 598.000 1048.040 ; - RECT 603.520 4.600 605.360 1048.040 ; - RECT 610.880 4.600 612.720 1048.040 ; - RECT 618.240 4.600 620.080 1048.040 ; - RECT 625.600 4.600 627.440 1048.040 ; - RECT 632.960 4.600 634.800 1048.040 ; - RECT 640.320 4.600 642.160 1048.040 ; - RECT 647.680 4.600 649.520 1048.040 ; - RECT 655.040 4.600 656.880 1048.040 ; - RECT 662.400 4.600 664.240 1048.040 ; - RECT 669.760 4.600 671.600 1048.040 ; - RECT 677.120 4.600 678.960 1048.040 ; - RECT 684.480 4.600 686.320 1048.040 ; - RECT 691.840 4.600 693.680 1048.040 ; - RECT 699.200 4.600 701.040 1048.040 ; - RECT 706.560 4.600 708.400 1048.040 ; - RECT 713.920 4.600 715.760 1048.040 ; - RECT 721.280 4.600 723.120 1048.040 ; - RECT 728.640 4.600 730.480 1048.040 ; - RECT 736.000 4.600 737.840 1048.040 ; - RECT 743.360 4.600 745.200 1048.040 ; - RECT 750.720 4.600 752.560 1048.040 ; - RECT 758.080 4.600 759.920 1048.040 ; - RECT 765.440 4.600 767.280 1048.040 ; - RECT 772.800 4.600 774.640 1048.040 ; - RECT 780.160 4.600 782.000 1048.040 ; - RECT 787.520 4.600 789.360 1048.040 ; - RECT 794.880 4.600 796.720 1048.040 ; - RECT 802.240 4.600 804.080 1048.040 ; - RECT 809.600 4.600 811.440 1048.040 ; - RECT 816.960 4.600 818.800 1048.040 ; - RECT 824.320 4.600 826.160 1048.040 ; - END - END VDD - OBS - LAYER met1 ; - RECT 0 0 834.440 1052.640 ; - LAYER met2 ; - RECT 0 0 834.440 1052.640 ; - LAYER met3 ; - RECT 0.460 0 834.440 1052.640 ; - RECT 0 0.000 0.460 4.370 ; - RECT 0 4.830 0.460 4.830 ; - RECT 0 5.290 0.460 5.290 ; - RECT 0 5.750 0.460 5.750 ; - RECT 0 6.210 0.460 6.210 ; - RECT 0 6.670 0.460 6.670 ; - RECT 0 7.130 0.460 7.130 ; - RECT 0 7.590 0.460 7.590 ; - RECT 0 8.050 0.460 8.050 ; - RECT 0 8.510 0.460 8.510 ; - RECT 0 8.970 0.460 8.970 ; - RECT 0 9.430 0.460 9.430 ; - RECT 0 9.890 0.460 9.890 ; - RECT 0 10.350 0.460 10.350 ; - RECT 0 10.810 0.460 10.810 ; - RECT 0 11.270 0.460 11.270 ; - RECT 0 11.730 0.460 11.730 ; - RECT 0 12.190 0.460 12.190 ; - RECT 0 12.650 0.460 12.650 ; - RECT 0 13.110 0.460 13.110 ; - RECT 0 13.570 0.460 13.570 ; - RECT 0 14.030 0.460 14.030 ; - RECT 0 14.490 0.460 14.490 ; - RECT 0 14.950 0.460 14.950 ; - RECT 0 15.410 0.460 15.410 ; - RECT 0 15.870 0.460 15.870 ; - RECT 0 16.330 0.460 16.330 ; - RECT 0 16.790 0.460 16.790 ; - RECT 0 17.250 0.460 17.250 ; - RECT 0 17.710 0.460 17.710 ; - RECT 0 18.170 0.460 18.170 ; - RECT 0 18.630 0.460 18.630 ; - RECT 0 19.090 0.460 19.090 ; - RECT 0 19.550 0.460 19.550 ; - RECT 0 20.010 0.460 20.010 ; - RECT 0 20.470 0.460 20.470 ; - RECT 0 20.930 0.460 20.930 ; - RECT 0 21.390 0.460 21.390 ; - RECT 0 21.850 0.460 21.850 ; - RECT 0 22.310 0.460 22.310 ; - RECT 0 22.770 0.460 22.770 ; - RECT 0 23.230 0.460 23.230 ; - RECT 0 23.690 0.460 23.690 ; - RECT 0 24.150 0.460 24.150 ; - RECT 0 24.610 0.460 24.610 ; - RECT 0 25.070 0.460 25.070 ; - RECT 0 25.530 0.460 25.530 ; - RECT 0 25.990 0.460 25.990 ; - RECT 0 26.450 0.460 26.450 ; - RECT 0 26.910 0.460 26.910 ; - RECT 0 27.370 0.460 27.370 ; - RECT 0 27.830 0.460 27.830 ; - RECT 0 28.290 0.460 28.290 ; - RECT 0 28.750 0.460 28.750 ; - RECT 0 29.210 0.460 29.210 ; - RECT 0 29.670 0.460 29.670 ; - RECT 0 30.130 0.460 30.130 ; - RECT 0 30.590 0.460 30.590 ; - RECT 0 31.050 0.460 31.050 ; - RECT 0 31.510 0.460 31.510 ; - RECT 0 31.970 0.460 31.970 ; - RECT 0 32.430 0.460 32.430 ; - RECT 0 32.890 0.460 32.890 ; - RECT 0 33.350 0.460 33.350 ; - RECT 0 33.810 0.460 33.810 ; - RECT 0 34.270 0.460 34.270 ; - RECT 0 34.730 0.460 34.730 ; - RECT 0 35.190 0.460 35.190 ; - RECT 0 35.650 0.460 35.650 ; - RECT 0 36.110 0.460 36.110 ; - RECT 0 36.570 0.460 36.570 ; - RECT 0 37.030 0.460 37.030 ; - RECT 0 37.490 0.460 37.490 ; - RECT 0 37.950 0.460 37.950 ; - RECT 0 38.410 0.460 38.410 ; - RECT 0 38.870 0.460 38.870 ; - RECT 0 39.330 0.460 39.330 ; - RECT 0 39.790 0.460 39.790 ; - RECT 0 40.250 0.460 40.250 ; - RECT 0 40.710 0.460 40.710 ; - RECT 0 41.170 0.460 41.170 ; - RECT 0 41.630 0.460 41.630 ; - RECT 0 42.090 0.460 42.090 ; - RECT 0 42.550 0.460 42.550 ; - RECT 0 43.010 0.460 43.010 ; - RECT 0 43.470 0.460 43.470 ; - RECT 0 43.930 0.460 43.930 ; - RECT 0 44.390 0.460 44.390 ; - RECT 0 44.850 0.460 44.850 ; - RECT 0 45.310 0.460 45.310 ; - RECT 0 45.770 0.460 45.770 ; - RECT 0 46.230 0.460 46.230 ; - RECT 0 46.690 0.460 46.690 ; - RECT 0 47.150 0.460 47.150 ; - RECT 0 47.610 0.460 47.610 ; - RECT 0 48.070 0.460 48.070 ; - RECT 0 48.530 0.460 48.530 ; - RECT 0 48.990 0.460 48.990 ; - RECT 0 49.450 0.460 49.450 ; - RECT 0 49.910 0.460 49.910 ; - RECT 0 50.370 0.460 50.370 ; - RECT 0 50.830 0.460 50.830 ; - RECT 0 51.290 0.460 51.290 ; - RECT 0 51.750 0.460 51.750 ; - RECT 0 52.210 0.460 52.210 ; - RECT 0 52.670 0.460 52.670 ; - RECT 0 53.130 0.460 53.130 ; - RECT 0 53.590 0.460 53.590 ; - RECT 0 54.050 0.460 54.050 ; - RECT 0 54.510 0.460 54.510 ; - RECT 0 54.970 0.460 54.970 ; - RECT 0 55.430 0.460 55.430 ; - RECT 0 55.890 0.460 55.890 ; - RECT 0 56.350 0.460 56.350 ; - RECT 0 56.810 0.460 56.810 ; - RECT 0 57.270 0.460 57.270 ; - RECT 0 57.730 0.460 57.730 ; - RECT 0 58.190 0.460 58.190 ; - RECT 0 58.650 0.460 58.650 ; - RECT 0 59.110 0.460 59.110 ; - RECT 0 59.570 0.460 59.570 ; - RECT 0 60.030 0.460 60.030 ; - RECT 0 60.490 0.460 60.490 ; - RECT 0 60.950 0.460 60.950 ; - RECT 0 61.410 0.460 61.410 ; - RECT 0 61.870 0.460 61.870 ; - RECT 0 62.330 0.460 62.330 ; - RECT 0 62.790 0.460 62.790 ; - RECT 0 63.250 0.460 63.250 ; - RECT 0 63.710 0.460 63.710 ; - RECT 0 64.170 0.460 64.170 ; - RECT 0 64.630 0.460 64.630 ; - RECT 0 65.090 0.460 65.090 ; - RECT 0 65.550 0.460 65.550 ; - RECT 0 66.010 0.460 66.010 ; - RECT 0 66.470 0.460 66.470 ; - RECT 0 66.930 0.460 66.930 ; - RECT 0 67.390 0.460 67.390 ; - RECT 0 67.850 0.460 67.850 ; - RECT 0 68.310 0.460 68.310 ; - RECT 0 68.770 0.460 68.770 ; - RECT 0 69.230 0.460 69.230 ; - RECT 0 69.690 0.460 69.690 ; - RECT 0 70.150 0.460 70.150 ; - RECT 0 70.610 0.460 70.610 ; - RECT 0 71.070 0.460 71.070 ; - RECT 0 71.530 0.460 71.530 ; - RECT 0 71.990 0.460 71.990 ; - RECT 0 72.450 0.460 72.450 ; - RECT 0 72.910 0.460 72.910 ; - RECT 0 73.370 0.460 73.370 ; - RECT 0 73.830 0.460 73.830 ; - RECT 0 74.290 0.460 74.290 ; - RECT 0 74.750 0.460 74.750 ; - RECT 0 75.210 0.460 75.210 ; - RECT 0 75.670 0.460 75.670 ; - RECT 0 76.130 0.460 76.130 ; - RECT 0 76.590 0.460 76.590 ; - RECT 0 77.050 0.460 77.050 ; - RECT 0 77.510 0.460 77.510 ; - RECT 0 77.970 0.460 77.970 ; - RECT 0 78.430 0.460 78.430 ; - RECT 0 78.890 0.460 78.890 ; - RECT 0 79.350 0.460 79.350 ; - RECT 0 79.810 0.460 79.810 ; - RECT 0 80.270 0.460 80.270 ; - RECT 0 80.730 0.460 80.730 ; - RECT 0 81.190 0.460 81.190 ; - RECT 0 81.650 0.460 81.650 ; - RECT 0 82.110 0.460 82.110 ; - RECT 0 82.570 0.460 82.570 ; - RECT 0 83.030 0.460 83.030 ; - RECT 0 83.490 0.460 83.490 ; - RECT 0 83.950 0.460 83.950 ; - RECT 0 84.410 0.460 84.410 ; - RECT 0 84.870 0.460 84.870 ; - RECT 0 85.330 0.460 85.330 ; - RECT 0 85.790 0.460 85.790 ; - RECT 0 86.250 0.460 86.250 ; - RECT 0 86.710 0.460 86.710 ; - RECT 0 87.170 0.460 87.170 ; - RECT 0 87.630 0.460 87.630 ; - RECT 0 88.090 0.460 88.090 ; - RECT 0 88.550 0.460 88.550 ; - RECT 0 89.010 0.460 89.010 ; - RECT 0 89.470 0.460 89.470 ; - RECT 0 89.930 0.460 89.930 ; - RECT 0 90.390 0.460 90.390 ; - RECT 0 90.850 0.460 90.850 ; - RECT 0 91.310 0.460 91.310 ; - RECT 0 91.770 0.460 91.770 ; - RECT 0 92.230 0.460 92.230 ; - RECT 0 92.690 0.460 92.690 ; - RECT 0 93.150 0.460 93.150 ; - RECT 0 93.610 0.460 93.610 ; - RECT 0 94.070 0.460 94.070 ; - RECT 0 94.530 0.460 94.530 ; - RECT 0 94.990 0.460 94.990 ; - RECT 0 95.450 0.460 95.450 ; - RECT 0 95.910 0.460 95.910 ; - RECT 0 96.370 0.460 96.370 ; - RECT 0 96.830 0.460 96.830 ; - RECT 0 97.290 0.460 97.290 ; - RECT 0 97.750 0.460 97.750 ; - RECT 0 98.210 0.460 98.210 ; - RECT 0 98.670 0.460 98.670 ; - RECT 0 99.130 0.460 99.130 ; - RECT 0 99.590 0.460 99.590 ; - RECT 0 100.050 0.460 100.050 ; - RECT 0 100.510 0.460 100.510 ; - RECT 0 100.970 0.460 100.970 ; - RECT 0 101.430 0.460 101.430 ; - RECT 0 101.890 0.460 101.890 ; - RECT 0 102.350 0.460 102.350 ; - RECT 0 102.810 0.460 102.810 ; - RECT 0 103.270 0.460 103.270 ; - RECT 0 103.730 0.460 103.730 ; - RECT 0 104.190 0.460 104.190 ; - RECT 0 104.650 0.460 104.650 ; - RECT 0 105.110 0.460 105.110 ; - RECT 0 105.570 0.460 105.570 ; - RECT 0 106.030 0.460 106.030 ; - RECT 0 106.490 0.460 106.490 ; - RECT 0 106.950 0.460 106.950 ; - RECT 0 107.410 0.460 107.410 ; - RECT 0 107.870 0.460 107.870 ; - RECT 0 108.330 0.460 108.330 ; - RECT 0 108.790 0.460 108.790 ; - RECT 0 109.250 0.460 109.250 ; - RECT 0 109.710 0.460 109.710 ; - RECT 0 110.170 0.460 110.170 ; - RECT 0 110.630 0.460 110.630 ; - RECT 0 111.090 0.460 111.090 ; - RECT 0 111.550 0.460 111.550 ; - RECT 0 112.010 0.460 112.010 ; - RECT 0 112.470 0.460 112.470 ; - RECT 0 112.930 0.460 112.930 ; - RECT 0 113.390 0.460 113.390 ; - RECT 0 113.850 0.460 113.850 ; - RECT 0 114.310 0.460 114.310 ; - RECT 0 114.770 0.460 114.770 ; - RECT 0 115.230 0.460 115.230 ; - RECT 0 115.690 0.460 115.690 ; - RECT 0 116.150 0.460 116.150 ; - RECT 0 116.610 0.460 116.610 ; - RECT 0 117.070 0.460 117.070 ; - RECT 0 117.530 0.460 117.530 ; - RECT 0 117.990 0.460 117.990 ; - RECT 0 118.450 0.460 118.450 ; - RECT 0 118.910 0.460 118.910 ; - RECT 0 119.370 0.460 119.370 ; - RECT 0 119.830 0.460 119.830 ; - RECT 0 120.290 0.460 120.290 ; - RECT 0 120.750 0.460 120.750 ; - RECT 0 121.210 0.460 121.210 ; - RECT 0 121.670 0.460 121.670 ; - RECT 0 122.130 0.460 122.130 ; - RECT 0 122.590 0.460 122.590 ; - RECT 0 123.050 0.460 123.050 ; - RECT 0 123.510 0.460 123.510 ; - RECT 0 123.970 0.460 123.970 ; - RECT 0 124.430 0.460 124.430 ; - RECT 0 124.890 0.460 124.890 ; - RECT 0 125.350 0.460 125.350 ; - RECT 0 125.810 0.460 125.810 ; - RECT 0 126.270 0.460 126.270 ; - RECT 0 126.730 0.460 126.730 ; - RECT 0 127.190 0.460 127.190 ; - RECT 0 127.650 0.460 127.650 ; - RECT 0 128.110 0.460 128.110 ; - RECT 0 128.570 0.460 128.570 ; - RECT 0 129.030 0.460 129.030 ; - RECT 0 129.490 0.460 129.490 ; - RECT 0 129.950 0.460 129.950 ; - RECT 0 130.410 0.460 130.410 ; - RECT 0 130.870 0.460 130.870 ; - RECT 0 131.330 0.460 131.330 ; - RECT 0 131.790 0.460 131.790 ; - RECT 0 132.250 0.460 132.250 ; - RECT 0 132.710 0.460 132.710 ; - RECT 0 133.170 0.460 133.170 ; - RECT 0 133.630 0.460 133.630 ; - RECT 0 134.090 0.460 134.090 ; - RECT 0 134.550 0.460 134.550 ; - RECT 0 135.010 0.460 135.010 ; - RECT 0 135.470 0.460 135.470 ; - RECT 0 135.930 0.460 135.930 ; - RECT 0 136.390 0.460 136.390 ; - RECT 0 136.850 0.460 136.850 ; - RECT 0 137.310 0.460 137.310 ; - RECT 0 137.770 0.460 137.770 ; - RECT 0 138.230 0.460 138.230 ; - RECT 0 138.690 0.460 138.690 ; - RECT 0 139.150 0.460 139.150 ; - RECT 0 139.610 0.460 139.610 ; - RECT 0 140.070 0.460 140.070 ; - RECT 0 140.530 0.460 140.530 ; - RECT 0 140.990 0.460 140.990 ; - RECT 0 141.450 0.460 141.450 ; - RECT 0 141.910 0.460 141.910 ; - RECT 0 142.370 0.460 142.370 ; - RECT 0 142.830 0.460 142.830 ; - RECT 0 143.290 0.460 143.290 ; - RECT 0 143.750 0.460 143.750 ; - RECT 0 144.210 0.460 144.210 ; - RECT 0 144.670 0.460 144.670 ; - RECT 0 145.130 0.460 145.130 ; - RECT 0 145.590 0.460 145.590 ; - RECT 0 146.050 0.460 146.050 ; - RECT 0 146.510 0.460 146.510 ; - RECT 0 146.970 0.460 146.970 ; - RECT 0 147.430 0.460 147.430 ; - RECT 0 147.890 0.460 147.890 ; - RECT 0 148.350 0.460 148.350 ; - RECT 0 148.810 0.460 148.810 ; - RECT 0 149.270 0.460 149.270 ; - RECT 0 149.730 0.460 149.730 ; - RECT 0 150.190 0.460 150.190 ; - RECT 0 150.650 0.460 150.650 ; - RECT 0 151.110 0.460 151.110 ; - RECT 0 151.570 0.460 151.570 ; - RECT 0 152.030 0.460 152.030 ; - RECT 0 152.490 0.460 152.490 ; - RECT 0 152.950 0.460 152.950 ; - RECT 0 153.410 0.460 153.410 ; - RECT 0 153.870 0.460 153.870 ; - RECT 0 154.330 0.460 154.330 ; - RECT 0 154.790 0.460 154.790 ; - RECT 0 155.250 0.460 155.250 ; - RECT 0 155.710 0.460 155.710 ; - RECT 0 156.170 0.460 156.170 ; - RECT 0 156.630 0.460 156.630 ; - RECT 0 157.090 0.460 157.090 ; - RECT 0 157.550 0.460 157.550 ; - RECT 0 158.010 0.460 158.010 ; - RECT 0 158.470 0.460 158.470 ; - RECT 0 158.930 0.460 158.930 ; - RECT 0 159.390 0.460 159.390 ; - RECT 0 159.850 0.460 159.850 ; - RECT 0 160.310 0.460 160.310 ; - RECT 0 160.770 0.460 160.770 ; - RECT 0 161.230 0.460 161.230 ; - RECT 0 161.690 0.460 161.690 ; - RECT 0 162.150 0.460 162.150 ; - RECT 0 162.610 0.460 162.610 ; - RECT 0 163.070 0.460 163.070 ; - RECT 0 163.530 0.460 163.530 ; - RECT 0 163.990 0.460 163.990 ; - RECT 0 164.450 0.460 164.450 ; - RECT 0 164.910 0.460 164.910 ; - RECT 0 165.370 0.460 165.370 ; - RECT 0 165.830 0.460 165.830 ; - RECT 0 166.290 0.460 166.290 ; - RECT 0 166.750 0.460 166.750 ; - RECT 0 167.210 0.460 167.210 ; - RECT 0 167.670 0.460 167.670 ; - RECT 0 168.130 0.460 168.130 ; - RECT 0 168.590 0.460 168.590 ; - RECT 0 169.050 0.460 169.050 ; - RECT 0 169.510 0.460 169.510 ; - RECT 0 169.970 0.460 169.970 ; - RECT 0 170.430 0.460 170.430 ; - RECT 0 170.890 0.460 170.890 ; - RECT 0 171.350 0.460 171.350 ; - RECT 0 171.810 0.460 171.810 ; - RECT 0 172.270 0.460 172.270 ; - RECT 0 172.730 0.460 172.730 ; - RECT 0 173.190 0.460 173.190 ; - RECT 0 173.650 0.460 173.650 ; - RECT 0 174.110 0.460 174.110 ; - RECT 0 174.570 0.460 174.570 ; - RECT 0 175.030 0.460 175.030 ; - RECT 0 175.490 0.460 175.490 ; - RECT 0 175.950 0.460 175.950 ; - RECT 0 176.410 0.460 176.410 ; - RECT 0 176.870 0.460 176.870 ; - RECT 0 177.330 0.460 177.330 ; - RECT 0 177.790 0.460 177.790 ; - RECT 0 178.250 0.460 178.250 ; - RECT 0 178.710 0.460 178.710 ; - RECT 0 179.170 0.460 179.170 ; - RECT 0 179.630 0.460 179.630 ; - RECT 0 180.090 0.460 180.090 ; - RECT 0 180.550 0.460 180.550 ; - RECT 0 181.010 0.460 181.010 ; - RECT 0 181.470 0.460 181.470 ; - RECT 0 181.930 0.460 181.930 ; - RECT 0 182.390 0.460 182.390 ; - RECT 0 182.850 0.460 182.850 ; - RECT 0 183.310 0.460 183.310 ; - RECT 0 183.770 0.460 183.770 ; - RECT 0 184.230 0.460 184.230 ; - RECT 0 184.690 0.460 184.690 ; - RECT 0 185.150 0.460 185.150 ; - RECT 0 185.610 0.460 185.610 ; - RECT 0 186.070 0.460 186.070 ; - RECT 0 186.530 0.460 186.530 ; - RECT 0 186.990 0.460 186.990 ; - RECT 0 187.450 0.460 187.450 ; - RECT 0 187.910 0.460 187.910 ; - RECT 0 188.370 0.460 188.370 ; - RECT 0 188.830 0.460 188.830 ; - RECT 0 189.290 0.460 189.290 ; - RECT 0 189.750 0.460 189.750 ; - RECT 0 190.210 0.460 190.210 ; - RECT 0 190.670 0.460 190.670 ; - RECT 0 191.130 0.460 191.130 ; - RECT 0 191.590 0.460 191.590 ; - RECT 0 192.050 0.460 192.050 ; - RECT 0 192.510 0.460 192.510 ; - RECT 0 192.970 0.460 192.970 ; - RECT 0 193.430 0.460 193.430 ; - RECT 0 193.890 0.460 193.890 ; - RECT 0 194.350 0.460 194.350 ; - RECT 0 194.810 0.460 194.810 ; - RECT 0 195.270 0.460 195.270 ; - RECT 0 195.730 0.460 195.730 ; - RECT 0 196.190 0.460 196.190 ; - RECT 0 196.650 0.460 196.650 ; - RECT 0 197.110 0.460 197.110 ; - RECT 0 197.570 0.460 197.570 ; - RECT 0 198.030 0.460 198.030 ; - RECT 0 198.490 0.460 198.490 ; - RECT 0 198.950 0.460 198.950 ; - RECT 0 199.410 0.460 199.410 ; - RECT 0 199.870 0.460 199.870 ; - RECT 0 200.330 0.460 200.330 ; - RECT 0 200.790 0.460 200.790 ; - RECT 0 201.250 0.460 201.250 ; - RECT 0 201.710 0.460 201.710 ; - RECT 0 202.170 0.460 202.170 ; - RECT 0 202.630 0.460 202.630 ; - RECT 0 203.090 0.460 203.090 ; - RECT 0 203.550 0.460 203.550 ; - RECT 0 204.010 0.460 204.010 ; - RECT 0 204.470 0.460 204.470 ; - RECT 0 204.930 0.460 204.930 ; - RECT 0 205.390 0.460 205.390 ; - RECT 0 205.850 0.460 205.850 ; - RECT 0 206.310 0.460 206.310 ; - RECT 0 206.770 0.460 206.770 ; - RECT 0 207.230 0.460 207.230 ; - RECT 0 207.690 0.460 207.690 ; - RECT 0 208.150 0.460 208.150 ; - RECT 0 208.610 0.460 208.610 ; - RECT 0 209.070 0.460 209.070 ; - RECT 0 209.530 0.460 209.530 ; - RECT 0 209.990 0.460 209.990 ; - RECT 0 210.450 0.460 210.450 ; - RECT 0 210.910 0.460 210.910 ; - RECT 0 211.370 0.460 211.370 ; - RECT 0 211.830 0.460 211.830 ; - RECT 0 212.290 0.460 212.290 ; - RECT 0 212.750 0.460 212.750 ; - RECT 0 213.210 0.460 213.210 ; - RECT 0 213.670 0.460 213.670 ; - RECT 0 214.130 0.460 214.130 ; - RECT 0 214.590 0.460 214.590 ; - RECT 0 215.050 0.460 215.050 ; - RECT 0 215.510 0.460 215.510 ; - RECT 0 215.970 0.460 215.970 ; - RECT 0 216.430 0.460 216.430 ; - RECT 0 216.890 0.460 216.890 ; - RECT 0 217.350 0.460 217.350 ; - RECT 0 217.810 0.460 217.810 ; - RECT 0 218.270 0.460 218.270 ; - RECT 0 218.730 0.460 218.730 ; - RECT 0 219.190 0.460 219.190 ; - RECT 0 219.650 0.460 219.650 ; - RECT 0 220.110 0.460 220.110 ; - RECT 0 220.570 0.460 220.570 ; - RECT 0 221.030 0.460 221.030 ; - RECT 0 221.490 0.460 221.490 ; - RECT 0 221.950 0.460 221.950 ; - RECT 0 222.410 0.460 222.410 ; - RECT 0 222.870 0.460 222.870 ; - RECT 0 223.330 0.460 223.330 ; - RECT 0 223.790 0.460 223.790 ; - RECT 0 224.250 0.460 224.250 ; - RECT 0 224.710 0.460 224.710 ; - RECT 0 225.170 0.460 225.170 ; - RECT 0 225.630 0.460 225.630 ; - RECT 0 226.090 0.460 226.090 ; - RECT 0 226.550 0.460 226.550 ; - RECT 0 227.010 0.460 227.010 ; - RECT 0 227.470 0.460 227.470 ; - RECT 0 227.930 0.460 227.930 ; - RECT 0 228.390 0.460 228.390 ; - RECT 0 228.850 0.460 228.850 ; - RECT 0 229.310 0.460 229.310 ; - RECT 0 229.770 0.460 229.770 ; - RECT 0 230.230 0.460 230.230 ; - RECT 0 230.690 0.460 230.690 ; - RECT 0 231.150 0.460 231.150 ; - RECT 0 231.610 0.460 231.610 ; - RECT 0 232.070 0.460 232.070 ; - RECT 0 232.530 0.460 232.530 ; - RECT 0 232.990 0.460 232.990 ; - RECT 0 233.450 0.460 233.450 ; - RECT 0 233.910 0.460 233.910 ; - RECT 0 234.370 0.460 234.370 ; - RECT 0 234.830 0.460 234.830 ; - RECT 0 235.290 0.460 235.290 ; - RECT 0 235.750 0.460 235.750 ; - RECT 0 236.210 0.460 236.210 ; - RECT 0 236.670 0.460 236.670 ; - RECT 0 237.130 0.460 237.130 ; - RECT 0 237.590 0.460 237.590 ; - RECT 0 238.050 0.460 238.050 ; - RECT 0 238.510 0.460 238.510 ; - RECT 0 238.970 0.460 238.970 ; - RECT 0 239.430 0.460 239.430 ; - RECT 0 239.890 0.460 322.230 ; - RECT 0 322.690 0.460 322.690 ; - RECT 0 323.150 0.460 323.150 ; - RECT 0 323.610 0.460 323.610 ; - RECT 0 324.070 0.460 324.070 ; - RECT 0 324.530 0.460 324.530 ; - RECT 0 324.990 0.460 324.990 ; - RECT 0 325.450 0.460 325.450 ; - RECT 0 325.910 0.460 325.910 ; - RECT 0 326.370 0.460 326.370 ; - RECT 0 326.830 0.460 326.830 ; - RECT 0 327.290 0.460 327.290 ; - RECT 0 327.750 0.460 327.750 ; - RECT 0 328.210 0.460 328.210 ; - RECT 0 328.670 0.460 328.670 ; - RECT 0 329.130 0.460 329.130 ; - RECT 0 329.590 0.460 329.590 ; - RECT 0 330.050 0.460 330.050 ; - RECT 0 330.510 0.460 330.510 ; - RECT 0 330.970 0.460 330.970 ; - RECT 0 331.430 0.460 331.430 ; - RECT 0 331.890 0.460 331.890 ; - RECT 0 332.350 0.460 332.350 ; - RECT 0 332.810 0.460 332.810 ; - RECT 0 333.270 0.460 333.270 ; - RECT 0 333.730 0.460 333.730 ; - RECT 0 334.190 0.460 334.190 ; - RECT 0 334.650 0.460 334.650 ; - RECT 0 335.110 0.460 335.110 ; - RECT 0 335.570 0.460 335.570 ; - RECT 0 336.030 0.460 336.030 ; - RECT 0 336.490 0.460 336.490 ; - RECT 0 336.950 0.460 336.950 ; - RECT 0 337.410 0.460 337.410 ; - RECT 0 337.870 0.460 337.870 ; - RECT 0 338.330 0.460 338.330 ; - RECT 0 338.790 0.460 338.790 ; - RECT 0 339.250 0.460 339.250 ; - RECT 0 339.710 0.460 339.710 ; - RECT 0 340.170 0.460 340.170 ; - RECT 0 340.630 0.460 340.630 ; - RECT 0 341.090 0.460 341.090 ; - RECT 0 341.550 0.460 341.550 ; - RECT 0 342.010 0.460 342.010 ; - RECT 0 342.470 0.460 342.470 ; - RECT 0 342.930 0.460 342.930 ; - RECT 0 343.390 0.460 343.390 ; - RECT 0 343.850 0.460 343.850 ; - RECT 0 344.310 0.460 344.310 ; - RECT 0 344.770 0.460 344.770 ; - RECT 0 345.230 0.460 345.230 ; - RECT 0 345.690 0.460 345.690 ; - RECT 0 346.150 0.460 346.150 ; - RECT 0 346.610 0.460 346.610 ; - RECT 0 347.070 0.460 347.070 ; - RECT 0 347.530 0.460 347.530 ; - RECT 0 347.990 0.460 347.990 ; - RECT 0 348.450 0.460 348.450 ; - RECT 0 348.910 0.460 348.910 ; - RECT 0 349.370 0.460 349.370 ; - RECT 0 349.830 0.460 349.830 ; - RECT 0 350.290 0.460 350.290 ; - RECT 0 350.750 0.460 350.750 ; - RECT 0 351.210 0.460 351.210 ; - RECT 0 351.670 0.460 351.670 ; - RECT 0 352.130 0.460 352.130 ; - RECT 0 352.590 0.460 352.590 ; - RECT 0 353.050 0.460 353.050 ; - RECT 0 353.510 0.460 353.510 ; - RECT 0 353.970 0.460 353.970 ; - RECT 0 354.430 0.460 354.430 ; - RECT 0 354.890 0.460 354.890 ; - RECT 0 355.350 0.460 355.350 ; - RECT 0 355.810 0.460 355.810 ; - RECT 0 356.270 0.460 356.270 ; - RECT 0 356.730 0.460 356.730 ; - RECT 0 357.190 0.460 357.190 ; - RECT 0 357.650 0.460 357.650 ; - RECT 0 358.110 0.460 358.110 ; - RECT 0 358.570 0.460 358.570 ; - RECT 0 359.030 0.460 359.030 ; - RECT 0 359.490 0.460 359.490 ; - RECT 0 359.950 0.460 359.950 ; - RECT 0 360.410 0.460 360.410 ; - RECT 0 360.870 0.460 360.870 ; - RECT 0 361.330 0.460 361.330 ; - RECT 0 361.790 0.460 361.790 ; - RECT 0 362.250 0.460 362.250 ; - RECT 0 362.710 0.460 362.710 ; - RECT 0 363.170 0.460 363.170 ; - RECT 0 363.630 0.460 363.630 ; - RECT 0 364.090 0.460 364.090 ; - RECT 0 364.550 0.460 364.550 ; - RECT 0 365.010 0.460 365.010 ; - RECT 0 365.470 0.460 365.470 ; - RECT 0 365.930 0.460 365.930 ; - RECT 0 366.390 0.460 366.390 ; - RECT 0 366.850 0.460 366.850 ; - RECT 0 367.310 0.460 367.310 ; - RECT 0 367.770 0.460 367.770 ; - RECT 0 368.230 0.460 368.230 ; - RECT 0 368.690 0.460 368.690 ; - RECT 0 369.150 0.460 369.150 ; - RECT 0 369.610 0.460 369.610 ; - RECT 0 370.070 0.460 370.070 ; - RECT 0 370.530 0.460 370.530 ; - RECT 0 370.990 0.460 370.990 ; - RECT 0 371.450 0.460 371.450 ; - RECT 0 371.910 0.460 371.910 ; - RECT 0 372.370 0.460 372.370 ; - RECT 0 372.830 0.460 372.830 ; - RECT 0 373.290 0.460 373.290 ; - RECT 0 373.750 0.460 373.750 ; - RECT 0 374.210 0.460 374.210 ; - RECT 0 374.670 0.460 374.670 ; - RECT 0 375.130 0.460 375.130 ; - RECT 0 375.590 0.460 375.590 ; - RECT 0 376.050 0.460 376.050 ; - RECT 0 376.510 0.460 376.510 ; - RECT 0 376.970 0.460 376.970 ; - RECT 0 377.430 0.460 377.430 ; - RECT 0 377.890 0.460 377.890 ; - RECT 0 378.350 0.460 378.350 ; - RECT 0 378.810 0.460 378.810 ; - RECT 0 379.270 0.460 379.270 ; - RECT 0 379.730 0.460 379.730 ; - RECT 0 380.190 0.460 380.190 ; - RECT 0 380.650 0.460 380.650 ; - RECT 0 381.110 0.460 381.110 ; - RECT 0 381.570 0.460 381.570 ; - RECT 0 382.030 0.460 382.030 ; - RECT 0 382.490 0.460 382.490 ; - RECT 0 382.950 0.460 382.950 ; - RECT 0 383.410 0.460 383.410 ; - RECT 0 383.870 0.460 383.870 ; - RECT 0 384.330 0.460 384.330 ; - RECT 0 384.790 0.460 384.790 ; - RECT 0 385.250 0.460 385.250 ; - RECT 0 385.710 0.460 385.710 ; - RECT 0 386.170 0.460 386.170 ; - RECT 0 386.630 0.460 386.630 ; - RECT 0 387.090 0.460 387.090 ; - RECT 0 387.550 0.460 387.550 ; - RECT 0 388.010 0.460 388.010 ; - RECT 0 388.470 0.460 388.470 ; - RECT 0 388.930 0.460 388.930 ; - RECT 0 389.390 0.460 389.390 ; - RECT 0 389.850 0.460 389.850 ; - RECT 0 390.310 0.460 390.310 ; - RECT 0 390.770 0.460 390.770 ; - RECT 0 391.230 0.460 391.230 ; - RECT 0 391.690 0.460 391.690 ; - RECT 0 392.150 0.460 392.150 ; - RECT 0 392.610 0.460 392.610 ; - RECT 0 393.070 0.460 393.070 ; - RECT 0 393.530 0.460 393.530 ; - RECT 0 393.990 0.460 393.990 ; - RECT 0 394.450 0.460 394.450 ; - RECT 0 394.910 0.460 394.910 ; - RECT 0 395.370 0.460 395.370 ; - RECT 0 395.830 0.460 395.830 ; - RECT 0 396.290 0.460 396.290 ; - RECT 0 396.750 0.460 396.750 ; - RECT 0 397.210 0.460 397.210 ; - RECT 0 397.670 0.460 397.670 ; - RECT 0 398.130 0.460 398.130 ; - RECT 0 398.590 0.460 398.590 ; - RECT 0 399.050 0.460 399.050 ; - RECT 0 399.510 0.460 399.510 ; - RECT 0 399.970 0.460 399.970 ; - RECT 0 400.430 0.460 400.430 ; - RECT 0 400.890 0.460 400.890 ; - RECT 0 401.350 0.460 401.350 ; - RECT 0 401.810 0.460 401.810 ; - RECT 0 402.270 0.460 402.270 ; - RECT 0 402.730 0.460 402.730 ; - RECT 0 403.190 0.460 403.190 ; - RECT 0 403.650 0.460 403.650 ; - RECT 0 404.110 0.460 404.110 ; - RECT 0 404.570 0.460 404.570 ; - RECT 0 405.030 0.460 405.030 ; - RECT 0 405.490 0.460 405.490 ; - RECT 0 405.950 0.460 405.950 ; - RECT 0 406.410 0.460 406.410 ; - RECT 0 406.870 0.460 406.870 ; - RECT 0 407.330 0.460 407.330 ; - RECT 0 407.790 0.460 407.790 ; - RECT 0 408.250 0.460 408.250 ; - RECT 0 408.710 0.460 408.710 ; - RECT 0 409.170 0.460 409.170 ; - RECT 0 409.630 0.460 409.630 ; - RECT 0 410.090 0.460 410.090 ; - RECT 0 410.550 0.460 410.550 ; - RECT 0 411.010 0.460 411.010 ; - RECT 0 411.470 0.460 411.470 ; - RECT 0 411.930 0.460 411.930 ; - RECT 0 412.390 0.460 412.390 ; - RECT 0 412.850 0.460 412.850 ; - RECT 0 413.310 0.460 413.310 ; - RECT 0 413.770 0.460 413.770 ; - RECT 0 414.230 0.460 414.230 ; - RECT 0 414.690 0.460 414.690 ; - RECT 0 415.150 0.460 415.150 ; - RECT 0 415.610 0.460 415.610 ; - RECT 0 416.070 0.460 416.070 ; - RECT 0 416.530 0.460 416.530 ; - RECT 0 416.990 0.460 416.990 ; - RECT 0 417.450 0.460 417.450 ; - RECT 0 417.910 0.460 417.910 ; - RECT 0 418.370 0.460 418.370 ; - RECT 0 418.830 0.460 418.830 ; - RECT 0 419.290 0.460 419.290 ; - RECT 0 419.750 0.460 419.750 ; - RECT 0 420.210 0.460 420.210 ; - RECT 0 420.670 0.460 420.670 ; - RECT 0 421.130 0.460 421.130 ; - RECT 0 421.590 0.460 421.590 ; - RECT 0 422.050 0.460 422.050 ; - RECT 0 422.510 0.460 422.510 ; - RECT 0 422.970 0.460 422.970 ; - RECT 0 423.430 0.460 423.430 ; - RECT 0 423.890 0.460 423.890 ; - RECT 0 424.350 0.460 424.350 ; - RECT 0 424.810 0.460 424.810 ; - RECT 0 425.270 0.460 425.270 ; - RECT 0 425.730 0.460 425.730 ; - RECT 0 426.190 0.460 426.190 ; - RECT 0 426.650 0.460 426.650 ; - RECT 0 427.110 0.460 427.110 ; - RECT 0 427.570 0.460 427.570 ; - RECT 0 428.030 0.460 428.030 ; - RECT 0 428.490 0.460 428.490 ; - RECT 0 428.950 0.460 428.950 ; - RECT 0 429.410 0.460 429.410 ; - RECT 0 429.870 0.460 429.870 ; - RECT 0 430.330 0.460 430.330 ; - RECT 0 430.790 0.460 430.790 ; - RECT 0 431.250 0.460 431.250 ; - RECT 0 431.710 0.460 431.710 ; - RECT 0 432.170 0.460 432.170 ; - RECT 0 432.630 0.460 432.630 ; - RECT 0 433.090 0.460 433.090 ; - RECT 0 433.550 0.460 433.550 ; - RECT 0 434.010 0.460 434.010 ; - RECT 0 434.470 0.460 434.470 ; - RECT 0 434.930 0.460 434.930 ; - RECT 0 435.390 0.460 435.390 ; - RECT 0 435.850 0.460 435.850 ; - RECT 0 436.310 0.460 436.310 ; - RECT 0 436.770 0.460 436.770 ; - RECT 0 437.230 0.460 437.230 ; - RECT 0 437.690 0.460 437.690 ; - RECT 0 438.150 0.460 438.150 ; - RECT 0 438.610 0.460 438.610 ; - RECT 0 439.070 0.460 439.070 ; - RECT 0 439.530 0.460 439.530 ; - RECT 0 439.990 0.460 439.990 ; - RECT 0 440.450 0.460 440.450 ; - RECT 0 440.910 0.460 440.910 ; - RECT 0 441.370 0.460 441.370 ; - RECT 0 441.830 0.460 441.830 ; - RECT 0 442.290 0.460 442.290 ; - RECT 0 442.750 0.460 442.750 ; - RECT 0 443.210 0.460 443.210 ; - RECT 0 443.670 0.460 443.670 ; - RECT 0 444.130 0.460 444.130 ; - RECT 0 444.590 0.460 444.590 ; - RECT 0 445.050 0.460 445.050 ; - RECT 0 445.510 0.460 445.510 ; - RECT 0 445.970 0.460 445.970 ; - RECT 0 446.430 0.460 446.430 ; - RECT 0 446.890 0.460 446.890 ; - RECT 0 447.350 0.460 447.350 ; - RECT 0 447.810 0.460 447.810 ; - RECT 0 448.270 0.460 448.270 ; - RECT 0 448.730 0.460 448.730 ; - RECT 0 449.190 0.460 449.190 ; - RECT 0 449.650 0.460 449.650 ; - RECT 0 450.110 0.460 450.110 ; - RECT 0 450.570 0.460 450.570 ; - RECT 0 451.030 0.460 451.030 ; - RECT 0 451.490 0.460 451.490 ; - RECT 0 451.950 0.460 451.950 ; - RECT 0 452.410 0.460 452.410 ; - RECT 0 452.870 0.460 452.870 ; - RECT 0 453.330 0.460 453.330 ; - RECT 0 453.790 0.460 453.790 ; - RECT 0 454.250 0.460 454.250 ; - RECT 0 454.710 0.460 454.710 ; - RECT 0 455.170 0.460 455.170 ; - RECT 0 455.630 0.460 455.630 ; - RECT 0 456.090 0.460 456.090 ; - RECT 0 456.550 0.460 456.550 ; - RECT 0 457.010 0.460 457.010 ; - RECT 0 457.470 0.460 457.470 ; - RECT 0 457.930 0.460 457.930 ; - RECT 0 458.390 0.460 458.390 ; - RECT 0 458.850 0.460 458.850 ; - RECT 0 459.310 0.460 459.310 ; - RECT 0 459.770 0.460 459.770 ; - RECT 0 460.230 0.460 460.230 ; - RECT 0 460.690 0.460 460.690 ; - RECT 0 461.150 0.460 461.150 ; - RECT 0 461.610 0.460 461.610 ; - RECT 0 462.070 0.460 462.070 ; - RECT 0 462.530 0.460 462.530 ; - RECT 0 462.990 0.460 462.990 ; - RECT 0 463.450 0.460 463.450 ; - RECT 0 463.910 0.460 463.910 ; - RECT 0 464.370 0.460 464.370 ; - RECT 0 464.830 0.460 464.830 ; - RECT 0 465.290 0.460 465.290 ; - RECT 0 465.750 0.460 465.750 ; - RECT 0 466.210 0.460 466.210 ; - RECT 0 466.670 0.460 466.670 ; - RECT 0 467.130 0.460 467.130 ; - RECT 0 467.590 0.460 467.590 ; - RECT 0 468.050 0.460 468.050 ; - RECT 0 468.510 0.460 468.510 ; - RECT 0 468.970 0.460 468.970 ; - RECT 0 469.430 0.460 469.430 ; - RECT 0 469.890 0.460 469.890 ; - RECT 0 470.350 0.460 470.350 ; - RECT 0 470.810 0.460 470.810 ; - RECT 0 471.270 0.460 471.270 ; - RECT 0 471.730 0.460 471.730 ; - RECT 0 472.190 0.460 472.190 ; - RECT 0 472.650 0.460 472.650 ; - RECT 0 473.110 0.460 473.110 ; - RECT 0 473.570 0.460 473.570 ; - RECT 0 474.030 0.460 474.030 ; - RECT 0 474.490 0.460 474.490 ; - RECT 0 474.950 0.460 474.950 ; - RECT 0 475.410 0.460 475.410 ; - RECT 0 475.870 0.460 475.870 ; - RECT 0 476.330 0.460 476.330 ; - RECT 0 476.790 0.460 476.790 ; - RECT 0 477.250 0.460 477.250 ; - RECT 0 477.710 0.460 477.710 ; - RECT 0 478.170 0.460 478.170 ; - RECT 0 478.630 0.460 478.630 ; - RECT 0 479.090 0.460 479.090 ; - RECT 0 479.550 0.460 479.550 ; - RECT 0 480.010 0.460 480.010 ; - RECT 0 480.470 0.460 480.470 ; - RECT 0 480.930 0.460 480.930 ; - RECT 0 481.390 0.460 481.390 ; - RECT 0 481.850 0.460 481.850 ; - RECT 0 482.310 0.460 482.310 ; - RECT 0 482.770 0.460 482.770 ; - RECT 0 483.230 0.460 483.230 ; - RECT 0 483.690 0.460 483.690 ; - RECT 0 484.150 0.460 484.150 ; - RECT 0 484.610 0.460 484.610 ; - RECT 0 485.070 0.460 485.070 ; - RECT 0 485.530 0.460 485.530 ; - RECT 0 485.990 0.460 485.990 ; - RECT 0 486.450 0.460 486.450 ; - RECT 0 486.910 0.460 486.910 ; - RECT 0 487.370 0.460 487.370 ; - RECT 0 487.830 0.460 487.830 ; - RECT 0 488.290 0.460 488.290 ; - RECT 0 488.750 0.460 488.750 ; - RECT 0 489.210 0.460 489.210 ; - RECT 0 489.670 0.460 489.670 ; - RECT 0 490.130 0.460 490.130 ; - RECT 0 490.590 0.460 490.590 ; - RECT 0 491.050 0.460 491.050 ; - RECT 0 491.510 0.460 491.510 ; - RECT 0 491.970 0.460 491.970 ; - RECT 0 492.430 0.460 492.430 ; - RECT 0 492.890 0.460 492.890 ; - RECT 0 493.350 0.460 493.350 ; - RECT 0 493.810 0.460 493.810 ; - RECT 0 494.270 0.460 494.270 ; - RECT 0 494.730 0.460 494.730 ; - RECT 0 495.190 0.460 495.190 ; - RECT 0 495.650 0.460 495.650 ; - RECT 0 496.110 0.460 496.110 ; - RECT 0 496.570 0.460 496.570 ; - RECT 0 497.030 0.460 497.030 ; - RECT 0 497.490 0.460 497.490 ; - RECT 0 497.950 0.460 497.950 ; - RECT 0 498.410 0.460 498.410 ; - RECT 0 498.870 0.460 498.870 ; - RECT 0 499.330 0.460 499.330 ; - RECT 0 499.790 0.460 499.790 ; - RECT 0 500.250 0.460 500.250 ; - RECT 0 500.710 0.460 500.710 ; - RECT 0 501.170 0.460 501.170 ; - RECT 0 501.630 0.460 501.630 ; - RECT 0 502.090 0.460 502.090 ; - RECT 0 502.550 0.460 502.550 ; - RECT 0 503.010 0.460 503.010 ; - RECT 0 503.470 0.460 503.470 ; - RECT 0 503.930 0.460 503.930 ; - RECT 0 504.390 0.460 504.390 ; - RECT 0 504.850 0.460 504.850 ; - RECT 0 505.310 0.460 505.310 ; - RECT 0 505.770 0.460 505.770 ; - RECT 0 506.230 0.460 506.230 ; - RECT 0 506.690 0.460 506.690 ; - RECT 0 507.150 0.460 507.150 ; - RECT 0 507.610 0.460 507.610 ; - RECT 0 508.070 0.460 508.070 ; - RECT 0 508.530 0.460 508.530 ; - RECT 0 508.990 0.460 508.990 ; - RECT 0 509.450 0.460 509.450 ; - RECT 0 509.910 0.460 509.910 ; - RECT 0 510.370 0.460 510.370 ; - RECT 0 510.830 0.460 510.830 ; - RECT 0 511.290 0.460 511.290 ; - RECT 0 511.750 0.460 511.750 ; - RECT 0 512.210 0.460 512.210 ; - RECT 0 512.670 0.460 512.670 ; - RECT 0 513.130 0.460 513.130 ; - RECT 0 513.590 0.460 513.590 ; - RECT 0 514.050 0.460 514.050 ; - RECT 0 514.510 0.460 514.510 ; - RECT 0 514.970 0.460 514.970 ; - RECT 0 515.430 0.460 515.430 ; - RECT 0 515.890 0.460 515.890 ; - RECT 0 516.350 0.460 516.350 ; - RECT 0 516.810 0.460 516.810 ; - RECT 0 517.270 0.460 517.270 ; - RECT 0 517.730 0.460 517.730 ; - RECT 0 518.190 0.460 518.190 ; - RECT 0 518.650 0.460 518.650 ; - RECT 0 519.110 0.460 519.110 ; - RECT 0 519.570 0.460 519.570 ; - RECT 0 520.030 0.460 520.030 ; - RECT 0 520.490 0.460 520.490 ; - RECT 0 520.950 0.460 520.950 ; - RECT 0 521.410 0.460 521.410 ; - RECT 0 521.870 0.460 521.870 ; - RECT 0 522.330 0.460 522.330 ; - RECT 0 522.790 0.460 522.790 ; - RECT 0 523.250 0.460 523.250 ; - RECT 0 523.710 0.460 523.710 ; - RECT 0 524.170 0.460 524.170 ; - RECT 0 524.630 0.460 524.630 ; - RECT 0 525.090 0.460 525.090 ; - RECT 0 525.550 0.460 525.550 ; - RECT 0 526.010 0.460 526.010 ; - RECT 0 526.470 0.460 526.470 ; - RECT 0 526.930 0.460 526.930 ; - RECT 0 527.390 0.460 527.390 ; - RECT 0 527.850 0.460 527.850 ; - RECT 0 528.310 0.460 528.310 ; - RECT 0 528.770 0.460 528.770 ; - RECT 0 529.230 0.460 529.230 ; - RECT 0 529.690 0.460 529.690 ; - RECT 0 530.150 0.460 530.150 ; - RECT 0 530.610 0.460 530.610 ; - RECT 0 531.070 0.460 531.070 ; - RECT 0 531.530 0.460 531.530 ; - RECT 0 531.990 0.460 531.990 ; - RECT 0 532.450 0.460 532.450 ; - RECT 0 532.910 0.460 532.910 ; - RECT 0 533.370 0.460 533.370 ; - RECT 0 533.830 0.460 533.830 ; - RECT 0 534.290 0.460 534.290 ; - RECT 0 534.750 0.460 534.750 ; - RECT 0 535.210 0.460 535.210 ; - RECT 0 535.670 0.460 535.670 ; - RECT 0 536.130 0.460 536.130 ; - RECT 0 536.590 0.460 536.590 ; - RECT 0 537.050 0.460 537.050 ; - RECT 0 537.510 0.460 537.510 ; - RECT 0 537.970 0.460 537.970 ; - RECT 0 538.430 0.460 538.430 ; - RECT 0 538.890 0.460 538.890 ; - RECT 0 539.350 0.460 539.350 ; - RECT 0 539.810 0.460 539.810 ; - RECT 0 540.270 0.460 540.270 ; - RECT 0 540.730 0.460 540.730 ; - RECT 0 541.190 0.460 541.190 ; - RECT 0 541.650 0.460 541.650 ; - RECT 0 542.110 0.460 542.110 ; - RECT 0 542.570 0.460 542.570 ; - RECT 0 543.030 0.460 543.030 ; - RECT 0 543.490 0.460 543.490 ; - RECT 0 543.950 0.460 543.950 ; - RECT 0 544.410 0.460 544.410 ; - RECT 0 544.870 0.460 544.870 ; - RECT 0 545.330 0.460 545.330 ; - RECT 0 545.790 0.460 545.790 ; - RECT 0 546.250 0.460 546.250 ; - RECT 0 546.710 0.460 546.710 ; - RECT 0 547.170 0.460 547.170 ; - RECT 0 547.630 0.460 547.630 ; - RECT 0 548.090 0.460 548.090 ; - RECT 0 548.550 0.460 548.550 ; - RECT 0 549.010 0.460 549.010 ; - RECT 0 549.470 0.460 549.470 ; - RECT 0 549.930 0.460 549.930 ; - RECT 0 550.390 0.460 550.390 ; - RECT 0 550.850 0.460 550.850 ; - RECT 0 551.310 0.460 551.310 ; - RECT 0 551.770 0.460 551.770 ; - RECT 0 552.230 0.460 552.230 ; - RECT 0 552.690 0.460 552.690 ; - RECT 0 553.150 0.460 553.150 ; - RECT 0 553.610 0.460 553.610 ; - RECT 0 554.070 0.460 554.070 ; - RECT 0 554.530 0.460 554.530 ; - RECT 0 554.990 0.460 554.990 ; - RECT 0 555.450 0.460 555.450 ; - RECT 0 555.910 0.460 555.910 ; - RECT 0 556.370 0.460 556.370 ; - RECT 0 556.830 0.460 556.830 ; - RECT 0 557.290 0.460 557.290 ; - RECT 0 557.750 0.460 640.090 ; - RECT 0 640.550 0.460 640.550 ; - RECT 0 641.010 0.460 641.010 ; - RECT 0 641.470 0.460 641.470 ; - RECT 0 641.930 0.460 641.930 ; - RECT 0 642.390 0.460 642.390 ; - RECT 0 642.850 0.460 642.850 ; - RECT 0 643.310 0.460 643.310 ; - RECT 0 643.770 0.460 643.770 ; - RECT 0 644.230 0.460 644.230 ; - RECT 0 644.690 0.460 644.690 ; - RECT 0 645.150 0.460 645.150 ; - RECT 0 645.610 0.460 645.610 ; - RECT 0 646.070 0.460 646.070 ; - RECT 0 646.530 0.460 646.530 ; - RECT 0 646.990 0.460 646.990 ; - RECT 0 647.450 0.460 647.450 ; - RECT 0 647.910 0.460 647.910 ; - RECT 0 648.370 0.460 648.370 ; - RECT 0 648.830 0.460 648.830 ; - RECT 0 649.290 0.460 649.290 ; - RECT 0 649.750 0.460 649.750 ; - RECT 0 650.210 0.460 650.210 ; - RECT 0 650.670 0.460 650.670 ; - RECT 0 651.130 0.460 651.130 ; - RECT 0 651.590 0.460 651.590 ; - RECT 0 652.050 0.460 652.050 ; - RECT 0 652.510 0.460 652.510 ; - RECT 0 652.970 0.460 652.970 ; - RECT 0 653.430 0.460 653.430 ; - RECT 0 653.890 0.460 653.890 ; - RECT 0 654.350 0.460 654.350 ; - RECT 0 654.810 0.460 654.810 ; - RECT 0 655.270 0.460 655.270 ; - RECT 0 655.730 0.460 655.730 ; - RECT 0 656.190 0.460 656.190 ; - RECT 0 656.650 0.460 656.650 ; - RECT 0 657.110 0.460 657.110 ; - RECT 0 657.570 0.460 657.570 ; - RECT 0 658.030 0.460 658.030 ; - RECT 0 658.490 0.460 658.490 ; - RECT 0 658.950 0.460 658.950 ; - RECT 0 659.410 0.460 659.410 ; - RECT 0 659.870 0.460 659.870 ; - RECT 0 660.330 0.460 660.330 ; - RECT 0 660.790 0.460 660.790 ; - RECT 0 661.250 0.460 661.250 ; - RECT 0 661.710 0.460 661.710 ; - RECT 0 662.170 0.460 662.170 ; - RECT 0 662.630 0.460 662.630 ; - RECT 0 663.090 0.460 663.090 ; - RECT 0 663.550 0.460 663.550 ; - RECT 0 664.010 0.460 664.010 ; - RECT 0 664.470 0.460 664.470 ; - RECT 0 664.930 0.460 664.930 ; - RECT 0 665.390 0.460 665.390 ; - RECT 0 665.850 0.460 665.850 ; - RECT 0 666.310 0.460 666.310 ; - RECT 0 666.770 0.460 666.770 ; - RECT 0 667.230 0.460 667.230 ; - RECT 0 667.690 0.460 667.690 ; - RECT 0 668.150 0.460 668.150 ; - RECT 0 668.610 0.460 668.610 ; - RECT 0 669.070 0.460 669.070 ; - RECT 0 669.530 0.460 669.530 ; - RECT 0 669.990 0.460 669.990 ; - RECT 0 670.450 0.460 670.450 ; - RECT 0 670.910 0.460 670.910 ; - RECT 0 671.370 0.460 671.370 ; - RECT 0 671.830 0.460 671.830 ; - RECT 0 672.290 0.460 672.290 ; - RECT 0 672.750 0.460 672.750 ; - RECT 0 673.210 0.460 673.210 ; - RECT 0 673.670 0.460 673.670 ; - RECT 0 674.130 0.460 674.130 ; - RECT 0 674.590 0.460 674.590 ; - RECT 0 675.050 0.460 675.050 ; - RECT 0 675.510 0.460 675.510 ; - RECT 0 675.970 0.460 675.970 ; - RECT 0 676.430 0.460 676.430 ; - RECT 0 676.890 0.460 676.890 ; - RECT 0 677.350 0.460 677.350 ; - RECT 0 677.810 0.460 677.810 ; - RECT 0 678.270 0.460 678.270 ; - RECT 0 678.730 0.460 678.730 ; - RECT 0 679.190 0.460 679.190 ; - RECT 0 679.650 0.460 679.650 ; - RECT 0 680.110 0.460 680.110 ; - RECT 0 680.570 0.460 680.570 ; - RECT 0 681.030 0.460 681.030 ; - RECT 0 681.490 0.460 681.490 ; - RECT 0 681.950 0.460 681.950 ; - RECT 0 682.410 0.460 682.410 ; - RECT 0 682.870 0.460 682.870 ; - RECT 0 683.330 0.460 683.330 ; - RECT 0 683.790 0.460 683.790 ; - RECT 0 684.250 0.460 684.250 ; - RECT 0 684.710 0.460 684.710 ; - RECT 0 685.170 0.460 685.170 ; - RECT 0 685.630 0.460 685.630 ; - RECT 0 686.090 0.460 686.090 ; - RECT 0 686.550 0.460 686.550 ; - RECT 0 687.010 0.460 687.010 ; - RECT 0 687.470 0.460 687.470 ; - RECT 0 687.930 0.460 687.930 ; - RECT 0 688.390 0.460 688.390 ; - RECT 0 688.850 0.460 688.850 ; - RECT 0 689.310 0.460 689.310 ; - RECT 0 689.770 0.460 689.770 ; - RECT 0 690.230 0.460 690.230 ; - RECT 0 690.690 0.460 690.690 ; - RECT 0 691.150 0.460 691.150 ; - RECT 0 691.610 0.460 691.610 ; - RECT 0 692.070 0.460 692.070 ; - RECT 0 692.530 0.460 692.530 ; - RECT 0 692.990 0.460 692.990 ; - RECT 0 693.450 0.460 693.450 ; - RECT 0 693.910 0.460 693.910 ; - RECT 0 694.370 0.460 694.370 ; - RECT 0 694.830 0.460 694.830 ; - RECT 0 695.290 0.460 695.290 ; - RECT 0 695.750 0.460 695.750 ; - RECT 0 696.210 0.460 696.210 ; - RECT 0 696.670 0.460 696.670 ; - RECT 0 697.130 0.460 697.130 ; - RECT 0 697.590 0.460 697.590 ; - RECT 0 698.050 0.460 698.050 ; - RECT 0 698.510 0.460 698.510 ; - RECT 0 698.970 0.460 698.970 ; - RECT 0 699.430 0.460 699.430 ; - RECT 0 699.890 0.460 699.890 ; - RECT 0 700.350 0.460 700.350 ; - RECT 0 700.810 0.460 700.810 ; - RECT 0 701.270 0.460 701.270 ; - RECT 0 701.730 0.460 701.730 ; - RECT 0 702.190 0.460 702.190 ; - RECT 0 702.650 0.460 702.650 ; - RECT 0 703.110 0.460 703.110 ; - RECT 0 703.570 0.460 703.570 ; - RECT 0 704.030 0.460 704.030 ; - RECT 0 704.490 0.460 704.490 ; - RECT 0 704.950 0.460 704.950 ; - RECT 0 705.410 0.460 705.410 ; - RECT 0 705.870 0.460 705.870 ; - RECT 0 706.330 0.460 706.330 ; - RECT 0 706.790 0.460 706.790 ; - RECT 0 707.250 0.460 707.250 ; - RECT 0 707.710 0.460 707.710 ; - RECT 0 708.170 0.460 708.170 ; - RECT 0 708.630 0.460 708.630 ; - RECT 0 709.090 0.460 709.090 ; - RECT 0 709.550 0.460 709.550 ; - RECT 0 710.010 0.460 710.010 ; - RECT 0 710.470 0.460 710.470 ; - RECT 0 710.930 0.460 710.930 ; - RECT 0 711.390 0.460 711.390 ; - RECT 0 711.850 0.460 711.850 ; - RECT 0 712.310 0.460 712.310 ; - RECT 0 712.770 0.460 712.770 ; - RECT 0 713.230 0.460 713.230 ; - RECT 0 713.690 0.460 713.690 ; - RECT 0 714.150 0.460 714.150 ; - RECT 0 714.610 0.460 714.610 ; - RECT 0 715.070 0.460 715.070 ; - RECT 0 715.530 0.460 715.530 ; - RECT 0 715.990 0.460 715.990 ; - RECT 0 716.450 0.460 716.450 ; - RECT 0 716.910 0.460 716.910 ; - RECT 0 717.370 0.460 717.370 ; - RECT 0 717.830 0.460 717.830 ; - RECT 0 718.290 0.460 718.290 ; - RECT 0 718.750 0.460 718.750 ; - RECT 0 719.210 0.460 719.210 ; - RECT 0 719.670 0.460 719.670 ; - RECT 0 720.130 0.460 720.130 ; - RECT 0 720.590 0.460 720.590 ; - RECT 0 721.050 0.460 721.050 ; - RECT 0 721.510 0.460 721.510 ; - RECT 0 721.970 0.460 721.970 ; - RECT 0 722.430 0.460 722.430 ; - RECT 0 722.890 0.460 722.890 ; - RECT 0 723.350 0.460 723.350 ; - RECT 0 723.810 0.460 723.810 ; - RECT 0 724.270 0.460 724.270 ; - RECT 0 724.730 0.460 724.730 ; - RECT 0 725.190 0.460 725.190 ; - RECT 0 725.650 0.460 725.650 ; - RECT 0 726.110 0.460 726.110 ; - RECT 0 726.570 0.460 726.570 ; - RECT 0 727.030 0.460 727.030 ; - RECT 0 727.490 0.460 727.490 ; - RECT 0 727.950 0.460 727.950 ; - RECT 0 728.410 0.460 728.410 ; - RECT 0 728.870 0.460 728.870 ; - RECT 0 729.330 0.460 729.330 ; - RECT 0 729.790 0.460 729.790 ; - RECT 0 730.250 0.460 730.250 ; - RECT 0 730.710 0.460 730.710 ; - RECT 0 731.170 0.460 731.170 ; - RECT 0 731.630 0.460 731.630 ; - RECT 0 732.090 0.460 732.090 ; - RECT 0 732.550 0.460 732.550 ; - RECT 0 733.010 0.460 733.010 ; - RECT 0 733.470 0.460 733.470 ; - RECT 0 733.930 0.460 733.930 ; - RECT 0 734.390 0.460 734.390 ; - RECT 0 734.850 0.460 734.850 ; - RECT 0 735.310 0.460 735.310 ; - RECT 0 735.770 0.460 735.770 ; - RECT 0 736.230 0.460 736.230 ; - RECT 0 736.690 0.460 736.690 ; - RECT 0 737.150 0.460 737.150 ; - RECT 0 737.610 0.460 737.610 ; - RECT 0 738.070 0.460 738.070 ; - RECT 0 738.530 0.460 738.530 ; - RECT 0 738.990 0.460 738.990 ; - RECT 0 739.450 0.460 739.450 ; - RECT 0 739.910 0.460 739.910 ; - RECT 0 740.370 0.460 740.370 ; - RECT 0 740.830 0.460 740.830 ; - RECT 0 741.290 0.460 741.290 ; - RECT 0 741.750 0.460 741.750 ; - RECT 0 742.210 0.460 742.210 ; - RECT 0 742.670 0.460 742.670 ; - RECT 0 743.130 0.460 743.130 ; - RECT 0 743.590 0.460 743.590 ; - RECT 0 744.050 0.460 744.050 ; - RECT 0 744.510 0.460 744.510 ; - RECT 0 744.970 0.460 744.970 ; - RECT 0 745.430 0.460 745.430 ; - RECT 0 745.890 0.460 745.890 ; - RECT 0 746.350 0.460 746.350 ; - RECT 0 746.810 0.460 746.810 ; - RECT 0 747.270 0.460 747.270 ; - RECT 0 747.730 0.460 747.730 ; - RECT 0 748.190 0.460 748.190 ; - RECT 0 748.650 0.460 748.650 ; - RECT 0 749.110 0.460 749.110 ; - RECT 0 749.570 0.460 749.570 ; - RECT 0 750.030 0.460 750.030 ; - RECT 0 750.490 0.460 750.490 ; - RECT 0 750.950 0.460 750.950 ; - RECT 0 751.410 0.460 751.410 ; - RECT 0 751.870 0.460 751.870 ; - RECT 0 752.330 0.460 752.330 ; - RECT 0 752.790 0.460 752.790 ; - RECT 0 753.250 0.460 753.250 ; - RECT 0 753.710 0.460 753.710 ; - RECT 0 754.170 0.460 754.170 ; - RECT 0 754.630 0.460 754.630 ; - RECT 0 755.090 0.460 755.090 ; - RECT 0 755.550 0.460 755.550 ; - RECT 0 756.010 0.460 756.010 ; - RECT 0 756.470 0.460 756.470 ; - RECT 0 756.930 0.460 756.930 ; - RECT 0 757.390 0.460 757.390 ; - RECT 0 757.850 0.460 757.850 ; - RECT 0 758.310 0.460 758.310 ; - RECT 0 758.770 0.460 758.770 ; - RECT 0 759.230 0.460 759.230 ; - RECT 0 759.690 0.460 759.690 ; - RECT 0 760.150 0.460 760.150 ; - RECT 0 760.610 0.460 760.610 ; - RECT 0 761.070 0.460 761.070 ; - RECT 0 761.530 0.460 761.530 ; - RECT 0 761.990 0.460 761.990 ; - RECT 0 762.450 0.460 762.450 ; - RECT 0 762.910 0.460 762.910 ; - RECT 0 763.370 0.460 763.370 ; - RECT 0 763.830 0.460 763.830 ; - RECT 0 764.290 0.460 764.290 ; - RECT 0 764.750 0.460 764.750 ; - RECT 0 765.210 0.460 765.210 ; - RECT 0 765.670 0.460 765.670 ; - RECT 0 766.130 0.460 766.130 ; - RECT 0 766.590 0.460 766.590 ; - RECT 0 767.050 0.460 767.050 ; - RECT 0 767.510 0.460 767.510 ; - RECT 0 767.970 0.460 767.970 ; - RECT 0 768.430 0.460 768.430 ; - RECT 0 768.890 0.460 768.890 ; - RECT 0 769.350 0.460 769.350 ; - RECT 0 769.810 0.460 769.810 ; - RECT 0 770.270 0.460 770.270 ; - RECT 0 770.730 0.460 770.730 ; - RECT 0 771.190 0.460 771.190 ; - RECT 0 771.650 0.460 771.650 ; - RECT 0 772.110 0.460 772.110 ; - RECT 0 772.570 0.460 772.570 ; - RECT 0 773.030 0.460 773.030 ; - RECT 0 773.490 0.460 773.490 ; - RECT 0 773.950 0.460 773.950 ; - RECT 0 774.410 0.460 774.410 ; - RECT 0 774.870 0.460 774.870 ; - RECT 0 775.330 0.460 775.330 ; - RECT 0 775.790 0.460 775.790 ; - RECT 0 776.250 0.460 776.250 ; - RECT 0 776.710 0.460 776.710 ; - RECT 0 777.170 0.460 777.170 ; - RECT 0 777.630 0.460 777.630 ; - RECT 0 778.090 0.460 778.090 ; - RECT 0 778.550 0.460 778.550 ; - RECT 0 779.010 0.460 779.010 ; - RECT 0 779.470 0.460 779.470 ; - RECT 0 779.930 0.460 779.930 ; - RECT 0 780.390 0.460 780.390 ; - RECT 0 780.850 0.460 780.850 ; - RECT 0 781.310 0.460 781.310 ; - RECT 0 781.770 0.460 781.770 ; - RECT 0 782.230 0.460 782.230 ; - RECT 0 782.690 0.460 782.690 ; - RECT 0 783.150 0.460 783.150 ; - RECT 0 783.610 0.460 783.610 ; - RECT 0 784.070 0.460 784.070 ; - RECT 0 784.530 0.460 784.530 ; - RECT 0 784.990 0.460 784.990 ; - RECT 0 785.450 0.460 785.450 ; - RECT 0 785.910 0.460 785.910 ; - RECT 0 786.370 0.460 786.370 ; - RECT 0 786.830 0.460 786.830 ; - RECT 0 787.290 0.460 787.290 ; - RECT 0 787.750 0.460 787.750 ; - RECT 0 788.210 0.460 788.210 ; - RECT 0 788.670 0.460 788.670 ; - RECT 0 789.130 0.460 789.130 ; - RECT 0 789.590 0.460 789.590 ; - RECT 0 790.050 0.460 790.050 ; - RECT 0 790.510 0.460 790.510 ; - RECT 0 790.970 0.460 790.970 ; - RECT 0 791.430 0.460 791.430 ; - RECT 0 791.890 0.460 791.890 ; - RECT 0 792.350 0.460 792.350 ; - RECT 0 792.810 0.460 792.810 ; - RECT 0 793.270 0.460 793.270 ; - RECT 0 793.730 0.460 793.730 ; - RECT 0 794.190 0.460 794.190 ; - RECT 0 794.650 0.460 794.650 ; - RECT 0 795.110 0.460 795.110 ; - RECT 0 795.570 0.460 795.570 ; - RECT 0 796.030 0.460 796.030 ; - RECT 0 796.490 0.460 796.490 ; - RECT 0 796.950 0.460 796.950 ; - RECT 0 797.410 0.460 797.410 ; - RECT 0 797.870 0.460 797.870 ; - RECT 0 798.330 0.460 798.330 ; - RECT 0 798.790 0.460 798.790 ; - RECT 0 799.250 0.460 799.250 ; - RECT 0 799.710 0.460 799.710 ; - RECT 0 800.170 0.460 800.170 ; - RECT 0 800.630 0.460 800.630 ; - RECT 0 801.090 0.460 801.090 ; - RECT 0 801.550 0.460 801.550 ; - RECT 0 802.010 0.460 802.010 ; - RECT 0 802.470 0.460 802.470 ; - RECT 0 802.930 0.460 802.930 ; - RECT 0 803.390 0.460 803.390 ; - RECT 0 803.850 0.460 803.850 ; - RECT 0 804.310 0.460 804.310 ; - RECT 0 804.770 0.460 804.770 ; - RECT 0 805.230 0.460 805.230 ; - RECT 0 805.690 0.460 805.690 ; - RECT 0 806.150 0.460 806.150 ; - RECT 0 806.610 0.460 806.610 ; - RECT 0 807.070 0.460 807.070 ; - RECT 0 807.530 0.460 807.530 ; - RECT 0 807.990 0.460 807.990 ; - RECT 0 808.450 0.460 808.450 ; - RECT 0 808.910 0.460 808.910 ; - RECT 0 809.370 0.460 809.370 ; - RECT 0 809.830 0.460 809.830 ; - RECT 0 810.290 0.460 810.290 ; - RECT 0 810.750 0.460 810.750 ; - RECT 0 811.210 0.460 811.210 ; - RECT 0 811.670 0.460 811.670 ; - RECT 0 812.130 0.460 812.130 ; - RECT 0 812.590 0.460 812.590 ; - RECT 0 813.050 0.460 813.050 ; - RECT 0 813.510 0.460 813.510 ; - RECT 0 813.970 0.460 813.970 ; - RECT 0 814.430 0.460 814.430 ; - RECT 0 814.890 0.460 814.890 ; - RECT 0 815.350 0.460 815.350 ; - RECT 0 815.810 0.460 815.810 ; - RECT 0 816.270 0.460 816.270 ; - RECT 0 816.730 0.460 816.730 ; - RECT 0 817.190 0.460 817.190 ; - RECT 0 817.650 0.460 817.650 ; - RECT 0 818.110 0.460 818.110 ; - RECT 0 818.570 0.460 818.570 ; - RECT 0 819.030 0.460 819.030 ; - RECT 0 819.490 0.460 819.490 ; - RECT 0 819.950 0.460 819.950 ; - RECT 0 820.410 0.460 820.410 ; - RECT 0 820.870 0.460 820.870 ; - RECT 0 821.330 0.460 821.330 ; - RECT 0 821.790 0.460 821.790 ; - RECT 0 822.250 0.460 822.250 ; - RECT 0 822.710 0.460 822.710 ; - RECT 0 823.170 0.460 823.170 ; - RECT 0 823.630 0.460 823.630 ; - RECT 0 824.090 0.460 824.090 ; - RECT 0 824.550 0.460 824.550 ; - RECT 0 825.010 0.460 825.010 ; - RECT 0 825.470 0.460 825.470 ; - RECT 0 825.930 0.460 825.930 ; - RECT 0 826.390 0.460 826.390 ; - RECT 0 826.850 0.460 826.850 ; - RECT 0 827.310 0.460 827.310 ; - RECT 0 827.770 0.460 827.770 ; - RECT 0 828.230 0.460 828.230 ; - RECT 0 828.690 0.460 828.690 ; - RECT 0 829.150 0.460 829.150 ; - RECT 0 829.610 0.460 829.610 ; - RECT 0 830.070 0.460 830.070 ; - RECT 0 830.530 0.460 830.530 ; - RECT 0 830.990 0.460 830.990 ; - RECT 0 831.450 0.460 831.450 ; - RECT 0 831.910 0.460 831.910 ; - RECT 0 832.370 0.460 832.370 ; - RECT 0 832.830 0.460 832.830 ; - RECT 0 833.290 0.460 833.290 ; - RECT 0 833.750 0.460 833.750 ; - RECT 0 834.210 0.460 834.210 ; - RECT 0 834.670 0.460 834.670 ; - RECT 0 835.130 0.460 835.130 ; - RECT 0 835.590 0.460 835.590 ; - RECT 0 836.050 0.460 836.050 ; - RECT 0 836.510 0.460 836.510 ; - RECT 0 836.970 0.460 836.970 ; - RECT 0 837.430 0.460 837.430 ; - RECT 0 837.890 0.460 837.890 ; - RECT 0 838.350 0.460 838.350 ; - RECT 0 838.810 0.460 838.810 ; - RECT 0 839.270 0.460 839.270 ; - RECT 0 839.730 0.460 839.730 ; - RECT 0 840.190 0.460 840.190 ; - RECT 0 840.650 0.460 840.650 ; - RECT 0 841.110 0.460 841.110 ; - RECT 0 841.570 0.460 841.570 ; - RECT 0 842.030 0.460 842.030 ; - RECT 0 842.490 0.460 842.490 ; - RECT 0 842.950 0.460 842.950 ; - RECT 0 843.410 0.460 843.410 ; - RECT 0 843.870 0.460 843.870 ; - RECT 0 844.330 0.460 844.330 ; - RECT 0 844.790 0.460 844.790 ; - RECT 0 845.250 0.460 845.250 ; - RECT 0 845.710 0.460 845.710 ; - RECT 0 846.170 0.460 846.170 ; - RECT 0 846.630 0.460 846.630 ; - RECT 0 847.090 0.460 847.090 ; - RECT 0 847.550 0.460 847.550 ; - RECT 0 848.010 0.460 848.010 ; - RECT 0 848.470 0.460 848.470 ; - RECT 0 848.930 0.460 848.930 ; - RECT 0 849.390 0.460 849.390 ; - RECT 0 849.850 0.460 849.850 ; - RECT 0 850.310 0.460 850.310 ; - RECT 0 850.770 0.460 850.770 ; - RECT 0 851.230 0.460 851.230 ; - RECT 0 851.690 0.460 851.690 ; - RECT 0 852.150 0.460 852.150 ; - RECT 0 852.610 0.460 852.610 ; - RECT 0 853.070 0.460 853.070 ; - RECT 0 853.530 0.460 853.530 ; - RECT 0 853.990 0.460 853.990 ; - RECT 0 854.450 0.460 854.450 ; - RECT 0 854.910 0.460 854.910 ; - RECT 0 855.370 0.460 855.370 ; - RECT 0 855.830 0.460 855.830 ; - RECT 0 856.290 0.460 856.290 ; - RECT 0 856.750 0.460 856.750 ; - RECT 0 857.210 0.460 857.210 ; - RECT 0 857.670 0.460 857.670 ; - RECT 0 858.130 0.460 858.130 ; - RECT 0 858.590 0.460 858.590 ; - RECT 0 859.050 0.460 859.050 ; - RECT 0 859.510 0.460 859.510 ; - RECT 0 859.970 0.460 859.970 ; - RECT 0 860.430 0.460 860.430 ; - RECT 0 860.890 0.460 860.890 ; - RECT 0 861.350 0.460 861.350 ; - RECT 0 861.810 0.460 861.810 ; - RECT 0 862.270 0.460 862.270 ; - RECT 0 862.730 0.460 862.730 ; - RECT 0 863.190 0.460 863.190 ; - RECT 0 863.650 0.460 863.650 ; - RECT 0 864.110 0.460 864.110 ; - RECT 0 864.570 0.460 864.570 ; - RECT 0 865.030 0.460 865.030 ; - RECT 0 865.490 0.460 865.490 ; - RECT 0 865.950 0.460 865.950 ; - RECT 0 866.410 0.460 866.410 ; - RECT 0 866.870 0.460 866.870 ; - RECT 0 867.330 0.460 867.330 ; - RECT 0 867.790 0.460 867.790 ; - RECT 0 868.250 0.460 868.250 ; - RECT 0 868.710 0.460 868.710 ; - RECT 0 869.170 0.460 869.170 ; - RECT 0 869.630 0.460 869.630 ; - RECT 0 870.090 0.460 870.090 ; - RECT 0 870.550 0.460 870.550 ; - RECT 0 871.010 0.460 871.010 ; - RECT 0 871.470 0.460 871.470 ; - RECT 0 871.930 0.460 871.930 ; - RECT 0 872.390 0.460 872.390 ; - RECT 0 872.850 0.460 872.850 ; - RECT 0 873.310 0.460 873.310 ; - RECT 0 873.770 0.460 873.770 ; - RECT 0 874.230 0.460 874.230 ; - RECT 0 874.690 0.460 874.690 ; - RECT 0 875.150 0.460 875.150 ; - RECT 0 875.610 0.460 957.950 ; - RECT 0 958.410 0.460 958.410 ; - RECT 0 958.870 0.460 958.870 ; - RECT 0 959.330 0.460 959.330 ; - RECT 0 959.790 0.460 959.790 ; - RECT 0 960.250 0.460 960.250 ; - RECT 0 960.710 0.460 960.710 ; - RECT 0 961.170 0.460 961.170 ; - RECT 0 961.630 0.460 1043.970 ; - RECT 0 1044.430 0.460 1044.430 ; - RECT 0 1044.890 0.460 1044.890 ; - RECT 0 1045.350 0.460 1052.640 ; - LAYER met4 ; - RECT 0 0 834.440 4.600 ; - RECT 0 1048.040 834.440 1052.640 ; - RECT 0.000 4.600 3.680 1048.040 ; - RECT 5.520 4.600 7.360 1048.040 ; - RECT 9.200 4.600 11.040 1048.040 ; - RECT 12.880 4.600 14.720 1048.040 ; - RECT 16.560 4.600 18.400 1048.040 ; - RECT 20.240 4.600 22.080 1048.040 ; - RECT 23.920 4.600 25.760 1048.040 ; - RECT 27.600 4.600 29.440 1048.040 ; - RECT 31.280 4.600 33.120 1048.040 ; - RECT 34.960 4.600 36.800 1048.040 ; - RECT 38.640 4.600 40.480 1048.040 ; - RECT 42.320 4.600 44.160 1048.040 ; - RECT 46.000 4.600 47.840 1048.040 ; - RECT 49.680 4.600 51.520 1048.040 ; - RECT 53.360 4.600 55.200 1048.040 ; - RECT 57.040 4.600 58.880 1048.040 ; - RECT 60.720 4.600 62.560 1048.040 ; - RECT 64.400 4.600 66.240 1048.040 ; - RECT 68.080 4.600 69.920 1048.040 ; - RECT 71.760 4.600 73.600 1048.040 ; - RECT 75.440 4.600 77.280 1048.040 ; - RECT 79.120 4.600 80.960 1048.040 ; - RECT 82.800 4.600 84.640 1048.040 ; - RECT 86.480 4.600 88.320 1048.040 ; - RECT 90.160 4.600 92.000 1048.040 ; - RECT 93.840 4.600 95.680 1048.040 ; - RECT 97.520 4.600 99.360 1048.040 ; - RECT 101.200 4.600 103.040 1048.040 ; - RECT 104.880 4.600 106.720 1048.040 ; - RECT 108.560 4.600 110.400 1048.040 ; - RECT 112.240 4.600 114.080 1048.040 ; - RECT 115.920 4.600 117.760 1048.040 ; - RECT 119.600 4.600 121.440 1048.040 ; - RECT 123.280 4.600 125.120 1048.040 ; - RECT 126.960 4.600 128.800 1048.040 ; - RECT 130.640 4.600 132.480 1048.040 ; - RECT 134.320 4.600 136.160 1048.040 ; - RECT 138.000 4.600 139.840 1048.040 ; - RECT 141.680 4.600 143.520 1048.040 ; - RECT 145.360 4.600 147.200 1048.040 ; - RECT 149.040 4.600 150.880 1048.040 ; - RECT 152.720 4.600 154.560 1048.040 ; - RECT 156.400 4.600 158.240 1048.040 ; - RECT 160.080 4.600 161.920 1048.040 ; - RECT 163.760 4.600 165.600 1048.040 ; - RECT 167.440 4.600 169.280 1048.040 ; - RECT 171.120 4.600 172.960 1048.040 ; - RECT 174.800 4.600 176.640 1048.040 ; - RECT 178.480 4.600 180.320 1048.040 ; - RECT 182.160 4.600 184.000 1048.040 ; - RECT 185.840 4.600 187.680 1048.040 ; - RECT 189.520 4.600 191.360 1048.040 ; - RECT 193.200 4.600 195.040 1048.040 ; - RECT 196.880 4.600 198.720 1048.040 ; - RECT 200.560 4.600 202.400 1048.040 ; - RECT 204.240 4.600 206.080 1048.040 ; - RECT 207.920 4.600 209.760 1048.040 ; - RECT 211.600 4.600 213.440 1048.040 ; - RECT 215.280 4.600 217.120 1048.040 ; - RECT 218.960 4.600 220.800 1048.040 ; - RECT 222.640 4.600 224.480 1048.040 ; - RECT 226.320 4.600 228.160 1048.040 ; - RECT 230.000 4.600 231.840 1048.040 ; - RECT 233.680 4.600 235.520 1048.040 ; - RECT 237.360 4.600 239.200 1048.040 ; - RECT 241.040 4.600 242.880 1048.040 ; - RECT 244.720 4.600 246.560 1048.040 ; - RECT 248.400 4.600 250.240 1048.040 ; - RECT 252.080 4.600 253.920 1048.040 ; - RECT 255.760 4.600 257.600 1048.040 ; - RECT 259.440 4.600 261.280 1048.040 ; - RECT 263.120 4.600 264.960 1048.040 ; - RECT 266.800 4.600 268.640 1048.040 ; - RECT 270.480 4.600 272.320 1048.040 ; - RECT 274.160 4.600 276.000 1048.040 ; - RECT 277.840 4.600 279.680 1048.040 ; - RECT 281.520 4.600 283.360 1048.040 ; - RECT 285.200 4.600 287.040 1048.040 ; - RECT 288.880 4.600 290.720 1048.040 ; - RECT 292.560 4.600 294.400 1048.040 ; - RECT 296.240 4.600 298.080 1048.040 ; - RECT 299.920 4.600 301.760 1048.040 ; - RECT 303.600 4.600 305.440 1048.040 ; - RECT 307.280 4.600 309.120 1048.040 ; - RECT 310.960 4.600 312.800 1048.040 ; - RECT 314.640 4.600 316.480 1048.040 ; - RECT 318.320 4.600 320.160 1048.040 ; - RECT 322.000 4.600 323.840 1048.040 ; - RECT 325.680 4.600 327.520 1048.040 ; - RECT 329.360 4.600 331.200 1048.040 ; - RECT 333.040 4.600 334.880 1048.040 ; - RECT 336.720 4.600 338.560 1048.040 ; - RECT 340.400 4.600 342.240 1048.040 ; - RECT 344.080 4.600 345.920 1048.040 ; - RECT 347.760 4.600 349.600 1048.040 ; - RECT 351.440 4.600 353.280 1048.040 ; - RECT 355.120 4.600 356.960 1048.040 ; - RECT 358.800 4.600 360.640 1048.040 ; - RECT 362.480 4.600 364.320 1048.040 ; - RECT 366.160 4.600 368.000 1048.040 ; - RECT 369.840 4.600 371.680 1048.040 ; - RECT 373.520 4.600 375.360 1048.040 ; - RECT 377.200 4.600 379.040 1048.040 ; - RECT 380.880 4.600 382.720 1048.040 ; - RECT 384.560 4.600 386.400 1048.040 ; - RECT 388.240 4.600 390.080 1048.040 ; - RECT 391.920 4.600 393.760 1048.040 ; - RECT 395.600 4.600 397.440 1048.040 ; - RECT 399.280 4.600 401.120 1048.040 ; - RECT 402.960 4.600 404.800 1048.040 ; - RECT 406.640 4.600 408.480 1048.040 ; - RECT 410.320 4.600 412.160 1048.040 ; - RECT 414.000 4.600 415.840 1048.040 ; - RECT 417.680 4.600 419.520 1048.040 ; - RECT 421.360 4.600 423.200 1048.040 ; - RECT 425.040 4.600 426.880 1048.040 ; - RECT 428.720 4.600 430.560 1048.040 ; - RECT 432.400 4.600 434.240 1048.040 ; - RECT 436.080 4.600 437.920 1048.040 ; - RECT 439.760 4.600 441.600 1048.040 ; - RECT 443.440 4.600 445.280 1048.040 ; - RECT 447.120 4.600 448.960 1048.040 ; - RECT 450.800 4.600 452.640 1048.040 ; - RECT 454.480 4.600 456.320 1048.040 ; - RECT 458.160 4.600 460.000 1048.040 ; - RECT 461.840 4.600 463.680 1048.040 ; - RECT 465.520 4.600 467.360 1048.040 ; - RECT 469.200 4.600 471.040 1048.040 ; - RECT 472.880 4.600 474.720 1048.040 ; - RECT 476.560 4.600 478.400 1048.040 ; - RECT 480.240 4.600 482.080 1048.040 ; - RECT 483.920 4.600 485.760 1048.040 ; - RECT 487.600 4.600 489.440 1048.040 ; - RECT 491.280 4.600 493.120 1048.040 ; - RECT 494.960 4.600 496.800 1048.040 ; - RECT 498.640 4.600 500.480 1048.040 ; - RECT 502.320 4.600 504.160 1048.040 ; - RECT 506.000 4.600 507.840 1048.040 ; - RECT 509.680 4.600 511.520 1048.040 ; - RECT 513.360 4.600 515.200 1048.040 ; - RECT 517.040 4.600 518.880 1048.040 ; - RECT 520.720 4.600 522.560 1048.040 ; - RECT 524.400 4.600 526.240 1048.040 ; - RECT 528.080 4.600 529.920 1048.040 ; - RECT 531.760 4.600 533.600 1048.040 ; - RECT 535.440 4.600 537.280 1048.040 ; - RECT 539.120 4.600 540.960 1048.040 ; - RECT 542.800 4.600 544.640 1048.040 ; - RECT 546.480 4.600 548.320 1048.040 ; - RECT 550.160 4.600 552.000 1048.040 ; - RECT 553.840 4.600 555.680 1048.040 ; - RECT 557.520 4.600 559.360 1048.040 ; - RECT 561.200 4.600 563.040 1048.040 ; - RECT 564.880 4.600 566.720 1048.040 ; - RECT 568.560 4.600 570.400 1048.040 ; - RECT 572.240 4.600 574.080 1048.040 ; - RECT 575.920 4.600 577.760 1048.040 ; - RECT 579.600 4.600 581.440 1048.040 ; - RECT 583.280 4.600 585.120 1048.040 ; - RECT 586.960 4.600 588.800 1048.040 ; - RECT 590.640 4.600 592.480 1048.040 ; - RECT 594.320 4.600 596.160 1048.040 ; - RECT 598.000 4.600 599.840 1048.040 ; - RECT 601.680 4.600 603.520 1048.040 ; - RECT 605.360 4.600 607.200 1048.040 ; - RECT 609.040 4.600 610.880 1048.040 ; - RECT 612.720 4.600 614.560 1048.040 ; - RECT 616.400 4.600 618.240 1048.040 ; - RECT 620.080 4.600 621.920 1048.040 ; - RECT 623.760 4.600 625.600 1048.040 ; - RECT 627.440 4.600 629.280 1048.040 ; - RECT 631.120 4.600 632.960 1048.040 ; - RECT 634.800 4.600 636.640 1048.040 ; - RECT 638.480 4.600 640.320 1048.040 ; - RECT 642.160 4.600 644.000 1048.040 ; - RECT 645.840 4.600 647.680 1048.040 ; - RECT 649.520 4.600 651.360 1048.040 ; - RECT 653.200 4.600 655.040 1048.040 ; - RECT 656.880 4.600 658.720 1048.040 ; - RECT 660.560 4.600 662.400 1048.040 ; - RECT 664.240 4.600 666.080 1048.040 ; - RECT 667.920 4.600 669.760 1048.040 ; - RECT 671.600 4.600 673.440 1048.040 ; - RECT 675.280 4.600 677.120 1048.040 ; - RECT 678.960 4.600 680.800 1048.040 ; - RECT 682.640 4.600 684.480 1048.040 ; - RECT 686.320 4.600 688.160 1048.040 ; - RECT 690.000 4.600 691.840 1048.040 ; - RECT 693.680 4.600 695.520 1048.040 ; - RECT 697.360 4.600 699.200 1048.040 ; - RECT 701.040 4.600 702.880 1048.040 ; - RECT 704.720 4.600 706.560 1048.040 ; - RECT 708.400 4.600 710.240 1048.040 ; - RECT 712.080 4.600 713.920 1048.040 ; - RECT 715.760 4.600 717.600 1048.040 ; - RECT 719.440 4.600 721.280 1048.040 ; - RECT 723.120 4.600 724.960 1048.040 ; - RECT 726.800 4.600 728.640 1048.040 ; - RECT 730.480 4.600 732.320 1048.040 ; - RECT 734.160 4.600 736.000 1048.040 ; - RECT 737.840 4.600 739.680 1048.040 ; - RECT 741.520 4.600 743.360 1048.040 ; - RECT 745.200 4.600 747.040 1048.040 ; - RECT 748.880 4.600 750.720 1048.040 ; - RECT 752.560 4.600 754.400 1048.040 ; - RECT 756.240 4.600 758.080 1048.040 ; - RECT 759.920 4.600 761.760 1048.040 ; - RECT 763.600 4.600 765.440 1048.040 ; - RECT 767.280 4.600 769.120 1048.040 ; - RECT 770.960 4.600 772.800 1048.040 ; - RECT 774.640 4.600 776.480 1048.040 ; - RECT 778.320 4.600 780.160 1048.040 ; - RECT 782.000 4.600 783.840 1048.040 ; - RECT 785.680 4.600 787.520 1048.040 ; - RECT 789.360 4.600 791.200 1048.040 ; - RECT 793.040 4.600 794.880 1048.040 ; - RECT 796.720 4.600 798.560 1048.040 ; - RECT 800.400 4.600 802.240 1048.040 ; - RECT 804.080 4.600 805.920 1048.040 ; - RECT 807.760 4.600 809.600 1048.040 ; - RECT 811.440 4.600 813.280 1048.040 ; - RECT 815.120 4.600 816.960 1048.040 ; - RECT 818.800 4.600 820.640 1048.040 ; - RECT 822.480 4.600 824.320 1048.040 ; - RECT 826.160 4.600 828.000 1048.040 ; - RECT 829.840 4.600 834.440 1048.040 ; - END -END fakeram130_256x512 - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x64.lef b/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x64.lef deleted file mode 100644 index a90aafc53f..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/fakeram130_256x64.lef +++ /dev/null @@ -1,2612 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram130_256x64 - FOREIGN fakeram130_256x64 0 0 ; - SYMMETRY X Y ; - SIZE 1010.160 BY 160.480 ; - CLASS BLOCK ; - PIN w_mask_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.370 0.460 4.830 ; - END - END w_mask_in[0] - PIN w_mask_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.830 0.460 5.290 ; - END - END w_mask_in[1] - PIN w_mask_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 5.290 0.460 5.750 ; - END - END w_mask_in[2] - PIN w_mask_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 5.750 0.460 6.210 ; - END - END w_mask_in[3] - PIN w_mask_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 6.210 0.460 6.670 ; - END - END w_mask_in[4] - PIN w_mask_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 6.670 0.460 7.130 ; - END - END w_mask_in[5] - PIN w_mask_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.130 0.460 7.590 ; - END - END w_mask_in[6] - PIN w_mask_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.590 0.460 8.050 ; - END - END w_mask_in[7] - PIN w_mask_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.050 0.460 8.510 ; - END - END w_mask_in[8] - PIN w_mask_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.510 0.460 8.970 ; - END - END w_mask_in[9] - PIN w_mask_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.970 0.460 9.430 ; - END - END w_mask_in[10] - PIN w_mask_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.430 0.460 9.890 ; - END - END w_mask_in[11] - PIN w_mask_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.890 0.460 10.350 ; - END - END w_mask_in[12] - PIN w_mask_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 10.350 0.460 10.810 ; - END - END w_mask_in[13] - PIN w_mask_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 10.810 0.460 11.270 ; - END - END w_mask_in[14] - PIN w_mask_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 11.270 0.460 11.730 ; - END - END w_mask_in[15] - PIN w_mask_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 11.730 0.460 12.190 ; - END - END w_mask_in[16] - PIN w_mask_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.190 0.460 12.650 ; - END - END w_mask_in[17] - PIN w_mask_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.650 0.460 13.110 ; - END - END w_mask_in[18] - PIN w_mask_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 13.110 0.460 13.570 ; - END - END w_mask_in[19] - PIN w_mask_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 13.570 0.460 14.030 ; - END - END w_mask_in[20] - PIN w_mask_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.030 0.460 14.490 ; - END - END w_mask_in[21] - PIN w_mask_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.490 0.460 14.950 ; - END - END w_mask_in[22] - PIN w_mask_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.950 0.460 15.410 ; - END - END w_mask_in[23] - PIN w_mask_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.410 0.460 15.870 ; - END - END w_mask_in[24] - PIN w_mask_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.870 0.460 16.330 ; - END - END w_mask_in[25] - PIN w_mask_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 16.330 0.460 16.790 ; - END - END w_mask_in[26] - PIN w_mask_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 16.790 0.460 17.250 ; - END - END w_mask_in[27] - PIN w_mask_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 17.250 0.460 17.710 ; - END - END w_mask_in[28] - PIN w_mask_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 17.710 0.460 18.170 ; - END - END w_mask_in[29] - PIN w_mask_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.170 0.460 18.630 ; - END - END w_mask_in[30] - PIN w_mask_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.630 0.460 19.090 ; - END - END w_mask_in[31] - PIN w_mask_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 19.090 0.460 19.550 ; - END - END w_mask_in[32] - PIN w_mask_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 19.550 0.460 20.010 ; - END - END w_mask_in[33] - PIN w_mask_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.010 0.460 20.470 ; - END - END w_mask_in[34] - PIN w_mask_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.470 0.460 20.930 ; - END - END w_mask_in[35] - PIN w_mask_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.930 0.460 21.390 ; - END - END w_mask_in[36] - PIN w_mask_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 21.390 0.460 21.850 ; - END - END w_mask_in[37] - PIN w_mask_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 21.850 0.460 22.310 ; - END - END w_mask_in[38] - PIN w_mask_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 22.310 0.460 22.770 ; - END - END w_mask_in[39] - PIN w_mask_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 22.770 0.460 23.230 ; - END - END w_mask_in[40] - PIN w_mask_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.230 0.460 23.690 ; - END - END w_mask_in[41] - PIN w_mask_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.690 0.460 24.150 ; - END - END w_mask_in[42] - PIN w_mask_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 24.150 0.460 24.610 ; - END - END w_mask_in[43] - PIN w_mask_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 24.610 0.460 25.070 ; - END - END w_mask_in[44] - PIN w_mask_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.070 0.460 25.530 ; - END - END w_mask_in[45] - PIN w_mask_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.530 0.460 25.990 ; - END - END w_mask_in[46] - PIN w_mask_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.990 0.460 26.450 ; - END - END w_mask_in[47] - PIN w_mask_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.450 0.460 26.910 ; - END - END w_mask_in[48] - PIN w_mask_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.910 0.460 27.370 ; - END - END w_mask_in[49] - PIN w_mask_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 27.370 0.460 27.830 ; - END - END w_mask_in[50] - PIN w_mask_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 27.830 0.460 28.290 ; - END - END w_mask_in[51] - PIN w_mask_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 28.290 0.460 28.750 ; - END - END w_mask_in[52] - PIN w_mask_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 28.750 0.460 29.210 ; - END - END w_mask_in[53] - PIN w_mask_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.210 0.460 29.670 ; - END - END w_mask_in[54] - PIN w_mask_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.670 0.460 30.130 ; - END - END w_mask_in[55] - PIN w_mask_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 30.130 0.460 30.590 ; - END - END w_mask_in[56] - PIN w_mask_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 30.590 0.460 31.050 ; - END - END w_mask_in[57] - PIN w_mask_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.050 0.460 31.510 ; - END - END w_mask_in[58] - PIN w_mask_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.510 0.460 31.970 ; - END - END w_mask_in[59] - PIN w_mask_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.970 0.460 32.430 ; - END - END w_mask_in[60] - PIN w_mask_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 32.430 0.460 32.890 ; - END - END w_mask_in[61] - PIN w_mask_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 32.890 0.460 33.350 ; - END - END w_mask_in[62] - PIN w_mask_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 33.350 0.460 33.810 ; - END - END w_mask_in[63] - PIN rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 47.610 0.460 48.070 ; - END - END rd_out[0] - PIN rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.070 0.460 48.530 ; - END - END rd_out[1] - PIN rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.530 0.460 48.990 ; - END - END rd_out[2] - PIN rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.990 0.460 49.450 ; - END - END rd_out[3] - PIN rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.450 0.460 49.910 ; - END - END rd_out[4] - PIN rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.910 0.460 50.370 ; - END - END rd_out[5] - PIN rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 50.370 0.460 50.830 ; - END - END rd_out[6] - PIN rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 50.830 0.460 51.290 ; - END - END rd_out[7] - PIN rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.290 0.460 51.750 ; - END - END rd_out[8] - PIN rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.750 0.460 52.210 ; - END - END rd_out[9] - PIN rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.210 0.460 52.670 ; - END - END rd_out[10] - PIN rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.670 0.460 53.130 ; - END - END rd_out[11] - PIN rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 53.130 0.460 53.590 ; - END - END rd_out[12] - PIN rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 53.590 0.460 54.050 ; - END - END rd_out[13] - PIN rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.050 0.460 54.510 ; - END - END rd_out[14] - PIN rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.510 0.460 54.970 ; - END - END rd_out[15] - PIN rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.970 0.460 55.430 ; - END - END rd_out[16] - PIN rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 55.430 0.460 55.890 ; - END - END rd_out[17] - PIN rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 55.890 0.460 56.350 ; - END - END rd_out[18] - PIN rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.350 0.460 56.810 ; - END - END rd_out[19] - PIN rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.810 0.460 57.270 ; - END - END rd_out[20] - PIN rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.270 0.460 57.730 ; - END - END rd_out[21] - PIN rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.730 0.460 58.190 ; - END - END rd_out[22] - PIN rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 58.190 0.460 58.650 ; - END - END rd_out[23] - PIN rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 58.650 0.460 59.110 ; - END - END rd_out[24] - PIN rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.110 0.460 59.570 ; - END - END rd_out[25] - PIN rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.570 0.460 60.030 ; - END - END rd_out[26] - PIN rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.030 0.460 60.490 ; - END - END rd_out[27] - PIN rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.490 0.460 60.950 ; - END - END rd_out[28] - PIN rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.950 0.460 61.410 ; - END - END rd_out[29] - PIN rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 61.410 0.460 61.870 ; - END - END rd_out[30] - PIN rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 61.870 0.460 62.330 ; - END - END rd_out[31] - PIN rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.330 0.460 62.790 ; - END - END rd_out[32] - PIN rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.790 0.460 63.250 ; - END - END rd_out[33] - PIN rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 63.250 0.460 63.710 ; - END - END rd_out[34] - PIN rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 63.710 0.460 64.170 ; - END - END rd_out[35] - PIN rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 64.170 0.460 64.630 ; - END - END rd_out[36] - PIN rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 64.630 0.460 65.090 ; - END - END rd_out[37] - PIN rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 65.090 0.460 65.550 ; - END - END rd_out[38] - PIN rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 65.550 0.460 66.010 ; - END - END rd_out[39] - PIN rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.010 0.460 66.470 ; - END - END rd_out[40] - PIN rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.470 0.460 66.930 ; - END - END rd_out[41] - PIN rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 66.930 0.460 67.390 ; - END - END rd_out[42] - PIN rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 67.390 0.460 67.850 ; - END - END rd_out[43] - PIN rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 67.850 0.460 68.310 ; - END - END rd_out[44] - PIN rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 68.310 0.460 68.770 ; - END - END rd_out[45] - PIN rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 68.770 0.460 69.230 ; - END - END rd_out[46] - PIN rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 69.230 0.460 69.690 ; - END - END rd_out[47] - PIN rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 69.690 0.460 70.150 ; - END - END rd_out[48] - PIN rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 70.150 0.460 70.610 ; - END - END rd_out[49] - PIN rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 70.610 0.460 71.070 ; - END - END rd_out[50] - PIN rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.070 0.460 71.530 ; - END - END rd_out[51] - PIN rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.530 0.460 71.990 ; - END - END rd_out[52] - PIN rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.990 0.460 72.450 ; - END - END rd_out[53] - PIN rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 72.450 0.460 72.910 ; - END - END rd_out[54] - PIN rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 72.910 0.460 73.370 ; - END - END rd_out[55] - PIN rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.370 0.460 73.830 ; - END - END rd_out[56] - PIN rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.830 0.460 74.290 ; - END - END rd_out[57] - PIN rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.290 0.460 74.750 ; - END - END rd_out[58] - PIN rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.750 0.460 75.210 ; - END - END rd_out[59] - PIN rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 75.210 0.460 75.670 ; - END - END rd_out[60] - PIN rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 75.670 0.460 76.130 ; - END - END rd_out[61] - PIN rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.130 0.460 76.590 ; - END - END rd_out[62] - PIN rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.590 0.460 77.050 ; - END - END rd_out[63] - PIN wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 90.850 0.460 91.310 ; - END - END wd_in[0] - PIN wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 91.310 0.460 91.770 ; - END - END wd_in[1] - PIN wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 91.770 0.460 92.230 ; - END - END wd_in[2] - PIN wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 92.230 0.460 92.690 ; - END - END wd_in[3] - PIN wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 92.690 0.460 93.150 ; - END - END wd_in[4] - PIN wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 93.150 0.460 93.610 ; - END - END wd_in[5] - PIN wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 93.610 0.460 94.070 ; - END - END wd_in[6] - PIN wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.070 0.460 94.530 ; - END - END wd_in[7] - PIN wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.530 0.460 94.990 ; - END - END wd_in[8] - PIN wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.990 0.460 95.450 ; - END - END wd_in[9] - PIN wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 95.450 0.460 95.910 ; - END - END wd_in[10] - PIN wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 95.910 0.460 96.370 ; - END - END wd_in[11] - PIN wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 96.370 0.460 96.830 ; - END - END wd_in[12] - PIN wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 96.830 0.460 97.290 ; - END - END wd_in[13] - PIN wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.290 0.460 97.750 ; - END - END wd_in[14] - PIN wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.750 0.460 98.210 ; - END - END wd_in[15] - PIN wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 98.210 0.460 98.670 ; - END - END wd_in[16] - PIN wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 98.670 0.460 99.130 ; - END - END wd_in[17] - PIN wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 99.130 0.460 99.590 ; - END - END wd_in[18] - PIN wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 99.590 0.460 100.050 ; - END - END wd_in[19] - PIN wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.050 0.460 100.510 ; - END - END wd_in[20] - PIN wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.510 0.460 100.970 ; - END - END wd_in[21] - PIN wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.970 0.460 101.430 ; - END - END wd_in[22] - PIN wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 101.430 0.460 101.890 ; - END - END wd_in[23] - PIN wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 101.890 0.460 102.350 ; - END - END wd_in[24] - PIN wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.350 0.460 102.810 ; - END - END wd_in[25] - PIN wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.810 0.460 103.270 ; - END - END wd_in[26] - PIN wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.270 0.460 103.730 ; - END - END wd_in[27] - PIN wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.730 0.460 104.190 ; - END - END wd_in[28] - PIN wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 104.190 0.460 104.650 ; - END - END wd_in[29] - PIN wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 104.650 0.460 105.110 ; - END - END wd_in[30] - PIN wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.110 0.460 105.570 ; - END - END wd_in[31] - PIN wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.570 0.460 106.030 ; - END - END wd_in[32] - PIN wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.030 0.460 106.490 ; - END - END wd_in[33] - PIN wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.490 0.460 106.950 ; - END - END wd_in[34] - PIN wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.950 0.460 107.410 ; - END - END wd_in[35] - PIN wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 107.410 0.460 107.870 ; - END - END wd_in[36] - PIN wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 107.870 0.460 108.330 ; - END - END wd_in[37] - PIN wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.330 0.460 108.790 ; - END - END wd_in[38] - PIN wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.790 0.460 109.250 ; - END - END wd_in[39] - PIN wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.250 0.460 109.710 ; - END - END wd_in[40] - PIN wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.710 0.460 110.170 ; - END - END wd_in[41] - PIN wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 110.170 0.460 110.630 ; - END - END wd_in[42] - PIN wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 110.630 0.460 111.090 ; - END - END wd_in[43] - PIN wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.090 0.460 111.550 ; - END - END wd_in[44] - PIN wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.550 0.460 112.010 ; - END - END wd_in[45] - PIN wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.010 0.460 112.470 ; - END - END wd_in[46] - PIN wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.470 0.460 112.930 ; - END - END wd_in[47] - PIN wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.930 0.460 113.390 ; - END - END wd_in[48] - PIN wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.390 0.460 113.850 ; - END - END wd_in[49] - PIN wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.850 0.460 114.310 ; - END - END wd_in[50] - PIN wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.310 0.460 114.770 ; - END - END wd_in[51] - PIN wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.770 0.460 115.230 ; - END - END wd_in[52] - PIN wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 115.230 0.460 115.690 ; - END - END wd_in[53] - PIN wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 115.690 0.460 116.150 ; - END - END wd_in[54] - PIN wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.150 0.460 116.610 ; - END - END wd_in[55] - PIN wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.610 0.460 117.070 ; - END - END wd_in[56] - PIN wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.070 0.460 117.530 ; - END - END wd_in[57] - PIN wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.530 0.460 117.990 ; - END - END wd_in[58] - PIN wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.990 0.460 118.450 ; - END - END wd_in[59] - PIN wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 118.450 0.460 118.910 ; - END - END wd_in[60] - PIN wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 118.910 0.460 119.370 ; - END - END wd_in[61] - PIN wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.370 0.460 119.830 ; - END - END wd_in[62] - PIN wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.830 0.460 120.290 ; - END - END wd_in[63] - PIN addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 134.090 0.460 134.550 ; - END - END addr_in[0] - PIN addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 134.550 0.460 135.010 ; - END - END addr_in[1] - PIN addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.010 0.460 135.470 ; - END - END addr_in[2] - PIN addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.470 0.460 135.930 ; - END - END addr_in[3] - PIN addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 135.930 0.460 136.390 ; - END - END addr_in[4] - PIN addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 136.390 0.460 136.850 ; - END - END addr_in[5] - PIN addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 136.850 0.460 137.310 ; - END - END addr_in[6] - PIN addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 137.310 0.460 137.770 ; - END - END addr_in[7] - PIN we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 151.570 0.460 152.030 ; - END - END we_in - PIN ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.030 0.460 152.490 ; - END - END ce_in - PIN clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.490 0.460 152.950 ; - END - END clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 3.680 4.600 5.520 155.880 ; - RECT 11.040 4.600 12.880 155.880 ; - RECT 18.400 4.600 20.240 155.880 ; - RECT 25.760 4.600 27.600 155.880 ; - RECT 33.120 4.600 34.960 155.880 ; - RECT 40.480 4.600 42.320 155.880 ; - RECT 47.840 4.600 49.680 155.880 ; - RECT 55.200 4.600 57.040 155.880 ; - RECT 62.560 4.600 64.400 155.880 ; - RECT 69.920 4.600 71.760 155.880 ; - RECT 77.280 4.600 79.120 155.880 ; - RECT 84.640 4.600 86.480 155.880 ; - RECT 92.000 4.600 93.840 155.880 ; - RECT 99.360 4.600 101.200 155.880 ; - RECT 106.720 4.600 108.560 155.880 ; - RECT 114.080 4.600 115.920 155.880 ; - RECT 121.440 4.600 123.280 155.880 ; - RECT 128.800 4.600 130.640 155.880 ; - RECT 136.160 4.600 138.000 155.880 ; - RECT 143.520 4.600 145.360 155.880 ; - RECT 150.880 4.600 152.720 155.880 ; - RECT 158.240 4.600 160.080 155.880 ; - RECT 165.600 4.600 167.440 155.880 ; - RECT 172.960 4.600 174.800 155.880 ; - RECT 180.320 4.600 182.160 155.880 ; - RECT 187.680 4.600 189.520 155.880 ; - RECT 195.040 4.600 196.880 155.880 ; - RECT 202.400 4.600 204.240 155.880 ; - RECT 209.760 4.600 211.600 155.880 ; - RECT 217.120 4.600 218.960 155.880 ; - RECT 224.480 4.600 226.320 155.880 ; - RECT 231.840 4.600 233.680 155.880 ; - RECT 239.200 4.600 241.040 155.880 ; - RECT 246.560 4.600 248.400 155.880 ; - RECT 253.920 4.600 255.760 155.880 ; - RECT 261.280 4.600 263.120 155.880 ; - RECT 268.640 4.600 270.480 155.880 ; - RECT 276.000 4.600 277.840 155.880 ; - RECT 283.360 4.600 285.200 155.880 ; - RECT 290.720 4.600 292.560 155.880 ; - RECT 298.080 4.600 299.920 155.880 ; - RECT 305.440 4.600 307.280 155.880 ; - RECT 312.800 4.600 314.640 155.880 ; - RECT 320.160 4.600 322.000 155.880 ; - RECT 327.520 4.600 329.360 155.880 ; - RECT 334.880 4.600 336.720 155.880 ; - RECT 342.240 4.600 344.080 155.880 ; - RECT 349.600 4.600 351.440 155.880 ; - RECT 356.960 4.600 358.800 155.880 ; - RECT 364.320 4.600 366.160 155.880 ; - RECT 371.680 4.600 373.520 155.880 ; - RECT 379.040 4.600 380.880 155.880 ; - RECT 386.400 4.600 388.240 155.880 ; - RECT 393.760 4.600 395.600 155.880 ; - RECT 401.120 4.600 402.960 155.880 ; - RECT 408.480 4.600 410.320 155.880 ; - RECT 415.840 4.600 417.680 155.880 ; - RECT 423.200 4.600 425.040 155.880 ; - RECT 430.560 4.600 432.400 155.880 ; - RECT 437.920 4.600 439.760 155.880 ; - RECT 445.280 4.600 447.120 155.880 ; - RECT 452.640 4.600 454.480 155.880 ; - RECT 460.000 4.600 461.840 155.880 ; - RECT 467.360 4.600 469.200 155.880 ; - RECT 474.720 4.600 476.560 155.880 ; - RECT 482.080 4.600 483.920 155.880 ; - RECT 489.440 4.600 491.280 155.880 ; - RECT 496.800 4.600 498.640 155.880 ; - RECT 504.160 4.600 506.000 155.880 ; - RECT 511.520 4.600 513.360 155.880 ; - RECT 518.880 4.600 520.720 155.880 ; - RECT 526.240 4.600 528.080 155.880 ; - RECT 533.600 4.600 535.440 155.880 ; - RECT 540.960 4.600 542.800 155.880 ; - RECT 548.320 4.600 550.160 155.880 ; - RECT 555.680 4.600 557.520 155.880 ; - RECT 563.040 4.600 564.880 155.880 ; - RECT 570.400 4.600 572.240 155.880 ; - RECT 577.760 4.600 579.600 155.880 ; - RECT 585.120 4.600 586.960 155.880 ; - RECT 592.480 4.600 594.320 155.880 ; - RECT 599.840 4.600 601.680 155.880 ; - RECT 607.200 4.600 609.040 155.880 ; - RECT 614.560 4.600 616.400 155.880 ; - RECT 621.920 4.600 623.760 155.880 ; - RECT 629.280 4.600 631.120 155.880 ; - RECT 636.640 4.600 638.480 155.880 ; - RECT 644.000 4.600 645.840 155.880 ; - RECT 651.360 4.600 653.200 155.880 ; - RECT 658.720 4.600 660.560 155.880 ; - RECT 666.080 4.600 667.920 155.880 ; - RECT 673.440 4.600 675.280 155.880 ; - RECT 680.800 4.600 682.640 155.880 ; - RECT 688.160 4.600 690.000 155.880 ; - RECT 695.520 4.600 697.360 155.880 ; - RECT 702.880 4.600 704.720 155.880 ; - RECT 710.240 4.600 712.080 155.880 ; - RECT 717.600 4.600 719.440 155.880 ; - RECT 724.960 4.600 726.800 155.880 ; - RECT 732.320 4.600 734.160 155.880 ; - RECT 739.680 4.600 741.520 155.880 ; - RECT 747.040 4.600 748.880 155.880 ; - RECT 754.400 4.600 756.240 155.880 ; - RECT 761.760 4.600 763.600 155.880 ; - RECT 769.120 4.600 770.960 155.880 ; - RECT 776.480 4.600 778.320 155.880 ; - RECT 783.840 4.600 785.680 155.880 ; - RECT 791.200 4.600 793.040 155.880 ; - RECT 798.560 4.600 800.400 155.880 ; - RECT 805.920 4.600 807.760 155.880 ; - RECT 813.280 4.600 815.120 155.880 ; - RECT 820.640 4.600 822.480 155.880 ; - RECT 828.000 4.600 829.840 155.880 ; - RECT 835.360 4.600 837.200 155.880 ; - RECT 842.720 4.600 844.560 155.880 ; - RECT 850.080 4.600 851.920 155.880 ; - RECT 857.440 4.600 859.280 155.880 ; - RECT 864.800 4.600 866.640 155.880 ; - RECT 872.160 4.600 874.000 155.880 ; - RECT 879.520 4.600 881.360 155.880 ; - RECT 886.880 4.600 888.720 155.880 ; - RECT 894.240 4.600 896.080 155.880 ; - RECT 901.600 4.600 903.440 155.880 ; - RECT 908.960 4.600 910.800 155.880 ; - RECT 916.320 4.600 918.160 155.880 ; - RECT 923.680 4.600 925.520 155.880 ; - RECT 931.040 4.600 932.880 155.880 ; - RECT 938.400 4.600 940.240 155.880 ; - RECT 945.760 4.600 947.600 155.880 ; - RECT 953.120 4.600 954.960 155.880 ; - RECT 960.480 4.600 962.320 155.880 ; - RECT 967.840 4.600 969.680 155.880 ; - RECT 975.200 4.600 977.040 155.880 ; - RECT 982.560 4.600 984.400 155.880 ; - RECT 989.920 4.600 991.760 155.880 ; - RECT 997.280 4.600 999.120 155.880 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 7.360 4.600 9.200 155.880 ; - RECT 14.720 4.600 16.560 155.880 ; - RECT 22.080 4.600 23.920 155.880 ; - RECT 29.440 4.600 31.280 155.880 ; - RECT 36.800 4.600 38.640 155.880 ; - RECT 44.160 4.600 46.000 155.880 ; - RECT 51.520 4.600 53.360 155.880 ; - RECT 58.880 4.600 60.720 155.880 ; - RECT 66.240 4.600 68.080 155.880 ; - RECT 73.600 4.600 75.440 155.880 ; - RECT 80.960 4.600 82.800 155.880 ; - RECT 88.320 4.600 90.160 155.880 ; - RECT 95.680 4.600 97.520 155.880 ; - RECT 103.040 4.600 104.880 155.880 ; - RECT 110.400 4.600 112.240 155.880 ; - RECT 117.760 4.600 119.600 155.880 ; - RECT 125.120 4.600 126.960 155.880 ; - RECT 132.480 4.600 134.320 155.880 ; - RECT 139.840 4.600 141.680 155.880 ; - RECT 147.200 4.600 149.040 155.880 ; - RECT 154.560 4.600 156.400 155.880 ; - RECT 161.920 4.600 163.760 155.880 ; - RECT 169.280 4.600 171.120 155.880 ; - RECT 176.640 4.600 178.480 155.880 ; - RECT 184.000 4.600 185.840 155.880 ; - RECT 191.360 4.600 193.200 155.880 ; - RECT 198.720 4.600 200.560 155.880 ; - RECT 206.080 4.600 207.920 155.880 ; - RECT 213.440 4.600 215.280 155.880 ; - RECT 220.800 4.600 222.640 155.880 ; - RECT 228.160 4.600 230.000 155.880 ; - RECT 235.520 4.600 237.360 155.880 ; - RECT 242.880 4.600 244.720 155.880 ; - RECT 250.240 4.600 252.080 155.880 ; - RECT 257.600 4.600 259.440 155.880 ; - RECT 264.960 4.600 266.800 155.880 ; - RECT 272.320 4.600 274.160 155.880 ; - RECT 279.680 4.600 281.520 155.880 ; - RECT 287.040 4.600 288.880 155.880 ; - RECT 294.400 4.600 296.240 155.880 ; - RECT 301.760 4.600 303.600 155.880 ; - RECT 309.120 4.600 310.960 155.880 ; - RECT 316.480 4.600 318.320 155.880 ; - RECT 323.840 4.600 325.680 155.880 ; - RECT 331.200 4.600 333.040 155.880 ; - RECT 338.560 4.600 340.400 155.880 ; - RECT 345.920 4.600 347.760 155.880 ; - RECT 353.280 4.600 355.120 155.880 ; - RECT 360.640 4.600 362.480 155.880 ; - RECT 368.000 4.600 369.840 155.880 ; - RECT 375.360 4.600 377.200 155.880 ; - RECT 382.720 4.600 384.560 155.880 ; - RECT 390.080 4.600 391.920 155.880 ; - RECT 397.440 4.600 399.280 155.880 ; - RECT 404.800 4.600 406.640 155.880 ; - RECT 412.160 4.600 414.000 155.880 ; - RECT 419.520 4.600 421.360 155.880 ; - RECT 426.880 4.600 428.720 155.880 ; - RECT 434.240 4.600 436.080 155.880 ; - RECT 441.600 4.600 443.440 155.880 ; - RECT 448.960 4.600 450.800 155.880 ; - RECT 456.320 4.600 458.160 155.880 ; - RECT 463.680 4.600 465.520 155.880 ; - RECT 471.040 4.600 472.880 155.880 ; - RECT 478.400 4.600 480.240 155.880 ; - RECT 485.760 4.600 487.600 155.880 ; - RECT 493.120 4.600 494.960 155.880 ; - RECT 500.480 4.600 502.320 155.880 ; - RECT 507.840 4.600 509.680 155.880 ; - RECT 515.200 4.600 517.040 155.880 ; - RECT 522.560 4.600 524.400 155.880 ; - RECT 529.920 4.600 531.760 155.880 ; - RECT 537.280 4.600 539.120 155.880 ; - RECT 544.640 4.600 546.480 155.880 ; - RECT 552.000 4.600 553.840 155.880 ; - RECT 559.360 4.600 561.200 155.880 ; - RECT 566.720 4.600 568.560 155.880 ; - RECT 574.080 4.600 575.920 155.880 ; - RECT 581.440 4.600 583.280 155.880 ; - RECT 588.800 4.600 590.640 155.880 ; - RECT 596.160 4.600 598.000 155.880 ; - RECT 603.520 4.600 605.360 155.880 ; - RECT 610.880 4.600 612.720 155.880 ; - RECT 618.240 4.600 620.080 155.880 ; - RECT 625.600 4.600 627.440 155.880 ; - RECT 632.960 4.600 634.800 155.880 ; - RECT 640.320 4.600 642.160 155.880 ; - RECT 647.680 4.600 649.520 155.880 ; - RECT 655.040 4.600 656.880 155.880 ; - RECT 662.400 4.600 664.240 155.880 ; - RECT 669.760 4.600 671.600 155.880 ; - RECT 677.120 4.600 678.960 155.880 ; - RECT 684.480 4.600 686.320 155.880 ; - RECT 691.840 4.600 693.680 155.880 ; - RECT 699.200 4.600 701.040 155.880 ; - RECT 706.560 4.600 708.400 155.880 ; - RECT 713.920 4.600 715.760 155.880 ; - RECT 721.280 4.600 723.120 155.880 ; - RECT 728.640 4.600 730.480 155.880 ; - RECT 736.000 4.600 737.840 155.880 ; - RECT 743.360 4.600 745.200 155.880 ; - RECT 750.720 4.600 752.560 155.880 ; - RECT 758.080 4.600 759.920 155.880 ; - RECT 765.440 4.600 767.280 155.880 ; - RECT 772.800 4.600 774.640 155.880 ; - RECT 780.160 4.600 782.000 155.880 ; - RECT 787.520 4.600 789.360 155.880 ; - RECT 794.880 4.600 796.720 155.880 ; - RECT 802.240 4.600 804.080 155.880 ; - RECT 809.600 4.600 811.440 155.880 ; - RECT 816.960 4.600 818.800 155.880 ; - RECT 824.320 4.600 826.160 155.880 ; - RECT 831.680 4.600 833.520 155.880 ; - RECT 839.040 4.600 840.880 155.880 ; - RECT 846.400 4.600 848.240 155.880 ; - RECT 853.760 4.600 855.600 155.880 ; - RECT 861.120 4.600 862.960 155.880 ; - RECT 868.480 4.600 870.320 155.880 ; - RECT 875.840 4.600 877.680 155.880 ; - RECT 883.200 4.600 885.040 155.880 ; - RECT 890.560 4.600 892.400 155.880 ; - RECT 897.920 4.600 899.760 155.880 ; - RECT 905.280 4.600 907.120 155.880 ; - RECT 912.640 4.600 914.480 155.880 ; - RECT 920.000 4.600 921.840 155.880 ; - RECT 927.360 4.600 929.200 155.880 ; - RECT 934.720 4.600 936.560 155.880 ; - RECT 942.080 4.600 943.920 155.880 ; - RECT 949.440 4.600 951.280 155.880 ; - RECT 956.800 4.600 958.640 155.880 ; - RECT 964.160 4.600 966.000 155.880 ; - RECT 971.520 4.600 973.360 155.880 ; - RECT 978.880 4.600 980.720 155.880 ; - RECT 986.240 4.600 988.080 155.880 ; - RECT 993.600 4.600 995.440 155.880 ; - RECT 1000.960 4.600 1002.800 155.880 ; - END - END VDD - OBS - LAYER met1 ; - RECT 0 0 1010.160 160.480 ; - LAYER met2 ; - RECT 0 0 1010.160 160.480 ; - LAYER met3 ; - RECT 0.460 0 1010.160 160.480 ; - RECT 0 0.000 0.460 4.370 ; - RECT 0 4.830 0.460 4.830 ; - RECT 0 5.290 0.460 5.290 ; - RECT 0 5.750 0.460 5.750 ; - RECT 0 6.210 0.460 6.210 ; - RECT 0 6.670 0.460 6.670 ; - RECT 0 7.130 0.460 7.130 ; - RECT 0 7.590 0.460 7.590 ; - RECT 0 8.050 0.460 8.050 ; - RECT 0 8.510 0.460 8.510 ; - RECT 0 8.970 0.460 8.970 ; - RECT 0 9.430 0.460 9.430 ; - RECT 0 9.890 0.460 9.890 ; - RECT 0 10.350 0.460 10.350 ; - RECT 0 10.810 0.460 10.810 ; - RECT 0 11.270 0.460 11.270 ; - RECT 0 11.730 0.460 11.730 ; - RECT 0 12.190 0.460 12.190 ; - RECT 0 12.650 0.460 12.650 ; - RECT 0 13.110 0.460 13.110 ; - RECT 0 13.570 0.460 13.570 ; - RECT 0 14.030 0.460 14.030 ; - RECT 0 14.490 0.460 14.490 ; - RECT 0 14.950 0.460 14.950 ; - RECT 0 15.410 0.460 15.410 ; - RECT 0 15.870 0.460 15.870 ; - RECT 0 16.330 0.460 16.330 ; - RECT 0 16.790 0.460 16.790 ; - RECT 0 17.250 0.460 17.250 ; - RECT 0 17.710 0.460 17.710 ; - RECT 0 18.170 0.460 18.170 ; - RECT 0 18.630 0.460 18.630 ; - RECT 0 19.090 0.460 19.090 ; - RECT 0 19.550 0.460 19.550 ; - RECT 0 20.010 0.460 20.010 ; - RECT 0 20.470 0.460 20.470 ; - RECT 0 20.930 0.460 20.930 ; - RECT 0 21.390 0.460 21.390 ; - RECT 0 21.850 0.460 21.850 ; - RECT 0 22.310 0.460 22.310 ; - RECT 0 22.770 0.460 22.770 ; - RECT 0 23.230 0.460 23.230 ; - RECT 0 23.690 0.460 23.690 ; - RECT 0 24.150 0.460 24.150 ; - RECT 0 24.610 0.460 24.610 ; - RECT 0 25.070 0.460 25.070 ; - RECT 0 25.530 0.460 25.530 ; - RECT 0 25.990 0.460 25.990 ; - RECT 0 26.450 0.460 26.450 ; - RECT 0 26.910 0.460 26.910 ; - RECT 0 27.370 0.460 27.370 ; - RECT 0 27.830 0.460 27.830 ; - RECT 0 28.290 0.460 28.290 ; - RECT 0 28.750 0.460 28.750 ; - RECT 0 29.210 0.460 29.210 ; - RECT 0 29.670 0.460 29.670 ; - RECT 0 30.130 0.460 30.130 ; - RECT 0 30.590 0.460 30.590 ; - RECT 0 31.050 0.460 31.050 ; - RECT 0 31.510 0.460 31.510 ; - RECT 0 31.970 0.460 31.970 ; - RECT 0 32.430 0.460 32.430 ; - RECT 0 32.890 0.460 32.890 ; - RECT 0 33.350 0.460 33.350 ; - RECT 0 33.810 0.460 47.610 ; - RECT 0 48.070 0.460 48.070 ; - RECT 0 48.530 0.460 48.530 ; - RECT 0 48.990 0.460 48.990 ; - RECT 0 49.450 0.460 49.450 ; - RECT 0 49.910 0.460 49.910 ; - RECT 0 50.370 0.460 50.370 ; - RECT 0 50.830 0.460 50.830 ; - RECT 0 51.290 0.460 51.290 ; - RECT 0 51.750 0.460 51.750 ; - RECT 0 52.210 0.460 52.210 ; - RECT 0 52.670 0.460 52.670 ; - RECT 0 53.130 0.460 53.130 ; - RECT 0 53.590 0.460 53.590 ; - RECT 0 54.050 0.460 54.050 ; - RECT 0 54.510 0.460 54.510 ; - RECT 0 54.970 0.460 54.970 ; - RECT 0 55.430 0.460 55.430 ; - RECT 0 55.890 0.460 55.890 ; - RECT 0 56.350 0.460 56.350 ; - RECT 0 56.810 0.460 56.810 ; - RECT 0 57.270 0.460 57.270 ; - RECT 0 57.730 0.460 57.730 ; - RECT 0 58.190 0.460 58.190 ; - RECT 0 58.650 0.460 58.650 ; - RECT 0 59.110 0.460 59.110 ; - RECT 0 59.570 0.460 59.570 ; - RECT 0 60.030 0.460 60.030 ; - RECT 0 60.490 0.460 60.490 ; - RECT 0 60.950 0.460 60.950 ; - RECT 0 61.410 0.460 61.410 ; - RECT 0 61.870 0.460 61.870 ; - RECT 0 62.330 0.460 62.330 ; - RECT 0 62.790 0.460 62.790 ; - RECT 0 63.250 0.460 63.250 ; - RECT 0 63.710 0.460 63.710 ; - RECT 0 64.170 0.460 64.170 ; - RECT 0 64.630 0.460 64.630 ; - RECT 0 65.090 0.460 65.090 ; - RECT 0 65.550 0.460 65.550 ; - RECT 0 66.010 0.460 66.010 ; - RECT 0 66.470 0.460 66.470 ; - RECT 0 66.930 0.460 66.930 ; - RECT 0 67.390 0.460 67.390 ; - RECT 0 67.850 0.460 67.850 ; - RECT 0 68.310 0.460 68.310 ; - RECT 0 68.770 0.460 68.770 ; - RECT 0 69.230 0.460 69.230 ; - RECT 0 69.690 0.460 69.690 ; - RECT 0 70.150 0.460 70.150 ; - RECT 0 70.610 0.460 70.610 ; - RECT 0 71.070 0.460 71.070 ; - RECT 0 71.530 0.460 71.530 ; - RECT 0 71.990 0.460 71.990 ; - RECT 0 72.450 0.460 72.450 ; - RECT 0 72.910 0.460 72.910 ; - RECT 0 73.370 0.460 73.370 ; - RECT 0 73.830 0.460 73.830 ; - RECT 0 74.290 0.460 74.290 ; - RECT 0 74.750 0.460 74.750 ; - RECT 0 75.210 0.460 75.210 ; - RECT 0 75.670 0.460 75.670 ; - RECT 0 76.130 0.460 76.130 ; - RECT 0 76.590 0.460 76.590 ; - RECT 0 77.050 0.460 90.850 ; - RECT 0 91.310 0.460 91.310 ; - RECT 0 91.770 0.460 91.770 ; - RECT 0 92.230 0.460 92.230 ; - RECT 0 92.690 0.460 92.690 ; - RECT 0 93.150 0.460 93.150 ; - RECT 0 93.610 0.460 93.610 ; - RECT 0 94.070 0.460 94.070 ; - RECT 0 94.530 0.460 94.530 ; - RECT 0 94.990 0.460 94.990 ; - RECT 0 95.450 0.460 95.450 ; - RECT 0 95.910 0.460 95.910 ; - RECT 0 96.370 0.460 96.370 ; - RECT 0 96.830 0.460 96.830 ; - RECT 0 97.290 0.460 97.290 ; - RECT 0 97.750 0.460 97.750 ; - RECT 0 98.210 0.460 98.210 ; - RECT 0 98.670 0.460 98.670 ; - RECT 0 99.130 0.460 99.130 ; - RECT 0 99.590 0.460 99.590 ; - RECT 0 100.050 0.460 100.050 ; - RECT 0 100.510 0.460 100.510 ; - RECT 0 100.970 0.460 100.970 ; - RECT 0 101.430 0.460 101.430 ; - RECT 0 101.890 0.460 101.890 ; - RECT 0 102.350 0.460 102.350 ; - RECT 0 102.810 0.460 102.810 ; - RECT 0 103.270 0.460 103.270 ; - RECT 0 103.730 0.460 103.730 ; - RECT 0 104.190 0.460 104.190 ; - RECT 0 104.650 0.460 104.650 ; - RECT 0 105.110 0.460 105.110 ; - RECT 0 105.570 0.460 105.570 ; - RECT 0 106.030 0.460 106.030 ; - RECT 0 106.490 0.460 106.490 ; - RECT 0 106.950 0.460 106.950 ; - RECT 0 107.410 0.460 107.410 ; - RECT 0 107.870 0.460 107.870 ; - RECT 0 108.330 0.460 108.330 ; - RECT 0 108.790 0.460 108.790 ; - RECT 0 109.250 0.460 109.250 ; - RECT 0 109.710 0.460 109.710 ; - RECT 0 110.170 0.460 110.170 ; - RECT 0 110.630 0.460 110.630 ; - RECT 0 111.090 0.460 111.090 ; - RECT 0 111.550 0.460 111.550 ; - RECT 0 112.010 0.460 112.010 ; - RECT 0 112.470 0.460 112.470 ; - RECT 0 112.930 0.460 112.930 ; - RECT 0 113.390 0.460 113.390 ; - RECT 0 113.850 0.460 113.850 ; - RECT 0 114.310 0.460 114.310 ; - RECT 0 114.770 0.460 114.770 ; - RECT 0 115.230 0.460 115.230 ; - RECT 0 115.690 0.460 115.690 ; - RECT 0 116.150 0.460 116.150 ; - RECT 0 116.610 0.460 116.610 ; - RECT 0 117.070 0.460 117.070 ; - RECT 0 117.530 0.460 117.530 ; - RECT 0 117.990 0.460 117.990 ; - RECT 0 118.450 0.460 118.450 ; - RECT 0 118.910 0.460 118.910 ; - RECT 0 119.370 0.460 119.370 ; - RECT 0 119.830 0.460 119.830 ; - RECT 0 120.290 0.460 134.090 ; - RECT 0 134.550 0.460 134.550 ; - RECT 0 135.010 0.460 135.010 ; - RECT 0 135.470 0.460 135.470 ; - RECT 0 135.930 0.460 135.930 ; - RECT 0 136.390 0.460 136.390 ; - RECT 0 136.850 0.460 136.850 ; - RECT 0 137.310 0.460 137.310 ; - RECT 0 137.770 0.460 151.570 ; - RECT 0 152.030 0.460 152.030 ; - RECT 0 152.490 0.460 152.490 ; - RECT 0 152.950 0.460 160.480 ; - LAYER met4 ; - RECT 0 0 1010.160 4.600 ; - RECT 0 155.880 1010.160 160.480 ; - RECT 0.000 4.600 3.680 155.880 ; - RECT 5.520 4.600 7.360 155.880 ; - RECT 9.200 4.600 11.040 155.880 ; - RECT 12.880 4.600 14.720 155.880 ; - RECT 16.560 4.600 18.400 155.880 ; - RECT 20.240 4.600 22.080 155.880 ; - RECT 23.920 4.600 25.760 155.880 ; - RECT 27.600 4.600 29.440 155.880 ; - RECT 31.280 4.600 33.120 155.880 ; - RECT 34.960 4.600 36.800 155.880 ; - RECT 38.640 4.600 40.480 155.880 ; - RECT 42.320 4.600 44.160 155.880 ; - RECT 46.000 4.600 47.840 155.880 ; - RECT 49.680 4.600 51.520 155.880 ; - RECT 53.360 4.600 55.200 155.880 ; - RECT 57.040 4.600 58.880 155.880 ; - RECT 60.720 4.600 62.560 155.880 ; - RECT 64.400 4.600 66.240 155.880 ; - RECT 68.080 4.600 69.920 155.880 ; - RECT 71.760 4.600 73.600 155.880 ; - RECT 75.440 4.600 77.280 155.880 ; - RECT 79.120 4.600 80.960 155.880 ; - RECT 82.800 4.600 84.640 155.880 ; - RECT 86.480 4.600 88.320 155.880 ; - RECT 90.160 4.600 92.000 155.880 ; - RECT 93.840 4.600 95.680 155.880 ; - RECT 97.520 4.600 99.360 155.880 ; - RECT 101.200 4.600 103.040 155.880 ; - RECT 104.880 4.600 106.720 155.880 ; - RECT 108.560 4.600 110.400 155.880 ; - RECT 112.240 4.600 114.080 155.880 ; - RECT 115.920 4.600 117.760 155.880 ; - RECT 119.600 4.600 121.440 155.880 ; - RECT 123.280 4.600 125.120 155.880 ; - RECT 126.960 4.600 128.800 155.880 ; - RECT 130.640 4.600 132.480 155.880 ; - RECT 134.320 4.600 136.160 155.880 ; - RECT 138.000 4.600 139.840 155.880 ; - RECT 141.680 4.600 143.520 155.880 ; - RECT 145.360 4.600 147.200 155.880 ; - RECT 149.040 4.600 150.880 155.880 ; - RECT 152.720 4.600 154.560 155.880 ; - RECT 156.400 4.600 158.240 155.880 ; - RECT 160.080 4.600 161.920 155.880 ; - RECT 163.760 4.600 165.600 155.880 ; - RECT 167.440 4.600 169.280 155.880 ; - RECT 171.120 4.600 172.960 155.880 ; - RECT 174.800 4.600 176.640 155.880 ; - RECT 178.480 4.600 180.320 155.880 ; - RECT 182.160 4.600 184.000 155.880 ; - RECT 185.840 4.600 187.680 155.880 ; - RECT 189.520 4.600 191.360 155.880 ; - RECT 193.200 4.600 195.040 155.880 ; - RECT 196.880 4.600 198.720 155.880 ; - RECT 200.560 4.600 202.400 155.880 ; - RECT 204.240 4.600 206.080 155.880 ; - RECT 207.920 4.600 209.760 155.880 ; - RECT 211.600 4.600 213.440 155.880 ; - RECT 215.280 4.600 217.120 155.880 ; - RECT 218.960 4.600 220.800 155.880 ; - RECT 222.640 4.600 224.480 155.880 ; - RECT 226.320 4.600 228.160 155.880 ; - RECT 230.000 4.600 231.840 155.880 ; - RECT 233.680 4.600 235.520 155.880 ; - RECT 237.360 4.600 239.200 155.880 ; - RECT 241.040 4.600 242.880 155.880 ; - RECT 244.720 4.600 246.560 155.880 ; - RECT 248.400 4.600 250.240 155.880 ; - RECT 252.080 4.600 253.920 155.880 ; - RECT 255.760 4.600 257.600 155.880 ; - RECT 259.440 4.600 261.280 155.880 ; - RECT 263.120 4.600 264.960 155.880 ; - RECT 266.800 4.600 268.640 155.880 ; - RECT 270.480 4.600 272.320 155.880 ; - RECT 274.160 4.600 276.000 155.880 ; - RECT 277.840 4.600 279.680 155.880 ; - RECT 281.520 4.600 283.360 155.880 ; - RECT 285.200 4.600 287.040 155.880 ; - RECT 288.880 4.600 290.720 155.880 ; - RECT 292.560 4.600 294.400 155.880 ; - RECT 296.240 4.600 298.080 155.880 ; - RECT 299.920 4.600 301.760 155.880 ; - RECT 303.600 4.600 305.440 155.880 ; - RECT 307.280 4.600 309.120 155.880 ; - RECT 310.960 4.600 312.800 155.880 ; - RECT 314.640 4.600 316.480 155.880 ; - RECT 318.320 4.600 320.160 155.880 ; - RECT 322.000 4.600 323.840 155.880 ; - RECT 325.680 4.600 327.520 155.880 ; - RECT 329.360 4.600 331.200 155.880 ; - RECT 333.040 4.600 334.880 155.880 ; - RECT 336.720 4.600 338.560 155.880 ; - RECT 340.400 4.600 342.240 155.880 ; - RECT 344.080 4.600 345.920 155.880 ; - RECT 347.760 4.600 349.600 155.880 ; - RECT 351.440 4.600 353.280 155.880 ; - RECT 355.120 4.600 356.960 155.880 ; - RECT 358.800 4.600 360.640 155.880 ; - RECT 362.480 4.600 364.320 155.880 ; - RECT 366.160 4.600 368.000 155.880 ; - RECT 369.840 4.600 371.680 155.880 ; - RECT 373.520 4.600 375.360 155.880 ; - RECT 377.200 4.600 379.040 155.880 ; - RECT 380.880 4.600 382.720 155.880 ; - RECT 384.560 4.600 386.400 155.880 ; - RECT 388.240 4.600 390.080 155.880 ; - RECT 391.920 4.600 393.760 155.880 ; - RECT 395.600 4.600 397.440 155.880 ; - RECT 399.280 4.600 401.120 155.880 ; - RECT 402.960 4.600 404.800 155.880 ; - RECT 406.640 4.600 408.480 155.880 ; - RECT 410.320 4.600 412.160 155.880 ; - RECT 414.000 4.600 415.840 155.880 ; - RECT 417.680 4.600 419.520 155.880 ; - RECT 421.360 4.600 423.200 155.880 ; - RECT 425.040 4.600 426.880 155.880 ; - RECT 428.720 4.600 430.560 155.880 ; - RECT 432.400 4.600 434.240 155.880 ; - RECT 436.080 4.600 437.920 155.880 ; - RECT 439.760 4.600 441.600 155.880 ; - RECT 443.440 4.600 445.280 155.880 ; - RECT 447.120 4.600 448.960 155.880 ; - RECT 450.800 4.600 452.640 155.880 ; - RECT 454.480 4.600 456.320 155.880 ; - RECT 458.160 4.600 460.000 155.880 ; - RECT 461.840 4.600 463.680 155.880 ; - RECT 465.520 4.600 467.360 155.880 ; - RECT 469.200 4.600 471.040 155.880 ; - RECT 472.880 4.600 474.720 155.880 ; - RECT 476.560 4.600 478.400 155.880 ; - RECT 480.240 4.600 482.080 155.880 ; - RECT 483.920 4.600 485.760 155.880 ; - RECT 487.600 4.600 489.440 155.880 ; - RECT 491.280 4.600 493.120 155.880 ; - RECT 494.960 4.600 496.800 155.880 ; - RECT 498.640 4.600 500.480 155.880 ; - RECT 502.320 4.600 504.160 155.880 ; - RECT 506.000 4.600 507.840 155.880 ; - RECT 509.680 4.600 511.520 155.880 ; - RECT 513.360 4.600 515.200 155.880 ; - RECT 517.040 4.600 518.880 155.880 ; - RECT 520.720 4.600 522.560 155.880 ; - RECT 524.400 4.600 526.240 155.880 ; - RECT 528.080 4.600 529.920 155.880 ; - RECT 531.760 4.600 533.600 155.880 ; - RECT 535.440 4.600 537.280 155.880 ; - RECT 539.120 4.600 540.960 155.880 ; - RECT 542.800 4.600 544.640 155.880 ; - RECT 546.480 4.600 548.320 155.880 ; - RECT 550.160 4.600 552.000 155.880 ; - RECT 553.840 4.600 555.680 155.880 ; - RECT 557.520 4.600 559.360 155.880 ; - RECT 561.200 4.600 563.040 155.880 ; - RECT 564.880 4.600 566.720 155.880 ; - RECT 568.560 4.600 570.400 155.880 ; - RECT 572.240 4.600 574.080 155.880 ; - RECT 575.920 4.600 577.760 155.880 ; - RECT 579.600 4.600 581.440 155.880 ; - RECT 583.280 4.600 585.120 155.880 ; - RECT 586.960 4.600 588.800 155.880 ; - RECT 590.640 4.600 592.480 155.880 ; - RECT 594.320 4.600 596.160 155.880 ; - RECT 598.000 4.600 599.840 155.880 ; - RECT 601.680 4.600 603.520 155.880 ; - RECT 605.360 4.600 607.200 155.880 ; - RECT 609.040 4.600 610.880 155.880 ; - RECT 612.720 4.600 614.560 155.880 ; - RECT 616.400 4.600 618.240 155.880 ; - RECT 620.080 4.600 621.920 155.880 ; - RECT 623.760 4.600 625.600 155.880 ; - RECT 627.440 4.600 629.280 155.880 ; - RECT 631.120 4.600 632.960 155.880 ; - RECT 634.800 4.600 636.640 155.880 ; - RECT 638.480 4.600 640.320 155.880 ; - RECT 642.160 4.600 644.000 155.880 ; - RECT 645.840 4.600 647.680 155.880 ; - RECT 649.520 4.600 651.360 155.880 ; - RECT 653.200 4.600 655.040 155.880 ; - RECT 656.880 4.600 658.720 155.880 ; - RECT 660.560 4.600 662.400 155.880 ; - RECT 664.240 4.600 666.080 155.880 ; - RECT 667.920 4.600 669.760 155.880 ; - RECT 671.600 4.600 673.440 155.880 ; - RECT 675.280 4.600 677.120 155.880 ; - RECT 678.960 4.600 680.800 155.880 ; - RECT 682.640 4.600 684.480 155.880 ; - RECT 686.320 4.600 688.160 155.880 ; - RECT 690.000 4.600 691.840 155.880 ; - RECT 693.680 4.600 695.520 155.880 ; - RECT 697.360 4.600 699.200 155.880 ; - RECT 701.040 4.600 702.880 155.880 ; - RECT 704.720 4.600 706.560 155.880 ; - RECT 708.400 4.600 710.240 155.880 ; - RECT 712.080 4.600 713.920 155.880 ; - RECT 715.760 4.600 717.600 155.880 ; - RECT 719.440 4.600 721.280 155.880 ; - RECT 723.120 4.600 724.960 155.880 ; - RECT 726.800 4.600 728.640 155.880 ; - RECT 730.480 4.600 732.320 155.880 ; - RECT 734.160 4.600 736.000 155.880 ; - RECT 737.840 4.600 739.680 155.880 ; - RECT 741.520 4.600 743.360 155.880 ; - RECT 745.200 4.600 747.040 155.880 ; - RECT 748.880 4.600 750.720 155.880 ; - RECT 752.560 4.600 754.400 155.880 ; - RECT 756.240 4.600 758.080 155.880 ; - RECT 759.920 4.600 761.760 155.880 ; - RECT 763.600 4.600 765.440 155.880 ; - RECT 767.280 4.600 769.120 155.880 ; - RECT 770.960 4.600 772.800 155.880 ; - RECT 774.640 4.600 776.480 155.880 ; - RECT 778.320 4.600 780.160 155.880 ; - RECT 782.000 4.600 783.840 155.880 ; - RECT 785.680 4.600 787.520 155.880 ; - RECT 789.360 4.600 791.200 155.880 ; - RECT 793.040 4.600 794.880 155.880 ; - RECT 796.720 4.600 798.560 155.880 ; - RECT 800.400 4.600 802.240 155.880 ; - RECT 804.080 4.600 805.920 155.880 ; - RECT 807.760 4.600 809.600 155.880 ; - RECT 811.440 4.600 813.280 155.880 ; - RECT 815.120 4.600 816.960 155.880 ; - RECT 818.800 4.600 820.640 155.880 ; - RECT 822.480 4.600 824.320 155.880 ; - RECT 826.160 4.600 828.000 155.880 ; - RECT 829.840 4.600 831.680 155.880 ; - RECT 833.520 4.600 835.360 155.880 ; - RECT 837.200 4.600 839.040 155.880 ; - RECT 840.880 4.600 842.720 155.880 ; - RECT 844.560 4.600 846.400 155.880 ; - RECT 848.240 4.600 850.080 155.880 ; - RECT 851.920 4.600 853.760 155.880 ; - RECT 855.600 4.600 857.440 155.880 ; - RECT 859.280 4.600 861.120 155.880 ; - RECT 862.960 4.600 864.800 155.880 ; - RECT 866.640 4.600 868.480 155.880 ; - RECT 870.320 4.600 872.160 155.880 ; - RECT 874.000 4.600 875.840 155.880 ; - RECT 877.680 4.600 879.520 155.880 ; - RECT 881.360 4.600 883.200 155.880 ; - RECT 885.040 4.600 886.880 155.880 ; - RECT 888.720 4.600 890.560 155.880 ; - RECT 892.400 4.600 894.240 155.880 ; - RECT 896.080 4.600 897.920 155.880 ; - RECT 899.760 4.600 901.600 155.880 ; - RECT 903.440 4.600 905.280 155.880 ; - RECT 907.120 4.600 908.960 155.880 ; - RECT 910.800 4.600 912.640 155.880 ; - RECT 914.480 4.600 916.320 155.880 ; - RECT 918.160 4.600 920.000 155.880 ; - RECT 921.840 4.600 923.680 155.880 ; - RECT 925.520 4.600 927.360 155.880 ; - RECT 929.200 4.600 931.040 155.880 ; - RECT 932.880 4.600 934.720 155.880 ; - RECT 936.560 4.600 938.400 155.880 ; - RECT 940.240 4.600 942.080 155.880 ; - RECT 943.920 4.600 945.760 155.880 ; - RECT 947.600 4.600 949.440 155.880 ; - RECT 951.280 4.600 953.120 155.880 ; - RECT 954.960 4.600 956.800 155.880 ; - RECT 958.640 4.600 960.480 155.880 ; - RECT 962.320 4.600 964.160 155.880 ; - RECT 966.000 4.600 967.840 155.880 ; - RECT 969.680 4.600 971.520 155.880 ; - RECT 973.360 4.600 975.200 155.880 ; - RECT 977.040 4.600 978.880 155.880 ; - RECT 980.720 4.600 982.560 155.880 ; - RECT 984.400 4.600 986.240 155.880 ; - RECT 988.080 4.600 989.920 155.880 ; - RECT 991.760 4.600 993.600 155.880 ; - RECT 995.440 4.600 997.280 155.880 ; - RECT 999.120 4.600 1000.960 155.880 ; - RECT 1002.800 4.600 1004.640 155.880 ; - RECT 1006.480 4.600 1010.160 155.880 ; - END -END fakeram130_256x64 - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/fakeram130_64x64.lef b/flow/platforms/sky130hd_fakestack/lef/fakeram130_64x64.lef deleted file mode 100644 index 0fdb0ccea9..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/fakeram130_64x64.lef +++ /dev/null @@ -1,2147 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram130_64x64 - FOREIGN fakeram130_64x64 0 0 ; - SYMMETRY X Y ; - SIZE 189.980 BY 232.560 ; - CLASS BLOCK ; - PIN w_mask_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 4.370 0.460 4.830 ; - END - END w_mask_in[0] - PIN w_mask_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 5.290 0.460 5.750 ; - END - END w_mask_in[1] - PIN w_mask_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 6.210 0.460 6.670 ; - END - END w_mask_in[2] - PIN w_mask_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 7.130 0.460 7.590 ; - END - END w_mask_in[3] - PIN w_mask_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.050 0.460 8.510 ; - END - END w_mask_in[4] - PIN w_mask_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 8.970 0.460 9.430 ; - END - END w_mask_in[5] - PIN w_mask_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 9.890 0.460 10.350 ; - END - END w_mask_in[6] - PIN w_mask_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 10.810 0.460 11.270 ; - END - END w_mask_in[7] - PIN w_mask_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 11.730 0.460 12.190 ; - END - END w_mask_in[8] - PIN w_mask_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 12.650 0.460 13.110 ; - END - END w_mask_in[9] - PIN w_mask_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 13.570 0.460 14.030 ; - END - END w_mask_in[10] - PIN w_mask_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 14.490 0.460 14.950 ; - END - END w_mask_in[11] - PIN w_mask_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 15.410 0.460 15.870 ; - END - END w_mask_in[12] - PIN w_mask_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 16.330 0.460 16.790 ; - END - END w_mask_in[13] - PIN w_mask_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 17.250 0.460 17.710 ; - END - END w_mask_in[14] - PIN w_mask_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 18.170 0.460 18.630 ; - END - END w_mask_in[15] - PIN w_mask_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 19.090 0.460 19.550 ; - END - END w_mask_in[16] - PIN w_mask_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.010 0.460 20.470 ; - END - END w_mask_in[17] - PIN w_mask_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 20.930 0.460 21.390 ; - END - END w_mask_in[18] - PIN w_mask_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 21.850 0.460 22.310 ; - END - END w_mask_in[19] - PIN w_mask_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 22.770 0.460 23.230 ; - END - END w_mask_in[20] - PIN w_mask_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 23.690 0.460 24.150 ; - END - END w_mask_in[21] - PIN w_mask_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 24.610 0.460 25.070 ; - END - END w_mask_in[22] - PIN w_mask_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 25.530 0.460 25.990 ; - END - END w_mask_in[23] - PIN w_mask_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 26.450 0.460 26.910 ; - END - END w_mask_in[24] - PIN w_mask_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 27.370 0.460 27.830 ; - END - END w_mask_in[25] - PIN w_mask_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 28.290 0.460 28.750 ; - END - END w_mask_in[26] - PIN w_mask_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 29.210 0.460 29.670 ; - END - END w_mask_in[27] - PIN w_mask_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 30.130 0.460 30.590 ; - END - END w_mask_in[28] - PIN w_mask_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.050 0.460 31.510 ; - END - END w_mask_in[29] - PIN w_mask_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 31.970 0.460 32.430 ; - END - END w_mask_in[30] - PIN w_mask_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 32.890 0.460 33.350 ; - END - END w_mask_in[31] - PIN w_mask_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 33.810 0.460 34.270 ; - END - END w_mask_in[32] - PIN w_mask_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 34.730 0.460 35.190 ; - END - END w_mask_in[33] - PIN w_mask_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 35.650 0.460 36.110 ; - END - END w_mask_in[34] - PIN w_mask_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 36.570 0.460 37.030 ; - END - END w_mask_in[35] - PIN w_mask_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 37.490 0.460 37.950 ; - END - END w_mask_in[36] - PIN w_mask_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 38.410 0.460 38.870 ; - END - END w_mask_in[37] - PIN w_mask_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 39.330 0.460 39.790 ; - END - END w_mask_in[38] - PIN w_mask_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 40.250 0.460 40.710 ; - END - END w_mask_in[39] - PIN w_mask_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 41.170 0.460 41.630 ; - END - END w_mask_in[40] - PIN w_mask_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 42.090 0.460 42.550 ; - END - END w_mask_in[41] - PIN w_mask_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.010 0.460 43.470 ; - END - END w_mask_in[42] - PIN w_mask_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 43.930 0.460 44.390 ; - END - END w_mask_in[43] - PIN w_mask_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 44.850 0.460 45.310 ; - END - END w_mask_in[44] - PIN w_mask_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 45.770 0.460 46.230 ; - END - END w_mask_in[45] - PIN w_mask_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 46.690 0.460 47.150 ; - END - END w_mask_in[46] - PIN w_mask_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 47.610 0.460 48.070 ; - END - END w_mask_in[47] - PIN w_mask_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 48.530 0.460 48.990 ; - END - END w_mask_in[48] - PIN w_mask_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 49.450 0.460 49.910 ; - END - END w_mask_in[49] - PIN w_mask_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 50.370 0.460 50.830 ; - END - END w_mask_in[50] - PIN w_mask_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 51.290 0.460 51.750 ; - END - END w_mask_in[51] - PIN w_mask_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 52.210 0.460 52.670 ; - END - END w_mask_in[52] - PIN w_mask_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 53.130 0.460 53.590 ; - END - END w_mask_in[53] - PIN w_mask_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.050 0.460 54.510 ; - END - END w_mask_in[54] - PIN w_mask_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 54.970 0.460 55.430 ; - END - END w_mask_in[55] - PIN w_mask_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 55.890 0.460 56.350 ; - END - END w_mask_in[56] - PIN w_mask_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 56.810 0.460 57.270 ; - END - END w_mask_in[57] - PIN w_mask_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 57.730 0.460 58.190 ; - END - END w_mask_in[58] - PIN w_mask_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 58.650 0.460 59.110 ; - END - END w_mask_in[59] - PIN w_mask_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 59.570 0.460 60.030 ; - END - END w_mask_in[60] - PIN w_mask_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 60.490 0.460 60.950 ; - END - END w_mask_in[61] - PIN w_mask_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 61.410 0.460 61.870 ; - END - END w_mask_in[62] - PIN w_mask_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 62.330 0.460 62.790 ; - END - END w_mask_in[63] - PIN rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 71.530 0.460 71.990 ; - END - END rd_out[0] - PIN rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 72.450 0.460 72.910 ; - END - END rd_out[1] - PIN rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 73.370 0.460 73.830 ; - END - END rd_out[2] - PIN rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 74.290 0.460 74.750 ; - END - END rd_out[3] - PIN rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 75.210 0.460 75.670 ; - END - END rd_out[4] - PIN rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 76.130 0.460 76.590 ; - END - END rd_out[5] - PIN rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.050 0.460 77.510 ; - END - END rd_out[6] - PIN rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 77.970 0.460 78.430 ; - END - END rd_out[7] - PIN rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 78.890 0.460 79.350 ; - END - END rd_out[8] - PIN rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 79.810 0.460 80.270 ; - END - END rd_out[9] - PIN rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 80.730 0.460 81.190 ; - END - END rd_out[10] - PIN rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 81.650 0.460 82.110 ; - END - END rd_out[11] - PIN rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 82.570 0.460 83.030 ; - END - END rd_out[12] - PIN rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 83.490 0.460 83.950 ; - END - END rd_out[13] - PIN rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 84.410 0.460 84.870 ; - END - END rd_out[14] - PIN rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 85.330 0.460 85.790 ; - END - END rd_out[15] - PIN rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 86.250 0.460 86.710 ; - END - END rd_out[16] - PIN rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 87.170 0.460 87.630 ; - END - END rd_out[17] - PIN rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 88.090 0.460 88.550 ; - END - END rd_out[18] - PIN rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.010 0.460 89.470 ; - END - END rd_out[19] - PIN rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 89.930 0.460 90.390 ; - END - END rd_out[20] - PIN rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 90.850 0.460 91.310 ; - END - END rd_out[21] - PIN rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 91.770 0.460 92.230 ; - END - END rd_out[22] - PIN rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 92.690 0.460 93.150 ; - END - END rd_out[23] - PIN rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 93.610 0.460 94.070 ; - END - END rd_out[24] - PIN rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 94.530 0.460 94.990 ; - END - END rd_out[25] - PIN rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 95.450 0.460 95.910 ; - END - END rd_out[26] - PIN rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 96.370 0.460 96.830 ; - END - END rd_out[27] - PIN rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 97.290 0.460 97.750 ; - END - END rd_out[28] - PIN rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 98.210 0.460 98.670 ; - END - END rd_out[29] - PIN rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 99.130 0.460 99.590 ; - END - END rd_out[30] - PIN rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.050 0.460 100.510 ; - END - END rd_out[31] - PIN rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 100.970 0.460 101.430 ; - END - END rd_out[32] - PIN rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 101.890 0.460 102.350 ; - END - END rd_out[33] - PIN rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 102.810 0.460 103.270 ; - END - END rd_out[34] - PIN rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 103.730 0.460 104.190 ; - END - END rd_out[35] - PIN rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 104.650 0.460 105.110 ; - END - END rd_out[36] - PIN rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 105.570 0.460 106.030 ; - END - END rd_out[37] - PIN rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 106.490 0.460 106.950 ; - END - END rd_out[38] - PIN rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 107.410 0.460 107.870 ; - END - END rd_out[39] - PIN rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 108.330 0.460 108.790 ; - END - END rd_out[40] - PIN rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 109.250 0.460 109.710 ; - END - END rd_out[41] - PIN rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 110.170 0.460 110.630 ; - END - END rd_out[42] - PIN rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 111.090 0.460 111.550 ; - END - END rd_out[43] - PIN rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.010 0.460 112.470 ; - END - END rd_out[44] - PIN rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 112.930 0.460 113.390 ; - END - END rd_out[45] - PIN rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 113.850 0.460 114.310 ; - END - END rd_out[46] - PIN rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 114.770 0.460 115.230 ; - END - END rd_out[47] - PIN rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 115.690 0.460 116.150 ; - END - END rd_out[48] - PIN rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 116.610 0.460 117.070 ; - END - END rd_out[49] - PIN rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 117.530 0.460 117.990 ; - END - END rd_out[50] - PIN rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 118.450 0.460 118.910 ; - END - END rd_out[51] - PIN rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 119.370 0.460 119.830 ; - END - END rd_out[52] - PIN rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 120.290 0.460 120.750 ; - END - END rd_out[53] - PIN rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 121.210 0.460 121.670 ; - END - END rd_out[54] - PIN rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 122.130 0.460 122.590 ; - END - END rd_out[55] - PIN rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.050 0.460 123.510 ; - END - END rd_out[56] - PIN rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 123.970 0.460 124.430 ; - END - END rd_out[57] - PIN rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 124.890 0.460 125.350 ; - END - END rd_out[58] - PIN rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 125.810 0.460 126.270 ; - END - END rd_out[59] - PIN rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 126.730 0.460 127.190 ; - END - END rd_out[60] - PIN rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 127.650 0.460 128.110 ; - END - END rd_out[61] - PIN rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 128.570 0.460 129.030 ; - END - END rd_out[62] - PIN rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 129.490 0.460 129.950 ; - END - END rd_out[63] - PIN wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 138.690 0.460 139.150 ; - END - END wd_in[0] - PIN wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 139.610 0.460 140.070 ; - END - END wd_in[1] - PIN wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 140.530 0.460 140.990 ; - END - END wd_in[2] - PIN wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 141.450 0.460 141.910 ; - END - END wd_in[3] - PIN wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 142.370 0.460 142.830 ; - END - END wd_in[4] - PIN wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 143.290 0.460 143.750 ; - END - END wd_in[5] - PIN wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 144.210 0.460 144.670 ; - END - END wd_in[6] - PIN wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 145.130 0.460 145.590 ; - END - END wd_in[7] - PIN wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 146.050 0.460 146.510 ; - END - END wd_in[8] - PIN wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 146.970 0.460 147.430 ; - END - END wd_in[9] - PIN wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 147.890 0.460 148.350 ; - END - END wd_in[10] - PIN wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 148.810 0.460 149.270 ; - END - END wd_in[11] - PIN wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 149.730 0.460 150.190 ; - END - END wd_in[12] - PIN wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 150.650 0.460 151.110 ; - END - END wd_in[13] - PIN wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 151.570 0.460 152.030 ; - END - END wd_in[14] - PIN wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 152.490 0.460 152.950 ; - END - END wd_in[15] - PIN wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 153.410 0.460 153.870 ; - END - END wd_in[16] - PIN wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 154.330 0.460 154.790 ; - END - END wd_in[17] - PIN wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 155.250 0.460 155.710 ; - END - END wd_in[18] - PIN wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 156.170 0.460 156.630 ; - END - END wd_in[19] - PIN wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 157.090 0.460 157.550 ; - END - END wd_in[20] - PIN wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.010 0.460 158.470 ; - END - END wd_in[21] - PIN wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 158.930 0.460 159.390 ; - END - END wd_in[22] - PIN wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 159.850 0.460 160.310 ; - END - END wd_in[23] - PIN wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 160.770 0.460 161.230 ; - END - END wd_in[24] - PIN wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 161.690 0.460 162.150 ; - END - END wd_in[25] - PIN wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 162.610 0.460 163.070 ; - END - END wd_in[26] - PIN wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 163.530 0.460 163.990 ; - END - END wd_in[27] - PIN wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 164.450 0.460 164.910 ; - END - END wd_in[28] - PIN wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 165.370 0.460 165.830 ; - END - END wd_in[29] - PIN wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 166.290 0.460 166.750 ; - END - END wd_in[30] - PIN wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 167.210 0.460 167.670 ; - END - END wd_in[31] - PIN wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 168.130 0.460 168.590 ; - END - END wd_in[32] - PIN wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.050 0.460 169.510 ; - END - END wd_in[33] - PIN wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 169.970 0.460 170.430 ; - END - END wd_in[34] - PIN wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 170.890 0.460 171.350 ; - END - END wd_in[35] - PIN wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 171.810 0.460 172.270 ; - END - END wd_in[36] - PIN wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 172.730 0.460 173.190 ; - END - END wd_in[37] - PIN wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 173.650 0.460 174.110 ; - END - END wd_in[38] - PIN wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 174.570 0.460 175.030 ; - END - END wd_in[39] - PIN wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 175.490 0.460 175.950 ; - END - END wd_in[40] - PIN wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 176.410 0.460 176.870 ; - END - END wd_in[41] - PIN wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 177.330 0.460 177.790 ; - END - END wd_in[42] - PIN wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 178.250 0.460 178.710 ; - END - END wd_in[43] - PIN wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 179.170 0.460 179.630 ; - END - END wd_in[44] - PIN wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 180.090 0.460 180.550 ; - END - END wd_in[45] - PIN wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.010 0.460 181.470 ; - END - END wd_in[46] - PIN wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 181.930 0.460 182.390 ; - END - END wd_in[47] - PIN wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 182.850 0.460 183.310 ; - END - END wd_in[48] - PIN wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 183.770 0.460 184.230 ; - END - END wd_in[49] - PIN wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 184.690 0.460 185.150 ; - END - END wd_in[50] - PIN wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 185.610 0.460 186.070 ; - END - END wd_in[51] - PIN wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 186.530 0.460 186.990 ; - END - END wd_in[52] - PIN wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 187.450 0.460 187.910 ; - END - END wd_in[53] - PIN wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 188.370 0.460 188.830 ; - END - END wd_in[54] - PIN wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 189.290 0.460 189.750 ; - END - END wd_in[55] - PIN wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 190.210 0.460 190.670 ; - END - END wd_in[56] - PIN wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 191.130 0.460 191.590 ; - END - END wd_in[57] - PIN wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 192.050 0.460 192.510 ; - END - END wd_in[58] - PIN wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 192.970 0.460 193.430 ; - END - END wd_in[59] - PIN wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 193.890 0.460 194.350 ; - END - END wd_in[60] - PIN wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 194.810 0.460 195.270 ; - END - END wd_in[61] - PIN wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 195.730 0.460 196.190 ; - END - END wd_in[62] - PIN wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 196.650 0.460 197.110 ; - END - END wd_in[63] - PIN addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 205.850 0.460 206.310 ; - END - END addr_in[0] - PIN addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 206.770 0.460 207.230 ; - END - END addr_in[1] - PIN addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 207.690 0.460 208.150 ; - END - END addr_in[2] - PIN addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 208.610 0.460 209.070 ; - END - END addr_in[3] - PIN addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 209.530 0.460 209.990 ; - END - END addr_in[4] - PIN addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 210.450 0.460 210.910 ; - END - END addr_in[5] - PIN we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 219.650 0.460 220.110 ; - END - END we_in - PIN ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 220.570 0.460 221.030 ; - END - END ce_in - PIN clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER met3 ; - RECT 0.000 221.490 0.460 221.950 ; - END - END clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 3.680 4.600 5.520 227.960 ; - RECT 11.040 4.600 12.880 227.960 ; - RECT 18.400 4.600 20.240 227.960 ; - RECT 25.760 4.600 27.600 227.960 ; - RECT 33.120 4.600 34.960 227.960 ; - RECT 40.480 4.600 42.320 227.960 ; - RECT 47.840 4.600 49.680 227.960 ; - RECT 55.200 4.600 57.040 227.960 ; - RECT 62.560 4.600 64.400 227.960 ; - RECT 69.920 4.600 71.760 227.960 ; - RECT 77.280 4.600 79.120 227.960 ; - RECT 84.640 4.600 86.480 227.960 ; - RECT 92.000 4.600 93.840 227.960 ; - RECT 99.360 4.600 101.200 227.960 ; - RECT 106.720 4.600 108.560 227.960 ; - RECT 114.080 4.600 115.920 227.960 ; - RECT 121.440 4.600 123.280 227.960 ; - RECT 128.800 4.600 130.640 227.960 ; - RECT 136.160 4.600 138.000 227.960 ; - RECT 143.520 4.600 145.360 227.960 ; - RECT 150.880 4.600 152.720 227.960 ; - RECT 158.240 4.600 160.080 227.960 ; - RECT 165.600 4.600 167.440 227.960 ; - RECT 172.960 4.600 174.800 227.960 ; - RECT 180.320 4.600 182.160 227.960 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 7.360 4.600 9.200 227.960 ; - RECT 14.720 4.600 16.560 227.960 ; - RECT 22.080 4.600 23.920 227.960 ; - RECT 29.440 4.600 31.280 227.960 ; - RECT 36.800 4.600 38.640 227.960 ; - RECT 44.160 4.600 46.000 227.960 ; - RECT 51.520 4.600 53.360 227.960 ; - RECT 58.880 4.600 60.720 227.960 ; - RECT 66.240 4.600 68.080 227.960 ; - RECT 73.600 4.600 75.440 227.960 ; - RECT 80.960 4.600 82.800 227.960 ; - RECT 88.320 4.600 90.160 227.960 ; - RECT 95.680 4.600 97.520 227.960 ; - RECT 103.040 4.600 104.880 227.960 ; - RECT 110.400 4.600 112.240 227.960 ; - RECT 117.760 4.600 119.600 227.960 ; - RECT 125.120 4.600 126.960 227.960 ; - RECT 132.480 4.600 134.320 227.960 ; - RECT 139.840 4.600 141.680 227.960 ; - RECT 147.200 4.600 149.040 227.960 ; - RECT 154.560 4.600 156.400 227.960 ; - RECT 161.920 4.600 163.760 227.960 ; - RECT 169.280 4.600 171.120 227.960 ; - RECT 176.640 4.600 178.480 227.960 ; - RECT 184.000 4.600 185.840 227.960 ; - END - END VDD - OBS - LAYER met1 ; - RECT 0 0 189.980 232.560 ; - LAYER met2 ; - RECT 0 0 189.980 232.560 ; - LAYER met3 ; - RECT 0.460 0 189.980 232.560 ; - RECT 0 0.000 0.460 4.370 ; - RECT 0 4.830 0.460 5.290 ; - RECT 0 5.750 0.460 6.210 ; - RECT 0 6.670 0.460 7.130 ; - RECT 0 7.590 0.460 8.050 ; - RECT 0 8.510 0.460 8.970 ; - RECT 0 9.430 0.460 9.890 ; - RECT 0 10.350 0.460 10.810 ; - RECT 0 11.270 0.460 11.730 ; - RECT 0 12.190 0.460 12.650 ; - RECT 0 13.110 0.460 13.570 ; - RECT 0 14.030 0.460 14.490 ; - RECT 0 14.950 0.460 15.410 ; - RECT 0 15.870 0.460 16.330 ; - RECT 0 16.790 0.460 17.250 ; - RECT 0 17.710 0.460 18.170 ; - RECT 0 18.630 0.460 19.090 ; - RECT 0 19.550 0.460 20.010 ; - RECT 0 20.470 0.460 20.930 ; - RECT 0 21.390 0.460 21.850 ; - RECT 0 22.310 0.460 22.770 ; - RECT 0 23.230 0.460 23.690 ; - RECT 0 24.150 0.460 24.610 ; - RECT 0 25.070 0.460 25.530 ; - RECT 0 25.990 0.460 26.450 ; - RECT 0 26.910 0.460 27.370 ; - RECT 0 27.830 0.460 28.290 ; - RECT 0 28.750 0.460 29.210 ; - RECT 0 29.670 0.460 30.130 ; - RECT 0 30.590 0.460 31.050 ; - RECT 0 31.510 0.460 31.970 ; - RECT 0 32.430 0.460 32.890 ; - RECT 0 33.350 0.460 33.810 ; - RECT 0 34.270 0.460 34.730 ; - RECT 0 35.190 0.460 35.650 ; - RECT 0 36.110 0.460 36.570 ; - RECT 0 37.030 0.460 37.490 ; - RECT 0 37.950 0.460 38.410 ; - RECT 0 38.870 0.460 39.330 ; - RECT 0 39.790 0.460 40.250 ; - RECT 0 40.710 0.460 41.170 ; - RECT 0 41.630 0.460 42.090 ; - RECT 0 42.550 0.460 43.010 ; - RECT 0 43.470 0.460 43.930 ; - RECT 0 44.390 0.460 44.850 ; - RECT 0 45.310 0.460 45.770 ; - RECT 0 46.230 0.460 46.690 ; - RECT 0 47.150 0.460 47.610 ; - RECT 0 48.070 0.460 48.530 ; - RECT 0 48.990 0.460 49.450 ; - RECT 0 49.910 0.460 50.370 ; - RECT 0 50.830 0.460 51.290 ; - RECT 0 51.750 0.460 52.210 ; - RECT 0 52.670 0.460 53.130 ; - RECT 0 53.590 0.460 54.050 ; - RECT 0 54.510 0.460 54.970 ; - RECT 0 55.430 0.460 55.890 ; - RECT 0 56.350 0.460 56.810 ; - RECT 0 57.270 0.460 57.730 ; - RECT 0 58.190 0.460 58.650 ; - RECT 0 59.110 0.460 59.570 ; - RECT 0 60.030 0.460 60.490 ; - RECT 0 60.950 0.460 61.410 ; - RECT 0 61.870 0.460 62.330 ; - RECT 0 62.790 0.460 71.530 ; - RECT 0 71.990 0.460 72.450 ; - RECT 0 72.910 0.460 73.370 ; - RECT 0 73.830 0.460 74.290 ; - RECT 0 74.750 0.460 75.210 ; - RECT 0 75.670 0.460 76.130 ; - RECT 0 76.590 0.460 77.050 ; - RECT 0 77.510 0.460 77.970 ; - RECT 0 78.430 0.460 78.890 ; - RECT 0 79.350 0.460 79.810 ; - RECT 0 80.270 0.460 80.730 ; - RECT 0 81.190 0.460 81.650 ; - RECT 0 82.110 0.460 82.570 ; - RECT 0 83.030 0.460 83.490 ; - RECT 0 83.950 0.460 84.410 ; - RECT 0 84.870 0.460 85.330 ; - RECT 0 85.790 0.460 86.250 ; - RECT 0 86.710 0.460 87.170 ; - RECT 0 87.630 0.460 88.090 ; - RECT 0 88.550 0.460 89.010 ; - RECT 0 89.470 0.460 89.930 ; - RECT 0 90.390 0.460 90.850 ; - RECT 0 91.310 0.460 91.770 ; - RECT 0 92.230 0.460 92.690 ; - RECT 0 93.150 0.460 93.610 ; - RECT 0 94.070 0.460 94.530 ; - RECT 0 94.990 0.460 95.450 ; - RECT 0 95.910 0.460 96.370 ; - RECT 0 96.830 0.460 97.290 ; - RECT 0 97.750 0.460 98.210 ; - RECT 0 98.670 0.460 99.130 ; - RECT 0 99.590 0.460 100.050 ; - RECT 0 100.510 0.460 100.970 ; - RECT 0 101.430 0.460 101.890 ; - RECT 0 102.350 0.460 102.810 ; - RECT 0 103.270 0.460 103.730 ; - RECT 0 104.190 0.460 104.650 ; - RECT 0 105.110 0.460 105.570 ; - RECT 0 106.030 0.460 106.490 ; - RECT 0 106.950 0.460 107.410 ; - RECT 0 107.870 0.460 108.330 ; - RECT 0 108.790 0.460 109.250 ; - RECT 0 109.710 0.460 110.170 ; - RECT 0 110.630 0.460 111.090 ; - RECT 0 111.550 0.460 112.010 ; - RECT 0 112.470 0.460 112.930 ; - RECT 0 113.390 0.460 113.850 ; - RECT 0 114.310 0.460 114.770 ; - RECT 0 115.230 0.460 115.690 ; - RECT 0 116.150 0.460 116.610 ; - RECT 0 117.070 0.460 117.530 ; - RECT 0 117.990 0.460 118.450 ; - RECT 0 118.910 0.460 119.370 ; - RECT 0 119.830 0.460 120.290 ; - RECT 0 120.750 0.460 121.210 ; - RECT 0 121.670 0.460 122.130 ; - RECT 0 122.590 0.460 123.050 ; - RECT 0 123.510 0.460 123.970 ; - RECT 0 124.430 0.460 124.890 ; - RECT 0 125.350 0.460 125.810 ; - RECT 0 126.270 0.460 126.730 ; - RECT 0 127.190 0.460 127.650 ; - RECT 0 128.110 0.460 128.570 ; - RECT 0 129.030 0.460 129.490 ; - RECT 0 129.950 0.460 138.690 ; - RECT 0 139.150 0.460 139.610 ; - RECT 0 140.070 0.460 140.530 ; - RECT 0 140.990 0.460 141.450 ; - RECT 0 141.910 0.460 142.370 ; - RECT 0 142.830 0.460 143.290 ; - RECT 0 143.750 0.460 144.210 ; - RECT 0 144.670 0.460 145.130 ; - RECT 0 145.590 0.460 146.050 ; - RECT 0 146.510 0.460 146.970 ; - RECT 0 147.430 0.460 147.890 ; - RECT 0 148.350 0.460 148.810 ; - RECT 0 149.270 0.460 149.730 ; - RECT 0 150.190 0.460 150.650 ; - RECT 0 151.110 0.460 151.570 ; - RECT 0 152.030 0.460 152.490 ; - RECT 0 152.950 0.460 153.410 ; - RECT 0 153.870 0.460 154.330 ; - RECT 0 154.790 0.460 155.250 ; - RECT 0 155.710 0.460 156.170 ; - RECT 0 156.630 0.460 157.090 ; - RECT 0 157.550 0.460 158.010 ; - RECT 0 158.470 0.460 158.930 ; - RECT 0 159.390 0.460 159.850 ; - RECT 0 160.310 0.460 160.770 ; - RECT 0 161.230 0.460 161.690 ; - RECT 0 162.150 0.460 162.610 ; - RECT 0 163.070 0.460 163.530 ; - RECT 0 163.990 0.460 164.450 ; - RECT 0 164.910 0.460 165.370 ; - RECT 0 165.830 0.460 166.290 ; - RECT 0 166.750 0.460 167.210 ; - RECT 0 167.670 0.460 168.130 ; - RECT 0 168.590 0.460 169.050 ; - RECT 0 169.510 0.460 169.970 ; - RECT 0 170.430 0.460 170.890 ; - RECT 0 171.350 0.460 171.810 ; - RECT 0 172.270 0.460 172.730 ; - RECT 0 173.190 0.460 173.650 ; - RECT 0 174.110 0.460 174.570 ; - RECT 0 175.030 0.460 175.490 ; - RECT 0 175.950 0.460 176.410 ; - RECT 0 176.870 0.460 177.330 ; - RECT 0 177.790 0.460 178.250 ; - RECT 0 178.710 0.460 179.170 ; - RECT 0 179.630 0.460 180.090 ; - RECT 0 180.550 0.460 181.010 ; - RECT 0 181.470 0.460 181.930 ; - RECT 0 182.390 0.460 182.850 ; - RECT 0 183.310 0.460 183.770 ; - RECT 0 184.230 0.460 184.690 ; - RECT 0 185.150 0.460 185.610 ; - RECT 0 186.070 0.460 186.530 ; - RECT 0 186.990 0.460 187.450 ; - RECT 0 187.910 0.460 188.370 ; - RECT 0 188.830 0.460 189.290 ; - RECT 0 189.750 0.460 190.210 ; - RECT 0 190.670 0.460 191.130 ; - RECT 0 191.590 0.460 192.050 ; - RECT 0 192.510 0.460 192.970 ; - RECT 0 193.430 0.460 193.890 ; - RECT 0 194.350 0.460 194.810 ; - RECT 0 195.270 0.460 195.730 ; - RECT 0 196.190 0.460 196.650 ; - RECT 0 197.110 0.460 205.850 ; - RECT 0 206.310 0.460 206.770 ; - RECT 0 207.230 0.460 207.690 ; - RECT 0 208.150 0.460 208.610 ; - RECT 0 209.070 0.460 209.530 ; - RECT 0 209.990 0.460 210.450 ; - RECT 0 210.910 0.460 219.650 ; - RECT 0 220.110 0.460 220.570 ; - RECT 0 221.030 0.460 221.490 ; - RECT 0 221.950 0.460 232.560 ; - LAYER met4 ; - RECT 0 0 189.980 4.600 ; - RECT 0 227.960 189.980 232.560 ; - RECT 0.000 4.600 3.680 227.960 ; - RECT 5.520 4.600 7.360 227.960 ; - RECT 9.200 4.600 11.040 227.960 ; - RECT 12.880 4.600 14.720 227.960 ; - RECT 16.560 4.600 18.400 227.960 ; - RECT 20.240 4.600 22.080 227.960 ; - RECT 23.920 4.600 25.760 227.960 ; - RECT 27.600 4.600 29.440 227.960 ; - RECT 31.280 4.600 33.120 227.960 ; - RECT 34.960 4.600 36.800 227.960 ; - RECT 38.640 4.600 40.480 227.960 ; - RECT 42.320 4.600 44.160 227.960 ; - RECT 46.000 4.600 47.840 227.960 ; - RECT 49.680 4.600 51.520 227.960 ; - RECT 53.360 4.600 55.200 227.960 ; - RECT 57.040 4.600 58.880 227.960 ; - RECT 60.720 4.600 62.560 227.960 ; - RECT 64.400 4.600 66.240 227.960 ; - RECT 68.080 4.600 69.920 227.960 ; - RECT 71.760 4.600 73.600 227.960 ; - RECT 75.440 4.600 77.280 227.960 ; - RECT 79.120 4.600 80.960 227.960 ; - RECT 82.800 4.600 84.640 227.960 ; - RECT 86.480 4.600 88.320 227.960 ; - RECT 90.160 4.600 92.000 227.960 ; - RECT 93.840 4.600 95.680 227.960 ; - RECT 97.520 4.600 99.360 227.960 ; - RECT 101.200 4.600 103.040 227.960 ; - RECT 104.880 4.600 106.720 227.960 ; - RECT 108.560 4.600 110.400 227.960 ; - RECT 112.240 4.600 114.080 227.960 ; - RECT 115.920 4.600 117.760 227.960 ; - RECT 119.600 4.600 121.440 227.960 ; - RECT 123.280 4.600 125.120 227.960 ; - RECT 126.960 4.600 128.800 227.960 ; - RECT 130.640 4.600 132.480 227.960 ; - RECT 134.320 4.600 136.160 227.960 ; - RECT 138.000 4.600 139.840 227.960 ; - RECT 141.680 4.600 143.520 227.960 ; - RECT 145.360 4.600 147.200 227.960 ; - RECT 149.040 4.600 150.880 227.960 ; - RECT 152.720 4.600 154.560 227.960 ; - RECT 156.400 4.600 158.240 227.960 ; - RECT 160.080 4.600 161.920 227.960 ; - RECT 163.760 4.600 165.600 227.960 ; - RECT 167.440 4.600 169.280 227.960 ; - RECT 171.120 4.600 172.960 227.960 ; - RECT 174.800 4.600 176.640 227.960 ; - RECT 178.480 4.600 180.320 227.960 ; - RECT 182.160 4.600 184.000 227.960 ; - RECT 185.840 4.600 189.980 227.960 ; - END -END fakeram130_64x64 - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd.tlef b/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd.tlef deleted file mode 100644 index 4e232ac725..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd.tlef +++ /dev/null @@ -1,792 +0,0 @@ -# Copyright 2020 The SkyWater PDK Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -VERSION 5.7 ; - -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; -USEMINSPACING OBS OFF ; - -UNITS - TIME NANOSECONDS 1 ; - CAPACITANCE PICOFARADS 1 ; - RESISTANCE OHMS 1 ; - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -PROPERTYDEFINITIONS - LAYER LEF58_TYPE STRING ; -END PROPERTYDEFINITIONS - -# High density, single height -SITE unithd - SYMMETRY Y ; - CLASS CORE ; - SIZE 0.46 BY 2.72 ; -END unithd - -# High density, double height -SITE unithddbl - SYMMETRY Y ; - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -LAYER nwell - TYPE MASTERSLICE ; - PROPERTY LEF58_TYPE "TYPE NWELL ;" ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; - PROPERTY LEF58_TYPE "TYPE PWELL ;" ; -END pwell - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.46 0.34 ; - OFFSET 0.23 0.17 ; - - WIDTH 0.17 ; # LI 1 - # SPACING 0.17 ; # LI 2 - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.17 ; - AREA 0.0561 ; # LI 6 - THICKNESS 0.1 ; - EDGECAPACITANCE 40.697E-6 ; - CAPACITANCE CPERSQDIST 36.9866E-6 ; - RESISTANCE RPERSQ 12.2 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ; -END li1 - -LAYER mcon - TYPE CUT ; - - WIDTH 0.17 ; # Mcon 1 - SPACING 0.19 ; # Mcon 2 - ENCLOSURE BELOW 0 0 ; # Mcon 4 - ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5 - - ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ; - DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC - -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 0.34 ; - OFFSET 0.17 ; - - WIDTH 0.14 ; # Met1 1 - # SPACING 0.14 ; # Met1 2 - # SPACING 0.28 RANGE 3.001 100 ; # Met1 3b - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.083 ; # Met1 6 - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - EDGECAPACITANCE 40.567E-6 ; - CAPACITANCE CPERSQDIST 25.7784E-6 ; - DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC - ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; - - RESISTANCE RPERSQ 0.125 ; -END met1 - -LAYER via - TYPE CUT ; - WIDTH 0.15 ; # Via 1a - SPACING 0.17 ; # Via 2 - ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a - ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5 - - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.46 ; - OFFSET 0.23 ; - - WIDTH 0.14 ; # Met2 1 - # SPACING 0.14 ; # Met2 2 - # SPACING 0.28 RANGE 3.001 100 ; # Met2 3b - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.14 - WIDTH 3 0.28 ; - AREA 0.0676 ; # Met2 6 - THICKNESS 0.35 ; - MINENCLOSEDAREA 0.14 ; - - EDGECAPACITANCE 37.759E-6 ; - CAPACITANCE CPERSQDIST 16.9423E-6 ; - RESISTANCE RPERSQ 0.125 ; - DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC - ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met2 - -# ******** Layer via2, type routing, number 44 ************** -LAYER via2 - TYPE CUT ; - WIDTH 0.2 ; # Via2 1 - SPACING 0.2 ; # Via2 2 - ENCLOSURE BELOW 0.04 0.085 ; # Via2 4 - ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4 - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 0.68 ; - OFFSET 0.34 ; - - WIDTH 0.3 ; # Met3 1 - # SPACING 0.3 ; # Met3 2 - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; # Met3 6 - THICKNESS 0.8 ; - - EDGECAPACITANCE 40.989E-6 ; - CAPACITANCE CPERSQDIST 12.3729E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC - ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met3 - -LAYER via3 - TYPE CUT ; - WIDTH 0.2 ; # Via3 1 - SPACING 0.2 ; # Via3 2 - ENCLOSURE BELOW 0.06 0.09 ; # Via3 4 / Via3 5 - ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3 - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - - PITCH 0.92 ; - OFFSET 0.46 ; - - WIDTH 0.3 ; # Met4 1 - # SPACING 0.3 ; # Met4 2 - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 0.3 - WIDTH 3 0.4 ; - AREA 0.24 ; # Met4 4a - - THICKNESS 0.8 ; - - EDGECAPACITANCE 36.676E-6 ; - CAPACITANCE CPERSQDIST 8.41537E-6 ; - RESISTANCE RPERSQ 0.047 ; - DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC - ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; - - MAXIMUMDENSITY 70 ; - DENSITYCHECKWINDOW 700 700 ; - DENSITYCHECKSTEP 70 ; -END met4 - -LAYER via4 - TYPE CUT ; - - WIDTH 0.8 ; # Via4 1 - SPACING 0.8 ; # Via4 2 - ENCLOSURE BELOW 0.19 0.19 ; # Via4 4 - ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3 - ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ; - DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - - PITCH 3.4 ; - OFFSET 1.7 ; - - WIDTH 1.6 ; # Met5 1 - #SPACING 1.6 ; # Met5 2 - SPACINGTABLE - PARALLELRUNLENGTH 0 - WIDTH 0 1.6 ; - AREA 4 ; # Met5 4 - - THICKNESS 1.2 ; - - EDGECAPACITANCE 38.851E-6 ; - CAPACITANCE CPERSQDIST 6.32063E-6 ; - RESISTANCE RPERSQ 0.0285 ; - DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC - ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC - - ANTENNAMODEL OXIDE1 ; - ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ; -END met5 - - -### Routing via cells section ### -# Plus via rule, metals are along the prefered direction -VIA L1M1_PR DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIARULE L1M1_PR GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.03 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR - -# Plus via rule, metals are along the non prefered direction -VIA L1M1_PR_R DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIARULE L1M1_PR_R GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.03 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA L1M1_PR_M DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIARULE L1M1_PR_M GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.03 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA L1M1_PR_MR DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIARULE L1M1_PR_MR GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.03 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_MR - -# Centered via rule, we really do not want to use it -VIA L1M1_PR_C DEFAULT - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIARULE L1M1_PR_C GENERATE - LAYER li1 ; - ENCLOSURE 0 0 ; - LAYER met1 ; - ENCLOSURE 0.06 0.06 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - SPACING 0.36 BY 0.36 ; -END L1M1_PR_C - -# Plus via rule, metals are along the prefered direction -VIA M1M2_PR DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIARULE M1M2_PR GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.055 ; - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR - -# Plus via rule, metals are along the non prefered direction -VIA M1M2_PR_R DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIARULE M1M2_PR_R GENERATE - LAYER met1 ; - ENCLOSURE 0.055 0.085 ; - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M1M2_PR_M DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIARULE M1M2_PR_M GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.055 ; - LAYER met2 ; - ENCLOSURE 0.085 0.055 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M1M2_PR_MR DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIARULE M1M2_PR_MR GENERATE - LAYER met1 ; - ENCLOSURE 0.055 0.085 ; - LAYER met2 ; - ENCLOSURE 0.055 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_MR - -# Centered via rule, we really do not want to use it -VIA M1M2_PR_C DEFAULT - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIARULE M1M2_PR_C GENERATE - LAYER met1 ; - ENCLOSURE 0.085 0.085 ; - LAYER met2 ; - ENCLOSURE 0.085 0.085 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - SPACING 0.32 BY 0.32 ; -END M1M2_PR_C - -# Plus via rule, metals are along the prefered direction -VIA M2M3_PR DEFAULT - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIARULE M2M3_PR GENERATE - LAYER met2 ; - ENCLOSURE 0.04 0.085 ; - LAYER met3 ; - ENCLOSURE 0.065 0.065 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M2M3_PR - -# Plus via rule, metals are along the non prefered direction -VIA M2M3_PR_R DEFAULT - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIARULE M2M3_PR_R GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.04 ; - LAYER met3 ; - ENCLOSURE 0.065 0.065 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M2M3_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M2M3_PR_M DEFAULT - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIARULE M2M3_PR_M GENERATE - LAYER met2 ; - ENCLOSURE 0.04 0.085 ; - LAYER met3 ; - ENCLOSURE 0.065 0.065 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M2M3_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M2M3_PR_MR DEFAULT - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIARULE M2M3_PR_MR GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.04 ; - LAYER met3 ; - ENCLOSURE 0.065 0.065 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M2M3_PR_MR - -# Centered via rule, we really do not want to use it -VIA M2M3_PR_C DEFAULT - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIARULE M2M3_PR_C GENERATE - LAYER met2 ; - ENCLOSURE 0.085 0.085 ; - LAYER met3 ; - ENCLOSURE 0.065 0.065 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M2M3_PR_C - -# Plus via rule, metals are along the prefered direction -VIA M3M4_PR DEFAULT - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIARULE M3M4_PR GENERATE - LAYER met3 ; - ENCLOSURE 0.09 0.06 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR - -# Plus via rule, metals are along the non prefered direction -VIA M3M4_PR_R DEFAULT - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIARULE M3M4_PR_R GENERATE - LAYER met3 ; - ENCLOSURE 0.06 0.09 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M3M4_PR_M DEFAULT - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIARULE M3M4_PR_M GENERATE - LAYER met3 ; - ENCLOSURE 0.09 0.06 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M3M4_PR_MR DEFAULT - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIARULE M3M4_PR_MR GENERATE - LAYER met3 ; - ENCLOSURE 0.06 0.09 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_MR - -# Centered via rule, we really do not want to use it -VIA M3M4_PR_C DEFAULT - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIARULE M3M4_PR_C GENERATE - LAYER met3 ; - ENCLOSURE 0.09 0.09 ; - LAYER met4 ; - ENCLOSURE 0.065 0.065 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - SPACING 0.4 BY 0.4 ; -END M3M4_PR_C - -# Plus via rule, metals are along the prefered direction -VIA M4M5_PR DEFAULT - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIARULE M4M5_PR GENERATE - LAYER met4 ; - ENCLOSURE 0.19 0.19 ; - LAYER met5 ; - ENCLOSURE 0.31 0.31 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - SPACING 1.6 BY 1.6 ; -END M4M5_PR - -# Plus via rule, metals are along the non prefered direction -VIA M4M5_PR_R DEFAULT - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIARULE M4M5_PR_R GENERATE - LAYER met4 ; - ENCLOSURE 0.19 0.19 ; - LAYER met5 ; - ENCLOSURE 0.31 0.31 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - SPACING 1.6 BY 1.6 ; -END M4M5_PR_R - -# Minus via rule, lower layer metal is along prefered direction -VIA M4M5_PR_M DEFAULT - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIARULE M4M5_PR_M GENERATE - LAYER met4 ; - ENCLOSURE 0.19 0.19 ; - LAYER met5 ; - ENCLOSURE 0.31 0.31 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - SPACING 1.6 BY 1.6 ; -END M4M5_PR_M - -# Minus via rule, upper layer metal is along prefered direction -VIA M4M5_PR_MR DEFAULT - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIARULE M4M5_PR_MR GENERATE - LAYER met4 ; - ENCLOSURE 0.19 0.19 ; - LAYER met5 ; - ENCLOSURE 0.31 0.31 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - SPACING 1.6 BY 1.6 ; -END M4M5_PR_MR - -# Centered via rule, we really do not want to use it -VIA M4M5_PR_C DEFAULT - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -VIARULE M4M5_PR_C GENERATE - LAYER met4 ; - ENCLOSURE 0.19 0.19 ; - LAYER met5 ; - ENCLOSURE 0.31 0.31 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - SPACING 1.6 BY 1.6 ; -END M4M5_PR_C -### end of single via cells ### - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd_merged.lef b/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd_merged.lef deleted file mode 100644 index 3392420376..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/sky130_fd_sc_hd_merged.lef +++ /dev/null @@ -1,68383 +0,0 @@ -# Copyright 2020 The SkyWater PDK Authors -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# https://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -VERSION 5.7 ; - DIVIDERCHAR "/" ; - BUSBITCHARS "[]" ; -MACRO sky130_ef_sc_hd__decap_12 - CLASS BLOCK ; - FOREIGN sky130_ef_sc_hd__decap_12 ; - ORIGIN 0.000 0.000 ; - SIZE 5.520 BY 2.720 ; - PIN VGND - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 1.670 0.630 2.010 1.460 ; - RECT 0.085 0.085 5.430 0.630 ; - RECT 0.000 -0.085 5.520 0.085 ; - LAYER mcon ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - LAYER met1 ; - RECT 0.000 -0.240 5.520 0.240 ; - END - END VGND - PIN VNB - DIRECTION INPUT ; - PORT - LAYER pwell ; - RECT 0.080 -0.130 0.360 0.150 ; - END - END VNB - PIN VPB - DIRECTION INPUT ; - PORT - LAYER nwell ; - RECT -0.190 1.305 5.710 2.910 ; - END - END VPB - PIN VPWR - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000 2.635 5.520 2.805 ; - RECT 0.085 2.200 5.430 2.635 ; - RECT 3.490 0.950 3.840 2.200 ; - LAYER mcon ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 1.065 2.635 1.235 2.805 ; - RECT 1.525 2.635 1.695 2.805 ; - RECT 1.985 2.635 2.155 2.805 ; - RECT 2.445 2.635 2.615 2.805 ; - RECT 2.905 2.635 3.075 2.805 ; - RECT 3.365 2.635 3.535 2.805 ; - RECT 3.825 2.635 3.995 2.805 ; - RECT 4.285 2.635 4.455 2.805 ; - RECT 4.745 2.635 4.915 2.805 ; - RECT 5.205 2.635 5.375 2.805 ; - LAYER met1 ; - RECT 0.000 2.480 5.520 2.960 ; - END - END VPWR -END sky130_ef_sc_hd__decap_12 - -#--------EOF--------- - -MACRO sky130_ef_sc_hd__fakediode_2 - CLASS CORE SPACER ; - FOREIGN sky130_ef_sc_hd__fakediode_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.920000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN DIODE - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.835000 2.465000 ; - END - END DIODE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.920000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.110000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.920000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.920000 0.085000 ; - RECT 0.000000 2.635000 0.920000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - END -END sky130_ef_sc_hd__fakediode_2 -#--------EOF--------- - -MACRO sky130_ef_sc_hd__fill_8 - CLASS CORE SPACER ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - END -END sky130_ef_sc_hd__fill_8 -#--------EOF--------- - -MACRO sky130_ef_sc_hd__fill_12 - CLASS CORE ; - FOREIGN sky130_ef_sc_hd__fill_12 ; - ORIGIN 0.000 0.000 ; - SIZE 5.520 BY 2.720 ; - SYMMETRY X Y R90 ; - SITE unithd ; - OBS - LAYER nwell ; - RECT -0.190 1.305 5.710 2.910 ; - LAYER pwell ; - RECT 0.145 -0.085 0.315 0.085 ; - RECT 2.935 -0.060 3.045 0.060 ; - RECT 4.755 -0.050 4.915 0.060 ; - LAYER li1 ; - RECT 0.000 2.635 5.520 2.805 ; - RECT 0.085 1.545 2.675 2.635 ; - RECT 0.085 0.855 1.295 1.375 ; - RECT 1.465 1.025 2.675 1.545 ; - RECT 0.085 0.085 2.675 0.855 ; - RECT 0.000 -0.085 5.520 0.085 ; - LAYER mcon ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 1.065 2.635 1.235 2.805 ; - RECT 1.525 2.635 1.695 2.805 ; - RECT 1.985 2.635 2.155 2.805 ; - RECT 2.445 2.635 2.615 2.805 ; - RECT 2.905 2.635 3.075 2.805 ; - RECT 3.365 2.635 3.535 2.805 ; - RECT 3.825 2.635 3.995 2.805 ; - RECT 4.285 2.635 4.455 2.805 ; - RECT 4.745 2.635 4.915 2.805 ; - RECT 5.205 2.635 5.375 2.805 ; - RECT 0.145 -0.085 0.315 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - LAYER met1 ; - RECT 0.000 2.480 5.520 2.960 ; - RECT 0.000 -0.240 5.520 0.240 ; - END -END sky130_ef_sc_hd__fill_12 - -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.910000 0.995000 1.240000 1.615000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.410000 0.995000 1.700000 1.375000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.280000 0.765000 3.540000 1.655000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.600000 1.355000 3.080000 1.655000 ; - RECT 2.820000 0.765000 3.080000 1.355000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.345000 0.810000 ; - RECT 0.085000 0.810000 0.260000 1.525000 ; - RECT 0.085000 1.525000 0.345000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.430000 0.995000 0.685000 1.325000 ; - RECT 0.515000 0.085000 0.945000 0.530000 ; - RECT 0.515000 1.325000 0.685000 1.805000 ; - RECT 0.515000 1.805000 1.275000 1.975000 ; - RECT 0.515000 2.235000 0.845000 2.635000 ; - RECT 1.105000 1.975000 1.275000 2.200000 ; - RECT 1.105000 2.200000 2.245000 2.370000 ; - RECT 1.180000 0.255000 1.350000 0.655000 ; - RECT 1.180000 0.655000 2.060000 0.825000 ; - RECT 1.520000 0.085000 2.240000 0.485000 ; - RECT 1.540000 1.545000 2.060000 1.715000 ; - RECT 1.540000 1.715000 1.710000 1.905000 ; - RECT 1.890000 0.825000 2.060000 1.545000 ; - RECT 1.990000 1.895000 2.400000 2.065000 ; - RECT 1.990000 2.065000 2.245000 2.200000 ; - RECT 1.990000 2.370000 2.245000 2.465000 ; - RECT 2.230000 0.700000 2.580000 0.870000 ; - RECT 2.230000 0.870000 2.400000 1.895000 ; - RECT 2.410000 0.255000 2.580000 0.700000 ; - RECT 2.415000 2.255000 2.745000 2.425000 ; - RECT 2.575000 1.835000 3.515000 2.005000 ; - RECT 2.575000 2.005000 2.745000 2.255000 ; - RECT 2.915000 2.175000 3.165000 2.635000 ; - RECT 3.155000 0.085000 3.555000 0.595000 ; - RECT 3.335000 2.005000 3.515000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a2bb2o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.345000 0.995000 1.675000 1.615000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.845000 0.995000 2.135000 1.375000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.730000 0.765000 3.990000 1.655000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.050000 1.355000 3.530000 1.655000 ; - RECT 3.270000 0.765000 3.530000 1.355000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.525000 0.255000 0.780000 0.810000 ; - RECT 0.525000 0.810000 0.695000 1.525000 ; - RECT 0.525000 1.525000 0.780000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.125000 -0.085000 0.295000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.185000 0.085000 0.355000 0.930000 ; - RECT 0.185000 1.445000 0.355000 2.635000 ; - RECT 0.865000 0.995000 1.120000 1.325000 ; - RECT 0.950000 0.085000 1.380000 0.530000 ; - RECT 0.950000 1.325000 1.120000 1.805000 ; - RECT 0.950000 1.805000 1.710000 1.975000 ; - RECT 0.950000 2.235000 1.280000 2.635000 ; - RECT 1.540000 1.975000 1.710000 2.200000 ; - RECT 1.540000 2.200000 2.670000 2.370000 ; - RECT 1.615000 0.255000 1.785000 0.655000 ; - RECT 1.615000 0.655000 2.510000 0.825000 ; - RECT 1.955000 0.085000 2.690000 0.485000 ; - RECT 1.975000 1.545000 2.510000 1.715000 ; - RECT 1.975000 1.715000 2.145000 1.905000 ; - RECT 2.340000 0.825000 2.510000 1.545000 ; - RECT 2.440000 1.895000 2.850000 2.065000 ; - RECT 2.440000 2.065000 2.670000 2.200000 ; - RECT 2.500000 2.370000 2.670000 2.465000 ; - RECT 2.680000 0.700000 3.030000 0.870000 ; - RECT 2.680000 0.870000 2.850000 1.895000 ; - RECT 2.860000 0.255000 3.030000 0.700000 ; - RECT 2.875000 2.255000 3.205000 2.425000 ; - RECT 3.035000 1.835000 3.965000 2.005000 ; - RECT 3.035000 2.005000 3.205000 2.255000 ; - RECT 3.375000 2.175000 3.625000 2.635000 ; - RECT 3.605000 0.085000 4.005000 0.595000 ; - RECT 3.795000 2.005000 3.965000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a2bb2o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.315000 1.075000 3.645000 1.325000 ; - RECT 3.475000 1.325000 3.645000 1.445000 ; - RECT 3.475000 1.445000 4.965000 1.615000 ; - RECT 4.605000 1.075000 4.965000 1.445000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.815000 1.075000 4.435000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.575000 1.445000 ; - RECT 0.085000 1.445000 1.685000 1.615000 ; - RECT 1.515000 1.075000 1.895000 1.245000 ; - RECT 1.515000 1.245000 1.685000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.805000 1.075000 1.345000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.235000 0.275000 5.565000 0.725000 ; - RECT 5.235000 0.725000 6.920000 0.905000 ; - RECT 5.275000 1.785000 6.365000 1.955000 ; - RECT 5.275000 1.955000 5.525000 2.465000 ; - RECT 6.075000 0.275000 6.405000 0.725000 ; - RECT 6.115000 1.415000 6.920000 1.655000 ; - RECT 6.115000 1.655000 6.365000 1.785000 ; - RECT 6.115000 1.955000 6.365000 2.465000 ; - RECT 6.610000 0.905000 6.920000 1.415000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.135000 1.785000 2.065000 1.955000 ; - RECT 0.135000 1.955000 0.385000 2.465000 ; - RECT 0.175000 0.085000 0.345000 0.895000 ; - RECT 0.515000 0.255000 1.685000 0.475000 ; - RECT 0.515000 0.475000 0.765000 0.905000 ; - RECT 0.555000 2.125000 0.805000 2.635000 ; - RECT 0.935000 0.645000 1.270000 0.735000 ; - RECT 0.935000 0.735000 2.525000 0.905000 ; - RECT 0.975000 1.955000 1.225000 2.465000 ; - RECT 1.395000 2.125000 1.645000 2.635000 ; - RECT 1.815000 1.955000 2.065000 2.295000 ; - RECT 1.815000 2.295000 2.905000 2.465000 ; - RECT 1.855000 0.085000 2.025000 0.555000 ; - RECT 1.855000 1.455000 2.065000 1.785000 ; - RECT 2.195000 0.255000 2.525000 0.735000 ; - RECT 2.235000 0.905000 2.445000 1.415000 ; - RECT 2.235000 1.415000 2.620000 1.965000 ; - RECT 2.235000 1.965000 2.485000 2.125000 ; - RECT 2.615000 1.075000 3.145000 1.245000 ; - RECT 2.655000 2.135000 2.905000 2.295000 ; - RECT 2.695000 0.085000 3.385000 0.555000 ; - RECT 2.955000 0.725000 4.725000 0.905000 ; - RECT 2.955000 0.905000 3.145000 1.075000 ; - RECT 2.955000 1.245000 3.145000 1.495000 ; - RECT 2.955000 1.495000 3.305000 1.665000 ; - RECT 3.135000 1.665000 3.305000 1.785000 ; - RECT 3.135000 1.785000 4.265000 1.965000 ; - RECT 3.175000 2.135000 3.425000 2.635000 ; - RECT 3.555000 0.255000 3.885000 0.725000 ; - RECT 3.595000 2.135000 3.845000 2.295000 ; - RECT 3.595000 2.295000 4.685000 2.465000 ; - RECT 4.015000 1.965000 4.265000 2.125000 ; - RECT 4.055000 0.085000 4.225000 0.555000 ; - RECT 4.395000 0.255000 4.725000 0.725000 ; - RECT 4.435000 1.785000 4.685000 2.295000 ; - RECT 4.855000 1.795000 5.105000 2.635000 ; - RECT 4.895000 0.085000 5.065000 0.895000 ; - RECT 5.135000 1.075000 6.440000 1.245000 ; - RECT 5.135000 1.245000 5.460000 1.615000 ; - RECT 5.695000 2.165000 5.945000 2.635000 ; - RECT 5.735000 0.085000 5.905000 0.555000 ; - RECT 6.535000 1.825000 6.785000 2.635000 ; - RECT 6.575000 0.085000 6.745000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.450000 1.445000 2.620000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.230000 1.445000 5.400000 1.615000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - LAYER met1 ; - RECT 2.390000 1.415000 2.680000 1.460000 ; - RECT 2.390000 1.460000 5.460000 1.600000 ; - RECT 2.390000 1.600000 2.680000 1.645000 ; - RECT 5.170000 1.415000 5.460000 1.460000 ; - RECT 5.170000 1.600000 5.460000 1.645000 ; - END -END sky130_fd_sc_hd__a2bb2o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.995000 0.520000 1.615000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.725000 1.010000 1.240000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.780000 0.995000 3.070000 1.615000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.245000 0.995000 2.610000 1.615000 ; - RECT 2.440000 0.425000 2.610000 0.995000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.515500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.420000 1.785000 1.945000 1.955000 ; - RECT 1.420000 1.955000 1.785000 2.465000 ; - RECT 1.775000 0.255000 2.205000 0.825000 ; - RECT 1.775000 0.825000 1.945000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.825000 ; - RECT 0.095000 1.805000 0.425000 2.635000 ; - RECT 0.595000 0.255000 0.765000 0.660000 ; - RECT 0.595000 0.660000 1.580000 0.830000 ; - RECT 0.875000 1.445000 1.580000 1.615000 ; - RECT 0.875000 1.615000 1.205000 2.465000 ; - RECT 0.935000 0.085000 1.605000 0.490000 ; - RECT 1.410000 0.830000 1.580000 1.445000 ; - RECT 1.955000 2.235000 2.285000 2.465000 ; - RECT 2.115000 1.785000 3.130000 1.955000 ; - RECT 2.115000 1.955000 2.285000 2.235000 ; - RECT 2.455000 2.135000 2.705000 2.635000 ; - RECT 2.795000 0.085000 3.125000 0.825000 ; - RECT 2.875000 1.955000 3.130000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a2bb2oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.310000 1.075000 4.205000 1.275000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.455000 1.075000 5.435000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.710000 1.445000 ; - RECT 0.085000 1.445000 2.030000 1.615000 ; - RECT 1.700000 1.075000 2.030000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.940000 1.075000 1.480000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.621000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 0.645000 1.400000 0.725000 ; - RECT 1.070000 0.725000 2.660000 0.905000 ; - RECT 2.330000 0.255000 2.660000 0.725000 ; - RECT 2.370000 0.905000 2.660000 1.660000 ; - RECT 2.370000 1.660000 2.620000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.270000 1.785000 2.200000 1.955000 ; - RECT 0.270000 1.955000 0.520000 2.465000 ; - RECT 0.310000 0.085000 0.480000 0.895000 ; - RECT 0.650000 0.255000 1.820000 0.475000 ; - RECT 0.650000 0.475000 0.900000 0.895000 ; - RECT 0.690000 2.135000 0.940000 2.635000 ; - RECT 1.110000 1.955000 1.360000 2.465000 ; - RECT 1.530000 2.135000 1.780000 2.635000 ; - RECT 1.950000 1.955000 2.200000 2.295000 ; - RECT 1.950000 2.295000 3.040000 2.465000 ; - RECT 1.990000 0.085000 2.160000 0.555000 ; - RECT 2.790000 1.795000 3.040000 2.295000 ; - RECT 2.830000 0.085000 3.520000 0.555000 ; - RECT 2.830000 0.995000 3.120000 1.325000 ; - RECT 2.950000 0.725000 4.860000 0.905000 ; - RECT 2.950000 0.905000 3.120000 0.995000 ; - RECT 2.950000 1.325000 3.120000 1.445000 ; - RECT 2.950000 1.445000 4.820000 1.615000 ; - RECT 3.310000 1.785000 4.400000 1.965000 ; - RECT 3.310000 1.965000 3.560000 2.465000 ; - RECT 3.690000 0.255000 4.020000 0.725000 ; - RECT 3.730000 2.135000 3.980000 2.635000 ; - RECT 4.150000 1.965000 4.400000 2.295000 ; - RECT 4.150000 2.295000 5.240000 2.465000 ; - RECT 4.190000 0.085000 4.360000 0.555000 ; - RECT 4.530000 0.255000 4.860000 0.725000 ; - RECT 4.570000 1.615000 4.820000 2.125000 ; - RECT 4.990000 1.455000 5.240000 2.295000 ; - RECT 5.030000 0.085000 5.200000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__a2bb2oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2bb2oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2bb2oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.945000 1.075000 7.320000 1.275000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.595000 1.075000 9.045000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.075000 1.555000 1.285000 ; - RECT 1.385000 1.285000 1.555000 1.445000 ; - RECT 1.385000 1.445000 3.575000 1.615000 ; - RECT 3.245000 1.075000 3.575000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.725000 1.075000 3.075000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.242000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.775000 0.645000 2.995000 0.725000 ; - RECT 1.775000 0.725000 5.045000 0.905000 ; - RECT 3.745000 0.905000 3.915000 1.415000 ; - RECT 3.745000 1.415000 4.965000 1.615000 ; - RECT 3.875000 0.275000 4.205000 0.725000 ; - RECT 3.915000 1.615000 4.165000 2.125000 ; - RECT 4.715000 0.275000 5.045000 0.725000 ; - RECT 4.745000 1.615000 4.965000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.085000 1.455000 1.215000 1.625000 ; - RECT 0.085000 1.625000 0.425000 2.465000 ; - RECT 0.175000 0.085000 0.345000 0.895000 ; - RECT 0.515000 0.255000 0.845000 0.725000 ; - RECT 0.515000 0.725000 1.605000 0.905000 ; - RECT 0.595000 1.795000 0.805000 2.635000 ; - RECT 0.975000 1.625000 1.215000 1.795000 ; - RECT 0.975000 1.795000 3.745000 1.965000 ; - RECT 0.975000 1.965000 1.215000 2.465000 ; - RECT 1.015000 0.085000 1.185000 0.555000 ; - RECT 1.355000 0.255000 3.365000 0.475000 ; - RECT 1.355000 0.475000 1.605000 0.725000 ; - RECT 1.395000 2.135000 1.645000 2.635000 ; - RECT 1.815000 1.965000 2.065000 2.465000 ; - RECT 2.235000 2.135000 2.485000 2.635000 ; - RECT 2.655000 1.965000 2.905000 2.465000 ; - RECT 3.075000 2.135000 3.325000 2.635000 ; - RECT 3.495000 1.965000 3.745000 2.295000 ; - RECT 3.495000 2.295000 5.465000 2.465000 ; - RECT 3.535000 0.085000 3.705000 0.555000 ; - RECT 4.085000 1.075000 5.725000 1.245000 ; - RECT 4.335000 1.795000 4.575000 2.295000 ; - RECT 4.375000 0.085000 4.545000 0.555000 ; - RECT 5.135000 1.455000 5.465000 2.295000 ; - RECT 5.215000 0.085000 5.905000 0.555000 ; - RECT 5.555000 0.735000 9.575000 0.905000 ; - RECT 5.555000 0.905000 5.725000 1.075000 ; - RECT 5.655000 1.455000 7.625000 1.625000 ; - RECT 5.655000 1.625000 5.985000 2.465000 ; - RECT 6.075000 0.255000 6.405000 0.725000 ; - RECT 6.075000 0.725000 8.925000 0.735000 ; - RECT 6.155000 1.795000 6.365000 2.635000 ; - RECT 6.540000 1.625000 6.780000 2.465000 ; - RECT 6.575000 0.085000 6.745000 0.555000 ; - RECT 6.915000 0.255000 7.245000 0.725000 ; - RECT 6.955000 1.795000 7.205000 2.635000 ; - RECT 7.375000 1.625000 7.625000 2.295000 ; - RECT 7.375000 2.295000 9.310000 2.465000 ; - RECT 7.415000 0.085000 7.585000 0.555000 ; - RECT 7.755000 0.255000 8.085000 0.725000 ; - RECT 7.795000 1.455000 9.575000 1.625000 ; - RECT 7.795000 1.625000 8.045000 2.125000 ; - RECT 8.215000 1.795000 8.465000 2.295000 ; - RECT 8.255000 0.085000 8.425000 0.555000 ; - RECT 8.595000 0.255000 8.925000 0.725000 ; - RECT 8.635000 1.625000 8.885000 2.125000 ; - RECT 9.060000 1.795000 9.310000 2.295000 ; - RECT 9.095000 0.085000 9.265000 0.555000 ; - RECT 9.215000 0.905000 9.575000 1.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__a2bb2oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21bo_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21bo_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.750000 0.995000 2.175000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.370000 0.995000 2.630000 1.615000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.325000 0.335000 1.665000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.300000 0.265000 3.580000 2.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.105000 1.845000 0.855000 2.045000 ; - RECT 0.105000 2.045000 0.345000 2.435000 ; - RECT 0.515000 0.265000 0.745000 1.165000 ; - RECT 0.515000 1.165000 0.855000 1.845000 ; - RECT 0.515000 2.225000 0.865000 2.635000 ; - RECT 0.945000 0.085000 1.190000 0.865000 ; - RECT 1.035000 1.045000 1.580000 1.345000 ; - RECT 1.035000 1.345000 1.365000 2.455000 ; - RECT 1.360000 0.265000 1.790000 0.625000 ; - RECT 1.360000 0.625000 3.100000 0.815000 ; - RECT 1.360000 0.815000 1.580000 1.045000 ; - RECT 1.535000 1.785000 2.560000 1.985000 ; - RECT 1.535000 1.985000 1.715000 2.455000 ; - RECT 1.885000 2.155000 2.215000 2.635000 ; - RECT 2.370000 0.085000 3.100000 0.455000 ; - RECT 2.390000 1.985000 2.560000 2.455000 ; - RECT 2.825000 1.495000 3.110000 2.635000 ; - RECT 2.840000 0.815000 3.100000 1.325000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a21bo_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21bo_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21bo_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.685000 0.995000 3.100000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.270000 0.995000 3.560000 1.615000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.035000 1.525000 1.325000 ; - RECT 1.330000 0.995000 1.525000 1.035000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.715000 0.850000 0.885000 ; - RECT 0.150000 0.885000 0.380000 1.835000 ; - RECT 0.150000 1.835000 0.850000 2.005000 ; - RECT 0.520000 0.315000 0.850000 0.715000 ; - RECT 0.595000 2.005000 0.850000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 0.085000 0.345000 0.545000 ; - RECT 0.090000 2.255000 0.425000 2.635000 ; - RECT 0.570000 1.075000 0.900000 1.495000 ; - RECT 0.570000 1.495000 1.285000 1.665000 ; - RECT 1.020000 0.085000 1.220000 0.865000 ; - RECT 1.040000 2.275000 1.370000 2.635000 ; - RECT 1.115000 1.665000 1.285000 1.895000 ; - RECT 1.115000 1.895000 2.225000 2.105000 ; - RECT 1.455000 0.655000 1.865000 0.825000 ; - RECT 1.455000 1.555000 1.865000 1.725000 ; - RECT 1.695000 0.825000 1.865000 0.995000 ; - RECT 1.695000 0.995000 2.175000 1.325000 ; - RECT 1.695000 1.325000 1.865000 1.555000 ; - RECT 1.975000 0.085000 2.305000 0.465000 ; - RECT 1.975000 2.105000 2.225000 2.465000 ; - RECT 2.055000 1.505000 2.515000 1.675000 ; - RECT 2.055000 1.675000 2.225000 1.895000 ; - RECT 2.345000 0.635000 2.740000 0.825000 ; - RECT 2.345000 0.825000 2.515000 1.505000 ; - RECT 2.395000 1.845000 3.565000 2.015000 ; - RECT 2.395000 2.015000 2.725000 2.465000 ; - RECT 2.895000 2.185000 3.065000 2.635000 ; - RECT 3.235000 0.085000 3.565000 0.825000 ; - RECT 3.235000 2.015000 3.565000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a21bo_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21bo_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21bo_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.590000 1.010000 4.955000 1.360000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.025000 1.010000 4.420000 1.275000 ; - RECT 4.245000 1.275000 4.420000 1.595000 ; - RECT 4.245000 1.595000 5.390000 1.765000 ; - RECT 5.220000 1.055000 5.700000 1.290000 ; - RECT 5.220000 1.290000 5.390000 1.595000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.500000 1.010000 0.830000 1.625000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.000000 0.615000 2.340000 0.785000 ; - RECT 1.000000 0.785000 1.235000 1.595000 ; - RECT 1.000000 1.595000 2.410000 1.765000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.105000 0.255000 0.540000 0.840000 ; - RECT 0.105000 0.840000 0.330000 1.795000 ; - RECT 0.105000 1.795000 0.565000 1.935000 ; - RECT 0.105000 1.935000 2.870000 2.105000 ; - RECT 0.105000 2.105000 0.550000 2.465000 ; - RECT 0.710000 0.085000 1.050000 0.445000 ; - RECT 0.720000 2.275000 1.050000 2.635000 ; - RECT 1.405000 0.995000 2.810000 1.185000 ; - RECT 1.405000 1.185000 2.530000 1.325000 ; - RECT 1.580000 0.085000 1.910000 0.445000 ; - RECT 1.580000 2.275000 1.910000 2.635000 ; - RECT 2.435000 2.275000 2.770000 2.635000 ; - RECT 2.515000 0.085000 3.285000 0.445000 ; - RECT 2.640000 0.615000 3.645000 0.670000 ; - RECT 2.640000 0.670000 4.965000 0.785000 ; - RECT 2.640000 0.785000 3.010000 0.800000 ; - RECT 2.640000 0.800000 2.810000 0.995000 ; - RECT 2.700000 1.355000 3.305000 1.525000 ; - RECT 2.700000 1.525000 2.870000 1.935000 ; - RECT 2.995000 0.995000 3.305000 1.355000 ; - RECT 3.055000 1.695000 3.225000 2.210000 ; - RECT 3.055000 2.210000 4.065000 2.380000 ; - RECT 3.475000 0.255000 3.645000 0.615000 ; - RECT 3.475000 0.785000 4.965000 0.840000 ; - RECT 3.475000 0.840000 3.645000 1.805000 ; - RECT 3.855000 0.085000 4.185000 0.445000 ; - RECT 3.885000 1.445000 4.065000 1.935000 ; - RECT 3.885000 1.935000 5.825000 2.105000 ; - RECT 3.885000 2.105000 4.065000 2.210000 ; - RECT 4.235000 2.275000 4.565000 2.635000 ; - RECT 4.685000 0.405000 4.965000 0.670000 ; - RECT 5.075000 2.275000 5.405000 2.635000 ; - RECT 5.545000 0.085000 5.825000 0.885000 ; - RECT 5.570000 1.460000 5.825000 1.935000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__a21bo_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21boi_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21boi_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.780000 0.765000 2.170000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.340000 0.765000 2.615000 1.435000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.470000 1.200000 0.895000 1.955000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 0.392200 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 1.200000 1.610000 1.655000 ; - RECT 1.065000 1.655000 1.305000 2.465000 ; - RECT 1.315000 0.255000 1.610000 1.200000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 0.280000 0.380000 0.780000 ; - RECT 0.095000 0.780000 1.145000 1.030000 ; - RECT 0.095000 1.030000 0.300000 2.085000 ; - RECT 0.095000 2.085000 0.355000 2.465000 ; - RECT 0.525000 2.175000 0.855000 2.635000 ; - RECT 0.550000 0.085000 1.145000 0.610000 ; - RECT 1.475000 1.825000 2.665000 2.005000 ; - RECT 1.475000 2.005000 1.805000 2.465000 ; - RECT 1.975000 2.175000 2.165000 2.635000 ; - RECT 2.335000 0.085000 2.665000 0.595000 ; - RECT 2.335000 2.005000 2.665000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__a21boi_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21boi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21boi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.760000 0.995000 2.155000 1.345000 ; - RECT 1.945000 0.375000 2.155000 0.995000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.350000 0.995000 2.640000 1.345000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.975000 0.335000 1.665000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 0.551000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.045000 1.045000 1.580000 1.345000 ; - RECT 1.045000 1.345000 1.375000 2.455000 ; - RECT 1.335000 0.265000 1.765000 0.795000 ; - RECT 1.335000 0.795000 1.580000 1.045000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 1.845000 0.855000 2.045000 ; - RECT 0.095000 2.045000 0.355000 2.435000 ; - RECT 0.365000 0.265000 0.745000 0.715000 ; - RECT 0.515000 0.715000 0.745000 1.165000 ; - RECT 0.515000 1.165000 0.855000 1.845000 ; - RECT 0.525000 2.225000 0.855000 2.635000 ; - RECT 0.925000 0.085000 1.155000 0.865000 ; - RECT 1.545000 1.525000 2.585000 1.725000 ; - RECT 1.545000 1.725000 1.735000 2.455000 ; - RECT 1.905000 1.905000 2.235000 2.635000 ; - RECT 2.325000 0.085000 2.655000 0.815000 ; - RECT 2.415000 1.725000 2.585000 2.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__a21boi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21boi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21boi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.605000 0.995000 3.215000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.095000 1.075000 2.425000 1.245000 ; - RECT 2.100000 1.245000 2.425000 1.495000 ; - RECT 2.100000 1.495000 3.675000 1.675000 ; - RECT 3.385000 1.035000 3.795000 1.295000 ; - RECT 3.385000 1.295000 3.675000 1.495000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.765000 0.425000 1.805000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 0.627500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.520000 0.255000 1.720000 0.615000 ; - RECT 1.520000 0.615000 3.060000 0.785000 ; - RECT 1.520000 0.785000 1.715000 2.115000 ; - RECT 2.730000 0.255000 3.060000 0.615000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.095000 2.080000 0.425000 2.635000 ; - RECT 0.265000 0.360000 0.795000 0.530000 ; - RECT 0.595000 0.530000 0.795000 1.070000 ; - RECT 0.595000 1.070000 1.325000 1.285000 ; - RECT 0.595000 1.285000 0.855000 2.265000 ; - RECT 0.985000 0.085000 1.225000 0.885000 ; - RECT 1.045000 1.795000 1.350000 2.285000 ; - RECT 1.045000 2.285000 2.215000 2.465000 ; - RECT 1.885000 1.855000 3.920000 2.025000 ; - RECT 1.885000 2.025000 2.215000 2.285000 ; - RECT 1.940000 0.085000 2.270000 0.445000 ; - RECT 2.385000 2.195000 2.555000 2.635000 ; - RECT 2.810000 2.025000 3.920000 2.105000 ; - RECT 2.810000 2.105000 2.980000 2.465000 ; - RECT 3.160000 2.275000 3.490000 2.635000 ; - RECT 3.635000 0.085000 3.930000 0.865000 ; - RECT 3.660000 2.105000 3.920000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a21boi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21boi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21boi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.545000 1.065000 4.970000 1.310000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.030000 1.065000 3.375000 1.480000 ; - RECT 3.030000 1.480000 6.450000 1.705000 ; - RECT 5.205000 1.075000 6.450000 1.480000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 1.075000 0.650000 1.615000 ; - RECT 0.480000 0.995000 0.650000 1.075000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 1.288000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.275000 0.370000 1.465000 0.615000 ; - RECT 1.275000 0.615000 2.325000 0.695000 ; - RECT 1.275000 0.695000 4.885000 0.865000 ; - RECT 1.560000 1.585000 2.860000 1.705000 ; - RECT 1.560000 1.705000 2.725000 2.035000 ; - RECT 2.135000 0.255000 2.325000 0.615000 ; - RECT 2.570000 0.865000 4.885000 0.895000 ; - RECT 2.570000 0.895000 2.860000 1.585000 ; - RECT 3.255000 0.675000 4.885000 0.695000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.090000 0.255000 0.445000 0.615000 ; - RECT 0.090000 0.615000 1.105000 0.795000 ; - RECT 0.125000 1.785000 0.990000 2.005000 ; - RECT 0.125000 2.005000 0.455000 2.465000 ; - RECT 0.625000 2.175000 0.885000 2.635000 ; - RECT 0.720000 0.085000 1.105000 0.445000 ; - RECT 0.820000 0.795000 1.105000 1.035000 ; - RECT 0.820000 1.035000 2.400000 1.345000 ; - RECT 0.820000 1.345000 0.990000 1.785000 ; - RECT 1.160000 1.795000 1.355000 2.215000 ; - RECT 1.160000 2.215000 3.095000 2.465000 ; - RECT 1.635000 0.085000 1.965000 0.445000 ; - RECT 1.935000 2.205000 3.095000 2.215000 ; - RECT 2.495000 0.085000 3.085000 0.525000 ; - RECT 2.895000 1.875000 6.605000 2.105000 ; - RECT 2.895000 2.105000 3.095000 2.205000 ; - RECT 3.265000 0.255000 5.315000 0.505000 ; - RECT 3.265000 2.275000 3.595000 2.635000 ; - RECT 4.125000 2.275000 4.455000 2.635000 ; - RECT 4.625000 2.105000 4.815000 2.465000 ; - RECT 4.985000 2.275000 5.315000 2.635000 ; - RECT 5.055000 0.505000 5.315000 0.735000 ; - RECT 5.055000 0.735000 6.175000 0.905000 ; - RECT 5.485000 0.085000 5.675000 0.565000 ; - RECT 5.485000 2.105000 5.665000 2.465000 ; - RECT 5.845000 0.255000 6.175000 0.735000 ; - RECT 5.845000 2.275000 6.175000 2.635000 ; - RECT 6.345000 0.085000 6.605000 0.885000 ; - RECT 6.345000 2.105000 6.605000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - END -END sky130_fd_sc_hd__a21boi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.660000 1.015000 2.185000 1.325000 ; - RECT 1.955000 0.375000 2.185000 1.015000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.365000 0.995000 2.665000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.015000 1.015000 1.480000 1.325000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.265000 0.355000 2.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.525000 1.905000 0.865000 2.635000 ; - RECT 0.545000 0.635000 1.775000 0.835000 ; - RECT 0.545000 0.835000 0.835000 1.505000 ; - RECT 0.545000 1.505000 1.315000 1.725000 ; - RECT 0.615000 0.085000 1.285000 0.455000 ; - RECT 1.045000 1.725000 1.315000 2.455000 ; - RECT 1.465000 0.265000 1.775000 0.635000 ; - RECT 1.495000 1.505000 2.655000 1.745000 ; - RECT 1.495000 1.745000 1.725000 2.455000 ; - RECT 1.895000 1.925000 2.225000 2.635000 ; - RECT 2.365000 0.085000 2.655000 0.815000 ; - RECT 2.395000 1.745000 2.655000 2.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__a21o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.240000 0.365000 2.620000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.810000 0.750000 3.125000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 0.995000 1.790000 1.410000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.555000 0.635000 0.955000 0.825000 ; - RECT 0.555000 0.825000 0.785000 2.465000 ; - RECT 0.765000 0.255000 0.955000 0.635000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.095000 1.665000 0.385000 2.635000 ; - RECT 0.265000 0.085000 0.595000 0.465000 ; - RECT 0.955000 0.995000 1.295000 1.690000 ; - RECT 0.955000 1.690000 1.790000 1.920000 ; - RECT 0.955000 2.220000 1.285000 2.635000 ; - RECT 1.125000 0.085000 1.455000 0.445000 ; - RECT 1.125000 0.655000 1.865000 0.825000 ; - RECT 1.125000 0.825000 1.295000 0.995000 ; - RECT 1.475000 1.920000 1.790000 2.465000 ; - RECT 1.675000 0.255000 1.865000 0.655000 ; - RECT 1.960000 1.670000 3.075000 1.935000 ; - RECT 1.960000 1.935000 2.185000 2.465000 ; - RECT 2.355000 2.125000 2.685000 2.635000 ; - RECT 2.805000 0.085000 3.135000 0.565000 ; - RECT 2.855000 1.935000 3.075000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a21o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.990000 1.010000 4.515000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.425000 1.010000 3.820000 1.275000 ; - RECT 3.645000 1.275000 3.820000 1.510000 ; - RECT 3.645000 1.510000 4.935000 1.680000 ; - RECT 4.685000 1.055000 5.100000 1.290000 ; - RECT 4.685000 1.290000 4.935000 1.510000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.395000 0.995000 2.705000 1.525000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.615000 1.735000 0.785000 ; - RECT 0.145000 0.785000 0.630000 1.585000 ; - RECT 0.145000 1.585000 1.735000 1.755000 ; - RECT 0.625000 1.755000 0.795000 2.185000 ; - RECT 1.485000 1.755000 1.735000 2.185000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.105000 0.085000 0.445000 0.445000 ; - RECT 0.115000 1.935000 0.445000 2.635000 ; - RECT 0.800000 0.995000 2.205000 1.325000 ; - RECT 0.975000 0.085000 1.305000 0.445000 ; - RECT 0.975000 1.935000 1.305000 2.635000 ; - RECT 1.910000 0.085000 2.685000 0.445000 ; - RECT 1.915000 1.515000 2.165000 2.635000 ; - RECT 2.035000 0.615000 3.045000 0.670000 ; - RECT 2.035000 0.670000 4.365000 0.785000 ; - RECT 2.035000 0.785000 2.205000 0.995000 ; - RECT 2.455000 1.695000 2.625000 2.295000 ; - RECT 2.455000 2.295000 3.465000 2.465000 ; - RECT 2.875000 0.255000 3.045000 0.615000 ; - RECT 2.875000 0.785000 4.365000 0.840000 ; - RECT 2.875000 0.840000 3.045000 2.125000 ; - RECT 3.255000 0.085000 3.585000 0.445000 ; - RECT 3.285000 1.445000 3.465000 1.850000 ; - RECT 3.285000 1.850000 5.360000 2.020000 ; - RECT 3.285000 2.020000 3.465000 2.295000 ; - RECT 3.635000 2.275000 3.965000 2.635000 ; - RECT 4.085000 0.405000 4.365000 0.670000 ; - RECT 4.135000 2.020000 4.305000 2.465000 ; - RECT 4.475000 2.275000 4.805000 2.635000 ; - RECT 4.945000 0.085000 5.225000 0.885000 ; - RECT 5.030000 2.020000 5.360000 2.395000 ; - RECT 5.105000 1.460000 5.360000 1.850000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__a21o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.850000 0.995000 1.265000 1.325000 ; - RECT 1.035000 0.375000 1.265000 0.995000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.445000 0.995000 1.740000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.675000 0.335000 1.325000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.447000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 1.495000 0.680000 1.685000 ; - RECT 0.095000 1.685000 0.370000 2.455000 ; - RECT 0.505000 0.645000 0.835000 0.825000 ; - RECT 0.505000 0.825000 0.680000 1.495000 ; - RECT 0.610000 0.265000 0.835000 0.645000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.110000 0.085000 0.440000 0.475000 ; - RECT 0.540000 1.855000 1.745000 2.025000 ; - RECT 0.540000 2.025000 0.870000 2.455000 ; - RECT 0.850000 1.525000 1.745000 1.855000 ; - RECT 1.040000 2.195000 1.235000 2.635000 ; - RECT 1.415000 2.025000 1.745000 2.455000 ; - RECT 1.445000 0.085000 1.745000 0.815000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__a21oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.815000 0.995000 1.425000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 1.035000 0.645000 1.495000 ; - RECT 0.145000 1.495000 1.930000 1.675000 ; - RECT 1.605000 1.075000 1.935000 1.245000 ; - RECT 1.605000 1.245000 1.930000 1.495000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.800000 0.995000 3.075000 1.625000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.627500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.955000 0.255000 1.300000 0.615000 ; - RECT 0.955000 0.615000 2.615000 0.785000 ; - RECT 2.295000 0.255000 2.615000 0.615000 ; - RECT 2.315000 0.785000 2.615000 2.115000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.100000 0.085000 0.395000 0.865000 ; - RECT 0.110000 1.855000 2.145000 2.025000 ; - RECT 0.110000 2.025000 1.220000 2.105000 ; - RECT 0.110000 2.105000 0.370000 2.465000 ; - RECT 0.540000 2.275000 0.870000 2.635000 ; - RECT 1.050000 2.105000 1.220000 2.465000 ; - RECT 1.475000 2.195000 1.645000 2.635000 ; - RECT 1.760000 0.085000 2.090000 0.445000 ; - RECT 1.815000 2.025000 2.145000 2.285000 ; - RECT 1.815000 2.285000 3.090000 2.465000 ; - RECT 2.785000 1.795000 3.090000 2.285000 ; - RECT 2.795000 0.085000 3.125000 0.825000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a21oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a21oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a21oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.565000 1.065000 4.000000 1.310000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.050000 1.065000 2.395000 1.480000 ; - RECT 2.050000 1.480000 5.470000 1.705000 ; - RECT 4.225000 1.075000 5.470000 1.480000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.995000 0.400000 1.035000 ; - RECT 0.090000 1.035000 1.430000 1.415000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.288000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.580000 1.585000 1.880000 1.705000 ; - RECT 0.580000 1.705000 1.745000 2.035000 ; - RECT 0.595000 0.370000 0.785000 0.615000 ; - RECT 0.595000 0.615000 1.645000 0.695000 ; - RECT 0.595000 0.695000 3.905000 0.865000 ; - RECT 1.455000 0.255000 1.645000 0.615000 ; - RECT 1.600000 0.865000 3.905000 0.895000 ; - RECT 1.600000 0.895000 1.880000 1.585000 ; - RECT 2.275000 0.675000 3.905000 0.695000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.805000 ; - RECT 0.180000 1.795000 0.375000 2.215000 ; - RECT 0.180000 2.215000 2.115000 2.465000 ; - RECT 0.955000 0.085000 1.285000 0.445000 ; - RECT 0.955000 2.205000 2.115000 2.215000 ; - RECT 1.835000 0.085000 2.115000 0.525000 ; - RECT 1.915000 1.875000 5.625000 2.105000 ; - RECT 1.915000 2.105000 2.115000 2.205000 ; - RECT 2.285000 0.255000 4.335000 0.505000 ; - RECT 2.285000 2.275000 2.615000 2.635000 ; - RECT 2.785000 2.105000 2.975000 2.465000 ; - RECT 3.145000 2.275000 3.475000 2.635000 ; - RECT 3.645000 2.105000 3.835000 2.465000 ; - RECT 4.005000 2.275000 4.335000 2.635000 ; - RECT 4.075000 0.505000 4.335000 0.735000 ; - RECT 4.075000 0.735000 5.195000 0.905000 ; - RECT 4.505000 0.085000 4.695000 0.565000 ; - RECT 4.505000 2.105000 4.685000 2.465000 ; - RECT 4.865000 0.255000 5.195000 0.735000 ; - RECT 4.865000 2.275000 5.195000 2.635000 ; - RECT 5.365000 0.085000 5.625000 0.885000 ; - RECT 5.365000 2.105000 5.625000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__a21oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.485000 0.675000 1.695000 1.075000 ; - RECT 1.485000 1.075000 1.815000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 1.040000 2.395000 1.345000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.765000 1.075000 1.240000 1.285000 ; - RECT 1.020000 0.675000 1.240000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.575000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.875000 0.255000 3.135000 0.585000 ; - RECT 2.875000 1.785000 3.135000 2.465000 ; - RECT 2.965000 0.585000 3.135000 1.785000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 0.085000 0.545000 0.850000 ; - RECT 0.090000 1.455000 1.265000 1.515000 ; - RECT 0.090000 1.515000 2.795000 1.625000 ; - RECT 0.090000 1.625000 0.345000 2.245000 ; - RECT 0.090000 2.245000 0.425000 2.465000 ; - RECT 0.595000 1.795000 0.780000 1.885000 ; - RECT 0.595000 1.885000 2.205000 2.085000 ; - RECT 0.595000 2.085000 0.825000 2.125000 ; - RECT 0.820000 0.255000 2.120000 0.465000 ; - RECT 0.935000 1.625000 2.735000 1.685000 ; - RECT 0.935000 1.685000 1.265000 1.715000 ; - RECT 1.370000 1.875000 2.205000 1.885000 ; - RECT 1.430000 2.255000 1.785000 2.635000 ; - RECT 1.950000 0.465000 2.120000 0.615000 ; - RECT 1.950000 0.615000 2.705000 0.740000 ; - RECT 1.950000 0.740000 2.795000 0.785000 ; - RECT 1.955000 2.085000 2.205000 2.465000 ; - RECT 2.375000 0.085000 2.705000 0.445000 ; - RECT 2.455000 1.855000 2.705000 2.635000 ; - RECT 2.525000 0.785000 2.795000 0.905000 ; - RECT 2.595000 1.480000 2.795000 1.515000 ; - RECT 2.625000 0.905000 2.795000 1.480000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a22o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.510000 0.675000 1.720000 1.075000 ; - RECT 1.510000 1.075000 1.840000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.010000 1.075000 2.415000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.765000 1.075000 1.240000 1.285000 ; - RECT 1.020000 0.675000 1.240000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.575000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.900000 0.255000 3.160000 0.585000 ; - RECT 2.900000 1.785000 3.160000 2.465000 ; - RECT 2.990000 0.585000 3.160000 1.785000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.095000 0.085000 0.545000 0.850000 ; - RECT 0.095000 1.455000 2.815000 1.625000 ; - RECT 0.095000 1.625000 0.425000 2.295000 ; - RECT 0.095000 2.295000 1.265000 2.465000 ; - RECT 0.595000 1.795000 2.230000 2.035000 ; - RECT 0.595000 2.035000 0.825000 2.125000 ; - RECT 0.820000 0.255000 2.145000 0.505000 ; - RECT 0.935000 2.255000 1.265000 2.295000 ; - RECT 1.455000 2.215000 1.810000 2.635000 ; - RECT 1.975000 0.505000 2.145000 0.735000 ; - RECT 1.975000 0.735000 2.815000 0.905000 ; - RECT 1.980000 2.035000 2.230000 2.465000 ; - RECT 2.355000 0.085000 2.685000 0.565000 ; - RECT 2.400000 1.875000 2.730000 2.635000 ; - RECT 2.645000 0.905000 2.815000 1.455000 ; - RECT 3.330000 0.085000 3.500000 0.985000 ; - RECT 3.330000 1.445000 3.500000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a22o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.900000 1.075000 5.395000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.350000 1.075000 4.680000 1.445000 ; - RECT 4.350000 1.445000 5.735000 1.615000 ; - RECT 5.565000 1.075000 6.355000 1.275000 ; - RECT 5.565000 1.275000 5.735000 1.445000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.125000 1.075000 3.680000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.420000 1.075000 2.955000 1.445000 ; - RECT 2.420000 1.445000 4.180000 1.615000 ; - RECT 3.850000 1.075000 4.180000 1.445000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.725000 1.770000 0.905000 ; - RECT 0.085000 0.905000 0.370000 1.445000 ; - RECT 0.085000 1.445000 1.730000 1.615000 ; - RECT 0.600000 0.265000 0.930000 0.725000 ; - RECT 0.640000 1.615000 0.890000 2.465000 ; - RECT 1.440000 0.255000 1.770000 0.725000 ; - RECT 1.480000 1.615000 1.730000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.220000 1.825000 0.470000 2.635000 ; - RECT 0.260000 0.085000 0.430000 0.555000 ; - RECT 0.540000 1.075000 2.230000 1.275000 ; - RECT 1.060000 1.795000 1.310000 2.635000 ; - RECT 1.100000 0.085000 1.270000 0.555000 ; - RECT 1.900000 1.275000 2.230000 1.785000 ; - RECT 1.900000 1.785000 3.930000 1.955000 ; - RECT 1.900000 2.125000 2.150000 2.635000 ; - RECT 1.940000 0.085000 2.630000 0.555000 ; - RECT 1.940000 0.735000 5.310000 0.905000 ; - RECT 1.940000 0.905000 2.230000 1.075000 ; - RECT 2.420000 2.125000 2.670000 2.295000 ; - RECT 2.420000 2.295000 4.430000 2.465000 ; - RECT 2.800000 0.255000 3.970000 0.475000 ; - RECT 2.840000 1.955000 3.090000 2.125000 ; - RECT 3.170000 0.645000 3.605000 0.735000 ; - RECT 3.260000 2.125000 3.510000 2.295000 ; - RECT 3.680000 1.955000 3.930000 2.125000 ; - RECT 4.100000 1.785000 6.110000 1.955000 ; - RECT 4.100000 1.955000 4.430000 2.295000 ; - RECT 4.185000 0.085000 4.355000 0.555000 ; - RECT 4.560000 0.255000 5.730000 0.475000 ; - RECT 4.600000 2.125000 4.850000 2.635000 ; - RECT 4.935000 0.645000 5.310000 0.735000 ; - RECT 5.020000 1.955000 5.270000 2.465000 ; - RECT 5.440000 2.125000 5.690000 2.635000 ; - RECT 5.480000 0.475000 5.730000 0.895000 ; - RECT 5.900000 0.085000 6.070000 0.895000 ; - RECT 5.905000 1.455000 6.110000 1.785000 ; - RECT 5.905000 1.955000 6.110000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__a22o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.490000 0.675000 1.700000 1.075000 ; - RECT 1.490000 1.075000 1.840000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.010000 0.995000 2.335000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.765000 1.075000 1.240000 1.275000 ; - RECT 0.990000 0.675000 1.240000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 0.765000 0.575000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.858000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 1.445000 1.840000 1.495000 ; - RECT 0.095000 1.495000 2.675000 1.625000 ; - RECT 0.095000 1.625000 0.425000 2.295000 ; - RECT 0.095000 2.295000 1.265000 2.465000 ; - RECT 0.820000 0.255000 2.125000 0.505000 ; - RECT 0.935000 2.255000 1.265000 2.295000 ; - RECT 1.615000 1.625000 2.675000 1.665000 ; - RECT 1.945000 0.505000 2.125000 0.655000 ; - RECT 1.945000 0.655000 2.675000 0.825000 ; - RECT 2.505000 0.825000 2.675000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 0.085000 0.545000 0.595000 ; - RECT 0.595000 1.795000 1.475000 1.835000 ; - RECT 0.595000 1.835000 2.125000 2.035000 ; - RECT 0.595000 2.035000 1.210000 2.085000 ; - RECT 0.595000 2.085000 0.825000 2.125000 ; - RECT 1.435000 2.255000 1.810000 2.635000 ; - RECT 1.955000 2.035000 2.125000 2.165000 ; - RECT 2.305000 0.085000 2.635000 0.485000 ; - RECT 2.360000 1.855000 2.625000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__a22oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 1.075000 3.100000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.390000 1.075000 4.500000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.075000 1.700000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 1.075000 0.780000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.141000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 1.485000 2.160000 1.655000 ; - RECT 0.095000 1.655000 0.345000 2.465000 ; - RECT 0.935000 1.655000 1.265000 2.125000 ; - RECT 1.355000 0.675000 3.045000 0.845000 ; - RECT 1.775000 1.655000 2.160000 2.125000 ; - RECT 1.870000 0.845000 2.160000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.095000 0.255000 0.345000 0.680000 ; - RECT 0.095000 0.680000 1.185000 0.850000 ; - RECT 0.515000 0.085000 0.845000 0.510000 ; - RECT 0.515000 1.825000 0.765000 2.295000 ; - RECT 0.515000 2.295000 2.625000 2.465000 ; - RECT 1.015000 0.255000 2.105000 0.505000 ; - RECT 1.015000 0.505000 1.185000 0.680000 ; - RECT 1.435000 1.825000 1.605000 2.295000 ; - RECT 2.295000 0.255000 3.385000 0.505000 ; - RECT 2.375000 1.485000 4.305000 1.655000 ; - RECT 2.375000 1.655000 2.625000 2.295000 ; - RECT 2.795000 1.825000 2.965000 2.635000 ; - RECT 3.135000 1.655000 3.465000 2.465000 ; - RECT 3.215000 0.505000 3.385000 0.680000 ; - RECT 3.215000 0.680000 4.375000 0.850000 ; - RECT 3.555000 0.085000 3.885000 0.510000 ; - RECT 3.635000 1.825000 3.805000 2.635000 ; - RECT 3.975000 1.655000 4.305000 2.465000 ; - RECT 4.055000 0.255000 4.375000 0.680000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__a22oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a22oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a22oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.275000 1.075000 5.685000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.910000 1.075000 7.735000 1.285000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.615000 1.075000 4.040000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 1.895000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 1.445000 3.325000 1.625000 ; - RECT 0.595000 1.625000 0.805000 2.125000 ; - RECT 1.395000 1.625000 1.645000 2.125000 ; - RECT 2.195000 0.645000 5.565000 0.885000 ; - RECT 2.195000 0.885000 2.445000 1.445000 ; - RECT 2.235000 1.625000 2.485000 2.125000 ; - RECT 3.075000 1.625000 3.325000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.090000 1.455000 0.425000 2.295000 ; - RECT 0.090000 2.295000 4.265000 2.465000 ; - RECT 0.095000 0.255000 0.425000 0.725000 ; - RECT 0.095000 0.725000 2.025000 0.905000 ; - RECT 0.595000 0.085000 0.765000 0.555000 ; - RECT 0.935000 0.255000 1.265000 0.725000 ; - RECT 0.975000 1.795000 1.225000 2.295000 ; - RECT 1.435000 0.085000 1.605000 0.555000 ; - RECT 1.775000 0.255000 3.785000 0.475000 ; - RECT 1.775000 0.475000 2.025000 0.725000 ; - RECT 1.815000 1.795000 2.065000 2.295000 ; - RECT 2.655000 1.795000 2.905000 2.295000 ; - RECT 3.495000 1.455000 7.625000 1.625000 ; - RECT 3.495000 1.625000 4.265000 2.295000 ; - RECT 3.975000 0.255000 5.985000 0.475000 ; - RECT 4.435000 1.795000 4.685000 2.635000 ; - RECT 4.855000 1.625000 5.105000 2.465000 ; - RECT 5.275000 1.795000 5.525000 2.635000 ; - RECT 5.695000 1.625000 5.945000 2.465000 ; - RECT 5.735000 0.475000 5.985000 0.725000 ; - RECT 5.735000 0.725000 7.665000 0.905000 ; - RECT 6.115000 1.795000 6.365000 2.635000 ; - RECT 6.155000 0.085000 6.325000 0.555000 ; - RECT 6.495000 0.255000 6.825000 0.725000 ; - RECT 6.535000 1.625000 6.785000 2.465000 ; - RECT 6.955000 1.795000 7.205000 2.635000 ; - RECT 6.995000 0.085000 7.165000 0.555000 ; - RECT 7.335000 0.255000 7.665000 0.725000 ; - RECT 7.375000 1.625000 7.625000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__a22oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.895000 0.995000 2.160000 1.655000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 0.995000 1.700000 1.655000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.935000 0.995000 1.240000 1.325000 ; - RECT 1.025000 1.325000 1.240000 1.655000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.375000 0.995000 2.620000 1.655000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.437250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.300000 0.425000 0.810000 ; - RECT 0.095000 0.810000 0.285000 1.575000 ; - RECT 0.095000 1.575000 0.425000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.455000 0.995000 0.765000 1.325000 ; - RECT 0.595000 0.085000 0.925000 0.485000 ; - RECT 0.595000 0.655000 2.960000 0.825000 ; - RECT 0.595000 0.825000 0.765000 0.995000 ; - RECT 0.595000 1.495000 0.845000 2.635000 ; - RECT 1.035000 1.825000 2.325000 1.995000 ; - RECT 1.035000 1.995000 1.285000 2.415000 ; - RECT 1.515000 2.165000 1.845000 2.635000 ; - RECT 1.975000 0.315000 2.305000 0.655000 ; - RECT 2.075000 1.995000 2.325000 2.415000 ; - RECT 2.475000 0.085000 2.805000 0.485000 ; - RECT 2.505000 1.825000 2.960000 1.995000 ; - RECT 2.505000 1.995000 2.835000 2.425000 ; - RECT 2.790000 0.825000 2.960000 1.825000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a31o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.965000 0.415000 2.175000 0.700000 ; - RECT 1.965000 0.700000 2.355000 0.870000 ; - RECT 2.185000 0.870000 2.355000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 0.400000 1.700000 0.695000 ; - RECT 1.530000 0.695000 1.795000 0.865000 ; - RECT 1.625000 0.865000 1.795000 1.075000 ; - RECT 1.625000 1.075000 1.955000 1.245000 ; - RECT 1.625000 1.245000 1.795000 1.260000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 0.760000 1.270000 0.995000 ; - RECT 1.065000 0.995000 1.395000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.895000 0.755000 3.090000 1.325000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.715000 0.765000 0.885000 ; - RECT 0.090000 0.885000 0.345000 1.835000 ; - RECT 0.090000 1.835000 0.765000 2.005000 ; - RECT 0.595000 0.255000 0.765000 0.715000 ; - RECT 0.595000 2.005000 0.765000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 0.085000 0.345000 0.545000 ; - RECT 0.135000 2.175000 0.385000 2.635000 ; - RECT 0.555000 1.075000 0.885000 1.245000 ; - RECT 0.555000 1.245000 0.725000 1.495000 ; - RECT 0.555000 1.495000 3.045000 1.665000 ; - RECT 0.935000 1.835000 1.185000 2.635000 ; - RECT 0.955000 0.085000 1.285000 0.465000 ; - RECT 1.015000 0.465000 1.185000 0.545000 ; - RECT 1.355000 1.835000 2.645000 2.005000 ; - RECT 1.355000 2.005000 1.605000 2.425000 ; - RECT 1.815000 2.175000 2.145000 2.635000 ; - RECT 2.335000 2.005000 2.585000 2.425000 ; - RECT 2.375000 0.335000 2.705000 0.505000 ; - RECT 2.460000 0.255000 2.705000 0.335000 ; - RECT 2.535000 0.505000 2.705000 1.495000 ; - RECT 2.875000 0.085000 3.135000 0.565000 ; - RECT 2.875000 1.665000 3.045000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a31o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.075000 1.705000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.725000 1.075000 1.055000 1.245000 ; - RECT 0.805000 0.735000 2.170000 0.905000 ; - RECT 0.805000 0.905000 0.975000 1.075000 ; - RECT 1.985000 0.905000 2.170000 1.075000 ; - RECT 1.985000 1.075000 2.315000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 1.075000 0.525000 1.445000 ; - RECT 0.150000 1.445000 2.855000 1.615000 ; - RECT 2.525000 1.075000 2.855000 1.445000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.575000 1.075000 4.030000 1.285000 ; - RECT 3.815000 0.745000 4.030000 1.075000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.505000 0.655000 6.295000 0.825000 ; - RECT 4.535000 1.785000 6.295000 1.955000 ; - RECT 4.595000 1.955000 4.765000 2.465000 ; - RECT 5.435000 1.955000 5.605000 2.465000 ; - RECT 6.125000 0.825000 6.295000 1.785000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.175000 0.085000 0.345000 0.905000 ; - RECT 0.175000 1.785000 2.985000 1.955000 ; - RECT 0.175000 1.955000 0.345000 2.465000 ; - RECT 0.515000 2.125000 0.845000 2.635000 ; - RECT 1.015000 1.955000 1.185000 2.465000 ; - RECT 1.355000 0.395000 2.520000 0.565000 ; - RECT 1.355000 2.125000 1.685000 2.635000 ; - RECT 1.855000 1.955000 2.025000 2.465000 ; - RECT 2.195000 2.125000 2.525000 2.635000 ; - RECT 2.350000 0.565000 2.520000 0.700000 ; - RECT 2.350000 0.700000 3.485000 0.805000 ; - RECT 2.350000 0.805000 3.345000 0.870000 ; - RECT 2.700000 0.085000 2.985000 0.530000 ; - RECT 2.815000 1.955000 2.985000 2.295000 ; - RECT 2.815000 2.295000 3.825000 2.465000 ; - RECT 3.155000 0.295000 3.485000 0.700000 ; - RECT 3.155000 0.870000 3.345000 1.455000 ; - RECT 3.155000 1.455000 4.395000 1.625000 ; - RECT 3.155000 1.625000 3.485000 2.115000 ; - RECT 3.655000 1.795000 3.825000 2.295000 ; - RECT 3.735000 0.085000 4.265000 0.565000 ; - RECT 4.095000 2.125000 4.425000 2.635000 ; - RECT 4.225000 0.995000 5.935000 1.325000 ; - RECT 4.225000 1.325000 4.395000 1.455000 ; - RECT 4.935000 0.085000 5.265000 0.485000 ; - RECT 4.935000 2.125000 5.265000 2.635000 ; - RECT 5.775000 0.085000 6.105000 0.485000 ; - RECT 5.775000 2.125000 6.105000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__a31o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.445000 1.455000 1.665000 ; - RECT 1.270000 0.995000 1.455000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 0.335000 1.055000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.365000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.965000 0.995000 2.215000 1.325000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.481250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.380000 0.295000 1.785000 0.715000 ; - RECT 1.380000 0.715000 1.795000 0.825000 ; - RECT 1.625000 0.825000 1.795000 1.495000 ; - RECT 1.625000 1.495000 2.210000 1.665000 ; - RECT 1.875000 1.665000 2.210000 2.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.090000 0.085000 0.430000 0.815000 ; - RECT 0.090000 1.495000 0.420000 2.635000 ; - RECT 0.590000 1.835000 1.695000 2.005000 ; - RECT 0.590000 2.005000 0.765000 2.415000 ; - RECT 0.935000 2.175000 1.265000 2.635000 ; - RECT 1.470000 2.005000 1.695000 2.415000 ; - RECT 1.955000 0.085000 2.215000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__a31oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.955000 0.995000 2.665000 1.615000 ; - RECT 2.905000 0.995000 3.075000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.050000 0.995000 1.755000 1.615000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.995000 0.820000 1.615000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.820000 1.075000 4.490000 1.275000 ; - RECT 4.265000 1.275000 4.490000 1.625000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.922000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.295000 0.655000 4.505000 0.825000 ; - RECT 3.255000 0.255000 3.425000 0.655000 ; - RECT 3.255000 0.825000 3.570000 1.445000 ; - RECT 3.255000 1.445000 4.085000 1.615000 ; - RECT 3.755000 1.615000 4.085000 2.115000 ; - RECT 4.175000 0.295000 4.505000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.095000 0.655000 2.105000 0.825000 ; - RECT 0.175000 1.785000 3.505000 1.955000 ; - RECT 0.175000 1.955000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.125000 0.845000 2.635000 ; - RECT 1.015000 1.955000 1.185000 2.465000 ; - RECT 1.355000 0.295000 3.075000 0.465000 ; - RECT 1.355000 2.125000 1.685000 2.635000 ; - RECT 1.855000 1.955000 2.025000 2.465000 ; - RECT 2.310000 2.125000 2.980000 2.635000 ; - RECT 3.335000 1.955000 3.505000 2.295000 ; - RECT 3.335000 2.295000 4.425000 2.465000 ; - RECT 3.675000 0.085000 4.005000 0.465000 ; - RECT 4.255000 1.795000 4.425000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__a31oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a31oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a31oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 0.995000 5.420000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.995000 3.550000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.995000 1.735000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.670000 0.995000 6.855000 1.630000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.443500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.975000 0.635000 7.585000 0.805000 ; - RECT 6.075000 1.915000 7.245000 2.085000 ; - RECT 6.575000 0.255000 6.745000 0.635000 ; - RECT 7.045000 0.805000 7.245000 1.915000 ; - RECT 7.415000 0.255000 7.585000 0.635000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 3.785000 0.805000 ; - RECT 0.175000 1.495000 5.405000 1.665000 ; - RECT 0.175000 1.665000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 1.915000 0.845000 2.635000 ; - RECT 1.015000 0.255000 1.185000 0.635000 ; - RECT 1.015000 1.665000 1.185000 2.465000 ; - RECT 1.355000 0.085000 1.685000 0.465000 ; - RECT 1.355000 1.915000 1.685000 2.635000 ; - RECT 1.855000 0.255000 2.025000 0.635000 ; - RECT 1.855000 1.665000 2.025000 2.465000 ; - RECT 2.195000 0.295000 5.565000 0.465000 ; - RECT 2.195000 1.915000 2.525000 2.635000 ; - RECT 2.695000 1.665000 2.865000 2.465000 ; - RECT 3.035000 1.915000 3.365000 2.635000 ; - RECT 3.535000 1.665000 3.705000 2.465000 ; - RECT 3.895000 1.915000 4.225000 2.635000 ; - RECT 4.395000 1.665000 4.565000 2.465000 ; - RECT 4.735000 2.255000 5.065000 2.635000 ; - RECT 5.235000 1.665000 5.405000 2.255000 ; - RECT 5.235000 2.255000 7.665000 2.425000 ; - RECT 5.235000 2.425000 5.405000 2.465000 ; - RECT 6.075000 0.085000 6.405000 0.465000 ; - RECT 6.915000 0.085000 7.245000 0.465000 ; - RECT 7.415000 1.495000 7.665000 2.255000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__a31oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 0.665000 2.280000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 0.665000 1.800000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 0.995000 1.320000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.450000 0.660000 2.870000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.180000 0.995000 3.530000 1.325000 ; - RECT 3.325000 1.325000 3.530000 1.615000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.544500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.300000 0.425000 0.560000 ; - RECT 0.090000 0.560000 0.345000 1.915000 ; - RECT 0.090000 1.915000 0.425000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.570000 0.995000 0.875000 1.325000 ; - RECT 0.595000 0.085000 0.925000 0.485000 ; - RECT 0.675000 1.835000 1.005000 2.635000 ; - RECT 0.705000 0.655000 1.265000 0.825000 ; - RECT 0.705000 0.825000 0.875000 0.995000 ; - RECT 0.705000 1.325000 0.875000 1.495000 ; - RECT 0.705000 1.495000 3.075000 1.665000 ; - RECT 1.095000 0.315000 2.710000 0.485000 ; - RECT 1.095000 0.485000 1.265000 0.655000 ; - RECT 1.250000 1.875000 2.675000 2.045000 ; - RECT 1.250000 2.045000 1.535000 2.465000 ; - RECT 1.790000 2.215000 2.120000 2.635000 ; - RECT 2.345000 2.045000 2.675000 2.295000 ; - RECT 2.345000 2.295000 3.505000 2.465000 ; - RECT 2.905000 1.665000 3.075000 2.125000 ; - RECT 3.255000 0.085000 3.585000 0.805000 ; - RECT 3.335000 1.795000 3.505000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a32o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.685000 0.955000 2.985000 1.325000 ; - RECT 2.755000 0.415000 3.105000 0.610000 ; - RECT 2.755000 0.610000 2.985000 0.955000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.165000 0.995000 3.545000 1.325000 ; - RECT 3.305000 0.425000 3.545000 0.995000 ; - RECT 3.305000 1.325000 3.545000 1.625000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.815000 0.995000 4.055000 1.630000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.085000 1.075000 2.515000 1.245000 ; - RECT 2.345000 1.245000 2.515000 1.445000 ; - RECT 2.345000 1.445000 2.550000 1.615000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.115000 0.745000 1.530000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.695500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 0.655000 0.845000 0.825000 ; - RECT 0.135000 0.825000 0.345000 1.785000 ; - RECT 0.135000 1.785000 1.185000 1.955000 ; - RECT 0.135000 1.955000 0.345000 2.465000 ; - RECT 1.015000 1.955000 1.185000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.465000 ; - RECT 0.515000 2.125000 0.845000 2.635000 ; - RECT 0.535000 0.995000 0.705000 1.445000 ; - RECT 0.535000 1.445000 2.125000 1.615000 ; - RECT 0.935000 0.085000 1.640000 0.445000 ; - RECT 1.535000 1.785000 1.705000 2.295000 ; - RECT 1.535000 2.295000 2.545000 2.465000 ; - RECT 1.700000 0.615000 2.585000 0.785000 ; - RECT 1.700000 0.785000 1.890000 1.445000 ; - RECT 1.875000 1.615000 2.125000 1.945000 ; - RECT 1.875000 1.945000 2.205000 2.115000 ; - RECT 2.255000 0.275000 2.585000 0.615000 ; - RECT 2.375000 1.795000 3.545000 1.965000 ; - RECT 2.375000 1.965000 2.545000 2.295000 ; - RECT 2.715000 2.140000 3.045000 2.635000 ; - RECT 3.375000 1.965000 3.545000 2.465000 ; - RECT 3.715000 0.085000 4.050000 0.805000 ; - RECT 3.715000 1.915000 4.050000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a32o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.280000 1.075000 5.075000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.335000 1.075000 4.030000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.210000 1.075000 3.105000 1.295000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.630000 1.075000 6.780000 1.625000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.030000 1.075000 7.710000 1.295000 ; - RECT 7.030000 1.295000 7.225000 1.635000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.635000 1.605000 0.805000 ; - RECT 0.120000 0.805000 0.340000 1.495000 ; - RECT 0.120000 1.495000 1.605000 1.665000 ; - RECT 0.595000 0.255000 0.765000 0.635000 ; - RECT 0.595000 1.665000 0.765000 2.465000 ; - RECT 1.435000 0.255000 1.605000 0.635000 ; - RECT 1.435000 1.665000 1.605000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 0.095000 1.915000 0.425000 2.635000 ; - RECT 0.570000 0.995000 1.970000 1.325000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 0.935000 1.915000 1.265000 2.635000 ; - RECT 1.775000 0.085000 2.105000 0.465000 ; - RECT 1.775000 1.915000 2.105000 2.635000 ; - RECT 1.800000 1.325000 1.970000 1.495000 ; - RECT 1.800000 1.495000 5.450000 1.665000 ; - RECT 2.275000 0.255000 2.445000 0.655000 ; - RECT 2.275000 0.655000 3.885000 0.825000 ; - RECT 2.275000 1.915000 5.065000 2.085000 ; - RECT 2.275000 2.085000 2.445000 2.465000 ; - RECT 2.615000 0.085000 2.945000 0.465000 ; - RECT 2.615000 2.255000 2.945000 2.635000 ; - RECT 3.135000 0.295000 5.145000 0.465000 ; - RECT 3.215000 2.085000 3.385000 2.465000 ; - RECT 3.555000 2.255000 3.885000 2.635000 ; - RECT 4.055000 2.085000 4.225000 2.465000 ; - RECT 4.395000 0.635000 6.425000 0.805000 ; - RECT 4.395000 2.255000 4.725000 2.635000 ; - RECT 4.895000 2.085000 5.065000 2.255000 ; - RECT 4.895000 2.255000 7.725000 2.425000 ; - RECT 5.280000 0.805000 5.450000 1.495000 ; - RECT 5.280000 1.665000 5.450000 1.905000 ; - RECT 5.280000 1.905000 6.200000 1.915000 ; - RECT 5.280000 1.915000 7.305000 2.075000 ; - RECT 5.670000 0.295000 6.805000 0.465000 ; - RECT 6.135000 2.075000 7.305000 2.085000 ; - RECT 6.635000 0.255000 6.805000 0.295000 ; - RECT 6.635000 0.465000 6.805000 0.645000 ; - RECT 6.635000 0.645000 7.645000 0.815000 ; - RECT 6.975000 0.085000 7.305000 0.465000 ; - RECT 7.475000 0.255000 7.645000 0.645000 ; - RECT 7.475000 1.755000 7.725000 2.255000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__a32o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.230000 1.075000 1.595000 1.255000 ; - RECT 1.405000 0.345000 1.705000 0.765000 ; - RECT 1.405000 0.765000 1.595000 1.075000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.805000 0.995000 2.165000 1.325000 ; - RECT 1.965000 0.415000 2.165000 0.995000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.335000 1.015000 2.750000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.855000 0.995000 1.025000 1.425000 ; - RECT 0.855000 1.425000 1.255000 1.615000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.345000 1.325000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.575500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.635000 1.165000 0.805000 ; - RECT 0.515000 0.805000 0.685000 1.785000 ; - RECT 0.515000 1.785000 0.865000 2.085000 ; - RECT 0.915000 0.295000 1.165000 0.635000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.835000 0.345000 2.255000 ; - RECT 0.085000 2.255000 1.345000 2.465000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 1.095000 1.785000 2.185000 1.955000 ; - RECT 1.095000 1.955000 1.345000 2.255000 ; - RECT 1.555000 2.135000 1.805000 2.635000 ; - RECT 2.015000 1.745000 2.185000 1.785000 ; - RECT 2.015000 1.955000 2.185000 2.465000 ; - RECT 2.355000 0.085000 2.695000 0.805000 ; - RECT 2.355000 1.495000 2.695000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a32oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.415000 1.075000 3.220000 1.625000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.725000 1.075000 4.480000 1.625000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.715000 1.075000 5.860000 1.625000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.045000 1.080000 1.725000 1.285000 ; - RECT 1.175000 1.075000 1.505000 1.080000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 1.075000 0.825000 1.285000 ; - RECT 0.145000 1.285000 0.325000 1.625000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.955000 0.845000 2.125000 ; - RECT 0.595000 1.455000 2.180000 1.625000 ; - RECT 0.595000 1.625000 0.765000 1.955000 ; - RECT 1.355000 0.655000 3.100000 0.825000 ; - RECT 1.435000 1.625000 1.605000 2.125000 ; - RECT 1.965000 0.825000 2.180000 1.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.095000 0.295000 0.425000 0.465000 ; - RECT 0.175000 0.465000 0.345000 0.715000 ; - RECT 0.175000 0.715000 1.185000 0.885000 ; - RECT 0.175000 1.795000 0.345000 2.295000 ; - RECT 0.175000 2.295000 2.025000 2.465000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.935000 0.295000 2.115000 0.465000 ; - RECT 1.015000 0.465000 1.185000 0.715000 ; - RECT 1.015000 1.795000 1.185000 2.295000 ; - RECT 1.855000 1.795000 2.025000 1.915000 ; - RECT 1.855000 1.915000 5.805000 2.085000 ; - RECT 1.855000 2.085000 2.025000 2.295000 ; - RECT 2.270000 2.255000 2.940000 2.635000 ; - RECT 2.350000 0.295000 4.370000 0.465000 ; - RECT 3.180000 1.795000 3.350000 1.915000 ; - RECT 3.180000 2.085000 3.350000 2.465000 ; - RECT 3.550000 2.255000 4.220000 2.635000 ; - RECT 3.620000 0.635000 5.390000 0.805000 ; - RECT 4.390000 1.795000 4.560000 1.915000 ; - RECT 4.390000 2.085000 4.560000 2.465000 ; - RECT 4.555000 0.085000 4.890000 0.465000 ; - RECT 4.765000 2.255000 5.435000 2.635000 ; - RECT 5.060000 0.275000 5.390000 0.635000 ; - RECT 5.560000 0.085000 5.885000 0.885000 ; - RECT 5.635000 1.795000 5.805000 1.915000 ; - RECT 5.635000 2.085000 5.805000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__a32oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a32oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a32oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.775000 1.075000 5.465000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.095000 1.075000 7.695000 1.300000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.295000 1.075000 9.985000 1.280000 ; - RECT 9.805000 0.755000 9.985000 1.075000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.585000 0.995000 3.555000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 1.750000 1.305000 ; - RECT 0.110000 1.305000 0.330000 1.965000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.575000 3.365000 1.745000 ; - RECT 0.515000 1.745000 0.845000 2.085000 ; - RECT 1.355000 1.745000 1.685000 2.085000 ; - RECT 1.975000 0.990000 2.365000 1.575000 ; - RECT 1.975000 1.745000 2.525000 2.085000 ; - RECT 2.195000 0.635000 5.565000 0.805000 ; - RECT 2.195000 0.805000 2.365000 0.990000 ; - RECT 3.035000 1.745000 3.365000 2.085000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.095000 2.255000 3.705000 2.425000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 2.025000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 1.015000 0.255000 1.185000 0.635000 ; - RECT 1.355000 0.085000 1.685000 0.465000 ; - RECT 1.855000 0.295000 3.785000 0.465000 ; - RECT 1.855000 0.465000 2.025000 0.635000 ; - RECT 3.535000 1.575000 9.925000 1.745000 ; - RECT 3.535000 1.745000 3.705000 2.255000 ; - RECT 3.895000 1.915000 4.225000 2.635000 ; - RECT 3.975000 0.295000 7.805000 0.465000 ; - RECT 4.395000 1.745000 4.565000 2.465000 ; - RECT 4.770000 1.915000 5.440000 2.635000 ; - RECT 5.640000 1.745000 5.810000 2.465000 ; - RECT 6.215000 0.635000 9.505000 0.805000 ; - RECT 6.215000 1.915000 6.545000 2.635000 ; - RECT 6.715000 1.745000 6.885000 2.465000 ; - RECT 7.055000 1.915000 7.385000 2.635000 ; - RECT 7.555000 1.745000 7.725000 2.465000 ; - RECT 7.995000 0.085000 8.325000 0.465000 ; - RECT 8.415000 1.915000 8.745000 2.635000 ; - RECT 8.495000 0.255000 8.665000 0.635000 ; - RECT 8.835000 0.085000 9.165000 0.465000 ; - RECT 8.915000 1.745000 9.085000 2.465000 ; - RECT 9.255000 1.915000 9.585000 2.635000 ; - RECT 9.335000 0.255000 9.505000 0.635000 ; - RECT 9.685000 0.085000 10.025000 0.465000 ; - RECT 9.755000 1.745000 9.925000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__a32oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.535000 0.995000 1.915000 1.325000 ; - RECT 1.535000 1.325000 1.835000 1.620000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.700000 0.415000 2.650000 0.600000 ; - RECT 2.225000 0.600000 2.445000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.705000 0.995000 3.085000 1.625000 ; - RECT 2.880000 0.395000 3.085000 0.995000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.315000 0.995000 3.570000 1.625000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.005000 1.075000 1.335000 1.635000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.300000 0.425000 0.560000 ; - RECT 0.085000 0.560000 0.345000 2.165000 ; - RECT 0.085000 2.165000 0.425000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.515000 0.735000 1.530000 0.810000 ; - RECT 0.515000 0.810000 1.335000 0.905000 ; - RECT 0.515000 0.905000 0.685000 1.825000 ; - RECT 0.515000 1.825000 1.365000 1.995000 ; - RECT 0.595000 0.085000 0.925000 0.565000 ; - RECT 0.595000 2.175000 0.845000 2.635000 ; - RECT 1.035000 1.995000 1.365000 2.425000 ; - RECT 1.115000 0.300000 1.530000 0.735000 ; - RECT 1.535000 1.795000 3.505000 1.965000 ; - RECT 1.535000 1.965000 1.705000 2.465000 ; - RECT 1.915000 2.175000 2.165000 2.635000 ; - RECT 2.375000 1.965000 2.545000 2.465000 ; - RECT 2.845000 2.175000 3.095000 2.635000 ; - RECT 3.255000 0.085000 3.595000 0.810000 ; - RECT 3.335000 1.965000 3.505000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a41o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.785000 0.730000 4.005000 1.625000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.085000 1.075000 3.550000 1.245000 ; - RECT 3.335000 0.745000 3.550000 1.075000 ; - RECT 3.335000 1.245000 3.550000 1.625000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.685000 0.995000 2.855000 1.435000 ; - RECT 2.685000 1.435000 3.090000 1.625000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.000000 0.995000 2.335000 1.625000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.400000 1.075000 1.730000 1.295000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.295000 0.765000 0.755000 ; - RECT 0.595000 0.755000 0.785000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.805000 ; - RECT 0.095000 1.495000 0.425000 2.635000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 0.980000 0.635000 2.545000 0.805000 ; - RECT 0.980000 0.805000 1.150000 1.495000 ; - RECT 0.980000 1.495000 1.785000 1.665000 ; - RECT 1.015000 1.835000 1.265000 2.635000 ; - RECT 1.455000 1.665000 1.785000 2.425000 ; - RECT 1.495000 0.255000 1.705000 0.635000 ; - RECT 1.875000 0.085000 2.205000 0.465000 ; - RECT 1.955000 1.795000 3.965000 1.965000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.335000 2.175000 2.585000 2.635000 ; - RECT 2.375000 0.295000 4.045000 0.465000 ; - RECT 2.375000 0.465000 2.545000 0.635000 ; - RECT 2.795000 1.965000 2.965000 2.465000 ; - RECT 3.335000 2.175000 3.585000 2.635000 ; - RECT 3.795000 1.965000 3.965000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a41o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.395000 1.075000 4.065000 1.295000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.275000 1.075000 4.975000 1.285000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.155000 1.075000 6.185000 1.295000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.495000 1.075000 7.505000 1.295000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.135000 1.075000 3.145000 1.280000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.635000 1.605000 0.805000 ; - RECT 0.150000 0.805000 0.320000 1.575000 ; - RECT 0.150000 1.575000 1.605000 1.745000 ; - RECT 0.595000 0.255000 0.765000 0.635000 ; - RECT 0.595000 1.745000 0.765000 2.465000 ; - RECT 1.435000 0.255000 1.605000 0.635000 ; - RECT 1.435000 1.745000 1.605000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 0.095000 1.915000 0.425000 2.635000 ; - RECT 0.490000 1.075000 1.945000 1.245000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 0.935000 1.915000 1.265000 2.635000 ; - RECT 1.775000 0.085000 2.125000 0.465000 ; - RECT 1.775000 0.645000 3.905000 0.815000 ; - RECT 1.775000 0.815000 1.945000 1.075000 ; - RECT 1.775000 1.245000 1.945000 1.455000 ; - RECT 1.775000 1.455000 2.965000 1.625000 ; - RECT 1.775000 1.915000 2.125000 2.635000 ; - RECT 2.295000 0.255000 2.465000 0.645000 ; - RECT 2.375000 1.795000 2.545000 2.295000 ; - RECT 2.375000 2.295000 3.405000 2.465000 ; - RECT 2.635000 0.085000 2.965000 0.465000 ; - RECT 2.715000 1.955000 3.045000 2.125000 ; - RECT 2.795000 1.625000 2.965000 1.955000 ; - RECT 3.155000 0.295000 4.245000 0.465000 ; - RECT 3.235000 1.535000 7.370000 1.705000 ; - RECT 3.235000 1.705000 3.405000 2.295000 ; - RECT 3.575000 1.915000 3.905000 2.635000 ; - RECT 4.075000 0.465000 4.245000 0.645000 ; - RECT 4.075000 0.645000 5.165000 0.815000 ; - RECT 4.075000 1.705000 4.245000 2.465000 ; - RECT 4.415000 0.295000 6.105000 0.465000 ; - RECT 4.415000 1.915000 4.745000 2.635000 ; - RECT 4.935000 1.705000 5.105000 2.465000 ; - RECT 5.345000 1.915000 6.035000 2.635000 ; - RECT 5.355000 0.645000 7.285000 0.815000 ; - RECT 6.275000 1.705000 6.445000 2.465000 ; - RECT 6.615000 0.085000 6.945000 0.465000 ; - RECT 6.615000 1.915000 6.945000 2.635000 ; - RECT 7.115000 0.255000 7.285000 0.645000 ; - RECT 7.115000 1.705000 7.285000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__a41o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.780000 0.995000 3.085000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.890000 0.755000 2.210000 1.665000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.470000 0.755000 1.710000 1.665000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.960000 0.965000 1.250000 1.665000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 0.965000 0.780000 1.665000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.669500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.285000 0.345000 0.615000 ; - RECT 0.090000 0.615000 1.290000 0.785000 ; - RECT 0.090000 0.785000 0.360000 1.845000 ; - RECT 0.090000 1.845000 0.425000 2.425000 ; - RECT 1.120000 0.295000 3.015000 0.465000 ; - RECT 1.120000 0.465000 1.290000 0.615000 ; - RECT 2.685000 0.465000 3.015000 0.805000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.595000 1.845000 3.015000 2.015000 ; - RECT 0.595000 2.015000 0.845000 2.465000 ; - RECT 0.620000 0.085000 0.950000 0.445000 ; - RECT 1.120000 2.195000 1.450000 2.635000 ; - RECT 1.760000 2.015000 1.930000 2.465000 ; - RECT 2.215000 2.195000 2.545000 2.635000 ; - RECT 2.765000 2.015000 3.015000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a41oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.785000 1.075000 2.455000 1.295000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.665000 1.075000 3.365000 1.285000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.545000 1.075000 4.575000 1.295000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.755000 1.075000 5.895000 1.295000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 1.075000 1.555000 1.280000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.621000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.645000 2.295000 0.815000 ; - RECT 0.145000 0.815000 0.315000 1.455000 ; - RECT 0.145000 1.455000 1.455000 1.625000 ; - RECT 0.685000 0.255000 0.855000 0.645000 ; - RECT 1.125000 1.625000 1.455000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.185000 0.085000 0.515000 0.465000 ; - RECT 0.785000 1.795000 0.955000 2.295000 ; - RECT 0.785000 2.295000 1.795000 2.465000 ; - RECT 1.025000 0.085000 1.375000 0.465000 ; - RECT 1.545000 0.295000 2.635000 0.465000 ; - RECT 1.625000 1.535000 5.760000 1.705000 ; - RECT 1.625000 1.705000 1.795000 2.295000 ; - RECT 1.965000 1.915000 2.295000 2.635000 ; - RECT 2.465000 0.465000 2.635000 0.645000 ; - RECT 2.465000 0.645000 3.555000 0.815000 ; - RECT 2.465000 1.705000 2.635000 2.465000 ; - RECT 2.805000 0.295000 4.495000 0.465000 ; - RECT 2.805000 1.915000 3.135000 2.635000 ; - RECT 3.325000 1.705000 3.495000 2.465000 ; - RECT 3.745000 0.645000 5.675000 0.815000 ; - RECT 3.755000 1.915000 4.425000 2.635000 ; - RECT 4.665000 1.705000 4.835000 2.465000 ; - RECT 5.005000 0.085000 5.335000 0.465000 ; - RECT 5.005000 1.915000 5.335000 2.635000 ; - RECT 5.505000 0.255000 5.675000 0.645000 ; - RECT 5.505000 1.705000 5.675000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__a41oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a41oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a41oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.385000 0.995000 4.205000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.405000 1.075000 6.315000 1.285000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.560000 1.075000 7.955000 1.300000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.285000 1.075000 9.975000 1.280000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 1.745000 1.305000 ; - RECT 0.105000 1.305000 0.325000 1.965000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.242000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.575000 2.155000 1.685000 ; - RECT 0.515000 1.685000 1.685000 1.745000 ; - RECT 0.515000 1.745000 0.845000 2.085000 ; - RECT 0.595000 0.255000 0.765000 0.635000 ; - RECT 0.595000 0.635000 4.015000 0.805000 ; - RECT 1.350000 1.495000 2.155000 1.575000 ; - RECT 1.350000 1.745000 1.685000 2.085000 ; - RECT 1.435000 0.255000 1.605000 0.635000 ; - RECT 1.935000 0.805000 2.155000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.465000 ; - RECT 0.090000 2.255000 2.335000 2.425000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 1.775000 0.085000 2.105000 0.465000 ; - RECT 2.165000 1.905000 3.515000 2.075000 ; - RECT 2.165000 2.075000 2.335000 2.255000 ; - RECT 2.165000 2.425000 2.335000 2.465000 ; - RECT 2.425000 0.295000 6.115000 0.465000 ; - RECT 2.505000 2.255000 3.175000 2.635000 ; - RECT 3.345000 1.575000 9.945000 1.745000 ; - RECT 3.345000 1.745000 3.515000 1.905000 ; - RECT 3.345000 2.075000 3.515000 2.465000 ; - RECT 3.685000 1.915000 4.015000 2.635000 ; - RECT 4.185000 1.745000 4.355000 2.425000 ; - RECT 4.525000 0.635000 7.895000 0.805000 ; - RECT 4.620000 1.915000 4.950000 2.635000 ; - RECT 5.120000 1.745000 5.290000 2.465000 ; - RECT 5.495000 1.915000 6.165000 2.635000 ; - RECT 6.305000 0.295000 8.235000 0.465000 ; - RECT 6.385000 1.745000 6.555000 2.465000 ; - RECT 6.725000 1.915000 7.055000 2.635000 ; - RECT 7.225000 1.745000 7.395000 2.465000 ; - RECT 7.565000 1.915000 7.895000 2.635000 ; - RECT 8.065000 0.255000 8.235000 0.295000 ; - RECT 8.065000 0.465000 8.235000 0.635000 ; - RECT 8.065000 0.635000 9.915000 0.805000 ; - RECT 8.065000 1.745000 8.235000 2.465000 ; - RECT 8.405000 0.085000 8.735000 0.465000 ; - RECT 8.405000 1.915000 8.735000 2.635000 ; - RECT 8.905000 0.255000 9.075000 0.635000 ; - RECT 8.905000 1.745000 9.075000 2.465000 ; - RECT 9.245000 0.085000 9.575000 0.465000 ; - RECT 9.245000 1.915000 9.575000 2.635000 ; - RECT 9.745000 0.255000 9.915000 0.635000 ; - RECT 9.775000 1.745000 9.945000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__a41oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.485000 0.995000 2.060000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.025000 0.995000 1.305000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.240000 0.995000 2.675000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.855000 0.995000 3.125000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.437250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.265000 0.425000 1.685000 ; - RECT 0.090000 1.685000 0.355000 2.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.135000 -0.085000 0.305000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.525000 1.915000 0.855000 2.635000 ; - RECT 0.600000 0.625000 3.085000 0.815000 ; - RECT 0.600000 0.815000 0.825000 1.505000 ; - RECT 0.600000 1.505000 3.095000 1.685000 ; - RECT 0.605000 0.085000 1.350000 0.455000 ; - RECT 1.045000 1.865000 2.235000 2.095000 ; - RECT 1.045000 2.095000 1.305000 2.455000 ; - RECT 1.475000 2.265000 1.805000 2.635000 ; - RECT 1.915000 0.265000 2.170000 0.625000 ; - RECT 1.975000 2.095000 2.235000 2.455000 ; - RECT 2.350000 0.085000 2.680000 0.455000 ; - RECT 2.805000 1.685000 3.095000 2.455000 ; - RECT 2.860000 0.265000 3.085000 0.625000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a211o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.980000 1.045000 2.450000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 1.045000 1.810000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.620000 1.045000 3.070000 1.275000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.260000 1.045000 3.595000 1.275000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.452000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.555000 0.255000 0.775000 0.635000 ; - RECT 0.555000 0.635000 0.785000 2.335000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 0.085000 0.385000 0.905000 ; - RECT 0.090000 1.490000 0.385000 2.635000 ; - RECT 0.945000 0.085000 1.795000 0.445000 ; - RECT 1.000000 0.695000 3.585000 0.875000 ; - RECT 1.000000 0.875000 1.310000 1.490000 ; - RECT 1.000000 1.490000 3.585000 1.660000 ; - RECT 1.000000 1.830000 1.255000 2.635000 ; - RECT 1.455000 1.840000 2.795000 2.020000 ; - RECT 1.455000 2.020000 1.785000 2.465000 ; - RECT 1.955000 2.190000 2.230000 2.635000 ; - RECT 2.275000 0.275000 2.605000 0.695000 ; - RECT 2.465000 2.020000 2.795000 2.465000 ; - RECT 2.810000 0.085000 3.085000 0.525000 ; - RECT 3.255000 0.275000 3.585000 0.695000 ; - RECT 3.255000 1.660000 3.585000 2.325000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a211o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.035000 1.020000 5.380000 1.330000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.495000 1.020000 4.825000 1.510000 ; - RECT 4.495000 1.510000 5.845000 1.700000 ; - RECT 5.635000 1.020000 6.225000 1.320000 ; - RECT 5.635000 1.320000 5.845000 1.510000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.540000 0.985000 2.805000 1.325000 ; - RECT 2.625000 1.325000 2.805000 1.445000 ; - RECT 2.625000 1.445000 4.175000 1.700000 ; - RECT 3.845000 0.985000 4.175000 1.445000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.975000 0.985000 3.645000 1.275000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.933750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.635000 2.025000 0.875000 ; - RECT 0.085000 0.875000 0.340000 1.495000 ; - RECT 0.085000 1.495000 1.640000 1.705000 ; - RECT 0.595000 1.705000 0.780000 2.465000 ; - RECT 0.985000 0.255000 1.175000 0.615000 ; - RECT 0.985000 0.615000 2.025000 0.635000 ; - RECT 1.450000 1.705000 1.640000 2.465000 ; - RECT 1.845000 0.255000 2.025000 0.615000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.090000 1.875000 0.425000 2.635000 ; - RECT 0.485000 0.085000 0.815000 0.465000 ; - RECT 0.525000 1.045000 2.370000 1.325000 ; - RECT 0.950000 1.875000 1.280000 2.635000 ; - RECT 1.345000 0.085000 1.675000 0.445000 ; - RECT 1.810000 1.835000 2.060000 2.635000 ; - RECT 2.185000 1.325000 2.370000 1.505000 ; - RECT 2.185000 1.505000 2.455000 1.675000 ; - RECT 2.195000 0.615000 5.490000 0.805000 ; - RECT 2.195000 0.805000 2.370000 1.045000 ; - RECT 2.220000 0.085000 2.555000 0.445000 ; - RECT 2.280000 1.675000 2.455000 1.870000 ; - RECT 2.280000 1.870000 3.510000 2.040000 ; - RECT 2.320000 2.210000 4.450000 2.465000 ; - RECT 2.725000 0.255000 2.970000 0.615000 ; - RECT 3.140000 0.085000 3.470000 0.445000 ; - RECT 3.640000 0.255000 4.020000 0.615000 ; - RECT 4.120000 1.880000 6.345000 2.105000 ; - RECT 4.120000 2.105000 4.450000 2.210000 ; - RECT 4.190000 0.085000 4.560000 0.445000 ; - RECT 4.620000 2.275000 4.950000 2.635000 ; - RECT 5.160000 0.275000 5.490000 0.615000 ; - RECT 5.160000 2.105000 5.420000 2.465000 ; - RECT 5.590000 2.275000 5.920000 2.635000 ; - RECT 6.015000 0.085000 6.345000 0.805000 ; - RECT 6.015000 1.535000 6.345000 1.880000 ; - RECT 6.090000 2.105000 6.345000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__a211o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.265000 0.855000 0.995000 ; - RECT 0.605000 0.995000 1.245000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.765000 0.435000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.425000 0.995000 1.755000 1.325000 ; - RECT 1.525000 1.325000 1.755000 2.455000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.995000 2.235000 1.615000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.619250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.180000 0.265000 1.365000 0.625000 ; - RECT 1.180000 0.625000 2.660000 0.815000 ; - RECT 1.935000 1.785000 2.660000 2.455000 ; - RECT 2.055000 0.265000 2.280000 0.625000 ; - RECT 2.445000 0.815000 2.660000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.085000 0.425000 0.595000 ; - RECT 0.250000 1.525000 1.355000 1.725000 ; - RECT 0.250000 1.725000 0.500000 2.455000 ; - RECT 0.670000 1.905000 1.000000 2.635000 ; - RECT 1.170000 1.725000 1.355000 2.455000 ; - RECT 1.545000 0.085000 1.875000 0.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__a211oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.370000 1.035000 3.080000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.740000 1.035000 4.500000 1.285000 ; - RECT 4.175000 1.285000 4.500000 1.655000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.035000 1.035000 1.785000 1.285000 ; - RECT 1.035000 1.285000 1.255000 1.615000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 0.995000 0.405000 1.615000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.826000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.575000 0.255000 0.835000 0.655000 ; - RECT 0.575000 0.655000 3.145000 0.855000 ; - RECT 0.575000 0.855000 0.855000 1.785000 ; - RECT 0.575000 1.785000 0.905000 2.105000 ; - RECT 1.505000 0.285000 1.695000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.125000 -0.085000 0.295000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.145000 0.085000 0.395000 0.815000 ; - RECT 0.145000 1.785000 0.405000 2.285000 ; - RECT 0.145000 2.285000 2.215000 2.455000 ; - RECT 1.005000 0.085000 1.335000 0.475000 ; - RECT 1.075000 1.785000 1.265000 2.255000 ; - RECT 1.075000 2.255000 2.215000 2.285000 ; - RECT 1.435000 1.455000 3.975000 1.655000 ; - RECT 1.435000 1.655000 1.765000 2.075000 ; - RECT 1.865000 0.085000 2.195000 0.475000 ; - RECT 1.935000 1.835000 2.215000 2.255000 ; - RECT 2.385000 0.265000 3.495000 0.475000 ; - RECT 2.435000 1.835000 2.665000 2.635000 ; - RECT 2.845000 1.655000 3.115000 2.465000 ; - RECT 3.295000 1.835000 3.525000 2.635000 ; - RECT 3.325000 0.475000 3.495000 0.635000 ; - RECT 3.325000 0.635000 4.435000 0.855000 ; - RECT 3.675000 0.085000 4.005000 0.455000 ; - RECT 3.705000 1.655000 3.975000 2.465000 ; - RECT 4.155000 1.835000 4.385000 2.635000 ; - RECT 4.185000 0.265000 4.435000 0.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__a211oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a211oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a211oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.655000 1.075000 3.005000 1.245000 ; - RECT 1.660000 1.035000 3.005000 1.075000 ; - RECT 1.660000 1.245000 3.005000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.035000 1.385000 1.445000 ; - RECT 0.100000 1.445000 3.575000 1.625000 ; - RECT 3.245000 1.035000 3.575000 1.445000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.745000 1.035000 4.755000 1.275000 ; - RECT 3.745000 1.275000 4.460000 1.615000 ; - LAYER mcon ; - RECT 3.830000 1.445000 4.000000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 6.590000 0.995000 6.935000 1.325000 ; - RECT 6.590000 1.325000 6.760000 1.615000 ; - LAYER mcon ; - RECT 6.590000 1.445000 6.760000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 3.770000 1.415000 4.060000 1.460000 ; - RECT 3.770000 1.460000 6.820000 1.600000 ; - RECT 3.770000 1.600000 4.060000 1.645000 ; - RECT 6.530000 1.415000 6.820000 1.460000 ; - RECT 6.530000 1.600000 6.820000 1.645000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.000000 1.035000 6.350000 1.275000 ; - RECT 6.130000 1.275000 6.350000 1.695000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.685000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.775000 0.675000 3.330000 0.695000 ; - RECT 1.775000 0.695000 7.275000 0.825000 ; - RECT 1.775000 0.825000 6.355000 0.865000 ; - RECT 3.875000 0.255000 4.195000 0.615000 ; - RECT 3.875000 0.615000 5.045000 0.625000 ; - RECT 3.875000 0.625000 7.275000 0.695000 ; - RECT 4.875000 0.255000 5.045000 0.615000 ; - RECT 5.170000 1.865000 7.275000 2.085000 ; - RECT 5.715000 0.255000 5.885000 0.615000 ; - RECT 5.715000 0.615000 7.275000 0.625000 ; - RECT 6.930000 1.495000 7.275000 1.865000 ; - RECT 7.105000 0.825000 7.275000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.095000 0.085000 0.395000 0.585000 ; - RECT 0.095000 1.795000 3.705000 2.085000 ; - RECT 0.095000 2.085000 0.345000 2.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 0.565000 0.530000 0.775000 0.695000 ; - RECT 0.565000 0.695000 1.605000 0.865000 ; - RECT 0.950000 0.085000 1.185000 0.525000 ; - RECT 1.015000 2.085000 3.705000 2.105000 ; - RECT 1.015000 2.105000 1.185000 2.465000 ; - RECT 1.355000 0.255000 3.365000 0.505000 ; - RECT 1.355000 0.505000 1.605000 0.695000 ; - RECT 1.355000 2.275000 1.685000 2.635000 ; - RECT 1.855000 2.105000 2.025000 2.465000 ; - RECT 2.195000 2.275000 2.525000 2.635000 ; - RECT 2.695000 2.105000 2.865000 2.465000 ; - RECT 3.035000 2.275000 3.365000 2.635000 ; - RECT 3.535000 0.085000 3.705000 0.525000 ; - RECT 3.535000 2.105000 3.705000 2.255000 ; - RECT 3.535000 2.255000 7.270000 2.465000 ; - RECT 3.875000 1.785000 4.910000 2.085000 ; - RECT 4.365000 0.085000 4.695000 0.445000 ; - RECT 4.630000 1.445000 5.960000 1.695000 ; - RECT 4.630000 1.695000 4.910000 1.785000 ; - RECT 5.215000 0.085000 5.545000 0.445000 ; - RECT 6.055000 0.085000 6.385000 0.445000 ; - RECT 6.915000 0.085000 7.270000 0.445000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__a211oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.970000 0.675000 2.255000 1.075000 ; - RECT 1.970000 1.075000 2.300000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.470000 1.075000 2.835000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.225000 1.075000 1.700000 1.275000 ; - RECT 1.420000 0.675000 1.700000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 1.075000 1.055000 1.275000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.440000 1.285000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.320000 0.255000 3.575000 0.585000 ; - RECT 3.320000 1.795000 3.575000 2.465000 ; - RECT 3.390000 0.585000 3.575000 0.665000 ; - RECT 3.405000 0.665000 3.575000 1.795000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 1.240000 0.905000 ; - RECT 0.175000 1.455000 3.235000 1.625000 ; - RECT 0.175000 1.625000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.515000 1.795000 0.845000 2.295000 ; - RECT 0.515000 2.295000 1.685000 2.465000 ; - RECT 1.015000 1.795000 2.650000 2.035000 ; - RECT 1.015000 2.035000 1.245000 2.125000 ; - RECT 1.070000 0.255000 2.605000 0.505000 ; - RECT 1.070000 0.505000 1.240000 0.735000 ; - RECT 1.355000 2.255000 1.685000 2.295000 ; - RECT 1.875000 2.215000 2.230000 2.635000 ; - RECT 2.400000 2.035000 2.650000 2.465000 ; - RECT 2.435000 0.505000 2.605000 0.735000 ; - RECT 2.435000 0.735000 3.235000 0.905000 ; - RECT 2.775000 0.085000 3.105000 0.565000 ; - RECT 2.820000 1.875000 3.150000 2.635000 ; - RECT 3.065000 0.905000 3.235000 1.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a221o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.970000 0.675000 2.255000 1.075000 ; - RECT 1.970000 1.075000 2.300000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.470000 1.075000 2.835000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.225000 1.075000 1.700000 1.275000 ; - RECT 1.420000 0.675000 1.700000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 1.075000 1.055000 1.275000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.440000 1.285000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.320000 0.255000 3.575000 0.585000 ; - RECT 3.320000 1.795000 3.575000 2.465000 ; - RECT 3.390000 0.585000 3.575000 0.665000 ; - RECT 3.405000 0.665000 3.575000 1.795000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 1.240000 0.905000 ; - RECT 0.175000 1.455000 3.235000 1.625000 ; - RECT 0.175000 1.625000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.515000 1.795000 0.845000 2.295000 ; - RECT 0.515000 2.295000 1.685000 2.465000 ; - RECT 1.015000 1.795000 2.650000 2.035000 ; - RECT 1.015000 2.035000 1.245000 2.125000 ; - RECT 1.070000 0.255000 2.605000 0.505000 ; - RECT 1.070000 0.505000 1.240000 0.735000 ; - RECT 1.355000 2.255000 1.685000 2.295000 ; - RECT 1.875000 2.215000 2.230000 2.635000 ; - RECT 2.400000 2.035000 2.650000 2.465000 ; - RECT 2.435000 0.505000 2.605000 0.735000 ; - RECT 2.435000 0.735000 3.235000 0.905000 ; - RECT 2.775000 0.085000 3.105000 0.565000 ; - RECT 2.820000 1.875000 3.150000 2.635000 ; - RECT 3.065000 0.905000 3.235000 1.455000 ; - RECT 3.745000 0.085000 3.915000 0.980000 ; - RECT 3.745000 1.445000 3.915000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a221o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.855000 1.075000 3.190000 1.105000 ; - RECT 2.855000 1.105000 4.060000 1.285000 ; - RECT 3.710000 1.075000 4.060000 1.105000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.265000 1.075000 2.680000 1.285000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.235000 1.075000 6.035000 1.285000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.270000 1.075000 7.280000 1.285000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.230000 1.075000 4.725000 1.285000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.735000 1.685000 0.905000 ; - RECT 0.095000 0.905000 0.325000 1.455000 ; - RECT 0.095000 1.455000 1.645000 1.625000 ; - RECT 0.515000 0.255000 0.845000 0.725000 ; - RECT 0.515000 0.725000 1.685000 0.735000 ; - RECT 0.555000 1.625000 0.805000 2.465000 ; - RECT 1.355000 0.255000 1.685000 0.725000 ; - RECT 1.395000 1.625000 1.645000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.155000 -0.085000 0.325000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.155000 1.795000 0.385000 2.635000 ; - RECT 0.175000 0.085000 0.345000 0.555000 ; - RECT 0.495000 1.075000 1.845000 1.115000 ; - RECT 0.495000 1.115000 1.985000 1.285000 ; - RECT 0.975000 1.795000 1.225000 2.635000 ; - RECT 1.015000 0.085000 1.185000 0.555000 ; - RECT 1.815000 1.285000 1.985000 1.455000 ; - RECT 1.815000 1.455000 5.065000 1.625000 ; - RECT 1.815000 1.795000 2.065000 2.635000 ; - RECT 1.855000 0.085000 2.025000 0.555000 ; - RECT 1.855000 0.735000 2.525000 0.905000 ; - RECT 1.945000 0.905000 2.165000 0.935000 ; - RECT 2.195000 0.255000 2.525000 0.735000 ; - RECT 2.235000 1.795000 4.230000 1.875000 ; - RECT 2.235000 1.875000 5.575000 1.965000 ; - RECT 2.235000 1.965000 2.485000 2.465000 ; - RECT 2.655000 2.135000 2.905000 2.635000 ; - RECT 2.695000 0.085000 2.865000 0.895000 ; - RECT 3.075000 1.965000 3.330000 2.465000 ; - RECT 3.080000 0.305000 4.305000 0.475000 ; - RECT 3.190000 0.735000 3.885000 0.905000 ; - RECT 3.315000 0.905000 3.610000 0.935000 ; - RECT 3.500000 2.135000 3.750000 2.635000 ; - RECT 3.550000 0.645000 3.885000 0.735000 ; - RECT 3.940000 2.215000 6.385000 2.295000 ; - RECT 3.940000 2.295000 7.225000 2.465000 ; - RECT 4.055000 0.475000 4.305000 0.725000 ; - RECT 4.055000 0.725000 5.065000 0.905000 ; - RECT 4.060000 1.965000 5.575000 2.045000 ; - RECT 4.405000 1.625000 4.735000 1.705000 ; - RECT 4.475000 0.085000 4.645000 0.555000 ; - RECT 4.815000 0.255000 5.985000 0.475000 ; - RECT 4.815000 0.475000 5.065000 0.725000 ; - RECT 4.895000 0.905000 5.065000 1.455000 ; - RECT 5.235000 0.645000 6.505000 0.725000 ; - RECT 5.235000 0.725000 7.345000 0.905000 ; - RECT 5.245000 1.455000 6.805000 1.625000 ; - RECT 5.245000 1.625000 5.575000 1.875000 ; - RECT 5.745000 1.795000 6.385000 2.215000 ; - RECT 6.555000 1.625000 6.805000 2.125000 ; - RECT 6.675000 0.085000 6.845000 0.555000 ; - RECT 6.975000 1.785000 7.225000 2.295000 ; - RECT 7.015000 0.255000 7.345000 0.725000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 1.995000 0.765000 2.165000 0.935000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.400000 0.765000 3.570000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 1.935000 0.735000 2.225000 0.780000 ; - RECT 1.935000 0.780000 3.630000 0.920000 ; - RECT 1.935000 0.920000 2.225000 0.965000 ; - RECT 3.340000 0.735000 3.630000 0.780000 ; - RECT 3.340000 0.920000 3.630000 0.965000 ; - END -END sky130_fd_sc_hd__a221o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.945000 0.675000 2.200000 1.075000 ; - RECT 1.945000 1.075000 2.275000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.470000 0.995000 2.755000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.225000 1.075000 1.695000 1.285000 ; - RECT 1.415000 0.675000 1.695000 1.075000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.615000 1.075000 1.055000 1.285000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.435000 1.285000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.767000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.170000 0.255000 0.345000 0.735000 ; - RECT 0.170000 0.735000 1.235000 0.905000 ; - RECT 0.175000 1.455000 2.300000 1.495000 ; - RECT 0.175000 1.495000 3.135000 1.625000 ; - RECT 0.175000 1.625000 0.345000 2.465000 ; - RECT 1.065000 0.255000 2.580000 0.505000 ; - RECT 1.065000 0.505000 1.235000 0.735000 ; - RECT 2.150000 1.625000 3.135000 1.665000 ; - RECT 2.380000 0.505000 2.580000 0.655000 ; - RECT 2.380000 0.655000 3.135000 0.825000 ; - RECT 2.925000 0.825000 3.135000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.515000 1.795000 0.765000 2.295000 ; - RECT 0.515000 2.295000 1.685000 2.465000 ; - RECT 1.015000 1.795000 2.025000 1.835000 ; - RECT 1.015000 1.835000 2.625000 2.045000 ; - RECT 1.015000 2.045000 1.240000 2.125000 ; - RECT 1.355000 2.255000 1.685000 2.295000 ; - RECT 1.875000 2.215000 2.205000 2.635000 ; - RECT 2.375000 2.045000 2.625000 2.465000 ; - RECT 2.750000 0.085000 3.080000 0.485000 ; - RECT 2.795000 1.875000 3.125000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a221oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.985000 1.075000 4.480000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.435000 1.075000 3.765000 1.445000 ; - RECT 3.435000 1.445000 4.820000 1.615000 ; - RECT 4.650000 1.075000 5.435000 1.275000 ; - RECT 4.650000 1.275000 4.820000 1.445000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.210000 1.075000 2.765000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.505000 1.075000 2.040000 1.445000 ; - RECT 1.505000 1.445000 3.265000 1.615000 ; - RECT 2.935000 1.075000 3.265000 1.445000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.420000 1.615000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.796500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.525000 0.305000 0.855000 0.725000 ; - RECT 0.525000 0.725000 4.395000 0.865000 ; - RECT 0.605000 0.865000 4.395000 0.905000 ; - RECT 0.605000 0.905000 0.855000 2.125000 ; - RECT 2.285000 0.645000 2.635000 0.725000 ; - RECT 4.065000 0.645000 4.395000 0.725000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.090000 1.795000 0.435000 2.295000 ; - RECT 0.090000 2.295000 1.275000 2.465000 ; - RECT 0.105000 0.085000 0.355000 0.895000 ; - RECT 1.025000 0.085000 1.715000 0.555000 ; - RECT 1.025000 1.495000 1.275000 1.785000 ; - RECT 1.025000 1.785000 3.015000 1.955000 ; - RECT 1.025000 1.955000 1.275000 2.295000 ; - RECT 1.505000 2.125000 1.755000 2.295000 ; - RECT 1.505000 2.295000 3.475000 2.465000 ; - RECT 1.885000 0.255000 3.055000 0.475000 ; - RECT 1.925000 1.955000 2.175000 2.125000 ; - RECT 2.345000 2.125000 2.595000 2.295000 ; - RECT 2.765000 1.955000 3.015000 2.125000 ; - RECT 3.225000 1.785000 5.195000 1.955000 ; - RECT 3.225000 1.955000 3.475000 2.295000 ; - RECT 3.270000 0.085000 3.440000 0.555000 ; - RECT 3.645000 0.255000 4.815000 0.475000 ; - RECT 3.685000 2.125000 3.935000 2.635000 ; - RECT 4.105000 1.955000 4.355000 2.465000 ; - RECT 4.525000 2.125000 4.775000 2.635000 ; - RECT 4.565000 0.475000 4.815000 0.905000 ; - RECT 4.985000 0.085000 5.155000 0.905000 ; - RECT 4.990000 1.455000 5.195000 1.785000 ; - RECT 4.990000 1.955000 5.195000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__a221oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a221oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a221oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.475000 1.075000 7.885000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.965000 1.075000 6.295000 1.445000 ; - RECT 5.965000 1.445000 8.265000 1.615000 ; - RECT 8.095000 1.075000 9.575000 1.275000 ; - RECT 8.095000 1.275000 8.265000 1.445000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.935000 0.995000 5.285000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.415000 0.995000 3.765000 1.325000 ; - RECT 3.595000 1.325000 3.765000 1.445000 ; - RECT 3.595000 1.445000 5.795000 1.615000 ; - RECT 5.465000 1.075000 5.795000 1.445000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 1.335000 1.275000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.593000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 1.705000 0.905000 ; - RECT 0.575000 1.445000 1.705000 1.615000 ; - RECT 0.575000 1.615000 0.825000 2.125000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 1.415000 1.615000 1.665000 2.125000 ; - RECT 1.505000 0.905000 1.705000 1.095000 ; - RECT 1.505000 1.095000 3.245000 1.275000 ; - RECT 1.505000 1.275000 1.705000 1.445000 ; - RECT 3.075000 0.645000 5.680000 0.735000 ; - RECT 3.075000 0.735000 7.765000 0.820000 ; - RECT 3.075000 0.820000 3.245000 1.095000 ; - RECT 5.510000 0.820000 6.460000 0.905000 ; - RECT 6.290000 0.645000 7.765000 0.735000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.090000 1.445000 0.405000 2.295000 ; - RECT 0.090000 2.295000 2.125000 2.465000 ; - RECT 0.115000 0.085000 0.365000 0.895000 ; - RECT 0.995000 1.785000 1.245000 2.295000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.875000 0.085000 2.045000 0.645000 ; - RECT 1.875000 0.645000 2.905000 0.925000 ; - RECT 1.875000 1.445000 3.030000 1.615000 ; - RECT 1.875000 1.615000 2.125000 2.295000 ; - RECT 2.235000 0.255000 5.585000 0.425000 ; - RECT 2.235000 0.425000 2.610000 0.475000 ; - RECT 2.315000 1.795000 2.565000 2.215000 ; - RECT 2.315000 2.215000 6.005000 2.465000 ; - RECT 2.735000 0.595000 2.905000 0.645000 ; - RECT 2.735000 1.615000 3.030000 1.835000 ; - RECT 2.735000 1.835000 5.585000 2.045000 ; - RECT 3.035000 0.425000 5.585000 0.475000 ; - RECT 5.755000 1.785000 8.605000 2.045000 ; - RECT 5.755000 2.045000 6.005000 2.215000 ; - RECT 5.835000 0.085000 6.005000 0.555000 ; - RECT 6.175000 0.255000 8.185000 0.475000 ; - RECT 6.175000 2.215000 8.185000 2.635000 ; - RECT 7.935000 0.475000 8.185000 0.725000 ; - RECT 7.935000 0.725000 9.025000 0.905000 ; - RECT 8.355000 0.085000 8.525000 0.555000 ; - RECT 8.355000 2.045000 8.525000 2.465000 ; - RECT 8.435000 1.445000 9.405000 1.615000 ; - RECT 8.435000 1.615000 8.605000 1.785000 ; - RECT 8.695000 0.255000 9.025000 0.725000 ; - RECT 8.775000 1.795000 8.945000 2.635000 ; - RECT 9.155000 1.615000 9.405000 2.465000 ; - RECT 9.195000 0.085000 9.365000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__a221oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a222oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a222oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.615000 1.000000 2.925000 1.330000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.095000 1.000000 3.435000 1.330000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.135000 1.000000 2.445000 1.330000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.655000 1.000000 1.965000 1.330000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.000000 0.545000 1.315000 ; - END - END C1 - PIN C2 - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.715000 1.000000 1.085000 1.315000 ; - END - END C2 - PIN Y - ANTENNADIFFAREA 0.897600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.255000 0.425000 0.645000 ; - RECT 0.095000 0.645000 2.645000 0.815000 ; - RECT 0.095000 1.485000 0.425000 1.500000 ; - RECT 0.095000 1.500000 1.425000 1.670000 ; - RECT 0.095000 1.670000 0.425000 1.680000 ; - RECT 0.095000 1.680000 0.345000 2.255000 ; - RECT 0.095000 2.255000 0.425000 2.465000 ; - RECT 1.015000 1.670000 1.185000 1.830000 ; - RECT 1.255000 0.815000 1.480000 1.330000 ; - RECT 1.255000 1.330000 1.425000 1.500000 ; - RECT 2.315000 0.295000 2.645000 0.645000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.000000 0.000000 3.680000 0.240000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.515000 1.875000 0.845000 2.075000 ; - RECT 0.595000 2.075000 0.765000 2.295000 ; - RECT 0.595000 2.295000 2.185000 2.465000 ; - RECT 0.875000 0.085000 1.605000 0.465000 ; - RECT 1.515000 1.825000 2.015000 1.965000 ; - RECT 1.515000 1.965000 1.970000 1.970000 ; - RECT 1.515000 1.970000 1.935000 1.980000 ; - RECT 1.515000 1.980000 1.915000 1.995000 ; - RECT 1.845000 1.655000 3.595000 1.670000 ; - RECT 1.845000 1.670000 2.685000 1.735000 ; - RECT 1.845000 1.735000 2.605000 1.825000 ; - RECT 2.015000 2.135000 2.185000 2.295000 ; - RECT 2.355000 1.500000 3.595000 1.655000 ; - RECT 2.355000 1.825000 2.605000 2.255000 ; - RECT 2.355000 2.255000 2.685000 2.465000 ; - RECT 2.775000 1.905000 3.105000 2.075000 ; - RECT 2.855000 2.075000 3.025000 2.635000 ; - RECT 3.220000 1.670000 3.595000 1.735000 ; - RECT 3.255000 0.085000 3.585000 0.815000 ; - RECT 3.255000 2.255000 3.595000 2.465000 ; - RECT 3.335000 1.735000 3.595000 2.255000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a222oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.965000 0.765000 2.155000 0.995000 ; - RECT 1.965000 0.995000 2.310000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.510000 0.750000 1.705000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.905000 0.995000 1.240000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.620000 0.995000 3.095000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.350000 0.995000 3.535000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.454000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.395000 0.670000 ; - RECT 0.085000 0.670000 0.255000 1.785000 ; - RECT 0.085000 1.785000 0.425000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.425000 0.995000 0.735000 1.325000 ; - RECT 0.565000 0.655000 1.260000 0.825000 ; - RECT 0.565000 0.825000 0.735000 0.995000 ; - RECT 0.565000 1.325000 0.735000 1.495000 ; - RECT 0.565000 1.495000 3.505000 1.665000 ; - RECT 0.590000 0.085000 0.920000 0.465000 ; - RECT 0.595000 2.175000 0.840000 2.635000 ; - RECT 1.015000 1.835000 2.575000 2.005000 ; - RECT 1.015000 2.005000 1.265000 2.465000 ; - RECT 1.090000 0.255000 2.495000 0.425000 ; - RECT 1.090000 0.425000 1.260000 0.655000 ; - RECT 1.455000 2.255000 2.125000 2.635000 ; - RECT 2.325000 0.425000 2.495000 0.655000 ; - RECT 2.325000 0.655000 3.505000 0.825000 ; - RECT 2.325000 2.005000 2.575000 2.465000 ; - RECT 2.765000 0.085000 3.095000 0.485000 ; - RECT 3.335000 0.255000 3.505000 0.655000 ; - RECT 3.335000 1.665000 3.505000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a311o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 0.605000 2.620000 0.995000 ; - RECT 2.440000 0.995000 2.675000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.895000 0.605000 2.165000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.495000 0.995000 1.710000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.895000 0.995000 3.235000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.695000 0.995000 4.005000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.295000 0.845000 2.425000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.085000 0.345000 0.885000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 1.015000 0.085000 1.345000 0.465000 ; - RECT 1.015000 0.655000 1.695000 0.825000 ; - RECT 1.015000 0.825000 1.185000 1.495000 ; - RECT 1.015000 1.495000 3.965000 1.665000 ; - RECT 1.160000 1.835000 1.380000 2.635000 ; - RECT 1.525000 0.255000 2.960000 0.425000 ; - RECT 1.525000 0.425000 1.695000 0.655000 ; - RECT 1.590000 1.835000 3.025000 2.005000 ; - RECT 1.590000 2.005000 1.840000 2.465000 ; - RECT 2.125000 2.255000 2.455000 2.635000 ; - RECT 2.715000 2.005000 3.025000 2.465000 ; - RECT 2.790000 0.425000 2.960000 0.655000 ; - RECT 2.790000 0.655000 3.965000 0.825000 ; - RECT 3.220000 0.085000 3.550000 0.485000 ; - RECT 3.795000 0.255000 3.965000 0.655000 ; - RECT 3.795000 1.665000 3.965000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a311o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.945000 1.075000 7.275000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.255000 1.075000 6.040000 1.285000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.515000 1.075000 4.945000 1.285000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.060000 1.075000 1.505000 1.285000 ; - RECT 1.060000 1.285000 1.255000 1.625000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 0.745000 0.350000 1.625000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.904000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.195000 0.295000 2.545000 0.465000 ; - RECT 2.295000 0.465000 2.465000 0.715000 ; - RECT 2.295000 0.715000 3.305000 0.885000 ; - RECT 2.715000 1.545000 3.885000 1.715000 ; - RECT 2.910000 0.885000 3.105000 1.545000 ; - RECT 3.055000 0.295000 3.385000 0.465000 ; - RECT 3.135000 0.465000 3.305000 0.715000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.095000 0.085000 0.345000 0.565000 ; - RECT 0.175000 1.795000 0.345000 2.295000 ; - RECT 0.175000 2.295000 2.025000 2.465000 ; - RECT 0.515000 0.295000 0.845000 0.465000 ; - RECT 0.515000 1.955000 0.845000 2.125000 ; - RECT 0.595000 0.465000 0.765000 0.715000 ; - RECT 0.595000 0.715000 2.025000 0.885000 ; - RECT 0.595000 0.885000 0.765000 1.955000 ; - RECT 1.015000 0.085000 1.185000 0.545000 ; - RECT 1.015000 1.795000 1.185000 2.295000 ; - RECT 1.355000 0.295000 1.685000 0.465000 ; - RECT 1.435000 0.465000 1.605000 0.715000 ; - RECT 1.435000 1.455000 2.385000 1.625000 ; - RECT 1.435000 1.625000 1.605000 2.125000 ; - RECT 1.855000 0.085000 2.025000 0.545000 ; - RECT 1.855000 0.885000 2.025000 1.075000 ; - RECT 1.855000 1.075000 2.705000 1.245000 ; - RECT 1.855000 1.795000 2.025000 2.295000 ; - RECT 2.195000 1.625000 2.385000 1.915000 ; - RECT 2.195000 1.915000 6.765000 2.085000 ; - RECT 2.295000 2.255000 2.625000 2.635000 ; - RECT 2.715000 0.085000 2.885000 0.545000 ; - RECT 3.135000 2.255000 3.465000 2.635000 ; - RECT 3.275000 1.075000 4.320000 1.245000 ; - RECT 3.555000 0.085000 4.065000 0.545000 ; - RECT 3.975000 2.255000 4.305000 2.635000 ; - RECT 4.150000 1.245000 4.320000 1.455000 ; - RECT 4.150000 1.455000 6.685000 1.625000 ; - RECT 4.275000 0.295000 4.605000 0.465000 ; - RECT 4.355000 0.465000 4.525000 0.715000 ; - RECT 4.355000 0.715000 6.005000 0.885000 ; - RECT 4.475000 1.795000 4.645000 1.915000 ; - RECT 4.475000 2.085000 4.645000 2.465000 ; - RECT 4.775000 0.085000 4.945000 0.545000 ; - RECT 4.815000 2.255000 5.175000 2.635000 ; - RECT 5.255000 0.255000 7.270000 0.425000 ; - RECT 5.255000 0.425000 6.345000 0.465000 ; - RECT 5.375000 1.795000 5.545000 1.915000 ; - RECT 5.375000 2.085000 5.545000 2.465000 ; - RECT 5.675000 0.645000 6.005000 0.715000 ; - RECT 5.715000 2.255000 6.045000 2.635000 ; - RECT 6.175000 0.465000 6.345000 0.885000 ; - RECT 6.515000 0.645000 6.845000 0.825000 ; - RECT 6.515000 0.825000 6.685000 1.455000 ; - RECT 6.595000 1.795000 6.765000 1.915000 ; - RECT 6.595000 2.085000 6.765000 2.465000 ; - RECT 6.935000 0.425000 7.270000 0.500000 ; - RECT 6.935000 1.795000 7.270000 2.635000 ; - RECT 7.015000 0.500000 7.270000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__a311o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.965000 0.265000 1.365000 0.660000 ; - RECT 1.195000 0.660000 1.365000 0.995000 ; - RECT 1.195000 0.995000 1.455000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.600000 0.265000 0.795000 0.995000 ; - RECT 0.600000 0.995000 1.025000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.420000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.710000 0.995000 1.935000 1.835000 ; - RECT 1.710000 1.835000 2.230000 2.005000 ; - RECT 1.950000 2.005000 2.230000 2.355000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 0.995000 2.685000 1.325000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.659750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.535000 0.255000 1.705000 0.655000 ; - RECT 1.535000 0.655000 2.650000 0.825000 ; - RECT 2.105000 0.825000 2.275000 1.495000 ; - RECT 2.105000 1.495000 2.650000 1.665000 ; - RECT 2.405000 0.295000 2.650000 0.655000 ; - RECT 2.410000 1.665000 2.650000 2.335000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.155000 -0.085000 0.325000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.805000 ; - RECT 0.095000 1.495000 0.425000 2.635000 ; - RECT 0.600000 1.575000 1.540000 1.745000 ; - RECT 0.600000 1.745000 0.770000 2.305000 ; - RECT 0.940000 1.915000 1.200000 2.635000 ; - RECT 1.370000 1.745000 1.540000 2.175000 ; - RECT 1.370000 2.175000 1.700000 2.345000 ; - RECT 1.905000 0.085000 2.235000 0.485000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a311oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.000000 0.995000 3.115000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.055000 0.995000 1.805000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 0.995000 0.800000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.395000 0.995000 4.055000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.730000 1.075000 5.410000 1.295000 ; - RECT 5.175000 1.295000 5.410000 1.625000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.141000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.295000 0.655000 5.345000 0.825000 ; - RECT 3.235000 0.255000 3.405000 0.655000 ; - RECT 4.085000 0.255000 4.255000 0.655000 ; - RECT 4.260000 0.825000 4.475000 1.510000 ; - RECT 4.260000 1.510000 4.990000 1.575000 ; - RECT 4.260000 1.575000 5.005000 1.680000 ; - RECT 4.660000 1.680000 5.005000 1.745000 ; - RECT 4.660000 1.745000 4.990000 1.915000 ; - RECT 4.660000 1.915000 5.005000 2.085000 ; - RECT 5.175000 0.255000 5.345000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.095000 1.495000 0.345000 2.635000 ; - RECT 0.175000 0.255000 0.345000 0.655000 ; - RECT 0.175000 0.655000 2.105000 0.825000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.595000 1.575000 3.915000 1.745000 ; - RECT 0.595000 1.745000 0.765000 2.465000 ; - RECT 0.935000 1.915000 1.265000 2.635000 ; - RECT 1.015000 0.255000 1.185000 0.655000 ; - RECT 1.355000 0.305000 3.045000 0.475000 ; - RECT 1.435000 1.745000 1.605000 2.465000 ; - RECT 1.785000 1.915000 2.135000 2.635000 ; - RECT 2.305000 1.745000 2.475000 2.465000 ; - RECT 2.645000 1.915000 2.975000 2.635000 ; - RECT 3.145000 2.255000 5.345000 2.425000 ; - RECT 3.585000 0.085000 3.915000 0.465000 ; - RECT 3.585000 1.745000 3.915000 2.085000 ; - RECT 4.110000 1.915000 4.440000 2.255000 ; - RECT 4.110000 2.425000 4.440000 2.465000 ; - RECT 4.675000 0.085000 5.005000 0.465000 ; - RECT 5.175000 1.795000 5.345000 2.255000 ; - RECT 5.175000 2.425000 5.345000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__a311oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a311oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a311oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.995000 5.420000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.995000 3.550000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.995000 1.735000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.670000 0.995000 6.855000 1.630000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.935000 0.995000 9.530000 1.325000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.898500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.975000 0.635000 9.485000 0.805000 ; - RECT 6.575000 0.255000 6.745000 0.635000 ; - RECT 7.415000 0.255000 7.585000 0.635000 ; - RECT 7.415000 0.805000 7.735000 1.545000 ; - RECT 7.415000 1.545000 9.145000 1.715000 ; - RECT 7.415000 1.715000 7.735000 1.975000 ; - RECT 7.975000 1.530000 8.305000 1.545000 ; - RECT 7.975000 1.715000 8.305000 2.085000 ; - RECT 8.475000 0.255000 8.645000 0.635000 ; - RECT 8.815000 1.715000 9.145000 2.085000 ; - RECT 9.315000 0.255000 9.485000 0.635000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.095000 1.575000 0.425000 2.635000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 3.785000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.595000 1.495000 4.965000 1.665000 ; - RECT 0.595000 1.665000 0.765000 2.465000 ; - RECT 0.935000 1.915000 1.265000 2.635000 ; - RECT 1.015000 0.255000 1.185000 0.635000 ; - RECT 1.355000 0.085000 1.685000 0.465000 ; - RECT 1.435000 1.665000 1.605000 2.465000 ; - RECT 1.775000 1.915000 2.105000 2.635000 ; - RECT 1.855000 0.255000 2.025000 0.635000 ; - RECT 2.195000 0.295000 5.565000 0.465000 ; - RECT 2.275000 1.665000 2.445000 2.465000 ; - RECT 2.615000 1.915000 2.945000 2.635000 ; - RECT 3.115000 1.665000 3.285000 2.465000 ; - RECT 3.455000 1.915000 3.785000 2.635000 ; - RECT 3.955000 1.665000 4.125000 2.465000 ; - RECT 4.295000 1.915000 4.625000 2.635000 ; - RECT 4.795000 1.665000 4.965000 1.915000 ; - RECT 4.795000 1.915000 7.245000 2.085000 ; - RECT 4.795000 2.085000 4.965000 2.465000 ; - RECT 5.135000 2.255000 5.465000 2.635000 ; - RECT 5.655000 2.255000 9.565000 2.425000 ; - RECT 6.075000 0.085000 6.405000 0.465000 ; - RECT 6.915000 0.085000 7.245000 0.465000 ; - RECT 7.975000 0.085000 8.305000 0.465000 ; - RECT 8.815000 0.085000 9.145000 0.465000 ; - RECT 9.315000 1.835000 9.565000 2.255000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__a311oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111o_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111o_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.905000 0.995000 3.290000 1.325000 ; - RECT 2.985000 0.285000 3.540000 0.845000 ; - RECT 2.985000 0.845000 3.290000 0.995000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.510000 1.025000 4.010000 1.290000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.400000 0.995000 2.680000 2.465000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.890000 1.050000 2.220000 2.465000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.290000 1.050000 1.720000 1.290000 ; - RECT 1.515000 1.290000 1.720000 2.465000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.504500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 0.255000 0.465000 1.620000 ; - RECT 0.135000 1.620000 0.390000 2.460000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - PORT - LAYER pwell ; - RECT 1.975000 -0.065000 2.145000 0.105000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.565000 1.815000 0.895000 2.635000 ; - RECT 0.635000 0.085000 1.310000 0.470000 ; - RECT 0.695000 0.650000 1.915000 0.655000 ; - RECT 0.695000 0.655000 2.805000 0.825000 ; - RECT 0.695000 0.825000 0.915000 1.465000 ; - RECT 0.695000 1.465000 1.345000 1.645000 ; - RECT 1.135000 1.645000 1.345000 2.460000 ; - RECT 1.585000 0.260000 1.915000 0.650000 ; - RECT 2.085000 0.085000 2.430000 0.485000 ; - RECT 2.600000 0.260000 2.805000 0.655000 ; - RECT 2.860000 1.495000 3.990000 1.665000 ; - RECT 2.860000 1.665000 3.145000 2.460000 ; - RECT 3.325000 1.835000 3.540000 2.635000 ; - RECT 3.715000 0.085000 3.955000 0.760000 ; - RECT 3.720000 1.665000 3.990000 2.460000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__a2111o_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111o_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111o_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.365000 0.955000 3.775000 1.740000 ; - RECT 3.505000 0.290000 3.995000 0.825000 ; - RECT 3.505000 0.825000 3.775000 0.955000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.945000 0.995000 4.515000 1.740000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.905000 0.995000 3.195000 1.740000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.425000 0.995000 2.735000 2.355000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.885000 0.995000 2.255000 1.325000 ; - RECT 1.960000 1.325000 2.255000 2.355000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.255000 0.895000 2.390000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.085000 0.435000 0.885000 ; - RECT 0.085000 1.635000 0.435000 2.635000 ; - RECT 1.065000 0.085000 2.010000 0.445000 ; - RECT 1.065000 0.445000 1.325000 0.865000 ; - RECT 1.065000 1.075000 1.705000 1.325000 ; - RECT 1.065000 1.495000 1.315000 2.635000 ; - RECT 1.495000 0.615000 3.335000 0.785000 ; - RECT 1.495000 0.785000 1.705000 1.075000 ; - RECT 1.495000 1.325000 1.705000 1.495000 ; - RECT 1.495000 1.495000 1.785000 2.465000 ; - RECT 2.180000 0.255000 2.420000 0.615000 ; - RECT 2.590000 0.085000 2.920000 0.445000 ; - RECT 3.070000 1.915000 4.515000 2.085000 ; - RECT 3.070000 2.085000 3.400000 2.465000 ; - RECT 3.090000 0.255000 3.335000 0.615000 ; - RECT 3.590000 2.255000 3.920000 2.635000 ; - RECT 4.090000 2.085000 4.515000 2.465000 ; - RECT 4.165000 0.085000 4.515000 0.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__a2111o_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111o_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111o_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 1.075000 4.495000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.675000 1.075000 5.625000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.450000 0.975000 3.255000 1.285000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.040000 0.975000 2.280000 1.285000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.370000 1.625000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.165000 0.255000 6.355000 0.635000 ; - RECT 6.165000 0.635000 7.735000 0.805000 ; - RECT 6.165000 1.465000 7.735000 1.635000 ; - RECT 6.165000 1.635000 7.215000 1.715000 ; - RECT 6.165000 1.715000 6.355000 2.465000 ; - RECT 7.025000 0.255000 7.215000 0.635000 ; - RECT 7.025000 1.715000 7.215000 2.465000 ; - RECT 7.490000 0.805000 7.735000 1.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.110000 1.795000 0.370000 2.295000 ; - RECT 0.110000 2.295000 2.160000 2.465000 ; - RECT 0.180000 0.255000 0.440000 0.635000 ; - RECT 0.180000 0.635000 3.655000 0.805000 ; - RECT 0.540000 0.805000 0.870000 2.125000 ; - RECT 0.610000 0.085000 0.940000 0.465000 ; - RECT 1.040000 1.455000 1.230000 2.295000 ; - RECT 1.110000 0.255000 1.340000 0.615000 ; - RECT 1.110000 0.615000 3.655000 0.635000 ; - RECT 1.400000 1.455000 3.100000 1.625000 ; - RECT 1.400000 1.625000 1.730000 2.125000 ; - RECT 1.510000 0.085000 1.840000 0.445000 ; - RECT 1.900000 1.795000 2.160000 2.295000 ; - RECT 2.015000 0.255000 2.240000 0.615000 ; - RECT 2.340000 1.795000 2.675000 2.295000 ; - RECT 2.340000 2.295000 3.650000 2.465000 ; - RECT 2.420000 0.085000 3.295000 0.445000 ; - RECT 2.845000 1.625000 3.100000 2.125000 ; - RECT 3.320000 1.795000 5.495000 1.995000 ; - RECT 3.320000 1.995000 3.650000 2.295000 ; - RECT 3.465000 0.255000 4.585000 0.445000 ; - RECT 3.465000 0.445000 3.655000 0.615000 ; - RECT 3.465000 0.805000 3.655000 1.445000 ; - RECT 3.465000 1.445000 5.975000 1.625000 ; - RECT 3.825000 0.615000 5.495000 0.785000 ; - RECT 3.865000 2.165000 4.195000 2.635000 ; - RECT 4.365000 1.995000 4.625000 2.415000 ; - RECT 4.805000 0.085000 5.140000 0.445000 ; - RECT 4.805000 2.255000 5.140000 2.635000 ; - RECT 5.310000 0.255000 5.495000 0.615000 ; - RECT 5.310000 1.995000 5.495000 2.465000 ; - RECT 5.665000 0.085000 5.995000 0.515000 ; - RECT 5.665000 1.800000 5.995000 2.635000 ; - RECT 5.795000 1.075000 7.320000 1.245000 ; - RECT 5.795000 1.245000 5.975000 1.445000 ; - RECT 6.525000 0.085000 6.855000 0.445000 ; - RECT 6.525000 1.885000 6.855000 2.635000 ; - RECT 7.385000 0.085000 7.715000 0.465000 ; - RECT 7.385000 1.805000 7.715000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__a2111o_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111oi_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111oi_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.035000 1.070000 2.625000 1.400000 ; - RECT 2.355000 0.660000 2.625000 1.070000 ; - RECT 2.355000 1.400000 2.625000 1.735000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.795000 0.650000 3.135000 1.735000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.495000 1.055000 1.845000 1.735000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.955000 1.055000 1.325000 2.360000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.730000 0.435000 1.655000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 0.424000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.360000 1.825000 0.785000 2.465000 ; - RECT 0.605000 0.635000 2.040000 0.885000 ; - RECT 0.605000 0.885000 0.785000 1.825000 ; - RECT 0.785000 0.255000 1.040000 0.615000 ; - RECT 0.785000 0.615000 2.040000 0.635000 ; - RECT 1.710000 0.280000 2.040000 0.615000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.285000 0.085000 0.615000 0.465000 ; - RECT 1.210000 0.085000 1.540000 0.445000 ; - RECT 1.540000 1.905000 2.870000 2.085000 ; - RECT 1.540000 2.085000 1.870000 2.465000 ; - RECT 2.040000 2.255000 2.370000 2.635000 ; - RECT 2.470000 0.085000 2.800000 0.480000 ; - RECT 2.540000 2.085000 2.870000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__a2111oi_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111oi_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111oi_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 0.995000 2.725000 1.400000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.905000 0.350000 3.090000 1.020000 ; - RECT 2.905000 1.020000 3.540000 1.290000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.940000 1.050000 2.270000 1.400000 ; - RECT 1.940000 1.400000 2.215000 2.455000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.435000 1.050000 1.770000 2.455000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.785000 1.050000 1.235000 2.455000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 1.388750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.700000 1.375000 0.705000 ; - RECT 0.145000 0.705000 2.420000 0.815000 ; - RECT 0.145000 0.815000 2.300000 0.880000 ; - RECT 0.145000 0.880000 0.530000 2.460000 ; - RECT 1.045000 0.260000 1.375000 0.700000 ; - RECT 2.090000 0.305000 2.420000 0.705000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - PORT - LAYER pwell ; - RECT 1.975000 -0.065000 2.145000 0.105000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.315000 0.085000 0.630000 0.525000 ; - RECT 1.550000 0.085000 1.880000 0.535000 ; - RECT 2.395000 1.580000 3.505000 1.750000 ; - RECT 2.395000 1.750000 2.625000 2.460000 ; - RECT 2.800000 1.920000 3.130000 2.635000 ; - RECT 3.270000 0.085000 3.510000 0.760000 ; - RECT 3.310000 1.750000 3.505000 2.460000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__a2111oi_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111oi_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111oi_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.465000 0.985000 3.715000 1.445000 ; - RECT 3.465000 1.445000 5.290000 1.675000 ; - RECT 4.895000 0.995000 5.290000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.970000 1.015000 4.725000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.185000 1.030000 2.855000 1.275000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 1.045000 0.455000 1.445000 ; - RECT 0.125000 1.445000 1.800000 1.680000 ; - RECT 1.615000 1.030000 1.975000 1.275000 ; - RECT 1.615000 1.275000 1.800000 1.445000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.755000 1.075000 1.425000 1.275000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 1.212750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.255000 0.380000 0.615000 ; - RECT 0.120000 0.615000 5.355000 0.805000 ; - RECT 0.120000 0.805000 3.255000 0.845000 ; - RECT 0.900000 1.850000 2.140000 2.105000 ; - RECT 1.050000 0.255000 1.295000 0.615000 ; - RECT 1.965000 0.255000 2.295000 0.615000 ; - RECT 1.970000 1.445000 3.255000 1.625000 ; - RECT 1.970000 1.625000 2.140000 1.850000 ; - RECT 2.965000 0.275000 3.295000 0.615000 ; - RECT 3.025000 0.845000 3.255000 1.445000 ; - RECT 5.020000 0.295000 5.355000 0.615000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.100000 1.870000 0.460000 2.275000 ; - RECT 0.100000 2.275000 2.185000 2.295000 ; - RECT 0.100000 2.295000 2.985000 2.465000 ; - RECT 0.550000 0.085000 0.880000 0.445000 ; - RECT 1.465000 0.085000 1.795000 0.445000 ; - RECT 2.310000 1.795000 3.335000 1.845000 ; - RECT 2.310000 1.845000 5.400000 1.965000 ; - RECT 2.310000 1.965000 2.640000 2.060000 ; - RECT 2.465000 0.085000 2.795000 0.445000 ; - RECT 2.815000 2.135000 2.985000 2.295000 ; - RECT 3.155000 1.965000 5.400000 2.095000 ; - RECT 3.155000 2.095000 3.520000 2.465000 ; - RECT 3.690000 2.275000 4.020000 2.635000 ; - RECT 4.125000 0.085000 4.455000 0.445000 ; - RECT 4.190000 2.095000 5.400000 2.105000 ; - RECT 4.190000 2.105000 4.400000 2.465000 ; - RECT 4.570000 2.275000 4.900000 2.635000 ; - RECT 5.070000 2.105000 5.400000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__a2111oi_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__a2111oi_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__a2111oi_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.095000 1.020000 7.745000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.960000 1.020000 9.990000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.955000 1.020000 5.650000 1.275000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.055000 1.020000 3.745000 1.275000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.495000 1.020000 1.845000 1.275000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 2.009500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.615000 7.620000 0.785000 ; - RECT 0.145000 0.785000 0.320000 1.475000 ; - RECT 0.145000 1.475000 1.720000 1.655000 ; - RECT 0.530000 1.655000 1.720000 1.685000 ; - RECT 0.530000 1.685000 0.860000 2.085000 ; - RECT 0.615000 0.455000 0.790000 0.615000 ; - RECT 1.390000 1.685000 1.720000 2.085000 ; - RECT 1.460000 0.455000 1.650000 0.615000 ; - RECT 2.400000 0.455000 2.590000 0.615000 ; - RECT 3.260000 0.455000 3.510000 0.615000 ; - RECT 4.180000 0.455000 4.420000 0.615000 ; - RECT 5.090000 0.455000 5.275000 0.615000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.100000 1.835000 0.360000 2.255000 ; - RECT 0.100000 2.255000 3.870000 2.445000 ; - RECT 0.115000 0.085000 0.445000 0.445000 ; - RECT 0.960000 0.085000 1.290000 0.445000 ; - RECT 1.030000 1.855000 1.220000 2.255000 ; - RECT 1.820000 0.085000 2.230000 0.445000 ; - RECT 1.890000 1.855000 2.080000 2.255000 ; - RECT 2.250000 1.475000 5.680000 1.655000 ; - RECT 2.250000 1.655000 3.440000 1.685000 ; - RECT 2.250000 1.685000 2.580000 2.085000 ; - RECT 2.750000 1.855000 2.940000 2.255000 ; - RECT 2.760000 0.085000 3.090000 0.445000 ; - RECT 3.110000 1.685000 3.440000 2.085000 ; - RECT 3.610000 1.835000 3.870000 2.255000 ; - RECT 3.680000 0.085000 4.010000 0.445000 ; - RECT 4.060000 1.835000 4.320000 2.255000 ; - RECT 4.060000 2.255000 5.180000 2.275000 ; - RECT 4.060000 2.275000 6.050000 2.445000 ; - RECT 4.490000 1.655000 5.680000 1.685000 ; - RECT 4.490000 1.685000 4.820000 2.085000 ; - RECT 4.590000 0.085000 4.920000 0.445000 ; - RECT 4.990000 1.855000 5.180000 2.255000 ; - RECT 5.350000 1.685000 5.680000 2.085000 ; - RECT 5.445000 0.085000 5.780000 0.445000 ; - RECT 5.860000 1.445000 9.770000 1.615000 ; - RECT 5.860000 1.615000 6.050000 2.275000 ; - RECT 5.980000 0.275000 8.075000 0.445000 ; - RECT 6.220000 1.785000 6.550000 2.635000 ; - RECT 6.720000 1.615000 6.910000 2.315000 ; - RECT 7.080000 1.805000 7.410000 2.635000 ; - RECT 7.580000 1.615000 9.770000 1.665000 ; - RECT 7.580000 1.665000 7.910000 2.315000 ; - RECT 7.885000 0.445000 8.075000 0.615000 ; - RECT 7.885000 0.615000 9.865000 0.785000 ; - RECT 8.080000 1.895000 8.410000 2.635000 ; - RECT 8.245000 0.085000 8.575000 0.445000 ; - RECT 8.580000 1.665000 9.770000 1.670000 ; - RECT 8.580000 1.670000 8.840000 2.290000 ; - RECT 8.745000 0.300000 8.935000 0.615000 ; - RECT 9.030000 1.915000 9.360000 2.635000 ; - RECT 9.105000 0.085000 9.435000 0.445000 ; - RECT 9.530000 1.670000 9.770000 2.260000 ; - RECT 9.605000 0.290000 9.865000 0.615000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__a2111oi_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.185000 0.430000 1.955000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.940000 1.080000 1.270000 1.615000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.280900 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.560000 0.255000 2.215000 0.525000 ; - RECT 1.790000 1.835000 2.215000 2.465000 ; - RECT 1.950000 0.525000 2.215000 1.835000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.160000 2.175000 0.430000 2.635000 ; - RECT 0.185000 0.280000 0.490000 0.695000 ; - RECT 0.185000 0.695000 1.780000 0.910000 ; - RECT 0.185000 0.910000 0.770000 0.950000 ; - RECT 0.600000 0.950000 0.770000 2.135000 ; - RECT 0.600000 2.135000 0.865000 2.465000 ; - RECT 0.950000 0.085000 1.390000 0.525000 ; - RECT 1.110000 1.835000 1.620000 2.635000 ; - RECT 1.450000 0.910000 1.780000 1.435000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__and2_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.075000 0.775000 1.325000 ; - RECT 0.100000 1.325000 0.365000 1.685000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.995000 1.075000 1.335000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.657000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.655000 0.255000 2.215000 0.545000 ; - RECT 1.755000 1.915000 2.215000 2.465000 ; - RECT 1.965000 0.545000 2.215000 1.915000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.285000 0.355000 0.615000 0.715000 ; - RECT 0.285000 0.715000 1.675000 0.905000 ; - RECT 0.285000 1.965000 0.565000 2.635000 ; - RECT 0.735000 1.575000 1.675000 1.745000 ; - RECT 0.735000 1.745000 1.035000 2.295000 ; - RECT 1.235000 0.085000 1.485000 0.545000 ; - RECT 1.235000 1.915000 1.565000 2.635000 ; - RECT 1.505000 0.905000 1.675000 0.995000 ; - RECT 1.505000 0.995000 1.795000 1.325000 ; - RECT 1.505000 1.325000 1.675000 1.575000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__and2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.775000 1.325000 ; - RECT 0.085000 1.325000 0.400000 1.765000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.005000 1.075000 1.335000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.643500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.665000 0.255000 2.215000 0.545000 ; - RECT 1.765000 1.915000 2.215000 2.465000 ; - RECT 1.965000 0.545000 2.215000 1.915000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.285000 0.355000 0.615000 0.715000 ; - RECT 0.285000 0.715000 1.675000 0.905000 ; - RECT 0.285000 1.965000 0.565000 2.635000 ; - RECT 0.735000 1.575000 1.675000 1.745000 ; - RECT 0.735000 1.745000 1.035000 2.295000 ; - RECT 1.245000 0.085000 1.495000 0.545000 ; - RECT 1.245000 1.915000 1.575000 2.635000 ; - RECT 1.505000 0.905000 1.675000 0.995000 ; - RECT 1.505000 0.995000 1.795000 1.325000 ; - RECT 1.505000 1.325000 1.675000 1.575000 ; - RECT 2.385000 0.085000 2.675000 0.885000 ; - RECT 2.385000 1.495000 2.675000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__and2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 0.995000 0.435000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.995000 0.980000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 0.515000 1.720000 0.615000 ; - RECT 1.530000 0.615000 3.135000 0.845000 ; - RECT 1.530000 1.535000 3.135000 1.760000 ; - RECT 1.530000 1.760000 1.720000 2.465000 ; - RECT 2.390000 0.255000 2.580000 0.615000 ; - RECT 2.390000 1.760000 3.135000 1.765000 ; - RECT 2.390000 1.765000 2.580000 2.465000 ; - RECT 2.855000 0.845000 3.135000 1.535000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.095000 0.255000 0.425000 0.615000 ; - RECT 0.095000 0.615000 1.360000 0.805000 ; - RECT 0.095000 1.880000 0.425000 2.635000 ; - RECT 0.605000 1.580000 1.360000 1.750000 ; - RECT 0.605000 1.750000 0.785000 2.465000 ; - RECT 0.955000 0.085000 1.285000 0.445000 ; - RECT 0.990000 1.935000 1.320000 2.635000 ; - RECT 1.150000 0.805000 1.360000 1.020000 ; - RECT 1.150000 1.020000 2.685000 1.355000 ; - RECT 1.150000 1.355000 1.360000 1.580000 ; - RECT 1.890000 0.085000 2.220000 0.445000 ; - RECT 1.890000 1.935000 2.220000 2.635000 ; - RECT 2.750000 0.085000 3.080000 0.445000 ; - RECT 2.750000 1.935000 3.080000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__and2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.765000 0.445000 1.615000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 1.645000 2.175000 1.955000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.350000 1.580000 2.655000 2.365000 ; - RECT 2.415000 0.255000 2.655000 0.775000 ; - RECT 2.480000 0.775000 2.655000 1.580000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.590000 ; - RECT 0.175000 1.785000 0.850000 2.015000 ; - RECT 0.175000 2.015000 0.345000 2.445000 ; - RECT 0.515000 2.185000 0.845000 2.635000 ; - RECT 0.595000 0.280000 0.835000 0.655000 ; - RECT 0.615000 0.655000 0.835000 0.805000 ; - RECT 0.615000 0.805000 1.150000 1.135000 ; - RECT 0.615000 1.135000 0.850000 1.785000 ; - RECT 1.020000 1.305000 2.305000 1.325000 ; - RECT 1.020000 1.325000 1.880000 1.475000 ; - RECT 1.020000 1.475000 1.305000 2.420000 ; - RECT 1.115000 0.270000 1.285000 0.415000 ; - RECT 1.115000 0.415000 1.490000 0.610000 ; - RECT 1.320000 0.610000 1.490000 0.945000 ; - RECT 1.320000 0.945000 2.305000 1.305000 ; - RECT 1.485000 2.165000 2.170000 2.635000 ; - RECT 1.850000 0.085000 2.245000 0.580000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__and2b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.765000 0.450000 1.615000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.505000 1.645000 2.200000 1.955000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.375000 1.580000 2.680000 2.365000 ; - RECT 2.445000 0.255000 2.680000 0.775000 ; - RECT 2.505000 0.775000 2.680000 1.580000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.590000 ; - RECT 0.175000 1.785000 0.855000 2.015000 ; - RECT 0.175000 2.015000 0.345000 2.445000 ; - RECT 0.515000 2.185000 0.845000 2.635000 ; - RECT 0.595000 0.280000 0.835000 0.655000 ; - RECT 0.620000 0.655000 0.835000 0.805000 ; - RECT 0.620000 0.805000 1.175000 1.135000 ; - RECT 0.620000 1.135000 0.855000 1.785000 ; - RECT 1.045000 1.305000 2.335000 1.325000 ; - RECT 1.045000 1.325000 1.905000 1.475000 ; - RECT 1.045000 1.475000 1.330000 2.420000 ; - RECT 1.115000 0.270000 1.285000 0.415000 ; - RECT 1.115000 0.415000 1.515000 0.610000 ; - RECT 1.345000 0.610000 1.515000 0.945000 ; - RECT 1.345000 0.945000 2.335000 1.305000 ; - RECT 1.510000 2.165000 2.195000 2.635000 ; - RECT 1.875000 0.085000 2.275000 0.580000 ; - RECT 2.865000 0.085000 3.135000 0.720000 ; - RECT 2.865000 1.680000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__and2b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and2b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and2b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.900000 0.625000 3.155000 0.995000 ; - RECT 2.900000 0.995000 3.205000 1.325000 ; - RECT 2.900000 1.325000 3.155000 1.745000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 0.995000 0.975000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.934000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.485000 1.535000 2.730000 1.745000 ; - RECT 1.525000 0.495000 1.715000 0.615000 ; - RECT 1.525000 0.615000 2.730000 0.825000 ; - RECT 2.440000 0.825000 2.730000 1.535000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.615000 ; - RECT 0.090000 0.615000 1.355000 0.805000 ; - RECT 0.090000 2.255000 0.425000 2.635000 ; - RECT 0.165000 0.995000 0.425000 1.325000 ; - RECT 0.165000 1.325000 0.335000 1.915000 ; - RECT 0.165000 1.915000 3.505000 2.085000 ; - RECT 0.515000 1.500000 1.315000 1.745000 ; - RECT 0.955000 0.085000 1.285000 0.445000 ; - RECT 0.990000 2.275000 1.320000 2.635000 ; - RECT 1.110000 1.435000 1.320000 1.485000 ; - RECT 1.110000 1.485000 1.315000 1.500000 ; - RECT 1.145000 0.805000 1.355000 0.995000 ; - RECT 1.145000 0.995000 2.260000 1.355000 ; - RECT 1.145000 1.355000 1.320000 1.435000 ; - RECT 1.885000 0.085000 2.215000 0.445000 ; - RECT 1.905000 2.275000 2.235000 2.635000 ; - RECT 2.745000 0.085000 3.075000 0.445000 ; - RECT 2.745000 2.275000 3.075000 2.635000 ; - RECT 3.330000 0.495000 3.500000 0.675000 ; - RECT 3.330000 0.675000 3.545000 0.845000 ; - RECT 3.335000 1.530000 3.545000 1.700000 ; - RECT 3.335000 1.700000 3.505000 1.915000 ; - RECT 3.375000 0.845000 3.545000 1.530000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__and2b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.635000 0.635000 1.020000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.865000 2.125000 1.345000 2.465000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.145000 0.305000 1.365000 0.790000 ; - RECT 1.145000 0.790000 1.475000 1.215000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.940000 1.765000 2.215000 2.465000 ; - RECT 1.955000 0.255000 2.215000 0.735000 ; - RECT 2.045000 0.735000 2.215000 1.765000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.295000 0.975000 0.465000 ; - RECT 0.085000 1.190000 0.975000 1.260000 ; - RECT 0.085000 1.260000 0.980000 1.285000 ; - RECT 0.085000 1.285000 0.990000 1.300000 ; - RECT 0.085000 1.300000 0.995000 1.315000 ; - RECT 0.085000 1.315000 1.005000 1.320000 ; - RECT 0.085000 1.320000 1.010000 1.330000 ; - RECT 0.085000 1.330000 1.015000 1.340000 ; - RECT 0.085000 1.340000 1.025000 1.345000 ; - RECT 0.085000 1.345000 1.035000 1.355000 ; - RECT 0.085000 1.355000 1.045000 1.360000 ; - RECT 0.085000 1.360000 0.345000 1.810000 ; - RECT 0.085000 1.980000 0.700000 2.080000 ; - RECT 0.085000 2.080000 0.690000 2.635000 ; - RECT 0.515000 1.710000 0.845000 1.955000 ; - RECT 0.515000 1.955000 0.700000 1.980000 ; - RECT 0.710000 1.360000 1.045000 1.365000 ; - RECT 0.710000 1.365000 1.060000 1.370000 ; - RECT 0.710000 1.370000 1.075000 1.380000 ; - RECT 0.710000 1.380000 1.100000 1.385000 ; - RECT 0.710000 1.385000 1.875000 1.390000 ; - RECT 0.740000 1.390000 1.875000 1.425000 ; - RECT 0.775000 1.425000 1.875000 1.450000 ; - RECT 0.805000 0.465000 0.975000 1.190000 ; - RECT 0.805000 1.450000 1.875000 1.480000 ; - RECT 0.825000 1.480000 1.875000 1.510000 ; - RECT 0.845000 1.510000 1.875000 1.540000 ; - RECT 0.915000 1.540000 1.875000 1.550000 ; - RECT 0.940000 1.550000 1.875000 1.560000 ; - RECT 0.960000 1.560000 1.875000 1.575000 ; - RECT 0.980000 1.575000 1.875000 1.590000 ; - RECT 0.985000 1.590000 1.770000 1.600000 ; - RECT 1.000000 1.600000 1.770000 1.635000 ; - RECT 1.015000 1.635000 1.770000 1.885000 ; - RECT 1.515000 2.090000 1.770000 2.635000 ; - RECT 1.535000 0.085000 1.785000 0.625000 ; - RECT 1.645000 0.990000 1.875000 1.385000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__and3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.470000 1.245000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.895000 2.125000 1.370000 2.465000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 0.305000 1.295000 0.750000 ; - RECT 1.065000 0.750000 1.475000 1.245000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.970000 1.795000 2.245000 2.465000 ; - RECT 1.980000 0.255000 2.230000 0.715000 ; - RECT 2.060000 0.715000 2.230000 0.925000 ; - RECT 2.060000 0.925000 2.675000 1.445000 ; - RECT 2.075000 1.445000 2.245000 1.795000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 2.130000 0.715000 2.635000 ; - RECT 0.100000 1.425000 1.890000 1.595000 ; - RECT 0.100000 1.595000 0.355000 1.960000 ; - RECT 0.105000 0.305000 0.895000 0.570000 ; - RECT 0.525000 1.765000 0.855000 1.955000 ; - RECT 0.525000 1.955000 0.715000 2.130000 ; - RECT 0.640000 0.570000 0.895000 1.425000 ; - RECT 1.080000 1.595000 1.330000 1.890000 ; - RECT 1.475000 0.085000 1.805000 0.580000 ; - RECT 1.555000 1.790000 1.770000 2.635000 ; - RECT 1.660000 0.995000 1.890000 1.425000 ; - RECT 2.400000 0.085000 2.675000 0.745000 ; - RECT 2.415000 1.625000 2.675000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__and3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.115000 0.995000 0.875000 1.340000 ; - RECT 0.115000 1.340000 0.365000 2.335000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 0.745000 1.355000 1.340000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.995000 1.900000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.450000 0.515000 2.640000 0.615000 ; - RECT 2.450000 0.615000 4.055000 0.845000 ; - RECT 2.450000 1.535000 4.055000 1.760000 ; - RECT 2.450000 1.760000 2.640000 2.465000 ; - RECT 3.310000 0.255000 3.500000 0.615000 ; - RECT 3.310000 1.760000 4.055000 1.765000 ; - RECT 3.310000 1.765000 3.500000 2.465000 ; - RECT 3.775000 0.845000 4.055000 1.535000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.465000 0.255000 0.800000 0.375000 ; - RECT 0.465000 0.375000 1.725000 0.565000 ; - RECT 0.465000 0.565000 0.800000 0.805000 ; - RECT 0.545000 1.580000 2.280000 1.750000 ; - RECT 0.545000 1.750000 0.725000 2.465000 ; - RECT 0.895000 1.935000 1.345000 2.635000 ; - RECT 1.520000 1.750000 1.700000 2.465000 ; - RECT 1.535000 0.565000 1.725000 0.615000 ; - RECT 1.535000 0.615000 2.280000 0.805000 ; - RECT 1.905000 0.085000 2.235000 0.445000 ; - RECT 1.910000 1.935000 2.240000 2.635000 ; - RECT 2.070000 0.805000 2.280000 1.020000 ; - RECT 2.070000 1.020000 3.605000 1.355000 ; - RECT 2.070000 1.355000 2.280000 1.580000 ; - RECT 2.810000 0.085000 3.140000 0.445000 ; - RECT 2.810000 1.935000 3.140000 2.635000 ; - RECT 3.670000 0.085000 4.000000 0.445000 ; - RECT 3.670000 1.935000 4.000000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__and3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.955000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.790000 2.125000 2.265000 2.465000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.305000 2.185000 0.725000 ; - RECT 1.985000 0.725000 2.395000 1.245000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.860000 1.765000 3.135000 2.465000 ; - RECT 2.875000 0.255000 3.135000 0.735000 ; - RECT 2.965000 0.735000 3.135000 1.765000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.905000 ; - RECT 0.085000 2.125000 0.345000 2.635000 ; - RECT 0.515000 0.485000 0.845000 0.905000 ; - RECT 0.595000 0.905000 0.845000 0.995000 ; - RECT 0.595000 0.995000 1.390000 1.245000 ; - RECT 0.595000 1.245000 0.765000 2.465000 ; - RECT 1.005000 1.425000 2.795000 1.595000 ; - RECT 1.005000 1.595000 1.255000 1.960000 ; - RECT 1.005000 2.130000 1.620000 2.635000 ; - RECT 1.025000 0.305000 1.815000 0.570000 ; - RECT 1.425000 1.765000 1.755000 1.955000 ; - RECT 1.425000 1.955000 1.620000 2.130000 ; - RECT 1.560000 0.570000 1.815000 1.425000 ; - RECT 1.975000 1.595000 2.690000 1.890000 ; - RECT 2.375000 0.085000 2.705000 0.545000 ; - RECT 2.435000 2.090000 2.650000 2.635000 ; - RECT 2.565000 0.995000 2.795000 1.425000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__and3b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.745000 0.410000 1.325000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.815000 2.125000 2.290000 2.465000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.010000 0.305000 2.220000 0.765000 ; - RECT 2.010000 0.765000 2.420000 1.245000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.875000 1.795000 3.160000 2.465000 ; - RECT 2.915000 0.255000 3.160000 0.715000 ; - RECT 2.990000 0.715000 3.160000 0.925000 ; - RECT 2.990000 0.925000 3.595000 1.445000 ; - RECT 2.990000 1.445000 3.160000 1.795000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.085000 0.355000 0.575000 ; - RECT 0.085000 1.575000 0.400000 2.635000 ; - RECT 0.580000 0.305000 0.855000 1.015000 ; - RECT 0.580000 1.015000 1.415000 1.245000 ; - RECT 0.580000 1.245000 0.855000 1.905000 ; - RECT 1.030000 2.130000 1.645000 2.635000 ; - RECT 1.050000 1.425000 2.820000 1.595000 ; - RECT 1.050000 1.595000 1.285000 1.960000 ; - RECT 1.055000 0.305000 1.840000 0.570000 ; - RECT 1.455000 1.765000 1.785000 1.955000 ; - RECT 1.455000 1.955000 1.645000 2.130000 ; - RECT 1.585000 0.570000 1.840000 1.425000 ; - RECT 2.010000 1.595000 2.200000 1.890000 ; - RECT 2.410000 0.085000 2.740000 0.580000 ; - RECT 2.460000 1.790000 2.675000 2.635000 ; - RECT 2.590000 0.995000 2.820000 1.425000 ; - RECT 3.330000 0.085000 3.595000 0.745000 ; - RECT 3.330000 1.625000 3.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__and3b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and3b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and3b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.715000 0.615000 3.995000 1.705000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.020000 0.725000 1.235000 1.340000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.995000 1.715000 1.340000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.934000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.225000 1.535000 3.535000 1.705000 ; - RECT 2.285000 0.515000 2.475000 0.615000 ; - RECT 2.285000 0.615000 3.535000 0.845000 ; - RECT 3.145000 0.255000 3.335000 0.615000 ; - RECT 3.270000 0.845000 3.535000 1.535000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.150000 0.255000 0.635000 0.355000 ; - RECT 0.150000 0.355000 1.600000 0.545000 ; - RECT 0.150000 0.545000 0.635000 0.805000 ; - RECT 0.150000 0.805000 0.370000 1.495000 ; - RECT 0.150000 1.495000 0.510000 2.165000 ; - RECT 0.540000 0.995000 0.850000 1.325000 ; - RECT 0.680000 1.325000 0.850000 1.875000 ; - RECT 0.680000 1.875000 4.445000 2.105000 ; - RECT 0.730000 2.275000 1.180000 2.635000 ; - RECT 1.280000 1.525000 2.055000 1.695000 ; - RECT 1.420000 0.545000 1.600000 0.615000 ; - RECT 1.420000 0.615000 2.115000 0.805000 ; - RECT 1.745000 2.275000 2.075000 2.635000 ; - RECT 1.780000 0.085000 2.110000 0.445000 ; - RECT 1.885000 0.805000 2.115000 1.020000 ; - RECT 1.885000 1.020000 3.100000 1.355000 ; - RECT 1.885000 1.355000 2.055000 1.525000 ; - RECT 2.645000 0.085000 2.975000 0.445000 ; - RECT 2.645000 2.275000 2.980000 2.635000 ; - RECT 3.505000 0.085000 3.835000 0.445000 ; - RECT 3.505000 2.275000 3.835000 2.635000 ; - RECT 4.165000 0.425000 4.445000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__and3b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.325000 2.075000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.885000 0.360000 1.235000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 0.355000 1.715000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.895000 0.355000 2.175000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.795000 0.295000 3.135000 0.805000 ; - RECT 2.795000 2.205000 3.135000 2.465000 ; - RECT 2.875000 0.805000 3.135000 2.205000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 2.255000 0.425000 2.635000 ; - RECT 0.170000 0.255000 0.665000 0.585000 ; - RECT 0.495000 0.585000 0.665000 1.495000 ; - RECT 0.495000 1.495000 2.685000 1.665000 ; - RECT 0.595000 1.665000 0.845000 2.465000 ; - RECT 1.065000 1.915000 1.395000 2.635000 ; - RECT 1.580000 1.665000 1.830000 2.465000 ; - RECT 2.295000 1.835000 2.625000 2.635000 ; - RECT 2.355000 0.085000 2.625000 0.885000 ; - RECT 2.370000 1.075000 2.700000 1.325000 ; - RECT 2.370000 1.325000 2.685000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__and4_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 0.755000 0.330000 2.075000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.890000 0.420000 1.245000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.420000 0.415000 1.720000 1.305000 ; - RECT 1.420000 1.305000 1.590000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.900000 0.415000 2.160000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.544500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 0.295000 3.065000 0.340000 ; - RECT 2.735000 0.340000 3.070000 0.805000 ; - RECT 2.735000 1.495000 3.070000 2.465000 ; - RECT 2.895000 0.805000 3.070000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.095000 2.255000 0.425000 2.635000 ; - RECT 0.175000 0.255000 0.670000 0.585000 ; - RECT 0.500000 0.585000 0.670000 1.495000 ; - RECT 0.500000 1.495000 2.555000 1.665000 ; - RECT 0.600000 1.665000 0.850000 2.465000 ; - RECT 1.070000 1.915000 1.400000 2.635000 ; - RECT 1.585000 1.665000 1.835000 2.465000 ; - RECT 2.235000 1.835000 2.565000 2.635000 ; - RECT 2.330000 0.085000 2.565000 0.890000 ; - RECT 2.330000 1.075000 2.725000 1.315000 ; - RECT 2.330000 1.315000 2.555000 1.495000 ; - RECT 3.245000 1.835000 3.575000 2.635000 ; - RECT 3.255000 0.085000 3.585000 0.810000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__and4_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 0.765000 0.330000 1.655000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.840000 0.995000 1.245000 1.325000 ; - RECT 0.890000 0.420000 1.245000 0.995000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 0.425000 1.700000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.905000 0.730000 2.155000 0.935000 ; - RECT 1.905000 0.935000 2.075000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.535000 0.255000 2.705000 0.640000 ; - RECT 2.535000 0.640000 4.050000 0.810000 ; - RECT 2.535000 1.795000 2.785000 2.465000 ; - RECT 2.615000 1.485000 4.050000 1.655000 ; - RECT 2.615000 1.655000 2.785000 1.795000 ; - RECT 3.375000 0.255000 3.545000 0.640000 ; - RECT 3.375000 1.655000 4.050000 1.745000 ; - RECT 3.375000 1.745000 3.545000 2.465000 ; - RECT 3.800000 0.810000 4.050000 1.485000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.105000 1.835000 0.385000 2.635000 ; - RECT 0.175000 0.255000 0.670000 0.585000 ; - RECT 0.500000 0.585000 0.670000 1.495000 ; - RECT 0.500000 1.495000 2.415000 1.665000 ; - RECT 0.555000 1.665000 0.765000 2.465000 ; - RECT 0.955000 1.935000 1.285000 2.635000 ; - RECT 1.455000 1.665000 1.645000 2.465000 ; - RECT 2.025000 0.085000 2.335000 0.550000 ; - RECT 2.025000 1.855000 2.355000 2.635000 ; - RECT 2.245000 1.105000 3.585000 1.305000 ; - RECT 2.245000 1.305000 2.415000 1.495000 ; - RECT 2.575000 1.075000 3.585000 1.105000 ; - RECT 2.875000 0.085000 3.205000 0.470000 ; - RECT 2.955000 1.835000 3.205000 2.635000 ; - RECT 3.715000 0.085000 4.045000 0.470000 ; - RECT 3.715000 1.915000 4.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__and4_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.450000 1.675000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.520000 0.420000 1.800000 1.695000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.025000 0.420000 2.295000 1.695000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.485000 0.665000 2.825000 1.695000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.255000 0.295000 3.590000 0.340000 ; - RECT 3.255000 0.340000 3.595000 0.805000 ; - RECT 3.335000 1.495000 3.595000 2.465000 ; - RECT 3.425000 0.805000 3.595000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.170000 0.255000 0.345000 0.655000 ; - RECT 0.170000 0.655000 0.800000 0.825000 ; - RECT 0.170000 1.845000 0.800000 2.015000 ; - RECT 0.170000 2.015000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.195000 0.845000 2.635000 ; - RECT 0.630000 0.825000 0.800000 0.995000 ; - RECT 0.630000 0.995000 0.980000 1.325000 ; - RECT 0.630000 1.325000 0.800000 1.845000 ; - RECT 1.090000 0.255000 1.320000 0.585000 ; - RECT 1.150000 0.585000 1.320000 1.875000 ; - RECT 1.150000 1.875000 3.165000 2.045000 ; - RECT 1.150000 2.045000 1.320000 2.465000 ; - RECT 1.555000 2.225000 2.225000 2.635000 ; - RECT 2.440000 2.045000 2.610000 2.465000 ; - RECT 2.755000 0.085000 3.085000 0.465000 ; - RECT 2.810000 2.225000 3.140000 2.635000 ; - RECT 2.995000 0.995000 3.255000 1.325000 ; - RECT 2.995000 1.325000 3.165000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__and4b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 0.740000 0.335000 1.630000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.420000 1.745000 1.745000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.960000 0.420000 2.275000 1.695000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 0.645000 2.775000 1.615000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.503250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.260000 0.255000 3.545000 0.640000 ; - RECT 3.260000 0.640000 4.055000 0.825000 ; - RECT 3.340000 1.535000 4.055000 1.745000 ; - RECT 3.340000 1.745000 3.545000 2.465000 ; - RECT 3.425000 0.825000 4.055000 1.535000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 0.175000 1.830000 0.805000 2.000000 ; - RECT 0.175000 2.000000 0.345000 2.465000 ; - RECT 0.515000 2.195000 0.845000 2.635000 ; - RECT 0.595000 0.255000 0.805000 0.585000 ; - RECT 0.635000 0.585000 0.805000 0.995000 ; - RECT 0.635000 0.995000 0.975000 1.325000 ; - RECT 0.635000 1.325000 0.805000 1.830000 ; - RECT 1.015000 1.660000 1.315000 1.915000 ; - RECT 1.015000 1.915000 3.165000 1.965000 ; - RECT 1.015000 1.965000 2.610000 2.085000 ; - RECT 1.015000 2.085000 1.185000 2.465000 ; - RECT 1.095000 0.255000 1.315000 0.585000 ; - RECT 1.145000 0.585000 1.315000 1.660000 ; - RECT 1.555000 2.255000 2.225000 2.635000 ; - RECT 2.440000 1.795000 3.165000 1.915000 ; - RECT 2.440000 2.085000 2.610000 2.465000 ; - RECT 2.760000 0.085000 3.090000 0.465000 ; - RECT 2.840000 2.195000 3.170000 2.635000 ; - RECT 2.995000 0.995000 3.255000 1.325000 ; - RECT 2.995000 1.325000 3.165000 1.795000 ; - RECT 3.715000 0.085000 4.050000 0.465000 ; - RECT 3.715000 1.915000 4.050000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__and4b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.440000 0.765000 0.790000 1.635000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.815000 0.735000 4.145000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.345000 0.755000 3.555000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.865000 0.995000 3.085000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.980000 0.650000 2.080000 0.820000 ; - RECT 0.980000 0.820000 1.260000 1.545000 ; - RECT 0.980000 1.545000 2.160000 1.715000 ; - RECT 1.070000 0.255000 1.240000 0.650000 ; - RECT 1.910000 0.255000 2.080000 0.650000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.585000 ; - RECT 0.085000 0.585000 0.260000 1.915000 ; - RECT 0.085000 1.915000 4.900000 2.085000 ; - RECT 0.085000 2.085000 0.345000 2.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 0.570000 0.085000 0.900000 0.470000 ; - RECT 1.410000 0.085000 1.740000 0.470000 ; - RECT 1.410000 2.255000 1.740000 2.635000 ; - RECT 1.440000 1.075000 2.550000 1.245000 ; - RECT 2.250000 2.255000 2.580000 2.635000 ; - RECT 2.285000 0.085000 2.615000 0.445000 ; - RECT 2.380000 0.615000 2.965000 0.785000 ; - RECT 2.380000 0.785000 2.550000 1.075000 ; - RECT 2.380000 1.245000 2.550000 1.545000 ; - RECT 2.380000 1.545000 4.545000 1.715000 ; - RECT 2.795000 0.300000 4.965000 0.470000 ; - RECT 2.795000 0.470000 2.965000 0.615000 ; - RECT 3.475000 2.255000 3.805000 2.635000 ; - RECT 4.390000 0.470000 4.965000 0.810000 ; - RECT 4.635000 2.255000 4.965000 2.635000 ; - RECT 4.730000 0.995000 4.900000 1.915000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__and4b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4bb_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4bb_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 1.625000 0.775000 1.955000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.765000 0.815000 0.945000 ; - RECT 0.605000 0.945000 1.225000 1.115000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.895000 0.415000 3.080000 0.995000 ; - RECT 2.895000 0.995000 3.125000 1.325000 ; - RECT 2.895000 1.325000 3.080000 1.635000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.350000 0.420000 3.545000 0.995000 ; - RECT 3.350000 0.995000 3.605000 1.325000 ; - RECT 3.350000 1.325000 3.545000 1.635000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.425400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.255000 0.255000 4.515000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.585000 ; - RECT 0.085000 0.585000 0.255000 1.285000 ; - RECT 0.085000 1.285000 1.215000 1.455000 ; - RECT 0.085000 1.455000 0.255000 2.135000 ; - RECT 0.085000 2.135000 0.345000 2.465000 ; - RECT 0.655000 0.085000 0.985000 0.465000 ; - RECT 0.655000 2.255000 0.985000 2.635000 ; - RECT 1.045000 1.455000 1.215000 1.575000 ; - RECT 1.045000 1.575000 1.625000 1.745000 ; - RECT 1.165000 0.255000 2.645000 0.425000 ; - RECT 1.165000 0.425000 1.565000 0.755000 ; - RECT 1.225000 1.915000 1.965000 2.085000 ; - RECT 1.225000 2.085000 1.415000 2.465000 ; - RECT 1.395000 0.755000 1.565000 1.235000 ; - RECT 1.395000 1.235000 1.965000 1.405000 ; - RECT 1.665000 2.255000 1.995000 2.635000 ; - RECT 1.755000 0.595000 2.305000 0.925000 ; - RECT 1.795000 1.405000 1.965000 1.915000 ; - RECT 2.135000 0.925000 2.305000 1.915000 ; - RECT 2.135000 1.915000 4.085000 2.085000 ; - RECT 2.205000 2.085000 2.375000 2.465000 ; - RECT 2.475000 0.425000 2.645000 1.325000 ; - RECT 2.570000 2.255000 2.900000 2.635000 ; - RECT 3.160000 2.085000 3.330000 2.465000 ; - RECT 3.755000 0.085000 4.085000 0.465000 ; - RECT 3.755000 2.255000 4.085000 2.635000 ; - RECT 3.915000 0.995000 4.085000 1.915000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__and4bb_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4bb_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4bb_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.995000 0.330000 1.635000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 0.765000 4.175000 1.305000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.910000 0.420000 3.175000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.350000 0.425000 3.655000 1.405000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.990000 1.545000 1.320000 1.715000 ; - RECT 1.015000 0.255000 1.240000 1.545000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.670000 0.805000 ; - RECT 0.175000 1.885000 1.925000 2.055000 ; - RECT 0.175000 2.055000 0.345000 2.465000 ; - RECT 0.500000 0.805000 0.670000 1.885000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 1.410000 0.085000 1.740000 0.465000 ; - RECT 1.415000 0.635000 2.405000 0.805000 ; - RECT 1.415000 0.805000 1.585000 1.325000 ; - RECT 1.490000 2.255000 2.160000 2.635000 ; - RECT 1.755000 0.995000 2.065000 1.325000 ; - RECT 1.755000 1.325000 1.925000 1.885000 ; - RECT 2.010000 0.255000 2.180000 0.635000 ; - RECT 2.235000 0.805000 2.405000 1.915000 ; - RECT 2.235000 1.915000 3.415000 2.085000 ; - RECT 2.395000 2.085000 2.565000 2.465000 ; - RECT 2.575000 1.400000 2.745000 1.575000 ; - RECT 2.575000 1.575000 3.755000 1.745000 ; - RECT 2.735000 2.255000 3.075000 2.635000 ; - RECT 3.245000 2.085000 3.415000 2.465000 ; - RECT 3.585000 1.745000 3.755000 1.915000 ; - RECT 3.585000 1.915000 4.515000 2.085000 ; - RECT 3.755000 2.255000 4.085000 2.635000 ; - RECT 3.835000 0.085000 4.085000 0.585000 ; - RECT 4.255000 0.255000 4.515000 0.585000 ; - RECT 4.255000 2.085000 4.515000 2.465000 ; - RECT 4.345000 0.585000 4.515000 1.915000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__and4bb_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__and4bb_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__and4bb_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.485000 0.995000 5.845000 1.620000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 0.765000 0.780000 1.635000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.250000 0.755000 3.545000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.680000 0.995000 3.080000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.960000 0.650000 2.080000 0.820000 ; - RECT 0.960000 0.820000 1.240000 1.545000 ; - RECT 0.960000 1.545000 2.160000 1.715000 ; - RECT 1.070000 0.255000 1.240000 0.650000 ; - RECT 1.910000 0.255000 2.080000 0.650000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.585000 ; - RECT 0.085000 0.585000 0.260000 1.915000 ; - RECT 0.085000 1.915000 4.490000 2.085000 ; - RECT 0.085000 2.085000 0.345000 2.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 0.570000 0.085000 0.900000 0.470000 ; - RECT 1.410000 0.085000 1.740000 0.470000 ; - RECT 1.410000 1.075000 2.500000 1.245000 ; - RECT 1.410000 2.255000 1.740000 2.635000 ; - RECT 2.250000 2.255000 2.580000 2.635000 ; - RECT 2.270000 0.085000 2.600000 0.445000 ; - RECT 2.330000 0.615000 2.940000 0.785000 ; - RECT 2.330000 0.785000 2.500000 1.075000 ; - RECT 2.330000 1.245000 2.500000 1.545000 ; - RECT 2.330000 1.545000 4.150000 1.715000 ; - RECT 2.770000 0.300000 4.610000 0.470000 ; - RECT 2.770000 0.470000 2.940000 0.615000 ; - RECT 3.330000 2.255000 3.660000 2.635000 ; - RECT 3.730000 0.995000 3.900000 1.155000 ; - RECT 3.730000 1.155000 4.490000 1.325000 ; - RECT 4.255000 0.470000 4.610000 0.810000 ; - RECT 4.320000 1.325000 4.490000 1.915000 ; - RECT 4.360000 2.255000 5.370000 2.635000 ; - RECT 4.950000 0.655000 5.805000 0.825000 ; - RECT 4.950000 0.825000 5.120000 1.915000 ; - RECT 4.950000 1.915000 5.805000 2.085000 ; - RECT 4.975000 0.085000 5.305000 0.465000 ; - RECT 5.635000 0.255000 5.805000 0.655000 ; - RECT 5.635000 2.085000 5.805000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__and4bb_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.196500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.985000 0.445000 1.355000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.340600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.025000 1.560000 1.295000 2.465000 ; - RECT 1.035000 0.255000 1.295000 0.760000 ; - RECT 1.115000 0.760000 1.295000 1.560000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.155000 -0.085000 0.325000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.165000 1.535000 0.840000 1.705000 ; - RECT 0.165000 1.705000 0.345000 2.465000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.525000 0.085000 0.855000 0.465000 ; - RECT 0.525000 1.875000 0.855000 2.635000 ; - RECT 0.670000 0.805000 0.840000 1.060000 ; - RECT 0.670000 1.060000 0.945000 1.390000 ; - RECT 0.670000 1.390000 0.840000 1.535000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__buf_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.440000 1.355000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.060000 0.255000 1.315000 0.830000 ; - RECT 1.060000 1.560000 1.315000 2.465000 ; - RECT 1.145000 0.830000 1.315000 1.560000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.175000 0.255000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.890000 0.805000 ; - RECT 0.175000 1.535000 0.890000 1.705000 ; - RECT 0.175000 1.705000 0.345000 2.465000 ; - RECT 0.560000 0.085000 0.890000 0.465000 ; - RECT 0.560000 1.875000 0.890000 2.635000 ; - RECT 0.720000 0.805000 0.890000 0.995000 ; - RECT 0.720000 0.995000 0.975000 1.325000 ; - RECT 0.720000 1.325000 0.890000 1.535000 ; - RECT 1.490000 0.085000 1.750000 0.925000 ; - RECT 1.490000 1.485000 1.750000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__buf_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.470000 1.315000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.015000 0.255000 1.185000 0.735000 ; - RECT 1.015000 0.735000 2.025000 0.905000 ; - RECT 1.015000 1.445000 2.025000 1.615000 ; - RECT 1.015000 1.615000 1.185000 2.465000 ; - RECT 1.530000 0.905000 2.025000 1.445000 ; - RECT 1.855000 0.255000 2.025000 0.735000 ; - RECT 1.855000 1.615000 2.025000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 1.485000 0.810000 1.655000 ; - RECT 0.095000 1.655000 0.425000 2.465000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 0.810000 0.905000 ; - RECT 0.525000 0.085000 0.765000 0.565000 ; - RECT 0.595000 1.835000 0.835000 2.635000 ; - RECT 0.640000 0.905000 0.810000 1.075000 ; - RECT 0.640000 1.075000 1.140000 1.245000 ; - RECT 0.640000 1.245000 0.810000 1.485000 ; - RECT 1.355000 0.085000 1.685000 0.565000 ; - RECT 1.355000 1.835000 1.685000 2.635000 ; - RECT 2.195000 0.085000 2.525000 0.885000 ; - RECT 2.195000 1.485000 2.525000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__buf_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_6 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_6 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.280000 1.075000 1.185000 1.315000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.336500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.255000 1.865000 0.735000 ; - RECT 1.695000 0.735000 3.545000 0.905000 ; - RECT 1.695000 1.445000 3.545000 1.615000 ; - RECT 1.695000 1.615000 1.865000 2.465000 ; - RECT 2.210000 0.905000 3.545000 1.445000 ; - RECT 2.535000 0.255000 2.705000 0.735000 ; - RECT 2.535000 1.615000 2.705000 2.465000 ; - RECT 3.375000 0.255000 3.545000 0.735000 ; - RECT 3.375000 1.615000 3.545000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.435000 0.085000 0.605000 0.565000 ; - RECT 0.435000 1.485000 0.605000 2.635000 ; - RECT 0.775000 0.255000 1.105000 0.735000 ; - RECT 0.775000 0.735000 1.525000 0.905000 ; - RECT 0.775000 1.485000 1.525000 1.655000 ; - RECT 0.775000 1.655000 1.105000 2.465000 ; - RECT 1.275000 0.085000 1.445000 0.565000 ; - RECT 1.275000 1.835000 1.515000 2.635000 ; - RECT 1.355000 0.905000 1.525000 1.075000 ; - RECT 1.355000 1.075000 1.825000 1.245000 ; - RECT 1.355000 1.245000 1.525000 1.485000 ; - RECT 2.035000 0.085000 2.365000 0.565000 ; - RECT 2.035000 1.835000 2.365000 2.635000 ; - RECT 2.875000 0.085000 3.205000 0.565000 ; - RECT 2.875000 1.835000 3.205000 2.635000 ; - RECT 3.715000 0.085000 4.045000 0.885000 ; - RECT 3.715000 1.485000 4.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__buf_6 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.742500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.140000 1.075000 1.240000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.855000 0.255000 2.025000 0.735000 ; - RECT 1.855000 0.735000 4.545000 0.905000 ; - RECT 1.855000 1.445000 4.545000 1.615000 ; - RECT 1.855000 1.615000 2.025000 2.465000 ; - RECT 2.695000 0.255000 2.865000 0.735000 ; - RECT 2.695000 1.615000 2.865000 2.465000 ; - RECT 3.535000 0.255000 3.705000 0.735000 ; - RECT 3.535000 1.615000 3.705000 2.465000 ; - RECT 4.290000 0.905000 4.545000 1.445000 ; - RECT 4.375000 0.255000 4.545000 0.735000 ; - RECT 4.375000 1.615000 4.545000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.095000 1.445000 1.595000 1.615000 ; - RECT 0.095000 1.615000 0.425000 2.465000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 1.595000 0.905000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.595000 1.835000 0.765000 2.635000 ; - RECT 0.935000 1.615000 1.265000 2.465000 ; - RECT 1.015000 0.260000 1.185000 0.735000 ; - RECT 1.355000 0.085000 1.685000 0.565000 ; - RECT 1.420000 0.905000 1.595000 1.075000 ; - RECT 1.420000 1.075000 4.045000 1.245000 ; - RECT 1.420000 1.245000 1.595000 1.445000 ; - RECT 1.435000 1.835000 1.605000 2.635000 ; - RECT 2.195000 0.085000 2.525000 0.565000 ; - RECT 2.195000 1.835000 2.525000 2.635000 ; - RECT 3.035000 0.085000 3.365000 0.565000 ; - RECT 3.035000 1.835000 3.365000 2.635000 ; - RECT 3.875000 0.085000 4.205000 0.565000 ; - RECT 3.875000 1.835000 4.205000 2.635000 ; - RECT 4.715000 0.085000 5.045000 0.885000 ; - RECT 4.715000 1.485000 5.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__buf_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_12 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_12 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 1.075000 1.660000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 2.673000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.275000 0.255000 2.445000 0.735000 ; - RECT 2.275000 0.735000 6.645000 0.905000 ; - RECT 2.275000 1.445000 6.645000 1.615000 ; - RECT 2.275000 1.615000 2.445000 2.465000 ; - RECT 3.115000 0.255000 3.285000 0.735000 ; - RECT 3.115000 1.615000 3.285000 2.465000 ; - RECT 3.955000 0.255000 4.125000 0.735000 ; - RECT 3.955000 1.615000 4.125000 2.465000 ; - RECT 4.710000 0.905000 6.645000 1.445000 ; - RECT 4.795000 0.255000 4.965000 0.735000 ; - RECT 4.795000 1.615000 4.965000 2.465000 ; - RECT 5.635000 0.255000 5.805000 0.735000 ; - RECT 5.635000 1.615000 5.805000 2.465000 ; - RECT 6.475000 0.255000 6.645000 0.735000 ; - RECT 6.475000 1.615000 6.645000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.570000 -0.085000 0.740000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.565000 ; - RECT 0.175000 1.835000 0.345000 2.635000 ; - RECT 0.515000 1.445000 2.015000 1.615000 ; - RECT 0.515000 1.615000 0.845000 2.465000 ; - RECT 0.595000 0.255000 0.765000 0.735000 ; - RECT 0.595000 0.735000 2.015000 0.905000 ; - RECT 0.935000 0.085000 1.265000 0.565000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.355000 1.615000 1.685000 2.465000 ; - RECT 1.435000 0.260000 1.605000 0.735000 ; - RECT 1.775000 0.085000 2.105000 0.565000 ; - RECT 1.840000 0.905000 2.015000 1.075000 ; - RECT 1.840000 1.075000 4.465000 1.245000 ; - RECT 1.840000 1.245000 2.015000 1.445000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.615000 0.085000 2.945000 0.565000 ; - RECT 2.615000 1.835000 2.945000 2.635000 ; - RECT 3.455000 0.085000 3.785000 0.565000 ; - RECT 3.455000 1.835000 3.785000 2.635000 ; - RECT 4.295000 0.085000 4.625000 0.565000 ; - RECT 4.295000 1.835000 4.625000 2.635000 ; - RECT 5.135000 0.085000 5.465000 0.565000 ; - RECT 5.135000 1.835000 5.465000 2.635000 ; - RECT 5.975000 0.085000 6.305000 0.565000 ; - RECT 5.975000 1.835000 6.305000 2.635000 ; - RECT 6.815000 0.085000 7.145000 0.885000 ; - RECT 6.815000 1.485000 7.145000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__buf_12 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__buf_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__buf_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.485000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 2.485000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 3.564000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.035000 0.255000 3.285000 0.260000 ; - RECT 3.035000 0.260000 3.365000 0.735000 ; - RECT 3.035000 0.735000 10.035000 0.905000 ; - RECT 3.035000 1.445000 10.035000 1.615000 ; - RECT 3.035000 1.615000 3.365000 2.465000 ; - RECT 3.875000 0.260000 4.205000 0.735000 ; - RECT 3.875000 1.615000 4.205000 2.465000 ; - RECT 3.955000 0.255000 4.125000 0.260000 ; - RECT 4.715000 0.260000 5.045000 0.735000 ; - RECT 4.715000 1.615000 5.045000 2.465000 ; - RECT 4.795000 0.255000 4.965000 0.260000 ; - RECT 5.555000 0.260000 5.885000 0.735000 ; - RECT 5.555000 1.615000 5.885000 2.465000 ; - RECT 6.395000 0.260000 6.725000 0.735000 ; - RECT 6.395000 1.615000 6.725000 2.465000 ; - RECT 7.235000 0.260000 7.565000 0.735000 ; - RECT 7.235000 1.615000 7.565000 2.465000 ; - RECT 8.075000 0.260000 8.405000 0.735000 ; - RECT 8.075000 1.615000 8.405000 2.465000 ; - RECT 8.915000 0.260000 9.245000 0.735000 ; - RECT 8.915000 1.615000 9.245000 2.465000 ; - RECT 9.655000 0.905000 10.035000 1.445000 ; - RECT 9.760000 0.365000 10.035000 0.735000 ; - RECT 9.760000 1.615000 10.035000 2.360000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.175000 0.085000 0.345000 0.905000 ; - RECT 0.175000 1.445000 0.345000 2.635000 ; - RECT 0.515000 0.260000 0.845000 0.735000 ; - RECT 0.515000 0.735000 2.865000 0.905000 ; - RECT 0.515000 1.445000 2.865000 1.615000 ; - RECT 0.515000 1.615000 0.845000 2.465000 ; - RECT 1.015000 0.085000 1.185000 0.565000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.355000 0.260000 1.685000 0.735000 ; - RECT 1.355000 1.615000 1.685000 2.465000 ; - RECT 1.855000 0.085000 2.025000 0.565000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.195000 0.260000 2.525000 0.735000 ; - RECT 2.195000 1.615000 2.525000 2.465000 ; - RECT 2.690000 0.905000 2.865000 1.075000 ; - RECT 2.690000 1.075000 9.410000 1.275000 ; - RECT 2.690000 1.275000 2.865000 1.445000 ; - RECT 2.695000 0.085000 2.865000 0.565000 ; - RECT 2.695000 1.835000 2.865000 2.635000 ; - RECT 3.535000 0.085000 3.705000 0.565000 ; - RECT 3.535000 1.835000 3.705000 2.635000 ; - RECT 4.375000 0.085000 4.545000 0.565000 ; - RECT 4.375000 1.835000 4.545000 2.635000 ; - RECT 5.215000 0.085000 5.385000 0.565000 ; - RECT 5.215000 1.835000 5.385000 2.635000 ; - RECT 6.055000 0.085000 6.225000 0.565000 ; - RECT 6.055000 1.835000 6.225000 2.635000 ; - RECT 6.895000 0.085000 7.065000 0.565000 ; - RECT 6.895000 1.835000 7.065000 2.635000 ; - RECT 7.735000 0.085000 7.905000 0.565000 ; - RECT 7.735000 1.835000 7.905000 2.635000 ; - RECT 8.575000 0.085000 8.745000 0.565000 ; - RECT 8.575000 1.835000 8.745000 2.635000 ; - RECT 9.415000 0.085000 9.585000 0.565000 ; - RECT 9.415000 1.835000 9.585000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__buf_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__bufbuf_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__bufbuf_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.440000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.230000 0.260000 3.560000 0.735000 ; - RECT 3.230000 0.735000 6.815000 0.905000 ; - RECT 3.230000 1.445000 6.815000 1.615000 ; - RECT 3.230000 1.615000 3.560000 2.465000 ; - RECT 4.070000 0.260000 4.400000 0.735000 ; - RECT 4.070000 1.615000 4.400000 2.465000 ; - RECT 4.910000 0.260000 5.240000 0.735000 ; - RECT 4.910000 1.615000 5.240000 2.465000 ; - RECT 5.750000 0.260000 6.080000 0.735000 ; - RECT 5.750000 1.615000 6.080000 2.465000 ; - RECT 6.435000 0.905000 6.815000 1.445000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.095000 0.260000 0.425000 0.735000 ; - RECT 0.095000 0.735000 0.780000 0.905000 ; - RECT 0.095000 1.445000 0.780000 1.615000 ; - RECT 0.095000 1.615000 0.425000 2.160000 ; - RECT 0.595000 0.085000 0.765000 0.565000 ; - RECT 0.595000 1.785000 0.765000 2.635000 ; - RECT 0.610000 0.905000 0.780000 0.995000 ; - RECT 0.610000 0.995000 1.040000 1.325000 ; - RECT 0.610000 1.325000 0.780000 1.445000 ; - RECT 1.000000 0.260000 1.380000 0.825000 ; - RECT 1.000000 1.545000 1.380000 2.465000 ; - RECT 1.210000 0.825000 1.380000 1.075000 ; - RECT 1.210000 1.075000 2.720000 1.275000 ; - RECT 1.210000 1.275000 1.380000 1.545000 ; - RECT 1.550000 0.260000 1.880000 0.735000 ; - RECT 1.550000 0.735000 3.060000 0.905000 ; - RECT 1.550000 1.445000 3.060000 1.615000 ; - RECT 1.550000 1.615000 1.880000 2.465000 ; - RECT 2.050000 0.085000 2.220000 0.565000 ; - RECT 2.050000 1.785000 2.220000 2.635000 ; - RECT 2.390000 0.260000 2.720000 0.735000 ; - RECT 2.390000 1.615000 2.720000 2.465000 ; - RECT 2.890000 0.085000 3.060000 0.565000 ; - RECT 2.890000 0.905000 3.060000 1.075000 ; - RECT 2.890000 1.075000 5.360000 1.275000 ; - RECT 2.890000 1.275000 3.060000 1.445000 ; - RECT 2.890000 1.785000 3.060000 2.635000 ; - RECT 3.730000 0.085000 3.900000 0.565000 ; - RECT 3.730000 1.835000 3.900000 2.635000 ; - RECT 4.570000 0.085000 4.740000 0.565000 ; - RECT 4.570000 1.835000 4.740000 2.635000 ; - RECT 5.410000 0.085000 5.580000 0.565000 ; - RECT 5.410000 1.835000 5.580000 2.635000 ; - RECT 6.250000 0.085000 6.420000 0.565000 ; - RECT 6.250000 1.835000 6.420000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - END -END sky130_fd_sc_hd__bufbuf_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__bufbuf_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__bufbuf_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.440000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 3.564000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.235000 0.255000 5.485000 0.260000 ; - RECT 5.235000 0.260000 5.565000 0.735000 ; - RECT 5.235000 0.735000 11.875000 0.905000 ; - RECT 5.235000 1.445000 11.875000 1.615000 ; - RECT 5.235000 1.615000 5.565000 2.465000 ; - RECT 6.075000 0.260000 6.405000 0.735000 ; - RECT 6.075000 1.615000 6.405000 2.465000 ; - RECT 6.155000 0.255000 6.325000 0.260000 ; - RECT 6.915000 0.260000 7.245000 0.735000 ; - RECT 6.915000 1.615000 7.245000 2.465000 ; - RECT 6.995000 0.255000 7.165000 0.260000 ; - RECT 7.755000 0.260000 8.085000 0.735000 ; - RECT 7.755000 1.615000 8.085000 2.465000 ; - RECT 8.595000 0.260000 8.925000 0.735000 ; - RECT 8.595000 1.615000 8.925000 2.465000 ; - RECT 9.435000 0.260000 9.765000 0.735000 ; - RECT 9.435000 1.615000 9.765000 2.465000 ; - RECT 10.275000 0.260000 10.605000 0.735000 ; - RECT 10.275000 1.615000 10.605000 2.465000 ; - RECT 11.115000 0.260000 11.445000 0.735000 ; - RECT 11.115000 1.615000 11.445000 2.465000 ; - RECT 11.620000 0.905000 11.875000 1.445000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.150000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.175000 0.085000 0.345000 0.905000 ; - RECT 0.175000 1.445000 0.345000 2.635000 ; - RECT 0.515000 0.260000 0.845000 0.905000 ; - RECT 0.515000 1.445000 0.845000 2.465000 ; - RECT 0.610000 0.905000 0.845000 1.075000 ; - RECT 0.610000 1.075000 2.205000 1.275000 ; - RECT 0.610000 1.275000 0.845000 1.445000 ; - RECT 1.035000 0.260000 1.365000 0.735000 ; - RECT 1.035000 0.735000 2.545000 0.905000 ; - RECT 1.035000 1.445000 2.545000 1.615000 ; - RECT 1.035000 1.615000 1.365000 2.465000 ; - RECT 1.535000 0.085000 1.705000 0.565000 ; - RECT 1.535000 1.785000 1.705000 2.635000 ; - RECT 1.875000 0.260000 2.205000 0.735000 ; - RECT 1.875000 1.615000 2.205000 2.465000 ; - RECT 2.375000 0.085000 2.545000 0.565000 ; - RECT 2.375000 0.905000 2.545000 1.075000 ; - RECT 2.375000 1.075000 4.685000 1.275000 ; - RECT 2.375000 1.275000 2.545000 1.445000 ; - RECT 2.375000 1.785000 2.545000 2.635000 ; - RECT 2.715000 0.260000 3.045000 0.735000 ; - RECT 2.715000 0.735000 5.065000 0.905000 ; - RECT 2.715000 1.445000 5.065000 1.615000 ; - RECT 2.715000 1.615000 3.045000 2.465000 ; - RECT 3.215000 0.085000 3.385000 0.565000 ; - RECT 3.215000 1.835000 3.385000 2.635000 ; - RECT 3.555000 0.260000 3.885000 0.735000 ; - RECT 3.555000 1.615000 3.885000 2.465000 ; - RECT 4.055000 0.085000 4.225000 0.565000 ; - RECT 4.055000 1.835000 4.225000 2.635000 ; - RECT 4.395000 0.260000 4.725000 0.735000 ; - RECT 4.395000 1.615000 4.725000 2.465000 ; - RECT 4.890000 0.905000 5.065000 1.075000 ; - RECT 4.890000 1.075000 11.450000 1.275000 ; - RECT 4.890000 1.275000 5.065000 1.445000 ; - RECT 4.895000 0.085000 5.065000 0.565000 ; - RECT 4.895000 1.835000 5.065000 2.635000 ; - RECT 5.735000 0.085000 5.905000 0.565000 ; - RECT 5.735000 1.835000 5.905000 2.635000 ; - RECT 6.575000 0.085000 6.745000 0.565000 ; - RECT 6.575000 1.835000 6.745000 2.635000 ; - RECT 7.415000 0.085000 7.585000 0.565000 ; - RECT 7.415000 1.835000 7.585000 2.635000 ; - RECT 8.255000 0.085000 8.425000 0.565000 ; - RECT 8.255000 1.835000 8.425000 2.635000 ; - RECT 9.095000 0.085000 9.265000 0.565000 ; - RECT 9.095000 1.835000 9.265000 2.635000 ; - RECT 9.935000 0.085000 10.105000 0.565000 ; - RECT 9.935000 1.835000 10.105000 2.635000 ; - RECT 10.775000 0.085000 10.945000 0.565000 ; - RECT 10.775000 1.835000 10.945000 2.635000 ; - RECT 11.615000 0.085000 11.785000 0.565000 ; - RECT 11.615000 1.835000 11.785000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - END -END sky130_fd_sc_hd__bufbuf_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__bufinv_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__bufinv_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.505000 1.275000 ; - END - END A - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.715000 0.260000 3.045000 0.735000 ; - RECT 2.715000 0.735000 6.355000 0.905000 ; - RECT 2.715000 1.445000 6.355000 1.615000 ; - RECT 2.715000 1.615000 3.045000 2.465000 ; - RECT 3.555000 0.260000 3.885000 0.735000 ; - RECT 3.555000 1.615000 3.885000 2.465000 ; - RECT 4.395000 0.260000 4.725000 0.735000 ; - RECT 4.395000 1.615000 4.725000 2.465000 ; - RECT 5.235000 0.260000 5.565000 0.735000 ; - RECT 5.235000 1.615000 5.565000 2.465000 ; - RECT 5.970000 0.905000 6.355000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.175000 0.085000 0.345000 0.905000 ; - RECT 0.175000 1.445000 0.345000 2.635000 ; - RECT 0.515000 0.260000 0.845000 0.905000 ; - RECT 0.515000 1.545000 0.845000 2.465000 ; - RECT 0.675000 0.905000 0.845000 1.075000 ; - RECT 0.675000 1.075000 2.205000 1.275000 ; - RECT 0.675000 1.275000 0.845000 1.545000 ; - RECT 1.035000 0.260000 1.365000 0.735000 ; - RECT 1.035000 0.735000 2.545000 0.905000 ; - RECT 1.035000 1.445000 2.545000 1.615000 ; - RECT 1.035000 1.615000 1.365000 2.465000 ; - RECT 1.535000 0.085000 1.705000 0.565000 ; - RECT 1.535000 1.785000 1.705000 2.635000 ; - RECT 1.875000 0.260000 2.205000 0.735000 ; - RECT 1.875000 1.615000 2.205000 2.465000 ; - RECT 2.375000 0.085000 2.545000 0.565000 ; - RECT 2.375000 0.905000 2.545000 1.075000 ; - RECT 2.375000 1.075000 5.760000 1.275000 ; - RECT 2.375000 1.275000 2.545000 1.445000 ; - RECT 2.375000 1.785000 2.545000 2.635000 ; - RECT 3.215000 0.085000 3.385000 0.565000 ; - RECT 3.215000 1.835000 3.385000 2.635000 ; - RECT 4.055000 0.085000 4.225000 0.565000 ; - RECT 4.055000 1.835000 4.225000 2.635000 ; - RECT 4.895000 0.085000 5.065000 0.565000 ; - RECT 4.895000 1.835000 5.065000 2.635000 ; - RECT 5.735000 0.085000 5.905000 0.565000 ; - RECT 5.735000 1.835000 5.905000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__bufinv_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__bufinv_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__bufinv_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.742500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 1.265000 1.275000 ; - END - END A - PIN Y - ANTENNADIFFAREA 3.564000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.295000 0.255000 4.545000 0.260000 ; - RECT 4.295000 0.260000 4.625000 0.735000 ; - RECT 4.295000 0.735000 10.955000 0.905000 ; - RECT 4.295000 1.445000 10.955000 1.615000 ; - RECT 4.295000 1.615000 4.625000 2.465000 ; - RECT 5.135000 0.260000 5.465000 0.735000 ; - RECT 5.135000 1.615000 5.465000 2.465000 ; - RECT 5.215000 0.255000 5.385000 0.260000 ; - RECT 5.975000 0.260000 6.305000 0.735000 ; - RECT 5.975000 1.615000 6.305000 2.465000 ; - RECT 6.055000 0.255000 6.225000 0.260000 ; - RECT 6.815000 0.260000 7.145000 0.735000 ; - RECT 6.815000 1.615000 7.145000 2.465000 ; - RECT 7.655000 0.260000 7.985000 0.735000 ; - RECT 7.655000 1.615000 7.985000 2.465000 ; - RECT 8.495000 0.260000 8.825000 0.735000 ; - RECT 8.495000 1.615000 8.825000 2.465000 ; - RECT 9.335000 0.260000 9.665000 0.735000 ; - RECT 9.335000 1.615000 9.665000 2.465000 ; - RECT 10.175000 0.260000 10.505000 0.735000 ; - RECT 10.175000 1.615000 10.505000 2.465000 ; - RECT 10.680000 0.905000 10.955000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.095000 0.260000 0.425000 0.735000 ; - RECT 0.095000 0.735000 1.605000 0.905000 ; - RECT 0.095000 1.445000 1.605000 1.615000 ; - RECT 0.095000 1.615000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.765000 0.565000 ; - RECT 0.595000 1.785000 0.765000 2.635000 ; - RECT 0.935000 0.260000 1.265000 0.735000 ; - RECT 0.935000 1.615000 1.265000 2.465000 ; - RECT 1.435000 0.085000 1.605000 0.565000 ; - RECT 1.435000 0.905000 1.605000 1.075000 ; - RECT 1.435000 1.075000 3.745000 1.275000 ; - RECT 1.435000 1.275000 1.605000 1.445000 ; - RECT 1.435000 1.785000 1.605000 2.635000 ; - RECT 1.775000 0.260000 2.105000 0.735000 ; - RECT 1.775000 0.735000 4.125000 0.905000 ; - RECT 1.775000 1.445000 4.125000 1.615000 ; - RECT 1.775000 1.615000 2.105000 2.465000 ; - RECT 2.275000 0.085000 2.445000 0.565000 ; - RECT 2.275000 1.835000 2.445000 2.635000 ; - RECT 2.615000 0.260000 2.945000 0.735000 ; - RECT 2.615000 1.615000 2.945000 2.465000 ; - RECT 3.115000 0.085000 3.285000 0.565000 ; - RECT 3.115000 1.835000 3.285000 2.635000 ; - RECT 3.455000 0.260000 3.785000 0.735000 ; - RECT 3.455000 1.615000 3.785000 2.465000 ; - RECT 3.950000 0.905000 4.125000 1.075000 ; - RECT 3.950000 1.075000 10.510000 1.275000 ; - RECT 3.950000 1.275000 4.125000 1.445000 ; - RECT 3.955000 0.085000 4.125000 0.565000 ; - RECT 3.955000 1.835000 4.125000 2.635000 ; - RECT 4.795000 0.085000 4.965000 0.565000 ; - RECT 4.795000 1.835000 4.965000 2.635000 ; - RECT 5.635000 0.085000 5.805000 0.565000 ; - RECT 5.635000 1.835000 5.805000 2.635000 ; - RECT 6.475000 0.085000 6.645000 0.565000 ; - RECT 6.475000 1.835000 6.645000 2.635000 ; - RECT 7.315000 0.085000 7.485000 0.565000 ; - RECT 7.315000 1.835000 7.485000 2.635000 ; - RECT 8.155000 0.085000 8.325000 0.565000 ; - RECT 8.155000 1.835000 8.325000 2.635000 ; - RECT 8.995000 0.085000 9.165000 0.565000 ; - RECT 8.995000 1.835000 9.165000 2.635000 ; - RECT 9.835000 0.085000 10.005000 0.565000 ; - RECT 9.835000 1.835000 10.005000 2.635000 ; - RECT 10.675000 0.085000 10.845000 0.565000 ; - RECT 10.675000 1.835000 10.845000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - END -END sky130_fd_sc_hd__bufinv_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkbuf_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkbuf_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.196500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.985000 1.275000 1.355000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.340600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.345000 0.760000 ; - RECT 0.085000 0.760000 0.255000 1.560000 ; - RECT 0.085000 1.560000 0.355000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.425000 1.060000 0.710000 1.390000 ; - RECT 0.525000 0.085000 0.855000 0.465000 ; - RECT 0.525000 1.875000 0.855000 2.635000 ; - RECT 0.540000 0.635000 1.205000 0.805000 ; - RECT 0.540000 0.805000 0.710000 1.060000 ; - RECT 0.540000 1.390000 0.710000 1.535000 ; - RECT 0.540000 1.535000 1.205000 1.705000 ; - RECT 1.035000 0.255000 1.205000 0.635000 ; - RECT 1.035000 1.705000 1.205000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__clkbuf_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkbuf_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkbuf_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.745000 0.785000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.383400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.040000 0.255000 1.245000 0.655000 ; - RECT 1.040000 0.655000 1.725000 0.825000 ; - RECT 1.060000 1.855000 1.725000 2.030000 ; - RECT 1.060000 2.030000 1.245000 2.435000 ; - RECT 1.385000 0.825000 1.725000 1.855000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.585000 ; - RECT 0.085000 0.585000 0.255000 1.495000 ; - RECT 0.085000 1.495000 1.215000 1.665000 ; - RECT 0.085000 1.665000 0.355000 2.435000 ; - RECT 0.525000 1.855000 0.855000 2.635000 ; - RECT 0.555000 0.085000 0.830000 0.565000 ; - RECT 0.965000 0.995000 1.215000 1.495000 ; - RECT 1.415000 0.085000 1.750000 0.485000 ; - RECT 1.415000 2.210000 1.750000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__clkbuf_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkbuf_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkbuf_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.755000 0.775000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.795200 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.345000 1.305000 0.735000 ; - RECT 1.010000 0.735000 2.660000 0.905000 ; - RECT 1.045000 1.835000 2.165000 2.005000 ; - RECT 1.045000 2.005000 1.305000 2.465000 ; - RECT 1.905000 0.345000 2.165000 0.735000 ; - RECT 1.905000 1.415000 2.660000 1.585000 ; - RECT 1.905000 1.585000 2.165000 1.835000 ; - RECT 1.905000 2.005000 2.165000 2.465000 ; - RECT 2.255000 0.905000 2.660000 1.415000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.255000 0.385000 0.585000 ; - RECT 0.085000 0.585000 0.255000 1.495000 ; - RECT 0.085000 1.495000 1.115000 1.665000 ; - RECT 0.085000 1.665000 0.395000 2.465000 ; - RECT 0.555000 0.085000 0.830000 0.565000 ; - RECT 0.565000 1.835000 0.875000 2.635000 ; - RECT 0.945000 1.075000 2.085000 1.245000 ; - RECT 0.945000 1.245000 1.115000 1.495000 ; - RECT 1.475000 0.085000 1.730000 0.565000 ; - RECT 1.475000 2.175000 1.730000 2.635000 ; - RECT 2.335000 0.085000 2.615000 0.565000 ; - RECT 2.335000 1.765000 2.620000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__clkbuf_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkbuf_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkbuf_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.426000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 0.400000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.590400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.420000 0.280000 1.680000 0.735000 ; - RECT 1.420000 0.735000 4.730000 0.905000 ; - RECT 1.420000 1.495000 4.730000 1.735000 ; - RECT 1.420000 1.735000 1.680000 2.460000 ; - RECT 2.280000 0.280000 2.540000 0.735000 ; - RECT 2.280000 1.735000 2.540000 2.460000 ; - RECT 3.140000 0.280000 3.400000 0.735000 ; - RECT 3.140000 1.735000 3.400000 2.460000 ; - RECT 3.760000 0.905000 4.730000 1.495000 ; - RECT 4.000000 0.280000 4.260000 0.735000 ; - RECT 4.000000 1.735000 4.260000 2.460000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.095000 1.525000 0.390000 2.635000 ; - RECT 0.145000 0.085000 0.390000 0.545000 ; - RECT 0.570000 0.265000 0.820000 1.075000 ; - RECT 0.570000 1.075000 3.590000 1.325000 ; - RECT 0.570000 1.325000 0.820000 2.460000 ; - RECT 0.990000 0.085000 1.250000 0.610000 ; - RECT 0.990000 1.525000 1.250000 2.635000 ; - RECT 1.850000 0.085000 2.110000 0.565000 ; - RECT 1.850000 1.905000 2.110000 2.635000 ; - RECT 2.710000 0.085000 2.970000 0.565000 ; - RECT 2.710000 1.905000 2.970000 2.635000 ; - RECT 3.570000 0.085000 3.830000 0.565000 ; - RECT 3.570000 1.905000 3.830000 2.635000 ; - RECT 4.430000 0.085000 4.730000 0.565000 ; - RECT 4.430000 1.905000 4.725000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__clkbuf_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkbuf_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkbuf_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.852000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.400000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 3.180800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.280000 0.280000 2.540000 0.735000 ; - RECT 2.280000 0.735000 9.025000 0.905000 ; - RECT 2.280000 1.495000 9.025000 1.720000 ; - RECT 2.280000 1.720000 7.685000 1.735000 ; - RECT 2.280000 1.735000 2.540000 2.460000 ; - RECT 3.140000 0.280000 3.400000 0.735000 ; - RECT 3.140000 1.735000 3.400000 2.460000 ; - RECT 4.000000 0.280000 4.260000 0.735000 ; - RECT 4.000000 1.735000 4.260000 2.460000 ; - RECT 4.845000 0.280000 5.120000 0.735000 ; - RECT 4.860000 1.735000 5.120000 2.460000 ; - RECT 5.705000 0.280000 5.965000 0.735000 ; - RECT 5.705000 1.735000 5.965000 2.460000 ; - RECT 6.565000 0.280000 6.825000 0.735000 ; - RECT 6.565000 1.735000 6.825000 2.460000 ; - RECT 7.425000 0.280000 7.685000 0.735000 ; - RECT 7.425000 1.735000 7.685000 2.460000 ; - RECT 7.860000 0.905000 9.025000 1.495000 ; - RECT 8.295000 0.280000 8.555000 0.735000 ; - RECT 8.295000 1.720000 8.585000 2.460000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.085000 0.085000 0.390000 0.595000 ; - RECT 0.095000 1.825000 0.390000 2.635000 ; - RECT 0.570000 0.265000 0.820000 1.075000 ; - RECT 0.570000 1.075000 7.690000 1.325000 ; - RECT 0.570000 1.325000 0.815000 2.465000 ; - RECT 0.990000 0.085000 1.250000 0.610000 ; - RECT 0.990000 1.825000 1.250000 2.635000 ; - RECT 1.430000 0.265000 1.680000 1.075000 ; - RECT 1.430000 1.325000 1.680000 2.460000 ; - RECT 1.850000 0.085000 2.110000 0.645000 ; - RECT 1.850000 1.835000 2.110000 2.630000 ; - RECT 1.850000 2.630000 8.125000 2.635000 ; - RECT 2.710000 0.085000 2.970000 0.565000 ; - RECT 2.710000 1.905000 2.970000 2.630000 ; - RECT 3.570000 0.085000 3.830000 0.565000 ; - RECT 3.570000 1.905000 3.830000 2.630000 ; - RECT 4.430000 0.085000 4.675000 0.565000 ; - RECT 4.430000 1.905000 4.690000 2.630000 ; - RECT 5.290000 0.085000 5.535000 0.565000 ; - RECT 5.290000 1.905000 5.535000 2.630000 ; - RECT 6.145000 0.085000 6.395000 0.565000 ; - RECT 6.150000 1.905000 6.395000 2.630000 ; - RECT 7.005000 0.085000 7.255000 0.565000 ; - RECT 7.010000 1.905000 7.255000 2.630000 ; - RECT 7.865000 0.085000 8.125000 0.565000 ; - RECT 7.870000 1.905000 8.125000 2.630000 ; - RECT 8.725000 0.085000 9.025000 0.565000 ; - RECT 8.755000 1.890000 9.025000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - END -END sky130_fd_sc_hd__clkbuf_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s15_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s15_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.560000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.376300 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.210000 0.285000 3.595000 0.545000 ; - RECT 3.210000 1.760000 3.595000 2.465000 ; - RECT 3.365000 0.545000 3.595000 1.760000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.255000 0.425000 0.715000 ; - RECT 0.085000 0.715000 1.215000 0.885000 ; - RECT 0.085000 1.495000 1.215000 1.665000 ; - RECT 0.085000 1.665000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.910000 0.545000 ; - RECT 0.595000 1.835000 0.925000 2.635000 ; - RECT 0.730000 0.885000 1.215000 1.495000 ; - RECT 1.385000 0.255000 1.760000 0.825000 ; - RECT 1.385000 1.835000 1.760000 2.465000 ; - RECT 1.590000 0.825000 1.760000 1.055000 ; - RECT 1.590000 1.055000 2.685000 1.250000 ; - RECT 1.590000 1.250000 1.760000 1.835000 ; - RECT 1.930000 0.255000 2.260000 0.715000 ; - RECT 1.930000 0.715000 3.195000 0.885000 ; - RECT 1.930000 1.420000 3.195000 1.590000 ; - RECT 1.930000 1.590000 2.410000 2.465000 ; - RECT 2.640000 1.760000 3.040000 2.635000 ; - RECT 2.710000 0.085000 3.040000 0.545000 ; - RECT 2.855000 0.885000 3.195000 1.420000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s15_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s15_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s15_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.060000 0.555000 1.625000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.397600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.050000 0.255000 3.550000 0.640000 ; - RECT 3.070000 1.485000 3.550000 2.465000 ; - RECT 3.355000 0.640000 3.550000 1.485000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.255000 0.415000 0.720000 ; - RECT 0.085000 0.720000 1.060000 0.890000 ; - RECT 0.085000 1.795000 1.060000 1.965000 ; - RECT 0.085000 1.965000 0.430000 2.465000 ; - RECT 0.585000 0.085000 0.915000 0.550000 ; - RECT 0.600000 2.135000 0.930000 2.635000 ; - RECT 0.890000 0.890000 1.060000 1.075000 ; - RECT 0.890000 1.075000 1.320000 1.245000 ; - RECT 0.890000 1.245000 1.060000 1.795000 ; - RECT 1.230000 1.785000 1.660000 2.465000 ; - RECT 1.280000 0.255000 1.660000 0.905000 ; - RECT 1.490000 0.905000 1.660000 1.075000 ; - RECT 1.490000 1.075000 2.415000 1.485000 ; - RECT 1.490000 1.485000 1.660000 1.785000 ; - RECT 1.830000 0.255000 2.100000 0.735000 ; - RECT 1.830000 0.735000 2.900000 0.905000 ; - RECT 1.830000 1.790000 2.900000 1.965000 ; - RECT 1.830000 1.965000 2.100000 2.465000 ; - RECT 2.550000 0.085000 2.880000 0.565000 ; - RECT 2.550000 2.135000 2.880000 2.635000 ; - RECT 2.730000 0.905000 2.900000 1.075000 ; - RECT 2.730000 1.075000 3.185000 1.245000 ; - RECT 2.730000 1.245000 2.900000 1.790000 ; - RECT 3.720000 0.085000 4.055000 0.645000 ; - RECT 3.720000 1.485000 4.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s15_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s18_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s18_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.055000 0.550000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.376300 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.210000 0.255000 3.590000 0.545000 ; - RECT 3.220000 1.760000 3.590000 2.465000 ; - RECT 3.365000 0.545000 3.590000 1.760000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.095000 0.255000 0.425000 0.715000 ; - RECT 0.095000 0.715000 1.215000 0.885000 ; - RECT 0.095000 1.495000 1.215000 1.665000 ; - RECT 0.095000 1.665000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.910000 0.545000 ; - RECT 0.595000 1.835000 0.925000 2.635000 ; - RECT 0.720000 0.885000 1.215000 1.495000 ; - RECT 1.385000 0.255000 1.760000 0.825000 ; - RECT 1.385000 1.835000 1.760000 2.465000 ; - RECT 1.590000 0.825000 1.760000 1.055000 ; - RECT 1.590000 1.055000 2.685000 1.250000 ; - RECT 1.590000 1.250000 1.760000 1.835000 ; - RECT 1.930000 0.255000 2.260000 0.715000 ; - RECT 1.930000 0.715000 3.195000 0.885000 ; - RECT 1.930000 1.420000 3.195000 1.590000 ; - RECT 1.930000 1.590000 2.260000 2.465000 ; - RECT 2.710000 0.085000 3.040000 0.545000 ; - RECT 2.710000 1.760000 3.040000 2.635000 ; - RECT 2.855000 0.885000 3.195000 1.420000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s18_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s18_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s18_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.560000 1.290000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.397600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.705000 0.270000 3.150000 0.640000 ; - RECT 2.715000 1.420000 3.180000 1.525000 ; - RECT 2.715000 1.525000 3.150000 2.465000 ; - RECT 2.965000 0.640000 3.150000 0.780000 ; - RECT 2.965000 0.780000 3.180000 0.945000 ; - RECT 3.010000 0.945000 3.180000 1.420000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.270000 0.415000 0.735000 ; - RECT 0.085000 0.735000 1.055000 0.905000 ; - RECT 0.085000 1.460000 1.055000 1.630000 ; - RECT 0.085000 1.630000 0.430000 2.465000 ; - RECT 0.585000 0.085000 0.915000 0.565000 ; - RECT 0.600000 1.800000 0.930000 2.635000 ; - RECT 0.730000 0.905000 1.055000 1.460000 ; - RECT 1.110000 1.800000 1.440000 2.465000 ; - RECT 1.160000 0.270000 1.440000 0.600000 ; - RECT 1.270000 0.600000 1.440000 1.075000 ; - RECT 1.270000 1.075000 2.205000 1.255000 ; - RECT 1.270000 1.255000 1.440000 1.800000 ; - RECT 1.630000 0.270000 1.960000 0.735000 ; - RECT 1.630000 0.735000 2.545000 0.905000 ; - RECT 1.630000 1.460000 2.545000 1.630000 ; - RECT 1.630000 1.630000 1.960000 2.465000 ; - RECT 2.130000 1.800000 2.545000 2.635000 ; - RECT 2.165000 0.085000 2.535000 0.565000 ; - RECT 2.375000 0.905000 2.545000 1.075000 ; - RECT 2.375000 1.075000 2.840000 1.245000 ; - RECT 2.375000 1.245000 2.545000 1.460000 ; - RECT 3.320000 0.085000 3.595000 0.645000 ; - RECT 3.320000 1.625000 3.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s18_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s25_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s25_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.485000 1.320000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.702900 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.015000 0.255000 3.595000 0.640000 ; - RECT 3.035000 1.565000 3.595000 2.465000 ; - RECT 3.230000 0.640000 3.595000 1.565000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.255000 0.410000 0.735000 ; - RECT 0.085000 0.735000 1.005000 0.905000 ; - RECT 0.085000 1.490000 1.005000 1.660000 ; - RECT 0.085000 1.660000 0.430000 2.465000 ; - RECT 0.580000 0.085000 0.910000 0.565000 ; - RECT 0.600000 1.830000 0.925000 2.635000 ; - RECT 0.655000 0.905000 1.005000 1.025000 ; - RECT 0.655000 1.025000 1.105000 1.295000 ; - RECT 0.655000 1.295000 1.005000 1.490000 ; - RECT 1.175000 0.255000 1.645000 0.855000 ; - RECT 1.195000 1.790000 1.645000 2.465000 ; - RECT 1.470000 0.855000 1.645000 1.075000 ; - RECT 1.470000 1.075000 2.420000 1.250000 ; - RECT 1.470000 1.250000 1.645000 1.790000 ; - RECT 1.815000 0.255000 2.065000 0.735000 ; - RECT 1.815000 0.735000 2.765000 0.905000 ; - RECT 1.815000 1.495000 2.765000 1.665000 ; - RECT 1.815000 1.665000 2.065000 2.465000 ; - RECT 2.235000 1.835000 2.845000 2.635000 ; - RECT 2.240000 0.085000 2.845000 0.565000 ; - RECT 2.595000 0.905000 2.765000 0.990000 ; - RECT 2.595000 0.990000 3.050000 1.325000 ; - RECT 2.595000 1.325000 2.765000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s25_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s25_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s25_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.495000 1.615000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.497000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.770000 0.285000 3.095000 0.615000 ; - RECT 2.770000 1.625000 3.095000 2.460000 ; - RECT 2.865000 0.615000 3.095000 0.765000 ; - RECT 2.865000 0.765000 3.595000 1.275000 ; - RECT 2.865000 1.275000 3.095000 1.625000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.095000 0.305000 0.345000 0.640000 ; - RECT 0.095000 0.640000 0.840000 0.810000 ; - RECT 0.095000 1.785000 0.835000 1.955000 ; - RECT 0.095000 1.955000 0.345000 2.465000 ; - RECT 0.575000 0.085000 0.905000 0.470000 ; - RECT 0.575000 2.125000 0.905000 2.635000 ; - RECT 0.665000 0.810000 0.840000 0.995000 ; - RECT 0.665000 0.995000 1.035000 1.325000 ; - RECT 0.665000 1.325000 1.005000 1.750000 ; - RECT 0.665000 1.750000 0.835000 1.785000 ; - RECT 1.095000 0.255000 1.425000 0.780000 ; - RECT 1.175000 1.425000 1.440000 2.465000 ; - RECT 1.205000 0.780000 1.425000 0.995000 ; - RECT 1.205000 0.995000 2.165000 1.325000 ; - RECT 1.205000 1.325000 1.440000 1.425000 ; - RECT 1.615000 0.255000 1.945000 0.635000 ; - RECT 1.615000 0.635000 2.595000 0.805000 ; - RECT 1.695000 1.500000 2.595000 1.745000 ; - RECT 1.695000 1.745000 1.945000 2.465000 ; - RECT 2.135000 0.085000 2.465000 0.465000 ; - RECT 2.135000 1.915000 2.465000 2.635000 ; - RECT 2.335000 0.805000 2.595000 1.500000 ; - RECT 3.265000 0.085000 3.595000 0.550000 ; - RECT 3.265000 1.635000 3.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s25_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s50_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s50_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.535000 1.290000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.504100 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.190000 0.255000 3.595000 0.640000 ; - RECT 3.190000 1.690000 3.595000 2.465000 ; - RECT 3.345000 0.640000 3.595000 1.690000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.255000 0.415000 0.735000 ; - RECT 0.085000 0.735000 1.055000 0.905000 ; - RECT 0.085000 1.460000 1.055000 1.630000 ; - RECT 0.085000 1.630000 0.430000 2.465000 ; - RECT 0.585000 0.085000 0.915000 0.565000 ; - RECT 0.600000 1.800000 0.930000 2.635000 ; - RECT 0.705000 0.905000 1.055000 1.025000 ; - RECT 0.705000 1.025000 1.135000 1.315000 ; - RECT 0.705000 1.315000 1.055000 1.460000 ; - RECT 1.380000 0.255000 1.730000 1.070000 ; - RECT 1.380000 1.070000 2.240000 1.320000 ; - RECT 1.380000 1.320000 1.730000 2.465000 ; - RECT 1.990000 0.255000 2.240000 0.730000 ; - RECT 1.990000 0.730000 2.580000 0.900000 ; - RECT 1.990000 1.495000 2.580000 1.665000 ; - RECT 1.990000 1.665000 2.240000 2.465000 ; - RECT 2.410000 0.900000 2.580000 0.995000 ; - RECT 2.410000 0.995000 3.175000 1.325000 ; - RECT 2.410000 1.325000 2.580000 1.495000 ; - RECT 2.690000 0.085000 3.020000 0.600000 ; - RECT 2.690000 1.835000 3.020000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s50_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkdlybuf4s50_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkdlybuf4s50_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.480000 1.285000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.390500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.185000 0.270000 3.625000 0.640000 ; - RECT 3.185000 1.530000 3.625000 2.465000 ; - RECT 3.345000 0.640000 3.625000 1.530000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.270000 0.415000 0.735000 ; - RECT 0.085000 0.735000 1.270000 0.905000 ; - RECT 0.085000 1.455000 1.270000 1.630000 ; - RECT 0.085000 1.630000 0.430000 2.465000 ; - RECT 0.585000 0.085000 0.915000 0.565000 ; - RECT 0.600000 1.800000 0.930000 2.635000 ; - RECT 0.765000 1.075000 1.435000 1.245000 ; - RECT 0.850000 0.905000 1.270000 1.075000 ; - RECT 0.850000 1.245000 1.270000 1.455000 ; - RECT 1.390000 1.785000 1.795000 2.465000 ; - RECT 1.440000 0.270000 1.795000 0.900000 ; - RECT 1.625000 0.900000 1.795000 1.075000 ; - RECT 1.625000 1.075000 2.305000 1.245000 ; - RECT 1.625000 1.245000 1.795000 1.785000 ; - RECT 1.985000 0.270000 2.235000 0.735000 ; - RECT 1.985000 0.735000 2.645000 0.905000 ; - RECT 1.985000 1.460000 2.645000 1.630000 ; - RECT 1.985000 1.630000 2.235000 2.465000 ; - RECT 2.475000 0.905000 2.645000 0.995000 ; - RECT 2.475000 0.995000 3.175000 1.325000 ; - RECT 2.475000 1.325000 2.645000 1.460000 ; - RECT 2.685000 0.085000 3.015000 0.565000 ; - RECT 2.685000 1.800000 3.015000 2.635000 ; - RECT 3.795000 0.085000 4.055000 0.635000 ; - RECT 3.795000 1.800000 4.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__clkdlybuf4s50_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinv_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinv_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.315000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.375000 0.325000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.336000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.840000 0.760000 ; - RECT 0.515000 0.760000 1.295000 1.290000 ; - RECT 0.515000 1.290000 0.845000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.085000 1.665000 0.345000 2.635000 ; - RECT 1.010000 0.085000 1.295000 0.590000 ; - RECT 1.015000 1.665000 1.295000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__clkinv_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinv_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinv_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.576000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.065000 1.305000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.662600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.155000 1.460000 1.755000 1.630000 ; - RECT 0.155000 1.630000 0.410000 2.435000 ; - RECT 1.010000 1.630000 1.270000 2.435000 ; - RECT 1.025000 0.280000 1.250000 0.725000 ; - RECT 1.025000 0.725000 1.755000 0.895000 ; - RECT 1.475000 0.895000 1.755000 1.460000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.560000 0.085000 0.855000 0.610000 ; - RECT 0.580000 1.800000 0.840000 2.635000 ; - RECT 1.420000 0.085000 1.750000 0.555000 ; - RECT 1.440000 1.800000 1.695000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__clkinv_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinv_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinv_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.152000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.445000 1.065000 2.660000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 1.075200 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.725000 3.135000 0.895000 ; - RECT 0.105000 0.895000 0.275000 1.460000 ; - RECT 0.105000 1.460000 3.135000 1.630000 ; - RECT 0.605000 1.630000 0.860000 2.435000 ; - RECT 1.030000 0.280000 1.290000 0.725000 ; - RECT 1.465000 1.630000 1.720000 2.435000 ; - RECT 1.890000 0.280000 2.145000 0.725000 ; - RECT 2.320000 1.630000 2.580000 2.435000 ; - RECT 2.835000 0.895000 3.135000 1.460000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.800000 0.430000 2.635000 ; - RECT 0.565000 0.085000 0.860000 0.555000 ; - RECT 1.030000 1.800000 1.290000 2.635000 ; - RECT 1.460000 0.085000 1.720000 0.555000 ; - RECT 1.890000 1.800000 2.150000 2.635000 ; - RECT 2.315000 0.085000 2.615000 0.555000 ; - RECT 2.750000 1.800000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__clkinv_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinv_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinv_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 2.304000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.455000 1.035000 4.865000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 2.090400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.115000 0.695000 5.440000 0.865000 ; - RECT 0.115000 0.865000 0.285000 1.460000 ; - RECT 0.115000 1.460000 5.440000 1.630000 ; - RECT 0.565000 1.630000 0.805000 2.435000 ; - RECT 1.405000 1.630000 1.645000 2.435000 ; - RECT 1.535000 0.280000 1.725000 0.695000 ; - RECT 2.245000 1.630000 2.495000 2.435000 ; - RECT 2.395000 0.280000 2.585000 0.695000 ; - RECT 3.080000 1.630000 3.325000 2.435000 ; - RECT 3.255000 0.280000 3.445000 0.695000 ; - RECT 3.920000 1.630000 4.175000 2.435000 ; - RECT 4.115000 0.280000 4.305000 0.695000 ; - RECT 4.765000 1.630000 5.005000 2.435000 ; - RECT 5.170000 0.865000 5.440000 1.460000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.135000 1.800000 0.395000 2.635000 ; - RECT 0.975000 1.800000 1.235000 2.635000 ; - RECT 1.035000 0.085000 1.365000 0.525000 ; - RECT 1.815000 1.800000 2.075000 2.635000 ; - RECT 1.895000 0.085000 2.225000 0.525000 ; - RECT 2.665000 1.800000 2.910000 2.635000 ; - RECT 2.755000 0.085000 3.085000 0.525000 ; - RECT 3.495000 1.800000 3.750000 2.635000 ; - RECT 3.615000 0.085000 3.945000 0.525000 ; - RECT 4.345000 1.800000 4.595000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.525000 ; - RECT 5.175000 1.800000 5.430000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__clkinv_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinv_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinv_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 4.608000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.345000 0.895000 2.155000 1.275000 ; - RECT 8.930000 0.895000 10.710000 1.275000 ; - LAYER mcon ; - RECT 1.525000 1.105000 1.695000 1.275000 ; - RECT 1.985000 1.105000 2.155000 1.275000 ; - RECT 9.345000 1.105000 9.515000 1.275000 ; - RECT 9.805000 1.105000 9.975000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.465000 1.075000 2.215000 1.120000 ; - RECT 1.465000 1.120000 10.035000 1.260000 ; - RECT 1.465000 1.260000 2.215000 1.305000 ; - RECT 9.285000 1.075000 10.035000 1.120000 ; - RECT 9.285000 1.260000 10.035000 1.305000 ; - END - END A - PIN Y - ANTENNADIFFAREA 4.520900 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.575000 1.455000 10.480000 1.665000 ; - RECT 0.575000 1.665000 0.830000 2.465000 ; - RECT 1.435000 1.665000 1.690000 2.450000 ; - RECT 2.325000 0.280000 2.550000 1.415000 ; - RECT 2.325000 1.415000 8.755000 1.455000 ; - RECT 2.325000 1.665000 2.550000 2.465000 ; - RECT 3.155000 0.280000 3.410000 1.415000 ; - RECT 3.155000 1.665000 3.410000 2.450000 ; - RECT 4.015000 0.280000 4.255000 1.415000 ; - RECT 4.015000 1.665000 4.255000 2.450000 ; - RECT 4.905000 0.280000 5.255000 1.415000 ; - RECT 4.905000 1.665000 5.280000 2.450000 ; - RECT 5.925000 0.280000 6.175000 1.415000 ; - RECT 5.925000 1.665000 6.175000 2.450000 ; - RECT 6.785000 0.280000 7.035000 1.415000 ; - RECT 6.785000 1.665000 7.035000 2.450000 ; - RECT 7.645000 0.280000 7.895000 1.415000 ; - RECT 7.645000 1.665000 7.895000 2.450000 ; - RECT 8.505000 0.280000 8.755000 1.415000 ; - RECT 8.505000 1.665000 8.755000 2.450000 ; - RECT 9.365000 1.665000 9.605000 2.450000 ; - RECT 10.225000 1.665000 10.480000 2.450000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.140000 1.495000 0.405000 2.635000 ; - RECT 1.000000 1.835000 1.260000 2.635000 ; - RECT 1.855000 0.085000 2.125000 0.610000 ; - RECT 1.865000 1.835000 2.120000 2.635000 ; - RECT 2.720000 0.085000 2.985000 0.610000 ; - RECT 2.720000 1.835000 2.980000 2.635000 ; - RECT 3.580000 0.085000 3.845000 0.610000 ; - RECT 3.585000 1.835000 3.840000 2.635000 ; - RECT 4.465000 0.085000 4.730000 0.610000 ; - RECT 4.465000 1.835000 4.720000 2.635000 ; - RECT 5.490000 0.085000 5.755000 0.610000 ; - RECT 5.490000 1.835000 5.745000 2.120000 ; - RECT 5.490000 2.120000 5.750000 2.635000 ; - RECT 6.350000 0.085000 6.575000 0.610000 ; - RECT 6.355000 1.835000 6.610000 2.635000 ; - RECT 7.210000 0.085000 7.475000 0.610000 ; - RECT 7.215000 1.835000 7.470000 2.635000 ; - RECT 8.070000 0.085000 8.335000 0.610000 ; - RECT 8.075000 1.835000 8.330000 2.635000 ; - RECT 8.930000 0.085000 9.195000 0.610000 ; - RECT 8.935000 1.835000 9.190000 2.635000 ; - RECT 9.795000 1.835000 10.050000 2.635000 ; - RECT 10.650000 1.835000 10.910000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - END -END sky130_fd_sc_hd__clkinv_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinvlp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinvlp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.665000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.995000 0.600000 1.665000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.436750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.810000 0.315000 1.445000 0.750000 ; - RECT 0.810000 0.750000 1.235000 2.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.225000 1.835000 0.555000 2.625000 ; - RECT 0.225000 2.625000 1.740000 2.635000 ; - RECT 0.295000 0.085000 0.625000 0.745000 ; - RECT 1.440000 1.455000 1.740000 2.625000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__clkinvlp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__clkinvlp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__clkinvlp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.330000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.745000 0.425000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.714000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.255000 1.215000 0.680000 ; - RECT 0.595000 0.680000 0.955000 1.015000 ; - RECT 0.595000 1.015000 2.015000 1.295000 ; - RECT 0.595000 1.295000 0.955000 2.465000 ; - RECT 1.685000 1.295000 2.015000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.575000 ; - RECT 0.095000 1.495000 0.425000 2.635000 ; - RECT 1.155000 1.465000 1.485000 2.635000 ; - RECT 1.675000 0.085000 2.005000 0.775000 ; - RECT 2.215000 1.465000 2.545000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__clkinvlp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__conb_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__conb_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN HI - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.605000 1.740000 ; - END - END HI - PIN LO - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.775000 0.915000 1.295000 2.465000 ; - END - END LO - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.275000 1.910000 0.605000 2.635000 ; - RECT 0.775000 0.085000 1.115000 0.745000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__conb_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__decap_3 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__decap_3 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.085000 0.085000 1.295000 0.835000 ; - RECT 0.085000 0.835000 0.605000 1.375000 ; - RECT 0.085000 1.545000 1.295000 2.635000 ; - RECT 0.775000 1.005000 1.295000 1.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__decap_3 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__decap_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__decap_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.085000 0.085000 1.755000 0.855000 ; - RECT 0.085000 0.855000 0.835000 1.375000 ; - RECT 0.085000 1.545000 1.755000 2.635000 ; - RECT 1.005000 1.025000 1.755000 1.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__decap_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__decap_6 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__decap_6 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.085000 2.675000 0.855000 ; - RECT 0.085000 0.855000 1.295000 1.375000 ; - RECT 0.085000 1.545000 2.675000 2.635000 ; - RECT 1.465000 1.025000 2.675000 1.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__decap_6 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__decap_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__decap_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.085000 3.595000 0.855000 ; - RECT 0.085000 0.855000 1.735000 1.375000 ; - RECT 0.085000 1.545000 3.595000 2.635000 ; - RECT 1.905000 1.025000 3.595000 1.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__decap_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__decap_12 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__decap_12 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.085000 0.085000 5.430000 0.855000 ; - RECT 0.085000 0.855000 2.665000 1.375000 ; - RECT 0.085000 1.545000 5.430000 2.635000 ; - RECT 2.835000 1.025000 5.430000 1.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__decap_12 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfbbn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfbbn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.745000 1.005000 2.155000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.615000 0.255000 11.875000 0.825000 ; - RECT 11.615000 1.455000 11.875000 2.465000 ; - RECT 11.665000 0.825000 11.875000 1.455000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.200000 0.255000 10.485000 0.715000 ; - RECT 10.200000 1.630000 10.485000 2.465000 ; - RECT 10.305000 0.715000 10.485000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.235000 1.095000 9.690000 1.325000 ; - END - END RESET_B - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.585000 0.735000 3.995000 0.965000 ; - RECT 3.585000 0.965000 3.915000 1.065000 ; - LAYER mcon ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.280000 0.735000 7.825000 1.065000 ; - LAYER mcon ; - RECT 7.575000 0.765000 7.745000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 7.805000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 7.515000 0.735000 7.805000 0.780000 ; - RECT 7.515000 0.920000 7.805000 0.965000 ; - END - END SET_B - PIN CLK_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.435000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.150000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.235000 2.465000 ; - RECT 1.405000 0.635000 2.125000 0.825000 ; - RECT 1.405000 0.825000 1.575000 1.795000 ; - RECT 1.405000 1.795000 2.125000 1.965000 ; - RECT 1.430000 0.085000 1.785000 0.465000 ; - RECT 1.430000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.325000 0.705000 2.545000 1.575000 ; - RECT 2.325000 1.575000 2.825000 1.955000 ; - RECT 2.335000 2.250000 3.165000 2.420000 ; - RECT 2.400000 0.265000 3.415000 0.465000 ; - RECT 2.725000 0.645000 3.075000 1.015000 ; - RECT 2.995000 1.195000 3.415000 1.235000 ; - RECT 2.995000 1.235000 4.345000 1.405000 ; - RECT 2.995000 1.405000 3.165000 2.250000 ; - RECT 3.245000 0.465000 3.415000 1.195000 ; - RECT 3.335000 1.575000 3.585000 1.785000 ; - RECT 3.335000 1.785000 4.685000 2.035000 ; - RECT 3.405000 2.205000 3.785000 2.635000 ; - RECT 3.585000 0.085000 3.755000 0.525000 ; - RECT 3.925000 0.255000 5.075000 0.425000 ; - RECT 3.925000 0.425000 4.255000 0.505000 ; - RECT 4.085000 2.035000 4.255000 2.375000 ; - RECT 4.095000 1.405000 4.345000 1.485000 ; - RECT 4.125000 1.155000 4.345000 1.235000 ; - RECT 4.405000 0.595000 4.735000 0.765000 ; - RECT 4.515000 0.765000 4.735000 0.895000 ; - RECT 4.515000 0.895000 5.825000 1.065000 ; - RECT 4.515000 1.065000 4.685000 1.785000 ; - RECT 4.855000 1.235000 5.185000 1.415000 ; - RECT 4.855000 1.415000 5.860000 1.655000 ; - RECT 4.875000 1.915000 5.205000 2.635000 ; - RECT 4.905000 0.425000 5.075000 0.715000 ; - RECT 5.325000 0.085000 5.675000 0.465000 ; - RECT 5.495000 1.065000 5.825000 1.235000 ; - RECT 6.060000 1.575000 6.295000 1.985000 ; - RECT 6.065000 1.060000 6.405000 1.125000 ; - RECT 6.065000 1.125000 6.740000 1.305000 ; - RECT 6.185000 0.705000 6.405000 1.060000 ; - RECT 6.250000 2.250000 7.080000 2.420000 ; - RECT 6.300000 0.265000 7.080000 0.465000 ; - RECT 6.535000 1.305000 6.740000 1.905000 ; - RECT 6.910000 0.465000 7.080000 1.235000 ; - RECT 6.910000 1.235000 8.260000 1.405000 ; - RECT 6.910000 1.405000 7.080000 2.250000 ; - RECT 7.250000 0.085000 7.575000 0.525000 ; - RECT 7.250000 1.575000 7.500000 1.915000 ; - RECT 7.250000 1.915000 10.030000 2.085000 ; - RECT 7.320000 2.255000 7.700000 2.635000 ; - RECT 7.745000 0.255000 8.955000 0.425000 ; - RECT 7.745000 0.425000 8.075000 0.545000 ; - RECT 7.940000 2.085000 8.110000 2.375000 ; - RECT 8.040000 1.075000 8.260000 1.235000 ; - RECT 8.215000 0.665000 8.615000 0.835000 ; - RECT 8.430000 0.835000 8.615000 0.840000 ; - RECT 8.430000 0.840000 8.600000 1.915000 ; - RECT 8.640000 2.255000 10.030000 2.635000 ; - RECT 8.770000 1.110000 9.055000 1.575000 ; - RECT 8.770000 1.575000 9.555000 1.745000 ; - RECT 8.785000 0.425000 8.955000 0.585000 ; - RECT 8.835000 0.755000 9.475000 0.925000 ; - RECT 8.835000 0.925000 9.055000 1.110000 ; - RECT 9.265000 0.265000 9.475000 0.755000 ; - RECT 9.725000 0.085000 10.030000 0.805000 ; - RECT 9.860000 0.995000 10.125000 1.325000 ; - RECT 9.860000 1.325000 10.030000 1.915000 ; - RECT 10.660000 0.255000 10.975000 0.995000 ; - RECT 10.660000 0.995000 11.495000 1.325000 ; - RECT 10.660000 1.325000 10.975000 2.415000 ; - RECT 11.150000 0.085000 11.445000 0.545000 ; - RECT 11.155000 1.765000 11.445000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 0.765000 0.780000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 1.785000 1.235000 1.955000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 0.765000 3.075000 0.935000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 1.445000 5.835000 1.615000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 1.105000 6.295000 1.275000 ; - RECT 6.125000 1.785000 6.295000 1.955000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.855000 1.445000 9.025000 1.615000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - LAYER met1 ; - RECT 0.550000 0.735000 0.840000 0.780000 ; - RECT 0.550000 0.780000 3.135000 0.920000 ; - RECT 0.550000 0.920000 0.840000 0.965000 ; - RECT 1.005000 1.755000 1.295000 1.800000 ; - RECT 1.005000 1.800000 6.355000 1.940000 ; - RECT 1.005000 1.940000 1.295000 1.985000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.845000 0.735000 3.135000 0.780000 ; - RECT 2.845000 0.920000 3.135000 0.965000 ; - RECT 2.920000 0.965000 3.135000 1.120000 ; - RECT 2.920000 1.120000 6.355000 1.260000 ; - RECT 5.605000 1.415000 5.895000 1.460000 ; - RECT 5.605000 1.460000 9.085000 1.600000 ; - RECT 5.605000 1.600000 5.895000 1.645000 ; - RECT 6.065000 1.075000 6.355000 1.120000 ; - RECT 6.065000 1.260000 6.355000 1.305000 ; - RECT 6.065000 1.755000 6.355000 1.800000 ; - RECT 6.065000 1.940000 6.355000 1.985000 ; - RECT 8.795000 1.415000 9.085000 1.460000 ; - RECT 8.795000 1.600000 9.085000 1.645000 ; - END -END sky130_fd_sc_hd__dfbbn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfbbn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfbbn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.88000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.760000 1.005000 2.170000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.115000 0.255000 12.345000 0.825000 ; - RECT 12.115000 1.445000 12.345000 2.465000 ; - RECT 12.160000 0.825000 12.345000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.240000 0.255000 10.500000 0.715000 ; - RECT 10.240000 1.630000 10.500000 2.465000 ; - RECT 10.320000 0.715000 10.500000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.250000 1.095000 9.730000 1.325000 ; - END - END RESET_B - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.600000 0.735000 4.010000 0.965000 ; - RECT 3.600000 0.965000 3.930000 1.065000 ; - LAYER mcon ; - RECT 3.840000 0.765000 4.010000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.470000 0.735000 7.845000 1.065000 ; - LAYER mcon ; - RECT 7.520000 0.765000 7.690000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.780000 0.735000 4.070000 0.780000 ; - RECT 3.780000 0.780000 7.750000 0.920000 ; - RECT 3.780000 0.920000 4.070000 0.965000 ; - RECT 7.460000 0.735000 7.750000 0.780000 ; - RECT 7.460000 0.920000 7.750000 0.965000 ; - END - END SET_B - PIN CLK_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.440000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.880000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 13.070000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.880000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.880000 0.085000 ; - RECT 0.000000 2.635000 12.880000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.840000 0.805000 ; - RECT 0.085000 1.795000 0.840000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.420000 0.635000 2.125000 0.825000 ; - RECT 1.420000 0.825000 1.590000 1.795000 ; - RECT 1.420000 1.795000 2.125000 1.965000 ; - RECT 1.445000 0.085000 1.785000 0.465000 ; - RECT 1.445000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.340000 0.705000 2.560000 1.575000 ; - RECT 2.340000 1.575000 2.840000 1.955000 ; - RECT 2.350000 2.250000 3.180000 2.420000 ; - RECT 2.415000 0.265000 3.410000 0.465000 ; - RECT 2.740000 0.645000 3.070000 1.015000 ; - RECT 3.010000 1.195000 3.410000 1.235000 ; - RECT 3.010000 1.235000 4.360000 1.405000 ; - RECT 3.010000 1.405000 3.180000 2.250000 ; - RECT 3.240000 0.465000 3.410000 1.195000 ; - RECT 3.350000 1.575000 3.600000 1.785000 ; - RECT 3.350000 1.785000 4.700000 2.035000 ; - RECT 3.420000 2.205000 3.800000 2.635000 ; - RECT 3.580000 0.085000 3.750000 0.525000 ; - RECT 3.920000 0.255000 5.170000 0.425000 ; - RECT 3.920000 0.425000 4.250000 0.545000 ; - RECT 4.100000 2.035000 4.270000 2.375000 ; - RECT 4.110000 1.405000 4.360000 1.485000 ; - RECT 4.140000 1.155000 4.360000 1.235000 ; - RECT 4.420000 0.595000 4.750000 0.765000 ; - RECT 4.530000 0.765000 4.750000 0.895000 ; - RECT 4.530000 0.895000 5.840000 1.065000 ; - RECT 4.530000 1.065000 4.700000 1.785000 ; - RECT 4.870000 1.235000 5.200000 1.415000 ; - RECT 4.870000 1.415000 5.875000 1.655000 ; - RECT 4.890000 1.915000 5.220000 2.635000 ; - RECT 4.920000 0.425000 5.170000 0.715000 ; - RECT 5.360000 0.085000 5.690000 0.465000 ; - RECT 5.510000 1.065000 5.840000 1.235000 ; - RECT 6.075000 1.575000 6.310000 1.985000 ; - RECT 6.135000 0.705000 6.420000 1.125000 ; - RECT 6.135000 1.125000 6.755000 1.305000 ; - RECT 6.265000 2.250000 7.095000 2.420000 ; - RECT 6.330000 0.265000 7.095000 0.465000 ; - RECT 6.550000 1.305000 6.755000 1.905000 ; - RECT 6.925000 0.465000 7.095000 1.235000 ; - RECT 6.925000 1.235000 8.275000 1.405000 ; - RECT 6.925000 1.405000 7.095000 2.250000 ; - RECT 7.265000 1.575000 7.515000 1.915000 ; - RECT 7.265000 1.915000 10.070000 2.085000 ; - RECT 7.275000 0.085000 7.535000 0.525000 ; - RECT 7.335000 2.255000 7.715000 2.635000 ; - RECT 7.795000 0.255000 8.965000 0.425000 ; - RECT 7.795000 0.425000 8.125000 0.545000 ; - RECT 7.955000 2.085000 8.125000 2.375000 ; - RECT 8.055000 1.075000 8.275000 1.235000 ; - RECT 8.295000 0.595000 8.625000 0.780000 ; - RECT 8.445000 0.780000 8.625000 1.915000 ; - RECT 8.655000 2.255000 10.070000 2.635000 ; - RECT 8.795000 0.425000 8.965000 0.585000 ; - RECT 8.795000 0.755000 9.500000 0.925000 ; - RECT 8.795000 0.925000 9.070000 1.575000 ; - RECT 8.795000 1.575000 9.570000 1.745000 ; - RECT 9.280000 0.265000 9.500000 0.755000 ; - RECT 9.740000 0.085000 10.070000 0.805000 ; - RECT 9.900000 0.995000 10.140000 1.325000 ; - RECT 9.900000 1.325000 10.070000 1.915000 ; - RECT 10.680000 0.085000 10.910000 0.885000 ; - RECT 10.680000 1.465000 10.910000 2.635000 ; - RECT 11.215000 0.255000 11.470000 0.995000 ; - RECT 11.215000 0.995000 11.990000 1.325000 ; - RECT 11.215000 1.325000 11.470000 2.415000 ; - RECT 11.650000 0.085000 11.945000 0.545000 ; - RECT 11.650000 1.765000 11.945000 2.635000 ; - RECT 12.515000 0.085000 12.795000 0.885000 ; - RECT 12.515000 1.465000 12.795000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 0.765000 0.780000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.460000 1.785000 2.630000 1.955000 ; - RECT 2.900000 0.765000 3.070000 0.935000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.680000 1.445000 5.850000 1.615000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.140000 1.105000 6.310000 1.275000 ; - RECT 6.140000 1.785000 6.310000 1.955000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 8.900000 1.445000 9.070000 1.615000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - LAYER met1 ; - RECT 0.550000 0.735000 0.840000 0.780000 ; - RECT 0.550000 0.780000 3.130000 0.920000 ; - RECT 0.550000 0.920000 0.840000 0.965000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 6.370000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.400000 1.755000 2.690000 1.800000 ; - RECT 2.400000 1.940000 2.690000 1.985000 ; - RECT 2.840000 0.735000 3.130000 0.780000 ; - RECT 2.840000 0.920000 3.130000 0.965000 ; - RECT 2.935000 0.965000 3.130000 1.120000 ; - RECT 2.935000 1.120000 6.370000 1.260000 ; - RECT 5.620000 1.415000 5.910000 1.460000 ; - RECT 5.620000 1.460000 9.130000 1.600000 ; - RECT 5.620000 1.600000 5.910000 1.645000 ; - RECT 6.080000 1.075000 6.370000 1.120000 ; - RECT 6.080000 1.260000 6.370000 1.305000 ; - RECT 6.080000 1.755000 6.370000 1.800000 ; - RECT 6.080000 1.940000 6.370000 1.985000 ; - RECT 8.840000 1.415000 9.130000 1.460000 ; - RECT 8.840000 1.600000 9.130000 1.645000 ; - END -END sky130_fd_sc_hd__dfbbn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfbbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfbbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.750000 1.005000 2.160000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.615000 0.255000 11.875000 0.825000 ; - RECT 11.615000 1.445000 11.875000 2.465000 ; - RECT 11.660000 0.825000 11.875000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.200000 0.255000 10.485000 0.715000 ; - RECT 10.200000 1.630000 10.485000 2.465000 ; - RECT 10.280000 0.715000 10.485000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.315000 1.095000 9.690000 1.325000 ; - END - END RESET_B - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.590000 0.735000 4.000000 0.965000 ; - RECT 3.590000 0.965000 3.920000 1.065000 ; - LAYER mcon ; - RECT 3.830000 0.765000 4.000000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.460000 0.735000 7.835000 1.065000 ; - LAYER mcon ; - RECT 7.510000 0.765000 7.680000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.770000 0.735000 4.060000 0.780000 ; - RECT 3.770000 0.780000 7.740000 0.920000 ; - RECT 3.770000 0.920000 4.060000 0.965000 ; - RECT 7.450000 0.735000 7.740000 0.780000 ; - RECT 7.450000 0.920000 7.740000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.150000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.840000 0.805000 ; - RECT 0.085000 1.795000 0.840000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.410000 0.635000 2.125000 0.825000 ; - RECT 1.410000 0.825000 1.580000 1.795000 ; - RECT 1.410000 1.795000 2.125000 1.965000 ; - RECT 1.435000 0.085000 1.785000 0.465000 ; - RECT 1.435000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.330000 0.705000 2.550000 1.575000 ; - RECT 2.330000 1.575000 2.830000 1.955000 ; - RECT 2.340000 2.250000 3.170000 2.420000 ; - RECT 2.405000 0.265000 3.400000 0.465000 ; - RECT 2.730000 0.645000 3.060000 1.015000 ; - RECT 3.000000 1.195000 3.400000 1.235000 ; - RECT 3.000000 1.235000 4.350000 1.405000 ; - RECT 3.000000 1.405000 3.170000 2.250000 ; - RECT 3.230000 0.465000 3.400000 1.195000 ; - RECT 3.340000 1.575000 3.590000 1.785000 ; - RECT 3.340000 1.785000 4.690000 2.035000 ; - RECT 3.410000 2.205000 3.790000 2.635000 ; - RECT 3.570000 0.085000 3.740000 0.525000 ; - RECT 3.910000 0.255000 5.080000 0.425000 ; - RECT 3.910000 0.425000 4.240000 0.545000 ; - RECT 4.090000 2.035000 4.260000 2.375000 ; - RECT 4.100000 1.405000 4.350000 1.485000 ; - RECT 4.130000 1.155000 4.350000 1.235000 ; - RECT 4.410000 0.595000 4.740000 0.765000 ; - RECT 4.520000 0.765000 4.740000 0.895000 ; - RECT 4.520000 0.895000 5.830000 1.065000 ; - RECT 4.520000 1.065000 4.690000 1.785000 ; - RECT 4.860000 1.235000 5.190000 1.415000 ; - RECT 4.860000 1.415000 5.865000 1.655000 ; - RECT 4.880000 1.915000 5.210000 2.635000 ; - RECT 4.910000 0.425000 5.080000 0.715000 ; - RECT 5.350000 0.085000 5.680000 0.465000 ; - RECT 5.500000 1.065000 5.830000 1.235000 ; - RECT 6.065000 1.575000 6.300000 1.985000 ; - RECT 6.125000 0.705000 6.410000 1.125000 ; - RECT 6.125000 1.125000 6.745000 1.305000 ; - RECT 6.255000 2.250000 7.085000 2.420000 ; - RECT 6.320000 0.265000 7.085000 0.465000 ; - RECT 6.540000 1.305000 6.745000 1.905000 ; - RECT 6.915000 0.465000 7.085000 1.235000 ; - RECT 6.915000 1.235000 8.265000 1.405000 ; - RECT 6.915000 1.405000 7.085000 2.250000 ; - RECT 7.255000 1.575000 7.505000 1.915000 ; - RECT 7.255000 1.915000 10.030000 2.085000 ; - RECT 7.265000 0.085000 7.525000 0.525000 ; - RECT 7.325000 2.255000 7.705000 2.635000 ; - RECT 7.785000 0.255000 8.955000 0.425000 ; - RECT 7.785000 0.425000 8.115000 0.545000 ; - RECT 7.945000 2.085000 8.115000 2.375000 ; - RECT 8.045000 1.075000 8.265000 1.235000 ; - RECT 8.285000 0.595000 8.615000 0.780000 ; - RECT 8.435000 0.780000 8.615000 1.915000 ; - RECT 8.645000 2.255000 10.030000 2.635000 ; - RECT 8.785000 0.425000 8.955000 0.585000 ; - RECT 8.785000 0.755000 9.475000 0.925000 ; - RECT 8.785000 0.925000 9.060000 1.575000 ; - RECT 8.785000 1.575000 9.545000 1.745000 ; - RECT 9.240000 0.265000 9.475000 0.755000 ; - RECT 9.700000 0.085000 10.030000 0.805000 ; - RECT 9.860000 0.995000 10.110000 1.325000 ; - RECT 9.860000 1.325000 10.030000 1.915000 ; - RECT 10.655000 0.255000 10.970000 0.995000 ; - RECT 10.655000 0.995000 11.490000 1.325000 ; - RECT 10.655000 1.325000 10.970000 2.415000 ; - RECT 11.150000 0.085000 11.445000 0.545000 ; - RECT 11.150000 1.765000 11.445000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.785000 0.780000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 0.765000 1.240000 0.935000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.450000 1.785000 2.620000 1.955000 ; - RECT 2.890000 0.765000 3.060000 0.935000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.670000 1.445000 5.840000 1.615000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.130000 1.105000 6.300000 1.275000 ; - RECT 6.130000 1.785000 6.300000 1.955000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 8.890000 1.445000 9.060000 1.615000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.755000 0.840000 1.800000 ; - RECT 0.550000 1.800000 6.360000 1.940000 ; - RECT 0.550000 1.940000 0.840000 1.985000 ; - RECT 1.010000 0.735000 1.300000 0.780000 ; - RECT 1.010000 0.780000 3.120000 0.920000 ; - RECT 1.010000 0.920000 1.300000 0.965000 ; - RECT 2.390000 1.755000 2.680000 1.800000 ; - RECT 2.390000 1.940000 2.680000 1.985000 ; - RECT 2.830000 0.735000 3.120000 0.780000 ; - RECT 2.830000 0.920000 3.120000 0.965000 ; - RECT 2.925000 0.965000 3.120000 1.120000 ; - RECT 2.925000 1.120000 6.360000 1.260000 ; - RECT 5.610000 1.415000 5.900000 1.460000 ; - RECT 5.610000 1.460000 9.120000 1.600000 ; - RECT 5.610000 1.600000 5.900000 1.645000 ; - RECT 6.070000 1.075000 6.360000 1.120000 ; - RECT 6.070000 1.260000 6.360000 1.305000 ; - RECT 6.070000 1.755000 6.360000 1.800000 ; - RECT 6.070000 1.940000 6.360000 1.985000 ; - RECT 8.830000 1.415000 9.120000 1.460000 ; - RECT 8.830000 1.600000 9.120000 1.645000 ; - END -END sky130_fd_sc_hd__dfbbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.58000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.449000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.600000 1.455000 9.005000 2.465000 ; - RECT 8.675000 0.275000 9.005000 1.455000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.180000 0.265000 10.435000 0.795000 ; - RECT 10.180000 1.445000 10.435000 2.325000 ; - RECT 10.225000 0.795000 10.435000 1.445000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.580000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.770000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.580000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.580000 0.085000 ; - RECT 0.000000 2.635000 10.580000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 8.135000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.430000 2.635000 ; - RECT 7.815000 0.465000 8.135000 0.820000 ; - RECT 7.815000 0.820000 8.140000 0.995000 ; - RECT 7.815000 0.995000 8.435000 1.295000 ; - RECT 7.990000 1.295000 8.435000 1.325000 ; - RECT 7.990000 1.325000 8.160000 1.915000 ; - RECT 8.335000 0.085000 8.505000 0.770000 ; - RECT 9.195000 0.345000 9.445000 0.995000 ; - RECT 9.195000 0.995000 10.055000 1.325000 ; - RECT 9.195000 1.325000 9.525000 2.425000 ; - RECT 9.760000 0.085000 9.930000 0.680000 ; - RECT 9.760000 1.495000 9.930000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - RECT 1.015000 1.785000 1.185000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 6.255000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 0.955000 1.755000 1.245000 1.800000 ; - RECT 0.955000 1.800000 6.255000 1.940000 ; - RECT 0.955000 1.940000 1.245000 1.985000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.511500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.160000 0.265000 9.495000 1.695000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.030000 1.535000 10.420000 2.080000 ; - RECT 10.040000 0.310000 10.420000 0.825000 ; - RECT 10.120000 2.080000 10.420000 2.465000 ; - RECT 10.250000 0.825000 10.420000 1.535000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 7.985000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.055000 2.635000 ; - RECT 7.815000 0.465000 7.985000 0.995000 ; - RECT 7.815000 0.995000 8.160000 1.075000 ; - RECT 7.815000 1.075000 8.650000 1.295000 ; - RECT 7.990000 1.295000 8.650000 1.325000 ; - RECT 7.990000 1.325000 8.160000 1.915000 ; - RECT 8.335000 0.345000 8.585000 0.715000 ; - RECT 8.335000 0.715000 8.990000 0.885000 ; - RECT 8.335000 1.795000 8.990000 1.865000 ; - RECT 8.335000 1.865000 9.835000 2.035000 ; - RECT 8.335000 2.035000 8.560000 2.465000 ; - RECT 8.730000 2.205000 9.070000 2.635000 ; - RECT 8.755000 0.085000 8.990000 0.545000 ; - RECT 8.820000 0.885000 8.990000 1.795000 ; - RECT 9.620000 2.255000 9.950000 2.635000 ; - RECT 9.665000 0.995000 10.080000 1.325000 ; - RECT 9.665000 1.325000 9.835000 1.865000 ; - RECT 9.700000 0.085000 9.870000 0.825000 ; - RECT 10.590000 0.085000 10.760000 0.930000 ; - RECT 10.590000 1.445000 10.760000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - RECT 1.015000 1.785000 1.185000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 6.255000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 0.955000 1.755000 1.245000 1.800000 ; - RECT 0.955000 1.800000 6.255000 1.940000 ; - RECT 0.955000 1.940000 1.245000 1.985000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrtn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrtn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.855000 0.265000 9.110000 0.795000 ; - RECT 8.855000 1.445000 9.110000 2.325000 ; - RECT 8.900000 0.795000 9.110000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 8.135000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.040000 2.635000 ; - RECT 7.815000 0.465000 8.135000 0.820000 ; - RECT 7.815000 0.820000 8.140000 0.995000 ; - RECT 7.815000 0.995000 8.730000 1.295000 ; - RECT 7.990000 1.295000 8.730000 1.325000 ; - RECT 7.990000 1.325000 8.160000 1.915000 ; - RECT 8.380000 0.085000 8.685000 0.545000 ; - RECT 8.380000 1.495000 8.685000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.655000 1.785000 0.825000 1.955000 ; - RECT 1.015000 1.105000 1.185000 1.275000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - LAYER met1 ; - RECT 0.595000 1.755000 0.885000 1.800000 ; - RECT 0.595000 1.800000 6.255000 1.940000 ; - RECT 0.595000 1.940000 0.885000 1.985000 ; - RECT 0.955000 1.075000 1.245000 1.120000 ; - RECT 0.955000 1.120000 6.255000 1.260000 ; - RECT 0.955000 1.260000 1.245000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrtn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.855000 0.265000 9.110000 0.795000 ; - RECT 8.855000 1.445000 9.110000 2.325000 ; - RECT 8.900000 0.795000 9.110000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 8.135000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.040000 2.635000 ; - RECT 7.815000 0.465000 8.135000 0.820000 ; - RECT 7.815000 0.820000 8.140000 0.995000 ; - RECT 7.815000 0.995000 8.730000 1.295000 ; - RECT 7.990000 1.295000 8.730000 1.325000 ; - RECT 7.990000 1.325000 8.160000 1.915000 ; - RECT 8.380000 0.085000 8.685000 0.545000 ; - RECT 8.380000 1.495000 8.685000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - RECT 1.015000 1.785000 1.185000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 6.255000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 0.955000 1.755000 1.245000 1.800000 ; - RECT 0.955000 1.800000 6.255000 1.940000 ; - RECT 0.955000 1.940000 1.245000 1.985000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.855000 0.265000 9.105000 0.795000 ; - RECT 8.855000 1.445000 9.105000 2.325000 ; - RECT 8.900000 0.795000 9.105000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 8.135000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.040000 2.635000 ; - RECT 7.815000 0.465000 8.135000 0.820000 ; - RECT 7.815000 0.820000 8.140000 0.995000 ; - RECT 7.815000 0.995000 8.730000 1.295000 ; - RECT 7.990000 1.295000 8.730000 1.325000 ; - RECT 7.990000 1.325000 8.160000 1.915000 ; - RECT 8.380000 0.085000 8.685000 0.545000 ; - RECT 8.380000 1.495000 8.685000 2.635000 ; - RECT 9.275000 0.085000 9.525000 0.840000 ; - RECT 9.275000 1.495000 9.525000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - RECT 1.015000 1.785000 1.185000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 6.255000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 0.955000 1.755000 1.245000 1.800000 ; - RECT 0.955000 1.800000 6.255000 1.940000 ; - RECT 0.955000 1.940000 1.245000 1.985000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfrtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfrtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.58000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 1.665000 1.680000 2.450000 ; - RECT 1.415000 0.615000 1.875000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.675000 0.255000 9.005000 0.735000 ; - RECT 8.675000 0.735000 10.440000 0.905000 ; - RECT 8.715000 1.455000 10.440000 1.625000 ; - RECT 8.715000 1.625000 9.005000 2.465000 ; - RECT 9.515000 0.255000 9.845000 0.735000 ; - RECT 9.555000 1.625000 9.805000 2.465000 ; - RECT 10.030000 0.905000 10.440000 1.455000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.765000 4.595000 1.015000 ; - LAYER mcon ; - RECT 4.165000 0.765000 4.335000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.105000 1.035000 7.645000 1.405000 ; - RECT 7.405000 0.635000 7.645000 1.035000 ; - LAYER mcon ; - RECT 7.105000 1.080000 7.275000 1.250000 ; - RECT 7.405000 0.765000 7.575000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.745000 0.735000 4.395000 0.780000 ; - RECT 3.745000 0.780000 7.635000 0.920000 ; - RECT 3.745000 0.920000 4.395000 0.965000 ; - RECT 7.045000 0.920000 7.635000 0.965000 ; - RECT 7.045000 0.965000 7.335000 1.280000 ; - RECT 7.345000 0.735000 7.635000 0.780000 ; - END - END RESET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.580000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.770000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.580000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.580000 0.085000 ; - RECT 0.000000 2.635000 10.580000 2.805000 ; - RECT 0.090000 0.345000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.840000 0.805000 ; - RECT 0.090000 1.795000 0.840000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.545000 0.085000 1.875000 0.445000 ; - RECT 1.850000 2.175000 2.100000 2.635000 ; - RECT 2.045000 0.305000 2.540000 0.475000 ; - RECT 2.045000 0.475000 2.215000 1.835000 ; - RECT 2.045000 1.835000 2.440000 2.005000 ; - RECT 2.270000 2.005000 2.440000 2.135000 ; - RECT 2.270000 2.135000 2.520000 2.465000 ; - RECT 2.385000 0.765000 2.735000 1.385000 ; - RECT 2.610000 1.575000 3.075000 1.965000 ; - RECT 2.735000 2.135000 3.415000 2.465000 ; - RECT 2.745000 0.305000 3.600000 0.475000 ; - RECT 2.905000 0.765000 3.260000 0.985000 ; - RECT 2.905000 0.985000 3.075000 1.575000 ; - RECT 3.245000 1.185000 4.935000 1.355000 ; - RECT 3.245000 1.355000 3.415000 2.135000 ; - RECT 3.430000 0.475000 3.600000 1.185000 ; - RECT 3.585000 1.865000 4.660000 2.035000 ; - RECT 3.585000 2.035000 3.755000 2.375000 ; - RECT 3.775000 1.525000 5.275000 1.695000 ; - RECT 3.990000 2.205000 4.320000 2.635000 ; - RECT 4.475000 0.085000 4.805000 0.545000 ; - RECT 4.490000 2.035000 4.660000 2.375000 ; - RECT 4.765000 1.005000 4.935000 1.185000 ; - RECT 4.955000 2.175000 5.325000 2.635000 ; - RECT 5.015000 0.275000 5.365000 0.445000 ; - RECT 5.015000 0.445000 5.275000 0.835000 ; - RECT 5.105000 0.835000 5.275000 1.525000 ; - RECT 5.105000 1.695000 5.275000 1.835000 ; - RECT 5.105000 1.835000 5.665000 2.005000 ; - RECT 5.465000 0.705000 5.675000 1.495000 ; - RECT 5.465000 1.495000 6.140000 1.655000 ; - RECT 5.465000 1.655000 6.430000 1.665000 ; - RECT 5.495000 2.005000 5.665000 2.465000 ; - RECT 5.585000 0.255000 6.535000 0.535000 ; - RECT 5.845000 0.705000 6.195000 1.325000 ; - RECT 5.900000 2.125000 6.770000 2.465000 ; - RECT 5.970000 1.665000 6.430000 1.955000 ; - RECT 6.365000 0.535000 6.535000 1.315000 ; - RECT 6.365000 1.315000 6.770000 1.485000 ; - RECT 6.600000 1.485000 6.770000 1.575000 ; - RECT 6.600000 1.575000 7.820000 1.745000 ; - RECT 6.600000 1.745000 6.770000 2.125000 ; - RECT 6.705000 0.085000 6.895000 0.525000 ; - RECT 6.705000 0.695000 7.235000 0.865000 ; - RECT 6.705000 0.865000 6.925000 1.145000 ; - RECT 6.940000 2.175000 7.190000 2.635000 ; - RECT 7.065000 0.295000 8.135000 0.465000 ; - RECT 7.065000 0.465000 7.235000 0.695000 ; - RECT 7.360000 1.915000 8.160000 2.085000 ; - RECT 7.360000 2.085000 7.530000 2.375000 ; - RECT 7.710000 2.255000 8.040000 2.635000 ; - RECT 7.815000 0.465000 8.135000 0.820000 ; - RECT 7.815000 0.820000 8.140000 1.075000 ; - RECT 7.815000 1.075000 9.845000 1.285000 ; - RECT 7.815000 1.285000 8.160000 1.295000 ; - RECT 7.990000 1.295000 8.160000 1.915000 ; - RECT 8.335000 0.085000 8.505000 0.895000 ; - RECT 8.335000 1.575000 8.505000 2.635000 ; - RECT 9.175000 0.085000 9.345000 0.555000 ; - RECT 9.175000 1.795000 9.345000 2.635000 ; - RECT 10.015000 0.085000 10.185000 0.555000 ; - RECT 10.015000 1.795000 10.185000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - RECT 1.015000 1.785000 1.185000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.785000 3.075000 1.955000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.025000 1.105000 6.195000 1.275000 ; - RECT 6.025000 1.785000 6.195000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 6.255000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 0.955000 1.755000 1.245000 1.800000 ; - RECT 0.955000 1.800000 6.255000 1.940000 ; - RECT 0.955000 1.940000 1.245000 1.985000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - RECT 2.845000 1.755000 3.135000 1.800000 ; - RECT 2.845000 1.940000 3.135000 1.985000 ; - RECT 5.965000 1.075000 6.255000 1.120000 ; - RECT 5.965000 1.260000 6.255000 1.305000 ; - RECT 5.965000 1.755000 6.255000 1.800000 ; - RECT 5.965000 1.940000 6.255000 1.985000 ; - END -END sky130_fd_sc_hd__dfrtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfsbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfsbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.58000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.770000 1.005000 2.180000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.865000 0.255000 10.125000 0.825000 ; - RECT 9.865000 1.445000 10.125000 2.465000 ; - RECT 9.910000 0.825000 10.125000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.370000 0.255000 8.700000 2.465000 ; - END - END Q_N - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.610000 0.735000 4.020000 1.065000 ; - LAYER mcon ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 6.660000 0.735000 7.320000 1.005000 ; - RECT 6.660000 1.005000 6.990000 1.065000 ; - LAYER mcon ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 7.275000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.580000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.770000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.580000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.580000 0.085000 ; - RECT 0.000000 2.635000 10.580000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.430000 0.635000 2.125000 0.825000 ; - RECT 1.430000 0.825000 1.600000 1.795000 ; - RECT 1.430000 1.795000 2.125000 1.965000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.350000 0.705000 2.570000 1.575000 ; - RECT 2.350000 1.575000 2.850000 1.955000 ; - RECT 2.360000 2.250000 3.190000 2.420000 ; - RECT 2.425000 0.265000 3.440000 0.465000 ; - RECT 2.750000 0.645000 3.100000 1.015000 ; - RECT 3.020000 1.195000 3.440000 1.235000 ; - RECT 3.020000 1.235000 4.370000 1.405000 ; - RECT 3.020000 1.405000 3.190000 2.250000 ; - RECT 3.270000 0.465000 3.440000 1.195000 ; - RECT 3.360000 1.575000 3.610000 1.835000 ; - RECT 3.360000 1.835000 4.710000 2.085000 ; - RECT 3.430000 2.255000 3.810000 2.635000 ; - RECT 3.610000 0.085000 4.020000 0.525000 ; - RECT 3.990000 2.085000 4.160000 2.375000 ; - RECT 4.120000 1.405000 4.370000 1.565000 ; - RECT 4.310000 0.295000 4.560000 0.725000 ; - RECT 4.310000 0.725000 4.710000 1.065000 ; - RECT 4.330000 2.255000 4.660000 2.635000 ; - RECT 4.540000 1.065000 4.710000 1.835000 ; - RECT 4.740000 0.085000 5.080000 0.545000 ; - RECT 4.900000 0.725000 6.150000 0.895000 ; - RECT 4.900000 0.895000 5.070000 1.655000 ; - RECT 4.900000 1.655000 5.400000 1.965000 ; - RECT 5.110000 2.165000 5.760000 2.415000 ; - RECT 5.240000 1.065000 5.420000 1.475000 ; - RECT 5.590000 1.235000 7.470000 1.405000 ; - RECT 5.590000 1.405000 5.760000 1.915000 ; - RECT 5.590000 1.915000 6.780000 2.085000 ; - RECT 5.590000 2.085000 5.760000 2.165000 ; - RECT 5.640000 0.305000 6.490000 0.475000 ; - RECT 5.820000 0.895000 6.150000 1.015000 ; - RECT 5.930000 1.575000 7.830000 1.745000 ; - RECT 5.930000 2.255000 6.340000 2.635000 ; - RECT 6.320000 0.475000 6.490000 1.235000 ; - RECT 6.540000 2.085000 6.780000 2.375000 ; - RECT 6.670000 0.085000 7.330000 0.565000 ; - RECT 7.010000 1.945000 7.340000 2.635000 ; - RECT 7.140000 1.175000 7.470000 1.235000 ; - RECT 7.510000 0.350000 7.830000 0.680000 ; - RECT 7.510000 1.745000 7.830000 1.765000 ; - RECT 7.510000 1.765000 7.680000 2.375000 ; - RECT 7.640000 0.680000 7.830000 1.575000 ; - RECT 8.020000 0.085000 8.200000 0.905000 ; - RECT 8.020000 1.480000 8.200000 2.635000 ; - RECT 8.890000 0.255000 9.220000 0.995000 ; - RECT 8.890000 0.995000 9.740000 1.325000 ; - RECT 8.890000 1.325000 9.220000 2.465000 ; - RECT 9.445000 0.085000 9.615000 0.585000 ; - RECT 9.445000 1.825000 9.615000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.645000 1.785000 0.815000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 0.765000 1.235000 0.935000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 0.765000 3.075000 0.935000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.245000 1.105000 5.415000 1.275000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - LAYER met1 ; - RECT 0.585000 1.755000 0.875000 1.800000 ; - RECT 0.585000 1.800000 5.435000 1.940000 ; - RECT 0.585000 1.940000 0.875000 1.985000 ; - RECT 1.005000 0.735000 1.295000 0.780000 ; - RECT 1.005000 0.780000 3.135000 0.920000 ; - RECT 1.005000 0.920000 1.295000 0.965000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.845000 0.735000 3.135000 0.780000 ; - RECT 2.845000 0.920000 3.135000 0.965000 ; - RECT 2.920000 0.965000 3.135000 1.120000 ; - RECT 2.920000 1.120000 5.475000 1.260000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 5.185000 1.075000 5.475000 1.120000 ; - RECT 5.185000 1.260000 5.475000 1.305000 ; - END -END sky130_fd_sc_hd__dfsbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfsbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfsbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.770000 1.005000 2.180000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.150000 1.495000 10.915000 1.665000 ; - RECT 10.150000 1.665000 10.480000 2.465000 ; - RECT 10.230000 0.255000 10.480000 0.720000 ; - RECT 10.230000 0.720000 10.915000 0.825000 ; - RECT 10.345000 0.825000 10.915000 0.845000 ; - RECT 10.360000 0.845000 10.915000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.370000 0.255000 8.700000 2.465000 ; - END - END Q_N - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.610000 0.735000 4.020000 1.065000 ; - LAYER mcon ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 6.660000 0.735000 7.320000 1.005000 ; - RECT 6.660000 1.005000 6.990000 1.065000 ; - LAYER mcon ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 7.275000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.430000 0.635000 2.125000 0.825000 ; - RECT 1.430000 0.825000 1.600000 1.795000 ; - RECT 1.430000 1.795000 2.125000 1.965000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.350000 0.705000 2.570000 1.575000 ; - RECT 2.350000 1.575000 2.850000 1.955000 ; - RECT 2.360000 2.250000 3.190000 2.420000 ; - RECT 2.425000 0.265000 3.440000 0.465000 ; - RECT 2.750000 0.645000 3.100000 1.015000 ; - RECT 3.020000 1.195000 3.440000 1.235000 ; - RECT 3.020000 1.235000 4.370000 1.405000 ; - RECT 3.020000 1.405000 3.190000 2.250000 ; - RECT 3.270000 0.465000 3.440000 1.195000 ; - RECT 3.360000 1.575000 3.610000 1.835000 ; - RECT 3.360000 1.835000 4.710000 2.085000 ; - RECT 3.430000 2.255000 3.810000 2.635000 ; - RECT 3.610000 0.085000 4.020000 0.525000 ; - RECT 3.990000 2.085000 4.160000 2.375000 ; - RECT 4.120000 1.405000 4.370000 1.565000 ; - RECT 4.310000 0.295000 4.560000 0.725000 ; - RECT 4.310000 0.725000 4.710000 1.065000 ; - RECT 4.330000 2.255000 4.660000 2.635000 ; - RECT 4.540000 1.065000 4.710000 1.835000 ; - RECT 4.740000 0.085000 5.080000 0.545000 ; - RECT 4.900000 0.725000 6.150000 0.895000 ; - RECT 4.900000 0.895000 5.070000 1.655000 ; - RECT 4.900000 1.655000 5.400000 1.965000 ; - RECT 5.110000 2.165000 5.760000 2.415000 ; - RECT 5.240000 1.065000 5.420000 1.475000 ; - RECT 5.590000 1.235000 7.470000 1.405000 ; - RECT 5.590000 1.405000 5.760000 1.915000 ; - RECT 5.590000 1.915000 6.780000 2.085000 ; - RECT 5.590000 2.085000 5.760000 2.165000 ; - RECT 5.640000 0.305000 6.490000 0.475000 ; - RECT 5.820000 0.895000 6.150000 1.015000 ; - RECT 5.930000 1.575000 7.830000 1.745000 ; - RECT 5.930000 2.255000 6.340000 2.635000 ; - RECT 6.320000 0.475000 6.490000 1.235000 ; - RECT 6.540000 2.085000 6.780000 2.375000 ; - RECT 6.670000 0.085000 7.330000 0.565000 ; - RECT 7.010000 1.945000 7.340000 2.635000 ; - RECT 7.140000 1.175000 7.470000 1.235000 ; - RECT 7.510000 0.350000 7.830000 0.680000 ; - RECT 7.510000 1.745000 7.830000 1.765000 ; - RECT 7.510000 1.765000 7.680000 2.375000 ; - RECT 7.640000 0.680000 7.830000 1.575000 ; - RECT 8.020000 0.085000 8.200000 0.905000 ; - RECT 8.020000 1.480000 8.200000 2.635000 ; - RECT 8.870000 0.085000 9.120000 0.905000 ; - RECT 8.870000 1.480000 9.120000 2.635000 ; - RECT 9.310000 0.255000 9.560000 0.995000 ; - RECT 9.310000 0.995000 10.190000 1.325000 ; - RECT 9.310000 1.325000 9.640000 2.465000 ; - RECT 9.730000 0.085000 10.060000 0.825000 ; - RECT 9.810000 1.495000 9.980000 2.635000 ; - RECT 10.650000 0.085000 10.915000 0.550000 ; - RECT 10.650000 1.835000 10.915000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.645000 1.785000 0.815000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 0.765000 1.235000 0.935000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 0.765000 3.075000 0.935000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.245000 1.105000 5.415000 1.275000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.585000 1.755000 0.875000 1.800000 ; - RECT 0.585000 1.800000 5.435000 1.940000 ; - RECT 0.585000 1.940000 0.875000 1.985000 ; - RECT 1.005000 0.735000 1.295000 0.780000 ; - RECT 1.005000 0.780000 3.135000 0.920000 ; - RECT 1.005000 0.920000 1.295000 0.965000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.845000 0.735000 3.135000 0.780000 ; - RECT 2.845000 0.920000 3.135000 0.965000 ; - RECT 2.920000 0.965000 3.135000 1.120000 ; - RECT 2.920000 1.120000 5.475000 1.260000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 5.185000 1.075000 5.475000 1.120000 ; - RECT 5.185000 1.260000 5.475000 1.305000 ; - END -END sky130_fd_sc_hd__dfsbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfstp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfstp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.770000 1.005000 2.180000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.945000 0.265000 9.200000 0.795000 ; - RECT 8.945000 1.655000 9.200000 2.325000 ; - RECT 9.020000 0.795000 9.200000 1.655000 ; - END - END Q - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.610000 0.735000 4.020000 1.065000 ; - LAYER mcon ; - RECT 3.850000 0.765000 4.020000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 6.680000 0.735000 7.340000 1.005000 ; - RECT 6.680000 1.005000 7.010000 1.065000 ; - LAYER mcon ; - RECT 7.110000 0.765000 7.280000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.790000 0.735000 4.080000 0.780000 ; - RECT 3.790000 0.780000 7.340000 0.920000 ; - RECT 3.790000 0.920000 4.080000 0.965000 ; - RECT 7.050000 0.735000 7.340000 0.780000 ; - RECT 7.050000 0.920000 7.340000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.430000 0.635000 2.125000 0.825000 ; - RECT 1.430000 0.825000 1.600000 1.795000 ; - RECT 1.430000 1.795000 2.125000 1.965000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.350000 0.705000 2.570000 1.575000 ; - RECT 2.350000 1.575000 2.850000 1.955000 ; - RECT 2.360000 2.250000 3.190000 2.420000 ; - RECT 2.425000 0.265000 3.440000 0.465000 ; - RECT 2.750000 0.645000 3.100000 1.015000 ; - RECT 3.020000 1.195000 3.440000 1.235000 ; - RECT 3.020000 1.235000 4.370000 1.405000 ; - RECT 3.020000 1.405000 3.190000 2.250000 ; - RECT 3.270000 0.465000 3.440000 1.195000 ; - RECT 3.360000 1.575000 3.610000 1.835000 ; - RECT 3.360000 1.835000 4.730000 2.085000 ; - RECT 3.430000 2.255000 3.810000 2.635000 ; - RECT 3.610000 0.085000 4.020000 0.525000 ; - RECT 3.990000 2.085000 4.160000 2.375000 ; - RECT 4.120000 1.405000 4.370000 1.565000 ; - RECT 4.310000 0.295000 4.560000 0.725000 ; - RECT 4.310000 0.725000 4.730000 1.065000 ; - RECT 4.330000 2.255000 4.660000 2.635000 ; - RECT 4.540000 1.065000 4.730000 1.835000 ; - RECT 4.760000 0.085000 5.080000 0.545000 ; - RECT 4.900000 0.725000 6.150000 0.895000 ; - RECT 4.900000 0.895000 5.070000 1.655000 ; - RECT 4.900000 1.655000 5.420000 1.965000 ; - RECT 5.130000 2.165000 5.760000 2.415000 ; - RECT 5.240000 1.065000 5.420000 1.475000 ; - RECT 5.590000 1.235000 7.490000 1.405000 ; - RECT 5.590000 1.405000 5.760000 1.915000 ; - RECT 5.590000 1.915000 6.800000 2.085000 ; - RECT 5.590000 2.085000 5.760000 2.165000 ; - RECT 5.640000 0.305000 6.490000 0.475000 ; - RECT 5.820000 0.895000 6.150000 1.015000 ; - RECT 5.930000 1.575000 7.850000 1.745000 ; - RECT 5.940000 2.255000 6.360000 2.635000 ; - RECT 6.320000 0.475000 6.490000 1.235000 ; - RECT 6.560000 2.085000 6.800000 2.375000 ; - RECT 6.690000 0.085000 7.350000 0.565000 ; - RECT 7.030000 1.945000 7.360000 2.635000 ; - RECT 7.160000 1.175000 7.490000 1.235000 ; - RECT 7.530000 0.350000 7.850000 0.680000 ; - RECT 7.530000 1.745000 7.850000 1.765000 ; - RECT 7.530000 1.765000 7.700000 2.375000 ; - RECT 7.660000 0.680000 7.850000 1.575000 ; - RECT 7.970000 1.915000 8.300000 2.425000 ; - RECT 8.050000 0.345000 8.300000 0.995000 ; - RECT 8.050000 0.995000 8.850000 1.325000 ; - RECT 8.050000 1.325000 8.300000 1.915000 ; - RECT 8.480000 0.085000 8.765000 0.545000 ; - RECT 8.480000 1.835000 8.765000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.785000 0.780000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 0.765000 1.240000 0.935000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 0.765000 3.100000 0.935000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.250000 1.105000 5.420000 1.275000 ; - RECT 5.250000 1.785000 5.420000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.755000 0.840000 1.800000 ; - RECT 0.550000 1.800000 5.480000 1.940000 ; - RECT 0.550000 1.940000 0.840000 1.985000 ; - RECT 1.010000 0.735000 1.300000 0.780000 ; - RECT 1.010000 0.780000 3.160000 0.920000 ; - RECT 1.010000 0.920000 1.300000 0.965000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 0.735000 3.160000 0.780000 ; - RECT 2.870000 0.920000 3.160000 0.965000 ; - RECT 2.945000 0.965000 3.160000 1.120000 ; - RECT 2.945000 1.120000 5.480000 1.260000 ; - RECT 5.190000 1.075000 5.480000 1.120000 ; - RECT 5.190000 1.260000 5.480000 1.305000 ; - RECT 5.190000 1.755000 5.480000 1.800000 ; - RECT 5.190000 1.940000 5.480000 1.985000 ; - END -END sky130_fd_sc_hd__dfstp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfstp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfstp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.770000 1.005000 2.180000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.810000 1.495000 9.575000 1.615000 ; - RECT 8.810000 1.615000 9.140000 2.460000 ; - RECT 8.890000 0.265000 9.135000 0.765000 ; - RECT 8.890000 0.765000 9.575000 0.825000 ; - RECT 8.975000 0.825000 9.575000 0.855000 ; - RECT 8.975000 1.445000 9.575000 1.495000 ; - RECT 8.990000 0.855000 9.575000 0.895000 ; - RECT 9.020000 0.895000 9.575000 1.445000 ; - END - END Q - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.610000 0.735000 4.020000 1.065000 ; - LAYER mcon ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 6.660000 0.735000 7.340000 1.005000 ; - RECT 6.660000 1.005000 7.010000 1.065000 ; - LAYER mcon ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 7.275000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.435000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.835000 0.805000 ; - RECT 0.085000 1.795000 0.835000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.835000 1.795000 ; - RECT 1.005000 0.565000 1.235000 2.045000 ; - RECT 1.015000 0.345000 1.235000 0.565000 ; - RECT 1.015000 2.045000 1.235000 2.465000 ; - RECT 1.430000 0.635000 2.125000 0.825000 ; - RECT 1.430000 0.825000 1.600000 1.795000 ; - RECT 1.430000 1.795000 2.125000 1.965000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.350000 0.705000 2.570000 1.575000 ; - RECT 2.350000 1.575000 2.850000 1.955000 ; - RECT 2.360000 2.250000 3.190000 2.420000 ; - RECT 2.425000 0.265000 3.440000 0.465000 ; - RECT 2.750000 0.645000 3.100000 1.015000 ; - RECT 3.020000 1.195000 3.440000 1.235000 ; - RECT 3.020000 1.235000 4.370000 1.405000 ; - RECT 3.020000 1.405000 3.190000 2.250000 ; - RECT 3.270000 0.465000 3.440000 1.195000 ; - RECT 3.360000 1.575000 3.610000 1.835000 ; - RECT 3.360000 1.835000 4.710000 2.085000 ; - RECT 3.430000 2.255000 3.810000 2.635000 ; - RECT 3.610000 0.085000 4.020000 0.525000 ; - RECT 3.990000 2.085000 4.160000 2.375000 ; - RECT 4.120000 1.405000 4.370000 1.565000 ; - RECT 4.310000 0.295000 4.560000 0.725000 ; - RECT 4.310000 0.725000 4.710000 1.065000 ; - RECT 4.330000 2.255000 4.660000 2.635000 ; - RECT 4.540000 1.065000 4.710000 1.835000 ; - RECT 4.760000 0.085000 5.080000 0.545000 ; - RECT 4.880000 0.725000 6.150000 0.895000 ; - RECT 4.880000 0.895000 5.050000 1.655000 ; - RECT 4.880000 1.655000 5.400000 1.965000 ; - RECT 5.110000 2.165000 5.740000 2.415000 ; - RECT 5.220000 1.065000 5.400000 1.475000 ; - RECT 5.570000 1.235000 7.490000 1.405000 ; - RECT 5.570000 1.405000 5.740000 1.915000 ; - RECT 5.570000 1.915000 6.780000 2.085000 ; - RECT 5.570000 2.085000 5.740000 2.165000 ; - RECT 5.640000 0.305000 6.490000 0.475000 ; - RECT 5.800000 0.895000 6.150000 1.015000 ; - RECT 5.910000 1.575000 7.880000 1.745000 ; - RECT 5.920000 2.255000 6.340000 2.635000 ; - RECT 6.320000 0.475000 6.490000 1.235000 ; - RECT 6.540000 2.085000 6.780000 2.375000 ; - RECT 6.690000 0.085000 7.330000 0.565000 ; - RECT 7.010000 1.945000 7.340000 2.635000 ; - RECT 7.140000 1.175000 7.490000 1.235000 ; - RECT 7.510000 1.745000 7.880000 1.765000 ; - RECT 7.510000 1.765000 7.680000 2.375000 ; - RECT 7.530000 0.350000 7.880000 0.680000 ; - RECT 7.690000 0.680000 7.880000 1.575000 ; - RECT 7.970000 1.915000 8.300000 2.425000 ; - RECT 8.050000 0.345000 8.220000 0.995000 ; - RECT 8.050000 0.995000 8.850000 1.325000 ; - RECT 8.050000 1.325000 8.300000 1.915000 ; - RECT 8.390000 0.085000 8.720000 0.825000 ; - RECT 8.470000 1.495000 8.640000 2.635000 ; - RECT 9.305000 0.085000 9.575000 0.595000 ; - RECT 9.310000 1.785000 9.575000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 1.785000 0.775000 1.955000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 0.765000 1.235000 0.935000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 0.765000 3.075000 0.935000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.225000 1.105000 5.395000 1.275000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.545000 1.755000 0.835000 1.800000 ; - RECT 0.545000 1.800000 5.435000 1.940000 ; - RECT 0.545000 1.940000 0.835000 1.985000 ; - RECT 1.005000 0.735000 1.295000 0.780000 ; - RECT 1.005000 0.780000 3.135000 0.920000 ; - RECT 1.005000 0.920000 1.295000 0.965000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.845000 0.735000 3.135000 0.780000 ; - RECT 2.845000 0.920000 3.135000 0.965000 ; - RECT 2.920000 0.965000 3.135000 1.120000 ; - RECT 2.920000 1.120000 5.455000 1.260000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 5.165000 1.075000 5.455000 1.120000 ; - RECT 5.165000 1.260000 5.455000 1.305000 ; - END -END sky130_fd_sc_hd__dfstp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfstp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfstp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.770000 1.005000 2.180000 1.625000 ; - END - END D - PIN Q - ANTENNADIFFAREA 1.320000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.925000 0.265000 9.170000 0.715000 ; - RECT 8.925000 0.715000 10.955000 0.885000 ; - RECT 8.925000 1.470000 10.955000 1.640000 ; - RECT 8.925000 1.640000 9.170000 2.465000 ; - RECT 9.765000 0.265000 9.935000 0.715000 ; - RECT 9.765000 1.640000 9.935000 2.465000 ; - RECT 10.605000 0.265000 10.955000 0.715000 ; - RECT 10.605000 1.640000 10.955000 2.465000 ; - RECT 10.725000 0.885000 10.955000 1.470000 ; - END - END Q - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.610000 0.735000 4.020000 1.065000 ; - LAYER mcon ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 6.660000 0.735000 7.320000 1.005000 ; - RECT 6.660000 1.005000 6.990000 1.065000 ; - LAYER mcon ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 7.275000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.430000 0.635000 2.125000 0.825000 ; - RECT 1.430000 0.825000 1.600000 1.795000 ; - RECT 1.430000 1.795000 2.125000 1.965000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.135000 1.785000 2.635000 ; - RECT 1.955000 0.305000 2.125000 0.635000 ; - RECT 1.955000 1.965000 2.125000 2.465000 ; - RECT 2.350000 0.705000 2.570000 1.575000 ; - RECT 2.350000 1.575000 2.850000 1.955000 ; - RECT 2.360000 2.250000 3.190000 2.420000 ; - RECT 2.425000 0.265000 3.440000 0.465000 ; - RECT 2.750000 0.645000 3.100000 1.015000 ; - RECT 3.020000 1.195000 3.440000 1.235000 ; - RECT 3.020000 1.235000 4.370000 1.405000 ; - RECT 3.020000 1.405000 3.190000 2.250000 ; - RECT 3.270000 0.465000 3.440000 1.195000 ; - RECT 3.360000 1.575000 3.610000 1.835000 ; - RECT 3.360000 1.835000 4.710000 2.085000 ; - RECT 3.430000 2.255000 3.810000 2.635000 ; - RECT 3.610000 0.085000 4.020000 0.525000 ; - RECT 3.990000 2.085000 4.160000 2.375000 ; - RECT 4.120000 1.405000 4.370000 1.565000 ; - RECT 4.310000 0.295000 4.560000 0.725000 ; - RECT 4.310000 0.725000 4.710000 1.065000 ; - RECT 4.330000 2.255000 4.660000 2.635000 ; - RECT 4.540000 1.065000 4.710000 1.835000 ; - RECT 4.740000 0.085000 5.080000 0.545000 ; - RECT 4.880000 0.725000 6.150000 0.895000 ; - RECT 4.880000 0.895000 5.050000 1.655000 ; - RECT 4.880000 1.655000 5.400000 1.965000 ; - RECT 5.110000 2.165000 5.740000 2.415000 ; - RECT 5.220000 1.065000 5.400000 1.475000 ; - RECT 5.570000 1.235000 7.470000 1.405000 ; - RECT 5.570000 1.405000 5.740000 1.915000 ; - RECT 5.570000 1.915000 6.780000 2.085000 ; - RECT 5.570000 2.085000 5.740000 2.165000 ; - RECT 5.640000 0.305000 6.490000 0.475000 ; - RECT 5.820000 0.895000 6.150000 1.015000 ; - RECT 5.910000 1.575000 7.850000 1.745000 ; - RECT 5.920000 2.255000 6.340000 2.635000 ; - RECT 6.320000 0.475000 6.490000 1.235000 ; - RECT 6.540000 2.085000 6.780000 2.375000 ; - RECT 6.670000 0.085000 7.330000 0.565000 ; - RECT 7.010000 1.945000 7.340000 2.635000 ; - RECT 7.140000 1.175000 7.470000 1.235000 ; - RECT 7.510000 0.350000 7.850000 0.680000 ; - RECT 7.510000 1.745000 7.850000 1.765000 ; - RECT 7.510000 1.765000 7.680000 2.375000 ; - RECT 7.640000 0.680000 7.850000 1.575000 ; - RECT 7.950000 1.915000 8.280000 2.425000 ; - RECT 8.030000 0.345000 8.280000 1.055000 ; - RECT 8.030000 1.055000 10.555000 1.275000 ; - RECT 8.030000 1.275000 8.280000 1.915000 ; - RECT 8.460000 0.085000 8.745000 0.545000 ; - RECT 8.460000 1.835000 8.745000 2.635000 ; - RECT 9.340000 0.085000 9.595000 0.545000 ; - RECT 9.340000 1.810000 9.595000 2.635000 ; - RECT 10.105000 0.085000 10.435000 0.545000 ; - RECT 10.105000 1.810000 10.435000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.615000 1.785000 0.785000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 0.765000 1.235000 0.935000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 0.765000 3.075000 0.935000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.225000 1.105000 5.395000 1.275000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.555000 1.755000 0.845000 1.800000 ; - RECT 0.555000 1.800000 5.435000 1.940000 ; - RECT 0.555000 1.940000 0.845000 1.985000 ; - RECT 1.005000 0.735000 1.295000 0.780000 ; - RECT 1.005000 0.780000 3.135000 0.920000 ; - RECT 1.005000 0.920000 1.295000 0.965000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.845000 0.735000 3.135000 0.780000 ; - RECT 2.845000 0.920000 3.135000 0.965000 ; - RECT 2.920000 0.965000 3.135000 1.120000 ; - RECT 2.920000 1.120000 5.455000 1.260000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 5.165000 1.075000 5.455000 1.120000 ; - RECT 5.165000 1.260000 5.455000 1.305000 ; - END -END sky130_fd_sc_hd__dfstp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfxbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfxbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.370000 0.715000 1.650000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.890000 1.495000 7.300000 1.575000 ; - RECT 6.890000 1.575000 7.220000 2.420000 ; - RECT 6.900000 0.305000 7.230000 0.740000 ; - RECT 6.900000 0.740000 7.300000 0.825000 ; - RECT 7.055000 0.825000 7.300000 0.865000 ; - RECT 7.065000 1.445000 7.300000 1.495000 ; - RECT 7.110000 0.865000 7.300000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.315000 1.480000 8.650000 2.465000 ; - RECT 8.395000 0.255000 8.650000 0.910000 ; - RECT 8.415000 0.910000 8.650000 1.480000 ; - END - END Q_N - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.200000 2.465000 ; - RECT 1.440000 2.175000 1.705000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.820000 0.675000 2.045000 0.805000 ; - RECT 1.820000 0.805000 1.990000 1.910000 ; - RECT 1.820000 1.910000 2.125000 2.040000 ; - RECT 1.875000 0.365000 2.210000 0.535000 ; - RECT 1.875000 0.535000 2.045000 0.675000 ; - RECT 1.875000 2.040000 2.125000 2.465000 ; - RECT 2.160000 1.125000 2.400000 1.720000 ; - RECT 2.215000 0.735000 2.740000 0.955000 ; - RECT 2.335000 2.190000 3.440000 2.360000 ; - RECT 2.405000 0.365000 3.080000 0.535000 ; - RECT 2.570000 0.955000 2.740000 1.655000 ; - RECT 2.570000 1.655000 3.100000 2.020000 ; - RECT 2.910000 0.535000 3.080000 1.315000 ; - RECT 2.910000 1.315000 3.780000 1.485000 ; - RECT 3.270000 1.485000 3.780000 1.575000 ; - RECT 3.270000 1.575000 3.440000 2.190000 ; - RECT 3.290000 0.765000 4.120000 1.065000 ; - RECT 3.290000 1.065000 3.490000 1.095000 ; - RECT 3.400000 0.085000 3.770000 0.585000 ; - RECT 3.610000 1.245000 3.780000 1.315000 ; - RECT 3.610000 1.835000 3.780000 2.635000 ; - RECT 3.950000 0.365000 4.355000 0.535000 ; - RECT 3.950000 0.535000 4.120000 0.765000 ; - RECT 3.950000 1.065000 4.120000 2.135000 ; - RECT 3.950000 2.135000 4.200000 2.465000 ; - RECT 4.290000 1.245000 4.480000 1.965000 ; - RECT 4.425000 2.165000 5.310000 2.335000 ; - RECT 4.505000 0.705000 4.970000 1.035000 ; - RECT 4.525000 0.365000 5.310000 0.535000 ; - RECT 4.650000 1.035000 4.970000 1.995000 ; - RECT 5.140000 0.535000 5.310000 0.995000 ; - RECT 5.140000 0.995000 6.020000 1.325000 ; - RECT 5.140000 1.325000 5.310000 2.165000 ; - RECT 5.480000 1.530000 6.380000 1.905000 ; - RECT 5.490000 2.135000 5.805000 2.635000 ; - RECT 5.585000 0.085000 5.795000 0.615000 ; - RECT 6.040000 1.905000 6.380000 2.465000 ; - RECT 6.060000 0.300000 6.390000 0.825000 ; - RECT 6.190000 0.825000 6.390000 0.995000 ; - RECT 6.190000 0.995000 6.940000 1.325000 ; - RECT 6.190000 1.325000 6.380000 1.530000 ; - RECT 6.550000 1.625000 6.720000 2.635000 ; - RECT 6.560000 0.085000 6.730000 0.695000 ; - RECT 7.410000 1.715000 7.740000 2.445000 ; - RECT 7.420000 0.345000 7.670000 0.615000 ; - RECT 7.470000 0.615000 7.670000 0.995000 ; - RECT 7.470000 0.995000 8.245000 1.325000 ; - RECT 7.470000 1.325000 7.740000 1.715000 ; - RECT 7.905000 0.085000 8.225000 0.545000 ; - RECT 7.930000 1.495000 8.145000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.630000 1.785000 0.800000 1.955000 ; - RECT 1.025000 1.445000 1.195000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.215000 1.445000 2.385000 1.615000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.730000 1.785000 2.900000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.300000 1.785000 4.470000 1.955000 ; - RECT 4.735000 1.445000 4.905000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - LAYER met1 ; - RECT 0.570000 1.755000 0.860000 1.800000 ; - RECT 0.570000 1.800000 4.530000 1.940000 ; - RECT 0.570000 1.940000 0.860000 1.985000 ; - RECT 0.965000 1.415000 1.255000 1.460000 ; - RECT 0.965000 1.460000 4.965000 1.600000 ; - RECT 0.965000 1.600000 1.255000 1.645000 ; - RECT 2.155000 1.415000 2.445000 1.460000 ; - RECT 2.155000 1.600000 2.445000 1.645000 ; - RECT 2.670000 1.755000 2.960000 1.800000 ; - RECT 2.670000 1.940000 2.960000 1.985000 ; - RECT 4.240000 1.755000 4.530000 1.800000 ; - RECT 4.240000 1.940000 4.530000 1.985000 ; - RECT 4.675000 1.415000 4.965000 1.460000 ; - RECT 4.675000 1.600000 4.965000 1.645000 ; - END -END sky130_fd_sc_hd__dfxbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfxbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfxbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.370000 0.715000 1.650000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.890000 1.495000 7.300000 1.575000 ; - RECT 6.890000 1.575000 7.220000 2.420000 ; - RECT 6.900000 0.305000 7.230000 0.740000 ; - RECT 6.900000 0.740000 7.300000 0.825000 ; - RECT 7.055000 0.825000 7.300000 0.865000 ; - RECT 7.065000 1.445000 7.300000 1.495000 ; - RECT 7.110000 0.865000 7.300000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.810000 1.495000 9.145000 2.465000 ; - RECT 8.890000 0.265000 9.145000 0.885000 ; - RECT 8.930000 0.885000 9.145000 1.495000 ; - END - END Q_N - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.200000 2.465000 ; - RECT 1.440000 2.175000 1.705000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.820000 0.675000 2.045000 0.805000 ; - RECT 1.820000 0.805000 1.990000 1.910000 ; - RECT 1.820000 1.910000 2.125000 2.040000 ; - RECT 1.875000 0.365000 2.210000 0.535000 ; - RECT 1.875000 0.535000 2.045000 0.675000 ; - RECT 1.875000 2.040000 2.125000 2.465000 ; - RECT 2.160000 1.125000 2.400000 1.720000 ; - RECT 2.215000 0.735000 2.740000 0.955000 ; - RECT 2.335000 2.190000 3.440000 2.360000 ; - RECT 2.405000 0.365000 3.080000 0.535000 ; - RECT 2.570000 0.955000 2.740000 1.655000 ; - RECT 2.570000 1.655000 3.100000 2.020000 ; - RECT 2.910000 0.535000 3.080000 1.315000 ; - RECT 2.910000 1.315000 3.780000 1.485000 ; - RECT 3.270000 1.485000 3.780000 1.575000 ; - RECT 3.270000 1.575000 3.440000 2.190000 ; - RECT 3.290000 0.765000 4.120000 1.065000 ; - RECT 3.290000 1.065000 3.490000 1.095000 ; - RECT 3.400000 0.085000 3.770000 0.585000 ; - RECT 3.610000 1.245000 3.780000 1.315000 ; - RECT 3.610000 1.835000 3.780000 2.635000 ; - RECT 3.950000 0.365000 4.355000 0.535000 ; - RECT 3.950000 0.535000 4.120000 0.765000 ; - RECT 3.950000 1.065000 4.120000 2.135000 ; - RECT 3.950000 2.135000 4.200000 2.465000 ; - RECT 4.290000 1.245000 4.480000 1.965000 ; - RECT 4.425000 2.165000 5.310000 2.335000 ; - RECT 4.505000 0.705000 4.970000 1.035000 ; - RECT 4.525000 0.365000 5.310000 0.535000 ; - RECT 4.650000 1.035000 4.970000 1.995000 ; - RECT 5.140000 0.535000 5.310000 0.995000 ; - RECT 5.140000 0.995000 6.020000 1.325000 ; - RECT 5.140000 1.325000 5.310000 2.165000 ; - RECT 5.480000 1.530000 6.380000 1.905000 ; - RECT 5.490000 2.135000 5.805000 2.635000 ; - RECT 5.585000 0.085000 5.795000 0.615000 ; - RECT 6.040000 1.905000 6.380000 2.465000 ; - RECT 6.060000 0.300000 6.390000 0.825000 ; - RECT 6.190000 0.825000 6.390000 0.995000 ; - RECT 6.190000 0.995000 6.940000 1.325000 ; - RECT 6.190000 1.325000 6.380000 1.530000 ; - RECT 6.550000 1.625000 6.720000 2.635000 ; - RECT 6.560000 0.085000 6.730000 0.695000 ; - RECT 7.390000 1.720000 7.565000 2.635000 ; - RECT 7.400000 0.085000 7.570000 0.600000 ; - RECT 7.905000 0.345000 8.165000 0.615000 ; - RECT 7.905000 1.715000 8.235000 2.445000 ; - RECT 7.965000 0.615000 8.165000 0.995000 ; - RECT 7.965000 0.995000 8.760000 1.325000 ; - RECT 7.965000 1.325000 8.235000 1.715000 ; - RECT 8.390000 0.085000 8.720000 0.825000 ; - RECT 8.425000 1.495000 8.640000 2.635000 ; - RECT 9.315000 0.085000 9.565000 0.905000 ; - RECT 9.315000 1.495000 9.565000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.630000 1.785000 0.800000 1.955000 ; - RECT 1.025000 1.445000 1.195000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.215000 1.445000 2.385000 1.615000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.730000 1.785000 2.900000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.300000 1.785000 4.470000 1.955000 ; - RECT 4.735000 1.445000 4.905000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.570000 1.755000 0.860000 1.800000 ; - RECT 0.570000 1.800000 4.530000 1.940000 ; - RECT 0.570000 1.940000 0.860000 1.985000 ; - RECT 0.965000 1.415000 1.255000 1.460000 ; - RECT 0.965000 1.460000 4.965000 1.600000 ; - RECT 0.965000 1.600000 1.255000 1.645000 ; - RECT 2.155000 1.415000 2.445000 1.460000 ; - RECT 2.155000 1.600000 2.445000 1.645000 ; - RECT 2.670000 1.755000 2.960000 1.800000 ; - RECT 2.670000 1.940000 2.960000 1.985000 ; - RECT 4.240000 1.755000 4.530000 1.800000 ; - RECT 4.240000 1.940000 4.530000 1.985000 ; - RECT 4.675000 1.415000 4.965000 1.460000 ; - RECT 4.675000 1.600000 4.965000 1.645000 ; - END -END sky130_fd_sc_hd__dfxbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfxtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfxtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.370000 0.715000 1.650000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.885000 1.495000 7.275000 1.575000 ; - RECT 6.885000 1.575000 7.215000 2.420000 ; - RECT 6.895000 0.305000 7.225000 0.740000 ; - RECT 6.895000 0.740000 7.275000 0.825000 ; - RECT 7.050000 0.825000 7.275000 0.865000 ; - RECT 7.060000 1.445000 7.275000 1.495000 ; - RECT 7.105000 0.865000 7.275000 1.445000 ; - END - END Q - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.200000 2.465000 ; - RECT 1.440000 2.175000 1.705000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.820000 0.675000 2.045000 0.805000 ; - RECT 1.820000 0.805000 1.990000 1.910000 ; - RECT 1.820000 1.910000 2.125000 2.040000 ; - RECT 1.875000 0.365000 2.210000 0.535000 ; - RECT 1.875000 0.535000 2.045000 0.675000 ; - RECT 1.875000 2.040000 2.125000 2.465000 ; - RECT 2.160000 1.125000 2.400000 1.720000 ; - RECT 2.215000 0.735000 2.740000 0.955000 ; - RECT 2.335000 2.190000 3.440000 2.360000 ; - RECT 2.405000 0.365000 3.080000 0.535000 ; - RECT 2.570000 0.955000 2.740000 1.655000 ; - RECT 2.570000 1.655000 3.100000 2.020000 ; - RECT 2.910000 0.535000 3.080000 1.315000 ; - RECT 2.910000 1.315000 3.780000 1.485000 ; - RECT 3.270000 1.485000 3.780000 1.575000 ; - RECT 3.270000 1.575000 3.440000 2.190000 ; - RECT 3.290000 0.765000 4.120000 1.065000 ; - RECT 3.290000 1.065000 3.490000 1.095000 ; - RECT 3.400000 0.085000 3.770000 0.585000 ; - RECT 3.610000 1.245000 3.780000 1.315000 ; - RECT 3.610000 1.835000 3.780000 2.635000 ; - RECT 3.950000 0.365000 4.355000 0.535000 ; - RECT 3.950000 0.535000 4.120000 0.765000 ; - RECT 3.950000 1.065000 4.120000 2.135000 ; - RECT 3.950000 2.135000 4.200000 2.465000 ; - RECT 4.290000 1.245000 4.480000 1.965000 ; - RECT 4.425000 2.165000 5.310000 2.335000 ; - RECT 4.505000 0.705000 4.970000 1.035000 ; - RECT 4.525000 0.365000 5.310000 0.535000 ; - RECT 4.650000 1.035000 4.970000 1.995000 ; - RECT 5.140000 0.535000 5.310000 0.995000 ; - RECT 5.140000 0.995000 6.015000 1.325000 ; - RECT 5.140000 1.325000 5.310000 2.165000 ; - RECT 5.480000 1.530000 6.375000 1.905000 ; - RECT 5.490000 2.135000 5.805000 2.635000 ; - RECT 5.585000 0.085000 5.795000 0.615000 ; - RECT 6.035000 1.905000 6.375000 2.465000 ; - RECT 6.055000 0.300000 6.385000 0.825000 ; - RECT 6.185000 0.825000 6.385000 0.995000 ; - RECT 6.185000 0.995000 6.935000 1.325000 ; - RECT 6.185000 1.325000 6.375000 1.530000 ; - RECT 6.545000 1.625000 6.715000 2.635000 ; - RECT 6.555000 0.085000 6.725000 0.695000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.630000 1.785000 0.800000 1.955000 ; - RECT 1.025000 1.445000 1.195000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.215000 1.445000 2.385000 1.615000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.730000 1.785000 2.900000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.300000 1.785000 4.470000 1.955000 ; - RECT 4.735000 1.445000 4.905000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - LAYER met1 ; - RECT 0.570000 1.755000 0.860000 1.800000 ; - RECT 0.570000 1.800000 4.530000 1.940000 ; - RECT 0.570000 1.940000 0.860000 1.985000 ; - RECT 0.965000 1.415000 1.255000 1.460000 ; - RECT 0.965000 1.460000 4.965000 1.600000 ; - RECT 0.965000 1.600000 1.255000 1.645000 ; - RECT 2.155000 1.415000 2.445000 1.460000 ; - RECT 2.155000 1.600000 2.445000 1.645000 ; - RECT 2.670000 1.755000 2.960000 1.800000 ; - RECT 2.670000 1.940000 2.960000 1.985000 ; - RECT 4.240000 1.755000 4.530000 1.800000 ; - RECT 4.240000 1.940000 4.530000 1.985000 ; - RECT 4.675000 1.415000 4.965000 1.460000 ; - RECT 4.675000 1.600000 4.965000 1.645000 ; - END -END sky130_fd_sc_hd__dfxtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfxtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfxtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.370000 0.715000 1.650000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.885000 1.495000 7.275000 1.575000 ; - RECT 6.885000 1.575000 7.215000 2.420000 ; - RECT 6.895000 0.305000 7.225000 0.740000 ; - RECT 6.895000 0.740000 7.275000 0.825000 ; - RECT 7.050000 0.825000 7.275000 0.865000 ; - RECT 7.060000 1.445000 7.275000 1.495000 ; - RECT 7.105000 0.865000 7.275000 1.445000 ; - END - END Q - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.200000 2.465000 ; - RECT 1.440000 2.175000 1.705000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.820000 0.675000 2.045000 0.805000 ; - RECT 1.820000 0.805000 1.990000 1.910000 ; - RECT 1.820000 1.910000 2.125000 2.040000 ; - RECT 1.875000 0.365000 2.210000 0.535000 ; - RECT 1.875000 0.535000 2.045000 0.675000 ; - RECT 1.875000 2.040000 2.125000 2.465000 ; - RECT 2.160000 1.125000 2.400000 1.720000 ; - RECT 2.215000 0.735000 2.740000 0.955000 ; - RECT 2.335000 2.190000 3.440000 2.360000 ; - RECT 2.405000 0.365000 3.080000 0.535000 ; - RECT 2.570000 0.955000 2.740000 1.655000 ; - RECT 2.570000 1.655000 3.100000 2.020000 ; - RECT 2.910000 0.535000 3.080000 1.315000 ; - RECT 2.910000 1.315000 3.780000 1.485000 ; - RECT 3.270000 1.485000 3.780000 1.575000 ; - RECT 3.270000 1.575000 3.440000 2.190000 ; - RECT 3.290000 0.765000 4.120000 1.065000 ; - RECT 3.290000 1.065000 3.490000 1.095000 ; - RECT 3.400000 0.085000 3.770000 0.585000 ; - RECT 3.610000 1.245000 3.780000 1.315000 ; - RECT 3.610000 1.835000 3.780000 2.635000 ; - RECT 3.950000 0.365000 4.355000 0.535000 ; - RECT 3.950000 0.535000 4.120000 0.765000 ; - RECT 3.950000 1.065000 4.120000 2.135000 ; - RECT 3.950000 2.135000 4.200000 2.465000 ; - RECT 4.290000 1.245000 4.480000 1.965000 ; - RECT 4.425000 2.165000 5.310000 2.335000 ; - RECT 4.505000 0.705000 4.970000 1.035000 ; - RECT 4.525000 0.365000 5.310000 0.535000 ; - RECT 4.650000 1.035000 4.970000 1.995000 ; - RECT 5.140000 0.535000 5.310000 0.995000 ; - RECT 5.140000 0.995000 6.015000 1.325000 ; - RECT 5.140000 1.325000 5.310000 2.165000 ; - RECT 5.480000 1.530000 6.375000 1.905000 ; - RECT 5.490000 2.135000 5.805000 2.635000 ; - RECT 5.585000 0.085000 5.795000 0.615000 ; - RECT 6.035000 1.905000 6.375000 2.465000 ; - RECT 6.055000 0.300000 6.385000 0.825000 ; - RECT 6.185000 0.825000 6.385000 0.995000 ; - RECT 6.185000 0.995000 6.935000 1.325000 ; - RECT 6.185000 1.325000 6.375000 1.530000 ; - RECT 6.545000 1.625000 6.715000 2.635000 ; - RECT 6.555000 0.085000 6.725000 0.695000 ; - RECT 7.385000 1.720000 7.555000 2.635000 ; - RECT 7.395000 0.085000 7.565000 0.600000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.630000 1.785000 0.800000 1.955000 ; - RECT 1.025000 1.445000 1.195000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.215000 1.445000 2.385000 1.615000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.730000 1.785000 2.900000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.300000 1.785000 4.470000 1.955000 ; - RECT 4.735000 1.445000 4.905000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 0.570000 1.755000 0.860000 1.800000 ; - RECT 0.570000 1.800000 4.530000 1.940000 ; - RECT 0.570000 1.940000 0.860000 1.985000 ; - RECT 0.965000 1.415000 1.255000 1.460000 ; - RECT 0.965000 1.460000 4.965000 1.600000 ; - RECT 0.965000 1.600000 1.255000 1.645000 ; - RECT 2.155000 1.415000 2.445000 1.460000 ; - RECT 2.155000 1.600000 2.445000 1.645000 ; - RECT 2.670000 1.755000 2.960000 1.800000 ; - RECT 2.670000 1.940000 2.960000 1.985000 ; - RECT 4.240000 1.755000 4.530000 1.800000 ; - RECT 4.240000 1.940000 4.530000 1.985000 ; - RECT 4.675000 1.415000 4.965000 1.460000 ; - RECT 4.675000 1.600000 4.965000 1.645000 ; - END -END sky130_fd_sc_hd__dfxtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dfxtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dfxtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.440000 1.065000 1.720000 1.665000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.985000 0.305000 7.320000 0.730000 ; - RECT 6.985000 0.730000 8.655000 0.900000 ; - RECT 6.985000 1.465000 8.655000 1.635000 ; - RECT 6.985000 1.635000 7.320000 2.395000 ; - RECT 7.840000 0.305000 8.175000 0.730000 ; - RECT 7.840000 1.635000 8.170000 2.395000 ; - RECT 8.410000 0.900000 8.655000 1.465000 ; - END - END Q - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.975000 0.440000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.840000 0.805000 ; - RECT 0.175000 1.795000 0.840000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.840000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.440000 2.175000 1.705000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.890000 0.365000 2.220000 0.535000 ; - RECT 1.890000 0.535000 2.060000 2.065000 ; - RECT 1.890000 2.065000 2.125000 2.440000 ; - RECT 2.230000 0.705000 2.810000 1.035000 ; - RECT 2.230000 1.035000 2.470000 1.905000 ; - RECT 2.370000 2.190000 3.440000 2.360000 ; - RECT 2.400000 0.365000 3.150000 0.535000 ; - RECT 2.660000 1.655000 3.100000 2.010000 ; - RECT 2.980000 0.535000 3.150000 1.315000 ; - RECT 2.980000 1.315000 3.780000 1.485000 ; - RECT 3.270000 1.485000 3.780000 1.575000 ; - RECT 3.270000 1.575000 3.440000 2.190000 ; - RECT 3.320000 0.765000 4.120000 1.065000 ; - RECT 3.320000 1.065000 3.490000 1.095000 ; - RECT 3.400000 0.085000 3.770000 0.585000 ; - RECT 3.610000 1.245000 3.780000 1.315000 ; - RECT 3.610000 1.835000 3.780000 2.635000 ; - RECT 3.950000 0.365000 4.410000 0.535000 ; - RECT 3.950000 0.535000 4.120000 0.765000 ; - RECT 3.950000 1.065000 4.120000 2.135000 ; - RECT 3.950000 2.135000 4.200000 2.465000 ; - RECT 4.290000 0.705000 4.840000 1.035000 ; - RECT 4.290000 1.245000 4.480000 1.965000 ; - RECT 4.425000 2.165000 5.310000 2.335000 ; - RECT 4.640000 0.365000 5.310000 0.535000 ; - RECT 4.650000 1.035000 4.840000 1.575000 ; - RECT 4.650000 1.575000 4.970000 1.905000 ; - RECT 5.140000 0.535000 5.310000 1.075000 ; - RECT 5.140000 1.075000 6.230000 1.245000 ; - RECT 5.140000 1.245000 5.310000 2.165000 ; - RECT 5.480000 1.500000 6.590000 1.670000 ; - RECT 5.480000 1.670000 6.340000 1.830000 ; - RECT 5.490000 2.135000 5.705000 2.635000 ; - RECT 5.625000 0.085000 5.795000 0.615000 ; - RECT 6.090000 0.295000 6.450000 0.735000 ; - RECT 6.090000 0.735000 6.590000 0.905000 ; - RECT 6.170000 1.830000 6.340000 2.455000 ; - RECT 6.420000 0.905000 6.590000 1.075000 ; - RECT 6.420000 1.075000 8.240000 1.245000 ; - RECT 6.420000 1.245000 6.590000 1.500000 ; - RECT 6.625000 0.085000 6.795000 0.565000 ; - RECT 6.625000 1.855000 6.805000 2.635000 ; - RECT 7.495000 0.085000 7.665000 0.560000 ; - RECT 7.500000 1.805000 7.670000 2.635000 ; - RECT 8.340000 1.805000 8.510000 2.635000 ; - RECT 8.345000 0.085000 8.515000 0.560000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.785000 0.780000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 0.765000 1.240000 0.935000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 0.765000 2.640000 0.935000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.785000 3.100000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.310000 0.765000 4.480000 0.935000 ; - RECT 4.310000 1.785000 4.480000 1.955000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.755000 0.840000 1.800000 ; - RECT 0.550000 1.800000 4.540000 1.940000 ; - RECT 0.550000 1.940000 0.840000 1.985000 ; - RECT 1.010000 0.735000 1.300000 0.780000 ; - RECT 1.010000 0.780000 4.540000 0.920000 ; - RECT 1.010000 0.920000 1.300000 0.965000 ; - RECT 2.410000 0.735000 2.700000 0.780000 ; - RECT 2.410000 0.920000 2.700000 0.965000 ; - RECT 2.870000 1.755000 3.160000 1.800000 ; - RECT 2.870000 1.940000 3.160000 1.985000 ; - RECT 4.250000 0.735000 4.540000 0.780000 ; - RECT 4.250000 0.920000 4.540000 0.965000 ; - RECT 4.250000 1.755000 4.540000 1.800000 ; - RECT 4.250000 1.940000 4.540000 1.985000 ; - END -END sky130_fd_sc_hd__dfxtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__diode_2 - CLASS CORE ANTENNACELL ; - FOREIGN sky130_fd_sc_hd__diode_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.920000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN DIODE - ANTENNADIFFAREA 0.434700 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.835000 2.465000 ; - END - END DIODE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.920000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.110000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.920000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.920000 0.085000 ; - RECT 0.000000 2.635000 0.920000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - END -END sky130_fd_sc_hd__diode_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlclkp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlclkp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 1.435000 2.185000 1.685000 ; - RECT 1.985000 0.385000 2.185000 1.435000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.055000 0.255000 6.355000 0.595000 ; - RECT 6.090000 1.495000 6.355000 2.455000 ; - RECT 6.170000 0.595000 6.355000 1.495000 ; - END - END GCLK - PIN CLK - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - LAYER mcon ; - RECT 0.145000 1.105000 0.315000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.190000 1.105000 5.510000 1.435000 ; - LAYER mcon ; - RECT 5.210000 1.105000 5.380000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.085000 1.075000 0.380000 1.120000 ; - RECT 0.085000 1.120000 5.440000 1.260000 ; - RECT 0.085000 1.260000 0.380000 1.305000 ; - RECT 5.150000 1.075000 5.440000 1.120000 ; - RECT 5.150000 1.260000 5.440000 1.305000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 0.995000 1.355000 ; - RECT -0.190000 1.355000 6.630000 2.910000 ; - RECT 2.620000 1.305000 6.630000 1.355000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.175000 0.260000 0.345000 0.615000 ; - RECT 0.175000 0.615000 0.780000 0.785000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.785000 0.780000 1.060000 ; - RECT 0.610000 1.060000 0.840000 1.390000 ; - RECT 0.610000 1.390000 0.780000 1.795000 ; - RECT 1.015000 0.260000 1.280000 1.855000 ; - RECT 1.015000 1.855000 2.590000 2.025000 ; - RECT 1.015000 2.025000 1.240000 2.465000 ; - RECT 1.450000 2.195000 1.815000 2.635000 ; - RECT 1.480000 0.085000 1.810000 0.905000 ; - RECT 2.390000 0.815000 3.220000 0.985000 ; - RECT 2.390000 0.985000 2.590000 1.855000 ; - RECT 2.475000 2.255000 3.225000 2.425000 ; - RECT 2.790000 0.390000 3.725000 0.560000 ; - RECT 3.055000 1.155000 4.175000 1.325000 ; - RECT 3.055000 1.325000 3.225000 2.255000 ; - RECT 3.395000 2.135000 3.695000 2.635000 ; - RECT 3.430000 1.535000 4.710000 1.840000 ; - RECT 3.430000 1.840000 4.130000 1.865000 ; - RECT 3.555000 0.560000 3.725000 0.995000 ; - RECT 3.555000 0.995000 4.175000 1.155000 ; - RECT 3.895000 0.085000 4.145000 0.610000 ; - RECT 3.910000 1.865000 4.130000 2.435000 ; - RECT 4.310000 2.010000 4.595000 2.635000 ; - RECT 4.320000 0.255000 4.580000 0.615000 ; - RECT 4.345000 0.615000 4.580000 0.995000 ; - RECT 4.345000 0.995000 4.740000 1.325000 ; - RECT 4.345000 1.325000 4.710000 1.535000 ; - RECT 4.840000 0.290000 5.155000 0.620000 ; - RECT 4.935000 0.620000 5.155000 0.765000 ; - RECT 4.935000 0.765000 6.000000 0.935000 ; - RECT 5.005000 1.725000 5.920000 1.895000 ; - RECT 5.005000 1.895000 5.335000 2.465000 ; - RECT 5.570000 2.130000 5.920000 2.635000 ; - RECT 5.670000 0.085000 5.840000 0.545000 ; - RECT 5.750000 0.935000 6.000000 1.325000 ; - RECT 5.750000 1.325000 5.920000 1.725000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__dlclkp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlclkp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlclkp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 1.435000 2.215000 1.685000 ; - RECT 1.985000 0.285000 2.215000 1.435000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.060000 0.255000 6.360000 0.595000 ; - RECT 6.095000 1.495000 6.360000 2.455000 ; - RECT 6.165000 0.595000 6.360000 1.495000 ; - END - END GCLK - PIN CLK - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - LAYER mcon ; - RECT 0.150000 1.105000 0.320000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.210000 1.105000 5.485000 1.435000 ; - END - PORT - LAYER met1 ; - RECT 0.090000 1.075000 0.380000 1.120000 ; - RECT 0.090000 1.120000 5.440000 1.260000 ; - RECT 0.090000 1.260000 0.380000 1.305000 ; - RECT 5.150000 1.075000 5.440000 1.120000 ; - RECT 5.150000 1.260000 5.440000 1.305000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 0.995000 1.355000 ; - RECT -0.190000 1.355000 7.090000 2.910000 ; - RECT 2.625000 1.305000 7.090000 1.355000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.175000 0.260000 0.345000 0.615000 ; - RECT 0.175000 0.615000 0.780000 0.785000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.785000 0.780000 1.060000 ; - RECT 0.610000 1.060000 0.840000 1.390000 ; - RECT 0.610000 1.390000 0.780000 1.795000 ; - RECT 1.015000 0.260000 1.280000 1.855000 ; - RECT 1.015000 1.855000 2.645000 2.025000 ; - RECT 1.015000 2.025000 1.240000 2.465000 ; - RECT 1.455000 2.195000 1.820000 2.635000 ; - RECT 1.485000 0.085000 1.815000 0.905000 ; - RECT 2.395000 0.815000 3.225000 0.985000 ; - RECT 2.395000 0.985000 2.645000 1.855000 ; - RECT 2.480000 2.255000 3.230000 2.425000 ; - RECT 2.795000 0.390000 3.725000 0.560000 ; - RECT 3.060000 1.155000 4.180000 1.325000 ; - RECT 3.060000 1.325000 3.230000 2.255000 ; - RECT 3.400000 2.135000 3.700000 2.635000 ; - RECT 3.435000 1.535000 4.735000 1.840000 ; - RECT 3.435000 1.840000 4.135000 1.865000 ; - RECT 3.555000 0.560000 3.725000 0.995000 ; - RECT 3.555000 0.995000 4.180000 1.155000 ; - RECT 3.895000 0.085000 4.145000 0.610000 ; - RECT 3.915000 1.865000 4.135000 2.435000 ; - RECT 4.315000 0.255000 4.585000 0.615000 ; - RECT 4.315000 2.010000 4.600000 2.635000 ; - RECT 4.350000 0.615000 4.585000 0.995000 ; - RECT 4.350000 0.995000 4.735000 1.535000 ; - RECT 4.835000 0.290000 5.150000 0.620000 ; - RECT 4.930000 0.620000 5.150000 0.765000 ; - RECT 4.930000 0.765000 5.995000 0.935000 ; - RECT 5.010000 1.725000 5.925000 1.895000 ; - RECT 5.010000 1.895000 5.340000 2.465000 ; - RECT 5.575000 2.130000 5.925000 2.635000 ; - RECT 5.675000 0.085000 5.845000 0.545000 ; - RECT 5.755000 0.935000 5.995000 1.325000 ; - RECT 5.755000 1.325000 5.925000 1.725000 ; - RECT 6.530000 0.085000 6.810000 0.885000 ; - RECT 6.530000 1.485000 6.810000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - END -END sky130_fd_sc_hd__dlclkp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlclkp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlclkp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 0.765000 1.950000 1.015000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 1.039500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.040000 0.255000 6.460000 0.545000 ; - RECT 6.040000 1.835000 7.300000 2.005000 ; - RECT 6.040000 2.005000 6.370000 2.455000 ; - RECT 6.290000 0.545000 6.460000 0.715000 ; - RECT 6.290000 0.715000 7.300000 0.885000 ; - RECT 6.585000 1.785000 7.300000 1.835000 ; - RECT 6.750000 0.885000 7.300000 1.785000 ; - RECT 6.970000 0.255000 7.300000 0.715000 ; - RECT 6.970000 2.005000 7.300000 2.465000 ; - END - END GCLK - PIN CLK - ANTENNAGATEAREA 0.406500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - LAYER mcon ; - RECT 0.150000 1.105000 0.320000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.230000 1.055000 5.740000 1.325000 ; - LAYER mcon ; - RECT 5.230000 1.105000 5.400000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.090000 1.075000 0.380000 1.120000 ; - RECT 0.090000 1.120000 5.460000 1.260000 ; - RECT 0.090000 1.260000 0.380000 1.305000 ; - RECT 5.170000 1.075000 5.460000 1.120000 ; - RECT 5.170000 1.260000 5.460000 1.305000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.085000 1.795000 0.780000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.280000 1.355000 ; - RECT 1.015000 1.355000 2.335000 1.585000 ; - RECT 1.015000 1.585000 1.240000 2.465000 ; - RECT 1.450000 0.085000 1.785000 0.465000 ; - RECT 1.450000 2.195000 1.815000 2.635000 ; - RECT 1.525000 1.785000 1.695000 1.855000 ; - RECT 1.525000 1.855000 2.845000 1.905000 ; - RECT 1.525000 1.905000 2.735000 2.025000 ; - RECT 2.045000 1.585000 2.335000 1.685000 ; - RECT 2.290000 0.705000 2.735000 1.035000 ; - RECT 2.415000 0.365000 3.075000 0.535000 ; - RECT 2.475000 2.195000 3.165000 2.425000 ; - RECT 2.505000 1.575000 2.845000 1.855000 ; - RECT 2.565000 1.035000 2.735000 1.575000 ; - RECT 2.905000 0.535000 3.075000 0.995000 ; - RECT 2.905000 0.995000 3.775000 1.165000 ; - RECT 2.915000 2.060000 3.185000 2.090000 ; - RECT 2.915000 2.090000 3.180000 2.105000 ; - RECT 2.915000 2.105000 3.165000 2.195000 ; - RECT 2.980000 2.015000 3.185000 2.060000 ; - RECT 3.015000 1.165000 3.775000 1.325000 ; - RECT 3.015000 1.325000 3.185000 2.015000 ; - RECT 3.315000 0.085000 3.650000 0.530000 ; - RECT 3.335000 2.175000 3.695000 2.635000 ; - RECT 3.355000 1.535000 4.115000 1.865000 ; - RECT 3.895000 0.415000 4.115000 0.745000 ; - RECT 3.895000 1.865000 4.115000 2.435000 ; - RECT 3.945000 0.745000 4.115000 0.995000 ; - RECT 3.945000 0.995000 4.720000 1.325000 ; - RECT 3.945000 1.325000 4.115000 1.535000 ; - RECT 4.295000 0.085000 4.580000 0.715000 ; - RECT 4.295000 2.010000 4.580000 2.635000 ; - RECT 4.750000 0.290000 5.060000 0.715000 ; - RECT 4.750000 0.715000 6.120000 0.825000 ; - RECT 4.750000 1.495000 6.140000 1.665000 ; - RECT 4.750000 1.665000 5.035000 2.465000 ; - RECT 4.890000 0.825000 6.120000 0.885000 ; - RECT 4.890000 0.885000 5.060000 1.495000 ; - RECT 5.575000 1.835000 5.840000 2.635000 ; - RECT 5.590000 0.085000 5.870000 0.545000 ; - RECT 5.910000 0.885000 6.120000 1.055000 ; - RECT 5.910000 1.055000 6.580000 1.290000 ; - RECT 5.910000 1.290000 6.140000 1.495000 ; - RECT 6.540000 2.175000 6.800000 2.635000 ; - RECT 6.630000 0.085000 6.800000 0.545000 ; - RECT 7.470000 0.085000 7.735000 0.885000 ; - RECT 7.470000 1.485000 7.735000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.785000 0.780000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.755000 0.840000 1.800000 ; - RECT 0.550000 1.800000 1.755000 1.940000 ; - RECT 0.550000 1.940000 0.840000 1.985000 ; - RECT 1.465000 1.755000 1.755000 1.800000 ; - RECT 1.465000 1.940000 1.755000 1.985000 ; - END -END sky130_fd_sc_hd__dlclkp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrbn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrbn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.060000 0.255000 6.380000 2.465000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.475000 0.255000 7.735000 0.595000 ; - RECT 7.475000 1.785000 7.735000 2.465000 ; - RECT 7.560000 0.595000 7.735000 1.785000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.470000 0.995000 5.455000 1.325000 ; - END - END RESET_B - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.085000 1.795000 0.780000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 2.005000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.840000 0.365000 3.500000 0.535000 ; - RECT 2.900000 2.255000 3.650000 2.425000 ; - RECT 2.925000 1.035000 3.095000 1.415000 ; - RECT 2.925000 1.415000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.300000 1.165000 ; - RECT 3.480000 1.165000 4.300000 1.325000 ; - RECT 3.480000 1.325000 3.650000 2.255000 ; - RECT 3.740000 0.085000 4.070000 0.530000 ; - RECT 3.820000 2.135000 4.090000 2.635000 ; - RECT 3.840000 1.535000 5.875000 1.765000 ; - RECT 3.840000 1.765000 4.970000 1.865000 ; - RECT 4.240000 0.255000 4.540000 0.655000 ; - RECT 4.240000 0.655000 5.875000 0.825000 ; - RECT 4.260000 2.135000 4.590000 2.635000 ; - RECT 4.760000 1.865000 4.970000 2.435000 ; - RECT 5.135000 0.085000 5.875000 0.485000 ; - RECT 5.150000 1.935000 5.890000 2.635000 ; - RECT 5.625000 0.825000 5.875000 1.535000 ; - RECT 6.580000 0.255000 6.750000 0.985000 ; - RECT 6.580000 0.985000 6.830000 0.995000 ; - RECT 6.580000 0.995000 7.390000 1.325000 ; - RECT 6.580000 1.325000 6.830000 2.465000 ; - RECT 6.975000 0.085000 7.305000 0.465000 ; - RECT 7.010000 1.835000 7.305000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.160000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.700000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 1.415000 3.160000 1.460000 ; - RECT 2.870000 1.600000 3.160000 1.645000 ; - END -END sky130_fd_sc_hd__dlrbn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrbn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrbn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.536250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.650000 0.415000 5.910000 0.655000 ; - RECT 5.650000 0.655000 5.950000 0.685000 ; - RECT 5.650000 0.685000 5.975000 0.825000 ; - RECT 5.650000 1.495000 5.975000 1.660000 ; - RECT 5.650000 1.660000 5.915000 2.465000 ; - RECT 5.740000 0.825000 5.975000 0.860000 ; - RECT 5.790000 0.860000 5.975000 0.885000 ; - RECT 5.790000 0.885000 6.355000 1.325000 ; - RECT 5.790000 1.325000 5.975000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.500000 0.255000 7.755000 0.825000 ; - RECT 7.500000 1.445000 7.755000 2.465000 ; - RECT 7.545000 0.825000 7.755000 1.055000 ; - RECT 7.545000 1.055000 8.195000 1.325000 ; - RECT 7.545000 1.325000 7.755000 1.445000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.390000 0.995000 5.140000 1.325000 ; - END - END RESET_B - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.085000 1.795000 0.780000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.780000 1.070000 ; - RECT 0.605000 1.070000 0.840000 1.400000 ; - RECT 0.605000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 2.005000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.840000 0.365000 3.500000 0.535000 ; - RECT 2.900000 2.255000 3.650000 2.425000 ; - RECT 2.925000 1.035000 3.095000 1.415000 ; - RECT 2.925000 1.415000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.200000 1.165000 ; - RECT 3.480000 1.165000 4.200000 1.325000 ; - RECT 3.480000 1.325000 3.650000 2.255000 ; - RECT 3.740000 0.085000 4.070000 0.825000 ; - RECT 3.820000 2.135000 4.590000 2.635000 ; - RECT 3.840000 1.495000 5.480000 1.665000 ; - RECT 3.840000 1.665000 4.930000 1.865000 ; - RECT 4.340000 0.415000 4.560000 0.655000 ; - RECT 4.340000 0.655000 5.480000 0.825000 ; - RECT 4.760000 1.865000 4.930000 2.435000 ; - RECT 5.100000 0.085000 5.480000 0.485000 ; - RECT 5.100000 1.855000 5.350000 2.635000 ; - RECT 5.310000 0.825000 5.480000 0.995000 ; - RECT 5.310000 0.995000 5.620000 1.325000 ; - RECT 5.310000 1.325000 5.480000 1.495000 ; - RECT 6.085000 0.085000 6.355000 0.545000 ; - RECT 6.085000 1.830000 6.355000 2.635000 ; - RECT 6.525000 0.255000 6.855000 0.995000 ; - RECT 6.525000 0.995000 7.375000 1.325000 ; - RECT 6.525000 1.325000 6.855000 2.465000 ; - RECT 7.025000 0.085000 7.330000 0.545000 ; - RECT 7.035000 1.835000 7.330000 2.635000 ; - RECT 7.925000 0.085000 8.195000 0.885000 ; - RECT 7.925000 1.495000 8.195000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.160000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.700000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 1.415000 3.160000 1.460000 ; - RECT 2.870000 1.600000 3.160000 1.645000 ; - END -END sky130_fd_sc_hd__dlrbn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.060000 0.255000 6.410000 2.465000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.475000 0.255000 7.735000 0.595000 ; - RECT 7.475000 1.785000 7.735000 2.465000 ; - RECT 7.565000 0.595000 7.735000 1.785000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.450000 0.995000 5.435000 1.325000 ; - END - END RESET_B - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.325000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.085000 1.795000 0.780000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 1.685000 ; - RECT 2.600000 0.765000 3.095000 1.035000 ; - RECT 2.745000 2.255000 3.585000 2.425000 ; - RECT 2.770000 0.365000 3.500000 0.535000 ; - RECT 2.925000 1.035000 3.095000 1.575000 ; - RECT 2.925000 1.575000 3.265000 1.905000 ; - RECT 2.925000 1.905000 3.130000 1.995000 ; - RECT 3.270000 2.125000 3.585000 2.255000 ; - RECT 3.305000 2.075000 3.585000 2.125000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.200000 1.165000 ; - RECT 3.395000 2.015000 3.605000 2.045000 ; - RECT 3.395000 2.045000 3.585000 2.075000 ; - RECT 3.415000 1.990000 3.605000 2.015000 ; - RECT 3.420000 1.975000 3.605000 1.990000 ; - RECT 3.430000 1.960000 3.605000 1.975000 ; - RECT 3.435000 1.165000 4.200000 1.325000 ; - RECT 3.435000 1.325000 3.605000 1.960000 ; - RECT 3.735000 0.085000 4.070000 0.530000 ; - RECT 3.755000 2.135000 4.590000 2.635000 ; - RECT 3.840000 1.535000 5.890000 1.765000 ; - RECT 3.840000 1.765000 4.950000 1.865000 ; - RECT 4.240000 0.255000 4.540000 0.655000 ; - RECT 4.240000 0.655000 5.890000 0.825000 ; - RECT 4.780000 1.865000 4.950000 2.435000 ; - RECT 5.120000 0.085000 5.890000 0.485000 ; - RECT 5.120000 1.935000 5.890000 2.635000 ; - RECT 5.655000 0.825000 5.890000 1.535000 ; - RECT 6.580000 0.255000 6.805000 0.995000 ; - RECT 6.580000 0.995000 7.395000 1.325000 ; - RECT 6.580000 1.325000 6.830000 2.465000 ; - RECT 6.975000 0.085000 7.305000 0.465000 ; - RECT 7.010000 1.835000 7.305000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.445000 2.640000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.925000 1.785000 3.095000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.700000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.155000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.415000 2.700000 1.460000 ; - RECT 2.410000 1.600000 2.700000 1.645000 ; - RECT 2.865000 1.755000 3.155000 1.800000 ; - RECT 2.865000 1.940000 3.155000 1.985000 ; - END -END sky130_fd_sc_hd__dlrbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.478500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.680000 0.330000 5.850000 0.665000 ; - RECT 5.680000 0.665000 6.150000 0.835000 ; - RECT 5.680000 1.495000 6.065000 1.660000 ; - RECT 5.680000 1.660000 5.930000 2.465000 ; - RECT 5.790000 0.835000 6.150000 0.885000 ; - RECT 5.790000 0.885000 6.360000 1.325000 ; - RECT 5.790000 1.325000 6.065000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.515000 0.255000 7.765000 0.825000 ; - RECT 7.515000 1.605000 7.765000 2.465000 ; - RECT 7.595000 0.825000 7.765000 1.055000 ; - RECT 7.595000 1.055000 8.195000 1.325000 ; - RECT 7.595000 1.325000 7.765000 1.605000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.400000 0.995000 5.150000 1.325000 ; - END - END RESET_B - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.085000 1.795000 0.780000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 1.685000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.745000 2.255000 3.585000 2.425000 ; - RECT 2.770000 0.365000 3.500000 0.535000 ; - RECT 2.925000 1.035000 3.095000 1.575000 ; - RECT 2.925000 1.575000 3.265000 1.905000 ; - RECT 2.925000 1.905000 3.125000 1.995000 ; - RECT 3.270000 2.125000 3.585000 2.255000 ; - RECT 3.305000 2.075000 3.585000 2.125000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.200000 1.165000 ; - RECT 3.395000 2.015000 3.605000 2.045000 ; - RECT 3.395000 2.045000 3.585000 2.075000 ; - RECT 3.415000 1.990000 3.605000 2.015000 ; - RECT 3.420000 1.975000 3.605000 1.990000 ; - RECT 3.430000 1.960000 3.605000 1.975000 ; - RECT 3.435000 1.165000 4.200000 1.325000 ; - RECT 3.435000 1.325000 3.605000 1.960000 ; - RECT 3.740000 0.085000 4.070000 0.530000 ; - RECT 3.755000 2.135000 4.600000 2.635000 ; - RECT 3.840000 1.535000 5.510000 1.705000 ; - RECT 3.840000 1.705000 4.940000 1.865000 ; - RECT 4.270000 0.415000 4.570000 0.655000 ; - RECT 4.270000 0.655000 5.510000 0.825000 ; - RECT 4.770000 1.865000 4.940000 2.435000 ; - RECT 5.110000 0.085000 5.490000 0.485000 ; - RECT 5.110000 1.875000 5.490000 2.635000 ; - RECT 5.320000 0.825000 5.510000 0.995000 ; - RECT 5.320000 0.995000 5.620000 1.325000 ; - RECT 5.320000 1.325000 5.510000 1.535000 ; - RECT 6.020000 0.085000 6.360000 0.465000 ; - RECT 6.100000 1.830000 6.360000 2.635000 ; - RECT 6.535000 0.255000 6.865000 0.995000 ; - RECT 6.535000 0.995000 7.425000 1.325000 ; - RECT 6.535000 1.325000 6.870000 2.465000 ; - RECT 7.035000 0.085000 7.340000 0.545000 ; - RECT 7.045000 1.835000 7.340000 2.635000 ; - RECT 7.935000 0.085000 8.195000 0.885000 ; - RECT 7.935000 1.495000 8.195000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.445000 2.640000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.785000 3.100000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.700000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.160000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.415000 2.700000 1.460000 ; - RECT 2.410000 1.600000 2.700000 1.645000 ; - RECT 2.870000 1.755000 3.160000 1.800000 ; - RECT 2.870000 1.940000 3.160000 1.985000 ; - END -END sky130_fd_sc_hd__dlrbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.095000 0.415000 6.355000 2.455000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.500000 0.995000 5.435000 1.325000 ; - END - END RESET_B - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 2.005000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.840000 0.365000 3.500000 0.535000 ; - RECT 2.900000 2.255000 3.650000 2.425000 ; - RECT 2.925000 1.035000 3.095000 1.415000 ; - RECT 2.925000 1.415000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 1.025000 ; - RECT 3.330000 1.025000 4.330000 1.245000 ; - RECT 3.480000 1.245000 4.330000 1.325000 ; - RECT 3.480000 1.325000 3.650000 2.255000 ; - RECT 3.740000 0.085000 4.070000 0.530000 ; - RECT 3.820000 1.535000 5.925000 1.865000 ; - RECT 3.820000 2.135000 4.110000 2.635000 ; - RECT 4.240000 0.255000 4.590000 0.655000 ; - RECT 4.240000 0.655000 5.925000 0.825000 ; - RECT 4.300000 2.135000 4.580000 2.635000 ; - RECT 4.750000 1.865000 4.940000 2.465000 ; - RECT 5.095000 0.085000 5.925000 0.485000 ; - RECT 5.110000 2.135000 5.925000 2.635000 ; - RECT 5.605000 0.825000 5.925000 1.535000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.160000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.700000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 1.415000 3.160000 1.460000 ; - RECT 2.870000 1.600000 3.160000 1.645000 ; - END -END sky130_fd_sc_hd__dlrtn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.480500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.595000 0.255000 5.925000 0.485000 ; - RECT 5.655000 1.875000 5.925000 2.465000 ; - RECT 5.755000 0.485000 5.925000 0.765000 ; - RECT 5.755000 0.765000 6.355000 0.865000 ; - RECT 5.755000 1.425000 6.355000 1.500000 ; - RECT 5.755000 1.500000 5.925000 1.875000 ; - RECT 5.760000 1.415000 6.355000 1.425000 ; - RECT 5.765000 1.410000 6.355000 1.415000 ; - RECT 5.770000 0.865000 6.355000 0.890000 ; - RECT 5.775000 1.385000 6.355000 1.410000 ; - RECT 5.785000 0.890000 6.355000 1.385000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.480000 0.995000 5.170000 1.325000 ; - END - END RESET_B - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.960000 0.785000 2.340000 1.095000 ; - RECT 1.960000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 2.005000 ; - RECT 2.675000 0.705000 3.095000 1.145000 ; - RECT 2.775000 2.255000 3.605000 2.425000 ; - RECT 2.810000 0.365000 3.500000 0.535000 ; - RECT 2.925000 1.145000 3.095000 1.415000 ; - RECT 2.925000 1.415000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 1.025000 ; - RECT 3.330000 1.025000 4.310000 1.245000 ; - RECT 3.435000 1.245000 4.310000 1.325000 ; - RECT 3.435000 1.325000 3.605000 2.255000 ; - RECT 3.735000 0.085000 4.070000 0.530000 ; - RECT 3.800000 2.135000 4.110000 2.635000 ; - RECT 3.820000 1.535000 5.585000 1.705000 ; - RECT 3.820000 1.705000 4.920000 1.865000 ; - RECT 4.240000 0.255000 4.590000 0.655000 ; - RECT 4.240000 0.655000 5.585000 0.825000 ; - RECT 4.280000 2.135000 4.560000 2.635000 ; - RECT 4.730000 1.865000 4.920000 2.465000 ; - RECT 5.090000 1.875000 5.460000 2.635000 ; - RECT 5.095000 0.085000 5.425000 0.485000 ; - RECT 5.350000 0.995000 5.615000 1.325000 ; - RECT 5.415000 0.825000 5.585000 0.995000 ; - RECT 5.415000 1.325000 5.585000 1.535000 ; - RECT 6.095000 0.085000 6.355000 0.595000 ; - RECT 6.095000 1.670000 6.355000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.160000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.700000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 1.415000 3.160000 1.460000 ; - RECT 2.870000 1.600000 3.160000 1.645000 ; - END -END sky130_fd_sc_hd__dlrtn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtn_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtn_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 0.955000 1.795000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 1.014750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.610000 0.255000 5.965000 0.485000 ; - RECT 5.680000 1.875000 5.965000 2.465000 ; - RECT 5.795000 0.485000 5.965000 0.765000 ; - RECT 5.795000 0.765000 7.275000 1.325000 ; - RECT 5.795000 1.325000 5.965000 1.875000 ; - RECT 6.575000 0.255000 6.775000 0.765000 ; - RECT 6.575000 1.325000 6.775000 2.465000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.505000 0.995000 5.145000 1.325000 ; - END - END RESET_B - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 1.960000 1.835000 2.275000 2.635000 ; - RECT 3.825000 2.135000 4.115000 2.635000 ; - RECT 4.305000 2.135000 4.585000 2.635000 ; - RECT 5.115000 1.875000 5.485000 2.635000 ; - RECT 6.135000 1.495000 6.405000 2.635000 ; - RECT 6.945000 1.495000 7.275000 2.635000 ; - LAYER mcon ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.460000 1.495000 2.145000 1.665000 ; - RECT 1.460000 1.665000 1.790000 2.415000 ; - RECT 1.540000 0.345000 1.710000 0.615000 ; - RECT 1.540000 0.615000 2.145000 0.765000 ; - RECT 1.540000 0.765000 2.345000 0.785000 ; - RECT 1.880000 0.085000 2.210000 0.445000 ; - RECT 1.975000 0.785000 2.345000 1.095000 ; - RECT 1.975000 1.095000 2.145000 1.495000 ; - RECT 2.475000 1.355000 2.760000 2.005000 ; - RECT 2.720000 0.705000 3.100000 1.035000 ; - RECT 2.845000 0.365000 3.505000 0.535000 ; - RECT 2.905000 2.255000 3.655000 2.425000 ; - RECT 2.930000 1.035000 3.100000 1.415000 ; - RECT 2.930000 1.415000 3.270000 1.995000 ; - RECT 3.335000 0.535000 3.505000 1.025000 ; - RECT 3.335000 1.025000 4.315000 1.245000 ; - RECT 3.485000 1.245000 4.315000 1.325000 ; - RECT 3.485000 1.325000 3.655000 2.255000 ; - RECT 3.745000 0.085000 4.075000 0.530000 ; - RECT 3.825000 1.535000 5.625000 1.705000 ; - RECT 3.825000 1.705000 4.945000 1.865000 ; - RECT 4.245000 0.255000 4.595000 0.655000 ; - RECT 4.245000 0.655000 5.625000 0.825000 ; - RECT 4.755000 1.865000 4.945000 2.465000 ; - RECT 5.100000 0.085000 5.440000 0.485000 ; - RECT 5.455000 0.825000 5.625000 1.535000 ; - RECT 6.135000 0.085000 6.405000 0.595000 ; - RECT 6.945000 0.085000 7.275000 0.595000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.475000 1.785000 2.645000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.935000 1.445000 3.105000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.165000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.705000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.415000 1.755000 2.705000 1.800000 ; - RECT 2.415000 1.940000 2.705000 1.985000 ; - RECT 2.875000 1.415000 3.165000 1.460000 ; - RECT 2.875000 1.600000 3.165000 1.645000 ; - END -END sky130_fd_sc_hd__dlrtn_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.435000 0.955000 1.765000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.610000 0.345000 5.895000 0.745000 ; - RECT 5.635000 1.670000 5.895000 2.455000 ; - RECT 5.725000 0.745000 5.895000 1.670000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.745000 0.345000 4.975000 0.995000 ; - RECT 4.745000 0.995000 5.075000 1.325000 ; - END - END RESET_B - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.325000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 1.795000 0.775000 1.965000 ; - RECT 0.085000 1.965000 0.345000 2.465000 ; - RECT 0.170000 0.345000 0.345000 0.635000 ; - RECT 0.170000 0.635000 0.775000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.775000 1.070000 ; - RECT 0.605000 1.070000 0.835000 1.400000 ; - RECT 0.605000 1.400000 0.775000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.235000 2.465000 ; - RECT 1.430000 1.495000 2.115000 1.665000 ; - RECT 1.430000 1.665000 1.785000 2.415000 ; - RECT 1.510000 0.345000 1.705000 0.615000 ; - RECT 1.510000 0.615000 2.115000 0.765000 ; - RECT 1.510000 0.765000 2.335000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.945000 0.785000 2.335000 1.095000 ; - RECT 1.945000 1.095000 2.115000 1.495000 ; - RECT 1.955000 1.835000 2.245000 2.635000 ; - RECT 2.445000 1.355000 2.835000 1.625000 ; - RECT 2.445000 1.625000 2.760000 1.685000 ; - RECT 2.690000 0.765000 3.245000 1.095000 ; - RECT 2.810000 2.255000 3.625000 2.425000 ; - RECT 2.815000 0.365000 3.585000 0.535000 ; - RECT 2.900000 1.785000 3.265000 1.995000 ; - RECT 3.005000 1.095000 3.245000 1.635000 ; - RECT 3.005000 1.635000 3.265000 1.785000 ; - RECT 3.415000 0.535000 3.585000 0.995000 ; - RECT 3.415000 0.995000 4.175000 1.165000 ; - RECT 3.455000 1.165000 4.175000 1.325000 ; - RECT 3.455000 1.325000 3.625000 2.255000 ; - RECT 3.755000 0.085000 4.025000 0.610000 ; - RECT 3.815000 1.535000 5.465000 1.735000 ; - RECT 3.815000 1.735000 4.965000 1.865000 ; - RECT 3.930000 2.135000 4.445000 2.635000 ; - RECT 4.195000 0.295000 4.575000 0.805000 ; - RECT 4.345000 0.805000 4.575000 1.505000 ; - RECT 4.345000 1.505000 5.465000 1.535000 ; - RECT 4.625000 1.865000 4.965000 2.435000 ; - RECT 5.135000 1.915000 5.465000 2.635000 ; - RECT 5.155000 0.085000 5.440000 0.715000 ; - RECT 5.245000 0.995000 5.555000 1.325000 ; - RECT 5.245000 1.325000 5.465000 1.505000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 1.445000 0.775000 1.615000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 1.785000 1.235000 1.955000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.445000 2.615000 1.615000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.925000 1.785000 3.095000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 0.545000 1.415000 0.835000 1.460000 ; - RECT 0.545000 1.460000 2.675000 1.600000 ; - RECT 0.545000 1.600000 0.835000 1.645000 ; - RECT 1.005000 1.755000 1.295000 1.800000 ; - RECT 1.005000 1.800000 3.155000 1.940000 ; - RECT 1.005000 1.940000 1.295000 1.985000 ; - RECT 2.385000 1.415000 2.675000 1.460000 ; - RECT 2.385000 1.600000 2.675000 1.645000 ; - RECT 2.865000 1.755000 3.155000 1.800000 ; - RECT 2.865000 1.940000 3.155000 1.985000 ; - END -END sky130_fd_sc_hd__dlrtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.440000 0.955000 1.770000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.480500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.595000 0.255000 5.925000 0.485000 ; - RECT 5.655000 1.875000 5.925000 2.465000 ; - RECT 5.755000 0.485000 5.925000 0.765000 ; - RECT 5.755000 0.765000 6.355000 0.865000 ; - RECT 5.755000 1.425000 6.355000 1.500000 ; - RECT 5.755000 1.500000 5.925000 1.875000 ; - RECT 5.760000 1.415000 6.355000 1.425000 ; - RECT 5.765000 1.410000 6.355000 1.415000 ; - RECT 5.770000 0.865000 6.355000 0.890000 ; - RECT 5.775000 1.385000 6.355000 1.410000 ; - RECT 5.785000 0.890000 6.355000 1.385000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.480000 0.995000 4.815000 1.035000 ; - RECT 4.480000 1.035000 5.240000 1.325000 ; - END - END RESET_B - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.635000 ; - RECT 0.085000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.435000 1.495000 2.120000 1.665000 ; - RECT 1.435000 1.665000 1.785000 2.415000 ; - RECT 1.515000 0.345000 1.705000 0.615000 ; - RECT 1.515000 0.615000 2.120000 0.765000 ; - RECT 1.515000 0.765000 2.335000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.950000 0.785000 2.335000 1.095000 ; - RECT 1.950000 1.095000 2.120000 1.495000 ; - RECT 1.955000 1.835000 2.250000 2.635000 ; - RECT 2.450000 1.355000 2.755000 1.685000 ; - RECT 2.585000 0.735000 3.100000 1.040000 ; - RECT 2.770000 0.365000 3.445000 0.535000 ; - RECT 2.770000 2.255000 3.580000 2.425000 ; - RECT 2.905000 1.780000 3.265000 1.910000 ; - RECT 2.905000 1.910000 3.175000 1.995000 ; - RECT 2.930000 1.040000 3.100000 1.570000 ; - RECT 2.930000 1.570000 3.265000 1.780000 ; - RECT 3.270000 0.535000 3.445000 0.995000 ; - RECT 3.270000 0.995000 4.220000 1.325000 ; - RECT 3.410000 2.000000 3.605000 2.085000 ; - RECT 3.410000 2.085000 3.580000 2.255000 ; - RECT 3.415000 1.995000 3.605000 2.000000 ; - RECT 3.420000 1.985000 3.605000 1.995000 ; - RECT 3.435000 1.325000 3.605000 1.985000 ; - RECT 3.720000 0.085000 4.060000 0.530000 ; - RECT 3.750000 2.175000 4.090000 2.635000 ; - RECT 3.775000 1.535000 5.585000 1.705000 ; - RECT 3.775000 1.705000 4.970000 1.865000 ; - RECT 4.240000 0.255000 4.580000 0.655000 ; - RECT 4.240000 0.655000 5.095000 0.695000 ; - RECT 4.240000 0.695000 5.585000 0.825000 ; - RECT 4.280000 2.135000 4.560000 2.635000 ; - RECT 4.800000 1.865000 4.970000 2.465000 ; - RECT 4.955000 0.825000 5.585000 0.865000 ; - RECT 5.140000 1.875000 5.485000 2.635000 ; - RECT 5.255000 0.085000 5.425000 0.525000 ; - RECT 5.415000 0.865000 5.585000 0.995000 ; - RECT 5.415000 0.995000 5.615000 1.325000 ; - RECT 5.415000 1.325000 5.585000 1.535000 ; - RECT 6.095000 0.085000 6.355000 0.595000 ; - RECT 6.095000 1.670000 6.355000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.450000 1.445000 2.620000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.925000 1.785000 3.095000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.680000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.155000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.390000 1.415000 2.680000 1.460000 ; - RECT 2.390000 1.600000 2.680000 1.645000 ; - RECT 2.865000 1.755000 3.155000 1.800000 ; - RECT 2.865000 1.940000 3.155000 1.985000 ; - END -END sky130_fd_sc_hd__dlrtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlrtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlrtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 0.955000 1.795000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 1.014750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.610000 0.255000 5.965000 0.485000 ; - RECT 5.680000 1.875000 5.965000 2.465000 ; - RECT 5.795000 0.485000 5.965000 0.765000 ; - RECT 5.795000 0.765000 7.275000 1.325000 ; - RECT 5.795000 1.325000 5.965000 1.875000 ; - RECT 6.575000 0.255000 6.775000 0.765000 ; - RECT 6.575000 1.325000 6.775000 2.465000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.505000 0.995000 5.145000 1.325000 ; - END - END RESET_B - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 1.960000 1.835000 2.275000 2.635000 ; - RECT 3.825000 2.135000 4.115000 2.635000 ; - RECT 4.305000 2.135000 4.585000 2.635000 ; - RECT 5.115000 1.875000 5.485000 2.635000 ; - RECT 6.135000 1.495000 6.405000 2.635000 ; - RECT 6.945000 1.495000 7.275000 2.635000 ; - LAYER mcon ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.460000 1.495000 2.145000 1.665000 ; - RECT 1.460000 1.665000 1.790000 2.415000 ; - RECT 1.540000 0.345000 1.710000 0.615000 ; - RECT 1.540000 0.615000 2.145000 0.765000 ; - RECT 1.540000 0.765000 2.345000 0.785000 ; - RECT 1.880000 0.085000 2.210000 0.445000 ; - RECT 1.975000 0.785000 2.345000 1.095000 ; - RECT 1.975000 1.095000 2.145000 1.495000 ; - RECT 2.475000 1.355000 2.760000 1.685000 ; - RECT 2.720000 0.705000 3.100000 1.035000 ; - RECT 2.845000 0.365000 3.505000 0.535000 ; - RECT 2.905000 2.255000 3.655000 2.425000 ; - RECT 2.930000 1.035000 3.100000 1.575000 ; - RECT 2.930000 1.575000 3.270000 1.995000 ; - RECT 3.335000 0.535000 3.505000 0.995000 ; - RECT 3.335000 0.995000 4.235000 1.165000 ; - RECT 3.485000 1.165000 4.235000 1.325000 ; - RECT 3.485000 1.325000 3.655000 2.255000 ; - RECT 3.745000 0.085000 4.075000 0.530000 ; - RECT 3.825000 1.535000 5.625000 1.705000 ; - RECT 3.825000 1.705000 4.945000 1.865000 ; - RECT 4.265000 0.255000 4.595000 0.655000 ; - RECT 4.265000 0.655000 5.625000 0.825000 ; - RECT 4.755000 1.865000 4.945000 2.465000 ; - RECT 5.100000 0.085000 5.440000 0.485000 ; - RECT 5.455000 0.825000 5.625000 1.535000 ; - RECT 6.135000 0.085000 6.405000 0.595000 ; - RECT 6.945000 0.085000 7.275000 0.595000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.475000 1.445000 2.645000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.935000 1.785000 3.105000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.705000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.165000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.415000 1.415000 2.705000 1.460000 ; - RECT 2.415000 1.600000 2.705000 1.645000 ; - RECT 2.875000 1.755000 3.165000 1.800000 ; - RECT 2.875000 1.940000 3.165000 1.985000 ; - END -END sky130_fd_sc_hd__dlrtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxbn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxbn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.445000 0.955000 1.785000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.140000 0.415000 5.480000 0.745000 ; - RECT 5.140000 1.670000 5.480000 2.465000 ; - RECT 5.310000 0.745000 5.480000 1.670000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.555000 0.255000 6.815000 0.825000 ; - RECT 6.555000 1.505000 6.815000 2.465000 ; - RECT 6.625000 0.825000 6.815000 1.505000 ; - END - END Q_N - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.480000 1.495000 2.165000 1.665000 ; - RECT 1.480000 1.665000 1.810000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.165000 0.785000 ; - RECT 1.875000 0.085000 2.230000 0.445000 ; - RECT 1.980000 1.835000 2.295000 2.635000 ; - RECT 1.995000 0.785000 2.165000 0.905000 ; - RECT 1.995000 0.905000 2.365000 1.235000 ; - RECT 1.995000 1.235000 2.165000 1.495000 ; - RECT 2.495000 1.355000 2.780000 2.005000 ; - RECT 2.565000 0.705000 3.120000 1.035000 ; - RECT 2.790000 0.365000 3.525000 0.535000 ; - RECT 2.920000 2.105000 3.620000 2.115000 ; - RECT 2.920000 2.115000 3.615000 2.130000 ; - RECT 2.920000 2.130000 3.610000 2.275000 ; - RECT 2.950000 1.035000 3.120000 1.415000 ; - RECT 2.950000 1.415000 3.290000 1.910000 ; - RECT 3.355000 0.535000 3.525000 0.995000 ; - RECT 3.355000 0.995000 4.225000 1.165000 ; - RECT 3.360000 2.075000 3.630000 2.090000 ; - RECT 3.360000 2.090000 3.625000 2.105000 ; - RECT 3.375000 2.060000 3.630000 2.075000 ; - RECT 3.420000 2.030000 3.630000 2.060000 ; - RECT 3.430000 2.015000 3.630000 2.030000 ; - RECT 3.460000 1.165000 4.225000 1.325000 ; - RECT 3.460000 1.325000 3.630000 2.015000 ; - RECT 3.765000 0.085000 4.095000 0.610000 ; - RECT 3.780000 2.175000 3.950000 2.635000 ; - RECT 3.800000 1.535000 4.580000 1.620000 ; - RECT 3.800000 1.620000 4.550000 1.865000 ; - RECT 4.300000 0.415000 4.470000 0.660000 ; - RECT 4.300000 0.660000 4.580000 0.840000 ; - RECT 4.300000 1.865000 4.550000 2.435000 ; - RECT 4.395000 0.840000 4.580000 0.995000 ; - RECT 4.395000 0.995000 5.140000 1.325000 ; - RECT 4.395000 1.325000 4.580000 1.535000 ; - RECT 4.640000 0.085000 4.970000 0.495000 ; - RECT 4.720000 1.830000 4.970000 2.635000 ; - RECT 5.660000 0.255000 5.910000 0.995000 ; - RECT 5.660000 0.995000 6.455000 1.325000 ; - RECT 5.660000 1.325000 5.910000 2.465000 ; - RECT 6.090000 0.085000 6.385000 0.545000 ; - RECT 6.090000 1.835000 6.385000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.495000 1.785000 2.665000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.955000 1.445000 3.125000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.185000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.725000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.435000 1.755000 2.725000 1.800000 ; - RECT 2.435000 1.940000 2.725000 1.985000 ; - RECT 2.895000 1.415000 3.185000 1.460000 ; - RECT 2.895000 1.600000 3.185000 1.645000 ; - END -END sky130_fd_sc_hd__dlxbn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxbn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxbn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 0.955000 1.810000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.215000 0.415000 5.465000 0.660000 ; - RECT 5.215000 0.660000 5.500000 0.825000 ; - RECT 5.215000 1.495000 5.500000 1.710000 ; - RECT 5.215000 1.710000 5.465000 2.455000 ; - RECT 5.330000 0.825000 5.500000 0.995000 ; - RECT 5.330000 0.995000 5.905000 1.325000 ; - RECT 5.330000 1.325000 5.500000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.050000 0.255000 7.305000 0.825000 ; - RECT 7.050000 1.445000 7.305000 2.465000 ; - RECT 7.095000 0.825000 7.305000 1.055000 ; - RECT 7.095000 1.055000 7.735000 1.325000 ; - RECT 7.095000 1.325000 7.305000 1.445000 ; - END - END Q_N - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.475000 1.495000 2.160000 1.665000 ; - RECT 1.475000 1.665000 1.805000 2.415000 ; - RECT 1.555000 0.345000 1.725000 0.615000 ; - RECT 1.555000 0.615000 2.160000 0.765000 ; - RECT 1.555000 0.765000 2.360000 0.785000 ; - RECT 1.895000 0.085000 2.225000 0.445000 ; - RECT 1.975000 1.835000 2.290000 2.635000 ; - RECT 1.990000 0.785000 2.360000 1.095000 ; - RECT 1.990000 1.095000 2.160000 1.495000 ; - RECT 2.490000 1.355000 2.775000 2.005000 ; - RECT 2.735000 0.705000 3.115000 1.035000 ; - RECT 2.860000 0.365000 3.520000 0.535000 ; - RECT 2.920000 2.255000 3.670000 2.425000 ; - RECT 2.945000 1.035000 3.115000 1.415000 ; - RECT 2.945000 1.415000 3.285000 1.995000 ; - RECT 3.350000 0.535000 3.520000 0.995000 ; - RECT 3.350000 0.995000 4.220000 1.165000 ; - RECT 3.500000 1.165000 4.220000 1.325000 ; - RECT 3.500000 1.325000 3.670000 2.255000 ; - RECT 3.760000 0.085000 4.090000 0.825000 ; - RECT 3.840000 2.135000 4.140000 2.635000 ; - RECT 3.860000 1.535000 4.580000 1.865000 ; - RECT 4.360000 0.415000 4.580000 0.825000 ; - RECT 4.360000 1.865000 4.580000 2.435000 ; - RECT 4.410000 0.825000 4.580000 0.995000 ; - RECT 4.410000 0.995000 5.160000 1.325000 ; - RECT 4.410000 1.325000 4.580000 1.535000 ; - RECT 4.760000 0.085000 5.045000 0.825000 ; - RECT 4.760000 1.495000 5.045000 2.635000 ; - RECT 5.635000 0.085000 5.905000 0.545000 ; - RECT 5.635000 1.835000 5.905000 2.635000 ; - RECT 6.075000 0.255000 6.405000 0.995000 ; - RECT 6.075000 0.995000 6.925000 1.325000 ; - RECT 6.075000 1.325000 6.405000 2.465000 ; - RECT 6.585000 0.085000 6.880000 0.545000 ; - RECT 6.585000 1.835000 6.880000 2.635000 ; - RECT 7.475000 0.085000 7.735000 0.885000 ; - RECT 7.475000 1.495000 7.735000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.490000 1.785000 2.660000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.950000 1.445000 3.120000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.180000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.720000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.430000 1.755000 2.720000 1.800000 ; - RECT 2.430000 1.940000 2.720000 1.985000 ; - RECT 2.890000 1.415000 3.180000 1.460000 ; - RECT 2.890000 1.600000 3.180000 1.645000 ; - END -END sky130_fd_sc_hd__dlxbn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.355000 0.955000 1.685000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.140000 0.255000 5.490000 0.820000 ; - RECT 5.140000 1.670000 5.490000 2.455000 ; - RECT 5.320000 0.820000 5.490000 1.670000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.555000 0.255000 6.815000 0.825000 ; - RECT 6.555000 1.445000 6.815000 2.465000 ; - RECT 6.600000 0.825000 6.815000 1.445000 ; - END - END Q_N - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.430000 1.495000 2.115000 1.665000 ; - RECT 1.430000 1.665000 1.795000 2.415000 ; - RECT 1.510000 0.345000 1.705000 0.615000 ; - RECT 1.510000 0.615000 2.135000 0.785000 ; - RECT 1.855000 0.785000 2.135000 0.875000 ; - RECT 1.855000 0.875000 2.335000 1.235000 ; - RECT 1.855000 1.235000 2.115000 1.495000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.965000 1.835000 2.245000 2.635000 ; - RECT 2.465000 1.355000 2.795000 1.685000 ; - RECT 2.580000 0.705000 3.135000 1.065000 ; - RECT 2.750000 2.255000 3.610000 2.425000 ; - RECT 2.800000 0.365000 3.475000 0.535000 ; - RECT 2.965000 1.065000 3.135000 1.575000 ; - RECT 2.965000 1.575000 3.290000 1.910000 ; - RECT 2.965000 1.910000 3.195000 1.995000 ; - RECT 3.305000 0.535000 3.475000 0.995000 ; - RECT 3.305000 0.995000 4.175000 1.165000 ; - RECT 3.425000 2.035000 3.650000 2.065000 ; - RECT 3.425000 2.065000 3.630000 2.090000 ; - RECT 3.425000 2.090000 3.610000 2.255000 ; - RECT 3.430000 2.020000 3.650000 2.035000 ; - RECT 3.435000 2.010000 3.650000 2.020000 ; - RECT 3.440000 1.995000 3.650000 2.010000 ; - RECT 3.460000 1.165000 4.175000 1.325000 ; - RECT 3.460000 1.325000 3.650000 1.995000 ; - RECT 3.700000 0.085000 4.045000 0.530000 ; - RECT 3.780000 2.175000 3.980000 2.635000 ; - RECT 3.820000 1.535000 4.515000 1.865000 ; - RECT 4.285000 0.415000 4.550000 0.745000 ; - RECT 4.285000 1.865000 4.515000 2.435000 ; - RECT 4.345000 0.745000 4.550000 0.995000 ; - RECT 4.345000 0.995000 5.150000 1.325000 ; - RECT 4.345000 1.325000 4.515000 1.535000 ; - RECT 4.685000 1.570000 4.970000 2.635000 ; - RECT 4.720000 0.085000 4.970000 0.715000 ; - RECT 5.660000 0.255000 5.910000 0.995000 ; - RECT 5.660000 0.995000 6.430000 1.325000 ; - RECT 5.660000 1.325000 5.910000 2.465000 ; - RECT 6.090000 0.085000 6.385000 0.545000 ; - RECT 6.090000 1.835000 6.385000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.555000 1.445000 2.725000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.965000 1.785000 3.135000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.785000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.195000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.495000 1.415000 2.785000 1.460000 ; - RECT 2.495000 1.600000 2.785000 1.645000 ; - RECT 2.905000 1.755000 3.195000 1.800000 ; - RECT 2.905000 1.940000 3.195000 1.985000 ; - END -END sky130_fd_sc_hd__dlxbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxtn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxtn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.435000 0.955000 1.765000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.175000 0.415000 5.435000 0.745000 ; - RECT 5.175000 1.670000 5.435000 2.455000 ; - RECT 5.265000 0.745000 5.435000 1.670000 ; - END - END Q - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.430000 1.495000 2.115000 1.665000 ; - RECT 1.430000 1.665000 1.785000 2.415000 ; - RECT 1.510000 0.345000 1.705000 0.615000 ; - RECT 1.510000 0.615000 2.115000 0.765000 ; - RECT 1.510000 0.765000 2.320000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.945000 0.785000 2.320000 1.235000 ; - RECT 1.945000 1.235000 2.115000 1.495000 ; - RECT 1.955000 1.835000 2.245000 2.635000 ; - RECT 2.445000 1.355000 2.780000 2.005000 ; - RECT 2.560000 0.735000 3.265000 1.040000 ; - RECT 2.745000 2.255000 3.605000 2.425000 ; - RECT 2.765000 0.365000 3.605000 0.535000 ; - RECT 2.950000 1.040000 3.265000 1.560000 ; - RECT 2.950000 1.560000 3.285000 1.910000 ; - RECT 3.295000 2.090000 3.620000 2.105000 ; - RECT 3.295000 2.105000 3.605000 2.255000 ; - RECT 3.390000 2.045000 3.645000 2.065000 ; - RECT 3.390000 2.065000 3.630000 2.085000 ; - RECT 3.390000 2.085000 3.620000 2.090000 ; - RECT 3.405000 2.035000 3.645000 2.045000 ; - RECT 3.430000 2.010000 3.645000 2.035000 ; - RECT 3.435000 0.535000 3.605000 0.995000 ; - RECT 3.435000 0.995000 4.200000 1.325000 ; - RECT 3.435000 1.325000 3.645000 1.450000 ; - RECT 3.455000 1.450000 3.645000 2.010000 ; - RECT 3.775000 0.085000 4.045000 0.545000 ; - RECT 3.775000 2.175000 4.095000 2.635000 ; - RECT 3.815000 1.535000 4.540000 1.865000 ; - RECT 4.295000 0.260000 4.540000 0.720000 ; - RECT 4.295000 1.865000 4.540000 2.435000 ; - RECT 4.370000 0.720000 4.540000 0.995000 ; - RECT 4.370000 0.995000 5.095000 1.325000 ; - RECT 4.370000 1.325000 4.540000 1.535000 ; - RECT 4.720000 1.570000 5.005000 2.635000 ; - RECT 4.755000 0.085000 4.980000 0.715000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.785000 2.615000 1.955000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.950000 1.445000 3.120000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.180000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.675000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.385000 1.755000 2.675000 1.800000 ; - RECT 2.385000 1.940000 2.675000 1.985000 ; - RECT 2.890000 1.415000 3.180000 1.460000 ; - RECT 2.890000 1.600000 3.180000 1.645000 ; - END -END sky130_fd_sc_hd__dlxtn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxtn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxtn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 0.955000 1.810000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.215000 0.415000 5.465000 0.685000 ; - RECT 5.215000 0.685000 5.500000 0.825000 ; - RECT 5.215000 1.495000 5.500000 1.640000 ; - RECT 5.215000 1.640000 5.465000 2.455000 ; - RECT 5.330000 0.825000 5.500000 0.995000 ; - RECT 5.330000 0.995000 5.895000 1.325000 ; - RECT 5.330000 1.325000 5.500000 1.495000 ; - END - END Q - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.475000 1.495000 2.160000 1.665000 ; - RECT 1.475000 1.665000 1.805000 2.415000 ; - RECT 1.555000 0.345000 1.725000 0.615000 ; - RECT 1.555000 0.615000 2.160000 0.765000 ; - RECT 1.555000 0.765000 2.360000 0.785000 ; - RECT 1.895000 0.085000 2.225000 0.445000 ; - RECT 1.975000 1.835000 2.290000 2.635000 ; - RECT 1.990000 0.785000 2.360000 1.095000 ; - RECT 1.990000 1.095000 2.160000 1.495000 ; - RECT 2.490000 1.355000 2.775000 2.005000 ; - RECT 2.735000 0.705000 3.115000 1.035000 ; - RECT 2.860000 0.365000 3.520000 0.535000 ; - RECT 2.920000 2.255000 3.670000 2.425000 ; - RECT 2.945000 1.035000 3.115000 1.415000 ; - RECT 2.945000 1.415000 3.285000 1.995000 ; - RECT 3.350000 0.535000 3.520000 0.995000 ; - RECT 3.350000 0.995000 4.220000 1.165000 ; - RECT 3.500000 1.165000 4.220000 1.325000 ; - RECT 3.500000 1.325000 3.670000 2.255000 ; - RECT 3.760000 0.085000 4.090000 0.825000 ; - RECT 3.840000 2.135000 4.140000 2.635000 ; - RECT 3.860000 1.535000 4.580000 1.865000 ; - RECT 4.360000 0.415000 4.580000 0.825000 ; - RECT 4.360000 1.865000 4.580000 2.435000 ; - RECT 4.410000 0.825000 4.580000 0.995000 ; - RECT 4.410000 0.995000 5.160000 1.325000 ; - RECT 4.410000 1.325000 4.580000 1.535000 ; - RECT 4.760000 0.085000 5.045000 0.825000 ; - RECT 4.760000 1.495000 5.045000 2.635000 ; - RECT 5.635000 0.085000 5.895000 0.550000 ; - RECT 5.635000 1.755000 5.895000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.490000 1.785000 2.660000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.950000 1.445000 3.120000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.180000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.720000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.430000 1.755000 2.720000 1.800000 ; - RECT 2.430000 1.940000 2.720000 1.985000 ; - RECT 2.890000 1.415000 3.180000 1.460000 ; - RECT 2.890000 1.600000 3.180000 1.645000 ; - END -END sky130_fd_sc_hd__dlxtn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxtn_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxtn_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.240000 0.415000 5.525000 0.745000 ; - RECT 5.240000 1.495000 5.525000 2.455000 ; - RECT 5.355000 0.745000 5.525000 0.995000 ; - RECT 5.355000 0.995000 6.815000 1.325000 ; - RECT 5.355000 1.325000 5.525000 1.495000 ; - RECT 6.115000 0.385000 6.385000 0.995000 ; - RECT 6.115000 1.325000 6.385000 2.455000 ; - END - END Q - PIN GATE_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.330000 1.625000 ; - END - END GATE_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 2.005000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.840000 0.365000 3.500000 0.535000 ; - RECT 2.900000 2.255000 3.650000 2.425000 ; - RECT 2.925000 1.035000 3.095000 1.415000 ; - RECT 2.925000 1.415000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.200000 1.165000 ; - RECT 3.480000 1.165000 4.200000 1.325000 ; - RECT 3.480000 1.325000 3.650000 2.255000 ; - RECT 3.740000 0.085000 4.070000 0.530000 ; - RECT 3.820000 2.135000 4.120000 2.635000 ; - RECT 3.840000 1.535000 4.605000 1.865000 ; - RECT 4.385000 0.415000 4.605000 0.745000 ; - RECT 4.385000 1.865000 4.605000 2.435000 ; - RECT 4.435000 0.745000 4.605000 0.995000 ; - RECT 4.435000 0.995000 5.185000 1.325000 ; - RECT 4.435000 1.325000 4.605000 1.535000 ; - RECT 4.785000 0.085000 5.070000 0.715000 ; - RECT 4.785000 1.495000 5.070000 2.635000 ; - RECT 5.695000 0.085000 5.945000 0.825000 ; - RECT 5.695000 1.495000 5.945000 2.635000 ; - RECT 6.555000 0.085000 6.815000 0.715000 ; - RECT 6.555000 1.495000 6.815000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.785000 2.640000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 3.160000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 2.700000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.755000 2.700000 1.800000 ; - RECT 2.410000 1.940000 2.700000 1.985000 ; - RECT 2.870000 1.415000 3.160000 1.460000 ; - RECT 2.870000 1.600000 3.160000 1.645000 ; - END -END sky130_fd_sc_hd__dlxtn_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlxtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlxtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.460000 0.955000 1.790000 1.325000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.470250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.150000 0.415000 5.435000 0.745000 ; - RECT 5.150000 1.670000 5.435000 2.455000 ; - RECT 5.265000 0.745000 5.435000 1.670000 ; - END - END Q - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - END - END GATE - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.070000 ; - RECT 0.610000 1.070000 0.840000 1.400000 ; - RECT 0.610000 1.400000 0.780000 1.795000 ; - RECT 1.015000 0.345000 1.185000 1.685000 ; - RECT 1.015000 1.685000 1.240000 2.465000 ; - RECT 1.455000 1.495000 2.140000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.415000 ; - RECT 1.535000 0.345000 1.705000 0.615000 ; - RECT 1.535000 0.615000 2.140000 0.765000 ; - RECT 1.535000 0.765000 2.340000 0.785000 ; - RECT 1.875000 0.085000 2.205000 0.445000 ; - RECT 1.955000 1.835000 2.270000 2.635000 ; - RECT 1.970000 0.785000 2.340000 1.095000 ; - RECT 1.970000 1.095000 2.140000 1.495000 ; - RECT 2.470000 1.355000 2.755000 1.685000 ; - RECT 2.715000 0.705000 3.095000 1.035000 ; - RECT 2.770000 2.255000 3.605000 2.425000 ; - RECT 2.840000 0.365000 3.500000 0.535000 ; - RECT 2.925000 1.035000 3.095000 1.575000 ; - RECT 2.925000 1.575000 3.265000 1.995000 ; - RECT 3.330000 0.535000 3.500000 0.995000 ; - RECT 3.330000 0.995000 4.175000 1.165000 ; - RECT 3.435000 1.165000 4.175000 1.325000 ; - RECT 3.435000 1.325000 3.605000 2.255000 ; - RECT 3.685000 0.085000 4.015000 0.530000 ; - RECT 3.775000 2.135000 3.945000 2.635000 ; - RECT 3.840000 1.535000 4.515000 1.865000 ; - RECT 4.295000 0.415000 4.515000 0.745000 ; - RECT 4.295000 1.865000 4.515000 2.435000 ; - RECT 4.345000 0.745000 4.515000 0.995000 ; - RECT 4.345000 0.995000 5.095000 1.325000 ; - RECT 4.345000 1.325000 4.515000 1.535000 ; - RECT 4.695000 0.085000 4.900000 0.715000 ; - RECT 4.695000 1.570000 4.900000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.610000 1.445000 0.780000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 1.785000 1.240000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.470000 1.445000 2.640000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.785000 3.100000 1.955000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - LAYER met1 ; - RECT 0.550000 1.415000 0.840000 1.460000 ; - RECT 0.550000 1.460000 2.700000 1.600000 ; - RECT 0.550000 1.600000 0.840000 1.645000 ; - RECT 1.010000 1.755000 1.300000 1.800000 ; - RECT 1.010000 1.800000 3.160000 1.940000 ; - RECT 1.010000 1.940000 1.300000 1.985000 ; - RECT 2.410000 1.415000 2.700000 1.460000 ; - RECT 2.410000 1.600000 2.700000 1.645000 ; - RECT 2.870000 1.755000 3.160000 1.800000 ; - RECT 2.870000 1.940000 3.160000 1.985000 ; - END -END sky130_fd_sc_hd__dlxtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlygate4sd1_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlygate4sd1_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.555000 1.615000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.410000 0.255000 2.700000 0.825000 ; - RECT 2.440000 1.495000 2.700000 2.465000 ; - RECT 2.530000 0.825000 2.700000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.785000 0.895000 2.005000 ; - RECT 0.085000 2.005000 0.380000 2.465000 ; - RECT 0.095000 0.255000 0.380000 0.715000 ; - RECT 0.095000 0.715000 0.895000 0.885000 ; - RECT 0.550000 0.085000 0.765000 0.545000 ; - RECT 0.550000 2.175000 0.765000 2.635000 ; - RECT 0.725000 0.885000 0.895000 0.995000 ; - RECT 0.725000 0.995000 0.980000 1.325000 ; - RECT 0.725000 1.325000 0.895000 1.785000 ; - RECT 0.935000 0.255000 1.320000 0.545000 ; - RECT 0.935000 2.175000 1.320000 2.465000 ; - RECT 1.150000 0.545000 1.320000 1.075000 ; - RECT 1.150000 1.075000 1.900000 1.275000 ; - RECT 1.150000 1.275000 1.320000 2.175000 ; - RECT 1.515000 0.255000 1.740000 0.735000 ; - RECT 1.515000 0.735000 2.240000 0.905000 ; - RECT 1.515000 1.575000 2.240000 1.745000 ; - RECT 1.515000 1.745000 1.740000 2.430000 ; - RECT 1.910000 0.085000 2.240000 0.565000 ; - RECT 1.910000 1.915000 2.270000 2.635000 ; - RECT 2.070000 0.905000 2.240000 0.995000 ; - RECT 2.070000 0.995000 2.360000 1.325000 ; - RECT 2.070000 1.325000 2.240000 1.575000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__dlygate4sd1_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlygate4sd2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlygate4sd2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.625000 1.615000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.570000 0.255000 3.135000 0.825000 ; - RECT 2.570000 1.495000 3.135000 2.465000 ; - RECT 2.675000 0.825000 3.135000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.255000 0.485000 0.715000 ; - RECT 0.085000 0.715000 1.030000 0.885000 ; - RECT 0.085000 1.785000 1.030000 2.005000 ; - RECT 0.085000 2.005000 0.485000 2.465000 ; - RECT 0.655000 0.085000 0.925000 0.545000 ; - RECT 0.655000 2.175000 0.925000 2.635000 ; - RECT 0.795000 0.885000 1.030000 0.995000 ; - RECT 0.795000 0.995000 1.085000 1.325000 ; - RECT 0.795000 1.325000 1.030000 1.785000 ; - RECT 1.155000 0.255000 1.425000 0.585000 ; - RECT 1.155000 2.135000 1.425000 2.465000 ; - RECT 1.255000 0.585000 1.425000 1.055000 ; - RECT 1.255000 1.055000 2.030000 1.615000 ; - RECT 1.255000 1.615000 1.425000 2.135000 ; - RECT 1.615000 0.255000 1.875000 0.715000 ; - RECT 1.615000 0.715000 2.400000 0.885000 ; - RECT 1.615000 1.785000 2.400000 2.005000 ; - RECT 1.615000 2.005000 1.875000 2.465000 ; - RECT 2.075000 0.085000 2.400000 0.545000 ; - RECT 2.075000 2.175000 2.400000 2.635000 ; - RECT 2.200000 0.885000 2.400000 0.995000 ; - RECT 2.200000 0.995000 2.505000 1.325000 ; - RECT 2.200000 1.325000 2.400000 1.785000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__dlygate4sd2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlygate4sd3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlygate4sd3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.775000 1.615000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.210000 0.255000 3.595000 0.825000 ; - RECT 3.210000 1.495000 3.595000 2.465000 ; - RECT 3.315000 0.825000 3.595000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.200000 0.255000 0.485000 0.715000 ; - RECT 0.200000 0.715000 1.155000 0.885000 ; - RECT 0.200000 1.785000 1.155000 2.005000 ; - RECT 0.200000 2.005000 0.485000 2.465000 ; - RECT 0.655000 0.085000 0.925000 0.545000 ; - RECT 0.655000 2.175000 0.925000 2.635000 ; - RECT 0.945000 0.885000 1.155000 1.785000 ; - RECT 1.325000 0.255000 1.725000 1.055000 ; - RECT 1.325000 1.055000 2.420000 1.615000 ; - RECT 1.325000 1.615000 1.725000 2.465000 ; - RECT 1.915000 0.255000 2.195000 0.715000 ; - RECT 1.915000 0.715000 3.040000 0.885000 ; - RECT 1.915000 1.785000 3.040000 2.005000 ; - RECT 1.915000 2.005000 2.195000 2.465000 ; - RECT 2.590000 0.885000 3.040000 0.995000 ; - RECT 2.590000 0.995000 3.145000 1.325000 ; - RECT 2.590000 1.325000 3.040000 1.785000 ; - RECT 2.715000 0.085000 3.040000 0.545000 ; - RECT 2.715000 2.175000 3.040000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__dlygate4sd3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlymetal6s2s_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlymetal6s2s_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.570000 1.700000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - ANTENNAGATEAREA 0.126000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.245000 0.255000 1.670000 0.825000 ; - RECT 1.245000 1.495000 2.150000 1.675000 ; - RECT 1.245000 1.675000 1.670000 2.465000 ; - RECT 1.320000 0.825000 1.670000 0.995000 ; - RECT 1.320000 0.995000 2.150000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.120000 -0.085000 0.290000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.255000 0.520000 0.655000 ; - RECT 0.085000 0.655000 1.075000 0.825000 ; - RECT 0.085000 1.870000 1.075000 2.040000 ; - RECT 0.085000 2.040000 0.520000 2.465000 ; - RECT 0.690000 0.085000 1.075000 0.485000 ; - RECT 0.690000 2.210000 1.075000 2.635000 ; - RECT 0.740000 0.825000 1.075000 0.995000 ; - RECT 0.740000 0.995000 1.150000 1.325000 ; - RECT 0.740000 1.325000 1.075000 1.870000 ; - RECT 1.840000 1.845000 2.670000 2.040000 ; - RECT 1.840000 2.040000 2.115000 2.465000 ; - RECT 1.860000 0.255000 2.115000 0.655000 ; - RECT 1.860000 0.655000 2.670000 0.825000 ; - RECT 2.285000 0.085000 2.670000 0.485000 ; - RECT 2.285000 2.210000 2.670000 2.635000 ; - RECT 2.320000 0.825000 2.670000 0.995000 ; - RECT 2.320000 0.995000 2.745000 1.325000 ; - RECT 2.320000 1.325000 2.670000 1.845000 ; - RECT 2.840000 0.255000 3.085000 0.825000 ; - RECT 2.840000 1.495000 3.565000 1.675000 ; - RECT 2.840000 1.675000 3.085000 2.465000 ; - RECT 2.915000 0.825000 3.085000 0.995000 ; - RECT 2.915000 0.995000 3.565000 1.495000 ; - RECT 3.275000 0.255000 3.530000 0.655000 ; - RECT 3.275000 0.655000 4.085000 0.825000 ; - RECT 3.275000 1.845000 4.085000 2.040000 ; - RECT 3.275000 2.040000 3.530000 2.465000 ; - RECT 3.700000 0.085000 4.085000 0.485000 ; - RECT 3.700000 2.210000 4.085000 2.635000 ; - RECT 3.735000 0.825000 4.085000 0.995000 ; - RECT 3.735000 0.995000 4.160000 1.325000 ; - RECT 3.735000 1.325000 4.085000 1.845000 ; - RECT 4.255000 0.255000 4.515000 0.825000 ; - RECT 4.255000 1.495000 4.515000 2.465000 ; - RECT 4.330000 0.825000 4.515000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__dlymetal6s2s_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlymetal6s4s_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlymetal6s4s_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.570000 1.700000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - ANTENNAGATEAREA 0.126000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.660000 0.255000 3.105000 0.825000 ; - RECT 2.660000 1.495000 3.565000 1.675000 ; - RECT 2.660000 1.675000 3.105000 2.465000 ; - RECT 2.735000 0.825000 3.105000 0.995000 ; - RECT 2.735000 0.995000 3.565000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.120000 -0.085000 0.290000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.255000 0.520000 0.655000 ; - RECT 0.085000 0.655000 1.075000 0.825000 ; - RECT 0.085000 1.870000 1.075000 2.040000 ; - RECT 0.085000 2.040000 0.520000 2.465000 ; - RECT 0.690000 0.085000 1.075000 0.485000 ; - RECT 0.690000 2.210000 1.075000 2.635000 ; - RECT 0.740000 0.825000 1.075000 0.995000 ; - RECT 0.740000 0.995000 1.150000 1.325000 ; - RECT 0.740000 1.325000 1.075000 1.870000 ; - RECT 1.245000 0.255000 1.515000 0.825000 ; - RECT 1.245000 1.495000 1.970000 1.675000 ; - RECT 1.245000 1.675000 1.515000 2.465000 ; - RECT 1.320000 0.825000 1.515000 0.995000 ; - RECT 1.320000 0.995000 1.970000 1.495000 ; - RECT 1.685000 0.255000 1.935000 0.655000 ; - RECT 1.685000 0.655000 2.490000 0.825000 ; - RECT 1.685000 1.845000 2.490000 2.040000 ; - RECT 1.685000 2.040000 1.935000 2.465000 ; - RECT 2.105000 0.085000 2.490000 0.485000 ; - RECT 2.105000 2.210000 2.490000 2.635000 ; - RECT 2.140000 0.825000 2.490000 0.995000 ; - RECT 2.140000 0.995000 2.565000 1.325000 ; - RECT 2.140000 1.325000 2.490000 1.845000 ; - RECT 3.275000 0.255000 3.530000 0.655000 ; - RECT 3.275000 0.655000 4.085000 0.825000 ; - RECT 3.275000 1.845000 4.085000 2.040000 ; - RECT 3.275000 2.040000 3.530000 2.465000 ; - RECT 3.700000 0.085000 4.085000 0.485000 ; - RECT 3.700000 2.210000 4.085000 2.635000 ; - RECT 3.735000 0.825000 4.085000 0.995000 ; - RECT 3.735000 0.995000 4.160000 1.325000 ; - RECT 3.735000 1.325000 4.085000 1.845000 ; - RECT 4.255000 0.255000 4.515000 0.825000 ; - RECT 4.255000 1.495000 4.515000 2.465000 ; - RECT 4.330000 0.825000 4.515000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__dlymetal6s4s_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__dlymetal6s6s_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__dlymetal6s6s_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.575000 1.700000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.080000 0.255000 4.515000 0.825000 ; - RECT 4.080000 1.495000 4.515000 2.465000 ; - RECT 4.155000 0.825000 4.515000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.125000 -0.085000 0.295000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.255000 0.525000 0.655000 ; - RECT 0.085000 0.655000 1.080000 0.825000 ; - RECT 0.085000 1.870000 1.080000 2.040000 ; - RECT 0.085000 2.040000 0.525000 2.465000 ; - RECT 0.695000 0.085000 1.080000 0.485000 ; - RECT 0.695000 2.210000 1.080000 2.635000 ; - RECT 0.745000 0.825000 1.080000 0.995000 ; - RECT 0.745000 0.995000 1.155000 1.325000 ; - RECT 0.745000 1.325000 1.080000 1.870000 ; - RECT 1.250000 0.255000 1.520000 0.825000 ; - RECT 1.250000 1.495000 1.975000 1.675000 ; - RECT 1.250000 1.675000 1.520000 2.465000 ; - RECT 1.325000 0.825000 1.520000 0.995000 ; - RECT 1.325000 0.995000 1.975000 1.495000 ; - RECT 1.690000 0.255000 1.940000 0.655000 ; - RECT 1.690000 0.655000 2.495000 0.825000 ; - RECT 1.690000 1.845000 2.495000 2.040000 ; - RECT 1.690000 2.040000 1.940000 2.465000 ; - RECT 2.110000 0.085000 2.495000 0.485000 ; - RECT 2.110000 2.210000 2.495000 2.635000 ; - RECT 2.145000 0.825000 2.495000 0.995000 ; - RECT 2.145000 0.995000 2.570000 1.325000 ; - RECT 2.145000 1.325000 2.495000 1.845000 ; - RECT 2.665000 0.255000 2.915000 0.825000 ; - RECT 2.665000 1.495000 3.390000 1.675000 ; - RECT 2.665000 1.675000 2.915000 2.465000 ; - RECT 2.740000 0.825000 2.915000 0.995000 ; - RECT 2.740000 0.995000 3.390000 1.495000 ; - RECT 3.085000 0.255000 3.355000 0.655000 ; - RECT 3.085000 0.655000 3.910000 0.825000 ; - RECT 3.085000 1.845000 3.910000 2.040000 ; - RECT 3.085000 2.040000 3.355000 2.465000 ; - RECT 3.525000 0.085000 3.910000 0.485000 ; - RECT 3.525000 2.210000 3.910000 2.635000 ; - RECT 3.560000 0.825000 3.910000 0.995000 ; - RECT 3.560000 0.995000 3.985000 1.325000 ; - RECT 3.560000 1.325000 3.910000 1.845000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__dlymetal6s6s_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ebufn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ebufn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.355000 1.615000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.309000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.910000 1.075000 1.240000 1.630000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.601000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.975000 1.495000 3.595000 2.465000 ; - RECT 3.125000 0.255000 3.595000 0.825000 ; - RECT 3.255000 0.825000 3.595000 1.495000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.280000 0.345000 0.615000 ; - RECT 0.085000 0.615000 1.185000 0.825000 ; - RECT 0.085000 1.785000 0.740000 2.005000 ; - RECT 0.085000 2.005000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.515000 2.175000 0.845000 2.635000 ; - RECT 0.525000 0.825000 0.740000 1.785000 ; - RECT 1.015000 0.255000 2.025000 0.465000 ; - RECT 1.015000 0.465000 1.185000 0.615000 ; - RECT 1.015000 1.800000 1.805000 2.005000 ; - RECT 1.015000 2.005000 1.270000 2.460000 ; - RECT 1.355000 0.635000 1.685000 0.885000 ; - RECT 1.410000 0.885000 1.685000 1.075000 ; - RECT 1.410000 1.075000 2.535000 1.325000 ; - RECT 1.410000 1.325000 1.805000 1.800000 ; - RECT 1.440000 2.175000 1.805000 2.635000 ; - RECT 1.855000 0.465000 2.025000 0.735000 ; - RECT 1.855000 0.735000 2.955000 0.905000 ; - RECT 2.195000 0.085000 2.955000 0.565000 ; - RECT 2.705000 0.905000 2.955000 0.995000 ; - RECT 2.705000 0.995000 3.085000 1.325000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__ebufn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ebufn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ebufn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.490000 0.765000 0.780000 1.675000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.441000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.765000 1.280000 1.275000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.905000 1.445000 4.055000 1.625000 ; - RECT 1.905000 1.625000 3.625000 1.765000 ; - RECT 3.295000 0.635000 4.055000 0.855000 ; - RECT 3.295000 1.765000 3.625000 2.125000 ; - RECT 3.825000 0.855000 4.055000 1.445000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.280000 0.345000 0.615000 ; - RECT 0.085000 0.615000 0.320000 1.845000 ; - RECT 0.085000 1.845000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.850000 0.595000 ; - RECT 0.515000 1.845000 0.950000 2.635000 ; - RECT 1.020000 0.255000 1.730000 0.595000 ; - RECT 1.120000 1.445000 1.735000 1.765000 ; - RECT 1.120000 1.765000 1.410000 2.465000 ; - RECT 1.450000 0.595000 1.730000 1.025000 ; - RECT 1.450000 1.025000 2.965000 1.275000 ; - RECT 1.450000 1.275000 1.735000 1.445000 ; - RECT 1.600000 1.935000 3.125000 2.105000 ; - RECT 1.600000 2.105000 1.810000 2.465000 ; - RECT 1.900000 0.255000 2.170000 0.655000 ; - RECT 1.900000 0.655000 3.125000 0.855000 ; - RECT 1.980000 2.275000 2.310000 2.635000 ; - RECT 2.340000 0.085000 2.670000 0.485000 ; - RECT 2.480000 2.105000 3.125000 2.295000 ; - RECT 2.480000 2.295000 4.055000 2.465000 ; - RECT 2.840000 0.275000 4.050000 0.465000 ; - RECT 2.840000 0.465000 3.125000 0.655000 ; - RECT 3.245000 1.025000 3.655000 1.275000 ; - RECT 3.795000 1.795000 4.055000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.150000 1.105000 0.320000 1.275000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.380000 1.105000 3.550000 1.275000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - LAYER met1 ; - RECT 0.085000 1.075000 0.380000 1.120000 ; - RECT 0.085000 1.120000 3.610000 1.260000 ; - RECT 0.085000 1.260000 0.380000 1.305000 ; - RECT 3.320000 1.075000 3.610000 1.120000 ; - RECT 3.320000 1.260000 3.610000 1.305000 ; - END -END sky130_fd_sc_hd__ebufn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ebufn_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ebufn_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.490000 0.765000 0.780000 1.675000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.811500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.765000 1.280000 1.425000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.895000 1.445000 5.895000 1.725000 ; - RECT 4.145000 0.615000 5.895000 0.855000 ; - RECT 5.675000 0.855000 5.895000 1.445000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.280000 0.345000 0.665000 ; - RECT 0.085000 0.665000 0.320000 1.765000 ; - RECT 0.085000 1.765000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.930000 0.595000 ; - RECT 0.515000 1.845000 0.930000 2.635000 ; - RECT 1.100000 0.255000 1.725000 0.595000 ; - RECT 1.100000 1.595000 1.725000 1.765000 ; - RECT 1.100000 1.765000 1.355000 2.465000 ; - RECT 1.450000 0.595000 1.725000 1.025000 ; - RECT 1.450000 1.025000 3.810000 1.275000 ; - RECT 1.450000 1.275000 1.725000 1.595000 ; - RECT 1.565000 1.935000 5.895000 2.105000 ; - RECT 1.565000 2.105000 1.810000 2.465000 ; - RECT 1.895000 0.255000 2.175000 0.655000 ; - RECT 1.895000 0.655000 3.975000 0.855000 ; - RECT 1.895000 1.895000 5.895000 1.935000 ; - RECT 1.980000 2.275000 2.310000 2.635000 ; - RECT 2.345000 0.085000 2.675000 0.485000 ; - RECT 2.480000 2.105000 2.650000 2.465000 ; - RECT 2.820000 2.275000 3.150000 2.635000 ; - RECT 2.845000 0.275000 3.015000 0.655000 ; - RECT 3.185000 0.085000 3.515000 0.485000 ; - RECT 3.320000 2.105000 5.895000 2.465000 ; - RECT 3.685000 0.255000 5.735000 0.445000 ; - RECT 3.685000 0.445000 3.975000 0.655000 ; - RECT 3.980000 1.025000 5.505000 1.275000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.150000 1.105000 0.320000 1.275000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.310000 1.105000 4.480000 1.275000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 0.085000 1.075000 0.380000 1.120000 ; - RECT 0.085000 1.120000 4.540000 1.260000 ; - RECT 0.085000 1.260000 0.380000 1.305000 ; - RECT 4.250000 1.075000 4.540000 1.120000 ; - RECT 4.250000 1.260000 4.540000 1.305000 ; - END -END sky130_fd_sc_hd__ebufn_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ebufn_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ebufn_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.430000 1.615000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 1.375500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.970000 0.620000 1.305000 0.995000 ; - RECT 0.970000 0.995000 1.430000 1.325000 ; - RECT 0.970000 1.325000 1.305000 1.695000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.995000 1.445000 9.575000 1.725000 ; - RECT 6.275000 0.615000 9.575000 0.855000 ; - RECT 9.325000 0.855000 9.575000 1.445000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.085000 0.085000 0.445000 0.825000 ; - RECT 0.085000 1.785000 0.445000 2.635000 ; - RECT 0.600000 0.995000 0.800000 1.615000 ; - RECT 0.615000 0.280000 0.800000 0.995000 ; - RECT 0.615000 1.615000 0.800000 2.465000 ; - RECT 0.970000 0.085000 1.305000 0.445000 ; - RECT 0.970000 1.865000 1.305000 2.635000 ; - RECT 1.475000 0.255000 1.985000 0.825000 ; - RECT 1.475000 1.495000 1.825000 2.465000 ; - RECT 1.600000 0.825000 1.985000 1.025000 ; - RECT 1.600000 1.025000 5.925000 1.275000 ; - RECT 1.600000 1.275000 1.825000 1.495000 ; - RECT 1.995000 1.895000 9.575000 2.065000 ; - RECT 1.995000 2.065000 2.245000 2.465000 ; - RECT 2.155000 0.255000 2.485000 0.655000 ; - RECT 2.155000 0.655000 6.105000 0.855000 ; - RECT 2.415000 2.235000 2.745000 2.635000 ; - RECT 2.655000 0.085000 2.985000 0.485000 ; - RECT 2.915000 2.065000 3.085000 2.465000 ; - RECT 3.155000 0.275000 3.325000 0.655000 ; - RECT 3.255000 2.235000 3.585000 2.635000 ; - RECT 3.495000 0.085000 3.825000 0.485000 ; - RECT 3.755000 2.065000 3.925000 2.465000 ; - RECT 3.995000 0.255000 4.165000 0.655000 ; - RECT 4.095000 2.235000 4.425000 2.635000 ; - RECT 4.335000 0.085000 4.665000 0.485000 ; - RECT 4.595000 2.065000 4.765000 2.465000 ; - RECT 4.835000 0.275000 5.005000 0.655000 ; - RECT 4.935000 2.235000 5.265000 2.635000 ; - RECT 5.175000 0.085000 5.505000 0.485000 ; - RECT 5.435000 2.065000 9.575000 2.465000 ; - RECT 5.675000 0.255000 9.575000 0.445000 ; - RECT 5.675000 0.445000 6.105000 0.655000 ; - RECT 6.175000 1.025000 9.155000 1.275000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 1.105000 0.775000 1.275000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.580000 1.105000 6.750000 1.275000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.545000 1.075000 0.835000 1.120000 ; - RECT 0.545000 1.120000 6.810000 1.260000 ; - RECT 0.545000 1.260000 0.835000 1.305000 ; - RECT 6.520000 1.075000 6.810000 1.120000 ; - RECT 6.520000 1.260000 6.810000 1.305000 ; - END -END sky130_fd_sc_hd__ebufn_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__edfxbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__edfxbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.225000 0.255000 11.555000 2.420000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.400000 1.065000 9.845000 1.410000 ; - RECT 9.400000 1.410000 9.730000 2.465000 ; - RECT 9.515000 0.255000 9.845000 1.065000 ; - END - END Q_N - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.150000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.795000 1.125000 4.980000 1.720000 ; - RECT 4.815000 0.735000 5.320000 0.955000 ; - RECT 4.915000 2.175000 5.955000 2.375000 ; - RECT 5.005000 0.255000 5.680000 0.565000 ; - RECT 5.150000 0.955000 5.320000 1.655000 ; - RECT 5.150000 1.655000 5.615000 2.005000 ; - RECT 5.510000 0.565000 5.680000 1.315000 ; - RECT 5.510000 1.315000 6.360000 1.485000 ; - RECT 5.785000 1.485000 6.360000 1.575000 ; - RECT 5.785000 1.575000 5.955000 2.175000 ; - RECT 5.870000 0.765000 6.935000 1.045000 ; - RECT 5.870000 1.045000 7.445000 1.065000 ; - RECT 5.870000 1.065000 6.070000 1.095000 ; - RECT 5.945000 0.085000 6.340000 0.560000 ; - RECT 6.125000 1.835000 6.360000 2.635000 ; - RECT 6.190000 1.245000 6.360000 1.315000 ; - RECT 6.530000 0.255000 6.935000 0.765000 ; - RECT 6.530000 1.065000 7.445000 1.375000 ; - RECT 6.530000 1.375000 6.860000 2.465000 ; - RECT 7.070000 2.105000 7.360000 2.635000 ; - RECT 7.165000 0.085000 7.440000 0.615000 ; - RECT 7.790000 1.245000 7.980000 1.965000 ; - RECT 7.925000 2.165000 8.890000 2.355000 ; - RECT 8.005000 0.705000 8.470000 1.035000 ; - RECT 8.025000 0.330000 8.890000 0.535000 ; - RECT 8.150000 1.035000 8.470000 1.995000 ; - RECT 8.640000 0.535000 8.890000 2.165000 ; - RECT 9.060000 1.495000 9.230000 2.635000 ; - RECT 9.095000 0.085000 9.345000 0.900000 ; - RECT 9.900000 1.575000 10.130000 2.010000 ; - RECT 10.015000 0.890000 10.640000 1.220000 ; - RECT 10.300000 0.255000 10.640000 0.890000 ; - RECT 10.300000 1.220000 10.640000 2.465000 ; - RECT 10.810000 0.085000 11.055000 0.900000 ; - RECT 10.810000 1.465000 11.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.800000 1.445000 4.970000 1.615000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.210000 1.785000 5.380000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.800000 1.785000 7.970000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.220000 1.445000 8.390000 1.615000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.680000 1.785000 8.850000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 9.930000 1.785000 10.100000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.390000 0.765000 10.560000 0.935000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 8.030000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 8.450000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 10.620000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.740000 1.415000 5.030000 1.460000 ; - RECT 4.740000 1.600000 5.030000 1.645000 ; - RECT 5.150000 1.755000 5.440000 1.800000 ; - RECT 5.150000 1.940000 5.440000 1.985000 ; - RECT 7.740000 1.755000 8.030000 1.800000 ; - RECT 7.740000 1.940000 8.030000 1.985000 ; - RECT 8.160000 1.415000 8.450000 1.460000 ; - RECT 8.160000 1.600000 8.450000 1.645000 ; - RECT 8.620000 1.755000 8.910000 1.800000 ; - RECT 8.620000 1.800000 10.160000 1.940000 ; - RECT 8.620000 1.940000 8.910000 1.985000 ; - RECT 9.870000 1.755000 10.160000 1.800000 ; - RECT 9.870000 1.940000 10.160000 1.985000 ; - RECT 10.330000 0.735000 10.620000 0.780000 ; - RECT 10.330000 0.920000 10.620000 0.965000 ; - END -END sky130_fd_sc_hd__edfxbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__edfxtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__edfxtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.465000 0.305000 10.795000 2.420000 ; - END - END Q - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.795000 1.125000 4.980000 1.720000 ; - RECT 4.815000 0.735000 5.320000 0.955000 ; - RECT 4.915000 2.175000 5.955000 2.375000 ; - RECT 5.005000 0.255000 5.680000 0.565000 ; - RECT 5.150000 0.955000 5.320000 1.655000 ; - RECT 5.150000 1.655000 5.615000 2.005000 ; - RECT 5.510000 0.565000 5.680000 1.315000 ; - RECT 5.510000 1.315000 6.360000 1.485000 ; - RECT 5.785000 1.485000 6.360000 1.575000 ; - RECT 5.785000 1.575000 5.955000 2.175000 ; - RECT 5.870000 0.765000 6.935000 1.045000 ; - RECT 5.870000 1.045000 7.445000 1.065000 ; - RECT 5.870000 1.065000 6.070000 1.095000 ; - RECT 5.945000 0.085000 6.340000 0.560000 ; - RECT 6.125000 1.835000 6.360000 2.635000 ; - RECT 6.190000 1.245000 6.360000 1.315000 ; - RECT 6.530000 0.255000 6.935000 0.765000 ; - RECT 6.530000 1.065000 7.445000 1.375000 ; - RECT 6.530000 1.375000 6.860000 2.465000 ; - RECT 7.070000 2.105000 7.360000 2.635000 ; - RECT 7.165000 0.085000 7.440000 0.615000 ; - RECT 7.790000 1.245000 7.980000 1.965000 ; - RECT 7.925000 2.165000 8.810000 2.355000 ; - RECT 8.005000 0.705000 8.470000 1.035000 ; - RECT 8.025000 0.330000 8.810000 0.535000 ; - RECT 8.150000 1.035000 8.470000 1.995000 ; - RECT 8.640000 0.535000 8.810000 0.995000 ; - RECT 8.640000 0.995000 9.510000 1.325000 ; - RECT 8.640000 1.325000 8.810000 2.165000 ; - RECT 8.980000 1.530000 9.880000 1.905000 ; - RECT 8.980000 2.135000 9.240000 2.635000 ; - RECT 9.050000 0.085000 9.365000 0.615000 ; - RECT 9.540000 1.905000 9.880000 2.465000 ; - RECT 9.550000 0.300000 9.880000 0.825000 ; - RECT 9.690000 0.825000 9.880000 1.530000 ; - RECT 10.050000 0.085000 10.295000 0.900000 ; - RECT 10.050000 1.465000 10.295000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.800000 1.445000 4.970000 1.615000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.210000 1.785000 5.380000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.800000 1.785000 7.970000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.220000 1.445000 8.390000 1.615000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.700000 0.765000 9.870000 0.935000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 8.030000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 8.450000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 9.930000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.740000 1.415000 5.030000 1.460000 ; - RECT 4.740000 1.600000 5.030000 1.645000 ; - RECT 5.150000 1.755000 5.440000 1.800000 ; - RECT 5.150000 1.940000 5.440000 1.985000 ; - RECT 7.740000 1.755000 8.030000 1.800000 ; - RECT 7.740000 1.940000 8.030000 1.985000 ; - RECT 8.160000 1.415000 8.450000 1.460000 ; - RECT 8.160000 1.600000 8.450000 1.645000 ; - RECT 9.640000 0.735000 9.930000 0.780000 ; - RECT 9.640000 0.920000 9.930000 0.965000 ; - END -END sky130_fd_sc_hd__edfxtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvn_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvn_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.500000 0.765000 1.755000 1.955000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.222000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.650000 1.725000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.275600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.160000 0.255000 1.755000 0.595000 ; - RECT 1.160000 0.595000 1.330000 2.125000 ; - RECT 1.160000 2.125000 1.755000 2.465000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.085000 0.255000 0.360000 0.655000 ; - RECT 0.085000 0.655000 0.990000 0.825000 ; - RECT 0.085000 1.895000 0.990000 2.065000 ; - RECT 0.085000 2.065000 0.400000 2.465000 ; - RECT 0.530000 0.085000 0.990000 0.485000 ; - RECT 0.570000 2.235000 0.990000 2.635000 ; - RECT 0.820000 0.825000 0.990000 1.895000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__einvn_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.970000 0.765000 2.215000 1.615000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.309000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.955000 0.510000 1.725000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.040000 1.785000 2.215000 2.465000 ; - RECT 1.620000 0.255000 2.215000 0.595000 ; - RECT 1.620000 0.595000 1.800000 1.785000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.255000 0.370000 0.615000 ; - RECT 0.085000 0.615000 1.450000 0.785000 ; - RECT 0.085000 1.895000 0.870000 2.065000 ; - RECT 0.085000 2.065000 0.370000 2.465000 ; - RECT 0.540000 0.085000 1.440000 0.445000 ; - RECT 0.540000 2.235000 0.870000 2.635000 ; - RECT 0.685000 0.785000 1.450000 1.615000 ; - RECT 0.685000 1.615000 0.870000 1.895000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__einvn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.785000 1.075000 3.135000 1.275000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.441000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.325000 1.385000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.694800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.945000 1.445000 3.135000 1.695000 ; - RECT 2.365000 0.595000 2.695000 0.845000 ; - RECT 2.365000 0.845000 2.615000 1.445000 ; - RECT 2.785000 1.695000 3.135000 2.465000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 0.840000 0.825000 ; - RECT 0.085000 1.555000 0.895000 1.725000 ; - RECT 0.085000 1.725000 0.345000 2.465000 ; - RECT 0.495000 0.825000 0.840000 0.995000 ; - RECT 0.495000 0.995000 2.035000 1.275000 ; - RECT 0.495000 1.275000 0.895000 1.555000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 1.895000 0.895000 2.635000 ; - RECT 1.015000 0.255000 1.280000 0.655000 ; - RECT 1.015000 0.655000 2.195000 0.825000 ; - RECT 1.070000 1.445000 1.775000 1.865000 ; - RECT 1.070000 1.865000 2.615000 2.085000 ; - RECT 1.070000 2.085000 1.240000 2.465000 ; - RECT 1.410000 2.255000 2.275000 2.635000 ; - RECT 1.450000 0.085000 1.780000 0.485000 ; - RECT 1.950000 0.255000 3.135000 0.425000 ; - RECT 1.950000 0.425000 2.195000 0.655000 ; - RECT 2.445000 2.085000 2.615000 2.465000 ; - RECT 2.865000 0.425000 3.135000 0.775000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__einvn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvn_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvn_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.530000 0.620000 4.975000 1.325000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 0.811500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.345000 1.325000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.190000 0.620000 4.360000 1.480000 ; - RECT 3.190000 1.480000 3.520000 2.075000 ; - RECT 4.030000 1.480000 4.360000 2.075000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 0.845000 0.825000 ; - RECT 0.085000 1.495000 0.845000 1.665000 ; - RECT 0.085000 1.665000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 0.825000 0.845000 0.995000 ; - RECT 0.515000 0.995000 3.020000 1.325000 ; - RECT 0.515000 1.325000 0.845000 1.495000 ; - RECT 0.515000 1.835000 0.845000 2.635000 ; - RECT 1.015000 0.255000 1.285000 0.655000 ; - RECT 1.015000 0.655000 2.995000 0.825000 ; - RECT 1.015000 1.495000 3.020000 1.665000 ; - RECT 1.015000 1.665000 1.240000 2.465000 ; - RECT 1.410000 1.835000 1.740000 2.635000 ; - RECT 1.455000 0.085000 1.785000 0.485000 ; - RECT 1.910000 1.665000 2.080000 2.465000 ; - RECT 1.955000 0.255000 2.125000 0.655000 ; - RECT 2.250000 1.835000 2.640000 2.635000 ; - RECT 2.295000 0.085000 2.625000 0.485000 ; - RECT 2.810000 1.665000 3.020000 2.295000 ; - RECT 2.810000 2.295000 4.975000 2.465000 ; - RECT 2.825000 0.255000 4.975000 0.450000 ; - RECT 2.825000 0.450000 2.995000 0.655000 ; - RECT 3.690000 1.650000 3.860000 2.295000 ; - RECT 4.530000 1.650000 4.975000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__einvn_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvn_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvn_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.645000 0.995000 7.800000 1.285000 ; - END - END A - PIN TE_B - ANTENNAGATEAREA 1.375500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.995000 0.345000 1.325000 ; - END - END TE_B - PIN Z - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.870000 0.620000 8.195000 0.825000 ; - RECT 4.870000 1.455000 8.195000 1.625000 ; - RECT 4.870000 1.625000 5.200000 2.125000 ; - RECT 5.710000 1.625000 6.040000 2.125000 ; - RECT 6.550000 1.625000 6.880000 2.125000 ; - RECT 7.390000 1.625000 7.720000 2.125000 ; - RECT 7.970000 0.825000 8.195000 1.455000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.090000 0.255000 0.345000 0.655000 ; - RECT 0.090000 0.655000 0.845000 0.825000 ; - RECT 0.090000 1.495000 0.845000 1.665000 ; - RECT 0.090000 1.665000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 0.825000 0.845000 0.995000 ; - RECT 0.515000 0.995000 4.475000 1.325000 ; - RECT 0.515000 1.325000 0.845000 1.495000 ; - RECT 0.515000 1.835000 0.845000 2.635000 ; - RECT 1.015000 0.255000 1.285000 0.655000 ; - RECT 1.015000 0.655000 4.700000 0.825000 ; - RECT 1.015000 1.495000 4.700000 1.665000 ; - RECT 1.015000 1.665000 1.240000 2.465000 ; - RECT 1.410000 1.835000 1.740000 2.635000 ; - RECT 1.455000 0.085000 1.785000 0.485000 ; - RECT 1.910000 1.665000 2.080000 2.465000 ; - RECT 1.955000 0.255000 2.125000 0.655000 ; - RECT 2.250000 1.835000 2.580000 2.635000 ; - RECT 2.295000 0.085000 2.625000 0.485000 ; - RECT 2.750000 1.665000 2.920000 2.465000 ; - RECT 2.795000 0.255000 2.965000 0.655000 ; - RECT 3.090000 1.835000 3.420000 2.635000 ; - RECT 3.135000 0.085000 3.465000 0.485000 ; - RECT 3.590000 1.665000 3.760000 2.465000 ; - RECT 3.635000 0.255000 3.805000 0.655000 ; - RECT 3.930000 1.835000 4.280000 2.635000 ; - RECT 3.975000 0.085000 4.315000 0.485000 ; - RECT 4.450000 1.665000 4.700000 2.295000 ; - RECT 4.450000 2.295000 8.195000 2.465000 ; - RECT 4.485000 0.255000 8.195000 0.450000 ; - RECT 4.485000 0.450000 4.700000 0.655000 ; - RECT 5.370000 1.795000 5.540000 2.295000 ; - RECT 6.210000 1.795000 6.380000 2.295000 ; - RECT 7.050000 1.795000 7.220000 2.295000 ; - RECT 7.890000 1.795000 8.195000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - END -END sky130_fd_sc_hd__einvn_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.975000 0.975000 2.215000 1.955000 ; - END - END A - PIN TE - ANTENNAGATEAREA 0.223500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.545000 1.725000 ; - END - END TE - PIN Z - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.620000 0.255000 2.215000 0.805000 ; - RECT 1.620000 0.805000 1.795000 2.125000 ; - RECT 1.620000 2.125000 2.215000 2.465000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 1.450000 0.825000 ; - RECT 0.085000 1.895000 1.450000 2.065000 ; - RECT 0.085000 2.065000 0.345000 2.465000 ; - RECT 0.515000 0.085000 1.450000 0.485000 ; - RECT 0.515000 2.235000 1.450000 2.635000 ; - RECT 0.715000 0.825000 1.450000 1.895000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__einvp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.850000 0.765000 3.135000 1.615000 ; - END - END A - PIN TE - ANTENNAGATEAREA 0.354000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.330000 1.615000 ; - END - END TE - PIN Z - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.350000 0.595000 2.680000 2.125000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 0.875000 0.825000 ; - RECT 0.085000 1.785000 0.875000 1.955000 ; - RECT 0.085000 1.955000 0.345000 2.465000 ; - RECT 0.500000 0.825000 0.875000 0.995000 ; - RECT 0.500000 0.995000 2.180000 1.325000 ; - RECT 0.500000 1.325000 0.875000 1.785000 ; - RECT 0.515000 0.085000 0.875000 0.485000 ; - RECT 0.515000 2.125000 0.875000 2.635000 ; - RECT 1.045000 0.255000 1.240000 0.655000 ; - RECT 1.045000 0.655000 2.180000 0.825000 ; - RECT 1.045000 1.555000 2.155000 1.725000 ; - RECT 1.045000 1.725000 1.285000 2.465000 ; - RECT 1.410000 0.085000 1.770000 0.485000 ; - RECT 1.455000 1.895000 1.785000 2.635000 ; - RECT 1.940000 0.255000 3.135000 0.425000 ; - RECT 1.940000 0.425000 2.180000 0.655000 ; - RECT 1.985000 1.725000 2.155000 2.295000 ; - RECT 1.985000 2.295000 3.135000 2.465000 ; - RECT 2.850000 0.425000 3.135000 0.595000 ; - RECT 2.850000 1.785000 3.135000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__einvp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.740000 1.020000 4.975000 1.275000 ; - END - END A - PIN TE - ANTENNAGATEAREA 0.637500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.330000 1.615000 ; - END - END TE - PIN Z - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.190000 0.635000 4.975000 0.850000 ; - RECT 3.190000 0.850000 3.570000 1.445000 ; - RECT 3.190000 1.445000 4.360000 1.615000 ; - RECT 3.190000 1.615000 3.520000 2.125000 ; - RECT 4.030000 1.615000 4.360000 2.125000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 0.695000 0.825000 ; - RECT 0.085000 1.785000 0.875000 1.955000 ; - RECT 0.085000 1.955000 0.345000 2.465000 ; - RECT 0.500000 0.825000 0.695000 0.995000 ; - RECT 0.500000 0.995000 3.020000 1.325000 ; - RECT 0.500000 1.325000 0.875000 1.785000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 2.125000 0.875000 2.635000 ; - RECT 1.035000 0.255000 1.205000 0.655000 ; - RECT 1.035000 0.655000 3.020000 0.825000 ; - RECT 1.075000 1.555000 2.995000 1.725000 ; - RECT 1.075000 1.725000 1.285000 2.465000 ; - RECT 1.375000 0.085000 1.705000 0.485000 ; - RECT 1.455000 1.895000 1.785000 2.635000 ; - RECT 1.875000 0.255000 2.045000 0.655000 ; - RECT 1.955000 1.725000 2.125000 2.465000 ; - RECT 2.215000 0.085000 2.555000 0.485000 ; - RECT 2.295000 1.895000 2.655000 2.635000 ; - RECT 2.735000 0.255000 4.975000 0.465000 ; - RECT 2.735000 0.465000 3.020000 0.655000 ; - RECT 2.825000 1.725000 2.995000 2.295000 ; - RECT 2.825000 2.295000 4.975000 2.465000 ; - RECT 3.690000 1.785000 3.860000 2.295000 ; - RECT 4.530000 1.445000 4.975000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__einvp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__einvp_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__einvp_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.420000 1.020000 8.195000 1.275000 ; - END - END A - PIN TE - ANTENNAGATEAREA 1.027500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.330000 1.615000 ; - END - END TE - PIN Z - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.870000 0.635000 8.195000 0.850000 ; - RECT 4.870000 0.850000 5.250000 1.445000 ; - RECT 4.870000 1.445000 7.720000 1.615000 ; - RECT 4.870000 1.615000 5.200000 2.125000 ; - RECT 5.710000 1.615000 6.040000 2.125000 ; - RECT 6.550000 1.615000 6.880000 2.125000 ; - RECT 7.390000 1.615000 7.720000 2.125000 ; - END - END Z - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.655000 ; - RECT 0.085000 0.655000 0.695000 0.825000 ; - RECT 0.085000 1.785000 0.875000 1.955000 ; - RECT 0.085000 1.955000 0.345000 2.465000 ; - RECT 0.500000 0.825000 0.695000 0.995000 ; - RECT 0.500000 0.995000 4.700000 1.325000 ; - RECT 0.500000 1.325000 0.875000 1.785000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 2.125000 0.875000 2.635000 ; - RECT 1.035000 0.255000 1.205000 0.655000 ; - RECT 1.035000 0.655000 4.700000 0.825000 ; - RECT 1.075000 1.555000 4.700000 1.725000 ; - RECT 1.075000 1.725000 1.285000 2.465000 ; - RECT 1.375000 0.085000 1.705000 0.485000 ; - RECT 1.455000 1.895000 1.785000 2.635000 ; - RECT 1.875000 0.255000 2.045000 0.655000 ; - RECT 1.955000 1.725000 2.125000 2.465000 ; - RECT 2.215000 0.085000 2.545000 0.485000 ; - RECT 2.295000 1.895000 2.625000 2.635000 ; - RECT 2.715000 0.255000 2.885000 0.655000 ; - RECT 2.795000 1.725000 2.965000 2.465000 ; - RECT 3.055000 0.085000 3.385000 0.485000 ; - RECT 3.135000 1.895000 3.465000 2.635000 ; - RECT 3.555000 0.255000 3.725000 0.655000 ; - RECT 3.635000 1.725000 3.805000 2.465000 ; - RECT 3.895000 0.085000 4.235000 0.485000 ; - RECT 3.975000 1.895000 4.305000 2.635000 ; - RECT 4.405000 0.255000 8.195000 0.465000 ; - RECT 4.405000 0.465000 4.700000 0.655000 ; - RECT 4.475000 1.725000 4.700000 2.295000 ; - RECT 4.475000 2.295000 8.195000 2.465000 ; - RECT 5.370000 1.785000 5.540000 2.295000 ; - RECT 6.210000 1.785000 6.380000 2.295000 ; - RECT 7.050000 1.785000 7.220000 2.295000 ; - RECT 7.890000 1.445000 8.195000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - END -END sky130_fd_sc_hd__einvp_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fa_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fa_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.504000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.910000 0.995000 1.240000 1.275000 ; - RECT 0.910000 1.275000 1.080000 1.325000 ; - LAYER mcon ; - RECT 1.070000 1.105000 1.240000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.230000 1.030000 2.620000 1.360000 ; - LAYER mcon ; - RECT 2.450000 1.105000 2.620000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 4.250000 0.955000 4.625000 1.275000 ; - LAYER mcon ; - RECT 4.310000 1.105000 4.480000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.885000 1.035000 6.325000 1.275000 ; - LAYER mcon ; - RECT 6.150000 1.105000 6.320000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.010000 1.075000 1.300000 1.120000 ; - RECT 1.010000 1.120000 6.380000 1.260000 ; - RECT 1.010000 1.260000 1.300000 1.305000 ; - RECT 2.390000 1.075000 2.680000 1.120000 ; - RECT 2.390000 1.260000 2.680000 1.305000 ; - RECT 4.250000 1.075000 4.540000 1.120000 ; - RECT 4.250000 1.260000 4.540000 1.305000 ; - RECT 6.090000 1.075000 6.380000 1.120000 ; - RECT 6.090000 1.260000 6.380000 1.305000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.504000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.300000 1.445000 1.700000 1.880000 ; - LAYER mcon ; - RECT 1.530000 1.445000 1.700000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 3.200000 1.435000 3.560000 1.765000 ; - LAYER mcon ; - RECT 3.390000 1.445000 3.560000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 5.635000 1.445000 6.055000 1.765000 ; - LAYER mcon ; - RECT 5.690000 1.445000 5.860000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 1.470000 1.415000 1.760000 1.460000 ; - RECT 1.470000 1.460000 5.920000 1.600000 ; - RECT 1.470000 1.600000 1.760000 1.645000 ; - RECT 3.330000 1.415000 3.620000 1.460000 ; - RECT 3.330000 1.600000 3.620000 1.645000 ; - RECT 5.630000 1.415000 5.920000 1.460000 ; - RECT 5.630000 1.600000 5.920000 1.645000 ; - END - END B - PIN CIN - ANTENNAGATEAREA 0.378000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.670000 1.105000 2.040000 1.275000 ; - RECT 1.870000 1.275000 2.040000 1.595000 ; - RECT 1.870000 1.595000 2.960000 1.765000 ; - RECT 2.790000 0.965000 3.955000 1.250000 ; - RECT 2.790000 1.250000 2.960000 1.595000 ; - RECT 3.785000 1.250000 3.955000 1.515000 ; - RECT 3.785000 1.515000 5.405000 1.685000 ; - RECT 5.155000 1.685000 5.405000 1.955000 ; - END - END CIN - PIN COUT - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.345000 0.830000 ; - RECT 0.085000 0.830000 0.260000 1.485000 ; - RECT 0.085000 1.485000 0.345000 2.465000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.840000 0.255000 7.240000 0.810000 ; - RECT 6.840000 1.485000 7.240000 2.465000 ; - RECT 6.910000 0.810000 7.240000 1.485000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.430000 0.995000 0.685000 1.325000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 0.635000 1.710000 0.805000 ; - RECT 0.515000 0.805000 0.685000 0.995000 ; - RECT 0.515000 1.325000 0.685000 1.625000 ; - RECT 0.515000 1.625000 1.105000 1.945000 ; - RECT 0.515000 2.150000 0.765000 2.635000 ; - RECT 0.935000 1.945000 1.105000 2.065000 ; - RECT 0.935000 2.065000 1.710000 2.465000 ; - RECT 1.110000 0.255000 1.710000 0.635000 ; - RECT 1.470000 0.805000 1.710000 0.935000 ; - RECT 1.960000 0.255000 2.130000 0.615000 ; - RECT 1.960000 0.615000 2.970000 0.785000 ; - RECT 1.960000 1.935000 3.035000 2.105000 ; - RECT 1.960000 2.105000 2.130000 2.465000 ; - RECT 2.300000 0.085000 2.630000 0.445000 ; - RECT 2.300000 2.275000 2.630000 2.635000 ; - RECT 2.800000 0.255000 2.970000 0.615000 ; - RECT 2.800000 2.105000 3.035000 2.465000 ; - RECT 3.240000 0.085000 3.570000 0.490000 ; - RECT 3.240000 2.255000 3.570000 2.635000 ; - RECT 3.740000 0.255000 3.910000 0.615000 ; - RECT 3.740000 0.615000 4.750000 0.785000 ; - RECT 3.740000 1.935000 4.750000 2.105000 ; - RECT 3.740000 2.105000 3.910000 2.465000 ; - RECT 4.080000 0.085000 4.410000 0.445000 ; - RECT 4.080000 2.275000 4.410000 2.635000 ; - RECT 4.580000 0.255000 4.750000 0.615000 ; - RECT 4.580000 2.105000 4.750000 2.465000 ; - RECT 4.795000 0.955000 5.460000 1.125000 ; - RECT 4.965000 0.765000 5.460000 0.955000 ; - RECT 5.085000 0.255000 6.095000 0.505000 ; - RECT 5.085000 0.505000 5.255000 0.595000 ; - RECT 5.085000 2.125000 6.170000 2.465000 ; - RECT 5.925000 0.505000 6.095000 0.615000 ; - RECT 5.925000 0.615000 6.665000 0.785000 ; - RECT 6.000000 1.935000 6.665000 2.105000 ; - RECT 6.000000 2.105000 6.170000 2.125000 ; - RECT 6.265000 0.085000 6.595000 0.445000 ; - RECT 6.340000 2.275000 6.670000 2.635000 ; - RECT 6.495000 0.785000 6.665000 0.995000 ; - RECT 6.495000 0.995000 6.740000 1.325000 ; - RECT 6.495000 1.325000 6.665000 1.935000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 0.765000 1.700000 0.935000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.230000 0.765000 5.400000 0.935000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - LAYER met1 ; - RECT 1.470000 0.735000 1.760000 0.780000 ; - RECT 1.470000 0.780000 5.460000 0.920000 ; - RECT 1.470000 0.920000 1.760000 0.965000 ; - RECT 5.170000 0.735000 5.460000 0.780000 ; - RECT 5.170000 0.920000 5.460000 0.965000 ; - END -END sky130_fd_sc_hd__fa_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fa_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fa_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.631500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.245000 0.995000 1.755000 1.275000 ; - RECT 1.245000 1.275000 1.505000 1.325000 ; - LAYER mcon ; - RECT 1.525000 1.105000 1.695000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.685000 1.030000 3.075000 1.360000 ; - LAYER mcon ; - RECT 2.905000 1.105000 3.075000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 4.720000 0.955000 5.080000 1.275000 ; - LAYER mcon ; - RECT 4.765000 1.105000 4.935000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 6.105000 0.995000 6.960000 1.275000 ; - LAYER mcon ; - RECT 6.145000 1.105000 6.315000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.465000 1.075000 1.755000 1.120000 ; - RECT 1.465000 1.120000 6.375000 1.260000 ; - RECT 1.465000 1.260000 1.755000 1.305000 ; - RECT 2.845000 1.075000 3.135000 1.120000 ; - RECT 2.845000 1.260000 3.135000 1.305000 ; - RECT 4.705000 1.075000 4.995000 1.120000 ; - RECT 4.705000 1.260000 4.995000 1.305000 ; - RECT 6.085000 1.075000 6.375000 1.120000 ; - RECT 6.085000 1.260000 6.375000 1.305000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.631500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.645000 1.445000 2.155000 1.690000 ; - LAYER mcon ; - RECT 1.985000 1.445000 2.155000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 3.655000 1.435000 4.070000 1.745000 ; - LAYER mcon ; - RECT 3.845000 1.445000 4.015000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 6.150000 1.445000 6.835000 1.735000 ; - LAYER mcon ; - RECT 6.605000 1.445000 6.775000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 1.925000 1.415000 2.215000 1.460000 ; - RECT 1.925000 1.460000 6.835000 1.600000 ; - RECT 1.925000 1.600000 2.215000 1.645000 ; - RECT 3.785000 1.415000 4.075000 1.460000 ; - RECT 3.785000 1.600000 4.075000 1.645000 ; - RECT 6.545000 1.415000 6.835000 1.460000 ; - RECT 6.545000 1.600000 6.835000 1.645000 ; - END - END B - PIN CIN - ANTENNAGATEAREA 0.475500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.125000 1.105000 2.495000 1.275000 ; - RECT 2.325000 1.275000 2.495000 1.570000 ; - RECT 2.325000 1.570000 3.415000 1.740000 ; - RECT 3.245000 0.965000 4.465000 1.250000 ; - RECT 3.245000 1.250000 3.415000 1.570000 ; - RECT 4.295000 1.250000 4.465000 1.435000 ; - RECT 4.295000 1.435000 4.655000 1.515000 ; - RECT 4.295000 1.515000 5.920000 1.685000 ; - RECT 5.670000 1.355000 5.920000 1.515000 ; - RECT 5.670000 1.685000 5.920000 1.955000 ; - END - END CIN - PIN COUT - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.735000 0.690000 0.905000 ; - RECT 0.085000 0.905000 0.370000 1.415000 ; - RECT 0.085000 1.415000 0.735000 1.585000 ; - RECT 0.520000 0.315000 0.850000 0.485000 ; - RECT 0.520000 0.485000 0.690000 0.735000 ; - RECT 0.565000 1.585000 0.735000 1.780000 ; - RECT 0.565000 1.780000 0.810000 1.950000 ; - RECT 0.600000 1.950000 0.810000 2.465000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.523500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.395000 0.255000 7.725000 0.485000 ; - RECT 7.395000 1.795000 7.645000 1.965000 ; - RECT 7.395000 1.965000 7.565000 2.465000 ; - RECT 7.475000 0.485000 7.725000 0.735000 ; - RECT 7.475000 0.735000 8.195000 0.905000 ; - RECT 7.475000 1.415000 8.195000 1.585000 ; - RECT 7.475000 1.585000 7.645000 1.795000 ; - RECT 7.970000 0.905000 8.195000 1.415000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.180000 0.085000 0.350000 0.565000 ; - RECT 0.180000 1.795000 0.350000 2.635000 ; - RECT 0.540000 1.075000 1.075000 1.245000 ; - RECT 0.905000 0.655000 2.165000 0.825000 ; - RECT 0.905000 0.825000 1.075000 1.075000 ; - RECT 0.905000 1.245000 1.075000 1.430000 ; - RECT 0.905000 1.430000 1.110000 1.495000 ; - RECT 0.905000 1.495000 1.475000 1.600000 ; - RECT 0.940000 1.600000 1.475000 1.665000 ; - RECT 0.980000 2.275000 1.310000 2.635000 ; - RECT 1.020000 0.085000 1.350000 0.465000 ; - RECT 1.305000 1.665000 1.475000 1.910000 ; - RECT 1.305000 1.910000 2.245000 2.080000 ; - RECT 1.535000 0.255000 2.165000 0.655000 ; - RECT 1.900000 2.080000 2.245000 2.465000 ; - RECT 1.925000 0.825000 2.165000 0.935000 ; - RECT 2.415000 0.255000 2.585000 0.615000 ; - RECT 2.415000 0.615000 3.425000 0.785000 ; - RECT 2.415000 1.935000 3.490000 2.105000 ; - RECT 2.415000 2.105000 2.585000 2.465000 ; - RECT 2.755000 0.085000 3.085000 0.445000 ; - RECT 2.755000 2.275000 3.085000 2.635000 ; - RECT 3.255000 0.255000 3.425000 0.615000 ; - RECT 3.255000 2.105000 3.490000 2.465000 ; - RECT 3.695000 0.085000 4.025000 0.490000 ; - RECT 3.695000 1.915000 4.025000 2.635000 ; - RECT 4.195000 0.255000 4.365000 0.615000 ; - RECT 4.195000 0.615000 5.205000 0.785000 ; - RECT 4.195000 1.935000 5.205000 2.105000 ; - RECT 4.195000 2.105000 4.365000 2.465000 ; - RECT 4.535000 0.085000 4.865000 0.445000 ; - RECT 4.535000 2.275000 4.865000 2.635000 ; - RECT 5.035000 0.255000 5.205000 0.615000 ; - RECT 5.035000 2.105000 5.205000 2.465000 ; - RECT 5.250000 0.955000 5.935000 1.125000 ; - RECT 5.420000 0.765000 5.935000 0.955000 ; - RECT 5.485000 2.125000 6.685000 2.465000 ; - RECT 5.540000 0.255000 6.550000 0.505000 ; - RECT 5.540000 0.505000 5.710000 0.595000 ; - RECT 6.380000 0.505000 6.550000 0.655000 ; - RECT 6.380000 0.655000 7.300000 0.825000 ; - RECT 6.515000 1.935000 7.180000 2.105000 ; - RECT 6.515000 2.105000 6.685000 2.125000 ; - RECT 6.780000 0.085000 7.110000 0.445000 ; - RECT 6.890000 2.275000 7.220000 2.635000 ; - RECT 7.010000 1.470000 7.300000 1.640000 ; - RECT 7.010000 1.640000 7.180000 1.935000 ; - RECT 7.130000 0.825000 7.300000 1.075000 ; - RECT 7.130000 1.075000 7.800000 1.245000 ; - RECT 7.130000 1.245000 7.300000 1.470000 ; - RECT 7.815000 1.795000 7.985000 2.635000 ; - RECT 7.895000 0.085000 8.065000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 0.765000 2.155000 0.935000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.685000 0.765000 5.855000 0.935000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 1.925000 0.735000 2.215000 0.780000 ; - RECT 1.925000 0.780000 5.915000 0.920000 ; - RECT 1.925000 0.920000 2.215000 0.965000 ; - RECT 5.625000 0.735000 5.915000 0.780000 ; - RECT 5.625000 0.920000 5.915000 0.965000 ; - END -END sky130_fd_sc_hd__fa_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fa_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fa_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.633000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.080000 0.995000 2.680000 1.275000 ; - RECT 2.080000 1.275000 2.340000 1.325000 ; - LAYER mcon ; - RECT 2.450000 1.105000 2.620000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 3.610000 1.030000 4.000000 1.360000 ; - LAYER mcon ; - RECT 3.830000 1.105000 4.000000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.645000 0.955000 6.005000 1.275000 ; - LAYER mcon ; - RECT 5.690000 1.105000 5.860000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 7.030000 0.995000 7.885000 1.275000 ; - LAYER mcon ; - RECT 7.070000 1.105000 7.240000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 2.390000 1.075000 2.680000 1.120000 ; - RECT 2.390000 1.120000 7.300000 1.260000 ; - RECT 2.390000 1.260000 2.680000 1.305000 ; - RECT 3.770000 1.075000 4.060000 1.120000 ; - RECT 3.770000 1.260000 4.060000 1.305000 ; - RECT 5.630000 1.075000 5.920000 1.120000 ; - RECT 5.630000 1.260000 5.920000 1.305000 ; - RECT 7.010000 1.075000 7.300000 1.120000 ; - RECT 7.010000 1.260000 7.300000 1.305000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.633000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.480000 1.445000 3.080000 1.690000 ; - LAYER mcon ; - RECT 2.910000 1.445000 3.080000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 4.580000 1.435000 4.995000 1.745000 ; - LAYER mcon ; - RECT 4.770000 1.445000 4.940000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 7.075000 1.445000 7.760000 1.735000 ; - LAYER mcon ; - RECT 7.530000 1.445000 7.700000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 2.850000 1.415000 3.140000 1.460000 ; - RECT 2.850000 1.460000 7.760000 1.600000 ; - RECT 2.850000 1.600000 3.140000 1.645000 ; - RECT 4.710000 1.415000 5.000000 1.460000 ; - RECT 4.710000 1.600000 5.000000 1.645000 ; - RECT 7.470000 1.415000 7.760000 1.460000 ; - RECT 7.470000 1.600000 7.760000 1.645000 ; - END - END B - PIN CIN - ANTENNAGATEAREA 0.477000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.050000 1.105000 3.420000 1.275000 ; - RECT 3.250000 1.275000 3.420000 1.570000 ; - RECT 3.250000 1.570000 4.340000 1.740000 ; - RECT 4.170000 0.965000 5.390000 1.250000 ; - RECT 4.170000 1.250000 4.340000 1.570000 ; - RECT 5.220000 1.250000 5.390000 1.435000 ; - RECT 5.220000 1.435000 5.580000 1.515000 ; - RECT 5.220000 1.515000 6.845000 1.685000 ; - RECT 6.595000 1.355000 6.845000 1.515000 ; - RECT 6.595000 1.685000 6.845000 1.955000 ; - END - END CIN - PIN COUT - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.735000 1.525000 0.905000 ; - RECT 0.085000 0.905000 0.435000 1.415000 ; - RECT 0.085000 1.415000 1.570000 1.585000 ; - RECT 0.515000 0.255000 0.845000 0.735000 ; - RECT 0.515000 1.585000 0.845000 2.445000 ; - RECT 1.355000 0.315000 1.685000 0.485000 ; - RECT 1.355000 0.485000 1.525000 0.735000 ; - RECT 1.400000 1.585000 1.570000 1.780000 ; - RECT 1.400000 1.780000 1.645000 1.950000 ; - RECT 1.435000 1.950000 1.645000 2.465000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.943000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.320000 0.255000 8.650000 0.485000 ; - RECT 8.320000 1.795000 8.570000 1.965000 ; - RECT 8.320000 1.965000 8.490000 2.465000 ; - RECT 8.400000 0.485000 8.650000 0.735000 ; - RECT 8.400000 0.735000 10.035000 0.905000 ; - RECT 8.400000 1.415000 10.035000 1.585000 ; - RECT 8.400000 1.585000 8.570000 1.795000 ; - RECT 9.160000 0.270000 9.490000 0.735000 ; - RECT 9.160000 1.585000 9.490000 2.425000 ; - RECT 9.700000 0.905000 10.035000 1.415000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.175000 0.085000 0.345000 0.565000 ; - RECT 0.175000 1.795000 0.345000 2.635000 ; - RECT 0.605000 1.075000 1.910000 1.245000 ; - RECT 1.015000 0.085000 1.185000 0.565000 ; - RECT 1.015000 1.795000 1.185000 2.635000 ; - RECT 1.740000 0.655000 3.090000 0.825000 ; - RECT 1.740000 0.825000 1.910000 1.075000 ; - RECT 1.740000 1.245000 1.910000 1.430000 ; - RECT 1.740000 1.430000 1.945000 1.495000 ; - RECT 1.740000 1.495000 2.310000 1.600000 ; - RECT 1.775000 1.600000 2.310000 1.665000 ; - RECT 1.815000 2.275000 2.145000 2.635000 ; - RECT 1.855000 0.085000 2.185000 0.465000 ; - RECT 2.140000 1.665000 2.310000 1.910000 ; - RECT 2.140000 1.910000 3.170000 2.080000 ; - RECT 2.370000 0.255000 3.090000 0.655000 ; - RECT 2.735000 2.080000 3.170000 2.465000 ; - RECT 2.850000 0.825000 3.090000 0.935000 ; - RECT 3.340000 0.255000 3.510000 0.615000 ; - RECT 3.340000 0.615000 4.350000 0.785000 ; - RECT 3.340000 1.935000 4.415000 2.105000 ; - RECT 3.340000 2.105000 3.510000 2.465000 ; - RECT 3.680000 0.085000 4.010000 0.445000 ; - RECT 3.680000 2.275000 4.010000 2.635000 ; - RECT 4.180000 0.255000 4.350000 0.615000 ; - RECT 4.180000 2.105000 4.415000 2.465000 ; - RECT 4.620000 0.085000 4.950000 0.490000 ; - RECT 4.620000 1.915000 4.950000 2.635000 ; - RECT 5.120000 0.255000 5.290000 0.615000 ; - RECT 5.120000 0.615000 6.130000 0.785000 ; - RECT 5.120000 1.935000 6.130000 2.105000 ; - RECT 5.120000 2.105000 5.290000 2.465000 ; - RECT 5.460000 0.085000 5.790000 0.445000 ; - RECT 5.460000 2.275000 5.790000 2.635000 ; - RECT 5.960000 0.255000 6.130000 0.615000 ; - RECT 5.960000 2.105000 6.130000 2.465000 ; - RECT 6.175000 0.955000 6.860000 1.125000 ; - RECT 6.345000 0.765000 6.860000 0.955000 ; - RECT 6.410000 2.125000 7.610000 2.465000 ; - RECT 6.465000 0.255000 7.475000 0.505000 ; - RECT 6.465000 0.505000 6.635000 0.595000 ; - RECT 7.305000 0.505000 7.475000 0.655000 ; - RECT 7.305000 0.655000 8.225000 0.825000 ; - RECT 7.440000 1.935000 8.105000 2.105000 ; - RECT 7.440000 2.105000 7.610000 2.125000 ; - RECT 7.705000 0.085000 8.035000 0.445000 ; - RECT 7.815000 2.275000 8.145000 2.635000 ; - RECT 7.935000 1.470000 8.225000 1.640000 ; - RECT 7.935000 1.640000 8.105000 1.935000 ; - RECT 8.055000 0.825000 8.225000 1.075000 ; - RECT 8.055000 1.075000 9.445000 1.245000 ; - RECT 8.055000 1.245000 8.225000 1.470000 ; - RECT 8.740000 1.795000 8.910000 2.635000 ; - RECT 8.820000 0.085000 8.990000 0.565000 ; - RECT 9.660000 0.085000 9.830000 0.565000 ; - RECT 9.660000 1.795000 9.830000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.910000 0.765000 3.080000 0.935000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.610000 0.765000 6.780000 0.935000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - LAYER met1 ; - RECT 2.850000 0.735000 3.140000 0.780000 ; - RECT 2.850000 0.780000 6.840000 0.920000 ; - RECT 2.850000 0.920000 3.140000 0.965000 ; - RECT 6.550000 0.735000 6.840000 0.780000 ; - RECT 6.550000 0.920000 6.840000 0.965000 ; - END -END sky130_fd_sc_hd__fa_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fah_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fah_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.42000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.492000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 1.075000 1.440000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.691500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 1.075000 2.495000 1.275000 ; - RECT 1.990000 1.275000 2.190000 1.410000 ; - RECT 2.015000 1.410000 2.190000 1.725000 ; - LAYER mcon ; - RECT 1.990000 1.105000 2.160000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.675000 0.995000 5.925000 1.325000 ; - LAYER mcon ; - RECT 5.680000 1.105000 5.850000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.930000 1.075000 2.220000 1.120000 ; - RECT 1.930000 1.120000 5.910000 1.260000 ; - RECT 1.930000 1.260000 2.220000 1.305000 ; - RECT 5.620000 1.075000 5.910000 1.120000 ; - RECT 5.620000 1.260000 5.910000 1.305000 ; - END - END B - PIN CI - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.475000 1.075000 9.865000 1.325000 ; - RECT 9.690000 0.735000 10.010000 0.935000 ; - RECT 9.690000 0.935000 9.865000 1.075000 ; - END - END CI - PIN COUT - ANTENNADIFFAREA 0.435500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.870000 0.270000 11.310000 0.825000 ; - RECT 10.870000 0.825000 11.040000 1.495000 ; - RECT 10.870000 1.495000 11.390000 2.465000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.506000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.980000 0.255000 12.335000 0.825000 ; - RECT 11.985000 1.785000 12.335000 2.465000 ; - RECT 12.110000 0.825000 12.335000 1.785000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.420000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.610000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.420000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.420000 0.085000 ; - RECT 0.000000 2.635000 12.420000 2.805000 ; - RECT 0.085000 0.255000 0.425000 0.805000 ; - RECT 0.085000 0.805000 0.255000 1.500000 ; - RECT 0.085000 1.500000 0.445000 1.895000 ; - RECT 0.085000 1.895000 2.805000 2.065000 ; - RECT 0.085000 2.065000 0.395000 2.465000 ; - RECT 0.425000 0.995000 0.780000 1.325000 ; - RECT 0.565000 2.260000 0.930000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.595000 0.735000 1.320000 0.905000 ; - RECT 0.595000 0.905000 0.780000 0.995000 ; - RECT 0.610000 1.325000 0.780000 1.380000 ; - RECT 0.610000 1.380000 0.815000 1.445000 ; - RECT 0.610000 1.445000 1.315000 1.455000 ; - RECT 0.615000 1.455000 1.315000 1.615000 ; - RECT 0.985000 1.615000 1.315000 1.715000 ; - RECT 0.990000 0.255000 1.320000 0.735000 ; - RECT 1.490000 1.445000 1.820000 1.500000 ; - RECT 1.490000 1.500000 1.840000 1.725000 ; - RECT 1.500000 0.255000 1.840000 0.715000 ; - RECT 1.500000 0.715000 2.520000 0.885000 ; - RECT 1.500000 0.885000 1.820000 0.905000 ; - RECT 1.615000 0.905000 1.820000 1.445000 ; - RECT 2.010000 0.085000 2.180000 0.545000 ; - RECT 2.065000 2.235000 2.395000 2.635000 ; - RECT 2.350000 0.255000 4.840000 0.425000 ; - RECT 2.350000 0.425000 2.520000 0.715000 ; - RECT 2.360000 1.445000 2.860000 1.715000 ; - RECT 2.635000 2.065000 2.805000 2.295000 ; - RECT 2.635000 2.295000 4.950000 2.465000 ; - RECT 2.690000 0.595000 2.860000 1.445000 ; - RECT 3.030000 0.425000 4.840000 0.465000 ; - RECT 3.030000 0.465000 3.200000 1.955000 ; - RECT 3.030000 1.955000 4.320000 2.125000 ; - RECT 3.370000 0.635000 3.900000 0.805000 ; - RECT 3.370000 0.805000 3.540000 1.455000 ; - RECT 3.370000 1.455000 3.815000 1.785000 ; - RECT 3.985000 1.785000 4.320000 1.955000 ; - RECT 4.070000 0.645000 4.400000 0.735000 ; - RECT 4.070000 0.735000 4.560000 0.755000 ; - RECT 4.070000 0.755000 5.170000 0.780000 ; - RECT 4.070000 0.780000 5.155000 0.805000 ; - RECT 4.070000 0.805000 5.145000 0.905000 ; - RECT 4.070000 1.075000 4.400000 1.160000 ; - RECT 4.070000 1.160000 4.535000 1.615000 ; - RECT 4.480000 0.905000 5.145000 0.925000 ; - RECT 4.650000 0.465000 4.840000 0.585000 ; - RECT 4.705000 0.925000 4.875000 2.295000 ; - RECT 4.925000 0.735000 5.180000 0.740000 ; - RECT 4.925000 0.740000 5.170000 0.755000 ; - RECT 4.950000 0.715000 5.180000 0.735000 ; - RECT 4.980000 0.690000 5.180000 0.715000 ; - RECT 5.000000 0.655000 5.180000 0.690000 ; - RECT 5.010000 0.255000 6.100000 0.425000 ; - RECT 5.010000 0.425000 5.180000 0.655000 ; - RECT 5.125000 1.150000 5.505000 1.320000 ; - RECT 5.125000 1.320000 5.295000 2.295000 ; - RECT 5.125000 2.295000 7.560000 2.465000 ; - RECT 5.320000 0.865000 5.520000 0.925000 ; - RECT 5.320000 0.925000 5.505000 1.150000 ; - RECT 5.335000 0.840000 5.520000 0.865000 ; - RECT 5.350000 0.595000 5.520000 0.840000 ; - RECT 5.475000 1.700000 5.875000 2.030000 ; - RECT 5.750000 0.425000 6.100000 0.565000 ; - RECT 6.105000 0.740000 6.435000 1.275000 ; - RECT 6.105000 1.445000 6.460000 1.615000 ; - RECT 6.270000 0.255000 9.735000 0.425000 ; - RECT 6.270000 0.425000 6.600000 0.570000 ; - RECT 6.290000 1.615000 6.460000 1.955000 ; - RECT 6.290000 1.955000 7.220000 2.125000 ; - RECT 6.610000 0.755000 6.940000 0.925000 ; - RECT 6.610000 0.925000 6.880000 1.275000 ; - RECT 6.710000 1.275000 6.880000 1.785000 ; - RECT 6.770000 0.595000 6.940000 0.755000 ; - RECT 7.050000 1.060000 7.280000 1.130000 ; - RECT 7.050000 1.130000 7.245000 1.175000 ; - RECT 7.050000 1.175000 7.220000 1.955000 ; - RECT 7.065000 1.045000 7.280000 1.060000 ; - RECT 7.090000 1.010000 7.280000 1.045000 ; - RECT 7.110000 0.595000 7.445000 0.765000 ; - RECT 7.110000 0.765000 7.280000 1.010000 ; - RECT 7.390000 1.275000 7.620000 1.375000 ; - RECT 7.390000 1.375000 7.595000 1.400000 ; - RECT 7.390000 1.400000 7.575000 1.425000 ; - RECT 7.390000 1.425000 7.560000 2.295000 ; - RECT 7.450000 0.995000 7.620000 1.275000 ; - RECT 7.705000 0.425000 7.960000 0.825000 ; - RECT 7.730000 1.510000 7.960000 2.295000 ; - RECT 7.730000 2.295000 9.655000 2.465000 ; - RECT 7.790000 0.825000 7.960000 1.510000 ; - RECT 8.145000 1.955000 9.250000 2.125000 ; - RECT 8.155000 0.595000 8.405000 0.925000 ; - RECT 8.225000 0.925000 8.405000 1.445000 ; - RECT 8.225000 1.445000 8.910000 1.785000 ; - RECT 8.575000 0.595000 8.745000 1.105000 ; - RECT 8.575000 1.105000 9.250000 1.275000 ; - RECT 8.920000 0.685000 9.300000 0.935000 ; - RECT 9.080000 1.275000 9.250000 1.955000 ; - RECT 9.400000 0.425000 9.735000 0.515000 ; - RECT 9.420000 1.495000 10.350000 1.705000 ; - RECT 9.420000 1.705000 9.655000 2.295000 ; - RECT 9.840000 2.275000 10.175000 2.635000 ; - RECT 9.905000 0.085000 10.075000 0.565000 ; - RECT 10.180000 0.995000 10.350000 1.495000 ; - RECT 10.245000 0.285000 10.690000 0.825000 ; - RECT 10.345000 1.875000 10.690000 2.465000 ; - RECT 10.520000 0.825000 10.690000 1.875000 ; - RECT 11.210000 0.995000 11.460000 1.325000 ; - RECT 11.480000 0.085000 11.810000 0.825000 ; - RECT 11.560000 1.785000 11.815000 2.635000 ; - RECT 11.630000 0.995000 11.940000 1.615000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.450000 1.445000 2.620000 1.615000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.370000 0.765000 3.540000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.365000 1.445000 4.535000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.570000 1.785000 5.740000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.150000 0.765000 6.320000 0.935000 ; - RECT 6.150000 1.445000 6.320000 1.615000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.610000 1.105000 6.780000 1.275000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.460000 1.445000 8.630000 1.615000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 8.920000 0.765000 9.090000 0.935000 ; - RECT 9.080000 1.785000 9.250000 1.955000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.785000 10.690000 1.955000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.220000 1.105000 11.390000 1.275000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 11.680000 1.445000 11.850000 1.615000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - LAYER met1 ; - RECT 2.390000 1.415000 2.680000 1.460000 ; - RECT 2.390000 1.460000 6.380000 1.600000 ; - RECT 2.390000 1.600000 2.680000 1.645000 ; - RECT 3.310000 0.735000 3.600000 0.780000 ; - RECT 3.310000 0.780000 9.150000 0.920000 ; - RECT 3.310000 0.920000 3.600000 0.965000 ; - RECT 3.925000 1.755000 4.215000 1.800000 ; - RECT 3.925000 1.800000 5.800000 1.940000 ; - RECT 3.925000 1.940000 4.215000 1.985000 ; - RECT 4.305000 1.415000 4.595000 1.460000 ; - RECT 4.305000 1.600000 4.595000 1.645000 ; - RECT 5.510000 1.755000 5.800000 1.800000 ; - RECT 5.510000 1.940000 5.800000 1.985000 ; - RECT 6.090000 0.735000 6.380000 0.780000 ; - RECT 6.090000 0.920000 6.380000 0.965000 ; - RECT 6.090000 1.415000 6.380000 1.460000 ; - RECT 6.090000 1.600000 6.380000 1.645000 ; - RECT 6.550000 1.075000 6.840000 1.120000 ; - RECT 6.550000 1.120000 11.450000 1.260000 ; - RECT 6.550000 1.260000 6.840000 1.305000 ; - RECT 8.400000 1.415000 8.690000 1.460000 ; - RECT 8.400000 1.460000 11.910000 1.600000 ; - RECT 8.400000 1.600000 8.690000 1.645000 ; - RECT 8.860000 0.735000 9.150000 0.780000 ; - RECT 8.860000 0.920000 9.150000 0.965000 ; - RECT 9.020000 1.755000 9.310000 1.800000 ; - RECT 9.020000 1.800000 10.750000 1.940000 ; - RECT 9.020000 1.940000 9.310000 1.985000 ; - RECT 10.460000 1.755000 10.750000 1.800000 ; - RECT 10.460000 1.940000 10.750000 1.985000 ; - RECT 11.160000 1.075000 11.450000 1.120000 ; - RECT 11.160000 1.260000 11.450000 1.305000 ; - RECT 11.620000 1.415000 11.910000 1.460000 ; - RECT 11.620000 1.600000 11.910000 1.645000 ; - END -END sky130_fd_sc_hd__fah_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fahcin_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fahcin_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.42000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 1.075000 1.340000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.691500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.510000 0.665000 1.740000 1.325000 ; - LAYER mcon ; - RECT 1.525000 0.765000 1.695000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 4.240000 0.645000 4.490000 1.325000 ; - LAYER mcon ; - RECT 4.285000 0.765000 4.455000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 1.465000 0.735000 1.755000 0.780000 ; - RECT 1.465000 0.780000 4.515000 0.920000 ; - RECT 1.465000 0.920000 1.755000 0.965000 ; - RECT 4.225000 0.735000 4.515000 0.780000 ; - RECT 4.225000 0.920000 4.515000 0.965000 ; - END - END B - PIN CIN - ANTENNAGATEAREA 0.493500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.520000 1.075000 10.965000 1.275000 ; - END - END CIN - PIN COUT - ANTENNADIFFAREA 0.402800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.600000 0.755000 6.925000 0.925000 ; - RECT 6.600000 0.925000 6.870000 1.675000 ; - RECT 6.700000 1.675000 6.870000 1.785000 ; - RECT 6.755000 0.595000 6.925000 0.755000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.470250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.995000 0.255000 12.335000 0.825000 ; - RECT 12.000000 1.785000 12.335000 2.465000 ; - RECT 12.125000 0.825000 12.335000 1.785000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.420000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.610000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.420000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.420000 0.085000 ; - RECT 0.000000 2.635000 12.420000 2.805000 ; - RECT 0.085000 0.735000 0.430000 0.805000 ; - RECT 0.085000 0.805000 0.255000 1.500000 ; - RECT 0.085000 1.500000 0.440000 1.840000 ; - RECT 0.085000 1.840000 1.110000 2.010000 ; - RECT 0.085000 2.010000 0.430000 2.465000 ; - RECT 0.100000 0.255000 0.430000 0.735000 ; - RECT 0.425000 0.995000 0.780000 1.325000 ; - RECT 0.600000 2.180000 0.770000 2.635000 ; - RECT 0.610000 0.735000 1.325000 0.905000 ; - RECT 0.610000 0.905000 0.780000 0.995000 ; - RECT 0.610000 1.325000 0.780000 1.500000 ; - RECT 0.610000 1.500000 1.450000 1.670000 ; - RECT 0.630000 0.085000 0.800000 0.545000 ; - RECT 0.940000 2.010000 1.110000 2.215000 ; - RECT 0.940000 2.215000 1.970000 2.295000 ; - RECT 0.940000 2.295000 3.515000 2.385000 ; - RECT 0.995000 0.255000 3.390000 0.425000 ; - RECT 0.995000 0.425000 2.100000 0.465000 ; - RECT 0.995000 0.465000 1.325000 0.735000 ; - RECT 1.280000 1.670000 1.450000 1.785000 ; - RECT 1.280000 1.785000 2.050000 1.955000 ; - RECT 1.280000 1.955000 1.450000 2.045000 ; - RECT 1.715000 2.385000 3.515000 2.465000 ; - RECT 1.985000 0.675000 2.390000 1.350000 ; - RECT 2.220000 0.595000 2.390000 0.675000 ; - RECT 2.220000 1.350000 2.390000 1.785000 ; - RECT 2.515000 0.425000 3.390000 0.465000 ; - RECT 2.565000 1.785000 2.895000 2.045000 ; - RECT 2.620000 0.655000 3.025000 0.735000 ; - RECT 2.620000 0.735000 3.135000 0.755000 ; - RECT 2.620000 0.755000 3.730000 0.905000 ; - RECT 2.640000 1.075000 2.970000 1.095000 ; - RECT 2.640000 1.095000 3.120000 1.245000 ; - RECT 2.800000 1.245000 3.120000 1.265000 ; - RECT 2.950000 1.265000 3.120000 1.615000 ; - RECT 3.055000 0.905000 3.730000 0.925000 ; - RECT 3.215000 0.465000 3.390000 0.585000 ; - RECT 3.245000 2.110000 3.460000 2.295000 ; - RECT 3.290000 0.925000 3.460000 2.110000 ; - RECT 3.560000 0.255000 4.570000 0.425000 ; - RECT 3.560000 0.425000 3.730000 0.755000 ; - RECT 3.710000 1.150000 4.070000 1.320000 ; - RECT 3.710000 1.320000 3.880000 2.290000 ; - RECT 3.710000 2.290000 5.065000 2.460000 ; - RECT 3.900000 0.595000 4.070000 1.150000 ; - RECT 4.080000 1.695000 4.445000 2.120000 ; - RECT 4.240000 0.425000 4.570000 0.475000 ; - RECT 4.690000 1.385000 5.170000 1.725000 ; - RECT 4.815000 1.895000 5.995000 2.065000 ; - RECT 4.815000 2.065000 5.065000 2.290000 ; - RECT 4.830000 0.510000 5.000000 0.995000 ; - RECT 4.830000 0.995000 5.630000 1.325000 ; - RECT 4.830000 1.325000 5.170000 1.385000 ; - RECT 5.180000 0.085000 5.510000 0.805000 ; - RECT 5.260000 2.235000 5.590000 2.635000 ; - RECT 5.635000 1.555000 6.370000 1.725000 ; - RECT 5.680000 0.380000 5.970000 0.815000 ; - RECT 5.800000 0.815000 5.970000 1.555000 ; - RECT 5.825000 2.065000 5.995000 2.295000 ; - RECT 5.825000 2.295000 7.950000 2.465000 ; - RECT 6.140000 0.740000 6.425000 1.325000 ; - RECT 6.200000 1.725000 6.370000 1.895000 ; - RECT 6.200000 1.895000 6.530000 1.955000 ; - RECT 6.200000 1.955000 7.210000 2.125000 ; - RECT 6.255000 0.255000 7.695000 0.425000 ; - RECT 6.255000 0.425000 6.585000 0.570000 ; - RECT 7.040000 1.060000 7.270000 1.230000 ; - RECT 7.040000 1.230000 7.210000 1.955000 ; - RECT 7.100000 0.595000 7.350000 0.925000 ; - RECT 7.100000 0.925000 7.270000 1.060000 ; - RECT 7.380000 1.360000 7.610000 1.530000 ; - RECT 7.380000 1.530000 7.550000 2.125000 ; - RECT 7.440000 1.105000 7.695000 1.290000 ; - RECT 7.440000 1.290000 7.610000 1.360000 ; - RECT 7.520000 0.425000 7.695000 1.105000 ; - RECT 7.780000 1.550000 8.035000 1.720000 ; - RECT 7.780000 1.720000 7.950000 2.295000 ; - RECT 7.865000 0.255000 9.980000 0.425000 ; - RECT 7.865000 0.425000 8.035000 0.740000 ; - RECT 7.865000 0.995000 8.035000 1.550000 ; - RECT 8.220000 1.955000 8.390000 2.295000 ; - RECT 8.220000 2.295000 9.410000 2.465000 ; - RECT 8.305000 0.595000 8.555000 0.925000 ; - RECT 8.375000 0.925000 8.555000 1.445000 ; - RECT 8.375000 1.445000 8.670000 1.530000 ; - RECT 8.375000 1.530000 8.890000 1.785000 ; - RECT 8.560000 1.785000 8.890000 2.125000 ; - RECT 8.725000 0.595000 9.410000 0.765000 ; - RECT 8.835000 0.995000 9.070000 1.325000 ; - RECT 9.240000 0.765000 9.410000 1.875000 ; - RECT 9.240000 1.875000 10.885000 2.025000 ; - RECT 9.240000 2.025000 10.145000 2.030000 ; - RECT 9.240000 2.030000 10.130000 2.035000 ; - RECT 9.240000 2.035000 10.120000 2.040000 ; - RECT 9.240000 2.040000 10.105000 2.045000 ; - RECT 9.240000 2.045000 9.410000 2.295000 ; - RECT 9.640000 0.425000 9.980000 0.825000 ; - RECT 9.640000 0.825000 9.810000 1.535000 ; - RECT 9.640000 1.535000 10.010000 1.705000 ; - RECT 9.980000 0.995000 10.350000 1.325000 ; - RECT 10.055000 1.870000 10.885000 1.875000 ; - RECT 10.070000 1.865000 10.885000 1.870000 ; - RECT 10.085000 1.860000 10.885000 1.865000 ; - RECT 10.100000 1.855000 10.885000 1.860000 ; - RECT 10.180000 0.085000 10.350000 0.565000 ; - RECT 10.180000 0.735000 10.910000 0.905000 ; - RECT 10.180000 0.905000 10.350000 0.995000 ; - RECT 10.180000 1.325000 10.350000 1.445000 ; - RECT 10.180000 1.445000 10.885000 1.855000 ; - RECT 10.190000 2.195000 10.360000 2.635000 ; - RECT 10.530000 0.285000 10.910000 0.735000 ; - RECT 10.535000 2.025000 10.885000 2.465000 ; - RECT 11.075000 1.455000 11.405000 2.465000 ; - RECT 11.155000 0.270000 11.325000 0.680000 ; - RECT 11.155000 0.680000 11.405000 1.455000 ; - RECT 11.495000 0.085000 11.825000 0.510000 ; - RECT 11.575000 1.785000 11.830000 2.635000 ; - RECT 11.645000 0.995000 11.955000 1.615000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.880000 1.785000 2.050000 1.955000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 1.105000 2.155000 1.275000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.570000 1.785000 2.740000 1.955000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.950000 1.445000 3.120000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.140000 1.785000 4.310000 1.955000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.760000 1.445000 4.930000 1.615000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.140000 1.105000 6.310000 1.275000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.520000 0.765000 7.690000 0.935000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.440000 1.445000 8.610000 1.615000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 8.900000 1.105000 9.070000 1.275000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.220000 0.765000 11.390000 0.935000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 11.680000 1.445000 11.850000 1.615000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - LAYER met1 ; - RECT 1.820000 1.755000 2.110000 1.800000 ; - RECT 1.820000 1.800000 4.370000 1.940000 ; - RECT 1.820000 1.940000 2.110000 1.985000 ; - RECT 1.925000 1.075000 2.215000 1.120000 ; - RECT 1.925000 1.120000 9.130000 1.260000 ; - RECT 1.925000 1.260000 2.215000 1.305000 ; - RECT 2.510000 1.755000 2.800000 1.800000 ; - RECT 2.510000 1.940000 2.800000 1.985000 ; - RECT 2.890000 1.415000 3.180000 1.460000 ; - RECT 2.890000 1.460000 4.990000 1.600000 ; - RECT 2.890000 1.600000 3.180000 1.645000 ; - RECT 4.080000 1.755000 4.370000 1.800000 ; - RECT 4.080000 1.940000 4.370000 1.985000 ; - RECT 4.700000 1.415000 4.990000 1.460000 ; - RECT 4.700000 1.600000 4.990000 1.645000 ; - RECT 6.080000 1.075000 6.370000 1.120000 ; - RECT 6.080000 1.260000 6.370000 1.305000 ; - RECT 7.460000 0.735000 7.750000 0.780000 ; - RECT 7.460000 0.780000 11.450000 0.920000 ; - RECT 7.460000 0.920000 7.750000 0.965000 ; - RECT 8.380000 1.415000 8.670000 1.460000 ; - RECT 8.380000 1.460000 11.910000 1.600000 ; - RECT 8.380000 1.600000 8.670000 1.645000 ; - RECT 8.840000 1.075000 9.130000 1.120000 ; - RECT 8.840000 1.260000 9.130000 1.305000 ; - RECT 11.160000 0.735000 11.450000 0.780000 ; - RECT 11.160000 0.920000 11.450000 0.965000 ; - RECT 11.620000 1.415000 11.910000 1.460000 ; - RECT 11.620000 1.600000 11.910000 1.645000 ; - END -END sky130_fd_sc_hd__fahcin_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fahcon_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__fahcon_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.42000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 1.075000 1.340000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.937500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.510000 0.710000 1.780000 1.325000 ; - LAYER mcon ; - RECT 1.525000 0.765000 1.695000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 4.265000 0.645000 4.515000 1.325000 ; - LAYER mcon ; - RECT 4.310000 0.765000 4.480000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 1.465000 0.735000 1.755000 0.780000 ; - RECT 1.465000 0.780000 4.540000 0.920000 ; - RECT 1.465000 0.920000 1.755000 0.965000 ; - RECT 4.250000 0.735000 4.540000 0.780000 ; - RECT 4.250000 0.920000 4.540000 0.965000 ; - END - END B - PIN CI - ANTENNAGATEAREA 0.493500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.530000 1.075000 10.975000 1.275000 ; - END - END CI - PIN COUT_N - ANTENNADIFFAREA 0.402800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.610000 0.755000 6.935000 0.925000 ; - RECT 6.610000 0.925000 6.880000 1.675000 ; - RECT 6.710000 1.675000 6.880000 1.785000 ; - RECT 6.765000 0.595000 6.935000 0.755000 ; - END - END COUT_N - PIN SUM - ANTENNADIFFAREA 0.463750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.995000 0.255000 12.335000 0.825000 ; - RECT 12.010000 1.785000 12.335000 2.465000 ; - RECT 12.135000 0.825000 12.335000 1.785000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.420000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.610000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.420000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.420000 0.085000 ; - RECT 0.000000 2.635000 12.420000 2.805000 ; - RECT 0.085000 0.735000 0.430000 0.805000 ; - RECT 0.085000 0.805000 0.255000 1.500000 ; - RECT 0.085000 1.500000 0.440000 1.840000 ; - RECT 0.085000 1.840000 1.110000 2.010000 ; - RECT 0.085000 2.010000 0.430000 2.465000 ; - RECT 0.100000 0.255000 0.430000 0.735000 ; - RECT 0.425000 0.995000 0.780000 1.325000 ; - RECT 0.600000 2.180000 0.770000 2.635000 ; - RECT 0.610000 0.735000 1.325000 0.905000 ; - RECT 0.610000 0.905000 0.780000 0.995000 ; - RECT 0.610000 1.325000 0.780000 1.500000 ; - RECT 0.610000 1.500000 1.450000 1.670000 ; - RECT 0.630000 0.085000 0.800000 0.545000 ; - RECT 0.940000 2.010000 1.110000 2.215000 ; - RECT 0.940000 2.215000 2.545000 2.295000 ; - RECT 0.940000 2.295000 3.540000 2.385000 ; - RECT 0.995000 0.255000 3.410000 0.465000 ; - RECT 0.995000 0.465000 1.325000 0.735000 ; - RECT 1.280000 1.670000 1.450000 1.875000 ; - RECT 1.280000 1.875000 2.920000 2.045000 ; - RECT 1.965000 0.635000 2.470000 1.705000 ; - RECT 2.375000 2.385000 3.540000 2.465000 ; - RECT 2.640000 0.655000 3.025000 0.735000 ; - RECT 2.640000 0.735000 3.160000 0.755000 ; - RECT 2.640000 0.755000 3.750000 0.905000 ; - RECT 2.640000 1.075000 2.975000 1.160000 ; - RECT 2.640000 1.160000 3.100000 1.615000 ; - RECT 3.055000 0.905000 3.750000 0.925000 ; - RECT 3.240000 0.465000 3.410000 0.585000 ; - RECT 3.270000 0.925000 3.440000 2.295000 ; - RECT 3.580000 0.255000 4.595000 0.425000 ; - RECT 3.580000 0.425000 3.750000 0.755000 ; - RECT 3.725000 1.150000 4.095000 1.320000 ; - RECT 3.725000 1.320000 3.895000 2.295000 ; - RECT 3.725000 2.295000 5.100000 2.465000 ; - RECT 3.925000 0.595000 4.095000 1.150000 ; - RECT 4.210000 1.755000 4.380000 2.095000 ; - RECT 4.265000 0.425000 4.595000 0.475000 ; - RECT 4.700000 1.385000 5.180000 1.725000 ; - RECT 4.840000 0.510000 5.030000 0.995000 ; - RECT 4.840000 0.995000 5.180000 1.385000 ; - RECT 4.875000 1.895000 6.005000 2.065000 ; - RECT 4.875000 2.065000 5.100000 2.295000 ; - RECT 5.200000 0.085000 5.530000 0.805000 ; - RECT 5.270000 2.235000 5.600000 2.635000 ; - RECT 5.645000 1.555000 6.380000 1.725000 ; - RECT 5.700000 0.380000 5.980000 0.815000 ; - RECT 5.810000 0.815000 5.980000 1.555000 ; - RECT 5.835000 2.065000 6.005000 2.295000 ; - RECT 5.835000 2.295000 7.960000 2.465000 ; - RECT 6.150000 0.740000 6.435000 1.325000 ; - RECT 6.210000 1.725000 6.380000 1.895000 ; - RECT 6.210000 1.895000 6.540000 1.955000 ; - RECT 6.210000 1.955000 7.220000 2.125000 ; - RECT 6.265000 0.255000 7.700000 0.425000 ; - RECT 6.265000 0.425000 6.595000 0.570000 ; - RECT 7.050000 1.060000 7.280000 1.230000 ; - RECT 7.050000 1.230000 7.220000 1.955000 ; - RECT 7.110000 0.595000 7.360000 0.925000 ; - RECT 7.110000 0.925000 7.280000 1.060000 ; - RECT 7.390000 1.360000 7.620000 1.530000 ; - RECT 7.390000 1.530000 7.560000 2.125000 ; - RECT 7.450000 1.105000 7.700000 1.290000 ; - RECT 7.450000 1.290000 7.620000 1.360000 ; - RECT 7.530000 0.425000 7.700000 1.105000 ; - RECT 7.790000 1.550000 8.045000 1.720000 ; - RECT 7.790000 1.720000 7.960000 2.295000 ; - RECT 7.875000 0.995000 8.045000 1.550000 ; - RECT 7.935000 0.255000 9.450000 0.425000 ; - RECT 7.935000 0.425000 8.270000 0.825000 ; - RECT 8.230000 1.785000 8.400000 2.295000 ; - RECT 8.230000 2.295000 9.950000 2.465000 ; - RECT 8.440000 0.595000 8.900000 0.765000 ; - RECT 8.440000 0.765000 8.610000 1.445000 ; - RECT 8.440000 1.445000 8.740000 1.530000 ; - RECT 8.440000 1.530000 8.900000 1.615000 ; - RECT 8.570000 1.615000 8.900000 2.125000 ; - RECT 8.780000 0.995000 9.110000 1.275000 ; - RECT 9.070000 1.530000 9.450000 2.045000 ; - RECT 9.070000 2.045000 9.420000 2.125000 ; - RECT 9.280000 0.425000 9.450000 1.530000 ; - RECT 9.620000 2.215000 9.950000 2.295000 ; - RECT 9.650000 0.255000 10.020000 0.825000 ; - RECT 9.650000 0.825000 9.820000 1.535000 ; - RECT 9.650000 1.535000 9.950000 2.215000 ; - RECT 9.990000 0.995000 10.360000 1.325000 ; - RECT 10.120000 2.275000 10.455000 2.635000 ; - RECT 10.190000 0.735000 10.920000 0.905000 ; - RECT 10.190000 0.905000 10.360000 0.995000 ; - RECT 10.190000 1.325000 10.360000 1.455000 ; - RECT 10.190000 1.455000 10.835000 2.045000 ; - RECT 10.200000 0.085000 10.370000 0.565000 ; - RECT 10.540000 0.285000 10.920000 0.735000 ; - RECT 10.625000 2.045000 10.835000 2.465000 ; - RECT 11.085000 1.455000 11.415000 2.465000 ; - RECT 11.165000 0.270000 11.335000 0.680000 ; - RECT 11.165000 0.680000 11.415000 1.455000 ; - RECT 11.535000 0.085000 11.825000 0.555000 ; - RECT 11.585000 1.785000 11.840000 2.635000 ; - RECT 11.655000 0.995000 11.965000 1.615000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.280000 1.785000 1.450000 1.955000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 1.105000 2.155000 1.275000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 2.930000 1.445000 3.100000 1.615000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.210000 1.785000 4.380000 1.955000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.770000 1.445000 4.940000 1.615000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.150000 1.105000 6.320000 1.275000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.530000 0.765000 7.700000 0.935000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.450000 1.445000 8.620000 1.615000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 8.910000 1.105000 9.080000 1.275000 ; - RECT 9.280000 1.785000 9.450000 1.955000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.190000 1.785000 10.360000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.230000 0.765000 11.400000 0.935000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 11.690000 1.445000 11.860000 1.615000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - LAYER met1 ; - RECT 1.195000 1.755000 1.510000 1.800000 ; - RECT 1.195000 1.800000 4.440000 1.940000 ; - RECT 1.195000 1.940000 1.510000 1.985000 ; - RECT 1.925000 1.075000 2.215000 1.120000 ; - RECT 1.925000 1.120000 9.140000 1.260000 ; - RECT 1.925000 1.260000 2.215000 1.305000 ; - RECT 2.845000 1.415000 3.160000 1.460000 ; - RECT 2.845000 1.460000 5.000000 1.600000 ; - RECT 2.845000 1.600000 3.160000 1.645000 ; - RECT 4.150000 1.755000 4.440000 1.800000 ; - RECT 4.150000 1.940000 4.440000 1.985000 ; - RECT 4.710000 1.415000 5.000000 1.460000 ; - RECT 4.710000 1.600000 5.000000 1.645000 ; - RECT 6.090000 1.075000 6.380000 1.120000 ; - RECT 6.090000 1.260000 6.380000 1.305000 ; - RECT 7.470000 0.735000 7.760000 0.780000 ; - RECT 7.470000 0.780000 11.460000 0.920000 ; - RECT 7.470000 0.920000 7.760000 0.965000 ; - RECT 8.390000 1.415000 8.680000 1.460000 ; - RECT 8.390000 1.460000 11.920000 1.600000 ; - RECT 8.390000 1.600000 8.680000 1.645000 ; - RECT 8.850000 1.075000 9.140000 1.120000 ; - RECT 8.850000 1.260000 9.140000 1.305000 ; - RECT 9.195000 1.755000 9.510000 1.800000 ; - RECT 9.195000 1.800000 10.420000 1.940000 ; - RECT 9.195000 1.940000 9.510000 1.985000 ; - RECT 10.130000 1.755000 10.420000 1.800000 ; - RECT 10.130000 1.940000 10.420000 1.985000 ; - RECT 11.170000 0.735000 11.460000 0.780000 ; - RECT 11.170000 0.920000 11.460000 0.965000 ; - RECT 11.630000 1.415000 11.920000 1.460000 ; - RECT 11.630000 1.600000 11.920000 1.645000 ; - END -END sky130_fd_sc_hd__fahcon_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fill_1 - CLASS CORE SPACER ; - FOREIGN sky130_fd_sc_hd__fill_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.460000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.460000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.055000 0.260000 0.055000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.460000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.460000 0.085000 ; - RECT 0.000000 2.635000 0.460000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - END -END sky130_fd_sc_hd__fill_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fill_2 - CLASS CORE SPACER ; - FOREIGN sky130_fd_sc_hd__fill_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.920000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.920000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.155000 -0.050000 0.315000 0.060000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.110000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.920000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.920000 0.085000 ; - RECT 0.000000 2.635000 0.920000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - END -END sky130_fd_sc_hd__fill_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fill_4 - CLASS CORE SPACER ; - FOREIGN sky130_fd_sc_hd__fill_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.175000 -0.060000 0.285000 0.060000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__fill_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__fill_8 - CLASS CORE SPACER ; - FOREIGN sky130_fd_sc_hd__fill_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.130000 -0.120000 0.350000 0.050000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__fill_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ha_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ha_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.335000 1.315000 3.585000 1.485000 ; - RECT 3.360000 1.055000 3.585000 1.315000 ; - RECT 3.360000 1.485000 3.585000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.850000 1.345000 2.155000 1.655000 ; - RECT 1.850000 1.655000 3.165000 1.825000 ; - RECT 1.850000 1.825000 2.155000 2.375000 ; - END - END B - PIN COUT - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.175000 0.315000 4.515000 0.825000 ; - RECT 4.175000 1.565000 4.515000 2.415000 ; - RECT 4.330000 0.825000 4.515000 1.565000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.315000 0.425000 0.825000 ; - RECT 0.090000 0.825000 0.320000 1.565000 ; - RECT 0.090000 1.565000 0.425000 2.415000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.490000 1.075000 1.130000 1.245000 ; - RECT 0.595000 0.085000 0.790000 0.885000 ; - RECT 0.595000 1.515000 0.790000 2.275000 ; - RECT 0.595000 2.275000 1.260000 2.635000 ; - RECT 0.960000 0.345000 1.285000 0.675000 ; - RECT 0.960000 0.675000 1.130000 1.075000 ; - RECT 0.960000 1.245000 1.130000 1.935000 ; - RECT 0.960000 1.935000 1.680000 2.105000 ; - RECT 1.300000 0.975000 3.170000 1.145000 ; - RECT 1.300000 1.145000 1.470000 1.325000 ; - RECT 1.510000 2.105000 1.680000 2.355000 ; - RECT 1.535000 0.345000 1.705000 0.635000 ; - RECT 1.535000 0.635000 2.545000 0.805000 ; - RECT 1.875000 0.085000 2.205000 0.465000 ; - RECT 2.375000 0.345000 2.545000 0.635000 ; - RECT 2.450000 2.275000 3.120000 2.635000 ; - RECT 3.000000 0.345000 3.170000 0.715000 ; - RECT 3.000000 0.715000 4.005000 0.885000 ; - RECT 3.000000 0.885000 3.170000 0.975000 ; - RECT 3.350000 1.785000 4.005000 1.955000 ; - RECT 3.350000 1.955000 3.520000 2.355000 ; - RECT 3.755000 0.085000 4.005000 0.545000 ; - RECT 3.755000 2.125000 4.005000 2.635000 ; - RECT 3.835000 0.885000 4.005000 0.995000 ; - RECT 3.835000 0.995000 4.160000 1.325000 ; - RECT 3.835000 1.325000 4.005000 1.785000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__ha_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ha_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ha_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.790000 1.055000 4.045000 1.225000 ; - RECT 3.820000 1.225000 4.045000 1.675000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.310000 1.005000 2.615000 1.395000 ; - RECT 2.310000 1.395000 3.595000 1.675000 ; - END - END B - PIN COUT - ANTENNADIFFAREA 0.511500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.635000 0.315000 4.965000 0.825000 ; - RECT 4.715000 1.545000 4.965000 2.415000 ; - RECT 4.790000 0.825000 4.965000 1.545000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.511500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.555000 0.315000 0.885000 0.825000 ; - RECT 0.555000 0.825000 0.780000 1.565000 ; - RECT 0.555000 1.565000 0.885000 2.415000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.135000 0.085000 0.375000 0.885000 ; - RECT 0.135000 1.495000 0.375000 2.635000 ; - RECT 0.950000 1.075000 1.590000 1.245000 ; - RECT 1.055000 0.085000 1.250000 0.885000 ; - RECT 1.055000 1.515000 1.250000 2.635000 ; - RECT 1.420000 0.345000 1.745000 0.675000 ; - RECT 1.420000 0.675000 1.590000 1.075000 ; - RECT 1.420000 1.245000 1.590000 2.205000 ; - RECT 1.420000 2.205000 2.220000 2.375000 ; - RECT 1.760000 0.995000 1.930000 1.855000 ; - RECT 1.760000 1.855000 4.465000 2.025000 ; - RECT 1.995000 0.345000 2.165000 0.635000 ; - RECT 1.995000 0.635000 3.005000 0.805000 ; - RECT 2.335000 0.085000 2.665000 0.465000 ; - RECT 2.835000 0.345000 3.005000 0.635000 ; - RECT 2.850000 2.205000 3.640000 2.635000 ; - RECT 3.460000 0.345000 3.630000 0.715000 ; - RECT 3.460000 0.715000 4.465000 0.885000 ; - RECT 3.810000 2.025000 3.980000 2.355000 ; - RECT 4.215000 0.085000 4.465000 0.545000 ; - RECT 4.215000 2.205000 4.545000 2.635000 ; - RECT 4.295000 0.885000 4.465000 0.995000 ; - RECT 4.295000 0.995000 4.620000 1.325000 ; - RECT 4.295000 1.325000 4.465000 1.855000 ; - RECT 5.145000 0.085000 5.385000 0.885000 ; - RECT 5.145000 1.495000 5.385000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__ha_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__ha_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__ha_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.320000 1.075000 4.380000 1.245000 ; - RECT 4.210000 1.245000 4.380000 1.505000 ; - RECT 4.210000 1.505000 6.810000 1.675000 ; - RECT 5.625000 0.995000 5.795000 1.505000 ; - RECT 6.580000 0.995000 7.055000 1.325000 ; - RECT 6.580000 1.325000 6.810000 1.505000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.550000 0.995000 5.455000 1.165000 ; - RECT 4.550000 1.165000 4.720000 1.325000 ; - RECT 5.285000 0.730000 6.315000 0.825000 ; - RECT 5.285000 0.825000 5.535000 0.845000 ; - RECT 5.285000 0.845000 5.495000 0.875000 ; - RECT 5.285000 0.875000 5.455000 0.995000 ; - RECT 5.295000 0.720000 6.315000 0.730000 ; - RECT 5.310000 0.710000 6.315000 0.720000 ; - RECT 5.320000 0.695000 6.315000 0.710000 ; - RECT 5.335000 0.675000 6.315000 0.695000 ; - RECT 5.345000 0.655000 6.315000 0.675000 ; - RECT 6.085000 0.825000 6.315000 1.325000 ; - END - END B - PIN COUT - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.595000 0.315000 7.845000 0.735000 ; - RECT 7.595000 0.735000 8.685000 0.905000 ; - RECT 7.595000 1.415000 8.685000 1.585000 ; - RECT 7.595000 1.585000 7.765000 2.415000 ; - RECT 8.405000 0.315000 8.685000 0.735000 ; - RECT 8.405000 0.905000 8.685000 1.415000 ; - RECT 8.405000 1.585000 8.685000 2.415000 ; - END - END COUT - PIN SUM - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.315000 0.845000 1.065000 ; - RECT 0.515000 1.065000 1.550000 1.335000 ; - RECT 0.515000 1.335000 0.845000 2.415000 ; - RECT 1.355000 0.315000 1.685000 0.825000 ; - RECT 1.355000 0.825000 1.550000 1.065000 ; - RECT 1.355000 1.335000 1.550000 1.565000 ; - RECT 1.355000 1.565000 1.685000 2.415000 ; - END - END SUM - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.135000 0.085000 0.345000 0.885000 ; - RECT 0.135000 1.495000 0.345000 2.635000 ; - RECT 1.015000 0.085000 1.185000 0.885000 ; - RECT 1.015000 1.515000 1.185000 2.635000 ; - RECT 1.720000 1.075000 2.750000 1.245000 ; - RECT 1.855000 0.085000 2.095000 0.885000 ; - RECT 1.855000 1.495000 2.365000 2.635000 ; - RECT 2.270000 0.305000 3.385000 0.475000 ; - RECT 2.580000 0.645000 3.045000 0.815000 ; - RECT 2.580000 0.815000 2.750000 1.075000 ; - RECT 2.580000 1.245000 2.750000 1.765000 ; - RECT 2.580000 1.765000 3.700000 1.935000 ; - RECT 2.770000 1.935000 2.940000 2.355000 ; - RECT 2.920000 0.995000 3.090000 1.425000 ; - RECT 2.920000 1.425000 4.040000 1.595000 ; - RECT 3.190000 2.105000 3.360000 2.635000 ; - RECT 3.215000 0.475000 3.385000 0.645000 ; - RECT 3.215000 0.645000 5.115000 0.815000 ; - RECT 3.530000 1.935000 3.700000 2.205000 ; - RECT 3.530000 2.205000 4.330000 2.375000 ; - RECT 3.555000 0.085000 3.910000 0.465000 ; - RECT 3.870000 1.595000 4.040000 1.855000 ; - RECT 3.870000 1.855000 7.395000 2.025000 ; - RECT 4.080000 0.345000 4.250000 0.645000 ; - RECT 4.420000 0.085000 4.750000 0.465000 ; - RECT 4.920000 0.255000 5.190000 0.585000 ; - RECT 4.920000 0.585000 5.115000 0.645000 ; - RECT 5.240000 2.205000 5.570000 2.635000 ; - RECT 5.385000 0.085000 5.715000 0.465000 ; - RECT 5.835000 2.025000 6.005000 2.355000 ; - RECT 6.175000 0.295000 6.875000 0.465000 ; - RECT 6.175000 2.205000 6.505000 2.635000 ; - RECT 6.675000 2.025000 6.845000 2.355000 ; - RECT 6.705000 0.465000 6.875000 0.645000 ; - RECT 6.705000 0.645000 7.395000 0.815000 ; - RECT 7.055000 0.085000 7.385000 0.465000 ; - RECT 7.055000 2.205000 7.385000 2.635000 ; - RECT 7.225000 0.815000 7.395000 1.075000 ; - RECT 7.225000 1.075000 8.225000 1.245000 ; - RECT 7.225000 1.245000 7.395000 1.855000 ; - RECT 7.935000 1.755000 8.225000 2.635000 ; - RECT 8.015000 0.085000 8.225000 0.565000 ; - RECT 8.855000 0.085000 9.065000 0.885000 ; - RECT 8.855000 1.495000 9.065000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - END -END sky130_fd_sc_hd__ha_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.320000 1.075000 0.650000 1.315000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.720000 0.255000 1.050000 0.885000 ; - RECT 0.720000 1.485000 1.050000 2.465000 ; - RECT 0.820000 0.885000 1.050000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.320000 0.085000 0.550000 0.905000 ; - RECT 0.340000 1.495000 0.550000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__inv_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 0.435000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.525000 0.255000 0.855000 0.885000 ; - RECT 0.525000 1.485000 0.855000 2.465000 ; - RECT 0.605000 0.885000 0.855000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.125000 0.085000 0.355000 0.905000 ; - RECT 0.125000 1.495000 0.355000 2.635000 ; - RECT 1.025000 0.085000 1.235000 0.905000 ; - RECT 1.025000 1.495000 1.235000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__inv_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 1.735000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.565000 0.255000 0.895000 0.725000 ; - RECT 0.565000 0.725000 2.170000 0.905000 ; - RECT 0.565000 1.495000 2.170000 1.665000 ; - RECT 0.565000 1.665000 0.895000 2.465000 ; - RECT 1.405000 0.255000 1.735000 0.725000 ; - RECT 1.405000 1.665000 2.170000 1.685000 ; - RECT 1.405000 1.685000 1.735000 2.465000 ; - RECT 1.905000 0.905000 2.170000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.130000 0.085000 0.395000 0.545000 ; - RECT 0.130000 1.495000 0.395000 2.635000 ; - RECT 1.065000 0.085000 1.235000 0.545000 ; - RECT 1.065000 1.835000 1.235000 2.635000 ; - RECT 1.905000 0.085000 2.155000 0.550000 ; - RECT 1.905000 2.175000 2.115000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__inv_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_6 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_6 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.485000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 2.615000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 1.336500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.685000 1.495000 3.135000 1.665000 ; - RECT 0.685000 1.665000 1.015000 2.465000 ; - RECT 0.765000 0.255000 0.935000 0.725000 ; - RECT 0.765000 0.725000 3.135000 0.905000 ; - RECT 1.525000 1.665000 1.855000 2.465000 ; - RECT 1.605000 0.255000 1.775000 0.725000 ; - RECT 2.365000 1.665000 3.135000 1.685000 ; - RECT 2.365000 1.685000 2.695000 2.465000 ; - RECT 2.445000 0.255000 2.615000 0.725000 ; - RECT 2.785000 0.905000 3.135000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.130000 0.085000 0.395000 0.545000 ; - RECT 0.130000 1.495000 0.425000 2.635000 ; - RECT 1.185000 0.085000 1.355000 0.545000 ; - RECT 1.185000 1.835000 1.355000 2.635000 ; - RECT 2.025000 0.085000 2.195000 0.545000 ; - RECT 2.025000 1.835000 2.195000 2.635000 ; - RECT 2.785000 0.085000 3.035000 0.550000 ; - RECT 2.865000 2.175000 3.035000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__inv_6 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.680000 1.075000 3.535000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 4.055000 0.905000 ; - RECT 0.085000 0.905000 0.430000 1.495000 ; - RECT 0.085000 1.495000 4.055000 1.665000 ; - RECT 0.680000 0.255000 1.010000 0.715000 ; - RECT 0.680000 1.665000 1.010000 2.465000 ; - RECT 1.520000 0.255000 1.850000 0.715000 ; - RECT 1.520000 1.665000 1.850000 2.465000 ; - RECT 2.360000 0.255000 2.690000 0.715000 ; - RECT 2.360000 1.665000 2.690000 2.465000 ; - RECT 3.200000 0.255000 3.530000 0.715000 ; - RECT 3.200000 1.665000 3.530000 2.465000 ; - RECT 3.735000 0.905000 4.055000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.255000 0.085000 0.510000 0.545000 ; - RECT 0.255000 1.835000 0.510000 2.635000 ; - RECT 1.180000 0.085000 1.350000 0.545000 ; - RECT 1.180000 1.835000 1.350000 2.635000 ; - RECT 2.020000 0.085000 2.190000 0.545000 ; - RECT 2.020000 1.835000 2.190000 2.635000 ; - RECT 2.860000 0.085000 3.030000 0.545000 ; - RECT 2.860000 1.835000 3.030000 2.635000 ; - RECT 3.700000 0.085000 4.005000 0.545000 ; - RECT 3.700000 1.835000 4.000000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__inv_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_12 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_12 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 2.970000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.680000 1.075000 5.270000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 2.673000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 5.895000 0.905000 ; - RECT 0.085000 0.905000 0.510000 1.495000 ; - RECT 0.085000 1.495000 5.895000 1.665000 ; - RECT 0.680000 0.255000 1.010000 0.715000 ; - RECT 0.680000 1.665000 1.010000 2.465000 ; - RECT 1.520000 0.255000 1.850000 0.715000 ; - RECT 1.520000 1.665000 1.850000 2.465000 ; - RECT 2.360000 0.255000 2.690000 0.715000 ; - RECT 2.360000 1.665000 2.690000 2.465000 ; - RECT 3.200000 0.255000 3.530000 0.715000 ; - RECT 3.200000 1.665000 3.530000 2.465000 ; - RECT 4.040000 0.255000 4.370000 0.715000 ; - RECT 4.040000 1.665000 4.370000 2.465000 ; - RECT 4.880000 0.255000 5.210000 0.715000 ; - RECT 4.880000 1.665000 5.210000 2.465000 ; - RECT 5.545000 0.905000 5.895000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.255000 0.085000 0.510000 0.545000 ; - RECT 0.255000 1.835000 0.510000 2.635000 ; - RECT 1.180000 0.085000 1.350000 0.545000 ; - RECT 1.180000 1.835000 1.350000 2.635000 ; - RECT 2.020000 0.085000 2.190000 0.545000 ; - RECT 2.020000 1.835000 2.190000 2.635000 ; - RECT 2.860000 0.085000 3.030000 0.545000 ; - RECT 2.860000 1.835000 3.030000 2.635000 ; - RECT 3.700000 0.085000 3.870000 0.545000 ; - RECT 3.700000 1.835000 3.870000 2.635000 ; - RECT 4.540000 0.085000 4.710000 0.545000 ; - RECT 4.540000 1.835000 4.710000 2.635000 ; - RECT 5.555000 0.085000 5.895000 0.545000 ; - RECT 5.555000 1.835000 5.895000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__inv_12 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__inv_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__inv_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 3.960000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 5.525000 1.315000 ; - END - END A - PIN Y - ANTENNADIFFAREA 3.564000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.580000 0.255000 0.910000 0.715000 ; - RECT 0.580000 0.715000 6.790000 0.905000 ; - RECT 0.580000 1.495000 6.790000 1.665000 ; - RECT 0.580000 1.665000 0.910000 2.465000 ; - RECT 1.420000 0.255000 1.750000 0.715000 ; - RECT 1.420000 1.665000 1.750000 2.465000 ; - RECT 2.260000 0.255000 2.590000 0.715000 ; - RECT 2.260000 1.665000 2.590000 2.465000 ; - RECT 3.100000 0.255000 3.430000 0.715000 ; - RECT 3.100000 1.665000 3.430000 2.465000 ; - RECT 3.940000 0.255000 4.270000 0.715000 ; - RECT 3.940000 1.665000 4.270000 2.465000 ; - RECT 4.780000 0.255000 5.110000 0.715000 ; - RECT 4.780000 1.665000 5.110000 2.465000 ; - RECT 5.620000 0.255000 5.950000 0.715000 ; - RECT 5.620000 1.665000 5.950000 2.465000 ; - RECT 6.460000 0.255000 6.790000 0.715000 ; - RECT 6.460000 0.905000 6.790000 1.495000 ; - RECT 6.460000 1.665000 6.790000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.180000 0.085000 0.410000 0.885000 ; - RECT 0.200000 1.485000 0.410000 2.635000 ; - RECT 1.080000 0.085000 1.250000 0.545000 ; - RECT 1.080000 1.835000 1.250000 2.635000 ; - RECT 1.920000 0.085000 2.090000 0.545000 ; - RECT 1.920000 1.835000 2.090000 2.635000 ; - RECT 2.760000 0.085000 2.930000 0.545000 ; - RECT 2.760000 1.835000 2.930000 2.635000 ; - RECT 3.600000 0.085000 3.770000 0.545000 ; - RECT 3.600000 1.835000 3.770000 2.635000 ; - RECT 4.440000 0.085000 4.610000 0.545000 ; - RECT 4.440000 1.835000 4.610000 2.635000 ; - RECT 5.280000 0.085000 5.450000 0.545000 ; - RECT 5.280000 1.835000 5.450000 2.635000 ; - RECT 6.120000 0.085000 6.290000 0.545000 ; - RECT 6.120000 1.835000 6.290000 2.635000 ; - RECT 6.960000 0.085000 7.170000 0.885000 ; - RECT 6.960000 1.835000 7.170000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__inv_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_bleeder_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_bleeder_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN SHORT - ANTENNAGATEAREA 0.270000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.275000 1.040000 1.975000 1.730000 ; - END - END SHORT - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.285000 0.085000 0.615000 0.870000 ; - RECT 2.145000 0.540000 2.475000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_bleeder_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkbufkapwr_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkbufkapwr_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.196500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.985000 1.275000 1.355000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.340600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.345000 0.760000 ; - RECT 0.085000 0.760000 0.255000 1.560000 ; - RECT 0.085000 1.560000 0.355000 2.465000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.525000 1.875000 0.855000 2.465000 ; - LAYER mcon ; - RECT 0.610000 2.125000 0.780000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.310000 2.340000 ; - RECT 0.550000 2.080000 0.840000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.425000 1.060000 0.710000 1.390000 ; - RECT 0.525000 0.085000 0.855000 0.465000 ; - RECT 0.540000 0.635000 1.205000 0.805000 ; - RECT 0.540000 0.805000 0.710000 1.060000 ; - RECT 0.540000 1.390000 0.710000 1.535000 ; - RECT 0.540000 1.535000 1.205000 1.705000 ; - RECT 1.035000 0.255000 1.205000 0.635000 ; - RECT 1.035000 1.705000 1.205000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkbufkapwr_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkbufkapwr_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkbufkapwr_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.745000 0.785000 1.240000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.383400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.040000 0.255000 1.245000 0.655000 ; - RECT 1.040000 0.655000 1.725000 0.825000 ; - RECT 1.060000 1.750000 1.725000 1.970000 ; - RECT 1.060000 1.970000 1.245000 2.435000 ; - RECT 1.385000 0.825000 1.725000 1.750000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.525000 1.855000 0.855000 2.465000 ; - LAYER mcon ; - RECT 0.610000 2.125000 0.780000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.415000 2.140000 1.750000 2.465000 ; - LAYER mcon ; - RECT 1.495000 2.140000 1.665000 2.310000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.770000 2.340000 ; - RECT 0.550000 2.080000 0.840000 2.140000 ; - RECT 1.435000 2.080000 1.725000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.585000 ; - RECT 0.085000 0.585000 0.255000 1.410000 ; - RECT 0.085000 1.410000 1.215000 1.580000 ; - RECT 0.085000 1.580000 0.355000 2.435000 ; - RECT 0.555000 0.085000 0.830000 0.565000 ; - RECT 0.965000 0.995000 1.215000 1.410000 ; - RECT 1.415000 0.085000 1.750000 0.485000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkbufkapwr_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkbufkapwr_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkbufkapwr_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.213000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.755000 0.775000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.795200 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.345000 1.305000 0.735000 ; - RECT 1.010000 0.735000 2.660000 0.905000 ; - RECT 1.025000 1.835000 2.165000 1.965000 ; - RECT 1.025000 1.965000 1.390000 1.970000 ; - RECT 1.025000 1.970000 1.385000 1.975000 ; - RECT 1.025000 1.975000 1.370000 1.980000 ; - RECT 1.025000 1.980000 1.330000 2.000000 ; - RECT 1.025000 2.000000 1.325000 2.005000 ; - RECT 1.025000 2.005000 1.265000 2.465000 ; - RECT 1.185000 1.825000 2.165000 1.835000 ; - RECT 1.195000 1.820000 2.165000 1.825000 ; - RECT 1.205000 1.815000 2.165000 1.820000 ; - RECT 1.215000 1.805000 2.165000 1.815000 ; - RECT 1.245000 1.785000 2.165000 1.805000 ; - RECT 1.270000 1.750000 2.165000 1.785000 ; - RECT 1.905000 0.345000 2.165000 0.735000 ; - RECT 1.905000 1.415000 2.660000 1.585000 ; - RECT 1.905000 1.585000 2.165000 1.750000 ; - RECT 1.935000 1.965000 2.165000 2.465000 ; - RECT 2.255000 0.905000 2.660000 1.415000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.525000 1.835000 0.855000 2.465000 ; - LAYER mcon ; - RECT 0.610000 2.125000 0.780000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.435000 2.140000 1.765000 2.465000 ; - RECT 2.335000 1.765000 2.620000 2.465000 ; - LAYER mcon ; - RECT 1.495000 2.140000 1.665000 2.310000 ; - RECT 2.375000 2.125000 2.545000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 2.690000 2.340000 ; - RECT 0.550000 2.080000 0.840000 2.140000 ; - RECT 1.435000 2.080000 1.725000 2.140000 ; - RECT 2.315000 2.080000 2.605000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.255000 0.385000 0.585000 ; - RECT 0.085000 0.585000 0.255000 1.495000 ; - RECT 0.085000 1.495000 1.115000 1.665000 ; - RECT 0.085000 1.665000 0.355000 2.465000 ; - RECT 0.555000 0.085000 0.830000 0.565000 ; - RECT 0.945000 1.075000 2.085000 1.245000 ; - RECT 0.945000 1.245000 1.115000 1.495000 ; - RECT 1.475000 0.085000 1.730000 0.565000 ; - RECT 2.335000 0.085000 2.615000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkbufkapwr_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkbufkapwr_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkbufkapwr_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.426000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 0.400000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.590400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.420000 0.280000 1.680000 0.735000 ; - RECT 1.420000 0.735000 4.730000 0.905000 ; - RECT 1.420000 1.495000 4.730000 1.735000 ; - RECT 1.420000 1.735000 1.680000 2.460000 ; - RECT 2.280000 0.280000 2.540000 0.735000 ; - RECT 2.280000 1.735000 2.540000 2.460000 ; - RECT 3.140000 0.280000 3.400000 0.735000 ; - RECT 3.140000 1.735000 3.400000 2.460000 ; - RECT 3.760000 0.905000 4.730000 1.495000 ; - RECT 4.000000 0.280000 4.260000 0.735000 ; - RECT 4.000000 1.735000 4.260000 2.460000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.095000 1.525000 0.390000 2.465000 ; - LAYER mcon ; - RECT 0.175000 2.125000 0.345000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.990000 1.525000 1.250000 2.465000 ; - LAYER mcon ; - RECT 1.035000 2.125000 1.205000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.850000 1.905000 2.110000 2.465000 ; - LAYER mcon ; - RECT 1.890000 2.125000 2.060000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 2.710000 1.905000 2.970000 2.465000 ; - LAYER mcon ; - RECT 2.740000 2.125000 2.910000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 3.570000 1.905000 3.830000 2.465000 ; - LAYER mcon ; - RECT 3.620000 2.125000 3.790000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 4.430000 1.905000 4.725000 2.465000 ; - LAYER mcon ; - RECT 4.480000 2.125000 4.650000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 4.990000 2.340000 ; - RECT 0.115000 2.080000 0.405000 2.140000 ; - RECT 0.975000 2.080000 1.265000 2.140000 ; - RECT 1.830000 2.080000 2.120000 2.140000 ; - RECT 2.680000 2.080000 2.970000 2.140000 ; - RECT 3.560000 2.080000 3.850000 2.140000 ; - RECT 4.420000 2.080000 4.710000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.145000 0.085000 0.390000 0.545000 ; - RECT 0.570000 0.265000 0.820000 1.075000 ; - RECT 0.570000 1.075000 3.590000 1.325000 ; - RECT 0.570000 1.325000 0.820000 2.460000 ; - RECT 0.990000 0.085000 1.250000 0.610000 ; - RECT 1.850000 0.085000 2.110000 0.565000 ; - RECT 2.710000 0.085000 2.970000 0.565000 ; - RECT 3.570000 0.085000 3.830000 0.565000 ; - RECT 4.430000 0.085000 4.730000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkbufkapwr_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkbufkapwr_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkbufkapwr_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.852000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.400000 1.325000 ; - END - END A - PIN X - ANTENNADIFFAREA 3.180800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.280000 0.280000 2.540000 0.735000 ; - RECT 2.280000 0.735000 9.025000 0.905000 ; - RECT 2.315000 1.495000 9.025000 1.720000 ; - RECT 2.315000 1.720000 7.685000 1.735000 ; - RECT 2.315000 1.735000 2.540000 2.460000 ; - RECT 3.140000 0.280000 3.400000 0.735000 ; - RECT 3.140000 1.735000 3.400000 2.460000 ; - RECT 4.000000 0.280000 4.260000 0.735000 ; - RECT 4.000000 1.735000 4.260000 2.460000 ; - RECT 4.845000 0.280000 5.120000 0.735000 ; - RECT 4.860000 1.735000 5.120000 2.460000 ; - RECT 5.705000 0.280000 5.965000 0.735000 ; - RECT 5.705000 1.735000 5.965000 2.460000 ; - RECT 6.565000 0.280000 6.825000 0.735000 ; - RECT 6.565000 1.735000 6.825000 2.460000 ; - RECT 7.425000 0.280000 7.685000 0.735000 ; - RECT 7.425000 1.735000 7.685000 2.460000 ; - RECT 7.860000 0.905000 9.025000 1.495000 ; - RECT 8.295000 0.280000 8.555000 0.735000 ; - RECT 8.295000 1.720000 8.585000 2.460000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.095000 1.495000 0.425000 2.465000 ; - LAYER mcon ; - RECT 0.175000 2.125000 0.345000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.955000 1.495000 1.285000 2.465000 ; - LAYER mcon ; - RECT 1.035000 2.125000 1.205000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.815000 1.495000 2.145000 2.465000 ; - LAYER mcon ; - RECT 1.890000 2.125000 2.060000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 2.710000 1.905000 2.970000 2.465000 ; - LAYER mcon ; - RECT 2.740000 2.125000 2.910000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 3.570000 1.905000 3.830000 2.465000 ; - LAYER mcon ; - RECT 3.620000 2.125000 3.790000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 4.430000 1.905000 4.690000 2.465000 ; - LAYER mcon ; - RECT 4.480000 2.125000 4.650000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 5.290000 1.905000 5.535000 2.465000 ; - LAYER mcon ; - RECT 5.335000 2.125000 5.505000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 6.150000 1.905000 6.395000 2.465000 ; - LAYER mcon ; - RECT 6.195000 2.125000 6.365000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 7.010000 1.905000 7.255000 2.465000 ; - LAYER mcon ; - RECT 7.050000 2.125000 7.220000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 7.870000 1.905000 8.125000 2.465000 ; - LAYER mcon ; - RECT 7.900000 2.125000 8.070000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 8.755000 1.890000 9.025000 2.465000 ; - LAYER mcon ; - RECT 8.780000 2.125000 8.950000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 9.130000 2.340000 ; - RECT 0.115000 2.080000 0.405000 2.140000 ; - RECT 0.975000 2.080000 1.265000 2.140000 ; - RECT 1.830000 2.080000 2.120000 2.140000 ; - RECT 2.680000 2.080000 2.970000 2.140000 ; - RECT 3.560000 2.080000 3.850000 2.140000 ; - RECT 4.420000 2.080000 4.710000 2.140000 ; - RECT 5.275000 2.080000 5.565000 2.140000 ; - RECT 6.135000 2.080000 6.425000 2.140000 ; - RECT 6.990000 2.080000 7.280000 2.140000 ; - RECT 7.840000 2.080000 8.130000 2.140000 ; - RECT 8.720000 2.080000 9.010000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.085000 0.085000 0.390000 0.595000 ; - RECT 0.595000 0.265000 0.820000 1.075000 ; - RECT 0.595000 1.075000 7.690000 1.325000 ; - RECT 0.595000 1.325000 0.785000 2.465000 ; - RECT 0.990000 0.085000 1.250000 0.610000 ; - RECT 1.430000 0.265000 1.680000 1.075000 ; - RECT 1.455000 1.325000 1.645000 2.460000 ; - RECT 1.850000 0.085000 2.110000 0.645000 ; - RECT 2.710000 0.085000 2.970000 0.565000 ; - RECT 3.570000 0.085000 3.830000 0.565000 ; - RECT 4.430000 0.085000 4.675000 0.565000 ; - RECT 5.290000 0.085000 5.535000 0.565000 ; - RECT 6.145000 0.085000 6.395000 0.565000 ; - RECT 7.005000 0.085000 7.255000 0.565000 ; - RECT 7.865000 0.085000 8.125000 0.565000 ; - RECT 8.725000 0.085000 9.025000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkbufkapwr_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkinvkapwr_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkinvkapwr_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.315000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.375000 0.325000 1.325000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.336000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.590000 0.255000 0.840000 0.760000 ; - RECT 0.590000 0.760000 1.295000 0.945000 ; - RECT 0.595000 0.945000 1.295000 1.290000 ; - RECT 0.595000 1.290000 0.765000 2.465000 ; - END - END Y - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.665000 0.425000 2.465000 ; - LAYER mcon ; - RECT 0.155000 2.125000 0.325000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.935000 1.665000 1.295000 2.465000 ; - LAYER mcon ; - RECT 1.055000 2.125000 1.225000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.310000 2.340000 ; - RECT 0.095000 2.080000 0.385000 2.140000 ; - RECT 0.995000 2.080000 1.285000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 1.010000 0.085000 1.295000 0.590000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkinvkapwr_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkinvkapwr_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkinvkapwr_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.576000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.065000 1.305000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 0.662600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.155000 1.460000 1.755000 1.630000 ; - RECT 0.155000 1.630000 0.375000 2.435000 ; - RECT 1.025000 0.280000 1.250000 0.725000 ; - RECT 1.025000 0.725000 1.755000 0.895000 ; - RECT 1.045000 1.630000 1.235000 2.435000 ; - RECT 1.475000 0.895000 1.755000 1.460000 ; - END - END Y - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.545000 1.800000 0.875000 2.465000 ; - LAYER mcon ; - RECT 0.600000 2.125000 0.770000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.405000 1.800000 1.735000 2.465000 ; - LAYER mcon ; - RECT 1.500000 2.125000 1.670000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.770000 2.340000 ; - RECT 0.540000 2.080000 0.830000 2.140000 ; - RECT 1.440000 2.080000 1.730000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.560000 0.085000 0.855000 0.610000 ; - RECT 1.420000 0.085000 1.750000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkinvkapwr_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkinvkapwr_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkinvkapwr_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.152000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.445000 1.065000 2.660000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 1.075200 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.725000 3.135000 0.895000 ; - RECT 0.105000 0.895000 0.275000 1.460000 ; - RECT 0.105000 1.460000 3.135000 1.630000 ; - RECT 0.645000 1.630000 0.815000 2.435000 ; - RECT 1.030000 0.280000 1.290000 0.725000 ; - RECT 1.505000 1.630000 1.675000 2.435000 ; - RECT 1.890000 0.280000 2.145000 0.725000 ; - RECT 2.365000 1.630000 2.535000 2.435000 ; - RECT 2.835000 0.895000 3.135000 1.460000 ; - END - END Y - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.135000 1.800000 0.465000 2.465000 ; - LAYER mcon ; - RECT 0.195000 2.125000 0.365000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.995000 1.800000 1.325000 2.465000 ; - LAYER mcon ; - RECT 1.055000 2.125000 1.225000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.855000 1.800000 2.185000 2.465000 ; - LAYER mcon ; - RECT 1.955000 2.125000 2.125000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 2.715000 1.800000 3.045000 2.465000 ; - LAYER mcon ; - RECT 2.835000 2.125000 3.005000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 3.150000 2.340000 ; - RECT 0.135000 2.080000 0.425000 2.140000 ; - RECT 0.995000 2.080000 1.285000 2.140000 ; - RECT 1.895000 2.080000 2.185000 2.140000 ; - RECT 2.775000 2.080000 3.065000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.565000 0.085000 0.860000 0.555000 ; - RECT 1.460000 0.085000 1.720000 0.555000 ; - RECT 2.315000 0.085000 2.615000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkinvkapwr_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkinvkapwr_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkinvkapwr_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 2.304000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.455000 1.035000 4.865000 1.290000 ; - END - END A - PIN Y - ANTENNADIFFAREA 2.090400 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.115000 0.695000 5.440000 0.865000 ; - RECT 0.115000 0.865000 0.285000 1.460000 ; - RECT 0.115000 1.460000 5.440000 1.630000 ; - RECT 0.595000 1.630000 0.765000 2.435000 ; - RECT 1.440000 1.630000 1.610000 2.435000 ; - RECT 1.535000 0.280000 1.725000 0.695000 ; - RECT 2.280000 1.630000 2.450000 2.435000 ; - RECT 2.395000 0.280000 2.585000 0.695000 ; - RECT 3.120000 1.630000 3.290000 2.435000 ; - RECT 3.255000 0.280000 3.445000 0.695000 ; - RECT 3.960000 1.630000 4.130000 2.435000 ; - RECT 4.115000 0.280000 4.305000 0.695000 ; - RECT 4.800000 1.630000 4.970000 2.435000 ; - RECT 5.170000 0.865000 5.440000 1.460000 ; - END - END Y - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.095000 1.800000 0.425000 2.465000 ; - RECT 5.140000 1.800000 5.470000 2.465000 ; - LAYER mcon ; - RECT 0.130000 2.125000 0.300000 2.295000 ; - RECT 5.255000 2.125000 5.425000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.940000 1.800000 1.270000 2.465000 ; - LAYER mcon ; - RECT 0.990000 2.125000 1.160000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.780000 1.800000 2.110000 2.465000 ; - LAYER mcon ; - RECT 1.890000 2.125000 2.060000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 2.620000 1.800000 2.950000 2.465000 ; - LAYER mcon ; - RECT 2.770000 2.125000 2.940000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 3.460000 1.800000 3.790000 2.465000 ; - LAYER mcon ; - RECT 3.495000 2.125000 3.665000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 4.300000 1.800000 4.630000 2.465000 ; - LAYER mcon ; - RECT 4.355000 2.125000 4.525000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.080000 0.360000 2.140000 ; - RECT 0.070000 2.140000 5.910000 2.340000 ; - RECT 0.930000 2.080000 1.220000 2.140000 ; - RECT 1.830000 2.080000 2.120000 2.140000 ; - RECT 2.710000 2.080000 3.000000 2.140000 ; - RECT 3.435000 2.080000 3.725000 2.140000 ; - RECT 4.295000 2.080000 4.585000 2.140000 ; - RECT 5.195000 2.080000 5.485000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 1.035000 0.085000 1.365000 0.525000 ; - RECT 1.895000 0.085000 2.225000 0.525000 ; - RECT 2.755000 0.085000 3.085000 0.525000 ; - RECT 3.615000 0.085000 3.945000 0.525000 ; - RECT 4.475000 0.085000 4.805000 0.525000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkinvkapwr_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_clkinvkapwr_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_clkinvkapwr_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 4.608000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.345000 0.895000 2.155000 1.275000 ; - RECT 8.930000 0.895000 10.710000 1.275000 ; - LAYER mcon ; - RECT 1.525000 1.105000 1.695000 1.275000 ; - RECT 1.985000 1.105000 2.155000 1.275000 ; - RECT 9.345000 1.105000 9.515000 1.275000 ; - RECT 9.805000 1.105000 9.975000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.465000 1.075000 2.215000 1.120000 ; - RECT 1.465000 1.120000 10.035000 1.260000 ; - RECT 1.465000 1.260000 2.215000 1.305000 ; - RECT 9.285000 1.075000 10.035000 1.120000 ; - RECT 9.285000 1.260000 10.035000 1.305000 ; - END - END A - PIN Y - ANTENNADIFFAREA 4.520900 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.615000 1.455000 10.480000 1.665000 ; - RECT 0.615000 1.665000 0.785000 2.465000 ; - RECT 1.475000 1.665000 1.645000 2.465000 ; - RECT 2.325000 0.280000 2.550000 1.415000 ; - RECT 2.325000 1.415000 8.755000 1.455000 ; - RECT 2.335000 1.665000 2.505000 2.465000 ; - RECT 3.155000 0.280000 3.410000 1.415000 ; - RECT 3.195000 1.665000 3.365000 2.465000 ; - RECT 4.015000 0.280000 4.255000 1.415000 ; - RECT 4.055000 1.665000 4.225000 2.465000 ; - RECT 4.905000 0.280000 5.255000 1.415000 ; - RECT 5.080000 1.665000 5.250000 2.465000 ; - RECT 5.925000 0.280000 6.175000 1.415000 ; - RECT 5.965000 1.665000 6.135000 2.465000 ; - RECT 6.785000 0.280000 7.035000 1.415000 ; - RECT 6.825000 1.665000 6.995000 2.465000 ; - RECT 7.645000 0.280000 7.895000 1.415000 ; - RECT 7.685000 1.665000 7.855000 2.465000 ; - RECT 8.505000 0.280000 8.755000 1.415000 ; - RECT 8.545000 1.665000 8.715000 2.465000 ; - RECT 9.405000 1.665000 9.575000 2.465000 ; - RECT 10.265000 1.665000 10.435000 2.465000 ; - END - END Y - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.110000 1.495000 0.440000 2.465000 ; - RECT 10.610000 1.835000 10.940000 2.465000 ; - LAYER mcon ; - RECT 0.130000 2.125000 0.300000 2.295000 ; - RECT 10.720000 2.125000 10.890000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 0.965000 1.835000 1.295000 2.465000 ; - LAYER mcon ; - RECT 0.990000 2.125000 1.160000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 1.825000 1.835000 2.155000 2.465000 ; - LAYER mcon ; - RECT 1.890000 2.125000 2.060000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 2.685000 1.835000 3.015000 2.465000 ; - LAYER mcon ; - RECT 2.770000 2.125000 2.940000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 3.545000 1.835000 3.875000 2.465000 ; - LAYER mcon ; - RECT 3.690000 2.125000 3.860000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 4.425000 1.835000 4.755000 2.465000 ; - LAYER mcon ; - RECT 4.550000 2.125000 4.720000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 5.450000 1.835000 5.780000 2.465000 ; - LAYER mcon ; - RECT 5.450000 2.125000 5.620000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 6.315000 1.835000 6.645000 2.465000 ; - LAYER mcon ; - RECT 6.370000 2.125000 6.540000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 7.175000 1.835000 7.505000 2.465000 ; - LAYER mcon ; - RECT 7.230000 2.125000 7.400000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 8.035000 1.835000 8.365000 2.465000 ; - LAYER mcon ; - RECT 8.130000 2.125000 8.300000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 8.895000 1.835000 9.225000 2.465000 ; - LAYER mcon ; - RECT 8.960000 2.125000 9.130000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 9.755000 1.835000 10.085000 2.465000 ; - LAYER mcon ; - RECT 9.820000 2.125000 9.990000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.080000 0.360000 2.140000 ; - RECT 0.070000 2.140000 10.970000 2.340000 ; - RECT 0.930000 2.080000 1.220000 2.140000 ; - RECT 1.830000 2.080000 2.120000 2.140000 ; - RECT 2.710000 2.080000 3.000000 2.140000 ; - RECT 3.630000 2.080000 3.920000 2.140000 ; - RECT 4.490000 2.080000 4.780000 2.140000 ; - RECT 5.390000 2.080000 5.680000 2.140000 ; - RECT 6.310000 2.080000 6.600000 2.140000 ; - RECT 7.170000 2.080000 7.460000 2.140000 ; - RECT 8.070000 2.080000 8.360000 2.140000 ; - RECT 8.900000 2.080000 9.190000 2.140000 ; - RECT 9.760000 2.080000 10.050000 2.140000 ; - RECT 10.660000 2.080000 10.950000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 1.855000 0.085000 2.125000 0.610000 ; - RECT 2.720000 0.085000 2.985000 0.610000 ; - RECT 3.580000 0.085000 3.845000 0.610000 ; - RECT 4.465000 0.085000 4.730000 0.610000 ; - RECT 5.490000 0.085000 5.755000 0.610000 ; - RECT 6.350000 0.085000 6.575000 0.610000 ; - RECT 7.210000 0.085000 7.475000 0.610000 ; - RECT 8.070000 0.085000 8.335000 0.610000 ; - RECT 8.930000 0.085000 9.195000 0.610000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_clkinvkapwr_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_decapkapwr_3 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_decapkapwr_3 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.545000 1.295000 2.465000 ; - RECT 0.775000 1.005000 1.295000 1.545000 ; - LAYER mcon ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.605000 2.125000 0.775000 2.295000 ; - RECT 1.065000 2.125000 1.235000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.310000 2.340000 ; - RECT 0.085000 2.080000 1.295000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.085000 0.085000 1.295000 0.835000 ; - RECT 0.085000 0.835000 0.605000 1.375000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_decapkapwr_3 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_decapkapwr_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_decapkapwr_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.545000 1.755000 2.465000 ; - RECT 1.005000 1.025000 1.755000 1.545000 ; - LAYER mcon ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.605000 2.125000 0.775000 2.295000 ; - RECT 1.065000 2.125000 1.235000 2.295000 ; - RECT 1.525000 2.125000 1.695000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 1.770000 2.340000 ; - RECT 0.085000 2.080000 1.755000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.085000 0.085000 1.755000 0.855000 ; - RECT 0.085000 0.855000 0.835000 1.375000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_decapkapwr_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_decapkapwr_6 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_decapkapwr_6 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.545000 2.675000 2.465000 ; - RECT 1.465000 1.025000 2.675000 1.545000 ; - LAYER mcon ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.605000 2.125000 0.775000 2.295000 ; - RECT 1.065000 2.125000 1.235000 2.295000 ; - RECT 1.525000 2.125000 1.695000 2.295000 ; - RECT 1.985000 2.125000 2.155000 2.295000 ; - RECT 2.445000 2.125000 2.615000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 2.690000 2.340000 ; - RECT 0.085000 2.080000 2.675000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.085000 2.675000 0.855000 ; - RECT 0.085000 0.855000 1.295000 1.375000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_decapkapwr_6 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_decapkapwr_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_decapkapwr_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.545000 3.595000 2.465000 ; - RECT 1.905000 1.025000 3.595000 1.545000 ; - LAYER mcon ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.605000 2.125000 0.775000 2.295000 ; - RECT 1.065000 2.125000 1.235000 2.295000 ; - RECT 1.525000 2.125000 1.695000 2.295000 ; - RECT 1.985000 2.125000 2.155000 2.295000 ; - RECT 2.445000 2.125000 2.615000 2.295000 ; - RECT 2.905000 2.125000 3.075000 2.295000 ; - RECT 3.365000 2.125000 3.535000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 3.610000 2.340000 ; - RECT 0.085000 2.080000 3.595000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.085000 3.595000 0.855000 ; - RECT 0.085000 0.855000 1.735000 1.375000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_decapkapwr_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_decapkapwr_12 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_decapkapwr_12 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.545000 5.430000 2.465000 ; - RECT 2.835000 1.025000 5.430000 1.545000 ; - LAYER mcon ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.605000 2.125000 0.775000 2.295000 ; - RECT 1.065000 2.125000 1.235000 2.295000 ; - RECT 1.525000 2.125000 1.695000 2.295000 ; - RECT 1.985000 2.125000 2.155000 2.295000 ; - RECT 2.445000 2.125000 2.615000 2.295000 ; - RECT 2.905000 2.125000 3.075000 2.295000 ; - RECT 3.365000 2.125000 3.535000 2.295000 ; - RECT 3.825000 2.125000 3.995000 2.295000 ; - RECT 4.285000 2.125000 4.455000 2.295000 ; - RECT 4.745000 2.125000 4.915000 2.295000 ; - RECT 5.205000 2.125000 5.375000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 5.450000 2.340000 ; - RECT 0.085000 2.080000 5.435000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.085000 0.085000 5.430000 0.855000 ; - RECT 0.085000 0.855000 2.665000 1.375000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_decapkapwr_12 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_inputiso0n_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_inputiso0n_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.075000 0.775000 1.325000 ; - RECT 0.100000 1.325000 0.365000 1.685000 ; - END - END A - PIN SLEEP_B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.995000 1.075000 1.335000 1.325000 ; - END - END SLEEP_B - PIN X - ANTENNADIFFAREA 0.657000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.655000 0.255000 2.215000 0.545000 ; - RECT 1.755000 1.915000 2.215000 2.465000 ; - RECT 1.965000 0.545000 2.215000 1.915000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.285000 0.355000 0.615000 0.715000 ; - RECT 0.285000 0.715000 1.675000 0.905000 ; - RECT 0.285000 1.965000 0.565000 2.635000 ; - RECT 0.735000 1.575000 1.675000 1.745000 ; - RECT 0.735000 1.745000 1.035000 2.295000 ; - RECT 1.235000 0.085000 1.485000 0.545000 ; - RECT 1.235000 1.915000 1.565000 2.635000 ; - RECT 1.505000 0.905000 1.675000 0.995000 ; - RECT 1.505000 0.995000 1.795000 1.325000 ; - RECT 1.505000 1.325000 1.675000 1.575000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_inputiso0n_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_inputiso0p_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_inputiso0p_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 1.645000 2.175000 1.955000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.765000 0.445000 1.615000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.350000 1.580000 2.655000 2.365000 ; - RECT 2.415000 0.255000 2.655000 0.775000 ; - RECT 2.480000 0.775000 2.655000 1.580000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.590000 ; - RECT 0.175000 1.785000 0.850000 2.015000 ; - RECT 0.175000 2.015000 0.345000 2.445000 ; - RECT 0.515000 2.185000 0.845000 2.635000 ; - RECT 0.595000 0.280000 0.835000 0.655000 ; - RECT 0.615000 0.655000 0.835000 0.805000 ; - RECT 0.615000 0.805000 1.150000 1.135000 ; - RECT 0.615000 1.135000 0.850000 1.785000 ; - RECT 1.020000 1.305000 2.305000 1.325000 ; - RECT 1.020000 1.325000 1.880000 1.475000 ; - RECT 1.020000 1.475000 1.305000 2.420000 ; - RECT 1.115000 0.270000 1.285000 0.415000 ; - RECT 1.115000 0.415000 1.490000 0.610000 ; - RECT 1.320000 0.610000 1.490000 0.945000 ; - RECT 1.320000 0.945000 2.305000 1.305000 ; - RECT 1.485000 2.165000 2.170000 2.635000 ; - RECT 1.850000 0.085000 2.245000 0.580000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_inputiso0p_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_inputiso1n_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_inputiso1n_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 2.085000 1.735000 2.415000 ; - END - END A - PIN SLEEP_B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.425000 1.325000 ; - END - END SLEEP_B - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 0.415000 2.675000 0.760000 ; - RECT 2.405000 1.495000 2.675000 2.465000 ; - RECT 2.505000 0.760000 2.675000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.110000 0.265000 0.420000 0.735000 ; - RECT 0.110000 0.735000 0.845000 0.905000 ; - RECT 0.590000 0.085000 1.325000 0.565000 ; - RECT 0.595000 0.905000 0.845000 0.995000 ; - RECT 0.595000 0.995000 1.335000 1.325000 ; - RECT 0.595000 1.325000 0.765000 1.885000 ; - RECT 0.990000 1.495000 2.235000 1.665000 ; - RECT 0.990000 1.665000 1.410000 1.915000 ; - RECT 1.495000 0.305000 1.665000 0.655000 ; - RECT 1.495000 0.655000 2.235000 0.825000 ; - RECT 1.835000 0.085000 2.215000 0.485000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - RECT 2.065000 0.825000 2.235000 0.995000 ; - RECT 2.065000 0.995000 2.295000 1.325000 ; - RECT 2.065000 1.325000 2.235000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_inputiso1n_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_inputiso1p_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_inputiso1p_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.765000 0.500000 1.325000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.765000 1.275000 1.325000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 0.509000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.565000 0.255000 2.180000 0.825000 ; - RECT 1.645000 1.845000 2.180000 2.465000 ; - RECT 1.865000 0.825000 2.180000 1.845000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.250000 0.085000 0.490000 0.595000 ; - RECT 0.270000 1.495000 1.695000 1.665000 ; - RECT 0.270000 1.665000 0.660000 1.840000 ; - RECT 0.670000 0.265000 0.950000 0.595000 ; - RECT 0.670000 0.595000 0.840000 1.495000 ; - RECT 1.145000 1.835000 1.475000 2.635000 ; - RECT 1.180000 0.085000 1.395000 0.595000 ; - RECT 1.525000 0.995000 1.695000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_inputiso1p_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_inputisolatch_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_inputisolatch_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.750000 0.765000 2.125000 1.095000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.690000 0.415000 4.975000 0.745000 ; - RECT 4.690000 1.670000 4.975000 2.455000 ; - RECT 4.805000 0.745000 4.975000 1.670000 ; - END - END Q - PIN SLEEP_B - ANTENNAGATEAREA 0.145500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.090000 0.985000 0.330000 1.625000 ; - END - END SLEEP_B - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.780000 0.805000 ; - RECT 0.175000 1.795000 0.780000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.610000 0.805000 0.780000 1.130000 ; - RECT 0.610000 1.130000 0.810000 1.460000 ; - RECT 0.610000 1.460000 0.780000 1.795000 ; - RECT 0.980000 0.740000 1.185000 0.910000 ; - RECT 0.980000 0.910000 1.150000 1.825000 ; - RECT 0.980000 1.825000 1.185000 1.915000 ; - RECT 0.980000 1.915000 2.845000 1.965000 ; - RECT 1.015000 0.345000 1.185000 0.740000 ; - RECT 1.015000 1.965000 2.845000 2.085000 ; - RECT 1.015000 2.085000 1.185000 2.465000 ; - RECT 1.320000 1.240000 1.490000 1.525000 ; - RECT 1.320000 1.525000 2.335000 1.695000 ; - RECT 1.455000 0.085000 1.785000 0.465000 ; - RECT 1.455000 2.255000 1.850000 2.635000 ; - RECT 2.050000 1.355000 2.335000 1.525000 ; - RECT 2.295000 0.705000 2.675000 1.035000 ; - RECT 2.310000 2.255000 3.185000 2.425000 ; - RECT 2.380000 0.365000 3.040000 0.535000 ; - RECT 2.505000 1.035000 2.675000 1.575000 ; - RECT 2.505000 1.575000 2.845000 1.915000 ; - RECT 2.870000 0.535000 3.040000 0.995000 ; - RECT 2.870000 0.995000 3.780000 1.165000 ; - RECT 3.015000 1.165000 3.780000 1.325000 ; - RECT 3.015000 1.325000 3.185000 2.255000 ; - RECT 3.265000 0.085000 3.595000 0.530000 ; - RECT 3.355000 2.135000 3.525000 2.635000 ; - RECT 3.420000 1.535000 4.125000 1.865000 ; - RECT 3.835000 0.415000 4.125000 0.745000 ; - RECT 3.835000 1.865000 4.125000 2.435000 ; - RECT 3.950000 0.745000 4.125000 1.535000 ; - RECT 4.295000 0.085000 4.465000 0.715000 ; - RECT 4.295000 1.570000 4.465000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_inputisolatch_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrc_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrc_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 0.725000 0.325000 1.325000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.960000 1.065000 1.325000 1.325000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 0.435500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.235000 0.255000 1.565000 0.725000 ; - RECT 1.235000 0.725000 2.215000 0.895000 ; - RECT 1.655000 1.850000 2.215000 2.465000 ; - RECT 2.035000 0.895000 2.215000 1.850000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.330000 0.370000 0.675000 0.545000 ; - RECT 0.415000 1.510000 1.705000 1.680000 ; - RECT 0.415000 1.680000 0.675000 1.905000 ; - RECT 0.495000 0.545000 0.675000 1.510000 ; - RECT 0.855000 0.085000 1.065000 0.895000 ; - RECT 0.875000 1.855000 1.205000 2.635000 ; - RECT 1.535000 1.075000 1.865000 1.245000 ; - RECT 1.535000 1.245000 1.705000 1.510000 ; - RECT 1.735000 0.085000 2.120000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrc_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrc_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrc_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.600000 1.065000 3.125000 1.275000 ; - RECT 2.910000 1.275000 3.125000 1.965000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.480000 1.065000 0.920000 1.275000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 0.621000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 1.705000 0.895000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 1.415000 0.895000 1.665000 2.125000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.365000 0.895000 ; - RECT 0.085000 1.445000 1.245000 1.655000 ; - RECT 0.085000 1.655000 0.405000 2.465000 ; - RECT 0.575000 1.825000 0.825000 2.635000 ; - RECT 0.995000 1.655000 1.245000 2.295000 ; - RECT 0.995000 2.295000 2.125000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.835000 1.445000 2.090000 1.890000 ; - RECT 1.835000 1.890000 2.125000 2.295000 ; - RECT 1.875000 0.085000 2.045000 0.895000 ; - RECT 1.875000 1.075000 2.430000 1.245000 ; - RECT 2.215000 0.725000 2.565000 0.895000 ; - RECT 2.215000 0.895000 2.430000 1.075000 ; - RECT 2.260000 1.245000 2.430000 1.445000 ; - RECT 2.260000 1.445000 2.565000 1.615000 ; - RECT 2.395000 0.445000 2.565000 0.725000 ; - RECT 2.395000 1.615000 2.565000 2.460000 ; - RECT 2.775000 0.085000 3.030000 0.845000 ; - RECT 2.775000 2.145000 3.025000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrc_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrc_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrc_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.445000 1.075000 4.975000 1.320000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.360000 1.075000 1.800000 1.275000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 1.242000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 3.385000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 2.295000 0.905000 2.625000 1.445000 ; - RECT 2.295000 1.445000 3.305000 1.745000 ; - RECT 2.295000 1.745000 2.465000 2.125000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 3.135000 1.745000 3.305000 2.125000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.085000 0.365000 0.905000 ; - RECT 0.085000 1.455000 2.125000 1.665000 ; - RECT 0.085000 1.665000 0.365000 2.465000 ; - RECT 0.535000 1.835000 0.865000 2.635000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.035000 1.665000 1.205000 2.465000 ; - RECT 1.375000 1.835000 1.625000 2.635000 ; - RECT 1.795000 1.665000 2.125000 2.295000 ; - RECT 1.795000 2.295000 3.855000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.635000 1.935000 2.965000 2.295000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 2.795000 1.075000 4.275000 1.275000 ; - RECT 3.475000 1.575000 3.855000 2.295000 ; - RECT 3.555000 0.085000 3.845000 0.905000 ; - RECT 4.025000 0.255000 4.355000 0.815000 ; - RECT 4.025000 0.815000 4.275000 1.075000 ; - RECT 4.025000 1.275000 4.275000 1.575000 ; - RECT 4.025000 1.575000 4.355000 2.465000 ; - RECT 4.525000 0.085000 4.815000 0.905000 ; - RECT 4.525000 1.495000 4.930000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrc_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrc_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrc_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.265000 1.065000 ; - RECT 0.085000 1.065000 0.575000 1.285000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.270000 1.075000 8.010000 1.275000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 2.484000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.005000 0.255000 2.335000 0.725000 ; - RECT 2.005000 0.725000 8.655000 0.905000 ; - RECT 2.845000 0.255000 3.175000 0.725000 ; - RECT 3.685000 0.255000 4.015000 0.725000 ; - RECT 4.525000 0.255000 4.855000 0.725000 ; - RECT 5.365000 0.255000 5.695000 0.725000 ; - RECT 5.405000 1.445000 8.655000 1.615000 ; - RECT 5.405000 1.615000 5.655000 2.125000 ; - RECT 6.205000 0.255000 6.535000 0.725000 ; - RECT 6.245000 1.615000 6.495000 2.125000 ; - RECT 7.045000 0.255000 7.375000 0.725000 ; - RECT 7.085000 1.615000 7.335000 2.125000 ; - RECT 7.885000 0.255000 8.215000 0.725000 ; - RECT 7.925000 1.615000 8.175000 2.125000 ; - RECT 8.180000 0.905000 8.655000 1.445000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.195000 1.455000 0.415000 2.635000 ; - RECT 0.435000 0.085000 0.655000 0.895000 ; - RECT 0.585000 1.455000 0.915000 2.465000 ; - RECT 0.745000 1.065000 1.155000 1.075000 ; - RECT 0.745000 1.075000 5.000000 1.285000 ; - RECT 0.745000 1.285000 0.915000 1.455000 ; - RECT 0.825000 0.255000 1.155000 1.065000 ; - RECT 1.085000 1.455000 1.330000 2.635000 ; - RECT 1.325000 0.085000 1.835000 0.905000 ; - RECT 1.555000 1.455000 5.235000 1.665000 ; - RECT 1.555000 1.665000 1.875000 2.465000 ; - RECT 2.045000 1.835000 2.295000 2.635000 ; - RECT 2.465000 1.665000 2.715000 2.465000 ; - RECT 2.505000 0.085000 2.675000 0.555000 ; - RECT 2.885000 1.835000 3.135000 2.635000 ; - RECT 3.305000 1.665000 3.555000 2.465000 ; - RECT 3.345000 0.085000 3.515000 0.555000 ; - RECT 3.725000 1.835000 3.975000 2.635000 ; - RECT 4.145000 1.665000 4.395000 2.465000 ; - RECT 4.185000 0.085000 4.355000 0.555000 ; - RECT 4.565000 1.835000 4.815000 2.635000 ; - RECT 4.985000 1.665000 5.235000 2.295000 ; - RECT 4.985000 2.295000 8.595000 2.465000 ; - RECT 5.025000 0.085000 5.195000 0.555000 ; - RECT 5.825000 1.785000 6.075000 2.295000 ; - RECT 5.865000 0.085000 6.035000 0.555000 ; - RECT 6.665000 1.785000 6.915000 2.295000 ; - RECT 6.705000 0.085000 6.875000 0.555000 ; - RECT 7.505000 1.785000 7.755000 2.295000 ; - RECT 7.545000 0.085000 7.715000 0.555000 ; - RECT 8.345000 1.785000 8.595000 2.295000 ; - RECT 8.385000 0.085000 8.655000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrc_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrc_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrc_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 16.56000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.315000 0.995000 ; - RECT 0.085000 0.995000 0.665000 1.325000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 3.960000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.450000 1.075000 15.650000 1.285000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 4.968000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.925000 0.255000 3.255000 0.725000 ; - RECT 2.925000 0.725000 16.475000 0.905000 ; - RECT 3.765000 0.255000 4.095000 0.725000 ; - RECT 4.605000 0.255000 4.935000 0.725000 ; - RECT 5.445000 0.255000 5.775000 0.725000 ; - RECT 6.285000 0.255000 6.615000 0.725000 ; - RECT 7.125000 0.255000 7.455000 0.725000 ; - RECT 7.965000 0.255000 8.295000 0.725000 ; - RECT 8.805000 0.255000 9.135000 0.725000 ; - RECT 9.645000 0.255000 9.975000 0.725000 ; - RECT 9.685000 1.455000 16.475000 1.625000 ; - RECT 9.685000 1.625000 9.935000 2.125000 ; - RECT 10.485000 0.255000 10.815000 0.725000 ; - RECT 10.525000 1.625000 10.775000 2.125000 ; - RECT 11.325000 0.255000 11.655000 0.725000 ; - RECT 11.365000 1.625000 11.615000 2.125000 ; - RECT 12.165000 0.255000 12.495000 0.725000 ; - RECT 12.205000 1.625000 12.455000 2.125000 ; - RECT 13.005000 0.255000 13.335000 0.725000 ; - RECT 13.045000 1.625000 13.295000 2.125000 ; - RECT 13.845000 0.255000 14.175000 0.725000 ; - RECT 13.885000 1.625000 14.135000 2.125000 ; - RECT 14.685000 0.255000 15.015000 0.725000 ; - RECT 14.725000 1.625000 14.975000 2.125000 ; - RECT 15.525000 0.255000 15.855000 0.725000 ; - RECT 15.565000 1.625000 15.815000 2.125000 ; - RECT 15.820000 0.905000 16.475000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 16.560000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 16.750000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 16.560000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 16.560000 0.085000 ; - RECT 0.000000 2.635000 16.560000 2.805000 ; - RECT 0.300000 1.495000 0.515000 2.635000 ; - RECT 0.485000 0.085000 0.815000 0.825000 ; - RECT 0.685000 1.495000 1.015000 2.465000 ; - RECT 0.835000 1.065000 2.035000 1.075000 ; - RECT 0.835000 1.075000 9.280000 1.285000 ; - RECT 0.835000 1.285000 1.015000 1.495000 ; - RECT 0.985000 0.255000 1.195000 1.065000 ; - RECT 1.185000 1.455000 1.355000 2.635000 ; - RECT 1.365000 0.085000 1.615000 0.895000 ; - RECT 1.525000 1.285000 1.855000 2.465000 ; - RECT 1.785000 0.255000 2.035000 1.065000 ; - RECT 2.025000 1.455000 2.270000 2.635000 ; - RECT 2.205000 0.085000 2.755000 0.905000 ; - RECT 2.475000 1.455000 9.515000 1.665000 ; - RECT 2.475000 1.665000 2.795000 2.465000 ; - RECT 2.965000 1.835000 3.215000 2.635000 ; - RECT 3.385000 1.665000 3.635000 2.465000 ; - RECT 3.425000 0.085000 3.595000 0.555000 ; - RECT 3.805000 1.835000 4.055000 2.635000 ; - RECT 4.225000 1.665000 4.475000 2.465000 ; - RECT 4.265000 0.085000 4.435000 0.555000 ; - RECT 4.645000 1.835000 4.895000 2.635000 ; - RECT 5.065000 1.665000 5.315000 2.465000 ; - RECT 5.105000 0.085000 5.275000 0.555000 ; - RECT 5.485000 1.835000 5.735000 2.635000 ; - RECT 5.905000 1.665000 6.155000 2.465000 ; - RECT 5.945000 0.085000 6.115000 0.555000 ; - RECT 6.325000 1.835000 6.575000 2.635000 ; - RECT 6.745000 1.665000 6.995000 2.465000 ; - RECT 6.785000 0.085000 6.955000 0.555000 ; - RECT 7.165000 1.835000 7.415000 2.635000 ; - RECT 7.585000 1.665000 7.835000 2.465000 ; - RECT 7.625000 0.085000 7.795000 0.555000 ; - RECT 8.005000 1.835000 8.255000 2.635000 ; - RECT 8.425000 1.665000 8.675000 2.465000 ; - RECT 8.465000 0.085000 8.635000 0.555000 ; - RECT 8.845000 1.835000 9.095000 2.635000 ; - RECT 9.265000 1.665000 9.515000 2.295000 ; - RECT 9.265000 2.295000 16.235000 2.465000 ; - RECT 9.305000 0.085000 9.475000 0.555000 ; - RECT 10.105000 1.795000 10.355000 2.295000 ; - RECT 10.145000 0.085000 10.315000 0.555000 ; - RECT 10.945000 1.795000 11.195000 2.295000 ; - RECT 10.985000 0.085000 11.155000 0.555000 ; - RECT 11.785000 1.795000 12.035000 2.295000 ; - RECT 11.825000 0.085000 11.995000 0.555000 ; - RECT 12.625000 1.795000 12.875000 2.295000 ; - RECT 12.665000 0.085000 12.835000 0.555000 ; - RECT 13.465000 1.795000 13.715000 2.295000 ; - RECT 13.505000 0.085000 13.675000 0.555000 ; - RECT 14.305000 1.795000 14.555000 2.295000 ; - RECT 14.345000 0.085000 14.515000 0.555000 ; - RECT 15.145000 1.795000 15.395000 2.295000 ; - RECT 15.185000 0.085000 15.355000 0.555000 ; - RECT 15.985000 1.795000 16.235000 2.295000 ; - RECT 16.025000 0.085000 16.295000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - RECT 14.405000 -0.085000 14.575000 0.085000 ; - RECT 14.405000 2.635000 14.575000 2.805000 ; - RECT 14.865000 -0.085000 15.035000 0.085000 ; - RECT 14.865000 2.635000 15.035000 2.805000 ; - RECT 15.325000 -0.085000 15.495000 0.085000 ; - RECT 15.325000 2.635000 15.495000 2.805000 ; - RECT 15.785000 -0.085000 15.955000 0.085000 ; - RECT 15.785000 2.635000 15.955000 2.805000 ; - RECT 16.245000 -0.085000 16.415000 0.085000 ; - RECT 16.245000 2.635000 16.415000 2.805000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrc_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.26000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.615000 1.320000 ; - END - END A - PIN SLEEP - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.260000 1.075000 4.700000 1.275000 ; - END - END SLEEP - PIN X - ANTENNADIFFAREA 3.180800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.340000 0.280000 7.600000 0.735000 ; - RECT 7.340000 0.735000 14.085000 0.905000 ; - RECT 7.375000 1.495000 14.085000 1.720000 ; - RECT 7.375000 1.720000 12.745000 1.735000 ; - RECT 7.375000 1.735000 7.600000 2.460000 ; - RECT 8.200000 0.280000 8.460000 0.735000 ; - RECT 8.200000 1.735000 8.460000 2.460000 ; - RECT 9.060000 0.280000 9.320000 0.735000 ; - RECT 9.060000 1.735000 9.320000 2.460000 ; - RECT 9.905000 0.280000 10.180000 0.735000 ; - RECT 9.920000 1.735000 10.180000 2.460000 ; - RECT 10.765000 0.280000 11.025000 0.735000 ; - RECT 10.765000 1.735000 11.025000 2.460000 ; - RECT 11.625000 0.280000 11.885000 0.735000 ; - RECT 11.625000 1.735000 11.885000 2.460000 ; - RECT 12.485000 0.280000 12.745000 0.735000 ; - RECT 12.485000 1.735000 12.745000 2.460000 ; - RECT 12.920000 0.905000 14.085000 1.495000 ; - RECT 13.355000 0.280000 13.615000 0.735000 ; - RECT 13.355000 1.720000 13.645000 2.460000 ; - END - END X - PIN KAPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 10.350000 1.905000 10.595000 2.465000 ; - LAYER mcon ; - RECT 10.395000 2.125000 10.565000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 11.210000 1.905000 11.455000 2.465000 ; - LAYER mcon ; - RECT 11.255000 2.125000 11.425000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 12.070000 1.905000 12.315000 2.465000 ; - LAYER mcon ; - RECT 12.110000 2.125000 12.280000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 12.930000 1.905000 13.185000 2.465000 ; - LAYER mcon ; - RECT 12.960000 2.125000 13.130000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 13.815000 1.890000 14.085000 2.465000 ; - LAYER mcon ; - RECT 13.840000 2.125000 14.010000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 5.155000 1.495000 5.485000 2.465000 ; - LAYER mcon ; - RECT 5.235000 2.125000 5.405000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 6.015000 1.495000 6.345000 2.465000 ; - LAYER mcon ; - RECT 6.095000 2.125000 6.265000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 6.875000 1.495000 7.205000 2.465000 ; - LAYER mcon ; - RECT 6.950000 2.125000 7.120000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 7.770000 1.905000 8.030000 2.465000 ; - LAYER mcon ; - RECT 7.800000 2.125000 7.970000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 8.630000 1.905000 8.890000 2.465000 ; - LAYER mcon ; - RECT 8.680000 2.125000 8.850000 2.295000 ; - END - PORT - LAYER li1 ; - RECT 9.490000 1.905000 9.750000 2.465000 ; - LAYER mcon ; - RECT 9.540000 2.125000 9.710000 2.295000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 14.190000 2.340000 ; - RECT 5.175000 2.080000 5.465000 2.140000 ; - RECT 6.035000 2.080000 6.325000 2.140000 ; - RECT 6.890000 2.080000 7.180000 2.140000 ; - RECT 7.740000 2.080000 8.030000 2.140000 ; - RECT 8.620000 2.080000 8.910000 2.140000 ; - RECT 9.480000 2.080000 9.770000 2.140000 ; - RECT 10.335000 2.080000 10.625000 2.140000 ; - RECT 11.195000 2.080000 11.485000 2.140000 ; - RECT 12.050000 2.080000 12.340000 2.140000 ; - RECT 12.900000 2.080000 13.190000 2.140000 ; - RECT 13.780000 2.080000 14.070000 2.140000 ; - END - END KAPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.260000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - PORT - LAYER pwell ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 14.450000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.260000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.260000 0.085000 ; - RECT 0.000000 2.635000 14.260000 2.805000 ; - RECT 0.130000 1.495000 0.535000 2.635000 ; - RECT 0.245000 0.085000 0.535000 0.905000 ; - RECT 0.705000 0.255000 1.035000 0.815000 ; - RECT 0.705000 1.575000 1.035000 2.465000 ; - RECT 0.785000 0.815000 1.035000 1.075000 ; - RECT 0.785000 1.075000 2.265000 1.275000 ; - RECT 0.785000 1.275000 1.035000 1.575000 ; - RECT 1.205000 1.575000 1.585000 2.295000 ; - RECT 1.205000 2.295000 3.265000 2.465000 ; - RECT 1.215000 0.085000 1.505000 0.905000 ; - RECT 1.675000 0.255000 2.005000 0.725000 ; - RECT 1.675000 0.725000 4.525000 0.905000 ; - RECT 1.755000 1.445000 2.765000 1.745000 ; - RECT 1.755000 1.745000 1.925000 2.125000 ; - RECT 2.095000 1.935000 2.425000 2.295000 ; - RECT 2.175000 0.085000 2.345000 0.555000 ; - RECT 2.435000 0.905000 3.095000 0.965000 ; - RECT 2.435000 0.965000 2.765000 1.445000 ; - RECT 2.515000 0.255000 2.845000 0.725000 ; - RECT 2.595000 1.745000 2.765000 2.125000 ; - RECT 2.935000 1.455000 4.975000 1.665000 ; - RECT 2.935000 1.665000 3.265000 2.295000 ; - RECT 3.015000 0.085000 3.185000 0.555000 ; - RECT 3.355000 0.255000 3.685000 0.725000 ; - RECT 3.435000 1.835000 3.685000 2.635000 ; - RECT 3.855000 0.085000 4.025000 0.555000 ; - RECT 3.855000 1.665000 4.025000 2.465000 ; - RECT 4.195000 0.255000 4.525000 0.725000 ; - RECT 4.195000 1.835000 4.525000 2.635000 ; - RECT 4.695000 0.085000 5.450000 0.565000 ; - RECT 4.695000 0.565000 4.975000 0.905000 ; - RECT 4.695000 1.665000 4.975000 2.465000 ; - RECT 5.145000 0.735000 5.460000 1.325000 ; - RECT 5.655000 0.265000 5.880000 1.075000 ; - RECT 5.655000 1.075000 12.750000 1.325000 ; - RECT 5.655000 1.325000 5.845000 2.465000 ; - RECT 6.050000 0.085000 6.310000 0.610000 ; - RECT 6.490000 0.265000 6.740000 1.075000 ; - RECT 6.515000 1.325000 6.705000 2.460000 ; - RECT 6.910000 0.085000 7.170000 0.645000 ; - RECT 7.770000 0.085000 8.030000 0.565000 ; - RECT 8.630000 0.085000 8.890000 0.565000 ; - RECT 9.490000 0.085000 9.735000 0.565000 ; - RECT 10.350000 0.085000 10.595000 0.565000 ; - RECT 11.205000 0.085000 11.455000 0.565000 ; - RECT 12.065000 0.085000 12.315000 0.565000 ; - RECT 12.925000 0.085000 13.185000 0.565000 ; - RECT 13.785000 0.085000 14.085000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.525000 0.765000 2.695000 0.935000 ; - RECT 2.885000 0.765000 3.055000 0.935000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.210000 0.765000 5.380000 0.935000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - LAYER met1 ; - RECT 2.465000 0.735000 3.115000 0.780000 ; - RECT 2.465000 0.780000 5.440000 0.920000 ; - RECT 2.465000 0.920000 3.115000 0.965000 ; - RECT 5.150000 0.735000 5.440000 0.780000 ; - RECT 5.150000 0.920000 5.440000 0.965000 ; - END -END sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.402500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.290000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 2.370000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 6.440000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 5.925000 4.595000 6.095000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 6.170000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 5.870000 3.455000 6.160000 3.500000 ; - RECT 5.870000 3.640000 6.160000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 6.630000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - PIN VPWRIN - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 6.170000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END VPWRIN - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 6.440000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.290000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.290000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 6.440000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.865000 0.085000 6.155000 0.810000 ; - RECT 5.865000 2.985000 6.155000 3.955000 ; - RECT 5.865000 4.630000 6.155000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 5.930000 3.485000 6.100000 3.655000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - RECT 5.925000 0.320000 6.095000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.610500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.255000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 2.370000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 6.440000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 6.125000 4.595000 6.295000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 6.300000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 6.010000 3.455000 6.300000 3.500000 ; - RECT 6.010000 3.640000 6.300000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 6.630000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - PIN VPWRIN - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 6.370000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END VPWRIN - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 6.440000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.255000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.255000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 6.440000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.825000 0.085000 6.155000 0.900000 ; - RECT 5.905000 1.610000 6.075000 2.635000 ; - RECT 6.065000 2.985000 6.355000 3.955000 ; - RECT 6.065000 4.630000 6.355000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 6.070000 3.485000 6.240000 3.655000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.072500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.255000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 1.085000 ; - RECT 5.360000 1.085000 6.555000 1.410000 ; - RECT 5.360000 1.410000 5.635000 2.370000 ; - RECT 6.280000 1.410000 6.555000 2.370000 ; - RECT 6.335000 0.255000 6.555000 1.085000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 7.360000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 7.045000 4.595000 7.215000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 7.290000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 6.930000 3.455000 7.220000 3.500000 ; - RECT 6.930000 3.640000 7.220000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 7.405000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - PIN VPWRIN - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 7.290000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END VPWRIN - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 7.360000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.255000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.255000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 7.360000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.825000 0.085000 6.155000 0.845000 ; - RECT 5.905000 1.610000 6.075000 2.635000 ; - RECT 6.755000 0.085000 7.005000 0.925000 ; - RECT 6.755000 1.610000 6.935000 2.635000 ; - RECT 6.985000 2.985000 7.275000 3.955000 ; - RECT 6.985000 4.630000 7.275000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.585000 5.355000 6.755000 5.525000 ; - RECT 6.990000 3.485000 7.160000 3.655000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.045000 5.355000 7.215000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.072500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.255000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 1.085000 ; - RECT 5.360000 1.085000 6.555000 1.410000 ; - RECT 5.360000 1.410000 5.635000 2.370000 ; - RECT 6.280000 1.410000 6.555000 2.370000 ; - RECT 6.335000 0.255000 6.555000 1.085000 ; - END - END X - PIN LOWLVPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 7.290000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END LOWLVPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 7.360000 5.680000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.075000 5.245000 0.200000 5.395000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT 4.250000 1.305000 7.405000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 7.360000 5.525000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.255000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.255000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 7.360000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.825000 0.085000 6.155000 0.845000 ; - RECT 5.905000 1.610000 6.075000 2.635000 ; - RECT 6.755000 0.085000 7.005000 0.925000 ; - RECT 6.755000 1.610000 6.935000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.585000 5.355000 6.755000 5.525000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.045000 5.355000 7.215000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.402500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.290000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 2.370000 ; - END - END X - PIN LOWLVPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 6.170000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END LOWLVPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 6.440000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 5.925000 4.595000 6.095000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 6.170000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 5.870000 3.455000 6.160000 3.500000 ; - RECT 5.870000 3.640000 6.160000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 6.630000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 6.440000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.290000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.290000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 6.440000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.865000 0.085000 6.155000 0.810000 ; - RECT 5.865000 2.985000 6.155000 3.955000 ; - RECT 5.865000 4.630000 6.155000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 5.930000 3.485000 6.100000 3.655000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - RECT 5.925000 0.320000 6.095000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 0.610500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.255000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 2.370000 ; - END - END X - PIN LOWLVPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 6.370000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END LOWLVPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 6.440000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 6.125000 4.595000 6.295000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 6.300000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 6.010000 3.455000 6.300000 3.500000 ; - RECT 6.010000 3.640000 6.300000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 6.630000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 6.440000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.255000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.255000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 6.440000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.825000 0.085000 6.155000 0.900000 ; - RECT 5.905000 1.610000 6.075000 2.635000 ; - RECT 6.065000 2.985000 6.355000 3.955000 ; - RECT 6.065000 4.630000 6.355000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 6.070000 3.485000 6.240000 3.655000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 5.440000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.603000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.070000 3.290000 1.540000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.072500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.335000 0.255000 5.635000 0.980000 ; - RECT 5.360000 0.980000 5.635000 1.085000 ; - RECT 5.360000 1.085000 6.555000 1.410000 ; - RECT 5.360000 1.410000 5.635000 2.370000 ; - RECT 6.280000 1.410000 6.555000 2.370000 ; - RECT 6.335000 0.255000 6.555000 1.085000 ; - END - END X - PIN LOWLVPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 1.380000 2.065000 2.390000 2.335000 ; - RECT 2.060000 1.635000 2.390000 2.065000 ; - RECT 2.060000 2.335000 2.390000 2.660000 ; - RECT 2.060000 2.660000 2.810000 3.750000 ; - LAYER mcon ; - RECT 1.420000 2.115000 1.590000 2.285000 ; - RECT 1.780000 2.115000 1.950000 2.285000 ; - RECT 2.140000 2.115000 2.310000 2.285000 ; - END - PORT - LAYER met1 ; - RECT 0.070000 2.140000 7.290000 2.280000 ; - RECT 1.360000 2.085000 2.370000 2.140000 ; - RECT 1.360000 2.280000 2.370000 2.315000 ; - LAYER nwell ; - RECT 1.920000 1.305000 2.980000 4.135000 ; - END - END LOWLVPWR - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 5.200000 7.360000 5.680000 ; - LAYER pwell ; - RECT 0.145000 4.595000 0.315000 5.120000 ; - RECT 7.045000 4.595000 7.215000 5.120000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.070000 3.500000 7.290000 3.640000 ; - RECT 0.080000 3.455000 0.370000 3.500000 ; - RECT 0.080000 3.640000 0.370000 3.685000 ; - RECT 6.930000 3.455000 7.220000 3.500000 ; - RECT 6.930000 3.640000 7.220000 3.685000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 4.135000 ; - RECT 4.250000 1.305000 7.405000 4.135000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 1.890000 2.805000 ; - RECT 0.000000 5.355000 7.360000 5.525000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 2.985000 0.375000 3.970000 ; - RECT 0.085000 4.630000 0.375000 5.355000 ; - RECT 2.020000 0.085000 2.350000 0.895000 ; - RECT 2.560000 0.375000 2.800000 2.130000 ; - RECT 2.560000 2.130000 3.390000 2.370000 ; - RECT 2.645000 4.515000 2.905000 5.355000 ; - RECT 3.060000 2.370000 3.390000 3.965000 ; - RECT 3.075000 4.265000 4.265000 4.325000 ; - RECT 3.075000 4.325000 3.405000 5.185000 ; - RECT 3.115000 0.085000 3.445000 0.900000 ; - RECT 3.145000 4.155000 4.195000 4.265000 ; - RECT 3.575000 4.515000 3.765000 5.355000 ; - RECT 3.615000 0.255000 3.805000 0.730000 ; - RECT 3.615000 0.730000 4.665000 0.980000 ; - RECT 3.680000 2.405000 4.190000 2.575000 ; - RECT 3.680000 2.575000 3.850000 3.470000 ; - RECT 3.680000 3.470000 4.720000 3.640000 ; - RECT 3.935000 4.325000 4.265000 5.185000 ; - RECT 3.975000 0.085000 4.305000 0.560000 ; - RECT 4.020000 0.980000 4.190000 2.405000 ; - RECT 4.020000 2.745000 4.640000 2.915000 ; - RECT 4.020000 2.915000 4.190000 3.300000 ; - RECT 4.020000 3.810000 4.190000 4.155000 ; - RECT 4.390000 3.085000 4.720000 3.470000 ; - RECT 4.410000 3.640000 4.720000 3.740000 ; - RECT 4.445000 4.515000 4.955000 5.355000 ; - RECT 4.470000 1.625000 4.640000 2.745000 ; - RECT 4.475000 0.255000 4.665000 0.730000 ; - RECT 4.835000 0.085000 5.165000 0.900000 ; - RECT 4.890000 1.625000 5.120000 2.635000 ; - RECT 4.890000 2.635000 7.360000 2.805000 ; - RECT 4.890000 2.805000 5.120000 3.740000 ; - RECT 5.135000 4.405000 5.765000 4.460000 ; - RECT 5.135000 4.460000 5.695000 4.820000 ; - RECT 5.135000 4.820000 5.485000 5.160000 ; - RECT 5.360000 3.070000 5.550000 4.125000 ; - RECT 5.360000 4.125000 6.085000 4.355000 ; - RECT 5.360000 4.355000 5.765000 4.405000 ; - RECT 5.825000 0.085000 6.155000 0.845000 ; - RECT 5.905000 1.610000 6.075000 2.635000 ; - RECT 6.755000 0.085000 7.005000 0.925000 ; - RECT 6.755000 1.610000 6.935000 2.635000 ; - RECT 6.985000 2.985000 7.275000 3.955000 ; - RECT 6.985000 4.630000 7.275000 5.355000 ; - LAYER mcon ; - RECT 0.140000 3.485000 0.310000 3.655000 ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.145000 5.355000 0.315000 5.525000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.605000 5.355000 0.775000 5.525000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.065000 5.355000 1.235000 5.525000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.525000 5.355000 1.695000 5.525000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 5.355000 2.155000 5.525000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 5.355000 2.615000 5.525000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 5.355000 3.075000 5.525000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 5.355000 3.535000 5.525000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 5.355000 3.995000 5.525000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 5.355000 4.455000 5.525000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 5.355000 4.915000 5.525000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.205000 5.355000 5.375000 5.525000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.665000 5.355000 5.835000 5.525000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.125000 5.355000 6.295000 5.525000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.585000 5.355000 6.755000 5.525000 ; - RECT 6.990000 3.485000 7.160000 3.655000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.045000 5.355000 7.215000 5.525000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END -END sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__macro_sparecell - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__macro_sparecell ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.34000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN LO - ANTENNAGATEAREA 1.980000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.215000 1.075000 4.965000 1.325000 ; - LAYER mcon ; - RECT 4.775000 1.105000 4.945000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.135000 1.075000 5.895000 1.325000 ; - LAYER mcon ; - RECT 5.705000 1.105000 5.875000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 6.755000 0.915000 7.275000 2.465000 ; - LAYER mcon ; - RECT 6.765000 1.105000 6.935000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 7.445000 1.075000 8.205000 1.325000 ; - LAYER mcon ; - RECT 7.625000 1.105000 7.795000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 8.375000 1.075000 9.125000 1.325000 ; - LAYER mcon ; - RECT 8.485000 1.105000 8.655000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 4.715000 1.075000 5.005000 1.120000 ; - RECT 4.715000 1.120000 8.715000 1.260000 ; - RECT 4.715000 1.260000 5.005000 1.305000 ; - RECT 5.645000 1.075000 5.935000 1.120000 ; - RECT 5.645000 1.260000 5.935000 1.305000 ; - RECT 6.705000 1.075000 6.995000 1.120000 ; - RECT 6.705000 1.260000 6.995000 1.305000 ; - RECT 7.565000 1.075000 7.855000 1.120000 ; - RECT 7.565000 1.260000 7.855000 1.305000 ; - RECT 8.425000 1.075000 8.715000 1.120000 ; - RECT 8.425000 1.260000 8.715000 1.305000 ; - END - END LO - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 0.000000 -0.085000 13.340000 0.085000 ; - RECT 0.145000 0.085000 0.355000 0.905000 ; - RECT 1.025000 0.085000 1.255000 0.905000 ; - RECT 1.515000 0.085000 1.805000 0.555000 ; - RECT 2.475000 0.085000 2.645000 0.555000 ; - RECT 3.315000 0.085000 3.590000 0.905000 ; - RECT 5.215000 0.085000 5.385000 0.545000 ; - RECT 6.755000 0.085000 7.095000 0.745000 ; - RECT 7.955000 0.085000 8.125000 0.545000 ; - RECT 9.750000 0.085000 10.025000 0.905000 ; - RECT 10.695000 0.085000 10.865000 0.555000 ; - RECT 11.535000 0.085000 11.825000 0.555000 ; - RECT 12.085000 0.085000 12.315000 0.905000 ; - RECT 12.985000 0.085000 13.195000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.340000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 13.530000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000000 2.635000 13.340000 2.805000 ; - RECT 0.145000 1.495000 0.355000 2.635000 ; - RECT 1.025000 1.495000 1.255000 2.635000 ; - RECT 2.815000 1.835000 3.145000 2.635000 ; - RECT 3.870000 1.835000 4.125000 2.635000 ; - RECT 4.795000 1.835000 4.965000 2.635000 ; - RECT 5.635000 1.495000 5.895000 2.635000 ; - RECT 6.255000 1.910000 6.585000 2.635000 ; - RECT 7.445000 1.495000 7.705000 2.635000 ; - RECT 8.375000 1.835000 8.545000 2.635000 ; - RECT 9.215000 1.835000 9.470000 2.635000 ; - RECT 10.195000 1.835000 10.525000 2.635000 ; - RECT 12.085000 1.495000 12.315000 2.635000 ; - RECT 12.985000 1.495000 13.195000 2.635000 ; - LAYER mcon ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.340000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.525000 0.255000 0.855000 0.885000 ; - RECT 0.525000 0.885000 0.775000 1.485000 ; - RECT 0.525000 1.485000 0.855000 2.465000 ; - RECT 0.945000 1.075000 1.275000 1.325000 ; - RECT 1.505000 1.835000 1.805000 2.295000 ; - RECT 1.505000 2.295000 2.645000 2.465000 ; - RECT 1.545000 0.735000 3.145000 0.905000 ; - RECT 1.545000 0.905000 1.760000 1.445000 ; - RECT 1.545000 1.445000 2.305000 1.665000 ; - RECT 1.930000 1.075000 2.700000 1.275000 ; - RECT 1.975000 0.255000 2.305000 0.725000 ; - RECT 1.975000 0.725000 3.145000 0.735000 ; - RECT 1.975000 1.665000 2.305000 2.125000 ; - RECT 2.475000 1.455000 3.590000 1.665000 ; - RECT 2.475000 1.665000 2.645000 2.295000 ; - RECT 2.815000 0.255000 3.145000 0.725000 ; - RECT 2.870000 1.075000 3.590000 1.275000 ; - RECT 3.315000 1.665000 3.590000 2.465000 ; - RECT 3.765000 0.655000 4.625000 0.905000 ; - RECT 3.765000 0.905000 4.045000 1.495000 ; - RECT 3.765000 1.495000 5.465000 1.665000 ; - RECT 3.875000 0.255000 5.045000 0.465000 ; - RECT 3.875000 0.465000 4.205000 0.485000 ; - RECT 4.295000 1.665000 4.625000 2.465000 ; - RECT 4.795000 0.465000 5.045000 0.715000 ; - RECT 4.795000 0.715000 5.895000 0.885000 ; - RECT 5.135000 1.665000 5.465000 2.465000 ; - RECT 5.555000 0.255000 5.895000 0.715000 ; - RECT 6.065000 0.255000 6.585000 1.740000 ; - RECT 7.445000 0.255000 7.785000 0.715000 ; - RECT 7.445000 0.715000 8.545000 0.885000 ; - RECT 7.875000 1.495000 9.575000 1.665000 ; - RECT 7.875000 1.665000 8.205000 2.465000 ; - RECT 8.295000 0.255000 9.465000 0.465000 ; - RECT 8.295000 0.465000 8.545000 0.715000 ; - RECT 8.715000 0.655000 9.575000 0.905000 ; - RECT 8.715000 1.665000 9.045000 2.465000 ; - RECT 9.135000 0.465000 9.465000 0.485000 ; - RECT 9.295000 0.905000 9.575000 1.495000 ; - RECT 9.750000 1.075000 10.470000 1.275000 ; - RECT 9.750000 1.455000 10.865000 1.665000 ; - RECT 9.750000 1.665000 10.025000 2.465000 ; - RECT 10.195000 0.255000 10.525000 0.725000 ; - RECT 10.195000 0.725000 11.365000 0.735000 ; - RECT 10.195000 0.735000 11.795000 0.905000 ; - RECT 10.640000 1.075000 11.410000 1.275000 ; - RECT 10.695000 1.665000 10.865000 2.295000 ; - RECT 10.695000 2.295000 11.835000 2.465000 ; - RECT 11.035000 0.255000 11.365000 0.725000 ; - RECT 11.035000 1.445000 11.795000 1.665000 ; - RECT 11.035000 1.665000 11.365000 2.125000 ; - RECT 11.535000 1.835000 11.835000 2.295000 ; - RECT 11.580000 0.905000 11.795000 1.445000 ; - RECT 12.065000 1.075000 12.395000 1.325000 ; - RECT 12.485000 0.255000 12.815000 0.885000 ; - RECT 12.485000 1.485000 12.815000 2.465000 ; - RECT 12.565000 0.885000 12.815000 1.485000 ; - LAYER mcon ; - RECT 0.565000 1.105000 0.735000 1.275000 ; - RECT 1.085000 1.105000 1.255000 1.275000 ; - RECT 1.570000 1.105000 1.740000 1.275000 ; - RECT 2.100000 1.105000 2.270000 1.275000 ; - RECT 2.960000 1.105000 3.130000 1.275000 ; - RECT 3.820000 1.105000 3.990000 1.275000 ; - RECT 9.345000 1.105000 9.515000 1.275000 ; - RECT 10.205000 1.105000 10.375000 1.275000 ; - RECT 11.065000 1.105000 11.235000 1.275000 ; - RECT 11.605000 1.105000 11.775000 1.275000 ; - RECT 12.090000 1.105000 12.260000 1.275000 ; - RECT 12.605000 1.105000 12.775000 1.275000 ; - LAYER met1 ; - RECT 0.505000 1.075000 0.875000 1.305000 ; - RECT 1.025000 1.075000 1.315000 1.120000 ; - RECT 1.025000 1.120000 1.800000 1.260000 ; - RECT 1.025000 1.260000 1.315000 1.305000 ; - RECT 1.510000 1.075000 1.800000 1.120000 ; - RECT 1.510000 1.260000 1.800000 1.305000 ; - RECT 2.040000 1.075000 2.330000 1.120000 ; - RECT 2.040000 1.120000 4.050000 1.260000 ; - RECT 2.040000 1.260000 2.330000 1.305000 ; - RECT 2.900000 1.075000 3.190000 1.120000 ; - RECT 2.900000 1.260000 3.190000 1.305000 ; - RECT 3.760000 1.075000 4.050000 1.120000 ; - RECT 3.760000 1.260000 4.050000 1.305000 ; - RECT 9.285000 1.075000 9.575000 1.120000 ; - RECT 9.285000 1.120000 11.295000 1.260000 ; - RECT 9.285000 1.260000 9.575000 1.305000 ; - RECT 10.145000 1.075000 10.435000 1.120000 ; - RECT 10.145000 1.260000 10.435000 1.305000 ; - RECT 11.005000 1.075000 11.295000 1.120000 ; - RECT 11.005000 1.260000 11.295000 1.305000 ; - RECT 11.545000 1.075000 11.835000 1.120000 ; - RECT 11.545000 1.120000 12.320000 1.260000 ; - RECT 11.545000 1.260000 11.835000 1.305000 ; - RECT 12.030000 1.075000 12.320000 1.120000 ; - RECT 12.030000 1.260000 12.320000 1.305000 ; - RECT 12.470000 1.075000 12.835000 1.305000 ; - LAYER pwell ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 3.360000 -0.085000 3.530000 0.085000 ; - RECT 5.660000 -0.085000 5.830000 0.085000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 7.510000 -0.085000 7.680000 0.085000 ; - RECT 9.810000 -0.085000 9.980000 0.085000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - END -END sky130_fd_sc_hd__macro_sparecell -#--------EOF--------- - -MACRO sky130_fd_sc_hd__maj3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__maj3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 0.995000 1.125000 1.325000 ; - RECT 0.610000 1.325000 0.780000 2.460000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.500000 0.995000 1.905000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.415000 0.765000 2.755000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.602250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.255000 0.255000 3.595000 0.825000 ; - RECT 3.255000 2.160000 3.595000 2.465000 ; - RECT 3.265000 1.495000 3.595000 2.160000 ; - RECT 3.370000 0.825000 3.595000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.135000 0.255000 0.395000 0.655000 ; - RECT 0.135000 0.655000 2.245000 0.825000 ; - RECT 0.135000 0.825000 0.395000 2.125000 ; - RECT 0.875000 0.085000 1.205000 0.485000 ; - RECT 0.955000 1.715000 1.205000 2.635000 ; - RECT 1.655000 0.255000 1.985000 0.640000 ; - RECT 1.655000 0.640000 2.245000 0.655000 ; - RECT 1.655000 1.815000 2.245000 2.080000 ; - RECT 2.075000 0.825000 2.245000 1.495000 ; - RECT 2.075000 1.495000 3.095000 1.665000 ; - RECT 2.075000 1.665000 2.245000 1.815000 ; - RECT 2.545000 0.085000 2.880000 0.470000 ; - RECT 2.555000 1.845000 2.885000 2.635000 ; - RECT 2.925000 0.995000 3.200000 1.325000 ; - RECT 2.925000 1.325000 3.095000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__maj3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__maj3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__maj3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.005000 0.995000 1.695000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.865000 0.995000 2.155000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.495000 ; - RECT 0.425000 1.495000 3.070000 1.665000 ; - RECT 2.415000 1.415000 3.070000 1.495000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.285000 0.255000 3.615000 0.905000 ; - RECT 3.285000 1.495000 3.615000 2.465000 ; - RECT 3.445000 0.905000 3.615000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.280000 0.525000 0.655000 ; - RECT 0.085000 0.655000 3.105000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.835000 ; - RECT 0.085000 1.835000 2.085000 2.005000 ; - RECT 0.085000 2.005000 0.615000 2.465000 ; - RECT 0.975000 0.085000 1.305000 0.485000 ; - RECT 0.975000 2.175000 1.305000 2.635000 ; - RECT 1.755000 0.255000 2.085000 0.655000 ; - RECT 1.755000 2.005000 2.085000 2.465000 ; - RECT 2.535000 1.835000 2.860000 2.635000 ; - RECT 2.635000 0.085000 2.965000 0.485000 ; - RECT 2.925000 0.825000 3.105000 1.075000 ; - RECT 2.925000 1.075000 3.275000 1.245000 ; - RECT 3.785000 0.085000 4.055000 0.905000 ; - RECT 3.785000 1.495000 4.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__maj3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__maj3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__maj3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.060000 1.075000 1.450000 1.635000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.960000 1.075000 2.290000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 1.075000 0.890000 1.285000 ; - RECT 0.720000 1.285000 0.890000 1.915000 ; - RECT 0.720000 1.915000 1.790000 2.085000 ; - RECT 1.620000 2.085000 1.790000 2.225000 ; - RECT 1.620000 2.225000 2.630000 2.395000 ; - RECT 2.460000 1.075000 2.945000 1.245000 ; - RECT 2.460000 1.245000 2.630000 2.225000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.375000 0.255000 3.705000 0.490000 ; - RECT 3.375000 1.455000 4.975000 1.625000 ; - RECT 3.375000 1.625000 3.705000 2.465000 ; - RECT 3.455000 0.490000 3.705000 0.715000 ; - RECT 3.455000 0.715000 4.975000 0.905000 ; - RECT 4.215000 0.255000 4.545000 0.715000 ; - RECT 4.215000 1.625000 4.545000 2.465000 ; - RECT 4.715000 0.905000 4.975000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.255000 0.635000 0.660000 ; - RECT 0.085000 0.660000 2.290000 0.715000 ; - RECT 0.085000 0.715000 3.285000 0.885000 ; - RECT 0.085000 0.885000 0.255000 1.455000 ; - RECT 0.085000 1.455000 0.465000 2.465000 ; - RECT 1.120000 0.085000 1.450000 0.490000 ; - RECT 1.120000 2.255000 1.450000 2.635000 ; - RECT 1.620000 0.885000 1.790000 1.545000 ; - RECT 1.620000 1.545000 2.290000 1.745000 ; - RECT 1.960000 0.255000 2.290000 0.660000 ; - RECT 1.960000 1.745000 2.290000 2.055000 ; - RECT 2.845000 1.455000 3.175000 2.635000 ; - RECT 2.860000 0.085000 3.205000 0.545000 ; - RECT 3.115000 0.885000 3.285000 1.075000 ; - RECT 3.115000 1.075000 4.545000 1.285000 ; - RECT 3.875000 0.085000 4.045000 0.545000 ; - RECT 3.875000 1.795000 4.045000 2.635000 ; - RECT 4.715000 0.085000 4.885000 0.545000 ; - RECT 4.715000 1.795000 4.925000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__maj3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 0.255000 2.265000 1.415000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.615000 0.815000 1.785000 1.615000 ; - RECT 1.615000 1.615000 2.625000 1.785000 ; - RECT 2.435000 0.255000 2.625000 1.615000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.910000 0.995000 1.105000 1.325000 ; - RECT 0.935000 1.325000 1.105000 2.295000 ; - RECT 0.935000 2.295000 2.965000 2.465000 ; - RECT 2.795000 1.440000 3.545000 1.630000 ; - RECT 2.795000 1.630000 2.965000 2.295000 ; - END - END S - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.255000 0.345000 0.825000 ; - RECT 0.090000 0.825000 0.260000 1.495000 ; - RECT 0.090000 1.495000 0.425000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.420000 -0.085000 0.590000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.430000 0.995000 0.685000 1.325000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 0.515000 0.655000 1.445000 0.825000 ; - RECT 0.515000 0.825000 0.685000 0.995000 ; - RECT 0.595000 1.495000 0.765000 2.635000 ; - RECT 1.270000 0.255000 1.800000 0.620000 ; - RECT 1.270000 0.620000 1.445000 0.655000 ; - RECT 1.275000 0.825000 1.445000 1.955000 ; - RECT 1.275000 1.955000 2.400000 2.125000 ; - RECT 2.805000 0.085000 3.315000 0.620000 ; - RECT 2.825000 0.895000 4.055000 1.065000 ; - RECT 3.135000 1.875000 3.305000 2.635000 ; - RECT 3.535000 0.290000 3.780000 0.895000 ; - RECT 3.540000 1.875000 4.055000 2.285000 ; - RECT 3.715000 1.065000 4.055000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__mux2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.815000 0.765000 2.445000 1.280000 ; - RECT 2.275000 1.280000 2.445000 1.315000 ; - RECT 2.275000 1.315000 3.090000 1.625000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.625000 0.735000 3.090000 1.025000 ; - RECT 2.900000 0.420000 3.090000 0.735000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.360000 0.755000 3.550000 1.625000 ; - END - END S - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.765000 0.750000 ; - RECT 0.515000 0.750000 0.685000 1.595000 ; - RECT 0.515000 1.595000 0.825000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.085000 0.345000 0.885000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.855000 0.995000 1.165000 1.325000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 0.995000 0.635000 1.605000 0.805000 ; - RECT 0.995000 0.805000 1.165000 0.995000 ; - RECT 0.995000 1.325000 1.165000 1.835000 ; - RECT 0.995000 1.835000 1.655000 2.005000 ; - RECT 1.025000 2.175000 1.315000 2.635000 ; - RECT 1.335000 0.995000 1.505000 1.495000 ; - RECT 1.335000 1.495000 1.995000 1.665000 ; - RECT 1.435000 0.295000 2.730000 0.465000 ; - RECT 1.435000 0.465000 1.605000 0.635000 ; - RECT 1.485000 2.005000 1.655000 2.255000 ; - RECT 1.485000 2.255000 2.795000 2.425000 ; - RECT 1.825000 1.665000 1.995000 1.835000 ; - RECT 1.825000 1.835000 4.050000 2.005000 ; - RECT 3.325000 2.175000 3.545000 2.635000 ; - RECT 3.350000 0.085000 3.550000 0.585000 ; - RECT 3.715000 2.005000 4.050000 2.465000 ; - RECT 3.720000 0.255000 4.050000 1.835000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__mux2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 0.995000 1.750000 1.615000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.965000 0.995000 2.435000 1.325000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 0.995000 0.740000 1.325000 ; - RECT 0.570000 0.635000 2.850000 0.805000 ; - RECT 0.570000 0.805000 0.740000 0.995000 ; - RECT 2.680000 0.805000 2.850000 0.995000 ; - RECT 2.680000 0.995000 3.395000 1.325000 ; - END - END S - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.915000 0.255000 4.085000 0.635000 ; - RECT 3.915000 0.635000 5.430000 0.805000 ; - RECT 3.915000 1.575000 5.430000 1.745000 ; - RECT 3.915000 1.745000 4.085000 2.465000 ; - RECT 4.755000 0.255000 4.925000 0.635000 ; - RECT 4.755000 1.745000 4.925000 2.465000 ; - RECT 5.200000 0.805000 5.430000 1.575000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.090000 0.295000 0.345000 0.625000 ; - RECT 0.090000 0.625000 0.260000 1.495000 ; - RECT 0.090000 1.495000 1.080000 1.665000 ; - RECT 0.090000 1.665000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 1.835000 0.820000 2.635000 ; - RECT 0.910000 0.995000 1.080000 1.495000 ; - RECT 0.990000 1.935000 1.340000 2.275000 ; - RECT 0.990000 2.275000 2.770000 2.445000 ; - RECT 1.530000 1.935000 3.245000 2.105000 ; - RECT 1.975000 0.295000 3.230000 0.465000 ; - RECT 1.980000 1.595000 3.735000 1.765000 ; - RECT 3.060000 0.465000 3.230000 0.655000 ; - RECT 3.060000 0.655000 3.735000 0.825000 ; - RECT 3.075000 2.105000 3.245000 2.465000 ; - RECT 3.415000 0.085000 3.745000 0.465000 ; - RECT 3.415000 2.255000 3.745000 2.635000 ; - RECT 3.565000 0.825000 3.735000 1.075000 ; - RECT 3.565000 1.075000 5.030000 1.245000 ; - RECT 3.565000 1.245000 3.735000 1.595000 ; - RECT 3.565000 1.765000 3.735000 1.785000 ; - RECT 4.255000 0.085000 4.585000 0.465000 ; - RECT 4.255000 1.915000 4.585000 2.635000 ; - RECT 5.095000 0.085000 5.425000 0.465000 ; - RECT 5.095000 1.915000 5.425000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__mux2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.492000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.180000 0.645000 6.895000 0.815000 ; - RECT 5.180000 0.815000 5.350000 1.325000 ; - RECT 5.305000 0.425000 5.890000 0.645000 ; - RECT 6.725000 0.815000 6.895000 0.995000 ; - RECT 6.725000 0.995000 7.195000 1.165000 ; - RECT 7.025000 1.165000 7.195000 1.325000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.492000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.290000 1.105000 4.475000 1.275000 ; - RECT 4.305000 0.995000 4.475000 1.105000 ; - RECT 4.305000 1.275000 4.475000 1.325000 ; - LAYER mcon ; - RECT 4.290000 1.105000 4.460000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 7.960000 0.995000 8.245000 1.325000 ; - LAYER mcon ; - RECT 7.960000 1.105000 8.130000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 4.230000 1.075000 4.520000 1.120000 ; - RECT 4.230000 1.120000 8.190000 1.260000 ; - RECT 4.230000 1.260000 4.520000 1.305000 ; - RECT 7.900000 1.075000 8.190000 1.120000 ; - RECT 7.900000 1.260000 8.190000 1.305000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.739500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.795000 0.995000 3.965000 1.495000 ; - RECT 3.795000 1.495000 6.035000 1.665000 ; - RECT 5.670000 0.995000 6.035000 1.495000 ; - LAYER mcon ; - RECT 5.670000 1.445000 5.840000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 9.215000 0.995000 9.510000 1.615000 ; - LAYER mcon ; - RECT 9.340000 1.445000 9.510000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 5.610000 1.415000 5.900000 1.460000 ; - RECT 5.610000 1.460000 9.570000 1.600000 ; - RECT 5.610000 1.600000 5.900000 1.645000 ; - RECT 9.280000 1.415000 9.570000 1.460000 ; - RECT 9.280000 1.600000 9.570000 1.645000 ; - END - END S - PIN X - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.255000 0.765000 0.635000 ; - RECT 0.595000 0.635000 3.285000 0.805000 ; - RECT 0.595000 0.805000 0.815000 1.575000 ; - RECT 0.595000 1.575000 3.285000 1.745000 ; - RECT 0.595000 1.745000 0.765000 2.465000 ; - RECT 1.435000 0.295000 1.605000 0.635000 ; - RECT 1.435000 1.745000 1.605000 2.465000 ; - RECT 2.275000 0.255000 2.445000 0.635000 ; - RECT 2.275000 1.745000 2.445000 2.465000 ; - RECT 3.115000 0.295000 3.285000 0.635000 ; - RECT 3.115000 1.745000 3.285000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.465000 ; - RECT 0.090000 1.915000 0.425000 2.635000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 0.935000 1.915000 1.265000 2.635000 ; - RECT 0.985000 1.075000 3.625000 1.245000 ; - RECT 1.775000 0.085000 2.105000 0.465000 ; - RECT 1.775000 1.915000 2.105000 2.635000 ; - RECT 2.615000 0.085000 2.945000 0.465000 ; - RECT 2.615000 1.915000 2.945000 2.635000 ; - RECT 3.455000 0.085000 3.785000 0.465000 ; - RECT 3.455000 0.635000 4.920000 0.805000 ; - RECT 3.455000 0.805000 3.625000 1.075000 ; - RECT 3.455000 1.245000 3.625000 1.835000 ; - RECT 3.455000 1.835000 8.225000 2.005000 ; - RECT 3.455000 2.255000 3.785000 2.635000 ; - RECT 3.955000 0.295000 5.125000 0.465000 ; - RECT 3.955000 2.255000 5.905000 2.425000 ; - RECT 4.750000 0.805000 4.920000 0.935000 ; - RECT 6.060000 0.085000 6.390000 0.465000 ; - RECT 6.075000 2.175000 6.245000 2.635000 ; - RECT 6.345000 0.995000 6.515000 1.495000 ; - RECT 6.345000 1.495000 8.855000 1.665000 ; - RECT 6.480000 2.255000 8.645000 2.425000 ; - RECT 6.575000 0.295000 7.865000 0.465000 ; - RECT 7.115000 0.635000 7.670000 0.805000 ; - RECT 7.500000 0.805000 7.670000 0.935000 ; - RECT 8.685000 0.645000 9.485000 0.815000 ; - RECT 8.685000 0.815000 8.855000 1.495000 ; - RECT 8.685000 1.665000 8.855000 1.915000 ; - RECT 8.685000 1.915000 9.485000 2.085000 ; - RECT 8.815000 0.085000 9.145000 0.465000 ; - RECT 8.815000 2.255000 9.145000 2.635000 ; - RECT 9.315000 0.295000 9.485000 0.645000 ; - RECT 9.315000 1.795000 9.485000 1.915000 ; - RECT 9.315000 2.085000 9.485000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.750000 0.765000 4.920000 0.935000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.500000 0.765000 7.670000 0.935000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 4.690000 0.735000 4.980000 0.780000 ; - RECT 4.690000 0.780000 7.730000 0.920000 ; - RECT 4.690000 0.920000 4.980000 0.965000 ; - RECT 7.440000 0.735000 7.730000 0.780000 ; - RECT 7.440000 0.920000 7.730000 0.965000 ; - END -END sky130_fd_sc_hd__mux2_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2i_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2i_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.060000 0.420000 1.285000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.955000 0.995000 1.125000 1.155000 ; - RECT 0.955000 1.155000 1.205000 1.325000 ; - RECT 1.035000 1.325000 1.205000 1.445000 ; - RECT 1.035000 1.445000 1.235000 2.110000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.260000 0.760000 3.595000 1.620000 ; - END - END S - PIN Y - ANTENNADIFFAREA 0.480500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.590000 0.595000 0.780000 1.455000 ; - RECT 0.590000 1.455000 0.840000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.255000 1.805000 0.425000 ; - RECT 0.085000 0.425000 0.440000 0.465000 ; - RECT 0.085000 0.465000 0.345000 0.885000 ; - RECT 0.120000 1.455000 0.420000 2.295000 ; - RECT 0.120000 2.295000 1.575000 2.465000 ; - RECT 0.955000 0.655000 1.520000 0.715000 ; - RECT 0.955000 0.715000 2.620000 0.825000 ; - RECT 0.965000 0.425000 1.805000 0.465000 ; - RECT 1.295000 0.825000 2.620000 0.885000 ; - RECT 1.385000 1.075000 3.085000 1.310000 ; - RECT 1.405000 1.480000 2.615000 1.650000 ; - RECT 1.405000 1.650000 1.575000 2.295000 ; - RECT 1.745000 1.835000 1.975000 2.635000 ; - RECT 1.975000 0.085000 2.145000 0.545000 ; - RECT 2.285000 1.650000 2.615000 2.465000 ; - RECT 2.385000 0.255000 2.620000 0.715000 ; - RECT 2.800000 0.255000 3.165000 0.485000 ; - RECT 2.800000 0.485000 3.085000 1.075000 ; - RECT 2.860000 1.310000 3.085000 2.465000 ; - RECT 3.295000 1.835000 3.590000 2.635000 ; - RECT 3.335000 0.085000 3.555000 0.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__mux2i_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2i_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2i_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.470000 1.075000 3.560000 1.275000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.310000 0.995000 4.635000 1.615000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 0.742500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 0.995000 0.780000 1.325000 ; - RECT 0.580000 0.725000 0.780000 0.995000 ; - END - END S - PIN Y - ANTENNADIFFAREA 1.691250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.715000 0.295000 4.975000 0.465000 ; - RECT 2.715000 2.255000 4.975000 2.425000 ; - RECT 4.750000 1.785000 4.975000 2.255000 ; - RECT 4.805000 0.465000 4.975000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.345000 0.345000 0.675000 ; - RECT 0.085000 0.675000 0.260000 1.495000 ; - RECT 0.085000 1.495000 1.395000 1.665000 ; - RECT 0.085000 1.665000 0.260000 2.135000 ; - RECT 0.085000 2.135000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.835000 0.545000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 0.935000 1.835000 1.735000 2.005000 ; - RECT 1.015000 0.575000 1.255000 0.935000 ; - RECT 1.225000 1.155000 1.985000 1.325000 ; - RECT 1.225000 1.325000 1.395000 1.495000 ; - RECT 1.355000 2.255000 1.685000 2.635000 ; - RECT 1.435000 0.085000 1.685000 0.885000 ; - RECT 1.565000 1.495000 3.465000 1.665000 ; - RECT 1.565000 1.665000 1.735000 1.835000 ; - RECT 1.655000 1.075000 1.985000 1.155000 ; - RECT 1.855000 0.295000 2.025000 0.735000 ; - RECT 1.855000 0.735000 3.465000 0.905000 ; - RECT 1.855000 2.135000 2.080000 2.465000 ; - RECT 1.910000 1.835000 2.885000 1.915000 ; - RECT 1.910000 1.915000 4.350000 2.005000 ; - RECT 1.910000 2.005000 2.080000 2.135000 ; - RECT 2.275000 0.085000 2.445000 0.545000 ; - RECT 2.275000 2.175000 2.525000 2.635000 ; - RECT 2.715000 2.005000 4.350000 2.085000 ; - RECT 3.135000 0.655000 3.465000 0.735000 ; - RECT 3.135000 1.665000 3.465000 1.715000 ; - RECT 3.850000 0.655000 4.345000 0.825000 ; - RECT 3.850000 0.825000 4.105000 0.935000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 0.765000 1.240000 0.935000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 3.850000 0.765000 4.020000 0.935000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - LAYER met1 ; - RECT 1.010000 0.735000 1.300000 0.780000 ; - RECT 1.010000 0.780000 4.080000 0.920000 ; - RECT 1.010000 0.920000 1.300000 0.965000 ; - RECT 3.790000 0.735000 4.080000 0.780000 ; - RECT 3.790000 0.920000 4.080000 0.965000 ; - END -END sky130_fd_sc_hd__mux2i_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux2i_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux2i_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.560000 0.995000 1.070000 1.105000 ; - RECT 0.560000 1.105000 1.240000 1.325000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.955000 0.995000 3.550000 1.325000 ; - END - END A1 - PIN S - ANTENNAGATEAREA 1.237500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.845000 1.075000 5.930000 1.290000 ; - RECT 5.760000 1.290000 5.930000 1.425000 ; - RECT 5.760000 1.425000 7.850000 1.595000 ; - RECT 7.680000 0.995000 7.850000 1.425000 ; - END - END S - PIN Y - ANTENNADIFFAREA 2.194500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.315000 3.785000 0.485000 ; - RECT 0.095000 0.485000 0.320000 2.255000 ; - RECT 0.095000 2.255000 3.785000 2.425000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.515000 0.655000 1.700000 0.825000 ; - RECT 0.515000 1.575000 5.580000 1.745000 ; - RECT 1.355000 0.825000 1.700000 0.935000 ; - RECT 2.195000 0.655000 5.485000 0.825000 ; - RECT 2.195000 1.915000 7.165000 2.085000 ; - RECT 3.975000 0.085000 4.305000 0.465000 ; - RECT 3.975000 2.255000 4.305000 2.635000 ; - RECT 4.475000 0.255000 4.645000 0.655000 ; - RECT 4.815000 0.085000 5.145000 0.465000 ; - RECT 4.815000 2.255000 5.145000 2.635000 ; - RECT 5.315000 0.255000 5.485000 0.655000 ; - RECT 5.655000 0.085000 5.980000 0.590000 ; - RECT 5.655000 2.255000 5.985000 2.635000 ; - RECT 6.150000 0.255000 6.325000 0.715000 ; - RECT 6.150000 0.715000 7.165000 0.905000 ; - RECT 6.150000 0.905000 6.450000 0.935000 ; - RECT 6.155000 1.795000 6.325000 1.915000 ; - RECT 6.155000 2.085000 6.325000 2.465000 ; - RECT 6.495000 2.255000 6.825000 2.635000 ; - RECT 6.545000 0.085000 6.795000 0.545000 ; - RECT 6.730000 1.075000 7.510000 1.245000 ; - RECT 6.995000 0.510000 7.165000 0.715000 ; - RECT 6.995000 1.795000 7.165000 1.915000 ; - RECT 6.995000 2.085000 7.165000 2.465000 ; - RECT 7.340000 0.655000 8.195000 0.825000 ; - RECT 7.340000 0.825000 7.510000 1.075000 ; - RECT 7.435000 0.085000 7.765000 0.465000 ; - RECT 7.435000 2.255000 7.765000 2.635000 ; - RECT 7.935000 0.255000 8.195000 0.655000 ; - RECT 7.935000 1.795000 8.195000 2.465000 ; - RECT 8.020000 0.825000 8.195000 1.795000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 0.765000 1.700000 0.935000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.150000 0.765000 6.320000 0.935000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 1.470000 0.735000 1.760000 0.780000 ; - RECT 1.470000 0.780000 6.380000 0.920000 ; - RECT 1.470000 0.920000 1.760000 0.965000 ; - RECT 6.090000 0.735000 6.380000 0.780000 ; - RECT 6.090000 0.920000 6.380000 0.965000 ; - END -END sky130_fd_sc_hd__mux2i_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux4_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux4_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.805000 0.995000 1.240000 1.615000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.995000 0.495000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.250000 1.055000 5.580000 1.675000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.800000 1.055000 5.045000 1.675000 ; - END - END A3 - PIN S0 - ANTENNAGATEAREA 0.378000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.265000 0.995000 3.565000 1.995000 ; - END - END S0 - PIN S1 - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.055000 0.995000 6.345000 1.675000 ; - END - END S1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.315000 0.255000 9.575000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.175000 0.260000 0.345000 0.635000 ; - RECT 0.175000 0.635000 1.185000 0.805000 ; - RECT 0.175000 1.795000 1.705000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 1.015000 0.255000 2.090000 0.425000 ; - RECT 1.015000 0.425000 1.185000 0.635000 ; - RECT 1.015000 2.135000 1.185000 2.295000 ; - RECT 1.015000 2.295000 2.545000 2.465000 ; - RECT 1.410000 0.595000 1.750000 0.765000 ; - RECT 1.410000 0.765000 1.700000 0.935000 ; - RECT 1.410000 0.935000 1.580000 1.455000 ; - RECT 1.410000 1.455000 2.045000 1.625000 ; - RECT 1.535000 1.965000 1.705000 2.125000 ; - RECT 1.875000 1.625000 2.045000 1.955000 ; - RECT 1.875000 1.955000 2.205000 2.125000 ; - RECT 1.920000 0.425000 2.090000 0.760000 ; - RECT 2.080000 1.105000 2.620000 1.285000 ; - RECT 2.260000 0.430000 2.620000 1.105000 ; - RECT 2.260000 1.285000 2.620000 1.395000 ; - RECT 2.260000 1.395000 3.065000 1.625000 ; - RECT 2.375000 1.795000 2.545000 2.295000 ; - RECT 2.715000 1.625000 3.065000 2.465000 ; - RECT 2.800000 0.085000 3.090000 0.805000 ; - RECT 3.235000 2.255000 3.565000 2.635000 ; - RECT 3.380000 0.255000 4.980000 0.425000 ; - RECT 3.380000 0.425000 3.550000 0.795000 ; - RECT 3.720000 0.595000 4.050000 0.845000 ; - RECT 3.735000 0.845000 4.050000 0.920000 ; - RECT 3.735000 0.920000 3.905000 1.445000 ; - RECT 3.735000 1.445000 4.495000 1.615000 ; - RECT 3.825000 1.785000 3.995000 2.295000 ; - RECT 3.825000 2.295000 4.835000 2.465000 ; - RECT 4.075000 1.095000 4.405000 1.105000 ; - RECT 4.075000 1.105000 4.460000 1.265000 ; - RECT 4.165000 1.615000 4.495000 2.125000 ; - RECT 4.220000 0.595000 4.390000 0.715000 ; - RECT 4.220000 0.715000 5.740000 0.885000 ; - RECT 4.220000 0.885000 4.390000 0.925000 ; - RECT 4.290000 1.265000 4.460000 1.275000 ; - RECT 4.625000 0.425000 4.980000 0.465000 ; - RECT 4.665000 1.915000 5.730000 2.085000 ; - RECT 4.665000 2.085000 4.835000 2.295000 ; - RECT 5.060000 2.255000 5.390000 2.635000 ; - RECT 5.150000 0.085000 5.320000 0.545000 ; - RECT 5.495000 0.295000 5.740000 0.715000 ; - RECT 5.560000 2.085000 5.730000 2.465000 ; - RECT 5.980000 2.255000 6.330000 2.635000 ; - RECT 6.010000 0.085000 6.340000 0.465000 ; - RECT 6.500000 2.135000 6.685000 2.465000 ; - RECT 6.510000 0.325000 6.685000 0.655000 ; - RECT 6.515000 0.655000 6.685000 1.105000 ; - RECT 6.515000 1.105000 6.805000 1.275000 ; - RECT 6.515000 1.275000 6.685000 2.135000 ; - RECT 6.980000 0.765000 7.220000 0.935000 ; - RECT 6.980000 0.935000 7.150000 2.135000 ; - RECT 6.980000 2.135000 7.190000 2.465000 ; - RECT 7.030000 0.255000 7.200000 0.415000 ; - RECT 7.030000 0.415000 7.560000 0.585000 ; - RECT 7.360000 2.255000 7.690000 2.295000 ; - RECT 7.360000 2.295000 8.645000 2.465000 ; - RECT 7.390000 0.585000 7.560000 1.755000 ; - RECT 7.390000 1.755000 8.175000 1.985000 ; - RECT 7.730000 0.255000 8.725000 0.425000 ; - RECT 7.730000 0.425000 7.900000 0.585000 ; - RECT 7.845000 1.985000 8.175000 2.125000 ; - RECT 7.970000 0.765000 8.385000 0.925000 ; - RECT 7.970000 0.925000 8.380000 0.935000 ; - RECT 8.190000 1.105000 8.645000 1.275000 ; - RECT 8.210000 0.595000 8.385000 0.765000 ; - RECT 8.475000 1.665000 9.125000 1.835000 ; - RECT 8.475000 1.835000 8.645000 2.295000 ; - RECT 8.555000 0.425000 8.725000 0.715000 ; - RECT 8.555000 0.715000 9.125000 0.885000 ; - RECT 8.815000 2.255000 9.145000 2.635000 ; - RECT 8.895000 0.085000 9.065000 0.545000 ; - RECT 8.955000 0.885000 9.125000 1.665000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 0.765000 1.700000 0.935000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.450000 1.105000 2.620000 1.275000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.290000 1.105000 4.460000 1.275000 ; - RECT 4.325000 1.785000 4.495000 1.955000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.635000 1.105000 6.805000 1.275000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.050000 0.765000 7.220000 0.935000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.555000 1.785000 7.725000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.475000 1.105000 8.645000 1.275000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 1.470000 0.735000 1.760000 0.780000 ; - RECT 1.470000 0.780000 8.200000 0.920000 ; - RECT 1.470000 0.920000 1.760000 0.965000 ; - RECT 2.390000 1.075000 2.680000 1.120000 ; - RECT 2.390000 1.120000 4.520000 1.260000 ; - RECT 2.390000 1.260000 2.680000 1.305000 ; - RECT 4.230000 1.075000 4.520000 1.120000 ; - RECT 4.230000 1.260000 4.520000 1.305000 ; - RECT 4.265000 1.755000 4.555000 1.800000 ; - RECT 4.265000 1.800000 7.785000 1.940000 ; - RECT 4.265000 1.940000 4.555000 1.985000 ; - RECT 6.575000 1.075000 6.865000 1.120000 ; - RECT 6.575000 1.120000 8.705000 1.260000 ; - RECT 6.575000 1.260000 6.865000 1.305000 ; - RECT 6.990000 0.735000 7.280000 0.780000 ; - RECT 6.990000 0.920000 7.280000 0.965000 ; - RECT 7.495000 1.755000 7.785000 1.800000 ; - RECT 7.495000 1.940000 7.785000 1.985000 ; - RECT 7.910000 0.735000 8.200000 0.780000 ; - RECT 7.910000 0.920000 8.200000 0.965000 ; - RECT 8.415000 1.075000 8.705000 1.120000 ; - RECT 8.415000 1.260000 8.705000 1.305000 ; - END -END sky130_fd_sc_hd__mux4_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux4_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux4_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.535000 0.375000 6.845000 0.995000 ; - RECT 6.535000 0.995000 6.945000 1.075000 ; - RECT 6.635000 1.075000 6.945000 1.325000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.745000 0.715000 5.115000 1.395000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.835000 0.765000 1.235000 1.095000 ; - RECT 1.020000 0.395000 1.235000 0.765000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.240000 0.715000 2.615000 1.015000 ; - RECT 2.410000 1.015000 2.615000 1.320000 ; - END - END A3 - PIN S0 - ANTENNAGATEAREA 0.393000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.975000 0.325000 1.745000 ; - LAYER mcon ; - RECT 0.145000 1.445000 0.315000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 1.005000 1.445000 1.390000 1.615000 ; - RECT 1.220000 1.285000 1.390000 1.445000 ; - LAYER mcon ; - RECT 1.065000 1.445000 1.235000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 6.125000 1.245000 6.465000 1.645000 ; - LAYER mcon ; - RECT 6.125000 1.445000 6.295000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 0.085000 1.415000 0.375000 1.460000 ; - RECT 0.085000 1.460000 6.355000 1.600000 ; - RECT 0.085000 1.600000 0.375000 1.645000 ; - RECT 1.005000 1.415000 1.295000 1.460000 ; - RECT 1.005000 1.600000 1.295000 1.645000 ; - RECT 6.065000 1.415000 6.355000 1.460000 ; - RECT 6.065000 1.600000 6.355000 1.645000 ; - END - END S0 - PIN S1 - ANTENNAGATEAREA 0.303000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.785000 0.715000 3.075000 1.320000 ; - END - END S1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.355000 1.835000 7.765000 2.455000 ; - RECT 7.435000 0.265000 7.765000 0.725000 ; - RECT 7.455000 1.495000 7.765000 1.835000 ; - RECT 7.595000 0.725000 7.765000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.170000 0.345000 0.345000 0.635000 ; - RECT 0.170000 0.635000 0.665000 0.805000 ; - RECT 0.175000 1.915000 1.900000 1.955000 ; - RECT 0.175000 1.955000 0.665000 2.085000 ; - RECT 0.175000 2.085000 0.345000 2.375000 ; - RECT 0.495000 0.805000 0.665000 1.785000 ; - RECT 0.495000 1.785000 1.900000 1.915000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 1.405000 0.705000 1.730000 1.035000 ; - RECT 1.410000 2.125000 2.240000 2.295000 ; - RECT 1.470000 0.365000 2.070000 0.535000 ; - RECT 1.560000 1.035000 1.730000 1.575000 ; - RECT 1.560000 1.575000 1.900000 1.785000 ; - RECT 1.900000 0.535000 2.070000 1.235000 ; - RECT 1.900000 1.235000 2.240000 1.405000 ; - RECT 2.070000 1.405000 2.240000 2.125000 ; - RECT 2.450000 0.085000 2.780000 0.545000 ; - RECT 2.595000 2.055000 2.825000 2.635000 ; - RECT 2.970000 1.785000 3.315000 1.955000 ; - RECT 2.985000 0.295000 3.415000 0.465000 ; - RECT 3.145000 1.490000 3.415000 1.660000 ; - RECT 3.145000 1.660000 3.315000 1.785000 ; - RECT 3.245000 0.465000 3.415000 1.060000 ; - RECT 3.245000 1.060000 3.480000 1.390000 ; - RECT 3.245000 1.390000 3.415000 1.490000 ; - RECT 3.305000 2.125000 3.820000 2.295000 ; - RECT 3.565000 1.810000 3.820000 2.125000 ; - RECT 3.585000 0.345000 3.820000 0.675000 ; - RECT 3.650000 0.675000 3.820000 1.810000 ; - RECT 3.990000 0.345000 4.180000 2.125000 ; - RECT 3.990000 2.125000 4.515000 2.295000 ; - RECT 4.395000 0.255000 4.600000 0.585000 ; - RECT 4.395000 0.585000 4.565000 1.565000 ; - RECT 4.395000 1.565000 5.495000 1.735000 ; - RECT 4.395000 1.735000 4.585000 1.895000 ; - RECT 4.755000 2.005000 5.100000 2.635000 ; - RECT 4.795000 0.085000 5.125000 0.545000 ; - RECT 5.325000 0.295000 6.220000 0.465000 ; - RECT 5.325000 0.465000 5.495000 1.565000 ; - RECT 5.325000 1.735000 5.495000 2.155000 ; - RECT 5.325000 2.155000 6.275000 2.325000 ; - RECT 5.665000 0.705000 6.285000 1.035000 ; - RECT 5.665000 1.035000 5.955000 1.985000 ; - RECT 6.525000 2.125000 6.845000 2.295000 ; - RECT 6.675000 1.495000 7.285000 1.665000 ; - RECT 6.675000 1.665000 6.845000 2.125000 ; - RECT 7.015000 0.085000 7.265000 0.815000 ; - RECT 7.015000 1.835000 7.185000 2.635000 ; - RECT 7.115000 0.995000 7.425000 1.325000 ; - RECT 7.115000 1.325000 7.285000 1.495000 ; - RECT 7.935000 0.085000 8.190000 0.885000 ; - RECT 7.935000 1.495000 8.185000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.785000 1.695000 1.955000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.125000 2.155000 2.295000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.125000 3.535000 2.295000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.125000 4.455000 2.295000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 1.785000 5.835000 1.955000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.125000 6.755000 2.295000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.755000 1.755000 1.800000 ; - RECT 1.465000 1.800000 5.895000 1.940000 ; - RECT 1.465000 1.940000 1.755000 1.985000 ; - RECT 1.925000 2.095000 2.215000 2.140000 ; - RECT 1.925000 2.140000 3.595000 2.280000 ; - RECT 1.925000 2.280000 2.215000 2.325000 ; - RECT 3.305000 2.095000 3.595000 2.140000 ; - RECT 3.305000 2.280000 3.595000 2.325000 ; - RECT 4.225000 2.095000 4.515000 2.140000 ; - RECT 4.225000 2.140000 6.815000 2.280000 ; - RECT 4.225000 2.280000 4.515000 2.325000 ; - RECT 5.605000 1.755000 5.895000 1.800000 ; - RECT 5.605000 1.940000 5.895000 1.985000 ; - RECT 6.525000 2.095000 6.815000 2.140000 ; - RECT 6.525000 2.280000 6.815000 2.325000 ; - END -END sky130_fd_sc_hd__mux4_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__mux4_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__mux4_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A0 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.540000 0.375000 6.850000 0.995000 ; - RECT 6.540000 0.995000 6.950000 1.075000 ; - RECT 6.640000 1.075000 6.950000 1.325000 ; - END - END A0 - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.750000 0.715000 5.120000 1.395000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.840000 0.765000 1.240000 1.095000 ; - RECT 1.025000 0.395000 1.240000 0.765000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.245000 0.715000 2.620000 1.015000 ; - RECT 2.415000 1.015000 2.620000 1.320000 ; - END - END A3 - PIN S0 - ANTENNAGATEAREA 0.393000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.975000 0.330000 1.745000 ; - LAYER mcon ; - RECT 0.150000 1.445000 0.320000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 1.010000 1.445000 1.395000 1.615000 ; - RECT 1.225000 1.285000 1.395000 1.445000 ; - LAYER mcon ; - RECT 1.070000 1.445000 1.240000 1.615000 ; - END - PORT - LAYER li1 ; - RECT 6.130000 1.245000 6.470000 1.645000 ; - LAYER mcon ; - RECT 6.130000 1.445000 6.300000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 0.085000 1.415000 0.380000 1.460000 ; - RECT 0.085000 1.460000 6.360000 1.600000 ; - RECT 0.085000 1.600000 0.380000 1.645000 ; - RECT 1.010000 1.415000 1.300000 1.460000 ; - RECT 1.010000 1.600000 1.300000 1.645000 ; - RECT 6.070000 1.415000 6.360000 1.460000 ; - RECT 6.070000 1.600000 6.360000 1.645000 ; - END - END S0 - PIN S1 - ANTENNAGATEAREA 0.303000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.790000 0.715000 3.080000 1.320000 ; - END - END S1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.360000 1.835000 7.770000 2.455000 ; - RECT 7.440000 0.265000 7.770000 0.725000 ; - RECT 7.460000 1.495000 7.770000 1.835000 ; - RECT 7.600000 0.725000 7.770000 1.065000 ; - RECT 7.600000 1.065000 8.685000 1.305000 ; - RECT 7.600000 1.305000 7.770000 1.495000 ; - RECT 8.360000 0.265000 8.685000 1.065000 ; - RECT 8.360000 1.305000 8.685000 2.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.135000 0.345000 0.345000 0.635000 ; - RECT 0.135000 0.635000 0.670000 0.805000 ; - RECT 0.135000 1.915000 1.905000 1.955000 ; - RECT 0.135000 1.955000 0.670000 2.085000 ; - RECT 0.135000 2.085000 0.345000 2.375000 ; - RECT 0.500000 0.805000 0.670000 1.785000 ; - RECT 0.500000 1.785000 1.905000 1.915000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.255000 0.845000 2.635000 ; - RECT 1.410000 0.705000 1.735000 1.035000 ; - RECT 1.415000 2.125000 2.245000 2.295000 ; - RECT 1.475000 0.365000 2.075000 0.535000 ; - RECT 1.565000 1.035000 1.735000 1.575000 ; - RECT 1.565000 1.575000 1.905000 1.785000 ; - RECT 1.905000 0.535000 2.075000 1.235000 ; - RECT 1.905000 1.235000 2.245000 1.405000 ; - RECT 2.075000 1.405000 2.245000 2.125000 ; - RECT 2.455000 0.085000 2.785000 0.545000 ; - RECT 2.600000 2.055000 2.830000 2.635000 ; - RECT 2.975000 1.785000 3.320000 1.955000 ; - RECT 2.990000 0.295000 3.420000 0.465000 ; - RECT 3.150000 1.490000 3.420000 1.660000 ; - RECT 3.150000 1.660000 3.320000 1.785000 ; - RECT 3.250000 0.465000 3.420000 1.060000 ; - RECT 3.250000 1.060000 3.485000 1.390000 ; - RECT 3.250000 1.390000 3.420000 1.490000 ; - RECT 3.310000 2.125000 3.825000 2.295000 ; - RECT 3.575000 1.810000 3.825000 2.125000 ; - RECT 3.590000 0.345000 3.825000 0.675000 ; - RECT 3.655000 0.675000 3.825000 1.810000 ; - RECT 3.995000 0.345000 4.185000 2.125000 ; - RECT 3.995000 2.125000 4.520000 2.295000 ; - RECT 4.400000 0.255000 4.605000 0.585000 ; - RECT 4.400000 0.585000 4.570000 1.565000 ; - RECT 4.400000 1.565000 5.500000 1.735000 ; - RECT 4.400000 1.735000 4.590000 1.895000 ; - RECT 4.760000 2.005000 5.105000 2.635000 ; - RECT 4.800000 0.085000 5.130000 0.545000 ; - RECT 5.330000 0.295000 6.225000 0.465000 ; - RECT 5.330000 0.465000 5.500000 1.565000 ; - RECT 5.330000 1.735000 5.500000 2.155000 ; - RECT 5.330000 2.155000 6.280000 2.325000 ; - RECT 5.670000 0.705000 6.290000 1.035000 ; - RECT 5.670000 1.035000 5.960000 1.985000 ; - RECT 6.530000 2.125000 6.850000 2.295000 ; - RECT 6.680000 1.495000 7.290000 1.665000 ; - RECT 6.680000 1.665000 6.850000 2.125000 ; - RECT 7.020000 0.085000 7.270000 0.815000 ; - RECT 7.020000 1.835000 7.190000 2.635000 ; - RECT 7.120000 0.995000 7.430000 1.325000 ; - RECT 7.120000 1.325000 7.290000 1.495000 ; - RECT 7.940000 0.085000 8.190000 0.885000 ; - RECT 7.940000 1.495000 8.190000 2.635000 ; - RECT 8.855000 0.085000 9.105000 0.885000 ; - RECT 8.855000 1.495000 9.105000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 1.785000 1.700000 1.955000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 1.990000 2.125000 2.160000 2.295000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.370000 2.125000 3.540000 2.295000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.290000 2.125000 4.460000 2.295000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 5.670000 1.785000 5.840000 1.955000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.590000 2.125000 6.760000 2.295000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - LAYER met1 ; - RECT 1.470000 1.755000 1.760000 1.800000 ; - RECT 1.470000 1.800000 5.900000 1.940000 ; - RECT 1.470000 1.940000 1.760000 1.985000 ; - RECT 1.930000 2.095000 2.220000 2.140000 ; - RECT 1.930000 2.140000 3.600000 2.280000 ; - RECT 1.930000 2.280000 2.220000 2.325000 ; - RECT 3.310000 2.095000 3.600000 2.140000 ; - RECT 3.310000 2.280000 3.600000 2.325000 ; - RECT 4.230000 2.095000 4.520000 2.140000 ; - RECT 4.230000 2.140000 6.820000 2.280000 ; - RECT 4.230000 2.280000 4.520000 2.325000 ; - RECT 5.610000 1.755000 5.900000 1.800000 ; - RECT 5.610000 1.940000 5.900000 1.985000 ; - RECT 6.530000 2.095000 6.820000 2.140000 ; - RECT 6.530000 2.280000 6.820000 2.325000 ; - END -END sky130_fd_sc_hd__mux4_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.940000 1.075000 1.275000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 1.055000 0.430000 1.325000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.439000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 1.485000 0.865000 2.465000 ; - RECT 0.600000 0.255000 1.295000 0.885000 ; - RECT 0.600000 0.885000 0.770000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.085000 0.085000 0.395000 0.885000 ; - RECT 0.085000 1.495000 0.365000 2.635000 ; - RECT 1.035000 1.495000 1.295000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__nand2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.015000 1.075000 1.765000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.845000 1.325000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.715500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.495000 2.215000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 0.655000 2.215000 0.905000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 1.935000 0.905000 2.215000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.255000 0.425000 0.715000 ; - RECT 0.085000 0.715000 1.185000 0.885000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.935000 0.255000 2.105000 0.465000 ; - RECT 0.935000 0.465000 1.185000 0.715000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.775000 0.465000 2.105000 0.485000 ; - RECT 1.855000 1.835000 2.110000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nand2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.615000 1.075000 4.055000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 1.730000 1.325000 ; - END - END B - PIN Y - ANTENNADIFFAREA 1.431000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.495000 3.365000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 1.910000 1.075000 2.445000 1.495000 ; - RECT 2.195000 0.635000 3.365000 0.805000 ; - RECT 2.195000 0.805000 2.445000 1.075000 ; - RECT 2.195000 1.665000 2.525000 2.465000 ; - RECT 3.035000 1.665000 3.365000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.715000 ; - RECT 0.090000 0.715000 2.025000 0.905000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.935000 0.255000 1.265000 0.715000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.435000 0.085000 1.605000 0.545000 ; - RECT 1.775000 0.255000 3.785000 0.465000 ; - RECT 1.775000 0.465000 2.025000 0.715000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.695000 1.835000 2.865000 2.635000 ; - RECT 3.535000 0.465000 3.785000 0.885000 ; - RECT 3.535000 1.835000 3.785000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__nand2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.290000 1.075000 6.305000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.510000 1.075000 3.365000 1.295000 ; - END - END B - PIN Y - ANTENNADIFFAREA 2.862000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.465000 6.725000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 2.195000 1.665000 2.525000 2.465000 ; - RECT 3.035000 1.665000 3.365000 2.465000 ; - RECT 3.640000 1.075000 4.120000 1.465000 ; - RECT 3.875000 0.655000 6.725000 0.905000 ; - RECT 3.875000 0.905000 4.120000 1.075000 ; - RECT 3.875000 1.665000 4.205000 2.465000 ; - RECT 4.715000 1.665000 5.045000 2.465000 ; - RECT 5.555000 1.665000 5.885000 2.465000 ; - RECT 6.395000 1.665000 6.725000 2.465000 ; - RECT 6.475000 0.905000 6.725000 1.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.735000 ; - RECT 0.090000 0.735000 3.705000 0.905000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.565000 ; - RECT 0.935000 0.255000 1.265000 0.735000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.435000 0.085000 1.605000 0.565000 ; - RECT 1.775000 0.255000 2.105000 0.735000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.275000 0.085000 2.445000 0.565000 ; - RECT 2.615000 0.255000 2.945000 0.735000 ; - RECT 2.695000 1.835000 2.865000 2.635000 ; - RECT 3.115000 0.085000 3.285000 0.565000 ; - RECT 3.455000 0.255000 7.270000 0.485000 ; - RECT 3.455000 0.485000 3.705000 0.735000 ; - RECT 3.535000 1.835000 3.705000 2.635000 ; - RECT 4.375000 1.835000 4.545000 2.635000 ; - RECT 5.215000 1.835000 5.385000 2.635000 ; - RECT 6.055000 1.835000 6.225000 2.635000 ; - RECT 6.895000 0.485000 7.270000 0.905000 ; - RECT 6.915000 1.495000 7.270000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__nand2_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.440000 1.315000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 1.075000 1.085000 1.315000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.439000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.000000 1.835000 2.170000 2.005000 ; - RECT 1.000000 2.005000 1.330000 2.465000 ; - RECT 1.420000 0.255000 2.170000 0.545000 ; - RECT 1.800000 0.545000 2.170000 1.835000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.090000 0.525000 0.360000 0.735000 ; - RECT 0.090000 0.735000 1.425000 0.905000 ; - RECT 0.090000 1.495000 1.425000 1.665000 ; - RECT 0.090000 1.665000 0.370000 1.825000 ; - RECT 0.580000 0.085000 0.910000 0.545000 ; - RECT 0.580000 1.835000 0.830000 2.635000 ; - RECT 1.255000 0.905000 1.425000 1.075000 ; - RECT 1.255000 1.075000 1.630000 1.325000 ; - RECT 1.255000 1.325000 1.425000 1.495000 ; - RECT 1.500000 2.175000 1.715000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nand2b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.455000 0.995000 0.800000 1.325000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 1.075000 3.135000 1.275000 ; - RECT 1.990000 1.275000 2.180000 1.655000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.775500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.035000 1.835000 2.635000 2.005000 ; - RECT 1.035000 2.005000 1.365000 2.465000 ; - RECT 1.525000 0.635000 1.855000 0.805000 ; - RECT 1.530000 0.805000 1.855000 0.905000 ; - RECT 1.530000 0.905000 1.810000 1.835000 ; - RECT 2.280000 2.005000 2.635000 2.465000 ; - RECT 2.360000 1.495000 2.635000 1.835000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.110000 0.510000 0.345000 0.840000 ; - RECT 0.110000 0.840000 0.280000 1.495000 ; - RECT 0.110000 1.495000 1.360000 1.665000 ; - RECT 0.110000 1.665000 0.410000 1.860000 ; - RECT 0.515000 0.085000 0.845000 0.825000 ; - RECT 0.580000 1.835000 0.835000 2.635000 ; - RECT 1.030000 1.075000 1.360000 1.495000 ; - RECT 1.080000 0.255000 2.275000 0.465000 ; - RECT 1.080000 0.465000 1.355000 0.905000 ; - RECT 1.535000 2.175000 2.110000 2.635000 ; - RECT 2.025000 0.465000 2.275000 0.695000 ; - RECT 2.025000 0.695000 3.135000 0.905000 ; - RECT 2.445000 0.085000 2.615000 0.525000 ; - RECT 2.785000 0.255000 3.135000 0.695000 ; - RECT 2.805000 1.495000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__nand2b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand2b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand2b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.440000 1.275000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.155000 1.075000 4.940000 1.275000 ; - END - END B - PIN Y - ANTENNADIFFAREA 1.431000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.455000 0.635000 2.640000 0.905000 ; - RECT 1.455000 1.445000 4.320000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.465000 ; - RECT 2.295000 1.665000 2.640000 2.465000 ; - RECT 2.375000 0.905000 2.640000 1.445000 ; - RECT 3.150000 1.665000 3.480000 2.465000 ; - RECT 3.990000 1.665000 4.320000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.715000 ; - RECT 0.090000 0.715000 0.780000 0.905000 ; - RECT 0.090000 1.445000 0.780000 1.665000 ; - RECT 0.090000 1.665000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.790000 0.545000 ; - RECT 0.595000 1.835000 1.285000 2.635000 ; - RECT 0.610000 0.905000 0.780000 1.075000 ; - RECT 0.610000 1.075000 2.205000 1.275000 ; - RECT 0.610000 1.275000 0.780000 1.445000 ; - RECT 0.970000 1.445000 1.285000 1.835000 ; - RECT 1.035000 0.255000 3.060000 0.465000 ; - RECT 1.035000 0.465000 1.285000 0.905000 ; - RECT 1.955000 1.835000 2.125000 2.635000 ; - RECT 2.810000 0.465000 3.060000 0.715000 ; - RECT 2.810000 0.715000 4.850000 0.905000 ; - RECT 2.810000 1.835000 2.980000 2.635000 ; - RECT 3.230000 0.085000 3.400000 0.545000 ; - RECT 3.570000 0.255000 3.900000 0.715000 ; - RECT 3.650000 1.835000 3.820000 2.635000 ; - RECT 4.070000 0.085000 4.310000 0.545000 ; - RECT 4.520000 0.255000 4.850000 0.715000 ; - RECT 4.520000 1.495000 4.850000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__nand2b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.445000 0.995000 1.755000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.865000 0.765000 1.240000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 0.745000 0.330000 1.325000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.699000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 1.745000 0.595000 ; - RECT 0.515000 0.595000 0.695000 1.495000 ; - RECT 0.515000 1.495000 1.745000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.415000 0.595000 1.745000 0.825000 ; - RECT 1.415000 1.665000 1.745000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.090000 0.085000 0.345000 0.575000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 1.015000 1.835000 1.245000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__nand3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.995000 0.330000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.075000 2.160000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.470000 1.075000 3.595000 1.275000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.985500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.635000 0.845000 1.445000 ; - RECT 0.515000 1.445000 3.045000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 2.715000 1.665000 3.045000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 0.295000 2.105000 0.465000 ; - RECT 0.090000 0.465000 0.345000 0.785000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.355000 0.635000 3.045000 0.905000 ; - RECT 1.855000 1.835000 2.545000 2.635000 ; - RECT 2.295000 0.085000 2.625000 0.465000 ; - RECT 3.215000 0.085000 3.595000 0.885000 ; - RECT 3.215000 1.445000 3.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__nand3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.850000 1.075000 5.565000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 1.075000 3.540000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 1.700000 1.275000 ; - END - END C - PIN Y - ANTENNADIFFAREA 1.971000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.445000 6.355000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 2.195000 1.665000 2.525000 2.465000 ; - RECT 3.035000 1.665000 3.365000 2.465000 ; - RECT 4.395000 0.655000 6.355000 0.905000 ; - RECT 4.395000 1.665000 4.725000 2.465000 ; - RECT 5.235000 1.665000 5.565000 2.465000 ; - RECT 6.125000 0.905000 6.355000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.735000 ; - RECT 0.090000 0.735000 3.785000 0.905000 ; - RECT 0.090000 1.445000 0.345000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.565000 ; - RECT 0.935000 0.255000 1.265000 0.735000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.435000 0.085000 1.605000 0.565000 ; - RECT 1.775000 0.655000 2.105000 0.735000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.195000 0.255000 6.000000 0.485000 ; - RECT 2.615000 0.655000 2.945000 0.735000 ; - RECT 2.695000 1.835000 2.865000 2.635000 ; - RECT 3.455000 0.655000 3.785000 0.735000 ; - RECT 3.535000 1.835000 4.225000 2.635000 ; - RECT 4.895000 1.835000 5.065000 2.635000 ; - RECT 5.735000 1.835000 6.000000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__nand3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.325000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.425000 0.995000 1.755000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.965000 0.995000 1.235000 1.325000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.732000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.130000 1.495000 2.675000 1.665000 ; - RECT 1.130000 1.665000 1.460000 2.465000 ; - RECT 2.085000 0.255000 2.675000 0.485000 ; - RECT 2.085000 1.665000 2.675000 2.465000 ; - RECT 2.385000 0.485000 2.675000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.445000 0.510000 0.655000 ; - RECT 0.085000 0.655000 2.215000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.595000 ; - RECT 0.085000 1.595000 0.510000 1.925000 ; - RECT 0.710000 0.085000 1.040000 0.485000 ; - RECT 0.710000 1.495000 0.960000 2.635000 ; - RECT 1.630000 1.835000 1.915000 2.635000 ; - RECT 2.045000 0.825000 2.215000 1.325000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__nand3b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 1.075000 0.780000 1.275000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.950000 1.075000 3.140000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.060000 1.075000 1.740000 1.275000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.985500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.060000 1.785000 4.050000 1.955000 ; - RECT 1.060000 1.955000 2.230000 2.005000 ; - RECT 1.060000 2.005000 1.390000 2.465000 ; - RECT 1.900000 2.005000 2.230000 2.465000 ; - RECT 3.260000 0.635000 4.050000 0.905000 ; - RECT 3.260000 1.955000 4.050000 2.005000 ; - RECT 3.260000 2.005000 3.510000 2.465000 ; - RECT 3.850000 0.905000 4.050000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.255000 0.410000 0.655000 ; - RECT 0.090000 0.655000 0.260000 1.445000 ; - RECT 0.090000 1.445000 3.650000 1.615000 ; - RECT 0.090000 1.615000 0.260000 2.065000 ; - RECT 0.090000 2.065000 0.410000 2.465000 ; - RECT 0.580000 0.085000 0.890000 0.905000 ; - RECT 0.580000 1.835000 0.890000 2.635000 ; - RECT 1.060000 0.255000 1.390000 0.715000 ; - RECT 1.060000 0.715000 2.750000 0.905000 ; - RECT 1.560000 0.085000 1.810000 0.545000 ; - RECT 1.560000 2.175000 1.730000 2.635000 ; - RECT 2.000000 0.255000 4.050000 0.465000 ; - RECT 2.000000 0.635000 2.750000 0.715000 ; - RECT 2.400000 2.175000 2.650000 2.635000 ; - RECT 2.840000 2.175000 3.090000 2.635000 ; - RECT 2.920000 0.465000 3.090000 0.905000 ; - RECT 3.320000 1.075000 3.650000 1.445000 ; - RECT 3.760000 2.175000 4.050000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__nand3b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand3b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand3b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 1.075000 0.780000 1.275000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.270000 1.075000 4.480000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.790000 1.075000 6.500000 1.275000 ; - END - END C - PIN Y - ANTENNADIFFAREA 1.971000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.455000 0.635000 2.965000 0.905000 ; - RECT 1.455000 1.445000 6.505000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.465000 ; - RECT 2.295000 1.665000 3.465000 2.005000 ; - RECT 2.295000 2.005000 2.625000 2.465000 ; - RECT 2.795000 0.905000 2.965000 1.075000 ; - RECT 2.795000 1.075000 3.100000 1.445000 ; - RECT 3.135000 2.005000 3.465000 2.465000 ; - RECT 3.975000 1.665000 4.305000 2.465000 ; - RECT 5.335000 1.665000 5.665000 2.465000 ; - RECT 6.175000 1.665000 6.505000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.085000 0.255000 0.425000 0.715000 ; - RECT 0.085000 0.715000 1.285000 0.905000 ; - RECT 0.085000 0.905000 0.260000 1.445000 ; - RECT 0.085000 1.445000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.845000 0.545000 ; - RECT 0.595000 1.445000 1.285000 2.635000 ; - RECT 1.005000 0.905000 1.285000 1.075000 ; - RECT 1.005000 1.075000 2.625000 1.275000 ; - RECT 1.035000 0.255000 4.725000 0.465000 ; - RECT 1.955000 1.835000 2.125000 2.635000 ; - RECT 2.795000 2.175000 2.965000 2.635000 ; - RECT 3.135000 0.635000 4.725000 0.715000 ; - RECT 3.135000 0.715000 6.505000 0.905000 ; - RECT 3.635000 1.835000 3.805000 2.635000 ; - RECT 4.475000 1.835000 5.165000 2.635000 ; - RECT 4.915000 0.085000 5.165000 0.545000 ; - RECT 5.335000 0.255000 5.665000 0.715000 ; - RECT 5.835000 0.085000 6.005000 0.545000 ; - RECT 5.835000 1.835000 6.005000 2.635000 ; - RECT 6.175000 0.255000 6.505000 0.715000 ; - RECT 6.675000 0.085000 7.005000 0.905000 ; - RECT 6.675000 1.445000 7.005000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__nand3b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.975000 0.995000 2.215000 1.665000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.000000 0.300000 1.350000 0.825000 ; - RECT 1.145000 0.825000 1.350000 0.995000 ; - RECT 1.145000 0.995000 1.455000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.300000 0.810000 0.995000 ; - RECT 0.595000 0.995000 0.975000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 0.995000 0.395000 1.325000 ; - END - END D - PIN Y - ANTENNADIFFAREA 0.795000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.495000 1.795000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.385000 1.665000 1.715000 2.465000 ; - RECT 1.520000 0.255000 2.215000 0.825000 ; - RECT 1.625000 0.825000 1.795000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 0.090000 0.085000 0.425000 0.825000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nand4_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.165000 1.075000 4.495000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.235000 1.075000 3.080000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.075000 1.700000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.845000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 1.255500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.445000 3.925000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 2.355000 1.665000 2.685000 2.465000 ; - RECT 3.370000 1.055000 3.925000 1.445000 ; - RECT 3.595000 0.635000 3.925000 1.055000 ; - RECT 3.595000 1.665000 3.925000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.735000 ; - RECT 0.090000 0.735000 1.185000 0.905000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.935000 0.255000 2.125000 0.465000 ; - RECT 0.935000 0.465000 1.185000 0.735000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.355000 0.635000 3.085000 0.905000 ; - RECT 1.855000 1.835000 2.185000 2.635000 ; - RECT 2.315000 0.255000 4.425000 0.465000 ; - RECT 2.995000 1.835000 3.325000 2.635000 ; - RECT 3.255000 0.465000 3.425000 0.885000 ; - RECT 4.095000 0.465000 4.425000 0.905000 ; - RECT 4.095000 1.445000 4.425000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__nand4_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.465000 1.075000 7.710000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.850000 1.075000 5.565000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 1.075000 3.540000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 1.700000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 2.511000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 1.445000 7.305000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - RECT 2.195000 1.665000 2.525000 2.465000 ; - RECT 3.035000 1.665000 3.365000 2.465000 ; - RECT 4.395000 1.665000 4.725000 2.465000 ; - RECT 5.235000 1.665000 5.565000 2.465000 ; - RECT 6.110000 0.655000 7.305000 0.905000 ; - RECT 6.110000 0.905000 6.290000 1.445000 ; - RECT 6.135000 1.665000 6.465000 2.465000 ; - RECT 6.975000 1.665000 7.305000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.090000 0.255000 0.345000 0.655000 ; - RECT 0.090000 0.655000 2.025000 0.905000 ; - RECT 0.090000 1.445000 0.345000 2.635000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 1.015000 0.255000 1.185000 0.655000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.355000 0.085000 1.685000 0.485000 ; - RECT 1.855000 0.255000 3.785000 0.485000 ; - RECT 1.855000 0.485000 2.025000 0.655000 ; - RECT 1.855000 1.835000 2.025000 2.635000 ; - RECT 2.195000 0.655000 5.565000 0.905000 ; - RECT 2.695000 1.835000 2.865000 2.635000 ; - RECT 3.535000 1.835000 4.225000 2.635000 ; - RECT 3.975000 0.255000 7.730000 0.485000 ; - RECT 4.895000 1.835000 5.065000 2.635000 ; - RECT 5.770000 0.485000 5.940000 0.905000 ; - RECT 5.770000 1.835000 5.940000 2.635000 ; - RECT 6.635000 1.835000 6.805000 2.635000 ; - RECT 7.475000 0.485000 7.730000 0.905000 ; - RECT 7.475000 1.445000 7.735000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__nand4_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.325000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.925000 0.765000 2.185000 1.325000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.505000 0.765000 1.755000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.965000 0.995000 1.235000 1.325000 ; - END - END D - PIN Y - ANTENNADIFFAREA 0.887500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.130000 1.495000 3.135000 1.665000 ; - RECT 1.130000 1.665000 1.460000 2.465000 ; - RECT 2.085000 1.665000 2.415000 2.465000 ; - RECT 2.695000 0.255000 3.135000 0.825000 ; - RECT 2.925000 0.825000 3.135000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.445000 0.475000 0.655000 ; - RECT 0.085000 0.655000 1.335000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.595000 ; - RECT 0.085000 1.595000 0.510000 1.925000 ; - RECT 0.655000 0.085000 0.985000 0.485000 ; - RECT 0.710000 1.495000 0.960000 2.635000 ; - RECT 1.155000 0.425000 2.525000 0.595000 ; - RECT 1.155000 0.595000 1.335000 0.655000 ; - RECT 1.630000 1.835000 1.915000 2.635000 ; - RECT 2.355000 0.595000 2.525000 0.995000 ; - RECT 2.355000 0.995000 2.755000 1.325000 ; - RECT 2.705000 1.835000 2.920000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__nand4b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.995000 0.330000 1.615000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.010000 1.075000 3.100000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.360000 1.075000 4.450000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.620000 1.075000 5.430000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 1.255500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.455000 0.635000 1.785000 0.825000 ; - RECT 1.455000 1.445000 4.865000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.465000 ; - RECT 1.550000 0.825000 1.785000 1.445000 ; - RECT 2.295000 1.665000 2.625000 2.465000 ; - RECT 3.605000 1.665000 3.935000 2.465000 ; - RECT 4.535000 1.665000 4.865000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.090000 0.255000 0.345000 0.635000 ; - RECT 0.090000 0.635000 0.670000 0.805000 ; - RECT 0.090000 1.915000 0.670000 2.085000 ; - RECT 0.090000 2.085000 0.345000 2.465000 ; - RECT 0.500000 0.805000 0.670000 1.075000 ; - RECT 0.500000 1.075000 1.380000 1.245000 ; - RECT 0.500000 1.245000 0.670000 1.915000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.255000 1.285000 2.635000 ; - RECT 1.035000 0.255000 2.125000 0.465000 ; - RECT 1.035000 0.465000 1.285000 0.905000 ; - RECT 1.035000 1.445000 1.285000 2.255000 ; - RECT 1.955000 0.465000 2.125000 0.635000 ; - RECT 1.955000 0.635000 3.045000 0.905000 ; - RECT 1.955000 1.835000 2.125000 2.635000 ; - RECT 2.295000 0.255000 3.985000 0.465000 ; - RECT 2.795000 1.835000 3.435000 2.635000 ; - RECT 3.235000 0.635000 4.455000 0.715000 ; - RECT 3.235000 0.715000 5.340000 0.905000 ; - RECT 4.105000 1.835000 4.365000 2.635000 ; - RECT 4.155000 0.255000 4.415000 0.615000 ; - RECT 4.155000 0.615000 4.455000 0.635000 ; - RECT 4.665000 0.085000 4.835000 0.545000 ; - RECT 5.005000 0.255000 5.340000 0.715000 ; - RECT 5.035000 1.495000 5.430000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__nand4b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.440000 1.275000 ; - END - END A_N - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.930000 1.075000 4.590000 1.275000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.790000 1.075000 6.510000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.015000 1.075000 8.655000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 2.511000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.455000 0.635000 2.640000 0.905000 ; - RECT 1.455000 1.445000 8.185000 1.665000 ; - RECT 1.455000 1.665000 1.785000 2.465000 ; - RECT 2.295000 1.665000 2.625000 2.465000 ; - RECT 2.375000 0.905000 2.640000 1.445000 ; - RECT 3.135000 1.665000 3.465000 2.465000 ; - RECT 3.975000 1.665000 4.305000 2.465000 ; - RECT 5.335000 1.665000 5.665000 2.465000 ; - RECT 6.175000 1.665000 6.505000 2.465000 ; - RECT 7.015000 1.665000 7.345000 2.465000 ; - RECT 7.855000 1.665000 8.185000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.090000 0.255000 0.425000 0.735000 ; - RECT 0.090000 0.735000 0.805000 0.905000 ; - RECT 0.090000 1.495000 0.805000 1.665000 ; - RECT 0.090000 1.665000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.845000 0.545000 ; - RECT 0.595000 1.835000 1.285000 2.635000 ; - RECT 0.610000 0.905000 0.805000 1.075000 ; - RECT 0.610000 1.075000 2.205000 1.275000 ; - RECT 0.610000 1.275000 0.805000 1.495000 ; - RECT 0.995000 1.495000 1.285000 1.835000 ; - RECT 1.035000 0.255000 4.725000 0.465000 ; - RECT 1.035000 0.465000 1.285000 0.905000 ; - RECT 1.955000 1.835000 2.125000 2.635000 ; - RECT 2.795000 1.835000 2.965000 2.635000 ; - RECT 3.135000 0.635000 6.505000 0.905000 ; - RECT 3.635000 1.835000 3.805000 2.635000 ; - RECT 4.475000 1.835000 5.165000 2.635000 ; - RECT 4.915000 0.255000 6.925000 0.465000 ; - RECT 5.835000 1.835000 6.005000 2.635000 ; - RECT 6.675000 0.465000 6.925000 0.735000 ; - RECT 6.675000 0.735000 8.610000 0.905000 ; - RECT 6.675000 1.835000 6.845000 2.635000 ; - RECT 7.095000 0.085000 7.265000 0.545000 ; - RECT 7.435000 0.255000 7.765000 0.735000 ; - RECT 7.515000 1.835000 7.685000 2.635000 ; - RECT 7.935000 0.085000 8.105000 0.545000 ; - RECT 8.275000 0.255000 8.610000 0.735000 ; - RECT 8.355000 1.445000 8.610000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - END -END sky130_fd_sc_hd__nand4b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4bb_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4bb_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.390000 0.725000 3.640000 1.615000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 1.075000 0.780000 1.655000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.500000 0.735000 1.720000 1.325000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.970000 1.075000 1.320000 1.325000 ; - END - END D - PIN Y - ANTENNADIFFAREA 0.909000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.120000 1.495000 2.670000 1.665000 ; - RECT 1.120000 1.665000 1.450000 2.465000 ; - RECT 2.140000 1.665000 2.470000 2.465000 ; - RECT 2.420000 0.255000 2.930000 0.825000 ; - RECT 2.420000 0.825000 2.670000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.485000 0.425000 0.715000 ; - RECT 0.085000 0.715000 1.270000 0.905000 ; - RECT 0.085000 0.905000 0.260000 2.065000 ; - RECT 0.085000 2.065000 0.425000 2.465000 ; - RECT 0.595000 0.085000 0.900000 0.545000 ; - RECT 0.595000 1.835000 0.925000 2.635000 ; - RECT 1.080000 0.365000 2.250000 0.555000 ; - RECT 1.080000 0.555000 1.270000 0.715000 ; - RECT 1.640000 1.835000 1.970000 2.635000 ; - RECT 1.970000 0.555000 2.250000 1.325000 ; - RECT 2.680000 2.175000 3.450000 2.635000 ; - RECT 2.840000 0.995000 3.090000 1.835000 ; - RECT 2.840000 1.835000 4.055000 2.005000 ; - RECT 3.100000 0.085000 3.450000 0.545000 ; - RECT 3.620000 0.255000 4.055000 0.545000 ; - RECT 3.635000 2.005000 4.055000 2.465000 ; - RECT 3.810000 0.545000 4.055000 1.835000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__nand4bb_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4bb_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4bb_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.560000 1.170000 0.890000 1.340000 ; - RECT 0.610000 1.070000 0.890000 1.170000 ; - RECT 0.610000 1.340000 0.890000 1.615000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.070000 0.330000 1.615000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.720000 1.075000 4.615000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.945000 1.075000 5.875000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 1.255500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.085000 0.655000 2.415000 1.445000 ; - RECT 2.085000 1.445000 5.455000 1.665000 ; - RECT 2.085000 1.665000 2.335000 2.465000 ; - RECT 2.925000 1.665000 3.255000 2.465000 ; - RECT 3.245000 1.075000 3.550000 1.445000 ; - RECT 4.285000 1.665000 4.615000 2.465000 ; - RECT 5.125000 1.665000 5.455000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.730000 ; - RECT 0.085000 0.730000 1.230000 0.900000 ; - RECT 0.085000 1.785000 1.230000 1.980000 ; - RECT 0.085000 1.980000 0.370000 2.440000 ; - RECT 0.515000 0.085000 0.765000 0.545000 ; - RECT 0.540000 2.195000 0.765000 2.635000 ; - RECT 0.935000 0.255000 1.575000 0.560000 ; - RECT 0.935000 2.150000 1.575000 2.465000 ; - RECT 1.060000 0.900000 1.230000 1.785000 ; - RECT 1.400000 0.560000 1.575000 0.715000 ; - RECT 1.400000 0.715000 1.580000 1.410000 ; - RECT 1.400000 1.410000 1.575000 2.150000 ; - RECT 1.745000 0.255000 3.675000 0.485000 ; - RECT 1.745000 0.485000 1.915000 0.585000 ; - RECT 1.745000 1.495000 1.915000 2.635000 ; - RECT 2.505000 1.835000 2.755000 2.635000 ; - RECT 2.745000 1.075000 3.075000 1.275000 ; - RECT 2.925000 0.655000 4.615000 0.905000 ; - RECT 3.425000 1.835000 4.115000 2.635000 ; - RECT 3.865000 0.255000 5.035000 0.485000 ; - RECT 4.785000 0.485000 5.035000 0.735000 ; - RECT 4.785000 0.735000 5.895000 0.905000 ; - RECT 4.785000 1.835000 4.955000 2.635000 ; - RECT 5.205000 0.085000 5.375000 0.565000 ; - RECT 5.545000 0.255000 5.895000 0.735000 ; - RECT 5.625000 1.445000 5.895000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.060000 1.105000 1.230000 1.275000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.105000 3.075000 1.275000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 1.000000 1.075000 3.135000 1.305000 ; - END -END sky130_fd_sc_hd__nand4bb_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nand4bb_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nand4bb_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 0.995000 0.330000 1.615000 ; - END - END A_N - PIN B_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.590000 0.995000 0.975000 1.615000 ; - END - END B_N - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.120000 1.075000 7.910000 1.275000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.420000 1.075000 10.015000 1.275000 ; - END - END D - PIN Y - ANTENNADIFFAREA 2.511000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.540000 0.655000 3.990000 0.905000 ; - RECT 2.540000 1.445000 9.590000 1.665000 ; - RECT 2.540000 1.665000 2.790000 2.465000 ; - RECT 3.380000 1.665000 3.710000 2.465000 ; - RECT 3.700000 0.905000 3.990000 1.445000 ; - RECT 4.220000 1.665000 4.550000 2.465000 ; - RECT 5.060000 1.665000 5.390000 2.465000 ; - RECT 6.740000 1.665000 7.070000 2.465000 ; - RECT 7.580000 1.665000 7.910000 2.465000 ; - RECT 8.420000 1.665000 8.750000 2.465000 ; - RECT 9.260000 1.665000 9.590000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.635000 ; - RECT 0.085000 0.635000 1.455000 0.805000 ; - RECT 0.085000 1.785000 1.455000 1.980000 ; - RECT 0.085000 1.980000 0.370000 2.440000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.540000 2.195000 0.765000 2.635000 ; - RECT 0.935000 2.150000 1.795000 2.465000 ; - RECT 1.015000 0.255000 1.795000 0.465000 ; - RECT 1.145000 0.805000 1.455000 1.785000 ; - RECT 1.625000 0.465000 1.795000 1.075000 ; - RECT 1.625000 1.075000 2.210000 1.305000 ; - RECT 1.625000 1.305000 1.795000 2.150000 ; - RECT 2.200000 0.255000 5.810000 0.485000 ; - RECT 2.200000 0.485000 2.370000 0.905000 ; - RECT 2.200000 1.495000 2.370000 2.635000 ; - RECT 2.540000 1.075000 3.285000 1.245000 ; - RECT 2.960000 1.835000 3.210000 2.635000 ; - RECT 3.880000 1.835000 4.050000 2.635000 ; - RECT 4.160000 1.075000 5.390000 1.275000 ; - RECT 4.220000 0.655000 5.390000 0.735000 ; - RECT 4.220000 0.735000 6.150000 0.905000 ; - RECT 4.720000 1.835000 4.890000 2.635000 ; - RECT 5.610000 1.835000 6.540000 2.635000 ; - RECT 5.980000 0.255000 7.910000 0.485000 ; - RECT 5.980000 0.485000 6.150000 0.735000 ; - RECT 6.320000 0.655000 10.035000 0.905000 ; - RECT 7.240000 1.835000 7.410000 2.635000 ; - RECT 8.080000 1.835000 8.250000 2.635000 ; - RECT 8.420000 0.085000 8.750000 0.485000 ; - RECT 8.920000 1.835000 9.090000 2.635000 ; - RECT 9.260000 0.085000 9.590000 0.485000 ; - RECT 9.760000 1.445000 10.035000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.980000 1.105000 2.150000 1.275000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.280000 1.105000 4.450000 1.275000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - LAYER met1 ; - RECT 1.920000 1.075000 2.210000 1.120000 ; - RECT 1.920000 1.120000 4.510000 1.260000 ; - RECT 1.920000 1.260000 2.210000 1.305000 ; - RECT 4.220000 1.075000 4.510000 1.120000 ; - RECT 4.220000 1.260000 4.510000 1.305000 ; - END -END sky130_fd_sc_hd__nand4bb_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.380000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 1.075000 1.295000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.435000 1.325000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.435500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 1.495000 0.775000 1.665000 ; - RECT 0.095000 1.665000 0.425000 2.450000 ; - RECT 0.515000 0.255000 0.845000 0.895000 ; - RECT 0.605000 0.895000 0.775000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.380000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.570000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.380000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.380000 0.085000 ; - RECT 0.000000 2.635000 1.380000 2.805000 ; - RECT 0.105000 0.085000 0.345000 0.895000 ; - RECT 0.955000 1.495000 1.285000 2.635000 ; - RECT 1.015000 0.085000 1.285000 0.895000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - END -END sky130_fd_sc_hd__nor2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.810000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.980000 1.075000 1.750000 1.275000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.621000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 1.705000 0.735000 ; - RECT 0.535000 0.735000 2.135000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 1.375000 1.445000 2.135000 1.665000 ; - RECT 1.375000 1.665000 1.705000 2.125000 ; - RECT 1.920000 0.905000 2.135000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.090000 1.455000 1.205000 1.665000 ; - RECT 0.090000 1.665000 0.365000 2.465000 ; - RECT 0.535000 1.835000 0.865000 2.635000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.035000 1.665000 1.205000 2.295000 ; - RECT 1.035000 2.295000 2.175000 2.465000 ; - RECT 1.875000 0.085000 2.165000 0.555000 ; - RECT 1.875000 1.835000 2.175000 2.295000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nor2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.140000 1.075000 1.800000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.120000 1.075000 3.485000 1.275000 ; - END - END B - PIN Y - ANTENNADIFFAREA 1.242000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 4.055000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 2.295000 1.445000 4.055000 1.745000 ; - RECT 2.295000 1.745000 2.465000 2.125000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 3.135000 1.745000 3.305000 2.125000 ; - RECT 3.655000 0.905000 4.055000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.090000 1.455000 2.125000 1.665000 ; - RECT 0.090000 1.665000 0.365000 2.465000 ; - RECT 0.535000 1.835000 0.865000 2.635000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.035000 1.665000 1.205000 2.465000 ; - RECT 1.375000 1.835000 1.625000 2.635000 ; - RECT 1.795000 1.665000 2.125000 2.295000 ; - RECT 1.795000 2.295000 3.890000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.635000 1.935000 2.965000 2.295000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 3.475000 1.915000 3.890000 2.295000 ; - RECT 3.555000 0.085000 3.840000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__nor2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.360000 1.075000 3.530000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.800000 1.075000 6.540000 1.275000 ; - END - END B - PIN Y - ANTENNADIFFAREA 2.484000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 7.275000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 3.895000 0.255000 4.225000 0.725000 ; - RECT 3.935000 1.445000 7.275000 1.615000 ; - RECT 3.935000 1.615000 4.185000 2.125000 ; - RECT 4.735000 0.255000 5.065000 0.725000 ; - RECT 4.775000 1.615000 5.025000 2.125000 ; - RECT 5.575000 0.255000 5.905000 0.725000 ; - RECT 5.615000 1.615000 5.865000 2.125000 ; - RECT 6.415000 0.255000 6.745000 0.725000 ; - RECT 6.455000 1.615000 6.705000 2.125000 ; - RECT 6.710000 0.905000 7.275000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.090000 1.455000 3.765000 1.665000 ; - RECT 0.090000 1.665000 0.405000 2.465000 ; - RECT 0.575000 1.835000 0.825000 2.635000 ; - RECT 0.995000 1.665000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.835000 1.665000 2.635000 ; - RECT 1.835000 1.665000 2.085000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.255000 1.835000 2.505000 2.635000 ; - RECT 2.675000 1.665000 2.925000 2.465000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 3.095000 1.835000 3.345000 2.635000 ; - RECT 3.515000 1.665000 3.765000 2.295000 ; - RECT 3.515000 2.295000 7.125000 2.465000 ; - RECT 3.555000 0.085000 3.725000 0.555000 ; - RECT 4.355000 1.785000 4.605000 2.295000 ; - RECT 4.395000 0.085000 4.565000 0.555000 ; - RECT 5.195000 1.785000 5.445000 2.295000 ; - RECT 5.235000 0.085000 5.405000 0.555000 ; - RECT 6.035000 1.785000 6.285000 2.295000 ; - RECT 6.075000 0.085000 6.245000 0.555000 ; - RECT 6.875000 1.785000 7.125000 2.295000 ; - RECT 6.915000 0.085000 7.205000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__nor2_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.960000 1.065000 1.325000 1.325000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 0.725000 0.325000 1.325000 ; - END - END B_N - PIN Y - ANTENNADIFFAREA 0.435500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.235000 0.255000 1.565000 0.725000 ; - RECT 1.235000 0.725000 2.215000 0.895000 ; - RECT 1.655000 1.850000 2.215000 2.465000 ; - RECT 2.035000 0.895000 2.215000 1.850000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.330000 0.370000 0.675000 0.545000 ; - RECT 0.415000 1.510000 1.705000 1.680000 ; - RECT 0.415000 1.680000 0.675000 1.905000 ; - RECT 0.495000 0.545000 0.675000 1.510000 ; - RECT 0.855000 0.085000 1.065000 0.895000 ; - RECT 0.875000 1.855000 1.205000 2.635000 ; - RECT 1.535000 1.075000 1.865000 1.245000 ; - RECT 1.535000 1.245000 1.705000 1.510000 ; - RECT 1.735000 0.085000 2.120000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nor2b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.480000 1.065000 0.920000 1.275000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.600000 1.065000 3.125000 1.275000 ; - RECT 2.910000 1.275000 3.125000 1.965000 ; - END - END B_N - PIN Y - ANTENNADIFFAREA 0.621000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 1.705000 0.895000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 1.415000 0.895000 1.665000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.365000 0.895000 ; - RECT 0.085000 1.445000 1.245000 1.655000 ; - RECT 0.085000 1.655000 0.405000 2.465000 ; - RECT 0.575000 1.825000 0.825000 2.635000 ; - RECT 0.995000 1.655000 1.245000 2.295000 ; - RECT 0.995000 2.295000 2.125000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.835000 1.445000 2.090000 1.890000 ; - RECT 1.835000 1.890000 2.125000 2.295000 ; - RECT 1.875000 0.085000 2.045000 0.895000 ; - RECT 1.875000 1.075000 2.430000 1.245000 ; - RECT 2.215000 0.725000 2.565000 0.895000 ; - RECT 2.215000 0.895000 2.430000 1.075000 ; - RECT 2.260000 1.245000 2.430000 1.445000 ; - RECT 2.260000 1.445000 2.565000 1.615000 ; - RECT 2.395000 0.445000 2.565000 0.725000 ; - RECT 2.395000 1.615000 2.565000 2.460000 ; - RECT 2.775000 0.085000 3.030000 0.845000 ; - RECT 2.775000 2.145000 3.025000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__nor2b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor2b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor2b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.360000 1.075000 1.800000 1.275000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.445000 1.075000 4.975000 1.320000 ; - END - END B_N - PIN Y - ANTENNADIFFAREA 1.242000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 3.385000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 2.295000 0.905000 2.625000 1.445000 ; - RECT 2.295000 1.445000 3.305000 1.745000 ; - RECT 2.295000 1.745000 2.465000 2.125000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 3.135000 1.745000 3.305000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.085000 0.365000 0.905000 ; - RECT 0.085000 1.455000 2.125000 1.665000 ; - RECT 0.085000 1.665000 0.365000 2.465000 ; - RECT 0.535000 1.835000 0.865000 2.635000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.035000 1.665000 1.205000 2.465000 ; - RECT 1.375000 1.835000 1.625000 2.635000 ; - RECT 1.795000 1.665000 2.125000 2.295000 ; - RECT 1.795000 2.295000 3.855000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.635000 1.935000 2.965000 2.295000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 2.795000 1.075000 4.275000 1.275000 ; - RECT 3.475000 1.575000 3.855000 2.295000 ; - RECT 3.555000 0.085000 3.845000 0.905000 ; - RECT 4.025000 0.255000 4.355000 0.815000 ; - RECT 4.025000 0.815000 4.275000 1.075000 ; - RECT 4.025000 1.275000 4.275000 1.575000 ; - RECT 4.025000 1.575000 4.355000 2.465000 ; - RECT 4.525000 0.085000 4.815000 0.905000 ; - RECT 4.525000 1.495000 4.930000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__nor2b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.485000 0.655000 1.755000 1.665000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.995000 0.975000 1.325000 ; - RECT 0.595000 1.325000 0.830000 2.005000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.995000 0.425000 1.325000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.604500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.385000 0.345000 0.655000 ; - RECT 0.090000 0.655000 1.315000 0.825000 ; - RECT 0.090000 1.495000 0.425000 2.280000 ; - RECT 0.090000 2.280000 1.170000 2.450000 ; - RECT 1.000000 1.495000 1.315000 1.665000 ; - RECT 1.000000 1.665000 1.170000 2.280000 ; - RECT 1.015000 0.385000 1.185000 0.655000 ; - RECT 1.145000 0.825000 1.315000 1.495000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.515000 0.085000 0.845000 0.485000 ; - RECT 1.355000 0.085000 1.685000 0.485000 ; - RECT 1.435000 1.835000 1.750000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__nor3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.135000 1.075000 0.965000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.135000 1.075000 2.185000 1.285000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.375000 1.075000 2.965000 1.285000 ; - RECT 2.375000 1.285000 2.640000 1.625000 ; - END - END C - PIN Y - ANTENNADIFFAREA 0.796500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 3.595000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.755000 0.255000 3.085000 0.725000 ; - RECT 2.835000 1.455000 3.595000 1.625000 ; - RECT 2.835000 1.625000 3.045000 2.125000 ; - RECT 3.135000 0.905000 3.595000 1.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.150000 1.455000 2.085000 1.625000 ; - RECT 0.150000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.795000 1.665000 2.295000 ; - RECT 1.415000 2.295000 3.465000 2.465000 ; - RECT 1.835000 1.625000 2.085000 2.125000 ; - RECT 1.875000 0.085000 2.585000 0.555000 ; - RECT 2.415000 1.795000 2.625000 2.295000 ; - RECT 3.215000 1.795000 3.465000 2.295000 ; - RECT 3.255000 0.085000 3.545000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__nor3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 1.825000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.095000 1.075000 3.685000 1.285000 ; - RECT 3.515000 1.285000 3.685000 1.445000 ; - RECT 3.515000 1.445000 5.165000 1.615000 ; - RECT 4.995000 1.075000 5.415000 1.285000 ; - RECT 4.995000 1.285000 5.165000 1.445000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.855000 1.075000 4.765000 1.275000 ; - END - END C - PIN Y - ANTENNADIFFAREA 1.593000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 5.895000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 3.515000 1.785000 5.895000 1.955000 ; - RECT 3.515000 1.955000 4.605000 1.965000 ; - RECT 3.515000 1.965000 3.765000 2.125000 ; - RECT 3.895000 0.255000 4.225000 0.725000 ; - RECT 4.355000 1.965000 4.605000 2.125000 ; - RECT 4.735000 0.255000 5.065000 0.725000 ; - RECT 5.605000 0.255000 5.895000 0.725000 ; - RECT 5.605000 0.905000 5.895000 1.785000 ; - RECT 5.615000 1.955000 5.895000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.150000 1.455000 2.085000 1.625000 ; - RECT 0.150000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.795000 1.665000 2.635000 ; - RECT 1.835000 1.625000 2.085000 2.085000 ; - RECT 1.835000 2.085000 2.925000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.255000 1.455000 3.345000 1.625000 ; - RECT 2.255000 1.625000 2.505000 1.915000 ; - RECT 2.675000 1.795000 2.925000 2.085000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 3.095000 1.625000 3.345000 2.295000 ; - RECT 3.095000 2.295000 5.025000 2.465000 ; - RECT 3.555000 0.085000 3.725000 0.555000 ; - RECT 3.935000 2.135000 4.185000 2.295000 ; - RECT 4.395000 0.085000 4.565000 0.555000 ; - RECT 4.775000 2.135000 5.025000 2.295000 ; - RECT 5.195000 2.125000 5.445000 2.465000 ; - RECT 5.235000 0.085000 5.405000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.125000 2.615000 2.295000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.125000 5.375000 2.295000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 2.385000 2.065000 2.680000 2.140000 ; - RECT 2.385000 2.140000 5.440000 2.280000 ; - RECT 2.385000 2.280000 2.680000 2.335000 ; - RECT 5.145000 2.065000 5.440000 2.140000 ; - RECT 5.145000 2.280000 5.440000 2.335000 ; - END -END sky130_fd_sc_hd__nor3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.475000 0.995000 1.815000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 0.995000 1.305000 1.615000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.995000 2.335000 1.615000 ; - END - END C_N - PIN Y - ANTENNADIFFAREA 0.716500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.605000 0.655000 ; - RECT 0.085000 0.655000 1.445000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.445000 ; - RECT 0.085000 1.445000 0.545000 2.455000 ; - RECT 1.275000 0.310000 1.445000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.425000 1.075000 0.885000 1.245000 ; - RECT 0.715000 1.245000 0.885000 1.785000 ; - RECT 0.715000 1.785000 2.675000 1.955000 ; - RECT 0.775000 0.085000 1.105000 0.485000 ; - RECT 1.615000 0.085000 1.945000 0.825000 ; - RECT 1.615000 2.125000 1.945000 2.635000 ; - RECT 2.180000 0.405000 2.350000 0.655000 ; - RECT 2.180000 0.655000 2.675000 0.825000 ; - RECT 2.505000 0.825000 2.675000 1.785000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__nor3b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.965000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.135000 1.075000 2.640000 1.285000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.030000 1.075000 4.515000 1.285000 ; - END - END C_N - PIN Y - ANTENNADIFFAREA 0.796500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 3.105000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.775000 0.255000 3.105000 0.725000 ; - RECT 2.815000 0.905000 3.065000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.090000 1.455000 2.085000 1.625000 ; - RECT 0.090000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.795000 1.665000 2.295000 ; - RECT 1.415000 2.295000 3.480000 2.465000 ; - RECT 1.835000 1.625000 2.085000 2.125000 ; - RECT 1.875000 0.085000 2.605000 0.555000 ; - RECT 2.375000 1.455000 2.645000 2.295000 ; - RECT 3.235000 1.075000 3.860000 1.285000 ; - RECT 3.235000 1.455000 3.480000 2.295000 ; - RECT 3.275000 0.085000 3.480000 0.895000 ; - RECT 3.690000 0.380000 4.045000 0.905000 ; - RECT 3.690000 0.905000 3.860000 1.075000 ; - RECT 3.690000 1.285000 3.860000 1.455000 ; - RECT 3.690000 1.455000 4.045000 1.870000 ; - RECT 4.215000 0.085000 4.505000 0.825000 ; - RECT 4.215000 1.540000 4.465000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__nor3b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor3b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor3b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.035000 1.075000 2.690000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.035000 1.075000 4.300000 1.285000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.445000 1.285000 ; - END - END C_N - PIN Y - ANTENNADIFFAREA 1.593000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.955000 0.255000 1.285000 0.725000 ; - RECT 0.955000 0.725000 6.760000 0.905000 ; - RECT 1.795000 0.255000 2.125000 0.725000 ; - RECT 3.155000 0.255000 3.485000 0.725000 ; - RECT 3.995000 0.255000 4.325000 0.725000 ; - RECT 4.835000 0.255000 5.165000 0.725000 ; - RECT 4.875000 1.455000 6.760000 1.625000 ; - RECT 4.875000 1.625000 5.125000 2.125000 ; - RECT 5.675000 0.255000 6.005000 0.725000 ; - RECT 5.715000 1.625000 5.965000 2.125000 ; - RECT 6.420000 0.905000 6.760000 1.455000 ; - RECT 6.515000 0.315000 6.760000 0.725000 ; - RECT 6.555000 1.625000 6.760000 2.415000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.110000 0.255000 0.445000 0.735000 ; - RECT 0.110000 0.735000 0.785000 0.905000 ; - RECT 0.110000 1.455000 4.705000 1.625000 ; - RECT 0.110000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.615000 0.085000 0.785000 0.555000 ; - RECT 0.615000 0.905000 0.785000 1.455000 ; - RECT 0.995000 1.795000 4.285000 1.965000 ; - RECT 0.995000 1.965000 1.245000 2.465000 ; - RECT 1.415000 2.135000 1.665000 2.635000 ; - RECT 1.455000 0.085000 1.625000 0.555000 ; - RECT 1.835000 1.965000 2.085000 2.465000 ; - RECT 2.255000 2.135000 2.505000 2.635000 ; - RECT 2.295000 0.085000 2.985000 0.555000 ; - RECT 2.775000 2.135000 3.025000 2.295000 ; - RECT 2.775000 2.295000 6.385000 2.465000 ; - RECT 3.195000 1.965000 3.445000 2.125000 ; - RECT 3.615000 2.135000 3.865000 2.295000 ; - RECT 3.655000 0.085000 3.825000 0.555000 ; - RECT 4.035000 1.965000 4.285000 2.125000 ; - RECT 4.455000 1.795000 4.705000 2.295000 ; - RECT 4.495000 0.085000 4.665000 0.555000 ; - RECT 4.535000 1.075000 6.125000 1.285000 ; - RECT 4.535000 1.285000 4.705000 1.455000 ; - RECT 5.295000 1.795000 5.545000 2.295000 ; - RECT 5.335000 0.085000 5.505000 0.555000 ; - RECT 6.135000 1.795000 6.385000 2.295000 ; - RECT 6.175000 0.085000 6.345000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - END -END sky130_fd_sc_hd__nor3b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.955000 0.655000 2.215000 1.665000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.245000 1.075000 1.695000 1.245000 ; - RECT 1.455000 1.245000 1.695000 2.450000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.845000 0.995000 1.075000 1.415000 ; - RECT 0.845000 1.415000 1.285000 1.615000 ; - RECT 1.030000 1.615000 1.285000 2.450000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.745000 0.335000 1.325000 ; - END - END D - PIN Y - ANTENNADIFFAREA 0.672750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.495000 0.675000 1.665000 ; - RECT 0.090000 1.665000 0.425000 2.450000 ; - RECT 0.505000 0.645000 0.860000 0.655000 ; - RECT 0.505000 0.655000 1.705000 0.825000 ; - RECT 0.505000 0.825000 0.675000 1.495000 ; - RECT 0.595000 0.385000 0.860000 0.645000 ; - RECT 1.535000 0.385000 1.705000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.575000 ; - RECT 1.035000 0.085000 1.365000 0.485000 ; - RECT 1.875000 0.085000 2.205000 0.485000 ; - RECT 1.955000 1.835000 2.215000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__nor4_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.200000 1.075000 0.965000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.135000 1.075000 1.940000 1.285000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.210000 1.075000 3.105000 1.285000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.340000 1.075000 3.925000 1.285000 ; - END - END D - PIN Y - ANTENNADIFFAREA 0.972000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 4.515000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.775000 0.255000 3.105000 0.725000 ; - RECT 3.615000 0.255000 3.945000 0.725000 ; - RECT 3.655000 1.455000 4.515000 1.625000 ; - RECT 3.655000 1.625000 3.905000 2.125000 ; - RECT 4.180000 0.905000 4.515000 1.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.150000 1.455000 2.085000 1.625000 ; - RECT 0.150000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.795000 1.665000 2.295000 ; - RECT 1.415000 2.295000 3.065000 2.465000 ; - RECT 1.835000 1.625000 2.085000 2.125000 ; - RECT 1.875000 0.085000 2.605000 0.555000 ; - RECT 2.395000 1.455000 3.485000 1.625000 ; - RECT 2.395000 1.625000 2.645000 2.125000 ; - RECT 2.815000 1.795000 3.065000 2.295000 ; - RECT 3.235000 1.625000 3.485000 2.295000 ; - RECT 3.235000 2.295000 4.325000 2.465000 ; - RECT 3.275000 0.085000 3.445000 0.555000 ; - RECT 4.075000 1.795000 4.325000 2.295000 ; - RECT 4.115000 0.085000 4.405000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__nor4_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.180000 1.075000 1.825000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.095000 1.075000 4.070000 1.285000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.295000 1.075000 5.705000 1.285000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.875000 1.075000 7.295000 1.285000 ; - END - END D - PIN Y - ANTENNADIFFAREA 1.944000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.865000 0.725000 ; - RECT 0.535000 0.725000 7.735000 0.905000 ; - RECT 1.375000 0.255000 1.705000 0.725000 ; - RECT 2.215000 0.255000 2.545000 0.725000 ; - RECT 3.055000 0.255000 3.385000 0.725000 ; - RECT 4.415000 0.255000 4.745000 0.725000 ; - RECT 5.255000 0.255000 5.585000 0.725000 ; - RECT 6.095000 0.255000 6.425000 0.725000 ; - RECT 6.135000 1.455000 7.735000 1.625000 ; - RECT 6.135000 1.625000 6.385000 2.125000 ; - RECT 6.935000 0.255000 7.265000 0.725000 ; - RECT 6.975000 1.625000 7.225000 2.125000 ; - RECT 7.465000 0.905000 7.735000 1.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.090000 0.085000 0.365000 0.905000 ; - RECT 0.090000 1.455000 2.085000 1.625000 ; - RECT 0.090000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.465000 ; - RECT 1.035000 0.085000 1.205000 0.555000 ; - RECT 1.415000 1.795000 1.665000 2.635000 ; - RECT 1.835000 1.625000 2.085000 2.295000 ; - RECT 1.835000 2.295000 3.820000 2.465000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.255000 1.455000 5.545000 1.625000 ; - RECT 2.255000 1.625000 2.505000 2.125000 ; - RECT 2.675000 1.795000 2.925000 2.295000 ; - RECT 2.715000 0.085000 2.885000 0.555000 ; - RECT 3.095000 1.625000 3.345000 2.125000 ; - RECT 3.515000 1.795000 3.820000 2.295000 ; - RECT 3.555000 0.085000 4.245000 0.555000 ; - RECT 4.005000 1.795000 4.285000 2.295000 ; - RECT 4.005000 2.295000 7.645000 2.465000 ; - RECT 4.455000 1.625000 4.705000 2.125000 ; - RECT 4.875000 1.795000 5.125000 2.295000 ; - RECT 4.915000 0.085000 5.085000 0.555000 ; - RECT 5.295000 1.625000 5.545000 2.125000 ; - RECT 5.715000 1.795000 5.965000 2.295000 ; - RECT 5.755000 0.085000 5.925000 0.555000 ; - RECT 6.555000 1.795000 6.805000 2.295000 ; - RECT 6.595000 0.085000 6.765000 0.555000 ; - RECT 7.395000 1.795000 7.645000 2.295000 ; - RECT 7.435000 0.085000 7.605000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__nor4_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.955000 0.995000 2.275000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.455000 0.995000 1.785000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.985000 0.995000 1.285000 1.615000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 0.995000 2.795000 1.615000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 0.871000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.655000 1.925000 0.825000 ; - RECT 0.085000 0.825000 0.345000 2.450000 ; - RECT 0.855000 0.300000 1.055000 0.655000 ; - RECT 1.725000 0.310000 1.925000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.355000 0.085000 0.685000 0.480000 ; - RECT 0.525000 0.995000 0.745000 1.795000 ; - RECT 0.525000 1.795000 3.135000 2.005000 ; - RECT 1.225000 0.085000 1.555000 0.485000 ; - RECT 2.095000 0.085000 2.425000 0.825000 ; - RECT 2.095000 2.185000 2.425000 2.635000 ; - RECT 2.660000 0.405000 2.830000 0.655000 ; - RECT 2.660000 0.655000 3.135000 0.825000 ; - RECT 2.965000 0.825000 3.135000 1.795000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__nor4b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.100000 1.075000 1.240000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.420000 1.075000 2.635000 1.285000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.815000 1.075000 3.535000 1.285000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.805000 1.075000 5.435000 1.285000 ; - RECT 5.185000 1.285000 5.435000 1.955000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 0.972000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.845000 0.725000 ; - RECT 0.515000 0.725000 3.920000 0.905000 ; - RECT 1.355000 0.255000 1.685000 0.725000 ; - RECT 2.750000 0.255000 3.080000 0.725000 ; - RECT 3.590000 0.255000 3.920000 0.725000 ; - RECT 3.630000 1.455000 4.035000 1.625000 ; - RECT 3.630000 1.625000 3.880000 2.125000 ; - RECT 3.715000 0.905000 3.920000 1.075000 ; - RECT 3.715000 1.075000 4.035000 1.455000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.905000 ; - RECT 0.085000 1.455000 2.105000 1.625000 ; - RECT 0.085000 1.625000 0.425000 2.465000 ; - RECT 0.595000 1.795000 0.805000 2.635000 ; - RECT 0.975000 1.625000 1.225000 2.465000 ; - RECT 1.015000 0.085000 1.185000 0.555000 ; - RECT 1.395000 1.795000 1.605000 2.295000 ; - RECT 1.395000 2.295000 3.040000 2.465000 ; - RECT 1.775000 1.625000 2.105000 2.125000 ; - RECT 1.855000 0.085000 2.580000 0.555000 ; - RECT 2.275000 1.455000 3.460000 1.625000 ; - RECT 2.275000 1.625000 2.660000 2.125000 ; - RECT 2.830000 1.795000 3.040000 2.295000 ; - RECT 3.210000 1.625000 3.460000 2.295000 ; - RECT 3.210000 2.295000 4.295000 2.465000 ; - RECT 3.250000 0.085000 3.420000 0.555000 ; - RECT 4.050000 1.795000 4.295000 2.295000 ; - RECT 4.090000 0.085000 4.295000 0.895000 ; - RECT 4.320000 1.075000 4.635000 1.245000 ; - RECT 4.465000 0.380000 4.820000 0.905000 ; - RECT 4.465000 0.905000 4.635000 1.075000 ; - RECT 4.465000 1.245000 4.635000 2.035000 ; - RECT 4.465000 2.035000 4.820000 2.450000 ; - RECT 4.990000 0.085000 5.240000 0.825000 ; - RECT 4.990000 2.135000 5.240000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__nor4b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.395000 1.075000 1.805000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.075000 1.075000 3.750000 1.285000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.985000 1.075000 5.685000 1.285000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.810000 1.075000 8.655000 1.285000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 1.944000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.845000 0.725000 ; - RECT 0.515000 0.725000 7.245000 0.905000 ; - RECT 1.355000 0.255000 1.685000 0.725000 ; - RECT 2.195000 0.255000 2.525000 0.725000 ; - RECT 3.035000 0.255000 3.365000 0.725000 ; - RECT 4.395000 0.255000 4.725000 0.725000 ; - RECT 5.235000 0.255000 5.565000 0.725000 ; - RECT 6.075000 0.255000 6.405000 0.725000 ; - RECT 6.115000 0.905000 6.465000 1.455000 ; - RECT 6.115000 1.455000 7.205000 1.625000 ; - RECT 6.115000 1.625000 6.365000 2.125000 ; - RECT 6.915000 0.255000 7.245000 0.725000 ; - RECT 6.955000 1.625000 7.205000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.095000 1.455000 2.065000 1.625000 ; - RECT 0.095000 1.625000 0.425000 2.465000 ; - RECT 0.175000 0.085000 0.345000 0.895000 ; - RECT 0.595000 1.795000 0.805000 2.635000 ; - RECT 0.975000 1.625000 1.225000 2.465000 ; - RECT 1.015000 0.085000 1.185000 0.555000 ; - RECT 1.395000 1.795000 1.645000 2.635000 ; - RECT 1.815000 1.625000 2.065000 2.295000 ; - RECT 1.815000 2.295000 3.745000 2.465000 ; - RECT 1.855000 0.085000 2.025000 0.555000 ; - RECT 2.235000 1.455000 5.525000 1.625000 ; - RECT 2.235000 1.625000 2.485000 2.125000 ; - RECT 2.655000 1.795000 2.905000 2.295000 ; - RECT 2.695000 0.085000 2.865000 0.555000 ; - RECT 3.075000 1.625000 3.325000 2.125000 ; - RECT 3.495000 1.795000 3.745000 2.295000 ; - RECT 3.535000 0.085000 4.225000 0.555000 ; - RECT 4.015000 1.795000 4.265000 2.295000 ; - RECT 4.015000 2.295000 7.625000 2.465000 ; - RECT 4.435000 1.625000 4.685000 2.125000 ; - RECT 4.855000 1.795000 5.105000 2.295000 ; - RECT 4.895000 0.085000 5.065000 0.555000 ; - RECT 5.275000 1.625000 5.525000 2.125000 ; - RECT 5.695000 1.455000 5.945000 2.295000 ; - RECT 5.735000 0.085000 5.905000 0.555000 ; - RECT 6.535000 1.795000 6.785000 2.295000 ; - RECT 6.575000 0.085000 6.745000 0.555000 ; - RECT 6.635000 1.075000 7.640000 1.285000 ; - RECT 7.375000 1.795000 7.625000 2.295000 ; - RECT 7.415000 0.085000 7.585000 0.555000 ; - RECT 7.470000 0.735000 8.185000 0.905000 ; - RECT 7.470000 0.905000 7.640000 1.075000 ; - RECT 7.470000 1.285000 7.640000 1.455000 ; - RECT 7.470000 1.455000 8.185000 1.625000 ; - RECT 7.810000 0.255000 8.185000 0.735000 ; - RECT 7.850000 1.625000 8.185000 2.465000 ; - RECT 8.355000 0.085000 8.585000 0.905000 ; - RECT 8.355000 1.455000 8.585000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - END -END sky130_fd_sc_hd__nor4b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4bb_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4bb_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.115000 0.995000 3.595000 1.275000 ; - RECT 3.295000 1.275000 3.595000 1.705000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.615000 0.995000 2.945000 1.445000 ; - RECT 2.615000 1.445000 3.085000 1.630000 ; - RECT 2.825000 1.630000 3.085000 2.410000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 0.995000 0.780000 1.695000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.995000 1.240000 1.325000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 0.606900 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.470000 1.955000 2.055000 2.125000 ; - RECT 1.855000 0.655000 3.085000 0.825000 ; - RECT 1.855000 0.825000 2.055000 1.955000 ; - RECT 2.015000 0.300000 2.215000 0.655000 ; - RECT 2.885000 0.310000 3.085000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.450000 0.405000 0.825000 ; - RECT 0.085000 0.825000 0.260000 1.885000 ; - RECT 0.085000 1.885000 1.205000 2.070000 ; - RECT 0.085000 2.070000 0.345000 2.455000 ; - RECT 0.515000 2.240000 0.845000 2.635000 ; - RECT 0.655000 0.085000 0.825000 0.825000 ; - RECT 0.995000 1.525000 1.590000 1.715000 ; - RECT 1.035000 2.070000 1.205000 2.295000 ; - RECT 1.035000 2.295000 2.395000 2.465000 ; - RECT 1.075000 0.450000 1.245000 0.655000 ; - RECT 1.075000 0.655000 1.590000 0.825000 ; - RECT 1.410000 0.825000 1.590000 0.995000 ; - RECT 1.410000 0.995000 1.685000 1.325000 ; - RECT 1.410000 1.325000 1.590000 1.525000 ; - RECT 1.515000 0.085000 1.845000 0.480000 ; - RECT 2.225000 0.995000 2.395000 2.295000 ; - RECT 2.385000 0.085000 2.715000 0.485000 ; - RECT 3.255000 0.085000 3.585000 0.825000 ; - RECT 3.255000 1.875000 3.585000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__nor4bb_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4bb_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4bb_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.130000 1.075000 5.895000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.165000 1.075000 4.960000 1.275000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.995000 1.235000 1.325000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.780000 1.695000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 0.972000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.060000 0.255000 2.390000 0.725000 ; - RECT 2.060000 0.725000 5.450000 0.905000 ; - RECT 2.900000 0.255000 3.230000 0.725000 ; - RECT 2.900000 1.445000 3.995000 1.705000 ; - RECT 3.575000 0.905000 3.995000 1.445000 ; - RECT 4.280000 0.255000 4.610000 0.725000 ; - RECT 5.120000 0.255000 5.450000 0.725000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.450000 0.465000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.885000 ; - RECT 0.085000 1.885000 1.915000 2.055000 ; - RECT 0.085000 2.055000 0.345000 2.455000 ; - RECT 0.515000 2.240000 0.845000 2.635000 ; - RECT 0.635000 0.085000 0.805000 0.825000 ; - RECT 0.995000 1.525000 1.575000 1.715000 ; - RECT 1.055000 0.450000 1.250000 0.655000 ; - RECT 1.055000 0.655000 1.575000 0.825000 ; - RECT 1.405000 0.825000 1.575000 1.075000 ; - RECT 1.405000 1.075000 2.390000 1.245000 ; - RECT 1.405000 1.245000 1.575000 1.525000 ; - RECT 1.560000 0.085000 1.890000 0.480000 ; - RECT 1.640000 2.225000 1.970000 2.295000 ; - RECT 1.640000 2.295000 3.650000 2.465000 ; - RECT 1.745000 1.415000 2.730000 1.585000 ; - RECT 1.745000 1.585000 1.915000 1.885000 ; - RECT 2.140000 1.795000 2.310000 1.875000 ; - RECT 2.140000 1.875000 4.610000 2.045000 ; - RECT 2.140000 2.045000 2.310000 2.125000 ; - RECT 2.480000 2.215000 3.650000 2.295000 ; - RECT 2.560000 0.085000 2.730000 0.555000 ; - RECT 2.560000 1.075000 3.405000 1.275000 ; - RECT 2.560000 1.275000 2.730000 1.415000 ; - RECT 3.400000 0.085000 4.110000 0.555000 ; - RECT 3.860000 2.215000 4.990000 2.465000 ; - RECT 4.320000 1.455000 4.610000 1.875000 ; - RECT 4.780000 0.085000 4.950000 0.555000 ; - RECT 4.780000 1.455000 5.870000 1.625000 ; - RECT 4.780000 1.625000 4.990000 2.215000 ; - RECT 5.160000 1.795000 5.370000 2.635000 ; - RECT 5.540000 1.625000 5.870000 2.465000 ; - RECT 5.620000 0.085000 5.895000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__nor4bb_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__nor4bb_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__nor4bb_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.375000 1.075000 9.110000 1.285000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.150000 1.075000 7.105000 1.285000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 0.445000 1.365000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.955000 1.075000 1.295000 1.325000 ; - END - END D_N - PIN Y - ANTENNADIFFAREA 1.944000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.840000 1.415000 3.185000 1.705000 ; - RECT 1.935000 0.255000 2.265000 0.725000 ; - RECT 1.935000 0.725000 8.665000 0.905000 ; - RECT 2.775000 0.255000 3.105000 0.725000 ; - RECT 3.015000 0.905000 3.185000 1.415000 ; - RECT 3.615000 0.255000 3.945000 0.725000 ; - RECT 4.455000 0.255000 4.785000 0.725000 ; - RECT 5.815000 0.255000 6.145000 0.725000 ; - RECT 6.655000 0.255000 6.985000 0.725000 ; - RECT 7.495000 0.255000 7.825000 0.725000 ; - RECT 8.335000 0.255000 8.665000 0.725000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.085000 0.255000 0.445000 0.725000 ; - RECT 0.085000 0.725000 0.785000 0.895000 ; - RECT 0.085000 1.535000 0.785000 1.875000 ; - RECT 0.085000 1.875000 3.525000 2.045000 ; - RECT 0.085000 2.045000 0.365000 2.465000 ; - RECT 0.535000 2.215000 0.865000 2.635000 ; - RECT 0.615000 0.085000 0.785000 0.555000 ; - RECT 0.615000 0.895000 0.785000 1.535000 ; - RECT 0.955000 0.255000 1.285000 0.735000 ; - RECT 0.955000 0.735000 1.635000 0.905000 ; - RECT 0.955000 1.535000 1.635000 1.705000 ; - RECT 1.465000 0.905000 1.635000 1.075000 ; - RECT 1.465000 1.075000 2.845000 1.245000 ; - RECT 1.465000 1.245000 1.635000 1.535000 ; - RECT 1.515000 2.215000 3.525000 2.295000 ; - RECT 1.515000 2.295000 5.195000 2.465000 ; - RECT 1.595000 0.085000 1.765000 0.555000 ; - RECT 2.435000 0.085000 2.605000 0.555000 ; - RECT 3.275000 0.085000 3.445000 0.555000 ; - RECT 3.355000 1.075000 4.905000 1.285000 ; - RECT 3.355000 1.285000 3.525000 1.875000 ; - RECT 3.695000 1.455000 6.945000 1.625000 ; - RECT 3.695000 1.625000 3.905000 2.125000 ; - RECT 4.075000 1.795000 4.325000 2.295000 ; - RECT 4.115000 0.085000 4.285000 0.555000 ; - RECT 4.495000 1.625000 4.745000 2.125000 ; - RECT 4.915000 1.795000 5.195000 2.295000 ; - RECT 4.955000 0.085000 5.645000 0.555000 ; - RECT 5.380000 1.795000 5.685000 2.295000 ; - RECT 5.380000 2.295000 7.365000 2.465000 ; - RECT 5.855000 1.625000 6.105000 2.125000 ; - RECT 6.275000 1.795000 6.525000 2.295000 ; - RECT 6.315000 0.085000 6.485000 0.555000 ; - RECT 6.695000 1.625000 6.945000 2.125000 ; - RECT 7.115000 1.455000 9.110000 1.625000 ; - RECT 7.115000 1.625000 7.365000 2.295000 ; - RECT 7.155000 0.085000 7.325000 0.555000 ; - RECT 7.535000 1.795000 7.785000 2.635000 ; - RECT 7.955000 1.625000 8.205000 2.465000 ; - RECT 7.995000 0.085000 8.165000 0.555000 ; - RECT 8.375000 1.795000 8.625000 2.635000 ; - RECT 8.795000 1.625000 9.110000 2.465000 ; - RECT 8.835000 0.085000 9.110000 0.905000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - END -END sky130_fd_sc_hd__nor4bb_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.770000 1.075000 1.220000 1.275000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 0.380000 1.290000 0.735000 ; - RECT 1.070000 0.735000 1.565000 0.905000 ; - RECT 1.390000 0.905000 1.565000 1.100000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.250000 1.075000 3.595000 1.645000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.520000 1.075000 3.080000 1.325000 ; - RECT 2.905000 1.325000 3.080000 2.425000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.425000 0.825000 ; - RECT 0.085000 0.825000 0.260000 1.795000 ; - RECT 0.085000 1.795000 0.345000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.430000 0.995000 0.600000 1.445000 ; - RECT 0.430000 1.445000 0.825000 1.615000 ; - RECT 0.515000 2.235000 0.845000 2.635000 ; - RECT 0.620000 0.085000 0.790000 0.750000 ; - RECT 0.655000 1.615000 0.825000 1.885000 ; - RECT 0.655000 1.885000 2.735000 2.055000 ; - RECT 0.995000 1.495000 2.010000 1.715000 ; - RECT 1.460000 0.395000 1.905000 0.565000 ; - RECT 1.715000 2.235000 2.115000 2.635000 ; - RECT 1.735000 0.565000 1.905000 1.355000 ; - RECT 1.735000 1.355000 2.010000 1.495000 ; - RECT 2.075000 0.320000 2.325000 0.690000 ; - RECT 2.155000 0.690000 2.325000 1.075000 ; - RECT 2.155000 1.075000 2.350000 1.245000 ; - RECT 2.180000 1.245000 2.350000 1.495000 ; - RECT 2.180000 1.495000 2.735000 1.885000 ; - RECT 2.405000 2.055000 2.735000 2.290000 ; - RECT 2.495000 0.320000 2.745000 0.725000 ; - RECT 2.495000 0.725000 3.595000 0.905000 ; - RECT 2.915000 0.085000 3.085000 0.555000 ; - RECT 3.250000 1.815000 3.595000 2.635000 ; - RECT 3.255000 0.320000 3.595000 0.725000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o2bb2a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.215000 1.075000 1.685000 1.275000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.515000 0.380000 1.735000 0.735000 ; - RECT 1.515000 0.735000 2.020000 0.770000 ; - RECT 1.515000 0.770000 2.025000 0.905000 ; - RECT 1.855000 0.905000 2.025000 1.100000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.700000 1.075000 4.045000 1.645000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.075000 3.525000 1.325000 ; - RECT 3.355000 1.325000 3.525000 2.425000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.255000 0.870000 0.825000 ; - RECT 0.535000 0.825000 0.705000 1.795000 ; - RECT 0.535000 1.795000 0.790000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.135000 -0.085000 0.305000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.110000 0.085000 0.365000 0.910000 ; - RECT 0.110000 1.410000 0.365000 2.635000 ; - RECT 0.875000 0.995000 1.045000 1.445000 ; - RECT 0.875000 1.445000 1.270000 1.615000 ; - RECT 0.960000 2.235000 1.290000 2.635000 ; - RECT 1.065000 0.085000 1.235000 0.750000 ; - RECT 1.100000 1.615000 1.270000 1.885000 ; - RECT 1.100000 1.885000 3.185000 2.055000 ; - RECT 1.440000 1.495000 2.460000 1.715000 ; - RECT 1.905000 0.395000 2.365000 0.565000 ; - RECT 2.160000 2.235000 2.565000 2.635000 ; - RECT 2.195000 0.565000 2.365000 1.355000 ; - RECT 2.195000 1.355000 2.460000 1.495000 ; - RECT 2.535000 0.320000 2.780000 0.690000 ; - RECT 2.610000 0.690000 2.780000 1.075000 ; - RECT 2.610000 1.075000 2.800000 1.245000 ; - RECT 2.630000 1.245000 2.800000 1.495000 ; - RECT 2.630000 1.495000 3.185000 1.885000 ; - RECT 2.835000 2.055000 3.185000 2.425000 ; - RECT 2.955000 0.320000 3.185000 0.725000 ; - RECT 2.955000 0.725000 4.045000 0.905000 ; - RECT 3.375000 0.085000 3.545000 0.555000 ; - RECT 3.715000 0.320000 4.045000 0.725000 ; - RECT 3.730000 1.815000 4.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o2bb2a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.315000 1.075000 3.645000 1.445000 ; - RECT 3.315000 1.445000 4.965000 1.615000 ; - RECT 4.605000 1.075000 4.965000 1.445000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.815000 1.075000 4.435000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.575000 1.445000 ; - RECT 0.085000 1.445000 1.895000 1.615000 ; - RECT 1.565000 1.075000 1.895000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.805000 1.075000 1.345000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.235000 0.275000 5.565000 0.725000 ; - RECT 5.235000 0.725000 6.910000 0.905000 ; - RECT 5.275000 1.785000 6.365000 1.955000 ; - RECT 5.275000 1.955000 5.525000 2.465000 ; - RECT 6.075000 0.275000 6.405000 0.725000 ; - RECT 6.115000 1.415000 6.910000 1.655000 ; - RECT 6.115000 1.655000 6.365000 1.785000 ; - RECT 6.115000 1.955000 6.365000 2.465000 ; - RECT 6.605000 0.905000 6.910000 1.415000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.095000 0.255000 0.425000 0.725000 ; - RECT 0.095000 0.725000 1.265000 0.735000 ; - RECT 0.095000 0.735000 2.025000 0.905000 ; - RECT 0.140000 1.795000 0.345000 2.635000 ; - RECT 0.555000 1.785000 0.805000 2.295000 ; - RECT 0.555000 2.295000 1.645000 2.465000 ; - RECT 0.595000 0.085000 0.765000 0.555000 ; - RECT 0.935000 0.255000 1.265000 0.725000 ; - RECT 0.975000 1.785000 2.615000 1.955000 ; - RECT 0.975000 1.955000 1.225000 2.125000 ; - RECT 1.395000 2.125000 1.645000 2.295000 ; - RECT 1.435000 0.085000 1.605000 0.555000 ; - RECT 1.775000 0.255000 2.945000 0.475000 ; - RECT 1.775000 0.475000 2.025000 0.735000 ; - RECT 1.815000 2.125000 2.065000 2.635000 ; - RECT 2.065000 1.075000 2.445000 1.415000 ; - RECT 2.065000 1.415000 2.615000 1.785000 ; - RECT 2.195000 0.645000 2.525000 0.815000 ; - RECT 2.195000 0.815000 2.445000 1.075000 ; - RECT 2.235000 1.955000 2.615000 1.965000 ; - RECT 2.235000 1.965000 2.525000 2.465000 ; - RECT 2.615000 1.075000 3.145000 1.245000 ; - RECT 2.695000 2.135000 3.425000 2.635000 ; - RECT 2.955000 0.725000 4.305000 0.905000 ; - RECT 2.955000 0.905000 3.145000 1.075000 ; - RECT 2.955000 1.245000 3.145000 1.785000 ; - RECT 2.955000 1.785000 4.685000 1.965000 ; - RECT 3.215000 0.085000 3.385000 0.555000 ; - RECT 3.555000 0.305000 4.725000 0.475000 ; - RECT 3.595000 1.965000 3.845000 2.125000 ; - RECT 3.975000 0.645000 4.305000 0.725000 ; - RECT 4.015000 2.135000 4.265000 2.635000 ; - RECT 4.435000 1.965000 4.685000 2.465000 ; - RECT 4.475000 0.475000 4.725000 0.895000 ; - RECT 4.855000 1.795000 5.105000 2.635000 ; - RECT 4.895000 0.085000 5.065000 0.895000 ; - RECT 5.165000 1.075000 6.435000 1.245000 ; - RECT 5.165000 1.245000 5.455000 1.615000 ; - RECT 5.695000 2.165000 5.945000 2.635000 ; - RECT 5.735000 0.085000 5.905000 0.555000 ; - RECT 6.535000 1.825000 6.785000 2.635000 ; - RECT 6.575000 0.085000 6.745000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 1.445000 2.615000 1.615000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.225000 1.445000 5.395000 1.615000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - LAYER met1 ; - RECT 2.385000 1.415000 2.675000 1.460000 ; - RECT 2.385000 1.460000 5.455000 1.600000 ; - RECT 2.385000 1.600000 2.675000 1.645000 ; - RECT 5.165000 1.415000 5.455000 1.460000 ; - RECT 5.165000 1.600000 5.455000 1.645000 ; - END -END sky130_fd_sc_hd__o2bb2a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.985000 0.435000 1.285000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.280000 0.825000 0.995000 ; - RECT 0.605000 0.995000 1.000000 1.325000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.785000 1.075000 3.135000 1.285000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.030000 1.075000 2.615000 1.325000 ; - RECT 2.445000 1.325000 2.615000 2.425000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.439000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.560000 0.430000 1.810000 0.790000 ; - RECT 1.640000 0.790000 1.810000 1.495000 ; - RECT 1.640000 1.495000 2.270000 1.665000 ; - RECT 1.940000 1.665000 2.270000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 0.085000 0.425000 0.815000 ; - RECT 0.150000 1.455000 0.400000 2.635000 ; - RECT 0.570000 1.495000 1.340000 1.665000 ; - RECT 0.570000 1.665000 0.820000 2.465000 ; - RECT 0.990000 1.835000 1.770000 2.635000 ; - RECT 1.000000 0.280000 1.340000 0.825000 ; - RECT 1.170000 0.825000 1.340000 0.995000 ; - RECT 1.170000 0.995000 1.470000 1.325000 ; - RECT 1.170000 1.325000 1.340000 1.495000 ; - RECT 1.980000 0.425000 2.270000 0.725000 ; - RECT 1.980000 0.725000 3.110000 0.905000 ; - RECT 2.440000 0.085000 2.610000 0.555000 ; - RECT 2.780000 0.275000 3.110000 0.725000 ; - RECT 2.820000 1.455000 3.070000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o2bb2ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.625000 1.445000 ; - RECT 0.090000 1.445000 1.945000 1.615000 ; - RECT 1.615000 1.075000 1.945000 1.445000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.795000 1.075000 1.400000 1.275000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.410000 1.075000 3.740000 1.445000 ; - RECT 3.410000 1.445000 5.435000 1.615000 ; - RECT 4.730000 1.075000 5.435000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.960000 1.075000 4.500000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.715500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.745000 0.645000 3.075000 1.075000 ; - RECT 2.745000 1.075000 3.215000 1.785000 ; - RECT 2.745000 1.785000 4.330000 1.955000 ; - RECT 2.745000 1.955000 3.035000 2.465000 ; - RECT 4.080000 1.955000 4.330000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.150000 1.795000 0.400000 2.635000 ; - RECT 0.195000 0.085000 0.365000 0.895000 ; - RECT 0.535000 0.305000 1.705000 0.475000 ; - RECT 0.535000 0.475000 0.785000 0.895000 ; - RECT 0.575000 1.785000 2.285000 1.965000 ; - RECT 0.575000 1.965000 0.825000 2.465000 ; - RECT 0.955000 0.645000 1.285000 0.725000 ; - RECT 0.955000 0.725000 2.285000 0.905000 ; - RECT 0.995000 2.135000 1.245000 2.635000 ; - RECT 1.415000 1.965000 1.665000 2.125000 ; - RECT 1.835000 2.135000 2.575000 2.635000 ; - RECT 1.875000 0.085000 2.045000 0.555000 ; - RECT 2.115000 0.905000 2.285000 0.995000 ; - RECT 2.115000 0.995000 2.575000 1.325000 ; - RECT 2.115000 1.325000 2.285000 1.785000 ; - RECT 2.325000 0.255000 3.530000 0.475000 ; - RECT 2.325000 0.475000 2.575000 0.555000 ; - RECT 3.205000 2.125000 3.490000 2.635000 ; - RECT 3.245000 0.475000 3.530000 0.735000 ; - RECT 3.245000 0.735000 5.210000 0.905000 ; - RECT 3.660000 2.125000 3.910000 2.295000 ; - RECT 3.660000 2.295000 4.750000 2.465000 ; - RECT 3.700000 0.085000 3.870000 0.555000 ; - RECT 4.040000 0.255000 4.370000 0.725000 ; - RECT 4.040000 0.725000 5.210000 0.735000 ; - RECT 4.500000 1.785000 4.750000 2.295000 ; - RECT 4.540000 0.085000 4.710000 0.555000 ; - RECT 4.880000 0.255000 5.210000 0.725000 ; - RECT 4.965000 1.795000 5.170000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__o2bb2ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2bb2ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2bb2ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1_N - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.095000 1.075000 3.505000 1.285000 ; - END - END A1_N - PIN A2_N - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 1.075000 1.825000 1.285000 ; - END - END A2_N - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.045000 1.075000 10.005000 1.285000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.465000 1.075000 7.875000 1.285000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.431000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.415000 0.645000 6.155000 0.905000 ; - RECT 4.425000 1.455000 7.715000 1.625000 ; - RECT 4.425000 1.625000 4.675000 2.465000 ; - RECT 5.265000 1.625000 5.515000 2.465000 ; - RECT 5.875000 0.905000 6.155000 1.455000 ; - RECT 6.625000 1.625000 6.875000 2.125000 ; - RECT 7.465000 1.625000 7.715000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.135000 -0.085000 0.305000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.085000 0.645000 1.705000 0.905000 ; - RECT 0.085000 0.905000 0.255000 1.455000 ; - RECT 0.085000 1.455000 3.915000 1.625000 ; - RECT 0.100000 0.255000 2.125000 0.475000 ; - RECT 0.155000 1.795000 0.405000 2.635000 ; - RECT 0.575000 1.625000 0.825000 2.465000 ; - RECT 0.995000 1.795000 1.245000 2.635000 ; - RECT 1.415000 1.625000 1.665000 2.465000 ; - RECT 1.835000 1.795000 2.085000 2.635000 ; - RECT 1.875000 0.475000 2.125000 0.725000 ; - RECT 1.875000 0.725000 3.805000 0.905000 ; - RECT 2.255000 1.625000 2.505000 2.465000 ; - RECT 2.295000 0.085000 2.465000 0.555000 ; - RECT 2.635000 0.255000 2.965000 0.725000 ; - RECT 2.675000 1.795000 2.925000 2.635000 ; - RECT 3.095000 1.625000 3.345000 2.465000 ; - RECT 3.135000 0.085000 3.305000 0.555000 ; - RECT 3.475000 0.255000 3.805000 0.725000 ; - RECT 3.515000 1.795000 4.255000 2.635000 ; - RECT 3.745000 1.075000 5.705000 1.285000 ; - RECT 3.745000 1.285000 3.915000 1.455000 ; - RECT 4.060000 0.255000 6.495000 0.475000 ; - RECT 4.060000 0.475000 4.245000 0.835000 ; - RECT 4.845000 1.795000 5.095000 2.635000 ; - RECT 5.685000 1.795000 5.935000 2.635000 ; - RECT 6.175000 1.795000 6.455000 2.295000 ; - RECT 6.175000 2.295000 8.135000 2.465000 ; - RECT 6.325000 0.475000 6.495000 0.735000 ; - RECT 6.325000 0.735000 9.855000 0.905000 ; - RECT 6.665000 0.085000 6.835000 0.555000 ; - RECT 7.005000 0.255000 7.335000 0.725000 ; - RECT 7.005000 0.725000 9.855000 0.735000 ; - RECT 7.045000 1.795000 7.295000 2.295000 ; - RECT 7.505000 0.085000 7.675000 0.555000 ; - RECT 7.845000 0.255000 8.175000 0.725000 ; - RECT 7.885000 1.455000 9.875000 1.625000 ; - RECT 7.885000 1.625000 8.135000 2.295000 ; - RECT 8.305000 1.795000 8.555000 2.635000 ; - RECT 8.345000 0.085000 8.515000 0.555000 ; - RECT 8.685000 0.255000 9.015000 0.725000 ; - RECT 8.725000 1.625000 8.975000 2.465000 ; - RECT 9.145000 1.795000 9.395000 2.635000 ; - RECT 9.185000 0.085000 9.355000 0.555000 ; - RECT 9.525000 0.255000 9.855000 0.725000 ; - RECT 9.565000 1.625000 9.875000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__o2bb2ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.345000 1.075000 2.675000 1.275000 ; - RECT 2.445000 1.275000 2.675000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.705000 1.075000 2.035000 1.095000 ; - RECT 1.705000 1.095000 2.155000 1.275000 ; - RECT 1.940000 1.275000 2.155000 2.390000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 1.075000 1.535000 1.305000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.449000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.425000 1.030000 ; - RECT 0.085000 1.030000 0.365000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.535000 1.860000 1.245000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 0.595000 0.715000 1.305000 0.905000 ; - RECT 0.595000 0.905000 0.880000 1.475000 ; - RECT 0.595000 1.475000 1.745000 1.690000 ; - RECT 1.005000 0.255000 1.365000 0.520000 ; - RECT 1.005000 0.520000 1.360000 0.525000 ; - RECT 1.005000 0.525000 1.355000 0.535000 ; - RECT 1.005000 0.535000 1.350000 0.540000 ; - RECT 1.005000 0.540000 1.345000 0.550000 ; - RECT 1.005000 0.550000 1.340000 0.555000 ; - RECT 1.005000 0.555000 1.330000 0.565000 ; - RECT 1.005000 0.565000 1.320000 0.575000 ; - RECT 1.005000 0.575000 1.305000 0.715000 ; - RECT 1.415000 1.690000 1.745000 2.465000 ; - RECT 1.495000 0.635000 1.825000 0.715000 ; - RECT 1.495000 0.715000 2.675000 0.905000 ; - RECT 1.995000 0.085000 2.165000 0.545000 ; - RECT 2.335000 0.255000 2.675000 0.715000 ; - RECT 2.335000 1.915000 2.665000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__o21a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.865000 0.995000 3.125000 1.450000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.025000 1.025000 2.610000 1.400000 ; - RECT 2.405000 1.400000 2.610000 1.985000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.445000 1.010000 1.855000 1.615000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.530000 0.255000 0.775000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 1.635000 0.345000 2.635000 ; - RECT 0.105000 0.085000 0.345000 0.885000 ; - RECT 0.945000 0.085000 1.275000 0.465000 ; - RECT 0.945000 0.635000 1.795000 0.840000 ; - RECT 0.945000 0.840000 1.275000 1.330000 ; - RECT 0.945000 2.185000 1.795000 2.635000 ; - RECT 1.105000 1.330000 1.275000 1.785000 ; - RECT 1.105000 1.785000 2.225000 2.005000 ; - RECT 1.465000 0.255000 1.795000 0.635000 ; - RECT 1.965000 0.465000 2.175000 0.635000 ; - RECT 1.965000 0.635000 3.120000 0.825000 ; - RECT 1.965000 2.005000 2.225000 2.465000 ; - RECT 2.345000 0.085000 2.675000 0.465000 ; - RECT 2.795000 1.650000 3.120000 2.635000 ; - RECT 2.845000 0.495000 3.120000 0.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o21a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.480000 0.990000 3.785000 1.495000 ; - RECT 3.480000 1.495000 5.400000 1.705000 ; - RECT 5.030000 0.995000 5.400000 1.495000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.140000 0.995000 4.690000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.485000 1.075000 3.155000 1.615000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.924000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.635000 1.715000 0.805000 ; - RECT 0.090000 0.805000 0.320000 1.530000 ; - RECT 0.090000 1.530000 1.955000 1.700000 ; - RECT 0.595000 0.615000 1.715000 0.635000 ; - RECT 0.915000 1.700000 1.105000 2.465000 ; - RECT 1.775000 1.700000 1.955000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 0.415000 1.870000 0.745000 2.635000 ; - RECT 0.490000 0.995000 2.315000 1.335000 ; - RECT 0.955000 0.085000 1.285000 0.445000 ; - RECT 1.275000 1.870000 1.605000 2.635000 ; - RECT 1.815000 0.085000 2.145000 0.465000 ; - RECT 2.115000 0.655000 3.095000 0.870000 ; - RECT 2.115000 0.870000 2.315000 0.995000 ; - RECT 2.125000 1.335000 2.315000 1.830000 ; - RECT 2.125000 1.830000 2.845000 1.875000 ; - RECT 2.125000 1.875000 4.545000 2.085000 ; - RECT 2.135000 2.255000 2.485000 2.635000 ; - RECT 2.335000 0.255000 3.605000 0.485000 ; - RECT 2.655000 2.085000 4.545000 2.105000 ; - RECT 2.655000 2.105000 2.845000 2.465000 ; - RECT 3.015000 2.275000 3.685000 2.635000 ; - RECT 3.275000 0.485000 3.605000 0.615000 ; - RECT 3.275000 0.615000 5.405000 0.785000 ; - RECT 3.775000 0.085000 4.115000 0.445000 ; - RECT 4.215000 2.105000 4.545000 2.445000 ; - RECT 4.645000 0.085000 4.975000 0.445000 ; - RECT 5.075000 1.935000 5.435000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__o21a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ai_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ai_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.955000 0.415000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 1.100000 1.005000 1.340000 ; - RECT 0.605000 1.340000 0.775000 1.645000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.515000 1.355000 1.730000 1.685000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.290500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.965000 1.510000 1.345000 1.680000 ; - RECT 0.965000 1.680000 1.300000 2.465000 ; - RECT 1.175000 0.955000 1.740000 1.125000 ; - RECT 1.175000 1.125000 1.345000 1.510000 ; - RECT 1.455000 0.280000 1.740000 0.955000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.120000 0.280000 0.380000 0.615000 ; - RECT 0.120000 0.615000 1.285000 0.785000 ; - RECT 0.145000 1.825000 0.475000 2.635000 ; - RECT 0.550000 0.085000 0.880000 0.445000 ; - RECT 1.050000 0.280000 1.285000 0.615000 ; - RECT 1.470000 1.855000 1.725000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__o21ai_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 1.840000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.995000 0.410000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.590000 0.995000 0.975000 1.325000 ; - RECT 0.590000 1.325000 0.785000 2.375000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.202500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.505000 1.295000 1.750000 1.655000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.517000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.965000 1.505000 1.315000 1.785000 ; - RECT 0.965000 1.785000 1.295000 2.465000 ; - RECT 1.145000 0.955000 1.665000 1.125000 ; - RECT 1.145000 1.125000 1.315000 1.505000 ; - RECT 1.495000 0.390000 1.665000 0.955000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 1.840000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.030000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 1.840000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 1.840000 0.085000 ; - RECT 0.000000 2.635000 1.840000 2.805000 ; - RECT 0.090000 0.265000 0.380000 0.615000 ; - RECT 0.090000 0.615000 1.305000 0.785000 ; - RECT 0.090000 1.495000 0.410000 2.635000 ; - RECT 0.575000 0.085000 0.905000 0.445000 ; - RECT 1.075000 0.310000 1.305000 0.615000 ; - RECT 1.495000 1.835000 1.750000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - END -END sky130_fd_sc_hd__o21ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 1.055000 0.450000 1.445000 ; - RECT 0.120000 1.445000 2.095000 1.615000 ; - RECT 1.600000 1.075000 2.095000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.620000 1.075000 1.420000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.815000 0.765000 3.130000 1.400000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.742000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.995000 1.785000 2.645000 1.965000 ; - RECT 0.995000 1.965000 1.295000 2.125000 ; - RECT 2.410000 1.965000 2.645000 2.465000 ; - RECT 2.435000 0.595000 2.645000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.105000 0.255000 0.435000 0.715000 ; - RECT 0.105000 0.715000 2.265000 0.885000 ; - RECT 0.105000 1.785000 0.435000 2.635000 ; - RECT 0.605000 1.785000 0.825000 2.295000 ; - RECT 0.605000 2.295000 1.715000 2.465000 ; - RECT 0.615000 0.085000 0.785000 0.545000 ; - RECT 0.965000 0.255000 1.295000 0.715000 ; - RECT 1.525000 0.085000 1.695000 0.545000 ; - RECT 1.525000 2.135000 1.715000 2.295000 ; - RECT 1.910000 2.175000 2.240000 2.635000 ; - RECT 1.935000 0.255000 3.125000 0.425000 ; - RECT 1.935000 0.425000 2.265000 0.715000 ; - RECT 2.815000 0.425000 3.125000 0.595000 ; - RECT 2.815000 1.570000 3.125000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o21ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.125000 1.015000 1.475000 1.320000 ; - RECT 0.575000 1.320000 1.475000 1.515000 ; - RECT 0.575000 1.515000 3.695000 1.685000 ; - RECT 3.445000 0.990000 3.695000 1.515000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 1.070000 3.275000 1.345000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.905000 1.015000 5.255000 1.275000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.484000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.840000 1.855000 5.150000 2.025000 ; - RECT 3.935000 1.445000 5.835000 1.700000 ; - RECT 3.935000 1.700000 5.150000 1.855000 ; - RECT 4.030000 0.615000 5.835000 0.845000 ; - RECT 4.080000 2.025000 5.150000 2.085000 ; - RECT 4.080000 2.085000 4.290000 2.465000 ; - RECT 4.960000 2.085000 5.150000 2.465000 ; - RECT 5.425000 0.845000 5.835000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.120000 0.615000 3.860000 0.820000 ; - RECT 0.120000 1.820000 0.405000 2.635000 ; - RECT 0.550000 0.085000 0.880000 0.445000 ; - RECT 0.575000 1.915000 1.670000 2.085000 ; - RECT 0.575000 2.085000 0.810000 2.465000 ; - RECT 0.980000 2.255000 1.310000 2.635000 ; - RECT 1.410000 0.085000 1.740000 0.445000 ; - RECT 1.480000 2.085000 1.670000 2.275000 ; - RECT 1.480000 2.275000 3.460000 2.465000 ; - RECT 2.270000 0.085000 2.600000 0.445000 ; - RECT 3.130000 0.085000 3.460000 0.445000 ; - RECT 3.630000 0.255000 5.650000 0.445000 ; - RECT 3.630000 0.445000 3.860000 0.615000 ; - RECT 3.630000 2.195000 3.910000 2.635000 ; - RECT 4.460000 2.255000 4.790000 2.635000 ; - RECT 5.320000 1.880000 5.650000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__o21ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ba_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ba_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.950000 1.075000 3.595000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.210000 1.075000 2.780000 1.285000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.030000 0.995000 1.360000 1.325000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.450000 0.445000 0.825000 ; - RECT 0.085000 0.825000 0.340000 1.480000 ; - RECT 0.085000 1.480000 0.425000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.510000 0.995000 0.860000 1.325000 ; - RECT 0.595000 1.325000 0.860000 1.865000 ; - RECT 0.595000 1.865000 2.575000 2.035000 ; - RECT 0.595000 2.205000 1.005000 2.635000 ; - RECT 0.710000 0.085000 0.880000 0.825000 ; - RECT 1.075000 1.525000 1.700000 1.695000 ; - RECT 1.160000 0.450000 1.330000 0.655000 ; - RECT 1.160000 0.655000 1.700000 0.825000 ; - RECT 1.530000 0.825000 1.700000 1.525000 ; - RECT 1.750000 2.215000 2.080000 2.635000 ; - RECT 1.870000 0.255000 2.040000 1.455000 ; - RECT 1.870000 1.455000 2.575000 1.865000 ; - RECT 2.250000 2.035000 2.575000 2.465000 ; - RECT 2.270000 0.255000 2.600000 0.735000 ; - RECT 2.270000 0.735000 3.440000 0.905000 ; - RECT 2.770000 0.085000 2.940000 0.555000 ; - RECT 3.050000 1.535000 3.380000 2.635000 ; - RECT 3.110000 0.270000 3.440000 0.735000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o21ba_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ba_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ba_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.100000 1.075000 3.595000 1.625000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 1.075000 2.930000 1.285000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.325000 ; - RECT 0.595000 1.325000 0.775000 1.695000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.255000 1.240000 0.595000 ; - RECT 0.945000 0.595000 1.115000 1.495000 ; - RECT 0.945000 1.495000 1.350000 1.695000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.430000 0.345000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.495000 ; - RECT 0.085000 1.495000 0.395000 1.865000 ; - RECT 0.085000 1.865000 1.935000 2.035000 ; - RECT 0.520000 2.205000 0.910000 2.635000 ; - RECT 0.595000 0.085000 0.775000 0.825000 ; - RECT 1.285000 0.890000 1.595000 1.060000 ; - RECT 1.285000 1.060000 1.455000 1.325000 ; - RECT 1.410000 0.085000 1.770000 0.485000 ; - RECT 1.415000 2.205000 2.230000 2.635000 ; - RECT 1.425000 0.655000 2.275000 0.825000 ; - RECT 1.425000 0.825000 1.595000 0.890000 ; - RECT 1.765000 0.995000 1.935000 1.865000 ; - RECT 1.940000 0.255000 2.275000 0.655000 ; - RECT 2.105000 0.825000 2.275000 1.455000 ; - RECT 2.105000 1.455000 2.725000 2.035000 ; - RECT 2.400000 2.035000 2.725000 2.465000 ; - RECT 2.445000 0.365000 2.745000 0.735000 ; - RECT 2.445000 0.735000 3.590000 0.905000 ; - RECT 2.915000 0.085000 3.085000 0.555000 ; - RECT 3.200000 1.875000 3.530000 2.635000 ; - RECT 3.255000 0.270000 3.590000 0.735000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o21ba_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21ba_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21ba_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.990000 1.075000 5.895000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.780000 1.075000 4.820000 1.275000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 1.075000 0.885000 1.285000 ; - RECT 0.605000 1.285000 0.885000 1.705000 ; - END - END B1_N - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.055000 0.255000 1.385000 0.725000 ; - RECT 1.055000 0.725000 2.225000 0.905000 ; - RECT 1.055000 0.905000 1.455000 1.445000 ; - RECT 1.055000 1.445000 2.225000 1.705000 ; - RECT 1.895000 0.255000 2.225000 0.725000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.265000 0.545000 0.855000 ; - RECT 0.085000 0.855000 0.255000 1.455000 ; - RECT 0.085000 1.455000 0.435000 1.875000 ; - RECT 0.085000 1.875000 2.565000 2.045000 ; - RECT 0.085000 2.045000 0.435000 2.465000 ; - RECT 0.635000 2.215000 0.965000 2.635000 ; - RECT 0.715000 0.085000 0.885000 0.905000 ; - RECT 1.475000 2.215000 1.805000 2.635000 ; - RECT 1.555000 0.085000 1.725000 0.555000 ; - RECT 1.625000 1.075000 2.565000 1.275000 ; - RECT 2.315000 2.215000 2.645000 2.635000 ; - RECT 2.395000 0.085000 2.565000 0.555000 ; - RECT 2.395000 0.725000 3.585000 0.895000 ; - RECT 2.395000 0.895000 2.565000 1.075000 ; - RECT 2.395000 1.445000 2.905000 1.615000 ; - RECT 2.395000 1.615000 2.565000 1.875000 ; - RECT 2.735000 1.075000 3.135000 1.245000 ; - RECT 2.735000 1.245000 2.905000 1.445000 ; - RECT 2.805000 0.255000 4.005000 0.475000 ; - RECT 2.815000 1.795000 4.380000 1.965000 ; - RECT 2.815000 1.965000 2.985000 2.465000 ; - RECT 3.200000 2.135000 3.450000 2.635000 ; - RECT 3.235000 0.645000 3.585000 0.725000 ; - RECT 3.395000 0.895000 3.585000 1.795000 ; - RECT 3.685000 2.135000 3.925000 2.295000 ; - RECT 3.685000 2.295000 4.765000 2.465000 ; - RECT 3.755000 0.475000 4.005000 0.725000 ; - RECT 3.755000 0.725000 5.710000 0.905000 ; - RECT 4.135000 1.445000 4.380000 1.795000 ; - RECT 4.135000 1.965000 4.380000 2.125000 ; - RECT 4.175000 0.085000 4.345000 0.555000 ; - RECT 4.515000 0.255000 4.845000 0.725000 ; - RECT 4.595000 1.455000 5.710000 1.665000 ; - RECT 4.595000 1.665000 4.765000 2.295000 ; - RECT 4.935000 1.835000 5.265000 2.635000 ; - RECT 5.015000 0.085000 5.185000 0.555000 ; - RECT 5.355000 0.265000 5.710000 0.725000 ; - RECT 5.435000 1.665000 5.710000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__o21ba_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21bai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21bai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.195000 1.075000 2.675000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 1.075000 2.025000 1.285000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.535000 1.345000 ; - RECT 0.085000 1.345000 0.355000 2.445000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 0.474000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.115000 0.255000 1.285000 0.645000 ; - RECT 1.115000 0.645000 1.355000 0.825000 ; - RECT 1.185000 0.825000 1.355000 1.455000 ; - RECT 1.185000 1.455000 1.795000 1.625000 ; - RECT 1.470000 1.625000 1.795000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.085000 0.085000 0.360000 0.825000 ; - RECT 0.525000 1.535000 1.015000 1.705000 ; - RECT 0.525000 1.705000 0.800000 2.210000 ; - RECT 0.580000 0.495000 0.770000 0.655000 ; - RECT 0.580000 0.655000 0.890000 0.825000 ; - RECT 0.720000 0.825000 0.890000 0.995000 ; - RECT 0.720000 0.995000 1.015000 1.535000 ; - RECT 0.970000 1.875000 1.300000 2.635000 ; - RECT 1.490000 0.255000 1.820000 0.485000 ; - RECT 1.570000 0.485000 1.740000 0.735000 ; - RECT 1.570000 0.735000 2.665000 0.905000 ; - RECT 1.995000 0.085000 2.165000 0.555000 ; - RECT 2.270000 1.535000 2.645000 2.635000 ; - RECT 2.335000 0.270000 2.665000 0.735000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__o21bai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21bai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21bai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.260000 1.075000 4.055000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.950000 1.075000 3.090000 1.275000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.525000 1.325000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 0.715500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.085000 1.445000 2.650000 1.615000 ; - RECT 1.085000 1.615000 1.255000 2.465000 ; - RECT 1.525000 0.645000 1.855000 0.905000 ; - RECT 1.525000 0.905000 1.780000 1.445000 ; - RECT 2.405000 1.615000 2.650000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.180000 0.085000 0.350000 0.825000 ; - RECT 0.180000 1.495000 0.865000 1.665000 ; - RECT 0.180000 1.665000 0.350000 1.915000 ; - RECT 0.585000 1.875000 0.915000 2.635000 ; - RECT 0.600000 0.445000 0.865000 0.825000 ; - RECT 0.695000 0.825000 0.865000 1.075000 ; - RECT 0.695000 1.075000 1.335000 1.245000 ; - RECT 0.695000 1.245000 0.865000 1.495000 ; - RECT 1.075000 0.255000 2.275000 0.475000 ; - RECT 1.075000 0.475000 1.355000 0.905000 ; - RECT 1.470000 1.795000 1.720000 2.635000 ; - RECT 1.955000 1.795000 2.235000 2.295000 ; - RECT 1.955000 2.295000 3.035000 2.465000 ; - RECT 2.025000 0.475000 2.275000 0.725000 ; - RECT 2.025000 0.725000 3.980000 0.905000 ; - RECT 2.445000 0.085000 2.615000 0.555000 ; - RECT 2.785000 0.255000 3.115000 0.725000 ; - RECT 2.865000 1.455000 3.980000 1.665000 ; - RECT 2.865000 1.665000 3.035000 2.295000 ; - RECT 3.205000 1.835000 3.535000 2.635000 ; - RECT 3.285000 0.085000 3.455000 0.555000 ; - RECT 3.625000 0.265000 3.980000 0.725000 ; - RECT 3.705000 1.665000 3.980000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o21bai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o21bai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o21bai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.645000 1.075000 6.810000 1.285000 ; - RECT 6.585000 1.285000 6.810000 2.455000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.065000 1.075000 4.475000 1.275000 ; - END - END A2 - PIN B1_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.555000 1.285000 ; - END - END B1_N - PIN Y - ANTENNADIFFAREA 1.431000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.065000 1.455000 4.315000 1.625000 ; - RECT 1.065000 1.625000 1.275000 2.465000 ; - RECT 1.420000 0.645000 2.675000 0.815000 ; - RECT 1.865000 1.625000 2.115000 2.465000 ; - RECT 2.445000 0.815000 2.675000 1.075000 ; - RECT 2.445000 1.075000 2.895000 1.445000 ; - RECT 2.445000 1.445000 4.315000 1.455000 ; - RECT 3.225000 1.625000 3.475000 2.125000 ; - RECT 4.065000 1.625000 4.315000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.145000 1.455000 0.895000 1.625000 ; - RECT 0.145000 1.625000 0.475000 2.435000 ; - RECT 0.225000 0.085000 0.395000 0.895000 ; - RECT 0.565000 0.290000 0.895000 0.895000 ; - RECT 0.645000 1.795000 0.855000 2.635000 ; - RECT 0.725000 0.895000 0.895000 1.075000 ; - RECT 0.725000 1.075000 2.275000 1.285000 ; - RECT 0.725000 1.285000 0.895000 1.455000 ; - RECT 1.080000 0.305000 3.095000 0.475000 ; - RECT 1.445000 1.795000 1.695000 2.635000 ; - RECT 2.285000 1.795000 2.535000 2.635000 ; - RECT 2.775000 1.795000 3.055000 2.295000 ; - RECT 2.775000 2.295000 4.735000 2.465000 ; - RECT 2.845000 0.475000 3.095000 0.725000 ; - RECT 2.845000 0.725000 6.455000 0.905000 ; - RECT 3.265000 0.085000 3.435000 0.555000 ; - RECT 3.605000 0.255000 3.935000 0.725000 ; - RECT 3.645000 1.795000 3.895000 2.295000 ; - RECT 4.105000 0.085000 4.275000 0.555000 ; - RECT 4.445000 0.255000 4.775000 0.725000 ; - RECT 4.485000 1.455000 6.415000 1.625000 ; - RECT 4.485000 1.625000 4.735000 2.295000 ; - RECT 4.905000 1.795000 5.155000 2.635000 ; - RECT 4.945000 0.085000 5.115000 0.555000 ; - RECT 5.285000 0.255000 5.615000 0.725000 ; - RECT 5.325000 1.625000 5.575000 2.465000 ; - RECT 5.745000 1.795000 5.995000 2.635000 ; - RECT 5.785000 0.085000 5.955000 0.555000 ; - RECT 6.125000 0.255000 6.455000 0.725000 ; - RECT 6.165000 1.625000 6.415000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - END -END sky130_fd_sc_hd__o21bai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.670000 1.075000 3.135000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.165000 1.075000 2.495000 1.325000 ; - RECT 2.315000 1.325000 2.495000 1.445000 ; - RECT 2.315000 1.445000 2.645000 1.615000 ; - RECT 2.445000 1.615000 2.645000 2.405000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.980000 1.075000 1.335000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 1.075000 1.995000 1.325000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.449000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.365000 0.365000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.535000 0.715000 1.785000 0.895000 ; - RECT 0.535000 0.895000 0.810000 1.495000 ; - RECT 0.535000 1.495000 2.145000 1.705000 ; - RECT 0.555000 1.875000 1.340000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.545000 ; - RECT 1.035000 0.295000 2.285000 0.475000 ; - RECT 1.420000 0.645000 1.785000 0.715000 ; - RECT 1.735000 1.705000 2.145000 1.805000 ; - RECT 1.735000 1.805000 2.120000 2.465000 ; - RECT 1.955000 0.475000 2.285000 0.695000 ; - RECT 1.955000 0.695000 3.135000 0.865000 ; - RECT 2.455000 0.085000 2.625000 0.525000 ; - RECT 2.795000 0.280000 3.135000 0.695000 ; - RECT 2.815000 1.455000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o22a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.095000 1.075000 3.590000 1.275000 ; - RECT 3.270000 1.275000 3.590000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.595000 1.075000 2.925000 1.325000 ; - RECT 2.745000 1.325000 2.925000 1.445000 ; - RECT 2.745000 1.445000 3.100000 1.615000 ; - RECT 2.900000 1.615000 3.100000 2.405000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.435000 1.075000 1.790000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.960000 1.075000 2.425000 1.325000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.590000 0.365000 0.805000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.130000 -0.085000 0.300000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.115000 1.445000 0.365000 2.635000 ; - RECT 0.185000 0.085000 0.355000 0.885000 ; - RECT 0.975000 0.715000 2.215000 0.895000 ; - RECT 0.975000 0.895000 1.255000 1.495000 ; - RECT 0.975000 1.495000 2.575000 1.705000 ; - RECT 0.995000 1.875000 1.795000 2.635000 ; - RECT 1.025000 0.085000 1.205000 0.545000 ; - RECT 1.465000 0.295000 2.730000 0.475000 ; - RECT 1.850000 0.645000 2.215000 0.715000 ; - RECT 2.190000 1.705000 2.575000 2.465000 ; - RECT 2.390000 0.475000 2.730000 0.695000 ; - RECT 2.390000 0.695000 3.590000 0.825000 ; - RECT 2.560000 0.825000 3.590000 0.865000 ; - RECT 2.915000 0.085000 3.085000 0.525000 ; - RECT 3.255000 0.280000 3.590000 0.695000 ; - RECT 3.270000 1.795000 3.590000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o22a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.350000 1.075000 4.680000 1.445000 ; - RECT 4.350000 1.445000 5.735000 1.615000 ; - RECT 5.565000 1.075000 6.355000 1.275000 ; - RECT 5.565000 1.275000 5.735000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.900000 1.075000 5.395000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.420000 1.075000 2.955000 1.445000 ; - RECT 2.420000 1.445000 4.180000 1.615000 ; - RECT 3.850000 1.075000 4.180000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.125000 1.075000 3.680000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.725000 1.770000 0.905000 ; - RECT 0.085000 0.905000 0.370000 1.445000 ; - RECT 0.085000 1.445000 1.730000 1.615000 ; - RECT 0.600000 0.265000 0.930000 0.725000 ; - RECT 0.640000 1.615000 0.890000 2.465000 ; - RECT 1.440000 0.255000 1.770000 0.725000 ; - RECT 1.480000 1.615000 1.730000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.220000 1.825000 0.470000 2.635000 ; - RECT 0.260000 0.085000 0.430000 0.555000 ; - RECT 0.540000 1.075000 2.230000 1.275000 ; - RECT 1.060000 1.795000 1.310000 2.635000 ; - RECT 1.100000 0.085000 1.270000 0.555000 ; - RECT 1.900000 1.275000 2.230000 1.785000 ; - RECT 1.900000 1.785000 5.270000 1.955000 ; - RECT 1.900000 2.125000 2.670000 2.635000 ; - RECT 1.940000 0.085000 2.110000 0.555000 ; - RECT 1.940000 0.735000 3.970000 0.905000 ; - RECT 1.940000 0.905000 2.230000 1.075000 ; - RECT 2.380000 0.255000 4.470000 0.475000 ; - RECT 2.415000 0.645000 3.970000 0.735000 ; - RECT 2.840000 2.125000 3.090000 2.295000 ; - RECT 2.840000 2.295000 3.930000 2.465000 ; - RECT 3.260000 1.955000 3.510000 2.125000 ; - RECT 3.680000 2.125000 3.930000 2.295000 ; - RECT 4.100000 2.125000 4.430000 2.635000 ; - RECT 4.140000 0.475000 4.470000 0.735000 ; - RECT 4.140000 0.735000 6.150000 0.905000 ; - RECT 4.600000 2.125000 4.850000 2.295000 ; - RECT 4.600000 2.295000 5.690000 2.465000 ; - RECT 4.640000 0.085000 4.810000 0.555000 ; - RECT 4.980000 0.255000 5.310000 0.725000 ; - RECT 4.980000 0.725000 6.150000 0.735000 ; - RECT 5.020000 1.955000 5.270000 2.125000 ; - RECT 5.440000 1.785000 5.690000 2.295000 ; - RECT 5.480000 0.085000 5.650000 0.555000 ; - RECT 5.820000 0.255000 6.150000 0.725000 ; - RECT 5.905000 1.455000 6.110000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__o22a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.755000 1.075000 2.215000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.220000 1.075000 1.585000 1.245000 ; - RECT 1.405000 1.245000 1.585000 1.445000 ; - RECT 1.405000 1.445000 1.725000 1.615000 ; - RECT 1.525000 1.615000 1.725000 2.405000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.665000 0.325000 1.990000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.835000 0.995000 1.005000 1.415000 ; - RECT 0.835000 1.415000 1.235000 1.665000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.650250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.495000 0.645000 0.845000 0.825000 ; - RECT 0.495000 0.825000 0.665000 1.835000 ; - RECT 0.495000 1.835000 1.335000 2.045000 ; - RECT 0.835000 2.045000 1.335000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.085000 0.295000 1.345000 0.475000 ; - RECT 0.135000 2.175000 0.345000 2.635000 ; - RECT 1.015000 0.475000 1.345000 0.695000 ; - RECT 1.015000 0.695000 2.215000 0.825000 ; - RECT 1.185000 0.825000 2.215000 0.865000 ; - RECT 1.535000 0.085000 1.705000 0.525000 ; - RECT 1.875000 0.280000 2.215000 0.695000 ; - RECT 1.895000 1.455000 2.215000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__o22ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.395000 1.075000 4.165000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.555000 1.075000 3.225000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.200000 1.075000 0.985000 1.285000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.155000 1.075000 1.925000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.645000 0.865000 0.725000 ; - RECT 0.535000 0.725000 2.340000 0.905000 ; - RECT 1.375000 0.645000 1.705000 0.725000 ; - RECT 1.415000 1.445000 3.065000 1.625000 ; - RECT 1.415000 1.625000 1.665000 2.125000 ; - RECT 2.095000 0.905000 2.340000 1.445000 ; - RECT 2.815000 1.625000 3.065000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.090000 0.305000 2.680000 0.475000 ; - RECT 0.090000 0.475000 0.365000 0.905000 ; - RECT 0.150000 1.455000 1.245000 1.625000 ; - RECT 0.150000 1.625000 0.405000 2.465000 ; - RECT 0.575000 1.795000 0.825000 2.635000 ; - RECT 0.995000 1.625000 1.245000 2.295000 ; - RECT 0.995000 2.295000 2.085000 2.465000 ; - RECT 1.835000 1.795000 2.085000 2.295000 ; - RECT 2.395000 1.795000 2.645000 2.295000 ; - RECT 2.395000 2.295000 3.485000 2.465000 ; - RECT 2.510000 0.475000 2.680000 0.725000 ; - RECT 2.510000 0.725000 4.365000 0.905000 ; - RECT 2.855000 0.085000 3.025000 0.555000 ; - RECT 3.195000 0.255000 3.525000 0.725000 ; - RECT 3.235000 1.455000 4.330000 1.625000 ; - RECT 3.235000 1.625000 3.485000 2.295000 ; - RECT 3.655000 1.795000 3.905000 2.635000 ; - RECT 3.695000 0.085000 3.865000 0.555000 ; - RECT 4.035000 0.255000 4.365000 0.725000 ; - RECT 4.075000 1.625000 4.330000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__o22ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o22ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o22ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 1.415000 1.275000 ; - RECT 1.150000 1.275000 1.415000 1.445000 ; - RECT 1.150000 1.445000 3.575000 1.615000 ; - RECT 3.275000 1.075000 3.605000 1.245000 ; - RECT 3.275000 1.245000 3.575000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.685000 1.075000 3.095000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.295000 0.995000 4.940000 1.445000 ; - RECT 4.295000 1.445000 6.935000 1.615000 ; - RECT 6.715000 0.995000 6.935000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.110000 1.075000 6.460000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.845000 1.785000 3.915000 1.955000 ; - RECT 1.845000 1.955000 2.095000 2.125000 ; - RECT 2.685000 1.955000 2.935000 2.125000 ; - RECT 3.745000 1.445000 4.125000 1.615000 ; - RECT 3.745000 1.615000 3.915000 1.785000 ; - RECT 3.955000 0.645000 7.275000 0.820000 ; - RECT 3.955000 0.820000 4.125000 1.445000 ; - RECT 5.255000 1.785000 7.275000 1.955000 ; - RECT 5.255000 1.955000 5.505000 2.125000 ; - RECT 6.095000 1.955000 6.345000 2.125000 ; - RECT 7.105000 0.820000 7.275000 1.785000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.125000 0.255000 0.455000 0.725000 ; - RECT 0.125000 0.725000 1.295000 0.735000 ; - RECT 0.125000 0.735000 3.785000 0.905000 ; - RECT 0.165000 1.445000 0.415000 2.635000 ; - RECT 0.585000 1.445000 0.835000 1.785000 ; - RECT 0.585000 1.785000 1.675000 1.955000 ; - RECT 0.585000 1.955000 0.835000 2.465000 ; - RECT 0.625000 0.085000 0.795000 0.555000 ; - RECT 0.965000 0.255000 1.295000 0.725000 ; - RECT 1.005000 2.125000 1.255000 2.635000 ; - RECT 1.425000 1.955000 1.675000 2.295000 ; - RECT 1.425000 2.295000 3.395000 2.465000 ; - RECT 1.465000 0.085000 1.635000 0.555000 ; - RECT 1.805000 0.255000 2.135000 0.725000 ; - RECT 1.805000 0.725000 2.975000 0.735000 ; - RECT 2.265000 2.125000 2.515000 2.295000 ; - RECT 2.305000 0.085000 2.475000 0.555000 ; - RECT 2.645000 0.255000 2.975000 0.725000 ; - RECT 3.105000 2.125000 3.395000 2.295000 ; - RECT 3.145000 0.085000 3.315000 0.555000 ; - RECT 3.485000 0.255000 7.245000 0.475000 ; - RECT 3.485000 0.475000 3.785000 0.735000 ; - RECT 3.565000 2.125000 3.785000 2.635000 ; - RECT 3.955000 2.125000 4.255000 2.465000 ; - RECT 4.085000 1.785000 5.085000 1.955000 ; - RECT 4.085000 1.955000 4.255000 2.125000 ; - RECT 4.425000 2.125000 4.665000 2.635000 ; - RECT 4.835000 1.955000 5.085000 2.295000 ; - RECT 4.835000 2.295000 6.765000 2.465000 ; - RECT 5.675000 2.125000 5.925000 2.295000 ; - RECT 6.515000 2.135000 6.765000 2.295000 ; - RECT 6.935000 2.125000 7.215000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__o22ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.905000 0.995000 1.295000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.480000 0.995000 1.725000 1.325000 ; - RECT 1.525000 1.325000 1.725000 2.125000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.925000 0.995000 2.175000 2.125000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.390000 0.995000 2.795000 1.325000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.594000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.265000 0.525000 0.825000 ; - RECT 0.085000 0.825000 0.395000 1.835000 ; - RECT 0.085000 1.835000 0.525000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.565000 0.995000 0.735000 1.445000 ; - RECT 0.565000 1.445000 1.355000 1.615000 ; - RECT 0.695000 0.085000 1.145000 0.825000 ; - RECT 0.700000 1.785000 1.015000 2.635000 ; - RECT 1.185000 1.615000 1.355000 2.295000 ; - RECT 1.185000 2.295000 2.615000 2.465000 ; - RECT 1.315000 0.255000 1.485000 0.655000 ; - RECT 1.315000 0.655000 2.475000 0.825000 ; - RECT 1.655000 0.085000 2.075000 0.485000 ; - RECT 2.245000 0.255000 2.475000 0.655000 ; - RECT 2.365000 1.495000 3.135000 1.665000 ; - RECT 2.365000 1.665000 2.615000 2.295000 ; - RECT 2.645000 0.255000 3.135000 0.825000 ; - RECT 2.795000 1.835000 3.125000 2.635000 ; - RECT 2.965000 0.825000 3.135000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o31a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.370000 0.995000 1.760000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.945000 0.995000 2.190000 1.325000 ; - RECT 1.990000 1.325000 2.190000 2.125000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.390000 0.995000 2.640000 2.125000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.855000 0.995000 3.255000 1.325000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.577500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.860000 1.295000 ; - RECT 0.550000 0.265000 0.990000 0.825000 ; - RECT 0.550000 0.825000 0.860000 1.075000 ; - RECT 0.550000 1.295000 0.860000 1.835000 ; - RECT 0.550000 1.835000 0.990000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.085000 0.380000 0.905000 ; - RECT 0.085000 1.465000 0.380000 2.635000 ; - RECT 1.030000 0.995000 1.200000 1.445000 ; - RECT 1.030000 1.445000 1.820000 1.615000 ; - RECT 1.160000 0.085000 1.610000 0.825000 ; - RECT 1.165000 1.785000 1.480000 2.635000 ; - RECT 1.650000 1.615000 1.820000 2.295000 ; - RECT 1.650000 2.295000 3.080000 2.465000 ; - RECT 1.780000 0.255000 1.950000 0.655000 ; - RECT 1.780000 0.655000 2.940000 0.825000 ; - RECT 2.120000 0.085000 2.540000 0.485000 ; - RECT 2.710000 0.255000 2.940000 0.655000 ; - RECT 2.830000 1.495000 3.595000 1.665000 ; - RECT 2.830000 1.665000 3.080000 2.295000 ; - RECT 3.110000 0.255000 3.595000 0.825000 ; - RECT 3.255000 1.835000 3.590000 2.635000 ; - RECT 3.425000 0.825000 3.595000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o31a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.140000 1.055000 5.470000 1.360000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.265000 1.055000 4.970000 1.360000 ; - RECT 4.680000 1.360000 4.970000 1.530000 ; - RECT 4.680000 1.530000 6.355000 1.700000 ; - RECT 5.640000 1.055000 6.355000 1.530000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.765000 1.055000 4.095000 1.360000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.780000 1.055000 3.575000 1.355000 ; - RECT 2.780000 1.355000 3.150000 1.695000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 1.765000 0.885000 ; - RECT 0.085000 0.885000 0.735000 1.460000 ; - RECT 0.085000 1.460000 1.750000 1.665000 ; - RECT 0.680000 0.255000 0.895000 0.655000 ; - RECT 0.680000 0.655000 1.765000 0.715000 ; - RECT 0.680000 1.665000 0.895000 2.465000 ; - RECT 1.565000 0.255000 1.765000 0.655000 ; - RECT 1.565000 1.665000 1.750000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.125000 -0.085000 0.295000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.085000 0.085000 0.510000 0.545000 ; - RECT 0.085000 1.835000 0.510000 2.635000 ; - RECT 0.905000 1.055000 2.610000 1.290000 ; - RECT 1.065000 0.085000 1.395000 0.485000 ; - RECT 1.065000 1.835000 1.395000 2.635000 ; - RECT 1.920000 1.460000 2.250000 2.635000 ; - RECT 1.935000 0.085000 2.250000 0.885000 ; - RECT 2.440000 0.255000 3.570000 0.465000 ; - RECT 2.440000 0.635000 3.210000 0.885000 ; - RECT 2.440000 0.885000 2.610000 1.055000 ; - RECT 2.440000 1.290000 2.610000 1.870000 ; - RECT 2.440000 1.870000 4.090000 2.070000 ; - RECT 2.440000 2.070000 2.610000 2.465000 ; - RECT 2.780000 2.240000 3.110000 2.635000 ; - RECT 3.320000 1.530000 4.510000 1.700000 ; - RECT 3.380000 0.465000 3.570000 0.635000 ; - RECT 3.380000 0.635000 6.355000 0.885000 ; - RECT 3.760000 0.085000 4.090000 0.445000 ; - RECT 3.760000 2.070000 4.090000 2.465000 ; - RECT 4.260000 0.255000 4.430000 0.635000 ; - RECT 4.260000 1.700000 4.510000 2.465000 ; - RECT 4.600000 0.085000 4.930000 0.445000 ; - RECT 4.680000 1.870000 5.720000 2.070000 ; - RECT 4.680000 2.070000 4.850000 2.465000 ; - RECT 5.020000 2.240000 5.350000 2.635000 ; - RECT 5.100000 0.255000 5.270000 0.635000 ; - RECT 5.440000 0.085000 5.770000 0.445000 ; - RECT 5.520000 2.070000 5.720000 2.465000 ; - RECT 5.890000 1.870000 6.355000 2.465000 ; - RECT 5.940000 0.255000 6.355000 0.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.125000 4.455000 2.295000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.125000 6.295000 2.295000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - LAYER met1 ; - RECT 4.225000 2.095000 4.515000 2.140000 ; - RECT 4.225000 2.140000 6.355000 2.280000 ; - RECT 4.225000 2.280000 4.515000 2.325000 ; - RECT 6.065000 2.095000 6.355000 2.140000 ; - RECT 6.065000 2.280000 6.355000 2.325000 ; - END -END sky130_fd_sc_hd__o31a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.440000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 1.075000 1.055000 2.465000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.225000 1.075000 1.700000 1.325000 ; - RECT 1.460000 1.325000 1.700000 2.405000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.330000 0.995000 2.675000 1.325000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.006000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.945000 0.260000 2.675000 0.825000 ; - RECT 1.945000 0.825000 2.160000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 1.495000 0.440000 2.635000 ; - RECT 0.175000 0.085000 0.345000 0.905000 ; - RECT 0.515000 0.255000 0.845000 0.735000 ; - RECT 0.515000 0.735000 1.700000 0.905000 ; - RECT 1.015000 0.085000 1.185000 0.565000 ; - RECT 1.370000 0.255000 1.700000 0.735000 ; - RECT 2.330000 1.495000 2.675000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__o31ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.055000 1.240000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.410000 1.055000 2.220000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.390000 1.055000 3.205000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.175000 0.755000 4.515000 1.325000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.063500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.335000 1.495000 4.515000 1.665000 ; - RECT 2.335000 1.665000 2.665000 2.125000 ; - RECT 3.175000 1.665000 3.505000 2.465000 ; - RECT 3.675000 0.595000 4.005000 1.495000 ; - RECT 4.175000 1.665000 4.515000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.090000 0.255000 0.445000 0.715000 ; - RECT 0.090000 0.715000 3.505000 0.885000 ; - RECT 0.090000 1.495000 2.125000 1.665000 ; - RECT 0.090000 1.665000 0.445000 2.465000 ; - RECT 0.615000 0.085000 0.785000 0.545000 ; - RECT 0.615000 1.835000 0.785000 2.635000 ; - RECT 0.955000 0.255000 1.285000 0.715000 ; - RECT 0.955000 1.665000 1.285000 2.465000 ; - RECT 1.455000 0.085000 1.965000 0.545000 ; - RECT 1.455000 1.835000 1.625000 2.295000 ; - RECT 1.455000 2.295000 3.005000 2.465000 ; - RECT 1.795000 1.665000 2.125000 2.125000 ; - RECT 2.175000 0.255000 2.505000 0.715000 ; - RECT 2.675000 0.085000 3.005000 0.545000 ; - RECT 2.835000 1.835000 3.005000 2.295000 ; - RECT 3.175000 0.255000 4.515000 0.425000 ; - RECT 3.175000 0.425000 3.505000 0.715000 ; - RECT 3.675000 1.835000 4.005000 2.635000 ; - RECT 4.175000 0.425000 4.515000 0.585000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__o31ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o31ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o31ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.055000 1.780000 1.425000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.950000 1.055000 3.605000 1.425000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.775000 1.055000 5.940000 1.275000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.465000 1.055000 7.735000 1.275000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.683800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.775000 1.445000 7.735000 1.695000 ; - RECT 5.770000 1.695000 5.940000 2.465000 ; - RECT 6.110000 0.645000 7.280000 0.885000 ; - RECT 6.110000 0.885000 6.295000 1.445000 ; - RECT 6.610000 1.695000 6.780000 2.465000 ; - RECT 7.450000 1.695000 7.735000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.090000 0.255000 0.445000 0.715000 ; - RECT 0.090000 0.715000 5.940000 0.885000 ; - RECT 0.090000 1.595000 2.125000 1.895000 ; - RECT 0.090000 1.895000 0.445000 2.465000 ; - RECT 0.615000 0.085000 0.785000 0.545000 ; - RECT 0.615000 2.065000 0.785000 2.635000 ; - RECT 0.955000 0.255000 1.285000 0.715000 ; - RECT 0.955000 1.895000 1.285000 2.465000 ; - RECT 1.455000 0.085000 1.625000 0.545000 ; - RECT 1.455000 2.065000 1.625000 2.635000 ; - RECT 1.795000 0.255000 2.125000 0.715000 ; - RECT 1.795000 1.895000 2.125000 2.205000 ; - RECT 1.795000 2.205000 3.885000 2.465000 ; - RECT 2.295000 0.085000 2.465000 0.545000 ; - RECT 2.295000 1.595000 3.605000 1.765000 ; - RECT 2.295000 1.765000 2.465000 2.035000 ; - RECT 2.635000 0.255000 2.965000 0.715000 ; - RECT 2.635000 1.935000 2.965000 2.205000 ; - RECT 3.135000 0.085000 3.305000 0.545000 ; - RECT 3.135000 1.765000 3.605000 1.865000 ; - RECT 3.135000 1.865000 5.600000 2.035000 ; - RECT 3.475000 0.255000 3.805000 0.715000 ; - RECT 3.995000 0.085000 4.640000 0.545000 ; - RECT 4.080000 2.035000 5.600000 2.465000 ; - RECT 4.810000 0.395000 4.980000 0.715000 ; - RECT 5.150000 0.085000 5.600000 0.545000 ; - RECT 5.770000 0.255000 7.735000 0.475000 ; - RECT 5.770000 0.475000 5.940000 0.715000 ; - RECT 6.110000 1.890000 6.440000 2.635000 ; - RECT 6.950000 1.890000 7.280000 2.635000 ; - RECT 7.450000 0.475000 7.735000 0.885000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__o31ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.005000 0.995000 1.175000 1.075000 ; - RECT 1.005000 1.075000 1.255000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 0.995000 1.810000 1.325000 ; - RECT 1.485000 1.325000 1.810000 2.125000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.980000 0.995000 2.255000 1.660000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.320000 0.995000 3.595000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 0.995000 2.795000 1.660000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.504000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.595000 0.825000 ; - RECT 0.085000 0.825000 0.260000 1.495000 ; - RECT 0.085000 1.495000 0.470000 2.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.445000 0.995000 0.635000 1.075000 ; - RECT 0.445000 1.075000 0.810000 1.325000 ; - RECT 0.640000 1.325000 0.810000 1.495000 ; - RECT 0.640000 1.495000 1.315000 1.665000 ; - RECT 0.685000 1.835000 0.975000 2.635000 ; - RECT 0.765000 0.085000 0.935000 0.645000 ; - RECT 1.140000 0.255000 1.470000 0.655000 ; - RECT 1.140000 0.655000 2.540000 0.825000 ; - RECT 1.145000 1.665000 1.315000 2.295000 ; - RECT 1.145000 2.295000 2.510000 2.465000 ; - RECT 1.645000 0.085000 1.975000 0.485000 ; - RECT 2.180000 1.835000 3.135000 2.085000 ; - RECT 2.180000 2.085000 2.510000 2.295000 ; - RECT 2.210000 0.255000 3.595000 0.465000 ; - RECT 2.210000 0.465000 2.540000 0.655000 ; - RECT 2.710000 0.635000 3.135000 0.825000 ; - RECT 2.965000 0.825000 3.135000 1.835000 ; - RECT 3.305000 0.465000 3.595000 0.735000 ; - RECT 3.305000 1.495000 3.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o32a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.495000 0.995000 1.715000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.995000 2.160000 1.615000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.415000 0.995000 2.635000 1.615000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.695000 1.075000 4.055000 1.245000 ; - RECT 3.725000 1.245000 4.055000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.910000 0.995000 3.155000 1.615000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.845000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.885000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 1.015000 0.995000 1.325000 1.785000 ; - RECT 1.015000 1.785000 3.525000 1.955000 ; - RECT 1.015000 2.125000 1.525000 2.635000 ; - RECT 1.095000 0.085000 1.425000 0.825000 ; - RECT 1.695000 0.255000 2.025000 0.655000 ; - RECT 1.695000 0.655000 3.025000 0.825000 ; - RECT 2.195000 0.085000 2.525000 0.485000 ; - RECT 2.695000 0.255000 4.055000 0.425000 ; - RECT 2.695000 0.425000 3.025000 0.655000 ; - RECT 2.695000 1.955000 3.025000 2.465000 ; - RECT 3.195000 0.595000 3.525000 0.825000 ; - RECT 3.325000 0.825000 3.525000 1.785000 ; - RECT 3.695000 0.425000 4.055000 0.905000 ; - RECT 3.695000 1.495000 4.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o32a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 1.075000 0.780000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.070000 1.075000 1.700000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.010000 1.075000 2.625000 1.275000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.870000 1.075000 4.230000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.790000 1.075000 5.260000 1.275000 ; - END - END B2 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.305000 0.255000 6.635000 0.715000 ; - RECT 6.305000 0.715000 8.135000 0.905000 ; - RECT 6.305000 1.495000 8.135000 1.665000 ; - RECT 6.305000 1.665000 6.635000 2.465000 ; - RECT 7.145000 0.255000 7.475000 0.715000 ; - RECT 7.145000 1.665000 7.475000 2.465000 ; - RECT 7.645000 0.905000 8.135000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.635000 ; - RECT 0.085000 0.635000 2.965000 0.885000 ; - RECT 0.085000 1.445000 1.265000 1.665000 ; - RECT 0.085000 1.665000 0.425000 2.465000 ; - RECT 0.515000 0.085000 2.545000 0.465000 ; - RECT 0.595000 1.835000 0.765000 2.635000 ; - RECT 0.935000 1.665000 1.265000 2.295000 ; - RECT 0.935000 2.295000 2.105000 2.465000 ; - RECT 1.435000 1.445000 2.625000 1.690000 ; - RECT 1.435000 1.690000 1.605000 2.045000 ; - RECT 1.775000 1.860000 2.105000 2.295000 ; - RECT 2.295000 1.690000 2.625000 2.295000 ; - RECT 2.295000 2.295000 3.465000 2.465000 ; - RECT 2.715000 0.255000 5.695000 0.465000 ; - RECT 2.715000 0.465000 2.965000 0.635000 ; - RECT 2.795000 1.105000 3.645000 1.275000 ; - RECT 2.795000 1.275000 2.965000 2.045000 ; - RECT 3.135000 1.445000 3.465000 2.295000 ; - RECT 3.455000 0.635000 5.775000 0.805000 ; - RECT 3.455000 0.805000 3.645000 1.105000 ; - RECT 3.655000 1.445000 3.985000 1.785000 ; - RECT 3.655000 1.785000 4.825000 1.955000 ; - RECT 3.655000 1.955000 3.985000 2.465000 ; - RECT 4.155000 2.125000 4.325000 2.635000 ; - RECT 4.400000 0.805000 4.620000 1.445000 ; - RECT 4.400000 1.445000 5.195000 1.615000 ; - RECT 4.495000 1.955000 4.825000 2.285000 ; - RECT 4.495000 2.285000 5.695000 2.465000 ; - RECT 5.025000 1.615000 5.195000 2.115000 ; - RECT 5.365000 1.445000 5.695000 2.285000 ; - RECT 5.520000 0.805000 5.775000 1.075000 ; - RECT 5.520000 1.075000 7.475000 1.245000 ; - RECT 5.520000 1.245000 6.135000 1.265000 ; - RECT 5.965000 0.085000 6.135000 0.885000 ; - RECT 5.965000 1.835000 6.135000 2.635000 ; - RECT 6.805000 0.085000 6.975000 0.545000 ; - RECT 6.805000 1.835000 6.975000 2.635000 ; - RECT 7.645000 0.085000 7.900000 0.545000 ; - RECT 7.645000 1.835000 7.900000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - END -END sky130_fd_sc_hd__o32a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.575000 0.995000 3.135000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.930000 0.995000 2.225000 2.465000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.410000 0.995000 1.700000 1.615000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.685000 0.345000 0.995000 ; - RECT 0.090000 0.995000 0.360000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.870000 0.995000 1.240000 1.615000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.821250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.655000 0.845000 0.825000 ; - RECT 0.530000 0.825000 0.700000 1.785000 ; - RECT 0.530000 1.785000 1.545000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.090000 0.255000 1.345000 0.485000 ; - RECT 0.090000 1.495000 0.360000 2.635000 ; - RECT 1.015000 0.485000 1.345000 0.655000 ; - RECT 1.015000 0.655000 2.525000 0.825000 ; - RECT 1.515000 0.085000 2.185000 0.485000 ; - RECT 2.355000 0.375000 2.525000 0.655000 ; - RECT 2.695000 0.085000 3.135000 0.825000 ; - RECT 2.695000 1.495000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o32ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.750000 1.075000 5.865000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.370000 1.075000 4.480000 1.325000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 1.075000 3.065000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.015000 1.075000 1.705000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.845000 1.325000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.655000 2.045000 0.905000 ; - RECT 0.515000 1.495000 3.105000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.095000 ; - RECT 1.875000 0.905000 2.045000 1.105000 ; - RECT 1.875000 1.105000 2.170000 1.495000 ; - RECT 2.775000 1.665000 3.105000 2.085000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.090000 0.255000 2.405000 0.485000 ; - RECT 0.090000 0.485000 0.345000 0.905000 ; - RECT 0.090000 1.495000 0.345000 2.295000 ; - RECT 0.090000 2.295000 1.265000 2.465000 ; - RECT 1.015000 1.835000 2.105000 2.005000 ; - RECT 1.015000 2.005000 1.265000 2.295000 ; - RECT 1.435000 2.175000 1.605000 2.635000 ; - RECT 1.775000 2.005000 2.105000 2.455000 ; - RECT 2.235000 0.485000 2.405000 0.715000 ; - RECT 2.235000 0.715000 5.755000 0.905000 ; - RECT 2.335000 1.835000 2.585000 2.255000 ; - RECT 2.335000 2.255000 4.385000 2.445000 ; - RECT 2.620000 0.085000 2.950000 0.545000 ; - RECT 3.135000 0.255000 3.465000 0.715000 ; - RECT 3.275000 1.495000 3.445000 2.255000 ; - RECT 3.615000 1.495000 5.325000 1.665000 ; - RECT 3.615000 1.665000 3.945000 2.085000 ; - RECT 3.635000 0.085000 3.805000 0.545000 ; - RECT 4.055000 0.255000 4.725000 0.715000 ; - RECT 4.135000 1.835000 4.385000 2.255000 ; - RECT 4.620000 1.835000 4.825000 2.635000 ; - RECT 4.905000 0.085000 5.235000 0.545000 ; - RECT 4.995000 1.665000 5.325000 2.460000 ; - RECT 5.425000 0.255000 5.755000 0.715000 ; - RECT 5.495000 1.495000 5.715000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__o32ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o32ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o32ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.290000 1.075000 10.035000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.090000 1.075000 7.260000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.770000 1.075000 5.380000 1.275000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.205000 1.075000 3.540000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.110000 1.075000 1.685000 1.275000 ; - END - END B2 - PIN Y - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.655000 3.380000 0.905000 ; - RECT 0.515000 1.495000 5.580000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.085000 ; - RECT 1.355000 1.665000 1.700000 2.085000 ; - RECT 1.855000 0.905000 2.035000 1.495000 ; - RECT 4.410000 1.665000 4.740000 2.085000 ; - RECT 5.250000 1.665000 5.580000 2.085000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.090000 0.255000 3.800000 0.465000 ; - RECT 0.090000 0.465000 0.345000 0.905000 ; - RECT 0.090000 1.495000 0.345000 2.255000 ; - RECT 0.090000 2.255000 2.040000 2.465000 ; - RECT 1.015000 1.835000 1.185000 2.255000 ; - RECT 1.870000 1.835000 3.800000 2.005000 ; - RECT 1.870000 2.005000 2.040000 2.255000 ; - RECT 2.210000 2.175000 2.540000 2.635000 ; - RECT 2.710000 2.005000 2.880000 2.425000 ; - RECT 3.050000 2.175000 3.380000 2.635000 ; - RECT 3.550000 0.465000 3.800000 0.735000 ; - RECT 3.550000 0.735000 10.035000 0.905000 ; - RECT 3.550000 2.005000 3.800000 2.465000 ; - RECT 3.970000 0.085000 4.140000 0.545000 ; - RECT 3.990000 1.835000 4.240000 2.255000 ; - RECT 3.990000 2.255000 7.680000 2.465000 ; - RECT 4.310000 0.255000 4.640000 0.735000 ; - RECT 4.810000 0.085000 5.140000 0.545000 ; - RECT 4.910000 1.835000 5.080000 2.255000 ; - RECT 5.310000 0.255000 5.980000 0.735000 ; - RECT 5.750000 1.835000 5.920000 2.255000 ; - RECT 6.090000 1.495000 9.460000 1.665000 ; - RECT 6.090000 1.665000 6.420000 2.085000 ; - RECT 6.170000 0.085000 6.340000 0.545000 ; - RECT 6.510000 0.255000 6.840000 0.735000 ; - RECT 6.590000 1.835000 6.760000 2.255000 ; - RECT 6.930000 1.665000 7.260000 2.085000 ; - RECT 7.010000 0.085000 7.180000 0.545000 ; - RECT 7.350000 0.255000 8.040000 0.735000 ; - RECT 7.430000 1.835000 7.680000 2.255000 ; - RECT 7.870000 1.835000 8.120000 2.635000 ; - RECT 8.290000 1.665000 8.620000 2.465000 ; - RECT 8.370000 0.085000 8.540000 0.545000 ; - RECT 8.710000 0.255000 9.040000 0.735000 ; - RECT 8.790000 1.835000 8.960000 2.635000 ; - RECT 9.130000 1.665000 9.460000 2.465000 ; - RECT 9.210000 0.085000 9.470000 0.545000 ; - RECT 9.630000 1.495000 10.035000 2.635000 ; - RECT 9.645000 0.255000 10.035000 0.735000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__o32ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.485000 1.075000 3.995000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.905000 1.075000 3.275000 2.390000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 1.075000 2.735000 2.390000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.865000 1.075000 2.195000 2.390000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.275000 1.075000 1.695000 1.285000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.672000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.425000 0.885000 ; - RECT 0.085000 0.885000 0.355000 1.455000 ; - RECT 0.085000 1.455000 0.610000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.525000 1.075000 1.105000 1.285000 ; - RECT 0.715000 0.085000 0.885000 0.545000 ; - RECT 0.735000 0.715000 1.485000 0.905000 ; - RECT 0.735000 0.905000 1.105000 1.075000 ; - RECT 0.845000 1.285000 1.105000 1.455000 ; - RECT 0.845000 1.455000 1.595000 1.745000 ; - RECT 0.845000 1.915000 1.175000 2.635000 ; - RECT 1.155000 0.270000 1.485000 0.715000 ; - RECT 1.345000 1.745000 1.595000 2.465000 ; - RECT 1.655000 0.415000 1.825000 0.735000 ; - RECT 1.655000 0.735000 3.955000 0.905000 ; - RECT 2.050000 0.085000 2.380000 0.545000 ; - RECT 2.580000 0.255000 2.910000 0.735000 ; - RECT 3.125000 0.085000 3.455000 0.545000 ; - RECT 3.605000 1.515000 3.935000 2.635000 ; - RECT 3.625000 0.255000 3.955000 0.735000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o41a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 1.075000 4.515000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.325000 1.075000 3.655000 2.335000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.825000 1.075000 3.155000 2.340000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.325000 1.075000 2.655000 2.340000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.775000 1.075000 2.155000 1.325000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.845000 0.880000 ; - RECT 0.515000 0.880000 0.790000 1.495000 ; - RECT 0.515000 1.495000 0.845000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.885000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 0.960000 1.075000 1.600000 1.325000 ; - RECT 1.015000 0.085000 1.260000 0.885000 ; - RECT 1.015000 1.495000 1.185000 1.835000 ; - RECT 1.015000 1.835000 1.525000 2.635000 ; - RECT 1.355000 1.325000 1.600000 1.495000 ; - RECT 1.355000 1.495000 2.145000 1.665000 ; - RECT 1.430000 0.255000 1.785000 0.850000 ; - RECT 1.430000 0.850000 1.600000 1.075000 ; - RECT 1.695000 1.665000 2.145000 2.465000 ; - RECT 1.985000 0.255000 2.315000 0.715000 ; - RECT 1.985000 0.715000 4.395000 0.905000 ; - RECT 2.485000 0.085000 2.750000 0.545000 ; - RECT 2.955000 0.255000 3.285000 0.715000 ; - RECT 3.505000 0.085000 3.775000 0.545000 ; - RECT 4.065000 0.255000 4.395000 0.715000 ; - RECT 4.065000 1.495000 4.395000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__o41a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.650000 1.075000 7.735000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.150000 1.075000 6.360000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.330000 1.075000 4.960000 1.275000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.410000 1.075000 4.040000 1.275000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.835000 1.075000 3.165000 1.275000 ; - END - END B1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.715000 1.685000 0.905000 ; - RECT 0.085000 0.905000 0.345000 1.465000 ; - RECT 0.085000 1.465000 1.685000 1.665000 ; - RECT 0.515000 0.255000 0.845000 0.715000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 1.355000 0.255000 1.685000 0.715000 ; - RECT 1.355000 1.665000 1.685000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.545000 ; - RECT 0.085000 1.835000 0.345000 2.635000 ; - RECT 0.515000 1.075000 2.665000 1.245000 ; - RECT 0.515000 1.245000 2.545000 1.295000 ; - RECT 1.015000 0.085000 1.185000 0.545000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.855000 0.085000 2.105000 0.885000 ; - RECT 1.855000 1.465000 2.025000 2.635000 ; - RECT 2.195000 1.295000 2.545000 1.445000 ; - RECT 2.195000 1.445000 3.825000 1.615000 ; - RECT 2.195000 1.615000 2.545000 2.465000 ; - RECT 2.295000 0.255000 3.485000 0.465000 ; - RECT 2.295000 0.635000 3.045000 0.905000 ; - RECT 2.295000 0.905000 2.665000 1.075000 ; - RECT 2.715000 1.835000 2.965000 2.635000 ; - RECT 3.135000 1.835000 3.405000 2.295000 ; - RECT 3.135000 2.295000 4.325000 2.465000 ; - RECT 3.235000 0.465000 3.485000 0.735000 ; - RECT 3.235000 0.735000 7.595000 0.905000 ; - RECT 3.575000 1.615000 3.825000 2.125000 ; - RECT 3.655000 0.085000 3.875000 0.545000 ; - RECT 3.995000 1.445000 5.165000 1.615000 ; - RECT 3.995000 1.615000 4.325000 2.295000 ; - RECT 4.075000 0.255000 4.245000 0.735000 ; - RECT 4.445000 0.085000 4.715000 0.545000 ; - RECT 4.495000 1.785000 4.665000 2.295000 ; - RECT 4.495000 2.295000 6.145000 2.465000 ; - RECT 4.835000 1.615000 5.165000 2.115000 ; - RECT 4.915000 0.255000 5.085000 0.735000 ; - RECT 5.305000 0.085000 5.915000 0.545000 ; - RECT 5.395000 1.445000 7.595000 1.615000 ; - RECT 5.395000 1.615000 5.645000 2.115000 ; - RECT 5.815000 1.785000 6.145000 2.295000 ; - RECT 6.240000 0.255000 6.410000 0.735000 ; - RECT 6.315000 1.615000 6.485000 2.455000 ; - RECT 6.655000 1.785000 6.985000 2.635000 ; - RECT 6.685000 0.085000 6.955000 0.545000 ; - RECT 7.265000 0.255000 7.595000 0.735000 ; - RECT 7.265000 1.615000 7.595000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__o41a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.500000 1.075000 3.080000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 1.415000 2.330000 2.355000 ; - RECT 2.000000 1.075000 2.330000 1.415000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.500000 1.075000 1.830000 1.245000 ; - RECT 1.500000 1.245000 1.820000 2.355000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.990000 1.075000 1.320000 1.245000 ; - RECT 1.015000 1.245000 1.320000 2.355000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 0.440000 1.275000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.439000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.425000 0.735000 ; - RECT 0.085000 0.735000 0.780000 0.905000 ; - RECT 0.515000 1.485000 0.845000 2.465000 ; - RECT 0.610000 0.905000 0.780000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.445000 0.345000 2.635000 ; - RECT 0.790000 0.255000 1.120000 0.565000 ; - RECT 0.950000 0.565000 1.120000 0.735000 ; - RECT 0.950000 0.735000 2.960000 0.905000 ; - RECT 1.290000 0.085000 1.540000 0.565000 ; - RECT 1.710000 0.255000 2.040000 0.735000 ; - RECT 2.210000 0.085000 2.460000 0.565000 ; - RECT 2.630000 0.255000 2.960000 0.735000 ; - RECT 2.630000 1.495000 2.960000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o41ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.720000 1.075000 5.895000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.780000 1.075000 4.540000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.595000 1.075000 3.580000 1.275000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.500000 1.075000 2.325000 1.275000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 0.440000 1.275000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 0.715500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.635000 0.845000 0.885000 ; - RECT 0.515000 1.505000 2.205000 1.665000 ; - RECT 0.515000 1.665000 0.845000 2.465000 ; - RECT 0.610000 0.885000 0.845000 1.445000 ; - RECT 0.610000 1.445000 2.205000 1.505000 ; - RECT 1.875000 1.665000 2.205000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.255000 1.265000 0.465000 ; - RECT 0.085000 0.465000 0.345000 0.905000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 1.015000 0.465000 1.265000 0.735000 ; - RECT 1.015000 0.735000 5.705000 0.905000 ; - RECT 1.015000 1.835000 1.265000 2.635000 ; - RECT 1.455000 0.085000 1.705000 0.545000 ; - RECT 1.455000 1.835000 1.705000 2.295000 ; - RECT 1.455000 2.295000 2.545000 2.465000 ; - RECT 1.875000 0.255000 2.205000 0.735000 ; - RECT 2.375000 0.085000 2.545000 0.545000 ; - RECT 2.375000 1.445000 3.465000 1.615000 ; - RECT 2.375000 1.615000 2.545000 2.295000 ; - RECT 2.715000 0.255000 3.045000 0.735000 ; - RECT 2.715000 1.835000 3.045000 2.295000 ; - RECT 2.715000 2.295000 4.445000 2.465000 ; - RECT 3.215000 0.085000 3.450000 0.545000 ; - RECT 3.215000 1.615000 3.465000 2.125000 ; - RECT 3.695000 0.255000 4.025000 0.735000 ; - RECT 3.695000 1.445000 5.705000 1.615000 ; - RECT 3.695000 1.615000 3.945000 2.125000 ; - RECT 4.115000 1.835000 4.445000 2.295000 ; - RECT 4.195000 0.085000 4.365000 0.545000 ; - RECT 4.535000 0.255000 4.865000 0.735000 ; - RECT 4.615000 1.615000 4.785000 2.465000 ; - RECT 4.955000 1.785000 5.285000 2.635000 ; - RECT 5.035000 0.085000 5.205000 0.545000 ; - RECT 5.375000 0.255000 5.705000 0.735000 ; - RECT 5.455000 1.615000 5.705000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__o41ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o41ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o41ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.155000 1.075000 10.035000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.170000 1.075000 7.940000 1.275000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.310000 1.075000 5.980000 1.275000 ; - END - END A3 - PIN A4 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.350000 1.075000 4.020000 1.275000 ; - END - END A4 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 1.075000 1.700000 1.275000 ; - END - END B1 - PIN Y - ANTENNADIFFAREA 1.431000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.635000 2.160000 0.905000 ; - RECT 0.515000 1.445000 3.885000 1.615000 ; - RECT 0.515000 1.615000 0.845000 2.465000 ; - RECT 1.355000 1.615000 1.685000 2.465000 ; - RECT 1.870000 0.905000 2.160000 1.445000 ; - RECT 2.715000 1.615000 3.045000 2.125000 ; - RECT 3.555000 1.615000 3.885000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.085000 0.255000 2.625000 0.465000 ; - RECT 0.085000 0.465000 0.345000 0.905000 ; - RECT 0.085000 1.445000 0.345000 2.635000 ; - RECT 1.015000 1.835000 1.185000 2.635000 ; - RECT 1.855000 1.835000 2.105000 2.635000 ; - RECT 2.295000 1.785000 2.545000 2.295000 ; - RECT 2.295000 2.295000 4.225000 2.465000 ; - RECT 2.350000 0.465000 2.625000 0.735000 ; - RECT 2.350000 0.735000 9.865000 0.905000 ; - RECT 2.795000 0.085000 2.965000 0.545000 ; - RECT 3.135000 0.255000 3.465000 0.735000 ; - RECT 3.215000 1.785000 3.385000 2.295000 ; - RECT 3.635000 0.085000 3.805000 0.545000 ; - RECT 3.975000 0.255000 4.305000 0.735000 ; - RECT 4.055000 1.445000 5.985000 1.615000 ; - RECT 4.055000 1.615000 4.225000 2.295000 ; - RECT 4.395000 1.785000 4.645000 2.295000 ; - RECT 4.395000 2.295000 7.685000 2.465000 ; - RECT 4.475000 0.085000 4.645000 0.545000 ; - RECT 4.815000 0.255000 5.145000 0.735000 ; - RECT 4.815000 1.615000 5.145000 2.125000 ; - RECT 5.315000 0.085000 5.485000 0.545000 ; - RECT 5.315000 1.785000 5.485000 2.295000 ; - RECT 5.655000 0.255000 5.985000 0.735000 ; - RECT 5.655000 1.615000 5.985000 2.125000 ; - RECT 6.175000 0.260000 6.505000 0.735000 ; - RECT 6.175000 1.445000 9.865000 1.615000 ; - RECT 6.175000 1.615000 6.505000 2.125000 ; - RECT 6.675000 0.085000 6.845000 0.545000 ; - RECT 6.675000 1.785000 6.845000 2.295000 ; - RECT 7.015000 0.260000 7.345000 0.735000 ; - RECT 7.015000 1.615000 7.345000 2.125000 ; - RECT 7.515000 0.085000 7.685000 0.545000 ; - RECT 7.515000 1.785000 7.685000 2.295000 ; - RECT 7.855000 0.260000 8.185000 0.735000 ; - RECT 7.855000 1.615000 8.185000 2.465000 ; - RECT 8.355000 0.085000 8.525000 0.545000 ; - RECT 8.355000 1.835000 8.525000 2.635000 ; - RECT 8.695000 0.260000 9.025000 0.735000 ; - RECT 8.695000 1.615000 9.025000 2.465000 ; - RECT 9.195000 0.085000 9.365000 0.545000 ; - RECT 9.195000 1.835000 9.365000 2.635000 ; - RECT 9.535000 0.260000 9.865000 0.735000 ; - RECT 9.535000 1.615000 9.865000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END -END sky130_fd_sc_hd__o41ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.300000 1.075000 1.720000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.890000 1.075000 2.220000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.390000 1.075000 2.720000 1.275000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.245000 1.075000 3.595000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.425000 0.885000 ; - RECT 0.085000 0.885000 0.260000 1.495000 ; - RECT 0.085000 1.495000 0.425000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.430000 1.075000 1.125000 1.245000 ; - RECT 0.595000 0.085000 0.845000 0.885000 ; - RECT 0.595000 1.495000 0.765000 2.635000 ; - RECT 0.955000 1.245000 1.125000 1.495000 ; - RECT 0.955000 1.495000 3.390000 1.665000 ; - RECT 1.035000 0.255000 1.365000 0.735000 ; - RECT 1.035000 0.735000 2.260000 0.905000 ; - RECT 1.035000 1.835000 1.285000 2.635000 ; - RECT 1.535000 0.085000 1.760000 0.545000 ; - RECT 1.930000 0.255000 2.260000 0.735000 ; - RECT 1.930000 1.665000 2.260000 2.465000 ; - RECT 2.560000 1.835000 2.890000 2.635000 ; - RECT 2.890000 0.255000 3.390000 0.865000 ; - RECT 2.890000 0.865000 3.060000 1.495000 ; - RECT 3.060000 1.665000 3.390000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o211a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.990000 0.995000 2.325000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.530000 0.995000 1.820000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.880000 0.995000 1.240000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.360000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.720000 0.255000 3.050000 0.615000 ; - RECT 2.720000 0.615000 3.540000 0.785000 ; - RECT 2.810000 1.905000 3.540000 2.075000 ; - RECT 2.810000 2.075000 3.000000 2.465000 ; - RECT 3.345000 0.785000 3.540000 1.905000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.090000 1.510000 2.665000 1.765000 ; - RECT 0.090000 1.765000 0.355000 2.465000 ; - RECT 0.095000 0.255000 0.430000 0.425000 ; - RECT 0.095000 0.425000 0.710000 0.825000 ; - RECT 0.525000 1.935000 0.855000 2.635000 ; - RECT 0.530000 0.825000 0.710000 1.510000 ; - RECT 0.880000 0.635000 2.150000 0.825000 ; - RECT 1.025000 1.765000 1.695000 2.465000 ; - RECT 1.390000 0.085000 1.725000 0.465000 ; - RECT 2.200000 1.935000 2.630000 2.635000 ; - RECT 2.315000 0.085000 2.550000 0.525000 ; - RECT 2.495000 0.995000 3.175000 1.325000 ; - RECT 2.495000 1.325000 2.665000 1.510000 ; - RECT 3.170000 2.255000 3.500000 2.635000 ; - RECT 3.220000 0.085000 3.550000 0.445000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o211a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.440000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.490000 1.035000 4.845000 1.495000 ; - RECT 4.490000 1.495000 6.290000 1.685000 ; - RECT 5.890000 1.035000 6.290000 1.495000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.030000 1.035000 5.705000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.540000 0.995000 2.830000 1.445000 ; - RECT 2.540000 1.445000 4.280000 1.685000 ; - RECT 3.950000 1.035000 4.280000 1.445000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.055000 1.035000 3.740000 1.275000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.911000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.635000 1.605000 0.805000 ; - RECT 0.085000 0.805000 0.365000 1.435000 ; - RECT 0.085000 1.435000 2.030000 1.700000 ; - RECT 0.595000 0.255000 0.765000 0.615000 ; - RECT 0.595000 0.615000 1.605000 0.635000 ; - RECT 0.980000 1.700000 1.160000 2.465000 ; - RECT 1.435000 0.255000 1.605000 0.615000 ; - RECT 1.840000 1.700000 2.030000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.440000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.630000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.440000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.440000 0.085000 ; - RECT 0.000000 2.635000 6.440000 2.805000 ; - RECT 0.095000 0.085000 0.425000 0.465000 ; - RECT 0.480000 1.870000 0.810000 2.635000 ; - RECT 0.535000 1.065000 2.370000 1.265000 ; - RECT 0.935000 0.085000 1.265000 0.445000 ; - RECT 1.340000 1.870000 1.670000 2.635000 ; - RECT 1.775000 0.085000 2.140000 0.465000 ; - RECT 2.200000 0.635000 3.520000 0.815000 ; - RECT 2.200000 0.815000 2.370000 1.065000 ; - RECT 2.200000 1.265000 2.370000 1.855000 ; - RECT 2.200000 1.855000 5.485000 2.025000 ; - RECT 2.200000 2.200000 2.530000 2.635000 ; - RECT 2.330000 0.255000 4.500000 0.465000 ; - RECT 2.700000 2.025000 3.060000 2.465000 ; - RECT 3.285000 2.195000 3.615000 2.635000 ; - RECT 3.785000 2.025000 4.120000 2.465000 ; - RECT 4.170000 0.465000 4.500000 0.695000 ; - RECT 4.170000 0.695000 6.345000 0.865000 ; - RECT 4.290000 2.195000 4.555000 2.635000 ; - RECT 4.670000 0.085000 4.985000 0.525000 ; - RECT 5.155000 0.255000 5.485000 0.695000 ; - RECT 5.155000 2.025000 5.485000 2.465000 ; - RECT 5.655000 0.085000 5.845000 0.525000 ; - RECT 6.015000 0.255000 6.345000 0.695000 ; - RECT 6.015000 1.915000 6.345000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - END -END sky130_fd_sc_hd__o211a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.395000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.995000 0.980000 1.325000 ; - RECT 0.605000 1.325000 0.775000 2.250000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.300000 0.995000 1.795000 1.325000 ; - RECT 1.470000 1.325000 1.795000 1.615000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.970000 1.075000 2.300000 1.615000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.418250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 1.595000 1.275000 1.815000 ; - RECT 0.945000 1.815000 2.675000 2.045000 ; - RECT 0.945000 2.045000 1.275000 2.445000 ; - RECT 1.965000 0.255000 2.675000 0.845000 ; - RECT 1.975000 2.045000 2.675000 2.465000 ; - RECT 2.470000 0.845000 2.675000 1.815000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.095000 0.255000 0.425000 0.615000 ; - RECT 0.095000 0.615000 1.455000 0.825000 ; - RECT 0.095000 1.575000 0.425000 2.635000 ; - RECT 0.595000 0.085000 0.925000 0.445000 ; - RECT 1.125000 0.255000 1.455000 0.615000 ; - RECT 1.445000 2.275000 1.775000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__o211ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.505000 1.075000 4.455000 1.245000 ; - RECT 3.560000 1.245000 4.455000 1.295000 ; - RECT 4.115000 0.765000 4.455000 1.075000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.365000 1.075000 3.335000 1.355000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.045000 1.075000 1.905000 1.365000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.375000 1.970000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.022000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 0.670000 0.875000 1.540000 ; - RECT 0.545000 1.540000 3.155000 1.710000 ; - RECT 0.545000 1.710000 0.805000 2.465000 ; - RECT 1.475000 1.710000 1.665000 2.465000 ; - RECT 2.825000 1.710000 3.155000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.095000 0.255000 2.165000 0.445000 ; - RECT 0.115000 2.175000 0.375000 2.635000 ; - RECT 0.975000 1.915000 1.305000 2.635000 ; - RECT 1.045000 0.445000 2.165000 0.465000 ; - RECT 1.045000 0.465000 1.235000 0.890000 ; - RECT 1.405000 0.635000 3.945000 0.845000 ; - RECT 1.835000 1.915000 2.165000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.445000 ; - RECT 2.395000 2.100000 2.655000 2.295000 ; - RECT 2.395000 2.295000 3.515000 2.465000 ; - RECT 3.255000 0.085000 3.585000 0.445000 ; - RECT 3.325000 1.525000 4.445000 1.695000 ; - RECT 3.325000 1.695000 3.515000 2.295000 ; - RECT 3.685000 1.865000 4.015000 2.635000 ; - RECT 3.755000 0.515000 3.945000 0.635000 ; - RECT 4.115000 0.085000 4.445000 0.445000 ; - RECT 4.185000 1.695000 4.445000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__o211ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o211ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o211ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.400000 1.075000 1.410000 1.330000 ; - RECT 0.965000 1.330000 1.410000 1.515000 ; - RECT 0.965000 1.515000 3.630000 1.685000 ; - RECT 3.350000 0.995000 3.630000 1.515000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.705000 1.075000 3.180000 1.345000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.800000 0.995000 4.975000 1.410000 ; - RECT 4.260000 1.410000 4.975000 1.515000 ; - RECT 4.260000 1.515000 7.000000 1.685000 ; - RECT 6.830000 0.995000 7.000000 1.515000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.370000 1.075000 6.440000 1.345000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 2.001000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.805000 1.855000 7.680000 2.025000 ; - RECT 1.805000 2.025000 3.470000 2.105000 ; - RECT 4.045000 2.025000 7.680000 2.105000 ; - RECT 5.280000 0.270000 6.735000 0.450000 ; - RECT 6.565000 0.450000 6.735000 0.655000 ; - RECT 6.565000 0.655000 7.350000 0.825000 ; - RECT 7.170000 0.825000 7.350000 1.340000 ; - RECT 7.170000 1.340000 7.680000 1.855000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.090000 1.665000 0.385000 2.635000 ; - RECT 0.155000 0.535000 0.355000 0.625000 ; - RECT 0.155000 0.625000 1.240000 0.695000 ; - RECT 0.155000 0.695000 3.835000 0.795000 ; - RECT 0.155000 0.795000 3.130000 0.865000 ; - RECT 0.155000 0.865000 1.795000 0.905000 ; - RECT 0.525000 0.085000 0.855000 0.445000 ; - RECT 0.555000 1.860000 0.775000 1.935000 ; - RECT 0.555000 1.935000 1.635000 2.105000 ; - RECT 0.555000 2.105000 0.775000 2.190000 ; - RECT 0.955000 2.275000 1.285000 2.635000 ; - RECT 1.025000 0.425000 1.240000 0.625000 ; - RECT 1.455000 2.105000 1.635000 2.275000 ; - RECT 1.455000 2.275000 3.435000 2.465000 ; - RECT 1.465000 0.085000 1.635000 0.525000 ; - RECT 1.775000 0.625000 3.835000 0.695000 ; - RECT 2.245000 0.085000 2.575000 0.445000 ; - RECT 3.105000 0.085000 3.435000 0.445000 ; - RECT 3.605000 0.255000 4.920000 0.455000 ; - RECT 3.605000 0.455000 3.835000 0.625000 ; - RECT 3.615000 2.195000 3.885000 2.635000 ; - RECT 4.005000 0.635000 6.170000 0.815000 ; - RECT 4.435000 2.275000 4.765000 2.635000 ; - RECT 5.280000 2.275000 5.610000 2.635000 ; - RECT 6.120000 2.275000 6.455000 2.635000 ; - RECT 6.980000 0.310000 7.680000 0.480000 ; - RECT 7.355000 2.275000 7.685000 2.635000 ; - RECT 7.510000 0.480000 7.680000 0.595000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.070000 0.425000 1.240000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 0.425000 7.680000 0.595000 ; - LAYER met1 ; - RECT 1.010000 0.395000 1.300000 0.440000 ; - RECT 1.010000 0.440000 7.740000 0.580000 ; - RECT 1.010000 0.580000 1.300000 0.625000 ; - RECT 7.450000 0.395000 7.740000 0.440000 ; - RECT 7.450000 0.580000 7.740000 0.625000 ; - END -END sky130_fd_sc_hd__o211ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.680000 1.075000 3.130000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.005000 1.075000 2.490000 1.285000 ; - RECT 2.005000 1.285000 2.380000 1.705000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.925000 1.075000 1.255000 1.285000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.435000 1.075000 1.815000 1.325000 ; - RECT 1.495000 1.325000 1.815000 1.705000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.415000 1.285000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.370000 0.265000 4.055000 0.905000 ; - RECT 3.390000 1.875000 4.055000 2.465000 ; - RECT 3.805000 0.905000 4.055000 1.875000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.240000 1.455000 1.325000 1.625000 ; - RECT 0.240000 1.625000 0.540000 2.465000 ; - RECT 0.245000 0.255000 0.575000 0.645000 ; - RECT 0.245000 0.645000 0.755000 0.825000 ; - RECT 0.585000 0.825000 0.755000 1.455000 ; - RECT 0.735000 1.795000 0.985000 2.635000 ; - RECT 0.745000 0.305000 1.930000 0.475000 ; - RECT 1.155000 1.625000 1.325000 1.875000 ; - RECT 1.155000 1.875000 2.720000 2.045000 ; - RECT 1.160000 0.645000 1.545000 0.735000 ; - RECT 1.160000 0.735000 2.860000 0.905000 ; - RECT 1.575000 2.045000 2.380000 2.465000 ; - RECT 2.190000 0.085000 2.360000 0.555000 ; - RECT 2.530000 0.270000 2.860000 0.735000 ; - RECT 2.550000 1.455000 3.470000 1.625000 ; - RECT 2.550000 1.625000 2.720000 1.875000 ; - RECT 2.890000 1.795000 3.220000 2.635000 ; - RECT 3.030000 0.085000 3.200000 0.905000 ; - RECT 3.300000 1.075000 3.635000 1.285000 ; - RECT 3.300000 1.285000 3.470000 1.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o221a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.635000 1.075000 3.075000 1.285000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.980000 1.075000 2.465000 1.285000 ; - RECT 1.980000 1.285000 2.285000 1.705000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.885000 1.075000 1.230000 1.275000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.400000 1.075000 1.790000 1.275000 ; - RECT 1.500000 1.275000 1.790000 1.705000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.345000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.295000 0.265000 3.625000 0.735000 ; - RECT 3.295000 0.735000 4.055000 0.905000 ; - RECT 3.295000 1.875000 4.055000 2.045000 ; - RECT 3.295000 2.045000 3.545000 2.465000 ; - RECT 3.745000 0.905000 4.055000 1.875000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.120000 -0.085000 0.290000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.170000 0.255000 0.500000 0.635000 ; - RECT 0.170000 0.635000 0.715000 0.805000 ; - RECT 0.250000 1.495000 1.330000 1.670000 ; - RECT 0.250000 1.670000 0.580000 2.465000 ; - RECT 0.545000 0.805000 0.715000 1.445000 ; - RECT 0.545000 1.445000 1.330000 1.495000 ; - RECT 0.670000 0.295000 1.855000 0.465000 ; - RECT 0.750000 1.850000 0.990000 2.635000 ; - RECT 1.085000 0.645000 1.470000 0.735000 ; - RECT 1.085000 0.735000 2.785000 0.905000 ; - RECT 1.160000 1.670000 1.330000 1.875000 ; - RECT 1.160000 1.875000 2.625000 2.045000 ; - RECT 1.550000 2.045000 2.305000 2.465000 ; - RECT 2.115000 0.085000 2.285000 0.555000 ; - RECT 2.455000 0.270000 2.785000 0.735000 ; - RECT 2.455000 1.455000 3.415000 1.625000 ; - RECT 2.455000 1.625000 2.625000 1.875000 ; - RECT 2.795000 1.795000 3.125000 2.635000 ; - RECT 2.955000 0.085000 3.125000 0.905000 ; - RECT 3.245000 1.075000 3.575000 1.285000 ; - RECT 3.245000 1.285000 3.415000 1.455000 ; - RECT 3.715000 2.215000 4.055000 2.635000 ; - RECT 3.795000 0.085000 3.965000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o221a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.005000 1.075000 3.605000 1.445000 ; - RECT 3.005000 1.445000 4.775000 1.615000 ; - RECT 4.525000 1.075000 5.035000 1.275000 ; - RECT 4.525000 1.275000 4.775000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.775000 1.075000 4.355000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.025000 1.075000 1.520000 1.445000 ; - RECT 1.025000 1.445000 2.745000 1.615000 ; - RECT 2.415000 1.075000 2.745000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.690000 1.075000 2.245000 1.275000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.440000 1.275000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.235000 0.255000 5.565000 0.725000 ; - RECT 5.235000 0.725000 6.405000 0.735000 ; - RECT 5.235000 0.735000 6.920000 0.905000 ; - RECT 5.315000 1.785000 5.900000 1.955000 ; - RECT 5.315000 1.955000 5.525000 2.465000 ; - RECT 5.730000 1.445000 6.920000 1.615000 ; - RECT 5.730000 1.615000 5.900000 1.785000 ; - RECT 6.075000 0.255000 6.405000 0.725000 ; - RECT 6.115000 1.615000 6.365000 2.465000 ; - RECT 6.575000 0.905000 6.920000 1.445000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.085000 0.255000 2.955000 0.475000 ; - RECT 0.085000 0.475000 0.345000 0.895000 ; - RECT 0.145000 1.455000 0.395000 2.635000 ; - RECT 0.515000 0.645000 0.845000 0.865000 ; - RECT 0.565000 1.445000 0.845000 1.785000 ; - RECT 0.565000 1.785000 5.145000 1.955000 ; - RECT 0.565000 1.955000 0.815000 2.465000 ; - RECT 0.610000 0.865000 0.845000 1.445000 ; - RECT 0.985000 2.125000 1.235000 2.635000 ; - RECT 1.015000 0.475000 1.185000 0.905000 ; - RECT 1.355000 0.645000 2.535000 0.715000 ; - RECT 1.355000 0.715000 3.885000 0.725000 ; - RECT 1.355000 0.725000 4.725000 0.905000 ; - RECT 1.405000 2.125000 1.655000 2.295000 ; - RECT 1.405000 2.295000 2.495000 2.465000 ; - RECT 1.825000 1.955000 2.075000 2.125000 ; - RECT 2.245000 2.125000 2.495000 2.295000 ; - RECT 2.665000 2.125000 3.425000 2.635000 ; - RECT 3.145000 0.085000 3.385000 0.545000 ; - RECT 3.555000 0.255000 3.885000 0.715000 ; - RECT 3.595000 2.125000 3.845000 2.295000 ; - RECT 3.595000 2.295000 4.685000 2.465000 ; - RECT 4.015000 1.955000 4.265000 2.125000 ; - RECT 4.055000 0.085000 4.225000 0.555000 ; - RECT 4.395000 0.255000 4.725000 0.725000 ; - RECT 4.435000 2.125000 4.685000 2.295000 ; - RECT 4.855000 2.125000 5.105000 2.635000 ; - RECT 4.895000 0.085000 5.065000 0.905000 ; - RECT 4.975000 1.445000 5.375000 1.615000 ; - RECT 4.975000 1.615000 5.145000 1.785000 ; - RECT 5.205000 1.075000 6.405000 1.275000 ; - RECT 5.205000 1.275000 5.375000 1.445000 ; - RECT 5.695000 2.125000 5.945000 2.635000 ; - RECT 5.735000 0.085000 5.905000 0.555000 ; - RECT 6.535000 1.795000 6.785000 2.635000 ; - RECT 6.575000 0.085000 6.830000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__o221a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.675000 1.075000 3.135000 1.275000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.165000 1.075000 2.505000 1.245000 ; - RECT 2.295000 1.245000 2.505000 1.445000 ; - RECT 2.295000 1.445000 2.675000 1.615000 ; - RECT 2.465000 1.615000 2.675000 2.405000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.995000 1.355000 1.325000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.995000 1.985000 1.325000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.465000 1.325000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.899000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.365000 0.345000 0.645000 ; - RECT 0.085000 0.645000 0.840000 0.825000 ; - RECT 0.085000 1.495000 2.125000 1.705000 ; - RECT 0.085000 1.705000 0.365000 2.465000 ; - RECT 0.635000 0.825000 0.840000 1.495000 ; - RECT 1.735000 1.705000 2.125000 1.785000 ; - RECT 1.735000 1.785000 2.245000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.515000 0.305000 1.775000 0.475000 ; - RECT 0.550000 1.875000 1.340000 2.635000 ; - RECT 1.010000 0.645000 2.220000 0.695000 ; - RECT 1.010000 0.695000 3.135000 0.825000 ; - RECT 1.945000 0.280000 2.220000 0.645000 ; - RECT 2.105000 0.825000 3.135000 0.865000 ; - RECT 2.455000 0.085000 2.625000 0.525000 ; - RECT 2.795000 0.280000 3.135000 0.695000 ; - RECT 2.875000 1.455000 3.135000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o221ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.430000 1.075000 3.760000 1.445000 ; - RECT 3.430000 1.445000 4.815000 1.615000 ; - RECT 4.645000 1.075000 5.435000 1.275000 ; - RECT 4.645000 1.275000 4.815000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.980000 1.075000 4.475000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.020000 1.075000 2.035000 1.445000 ; - RECT 1.020000 1.445000 3.260000 1.615000 ; - RECT 2.930000 1.075000 3.260000 1.445000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.205000 1.075000 2.760000 1.275000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.435000 1.275000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.985500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.520000 0.645000 0.850000 0.865000 ; - RECT 0.560000 1.445000 0.850000 1.785000 ; - RECT 0.560000 1.785000 4.350000 1.955000 ; - RECT 0.560000 1.955000 0.810000 2.465000 ; - RECT 0.605000 0.865000 0.850000 1.445000 ; - RECT 2.340000 1.955000 2.590000 2.125000 ; - RECT 4.100000 1.955000 4.350000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.100000 0.255000 1.270000 0.475000 ; - RECT 0.100000 0.475000 0.350000 0.895000 ; - RECT 0.140000 1.455000 0.390000 2.635000 ; - RECT 0.980000 2.125000 1.750000 2.635000 ; - RECT 1.020000 0.475000 1.270000 0.645000 ; - RECT 1.020000 0.645000 3.050000 0.905000 ; - RECT 1.460000 0.255000 3.550000 0.475000 ; - RECT 1.920000 2.125000 2.170000 2.295000 ; - RECT 1.920000 2.295000 3.010000 2.465000 ; - RECT 2.760000 2.125000 3.010000 2.295000 ; - RECT 3.180000 2.125000 3.510000 2.635000 ; - RECT 3.220000 0.475000 3.550000 0.735000 ; - RECT 3.220000 0.735000 5.230000 0.905000 ; - RECT 3.680000 2.125000 3.930000 2.295000 ; - RECT 3.680000 2.295000 4.770000 2.465000 ; - RECT 3.720000 0.085000 3.890000 0.555000 ; - RECT 4.060000 0.255000 4.390000 0.725000 ; - RECT 4.060000 0.725000 5.230000 0.735000 ; - RECT 4.520000 1.785000 4.770000 2.295000 ; - RECT 4.560000 0.085000 4.730000 0.555000 ; - RECT 4.900000 0.255000 5.230000 0.725000 ; - RECT 4.985000 1.455000 5.190000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__o221ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o221ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o221ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.965000 1.075000 6.295000 1.445000 ; - RECT 5.965000 1.445000 8.420000 1.615000 ; - RECT 8.155000 1.075000 9.575000 1.275000 ; - RECT 8.155000 1.275000 8.420000 1.445000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.475000 1.075000 7.885000 1.275000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.360000 1.075000 4.505000 1.275000 ; - RECT 4.335000 1.275000 4.505000 1.495000 ; - RECT 4.335000 1.495000 5.795000 1.665000 ; - RECT 5.465000 1.075000 5.795000 1.495000 ; - END - END B1 - PIN B2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.675000 0.995000 5.285000 1.325000 ; - END - END B2 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 1.750000 1.275000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.971000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.535000 0.645000 2.125000 0.865000 ; - RECT 0.575000 1.445000 4.165000 1.615000 ; - RECT 0.575000 1.615000 0.825000 2.465000 ; - RECT 1.415000 1.615000 2.125000 1.955000 ; - RECT 1.415000 1.955000 1.665000 2.465000 ; - RECT 1.920000 0.865000 2.125000 1.445000 ; - RECT 3.995000 1.615000 4.165000 1.835000 ; - RECT 3.995000 1.835000 7.725000 1.955000 ; - RECT 3.995000 1.955000 6.885000 2.005000 ; - RECT 3.995000 2.005000 4.285000 2.125000 ; - RECT 4.875000 2.005000 5.085000 2.125000 ; - RECT 5.965000 1.785000 7.725000 1.835000 ; - RECT 6.675000 2.005000 6.885000 2.125000 ; - RECT 7.475000 1.955000 7.725000 2.125000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.115000 0.255000 5.585000 0.475000 ; - RECT 0.115000 0.475000 0.365000 0.895000 ; - RECT 0.155000 1.485000 0.405000 2.635000 ; - RECT 0.995000 1.825000 1.245000 2.635000 ; - RECT 1.835000 2.125000 2.605000 2.635000 ; - RECT 2.315000 0.645000 6.085000 0.735000 ; - RECT 2.315000 0.735000 9.445000 0.820000 ; - RECT 2.775000 1.785000 3.825000 1.955000 ; - RECT 2.775000 1.955000 3.025000 2.465000 ; - RECT 3.195000 2.125000 3.445000 2.635000 ; - RECT 3.615000 1.955000 3.825000 2.295000 ; - RECT 3.615000 2.295000 5.585000 2.465000 ; - RECT 4.455000 2.175000 4.705000 2.295000 ; - RECT 5.255000 2.175000 5.585000 2.295000 ; - RECT 5.465000 0.820000 9.445000 0.905000 ; - RECT 5.755000 0.255000 6.085000 0.645000 ; - RECT 5.755000 2.175000 6.005000 2.635000 ; - RECT 6.175000 2.175000 6.505000 2.295000 ; - RECT 6.175000 2.295000 8.145000 2.465000 ; - RECT 6.255000 0.085000 6.425000 0.555000 ; - RECT 6.595000 0.255000 6.925000 0.725000 ; - RECT 6.595000 0.725000 7.765000 0.735000 ; - RECT 7.055000 2.125000 7.305000 2.295000 ; - RECT 7.095000 0.085000 7.265000 0.555000 ; - RECT 7.435000 0.255000 7.765000 0.725000 ; - RECT 7.895000 1.785000 8.985000 1.955000 ; - RECT 7.895000 1.955000 8.145000 2.295000 ; - RECT 7.935000 0.085000 8.105000 0.555000 ; - RECT 8.275000 0.255000 8.605000 0.725000 ; - RECT 8.275000 0.725000 9.445000 0.735000 ; - RECT 8.315000 2.125000 8.565000 2.635000 ; - RECT 8.735000 1.445000 8.985000 1.785000 ; - RECT 8.735000 1.955000 8.985000 2.465000 ; - RECT 8.775000 0.085000 8.945000 0.555000 ; - RECT 9.115000 0.255000 9.445000 0.725000 ; - RECT 9.155000 1.445000 9.405000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__o221ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.995000 1.280000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.450000 0.995000 1.790000 1.325000 ; - RECT 1.520000 1.325000 1.790000 2.070000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.980000 0.995000 2.270000 1.325000 ; - RECT 1.980000 1.325000 2.215000 2.070000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 0.995000 2.840000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.350000 0.995000 3.595000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.355000 1.070000 ; - RECT 0.085000 1.070000 0.435000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.525000 0.085000 1.195000 0.825000 ; - RECT 0.605000 0.995000 0.775000 1.495000 ; - RECT 0.605000 1.495000 1.350000 1.665000 ; - RECT 0.605000 1.835000 1.010000 2.635000 ; - RECT 1.180000 1.665000 1.350000 2.295000 ; - RECT 1.180000 2.295000 2.715000 2.465000 ; - RECT 1.365000 0.310000 1.660000 0.655000 ; - RECT 1.365000 0.655000 2.760000 0.825000 ; - RECT 1.840000 0.085000 2.215000 0.485000 ; - RECT 2.385000 1.495000 3.595000 1.665000 ; - RECT 2.385000 1.665000 2.715000 2.295000 ; - RECT 2.430000 0.310000 2.760000 0.655000 ; - RECT 2.900000 1.835000 3.135000 2.635000 ; - RECT 3.010000 0.255000 3.595000 0.825000 ; - RECT 3.010000 0.825000 3.180000 1.495000 ; - RECT 3.305000 1.665000 3.595000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__o311a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 0.995000 1.750000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.920000 0.995000 2.250000 1.325000 ; - RECT 1.980000 1.325000 2.250000 2.070000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 0.995000 2.730000 1.325000 ; - RECT 2.440000 1.325000 2.675000 2.070000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.900000 0.995000 3.300000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.810000 0.995000 4.055000 1.325000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.905000 1.315000 ; - RECT 0.550000 0.255000 0.825000 0.995000 ; - RECT 0.550000 0.995000 0.905000 1.055000 ; - RECT 0.550000 1.315000 0.905000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.085000 0.380000 0.885000 ; - RECT 0.085000 1.485000 0.380000 2.635000 ; - RECT 0.995000 0.085000 1.665000 0.825000 ; - RECT 1.075000 0.995000 1.245000 1.495000 ; - RECT 1.075000 1.495000 1.810000 1.665000 ; - RECT 1.075000 1.835000 1.470000 2.635000 ; - RECT 1.640000 1.665000 1.810000 2.295000 ; - RECT 1.640000 2.295000 3.175000 2.465000 ; - RECT 1.835000 0.310000 2.120000 0.655000 ; - RECT 1.835000 0.655000 3.220000 0.825000 ; - RECT 2.300000 0.085000 2.675000 0.485000 ; - RECT 2.845000 1.495000 4.055000 1.665000 ; - RECT 2.845000 1.665000 3.175000 2.295000 ; - RECT 2.890000 0.310000 3.220000 0.655000 ; - RECT 3.360000 1.835000 3.595000 2.635000 ; - RECT 3.470000 0.255000 4.055000 0.825000 ; - RECT 3.470000 0.825000 3.640000 1.495000 ; - RECT 3.765000 1.665000 4.055000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o311a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.820000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.950000 1.055000 7.735000 1.315000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.020000 1.055000 6.770000 1.315000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.655000 1.055000 5.850000 1.315000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.250000 1.055000 4.475000 1.315000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.115000 1.055000 3.080000 1.315000 ; - END - END C1 - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 0.765000 1.315000 ; - RECT 0.595000 0.255000 0.765000 0.715000 ; - RECT 0.595000 0.715000 1.605000 0.885000 ; - RECT 0.595000 0.885000 0.765000 1.055000 ; - RECT 0.595000 1.315000 0.765000 1.485000 ; - RECT 0.595000 1.485000 1.605000 1.725000 ; - RECT 0.595000 1.725000 0.765000 2.465000 ; - RECT 1.435000 0.255000 1.605000 0.715000 ; - RECT 1.435000 1.725000 1.605000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.820000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.010000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.820000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.820000 0.085000 ; - RECT 0.000000 2.635000 7.820000 2.805000 ; - RECT 0.085000 0.085000 0.425000 0.885000 ; - RECT 0.085000 1.485000 0.425000 2.635000 ; - RECT 0.935000 0.085000 1.265000 0.545000 ; - RECT 0.935000 1.055000 1.945000 1.315000 ; - RECT 0.935000 1.895000 1.265000 2.635000 ; - RECT 1.775000 0.085000 2.025000 0.545000 ; - RECT 1.775000 0.715000 3.045000 0.885000 ; - RECT 1.775000 0.885000 1.945000 1.055000 ; - RECT 1.775000 1.315000 1.945000 1.485000 ; - RECT 1.775000 1.485000 5.005000 1.725000 ; - RECT 1.775000 1.895000 2.445000 2.635000 ; - RECT 2.195000 0.255000 4.305000 0.505000 ; - RECT 2.195000 0.675000 3.045000 0.715000 ; - RECT 2.615000 1.725000 2.785000 2.465000 ; - RECT 2.955000 1.895000 3.285000 2.635000 ; - RECT 3.215000 0.505000 3.385000 0.885000 ; - RECT 3.455000 1.725000 3.625000 2.465000 ; - RECT 3.555000 0.675000 7.735000 0.885000 ; - RECT 3.855000 1.895000 4.045000 2.635000 ; - RECT 4.335000 1.895000 4.665000 2.295000 ; - RECT 4.335000 2.295000 6.445000 2.465000 ; - RECT 4.485000 0.255000 4.755000 0.675000 ; - RECT 4.835000 1.725000 5.005000 2.125000 ; - RECT 4.925000 0.085000 5.605000 0.505000 ; - RECT 5.255000 1.485000 5.525000 2.295000 ; - RECT 5.695000 1.485000 7.735000 1.725000 ; - RECT 5.695000 1.725000 5.945000 2.125000 ; - RECT 5.775000 0.255000 5.945000 0.675000 ; - RECT 6.115000 0.085000 6.445000 0.505000 ; - RECT 6.115000 1.895000 6.445000 2.295000 ; - RECT 6.615000 0.255000 6.785000 0.675000 ; - RECT 6.615000 1.725000 6.785000 2.125000 ; - RECT 6.955000 0.085000 7.285000 0.505000 ; - RECT 6.955000 1.895000 7.285000 2.635000 ; - RECT 7.455000 0.255000 7.735000 0.675000 ; - RECT 7.455000 1.725000 7.735000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - END -END sky130_fd_sc_hd__o311a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311ai_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311ai_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.570000 0.995000 ; - RECT 0.085000 0.995000 0.780000 1.625000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.995000 1.260000 2.465000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.430000 0.995000 1.780000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.260000 2.200000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.830000 0.765000 3.135000 1.325000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.604000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.430000 1.495000 3.135000 1.665000 ; - RECT 1.430000 1.665000 1.980000 2.465000 ; - RECT 2.445000 0.255000 3.135000 0.595000 ; - RECT 2.445000 0.595000 2.660000 1.495000 ; - RECT 2.650000 1.665000 3.135000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.570000 0.595000 ; - RECT 0.085000 1.795000 0.780000 2.635000 ; - RECT 0.740000 0.255000 0.910000 0.655000 ; - RECT 0.740000 0.655000 1.750000 0.825000 ; - RECT 1.080000 0.085000 1.410000 0.485000 ; - RECT 1.580000 0.255000 1.750000 0.655000 ; - RECT 2.150000 1.835000 2.480000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o311ai_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.780000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.995000 1.260000 2.465000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.430000 0.995000 1.780000 1.325000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.320000 2.200000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.830000 0.995000 3.135000 1.325000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 0.942000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.430000 1.495000 3.135000 1.665000 ; - RECT 1.430000 1.665000 1.980000 2.465000 ; - RECT 2.445000 0.255000 3.135000 0.825000 ; - RECT 2.445000 0.825000 2.660000 1.495000 ; - RECT 2.650000 1.665000 3.135000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.570000 0.825000 ; - RECT 0.085000 1.495000 0.780000 2.635000 ; - RECT 0.740000 0.255000 0.910000 0.655000 ; - RECT 0.740000 0.655000 1.750000 0.825000 ; - RECT 1.080000 0.085000 1.410000 0.485000 ; - RECT 1.580000 0.255000 1.750000 0.655000 ; - RECT 2.150000 1.835000 2.480000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o311ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 1.105000 1.315000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.275000 1.055000 2.155000 1.315000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.325000 1.055000 3.075000 1.315000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.365000 1.055000 4.385000 1.315000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.085000 1.055000 5.895000 1.315000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 1.551000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.415000 1.485000 5.895000 1.725000 ; - RECT 2.415000 1.725000 2.665000 2.125000 ; - RECT 3.335000 1.725000 3.505000 2.465000 ; - RECT 4.515000 1.725000 4.825000 2.465000 ; - RECT 4.555000 0.655000 5.895000 0.885000 ; - RECT 4.555000 0.885000 4.915000 1.485000 ; - RECT 5.495000 1.725000 5.895000 2.465000 ; - RECT 5.515000 0.255000 5.895000 0.655000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.255000 0.485000 0.655000 ; - RECT 0.085000 0.655000 4.385000 0.885000 ; - RECT 0.085000 1.485000 2.225000 1.725000 ; - RECT 0.085000 1.725000 0.465000 2.465000 ; - RECT 0.635000 1.895000 0.965000 2.635000 ; - RECT 0.655000 0.085000 0.985000 0.485000 ; - RECT 1.135000 1.725000 1.305000 2.465000 ; - RECT 1.155000 0.255000 1.325000 0.655000 ; - RECT 1.475000 1.895000 1.805000 2.295000 ; - RECT 1.475000 2.295000 3.165000 2.465000 ; - RECT 1.495000 0.085000 1.825000 0.485000 ; - RECT 1.975000 1.725000 2.225000 2.125000 ; - RECT 1.995000 0.255000 2.165000 0.655000 ; - RECT 2.335000 0.085000 3.105000 0.485000 ; - RECT 2.835000 1.895000 3.165000 2.295000 ; - RECT 3.275000 0.255000 3.445000 0.655000 ; - RECT 3.615000 0.255000 5.345000 0.485000 ; - RECT 3.675000 1.895000 4.345000 2.635000 ; - RECT 4.995000 1.895000 5.325000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - END -END sky130_fd_sc_hd__o311ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o311ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o311ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.055000 1.775000 1.315000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.945000 1.055000 3.615000 1.315000 ; - END - END A2 - PIN A3 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 1.055000 5.885000 1.315000 ; - END - END A3 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.055000 1.055000 7.695000 1.315000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.865000 1.055000 9.090000 1.315000 ; - END - END C1 - PIN Y - ANTENNADIFFAREA 2.241000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.055000 1.485000 9.575000 1.725000 ; - RECT 4.055000 1.725000 4.305000 2.115000 ; - RECT 4.975000 1.725000 5.145000 2.115000 ; - RECT 5.815000 1.725000 6.005000 2.465000 ; - RECT 6.675000 1.725000 6.845000 2.465000 ; - RECT 7.515000 1.725000 7.685000 2.465000 ; - RECT 7.895000 0.655000 9.575000 0.885000 ; - RECT 8.355000 1.725000 8.525000 2.465000 ; - RECT 9.195000 1.725000 9.575000 2.465000 ; - RECT 9.260000 0.885000 9.575000 1.485000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.125000 -0.085000 0.295000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.085000 0.085000 0.505000 0.885000 ; - RECT 0.085000 1.485000 3.865000 1.725000 ; - RECT 0.085000 1.725000 0.405000 2.465000 ; - RECT 0.595000 1.895000 0.925000 2.635000 ; - RECT 0.675000 0.255000 0.845000 0.655000 ; - RECT 0.675000 0.655000 7.385000 0.885000 ; - RECT 1.015000 0.085000 1.345000 0.485000 ; - RECT 1.095000 1.725000 1.265000 2.465000 ; - RECT 1.435000 1.895000 1.765000 2.635000 ; - RECT 1.515000 0.255000 1.685000 0.655000 ; - RECT 1.855000 0.085000 2.185000 0.485000 ; - RECT 1.935000 1.725000 2.105000 2.465000 ; - RECT 2.275000 1.895000 2.605000 2.295000 ; - RECT 2.275000 2.295000 5.645000 2.465000 ; - RECT 2.355000 0.255000 2.525000 0.655000 ; - RECT 2.695000 0.085000 3.025000 0.485000 ; - RECT 2.775000 1.725000 2.945000 2.115000 ; - RECT 3.115000 1.895000 3.445000 2.295000 ; - RECT 3.195000 0.255000 3.365000 0.655000 ; - RECT 3.535000 0.085000 3.885000 0.485000 ; - RECT 3.615000 1.725000 3.865000 2.115000 ; - RECT 4.055000 0.255000 4.225000 0.655000 ; - RECT 4.395000 0.085000 4.725000 0.485000 ; - RECT 4.475000 1.895000 4.805000 2.295000 ; - RECT 4.895000 0.255000 5.065000 0.655000 ; - RECT 5.235000 0.085000 5.585000 0.485000 ; - RECT 5.315000 1.895000 5.645000 2.295000 ; - RECT 5.755000 0.255000 9.575000 0.485000 ; - RECT 6.175000 1.895000 6.505000 2.635000 ; - RECT 7.015000 1.895000 7.345000 2.635000 ; - RECT 7.555000 0.485000 7.725000 0.885000 ; - RECT 7.855000 1.895000 8.185000 2.635000 ; - RECT 8.695000 1.895000 9.025000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__o311ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111a_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111a_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.705000 1.075000 4.035000 1.660000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.050000 1.075000 3.535000 1.325000 ; - RECT 3.350000 1.325000 3.535000 2.415000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.445000 0.390000 2.690000 0.995000 ; - RECT 2.445000 0.995000 2.705000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.925000 0.390000 2.195000 1.325000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.265000 1.075000 1.745000 1.325000 ; - RECT 1.535000 0.390000 1.745000 1.075000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.095000 0.255000 0.355000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.525000 0.995000 0.865000 1.325000 ; - RECT 0.525000 1.835000 1.335000 2.635000 ; - RECT 0.535000 0.085000 0.845000 0.565000 ; - RECT 0.695000 0.735000 1.365000 0.905000 ; - RECT 0.695000 0.905000 0.865000 0.995000 ; - RECT 0.695000 1.325000 0.865000 1.495000 ; - RECT 0.695000 1.495000 3.180000 1.665000 ; - RECT 1.025000 0.255000 1.365000 0.735000 ; - RECT 1.505000 1.665000 1.835000 2.465000 ; - RECT 2.020000 1.835000 2.760000 2.635000 ; - RECT 2.870000 0.255000 3.160000 0.705000 ; - RECT 2.870000 0.705000 4.055000 0.875000 ; - RECT 2.930000 1.665000 3.180000 2.465000 ; - RECT 3.330000 0.085000 3.620000 0.535000 ; - RECT 3.730000 1.835000 4.055000 2.635000 ; - RECT 3.790000 0.255000 4.055000 0.705000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__o2111a_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111a_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111a_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.830000 1.005000 4.515000 1.315000 ; - RECT 4.310000 1.315000 4.515000 2.355000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.300000 0.995000 3.660000 1.325000 ; - RECT 3.370000 1.325000 3.660000 2.370000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.680000 1.075000 3.100000 1.615000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.005000 0.255000 2.390000 1.615000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.505000 1.075000 1.835000 1.615000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.515000 0.255000 0.855000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.135000 0.085000 0.345000 0.885000 ; - RECT 0.135000 1.495000 0.345000 2.635000 ; - RECT 1.030000 0.715000 1.805000 0.885000 ; - RECT 1.030000 0.885000 1.305000 1.785000 ; - RECT 1.030000 1.785000 3.195000 2.025000 ; - RECT 1.035000 0.085000 1.285000 0.545000 ; - RECT 1.035000 2.195000 1.655000 2.635000 ; - RECT 1.475000 0.255000 1.805000 0.715000 ; - RECT 1.860000 2.025000 2.140000 2.465000 ; - RECT 2.325000 2.255000 2.655000 2.635000 ; - RECT 2.865000 0.255000 3.195000 0.625000 ; - RECT 2.865000 0.625000 4.215000 0.825000 ; - RECT 2.865000 2.025000 3.195000 2.465000 ; - RECT 3.385000 0.085000 3.715000 0.455000 ; - RECT 3.885000 0.255000 4.215000 0.625000 ; - RECT 3.885000 1.495000 4.140000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__o2111a_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111a_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111a_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.890000 1.075000 4.485000 1.245000 ; - RECT 4.130000 1.245000 4.485000 1.320000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.135000 1.075000 3.600000 1.245000 ; - RECT 3.145000 1.245000 3.600000 1.320000 ; - RECT 3.305000 1.320000 3.600000 1.490000 ; - RECT 3.305000 1.490000 4.825000 1.660000 ; - RECT 4.655000 1.075000 4.985000 1.320000 ; - RECT 4.655000 1.320000 4.825000 1.490000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.775000 1.075000 2.215000 1.320000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.150000 0.995000 1.395000 1.490000 ; - RECT 1.150000 1.490000 2.660000 1.660000 ; - RECT 2.445000 1.080000 2.820000 1.320000 ; - RECT 2.445000 1.320000 2.660000 1.490000 ; - RECT 2.490000 1.075000 2.820000 1.080000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.120000 0.995000 0.340000 1.655000 ; - END - END D1 - PIN X - ANTENNADIFFAREA 0.962500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.650000 0.255000 5.875000 0.695000 ; - RECT 5.650000 0.695000 7.275000 0.865000 ; - RECT 5.755000 1.495000 7.275000 1.665000 ; - RECT 5.755000 1.665000 5.925000 2.465000 ; - RECT 6.545000 0.255000 6.745000 0.695000 ; - RECT 6.585000 1.665000 6.775000 2.465000 ; - RECT 7.005000 0.865000 7.275000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.090000 1.835000 5.550000 2.000000 ; - RECT 0.090000 2.000000 5.065000 2.005000 ; - RECT 0.090000 2.005000 0.345000 2.465000 ; - RECT 0.100000 0.255000 2.940000 0.485000 ; - RECT 0.100000 0.485000 0.345000 0.825000 ; - RECT 0.515000 0.655000 0.860000 1.830000 ; - RECT 0.515000 1.830000 5.550000 1.835000 ; - RECT 0.515000 2.175000 0.845000 2.635000 ; - RECT 1.015000 2.005000 1.230000 2.465000 ; - RECT 1.400000 2.175000 1.625000 2.635000 ; - RECT 1.720000 0.655000 4.795000 0.885000 ; - RECT 1.795000 2.005000 2.025000 2.465000 ; - RECT 2.195000 2.175000 2.525000 2.635000 ; - RECT 2.695000 2.005000 3.285000 2.465000 ; - RECT 3.110000 0.085000 3.440000 0.485000 ; - RECT 3.610000 0.255000 3.825000 0.655000 ; - RECT 3.805000 2.180000 4.135000 2.635000 ; - RECT 3.995000 0.085000 4.365000 0.485000 ; - RECT 4.535000 0.255000 4.795000 0.655000 ; - RECT 4.775000 2.005000 5.065000 2.465000 ; - RECT 5.035000 0.085000 5.300000 0.545000 ; - RECT 5.245000 2.170000 5.585000 2.635000 ; - RECT 5.380000 1.075000 6.760000 1.320000 ; - RECT 5.380000 1.320000 5.550000 1.830000 ; - RECT 6.075000 0.085000 6.375000 0.525000 ; - RECT 6.095000 1.835000 6.415000 2.635000 ; - RECT 6.915000 0.085000 7.275000 0.525000 ; - RECT 6.945000 1.835000 7.270000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - END -END sky130_fd_sc_hd__o2111a_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111ai_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111ai_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.785000 1.005000 3.115000 1.615000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 0.995000 2.615000 1.615000 ; - RECT 2.270000 1.615000 2.615000 2.370000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.995000 1.815000 1.615000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.025000 0.255000 1.355000 1.615000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.485000 1.075000 0.815000 1.615000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 0.857250 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.255000 0.690000 0.885000 ; - RECT 0.085000 0.885000 0.315000 1.785000 ; - RECT 0.085000 1.785000 2.095000 2.025000 ; - RECT 0.790000 2.025000 1.025000 2.465000 ; - RECT 1.750000 2.025000 2.095000 2.465000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.290000 2.195000 0.620000 2.635000 ; - RECT 1.210000 2.255000 1.540000 2.635000 ; - RECT 1.750000 0.255000 2.095000 0.625000 ; - RECT 1.750000 0.625000 3.115000 0.825000 ; - RECT 2.285000 0.085000 2.615000 0.455000 ; - RECT 2.785000 0.255000 3.115000 0.625000 ; - RECT 2.785000 1.795000 3.115000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__o2111ai_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111ai_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111ai_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.635000 1.075000 5.435000 1.325000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.365000 1.075000 4.455000 1.325000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.200000 1.075000 3.185000 1.325000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.045000 1.075000 1.790000 1.325000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.355000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 1.302000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.615000 0.935000 0.905000 ; - RECT 0.605000 0.905000 0.865000 1.495000 ; - RECT 0.605000 1.495000 4.005000 1.665000 ; - RECT 0.605000 1.665000 0.865000 2.465000 ; - RECT 1.535000 1.665000 1.725000 2.465000 ; - RECT 2.395000 1.665000 2.575000 2.465000 ; - RECT 3.815000 1.665000 4.005000 2.105000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.175000 0.260000 1.300000 0.445000 ; - RECT 0.175000 0.445000 0.435000 0.865000 ; - RECT 0.175000 1.525000 0.425000 2.635000 ; - RECT 1.035000 1.835000 1.365000 2.635000 ; - RECT 1.115000 0.445000 1.300000 0.735000 ; - RECT 1.115000 0.735000 2.275000 0.905000 ; - RECT 1.470000 0.255000 3.210000 0.445000 ; - RECT 1.470000 0.445000 1.775000 0.530000 ; - RECT 1.470000 0.530000 1.760000 0.565000 ; - RECT 1.895000 1.840000 2.225000 2.635000 ; - RECT 1.925000 0.620000 2.275000 0.735000 ; - RECT 2.450000 0.655000 5.435000 0.840000 ; - RECT 2.755000 1.835000 3.085000 2.635000 ; - RECT 2.880000 0.445000 3.210000 0.485000 ; - RECT 3.310000 1.835000 3.570000 2.275000 ; - RECT 3.310000 2.275000 4.500000 2.465000 ; - RECT 3.380000 0.365000 3.570000 0.655000 ; - RECT 3.740000 0.085000 4.070000 0.485000 ; - RECT 4.240000 0.365000 4.430000 0.650000 ; - RECT 4.240000 0.650000 5.435000 0.655000 ; - RECT 4.240000 1.515000 5.360000 1.685000 ; - RECT 4.240000 1.685000 4.500000 2.275000 ; - RECT 4.600000 0.085000 4.930000 0.480000 ; - RECT 4.670000 1.855000 4.930000 2.635000 ; - RECT 5.100000 0.365000 5.435000 0.650000 ; - RECT 5.100000 1.685000 5.360000 2.465000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__o2111ai_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__o2111ai_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__o2111ai_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.820000 1.075000 9.575000 1.340000 ; - END - END A1 - PIN A2 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.110000 1.075000 7.325000 1.345000 ; - END - END A2 - PIN B1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.815000 1.075000 5.455000 1.345000 ; - END - END B1 - PIN C1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.940000 1.075000 3.550000 1.345000 ; - END - END C1 - PIN D1 - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 1.075000 1.755000 1.345000 ; - END - END D1 - PIN Y - ANTENNADIFFAREA 2.984350 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.645000 1.685000 0.815000 ; - RECT 0.085000 0.815000 0.375000 1.515000 ; - RECT 0.085000 1.515000 7.390000 1.685000 ; - RECT 0.085000 1.685000 0.360000 2.465000 ; - RECT 1.015000 1.685000 1.195000 2.465000 ; - RECT 1.845000 1.685000 2.035000 2.465000 ; - RECT 2.685000 1.685000 2.875000 2.465000 ; - RECT 3.525000 1.685000 3.715000 2.465000 ; - RECT 4.570000 1.685000 4.760000 2.465000 ; - RECT 5.410000 1.685000 5.600000 2.465000 ; - RECT 6.285000 1.685000 6.480000 2.100000 ; - RECT 7.045000 1.685000 7.390000 1.720000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.095000 0.285000 2.025000 0.475000 ; - RECT 0.530000 1.855000 0.845000 2.635000 ; - RECT 1.390000 1.855000 1.675000 2.635000 ; - RECT 1.855000 0.475000 2.025000 0.615000 ; - RECT 1.855000 0.615000 3.785000 0.825000 ; - RECT 2.195000 0.255000 5.565000 0.445000 ; - RECT 2.205000 1.855000 2.515000 2.635000 ; - RECT 3.045000 1.855000 3.355000 2.635000 ; - RECT 3.975000 0.655000 9.440000 0.905000 ; - RECT 4.075000 1.855000 4.400000 2.635000 ; - RECT 4.930000 1.855000 5.220000 2.635000 ; - RECT 5.785000 1.855000 6.115000 2.270000 ; - RECT 5.785000 2.270000 7.005000 2.465000 ; - RECT 6.100000 0.085000 6.430000 0.485000 ; - RECT 6.705000 1.890000 8.235000 2.060000 ; - RECT 6.705000 2.060000 7.005000 2.270000 ; - RECT 6.960000 0.085000 7.290000 0.485000 ; - RECT 7.555000 2.230000 7.885000 2.635000 ; - RECT 7.825000 0.085000 8.155000 0.485000 ; - RECT 8.045000 1.515000 9.080000 1.685000 ; - RECT 8.045000 1.685000 8.235000 1.890000 ; - RECT 8.055000 2.060000 8.235000 2.465000 ; - RECT 8.410000 1.855000 8.720000 2.635000 ; - RECT 8.665000 0.085000 8.995000 0.485000 ; - RECT 8.890000 1.685000 9.080000 2.465000 ; - RECT 9.265000 1.535000 9.575000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - END -END sky130_fd_sc_hd__o2111ai_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2_0 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2_0 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.995000 1.335000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.995000 0.500000 1.615000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.326800 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.565000 0.525000 2.180000 0.825000 ; - RECT 1.645000 2.135000 2.180000 2.465000 ; - RECT 1.865000 0.825000 2.180000 2.135000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.250000 0.085000 0.490000 0.825000 ; - RECT 0.270000 1.785000 1.695000 1.955000 ; - RECT 0.270000 1.955000 0.660000 2.130000 ; - RECT 0.670000 0.425000 0.950000 0.825000 ; - RECT 0.670000 0.825000 0.840000 1.785000 ; - RECT 1.145000 2.125000 1.475000 2.635000 ; - RECT 1.180000 0.085000 1.395000 0.825000 ; - RECT 1.525000 0.995000 1.695000 1.785000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__or2_0 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.010000 0.765000 1.275000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.145000 0.765000 0.500000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.509000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.565000 0.255000 2.180000 0.825000 ; - RECT 1.645000 1.845000 2.180000 2.465000 ; - RECT 1.865000 0.825000 2.180000 1.845000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.250000 0.085000 0.490000 0.595000 ; - RECT 0.270000 1.495000 1.695000 1.665000 ; - RECT 0.270000 1.665000 0.660000 1.840000 ; - RECT 0.670000 0.265000 0.950000 0.595000 ; - RECT 0.670000 0.595000 0.840000 1.495000 ; - RECT 1.145000 1.835000 1.475000 2.635000 ; - RECT 1.180000 0.085000 1.395000 0.595000 ; - RECT 1.525000 0.995000 1.695000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__or2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.865000 0.765000 1.275000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.150000 0.765000 0.345000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.440000 1.835000 2.215000 2.005000 ; - RECT 1.440000 2.005000 1.770000 2.465000 ; - RECT 1.520000 0.385000 1.690000 0.655000 ; - RECT 1.520000 0.655000 2.215000 0.825000 ; - RECT 1.785000 0.825000 2.215000 1.835000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.105000 0.085000 0.345000 0.595000 ; - RECT 0.155000 1.495000 1.615000 1.665000 ; - RECT 0.155000 1.665000 0.515000 1.840000 ; - RECT 0.515000 0.255000 0.805000 0.595000 ; - RECT 0.515000 0.595000 0.695000 1.495000 ; - RECT 1.035000 0.085000 1.350000 0.595000 ; - RECT 1.100000 1.835000 1.270000 2.635000 ; - RECT 1.445000 0.995000 1.615000 1.495000 ; - RECT 1.860000 0.085000 2.190000 0.485000 ; - RECT 1.940000 2.175000 2.110000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__or2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.865000 0.995000 1.240000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.765000 0.345000 1.325000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.440000 0.265000 1.770000 0.735000 ; - RECT 1.440000 0.735000 3.135000 0.905000 ; - RECT 1.440000 1.835000 2.610000 2.005000 ; - RECT 1.440000 2.005000 1.770000 2.465000 ; - RECT 2.280000 0.265000 2.610000 0.735000 ; - RECT 2.280000 1.495000 3.135000 1.665000 ; - RECT 2.280000 1.665000 2.610000 1.835000 ; - RECT 2.280000 2.005000 2.610000 2.465000 ; - RECT 2.790000 0.905000 3.135000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.105000 0.085000 0.345000 0.595000 ; - RECT 0.155000 1.495000 1.615000 1.665000 ; - RECT 0.155000 1.665000 0.515000 2.465000 ; - RECT 0.515000 0.290000 0.845000 0.825000 ; - RECT 0.515000 0.825000 0.695000 1.495000 ; - RECT 1.060000 0.085000 1.230000 0.825000 ; - RECT 1.060000 1.835000 1.230000 2.635000 ; - RECT 1.410000 1.075000 2.620000 1.245000 ; - RECT 1.410000 1.245000 1.615000 1.495000 ; - RECT 1.940000 0.085000 2.110000 0.565000 ; - RECT 1.940000 2.175000 2.110000 2.635000 ; - RECT 2.780000 0.085000 2.950000 0.565000 ; - RECT 2.780000 1.835000 2.950000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__or2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 2.085000 1.735000 2.415000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.425000 1.325000 ; - END - END B_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 0.415000 2.675000 0.760000 ; - RECT 2.405000 1.495000 2.675000 2.465000 ; - RECT 2.505000 0.760000 2.675000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 1.495000 0.345000 2.635000 ; - RECT 0.110000 0.265000 0.420000 0.735000 ; - RECT 0.110000 0.735000 0.845000 0.905000 ; - RECT 0.590000 0.085000 1.325000 0.565000 ; - RECT 0.595000 0.905000 0.845000 0.995000 ; - RECT 0.595000 0.995000 1.335000 1.325000 ; - RECT 0.595000 1.325000 0.765000 1.885000 ; - RECT 0.990000 1.495000 2.235000 1.665000 ; - RECT 0.990000 1.665000 1.410000 1.915000 ; - RECT 1.495000 0.305000 1.665000 0.655000 ; - RECT 1.495000 0.655000 2.235000 0.825000 ; - RECT 1.835000 0.085000 2.215000 0.485000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - RECT 2.065000 0.825000 2.235000 0.995000 ; - RECT 2.065000 0.995000 2.295000 1.325000 ; - RECT 2.065000 1.325000 2.235000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__or2b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 2.085000 1.730000 2.415000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.325000 ; - END - END B_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.400000 0.415000 2.630000 0.760000 ; - RECT 2.400000 1.495000 2.630000 2.465000 ; - RECT 2.460000 0.760000 2.630000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 0.105000 0.265000 0.420000 0.735000 ; - RECT 0.105000 0.735000 0.840000 0.905000 ; - RECT 0.590000 0.085000 1.320000 0.565000 ; - RECT 0.595000 0.905000 0.840000 0.995000 ; - RECT 0.595000 0.995000 1.330000 1.325000 ; - RECT 0.595000 1.325000 0.765000 1.885000 ; - RECT 0.985000 1.495000 2.230000 1.665000 ; - RECT 0.985000 1.665000 1.405000 1.915000 ; - RECT 1.490000 0.305000 1.660000 0.655000 ; - RECT 1.490000 0.655000 2.230000 0.825000 ; - RECT 1.830000 0.085000 2.210000 0.485000 ; - RECT 1.910000 1.835000 2.190000 2.635000 ; - RECT 2.060000 0.825000 2.230000 0.995000 ; - RECT 2.060000 0.995000 2.290000 1.325000 ; - RECT 2.060000 1.325000 2.230000 1.495000 ; - RECT 2.800000 0.085000 3.055000 0.925000 ; - RECT 2.800000 1.460000 3.055000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__or2b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or2b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or2b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.630000 1.075000 2.320000 1.275000 ; - END - END A - PIN B_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.425000 1.955000 ; - END - END B_N - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.325000 0.290000 2.655000 0.735000 ; - RECT 2.325000 0.735000 4.055000 0.905000 ; - RECT 2.365000 1.785000 3.455000 1.955000 ; - RECT 2.365000 1.955000 2.615000 2.465000 ; - RECT 2.830000 1.445000 4.055000 1.615000 ; - RECT 2.830000 1.615000 3.455000 1.785000 ; - RECT 3.165000 0.290000 3.495000 0.735000 ; - RECT 3.205000 1.955000 3.455000 2.465000 ; - RECT 3.670000 0.905000 4.055000 1.445000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.090000 2.125000 0.345000 2.635000 ; - RECT 0.110000 0.265000 0.420000 0.735000 ; - RECT 0.110000 0.735000 0.845000 0.905000 ; - RECT 0.590000 0.085000 1.245000 0.565000 ; - RECT 0.595000 0.905000 0.845000 0.995000 ; - RECT 0.595000 0.995000 1.120000 1.325000 ; - RECT 0.595000 1.325000 0.765000 2.465000 ; - RECT 0.990000 1.495000 2.660000 1.615000 ; - RECT 0.990000 1.615000 1.460000 2.465000 ; - RECT 1.290000 0.735000 1.745000 0.905000 ; - RECT 1.290000 0.905000 1.460000 1.445000 ; - RECT 1.290000 1.445000 2.660000 1.495000 ; - RECT 1.415000 0.305000 1.745000 0.735000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - RECT 1.980000 0.085000 2.155000 0.905000 ; - RECT 2.490000 1.075000 3.500000 1.245000 ; - RECT 2.490000 1.245000 2.660000 1.445000 ; - RECT 2.785000 2.135000 3.035000 2.635000 ; - RECT 2.825000 0.085000 2.995000 0.550000 ; - RECT 3.625000 1.795000 3.875000 2.635000 ; - RECT 3.665000 0.085000 3.835000 0.550000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__or2b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.300000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.600000 0.995000 1.425000 1.325000 ; - RECT 0.600000 1.325000 0.795000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 2.125000 1.275000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.430000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.415000 2.210000 0.760000 ; - RECT 1.935000 1.495000 2.210000 2.465000 ; - RECT 2.040000 0.760000 2.210000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.300000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.490000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.300000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.300000 0.085000 ; - RECT 0.000000 2.635000 2.300000 2.805000 ; - RECT 0.100000 0.305000 0.355000 0.655000 ; - RECT 0.100000 0.655000 1.765000 0.825000 ; - RECT 0.105000 1.495000 0.430000 1.785000 ; - RECT 0.105000 1.785000 1.275000 1.955000 ; - RECT 0.525000 0.085000 0.855000 0.485000 ; - RECT 1.025000 0.305000 1.195000 0.655000 ; - RECT 1.105000 1.495000 1.765000 1.665000 ; - RECT 1.105000 1.665000 1.275000 1.785000 ; - RECT 1.365000 0.085000 1.745000 0.485000 ; - RECT 1.445000 1.835000 1.725000 2.635000 ; - RECT 1.595000 0.825000 1.765000 0.995000 ; - RECT 1.595000 0.995000 1.870000 1.325000 ; - RECT 1.595000 1.325000 1.765000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - END -END sky130_fd_sc_hd__or3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.605000 0.995000 1.430000 1.325000 ; - RECT 0.605000 1.325000 0.830000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 2.125000 1.280000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.995000 0.435000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.940000 0.415000 2.215000 0.760000 ; - RECT 1.940000 1.495000 2.215000 2.465000 ; - RECT 2.045000 0.760000 2.215000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.105000 0.305000 0.360000 0.655000 ; - RECT 0.105000 0.655000 1.770000 0.825000 ; - RECT 0.105000 1.495000 0.435000 1.785000 ; - RECT 0.105000 1.785000 1.270000 1.955000 ; - RECT 0.530000 0.085000 0.860000 0.485000 ; - RECT 1.030000 0.305000 1.200000 0.655000 ; - RECT 1.100000 1.495000 1.770000 1.665000 ; - RECT 1.100000 1.665000 1.270000 1.785000 ; - RECT 1.370000 0.085000 1.750000 0.485000 ; - RECT 1.450000 1.835000 1.730000 2.635000 ; - RECT 1.600000 0.825000 1.770000 0.995000 ; - RECT 1.600000 0.995000 1.875000 1.325000 ; - RECT 1.600000 1.325000 1.770000 1.495000 ; - RECT 2.385000 0.085000 2.675000 0.915000 ; - RECT 2.385000 1.430000 2.675000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__or3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.225000 1.075000 1.700000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 1.075000 1.055000 1.325000 ; - RECT 0.595000 1.325000 0.830000 2.050000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.305000 0.265000 2.635000 0.735000 ; - RECT 2.305000 0.735000 4.055000 0.905000 ; - RECT 2.345000 1.455000 4.055000 1.625000 ; - RECT 2.345000 1.625000 2.595000 2.465000 ; - RECT 3.145000 0.265000 3.475000 0.735000 ; - RECT 3.185000 1.625000 3.435000 2.465000 ; - RECT 3.765000 0.905000 4.055000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.255000 0.425000 0.725000 ; - RECT 0.085000 0.725000 2.090000 0.905000 ; - RECT 0.085000 1.495000 0.425000 2.295000 ; - RECT 0.085000 2.295000 1.265000 2.465000 ; - RECT 0.595000 0.085000 0.765000 0.555000 ; - RECT 0.935000 0.255000 1.265000 0.725000 ; - RECT 1.000000 1.495000 2.090000 1.665000 ; - RECT 1.000000 1.665000 1.265000 2.295000 ; - RECT 1.435000 0.085000 2.135000 0.555000 ; - RECT 1.435000 1.835000 2.135000 2.635000 ; - RECT 1.870000 0.905000 2.090000 1.075000 ; - RECT 1.870000 1.075000 3.595000 1.245000 ; - RECT 1.870000 1.245000 2.090000 1.495000 ; - RECT 2.765000 1.795000 3.015000 2.635000 ; - RECT 2.805000 0.085000 2.975000 0.555000 ; - RECT 3.605000 1.795000 3.855000 2.635000 ; - RECT 3.645000 0.085000 3.815000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__or3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.525000 0.995000 2.350000 1.325000 ; - RECT 1.525000 1.325000 1.770000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.585000 2.125000 2.200000 2.455000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 1.075000 0.425000 1.325000 ; - END - END C_N - PIN X - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.860000 0.415000 3.135000 0.760000 ; - RECT 2.860000 1.495000 3.135000 2.465000 ; - RECT 2.965000 0.760000 3.135000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.905000 ; - RECT 0.085000 1.495000 0.345000 2.635000 ; - RECT 0.515000 0.485000 0.845000 0.905000 ; - RECT 0.595000 0.905000 0.845000 0.995000 ; - RECT 0.595000 0.995000 1.310000 1.325000 ; - RECT 0.595000 1.325000 0.765000 1.885000 ; - RECT 1.025000 0.255000 1.285000 0.655000 ; - RECT 1.025000 0.655000 2.690000 0.825000 ; - RECT 1.025000 1.495000 1.355000 1.785000 ; - RECT 1.025000 1.785000 2.200000 1.955000 ; - RECT 1.455000 0.085000 1.785000 0.485000 ; - RECT 1.955000 0.305000 2.125000 0.655000 ; - RECT 2.030000 1.495000 2.690000 1.665000 ; - RECT 2.030000 1.665000 2.200000 1.785000 ; - RECT 2.295000 0.085000 2.670000 0.485000 ; - RECT 2.370000 1.835000 2.650000 2.635000 ; - RECT 2.520000 0.825000 2.690000 0.995000 ; - RECT 2.520000 0.995000 2.795000 1.325000 ; - RECT 2.520000 1.325000 2.690000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__or3b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 1.075000 2.230000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 2.125000 3.135000 2.365000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.640000 ; - END - END C_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.935000 0.265000 1.285000 0.595000 ; - RECT 0.935000 0.595000 1.105000 1.495000 ; - RECT 0.935000 1.495000 1.330000 1.700000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.290000 0.345000 0.735000 ; - RECT 0.085000 0.735000 0.765000 0.905000 ; - RECT 0.085000 1.810000 0.765000 1.870000 ; - RECT 0.085000 1.870000 2.660000 1.955000 ; - RECT 0.085000 1.955000 1.720000 2.040000 ; - RECT 0.085000 2.040000 0.345000 2.220000 ; - RECT 0.550000 2.210000 0.910000 2.635000 ; - RECT 0.595000 0.085000 0.765000 0.565000 ; - RECT 0.595000 0.905000 0.765000 1.810000 ; - RECT 1.275000 0.765000 3.135000 0.825000 ; - RECT 1.275000 0.825000 2.160000 0.905000 ; - RECT 1.275000 0.905000 1.595000 0.935000 ; - RECT 1.275000 0.935000 1.445000 1.325000 ; - RECT 1.425000 0.735000 3.135000 0.765000 ; - RECT 1.425000 2.210000 1.755000 2.635000 ; - RECT 1.520000 0.085000 1.690000 0.565000 ; - RECT 1.550000 1.785000 2.660000 1.870000 ; - RECT 1.990000 0.305000 2.160000 0.655000 ; - RECT 1.990000 0.655000 3.135000 0.735000 ; - RECT 2.330000 0.085000 2.660000 0.485000 ; - RECT 2.490000 0.995000 2.790000 1.325000 ; - RECT 2.490000 1.325000 2.660000 1.785000 ; - RECT 2.830000 0.305000 3.085000 0.605000 ; - RECT 2.830000 0.605000 3.135000 0.655000 ; - RECT 2.830000 1.495000 3.135000 1.925000 ; - RECT 2.965000 0.825000 3.135000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__or3b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or3b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or3b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.400000 1.415000 2.720000 1.700000 ; - RECT 2.535000 0.995000 2.720000 1.415000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.890000 0.995000 3.200000 1.700000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.640000 ; - END - END C_N - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.935000 0.735000 2.025000 0.905000 ; - RECT 0.935000 0.905000 1.105000 1.415000 ; - RECT 0.935000 1.415000 2.220000 1.700000 ; - RECT 1.000000 0.285000 1.330000 0.735000 ; - RECT 1.855000 0.255000 2.090000 0.585000 ; - RECT 1.855000 0.585000 2.025000 0.735000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.290000 0.345000 0.735000 ; - RECT 0.085000 0.735000 0.765000 0.905000 ; - RECT 0.085000 1.810000 0.765000 1.870000 ; - RECT 0.085000 1.870000 3.620000 2.040000 ; - RECT 0.085000 2.040000 0.345000 2.220000 ; - RECT 0.550000 2.210000 0.910000 2.635000 ; - RECT 0.595000 0.905000 0.765000 1.810000 ; - RECT 0.620000 0.085000 0.790000 0.565000 ; - RECT 1.275000 1.075000 2.365000 1.245000 ; - RECT 1.420000 2.210000 1.750000 2.635000 ; - RECT 1.500000 0.085000 1.670000 0.565000 ; - RECT 2.195000 0.720000 4.055000 0.825000 ; - RECT 2.195000 0.825000 2.400000 0.890000 ; - RECT 2.195000 0.890000 2.365000 1.075000 ; - RECT 2.250000 0.655000 4.055000 0.720000 ; - RECT 2.255000 2.210000 2.595000 2.635000 ; - RECT 2.260000 0.085000 2.590000 0.485000 ; - RECT 2.760000 0.305000 2.930000 0.655000 ; - RECT 3.100000 0.085000 3.490000 0.485000 ; - RECT 3.390000 0.995000 3.680000 1.325000 ; - RECT 3.390000 1.325000 3.620000 1.870000 ; - RECT 3.520000 2.210000 4.055000 2.425000 ; - RECT 3.660000 0.305000 3.915000 0.605000 ; - RECT 3.660000 0.605000 4.055000 0.655000 ; - RECT 3.850000 0.825000 4.055000 2.210000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__or3b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 2.760000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.490000 0.995000 1.895000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 2.125000 1.745000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 0.995000 1.320000 1.615000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.090000 0.755000 0.440000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 0.415000 2.675000 0.760000 ; - RECT 2.405000 1.495000 2.675000 2.465000 ; - RECT 2.505000 0.760000 2.675000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 2.760000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 2.950000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 2.760000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 2.760000 0.085000 ; - RECT 0.000000 2.635000 2.760000 2.805000 ; - RECT 0.090000 1.495000 0.410000 1.785000 ; - RECT 0.090000 1.785000 1.680000 1.955000 ; - RECT 0.095000 0.085000 0.425000 0.585000 ; - RECT 0.625000 0.305000 0.795000 0.655000 ; - RECT 0.625000 0.655000 2.235000 0.825000 ; - RECT 0.995000 0.085000 1.325000 0.485000 ; - RECT 1.495000 0.305000 1.665000 0.655000 ; - RECT 1.510000 1.495000 2.235000 1.665000 ; - RECT 1.510000 1.665000 1.680000 1.785000 ; - RECT 1.835000 0.085000 2.215000 0.485000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - RECT 2.065000 0.825000 2.235000 0.995000 ; - RECT 2.065000 0.995000 2.335000 1.325000 ; - RECT 2.065000 1.325000 2.235000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - END -END sky130_fd_sc_hd__or4_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.490000 0.995000 1.895000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 2.125000 1.745000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 0.995000 1.320000 1.615000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.755000 0.440000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.405000 0.415000 2.680000 0.760000 ; - RECT 2.405000 1.495000 2.680000 2.465000 ; - RECT 2.510000 0.760000 2.680000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 1.495000 0.410000 1.785000 ; - RECT 0.085000 1.785000 1.680000 1.955000 ; - RECT 0.090000 0.085000 0.425000 0.585000 ; - RECT 0.625000 0.305000 0.795000 0.655000 ; - RECT 0.625000 0.655000 2.235000 0.825000 ; - RECT 0.995000 0.085000 1.325000 0.485000 ; - RECT 1.495000 0.305000 1.665000 0.655000 ; - RECT 1.510000 1.495000 2.235000 1.665000 ; - RECT 1.510000 1.665000 1.680000 1.785000 ; - RECT 1.835000 0.085000 2.215000 0.485000 ; - RECT 1.915000 1.835000 2.195000 2.635000 ; - RECT 2.065000 0.825000 2.235000 0.995000 ; - RECT 2.065000 0.995000 2.340000 1.325000 ; - RECT 2.065000 1.325000 2.235000 1.495000 ; - RECT 2.850000 0.085000 3.020000 1.000000 ; - RECT 2.850000 1.455000 3.020000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__or4_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.840000 0.995000 2.010000 1.445000 ; - RECT 1.840000 1.445000 2.275000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.280000 0.995000 1.610000 1.450000 ; - RECT 1.400000 1.450000 1.610000 1.785000 ; - RECT 1.400000 1.785000 1.720000 2.375000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.880000 0.995000 1.050000 1.620000 ; - RECT 0.880000 1.620000 1.230000 2.375000 ; - END - END C - PIN D - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.755000 0.370000 1.325000 ; - END - END D - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.480000 1.455000 4.055000 1.625000 ; - RECT 2.480000 1.625000 2.730000 2.465000 ; - RECT 2.520000 0.255000 2.770000 0.725000 ; - RECT 2.520000 0.725000 4.055000 0.905000 ; - RECT 3.280000 0.255000 3.610000 0.725000 ; - RECT 3.320000 1.625000 3.570000 2.465000 ; - RECT 3.810000 0.905000 4.055000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.140000 -0.085000 0.310000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.115000 1.495000 0.710000 1.665000 ; - RECT 0.115000 1.665000 0.450000 2.450000 ; - RECT 0.120000 0.085000 0.370000 0.585000 ; - RECT 0.540000 0.655000 2.350000 0.825000 ; - RECT 0.540000 0.825000 0.710000 1.495000 ; - RECT 0.700000 0.305000 0.870000 0.655000 ; - RECT 1.070000 0.085000 1.400000 0.485000 ; - RECT 1.570000 0.305000 1.740000 0.655000 ; - RECT 1.960000 0.085000 2.340000 0.485000 ; - RECT 2.005000 1.795000 2.255000 2.635000 ; - RECT 2.180000 0.825000 2.350000 1.075000 ; - RECT 2.180000 1.075000 3.640000 1.245000 ; - RECT 2.900000 1.795000 3.150000 2.635000 ; - RECT 2.940000 0.085000 3.110000 0.555000 ; - RECT 3.740000 1.795000 3.990000 2.635000 ; - RECT 3.780000 0.085000 3.950000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__or4_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4b_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4b_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.430000 0.995000 2.810000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.610000 2.125000 2.660000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.520000 0.995000 2.260000 1.615000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.755000 0.425000 1.325000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.320000 0.415000 3.595000 0.760000 ; - RECT 3.320000 1.495000 3.595000 2.465000 ; - RECT 3.425000 0.760000 3.595000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.085000 0.425000 0.585000 ; - RECT 0.085000 1.560000 0.425000 2.635000 ; - RECT 0.595000 0.305000 0.840000 0.995000 ; - RECT 0.595000 0.995000 1.250000 1.325000 ; - RECT 0.595000 1.325000 0.835000 1.920000 ; - RECT 1.030000 1.495000 1.350000 1.785000 ; - RECT 1.030000 1.785000 2.660000 1.955000 ; - RECT 1.035000 0.085000 1.365000 0.585000 ; - RECT 1.565000 0.305000 1.735000 0.655000 ; - RECT 1.565000 0.655000 3.150000 0.825000 ; - RECT 1.910000 0.085000 2.240000 0.485000 ; - RECT 2.410000 0.305000 2.580000 0.655000 ; - RECT 2.490000 1.495000 3.150000 1.665000 ; - RECT 2.490000 1.665000 2.660000 1.785000 ; - RECT 2.750000 0.085000 3.130000 0.485000 ; - RECT 2.830000 1.835000 3.110000 2.635000 ; - RECT 2.980000 0.825000 3.150000 0.995000 ; - RECT 2.980000 0.995000 3.255000 1.325000 ; - RECT 2.980000 1.325000 3.150000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__or4b_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4b_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4b_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.680000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.755000 1.075000 2.320000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.985000 2.125000 2.670000 2.415000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.550000 1.075000 3.550000 1.275000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 1.075000 0.425000 1.435000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.935000 0.675000 1.250000 0.680000 ; - RECT 0.935000 0.680000 1.245000 0.790000 ; - RECT 0.935000 0.790000 1.105000 1.495000 ; - RECT 0.935000 1.495000 1.250000 1.825000 ; - RECT 0.970000 0.260000 1.250000 0.675000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.680000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.870000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.680000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.680000 0.085000 ; - RECT 0.000000 2.635000 3.680000 2.805000 ; - RECT 0.085000 0.325000 0.350000 0.735000 ; - RECT 0.085000 0.735000 0.765000 0.905000 ; - RECT 0.085000 1.605000 0.765000 1.890000 ; - RECT 0.510000 1.890000 0.765000 1.995000 ; - RECT 0.510000 1.995000 1.715000 2.165000 ; - RECT 0.515000 2.335000 0.845000 2.635000 ; - RECT 0.595000 0.905000 0.765000 1.605000 ; - RECT 0.630000 0.085000 0.800000 0.565000 ; - RECT 1.290000 0.995000 1.585000 1.325000 ; - RECT 1.415000 0.735000 3.055000 0.905000 ; - RECT 1.415000 0.905000 1.585000 0.995000 ; - RECT 1.415000 1.325000 1.585000 1.355000 ; - RECT 1.415000 1.355000 1.600000 1.370000 ; - RECT 1.415000 1.370000 1.610000 1.380000 ; - RECT 1.415000 1.380000 1.620000 1.390000 ; - RECT 1.415000 1.390000 1.625000 1.400000 ; - RECT 1.415000 1.400000 1.630000 1.410000 ; - RECT 1.415000 1.410000 1.645000 1.420000 ; - RECT 1.415000 1.420000 1.655000 1.425000 ; - RECT 1.415000 1.425000 1.665000 1.445000 ; - RECT 1.415000 1.445000 3.560000 1.450000 ; - RECT 1.420000 1.450000 3.560000 1.615000 ; - RECT 1.435000 0.085000 1.815000 0.485000 ; - RECT 1.440000 1.785000 3.030000 1.955000 ; - RECT 1.440000 1.955000 1.715000 1.995000 ; - RECT 1.480000 2.335000 1.815000 2.635000 ; - RECT 1.985000 0.305000 2.155000 0.735000 ; - RECT 2.385000 0.085000 2.715000 0.485000 ; - RECT 2.860000 1.955000 3.030000 2.215000 ; - RECT 2.860000 2.215000 3.345000 2.385000 ; - RECT 2.885000 0.305000 3.055000 0.735000 ; - RECT 3.225000 0.085000 3.555000 0.585000 ; - RECT 3.225000 1.615000 3.560000 1.815000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - END -END sky130_fd_sc_hd__or4b_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4b_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4b_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.060000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.755000 0.995000 2.925000 1.445000 ; - RECT 2.755000 1.445000 3.190000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.195000 0.995000 2.525000 1.450000 ; - RECT 2.335000 1.450000 2.525000 1.785000 ; - RECT 2.335000 1.785000 2.635000 2.375000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.795000 0.995000 1.965000 1.620000 ; - RECT 1.795000 1.620000 2.155000 2.375000 ; - END - END C - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.105000 0.995000 0.445000 1.955000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.395000 1.455000 4.965000 1.625000 ; - RECT 3.395000 1.625000 3.645000 2.465000 ; - RECT 3.435000 0.255000 3.685000 0.725000 ; - RECT 3.435000 0.725000 4.965000 0.905000 ; - RECT 4.195000 0.255000 4.525000 0.725000 ; - RECT 4.235000 1.625000 4.485000 2.465000 ; - RECT 4.725000 0.905000 4.965000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.060000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.250000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.060000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.060000 0.085000 ; - RECT 0.000000 2.635000 5.060000 2.805000 ; - RECT 0.085000 0.085000 0.345000 0.825000 ; - RECT 0.085000 2.135000 0.365000 2.635000 ; - RECT 0.595000 0.435000 0.785000 0.905000 ; - RECT 0.595000 2.065000 0.785000 2.455000 ; - RECT 0.615000 0.905000 0.785000 0.995000 ; - RECT 0.615000 0.995000 1.215000 1.325000 ; - RECT 0.615000 1.325000 0.785000 2.065000 ; - RECT 1.035000 0.085000 1.285000 0.585000 ; - RECT 1.035000 1.575000 1.625000 1.745000 ; - RECT 1.035000 1.745000 1.365000 2.450000 ; - RECT 1.455000 0.655000 3.265000 0.825000 ; - RECT 1.455000 0.825000 1.625000 1.575000 ; - RECT 1.615000 0.305000 1.785000 0.655000 ; - RECT 1.985000 0.085000 2.315000 0.485000 ; - RECT 2.485000 0.305000 2.655000 0.655000 ; - RECT 2.875000 0.085000 3.255000 0.485000 ; - RECT 2.920000 1.795000 3.170000 2.635000 ; - RECT 3.095000 0.825000 3.265000 1.075000 ; - RECT 3.095000 1.075000 4.555000 1.245000 ; - RECT 3.815000 1.795000 4.065000 2.635000 ; - RECT 3.855000 0.085000 4.025000 0.555000 ; - RECT 4.655000 1.795000 4.905000 2.635000 ; - RECT 4.695000 0.085000 4.865000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - END -END sky130_fd_sc_hd__or4b_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4bb_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4bb_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.140000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.615000 0.995000 3.270000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.480000 2.125000 3.120000 2.455000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.695000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.995000 1.235000 1.325000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.453750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.780000 0.415000 4.055000 0.760000 ; - RECT 3.780000 1.495000 4.055000 2.465000 ; - RECT 3.885000 0.760000 4.055000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.140000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.330000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.140000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.140000 0.085000 ; - RECT 0.000000 2.635000 4.140000 2.805000 ; - RECT 0.085000 0.450000 0.400000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.865000 ; - RECT 0.085000 1.865000 1.915000 2.035000 ; - RECT 0.085000 2.035000 0.345000 2.455000 ; - RECT 0.515000 2.205000 0.845000 2.635000 ; - RECT 0.655000 0.085000 0.825000 0.825000 ; - RECT 0.990000 1.525000 1.575000 1.695000 ; - RECT 1.075000 0.450000 1.245000 0.655000 ; - RECT 1.075000 0.655000 1.575000 0.825000 ; - RECT 1.405000 0.825000 1.575000 1.075000 ; - RECT 1.405000 1.075000 1.830000 1.245000 ; - RECT 1.405000 1.245000 1.575000 1.525000 ; - RECT 1.470000 0.085000 1.845000 0.485000 ; - RECT 1.510000 2.205000 2.255000 2.375000 ; - RECT 1.745000 1.415000 2.395000 1.585000 ; - RECT 1.745000 1.585000 1.915000 1.865000 ; - RECT 2.015000 0.305000 2.185000 0.655000 ; - RECT 2.015000 0.655000 3.610000 0.825000 ; - RECT 2.085000 1.785000 3.120000 1.955000 ; - RECT 2.085000 1.955000 2.255000 2.205000 ; - RECT 2.225000 0.995000 2.395000 1.415000 ; - RECT 2.370000 0.085000 2.700000 0.485000 ; - RECT 2.870000 0.305000 3.040000 0.655000 ; - RECT 2.950000 1.495000 3.610000 1.665000 ; - RECT 2.950000 1.665000 3.120000 1.785000 ; - RECT 3.210000 0.085000 3.590000 0.485000 ; - RECT 3.290000 1.835000 3.570000 2.635000 ; - RECT 3.440000 0.825000 3.610000 0.995000 ; - RECT 3.440000 0.995000 3.715000 1.325000 ; - RECT 3.440000 1.325000 3.610000 1.495000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - END -END sky130_fd_sc_hd__or4bb_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4bb_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4bb_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 4.600000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.640000 0.995000 3.295000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.505000 2.125000 3.145000 2.455000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.430000 0.995000 0.780000 1.695000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.950000 0.995000 1.240000 1.325000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.805000 0.415000 4.080000 0.760000 ; - RECT 3.805000 1.495000 4.080000 2.465000 ; - RECT 3.910000 0.760000 4.080000 1.495000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 4.600000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.790000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 4.600000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 4.600000 0.085000 ; - RECT 0.000000 2.635000 4.600000 2.805000 ; - RECT 0.085000 0.450000 0.405000 0.825000 ; - RECT 0.085000 0.825000 0.260000 1.865000 ; - RECT 0.085000 1.865000 1.940000 2.035000 ; - RECT 0.085000 2.035000 0.345000 2.455000 ; - RECT 0.515000 2.205000 0.845000 2.635000 ; - RECT 0.660000 0.085000 0.830000 0.825000 ; - RECT 0.995000 1.525000 1.600000 1.695000 ; - RECT 1.080000 0.450000 1.250000 0.655000 ; - RECT 1.080000 0.655000 1.600000 0.825000 ; - RECT 1.410000 0.825000 1.600000 1.075000 ; - RECT 1.410000 1.075000 1.855000 1.245000 ; - RECT 1.410000 1.245000 1.600000 1.525000 ; - RECT 1.495000 0.085000 1.850000 0.485000 ; - RECT 1.535000 2.205000 2.280000 2.375000 ; - RECT 1.770000 1.415000 2.420000 1.585000 ; - RECT 1.770000 1.585000 1.940000 1.865000 ; - RECT 2.025000 0.305000 2.195000 0.655000 ; - RECT 2.025000 0.655000 3.635000 0.825000 ; - RECT 2.110000 1.785000 3.145000 1.955000 ; - RECT 2.110000 1.955000 2.280000 2.205000 ; - RECT 2.250000 0.995000 2.420000 1.415000 ; - RECT 2.395000 0.085000 2.725000 0.485000 ; - RECT 2.895000 0.305000 3.065000 0.655000 ; - RECT 2.975000 1.495000 3.635000 1.665000 ; - RECT 2.975000 1.665000 3.145000 1.785000 ; - RECT 3.235000 0.085000 3.615000 0.485000 ; - RECT 3.315000 1.835000 3.595000 2.635000 ; - RECT 3.465000 0.825000 3.635000 0.995000 ; - RECT 3.465000 0.995000 3.740000 1.325000 ; - RECT 3.465000 1.325000 3.635000 1.495000 ; - RECT 4.250000 0.085000 4.420000 1.025000 ; - RECT 4.250000 1.440000 4.420000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - END -END sky130_fd_sc_hd__or4bb_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__or4bb_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__or4bb_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.235000 0.995000 3.405000 1.445000 ; - RECT 3.235000 1.445000 3.670000 1.615000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.675000 0.995000 3.005000 1.450000 ; - RECT 2.795000 1.450000 3.005000 1.785000 ; - RECT 2.795000 1.785000 3.115000 2.375000 ; - END - END B - PIN C_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.775000 1.695000 ; - END - END C_N - PIN D_N - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.945000 0.995000 1.235000 1.325000 ; - END - END D_N - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.875000 1.455000 5.435000 1.625000 ; - RECT 3.875000 1.625000 4.125000 2.465000 ; - RECT 3.915000 0.255000 4.165000 0.725000 ; - RECT 3.915000 0.725000 5.435000 0.905000 ; - RECT 4.675000 0.255000 5.005000 0.725000 ; - RECT 4.715000 1.625000 4.965000 2.465000 ; - RECT 5.205000 0.905000 5.435000 1.455000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.085000 0.450000 0.400000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.865000 ; - RECT 0.085000 1.865000 1.295000 2.035000 ; - RECT 0.085000 2.035000 0.345000 2.455000 ; - RECT 0.515000 2.205000 0.845000 2.635000 ; - RECT 0.655000 0.085000 0.825000 0.825000 ; - RECT 0.990000 1.525000 1.595000 1.695000 ; - RECT 1.075000 0.450000 1.245000 0.655000 ; - RECT 1.075000 0.655000 1.595000 0.825000 ; - RECT 1.125000 2.035000 1.295000 2.295000 ; - RECT 1.125000 2.295000 2.445000 2.465000 ; - RECT 1.405000 0.825000 1.595000 0.995000 ; - RECT 1.405000 0.995000 1.695000 1.325000 ; - RECT 1.405000 1.325000 1.595000 1.525000 ; - RECT 1.510000 1.955000 2.105000 2.125000 ; - RECT 1.515000 0.085000 1.845000 0.480000 ; - RECT 1.935000 0.655000 3.745000 0.825000 ; - RECT 1.935000 0.825000 2.105000 1.955000 ; - RECT 2.095000 0.305000 2.265000 0.655000 ; - RECT 2.275000 0.995000 2.445000 2.295000 ; - RECT 2.465000 0.085000 2.795000 0.485000 ; - RECT 2.965000 0.305000 3.135000 0.655000 ; - RECT 3.355000 0.085000 3.735000 0.485000 ; - RECT 3.400000 1.795000 3.650000 2.635000 ; - RECT 3.575000 0.825000 3.745000 1.075000 ; - RECT 3.575000 1.075000 5.035000 1.245000 ; - RECT 4.295000 1.795000 4.545000 2.635000 ; - RECT 4.335000 0.085000 4.505000 0.555000 ; - RECT 5.135000 1.795000 5.385000 2.635000 ; - RECT 5.175000 0.085000 5.345000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - END -END sky130_fd_sc_hd__or4bb_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__probe_p_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__probe_p_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.742500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.140000 1.075000 1.240000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met5 ; - RECT 1.250000 0.560000 4.270000 2.160000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.520000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.095000 1.445000 1.595000 1.615000 ; - RECT 0.095000 1.615000 0.425000 2.465000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 1.595000 0.905000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.595000 1.835000 0.765000 2.635000 ; - RECT 0.935000 1.615000 1.265000 2.465000 ; - RECT 1.015000 0.260000 1.185000 0.735000 ; - RECT 1.355000 0.085000 1.685000 0.565000 ; - RECT 1.420000 0.905000 1.595000 1.075000 ; - RECT 1.420000 1.075000 4.045000 1.245000 ; - RECT 1.420000 1.245000 1.595000 1.445000 ; - RECT 1.435000 1.835000 1.605000 2.635000 ; - RECT 1.855000 0.255000 2.025000 0.735000 ; - RECT 1.855000 0.735000 4.545000 0.905000 ; - RECT 1.855000 1.445000 4.545000 1.615000 ; - RECT 1.855000 1.615000 2.025000 2.465000 ; - RECT 2.195000 0.085000 2.525000 0.565000 ; - RECT 2.195000 1.835000 2.525000 2.635000 ; - RECT 2.695000 0.255000 2.865000 0.735000 ; - RECT 2.695000 1.615000 2.865000 2.465000 ; - RECT 3.035000 0.085000 3.365000 0.565000 ; - RECT 3.035000 1.835000 3.365000 2.635000 ; - RECT 3.535000 0.255000 3.705000 0.735000 ; - RECT 3.535000 1.615000 3.705000 2.465000 ; - RECT 3.875000 0.085000 4.205000 0.565000 ; - RECT 3.875000 1.835000 4.205000 2.635000 ; - RECT 4.290000 0.905000 4.545000 1.055000 ; - RECT 4.290000 1.055000 4.885000 1.315000 ; - RECT 4.290000 1.315000 4.545000 1.445000 ; - RECT 4.375000 0.255000 4.545000 0.735000 ; - RECT 4.375000 1.615000 4.545000 2.465000 ; - RECT 4.715000 0.085000 5.045000 0.885000 ; - RECT 4.715000 1.485000 5.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.320000 1.105000 4.490000 1.275000 ; - RECT 4.680000 1.105000 4.850000 1.275000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - LAYER met1 ; - RECT 3.465000 1.060000 4.105000 1.075000 ; - RECT 3.465000 1.075000 4.910000 1.305000 ; - RECT 3.465000 1.305000 4.105000 1.320000 ; - LAYER met2 ; - RECT 3.445000 1.005000 4.125000 1.375000 ; - LAYER met3 ; - RECT 3.395000 1.025000 4.175000 1.355000 ; - LAYER met4 ; - RECT 1.370000 0.680000 4.150000 1.860000 ; - LAYER via ; - RECT 3.495000 1.060000 3.755000 1.320000 ; - RECT 3.815000 1.060000 4.075000 1.320000 ; - LAYER via2 ; - RECT 3.445000 1.050000 3.725000 1.330000 ; - RECT 3.845000 1.050000 4.125000 1.330000 ; - LAYER via3 ; - RECT 3.425000 1.030000 3.745000 1.350000 ; - RECT 3.825000 1.030000 4.145000 1.350000 ; - LAYER via4 ; - RECT 2.970000 0.680000 4.150000 1.860000 ; - END -END sky130_fd_sc_hd__probe_p_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__probec_p_8 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__probec_p_8 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.520000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.742500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.140000 1.075000 1.240000 1.275000 ; - END - END A - PIN X - ANTENNADIFFAREA 1.782000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT -1.140000 0.770000 0.040000 1.950000 ; - RECT 1.460000 0.770000 2.640000 1.950000 ; - END - PORT - LAYER met5 ; - RECT -1.260000 0.560000 2.760000 2.160000 ; - RECT 1.160000 -1.105000 2.760000 0.560000 ; - RECT 1.160000 2.160000 2.760000 3.825000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met5 ; - RECT 4.360000 -1.170000 6.675000 0.560000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 5.710000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met5 ; - RECT 4.360000 2.160000 6.675000 3.890000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.520000 0.085000 ; - RECT 0.000000 2.635000 5.520000 2.805000 ; - RECT 0.095000 1.445000 1.595000 1.615000 ; - RECT 0.095000 1.615000 0.425000 2.465000 ; - RECT 0.175000 0.255000 0.345000 0.735000 ; - RECT 0.175000 0.735000 1.595000 0.905000 ; - RECT 0.515000 0.085000 0.845000 0.565000 ; - RECT 0.595000 1.835000 0.765000 2.635000 ; - RECT 0.935000 1.615000 1.265000 2.465000 ; - RECT 1.015000 0.260000 1.185000 0.735000 ; - RECT 1.355000 0.085000 1.685000 0.565000 ; - RECT 1.420000 0.905000 1.595000 1.075000 ; - RECT 1.420000 1.075000 4.045000 1.245000 ; - RECT 1.420000 1.245000 1.595000 1.445000 ; - RECT 1.435000 1.835000 1.605000 2.635000 ; - RECT 1.855000 0.255000 2.025000 0.735000 ; - RECT 1.855000 0.735000 4.545000 0.905000 ; - RECT 1.855000 1.445000 4.545000 1.615000 ; - RECT 1.855000 1.615000 2.025000 2.465000 ; - RECT 2.195000 0.085000 2.525000 0.565000 ; - RECT 2.195000 1.835000 2.525000 2.635000 ; - RECT 2.695000 0.255000 2.865000 0.735000 ; - RECT 2.695000 1.615000 2.865000 2.465000 ; - RECT 3.035000 0.085000 3.365000 0.565000 ; - RECT 3.035000 1.835000 3.365000 2.635000 ; - RECT 3.535000 0.255000 3.705000 0.735000 ; - RECT 3.535000 1.615000 3.705000 2.465000 ; - RECT 3.875000 0.085000 4.205000 0.565000 ; - RECT 3.875000 1.835000 4.205000 2.635000 ; - RECT 4.290000 0.905000 4.545000 1.055000 ; - RECT 4.290000 1.055000 4.870000 1.315000 ; - RECT 4.290000 1.315000 4.545000 1.445000 ; - RECT 4.375000 0.255000 4.545000 0.735000 ; - RECT 4.375000 1.615000 4.545000 2.465000 ; - RECT 4.715000 0.085000 5.045000 0.885000 ; - RECT 4.715000 1.485000 5.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.305000 1.105000 4.475000 1.275000 ; - RECT 4.665000 1.105000 4.835000 1.275000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - LAYER met1 ; - RECT 0.000000 -0.240000 5.520000 -0.130000 ; - RECT 0.000000 -0.130000 5.840000 0.130000 ; - RECT 0.000000 0.130000 5.520000 0.240000 ; - RECT 0.000000 2.480000 5.520000 2.590000 ; - RECT 0.000000 2.590000 5.840000 2.850000 ; - RECT 0.000000 2.850000 5.520000 2.960000 ; - RECT 2.020000 1.060000 2.660000 1.120000 ; - RECT 2.020000 1.120000 4.895000 1.260000 ; - RECT 2.020000 1.260000 2.660000 1.320000 ; - RECT 4.245000 1.075000 4.895000 1.120000 ; - RECT 4.245000 1.260000 4.895000 1.305000 ; - LAYER met2 ; - RECT 1.890000 1.050000 2.660000 1.330000 ; - RECT 5.135000 -0.140000 5.905000 0.140000 ; - RECT 5.135000 2.580000 5.905000 2.860000 ; - LAYER met3 ; - RECT -0.715000 1.030000 0.065000 1.350000 ; - RECT 1.885000 1.025000 2.665000 1.355000 ; - RECT 5.130000 -0.165000 5.910000 0.165000 ; - RECT 5.130000 2.555000 5.910000 2.885000 ; - LAYER met4 ; - RECT 4.930000 -0.895000 6.110000 0.285000 ; - RECT 4.930000 2.435000 6.110000 3.615000 ; - LAYER via ; - RECT 2.050000 1.060000 2.310000 1.320000 ; - RECT 2.370000 1.060000 2.630000 1.320000 ; - RECT 5.230000 -0.130000 5.490000 0.130000 ; - RECT 5.230000 2.590000 5.490000 2.850000 ; - RECT 5.550000 -0.130000 5.810000 0.130000 ; - RECT 5.550000 2.590000 5.810000 2.850000 ; - LAYER via2 ; - RECT 1.935000 1.050000 2.215000 1.330000 ; - RECT 2.335000 1.050000 2.615000 1.330000 ; - RECT 5.180000 -0.140000 5.460000 0.140000 ; - RECT 5.180000 2.580000 5.460000 2.860000 ; - RECT 5.580000 -0.140000 5.860000 0.140000 ; - RECT 5.580000 2.580000 5.860000 2.860000 ; - LAYER via3 ; - RECT -0.685000 1.030000 -0.365000 1.350000 ; - RECT -0.285000 1.030000 0.035000 1.350000 ; - RECT 1.915000 1.030000 2.235000 1.350000 ; - RECT 2.315000 1.030000 2.635000 1.350000 ; - RECT 5.160000 -0.160000 5.480000 0.160000 ; - RECT 5.160000 2.560000 5.480000 2.880000 ; - RECT 5.560000 -0.160000 5.880000 0.160000 ; - RECT 5.560000 2.560000 5.880000 2.880000 ; - END -END sky130_fd_sc_hd__probec_p_8 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfbbn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfbbn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.26000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.775000 1.405000 4.105000 1.575000 ; - RECT 3.775000 1.575000 4.060000 1.675000 ; - RECT 3.825000 1.675000 4.060000 2.375000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 13.915000 0.255000 14.175000 0.785000 ; - RECT 13.915000 1.470000 14.175000 2.465000 ; - RECT 13.965000 0.785000 14.175000 1.470000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.500000 0.255000 12.785000 0.715000 ; - RECT 12.500000 1.630000 12.785000 2.465000 ; - RECT 12.605000 0.715000 12.785000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.535000 1.095000 11.990000 1.325000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 1.025000 1.695000 1.685000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.345000 2.155000 0.815000 ; - RECT 1.935000 0.815000 2.315000 1.150000 ; - RECT 1.935000 1.150000 2.155000 1.695000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.870000 0.735000 6.295000 0.965000 ; - RECT 5.870000 0.965000 6.215000 1.065000 ; - LAYER mcon ; - RECT 6.125000 0.765000 6.295000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.755000 0.735000 10.130000 1.065000 ; - LAYER mcon ; - RECT 9.805000 0.765000 9.975000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.065000 0.735000 6.355000 0.780000 ; - RECT 6.065000 0.780000 10.035000 0.920000 ; - RECT 6.065000 0.920000 6.355000 0.965000 ; - RECT 9.745000 0.735000 10.035000 0.780000 ; - RECT 9.745000 0.920000 10.035000 0.965000 ; - END - END SET_B - PIN CLK_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.435000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.260000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 14.450000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.260000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.260000 0.085000 ; - RECT 0.000000 2.635000 14.260000 2.805000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.095000 1.795000 0.835000 1.965000 ; - RECT 0.095000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.835000 1.795000 ; - RECT 1.015000 0.345000 1.235000 2.465000 ; - RECT 1.430000 0.085000 1.705000 0.635000 ; - RECT 1.430000 1.885000 1.785000 2.635000 ; - RECT 2.215000 1.875000 2.575000 2.385000 ; - RECT 2.325000 0.265000 2.655000 0.595000 ; - RECT 2.405000 1.295000 3.075000 1.405000 ; - RECT 2.405000 1.405000 2.670000 1.430000 ; - RECT 2.405000 1.430000 2.630000 1.465000 ; - RECT 2.405000 1.465000 2.605000 1.505000 ; - RECT 2.405000 1.505000 2.575000 1.875000 ; - RECT 2.460000 1.255000 3.075000 1.295000 ; - RECT 2.485000 0.595000 2.655000 1.075000 ; - RECT 2.485000 1.075000 3.075000 1.255000 ; - RECT 2.760000 1.575000 3.605000 1.745000 ; - RECT 2.760000 1.745000 3.140000 1.905000 ; - RECT 2.870000 0.305000 3.040000 0.625000 ; - RECT 2.870000 0.625000 3.645000 0.765000 ; - RECT 2.870000 0.765000 3.770000 0.795000 ; - RECT 2.970000 1.905000 3.140000 2.465000 ; - RECT 3.225000 0.085000 3.555000 0.445000 ; - RECT 3.310000 2.215000 3.640000 2.635000 ; - RECT 3.430000 0.795000 3.770000 1.095000 ; - RECT 3.430000 1.095000 3.605000 1.575000 ; - RECT 3.950000 0.425000 4.330000 0.595000 ; - RECT 3.950000 0.595000 4.120000 1.065000 ; - RECT 3.950000 1.065000 4.400000 1.105000 ; - RECT 3.950000 1.105000 4.410000 1.175000 ; - RECT 3.950000 1.175000 4.445000 1.235000 ; - RECT 4.160000 0.265000 4.330000 0.425000 ; - RECT 4.225000 1.235000 4.445000 1.275000 ; - RECT 4.230000 2.135000 4.445000 2.465000 ; - RECT 4.245000 1.275000 4.445000 1.305000 ; - RECT 4.275000 1.305000 4.445000 2.135000 ; - RECT 4.555000 0.265000 5.655000 0.465000 ; - RECT 4.570000 0.705000 4.790000 1.035000 ; - RECT 4.615000 1.035000 4.790000 1.575000 ; - RECT 4.615000 1.575000 5.125000 1.955000 ; - RECT 4.635000 2.250000 5.465000 2.420000 ; - RECT 5.000000 0.735000 5.330000 1.015000 ; - RECT 5.295000 1.195000 5.670000 1.235000 ; - RECT 5.295000 1.235000 6.645000 1.405000 ; - RECT 5.295000 1.405000 5.465000 2.250000 ; - RECT 5.485000 0.465000 5.655000 0.585000 ; - RECT 5.485000 0.585000 5.670000 0.655000 ; - RECT 5.500000 0.655000 5.670000 1.195000 ; - RECT 5.635000 1.575000 5.885000 1.785000 ; - RECT 5.635000 1.785000 6.985000 2.035000 ; - RECT 5.705000 2.205000 6.085000 2.635000 ; - RECT 5.835000 0.085000 6.005000 0.525000 ; - RECT 6.260000 0.255000 7.350000 0.425000 ; - RECT 6.260000 0.425000 6.590000 0.465000 ; - RECT 6.385000 2.035000 6.555000 2.375000 ; - RECT 6.395000 1.405000 6.645000 1.485000 ; - RECT 6.425000 1.155000 6.645000 1.235000 ; - RECT 6.680000 0.610000 7.010000 0.780000 ; - RECT 6.810000 0.780000 7.010000 0.895000 ; - RECT 6.810000 0.895000 8.125000 1.060000 ; - RECT 6.815000 1.060000 8.125000 1.065000 ; - RECT 6.815000 1.065000 6.985000 1.785000 ; - RECT 7.155000 1.235000 7.485000 1.415000 ; - RECT 7.155000 1.415000 8.160000 1.655000 ; - RECT 7.175000 1.915000 7.505000 2.635000 ; - RECT 7.180000 0.425000 7.350000 0.715000 ; - RECT 7.620000 0.085000 7.975000 0.465000 ; - RECT 7.795000 1.065000 8.125000 1.235000 ; - RECT 8.360000 1.575000 8.595000 1.985000 ; - RECT 8.420000 0.705000 8.705000 1.125000 ; - RECT 8.420000 1.125000 9.040000 1.305000 ; - RECT 8.550000 2.250000 9.380000 2.420000 ; - RECT 8.615000 0.265000 9.380000 0.465000 ; - RECT 8.835000 1.305000 9.040000 1.905000 ; - RECT 9.210000 0.465000 9.380000 1.235000 ; - RECT 9.210000 1.235000 10.560000 1.405000 ; - RECT 9.210000 1.405000 9.380000 2.250000 ; - RECT 9.550000 1.575000 9.800000 1.915000 ; - RECT 9.550000 1.915000 12.330000 2.085000 ; - RECT 9.560000 0.085000 9.820000 0.525000 ; - RECT 9.620000 2.255000 10.000000 2.635000 ; - RECT 10.080000 0.255000 11.250000 0.425000 ; - RECT 10.080000 0.425000 10.410000 0.545000 ; - RECT 10.240000 2.085000 10.410000 2.375000 ; - RECT 10.340000 1.075000 10.560000 1.235000 ; - RECT 10.575000 0.595000 10.905000 0.780000 ; - RECT 10.730000 0.780000 10.905000 1.915000 ; - RECT 10.940000 2.255000 12.330000 2.635000 ; - RECT 11.075000 0.425000 11.250000 0.585000 ; - RECT 11.080000 0.755000 11.775000 0.925000 ; - RECT 11.080000 0.925000 11.355000 1.575000 ; - RECT 11.080000 1.575000 11.855000 1.745000 ; - RECT 11.565000 0.265000 11.775000 0.755000 ; - RECT 12.000000 0.085000 12.330000 0.805000 ; - RECT 12.160000 0.995000 12.425000 1.325000 ; - RECT 12.160000 1.325000 12.330000 1.915000 ; - RECT 12.960000 0.255000 13.275000 0.995000 ; - RECT 12.960000 0.995000 13.795000 1.325000 ; - RECT 12.960000 1.325000 13.275000 2.415000 ; - RECT 13.455000 0.085000 13.745000 0.545000 ; - RECT 13.455000 1.765000 13.740000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 0.765000 0.775000 0.935000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 1.785000 1.235000 1.955000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.105000 3.075000 1.275000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.230000 1.105000 4.400000 1.275000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.785000 4.915000 1.955000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.155000 0.765000 5.325000 0.935000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 1.445000 8.135000 1.615000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 1.105000 8.595000 1.275000 ; - RECT 8.425000 1.785000 8.595000 1.955000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 1.445000 11.355000 1.615000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - LAYER met1 ; - RECT 0.545000 0.735000 0.835000 0.780000 ; - RECT 0.545000 0.780000 5.385000 0.920000 ; - RECT 0.545000 0.920000 0.835000 0.965000 ; - RECT 1.005000 1.755000 1.295000 1.800000 ; - RECT 1.005000 1.800000 8.655000 1.940000 ; - RECT 1.005000 1.940000 1.295000 1.985000 ; - RECT 2.845000 1.075000 3.135000 1.120000 ; - RECT 2.845000 1.120000 4.460000 1.260000 ; - RECT 2.845000 1.260000 3.135000 1.305000 ; - RECT 4.170000 1.075000 4.460000 1.120000 ; - RECT 4.170000 1.260000 4.460000 1.305000 ; - RECT 4.685000 1.755000 4.975000 1.800000 ; - RECT 4.685000 1.940000 4.975000 1.985000 ; - RECT 5.095000 0.735000 5.385000 0.780000 ; - RECT 5.095000 0.920000 5.385000 0.965000 ; - RECT 5.170000 0.965000 5.385000 1.120000 ; - RECT 5.170000 1.120000 8.655000 1.260000 ; - RECT 7.905000 1.415000 8.195000 1.460000 ; - RECT 7.905000 1.460000 11.415000 1.600000 ; - RECT 7.905000 1.600000 8.195000 1.645000 ; - RECT 8.365000 1.075000 8.655000 1.120000 ; - RECT 8.365000 1.260000 8.655000 1.305000 ; - RECT 8.365000 1.755000 8.655000 1.800000 ; - RECT 8.365000 1.940000 8.655000 1.985000 ; - RECT 11.125000 1.415000 11.415000 1.460000 ; - RECT 11.125000 1.600000 11.415000 1.645000 ; - END -END sky130_fd_sc_hd__sdfbbn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfbbn_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfbbn_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 15.18000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 1.325000 4.025000 2.375000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 14.415000 0.255000 14.665000 0.825000 ; - RECT 14.415000 1.445000 14.665000 2.465000 ; - RECT 14.460000 0.825000 14.665000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.580000 0.255000 12.830000 0.715000 ; - RECT 12.580000 1.630000 12.830000 2.465000 ; - RECT 12.660000 0.715000 12.830000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.590000 1.095000 12.070000 1.325000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.415000 1.025000 1.695000 1.685000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.935000 0.345000 2.145000 0.765000 ; - RECT 1.935000 0.765000 2.335000 1.095000 ; - RECT 1.935000 1.095000 2.155000 1.695000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.885000 0.735000 6.295000 0.965000 ; - RECT 5.885000 0.965000 6.215000 1.065000 ; - LAYER mcon ; - RECT 6.125000 0.765000 6.295000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.755000 0.735000 10.130000 1.065000 ; - LAYER mcon ; - RECT 9.805000 0.765000 9.975000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.065000 0.735000 6.355000 0.780000 ; - RECT 6.065000 0.780000 10.035000 0.920000 ; - RECT 6.065000 0.920000 6.355000 0.965000 ; - RECT 9.745000 0.735000 10.035000 0.780000 ; - RECT 9.745000 0.920000 10.035000 0.965000 ; - END - END SET_B - PIN CLK_N - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.435000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 15.180000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 15.370000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 15.180000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 15.180000 0.085000 ; - RECT 0.000000 2.635000 15.180000 2.805000 ; - RECT 0.170000 0.345000 0.345000 0.635000 ; - RECT 0.170000 0.635000 0.835000 0.805000 ; - RECT 0.170000 1.795000 0.835000 1.965000 ; - RECT 0.170000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.835000 1.795000 ; - RECT 1.015000 0.345000 1.235000 2.465000 ; - RECT 1.430000 0.085000 1.705000 0.635000 ; - RECT 1.430000 1.885000 1.785000 2.635000 ; - RECT 2.215000 1.875000 2.575000 2.385000 ; - RECT 2.315000 0.265000 2.730000 0.595000 ; - RECT 2.405000 1.250000 3.075000 1.405000 ; - RECT 2.405000 1.405000 2.575000 1.875000 ; - RECT 2.435000 1.235000 3.075000 1.250000 ; - RECT 2.560000 0.595000 2.730000 1.075000 ; - RECT 2.560000 1.075000 3.075000 1.235000 ; - RECT 2.745000 1.575000 3.645000 1.745000 ; - RECT 2.745000 1.745000 3.065000 1.905000 ; - RECT 2.895000 1.905000 3.065000 2.465000 ; - RECT 2.955000 0.305000 3.125000 0.625000 ; - RECT 2.955000 0.625000 3.645000 0.765000 ; - RECT 2.955000 0.765000 3.770000 0.795000 ; - RECT 3.295000 2.215000 3.640000 2.635000 ; - RECT 3.370000 0.085000 3.700000 0.445000 ; - RECT 3.475000 0.795000 3.770000 1.095000 ; - RECT 3.475000 1.095000 3.645000 1.575000 ; - RECT 4.230000 0.305000 4.455000 2.465000 ; - RECT 4.625000 0.705000 4.845000 1.575000 ; - RECT 4.625000 1.575000 5.125000 1.955000 ; - RECT 4.635000 2.250000 5.465000 2.420000 ; - RECT 4.700000 0.265000 5.715000 0.465000 ; - RECT 5.025000 0.645000 5.375000 1.015000 ; - RECT 5.295000 1.195000 5.715000 1.235000 ; - RECT 5.295000 1.235000 6.645000 1.405000 ; - RECT 5.295000 1.405000 5.465000 2.250000 ; - RECT 5.545000 0.465000 5.715000 1.195000 ; - RECT 5.635000 1.575000 5.885000 1.785000 ; - RECT 5.635000 1.785000 6.985000 2.035000 ; - RECT 5.705000 2.205000 6.085000 2.635000 ; - RECT 5.885000 0.085000 6.055000 0.525000 ; - RECT 6.225000 0.255000 7.375000 0.425000 ; - RECT 6.225000 0.425000 6.555000 0.505000 ; - RECT 6.385000 2.035000 6.555000 2.375000 ; - RECT 6.395000 1.405000 6.645000 1.485000 ; - RECT 6.425000 1.155000 6.645000 1.235000 ; - RECT 6.705000 0.595000 7.035000 0.765000 ; - RECT 6.815000 0.765000 7.035000 0.895000 ; - RECT 6.815000 0.895000 8.125000 1.065000 ; - RECT 6.815000 1.065000 6.985000 1.785000 ; - RECT 7.155000 1.235000 7.485000 1.415000 ; - RECT 7.155000 1.415000 8.160000 1.655000 ; - RECT 7.175000 1.915000 7.505000 2.635000 ; - RECT 7.205000 0.425000 7.375000 0.715000 ; - RECT 7.645000 0.085000 7.975000 0.465000 ; - RECT 7.795000 1.065000 8.125000 1.235000 ; - RECT 8.360000 1.575000 8.595000 1.985000 ; - RECT 8.420000 0.705000 8.705000 1.125000 ; - RECT 8.420000 1.125000 9.040000 1.305000 ; - RECT 8.550000 2.250000 9.380000 2.420000 ; - RECT 8.615000 0.265000 9.380000 0.465000 ; - RECT 8.835000 1.305000 9.040000 1.905000 ; - RECT 9.210000 0.465000 9.380000 1.235000 ; - RECT 9.210000 1.235000 10.560000 1.405000 ; - RECT 9.210000 1.405000 9.380000 2.250000 ; - RECT 9.550000 1.575000 9.800000 1.915000 ; - RECT 9.550000 1.915000 12.410000 2.085000 ; - RECT 9.560000 0.085000 9.820000 0.525000 ; - RECT 9.620000 2.255000 10.000000 2.635000 ; - RECT 10.080000 0.255000 11.250000 0.425000 ; - RECT 10.080000 0.425000 10.410000 0.545000 ; - RECT 10.240000 2.085000 10.410000 2.375000 ; - RECT 10.340000 1.075000 10.560000 1.235000 ; - RECT 10.580000 0.595000 10.910000 0.780000 ; - RECT 10.730000 0.780000 10.910000 1.915000 ; - RECT 10.940000 2.255000 12.410000 2.635000 ; - RECT 11.080000 0.425000 11.250000 0.585000 ; - RECT 11.080000 0.755000 11.845000 0.925000 ; - RECT 11.080000 0.925000 11.355000 1.575000 ; - RECT 11.080000 1.575000 11.925000 1.745000 ; - RECT 11.620000 0.265000 11.845000 0.755000 ; - RECT 12.080000 0.085000 12.410000 0.805000 ; - RECT 12.240000 0.995000 12.480000 1.325000 ; - RECT 12.240000 1.325000 12.410000 1.915000 ; - RECT 13.000000 0.085000 13.235000 0.885000 ; - RECT 13.000000 1.495000 13.235000 2.635000 ; - RECT 13.455000 0.255000 13.770000 0.995000 ; - RECT 13.455000 0.995000 14.290000 1.325000 ; - RECT 13.455000 1.325000 13.770000 2.415000 ; - RECT 13.950000 0.085000 14.245000 0.545000 ; - RECT 13.950000 1.765000 14.245000 2.635000 ; - RECT 14.835000 0.085000 15.075000 0.885000 ; - RECT 14.835000 1.495000 15.075000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 0.765000 0.775000 0.935000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 1.785000 1.235000 1.955000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.105000 3.075000 1.275000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.785000 4.915000 1.955000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 0.765000 5.375000 0.935000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 1.445000 8.135000 1.615000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 1.105000 8.595000 1.275000 ; - RECT 8.425000 1.785000 8.595000 1.955000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 1.445000 11.355000 1.615000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - RECT 14.405000 -0.085000 14.575000 0.085000 ; - RECT 14.405000 2.635000 14.575000 2.805000 ; - RECT 14.865000 -0.085000 15.035000 0.085000 ; - RECT 14.865000 2.635000 15.035000 2.805000 ; - LAYER met1 ; - RECT 0.545000 0.735000 0.835000 0.780000 ; - RECT 0.545000 0.780000 5.435000 0.920000 ; - RECT 0.545000 0.920000 0.835000 0.965000 ; - RECT 1.005000 1.755000 1.295000 1.800000 ; - RECT 1.005000 1.800000 8.655000 1.940000 ; - RECT 1.005000 1.940000 1.295000 1.985000 ; - RECT 2.845000 1.075000 3.135000 1.120000 ; - RECT 2.845000 1.120000 4.515000 1.260000 ; - RECT 2.845000 1.260000 3.135000 1.305000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.755000 4.975000 1.800000 ; - RECT 4.685000 1.940000 4.975000 1.985000 ; - RECT 5.145000 0.735000 5.435000 0.780000 ; - RECT 5.145000 0.920000 5.435000 0.965000 ; - RECT 5.220000 0.965000 5.435000 1.120000 ; - RECT 5.220000 1.120000 8.655000 1.260000 ; - RECT 7.905000 1.415000 8.195000 1.460000 ; - RECT 7.905000 1.460000 11.415000 1.600000 ; - RECT 7.905000 1.600000 8.195000 1.645000 ; - RECT 8.365000 1.075000 8.655000 1.120000 ; - RECT 8.365000 1.260000 8.655000 1.305000 ; - RECT 8.365000 1.755000 8.655000 1.800000 ; - RECT 8.365000 1.940000 8.655000 1.985000 ; - RECT 11.125000 1.415000 11.415000 1.460000 ; - RECT 11.125000 1.600000 11.415000 1.645000 ; - END -END sky130_fd_sc_hd__sdfbbn_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfbbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfbbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.26000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.126000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.825000 1.325000 4.025000 2.375000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 13.915000 0.255000 14.175000 0.825000 ; - RECT 13.915000 1.605000 14.175000 2.465000 ; - RECT 13.965000 0.825000 14.175000 1.605000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.500000 0.255000 12.785000 0.715000 ; - RECT 12.500000 1.630000 12.785000 2.465000 ; - RECT 12.605000 0.715000 12.785000 1.630000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.535000 1.095000 11.990000 1.325000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.440000 1.025000 1.720000 1.685000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.960000 0.345000 2.180000 0.845000 ; - RECT 1.960000 0.845000 2.415000 1.015000 ; - RECT 1.960000 1.015000 2.180000 1.695000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.885000 0.735000 6.295000 0.965000 ; - RECT 5.885000 0.965000 6.215000 1.065000 ; - LAYER mcon ; - RECT 6.125000 0.765000 6.295000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.755000 0.735000 10.130000 1.065000 ; - LAYER mcon ; - RECT 9.805000 0.765000 9.975000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.065000 0.735000 6.355000 0.780000 ; - RECT 6.065000 0.780000 10.035000 0.920000 ; - RECT 6.065000 0.920000 6.355000 0.965000 ; - RECT 9.745000 0.735000 10.035000 0.780000 ; - RECT 9.745000 0.920000 10.035000 0.965000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.085000 0.975000 0.435000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.260000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 14.450000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.260000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.260000 0.085000 ; - RECT 0.000000 2.635000 14.260000 2.805000 ; - RECT 0.170000 0.345000 0.345000 0.635000 ; - RECT 0.170000 0.635000 0.835000 0.805000 ; - RECT 0.170000 1.795000 0.835000 1.965000 ; - RECT 0.170000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.605000 0.805000 0.835000 1.795000 ; - RECT 1.015000 0.345000 1.240000 2.465000 ; - RECT 1.455000 0.085000 1.705000 0.635000 ; - RECT 1.455000 1.885000 1.785000 2.635000 ; - RECT 2.235000 1.875000 2.565000 2.385000 ; - RECT 2.350000 0.265000 2.755000 0.595000 ; - RECT 2.350000 1.185000 3.075000 1.365000 ; - RECT 2.350000 1.365000 2.565000 1.875000 ; - RECT 2.585000 0.595000 2.755000 1.075000 ; - RECT 2.585000 1.075000 3.075000 1.185000 ; - RECT 2.745000 1.575000 3.645000 1.745000 ; - RECT 2.745000 1.745000 3.065000 1.905000 ; - RECT 2.895000 1.905000 3.065000 2.465000 ; - RECT 2.925000 0.305000 3.125000 0.625000 ; - RECT 2.925000 0.625000 3.645000 0.765000 ; - RECT 2.925000 0.765000 3.770000 0.795000 ; - RECT 3.310000 2.215000 3.640000 2.635000 ; - RECT 3.370000 0.085000 3.700000 0.445000 ; - RECT 3.475000 0.795000 3.770000 1.095000 ; - RECT 3.475000 1.095000 3.645000 1.575000 ; - RECT 4.230000 0.305000 4.455000 2.465000 ; - RECT 4.625000 0.705000 4.845000 1.575000 ; - RECT 4.625000 1.575000 5.125000 1.955000 ; - RECT 4.635000 2.250000 5.465000 2.420000 ; - RECT 4.700000 0.265000 5.715000 0.465000 ; - RECT 5.025000 0.645000 5.375000 1.015000 ; - RECT 5.295000 1.195000 5.715000 1.235000 ; - RECT 5.295000 1.235000 6.645000 1.405000 ; - RECT 5.295000 1.405000 5.465000 2.250000 ; - RECT 5.545000 0.465000 5.715000 1.195000 ; - RECT 5.635000 1.575000 5.885000 1.785000 ; - RECT 5.635000 1.785000 6.985000 2.035000 ; - RECT 5.705000 2.205000 6.085000 2.635000 ; - RECT 5.885000 0.085000 6.055000 0.525000 ; - RECT 6.225000 0.255000 7.395000 0.425000 ; - RECT 6.225000 0.425000 6.555000 0.465000 ; - RECT 6.385000 2.035000 6.555000 2.375000 ; - RECT 6.395000 1.405000 6.645000 1.485000 ; - RECT 6.425000 1.155000 6.645000 1.235000 ; - RECT 6.700000 0.595000 7.030000 0.765000 ; - RECT 6.815000 0.765000 7.030000 0.895000 ; - RECT 6.815000 0.895000 8.125000 1.065000 ; - RECT 6.815000 1.065000 6.985000 1.785000 ; - RECT 7.155000 1.235000 7.485000 1.415000 ; - RECT 7.155000 1.415000 8.160000 1.655000 ; - RECT 7.175000 1.915000 7.505000 2.635000 ; - RECT 7.200000 0.425000 7.395000 0.715000 ; - RECT 7.640000 0.085000 7.975000 0.465000 ; - RECT 7.795000 1.065000 8.125000 1.235000 ; - RECT 8.360000 1.575000 8.595000 1.985000 ; - RECT 8.420000 0.705000 8.705000 1.125000 ; - RECT 8.420000 1.125000 9.040000 1.305000 ; - RECT 8.550000 2.250000 9.380000 2.420000 ; - RECT 8.615000 0.265000 9.380000 0.465000 ; - RECT 8.835000 1.305000 9.040000 1.905000 ; - RECT 9.210000 0.465000 9.380000 1.235000 ; - RECT 9.210000 1.235000 10.560000 1.405000 ; - RECT 9.210000 1.405000 9.380000 2.250000 ; - RECT 9.550000 1.575000 9.800000 1.915000 ; - RECT 9.550000 1.915000 12.330000 2.085000 ; - RECT 9.560000 0.085000 9.820000 0.525000 ; - RECT 9.620000 2.255000 10.000000 2.635000 ; - RECT 10.080000 0.255000 11.250000 0.425000 ; - RECT 10.080000 0.425000 10.430000 0.465000 ; - RECT 10.240000 2.085000 10.410000 2.375000 ; - RECT 10.340000 1.075000 10.560000 1.235000 ; - RECT 10.575000 0.645000 10.905000 0.815000 ; - RECT 10.730000 0.815000 10.905000 1.915000 ; - RECT 10.940000 2.255000 12.330000 2.635000 ; - RECT 11.075000 0.425000 11.250000 0.585000 ; - RECT 11.080000 0.755000 11.765000 0.925000 ; - RECT 11.080000 0.925000 11.355000 1.575000 ; - RECT 11.080000 1.575000 11.855000 1.745000 ; - RECT 11.565000 0.265000 11.765000 0.755000 ; - RECT 12.000000 0.085000 12.330000 0.805000 ; - RECT 12.160000 0.995000 12.425000 1.325000 ; - RECT 12.160000 1.325000 12.330000 1.915000 ; - RECT 12.960000 0.255000 13.275000 0.995000 ; - RECT 12.960000 0.995000 13.795000 1.325000 ; - RECT 12.960000 1.325000 13.275000 2.415000 ; - RECT 13.450000 1.765000 13.745000 2.635000 ; - RECT 13.455000 0.085000 13.745000 0.545000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 1.785000 0.775000 1.955000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 0.765000 1.235000 0.935000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.105000 3.075000 1.275000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.785000 4.915000 1.955000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 0.765000 5.375000 0.935000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 1.445000 8.135000 1.615000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 1.105000 8.595000 1.275000 ; - RECT 8.425000 1.785000 8.595000 1.955000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 1.445000 11.355000 1.615000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - LAYER met1 ; - RECT 0.545000 1.755000 0.835000 1.800000 ; - RECT 0.545000 1.800000 8.655000 1.940000 ; - RECT 0.545000 1.940000 0.835000 1.985000 ; - RECT 1.005000 0.735000 1.295000 0.780000 ; - RECT 1.005000 0.780000 5.435000 0.920000 ; - RECT 1.005000 0.920000 1.295000 0.965000 ; - RECT 2.845000 1.075000 3.135000 1.120000 ; - RECT 2.845000 1.120000 4.515000 1.260000 ; - RECT 2.845000 1.260000 3.135000 1.305000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.755000 4.975000 1.800000 ; - RECT 4.685000 1.940000 4.975000 1.985000 ; - RECT 5.145000 0.735000 5.435000 0.780000 ; - RECT 5.145000 0.920000 5.435000 0.965000 ; - RECT 5.220000 0.965000 5.435000 1.120000 ; - RECT 5.220000 1.120000 8.655000 1.260000 ; - RECT 7.905000 1.415000 8.195000 1.460000 ; - RECT 7.905000 1.460000 11.415000 1.600000 ; - RECT 7.905000 1.600000 8.195000 1.645000 ; - RECT 8.365000 1.075000 8.655000 1.120000 ; - RECT 8.365000 1.260000 8.655000 1.305000 ; - RECT 8.365000 1.755000 8.655000 1.800000 ; - RECT 8.365000 1.940000 8.655000 1.985000 ; - RECT 11.125000 1.415000 11.415000 1.460000 ; - RECT 11.125000 1.600000 11.415000 1.645000 ; - END -END sky130_fd_sc_hd__sdfbbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.88000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.140000 0.265000 11.400000 0.795000 ; - RECT 11.140000 1.460000 11.400000 2.325000 ; - RECT 11.150000 1.445000 11.400000 1.460000 ; - RECT 11.190000 0.795000 11.400000 1.445000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.340600 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.510000 1.560000 12.780000 2.465000 ; - RECT 12.520000 0.255000 12.780000 0.760000 ; - RECT 12.600000 0.760000 12.780000 1.560000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.880000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 13.070000 2.910000 ; - RECT 4.405000 1.305000 13.070000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.880000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.880000 0.085000 ; - RECT 0.000000 2.635000 12.880000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 0.995000 ; - RECT 10.345000 0.995000 11.020000 1.295000 ; - RECT 10.375000 1.295000 11.020000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.720000 0.085000 10.890000 0.545000 ; - RECT 10.720000 1.495000 10.970000 2.635000 ; - RECT 11.650000 1.535000 12.325000 1.705000 ; - RECT 11.650000 1.705000 11.830000 2.465000 ; - RECT 11.660000 0.255000 11.830000 0.635000 ; - RECT 11.660000 0.635000 12.325000 0.805000 ; - RECT 12.010000 0.085000 12.340000 0.465000 ; - RECT 12.010000 1.875000 12.340000 2.635000 ; - RECT 12.155000 0.805000 12.325000 1.060000 ; - RECT 12.155000 1.060000 12.430000 1.390000 ; - RECT 12.155000 1.390000 12.325000 1.535000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.805000 1.105000 0.975000 1.275000 ; - RECT 1.035000 1.785000 1.205000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - LAYER met1 ; - RECT 0.745000 1.075000 1.035000 1.120000 ; - RECT 0.745000 1.120000 8.635000 1.260000 ; - RECT 0.745000 1.260000 1.035000 1.305000 ; - RECT 0.970000 1.755000 1.270000 1.800000 ; - RECT 0.970000 1.800000 8.675000 1.940000 ; - RECT 0.970000 1.940000 1.270000 1.985000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.34000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.511500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.575000 0.265000 11.925000 1.695000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.435000 1.535000 12.825000 2.080000 ; - RECT 12.445000 0.310000 12.825000 0.825000 ; - RECT 12.525000 2.080000 12.825000 2.465000 ; - RECT 12.655000 0.825000 12.825000 1.535000 ; - END - END Q_N - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.340000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 13.530000 2.910000 ; - RECT 4.405000 1.305000 13.530000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.340000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 13.340000 0.085000 ; - RECT 0.000000 2.635000 13.340000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 1.055000 ; - RECT 10.345000 1.055000 11.060000 1.295000 ; - RECT 10.375000 1.295000 11.060000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.715000 0.345000 10.885000 0.715000 ; - RECT 10.715000 0.715000 11.405000 0.885000 ; - RECT 10.715000 1.795000 11.405000 1.865000 ; - RECT 10.715000 1.865000 12.265000 2.035000 ; - RECT 10.715000 2.035000 10.890000 2.465000 ; - RECT 11.090000 0.085000 11.365000 0.545000 ; - RECT 11.090000 2.205000 11.420000 2.635000 ; - RECT 11.230000 0.885000 11.405000 1.795000 ; - RECT 11.550000 2.035000 12.265000 2.085000 ; - RECT 12.025000 2.255000 12.355000 2.635000 ; - RECT 12.095000 0.995000 12.485000 1.325000 ; - RECT 12.095000 1.325000 12.265000 1.865000 ; - RECT 12.105000 0.085000 12.275000 0.825000 ; - RECT 12.995000 0.085000 13.165000 0.930000 ; - RECT 12.995000 1.495000 13.245000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.805000 1.105000 0.975000 1.275000 ; - RECT 1.035000 1.785000 1.205000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - LAYER met1 ; - RECT 0.745000 1.075000 1.035000 1.120000 ; - RECT 0.745000 1.120000 8.635000 1.260000 ; - RECT 0.745000 1.260000 1.035000 1.305000 ; - RECT 0.970000 1.755000 1.270000 1.800000 ; - RECT 0.970000 1.800000 8.675000 1.940000 ; - RECT 0.970000 1.940000 1.270000 1.985000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrtn_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrtn_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.50000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.140000 0.265000 11.400000 0.795000 ; - RECT 11.140000 1.460000 11.400000 2.325000 ; - RECT 11.150000 1.445000 11.400000 1.460000 ; - RECT 11.190000 0.795000 11.400000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK_N - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK_N - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.500000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 11.690000 2.910000 ; - RECT 4.405000 1.305000 11.690000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.500000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.500000 0.085000 ; - RECT 0.000000 2.635000 11.500000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 0.995000 ; - RECT 10.345000 0.995000 11.020000 1.295000 ; - RECT 10.375000 1.295000 11.020000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.720000 0.085000 10.890000 0.545000 ; - RECT 10.720000 1.495000 10.970000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.675000 1.785000 0.845000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.145000 1.105000 1.315000 1.275000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - LAYER met1 ; - RECT 0.615000 1.755000 0.915000 1.800000 ; - RECT 0.615000 1.800000 8.675000 1.940000 ; - RECT 0.615000 1.940000 0.915000 1.985000 ; - RECT 1.085000 1.075000 1.375000 1.120000 ; - RECT 1.085000 1.120000 8.635000 1.260000 ; - RECT 1.085000 1.260000 1.375000 1.305000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrtn_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.50000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.140000 0.265000 11.400000 0.795000 ; - RECT 11.140000 1.460000 11.400000 2.325000 ; - RECT 11.150000 1.445000 11.400000 1.460000 ; - RECT 11.190000 0.795000 11.400000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.500000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 11.690000 2.910000 ; - RECT 4.405000 1.305000 11.690000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.500000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.500000 0.085000 ; - RECT 0.000000 2.635000 11.500000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 0.995000 ; - RECT 10.345000 0.995000 11.020000 1.295000 ; - RECT 10.375000 1.295000 11.020000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.720000 0.085000 10.890000 0.545000 ; - RECT 10.720000 1.495000 10.970000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.805000 1.105000 0.975000 1.275000 ; - RECT 1.035000 1.785000 1.205000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - LAYER met1 ; - RECT 0.745000 1.075000 1.035000 1.120000 ; - RECT 0.745000 1.120000 8.635000 1.260000 ; - RECT 0.745000 1.260000 1.035000 1.305000 ; - RECT 0.970000 1.755000 1.270000 1.800000 ; - RECT 0.970000 1.800000 8.675000 1.940000 ; - RECT 0.970000 1.940000 1.270000 1.985000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.140000 0.265000 11.400000 0.795000 ; - RECT 11.140000 1.460000 11.400000 2.325000 ; - RECT 11.150000 1.445000 11.400000 1.460000 ; - RECT 11.190000 0.795000 11.400000 1.445000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 12.150000 2.910000 ; - RECT 4.405000 1.305000 12.150000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 0.995000 ; - RECT 10.345000 0.995000 11.020000 1.295000 ; - RECT 10.375000 1.295000 11.020000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.720000 0.085000 10.890000 0.545000 ; - RECT 10.720000 1.495000 10.970000 2.635000 ; - RECT 11.570000 0.085000 11.740000 0.545000 ; - RECT 11.570000 1.495000 11.820000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.805000 1.105000 0.975000 1.275000 ; - RECT 1.035000 1.785000 1.205000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - LAYER met1 ; - RECT 0.745000 1.075000 1.035000 1.120000 ; - RECT 0.745000 1.120000 8.635000 1.260000 ; - RECT 0.745000 1.260000 1.035000 1.305000 ; - RECT 0.970000 1.755000 1.270000 1.800000 ; - RECT 0.970000 1.800000 8.675000 1.940000 ; - RECT 0.970000 1.940000 1.270000 1.985000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfrtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfrtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.88000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.144000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.735000 1.355000 3.120000 1.785000 ; - RECT 2.865000 1.785000 3.120000 2.465000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.140000 0.265000 11.400000 0.795000 ; - RECT 11.140000 1.460000 11.400000 2.325000 ; - RECT 11.150000 1.445000 11.400000 1.460000 ; - RECT 11.190000 0.795000 11.400000 0.995000 ; - RECT 11.190000 0.995000 12.240000 1.325000 ; - RECT 11.190000 1.325000 11.400000 1.445000 ; - RECT 11.990000 0.265000 12.240000 0.995000 ; - RECT 11.990000 1.325000 12.240000 2.325000 ; - END - END Q - PIN RESET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.505000 0.765000 7.035000 1.045000 ; - LAYER mcon ; - RECT 6.865000 0.765000 7.035000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 9.525000 1.065000 10.115000 1.275000 ; - RECT 9.825000 0.635000 10.115000 1.065000 ; - LAYER mcon ; - RECT 9.690000 1.105000 9.860000 1.275000 ; - RECT 9.945000 0.765000 10.115000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 6.445000 0.735000 7.095000 0.780000 ; - RECT 6.445000 0.780000 10.175000 0.920000 ; - RECT 6.445000 0.920000 7.095000 0.965000 ; - RECT 9.630000 0.920000 10.175000 0.965000 ; - RECT 9.630000 0.965000 9.920000 1.305000 ; - RECT 9.885000 0.735000 10.175000 0.780000 ; - END - END RESET_B - PIN SCD - ANTENNAGATEAREA 0.156600 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.020000 0.285000 4.275000 0.710000 ; - RECT 4.020000 0.710000 4.395000 1.700000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.435000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.465000 1.985000 1.730000 2.465000 ; - RECT 1.485000 1.070000 1.730000 1.985000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.247500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.140000 0.975000 0.490000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.880000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.215000 -0.010000 0.235000 0.015000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 1.970000 1.425000 ; - RECT -0.190000 1.425000 13.070000 2.910000 ; - RECT 4.405000 1.305000 13.070000 1.425000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.880000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.880000 0.085000 ; - RECT 0.000000 2.635000 12.880000 2.805000 ; - RECT 0.090000 1.795000 0.865000 1.965000 ; - RECT 0.090000 1.965000 0.345000 2.465000 ; - RECT 0.095000 0.345000 0.345000 0.635000 ; - RECT 0.095000 0.635000 0.835000 0.805000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.530000 2.135000 0.860000 2.635000 ; - RECT 0.660000 0.805000 0.835000 0.995000 ; - RECT 0.660000 0.995000 0.975000 1.325000 ; - RECT 0.660000 1.325000 0.865000 1.795000 ; - RECT 1.015000 0.345000 1.315000 0.675000 ; - RECT 1.035000 1.730000 1.315000 1.900000 ; - RECT 1.035000 1.900000 1.205000 2.465000 ; - RECT 1.145000 0.675000 1.315000 1.730000 ; - RECT 1.535000 0.395000 1.705000 0.730000 ; - RECT 1.535000 0.730000 2.225000 0.900000 ; - RECT 1.875000 0.085000 2.205000 0.560000 ; - RECT 1.900000 2.055000 2.150000 2.400000 ; - RECT 1.980000 1.260000 2.470000 1.455000 ; - RECT 1.980000 1.455000 2.150000 2.055000 ; - RECT 2.055000 0.900000 2.225000 0.995000 ; - RECT 2.055000 0.995000 3.085000 1.185000 ; - RECT 2.055000 1.185000 2.470000 1.260000 ; - RECT 2.320000 2.040000 2.490000 2.635000 ; - RECT 2.395000 0.085000 2.725000 0.825000 ; - RECT 2.915000 0.255000 3.850000 0.425000 ; - RECT 2.915000 0.425000 3.085000 0.995000 ; - RECT 3.255000 0.675000 3.425000 1.015000 ; - RECT 3.255000 1.015000 3.460000 1.185000 ; - RECT 3.290000 1.185000 3.460000 1.935000 ; - RECT 3.290000 1.935000 5.075000 2.105000 ; - RECT 3.460000 2.105000 3.630000 2.465000 ; - RECT 3.680000 0.425000 3.850000 1.685000 ; - RECT 4.300000 2.275000 4.630000 2.635000 ; - RECT 4.445000 0.085000 4.775000 0.540000 ; - RECT 4.565000 0.715000 5.145000 0.895000 ; - RECT 4.565000 0.895000 4.735000 1.935000 ; - RECT 4.905000 1.065000 5.075000 1.395000 ; - RECT 4.905000 2.105000 5.075000 2.185000 ; - RECT 4.905000 2.185000 5.275000 2.435000 ; - RECT 4.975000 0.335000 5.315000 0.505000 ; - RECT 4.975000 0.505000 5.145000 0.715000 ; - RECT 5.245000 1.575000 5.495000 1.955000 ; - RECT 5.325000 0.705000 5.975000 1.035000 ; - RECT 5.325000 1.035000 5.495000 1.575000 ; - RECT 5.470000 2.135000 5.835000 2.465000 ; - RECT 5.485000 0.305000 6.335000 0.475000 ; - RECT 5.665000 1.215000 7.375000 1.385000 ; - RECT 5.665000 1.385000 5.835000 2.135000 ; - RECT 6.005000 1.935000 7.165000 2.105000 ; - RECT 6.005000 2.105000 6.175000 2.375000 ; - RECT 6.165000 0.475000 6.335000 1.215000 ; - RECT 6.285000 1.595000 7.715000 1.765000 ; - RECT 6.410000 2.355000 6.740000 2.635000 ; - RECT 6.915000 0.085000 7.245000 0.545000 ; - RECT 6.995000 2.105000 7.165000 2.375000 ; - RECT 7.205000 1.005000 7.375000 1.215000 ; - RECT 7.375000 2.175000 7.745000 2.635000 ; - RECT 7.455000 0.275000 7.785000 0.445000 ; - RECT 7.455000 0.445000 7.715000 0.835000 ; - RECT 7.455000 1.765000 7.715000 1.835000 ; - RECT 7.455000 1.835000 8.140000 2.005000 ; - RECT 7.545000 0.835000 7.715000 1.595000 ; - RECT 7.885000 0.705000 8.095000 1.495000 ; - RECT 7.885000 1.495000 8.520000 1.655000 ; - RECT 7.885000 1.655000 8.870000 1.665000 ; - RECT 7.970000 2.005000 8.140000 2.465000 ; - RECT 8.005000 0.255000 8.915000 0.535000 ; - RECT 8.310000 1.665000 8.870000 1.935000 ; - RECT 8.310000 1.935000 8.840000 1.955000 ; - RECT 8.320000 2.125000 9.190000 2.465000 ; - RECT 8.405000 0.920000 8.575000 1.325000 ; - RECT 8.745000 0.535000 8.915000 1.315000 ; - RECT 8.745000 1.315000 9.210000 1.485000 ; - RECT 9.015000 2.035000 9.210000 2.115000 ; - RECT 9.015000 2.115000 9.190000 2.125000 ; - RECT 9.040000 1.485000 9.210000 1.575000 ; - RECT 9.040000 1.575000 10.205000 1.745000 ; - RECT 9.040000 1.745000 9.210000 2.035000 ; - RECT 9.085000 0.085000 9.255000 0.525000 ; - RECT 9.125000 0.695000 9.655000 0.865000 ; - RECT 9.125000 0.865000 9.295000 1.145000 ; - RECT 9.360000 2.195000 9.610000 2.635000 ; - RECT 9.485000 0.295000 10.515000 0.465000 ; - RECT 9.485000 0.465000 9.655000 0.695000 ; - RECT 9.780000 1.915000 10.545000 2.085000 ; - RECT 9.780000 2.085000 9.950000 2.375000 ; - RECT 10.120000 2.255000 10.450000 2.635000 ; - RECT 10.345000 0.465000 10.515000 0.995000 ; - RECT 10.345000 0.995000 11.020000 1.295000 ; - RECT 10.375000 1.295000 11.020000 1.325000 ; - RECT 10.375000 1.325000 10.545000 1.915000 ; - RECT 10.720000 0.085000 10.890000 0.545000 ; - RECT 10.720000 1.495000 10.970000 2.635000 ; - RECT 11.570000 0.085000 11.740000 0.545000 ; - RECT 11.570000 1.495000 11.820000 2.635000 ; - RECT 12.410000 0.085000 12.580000 0.545000 ; - RECT 12.410000 1.495000 12.660000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.805000 1.105000 0.975000 1.275000 ; - RECT 1.035000 1.785000 1.205000 1.955000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.905000 1.105000 5.075000 1.275000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.325000 1.785000 5.495000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.405000 1.105000 8.575000 1.275000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.445000 1.785000 8.615000 1.955000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - LAYER met1 ; - RECT 0.745000 1.075000 1.035000 1.120000 ; - RECT 0.745000 1.120000 8.635000 1.260000 ; - RECT 0.745000 1.260000 1.035000 1.305000 ; - RECT 0.970000 1.755000 1.270000 1.800000 ; - RECT 0.970000 1.800000 8.675000 1.940000 ; - RECT 0.970000 1.940000 1.270000 1.985000 ; - RECT 4.845000 1.075000 5.135000 1.120000 ; - RECT 4.845000 1.260000 5.135000 1.305000 ; - RECT 5.265000 1.755000 5.555000 1.800000 ; - RECT 5.265000 1.940000 5.555000 1.985000 ; - RECT 8.345000 1.075000 8.635000 1.120000 ; - RECT 8.345000 1.260000 8.635000 1.305000 ; - RECT 8.385000 1.755000 8.675000 1.800000 ; - RECT 8.385000 1.940000 8.675000 1.985000 ; - END -END sky130_fd_sc_hd__sdfrtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfsbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfsbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.34000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.055000 0.765000 1.335000 1.675000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.915000 0.275000 13.255000 0.825000 ; - RECT 12.915000 1.495000 13.255000 2.450000 ; - RECT 13.070000 0.825000 13.255000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.500000 0.255000 11.830000 2.465000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.345000 1.675000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 0.765000 0.825000 1.675000 ; - LAYER mcon ; - RECT 0.610000 1.105000 0.780000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.370000 1.075000 2.700000 1.600000 ; - LAYER mcon ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.550000 1.075000 0.840000 1.120000 ; - RECT 0.550000 1.120000 2.675000 1.260000 ; - RECT 0.550000 1.260000 0.840000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.640000 1.445000 7.015000 1.765000 ; - END - PORT - LAYER li1 ; - RECT 8.885000 1.415000 9.110000 1.525000 ; - RECT 8.885000 1.525000 10.075000 1.725000 ; - LAYER mcon ; - RECT 8.885000 1.445000 9.055000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 6.580000 1.415000 6.870000 1.460000 ; - RECT 6.580000 1.460000 9.115000 1.600000 ; - RECT 6.580000 1.600000 6.870000 1.645000 ; - RECT 8.825000 1.415000 9.115000 1.460000 ; - RECT 8.825000 1.600000 9.115000 1.645000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 2.905000 0.725000 3.100000 1.055000 ; - RECT 2.905000 1.055000 3.565000 1.590000 ; - RECT 2.905000 1.590000 3.085000 1.960000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.340000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 13.530000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.340000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 13.340000 0.085000 ; - RECT 0.000000 2.635000 13.340000 2.805000 ; - RECT 0.085000 0.085000 0.480000 0.595000 ; - RECT 0.085000 1.845000 1.105000 2.025000 ; - RECT 0.085000 2.025000 0.345000 2.465000 ; - RECT 0.515000 2.195000 0.765000 2.635000 ; - RECT 0.875000 0.280000 1.655000 0.560000 ; - RECT 0.935000 2.025000 1.105000 2.255000 ; - RECT 0.935000 2.255000 2.045000 2.465000 ; - RECT 1.295000 1.870000 1.695000 2.075000 ; - RECT 1.380000 0.560000 1.655000 0.590000 ; - RECT 1.380000 0.590000 1.660000 0.600000 ; - RECT 1.395000 0.600000 1.660000 0.605000 ; - RECT 1.405000 0.605000 1.660000 0.610000 ; - RECT 1.420000 0.610000 1.660000 0.615000 ; - RECT 1.430000 0.615000 1.670000 0.620000 ; - RECT 1.440000 0.620000 1.670000 0.630000 ; - RECT 1.445000 0.630000 1.670000 0.635000 ; - RECT 1.460000 0.635000 1.670000 0.645000 ; - RECT 1.475000 0.645000 1.670000 0.655000 ; - RECT 1.475000 0.655000 1.695000 0.665000 ; - RECT 1.495000 0.665000 1.695000 0.705000 ; - RECT 1.505000 0.705000 1.695000 1.870000 ; - RECT 1.825000 0.085000 2.005000 0.545000 ; - RECT 1.865000 0.715000 2.515000 0.905000 ; - RECT 1.865000 0.905000 2.200000 1.770000 ; - RECT 1.865000 1.770000 2.520000 2.085000 ; - RECT 2.260000 0.255000 2.515000 0.715000 ; - RECT 2.270000 2.085000 2.520000 2.465000 ; - RECT 2.690000 0.085000 3.030000 0.555000 ; - RECT 2.690000 2.140000 3.030000 2.635000 ; - RECT 3.255000 1.775000 3.995000 1.955000 ; - RECT 3.255000 1.955000 3.425000 2.325000 ; - RECT 3.270000 0.255000 3.455000 0.715000 ; - RECT 3.270000 0.715000 3.995000 0.885000 ; - RECT 3.595000 2.275000 3.925000 2.635000 ; - RECT 3.630000 0.085000 3.940000 0.545000 ; - RECT 3.735000 0.885000 3.995000 1.775000 ; - RECT 4.095000 2.135000 4.440000 2.465000 ; - RECT 4.110000 0.255000 4.335000 0.585000 ; - RECT 4.165000 0.585000 4.335000 1.090000 ; - RECT 4.165000 1.090000 4.490000 1.420000 ; - RECT 4.165000 1.420000 4.440000 2.135000 ; - RECT 4.505000 0.255000 4.830000 0.920000 ; - RECT 4.610000 1.590000 4.915000 1.615000 ; - RECT 4.610000 1.615000 4.830000 2.465000 ; - RECT 4.660000 0.920000 4.830000 1.445000 ; - RECT 4.660000 1.445000 4.915000 1.590000 ; - RECT 5.000000 0.255000 5.440000 1.225000 ; - RECT 5.000000 1.225000 7.660000 1.275000 ; - RECT 5.030000 2.135000 5.755000 2.465000 ; - RECT 5.085000 1.275000 6.435000 1.395000 ; - RECT 5.205000 1.575000 5.415000 1.955000 ; - RECT 5.585000 1.395000 5.755000 2.135000 ; - RECT 5.610000 0.085000 6.095000 0.465000 ; - RECT 5.610000 0.635000 6.535000 0.805000 ; - RECT 5.610000 0.805000 5.975000 1.015000 ; - RECT 5.925000 1.575000 6.095000 1.935000 ; - RECT 5.925000 1.935000 6.765000 2.105000 ; - RECT 5.945000 2.275000 6.275000 2.635000 ; - RECT 6.250000 0.975000 7.660000 1.225000 ; - RECT 6.275000 0.255000 6.535000 0.635000 ; - RECT 6.550000 2.105000 6.765000 2.450000 ; - RECT 6.735000 0.085000 7.630000 0.805000 ; - RECT 7.005000 2.125000 7.960000 2.635000 ; - RECT 7.190000 1.495000 8.005000 1.955000 ; - RECT 7.300000 1.275000 7.660000 1.325000 ; - RECT 7.835000 0.695000 9.040000 0.895000 ; - RECT 7.835000 0.895000 8.005000 1.495000 ; - RECT 8.130000 2.125000 8.935000 2.460000 ; - RECT 8.365000 1.075000 8.595000 1.905000 ; - RECT 8.410000 0.275000 9.825000 0.445000 ; - RECT 8.765000 1.895000 10.465000 2.065000 ; - RECT 8.765000 2.065000 8.935000 2.125000 ; - RECT 8.810000 0.895000 9.040000 1.245000 ; - RECT 9.195000 2.235000 9.525000 2.635000 ; - RECT 9.290000 0.855000 9.465000 1.185000 ; - RECT 9.290000 1.185000 10.895000 1.355000 ; - RECT 9.655000 0.445000 9.825000 0.845000 ; - RECT 9.655000 0.845000 10.545000 1.015000 ; - RECT 9.695000 2.065000 9.910000 2.450000 ; - RECT 10.135000 2.235000 10.465000 2.635000 ; - RECT 10.220000 0.085000 10.390000 0.545000 ; - RECT 10.245000 1.525000 10.465000 1.895000 ; - RECT 10.560000 0.255000 10.895000 0.540000 ; - RECT 10.635000 1.355000 10.895000 2.465000 ; - RECT 10.715000 0.540000 10.895000 1.185000 ; - RECT 11.120000 0.085000 11.330000 0.885000 ; - RECT 11.120000 1.485000 11.330000 2.635000 ; - RECT 12.060000 0.255000 12.270000 0.995000 ; - RECT 12.060000 0.995000 12.900000 1.325000 ; - RECT 12.060000 1.325000 12.270000 2.465000 ; - RECT 12.540000 0.085000 12.745000 0.825000 ; - RECT 12.575000 1.575000 12.745000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.785000 3.995000 1.955000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.445000 4.915000 1.615000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 1.785000 7.675000 1.955000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 1.105000 8.595000 1.275000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 4.975000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 3.765000 1.755000 4.055000 1.800000 ; - RECT 3.765000 1.800000 7.735000 1.940000 ; - RECT 3.765000 1.940000 4.055000 1.985000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.120000 8.655000 1.260000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.415000 4.975000 1.460000 ; - RECT 4.685000 1.600000 4.975000 1.645000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 7.445000 1.755000 7.735000 1.800000 ; - RECT 7.445000 1.940000 7.735000 1.985000 ; - RECT 8.365000 1.075000 8.655000 1.120000 ; - RECT 8.365000 1.260000 8.655000 1.305000 ; - END -END sky130_fd_sc_hd__sdfsbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfsbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfsbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.26000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.050000 0.765000 1.335000 1.675000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 13.410000 0.275000 13.740000 0.825000 ; - RECT 13.410000 1.495000 13.740000 2.450000 ; - RECT 13.515000 0.825000 13.740000 1.495000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.460000 0.255000 11.855000 2.465000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.340000 1.675000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 0.765000 0.820000 1.675000 ; - LAYER mcon ; - RECT 0.605000 1.105000 0.775000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.405000 1.075000 2.735000 1.590000 ; - LAYER mcon ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.545000 1.075000 0.835000 1.120000 ; - RECT 0.545000 1.120000 2.675000 1.260000 ; - RECT 0.545000 1.260000 0.835000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.640000 1.445000 7.065000 1.765000 ; - END - PORT - LAYER li1 ; - RECT 8.880000 1.435000 9.115000 1.525000 ; - RECT 8.880000 1.525000 9.935000 1.725000 ; - LAYER mcon ; - RECT 8.940000 1.445000 9.110000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 6.580000 1.415000 6.870000 1.460000 ; - RECT 6.580000 1.460000 9.170000 1.600000 ; - RECT 6.580000 1.600000 6.870000 1.645000 ; - RECT 8.880000 1.415000 9.170000 1.460000 ; - RECT 8.880000 1.600000 9.170000 1.645000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 2.905000 0.725000 3.100000 1.055000 ; - RECT 2.905000 1.055000 3.565000 1.615000 ; - RECT 2.905000 1.615000 3.100000 1.970000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.260000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 14.450000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.260000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.260000 0.085000 ; - RECT 0.000000 2.635000 14.260000 2.805000 ; - RECT 0.085000 0.085000 0.700000 0.595000 ; - RECT 0.085000 1.845000 1.185000 2.075000 ; - RECT 0.085000 2.075000 0.345000 2.465000 ; - RECT 0.515000 2.275000 0.845000 2.635000 ; - RECT 0.870000 0.255000 1.670000 0.595000 ; - RECT 1.015000 2.075000 1.185000 2.255000 ; - RECT 1.015000 2.255000 2.105000 2.465000 ; - RECT 1.355000 1.845000 1.695000 2.085000 ; - RECT 1.495000 0.595000 1.670000 0.645000 ; - RECT 1.495000 0.645000 1.695000 0.705000 ; - RECT 1.500000 0.705000 1.695000 0.720000 ; - RECT 1.505000 0.720000 1.695000 1.845000 ; - RECT 1.840000 0.085000 2.090000 0.545000 ; - RECT 1.980000 0.715000 2.530000 0.905000 ; - RECT 1.980000 0.905000 2.235000 1.760000 ; - RECT 1.980000 1.760000 2.535000 2.085000 ; - RECT 2.260000 0.255000 2.530000 0.715000 ; - RECT 2.275000 2.085000 2.535000 2.465000 ; - RECT 2.700000 0.085000 3.100000 0.555000 ; - RECT 2.705000 2.140000 3.100000 2.635000 ; - RECT 3.270000 0.255000 3.470000 0.715000 ; - RECT 3.270000 0.715000 3.995000 0.885000 ; - RECT 3.270000 1.830000 3.995000 2.000000 ; - RECT 3.270000 2.000000 3.475000 2.325000 ; - RECT 3.640000 0.085000 3.940000 0.545000 ; - RECT 3.645000 2.275000 3.975000 2.635000 ; - RECT 3.735000 0.885000 3.995000 1.830000 ; - RECT 4.110000 0.255000 4.335000 0.585000 ; - RECT 4.145000 2.135000 4.440000 2.465000 ; - RECT 4.165000 0.585000 4.335000 1.090000 ; - RECT 4.165000 1.090000 4.490000 1.420000 ; - RECT 4.165000 1.420000 4.440000 2.135000 ; - RECT 4.505000 0.255000 4.885000 0.920000 ; - RECT 4.665000 1.590000 4.970000 1.615000 ; - RECT 4.665000 1.615000 4.890000 2.465000 ; - RECT 4.715000 0.920000 4.885000 1.445000 ; - RECT 4.715000 1.445000 4.970000 1.590000 ; - RECT 5.055000 0.255000 5.450000 1.225000 ; - RECT 5.055000 1.225000 7.705000 1.275000 ; - RECT 5.060000 2.135000 5.805000 2.465000 ; - RECT 5.140000 1.275000 6.475000 1.395000 ; - RECT 5.205000 1.575000 5.465000 1.955000 ; - RECT 5.620000 0.635000 6.550000 0.805000 ; - RECT 5.620000 0.805000 6.015000 1.015000 ; - RECT 5.635000 1.395000 5.805000 2.135000 ; - RECT 5.665000 0.085000 6.165000 0.465000 ; - RECT 5.975000 1.575000 6.145000 1.935000 ; - RECT 5.975000 1.935000 6.820000 2.105000 ; - RECT 6.000000 2.275000 6.330000 2.635000 ; - RECT 6.305000 0.975000 7.705000 1.225000 ; - RECT 6.335000 0.255000 6.550000 0.635000 ; - RECT 6.605000 2.105000 6.820000 2.450000 ; - RECT 6.720000 0.085000 7.705000 0.805000 ; - RECT 7.060000 2.125000 8.015000 2.635000 ; - RECT 7.355000 1.275000 7.705000 1.325000 ; - RECT 7.385000 1.705000 8.055000 1.955000 ; - RECT 7.885000 0.695000 9.085000 0.895000 ; - RECT 7.885000 0.895000 8.055000 1.705000 ; - RECT 8.185000 2.125000 8.990000 2.460000 ; - RECT 8.420000 1.075000 8.650000 1.905000 ; - RECT 8.465000 0.275000 9.855000 0.515000 ; - RECT 8.820000 1.895000 10.430000 2.065000 ; - RECT 8.820000 2.065000 8.990000 2.125000 ; - RECT 8.830000 0.895000 9.085000 1.265000 ; - RECT 9.160000 2.235000 9.490000 2.635000 ; - RECT 9.285000 0.855000 9.515000 1.185000 ; - RECT 9.285000 1.185000 10.910000 1.355000 ; - RECT 9.660000 2.065000 9.930000 2.450000 ; - RECT 9.685000 0.515000 9.855000 0.845000 ; - RECT 9.685000 0.845000 10.560000 1.015000 ; - RECT 10.035000 0.085000 10.285000 0.545000 ; - RECT 10.100000 2.235000 10.430000 2.635000 ; - RECT 10.105000 1.525000 10.430000 1.895000 ; - RECT 10.465000 0.255000 10.910000 0.585000 ; - RECT 10.600000 1.355000 10.845000 2.465000 ; - RECT 10.730000 0.585000 10.910000 1.185000 ; - RECT 11.080000 1.485000 11.290000 2.635000 ; - RECT 11.120000 0.085000 11.290000 0.885000 ; - RECT 12.025000 0.085000 12.315000 0.885000 ; - RECT 12.025000 1.485000 12.315000 2.635000 ; - RECT 12.530000 0.255000 12.715000 0.995000 ; - RECT 12.530000 0.995000 13.345000 1.325000 ; - RECT 12.530000 1.325000 12.715000 2.465000 ; - RECT 12.885000 0.085000 13.240000 0.825000 ; - RECT 12.885000 1.635000 13.240000 2.635000 ; - RECT 13.910000 0.085000 14.175000 0.885000 ; - RECT 13.910000 1.485000 14.175000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.785000 3.995000 1.955000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.800000 1.445000 4.970000 1.615000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.260000 1.785000 5.430000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.560000 1.785000 7.730000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.480000 1.105000 8.650000 1.275000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 5.030000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 3.765000 1.755000 4.055000 1.800000 ; - RECT 3.765000 1.800000 7.790000 1.940000 ; - RECT 3.765000 1.940000 4.055000 1.985000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.120000 8.710000 1.260000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.740000 1.415000 5.030000 1.460000 ; - RECT 4.740000 1.600000 5.030000 1.645000 ; - RECT 5.200000 1.755000 5.490000 1.800000 ; - RECT 5.200000 1.940000 5.490000 1.985000 ; - RECT 7.500000 1.755000 7.790000 1.800000 ; - RECT 7.500000 1.940000 7.790000 1.985000 ; - RECT 8.420000 1.075000 8.710000 1.120000 ; - RECT 8.420000 1.260000 8.710000 1.305000 ; - END -END sky130_fd_sc_hd__sdfsbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfstp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfstp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.42000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.050000 0.765000 1.335000 1.675000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.995000 0.275000 12.335000 0.825000 ; - RECT 11.995000 1.495000 12.335000 2.450000 ; - RECT 12.145000 0.825000 12.335000 1.495000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.340000 1.675000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 0.765000 0.820000 1.675000 ; - LAYER mcon ; - RECT 0.605000 1.105000 0.775000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.370000 1.075000 2.700000 1.600000 ; - LAYER mcon ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.545000 1.075000 0.835000 1.120000 ; - RECT 0.545000 1.120000 2.675000 1.260000 ; - RECT 0.545000 1.260000 0.835000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.640000 1.445000 7.065000 1.765000 ; - END - PORT - LAYER li1 ; - RECT 8.880000 1.425000 9.135000 1.545000 ; - RECT 8.880000 1.545000 9.945000 1.725000 ; - LAYER mcon ; - RECT 8.940000 1.445000 9.110000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 6.580000 1.415000 6.870000 1.460000 ; - RECT 6.580000 1.460000 9.170000 1.600000 ; - RECT 6.580000 1.600000 6.870000 1.645000 ; - RECT 8.880000 1.415000 9.170000 1.460000 ; - RECT 8.880000 1.600000 9.170000 1.645000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 2.905000 0.725000 3.100000 1.055000 ; - RECT 2.905000 1.055000 3.565000 1.615000 ; - RECT 2.905000 1.615000 3.085000 1.960000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.420000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.610000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.420000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.420000 0.085000 ; - RECT 0.000000 2.635000 12.420000 2.805000 ; - RECT 0.085000 0.085000 0.700000 0.595000 ; - RECT 0.085000 1.845000 1.125000 2.025000 ; - RECT 0.085000 2.025000 0.345000 2.465000 ; - RECT 0.515000 2.195000 0.785000 2.635000 ; - RECT 0.870000 0.255000 1.625000 0.555000 ; - RECT 0.870000 0.555000 1.640000 0.575000 ; - RECT 0.870000 0.575000 1.650000 0.595000 ; - RECT 0.955000 2.025000 1.125000 2.255000 ; - RECT 0.955000 2.255000 2.045000 2.465000 ; - RECT 1.295000 1.845000 1.695000 2.085000 ; - RECT 1.380000 0.595000 1.660000 0.600000 ; - RECT 1.395000 0.600000 1.660000 0.605000 ; - RECT 1.405000 0.605000 1.660000 0.610000 ; - RECT 1.420000 0.610000 1.660000 0.615000 ; - RECT 1.430000 0.615000 1.660000 0.620000 ; - RECT 1.440000 0.620000 1.665000 0.630000 ; - RECT 1.445000 0.630000 1.665000 0.635000 ; - RECT 1.460000 0.635000 1.665000 0.645000 ; - RECT 1.475000 0.645000 1.670000 0.660000 ; - RECT 1.475000 0.660000 1.675000 0.665000 ; - RECT 1.495000 0.665000 1.675000 0.705000 ; - RECT 1.505000 0.705000 1.675000 0.710000 ; - RECT 1.505000 0.710000 1.695000 1.845000 ; - RECT 1.825000 0.085000 2.090000 0.545000 ; - RECT 1.865000 0.715000 2.520000 0.905000 ; - RECT 1.865000 0.905000 2.200000 1.770000 ; - RECT 1.865000 1.770000 2.520000 2.085000 ; - RECT 2.260000 0.255000 2.520000 0.715000 ; - RECT 2.270000 2.085000 2.520000 2.465000 ; - RECT 2.690000 0.085000 3.100000 0.555000 ; - RECT 2.690000 2.140000 2.985000 2.635000 ; - RECT 3.255000 1.830000 3.995000 1.990000 ; - RECT 3.255000 1.990000 3.985000 2.000000 ; - RECT 3.255000 2.000000 3.425000 2.325000 ; - RECT 3.270000 0.255000 3.455000 0.715000 ; - RECT 3.270000 0.715000 3.995000 0.885000 ; - RECT 3.595000 2.275000 3.925000 2.635000 ; - RECT 3.625000 0.085000 3.955000 0.545000 ; - RECT 3.735000 0.885000 3.995000 1.830000 ; - RECT 4.095000 2.135000 4.440000 2.465000 ; - RECT 4.125000 0.255000 4.335000 0.585000 ; - RECT 4.165000 0.585000 4.335000 1.090000 ; - RECT 4.165000 1.090000 4.490000 1.420000 ; - RECT 4.165000 1.420000 4.440000 2.135000 ; - RECT 4.505000 0.255000 4.830000 0.920000 ; - RECT 4.615000 1.590000 4.915000 1.615000 ; - RECT 4.615000 1.615000 4.830000 2.465000 ; - RECT 4.660000 0.920000 4.830000 1.445000 ; - RECT 4.660000 1.445000 4.915000 1.590000 ; - RECT 5.000000 0.255000 5.440000 1.225000 ; - RECT 5.000000 1.225000 7.715000 1.275000 ; - RECT 5.035000 2.135000 5.755000 2.465000 ; - RECT 5.085000 1.275000 6.475000 1.395000 ; - RECT 5.205000 1.575000 5.415000 1.955000 ; - RECT 5.585000 1.395000 5.755000 2.135000 ; - RECT 5.610000 0.085000 6.095000 0.465000 ; - RECT 5.645000 0.635000 6.535000 0.805000 ; - RECT 5.645000 0.805000 5.975000 1.015000 ; - RECT 5.925000 1.575000 6.095000 1.935000 ; - RECT 5.925000 1.935000 6.820000 2.105000 ; - RECT 5.945000 2.275000 6.330000 2.635000 ; - RECT 6.285000 0.255000 6.535000 0.635000 ; - RECT 6.305000 0.975000 7.715000 1.225000 ; - RECT 6.605000 2.105000 6.820000 2.450000 ; - RECT 6.705000 0.085000 7.715000 0.805000 ; - RECT 7.060000 2.125000 8.015000 2.635000 ; - RECT 7.235000 1.670000 8.135000 1.955000 ; - RECT 7.355000 1.275000 7.715000 1.325000 ; - RECT 7.885000 0.720000 9.105000 0.905000 ; - RECT 7.885000 0.905000 8.135000 1.670000 ; - RECT 8.185000 2.125000 8.990000 2.460000 ; - RECT 8.425000 1.075000 8.650000 1.905000 ; - RECT 8.465000 0.275000 9.910000 0.545000 ; - RECT 8.820000 0.905000 9.105000 1.255000 ; - RECT 8.820000 1.895000 10.485000 2.065000 ; - RECT 8.820000 2.065000 8.990000 2.125000 ; - RECT 9.160000 2.235000 9.490000 2.635000 ; - RECT 9.320000 0.855000 9.530000 1.195000 ; - RECT 9.320000 1.195000 10.915000 1.365000 ; - RECT 9.660000 2.065000 9.965000 2.450000 ; - RECT 9.710000 0.545000 9.910000 0.785000 ; - RECT 9.710000 0.785000 10.515000 1.015000 ; - RECT 10.115000 0.085000 10.365000 0.545000 ; - RECT 10.155000 1.605000 10.485000 1.895000 ; - RECT 10.155000 2.235000 10.485000 2.635000 ; - RECT 10.575000 0.255000 10.915000 0.585000 ; - RECT 10.655000 1.365000 10.915000 2.465000 ; - RECT 10.685000 0.585000 10.915000 1.195000 ; - RECT 11.085000 0.255000 11.345000 0.995000 ; - RECT 11.085000 0.995000 11.975000 1.325000 ; - RECT 11.085000 1.325000 11.345000 2.465000 ; - RECT 11.515000 0.085000 11.825000 0.825000 ; - RECT 11.515000 1.790000 11.825000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.785000 3.995000 1.955000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.445000 4.915000 1.615000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.560000 1.785000 7.730000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.480000 1.105000 8.650000 1.275000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 4.975000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 3.765000 1.755000 4.055000 1.800000 ; - RECT 3.765000 1.800000 7.790000 1.940000 ; - RECT 3.765000 1.940000 4.055000 1.985000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.120000 8.710000 1.260000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.415000 4.975000 1.460000 ; - RECT 4.685000 1.600000 4.975000 1.645000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 7.500000 1.755000 7.790000 1.800000 ; - RECT 7.500000 1.940000 7.790000 1.985000 ; - RECT 8.420000 1.075000 8.710000 1.120000 ; - RECT 8.420000 1.260000 8.710000 1.305000 ; - END -END sky130_fd_sc_hd__sdfstp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfstp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfstp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 12.88000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.050000 0.765000 1.335000 1.675000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.519750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.035000 0.255000 12.365000 0.825000 ; - RECT 12.035000 1.495000 12.365000 2.450000 ; - RECT 12.145000 0.825000 12.365000 1.495000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.340000 1.675000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 0.765000 0.820000 1.675000 ; - LAYER mcon ; - RECT 0.605000 1.105000 0.775000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.370000 1.075000 2.700000 1.600000 ; - LAYER mcon ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.545000 1.075000 0.835000 1.120000 ; - RECT 0.545000 1.120000 2.675000 1.260000 ; - RECT 0.545000 1.260000 0.835000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.640000 1.445000 7.065000 1.765000 ; - END - PORT - LAYER li1 ; - RECT 8.880000 1.425000 9.135000 1.545000 ; - RECT 8.880000 1.545000 9.945000 1.725000 ; - LAYER mcon ; - RECT 8.940000 1.445000 9.110000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 6.580000 1.415000 6.870000 1.460000 ; - RECT 6.580000 1.460000 9.170000 1.600000 ; - RECT 6.580000 1.600000 6.870000 1.645000 ; - RECT 8.880000 1.415000 9.170000 1.460000 ; - RECT 8.880000 1.600000 9.170000 1.645000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 2.905000 0.725000 3.100000 1.055000 ; - RECT 2.905000 1.055000 3.565000 1.615000 ; - RECT 2.905000 1.615000 3.085000 1.960000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 12.880000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 13.070000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 12.880000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 12.880000 0.085000 ; - RECT 0.000000 2.635000 12.880000 2.805000 ; - RECT 0.085000 0.085000 0.700000 0.595000 ; - RECT 0.085000 1.845000 1.125000 2.025000 ; - RECT 0.085000 2.025000 0.345000 2.465000 ; - RECT 0.515000 2.195000 0.785000 2.635000 ; - RECT 0.870000 0.255000 1.625000 0.555000 ; - RECT 0.870000 0.555000 1.640000 0.575000 ; - RECT 0.870000 0.575000 1.650000 0.595000 ; - RECT 0.955000 2.025000 1.125000 2.255000 ; - RECT 0.955000 2.255000 2.045000 2.465000 ; - RECT 1.295000 1.845000 1.695000 2.085000 ; - RECT 1.380000 0.595000 1.660000 0.600000 ; - RECT 1.395000 0.600000 1.660000 0.605000 ; - RECT 1.405000 0.605000 1.660000 0.610000 ; - RECT 1.420000 0.610000 1.660000 0.615000 ; - RECT 1.430000 0.615000 1.660000 0.620000 ; - RECT 1.440000 0.620000 1.665000 0.630000 ; - RECT 1.445000 0.630000 1.665000 0.635000 ; - RECT 1.460000 0.635000 1.665000 0.645000 ; - RECT 1.475000 0.645000 1.670000 0.660000 ; - RECT 1.475000 0.660000 1.675000 0.665000 ; - RECT 1.495000 0.665000 1.675000 0.705000 ; - RECT 1.505000 0.705000 1.675000 0.710000 ; - RECT 1.505000 0.710000 1.695000 1.845000 ; - RECT 1.825000 0.085000 2.090000 0.545000 ; - RECT 1.865000 0.715000 2.520000 0.905000 ; - RECT 1.865000 0.905000 2.200000 1.770000 ; - RECT 1.865000 1.770000 2.520000 2.085000 ; - RECT 2.260000 0.255000 2.520000 0.715000 ; - RECT 2.270000 2.085000 2.520000 2.465000 ; - RECT 2.690000 0.085000 3.100000 0.555000 ; - RECT 2.690000 2.140000 2.985000 2.635000 ; - RECT 3.255000 1.830000 3.995000 1.990000 ; - RECT 3.255000 1.990000 3.985000 2.000000 ; - RECT 3.255000 2.000000 3.425000 2.325000 ; - RECT 3.270000 0.255000 3.455000 0.715000 ; - RECT 3.270000 0.715000 3.995000 0.885000 ; - RECT 3.595000 2.275000 3.925000 2.635000 ; - RECT 3.625000 0.085000 3.955000 0.545000 ; - RECT 3.735000 0.885000 3.995000 1.830000 ; - RECT 4.095000 2.135000 4.440000 2.465000 ; - RECT 4.125000 0.255000 4.335000 0.585000 ; - RECT 4.165000 0.585000 4.335000 1.090000 ; - RECT 4.165000 1.090000 4.490000 1.420000 ; - RECT 4.165000 1.420000 4.440000 2.135000 ; - RECT 4.505000 0.255000 4.830000 0.920000 ; - RECT 4.615000 1.590000 4.915000 1.615000 ; - RECT 4.615000 1.615000 4.830000 2.465000 ; - RECT 4.660000 0.920000 4.830000 1.445000 ; - RECT 4.660000 1.445000 4.915000 1.590000 ; - RECT 5.000000 0.255000 5.440000 1.225000 ; - RECT 5.000000 1.225000 7.715000 1.275000 ; - RECT 5.035000 2.135000 5.755000 2.465000 ; - RECT 5.085000 1.275000 6.475000 1.395000 ; - RECT 5.205000 1.575000 5.415000 1.955000 ; - RECT 5.585000 1.395000 5.755000 2.135000 ; - RECT 5.610000 0.085000 6.095000 0.465000 ; - RECT 5.645000 0.635000 6.535000 0.805000 ; - RECT 5.645000 0.805000 5.975000 1.015000 ; - RECT 5.925000 1.575000 6.095000 1.935000 ; - RECT 5.925000 1.935000 6.820000 2.105000 ; - RECT 5.945000 2.275000 6.330000 2.635000 ; - RECT 6.285000 0.255000 6.535000 0.635000 ; - RECT 6.305000 0.975000 7.715000 1.225000 ; - RECT 6.605000 2.105000 6.820000 2.450000 ; - RECT 6.705000 0.085000 7.715000 0.805000 ; - RECT 7.060000 2.125000 8.015000 2.635000 ; - RECT 7.235000 1.670000 8.135000 1.955000 ; - RECT 7.355000 1.275000 7.715000 1.325000 ; - RECT 7.885000 0.720000 9.105000 0.905000 ; - RECT 7.885000 0.905000 8.135000 1.670000 ; - RECT 8.185000 2.125000 8.990000 2.460000 ; - RECT 8.425000 1.075000 8.650000 1.905000 ; - RECT 8.465000 0.275000 9.910000 0.545000 ; - RECT 8.820000 0.905000 9.105000 1.255000 ; - RECT 8.820000 1.895000 10.485000 2.065000 ; - RECT 8.820000 2.065000 8.990000 2.125000 ; - RECT 9.160000 2.235000 9.490000 2.635000 ; - RECT 9.320000 0.855000 9.530000 1.195000 ; - RECT 9.320000 1.195000 10.915000 1.365000 ; - RECT 9.660000 2.065000 9.965000 2.450000 ; - RECT 9.710000 0.545000 9.910000 0.785000 ; - RECT 9.710000 0.785000 10.515000 1.015000 ; - RECT 10.115000 0.085000 10.365000 0.545000 ; - RECT 10.155000 1.605000 10.485000 1.895000 ; - RECT 10.155000 2.235000 10.485000 2.635000 ; - RECT 10.575000 0.255000 10.915000 0.585000 ; - RECT 10.655000 1.365000 10.915000 2.465000 ; - RECT 10.685000 0.585000 10.915000 1.195000 ; - RECT 11.085000 0.255000 11.345000 0.995000 ; - RECT 11.085000 0.995000 11.975000 1.325000 ; - RECT 11.085000 1.325000 11.345000 2.465000 ; - RECT 11.570000 0.085000 11.865000 0.825000 ; - RECT 11.570000 1.790000 11.820000 2.635000 ; - RECT 12.535000 0.085000 12.795000 0.885000 ; - RECT 12.535000 1.495000 12.795000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.785000 3.995000 1.955000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.445000 4.915000 1.615000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.560000 1.785000 7.730000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.480000 1.105000 8.650000 1.275000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 4.975000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 3.765000 1.755000 4.055000 1.800000 ; - RECT 3.765000 1.800000 7.790000 1.940000 ; - RECT 3.765000 1.940000 4.055000 1.985000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.120000 8.710000 1.260000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.415000 4.975000 1.460000 ; - RECT 4.685000 1.600000 4.975000 1.645000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 7.500000 1.755000 7.790000 1.800000 ; - RECT 7.500000 1.940000 7.790000 1.985000 ; - RECT 8.420000 1.075000 8.710000 1.120000 ; - RECT 8.420000 1.260000 8.710000 1.305000 ; - END -END sky130_fd_sc_hd__sdfstp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfstp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfstp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.80000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.050000 0.765000 1.335000 1.675000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.040000 0.275000 12.370000 0.825000 ; - RECT 12.040000 1.495000 12.370000 2.450000 ; - RECT 12.145000 0.825000 12.370000 1.055000 ; - RECT 12.145000 1.055000 13.210000 1.325000 ; - RECT 12.145000 1.325000 12.370000 1.495000 ; - RECT 12.880000 0.255000 13.210000 1.055000 ; - RECT 12.880000 1.325000 13.210000 2.465000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.765000 0.340000 1.675000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.540000 0.765000 0.820000 1.675000 ; - LAYER mcon ; - RECT 0.605000 1.105000 0.775000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 2.370000 1.075000 2.700000 1.600000 ; - LAYER mcon ; - RECT 2.445000 1.105000 2.615000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 0.545000 1.075000 0.835000 1.120000 ; - RECT 0.545000 1.120000 2.675000 1.260000 ; - RECT 0.545000 1.260000 0.835000 1.305000 ; - RECT 2.385000 1.075000 2.675000 1.120000 ; - RECT 2.385000 1.260000 2.675000 1.305000 ; - END - END SCE - PIN SET_B - ANTENNAGATEAREA 0.252000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.640000 1.445000 7.065000 1.765000 ; - END - PORT - LAYER li1 ; - RECT 8.880000 1.425000 9.135000 1.545000 ; - RECT 8.880000 1.545000 9.945000 1.725000 ; - LAYER mcon ; - RECT 8.940000 1.445000 9.110000 1.615000 ; - END - PORT - LAYER met1 ; - RECT 6.580000 1.415000 6.870000 1.460000 ; - RECT 6.580000 1.460000 9.170000 1.600000 ; - RECT 6.580000 1.600000 6.870000 1.645000 ; - RECT 8.880000 1.415000 9.170000 1.460000 ; - RECT 8.880000 1.600000 9.170000 1.645000 ; - END - END SET_B - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 2.905000 0.725000 3.100000 1.055000 ; - RECT 2.905000 1.055000 3.565000 1.615000 ; - RECT 2.905000 1.615000 3.085000 1.960000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.800000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 13.990000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.800000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 13.800000 0.085000 ; - RECT 0.000000 2.635000 13.800000 2.805000 ; - RECT 0.085000 0.085000 0.700000 0.595000 ; - RECT 0.085000 1.845000 1.125000 2.025000 ; - RECT 0.085000 2.025000 0.345000 2.465000 ; - RECT 0.515000 2.195000 0.785000 2.635000 ; - RECT 0.870000 0.255000 1.625000 0.555000 ; - RECT 0.870000 0.555000 1.640000 0.575000 ; - RECT 0.870000 0.575000 1.650000 0.595000 ; - RECT 0.955000 2.025000 1.125000 2.255000 ; - RECT 0.955000 2.255000 2.045000 2.465000 ; - RECT 1.295000 1.845000 1.695000 2.085000 ; - RECT 1.380000 0.595000 1.660000 0.600000 ; - RECT 1.395000 0.600000 1.660000 0.605000 ; - RECT 1.405000 0.605000 1.660000 0.610000 ; - RECT 1.420000 0.610000 1.660000 0.615000 ; - RECT 1.430000 0.615000 1.660000 0.620000 ; - RECT 1.440000 0.620000 1.665000 0.630000 ; - RECT 1.445000 0.630000 1.665000 0.635000 ; - RECT 1.460000 0.635000 1.665000 0.645000 ; - RECT 1.475000 0.645000 1.670000 0.660000 ; - RECT 1.475000 0.660000 1.675000 0.665000 ; - RECT 1.495000 0.665000 1.675000 0.705000 ; - RECT 1.505000 0.705000 1.675000 0.710000 ; - RECT 1.505000 0.710000 1.695000 1.845000 ; - RECT 1.825000 0.085000 2.090000 0.545000 ; - RECT 1.865000 0.715000 2.520000 0.905000 ; - RECT 1.865000 0.905000 2.200000 1.770000 ; - RECT 1.865000 1.770000 2.520000 2.085000 ; - RECT 2.260000 0.255000 2.520000 0.715000 ; - RECT 2.270000 2.085000 2.520000 2.465000 ; - RECT 2.690000 0.085000 3.100000 0.555000 ; - RECT 2.690000 2.140000 2.985000 2.635000 ; - RECT 3.255000 1.830000 3.995000 1.990000 ; - RECT 3.255000 1.990000 3.985000 2.000000 ; - RECT 3.255000 2.000000 3.425000 2.325000 ; - RECT 3.270000 0.255000 3.455000 0.715000 ; - RECT 3.270000 0.715000 3.995000 0.885000 ; - RECT 3.595000 2.275000 3.925000 2.635000 ; - RECT 3.625000 0.085000 3.955000 0.545000 ; - RECT 3.735000 0.885000 3.995000 1.830000 ; - RECT 4.095000 2.135000 4.440000 2.465000 ; - RECT 4.125000 0.255000 4.335000 0.585000 ; - RECT 4.165000 0.585000 4.335000 1.090000 ; - RECT 4.165000 1.090000 4.490000 1.420000 ; - RECT 4.165000 1.420000 4.440000 2.135000 ; - RECT 4.505000 0.255000 4.830000 0.920000 ; - RECT 4.615000 1.590000 4.915000 1.615000 ; - RECT 4.615000 1.615000 4.830000 2.465000 ; - RECT 4.660000 0.920000 4.830000 1.445000 ; - RECT 4.660000 1.445000 4.915000 1.590000 ; - RECT 5.000000 0.255000 5.440000 1.225000 ; - RECT 5.000000 1.225000 7.715000 1.275000 ; - RECT 5.035000 2.135000 5.755000 2.465000 ; - RECT 5.085000 1.275000 6.475000 1.395000 ; - RECT 5.205000 1.575000 5.415000 1.955000 ; - RECT 5.585000 1.395000 5.755000 2.135000 ; - RECT 5.610000 0.085000 6.095000 0.465000 ; - RECT 5.645000 0.635000 6.535000 0.805000 ; - RECT 5.645000 0.805000 5.975000 1.015000 ; - RECT 5.925000 1.575000 6.095000 1.935000 ; - RECT 5.925000 1.935000 6.820000 2.105000 ; - RECT 5.945000 2.275000 6.330000 2.635000 ; - RECT 6.285000 0.255000 6.535000 0.635000 ; - RECT 6.305000 0.975000 7.715000 1.225000 ; - RECT 6.605000 2.105000 6.820000 2.450000 ; - RECT 6.705000 0.085000 7.715000 0.805000 ; - RECT 7.060000 2.125000 8.015000 2.635000 ; - RECT 7.235000 1.670000 8.135000 1.955000 ; - RECT 7.355000 1.275000 7.715000 1.325000 ; - RECT 7.885000 0.720000 9.105000 0.905000 ; - RECT 7.885000 0.905000 8.135000 1.670000 ; - RECT 8.185000 2.125000 8.990000 2.460000 ; - RECT 8.425000 1.075000 8.650000 1.905000 ; - RECT 8.465000 0.275000 9.910000 0.545000 ; - RECT 8.820000 0.905000 9.105000 1.255000 ; - RECT 8.820000 1.895000 10.485000 2.065000 ; - RECT 8.820000 2.065000 8.990000 2.125000 ; - RECT 9.160000 2.235000 9.490000 2.635000 ; - RECT 9.320000 0.855000 9.530000 1.195000 ; - RECT 9.320000 1.195000 10.915000 1.365000 ; - RECT 9.660000 2.065000 9.965000 2.450000 ; - RECT 9.710000 0.545000 9.910000 0.785000 ; - RECT 9.710000 0.785000 10.515000 1.015000 ; - RECT 10.115000 0.085000 10.365000 0.545000 ; - RECT 10.155000 1.605000 10.485000 1.895000 ; - RECT 10.155000 2.235000 10.485000 2.635000 ; - RECT 10.575000 0.255000 10.915000 0.585000 ; - RECT 10.655000 1.365000 10.915000 2.465000 ; - RECT 10.685000 0.585000 10.915000 1.195000 ; - RECT 11.085000 0.255000 11.345000 0.995000 ; - RECT 11.085000 0.995000 11.975000 1.325000 ; - RECT 11.085000 1.325000 11.345000 2.465000 ; - RECT 11.515000 0.085000 11.870000 0.825000 ; - RECT 11.515000 1.495000 11.870000 2.635000 ; - RECT 12.540000 0.085000 12.710000 0.885000 ; - RECT 12.540000 1.495000 12.710000 2.635000 ; - RECT 13.380000 0.085000 13.715000 0.885000 ; - RECT 13.380000 1.495000 13.715000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.785000 3.995000 1.955000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.105000 4.455000 1.275000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 1.445000 4.915000 1.615000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.560000 1.785000 7.730000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.480000 1.105000 8.650000 1.275000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 4.975000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 3.765000 1.755000 4.055000 1.800000 ; - RECT 3.765000 1.800000 7.790000 1.940000 ; - RECT 3.765000 1.940000 4.055000 1.985000 ; - RECT 4.225000 1.075000 4.515000 1.120000 ; - RECT 4.225000 1.120000 8.710000 1.260000 ; - RECT 4.225000 1.260000 4.515000 1.305000 ; - RECT 4.685000 1.415000 4.975000 1.460000 ; - RECT 4.685000 1.600000 4.975000 1.645000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 7.500000 1.755000 7.790000 1.800000 ; - RECT 7.500000 1.940000 7.790000 1.985000 ; - RECT 8.420000 1.075000 8.710000 1.120000 ; - RECT 8.420000 1.260000 8.710000 1.305000 ; - END -END sky130_fd_sc_hd__sdfstp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfxbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfxbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.440000 1.355000 2.775000 1.685000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.180000 0.305000 9.530000 0.725000 ; - RECT 9.180000 0.725000 9.560000 0.790000 ; - RECT 9.180000 0.790000 9.610000 0.825000 ; - RECT 9.200000 1.505000 9.610000 1.540000 ; - RECT 9.200000 1.540000 9.530000 2.465000 ; - RECT 9.355000 1.430000 9.610000 1.505000 ; - RECT 9.390000 0.825000 9.610000 1.430000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 10.685000 0.265000 10.940000 0.795000 ; - RECT 10.685000 1.445000 10.940000 2.325000 ; - RECT 10.730000 0.795000 10.940000 1.445000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.515000 1.055000 3.995000 1.655000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.760000 0.750000 3.235000 0.785000 ; - RECT 1.760000 0.785000 2.010000 0.810000 ; - RECT 1.760000 0.810000 1.990000 0.820000 ; - RECT 1.760000 0.820000 1.975000 0.835000 ; - RECT 1.760000 0.835000 1.970000 0.840000 ; - RECT 1.760000 0.840000 1.965000 0.850000 ; - RECT 1.760000 0.850000 1.960000 0.855000 ; - RECT 1.760000 0.855000 1.955000 0.860000 ; - RECT 1.760000 0.860000 1.950000 0.870000 ; - RECT 1.760000 0.870000 1.945000 0.875000 ; - RECT 1.760000 0.875000 1.940000 0.880000 ; - RECT 1.760000 0.880000 1.930000 1.685000 ; - RECT 1.790000 0.735000 3.235000 0.750000 ; - RECT 1.805000 0.725000 3.235000 0.735000 ; - RECT 1.820000 0.715000 3.235000 0.725000 ; - RECT 1.830000 0.705000 3.235000 0.715000 ; - RECT 1.840000 0.690000 3.235000 0.705000 ; - RECT 1.860000 0.655000 3.235000 0.690000 ; - RECT 1.875000 0.615000 3.235000 0.655000 ; - RECT 2.455000 0.305000 2.630000 0.615000 ; - RECT 3.065000 0.785000 3.235000 1.115000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.810000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.810000 0.970000 ; - RECT 0.615000 0.970000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.420000 0.255000 1.705000 0.585000 ; - RECT 1.420000 0.585000 1.590000 1.860000 ; - RECT 1.420000 1.860000 3.230000 2.075000 ; - RECT 1.420000 2.075000 1.705000 2.445000 ; - RECT 1.875000 2.245000 2.205000 2.635000 ; - RECT 1.955000 0.085000 2.285000 0.445000 ; - RECT 2.100000 0.955000 2.445000 1.125000 ; - RECT 2.100000 1.125000 2.270000 1.860000 ; - RECT 2.675000 2.245000 3.570000 2.415000 ; - RECT 2.800000 0.275000 3.575000 0.445000 ; - RECT 3.060000 1.355000 3.255000 1.685000 ; - RECT 3.060000 1.685000 3.230000 1.860000 ; - RECT 3.400000 1.825000 4.335000 1.995000 ; - RECT 3.400000 1.995000 3.570000 2.245000 ; - RECT 3.405000 0.445000 3.575000 0.715000 ; - RECT 3.405000 0.715000 4.335000 0.885000 ; - RECT 3.740000 2.165000 3.910000 2.635000 ; - RECT 3.745000 0.085000 3.945000 0.545000 ; - RECT 4.165000 0.365000 4.515000 0.535000 ; - RECT 4.165000 0.535000 4.335000 0.715000 ; - RECT 4.165000 0.885000 4.335000 1.825000 ; - RECT 4.165000 1.995000 4.335000 2.070000 ; - RECT 4.165000 2.070000 4.450000 2.440000 ; - RECT 4.505000 0.705000 5.085000 1.035000 ; - RECT 4.505000 1.035000 4.745000 1.905000 ; - RECT 4.645000 2.190000 5.715000 2.360000 ; - RECT 4.685000 0.365000 5.425000 0.535000 ; - RECT 4.935000 1.655000 5.375000 2.010000 ; - RECT 5.255000 0.535000 5.425000 1.315000 ; - RECT 5.255000 1.315000 6.055000 1.485000 ; - RECT 5.545000 1.485000 6.055000 1.575000 ; - RECT 5.545000 1.575000 5.715000 2.190000 ; - RECT 5.595000 0.765000 6.395000 1.065000 ; - RECT 5.595000 1.065000 5.765000 1.095000 ; - RECT 5.675000 0.085000 6.045000 0.585000 ; - RECT 5.885000 1.245000 6.055000 1.315000 ; - RECT 5.885000 1.835000 6.055000 2.635000 ; - RECT 6.225000 0.365000 6.685000 0.535000 ; - RECT 6.225000 0.535000 6.395000 0.765000 ; - RECT 6.225000 1.065000 6.395000 2.135000 ; - RECT 6.225000 2.135000 6.475000 2.465000 ; - RECT 6.565000 0.705000 7.115000 1.035000 ; - RECT 6.565000 1.245000 6.755000 1.965000 ; - RECT 6.700000 2.165000 7.585000 2.335000 ; - RECT 6.915000 0.365000 7.455000 0.535000 ; - RECT 6.925000 1.035000 7.115000 1.575000 ; - RECT 6.925000 1.575000 7.245000 1.905000 ; - RECT 7.285000 0.535000 7.455000 0.995000 ; - RECT 7.285000 0.995000 8.315000 1.325000 ; - RECT 7.285000 1.325000 7.585000 1.405000 ; - RECT 7.415000 1.405000 7.585000 2.165000 ; - RECT 7.700000 0.085000 8.070000 0.615000 ; - RECT 7.755000 1.575000 8.670000 1.905000 ; - RECT 7.765000 2.135000 8.070000 2.635000 ; - RECT 8.340000 0.300000 8.670000 0.825000 ; - RECT 8.380000 1.905000 8.670000 2.455000 ; - RECT 8.485000 0.825000 8.670000 0.995000 ; - RECT 8.485000 0.995000 9.220000 1.325000 ; - RECT 8.485000 1.325000 8.670000 1.575000 ; - RECT 8.840000 0.085000 9.010000 0.695000 ; - RECT 8.840000 1.625000 9.010000 2.635000 ; - RECT 9.700000 0.345000 9.950000 0.620000 ; - RECT 9.700000 1.685000 10.030000 2.425000 ; - RECT 9.780000 0.620000 9.950000 0.995000 ; - RECT 9.780000 0.995000 10.560000 1.325000 ; - RECT 9.780000 1.325000 10.030000 1.685000 ; - RECT 10.185000 0.085000 10.515000 0.805000 ; - RECT 10.210000 1.495000 10.515000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.645000 1.785000 0.815000 1.955000 ; - RECT 1.015000 0.765000 1.185000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.765000 4.915000 0.935000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.165000 1.785000 5.335000 1.955000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.575000 1.785000 6.745000 1.955000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 0.765000 6.755000 0.935000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.585000 1.755000 0.875000 1.800000 ; - RECT 0.585000 1.800000 6.805000 1.940000 ; - RECT 0.585000 1.940000 0.875000 1.985000 ; - RECT 0.955000 0.735000 1.245000 0.780000 ; - RECT 0.955000 0.780000 6.815000 0.920000 ; - RECT 0.955000 0.920000 1.245000 0.965000 ; - RECT 4.685000 0.735000 4.975000 0.780000 ; - RECT 4.685000 0.920000 4.975000 0.965000 ; - RECT 5.105000 1.755000 5.395000 1.800000 ; - RECT 5.105000 1.940000 5.395000 1.985000 ; - RECT 6.515000 1.755000 6.805000 1.800000 ; - RECT 6.515000 1.940000 6.805000 1.985000 ; - RECT 6.525000 0.735000 6.815000 0.780000 ; - RECT 6.525000 0.920000 6.815000 0.965000 ; - END -END sky130_fd_sc_hd__sdfxbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfxbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfxbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.96000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.460000 1.355000 2.795000 1.685000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.255000 0.255000 9.585000 0.790000 ; - RECT 9.255000 0.790000 9.615000 0.825000 ; - RECT 9.255000 1.495000 9.615000 1.530000 ; - RECT 9.255000 1.530000 9.585000 2.430000 ; - RECT 9.410000 0.825000 9.615000 0.890000 ; - RECT 9.410000 1.430000 9.615000 1.495000 ; - RECT 9.445000 0.890000 9.615000 1.430000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.190000 0.265000 11.440000 0.795000 ; - RECT 11.190000 1.445000 11.440000 2.325000 ; - RECT 11.235000 0.795000 11.440000 1.445000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.535000 1.035000 4.035000 1.655000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.780000 0.615000 3.255000 0.785000 ; - RECT 1.780000 0.785000 1.950000 1.685000 ; - RECT 2.475000 0.305000 2.650000 0.615000 ; - RECT 3.085000 0.785000 3.255000 1.115000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.960000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 12.150000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.960000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.960000 0.085000 ; - RECT 0.000000 2.635000 11.960000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.810000 0.805000 ; - RECT 0.180000 1.795000 0.845000 1.965000 ; - RECT 0.180000 1.965000 0.350000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.520000 2.135000 0.850000 2.635000 ; - RECT 0.615000 0.805000 0.810000 0.970000 ; - RECT 0.615000 0.970000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.245000 0.715000 ; - RECT 1.020000 0.715000 1.245000 2.465000 ; - RECT 1.435000 0.275000 1.805000 0.445000 ; - RECT 1.435000 0.445000 1.605000 1.860000 ; - RECT 1.435000 1.860000 3.250000 2.075000 ; - RECT 1.435000 2.075000 1.710000 2.445000 ; - RECT 1.880000 2.245000 2.210000 2.635000 ; - RECT 1.975000 0.085000 2.305000 0.445000 ; - RECT 2.120000 0.955000 2.465000 1.125000 ; - RECT 2.120000 1.125000 2.290000 1.860000 ; - RECT 2.695000 2.245000 3.590000 2.415000 ; - RECT 2.820000 0.275000 3.595000 0.445000 ; - RECT 3.080000 1.355000 3.275000 1.685000 ; - RECT 3.080000 1.685000 3.250000 1.860000 ; - RECT 3.420000 1.825000 4.375000 1.995000 ; - RECT 3.420000 1.995000 3.590000 2.245000 ; - RECT 3.425000 0.445000 3.595000 0.695000 ; - RECT 3.425000 0.695000 4.375000 0.865000 ; - RECT 3.760000 2.165000 3.930000 2.635000 ; - RECT 3.765000 0.085000 3.965000 0.525000 ; - RECT 4.205000 0.365000 4.555000 0.535000 ; - RECT 4.205000 0.535000 4.375000 0.695000 ; - RECT 4.205000 0.865000 4.375000 1.825000 ; - RECT 4.205000 1.995000 4.375000 2.065000 ; - RECT 4.205000 2.065000 4.485000 2.440000 ; - RECT 4.545000 0.705000 5.125000 1.035000 ; - RECT 4.545000 1.035000 4.785000 1.905000 ; - RECT 4.685000 2.190000 5.755000 2.360000 ; - RECT 4.725000 0.365000 5.465000 0.535000 ; - RECT 4.975000 1.655000 5.415000 2.010000 ; - RECT 5.295000 0.535000 5.465000 1.315000 ; - RECT 5.295000 1.315000 6.095000 1.485000 ; - RECT 5.585000 1.485000 6.095000 1.575000 ; - RECT 5.585000 1.575000 5.755000 2.190000 ; - RECT 5.635000 0.765000 6.435000 1.065000 ; - RECT 5.635000 1.065000 5.805000 1.095000 ; - RECT 5.715000 0.085000 6.085000 0.585000 ; - RECT 5.925000 1.245000 6.095000 1.315000 ; - RECT 5.925000 1.835000 6.095000 2.635000 ; - RECT 6.265000 0.365000 6.725000 0.535000 ; - RECT 6.265000 0.535000 6.435000 0.765000 ; - RECT 6.265000 1.065000 6.435000 2.135000 ; - RECT 6.265000 2.135000 6.515000 2.465000 ; - RECT 6.605000 0.705000 7.155000 1.035000 ; - RECT 6.605000 1.245000 6.795000 1.965000 ; - RECT 6.740000 2.165000 7.625000 2.335000 ; - RECT 6.955000 0.365000 7.495000 0.535000 ; - RECT 6.965000 1.035000 7.155000 1.575000 ; - RECT 6.965000 1.575000 7.285000 1.905000 ; - RECT 7.325000 0.535000 7.495000 0.995000 ; - RECT 7.325000 0.995000 8.370000 1.325000 ; - RECT 7.325000 1.325000 7.625000 1.405000 ; - RECT 7.455000 1.405000 7.625000 2.165000 ; - RECT 7.740000 0.085000 8.110000 0.615000 ; - RECT 7.795000 1.575000 8.725000 1.905000 ; - RECT 7.805000 2.135000 8.110000 2.635000 ; - RECT 8.360000 0.300000 8.725000 0.825000 ; - RECT 8.395000 1.905000 8.725000 2.455000 ; - RECT 8.540000 0.825000 8.725000 0.995000 ; - RECT 8.540000 0.995000 9.275000 1.325000 ; - RECT 8.540000 1.325000 8.725000 1.575000 ; - RECT 8.895000 0.085000 9.085000 0.695000 ; - RECT 8.895000 1.625000 9.075000 2.635000 ; - RECT 9.755000 0.085000 9.985000 0.690000 ; - RECT 9.765000 1.615000 9.935000 2.635000 ; - RECT 10.205000 0.345000 10.455000 0.995000 ; - RECT 10.205000 0.995000 11.065000 1.325000 ; - RECT 10.205000 1.325000 10.535000 2.425000 ; - RECT 10.690000 0.085000 11.020000 0.805000 ; - RECT 10.715000 1.495000 11.020000 2.635000 ; - RECT 11.610000 0.085000 11.780000 0.955000 ; - RECT 11.610000 1.395000 11.780000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.645000 1.785000 0.815000 1.955000 ; - RECT 1.050000 0.765000 1.220000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.765000 4.915000 0.935000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.625000 1.785000 6.795000 1.955000 ; - RECT 6.640000 0.765000 6.810000 0.935000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - LAYER met1 ; - RECT 0.585000 1.755000 0.875000 1.800000 ; - RECT 0.585000 1.800000 6.855000 1.940000 ; - RECT 0.585000 1.940000 0.875000 1.985000 ; - RECT 0.990000 0.735000 1.280000 0.780000 ; - RECT 0.990000 0.780000 6.870000 0.920000 ; - RECT 0.990000 0.920000 1.280000 0.965000 ; - RECT 4.685000 0.735000 4.975000 0.780000 ; - RECT 4.685000 0.920000 4.975000 0.965000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 6.565000 1.755000 6.855000 1.800000 ; - RECT 6.565000 1.940000 6.855000 1.985000 ; - RECT 6.580000 0.735000 6.870000 0.780000 ; - RECT 6.580000 0.920000 6.870000 0.965000 ; - END -END sky130_fd_sc_hd__sdfxbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfxtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfxtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.460000 1.355000 2.790000 1.685000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.230000 0.305000 9.575000 0.820000 ; - RECT 9.230000 1.505000 9.575000 2.395000 ; - RECT 9.405000 0.820000 9.575000 1.505000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.530000 1.055000 3.990000 1.655000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.760000 0.635000 3.250000 0.785000 ; - RECT 1.760000 0.785000 1.990000 0.835000 ; - RECT 1.760000 0.835000 1.930000 1.685000 ; - RECT 1.870000 0.615000 3.250000 0.635000 ; - RECT 2.475000 0.305000 2.650000 0.615000 ; - RECT 3.065000 0.785000 3.250000 1.095000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.810000 0.805000 ; - RECT 0.180000 1.795000 0.845000 1.965000 ; - RECT 0.180000 1.965000 0.350000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.520000 2.135000 0.850000 2.635000 ; - RECT 0.615000 0.805000 0.810000 0.970000 ; - RECT 0.615000 0.970000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.230000 0.715000 ; - RECT 1.020000 0.715000 1.230000 2.465000 ; - RECT 1.420000 0.260000 1.790000 0.465000 ; - RECT 1.420000 0.465000 1.590000 1.860000 ; - RECT 1.420000 1.860000 3.220000 2.075000 ; - RECT 1.420000 2.075000 1.710000 2.445000 ; - RECT 1.880000 2.245000 2.210000 2.635000 ; - RECT 1.960000 0.085000 2.305000 0.445000 ; - RECT 2.115000 0.960000 2.460000 1.130000 ; - RECT 2.115000 1.130000 2.290000 1.860000 ; - RECT 2.690000 2.245000 3.560000 2.415000 ; - RECT 2.820000 0.275000 3.590000 0.445000 ; - RECT 3.050000 1.305000 3.270000 1.635000 ; - RECT 3.050000 1.635000 3.220000 1.860000 ; - RECT 3.390000 1.825000 4.350000 1.995000 ; - RECT 3.390000 1.995000 3.560000 2.245000 ; - RECT 3.420000 0.445000 3.590000 0.715000 ; - RECT 3.420000 0.715000 4.350000 0.885000 ; - RECT 3.730000 2.165000 3.925000 2.635000 ; - RECT 3.760000 0.085000 3.960000 0.545000 ; - RECT 4.180000 0.285000 4.460000 0.615000 ; - RECT 4.180000 0.615000 4.350000 0.715000 ; - RECT 4.180000 0.885000 4.350000 1.825000 ; - RECT 4.180000 1.995000 4.350000 2.065000 ; - RECT 4.180000 2.065000 4.420000 2.440000 ; - RECT 4.520000 0.780000 5.100000 1.035000 ; - RECT 4.520000 1.035000 4.760000 1.905000 ; - RECT 4.630000 0.705000 5.100000 0.780000 ; - RECT 4.660000 2.190000 5.730000 2.360000 ; - RECT 4.700000 0.365000 5.440000 0.535000 ; - RECT 4.950000 1.655000 5.390000 2.010000 ; - RECT 5.270000 0.535000 5.440000 1.315000 ; - RECT 5.270000 1.315000 6.070000 1.485000 ; - RECT 5.560000 1.485000 6.070000 1.575000 ; - RECT 5.560000 1.575000 5.730000 2.190000 ; - RECT 5.610000 0.765000 6.410000 1.065000 ; - RECT 5.610000 1.065000 5.780000 1.095000 ; - RECT 5.690000 0.085000 6.060000 0.585000 ; - RECT 5.900000 1.245000 6.070000 1.315000 ; - RECT 5.900000 1.835000 6.070000 2.635000 ; - RECT 6.240000 0.365000 6.700000 0.535000 ; - RECT 6.240000 0.535000 6.410000 0.765000 ; - RECT 6.240000 1.065000 6.410000 2.135000 ; - RECT 6.240000 2.135000 6.490000 2.465000 ; - RECT 6.580000 0.705000 7.130000 1.035000 ; - RECT 6.580000 1.245000 6.770000 1.965000 ; - RECT 6.715000 2.165000 7.600000 2.335000 ; - RECT 6.930000 0.365000 7.470000 0.535000 ; - RECT 6.940000 1.035000 7.130000 1.575000 ; - RECT 6.940000 1.575000 7.260000 1.905000 ; - RECT 7.300000 0.535000 7.470000 0.995000 ; - RECT 7.300000 0.995000 8.365000 1.325000 ; - RECT 7.300000 1.325000 7.600000 1.405000 ; - RECT 7.430000 1.405000 7.600000 2.165000 ; - RECT 7.715000 0.085000 8.085000 0.615000 ; - RECT 7.770000 1.575000 8.705000 1.905000 ; - RECT 7.790000 2.135000 8.095000 2.635000 ; - RECT 8.355000 0.300000 8.705000 0.825000 ; - RECT 8.435000 1.905000 8.705000 2.455000 ; - RECT 8.535000 0.825000 8.705000 0.995000 ; - RECT 8.535000 0.995000 9.235000 1.325000 ; - RECT 8.535000 1.325000 8.705000 1.575000 ; - RECT 8.875000 0.085000 9.045000 0.695000 ; - RECT 8.875000 1.625000 9.045000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.640000 1.785000 0.810000 1.955000 ; - RECT 1.040000 0.765000 1.210000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.765000 4.915000 0.935000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.590000 1.785000 6.760000 1.955000 ; - RECT 6.630000 0.765000 6.800000 0.935000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 0.580000 1.755000 0.870000 1.800000 ; - RECT 0.580000 1.800000 6.820000 1.940000 ; - RECT 0.580000 1.940000 0.870000 1.985000 ; - RECT 0.980000 0.735000 1.270000 0.780000 ; - RECT 0.980000 0.780000 6.860000 0.920000 ; - RECT 0.980000 0.920000 1.270000 0.965000 ; - RECT 4.685000 0.735000 4.975000 0.780000 ; - RECT 4.685000 0.920000 4.975000 0.965000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 6.530000 1.755000 6.820000 1.800000 ; - RECT 6.530000 1.940000 6.820000 1.985000 ; - RECT 6.570000 0.735000 6.860000 0.780000 ; - RECT 6.570000 0.920000 6.860000 0.965000 ; - END -END sky130_fd_sc_hd__sdfxtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfxtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfxtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.460000 1.355000 2.790000 1.685000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.260000 0.305000 9.605000 0.820000 ; - RECT 9.260000 1.505000 9.605000 2.395000 ; - RECT 9.435000 0.820000 9.605000 1.505000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.530000 1.035000 4.020000 1.655000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.780000 0.615000 3.250000 0.785000 ; - RECT 1.780000 0.785000 1.950000 1.685000 ; - RECT 2.475000 0.305000 2.650000 0.615000 ; - RECT 3.080000 0.785000 3.250000 1.115000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.810000 0.805000 ; - RECT 0.180000 1.795000 0.845000 1.965000 ; - RECT 0.180000 1.965000 0.350000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.520000 2.135000 0.850000 2.635000 ; - RECT 0.615000 0.805000 0.810000 0.970000 ; - RECT 0.615000 0.970000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.245000 0.715000 ; - RECT 1.020000 0.715000 1.245000 2.465000 ; - RECT 1.435000 0.275000 1.805000 0.445000 ; - RECT 1.435000 0.445000 1.605000 1.860000 ; - RECT 1.435000 1.860000 3.245000 2.075000 ; - RECT 1.435000 2.075000 1.710000 2.445000 ; - RECT 1.880000 2.245000 2.210000 2.635000 ; - RECT 1.975000 0.085000 2.305000 0.445000 ; - RECT 2.120000 0.955000 2.460000 1.125000 ; - RECT 2.120000 1.125000 2.290000 1.860000 ; - RECT 2.690000 2.245000 3.585000 2.415000 ; - RECT 2.820000 0.275000 3.590000 0.445000 ; - RECT 3.075000 1.355000 3.270000 1.685000 ; - RECT 3.075000 1.685000 3.245000 1.860000 ; - RECT 3.415000 1.825000 4.380000 1.995000 ; - RECT 3.415000 1.995000 3.585000 2.245000 ; - RECT 3.420000 0.445000 3.590000 0.695000 ; - RECT 3.420000 0.695000 4.380000 0.865000 ; - RECT 3.755000 2.165000 3.925000 2.635000 ; - RECT 3.760000 0.085000 3.960000 0.525000 ; - RECT 4.210000 0.365000 4.560000 0.535000 ; - RECT 4.210000 0.535000 4.380000 0.695000 ; - RECT 4.210000 0.865000 4.380000 1.825000 ; - RECT 4.210000 1.995000 4.380000 2.065000 ; - RECT 4.210000 2.065000 4.445000 2.440000 ; - RECT 4.550000 0.705000 5.130000 1.035000 ; - RECT 4.550000 1.035000 4.790000 1.905000 ; - RECT 4.690000 2.190000 5.760000 2.360000 ; - RECT 4.730000 0.365000 5.470000 0.535000 ; - RECT 4.980000 1.655000 5.420000 2.010000 ; - RECT 5.300000 0.535000 5.470000 1.315000 ; - RECT 5.300000 1.315000 6.100000 1.485000 ; - RECT 5.590000 1.485000 6.100000 1.575000 ; - RECT 5.590000 1.575000 5.760000 2.190000 ; - RECT 5.640000 0.765000 6.440000 1.065000 ; - RECT 5.640000 1.065000 5.810000 1.095000 ; - RECT 5.720000 0.085000 6.090000 0.585000 ; - RECT 5.930000 1.245000 6.100000 1.315000 ; - RECT 5.930000 1.835000 6.100000 2.635000 ; - RECT 6.270000 0.365000 6.730000 0.535000 ; - RECT 6.270000 0.535000 6.440000 0.765000 ; - RECT 6.270000 1.065000 6.440000 2.135000 ; - RECT 6.270000 2.135000 6.520000 2.465000 ; - RECT 6.610000 0.705000 7.160000 1.035000 ; - RECT 6.610000 1.245000 6.800000 1.965000 ; - RECT 6.745000 2.165000 7.630000 2.335000 ; - RECT 6.960000 0.365000 7.500000 0.535000 ; - RECT 6.970000 1.035000 7.160000 1.575000 ; - RECT 6.970000 1.575000 7.290000 1.905000 ; - RECT 7.330000 0.535000 7.500000 0.995000 ; - RECT 7.330000 0.995000 8.395000 1.325000 ; - RECT 7.330000 1.325000 7.630000 1.405000 ; - RECT 7.460000 1.405000 7.630000 2.165000 ; - RECT 7.745000 0.085000 8.115000 0.615000 ; - RECT 7.800000 1.575000 8.735000 1.905000 ; - RECT 7.810000 2.135000 8.115000 2.635000 ; - RECT 8.385000 0.300000 8.735000 0.825000 ; - RECT 8.465000 1.905000 8.735000 2.455000 ; - RECT 8.565000 0.825000 8.735000 0.995000 ; - RECT 8.565000 0.995000 9.265000 1.325000 ; - RECT 8.565000 1.325000 8.735000 1.575000 ; - RECT 8.905000 0.085000 9.075000 0.695000 ; - RECT 8.905000 1.625000 9.080000 2.635000 ; - RECT 9.775000 0.085000 9.945000 0.930000 ; - RECT 9.775000 1.405000 9.945000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.640000 1.785000 0.810000 1.955000 ; - RECT 1.050000 0.765000 1.220000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.765000 4.915000 0.935000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 1.785000 5.375000 1.955000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.620000 1.785000 6.790000 1.955000 ; - RECT 6.630000 0.765000 6.800000 0.935000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - LAYER met1 ; - RECT 0.580000 1.755000 0.870000 1.800000 ; - RECT 0.580000 1.800000 6.850000 1.940000 ; - RECT 0.580000 1.940000 0.870000 1.985000 ; - RECT 0.990000 0.735000 1.280000 0.780000 ; - RECT 0.990000 0.780000 6.860000 0.920000 ; - RECT 0.990000 0.920000 1.280000 0.965000 ; - RECT 4.685000 0.735000 4.975000 0.780000 ; - RECT 4.685000 0.920000 4.975000 0.965000 ; - RECT 5.145000 1.755000 5.435000 1.800000 ; - RECT 5.145000 1.940000 5.435000 1.985000 ; - RECT 6.560000 1.755000 6.850000 1.800000 ; - RECT 6.560000 1.940000 6.850000 1.985000 ; - RECT 6.570000 0.735000 6.860000 0.780000 ; - RECT 6.570000 0.920000 6.860000 0.965000 ; - END -END sky130_fd_sc_hd__sdfxtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdfxtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdfxtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 11.04000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.460000 1.355000 2.795000 1.685000 ; - END - END D - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 9.285000 0.305000 9.615000 0.735000 ; - RECT 9.285000 0.735000 10.955000 0.905000 ; - RECT 9.285000 1.505000 10.955000 1.675000 ; - RECT 9.285000 1.675000 9.615000 2.395000 ; - RECT 10.135000 0.305000 10.465000 0.735000 ; - RECT 10.135000 1.675000 10.465000 2.395000 ; - RECT 10.655000 0.905000 10.955000 1.505000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.535000 1.035000 4.025000 1.655000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.780000 0.615000 3.255000 0.785000 ; - RECT 1.780000 0.785000 1.950000 1.685000 ; - RECT 2.475000 0.305000 2.650000 0.615000 ; - RECT 3.085000 0.785000 3.255000 1.115000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 11.040000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 11.230000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 11.040000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 11.040000 0.085000 ; - RECT 0.000000 2.635000 11.040000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.810000 0.805000 ; - RECT 0.180000 1.795000 0.845000 1.965000 ; - RECT 0.180000 1.965000 0.350000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.520000 2.135000 0.850000 2.635000 ; - RECT 0.615000 0.805000 0.810000 0.970000 ; - RECT 0.615000 0.970000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.245000 0.715000 ; - RECT 1.020000 0.715000 1.245000 2.465000 ; - RECT 1.435000 0.275000 1.805000 0.445000 ; - RECT 1.435000 0.445000 1.605000 1.860000 ; - RECT 1.435000 1.860000 3.250000 2.075000 ; - RECT 1.435000 2.075000 1.710000 2.445000 ; - RECT 1.880000 2.245000 2.210000 2.635000 ; - RECT 1.975000 0.085000 2.305000 0.445000 ; - RECT 2.120000 0.955000 2.465000 1.125000 ; - RECT 2.120000 1.125000 2.290000 1.860000 ; - RECT 2.695000 2.245000 3.590000 2.415000 ; - RECT 2.820000 0.275000 3.595000 0.445000 ; - RECT 3.080000 1.355000 3.275000 1.685000 ; - RECT 3.080000 1.685000 3.250000 1.860000 ; - RECT 3.420000 1.825000 4.385000 1.995000 ; - RECT 3.420000 1.995000 3.590000 2.245000 ; - RECT 3.425000 0.445000 3.595000 0.695000 ; - RECT 3.425000 0.695000 4.385000 0.865000 ; - RECT 3.760000 2.165000 3.930000 2.635000 ; - RECT 3.765000 0.085000 3.965000 0.525000 ; - RECT 4.215000 0.365000 4.565000 0.535000 ; - RECT 4.215000 0.535000 4.385000 0.695000 ; - RECT 4.215000 0.865000 4.385000 1.825000 ; - RECT 4.215000 1.995000 4.385000 2.065000 ; - RECT 4.215000 2.065000 4.450000 2.440000 ; - RECT 4.555000 0.705000 5.135000 1.035000 ; - RECT 4.555000 1.035000 4.795000 1.905000 ; - RECT 4.695000 2.190000 5.765000 2.360000 ; - RECT 4.735000 0.365000 5.475000 0.535000 ; - RECT 4.985000 1.655000 5.425000 2.010000 ; - RECT 5.305000 0.535000 5.475000 1.315000 ; - RECT 5.305000 1.315000 6.105000 1.485000 ; - RECT 5.595000 1.485000 6.105000 1.575000 ; - RECT 5.595000 1.575000 5.765000 2.190000 ; - RECT 5.645000 0.765000 6.445000 1.065000 ; - RECT 5.645000 1.065000 5.815000 1.095000 ; - RECT 5.725000 0.085000 6.095000 0.585000 ; - RECT 5.935000 1.245000 6.105000 1.315000 ; - RECT 5.935000 1.835000 6.105000 2.635000 ; - RECT 6.275000 0.365000 6.735000 0.535000 ; - RECT 6.275000 0.535000 6.445000 0.765000 ; - RECT 6.275000 1.065000 6.445000 2.135000 ; - RECT 6.275000 2.135000 6.525000 2.465000 ; - RECT 6.615000 0.705000 7.165000 1.035000 ; - RECT 6.615000 1.245000 6.805000 1.965000 ; - RECT 6.750000 2.165000 7.635000 2.335000 ; - RECT 6.965000 0.365000 7.505000 0.535000 ; - RECT 6.975000 1.035000 7.165000 1.575000 ; - RECT 6.975000 1.575000 7.295000 1.905000 ; - RECT 7.335000 0.535000 7.505000 0.995000 ; - RECT 7.335000 0.995000 8.400000 1.325000 ; - RECT 7.335000 1.325000 7.635000 1.405000 ; - RECT 7.465000 1.405000 7.635000 2.165000 ; - RECT 7.750000 0.085000 8.120000 0.615000 ; - RECT 7.805000 1.575000 8.755000 1.905000 ; - RECT 7.815000 2.135000 8.120000 2.635000 ; - RECT 8.390000 0.300000 8.750000 0.825000 ; - RECT 8.470000 1.905000 8.755000 2.455000 ; - RECT 8.570000 0.825000 8.750000 1.075000 ; - RECT 8.570000 1.075000 10.485000 1.325000 ; - RECT 8.570000 1.325000 8.755000 1.575000 ; - RECT 8.925000 0.085000 9.095000 0.695000 ; - RECT 8.925000 1.625000 9.105000 2.635000 ; - RECT 9.795000 0.085000 9.965000 0.565000 ; - RECT 9.795000 1.845000 9.965000 2.635000 ; - RECT 10.635000 0.085000 10.805000 0.565000 ; - RECT 10.635000 1.845000 10.805000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.615000 1.785000 0.785000 1.955000 ; - RECT 1.055000 0.765000 1.225000 0.935000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 4.755000 0.765000 4.925000 0.935000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.215000 1.785000 5.385000 1.955000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 6.625000 0.765000 6.795000 0.935000 ; - RECT 6.625000 1.785000 6.795000 1.955000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - LAYER met1 ; - RECT 0.555000 1.755000 0.845000 1.800000 ; - RECT 0.555000 1.800000 6.855000 1.940000 ; - RECT 0.555000 1.940000 0.845000 1.985000 ; - RECT 0.995000 0.735000 1.285000 0.780000 ; - RECT 0.995000 0.780000 6.855000 0.920000 ; - RECT 0.995000 0.920000 1.285000 0.965000 ; - RECT 4.695000 0.735000 4.985000 0.780000 ; - RECT 4.695000 0.920000 4.985000 0.965000 ; - RECT 5.155000 1.755000 5.445000 1.800000 ; - RECT 5.155000 1.940000 5.445000 1.985000 ; - RECT 6.565000 0.735000 6.855000 0.780000 ; - RECT 6.565000 0.920000 6.855000 0.965000 ; - RECT 6.565000 1.755000 6.855000 1.800000 ; - RECT 6.565000 1.940000 6.855000 1.985000 ; - END -END sky130_fd_sc_hd__sdfxtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdlclkp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdlclkp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 6.900000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.850000 0.955000 1.190000 1.325000 ; - RECT 0.880000 1.325000 1.190000 1.445000 ; - RECT 0.880000 1.445000 1.235000 1.955000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.530000 0.255000 6.815000 0.825000 ; - RECT 6.530000 1.495000 6.815000 2.465000 ; - RECT 6.645000 0.825000 6.815000 1.495000 ; - END - END GCLK - PIN SCE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.955000 0.340000 1.665000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 4.710000 0.955000 6.010000 1.265000 ; - RECT 4.710000 1.265000 4.930000 1.325000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 6.900000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.090000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 6.900000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 6.900000 0.085000 ; - RECT 0.000000 2.635000 6.900000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.615000 ; - RECT 0.085000 0.615000 1.190000 0.785000 ; - RECT 0.085000 1.835000 0.345000 2.635000 ; - RECT 0.510000 0.785000 0.680000 1.460000 ; - RECT 0.510000 1.460000 0.710000 1.755000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.540000 1.755000 0.710000 2.125000 ; - RECT 0.540000 2.125000 1.255000 2.465000 ; - RECT 1.015000 0.255000 1.190000 0.615000 ; - RECT 1.360000 0.255000 2.495000 0.535000 ; - RECT 1.360000 0.705000 1.700000 1.205000 ; - RECT 1.360000 1.205000 1.860000 1.325000 ; - RECT 1.405000 1.325000 1.860000 1.955000 ; - RECT 1.425000 2.125000 2.200000 2.465000 ; - RECT 1.870000 0.705000 2.155000 1.035000 ; - RECT 2.030000 1.205000 3.010000 1.375000 ; - RECT 2.030000 1.375000 2.200000 2.125000 ; - RECT 2.325000 0.535000 2.495000 0.995000 ; - RECT 2.325000 0.995000 3.010000 1.205000 ; - RECT 2.370000 1.575000 2.540000 1.635000 ; - RECT 2.370000 1.635000 3.400000 1.905000 ; - RECT 2.370000 2.075000 3.010000 2.635000 ; - RECT 2.665000 0.085000 3.010000 0.825000 ; - RECT 3.180000 0.255000 3.400000 1.635000 ; - RECT 3.180000 1.905000 3.400000 1.915000 ; - RECT 3.180000 1.915000 5.450000 2.085000 ; - RECT 3.180000 2.085000 3.400000 2.465000 ; - RECT 3.580000 0.255000 3.910000 0.765000 ; - RECT 3.580000 0.765000 4.005000 0.935000 ; - RECT 3.580000 0.935000 3.750000 1.575000 ; - RECT 3.580000 1.575000 3.990000 1.745000 ; - RECT 3.580000 2.255000 5.490000 2.635000 ; - RECT 3.920000 1.105000 4.465000 1.275000 ; - RECT 4.080000 0.085000 4.410000 0.445000 ; - RECT 4.160000 1.275000 4.465000 1.495000 ; - RECT 4.160000 1.495000 4.960000 1.745000 ; - RECT 4.175000 0.615000 4.830000 0.785000 ; - RECT 4.175000 0.785000 4.465000 1.105000 ; - RECT 4.580000 0.255000 4.830000 0.615000 ; - RECT 5.010000 0.255000 5.270000 0.615000 ; - RECT 5.010000 0.615000 6.360000 0.785000 ; - RECT 5.140000 1.435000 5.610000 1.605000 ; - RECT 5.140000 1.605000 5.450000 1.915000 ; - RECT 5.505000 0.085000 6.360000 0.445000 ; - RECT 5.660000 1.775000 6.360000 2.085000 ; - RECT 5.660000 2.085000 5.830000 2.465000 ; - RECT 5.780000 1.435000 6.360000 1.775000 ; - RECT 6.030000 2.255000 6.360000 2.635000 ; - RECT 6.190000 0.785000 6.360000 0.995000 ; - RECT 6.190000 0.995000 6.460000 1.325000 ; - RECT 6.190000 1.325000 6.360000 1.435000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 1.445000 1.695000 1.615000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 0.765000 2.155000 0.935000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 3.835000 0.765000 4.005000 0.935000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.295000 1.445000 4.465000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - LAYER met1 ; - RECT 1.465000 1.415000 1.755000 1.460000 ; - RECT 1.465000 1.460000 4.525000 1.600000 ; - RECT 1.465000 1.600000 1.755000 1.645000 ; - RECT 1.925000 0.735000 2.215000 0.780000 ; - RECT 1.925000 0.780000 4.065000 0.920000 ; - RECT 1.925000 0.920000 2.215000 0.965000 ; - RECT 3.775000 0.735000 4.065000 0.780000 ; - RECT 3.775000 0.920000 4.065000 0.965000 ; - RECT 4.235000 1.415000 4.525000 1.460000 ; - RECT 4.235000 1.600000 4.525000 1.645000 ; - END -END sky130_fd_sc_hd__sdlclkp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdlclkp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdlclkp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 7.360000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.855000 0.955000 1.195000 1.445000 ; - RECT 0.855000 1.445000 1.240000 1.955000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.570000 0.255000 6.840000 0.825000 ; - RECT 6.570000 1.495000 6.840000 2.465000 ; - RECT 6.670000 0.825000 6.840000 1.055000 ; - RECT 6.670000 1.055000 7.275000 1.315000 ; - RECT 6.670000 1.315000 6.840000 1.495000 ; - END - END GCLK - PIN SCE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.955000 0.340000 1.665000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 4.705000 0.955000 6.050000 1.265000 ; - RECT 4.705000 1.265000 4.925000 1.325000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 7.360000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 7.550000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 7.360000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 7.360000 0.085000 ; - RECT 0.000000 2.635000 7.360000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.615000 ; - RECT 0.085000 0.615000 1.195000 0.785000 ; - RECT 0.085000 1.835000 0.345000 2.635000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.515000 0.785000 0.685000 2.125000 ; - RECT 0.515000 2.125000 1.260000 2.465000 ; - RECT 1.015000 0.255000 1.195000 0.615000 ; - RECT 1.365000 0.255000 2.500000 0.535000 ; - RECT 1.365000 0.705000 1.705000 1.205000 ; - RECT 1.365000 1.205000 1.865000 1.325000 ; - RECT 1.410000 1.325000 1.865000 1.955000 ; - RECT 1.430000 2.125000 2.205000 2.465000 ; - RECT 1.875000 0.705000 2.160000 1.035000 ; - RECT 2.035000 1.205000 3.015000 1.375000 ; - RECT 2.035000 1.375000 2.205000 2.125000 ; - RECT 2.330000 0.535000 2.500000 0.995000 ; - RECT 2.330000 0.995000 3.015000 1.205000 ; - RECT 2.375000 1.575000 2.545000 1.635000 ; - RECT 2.375000 1.635000 3.405000 1.905000 ; - RECT 2.375000 2.075000 3.015000 2.635000 ; - RECT 2.670000 0.085000 3.015000 0.825000 ; - RECT 3.185000 0.255000 3.405000 1.635000 ; - RECT 3.185000 1.905000 3.405000 1.915000 ; - RECT 3.185000 1.915000 5.490000 2.085000 ; - RECT 3.185000 2.085000 3.405000 2.465000 ; - RECT 3.575000 0.255000 3.925000 0.765000 ; - RECT 3.575000 0.765000 4.000000 0.935000 ; - RECT 3.575000 0.935000 3.745000 1.575000 ; - RECT 3.575000 1.575000 4.040000 1.745000 ; - RECT 3.575000 2.255000 5.530000 2.635000 ; - RECT 3.915000 1.105000 4.460000 1.275000 ; - RECT 4.095000 0.085000 4.425000 0.445000 ; - RECT 4.170000 0.615000 4.825000 0.785000 ; - RECT 4.170000 0.785000 4.460000 1.105000 ; - RECT 4.210000 1.275000 4.460000 1.495000 ; - RECT 4.210000 1.495000 5.010000 1.745000 ; - RECT 4.595000 0.255000 4.825000 0.615000 ; - RECT 5.100000 0.255000 5.310000 0.615000 ; - RECT 5.100000 0.615000 6.400000 0.785000 ; - RECT 5.180000 1.435000 5.650000 1.605000 ; - RECT 5.180000 1.605000 5.490000 1.915000 ; - RECT 5.490000 0.085000 6.400000 0.445000 ; - RECT 5.700000 1.775000 6.400000 2.085000 ; - RECT 5.700000 2.085000 5.870000 2.465000 ; - RECT 5.820000 1.435000 6.400000 1.775000 ; - RECT 6.070000 2.255000 6.400000 2.635000 ; - RECT 6.230000 0.785000 6.400000 0.995000 ; - RECT 6.230000 0.995000 6.500000 1.325000 ; - RECT 6.230000 1.325000 6.400000 1.435000 ; - RECT 7.010000 0.085000 7.275000 0.885000 ; - RECT 7.010000 1.485000 7.275000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 1.445000 1.700000 1.615000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 1.990000 0.765000 2.160000 0.935000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 3.830000 0.765000 4.000000 0.935000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.290000 1.445000 4.460000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - LAYER met1 ; - RECT 1.470000 1.415000 1.760000 1.460000 ; - RECT 1.470000 1.460000 4.520000 1.600000 ; - RECT 1.470000 1.600000 1.760000 1.645000 ; - RECT 1.930000 0.735000 2.220000 0.780000 ; - RECT 1.930000 0.780000 4.060000 0.920000 ; - RECT 1.930000 0.920000 2.220000 0.965000 ; - RECT 3.770000 0.735000 4.060000 0.780000 ; - RECT 3.770000 0.920000 4.060000 0.965000 ; - RECT 4.230000 1.415000 4.520000 1.460000 ; - RECT 4.230000 1.600000 4.520000 1.645000 ; - END -END sky130_fd_sc_hd__sdlclkp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sdlclkp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sdlclkp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN GATE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.855000 0.955000 1.195000 1.445000 ; - RECT 0.855000 1.445000 1.240000 1.955000 ; - END - END GATE - PIN GCLK - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.500000 0.255000 6.830000 0.445000 ; - RECT 6.580000 0.445000 6.830000 0.715000 ; - RECT 6.580000 0.715000 7.220000 0.885000 ; - RECT 6.580000 1.485000 7.220000 1.655000 ; - RECT 6.580000 1.655000 6.830000 2.465000 ; - RECT 7.050000 0.885000 7.220000 1.055000 ; - RECT 7.050000 1.055000 8.195000 1.315000 ; - RECT 7.050000 1.315000 7.220000 1.485000 ; - RECT 7.420000 0.255000 7.720000 1.055000 ; - RECT 7.420000 1.315000 7.720000 2.465000 ; - END - END GCLK - PIN SCE - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.955000 0.345000 1.665000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.406500 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 4.725000 0.995000 4.945000 1.325000 ; - LAYER mcon ; - RECT 4.770000 1.105000 4.940000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 5.685000 0.995000 6.065000 1.325000 ; - LAYER mcon ; - RECT 5.710000 1.105000 5.880000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 4.710000 1.075000 5.000000 1.120000 ; - RECT 4.710000 1.120000 5.940000 1.260000 ; - RECT 4.710000 1.260000 5.000000 1.305000 ; - RECT 5.650000 1.075000 5.940000 1.120000 ; - RECT 5.650000 1.260000 5.940000 1.305000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.085000 0.255000 0.345000 0.615000 ; - RECT 0.085000 0.615000 1.195000 0.785000 ; - RECT 0.085000 1.835000 0.345000 2.635000 ; - RECT 0.515000 0.085000 0.845000 0.445000 ; - RECT 0.515000 0.785000 0.685000 2.125000 ; - RECT 0.515000 2.125000 1.260000 2.465000 ; - RECT 1.015000 0.255000 1.195000 0.615000 ; - RECT 1.365000 0.255000 2.500000 0.535000 ; - RECT 1.365000 0.705000 1.705000 1.205000 ; - RECT 1.365000 1.205000 1.865000 1.325000 ; - RECT 1.410000 1.325000 1.865000 1.955000 ; - RECT 1.430000 2.125000 2.205000 2.465000 ; - RECT 1.875000 0.705000 2.160000 1.035000 ; - RECT 2.035000 1.205000 3.015000 1.375000 ; - RECT 2.035000 1.375000 2.205000 2.125000 ; - RECT 2.330000 0.535000 2.500000 0.995000 ; - RECT 2.330000 0.995000 3.015000 1.205000 ; - RECT 2.375000 1.575000 2.545000 1.635000 ; - RECT 2.375000 1.635000 3.405000 1.905000 ; - RECT 2.375000 2.075000 3.015000 2.635000 ; - RECT 2.670000 0.085000 3.015000 0.825000 ; - RECT 3.185000 0.255000 3.405000 1.635000 ; - RECT 3.185000 1.905000 3.405000 1.915000 ; - RECT 3.185000 1.915000 5.515000 2.085000 ; - RECT 3.185000 2.085000 3.405000 2.465000 ; - RECT 3.595000 0.255000 3.925000 0.765000 ; - RECT 3.595000 0.765000 4.020000 0.935000 ; - RECT 3.595000 0.935000 3.765000 1.575000 ; - RECT 3.595000 1.575000 4.005000 1.745000 ; - RECT 3.595000 2.255000 5.515000 2.635000 ; - RECT 3.935000 1.105000 4.480000 1.275000 ; - RECT 4.095000 0.085000 4.425000 0.445000 ; - RECT 4.175000 1.275000 4.480000 1.495000 ; - RECT 4.175000 1.495000 4.975000 1.745000 ; - RECT 4.190000 0.615000 4.845000 0.785000 ; - RECT 4.190000 0.785000 4.480000 1.105000 ; - RECT 4.595000 0.255000 4.845000 0.615000 ; - RECT 5.015000 0.255000 5.435000 0.615000 ; - RECT 5.015000 0.615000 6.410000 0.785000 ; - RECT 5.165000 0.995000 5.515000 1.915000 ; - RECT 5.605000 0.085000 6.330000 0.445000 ; - RECT 5.685000 1.495000 6.410000 2.085000 ; - RECT 5.685000 2.085000 5.855000 2.465000 ; - RECT 6.055000 2.255000 6.385000 2.635000 ; - RECT 6.240000 0.785000 6.410000 1.055000 ; - RECT 6.240000 1.055000 6.880000 1.315000 ; - RECT 6.240000 1.315000 6.410000 1.495000 ; - RECT 7.000000 0.085000 7.250000 0.545000 ; - RECT 7.000000 1.825000 7.250000 2.635000 ; - RECT 7.890000 0.085000 8.195000 0.885000 ; - RECT 7.890000 1.485000 8.195000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.530000 1.445000 1.700000 1.615000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 1.990000 0.765000 2.160000 0.935000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 3.850000 0.765000 4.020000 0.935000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.310000 1.445000 4.480000 1.615000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 1.470000 1.415000 1.760000 1.460000 ; - RECT 1.470000 1.460000 4.540000 1.600000 ; - RECT 1.470000 1.600000 1.760000 1.645000 ; - RECT 1.930000 0.735000 2.220000 0.780000 ; - RECT 1.930000 0.780000 4.080000 0.920000 ; - RECT 1.930000 0.920000 2.220000 0.965000 ; - RECT 3.790000 0.735000 4.080000 0.780000 ; - RECT 3.790000 0.920000 4.080000 0.965000 ; - RECT 4.250000 1.415000 4.540000 1.460000 ; - RECT 4.250000 1.600000 4.540000 1.645000 ; - END -END sky130_fd_sc_hd__sdlclkp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sedfxbp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sedfxbp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.26000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 13.525000 0.255000 13.855000 2.420000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.429000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.700000 1.065000 12.145000 1.410000 ; - RECT 11.700000 1.410000 12.030000 2.465000 ; - RECT 11.815000 0.255000 12.145000 1.065000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.760000 1.105000 6.215000 1.665000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.025000 1.105000 5.250000 1.615000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.260000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.885000 1.435000 ; - RECT -0.190000 1.435000 14.450000 2.910000 ; - RECT 7.200000 1.305000 14.450000 1.435000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.260000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.260000 0.085000 ; - RECT 0.000000 2.635000 14.260000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.595000 0.255000 4.795000 0.645000 ; - RECT 4.595000 0.645000 4.855000 0.825000 ; - RECT 4.635000 2.210000 4.965000 2.465000 ; - RECT 4.685000 0.825000 4.855000 1.785000 ; - RECT 4.685000 1.785000 4.965000 2.210000 ; - RECT 4.965000 0.255000 5.590000 0.515000 ; - RECT 5.155000 1.835000 6.585000 2.005000 ; - RECT 5.155000 2.005000 5.495000 2.465000 ; - RECT 5.260000 0.515000 5.590000 0.935000 ; - RECT 5.420000 0.935000 5.590000 1.835000 ; - RECT 5.665000 2.175000 6.010000 2.635000 ; - RECT 5.760000 0.085000 6.010000 0.905000 ; - RECT 6.385000 1.355000 6.585000 1.835000 ; - RECT 6.515000 0.255000 7.135000 0.565000 ; - RECT 6.515000 0.565000 6.925000 1.185000 ; - RECT 6.675000 2.150000 7.005000 2.465000 ; - RECT 6.755000 1.185000 6.925000 1.865000 ; - RECT 6.755000 1.865000 7.005000 2.150000 ; - RECT 7.095000 1.125000 7.280000 1.720000 ; - RECT 7.115000 0.735000 7.620000 0.955000 ; - RECT 7.215000 2.175000 8.255000 2.375000 ; - RECT 7.305000 0.255000 7.980000 0.565000 ; - RECT 7.450000 0.955000 7.620000 1.655000 ; - RECT 7.450000 1.655000 7.915000 2.005000 ; - RECT 7.810000 0.565000 7.980000 1.315000 ; - RECT 7.810000 1.315000 8.660000 1.485000 ; - RECT 8.085000 1.485000 8.660000 1.575000 ; - RECT 8.085000 1.575000 8.255000 2.175000 ; - RECT 8.170000 0.765000 9.235000 1.045000 ; - RECT 8.170000 1.045000 9.745000 1.065000 ; - RECT 8.170000 1.065000 8.370000 1.095000 ; - RECT 8.245000 0.085000 8.640000 0.560000 ; - RECT 8.425000 1.835000 8.660000 2.635000 ; - RECT 8.490000 1.245000 8.660000 1.315000 ; - RECT 8.830000 0.255000 9.235000 0.765000 ; - RECT 8.830000 1.065000 9.745000 1.375000 ; - RECT 8.830000 1.375000 9.160000 2.465000 ; - RECT 9.370000 2.105000 9.660000 2.635000 ; - RECT 9.465000 0.085000 9.740000 0.615000 ; - RECT 10.090000 1.245000 10.280000 1.965000 ; - RECT 10.225000 2.165000 11.190000 2.355000 ; - RECT 10.305000 0.705000 10.770000 1.035000 ; - RECT 10.325000 0.330000 11.190000 0.535000 ; - RECT 10.450000 1.035000 10.770000 1.995000 ; - RECT 10.940000 0.535000 11.190000 2.165000 ; - RECT 11.360000 1.495000 11.530000 2.635000 ; - RECT 11.395000 0.085000 11.645000 0.900000 ; - RECT 12.200000 1.575000 12.430000 2.010000 ; - RECT 12.315000 0.890000 12.940000 1.220000 ; - RECT 12.600000 0.255000 12.940000 0.890000 ; - RECT 12.600000 1.220000 12.940000 2.465000 ; - RECT 13.110000 0.085000 13.355000 0.900000 ; - RECT 13.110000 1.465000 13.355000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.615000 0.425000 4.785000 0.595000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.530000 0.425000 6.700000 0.595000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.100000 1.445000 7.270000 1.615000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 1.785000 7.680000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.100000 1.785000 10.270000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.445000 10.690000 1.615000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 10.980000 1.785000 11.150000 1.955000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.230000 1.785000 12.400000 1.955000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 12.690000 0.765000 12.860000 0.935000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 10.330000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 10.750000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 12.920000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.555000 0.395000 6.760000 0.580000 ; - RECT 4.555000 0.580000 4.845000 0.625000 ; - RECT 6.470000 0.580000 6.760000 0.625000 ; - RECT 7.040000 1.415000 7.330000 1.460000 ; - RECT 7.040000 1.600000 7.330000 1.645000 ; - RECT 7.450000 1.755000 7.740000 1.800000 ; - RECT 7.450000 1.940000 7.740000 1.985000 ; - RECT 10.040000 1.755000 10.330000 1.800000 ; - RECT 10.040000 1.940000 10.330000 1.985000 ; - RECT 10.460000 1.415000 10.750000 1.460000 ; - RECT 10.460000 1.600000 10.750000 1.645000 ; - RECT 10.920000 1.755000 11.210000 1.800000 ; - RECT 10.920000 1.800000 12.460000 1.940000 ; - RECT 10.920000 1.940000 11.210000 1.985000 ; - RECT 12.170000 1.755000 12.460000 1.800000 ; - RECT 12.170000 1.940000 12.460000 1.985000 ; - RECT 12.630000 0.735000 12.920000 0.780000 ; - RECT 12.630000 0.920000 12.920000 0.965000 ; - END -END sky130_fd_sc_hd__sedfxbp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sedfxbp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sedfxbp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 15.18000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 13.935000 0.255000 14.265000 2.420000 ; - END - END Q - PIN Q_N - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 11.700000 1.065000 12.145000 1.300000 ; - RECT 11.700000 1.300000 12.030000 2.465000 ; - RECT 11.815000 0.255000 12.145000 1.065000 ; - END - END Q_N - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.760000 1.105000 6.215000 1.665000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.025000 1.105000 5.250000 1.615000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 15.180000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.885000 1.435000 ; - RECT -0.190000 1.435000 15.370000 2.910000 ; - RECT 7.200000 1.305000 15.370000 1.435000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 15.180000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 15.180000 0.085000 ; - RECT 0.000000 2.635000 15.180000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.595000 0.255000 4.795000 0.645000 ; - RECT 4.595000 0.645000 4.855000 0.825000 ; - RECT 4.635000 2.210000 4.965000 2.465000 ; - RECT 4.685000 0.825000 4.855000 1.785000 ; - RECT 4.685000 1.785000 4.965000 2.210000 ; - RECT 4.965000 0.255000 5.590000 0.515000 ; - RECT 5.155000 1.835000 6.585000 2.005000 ; - RECT 5.155000 2.005000 5.495000 2.465000 ; - RECT 5.260000 0.515000 5.590000 0.935000 ; - RECT 5.420000 0.935000 5.590000 1.835000 ; - RECT 5.665000 2.175000 6.010000 2.635000 ; - RECT 5.760000 0.085000 6.010000 0.905000 ; - RECT 6.385000 1.355000 6.585000 1.835000 ; - RECT 6.515000 0.255000 7.135000 0.565000 ; - RECT 6.515000 0.565000 6.925000 1.185000 ; - RECT 6.675000 2.150000 7.005000 2.465000 ; - RECT 6.755000 1.185000 6.925000 1.865000 ; - RECT 6.755000 1.865000 7.005000 2.150000 ; - RECT 7.095000 1.125000 7.280000 1.720000 ; - RECT 7.115000 0.735000 7.620000 0.955000 ; - RECT 7.215000 2.175000 8.255000 2.375000 ; - RECT 7.305000 0.255000 7.980000 0.565000 ; - RECT 7.450000 0.955000 7.620000 1.655000 ; - RECT 7.450000 1.655000 7.915000 2.005000 ; - RECT 7.810000 0.565000 7.980000 1.315000 ; - RECT 7.810000 1.315000 8.660000 1.485000 ; - RECT 8.085000 1.485000 8.660000 1.575000 ; - RECT 8.085000 1.575000 8.255000 2.175000 ; - RECT 8.170000 0.765000 9.235000 1.045000 ; - RECT 8.170000 1.045000 9.745000 1.065000 ; - RECT 8.170000 1.065000 8.370000 1.095000 ; - RECT 8.245000 0.085000 8.640000 0.560000 ; - RECT 8.425000 1.835000 8.660000 2.635000 ; - RECT 8.490000 1.245000 8.660000 1.315000 ; - RECT 8.830000 0.255000 9.235000 0.765000 ; - RECT 8.830000 1.065000 9.745000 1.375000 ; - RECT 8.830000 1.375000 9.160000 2.465000 ; - RECT 9.370000 2.105000 9.660000 2.635000 ; - RECT 9.465000 0.085000 9.740000 0.615000 ; - RECT 10.090000 1.245000 10.280000 1.965000 ; - RECT 10.225000 2.165000 11.190000 2.355000 ; - RECT 10.305000 0.705000 10.770000 1.035000 ; - RECT 10.325000 0.330000 11.190000 0.535000 ; - RECT 10.450000 1.035000 10.770000 1.995000 ; - RECT 10.940000 0.535000 11.190000 2.165000 ; - RECT 11.360000 1.495000 11.530000 2.635000 ; - RECT 11.395000 0.085000 11.645000 0.900000 ; - RECT 12.200000 1.465000 12.450000 2.635000 ; - RECT 12.315000 0.085000 12.565000 0.900000 ; - RECT 12.620000 1.575000 12.850000 2.010000 ; - RECT 12.735000 0.890000 13.360000 1.220000 ; - RECT 13.020000 0.255000 13.360000 0.890000 ; - RECT 13.020000 1.220000 13.360000 2.465000 ; - RECT 13.530000 0.085000 13.765000 0.900000 ; - RECT 13.530000 1.465000 13.765000 2.635000 ; - RECT 14.435000 0.085000 14.695000 0.900000 ; - RECT 14.435000 1.465000 14.695000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.615000 0.425000 4.785000 0.595000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.530000 0.425000 6.700000 0.595000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.100000 1.445000 7.270000 1.615000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 1.785000 7.680000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.100000 1.785000 10.270000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.445000 10.690000 1.615000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 10.980000 1.785000 11.150000 1.955000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 12.650000 1.785000 12.820000 1.955000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.110000 0.765000 13.280000 0.935000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - RECT 14.405000 -0.085000 14.575000 0.085000 ; - RECT 14.405000 2.635000 14.575000 2.805000 ; - RECT 14.865000 -0.085000 15.035000 0.085000 ; - RECT 14.865000 2.635000 15.035000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 10.330000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 10.750000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 13.340000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.555000 0.395000 6.760000 0.580000 ; - RECT 4.555000 0.580000 4.845000 0.625000 ; - RECT 6.470000 0.580000 6.760000 0.625000 ; - RECT 7.040000 1.415000 7.330000 1.460000 ; - RECT 7.040000 1.600000 7.330000 1.645000 ; - RECT 7.450000 1.755000 7.740000 1.800000 ; - RECT 7.450000 1.940000 7.740000 1.985000 ; - RECT 10.040000 1.755000 10.330000 1.800000 ; - RECT 10.040000 1.940000 10.330000 1.985000 ; - RECT 10.460000 1.415000 10.750000 1.460000 ; - RECT 10.460000 1.600000 10.750000 1.645000 ; - RECT 10.920000 1.755000 11.210000 1.800000 ; - RECT 10.920000 1.800000 12.880000 1.940000 ; - RECT 10.920000 1.940000 11.210000 1.985000 ; - RECT 12.590000 1.755000 12.880000 1.800000 ; - RECT 12.590000 1.940000 12.880000 1.985000 ; - RECT 13.050000 0.735000 13.340000 0.780000 ; - RECT 13.050000 0.920000 13.340000 0.965000 ; - END -END sky130_fd_sc_hd__sedfxbp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sedfxtp_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sedfxtp_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.34000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.462000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.765000 0.305000 13.095000 2.420000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.760000 1.105000 6.215000 1.665000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.025000 1.105000 5.250000 1.615000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.340000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.885000 1.435000 ; - RECT -0.190000 1.435000 13.530000 2.910000 ; - RECT 7.200000 1.305000 13.530000 1.435000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.340000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 13.340000 0.085000 ; - RECT 0.000000 2.635000 13.340000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.595000 0.255000 4.795000 0.645000 ; - RECT 4.595000 0.645000 4.855000 0.825000 ; - RECT 4.635000 2.210000 4.965000 2.465000 ; - RECT 4.685000 0.825000 4.855000 1.785000 ; - RECT 4.685000 1.785000 4.965000 2.210000 ; - RECT 4.965000 0.255000 5.590000 0.515000 ; - RECT 5.155000 1.835000 6.585000 2.005000 ; - RECT 5.155000 2.005000 5.495000 2.465000 ; - RECT 5.260000 0.515000 5.590000 0.935000 ; - RECT 5.420000 0.935000 5.590000 1.835000 ; - RECT 5.665000 2.175000 6.010000 2.635000 ; - RECT 5.760000 0.085000 6.010000 0.905000 ; - RECT 6.385000 1.355000 6.585000 1.835000 ; - RECT 6.515000 0.255000 7.135000 0.565000 ; - RECT 6.515000 0.565000 6.925000 1.185000 ; - RECT 6.675000 2.150000 7.005000 2.465000 ; - RECT 6.755000 1.185000 6.925000 1.865000 ; - RECT 6.755000 1.865000 7.005000 2.150000 ; - RECT 7.095000 1.125000 7.280000 1.720000 ; - RECT 7.115000 0.735000 7.620000 0.955000 ; - RECT 7.215000 2.175000 8.255000 2.375000 ; - RECT 7.305000 0.255000 7.980000 0.565000 ; - RECT 7.450000 0.955000 7.620000 1.655000 ; - RECT 7.450000 1.655000 7.915000 2.005000 ; - RECT 7.810000 0.565000 7.980000 1.315000 ; - RECT 7.810000 1.315000 8.660000 1.485000 ; - RECT 8.085000 1.485000 8.660000 1.575000 ; - RECT 8.085000 1.575000 8.255000 2.175000 ; - RECT 8.170000 0.765000 9.235000 1.045000 ; - RECT 8.170000 1.045000 9.745000 1.065000 ; - RECT 8.170000 1.065000 8.370000 1.095000 ; - RECT 8.245000 0.085000 8.640000 0.560000 ; - RECT 8.425000 1.835000 8.660000 2.635000 ; - RECT 8.490000 1.245000 8.660000 1.315000 ; - RECT 8.830000 0.255000 9.235000 0.765000 ; - RECT 8.830000 1.065000 9.745000 1.375000 ; - RECT 8.830000 1.375000 9.160000 2.465000 ; - RECT 9.370000 2.105000 9.660000 2.635000 ; - RECT 9.465000 0.085000 9.740000 0.615000 ; - RECT 10.090000 1.245000 10.280000 1.965000 ; - RECT 10.225000 2.165000 11.110000 2.355000 ; - RECT 10.305000 0.705000 10.770000 1.035000 ; - RECT 10.325000 0.330000 11.110000 0.535000 ; - RECT 10.450000 1.035000 10.770000 1.995000 ; - RECT 10.940000 0.535000 11.110000 0.995000 ; - RECT 10.940000 0.995000 11.810000 1.325000 ; - RECT 10.940000 1.325000 11.110000 2.165000 ; - RECT 11.280000 1.530000 12.180000 1.905000 ; - RECT 11.280000 2.135000 11.540000 2.635000 ; - RECT 11.350000 0.085000 11.665000 0.615000 ; - RECT 11.840000 1.905000 12.180000 2.465000 ; - RECT 11.850000 0.300000 12.180000 0.825000 ; - RECT 11.990000 0.825000 12.180000 1.530000 ; - RECT 12.350000 0.085000 12.595000 0.900000 ; - RECT 12.350000 1.465000 12.595000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.615000 0.425000 4.785000 0.595000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.530000 0.425000 6.700000 0.595000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.100000 1.445000 7.270000 1.615000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 1.785000 7.680000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.100000 1.785000 10.270000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.445000 10.690000 1.615000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.000000 0.765000 12.170000 0.935000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 10.330000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 10.750000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 12.230000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.555000 0.395000 6.760000 0.580000 ; - RECT 4.555000 0.580000 4.845000 0.625000 ; - RECT 6.470000 0.580000 6.760000 0.625000 ; - RECT 7.040000 1.415000 7.330000 1.460000 ; - RECT 7.040000 1.600000 7.330000 1.645000 ; - RECT 7.450000 1.755000 7.740000 1.800000 ; - RECT 7.450000 1.940000 7.740000 1.985000 ; - RECT 10.040000 1.755000 10.330000 1.800000 ; - RECT 10.040000 1.940000 10.330000 1.985000 ; - RECT 10.460000 1.415000 10.750000 1.460000 ; - RECT 10.460000 1.600000 10.750000 1.645000 ; - RECT 11.940000 0.735000 12.230000 0.780000 ; - RECT 11.940000 0.920000 12.230000 0.965000 ; - END -END sky130_fd_sc_hd__sedfxtp_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sedfxtp_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sedfxtp_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 13.80000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.755000 0.305000 13.085000 2.420000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.760000 1.105000 6.215000 1.665000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.025000 1.105000 5.250000 1.615000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 13.800000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.885000 1.435000 ; - RECT -0.190000 1.435000 13.990000 2.910000 ; - RECT 7.200000 1.305000 13.990000 1.435000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 13.800000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 13.800000 0.085000 ; - RECT 0.000000 2.635000 13.800000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.595000 0.255000 4.795000 0.645000 ; - RECT 4.595000 0.645000 4.855000 0.825000 ; - RECT 4.635000 2.210000 4.965000 2.465000 ; - RECT 4.685000 0.825000 4.855000 1.785000 ; - RECT 4.685000 1.785000 4.965000 2.210000 ; - RECT 4.965000 0.255000 5.590000 0.515000 ; - RECT 5.155000 1.835000 6.585000 2.005000 ; - RECT 5.155000 2.005000 5.495000 2.465000 ; - RECT 5.260000 0.515000 5.590000 0.935000 ; - RECT 5.420000 0.935000 5.590000 1.835000 ; - RECT 5.665000 2.175000 6.010000 2.635000 ; - RECT 5.760000 0.085000 6.010000 0.905000 ; - RECT 6.385000 1.355000 6.585000 1.835000 ; - RECT 6.515000 0.255000 7.135000 0.565000 ; - RECT 6.515000 0.565000 6.925000 1.185000 ; - RECT 6.675000 2.150000 7.005000 2.465000 ; - RECT 6.755000 1.185000 6.925000 1.865000 ; - RECT 6.755000 1.865000 7.005000 2.150000 ; - RECT 7.095000 1.125000 7.280000 1.720000 ; - RECT 7.115000 0.735000 7.620000 0.955000 ; - RECT 7.215000 2.175000 8.255000 2.375000 ; - RECT 7.305000 0.255000 7.980000 0.565000 ; - RECT 7.450000 0.955000 7.620000 1.655000 ; - RECT 7.450000 1.655000 7.915000 2.005000 ; - RECT 7.810000 0.565000 7.980000 1.315000 ; - RECT 7.810000 1.315000 8.660000 1.485000 ; - RECT 8.085000 1.485000 8.660000 1.575000 ; - RECT 8.085000 1.575000 8.255000 2.175000 ; - RECT 8.170000 0.765000 9.235000 1.045000 ; - RECT 8.170000 1.045000 9.745000 1.065000 ; - RECT 8.170000 1.065000 8.370000 1.095000 ; - RECT 8.245000 0.085000 8.640000 0.560000 ; - RECT 8.425000 1.835000 8.660000 2.635000 ; - RECT 8.490000 1.245000 8.660000 1.315000 ; - RECT 8.830000 0.255000 9.235000 0.765000 ; - RECT 8.830000 1.065000 9.745000 1.375000 ; - RECT 8.830000 1.375000 9.160000 2.465000 ; - RECT 9.370000 2.105000 9.660000 2.635000 ; - RECT 9.465000 0.085000 9.740000 0.615000 ; - RECT 10.090000 1.245000 10.280000 1.965000 ; - RECT 10.225000 2.165000 11.110000 2.355000 ; - RECT 10.305000 0.705000 10.770000 1.035000 ; - RECT 10.325000 0.330000 11.110000 0.535000 ; - RECT 10.450000 1.035000 10.770000 1.995000 ; - RECT 10.940000 0.535000 11.110000 0.995000 ; - RECT 10.940000 0.995000 11.810000 1.325000 ; - RECT 10.940000 1.325000 11.110000 2.165000 ; - RECT 11.280000 1.530000 12.180000 1.905000 ; - RECT 11.280000 2.135000 11.540000 2.635000 ; - RECT 11.350000 0.085000 11.665000 0.615000 ; - RECT 11.840000 1.905000 12.180000 2.465000 ; - RECT 11.850000 0.300000 12.180000 0.825000 ; - RECT 11.990000 0.825000 12.180000 1.530000 ; - RECT 12.350000 0.085000 12.585000 0.900000 ; - RECT 12.350000 1.465000 12.585000 2.635000 ; - RECT 13.255000 0.085000 13.515000 0.900000 ; - RECT 13.255000 1.465000 13.515000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.615000 0.425000 4.785000 0.595000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.530000 0.425000 6.700000 0.595000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.100000 1.445000 7.270000 1.615000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 1.785000 7.680000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.100000 1.785000 10.270000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.445000 10.690000 1.615000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.000000 0.765000 12.170000 0.935000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 10.330000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 10.750000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 12.230000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.555000 0.395000 6.760000 0.580000 ; - RECT 4.555000 0.580000 4.845000 0.625000 ; - RECT 6.470000 0.580000 6.760000 0.625000 ; - RECT 7.040000 1.415000 7.330000 1.460000 ; - RECT 7.040000 1.600000 7.330000 1.645000 ; - RECT 7.450000 1.755000 7.740000 1.800000 ; - RECT 7.450000 1.940000 7.740000 1.985000 ; - RECT 10.040000 1.755000 10.330000 1.800000 ; - RECT 10.040000 1.940000 10.330000 1.985000 ; - RECT 10.460000 1.415000 10.750000 1.460000 ; - RECT 10.460000 1.600000 10.750000 1.645000 ; - RECT 11.940000 0.735000 12.230000 0.780000 ; - RECT 11.940000 0.920000 12.230000 0.965000 ; - END -END sky130_fd_sc_hd__sedfxtp_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__sedfxtp_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__sedfxtp_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 14.72000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN D - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.695000 0.765000 1.915000 1.720000 ; - END - END D - PIN DE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.110000 0.765000 2.565000 1.185000 ; - RECT 2.110000 1.185000 2.325000 1.370000 ; - END - END DE - PIN Q - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 12.755000 0.305000 13.085000 1.070000 ; - RECT 12.755000 1.070000 13.925000 1.295000 ; - RECT 12.755000 1.295000 13.085000 2.420000 ; - RECT 13.595000 0.305000 13.925000 1.070000 ; - RECT 13.595000 1.295000 13.925000 2.420000 ; - END - END Q - PIN SCD - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.760000 1.105000 6.215000 1.665000 ; - END - END SCD - PIN SCE - ANTENNAGATEAREA 0.318000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 5.025000 1.105000 5.250000 1.615000 ; - END - END SCE - PIN CLK - ANTENNAGATEAREA 0.159000 ; - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER li1 ; - RECT 0.095000 0.975000 0.445000 1.625000 ; - END - END CLK - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 14.720000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 4.885000 1.435000 ; - RECT -0.190000 1.435000 14.910000 2.910000 ; - RECT 7.200000 1.305000 14.910000 1.435000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 14.720000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 14.720000 0.085000 ; - RECT 0.000000 2.635000 14.720000 2.805000 ; - RECT 0.175000 0.345000 0.345000 0.635000 ; - RECT 0.175000 0.635000 0.845000 0.805000 ; - RECT 0.175000 1.795000 0.845000 1.965000 ; - RECT 0.175000 1.965000 0.345000 2.465000 ; - RECT 0.515000 0.085000 0.845000 0.465000 ; - RECT 0.515000 2.135000 0.845000 2.635000 ; - RECT 0.615000 0.805000 0.845000 1.795000 ; - RECT 1.015000 0.345000 1.185000 2.465000 ; - RECT 1.355000 0.255000 1.785000 0.515000 ; - RECT 1.355000 0.515000 1.525000 1.890000 ; - RECT 1.355000 1.890000 1.785000 2.465000 ; - RECT 2.235000 0.085000 2.565000 0.515000 ; - RECT 2.235000 1.890000 2.565000 2.635000 ; - RECT 2.495000 1.355000 3.085000 1.720000 ; - RECT 2.755000 1.720000 3.085000 2.425000 ; - RECT 2.780000 0.255000 3.005000 0.845000 ; - RECT 2.780000 0.845000 3.635000 1.175000 ; - RECT 2.780000 1.175000 3.085000 1.355000 ; - RECT 3.185000 0.085000 3.515000 0.610000 ; - RECT 3.265000 1.825000 3.460000 2.635000 ; - RECT 3.805000 0.685000 3.975000 1.320000 ; - RECT 3.805000 1.320000 4.175000 1.650000 ; - RECT 4.125000 1.820000 4.515000 2.020000 ; - RECT 4.125000 2.020000 4.455000 2.465000 ; - RECT 4.145000 0.255000 4.415000 0.980000 ; - RECT 4.145000 0.980000 4.515000 1.150000 ; - RECT 4.345000 1.150000 4.515000 1.820000 ; - RECT 4.595000 0.255000 4.795000 0.645000 ; - RECT 4.595000 0.645000 4.855000 0.825000 ; - RECT 4.635000 2.210000 4.965000 2.465000 ; - RECT 4.685000 0.825000 4.855000 1.785000 ; - RECT 4.685000 1.785000 4.965000 2.210000 ; - RECT 4.965000 0.255000 5.590000 0.515000 ; - RECT 5.155000 1.835000 6.585000 2.005000 ; - RECT 5.155000 2.005000 5.495000 2.465000 ; - RECT 5.260000 0.515000 5.590000 0.935000 ; - RECT 5.420000 0.935000 5.590000 1.835000 ; - RECT 5.665000 2.175000 6.010000 2.635000 ; - RECT 5.760000 0.085000 6.010000 0.905000 ; - RECT 6.385000 1.355000 6.585000 1.835000 ; - RECT 6.515000 0.255000 7.135000 0.565000 ; - RECT 6.515000 0.565000 6.925000 1.185000 ; - RECT 6.675000 2.150000 7.005000 2.465000 ; - RECT 6.755000 1.185000 6.925000 1.865000 ; - RECT 6.755000 1.865000 7.005000 2.150000 ; - RECT 7.095000 1.125000 7.280000 1.720000 ; - RECT 7.115000 0.735000 7.620000 0.955000 ; - RECT 7.215000 2.175000 8.255000 2.375000 ; - RECT 7.305000 0.255000 7.980000 0.565000 ; - RECT 7.450000 0.955000 7.620000 1.655000 ; - RECT 7.450000 1.655000 7.915000 2.005000 ; - RECT 7.810000 0.565000 7.980000 1.315000 ; - RECT 7.810000 1.315000 8.660000 1.485000 ; - RECT 8.085000 1.485000 8.660000 1.575000 ; - RECT 8.085000 1.575000 8.255000 2.175000 ; - RECT 8.170000 0.765000 9.235000 1.045000 ; - RECT 8.170000 1.045000 9.745000 1.065000 ; - RECT 8.170000 1.065000 8.370000 1.095000 ; - RECT 8.245000 0.085000 8.640000 0.560000 ; - RECT 8.425000 1.835000 8.660000 2.635000 ; - RECT 8.490000 1.245000 8.660000 1.315000 ; - RECT 8.830000 0.255000 9.235000 0.765000 ; - RECT 8.830000 1.065000 9.745000 1.375000 ; - RECT 8.830000 1.375000 9.160000 2.465000 ; - RECT 9.370000 2.105000 9.660000 2.635000 ; - RECT 9.465000 0.085000 9.740000 0.615000 ; - RECT 10.090000 1.245000 10.280000 1.965000 ; - RECT 10.225000 2.165000 11.110000 2.355000 ; - RECT 10.305000 0.705000 10.770000 1.035000 ; - RECT 10.325000 0.330000 11.110000 0.535000 ; - RECT 10.450000 1.035000 10.770000 1.995000 ; - RECT 10.940000 0.535000 11.110000 0.995000 ; - RECT 10.940000 0.995000 11.810000 1.325000 ; - RECT 10.940000 1.325000 11.110000 2.165000 ; - RECT 11.280000 1.530000 12.180000 1.905000 ; - RECT 11.280000 2.135000 11.540000 2.635000 ; - RECT 11.350000 0.085000 11.665000 0.615000 ; - RECT 11.840000 1.905000 12.180000 2.465000 ; - RECT 11.850000 0.300000 12.180000 0.825000 ; - RECT 11.990000 0.825000 12.180000 1.530000 ; - RECT 12.350000 0.085000 12.585000 0.900000 ; - RECT 12.350000 1.465000 12.585000 2.635000 ; - RECT 13.255000 0.085000 13.425000 0.900000 ; - RECT 13.255000 1.465000 13.425000 2.635000 ; - RECT 14.095000 0.085000 14.355000 1.280000 ; - RECT 14.095000 1.465000 14.355000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 0.635000 1.785000 0.805000 1.955000 ; - RECT 1.015000 1.445000 1.185000 1.615000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.355000 0.425000 1.525000 0.595000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.805000 0.765000 3.975000 0.935000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.185000 0.425000 4.355000 0.595000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.615000 0.425000 4.785000 0.595000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.530000 0.425000 6.700000 0.595000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.100000 1.445000 7.270000 1.615000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.510000 1.785000 7.680000 1.955000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - RECT 10.100000 1.785000 10.270000 1.955000 ; - RECT 10.265000 -0.085000 10.435000 0.085000 ; - RECT 10.265000 2.635000 10.435000 2.805000 ; - RECT 10.520000 1.445000 10.690000 1.615000 ; - RECT 10.725000 -0.085000 10.895000 0.085000 ; - RECT 10.725000 2.635000 10.895000 2.805000 ; - RECT 11.185000 -0.085000 11.355000 0.085000 ; - RECT 11.185000 2.635000 11.355000 2.805000 ; - RECT 11.645000 -0.085000 11.815000 0.085000 ; - RECT 11.645000 2.635000 11.815000 2.805000 ; - RECT 12.000000 0.765000 12.170000 0.935000 ; - RECT 12.105000 -0.085000 12.275000 0.085000 ; - RECT 12.105000 2.635000 12.275000 2.805000 ; - RECT 12.565000 -0.085000 12.735000 0.085000 ; - RECT 12.565000 2.635000 12.735000 2.805000 ; - RECT 13.025000 -0.085000 13.195000 0.085000 ; - RECT 13.025000 2.635000 13.195000 2.805000 ; - RECT 13.485000 -0.085000 13.655000 0.085000 ; - RECT 13.485000 2.635000 13.655000 2.805000 ; - RECT 13.945000 -0.085000 14.115000 0.085000 ; - RECT 13.945000 2.635000 14.115000 2.805000 ; - RECT 14.405000 -0.085000 14.575000 0.085000 ; - RECT 14.405000 2.635000 14.575000 2.805000 ; - LAYER met1 ; - RECT 0.575000 1.755000 0.865000 1.800000 ; - RECT 0.575000 1.800000 10.330000 1.940000 ; - RECT 0.575000 1.940000 0.865000 1.985000 ; - RECT 0.955000 1.415000 1.245000 1.460000 ; - RECT 0.955000 1.460000 10.750000 1.600000 ; - RECT 0.955000 1.600000 1.245000 1.645000 ; - RECT 1.295000 0.395000 4.415000 0.580000 ; - RECT 1.295000 0.580000 1.585000 0.625000 ; - RECT 3.745000 0.735000 4.035000 0.780000 ; - RECT 3.745000 0.780000 12.230000 0.920000 ; - RECT 3.745000 0.920000 4.035000 0.965000 ; - RECT 4.125000 0.580000 4.415000 0.625000 ; - RECT 4.555000 0.395000 6.760000 0.580000 ; - RECT 4.555000 0.580000 4.845000 0.625000 ; - RECT 6.470000 0.580000 6.760000 0.625000 ; - RECT 7.040000 1.415000 7.330000 1.460000 ; - RECT 7.040000 1.600000 7.330000 1.645000 ; - RECT 7.450000 1.755000 7.740000 1.800000 ; - RECT 7.450000 1.940000 7.740000 1.985000 ; - RECT 10.040000 1.755000 10.330000 1.800000 ; - RECT 10.040000 1.940000 10.330000 1.985000 ; - RECT 10.460000 1.415000 10.750000 1.460000 ; - RECT 10.460000 1.600000 10.750000 1.645000 ; - RECT 11.940000 0.735000 12.230000 0.780000 ; - RECT 11.940000 0.920000 12.230000 0.965000 ; - END -END sky130_fd_sc_hd__sedfxtp_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__tap_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__tap_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.460000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.460000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 0.085000 0.265000 0.375000 0.810000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.470000 0.375000 2.455000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.460000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.460000 0.085000 ; - RECT 0.000000 2.635000 0.460000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - END -END sky130_fd_sc_hd__tap_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__tap_2 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__tap_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.920000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.920000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 0.085000 0.265000 0.835000 0.810000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.775000 0.845000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.085000 1.470000 0.835000 2.455000 ; - LAYER nwell ; - RECT -0.190000 1.305000 1.110000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.920000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.920000 0.085000 ; - RECT 0.000000 2.635000 0.920000 2.805000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - END -END sky130_fd_sc_hd__tap_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__tapvgnd2_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__tapvgnd2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.460000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.460000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.085000 1.755000 0.375000 1.985000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.460000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.460000 0.085000 ; - RECT 0.000000 2.635000 0.460000 2.805000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 1.470000 0.375000 2.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 1.785000 0.315000 1.955000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - END -END sky130_fd_sc_hd__tapvgnd2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__tapvgnd_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__tapvgnd_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.460000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.460000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END - END VGND - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.085000 2.095000 0.375000 2.325000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.460000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.460000 0.085000 ; - RECT 0.000000 2.635000 0.460000 2.805000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 1.470000 0.375000 2.455000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.125000 0.315000 2.295000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - END -END sky130_fd_sc_hd__tapvgnd_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__tapvpwrvgnd_1 - CLASS CORE WELLTAP ; - FOREIGN sky130_fd_sc_hd__tapvpwrvgnd_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 0.460000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 0.460000 0.240000 ; - LAYER pwell ; - RECT 0.145000 0.320000 0.315000 0.845000 ; - END - END VGND - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 0.460000 2.960000 ; - LAYER nwell ; - RECT -0.190000 1.305000 0.650000 2.910000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 0.460000 0.085000 ; - RECT 0.000000 2.635000 0.460000 2.805000 ; - RECT 0.085000 0.085000 0.375000 0.810000 ; - RECT 0.085000 1.470000 0.375000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - END -END sky130_fd_sc_hd__tapvpwrvgnd_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.930000 1.075000 1.625000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.670000 1.445000 ; - RECT 0.425000 1.445000 1.965000 1.615000 ; - RECT 1.795000 1.075000 2.395000 1.245000 ; - RECT 1.795000 1.245000 1.965000 1.445000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.525000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.265000 2.125000 2.645000 2.295000 ; - RECT 2.475000 1.755000 3.135000 1.955000 ; - RECT 2.475000 1.955000 2.645000 2.125000 ; - RECT 2.815000 0.345000 3.135000 0.825000 ; - RECT 2.965000 0.825000 3.135000 1.755000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.280000 0.550000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.785000 ; - RECT 0.085000 1.785000 2.305000 1.955000 ; - RECT 0.085000 2.125000 0.385000 2.635000 ; - RECT 0.555000 1.955000 0.885000 2.465000 ; - RECT 1.055000 0.085000 1.225000 0.905000 ; - RECT 1.055000 2.125000 1.685000 2.635000 ; - RECT 1.395000 0.255000 1.725000 0.735000 ; - RECT 1.395000 0.735000 2.645000 0.825000 ; - RECT 1.395000 0.825000 2.305000 0.905000 ; - RECT 1.895000 0.085000 2.245000 0.475000 ; - RECT 2.135000 0.655000 2.645000 0.735000 ; - RECT 2.135000 1.415000 2.795000 1.585000 ; - RECT 2.135000 1.585000 2.305000 1.785000 ; - RECT 2.415000 0.255000 2.645000 0.655000 ; - RECT 2.625000 0.995000 2.795000 1.415000 ; - RECT 2.815000 2.125000 3.115000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__xnor2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.255000 1.075000 2.705000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.485000 1.075000 0.960000 1.285000 ; - RECT 0.790000 1.285000 0.960000 1.445000 ; - RECT 0.790000 1.445000 3.100000 1.615000 ; - RECT 2.930000 1.075000 3.955000 1.285000 ; - RECT 2.930000 1.285000 3.100000 1.445000 ; - END - END B - PIN Y - ANTENNADIFFAREA 0.913000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.725000 1.795000 5.295000 1.965000 ; - RECT 3.725000 1.965000 3.935000 2.125000 ; - RECT 4.585000 0.305000 5.895000 0.475000 ; - RECT 5.045000 1.415000 5.895000 1.625000 ; - RECT 5.045000 1.625000 5.295000 1.795000 ; - RECT 5.045000 1.965000 5.295000 2.125000 ; - RECT 5.505000 0.475000 5.895000 1.415000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.085000 0.645000 0.860000 0.895000 ; - RECT 0.085000 0.895000 0.315000 1.785000 ; - RECT 0.085000 1.785000 3.480000 1.955000 ; - RECT 0.085000 1.955000 2.080000 1.965000 ; - RECT 0.085000 1.965000 0.400000 2.465000 ; - RECT 0.105000 0.255000 1.280000 0.475000 ; - RECT 0.570000 2.135000 0.820000 2.635000 ; - RECT 0.990000 1.965000 1.240000 2.465000 ; - RECT 1.030000 0.475000 1.280000 0.725000 ; - RECT 1.030000 0.725000 2.120000 0.905000 ; - RECT 1.410000 2.135000 1.660000 2.635000 ; - RECT 1.450000 0.085000 1.620000 0.555000 ; - RECT 1.790000 0.255000 2.120000 0.725000 ; - RECT 1.830000 1.965000 2.080000 2.465000 ; - RECT 2.390000 2.125000 2.640000 2.465000 ; - RECT 2.430000 0.085000 2.600000 0.905000 ; - RECT 2.770000 0.255000 3.100000 0.725000 ; - RECT 2.770000 0.725000 5.335000 0.905000 ; - RECT 2.810000 2.135000 3.060000 2.635000 ; - RECT 3.230000 2.125000 3.555000 2.295000 ; - RECT 3.230000 2.295000 4.355000 2.465000 ; - RECT 3.270000 0.085000 3.440000 0.555000 ; - RECT 3.310000 1.455000 4.805000 1.625000 ; - RECT 3.310000 1.625000 3.480000 1.785000 ; - RECT 3.610000 0.255000 3.975000 0.725000 ; - RECT 4.105000 2.135000 4.355000 2.295000 ; - RECT 4.145000 0.085000 4.315000 0.555000 ; - RECT 4.625000 2.135000 4.875000 2.635000 ; - RECT 4.635000 1.075000 5.295000 1.245000 ; - RECT 4.635000 1.245000 4.805000 1.455000 ; - RECT 5.005000 0.645000 5.335000 0.725000 ; - RECT 5.465000 1.795000 5.895000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.465000 2.125000 2.635000 2.295000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.385000 2.125000 3.555000 2.295000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 2.405000 2.095000 2.695000 2.140000 ; - RECT 2.405000 2.140000 3.615000 2.280000 ; - RECT 2.405000 2.280000 2.695000 2.325000 ; - RECT 3.325000 2.095000 3.615000 2.140000 ; - RECT 3.325000 2.280000 3.615000 2.325000 ; - END -END sky130_fd_sc_hd__xnor2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.175000 1.075000 5.390000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.490000 1.075000 1.855000 1.275000 ; - RECT 1.685000 1.275000 1.855000 1.445000 ; - RECT 1.685000 1.445000 5.730000 1.615000 ; - RECT 5.560000 1.075000 7.430000 1.275000 ; - RECT 5.560000 1.275000 5.730000 1.445000 ; - END - END B - PIN Y - ANTENNADIFFAREA 1.721000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.160000 1.785000 8.250000 2.045000 ; - RECT 7.960000 1.445000 10.035000 1.665000 ; - RECT 7.960000 1.665000 8.250000 1.785000 ; - RECT 7.960000 2.045000 8.250000 2.465000 ; - RECT 8.380000 0.645000 10.035000 0.905000 ; - RECT 8.840000 1.665000 9.090000 2.465000 ; - RECT 9.680000 1.665000 10.035000 2.465000 ; - RECT 9.815000 0.905000 10.035000 1.445000 ; - END - END Y - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.085000 0.645000 1.760000 0.905000 ; - RECT 0.085000 0.905000 0.320000 1.445000 ; - RECT 0.085000 1.445000 1.300000 1.615000 ; - RECT 0.085000 1.615000 0.460000 2.465000 ; - RECT 0.170000 0.255000 2.180000 0.475000 ; - RECT 0.630000 1.835000 0.880000 2.635000 ; - RECT 1.050000 1.615000 1.300000 1.785000 ; - RECT 1.050000 1.785000 3.820000 2.005000 ; - RECT 1.050000 2.005000 1.300000 2.465000 ; - RECT 1.470000 2.175000 1.720000 2.635000 ; - RECT 1.890000 2.005000 2.140000 2.465000 ; - RECT 1.930000 0.475000 2.180000 0.725000 ; - RECT 1.930000 0.725000 3.860000 0.905000 ; - RECT 2.310000 2.175000 2.560000 2.635000 ; - RECT 2.350000 0.085000 2.520000 0.555000 ; - RECT 2.690000 0.255000 3.020000 0.725000 ; - RECT 2.730000 2.005000 2.980000 2.465000 ; - RECT 3.150000 2.175000 3.400000 2.635000 ; - RECT 3.190000 0.085000 3.360000 0.555000 ; - RECT 3.530000 0.255000 3.860000 0.725000 ; - RECT 3.570000 2.005000 3.820000 2.465000 ; - RECT 4.035000 0.085000 4.310000 0.905000 ; - RECT 4.035000 1.785000 5.990000 2.005000 ; - RECT 4.035000 2.005000 4.350000 2.465000 ; - RECT 4.480000 0.255000 4.810000 0.725000 ; - RECT 4.480000 0.725000 7.430000 0.735000 ; - RECT 4.480000 0.735000 8.210000 0.905000 ; - RECT 4.520000 2.175000 4.770000 2.635000 ; - RECT 4.940000 2.005000 5.190000 2.465000 ; - RECT 4.980000 0.085000 5.150000 0.555000 ; - RECT 5.320000 0.255000 5.650000 0.725000 ; - RECT 5.360000 2.175000 5.610000 2.635000 ; - RECT 5.780000 2.005000 5.990000 2.215000 ; - RECT 5.780000 2.215000 7.750000 2.465000 ; - RECT 5.820000 0.085000 5.990000 0.555000 ; - RECT 5.900000 1.445000 7.770000 1.615000 ; - RECT 6.160000 0.255000 6.490000 0.725000 ; - RECT 6.660000 0.085000 6.830000 0.555000 ; - RECT 7.000000 0.255000 7.330000 0.725000 ; - RECT 7.500000 0.085000 7.770000 0.555000 ; - RECT 7.600000 1.075000 9.645000 1.275000 ; - RECT 7.600000 1.275000 7.770000 1.445000 ; - RECT 7.960000 0.305000 9.970000 0.475000 ; - RECT 7.960000 0.475000 8.210000 0.735000 ; - RECT 8.420000 1.835000 8.670000 2.635000 ; - RECT 9.260000 1.835000 9.510000 2.635000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 1.445000 1.235000 1.615000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 1.445000 6.295000 1.615000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - LAYER met1 ; - RECT 1.005000 1.415000 1.295000 1.460000 ; - RECT 1.005000 1.460000 6.355000 1.600000 ; - RECT 1.005000 1.600000 1.295000 1.645000 ; - RECT 6.065000 1.415000 6.355000 1.460000 ; - RECT 6.065000 1.600000 6.355000 1.645000 ; - END -END sky130_fd_sc_hd__xnor2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.280000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.045000 1.075000 7.455000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.225000 0.995000 6.395000 1.445000 ; - RECT 6.225000 1.445000 6.805000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.615000 1.075000 2.180000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.449000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.350000 0.345000 0.925000 ; - RECT 0.085000 0.925000 0.330000 1.440000 ; - RECT 0.085000 1.440000 0.365000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.280000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.470000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.280000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.280000 0.085000 ; - RECT 0.000000 2.635000 8.280000 2.805000 ; - RECT 0.500000 0.995000 0.705000 1.325000 ; - RECT 0.515000 0.085000 0.765000 0.525000 ; - RECT 0.530000 0.695000 1.105000 0.865000 ; - RECT 0.530000 0.865000 0.705000 0.995000 ; - RECT 0.535000 1.325000 0.705000 1.875000 ; - RECT 0.535000 1.875000 1.220000 2.045000 ; - RECT 0.535000 2.215000 0.870000 2.635000 ; - RECT 0.935000 0.255000 2.505000 0.425000 ; - RECT 0.935000 0.425000 1.105000 0.695000 ; - RECT 0.935000 1.535000 2.520000 1.705000 ; - RECT 1.050000 2.045000 1.220000 2.235000 ; - RECT 1.050000 2.235000 2.520000 2.405000 ; - RECT 1.275000 0.595000 1.445000 1.535000 ; - RECT 1.560000 1.895000 4.060000 2.065000 ; - RECT 1.745000 0.625000 2.965000 0.795000 ; - RECT 1.745000 0.795000 2.125000 0.905000 ; - RECT 2.070000 0.425000 2.505000 0.455000 ; - RECT 2.350000 0.995000 2.625000 1.325000 ; - RECT 2.350000 1.325000 2.520000 1.535000 ; - RECT 2.675000 0.285000 3.305000 0.455000 ; - RECT 2.690000 1.525000 3.075000 1.695000 ; - RECT 2.795000 0.795000 2.965000 1.375000 ; - RECT 2.795000 1.375000 3.075000 1.525000 ; - RECT 3.135000 0.455000 3.305000 1.035000 ; - RECT 3.135000 1.035000 3.415000 1.205000 ; - RECT 3.225000 2.235000 3.555000 2.635000 ; - RECT 3.245000 1.205000 3.415000 1.895000 ; - RECT 3.475000 0.085000 3.645000 0.865000 ; - RECT 3.645000 1.445000 4.065000 1.715000 ; - RECT 3.825000 0.415000 4.065000 1.445000 ; - RECT 3.890000 2.065000 4.060000 2.275000 ; - RECT 3.890000 2.275000 6.985000 2.445000 ; - RECT 4.245000 0.265000 4.655000 0.485000 ; - RECT 4.245000 0.485000 4.455000 0.595000 ; - RECT 4.245000 0.595000 4.415000 2.105000 ; - RECT 4.585000 0.720000 4.995000 0.825000 ; - RECT 4.585000 0.825000 4.795000 0.890000 ; - RECT 4.585000 0.890000 4.755000 2.275000 ; - RECT 4.625000 0.655000 4.995000 0.720000 ; - RECT 4.825000 0.320000 4.995000 0.655000 ; - RECT 4.935000 1.445000 5.715000 1.615000 ; - RECT 4.935000 1.615000 5.350000 2.045000 ; - RECT 4.950000 0.995000 5.375000 1.270000 ; - RECT 5.165000 0.630000 5.375000 0.995000 ; - RECT 5.545000 0.255000 6.690000 0.425000 ; - RECT 5.545000 0.425000 5.715000 1.445000 ; - RECT 5.885000 0.595000 6.055000 1.935000 ; - RECT 5.885000 1.935000 8.195000 2.105000 ; - RECT 6.225000 0.425000 6.690000 0.465000 ; - RECT 6.565000 0.730000 6.770000 0.945000 ; - RECT 6.565000 0.945000 6.875000 1.275000 ; - RECT 6.975000 1.495000 7.795000 1.705000 ; - RECT 7.015000 0.295000 7.305000 0.735000 ; - RECT 7.015000 0.735000 7.795000 0.750000 ; - RECT 7.055000 0.750000 7.795000 0.905000 ; - RECT 7.395000 2.275000 7.730000 2.635000 ; - RECT 7.475000 0.085000 7.645000 0.565000 ; - RECT 7.625000 0.905000 7.795000 0.995000 ; - RECT 7.625000 0.995000 7.855000 1.325000 ; - RECT 7.625000 1.325000 7.795000 1.495000 ; - RECT 7.710000 1.875000 8.195000 1.935000 ; - RECT 7.895000 0.255000 8.195000 0.585000 ; - RECT 7.900000 2.105000 8.195000 2.465000 ; - RECT 8.025000 0.585000 8.195000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 1.445000 3.075000 1.615000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 0.765000 3.995000 0.935000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 0.425000 4.455000 0.595000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 0.765000 5.375000 0.935000 ; - RECT 5.205000 1.445000 5.375000 1.615000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 0.765000 6.755000 0.935000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 0.425000 7.215000 0.595000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - LAYER met1 ; - RECT 2.845000 1.415000 3.135000 1.460000 ; - RECT 2.845000 1.460000 5.435000 1.600000 ; - RECT 2.845000 1.600000 3.135000 1.645000 ; - RECT 3.765000 0.735000 4.055000 0.780000 ; - RECT 3.765000 0.780000 6.815000 0.920000 ; - RECT 3.765000 0.920000 4.055000 0.965000 ; - RECT 4.225000 0.395000 4.515000 0.440000 ; - RECT 4.225000 0.440000 7.275000 0.580000 ; - RECT 4.225000 0.580000 4.515000 0.625000 ; - RECT 5.145000 0.735000 5.435000 0.780000 ; - RECT 5.145000 0.920000 5.435000 0.965000 ; - RECT 5.145000 1.415000 5.435000 1.460000 ; - RECT 5.145000 1.600000 5.435000 1.645000 ; - RECT 6.525000 0.735000 6.815000 0.780000 ; - RECT 6.525000 0.920000 6.815000 0.965000 ; - RECT 6.985000 0.395000 7.275000 0.440000 ; - RECT 6.985000 0.580000 7.275000 0.625000 ; - END -END sky130_fd_sc_hd__xnor3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.505000 1.075000 7.915000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.685000 0.995000 6.855000 1.445000 ; - RECT 6.685000 1.445000 7.265000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.075000 1.075000 2.640000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 0.350000 0.805000 0.925000 ; - RECT 0.545000 0.925000 0.790000 1.440000 ; - RECT 0.545000 1.440000 0.825000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.150000 -0.085000 0.320000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.085000 0.085000 0.375000 0.735000 ; - RECT 0.085000 1.490000 0.375000 2.635000 ; - RECT 0.960000 0.995000 1.165000 1.325000 ; - RECT 0.975000 0.085000 1.225000 0.525000 ; - RECT 0.990000 0.695000 1.565000 0.865000 ; - RECT 0.990000 0.865000 1.165000 0.995000 ; - RECT 0.995000 1.325000 1.165000 1.875000 ; - RECT 0.995000 1.875000 1.680000 2.045000 ; - RECT 0.995000 2.215000 1.330000 2.635000 ; - RECT 1.395000 0.255000 2.965000 0.425000 ; - RECT 1.395000 0.425000 1.565000 0.695000 ; - RECT 1.395000 1.535000 2.980000 1.705000 ; - RECT 1.510000 2.045000 1.680000 2.235000 ; - RECT 1.510000 2.235000 2.980000 2.405000 ; - RECT 1.735000 0.595000 1.905000 1.535000 ; - RECT 2.020000 1.895000 4.520000 2.065000 ; - RECT 2.205000 0.625000 3.425000 0.795000 ; - RECT 2.205000 0.795000 2.585000 0.905000 ; - RECT 2.530000 0.425000 2.965000 0.455000 ; - RECT 2.810000 0.995000 3.085000 1.325000 ; - RECT 2.810000 1.325000 2.980000 1.535000 ; - RECT 3.135000 0.285000 3.765000 0.455000 ; - RECT 3.150000 1.525000 3.535000 1.695000 ; - RECT 3.255000 0.795000 3.425000 1.375000 ; - RECT 3.255000 1.375000 3.535000 1.525000 ; - RECT 3.595000 0.455000 3.765000 1.035000 ; - RECT 3.595000 1.035000 3.875000 1.205000 ; - RECT 3.685000 2.235000 4.015000 2.635000 ; - RECT 3.705000 1.205000 3.875000 1.895000 ; - RECT 3.935000 0.085000 4.105000 0.865000 ; - RECT 4.105000 1.445000 4.525000 1.715000 ; - RECT 4.285000 0.415000 4.525000 1.445000 ; - RECT 4.350000 2.065000 4.520000 2.275000 ; - RECT 4.350000 2.275000 7.445000 2.445000 ; - RECT 4.705000 0.265000 5.115000 0.485000 ; - RECT 4.705000 0.485000 4.915000 0.595000 ; - RECT 4.705000 0.595000 4.875000 2.105000 ; - RECT 5.045000 0.720000 5.455000 0.825000 ; - RECT 5.045000 0.825000 5.255000 0.890000 ; - RECT 5.045000 0.890000 5.215000 2.275000 ; - RECT 5.085000 0.655000 5.455000 0.720000 ; - RECT 5.285000 0.320000 5.455000 0.655000 ; - RECT 5.395000 1.445000 6.175000 1.615000 ; - RECT 5.395000 1.615000 5.810000 2.045000 ; - RECT 5.410000 0.995000 5.835000 1.270000 ; - RECT 5.625000 0.630000 5.835000 0.995000 ; - RECT 6.005000 0.255000 7.150000 0.425000 ; - RECT 6.005000 0.425000 6.175000 1.445000 ; - RECT 6.345000 0.595000 6.515000 1.935000 ; - RECT 6.345000 1.935000 8.655000 2.105000 ; - RECT 6.685000 0.425000 7.150000 0.465000 ; - RECT 7.025000 0.730000 7.230000 0.945000 ; - RECT 7.025000 0.945000 7.335000 1.275000 ; - RECT 7.435000 1.495000 8.255000 1.705000 ; - RECT 7.475000 0.295000 7.765000 0.735000 ; - RECT 7.475000 0.735000 8.255000 0.750000 ; - RECT 7.515000 0.750000 8.255000 0.905000 ; - RECT 7.855000 2.275000 8.190000 2.635000 ; - RECT 7.935000 0.085000 8.105000 0.565000 ; - RECT 8.085000 0.905000 8.255000 0.995000 ; - RECT 8.085000 0.995000 8.315000 1.325000 ; - RECT 8.085000 1.325000 8.255000 1.495000 ; - RECT 8.170000 1.875000 8.655000 1.935000 ; - RECT 8.355000 0.255000 8.655000 0.585000 ; - RECT 8.360000 2.105000 8.655000 2.465000 ; - RECT 8.485000 0.585000 8.655000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 1.445000 3.535000 1.615000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 0.765000 4.455000 0.935000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.425000 4.915000 0.595000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 0.765000 5.835000 0.935000 ; - RECT 5.665000 1.445000 5.835000 1.615000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 0.425000 7.675000 0.595000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - LAYER met1 ; - RECT 3.305000 1.415000 3.595000 1.460000 ; - RECT 3.305000 1.460000 5.895000 1.600000 ; - RECT 3.305000 1.600000 3.595000 1.645000 ; - RECT 4.225000 0.735000 4.515000 0.780000 ; - RECT 4.225000 0.780000 7.275000 0.920000 ; - RECT 4.225000 0.920000 4.515000 0.965000 ; - RECT 4.685000 0.395000 4.975000 0.440000 ; - RECT 4.685000 0.440000 7.735000 0.580000 ; - RECT 4.685000 0.580000 4.975000 0.625000 ; - RECT 5.605000 0.735000 5.895000 0.780000 ; - RECT 5.605000 0.920000 5.895000 0.965000 ; - RECT 5.605000 1.415000 5.895000 1.460000 ; - RECT 5.605000 1.600000 5.895000 1.645000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - RECT 7.445000 0.395000 7.735000 0.440000 ; - RECT 7.445000 0.580000 7.735000 0.625000 ; - END -END sky130_fd_sc_hd__xnor3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xnor3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xnor3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.660000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.425000 1.075000 8.835000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.605000 0.995000 7.775000 1.445000 ; - RECT 7.605000 1.445000 8.185000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.995000 1.075000 3.560000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.625000 0.375000 0.875000 0.995000 ; - RECT 0.625000 0.995000 1.710000 1.325000 ; - RECT 0.625000 1.325000 0.955000 2.425000 ; - RECT 1.465000 0.350000 1.725000 0.925000 ; - RECT 1.465000 0.925000 1.710000 0.995000 ; - RECT 1.465000 1.325000 1.710000 1.440000 ; - RECT 1.465000 1.440000 1.745000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.660000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.850000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.660000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.660000 0.085000 ; - RECT 0.000000 2.635000 9.660000 2.805000 ; - RECT 0.285000 0.085000 0.455000 0.735000 ; - RECT 0.285000 1.490000 0.455000 2.635000 ; - RECT 1.125000 0.085000 1.295000 0.735000 ; - RECT 1.125000 1.495000 1.295000 2.635000 ; - RECT 1.880000 0.995000 2.085000 1.325000 ; - RECT 1.895000 0.085000 2.145000 0.525000 ; - RECT 1.910000 0.695000 2.485000 0.865000 ; - RECT 1.910000 0.865000 2.085000 0.995000 ; - RECT 1.915000 1.325000 2.085000 1.875000 ; - RECT 1.915000 1.875000 2.600000 2.045000 ; - RECT 1.915000 2.215000 2.250000 2.635000 ; - RECT 2.315000 0.255000 3.885000 0.425000 ; - RECT 2.315000 0.425000 2.485000 0.695000 ; - RECT 2.315000 1.535000 3.900000 1.705000 ; - RECT 2.430000 2.045000 2.600000 2.235000 ; - RECT 2.430000 2.235000 3.900000 2.405000 ; - RECT 2.655000 0.595000 2.825000 1.535000 ; - RECT 2.940000 1.895000 5.440000 2.065000 ; - RECT 3.125000 0.625000 4.345000 0.795000 ; - RECT 3.125000 0.795000 3.505000 0.905000 ; - RECT 3.450000 0.425000 3.885000 0.455000 ; - RECT 3.730000 0.995000 4.005000 1.325000 ; - RECT 3.730000 1.325000 3.900000 1.535000 ; - RECT 4.055000 0.285000 4.685000 0.455000 ; - RECT 4.070000 1.525000 4.455000 1.695000 ; - RECT 4.175000 0.795000 4.345000 1.375000 ; - RECT 4.175000 1.375000 4.455000 1.525000 ; - RECT 4.515000 0.455000 4.685000 1.035000 ; - RECT 4.515000 1.035000 4.795000 1.205000 ; - RECT 4.605000 2.235000 4.935000 2.635000 ; - RECT 4.625000 1.205000 4.795000 1.895000 ; - RECT 4.855000 0.085000 5.025000 0.865000 ; - RECT 5.025000 1.445000 5.445000 1.715000 ; - RECT 5.205000 0.415000 5.445000 1.445000 ; - RECT 5.270000 2.065000 5.440000 2.275000 ; - RECT 5.270000 2.275000 8.365000 2.445000 ; - RECT 5.625000 0.265000 6.035000 0.485000 ; - RECT 5.625000 0.485000 5.835000 0.595000 ; - RECT 5.625000 0.595000 5.795000 2.105000 ; - RECT 5.965000 0.720000 6.375000 0.825000 ; - RECT 5.965000 0.825000 6.175000 0.890000 ; - RECT 5.965000 0.890000 6.135000 2.275000 ; - RECT 6.005000 0.655000 6.375000 0.720000 ; - RECT 6.205000 0.320000 6.375000 0.655000 ; - RECT 6.315000 1.445000 7.095000 1.615000 ; - RECT 6.315000 1.615000 6.730000 2.045000 ; - RECT 6.330000 0.995000 6.755000 1.270000 ; - RECT 6.545000 0.630000 6.755000 0.995000 ; - RECT 6.925000 0.255000 8.070000 0.425000 ; - RECT 6.925000 0.425000 7.095000 1.445000 ; - RECT 7.265000 0.595000 7.435000 1.935000 ; - RECT 7.265000 1.935000 9.575000 2.105000 ; - RECT 7.605000 0.425000 8.070000 0.465000 ; - RECT 7.945000 0.730000 8.150000 0.945000 ; - RECT 7.945000 0.945000 8.255000 1.275000 ; - RECT 8.355000 1.495000 9.175000 1.705000 ; - RECT 8.395000 0.295000 8.685000 0.735000 ; - RECT 8.395000 0.735000 9.175000 0.750000 ; - RECT 8.435000 0.750000 9.175000 0.905000 ; - RECT 8.775000 2.275000 9.110000 2.635000 ; - RECT 8.855000 0.085000 9.025000 0.565000 ; - RECT 9.005000 0.905000 9.175000 0.995000 ; - RECT 9.005000 0.995000 9.235000 1.325000 ; - RECT 9.005000 1.325000 9.175000 1.495000 ; - RECT 9.090000 1.875000 9.575000 1.935000 ; - RECT 9.275000 0.255000 9.575000 0.585000 ; - RECT 9.280000 2.105000 9.575000 2.465000 ; - RECT 9.405000 0.585000 9.575000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 1.445000 4.455000 1.615000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 0.765000 5.375000 0.935000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 0.425000 5.835000 0.595000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 0.765000 6.755000 0.935000 ; - RECT 6.585000 1.445000 6.755000 1.615000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 0.765000 8.135000 0.935000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 0.425000 8.595000 0.595000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - LAYER met1 ; - RECT 4.225000 1.415000 4.515000 1.460000 ; - RECT 4.225000 1.460000 6.815000 1.600000 ; - RECT 4.225000 1.600000 4.515000 1.645000 ; - RECT 5.145000 0.735000 5.435000 0.780000 ; - RECT 5.145000 0.780000 8.195000 0.920000 ; - RECT 5.145000 0.920000 5.435000 0.965000 ; - RECT 5.605000 0.395000 5.895000 0.440000 ; - RECT 5.605000 0.440000 8.655000 0.580000 ; - RECT 5.605000 0.580000 5.895000 0.625000 ; - RECT 6.525000 0.735000 6.815000 0.780000 ; - RECT 6.525000 0.920000 6.815000 0.965000 ; - RECT 6.525000 1.415000 6.815000 1.460000 ; - RECT 6.525000 1.600000 6.815000 1.645000 ; - RECT 7.905000 0.735000 8.195000 0.780000 ; - RECT 7.905000 0.920000 8.195000 0.965000 ; - RECT 8.365000 0.395000 8.655000 0.440000 ; - RECT 8.365000 0.580000 8.655000 0.625000 ; - END -END sky130_fd_sc_hd__xnor3_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor2_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor2_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 3.220000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.840000 1.075000 1.390000 1.275000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.495000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 0.995000 0.670000 1.445000 ; - RECT 0.425000 1.445000 1.730000 1.615000 ; - RECT 1.560000 1.075000 1.935000 1.245000 ; - RECT 1.560000 1.245000 1.730000 1.445000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.800500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.720000 0.315000 2.675000 0.485000 ; - RECT 2.505000 0.485000 2.675000 1.365000 ; - RECT 2.505000 1.365000 3.135000 1.535000 ; - RECT 2.815000 1.535000 3.135000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 3.220000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 3.410000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 3.220000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 3.220000 0.085000 ; - RECT 0.000000 2.635000 3.220000 2.805000 ; - RECT 0.085000 0.655000 2.335000 0.825000 ; - RECT 0.085000 0.825000 0.255000 1.785000 ; - RECT 0.085000 1.785000 0.465000 2.465000 ; - RECT 0.135000 0.085000 0.465000 0.475000 ; - RECT 0.635000 0.335000 0.805000 0.655000 ; - RECT 0.975000 0.085000 1.305000 0.475000 ; - RECT 1.055000 1.785000 1.225000 2.635000 ; - RECT 1.395000 1.785000 2.635000 1.955000 ; - RECT 1.395000 1.955000 1.725000 2.465000 ; - RECT 1.895000 2.125000 2.065000 2.635000 ; - RECT 2.105000 0.825000 2.335000 1.325000 ; - RECT 2.235000 1.955000 2.635000 2.465000 ; - RECT 2.845000 0.085000 3.135000 0.920000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - END -END sky130_fd_sc_hd__xor2_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor2_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor2_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 5.980000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 1.075000 0.875000 1.275000 ; - RECT 0.705000 1.275000 0.875000 1.445000 ; - RECT 0.705000 1.445000 1.880000 1.615000 ; - RECT 1.710000 1.075000 3.230000 1.275000 ; - RECT 1.710000 1.275000 1.880000 1.445000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.990000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.045000 1.075000 1.540000 1.275000 ; - LAYER mcon ; - RECT 1.065000 1.105000 1.235000 1.275000 ; - END - PORT - LAYER li1 ; - RECT 3.420000 1.075000 4.090000 1.275000 ; - LAYER mcon ; - RECT 3.825000 1.105000 3.995000 1.275000 ; - END - PORT - LAYER met1 ; - RECT 1.005000 1.075000 1.295000 1.120000 ; - RECT 1.005000 1.120000 4.055000 1.260000 ; - RECT 1.005000 1.260000 1.295000 1.305000 ; - RECT 3.765000 1.075000 4.055000 1.120000 ; - RECT 3.765000 1.260000 4.055000 1.305000 ; - END - END B - PIN X - ANTENNADIFFAREA 0.656750 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 3.625000 0.645000 3.955000 0.725000 ; - RECT 3.625000 0.725000 5.895000 0.905000 ; - RECT 4.985000 0.645000 5.315000 0.725000 ; - RECT 5.025000 1.415000 5.895000 1.625000 ; - RECT 5.025000 1.625000 5.275000 2.125000 ; - RECT 5.485000 0.905000 5.895000 1.415000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 5.980000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 6.170000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 5.980000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 5.980000 0.085000 ; - RECT 0.000000 2.635000 5.980000 2.805000 ; - RECT 0.120000 0.725000 1.700000 0.905000 ; - RECT 0.120000 0.905000 0.290000 1.785000 ; - RECT 0.120000 1.785000 2.220000 1.955000 ; - RECT 0.120000 2.135000 0.400000 2.465000 ; - RECT 0.145000 2.125000 0.315000 2.135000 ; - RECT 0.190000 0.085000 0.360000 0.555000 ; - RECT 0.530000 0.255000 0.860000 0.725000 ; - RECT 0.570000 2.135000 0.820000 2.635000 ; - RECT 0.990000 2.135000 1.240000 2.295000 ; - RECT 0.990000 2.295000 2.080000 2.465000 ; - RECT 1.030000 0.085000 1.200000 0.555000 ; - RECT 1.065000 2.125000 1.235000 2.135000 ; - RECT 1.370000 0.255000 1.700000 0.725000 ; - RECT 1.410000 1.955000 1.660000 2.125000 ; - RECT 1.830000 2.135000 2.080000 2.295000 ; - RECT 1.870000 0.085000 2.040000 0.555000 ; - RECT 2.050000 1.445000 4.785000 1.615000 ; - RECT 2.050000 1.615000 2.220000 1.785000 ; - RECT 2.285000 2.125000 2.600000 2.465000 ; - RECT 2.310000 0.255000 2.640000 0.725000 ; - RECT 2.310000 0.725000 3.400000 0.905000 ; - RECT 2.390000 1.785000 4.855000 1.955000 ; - RECT 2.390000 1.955000 2.600000 2.125000 ; - RECT 2.770000 2.135000 3.020000 2.635000 ; - RECT 2.810000 0.085000 2.980000 0.555000 ; - RECT 3.150000 0.255000 4.380000 0.475000 ; - RECT 3.150000 0.475000 3.400000 0.725000 ; - RECT 3.190000 1.955000 3.440000 2.465000 ; - RECT 3.610000 2.135000 3.915000 2.635000 ; - RECT 4.085000 1.955000 4.855000 2.295000 ; - RECT 4.085000 2.295000 5.695000 2.465000 ; - RECT 4.615000 1.075000 5.275000 1.245000 ; - RECT 4.615000 1.245000 4.785000 1.445000 ; - RECT 4.645000 0.085000 4.815000 0.555000 ; - RECT 5.445000 1.795000 5.695000 2.295000 ; - RECT 5.485000 0.085000 5.655000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - LAYER met1 ; - RECT 0.085000 2.095000 0.375000 2.140000 ; - RECT 0.085000 2.140000 1.295000 2.280000 ; - RECT 0.085000 2.280000 0.375000 2.325000 ; - RECT 1.005000 2.095000 1.295000 2.140000 ; - RECT 1.005000 2.280000 1.295000 2.325000 ; - END -END sky130_fd_sc_hd__xor2_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor2_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor2_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.425000 1.075000 2.800000 1.275000 ; - RECT 2.630000 1.275000 2.800000 1.445000 ; - RECT 2.630000 1.445000 6.165000 1.615000 ; - RECT 5.995000 1.075000 7.370000 1.275000 ; - RECT 5.995000 1.275000 6.165000 1.445000 ; - END - END A - PIN B - ANTENNAGATEAREA 1.980000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.970000 1.075000 5.000000 1.105000 ; - RECT 2.970000 1.105000 5.740000 1.275000 ; - END - END B - PIN X - ANTENNADIFFAREA 1.524450 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 4.165000 0.645000 5.580000 0.905000 ; - RECT 5.150000 0.905000 5.580000 0.935000 ; - LAYER mcon ; - RECT 5.205000 0.765000 5.375000 0.935000 ; - END - PORT - LAYER li1 ; - RECT 7.850000 0.725000 8.630000 0.735000 ; - RECT 7.850000 0.735000 10.035000 0.905000 ; - RECT 7.850000 0.905000 8.305000 0.935000 ; - RECT 7.880000 1.445000 10.035000 1.625000 ; - RECT 7.880000 1.625000 9.010000 1.665000 ; - RECT 7.880000 1.665000 8.170000 2.125000 ; - RECT 8.300000 0.255000 8.630000 0.725000 ; - RECT 8.760000 1.665000 9.010000 2.125000 ; - RECT 9.140000 0.255000 9.470000 0.735000 ; - RECT 9.600000 1.625000 10.035000 2.465000 ; - RECT 9.735000 0.905000 10.035000 1.445000 ; - LAYER mcon ; - RECT 7.965000 0.765000 8.135000 0.935000 ; - END - PORT - LAYER met1 ; - RECT 5.145000 0.735000 5.435000 0.780000 ; - RECT 5.145000 0.780000 8.195000 0.920000 ; - RECT 5.145000 0.920000 5.435000 0.965000 ; - RECT 7.905000 0.735000 8.195000 0.780000 ; - RECT 7.905000 0.920000 8.195000 0.965000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.085000 0.085000 0.360000 0.565000 ; - RECT 0.085000 0.735000 3.380000 0.905000 ; - RECT 0.085000 0.905000 0.255000 1.445000 ; - RECT 0.085000 1.445000 2.420000 1.615000 ; - RECT 0.085000 1.785000 2.080000 2.005000 ; - RECT 0.085000 2.005000 0.400000 2.465000 ; - RECT 0.530000 0.255000 0.860000 0.725000 ; - RECT 0.530000 0.725000 3.380000 0.735000 ; - RECT 0.570000 2.175000 0.820000 2.635000 ; - RECT 0.990000 2.005000 1.240000 2.465000 ; - RECT 1.030000 0.085000 1.200000 0.555000 ; - RECT 1.370000 0.255000 1.700000 0.725000 ; - RECT 1.410000 2.175000 1.660000 2.635000 ; - RECT 1.830000 2.005000 2.080000 2.295000 ; - RECT 1.830000 2.295000 3.760000 2.465000 ; - RECT 1.870000 0.085000 2.040000 0.555000 ; - RECT 2.210000 0.255000 2.540000 0.725000 ; - RECT 2.250000 1.615000 2.420000 1.785000 ; - RECT 2.250000 1.785000 3.340000 1.955000 ; - RECT 2.250000 1.955000 2.500000 2.125000 ; - RECT 2.670000 2.125000 2.920000 2.295000 ; - RECT 2.710000 0.085000 2.880000 0.555000 ; - RECT 3.050000 0.255000 3.380000 0.725000 ; - RECT 3.090000 1.955000 3.340000 2.125000 ; - RECT 3.510000 1.795000 3.760000 2.295000 ; - RECT 3.550000 0.085000 3.820000 0.895000 ; - RECT 3.990000 0.255000 6.000000 0.475000 ; - RECT 4.030000 1.785000 7.640000 2.005000 ; - RECT 4.030000 2.005000 4.280000 2.465000 ; - RECT 4.450000 2.175000 4.700000 2.635000 ; - RECT 4.870000 2.005000 5.120000 2.465000 ; - RECT 5.290000 2.175000 5.540000 2.635000 ; - RECT 5.710000 2.005000 5.960000 2.465000 ; - RECT 5.750000 0.475000 6.000000 0.725000 ; - RECT 5.750000 0.725000 7.680000 0.905000 ; - RECT 6.130000 2.175000 6.380000 2.635000 ; - RECT 6.170000 0.085000 6.340000 0.555000 ; - RECT 6.510000 0.255000 6.840000 0.725000 ; - RECT 6.550000 1.455000 6.800000 1.785000 ; - RECT 6.550000 2.005000 6.800000 2.465000 ; - RECT 6.970000 2.175000 7.220000 2.635000 ; - RECT 7.010000 0.085000 7.180000 0.555000 ; - RECT 7.260000 1.445000 7.710000 1.615000 ; - RECT 7.350000 0.255000 7.680000 0.725000 ; - RECT 7.390000 2.005000 7.640000 2.295000 ; - RECT 7.390000 2.295000 9.430000 2.465000 ; - RECT 7.540000 1.105000 9.565000 1.275000 ; - RECT 7.540000 1.275000 7.710000 1.445000 ; - RECT 7.960000 0.085000 8.130000 0.555000 ; - RECT 8.340000 1.835000 8.590000 2.295000 ; - RECT 8.540000 1.075000 9.565000 1.105000 ; - RECT 8.800000 0.085000 8.970000 0.555000 ; - RECT 9.180000 1.795000 9.430000 2.295000 ; - RECT 9.640000 0.085000 9.810000 0.555000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 1.445000 2.155000 1.615000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 1.445000 7.675000 1.615000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - LAYER met1 ; - RECT 1.925000 1.415000 2.215000 1.460000 ; - RECT 1.925000 1.460000 7.735000 1.600000 ; - RECT 1.925000 1.600000 2.215000 1.645000 ; - RECT 7.445000 1.415000 7.735000 1.460000 ; - RECT 7.445000 1.600000 7.735000 1.645000 ; - END -END sky130_fd_sc_hd__xor2_4 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor3_1 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor3_1 ; - ORIGIN 0.000000 0.000000 ; - SIZE 8.740000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.505000 1.075000 7.915000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 6.685000 0.995000 6.855000 1.445000 ; - RECT 6.685000 1.445000 7.265000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 1.860000 0.995000 2.495000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.449000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.085000 0.350000 0.590000 0.925000 ; - RECT 0.085000 0.925000 0.400000 1.440000 ; - RECT 0.085000 1.440000 0.610000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 8.740000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 8.930000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 8.740000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 8.740000 0.085000 ; - RECT 0.000000 2.635000 8.740000 2.805000 ; - RECT 0.750000 0.995000 0.950000 1.325000 ; - RECT 0.760000 0.085000 1.010000 0.525000 ; - RECT 0.780000 0.695000 1.350000 0.865000 ; - RECT 0.780000 0.865000 0.950000 0.995000 ; - RECT 0.780000 1.325000 0.950000 1.875000 ; - RECT 0.780000 1.875000 1.470000 2.045000 ; - RECT 0.780000 2.215000 1.115000 2.635000 ; - RECT 1.180000 0.255000 2.740000 0.425000 ; - RECT 1.180000 0.425000 1.350000 0.695000 ; - RECT 1.185000 1.535000 2.835000 1.705000 ; - RECT 1.300000 2.045000 1.470000 2.235000 ; - RECT 1.300000 2.235000 2.895000 2.405000 ; - RECT 1.520000 0.595000 1.690000 1.535000 ; - RECT 1.870000 1.895000 3.175000 2.065000 ; - RECT 1.970000 0.655000 3.080000 0.825000 ; - RECT 2.390000 0.425000 2.740000 0.455000 ; - RECT 2.665000 0.995000 2.940000 1.325000 ; - RECT 2.665000 1.325000 2.835000 1.535000 ; - RECT 2.910000 0.255000 3.760000 0.425000 ; - RECT 2.910000 0.425000 3.080000 0.655000 ; - RECT 3.005000 1.525000 3.535000 1.695000 ; - RECT 3.005000 1.695000 3.175000 1.895000 ; - RECT 3.110000 2.235000 3.515000 2.405000 ; - RECT 3.250000 0.595000 3.420000 1.375000 ; - RECT 3.250000 1.375000 3.535000 1.525000 ; - RECT 3.345000 1.895000 4.520000 2.065000 ; - RECT 3.345000 2.065000 3.515000 2.235000 ; - RECT 3.590000 0.425000 3.760000 1.035000 ; - RECT 3.590000 1.035000 3.875000 1.205000 ; - RECT 3.685000 2.235000 4.015000 2.635000 ; - RECT 3.705000 1.205000 3.875000 1.895000 ; - RECT 3.930000 0.085000 4.100000 0.865000 ; - RECT 4.105000 1.445000 4.520000 1.715000 ; - RECT 4.280000 0.415000 4.520000 1.445000 ; - RECT 4.350000 2.065000 4.520000 2.275000 ; - RECT 4.350000 2.275000 7.445000 2.445000 ; - RECT 4.695000 0.265000 5.110000 0.485000 ; - RECT 4.695000 0.485000 4.915000 0.595000 ; - RECT 4.695000 0.595000 4.865000 2.105000 ; - RECT 5.035000 0.720000 5.450000 0.825000 ; - RECT 5.035000 0.825000 5.255000 0.890000 ; - RECT 5.035000 0.890000 5.205000 2.275000 ; - RECT 5.085000 0.655000 5.450000 0.720000 ; - RECT 5.280000 0.320000 5.450000 0.655000 ; - RECT 5.395000 1.445000 6.175000 1.615000 ; - RECT 5.395000 1.615000 5.810000 2.045000 ; - RECT 5.410000 0.995000 5.835000 1.270000 ; - RECT 5.620000 0.630000 5.835000 0.995000 ; - RECT 6.005000 0.255000 7.150000 0.425000 ; - RECT 6.005000 0.425000 6.175000 1.445000 ; - RECT 6.345000 0.595000 6.515000 1.935000 ; - RECT 6.345000 1.935000 8.655000 2.105000 ; - RECT 6.685000 0.425000 7.150000 0.465000 ; - RECT 7.025000 0.730000 7.230000 0.945000 ; - RECT 7.025000 0.945000 7.335000 1.275000 ; - RECT 7.435000 1.495000 8.255000 1.705000 ; - RECT 7.475000 0.295000 7.765000 0.735000 ; - RECT 7.475000 0.735000 8.255000 0.750000 ; - RECT 7.515000 0.750000 8.255000 0.905000 ; - RECT 7.855000 2.275000 8.190000 2.635000 ; - RECT 7.935000 0.085000 8.105000 0.565000 ; - RECT 8.085000 0.905000 8.255000 0.995000 ; - RECT 8.085000 0.995000 8.315000 1.325000 ; - RECT 8.085000 1.325000 8.255000 1.495000 ; - RECT 8.170000 1.875000 8.655000 1.935000 ; - RECT 8.355000 0.255000 8.655000 0.585000 ; - RECT 8.360000 2.105000 8.655000 2.465000 ; - RECT 8.485000 0.585000 8.655000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 1.445000 3.535000 1.615000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 0.765000 4.455000 0.935000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.425000 4.915000 0.595000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 0.765000 5.835000 0.935000 ; - RECT 5.665000 1.445000 5.835000 1.615000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 0.765000 7.215000 0.935000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 0.425000 7.675000 0.595000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - LAYER met1 ; - RECT 3.305000 1.415000 3.595000 1.460000 ; - RECT 3.305000 1.460000 5.895000 1.600000 ; - RECT 3.305000 1.600000 3.595000 1.645000 ; - RECT 4.225000 0.735000 4.515000 0.780000 ; - RECT 4.225000 0.780000 7.275000 0.920000 ; - RECT 4.225000 0.920000 4.515000 0.965000 ; - RECT 4.685000 0.395000 4.975000 0.440000 ; - RECT 4.685000 0.440000 7.735000 0.580000 ; - RECT 4.685000 0.580000 4.975000 0.625000 ; - RECT 5.605000 0.735000 5.895000 0.780000 ; - RECT 5.605000 0.920000 5.895000 0.965000 ; - RECT 5.605000 1.415000 5.895000 1.460000 ; - RECT 5.605000 1.600000 5.895000 1.645000 ; - RECT 6.985000 0.735000 7.275000 0.780000 ; - RECT 6.985000 0.920000 7.275000 0.965000 ; - RECT 7.445000 0.395000 7.735000 0.440000 ; - RECT 7.445000 0.580000 7.735000 0.625000 ; - END -END sky130_fd_sc_hd__xor3_1 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor3_2 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor3_2 ; - ORIGIN 0.000000 0.000000 ; - SIZE 9.200000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.965000 1.075000 8.375000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.145000 0.995000 7.315000 1.445000 ; - RECT 7.145000 1.445000 7.725000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.320000 0.995000 2.955000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.445500 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.545000 0.660000 1.050000 0.925000 ; - RECT 0.545000 0.925000 0.860000 1.440000 ; - RECT 0.545000 1.440000 1.070000 2.045000 ; - RECT 0.800000 0.350000 1.050000 0.660000 ; - RECT 0.820000 2.045000 1.070000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 9.200000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 9.390000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0.000000 2.480000 9.200000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 0.000000 -0.085000 9.200000 0.085000 ; - RECT 0.000000 2.635000 9.200000 2.805000 ; - RECT 0.300000 0.085000 0.630000 0.465000 ; - RECT 0.300000 2.215000 0.650000 2.635000 ; - RECT 1.210000 0.995000 1.410000 1.325000 ; - RECT 1.220000 0.085000 1.470000 0.525000 ; - RECT 1.240000 0.695000 1.810000 0.865000 ; - RECT 1.240000 0.865000 1.410000 0.995000 ; - RECT 1.240000 1.325000 1.410000 1.875000 ; - RECT 1.240000 1.875000 1.930000 2.045000 ; - RECT 1.240000 2.215000 1.575000 2.635000 ; - RECT 1.640000 0.255000 3.200000 0.425000 ; - RECT 1.640000 0.425000 1.810000 0.695000 ; - RECT 1.645000 1.535000 3.295000 1.705000 ; - RECT 1.760000 2.045000 1.930000 2.235000 ; - RECT 1.760000 2.235000 3.355000 2.405000 ; - RECT 1.980000 0.595000 2.150000 1.535000 ; - RECT 2.330000 1.895000 3.635000 2.065000 ; - RECT 2.430000 0.655000 3.540000 0.825000 ; - RECT 2.850000 0.425000 3.200000 0.455000 ; - RECT 3.125000 0.995000 3.400000 1.325000 ; - RECT 3.125000 1.325000 3.295000 1.535000 ; - RECT 3.370000 0.255000 4.220000 0.425000 ; - RECT 3.370000 0.425000 3.540000 0.655000 ; - RECT 3.465000 1.525000 3.995000 1.695000 ; - RECT 3.465000 1.695000 3.635000 1.895000 ; - RECT 3.570000 2.235000 3.975000 2.405000 ; - RECT 3.710000 0.595000 3.880000 1.375000 ; - RECT 3.710000 1.375000 3.995000 1.525000 ; - RECT 3.805000 1.895000 4.980000 2.065000 ; - RECT 3.805000 2.065000 3.975000 2.235000 ; - RECT 4.050000 0.425000 4.220000 1.035000 ; - RECT 4.050000 1.035000 4.335000 1.205000 ; - RECT 4.145000 2.235000 4.475000 2.635000 ; - RECT 4.165000 1.205000 4.335000 1.895000 ; - RECT 4.390000 0.085000 4.560000 0.865000 ; - RECT 4.565000 1.445000 4.980000 1.715000 ; - RECT 4.740000 0.415000 4.980000 1.445000 ; - RECT 4.810000 2.065000 4.980000 2.275000 ; - RECT 4.810000 2.275000 7.905000 2.445000 ; - RECT 5.155000 0.265000 5.570000 0.485000 ; - RECT 5.155000 0.485000 5.375000 0.595000 ; - RECT 5.155000 0.595000 5.325000 2.105000 ; - RECT 5.495000 0.720000 5.910000 0.825000 ; - RECT 5.495000 0.825000 5.715000 0.890000 ; - RECT 5.495000 0.890000 5.665000 2.275000 ; - RECT 5.545000 0.655000 5.910000 0.720000 ; - RECT 5.740000 0.320000 5.910000 0.655000 ; - RECT 5.855000 1.445000 6.635000 1.615000 ; - RECT 5.855000 1.615000 6.270000 2.045000 ; - RECT 5.870000 0.995000 6.295000 1.270000 ; - RECT 6.080000 0.630000 6.295000 0.995000 ; - RECT 6.465000 0.255000 7.610000 0.425000 ; - RECT 6.465000 0.425000 6.635000 1.445000 ; - RECT 6.805000 0.595000 6.975000 1.935000 ; - RECT 6.805000 1.935000 9.115000 2.105000 ; - RECT 7.145000 0.425000 7.610000 0.465000 ; - RECT 7.485000 0.730000 7.690000 0.945000 ; - RECT 7.485000 0.945000 7.795000 1.275000 ; - RECT 7.895000 1.495000 8.715000 1.705000 ; - RECT 7.935000 0.295000 8.225000 0.735000 ; - RECT 7.935000 0.735000 8.715000 0.750000 ; - RECT 7.975000 0.750000 8.715000 0.905000 ; - RECT 8.315000 2.275000 8.650000 2.635000 ; - RECT 8.395000 0.085000 8.565000 0.565000 ; - RECT 8.545000 0.905000 8.715000 0.995000 ; - RECT 8.545000 0.995000 8.775000 1.325000 ; - RECT 8.545000 1.325000 8.715000 1.495000 ; - RECT 8.630000 1.875000 9.115000 1.935000 ; - RECT 8.815000 0.255000 9.115000 0.585000 ; - RECT 8.820000 2.105000 9.115000 2.465000 ; - RECT 8.945000 0.585000 9.115000 1.875000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 3.825000 1.445000 3.995000 1.615000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 4.745000 0.765000 4.915000 0.935000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.205000 0.425000 5.375000 0.595000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.125000 0.765000 6.295000 0.935000 ; - RECT 6.125000 1.445000 6.295000 1.615000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.505000 0.765000 7.675000 0.935000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 7.965000 0.425000 8.135000 0.595000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - LAYER met1 ; - RECT 3.765000 1.415000 4.055000 1.460000 ; - RECT 3.765000 1.460000 6.355000 1.600000 ; - RECT 3.765000 1.600000 4.055000 1.645000 ; - RECT 4.685000 0.735000 4.975000 0.780000 ; - RECT 4.685000 0.780000 7.735000 0.920000 ; - RECT 4.685000 0.920000 4.975000 0.965000 ; - RECT 5.145000 0.395000 5.435000 0.440000 ; - RECT 5.145000 0.440000 8.195000 0.580000 ; - RECT 5.145000 0.580000 5.435000 0.625000 ; - RECT 6.065000 0.735000 6.355000 0.780000 ; - RECT 6.065000 0.920000 6.355000 0.965000 ; - RECT 6.065000 1.415000 6.355000 1.460000 ; - RECT 6.065000 1.600000 6.355000 1.645000 ; - RECT 7.445000 0.735000 7.735000 0.780000 ; - RECT 7.445000 0.920000 7.735000 0.965000 ; - RECT 7.905000 0.395000 8.195000 0.440000 ; - RECT 7.905000 0.580000 8.195000 0.625000 ; - END -END sky130_fd_sc_hd__xor3_2 -#--------EOF--------- - -MACRO sky130_fd_sc_hd__xor3_4 - CLASS CORE ; - FOREIGN sky130_fd_sc_hd__xor3_4 ; - ORIGIN 0.000000 0.000000 ; - SIZE 10.12000 BY 2.720000 ; - SYMMETRY X Y R90 ; - SITE unithd ; - PIN A - ANTENNAGATEAREA 0.246000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 8.525000 1.075000 8.935000 1.325000 ; - END - END A - PIN B - ANTENNAGATEAREA 0.661500 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 7.705000 0.995000 7.875000 1.445000 ; - RECT 7.705000 1.445000 8.285000 1.615000 ; - END - END B - PIN C - ANTENNAGATEAREA 0.381000 ; - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 2.880000 0.995000 3.515000 1.325000 ; - END - END C - PIN X - ANTENNADIFFAREA 0.891000 ; - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER li1 ; - RECT 0.595000 0.350000 0.765000 0.660000 ; - RECT 0.595000 0.660000 1.605000 0.830000 ; - RECT 0.595000 0.830000 1.535000 0.925000 ; - RECT 0.695000 1.440000 1.420000 1.455000 ; - RECT 0.695000 1.455000 1.705000 2.045000 ; - RECT 0.695000 2.045000 0.865000 2.465000 ; - RECT 1.105000 0.925000 1.420000 1.440000 ; - RECT 1.435000 0.350000 1.605000 0.660000 ; - RECT 1.535000 2.045000 1.705000 2.465000 ; - END - END X - PIN VGND - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE GROUND ; - PORT - LAYER li1 ; - RECT 0.000000 -0.085000 10.120000 0.085000 ; - RECT 0.175000 0.085000 0.345000 0.545000 ; - RECT 0.935000 0.085000 1.265000 0.465000 ; - RECT 1.855000 0.085000 2.025000 0.525000 ; - RECT 4.950000 0.085000 5.120000 0.885000 ; - RECT 8.995000 0.085000 9.165000 0.565000 ; - LAYER mcon ; - RECT 0.145000 -0.085000 0.315000 0.085000 ; - RECT 0.605000 -0.085000 0.775000 0.085000 ; - RECT 1.065000 -0.085000 1.235000 0.085000 ; - RECT 1.525000 -0.085000 1.695000 0.085000 ; - RECT 1.985000 -0.085000 2.155000 0.085000 ; - RECT 2.445000 -0.085000 2.615000 0.085000 ; - RECT 2.905000 -0.085000 3.075000 0.085000 ; - RECT 3.365000 -0.085000 3.535000 0.085000 ; - RECT 3.825000 -0.085000 3.995000 0.085000 ; - RECT 4.285000 -0.085000 4.455000 0.085000 ; - RECT 4.745000 -0.085000 4.915000 0.085000 ; - RECT 5.205000 -0.085000 5.375000 0.085000 ; - RECT 5.665000 -0.085000 5.835000 0.085000 ; - RECT 6.125000 -0.085000 6.295000 0.085000 ; - RECT 6.585000 -0.085000 6.755000 0.085000 ; - RECT 7.045000 -0.085000 7.215000 0.085000 ; - RECT 7.505000 -0.085000 7.675000 0.085000 ; - RECT 7.965000 -0.085000 8.135000 0.085000 ; - RECT 8.425000 -0.085000 8.595000 0.085000 ; - RECT 8.885000 -0.085000 9.055000 0.085000 ; - RECT 9.345000 -0.085000 9.515000 0.085000 ; - RECT 9.805000 -0.085000 9.975000 0.085000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 -0.240000 10.120000 0.240000 ; - END - END VGND - PIN VNB - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER pwell ; - RECT 0.235000 -0.085000 0.405000 0.085000 ; - END - END VNB - PIN VPB - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER nwell ; - RECT -0.190000 1.305000 10.310000 2.910000 ; - END - END VPB - PIN VPWR - DIRECTION INOUT ; - SHAPE ABUTMENT ; - USE POWER ; - PORT - LAYER li1 ; - RECT 0.000000 2.635000 10.120000 2.805000 ; - RECT 0.275000 2.135000 0.445000 2.635000 ; - RECT 1.035000 2.215000 1.365000 2.635000 ; - RECT 1.875000 2.215000 2.205000 2.635000 ; - RECT 4.705000 2.235000 5.035000 2.635000 ; - RECT 8.915000 2.275000 9.245000 2.635000 ; - LAYER mcon ; - RECT 0.145000 2.635000 0.315000 2.805000 ; - RECT 0.605000 2.635000 0.775000 2.805000 ; - RECT 1.065000 2.635000 1.235000 2.805000 ; - RECT 1.525000 2.635000 1.695000 2.805000 ; - RECT 1.985000 2.635000 2.155000 2.805000 ; - RECT 2.445000 2.635000 2.615000 2.805000 ; - RECT 2.905000 2.635000 3.075000 2.805000 ; - RECT 3.365000 2.635000 3.535000 2.805000 ; - RECT 3.825000 2.635000 3.995000 2.805000 ; - RECT 4.285000 2.635000 4.455000 2.805000 ; - RECT 4.745000 2.635000 4.915000 2.805000 ; - RECT 5.205000 2.635000 5.375000 2.805000 ; - RECT 5.665000 2.635000 5.835000 2.805000 ; - RECT 6.125000 2.635000 6.295000 2.805000 ; - RECT 6.585000 2.635000 6.755000 2.805000 ; - RECT 7.045000 2.635000 7.215000 2.805000 ; - RECT 7.505000 2.635000 7.675000 2.805000 ; - RECT 7.965000 2.635000 8.135000 2.805000 ; - RECT 8.425000 2.635000 8.595000 2.805000 ; - RECT 8.885000 2.635000 9.055000 2.805000 ; - RECT 9.345000 2.635000 9.515000 2.805000 ; - RECT 9.805000 2.635000 9.975000 2.805000 ; - END - PORT - LAYER met1 ; - RECT 0.000000 2.480000 10.120000 2.960000 ; - END - END VPWR - OBS - LAYER li1 ; - RECT 1.820000 0.965000 2.045000 1.325000 ; - RECT 1.875000 0.695000 2.365000 0.865000 ; - RECT 1.875000 0.865000 2.045000 0.965000 ; - RECT 1.875000 1.325000 2.045000 1.875000 ; - RECT 1.875000 1.875000 2.545000 2.045000 ; - RECT 2.195000 0.255000 3.760000 0.425000 ; - RECT 2.195000 0.425000 2.365000 0.695000 ; - RECT 2.370000 1.535000 3.855000 1.705000 ; - RECT 2.375000 2.045000 2.545000 2.235000 ; - RECT 2.375000 2.235000 3.915000 2.405000 ; - RECT 2.540000 0.595000 2.710000 1.535000 ; - RECT 2.890000 1.895000 4.195000 2.065000 ; - RECT 2.990000 0.655000 4.100000 0.825000 ; - RECT 3.410000 0.425000 3.760000 0.455000 ; - RECT 3.685000 0.995000 4.055000 1.325000 ; - RECT 3.685000 1.325000 3.855000 1.535000 ; - RECT 3.930000 0.255000 4.780000 0.425000 ; - RECT 3.930000 0.425000 4.100000 0.655000 ; - RECT 4.025000 1.525000 4.555000 1.695000 ; - RECT 4.025000 1.695000 4.195000 1.895000 ; - RECT 4.130000 2.235000 4.535000 2.405000 ; - RECT 4.270000 0.595000 4.440000 1.375000 ; - RECT 4.270000 1.375000 4.555000 1.525000 ; - RECT 4.365000 1.895000 5.540000 2.065000 ; - RECT 4.365000 2.065000 4.535000 2.235000 ; - RECT 4.610000 0.425000 4.780000 1.035000 ; - RECT 4.610000 1.035000 4.865000 1.040000 ; - RECT 4.610000 1.040000 4.880000 1.045000 ; - RECT 4.610000 1.045000 4.890000 1.050000 ; - RECT 4.610000 1.050000 4.895000 1.205000 ; - RECT 4.725000 1.205000 4.895000 1.895000 ; - RECT 5.125000 1.445000 5.540000 1.715000 ; - RECT 5.300000 0.415000 5.540000 1.445000 ; - RECT 5.370000 2.065000 5.540000 2.275000 ; - RECT 5.370000 2.275000 8.465000 2.445000 ; - RECT 5.715000 0.265000 6.130000 0.485000 ; - RECT 5.715000 0.485000 5.935000 0.595000 ; - RECT 5.715000 0.595000 5.885000 2.105000 ; - RECT 6.075000 0.720000 6.470000 0.825000 ; - RECT 6.075000 0.825000 6.275000 0.890000 ; - RECT 6.075000 0.890000 6.245000 2.275000 ; - RECT 6.105000 0.655000 6.470000 0.720000 ; - RECT 6.300000 0.320000 6.470000 0.655000 ; - RECT 6.415000 1.445000 7.195000 1.615000 ; - RECT 6.415000 1.615000 6.830000 2.045000 ; - RECT 6.430000 0.995000 6.855000 1.270000 ; - RECT 6.640000 0.630000 6.855000 0.995000 ; - RECT 7.025000 0.255000 8.170000 0.425000 ; - RECT 7.025000 0.425000 7.195000 1.445000 ; - RECT 7.365000 0.595000 7.535000 1.935000 ; - RECT 7.365000 1.935000 9.675000 2.105000 ; - RECT 7.705000 0.425000 8.170000 0.465000 ; - RECT 8.045000 0.730000 8.250000 0.945000 ; - RECT 8.045000 0.945000 8.355000 1.275000 ; - RECT 8.455000 1.495000 9.275000 1.705000 ; - RECT 8.495000 0.295000 8.785000 0.735000 ; - RECT 8.495000 0.735000 9.275000 0.750000 ; - RECT 8.535000 0.750000 9.275000 0.905000 ; - RECT 9.105000 0.905000 9.275000 0.995000 ; - RECT 9.105000 0.995000 9.335000 1.325000 ; - RECT 9.105000 1.325000 9.275000 1.495000 ; - RECT 9.190000 1.875000 9.675000 1.935000 ; - RECT 9.415000 0.255000 9.675000 0.585000 ; - RECT 9.415000 2.105000 9.675000 2.465000 ; - RECT 9.505000 0.585000 9.675000 1.875000 ; - LAYER mcon ; - RECT 4.385000 1.445000 4.555000 1.615000 ; - RECT 5.305000 0.765000 5.475000 0.935000 ; - RECT 5.765000 0.425000 5.935000 0.595000 ; - RECT 6.685000 0.765000 6.855000 0.935000 ; - RECT 6.685000 1.445000 6.855000 1.615000 ; - RECT 8.065000 0.765000 8.235000 0.935000 ; - RECT 8.525000 0.425000 8.695000 0.595000 ; - LAYER met1 ; - RECT 4.325000 1.415000 4.615000 1.460000 ; - RECT 4.325000 1.460000 6.915000 1.600000 ; - RECT 4.325000 1.600000 4.615000 1.645000 ; - RECT 5.245000 0.735000 5.535000 0.780000 ; - RECT 5.245000 0.780000 8.295000 0.920000 ; - RECT 5.245000 0.920000 5.535000 0.965000 ; - RECT 5.705000 0.395000 5.995000 0.440000 ; - RECT 5.705000 0.440000 8.755000 0.580000 ; - RECT 5.705000 0.580000 5.995000 0.625000 ; - RECT 6.625000 0.735000 6.915000 0.780000 ; - RECT 6.625000 0.920000 6.915000 0.965000 ; - RECT 6.625000 1.415000 6.915000 1.460000 ; - RECT 6.625000 1.600000 6.915000 1.645000 ; - RECT 8.005000 0.735000 8.295000 0.780000 ; - RECT 8.005000 0.920000 8.295000 0.965000 ; - RECT 8.465000 0.395000 8.755000 0.440000 ; - RECT 8.465000 0.580000 8.755000 0.625000 ; - END -END sky130_fd_sc_hd__xor3_4 -#--------EOF--------- - - -END LIBRARY diff --git a/flow/platforms/sky130hd_fakestack/lef/sky130io_fill.lef b/flow/platforms/sky130hd_fakestack/lef/sky130io_fill.lef deleted file mode 100644 index 52770e9d75..0000000000 --- a/flow/platforms/sky130hd_fakestack/lef/sky130io_fill.lef +++ /dev/null @@ -1,52 +0,0 @@ -VERSION 5.3 ; - NAMESCASESENSITIVE ON ; - NOWIREEXTENSIONATPIN ON ; - DIVIDERCHAR "/" ; - BUSBITCHARS "[]" ; -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MACRO s8iom0s8_com_bus_slice_1um - CLASS BLOCK ; - FOREIGN s8iom0s8_com_bus_slice_1um ; - ORIGIN 0.0000 0.0000 ; - SIZE 1.0000 BY 197.9650 ; - OBS - LAYER li1 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met1 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met2 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met3 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met4 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met5 ; - RECT 0.000 0.0 1.000 197.965 ; - END -END s8iom0s8_com_bus_slice_1um -MACRO s8iom0s8_com_bus_slice_tied_1um - CLASS BLOCK ; - FOREIGN s8iom0s8_com_bus_slice_1um ; - ORIGIN 0.0000 0.0000 ; - SIZE 1.0000 BY 197.9650 ; - OBS - LAYER li1 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met1 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met2 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met3 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met4 ; - RECT 0.000 0.0 1.000 197.965 ; - LAYER met5 ; - RECT 0.000 0.0 1.000 197.965 ; - END -END s8iom0s8_com_bus_slice_tied_1um - -END LIBRARY - diff --git a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x16.lib b/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x16.lib deleted file mode 100644 index ba9bf9976a..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x16.lib +++ /dev/null @@ -1,460 +0,0 @@ -library(fakeram130_256x16) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2022-07-01 02:45:35Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.8; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.8; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 1.110; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram130_256x16_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram130_256x16_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram130_256x16_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram130_256x16_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram130_256x16_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram130_256x16_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 16; - bit_from : 15; - bit_to : 0 ; - downto : true ; - } - type (fakeram130_256x16_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram130_256x16) { - area : 53612.669; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 16; - } - pin(clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.440 ; - internal_power(){ - rise_power(fakeram130_256x16_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("11.919, 11.919") - } - fall_power(fakeram130_256x16_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("11.919, 11.919") - } - } - } - - bus(rd_out) { - bus_type : fakeram130_256x16_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : addr_in; - } - timing() { - related_pin : "clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram130_256x16_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.584, 0.584", \ - "0.584, 0.584" \ - ) - } - cell_fall(fakeram130_256x16_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.584, 0.584", \ - "0.584, 0.584" \ - ) - } - rise_transition(fakeram130_256x16_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - fall_transition(fakeram130_256x16_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - } - } - pin(we_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - } - pin(ce_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - } - bus(addr_in) { - bus_type : fakeram130_256x16_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - } - bus(wd_in) { - bus_type : fakeram130_256x16_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - } - bus(w_mask_in) { - bus_type : fakeram130_256x16_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x16_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - fall_power(fakeram130_256x16_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") - } - } - } - cell_leakage_power : 148.019; -} - -} diff --git a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x32.lib b/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x32.lib deleted file mode 100644 index bcf8965b61..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x32.lib +++ /dev/null @@ -1,460 +0,0 @@ -library(fakeram130_256x32) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2022-07-01 02:45:34Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.8; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.8; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 1.110; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram130_256x32_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram130_256x32_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram130_256x32_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram130_256x32_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram130_256x32_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram130_256x32_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 32; - bit_from : 31; - bit_to : 0 ; - downto : true ; - } - type (fakeram130_256x32_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram130_256x32) { - area : 102737.909; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 32; - } - pin(clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.440 ; - internal_power(){ - rise_power(fakeram130_256x32_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("17.953, 17.953") - } - fall_power(fakeram130_256x32_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("17.953, 17.953") - } - } - } - - bus(rd_out) { - bus_type : fakeram130_256x32_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : addr_in; - } - timing() { - related_pin : "clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram130_256x32_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.613, 0.613", \ - "0.613, 0.613" \ - ) - } - cell_fall(fakeram130_256x32_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.613, 0.613", \ - "0.613, 0.613" \ - ) - } - rise_transition(fakeram130_256x32_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - fall_transition(fakeram130_256x32_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - } - } - pin(we_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - } - pin(ce_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - } - bus(addr_in) { - bus_type : fakeram130_256x32_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - } - bus(wd_in) { - bus_type : fakeram130_256x32_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - } - bus(w_mask_in) { - bus_type : fakeram130_256x32_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x32_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - fall_power(fakeram130_256x32_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.180, 0.180") - } - } - } - cell_leakage_power : 157.750; -} - -} diff --git a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x512.lib b/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x512.lib deleted file mode 100644 index 2be3486371..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x512.lib +++ /dev/null @@ -1,460 +0,0 @@ -library(fakeram130_256x512) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2022-07-01 02:45:34Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.8; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.8; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 1.110; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram130_256x512_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram130_256x512_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram130_256x512_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram130_256x512_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram130_256x512_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram130_256x512_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 512; - bit_from : 511; - bit_to : 0 ; - downto : true ; - } - type (fakeram130_256x512_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram130_256x512) { - area : 878364.922; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 512; - } - pin(clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.702 ; - internal_power(){ - rise_power(fakeram130_256x512_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("307.445, 307.445") - } - fall_power(fakeram130_256x512_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("307.445, 307.445") - } - } - } - - bus(rd_out) { - bus_type : fakeram130_256x512_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : addr_in; - } - timing() { - related_pin : "clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram130_256x512_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.914, 0.914", \ - "0.914, 0.914" \ - ) - } - cell_fall(fakeram130_256x512_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.914, 0.914", \ - "0.914, 0.914" \ - ) - } - rise_transition(fakeram130_256x512_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - fall_transition(fakeram130_256x512_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - } - } - pin(we_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - } - pin(ce_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - } - bus(addr_in) { - bus_type : fakeram130_256x512_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - } - bus(wd_in) { - bus_type : fakeram130_256x512_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - } - bus(w_mask_in) { - bus_type : fakeram130_256x512_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x512_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - fall_power(fakeram130_256x512_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("3.074, 3.074") - } - } - } - cell_leakage_power : 1219.910; -} - -} diff --git a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x64.lib b/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x64.lib deleted file mode 100644 index f1b430bc0f..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/fakeram130_256x64.lib +++ /dev/null @@ -1,460 +0,0 @@ -library(fakeram130_256x64) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2022-07-02 07:30:56Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.8; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.8; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 1.110; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram130_256x64_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram130_256x64_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram130_256x64_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram130_256x64_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram130_256x64_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram130_256x64_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 64; - bit_from : 63; - bit_to : 0 ; - downto : true ; - } - type (fakeram130_256x64_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram130_256x64) { - area : 162110.477; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 64; - } - pin(clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.595 ; - internal_power(){ - rise_power(fakeram130_256x64_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("21.113, 21.113") - } - fall_power(fakeram130_256x64_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("21.113, 21.113") - } - } - } - - bus(rd_out) { - bus_type : fakeram130_256x64_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : addr_in; - } - timing() { - related_pin : "clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram130_256x64_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.558, 0.558", \ - "0.558, 0.558" \ - ) - } - cell_fall(fakeram130_256x64_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.558, 0.558", \ - "0.558, 0.558" \ - ) - } - rise_transition(fakeram130_256x64_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - fall_transition(fakeram130_256x64_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - } - } - pin(we_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - } - pin(ce_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - } - bus(addr_in) { - bus_type : fakeram130_256x64_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - } - bus(wd_in) { - bus_type : fakeram130_256x64_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - } - bus(w_mask_in) { - bus_type : fakeram130_256x64_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_256x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - fall_power(fakeram130_256x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.211, 0.211") - } - } - } - cell_leakage_power : 264.800; -} - -} diff --git a/flow/platforms/sky130hd_fakestack/lib/fakeram130_64x64.lib b/flow/platforms/sky130hd_fakestack/lib/fakeram130_64x64.lib deleted file mode 100644 index e556849f14..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/fakeram130_64x64.lib +++ /dev/null @@ -1,460 +0,0 @@ -library(fakeram130_64x64) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2022-07-01 02:45:36Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.8; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.8; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 1.110; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram130_64x64_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram130_64x64_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram130_64x64_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram130_64x64_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram130_64x64_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram130_64x64_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 64; - bit_from : 63; - bit_to : 0 ; - downto : true ; - } - type (fakeram130_64x64_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 6; - bit_from : 5; - bit_to : 0 ; - downto : true ; - } -cell(fakeram130_64x64) { - area : 44181.749; - interface_timing : true; - memory() { - type : ram; - address_width : 6; - word_width : 64; - } - pin(clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.394 ; - internal_power(){ - rise_power(fakeram130_64x64_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("15.950, 15.950") - } - fall_power(fakeram130_64x64_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("15.950, 15.950") - } - } - } - - bus(rd_out) { - bus_type : fakeram130_64x64_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : addr_in; - } - timing() { - related_pin : "clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram130_64x64_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.567, 0.567", \ - "0.567, 0.567" \ - ) - } - cell_fall(fakeram130_64x64_mem_out_delay_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.005, 0.500"); - values ( \ - "0.567, 0.567", \ - "0.567, 0.567" \ - ) - } - rise_transition(fakeram130_64x64_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - fall_transition(fakeram130_64x64_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.044, 1.110") - } - } - } - pin(we_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - } - pin(ce_in){ - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - } - bus(addr_in) { - bus_type : fakeram130_64x64_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - } - bus(wd_in) { - bus_type : fakeram130_64x64_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - } - bus(w_mask_in) { - bus_type : fakeram130_64x64_DATA; - memory_write() { - address : addr_in; - clocked_on : "clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : clk; - timing_type : setup_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : clk; - timing_type : hold_rising ; - rise_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram130_64x64_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (we_in) )"; - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - internal_power(){ - when : "(we_in)"; - rise_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - fall_power(fakeram130_64x64_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.160, 0.160") - } - } - } - cell_leakage_power : 79.056; -} - -} diff --git a/flow/platforms/sky130hd_fakestack/lib/sky130_dummy_io.lib b/flow/platforms/sky130hd_fakestack/lib/sky130_dummy_io.lib deleted file mode 100644 index 32e52a1bc7..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/sky130_dummy_io.lib +++ /dev/null @@ -1,493 +0,0 @@ -library (sky130_io_dummy_tt) { - comment : ""; - delay_model : table_lookup; - capacitive_load_unit (1,ff); - current_unit : "1mA"; - leakage_power_unit : "1mW"; - pulling_resistance_unit : "1kohm"; - time_unit : "1ps"; - voltage_unit : "1V"; - voltage_map (VCCD, 0.8); - voltage_map (VDDA, 0.8); - voltage_map (VDDIO, 1.8); - voltage_map (VSSC, 0); - voltage_map (VSSA, 0); - voltage_map (VSSIO, 0); - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 1; - default_input_pin_cap : 1; - default_leakage_power_density : 0; - default_max_fanout : 30; - default_max_transition : 5000; - default_output_pin_cap : 0; - in_place_swap_mode : match_footprint; - input_threshold_pct_fall : 50; - input_threshold_pct_rise : 50; - nom_process : 1; - nom_temperature : 25; - nom_voltage : 0.8; - output_threshold_pct_fall : 50; - output_threshold_pct_rise : 50; - slew_derate_from_library : 1; - slew_lower_threshold_pct_fall : 20; - slew_lower_threshold_pct_rise : 20; - slew_upper_threshold_pct_fall : 80; - slew_upper_threshold_pct_rise : 80; - input_voltage (default_VCCD_VSSC_input) { - vih : 1.8; - vil : 0; - vimax : 1.8; - vimin : 0; - } - output_voltage (default_VCCD_VSSC_output) { - voh : 1.8; - vol : 0; - vomax : 1.8; - vomin : 0; - } - input_voltage (default_VDDIO_VSSIO_input) { - vih : 3.3; - vil : 0; - vimax : 3.3; - vimin : 0; - } - output_voltage (default_VDDIO_VSSIO_output) { - voh : 3.3; - vol : 0; - vomax : 3.3; - vomin : 0; - } - operating_conditions ("typ") { - process : 1; - temperature : 25; - voltage : 1.8; - tree_type: "balanced_tree"; - } - wire_load (DEFAULT) { - area : 1; - capacitance : 0; - resistance : 0; - slope : 0.05; - fanout_length (1, 0.100); - fanout_length (8, 1.000); - } - default_operating_conditions : "typ"; - bus_naming_style : "%s[%d]"; - type (bus_DM_2_0) { - base_type : array; - data_type : bit; - bit_width : 3; - bit_from : 2; - bit_to : 0; - downto : true; - } - lu_table_template (delay_template_2x2) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("10, 200"); - index_2 ("500, 30000"); - } - cell (sky130_fd_io__top_gpiov2) { - area : 16000; - dont_touch : true; - dont_use : true; - timing_model_type : abstracted; - pad_cell : true; - pg_pin (VCCD) { - pg_type : primary_power; - voltage_name : "VCCD"; - } - pg_pin (VDDIO) { - pg_type : primary_power; - voltage_name : "VDDIO"; - } - pg_pin (VSSC) { - pg_type : primary_ground; - voltage_name : "VSSC"; - } - pg_pin (VSSIO) { - pg_type : primary_ground; - voltage_name : "VSSIO"; - } - pg_pin (VSSIO_Q) { - pg_type : primary_ground; - voltage_name : "VSSIO_Q"; - } - leakage_power () { - value : 0.0; - related_pg_pin : VDDIO; - } - leakage_power () { - value : 0.0; - related_pg_pin : VCCD; - } - pin (AMUXBUS_A) { - direction : inout; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (AMUXBUS_B) { - direction : inout; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ANALOG_EN) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ANALOG_POL) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ANALOG_SEL) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ENABLE_H) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ENABLE_INP_H) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ENABLE_VDDA_H) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ENABLE_VDDIO) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (ENABLE_VSWITCH_H) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (HLD_H_N) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (HLD_OVR) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (IB_MODE_SEL) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (INP_DIS) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (IN_H) { - direction : output; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (OE_N) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (PAD_A_ESD_0_H) { - direction : inout; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (PAD_A_ESD_1_H) { - direction : inout; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (PAD_A_NOESD_H) { - direction : inout; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (SLOW) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (TIE_HI_ESD) { - direction : output; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (TIE_LO_ESD) { - direction : output; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (VTRIP_SEL) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - output_voltage : default_VDDC_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (PAD) { - direction : inout; - function : "(OUT)"; - three_state : "!OE_N"; - input_voltage : default_VDDIO_VSSIO_input; - is_pad : true; - output_voltage : default_VDDIO_VSSIO_output; - related_ground_pin : VSSIO; - related_power_pin : VDDIO; - max_capacitance : 30000; - max_transition : 2000; - capacitance : 2000; - timing () { - related_pin : "OUT"; - timing_sense : positive_unate; - timing_type : combinational; - cell_rise (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "1000, 1000", \ - "1000, 1000" \ - ); - } - rise_transition (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "200, 200", \ - "200, 200" \ - ); - } - cell_fall (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "1000, 1000", \ - "1000, 1000" \ - ); - } - fall_transition (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "200, 200", \ - "200, 200" \ - ); - } - } - } - pin (IN) { - direction : output; - function : "(PAD)"; - output_voltage : default_VCCD_VSSC_output; - related_ground_pin : VSSC; - related_power_pin : VCCD; - max_capacitance : 500; - max_transition : 200; - timing () { - related_pin : "PAD"; - timing_type : combinational; - cell_rise (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "1000, 1000", \ - "1000, 1000" \ - ); - } - rise_transition (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "200, 200", \ - "200, 200" \ - ); - } - cell_fall (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "1000, 1000", \ - "1000, 1000" \ - ); - } - fall_transition (delay_template_2x2) { - index_1 ("10, 200"); - index_2 ("2000, 30000"); - values ( \ - "200, 200", \ - "200, 200" \ - ); - } - } - } - pin (OUT) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_transition : 200; - capacitance : 12.2211; - rise_capacitance : 12.1358; - rise_capacitance_range (11.5819, 12.4454); - fall_capacitance : 12.2211; - fall_capacitance_range (11.6201, 12.5072); - } - bus (DM) { - bus_type : bus_DM_2_0; - pin (DM[2]) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (DM[1]) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - pin (DM[0]) { - direction : input; - input_voltage : default_VDDC_VSSC_input; - related_ground_pin : VSSC; - related_power_pin : VDDC; - max_capacitance : 500; - max_transition : 200; - capacitance : 10; - } - } - } -} diff --git a/flow/platforms/sky130hd_fakestack/lib/sky130_fd_sc_hd__tt_025C_1v80.lib b/flow/platforms/sky130hd_fakestack/lib/sky130_fd_sc_hd__tt_025C_1v80.lib deleted file mode 100644 index 5773657fe7..0000000000 --- a/flow/platforms/sky130hd_fakestack/lib/sky130_fd_sc_hd__tt_025C_1v80.lib +++ /dev/null @@ -1,173160 +0,0 @@ -library ("sky130_fd_sc_hd__tt_025C_1v80") { - define(def_sim_opt,library,string); - define(default_arc_mode,library,string); - define(default_constraint_arc_mode,library,string); - define(driver_model,library,string); - define(leakage_sim_opt,library,string); - define(min_pulse_width_mode,library,string); - define(simulator,library,string); - define(switching_power_split_model,library,string); - define(sim_opt,timing,string); - define(violation_delay_degrade_pct,timing,string); - technology("cmos"); - delay_model : "table_lookup"; - bus_naming_style : "%s[%d]"; - time_unit : "1ns"; - voltage_unit : "1V"; - leakage_power_unit : "1nW"; - current_unit : "1mA"; - pulling_resistance_unit : "1kohm"; - capacitive_load_unit(1.0000000000, "pf"); - revision : 1.0000000000; - default_cell_leakage_power : 0.0000000000; - default_fanout_load : 1.0000000000; - default_inout_pin_cap : 0.0000000000; - default_input_pin_cap : 0.0000000000; - default_max_transition : 1.5000000000; - default_output_pin_cap : 0.0000000000; - default_arc_mode : "worst_edges"; - default_constraint_arc_mode : "worst"; - default_leakage_power_density : 0.0000000000; - operating_conditions ("tt_025C_1v80") { - voltage : 1.8000000000; - process : 1.0000000000; - temperature : 25.000000000; - tree_type : "balanced_tree"; - } - /* Wire load tables */ - - wire_load("Small") { - capacitance : 1.42e-05; - resistance : 0.0745; - slope : 8.3631; - fanout_length( 1, 23.2746); - fanout_length( 2, 32.1136); - fanout_length( 3, 48.4862); - fanout_length( 4, 64.0974); - fanout_length( 5, 86.2649); - fanout_length( 6, 84.2649); - } - - - wire_load("Medium") { - capacitance : 1.42e-05; - resistance : 0.0745; - slope : 8.3631; - fanout_length( 1, 23.2746); - fanout_length( 2, 32.1136); - fanout_length( 3, 48.4862); - fanout_length( 4, 64.0974); - fanout_length( 5, 86.2649); - fanout_length( 6, 84.2649); - } - - wire_load("Large") { - capacitance : 1.42e-05; - resistance : 0.0745; - slope : 8.3631; - fanout_length( 1, 23.2746); - fanout_length( 2, 32.1136); - fanout_length( 3, 48.4862); - fanout_length( 4, 64.0974); - fanout_length( 5, 86.2649); - fanout_length( 6, 84.2649); - } - - - wire_load("Huge") { - capacitance : 1.42e-05; - resistance : 0.0745; - slope : 8.3631; - fanout_length( 1, 23.2746); - fanout_length( 2, 32.1136); - fanout_length( 3, 48.4862); - fanout_length( 4, 64.0974); - fanout_length( 5, 86.2649); - fanout_length( 6, 84.2649); - } - - - default_wire_load : "Small" ; - default_wire_load_mode : top; - - power_lut_template ("power_inputs_1") { - variable_1 : "input_transition_time"; - index_1("1, 2, 3, 4, 5, 6, 7"); - } - power_lut_template ("power_outputs_1") { - variable_1 : "input_transition_time"; - variable_2 : "total_output_net_capacitance"; - index_1("1, 2, 3, 4, 5, 6, 7"); - index_2("1, 2, 3, 4, 5, 6, 7"); - } - lu_table_template ("constraint_3_0_1") { - variable_1 : "related_pin_transition"; - index_1("1, 2, 3"); - } - lu_table_template ("del_1_7_7") { - variable_1 : "input_net_transition"; - variable_2 : "total_output_net_capacitance"; - index_1("1, 2, 3, 4, 5, 6, 7"); - index_2("1, 2, 3, 4, 5, 6, 7"); - } - lu_table_template ("driver_waveform_template") { - variable_1 : "input_net_transition"; - variable_2 : "normalized_voltage"; - index_1("1, 2"); - index_2("1, 2"); - } - lu_table_template ("vio_3_3_1") { - variable_1 : "related_pin_transition"; - variable_2 : "constrained_pin_transition"; - index_1("1, 2, 3"); - index_2("1, 2, 3"); - } - normalized_driver_waveform ("driver_waveform_template") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224745000, 0.2823108000, 0.5000000000, 0.6507428000, 1.5000000000"); - index_2("0.0000000000, 0.5000000000, 1.0000000000"); - driver_waveform_name : "ramp"; - values("0.0000000000, 0.0083333333, 0.0166666670", \ - "0.0000000000, 0.0192088180, 0.0384176350", \ - "0.0000000000, 0.0442774400, 0.0885548810", \ - "0.0000000000, 0.1020620700, 0.2041241500", \ - "0.0000000000, 0.2352590100, 0.4705180100", \ - "0.0000000000, 0.4166666700, 0.8333333300", \ - "0.0000000000, 0.5422856800, 1.0845714000", \ - "0.0000000000, 1.2500000000, 2.5000000000"); - } - library_features("report_delay_calculation"); - voltage_map("VSS", 0.0000000000); - voltage_map("KAPWR", 1.8000000000); - voltage_map("LOWLVPWR", 1.8000000000); - voltage_map("VGND", 0.0000000000); - voltage_map("VNB", 0.0000000000); - voltage_map("VPB", 1.8000000000); - voltage_map("VPWR", 1.8000000000); - voltage_map("VPWRIN", 1.8000000000); - driver_model : "ramp"; - in_place_swap_mode : "match_footprint"; - input_threshold_pct_fall : 50.000000000; - input_threshold_pct_rise : 50.000000000; - min_pulse_width_mode : "max"; - nom_process : 1.0000000000; - nom_temperature : 25.000000000; - nom_voltage : 1.8000000000; - output_threshold_pct_fall : 50.000000000; - output_threshold_pct_rise : 50.000000000; - simulation : "true"; - slew_derate_from_library : 1.0000000000; - slew_lower_threshold_pct_fall : 20.000000000; - slew_lower_threshold_pct_rise : 20.000000000; - slew_upper_threshold_pct_fall : 80.000000000; - slew_upper_threshold_pct_rise : 80.000000000; - switching_power_split_model : "true"; - - cell ("sky130_fd_sc_hd__a2111o_1") { - leakage_power () { - value : 0.0017945000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0105548000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004483000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0009140000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0004413000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0008205000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004191000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0004435000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0017945000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0110122000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004483000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0009140000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0004413000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0008205000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004191000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0004435000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0017945000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0108066000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004483000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0009140000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0004413000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0008205000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004191000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0004435000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0005702000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0020124000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004360000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0005442000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0004304000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0005403000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0004162000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0004352000; - when : "A1&A2&B1&C1&!D1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a2111o"; - cell_leakage_power : 0.0016750690; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046480000, 0.0046550000, 0.0046712000, 0.0046726000, 0.0046759000, 0.0046834000, 0.0047007000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003798300, -0.003799000, -0.003800600, -0.003794000, -0.003778800, -0.003743900, -0.003663400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025030000; - } - pin ("A2") { - capacitance : 0.0022890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039949000, 0.0039918000, 0.0039845000, 0.0039819000, 0.0039757000, 0.0039616000, 0.0039290000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003994500, -0.003992500, -0.003987700, -0.003988100, -0.003988900, -0.003990800, -0.003995100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023900000; - } - pin ("B1") { - capacitance : 0.0024100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041808000, 0.0041753000, 0.0041628000, 0.0041642000, 0.0041673000, 0.0041747000, 0.0041916000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003592600, -0.003620300, -0.003684100, -0.003699400, -0.003734800, -0.003816400, -0.004004400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025640000; - } - pin ("C1") { - capacitance : 0.0023750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038916000, 0.0038899000, 0.0038862000, 0.0038879000, 0.0038919000, 0.0039010000, 0.0039220000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003421000, -0.003506000, -0.003701800, -0.003707700, -0.003721300, -0.003752600, -0.003824800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025420000; - } - pin ("D1") { - capacitance : 0.0023470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026200000, 0.0026165000, 0.0026083000, 0.0026152000, 0.0026309000, 0.0026673000, 0.0027511000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001786200, -0.001790900, -0.001801700, -0.001800500, -0.001797600, -0.001791100, -0.001775900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1) | (D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0149448000, 0.0139985000, 0.0115268000, 0.0038442000, -0.019194400, -0.085157200, -0.262589100", \ - "0.0147160000, 0.0137918000, 0.0113018000, 0.0037331000, -0.019396600, -0.085299900, -0.262778400", \ - "0.0144236000, 0.0134912000, 0.0109864000, 0.0034834000, -0.019690600, -0.085629300, -0.263070800", \ - "0.0141531000, 0.0132663000, 0.0107662000, 0.0031863000, -0.019922000, -0.085836900, -0.263276000", \ - "0.0140122000, 0.0130803000, 0.0105792000, 0.0029654000, -0.020154400, -0.086031500, -0.263476000", \ - "0.0139266000, 0.0129691000, 0.0104978000, 0.0029385000, -0.020232200, -0.086190200, -0.263585100", \ - "0.0187978000, 0.0174192000, 0.0137610000, 0.0042739000, -0.020785300, -0.086252600, -0.263670200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0153500000, 0.0169853000, 0.0211357000, 0.0314025000, 0.0569639000, 0.1233940000, 0.3003729000", \ - "0.0152378000, 0.0168750000, 0.0210689000, 0.0312760000, 0.0568628000, 0.1239250000, 0.2986911000", \ - "0.0151158000, 0.0167507000, 0.0209164000, 0.0310910000, 0.0566883000, 0.1236972000, 0.2987928000", \ - "0.0150866000, 0.0166901000, 0.0207649000, 0.0307967000, 0.0564069000, 0.1233938000, 0.2985778000", \ - "0.0151123000, 0.0166682000, 0.0205879000, 0.0305136000, 0.0560457000, 0.1226545000, 0.2998661000", \ - "0.0163157000, 0.0176711000, 0.0212556000, 0.0304690000, 0.0559323000, 0.1222240000, 0.2998603000", \ - "0.0178701000, 0.0191675000, 0.0226900000, 0.0318558000, 0.0568748000, 0.1237405000, 0.2991926000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0177688000, 0.0168299000, 0.0142861000, 0.0066822000, -0.016319900, -0.082109800, -0.259423700", \ - "0.0176804000, 0.0167172000, 0.0142017000, 0.0066413000, -0.016408800, -0.082205800, -0.259522400", \ - "0.0175901000, 0.0166197000, 0.0140953000, 0.0064727000, -0.016549100, -0.082386900, -0.259720900", \ - "0.0173737000, 0.0164476000, 0.0138884000, 0.0063834000, -0.016683800, -0.082513100, -0.259856100", \ - "0.0172762000, 0.0163347000, 0.0137972000, 0.0061874000, -0.016859100, -0.082647900, -0.259941500", \ - "0.0172882000, 0.0163133000, 0.0137673000, 0.0061912000, -0.016884300, -0.082680400, -0.259993300", \ - "0.0222256000, 0.0208098000, 0.0172616000, 0.0077077000, -0.017407300, -0.082739000, -0.260040600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0154630000, 0.0171039000, 0.0212946000, 0.0314867000, 0.0570929000, 0.1241113000, 0.2991735000", \ - "0.0153715000, 0.0170041000, 0.0211497000, 0.0313910000, 0.0569623000, 0.1233660000, 0.3003458000", \ - "0.0152263000, 0.0168629000, 0.0210286000, 0.0312179000, 0.0568479000, 0.1238692000, 0.2989113000", \ - "0.0152516000, 0.0168509000, 0.0209523000, 0.0310704000, 0.0566701000, 0.1230209000, 0.2989175000", \ - "0.0153090000, 0.0168360000, 0.0208473000, 0.0308938000, 0.0564059000, 0.1235849000, 0.3000059000", \ - "0.0165996000, 0.0179311000, 0.0215319000, 0.0307623000, 0.0563253000, 0.1225837000, 0.2999410000", \ - "0.0177203000, 0.0190705000, 0.0227514000, 0.0319051000, 0.0568276000, 0.1236012000, 0.2981184000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0152325000, 0.0142988000, 0.0117558000, 0.0042041000, -0.018841500, -0.084629500, -0.261976400", \ - "0.0150779000, 0.0141426000, 0.0116163000, 0.0040504000, -0.018999900, -0.084791600, -0.262141100", \ - "0.0148576000, 0.0140208000, 0.0113858000, 0.0038932000, -0.019182100, -0.084994700, -0.262357000", \ - "0.0147100000, 0.0137563000, 0.0112714000, 0.0035870000, -0.019378500, -0.085169100, -0.262502100", \ - "0.0145976000, 0.0136425000, 0.0110788000, 0.0035609000, -0.019540400, -0.085320100, -0.262668100", \ - "0.0145563000, 0.0135616000, 0.0111124000, 0.0034657000, -0.019647000, -0.085444000, -0.262746200", \ - "0.0192461000, 0.0177695000, 0.0140674000, 0.0045185000, -0.020161700, -0.085581300, -0.262812600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0136037000, 0.0151354000, 0.0190044000, 0.0287797000, 0.0541618000, 0.1202089000, 0.2956793000", \ - "0.0136124000, 0.0151408000, 0.0190153000, 0.0287982000, 0.0539343000, 0.1206643000, 0.2970734000", \ - "0.0136595000, 0.0151735000, 0.0190036000, 0.0287632000, 0.0539043000, 0.1200105000, 0.2970331000", \ - "0.0135001000, 0.0149856000, 0.0187653000, 0.0284921000, 0.0536734000, 0.1205940000, 0.2954956000", \ - "0.0136467000, 0.0149833000, 0.0186257000, 0.0282559000, 0.0534121000, 0.1197658000, 0.2967698000", \ - "0.0142192000, 0.0155130000, 0.0191179000, 0.0285716000, 0.0536785000, 0.1195655000, 0.2968778000", \ - "0.0154766000, 0.0167674000, 0.0202604000, 0.0297396000, 0.0547390000, 0.1211301000, 0.2965006000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0131315000, 0.0121536000, 0.0096917000, 0.0019803000, -0.020947100, -0.086742900, -0.264127900", \ - "0.0129489000, 0.0120088000, 0.0095430000, 0.0019071000, -0.021145700, -0.086931500, -0.264289200", \ - "0.0127408000, 0.0118048000, 0.0092526000, 0.0017947000, -0.021313400, -0.087160500, -0.264489300", \ - "0.0126146000, 0.0116513000, 0.0091059000, 0.0015122000, -0.021503100, -0.087334800, -0.264656100", \ - "0.0124613000, 0.0115069000, 0.0089404000, 0.0014199000, -0.021668000, -0.087453000, -0.264800600", \ - "0.0124760000, 0.0114395000, 0.0089030000, 0.0012695000, -0.021829400, -0.087623200, -0.264909400", \ - "0.0175837000, 0.0160903000, 0.0123658000, 0.0027698000, -0.022078400, -0.087111400, -0.264542300"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0124139000, 0.0138752000, 0.0176428000, 0.0272907000, 0.0525966000, 0.1190191000, 0.2951986000", \ - "0.0124985000, 0.0139573000, 0.0177238000, 0.0273553000, 0.0524772000, 0.1185900000, 0.2940638000", \ - "0.0126462000, 0.0140932000, 0.0178367000, 0.0274606000, 0.0527777000, 0.1186275000, 0.2941056000", \ - "0.0124771000, 0.0138953000, 0.0176038000, 0.0272050000, 0.0523594000, 0.1185878000, 0.2941119000", \ - "0.0125711000, 0.0139316000, 0.0174439000, 0.0269914000, 0.0520705000, 0.1183376000, 0.2954959000", \ - "0.0126989000, 0.0140337000, 0.0176523000, 0.0271154000, 0.0521863000, 0.1185945000, 0.2937155000", \ - "0.0140074000, 0.0152955000, 0.0188319000, 0.0282826000, 0.0532835000, 0.1197277000, 0.2951247000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0123280000, 0.0113958000, 0.0089248000, 0.0013077000, -0.021766100, -0.087546400, -0.264890200", \ - "0.0121448000, 0.0111997000, 0.0086070000, 0.0010978000, -0.021962500, -0.087771300, -0.265104700", \ - "0.0119034000, 0.0108622000, 0.0084087000, 0.0008656000, -0.022237100, -0.088031300, -0.265335500", \ - "0.0116971000, 0.0107253000, 0.0082544000, 0.0006750000, -0.022372100, -0.088202600, -0.265520900", \ - "0.0115932000, 0.0106289000, 0.0081730000, 0.0005774000, -0.022508200, -0.088327100, -0.265625100", \ - "0.0124448000, 0.0118229000, 0.0091170000, 0.0013446000, -0.021814300, -0.087703700, -0.264998000", \ - "0.0188575000, 0.0173199000, 0.0135229000, 0.0038920000, -0.021406800, -0.086906400, -0.264171700"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013283360, 0.0035289520, 0.0093752650, 0.0249070000, 0.0661697100, 0.1757912000"); - values("0.0092569000, 0.0106562000, 0.0142655000, 0.0236749000, 0.0484970000, 0.1151158000, 0.2916287000", \ - "0.0092100000, 0.0106089000, 0.0142243000, 0.0236517000, 0.0485061000, 0.1151554000, 0.2918199000", \ - "0.0090807000, 0.0104672000, 0.0140958000, 0.0235515000, 0.0484841000, 0.1151469000, 0.2915644000", \ - "0.0088955000, 0.0102629000, 0.0138917000, 0.0233576000, 0.0483960000, 0.1151090000, 0.2908169000", \ - "0.0089571000, 0.0103281000, 0.0137447000, 0.0232338000, 0.0482307000, 0.1149365000, 0.2900442000", \ - "0.0091280000, 0.0104505000, 0.0140455000, 0.0235072000, 0.0484072000, 0.1145972000, 0.2914875000", \ - "0.0105622000, 0.0118417000, 0.0153279000, 0.0247776000, 0.0497260000, 0.1160993000, 0.2896132000"); - } - } - max_capacitance : 0.1757910000; - max_transition : 1.4999410000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.3190903000, 0.3289237000, 0.3495668000, 0.3895317000, 0.4648215000, 0.6163044000, 0.9633411000", \ - "0.3223206000, 0.3320963000, 0.3527997000, 0.3926703000, 0.4680527000, 0.6195656000, 0.9665978000", \ - "0.3323149000, 0.3421001000, 0.3625892000, 0.4023682000, 0.4776523000, 0.6293935000, 0.9767384000", \ - "0.3590631000, 0.3690398000, 0.3895445000, 0.4290070000, 0.5047419000, 0.6564694000, 1.0037350000", \ - "0.4177338000, 0.4274977000, 0.4480879000, 0.4875928000, 0.5633634000, 0.7149081000, 1.0622273000", \ - "0.5324310000, 0.5425175000, 0.5631512000, 0.6035358000, 0.6794277000, 0.8312054000, 1.1787290000", \ - "0.7254669000, 0.7366381000, 0.7595250000, 0.8035871000, 0.8850058000, 1.0440845000, 1.3957675000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0840835000, 0.0917357000, 0.1092000000, 0.1489394000, 0.2451822000, 0.4920672000, 1.1405393000", \ - "0.0882820000, 0.0959815000, 0.1134185000, 0.1530318000, 0.2492248000, 0.4960878000, 1.1430674000", \ - "0.0989385000, 0.1065995000, 0.1239122000, 0.1633020000, 0.2595427000, 0.5061135000, 1.1528150000", \ - "0.1243474000, 0.1317477000, 0.1486583000, 0.1875383000, 0.2833339000, 0.5298310000, 1.1770668000", \ - "0.1669113000, 0.1746878000, 0.1910878000, 0.2299491000, 0.3260064000, 0.5718119000, 1.2212958000", \ - "0.2187389000, 0.2278396000, 0.2464123000, 0.2849220000, 0.3800726000, 0.6263021000, 1.2752830000", \ - "0.2571726000, 0.2688372000, 0.2919402000, 0.3352114000, 0.4300004000, 0.6760532000, 1.3235429000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0390692000, 0.0458549000, 0.0611797000, 0.0907273000, 0.1569962000, 0.3131986000, 0.7382486000", \ - "0.0388887000, 0.0460319000, 0.0604493000, 0.0906267000, 0.1572972000, 0.3123424000, 0.7388531000", \ - "0.0389358000, 0.0457867000, 0.0601718000, 0.0911997000, 0.1573085000, 0.3143655000, 0.7372823000", \ - "0.0390684000, 0.0456704000, 0.0601646000, 0.0908330000, 0.1578590000, 0.3121484000, 0.7387103000", \ - "0.0389255000, 0.0459988000, 0.0602284000, 0.0908982000, 0.1559452000, 0.3123069000, 0.7389503000", \ - "0.0407768000, 0.0473649000, 0.0620398000, 0.0933479000, 0.1590979000, 0.3147353000, 0.7387339000", \ - "0.0465345000, 0.0538740000, 0.0693723000, 0.1020898000, 0.1697786000, 0.3250598000, 0.7440078000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0254432000, 0.0325754000, 0.0506950000, 0.0986632000, 0.2281000000, 0.5721540000, 1.4932626000", \ - "0.0252966000, 0.0325427000, 0.0505642000, 0.0985849000, 0.2278359000, 0.5734720000, 1.4946276000", \ - "0.0250476000, 0.0322104000, 0.0504140000, 0.0984678000, 0.2272414000, 0.5727883000, 1.4930922000", \ - "0.0247733000, 0.0317673000, 0.0496484000, 0.0978288000, 0.2268608000, 0.5718572000, 1.4914934000", \ - "0.0274668000, 0.0340614000, 0.0517402000, 0.0980554000, 0.2263613000, 0.5728195000, 1.4956867000", \ - "0.0338409000, 0.0405761000, 0.0560270000, 0.1003293000, 0.2273714000, 0.5715604000, 1.4940440000", \ - "0.0460458000, 0.0533903000, 0.0687767000, 0.1081061000, 0.2281990000, 0.5747279000, 1.4899872000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.3594698000, 0.3699910000, 0.3915546000, 0.4328507000, 0.5098555000, 0.6635300000, 1.0128205000", \ - "0.3636545000, 0.3743708000, 0.3958643000, 0.4370524000, 0.5141900000, 0.6678380000, 1.0171159000", \ - "0.3753173000, 0.3858758000, 0.4075253000, 0.4487970000, 0.5263114000, 0.6798122000, 1.0289715000", \ - "0.4020018000, 0.4125417000, 0.4338126000, 0.4750526000, 0.5523861000, 0.7061842000, 1.0551442000", \ - "0.4561451000, 0.4666785000, 0.4882129000, 0.5289315000, 0.6065682000, 0.7602695000, 1.1095891000", \ - "0.5608755000, 0.5714728000, 0.5933402000, 0.6349001000, 0.7119150000, 0.8658510000, 1.2151277000", \ - "0.7354117000, 0.7467312000, 0.7706528000, 0.8152184000, 0.8978202000, 1.0574788000, 1.4101745000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0880244000, 0.0957497000, 0.1132034000, 0.1528188000, 0.2491312000, 0.4957934000, 1.1416508000", \ - "0.0925671000, 0.1001869000, 0.1175902000, 0.1572370000, 0.2534390000, 0.5002936000, 1.1487200000", \ - "0.1023329000, 0.1099951000, 0.1273375000, 0.1668649000, 0.2628900000, 0.5097833000, 1.1558240000", \ - "0.1251233000, 0.1325927000, 0.1495871000, 0.1885837000, 0.2846892000, 0.5304560000, 1.1788474000", \ - "0.1667573000, 0.1744005000, 0.1917440000, 0.2307170000, 0.3262182000, 0.5729252000, 1.2212653000", \ - "0.2244172000, 0.2333881000, 0.2521549000, 0.2920185000, 0.3871029000, 0.6330495000, 1.2827108000", \ - "0.2818188000, 0.2933477000, 0.3159933000, 0.3591409000, 0.4547244000, 0.7007356000, 1.3472924000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0438708000, 0.0507399000, 0.0642989000, 0.0957662000, 0.1600051000, 0.3175413000, 0.7422614000", \ - "0.0436301000, 0.0502523000, 0.0645974000, 0.0958646000, 0.1602365000, 0.3175310000, 0.7427852000", \ - "0.0430019000, 0.0498861000, 0.0642083000, 0.0947925000, 0.1605816000, 0.3169968000, 0.7426369000", \ - "0.0430142000, 0.0501154000, 0.0646604000, 0.0957839000, 0.1611015000, 0.3162888000, 0.7415919000", \ - "0.0437022000, 0.0506768000, 0.0643164000, 0.0951563000, 0.1596460000, 0.3177603000, 0.7395570000", \ - "0.0442002000, 0.0509747000, 0.0651941000, 0.0956620000, 0.1605663000, 0.3179341000, 0.7424278000", \ - "0.0504117000, 0.0573907000, 0.0741602000, 0.1043977000, 0.1706796000, 0.3264520000, 0.7457623000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0253370000, 0.0325569000, 0.0506810000, 0.0987801000, 0.2274845000, 0.5733150000, 1.4946702000", \ - "0.0252911000, 0.0324111000, 0.0505358000, 0.0985369000, 0.2280276000, 0.5722391000, 1.4927543000", \ - "0.0251010000, 0.0322888000, 0.0504267000, 0.0984950000, 0.2278604000, 0.5734477000, 1.4949251000", \ - "0.0249341000, 0.0320615000, 0.0500063000, 0.0980978000, 0.2277742000, 0.5726755000, 1.4909479000", \ - "0.0271800000, 0.0342408000, 0.0514140000, 0.0979232000, 0.2269928000, 0.5722665000, 1.4925735000", \ - "0.0329031000, 0.0394216000, 0.0559004000, 0.1002220000, 0.2270916000, 0.5724417000, 1.4956580000", \ - "0.0434918000, 0.0510931000, 0.0676624000, 0.1080043000, 0.2288458000, 0.5738863000, 1.4926184000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.3393341000, 0.3498677000, 0.3714714000, 0.4128207000, 0.4898030000, 0.6434701000, 0.9927731000", \ - "0.3417429000, 0.3522357000, 0.3739633000, 0.4151378000, 0.4921604000, 0.6458582000, 0.9951169000", \ - "0.3510458000, 0.3614695000, 0.3830864000, 0.4240720000, 0.5013865000, 0.6552513000, 1.0044376000", \ - "0.3761652000, 0.3865262000, 0.4082083000, 0.4494436000, 0.5263351000, 0.6800285000, 1.0292270000", \ - "0.4326281000, 0.4433414000, 0.4647781000, 0.5056752000, 0.5832019000, 0.7368999000, 1.0861703000", \ - "0.5536628000, 0.5643304000, 0.5862446000, 0.6280919000, 0.7052632000, 0.8591741000, 1.2084369000", \ - "0.7741325000, 0.7860201000, 0.8107316000, 0.8568278000, 0.9412007000, 1.1024732000, 1.4563075000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0636804000, 0.0702286000, 0.0854631000, 0.1220142000, 0.2152184000, 0.4587050000, 1.1044814000", \ - "0.0684957000, 0.0750651000, 0.0902833000, 0.1268027000, 0.2196850000, 0.4640861000, 1.1113639000", \ - "0.0798744000, 0.0863642000, 0.1014471000, 0.1378466000, 0.2307515000, 0.4751651000, 1.1226310000", \ - "0.1042312000, 0.1107012000, 0.1256886000, 0.1618500000, 0.2551892000, 0.4991096000, 1.1437774000", \ - "0.1388102000, 0.1461107000, 0.1619729000, 0.1984673000, 0.2913217000, 0.5355452000, 1.1841924000", \ - "0.1742402000, 0.1833706000, 0.2020458000, 0.2399973000, 0.3330112000, 0.5767720000, 1.2250434000", \ - "0.1871855000, 0.1994102000, 0.2237630000, 0.2678604000, 0.3616296000, 0.6062204000, 1.2511664000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0437775000, 0.0507887000, 0.0645389000, 0.0957586000, 0.1614305000, 0.3175049000, 0.7427157000", \ - "0.0437038000, 0.0507091000, 0.0647523000, 0.0945574000, 0.1614945000, 0.3174732000, 0.7433115000", \ - "0.0430285000, 0.0502587000, 0.0643410000, 0.0961732000, 0.1611690000, 0.3176947000, 0.7398721000", \ - "0.0430522000, 0.0497144000, 0.0652657000, 0.0945576000, 0.1614348000, 0.3172590000, 0.7432553000", \ - "0.0434596000, 0.0502163000, 0.0643508000, 0.0961523000, 0.1619920000, 0.3181203000, 0.7404354000", \ - "0.0455721000, 0.0520366000, 0.0662925000, 0.0972447000, 0.1626215000, 0.3182720000, 0.7423014000", \ - "0.0539693000, 0.0609033000, 0.0778256000, 0.1081410000, 0.1753711000, 0.3279352000, 0.7441815000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0210657000, 0.0275411000, 0.0448885000, 0.0927056000, 0.2229618000, 0.5681204000, 1.4929451000", \ - "0.0210419000, 0.0275286000, 0.0449262000, 0.0927037000, 0.2224762000, 0.5691120000, 1.4940214000", \ - "0.0208809000, 0.0273894000, 0.0448075000, 0.0926644000, 0.2223974000, 0.5694518000, 1.4935460000", \ - "0.0216975000, 0.0278821000, 0.0449000000, 0.0923978000, 0.2223780000, 0.5694746000, 1.4886246000", \ - "0.0261871000, 0.0320026000, 0.0476385000, 0.0935079000, 0.2227658000, 0.5701083000, 1.4915755000", \ - "0.0351052000, 0.0405499000, 0.0549873000, 0.0968749000, 0.2233602000, 0.5679143000, 1.4940095000", \ - "0.0482355000, 0.0551261000, 0.0701301000, 0.1079765000, 0.2261601000, 0.5714155000, 1.4894329000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.3011523000, 0.3115468000, 0.3332296000, 0.3745168000, 0.4511412000, 0.6049143000, 0.9539955000", \ - "0.3033876000, 0.3137829000, 0.3354221000, 0.3768289000, 0.4542033000, 0.6070895000, 0.9560340000", \ - "0.3119252000, 0.3225163000, 0.3440170000, 0.3848583000, 0.4624144000, 0.6161989000, 0.9652688000", \ - "0.3359958000, 0.3464662000, 0.3680553000, 0.4094126000, 0.4868986000, 0.6404866000, 0.9896872000", \ - "0.3936973000, 0.4044269000, 0.4258908000, 0.4669254000, 0.5442725000, 0.6980646000, 1.0472715000", \ - "0.5249393000, 0.5356697000, 0.5577225000, 0.5996074000, 0.6775812000, 0.8317315000, 1.1811114000", \ - "0.7650701000, 0.7773504000, 0.8031371000, 0.8496877000, 0.9341286000, 1.0925684000, 1.4465286000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0602701000, 0.0666016000, 0.0813854000, 0.1172064000, 0.2097006000, 0.4537443000, 1.1012151000", \ - "0.0651033000, 0.0714248000, 0.0861847000, 0.1220496000, 0.2143847000, 0.4577487000, 1.1033011000", \ - "0.0762066000, 0.0824837000, 0.0971569000, 0.1329918000, 0.2257849000, 0.4687789000, 1.1147419000", \ - "0.0990028000, 0.1053889000, 0.1201538000, 0.1559731000, 0.2483493000, 0.4922118000, 1.1383721000", \ - "0.1295375000, 0.1368108000, 0.1525907000, 0.1888009000, 0.2812161000, 0.5252799000, 1.1712337000", \ - "0.1582018000, 0.1677070000, 0.1864661000, 0.2245319000, 0.3171472000, 0.5608062000, 1.2071658000", \ - "0.1590991000, 0.1717613000, 0.1967573000, 0.2417342000, 0.3354891000, 0.5796997000, 1.2249126000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0432811000, 0.0497532000, 0.0654149000, 0.0945718000, 0.1610237000, 0.3166531000, 0.7438703000", \ - "0.0430168000, 0.0497754000, 0.0654591000, 0.0946862000, 0.1595373000, 0.3161698000, 0.7427433000", \ - "0.0431449000, 0.0501829000, 0.0642839000, 0.0951441000, 0.1614036000, 0.3165402000, 0.7413028000", \ - "0.0431803000, 0.0498549000, 0.0642295000, 0.0948111000, 0.1609677000, 0.3172239000, 0.7426638000", \ - "0.0433990000, 0.0501725000, 0.0643075000, 0.0954885000, 0.1611962000, 0.3177330000, 0.7411498000", \ - "0.0459210000, 0.0527959000, 0.0672237000, 0.0964296000, 0.1625705000, 0.3181032000, 0.7423723000", \ - "0.0582208000, 0.0658259000, 0.0801414000, 0.1109312000, 0.1752642000, 0.3288714000, 0.7462974000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0200969000, 0.0264554000, 0.0437325000, 0.0915487000, 0.2224807000, 0.5698914000, 1.4919915000", \ - "0.0200713000, 0.0264505000, 0.0436950000, 0.0916467000, 0.2223056000, 0.5693364000, 1.4906854000", \ - "0.0200495000, 0.0264587000, 0.0437539000, 0.0914765000, 0.2219544000, 0.5697729000, 1.4944505000", \ - "0.0213702000, 0.0274396000, 0.0442047000, 0.0916843000, 0.2221821000, 0.5700579000, 1.4937632000", \ - "0.0261287000, 0.0317806000, 0.0472286000, 0.0929114000, 0.2217534000, 0.5700935000, 1.4942241000", \ - "0.0355943000, 0.0412962000, 0.0553871000, 0.0966399000, 0.2231374000, 0.5678676000, 1.4930703000", \ - "0.0497108000, 0.0568038000, 0.0723863000, 0.1094207000, 0.2261709000, 0.5720945000, 1.4877709000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.2473589000, 0.2578767000, 0.2795370000, 0.3209178000, 0.3979260000, 0.5516649000, 0.9009031000", \ - "0.2485475000, 0.2589751000, 0.2805662000, 0.3216066000, 0.3989378000, 0.5530332000, 0.9021137000", \ - "0.2546061000, 0.2648829000, 0.2864597000, 0.3277259000, 0.4051399000, 0.5588892000, 0.9081983000", \ - "0.2778454000, 0.2881622000, 0.3097453000, 0.3511371000, 0.4285267000, 0.5819825000, 0.9310154000", \ - "0.3367872000, 0.3472485000, 0.3687806000, 0.4099680000, 0.4874922000, 0.6410074000, 0.9900076000", \ - "0.4787370000, 0.4893705000, 0.5110559000, 0.5519556000, 0.6289129000, 0.7825909000, 1.1316854000", \ - "0.7192442000, 0.7318585000, 0.7585345000, 0.8047458000, 0.8852681000, 1.0415516000, 1.3958803000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0535721000, 0.0596494000, 0.0738941000, 0.1088234000, 0.2001901000, 0.4439459000, 1.0945471000", \ - "0.0583437000, 0.0644130000, 0.0786526000, 0.1137599000, 0.2053974000, 0.4486207000, 1.0967097000", \ - "0.0692800000, 0.0753079000, 0.0895226000, 0.1247745000, 0.2167038000, 0.4602358000, 1.1118598000", \ - "0.0897087000, 0.0960593000, 0.1106440000, 0.1459227000, 0.2382114000, 0.4811504000, 1.1297338000", \ - "0.1150310000, 0.1224717000, 0.1382904000, 0.1742716000, 0.2662983000, 0.5106973000, 1.1551733000", \ - "0.1352070000, 0.1452878000, 0.1646696000, 0.2030699000, 0.2951973000, 0.5385046000, 1.1866097000", \ - "0.1239338000, 0.1372535000, 0.1636653000, 0.2100409000, 0.3044862000, 0.5469789000, 1.1928603000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0429595000, 0.0496558000, 0.0653937000, 0.0946086000, 0.1599681000, 0.3173342000, 0.7433879000", \ - "0.0432642000, 0.0505936000, 0.0643092000, 0.0957585000, 0.1613658000, 0.3163494000, 0.7412822000", \ - "0.0432018000, 0.0501548000, 0.0647752000, 0.0954436000, 0.1595072000, 0.3174440000, 0.7414550000", \ - "0.0432442000, 0.0498363000, 0.0645903000, 0.0951084000, 0.1605607000, 0.3161500000, 0.7409089000", \ - "0.0427671000, 0.0493969000, 0.0649966000, 0.0956289000, 0.1616674000, 0.3164569000, 0.7415055000", \ - "0.0466531000, 0.0533440000, 0.0665588000, 0.0959869000, 0.1621598000, 0.3162744000, 0.7416454000", \ - "0.0623616000, 0.0692327000, 0.0838778000, 0.1109674000, 0.1714782000, 0.3257857000, 0.7470813000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013283400, 0.0035289500, 0.0093752600, 0.0249070000, 0.0661697000, 0.1757910000"); - values("0.0193710000, 0.0257544000, 0.0430966000, 0.0911177000, 0.2218338000, 0.5707849000, 1.4998913000", \ - "0.0193748000, 0.0257785000, 0.0430416000, 0.0911081000, 0.2214844000, 0.5705008000, 1.4999412000", \ - "0.0195016000, 0.0258628000, 0.0431215000, 0.0911922000, 0.2216915000, 0.5710344000, 1.4998575000", \ - "0.0216109000, 0.0275779000, 0.0440799000, 0.0911708000, 0.2217520000, 0.5712891000, 1.4970206000", \ - "0.0272298000, 0.0326565000, 0.0476733000, 0.0928503000, 0.2215701000, 0.5704672000, 1.4925718000", \ - "0.0377072000, 0.0436114000, 0.0574321000, 0.0973387000, 0.2226521000, 0.5670922000, 1.4942881000", \ - "0.0536088000, 0.0610433000, 0.0763432000, 0.1126354000, 0.2266385000, 0.5732466000, 1.4889554000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111o_2") { - leakage_power () { - value : 0.0021893000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0093488000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0009247000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0013982000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0009175000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0013030000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0008951000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0009198000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0021893000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0098256000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0009247000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0013982000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0009175000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0013030000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0008951000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0009198000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0021894000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0096205000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0009247000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0013982000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0009175000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0013030000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0008951000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0009198000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0010558000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0026066000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0009145000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0010283000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0009085000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0010235000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0008939000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0009118000; - when : "A1&A2&B1&C1&!D1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__a2111o"; - cell_leakage_power : 0.0019931500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045623000, 0.0045609000, 0.0045576000, 0.0045568000, 0.0045549000, 0.0045506000, 0.0045407000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003503400, -0.003507500, -0.003516800, -0.003508400, -0.003489100, -0.003444500, -0.003341700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025580000; - } - pin ("A2") { - capacitance : 0.0023940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040955000, 0.0040975000, 0.0041022000, 0.0041044000, 0.0041096000, 0.0041215000, 0.0041489000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004095600, -0.004093400, -0.004088500, -0.004090400, -0.004094600, -0.004104300, -0.004126800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025000000; - } - pin ("B1") { - capacitance : 0.0023330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038545000, 0.0038513000, 0.0038440000, 0.0038451000, 0.0038476000, 0.0038534000, 0.0038669000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003255300, -0.003289000, -0.003366800, -0.003382700, -0.003419500, -0.003504300, -0.003699800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024780000; - } - pin ("C1") { - capacitance : 0.0024560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038798000, 0.0038800000, 0.0038805000, 0.0038787000, 0.0038745000, 0.0038650000, 0.0038430000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003398500, -0.003486000, -0.003687900, -0.003693800, -0.003707300, -0.003738500, -0.003810300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026210000; - } - pin ("D1") { - capacitance : 0.0024250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025480000, 0.0025452000, 0.0025388000, 0.0025460000, 0.0025627000, 0.0026012000, 0.0026898000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001782000, -0.001785600, -0.001793900, -0.001795100, -0.001798000, -0.001804700, -0.001820000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026360000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1) | (D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0175895000, 0.0158676000, 0.0117819000, 3.820000e-05, -0.036712700, -0.152252300, -0.498309400", \ - "0.0173684000, 0.0156923000, 0.0116244000, 3.360000e-05, -0.036874300, -0.152442000, -0.498426900", \ - "0.0171390000, 0.0154426000, 0.0114644000, -0.000210900, -0.037183100, -0.152608900, -0.498731400", \ - "0.0169597000, 0.0152000000, 0.0112480000, -0.000437100, -0.037398200, -0.152953800, -0.498972200", \ - "0.0167926000, 0.0150960000, 0.0109933000, -0.000697300, -0.037645600, -0.153155800, -0.499192800", \ - "0.0168538000, 0.0151489000, 0.0109929000, -0.000795200, -0.037743400, -0.153312200, -0.499306600", \ - "0.0221465000, 0.0202586000, 0.0151715000, 0.0013030000, -0.038313000, -0.153355700, -0.499325500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0200553000, 0.0218436000, 0.0269826000, 0.0415391000, 0.0822400000, 0.1992925000, 0.5416241000", \ - "0.0199275000, 0.0216981000, 0.0268961000, 0.0414617000, 0.0821325000, 0.1992412000, 0.5418606000", \ - "0.0197869000, 0.0215853000, 0.0267458000, 0.0412731000, 0.0820155000, 0.1996551000, 0.5440988000", \ - "0.0198480000, 0.0215911000, 0.0267458000, 0.0411729000, 0.0816822000, 0.1988550000, 0.5416093000", \ - "0.0199121000, 0.0215933000, 0.0266357000, 0.0407885000, 0.0812491000, 0.1985318000, 0.5414044000", \ - "0.0213450000, 0.0228834000, 0.0275142000, 0.0409337000, 0.0806395000, 0.1976097000, 0.5402076000", \ - "0.0232385000, 0.0247265000, 0.0291767000, 0.0427054000, 0.0820477000, 0.1992730000, 0.5421347000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0209735000, 0.0192750000, 0.0150178000, 0.0032433000, -0.033704000, -0.149127700, -0.495054300", \ - "0.0207270000, 0.0190055000, 0.0150532000, 0.0031944000, -0.033793300, -0.149195900, -0.495136100", \ - "0.0205949000, 0.0190147000, 0.0146986000, 0.0028649000, -0.033867400, -0.149324300, -0.495265000", \ - "0.0205013000, 0.0187443000, 0.0145420000, 0.0027809000, -0.034124700, -0.149473300, -0.495342100", \ - "0.0204141000, 0.0186981000, 0.0145000000, 0.0027078000, -0.034247800, -0.149643800, -0.495519000", \ - "0.0205511000, 0.0187809000, 0.0145338000, 0.0026701000, -0.034278900, -0.149742200, -0.495628800", \ - "0.0258199000, 0.0239159000, 0.0187623000, 0.0047276000, -0.034840500, -0.149822900, -0.495700800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0204730000, 0.0222787000, 0.0274004000, 0.0419904000, 0.0826897000, 0.1995910000, 0.5417232000", \ - "0.0203463000, 0.0221266000, 0.0273260000, 0.0418962000, 0.0825270000, 0.1997103000, 0.5427387000", \ - "0.0202188000, 0.0220026000, 0.0271407000, 0.0417475000, 0.0823961000, 0.1994208000, 0.5418991000", \ - "0.0202261000, 0.0220051000, 0.0271655000, 0.0416155000, 0.0822512000, 0.1991828000, 0.5442334000", \ - "0.0203847000, 0.0221202000, 0.0271713000, 0.0414561000, 0.0818676000, 0.1992147000, 0.5417660000", \ - "0.0216734000, 0.0232452000, 0.0278759000, 0.0414805000, 0.0816898000, 0.1985927000, 0.5409699000", \ - "0.0233985000, 0.0248922000, 0.0293642000, 0.0428966000, 0.0828560000, 0.1997257000, 0.5410491000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0184993000, 0.0167684000, 0.0125626000, 0.0009522000, -0.035975900, -0.151431700, -0.497354300", \ - "0.0185150000, 0.0167981000, 0.0125541000, 0.0008786000, -0.036164200, -0.151562800, -0.497503800", \ - "0.0182310000, 0.0164631000, 0.0122769000, 0.0005292000, -0.036397800, -0.151734000, -0.497611600", \ - "0.0179864000, 0.0162575000, 0.0120672000, 0.0003103000, -0.036488600, -0.151960000, -0.497873600", \ - "0.0178809000, 0.0161521000, 0.0119664000, 0.0001525000, -0.036741300, -0.152094200, -0.498016200", \ - "0.0179581000, 0.0162168000, 0.0119354000, 0.0002101000, -0.036857600, -0.152300400, -0.498130300", \ - "0.0225252000, 0.0205951000, 0.0153827000, 0.0012780000, -0.037279500, -0.152421200, -0.498237700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0185539000, 0.0203005000, 0.0253611000, 0.0394691000, 0.0797368000, 0.1963160000, 0.5406157000", \ - "0.0185906000, 0.0203366000, 0.0253797000, 0.0395065000, 0.0797068000, 0.1965762000, 0.5406738000", \ - "0.0185976000, 0.0203418000, 0.0253693000, 0.0394511000, 0.0796902000, 0.1964688000, 0.5381626000", \ - "0.0185396000, 0.0202393000, 0.0251943000, 0.0391838000, 0.0794330000, 0.1962605000, 0.5381023000", \ - "0.0186700000, 0.0202899000, 0.0250756000, 0.0389761000, 0.0790524000, 0.1960198000, 0.5376181000", \ - "0.0194328000, 0.0209885000, 0.0257383000, 0.0392882000, 0.0790473000, 0.1952459000, 0.5400221000", \ - "0.0211181000, 0.0225345000, 0.0269973000, 0.0406611000, 0.0804002000, 0.1973430000, 0.5396810000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0165880000, 0.0148491000, 0.0107269000, -0.001081200, -0.038122500, -0.153551500, -0.499461700", \ - "0.0165239000, 0.0147996000, 0.0105997000, -0.001208200, -0.038244900, -0.153659900, -0.499598800", \ - "0.0160769000, 0.0145929000, 0.0104521000, -0.001408300, -0.038441300, -0.153819700, -0.499787100", \ - "0.0158760000, 0.0141230000, 0.0100008000, -0.001813300, -0.038741100, -0.153931000, -0.499923100", \ - "0.0157950000, 0.0141370000, 0.0099127000, -0.001863800, -0.038838600, -0.154226000, -0.500076100", \ - "0.0158139000, 0.0140417000, 0.0097842000, -0.001641300, -0.038917000, -0.154387100, -0.500242400", \ - "0.0219222000, 0.0198741000, 0.0138108000, -0.000400100, -0.039150100, -0.153495600, -0.499754200"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0173441000, 0.0190814000, 0.0240474000, 0.0380302000, 0.0781054000, 0.1954299000, 0.5373996000", \ - "0.0174309000, 0.0191636000, 0.0241297000, 0.0381422000, 0.0782513000, 0.1947449000, 0.5377639000", \ - "0.0176145000, 0.0193320000, 0.0242780000, 0.0382502000, 0.0783625000, 0.1948858000, 0.5379096000", \ - "0.0175046000, 0.0191886000, 0.0240498000, 0.0379629000, 0.0781313000, 0.1950939000, 0.5397139000", \ - "0.0177412000, 0.0192970000, 0.0239552000, 0.0377816000, 0.0776898000, 0.1943747000, 0.5375334000", \ - "0.0180736000, 0.0196318000, 0.0242573000, 0.0379439000, 0.0776464000, 0.1935123000, 0.5366031000", \ - "0.0196946000, 0.0211759000, 0.0256112000, 0.0391788000, 0.0789711000, 0.1956621000, 0.5359274000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0156807000, 0.0139580000, 0.0097915000, -0.001962300, -0.038896200, -0.154284500, -0.500140000", \ - "0.0155232000, 0.0138119000, 0.0095966000, -0.002145900, -0.039049800, -0.154456000, -0.500405300", \ - "0.0152178000, 0.0134900000, 0.0093566000, -0.002405300, -0.039324600, -0.154712500, -0.500627400", \ - "0.0150558000, 0.0133353000, 0.0091361000, -0.002614500, -0.039527800, -0.154867600, -0.500838800", \ - "0.0149137000, 0.0131900000, 0.0089128000, -0.002744700, -0.039685900, -0.155035100, -0.500965200", \ - "0.0154331000, 0.0136896000, 0.0094892000, -0.002390700, -0.039013200, -0.154515500, -0.500399000", \ - "0.0228940000, 0.0208968000, 0.0155589000, 0.0012543000, -0.038604300, -0.153893400, -0.499647000"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014709220, 0.0043272230, 0.0127300100, 0.0374497200, 0.1101712000, 0.3241066000"); - values("0.0143207000, 0.0160273000, 0.0209077000, 0.0347754000, 0.0746000000, 0.1912298000, 0.5363846000", \ - "0.0142967000, 0.0160192000, 0.0209041000, 0.0347471000, 0.0745882000, 0.1912948000, 0.5339048000", \ - "0.0142338000, 0.0159464000, 0.0208070000, 0.0346349000, 0.0745383000, 0.1912576000, 0.5343066000", \ - "0.0140928000, 0.0157467000, 0.0205668000, 0.0343256000, 0.0742799000, 0.1912131000, 0.5317370000", \ - "0.0143317000, 0.0159093000, 0.0204723000, 0.0341415000, 0.0739202000, 0.1907577000, 0.5311908000", \ - "0.0146063000, 0.0161450000, 0.0207587000, 0.0344607000, 0.0739745000, 0.1900216000, 0.5356314000", \ - "0.0163034000, 0.0177501000, 0.0221552000, 0.0356920000, 0.0755064000, 0.1919605000, 0.5343207000"); - } - } - max_capacitance : 0.3241070000; - max_transition : 1.5024650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.3777113000, 0.3863187000, 0.4057278000, 0.4448160000, 0.5192214000, 0.6690808000, 1.0153002000", \ - "0.3813398000, 0.3899014000, 0.4093795000, 0.4482913000, 0.5235249000, 0.6728683000, 1.0191128000", \ - "0.3915805000, 0.4000859000, 0.4194511000, 0.4585159000, 0.5332224000, 0.6829755000, 1.0292533000", \ - "0.4178302000, 0.4262165000, 0.4455677000, 0.4847533000, 0.5597308000, 0.7091557000, 1.0554290000", \ - "0.4755422000, 0.4840481000, 0.5033948000, 0.5427405000, 0.6170811000, 0.7668091000, 1.1128498000", \ - "0.5925047000, 0.6011262000, 0.6203793000, 0.6595177000, 0.7347972000, 0.8844569000, 1.2303127000", \ - "0.7999251000, 0.8092269000, 0.8301906000, 0.8726431000, 0.9521686000, 1.1086430000, 1.4594156000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0911197000, 0.0972749000, 0.1116989000, 0.1451828000, 0.2293329000, 0.4639771000, 1.1448728000", \ - "0.0953220000, 0.1014064000, 0.1158984000, 0.1493359000, 0.2334211000, 0.4676544000, 1.1480390000", \ - "0.1055744000, 0.1116507000, 0.1260933000, 0.1592914000, 0.2433214000, 0.4779189000, 1.1583021000", \ - "0.1309991000, 0.1369593000, 0.1511876000, 0.1839418000, 0.2674673000, 0.5019168000, 1.1823530000", \ - "0.1777463000, 0.1840414000, 0.1986684000, 0.2317114000, 0.3149526000, 0.5490914000, 1.2271257000", \ - "0.2356008000, 0.2434250000, 0.2603922000, 0.2950673000, 0.3777581000, 0.6114009000, 1.2910684000", \ - "0.2832265000, 0.2933162000, 0.3150183000, 0.3562344000, 0.4413624000, 0.6744584000, 1.3532487000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0450229000, 0.0500477000, 0.0629138000, 0.0889542000, 0.1485761000, 0.2864628000, 0.6855131000", \ - "0.0449956000, 0.0503023000, 0.0625338000, 0.0893698000, 0.1468046000, 0.2865251000, 0.6852951000", \ - "0.0452496000, 0.0505660000, 0.0625703000, 0.0896703000, 0.1468259000, 0.2869072000, 0.6877683000", \ - "0.0449952000, 0.0503307000, 0.0631574000, 0.0902012000, 0.1461188000, 0.2865021000, 0.6853225000", \ - "0.0449319000, 0.0504640000, 0.0630453000, 0.0896576000, 0.1464976000, 0.2864138000, 0.6865450000", \ - "0.0458630000, 0.0513044000, 0.0633824000, 0.0895144000, 0.1460581000, 0.2866728000, 0.6863191000", \ - "0.0526411000, 0.0578125000, 0.0719040000, 0.0996264000, 0.1582323000, 0.2964246000, 0.6913044000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0221917000, 0.0272044000, 0.0405582000, 0.0773913000, 0.1882129000, 0.5196601000, 1.4997155000", \ - "0.0220797000, 0.0271477000, 0.0404358000, 0.0772614000, 0.1881099000, 0.5181540000, 1.4973572000", \ - "0.0220464000, 0.0271043000, 0.0401689000, 0.0770607000, 0.1877123000, 0.5185778000, 1.4965741000", \ - "0.0215231000, 0.0264818000, 0.0397020000, 0.0765681000, 0.1874450000, 0.5190166000, 1.4963181000", \ - "0.0244040000, 0.0290851000, 0.0417191000, 0.0773953000, 0.1869171000, 0.5183519000, 1.4993103000", \ - "0.0319434000, 0.0364663000, 0.0485840000, 0.0816755000, 0.1886792000, 0.5182512000, 1.4987005000", \ - "0.0433408000, 0.0495803000, 0.0630872000, 0.0942592000, 0.1919588000, 0.5209929000, 1.4984282000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.4197279000, 0.4288520000, 0.4497640000, 0.4908186000, 0.5677789000, 0.7191464000, 1.0670111000", \ - "0.4242482000, 0.4334626000, 0.4541598000, 0.4950182000, 0.5722736000, 0.7241404000, 1.0718210000", \ - "0.4360730000, 0.4453905000, 0.4661142000, 0.5069383000, 0.5831163000, 0.7353858000, 1.0835852000", \ - "0.4622788000, 0.4714882000, 0.4920876000, 0.5330719000, 0.6100879000, 0.7614442000, 1.1099017000", \ - "0.5154207000, 0.5246351000, 0.5452638000, 0.5863300000, 0.6633793000, 0.8146557000, 1.1630549000", \ - "0.6198184000, 0.6289865000, 0.6496602000, 0.6906508000, 0.7677095000, 0.9199470000, 1.2678329000", \ - "0.8011828000, 0.8110651000, 0.8332218000, 0.8772613000, 0.9579788000, 1.1156002000, 1.4675922000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0956310000, 0.1017615000, 0.1162174000, 0.1496133000, 0.2336343000, 0.4680123000, 1.1473708000", \ - "0.1000382000, 0.1061649000, 0.1206464000, 0.1540839000, 0.2381379000, 0.4722991000, 1.1514774000", \ - "0.1096835000, 0.1158033000, 0.1302356000, 0.1635617000, 0.2474619000, 0.4815917000, 1.1606606000", \ - "0.1322998000, 0.1382885000, 0.1525456000, 0.1855156000, 0.2692391000, 0.5038920000, 1.1847048000", \ - "0.1756235000, 0.1820403000, 0.1967228000, 0.2299561000, 0.3130297000, 0.5467167000, 1.2255170000", \ - "0.2377858000, 0.2453119000, 0.2617187000, 0.2961286000, 0.3801030000, 0.6135255000, 1.2932201000", \ - "0.3022296000, 0.3117662000, 0.3324780000, 0.3728876000, 0.4588188000, 0.6929730000, 1.3706505000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0497766000, 0.0548192000, 0.0675965000, 0.0937262000, 0.1501449000, 0.2907015000, 0.6902859000", \ - "0.0496255000, 0.0552689000, 0.0677728000, 0.0939890000, 0.1508689000, 0.2900081000, 0.6895581000", \ - "0.0494489000, 0.0553731000, 0.0679240000, 0.0937617000, 0.1532144000, 0.2909580000, 0.6895430000", \ - "0.0493028000, 0.0549418000, 0.0685376000, 0.0939964000, 0.1522046000, 0.2910423000, 0.6884670000", \ - "0.0493286000, 0.0552353000, 0.0683069000, 0.0951510000, 0.1504142000, 0.2911140000, 0.6893915000", \ - "0.0500967000, 0.0552624000, 0.0678464000, 0.0940343000, 0.1525831000, 0.2895635000, 0.6903348000", \ - "0.0561320000, 0.0623208000, 0.0750067000, 0.1037870000, 0.1617297000, 0.2985482000, 0.6940044000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0222087000, 0.0273074000, 0.0405449000, 0.0773492000, 0.1879323000, 0.5194499000, 1.4987293000", \ - "0.0221572000, 0.0272973000, 0.0405223000, 0.0773237000, 0.1880431000, 0.5184593000, 1.4982336000", \ - "0.0219446000, 0.0269383000, 0.0402743000, 0.0772232000, 0.1877162000, 0.5195641000, 1.4992187000", \ - "0.0217034000, 0.0267514000, 0.0399695000, 0.0768773000, 0.1875565000, 0.5194408000, 1.4997953000", \ - "0.0236669000, 0.0287717000, 0.0415285000, 0.0773584000, 0.1874460000, 0.5192481000, 1.4993953000", \ - "0.0293904000, 0.0345825000, 0.0470595000, 0.0815746000, 0.1883304000, 0.5174410000, 1.4990469000", \ - "0.0401507000, 0.0464067000, 0.0597187000, 0.0924357000, 0.1928068000, 0.5201998000, 1.4957061000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.3995388000, 0.4087569000, 0.4290465000, 0.4701970000, 0.5475126000, 0.6995094000, 1.0475496000", \ - "0.4024147000, 0.4116045000, 0.4324814000, 0.4734068000, 0.5505738000, 0.7018805000, 1.0499492000", \ - "0.4121145000, 0.4213622000, 0.4419159000, 0.4830801000, 0.5600260000, 0.7112916000, 1.0597525000", \ - "0.4367881000, 0.4459360000, 0.4667260000, 0.5075638000, 0.5838143000, 0.7358508000, 1.0842947000", \ - "0.4931046000, 0.5023221000, 0.5231503000, 0.5639035000, 0.6405167000, 0.7926018000, 1.1407807000", \ - "0.6163958000, 0.6257156000, 0.6463458000, 0.6874121000, 0.7644869000, 0.9166052000, 1.2648130000", \ - "0.8526042000, 0.8628012000, 0.8854374000, 0.9306530000, 1.0131870000, 1.1715863000, 1.5240115000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0687939000, 0.0739321000, 0.0863338000, 0.1163011000, 0.1966887000, 0.4288950000, 1.1060015000", \ - "0.0736192000, 0.0787502000, 0.0911422000, 0.1211407000, 0.2016914000, 0.4329103000, 1.1114289000", \ - "0.0848317000, 0.0899451000, 0.1022864000, 0.1321652000, 0.2125971000, 0.4447232000, 1.1210162000", \ - "0.1103884000, 0.1154773000, 0.1276897000, 0.1573239000, 0.2375201000, 0.4700453000, 1.1462822000", \ - "0.1495494000, 0.1556403000, 0.1691184000, 0.1997174000, 0.2800082000, 0.5125713000, 1.1890737000", \ - "0.1925584000, 0.2003692000, 0.2173686000, 0.2510453000, 0.3318592000, 0.5632165000, 1.2415792000", \ - "0.2172121000, 0.2275204000, 0.2498155000, 0.2922987000, 0.3765764000, 0.6080975000, 1.2850383000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0496567000, 0.0553608000, 0.0674577000, 0.0942882000, 0.1509752000, 0.2902286000, 0.6906103000", \ - "0.0496098000, 0.0553439000, 0.0675019000, 0.0935923000, 0.1501349000, 0.2902472000, 0.6912826000", \ - "0.0495610000, 0.0547722000, 0.0685521000, 0.0943776000, 0.1524853000, 0.2911466000, 0.6891375000", \ - "0.0494436000, 0.0553774000, 0.0685637000, 0.0938821000, 0.1531420000, 0.2918204000, 0.6895292000", \ - "0.0494030000, 0.0550800000, 0.0682038000, 0.0938022000, 0.1521161000, 0.2910058000, 0.6892913000", \ - "0.0500431000, 0.0553711000, 0.0678133000, 0.0954423000, 0.1525858000, 0.2904376000, 0.6897293000", \ - "0.0588857000, 0.0649671000, 0.0790239000, 0.1069441000, 0.1628683000, 0.2991767000, 0.6948022000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0182279000, 0.0225508000, 0.0346906000, 0.0710760000, 0.1829107000, 0.5161021000, 1.4945991000", \ - "0.0182096000, 0.0224976000, 0.0346685000, 0.0711646000, 0.1828403000, 0.5156245000, 1.4929258000", \ - "0.0180763000, 0.0223848000, 0.0345784000, 0.0710540000, 0.1825700000, 0.5151237000, 1.4963195000", \ - "0.0185598000, 0.0227357000, 0.0347689000, 0.0708289000, 0.1827679000, 0.5153454000, 1.4965300000", \ - "0.0236434000, 0.0275504000, 0.0385607000, 0.0728461000, 0.1829481000, 0.5156544000, 1.4957969000", \ - "0.0324583000, 0.0367466000, 0.0482848000, 0.0785247000, 0.1842351000, 0.5146512000, 1.4956377000", \ - "0.0448803000, 0.0511647000, 0.0640294000, 0.0947047000, 0.1898568000, 0.5186319000, 1.4916007000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.3613674000, 0.3703108000, 0.3912567000, 0.4322384000, 0.5093104000, 0.6606468000, 1.0085548000", \ - "0.3640395000, 0.3732766000, 0.3939085000, 0.4348458000, 0.5120036000, 0.6638325000, 1.0122241000", \ - "0.3727306000, 0.3819688000, 0.4026124000, 0.4435990000, 0.5206501000, 0.6718931000, 1.0198429000", \ - "0.3961481000, 0.4051480000, 0.4261765000, 0.4668617000, 0.5441916000, 0.6950340000, 1.0430785000", \ - "0.4536015000, 0.4628319000, 0.4834961000, 0.5245975000, 0.6016896000, 0.7528265000, 1.1012359000", \ - "0.5879439000, 0.5972219000, 0.6191978000, 0.6594107000, 0.7357838000, 0.8881635000, 1.2360593000", \ - "0.8496697000, 0.8599796000, 0.8829698000, 0.9283506000, 1.0116196000, 1.1685295000, 1.5207572000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0652524000, 0.0702799000, 0.0824012000, 0.1118466000, 0.1916949000, 0.4223106000, 1.1007516000", \ - "0.0700207000, 0.0750411000, 0.0870867000, 0.1165255000, 0.1964521000, 0.4279521000, 1.1053154000", \ - "0.0811639000, 0.0861841000, 0.0982558000, 0.1276103000, 0.2072586000, 0.4384543000, 1.1166584000", \ - "0.1056349000, 0.1107021000, 0.1227949000, 0.1521340000, 0.2319051000, 0.4632233000, 1.1433249000", \ - "0.1411534000, 0.1472422000, 0.1607300000, 0.1911842000, 0.2710420000, 0.5020815000, 1.1808606000", \ - "0.1773288000, 0.1853370000, 0.2024902000, 0.2365188000, 0.3172706000, 0.5483022000, 1.2292317000", \ - "0.1911449000, 0.2017134000, 0.2245617000, 0.2679314000, 0.3527678000, 0.5840214000, 1.2605993000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0495493000, 0.0548984000, 0.0676404000, 0.0936039000, 0.1503649000, 0.2912338000, 0.6894454000", \ - "0.0497096000, 0.0551437000, 0.0676578000, 0.0939139000, 0.1507307000, 0.2904362000, 0.6910006000", \ - "0.0493754000, 0.0548572000, 0.0676435000, 0.0935858000, 0.1503887000, 0.2915706000, 0.6894704000", \ - "0.0493535000, 0.0552183000, 0.0681166000, 0.0938555000, 0.1505104000, 0.2911435000, 0.6895085000", \ - "0.0493990000, 0.0553657000, 0.0682589000, 0.0950465000, 0.1503612000, 0.2911563000, 0.6896154000", \ - "0.0505192000, 0.0556349000, 0.0678227000, 0.0957669000, 0.1513448000, 0.2912720000, 0.6892966000", \ - "0.0623395000, 0.0682860000, 0.0824623000, 0.1089729000, 0.1646015000, 0.3013402000, 0.6955746000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0174968000, 0.0217049000, 0.0338066000, 0.0700211000, 0.1818369000, 0.5142428000, 1.4976331000", \ - "0.0174971000, 0.0217186000, 0.0337855000, 0.0700489000, 0.1821584000, 0.5162618000, 1.4967422000", \ - "0.0174679000, 0.0217198000, 0.0338652000, 0.0700938000, 0.1819938000, 0.5154879000, 1.4970308000", \ - "0.0184312000, 0.0224654000, 0.0342880000, 0.0702553000, 0.1815639000, 0.5153658000, 1.4988581000", \ - "0.0236778000, 0.0275350000, 0.0385569000, 0.0725358000, 0.1822238000, 0.5149991000, 1.4973089000", \ - "0.0331988000, 0.0374700000, 0.0480816000, 0.0789829000, 0.1840568000, 0.5147981000, 1.4977738000", \ - "0.0463944000, 0.0524996000, 0.0656235000, 0.0959141000, 0.1902279000, 0.5178184000, 1.4906327000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.3071579000, 0.3164347000, 0.3370795000, 0.3782359000, 0.4552806000, 0.6065197000, 0.9549040000", \ - "0.3085127000, 0.3178788000, 0.3385025000, 0.3797120000, 0.4567691000, 0.6081105000, 0.9566167000", \ - "0.3146533000, 0.3238779000, 0.3446874000, 0.3853603000, 0.4625828000, 0.6147455000, 0.9630803000", \ - "0.3368440000, 0.3460174000, 0.3666942000, 0.4078573000, 0.4848256000, 0.6365665000, 0.9849737000", \ - "0.3952033000, 0.4044249000, 0.4249720000, 0.4661097000, 0.5434714000, 0.6956332000, 1.0437179000", \ - "0.5393696000, 0.5483443000, 0.5685729000, 0.6089305000, 0.6848270000, 0.8369826000, 1.1853560000", \ - "0.8089973000, 0.8197084000, 0.8443463000, 0.8914163000, 0.9732278000, 1.1279647000, 1.4773710000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0583868000, 0.0632251000, 0.0750606000, 0.1039627000, 0.1832201000, 0.4136044000, 1.0924037000", \ - "0.0630660000, 0.0679354000, 0.0797258000, 0.1085947000, 0.1876543000, 0.4183956000, 1.0952406000", \ - "0.0742825000, 0.0791402000, 0.0908829000, 0.1197342000, 0.1990877000, 0.4299359000, 1.1087384000", \ - "0.0972002000, 0.1022341000, 0.1141984000, 0.1431640000, 0.2223578000, 0.4537431000, 1.1307589000", \ - "0.1277943000, 0.1340239000, 0.1476504000, 0.1780513000, 0.2576114000, 0.4898199000, 1.1656908000", \ - "0.1563009000, 0.1646270000, 0.1823806000, 0.2168927000, 0.2974961000, 0.5284140000, 1.2088109000", \ - "0.1583891000, 0.1693265000, 0.1931600000, 0.2381714000, 0.3238919000, 0.5552401000, 1.2314653000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0496797000, 0.0548473000, 0.0682678000, 0.0948871000, 0.1502663000, 0.2910230000, 0.6904202000", \ - "0.0493222000, 0.0548165000, 0.0684667000, 0.0942931000, 0.1525954000, 0.2908530000, 0.6884741000", \ - "0.0496975000, 0.0553297000, 0.0678246000, 0.0944632000, 0.1511860000, 0.2902573000, 0.6902726000", \ - "0.0494099000, 0.0551904000, 0.0681535000, 0.0947046000, 0.1506455000, 0.2911229000, 0.6893756000", \ - "0.0493560000, 0.0548398000, 0.0674909000, 0.0943639000, 0.1524707000, 0.2907940000, 0.6893683000", \ - "0.0492283000, 0.0545193000, 0.0668676000, 0.0928827000, 0.1538553000, 0.2910676000, 0.6897716000", \ - "0.0677333000, 0.0732533000, 0.0869778000, 0.1120217000, 0.1646735000, 0.2974535000, 0.6955500000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014709200, 0.0043272200, 0.0127300000, 0.0374497000, 0.1101710000, 0.3241070000"); - values("0.0167541000, 0.0209493000, 0.0330482000, 0.0694558000, 0.1817812000, 0.5155558000, 1.5024646000", \ - "0.0167426000, 0.0209584000, 0.0330835000, 0.0693904000, 0.1816400000, 0.5152510000, 1.4987201000", \ - "0.0167443000, 0.0209751000, 0.0330468000, 0.0694558000, 0.1818818000, 0.5160596000, 1.4985904000", \ - "0.0185760000, 0.0225247000, 0.0340612000, 0.0696919000, 0.1816074000, 0.5153201000, 1.4962586000", \ - "0.0244649000, 0.0282515000, 0.0390247000, 0.0725269000, 0.1815689000, 0.5156460000, 1.4981617000", \ - "0.0347936000, 0.0390050000, 0.0497091000, 0.0799913000, 0.1842178000, 0.5131632000, 1.4984572000", \ - "0.0491915000, 0.0552525000, 0.0688059000, 0.0992234000, 0.1912681000, 0.5162046000, 1.4943380000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111o_4") { - leakage_power () { - value : 0.0054313000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0118340000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0250712000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0370519000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0252806000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0467636000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0250182000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0353823000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0054324000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0084080000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0020969000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0042066000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0020850000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0040078000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0019724000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0020893000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0054327000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0081938000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0020969000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0042066000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0020855000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0040078000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0019724000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0020893000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0022713000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0057660000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0020096000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0022608000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0020059000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0022651000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0019466000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0020131000; - when : "A1&A2&B1&C1&!D1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a2111o"; - cell_leakage_power : 0.0091485880; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091843000, 0.0091789000, 0.0091663000, 0.0091665000, 0.0091668000, 0.0091678000, 0.0091699000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007162600, -0.007171300, -0.007191300, -0.007177900, -0.007146600, -0.007074600, -0.006908600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044800000; - } - pin ("A2") { - capacitance : 0.0044660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082704000, 0.0082618000, 0.0082421000, 0.0082419000, 0.0082416000, 0.0082410000, 0.0082394000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008197000, -0.008192400, -0.008181700, -0.008185200, -0.008193000, -0.008211000, -0.008252500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047410000; - } - pin ("B1") { - capacitance : 0.0044630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0098281000, 0.0098192000, 0.0097987000, 0.0097977000, 0.0097954000, 0.0097899000, 0.0097776000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006882700, -0.006935400, -0.007057100, -0.007089600, -0.007164600, -0.007337600, -0.007736200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047720000; - } - pin ("C1") { - capacitance : 0.0043980000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082912000, 0.0082878000, 0.0082801000, 0.0082801000, 0.0082800000, 0.0082797000, 0.0082794000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007180700, -0.007315800, -0.007627400, -0.007641400, -0.007673600, -0.007748000, -0.007919200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047560000; - } - pin ("D1") { - capacitance : 0.0043130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050873000, 0.0050847000, 0.0050786000, 0.0051019000, 0.0051558000, 0.0052800000, 0.0055661000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003587000, -0.003579200, -0.003561200, -0.003562600, -0.003566000, -0.003573400, -0.003590700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047000000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1) | (D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0370431000, 0.0350998000, 0.0298243000, 0.0150922000, -0.036520400, -0.217091800, -0.812282800", \ - "0.0367890000, 0.0348262000, 0.0295256000, 0.0147655000, -0.036743700, -0.217342500, -0.812414000", \ - "0.0362817000, 0.0343347000, 0.0294153000, 0.0142798000, -0.037335900, -0.217877000, -0.813066500", \ - "0.0357731000, 0.0337640000, 0.0284689000, 0.0135311000, -0.037964700, -0.218513900, -0.813542400", \ - "0.0353114000, 0.0333889000, 0.0279938000, 0.0130309000, -0.038514600, -0.219067600, -0.814099500", \ - "0.0352202000, 0.0333423000, 0.0279620000, 0.0130431000, -0.038681400, -0.219343000, -0.814368300", \ - "0.0452960000, 0.0431922000, 0.0369365000, 0.0182128000, -0.039937300, -0.219501700, -0.814312600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0378468000, 0.0397922000, 0.0460762000, 0.0655750000, 0.1247708000, 0.3103613000, 0.8999013000", \ - "0.0376934000, 0.0396198000, 0.0458719000, 0.0653036000, 0.1246188000, 0.3096418000, 0.8987992000", \ - "0.0373458000, 0.0393472000, 0.0454998000, 0.0652333000, 0.1244342000, 0.3097854000, 0.8992468000", \ - "0.0370942000, 0.0389606000, 0.0452460000, 0.0648849000, 0.1240305000, 0.3095824000, 0.8990234000", \ - "0.0372350000, 0.0391143000, 0.0453372000, 0.0644245000, 0.1233493000, 0.3090626000, 0.8991017000", \ - "0.0394021000, 0.0411684000, 0.0468009000, 0.0647048000, 0.1231621000, 0.3078197000, 0.8988902000", \ - "0.0426433000, 0.0443353000, 0.0507613000, 0.0687756000, 0.1264536000, 0.3101726000, 0.9000545000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0430825000, 0.0410898000, 0.0356724000, 0.0207536000, -0.030850200, -0.212074400, -0.807594500", \ - "0.0428761000, 0.0409369000, 0.0356206000, 0.0205269000, -0.031111400, -0.212207700, -0.807715600", \ - "0.0429502000, 0.0409991000, 0.0355622000, 0.0205369000, -0.031380900, -0.212536500, -0.808055200", \ - "0.0422856000, 0.0402780000, 0.0349615000, 0.0199373000, -0.031757300, -0.212838400, -0.808388900", \ - "0.0419281000, 0.0399258000, 0.0346136000, 0.0196177000, -0.032231300, -0.213198500, -0.808576300", \ - "0.0420237000, 0.0400077000, 0.0346329000, 0.0195910000, -0.032394200, -0.213382800, -0.808744500", \ - "0.0505946000, 0.0484930000, 0.0421522000, 0.0236464000, -0.033142100, -0.213344500, -0.808521500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0386293000, 0.0405579000, 0.0468313000, 0.0663775000, 0.1255400000, 0.3104193000, 0.9002008000", \ - "0.0385139000, 0.0404205000, 0.0466813000, 0.0660757000, 0.1253177000, 0.3103760000, 0.9032879000", \ - "0.0382459000, 0.0401523000, 0.0463403000, 0.0658774000, 0.1249757000, 0.3102738000, 0.8995112000", \ - "0.0379147000, 0.0398002000, 0.0461112000, 0.0657450000, 0.1247783000, 0.3101180000, 0.8991192000", \ - "0.0381898000, 0.0401605000, 0.0463096000, 0.0654483000, 0.1246343000, 0.3093500000, 0.9016978000", \ - "0.0407860000, 0.0425737000, 0.0482729000, 0.0664494000, 0.1243317000, 0.3090972000, 0.8991015000", \ - "0.0428108000, 0.0445661000, 0.0501175000, 0.0682025000, 0.1256943000, 0.3105553000, 0.8986520000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0375007000, 0.0355553000, 0.0301077000, 0.0150807000, -0.036826500, -0.217752300, -0.813069700", \ - "0.0371931000, 0.0351892000, 0.0297945000, 0.0146990000, -0.037153800, -0.218033200, -0.813376800", \ - "0.0364590000, 0.0344844000, 0.0291999000, 0.0140888000, -0.037576400, -0.218423100, -0.813661800", \ - "0.0364061000, 0.0345024000, 0.0290023000, 0.0139636000, -0.037957900, -0.218864200, -0.814116700", \ - "0.0357090000, 0.0336994000, 0.0285635000, 0.0134469000, -0.038382900, -0.219294300, -0.814451900", \ - "0.0359428000, 0.0339137000, 0.0285238000, 0.0133868000, -0.038598800, -0.219374400, -0.814446700", \ - "0.0447162000, 0.0425787000, 0.0361847000, 0.0171906000, -0.039157400, -0.219265700, -0.814324700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0349719000, 0.0369699000, 0.0433398000, 0.0626883000, 0.1218261000, 0.3080500000, 0.9002615000", \ - "0.0349867000, 0.0369790000, 0.0433233000, 0.0627094000, 0.1218535000, 0.3064868000, 0.9003501000", \ - "0.0350080000, 0.0370468000, 0.0433456000, 0.0627084000, 0.1217315000, 0.3068702000, 0.8973238000", \ - "0.0348630000, 0.0368340000, 0.0430164000, 0.0621766000, 0.1211635000, 0.3065484000, 0.8970224000", \ - "0.0349607000, 0.0368107000, 0.0428607000, 0.0617782000, 0.1205394000, 0.3060511000, 0.8967277000", \ - "0.0365306000, 0.0383188000, 0.0440415000, 0.0624877000, 0.1204079000, 0.3049592000, 0.8957521000", \ - "0.0398922000, 0.0415317000, 0.0471981000, 0.0652671000, 0.1235346000, 0.3080686000, 0.8946060000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0339570000, 0.0320178000, 0.0266484000, 0.0115754000, -0.040186400, -0.220844200, -0.815726300", \ - "0.0336898000, 0.0317046000, 0.0263997000, 0.0113350000, -0.040451100, -0.221031300, -0.816046100", \ - "0.0332202000, 0.0312859000, 0.0259727000, 0.0110177000, -0.040813600, -0.221501200, -0.816475500", \ - "0.0329918000, 0.0310144000, 0.0256891000, 0.0103988000, -0.041220300, -0.221940700, -0.816927100", \ - "0.0323432000, 0.0304357000, 0.0251113000, 0.0101349000, -0.041610500, -0.222288800, -0.817293700", \ - "0.0325139000, 0.0305673000, 0.0254898000, 0.0105536000, -0.041687100, -0.222482700, -0.817374100", \ - "0.0415562000, 0.0393891000, 0.0329247000, 0.0137850000, -0.042334500, -0.222350300, -0.816796900"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0330249000, 0.0350280000, 0.0412725000, 0.0604756000, 0.1194725000, 0.3047105000, 0.8936072000", \ - "0.0331587000, 0.0351213000, 0.0413815000, 0.0606113000, 0.1195693000, 0.3059467000, 0.8948953000", \ - "0.0334022000, 0.0354031000, 0.0416408000, 0.0608067000, 0.1197893000, 0.3051785000, 0.8938583000", \ - "0.0331790000, 0.0351000000, 0.0412594000, 0.0602795000, 0.1192456000, 0.3048228000, 0.8982117000", \ - "0.0331629000, 0.0350317000, 0.0410159000, 0.0598460000, 0.1184984000, 0.3043212000, 0.8968101000", \ - "0.0342229000, 0.0360229000, 0.0417321000, 0.0602359000, 0.1182571000, 0.3030233000, 0.8962260000", \ - "0.0370409000, 0.0387308000, 0.0442581000, 0.0623741000, 0.1206597000, 0.3050319000, 0.8916636000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0322863000, 0.0302956000, 0.0247789000, 0.0100184000, -0.041787400, -0.222339900, -0.817159700", \ - "0.0318474000, 0.0299104000, 0.0245896000, 0.0095267000, -0.042122100, -0.222570300, -0.817504600", \ - "0.0314484000, 0.0294694000, 0.0240673000, 0.0092043000, -0.042559000, -0.223050700, -0.817878500", \ - "0.0309156000, 0.0289601000, 0.0236288000, 0.0086595000, -0.043047700, -0.223584000, -0.818279800", \ - "0.0307047000, 0.0287053000, 0.0233329000, 0.0083716000, -0.043375900, -0.223912100, -0.818570100", \ - "0.0314190000, 0.0294362000, 0.0239977000, 0.0096901000, -0.043000300, -0.223324000, -0.818131500", \ - "0.0445028000, 0.0422378000, 0.0356596000, 0.0166719000, -0.041675300, -0.221951000, -0.816626100"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015993650, 0.0051159350, 0.0163644900, 0.0523455900, 0.1674394000, 0.5355933000"); - values("0.0252292000, 0.0272266000, 0.0334461000, 0.0527404000, 0.1116176000, 0.2968349000, 0.8877106000", \ - "0.0252576000, 0.0272529000, 0.0334966000, 0.0527502000, 0.1117030000, 0.2978237000, 0.8875495000", \ - "0.0251661000, 0.0271509000, 0.0333350000, 0.0525200000, 0.1114021000, 0.2961668000, 0.8867464000", \ - "0.0249880000, 0.0269113000, 0.0329497000, 0.0519505000, 0.1108438000, 0.2959818000, 0.8864121000", \ - "0.0250726000, 0.0268820000, 0.0327630000, 0.0514884000, 0.1100945000, 0.2956256000, 0.8861587000", \ - "0.0262419000, 0.0280199000, 0.0337328000, 0.0522248000, 0.1098933000, 0.2945102000, 0.8862561000", \ - "0.0287704000, 0.0304465000, 0.0359998000, 0.0539533000, 0.1123027000, 0.2962995000, 0.8839073000"); - } - } - max_capacitance : 0.5355930000; - max_transition : 1.4995610000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.4115941000, 0.4175033000, 0.4329213000, 0.4673878000, 0.5380981000, 0.6840060000, 1.0310978000", \ - "0.4148444000, 0.4208039000, 0.4362171000, 0.4709618000, 0.5413902000, 0.6874268000, 1.0344630000", \ - "0.4240364000, 0.4299260000, 0.4452283000, 0.4797683000, 0.5504759000, 0.6966396000, 1.0435759000", \ - "0.4476691000, 0.4535678000, 0.4689522000, 0.5034552000, 0.5735579000, 0.7200097000, 1.0671127000", \ - "0.5006885000, 0.5065925000, 0.5217816000, 0.5565836000, 0.6268304000, 0.7731911000, 1.1202571000", \ - "0.6093019000, 0.6151657000, 0.6306063000, 0.6652667000, 0.7359207000, 0.8822514000, 1.2292292000", \ - "0.7955708000, 0.8019144000, 0.8185901000, 0.8554488000, 0.9303637000, 1.0832956000, 1.4359871000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.1155489000, 0.1203134000, 0.1330129000, 0.1638583000, 0.2420998000, 0.4686905000, 1.1810698000", \ - "0.1197018000, 0.1245155000, 0.1371148000, 0.1679199000, 0.2461037000, 0.4734624000, 1.1838098000", \ - "0.1298974000, 0.1346235000, 0.1471999000, 0.1780507000, 0.2561422000, 0.4826625000, 1.1942837000", \ - "0.1552305000, 0.1598858000, 0.1723547000, 0.2029143000, 0.2805815000, 0.5071073000, 1.2191946000", \ - "0.2088519000, 0.2136007000, 0.2262018000, 0.2565188000, 0.3336759000, 0.5596335000, 1.2697078000", \ - "0.2817954000, 0.2870962000, 0.3011684000, 0.3331898000, 0.4110781000, 0.6367311000, 1.3472002000", \ - "0.3553420000, 0.3623765000, 0.3793410000, 0.4170586000, 0.4976368000, 0.7214785000, 1.4311019000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0480871000, 0.0516464000, 0.0612945000, 0.0840995000, 0.1367413000, 0.2717778000, 0.6683779000", \ - "0.0481557000, 0.0516889000, 0.0614237000, 0.0847249000, 0.1370753000, 0.2719025000, 0.6696127000", \ - "0.0480849000, 0.0516376000, 0.0618651000, 0.0850511000, 0.1367214000, 0.2718762000, 0.6681152000", \ - "0.0484118000, 0.0516246000, 0.0613440000, 0.0837803000, 0.1372669000, 0.2714812000, 0.6689925000", \ - "0.0480523000, 0.0516124000, 0.0615392000, 0.0837779000, 0.1376039000, 0.2717303000, 0.6693000000", \ - "0.0490720000, 0.0526121000, 0.0624202000, 0.0847987000, 0.1371412000, 0.2716447000, 0.6694921000", \ - "0.0553412000, 0.0590917000, 0.0689578000, 0.0936347000, 0.1485734000, 0.2816013000, 0.6740966000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0273855000, 0.0310724000, 0.0420489000, 0.0728962000, 0.1688231000, 0.4833386000, 1.4953184000", \ - "0.0272884000, 0.0311188000, 0.0419613000, 0.0727831000, 0.1688928000, 0.4824634000, 1.4977052000", \ - "0.0272541000, 0.0309167000, 0.0417322000, 0.0725854000, 0.1684801000, 0.4832154000, 1.4979696000", \ - "0.0267420000, 0.0305250000, 0.0410955000, 0.0719168000, 0.1681389000, 0.4830277000, 1.4957076000", \ - "0.0280348000, 0.0315696000, 0.0420309000, 0.0721543000, 0.1672298000, 0.4825285000, 1.4988765000", \ - "0.0348975000, 0.0384332000, 0.0479786000, 0.0764804000, 0.1690848000, 0.4812143000, 1.4975465000", \ - "0.0479628000, 0.0516827000, 0.0633244000, 0.0906918000, 0.1740881000, 0.4832356000, 1.4952820000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.4448634000, 0.4512119000, 0.4675791000, 0.5036939000, 0.5755290000, 0.7225767000, 1.0703615000", \ - "0.4490507000, 0.4554687000, 0.4718586000, 0.5078594000, 0.5790171000, 0.7264089000, 1.0745699000", \ - "0.4605443000, 0.4668559000, 0.4831666000, 0.5192426000, 0.5912253000, 0.7383091000, 1.0861898000", \ - "0.4862011000, 0.4924626000, 0.5089066000, 0.5448581000, 0.6169412000, 0.7642657000, 1.1119535000", \ - "0.5399827000, 0.5462258000, 0.5627007000, 0.5985560000, 0.6706983000, 0.8172709000, 1.1653039000", \ - "0.6470642000, 0.6534038000, 0.6698226000, 0.7058856000, 0.7780186000, 0.9253514000, 1.2731071000", \ - "0.8370855000, 0.8436525000, 0.8609594000, 0.8997531000, 0.9754298000, 1.1281145000, 1.4803317000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.1199637000, 0.1247155000, 0.1373762000, 0.1682281000, 0.2462877000, 0.4729104000, 1.1819367000", \ - "0.1241539000, 0.1289057000, 0.1415068000, 0.1722762000, 0.2502615000, 0.4772293000, 1.1889939000", \ - "0.1324321000, 0.1371600000, 0.1497774000, 0.1804953000, 0.2584480000, 0.4847056000, 1.1967375000", \ - "0.1514974000, 0.1561837000, 0.1687262000, 0.1993471000, 0.2770071000, 0.5034633000, 1.2155169000", \ - "0.1912431000, 0.1960713000, 0.2087525000, 0.2394528000, 0.3169678000, 0.5434870000, 1.2539781000", \ - "0.2526128000, 0.2578559000, 0.2716620000, 0.3036127000, 0.3821604000, 0.6080910000, 1.3173027000", \ - "0.3203928000, 0.3270385000, 0.3436597000, 0.3798863000, 0.4608751000, 0.6867595000, 1.3958078000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0521519000, 0.0558590000, 0.0660838000, 0.0878332000, 0.1402059000, 0.2737608000, 0.6712583000", \ - "0.0522502000, 0.0559862000, 0.0656455000, 0.0877887000, 0.1404759000, 0.2738836000, 0.6711888000", \ - "0.0521065000, 0.0560804000, 0.0655479000, 0.0875770000, 0.1398165000, 0.2735885000, 0.6712502000", \ - "0.0520543000, 0.0559837000, 0.0659450000, 0.0879500000, 0.1398222000, 0.2738454000, 0.6711001000", \ - "0.0523931000, 0.0560042000, 0.0658888000, 0.0879303000, 0.1397945000, 0.2738825000, 0.6716265000", \ - "0.0521955000, 0.0559536000, 0.0659648000, 0.0881366000, 0.1395719000, 0.2737408000, 0.6711478000", \ - "0.0587509000, 0.0625227000, 0.0724000000, 0.0956862000, 0.1485478000, 0.2804633000, 0.6757898000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0274192000, 0.0312213000, 0.0417866000, 0.0727488000, 0.1686087000, 0.4828856000, 1.4990658000", \ - "0.0272715000, 0.0310303000, 0.0418953000, 0.0726723000, 0.1687138000, 0.4825555000, 1.4995613000", \ - "0.0271192000, 0.0308935000, 0.0418020000, 0.0725791000, 0.1686530000, 0.4832557000, 1.4957356000", \ - "0.0268580000, 0.0306139000, 0.0412676000, 0.0722630000, 0.1683329000, 0.4828969000, 1.4979197000", \ - "0.0280082000, 0.0318064000, 0.0425007000, 0.0724488000, 0.1677774000, 0.4821093000, 1.4954128000", \ - "0.0325901000, 0.0362795000, 0.0469310000, 0.0761606000, 0.1697543000, 0.4818549000, 1.4991328000", \ - "0.0420402000, 0.0461143000, 0.0574055000, 0.0856753000, 0.1740334000, 0.4838551000, 1.4935611000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.4260579000, 0.4323966000, 0.4487163000, 0.4847882000, 0.5568040000, 0.7041508000, 1.0520426000", \ - "0.4282617000, 0.4345690000, 0.4510168000, 0.4871672000, 0.5591589000, 0.7066823000, 1.0537284000", \ - "0.4369451000, 0.4429887000, 0.4595819000, 0.4955998000, 0.5668102000, 0.7142840000, 1.0627386000", \ - "0.4596542000, 0.4659618000, 0.4822875000, 0.5183359000, 0.5903281000, 0.7377422000, 1.0856083000", \ - "0.5117728000, 0.5180855000, 0.5344215000, 0.5704623000, 0.6424428000, 0.7897626000, 1.1376965000", \ - "0.6238796000, 0.6301412000, 0.6466553000, 0.6827395000, 0.7548828000, 0.9021879000, 1.2504355000", \ - "0.8321034000, 0.8390568000, 0.8569158000, 0.8965711000, 0.9740722000, 1.1284773000, 1.4812391000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0744878000, 0.0780968000, 0.0880337000, 0.1137975000, 0.1859537000, 0.4089993000, 1.1182703000", \ - "0.0791558000, 0.0827642000, 0.0926919000, 0.1184921000, 0.1904914000, 0.4135318000, 1.1226089000", \ - "0.0904908000, 0.0941425000, 0.1039857000, 0.1296799000, 0.2018417000, 0.4249385000, 1.1320305000", \ - "0.1163552000, 0.1199349000, 0.1296344000, 0.1550484000, 0.2270181000, 0.4503184000, 1.1575541000", \ - "0.1573870000, 0.1614313000, 0.1720743000, 0.1983847000, 0.2703751000, 0.4939892000, 1.2012703000", \ - "0.2039934000, 0.2091821000, 0.2223291000, 0.2515462000, 0.3244359000, 0.5472220000, 1.2577883000", \ - "0.2351040000, 0.2418778000, 0.2591554000, 0.2960127000, 0.3734746000, 0.5964407000, 1.3030648000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0521095000, 0.0560787000, 0.0655455000, 0.0875655000, 0.1397707000, 0.2737905000, 0.6710662000", \ - "0.0520471000, 0.0558503000, 0.0655094000, 0.0877114000, 0.1398383000, 0.2732096000, 0.6715268000", \ - "0.0523024000, 0.0562556000, 0.0654785000, 0.0877994000, 0.1406029000, 0.2739475000, 0.6711502000", \ - "0.0521535000, 0.0562051000, 0.0655470000, 0.0875649000, 0.1398186000, 0.2737783000, 0.6709121000", \ - "0.0520456000, 0.0558053000, 0.0655826000, 0.0876098000, 0.1400015000, 0.2735221000, 0.6717790000", \ - "0.0526572000, 0.0562642000, 0.0665058000, 0.0883732000, 0.1397664000, 0.2737919000, 0.6701952000", \ - "0.0612598000, 0.0651435000, 0.0760417000, 0.0999324000, 0.1529886000, 0.2828456000, 0.6786085000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0198037000, 0.0228179000, 0.0321572000, 0.0615093000, 0.1586521000, 0.4756767000, 1.4944943000", \ - "0.0198198000, 0.0227999000, 0.0320844000, 0.0614283000, 0.1587177000, 0.4750618000, 1.4944143000", \ - "0.0196803000, 0.0227173000, 0.0319789000, 0.0614144000, 0.1588066000, 0.4758108000, 1.4921978000", \ - "0.0198888000, 0.0228547000, 0.0320599000, 0.0612261000, 0.1584023000, 0.4750961000, 1.4939916000", \ - "0.0244362000, 0.0273059000, 0.0356048000, 0.0633472000, 0.1585914000, 0.4758947000, 1.4939372000", \ - "0.0328225000, 0.0356976000, 0.0440039000, 0.0693326000, 0.1609359000, 0.4749983000, 1.4905308000", \ - "0.0457933000, 0.0496005000, 0.0595614000, 0.0846516000, 0.1670669000, 0.4785687000, 1.4910705000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.3879921000, 0.3943458000, 0.4106597000, 0.4468968000, 0.5187451000, 0.6655091000, 1.0134882000", \ - "0.3900253000, 0.3964577000, 0.4128411000, 0.4488208000, 0.5211057000, 0.6675859000, 1.0158707000", \ - "0.3977841000, 0.4041448000, 0.4204827000, 0.4566127000, 0.5285767000, 0.6752152000, 1.0232879000", \ - "0.4202141000, 0.4265851000, 0.4429844000, 0.4790262000, 0.5511084000, 0.6985656000, 1.0456881000", \ - "0.4746845000, 0.4809805000, 0.4970734000, 0.5333782000, 0.6050709000, 0.7525278000, 1.1007366000", \ - "0.6023234000, 0.6092777000, 0.6250918000, 0.6615928000, 0.7330948000, 0.8810347000, 1.2288970000", \ - "0.8467784000, 0.8538470000, 0.8722110000, 0.9126857000, 0.9906848000, 1.1456123000, 1.4953718000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0754043000, 0.0790623000, 0.0890920000, 0.1149562000, 0.1867036000, 0.4089906000, 1.1156904000", \ - "0.0800322000, 0.0836774000, 0.0937203000, 0.1196167000, 0.1915537000, 0.4139878000, 1.1215527000", \ - "0.0911567000, 0.0948162000, 0.1048271000, 0.1306075000, 0.2025511000, 0.4249992000, 1.1313385000", \ - "0.1160362000, 0.1196838000, 0.1296467000, 0.1553387000, 0.2271078000, 0.4498247000, 1.1587681000", \ - "0.1545259000, 0.1586868000, 0.1695713000, 0.1963022000, 0.2684931000, 0.4912278000, 1.1989528000", \ - "0.1962747000, 0.2016587000, 0.2149924000, 0.2449023000, 0.3182509000, 0.5409259000, 1.2504535000", \ - "0.2192432000, 0.2262179000, 0.2439352000, 0.2818392000, 0.3606363000, 0.5835799000, 1.2902825000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0522805000, 0.0556485000, 0.0660161000, 0.0885238000, 0.1411741000, 0.2740345000, 0.6720995000", \ - "0.0524252000, 0.0557000000, 0.0657058000, 0.0878135000, 0.1398764000, 0.2742993000, 0.6709960000", \ - "0.0522849000, 0.0557163000, 0.0657158000, 0.0891508000, 0.1393863000, 0.2734984000, 0.6710753000", \ - "0.0518516000, 0.0557694000, 0.0663125000, 0.0892823000, 0.1398731000, 0.2736480000, 0.6717066000", \ - "0.0524370000, 0.0562503000, 0.0654116000, 0.0879080000, 0.1403088000, 0.2739899000, 0.6715009000", \ - "0.0530770000, 0.0562914000, 0.0663907000, 0.0891292000, 0.1402306000, 0.2738280000, 0.6709798000", \ - "0.0647640000, 0.0687660000, 0.0796031000, 0.1022917000, 0.1538639000, 0.2835343000, 0.6787885000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0198304000, 0.0228452000, 0.0322018000, 0.0613072000, 0.1581851000, 0.4761771000, 1.4924715000", \ - "0.0197899000, 0.0228318000, 0.0321057000, 0.0613059000, 0.1579673000, 0.4764470000, 1.4944048000", \ - "0.0198202000, 0.0228212000, 0.0321892000, 0.0612604000, 0.1581291000, 0.4763507000, 1.4922742000", \ - "0.0202291000, 0.0232366000, 0.0324482000, 0.0614150000, 0.1582107000, 0.4763656000, 1.4957900000", \ - "0.0245618000, 0.0276892000, 0.0362075000, 0.0639145000, 0.1587554000, 0.4760822000, 1.4920548000", \ - "0.0336128000, 0.0368419000, 0.0449341000, 0.0705546000, 0.1614461000, 0.4754817000, 1.4926511000", \ - "0.0474977000, 0.0512071000, 0.0619531000, 0.0867678000, 0.1686170000, 0.4782090000, 1.4910144000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.3110585000, 0.3172504000, 0.3336273000, 0.3695194000, 0.4417545000, 0.5892191000, 0.9374352000", \ - "0.3127800000, 0.3191797000, 0.3355941000, 0.3715809000, 0.4434412000, 0.5912803000, 0.9391263000", \ - "0.3194079000, 0.3257943000, 0.3417628000, 0.3779203000, 0.4502843000, 0.5976453000, 0.9457015000", \ - "0.3398970000, 0.3462114000, 0.3626021000, 0.3984869000, 0.4708007000, 0.6182709000, 0.9662278000", \ - "0.3990611000, 0.4053723000, 0.4217635000, 0.4578828000, 0.5298072000, 0.6774880000, 1.0256809000", \ - "0.5436333000, 0.5497073000, 0.5654677000, 0.6000526000, 0.6718743000, 0.8174607000, 1.1653948000", \ - "0.8114407000, 0.8187266000, 0.8383094000, 0.8796452000, 0.9572032000, 1.1066177000, 1.4560900000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0688532000, 0.0725058000, 0.0825234000, 0.1084050000, 0.1800581000, 0.4019365000, 1.1124712000", \ - "0.0736062000, 0.0772628000, 0.0872979000, 0.1131922000, 0.1847907000, 0.4072825000, 1.1152105000", \ - "0.0848911000, 0.0885370000, 0.0985153000, 0.1243479000, 0.1961611000, 0.4180276000, 1.1246665000", \ - "0.1089366000, 0.1126230000, 0.1226063000, 0.1483408000, 0.2201861000, 0.4426174000, 1.1491034000", \ - "0.1438876000, 0.1482606000, 0.1593990000, 0.1863978000, 0.2587674000, 0.4815920000, 1.1883340000", \ - "0.1806834000, 0.1862489000, 0.2003267000, 0.2311591000, 0.3051920000, 0.5278019000, 1.2380603000", \ - "0.1983939000, 0.2056802000, 0.2244082000, 0.2643278000, 0.3449503000, 0.5675256000, 1.2747871000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0518893000, 0.0559179000, 0.0660463000, 0.0886613000, 0.1407176000, 0.2736480000, 0.6717947000", \ - "0.0522783000, 0.0557100000, 0.0657644000, 0.0877981000, 0.1399779000, 0.2737548000, 0.6703403000", \ - "0.0521889000, 0.0560053000, 0.0652399000, 0.0882672000, 0.1394243000, 0.2731839000, 0.6710925000", \ - "0.0522055000, 0.0560829000, 0.0654860000, 0.0882540000, 0.1400610000, 0.2735360000, 0.6720643000", \ - "0.0519813000, 0.0557948000, 0.0661301000, 0.0885273000, 0.1411355000, 0.2733639000, 0.6714394000", \ - "0.0511529000, 0.0546518000, 0.0645173000, 0.0868458000, 0.1389177000, 0.2746212000, 0.6718032000", \ - "0.0711283000, 0.0753986000, 0.0852996000, 0.1070884000, 0.1529148000, 0.2806175000, 0.6777284000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015993600, 0.0051159400, 0.0163645000, 0.0523456000, 0.1674390000, 0.5355930000"); - values("0.0194558000, 0.0224630000, 0.0317362000, 0.0608019000, 0.1576397000, 0.4758674000, 1.4979532000", \ - "0.0194579000, 0.0224621000, 0.0318045000, 0.0609183000, 0.1578312000, 0.4765524000, 1.4965551000", \ - "0.0194551000, 0.0225120000, 0.0317885000, 0.0610427000, 0.1578143000, 0.4752955000, 1.4956085000", \ - "0.0204835000, 0.0235030000, 0.0325711000, 0.0614602000, 0.1577602000, 0.4754265000, 1.4950411000", \ - "0.0255533000, 0.0283522000, 0.0370597000, 0.0644891000, 0.1585852000, 0.4758463000, 1.4952510000", \ - "0.0356467000, 0.0385614000, 0.0471194000, 0.0723618000, 0.1616285000, 0.4752353000, 1.4951923000", \ - "0.0506853000, 0.0546160000, 0.0653799000, 0.0908023000, 0.1710229000, 0.4771084000, 1.4912365000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111oi_0") { - leakage_power () { - value : 0.0011728000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0015217000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 6.5922142e-05; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004276000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 5.8325571e-05; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003562000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 3.4985087e-05; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 5.9731544e-05; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0011728000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0020010000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 6.5922142e-05; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004276000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 5.8325571e-05; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003562000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 3.4985087e-05; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 5.9731544e-05; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0011728000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0017973000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 6.5922142e-05; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004276000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 5.8325571e-05; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003562000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 3.4985087e-05; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 5.9731544e-05; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0001566000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0010558000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 4.9966978e-05; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001343000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 4.5591318e-05; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001320000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 3.1057073e-05; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 4.9454256e-05; - when : "A1&A2&B1&C1&!D1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a2111oi"; - cell_leakage_power : 0.0004219171; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0018940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032499000, 0.0032499000, 0.0032498000, 0.0032483000, 0.0032448000, 0.0032367000, 0.0032181000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002709600, -0.002712300, -0.002718400, -0.002714200, -0.002704500, -0.002682000, -0.002630300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019380000; - } - pin ("A2") { - capacitance : 0.0018450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028989000, 0.0029017000, 0.0029081000, 0.0029091000, 0.0029112000, 0.0029162000, 0.0029276000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002915000, -0.002912600, -0.002906900, -0.002907400, -0.002908300, -0.002910600, -0.002915700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019090000; - } - pin ("B1") { - capacitance : 0.0017480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026687000, 0.0026707000, 0.0026752000, 0.0026760000, 0.0026779000, 0.0026822000, 0.0026921000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002277400, -0.002301800, -0.002357900, -0.002368300, -0.002392400, -0.002447700, -0.002575400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018440000; - } - pin ("C1") { - capacitance : 0.0018950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027801000, 0.0027767000, 0.0027687000, 0.0027669000, 0.0027627000, 0.0027530000, 0.0027307000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002446000, -0.002502800, -0.002633600, -0.002638200, -0.002648700, -0.002672900, -0.002728600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020270000; - } - pin ("D1") { - capacitance : 0.0017730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019198000, 0.0019179000, 0.0019135000, 0.0019181000, 0.0019286000, 0.0019530000, 0.0020092000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001387400, -0.001388500, -0.001390900, -0.001390900, -0.001390800, -0.001390700, -0.001390600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019110000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1&!D1) | (!A2&!B1&!C1&!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0049693000, 0.0042692000, 0.0029794000, 0.0005457000, -0.003965700, -0.012346800, -0.028035000", \ - "0.0048922000, 0.0041979000, 0.0028991000, 0.0004752000, -0.004035400, -0.012406000, -0.028105700", \ - "0.0048122000, 0.0040937000, 0.0027963000, 0.0003685000, -0.004128900, -0.012500900, -0.028194200", \ - "0.0046702000, 0.0039918000, 0.0027088000, 0.0002753000, -0.004252500, -0.012634500, -0.028293100", \ - "0.0045436000, 0.0038567000, 0.0025909000, 0.0001916000, -0.004292700, -0.012708900, -0.028358000", \ - "0.0046048000, 0.0038922000, 0.0025768000, 0.0001328000, -0.004382900, -0.012714100, -0.028395800", \ - "0.0053493000, 0.0046507000, 0.0033394000, 0.0008593000, -0.003638300, -0.012092600, -0.028012400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0106551000, 0.0113995000, 0.0126968000, 0.0151845000, 0.0196624000, 0.0281350000, 0.0437375000", \ - "0.0105178000, 0.0112714000, 0.0125909000, 0.0150925000, 0.0196148000, 0.0280483000, 0.0438140000", \ - "0.0103650000, 0.0110883000, 0.0124202000, 0.0149451000, 0.0194915000, 0.0279506000, 0.0436376000", \ - "0.0102104000, 0.0109257000, 0.0122570000, 0.0147511000, 0.0193645000, 0.0278088000, 0.0436586000", \ - "0.0101120000, 0.0108275000, 0.0121288000, 0.0146134000, 0.0191551000, 0.0276636000, 0.0433042000", \ - "0.0100990000, 0.0108044000, 0.0120882000, 0.0145195000, 0.0190930000, 0.0275170000, 0.0433233000", \ - "0.0101000000, 0.0107872000, 0.0121191000, 0.0145818000, 0.0190912000, 0.0274149000, 0.0431413000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0050101000, 0.0043077000, 0.0030149000, 0.0005774000, -0.003921000, -0.012305700, -0.027985700", \ - "0.0049314000, 0.0042292000, 0.0029293000, 0.0005008000, -0.004011100, -0.012392600, -0.028078900", \ - "0.0048241000, 0.0041311000, 0.0028230000, 0.0003989000, -0.004105400, -0.012490000, -0.028169300", \ - "0.0047635000, 0.0040707000, 0.0027617000, 0.0003239000, -0.004184300, -0.012576500, -0.028261100", \ - "0.0046745000, 0.0039848000, 0.0027025000, 0.0002739000, -0.004213000, -0.012646300, -0.028261400", \ - "0.0047548000, 0.0040276000, 0.0027346000, 0.0002653000, -0.004309200, -0.012669100, -0.028309000", \ - "0.0053402000, 0.0045969000, 0.0032982000, 0.0008356000, -0.003768700, -0.012312700, -0.028255600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0126126000, 0.0133050000, 0.0146007000, 0.0170281000, 0.0215006000, 0.0299608000, 0.0455376000", \ - "0.0125329000, 0.0132334000, 0.0145406000, 0.0169809000, 0.0214811000, 0.0298907000, 0.0455403000", \ - "0.0124221000, 0.0131374000, 0.0144502000, 0.0168958000, 0.0214169000, 0.0298436000, 0.0454823000", \ - "0.0123489000, 0.0130399000, 0.0143589000, 0.0167967000, 0.0213304000, 0.0297736000, 0.0453865000", \ - "0.0122542000, 0.0129528000, 0.0142662000, 0.0166835000, 0.0212417000, 0.0296350000, 0.0453166000", \ - "0.0122425000, 0.0129397000, 0.0142529000, 0.0166771000, 0.0211926000, 0.0295733000, 0.0452725000", \ - "0.0122077000, 0.0128936000, 0.0142178000, 0.0166727000, 0.0211379000, 0.0295548000, 0.0451923000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0029777000, 0.0022839000, 0.0009850000, -0.001424500, -0.005923400, -0.014343600, -0.030113800", \ - "0.0029918000, 0.0022990000, 0.0009914000, -0.001414900, -0.005912600, -0.014339600, -0.030103100", \ - "0.0030118000, 0.0023148000, 0.0010171000, -0.001387400, -0.005896600, -0.014309400, -0.030072600", \ - "0.0028890000, 0.0022152000, 0.0009376000, -0.001469400, -0.005935500, -0.014349600, -0.030104200", \ - "0.0029654000, 0.0022635000, 0.0009394000, -0.001458500, -0.005938000, -0.014378600, -0.030095900", \ - "0.0032096000, 0.0025302000, 0.0011081000, -0.001304300, -0.005835700, -0.014323100, -0.030093400", \ - "0.0038797000, 0.0031666000, 0.0018285000, -0.000629300, -0.005093700, -0.013760200, -0.029472600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0109653000, 0.0116833000, 0.0129972000, 0.0154459000, 0.0199607000, 0.0283597000, 0.0440364000", \ - "0.0108568000, 0.0115684000, 0.0128839000, 0.0153486000, 0.0198715000, 0.0283331000, 0.0439903000", \ - "0.0107142000, 0.0114226000, 0.0127491000, 0.0152162000, 0.0197480000, 0.0282251000, 0.0438665000", \ - "0.0106040000, 0.0113106000, 0.0126195000, 0.0150624000, 0.0196389000, 0.0280755000, 0.0437516000", \ - "0.0105235000, 0.0112236000, 0.0125443000, 0.0149721000, 0.0195047000, 0.0279819000, 0.0436338000", \ - "0.0104951000, 0.0112056000, 0.0125002000, 0.0149108000, 0.0194400000, 0.0278571000, 0.0435353000", \ - "0.0104854000, 0.0111799000, 0.0124998000, 0.0149323000, 0.0194621000, 0.0279038000, 0.0435584000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0022392000, 0.0015427000, 0.0002443000, -0.002176500, -0.006712700, -0.015181000, -0.030988900", \ - "0.0022728000, 0.0015743000, 0.0002829000, -0.002126500, -0.006648400, -0.015110200, -0.030913200", \ - "0.0023444000, 0.0016654000, 0.0003849000, -0.002012300, -0.006524500, -0.014961700, -0.030754700", \ - "0.0022056000, 0.0015362000, 0.0002731000, -0.002087900, -0.006563500, -0.014972300, -0.030747200", \ - "0.0022485000, 0.0015667000, 0.0002895000, -0.002169800, -0.006617500, -0.015050300, -0.030755500", \ - "0.0023217000, 0.0016457000, 0.0002358000, -0.002163300, -0.006651100, -0.015066000, -0.030685000", \ - "0.0028273000, 0.0021414000, 0.0007826000, -0.001655100, -0.006185700, -0.014650000, -0.030354400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0098711000, 0.0105843000, 0.0119248000, 0.0144052000, 0.0189006000, 0.0272336000, 0.0428608000", \ - "0.0097178000, 0.0104372000, 0.0117821000, 0.0142581000, 0.0188140000, 0.0272600000, 0.0429482000", \ - "0.0095572000, 0.0102728000, 0.0116034000, 0.0140960000, 0.0186618000, 0.0271336000, 0.0428150000", \ - "0.0094243000, 0.0101320000, 0.0114559000, 0.0139184000, 0.0184819000, 0.0269716000, 0.0427095000", \ - "0.0093323000, 0.0100435000, 0.0113589000, 0.0138007000, 0.0183387000, 0.0267767000, 0.0425218000", \ - "0.0092942000, 0.0099825000, 0.0112886000, 0.0137682000, 0.0182891000, 0.0267143000, 0.0424006000", \ - "0.0094844000, 0.0101722000, 0.0114695000, 0.0138740000, 0.0183388000, 0.0268217000, 0.0424489000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0002045000, -0.000489300, -0.001792500, -0.004224400, -0.008765800, -0.017245300, -0.033067100", \ - "0.0001440000, -0.000541200, -0.001816600, -0.004228600, -0.008740700, -0.017197600, -0.033006300", \ - "2.510000e-05, -0.000637400, -0.001896800, -0.004268700, -0.008752800, -0.017178100, -0.032957000", \ - "-0.000140700, -0.000805200, -0.002000200, -0.004385100, -0.008815300, -0.017199500, -0.032958200", \ - "-0.000159700, -0.000827400, -0.002077700, -0.004494800, -0.008925200, -0.017285100, -0.032967400", \ - "-9.59000e-05, -0.000791100, -0.001946800, -0.004488300, -0.008928000, -0.017348100, -0.033083000", \ - "0.0006421000, -0.000103500, -0.001444600, -0.003908200, -0.008436400, -0.017049500, -0.032917000"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009327012, 0.0017398630, 0.0032455450, 0.0060542470, 0.0112936100, 0.0210671200"); - values("0.0091902000, 0.0099231000, 0.0112401000, 0.0137055000, 0.0182464000, 0.0266335000, 0.0422873000", \ - "0.0090224000, 0.0097646000, 0.0110935000, 0.0135710000, 0.0181571000, 0.0266048000, 0.0422188000", \ - "0.0088142000, 0.0095522000, 0.0109123000, 0.0133866000, 0.0179774000, 0.0264986000, 0.0421762000", \ - "0.0087154000, 0.0094301000, 0.0107111000, 0.0131631000, 0.0177688000, 0.0262710000, 0.0420385000", \ - "0.0086762000, 0.0093885000, 0.0107049000, 0.0131538000, 0.0176069000, 0.0260630000, 0.0418538000", \ - "0.0088896000, 0.0095730000, 0.0108546000, 0.0132380000, 0.0177150000, 0.0260709000, 0.0417560000", \ - "0.0096152000, 0.0102733000, 0.0115214000, 0.0139165000, 0.0182142000, 0.0264689000, 0.0417832000"); - } - } - max_capacitance : 0.0210670000; - max_transition : 1.4621900000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0427857000, 0.0476023000, 0.0561553000, 0.0715698000, 0.0987964000, 0.1470173000, 0.2333926000", \ - "0.0473242000, 0.0520489000, 0.0605279000, 0.0758654000, 0.1029342000, 0.1511635000, 0.2374605000", \ - "0.0586463000, 0.0629940000, 0.0712829000, 0.0862564000, 0.1131296000, 0.1610467000, 0.2473123000", \ - "0.0847386000, 0.0896115000, 0.0975627000, 0.1120526000, 0.1372938000, 0.1847604000, 0.2706358000", \ - "0.1229636000, 0.1299358000, 0.1419755000, 0.1621067000, 0.1942211000, 0.2429436000, 0.3278804000", \ - "0.1689841000, 0.1793915000, 0.1970073000, 0.2269288000, 0.2740012000, 0.3471725000, 0.4550645000", \ - "0.2055513000, 0.2213390000, 0.2481153000, 0.2925533000, 0.3629707000, 0.4723785000, 0.6356818000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2327915000, 0.2529649000, 0.2904252000, 0.3585241000, 0.4823342000, 0.7154078000, 1.1478410000", \ - "0.2353369000, 0.2559881000, 0.2937431000, 0.3625040000, 0.4870774000, 0.7203861000, 1.1545647000", \ - "0.2453757000, 0.2652880000, 0.3035569000, 0.3723628000, 0.4981013000, 0.7324216000, 1.1674507000", \ - "0.2723867000, 0.2920394000, 0.3293912000, 0.3984586000, 0.5265253000, 0.7587972000, 1.1951972000", \ - "0.3303081000, 0.3494936000, 0.3863661000, 0.4549623000, 0.5827517000, 0.8175803000, 1.2495150000", \ - "0.4369858000, 0.4583045000, 0.4975265000, 0.5681621000, 0.6942432000, 0.9311015000, 1.3685616000", \ - "0.6082150000, 0.6347700000, 0.6844170000, 0.7678977000, 0.9150130000, 1.1653272000, 1.6020830000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0490046000, 0.0545902000, 0.0651670000, 0.0836526000, 0.1168926000, 0.1771970000, 0.2876475000", \ - "0.0481675000, 0.0538159000, 0.0643076000, 0.0828639000, 0.1166014000, 0.1769010000, 0.2873277000", \ - "0.0476687000, 0.0530360000, 0.0630708000, 0.0816487000, 0.1156903000, 0.1759006000, 0.2876215000", \ - "0.0581361000, 0.0620213000, 0.0699190000, 0.0854403000, 0.1161938000, 0.1752280000, 0.2859167000", \ - "0.0864564000, 0.0918387000, 0.1016714000, 0.1171686000, 0.1412500000, 0.1892943000, 0.2899646000", \ - "0.1367464000, 0.1443510000, 0.1575806000, 0.1792096000, 0.2121456000, 0.2688383000, 0.3499646000", \ - "0.2253044000, 0.2367339000, 0.2557489000, 0.2885666000, 0.3395142000, 0.4173004000, 0.5361819000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.1741267000, 0.2002054000, 0.2484063000, 0.3377208000, 0.5033508000, 0.8148458000, 1.3893102000", \ - "0.1741904000, 0.2002157000, 0.2484271000, 0.3378336000, 0.5029177000, 0.8134877000, 1.3932403000", \ - "0.1738711000, 0.2002342000, 0.2484473000, 0.3382425000, 0.5034037000, 0.8135085000, 1.3897226000", \ - "0.1746774000, 0.1999968000, 0.2484331000, 0.3378454000, 0.5062922000, 0.8137463000, 1.3945040000", \ - "0.1759619000, 0.2007462000, 0.2484694000, 0.3379177000, 0.5049858000, 0.8188433000, 1.3900509000", \ - "0.1973618000, 0.2213902000, 0.2652252000, 0.3505784000, 0.5086954000, 0.8154397000, 1.3953941000", \ - "0.2553630000, 0.2800417000, 0.3281651000, 0.4150332000, 0.5721048000, 0.8540014000, 1.4087753000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0466428000, 0.0513344000, 0.0599219000, 0.0751696000, 0.1023135000, 0.1504985000, 0.2367524000", \ - "0.0513004000, 0.0559625000, 0.0644872000, 0.0797046000, 0.1067820000, 0.1549173000, 0.2411885000", \ - "0.0614880000, 0.0660907000, 0.0743998000, 0.0894418000, 0.1163707000, 0.1644535000, 0.2506852000", \ - "0.0844721000, 0.0893093000, 0.0977550000, 0.1126254000, 0.1390618000, 0.1868581000, 0.2730725000", \ - "0.1224711000, 0.1288089000, 0.1398468000, 0.1579913000, 0.1880581000, 0.2381273000, 0.3247608000", \ - "0.1748330000, 0.1840733000, 0.1999050000, 0.2263796000, 0.2683998000, 0.3345086000, 0.4366634000", \ - "0.2286955000, 0.2429787000, 0.2662248000, 0.3066665000, 0.3716610000, 0.4728060000, 0.6176978000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2654632000, 0.2851192000, 0.3219139000, 0.3900417000, 0.5158559000, 0.7503478000, 1.1872624000", \ - "0.2696209000, 0.2897279000, 0.3263953000, 0.3944880000, 0.5209538000, 0.7559600000, 1.1930591000", \ - "0.2815253000, 0.3013058000, 0.3381674000, 0.4066161000, 0.5333896000, 0.7691096000, 1.2060353000", \ - "0.3079694000, 0.3278548000, 0.3644732000, 0.4330449000, 0.5599988000, 0.7956229000, 1.2334483000", \ - "0.3618921000, 0.3819967000, 0.4185334000, 0.4868275000, 0.6135287000, 0.8490331000, 1.2872581000", \ - "0.4629306000, 0.4841963000, 0.5227009000, 0.5924164000, 0.7189120000, 0.9539647000, 1.3920682000", \ - "0.6225742000, 0.6478982000, 0.6945137000, 0.7763769000, 0.9199874000, 1.1706882000, 1.6104174000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0483014000, 0.0540794000, 0.0643134000, 0.0830472000, 0.1163461000, 0.1762655000, 0.2864621000", \ - "0.0477765000, 0.0535795000, 0.0640257000, 0.0827279000, 0.1158327000, 0.1766764000, 0.2872921000", \ - "0.0473760000, 0.0530070000, 0.0631531000, 0.0818893000, 0.1153857000, 0.1764698000, 0.2871834000", \ - "0.0539202000, 0.0584342000, 0.0671019000, 0.0839207000, 0.1155981000, 0.1755964000, 0.2869150000", \ - "0.0753376000, 0.0802371000, 0.0888848000, 0.1038556000, 0.1312033000, 0.1835587000, 0.2888076000", \ - "0.1179117000, 0.1240403000, 0.1346685000, 0.1532757000, 0.1834266000, 0.2357550000, 0.3275697000", \ - "0.1946683000, 0.2036868000, 0.2181031000, 0.2448135000, 0.2869161000, 0.3518442000, 0.4558761000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2052786000, 0.2322175000, 0.2798335000, 0.3716066000, 0.5386031000, 0.8510954000, 1.4323370000", \ - "0.2061574000, 0.2314799000, 0.2808582000, 0.3705870000, 0.5387035000, 0.8510015000, 1.4364471000", \ - "0.2060381000, 0.2313949000, 0.2808449000, 0.3705924000, 0.5384374000, 0.8540011000, 1.4318174000", \ - "0.2062259000, 0.2315835000, 0.2801608000, 0.3704966000, 0.5389137000, 0.8511168000, 1.4321021000", \ - "0.2061599000, 0.2322054000, 0.2801838000, 0.3705722000, 0.5385167000, 0.8504994000, 1.4330381000", \ - "0.2252963000, 0.2482880000, 0.2945047000, 0.3805265000, 0.5447415000, 0.8512819000, 1.4343088000", \ - "0.2804324000, 0.3058059000, 0.3555249000, 0.4428435000, 0.6004909000, 0.8908806000, 1.4490464000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0267761000, 0.0294629000, 0.0344258000, 0.0432579000, 0.0591015000, 0.0873819000, 0.1389421000", \ - "0.0319248000, 0.0345374000, 0.0393416000, 0.0481189000, 0.0638526000, 0.0921625000, 0.1436990000", \ - "0.0442694000, 0.0466879000, 0.0512934000, 0.0597965000, 0.0750633000, 0.1032919000, 0.1548318000", \ - "0.0650341000, 0.0688718000, 0.0752058000, 0.0850958000, 0.1017972000, 0.1294432000, 0.1807191000", \ - "0.0910099000, 0.0967629000, 0.1066126000, 0.1228714000, 0.1482999000, 0.1868371000, 0.2423185000", \ - "0.1167786000, 0.1253013000, 0.1418888000, 0.1669309000, 0.2066892000, 0.2664010000, 0.3524831000", \ - "0.1231984000, 0.1370269000, 0.1610109000, 0.2006257000, 0.2619877000, 0.3573516000, 0.4906729000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2468322000, 0.2667146000, 0.3035399000, 0.3721992000, 0.4988978000, 0.7336315000, 1.1710667000", \ - "0.2487926000, 0.2687432000, 0.3062517000, 0.3749425000, 0.5021631000, 0.7378793000, 1.1757523000", \ - "0.2577662000, 0.2777669000, 0.3152552000, 0.3841108000, 0.5117997000, 0.7482440000, 1.1864144000", \ - "0.2821143000, 0.3023834000, 0.3391360000, 0.4079187000, 0.5351983000, 0.7716153000, 1.2121024000", \ - "0.3368608000, 0.3564471000, 0.3932830000, 0.4618946000, 0.5887454000, 0.8245424000, 1.2634125000", \ - "0.4458603000, 0.4686317000, 0.5090708000, 0.5807995000, 0.7075380000, 0.9431013000, 1.3814920000", \ - "0.6345984000, 0.6635227000, 0.7166585000, 0.8054608000, 0.9586922000, 1.2136668000, 1.6556140000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0304180000, 0.0334935000, 0.0392077000, 0.0496685000, 0.0688558000, 0.1045066000, 0.1704667000", \ - "0.0297592000, 0.0329324000, 0.0387218000, 0.0493126000, 0.0685962000, 0.1043890000, 0.1714384000", \ - "0.0322363000, 0.0348494000, 0.0398216000, 0.0494724000, 0.0681446000, 0.1042901000, 0.1706374000", \ - "0.0468575000, 0.0491221000, 0.0532535000, 0.0608354000, 0.0756901000, 0.1068166000, 0.1703338000", \ - "0.0755974000, 0.0788778000, 0.0845312000, 0.0946205000, 0.1108819000, 0.1365442000, 0.1878940000", \ - "0.1255946000, 0.1313062000, 0.1394044000, 0.1546361000, 0.1788710000, 0.2165293000, 0.2718670000", \ - "0.2140487000, 0.2222091000, 0.2365751000, 0.2602154000, 0.2990786000, 0.3553835000, 0.4409079000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2061360000, 0.2315051000, 0.2801483000, 0.3708803000, 0.5400312000, 0.8510826000, 1.4357405000", \ - "0.2050922000, 0.2312139000, 0.2802862000, 0.3706206000, 0.5379334000, 0.8510305000, 1.4367366000", \ - "0.2052639000, 0.2322176000, 0.2798505000, 0.3703342000, 0.5381548000, 0.8514561000, 1.4325762000", \ - "0.2062443000, 0.2323644000, 0.2800170000, 0.3706832000, 0.5381546000, 0.8509368000, 1.4357210000", \ - "0.2073784000, 0.2329963000, 0.2817611000, 0.3717796000, 0.5400100000, 0.8509770000, 1.4331824000", \ - "0.2396890000, 0.2622951000, 0.3058360000, 0.3889291000, 0.5492936000, 0.8518604000, 1.4367232000", \ - "0.3242298000, 0.3491024000, 0.3966257000, 0.4787608000, 0.6281297000, 0.9027377000, 1.4506079000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0276702000, 0.0300683000, 0.0345480000, 0.0427938000, 0.0577378000, 0.0851027000, 0.1359337000", \ - "0.0325579000, 0.0349231000, 0.0393661000, 0.0475654000, 0.0626012000, 0.0899947000, 0.1408493000", \ - "0.0440781000, 0.0464925000, 0.0509399000, 0.0590027000, 0.0738222000, 0.1013099000, 0.1521812000", \ - "0.0626679000, 0.0664674000, 0.0729888000, 0.0837871000, 0.0998637000, 0.1274229000, 0.1781895000", \ - "0.0842466000, 0.0903022000, 0.1007324000, 0.1177464000, 0.1441217000, 0.1835053000, 0.2398280000", \ - "0.1027584000, 0.1121095000, 0.1296106000, 0.1564493000, 0.1982451000, 0.2601067000, 0.3456105000", \ - "0.0979928000, 0.1133235000, 0.1384948000, 0.1811768000, 0.2474239000, 0.3449193000, 0.4827280000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2216766000, 0.2417723000, 0.2789306000, 0.3478707000, 0.4749482000, 0.7101780000, 1.1475887000", \ - "0.2227049000, 0.2429147000, 0.2803011000, 0.3497084000, 0.4774677000, 0.7136127000, 1.1516128000", \ - "0.2297778000, 0.2502062000, 0.2876368000, 0.3570022000, 0.4852329000, 0.7227769000, 1.1610026000", \ - "0.2527834000, 0.2726135000, 0.3096595000, 0.3788519000, 0.5066283000, 0.7436926000, 1.1842983000", \ - "0.3083200000, 0.3281335000, 0.3652326000, 0.4338679000, 0.5611989000, 0.7980623000, 1.2376642000", \ - "0.4252322000, 0.4488038000, 0.4910136000, 0.5662681000, 0.6935559000, 0.9296072000, 1.3687754000", \ - "0.6262291000, 0.6596972000, 0.7174769000, 0.8154573000, 0.9746004000, 1.2385066000, 1.6784789000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0259414000, 0.0289408000, 0.0345054000, 0.0447914000, 0.0638538000, 0.0994946000, 0.1663911000", \ - "0.0257807000, 0.0288083000, 0.0344427000, 0.0447341000, 0.0638435000, 0.0994762000, 0.1663027000", \ - "0.0282770000, 0.0308013000, 0.0358147000, 0.0452957000, 0.0638185000, 0.0994840000, 0.1663312000", \ - "0.0429058000, 0.0452919000, 0.0496477000, 0.0569455000, 0.0720875000, 0.1026453000, 0.1662943000", \ - "0.0713085000, 0.0746740000, 0.0805637000, 0.0909843000, 0.1076510000, 0.1339033000, 0.1843548000", \ - "0.1214231000, 0.1271394000, 0.1352524000, 0.1506363000, 0.1754583000, 0.2134048000, 0.2735566000", \ - "0.2103268000, 0.2190396000, 0.2334294000, 0.2572357000, 0.2951183000, 0.3523668000, 0.4396270000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2053196000, 0.2313374000, 0.2799529000, 0.3705654000, 0.5400018000, 0.8510772000, 1.4322543000", \ - "0.2053753000, 0.2314699000, 0.2799184000, 0.3704871000, 0.5400242000, 0.8508552000, 1.4321770000", \ - "0.2051034000, 0.2320867000, 0.2801260000, 0.3704512000, 0.5382554000, 0.8519042000, 1.4326733000", \ - "0.2061411000, 0.2314478000, 0.2797837000, 0.3718898000, 0.5385678000, 0.8513591000, 1.4373498000", \ - "0.2098156000, 0.2345489000, 0.2816935000, 0.3715042000, 0.5384564000, 0.8530380000, 1.4372733000", \ - "0.2547203000, 0.2758734000, 0.3151883000, 0.3962212000, 0.5508191000, 0.8518509000, 1.4332099000", \ - "0.3593439000, 0.3854212000, 0.4293471000, 0.5154721000, 0.6551731000, 0.9210941000, 1.4536892000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0229629000, 0.0253199000, 0.0297926000, 0.0378629000, 0.0529029000, 0.0809202000, 0.1327237000", \ - "0.0278111000, 0.0302060000, 0.0347879000, 0.0427637000, 0.0578816000, 0.0858518000, 0.1378743000", \ - "0.0385982000, 0.0415344000, 0.0462108000, 0.0540983000, 0.0692751000, 0.0976515000, 0.1494902000", \ - "0.0539561000, 0.0582283000, 0.0657234000, 0.0778705000, 0.0961237000, 0.1243461000, 0.1763223000", \ - "0.0708559000, 0.0781395000, 0.0902552000, 0.1092420000, 0.1379439000, 0.1797849000, 0.2384463000", \ - "0.0824928000, 0.0941640000, 0.1127195000, 0.1441306000, 0.1906675000, 0.2560653000, 0.3477575000", \ - "0.0675176000, 0.0870846000, 0.1167890000, 0.1654763000, 0.2376048000, 0.3437696000, 0.4886160000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.1636408000, 0.1837952000, 0.2212614000, 0.2901101000, 0.4171904000, 0.6526985000, 1.0898760000", \ - "0.1632356000, 0.1843931000, 0.2217649000, 0.2913468000, 0.4189935000, 0.6551317000, 1.0933190000", \ - "0.1689428000, 0.1896694000, 0.2273811000, 0.2969027000, 0.4253488000, 0.6625392000, 1.1018553000", \ - "0.1919431000, 0.2116513000, 0.2475041000, 0.3166843000, 0.4447319000, 0.6824210000, 1.1229769000", \ - "0.2511599000, 0.2699109000, 0.3060272000, 0.3740598000, 0.4983888000, 0.7349971000, 1.1744594000", \ - "0.3751602000, 0.3989967000, 0.4407375000, 0.5134689000, 0.6363147000, 0.8691247000, 1.3071023000", \ - "0.5696984000, 0.6042526000, 0.6646321000, 0.7684663000, 0.9315707000, 1.1885047000, 1.6159526000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.0213462000, 0.0245466000, 0.0304096000, 0.0410917000, 0.0608201000, 0.0976384000, 0.1661651000", \ - "0.0213602000, 0.0245484000, 0.0304144000, 0.0410850000, 0.0608537000, 0.0974917000, 0.1661469000", \ - "0.0257780000, 0.0282182000, 0.0329436000, 0.0423709000, 0.0609696000, 0.0976725000, 0.1661763000", \ - "0.0415816000, 0.0440613000, 0.0485236000, 0.0558416000, 0.0702973000, 0.1012890000, 0.1663462000", \ - "0.0696971000, 0.0731889000, 0.0793187000, 0.0898465000, 0.1067635000, 0.1331012000, 0.1851118000", \ - "0.1207178000, 0.1259165000, 0.1363518000, 0.1506335000, 0.1753347000, 0.2125467000, 0.2706948000", \ - "0.2146026000, 0.2220957000, 0.2355890000, 0.2584322000, 0.2974749000, 0.3531494000, 0.4362840000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009327010, 0.0017398600, 0.0032455400, 0.0060542500, 0.0112936000, 0.0210671000"); - values("0.2045573000, 0.2302182000, 0.2795617000, 0.3700464000, 0.5393937000, 0.8511306000, 1.4323210000", \ - "0.2041298000, 0.2302448000, 0.2793542000, 0.3715176000, 0.5383144000, 0.8510729000, 1.4327199000", \ - "0.2023074000, 0.2291994000, 0.2799250000, 0.3700038000, 0.5391905000, 0.8508048000, 1.4331736000", \ - "0.1990606000, 0.2267869000, 0.2776911000, 0.3705833000, 0.5380097000, 0.8534764000, 1.4373946000", \ - "0.2059725000, 0.2301874000, 0.2768094000, 0.3670374000, 0.5384720000, 0.8508707000, 1.4329443000", \ - "0.2608377000, 0.2869545000, 0.3266881000, 0.4022797000, 0.5521412000, 0.8489037000, 1.4332027000", \ - "0.3576494000, 0.3888753000, 0.4434487000, 0.5367459000, 0.6880838000, 0.9430084000, 1.4621897000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111oi_1") { - leakage_power () { - value : 0.0007679000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0016064000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 4.951635e-05; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004041000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 4.9203117e-05; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003824000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 2.9261878e-05; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 5.2565696e-05; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0007679000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0020597000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 4.951635e-05; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004041000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 4.9203121e-05; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003824000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 2.9261878e-05; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 5.2565696e-05; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0007679000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0018577000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 4.951635e-05; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0004041000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 4.9203117e-05; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003824000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 2.9261986e-05; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 5.2565696e-05; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0001610000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0015384000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 4.1952329e-05; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001424000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 4.2998238e-05; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001448000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 2.7212565e-05; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 4.5938449e-05; - when : "A1&A2&B1&C1&!D1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a2111oi"; - cell_leakage_power : 0.0004022940; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044634000, 0.0044657000, 0.0044710000, 0.0044710000, 0.0044712000, 0.0044716000, 0.0044725000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003547700, -0.003550800, -0.003558000, -0.003550300, -0.003532400, -0.003491300, -0.003396400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023590000; - } - pin ("A2") { - capacitance : 0.0023500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040686000, 0.0040676000, 0.0040652000, 0.0040675000, 0.0040728000, 0.0040848000, 0.0041127000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004063500, -0.004063800, -0.004064600, -0.004064700, -0.004065000, -0.004065800, -0.004067600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024560000; - } - pin ("B1") { - capacitance : 0.0024050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041281000, 0.0041251000, 0.0041182000, 0.0041186000, 0.0041194000, 0.0041212000, 0.0041255000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003573800, -0.003596700, -0.003649400, -0.003665300, -0.003701800, -0.003785900, -0.003979800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025500000; - } - pin ("C1") { - capacitance : 0.0024310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038849000, 0.0038852000, 0.0038861000, 0.0038840000, 0.0038791000, 0.0038679000, 0.0038420000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003468600, -0.003542800, -0.003713700, -0.003719100, -0.003731500, -0.003760100, -0.003826000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025900000; - } - pin ("D1") { - capacitance : 0.0024550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027743000, 0.0027719000, 0.0027664000, 0.0027743000, 0.0027924000, 0.0028343000, 0.0029307000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001868000, -0.001869500, -0.001873100, -0.001872700, -0.001871500, -0.001869000, -0.001863100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026610000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1&!D1) | (!A2&!B1&!C1&!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0088256000, 0.0080353000, 0.0064474000, 0.0032728000, -0.003011500, -0.015481300, -0.040311000", \ - "0.0087040000, 0.0079001000, 0.0063311000, 0.0031699000, -0.003115500, -0.015566400, -0.040415400", \ - "0.0085679000, 0.0077665000, 0.0061772000, 0.0030161000, -0.003255200, -0.015700400, -0.040527700", \ - "0.0084302000, 0.0076524000, 0.0060252000, 0.0029015000, -0.003404800, -0.015878100, -0.040698100", \ - "0.0082391000, 0.0074371000, 0.0058611000, 0.0027612000, -0.003493300, -0.015920500, -0.040811400", \ - "0.0084974000, 0.0076830000, 0.0060351000, 0.0028449000, -0.003535700, -0.016020500, -0.040748100", \ - "0.0097071000, 0.0088844000, 0.0073427000, 0.0040342000, -0.002263600, -0.014910900, -0.040347700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0157701000, 0.0165969000, 0.0182367000, 0.0214060000, 0.0277117000, 0.0401954000, 0.0651089000", \ - "0.0155621000, 0.0164335000, 0.0180608000, 0.0212688000, 0.0276066000, 0.0401558000, 0.0649925000", \ - "0.0153163000, 0.0161474000, 0.0178096000, 0.0210055000, 0.0273871000, 0.0399714000, 0.0648526000", \ - "0.0151291000, 0.0159170000, 0.0175605000, 0.0207952000, 0.0271352000, 0.0397494000, 0.0647056000", \ - "0.0149653000, 0.0157843000, 0.0174033000, 0.0205573000, 0.0268988000, 0.0394592000, 0.0643957000", \ - "0.0149348000, 0.0157486000, 0.0173179000, 0.0204834000, 0.0268162000, 0.0392716000, 0.0641559000", \ - "0.0148993000, 0.0157041000, 0.0173210000, 0.0205181000, 0.0268285000, 0.0391929000, 0.0641516000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0092566000, 0.0084675000, 0.0068713000, 0.0037159000, -0.002579900, -0.015041200, -0.039873200", \ - "0.0091504000, 0.0083463000, 0.0067656000, 0.0035941000, -0.002705200, -0.015154400, -0.039976300", \ - "0.0090042000, 0.0082027000, 0.0066140000, 0.0034552000, -0.002833200, -0.015290700, -0.040124900", \ - "0.0088831000, 0.0081022000, 0.0065137000, 0.0033689000, -0.002941300, -0.015417000, -0.040249000", \ - "0.0087868000, 0.0079941000, 0.0064153000, 0.0033062000, -0.003076900, -0.015518500, -0.040296400", \ - "0.0089371000, 0.0081393000, 0.0065350000, 0.0033243000, -0.003077000, -0.015548600, -0.040387300", \ - "0.0099036000, 0.0090918000, 0.0074448000, 0.0042578000, -0.002144100, -0.014822300, -0.040042400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0189319000, 0.0197326000, 0.0213250000, 0.0244956000, 0.0307591000, 0.0432426000, 0.0679874000", \ - "0.0188103000, 0.0196178000, 0.0212188000, 0.0243994000, 0.0306909000, 0.0431897000, 0.0679459000", \ - "0.0186418000, 0.0194497000, 0.0210631000, 0.0242601000, 0.0305625000, 0.0431034000, 0.0679606000", \ - "0.0184845000, 0.0192971000, 0.0209029000, 0.0240937000, 0.0304225000, 0.0429692000, 0.0677954000", \ - "0.0183591000, 0.0191624000, 0.0207510000, 0.0239386000, 0.0302265000, 0.0427780000, 0.0675761000", \ - "0.0183119000, 0.0191174000, 0.0207226000, 0.0238927000, 0.0301865000, 0.0427115000, 0.0675153000", \ - "0.0182392000, 0.0190423000, 0.0206533000, 0.0238576000, 0.0300923000, 0.0425935000, 0.0674605000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0061823000, 0.0053802000, 0.0037891000, 0.0006448000, -0.005603500, -0.018096000, -0.043072500", \ - "0.0061910000, 0.0053917000, 0.0038121000, 0.0006583000, -0.005614200, -0.018088900, -0.043066600", \ - "0.0061776000, 0.0054071000, 0.0038145000, 0.0006613000, -0.005580600, -0.018098500, -0.043054200", \ - "0.0060266000, 0.0052391000, 0.0036773000, 0.0005525000, -0.005697600, -0.018154000, -0.043106300", \ - "0.0061514000, 0.0053549000, 0.0037448000, 0.0005339000, -0.005746600, -0.018188900, -0.043058400", \ - "0.0065912000, 0.0056439000, 0.0040434000, 0.0008898000, -0.005277100, -0.017990100, -0.042940000", \ - "0.0076113000, 0.0067871000, 0.0051683000, 0.0019743000, -0.004578500, -0.017145900, -0.042035200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0164952000, 0.0173026000, 0.0189108000, 0.0221290000, 0.0283962000, 0.0409370000, 0.0656363000", \ - "0.0162999000, 0.0171115000, 0.0187306000, 0.0219425000, 0.0282933000, 0.0407787000, 0.0656956000", \ - "0.0160873000, 0.0169091000, 0.0185323000, 0.0217513000, 0.0281000000, 0.0406742000, 0.0655718000", \ - "0.0159325000, 0.0167437000, 0.0183481000, 0.0215527000, 0.0278699000, 0.0404772000, 0.0653923000", \ - "0.0158198000, 0.0166280000, 0.0182363000, 0.0214206000, 0.0277028000, 0.0402724000, 0.0651626000", \ - "0.0157814000, 0.0165863000, 0.0181653000, 0.0213317000, 0.0276262000, 0.0401367000, 0.0650232000", \ - "0.0157766000, 0.0165743000, 0.0181746000, 0.0213375000, 0.0276678000, 0.0401926000, 0.0649525000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0049227000, 0.0041263000, 0.0025344000, -0.000632200, -0.006929000, -0.019506400, -0.044566300", \ - "0.0049865000, 0.0041955000, 0.0025984000, -0.000556100, -0.006847100, -0.019410200, -0.044465400", \ - "0.0051171000, 0.0043292000, 0.0027523000, -0.000383000, -0.006678900, -0.019221900, -0.044256600", \ - "0.0049652000, 0.0041894000, 0.0026407000, -0.000476500, -0.006697600, -0.019222700, -0.044228100", \ - "0.0050089000, 0.0042263000, 0.0027151000, -0.000410600, -0.006824400, -0.019264500, -0.044203100", \ - "0.0050795000, 0.0042866000, 0.0027072000, -0.000437700, -0.006702600, -0.019219800, -0.044287100", \ - "0.0060924000, 0.0052682000, 0.0036309000, 0.0004148000, -0.006037900, -0.018588800, -0.043836100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0143801000, 0.0151952000, 0.0168087000, 0.0200063000, 0.0263101000, 0.0387837000, 0.0636266000", \ - "0.0141958000, 0.0150101000, 0.0166364000, 0.0198404000, 0.0261861000, 0.0387304000, 0.0636035000", \ - "0.0139752000, 0.0147963000, 0.0164145000, 0.0196286000, 0.0259876000, 0.0385626000, 0.0634431000", \ - "0.0138313000, 0.0146405000, 0.0162492000, 0.0194338000, 0.0258043000, 0.0383612000, 0.0632870000", \ - "0.0137302000, 0.0145216000, 0.0161386000, 0.0193095000, 0.0256408000, 0.0382024000, 0.0631194000", \ - "0.0136724000, 0.0144893000, 0.0160857000, 0.0192795000, 0.0256179000, 0.0381002000, 0.0629094000", \ - "0.0139431000, 0.0147068000, 0.0163013000, 0.0194339000, 0.0256609000, 0.0382269000, 0.0631420000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0017555000, 0.0009496000, -0.000647500, -0.003831000, -0.010178900, -0.022784200, -0.047878700", \ - "0.0016744000, 0.0008883000, -0.000693200, -0.003846000, -0.010141300, -0.022716300, -0.047793100", \ - "0.0015272000, 0.0007605000, -0.000791000, -0.003900400, -0.010153200, -0.022670600, -0.047711700", \ - "0.0013100000, 0.0005560000, -0.000971400, -0.004032800, -0.010224600, -0.022695200, -0.047694100", \ - "0.0012273000, 0.0004631000, -0.001055800, -0.004115600, -0.010395000, -0.022805900, -0.047696400", \ - "0.0013087000, 0.0005118000, -0.001065700, -0.004198800, -0.010423200, -0.022850600, -0.047852700", \ - "0.0023781000, 0.0015309000, -6.27000e-05, -0.003354700, -0.009871700, -0.022332000, -0.047629900"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009954587, 0.0019818760, 0.0039457520, 0.0078556670, 0.0156399900, 0.0311379200"); - values("0.0136526000, 0.0144725000, 0.0160886000, 0.0193264000, 0.0256584000, 0.0381680000, 0.0630669000", \ - "0.0133721000, 0.0142133000, 0.0158686000, 0.0191165000, 0.0255078000, 0.0380765000, 0.0629917000", \ - "0.0130996000, 0.0139160000, 0.0155471000, 0.0188118000, 0.0252165000, 0.0378688000, 0.0628442000", \ - "0.0128651000, 0.0136899000, 0.0153271000, 0.0185634000, 0.0249290000, 0.0375635000, 0.0625902000", \ - "0.0129280000, 0.0136775000, 0.0152482000, 0.0184095000, 0.0247164000, 0.0373165000, 0.0622653000", \ - "0.0134967000, 0.0142729000, 0.0158554000, 0.0189093000, 0.0248848000, 0.0372522000, 0.0620555000", \ - "0.0141752000, 0.0149744000, 0.0164958000, 0.0195713000, 0.0256203000, 0.0378506000, 0.0621376000"); - } - } - max_capacitance : 0.0311380000; - max_transition : 1.4962260000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0360371000, 0.0392184000, 0.0453209000, 0.0571346000, 0.0794801000, 0.1216245000, 0.2016757000", \ - "0.0406190000, 0.0437328000, 0.0497408000, 0.0613892000, 0.0836206000, 0.1256745000, 0.2056768000", \ - "0.0519227000, 0.0548427000, 0.0606355000, 0.0719315000, 0.0937850000, 0.1356108000, 0.2154509000", \ - "0.0762122000, 0.0796765000, 0.0863394000, 0.0976838000, 0.1187520000, 0.1589918000, 0.2383997000", \ - "0.1087408000, 0.1138104000, 0.1232851000, 0.1401680000, 0.1692116000, 0.2161564000, 0.2942512000", \ - "0.1438306000, 0.1514219000, 0.1656288000, 0.1898440000, 0.2328403000, 0.3034748000, 0.4098196000", \ - "0.1587622000, 0.1699241000, 0.1896235000, 0.2275805000, 0.2924430000, 0.3981615000, 0.5639192000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2438844000, 0.2592904000, 0.2906459000, 0.3503352000, 0.4695324000, 0.7056698000, 1.1801112000", \ - "0.2465884000, 0.2626633000, 0.2937651000, 0.3540947000, 0.4740247000, 0.7165225000, 1.1788805000", \ - "0.2567157000, 0.2720182000, 0.3038269000, 0.3646920000, 0.4848588000, 0.7226010000, 1.2023050000", \ - "0.2838634000, 0.2999603000, 0.3301779000, 0.3916988000, 0.5109475000, 0.7490252000, 1.2206537000", \ - "0.3427540000, 0.3579929000, 0.3885622000, 0.4489259000, 0.5692937000, 0.8097885000, 1.2835453000", \ - "0.4543338000, 0.4708687000, 0.5030813000, 0.5660524000, 0.6857335000, 0.9218892000, 1.3913207000", \ - "0.6380268000, 0.6582409000, 0.6972310000, 0.7726358000, 0.9101356000, 1.1646830000, 1.6376550000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0421922000, 0.0460644000, 0.0536361000, 0.0679992000, 0.0958438000, 0.1487195000, 0.2502148000", \ - "0.0414006000, 0.0452933000, 0.0529621000, 0.0674758000, 0.0953444000, 0.1480206000, 0.2509588000", \ - "0.0421598000, 0.0455796000, 0.0526348000, 0.0666060000, 0.0943794000, 0.1476952000, 0.2496430000", \ - "0.0547491000, 0.0580184000, 0.0629966000, 0.0738381000, 0.0973910000, 0.1471725000, 0.2499719000", \ - "0.0825406000, 0.0864115000, 0.0935758000, 0.1065424000, 0.1284378000, 0.1672252000, 0.2566785000", \ - "0.1311969000, 0.1367585000, 0.1471632000, 0.1652132000, 0.1958100000, 0.2451058000, 0.3279870000", \ - "0.2177443000, 0.2260393000, 0.2438233000, 0.2690973000, 0.3139726000, 0.3891342000, 0.5017994000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.1792211000, 0.1991000000, 0.2396399000, 0.3181912000, 0.4753895000, 0.7875030000, 1.4120938000", \ - "0.1792531000, 0.1996764000, 0.2396068000, 0.3182095000, 0.4756679000, 0.7911314000, 1.4065924000", \ - "0.1796127000, 0.1995713000, 0.2395865000, 0.3179002000, 0.4762205000, 0.7871963000, 1.4145554000", \ - "0.1797315000, 0.1999248000, 0.2390506000, 0.3182279000, 0.4749243000, 0.7873361000, 1.4088321000", \ - "0.1804381000, 0.2002998000, 0.2398751000, 0.3183145000, 0.4759669000, 0.7894437000, 1.4120592000", \ - "0.1997620000, 0.2189384000, 0.2548732000, 0.3290993000, 0.4813855000, 0.7881057000, 1.4093112000", \ - "0.2533392000, 0.2730293000, 0.3127857000, 0.3905811000, 0.5422370000, 0.8253889000, 1.4238386000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0410659000, 0.0441829000, 0.0503149000, 0.0620259000, 0.0843167000, 0.1264635000, 0.2064993000", \ - "0.0457465000, 0.0488781000, 0.0548846000, 0.0665592000, 0.0887508000, 0.1307687000, 0.2108154000", \ - "0.0560891000, 0.0591103000, 0.0650060000, 0.0764743000, 0.0984953000, 0.1404187000, 0.2202988000", \ - "0.0781380000, 0.0815140000, 0.0878403000, 0.0997324000, 0.1213786000, 0.1628733000, 0.2425857000", \ - "0.1123173000, 0.1169048000, 0.1253308000, 0.1407170000, 0.1675506000, 0.2132324000, 0.2941315000", \ - "0.1559477000, 0.1622261000, 0.1750531000, 0.1980812000, 0.2365673000, 0.2998894000, 0.4008502000", \ - "0.1904545000, 0.2007793000, 0.2198972000, 0.2539723000, 0.3148800000, 0.4124906000, 0.5618762000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2883347000, 0.3038025000, 0.3346436000, 0.3960277000, 0.5173701000, 0.7583514000, 1.2361687000", \ - "0.2921752000, 0.3076164000, 0.3389397000, 0.4004388000, 0.5221690000, 0.7633467000, 1.2415948000", \ - "0.3032711000, 0.3188099000, 0.3502607000, 0.4118778000, 0.5341091000, 0.7760044000, 1.2548086000", \ - "0.3295881000, 0.3452432000, 0.3761388000, 0.4380079000, 0.5602468000, 0.8025327000, 1.2818162000", \ - "0.3833753000, 0.3993654000, 0.4302931000, 0.4918356000, 0.6136344000, 0.8556177000, 1.3362973000", \ - "0.4859088000, 0.5026244000, 0.5349349000, 0.5975432000, 0.7193917000, 0.9604271000, 1.4408784000", \ - "0.6512726000, 0.6708715000, 0.7090765000, 0.7821589000, 0.9198970000, 1.1759812000, 1.6579031000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0418914000, 0.0458179000, 0.0532591000, 0.0679792000, 0.0956462000, 0.1484382000, 0.2505465000", \ - "0.0413751000, 0.0452693000, 0.0529103000, 0.0676168000, 0.0952540000, 0.1477840000, 0.2499043000", \ - "0.0414985000, 0.0452017000, 0.0524569000, 0.0666799000, 0.0945670000, 0.1477602000, 0.2498797000", \ - "0.0497506000, 0.0527944000, 0.0588899000, 0.0708622000, 0.0960854000, 0.1473803000, 0.2500302000", \ - "0.0726995000, 0.0762274000, 0.0831481000, 0.0955659000, 0.1160935000, 0.1589680000, 0.2555672000", \ - "0.1150887000, 0.1199004000, 0.1289246000, 0.1437045000, 0.1698865000, 0.2163564000, 0.2994327000", \ - "0.1907062000, 0.1975157000, 0.2097935000, 0.2315230000, 0.2689167000, 0.3333545000, 0.4353797000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2174081000, 0.2380815000, 0.2792213000, 0.3598143000, 0.5216149000, 0.8414930000, 1.4730394000", \ - "0.2175153000, 0.2381078000, 0.2791591000, 0.3598187000, 0.5222243000, 0.8422728000, 1.4720478000", \ - "0.2175386000, 0.2380971000, 0.2797902000, 0.3600588000, 0.5209833000, 0.8413530000, 1.4757222000", \ - "0.2177834000, 0.2380937000, 0.2791704000, 0.3598394000, 0.5210134000, 0.8414203000, 1.4720328000", \ - "0.2185220000, 0.2392705000, 0.2790697000, 0.3608006000, 0.5209133000, 0.8421269000, 1.4739611000", \ - "0.2343130000, 0.2528541000, 0.2918307000, 0.3696316000, 0.5265484000, 0.8400200000, 1.4769376000", \ - "0.2852622000, 0.3053449000, 0.3475192000, 0.4263312000, 0.5795424000, 0.8775364000, 1.4886771000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0245600000, 0.0264606000, 0.0302425000, 0.0374207000, 0.0511606000, 0.0771515000, 0.1272972000", \ - "0.0296798000, 0.0315607000, 0.0351928000, 0.0422979000, 0.0558194000, 0.0818116000, 0.1319845000", \ - "0.0417155000, 0.0437407000, 0.0470619000, 0.0538369000, 0.0670745000, 0.0927143000, 0.1427638000", \ - "0.0605782000, 0.0633624000, 0.0685213000, 0.0776697000, 0.0926594000, 0.1183504000, 0.1680630000", \ - "0.0830888000, 0.0873338000, 0.0951972000, 0.1090638000, 0.1328997000, 0.1706154000, 0.2278377000", \ - "0.0993118000, 0.1068871000, 0.1193724000, 0.1410631000, 0.1774201000, 0.2364468000, 0.3253096000", \ - "0.0859753000, 0.0962292000, 0.1154106000, 0.1497412000, 0.2085060000, 0.3010830000, 0.4393489000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2673640000, 0.2829265000, 0.3143152000, 0.3760088000, 0.4979405000, 0.7394266000, 1.2176382000", \ - "0.2692610000, 0.2851289000, 0.3164122000, 0.3785668000, 0.5011423000, 0.7428346000, 1.2224106000", \ - "0.2783098000, 0.2939570000, 0.3255572000, 0.3876575000, 0.5105608000, 0.7537097000, 1.2336864000", \ - "0.3036540000, 0.3192158000, 0.3504440000, 0.4123752000, 0.5348250000, 0.7777185000, 1.2588750000", \ - "0.3607918000, 0.3763431000, 0.4073095000, 0.4688481000, 0.5909223000, 0.8329629000, 1.3139261000", \ - "0.4778687000, 0.4950386000, 0.5290479000, 0.5926207000, 0.7144678000, 0.9558579000, 1.4357684000", \ - "0.6861217000, 0.7081572000, 0.7501418000, 0.8288147000, 0.9752917000, 1.2364926000, 1.7183546000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0288042000, 0.0309796000, 0.0353175000, 0.0437648000, 0.0602101000, 0.0925224000, 0.1565877000", \ - "0.0282550000, 0.0303572000, 0.0347207000, 0.0432746000, 0.0598663000, 0.0923769000, 0.1565597000", \ - "0.0315322000, 0.0332136000, 0.0367203000, 0.0441877000, 0.0597619000, 0.0919308000, 0.1563348000", \ - "0.0468668000, 0.0484653000, 0.0515112000, 0.0572783000, 0.0692576000, 0.0964156000, 0.1566130000", \ - "0.0749717000, 0.0773542000, 0.0818836000, 0.0904170000, 0.1049897000, 0.1301134000, 0.1773051000", \ - "0.1250398000, 0.1282458000, 0.1351672000, 0.1481878000, 0.1709319000, 0.2071340000, 0.2656562000", \ - "0.2124498000, 0.2186524000, 0.2299008000, 0.2498997000, 0.2844370000, 0.3403412000, 0.4290740000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2174994000, 0.2380907000, 0.2791965000, 0.3597775000, 0.5213995000, 0.8415044000, 1.4729452000", \ - "0.2177993000, 0.2378980000, 0.2789475000, 0.3600061000, 0.5222341000, 0.8394154000, 1.4772370000", \ - "0.2173724000, 0.2380857000, 0.2792935000, 0.3598014000, 0.5217568000, 0.8403130000, 1.4771044000", \ - "0.2174588000, 0.2380973000, 0.2792294000, 0.3599067000, 0.5208610000, 0.8396586000, 1.4770694000", \ - "0.2192455000, 0.2390047000, 0.2802622000, 0.3601253000, 0.5207817000, 0.8421844000, 1.4768974000", \ - "0.2456085000, 0.2635769000, 0.3007414000, 0.3765814000, 0.5303869000, 0.8418164000, 1.4776151000", \ - "0.3265911000, 0.3457984000, 0.3845189000, 0.4588807000, 0.6043003000, 0.8878531000, 1.4920077000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0243466000, 0.0260540000, 0.0294436000, 0.0359857000, 0.0486161000, 0.0733274000, 0.1219969000", \ - "0.0292151000, 0.0308843000, 0.0341431000, 0.0406753000, 0.0533249000, 0.0780404000, 0.1267182000", \ - "0.0404628000, 0.0422782000, 0.0456038000, 0.0520130000, 0.0643784000, 0.0891158000, 0.1377330000", \ - "0.0569639000, 0.0597319000, 0.0649171000, 0.0741480000, 0.0896702000, 0.1145959000, 0.1631508000", \ - "0.0746979000, 0.0791503000, 0.0866512000, 0.1014752000, 0.1263266000, 0.1648952000, 0.2227769000", \ - "0.0841658000, 0.0912163000, 0.1042941000, 0.1274824000, 0.1662610000, 0.2269953000, 0.3178297000", \ - "0.0558854000, 0.0671351000, 0.0880282000, 0.1250347000, 0.1873398000, 0.2832788000, 0.4266623000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2287418000, 0.2445499000, 0.2760527000, 0.3377864000, 0.4598093000, 0.7008802000, 1.1798177000", \ - "0.2306773000, 0.2462870000, 0.2780534000, 0.3401326000, 0.4626306000, 0.7047521000, 1.1837806000", \ - "0.2392481000, 0.2551103000, 0.2863326000, 0.3486971000, 0.4715467000, 0.7146055000, 1.1940740000", \ - "0.2635829000, 0.2793293000, 0.3104356000, 0.3725326000, 0.4948704000, 0.7375452000, 1.2185596000", \ - "0.3221730000, 0.3375457000, 0.3689918000, 0.4306258000, 0.5525745000, 0.7946830000, 1.2753039000", \ - "0.4473877000, 0.4653398000, 0.5006726000, 0.5679109000, 0.6895124000, 0.9314783000, 1.4113620000", \ - "0.6712884000, 0.6968396000, 0.7442688000, 0.8301762000, 0.9819379000, 1.2524296000, 1.7333792000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0246019000, 0.0266631000, 0.0307567000, 0.0387752000, 0.0547500000, 0.0865295000, 0.1500746000", \ - "0.0243104000, 0.0263949000, 0.0305519000, 0.0386988000, 0.0546995000, 0.0865158000, 0.1500574000", \ - "0.0279115000, 0.0295846000, 0.0329899000, 0.0400380000, 0.0550552000, 0.0866278000, 0.1500183000", \ - "0.0429138000, 0.0446641000, 0.0479406000, 0.0540037000, 0.0656139000, 0.0921284000, 0.1516402000", \ - "0.0702977000, 0.0727912000, 0.0785186000, 0.0870645000, 0.1015303000, 0.1270947000, 0.1730111000", \ - "0.1192490000, 0.1231695000, 0.1306449000, 0.1438764000, 0.1665530000, 0.2042341000, 0.2615539000", \ - "0.2086684000, 0.2147901000, 0.2262757000, 0.2467786000, 0.2815717000, 0.3382316000, 0.4222422000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2174595000, 0.2378675000, 0.2792903000, 0.3597061000, 0.5223866000, 0.8395881000, 1.4747797000", \ - "0.2174895000, 0.2380993000, 0.2798366000, 0.3599811000, 0.5213147000, 0.8422605000, 1.4745829000", \ - "0.2180846000, 0.2380301000, 0.2788842000, 0.3611618000, 0.5219165000, 0.8402660000, 1.4732339000", \ - "0.2174012000, 0.2378369000, 0.2797558000, 0.3604415000, 0.5207138000, 0.8400452000, 1.4744248000", \ - "0.2203483000, 0.2402036000, 0.2796084000, 0.3611330000, 0.5215210000, 0.8421668000, 1.4773828000", \ - "0.2576544000, 0.2744725000, 0.3096295000, 0.3832145000, 0.5315650000, 0.8421446000, 1.4759726000", \ - "0.3623249000, 0.3823890000, 0.4200050000, 0.4927234000, 0.6294135000, 0.9032852000, 1.4872467000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0212846000, 0.0229046000, 0.0260763000, 0.0324210000, 0.0449639000, 0.0696183000, 0.1186578000", \ - "0.0259574000, 0.0276664000, 0.0308306000, 0.0371578000, 0.0497100000, 0.0744916000, 0.1235943000", \ - "0.0359689000, 0.0380792000, 0.0418781000, 0.0484598000, 0.0609925000, 0.0854790000, 0.1346102000", \ - "0.0485518000, 0.0518760000, 0.0579311000, 0.0683628000, 0.0852971000, 0.1117290000, 0.1607712000", \ - "0.0603120000, 0.0656437000, 0.0752516000, 0.0918602000, 0.1185628000, 0.1595464000, 0.2197114000", \ - "0.0598846000, 0.0684452000, 0.0839949000, 0.1106217000, 0.1534700000, 0.2183678000, 0.3134749000", \ - "0.0164194000, 0.0301449000, 0.0551986000, 0.0977700000, 0.1670653000, 0.2701098000, 0.4212426000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.1748793000, 0.1904811000, 0.2225552000, 0.2847977000, 0.4073951000, 0.6490447000, 1.1283884000", \ - "0.1746997000, 0.1909742000, 0.2228850000, 0.2855418000, 0.4089531000, 0.6516084000, 1.1315642000", \ - "0.1809250000, 0.1967215000, 0.2279223000, 0.2909974000, 0.4151897000, 0.6591225000, 1.1399256000", \ - "0.2035372000, 0.2192111000, 0.2504666000, 0.3128343000, 0.4354840000, 0.6795517000, 1.1608402000", \ - "0.2655585000, 0.2804219000, 0.3111627000, 0.3722463000, 0.4942134000, 0.7366640000, 1.2176370000", \ - "0.4054050000, 0.4234276000, 0.4574761000, 0.5198926000, 0.6364838000, 0.8758624000, 1.3539918000", \ - "0.6293597000, 0.6571360000, 0.7066757000, 0.7967305000, 0.9528391000, 1.2100028000, 1.6768126000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.0199226000, 0.0221109000, 0.0263863000, 0.0346923000, 0.0510690000, 0.0835792000, 0.1480371000", \ - "0.0200563000, 0.0221385000, 0.0263804000, 0.0347005000, 0.0510821000, 0.0835554000, 0.1485744000", \ - "0.0253897000, 0.0268817000, 0.0301637000, 0.0370512000, 0.0517748000, 0.0835407000, 0.1479681000", \ - "0.0413062000, 0.0430844000, 0.0463979000, 0.0526736000, 0.0638283000, 0.0897117000, 0.1493095000", \ - "0.0691082000, 0.0715865000, 0.0765545000, 0.0852611000, 0.1007475000, 0.1262416000, 0.1732153000", \ - "0.1202257000, 0.1238601000, 0.1307321000, 0.1439140000, 0.1660658000, 0.2032294000, 0.2607894000", \ - "0.2141682000, 0.2192281000, 0.2296131000, 0.2494342000, 0.2827352000, 0.3387292000, 0.4224397000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009954590, 0.0019818800, 0.0039457500, 0.0078556700, 0.0156400000, 0.0311379000"); - values("0.2158328000, 0.2371655000, 0.2783720000, 0.3601615000, 0.5221399000, 0.8396978000, 1.4773419000", \ - "0.2153276000, 0.2364691000, 0.2785576000, 0.3597511000, 0.5206527000, 0.8393422000, 1.4764379000", \ - "0.2142676000, 0.2354470000, 0.2780553000, 0.3598188000, 0.5205165000, 0.8421402000, 1.4760132000", \ - "0.2109600000, 0.2334977000, 0.2756981000, 0.3584990000, 0.5206688000, 0.8403299000, 1.4731065000", \ - "0.2143524000, 0.2341487000, 0.2748418000, 0.3542468000, 0.5189407000, 0.8420458000, 1.4763905000", \ - "0.2691199000, 0.2872484000, 0.3210062000, 0.3877609000, 0.5324846000, 0.8412728000, 1.4728783000", \ - "0.3690266000, 0.3929555000, 0.4380396000, 0.5194155000, 0.6633735000, 0.9240099000, 1.4962257000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111oi_2") { - leakage_power () { - value : 0.0015199000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0032827000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001769000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0016900000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002059000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0019151000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001026000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002221000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0015199000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0041276000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001769000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0016900000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002062000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0019151000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001037000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002221000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0015199000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0040104000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001769000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0016900000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002063000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0019151000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001025000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002221000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0003607000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0037175000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001302000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0003838000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002334000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0004051000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 8.6054549e-05; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0001598000; - when : "A1&A2&B1&C1&!D1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__a2111oi"; - cell_leakage_power : 0.0010748780; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0048170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0097740000, 0.0097773000, 0.0097849000, 0.0097880000, 0.0097953000, 0.0098122000, 0.0098511000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007508900, -0.007526400, -0.007566600, -0.007550400, -0.007513000, -0.007426700, -0.007227900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049810000; - } - pin ("A2") { - capacitance : 0.0044720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078534000, 0.0078553000, 0.0078597000, 0.0078581000, 0.0078543000, 0.0078456000, 0.0078255000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007855300, -0.007852900, -0.007847300, -0.007846800, -0.007845700, -0.007843100, -0.007837000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046910000; - } - pin ("B1") { - capacitance : 0.0043640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072272000, 0.0072317000, 0.0072421000, 0.0072401000, 0.0072355000, 0.0072249000, 0.0072003000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006516300, -0.006572200, -0.006700800, -0.006735500, -0.006815400, -0.006999600, -0.007424200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046930000; - } - pin ("C1") { - capacitance : 0.0047370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078615000, 0.0078624000, 0.0078644000, 0.0078626000, 0.0078583000, 0.0078485000, 0.0078258000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007001200, -0.007144500, -0.007474800, -0.007489800, -0.007524400, -0.007604200, -0.007788100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050980000; - } - pin ("D1") { - capacitance : 0.0044040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051207000, 0.0051139000, 0.0050983000, 0.0051128000, 0.0051461000, 0.0052230000, 0.0054002000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003421100, -0.003426400, -0.003438500, -0.003436900, -0.003433000, -0.003424100, -0.003403600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047680000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1&!D1) | (!A2&!B1&!C1&!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0148362000, 0.0138724000, 0.0117485000, 0.0070432000, -0.003242500, -0.025810800, -0.075390900", \ - "0.0146034000, 0.0136116000, 0.0114995000, 0.0068213000, -0.003459200, -0.026065500, -0.075634900", \ - "0.0142958000, 0.0133378000, 0.0112391000, 0.0065441000, -0.003759200, -0.026291000, -0.075879800", \ - "0.0139055000, 0.0129579000, 0.0108455000, 0.0061776000, -0.004029300, -0.026691800, -0.076196200", \ - "0.0135538000, 0.0126201000, 0.0105183000, 0.0059213000, -0.004299300, -0.026772200, -0.076430400", \ - "0.0140028000, 0.0130120000, 0.0108355000, 0.0060837000, -0.004088400, -0.026808300, -0.076407300", \ - "0.0168407000, 0.0158279000, 0.0136081000, 0.0087972000, -0.001829600, -0.025042400, -0.075820600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0298177000, 0.0308745000, 0.0330231000, 0.0379080000, 0.0483368000, 0.0708264000, 0.1206304000", \ - "0.0293174000, 0.0303390000, 0.0326223000, 0.0374324000, 0.0479591000, 0.0706994000, 0.1204447000", \ - "0.0287595000, 0.0297831000, 0.0320581000, 0.0369636000, 0.0476297000, 0.0703343000, 0.1202298000", \ - "0.0283839000, 0.0293856000, 0.0315849000, 0.0363804000, 0.0468367000, 0.0698571000, 0.1199657000", \ - "0.0281193000, 0.0290900000, 0.0312354000, 0.0359583000, 0.0463226000, 0.0691563000, 0.1191447000", \ - "0.0280630000, 0.0290363000, 0.0311663000, 0.0358635000, 0.0461839000, 0.0689525000, 0.1185659000", \ - "0.0280689000, 0.0290948000, 0.0312219000, 0.0359124000, 0.0462164000, 0.0686271000, 0.1183989000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0153904000, 0.0144202000, 0.0122948000, 0.0076100000, -0.002693100, -0.025251200, -0.074876000", \ - "0.0151782000, 0.0141894000, 0.0120737000, 0.0073780000, -0.002901600, -0.025504000, -0.075073800", \ - "0.0149330000, 0.0139488000, 0.0118139000, 0.0071363000, -0.003155700, -0.025768800, -0.075335200", \ - "0.0146810000, 0.0137122000, 0.0116239000, 0.0069740000, -0.003382500, -0.025967900, -0.075554700", \ - "0.0144645000, 0.0135090000, 0.0114068000, 0.0067652000, -0.003432400, -0.025881100, -0.075646100", \ - "0.0147249000, 0.0137195000, 0.0115615000, 0.0069061000, -0.003511400, -0.026237600, -0.075846800", \ - "0.0165650000, 0.0155901000, 0.0134123000, 0.0086540000, -0.001866900, -0.024864500, -0.075245700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0367208000, 0.0377169000, 0.0398504000, 0.0445678000, 0.0548290000, 0.0774586000, 0.1269977000", \ - "0.0363964000, 0.0373951000, 0.0395523000, 0.0442717000, 0.0546480000, 0.0773475000, 0.1269924000", \ - "0.0359782000, 0.0369738000, 0.0391626000, 0.0439218000, 0.0543257000, 0.0770674000, 0.1266411000", \ - "0.0356449000, 0.0366462000, 0.0387983000, 0.0435524000, 0.0539484000, 0.0766599000, 0.1265348000", \ - "0.0354175000, 0.0363848000, 0.0385337000, 0.0432498000, 0.0535819000, 0.0762831000, 0.1259889000", \ - "0.0353744000, 0.0363660000, 0.0385170000, 0.0431861000, 0.0535318000, 0.0761137000, 0.1258326000", \ - "0.0353734000, 0.0363597000, 0.0384965000, 0.0432219000, 0.0535036000, 0.0760674000, 0.1257257000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0101771000, 0.0092177000, 0.0070971000, 0.0024147000, -0.007831300, -0.030357000, -0.080175600", \ - "0.0101861000, 0.0092233000, 0.0070900000, 0.0024175000, -0.007818100, -0.030356500, -0.080175600", \ - "0.0101833000, 0.0092358000, 0.0071288000, 0.0024312000, -0.007808900, -0.030334900, -0.080146700", \ - "0.0097661000, 0.0088110000, 0.0067313000, 0.0021341000, -0.007998600, -0.030480100, -0.080264800", \ - "0.0097692000, 0.0087899000, 0.0066786000, 0.0020777000, -0.008032200, -0.030487400, -0.080266400", \ - "0.0108700000, 0.0099252000, 0.0078482000, 0.0028481000, -0.007481400, -0.029920100, -0.080059000", \ - "0.0135040000, 0.0125059000, 0.0103327000, 0.0054650000, -0.004890300, -0.027451100, -0.078028800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0328367000, 0.0338408000, 0.0360371000, 0.0408085000, 0.0511843000, 0.0738418000, 0.1234503000", \ - "0.0323746000, 0.0333916000, 0.0356101000, 0.0403944000, 0.0508515000, 0.0736395000, 0.1233067000", \ - "0.0318419000, 0.0328456000, 0.0350460000, 0.0398298000, 0.0503367000, 0.0731960000, 0.1230654000", \ - "0.0314834000, 0.0324750000, 0.0346564000, 0.0394158000, 0.0498425000, 0.0726293000, 0.1225843000", \ - "0.0312048000, 0.0321789000, 0.0343308000, 0.0390610000, 0.0493829000, 0.0720835000, 0.1219827000", \ - "0.0312258000, 0.0321532000, 0.0343024000, 0.0389817000, 0.0492861000, 0.0719465000, 0.1217413000", \ - "0.0313172000, 0.0322911000, 0.0344164000, 0.0391063000, 0.0495285000, 0.0720981000, 0.1215938000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0070500000, 0.0060776000, 0.0039461000, -0.000751400, -0.011076800, -0.033805500, -0.083874100", \ - "0.0071181000, 0.0061553000, 0.0040315000, -0.000635600, -0.010927900, -0.033628100, -0.083693300", \ - "0.0072969000, 0.0063470000, 0.0042626000, -0.000366400, -0.010612900, -0.033249600, -0.083279600", \ - "0.0069828000, 0.0060529000, 0.0040141000, -0.000550200, -0.010680600, -0.033220800, -0.083190800", \ - "0.0070747000, 0.0061342000, 0.0040623000, -0.000521000, -0.010743200, -0.033235900, -0.083150800", \ - "0.0073465000, 0.0063810000, 0.0042705000, -0.000373400, -0.010595000, -0.032881700, -0.083111900", \ - "0.0095384000, 0.0085228000, 0.0063217000, 0.0015304000, -0.008886500, -0.031091500, -0.081654100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0276524000, 0.0286506000, 0.0308609000, 0.0355941000, 0.0460230000, 0.0686115000, 0.1182474000", \ - "0.0272493000, 0.0282503000, 0.0304569000, 0.0352720000, 0.0457014000, 0.0684290000, 0.1181198000", \ - "0.0268451000, 0.0278511000, 0.0300324000, 0.0348086000, 0.0452748000, 0.0680617000, 0.1178925000", \ - "0.0264967000, 0.0275141000, 0.0296790000, 0.0344319000, 0.0448339000, 0.0676454000, 0.1175379000", \ - "0.0263045000, 0.0272865000, 0.0294315000, 0.0341725000, 0.0445054000, 0.0672671000, 0.1171241000", \ - "0.0262159000, 0.0271658000, 0.0293120000, 0.0340932000, 0.0443650000, 0.0670598000, 0.1166244000", \ - "0.0269320000, 0.0278857000, 0.0299278000, 0.0345965000, 0.0447909000, 0.0672674000, 0.1170095000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0007378000, -0.000231600, -0.002374000, -0.007114500, -0.017543900, -0.040410600, -0.090582300", \ - "0.0005597000, -0.000385200, -0.002485500, -0.007151200, -0.017492900, -0.040279600, -0.090411300", \ - "0.0002528000, -0.000673600, -0.002730200, -0.007293500, -0.017498200, -0.040157000, -0.090217100", \ - "-0.000115900, -0.001033600, -0.003038700, -0.007560000, -0.017643000, -0.040165000, -0.090099200", \ - "-8.87000e-05, -0.001023800, -0.003051300, -0.007542000, -0.017748300, -0.040173400, -0.090016100", \ - "0.0002577000, -0.000711200, -0.002849200, -0.007529700, -0.017741900, -0.040214700, -0.089977300", \ - "0.0024870000, 0.0014318000, -0.000796000, -0.005654600, -0.016155400, -0.039482000, -0.089627000"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011002670, 0.0024211770, 0.0053278830, 0.0117241900, 0.0257994900, 0.0567726800"); - values("0.0253605000, 0.0263488000, 0.0285501000, 0.0332794000, 0.0436681000, 0.0663165000, 0.1158221000", \ - "0.0249474000, 0.0259592000, 0.0281638000, 0.0329443000, 0.0433742000, 0.0661332000, 0.1158511000", \ - "0.0245185000, 0.0254705000, 0.0276628000, 0.0324354000, 0.0429224000, 0.0657447000, 0.1155754000", \ - "0.0242751000, 0.0251679000, 0.0273283000, 0.0320724000, 0.0424307000, 0.0652722000, 0.1151806000", \ - "0.0243647000, 0.0253412000, 0.0274380000, 0.0321080000, 0.0422077000, 0.0649082000, 0.1148539000", \ - "0.0251084000, 0.0261139000, 0.0281904000, 0.0328459000, 0.0431266000, 0.0652809000, 0.1146652000", \ - "0.0269683000, 0.0278133000, 0.0298344000, 0.0343689000, 0.0443262000, 0.0661988000, 0.1153576000"); - } - } - max_capacitance : 0.0567730000; - max_transition : 1.4971110000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0315105000, 0.0336710000, 0.0383103000, 0.0481322000, 0.0685247000, 0.1105197000, 0.1970978000", \ - "0.0361997000, 0.0383199000, 0.0428555000, 0.0525453000, 0.0727474000, 0.1145783000, 0.2010859000", \ - "0.0480067000, 0.0499149000, 0.0541455000, 0.0633775000, 0.0831039000, 0.1244757000, 0.2108390000", \ - "0.0712495000, 0.0737230000, 0.0788752000, 0.0890653000, 0.1085888000, 0.1481288000, 0.2337802000", \ - "0.1025298000, 0.1060857000, 0.1135145000, 0.1281858000, 0.1560672000, 0.2044914000, 0.2897854000", \ - "0.1363868000, 0.1415304000, 0.1523397000, 0.1740144000, 0.2126213000, 0.2860878000, 0.4058363000", \ - "0.1503569000, 0.1580136000, 0.1738665000, 0.2060062000, 0.2660979000, 0.3762886000, 0.5577644000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2347744000, 0.2453409000, 0.2681581000, 0.3178505000, 0.4252734000, 0.6545668000, 1.1614438000", \ - "0.2362424000, 0.2467895000, 0.2703091000, 0.3193490000, 0.4268907000, 0.6597192000, 1.1679299000", \ - "0.2447209000, 0.2552135000, 0.2785082000, 0.3287074000, 0.4370954000, 0.6732850000, 1.1793068000", \ - "0.2690107000, 0.2795432000, 0.3025157000, 0.3516541000, 0.4583867000, 0.6947584000, 1.2094140000", \ - "0.3212463000, 0.3311041000, 0.3538979000, 0.4027058000, 0.5084168000, 0.7411297000, 1.2520230000", \ - "0.4133291000, 0.4244563000, 0.4498859000, 0.5018150000, 0.6104140000, 0.8438586000, 1.3515914000", \ - "0.5578352000, 0.5726510000, 0.6017101000, 0.6635146000, 0.7894210000, 1.0429713000, 1.5585062000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0393488000, 0.0419186000, 0.0475444000, 0.0594659000, 0.0844151000, 0.1363494000, 0.2455342000", \ - "0.0382461000, 0.0409480000, 0.0466714000, 0.0587749000, 0.0838004000, 0.1359038000, 0.2455353000", \ - "0.0398480000, 0.0421376000, 0.0471073000, 0.0580497000, 0.0823970000, 0.1348625000, 0.2450359000", \ - "0.0537213000, 0.0556120000, 0.0595559000, 0.0675105000, 0.0875721000, 0.1347961000, 0.2440006000", \ - "0.0808837000, 0.0833758000, 0.0886244000, 0.0996436000, 0.1203367000, 0.1578368000, 0.2514410000", \ - "0.1292447000, 0.1332095000, 0.1412921000, 0.1553341000, 0.1849123000, 0.2348384000, 0.3231706000", \ - "0.2107816000, 0.2166156000, 0.2291465000, 0.2521988000, 0.2971089000, 0.3710387000, 0.4909019000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.1570067000, 0.1704326000, 0.1999511000, 0.2650389000, 0.4063285000, 0.7147021000, 1.3939139000", \ - "0.1581137000, 0.1706010000, 0.2006400000, 0.2643515000, 0.4054576000, 0.7156746000, 1.3954469000", \ - "0.1574180000, 0.1708037000, 0.2004190000, 0.2650221000, 0.4072019000, 0.7173972000, 1.3940696000", \ - "0.1576920000, 0.1709119000, 0.2010706000, 0.2650683000, 0.4051955000, 0.7171433000, 1.3993301000", \ - "0.1588714000, 0.1721624000, 0.2010704000, 0.2646714000, 0.4055519000, 0.7151520000, 1.3946433000", \ - "0.1807108000, 0.1930624000, 0.2207980000, 0.2804007000, 0.4149625000, 0.7189893000, 1.3956969000", \ - "0.2255096000, 0.2398345000, 0.2687281000, 0.3346130000, 0.4729289000, 0.7677083000, 1.4138217000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0365295000, 0.0386313000, 0.0432086000, 0.0528696000, 0.0731081000, 0.1148120000, 0.2013994000", \ - "0.0411903000, 0.0432720000, 0.0477687000, 0.0573521000, 0.0774508000, 0.1191316000, 0.2055738000", \ - "0.0513964000, 0.0533938000, 0.0577400000, 0.0671121000, 0.0869333000, 0.1284045000, 0.2147050000", \ - "0.0714036000, 0.0737604000, 0.0788228000, 0.0892603000, 0.1092139000, 0.1499659000, 0.2359972000", \ - "0.1019042000, 0.1051448000, 0.1118801000, 0.1250134000, 0.1504948000, 0.1985822000, 0.2851762000", \ - "0.1366220000, 0.1409708000, 0.1512051000, 0.1708694000, 0.2082740000, 0.2735560000, 0.3844888000", \ - "0.1530199000, 0.1599020000, 0.1749687000, 0.2046437000, 0.2624935000, 0.3622401000, 0.5281778000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2888679000, 0.2994934000, 0.3226280000, 0.3722378000, 0.4811532000, 0.7191275000, 1.2411357000", \ - "0.2920983000, 0.3026266000, 0.3254747000, 0.3759282000, 0.4851680000, 0.7238481000, 1.2461744000", \ - "0.3018583000, 0.3128497000, 0.3359630000, 0.3863009000, 0.4962684000, 0.7356629000, 1.2588798000", \ - "0.3279921000, 0.3382986000, 0.3617275000, 0.4116692000, 0.5216736000, 0.7615591000, 1.2855881000", \ - "0.3836572000, 0.3940663000, 0.4164540000, 0.4667676000, 0.5759443000, 0.8157678000, 1.3412015000", \ - "0.4907247000, 0.5017589000, 0.5250605000, 0.5771474000, 0.6862786000, 0.9251896000, 1.4489501000", \ - "0.6681397000, 0.6812301000, 0.7098006000, 0.7690528000, 0.8939969000, 1.1495553000, 1.6758929000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0384679000, 0.0411477000, 0.0467339000, 0.0586853000, 0.0836809000, 0.1354930000, 0.2458307000", \ - "0.0380644000, 0.0406509000, 0.0462415000, 0.0581671000, 0.0831768000, 0.1352707000, 0.2453607000", \ - "0.0388078000, 0.0412249000, 0.0463356000, 0.0578177000, 0.0823017000, 0.1348595000, 0.2450043000", \ - "0.0484306000, 0.0505279000, 0.0548665000, 0.0640253000, 0.0856476000, 0.1344458000, 0.2442735000", \ - "0.0713442000, 0.0735733000, 0.0779887000, 0.0886417000, 0.1094840000, 0.1502531000, 0.2507586000", \ - "0.1127737000, 0.1158172000, 0.1225570000, 0.1358497000, 0.1598041000, 0.2057569000, 0.2975022000", \ - "0.1877686000, 0.1924881000, 0.2015617000, 0.2196628000, 0.2556917000, 0.3177256000, 0.4262417000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2016875000, 0.2163719000, 0.2459095000, 0.3123615000, 0.4588184000, 0.7782268000, 1.4788676000", \ - "0.2015180000, 0.2155338000, 0.2457120000, 0.3135480000, 0.4589522000, 0.7783522000, 1.4782158000", \ - "0.2025873000, 0.2165508000, 0.2459924000, 0.3135528000, 0.4588541000, 0.7783627000, 1.4777066000", \ - "0.2018477000, 0.2165178000, 0.2461801000, 0.3128337000, 0.4587956000, 0.7782713000, 1.4782336000", \ - "0.2028823000, 0.2160810000, 0.2471398000, 0.3127007000, 0.4588647000, 0.7816277000, 1.4810437000", \ - "0.2178433000, 0.2302410000, 0.2590212000, 0.3228071000, 0.4649393000, 0.7789638000, 1.4824409000", \ - "0.2637683000, 0.2778038000, 0.3089096000, 0.3742084000, 0.5166617000, 0.8158466000, 1.4944199000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0224121000, 0.0237692000, 0.0267615000, 0.0329788000, 0.0459623000, 0.0726847000, 0.1286355000", \ - "0.0276668000, 0.0289543000, 0.0317133000, 0.0378455000, 0.0506428000, 0.0773092000, 0.1332042000", \ - "0.0399112000, 0.0412773000, 0.0441192000, 0.0496815000, 0.0619563000, 0.0881245000, 0.1438768000", \ - "0.0578924000, 0.0599076000, 0.0640825000, 0.0723053000, 0.0875503000, 0.1136392000, 0.1688298000", \ - "0.0788108000, 0.0819420000, 0.0882182000, 0.1006072000, 0.1233112000, 0.1633279000, 0.2281388000", \ - "0.0929970000, 0.0975229000, 0.1067762000, 0.1267791000, 0.1625626000, 0.2236741000, 0.3245509000", \ - "0.0748601000, 0.0818698000, 0.0965731000, 0.1263112000, 0.1812423000, 0.2770632000, 0.4340930000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2708506000, 0.2819598000, 0.3053991000, 0.3557976000, 0.4656467000, 0.7044060000, 1.2271556000", \ - "0.2719485000, 0.2828939000, 0.3062678000, 0.3568889000, 0.4675806000, 0.7074721000, 1.2310835000", \ - "0.2795461000, 0.2896348000, 0.3132951000, 0.3643809000, 0.4752130000, 0.7159980000, 1.2417635000", \ - "0.3029407000, 0.3139045000, 0.3368969000, 0.3877207000, 0.4976641000, 0.7385380000, 1.2645014000", \ - "0.3572150000, 0.3679566000, 0.3909265000, 0.4411088000, 0.5508580000, 0.7904158000, 1.3156930000", \ - "0.4637789000, 0.4754969000, 0.5015746000, 0.5559910000, 0.6661966000, 0.9048920000, 1.4289661000", \ - "0.6456110000, 0.6605892000, 0.6922555000, 0.7584142000, 0.8942305000, 1.1594899000, 1.6889743000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0294299000, 0.0309195000, 0.0341499000, 0.0412249000, 0.0562950000, 0.0888390000, 0.1604209000", \ - "0.0289495000, 0.0303418000, 0.0334370000, 0.0405587000, 0.0558874000, 0.0885778000, 0.1602626000", \ - "0.0328289000, 0.0338970000, 0.0363619000, 0.0421677000, 0.0557981000, 0.0879700000, 0.1600942000", \ - "0.0486344000, 0.0496700000, 0.0519136000, 0.0565523000, 0.0666419000, 0.0930710000, 0.1592136000", \ - "0.0768945000, 0.0783587000, 0.0815962000, 0.0884138000, 0.1022968000, 0.1278922000, 0.1803573000", \ - "0.1260292000, 0.1284493000, 0.1337277000, 0.1442372000, 0.1646561000, 0.2027045000, 0.2670474000", \ - "0.2132680000, 0.2171214000, 0.2248890000, 0.2430231000, 0.2745390000, 0.3339098000, 0.4302299000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2020838000, 0.2162642000, 0.2459011000, 0.3123988000, 0.4589310000, 0.7782885000, 1.4773877000", \ - "0.2024336000, 0.2164055000, 0.2457796000, 0.3130270000, 0.4587539000, 0.7782420000, 1.4768180000", \ - "0.2016252000, 0.2162641000, 0.2456539000, 0.3127843000, 0.4589556000, 0.7783282000, 1.4808536000", \ - "0.2025751000, 0.2153755000, 0.2460344000, 0.3139470000, 0.4589349000, 0.7775952000, 1.4770626000", \ - "0.2038699000, 0.2174568000, 0.2470385000, 0.3142522000, 0.4593644000, 0.7776265000, 1.4772432000", \ - "0.2322445000, 0.2444195000, 0.2713790000, 0.3333016000, 0.4710818000, 0.7797845000, 1.4818538000", \ - "0.3072013000, 0.3211442000, 0.3499868000, 0.4144534000, 0.5524187000, 0.8349942000, 1.4967773000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0217920000, 0.0229182000, 0.0254269000, 0.0305829000, 0.0416088000, 0.0648559000, 0.1151015000", \ - "0.0267091000, 0.0278126000, 0.0302361000, 0.0354543000, 0.0463411000, 0.0695611000, 0.1197761000", \ - "0.0377846000, 0.0390447000, 0.0416736000, 0.0468426000, 0.0574230000, 0.0806925000, 0.1309641000", \ - "0.0528363000, 0.0548158000, 0.0590167000, 0.0669329000, 0.0816143000, 0.1069357000, 0.1565318000", \ - "0.0689365000, 0.0719474000, 0.0782650000, 0.0907866000, 0.1132899000, 0.1529316000, 0.2160281000", \ - "0.0752914000, 0.0801506000, 0.0902410000, 0.1102024000, 0.1467974000, 0.2086100000, 0.3078530000", \ - "0.0454969000, 0.0531226000, 0.0691992000, 0.0997662000, 0.1581631000, 0.2554361000, 0.4124927000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2192598000, 0.2297001000, 0.2531671000, 0.3037287000, 0.4133174000, 0.6520740000, 1.1753876000", \ - "0.2202887000, 0.2309512000, 0.2545097000, 0.3051898000, 0.4154865000, 0.6549826000, 1.1786305000", \ - "0.2280416000, 0.2386942000, 0.2616428000, 0.3126243000, 0.4230038000, 0.6633457000, 1.1879114000", \ - "0.2504766000, 0.2614812000, 0.2841433000, 0.3346453000, 0.4447833000, 0.6851580000, 1.2111330000", \ - "0.3059246000, 0.3161986000, 0.3394717000, 0.3893334000, 0.4989175000, 0.7384623000, 1.2633107000", \ - "0.4199660000, 0.4325052000, 0.4588193000, 0.5165398000, 0.6290340000, 0.8684262000, 1.3924122000", \ - "0.6227481000, 0.6401996000, 0.6765706000, 0.7501373000, 0.8951750000, 1.1665752000, 1.6983494000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0230632000, 0.0243234000, 0.0270941000, 0.0331957000, 0.0466236000, 0.0762981000, 0.1420715000", \ - "0.0227038000, 0.0239285000, 0.0266613000, 0.0329133000, 0.0465000000, 0.0762095000, 0.1421198000", \ - "0.0268640000, 0.0277971000, 0.0299600000, 0.0351173000, 0.0472635000, 0.0761594000, 0.1426932000", \ - "0.0415973000, 0.0427107000, 0.0450457000, 0.0498085000, 0.0595477000, 0.0829704000, 0.1430547000", \ - "0.0678174000, 0.0693597000, 0.0727716000, 0.0799862000, 0.0943405000, 0.1192210000, 0.1679913000", \ - "0.1154138000, 0.1178820000, 0.1233069000, 0.1341353000, 0.1545790000, 0.1918407000, 0.2539289000", \ - "0.2025593000, 0.2062041000, 0.2149985000, 0.2312938000, 0.2629054000, 0.3207042000, 0.4125615000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.2011794000, 0.2151034000, 0.2463157000, 0.3128005000, 0.4595969000, 0.7800859000, 1.4821105000", \ - "0.2011551000, 0.2152063000, 0.2467696000, 0.3124034000, 0.4588717000, 0.7787938000, 1.4814409000", \ - "0.2020875000, 0.2152996000, 0.2457024000, 0.3134951000, 0.4588501000, 0.7782323000, 1.4766834000", \ - "0.2009827000, 0.2158430000, 0.2454636000, 0.3123767000, 0.4588321000, 0.7789096000, 1.4826428000", \ - "0.2054772000, 0.2185634000, 0.2479121000, 0.3128882000, 0.4588469000, 0.7783625000, 1.4782658000", \ - "0.2467711000, 0.2583824000, 0.2838421000, 0.3432470000, 0.4751503000, 0.7837033000, 1.4782717000", \ - "0.3418233000, 0.3553018000, 0.3848156000, 0.4501181000, 0.5818955000, 0.8503722000, 1.4965060000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0176132000, 0.0186203000, 0.0208418000, 0.0255856000, 0.0359425000, 0.0584418000, 0.1078556000", \ - "0.0222891000, 0.0233391000, 0.0255956000, 0.0302904000, 0.0406962000, 0.0632806000, 0.1127077000", \ - "0.0308446000, 0.0323637000, 0.0354230000, 0.0413269000, 0.0517243000, 0.0743808000, 0.1237945000", \ - "0.0407258000, 0.0431982000, 0.0478650000, 0.0571075000, 0.0734416000, 0.1003347000, 0.1497297000", \ - "0.0478417000, 0.0516574000, 0.0594004000, 0.0744926000, 0.1001873000, 0.1416031000, 0.2075044000", \ - "0.0403038000, 0.0456225000, 0.0580326000, 0.0817936000, 0.1232696000, 0.1902764000, 0.2918155000", \ - "-0.015980800, -0.008110600, 0.0118588000, 0.0499229000, 0.1163005000, 0.2235736000, 0.3874193000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.1492021000, 0.1600812000, 0.1834246000, 0.2339222000, 0.3434454000, 0.5821842000, 1.1045710000", \ - "0.1500241000, 0.1610163000, 0.1844381000, 0.2346222000, 0.3452764000, 0.5849886000, 1.1085322000", \ - "0.1572755000, 0.1674881000, 0.1904149000, 0.2411282000, 0.3517852000, 0.5923862000, 1.1191552000", \ - "0.1814654000, 0.1908266000, 0.2137535000, 0.2637620000, 0.3735086000, 0.6143558000, 1.1400428000", \ - "0.2468775000, 0.2559878000, 0.2769138000, 0.3252210000, 0.4316224000, 0.6708102000, 1.1955226000", \ - "0.3812815000, 0.3940933000, 0.4201236000, 0.4736934000, 0.5792038000, 0.8103971000, 1.3310857000", \ - "0.6036994000, 0.6193672000, 0.6576535000, 0.7355487000, 0.8827240000, 1.1477693000, 1.6635733000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.0167359000, 0.0181242000, 0.0211550000, 0.0276134000, 0.0414667000, 0.0715855000, 0.1379117000", \ - "0.0173770000, 0.0186374000, 0.0214473000, 0.0276443000, 0.0414734000, 0.0716297000, 0.1386975000", \ - "0.0241726000, 0.0249621000, 0.0268728000, 0.0316595000, 0.0433891000, 0.0716656000, 0.1378274000", \ - "0.0392409000, 0.0403847000, 0.0428346000, 0.0480145000, 0.0581510000, 0.0803751000, 0.1392441000", \ - "0.0660507000, 0.0676268000, 0.0711020000, 0.0780862000, 0.0923758000, 0.1184304000, 0.1658911000", \ - "0.1155484000, 0.1177855000, 0.1228773000, 0.1330158000, 0.1532877000, 0.1905816000, 0.2546958000", \ - "0.2074490000, 0.2106524000, 0.2181873000, 0.2335972000, 0.2645309000, 0.3183894000, 0.4093022000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011002700, 0.0024211800, 0.0053278800, 0.0117242000, 0.0257995000, 0.0567727000"); - values("0.1966686000, 0.2118351000, 0.2427950000, 0.3110905000, 0.4585812000, 0.7783691000, 1.4781166000", \ - "0.1963050000, 0.2102487000, 0.2421081000, 0.3116948000, 0.4595946000, 0.7780273000, 1.4805724000", \ - "0.1935207000, 0.2086280000, 0.2406423000, 0.3110527000, 0.4582973000, 0.7783568000, 1.4796419000", \ - "0.1884513000, 0.2036022000, 0.2376316000, 0.3073881000, 0.4588780000, 0.7797148000, 1.4798645000", \ - "0.1953051000, 0.2085805000, 0.2381390000, 0.3035285000, 0.4524683000, 0.7779676000, 1.4828135000", \ - "0.2450555000, 0.2593056000, 0.2881187000, 0.3446885000, 0.4739343000, 0.7779070000, 1.4769245000", \ - "0.3369408000, 0.3532897000, 0.3889823000, 0.4623259000, 0.6042550000, 0.8701577000, 1.4971110000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2111oi_4") { - leakage_power () { - value : 0.0040425000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0065744000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0002915000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0026514000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002728000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0023693000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001528000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002870000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0040425000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0083402000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0002915000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0026514000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002729000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0023693000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001528000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002870000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0040425000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0079083000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0002915000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0026514000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0002732000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0023693000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001528000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0002870000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0003745000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0033081000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001722000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0003826000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0003510000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0003984000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001269000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0001883000; - when : "A1&A2&B1&C1&!D1"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__a2111oi"; - cell_leakage_power : 0.0018227260; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0084230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181535000, 0.0181564000, 0.0181631000, 0.0181659000, 0.0181724000, 0.0181874000, 0.0182220000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012960300, -0.012981500, -0.013030400, -0.012991600, -0.012902200, -0.012696100, -0.012221000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087470000; - } - pin ("A2") { - capacitance : 0.0087170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0160182000, 0.0160123000, 0.0159988000, 0.0160009000, 0.0160057000, 0.0160169000, 0.0160426000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015953900, -0.015947400, -0.015932600, -0.015932900, -0.015933400, -0.015934800, -0.015937800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091580000; - } - pin ("B1") { - capacitance : 0.0084530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0230492000, 0.0230424000, 0.0230267000, 0.0230259000, 0.0230242000, 0.0230203000, 0.0230112000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013304300, -0.013419500, -0.013685000, -0.013751400, -0.013904400, -0.014257100, -0.015070100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090270000; - } - pin ("C1") { - capacitance : 0.0083860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0168871000, 0.0168843000, 0.0168780000, 0.0168853000, 0.0169020000, 0.0169407000, 0.0170297000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014006800, -0.014278900, -0.014906100, -0.014936600, -0.015006900, -0.015169100, -0.015542900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090500000; - } - pin ("D1") { - capacitance : 0.0084560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0070130000, 0.0070113000, 0.0070073000, 0.0070235000, 0.0070607000, 0.0071464000, 0.0073440000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006827100, -0.006833300, -0.006847400, -0.006844500, -0.006837800, -0.006822400, -0.006786900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092270000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1&!D1) | (!A2&!B1&!C1&!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0154412000, 0.0142968000, 0.0114620000, 0.0045753000, -0.012214800, -0.053262200, -0.153626400", \ - "0.0156108000, 0.0144557000, 0.0116597000, 0.0048107000, -0.011933100, -0.052933500, -0.153281000", \ - "0.0159635000, 0.0148388000, 0.0120726000, 0.0052760000, -0.011343700, -0.052240000, -0.152489400", \ - "0.0153489000, 0.0142404000, 0.0115016000, 0.0048894000, -0.011578100, -0.052281200, -0.152381200", \ - "0.0157784000, 0.0144773000, 0.0116643000, 0.0048014000, -0.011945800, -0.052381000, -0.152246700", \ - "0.0164497000, 0.0152845000, 0.0124526000, 0.0055693000, -0.011202500, -0.051692100, -0.152190100", \ - "0.0205497000, 0.0193247000, 0.0163903000, 0.0092023000, -0.007958400, -0.048913700, -0.150010600"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0484968000, 0.0496914000, 0.0525959000, 0.0596357000, 0.0766356000, 0.1175880000, 0.2169141000", \ - "0.0478011000, 0.0490473000, 0.0519275000, 0.0590651000, 0.0761616000, 0.1172805000, 0.2168211000", \ - "0.0470342000, 0.0482874000, 0.0511632000, 0.0582242000, 0.0753521000, 0.1167293000, 0.2165900000", \ - "0.0463877000, 0.0476024000, 0.0504947000, 0.0575168000, 0.0744937000, 0.1160013000, 0.2159778000", \ - "0.0458935000, 0.0470801000, 0.0499501000, 0.0568360000, 0.0738097000, 0.1150032000, 0.2148958000", \ - "0.0457446000, 0.0469101000, 0.0497468000, 0.0567781000, 0.0737387000, 0.1146090000, 0.2141973000", \ - "0.0466716000, 0.0478551000, 0.0506132000, 0.0574564000, 0.0741223000, 0.1148746000, 0.2147139000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0015452000, 0.0004271000, -0.002322300, -0.009175100, -0.026136200, -0.067514200, -0.168168100", \ - "0.0011328000, 4.400000e-05, -0.002652400, -0.009370000, -0.026121800, -0.067280800, -0.167789400", \ - "0.0004780000, -0.000602300, -0.003261400, -0.009832100, -0.026250400, -0.067116900, -0.167454100", \ - "-0.000247100, -0.001371600, -0.003942500, -0.010485900, -0.026778600, -0.067221700, -0.167206000", \ - "3.720000e-05, -0.001039900, -0.003729300, -0.010306400, -0.026946400, -0.067382700, -0.167191700", \ - "0.0008333000, -0.000335900, -0.003156200, -0.009790900, -0.026536200, -0.067238000, -0.167188200", \ - "0.0051264000, 0.0038580000, 0.0007854000, -0.006590700, -0.023712200, -0.065107300, -0.165455100"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0486991000, 0.0499202000, 0.0528926000, 0.0601570000, 0.0773388000, 0.1184517000, 0.2181123000", \ - "0.0478388000, 0.0490782000, 0.0520754000, 0.0593483000, 0.0765048000, 0.1179640000, 0.2178546000", \ - "0.0471685000, 0.0483604000, 0.0513619000, 0.0583555000, 0.0756045000, 0.1171491000, 0.2175230000", \ - "0.0466519000, 0.0478513000, 0.0505773000, 0.0576021000, 0.0747497000, 0.1163281000, 0.2165555000", \ - "0.0465485000, 0.0476917000, 0.0505014000, 0.0574066000, 0.0742342000, 0.1153859000, 0.2155768000", \ - "0.0489098000, 0.0500399000, 0.0527647000, 0.0596385000, 0.0751609000, 0.1158525000, 0.2150199000", \ - "0.0525890000, 0.0536673000, 0.0563581000, 0.0629656000, 0.0791350000, 0.1186919000, 0.2170144000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0289515000, 0.0277852000, 0.0249500000, 0.0180320000, 0.0012009000, -0.039767000, -0.139385700", \ - "0.0285124000, 0.0273514000, 0.0245357000, 0.0176653000, 0.0008155000, -0.040185300, -0.139800800", \ - "0.0279871000, 0.0268194000, 0.0240089000, 0.0170815000, 0.0002887000, -0.040656100, -0.140330800", \ - "0.0272963000, 0.0261262000, 0.0234167000, 0.0165357000, -0.000334000, -0.041277100, -0.140924100", \ - "0.0266524000, 0.0255056000, 0.0227632000, 0.0160802000, -0.000779200, -0.041662900, -0.141221100", \ - "0.0259030000, 0.0247516000, 0.0219209000, 0.0149855000, -0.001405000, -0.042280500, -0.141511300", \ - "0.0298226000, 0.0286787000, 0.0258159000, 0.0189346000, 0.0023602000, -0.039554900, -0.140887900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0541483000, 0.0553531000, 0.0582765000, 0.0652318000, 0.0821347000, 0.1230572000, 0.2225209000", \ - "0.0533846000, 0.0546481000, 0.0575590000, 0.0648152000, 0.0817813000, 0.1228017000, 0.2235682000", \ - "0.0523511000, 0.0535825000, 0.0565565000, 0.0637449000, 0.0810308000, 0.1224125000, 0.2222211000", \ - "0.0516390000, 0.0528933000, 0.0558649000, 0.0629471000, 0.0800360000, 0.1216244000, 0.2217404000", \ - "0.0510761000, 0.0522727000, 0.0552109000, 0.0621918000, 0.0791393000, 0.1205729000, 0.2212182000", \ - "0.0509793000, 0.0521479000, 0.0549833000, 0.0619257000, 0.0787943000, 0.1203100000, 0.2199191000", \ - "0.0507873000, 0.0519839000, 0.0548267000, 0.0619069000, 0.0789040000, 0.1193148000, 0.2197019000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0315479000, 0.0303827000, 0.0275664000, 0.0206151000, 0.0037727000, -0.037177900, -0.136825400", \ - "0.0310447000, 0.0298852000, 0.0270705000, 0.0201761000, 0.0033141000, -0.037660700, -0.137256900", \ - "0.0304988000, 0.0293362000, 0.0265010000, 0.0195944000, 0.0027592000, -0.038243600, -0.137869100", \ - "0.0299641000, 0.0288264000, 0.0260037000, 0.0191485000, 0.0022765000, -0.038758900, -0.138429900", \ - "0.0295944000, 0.0284363000, 0.0256246000, 0.0188127000, 0.0021027000, -0.038885900, -0.138508100", \ - "0.0290952000, 0.0278977000, 0.0251905000, 0.0183363000, 0.0014346000, -0.039280700, -0.138986200", \ - "0.0321254000, 0.0309306000, 0.0280252000, 0.0211643000, 0.0039671000, -0.037644700, -0.138626300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0688265000, 0.0699564000, 0.0728051000, 0.0797369000, 0.0965005000, 0.1373680000, 0.2367023000", \ - "0.0682578000, 0.0694514000, 0.0723245000, 0.0792632000, 0.0960643000, 0.1369882000, 0.2363721000", \ - "0.0676682000, 0.0687894000, 0.0717129000, 0.0787108000, 0.0955975000, 0.1366311000, 0.2360693000", \ - "0.0670096000, 0.0682062000, 0.0711050000, 0.0781153000, 0.0950286000, 0.1361706000, 0.2358075000", \ - "0.0664946000, 0.0676989000, 0.0705179000, 0.0775102000, 0.0944155000, 0.1355356000, 0.2353233000", \ - "0.0662482000, 0.0674313000, 0.0702900000, 0.0772253000, 0.0940702000, 0.1350269000, 0.2347841000", \ - "0.0661768000, 0.0673355000, 0.0702512000, 0.0772227000, 0.0940449000, 0.1349469000, 0.2346230000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0204779000, 0.0192959000, 0.0164681000, 0.0095953000, -0.007221300, -0.048055700, -0.148067600", \ - "0.0204909000, 0.0193328000, 0.0164881000, 0.0095890000, -0.007169800, -0.048023200, -0.148019400", \ - "0.0204836000, 0.0193243000, 0.0165165000, 0.0096892000, -0.007101200, -0.047928100, -0.147890000", \ - "0.0198848000, 0.0187425000, 0.0159410000, 0.0091291000, -0.007504600, -0.048182600, -0.148114300", \ - "0.0194189000, 0.0182738000, 0.0154896000, 0.0087082000, -0.007607800, -0.048240700, -0.148060500", \ - "0.0209419000, 0.0198013000, 0.0169821000, 0.0100759000, -0.006809300, -0.047973500, -0.148038700", \ - "0.0254725000, 0.0242618000, 0.0213377000, 0.0142095000, -0.002861800, -0.044357600, -0.145506800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012195790, 0.0029747470, 0.0072558810, 0.0176982400, 0.0431688200, 0.1052956000"); - values("0.0519259000, 0.0531336000, 0.0559949000, 0.0630608000, 0.0799414000, 0.1208429000, 0.2203961000", \ - "0.0512559000, 0.0524645000, 0.0554056000, 0.0624154000, 0.0794814000, 0.1205470000, 0.2200400000", \ - "0.0504344000, 0.0516079000, 0.0545148000, 0.0616494000, 0.0787614000, 0.1200581000, 0.2197832000", \ - "0.0497831000, 0.0509902000, 0.0538733000, 0.0608974000, 0.0779379000, 0.1192651000, 0.2192973000", \ - "0.0492809000, 0.0504344000, 0.0532595000, 0.0602150000, 0.0771750000, 0.1183517000, 0.2182724000", \ - "0.0490579000, 0.0501926000, 0.0530133000, 0.0599999000, 0.0767595000, 0.1178181000, 0.2176222000", \ - "0.0492126000, 0.0503577000, 0.0532131000, 0.0601983000, 0.0770146000, 0.1180387000, 0.2176914000"); - } - } - max_capacitance : 0.1052960000; - max_transition : 1.5000270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0345311000, 0.0362170000, 0.0401163000, 0.0492228000, 0.0699652000, 0.1162848000, 0.2204881000", \ - "0.0391834000, 0.0408276000, 0.0446358000, 0.0536352000, 0.0741424000, 0.1202989000, 0.2244269000", \ - "0.0508691000, 0.0523195000, 0.0558915000, 0.0644440000, 0.0844361000, 0.1300924000, 0.2343200000", \ - "0.0750916000, 0.0769049000, 0.0814274000, 0.0911035000, 0.1098633000, 0.1541844000, 0.2569184000", \ - "0.1069953000, 0.1095456000, 0.1155179000, 0.1287897000, 0.1562429000, 0.2092952000, 0.3121709000", \ - "0.1412854000, 0.1449778000, 0.1536307000, 0.1732886000, 0.2126793000, 0.2908991000, 0.4304660000", \ - "0.1510325000, 0.1565964000, 0.1693347000, 0.1979827000, 0.2581545000, 0.3761315000, 0.5872233000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.2353509000, 0.2421938000, 0.2593210000, 0.2997171000, 0.3959593000, 0.6277714000, 1.1920388000", \ - "0.2374875000, 0.2448798000, 0.2617631000, 0.3030369000, 0.4001110000, 0.6331309000, 1.2056589000", \ - "0.2469594000, 0.2538633000, 0.2706934000, 0.3126838000, 0.4109569000, 0.6453312000, 1.2115007000", \ - "0.2739980000, 0.2809072000, 0.2976949000, 0.3388343000, 0.4371444000, 0.6715829000, 1.2395489000", \ - "0.3329486000, 0.3396131000, 0.3564089000, 0.3962631000, 0.4929899000, 0.7288193000, 1.2980973000", \ - "0.4419191000, 0.4504237000, 0.4679979000, 0.5120699000, 0.6105537000, 0.8458660000, 1.4118720000", \ - "0.6256540000, 0.6349273000, 0.6568119000, 0.7089941000, 0.8250341000, 1.0835384000, 1.6564784000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0479751000, 0.0499923000, 0.0548804000, 0.0664691000, 0.0934509000, 0.1554311000, 0.3004395000", \ - "0.0466602000, 0.0487171000, 0.0537314000, 0.0655752000, 0.0927113000, 0.1549011000, 0.3002123000", \ - "0.0467610000, 0.0485734000, 0.0530461000, 0.0641601000, 0.0910385000, 0.1537764000, 0.2996791000", \ - "0.0583282000, 0.0599124000, 0.0640868000, 0.0728720000, 0.0954204000, 0.1530548000, 0.2989613000", \ - "0.0821621000, 0.0842941000, 0.0893949000, 0.1013961000, 0.1244672000, 0.1749544000, 0.3038638000", \ - "0.1286859000, 0.1315295000, 0.1380450000, 0.1526260000, 0.1838950000, 0.2450402000, 0.3696662000", \ - "0.2102025000, 0.2144825000, 0.2245761000, 0.2465321000, 0.2917096000, 0.3766607000, 0.5332474000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1508708000, 0.1597921000, 0.1808156000, 0.2332620000, 0.3611033000, 0.6716003000, 1.4267170000", \ - "0.1506659000, 0.1595097000, 0.1815766000, 0.2337034000, 0.3611288000, 0.6712646000, 1.4398693000", \ - "0.1512074000, 0.1602650000, 0.1815984000, 0.2334239000, 0.3610691000, 0.6716039000, 1.4266620000", \ - "0.1515202000, 0.1600124000, 0.1813181000, 0.2342364000, 0.3613007000, 0.6717157000, 1.4268736000", \ - "0.1526616000, 0.1614800000, 0.1818437000, 0.2342612000, 0.3610091000, 0.6717903000, 1.4315611000", \ - "0.1716144000, 0.1799262000, 0.1997020000, 0.2479943000, 0.3694374000, 0.6741422000, 1.4273401000", \ - "0.2187338000, 0.2274530000, 0.2480916000, 0.3001059000, 0.4239132000, 0.7153298000, 1.4421089000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0405000000, 0.0420575000, 0.0458598000, 0.0548314000, 0.0753532000, 0.1217469000, 0.2262497000", \ - "0.0449303000, 0.0465725000, 0.0503719000, 0.0593207000, 0.0797776000, 0.1256937000, 0.2299401000", \ - "0.0542539000, 0.0557999000, 0.0594117000, 0.0680994000, 0.0883877000, 0.1342769000, 0.2385359000", \ - "0.0728919000, 0.0746480000, 0.0788332000, 0.0880391000, 0.1080755000, 0.1531723000, 0.2572513000", \ - "0.1019200000, 0.1040840000, 0.1092008000, 0.1209501000, 0.1455240000, 0.1957236000, 0.3008409000", \ - "0.1359729000, 0.1391698000, 0.1470820000, 0.1631693000, 0.1981414000, 0.2665399000, 0.3913713000", \ - "0.1519715000, 0.1567375000, 0.1679287000, 0.1924280000, 0.2458690000, 0.3476654000, 0.5282499000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.2878613000, 0.2947414000, 0.3112910000, 0.3508005000, 0.4477843000, 0.6812966000, 1.2480867000", \ - "0.2905748000, 0.2976880000, 0.3146083000, 0.3547770000, 0.4517767000, 0.6854425000, 1.2526180000", \ - "0.3011534000, 0.3079187000, 0.3254424000, 0.3659690000, 0.4634438000, 0.6977926000, 1.2654783000", \ - "0.3273903000, 0.3345845000, 0.3516507000, 0.3921476000, 0.4897137000, 0.7249425000, 1.2942378000", \ - "0.3834274000, 0.3908038000, 0.4071529000, 0.4478085000, 0.5450220000, 0.7798123000, 1.3494686000", \ - "0.4892964000, 0.4966734000, 0.5145891000, 0.5571964000, 0.6547243000, 0.8890880000, 1.4579685000", \ - "0.6661491000, 0.6744327000, 0.6950243000, 0.7445721000, 0.8564838000, 1.1096198000, 1.6831935000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0471845000, 0.0492456000, 0.0541498000, 0.0658212000, 0.0930451000, 0.1548477000, 0.3000765000", \ - "0.0465059000, 0.0485105000, 0.0534301000, 0.0651971000, 0.0922532000, 0.1544742000, 0.2999120000", \ - "0.0464123000, 0.0482705000, 0.0530192000, 0.0643399000, 0.0914166000, 0.1539336000, 0.2994428000", \ - "0.0534027000, 0.0551640000, 0.0591529000, 0.0690326000, 0.0935084000, 0.1535018000, 0.2990981000", \ - "0.0726287000, 0.0743250000, 0.0787967000, 0.0889706000, 0.1117746000, 0.1652872000, 0.3016546000", \ - "0.1116540000, 0.1137762000, 0.1194919000, 0.1312315000, 0.1572027000, 0.2148929000, 0.3385614000", \ - "0.1828975000, 0.1858125000, 0.1929121000, 0.2092859000, 0.2435306000, 0.3140454000, 0.4543378000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1972737000, 0.2066901000, 0.2275939000, 0.2811552000, 0.4089064000, 0.7213269000, 1.4796754000", \ - "0.1981734000, 0.2071144000, 0.2279522000, 0.2803881000, 0.4091268000, 0.7212038000, 1.4788198000", \ - "0.1976336000, 0.2069356000, 0.2289198000, 0.2803909000, 0.4091096000, 0.7211629000, 1.4793199000", \ - "0.1982738000, 0.2072247000, 0.2279003000, 0.2818620000, 0.4091894000, 0.7236458000, 1.4809260000", \ - "0.1986605000, 0.2073942000, 0.2291516000, 0.2805238000, 0.4104062000, 0.7212222000, 1.4843994000", \ - "0.2129944000, 0.2212571000, 0.2415320000, 0.2915272000, 0.4158711000, 0.7219157000, 1.4820536000", \ - "0.2574702000, 0.2667840000, 0.2891973000, 0.3402587000, 0.4665422000, 0.7595592000, 1.4964138000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0232670000, 0.0243025000, 0.0266350000, 0.0322352000, 0.0449255000, 0.0733494000, 0.1381523000", \ - "0.0283898000, 0.0293405000, 0.0316671000, 0.0371043000, 0.0496123000, 0.0779726000, 0.1427368000", \ - "0.0405032000, 0.0415034000, 0.0438087000, 0.0489537000, 0.0609012000, 0.0888826000, 0.1535724000", \ - "0.0589413000, 0.0603612000, 0.0636477000, 0.0706609000, 0.0856236000, 0.1143309000, 0.1784337000", \ - "0.0806831000, 0.0827108000, 0.0874930000, 0.0981776000, 0.1204393000, 0.1627615000, 0.2373349000", \ - "0.0955709000, 0.0986887000, 0.1060581000, 0.1230955000, 0.1575317000, 0.2225474000, 0.3363409000", \ - "0.0789200000, 0.0837265000, 0.0950041000, 0.1206165000, 0.1731621000, 0.2744872000, 0.4519131000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.2667752000, 0.2738141000, 0.2906936000, 0.3311000000, 0.4282533000, 0.6625288000, 1.2301800000", \ - "0.2682914000, 0.2753814000, 0.2924381000, 0.3332392000, 0.4312493000, 0.6659610000, 1.2338021000", \ - "0.2765708000, 0.2836507000, 0.3006388000, 0.3412621000, 0.4399291000, 0.6757598000, 1.2447140000", \ - "0.3003460000, 0.3075450000, 0.3245714000, 0.3646288000, 0.4631864000, 0.6993614000, 1.2694898000", \ - "0.3549939000, 0.3615327000, 0.3783913000, 0.4190482000, 0.5168930000, 0.7521273000, 1.3223395000", \ - "0.4627497000, 0.4705041000, 0.4891456000, 0.5332484000, 0.6327103000, 0.8673931000, 1.4367217000", \ - "0.6489581000, 0.6584707000, 0.6817360000, 0.7367960000, 0.8570201000, 1.1208520000, 1.6973067000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0329807000, 0.0340119000, 0.0365923000, 0.0429887000, 0.0582021000, 0.0948677000, 0.1833936000", \ - "0.0322481000, 0.0332538000, 0.0357524000, 0.0421622000, 0.0577219000, 0.0945554000, 0.1832448000", \ - "0.0353979000, 0.0362211000, 0.0382993000, 0.0437550000, 0.0576510000, 0.0939929000, 0.1830313000", \ - "0.0493811000, 0.0502387000, 0.0522775000, 0.0574417000, 0.0684667000, 0.0991059000, 0.1826755000", \ - "0.0763466000, 0.0775570000, 0.0805006000, 0.0868476000, 0.1016157000, 0.1319510000, 0.2017943000", \ - "0.1253554000, 0.1271295000, 0.1312685000, 0.1406856000, 0.1610254000, 0.2027025000, 0.2817965000", \ - "0.2124326000, 0.2151707000, 0.2217000000, 0.2357070000, 0.2675837000, 0.3285233000, 0.4412154000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1971377000, 0.2066019000, 0.2274341000, 0.2815671000, 0.4091720000, 0.7236763000, 1.4843411000", \ - "0.1975099000, 0.2060431000, 0.2284339000, 0.2804759000, 0.4089257000, 0.7211686000, 1.4794209000", \ - "0.1972916000, 0.2067462000, 0.2275980000, 0.2814789000, 0.4090635000, 0.7213468000, 1.4797065000", \ - "0.1983215000, 0.2072287000, 0.2278241000, 0.2810769000, 0.4089680000, 0.7213614000, 1.4799418000", \ - "0.1988496000, 0.2079437000, 0.2296270000, 0.2821194000, 0.4089692000, 0.7212198000, 1.4793403000", \ - "0.2260729000, 0.2344829000, 0.2533418000, 0.3018118000, 0.4227037000, 0.7234812000, 1.4816286000", \ - "0.2962616000, 0.3052713000, 0.3268635000, 0.3777011000, 0.4974418000, 0.7796483000, 1.5000274000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0220852000, 0.0229603000, 0.0249152000, 0.0295701000, 0.0401644000, 0.0646455000, 0.1227497000", \ - "0.0268757000, 0.0277287000, 0.0296794000, 0.0341841000, 0.0447651000, 0.0692749000, 0.1273291000", \ - "0.0376513000, 0.0385949000, 0.0407761000, 0.0452970000, 0.0556801000, 0.0801295000, 0.1382348000", \ - "0.0520796000, 0.0534712000, 0.0567037000, 0.0638392000, 0.0785802000, 0.1053140000, 0.1633206000", \ - "0.0658946000, 0.0685094000, 0.0733797000, 0.0844150000, 0.1069312000, 0.1485652000, 0.2213156000", \ - "0.0682692000, 0.0716558000, 0.0795310000, 0.0966298000, 0.1325048000, 0.1977530000, 0.3109825000", \ - "0.0273170000, 0.0325441000, 0.0447534000, 0.0720278000, 0.1289483000, 0.2317970000, 0.4095903000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.2219286000, 0.2290668000, 0.2460704000, 0.2867501000, 0.3843346000, 0.6185715000, 1.1875927000", \ - "0.2226666000, 0.2298478000, 0.2469787000, 0.2883983000, 0.3865844000, 0.6218995000, 1.1913367000", \ - "0.2300187000, 0.2374273000, 0.2546996000, 0.2956104000, 0.3941402000, 0.6302543000, 1.1997092000", \ - "0.2535664000, 0.2607474000, 0.2778995000, 0.3183240000, 0.4165167000, 0.6527250000, 1.2232957000", \ - "0.3096253000, 0.3165056000, 0.3335860000, 0.3736652000, 0.4713296000, 0.7066211000, 1.2767906000", \ - "0.4248784000, 0.4332623000, 0.4526021000, 0.4996460000, 0.6023835000, 0.8373432000, 1.4065799000", \ - "0.6288982000, 0.6403791000, 0.6673723000, 0.7282684000, 0.8605415000, 1.1333692000, 1.7141745000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0235072000, 0.0244522000, 0.0267772000, 0.0324765000, 0.0461254000, 0.0788893000, 0.1587961000", \ - "0.0230648000, 0.0239901000, 0.0263055000, 0.0321228000, 0.0459675000, 0.0788547000, 0.1587321000", \ - "0.0267489000, 0.0275068000, 0.0295301000, 0.0344719000, 0.0468945000, 0.0787328000, 0.1588029000", \ - "0.0409663000, 0.0418514000, 0.0439628000, 0.0488515000, 0.0595327000, 0.0859656000, 0.1597907000", \ - "0.0672613000, 0.0681978000, 0.0711002000, 0.0777111000, 0.0918629000, 0.1210741000, 0.1823092000", \ - "0.1139782000, 0.1156944000, 0.1199971000, 0.1301762000, 0.1506145000, 0.1915803000, 0.2661135000", \ - "0.2005359000, 0.2033587000, 0.2099698000, 0.2247250000, 0.2553599000, 0.3165200000, 0.4233003000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1973544000, 0.2066313000, 0.2274880000, 0.2802686000, 0.4090384000, 0.7213601000, 1.4808271000", \ - "0.1976940000, 0.2068784000, 0.2275930000, 0.2804606000, 0.4104909000, 0.7236591000, 1.4814060000", \ - "0.1977378000, 0.2068543000, 0.2282967000, 0.2801768000, 0.4091568000, 0.7211325000, 1.4818939000", \ - "0.1975237000, 0.2067706000, 0.2275449000, 0.2805006000, 0.4089464000, 0.7217061000, 1.4789646000", \ - "0.2014467000, 0.2097801000, 0.2302731000, 0.2822721000, 0.4091510000, 0.7214947000, 1.4791811000", \ - "0.2393933000, 0.2466926000, 0.2654157000, 0.3115244000, 0.4282701000, 0.7277478000, 1.4790151000", \ - "0.3310665000, 0.3402099000, 0.3616438000, 0.4143988000, 0.5365574000, 0.7995751000, 1.4965519000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0161569000, 0.0168754000, 0.0185615000, 0.0225092000, 0.0317548000, 0.0535000000, 0.1060772000", \ - "0.0208282000, 0.0215484000, 0.0232680000, 0.0271944000, 0.0364622000, 0.0583377000, 0.1109989000", \ - "0.0287182000, 0.0298258000, 0.0323080000, 0.0376217000, 0.0475032000, 0.0694245000, 0.1220420000", \ - "0.0374615000, 0.0391427000, 0.0429541000, 0.0511946000, 0.0670931000, 0.0950021000, 0.1474669000", \ - "0.0425844000, 0.0452832000, 0.0514007000, 0.0643833000, 0.0901437000, 0.1331765000, 0.2054551000", \ - "0.0311951000, 0.0354964000, 0.0455826000, 0.0658835000, 0.1062681000, 0.1761996000, 0.2884404000", \ - "-0.031164200, -0.024276700, -0.008511000, 0.0246778000, 0.0891399000, 0.2004354000, 0.3805528000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1418014000, 0.1488970000, 0.1666060000, 0.2081663000, 0.3070887000, 0.5426214000, 1.1112122000", \ - "0.1422476000, 0.1495284000, 0.1664453000, 0.2089141000, 0.3080244000, 0.5446540000, 1.1139785000", \ - "0.1499350000, 0.1567758000, 0.1742202000, 0.2148991000, 0.3141047000, 0.5513657000, 1.1222427000", \ - "0.1739214000, 0.1806494000, 0.1965225000, 0.2370693000, 0.3352521000, 0.5719791000, 1.1437113000", \ - "0.2394765000, 0.2452138000, 0.2599680000, 0.2974057000, 0.3936158000, 0.6287223000, 1.1991291000", \ - "0.3730779000, 0.3813429000, 0.4003889000, 0.4440176000, 0.5407672000, 0.7692256000, 1.3351927000", \ - "0.5882214000, 0.6000276000, 0.6282198000, 0.6927974000, 0.8300472000, 1.1012853000, 1.6584791000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.0124167000, 0.0133210000, 0.0156505000, 0.0212962000, 0.0346389000, 0.0648213000, 0.1362390000", \ - "0.0130989000, 0.0139303000, 0.0160849000, 0.0213875000, 0.0346828000, 0.0648147000, 0.1363119000", \ - "0.0202272000, 0.0209297000, 0.0226240000, 0.0262580000, 0.0372059000, 0.0651689000, 0.1362677000", \ - "0.0355992000, 0.0364339000, 0.0382776000, 0.0427766000, 0.0529490000, 0.0748193000, 0.1380495000", \ - "0.0630573000, 0.0640997000, 0.0666878000, 0.0726953000, 0.0855752000, 0.1125876000, 0.1644155000", \ - "0.1125305000, 0.1139477000, 0.1170297000, 0.1258133000, 0.1442521000, 0.1814121000, 0.2527015000", \ - "0.2038305000, 0.2059747000, 0.2109711000, 0.2237230000, 0.2505027000, 0.3069522000, 0.4068186000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012195800, 0.0029747500, 0.0072558800, 0.0176982000, 0.0431688000, 0.1052960000"); - values("0.1919651000, 0.2016277000, 0.2244716000, 0.2791912000, 0.4096578000, 0.7233397000, 1.4844077000", \ - "0.1910709000, 0.2002506000, 0.2231019000, 0.2776904000, 0.4090987000, 0.7207641000, 1.4816465000", \ - "0.1888859000, 0.1987328000, 0.2215779000, 0.2768189000, 0.4086638000, 0.7211313000, 1.4800223000", \ - "0.1833146000, 0.1924057000, 0.2161689000, 0.2741539000, 0.4066425000, 0.7217537000, 1.4788292000", \ - "0.1906062000, 0.1993470000, 0.2192240000, 0.2719825000, 0.4005863000, 0.7208312000, 1.4794048000", \ - "0.2387513000, 0.2487646000, 0.2724144000, 0.3177764000, 0.4288639000, 0.7217739000, 1.4794257000", \ - "0.3233296000, 0.3346813000, 0.3616530000, 0.4236127000, 0.5560842000, 0.8235763000, 1.4995479000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211o_1") { - leakage_power () { - value : 0.0028539000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0108164000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0004218000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0010345000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0028539000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0112867000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0004218000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0010345000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0028539000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0111734000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0004218000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0010345000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0005826000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0024635000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0004021000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0005410000; - when : "A1&A2&B1&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a211o"; - cell_leakage_power : 0.0031372750; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046832000, 0.0046837000, 0.0046848000, 0.0046855000, 0.0046871000, 0.0046909000, 0.0046996000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003744000, -0.003746400, -0.003751900, -0.003744900, -0.003728600, -0.003691200, -0.003605000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025290000; - } - pin ("A2") { - capacitance : 0.0024320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043384000, 0.0043414000, 0.0043483000, 0.0043494000, 0.0043518000, 0.0043574000, 0.0043703000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004357700, -0.004354000, -0.004345700, -0.004346200, -0.004347300, -0.004349800, -0.004355500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025740000; - } - pin ("B1") { - capacitance : 0.0023730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038257000, 0.0038240000, 0.0038202000, 0.0038192000, 0.0038167000, 0.0038110000, 0.0037980000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003408200, -0.003484500, -0.003660200, -0.003665900, -0.003679100, -0.003709400, -0.003779200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025390000; - } - pin ("C1") { - capacitance : 0.0023300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026352000, 0.0026316000, 0.0026233000, 0.0026312000, 0.0026493000, 0.0026911000, 0.0027875000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001728700, -0.001724900, -0.001716200, -0.001715800, -0.001715000, -0.001713000, -0.001708600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025180000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0128169000, 0.0119644000, 0.0095206000, 0.0017364000, -0.022165100, -0.088929400, -0.267549300", \ - "0.0126353000, 0.0117644000, 0.0092975000, 0.0015204000, -0.022403100, -0.089179800, -0.267734900", \ - "0.0123370000, 0.0114638000, 0.0090011000, 0.0012102000, -0.022696600, -0.089484900, -0.268028500", \ - "0.0121375000, 0.0112608000, 0.0087959000, 0.0009787000, -0.022926600, -0.089723900, -0.268264200", \ - "0.0119102000, 0.0110772000, 0.0085884000, 0.0007751000, -0.023149900, -0.089952700, -0.268446800", \ - "0.0118930000, 0.0105194000, 0.0081653000, 0.0006476000, -0.023239700, -0.089966600, -0.268476800", \ - "0.0160647000, 0.0146482000, 0.0110419000, 0.0016226000, -0.023410700, -0.089913500, -0.268394500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0143313000, 0.0158376000, 0.0196480000, 0.0293455000, 0.0545349000, 0.1209380000, 0.2976879000", \ - "0.0142007000, 0.0157054000, 0.0195561000, 0.0292620000, 0.0544479000, 0.1208434000, 0.2975651000", \ - "0.0140460000, 0.0155539000, 0.0193777000, 0.0290965000, 0.0542931000, 0.1213705000, 0.2971941000", \ - "0.0139262000, 0.0153763000, 0.0191656000, 0.0288795000, 0.0543019000, 0.1211539000, 0.2969180000", \ - "0.0138924000, 0.0152585000, 0.0190223000, 0.0286036000, 0.0537820000, 0.1204275000, 0.2969258000", \ - "0.0145221000, 0.0158489000, 0.0194285000, 0.0287436000, 0.0538851000, 0.1206841000, 0.2966429000", \ - "0.0159786000, 0.0172985000, 0.0208316000, 0.0302313000, 0.0548786000, 0.1218351000, 0.2968918000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0157210000, 0.0148463000, 0.0123940000, 0.0046158000, -0.019178700, -0.085856100, -0.264327200", \ - "0.0155591000, 0.0146803000, 0.0122439000, 0.0044622000, -0.019359000, -0.086026600, -0.264489200", \ - "0.0153239000, 0.0144719000, 0.0120222000, 0.0042410000, -0.019577600, -0.086237300, -0.264729000", \ - "0.0151645000, 0.0142819000, 0.0118833000, 0.0040607000, -0.019775700, -0.086441500, -0.264894800", \ - "0.0150077000, 0.0140881000, 0.0116163000, 0.0038571000, -0.019959900, -0.086620200, -0.265055200", \ - "0.0145942000, 0.0137125000, 0.0114057000, 0.0037656000, -0.020016500, -0.086647100, -0.265077600", \ - "0.0194245000, 0.0180094000, 0.0143807000, 0.0049662000, -0.020002800, -0.086552200, -0.264946200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0148627000, 0.0163329000, 0.0201813000, 0.0298732000, 0.0549854000, 0.1218368000, 0.2992898000", \ - "0.0147371000, 0.0162220000, 0.0200563000, 0.0297606000, 0.0548868000, 0.1217460000, 0.2992046000", \ - "0.0145668000, 0.0160715000, 0.0198922000, 0.0295761000, 0.0547148000, 0.1216586000, 0.2972766000", \ - "0.0144044000, 0.0158955000, 0.0197050000, 0.0293805000, 0.0547669000, 0.1209214000, 0.2974585000", \ - "0.0144729000, 0.0158792000, 0.0196529000, 0.0291959000, 0.0544117000, 0.1208328000, 0.2973652000", \ - "0.0150837000, 0.0164565000, 0.0200181000, 0.0292969000, 0.0544811000, 0.1211362000, 0.2970344000", \ - "0.0161749000, 0.0174898000, 0.0210542000, 0.0303141000, 0.0552815000, 0.1222259000, 0.2988340000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0137890000, 0.0128706000, 0.0104156000, 0.0026184000, -0.021220200, -0.087868200, -0.266318400", \ - "0.0135446000, 0.0126100000, 0.0102812000, 0.0024506000, -0.021387800, -0.088044900, -0.266487000", \ - "0.0133725000, 0.0124498000, 0.0099689000, 0.0022222000, -0.021620400, -0.088273000, -0.266721000", \ - "0.0132007000, 0.0122757000, 0.0098505000, 0.0020244000, -0.021807700, -0.088470400, -0.266884600", \ - "0.0130144000, 0.0121369000, 0.0096319000, 0.0018288000, -0.021960100, -0.088615900, -0.267039900", \ - "0.0126283000, 0.0117814000, 0.0097511000, 0.0018293000, -0.022029700, -0.088699200, -0.267104300", \ - "0.0177403000, 0.0163160000, 0.0126340000, 0.0030883000, -0.021594300, -0.088232200, -0.266702900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0124666000, 0.0139336000, 0.0177305000, 0.0274424000, 0.0528560000, 0.1196759000, 0.2970432000", \ - "0.0125071000, 0.0139875000, 0.0177669000, 0.0274797000, 0.0526504000, 0.1197253000, 0.2970945000", \ - "0.0125877000, 0.0140463000, 0.0178044000, 0.0274954000, 0.0529455000, 0.1197789000, 0.2971267000", \ - "0.0123348000, 0.0137593000, 0.0174860000, 0.0271528000, 0.0526404000, 0.1194761000, 0.2966920000", \ - "0.0123878000, 0.0137551000, 0.0172644000, 0.0269016000, 0.0521763000, 0.1192810000, 0.2967750000", \ - "0.0126804000, 0.0140161000, 0.0176421000, 0.0271254000, 0.0522500000, 0.1185101000, 0.2952732000", \ - "0.0140695000, 0.0153611000, 0.0188875000, 0.0284160000, 0.0534886000, 0.1202940000, 0.2951935000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0126754000, 0.0118012000, 0.0093076000, 0.0015497000, -0.022249400, -0.088883000, -0.267326900", \ - "0.0125225000, 0.0116238000, 0.0091565000, 0.0013835000, -0.022424600, -0.089083100, -0.267525000", \ - "0.0122782000, 0.0113580000, 0.0089026000, 0.0011075000, -0.022697300, -0.089360700, -0.267790000", \ - "0.0120817000, 0.0112192000, 0.0087565000, 0.0009462000, -0.022885600, -0.089528800, -0.267968100", \ - "0.0123649000, 0.0114474000, 0.0089326000, 0.0010846000, -0.022789100, -0.089454600, -0.267871500", \ - "0.0131831000, 0.0117972000, 0.0089732000, 0.0015575000, -0.022358400, -0.089054600, -0.267481700", \ - "0.0183458000, 0.0168658000, 0.0131605000, 0.0038722000, -0.021365200, -0.087977200, -0.266344600"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0091476000, 0.0106221000, 0.0144114000, 0.0240596000, 0.0494650000, 0.1163894000, 0.2925436000", \ - "0.0090864000, 0.0105625000, 0.0143402000, 0.0239985000, 0.0491364000, 0.1162588000, 0.2924623000", \ - "0.0089243000, 0.0103698000, 0.0141146000, 0.0237679000, 0.0491827000, 0.1156094000, 0.2920572000", \ - "0.0086866000, 0.0100967000, 0.0137978000, 0.0234121000, 0.0488835000, 0.1150552000, 0.2905348000", \ - "0.0087480000, 0.0101265000, 0.0136221000, 0.0231924000, 0.0485426000, 0.1149556000, 0.2907617000", \ - "0.0090312000, 0.0103479000, 0.0139791000, 0.0235083000, 0.0485998000, 0.1151582000, 0.2933296000", \ - "0.0106540000, 0.0119514000, 0.0154695000, 0.0250473000, 0.0500748000, 0.1169077000, 0.2915438000"); - } - } - max_capacitance : 0.1767070000; - max_transition : 1.5007080000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2169105000, 0.2253080000, 0.2430200000, 0.2773116000, 0.3441820000, 0.4859842000, 0.8332647000", \ - "0.2204511000, 0.2288133000, 0.2465166000, 0.2808791000, 0.3476209000, 0.4895116000, 0.8362136000", \ - "0.2311782000, 0.2394815000, 0.2569073000, 0.2916340000, 0.3584127000, 0.5000911000, 0.8471903000", \ - "0.2583219000, 0.2667059000, 0.2843802000, 0.3185810000, 0.3854203000, 0.5271224000, 0.8742516000", \ - "0.3164949000, 0.3248757000, 0.3425455000, 0.3769932000, 0.4437416000, 0.5855078000, 0.9326229000", \ - "0.4252872000, 0.4343425000, 0.4531750000, 0.4896362000, 0.5588816000, 0.7021719000, 1.0498663000", \ - "0.6084505000, 0.6188071000, 0.6405781000, 0.6819749000, 0.7588972000, 0.9090391000, 1.2593812000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0777244000, 0.0846605000, 0.1005061000, 0.1373795000, 0.2304908000, 0.4733265000, 1.1182305000", \ - "0.0817545000, 0.0887291000, 0.1045994000, 0.1414185000, 0.2345178000, 0.4772820000, 1.1222605000", \ - "0.0921151000, 0.0990717000, 0.1148790000, 0.1517657000, 0.2448565000, 0.4880943000, 1.1315310000", \ - "0.1163186000, 0.1231595000, 0.1387572000, 0.1753016000, 0.2682628000, 0.5115038000, 1.1548007000", \ - "0.1536034000, 0.1608832000, 0.1764833000, 0.2137665000, 0.3065999000, 0.5499212000, 1.1946043000", \ - "0.1956370000, 0.2043735000, 0.2220368000, 0.2598327000, 0.3523084000, 0.5958496000, 1.2395494000", \ - "0.2192845000, 0.2306274000, 0.2530351000, 0.2946035000, 0.3865768000, 0.6296376000, 1.2740236000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0310297000, 0.0370177000, 0.0499734000, 0.0770892000, 0.1398669000, 0.2987105000, 0.7464515000", \ - "0.0307775000, 0.0370639000, 0.0499776000, 0.0771037000, 0.1399814000, 0.2976581000, 0.7449162000", \ - "0.0308863000, 0.0368709000, 0.0496370000, 0.0769726000, 0.1396805000, 0.2987688000, 0.7461698000", \ - "0.0307560000, 0.0366943000, 0.0499685000, 0.0771610000, 0.1394917000, 0.2989835000, 0.7447440000", \ - "0.0308929000, 0.0371428000, 0.0495843000, 0.0779538000, 0.1395420000, 0.2985561000, 0.7474441000", \ - "0.0347207000, 0.0410575000, 0.0541216000, 0.0827186000, 0.1443034000, 0.3007220000, 0.7420838000", \ - "0.0432821000, 0.0502937000, 0.0651372000, 0.0949222000, 0.1581829000, 0.3142053000, 0.7476599000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0231573000, 0.0299356000, 0.0474712000, 0.0948336000, 0.2244253000, 0.5709567000, 1.4973699000", \ - "0.0230892000, 0.0299025000, 0.0473547000, 0.0947927000, 0.2244234000, 0.5711366000, 1.4971110000", \ - "0.0229307000, 0.0297373000, 0.0472782000, 0.0945725000, 0.2241870000, 0.5702279000, 1.4960415000", \ - "0.0228739000, 0.0297670000, 0.0471778000, 0.0943364000, 0.2242800000, 0.5702585000, 1.4956923000", \ - "0.0259730000, 0.0322011000, 0.0491826000, 0.0953571000, 0.2239996000, 0.5716473000, 1.4961824000", \ - "0.0324515000, 0.0386573000, 0.0539845000, 0.0973164000, 0.2250482000, 0.5706970000, 1.4952461000", \ - "0.0439797000, 0.0510173000, 0.0665755000, 0.1053754000, 0.2259187000, 0.5729032000, 1.4936440000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2499118000, 0.2588086000, 0.2771111000, 0.3121280000, 0.3804095000, 0.5236780000, 0.8714386000", \ - "0.2539575000, 0.2627795000, 0.2811799000, 0.3164719000, 0.3845323000, 0.5278653000, 0.8762667000", \ - "0.2651989000, 0.2740670000, 0.2924347000, 0.3274626000, 0.3957792000, 0.5390760000, 0.8872744000", \ - "0.2909573000, 0.2997677000, 0.3179217000, 0.3535380000, 0.4214818000, 0.5649178000, 0.9131425000", \ - "0.3441559000, 0.3529680000, 0.3713345000, 0.4067947000, 0.4749557000, 0.6182238000, 0.9661194000", \ - "0.4450972000, 0.4545388000, 0.4737458000, 0.5104220000, 0.5805127000, 0.7248988000, 1.0733886000", \ - "0.6135122000, 0.6243781000, 0.6459885000, 0.6872525000, 0.7627911000, 0.9140635000, 1.2656456000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0822543000, 0.0892056000, 0.1050934000, 0.1418972000, 0.2342378000, 0.4778734000, 1.1226881000", \ - "0.0864376000, 0.0933736000, 0.1092499000, 0.1460658000, 0.2384773000, 0.4820787000, 1.1265330000", \ - "0.0956405000, 0.1026067000, 0.1184301000, 0.1552393000, 0.2480356000, 0.4912686000, 1.1345983000", \ - "0.1164297000, 0.1232365000, 0.1390017000, 0.1755870000, 0.2684822000, 0.5112734000, 1.1554356000", \ - "0.1518631000, 0.1591443000, 0.1754369000, 0.2126287000, 0.3053688000, 0.5482872000, 1.1925100000", \ - "0.1961215000, 0.2047857000, 0.2225908000, 0.2607114000, 0.3533706000, 0.5963550000, 1.2404278000", \ - "0.2291460000, 0.2402695000, 0.2626096000, 0.3038484000, 0.3976254000, 0.6409648000, 1.2845384000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0339126000, 0.0398146000, 0.0529101000, 0.0810757000, 0.1426348000, 0.3002769000, 0.7455156000", \ - "0.0340114000, 0.0400603000, 0.0529103000, 0.0801661000, 0.1429069000, 0.3015029000, 0.7440132000", \ - "0.0336751000, 0.0394246000, 0.0529110000, 0.0810637000, 0.1428213000, 0.3013599000, 0.7459360000", \ - "0.0339884000, 0.0400239000, 0.0532315000, 0.0798578000, 0.1431449000, 0.3017938000, 0.7465237000", \ - "0.0335833000, 0.0394485000, 0.0532594000, 0.0797274000, 0.1427002000, 0.3009735000, 0.7448190000", \ - "0.0373994000, 0.0434598000, 0.0559701000, 0.0841930000, 0.1464187000, 0.3029238000, 0.7454905000", \ - "0.0446836000, 0.0516316000, 0.0652109000, 0.0959285000, 0.1599701000, 0.3140552000, 0.7469174000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0230947000, 0.0299657000, 0.0474546000, 0.0947842000, 0.2243972000, 0.5713487000, 1.4957833000", \ - "0.0230795000, 0.0299359000, 0.0474826000, 0.0948458000, 0.2243363000, 0.5716370000, 1.4947552000", \ - "0.0230294000, 0.0298160000, 0.0473798000, 0.0948085000, 0.2238125000, 0.5715368000, 1.4929361000", \ - "0.0229896000, 0.0299100000, 0.0473894000, 0.0945347000, 0.2243865000, 0.5701691000, 1.4969878000", \ - "0.0256732000, 0.0321150000, 0.0489415000, 0.0952860000, 0.2236067000, 0.5697712000, 1.4970170000", \ - "0.0312322000, 0.0377093000, 0.0535962000, 0.0977028000, 0.2246448000, 0.5696832000, 1.4940242000", \ - "0.0416672000, 0.0487722000, 0.0646109000, 0.1057116000, 0.2266103000, 0.5729116000, 1.4909231000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2284027000, 0.2372364000, 0.2556069000, 0.2911346000, 0.3594813000, 0.5026260000, 0.8503909000", \ - "0.2314410000, 0.2402586000, 0.2584568000, 0.2940913000, 0.3623957000, 0.5055591000, 0.8537887000", \ - "0.2414257000, 0.2502737000, 0.2687245000, 0.3041665000, 0.3724564000, 0.5156209000, 0.8633690000", \ - "0.2669514000, 0.2756876000, 0.2939745000, 0.3295039000, 0.3976716000, 0.5409481000, 0.8889871000", \ - "0.3272032000, 0.3359914000, 0.3542445000, 0.3897925000, 0.4579690000, 0.6012265000, 0.9496789000", \ - "0.4521226000, 0.4617017000, 0.4820522000, 0.5192830000, 0.5894880000, 0.7339647000, 1.0822855000", \ - "0.6692284000, 0.6805062000, 0.7041490000, 0.7470987000, 0.8232842000, 0.9741919000, 1.3262431000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0599351000, 0.0661704000, 0.0807948000, 0.1163957000, 0.2083600000, 0.4512109000, 1.0959961000", \ - "0.0647054000, 0.0709423000, 0.0855550000, 0.1211505000, 0.2130496000, 0.4559756000, 1.1008137000", \ - "0.0758344000, 0.0820166000, 0.0965259000, 0.1320494000, 0.2241397000, 0.4672961000, 1.1125482000", \ - "0.0986171000, 0.1049138000, 0.1195167000, 0.1551283000, 0.2475176000, 0.4912155000, 1.1375927000", \ - "0.1292012000, 0.1363950000, 0.1519402000, 0.1879260000, 0.2801148000, 0.5237387000, 1.1682446000", \ - "0.1588849000, 0.1682477000, 0.1868441000, 0.2245403000, 0.3169265000, 0.5597990000, 1.2049174000", \ - "0.1646502000, 0.1771033000, 0.2017534000, 0.2461777000, 0.3392693000, 0.5828262000, 1.2264790000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0339394000, 0.0398946000, 0.0528164000, 0.0795297000, 0.1429251000, 0.3002348000, 0.7458423000", \ - "0.0340192000, 0.0393623000, 0.0531739000, 0.0798188000, 0.1429236000, 0.3014107000, 0.7472661000", \ - "0.0338698000, 0.0394114000, 0.0526758000, 0.0808004000, 0.1426647000, 0.3002338000, 0.7460902000", \ - "0.0335449000, 0.0394800000, 0.0527665000, 0.0797289000, 0.1433021000, 0.3014448000, 0.7446753000", \ - "0.0337822000, 0.0399130000, 0.0522921000, 0.0799091000, 0.1428203000, 0.3016083000, 0.7434898000", \ - "0.0381026000, 0.0444990000, 0.0583599000, 0.0851134000, 0.1467386000, 0.3030289000, 0.7474875000", \ - "0.0510831000, 0.0580595000, 0.0725431000, 0.0999751000, 0.1624320000, 0.3147804000, 0.7501955000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0196276000, 0.0259973000, 0.0433245000, 0.0913504000, 0.2217304000, 0.5698303000, 1.4963704000", \ - "0.0195944000, 0.0259733000, 0.0432801000, 0.0913206000, 0.2214369000, 0.5697339000, 1.4964372000", \ - "0.0196213000, 0.0259779000, 0.0433415000, 0.0913158000, 0.2218112000, 0.5703868000, 1.4974727000", \ - "0.0209494000, 0.0270112000, 0.0438587000, 0.0914220000, 0.2224137000, 0.5701584000, 1.4933098000", \ - "0.0257524000, 0.0313446000, 0.0468167000, 0.0926890000, 0.2216885000, 0.5702393000, 1.4959064000", \ - "0.0350912000, 0.0405114000, 0.0547596000, 0.0961289000, 0.2228424000, 0.5692476000, 1.4945585000", \ - "0.0489425000, 0.0558874000, 0.0710304000, 0.1083654000, 0.2257784000, 0.5724169000, 1.4912784000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.1908996000, 0.1997498000, 0.2181066000, 0.2536896000, 0.3215312000, 0.4648467000, 0.8130022000", \ - "0.1931995000, 0.2020688000, 0.2205303000, 0.2559782000, 0.3242811000, 0.4674844000, 0.8153627000", \ - "0.2010170000, 0.2098139000, 0.2282133000, 0.2633211000, 0.3315486000, 0.4749072000, 0.8232013000", \ - "0.2250181000, 0.2338736000, 0.2521884000, 0.2876746000, 0.3559863000, 0.4991030000, 0.8472857000", \ - "0.2858837000, 0.2946613000, 0.3128358000, 0.3481522000, 0.4162335000, 0.5595965000, 0.9075872000", \ - "0.4138523000, 0.4237111000, 0.4429433000, 0.4789527000, 0.5487844000, 0.6931452000, 1.0416854000", \ - "0.6147728000, 0.6269160000, 0.6514688000, 0.6933867000, 0.7678067000, 0.9155914000, 1.2684659000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0556202000, 0.0619824000, 0.0767586000, 0.1124617000, 0.2040580000, 0.4462823000, 1.0899163000", \ - "0.0604706000, 0.0668237000, 0.0815934000, 0.1171946000, 0.2092309000, 0.4524323000, 1.0947911000", \ - "0.0715930000, 0.0778762000, 0.0925277000, 0.1281968000, 0.2202961000, 0.4638376000, 1.1062657000", \ - "0.0929210000, 0.0994410000, 0.1143623000, 0.1500556000, 0.2422481000, 0.4895860000, 1.1306091000", \ - "0.1205733000, 0.1281512000, 0.1443418000, 0.1807373000, 0.2728873000, 0.5189966000, 1.1649448000", \ - "0.1477547000, 0.1575336000, 0.1775212000, 0.2162492000, 0.3084693000, 0.5514014000, 1.1954344000", \ - "0.1530223000, 0.1664964000, 0.1929712000, 0.2400840000, 0.3339287000, 0.5770472000, 1.2219951000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0340028000, 0.0394904000, 0.0522268000, 0.0798686000, 0.1427832000, 0.3012331000, 0.7451199000", \ - "0.0334342000, 0.0396799000, 0.0526814000, 0.0795361000, 0.1421561000, 0.3005593000, 0.7463345000", \ - "0.0335938000, 0.0397978000, 0.0530183000, 0.0800352000, 0.1428817000, 0.3017504000, 0.7460170000", \ - "0.0335863000, 0.0396667000, 0.0530589000, 0.0797525000, 0.1430834000, 0.3016152000, 0.7485313000", \ - "0.0334296000, 0.0400039000, 0.0525394000, 0.0799047000, 0.1428772000, 0.3008267000, 0.7467494000", \ - "0.0404576000, 0.0460235000, 0.0579118000, 0.0856586000, 0.1466541000, 0.3035899000, 0.7435110000", \ - "0.0559184000, 0.0628611000, 0.0757891000, 0.1019725000, 0.1577233000, 0.3113939000, 0.7502618000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0197224000, 0.0261022000, 0.0432193000, 0.0912659000, 0.2228551000, 0.5728104000, 1.4959588000", \ - "0.0196844000, 0.0261085000, 0.0433142000, 0.0910765000, 0.2221711000, 0.5722680000, 1.4960228000", \ - "0.0197933000, 0.0261707000, 0.0434321000, 0.0910497000, 0.2221612000, 0.5718181000, 1.4939016000", \ - "0.0218348000, 0.0277551000, 0.0443854000, 0.0912712000, 0.2223208000, 0.5701223000, 1.4953730000", \ - "0.0273657000, 0.0329477000, 0.0480491000, 0.0932810000, 0.2217824000, 0.5712489000, 1.4983897000", \ - "0.0377998000, 0.0435875000, 0.0576992000, 0.0976890000, 0.2231430000, 0.5687450000, 1.5007083000", \ - "0.0536107000, 0.0608527000, 0.0763098000, 0.1133056000, 0.2269724000, 0.5730075000, 1.4927577000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211o_2") { - leakage_power () { - value : 0.0033770000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0088263000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0009115000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0015595000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0033770000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0093125000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0009115000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0015595000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0033769000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0091985000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0009115000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0015595000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0010665000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0029335000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0008925000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0010281000; - when : "A1&A2&B1&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a211o"; - cell_leakage_power : 0.0031751010; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046543000, 0.0046572000, 0.0046640000, 0.0046647000, 0.0046662000, 0.0046697000, 0.0046777000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003528500, -0.003532900, -0.003542800, -0.003534400, -0.003515000, -0.003470200, -0.003367100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024540000; - } - pin ("A2") { - capacitance : 0.0023760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043393000, 0.0043395000, 0.0043399000, 0.0043391000, 0.0043372000, 0.0043328000, 0.0043227000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004337100, -0.004336200, -0.004334100, -0.004334000, -0.004333800, -0.004333200, -0.004332000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025160000; - } - pin ("B1") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038086000, 0.0038080000, 0.0038067000, 0.0038081000, 0.0038115000, 0.0038191000, 0.0038368000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003363900, -0.003447100, -0.003639100, -0.003644800, -0.003658100, -0.003688800, -0.003759400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025240000; - } - pin ("C1") { - capacitance : 0.0023280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024983000, 0.0024947000, 0.0024863000, 0.0024927000, 0.0025074000, 0.0025413000, 0.0026194000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001716900, -0.001719500, -0.001725600, -0.001726200, -0.001727700, -0.001731100, -0.001738800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025220000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0158011000, 0.0142261000, 0.0104267000, -0.000901900, -0.038212900, -0.155030100, -0.502531400", \ - "0.0156227000, 0.0140706000, 0.0102607000, -0.001036700, -0.038394200, -0.155209200, -0.502704900", \ - "0.0152209000, 0.0136510000, 0.0100322000, -0.001365200, -0.038654300, -0.155549400, -0.502897600", \ - "0.0150653000, 0.0134791000, 0.0096827000, -0.001625800, -0.039015500, -0.155790700, -0.503257300", \ - "0.0147476000, 0.0132048000, 0.0094594000, -0.001934600, -0.039298400, -0.156074200, -0.503387300", \ - "0.0148243000, 0.0132459000, 0.0094865000, -0.001959000, -0.039374000, -0.156149500, -0.503494500", \ - "0.0211190000, 0.0193027000, 0.0144366000, 0.0009827000, -0.039078500, -0.156116900, -0.503425400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0186546000, 0.0204114000, 0.0253448000, 0.0393512000, 0.0795052000, 0.1965619000, 0.5414813000", \ - "0.0185535000, 0.0202438000, 0.0252496000, 0.0392648000, 0.0794092000, 0.1963600000, 0.5394426000", \ - "0.0183925000, 0.0201152000, 0.0250833000, 0.0391266000, 0.0792406000, 0.1959027000, 0.5397464000", \ - "0.0182776000, 0.0199637000, 0.0249786000, 0.0389474000, 0.0790717000, 0.1959595000, 0.5393673000", \ - "0.0184016000, 0.0201513000, 0.0250550000, 0.0388173000, 0.0786093000, 0.1965938000, 0.5395433000", \ - "0.0192080000, 0.0207501000, 0.0253587000, 0.0389110000, 0.0785511000, 0.1949809000, 0.5389521000", \ - "0.0210287000, 0.0225103000, 0.0269792000, 0.0405872000, 0.0794993000, 0.1966853000, 0.5383591000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0187977000, 0.0172038000, 0.0134036000, 0.0019586000, -0.035214100, -0.151842200, -0.499144400", \ - "0.0187005000, 0.0170765000, 0.0132666000, 0.0018698000, -0.035398200, -0.151996100, -0.499277700", \ - "0.0185453000, 0.0169409000, 0.0131115000, 0.0017074000, -0.035559800, -0.152198100, -0.499489600", \ - "0.0183375000, 0.0167124000, 0.0128926000, 0.0014945000, -0.035787600, -0.152387800, -0.499652100", \ - "0.0181289000, 0.0165296000, 0.0127524000, 0.0013380000, -0.035956700, -0.152629300, -0.499854700", \ - "0.0181834000, 0.0165893000, 0.0128514000, 0.0013416000, -0.035978600, -0.152669200, -0.499908800", \ - "0.0252212000, 0.0233910000, 0.0183923000, 0.0045369000, -0.035641500, -0.152588200, -0.499802100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0193996000, 0.0211312000, 0.0261097000, 0.0400710000, 0.0801096000, 0.1974650000, 0.5408244000", \ - "0.0192658000, 0.0209617000, 0.0259546000, 0.0399559000, 0.0800419000, 0.1968729000, 0.5400944000", \ - "0.0191136000, 0.0208278000, 0.0257841000, 0.0398128000, 0.0799153000, 0.1965625000, 0.5402626000", \ - "0.0190936000, 0.0208039000, 0.0257344000, 0.0397367000, 0.0797740000, 0.1966313000, 0.5393049000", \ - "0.0190955000, 0.0207574000, 0.0256514000, 0.0393244000, 0.0795100000, 0.1966700000, 0.5415033000", \ - "0.0201410000, 0.0217006000, 0.0262978000, 0.0399268000, 0.0794804000, 0.1960976000, 0.5391830000", \ - "0.0215108000, 0.0230334000, 0.0275538000, 0.0411555000, 0.0808574000, 0.1975335000, 0.5408701000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0168253000, 0.0152304000, 0.0114304000, 6.270000e-05, -0.037171800, -0.153790000, -0.501084800", \ - "0.0167225000, 0.0150902000, 0.0112844000, -0.000110600, -0.037382100, -0.153993100, -0.501272400", \ - "0.0164562000, 0.0148371000, 0.0110958000, -0.000329700, -0.037604100, -0.154189800, -0.501453800", \ - "0.0162588000, 0.0146390000, 0.0108713000, -0.000505200, -0.037796500, -0.154388400, -0.501685300", \ - "0.0161323000, 0.0145050000, 0.0106899000, -0.000756500, -0.037993000, -0.154614100, -0.501884300", \ - "0.0162632000, 0.0146070000, 0.0106735000, -0.000581100, -0.038058400, -0.154783000, -0.501995100", \ - "0.0230386000, 0.0211520000, 0.0160684000, 0.0020692000, -0.038160400, -0.154659300, -0.501795000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0168897000, 0.0186249000, 0.0235872000, 0.0376414000, 0.0778229000, 0.1945585000, 0.5386232000", \ - "0.0169484000, 0.0186994000, 0.0236768000, 0.0377058000, 0.0779038000, 0.1956673000, 0.5374007000", \ - "0.0170703000, 0.0188127000, 0.0237593000, 0.0377396000, 0.0779685000, 0.1947942000, 0.5382300000", \ - "0.0169035000, 0.0185921000, 0.0234499000, 0.0373942000, 0.0776188000, 0.1948759000, 0.5405812000", \ - "0.0170003000, 0.0185654000, 0.0232573000, 0.0370922000, 0.0770722000, 0.1943290000, 0.5385272000", \ - "0.0176431000, 0.0191932000, 0.0238307000, 0.0375463000, 0.0772618000, 0.1935581000, 0.5401395000", \ - "0.0193162000, 0.0207618000, 0.0252183000, 0.0387919000, 0.0786587000, 0.1954380000, 0.5372260000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0159000000, 0.0143570000, 0.0105653000, -0.000808400, -0.038076800, -0.154760700, -0.502006900", \ - "0.0158124000, 0.0141961000, 0.0103948000, -0.000996700, -0.038265900, -0.154940200, -0.502160100", \ - "0.0154886000, 0.0139001000, 0.0101564000, -0.001231400, -0.038485100, -0.155142000, -0.502428800", \ - "0.0153343000, 0.0137207000, 0.0099276000, -0.001477800, -0.038720000, -0.155374000, -0.502645200", \ - "0.0152204000, 0.0135974000, 0.0098124000, -0.001452200, -0.038723800, -0.155404900, -0.502609800", \ - "0.0164482000, 0.0147835000, 0.0108513000, -0.000990100, -0.038037400, -0.154868300, -0.502127900", \ - "0.0247444000, 0.0227955000, 0.0175934000, 0.0029346000, -0.036814500, -0.153967800, -0.501224500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0137171000, 0.0154666000, 0.0204679000, 0.0345023000, 0.0745989000, 0.1918900000, 0.5357772000", \ - "0.0137244000, 0.0154638000, 0.0204590000, 0.0344758000, 0.0745737000, 0.1919206000, 0.5355025000", \ - "0.0136252000, 0.0153658000, 0.0203079000, 0.0343164000, 0.0744746000, 0.1915658000, 0.5358217000", \ - "0.0134526000, 0.0151306000, 0.0199867000, 0.0339105000, 0.0740678000, 0.1923575000, 0.5350303000", \ - "0.0136345000, 0.0152012000, 0.0198277000, 0.0337025000, 0.0736426000, 0.1909211000, 0.5359591000", \ - "0.0141341000, 0.0156731000, 0.0202898000, 0.0340402000, 0.0737071000, 0.1902633000, 0.5371935000", \ - "0.0159487000, 0.0173976000, 0.0218071000, 0.0353393000, 0.0752904000, 0.1921632000, 0.5337435000"); - } - } - max_capacitance : 0.3250220000; - max_transition : 1.5056200000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2572353000, 0.2646924000, 0.2815010000, 0.3153468000, 0.3800540000, 0.5159262000, 0.8543575000", \ - "0.2612747000, 0.2687305000, 0.2855267000, 0.3193544000, 0.3841061000, 0.5200032000, 0.8584629000", \ - "0.2722252000, 0.2796544000, 0.2964023000, 0.3296851000, 0.3949753000, 0.5309543000, 0.8691135000", \ - "0.2989180000, 0.3063250000, 0.3231917000, 0.3569488000, 0.4217136000, 0.5575783000, 0.8960797000", \ - "0.3572463000, 0.3645989000, 0.3814098000, 0.4149412000, 0.4801405000, 0.6160750000, 0.9544860000", \ - "0.4741640000, 0.4819402000, 0.4994228000, 0.5344275000, 0.6004990000, 0.7372167000, 1.0759719000", \ - "0.6766539000, 0.6854167000, 0.7051614000, 0.7445354000, 0.8184566000, 0.9634682000, 1.3073714000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0864484000, 0.0922712000, 0.1058440000, 0.1373426000, 0.2185346000, 0.4501413000, 1.1275969000", \ - "0.0905055000, 0.0963196000, 0.1099400000, 0.1414139000, 0.2225969000, 0.4550382000, 1.1312988000", \ - "0.1005417000, 0.1063188000, 0.1198822000, 0.1513216000, 0.2323443000, 0.4642096000, 1.1449665000", \ - "0.1252711000, 0.1308240000, 0.1442454000, 0.1754262000, 0.2562437000, 0.4888493000, 1.1657380000", \ - "0.1681852000, 0.1744526000, 0.1885089000, 0.2202341000, 0.3009613000, 0.5331786000, 1.2109609000", \ - "0.2187971000, 0.2264347000, 0.2432275000, 0.2764682000, 0.3577199000, 0.5893285000, 1.2706093000", \ - "0.2551472000, 0.2654107000, 0.2870142000, 0.3279284000, 0.4107423000, 0.6425500000, 1.3196886000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0334429000, 0.0382243000, 0.0493670000, 0.0735302000, 0.1268049000, 0.2655317000, 0.6879586000", \ - "0.0334572000, 0.0382158000, 0.0493686000, 0.0738359000, 0.1268308000, 0.2655784000, 0.6873685000", \ - "0.0334750000, 0.0383039000, 0.0498537000, 0.0731845000, 0.1258925000, 0.2654240000, 0.6882338000", \ - "0.0334672000, 0.0385639000, 0.0493078000, 0.0735601000, 0.1269348000, 0.2656406000, 0.6889882000", \ - "0.0335334000, 0.0385631000, 0.0496317000, 0.0738463000, 0.1270828000, 0.2652389000, 0.6895907000", \ - "0.0368970000, 0.0413929000, 0.0526619000, 0.0761704000, 0.1299421000, 0.2667034000, 0.6910589000", \ - "0.0451539000, 0.0506337000, 0.0627121000, 0.0890855000, 0.1442467000, 0.2809423000, 0.6955515000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0200359000, 0.0248846000, 0.0377545000, 0.0739468000, 0.1843627000, 0.5165796000, 1.5005244000", \ - "0.0201757000, 0.0249824000, 0.0376987000, 0.0739304000, 0.1844354000, 0.5173261000, 1.5014229000", \ - "0.0200595000, 0.0248868000, 0.0375982000, 0.0736788000, 0.1844096000, 0.5168687000, 1.4987029000", \ - "0.0197148000, 0.0246922000, 0.0373842000, 0.0735816000, 0.1842102000, 0.5179949000, 1.5017203000", \ - "0.0232006000, 0.0276431000, 0.0399936000, 0.0750039000, 0.1842735000, 0.5176271000, 1.5012910000", \ - "0.0304371000, 0.0354047000, 0.0469727000, 0.0798776000, 0.1861313000, 0.5167583000, 1.5025576000", \ - "0.0417940000, 0.0484433000, 0.0620890000, 0.0927581000, 0.1912474000, 0.5181077000, 1.4972903000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2909248000, 0.2989161000, 0.3166879000, 0.3515876000, 0.4178369000, 0.5554620000, 0.8955240000", \ - "0.2953372000, 0.3032459000, 0.3210994000, 0.3559743000, 0.4230721000, 0.5600511000, 0.8998138000", \ - "0.3068595000, 0.3148461000, 0.3325331000, 0.3675066000, 0.4345111000, 0.5715347000, 0.9111518000", \ - "0.3326989000, 0.3406574000, 0.3583770000, 0.3932299000, 0.4603083000, 0.5973059000, 0.9370940000", \ - "0.3856692000, 0.3936088000, 0.4112271000, 0.4462468000, 0.5130014000, 0.6507311000, 0.9906896000", \ - "0.4919707000, 0.5000483000, 0.5185303000, 0.5542461000, 0.6218393000, 0.7602948000, 1.1000161000", \ - "0.6746539000, 0.6839313000, 0.7043643000, 0.7438953000, 0.8181976000, 0.9639270000, 1.3087770000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0913416000, 0.0971137000, 0.1107339000, 0.1421090000, 0.2228869000, 0.4548585000, 1.1326470000", \ - "0.0954525000, 0.1012772000, 0.1148757000, 0.1463728000, 0.2274040000, 0.4596497000, 1.1360989000", \ - "0.1046599000, 0.1104816000, 0.1240384000, 0.1554081000, 0.2364049000, 0.4686509000, 1.1460730000", \ - "0.1257447000, 0.1314457000, 0.1448634000, 0.1761062000, 0.2570024000, 0.4893485000, 1.1654133000", \ - "0.1643014000, 0.1705117000, 0.1846486000, 0.2166192000, 0.2975325000, 0.5289880000, 1.2070104000", \ - "0.2154120000, 0.2227735000, 0.2390042000, 0.2729773000, 0.3547139000, 0.5860378000, 1.2635271000", \ - "0.2594584000, 0.2691086000, 0.2900737000, 0.3298032000, 0.4141893000, 0.6451999000, 1.3227927000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0370192000, 0.0420420000, 0.0532049000, 0.0762267000, 0.1304570000, 0.2687510000, 0.6914021000", \ - "0.0368203000, 0.0420041000, 0.0533103000, 0.0762390000, 0.1298735000, 0.2696522000, 0.6913582000", \ - "0.0366895000, 0.0421457000, 0.0535353000, 0.0763119000, 0.1298934000, 0.2694930000, 0.6910475000", \ - "0.0368047000, 0.0417948000, 0.0532884000, 0.0762345000, 0.1298615000, 0.2696278000, 0.6914318000", \ - "0.0372790000, 0.0422126000, 0.0530960000, 0.0777868000, 0.1308216000, 0.2689145000, 0.6918154000", \ - "0.0394427000, 0.0444358000, 0.0557258000, 0.0792216000, 0.1314161000, 0.2698515000, 0.6907789000", \ - "0.0469525000, 0.0525268000, 0.0650558000, 0.0900943000, 0.1445112000, 0.2818890000, 0.6966651000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0200747000, 0.0249344000, 0.0376510000, 0.0739553000, 0.1841128000, 0.5162342000, 1.4984496000", \ - "0.0201488000, 0.0249977000, 0.0377177000, 0.0739444000, 0.1844821000, 0.5175789000, 1.5015834000", \ - "0.0200759000, 0.0248836000, 0.0376455000, 0.0738994000, 0.1844477000, 0.5178694000, 1.5014998000", \ - "0.0198465000, 0.0247248000, 0.0374610000, 0.0737200000, 0.1844103000, 0.5172134000, 1.5010664000", \ - "0.0221543000, 0.0270317000, 0.0395037000, 0.0751408000, 0.1840843000, 0.5168228000, 1.4991953000", \ - "0.0281811000, 0.0331489000, 0.0455009000, 0.0790987000, 0.1860934000, 0.5171303000, 1.5013326000", \ - "0.0382474000, 0.0450715000, 0.0587232000, 0.0900045000, 0.1900353000, 0.5190317000, 1.4993115000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2694064000, 0.2773983000, 0.2951547000, 0.3301660000, 0.3963098000, 0.5339521000, 0.8740310000", \ - "0.2728116000, 0.2808000000, 0.2985076000, 0.3334711000, 0.4005080000, 0.5375141000, 0.8771619000", \ - "0.2827181000, 0.2906950000, 0.3084267000, 0.3434323000, 0.4105101000, 0.5475138000, 0.8872529000", \ - "0.3077121000, 0.3156503000, 0.3333711000, 0.3683189000, 0.4347946000, 0.5722957000, 0.9124835000", \ - "0.3674696000, 0.3753302000, 0.3930952000, 0.4279435000, 0.4948421000, 0.6324776000, 0.9725825000", \ - "0.5001655000, 0.5087786000, 0.5265382000, 0.5640403000, 0.6315513000, 0.7697823000, 1.1098708000", \ - "0.7377672000, 0.7473944000, 0.7694793000, 0.8111801000, 0.8868672000, 1.0331470000, 1.3783034000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0645328000, 0.0695169000, 0.0814693000, 0.1106351000, 0.1900914000, 0.4210508000, 1.0994056000", \ - "0.0691954000, 0.0741859000, 0.0861691000, 0.1153620000, 0.1950673000, 0.4261861000, 1.1026587000", \ - "0.0804360000, 0.0854119000, 0.0973512000, 0.1264723000, 0.2062054000, 0.4375524000, 1.1148616000", \ - "0.1050838000, 0.1101269000, 0.1221053000, 0.1511720000, 0.2310303000, 0.4617401000, 1.1407972000", \ - "0.1407032000, 0.1468952000, 0.1604865000, 0.1906499000, 0.2703852000, 0.5017831000, 1.1795894000", \ - "0.1780625000, 0.1862147000, 0.2035305000, 0.2374459000, 0.3179865000, 0.5488762000, 1.2291306000", \ - "0.1973102000, 0.2079729000, 0.2310041000, 0.2743396000, 0.3587371000, 0.5890988000, 1.2665610000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0370409000, 0.0420733000, 0.0528301000, 0.0772121000, 0.1304934000, 0.2687923000, 0.6914125000", \ - "0.0367286000, 0.0416675000, 0.0534807000, 0.0762959000, 0.1298255000, 0.2695671000, 0.6910850000", \ - "0.0370058000, 0.0420528000, 0.0526205000, 0.0762627000, 0.1298831000, 0.2696508000, 0.6912946000", \ - "0.0368968000, 0.0421038000, 0.0527637000, 0.0772803000, 0.1296725000, 0.2688902000, 0.6905509000", \ - "0.0369115000, 0.0423026000, 0.0537052000, 0.0764028000, 0.1290432000, 0.2690755000, 0.6896279000", \ - "0.0401628000, 0.0456457000, 0.0563675000, 0.0793164000, 0.1317468000, 0.2693192000, 0.6894886000", \ - "0.0527972000, 0.0577813000, 0.0703030000, 0.0950409000, 0.1475543000, 0.2827928000, 0.6955836000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0166752000, 0.0208162000, 0.0328248000, 0.0692079000, 0.1816044000, 0.5159047000, 1.4995309000", \ - "0.0166410000, 0.0208410000, 0.0328461000, 0.0691888000, 0.1817723000, 0.5160832000, 1.4993367000", \ - "0.0166302000, 0.0208308000, 0.0328505000, 0.0691754000, 0.1817776000, 0.5164741000, 1.5004017000", \ - "0.0176743000, 0.0216750000, 0.0334005000, 0.0693928000, 0.1815439000, 0.5155887000, 1.5003970000", \ - "0.0232209000, 0.0269553000, 0.0378655000, 0.0715898000, 0.1818736000, 0.5160749000, 1.4973324000", \ - "0.0323332000, 0.0366790000, 0.0474960000, 0.0782549000, 0.1836925000, 0.5154770000, 1.4993010000", \ - "0.0450822000, 0.0511900000, 0.0644686000, 0.0949005000, 0.1891156000, 0.5163547000, 1.4962510000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2340530000, 0.2420552000, 0.2598834000, 0.2948783000, 0.3618059000, 0.4993504000, 0.8390094000", \ - "0.2364658000, 0.2445179000, 0.2622773000, 0.2971805000, 0.3642230000, 0.5018740000, 0.8413241000", \ - "0.2439446000, 0.2518934000, 0.2696383000, 0.3043416000, 0.3712482000, 0.5088323000, 0.8489677000", \ - "0.2672849000, 0.2752230000, 0.2927968000, 0.3278658000, 0.3946469000, 0.5324254000, 0.8718904000", \ - "0.3276652000, 0.3355556000, 0.3532428000, 0.3880774000, 0.4549989000, 0.5926910000, 0.9323224000", \ - "0.4657643000, 0.4741963000, 0.4926938000, 0.5287359000, 0.5953447000, 0.7334384000, 1.0734375000", \ - "0.6922102000, 0.7027026000, 0.7255616000, 0.7684460000, 0.8433895000, 0.9869230000, 1.3317739000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0605958000, 0.0656752000, 0.0778619000, 0.1072099000, 0.1866084000, 0.4182393000, 1.0944197000", \ - "0.0654178000, 0.0704988000, 0.0826452000, 0.1120216000, 0.1914770000, 0.4236232000, 1.0998574000", \ - "0.0768445000, 0.0818932000, 0.0940176000, 0.1232633000, 0.2027944000, 0.4353923000, 1.1130412000", \ - "0.1009515000, 0.1061805000, 0.1184418000, 0.1477552000, 0.2272176000, 0.4596063000, 1.1362790000", \ - "0.1345420000, 0.1409852000, 0.1551093000, 0.1859862000, 0.2657890000, 0.4976086000, 1.1794897000", \ - "0.1712089000, 0.1798143000, 0.1980306000, 0.2331337000, 0.3140986000, 0.5449150000, 1.2246137000", \ - "0.1927317000, 0.2039548000, 0.2282278000, 0.2736405000, 0.3600635000, 0.5913967000, 1.2680047000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0371691000, 0.0419755000, 0.0533532000, 0.0763595000, 0.1298567000, 0.2685880000, 0.6899318000", \ - "0.0368415000, 0.0418621000, 0.0532503000, 0.0762633000, 0.1299258000, 0.2693269000, 0.6911567000", \ - "0.0371464000, 0.0421422000, 0.0528394000, 0.0766511000, 0.1292110000, 0.2690667000, 0.6910321000", \ - "0.0372302000, 0.0421668000, 0.0530118000, 0.0764747000, 0.1308328000, 0.2693240000, 0.6904763000", \ - "0.0367597000, 0.0418373000, 0.0527261000, 0.0769215000, 0.1304727000, 0.2687504000, 0.6908380000", \ - "0.0418990000, 0.0465272000, 0.0573571000, 0.0797963000, 0.1332638000, 0.2707945000, 0.6924908000", \ - "0.0587767000, 0.0649113000, 0.0776248000, 0.1009444000, 0.1490718000, 0.2809613000, 0.6974544000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0167898000, 0.0209916000, 0.0330438000, 0.0692587000, 0.1813717000, 0.5161943000, 1.5035698000", \ - "0.0167705000, 0.0209858000, 0.0330577000, 0.0692325000, 0.1812255000, 0.5176620000, 1.5025756000", \ - "0.0168067000, 0.0210540000, 0.0330864000, 0.0693966000, 0.1812213000, 0.5160575000, 1.5029064000", \ - "0.0183805000, 0.0223568000, 0.0339689000, 0.0696520000, 0.1813903000, 0.5181585000, 1.4971101000", \ - "0.0245447000, 0.0283080000, 0.0390503000, 0.0725147000, 0.1819344000, 0.5170402000, 1.5056203000", \ - "0.0344926000, 0.0389470000, 0.0498292000, 0.0802451000, 0.1842082000, 0.5149396000, 1.5042434000", \ - "0.0485009000, 0.0548500000, 0.0686329000, 0.0992861000, 0.1915137000, 0.5175211000, 1.4973809000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211o_4") { - leakage_power () { - value : 0.0033710000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0098061000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0021701000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0036611000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0033711000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0107815000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0021701000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0036611000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0033720000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0104498000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0021701000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0036611000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0022448000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0044171000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0021068000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0022659000; - when : "A1&A2&B1&!C1"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__a211o"; - cell_leakage_power : 0.0043549920; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087844000, 0.0087905000, 0.0088045000, 0.0088028000, 0.0087988000, 0.0087896000, 0.0087685000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006940900, -0.006947100, -0.006961200, -0.006948800, -0.006920300, -0.006854500, -0.006703000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045470000; - } - pin ("A2") { - capacitance : 0.0047860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082288000, 0.0082254000, 0.0082177000, 0.0082178000, 0.0082181000, 0.0082188000, 0.0082204000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008218100, -0.008216500, -0.008212700, -0.008214200, -0.008217700, -0.008225700, -0.008244200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050090000; - } - pin ("B1") { - capacitance : 0.0048560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077562000, 0.0077565000, 0.0077572000, 0.0077598000, 0.0077660000, 0.0077802000, 0.0078129000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006955100, -0.007100300, -0.007435000, -0.007444000, -0.007464600, -0.007512200, -0.007621800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0052080000; - } - pin ("C1") { - capacitance : 0.0044290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051831000, 0.0051775000, 0.0051647000, 0.0051795000, 0.0052138000, 0.0052927000, 0.0054745000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003443200, -0.003448300, -0.003460100, -0.003463300, -0.003470500, -0.003487100, -0.003525300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047710000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0322366000, 0.0302823000, 0.0248279000, 0.0094306000, -0.044650200, -0.234971500, -0.859179000", \ - "0.0319452000, 0.0299994000, 0.0245276000, 0.0091660000, -0.044943400, -0.235196200, -0.859442000", \ - "0.0315587000, 0.0295940000, 0.0239852000, 0.0086813000, -0.045427100, -0.235671300, -0.859908600", \ - "0.0311294000, 0.0292645000, 0.0237727000, 0.0082858000, -0.045830700, -0.236155700, -0.860359000", \ - "0.0307593000, 0.0288234000, 0.0232542000, 0.0078733000, -0.046392500, -0.236565900, -0.860871800", \ - "0.0309979000, 0.0289888000, 0.0233394000, 0.0077548000, -0.046513300, -0.236773700, -0.860912000", \ - "0.0412584000, 0.0391754000, 0.0327867000, 0.0137215000, -0.046081700, -0.236869900, -0.860900800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0358321000, 0.0378453000, 0.0442643000, 0.0643075000, 0.1255932000, 0.3187886000, 0.9371956000", \ - "0.0357061000, 0.0376208000, 0.0440536000, 0.0640619000, 0.1254495000, 0.3180666000, 0.9355197000", \ - "0.0354528000, 0.0374393000, 0.0438628000, 0.0638494000, 0.1251442000, 0.3179808000, 0.9362197000", \ - "0.0353372000, 0.0373293000, 0.0436037000, 0.0634959000, 0.1245722000, 0.3174247000, 0.9382001000", \ - "0.0355908000, 0.0375132000, 0.0438121000, 0.0632414000, 0.1236452000, 0.3173482000, 0.9357538000", \ - "0.0372837000, 0.0390865000, 0.0449146000, 0.0636648000, 0.1235029000, 0.3155146000, 0.9375613000", \ - "0.0402401000, 0.0419649000, 0.0476608000, 0.0664073000, 0.1247814000, 0.3172446000, 0.9333955000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0388081000, 0.0368478000, 0.0312879000, 0.0161034000, -0.038226000, -0.228689200, -0.852861800", \ - "0.0388851000, 0.0369405000, 0.0313777000, 0.0159348000, -0.038461100, -0.228928900, -0.853078500", \ - "0.0383306000, 0.0363692000, 0.0308024000, 0.0155273000, -0.038716000, -0.229167500, -0.853331100", \ - "0.0379444000, 0.0360708000, 0.0305727000, 0.0151858000, -0.039098500, -0.229377900, -0.853531500", \ - "0.0377875000, 0.0359094000, 0.0303897000, 0.0149368000, -0.039406400, -0.229906900, -0.853854800", \ - "0.0379917000, 0.0359354000, 0.0302192000, 0.0149090000, -0.039456600, -0.229981000, -0.853991400", \ - "0.0487253000, 0.0466167000, 0.0402500000, 0.0211483000, -0.039033300, -0.230110400, -0.854027500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0371342000, 0.0391607000, 0.0454953000, 0.0655306000, 0.1268459000, 0.3195929000, 0.9371482000", \ - "0.0369710000, 0.0389137000, 0.0452903000, 0.0653077000, 0.1265614000, 0.3195008000, 0.9380592000", \ - "0.0366122000, 0.0385979000, 0.0450162000, 0.0650067000, 0.1262577000, 0.3190832000, 0.9372443000", \ - "0.0366085000, 0.0385489000, 0.0449533000, 0.0648352000, 0.1258742000, 0.3188115000, 0.9371064000", \ - "0.0363940000, 0.0383395000, 0.0445965000, 0.0639752000, 0.1252599000, 0.3184400000, 0.9358991000", \ - "0.0378470000, 0.0396619000, 0.0455784000, 0.0645139000, 0.1244030000, 0.3170427000, 0.9361182000", \ - "0.0406575000, 0.0423947000, 0.0480541000, 0.0667897000, 0.1269176000, 0.3188760000, 0.9337865000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0349991000, 0.0330485000, 0.0276174000, 0.0120792000, -0.042267600, -0.232769200, -0.856923300", \ - "0.0343230000, 0.0323731000, 0.0268161000, 0.0115481000, -0.042652000, -0.233088400, -0.857250100", \ - "0.0341569000, 0.0320580000, 0.0264899000, 0.0111268000, -0.043202400, -0.233605800, -0.857673400", \ - "0.0335394000, 0.0316242000, 0.0259706000, 0.0106103000, -0.043722200, -0.233975800, -0.858125300", \ - "0.0331254000, 0.0312136000, 0.0256728000, 0.0102231000, -0.044139600, -0.234454100, -0.858492100", \ - "0.0336789000, 0.0315251000, 0.0257275000, 0.0100326000, -0.044434100, -0.234676700, -0.858709800", \ - "0.0455546000, 0.0433790000, 0.0368587000, 0.0174462000, -0.043330400, -0.234337100, -0.858160300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0323189000, 0.0342946000, 0.0405127000, 0.0597846000, 0.1197641000, 0.3115664000, 0.9287061000", \ - "0.0323618000, 0.0343690000, 0.0405841000, 0.0598435000, 0.1198887000, 0.3112516000, 0.9297896000", \ - "0.0325377000, 0.0345110000, 0.0407503000, 0.0599526000, 0.1200496000, 0.3115101000, 0.9300385000", \ - "0.0322009000, 0.0341291000, 0.0402289000, 0.0593853000, 0.1195764000, 0.3118091000, 0.9315314000", \ - "0.0323330000, 0.0341207000, 0.0399170000, 0.0589817000, 0.1188819000, 0.3107754000, 0.9295041000", \ - "0.0332604000, 0.0350398000, 0.0408480000, 0.0596606000, 0.1189334000, 0.3101296000, 0.9279700000", \ - "0.0363276000, 0.0379671000, 0.0436678000, 0.0619664000, 0.1220409000, 0.3137059000, 0.9283750000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0322925000, 0.0304839000, 0.0250289000, 0.0096642000, -0.044693000, -0.235137200, -0.859213300", \ - "0.0321046000, 0.0301830000, 0.0246468000, 0.0092171000, -0.045114200, -0.235483700, -0.859573500", \ - "0.0314025000, 0.0295666000, 0.0239825000, 0.0086047000, -0.045600900, -0.235943100, -0.860154200", \ - "0.0310072000, 0.0290426000, 0.0235712000, 0.0081655000, -0.046094100, -0.236508200, -0.860599100", \ - "0.0307371000, 0.0288258000, 0.0233036000, 0.0079065000, -0.046508900, -0.236944400, -0.860823800", \ - "0.0326261000, 0.0306511000, 0.0247789000, 0.0089381000, -0.045710200, -0.235805200, -0.859761700", \ - "0.0464652000, 0.0442177000, 0.0376299000, 0.0180290000, -0.042715500, -0.234164800, -0.858128000"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016109980, 0.0051906300, 0.0167241900, 0.0538852700, 0.1736182000, 0.5593970000"); - values("0.0257314000, 0.0277222000, 0.0341068000, 0.0535940000, 0.1139127000, 0.3059156000, 0.9201938000", \ - "0.0257258000, 0.0277341000, 0.0340505000, 0.0535849000, 0.1139353000, 0.3060225000, 0.9220799000", \ - "0.0255962000, 0.0275840000, 0.0338497000, 0.0533008000, 0.1136834000, 0.3075420000, 0.9204270000", \ - "0.0252476000, 0.0271591000, 0.0333280000, 0.0525872000, 0.1130867000, 0.3060837000, 0.9242634000", \ - "0.0254932000, 0.0273017000, 0.0330918000, 0.0521805000, 0.1122592000, 0.3050259000, 0.9238082000", \ - "0.0264709000, 0.0282508000, 0.0340303000, 0.0529474000, 0.1122653000, 0.3039954000, 0.9239495000", \ - "0.0295100000, 0.0310320000, 0.0365463000, 0.0549085000, 0.1150527000, 0.3068675000, 0.9211552000"); - } - } - max_capacitance : 0.5593970000; - max_transition : 1.5038380000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.2856875000, 0.2907152000, 0.3038002000, 0.3336763000, 0.3953710000, 0.5298653000, 0.8767365000", \ - "0.2897101000, 0.2946884000, 0.3077783000, 0.3376397000, 0.3994204000, 0.5339537000, 0.8809217000", \ - "0.3008832000, 0.3057412000, 0.3187812000, 0.3486222000, 0.4104058000, 0.5449607000, 0.8919538000", \ - "0.3276211000, 0.3325058000, 0.3455298000, 0.3752545000, 0.4370445000, 0.5715335000, 0.9184025000", \ - "0.3844702000, 0.3894142000, 0.4023747000, 0.4322060000, 0.4941514000, 0.6286189000, 0.9756872000", \ - "0.4989101000, 0.5040336000, 0.5174861000, 0.5479965000, 0.6104372000, 0.7455878000, 1.0928406000", \ - "0.7011541000, 0.7067448000, 0.7214533000, 0.7547786000, 0.8237358000, 0.9665440000, 1.3192777000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0870568000, 0.0909593000, 0.1015945000, 0.1287866000, 0.2019244000, 0.4245159000, 1.1333072000", \ - "0.0911613000, 0.0950457000, 0.1056855000, 0.1328349000, 0.2061697000, 0.4291782000, 1.1391758000", \ - "0.1014643000, 0.1053385000, 0.1159254000, 0.1429754000, 0.2162203000, 0.4393680000, 1.1498124000", \ - "0.1258936000, 0.1297045000, 0.1401067000, 0.1667886000, 0.2394457000, 0.4618272000, 1.1707414000", \ - "0.1675881000, 0.1715945000, 0.1822803000, 0.2091956000, 0.2820890000, 0.5046221000, 1.2133975000", \ - "0.2166980000, 0.2216004000, 0.2339987000, 0.2619284000, 0.3352502000, 0.5576050000, 1.2678381000", \ - "0.2512288000, 0.2576838000, 0.2737073000, 0.3085520000, 0.3832113000, 0.6056036000, 1.3137018000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0395493000, 0.0425731000, 0.0509027000, 0.0713082000, 0.1206289000, 0.2545721000, 0.6867869000", \ - "0.0396083000, 0.0426168000, 0.0509258000, 0.0713888000, 0.1205623000, 0.2545313000, 0.6859112000", \ - "0.0398908000, 0.0427884000, 0.0510599000, 0.0713834000, 0.1203893000, 0.2543065000, 0.6861525000", \ - "0.0398880000, 0.0429261000, 0.0512620000, 0.0707105000, 0.1204592000, 0.2544822000, 0.6868598000", \ - "0.0396150000, 0.0425976000, 0.0515378000, 0.0712927000, 0.1202607000, 0.2538110000, 0.6868153000", \ - "0.0425603000, 0.0454232000, 0.0535827000, 0.0737196000, 0.1226405000, 0.2554626000, 0.6854725000", \ - "0.0504605000, 0.0537204000, 0.0627603000, 0.0837482000, 0.1352099000, 0.2684315000, 0.6920695000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0221420000, 0.0253788000, 0.0350325000, 0.0644038000, 0.1599166000, 0.4763629000, 1.5006503000", \ - "0.0220745000, 0.0254608000, 0.0349854000, 0.0643152000, 0.1599054000, 0.4763859000, 1.5018790000", \ - "0.0219934000, 0.0253035000, 0.0348202000, 0.0641945000, 0.1599498000, 0.4771170000, 1.5007886000", \ - "0.0215959000, 0.0247730000, 0.0345702000, 0.0639018000, 0.1595833000, 0.4769025000, 1.5004827000", \ - "0.0244742000, 0.0276922000, 0.0368462000, 0.0652750000, 0.1600285000, 0.4757880000, 1.5009133000", \ - "0.0316981000, 0.0348820000, 0.0434008000, 0.0701915000, 0.1619774000, 0.4755160000, 1.4978976000", \ - "0.0439959000, 0.0479741000, 0.0582612000, 0.0830331000, 0.1675975000, 0.4780273000, 1.4994200000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.2947404000, 0.2998014000, 0.3130372000, 0.3423936000, 0.4029793000, 0.5342904000, 0.8785426000", \ - "0.2995128000, 0.3045240000, 0.3178222000, 0.3473564000, 0.4078730000, 0.5391741000, 0.8834115000", \ - "0.3119515000, 0.3170078000, 0.3302422000, 0.3598966000, 0.4202167000, 0.5515271000, 0.8957877000", \ - "0.3400740000, 0.3451296000, 0.3584006000, 0.3879574000, 0.4487248000, 0.5794059000, 0.9239829000", \ - "0.3979464000, 0.4030038000, 0.4161824000, 0.4456933000, 0.5062855000, 0.6377213000, 0.9820627000", \ - "0.5136720000, 0.5189028000, 0.5325164000, 0.5624919000, 0.6238005000, 0.7553355000, 1.0994171000", \ - "0.7155839000, 0.7213721000, 0.7364562000, 0.7699874000, 0.8371058000, 0.9762655000, 1.3252539000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0919621000, 0.0958728000, 0.1065032000, 0.1336478000, 0.2068716000, 0.4290899000, 1.1368835000", \ - "0.0962468000, 0.1000905000, 0.1107211000, 0.1378956000, 0.2111282000, 0.4341549000, 1.1422930000", \ - "0.1055451000, 0.1094313000, 0.1200296000, 0.1471154000, 0.2203695000, 0.4434668000, 1.1538521000", \ - "0.1270807000, 0.1309170000, 0.1413932000, 0.1682033000, 0.2411985000, 0.4642995000, 1.1746963000", \ - "0.1663586000, 0.1704235000, 0.1813711000, 0.2087338000, 0.2812732000, 0.5037598000, 1.2114370000", \ - "0.2193578000, 0.2241095000, 0.2363330000, 0.2653826000, 0.3386695000, 0.5607617000, 1.2726694000", \ - "0.2660851000, 0.2721988000, 0.2877465000, 0.3218159000, 0.3981853000, 0.6208490000, 1.3280050000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0399153000, 0.0429451000, 0.0511477000, 0.0711413000, 0.1178846000, 0.2498336000, 0.6840482000", \ - "0.0399771000, 0.0428513000, 0.0509184000, 0.0709225000, 0.1171143000, 0.2496866000, 0.6836586000", \ - "0.0399164000, 0.0429465000, 0.0511406000, 0.0698012000, 0.1178867000, 0.2498139000, 0.6840331000", \ - "0.0402358000, 0.0432961000, 0.0509044000, 0.0707649000, 0.1171320000, 0.2495772000, 0.6822868000", \ - "0.0402614000, 0.0434810000, 0.0517350000, 0.0701564000, 0.1182133000, 0.2501686000, 0.6821884000", \ - "0.0424804000, 0.0454344000, 0.0532435000, 0.0721925000, 0.1191672000, 0.2503546000, 0.6847166000", \ - "0.0505379000, 0.0537991000, 0.0625121000, 0.0828114000, 0.1314729000, 0.2618848000, 0.6877049000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0220719000, 0.0253359000, 0.0350170000, 0.0643221000, 0.1601706000, 0.4768894000, 1.5016929000", \ - "0.0221197000, 0.0254232000, 0.0350479000, 0.0642975000, 0.1602991000, 0.4761465000, 1.4995321000", \ - "0.0220779000, 0.0253586000, 0.0349067000, 0.0642437000, 0.1601298000, 0.4771194000, 1.5007138000", \ - "0.0218905000, 0.0251249000, 0.0347010000, 0.0640408000, 0.1600192000, 0.4770311000, 1.4992503000", \ - "0.0240649000, 0.0272985000, 0.0365176000, 0.0653659000, 0.1598889000, 0.4767225000, 1.5018399000", \ - "0.0296268000, 0.0327797000, 0.0424360000, 0.0693618000, 0.1619229000, 0.4759914000, 1.5004781000", \ - "0.0406895000, 0.0445766000, 0.0545610000, 0.0810396000, 0.1661865000, 0.4784668000, 1.5000430000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.2751185000, 0.2801948000, 0.2934522000, 0.3230257000, 0.3836559000, 0.5148733000, 0.8591881000", \ - "0.2780202000, 0.2830934000, 0.2963526000, 0.3260194000, 0.3863829000, 0.5177151000, 0.8620067000", \ - "0.2874797000, 0.2926251000, 0.3058590000, 0.3354859000, 0.3962107000, 0.5270501000, 0.8709657000", \ - "0.3118258000, 0.3168998000, 0.3301195000, 0.3596421000, 0.4204821000, 0.5513047000, 0.8959385000", \ - "0.3696403000, 0.3747238000, 0.3879025000, 0.4173840000, 0.4781049000, 0.6093613000, 0.9539698000", \ - "0.4976659000, 0.5028265000, 0.5167283000, 0.5473300000, 0.6087907000, 0.7403285000, 1.0845896000", \ - "0.7277179000, 0.7338088000, 0.7498294000, 0.7850099000, 0.8541070000, 0.9945134000, 1.3446726000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0641276000, 0.0673347000, 0.0762717000, 0.1001156000, 0.1695035000, 0.3894394000, 1.0988571000", \ - "0.0688170000, 0.0720353000, 0.0809709000, 0.1048315000, 0.1743784000, 0.3942491000, 1.1016815000", \ - "0.0797849000, 0.0830214000, 0.0919498000, 0.1157029000, 0.1853582000, 0.4053166000, 1.1126370000", \ - "0.1037092000, 0.1069615000, 0.1159059000, 0.1397282000, 0.2092109000, 0.4295811000, 1.1371222000", \ - "0.1370553000, 0.1409217000, 0.1509485000, 0.1759518000, 0.2458683000, 0.4665454000, 1.1737853000", \ - "0.1705527000, 0.1755878000, 0.1882528000, 0.2166583000, 0.2876653000, 0.5090986000, 1.2178673000", \ - "0.1813109000, 0.1880057000, 0.2048736000, 0.2412281000, 0.3174280000, 0.5380643000, 1.2436114000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0399733000, 0.0430311000, 0.0515516000, 0.0707541000, 0.1168975000, 0.2496567000, 0.6836965000", \ - "0.0399176000, 0.0429511000, 0.0511648000, 0.0698079000, 0.1178293000, 0.2495296000, 0.6838731000", \ - "0.0399188000, 0.0428882000, 0.0511631000, 0.0701808000, 0.1176901000, 0.2501305000, 0.6841683000", \ - "0.0402234000, 0.0428939000, 0.0510426000, 0.0698359000, 0.1174895000, 0.2496598000, 0.6823333000", \ - "0.0402486000, 0.0429500000, 0.0513386000, 0.0699309000, 0.1172787000, 0.2491601000, 0.6838548000", \ - "0.0439201000, 0.0470331000, 0.0549710000, 0.0739028000, 0.1199637000, 0.2519704000, 0.6843851000", \ - "0.0565186000, 0.0599273000, 0.0683941000, 0.0887207000, 0.1354372000, 0.2633751000, 0.6901671000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0178087000, 0.0206291000, 0.0295061000, 0.0585200000, 0.1556262000, 0.4741025000, 1.5011904000", \ - "0.0178121000, 0.0206827000, 0.0295447000, 0.0585504000, 0.1557912000, 0.4733520000, 1.4977766000", \ - "0.0178160000, 0.0205849000, 0.0295516000, 0.0584993000, 0.1556400000, 0.4735015000, 1.4974745000", \ - "0.0188272000, 0.0215192000, 0.0301720000, 0.0587197000, 0.1557986000, 0.4737341000, 1.4975263000", \ - "0.0238424000, 0.0263464000, 0.0344322000, 0.0612809000, 0.1559380000, 0.4734331000, 1.4968941000", \ - "0.0333320000, 0.0358511000, 0.0438703000, 0.0681013000, 0.1579896000, 0.4735695000, 1.4999765000", \ - "0.0466599000, 0.0505911000, 0.0605936000, 0.0844909000, 0.1650072000, 0.4759026000, 1.4929707000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.2345037000, 0.2395532000, 0.2529028000, 0.2824408000, 0.3429973000, 0.4743609000, 0.8186568000", \ - "0.2368269000, 0.2419679000, 0.2552630000, 0.2848683000, 0.3455166000, 0.4770112000, 0.8209336000", \ - "0.2447472000, 0.2498002000, 0.2628241000, 0.2924909000, 0.3529225000, 0.4842410000, 0.8286449000", \ - "0.2693265000, 0.2743672000, 0.2876051000, 0.3171219000, 0.3777202000, 0.5092421000, 0.8532542000", \ - "0.3328171000, 0.3379156000, 0.3511336000, 0.3807395000, 0.4413456000, 0.5728198000, 0.9172853000", \ - "0.4810669000, 0.4863471000, 0.5000815000, 0.5302728000, 0.5911433000, 0.7209153000, 1.0649812000", \ - "0.7338798000, 0.7403906000, 0.7575583000, 0.7947115000, 0.8641746000, 1.0008790000, 1.3498923000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0616369000, 0.0649783000, 0.0742901000, 0.0987160000, 0.1685097000, 0.3881851000, 1.0960394000", \ - "0.0662534000, 0.0696063000, 0.0788887000, 0.1034282000, 0.1732460000, 0.3929230000, 1.1139482000", \ - "0.0773148000, 0.0806414000, 0.0898821000, 0.1143149000, 0.1843586000, 0.4045158000, 1.1132999000", \ - "0.0999440000, 0.1033689000, 0.1127314000, 0.1371624000, 0.2073858000, 0.4283673000, 1.1341664000", \ - "0.1301315000, 0.1342994000, 0.1447946000, 0.1705622000, 0.2411686000, 0.4624461000, 1.1686591000", \ - "0.1573492000, 0.1627031000, 0.1763241000, 0.2061366000, 0.2780827000, 0.4986991000, 1.2068481000", \ - "0.1570861000, 0.1640671000, 0.1822407000, 0.2209569000, 0.2993921000, 0.5195087000, 1.2267019000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0400509000, 0.0428737000, 0.0510754000, 0.0709754000, 0.1170794000, 0.2497207000, 0.6840254000", \ - "0.0399623000, 0.0430360000, 0.0511577000, 0.0700017000, 0.1172588000, 0.2500031000, 0.6844618000", \ - "0.0400599000, 0.0430569000, 0.0509788000, 0.0707152000, 0.1178490000, 0.2493851000, 0.6831913000", \ - "0.0399166000, 0.0429725000, 0.0508312000, 0.0707839000, 0.1169752000, 0.2502215000, 0.6842946000", \ - "0.0402251000, 0.0430459000, 0.0507812000, 0.0698500000, 0.1171400000, 0.2496105000, 0.6832820000", \ - "0.0448358000, 0.0478526000, 0.0564413000, 0.0733712000, 0.1187520000, 0.2518399000, 0.6847739000", \ - "0.0637558000, 0.0672903000, 0.0762557000, 0.0966580000, 0.1383432000, 0.2614313000, 0.6891412000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016110000, 0.0051906300, 0.0167242000, 0.0538853000, 0.1736180000, 0.5593970000"); - values("0.0182508000, 0.0210669000, 0.0300391000, 0.0588733000, 0.1553422000, 0.4737125000, 1.5009366000", \ - "0.0182249000, 0.0210988000, 0.0300378000, 0.0589251000, 0.1558124000, 0.4761699000, 1.5038376000", \ - "0.0182313000, 0.0210784000, 0.0300926000, 0.0588997000, 0.1557027000, 0.4761833000, 1.4992977000", \ - "0.0198243000, 0.0225180000, 0.0311881000, 0.0594178000, 0.1558606000, 0.4753937000, 1.5033070000", \ - "0.0253861000, 0.0279727000, 0.0360848000, 0.0625571000, 0.1564769000, 0.4749359000, 1.5019243000", \ - "0.0358669000, 0.0387199000, 0.0467705000, 0.0708261000, 0.1591203000, 0.4737829000, 1.4984619000", \ - "0.0502490000, 0.0545919000, 0.0652988000, 0.0899610000, 0.1682293000, 0.4751127000, 1.4962180000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211oi_1") { - leakage_power () { - value : 0.0025126000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0008228000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 8.0514879e-05; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0006932000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0025126000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0012490000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 8.0514879e-05; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0006932000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0025126000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0010943000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 8.0514879e-05; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0006932000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0002412000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0021221000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 6.2648583e-05; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0001996000; - when : "A1&A2&B1&!C1"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__a211oi"; - cell_leakage_power : 0.0009781671; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044984000, 0.0045041000, 0.0045175000, 0.0045192000, 0.0045232000, 0.0045325000, 0.0045539000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003588500, -0.003590800, -0.003596200, -0.003589700, -0.003574700, -0.003540100, -0.003460300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024850000; - } - pin ("A2") { - capacitance : 0.0023770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040315000, 0.0040271000, 0.0040170000, 0.0040186000, 0.0040224000, 0.0040309000, 0.0040508000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004041100, -0.004034200, -0.004018300, -0.004017600, -0.004016000, -0.004012300, -0.004003800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("B1") { - capacitance : 0.0024080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038973000, 0.0038977000, 0.0038986000, 0.0038964000, 0.0038915000, 0.0038801000, 0.0038538000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003466100, -0.003549100, -0.003740600, -0.003746300, -0.003759500, -0.003789900, -0.003860100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - } - pin ("C1") { - capacitance : 0.0023570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026285000, 0.0026227000, 0.0026094000, 0.0026168000, 0.0026339000, 0.0026732000, 0.0027640000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001710900, -0.001710800, -0.001710600, -0.001710600, -0.001710700, -0.001710900, -0.001711300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025380000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0062803000, 0.0053688000, 0.0034141000, -0.000756800, -0.009638000, -0.028666600, -0.069547000", \ - "0.0061549000, 0.0052415000, 0.0032921000, -0.000870700, -0.009746400, -0.028774100, -0.069664300", \ - "0.0060013000, 0.0050866000, 0.0031347000, -0.001017300, -0.009875000, -0.028896300, -0.069804000", \ - "0.0057963000, 0.0049056000, 0.0029742000, -0.001152800, -0.010042900, -0.029034300, -0.069873100", \ - "0.0056644000, 0.0047593000, 0.0028654000, -0.001293200, -0.010109800, -0.029166800, -0.070003100", \ - "0.0061013000, 0.0051551000, 0.0031551000, -0.001043700, -0.010055100, -0.029137700, -0.070036400", \ - "0.0073151000, 0.0063592000, 0.0042704000, 4.240000e-05, -0.009042500, -0.028479100, -0.069724500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0113506000, 0.0123128000, 0.0143345000, 0.0185846000, 0.0274692000, 0.0464653000, 0.0869768000", \ - "0.0111129000, 0.0120947000, 0.0141319000, 0.0184277000, 0.0273836000, 0.0464538000, 0.0869562000", \ - "0.0108484000, 0.0118121000, 0.0138624000, 0.0181714000, 0.0273350000, 0.0466528000, 0.0869509000", \ - "0.0107008000, 0.0116410000, 0.0136440000, 0.0179242000, 0.0269503000, 0.0463803000, 0.0867768000", \ - "0.0105720000, 0.0114833000, 0.0134553000, 0.0176957000, 0.0266431000, 0.0457862000, 0.0865611000", \ - "0.0105567000, 0.0114819000, 0.0134579000, 0.0176417000, 0.0265423000, 0.0457647000, 0.0865497000", \ - "0.0103166000, 0.0112463000, 0.0131607000, 0.0175896000, 0.0267304000, 0.0456203000, 0.0863105000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0066063000, 0.0056964000, 0.0037419000, -0.000438800, -0.009312400, -0.028360200, -0.069230000", \ - "0.0064866000, 0.0055696000, 0.0036113000, -0.000554400, -0.009432500, -0.028483200, -0.069368700", \ - "0.0063370000, 0.0054135000, 0.0034610000, -0.000709000, -0.009577400, -0.028626700, -0.069495000", \ - "0.0062000000, 0.0052972000, 0.0033571000, -0.000800000, -0.009677900, -0.028713600, -0.069585400", \ - "0.0060823000, 0.0051751000, 0.0032489000, -0.000865100, -0.009749100, -0.028798100, -0.069655800", \ - "0.0064050000, 0.0054861000, 0.0035289000, -0.000685800, -0.009693400, -0.028811900, -0.069670400", \ - "0.0073781000, 0.0064225000, 0.0044494000, 0.0001075000, -0.008897900, -0.028308800, -0.069500800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0145050000, 0.0154312000, 0.0174064000, 0.0215891000, 0.0304780000, 0.0494880000, 0.0900255000", \ - "0.0143781000, 0.0153002000, 0.0172914000, 0.0214995000, 0.0304350000, 0.0493794000, 0.0899326000", \ - "0.0142307000, 0.0151553000, 0.0171519000, 0.0213811000, 0.0303337000, 0.0493068000, 0.0899162000", \ - "0.0141004000, 0.0150194000, 0.0170089000, 0.0212319000, 0.0302014000, 0.0492443000, 0.0898338000", \ - "0.0139802000, 0.0148997000, 0.0168747000, 0.0210800000, 0.0300211000, 0.0490419000, 0.0895724000", \ - "0.0139617000, 0.0149035000, 0.0168767000, 0.0210292000, 0.0299474000, 0.0489927000, 0.0895795000", \ - "0.0137682000, 0.0146812000, 0.0165876000, 0.0210360000, 0.0301472000, 0.0491045000, 0.0895639000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0038910000, 0.0029802000, 0.0010311000, -0.003129300, -0.012071600, -0.031228900, -0.072223300", \ - "0.0039231000, 0.0030209000, 0.0010928000, -0.003074200, -0.011997200, -0.031137200, -0.072126500", \ - "0.0039798000, 0.0030949000, 0.0011883000, -0.002931200, -0.011845500, -0.030957500, -0.071927000", \ - "0.0037337000, 0.0028590000, 0.0009709000, -0.003069200, -0.011945500, -0.031013600, -0.071954400", \ - "0.0038898000, 0.0028926000, 0.0009728000, -0.003151900, -0.012079000, -0.031098500, -0.071988400", \ - "0.0041051000, 0.0031985000, 0.0013183000, -0.002945000, -0.011997800, -0.031190700, -0.071892500", \ - "0.0053162000, 0.0043459000, 0.0022882000, -0.002002800, -0.011227100, -0.030464800, -0.071621000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0123065000, 0.0132460000, 0.0152425000, 0.0194827000, 0.0284209000, 0.0474374000, 0.0879637000", \ - "0.0120984000, 0.0130431000, 0.0150591000, 0.0193221000, 0.0283167000, 0.0473498000, 0.0878237000", \ - "0.0118794000, 0.0128169000, 0.0148429000, 0.0191015000, 0.0281234000, 0.0472402000, 0.0878777000", \ - "0.0117357000, 0.0126702000, 0.0146635000, 0.0188840000, 0.0278626000, 0.0470478000, 0.0876783000", \ - "0.0116482000, 0.0125695000, 0.0145476000, 0.0187582000, 0.0277227000, 0.0468081000, 0.0873603000", \ - "0.0116068000, 0.0125346000, 0.0144914000, 0.0186806000, 0.0277266000, 0.0467535000, 0.0873878000", \ - "0.0120842000, 0.0129698000, 0.0148691000, 0.0189772000, 0.0279240000, 0.0467787000, 0.0875129000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0004892000, -0.000392600, -0.002304100, -0.006453400, -0.015397500, -0.034568400, -0.075590900", \ - "0.0003596000, -0.000494200, -0.002363200, -0.006467700, -0.015351500, -0.034493100, -0.075501100", \ - "0.0001857000, -0.000657100, -0.002499900, -0.006536100, -0.015374500, -0.034451800, -0.075419200", \ - "-4.96000e-05, -0.000882200, -0.002700800, -0.006712900, -0.015479300, -0.034497100, -0.075426800", \ - "8.050000e-05, -0.000794000, -0.002786500, -0.006849600, -0.015707800, -0.034630200, -0.075480800", \ - "0.0004200000, -0.000499100, -0.002435700, -0.006808800, -0.015688000, -0.034797100, -0.075478900", \ - "0.0019784000, 0.0009926000, -0.001135300, -0.005608800, -0.014928200, -0.034032800, -0.075211500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0112923000, 0.0122463000, 0.0142587000, 0.0185310000, 0.0274953000, 0.0465232000, 0.0870549000", \ - "0.0110512000, 0.0120214000, 0.0140408000, 0.0183347000, 0.0273682000, 0.0463892000, 0.0870571000", \ - "0.0108235000, 0.0117423000, 0.0137548000, 0.0180455000, 0.0271345000, 0.0462832000, 0.0869417000", \ - "0.0107180000, 0.0115909000, 0.0135960000, 0.0178270000, 0.0268303000, 0.0460530000, 0.0867443000", \ - "0.0108735000, 0.0117929000, 0.0137379000, 0.0178452000, 0.0267374000, 0.0458171000, 0.0865445000", \ - "0.0115838000, 0.0124633000, 0.0144093000, 0.0185509000, 0.0268955000, 0.0457467000, 0.0863213000", \ - "0.0127779000, 0.0136291000, 0.0154873000, 0.0194800000, 0.0279059000, 0.0465064000, 0.0863987000"); - } - } - max_capacitance : 0.0476170000; - max_transition : 1.4910050000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0324412000, 0.0360747000, 0.0435330000, 0.0585984000, 0.0885819000, 0.1494614000, 0.2759021000", \ - "0.0367436000, 0.0403787000, 0.0477122000, 0.0626236000, 0.0925840000, 0.1534192000, 0.2800790000", \ - "0.0477125000, 0.0510549000, 0.0580973000, 0.0726740000, 0.1024258000, 0.1632165000, 0.2896691000", \ - "0.0693250000, 0.0735887000, 0.0820586000, 0.0975556000, 0.1259013000, 0.1863852000, 0.3129081000", \ - "0.0957856000, 0.1021188000, 0.1145103000, 0.1374560000, 0.1773255000, 0.2424516000, 0.3684330000", \ - "0.1209173000, 0.1301893000, 0.1488533000, 0.1823734000, 0.2431846000, 0.3414376000, 0.4921701000", \ - "0.1195777000, 0.1338013000, 0.1619446000, 0.2148445000, 0.3060176000, 0.4574891000, 0.6921864000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1308228000, 0.1430269000, 0.1694186000, 0.2244026000, 0.3388981000, 0.5836877000, 1.1061446000", \ - "0.1343641000, 0.1470174000, 0.1734846000, 0.2291989000, 0.3441486000, 0.5896128000, 1.1123186000", \ - "0.1458003000, 0.1582513000, 0.1847020000, 0.2405682000, 0.3581186000, 0.6061658000, 1.1258167000", \ - "0.1737943000, 0.1860410000, 0.2122237000, 0.2672624000, 0.3842217000, 0.6364461000, 1.1539447000", \ - "0.2309099000, 0.2436834000, 0.2697724000, 0.3242823000, 0.4400490000, 0.6865368000, 1.2110896000", \ - "0.3262133000, 0.3430406000, 0.3755437000, 0.4395274000, 0.5626275000, 0.8086676000, 1.3373226000", \ - "0.4790731000, 0.5042852000, 0.5520319000, 0.6373097000, 0.7959640000, 1.0787564000, 1.6109680000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0342941000, 0.0385107000, 0.0471326000, 0.0647526000, 0.1018941000, 0.1802514000, 0.3458560000", \ - "0.0334173000, 0.0376824000, 0.0464761000, 0.0644375000, 0.1016934000, 0.1796494000, 0.3455390000", \ - "0.0343564000, 0.0380442000, 0.0459915000, 0.0637088000, 0.1012213000, 0.1792269000, 0.3467385000", \ - "0.0468266000, 0.0504133000, 0.0568232000, 0.0705724000, 0.1037055000, 0.1792922000, 0.3460666000", \ - "0.0708747000, 0.0754964000, 0.0853081000, 0.1023564000, 0.1332050000, 0.1943013000, 0.3483657000", \ - "0.1141052000, 0.1214519000, 0.1347078000, 0.1599010000, 0.2060543000, 0.2746994000, 0.4023155000", \ - "0.1908714000, 0.2019242000, 0.2232950000, 0.2647987000, 0.3256443000, 0.4297374000, 0.5903364000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0926044000, 0.1087710000, 0.1429159000, 0.2153663000, 0.3707426000, 0.6995404000, 1.4017565000", \ - "0.0930805000, 0.1090378000, 0.1429765000, 0.2159252000, 0.3703183000, 0.6998075000, 1.4016381000", \ - "0.0929663000, 0.1086542000, 0.1429237000, 0.2156175000, 0.3722564000, 0.7040382000, 1.4019275000", \ - "0.0932675000, 0.1089129000, 0.1430315000, 0.2156285000, 0.3701695000, 0.7054278000, 1.4048902000", \ - "0.1006310000, 0.1152250000, 0.1473130000, 0.2171925000, 0.3697974000, 0.6987035000, 1.4020564000", \ - "0.1315130000, 0.1474059000, 0.1796459000, 0.2455769000, 0.3853095000, 0.7038536000, 1.4085754000", \ - "0.2065851000, 0.2238066000, 0.2588116000, 0.3297831000, 0.4755452000, 0.7611153000, 1.4212586000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0369941000, 0.0406137000, 0.0480550000, 0.0630028000, 0.0929230000, 0.1538540000, 0.2804096000", \ - "0.0414081000, 0.0450197000, 0.0523748000, 0.0672655000, 0.0971990000, 0.1580760000, 0.2846174000", \ - "0.0513956000, 0.0548551000, 0.0620548000, 0.0768149000, 0.1065954000, 0.1674817000, 0.2940051000", \ - "0.0713092000, 0.0754310000, 0.0837225000, 0.0989469000, 0.1287102000, 0.1895463000, 0.3162515000", \ - "0.1000148000, 0.1059667000, 0.1170841000, 0.1375040000, 0.1747006000, 0.2395344000, 0.3667441000", \ - "0.1324145000, 0.1410773000, 0.1579362000, 0.1880712000, 0.2427623000, 0.3315578000, 0.4794851000", \ - "0.1482953000, 0.1615416000, 0.1857781000, 0.2357664000, 0.3194884000, 0.4562637000, 0.6684532000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1595156000, 0.1717968000, 0.1980758000, 0.2536183000, 0.3716226000, 0.6229489000, 1.1591496000", \ - "0.1638783000, 0.1763879000, 0.2026295000, 0.2586623000, 0.3770378000, 0.6289054000, 1.1674867000", \ - "0.1756793000, 0.1880368000, 0.2148554000, 0.2710156000, 0.3895682000, 0.6413352000, 1.1779445000", \ - "0.2020690000, 0.2146061000, 0.2409080000, 0.2969003000, 0.4157506000, 0.6679557000, 1.2051089000", \ - "0.2554101000, 0.2678607000, 0.2941053000, 0.3499356000, 0.4684992000, 0.7207684000, 1.2593255000", \ - "0.3455282000, 0.3607486000, 0.3924154000, 0.4551121000, 0.5793424000, 0.8310679000, 1.3682768000", \ - "0.4911470000, 0.5121595000, 0.5535541000, 0.6355615000, 0.7884384000, 1.0735631000, 1.6175346000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0337779000, 0.0380380000, 0.0467928000, 0.0646806000, 0.1016698000, 0.1799062000, 0.3456145000", \ - "0.0333509000, 0.0376068000, 0.0463824000, 0.0642507000, 0.1015209000, 0.1798661000, 0.3471486000", \ - "0.0336970000, 0.0376522000, 0.0460389000, 0.0638517000, 0.1010655000, 0.1796780000, 0.3458433000", \ - "0.0421952000, 0.0456321000, 0.0526604000, 0.0678338000, 0.1026270000, 0.1790810000, 0.3464481000", \ - "0.0623878000, 0.0664810000, 0.0749047000, 0.0913692000, 0.1222757000, 0.1883812000, 0.3480904000", \ - "0.1009553000, 0.1069236000, 0.1183049000, 0.1380673000, 0.1768644000, 0.2467010000, 0.3810896000", \ - "0.1698610000, 0.1783663000, 0.1953190000, 0.2260632000, 0.2806655000, 0.3674723000, 0.5188867000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1185914000, 0.1350310000, 0.1701727000, 0.2445685000, 0.4032017000, 0.7430039000, 1.4667838000", \ - "0.1190628000, 0.1350390000, 0.1700877000, 0.2445525000, 0.4046342000, 0.7428405000, 1.4654498000", \ - "0.1185789000, 0.1351577000, 0.1700797000, 0.2449895000, 0.4032142000, 0.7410756000, 1.4658058000", \ - "0.1190820000, 0.1350341000, 0.1703164000, 0.2445480000, 0.4031284000, 0.7408106000, 1.4634346000", \ - "0.1240517000, 0.1394734000, 0.1732589000, 0.2456288000, 0.4032650000, 0.7411751000, 1.4639308000", \ - "0.1527722000, 0.1689174000, 0.2023542000, 0.2717261000, 0.4182188000, 0.7439867000, 1.4622852000", \ - "0.2223932000, 0.2395230000, 0.2761331000, 0.3496939000, 0.4998654000, 0.8047798000, 1.4829624000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0220150000, 0.0240520000, 0.0283023000, 0.0370987000, 0.0552611000, 0.0933571000, 0.1740430000", \ - "0.0267949000, 0.0288676000, 0.0330850000, 0.0417964000, 0.0599598000, 0.0980675000, 0.1787478000", \ - "0.0375739000, 0.0399079000, 0.0444507000, 0.0530071000, 0.0710241000, 0.1091339000, 0.1898196000", \ - "0.0522651000, 0.0558925000, 0.0628541000, 0.0756834000, 0.0965349000, 0.1347263000, 0.2153148000", \ - "0.0675705000, 0.0734032000, 0.0844115000, 0.1044941000, 0.1378671000, 0.1912415000, 0.2757565000", \ - "0.0746858000, 0.0834588000, 0.1000852000, 0.1321627000, 0.1856256000, 0.2692996000, 0.3946442000", \ - "0.0480720000, 0.0612581000, 0.0882478000, 0.1379889000, 0.2223860000, 0.3546705000, 0.5537598000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1418708000, 0.1546727000, 0.1813711000, 0.2375615000, 0.3562563000, 0.6075375000, 1.1439286000", \ - "0.1448804000, 0.1575113000, 0.1844868000, 0.2408662000, 0.3600552000, 0.6121488000, 1.1503216000", \ - "0.1550120000, 0.1676438000, 0.1945313000, 0.2510574000, 0.3706314000, 0.6233946000, 1.1607236000", \ - "0.1810027000, 0.1935679000, 0.2199582000, 0.2762441000, 0.3955148000, 0.6486366000, 1.1864725000", \ - "0.2411382000, 0.2539440000, 0.2804631000, 0.3365627000, 0.4553247000, 0.7078607000, 1.2473029000", \ - "0.3482921000, 0.3657666000, 0.4008473000, 0.4691607000, 0.5961420000, 0.8495369000, 1.3869418000", \ - "0.5289852000, 0.5561051000, 0.6082604000, 0.7051192000, 0.8775529000, 1.1692336000, 1.7156354000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0212652000, 0.0236964000, 0.0288229000, 0.0396760000, 0.0628222000, 0.1125744000, 0.2189729000", \ - "0.0210144000, 0.0233813000, 0.0286364000, 0.0395655000, 0.0628300000, 0.1130710000, 0.2191313000", \ - "0.0252940000, 0.0271568000, 0.0312777000, 0.0409564000, 0.0629011000, 0.1124580000, 0.2190239000", \ - "0.0400831000, 0.0422262000, 0.0464541000, 0.0548465000, 0.0722889000, 0.1151722000, 0.2189136000", \ - "0.0668746000, 0.0693820000, 0.0756851000, 0.0875234000, 0.1088756000, 0.1451680000, 0.2306458000", \ - "0.1131910000, 0.1182513000, 0.1287721000, 0.1462222000, 0.1774006000, 0.2282799000, 0.3124491000", \ - "0.1972934000, 0.2051865000, 0.2198442000, 0.2478597000, 0.2959805000, 0.3742199000, 0.4961680000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1185351000, 0.1352139000, 0.1699542000, 0.2444503000, 0.4036629000, 0.7409459000, 1.4655840000", \ - "0.1186988000, 0.1350320000, 0.1702823000, 0.2445462000, 0.4031664000, 0.7407906000, 1.4634575000", \ - "0.1185713000, 0.1352302000, 0.1700267000, 0.2445045000, 0.4031598000, 0.7410915000, 1.4638525000", \ - "0.1187615000, 0.1350606000, 0.1701623000, 0.2445186000, 0.4031661000, 0.7418652000, 1.4611861000", \ - "0.1296174000, 0.1443649000, 0.1764386000, 0.2475543000, 0.4030941000, 0.7411727000, 1.4653162000", \ - "0.1763482000, 0.1918160000, 0.2229514000, 0.2849534000, 0.4245927000, 0.7443139000, 1.4618240000", \ - "0.2730112000, 0.2929056000, 0.3298662000, 0.4011946000, 0.5421373000, 0.8158191000, 1.4780327000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0184392000, 0.0204351000, 0.0245662000, 0.0332393000, 0.0515413000, 0.0904340000, 0.1733318000", \ - "0.0231773000, 0.0251958000, 0.0293797000, 0.0381087000, 0.0565167000, 0.0954614000, 0.1783630000", \ - "0.0322459000, 0.0350754000, 0.0403825000, 0.0495205000, 0.0679255000, 0.1066223000, 0.1896482000", \ - "0.0435084000, 0.0477544000, 0.0560345000, 0.0704691000, 0.0938524000, 0.1333043000, 0.2150752000", \ - "0.0527353000, 0.0596634000, 0.0735145000, 0.0965380000, 0.1333431000, 0.1902454000, 0.2772923000", \ - "0.0528882000, 0.0641641000, 0.0849029000, 0.1215733000, 0.1804275000, 0.2694881000, 0.3993577000", \ - "0.0187118000, 0.0356518000, 0.0686164000, 0.1262084000, 0.2191738000, 0.3599731000, 0.5667718000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1062713000, 0.1191400000, 0.1460369000, 0.2023917000, 0.3214055000, 0.5732487000, 1.1098042000", \ - "0.1081676000, 0.1208473000, 0.1476311000, 0.2047507000, 0.3243498000, 0.5767505000, 1.1137875000", \ - "0.1161262000, 0.1283055000, 0.1551862000, 0.2122960000, 0.3323429000, 0.5857490000, 1.1237581000", \ - "0.1409518000, 0.1525259000, 0.1791496000, 0.2350824000, 0.3543796000, 0.6080919000, 1.1463694000", \ - "0.2025036000, 0.2153985000, 0.2411349000, 0.2948922000, 0.4129395000, 0.6650272000, 1.2034947000", \ - "0.3050166000, 0.3240831000, 0.3627025000, 0.4326794000, 0.5579012000, 0.8062552000, 1.3418254000", \ - "0.4696228000, 0.4971145000, 0.5517876000, 0.6557396000, 0.8345351000, 1.1365909000, 1.6660144000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0161361000, 0.0188460000, 0.0244107000, 0.0359124000, 0.0600108000, 0.1115466000, 0.2212684000", \ - "0.0165182000, 0.0190287000, 0.0244392000, 0.0359025000, 0.0599966000, 0.1114174000, 0.2210923000", \ - "0.0229970000, 0.0245401000, 0.0284913000, 0.0379455000, 0.0602667000, 0.1115357000, 0.2213014000", \ - "0.0382341000, 0.0404689000, 0.0448509000, 0.0532247000, 0.0702925000, 0.1140963000, 0.2210749000", \ - "0.0656464000, 0.0688754000, 0.0744253000, 0.0862122000, 0.1077822000, 0.1447773000, 0.2321075000", \ - "0.1139292000, 0.1185473000, 0.1279132000, 0.1454365000, 0.1763675000, 0.2282077000, 0.3144934000", \ - "0.2029183000, 0.2094540000, 0.2233852000, 0.2504343000, 0.2962812000, 0.3751901000, 0.4985866000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1180911000, 0.1348524000, 0.1704704000, 0.2446388000, 0.4032398000, 0.7415775000, 1.4624859000", \ - "0.1179285000, 0.1348557000, 0.1699902000, 0.2445670000, 0.4031441000, 0.7411898000, 1.4633807000", \ - "0.1176462000, 0.1341129000, 0.1695632000, 0.2444881000, 0.4035890000, 0.7410885000, 1.4645939000", \ - "0.1159081000, 0.1322920000, 0.1676110000, 0.2449191000, 0.4031725000, 0.7410755000, 1.4607978000", \ - "0.1374020000, 0.1505418000, 0.1808537000, 0.2475712000, 0.4020887000, 0.7409938000, 1.4634659000", \ - "0.1872038000, 0.2052554000, 0.2411721000, 0.3068981000, 0.4361030000, 0.7442150000, 1.4642828000", \ - "0.2761023000, 0.3009276000, 0.3483774000, 0.4345829000, 0.5874232000, 0.8579736000, 1.4910051000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211oi_2") { - leakage_power () { - value : 0.0035885000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0016038000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0002537000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0023224000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0035885000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0022978000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0002537000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0023224000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0035885000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0021311000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0002537000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0023224000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0004620000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0043304000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0001730000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0004472000; - when : "A1&A2&B1&!C1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__a211oi"; - cell_leakage_power : 0.0018711960; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091896000, 0.0091992000, 0.0092215000, 0.0092208000, 0.0092193000, 0.0092159000, 0.0092079000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006375400, -0.006378500, -0.006385700, -0.006367400, -0.006325300, -0.006228100, -0.006004100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045040000; - } - pin ("A2") { - capacitance : 0.0043880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079358000, 0.0079315000, 0.0079215000, 0.0079207000, 0.0079187000, 0.0079142000, 0.0079038000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007896800, -0.007896200, -0.007894700, -0.007895200, -0.007896100, -0.007898300, -0.007903400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045940000; - } - pin ("B1") { - capacitance : 0.0043340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084616000, 0.0084577000, 0.0084486000, 0.0084510000, 0.0084566000, 0.0084696000, 0.0084995000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007232200, -0.007352100, -0.007628500, -0.007638600, -0.007661900, -0.007715600, -0.007839400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046350000; - } - pin ("C1") { - capacitance : 0.0043270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038748000, 0.0038702000, 0.0038598000, 0.0038784000, 0.0039214000, 0.0040203000, 0.0042485000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003557300, -0.003555000, -0.003549600, -0.003550500, -0.003552700, -0.003557700, -0.003569300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046640000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0107284000, 0.0096353000, 0.0070167000, 0.0008095000, -0.013854000, -0.048593800, -0.131421600", \ - "0.0104749000, 0.0093739000, 0.0067729000, 0.0005640000, -0.014079300, -0.048824600, -0.131639200", \ - "0.0101891000, 0.0091060000, 0.0064951000, 0.0002911000, -0.014328000, -0.049056100, -0.131897900", \ - "0.0097813000, 0.0086921000, 0.0061378000, -2.93000e-05, -0.014597700, -0.049340100, -0.132065300", \ - "0.0094955000, 0.0082847000, 0.0057065000, -0.000234100, -0.014846500, -0.049528800, -0.132300600", \ - "0.0102485000, 0.0093951000, 0.0066949000, 0.0001510000, -0.014846100, -0.049348700, -0.132240900", \ - "0.0127523000, 0.0115671000, 0.0087797000, 0.0023391000, -0.012618800, -0.048206500, -0.132041900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0202919000, 0.0215098000, 0.0242135000, 0.0305850000, 0.0453731000, 0.0800994000, 0.1622388000", \ - "0.0198500000, 0.0210157000, 0.0238316000, 0.0302507000, 0.0451686000, 0.0806188000, 0.1623266000", \ - "0.0193921000, 0.0205325000, 0.0233218000, 0.0298088000, 0.0448313000, 0.0800192000, 0.1627453000", \ - "0.0190694000, 0.0202238000, 0.0229289000, 0.0292622000, 0.0442460000, 0.0793721000, 0.1631448000", \ - "0.0188570000, 0.0199965000, 0.0226270000, 0.0289235000, 0.0438142000, 0.0790595000, 0.1613763000", \ - "0.0188232000, 0.0200047000, 0.0226348000, 0.0288957000, 0.0435335000, 0.0785060000, 0.1615026000", \ - "0.0185123000, 0.0196070000, 0.0221939000, 0.0286061000, 0.0439032000, 0.0783302000, 0.1611016000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0121086000, 0.0109931000, 0.0083725000, 0.0021722000, -0.012490000, -0.047233700, -0.130058800", \ - "0.0118737000, 0.0107762000, 0.0081439000, 0.0019517000, -0.012691300, -0.047474000, -0.130288900", \ - "0.0116135000, 0.0105122000, 0.0078991000, 0.0016945000, -0.012942100, -0.047697100, -0.130502200", \ - "0.0113432000, 0.0102415000, 0.0076682000, 0.0015013000, -0.013124100, -0.047909600, -0.130716100", \ - "0.0111170000, 0.0100268000, 0.0074368000, 0.0013233000, -0.013233300, -0.047853200, -0.130678200", \ - "0.0116058000, 0.0105244000, 0.0079442000, 0.0016486000, -0.013180500, -0.048143100, -0.130785600", \ - "0.0132662000, 0.0121148000, 0.0094205000, 0.0031427000, -0.011895700, -0.047213500, -0.130451300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0279104000, 0.0290588000, 0.0316921000, 0.0379266000, 0.0526491000, 0.0873113000, 0.1693136000", \ - "0.0276659000, 0.0287259000, 0.0313861000, 0.0376624000, 0.0524655000, 0.0871933000, 0.1693261000", \ - "0.0272529000, 0.0283845000, 0.0310480000, 0.0373735000, 0.0522510000, 0.0870304000, 0.1693312000", \ - "0.0269524000, 0.0281096000, 0.0307336000, 0.0370609000, 0.0519188000, 0.0868123000, 0.1692257000", \ - "0.0267177000, 0.0278297000, 0.0304891000, 0.0367506000, 0.0515465000, 0.0864296000, 0.1689024000", \ - "0.0267130000, 0.0278162000, 0.0304775000, 0.0367084000, 0.0513946000, 0.0862651000, 0.1685259000", \ - "0.0262803000, 0.0273335000, 0.0299354000, 0.0366025000, 0.0516016000, 0.0863689000, 0.1684201000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0078288000, 0.0067387000, 0.0041500000, -0.002009700, -0.016696200, -0.051622900, -0.134668400", \ - "0.0078341000, 0.0067517000, 0.0041768000, -0.001955700, -0.016612900, -0.051526000, -0.134549300", \ - "0.0078458000, 0.0067574000, 0.0042110000, -0.001864300, -0.016426300, -0.051293700, -0.134286700", \ - "0.0073553000, 0.0062944000, 0.0038107000, -0.002205500, -0.016688600, -0.051419000, -0.134348700", \ - "0.0075959000, 0.0064782000, 0.0039170000, -0.002188000, -0.016867800, -0.051543000, -0.134379500", \ - "0.0081438000, 0.0070415000, 0.0044469000, -0.001739400, -0.016388700, -0.051496900, -0.134435800", \ - "0.0108012000, 0.0096213000, 0.0068551000, 0.0003490000, -0.014736800, -0.050000700, -0.133587300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0223361000, 0.0234157000, 0.0261122000, 0.0324368000, 0.0473142000, 0.0821082000, 0.1641270000", \ - "0.0219484000, 0.0230961000, 0.0258237000, 0.0321738000, 0.0470809000, 0.0818973000, 0.1642944000", \ - "0.0216687000, 0.0227294000, 0.0254364000, 0.0317943000, 0.0467379000, 0.0817417000, 0.1641291000", \ - "0.0214063000, 0.0224858000, 0.0251361000, 0.0314219000, 0.0463424000, 0.0813361000, 0.1637624000", \ - "0.0210907000, 0.0222143000, 0.0248799000, 0.0311383000, 0.0459523000, 0.0808166000, 0.1633033000", \ - "0.0210704000, 0.0221753000, 0.0248307000, 0.0310538000, 0.0459259000, 0.0807907000, 0.1630231000", \ - "0.0218556000, 0.0229317000, 0.0254424000, 0.0315608000, 0.0462937000, 0.0809199000, 0.1631521000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("-0.000190200, -0.001230300, -0.003750000, -0.009875800, -0.024578700, -0.059605600, -0.142765600", \ - "-0.000486500, -0.001466300, -0.003919200, -0.009927500, -0.024517000, -0.059442500, -0.142561600", \ - "-0.000848700, -0.001840500, -0.004202300, -0.010110700, -0.024544500, -0.059357100, -0.142397700", \ - "-0.001131700, -0.002129200, -0.004626800, -0.010454900, -0.024715100, -0.059402200, -0.142346800", \ - "-0.000859300, -0.001933300, -0.004457100, -0.010434000, -0.025050900, -0.059607100, -0.142384900", \ - "-7.65000e-05, -0.001226900, -0.003871800, -0.010254400, -0.024847800, -0.059607500, -0.142591800", \ - "0.0030651000, 0.0017735000, -0.001142100, -0.007861700, -0.023117100, -0.058093200, -0.141622700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0219608000, 0.0231027000, 0.0258393000, 0.0322325000, 0.0471287000, 0.0819935000, 0.1641752000", \ - "0.0215587000, 0.0227087000, 0.0254614000, 0.0318207000, 0.0468489000, 0.0817178000, 0.1642022000", \ - "0.0211763000, 0.0223167000, 0.0249996000, 0.0313393000, 0.0463969000, 0.0814830000, 0.1638955000", \ - "0.0208298000, 0.0219697000, 0.0246650000, 0.0308195000, 0.0458163000, 0.0810142000, 0.1636564000", \ - "0.0210073000, 0.0220434000, 0.0246732000, 0.0308808000, 0.0455656000, 0.0804746000, 0.1630184000", \ - "0.0218582000, 0.0229466000, 0.0254965000, 0.0315597000, 0.0460217000, 0.0806097000, 0.1627270000", \ - "0.0246091000, 0.0256234000, 0.0280609000, 0.0339614000, 0.0481288000, 0.0819538000, 0.1623287000"); - } - } - max_capacitance : 0.0888160000; - max_transition : 1.4972550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0301879000, 0.0328299000, 0.0389262000, 0.0521889000, 0.0809793000, 0.1444991000, 0.2892254000", \ - "0.0345577000, 0.0371548000, 0.0431101000, 0.0562593000, 0.0850523000, 0.1484319000, 0.2933461000", \ - "0.0461333000, 0.0484447000, 0.0539801000, 0.0664893000, 0.0948931000, 0.1582436000, 0.3028838000", \ - "0.0677036000, 0.0704239000, 0.0773507000, 0.0917122000, 0.1194513000, 0.1814539000, 0.3260707000", \ - "0.0943783000, 0.0993366000, 0.1092574000, 0.1294460000, 0.1686564000, 0.2382227000, 0.3821202000", \ - "0.1205518000, 0.1269176000, 0.1416013000, 0.1729669000, 0.2316693000, 0.3345224000, 0.5095024000", \ - "0.1244226000, 0.1349197000, 0.1566287000, 0.2020449000, 0.2912454000, 0.4514154000, 0.7156025000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1246146000, 0.1333897000, 0.1531862000, 0.1988729000, 0.3036789000, 0.5507188000, 1.1350849000", \ - "0.1279870000, 0.1366869000, 0.1567027000, 0.2024793000, 0.3086272000, 0.5606456000, 1.1409116000", \ - "0.1391120000, 0.1476121000, 0.1674445000, 0.2137730000, 0.3207427000, 0.5702903000, 1.1559833000", \ - "0.1652519000, 0.1733318000, 0.1930251000, 0.2386403000, 0.3446786000, 0.5943521000, 1.1868077000", \ - "0.2167265000, 0.2257426000, 0.2458648000, 0.2912998000, 0.3973850000, 0.6517686000, 1.2342327000", \ - "0.2988727000, 0.3108302000, 0.3355939000, 0.3904722000, 0.5073416000, 0.7575333000, 1.3487044000", \ - "0.4254714000, 0.4422487000, 0.4788450000, 0.5543555000, 0.7027522000, 0.9949694000, 1.5934537000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0346289000, 0.0373951000, 0.0441634000, 0.0595200000, 0.0943732000, 0.1758186000, 0.3694197000", \ - "0.0330569000, 0.0362540000, 0.0432324000, 0.0588961000, 0.0941584000, 0.1758008000, 0.3691255000", \ - "0.0340132000, 0.0365221000, 0.0427085000, 0.0576345000, 0.0934289000, 0.1755352000, 0.3692711000", \ - "0.0454342000, 0.0480798000, 0.0540650000, 0.0657274000, 0.0961013000, 0.1747939000, 0.3687111000", \ - "0.0681175000, 0.0716086000, 0.0793699000, 0.0956368000, 0.1272254000, 0.1907636000, 0.3704254000", \ - "0.1086283000, 0.1141485000, 0.1257253000, 0.1481509000, 0.1910849000, 0.2712778000, 0.4194665000", \ - "0.1800415000, 0.1900569000, 0.2090016000, 0.2457036000, 0.3062064000, 0.4165001000, 0.6050354000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0789782000, 0.0896707000, 0.1149972000, 0.1750773000, 0.3163406000, 0.6513911000, 1.4402181000", \ - "0.0791375000, 0.0902635000, 0.1151943000, 0.1741919000, 0.3167638000, 0.6556927000, 1.4431008000", \ - "0.0792659000, 0.0903443000, 0.1153411000, 0.1752533000, 0.3165962000, 0.6519967000, 1.4448989000", \ - "0.0796511000, 0.0902023000, 0.1155756000, 0.1750686000, 0.3164547000, 0.6500851000, 1.4541134000", \ - "0.0880836000, 0.0979197000, 0.1208700000, 0.1781585000, 0.3166877000, 0.6551589000, 1.4391560000", \ - "0.1151747000, 0.1254109000, 0.1504659000, 0.2077829000, 0.3363755000, 0.6563284000, 1.4452530000", \ - "0.1823533000, 0.1940377000, 0.2198696000, 0.2809113000, 0.4180017000, 0.7192792000, 1.4645647000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0363316000, 0.0389799000, 0.0449058000, 0.0580584000, 0.0868387000, 0.1502285000, 0.2949237000", \ - "0.0408859000, 0.0434943000, 0.0493681000, 0.0625273000, 0.0911448000, 0.1546461000, 0.2991795000", \ - "0.0508177000, 0.0532942000, 0.0589988000, 0.0719277000, 0.1004710000, 0.1638164000, 0.3086257000", \ - "0.0700249000, 0.0729254000, 0.0793927000, 0.0932816000, 0.1217631000, 0.1850593000, 0.3297718000", \ - "0.0984902000, 0.1023768000, 0.1113332000, 0.1295277000, 0.1646681000, 0.2333624000, 0.3792275000", \ - "0.1291238000, 0.1351810000, 0.1481781000, 0.1744501000, 0.2268186000, 0.3199290000, 0.4894023000", \ - "0.1405471000, 0.1497084000, 0.1698637000, 0.2111947000, 0.2932344000, 0.4361803000, 0.6747077000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1605514000, 0.1683552000, 0.1879737000, 0.2325614000, 0.3377382000, 0.5852272000, 1.1709810000", \ - "0.1644064000, 0.1727684000, 0.1918358000, 0.2372854000, 0.3427209000, 0.5903611000, 1.1754397000", \ - "0.1756179000, 0.1842089000, 0.2036126000, 0.2491794000, 0.3549757000, 0.6031700000, 1.1893776000", \ - "0.2018622000, 0.2102929000, 0.2296311000, 0.2749813000, 0.3808490000, 0.6296717000, 1.2156410000", \ - "0.2558787000, 0.2639317000, 0.2831745000, 0.3283811000, 0.4339745000, 0.6828069000, 1.2691991000", \ - "0.3477607000, 0.3573110000, 0.3808733000, 0.4321505000, 0.5454848000, 0.7941783000, 1.3807078000", \ - "0.4968835000, 0.5107127000, 0.5425550000, 0.6087892000, 0.7487622000, 1.0340374000, 1.6307300000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0335088000, 0.0364159000, 0.0432354000, 0.0587528000, 0.0941101000, 0.1757656000, 0.3689005000", \ - "0.0330958000, 0.0360376000, 0.0428089000, 0.0585234000, 0.0937635000, 0.1756345000, 0.3692525000", \ - "0.0333718000, 0.0361838000, 0.0426528000, 0.0579093000, 0.0934299000, 0.1754233000, 0.3691354000", \ - "0.0411494000, 0.0435605000, 0.0494736000, 0.0622089000, 0.0947252000, 0.1752853000, 0.3696168000", \ - "0.0601416000, 0.0630816000, 0.0690840000, 0.0832255000, 0.1138378000, 0.1846420000, 0.3690353000", \ - "0.0963497000, 0.1004736000, 0.1094430000, 0.1274301000, 0.1660593000, 0.2370717000, 0.4009944000", \ - "0.1633380000, 0.1693123000, 0.1825913000, 0.2084271000, 0.2610958000, 0.3545650000, 0.5344286000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1073853000, 0.1183288000, 0.1439461000, 0.2039414000, 0.3454523000, 0.6798082000, 1.4730384000", \ - "0.1074318000, 0.1181879000, 0.1438780000, 0.2038283000, 0.3454457000, 0.6797248000, 1.4686923000", \ - "0.1075351000, 0.1187890000, 0.1437266000, 0.2044076000, 0.3455084000, 0.6798881000, 1.4713983000", \ - "0.1078972000, 0.1183776000, 0.1437323000, 0.2038814000, 0.3456006000, 0.6798331000, 1.4717222000", \ - "0.1124569000, 0.1226865000, 0.1470330000, 0.2050609000, 0.3455776000, 0.6823370000, 1.4734336000", \ - "0.1389581000, 0.1493308000, 0.1748285000, 0.2314140000, 0.3619350000, 0.6835447000, 1.4708518000", \ - "0.2026977000, 0.2140663000, 0.2407539000, 0.3021998000, 0.4389221000, 0.7437349000, 1.4878120000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0197362000, 0.0211456000, 0.0243290000, 0.0315237000, 0.0476598000, 0.0841345000, 0.1694411000", \ - "0.0246562000, 0.0260208000, 0.0291919000, 0.0363470000, 0.0523088000, 0.0887916000, 0.1741247000", \ - "0.0352857000, 0.0369357000, 0.0405133000, 0.0477118000, 0.0634911000, 0.0998903000, 0.1852022000", \ - "0.0493241000, 0.0518521000, 0.0575097000, 0.0684109000, 0.0888682000, 0.1260263000, 0.2108934000", \ - "0.0641405000, 0.0676305000, 0.0761292000, 0.0935254000, 0.1255508000, 0.1803986000, 0.2714632000", \ - "0.0706166000, 0.0767415000, 0.0900126000, 0.1168001000, 0.1675956000, 0.2535660000, 0.3919563000", \ - "0.0450560000, 0.0545292000, 0.0753867000, 0.1173980000, 0.1968991000, 0.3328200000, 0.5505099000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1424451000, 0.1509101000, 0.1700842000, 0.2158225000, 0.3217214000, 0.5697867000, 1.1556397000", \ - "0.1454671000, 0.1536169000, 0.1734495000, 0.2188919000, 0.3253112000, 0.5738706000, 1.1595161000", \ - "0.1555474000, 0.1638500000, 0.1834858000, 0.2288894000, 0.3355466000, 0.5849130000, 1.1710383000", \ - "0.1814373000, 0.1894552000, 0.2090295000, 0.2543170000, 0.3604015000, 0.6099302000, 1.1969752000", \ - "0.2381411000, 0.2467925000, 0.2664382000, 0.3115573000, 0.4173004000, 0.6661638000, 1.2533062000", \ - "0.3371866000, 0.3486908000, 0.3746271000, 0.4316323000, 0.5509596000, 0.8002221000, 1.3867526000", \ - "0.4986546000, 0.5162779000, 0.5552009000, 0.6369413000, 0.7962575000, 1.1014402000, 1.6992887000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0202182000, 0.0217786000, 0.0254814000, 0.0342278000, 0.0544487000, 0.1019240000, 0.2163734000", \ - "0.0198495000, 0.0213724000, 0.0250194000, 0.0339803000, 0.0543721000, 0.1019184000, 0.2151944000", \ - "0.0243291000, 0.0254353000, 0.0283620000, 0.0357822000, 0.0545890000, 0.1019074000, 0.2155380000", \ - "0.0392033000, 0.0404889000, 0.0436229000, 0.0505780000, 0.0652417000, 0.1053146000, 0.2149310000", \ - "0.0653599000, 0.0674282000, 0.0719533000, 0.0815755000, 0.1010151000, 0.1373354000, 0.2285664000", \ - "0.1111240000, 0.1143304000, 0.1214343000, 0.1365004000, 0.1657280000, 0.2177495000, 0.3070950000", \ - "0.1931389000, 0.1980005000, 0.2096668000, 0.2332471000, 0.2774163000, 0.3565195000, 0.4876625000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1075345000, 0.1180867000, 0.1438974000, 0.2038886000, 0.3455423000, 0.6794205000, 1.4740584000", \ - "0.1073673000, 0.1181094000, 0.1439232000, 0.2039358000, 0.3454733000, 0.6797867000, 1.4716612000", \ - "0.1073982000, 0.1181831000, 0.1439491000, 0.2039535000, 0.3454061000, 0.6797048000, 1.4695486000", \ - "0.1076892000, 0.1184125000, 0.1439171000, 0.2041012000, 0.3455488000, 0.6798584000, 1.4683643000", \ - "0.1184197000, 0.1281140000, 0.1519639000, 0.2083186000, 0.3463259000, 0.6798225000, 1.4698263000", \ - "0.1606597000, 0.1713187000, 0.1955299000, 0.2497862000, 0.3717155000, 0.6844276000, 1.4706575000", \ - "0.2509506000, 0.2634059000, 0.2927632000, 0.3583743000, 0.4867486000, 0.7695150000, 1.4903760000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0154336000, 0.0166712000, 0.0194894000, 0.0259412000, 0.0407447000, 0.0756272000, 0.1581565000", \ - "0.0200970000, 0.0213592000, 0.0241432000, 0.0306343000, 0.0456037000, 0.0806285000, 0.1630677000", \ - "0.0274157000, 0.0293843000, 0.0336127000, 0.0417720000, 0.0569821000, 0.0917263000, 0.1743373000", \ - "0.0353106000, 0.0385356000, 0.0452303000, 0.0582479000, 0.0804848000, 0.1182460000, 0.2004034000", \ - "0.0399183000, 0.0450894000, 0.0557435000, 0.0768119000, 0.1123445000, 0.1700210000, 0.2614725000", \ - "0.0303154000, 0.0383853000, 0.0553217000, 0.0883480000, 0.1452210000, 0.2365184000, 0.3777024000", \ - "-0.022792900, -0.009354400, 0.0179415000, 0.0707219000, 0.1599350000, 0.3040990000, 0.5270949000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0957186000, 0.1041735000, 0.1240733000, 0.1700525000, 0.2764623000, 0.5249370000, 1.1100012000", \ - "0.0978343000, 0.1064380000, 0.1263848000, 0.1720933000, 0.2791169000, 0.5281318000, 1.1145557000", \ - "0.1067741000, 0.1149320000, 0.1342621000, 0.1802073000, 0.2872132000, 0.5372038000, 1.1240465000", \ - "0.1320467000, 0.1401478000, 0.1594247000, 0.2033463000, 0.3102650000, 0.5603155000, 1.1478893000", \ - "0.1957236000, 0.2041460000, 0.2232871000, 0.2667253000, 0.3703081000, 0.6200483000, 1.2069815000", \ - "0.2987025000, 0.3116384000, 0.3404091000, 0.4009914000, 0.5180175000, 0.7632714000, 1.3474573000", \ - "0.4684696000, 0.4866982000, 0.5272104000, 0.6158228000, 0.7875947000, 1.0977433000, 1.6749270000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0114869000, 0.0131120000, 0.0172046000, 0.0263436000, 0.0466619000, 0.0927224000, 0.2021957000", \ - "0.0123745000, 0.0138570000, 0.0175751000, 0.0263664000, 0.0465864000, 0.0927239000, 0.2025615000", \ - "0.0203329000, 0.0213375000, 0.0237024000, 0.0301849000, 0.0477204000, 0.0927416000, 0.2020349000", \ - "0.0360302000, 0.0373791000, 0.0402571000, 0.0470197000, 0.0609088000, 0.0977869000, 0.2019648000", \ - "0.0629686000, 0.0647288000, 0.0690573000, 0.0783543000, 0.0973184000, 0.1324116000, 0.2165934000", \ - "0.1113236000, 0.1140030000, 0.1201381000, 0.1335854000, 0.1615877000, 0.2123599000, 0.3002915000", \ - "0.2006424000, 0.2047864000, 0.2137481000, 0.2340678000, 0.2759943000, 0.3535104000, 0.4815116000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1063855000, 0.1176593000, 0.1431614000, 0.2038075000, 0.3455304000, 0.6800794000, 1.4686881000", \ - "0.1059640000, 0.1174757000, 0.1431771000, 0.2042129000, 0.3455497000, 0.6798077000, 1.4740512000", \ - "0.1048167000, 0.1161397000, 0.1424678000, 0.2034249000, 0.3454927000, 0.6813987000, 1.4692202000", \ - "0.1031559000, 0.1139452000, 0.1397613000, 0.2021292000, 0.3452819000, 0.6823347000, 1.4737896000", \ - "0.1243311000, 0.1336571000, 0.1555361000, 0.2089835000, 0.3451614000, 0.6801270000, 1.4701425000", \ - "0.1700186000, 0.1826631000, 0.2102648000, 0.2685754000, 0.3856384000, 0.6856528000, 1.4712490000", \ - "0.2496665000, 0.2673830000, 0.3051681000, 0.3830763000, 0.5301523000, 0.8032505000, 1.4972549000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a211oi_4") { - leakage_power () { - value : 0.0020907000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0046760000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0018881000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0020063000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0020907000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0068997000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0018881000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0020063000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0020907000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0060819000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0018881000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0020063000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0004918000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0032064000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 9.3357871e-05; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0007064000; - when : "A1&A2&B1&!C1"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__a211oi"; - cell_leakage_power : 0.0025069380; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0084810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0175481000, 0.0175479000, 0.0175476000, 0.0175420000, 0.0175293000, 0.0174999000, 0.0174320000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013220800, -0.013244900, -0.013300300, -0.013272600, -0.013208700, -0.013061500, -0.012722100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088430000; - } - pin ("A2") { - capacitance : 0.0091250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162183000, 0.0161981000, 0.0161514000, 0.0161459000, 0.0161332000, 0.0161041000, 0.0160368000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016108200, -0.016105100, -0.016098100, -0.016100600, -0.016106200, -0.016119100, -0.016148900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0095820000; - } - pin ("B1") { - capacitance : 0.0091130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0084920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0167266000, 0.0167304000, 0.0167391000, 0.0167465000, 0.0167638000, 0.0168035000, 0.0168950000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013992100, -0.014317000, -0.015066100, -0.015096600, -0.015166700, -0.015328500, -0.015701300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0097350000; - } - pin ("C1") { - capacitance : 0.0085760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089947000, 0.0089810000, 0.0089494000, 0.0089776000, 0.0090426000, 0.0091925000, 0.0095379000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007051100, -0.007053900, -0.007060500, -0.007059800, -0.007058200, -0.007054400, -0.007045700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092480000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0221156000, 0.0208468000, 0.0176278000, 0.0093325000, -0.011863700, -0.065983000, -0.205359100", \ - "0.0217268000, 0.0204705000, 0.0172360000, 0.0089517000, -0.012252000, -0.066349100, -0.205826800", \ - "0.0212021000, 0.0199401000, 0.0167418000, 0.0084433000, -0.012709400, -0.066787500, -0.206262600", \ - "0.0203392000, 0.0191198000, 0.0159198000, 0.0078846000, -0.013254700, -0.067317700, -0.206732300", \ - "0.0197261000, 0.0184789000, 0.0153051000, 0.0072742000, -0.013809900, -0.067702000, -0.207109400", \ - "0.0211297000, 0.0198658000, 0.0160973000, 0.0077394000, -0.013622500, -0.067728800, -0.207188500", \ - "0.0245280000, 0.0232065000, 0.0197998000, 0.0111881000, -0.010441300, -0.065719300, -0.206648100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0394850000, 0.0408585000, 0.0441602000, 0.0526879000, 0.0739746000, 0.1289948000, 0.2671932000", \ - "0.0385991000, 0.0399060000, 0.0433940000, 0.0520758000, 0.0737182000, 0.1281658000, 0.2670183000", \ - "0.0376642000, 0.0390297000, 0.0424412000, 0.0511073000, 0.0730443000, 0.1275838000, 0.2664346000", \ - "0.0371633000, 0.0384923000, 0.0417716000, 0.0502876000, 0.0721269000, 0.1269194000, 0.2664840000", \ - "0.0367219000, 0.0380032000, 0.0412930000, 0.0496795000, 0.0710664000, 0.1256876000, 0.2648738000", \ - "0.0368373000, 0.0380849000, 0.0413811000, 0.0496279000, 0.0708085000, 0.1254205000, 0.2642741000", \ - "0.0359036000, 0.0371094000, 0.0405792000, 0.0497000000, 0.0711540000, 0.1251130000, 0.2640029000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0246988000, 0.0234473000, 0.0202332000, 0.0119253000, -0.009287800, -0.063383400, -0.202831400", \ - "0.0242574000, 0.0230048000, 0.0197667000, 0.0114633000, -0.009731700, -0.063831800, -0.203238200", \ - "0.0236619000, 0.0224235000, 0.0191703000, 0.0108869000, -0.010298700, -0.064391600, -0.203798400", \ - "0.0230004000, 0.0217748000, 0.0185921000, 0.0104387000, -0.010752500, -0.064896700, -0.204285500", \ - "0.0224409000, 0.0211900000, 0.0180459000, 0.0099092000, -0.011042400, -0.065040000, -0.204370000", \ - "0.0229407000, 0.0216701000, 0.0184394000, 0.0102636000, -0.011051900, -0.065639000, -0.204750000", \ - "0.0259901000, 0.0246867000, 0.0214038000, 0.0128091000, -0.008845200, -0.063762400, -0.204518400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0532440000, 0.0544720000, 0.0577266000, 0.0660301000, 0.0871699000, 0.1413075000, 0.2797061000", \ - "0.0526046000, 0.0538823000, 0.0571748000, 0.0655255000, 0.0868501000, 0.1411183000, 0.2794157000", \ - "0.0520476000, 0.0532833000, 0.0565909000, 0.0650645000, 0.0864260000, 0.1408371000, 0.2794185000", \ - "0.0515176000, 0.0528237000, 0.0560673000, 0.0644684000, 0.0859118000, 0.1403833000, 0.2792153000", \ - "0.0510427000, 0.0523060000, 0.0555702000, 0.0639392000, 0.0852876000, 0.1397616000, 0.2785661000", \ - "0.0511034000, 0.0523810000, 0.0555909000, 0.0638242000, 0.0851234000, 0.1394521000, 0.2782262000", \ - "0.0500127000, 0.0512533000, 0.0549071000, 0.0639114000, 0.0854494000, 0.1396124000, 0.2778673000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0141680000, 0.0129206000, 0.0097168000, 0.0014980000, -0.019664500, -0.074124300, -0.214070000", \ - "0.0142693000, 0.0130319000, 0.0098558000, 0.0016853000, -0.019428900, -0.073849600, -0.213793400", \ - "0.0144943000, 0.0132838000, 0.0101645000, 0.0021199000, -0.018890200, -0.073175500, -0.213062200", \ - "0.0136515000, 0.0124432000, 0.0093393000, 0.0013957000, -0.019338500, -0.073422700, -0.213167700", \ - "0.0137852000, 0.0125618000, 0.0093852000, 0.0013122000, -0.019623100, -0.073667400, -0.213160600", \ - "0.0148033000, 0.0135597000, 0.0103079000, 0.0020957000, -0.018912600, -0.073143700, -0.213237600", \ - "0.0192328000, 0.0178974000, 0.0145460000, 0.0058049000, -0.015951000, -0.070223900, -0.211602700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0433691000, 0.0447289000, 0.0481205000, 0.0566108000, 0.0780046000, 0.1323463000, 0.2708757000", \ - "0.0425511000, 0.0439098000, 0.0472925000, 0.0558846000, 0.0775006000, 0.1319729000, 0.2707422000", \ - "0.0417434000, 0.0430822000, 0.0464314000, 0.0549452000, 0.0766209000, 0.1314450000, 0.2704249000", \ - "0.0411625000, 0.0424654000, 0.0458194000, 0.0541808000, 0.0757978000, 0.1305802000, 0.2697611000", \ - "0.0406302000, 0.0419516000, 0.0452135000, 0.0536193000, 0.0749881000, 0.1295522000, 0.2687124000", \ - "0.0406754000, 0.0419357000, 0.0451812000, 0.0534867000, 0.0749747000, 0.1292553000, 0.2679652000", \ - "0.0420192000, 0.0432514000, 0.0463857000, 0.0544831000, 0.0756537000, 0.1297580000, 0.2685350000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0010383000, -0.000144500, -0.003265400, -0.011428700, -0.032655100, -0.087251600, -0.227414300", \ - "0.0005817000, -0.000578900, -0.003585200, -0.011568500, -0.032559200, -0.086978400, -0.227043600", \ - "-0.000110700, -0.001237900, -0.004204800, -0.012008000, -0.032626700, -0.086776000, -0.226703600", \ - "-0.000852900, -0.002008500, -0.004907500, -0.012661900, -0.033103500, -0.086887200, -0.226531100", \ - "-0.000319600, -0.001518000, -0.004583200, -0.012413300, -0.033441100, -0.087185800, -0.226587300", \ - "0.0006659000, -0.000628600, -0.003944600, -0.012176500, -0.033603500, -0.086951900, -0.226904000", \ - "0.0053528000, 0.0039913000, 0.0003857000, -0.008663900, -0.030703500, -0.085166300, -0.225718000"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0408056000, 0.0421293000, 0.0455600000, 0.0541821000, 0.0757811000, 0.1301579000, 0.2687449000", \ - "0.0398577000, 0.0412109000, 0.0446201000, 0.0533371000, 0.0750778000, 0.1297036000, 0.2685910000", \ - "0.0388820000, 0.0402945000, 0.0436449000, 0.0523519000, 0.0740222000, 0.1290034000, 0.2681436000", \ - "0.0384046000, 0.0397226000, 0.0430135000, 0.0513267000, 0.0730042000, 0.1279927000, 0.2675222000", \ - "0.0383710000, 0.0396303000, 0.0428792000, 0.0511848000, 0.0724384000, 0.1270534000, 0.2661988000", \ - "0.0403588000, 0.0415815000, 0.0447243000, 0.0528472000, 0.0742503000, 0.1276236000, 0.2658975000", \ - "0.0443113000, 0.0454780000, 0.0486216000, 0.0564144000, 0.0769813000, 0.1293815000, 0.2653688000"); - } - } - max_capacitance : 0.1419170000; - max_transition : 1.4951940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0272965000, 0.0289054000, 0.0327028000, 0.0420102000, 0.0639283000, 0.1148638000, 0.2384372000", \ - "0.0318684000, 0.0333361000, 0.0371235000, 0.0462609000, 0.0678561000, 0.1188243000, 0.2423455000", \ - "0.0434820000, 0.0448992000, 0.0482396000, 0.0567658000, 0.0778951000, 0.1286215000, 0.2518468000", \ - "0.0627523000, 0.0646993000, 0.0693996000, 0.0804571000, 0.1025260000, 0.1520563000, 0.2743207000", \ - "0.0848253000, 0.0876269000, 0.0944193000, 0.1099972000, 0.1425042000, 0.2056260000, 0.3284842000", \ - "0.1007382000, 0.1048275000, 0.1156371000, 0.1387328000, 0.1874079000, 0.2804358000, 0.4469907000", \ - "0.0822758000, 0.0884128000, 0.1034314000, 0.1382994000, 0.2122502000, 0.3554418000, 0.6093483000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1480236000, 0.1542155000, 0.1695064000, 0.2083032000, 0.3045972000, 0.5528976000, 1.1799943000", \ - "0.1505015000, 0.1565336000, 0.1727531000, 0.2120801000, 0.3095864000, 0.5566027000, 1.1886787000", \ - "0.1611980000, 0.1671785000, 0.1830993000, 0.2225450000, 0.3218102000, 0.5672635000, 1.1936885000", \ - "0.1893665000, 0.1955228000, 0.2107157000, 0.2494253000, 0.3481699000, 0.5966931000, 1.2316569000", \ - "0.2473615000, 0.2536228000, 0.2692974000, 0.3078566000, 0.4043820000, 0.6547429000, 1.2803051000", \ - "0.3465631000, 0.3539995000, 0.3732187000, 0.4182940000, 0.5243613000, 0.7716115000, 1.3995708000", \ - "0.5107976000, 0.5214859000, 0.5492525000, 0.6087132000, 0.7413538000, 1.0276199000, 1.6655854000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0342329000, 0.0360598000, 0.0405218000, 0.0518387000, 0.0794189000, 0.1473165000, 0.3212533000", \ - "0.0328442000, 0.0345920000, 0.0392897000, 0.0508775000, 0.0787478000, 0.1471445000, 0.3209864000", \ - "0.0349262000, 0.0364408000, 0.0403011000, 0.0505651000, 0.0775490000, 0.1465612000, 0.3208906000", \ - "0.0461338000, 0.0478322000, 0.0519629000, 0.0618951000, 0.0840256000, 0.1468514000, 0.3203915000", \ - "0.0686451000, 0.0707711000, 0.0757845000, 0.0883502000, 0.1139361000, 0.1714234000, 0.3242303000", \ - "0.1091191000, 0.1124203000, 0.1194186000, 0.1371215000, 0.1723642000, 0.2443380000, 0.3888750000", \ - "0.1805941000, 0.1855963000, 0.1978244000, 0.2240097000, 0.2763643000, 0.3762237000, 0.5574806000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0955339000, 0.1031859000, 0.1228858000, 0.1733910000, 0.3045253000, 0.6393112000, 1.4823204000", \ - "0.0956411000, 0.1032490000, 0.1236756000, 0.1739820000, 0.3036306000, 0.6354816000, 1.4825634000", \ - "0.0962113000, 0.1034863000, 0.1230823000, 0.1735057000, 0.3039255000, 0.6334189000, 1.4801652000", \ - "0.0959572000, 0.1036575000, 0.1232535000, 0.1735936000, 0.3036753000, 0.6353654000, 1.4841793000", \ - "0.1018002000, 0.1087071000, 0.1272964000, 0.1757599000, 0.3038399000, 0.6346198000, 1.4786555000", \ - "0.1271563000, 0.1351050000, 0.1539463000, 0.2027539000, 0.3202893000, 0.6398001000, 1.4821143000", \ - "0.1891294000, 0.1965066000, 0.2179558000, 0.2676398000, 0.3939622000, 0.6955521000, 1.4951939000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0328696000, 0.0344189000, 0.0381778000, 0.0474562000, 0.0691948000, 0.1203730000, 0.2439331000", \ - "0.0372462000, 0.0387228000, 0.0425437000, 0.0517247000, 0.0733600000, 0.1244223000, 0.2475325000", \ - "0.0466691000, 0.0481366000, 0.0517488000, 0.0606434000, 0.0820810000, 0.1328522000, 0.2559440000", \ - "0.0638202000, 0.0656176000, 0.0700202000, 0.0804781000, 0.1024110000, 0.1529628000, 0.2761225000", \ - "0.0877207000, 0.0901225000, 0.0959586000, 0.1097034000, 0.1390488000, 0.1968565000, 0.3223447000", \ - "0.1102096000, 0.1138510000, 0.1227232000, 0.1427336000, 0.1851047000, 0.2673367000, 0.4204063000", \ - "0.1062908000, 0.1116604000, 0.1248432000, 0.1555533000, 0.2219678000, 0.3482218000, 0.5705639000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1819350000, 0.1877093000, 0.2022092000, 0.2389743000, 0.3318716000, 0.5678760000, 1.1708684000", \ - "0.1855953000, 0.1913780000, 0.2058044000, 0.2431165000, 0.3363568000, 0.5726134000, 1.1757727000", \ - "0.1970715000, 0.2030403000, 0.2175634000, 0.2550198000, 0.3487331000, 0.5855898000, 1.1892015000", \ - "0.2247729000, 0.2305849000, 0.2453511000, 0.2824516000, 0.3761824000, 0.6135866000, 1.2182323000", \ - "0.2820222000, 0.2877369000, 0.3021141000, 0.3391343000, 0.4327664000, 0.6700214000, 1.2753923000", \ - "0.3834159000, 0.3904855000, 0.4076703000, 0.4493140000, 0.5492656000, 0.7865094000, 1.3913478000", \ - "0.5534269000, 0.5624146000, 0.5845266000, 0.6374737000, 0.7596614000, 1.0315550000, 1.6474837000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0339411000, 0.0357059000, 0.0402163000, 0.0515571000, 0.0792550000, 0.1473140000, 0.3209582000", \ - "0.0332168000, 0.0350506000, 0.0396148000, 0.0509134000, 0.0788268000, 0.1470855000, 0.3208709000", \ - "0.0340540000, 0.0357096000, 0.0399314000, 0.0507177000, 0.0781190000, 0.1466348000, 0.3209744000", \ - "0.0422368000, 0.0437152000, 0.0475588000, 0.0572142000, 0.0812529000, 0.1468599000, 0.3206589000", \ - "0.0609228000, 0.0626118000, 0.0669725000, 0.0771486000, 0.1019400000, 0.1609509000, 0.3229426000", \ - "0.0961121000, 0.0985442000, 0.1043987000, 0.1180425000, 0.1488710000, 0.2119113000, 0.3623811000", \ - "0.1624217000, 0.1659013000, 0.1744450000, 0.1926689000, 0.2346745000, 0.3175070000, 0.4867499000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1250177000, 0.1320005000, 0.1511113000, 0.2008050000, 0.3262010000, 0.6455128000, 1.4609965000", \ - "0.1245866000, 0.1317979000, 0.1511476000, 0.1999534000, 0.3248177000, 0.6445428000, 1.4584662000", \ - "0.1248207000, 0.1318827000, 0.1511364000, 0.2000310000, 0.3248049000, 0.6439053000, 1.4593264000", \ - "0.1251538000, 0.1323252000, 0.1511702000, 0.2001491000, 0.3249453000, 0.6436588000, 1.4639577000", \ - "0.1279325000, 0.1349348000, 0.1539214000, 0.2016120000, 0.3249633000, 0.6447001000, 1.4609185000", \ - "0.1524352000, 0.1600198000, 0.1781651000, 0.2254993000, 0.3409136000, 0.6486571000, 1.4647948000", \ - "0.2110360000, 0.2187941000, 0.2389257000, 0.2886704000, 0.4110937000, 0.7041578000, 1.4774965000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0194387000, 0.0203379000, 0.0225768000, 0.0279264000, 0.0406229000, 0.0713035000, 0.1479481000", \ - "0.0243040000, 0.0251837000, 0.0273561000, 0.0325395000, 0.0451948000, 0.0759252000, 0.1525556000", \ - "0.0345380000, 0.0355970000, 0.0381359000, 0.0439365000, 0.0561166000, 0.0867431000, 0.1633954000", \ - "0.0474847000, 0.0490367000, 0.0528290000, 0.0614232000, 0.0792333000, 0.1121355000, 0.1886053000", \ - "0.0591432000, 0.0616002000, 0.0674366000, 0.0808701000, 0.1079799000, 0.1590680000, 0.2476564000", \ - "0.0593066000, 0.0630353000, 0.0712698000, 0.0922709000, 0.1356852000, 0.2158184000, 0.3527726000", \ - "0.0145719000, 0.0205511000, 0.0356634000, 0.0682807000, 0.1367868000, 0.2632294000, 0.4784483000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1595585000, 0.1653061000, 0.1808027000, 0.2183354000, 0.3122259000, 0.5488541000, 1.1521174000", \ - "0.1617399000, 0.1672008000, 0.1828890000, 0.2207501000, 0.3152628000, 0.5528027000, 1.1571417000", \ - "0.1713321000, 0.1766261000, 0.1919867000, 0.2296593000, 0.3244838000, 0.5630200000, 1.1681678000", \ - "0.1970927000, 0.2025760000, 0.2176562000, 0.2551743000, 0.3493205000, 0.5878491000, 1.1938942000", \ - "0.2555699000, 0.2613580000, 0.2761451000, 0.3131635000, 0.4072059000, 0.6449048000, 1.2514196000", \ - "0.3626777000, 0.3702968000, 0.3891561000, 0.4348200000, 0.5416940000, 0.7800087000, 1.3853916000", \ - "0.5493393000, 0.5604394000, 0.5884079000, 0.6529760000, 0.7946984000, 1.0861295000, 1.7045961000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0201505000, 0.0210831000, 0.0235327000, 0.0297690000, 0.0455648000, 0.0859100000, 0.1895014000", \ - "0.0198254000, 0.0207079000, 0.0230500000, 0.0293138000, 0.0454158000, 0.0858546000, 0.1896012000", \ - "0.0245215000, 0.0251900000, 0.0270346000, 0.0321916000, 0.0462265000, 0.0857509000, 0.1897039000", \ - "0.0385894000, 0.0394377000, 0.0416941000, 0.0471602000, 0.0592335000, 0.0916235000, 0.1894262000", \ - "0.0636488000, 0.0649509000, 0.0681069000, 0.0757829000, 0.0928386000, 0.1269515000, 0.2067529000", \ - "0.1088823000, 0.1108746000, 0.1157272000, 0.1270893000, 0.1519790000, 0.2008152000, 0.2916320000", \ - "0.1911590000, 0.1942696000, 0.2009059000, 0.2197489000, 0.2567068000, 0.3306289000, 0.4615005000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1244626000, 0.1321199000, 0.1515155000, 0.2000648000, 0.3250306000, 0.6439430000, 1.4617300000", \ - "0.1244562000, 0.1320890000, 0.1509985000, 0.1998602000, 0.3252333000, 0.6461469000, 1.4637432000", \ - "0.1244720000, 0.1320851000, 0.1514310000, 0.2001226000, 0.3249268000, 0.6438603000, 1.4594994000", \ - "0.1245386000, 0.1322426000, 0.1514208000, 0.1999393000, 0.3249942000, 0.6439551000, 1.4604412000", \ - "0.1335451000, 0.1405111000, 0.1583751000, 0.2041855000, 0.3260326000, 0.6443044000, 1.4644188000", \ - "0.1735384000, 0.1812981000, 0.1993351000, 0.2438904000, 0.3527012000, 0.6509998000, 1.4648387000", \ - "0.2597020000, 0.2683563000, 0.2897211000, 0.3403426000, 0.4628435000, 0.7348970000, 1.4784362000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0157445000, 0.0165739000, 0.0185986000, 0.0235477000, 0.0357198000, 0.0662324000, 0.1440219000", \ - "0.0203123000, 0.0211565000, 0.0231740000, 0.0281984000, 0.0404483000, 0.0710601000, 0.1489006000", \ - "0.0273821000, 0.0287270000, 0.0318900000, 0.0384473000, 0.0513441000, 0.0820152000, 0.1598376000", \ - "0.0345061000, 0.0366217000, 0.0413690000, 0.0518291000, 0.0720572000, 0.1076828000, 0.1848953000", \ - "0.0363004000, 0.0395698000, 0.0472537000, 0.0638937000, 0.0959178000, 0.1517722000, 0.2438873000", \ - "0.0196911000, 0.0248931000, 0.0370757000, 0.0634394000, 0.1146394000, 0.2020366000, 0.3464016000", \ - "-0.050150200, -0.041715100, -0.022542600, 0.0185075000, 0.0996049000, 0.2391649000, 0.4664591000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1116869000, 0.1180317000, 0.1332469000, 0.1712595000, 0.2657234000, 0.5027728000, 1.1062494000", \ - "0.1126664000, 0.1189407000, 0.1341950000, 0.1726535000, 0.2679277000, 0.5060595000, 1.1103388000", \ - "0.1203372000, 0.1264614000, 0.1415230000, 0.1799173000, 0.2749690000, 0.5143140000, 1.1198040000", \ - "0.1460503000, 0.1519174000, 0.1663505000, 0.2033240000, 0.2979532000, 0.5372738000, 1.1438950000", \ - "0.2131526000, 0.2189709000, 0.2331277000, 0.2682994000, 0.3608973000, 0.5982957000, 1.2050917000", \ - "0.3321398000, 0.3406724000, 0.3614303000, 0.4092768000, 0.5134939000, 0.7441973000, 1.3457138000", \ - "0.5295790000, 0.5413948000, 0.5713981000, 0.6416946000, 0.7954170000, 1.0929305000, 1.6904041000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0120926000, 0.0132403000, 0.0161787000, 0.0233781000, 0.0403887000, 0.0820104000, 0.1881351000", \ - "0.0130510000, 0.0140347000, 0.0166228000, 0.0234475000, 0.0403628000, 0.0821452000, 0.1881592000", \ - "0.0207558000, 0.0215112000, 0.0234460000, 0.0281465000, 0.0423897000, 0.0821536000, 0.1881041000", \ - "0.0356843000, 0.0365808000, 0.0388532000, 0.0445828000, 0.0573207000, 0.0893170000, 0.1881775000", \ - "0.0623071000, 0.0635297000, 0.0666760000, 0.0745288000, 0.0915437000, 0.1260985000, 0.2066882000", \ - "0.1104391000, 0.1121395000, 0.1166255000, 0.1276982000, 0.1518485000, 0.2018140000, 0.2928830000", \ - "0.1986204000, 0.2016845000, 0.2083596000, 0.2249585000, 0.2602841000, 0.3346141000, 0.4640550000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.1235173000, 0.1310827000, 0.1509225000, 0.1998302000, 0.3248735000, 0.6438162000, 1.4635196000", \ - "0.1232601000, 0.1310464000, 0.1500747000, 0.1997159000, 0.3247428000, 0.6460481000, 1.4643132000", \ - "0.1223085000, 0.1298381000, 0.1499219000, 0.2000642000, 0.3249802000, 0.6457772000, 1.4613371000", \ - "0.1193835000, 0.1275774000, 0.1467551000, 0.1978687000, 0.3245980000, 0.6462895000, 1.4620882000", \ - "0.1364788000, 0.1428331000, 0.1595662000, 0.2038605000, 0.3243976000, 0.6443894000, 1.4642412000", \ - "0.1849791000, 0.1931733000, 0.2134184000, 0.2612375000, 0.3623867000, 0.6506164000, 1.4639172000", \ - "0.2667235000, 0.2781467000, 0.3055392000, 0.3688289000, 0.5012452000, 0.7655107000, 1.4857141000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21bo_1") { - leakage_power () { - value : 0.0133250000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0036261000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0137870000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0036261000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0136789000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0036261000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0054535000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0010178000; - when : "A1&A2&!B1_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a21bo"; - cell_leakage_power : 0.0072675400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041136000, 0.0041125000, 0.0041100000, 0.0041109000, 0.0041130000, 0.0041178000, 0.0041290000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004121400, -0.004119200, -0.004114100, -0.004112900, -0.004110300, -0.004104200, -0.004090200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025280000; - } - pin ("A2") { - capacitance : 0.0024440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040518000, 0.0040518000, 0.0040517000, 0.0040531000, 0.0040563000, 0.0040638000, 0.0040811000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004040100, -0.004039400, -0.004037800, -0.004038400, -0.004039900, -0.004043300, -0.004051300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025700000; - } - pin ("B1_N") { - capacitance : 0.0017330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091397000, 0.0090288000, 0.0087731000, 0.0088407000, 0.0089965000, 0.0093555000, 0.0101831000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017744000, 0.0016985000, 0.0015235000, 0.0015913000, 0.0017477000, 0.0021082000, 0.0029391000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018080000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0112903000, 0.0103609000, 0.0077484000, -0.000811900, -0.026220800, -0.095548300, -0.281278500", \ - "0.0110519000, 0.0101363000, 0.0074985000, -0.001045600, -0.026448000, -0.095801200, -0.281518600", \ - "0.0107867000, 0.0098710000, 0.0072392000, -0.001335500, -0.026717100, -0.096088400, -0.281796100", \ - "0.0105674000, 0.0096476000, 0.0070234000, -0.001557800, -0.026966800, -0.096270600, -0.281978700", \ - "0.0103975000, 0.0094274000, 0.0067863000, -0.001817000, -0.027196400, -0.096460300, -0.282132100", \ - "0.0119405000, 0.0105964000, 0.0070154000, -0.002448300, -0.027300300, -0.096503100, -0.282194700", \ - "0.0131878000, 0.0117595000, 0.0080819000, -0.001564900, -0.027371100, -0.096216400, -0.281820000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0133207000, 0.0147770000, 0.0185467000, 0.0283111000, 0.0541058000, 0.1227101000, 0.3061630000", \ - "0.0131863000, 0.0146419000, 0.0184172000, 0.0281957000, 0.0539695000, 0.1225263000, 0.3059488000", \ - "0.0129863000, 0.0144364000, 0.0182060000, 0.0279872000, 0.0537924000, 0.1224837000, 0.3060387000", \ - "0.0127391000, 0.0141790000, 0.0179383000, 0.0277101000, 0.0534988000, 0.1222222000, 0.3057694000", \ - "0.0128717000, 0.0142061000, 0.0178079000, 0.0274760000, 0.0531461000, 0.1220382000, 0.3056589000", \ - "0.0134005000, 0.0147748000, 0.0184156000, 0.0279254000, 0.0538270000, 0.1220316000, 0.3065680000", \ - "0.0149740000, 0.0163511000, 0.0198855000, 0.0295085000, 0.0549563000, 0.1239321000, 0.3064509000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0138000000, 0.0128794000, 0.0102586000, 0.0017712000, -0.023521700, -0.092753000, -0.278401200", \ - "0.0136921000, 0.0127466000, 0.0101110000, 0.0016223000, -0.023672600, -0.092899900, -0.278539200", \ - "0.0135051000, 0.0125488000, 0.0099056000, 0.0014195000, -0.023856500, -0.093080300, -0.278716600", \ - "0.0133452000, 0.0123758000, 0.0097247000, 0.0012220000, -0.024040400, -0.093247900, -0.278914000", \ - "0.0131628000, 0.0121989000, 0.0095483000, 0.0010497000, -0.024233900, -0.093413600, -0.279058700", \ - "0.0147312000, 0.0133765000, 0.0097875000, 0.0005380000, -0.024381900, -0.093489900, -0.279081200", \ - "0.0163311000, 0.0149491000, 0.0112614000, 0.0015936000, -0.024178500, -0.093067900, -0.278563400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0131344000, 0.0145674000, 0.0183283000, 0.0280564000, 0.0537574000, 0.1223718000, 0.3058435000", \ - "0.0130077000, 0.0144416000, 0.0182022000, 0.0279362000, 0.0535994000, 0.1227422000, 0.3065449000", \ - "0.0128111000, 0.0142680000, 0.0180219000, 0.0277590000, 0.0535171000, 0.1221005000, 0.3055940000", \ - "0.0126228000, 0.0140536000, 0.0177636000, 0.0275004000, 0.0535397000, 0.1224171000, 0.3066577000", \ - "0.0126307000, 0.0139679000, 0.0175914000, 0.0273463000, 0.0531165000, 0.1218512000, 0.3054115000", \ - "0.0128652000, 0.0142208000, 0.0178855000, 0.0275410000, 0.0533784000, 0.1216234000, 0.3066507000", \ - "0.0142197000, 0.0156052000, 0.0191980000, 0.0288613000, 0.0546595000, 0.1234404000, 0.3069442000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0127924000, 0.0118414000, 0.0091961000, 0.0007010000, -0.024575300, -0.093765700, -0.279401200", \ - "0.0127295000, 0.0117893000, 0.0091584000, 0.0006757000, -0.024608500, -0.093848700, -0.279455500", \ - "0.0127444000, 0.0117710000, 0.0091207000, 0.0006361000, -0.024628900, -0.093826500, -0.279468500", \ - "0.0124144000, 0.0114910000, 0.0088435000, 0.0003389000, -0.024924900, -0.094134900, -0.279749800", \ - "0.0120677000, 0.0111481000, 0.0084867000, 1.180000e-05, -0.025269200, -0.094457100, -0.280094100", \ - "0.0144815000, 0.0131955000, 0.0097112000, 0.0002378000, -0.025363000, -0.094543300, -0.280187900", \ - "0.0148609000, 0.0135917000, 0.0099743000, 0.0005930000, -0.025114700, -0.094419300, -0.280059100"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0111483000, 0.0126855000, 0.0165657000, 0.0264281000, 0.0523948000, 0.1209784000, 0.3048933000", \ - "0.0110597000, 0.0126156000, 0.0164888000, 0.0263554000, 0.0521296000, 0.1209401000, 0.3064828000", \ - "0.0111130000, 0.0126940000, 0.0165447000, 0.0264024000, 0.0524327000, 0.1216300000, 0.3064972000", \ - "0.0108384000, 0.0123875000, 0.0162581000, 0.0261263000, 0.0518365000, 0.1207249000, 0.3059700000", \ - "0.0104690000, 0.0120147000, 0.0158746000, 0.0257333000, 0.0515155000, 0.1203362000, 0.3034417000", \ - "0.0106377000, 0.0120530000, 0.0157214000, 0.0257969000, 0.0515657000, 0.1202691000, 0.3051553000", \ - "0.0106018000, 0.0120348000, 0.0157246000, 0.0255474000, 0.0512902000, 0.1205036000, 0.3049245000"); - } - } - max_capacitance : 0.1831150000; - max_transition : 1.5086480000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1322761000, 0.1388518000, 0.1529419000, 0.1810452000, 0.2395658000, 0.3771787000, 0.7376869000", \ - "0.1366490000, 0.1432705000, 0.1571785000, 0.1853777000, 0.2438289000, 0.3814679000, 0.7422641000", \ - "0.1482828000, 0.1549356000, 0.1691031000, 0.1971578000, 0.2557015000, 0.3933020000, 0.7541591000", \ - "0.1762953000, 0.1828483000, 0.1968730000, 0.2249592000, 0.2834578000, 0.4209273000, 0.7815761000", \ - "0.2350780000, 0.2418786000, 0.2561843000, 0.2848146000, 0.3434542000, 0.4811374000, 0.8411882000", \ - "0.3366321000, 0.3445839000, 0.3611289000, 0.3933130000, 0.4557254000, 0.5960202000, 0.9563347000", \ - "0.5004308000, 0.5104679000, 0.5313362000, 0.5705061000, 0.6421517000, 0.7883733000, 1.1503168000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0689489000, 0.0752643000, 0.0899549000, 0.1250477000, 0.2162975000, 0.4588205000, 1.1070140000", \ - "0.0729583000, 0.0792778000, 0.0939743000, 0.1291249000, 0.2203681000, 0.4625369000, 1.1101932000", \ - "0.0828238000, 0.0891405000, 0.1038215000, 0.1390158000, 0.2306312000, 0.4730806000, 1.1212506000", \ - "0.1049721000, 0.1114090000, 0.1260883000, 0.1615481000, 0.2527906000, 0.4949732000, 1.1420962000", \ - "0.1359260000, 0.1426998000, 0.1580251000, 0.1934964000, 0.2852193000, 0.5276920000, 1.1747244000", \ - "0.1675489000, 0.1759173000, 0.1927618000, 0.2284794000, 0.3200412000, 0.5631328000, 1.2140259000", \ - "0.1775831000, 0.1884975000, 0.2100965000, 0.2503484000, 0.3408139000, 0.5841934000, 1.2318621000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0218016000, 0.0264944000, 0.0375578000, 0.0626871000, 0.1249402000, 0.2984875000, 0.7721503000", \ - "0.0216524000, 0.0262949000, 0.0374144000, 0.0629547000, 0.1248662000, 0.2959935000, 0.7761352000", \ - "0.0217252000, 0.0264328000, 0.0374904000, 0.0627345000, 0.1250405000, 0.2960582000, 0.7762948000", \ - "0.0219012000, 0.0267811000, 0.0374604000, 0.0626300000, 0.1252401000, 0.2968880000, 0.7714178000", \ - "0.0235076000, 0.0281525000, 0.0390669000, 0.0638266000, 0.1255474000, 0.2971501000, 0.7709084000", \ - "0.0293156000, 0.0347950000, 0.0459493000, 0.0713732000, 0.1327359000, 0.2991969000, 0.7787394000", \ - "0.0406483000, 0.0471058000, 0.0608020000, 0.0881408000, 0.1488970000, 0.3074988000, 0.7723754000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0202189000, 0.0265896000, 0.0436277000, 0.0906574000, 0.2204567000, 0.5688199000, 1.5009566000", \ - "0.0202123000, 0.0265800000, 0.0436193000, 0.0906857000, 0.2204179000, 0.5680499000, 1.4986581000", \ - "0.0201529000, 0.0265434000, 0.0435970000, 0.0905778000, 0.2201380000, 0.5691541000, 1.5017377000", \ - "0.0208899000, 0.0271455000, 0.0439019000, 0.0907727000, 0.2201623000, 0.5676500000, 1.4970639000", \ - "0.0236253000, 0.0297518000, 0.0459407000, 0.0921390000, 0.2205123000, 0.5672600000, 1.4978997000", \ - "0.0303558000, 0.0361894000, 0.0509518000, 0.0941865000, 0.2214348000, 0.5674867000, 1.5022594000", \ - "0.0416782000, 0.0486460000, 0.0631206000, 0.1015886000, 0.2227666000, 0.5705518000, 1.4986746000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1534382000, 0.1603075000, 0.1748735000, 0.2035973000, 0.2630917000, 0.4015220000, 0.7631161000", \ - "0.1581609000, 0.1650536000, 0.1795530000, 0.2083386000, 0.2678294000, 0.4062632000, 0.7674331000", \ - "0.1703849000, 0.1771941000, 0.1917460000, 0.2203549000, 0.2799559000, 0.4183724000, 0.7799006000", \ - "0.1968277000, 0.2036854000, 0.2181886000, 0.2470006000, 0.3065232000, 0.4447517000, 0.8053408000", \ - "0.2531540000, 0.2600805000, 0.2744203000, 0.3034422000, 0.3630511000, 0.5015359000, 0.8619218000", \ - "0.3531485000, 0.3610750000, 0.3776203000, 0.4096067000, 0.4724532000, 0.6132104000, 0.9741049000", \ - "0.5180847000, 0.5279516000, 0.5480677000, 0.5858948000, 0.6559395000, 0.8013825000, 1.1640465000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0732539000, 0.0795920000, 0.0942100000, 0.1291941000, 0.2200983000, 0.4625559000, 1.1106077000", \ - "0.0774092000, 0.0837197000, 0.0983293000, 0.1334073000, 0.2246776000, 0.4674258000, 1.1164225000", \ - "0.0864266000, 0.0927460000, 0.1073422000, 0.1424012000, 0.2334360000, 0.4759104000, 1.1239724000", \ - "0.1058450000, 0.1121833000, 0.1269069000, 0.1621207000, 0.2533941000, 0.4967584000, 1.1463145000", \ - "0.1366176000, 0.1435578000, 0.1589570000, 0.1945931000, 0.2860629000, 0.5288670000, 1.1770078000", \ - "0.1717602000, 0.1799089000, 0.1971713000, 0.2340438000, 0.3257893000, 0.5682952000, 1.2190793000", \ - "0.1903316000, 0.2012635000, 0.2230988000, 0.2638220000, 0.3562189000, 0.5997954000, 1.2465017000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0236509000, 0.0284656000, 0.0391379000, 0.0648858000, 0.1271366000, 0.2990423000, 0.7769256000", \ - "0.0236493000, 0.0283573000, 0.0391602000, 0.0647068000, 0.1273320000, 0.2985021000, 0.7785347000", \ - "0.0234750000, 0.0284858000, 0.0392298000, 0.0647518000, 0.1266909000, 0.2988252000, 0.7750978000", \ - "0.0234493000, 0.0281508000, 0.0393890000, 0.0649290000, 0.1269360000, 0.2979377000, 0.7734266000", \ - "0.0243697000, 0.0290084000, 0.0405916000, 0.0654212000, 0.1269932000, 0.2985493000, 0.7728815000", \ - "0.0291909000, 0.0344735000, 0.0462312000, 0.0716364000, 0.1330485000, 0.3000374000, 0.7803618000", \ - "0.0399049000, 0.0459556000, 0.0588033000, 0.0853647000, 0.1459979000, 0.3075213000, 0.7731004000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0201956000, 0.0266194000, 0.0436061000, 0.0905027000, 0.2202452000, 0.5692715000, 1.5021688000", \ - "0.0201383000, 0.0266409000, 0.0435540000, 0.0906877000, 0.2200748000, 0.5693890000, 1.5030791000", \ - "0.0201427000, 0.0266026000, 0.0435662000, 0.0905811000, 0.2203310000, 0.5691692000, 1.5018538000", \ - "0.0206257000, 0.0269511000, 0.0438347000, 0.0907422000, 0.2208138000, 0.5687235000, 1.4989849000", \ - "0.0232514000, 0.0295643000, 0.0457922000, 0.0916897000, 0.2203527000, 0.5691858000, 1.5020993000", \ - "0.0292172000, 0.0354332000, 0.0507203000, 0.0940041000, 0.2208457000, 0.5668023000, 1.5021623000", \ - "0.0398285000, 0.0468283000, 0.0622992000, 0.1016533000, 0.2230273000, 0.5705356000, 1.4983781000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1595958000, 0.1664653000, 0.1810424000, 0.2100081000, 0.2693484000, 0.4076859000, 0.7681688000", \ - "0.1641430000, 0.1710254000, 0.1853857000, 0.2142817000, 0.2738538000, 0.4123021000, 0.7737089000", \ - "0.1750934000, 0.1819994000, 0.1965303000, 0.2255121000, 0.2848288000, 0.4233935000, 0.7846520000", \ - "0.1958604000, 0.2027276000, 0.2172131000, 0.2462134000, 0.3054765000, 0.4439350000, 0.8050118000", \ - "0.2255625000, 0.2324767000, 0.2468022000, 0.2757719000, 0.3354337000, 0.4739141000, 0.8354060000", \ - "0.2612235000, 0.2681409000, 0.2826605000, 0.3116632000, 0.3707685000, 0.5093370000, 0.8697145000", \ - "0.2938144000, 0.3006911000, 0.3151753000, 0.3440556000, 0.4037403000, 0.5424526000, 0.9034080000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1401375000, 0.1463036000, 0.1605721000, 0.1957770000, 0.2871364000, 0.5301749000, 1.1789454000", \ - "0.1445039000, 0.1506362000, 0.1649572000, 0.2000249000, 0.2912853000, 0.5341184000, 1.1861083000", \ - "0.1568710000, 0.1630042000, 0.1772764000, 0.2124959000, 0.3037640000, 0.5460558000, 1.1949167000", \ - "0.1876242000, 0.1937923000, 0.2080946000, 0.2432005000, 0.3345978000, 0.5775980000, 1.2267634000", \ - "0.2547557000, 0.2609848000, 0.2753217000, 0.3104172000, 0.4017896000, 0.6443268000, 1.3024460000", \ - "0.3643959000, 0.3709986000, 0.3856530000, 0.4207843000, 0.5122467000, 0.7549185000, 1.4034296000", \ - "0.5326218000, 0.5401534000, 0.5558157000, 0.5913607000, 0.6830055000, 0.9256289000, 1.5729584000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0237112000, 0.0284704000, 0.0392874000, 0.0648151000, 0.1266576000, 0.2980508000, 0.7721412000", \ - "0.0233826000, 0.0281756000, 0.0393010000, 0.0646054000, 0.1267597000, 0.2985858000, 0.7779324000", \ - "0.0236909000, 0.0281520000, 0.0395328000, 0.0645461000, 0.1266691000, 0.2985003000, 0.7735772000", \ - "0.0235679000, 0.0283297000, 0.0391265000, 0.0646405000, 0.1265953000, 0.2978385000, 0.7788754000", \ - "0.0234223000, 0.0281549000, 0.0393323000, 0.0646850000, 0.1271240000, 0.2986539000, 0.7764589000", \ - "0.0235302000, 0.0283595000, 0.0393498000, 0.0647795000, 0.1271565000, 0.2964947000, 0.7713894000", \ - "0.0240964000, 0.0286812000, 0.0395522000, 0.0649034000, 0.1274626000, 0.2982169000, 0.7728907000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0197268000, 0.0256197000, 0.0421811000, 0.0892645000, 0.2188651000, 0.5680674000, 1.5046778000", \ - "0.0197184000, 0.0255967000, 0.0420757000, 0.0894376000, 0.2190843000, 0.5688323000, 1.5086482000", \ - "0.0197499000, 0.0256101000, 0.0421964000, 0.0894849000, 0.2189296000, 0.5695082000, 1.5067533000", \ - "0.0197634000, 0.0255981000, 0.0420784000, 0.0894669000, 0.2190393000, 0.5684776000, 1.5044349000", \ - "0.0202770000, 0.0260506000, 0.0424172000, 0.0895220000, 0.2189917000, 0.5680038000, 1.4999010000", \ - "0.0224261000, 0.0278496000, 0.0435234000, 0.0899130000, 0.2187604000, 0.5664715000, 1.5065512000", \ - "0.0268392000, 0.0319081000, 0.0462891000, 0.0908829000, 0.2191836000, 0.5656248000, 1.4991177000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21bo_2") { - leakage_power () { - value : 0.0064781000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0040086000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0068416000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0040089000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0066893000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0040090000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0043693000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0013125000; - when : "A1&A2&!B1_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a21bo"; - cell_leakage_power : 0.0047146520; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041447000, 0.0041441000, 0.0041429000, 0.0041444000, 0.0041479000, 0.0041560000, 0.0041746000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004136100, -0.004137000, -0.004139200, -0.004140500, -0.004143500, -0.004150500, -0.004166400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024810000; - } - pin ("A2") { - capacitance : 0.0023710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040217000, 0.0040220000, 0.0040229000, 0.0040245000, 0.0040280000, 0.0040361000, 0.0040549000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004020900, -0.004020300, -0.004018700, -0.004018700, -0.004018600, -0.004018400, -0.004017900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024780000; - } - pin ("B1_N") { - capacitance : 0.0013370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077233000, 0.0076417000, 0.0074535000, 0.0075127000, 0.0076492000, 0.0079637000, 0.0086888000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017738000, 0.0017186000, 0.0015914000, 0.0016483000, 0.0017796000, 0.0020823000, 0.0027798000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0013830000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0144847000, 0.0130862000, 0.0094839000, -0.001217100, -0.036049800, -0.141269200, -0.446422500", \ - "0.0143501000, 0.0129602000, 0.0093338000, -0.001356500, -0.036260600, -0.141396100, -0.446549400", \ - "0.0141451000, 0.0127189000, 0.0090686000, -0.001630500, -0.036458400, -0.141647000, -0.446820300", \ - "0.0138971000, 0.0124566000, 0.0088429000, -0.001877800, -0.036722700, -0.141937500, -0.447046400", \ - "0.0137277000, 0.0122739000, 0.0085677000, -0.002209300, -0.037098400, -0.142193800, -0.447274800", \ - "0.0146931000, 0.0131315000, 0.0087285000, -0.002976500, -0.037458400, -0.142379900, -0.447373900", \ - "0.0177635000, 0.0160726000, 0.0115075000, -0.001140300, -0.037396500, -0.142380200, -0.447183800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0187861000, 0.0205289000, 0.0251880000, 0.0383831000, 0.0753395000, 0.1811380000, 0.4837537000", \ - "0.0187185000, 0.0203830000, 0.0250476000, 0.0382803000, 0.0751996000, 0.1805002000, 0.4819583000", \ - "0.0184960000, 0.0201762000, 0.0249178000, 0.0381079000, 0.0750056000, 0.1808926000, 0.4815784000", \ - "0.0183879000, 0.0200286000, 0.0247260000, 0.0378040000, 0.0746641000, 0.1805964000, 0.4832862000", \ - "0.0183714000, 0.0199921000, 0.0246003000, 0.0373278000, 0.0741645000, 0.1796216000, 0.4819490000", \ - "0.0191981000, 0.0207221000, 0.0251753000, 0.0375624000, 0.0744365000, 0.1789505000, 0.4818922000", \ - "0.0205600000, 0.0220469000, 0.0262949000, 0.0388842000, 0.0755398000, 0.1811421000, 0.4813587000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0169246000, 0.0154757000, 0.0117469000, 0.0010171000, -0.033720900, -0.138791900, -0.443797400", \ - "0.0167299000, 0.0152914000, 0.0116060000, 0.0008804000, -0.033853900, -0.138859700, -0.443875800", \ - "0.0167037000, 0.0152410000, 0.0115379000, 0.0007282000, -0.034029900, -0.139028400, -0.444028500", \ - "0.0164877000, 0.0150272000, 0.0113689000, 0.0005685000, -0.034201600, -0.139176900, -0.444168600", \ - "0.0164493000, 0.0149784000, 0.0112208000, 0.0004043000, -0.034403800, -0.139358400, -0.444341200", \ - "0.0171179000, 0.0155321000, 0.0110407000, -0.000188300, -0.034693900, -0.139509000, -0.444424800", \ - "0.0206666000, 0.0189846000, 0.0145174000, 0.0018410000, -0.034488200, -0.139474300, -0.444192800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0186260000, 0.0203081000, 0.0250000000, 0.0381598000, 0.0751303000, 0.1801802000, 0.4842359000", \ - "0.0184759000, 0.0201745000, 0.0248509000, 0.0380496000, 0.0750107000, 0.1808462000, 0.4834475000", \ - "0.0183606000, 0.0200343000, 0.0247185000, 0.0378864000, 0.0749026000, 0.1797753000, 0.4819169000", \ - "0.0181518000, 0.0198103000, 0.0244979000, 0.0376771000, 0.0745655000, 0.1804893000, 0.4830987000", \ - "0.0180625000, 0.0196877000, 0.0243032000, 0.0372867000, 0.0742193000, 0.1792974000, 0.4816986000", \ - "0.0185396000, 0.0200866000, 0.0246208000, 0.0373594000, 0.0741254000, 0.1788466000, 0.4826252000", \ - "0.0197338000, 0.0212180000, 0.0256014000, 0.0383810000, 0.0750875000, 0.1806656000, 0.4806430000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0162627000, 0.0148228000, 0.0111439000, 0.0004147000, -0.034298700, -0.139293300, -0.444259300", \ - "0.0162383000, 0.0148019000, 0.0111205000, 0.0003845000, -0.034294600, -0.139282600, -0.444263700", \ - "0.0161805000, 0.0147196000, 0.0111283000, 0.0002786000, -0.034468000, -0.139393000, -0.444394300", \ - "0.0158074000, 0.0143442000, 0.0107513000, -0.000103600, -0.034848400, -0.139770700, -0.444764800", \ - "0.0154328000, 0.0139947000, 0.0103154000, -0.000445000, -0.035174200, -0.140154800, -0.445103000", \ - "0.0186418000, 0.0171485000, 0.0129602000, 0.0005665000, -0.035369900, -0.140352200, -0.445310200", \ - "0.0192021000, 0.0176897000, 0.0133512000, 0.0009452000, -0.034961100, -0.140274000, -0.445490900"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0169175000, 0.0185951000, 0.0233158000, 0.0364459000, 0.0731774000, 0.1782158000, 0.4808589000", \ - "0.0168847000, 0.0185616000, 0.0232926000, 0.0364099000, 0.0732260000, 0.1781603000, 0.4811648000", \ - "0.0168853000, 0.0185834000, 0.0233110000, 0.0364295000, 0.0732412000, 0.1782001000, 0.4782466000", \ - "0.0166943000, 0.0183645000, 0.0231119000, 0.0362184000, 0.0729164000, 0.1779451000, 0.4805122000", \ - "0.0163886000, 0.0180627000, 0.0227869000, 0.0358786000, 0.0726154000, 0.1776329000, 0.4801213000", \ - "0.0160616000, 0.0176387000, 0.0222150000, 0.0354317000, 0.0720484000, 0.1770992000, 0.4773357000", \ - "0.0163243000, 0.0179185000, 0.0224578000, 0.0354016000, 0.0719049000, 0.1772672000, 0.4779836000"); - } - } - max_capacitance : 0.2884010000; - max_transition : 1.5044830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1591938000, 0.1647438000, 0.1773027000, 0.2025539000, 0.2533492000, 0.3677770000, 0.6724877000", \ - "0.1640461000, 0.1696070000, 0.1821472000, 0.2076079000, 0.2582776000, 0.3726033000, 0.6776346000", \ - "0.1762360000, 0.1817527000, 0.1942627000, 0.2195396000, 0.2703331000, 0.3846759000, 0.6897635000", \ - "0.2037787000, 0.2092314000, 0.2215032000, 0.2472101000, 0.2978767000, 0.4122008000, 0.7174590000", \ - "0.2648229000, 0.2703429000, 0.2827821000, 0.3079467000, 0.3589232000, 0.4732746000, 0.7779249000", \ - "0.3785563000, 0.3848544000, 0.3990346000, 0.4272905000, 0.4821666000, 0.5986787000, 0.9039862000", \ - "0.5659118000, 0.5736319000, 0.5910385000, 0.6254687000, 0.6886224000, 0.8141933000, 1.1224958000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0870691000, 0.0926895000, 0.1062255000, 0.1383541000, 0.2219979000, 0.4578226000, 1.1315175000", \ - "0.0910992000, 0.0967326000, 0.1102175000, 0.1423134000, 0.2257998000, 0.4610625000, 1.1386013000", \ - "0.1009430000, 0.1065866000, 0.1201568000, 0.1522473000, 0.2358907000, 0.4711905000, 1.1444641000", \ - "0.1248844000, 0.1304253000, 0.1438547000, 0.1757766000, 0.2593207000, 0.4949121000, 1.1691614000", \ - "0.1649817000, 0.1709651000, 0.1849847000, 0.2172715000, 0.3009805000, 0.5364981000, 1.2112163000", \ - "0.2123430000, 0.2195372000, 0.2356912000, 0.2700621000, 0.3529493000, 0.5884435000, 1.2642505000", \ - "0.2489847000, 0.2588099000, 0.2795664000, 0.3192337000, 0.4046906000, 0.6391990000, 1.3136867000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0250901000, 0.0286569000, 0.0369801000, 0.0562006000, 0.1036360000, 0.2344632000, 0.6356846000", \ - "0.0252172000, 0.0287233000, 0.0373038000, 0.0566030000, 0.1037902000, 0.2348399000, 0.6361271000", \ - "0.0253916000, 0.0286591000, 0.0370041000, 0.0562682000, 0.1036418000, 0.2348014000, 0.6358639000", \ - "0.0253848000, 0.0287784000, 0.0375417000, 0.0565762000, 0.1038033000, 0.2347162000, 0.6356526000", \ - "0.0258292000, 0.0294577000, 0.0373881000, 0.0564934000, 0.1040189000, 0.2354779000, 0.6348962000", \ - "0.0318741000, 0.0361246000, 0.0445118000, 0.0647863000, 0.1103794000, 0.2392836000, 0.6385871000", \ - "0.0451815000, 0.0503107000, 0.0598749000, 0.0811990000, 0.1272860000, 0.2514764000, 0.6363654000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0215493000, 0.0264644000, 0.0398533000, 0.0779353000, 0.1925557000, 0.5295158000, 1.4987247000", \ - "0.0215910000, 0.0264508000, 0.0398358000, 0.0779536000, 0.1921304000, 0.5286052000, 1.4989469000", \ - "0.0215138000, 0.0265390000, 0.0398787000, 0.0779163000, 0.1923308000, 0.5290930000, 1.4969658000", \ - "0.0216034000, 0.0265479000, 0.0398522000, 0.0781366000, 0.1924969000, 0.5294584000, 1.4977373000", \ - "0.0250182000, 0.0297265000, 0.0425415000, 0.0799266000, 0.1929939000, 0.5290261000, 1.4989717000", \ - "0.0327669000, 0.0374450000, 0.0492501000, 0.0838995000, 0.1943288000, 0.5273017000, 1.4999820000", \ - "0.0454271000, 0.0516036000, 0.0644049000, 0.0964689000, 0.1983539000, 0.5322159000, 1.4936987000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1784200000, 0.1842270000, 0.1971562000, 0.2232970000, 0.2750457000, 0.3905994000, 0.6963566000", \ - "0.1836018000, 0.1893864000, 0.2023860000, 0.2285410000, 0.2802732000, 0.3958106000, 0.7016780000", \ - "0.1961919000, 0.2020053000, 0.2149718000, 0.2411182000, 0.2930882000, 0.4084783000, 0.7139191000", \ - "0.2227750000, 0.2285509000, 0.2415755000, 0.2677388000, 0.3196182000, 0.4350404000, 0.7405579000", \ - "0.2802071000, 0.2860135000, 0.2989034000, 0.3249997000, 0.3770293000, 0.4926238000, 0.7984671000", \ - "0.3892950000, 0.3957626000, 0.4098282000, 0.4383204000, 0.4932675000, 0.6109008000, 0.9167708000", \ - "0.5688593000, 0.5767587000, 0.5945119000, 0.6281621000, 0.6905820000, 0.8156522000, 1.1245004000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0910401000, 0.0966491000, 0.1102089000, 0.1423280000, 0.2260215000, 0.4610136000, 1.1363486000", \ - "0.0953372000, 0.1009964000, 0.1145304000, 0.1466738000, 0.2303520000, 0.4660290000, 1.1396859000", \ - "0.1049286000, 0.1105445000, 0.1240413000, 0.1561592000, 0.2397315000, 0.4746973000, 1.1499126000", \ - "0.1263912000, 0.1319939000, 0.1455465000, 0.1775319000, 0.2611628000, 0.4969055000, 1.1703291000", \ - "0.1658598000, 0.1718615000, 0.1859297000, 0.2185205000, 0.3022439000, 0.5374583000, 1.2130869000", \ - "0.2193649000, 0.2265038000, 0.2424315000, 0.2768174000, 0.3610093000, 0.5961006000, 1.2726105000", \ - "0.2719392000, 0.2813048000, 0.3017038000, 0.3410825000, 0.4273203000, 0.6626678000, 1.3365442000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0271968000, 0.0308128000, 0.0391819000, 0.0581828000, 0.1060035000, 0.2369176000, 0.6385831000", \ - "0.0272574000, 0.0309249000, 0.0395773000, 0.0582328000, 0.1059271000, 0.2367798000, 0.6362776000", \ - "0.0274570000, 0.0307539000, 0.0396209000, 0.0586077000, 0.1056141000, 0.2368892000, 0.6393973000", \ - "0.0273897000, 0.0310017000, 0.0391563000, 0.0588840000, 0.1057438000, 0.2374236000, 0.6393964000", \ - "0.0274455000, 0.0309010000, 0.0394677000, 0.0585154000, 0.1057311000, 0.2367721000, 0.6394271000", \ - "0.0328189000, 0.0368281000, 0.0452198000, 0.0648773000, 0.1109709000, 0.2404454000, 0.6383130000", \ - "0.0453218000, 0.0492244000, 0.0589551000, 0.0795077000, 0.1253847000, 0.2507969000, 0.6370041000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0215454000, 0.0265159000, 0.0398076000, 0.0780870000, 0.1926254000, 0.5294133000, 1.5008396000", \ - "0.0214717000, 0.0263789000, 0.0398540000, 0.0779772000, 0.1926141000, 0.5295088000, 1.4979925000", \ - "0.0215634000, 0.0264403000, 0.0397823000, 0.0778945000, 0.1924054000, 0.5284358000, 1.4999868000", \ - "0.0216720000, 0.0266157000, 0.0398746000, 0.0781071000, 0.1926097000, 0.5296132000, 1.4955911000", \ - "0.0241438000, 0.0290531000, 0.0421613000, 0.0793500000, 0.1926420000, 0.5286863000, 1.5001025000", \ - "0.0303189000, 0.0351616000, 0.0480847000, 0.0834082000, 0.1943044000, 0.5279082000, 1.4981328000", \ - "0.0418673000, 0.0477994000, 0.0613490000, 0.0941198000, 0.1979204000, 0.5314221000, 1.4956653000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1847016000, 0.1905313000, 0.2035302000, 0.2297415000, 0.2815798000, 0.3969844000, 0.7028985000", \ - "0.1895024000, 0.1953110000, 0.2083494000, 0.2345786000, 0.2862806000, 0.4018640000, 0.7077426000", \ - "0.1997617000, 0.2055524000, 0.2185754000, 0.2447875000, 0.2968743000, 0.4123686000, 0.7177240000", \ - "0.2191616000, 0.2249401000, 0.2379543000, 0.2641476000, 0.3161413000, 0.4316458000, 0.7370702000", \ - "0.2464236000, 0.2522301000, 0.2652073000, 0.2912504000, 0.3431929000, 0.4588410000, 0.7642522000", \ - "0.2794383000, 0.2852421000, 0.2981873000, 0.3243100000, 0.3762572000, 0.4918352000, 0.7976929000", \ - "0.3048277000, 0.3106294000, 0.3235500000, 0.3496359000, 0.4016875000, 0.5173873000, 0.8223030000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1534354000, 0.1586577000, 0.1712154000, 0.2019983000, 0.2848143000, 0.5192135000, 1.1961587000", \ - "0.1581806000, 0.1633899000, 0.1760233000, 0.2067435000, 0.2892802000, 0.5246480000, 1.2028428000", \ - "0.1710571000, 0.1762570000, 0.1888844000, 0.2195650000, 0.3021201000, 0.5375141000, 1.2103477000", \ - "0.2028143000, 0.2079968000, 0.2205967000, 0.2513656000, 0.3341475000, 0.5685296000, 1.2468351000", \ - "0.2731698000, 0.2783904000, 0.2910211000, 0.3217676000, 0.4044402000, 0.6386000000, 1.3162197000", \ - "0.3933012000, 0.3988387000, 0.4117477000, 0.4427225000, 0.5256422000, 0.7603237000, 1.4338422000", \ - "0.5838380000, 0.5900309000, 0.6039845000, 0.6356692000, 0.7186800000, 0.9531509000, 1.6267468000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0272618000, 0.0309263000, 0.0395083000, 0.0580590000, 0.1058277000, 0.2365589000, 0.6364606000", \ - "0.0272750000, 0.0309285000, 0.0395245000, 0.0582245000, 0.1058474000, 0.2366921000, 0.6362747000", \ - "0.0274503000, 0.0310112000, 0.0394399000, 0.0583604000, 0.1056789000, 0.2373566000, 0.6356425000", \ - "0.0274231000, 0.0309962000, 0.0394278000, 0.0582882000, 0.1056469000, 0.2372897000, 0.6357163000", \ - "0.0271828000, 0.0310422000, 0.0393611000, 0.0583403000, 0.1058684000, 0.2362513000, 0.6364285000", \ - "0.0273406000, 0.0308558000, 0.0394994000, 0.0581974000, 0.1057306000, 0.2356085000, 0.6375255000", \ - "0.0273445000, 0.0309551000, 0.0398801000, 0.0587051000, 0.1060066000, 0.2370029000, 0.6359789000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0201793000, 0.0246510000, 0.0374321000, 0.0755621000, 0.1902292000, 0.5274281000, 1.5024821000", \ - "0.0201869000, 0.0246490000, 0.0374474000, 0.0756535000, 0.1906674000, 0.5275638000, 1.5044830000", \ - "0.0201515000, 0.0246349000, 0.0374419000, 0.0756537000, 0.1906426000, 0.5275476000, 1.4995895000", \ - "0.0201868000, 0.0246530000, 0.0374104000, 0.0755859000, 0.1904446000, 0.5274381000, 1.5014531000", \ - "0.0203947000, 0.0249063000, 0.0376035000, 0.0755552000, 0.1907256000, 0.5282303000, 1.5037064000", \ - "0.0222782000, 0.0265858000, 0.0389121000, 0.0762117000, 0.1907721000, 0.5267085000, 1.4993501000", \ - "0.0262549000, 0.0302962000, 0.0421667000, 0.0782205000, 0.1916340000, 0.5252778000, 1.4968612000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21bo_4") { - leakage_power () { - value : 0.0083995000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0058546000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0093676000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0058546000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0090397000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0058546000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0075080000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0029896000; - when : "A1&A2&!B1_N"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__a21bo"; - cell_leakage_power : 0.0068585080; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075869000, 0.0075855000, 0.0075821000, 0.0075834000, 0.0075866000, 0.0075938000, 0.0076105000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007591200, -0.007585700, -0.007573200, -0.007575600, -0.007581300, -0.007594300, -0.007624300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045930000; - } - pin ("A2") { - capacitance : 0.0047940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082730000, 0.0082754000, 0.0082810000, 0.0082783000, 0.0082720000, 0.0082576000, 0.0082244000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008297100, -0.008289300, -0.008271400, -0.008266600, -0.008255700, -0.008230500, -0.008172500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050270000; - } - pin ("B1_N") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150112000, 0.0148767000, 0.0145667000, 0.0147210000, 0.0150768000, 0.0158968000, 0.0177870000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045746000, 0.0044631000, 0.0042062000, 0.0043370000, 0.0046384000, 0.0053330000, 0.0069343000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025040000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0287793000, 0.0271694000, 0.0220928000, 0.0080520000, -0.040900100, -0.206192300, -0.730139000", \ - "0.0284898000, 0.0268578000, 0.0217968000, 0.0077329000, -0.041169300, -0.206484400, -0.730406200", \ - "0.0280752000, 0.0263928000, 0.0213284000, 0.0072575000, -0.041584400, -0.206885400, -0.730785400", \ - "0.0276595000, 0.0260156000, 0.0208948000, 0.0067593000, -0.042059400, -0.207346300, -0.731212700", \ - "0.0273730000, 0.0257394000, 0.0205815000, 0.0063134000, -0.042680000, -0.207770100, -0.731619000", \ - "0.0274773000, 0.0256214000, 0.0200771000, 0.0051556000, -0.043275500, -0.208016000, -0.731728900", \ - "0.0351097000, 0.0331327000, 0.0273658000, 0.0102528000, -0.042476700, -0.208205400, -0.731476800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0333402000, 0.0351655000, 0.0410453000, 0.0590654000, 0.1131127000, 0.2794436000, 0.7979701000", \ - "0.0330529000, 0.0349316000, 0.0408465000, 0.0588127000, 0.1128753000, 0.2792588000, 0.7974006000", \ - "0.0327559000, 0.0346593000, 0.0405588000, 0.0584922000, 0.1125829000, 0.2790510000, 0.7973509000", \ - "0.0326359000, 0.0345006000, 0.0403115000, 0.0580010000, 0.1119062000, 0.2782930000, 0.7969835000", \ - "0.0325387000, 0.0343185000, 0.0400873000, 0.0576573000, 0.1112481000, 0.2779141000, 0.7969836000", \ - "0.0339698000, 0.0357156000, 0.0412736000, 0.0584154000, 0.1112888000, 0.2773279000, 0.7969349000", \ - "0.0366732000, 0.0383493000, 0.0436714000, 0.0606443000, 0.1129905000, 0.2791802000, 0.7965250000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0339691000, 0.0323885000, 0.0273396000, 0.0131172000, -0.036043700, -0.201253800, -0.725046400", \ - "0.0338321000, 0.0321215000, 0.0270626000, 0.0129102000, -0.036236300, -0.201454300, -0.725246400", \ - "0.0334752000, 0.0318821000, 0.0268585000, 0.0126001000, -0.036453200, -0.201736100, -0.725527300", \ - "0.0331887000, 0.0315567000, 0.0264820000, 0.0123323000, -0.036788900, -0.202035600, -0.725830600", \ - "0.0329923000, 0.0313791000, 0.0263054000, 0.0119304000, -0.037213200, -0.202393600, -0.726119300", \ - "0.0322166000, 0.0303558000, 0.0250221000, 0.0108796000, -0.037733200, -0.202653200, -0.726238700", \ - "0.0405651000, 0.0386272000, 0.0328419000, 0.0157682000, -0.037011600, -0.202233500, -0.725604600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0340306000, 0.0358822000, 0.0418081000, 0.0596959000, 0.1137801000, 0.2801414000, 0.7984925000", \ - "0.0337596000, 0.0356374000, 0.0415791000, 0.0594662000, 0.1135741000, 0.2796059000, 0.7982059000", \ - "0.0334470000, 0.0353312000, 0.0412274000, 0.0591395000, 0.1132261000, 0.2793379000, 0.7978198000", \ - "0.0332315000, 0.0351187000, 0.0408322000, 0.0585830000, 0.1126540000, 0.2789831000, 0.7975082000", \ - "0.0330020000, 0.0348102000, 0.0406174000, 0.0581032000, 0.1119671000, 0.2784653000, 0.7973982000", \ - "0.0336277000, 0.0354219000, 0.0409976000, 0.0582639000, 0.1113727000, 0.2772210000, 0.7964655000", \ - "0.0357862000, 0.0374931000, 0.0428547000, 0.0596898000, 0.1132096000, 0.2791582000, 0.7961487000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0324016000, 0.0308023000, 0.0257737000, 0.0115719000, -0.037551200, -0.202780300, -0.726471400", \ - "0.0322602000, 0.0306923000, 0.0256258000, 0.0114791000, -0.037570200, -0.202772500, -0.726554600", \ - "0.0322285000, 0.0306345000, 0.0255468000, 0.0113821000, -0.037686400, -0.202883000, -0.726596400", \ - "0.0315412000, 0.0299254000, 0.0249078000, 0.0106471000, -0.038502000, -0.203658200, -0.727305700", \ - "0.0308948000, 0.0292294000, 0.0242289000, 0.0099391000, -0.039075400, -0.204335300, -0.727961200", \ - "0.0361274000, 0.0343958000, 0.0291395000, 0.0127474000, -0.039511700, -0.204840500, -0.728459500", \ - "0.0375030000, 0.0357779000, 0.0305623000, 0.0141698000, -0.038087400, -0.204487200, -0.728510300"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015677720, 0.0049158190, 0.0154137700, 0.0483305500, 0.1515426000, 0.4751685000"); - values("0.0296901000, 0.0315954000, 0.0374580000, 0.0551122000, 0.1085342000, 0.2741842000, 0.7926498000", \ - "0.0297196000, 0.0316132000, 0.0374604000, 0.0550639000, 0.1084750000, 0.2741530000, 0.7902036000", \ - "0.0297005000, 0.0315931000, 0.0374314000, 0.0550478000, 0.1084938000, 0.2740096000, 0.7934591000", \ - "0.0293089000, 0.0312025000, 0.0370426000, 0.0546486000, 0.1081160000, 0.2739454000, 0.7894757000", \ - "0.0287299000, 0.0306083000, 0.0364361000, 0.0540292000, 0.1074659000, 0.2731660000, 0.7893720000", \ - "0.0280174000, 0.0298118000, 0.0353718000, 0.0530533000, 0.1064970000, 0.2720843000, 0.7915000000", \ - "0.0287192000, 0.0304776000, 0.0360719000, 0.0533972000, 0.1070237000, 0.2732195000, 0.7892881000"); - } - } - max_capacitance : 0.4751690000; - max_transition : 1.5028070000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.1742197000, 0.1780640000, 0.1880849000, 0.2105681000, 0.2566490000, 0.3601659000, 0.6396088000", \ - "0.1788503000, 0.1827494000, 0.1927525000, 0.2152181000, 0.2615883000, 0.3648690000, 0.6444100000", \ - "0.1910125000, 0.1948932000, 0.2048582000, 0.2272935000, 0.2733362000, 0.3770075000, 0.6564735000", \ - "0.2180152000, 0.2219428000, 0.2319173000, 0.2542085000, 0.3003956000, 0.4040419000, 0.6836128000", \ - "0.2768746000, 0.2807476000, 0.2907441000, 0.3130421000, 0.3593770000, 0.4629205000, 0.7425008000", \ - "0.3892839000, 0.3936184000, 0.4047327000, 0.4292694000, 0.4788290000, 0.5853579000, 0.8656543000", \ - "0.5849097000, 0.5899720000, 0.6030840000, 0.6318827000, 0.6886934000, 0.8035936000, 1.0888854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0812039000, 0.0850591000, 0.0954708000, 0.1222509000, 0.1959267000, 0.4189616000, 1.1148638000", \ - "0.0851859000, 0.0890557000, 0.0994616000, 0.1262328000, 0.1998155000, 0.4226112000, 1.1168256000", \ - "0.0952106000, 0.0991258000, 0.1095270000, 0.1362918000, 0.2100338000, 0.4332018000, 1.1263553000", \ - "0.1184577000, 0.1223091000, 0.1326109000, 0.1591327000, 0.2328353000, 0.4556872000, 1.1503005000", \ - "0.1542216000, 0.1582682000, 0.1690266000, 0.1961616000, 0.2696312000, 0.4929969000, 1.1881556000", \ - "0.1936795000, 0.1986486000, 0.2109398000, 0.2390957000, 0.3128864000, 0.5362993000, 1.2308347000", \ - "0.2144158000, 0.2209255000, 0.2368774000, 0.2709901000, 0.3457119000, 0.5685626000, 1.2621847000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0267205000, 0.0290676000, 0.0356235000, 0.0515748000, 0.0912549000, 0.2032114000, 0.5688400000", \ - "0.0266218000, 0.0290910000, 0.0356017000, 0.0512859000, 0.0910307000, 0.2034048000, 0.5685457000", \ - "0.0265148000, 0.0289401000, 0.0353127000, 0.0512335000, 0.0913416000, 0.2034733000, 0.5692317000", \ - "0.0265820000, 0.0290210000, 0.0354396000, 0.0511558000, 0.0912500000, 0.2031310000, 0.5689907000", \ - "0.0267277000, 0.0292150000, 0.0356133000, 0.0513482000, 0.0912542000, 0.2037851000, 0.5689327000", \ - "0.0323046000, 0.0345760000, 0.0415241000, 0.0584577000, 0.0971136000, 0.2075183000, 0.5697293000", \ - "0.0441596000, 0.0467431000, 0.0545901000, 0.0718980000, 0.1120691000, 0.2209788000, 0.5733417000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0209235000, 0.0244787000, 0.0346636000, 0.0657264000, 0.1665099000, 0.4874191000, 1.5000967000", \ - "0.0210245000, 0.0244326000, 0.0346178000, 0.0655984000, 0.1660945000, 0.4885085000, 1.4965013000", \ - "0.0209917000, 0.0244279000, 0.0345868000, 0.0657684000, 0.1664739000, 0.4883761000, 1.4995049000", \ - "0.0211358000, 0.0244984000, 0.0346708000, 0.0658532000, 0.1664428000, 0.4881575000, 1.4963880000", \ - "0.0238646000, 0.0272311000, 0.0370887000, 0.0677095000, 0.1669990000, 0.4881817000, 1.4973883000", \ - "0.0308081000, 0.0341815000, 0.0437360000, 0.0717744000, 0.1685215000, 0.4884014000, 1.4990746000", \ - "0.0431141000, 0.0469133000, 0.0572300000, 0.0839376000, 0.1727752000, 0.4896490000, 1.4983087000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.1797980000, 0.1836751000, 0.1935369000, 0.2152691000, 0.2600786000, 0.3611437000, 0.6395937000", \ - "0.1849727000, 0.1888569000, 0.1987461000, 0.2205022000, 0.2653114000, 0.3663918000, 0.6448422000", \ - "0.1978486000, 0.2017258000, 0.2114740000, 0.2332370000, 0.2781423000, 0.3792207000, 0.6575198000", \ - "0.2257639000, 0.2296417000, 0.2394864000, 0.2610704000, 0.3058354000, 0.4070586000, 0.6856051000", \ - "0.2860129000, 0.2898971000, 0.2997135000, 0.3213620000, 0.3662129000, 0.4676187000, 0.7461193000", \ - "0.4026601000, 0.4069690000, 0.4178959000, 0.4417051000, 0.4894851000, 0.5932344000, 0.8721475000", \ - "0.5997753000, 0.6050404000, 0.6183561000, 0.6468679000, 0.7019378000, 0.8128681000, 1.0953696000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0860955000, 0.0899547000, 0.1003823000, 0.1270803000, 0.2005793000, 0.4234437000, 1.1160106000", \ - "0.0902399000, 0.0941002000, 0.1045153000, 0.1313040000, 0.2049885000, 0.4274504000, 1.1218353000", \ - "0.0993672000, 0.1032885000, 0.1136900000, 0.1404546000, 0.2141426000, 0.4371498000, 1.1309083000", \ - "0.1199406000, 0.1237990000, 0.1341179000, 0.1606593000, 0.2341188000, 0.4571609000, 1.1511158000", \ - "0.1552446000, 0.1593357000, 0.1702255000, 0.1974764000, 0.2710906000, 0.4944444000, 1.1901591000", \ - "0.1996959000, 0.2045362000, 0.2168433000, 0.2457953000, 0.3201915000, 0.5433026000, 1.2377342000", \ - "0.2328524000, 0.2391623000, 0.2548964000, 0.2886088000, 0.3656588000, 0.5890500000, 1.2818829000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0264639000, 0.0288509000, 0.0350456000, 0.0497332000, 0.0877827000, 0.2002396000, 0.5658528000", \ - "0.0263749000, 0.0286927000, 0.0347541000, 0.0497043000, 0.0877778000, 0.2002828000, 0.5659527000", \ - "0.0265453000, 0.0289328000, 0.0351228000, 0.0500041000, 0.0885391000, 0.2005314000, 0.5660239000", \ - "0.0262255000, 0.0285650000, 0.0346183000, 0.0501055000, 0.0886324000, 0.2005065000, 0.5667364000", \ - "0.0265447000, 0.0286830000, 0.0347922000, 0.0498333000, 0.0885925000, 0.2003341000, 0.5662483000", \ - "0.0319563000, 0.0344159000, 0.0405070000, 0.0563036000, 0.0935921000, 0.2035677000, 0.5683297000", \ - "0.0437548000, 0.0467956000, 0.0536869000, 0.0703166000, 0.1088737000, 0.2163804000, 0.5726232000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0209982000, 0.0244754000, 0.0346353000, 0.0658166000, 0.1659043000, 0.4889789000, 1.4998146000", \ - "0.0209773000, 0.0244497000, 0.0345894000, 0.0656563000, 0.1664779000, 0.4882972000, 1.4949160000", \ - "0.0210344000, 0.0244291000, 0.0345518000, 0.0657166000, 0.1664803000, 0.4879909000, 1.4977577000", \ - "0.0210953000, 0.0245372000, 0.0348379000, 0.0659311000, 0.1659517000, 0.4888517000, 1.4979752000", \ - "0.0234715000, 0.0269156000, 0.0369016000, 0.0674132000, 0.1670476000, 0.4874444000, 1.4988806000", \ - "0.0294439000, 0.0329116000, 0.0424406000, 0.0713575000, 0.1685258000, 0.4873001000, 1.4993654000", \ - "0.0400162000, 0.0441677000, 0.0550432000, 0.0825176000, 0.1726244000, 0.4898127000, 1.4936906000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.1890289000, 0.1928648000, 0.2027495000, 0.2246165000, 0.2694354000, 0.3706662000, 0.6491117000", \ - "0.1935168000, 0.1974356000, 0.2073392000, 0.2291864000, 0.2737517000, 0.3749880000, 0.6535471000", \ - "0.2037843000, 0.2076755000, 0.2175529000, 0.2392710000, 0.2842107000, 0.3853059000, 0.6635714000", \ - "0.2236644000, 0.2275304000, 0.2374358000, 0.2591964000, 0.3041446000, 0.4053242000, 0.6839452000", \ - "0.2522212000, 0.2561030000, 0.2659503000, 0.2877348000, 0.3324453000, 0.4336784000, 0.7122307000", \ - "0.2842631000, 0.2881492000, 0.2980409000, 0.3198236000, 0.3646624000, 0.4658789000, 0.7446369000", \ - "0.3059309000, 0.3098112000, 0.3196793000, 0.3413907000, 0.3860739000, 0.4876290000, 0.7659757000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.1418139000, 0.1453436000, 0.1549130000, 0.1801688000, 0.2524746000, 0.4737471000, 1.1724953000", \ - "0.1469704000, 0.1504676000, 0.1600721000, 0.1853471000, 0.2576038000, 0.4797613000, 1.1711611000", \ - "0.1596621000, 0.1631629000, 0.1727294000, 0.1979014000, 0.2702188000, 0.4916235000, 1.1847316000", \ - "0.1910541000, 0.1945636000, 0.2041682000, 0.2293195000, 0.3013612000, 0.5227239000, 1.2166573000", \ - "0.2587478000, 0.2622743000, 0.2719039000, 0.2970790000, 0.3691051000, 0.5909195000, 1.2907644000", \ - "0.3708572000, 0.3745136000, 0.3844050000, 0.4099484000, 0.4823748000, 0.7042895000, 1.3968923000", \ - "0.5488578000, 0.5529336000, 0.5636424000, 0.5900229000, 0.6628344000, 0.8847304000, 1.5768501000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0265096000, 0.0286590000, 0.0349137000, 0.0498453000, 0.0884511000, 0.2003135000, 0.5678873000", \ - "0.0261802000, 0.0285673000, 0.0346230000, 0.0499121000, 0.0886664000, 0.2005183000, 0.5667364000", \ - "0.0264940000, 0.0289281000, 0.0350364000, 0.0500665000, 0.0884474000, 0.2004743000, 0.5660328000", \ - "0.0265495000, 0.0287951000, 0.0350933000, 0.0499720000, 0.0877874000, 0.2004595000, 0.5672240000", \ - "0.0263916000, 0.0287207000, 0.0347942000, 0.0495707000, 0.0885794000, 0.2001880000, 0.5677520000", \ - "0.0264334000, 0.0288223000, 0.0348116000, 0.0502055000, 0.0883921000, 0.1997533000, 0.5681511000", \ - "0.0268616000, 0.0291927000, 0.0351966000, 0.0501015000, 0.0887583000, 0.2006360000, 0.5673585000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015677700, 0.0049158200, 0.0154138000, 0.0483306000, 0.1515430000, 0.4751690000"); - values("0.0194658000, 0.0226169000, 0.0322660000, 0.0633327000, 0.1643276000, 0.4868352000, 1.5026870000", \ - "0.0194885000, 0.0225686000, 0.0323452000, 0.0632799000, 0.1645645000, 0.4868954000, 1.4960473000", \ - "0.0195035000, 0.0226362000, 0.0323479000, 0.0633297000, 0.1643599000, 0.4864986000, 1.5028071000", \ - "0.0194972000, 0.0226186000, 0.0323408000, 0.0633526000, 0.1642046000, 0.4860489000, 1.4986129000", \ - "0.0198830000, 0.0229833000, 0.0326203000, 0.0634512000, 0.1641609000, 0.4871501000, 1.5012728000", \ - "0.0215170000, 0.0245371000, 0.0339653000, 0.0643597000, 0.1648631000, 0.4861204000, 1.5006558000", \ - "0.0252759000, 0.0281310000, 0.0371671000, 0.0661540000, 0.1657219000, 0.4864348000, 1.4941253000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21boi_0") { - leakage_power () { - value : 0.0028661000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0019830000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0033439000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0019830000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0031333000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0019830000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0039234000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0006065000; - when : "A1&A2&!B1_N"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__a21boi"; - cell_leakage_power : 0.0024778020; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0018010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029234000, 0.0029271000, 0.0029356000, 0.0029355000, 0.0029354000, 0.0029352000, 0.0029345000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002949900, -0.002945100, -0.002934000, -0.002933400, -0.002932100, -0.002929100, -0.002922200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018480000; - } - pin ("A2") { - capacitance : 0.0017180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027691000, 0.0027707000, 0.0027744000, 0.0027737000, 0.0027721000, 0.0027685000, 0.0027602000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002769500, -0.002768600, -0.002766700, -0.002767200, -0.002768200, -0.002770500, -0.002776000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017840000; - } - pin ("B1_N") { - capacitance : 0.0016230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081007000, 0.0079922000, 0.0077421000, 0.0078175000, 0.0079913000, 0.0083920000, 0.0093156000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0010923000, 0.0010185000, 0.0008485000, 0.0009176000, 0.0010767000, 0.0014434000, 0.0022887000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016880000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&B1_N) | (!A2&B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0034673000, 0.0025596000, 0.0006043000, -0.003609700, -0.012691300, -0.032194600, -0.074090600", \ - "0.0033545000, 0.0024488000, 0.0005091000, -0.003688300, -0.012748800, -0.032264500, -0.074149900", \ - "0.0031937000, 0.0023037000, 0.0003744000, -0.003807800, -0.012828300, -0.032325500, -0.074218400", \ - "0.0030249000, 0.0021552000, 0.0002455000, -0.003914300, -0.012923800, -0.032399800, -0.074273400", \ - "0.0029640000, 0.0020543000, 0.0001226000, -0.004034700, -0.013027200, -0.032459500, -0.074281400", \ - "0.0032411000, 0.0022993000, 0.0002941000, -0.003973200, -0.013056900, -0.032519100, -0.074304600", \ - "0.0040956000, 0.0030963000, 0.0010415000, -0.003337200, -0.012600800, -0.032299800, -0.074250900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0063767000, 0.0073516000, 0.0093674000, 0.0136197000, 0.0226608000, 0.0421624000, 0.0840990000", \ - "0.0062028000, 0.0071959000, 0.0092622000, 0.0135874000, 0.0227931000, 0.0420732000, 0.0840427000", \ - "0.0060058000, 0.0069871000, 0.0090370000, 0.0133765000, 0.0225146000, 0.0419146000, 0.0833502000", \ - "0.0058898000, 0.0068434000, 0.0088817000, 0.0131744000, 0.0223376000, 0.0417965000, 0.0832765000", \ - "0.0058008000, 0.0067416000, 0.0087237000, 0.0130126000, 0.0221679000, 0.0418411000, 0.0833484000", \ - "0.0057769000, 0.0067097000, 0.0087162000, 0.0129975000, 0.0220721000, 0.0415787000, 0.0834868000", \ - "0.0058126000, 0.0067505000, 0.0086559000, 0.0129454000, 0.0221268000, 0.0416577000, 0.0832080000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0031982000, 0.0022839000, 0.0003252000, -0.003885700, -0.012954300, -0.032477800, -0.074358400", \ - "0.0031155000, 0.0022054000, 0.0002517000, -0.003959200, -0.013022400, -0.032548700, -0.074427200", \ - "0.0030092000, 0.0021028000, 0.0001591000, -0.004039900, -0.013098200, -0.032596400, -0.074480600", \ - "0.0028864000, 0.0019887000, 4.270000e-05, -0.004119400, -0.013157800, -0.032656200, -0.074521300", \ - "0.0028784000, 0.0019075000, -1.15000e-05, -0.004169100, -0.013213000, -0.032662700, -0.074525300", \ - "0.0029915000, 0.0020618000, 7.390000e-05, -0.004125300, -0.013304000, -0.032744200, -0.074569700", \ - "0.0035916000, 0.0026306000, 0.0005923000, -0.003740100, -0.012952300, -0.032646200, -0.074543300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0079611000, 0.0088855000, 0.0108705000, 0.0150855000, 0.0241173000, 0.0433891000, 0.0848076000", \ - "0.0078790000, 0.0088088000, 0.0108127000, 0.0150407000, 0.0240824000, 0.0434264000, 0.0847875000", \ - "0.0077746000, 0.0087112000, 0.0107225000, 0.0149690000, 0.0240225000, 0.0433700000, 0.0846289000", \ - "0.0077010000, 0.0086421000, 0.0106368000, 0.0148819000, 0.0239582000, 0.0433350000, 0.0847021000", \ - "0.0076460000, 0.0085718000, 0.0105530000, 0.0147886000, 0.0238580000, 0.0432094000, 0.0846330000", \ - "0.0076191000, 0.0085459000, 0.0105586000, 0.0148131000, 0.0238922000, 0.0432442000, 0.0846119000", \ - "0.0077043000, 0.0085892000, 0.0105280000, 0.0147907000, 0.0240332000, 0.0433940000, 0.0848524000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0017681000, 0.0009836000, -0.000815200, -0.004909200, -0.013965100, -0.033486000, -0.075431500", \ - "0.0016983000, 0.0009087000, -0.000890300, -0.004988500, -0.014027200, -0.033560300, -0.075500200", \ - "0.0017512000, 0.0009679000, -0.000824600, -0.004918000, -0.013946400, -0.033479500, -0.075417400", \ - "0.0015364000, 0.0007426000, -0.001051900, -0.005145900, -0.014162200, -0.033668200, -0.075600400", \ - "0.0011960000, 0.0004114000, -0.001364100, -0.005387300, -0.014344800, -0.033810800, -0.075727100", \ - "0.0011572000, 0.0002696000, -0.001623500, -0.005753200, -0.014600600, -0.033953800, -0.075803900", \ - "0.0014092000, 0.0005042000, -0.001382200, -0.005566100, -0.014446400, -0.033826000, -0.075649200"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010718840, 0.0022978700, 0.0049261010, 0.0105604200, 0.0226390800, 0.0485329300"); - values("0.0074271000, 0.0083828000, 0.0103867000, 0.0146261000, 0.0236164000, 0.0428907000, 0.0842059000", \ - "0.0073844000, 0.0083380000, 0.0103362000, 0.0145824000, 0.0235963000, 0.0428813000, 0.0842196000", \ - "0.0073250000, 0.0082745000, 0.0102982000, 0.0145538000, 0.0236102000, 0.0429194000, 0.0841929000", \ - "0.0069937000, 0.0079384000, 0.0099606000, 0.0142474000, 0.0233441000, 0.0427123000, 0.0841207000", \ - "0.0067295000, 0.0076203000, 0.0096263000, 0.0139108000, 0.0230449000, 0.0424294000, 0.0838575000", \ - "0.0067775000, 0.0077078000, 0.0095981000, 0.0138214000, 0.0228822000, 0.0423295000, 0.0837756000", \ - "0.0069950000, 0.0079289000, 0.0098299000, 0.0140763000, 0.0230269000, 0.0424518000, 0.0838925000"); - } - } - max_capacitance : 0.0485330000; - max_transition : 1.4866620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0380728000, 0.0436839000, 0.0549947000, 0.0784996000, 0.1271163000, 0.2300324000, 0.4489907000", \ - "0.0420554000, 0.0476385000, 0.0590898000, 0.0825841000, 0.1313533000, 0.2341154000, 0.4532756000", \ - "0.0520687000, 0.0575908000, 0.0689514000, 0.0925483000, 0.1413230000, 0.2442983000, 0.4633447000", \ - "0.0731726000, 0.0798639000, 0.0931035000, 0.1168375000, 0.1654529000, 0.2683382000, 0.4875468000", \ - "0.0995769000, 0.1099245000, 0.1296271000, 0.1639902000, 0.2216933000, 0.3238351000, 0.5416854000", \ - "0.1266286000, 0.1421934000, 0.1718745000, 0.2241017000, 0.3115685000, 0.4497199000, 0.6693294000", \ - "0.1349786000, 0.1586241000, 0.2042677000, 0.2847614000, 0.4181582000, 0.6288214000, 0.9493768000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0844585000, 0.0971248000, 0.1234543000, 0.1788296000, 0.2975220000, 0.5480036000, 1.0912204000", \ - "0.0886343000, 0.1014374000, 0.1282234000, 0.1850547000, 0.3040969000, 0.5550640000, 1.0986925000", \ - "0.1005545000, 0.1130881000, 0.1398718000, 0.1960722000, 0.3149302000, 0.5665715000, 1.1045977000", \ - "0.1288126000, 0.1410806000, 0.1675881000, 0.2234891000, 0.3423327000, 0.5949732000, 1.1336638000", \ - "0.1818921000, 0.1974865000, 0.2273259000, 0.2842611000, 0.4048522000, 0.6590721000, 1.1982662000", \ - "0.2673328000, 0.2912838000, 0.3327165000, 0.4098335000, 0.5424903000, 0.7966502000, 1.3389720000", \ - "0.3956782000, 0.4334945000, 0.5019031000, 0.6172405000, 0.8048897000, 1.1172651000, 1.6620432000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0344051000, 0.0406669000, 0.0545888000, 0.0841045000, 0.1473799000, 0.2843287000, 0.5780217000", \ - "0.0340644000, 0.0404794000, 0.0543033000, 0.0840516000, 0.1475246000, 0.2834009000, 0.5768296000", \ - "0.0345846000, 0.0406179000, 0.0539941000, 0.0838667000, 0.1475950000, 0.2835076000, 0.5769769000", \ - "0.0462305000, 0.0518554000, 0.0623484000, 0.0876871000, 0.1478961000, 0.2836730000, 0.5761603000", \ - "0.0705862000, 0.0784967000, 0.0937033000, 0.1201037000, 0.1679439000, 0.2890042000, 0.5758195000", \ - "0.1140174000, 0.1257207000, 0.1469030000, 0.1844742000, 0.2489523000, 0.3520940000, 0.5990584000", \ - "0.1912445000, 0.2114401000, 0.2412551000, 0.2983874000, 0.3874887000, 0.5322461000, 0.7628532000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0610721000, 0.0774068000, 0.1129036000, 0.1882740000, 0.3504240000, 0.6961107000, 1.4495286000", \ - "0.0611074000, 0.0776131000, 0.1131556000, 0.1887556000, 0.3525268000, 0.6963532000, 1.4482049000", \ - "0.0610945000, 0.0776244000, 0.1129814000, 0.1884114000, 0.3497085000, 0.6952583000, 1.4389513000", \ - "0.0619329000, 0.0780707000, 0.1131920000, 0.1881531000, 0.3495787000, 0.6963715000, 1.4393192000", \ - "0.0797155000, 0.0941781000, 0.1238460000, 0.1931400000, 0.3509696000, 0.7004834000, 1.4367931000", \ - "0.1211453000, 0.1385961000, 0.1718322000, 0.2397355000, 0.3748651000, 0.6995122000, 1.4425864000", \ - "0.2098579000, 0.2315663000, 0.2737357000, 0.3519741000, 0.4979572000, 0.7810839000, 1.4509470000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0410231000, 0.0465025000, 0.0578176000, 0.0812421000, 0.1300287000, 0.2328068000, 0.4520348000", \ - "0.0453774000, 0.0508894000, 0.0622205000, 0.0856582000, 0.1343975000, 0.2372064000, 0.4562745000", \ - "0.0548483000, 0.0603503000, 0.0717323000, 0.0953039000, 0.1441086000, 0.2470198000, 0.4662951000", \ - "0.0745037000, 0.0807491000, 0.0931350000, 0.1174457000, 0.1664249000, 0.2694109000, 0.4886984000", \ - "0.1042357000, 0.1131815000, 0.1302763000, 0.1612136000, 0.2159852000, 0.3206653000, 0.5410521000", \ - "0.1397837000, 0.1537231000, 0.1795772000, 0.2260462000, 0.3032155000, 0.4311347000, 0.6606466000", \ - "0.1667142000, 0.1885417000, 0.2293992000, 0.3021382000, 0.4222208000, 0.6101458000, 0.9019249000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0977039000, 0.1100000000, 0.1363577000, 0.1921653000, 0.3106705000, 0.5648842000, 1.1088773000", \ - "0.1027906000, 0.1151737000, 0.1416406000, 0.1974497000, 0.3163249000, 0.5702377000, 1.1139925000", \ - "0.1154068000, 0.1279108000, 0.1544714000, 0.2104805000, 0.3297756000, 0.5838454000, 1.1282243000", \ - "0.1427625000, 0.1551179000, 0.1815540000, 0.2376900000, 0.3570450000, 0.6119296000, 1.1559412000", \ - "0.1965809000, 0.2110438000, 0.2397360000, 0.2960589000, 0.4154644000, 0.6696694000, 1.2136102000", \ - "0.2849097000, 0.3043389000, 0.3430148000, 0.4155448000, 0.5474234000, 0.8026735000, 1.3468882000", \ - "0.4182072000, 0.4499495000, 0.5096495000, 0.6151260000, 0.7964172000, 1.1016603000, 1.6545331000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0340717000, 0.0405737000, 0.0545059000, 0.0840954000, 0.1477981000, 0.2836278000, 0.5765145000", \ - "0.0339450000, 0.0404977000, 0.0543712000, 0.0838958000, 0.1476470000, 0.2848175000, 0.5761022000", \ - "0.0342261000, 0.0405756000, 0.0541088000, 0.0839370000, 0.1474561000, 0.2844782000, 0.5763597000", \ - "0.0413516000, 0.0467419000, 0.0586686000, 0.0861394000, 0.1476366000, 0.2845061000, 0.5762621000", \ - "0.0607747000, 0.0674577000, 0.0810331000, 0.1066605000, 0.1604782000, 0.2866819000, 0.5765491000", \ - "0.0991735000, 0.1083830000, 0.1254530000, 0.1592366000, 0.2150957000, 0.3274217000, 0.5905277000", \ - "0.1678841000, 0.1818785000, 0.2073887000, 0.2522124000, 0.3288897000, 0.4583562000, 0.7001049000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0754835000, 0.0922899000, 0.1281990000, 0.2048346000, 0.3677645000, 0.7201539000, 1.4703121000", \ - "0.0755239000, 0.0922819000, 0.1281870000, 0.2044356000, 0.3680850000, 0.7174137000, 1.4687911000", \ - "0.0755056000, 0.0922769000, 0.1281567000, 0.2044994000, 0.3693833000, 0.7172168000, 1.4708099000", \ - "0.0760679000, 0.0924995000, 0.1282942000, 0.2043768000, 0.3677796000, 0.7207666000, 1.4709368000", \ - "0.0906992000, 0.1053543000, 0.1375351000, 0.2090323000, 0.3678459000, 0.7176532000, 1.4663372000", \ - "0.1307545000, 0.1477981000, 0.1819773000, 0.2500085000, 0.3920123000, 0.7216493000, 1.4658198000", \ - "0.2182698000, 0.2394242000, 0.2814058000, 0.3592483000, 0.5086029000, 0.7999399000, 1.4866618000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0878912000, 0.0927692000, 0.1018790000, 0.1181404000, 0.1488391000, 0.2101083000, 0.3397270000", \ - "0.0925467000, 0.0972583000, 0.1063142000, 0.1227086000, 0.1533730000, 0.2147691000, 0.3442618000", \ - "0.1049485000, 0.1096589000, 0.1188882000, 0.1351750000, 0.1657666000, 0.2271710000, 0.3566370000", \ - "0.1357703000, 0.1405978000, 0.1495512000, 0.1658948000, 0.1966687000, 0.2580408000, 0.3873993000", \ - "0.1968920000, 0.2023234000, 0.2121655000, 0.2295363000, 0.2612162000, 0.3231167000, 0.4521309000", \ - "0.2909812000, 0.2975337000, 0.3094777000, 0.3297477000, 0.3641598000, 0.4276447000, 0.5568624000", \ - "0.4368098000, 0.4454985000, 0.4611379000, 0.4859057000, 0.5261457000, 0.5917528000, 0.7232122000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.1017047000, 0.1142952000, 0.1409814000, 0.1968666000, 0.3152343000, 0.5683885000, 1.1116751000", \ - "0.1063398000, 0.1190273000, 0.1456452000, 0.2016249000, 0.3201995000, 0.5736860000, 1.1160926000", \ - "0.1161260000, 0.1289081000, 0.1557228000, 0.2121939000, 0.3313841000, 0.5851859000, 1.1280872000", \ - "0.1345487000, 0.1472205000, 0.1739941000, 0.2304545000, 0.3501129000, 0.6043053000, 1.1474611000", \ - "0.1601504000, 0.1722023000, 0.1988374000, 0.2553172000, 0.3750730000, 0.6295747000, 1.1738456000", \ - "0.1899582000, 0.2023720000, 0.2285967000, 0.2841106000, 0.4036936000, 0.6581946000, 1.2021178000", \ - "0.2122404000, 0.2249641000, 0.2500209000, 0.3050102000, 0.4239600000, 0.6786284000, 1.2228754000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0287825000, 0.0322559000, 0.0397382000, 0.0555699000, 0.0902998000, 0.1671723000, 0.3366649000", \ - "0.0287287000, 0.0322167000, 0.0397128000, 0.0557388000, 0.0901777000, 0.1670355000, 0.3371619000", \ - "0.0287066000, 0.0322132000, 0.0396848000, 0.0555629000, 0.0901200000, 0.1670494000, 0.3370855000", \ - "0.0290892000, 0.0325477000, 0.0399426000, 0.0557422000, 0.0900818000, 0.1672317000, 0.3370142000", \ - "0.0345747000, 0.0376556000, 0.0444741000, 0.0593478000, 0.0926681000, 0.1679763000, 0.3371922000", \ - "0.0470384000, 0.0498026000, 0.0558171000, 0.0692770000, 0.1007599000, 0.1734718000, 0.3396304000", \ - "0.0663410000, 0.0692849000, 0.0757076000, 0.0886149000, 0.1167695000, 0.1836810000, 0.3436784000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010718800, 0.0022978700, 0.0049261000, 0.0105604000, 0.0226391000, 0.0485329000"); - values("0.0753173000, 0.0921843000, 0.1281250000, 0.2048333000, 0.3679541000, 0.7177886000, 1.4701753000", \ - "0.0753254000, 0.0921222000, 0.1281050000, 0.2043851000, 0.3677908000, 0.7170343000, 1.4658476000", \ - "0.0752279000, 0.0921869000, 0.1281775000, 0.2045257000, 0.3678929000, 0.7175171000, 1.4652153000", \ - "0.0752296000, 0.0920317000, 0.1280089000, 0.2044437000, 0.3678319000, 0.7175992000, 1.4648384000", \ - "0.0751789000, 0.0918488000, 0.1284889000, 0.2044096000, 0.3677683000, 0.7177138000, 1.4652152000", \ - "0.0769907000, 0.0933366000, 0.1285936000, 0.2048275000, 0.3683951000, 0.7180954000, 1.4665755000", \ - "0.0855903000, 0.1001521000, 0.1335783000, 0.2067587000, 0.3690151000, 0.7184118000, 1.4665419000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21boi_1") { - leakage_power () { - value : 0.0027114000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0032627000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0031220000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0032627000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0029362000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0032627000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0050082000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0006645000; - when : "A1&A2&!B1_N"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__a21boi"; - cell_leakage_power : 0.0030288050; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041267000, 0.0041251000, 0.0041216000, 0.0041229000, 0.0041260000, 0.0041331000, 0.0041495000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004131300, -0.004127900, -0.004120000, -0.004119200, -0.004117300, -0.004113000, -0.004103000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024040000; - } - pin ("A2") { - capacitance : 0.0023130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022100000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040280000, 0.0040268000, 0.0040240000, 0.0040249000, 0.0040269000, 0.0040315000, 0.0040421000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004025300, -0.004024000, -0.004020900, -0.004021800, -0.004023700, -0.004028200, -0.004038400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024150000; - } - pin ("B1_N") { - capacitance : 0.0016370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090481000, 0.0089414000, 0.0086954000, 0.0087645000, 0.0089240000, 0.0092914000, 0.0101384000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016298000, 0.0015630000, 0.0014090000, 0.0014749000, 0.0016270000, 0.0019777000, 0.0027858000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017060000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&B1_N) | (!A2&B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0050423000, 0.0040060000, 0.0015848000, -0.003993800, -0.017024700, -0.047157200, -0.116884600", \ - "0.0048788000, 0.0038535000, 0.0014602000, -0.004129900, -0.017105200, -0.047216600, -0.116969700", \ - "0.0046529000, 0.0036387000, 0.0012650000, -0.004271000, -0.017210000, -0.047295200, -0.117048600", \ - "0.0044409000, 0.0034541000, 0.0011002000, -0.004421600, -0.017341800, -0.047398700, -0.117102400", \ - "0.0044676000, 0.0034228000, 0.0010343000, -0.004512500, -0.017466800, -0.047517700, -0.117152200", \ - "0.0049771000, 0.0038997000, 0.0013947000, -0.004303400, -0.017458500, -0.047416600, -0.117095000", \ - "0.0064644000, 0.0053381000, 0.0027271000, -0.003106700, -0.016344200, -0.046870300, -0.116925800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0080050000, 0.0091491000, 0.0116955000, 0.0174492000, 0.0305842000, 0.0604860000, 0.1290175000", \ - "0.0077563000, 0.0089124000, 0.0114702000, 0.0172194000, 0.0302726000, 0.0601802000, 0.1300896000", \ - "0.0075455000, 0.0086644000, 0.0112135000, 0.0169683000, 0.0300680000, 0.0600514000, 0.1290373000", \ - "0.0074136000, 0.0085018000, 0.0109937000, 0.0166978000, 0.0298989000, 0.0600949000, 0.1289103000", \ - "0.0072924000, 0.0083683000, 0.0108750000, 0.0164993000, 0.0296534000, 0.0595856000, 0.1290406000", \ - "0.0072222000, 0.0083475000, 0.0107975000, 0.0165469000, 0.0295681000, 0.0597751000, 0.1284183000", \ - "0.0075829000, 0.0085705000, 0.0109183000, 0.0164055000, 0.0297212000, 0.0595956000, 0.1289683000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0048520000, 0.0038000000, 0.0013818000, -0.004226600, -0.017214800, -0.047386000, -0.117087500", \ - "0.0047286000, 0.0036792000, 0.0012592000, -0.004323900, -0.017337800, -0.047460600, -0.117217400", \ - "0.0045543000, 0.0035248000, 0.0011276000, -0.004450500, -0.017412200, -0.047554100, -0.117271000", \ - "0.0043598000, 0.0033421000, 0.0009718000, -0.004561400, -0.017514000, -0.047604400, -0.117331500", \ - "0.0044409000, 0.0034096000, 0.0009375000, -0.004689000, -0.017582600, -0.047626500, -0.117320300", \ - "0.0046277000, 0.0035817000, 0.0011093000, -0.004561100, -0.017679300, -0.047756500, -0.117383500", \ - "0.0057156000, 0.0046139000, 0.0020514000, -0.003770700, -0.016996000, -0.047393700, -0.117283200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0107565000, 0.0118236000, 0.0142872000, 0.0199050000, 0.0328765000, 0.0627459000, 0.1315772000", \ - "0.0106184000, 0.0116879000, 0.0141659000, 0.0198288000, 0.0328176000, 0.0627004000, 0.1315609000", \ - "0.0104752000, 0.0115573000, 0.0140427000, 0.0197174000, 0.0327389000, 0.0626589000, 0.1316017000", \ - "0.0103647000, 0.0114439000, 0.0138997000, 0.0195790000, 0.0326086000, 0.0625309000, 0.1314706000", \ - "0.0102688000, 0.0113600000, 0.0137931000, 0.0194625000, 0.0324513000, 0.0623850000, 0.1312863000", \ - "0.0102165000, 0.0113000000, 0.0137623000, 0.0194167000, 0.0324960000, 0.0624170000, 0.1311391000", \ - "0.0105574000, 0.0115611000, 0.0139230000, 0.0194127000, 0.0326522000, 0.0627176000, 0.1314768000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0021901000, 0.0013506000, -0.000728900, -0.005941700, -0.018708600, -0.048772500, -0.118567100", \ - "0.0021019000, 0.0012855000, -0.000803800, -0.006022300, -0.018786400, -0.048855700, -0.118618600", \ - "0.0021693000, 0.0013121000, -0.000780300, -0.005984000, -0.018717200, -0.048770700, -0.118529700", \ - "0.0019360000, 0.0010723000, -0.001034800, -0.006247000, -0.018972300, -0.049008700, -0.118754600", \ - "0.0016154000, 0.0007096000, -0.001398900, -0.006597100, -0.019253200, -0.049205500, -0.118878000", \ - "0.0019112000, 0.0008985000, -0.001478400, -0.006988400, -0.019374700, -0.049143900, -0.118730100", \ - "0.0024175000, 0.0013540000, -0.001237000, -0.006783900, -0.019625300, -0.049457700, -0.118732500"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0100263000, 0.0111324000, 0.0136440000, 0.0193477000, 0.0323375000, 0.0621052000, 0.1310365000", \ - "0.0099885000, 0.0110813000, 0.0135895000, 0.0192928000, 0.0322947000, 0.0621604000, 0.1310135000", \ - "0.0099664000, 0.0110591000, 0.0135681000, 0.0192934000, 0.0323424000, 0.0622165000, 0.1310117000", \ - "0.0096286000, 0.0107244000, 0.0132231000, 0.0189449000, 0.0320165000, 0.0619071000, 0.1308660000", \ - "0.0093554000, 0.0104511000, 0.0129346000, 0.0186494000, 0.0316977000, 0.0617391000, 0.1306356000", \ - "0.0093974000, 0.0105279000, 0.0128570000, 0.0184490000, 0.0314551000, 0.0614840000, 0.1304442000", \ - "0.0097488000, 0.0108826000, 0.0131717000, 0.0187666000, 0.0316493000, 0.0616695000, 0.1306257000"); - } - } - max_capacitance : 0.0759990000; - max_transition : 1.4968110000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0286314000, 0.0324302000, 0.0406985000, 0.0586481000, 0.0986375000, 0.1892330000, 0.3969397000", \ - "0.0326392000, 0.0363826000, 0.0446528000, 0.0627652000, 0.1027321000, 0.1934526000, 0.4010819000", \ - "0.0429112000, 0.0465626000, 0.0546404000, 0.0726402000, 0.1127336000, 0.2034632000, 0.4116073000", \ - "0.0600491000, 0.0650307000, 0.0761956000, 0.0967479000, 0.1367116000, 0.2269881000, 0.4349057000", \ - "0.0784634000, 0.0868162000, 0.1032616000, 0.1341583000, 0.1885015000, 0.2827479000, 0.4902260000", \ - "0.0920935000, 0.1042548000, 0.1293009000, 0.1759102000, 0.2597093000, 0.3935706000, 0.6175185000", \ - "0.0748052000, 0.0938442000, 0.1319301000, 0.2042021000, 0.3312326000, 0.5401983000, 0.8709030000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0703764000, 0.0797354000, 0.1008142000, 0.1483832000, 0.2564648000, 0.5035691000, 1.0708699000", \ - "0.0747834000, 0.0842060000, 0.1055881000, 0.1529693000, 0.2607137000, 0.5074068000, 1.0834390000", \ - "0.0870595000, 0.0964567000, 0.1173927000, 0.1655141000, 0.2743707000, 0.5212880000, 1.0900350000", \ - "0.1151027000, 0.1243498000, 0.1453011000, 0.1927891000, 0.3017981000, 0.5510545000, 1.1192141000", \ - "0.1650451000, 0.1773004000, 0.2030645000, 0.2542456000, 0.3627936000, 0.6102671000, 1.1846955000", \ - "0.2441360000, 0.2634792000, 0.3017223000, 0.3736605000, 0.5035733000, 0.7539866000, 1.3267900000", \ - "0.3675479000, 0.3984079000, 0.4600411000, 0.5706161000, 0.7602604000, 1.0753264000, 1.6563294000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0252221000, 0.0293731000, 0.0391854000, 0.0614410000, 0.1130621000, 0.2330409000, 0.5090198000", \ - "0.0246559000, 0.0290614000, 0.0390025000, 0.0613026000, 0.1128446000, 0.2332281000, 0.5097608000", \ - "0.0268890000, 0.0305204000, 0.0394982000, 0.0611200000, 0.1130278000, 0.2331233000, 0.5088063000", \ - "0.0388130000, 0.0433606000, 0.0522103000, 0.0688176000, 0.1148664000, 0.2322536000, 0.5085055000", \ - "0.0611538000, 0.0666168000, 0.0789123000, 0.1026836000, 0.1427223000, 0.2429025000, 0.5090703000", \ - "0.0991270000, 0.1084865000, 0.1268896000, 0.1607493000, 0.2198245000, 0.3215397000, 0.5397053000", \ - "0.1685562000, 0.1830335000, 0.2133166000, 0.2634162000, 0.3513549000, 0.4920926000, 0.7232635000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0471880000, 0.0590867000, 0.0870247000, 0.1509624000, 0.2986901000, 0.6355283000, 1.4101017000", \ - "0.0472957000, 0.0592328000, 0.0869464000, 0.1502435000, 0.2970047000, 0.6337273000, 1.4217010000", \ - "0.0473308000, 0.0592676000, 0.0870124000, 0.1503343000, 0.2964966000, 0.6328763000, 1.4177663000", \ - "0.0495296000, 0.0608757000, 0.0871891000, 0.1504989000, 0.2973358000, 0.6352483000, 1.4129744000", \ - "0.0677207000, 0.0788339000, 0.1029776000, 0.1582908000, 0.2977156000, 0.6343313000, 1.4162862000", \ - "0.1084207000, 0.1215386000, 0.1493190000, 0.2074032000, 0.3293028000, 0.6414553000, 1.4122620000", \ - "0.1925291000, 0.2094547000, 0.2454077000, 0.3163195000, 0.4546993000, 0.7317041000, 1.4321130000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0327580000, 0.0365138000, 0.0446815000, 0.0627467000, 0.1027020000, 0.1932503000, 0.4009660000", \ - "0.0370563000, 0.0408468000, 0.0490536000, 0.0670420000, 0.1070657000, 0.1977101000, 0.4054105000", \ - "0.0467410000, 0.0504578000, 0.0586398000, 0.0767111000, 0.1168638000, 0.2073833000, 0.4157629000", \ - "0.0640835000, 0.0687075000, 0.0786387000, 0.0984988000, 0.1390353000, 0.2299866000, 0.4378583000", \ - "0.0877770000, 0.0946660000, 0.1089133000, 0.1362576000, 0.1864249000, 0.2811501000, 0.4900447000", \ - "0.1104604000, 0.1212924000, 0.1437344000, 0.1859619000, 0.2601586000, 0.3849716000, 0.6094580000", \ - "0.1142102000, 0.1311980000, 0.1664401000, 0.2333302000, 0.3499028000, 0.5383019000, 0.8396543000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0879684000, 0.0973090000, 0.1186112000, 0.1669662000, 0.2776871000, 0.5323659000, 1.1200265000", \ - "0.0929933000, 0.1023616000, 0.1238323000, 0.1724301000, 0.2833117000, 0.5382576000, 1.1261535000", \ - "0.1055824000, 0.1148072000, 0.1363608000, 0.1851543000, 0.2962952000, 0.5514624000, 1.1392542000", \ - "0.1322536000, 0.1416165000, 0.1629274000, 0.2117047000, 0.3229735000, 0.5784316000, 1.1676855000", \ - "0.1830166000, 0.1945276000, 0.2187363000, 0.2693021000, 0.3806309000, 0.6361501000, 1.2254404000", \ - "0.2662526000, 0.2825062000, 0.3152714000, 0.3822673000, 0.5107436000, 0.7691310000, 1.3597139000", \ - "0.3955718000, 0.4206906000, 0.4726520000, 0.5709205000, 0.7483076000, 1.0662774000, 1.6660743000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0251415000, 0.0292992000, 0.0391243000, 0.0613605000, 0.1131532000, 0.2331079000, 0.5085240000", \ - "0.0249174000, 0.0292697000, 0.0389800000, 0.0613904000, 0.1131202000, 0.2330774000, 0.5103144000", \ - "0.0258113000, 0.0297803000, 0.0391493000, 0.0612104000, 0.1130871000, 0.2329969000, 0.5091929000", \ - "0.0341233000, 0.0382640000, 0.0467515000, 0.0655571000, 0.1139170000, 0.2323328000, 0.5094178000", \ - "0.0532552000, 0.0585877000, 0.0680362000, 0.0887029000, 0.1315916000, 0.2393282000, 0.5098066000", \ - "0.0885664000, 0.0954548000, 0.1099757000, 0.1376755000, 0.1893772000, 0.2895592000, 0.5279579000", \ - "0.1525619000, 0.1631473000, 0.1853656000, 0.2266645000, 0.2983198000, 0.4233194000, 0.6509507000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0635228000, 0.0760484000, 0.1048000000, 0.1707510000, 0.3221727000, 0.6713102000, 1.4781248000", \ - "0.0635569000, 0.0761005000, 0.1048923000, 0.1708066000, 0.3228402000, 0.6732854000, 1.4771641000", \ - "0.0635816000, 0.0760239000, 0.1047803000, 0.1710330000, 0.3222738000, 0.6709657000, 1.4765522000", \ - "0.0646490000, 0.0767055000, 0.1050241000, 0.1708111000, 0.3224643000, 0.6714679000, 1.4796431000", \ - "0.0801867000, 0.0919787000, 0.1172827000, 0.1770906000, 0.3233015000, 0.6729493000, 1.4820776000", \ - "0.1193032000, 0.1322247000, 0.1610518000, 0.2209169000, 0.3508806000, 0.6773674000, 1.4826207000", \ - "0.2013820000, 0.2179039000, 0.2539433000, 0.3247953000, 0.4667459000, 0.7626181000, 1.4968113000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0958336000, 0.1002087000, 0.1086276000, 0.1244578000, 0.1540351000, 0.2142631000, 0.3480492000", \ - "0.1002669000, 0.1048472000, 0.1131798000, 0.1289162000, 0.1584914000, 0.2185841000, 0.3524006000", \ - "0.1128745000, 0.1172121000, 0.1254983000, 0.1410273000, 0.1710642000, 0.2312291000, 0.3649300000", \ - "0.1436606000, 0.1480046000, 0.1564462000, 0.1724594000, 0.2019123000, 0.2621345000, 0.3959252000", \ - "0.2087771000, 0.2134616000, 0.2225862000, 0.2392792000, 0.2696709000, 0.3303955000, 0.4642367000", \ - "0.3113038000, 0.3172968000, 0.3285153000, 0.3482965000, 0.3826232000, 0.4456041000, 0.5791154000", \ - "0.4688911000, 0.4766018000, 0.4909666000, 0.5164303000, 0.5577638000, 0.6248897000, 0.7610104000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0973592000, 0.1070514000, 0.1287997000, 0.1778348000, 0.2888080000, 0.5437322000, 1.1310821000", \ - "0.1021448000, 0.1117298000, 0.1334838000, 0.1824670000, 0.2936252000, 0.5486688000, 1.1360402000", \ - "0.1131935000, 0.1226610000, 0.1444738000, 0.1935542000, 0.3049918000, 0.5604037000, 1.1493226000", \ - "0.1340321000, 0.1436116000, 0.1652343000, 0.2143304000, 0.3260950000, 0.5819432000, 1.1700525000", \ - "0.1638662000, 0.1736819000, 0.1953162000, 0.2445696000, 0.3561033000, 0.6117835000, 1.2002171000", \ - "0.2007568000, 0.2099045000, 0.2312050000, 0.2792338000, 0.3906745000, 0.6463801000, 1.2355974000", \ - "0.2336653000, 0.2433324000, 0.2642224000, 0.3117474000, 0.4223670000, 0.6781971000, 1.2664813000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0300790000, 0.0323149000, 0.0379153000, 0.0508355000, 0.0808023000, 0.1530163000, 0.3262580000", \ - "0.0300057000, 0.0322739000, 0.0378054000, 0.0508570000, 0.0809256000, 0.1528126000, 0.3264835000", \ - "0.0300486000, 0.0323119000, 0.0379151000, 0.0509013000, 0.0808110000, 0.1530055000, 0.3265462000", \ - "0.0301534000, 0.0324618000, 0.0380187000, 0.0509007000, 0.0808597000, 0.1529567000, 0.3266794000", \ - "0.0354267000, 0.0374303000, 0.0424432000, 0.0542620000, 0.0829222000, 0.1536646000, 0.3272019000", \ - "0.0496101000, 0.0513522000, 0.0557038000, 0.0664105000, 0.0929709000, 0.1606824000, 0.3295607000", \ - "0.0710240000, 0.0731049000, 0.0780799000, 0.0890316000, 0.1131121000, 0.1753839000, 0.3358520000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0633113000, 0.0759247000, 0.1048491000, 0.1710819000, 0.3227970000, 0.6739629000, 1.4769169000", \ - "0.0632364000, 0.0759438000, 0.1048348000, 0.1707954000, 0.3224223000, 0.6719812000, 1.4766151000", \ - "0.0633093000, 0.0759189000, 0.1047306000, 0.1708755000, 0.3222902000, 0.6720474000, 1.4826764000", \ - "0.0633578000, 0.0758126000, 0.1047175000, 0.1707270000, 0.3228385000, 0.6736797000, 1.4815925000", \ - "0.0642473000, 0.0765346000, 0.1055141000, 0.1712109000, 0.3228055000, 0.6729032000, 1.4766846000", \ - "0.0672141000, 0.0788178000, 0.1067928000, 0.1719607000, 0.3232994000, 0.6725543000, 1.4816691000", \ - "0.0777082000, 0.0887088000, 0.1139714000, 0.1747231000, 0.3245355000, 0.6748661000, 1.4789212000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21boi_2") { - leakage_power () { - value : 0.0033877000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0035737000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0043240000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0035736000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0040067000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0035737000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0049842000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0007049000; - when : "A1&A2&!B1_N"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a21boi"; - cell_leakage_power : 0.0035160600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075831000, 0.0075785000, 0.0075678000, 0.0075710000, 0.0075784000, 0.0075953000, 0.0076344000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007571600, -0.007567400, -0.007557600, -0.007554800, -0.007548200, -0.007532900, -0.007497900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046050000; - } - pin ("A2") { - capacitance : 0.0047950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082955000, 0.0082926000, 0.0082858000, 0.0082827000, 0.0082756000, 0.0082592000, 0.0082215000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008304800, -0.008297600, -0.008280900, -0.008281200, -0.008281800, -0.008283300, -0.008286700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050170000; - } - pin ("B1_N") { - capacitance : 0.0015470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0119640000, 0.0118624000, 0.0116282000, 0.0116949000, 0.0118486000, 0.0122030000, 0.0130199000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038520000, 0.0037982000, 0.0036741000, 0.0037475000, 0.0039168000, 0.0043070000, 0.0052065000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016110000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&B1_N) | (!A2&B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0088744000, 0.0076572000, 0.0045942000, -0.003176700, -0.022858400, -0.072685100, -0.198761400", \ - "0.0085995000, 0.0073903000, 0.0043278000, -0.003406000, -0.023023400, -0.072879300, -0.198898800", \ - "0.0082392000, 0.0070326000, 0.0039874000, -0.003677300, -0.023284200, -0.073043000, -0.199107700", \ - "0.0077457000, 0.0066002000, 0.0036377000, -0.003974300, -0.023505100, -0.073192200, -0.199175300", \ - "0.0077702000, 0.0066402000, 0.0036240000, -0.004117000, -0.023634300, -0.073381300, -0.199360800", \ - "0.0090662000, 0.0078061000, 0.0043193000, -0.003639100, -0.023425600, -0.073265400, -0.199217200", \ - "0.0113386000, 0.0099571000, 0.0067718000, -0.001531300, -0.021715700, -0.072262500, -0.198965100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0138701000, 0.0152259000, 0.0185664000, 0.0266086000, 0.0463721000, 0.0960930000, 0.2212602000", \ - "0.0134349000, 0.0147855000, 0.0181120000, 0.0262742000, 0.0461779000, 0.0958178000, 0.2205624000", \ - "0.0131156000, 0.0144094000, 0.0176602000, 0.0257530000, 0.0458059000, 0.0963537000, 0.2204978000", \ - "0.0129123000, 0.0141700000, 0.0173704000, 0.0253643000, 0.0452692000, 0.0952203000, 0.2209403000", \ - "0.0127152000, 0.0139939000, 0.0171472000, 0.0249736000, 0.0448420000, 0.0950004000, 0.2198124000", \ - "0.0126808000, 0.0139055000, 0.0170500000, 0.0249846000, 0.0446737000, 0.0946505000, 0.2192944000", \ - "0.0130159000, 0.0141727000, 0.0171728000, 0.0247902000, 0.0447967000, 0.0940349000, 0.2202726000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0095771000, 0.0083566000, 0.0052681000, -0.002509300, -0.022165600, -0.072004500, -0.198060600", \ - "0.0092874000, 0.0080826000, 0.0050070000, -0.002730600, -0.022382500, -0.072222200, -0.198264300", \ - "0.0088969000, 0.0077026000, 0.0046758000, -0.003046000, -0.022628000, -0.072428900, -0.198472400", \ - "0.0084093000, 0.0072405000, 0.0042781000, -0.003318600, -0.022862900, -0.072602000, -0.198603500", \ - "0.0085281000, 0.0073493000, 0.0042521000, -0.003696000, -0.023088400, -0.072643400, -0.198610900", \ - "0.0088318000, 0.0076139000, 0.0044830000, -0.003317700, -0.023112700, -0.072886300, -0.198793500", \ - "0.0107900000, 0.0095376000, 0.0062477000, -0.001902400, -0.021993200, -0.072343600, -0.198654500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0190900000, 0.0203316000, 0.0234914000, 0.0313479000, 0.0510570000, 0.1004738000, 0.2251018000", \ - "0.0187807000, 0.0200308000, 0.0232127000, 0.0311229000, 0.0509361000, 0.1003600000, 0.2249567000", \ - "0.0185069000, 0.0197370000, 0.0228966000, 0.0308636000, 0.0506725000, 0.1002713000, 0.2249128000", \ - "0.0182528000, 0.0195153000, 0.0226513000, 0.0305479000, 0.0503841000, 0.1000133000, 0.2247574000", \ - "0.0180503000, 0.0193527000, 0.0224722000, 0.0303026000, 0.0500381000, 0.0997670000, 0.2245815000", \ - "0.0180233000, 0.0192587000, 0.0224081000, 0.0303590000, 0.0500808000, 0.0997411000, 0.2242913000", \ - "0.0183493000, 0.0195806000, 0.0225898000, 0.0301880000, 0.0502617000, 0.1001033000, 0.2248905000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0022155000, 0.0012214000, -0.001266800, -0.008186100, -0.027028900, -0.076461700, -0.202475900", \ - "0.0021889000, 0.0011580000, -0.001402700, -0.008292200, -0.027049300, -0.076487400, -0.202501100", \ - "0.0022419000, 0.0012165000, -0.001331700, -0.008238800, -0.026968800, -0.076415300, -0.202418000", \ - "0.0020057000, 0.0009612000, -0.001645700, -0.008567200, -0.027307900, -0.076663800, -0.202651800", \ - "0.0017452000, 0.0006801000, -0.001984600, -0.009010300, -0.027766100, -0.077037700, -0.202925200", \ - "0.0021857000, 0.0009353000, -0.002154900, -0.009847300, -0.028279400, -0.077401800, -0.203178100", \ - "0.0043345000, 0.0030249000, -0.000158300, -0.007914200, -0.028227300, -0.077727400, -0.203302800"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0165644000, 0.0178531000, 0.0210044000, 0.0290119000, 0.0488816000, 0.0984471000, 0.2231286000", \ - "0.0165285000, 0.0177956000, 0.0210079000, 0.0290289000, 0.0488967000, 0.0984580000, 0.2230328000", \ - "0.0165461000, 0.0178404000, 0.0210252000, 0.0290424000, 0.0488807000, 0.0985285000, 0.2231360000", \ - "0.0162108000, 0.0174882000, 0.0206740000, 0.0286405000, 0.0485216000, 0.0982352000, 0.2228706000", \ - "0.0159768000, 0.0172294000, 0.0203839000, 0.0281966000, 0.0480548000, 0.0978088000, 0.2229995000", \ - "0.0160736000, 0.0173207000, 0.0203199000, 0.0279330000, 0.0477201000, 0.0975309000, 0.2223212000", \ - "0.0162854000, 0.0175278000, 0.0207182000, 0.0282639000, 0.0477271000, 0.0974830000, 0.2220772000"); - } - } - max_capacitance : 0.1290990000; - max_transition : 1.4912630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0228254000, 0.0252785000, 0.0309547000, 0.0441506000, 0.0751558000, 0.1502518000, 0.3374191000", \ - "0.0270001000, 0.0293867000, 0.0350489000, 0.0482021000, 0.0791435000, 0.1542483000, 0.3412206000", \ - "0.0374502000, 0.0398704000, 0.0454523000, 0.0582334000, 0.0890830000, 0.1642259000, 0.3512159000", \ - "0.0521334000, 0.0555480000, 0.0636208000, 0.0806112000, 0.1130407000, 0.1871044000, 0.3741573000", \ - "0.0669988000, 0.0720586000, 0.0843348000, 0.1096446000, 0.1576998000, 0.2430585000, 0.4294691000", \ - "0.0722394000, 0.0802534000, 0.0989663000, 0.1374343000, 0.2113645000, 0.3387375000, 0.5566891000", \ - "0.0395615000, 0.0525330000, 0.0806021000, 0.1403980000, 0.2540852000, 0.4534031000, 0.7827829000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0720932000, 0.0790281000, 0.0960600000, 0.1372009000, 0.2369119000, 0.4886331000, 1.1205994000", \ - "0.0762519000, 0.0831606000, 0.1001862000, 0.1415426000, 0.2422081000, 0.4925484000, 1.1219787000", \ - "0.0887831000, 0.0954697000, 0.1122221000, 0.1534774000, 0.2544416000, 0.5088683000, 1.1355222000", \ - "0.1166802000, 0.1235715000, 0.1400923000, 0.1809188000, 0.2814400000, 0.5332904000, 1.1765433000", \ - "0.1654051000, 0.1741221000, 0.1945713000, 0.2405631000, 0.3416246000, 0.5967803000, 1.2246718000", \ - "0.2445147000, 0.2579717000, 0.2877361000, 0.3512161000, 0.4757159000, 0.7323697000, 1.3632591000", \ - "0.3692634000, 0.3908641000, 0.4402013000, 0.5391094000, 0.7170148000, 1.0396656000, 1.6901064000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0220289000, 0.0244617000, 0.0306098000, 0.0460706000, 0.0848481000, 0.1836035000, 0.4345596000", \ - "0.0212378000, 0.0237299000, 0.0300996000, 0.0457330000, 0.0847083000, 0.1838419000, 0.4340297000", \ - "0.0246856000, 0.0266993000, 0.0318552000, 0.0460367000, 0.0843425000, 0.1834194000, 0.4351730000", \ - "0.0353278000, 0.0381407000, 0.0443532000, 0.0576003000, 0.0891807000, 0.1833634000, 0.4347028000", \ - "0.0550549000, 0.0597151000, 0.0683292000, 0.0873678000, 0.1226709000, 0.2002166000, 0.4348258000", \ - "0.0901286000, 0.0969930000, 0.1101248000, 0.1382718000, 0.1895423000, 0.2838327000, 0.4767564000", \ - "0.1522499000, 0.1625680000, 0.1849640000, 0.2282986000, 0.3067330000, 0.4391684000, 0.6658970000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0422970000, 0.0511012000, 0.0727935000, 0.1275666000, 0.2644673000, 0.6092562000, 1.4795348000", \ - "0.0423496000, 0.0511778000, 0.0729937000, 0.1274451000, 0.2645460000, 0.6094680000, 1.4775948000", \ - "0.0424740000, 0.0513049000, 0.0731210000, 0.1275537000, 0.2646710000, 0.6126452000, 1.4750802000", \ - "0.0445560000, 0.0527441000, 0.0735603000, 0.1279839000, 0.2644521000, 0.6097521000, 1.4845424000", \ - "0.0599483000, 0.0686668000, 0.0888828000, 0.1369743000, 0.2665726000, 0.6123630000, 1.4761435000", \ - "0.0951377000, 0.1050602000, 0.1287891000, 0.1806541000, 0.3003332000, 0.6167036000, 1.4799302000", \ - "0.1741313000, 0.1864420000, 0.2151657000, 0.2772233000, 0.4089481000, 0.6994965000, 1.4912627000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0278636000, 0.0303030000, 0.0359731000, 0.0491837000, 0.0800819000, 0.1551730000, 0.3420846000", \ - "0.0320849000, 0.0344961000, 0.0401934000, 0.0533643000, 0.0843495000, 0.1594697000, 0.3467359000", \ - "0.0414383000, 0.0439658000, 0.0496245000, 0.0627243000, 0.0936922000, 0.1688540000, 0.3561384000", \ - "0.0566684000, 0.0599635000, 0.0672325000, 0.0828064000, 0.1152372000, 0.1906268000, 0.3778984000", \ - "0.0753642000, 0.0799864000, 0.0909617000, 0.1129746000, 0.1564944000, 0.2404481000, 0.4282068000", \ - "0.0887210000, 0.0960847000, 0.1127823000, 0.1471832000, 0.2137585000, 0.3307934000, 0.5429021000", \ - "0.0725968000, 0.0836427000, 0.1091570000, 0.1647833000, 0.2690300000, 0.4500874000, 0.7486714000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0895834000, 0.0957657000, 0.1108257000, 0.1484459000, 0.2413359000, 0.4743275000, 1.0605515000", \ - "0.0943293000, 0.1003972000, 0.1157046000, 0.1536055000, 0.2468096000, 0.4801609000, 1.0667546000", \ - "0.1070996000, 0.1133245000, 0.1285996000, 0.1662453000, 0.2598974000, 0.4931894000, 1.0798504000", \ - "0.1352613000, 0.1414498000, 0.1564842000, 0.1942773000, 0.2878269000, 0.5214502000, 1.1082588000", \ - "0.1888959000, 0.1965622000, 0.2143448000, 0.2547297000, 0.3482811000, 0.5819691000, 1.1694891000", \ - "0.2787785000, 0.2891304000, 0.3146395000, 0.3694917000, 0.4824136000, 0.7214707000, 1.3094810000", \ - "0.4202208000, 0.4381098000, 0.4776337000, 0.5614280000, 0.7227495000, 1.0287542000, 1.6332399000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0219240000, 0.0243189000, 0.0304914000, 0.0459021000, 0.0847254000, 0.1835422000, 0.4344407000", \ - "0.0215692000, 0.0241048000, 0.0303479000, 0.0457511000, 0.0846366000, 0.1834964000, 0.4346590000", \ - "0.0231697000, 0.0253148000, 0.0309817000, 0.0458795000, 0.0845829000, 0.1837151000, 0.4345465000", \ - "0.0317859000, 0.0339274000, 0.0395277000, 0.0526395000, 0.0871446000, 0.1836343000, 0.4351973000", \ - "0.0495421000, 0.0528205000, 0.0594067000, 0.0747715000, 0.1091139000, 0.1941004000, 0.4348922000", \ - "0.0826666000, 0.0869565000, 0.0970859000, 0.1189350000, 0.1623781000, 0.2519231000, 0.4609472000", \ - "0.1418355000, 0.1491763000, 0.1652356000, 0.1987715000, 0.2613228000, 0.3769390000, 0.5971661000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0550640000, 0.0632982000, 0.0837626000, 0.1350718000, 0.2626442000, 0.5846156000, 1.3900158000", \ - "0.0550585000, 0.0632964000, 0.0838050000, 0.1349685000, 0.2627496000, 0.5830841000, 1.3930699000", \ - "0.0551475000, 0.0633776000, 0.0838563000, 0.1350721000, 0.2625490000, 0.5827196000, 1.3903616000", \ - "0.0557635000, 0.0639712000, 0.0841862000, 0.1351138000, 0.2633089000, 0.5827987000, 1.3883168000", \ - "0.0702421000, 0.0783548000, 0.0967049000, 0.1428025000, 0.2639957000, 0.5832269000, 1.3913701000", \ - "0.1059297000, 0.1149807000, 0.1365804000, 0.1860138000, 0.2960777000, 0.5916967000, 1.3928760000", \ - "0.1837942000, 0.1959161000, 0.2238237000, 0.2837348000, 0.4086222000, 0.6799982000, 1.4096460000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1220069000, 0.1254143000, 0.1334772000, 0.1489285000, 0.1776447000, 0.2338046000, 0.3587487000", \ - "0.1266728000, 0.1301713000, 0.1381857000, 0.1539354000, 0.1824878000, 0.2386495000, 0.3635165000", \ - "0.1389880000, 0.1427344000, 0.1507696000, 0.1662468000, 0.1949908000, 0.2511225000, 0.3759447000", \ - "0.1696245000, 0.1734004000, 0.1813296000, 0.1967385000, 0.2255536000, 0.2816291000, 0.4065690000", \ - "0.2409569000, 0.2447657000, 0.2526506000, 0.2683135000, 0.2972554000, 0.3537508000, 0.4784457000", \ - "0.3649632000, 0.3695546000, 0.3795628000, 0.3986487000, 0.4321188000, 0.4922392000, 0.6188425000", \ - "0.5560311000, 0.5621766000, 0.5746155000, 0.5991773000, 0.6409313000, 0.7107878000, 0.8420930000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1041551000, 0.1104865000, 0.1256181000, 0.1638184000, 0.2576246000, 0.4909770000, 1.0779888000", \ - "0.1089524000, 0.1150700000, 0.1305366000, 0.1686409000, 0.2625750000, 0.4959112000, 1.0828779000", \ - "0.1202003000, 0.1265176000, 0.1418673000, 0.1797946000, 0.2736449000, 0.5072356000, 1.0943561000", \ - "0.1451175000, 0.1510098000, 0.1662835000, 0.2041721000, 0.2979831000, 0.5319374000, 1.1193461000", \ - "0.1846709000, 0.1907452000, 0.2061012000, 0.2436748000, 0.3371524000, 0.5710827000, 1.1618317000", \ - "0.2361973000, 0.2425309000, 0.2575587000, 0.2948346000, 0.3874526000, 0.6210446000, 1.2088694000", \ - "0.2903712000, 0.2972814000, 0.3134265000, 0.3507281000, 0.4422939000, 0.6748971000, 1.2625173000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0366551000, 0.0379279000, 0.0413092000, 0.0504938000, 0.0735889000, 0.1315145000, 0.2857684000", \ - "0.0366502000, 0.0378249000, 0.0411833000, 0.0504243000, 0.0734354000, 0.1318286000, 0.2858296000", \ - "0.0366292000, 0.0378255000, 0.0412928000, 0.0503907000, 0.0734672000, 0.1315874000, 0.2857931000", \ - "0.0366738000, 0.0379289000, 0.0413307000, 0.0504895000, 0.0733963000, 0.1313441000, 0.2856388000", \ - "0.0386067000, 0.0397338000, 0.0429054000, 0.0516183000, 0.0743206000, 0.1320161000, 0.2856491000", \ - "0.0541313000, 0.0551519000, 0.0581676000, 0.0658767000, 0.0859769000, 0.1395493000, 0.2888509000", \ - "0.0785580000, 0.0795988000, 0.0830926000, 0.0920046000, 0.1117776000, 0.1611589000, 0.2997251000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0545994000, 0.0629886000, 0.0835648000, 0.1349140000, 0.2634703000, 0.5826326000, 1.3877066000", \ - "0.0547155000, 0.0628984000, 0.0834969000, 0.1349243000, 0.2628058000, 0.5837485000, 1.3905054000", \ - "0.0546105000, 0.0629810000, 0.0835550000, 0.1350016000, 0.2634608000, 0.5829494000, 1.3878234000", \ - "0.0547392000, 0.0629752000, 0.0835113000, 0.1349411000, 0.2629181000, 0.5828898000, 1.3932995000", \ - "0.0561599000, 0.0641514000, 0.0847301000, 0.1351541000, 0.2635781000, 0.5845247000, 1.3947828000", \ - "0.0607376000, 0.0684649000, 0.0874035000, 0.1367651000, 0.2640612000, 0.5829740000, 1.3896440000", \ - "0.0728815000, 0.0802046000, 0.0981511000, 0.1436041000, 0.2661921000, 0.5842795000, 1.3946286000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21boi_4") { - leakage_power () { - value : 0.0127454000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0041562000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0146596000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0041568000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0138528000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0041568000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0134462000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0008047000; - when : "A1&A2&!B1_N"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__a21boi"; - cell_leakage_power : 0.0084973050; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0085800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0151147000, 0.0150977000, 0.0150585000, 0.0150657000, 0.0150822000, 0.0151202000, 0.0152080000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015057900, -0.015057100, -0.015055100, -0.015058900, -0.015067700, -0.015087800, -0.015134400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089270000; - } - pin ("A2") { - capacitance : 0.0092350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0087590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162072000, 0.0162163000, 0.0162375000, 0.0162370000, 0.0162359000, 0.0162333000, 0.0162274000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016314700, -0.016287700, -0.016225500, -0.016226000, -0.016227100, -0.016229800, -0.016236000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0097110000; - } - pin ("B1_N") { - capacitance : 0.0024730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0223864000, 0.0222207000, 0.0218388000, 0.0220458000, 0.0225232000, 0.0236236000, 0.0261601000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076559000, 0.0075393000, 0.0072705000, 0.0074519000, 0.0078701000, 0.0088341000, 0.0110560000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026060000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&B1_N) | (!A2&B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0179400000, 0.0165514000, 0.0126924000, 0.0021153000, -0.026998700, -0.107292700, -0.328600700", \ - "0.0173839000, 0.0160152000, 0.0121979000, 0.0016559000, -0.027356500, -0.107687000, -0.329087900", \ - "0.0166422000, 0.0152691000, 0.0114868000, 0.0010903000, -0.027860100, -0.108094200, -0.329416300", \ - "0.0157621000, 0.0144430000, 0.0107372000, 0.0004370000, -0.028415600, -0.108500900, -0.329641800", \ - "0.0155883000, 0.0142394000, 0.0104373000, 0.0001570000, -0.028857800, -0.108736600, -0.329979100", \ - "0.0175168000, 0.0161445000, 0.0123130000, 0.0011070000, -0.028157700, -0.108440400, -0.329641800", \ - "0.0218922000, 0.0203808000, 0.0163483000, 0.0051489000, -0.025144600, -0.106767200, -0.329298500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0273046000, 0.0289106000, 0.0331072000, 0.0443030000, 0.0736493000, 0.1535120000, 0.3729338000", \ - "0.0264476000, 0.0279858000, 0.0322617000, 0.0435424000, 0.0732495000, 0.1534320000, 0.3724521000", \ - "0.0257749000, 0.0272622000, 0.0313671000, 0.0425115000, 0.0725294000, 0.1530507000, 0.3722575000", \ - "0.0253493000, 0.0267916000, 0.0307914000, 0.0418194000, 0.0714141000, 0.1531168000, 0.3719285000", \ - "0.0249085000, 0.0263533000, 0.0303152000, 0.0410525000, 0.0706078000, 0.1516758000, 0.3733080000", \ - "0.0248423000, 0.0262696000, 0.0301605000, 0.0410028000, 0.0702580000, 0.1507261000, 0.3701028000", \ - "0.0252941000, 0.0266002000, 0.0302000000, 0.0405826000, 0.0703921000, 0.1507848000, 0.3709306000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0190111000, 0.0175916000, 0.0137469000, 0.0031532000, -0.025982900, -0.106255400, -0.327576000", \ - "0.0184312000, 0.0170459000, 0.0132000000, 0.0026725000, -0.026437900, -0.106709900, -0.328037400", \ - "0.0176615000, 0.0162706000, 0.0124773000, 0.0020149000, -0.026958900, -0.107230100, -0.328454100", \ - "0.0167216000, 0.0153775000, 0.0117108000, 0.0013952000, -0.027453700, -0.107564100, -0.328757700", \ - "0.0168695000, 0.0154749000, 0.0115563000, 0.0008289000, -0.027996100, -0.107678300, -0.328763200", \ - "0.0171886000, 0.0157720000, 0.0118579000, 0.0012250000, -0.027946000, -0.108427900, -0.329073600", \ - "0.0204439000, 0.0190637000, 0.0149577000, 0.0039080000, -0.025951000, -0.106969600, -0.328960900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0392188000, 0.0406429000, 0.0445632000, 0.0552764000, 0.0846306000, 0.1643358000, 0.3830583000", \ - "0.0385065000, 0.0399870000, 0.0439164000, 0.0547324000, 0.0841576000, 0.1642415000, 0.3830464000", \ - "0.0377953000, 0.0392322000, 0.0432029000, 0.0540813000, 0.0836967000, 0.1636554000, 0.3827007000", \ - "0.0372947000, 0.0386963000, 0.0426544000, 0.0534635000, 0.0829231000, 0.1633219000, 0.3824333000", \ - "0.0368807000, 0.0383597000, 0.0422489000, 0.0529334000, 0.0823233000, 0.1626710000, 0.3818196000", \ - "0.0367419000, 0.0381453000, 0.0420459000, 0.0529545000, 0.0823381000, 0.1623125000, 0.3815902000", \ - "0.0369284000, 0.0382896000, 0.0420317000, 0.0524766000, 0.0825557000, 0.1630147000, 0.3822354000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0070916000, 0.0058901000, 0.0026881000, -0.006482700, -0.033946400, -0.113440100, -0.334701200", \ - "0.0069365000, 0.0058146000, 0.0027242000, -0.006456000, -0.033941500, -0.113475400, -0.334691700", \ - "0.0070842000, 0.0059010000, 0.0027158000, -0.006475600, -0.033891300, -0.113361000, -0.334583600", \ - "0.0064916000, 0.0052715000, 0.0021617000, -0.007121400, -0.034528700, -0.113888100, -0.335021200", \ - "0.0058405000, 0.0046114000, 0.0012343000, -0.008204900, -0.035554600, -0.114636900, -0.335620600", \ - "0.0064632000, 0.0050590000, 0.0012327000, -0.009056200, -0.036974500, -0.115571000, -0.336243800", \ - "0.0082022000, 0.0067200000, 0.0027048000, -0.008042500, -0.036873500, -0.116404300, -0.336706900"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0341045000, 0.0355705000, 0.0395931000, 0.0505152000, 0.0801172000, 0.1603017000, 0.3793491000", \ - "0.0341334000, 0.0356110000, 0.0396140000, 0.0505361000, 0.0801725000, 0.1602648000, 0.3790861000", \ - "0.0341295000, 0.0355994000, 0.0395971000, 0.0505257000, 0.0801092000, 0.1602200000, 0.3791903000", \ - "0.0334739000, 0.0349182000, 0.0389011000, 0.0498240000, 0.0793633000, 0.1595830000, 0.3786972000", \ - "0.0329132000, 0.0340619000, 0.0380061000, 0.0488583000, 0.0784789000, 0.1588001000, 0.3779502000", \ - "0.0328308000, 0.0342285000, 0.0376381000, 0.0483366000, 0.0777601000, 0.1580971000, 0.3773340000", \ - "0.0333336000, 0.0347374000, 0.0386818000, 0.0492310000, 0.0783362000, 0.1583211000, 0.3771580000"); - } - } - max_capacitance : 0.2151590000; - max_transition : 1.4962450000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0238817000, 0.0254790000, 0.0296035000, 0.0400575000, 0.0662833000, 0.1340798000, 0.3167884000", \ - "0.0279458000, 0.0294956000, 0.0335855000, 0.0440253000, 0.0702183000, 0.1380050000, 0.3207188000", \ - "0.0383102000, 0.0399649000, 0.0440668000, 0.0539390000, 0.0799476000, 0.1478165000, 0.3304111000", \ - "0.0532786000, 0.0552931000, 0.0611849000, 0.0747607000, 0.1032636000, 0.1708134000, 0.3534842000", \ - "0.0677599000, 0.0709785000, 0.0796532000, 0.0996983000, 0.1428810000, 0.2254693000, 0.4078537000", \ - "0.0701560000, 0.0751625000, 0.0881232000, 0.1198765000, 0.1859028000, 0.3098934000, 0.5327292000", \ - "0.0312895000, 0.0390333000, 0.0596928000, 0.1067486000, 0.2085984000, 0.4017771000, 0.7398683000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0811141000, 0.0861230000, 0.0990114000, 0.1329480000, 0.2219588000, 0.4615499000, 1.1244781000", \ - "0.0848176000, 0.0897153000, 0.1027063000, 0.1366865000, 0.2263829000, 0.4674799000, 1.1256287000", \ - "0.0969788000, 0.1017650000, 0.1143904000, 0.1481545000, 0.2382929000, 0.4802758000, 1.1396184000", \ - "0.1252928000, 0.1299292000, 0.1423429000, 0.1754213000, 0.2653191000, 0.5103279000, 1.1693062000", \ - "0.1752889000, 0.1810885000, 0.1962617000, 0.2341585000, 0.3240063000, 0.5691193000, 1.2326145000", \ - "0.2591884000, 0.2679308000, 0.2890225000, 0.3409481000, 0.4536259000, 0.7031590000, 1.3643427000", \ - "0.3952025000, 0.4108039000, 0.4441162000, 0.5251620000, 0.6867892000, 1.0061698000, 1.6841920000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0253690000, 0.0269479000, 0.0311615000, 0.0429115000, 0.0755245000, 0.1662289000, 0.4188494000", \ - "0.0243668000, 0.0259334000, 0.0303019000, 0.0425242000, 0.0753109000, 0.1663667000, 0.4190571000", \ - "0.0275211000, 0.0287484000, 0.0322940000, 0.0429973000, 0.0748660000, 0.1661558000, 0.4185659000", \ - "0.0377769000, 0.0398383000, 0.0444560000, 0.0547618000, 0.0815948000, 0.1665225000, 0.4188269000", \ - "0.0578871000, 0.0599499000, 0.0663381000, 0.0815559000, 0.1134756000, 0.1872887000, 0.4193249000", \ - "0.0930508000, 0.0970399000, 0.1073559000, 0.1299204000, 0.1758854000, 0.2686066000, 0.4652557000", \ - "0.1554881000, 0.1618080000, 0.1779811000, 0.2144157000, 0.2849083000, 0.4136971000, 0.6570327000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0488291000, 0.0548699000, 0.0711473000, 0.1160331000, 0.2376175000, 0.5697740000, 1.4800881000", \ - "0.0489013000, 0.0548287000, 0.0713509000, 0.1157709000, 0.2376411000, 0.5703334000, 1.4784131000", \ - "0.0490675000, 0.0548439000, 0.0712859000, 0.1159155000, 0.2374366000, 0.5697366000, 1.4777536000", \ - "0.0501481000, 0.0561138000, 0.0720648000, 0.1162203000, 0.2374971000, 0.5733127000, 1.4790417000", \ - "0.0651333000, 0.0710445000, 0.0863103000, 0.1258202000, 0.2405900000, 0.5706358000, 1.4900124000", \ - "0.0982237000, 0.1046037000, 0.1226096000, 0.1660518000, 0.2739540000, 0.5777669000, 1.4818126000", \ - "0.1754289000, 0.1836767000, 0.2056811000, 0.2566263000, 0.3752195000, 0.6633920000, 1.4962455000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0295888000, 0.0311504000, 0.0352770000, 0.0456890000, 0.0718773000, 0.1397753000, 0.3221623000", \ - "0.0337294000, 0.0353096000, 0.0394107000, 0.0498323000, 0.0760530000, 0.1439188000, 0.3264378000", \ - "0.0427192000, 0.0443317000, 0.0484122000, 0.0586838000, 0.0848531000, 0.1528284000, 0.3357343000", \ - "0.0573435000, 0.0593337000, 0.0645852000, 0.0768526000, 0.1050676000, 0.1731617000, 0.3561144000", \ - "0.0754570000, 0.0783919000, 0.0857048000, 0.1030350000, 0.1407480000, 0.2190998000, 0.4038699000", \ - "0.0862276000, 0.0908366000, 0.1024084000, 0.1295690000, 0.1870858000, 0.2967673000, 0.5100952000", \ - "0.0624235000, 0.0692935000, 0.0877484000, 0.1307685000, 0.2212856000, 0.3933705000, 0.6938073000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1054145000, 0.1096106000, 0.1214591000, 0.1525865000, 0.2361999000, 0.4639159000, 1.0918493000", \ - "0.1097738000, 0.1140396000, 0.1255658000, 0.1572681000, 0.2413466000, 0.4695277000, 1.0935292000", \ - "0.1219303000, 0.1260915000, 0.1379634000, 0.1694633000, 0.2539843000, 0.4830152000, 1.1069742000", \ - "0.1493125000, 0.1538333000, 0.1654086000, 0.1968260000, 0.2815466000, 0.5104387000, 1.1350382000", \ - "0.2036337000, 0.2087274000, 0.2220837000, 0.2554855000, 0.3398557000, 0.5689532000, 1.1939170000", \ - "0.2979302000, 0.3047121000, 0.3221493000, 0.3661334000, 0.4683441000, 0.7034567000, 1.3292749000", \ - "0.4523747000, 0.4630311000, 0.4897764000, 0.5556535000, 0.6983525000, 0.9978796000, 1.6437388000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0251428000, 0.0266655000, 0.0309679000, 0.0427622000, 0.0753954000, 0.1661905000, 0.4182691000", \ - "0.0248176000, 0.0263905000, 0.0307123000, 0.0426286000, 0.0752355000, 0.1660935000, 0.4189382000", \ - "0.0261053000, 0.0274862000, 0.0314921000, 0.0428197000, 0.0749918000, 0.1660914000, 0.4182372000", \ - "0.0340799000, 0.0354981000, 0.0394395000, 0.0498761000, 0.0785367000, 0.1663884000, 0.4184356000", \ - "0.0515194000, 0.0533362000, 0.0580381000, 0.0703700000, 0.0995473000, 0.1782699000, 0.4193900000", \ - "0.0843545000, 0.0870453000, 0.0937844000, 0.1108383000, 0.1486705000, 0.2331617000, 0.4473037000", \ - "0.1448443000, 0.1489018000, 0.1598868000, 0.1855608000, 0.2415403000, 0.3500465000, 0.5764903000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0672715000, 0.0730043000, 0.0887345000, 0.1310951000, 0.2466677000, 0.5619774000, 1.4251855000", \ - "0.0673329000, 0.0730423000, 0.0887075000, 0.1313065000, 0.2467254000, 0.5608417000, 1.4265582000", \ - "0.0673420000, 0.0730662000, 0.0887504000, 0.1311598000, 0.2465849000, 0.5618168000, 1.4223146000", \ - "0.0677214000, 0.0733798000, 0.0889237000, 0.1312336000, 0.2465553000, 0.5609436000, 1.4227088000", \ - "0.0806480000, 0.0858447000, 0.0998303000, 0.1388296000, 0.2484700000, 0.5612510000, 1.4212885000", \ - "0.1132626000, 0.1194871000, 0.1356006000, 0.1773639000, 0.2806888000, 0.5698199000, 1.4257683000", \ - "0.1895308000, 0.1972419000, 0.2170841000, 0.2658895000, 0.3811835000, 0.6547575000, 1.4428120000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1098076000, 0.1120931000, 0.1173242000, 0.1293472000, 0.1534723000, 0.2030025000, 0.3216991000", \ - "0.1145612000, 0.1168307000, 0.1221505000, 0.1340299000, 0.1581827000, 0.2078218000, 0.3265197000", \ - "0.1268913000, 0.1291829000, 0.1345055000, 0.1463870000, 0.1703785000, 0.2201632000, 0.3388767000", \ - "0.1565518000, 0.1587095000, 0.1640267000, 0.1758910000, 0.2000894000, 0.2497649000, 0.3686033000", \ - "0.2238727000, 0.2260697000, 0.2319684000, 0.2439746000, 0.2685291000, 0.3186725000, 0.4377200000", \ - "0.3327764000, 0.3356538000, 0.3429247000, 0.3581601000, 0.3873080000, 0.4417023000, 0.5631183000", \ - "0.4975669000, 0.5012222000, 0.5102366000, 0.5288139000, 0.5662333000, 0.6311296000, 0.7575770000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1227587000, 0.1272081000, 0.1388125000, 0.1708478000, 0.2554687000, 0.4839167000, 1.1081261000", \ - "0.1272728000, 0.1316768000, 0.1433067000, 0.1752968000, 0.2600071000, 0.4885434000, 1.1121438000", \ - "0.1382430000, 0.1426486000, 0.1542662000, 0.1861169000, 0.2709461000, 0.4995752000, 1.1271158000", \ - "0.1626899000, 0.1668723000, 0.1785672000, 0.2101744000, 0.2951376000, 0.5240045000, 1.1481623000", \ - "0.2039219000, 0.2076751000, 0.2193135000, 0.2510372000, 0.3349771000, 0.5638474000, 1.1894175000", \ - "0.2563413000, 0.2606526000, 0.2714866000, 0.3028125000, 0.3871463000, 0.6158055000, 1.2402183000", \ - "0.3109474000, 0.3156089000, 0.3274500000, 0.3588873000, 0.4417121000, 0.6690754000, 1.2934693000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0358714000, 0.0365547000, 0.0386107000, 0.0451238000, 0.0639886000, 0.1163940000, 0.2678614000", \ - "0.0358513000, 0.0365019000, 0.0386409000, 0.0450492000, 0.0639435000, 0.1166546000, 0.2674008000", \ - "0.0358666000, 0.0365547000, 0.0386464000, 0.0451107000, 0.0639291000, 0.1165389000, 0.2675802000", \ - "0.0360173000, 0.0366383000, 0.0386762000, 0.0451534000, 0.0639818000, 0.1165105000, 0.2674500000", \ - "0.0398601000, 0.0404480000, 0.0422265000, 0.0479167000, 0.0655758000, 0.1172598000, 0.2678958000", \ - "0.0565756000, 0.0570135000, 0.0584352000, 0.0635369000, 0.0789186000, 0.1269077000, 0.2717415000", \ - "0.0816042000, 0.0820950000, 0.0837891000, 0.0896463000, 0.1053326000, 0.1477050000, 0.2820584000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0669014000, 0.0727075000, 0.0884288000, 0.1311922000, 0.2465967000, 0.5611394000, 1.4245812000", \ - "0.0668951000, 0.0727029000, 0.0884316000, 0.1311898000, 0.2466344000, 0.5611989000, 1.4221558000", \ - "0.0668983000, 0.0727075000, 0.0884303000, 0.1311174000, 0.2465479000, 0.5614118000, 1.4235002000", \ - "0.0668908000, 0.0726760000, 0.0883118000, 0.1310841000, 0.2469304000, 0.5610415000, 1.4207002000", \ - "0.0680678000, 0.0739535000, 0.0891616000, 0.1314690000, 0.2466198000, 0.5614177000, 1.4232320000", \ - "0.0716922000, 0.0770771000, 0.0925021000, 0.1332862000, 0.2483803000, 0.5613787000, 1.4223859000", \ - "0.0841176000, 0.0891081000, 0.1031710000, 0.1404703000, 0.2501944000, 0.5626596000, 1.4244410000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21o_1") { - leakage_power () { - value : 0.0033020000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0109817000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0033020000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0114142000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0033020000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0112135000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0006234000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0030859000; - when : "A1&A2&!B1"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__a21o"; - cell_leakage_power : 0.0059030840; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045540000, 0.0045540000, 0.0045539000, 0.0045521000, 0.0045481000, 0.0045386000, 0.0045169000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003625300, -0.003627800, -0.003633800, -0.003627300, -0.003612500, -0.003578400, -0.003499600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024710000; - } - pin ("A2") { - capacitance : 0.0023340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040206000, 0.0040237000, 0.0040308000, 0.0040304000, 0.0040296000, 0.0040277000, 0.0040233000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004034700, -0.004034800, -0.004034900, -0.004035200, -0.004035900, -0.004037500, -0.004041200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024340000; - } - pin ("B1") { - capacitance : 0.0024200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026137000, 0.0026063000, 0.0025893000, 0.0026038000, 0.0026374000, 0.0027148000, 0.0028932000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001725400, -0.001725100, -0.001724400, -0.001724200, -0.001723800, -0.001722900, -0.001720700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025940000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0103859000, 0.0094608000, 0.0067777000, -0.001719700, -0.026621600, -0.094005600, -0.273648300", \ - "0.0101756000, 0.0092349000, 0.0065938000, -0.001933100, -0.026835800, -0.094236500, -0.273805700", \ - "0.0099510000, 0.0090682000, 0.0063200000, -0.002214500, -0.027082500, -0.094475100, -0.274044500", \ - "0.0097338000, 0.0087859000, 0.0060891000, -0.002448400, -0.027311100, -0.094688300, -0.274267700", \ - "0.0095490000, 0.0085320000, 0.0058344000, -0.002680600, -0.027525600, -0.094858400, -0.274422400", \ - "0.0109378000, 0.0096111000, 0.0061458000, -0.003243600, -0.027667100, -0.094904200, -0.274504200", \ - "0.0118892000, 0.0104837000, 0.0071129000, -0.002391300, -0.027508400, -0.094552400, -0.274031200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0129800000, 0.0144592000, 0.0182718000, 0.0280145000, 0.0533985000, 0.1202975000, 0.2993030000", \ - "0.0128424000, 0.0143115000, 0.0181391000, 0.0279011000, 0.0532733000, 0.1206119000, 0.2988908000", \ - "0.0126425000, 0.0141233000, 0.0179294000, 0.0277016000, 0.0530815000, 0.1205282000, 0.2990129000", \ - "0.0124064000, 0.0138520000, 0.0176266000, 0.0273610000, 0.0527130000, 0.1196196000, 0.2971840000", \ - "0.0125219000, 0.0138452000, 0.0174850000, 0.0270335000, 0.0523758000, 0.1193901000, 0.2970324000", \ - "0.0128766000, 0.0142279000, 0.0178138000, 0.0273158000, 0.0527867000, 0.1190530000, 0.2984278000", \ - "0.0145151000, 0.0158795000, 0.0193984000, 0.0288807000, 0.0540874000, 0.1212303000, 0.2990392000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0132623000, 0.0122940000, 0.0096458000, 0.0012168000, -0.023561900, -0.090830100, -0.270360400", \ - "0.0131528000, 0.0122293000, 0.0095127000, 0.0010977000, -0.023686600, -0.090946700, -0.270508300", \ - "0.0129686000, 0.0120631000, 0.0093651000, 0.0009377000, -0.023838200, -0.091116400, -0.270639200", \ - "0.0128702000, 0.0119111000, 0.0092030000, 0.0007657000, -0.023993200, -0.091283900, -0.270796900", \ - "0.0127265000, 0.0117374000, 0.0090173000, 0.0005687000, -0.024182500, -0.091412400, -0.270917400", \ - "0.0143375000, 0.0130318000, 0.0094585000, 5.060000e-05, -0.024298800, -0.091480800, -0.270947100", \ - "0.0154742000, 0.0140687000, 0.0104348000, 0.0009459000, -0.024200200, -0.091167200, -0.270530400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0132646000, 0.0147467000, 0.0185711000, 0.0283613000, 0.0537408000, 0.1205683000, 0.2980731000", \ - "0.0131639000, 0.0146366000, 0.0184653000, 0.0282340000, 0.0536443000, 0.1204603000, 0.2995297000", \ - "0.0130006000, 0.0144821000, 0.0182877000, 0.0280428000, 0.0534431000, 0.1207884000, 0.2990669000", \ - "0.0128333000, 0.0142978000, 0.0180452000, 0.0277755000, 0.0532187000, 0.1201396000, 0.2977600000", \ - "0.0128235000, 0.0141593000, 0.0178552000, 0.0275223000, 0.0529136000, 0.1199435000, 0.2975963000", \ - "0.0130772000, 0.0144143000, 0.0180688000, 0.0276012000, 0.0529443000, 0.1194649000, 0.2988184000", \ - "0.0143227000, 0.0156513000, 0.0192467000, 0.0287580000, 0.0540231000, 0.1213220000, 0.2976497000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0122175000, 0.0112622000, 0.0086281000, 0.0001830000, -0.024570100, -0.091839500, -0.271366400", \ - "0.0120210000, 0.0110907000, 0.0084215000, -4.33000e-05, -0.024816700, -0.092059100, -0.271586200", \ - "0.0117787000, 0.0108091000, 0.0081652000, -0.000305200, -0.025058800, -0.092338800, -0.271856800", \ - "0.0116186000, 0.0106678000, 0.0079617000, -0.000497300, -0.025240800, -0.092493100, -0.271997000", \ - "0.0116198000, 0.0106362000, 0.0078928000, -0.000614400, -0.025355100, -0.092556900, -0.272025000", \ - "0.0136973000, 0.0123474000, 0.0087869000, -0.000521200, -0.024871700, -0.092089700, -0.271538300", \ - "0.0163046000, 0.0148936000, 0.0112299000, 0.0016272000, -0.023337600, -0.090346500, -0.269759200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013306320, 0.0035411620, 0.0094239650, 0.0250796500, 0.0667435700, 0.1776222000"); - values("0.0086209000, 0.0100721000, 0.0137601000, 0.0232446000, 0.0485131000, 0.1151700000, 0.2929835000", \ - "0.0085063000, 0.0099413000, 0.0136334000, 0.0231406000, 0.0482892000, 0.1156662000, 0.2917032000", \ - "0.0082492000, 0.0096707000, 0.0133528000, 0.0229168000, 0.0480994000, 0.1154397000, 0.2943959000", \ - "0.0079457000, 0.0093467000, 0.0129806000, 0.0225559000, 0.0477508000, 0.1146761000, 0.2911292000", \ - "0.0080805000, 0.0094567000, 0.0129630000, 0.0224968000, 0.0477010000, 0.1150787000, 0.2922951000", \ - "0.0086805000, 0.0100098000, 0.0136641000, 0.0231572000, 0.0482607000, 0.1145053000, 0.2938411000", \ - "0.0109404000, 0.0122345000, 0.0157370000, 0.0252553000, 0.0504947000, 0.1173394000, 0.2941986000"); - } - } - max_capacitance : 0.1776220000; - max_transition : 1.5041070000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.1207517000, 0.1270962000, 0.1403721000, 0.1672627000, 0.2234068000, 0.3566018000, 0.7069951000", \ - "0.1254665000, 0.1316861000, 0.1450832000, 0.1719145000, 0.2280868000, 0.3613927000, 0.7107013000", \ - "0.1377666000, 0.1440935000, 0.1573505000, 0.1841707000, 0.2403246000, 0.3736152000, 0.7237677000", \ - "0.1663351000, 0.1726014000, 0.1859274000, 0.2127409000, 0.2688817000, 0.4021094000, 0.7516895000", \ - "0.2253126000, 0.2318206000, 0.2455778000, 0.2729740000, 0.3295920000, 0.4630388000, 0.8132443000", \ - "0.3252157000, 0.3328969000, 0.3489725000, 0.3799497000, 0.4407315000, 0.5761166000, 0.9248942000", \ - "0.4847406000, 0.4944937000, 0.5145861000, 0.5527568000, 0.6223884000, 0.7632169000, 1.1135778000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0704410000, 0.0770437000, 0.0922062000, 0.1284827000, 0.2213105000, 0.4640789000, 1.1090238000", \ - "0.0744161000, 0.0810166000, 0.0961933000, 0.1324726000, 0.2253173000, 0.4690475000, 1.1160889000", \ - "0.0841865000, 0.0907527000, 0.1059753000, 0.1422493000, 0.2346888000, 0.4781091000, 1.1234175000", \ - "0.1064930000, 0.1131050000, 0.1281572000, 0.1642892000, 0.2566394000, 0.4998438000, 1.1444806000", \ - "0.1377045000, 0.1446105000, 0.1602261000, 0.1962840000, 0.2891741000, 0.5324550000, 1.1780305000", \ - "0.1707978000, 0.1788932000, 0.1958730000, 0.2328942000, 0.3254965000, 0.5693461000, 1.2177344000", \ - "0.1832930000, 0.1941622000, 0.2154107000, 0.2557097000, 0.3473485000, 0.5915377000, 1.2371163000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0207336000, 0.0253822000, 0.0357143000, 0.0601569000, 0.1210863000, 0.2896581000, 0.7523467000", \ - "0.0206343000, 0.0252022000, 0.0357525000, 0.0602236000, 0.1214766000, 0.2909483000, 0.7492739000", \ - "0.0207238000, 0.0253114000, 0.0360352000, 0.0604234000, 0.1210451000, 0.2894581000, 0.7492082000", \ - "0.0205332000, 0.0254145000, 0.0357070000, 0.0604744000, 0.1210135000, 0.2895902000, 0.7536655000", \ - "0.0224729000, 0.0271653000, 0.0376906000, 0.0615463000, 0.1221198000, 0.2893380000, 0.7496609000", \ - "0.0284378000, 0.0338464000, 0.0452324000, 0.0695587000, 0.1290867000, 0.2919727000, 0.7580527000", \ - "0.0397828000, 0.0462130000, 0.0603518000, 0.0867824000, 0.1452466000, 0.3000954000, 0.7509625000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0208100000, 0.0274111000, 0.0446743000, 0.0922680000, 0.2223922000, 0.5702023000, 1.4967244000", \ - "0.0208286000, 0.0274399000, 0.0446867000, 0.0923201000, 0.2222158000, 0.5696926000, 1.4947507000", \ - "0.0207297000, 0.0273887000, 0.0447103000, 0.0922012000, 0.2225471000, 0.5704976000, 1.4980222000", \ - "0.0213688000, 0.0278921000, 0.0450825000, 0.0923928000, 0.2222956000, 0.5688723000, 1.4946487000", \ - "0.0241512000, 0.0302294000, 0.0468739000, 0.0937618000, 0.2228357000, 0.5704781000, 1.4974612000", \ - "0.0306972000, 0.0364988000, 0.0514350000, 0.0954410000, 0.2236456000, 0.5703668000, 1.4949727000", \ - "0.0419928000, 0.0488144000, 0.0631112000, 0.1022974000, 0.2245686000, 0.5731163000, 1.4911166000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.1405778000, 0.1471221000, 0.1610224000, 0.1884188000, 0.2455979000, 0.3797601000, 0.7301091000", \ - "0.1457073000, 0.1522930000, 0.1661173000, 0.1935260000, 0.2507582000, 0.3849439000, 0.7345892000", \ - "0.1584030000, 0.1649769000, 0.1785809000, 0.2062266000, 0.2634348000, 0.3975450000, 0.7475900000", \ - "0.1855613000, 0.1921034000, 0.2059217000, 0.2335375000, 0.2906910000, 0.4248555000, 0.7750235000", \ - "0.2422388000, 0.2489030000, 0.2629128000, 0.2905643000, 0.3479311000, 0.4821922000, 0.8321805000", \ - "0.3411315000, 0.3486773000, 0.3644538000, 0.3952776000, 0.4560329000, 0.5922547000, 0.9417089000", \ - "0.4993399000, 0.5089338000, 0.5285082000, 0.5651840000, 0.6330898000, 0.7738204000, 1.1249062000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0748536000, 0.0814343000, 0.0967105000, 0.1329365000, 0.2254104000, 0.4684181000, 1.1137995000", \ - "0.0792179000, 0.0858093000, 0.1009933000, 0.1372350000, 0.2296889000, 0.4727457000, 1.1176697000", \ - "0.0886673000, 0.0952682000, 0.1104399000, 0.1467552000, 0.2395903000, 0.4833237000, 1.1303865000", \ - "0.1093766000, 0.1159454000, 0.1311501000, 0.1672222000, 0.2597979000, 0.5030806000, 1.1485974000", \ - "0.1432803000, 0.1503439000, 0.1660598000, 0.2025268000, 0.2952724000, 0.5386711000, 1.1840210000", \ - "0.1848648000, 0.1931645000, 0.2106505000, 0.2480913000, 0.3407757000, 0.5840439000, 1.2313858000", \ - "0.2166481000, 0.2275741000, 0.2496704000, 0.2908122000, 0.3839101000, 0.6274745000, 1.2720464000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0225129000, 0.0271585000, 0.0373551000, 0.0622143000, 0.1232574000, 0.2906925000, 0.7553682000", \ - "0.0225370000, 0.0271401000, 0.0375558000, 0.0623497000, 0.1232087000, 0.2916632000, 0.7524855000", \ - "0.0223479000, 0.0271766000, 0.0377739000, 0.0621176000, 0.1230641000, 0.2903325000, 0.7571139000", \ - "0.0225880000, 0.0273269000, 0.0375281000, 0.0623000000, 0.1229430000, 0.2921660000, 0.7533820000", \ - "0.0232758000, 0.0280258000, 0.0383678000, 0.0632812000, 0.1232975000, 0.2917445000, 0.7519346000", \ - "0.0287272000, 0.0336532000, 0.0454019000, 0.0690952000, 0.1293925000, 0.2930482000, 0.7540360000", \ - "0.0393928000, 0.0453660000, 0.0583309000, 0.0835063000, 0.1422070000, 0.2999248000, 0.7506032000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0208516000, 0.0274195000, 0.0447673000, 0.0923466000, 0.2226182000, 0.5706040000, 1.4972257000", \ - "0.0208622000, 0.0274310000, 0.0447280000, 0.0921672000, 0.2223446000, 0.5698572000, 1.4962867000", \ - "0.0208206000, 0.0273473000, 0.0446797000, 0.0923821000, 0.2222083000, 0.5699486000, 1.4947659000", \ - "0.0211657000, 0.0277122000, 0.0449931000, 0.0922814000, 0.2225232000, 0.5708848000, 1.4983247000", \ - "0.0238111000, 0.0301455000, 0.0469178000, 0.0932780000, 0.2223012000, 0.5709679000, 1.4980547000", \ - "0.0297566000, 0.0359965000, 0.0516562000, 0.0953801000, 0.2233382000, 0.5699292000, 1.4971988000", \ - "0.0406217000, 0.0474154000, 0.0632025000, 0.1031195000, 0.2251407000, 0.5719495000, 1.4910529000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.1214856000, 0.1280432000, 0.1419069000, 0.1695194000, 0.2264375000, 0.3606111000, 0.7109650000", \ - "0.1246210000, 0.1311969000, 0.1450670000, 0.1727524000, 0.2298718000, 0.3638843000, 0.7131665000", \ - "0.1344706000, 0.1410417000, 0.1548687000, 0.1823978000, 0.2395970000, 0.3737424000, 0.7239087000", \ - "0.1619536000, 0.1685159000, 0.1823137000, 0.2098467000, 0.2670801000, 0.4013009000, 0.7511006000", \ - "0.2262558000, 0.2329567000, 0.2469770000, 0.2748119000, 0.3321883000, 0.4665409000, 0.8166869000", \ - "0.3336888000, 0.3418877000, 0.3580835000, 0.3878891000, 0.4478108000, 0.5845374000, 0.9342143000", \ - "0.5047432000, 0.5152042000, 0.5357078000, 0.5722605000, 0.6362030000, 0.7742306000, 1.1262274000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0481001000, 0.0539573000, 0.0677945000, 0.1025531000, 0.1936450000, 0.4373999000, 1.0865135000", \ - "0.0527486000, 0.0585948000, 0.0724903000, 0.1072384000, 0.1980939000, 0.4404923000, 1.0936752000", \ - "0.0633547000, 0.0691446000, 0.0830191000, 0.1178298000, 0.2095132000, 0.4517288000, 1.0974690000", \ - "0.0814188000, 0.0875652000, 0.1018161000, 0.1369508000, 0.2291655000, 0.4704058000, 1.1156909000", \ - "0.1027100000, 0.1100047000, 0.1253805000, 0.1608826000, 0.2525796000, 0.4950151000, 1.1394471000", \ - "0.1192403000, 0.1289153000, 0.1478051000, 0.1852538000, 0.2768556000, 0.5203420000, 1.1681441000", \ - "0.1082897000, 0.1213376000, 0.1467178000, 0.1917435000, 0.2844602000, 0.5277005000, 1.1730744000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0222942000, 0.0269503000, 0.0373622000, 0.0620888000, 0.1232670000, 0.2907885000, 0.7553696000", \ - "0.0222754000, 0.0272469000, 0.0378022000, 0.0622893000, 0.1229365000, 0.2916191000, 0.7520427000", \ - "0.0226660000, 0.0269196000, 0.0376509000, 0.0622582000, 0.1230349000, 0.2904696000, 0.7573653000", \ - "0.0223538000, 0.0268329000, 0.0374300000, 0.0621947000, 0.1228068000, 0.2913015000, 0.7506337000", \ - "0.0240614000, 0.0286029000, 0.0389906000, 0.0632594000, 0.1233542000, 0.2922094000, 0.7524290000", \ - "0.0326999000, 0.0372539000, 0.0472479000, 0.0704639000, 0.1295316000, 0.2938900000, 0.7564114000", \ - "0.0457194000, 0.0517404000, 0.0628366000, 0.0846190000, 0.1392436000, 0.2984251000, 0.7516274000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013306300, 0.0035411600, 0.0094239600, 0.0250797000, 0.0667436000, 0.1776220000"); - values("0.0179465000, 0.0243056000, 0.0418710000, 0.0902238000, 0.2218376000, 0.5717004000, 1.5036992000", \ - "0.0179474000, 0.0243742000, 0.0419176000, 0.0902959000, 0.2215096000, 0.5717156000, 1.4983086000", \ - "0.0181434000, 0.0244688000, 0.0419633000, 0.0904214000, 0.2217969000, 0.5720353000, 1.5041065000", \ - "0.0205333000, 0.0264255000, 0.0430459000, 0.0906399000, 0.2214119000, 0.5715373000, 1.4934478000", \ - "0.0262328000, 0.0315206000, 0.0463599000, 0.0918452000, 0.2209870000, 0.5709444000, 1.4997720000", \ - "0.0365732000, 0.0419992000, 0.0553565000, 0.0957074000, 0.2224560000, 0.5687580000, 1.4959153000", \ - "0.0520031000, 0.0587121000, 0.0734793000, 0.1092364000, 0.2254418000, 0.5718275000, 1.4930691000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21o_2") { - leakage_power () { - value : 0.0036643000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0081635000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0036641000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0086168000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0036643000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0083986000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0011005000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0035415000; - when : "A1&A2&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a21o"; - cell_leakage_power : 0.0051017210; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045295000, 0.0045314000, 0.0045358000, 0.0045357000, 0.0045356000, 0.0045352000, 0.0045344000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003454600, -0.003457900, -0.003465600, -0.003458300, -0.003441400, -0.003402500, -0.003312700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024440000; - } - pin ("A2") { - capacitance : 0.0023150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039752000, 0.0039712000, 0.0039618000, 0.0039624000, 0.0039639000, 0.0039673000, 0.0039752000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003962100, -0.003964500, -0.003970000, -0.003970800, -0.003972400, -0.003976300, -0.003985100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("B1") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021215000, 0.0021123000, 0.0020910000, 0.0021043000, 0.0021348000, 0.0022052000, 0.0023675000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001729500, -0.001727100, -0.001721500, -0.001720700, -0.001719000, -0.001714900, -0.001705400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025640000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0138297000, 0.0123528000, 0.0086713000, -0.002509500, -0.039559000, -0.151898400, -0.481335900", \ - "0.0135840000, 0.0121282000, 0.0085016000, -0.002644600, -0.039628400, -0.152033500, -0.481464900", \ - "0.0133875000, 0.0119578000, 0.0082582000, -0.002900500, -0.039916100, -0.152295100, -0.481734500", \ - "0.0131576000, 0.0116663000, 0.0080047000, -0.003209000, -0.040169400, -0.152528900, -0.481974900", \ - "0.0130298000, 0.0115583000, 0.0077787000, -0.003499500, -0.040493900, -0.152814800, -0.482224700", \ - "0.0142303000, 0.0126101000, 0.0080443000, -0.004164800, -0.040824800, -0.152996100, -0.482317800", \ - "0.0173918000, 0.0156189000, 0.0108741000, -0.002406000, -0.040726300, -0.152824600, -0.482049800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0175800000, 0.0192934000, 0.0241455000, 0.0377649000, 0.0766362000, 0.1883976000, 0.5145676000", \ - "0.0174493000, 0.0191502000, 0.0240206000, 0.0376698000, 0.0765561000, 0.1883861000, 0.5146285000", \ - "0.0172356000, 0.0189128000, 0.0237858000, 0.0375095000, 0.0763096000, 0.1891068000, 0.5134890000", \ - "0.0170708000, 0.0187426000, 0.0236092000, 0.0372263000, 0.0760422000, 0.1882379000, 0.5138046000", \ - "0.0171304000, 0.0187131000, 0.0234981000, 0.0367418000, 0.0754271000, 0.1876369000, 0.5140355000", \ - "0.0180098000, 0.0195207000, 0.0240330000, 0.0374002000, 0.0756119000, 0.1867649000, 0.5135694000", \ - "0.0194734000, 0.0209411000, 0.0253142000, 0.0383495000, 0.0769557000, 0.1890820000, 0.5129636000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0168256000, 0.0153388000, 0.0115864000, 0.0003811000, -0.036508800, -0.148661000, -0.477949000", \ - "0.0167998000, 0.0153306000, 0.0115669000, 0.0003692000, -0.036546500, -0.148735800, -0.478089200", \ - "0.0165649000, 0.0151053000, 0.0113207000, 0.0001869000, -0.036637400, -0.148870200, -0.478224300", \ - "0.0164635000, 0.0150029000, 0.0112338000, 3.420000e-05, -0.036867000, -0.149083900, -0.478379800", \ - "0.0163707000, 0.0148859000, 0.0110808000, -0.000204800, -0.037055900, -0.149252000, -0.478565600", \ - "0.0172769000, 0.0156658000, 0.0110846000, -0.000682200, -0.037302500, -0.149366600, -0.478619700", \ - "0.0216440000, 0.0198746000, 0.0150470000, 0.0015989000, -0.036895900, -0.149154200, -0.478303100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0179906000, 0.0196977000, 0.0245014000, 0.0382161000, 0.0770700000, 0.1898426000, 0.5142041000", \ - "0.0178414000, 0.0195267000, 0.0244043000, 0.0381345000, 0.0769485000, 0.1887595000, 0.5148460000", \ - "0.0177321000, 0.0194099000, 0.0242792000, 0.0379576000, 0.0768635000, 0.1889105000, 0.5150404000", \ - "0.0175876000, 0.0192471000, 0.0240622000, 0.0377653000, 0.0765888000, 0.1884837000, 0.5159614000", \ - "0.0174396000, 0.0190812000, 0.0238708000, 0.0373872000, 0.0761888000, 0.1881195000, 0.5143648000", \ - "0.0180641000, 0.0196311000, 0.0242205000, 0.0374498000, 0.0760126000, 0.1876343000, 0.5160890000", \ - "0.0193084000, 0.0207981000, 0.0252658000, 0.0385049000, 0.0771181000, 0.1893926000, 0.5148711000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0165705000, 0.0149744000, 0.0112114000, 7.940000e-05, -0.036744000, -0.148976500, -0.478304400", \ - "0.0162846000, 0.0147719000, 0.0110487000, -0.000111500, -0.036970200, -0.149187000, -0.478543300", \ - "0.0160419000, 0.0145124000, 0.0107649000, -0.000420600, -0.037269400, -0.149455300, -0.478807400", \ - "0.0158244000, 0.0143359000, 0.0105966000, -0.000608100, -0.037463400, -0.149677200, -0.479013900", \ - "0.0157751000, 0.0142589000, 0.0104477000, -0.000857600, -0.037736600, -0.149816500, -0.479100400", \ - "0.0173357000, 0.0156641000, 0.0109888000, -0.000778100, -0.037528900, -0.149598900, -0.478788900", \ - "0.0232603000, 0.0214474000, 0.0164607000, 0.0030023000, -0.035154200, -0.147387100, -0.476622100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0134224000, 0.0151274000, 0.0199198000, 0.0332486000, 0.0715512000, 0.1831939000, 0.5090274000", \ - "0.0133710000, 0.0150686000, 0.0198615000, 0.0332133000, 0.0715299000, 0.1840874000, 0.5093867000", \ - "0.0132053000, 0.0148899000, 0.0196409000, 0.0329940000, 0.0714006000, 0.1840570000, 0.5098790000", \ - "0.0129065000, 0.0145460000, 0.0192354000, 0.0326199000, 0.0710918000, 0.1820934000, 0.5079839000", \ - "0.0131486000, 0.0147131000, 0.0191831000, 0.0324627000, 0.0707839000, 0.1825481000, 0.5094423000", \ - "0.0136986000, 0.0152227000, 0.0197488000, 0.0330686000, 0.0711085000, 0.1822832000, 0.5114150000", \ - "0.0160450000, 0.0174373000, 0.0218355000, 0.0349748000, 0.0734078000, 0.1849500000, 0.5084557000"); - } - } - max_capacitance : 0.3094580000; - max_transition : 1.5057260000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1544624000, 0.1602229000, 0.1731887000, 0.1995518000, 0.2524129000, 0.3733696000, 0.7023352000", \ - "0.1593807000, 0.1651344000, 0.1781568000, 0.2043085000, 0.2572609000, 0.3783185000, 0.7079297000", \ - "0.1716268000, 0.1773632000, 0.1903282000, 0.2167068000, 0.2695127000, 0.3905297000, 0.7196740000", \ - "0.1996523000, 0.2053640000, 0.2183046000, 0.2445561000, 0.2974739000, 0.4185278000, 0.7482495000", \ - "0.2613348000, 0.2670949000, 0.2798973000, 0.3061656000, 0.3592035000, 0.4801719000, 0.8098085000", \ - "0.3757423000, 0.3823252000, 0.3970155000, 0.4263759000, 0.4835216000, 0.6068181000, 0.9363474000", \ - "0.5649198000, 0.5730427000, 0.5910288000, 0.6268034000, 0.6928694000, 0.8250644000, 1.1565756000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0822214000, 0.0878291000, 0.1011136000, 0.1324621000, 0.2144200000, 0.4473038000, 1.1254617000", \ - "0.0862155000, 0.0918263000, 0.1051206000, 0.1364604000, 0.2183831000, 0.4513446000, 1.1295445000", \ - "0.0959011000, 0.1015136000, 0.1148181000, 0.1461622000, 0.2281201000, 0.4616963000, 1.1374713000", \ - "0.1195847000, 0.1251172000, 0.1383021000, 0.1694801000, 0.2511329000, 0.4846858000, 1.1651791000", \ - "0.1577860000, 0.1637966000, 0.1777524000, 0.2095279000, 0.2914495000, 0.5246423000, 1.2028659000", \ - "0.2009330000, 0.2084607000, 0.2247890000, 0.2583966000, 0.3400902000, 0.5736287000, 1.2547531000", \ - "0.2286442000, 0.2385479000, 0.2597619000, 0.2997864000, 0.3840505000, 0.6171906000, 1.2940131000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0236811000, 0.0277043000, 0.0364659000, 0.0563485000, 0.1067619000, 0.2492304000, 0.6865789000", \ - "0.0236274000, 0.0273685000, 0.0361673000, 0.0564517000, 0.1067180000, 0.2487742000, 0.6894043000", \ - "0.0238234000, 0.0277599000, 0.0364779000, 0.0563988000, 0.1065376000, 0.2491200000, 0.6866480000", \ - "0.0236892000, 0.0275944000, 0.0364681000, 0.0563184000, 0.1067451000, 0.2489763000, 0.6895645000", \ - "0.0243051000, 0.0280995000, 0.0366646000, 0.0567363000, 0.1070091000, 0.2490000000, 0.6910109000", \ - "0.0301680000, 0.0343852000, 0.0436028000, 0.0649294000, 0.1134773000, 0.2526502000, 0.6869768000", \ - "0.0427430000, 0.0474460000, 0.0583396000, 0.0810355000, 0.1315151000, 0.2648751000, 0.6902978000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0195527000, 0.0244121000, 0.0373087000, 0.0744551000, 0.1865707000, 0.5210989000, 1.5017658000", \ - "0.0195599000, 0.0244273000, 0.0372991000, 0.0742988000, 0.1867573000, 0.5221441000, 1.5013363000", \ - "0.0195977000, 0.0243834000, 0.0373390000, 0.0743974000, 0.1869557000, 0.5222392000, 1.5004334000", \ - "0.0198407000, 0.0245583000, 0.0374371000, 0.0744139000, 0.1868594000, 0.5219464000, 1.5013062000", \ - "0.0229981000, 0.0279016000, 0.0401076000, 0.0763234000, 0.1872161000, 0.5222139000, 1.5007484000", \ - "0.0308800000, 0.0355957000, 0.0473507000, 0.0806991000, 0.1887615000, 0.5220194000, 1.5005479000", \ - "0.0424974000, 0.0489905000, 0.0621579000, 0.0937697000, 0.1930567000, 0.5247267000, 1.4990452000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1754647000, 0.1815153000, 0.1950037000, 0.2221900000, 0.2763312000, 0.3983091000, 0.7285473000", \ - "0.1806138000, 0.1866812000, 0.2001881000, 0.2273445000, 0.2814787000, 0.4033890000, 0.7329094000", \ - "0.1932465000, 0.1993037000, 0.2128280000, 0.2396641000, 0.2938631000, 0.4160828000, 0.7462351000", \ - "0.2201979000, 0.2262565000, 0.2397740000, 0.2668297000, 0.3209424000, 0.4430773000, 0.7730511000", \ - "0.2780437000, 0.2841044000, 0.2976351000, 0.3247143000, 0.3788883000, 0.5011948000, 0.8314599000", \ - "0.3876081000, 0.3945259000, 0.4094091000, 0.4390636000, 0.4961025000, 0.6205424000, 0.9509681000", \ - "0.5693120000, 0.5775674000, 0.5956566000, 0.6307609000, 0.6955354000, 0.8273393000, 1.1603348000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0868364000, 0.0924523000, 0.1057366000, 0.1371263000, 0.2191022000, 0.4525853000, 1.1286295000", \ - "0.0911765000, 0.0967856000, 0.1101065000, 0.1414982000, 0.2234701000, 0.4565415000, 1.1342143000", \ - "0.1007208000, 0.1063122000, 0.1196188000, 0.1509835000, 0.2328160000, 0.4662048000, 1.1436497000", \ - "0.1221480000, 0.1277010000, 0.1409050000, 0.1721808000, 0.2540520000, 0.4880129000, 1.1642901000", \ - "0.1606674000, 0.1667308000, 0.1807163000, 0.2127188000, 0.2948411000, 0.5279495000, 1.2062288000", \ - "0.2117349000, 0.2190803000, 0.2350424000, 0.2689291000, 0.3512999000, 0.5843142000, 1.2649071000", \ - "0.2589436000, 0.2685016000, 0.2890472000, 0.3289846000, 0.4140288000, 0.6475376000, 1.3243802000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0258933000, 0.0296860000, 0.0383340000, 0.0586651000, 0.1089606000, 0.2509358000, 0.6903495000", \ - "0.0258448000, 0.0297176000, 0.0390461000, 0.0588980000, 0.1088084000, 0.2514509000, 0.6876827000", \ - "0.0258409000, 0.0297044000, 0.0384505000, 0.0589410000, 0.1091197000, 0.2509462000, 0.6903685000", \ - "0.0258020000, 0.0297117000, 0.0389013000, 0.0585195000, 0.1088668000, 0.2509039000, 0.6886230000", \ - "0.0260314000, 0.0299789000, 0.0387904000, 0.0588082000, 0.1087872000, 0.2510790000, 0.6915390000", \ - "0.0313274000, 0.0356376000, 0.0446286000, 0.0653849000, 0.1143775000, 0.2536094000, 0.6919771000", \ - "0.0430924000, 0.0473450000, 0.0580323000, 0.0799927000, 0.1302066000, 0.2645504000, 0.6907883000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0195913000, 0.0244081000, 0.0373435000, 0.0743946000, 0.1870681000, 0.5224323000, 1.5008721000", \ - "0.0195597000, 0.0243592000, 0.0372725000, 0.0743709000, 0.1870209000, 0.5209197000, 1.5019835000", \ - "0.0195704000, 0.0244706000, 0.0372813000, 0.0742798000, 0.1869283000, 0.5222619000, 1.5001727000", \ - "0.0196313000, 0.0245565000, 0.0373523000, 0.0743567000, 0.1866979000, 0.5227990000, 1.4982965000", \ - "0.0224099000, 0.0270729000, 0.0397507000, 0.0761142000, 0.1874077000, 0.5210212000, 1.5019234000", \ - "0.0286069000, 0.0335691000, 0.0457542000, 0.0806304000, 0.1888996000, 0.5205709000, 1.5026227000", \ - "0.0397134000, 0.0457201000, 0.0592028000, 0.0917587000, 0.1930681000, 0.5230024000, 1.4962389000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1564649000, 0.1625113000, 0.1760724000, 0.2032509000, 0.2573252000, 0.3794004000, 0.7094985000", \ - "0.1598119000, 0.1658771000, 0.1793932000, 0.2066793000, 0.2607024000, 0.3829765000, 0.7132521000", \ - "0.1691886000, 0.1751875000, 0.1886226000, 0.2158351000, 0.2699214000, 0.3920495000, 0.7217557000", \ - "0.1960308000, 0.2020863000, 0.2155360000, 0.2426676000, 0.2968254000, 0.4189996000, 0.7490605000", \ - "0.2617018000, 0.2677355000, 0.2811692000, 0.3081732000, 0.3621779000, 0.4843141000, 0.8144966000", \ - "0.3873420000, 0.3945048000, 0.4104795000, 0.4403986000, 0.4972694000, 0.6221265000, 0.9521623000", \ - "0.5850971000, 0.5948994000, 0.6148247000, 0.6525070000, 0.7169501000, 0.8461585000, 1.1792143000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0558410000, 0.0606723000, 0.0724040000, 0.1012692000, 0.1813736000, 0.4143315000, 1.0961093000", \ - "0.0606152000, 0.0654381000, 0.0771521000, 0.1060217000, 0.1860845000, 0.4176263000, 1.0934799000", \ - "0.0715914000, 0.0763845000, 0.0880405000, 0.1169376000, 0.1971483000, 0.4294494000, 1.1103507000", \ - "0.0934873000, 0.0985745000, 0.1104981000, 0.1396749000, 0.2199077000, 0.4537015000, 1.1434880000", \ - "0.1217783000, 0.1280185000, 0.1416141000, 0.1720981000, 0.2525594000, 0.4880940000, 1.1658172000", \ - "0.1488647000, 0.1571915000, 0.1748248000, 0.2090172000, 0.2901381000, 0.5227556000, 1.2003005000", \ - "0.1544315000, 0.1652930000, 0.1887297000, 0.2325463000, 0.3178596000, 0.5501363000, 1.2261624000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0258564000, 0.0297995000, 0.0384877000, 0.0585441000, 0.1088701000, 0.2509047000, 0.6903953000", \ - "0.0261112000, 0.0300026000, 0.0389623000, 0.0583099000, 0.1088053000, 0.2510164000, 0.6912470000", \ - "0.0258901000, 0.0298711000, 0.0389066000, 0.0582643000, 0.1086866000, 0.2512603000, 0.6877551000", \ - "0.0258681000, 0.0297865000, 0.0389783000, 0.0586669000, 0.1089987000, 0.2513645000, 0.6907995000", \ - "0.0260642000, 0.0299615000, 0.0390503000, 0.0587600000, 0.1091340000, 0.2514238000, 0.6907827000", \ - "0.0360795000, 0.0400301000, 0.0485027000, 0.0670598000, 0.1151378000, 0.2545412000, 0.6906004000", \ - "0.0512618000, 0.0568824000, 0.0675243000, 0.0875791000, 0.1327051000, 0.2635288000, 0.6918930000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0164360000, 0.0207641000, 0.0332396000, 0.0706902000, 0.1850525000, 0.5216266000, 1.5005025000", \ - "0.0164148000, 0.0207524000, 0.0332533000, 0.0707039000, 0.1852776000, 0.5234563000, 1.4976113000", \ - "0.0164641000, 0.0208059000, 0.0332908000, 0.0706621000, 0.1852674000, 0.5238021000, 1.5053958000", \ - "0.0186839000, 0.0226487000, 0.0344685000, 0.0711828000, 0.1853275000, 0.5202536000, 1.5044075000", \ - "0.0246536000, 0.0284861000, 0.0393385000, 0.0737580000, 0.1852756000, 0.5214499000, 1.5057265000", \ - "0.0349893000, 0.0392080000, 0.0498974000, 0.0804903000, 0.1869680000, 0.5191657000, 1.5043161000", \ - "0.0491816000, 0.0552095000, 0.0688503000, 0.0994934000, 0.1935202000, 0.5225637000, 1.4972963000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21o_4") { - leakage_power () { - value : 0.0051242000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0078745000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0051242000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0088385000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0051242000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0085104000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0022388000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0042370000; - when : "A1&A2&!B1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__a21o"; - cell_leakage_power : 0.0058839750; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087483000, 0.0087497000, 0.0087528000, 0.0087509000, 0.0087465000, 0.0087363000, 0.0087127000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006951100, -0.006958200, -0.006974600, -0.006961500, -0.006931400, -0.006862100, -0.006702300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045840000; - } - pin ("A2") { - capacitance : 0.0047940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082731000, 0.0082607000, 0.0082321000, 0.0082300000, 0.0082250000, 0.0082134000, 0.0081868000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008241200, -0.008240200, -0.008237800, -0.008234200, -0.008225800, -0.008206400, -0.008161600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050290000; - } - pin ("B1") { - capacitance : 0.0044150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041862000, 0.0041764000, 0.0041537000, 0.0041792000, 0.0042380000, 0.0043735000, 0.0046857000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003477800, -0.003489200, -0.003515600, -0.003515900, -0.003516400, -0.003517600, -0.003520500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047560000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0274778000, 0.0257842000, 0.0204869000, 0.0050696000, -0.051546200, -0.246660100, -0.882432800", \ - "0.0269723000, 0.0253111000, 0.0201012000, 0.0046633000, -0.051776900, -0.246946200, -0.882703100", \ - "0.0265437000, 0.0249533000, 0.0197571000, 0.0042438000, -0.052389000, -0.247404700, -0.883153000", \ - "0.0262383000, 0.0244738000, 0.0192471000, 0.0037275000, -0.052877300, -0.247824100, -0.883565200", \ - "0.0259339000, 0.0241452000, 0.0188981000, 0.0033086000, -0.053353700, -0.248451600, -0.883990600", \ - "0.0266870000, 0.0247809000, 0.0188823000, 0.0020311000, -0.053701900, -0.248686400, -0.884101900", \ - "0.0341319000, 0.0319583000, 0.0258450000, 0.0068038000, -0.053481300, -0.248732400, -0.883785000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0330636000, 0.0350609000, 0.0413218000, 0.0611292000, 0.1228294000, 0.3179810000, 0.9478509000", \ - "0.0327936000, 0.0347337000, 0.0410547000, 0.0609710000, 0.1226351000, 0.3178463000, 0.9473153000", \ - "0.0324691000, 0.0344188000, 0.0408446000, 0.0606755000, 0.1222320000, 0.3176016000, 0.9474776000", \ - "0.0322222000, 0.0341736000, 0.0404913000, 0.0601078000, 0.1216352000, 0.3174235000, 0.9503319000", \ - "0.0322422000, 0.0341090000, 0.0401928000, 0.0593635000, 0.1207750000, 0.3167311000, 0.9449057000", \ - "0.0337489000, 0.0355696000, 0.0414176000, 0.0604444000, 0.1206062000, 0.3157646000, 0.9467749000", \ - "0.0364213000, 0.0381387000, 0.0439368000, 0.0626222000, 0.1228693000, 0.3176702000, 0.9441429000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0334991000, 0.0317251000, 0.0263876000, 0.0109445000, -0.045676900, -0.240561000, -0.876117400", \ - "0.0333108000, 0.0315216000, 0.0262465000, 0.0107117000, -0.045843500, -0.240766000, -0.876348200", \ - "0.0330366000, 0.0313089000, 0.0259707000, 0.0104848000, -0.046152100, -0.241187500, -0.876547100", \ - "0.0327946000, 0.0310211000, 0.0256751000, 0.0101838000, -0.046375300, -0.241363600, -0.876892900", \ - "0.0325683000, 0.0308201000, 0.0254045000, 0.0097607000, -0.046868300, -0.241832300, -0.877248100", \ - "0.0319419000, 0.0300183000, 0.0243119000, 0.0088544000, -0.047405600, -0.242109500, -0.877314800", \ - "0.0406224000, 0.0385761000, 0.0322784000, 0.0132953000, -0.047088000, -0.242214400, -0.877104700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0342820000, 0.0362558000, 0.0426403000, 0.0623915000, 0.1239853000, 0.3191934000, 0.9489039000", \ - "0.0339682000, 0.0359562000, 0.0422826000, 0.0621959000, 0.1238344000, 0.3188638000, 0.9486144000", \ - "0.0337055000, 0.0356542000, 0.0420451000, 0.0618595000, 0.1234445000, 0.3187221000, 0.9484806000", \ - "0.0334580000, 0.0354327000, 0.0416588000, 0.0613353000, 0.1228855000, 0.3186205000, 0.9514069000", \ - "0.0333724000, 0.0352121000, 0.0413668000, 0.0607926000, 0.1221494000, 0.3180307000, 0.9476641000", \ - "0.0340376000, 0.0358707000, 0.0418630000, 0.0610341000, 0.1214467000, 0.3162526000, 0.9463069000", \ - "0.0361274000, 0.0379113000, 0.0436950000, 0.0622072000, 0.1234371000, 0.3183160000, 0.9435171000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0324514000, 0.0306536000, 0.0253277000, 0.0098852000, -0.046682800, -0.241552500, -0.877123800", \ - "0.0322419000, 0.0304352000, 0.0251607000, 0.0095180000, -0.047087500, -0.242059700, -0.877376800", \ - "0.0317360000, 0.0299028000, 0.0246901000, 0.0091220000, -0.047454300, -0.242513700, -0.877935400", \ - "0.0311761000, 0.0294491000, 0.0241930000, 0.0085777000, -0.047963700, -0.242974100, -0.878399900", \ - "0.0311684000, 0.0293973000, 0.0240696000, 0.0083267000, -0.048393400, -0.243286600, -0.878504000", \ - "0.0334300000, 0.0314627000, 0.0253489000, 0.0084344000, -0.047942300, -0.242581300, -0.877700100", \ - "0.0436091000, 0.0414602000, 0.0349051000, 0.0155753000, -0.045148700, -0.240076500, -0.875019100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016153630, 0.0052187940, 0.0168604900, 0.0544716200, 0.1759829000, 0.5685523000"); - values("0.0245626000, 0.0266064000, 0.0330239000, 0.0526668000, 0.1135416000, 0.3086566000, 0.9389211000", \ - "0.0245103000, 0.0265413000, 0.0329450000, 0.0525805000, 0.1134985000, 0.3085676000, 0.9348980000", \ - "0.0242575000, 0.0262599000, 0.0325656000, 0.0521222000, 0.1131899000, 0.3084561000, 0.9328988000", \ - "0.0237946000, 0.0257163000, 0.0318873000, 0.0513004000, 0.1124599000, 0.3077800000, 0.9372535000", \ - "0.0241055000, 0.0259411000, 0.0318148000, 0.0508071000, 0.1116123000, 0.3072772000, 0.9369822000", \ - "0.0249849000, 0.0267604000, 0.0326091000, 0.0517580000, 0.1117228000, 0.3062566000, 0.9364688000", \ - "0.0292107000, 0.0308523000, 0.0364108000, 0.0550087000, 0.1158274000, 0.3101484000, 0.9353101000"); - } - } - max_capacitance : 0.5685520000; - max_transition : 1.5080650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.1667089000, 0.1705674000, 0.1807010000, 0.2037151000, 0.2523315000, 0.3670029000, 0.6962084000", \ - "0.1715227000, 0.1753772000, 0.1855029000, 0.2083039000, 0.2572662000, 0.3717957000, 0.7009525000", \ - "0.1839464000, 0.1877690000, 0.1978677000, 0.2208456000, 0.2696686000, 0.3841860000, 0.7133577000", \ - "0.2123439000, 0.2161759000, 0.2261812000, 0.2490373000, 0.2980736000, 0.4125423000, 0.7417662000", \ - "0.2738375000, 0.2776756000, 0.2877082000, 0.3104602000, 0.3593439000, 0.4740748000, 0.8032273000", \ - "0.3905263000, 0.3950144000, 0.4062700000, 0.4312796000, 0.4839855000, 0.6010177000, 0.9311838000", \ - "0.5907647000, 0.5958105000, 0.6096319000, 0.6398450000, 0.7004462000, 0.8274088000, 1.1611672000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0792055000, 0.0828863000, 0.0928173000, 0.1185888000, 0.1902659000, 0.4136975000, 1.1290321000", \ - "0.0831300000, 0.0868059000, 0.0967804000, 0.1226076000, 0.1943042000, 0.4179284000, 1.1329810000", \ - "0.0931850000, 0.0968258000, 0.1068566000, 0.1325580000, 0.2041857000, 0.4275185000, 1.1429809000", \ - "0.1164868000, 0.1201262000, 0.1299970000, 0.1555562000, 0.2271631000, 0.4502684000, 1.1668938000", \ - "0.1524564000, 0.1563834000, 0.1667384000, 0.1929570000, 0.2645744000, 0.4890033000, 1.2025244000", \ - "0.1916982000, 0.1965845000, 0.2086638000, 0.2363082000, 0.3085659000, 0.5321583000, 1.2485090000", \ - "0.2121046000, 0.2184788000, 0.2345657000, 0.2688739000, 0.3430226000, 0.5654948000, 1.2805589000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0255522000, 0.0280821000, 0.0346573000, 0.0508314000, 0.0938622000, 0.2221205000, 0.6573893000", \ - "0.0255547000, 0.0280737000, 0.0345198000, 0.0513946000, 0.0940330000, 0.2224775000, 0.6565484000", \ - "0.0255340000, 0.0277512000, 0.0343106000, 0.0507223000, 0.0938892000, 0.2222570000, 0.6567179000", \ - "0.0253860000, 0.0278725000, 0.0348922000, 0.0507936000, 0.0937318000, 0.2220253000, 0.6573875000", \ - "0.0255751000, 0.0280530000, 0.0349782000, 0.0509857000, 0.0942029000, 0.2216931000, 0.6562850000", \ - "0.0312254000, 0.0337963000, 0.0408620000, 0.0580032000, 0.0996626000, 0.2264185000, 0.6588828000", \ - "0.0435838000, 0.0464076000, 0.0542099000, 0.0726916000, 0.1166850000, 0.2390488000, 0.6589572000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0193731000, 0.0224377000, 0.0318313000, 0.0606492000, 0.1566595000, 0.4750573000, 1.5031871000", \ - "0.0193656000, 0.0224547000, 0.0317908000, 0.0606000000, 0.1566688000, 0.4750269000, 1.5031799000", \ - "0.0193240000, 0.0224966000, 0.0317529000, 0.0604945000, 0.1564875000, 0.4744984000, 1.5031826000", \ - "0.0196103000, 0.0227217000, 0.0319863000, 0.0606526000, 0.1564419000, 0.4746661000, 1.5037449000", \ - "0.0224793000, 0.0254885000, 0.0344484000, 0.0627508000, 0.1573912000, 0.4740602000, 1.5010383000", \ - "0.0297750000, 0.0328684000, 0.0412979000, 0.0673344000, 0.1592594000, 0.4738858000, 1.5030900000", \ - "0.0418062000, 0.0456527000, 0.0554911000, 0.0796857000, 0.1638428000, 0.4754935000, 1.5002588000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.1789690000, 0.1828819000, 0.1930213000, 0.2158037000, 0.2637320000, 0.3772057000, 0.7064686000", \ - "0.1842585000, 0.1881712000, 0.1983185000, 0.2211609000, 0.2690282000, 0.3825235000, 0.7116340000", \ - "0.1973684000, 0.2012791000, 0.2114137000, 0.2342041000, 0.2823592000, 0.3956743000, 0.7249379000", \ - "0.2265678000, 0.2304777000, 0.2406150000, 0.2634019000, 0.3113485000, 0.4248725000, 0.7540166000", \ - "0.2891637000, 0.2930801000, 0.3032159000, 0.3258961000, 0.3740083000, 0.4877554000, 0.8165842000", \ - "0.4112793000, 0.4156516000, 0.4269158000, 0.4516750000, 0.5029182000, 0.6187523000, 0.9477154000", \ - "0.6181000000, 0.6234683000, 0.6371988000, 0.6670761000, 0.7262041000, 0.8504076000, 1.1830061000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0840004000, 0.0877201000, 0.0976883000, 0.1233646000, 0.1950546000, 0.4180092000, 1.1335686000", \ - "0.0881932000, 0.0918380000, 0.1018162000, 0.1276303000, 0.1992686000, 0.4226567000, 1.1379225000", \ - "0.0973611000, 0.1010033000, 0.1110333000, 0.1367450000, 0.2084193000, 0.4315551000, 1.1469846000", \ - "0.1180590000, 0.1216991000, 0.1315874000, 0.1572195000, 0.2289073000, 0.4519153000, 1.1684128000", \ - "0.1534077000, 0.1573463000, 0.1678135000, 0.1942218000, 0.2660085000, 0.4892663000, 1.2051552000", \ - "0.1977714000, 0.2024717000, 0.2145538000, 0.2425122000, 0.3152376000, 0.5383196000, 1.2537931000", \ - "0.2300110000, 0.2361857000, 0.2518082000, 0.2856657000, 0.3615406000, 0.5853615000, 1.2995061000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0260170000, 0.0284434000, 0.0349520000, 0.0505255000, 0.0930404000, 0.2203122000, 0.6569143000", \ - "0.0259900000, 0.0283878000, 0.0347688000, 0.0506457000, 0.0930903000, 0.2206009000, 0.6577096000", \ - "0.0261256000, 0.0285093000, 0.0349974000, 0.0504950000, 0.0928906000, 0.2208668000, 0.6569135000", \ - "0.0260119000, 0.0284303000, 0.0349098000, 0.0505887000, 0.0930124000, 0.2206867000, 0.6579301000", \ - "0.0260024000, 0.0287239000, 0.0347177000, 0.0504723000, 0.0927500000, 0.2207703000, 0.6566809000", \ - "0.0313011000, 0.0339602000, 0.0406455000, 0.0563300000, 0.0973993000, 0.2236620000, 0.6581443000", \ - "0.0433128000, 0.0462719000, 0.0538721000, 0.0713325000, 0.1133764000, 0.2357806000, 0.6582873000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0193831000, 0.0225205000, 0.0317290000, 0.0605641000, 0.1563800000, 0.4739302000, 1.5029724000", \ - "0.0193929000, 0.0224443000, 0.0317943000, 0.0606332000, 0.1566589000, 0.4750706000, 1.5033857000", \ - "0.0193446000, 0.0225175000, 0.0317715000, 0.0605527000, 0.1563951000, 0.4745414000, 1.5031703000", \ - "0.0194832000, 0.0226502000, 0.0319620000, 0.0607179000, 0.1565337000, 0.4746654000, 1.5036117000", \ - "0.0220012000, 0.0250666000, 0.0341806000, 0.0624144000, 0.1572862000, 0.4745911000, 1.5031678000", \ - "0.0278237000, 0.0309823000, 0.0403250000, 0.0669312000, 0.1586233000, 0.4740527000, 1.5025758000", \ - "0.0389087000, 0.0426030000, 0.0527071000, 0.0782833000, 0.1636048000, 0.4754738000, 1.4996989000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.1536402000, 0.1576062000, 0.1677444000, 0.1905571000, 0.2384588000, 0.3519686000, 0.6810947000", \ - "0.1570656000, 0.1610082000, 0.1711703000, 0.1939816000, 0.2423291000, 0.3553754000, 0.6847278000", \ - "0.1671333000, 0.1710480000, 0.1811008000, 0.2039052000, 0.2520921000, 0.3656219000, 0.6950172000", \ - "0.1942200000, 0.1981073000, 0.2082662000, 0.2309622000, 0.2791505000, 0.3927325000, 0.7218831000", \ - "0.2611191000, 0.2650255000, 0.2751031000, 0.2976796000, 0.3456586000, 0.4591856000, 0.7883175000", \ - "0.3910144000, 0.3957536000, 0.4078788000, 0.4334276000, 0.4843862000, 0.6004732000, 0.9302570000", \ - "0.5977439000, 0.6036122000, 0.6188354000, 0.6520439000, 0.7124349000, 0.8325155000, 1.1648997000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0544353000, 0.0576169000, 0.0665371000, 0.0903139000, 0.1601130000, 0.3810326000, 1.1000937000", \ - "0.0590325000, 0.0622123000, 0.0711173000, 0.0948771000, 0.1647808000, 0.3858829000, 1.1152925000", \ - "0.0699760000, 0.0731225000, 0.0819383000, 0.1056232000, 0.1756681000, 0.3968275000, 1.1117878000", \ - "0.0908976000, 0.0941777000, 0.1031807000, 0.1270713000, 0.1968986000, 0.4206701000, 1.1331958000", \ - "0.1173758000, 0.1213029000, 0.1315670000, 0.1567298000, 0.2271165000, 0.4500086000, 1.1640242000", \ - "0.1406823000, 0.1459290000, 0.1590848000, 0.1880410000, 0.2594577000, 0.4826555000, 1.1977949000", \ - "0.1371970000, 0.1441519000, 0.1619289000, 0.1994857000, 0.2764253000, 0.4989587000, 1.2125223000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0259005000, 0.0283259000, 0.0348526000, 0.0506371000, 0.0931228000, 0.2205883000, 0.6578232000", \ - "0.0259197000, 0.0283137000, 0.0346959000, 0.0506541000, 0.0927827000, 0.2210241000, 0.6571803000", \ - "0.0262439000, 0.0283099000, 0.0348177000, 0.0509282000, 0.0928776000, 0.2209568000, 0.6576477000", \ - "0.0261770000, 0.0286011000, 0.0346331000, 0.0505801000, 0.0929571000, 0.2204922000, 0.6564415000", \ - "0.0260781000, 0.0284484000, 0.0347977000, 0.0507030000, 0.0931648000, 0.2206822000, 0.6560777000", \ - "0.0359847000, 0.0385134000, 0.0455518000, 0.0593631000, 0.0994902000, 0.2240934000, 0.6585995000", \ - "0.0523576000, 0.0555971000, 0.0646863000, 0.0804370000, 0.1170669000, 0.2346419000, 0.6597344000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016153600, 0.0052187900, 0.0168605000, 0.0544716000, 0.1759830000, 0.5685520000"); - values("0.0161763000, 0.0189805000, 0.0278221000, 0.0566970000, 0.1541050000, 0.4737553000, 1.5080651000", \ - "0.0161765000, 0.0189896000, 0.0278410000, 0.0567404000, 0.1538318000, 0.4735923000, 1.5025577000", \ - "0.0162284000, 0.0190294000, 0.0278980000, 0.0567586000, 0.1537915000, 0.4735705000, 1.4981256000", \ - "0.0182533000, 0.0208620000, 0.0292042000, 0.0573284000, 0.1541527000, 0.4738149000, 1.5004109000", \ - "0.0237159000, 0.0261375000, 0.0339486000, 0.0601992000, 0.1547536000, 0.4721910000, 1.5048959000", \ - "0.0335015000, 0.0362073000, 0.0440379000, 0.0678078000, 0.1569791000, 0.4714880000, 1.5001856000", \ - "0.0472626000, 0.0512252000, 0.0616771000, 0.0853861000, 0.1646331000, 0.4738265000, 1.4983581000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21oi_1") { - leakage_power () { - value : 0.0028691000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0003427000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0028691000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0007136000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0028691000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0005573000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0002865000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0027093000; - when : "A1&A2&!B1"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__a21oi"; - cell_leakage_power : 0.0016520860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046211000, 0.0046223000, 0.0046252000, 0.0046255000, 0.0046262000, 0.0046277000, 0.0046313000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003672300, -0.003674100, -0.003678200, -0.003671900, -0.003657300, -0.003623600, -0.003546000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024260000; - } - pin ("A2") { - capacitance : 0.0023210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040597000, 0.0040515000, 0.0040325000, 0.0040330000, 0.0040341000, 0.0040367000, 0.0040426000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004038500, -0.004038300, -0.004038000, -0.004038500, -0.004039700, -0.004042400, -0.004048700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024240000; - } - pin ("B1") { - capacitance : 0.0023230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0018982000, 0.0018957000, 0.0018901000, 0.0019014000, 0.0019275000, 0.0019877000, 0.0021263000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001733400, -0.001733100, -0.001732200, -0.001731600, -0.001730100, -0.001726600, -0.001718700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024770000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0047644000, 0.0037333000, 0.0013459000, -0.004154700, -0.016899700, -0.046325600, -0.114186600", \ - "0.0046176000, 0.0035934000, 0.0012260000, -0.004268100, -0.016996000, -0.046432000, -0.114242700", \ - "0.0044224000, 0.0033828000, 0.0010281000, -0.004417000, -0.017096200, -0.046490600, -0.114329000", \ - "0.0041436000, 0.0031422000, 0.0008270000, -0.004591200, -0.017246900, -0.046598700, -0.114392900", \ - "0.0041040000, 0.0030710000, 0.0007057000, -0.004728500, -0.017394800, -0.046732400, -0.114459000", \ - "0.0045495000, 0.0034805000, 0.0010365000, -0.004567100, -0.017447500, -0.046691400, -0.114485700", \ - "0.0059567000, 0.0048052000, 0.0022178000, -0.003530200, -0.016530700, -0.046303000, -0.114420100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0070315000, 0.0081568000, 0.0106833000, 0.0162757000, 0.0290142000, 0.0581655000, 0.1251424000", \ - "0.0067801000, 0.0079233000, 0.0104749000, 0.0161313000, 0.0289417000, 0.0581261000, 0.1259277000", \ - "0.0065608000, 0.0076593000, 0.0102000000, 0.0159574000, 0.0287511000, 0.0580617000, 0.1258549000", \ - "0.0064279000, 0.0075122000, 0.0099829000, 0.0156161000, 0.0285049000, 0.0578864000, 0.1250811000", \ - "0.0063339000, 0.0073944000, 0.0098273000, 0.0154306000, 0.0283436000, 0.0575251000, 0.1248237000", \ - "0.0063119000, 0.0073722000, 0.0098065000, 0.0153861000, 0.0282299000, 0.0576696000, 0.1246271000", \ - "0.0065593000, 0.0075393000, 0.0099096000, 0.0153101000, 0.0283421000, 0.0576448000, 0.1251447000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0050676000, 0.0040230000, 0.0016303000, -0.003884300, -0.016626100, -0.046052200, -0.113881100", \ - "0.0049422000, 0.0039057000, 0.0015272000, -0.003983000, -0.016722600, -0.046142400, -0.113982700", \ - "0.0047602000, 0.0037361000, 0.0013737000, -0.004118700, -0.016826300, -0.046233500, -0.114049200", \ - "0.0045340000, 0.0035174000, 0.0011895000, -0.004250900, -0.016934300, -0.046302100, -0.114121100", \ - "0.0045793000, 0.0035393000, 0.0010846000, -0.004399000, -0.017024100, -0.046353800, -0.114129800", \ - "0.0047488000, 0.0036946000, 0.0012855000, -0.004290300, -0.017113000, -0.046481300, -0.114208500", \ - "0.0058509000, 0.0046933000, 0.0021760000, -0.003518700, -0.016524700, -0.046168100, -0.114121000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0102812000, 0.0113398000, 0.0137625000, 0.0193167000, 0.0320061000, 0.0611753000, 0.1282181000", \ - "0.0101449000, 0.0112065000, 0.0136702000, 0.0192357000, 0.0319817000, 0.0611355000, 0.1281008000", \ - "0.0099992000, 0.0110640000, 0.0135273000, 0.0191404000, 0.0319145000, 0.0610932000, 0.1281518000", \ - "0.0098785000, 0.0109489000, 0.0133868000, 0.0189881000, 0.0317760000, 0.0610459000, 0.1280721000", \ - "0.0097826000, 0.0108432000, 0.0132905000, 0.0188593000, 0.0315947000, 0.0608536000, 0.1279934000", \ - "0.0097580000, 0.0108044000, 0.0132493000, 0.0188525000, 0.0316467000, 0.0608330000, 0.1279382000", \ - "0.0100130000, 0.0110157000, 0.0133470000, 0.0187581000, 0.0317899000, 0.0611316000, 0.1282419000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0001410000, -0.000819300, -0.003134200, -0.008618200, -0.021402700, -0.050891300, -0.118805900", \ - "-1.37000e-05, -0.000954300, -0.003218900, -0.008634500, -0.021359400, -0.050828200, -0.118714200", \ - "-0.000251000, -0.001176500, -0.003401200, -0.008746900, -0.021391300, -0.050798500, -0.118663800", \ - "-0.000487800, -0.001433100, -0.003672400, -0.008975600, -0.021540700, -0.050865400, -0.118676100", \ - "-0.000254400, -0.001276800, -0.003616500, -0.009009400, -0.021688900, -0.050976000, -0.118724000", \ - "0.0003188000, -0.000794800, -0.003273000, -0.008784500, -0.021765100, -0.050970900, -0.118739600", \ - "0.0022458000, 0.0009957000, -0.001720600, -0.007658200, -0.020753900, -0.050701700, -0.118146000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0098103000, 0.0109194000, 0.0134201000, 0.0190535000, 0.0318221000, 0.0610448000, 0.1280240000", \ - "0.0095511000, 0.0106630000, 0.0131711000, 0.0188644000, 0.0317010000, 0.0609482000, 0.1280060000", \ - "0.0093424000, 0.0104048000, 0.0128555000, 0.0185778000, 0.0315006000, 0.0608515000, 0.1278758000", \ - "0.0092969000, 0.0103558000, 0.0127973000, 0.0183634000, 0.0312072000, 0.0606119000, 0.1278199000", \ - "0.0093253000, 0.0103467000, 0.0127379000, 0.0182625000, 0.0310172000, 0.0602979000, 0.1274821000", \ - "0.0098543000, 0.0108487000, 0.0131829000, 0.0186122000, 0.0311571000, 0.0602465000, 0.1272701000", \ - "0.0115123000, 0.0124909000, 0.0149272000, 0.0213536000, 0.0329529000, 0.0613026000, 0.1274609000"); - } - } - max_capacitance : 0.0741680000; - max_transition : 1.5047040000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0292366000, 0.0332307000, 0.0418398000, 0.0602929000, 0.1013762000, 0.1937037000, 0.4044020000", \ - "0.0332467000, 0.0372111000, 0.0458168000, 0.0643841000, 0.1053733000, 0.1977417000, 0.4084880000", \ - "0.0437284000, 0.0472849000, 0.0557225000, 0.0742684000, 0.1153830000, 0.2078222000, 0.4184735000", \ - "0.0609761000, 0.0665077000, 0.0774729000, 0.0984017000, 0.1392950000, 0.2308388000, 0.4417211000", \ - "0.0803080000, 0.0884776000, 0.1053219000, 0.1367922000, 0.1917197000, 0.2871634000, 0.4977369000", \ - "0.0950039000, 0.1075632000, 0.1328724000, 0.1801609000, 0.2647471000, 0.3994837000, 0.6237419000", \ - "0.0806510000, 0.0997553000, 0.1378712000, 0.2119956000, 0.3402130000, 0.5507781000, 0.8815571000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0699607000, 0.0798140000, 0.1015372000, 0.1499798000, 0.2596720000, 0.5111125000, 1.0886149000", \ - "0.0741475000, 0.0838990000, 0.1060762000, 0.1549961000, 0.2652038000, 0.5173203000, 1.1007669000", \ - "0.0865265000, 0.0963770000, 0.1180515000, 0.1676602000, 0.2785536000, 0.5302879000, 1.1194431000", \ - "0.1154598000, 0.1249630000, 0.1465047000, 0.1953203000, 0.3058794000, 0.5586747000, 1.1362520000", \ - "0.1660585000, 0.1787881000, 0.2052318000, 0.2573759000, 0.3681443000, 0.6232969000, 1.1999789000", \ - "0.2454068000, 0.2650819000, 0.3043500000, 0.3765665000, 0.5093799000, 0.7649040000, 1.3426994000", \ - "0.3654840000, 0.3977821000, 0.4616475000, 0.5759380000, 0.7662337000, 1.0863932000, 1.6741031000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0247645000, 0.0291650000, 0.0394405000, 0.0626756000, 0.1158906000, 0.2377813000, 0.5213558000", \ - "0.0242951000, 0.0289179000, 0.0391857000, 0.0623774000, 0.1159611000, 0.2387292000, 0.5191834000", \ - "0.0261836000, 0.0300844000, 0.0396034000, 0.0621279000, 0.1158199000, 0.2378465000, 0.5206202000", \ - "0.0376490000, 0.0422070000, 0.0517682000, 0.0695706000, 0.1172090000, 0.2388051000, 0.5208393000", \ - "0.0592975000, 0.0656250000, 0.0781037000, 0.1033591000, 0.1444312000, 0.2476301000, 0.5197366000", \ - "0.0971220000, 0.1068676000, 0.1261328000, 0.1606879000, 0.2211804000, 0.3242252000, 0.5490872000", \ - "0.1637932000, 0.1796244000, 0.2125160000, 0.2634696000, 0.3514114000, 0.4930869000, 0.7314829000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0460511000, 0.0583768000, 0.0868402000, 0.1518191000, 0.3015310000, 0.6446138000, 1.4343136000", \ - "0.0460975000, 0.0583509000, 0.0868379000, 0.1518099000, 0.3015840000, 0.6446437000, 1.4419462000", \ - "0.0461727000, 0.0584702000, 0.0867862000, 0.1525969000, 0.3008810000, 0.6460642000, 1.4474948000", \ - "0.0483940000, 0.0599318000, 0.0870590000, 0.1519971000, 0.3016596000, 0.6448282000, 1.4419352000", \ - "0.0665890000, 0.0781456000, 0.1022215000, 0.1596704000, 0.3030082000, 0.6465897000, 1.4355848000", \ - "0.1071570000, 0.1205791000, 0.1492928000, 0.2084516000, 0.3320071000, 0.6516286000, 1.4365483000", \ - "0.1908638000, 0.2087178000, 0.2454736000, 0.3182022000, 0.4584277000, 0.7410632000, 1.4510164000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0336276000, 0.0375980000, 0.0461672000, 0.0646666000, 0.1056675000, 0.1979156000, 0.4090566000", \ - "0.0379958000, 0.0418988000, 0.0504743000, 0.0690881000, 0.1100626000, 0.2023379000, 0.4130629000", \ - "0.0476307000, 0.0515111000, 0.0600115000, 0.0786410000, 0.1196677000, 0.2121669000, 0.4228247000", \ - "0.0652475000, 0.0699769000, 0.0802198000, 0.1004714000, 0.1419712000, 0.2346617000, 0.4459217000", \ - "0.0892540000, 0.0963119000, 0.1109342000, 0.1388978000, 0.1894455000, 0.2857638000, 0.4977388000", \ - "0.1125611000, 0.1236970000, 0.1463544000, 0.1896487000, 0.2649042000, 0.3903235000, 0.6171531000", \ - "0.1169349000, 0.1348822000, 0.1709153000, 0.2380518000, 0.3562361000, 0.5463627000, 0.8491732000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0875986000, 0.0968686000, 0.1186122000, 0.1675820000, 0.2790399000, 0.5345483000, 1.1217486000", \ - "0.0924333000, 0.1018339000, 0.1237321000, 0.1728484000, 0.2845736000, 0.5401564000, 1.1280487000", \ - "0.1050098000, 0.1145372000, 0.1362206000, 0.1856579000, 0.2976957000, 0.5537739000, 1.1413556000", \ - "0.1324927000, 0.1421989000, 0.1638037000, 0.2130083000, 0.3251331000, 0.5812509000, 1.1687474000", \ - "0.1847172000, 0.1959790000, 0.2208083000, 0.2715889000, 0.3835416000, 0.6398991000, 1.2284525000", \ - "0.2684356000, 0.2847678000, 0.3191489000, 0.3856584000, 0.5150293000, 0.7736058000, 1.3620641000", \ - "0.3965344000, 0.4224517000, 0.4757956000, 0.5758843000, 0.7544984000, 1.0737626000, 1.6723056000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0245268000, 0.0289741000, 0.0393119000, 0.0625452000, 0.1158757000, 0.2379766000, 0.5203321000", \ - "0.0243761000, 0.0289485000, 0.0391633000, 0.0624816000, 0.1158682000, 0.2377901000, 0.5197315000", \ - "0.0251441000, 0.0294354000, 0.0392477000, 0.0623541000, 0.1156101000, 0.2379656000, 0.5192724000", \ - "0.0332917000, 0.0375502000, 0.0462198000, 0.0661953000, 0.1167221000, 0.2387837000, 0.5202786000", \ - "0.0519651000, 0.0569479000, 0.0676730000, 0.0891398000, 0.1334317000, 0.2449696000, 0.5213754000", \ - "0.0873925000, 0.0944634000, 0.1092484000, 0.1381085000, 0.1919352000, 0.2942665000, 0.5385004000", \ - "0.1507914000, 0.1616032000, 0.1849366000, 0.2266964000, 0.3016834000, 0.4264134000, 0.6632461000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0620612000, 0.0745917000, 0.1037986000, 0.1702081000, 0.3231634000, 0.6749278000, 1.4826423000", \ - "0.0620670000, 0.0746424000, 0.1038045000, 0.1702600000, 0.3226652000, 0.6724408000, 1.4820697000", \ - "0.0620817000, 0.0747167000, 0.1037881000, 0.1702216000, 0.3231925000, 0.6752917000, 1.4809179000", \ - "0.0629950000, 0.0751841000, 0.1037875000, 0.1701841000, 0.3226163000, 0.6724057000, 1.4812345000", \ - "0.0787006000, 0.0902340000, 0.1156914000, 0.1767698000, 0.3232077000, 0.6730609000, 1.4776302000", \ - "0.1178820000, 0.1313134000, 0.1599276000, 0.2201836000, 0.3517292000, 0.6781848000, 1.4786042000", \ - "0.2005590000, 0.2176025000, 0.2546007000, 0.3261117000, 0.4683177000, 0.7677009000, 1.4955163000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0159580000, 0.0183263000, 0.0235272000, 0.0349811000, 0.0610219000, 0.1206980000, 0.2577920000", \ - "0.0206340000, 0.0230289000, 0.0283030000, 0.0398539000, 0.0659218000, 0.1256632000, 0.2627502000", \ - "0.0283588000, 0.0320077000, 0.0389512000, 0.0512123000, 0.0771721000, 0.1369484000, 0.2740582000", \ - "0.0367556000, 0.0429492000, 0.0537759000, 0.0728745000, 0.1039739000, 0.1634987000, 0.3000111000", \ - "0.0433728000, 0.0525560000, 0.0698445000, 0.0997237000, 0.1487252000, 0.2242195000, 0.3610305000", \ - "0.0395791000, 0.0538181000, 0.0812232000, 0.1283487000, 0.2059187000, 0.3224305000, 0.5006454000", \ - "0.0032486000, 0.0242410000, 0.0669605000, 0.1409372000, 0.2619791000, 0.4476115000, 0.7222248000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0649624000, 0.0749400000, 0.0970057000, 0.1465428000, 0.2587008000, 0.5144677000, 1.1020559000", \ - "0.0679162000, 0.0779366000, 0.1000679000, 0.1499611000, 0.2625803000, 0.5188299000, 1.1062755000", \ - "0.0780775000, 0.0875626000, 0.1095702000, 0.1597282000, 0.2726914000, 0.5293767000, 1.1188430000", \ - "0.1062524000, 0.1154104000, 0.1368252000, 0.1853406000, 0.2977174000, 0.5549208000, 1.1430645000", \ - "0.1598839000, 0.1728297000, 0.2000796000, 0.2515287000, 0.3628583000, 0.6178959000, 1.2069281000", \ - "0.2419978000, 0.2630889000, 0.3041735000, 0.3813884000, 0.5151891000, 0.7693350000, 1.3554580000", \ - "0.3790394000, 0.4080830000, 0.4677136000, 0.5828878000, 0.7870510000, 1.1179621000, 1.7042737000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0127740000, 0.0159974000, 0.0229612000, 0.0381835000, 0.0725837000, 0.1517055000, 0.3336124000", \ - "0.0136043000, 0.0164493000, 0.0229924000, 0.0381791000, 0.0726192000, 0.1523759000, 0.3341012000", \ - "0.0211588000, 0.0231143000, 0.0275338000, 0.0400362000, 0.0726780000, 0.1516807000, 0.3336727000", \ - "0.0359024000, 0.0384778000, 0.0440822000, 0.0551242000, 0.0806063000, 0.1524014000, 0.3336112000", \ - "0.0619073000, 0.0656447000, 0.0738495000, 0.0901722000, 0.1182513000, 0.1747373000, 0.3360301000", \ - "0.1078168000, 0.1135979000, 0.1255042000, 0.1495812000, 0.1917337000, 0.2656085000, 0.3921674000", \ - "0.1918463000, 0.2007218000, 0.2180982000, 0.2538600000, 0.3180610000, 0.4241133000, 0.6009362000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0618799000, 0.0745093000, 0.1036064000, 0.1703418000, 0.3227879000, 0.6746547000, 1.4822490000", \ - "0.0617297000, 0.0744341000, 0.1036278000, 0.1703439000, 0.3229131000, 0.6734094000, 1.4759793000", \ - "0.0612479000, 0.0740791000, 0.1035770000, 0.1703209000, 0.3227986000, 0.6728468000, 1.4835743000", \ - "0.0665117000, 0.0774123000, 0.1042795000, 0.1699185000, 0.3225517000, 0.6727377000, 1.4766524000", \ - "0.0936585000, 0.1061293000, 0.1293759000, 0.1835967000, 0.3237003000, 0.6731188000, 1.4772628000", \ - "0.1404823000, 0.1575328000, 0.1914483000, 0.2536697000, 0.3717621000, 0.6796080000, 1.4777833000", \ - "0.2141475000, 0.2393938000, 0.2906258000, 0.3826895000, 0.5418102000, 0.8030760000, 1.5047041000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21oi_2") { - leakage_power () { - value : 0.0022984000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0009833000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0022984000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0018995000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0022984000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0015859000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0002760000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0026604000; - when : "A1&A2&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a21oi"; - cell_leakage_power : 0.0017875370; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087968000, 0.0088015000, 0.0088122000, 0.0088129000, 0.0088145000, 0.0088182000, 0.0088267000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007034600, -0.007038700, -0.007048100, -0.007036900, -0.007011000, -0.006951300, -0.006813800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046060000; - } - pin ("A2") { - capacitance : 0.0048300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082841000, 0.0082771000, 0.0082611000, 0.0082585000, 0.0082526000, 0.0082390000, 0.0082076000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008282500, -0.008276700, -0.008263100, -0.008263300, -0.008263800, -0.008264900, -0.008267500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050520000; - } - pin ("B1") { - capacitance : 0.0044130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039188000, 0.0039129000, 0.0038992000, 0.0039234000, 0.0039792000, 0.0041079000, 0.0044044000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003542400, -0.003544400, -0.003549000, -0.003547700, -0.003544700, -0.003537800, -0.003522000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047070000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0083554000, 0.0071518000, 0.0040842000, -0.003633300, -0.023149400, -0.072622900, -0.197672900", \ - "0.0081017000, 0.0068932000, 0.0038464000, -0.003829700, -0.023320100, -0.072788500, -0.197847800", \ - "0.0077956000, 0.0065950000, 0.0035389000, -0.004100700, -0.023557300, -0.072936400, -0.198046700", \ - "0.0073106000, 0.0061371000, 0.0031132000, -0.004392300, -0.023784900, -0.073188100, -0.198108400", \ - "0.0072948000, 0.0061098000, 0.0030655000, -0.004620500, -0.023944500, -0.073331600, -0.198277400", \ - "0.0082193000, 0.0069257000, 0.0037968000, -0.004107400, -0.023789300, -0.073259200, -0.198218400", \ - "0.0106448000, 0.0094234000, 0.0061678000, -0.002124700, -0.022191100, -0.072333900, -0.198060800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0129984000, 0.0143597000, 0.0176805000, 0.0257446000, 0.0453397000, 0.0944759000, 0.2182500000", \ - "0.0125470000, 0.0139021000, 0.0172283000, 0.0253948000, 0.0454030000, 0.0951715000, 0.2189303000", \ - "0.0122316000, 0.0134861000, 0.0167763000, 0.0247803000, 0.0450081000, 0.0944491000, 0.2180758000", \ - "0.0119909000, 0.0132692000, 0.0164318000, 0.0244192000, 0.0442061000, 0.0945361000, 0.2186042000", \ - "0.0118227000, 0.0130876000, 0.0161850000, 0.0240136000, 0.0437906000, 0.0932005000, 0.2191081000", \ - "0.0117696000, 0.0130129000, 0.0161401000, 0.0240396000, 0.0436748000, 0.0931144000, 0.2168994000", \ - "0.0121585000, 0.0132429000, 0.0163043000, 0.0238532000, 0.0438065000, 0.0934593000, 0.2176852000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0095667000, 0.0083510000, 0.0052804000, -0.002445300, -0.021972000, -0.071423200, -0.196476900", \ - "0.0093046000, 0.0080877000, 0.0050269000, -0.002654900, -0.022192900, -0.071649500, -0.196722100", \ - "0.0089248000, 0.0077187000, 0.0046945000, -0.002970200, -0.022419700, -0.071875100, -0.196897800", \ - "0.0084189000, 0.0072541000, 0.0042709000, -0.003306500, -0.022657500, -0.072041900, -0.197024200", \ - "0.0085336000, 0.0073140000, 0.0042907000, -0.003568100, -0.022840900, -0.072106000, -0.197042500", \ - "0.0088385000, 0.0076993000, 0.0045308000, -0.003253100, -0.022923200, -0.072457100, -0.197239200", \ - "0.0107625000, 0.0094690000, 0.0062301000, -0.001850000, -0.021828700, -0.071757900, -0.197116000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0195110000, 0.0207300000, 0.0238554000, 0.0316905000, 0.0512702000, 0.1003882000, 0.2240212000", \ - "0.0191708000, 0.0204504000, 0.0236023000, 0.0314954000, 0.0511732000, 0.1002942000, 0.2239485000", \ - "0.0188553000, 0.0201133000, 0.0232745000, 0.0311855000, 0.0509087000, 0.1001921000, 0.2238845000", \ - "0.0186650000, 0.0199045000, 0.0230528000, 0.0309119000, 0.0506461000, 0.0999633000, 0.2237600000", \ - "0.0184907000, 0.0197075000, 0.0228665000, 0.0306947000, 0.0502867000, 0.0996700000, 0.2234883000", \ - "0.0184271000, 0.0196504000, 0.0227914000, 0.0306691000, 0.0504663000, 0.0997997000, 0.2231657000", \ - "0.0187555000, 0.0198982000, 0.0228951000, 0.0305049000, 0.0504588000, 0.0997691000, 0.2238202000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("-0.000623700, -0.001711600, -0.004604700, -0.012219500, -0.031807400, -0.081449600, -0.206692200", \ - "-0.000950700, -0.001987600, -0.004803400, -0.012288500, -0.031760200, -0.081312900, -0.206514000", \ - "-0.001334200, -0.002421800, -0.005127700, -0.012513300, -0.031829400, -0.081256500, -0.206400700", \ - "-0.001489900, -0.002710500, -0.005521600, -0.012945500, -0.032114300, -0.081367200, -0.206406500", \ - "-0.001260800, -0.002447000, -0.005475900, -0.013039000, -0.032532500, -0.081623000, -0.206473000", \ - "-0.000230100, -0.001532400, -0.004766200, -0.012613500, -0.032073400, -0.081716000, -0.206636100", \ - "0.0034079000, 0.0019184000, -0.001665000, -0.009910600, -0.030297100, -0.079761400, -0.205946000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0182262000, 0.0195526000, 0.0227954000, 0.0308349000, 0.0505434000, 0.0996942000, 0.2233625000", \ - "0.0177870000, 0.0190959000, 0.0223559000, 0.0303454000, 0.0502865000, 0.0996572000, 0.2234297000", \ - "0.0174965000, 0.0187463000, 0.0219585000, 0.0299072000, 0.0498122000, 0.0994198000, 0.2233882000", \ - "0.0171965000, 0.0184602000, 0.0216127000, 0.0295939000, 0.0493120000, 0.0988999000, 0.2227902000", \ - "0.0173855000, 0.0186018000, 0.0216680000, 0.0294281000, 0.0490128000, 0.0983793000, 0.2225364000", \ - "0.0184431000, 0.0196160000, 0.0225479000, 0.0301491000, 0.0493155000, 0.0982455000, 0.2217873000", \ - "0.0208847000, 0.0219426000, 0.0248384000, 0.0325223000, 0.0516071000, 0.0995773000, 0.2222581000"); - } - } - max_capacitance : 0.1281840000; - max_transition : 1.5008840000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0234585000, 0.0258557000, 0.0314719000, 0.0445254000, 0.0752649000, 0.1499284000, 0.3354227000", \ - "0.0276339000, 0.0299770000, 0.0355515000, 0.0486261000, 0.0793531000, 0.1540784000, 0.3395351000", \ - "0.0382765000, 0.0406478000, 0.0459159000, 0.0586108000, 0.0892656000, 0.1639685000, 0.3495471000", \ - "0.0529799000, 0.0565540000, 0.0645319000, 0.0811096000, 0.1132619000, 0.1869332000, 0.3725021000", \ - "0.0679856000, 0.0733069000, 0.0852540000, 0.1103994000, 0.1581317000, 0.2428373000, 0.4278185000", \ - "0.0741138000, 0.0822975000, 0.1005763000, 0.1386197000, 0.2121246000, 0.3388179000, 0.5552834000", \ - "0.0430327000, 0.0553590000, 0.0827233000, 0.1417715000, 0.2555051000, 0.4536174000, 0.7811977000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0704350000, 0.0774896000, 0.0945770000, 0.1357852000, 0.2369627000, 0.4885350000, 1.1219468000", \ - "0.0746153000, 0.0815201000, 0.0987221000, 0.1405715000, 0.2427856000, 0.4967607000, 1.1332945000", \ - "0.0873673000, 0.0940666000, 0.1108086000, 0.1520915000, 0.2554174000, 0.5112072000, 1.1416811000", \ - "0.1163554000, 0.1230529000, 0.1395715000, 0.1804257000, 0.2818979000, 0.5385455000, 1.1741426000", \ - "0.1664955000, 0.1751279000, 0.1956541000, 0.2414019000, 0.3432408000, 0.5960927000, 1.2374693000", \ - "0.2474930000, 0.2609992000, 0.2904600000, 0.3532424000, 0.4774121000, 0.7350378000, 1.3709585000", \ - "0.3734308000, 0.3953488000, 0.4447185000, 0.5426440000, 0.7197491000, 1.0468123000, 1.6953031000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0211086000, 0.0235874000, 0.0298151000, 0.0453820000, 0.0841742000, 0.1827484000, 0.4316089000", \ - "0.0202027000, 0.0227726000, 0.0293381000, 0.0450705000, 0.0840798000, 0.1827979000, 0.4314609000", \ - "0.0235212000, 0.0255599000, 0.0309326000, 0.0453178000, 0.0839581000, 0.1826203000, 0.4318527000", \ - "0.0339408000, 0.0369264000, 0.0433630000, 0.0567085000, 0.0887590000, 0.1830454000, 0.4316554000", \ - "0.0539016000, 0.0579132000, 0.0667210000, 0.0858013000, 0.1220775000, 0.1994819000, 0.4316293000", \ - "0.0889158000, 0.0952496000, 0.1096753000, 0.1377053000, 0.1888972000, 0.2811719000, 0.4739122000", \ - "0.1501839000, 0.1605393000, 0.1842226000, 0.2287385000, 0.3041295000, 0.4371910000, 0.6639768000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0436633000, 0.0519710000, 0.0739916000, 0.1290379000, 0.2659681000, 0.6116678000, 1.4848873000", \ - "0.0437719000, 0.0522369000, 0.0741327000, 0.1291282000, 0.2679725000, 0.6161599000, 1.4879455000", \ - "0.0435891000, 0.0522967000, 0.0740921000, 0.1289290000, 0.2680032000, 0.6140247000, 1.4866470000", \ - "0.0457139000, 0.0537062000, 0.0745700000, 0.1290028000, 0.2668747000, 0.6163134000, 1.4868859000", \ - "0.0618084000, 0.0700654000, 0.0897403000, 0.1374826000, 0.2680907000, 0.6121871000, 1.4954475000", \ - "0.0977669000, 0.1069906000, 0.1296213000, 0.1811270000, 0.2991660000, 0.6191198000, 1.4861569000", \ - "0.1761773000, 0.1885681000, 0.2163191000, 0.2786396000, 0.4105350000, 0.7055732000, 1.5008843000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0285481000, 0.0309182000, 0.0365294000, 0.0496253000, 0.0803770000, 0.1550135000, 0.3404790000", \ - "0.0327911000, 0.0351762000, 0.0407443000, 0.0538165000, 0.0846028000, 0.1591854000, 0.3448271000", \ - "0.0421495000, 0.0445893000, 0.0501813000, 0.0631735000, 0.0939435000, 0.1687130000, 0.3542837000", \ - "0.0574287000, 0.0606090000, 0.0679699000, 0.0832999000, 0.1155758000, 0.1907306000, 0.3763164000", \ - "0.0767015000, 0.0812369000, 0.0920458000, 0.1137668000, 0.1572290000, 0.2401927000, 0.4266828000", \ - "0.0907349000, 0.0982425000, 0.1144212000, 0.1485232000, 0.2146052000, 0.3300302000, 0.5414607000", \ - "0.0757085000, 0.0867515000, 0.1122562000, 0.1671554000, 0.2705442000, 0.4504700000, 0.7473765000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0881340000, 0.0942196000, 0.1094456000, 0.1471179000, 0.2408917000, 0.4753338000, 1.0650331000", \ - "0.0927901000, 0.0990408000, 0.1143272000, 0.1522877000, 0.2462928000, 0.4812034000, 1.0718610000", \ - "0.1056566000, 0.1118926000, 0.1270641000, 0.1653903000, 0.2595905000, 0.4945264000, 1.0847735000", \ - "0.1348692000, 0.1408744000, 0.1561163000, 0.1940498000, 0.2883249000, 0.5237995000, 1.1139557000", \ - "0.1902233000, 0.1977069000, 0.2154370000, 0.2557013000, 0.3497213000, 0.5849615000, 1.1756639000", \ - "0.2815931000, 0.2920510000, 0.3170528000, 0.3710074000, 0.4850365000, 0.7249721000, 1.3183004000", \ - "0.4251879000, 0.4416236000, 0.4814352000, 0.5646431000, 0.7254614000, 1.0296821000, 1.6405455000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0209304000, 0.0234256000, 0.0297053000, 0.0452125000, 0.0842666000, 0.1825232000, 0.4309810000", \ - "0.0206308000, 0.0231856000, 0.0295412000, 0.0451248000, 0.0842403000, 0.1831149000, 0.4317153000", \ - "0.0220075000, 0.0242893000, 0.0300812000, 0.0452181000, 0.0840391000, 0.1829630000, 0.4310713000", \ - "0.0303185000, 0.0327327000, 0.0383176000, 0.0519760000, 0.0866628000, 0.1829426000, 0.4312835000", \ - "0.0477601000, 0.0510698000, 0.0581315000, 0.0745086000, 0.1088346000, 0.1930139000, 0.4317446000", \ - "0.0806609000, 0.0856079000, 0.0957835000, 0.1179452000, 0.1613180000, 0.2493862000, 0.4587015000", \ - "0.1400293000, 0.1476705000, 0.1639957000, 0.1977100000, 0.2609354000, 0.3754612000, 0.5946711000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0563680000, 0.0645023000, 0.0849565000, 0.1360036000, 0.2649555000, 0.5875816000, 1.3943821000", \ - "0.0563348000, 0.0645332000, 0.0849432000, 0.1358588000, 0.2643162000, 0.5857319000, 1.3952307000", \ - "0.0563150000, 0.0645400000, 0.0848793000, 0.1359705000, 0.2640012000, 0.5854114000, 1.3945413000", \ - "0.0569812000, 0.0649494000, 0.0850116000, 0.1360600000, 0.2639519000, 0.5850857000, 1.3930818000", \ - "0.0718520000, 0.0792528000, 0.0974168000, 0.1432449000, 0.2656056000, 0.5864184000, 1.3946800000", \ - "0.1074710000, 0.1164776000, 0.1376679000, 0.1863762000, 0.2976592000, 0.5930284000, 1.3998634000", \ - "0.1855945000, 0.1975744000, 0.2241878000, 0.2842051000, 0.4085141000, 0.6817036000, 1.4136770000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0141037000, 0.0154592000, 0.0186898000, 0.0264855000, 0.0455793000, 0.0933741000, 0.2136252000", \ - "0.0185035000, 0.0199409000, 0.0232801000, 0.0311872000, 0.0503443000, 0.0981431000, 0.2184457000", \ - "0.0243723000, 0.0268245000, 0.0320027000, 0.0420827000, 0.0614434000, 0.1091854000, 0.2294937000", \ - "0.0299747000, 0.0339320000, 0.0419218000, 0.0580279000, 0.0858934000, 0.1354260000, 0.2550731000", \ - "0.0306929000, 0.0369354000, 0.0502937000, 0.0759794000, 0.1198903000, 0.1914732000, 0.3149406000", \ - "0.0154284000, 0.0252930000, 0.0470958000, 0.0865328000, 0.1557426000, 0.2687553000, 0.4463793000", \ - "-0.045583100, -0.030379200, 0.0023169000, 0.0657295000, 0.1760791000, 0.3525997000, 0.6318039000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0616192000, 0.0682867000, 0.0838725000, 0.1225422000, 0.2170830000, 0.4525224000, 1.0427396000", \ - "0.0647887000, 0.0714446000, 0.0871949000, 0.1255579000, 0.2205236000, 0.4562883000, 1.0464010000", \ - "0.0757656000, 0.0819322000, 0.0975661000, 0.1355927000, 0.2306755000, 0.4667857000, 1.0576486000", \ - "0.1049093000, 0.1107130000, 0.1255553000, 0.1633740000, 0.2569462000, 0.4933310000, 1.0856015000", \ - "0.1603890000, 0.1690424000, 0.1891919000, 0.2310629000, 0.3243843000, 0.5587203000, 1.1501439000", \ - "0.2482152000, 0.2614086000, 0.2922820000, 0.3563809000, 0.4785004000, 0.7146054000, 1.3036130000", \ - "0.3995013000, 0.4185702000, 0.4625290000, 0.5579686000, 0.7431774000, 1.0671604000, 1.6645002000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0095400000, 0.0113436000, 0.0158137000, 0.0264184000, 0.0516810000, 0.1148881000, 0.2737325000", \ - "0.0110336000, 0.0124878000, 0.0163695000, 0.0264607000, 0.0516858000, 0.1147357000, 0.2734692000", \ - "0.0190435000, 0.0202050000, 0.0230806000, 0.0303096000, 0.0524282000, 0.1147655000, 0.2737087000", \ - "0.0333149000, 0.0348416000, 0.0386774000, 0.0469898000, 0.0646020000, 0.1173724000, 0.2739397000", \ - "0.0584220000, 0.0605560000, 0.0657711000, 0.0778005000, 0.1018256000, 0.1479337000, 0.2796322000", \ - "0.1031944000, 0.1061988000, 0.1140986000, 0.1322191000, 0.1693623000, 0.2334268000, 0.3491095000", \ - "0.1853039000, 0.1897215000, 0.2021839000, 0.2290633000, 0.2835594000, 0.3836533000, 0.5520545000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0560266000, 0.0643649000, 0.0847640000, 0.1362160000, 0.2641088000, 0.5870635000, 1.3993650000", \ - "0.0558612000, 0.0641709000, 0.0846173000, 0.1359417000, 0.2638563000, 0.5861314000, 1.3941674000", \ - "0.0552965000, 0.0636867000, 0.0844877000, 0.1359661000, 0.2643877000, 0.5853425000, 1.3937794000", \ - "0.0605327000, 0.0677455000, 0.0861934000, 0.1351358000, 0.2640089000, 0.5862528000, 1.3991076000", \ - "0.0856907000, 0.0942773000, 0.1133828000, 0.1533348000, 0.2674068000, 0.5855177000, 1.3950562000", \ - "0.1291262000, 0.1407896000, 0.1670744000, 0.2197104000, 0.3210104000, 0.5957310000, 1.3991899000", \ - "0.1988686000, 0.2168420000, 0.2552878000, 0.3343094000, 0.4748869000, 0.7312506000, 1.4237073000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a21oi_4") { - leakage_power () { - value : 0.0037804000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0024464000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0037807000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0043513000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0037807000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0035496000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0003708000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0035062000; - when : "A1&A2&!B1"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__a21oi"; - cell_leakage_power : 0.0031957700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0085710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0176627000, 0.0176647000, 0.0176693000, 0.0176767000, 0.0176937000, 0.0177329000, 0.0178234000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013210700, -0.013205000, -0.013191600, -0.013160000, -0.013087000, -0.012918900, -0.012531300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089170000; - } - pin ("A2") { - capacitance : 0.0092380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0087670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0164539000, 0.0164246000, 0.0163571000, 0.0163522000, 0.0163411000, 0.0163154000, 0.0162562000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016374300, -0.016358500, -0.016322100, -0.016320300, -0.016316000, -0.016306000, -0.016283100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0097100000; - } - pin ("B1") { - capacitance : 0.0085960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079063000, 0.0078853000, 0.0078369000, 0.0078799000, 0.0079788000, 0.0082069000, 0.0087326000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006904200, -0.006903100, -0.006900400, -0.006895700, -0.006884800, -0.006859600, -0.006801600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092270000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("0.0160100000, 0.0146164000, 0.0107003000, -3.67000e-05, -0.029765500, -0.112225300, -0.340738000", \ - "0.0154877000, 0.0141227000, 0.0102400000, -0.000481900, -0.030094800, -0.112584600, -0.341119100", \ - "0.0147161000, 0.0133482000, 0.0095153000, -0.001078800, -0.030642400, -0.113008400, -0.341536400", \ - "0.0136958000, 0.0123339000, 0.0087090000, -0.001829400, -0.031248000, -0.113498200, -0.341832800", \ - "0.0135495000, 0.0121518000, 0.0084323000, -0.002128400, -0.031674100, -0.113788400, -0.342271100", \ - "0.0155387000, 0.0140834000, 0.0099603000, -0.001415500, -0.031509800, -0.113754600, -0.342075600", \ - "0.0192814000, 0.0177658000, 0.0134339000, 0.0020592000, -0.028714700, -0.112502700, -0.342228200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("0.0245839000, 0.0261919000, 0.0305010000, 0.0418689000, 0.0718377000, 0.1539028000, 0.3827241000", \ - "0.0236878000, 0.0252792000, 0.0295306000, 0.0411230000, 0.0714105000, 0.1548461000, 0.3829275000", \ - "0.0229696000, 0.0244674000, 0.0286299000, 0.0399911000, 0.0706113000, 0.1533308000, 0.3798184000", \ - "0.0225087000, 0.0239926000, 0.0280340000, 0.0392161000, 0.0695515000, 0.1534905000, 0.3794085000", \ - "0.0220932000, 0.0235537000, 0.0275719000, 0.0384716000, 0.0686501000, 0.1512764000, 0.3785113000", \ - "0.0220257000, 0.0234543000, 0.0274337000, 0.0384559000, 0.0683968000, 0.1509986000, 0.3774860000", \ - "0.0225028000, 0.0238276000, 0.0274343000, 0.0379557000, 0.0685071000, 0.1510636000, 0.3785388000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("0.0189295000, 0.0175048000, 0.0135890000, 0.0028487000, -0.026859300, -0.109374500, -0.337905200", \ - "0.0184176000, 0.0170017000, 0.0131090000, 0.0023912000, -0.027312700, -0.109788800, -0.338314400", \ - "0.0176674000, 0.0162818000, 0.0124433000, 0.0018022000, -0.027803900, -0.110238700, -0.338723100", \ - "0.0167596000, 0.0153980000, 0.0115883000, 0.0011001000, -0.028311500, -0.110622200, -0.339027600", \ - "0.0165243000, 0.0151472000, 0.0111949000, 0.0005495000, -0.028712300, -0.110727000, -0.339046800", \ - "0.0171449000, 0.0158516000, 0.0118297000, 0.0009848000, -0.028716800, -0.111496800, -0.339392400", \ - "0.0203859000, 0.0189749000, 0.0148125000, 0.0036139000, -0.026900700, -0.110133000, -0.339314800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("0.0387408000, 0.0402516000, 0.0442085000, 0.0551265000, 0.0849807000, 0.1671127000, 0.3931873000", \ - "0.0380820000, 0.0395421000, 0.0435954000, 0.0546534000, 0.0846505000, 0.1669436000, 0.3927868000", \ - "0.0374738000, 0.0389158000, 0.0429699000, 0.0540081000, 0.0841868000, 0.1665764000, 0.3927683000", \ - "0.0370219000, 0.0383739000, 0.0423688000, 0.0534383000, 0.0836971000, 0.1660855000, 0.3924691000", \ - "0.0365073000, 0.0380068000, 0.0420169000, 0.0529156000, 0.0829307000, 0.1655618000, 0.3917991000", \ - "0.0365221000, 0.0378742000, 0.0418895000, 0.0528352000, 0.0829947000, 0.1654112000, 0.3915716000", \ - "0.0367134000, 0.0380695000, 0.0418534000, 0.0524787000, 0.0832277000, 0.1659130000, 0.3923051000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("-0.000178600, -0.001441100, -0.005022100, -0.015454400, -0.045183200, -0.127966500, -0.356849800", \ - "-0.000822800, -0.002021000, -0.005491200, -0.015652200, -0.045100100, -0.127715600, -0.356513000", \ - "-0.001569200, -0.002780700, -0.006288400, -0.016236800, -0.045290100, -0.127607800, -0.356270400", \ - "-0.002277700, -0.003574600, -0.007183700, -0.017158400, -0.045939000, -0.127805600, -0.356249200", \ - "-0.001535500, -0.002925700, -0.006727400, -0.017040000, -0.046494700, -0.128264800, -0.356381600", \ - "0.0002981000, -0.001201100, -0.005283000, -0.016348200, -0.045885500, -0.128515400, -0.356704100", \ - "0.0067197000, 0.0050363000, 0.0004822000, -0.011555800, -0.042962400, -0.125568600, -0.356146700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013805730, 0.0038119630, 0.0105253900, 0.0290621300, 0.0802447800, 0.2215675000"); - values("0.0359073000, 0.0374439000, 0.0416454000, 0.0528963000, 0.0831943000, 0.1654002000, 0.3915609000", \ - "0.0351250000, 0.0365980000, 0.0407347000, 0.0521921000, 0.0826883000, 0.1652002000, 0.3914749000", \ - "0.0343364000, 0.0358225000, 0.0399558000, 0.0512949000, 0.0817728000, 0.1645821000, 0.3912592000", \ - "0.0340924000, 0.0355626000, 0.0395722000, 0.0505803000, 0.0807197000, 0.1637268000, 0.3907216000", \ - "0.0340947000, 0.0354957000, 0.0393985000, 0.0502459000, 0.0801303000, 0.1625945000, 0.3897599000", \ - "0.0370809000, 0.0384560000, 0.0422412000, 0.0528237000, 0.0821207000, 0.1637129000, 0.3880777000", \ - "0.0415913000, 0.0428849000, 0.0466998000, 0.0575601000, 0.0857223000, 0.1654100000, 0.3897643000"); - } - } - max_capacitance : 0.2215680000; - max_transition : 1.4966630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0246992000, 0.0263024000, 0.0304106000, 0.0410125000, 0.0678401000, 0.1380803000, 0.3284191000", \ - "0.0287528000, 0.0303059000, 0.0344198000, 0.0449538000, 0.0717621000, 0.1421019000, 0.3323391000", \ - "0.0391000000, 0.0406930000, 0.0447374000, 0.0548324000, 0.0815114000, 0.1516950000, 0.3419164000", \ - "0.0539156000, 0.0562234000, 0.0620181000, 0.0758049000, 0.1047227000, 0.1747259000, 0.3650390000", \ - "0.0682020000, 0.0716078000, 0.0802008000, 0.1009026000, 0.1450502000, 0.2294386000, 0.4194306000", \ - "0.0708632000, 0.0760541000, 0.0893124000, 0.1215272000, 0.1892958000, 0.3160761000, 0.5451449000", \ - "0.0329337000, 0.0408214000, 0.0602664000, 0.1091740000, 0.2135064000, 0.4116788000, 0.7576772000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0750266000, 0.0797863000, 0.0926365000, 0.1260724000, 0.2144161000, 0.4553959000, 1.1264553000", \ - "0.0788206000, 0.0836378000, 0.0963492000, 0.1303970000, 0.2206709000, 0.4648922000, 1.1340058000", \ - "0.0914359000, 0.0958637000, 0.1082775000, 0.1416296000, 0.2321347000, 0.4742727000, 1.1387330000", \ - "0.1205273000, 0.1250511000, 0.1373143000, 0.1697234000, 0.2593165000, 0.5051595000, 1.1692536000", \ - "0.1719356000, 0.1776844000, 0.1927567000, 0.2304034000, 0.3200600000, 0.5627075000, 1.2301592000", \ - "0.2563241000, 0.2650938000, 0.2868255000, 0.3391377000, 0.4519958000, 0.7019299000, 1.3689805000", \ - "0.3922306000, 0.4065449000, 0.4417791000, 0.5239923000, 0.6878029000, 1.0084236000, 1.6948052000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0237953000, 0.0254264000, 0.0298570000, 0.0421778000, 0.0761349000, 0.1706823000, 0.4346524000", \ - "0.0227089000, 0.0243467000, 0.0291293000, 0.0418578000, 0.0760946000, 0.1711810000, 0.4347354000", \ - "0.0255739000, 0.0268890000, 0.0307350000, 0.0420823000, 0.0756712000, 0.1710417000, 0.4347011000", \ - "0.0352760000, 0.0371595000, 0.0423320000, 0.0541057000, 0.0819962000, 0.1712114000, 0.4346026000", \ - "0.0548268000, 0.0575359000, 0.0644661000, 0.0804540000, 0.1146775000, 0.1911494000, 0.4352762000", \ - "0.0900704000, 0.0942685000, 0.1048262000, 0.1281075000, 0.1751626000, 0.2719571000, 0.4789162000", \ - "0.1522599000, 0.1588400000, 0.1759171000, 0.2133319000, 0.2874350000, 0.4193671000, 0.6672240000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0467260000, 0.0524283000, 0.0684499000, 0.1124418000, 0.2332804000, 0.5658687000, 1.4956092000", \ - "0.0466227000, 0.0523710000, 0.0683550000, 0.1125319000, 0.2335217000, 0.5705383000, 1.4966625000", \ - "0.0468068000, 0.0525925000, 0.0684013000, 0.1120551000, 0.2333967000, 0.5663319000, 1.4828127000", \ - "0.0484445000, 0.0538229000, 0.0689868000, 0.1124572000, 0.2333526000, 0.5698152000, 1.4816560000", \ - "0.0646310000, 0.0699947000, 0.0845821000, 0.1227971000, 0.2360603000, 0.5660067000, 1.4815442000", \ - "0.0996765000, 0.1055815000, 0.1224559000, 0.1642453000, 0.2706902000, 0.5735811000, 1.4800224000", \ - "0.1774712000, 0.1853416000, 0.2068150000, 0.2567463000, 0.3780628000, 0.6619884000, 1.4964621000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0303720000, 0.0319421000, 0.0360462000, 0.0465930000, 0.0734489000, 0.1436749000, 0.3338050000", \ - "0.0345541000, 0.0361274000, 0.0402576000, 0.0507694000, 0.0776014000, 0.1478207000, 0.3379790000", \ - "0.0434589000, 0.0450755000, 0.0491940000, 0.0596294000, 0.0864283000, 0.1566288000, 0.3469683000", \ - "0.0582558000, 0.0602947000, 0.0652601000, 0.0777804000, 0.1065639000, 0.1770607000, 0.3676280000", \ - "0.0760603000, 0.0789380000, 0.0865548000, 0.1045777000, 0.1430287000, 0.2231852000, 0.4154668000", \ - "0.0872149000, 0.0918042000, 0.1033720000, 0.1311212000, 0.1900211000, 0.3022428000, 0.5220377000", \ - "0.0635701000, 0.0704689000, 0.0891165000, 0.1331368000, 0.2257614000, 0.4016808000, 0.7096582000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.1000751000, 0.1046043000, 0.1162003000, 0.1478840000, 0.2332025000, 0.4665976000, 1.1106092000", \ - "0.1042715000, 0.1085854000, 0.1206454000, 0.1524753000, 0.2383677000, 0.4724077000, 1.1153842000", \ - "0.1167402000, 0.1209889000, 0.1329661000, 0.1650169000, 0.2512142000, 0.4855794000, 1.1288390000", \ - "0.1453300000, 0.1496031000, 0.1613673000, 0.1928352000, 0.2792188000, 0.5142880000, 1.1581179000", \ - "0.2010961000, 0.2057910000, 0.2193319000, 0.2531864000, 0.3390513000, 0.5739352000, 1.2181819000", \ - "0.2952266000, 0.3026608000, 0.3204691000, 0.3643097000, 0.4688417000, 0.7096645000, 1.3546856000", \ - "0.4502845000, 0.4609294000, 0.4883598000, 0.5551191000, 0.7015018000, 1.0043314000, 1.6689661000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0234857000, 0.0251504000, 0.0295464000, 0.0419536000, 0.0761041000, 0.1707974000, 0.4347723000", \ - "0.0232008000, 0.0247701000, 0.0293919000, 0.0418056000, 0.0760696000, 0.1707507000, 0.4349299000", \ - "0.0243234000, 0.0258277000, 0.0300541000, 0.0419620000, 0.0758903000, 0.1710470000, 0.4344189000", \ - "0.0319007000, 0.0334027000, 0.0376642000, 0.0487173000, 0.0792328000, 0.1710440000, 0.4344038000", \ - "0.0488382000, 0.0509167000, 0.0560617000, 0.0687969000, 0.1008201000, 0.1824777000, 0.4351133000", \ - "0.0817142000, 0.0846931000, 0.0919354000, 0.1097751000, 0.1499707000, 0.2369296000, 0.4610488000", \ - "0.1421957000, 0.1463004000, 0.1580165000, 0.1848181000, 0.2429588000, 0.3541444000, 0.5896604000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0663352000, 0.0720004000, 0.0874282000, 0.1301507000, 0.2472445000, 0.5690678000, 1.4580566000", \ - "0.0663367000, 0.0719630000, 0.0875674000, 0.1303482000, 0.2474753000, 0.5699129000, 1.4580978000", \ - "0.0663620000, 0.0719541000, 0.0876010000, 0.1302648000, 0.2472489000, 0.5708328000, 1.4571687000", \ - "0.0667478000, 0.0722302000, 0.0875231000, 0.1301830000, 0.2478976000, 0.5710591000, 1.4584911000", \ - "0.0802531000, 0.0854773000, 0.0988501000, 0.1376960000, 0.2497255000, 0.5692700000, 1.4564131000", \ - "0.1143615000, 0.1200268000, 0.1359616000, 0.1769583000, 0.2825214000, 0.5786259000, 1.4604168000", \ - "0.1914367000, 0.1988145000, 0.2184393000, 0.2669700000, 0.3850886000, 0.6629319000, 1.4757747000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0135185000, 0.0143941000, 0.0166940000, 0.0225876000, 0.0383249000, 0.0810906000, 0.1989269000", \ - "0.0178918000, 0.0189115000, 0.0213059000, 0.0272632000, 0.0430952000, 0.0859894000, 0.2037653000", \ - "0.0235355000, 0.0251751000, 0.0290854000, 0.0374390000, 0.0540872000, 0.0970135000, 0.2148406000", \ - "0.0284403000, 0.0310814000, 0.0371770000, 0.0506845000, 0.0762546000, 0.1222949000, 0.2401767000", \ - "0.0278651000, 0.0319002000, 0.0417128000, 0.0633590000, 0.1038603000, 0.1746218000, 0.2996976000", \ - "0.0095130000, 0.0158928000, 0.0313962000, 0.0651880000, 0.1290223000, 0.2406523000, 0.4254231000", \ - "-0.058599800, -0.048449400, -0.025075800, 0.0284418000, 0.1300526000, 0.3056845000, 0.5961014000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0716525000, 0.0759262000, 0.0883610000, 0.1208460000, 0.2072832000, 0.4414711000, 1.0850894000", \ - "0.0743050000, 0.0788088000, 0.0906466000, 0.1237824000, 0.2106755000, 0.4456273000, 1.0889943000", \ - "0.0845636000, 0.0887598000, 0.1009570000, 0.1334126000, 0.2201716000, 0.4560929000, 1.1002584000", \ - "0.1131277000, 0.1172963000, 0.1286992000, 0.1603097000, 0.2460977000, 0.4820407000, 1.1270492000", \ - "0.1725520000, 0.1782892000, 0.1926072000, 0.2278103000, 0.3130372000, 0.5473165000, 1.1927437000", \ - "0.2681701000, 0.2767737000, 0.2989280000, 0.3522381000, 0.4660110000, 0.7020082000, 1.3409110000", \ - "0.4304704000, 0.4427189000, 0.4749074000, 0.5537185000, 0.7241591000, 1.0536048000, 1.7029687000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0096355000, 0.0107941000, 0.0140843000, 0.0226383000, 0.0442555000, 0.1021003000, 0.2614125000", \ - "0.0111552000, 0.0120372000, 0.0148126000, 0.0227606000, 0.0442452000, 0.1021308000, 0.2611587000", \ - "0.0194078000, 0.0201429000, 0.0221837000, 0.0276640000, 0.0457742000, 0.1021044000, 0.2609619000", \ - "0.0338533000, 0.0347488000, 0.0372785000, 0.0440128000, 0.0599016000, 0.1065845000, 0.2611496000", \ - "0.0597022000, 0.0608729000, 0.0643303000, 0.0736680000, 0.0953186000, 0.1401274000, 0.2692475000", \ - "0.1059452000, 0.1077217000, 0.1127917000, 0.1262226000, 0.1586446000, 0.2213740000, 0.3435039000", \ - "0.1902590000, 0.1930315000, 0.2015757000, 0.2211665000, 0.2681819000, 0.3641596000, 0.5366358000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013805700, 0.0038119600, 0.0105254000, 0.0290621000, 0.0802448000, 0.2215680000"); - values("0.0660474000, 0.0717453000, 0.0872211000, 0.1299034000, 0.2472559000, 0.5689522000, 1.4575016000", \ - "0.0660480000, 0.0717603000, 0.0873675000, 0.1300289000, 0.2473235000, 0.5697718000, 1.4559419000", \ - "0.0657350000, 0.0712875000, 0.0871369000, 0.1299754000, 0.2471239000, 0.5697799000, 1.4559501000", \ - "0.0684186000, 0.0734758000, 0.0879290000, 0.1293574000, 0.2472611000, 0.5712855000, 1.4595147000", \ - "0.0943538000, 0.1002580000, 0.1142815000, 0.1470440000, 0.2506376000, 0.5690546000, 1.4568604000", \ - "0.1374919000, 0.1453960000, 0.1652583000, 0.2117812000, 0.3101206000, 0.5831928000, 1.4582071000", \ - "0.2077899000, 0.2193168000, 0.2494748000, 0.3159837000, 0.4532922000, 0.7197276000, 1.4803000000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221o_1") { - leakage_power () { - value : 0.0033058000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0032504000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0035206000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0035196000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0006097000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0031433000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0035238000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0037941000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0037931000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0006097000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0031433000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0035307000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0038010000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0033058000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0038000000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0006097000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0031433000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0005950000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0029080000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0005946000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0028845000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0005947000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0028281000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0004644000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0006033000; - when : "A1&A2&B1&B2&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a221o"; - cell_leakage_power : 0.0026567950; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047582000, 0.0047520000, 0.0047378000, 0.0047398000, 0.0047446000, 0.0047555000, 0.0047807000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003743700, -0.003746300, -0.003752300, -0.003745900, -0.003731000, -0.003696800, -0.003618000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024410000; - } - pin ("A2") { - capacitance : 0.0023540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043119000, 0.0043140000, 0.0043188000, 0.0043196000, 0.0043215000, 0.0043258000, 0.0043358000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004317800, -0.004316400, -0.004313100, -0.004313600, -0.004314600, -0.004317100, -0.004322800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024960000; - } - pin ("B1") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047619000, 0.0047641000, 0.0047689000, 0.0047679000, 0.0047655000, 0.0047599000, 0.0047471000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003951600, -0.003954400, -0.003961100, -0.003954000, -0.003937600, -0.003900000, -0.003813200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025020000; - } - pin ("B2") { - capacitance : 0.0023670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041230000, 0.0041239000, 0.0041262000, 0.0041251000, 0.0041227000, 0.0041171000, 0.0041042000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004129900, -0.004130000, -0.004130000, -0.004129000, -0.004126700, -0.004121400, -0.004109200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025380000; - } - pin ("C1") { - capacitance : 0.0022730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021467000, 0.0021438000, 0.0021371000, 0.0021507000, 0.0021820000, 0.0022541000, 0.0024205000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001741500, -0.001744000, -0.001749600, -0.001748300, -0.001745300, -0.001738300, -0.001722100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024630000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0165701000, 0.0157645000, 0.0135019000, 0.0064744000, -0.015101700, -0.075164300, -0.233346400", \ - "0.0164919000, 0.0156339000, 0.0134355000, 0.0063632000, -0.015279300, -0.075315500, -0.233499100", \ - "0.0161803000, 0.0153724000, 0.0131099000, 0.0060792000, -0.015520300, -0.075593500, -0.233740400", \ - "0.0159177000, 0.0151252000, 0.0128915000, 0.0058141000, -0.015811200, -0.075864500, -0.234032800", \ - "0.0156859000, 0.0148648000, 0.0126740000, 0.0055672000, -0.016079400, -0.076086700, -0.234258100", \ - "0.0153334000, 0.0146226000, 0.0125311000, 0.0054664000, -0.016157200, -0.076176700, -0.234309500", \ - "0.0201815000, 0.0188640000, 0.0156387000, 0.0067766000, -0.016294900, -0.076201300, -0.234305100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0149860000, 0.0164532000, 0.0201214000, 0.0291505000, 0.0522429000, 0.1121995000, 0.2687662000", \ - "0.0148604000, 0.0163335000, 0.0200008000, 0.0290371000, 0.0521351000, 0.1121251000, 0.2686693000", \ - "0.0147276000, 0.0161975000, 0.0198713000, 0.0289044000, 0.0520193000, 0.1120838000, 0.2685445000", \ - "0.0146083000, 0.0160639000, 0.0197101000, 0.0287586000, 0.0518530000, 0.1123943000, 0.2685172000", \ - "0.0145510000, 0.0159829000, 0.0195810000, 0.0286138000, 0.0519132000, 0.1121644000, 0.2693987000", \ - "0.0152583000, 0.0165653000, 0.0199754000, 0.0286201000, 0.0518385000, 0.1114890000, 0.2694092000", \ - "0.0167856000, 0.0180312000, 0.0213988000, 0.0302351000, 0.0531582000, 0.1134458000, 0.2698131000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0193955000, 0.0186090000, 0.0163114000, 0.0091541000, -0.012684800, -0.073164500, -0.231634900", \ - "0.0192845000, 0.0184785000, 0.0162046000, 0.0090394000, -0.012882200, -0.073348300, -0.231756800", \ - "0.0191618000, 0.0182697000, 0.0159964000, 0.0088098000, -0.013050800, -0.073529600, -0.231945400", \ - "0.0188277000, 0.0180608000, 0.0157604000, 0.0086007000, -0.013245000, -0.073669900, -0.232127100", \ - "0.0186880000, 0.0178486000, 0.0156051000, 0.0084242000, -0.013461400, -0.073883000, -0.232267600", \ - "0.0186156000, 0.0177288000, 0.0154941000, 0.0083748000, -0.013466000, -0.073804900, -0.232200600", \ - "0.0233703000, 0.0220195000, 0.0185360000, 0.0095908000, -0.013749400, -0.073671400, -0.232002900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0155580000, 0.0170276000, 0.0206907000, 0.0296667000, 0.0526172000, 0.1124515000, 0.2689110000", \ - "0.0154550000, 0.0169170000, 0.0205833000, 0.0295611000, 0.0525248000, 0.1123779000, 0.2687970000", \ - "0.0153180000, 0.0167800000, 0.0204294000, 0.0294574000, 0.0524009000, 0.1127503000, 0.2700601000", \ - "0.0151712000, 0.0166194000, 0.0202653000, 0.0293062000, 0.0525382000, 0.1127272000, 0.2700200000", \ - "0.0151345000, 0.0165776000, 0.0202070000, 0.0292499000, 0.0522948000, 0.1121982000, 0.2686108000", \ - "0.0157258000, 0.0170418000, 0.0204636000, 0.0291219000, 0.0523228000, 0.1119194000, 0.2685118000", \ - "0.0166547000, 0.0179458000, 0.0213040000, 0.0301497000, 0.0530972000, 0.1132737000, 0.2682263000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0141002000, 0.0132798000, 0.0110195000, 0.0038003000, -0.018064900, -0.078376300, -0.236712100", \ - "0.0139945000, 0.0131406000, 0.0108647000, 0.0036355000, -0.018204500, -0.078523700, -0.236840600", \ - "0.0136490000, 0.0128401000, 0.0105904000, 0.0034055000, -0.018483900, -0.078755700, -0.237092700", \ - "0.0133835000, 0.0125610000, 0.0103139000, 0.0030914000, -0.018759400, -0.079042000, -0.237343900", \ - "0.0131263000, 0.0123371000, 0.0100178000, 0.0028401000, -0.018980900, -0.079218400, -0.237509100", \ - "0.0127510000, 0.0120028000, 0.0098559000, 0.0026842000, -0.019037500, -0.079231700, -0.237507500", \ - "0.0179728000, 0.0166080000, 0.0131130000, 0.0042302000, -0.018982400, -0.078968800, -0.237203400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0136558000, 0.0150940000, 0.0187357000, 0.0279029000, 0.0511829000, 0.1113552000, 0.2680427000", \ - "0.0136115000, 0.0150585000, 0.0187130000, 0.0278509000, 0.0511539000, 0.1118226000, 0.2691951000", \ - "0.0135170000, 0.0149604000, 0.0186033000, 0.0277618000, 0.0510513000, 0.1112536000, 0.2680474000", \ - "0.0132905000, 0.0147098000, 0.0183196000, 0.0274276000, 0.0507061000, 0.1109272000, 0.2675932000", \ - "0.0131141000, 0.0145303000, 0.0181026000, 0.0271136000, 0.0503605000, 0.1107457000, 0.2686695000", \ - "0.0135385000, 0.0148686000, 0.0183302000, 0.0270892000, 0.0503581000, 0.1102456000, 0.2672304000", \ - "0.0147135000, 0.0159713000, 0.0193345000, 0.0283024000, 0.0513899000, 0.1117937000, 0.2673491000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0168438000, 0.0160031000, 0.0137754000, 0.0066034000, -0.015223300, -0.075505000, -0.233737300", \ - "0.0167167000, 0.0158659000, 0.0136592000, 0.0064983000, -0.015320000, -0.075570900, -0.233864200", \ - "0.0165714000, 0.0157376000, 0.0134873000, 0.0063296000, -0.015493000, -0.075729800, -0.234030000", \ - "0.0163674000, 0.0155769000, 0.0132831000, 0.0061388000, -0.015626100, -0.075870300, -0.234162700", \ - "0.0162232000, 0.0154104000, 0.0131415000, 0.0059603000, -0.015831600, -0.076045900, -0.234312900", \ - "0.0161433000, 0.0153150000, 0.0130318000, 0.0060608000, -0.015774600, -0.075980800, -0.234241500", \ - "0.0209649000, 0.0196026000, 0.0161066000, 0.0071562000, -0.016124900, -0.075808100, -0.234046600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0139559000, 0.0154035000, 0.0190525000, 0.0281939000, 0.0514873000, 0.1121519000, 0.2695059000", \ - "0.0139394000, 0.0153876000, 0.0190385000, 0.0281809000, 0.0514852000, 0.1121509000, 0.2695097000", \ - "0.0138531000, 0.0152995000, 0.0189520000, 0.0280759000, 0.0513672000, 0.1120875000, 0.2692497000", \ - "0.0136384000, 0.0150775000, 0.0187081000, 0.0278230000, 0.0511436000, 0.1113926000, 0.2692940000", \ - "0.0133793000, 0.0148223000, 0.0184124000, 0.0274456000, 0.0509335000, 0.1115437000, 0.2675648000", \ - "0.0136404000, 0.0150008000, 0.0184602000, 0.0272379000, 0.0505417000, 0.1110688000, 0.2686249000", \ - "0.0143280000, 0.0156555000, 0.0190694000, 0.0280091000, 0.0511463000, 0.1115894000, 0.2681380000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0163677000, 0.0155300000, 0.0133181000, 0.0061892000, -0.015516500, -0.075621700, -0.233767500", \ - "0.0162224000, 0.0154282000, 0.0131497000, 0.0060160000, -0.015664500, -0.075716300, -0.233894200", \ - "0.0159708000, 0.0151814000, 0.0128861000, 0.0057917000, -0.015914600, -0.075991900, -0.234139200", \ - "0.0157979000, 0.0150039000, 0.0127342000, 0.0056107000, -0.016083400, -0.076162600, -0.234314100", \ - "0.0157164000, 0.0149494000, 0.0127073000, 0.0055133000, -0.016175300, -0.076280300, -0.234435000", \ - "0.0159048000, 0.0154919000, 0.0132787000, 0.0060781000, -0.015584600, -0.075702900, -0.233834100", \ - "0.0225818000, 0.0207384000, 0.0172320000, 0.0082846000, -0.014713200, -0.074774700, -0.233012500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0089097000, 0.0103600000, 0.0140091000, 0.0230901000, 0.0462130000, 0.1063316000, 0.2641330000", \ - "0.0088646000, 0.0103112000, 0.0139526000, 0.0230518000, 0.0462122000, 0.1068807000, 0.2623319000", \ - "0.0087411000, 0.0101714000, 0.0137723000, 0.0228654000, 0.0460633000, 0.1061756000, 0.2627083000", \ - "0.0085178000, 0.0099104000, 0.0134745000, 0.0225386000, 0.0457982000, 0.1065775000, 0.2629186000", \ - "0.0086120000, 0.0099051000, 0.0133456000, 0.0223173000, 0.0455238000, 0.1063586000, 0.2608913000", \ - "0.0089174000, 0.0102216000, 0.0136869000, 0.0225674000, 0.0457318000, 0.1054130000, 0.2627094000", \ - "0.0104028000, 0.0116309000, 0.0149632000, 0.0239229000, 0.0469866000, 0.1072076000, 0.2634127000"); - } - } - max_capacitance : 0.1583960000; - max_transition : 1.4995910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2718699000, 0.2810688000, 0.2998839000, 0.3359439000, 0.4037139000, 0.5431080000, 0.8693125000", \ - "0.2757802000, 0.2850464000, 0.3037228000, 0.3397519000, 0.4077485000, 0.5471860000, 0.8733100000", \ - "0.2864037000, 0.2955801000, 0.3143870000, 0.3504405000, 0.4182074000, 0.5576269000, 0.8838270000", \ - "0.3111263000, 0.3203105000, 0.3392096000, 0.3751683000, 0.4434154000, 0.5826744000, 0.9089619000", \ - "0.3637162000, 0.3728983000, 0.3917417000, 0.4276783000, 0.4957171000, 0.6351205000, 0.9610824000", \ - "0.4665527000, 0.4762496000, 0.4957720000, 0.5329387000, 0.6025213000, 0.7426615000, 1.0692653000", \ - "0.6360417000, 0.6472651000, 0.6691763000, 0.7105261000, 0.7865938000, 0.9337855000, 1.2641687000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0959597000, 0.1042351000, 0.1222814000, 0.1618205000, 0.2575242000, 0.5031873000, 1.1405868000", \ - "0.1001007000, 0.1084136000, 0.1264623000, 0.1660218000, 0.2617233000, 0.5072890000, 1.1444498000", \ - "0.1104486000, 0.1187022000, 0.1367225000, 0.1762487000, 0.2719180000, 0.5172002000, 1.1552972000", \ - "0.1359734000, 0.1441635000, 0.1619924000, 0.2013576000, 0.2969254000, 0.5424669000, 1.1801572000", \ - "0.1830391000, 0.1917007000, 0.2100285000, 0.2498530000, 0.3452868000, 0.5912923000, 1.2305148000", \ - "0.2436762000, 0.2539087000, 0.2742672000, 0.3156666000, 0.4116452000, 0.6566855000, 1.2977542000", \ - "0.3031535000, 0.3163811000, 0.3420524000, 0.3882771000, 0.4855646000, 0.7309999000, 1.3683619000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0356671000, 0.0416622000, 0.0545874000, 0.0828700000, 0.1453446000, 0.2969950000, 0.7081519000", \ - "0.0359891000, 0.0414291000, 0.0553914000, 0.0828648000, 0.1453334000, 0.2966787000, 0.7098238000", \ - "0.0356400000, 0.0416574000, 0.0545784000, 0.0827604000, 0.1453443000, 0.2969449000, 0.7086830000", \ - "0.0355609000, 0.0418343000, 0.0551318000, 0.0825394000, 0.1451487000, 0.2970949000, 0.7099778000", \ - "0.0354871000, 0.0414700000, 0.0552905000, 0.0826016000, 0.1453093000, 0.2968340000, 0.7102247000", \ - "0.0382663000, 0.0445750000, 0.0583604000, 0.0857558000, 0.1484024000, 0.2978196000, 0.7147290000", \ - "0.0457886000, 0.0526737000, 0.0673120000, 0.0978294000, 0.1608631000, 0.3097987000, 0.7129807000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0291442000, 0.0364572000, 0.0549331000, 0.1027931000, 0.2335966000, 0.5811169000, 1.4888019000", \ - "0.0290845000, 0.0364681000, 0.0547543000, 0.1030110000, 0.2337516000, 0.5809531000, 1.4895148000", \ - "0.0289415000, 0.0362587000, 0.0547261000, 0.1028698000, 0.2331089000, 0.5798897000, 1.4918503000", \ - "0.0285090000, 0.0358541000, 0.0541181000, 0.1024778000, 0.2335453000, 0.5815843000, 1.4890666000", \ - "0.0315638000, 0.0383915000, 0.0559664000, 0.1032178000, 0.2332359000, 0.5806928000, 1.4938475000", \ - "0.0394674000, 0.0457386000, 0.0619027000, 0.1061798000, 0.2339669000, 0.5799363000, 1.4913223000", \ - "0.0533456000, 0.0603151000, 0.0762228000, 0.1162562000, 0.2372684000, 0.5835843000, 1.4880850000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.3004158000, 0.3098479000, 0.3290808000, 0.3654387000, 0.4330077000, 0.5719390000, 0.8979430000", \ - "0.3047891000, 0.3143433000, 0.3336198000, 0.3698342000, 0.4378845000, 0.5767571000, 0.9025515000", \ - "0.3166261000, 0.3261766000, 0.3453865000, 0.3817236000, 0.4498709000, 0.5886904000, 0.9146890000", \ - "0.3435060000, 0.3530606000, 0.3722734000, 0.4086489000, 0.4762593000, 0.6152399000, 0.9410532000", \ - "0.3998510000, 0.4093862000, 0.4286267000, 0.4648197000, 0.5326425000, 0.6715760000, 0.9974001000", \ - "0.5152854000, 0.5250763000, 0.5447906000, 0.5813061000, 0.6505340000, 0.7898678000, 1.1159420000", \ - "0.7160773000, 0.7272625000, 0.7493714000, 0.7902805000, 0.8652599000, 1.0113297000, 1.3407643000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.1007749000, 0.1090890000, 0.1271255000, 0.1664735000, 0.2615760000, 0.5065852000, 1.1434349000", \ - "0.1050570000, 0.1133413000, 0.1313675000, 0.1707109000, 0.2658283000, 0.5103087000, 1.1488456000", \ - "0.1143064000, 0.1226585000, 0.1405376000, 0.1799799000, 0.2750079000, 0.5205680000, 1.1593690000", \ - "0.1355205000, 0.1437775000, 0.1615642000, 0.2010046000, 0.2962827000, 0.5417634000, 1.1802088000", \ - "0.1756602000, 0.1842682000, 0.2027111000, 0.2425919000, 0.3377742000, 0.5824721000, 1.2205560000", \ - "0.2317263000, 0.2416789000, 0.2618763000, 0.3033079000, 0.3992129000, 0.6441765000, 1.2817373000", \ - "0.2857856000, 0.2985872000, 0.3232096000, 0.3689463000, 0.4664761000, 0.7118849000, 1.3488795000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0384919000, 0.0441007000, 0.0568520000, 0.0844209000, 0.1471822000, 0.2986121000, 0.7098613000", \ - "0.0380010000, 0.0439337000, 0.0578089000, 0.0844708000, 0.1476124000, 0.2983498000, 0.7108239000", \ - "0.0381211000, 0.0441907000, 0.0568071000, 0.0848140000, 0.1472561000, 0.2984803000, 0.7109242000", \ - "0.0379861000, 0.0441287000, 0.0568603000, 0.0846498000, 0.1471402000, 0.2987257000, 0.7112493000", \ - "0.0378775000, 0.0437931000, 0.0577880000, 0.0845401000, 0.1476328000, 0.2983287000, 0.7107760000", \ - "0.0409985000, 0.0461264000, 0.0589079000, 0.0865390000, 0.1485323000, 0.2992576000, 0.7107380000", \ - "0.0474114000, 0.0540479000, 0.0683895000, 0.0981506000, 0.1603646000, 0.3085311000, 0.7156951000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0291138000, 0.0364654000, 0.0548144000, 0.1031444000, 0.2336981000, 0.5809621000, 1.4894842000", \ - "0.0291039000, 0.0364743000, 0.0547754000, 0.1029609000, 0.2332981000, 0.5804553000, 1.4935367000", \ - "0.0290583000, 0.0363495000, 0.0546895000, 0.1028060000, 0.2332926000, 0.5814085000, 1.4935118000", \ - "0.0287983000, 0.0361032000, 0.0544363000, 0.1027507000, 0.2336568000, 0.5819534000, 1.4929743000", \ - "0.0310509000, 0.0381871000, 0.0559560000, 0.1030713000, 0.2334075000, 0.5796945000, 1.4923894000", \ - "0.0369614000, 0.0438781000, 0.0610503000, 0.1062305000, 0.2344843000, 0.5810502000, 1.4908015000", \ - "0.0494959000, 0.0570786000, 0.0732087000, 0.1147128000, 0.2371817000, 0.5842737000, 1.4900224000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2539825000, 0.2633082000, 0.2822771000, 0.3182887000, 0.3866293000, 0.5260674000, 0.8526010000", \ - "0.2570007000, 0.2663085000, 0.2852185000, 0.3212924000, 0.3896883000, 0.5290967000, 0.8556876000", \ - "0.2660787000, 0.2753216000, 0.2942942000, 0.3298169000, 0.3981942000, 0.5379115000, 0.8643479000", \ - "0.2896681000, 0.2989212000, 0.3178773000, 0.3534442000, 0.4218080000, 0.5615625000, 0.8879980000", \ - "0.3438335000, 0.3531184000, 0.3720472000, 0.4080985000, 0.4764816000, 0.6161828000, 0.9427032000", \ - "0.4572395000, 0.4671836000, 0.4873230000, 0.5253570000, 0.5955614000, 0.7365882000, 1.0631587000", \ - "0.6485438000, 0.6603563000, 0.6842760000, 0.7277882000, 0.8051060000, 0.9533464000, 1.2848432000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0912742000, 0.0993004000, 0.1169786000, 0.1563876000, 0.2519393000, 0.4971291000, 1.1353235000", \ - "0.0957276000, 0.1037877000, 0.1215190000, 0.1608301000, 0.2564353000, 0.5026937000, 1.1429757000", \ - "0.1061334000, 0.1141749000, 0.1318499000, 0.1712231000, 0.2668671000, 0.5123179000, 1.1498752000", \ - "0.1303554000, 0.1382834000, 0.1558328000, 0.1950277000, 0.2907733000, 0.5362533000, 1.1753134000", \ - "0.1722499000, 0.1808413000, 0.1990510000, 0.2388380000, 0.3345243000, 0.5799629000, 1.2197073000", \ - "0.2233016000, 0.2337205000, 0.2543230000, 0.2959292000, 0.3921835000, 0.6382426000, 1.2769682000", \ - "0.2677511000, 0.2812188000, 0.3076498000, 0.3550390000, 0.4526826000, 0.6988506000, 1.3375542000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0364490000, 0.0422784000, 0.0561679000, 0.0836181000, 0.1471449000, 0.2983244000, 0.7133231000", \ - "0.0362543000, 0.0423520000, 0.0560120000, 0.0836238000, 0.1473026000, 0.2985255000, 0.7152064000", \ - "0.0364651000, 0.0425286000, 0.0562285000, 0.0852384000, 0.1469597000, 0.2986470000, 0.7088772000", \ - "0.0364477000, 0.0422557000, 0.0562341000, 0.0851500000, 0.1469071000, 0.2985923000, 0.7096913000", \ - "0.0362134000, 0.0424838000, 0.0564007000, 0.0835699000, 0.1465356000, 0.2984263000, 0.7134555000", \ - "0.0410827000, 0.0472070000, 0.0603503000, 0.0886371000, 0.1507796000, 0.3000621000, 0.7111194000", \ - "0.0517275000, 0.0589139000, 0.0735132000, 0.1040957000, 0.1653257000, 0.3126254000, 0.7170531000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0269304000, 0.0340213000, 0.0519629000, 0.1000307000, 0.2316129000, 0.5788491000, 1.4917040000", \ - "0.0269821000, 0.0340367000, 0.0521124000, 0.1002157000, 0.2308588000, 0.5812423000, 1.4908215000", \ - "0.0269922000, 0.0339995000, 0.0519551000, 0.1000833000, 0.2315639000, 0.5797731000, 1.4885727000", \ - "0.0270785000, 0.0341648000, 0.0521297000, 0.1001156000, 0.2317119000, 0.5812629000, 1.4932126000", \ - "0.0307866000, 0.0374730000, 0.0548242000, 0.1018420000, 0.2318479000, 0.5798857000, 1.4936437000", \ - "0.0394687000, 0.0457658000, 0.0618798000, 0.1055013000, 0.2330997000, 0.5801761000, 1.4883024000", \ - "0.0544824000, 0.0616852000, 0.0775583000, 0.1174234000, 0.2366905000, 0.5825116000, 1.4884424000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2765441000, 0.2860521000, 0.3053623000, 0.3415714000, 0.4098088000, 0.5490614000, 0.8752761000", \ - "0.2803659000, 0.2899307000, 0.3091865000, 0.3455349000, 0.4136711000, 0.5525916000, 0.8787790000", \ - "0.2911181000, 0.3007225000, 0.3198700000, 0.3562009000, 0.4244022000, 0.5632758000, 0.8901407000", \ - "0.3175419000, 0.3269586000, 0.3461819000, 0.3825674000, 0.4504074000, 0.5898028000, 0.9161633000", \ - "0.3771739000, 0.3866017000, 0.4055787000, 0.4419711000, 0.5101174000, 0.6497744000, 0.9761045000", \ - "0.5071506000, 0.5174720000, 0.5375467000, 0.5747650000, 0.6443590000, 0.7842276000, 1.1106879000", \ - "0.7362507000, 0.7484099000, 0.7718258000, 0.8144591000, 0.8907071000, 1.0373323000, 1.3675626000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0954227000, 0.1034715000, 0.1212026000, 0.1605127000, 0.2561448000, 0.5024366000, 1.1426825000", \ - "0.0998925000, 0.1079468000, 0.1256690000, 0.1649982000, 0.2606129000, 0.5068683000, 1.1471655000", \ - "0.1092156000, 0.1172802000, 0.1349992000, 0.1743119000, 0.2698903000, 0.5160656000, 1.1562927000", \ - "0.1296779000, 0.1377135000, 0.1553316000, 0.1946032000, 0.2899707000, 0.5354094000, 1.1747705000", \ - "0.1664861000, 0.1750291000, 0.1932600000, 0.2330757000, 0.3289625000, 0.5744219000, 1.2135923000", \ - "0.2148218000, 0.2247603000, 0.2451133000, 0.2865945000, 0.3826625000, 0.6284097000, 1.2693674000", \ - "0.2552108000, 0.2681561000, 0.2937839000, 0.3400671000, 0.4380692000, 0.6847894000, 1.3223149000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0379094000, 0.0439151000, 0.0576134000, 0.0845433000, 0.1475603000, 0.2982687000, 0.7106195000", \ - "0.0380198000, 0.0440907000, 0.0572019000, 0.0855729000, 0.1465825000, 0.2981369000, 0.7120607000", \ - "0.0385985000, 0.0446998000, 0.0568747000, 0.0855697000, 0.1470884000, 0.2982007000, 0.7145803000", \ - "0.0385183000, 0.0441110000, 0.0568439000, 0.0845440000, 0.1469030000, 0.2983372000, 0.7119609000", \ - "0.0384161000, 0.0440742000, 0.0571592000, 0.0847161000, 0.1471671000, 0.2984562000, 0.7109136000", \ - "0.0415483000, 0.0477754000, 0.0602529000, 0.0881896000, 0.1493532000, 0.2987320000, 0.7118368000", \ - "0.0526828000, 0.0596483000, 0.0736350000, 0.1014694000, 0.1616212000, 0.3099152000, 0.7157793000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0269514000, 0.0340627000, 0.0520946000, 0.1002149000, 0.2310032000, 0.5811070000, 1.4914476000", \ - "0.0269133000, 0.0340471000, 0.0521244000, 0.1002141000, 0.2308434000, 0.5812281000, 1.4910105000", \ - "0.0269653000, 0.0340273000, 0.0521162000, 0.1002145000, 0.2310959000, 0.5814160000, 1.4910991000", \ - "0.0270386000, 0.0341456000, 0.0521707000, 0.1000333000, 0.2315769000, 0.5801148000, 1.4936803000", \ - "0.0298854000, 0.0368303000, 0.0543196000, 0.1013145000, 0.2318877000, 0.5806599000, 1.4938070000", \ - "0.0370502000, 0.0439780000, 0.0602190000, 0.1050491000, 0.2328866000, 0.5786459000, 1.4941333000", \ - "0.0502154000, 0.0581426000, 0.0742244000, 0.1153054000, 0.2359061000, 0.5819881000, 1.4857710000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2229584000, 0.2325068000, 0.2515835000, 0.2880177000, 0.3564383000, 0.4963160000, 0.8226516000", \ - "0.2257875000, 0.2352964000, 0.2544992000, 0.2904823000, 0.3592360000, 0.4990857000, 0.8257683000", \ - "0.2336453000, 0.2430559000, 0.2623074000, 0.2984722000, 0.3669235000, 0.5070084000, 0.8334508000", \ - "0.2571214000, 0.2667293000, 0.2858806000, 0.3222652000, 0.3906405000, 0.5305519000, 0.8571033000", \ - "0.3182233000, 0.3277199000, 0.3468688000, 0.3832038000, 0.4518051000, 0.5913927000, 0.9181776000", \ - "0.4538479000, 0.4646018000, 0.4843421000, 0.5210731000, 0.5899943000, 0.7303618000, 1.0571100000", \ - "0.6737121000, 0.6851760000, 0.7099940000, 0.7527453000, 0.8244217000, 0.9678613000, 1.2986153000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0637429000, 0.0710199000, 0.0873325000, 0.1250781000, 0.2198004000, 0.4636752000, 1.1114848000", \ - "0.0686784000, 0.0758949000, 0.0922120000, 0.1298863000, 0.2244274000, 0.4693011000, 1.1167899000", \ - "0.0799824000, 0.0871196000, 0.1033250000, 0.1410552000, 0.2354634000, 0.4809775000, 1.1178870000", \ - "0.1031575000, 0.1104671000, 0.1267859000, 0.1645018000, 0.2593175000, 0.5046377000, 1.1416250000", \ - "0.1357895000, 0.1442785000, 0.1619752000, 0.2007166000, 0.2955195000, 0.5408246000, 1.1840898000", \ - "0.1718431000, 0.1828596000, 0.2045599000, 0.2458606000, 0.3411652000, 0.5863753000, 1.2267836000", \ - "0.1928274000, 0.2075953000, 0.2363610000, 0.2862464000, 0.3842620000, 0.6302266000, 1.2673107000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0379450000, 0.0439077000, 0.0569594000, 0.0844909000, 0.1472784000, 0.2976488000, 0.7107805000", \ - "0.0386317000, 0.0443539000, 0.0568535000, 0.0857940000, 0.1468609000, 0.2978483000, 0.7117269000", \ - "0.0385428000, 0.0440901000, 0.0568262000, 0.0849172000, 0.1472062000, 0.2972294000, 0.7107545000", \ - "0.0383676000, 0.0447804000, 0.0570603000, 0.0845916000, 0.1469499000, 0.2983977000, 0.7110497000", \ - "0.0375940000, 0.0441645000, 0.0574290000, 0.0842464000, 0.1471552000, 0.2978055000, 0.7148907000", \ - "0.0428732000, 0.0481506000, 0.0600489000, 0.0869130000, 0.1489986000, 0.2987990000, 0.7114626000", \ - "0.0590360000, 0.0656095000, 0.0779697000, 0.1024993000, 0.1591125000, 0.3069011000, 0.7154674000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0230017000, 0.0298173000, 0.0479198000, 0.0970976000, 0.2302919000, 0.5787556000, 1.4995905000", \ - "0.0230372000, 0.0298051000, 0.0478826000, 0.0969700000, 0.2302358000, 0.5818353000, 1.4952926000", \ - "0.0231306000, 0.0299067000, 0.0479447000, 0.0970460000, 0.2295413000, 0.5800320000, 1.4894636000", \ - "0.0248245000, 0.0313033000, 0.0487716000, 0.0972161000, 0.2302941000, 0.5819014000, 1.4933398000", \ - "0.0312096000, 0.0370929000, 0.0531031000, 0.0994479000, 0.2302947000, 0.5824335000, 1.4926370000", \ - "0.0428589000, 0.0487467000, 0.0632375000, 0.1049852000, 0.2316898000, 0.5784991000, 1.4973621000", \ - "0.0600106000, 0.0679208000, 0.0842151000, 0.1220568000, 0.2362384000, 0.5812168000, 1.4852509000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221o_2") { - leakage_power () { - value : 0.0037804000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0036531000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0037804000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0039234000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0037804000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0039224000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0010843000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0036179000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0037804000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0039373000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0037802000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0042077000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0037803000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0042066000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0010843000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0036179000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0037804000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0039616000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0037802000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0042319000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0037803000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0042308000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0010843000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0036179000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0010299000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0029993000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0010298000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0029796000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0010299000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0029315000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0009270000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0010385000; - when : "A1&A2&B1&B2&!C1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a221o"; - cell_leakage_power : 0.0030740500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047372000, 0.0047372000, 0.0047372000, 0.0047385000, 0.0047414000, 0.0047481000, 0.0047635000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003736800, -0.003740100, -0.003747900, -0.003741200, -0.003725800, -0.003690300, -0.003608400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024250000; - } - pin ("A2") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043240000, 0.0043216000, 0.0043161000, 0.0043144000, 0.0043104000, 0.0043013000, 0.0042801000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004302100, -0.004301300, -0.004299600, -0.004299400, -0.004299100, -0.004298400, -0.004296800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024870000; - } - pin ("B1") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047582000, 0.0047609000, 0.0047670000, 0.0047660000, 0.0047636000, 0.0047582000, 0.0047457000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003940800, -0.003946700, -0.003960300, -0.003953800, -0.003939000, -0.003904800, -0.003825800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - } - pin ("B2") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041131000, 0.0041140000, 0.0041159000, 0.0041161000, 0.0041165000, 0.0041175000, 0.0041197000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004126500, -0.004124900, -0.004121100, -0.004121200, -0.004121400, -0.004121800, -0.004122700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025320000; - } - pin ("C1") { - capacitance : 0.0022570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021307000, 0.0021311000, 0.0021320000, 0.0021459000, 0.0021780000, 0.0022520000, 0.0024226000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001741900, -0.001743700, -0.001747700, -0.001745800, -0.001741500, -0.001731600, -0.001708600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024470000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0195943000, 0.0181055000, 0.0144627000, 0.0038551000, -0.030882300, -0.138711800, -0.456277500", \ - "0.0193223000, 0.0178298000, 0.0142573000, 0.0035783000, -0.031001600, -0.138779600, -0.456393700", \ - "0.0192105000, 0.0176549000, 0.0140916000, 0.0034224000, -0.031190200, -0.139072000, -0.456619800", \ - "0.0189233000, 0.0174410000, 0.0137924000, 0.0031900000, -0.031533900, -0.139366700, -0.456889600", \ - "0.0185877000, 0.0170658000, 0.0134936000, 0.0028438000, -0.031795300, -0.139627700, -0.457172300", \ - "0.0185675000, 0.0170833000, 0.0134370000, 0.0027287000, -0.031938300, -0.139751300, -0.457267100", \ - "0.0250681000, 0.0233250000, 0.0186692000, 0.0055975000, -0.031941100, -0.139776900, -0.457270000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0197958000, 0.0214662000, 0.0262964000, 0.0397053000, 0.0772859000, 0.1855105000, 0.5003152000", \ - "0.0196929000, 0.0213458000, 0.0261845000, 0.0395918000, 0.0771904000, 0.1854180000, 0.5002012000", \ - "0.0195247000, 0.0212095000, 0.0260243000, 0.0394843000, 0.0770498000, 0.1854191000, 0.5017917000", \ - "0.0195106000, 0.0211708000, 0.0259697000, 0.0393816000, 0.0769400000, 0.1851100000, 0.4994904000", \ - "0.0195639000, 0.0212031000, 0.0258828000, 0.0392170000, 0.0768240000, 0.1854618000, 0.5016940000", \ - "0.0205751000, 0.0220893000, 0.0266302000, 0.0393509000, 0.0768677000, 0.1850422000, 0.5016983000", \ - "0.0221658000, 0.0236318000, 0.0279322000, 0.0409608000, 0.0782511000, 0.1866315000, 0.5012372000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0223092000, 0.0207473000, 0.0171886000, 0.0064359000, -0.028460200, -0.136594400, -0.454575600", \ - "0.0223473000, 0.0207949000, 0.0172275000, 0.0064069000, -0.028473300, -0.136765400, -0.454658600", \ - "0.0220279000, 0.0205057000, 0.0169024000, 0.0060975000, -0.028670300, -0.136909600, -0.454762700", \ - "0.0218067000, 0.0202523000, 0.0166824000, 0.0059319000, -0.028932300, -0.137125800, -0.455017100", \ - "0.0216008000, 0.0200773000, 0.0164909000, 0.0057489000, -0.029141500, -0.137337300, -0.455206100", \ - "0.0217300000, 0.0202176000, 0.0165030000, 0.0056952000, -0.029196400, -0.137316100, -0.455121900", \ - "0.0279054000, 0.0262271000, 0.0214801000, 0.0082397000, -0.029665700, -0.137185700, -0.454929700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0203779000, 0.0220471000, 0.0268725000, 0.0402888000, 0.0777814000, 0.1860093000, 0.4993225000", \ - "0.0202826000, 0.0219563000, 0.0267683000, 0.0401861000, 0.0776649000, 0.1856406000, 0.4999676000", \ - "0.0201339000, 0.0218105000, 0.0265956000, 0.0400651000, 0.0775023000, 0.1856663000, 0.4996022000", \ - "0.0200011000, 0.0216548000, 0.0264746000, 0.0398917000, 0.0774216000, 0.1865062000, 0.4998207000", \ - "0.0199915000, 0.0216408000, 0.0264101000, 0.0397639000, 0.0773497000, 0.1857970000, 0.4997935000", \ - "0.0208448000, 0.0223808000, 0.0268940000, 0.0397402000, 0.0773458000, 0.1851421000, 0.4995026000", \ - "0.0221269000, 0.0235719000, 0.0279943000, 0.0409946000, 0.0783642000, 0.1865047000, 0.4988851000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0169403000, 0.0154206000, 0.0119030000, 0.0011000000, -0.033728200, -0.141847700, -0.459621600", \ - "0.0168225000, 0.0153140000, 0.0117306000, 0.0009918000, -0.033883600, -0.141937700, -0.459727500", \ - "0.0166923000, 0.0151517000, 0.0115496000, 0.0007914000, -0.034098300, -0.142238300, -0.459977100", \ - "0.0164225000, 0.0149185000, 0.0113002000, 0.0005357000, -0.034412200, -0.142489400, -0.460226000", \ - "0.0160458000, 0.0145560000, 0.0109484000, 0.0002111000, -0.034703700, -0.142746200, -0.460458500", \ - "0.0160908000, 0.0145292000, 0.0109213000, -2.60000e-06, -0.034791600, -0.142804300, -0.460451200", \ - "0.0231325000, 0.0213498000, 0.0165382000, 0.0029854000, -0.034802300, -0.142115400, -0.460007100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0183717000, 0.0200564000, 0.0248766000, 0.0383435000, 0.0762955000, 0.1851181000, 0.5016251000", \ - "0.0183796000, 0.0200448000, 0.0248644000, 0.0383310000, 0.0763309000, 0.1852555000, 0.4994167000", \ - "0.0182977000, 0.0199596000, 0.0247897000, 0.0383212000, 0.0761804000, 0.1849263000, 0.4995154000", \ - "0.0181795000, 0.0198451000, 0.0246375000, 0.0380924000, 0.0758823000, 0.1847446000, 0.4991556000", \ - "0.0180647000, 0.0197040000, 0.0243899000, 0.0377149000, 0.0754524000, 0.1852232000, 0.5011514000", \ - "0.0187865000, 0.0203073000, 0.0248952000, 0.0377159000, 0.0753784000, 0.1836361000, 0.4991196000", \ - "0.0201472000, 0.0215837000, 0.0259771000, 0.0390261000, 0.0764821000, 0.1851973000, 0.4981081000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0197219000, 0.0181988000, 0.0146656000, 0.0039405000, -0.030868700, -0.138960100, -0.456686700", \ - "0.0198457000, 0.0183120000, 0.0146995000, 0.0039001000, -0.030969600, -0.139071300, -0.456792600", \ - "0.0194910000, 0.0179725000, 0.0145567000, 0.0038143000, -0.031053700, -0.139190400, -0.456906300", \ - "0.0194110000, 0.0178725000, 0.0142482000, 0.0035223000, -0.031315500, -0.139411100, -0.457100000", \ - "0.0191269000, 0.0176192000, 0.0140605000, 0.0032733000, -0.031546700, -0.139566800, -0.457256800", \ - "0.0191857000, 0.0179631000, 0.0139506000, 0.0031793000, -0.031474400, -0.139550700, -0.457213600", \ - "0.0258806000, 0.0240974000, 0.0192805000, 0.0059434000, -0.031768200, -0.139336900, -0.457050800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0186697000, 0.0203503000, 0.0251811000, 0.0386484000, 0.0766154000, 0.1862656000, 0.4990586000", \ - "0.0186762000, 0.0203472000, 0.0251806000, 0.0387052000, 0.0766038000, 0.1862661000, 0.4990895000", \ - "0.0186156000, 0.0203017000, 0.0251391000, 0.0386497000, 0.0765320000, 0.1852285000, 0.4991633000", \ - "0.0184476000, 0.0201102000, 0.0249196000, 0.0384095000, 0.0762623000, 0.1851653000, 0.4998191000", \ - "0.0182855000, 0.0199002000, 0.0247147000, 0.0380095000, 0.0758566000, 0.1848130000, 0.4993367000", \ - "0.0187725000, 0.0203162000, 0.0249078000, 0.0379043000, 0.0755288000, 0.1837145000, 0.4992848000", \ - "0.0196647000, 0.0211387000, 0.0255698000, 0.0387294000, 0.0763044000, 0.1851831000, 0.4993995000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0193244000, 0.0177835000, 0.0142076000, 0.0034813000, -0.031327400, -0.139131500, -0.456758500", \ - "0.0192346000, 0.0176865000, 0.0141238000, 0.0033641000, -0.031419100, -0.139293000, -0.456885500", \ - "0.0189879000, 0.0174555000, 0.0138693000, 0.0030701000, -0.031656000, -0.139479600, -0.457027300", \ - "0.0187781000, 0.0173073000, 0.0136799000, 0.0029270000, -0.031828600, -0.139698300, -0.457281100", \ - "0.0186148000, 0.0170742000, 0.0134934000, 0.0028539000, -0.032057700, -0.139902800, -0.457440200", \ - "0.0190463000, 0.0174949000, 0.0138177000, 0.0029342000, -0.031510400, -0.139597000, -0.457198100", \ - "0.0274348000, 0.0255918000, 0.0207133000, 0.0072035000, -0.030071600, -0.138120800, -0.455831400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0137065000, 0.0154214000, 0.0202881000, 0.0337683000, 0.0715939000, 0.1810922000, 0.4945675000", \ - "0.0137127000, 0.0154090000, 0.0202706000, 0.0337552000, 0.0716030000, 0.1793317000, 0.4946150000", \ - "0.0136460000, 0.0153411000, 0.0201768000, 0.0336285000, 0.0714260000, 0.1801023000, 0.4930587000", \ - "0.0134705000, 0.0151349000, 0.0198884000, 0.0332203000, 0.0711068000, 0.1799424000, 0.4947681000", \ - "0.0134704000, 0.0150364000, 0.0197177000, 0.0328489000, 0.0705986000, 0.1796128000, 0.4948464000", \ - "0.0142977000, 0.0158040000, 0.0202821000, 0.0333852000, 0.0708406000, 0.1788205000, 0.4943905000", \ - "0.0158550000, 0.0172906000, 0.0216076000, 0.0347362000, 0.0720394000, 0.1804881000, 0.4935982000"); - } - } - max_capacitance : 0.2993870000; - max_transition : 1.5038360000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.3129089000, 0.3209928000, 0.3388361000, 0.3740128000, 0.4408129000, 0.5765300000, 0.9004160000", \ - "0.3172753000, 0.3253968000, 0.3432312000, 0.3784160000, 0.4447771000, 0.5801912000, 0.9042688000", \ - "0.3281991000, 0.3362946000, 0.3541021000, 0.3894759000, 0.4560148000, 0.5916612000, 0.9156850000", \ - "0.3530388000, 0.3611191000, 0.3789282000, 0.4140795000, 0.4803788000, 0.6161047000, 0.9401624000", \ - "0.4055478000, 0.4136745000, 0.4314752000, 0.4665365000, 0.5331681000, 0.6686677000, 0.9924919000", \ - "0.5139023000, 0.5223660000, 0.5406284000, 0.5761926000, 0.6431716000, 0.7792890000, 1.1034598000", \ - "0.6994129000, 0.7086559000, 0.7291153000, 0.7689527000, 0.8427091000, 0.9855123000, 1.3148073000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1049945000, 0.1117510000, 0.1273271000, 0.1619036000, 0.2462126000, 0.4812113000, 1.1576101000", \ - "0.1091210000, 0.1159061000, 0.1314900000, 0.1660496000, 0.2503381000, 0.4852863000, 1.1617370000", \ - "0.1195385000, 0.1263171000, 0.1419194000, 0.1764474000, 0.2607114000, 0.4948540000, 1.1741705000", \ - "0.1444801000, 0.1511501000, 0.1665112000, 0.2008896000, 0.2849631000, 0.5193896000, 1.1986647000", \ - "0.1951459000, 0.2022448000, 0.2181252000, 0.2527949000, 0.3370468000, 0.5714890000, 1.2492597000", \ - "0.2632674000, 0.2719066000, 0.2904564000, 0.3276845000, 0.4129994000, 0.6475354000, 1.3251595000", \ - "0.3341542000, 0.3452706000, 0.3690226000, 0.4138005000, 0.5028092000, 0.7378873000, 1.4133040000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0394573000, 0.0445037000, 0.0551165000, 0.0792782000, 0.1312807000, 0.2665751000, 0.6619360000", \ - "0.0394718000, 0.0444177000, 0.0551418000, 0.0796378000, 0.1328746000, 0.2672127000, 0.6611391000", \ - "0.0392863000, 0.0441293000, 0.0559889000, 0.0793627000, 0.1317847000, 0.2665049000, 0.6625996000", \ - "0.0394339000, 0.0444881000, 0.0550639000, 0.0792822000, 0.1324433000, 0.2665791000, 0.6635039000", \ - "0.0392529000, 0.0441643000, 0.0553710000, 0.0786216000, 0.1320429000, 0.2671030000, 0.6626692000", \ - "0.0416697000, 0.0462898000, 0.0573780000, 0.0804892000, 0.1345712000, 0.2679686000, 0.6626783000", \ - "0.0493158000, 0.0547334000, 0.0675960000, 0.0918233000, 0.1461473000, 0.2804369000, 0.6683337000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0259695000, 0.0311733000, 0.0445778000, 0.0815688000, 0.1922603000, 0.5251626000, 1.4996693000", \ - "0.0259681000, 0.0311404000, 0.0445769000, 0.0815506000, 0.1921027000, 0.5248968000, 1.4991932000", \ - "0.0258876000, 0.0310163000, 0.0444992000, 0.0815733000, 0.1922751000, 0.5253765000, 1.4998386000", \ - "0.0253961000, 0.0306160000, 0.0441297000, 0.0813153000, 0.1920290000, 0.5246678000, 1.4958526000", \ - "0.0281678000, 0.0331774000, 0.0459792000, 0.0819872000, 0.1916103000, 0.5256359000, 1.4994627000", \ - "0.0369556000, 0.0415192000, 0.0543997000, 0.0875427000, 0.1944332000, 0.5251540000, 1.4980996000", \ - "0.0500995000, 0.0565375000, 0.0698803000, 0.1025845000, 0.1999383000, 0.5277170000, 1.4935811000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.3417690000, 0.3501460000, 0.3688375000, 0.4047680000, 0.4724293000, 0.6075234000, 0.9317824000", \ - "0.3465803000, 0.3548540000, 0.3736714000, 0.4096276000, 0.4770286000, 0.6128624000, 0.9371609000", \ - "0.3586978000, 0.3672533000, 0.3858270000, 0.4217474000, 0.4883643000, 0.6245784000, 0.9486915000", \ - "0.3861022000, 0.3944859000, 0.4131878000, 0.4489641000, 0.5166054000, 0.6517420000, 0.9760130000", \ - "0.4436336000, 0.4522185000, 0.4708556000, 0.5067898000, 0.5739089000, 0.7096336000, 1.0339392000", \ - "0.5644096000, 0.5729490000, 0.5917729000, 0.6277982000, 0.6949138000, 0.8311873000, 1.1555403000", \ - "0.7841740000, 0.7938076000, 0.8150305000, 0.8547439000, 0.9281249000, 1.0702916000, 1.3987616000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1097419000, 0.1165753000, 0.1321244000, 0.1666571000, 0.2508511000, 0.4858541000, 1.1610625000", \ - "0.1140041000, 0.1207555000, 0.1362840000, 0.1708530000, 0.2548414000, 0.4890314000, 1.1679256000", \ - "0.1231353000, 0.1298957000, 0.1454124000, 0.1799997000, 0.2641806000, 0.4979476000, 1.1771515000", \ - "0.1442615000, 0.1509662000, 0.1664263000, 0.2008763000, 0.2850443000, 0.5200549000, 1.1950521000", \ - "0.1861258000, 0.1931883000, 0.2091881000, 0.2439927000, 0.3283664000, 0.5627309000, 1.2377294000", \ - "0.2472406000, 0.2554355000, 0.2735299000, 0.3105054000, 0.3960691000, 0.6304939000, 1.3062879000", \ - "0.3094142000, 0.3198932000, 0.3423520000, 0.3855379000, 0.4744092000, 0.7097001000, 1.3845970000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0421644000, 0.0475404000, 0.0592311000, 0.0811147000, 0.1342708000, 0.2689918000, 0.6614829000", \ - "0.0422806000, 0.0470376000, 0.0580719000, 0.0824140000, 0.1348856000, 0.2678721000, 0.6641943000", \ - "0.0422823000, 0.0473564000, 0.0582053000, 0.0810551000, 0.1352831000, 0.2692107000, 0.6628971000", \ - "0.0422169000, 0.0475112000, 0.0591493000, 0.0812353000, 0.1345340000, 0.2687859000, 0.6632069000", \ - "0.0423061000, 0.0474017000, 0.0585825000, 0.0815744000, 0.1340655000, 0.2686928000, 0.6627727000", \ - "0.0436475000, 0.0487688000, 0.0594140000, 0.0816133000, 0.1342598000, 0.2685804000, 0.6632540000", \ - "0.0511722000, 0.0569639000, 0.0694191000, 0.0930819000, 0.1455951000, 0.2802803000, 0.6668233000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0260104000, 0.0310472000, 0.0445638000, 0.0815680000, 0.1920879000, 0.5245304000, 1.4956508000", \ - "0.0258988000, 0.0311143000, 0.0445428000, 0.0815899000, 0.1920178000, 0.5247270000, 1.4959890000", \ - "0.0258784000, 0.0309527000, 0.0445044000, 0.0815267000, 0.1921829000, 0.5252207000, 1.4984524000", \ - "0.0256131000, 0.0307629000, 0.0442696000, 0.0813995000, 0.1922308000, 0.5260575000, 1.4989449000", \ - "0.0275869000, 0.0327953000, 0.0458961000, 0.0820395000, 0.1917684000, 0.5256475000, 1.4976358000", \ - "0.0339256000, 0.0386023000, 0.0518796000, 0.0867906000, 0.1939690000, 0.5237469000, 1.4984641000", \ - "0.0454801000, 0.0513728000, 0.0650141000, 0.0985357000, 0.1988499000, 0.5263620000, 1.4967342000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2966888000, 0.3048864000, 0.3230292000, 0.3585528000, 0.4258047000, 0.5622831000, 0.8872204000", \ - "0.3000986000, 0.3083434000, 0.3264632000, 0.3620032000, 0.4287808000, 0.5655797000, 0.8904551000", \ - "0.3094880000, 0.3176800000, 0.3358207000, 0.3714140000, 0.4387564000, 0.5752415000, 0.9002475000", \ - "0.3329020000, 0.3410615000, 0.3591603000, 0.3946949000, 0.4620726000, 0.5985829000, 0.9237213000", \ - "0.3865419000, 0.3947293000, 0.4127826000, 0.4481105000, 0.5155443000, 0.6520273000, 0.9771018000", \ - "0.5066172000, 0.5151963000, 0.5341025000, 0.5703457000, 0.6384429000, 0.7757340000, 1.1007402000", \ - "0.7175862000, 0.7275384000, 0.7492761000, 0.7909615000, 0.8669785000, 1.0108155000, 1.3416520000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0999778000, 0.1065475000, 0.1217092000, 0.1556299000, 0.2395931000, 0.4749851000, 1.1523964000", \ - "0.1045224000, 0.1110400000, 0.1261606000, 0.1601029000, 0.2441120000, 0.4784475000, 1.1543013000", \ - "0.1148857000, 0.1214365000, 0.1365783000, 0.1706205000, 0.2546058000, 0.4890454000, 1.1656691000", \ - "0.1394368000, 0.1459178000, 0.1609610000, 0.1948390000, 0.2786933000, 0.5133131000, 1.1896957000", \ - "0.1866767000, 0.1936660000, 0.2095486000, 0.2439882000, 0.3279686000, 0.5626703000, 1.2394529000", \ - "0.2466831000, 0.2554416000, 0.2742127000, 0.3116480000, 0.3970404000, 0.6320025000, 1.3095299000", \ - "0.3054222000, 0.3168583000, 0.3412488000, 0.3868843000, 0.4766590000, 0.7118651000, 1.3877627000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0403177000, 0.0454513000, 0.0564067000, 0.0809131000, 0.1341009000, 0.2692793000, 0.6645970000", \ - "0.0403784000, 0.0454349000, 0.0562697000, 0.0810416000, 0.1347255000, 0.2696366000, 0.6633448000", \ - "0.0402220000, 0.0452208000, 0.0561571000, 0.0812507000, 0.1346538000, 0.2689902000, 0.6627296000", \ - "0.0403981000, 0.0452274000, 0.0562175000, 0.0807765000, 0.1331881000, 0.2688407000, 0.6628967000", \ - "0.0404804000, 0.0452977000, 0.0562847000, 0.0812386000, 0.1338967000, 0.2688964000, 0.6649417000", \ - "0.0439283000, 0.0488479000, 0.0599842000, 0.0833458000, 0.1361176000, 0.2706134000, 0.6639809000", \ - "0.0555397000, 0.0608072000, 0.0730712000, 0.0983252000, 0.1530542000, 0.2848819000, 0.6714296000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0243722000, 0.0292848000, 0.0425673000, 0.0791830000, 0.1901391000, 0.5238031000, 1.5003229000", \ - "0.0242924000, 0.0292224000, 0.0425529000, 0.0791952000, 0.1901379000, 0.5246046000, 1.4974605000", \ - "0.0243805000, 0.0292234000, 0.0425133000, 0.0791529000, 0.1899009000, 0.5240065000, 1.4986875000", \ - "0.0242154000, 0.0292719000, 0.0425123000, 0.0791903000, 0.1899093000, 0.5242747000, 1.4981766000", \ - "0.0276299000, 0.0325990000, 0.0452883000, 0.0809080000, 0.1900966000, 0.5254184000, 1.4969698000", \ - "0.0374352000, 0.0418215000, 0.0545832000, 0.0872605000, 0.1935939000, 0.5243666000, 1.4998254000", \ - "0.0511930000, 0.0575931000, 0.0717280000, 0.1041835000, 0.2002010000, 0.5269292000, 1.4963518000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.3173250000, 0.3258464000, 0.3444654000, 0.3803552000, 0.4475086000, 0.5836571000, 0.9078566000", \ - "0.3215175000, 0.3299723000, 0.3484943000, 0.3844100000, 0.4519641000, 0.5879456000, 0.9125475000", \ - "0.3322573000, 0.3407730000, 0.3593132000, 0.3950276000, 0.4623820000, 0.5986279000, 0.9228168000", \ - "0.3586099000, 0.3671146000, 0.3857069000, 0.4217812000, 0.4891544000, 0.6252100000, 0.9499076000", \ - "0.4179878000, 0.4264962000, 0.4448482000, 0.4808681000, 0.5482967000, 0.6842684000, 1.0091580000", \ - "0.5527709000, 0.5620407000, 0.5805235000, 0.6166468000, 0.6837706000, 0.8201861000, 1.1445328000", \ - "0.7991312000, 0.8092440000, 0.8313746000, 0.8730281000, 0.9477615000, 1.0915298000, 1.4208201000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1041523000, 0.1107329000, 0.1258727000, 0.1598015000, 0.2437667000, 0.4778882000, 1.1534876000", \ - "0.1086130000, 0.1151748000, 0.1303222000, 0.1643616000, 0.2483118000, 0.4822929000, 1.1577962000", \ - "0.1180427000, 0.1245880000, 0.1397196000, 0.1737271000, 0.2576764000, 0.4915489000, 1.1675099000", \ - "0.1389509000, 0.1454902000, 0.1605895000, 0.1945476000, 0.2785047000, 0.5131796000, 1.1897913000", \ - "0.1789352000, 0.1859399000, 0.2016680000, 0.2361495000, 0.3204607000, 0.5552358000, 1.2319600000", \ - "0.2348828000, 0.2430962000, 0.2611711000, 0.2982643000, 0.3838413000, 0.6183198000, 1.2958336000", \ - "0.2887348000, 0.2993887000, 0.3224254000, 0.3662069000, 0.4556775000, 0.6901686000, 1.3664468000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0425281000, 0.0475758000, 0.0582753000, 0.0823287000, 0.1342004000, 0.2683062000, 0.6623228000", \ - "0.0421124000, 0.0471080000, 0.0582891000, 0.0823732000, 0.1339670000, 0.2686049000, 0.6626042000", \ - "0.0422143000, 0.0474383000, 0.0585750000, 0.0817110000, 0.1356039000, 0.2682895000, 0.6623487000", \ - "0.0421574000, 0.0473039000, 0.0578749000, 0.0820410000, 0.1345557000, 0.2682027000, 0.6616291000", \ - "0.0422447000, 0.0475058000, 0.0585796000, 0.0814962000, 0.1341378000, 0.2689503000, 0.6640711000", \ - "0.0445763000, 0.0491356000, 0.0596189000, 0.0824434000, 0.1358307000, 0.2695510000, 0.6637433000", \ - "0.0565960000, 0.0627225000, 0.0746297000, 0.0980748000, 0.1494204000, 0.2806371000, 0.6698126000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0243655000, 0.0292958000, 0.0425441000, 0.0790971000, 0.1901237000, 0.5243375000, 1.4947931000", \ - "0.0244157000, 0.0293618000, 0.0424922000, 0.0792588000, 0.1901833000, 0.5241360000, 1.4953877000", \ - "0.0243239000, 0.0292772000, 0.0425037000, 0.0792609000, 0.1901879000, 0.5238444000, 1.4960263000", \ - "0.0243855000, 0.0293216000, 0.0424774000, 0.0791645000, 0.1898162000, 0.5244823000, 1.4991514000", \ - "0.0269324000, 0.0316688000, 0.0446499000, 0.0804979000, 0.1901673000, 0.5246016000, 1.4992289000", \ - "0.0338182000, 0.0388488000, 0.0515380000, 0.0859075000, 0.1930097000, 0.5238776000, 1.4996295000", \ - "0.0465960000, 0.0525771000, 0.0661941000, 0.0991319000, 0.1988303000, 0.5258055000, 1.4958856000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2634756000, 0.2719917000, 0.2907479000, 0.3265168000, 0.3943286000, 0.5299948000, 0.8545976000", \ - "0.2665037000, 0.2750564000, 0.2936894000, 0.3296016000, 0.3972825000, 0.5328940000, 0.8575075000", \ - "0.2746881000, 0.2832282000, 0.3019050000, 0.3377814000, 0.4050992000, 0.5412835000, 0.8661196000", \ - "0.2977854000, 0.3063021000, 0.3249010000, 0.3606868000, 0.4283228000, 0.5646246000, 0.8891607000", \ - "0.3575866000, 0.3661590000, 0.3847275000, 0.4198523000, 0.4882057000, 0.6244392000, 0.9490845000", \ - "0.4985447000, 0.5071921000, 0.5264424000, 0.5622917000, 0.6290313000, 0.7653229000, 1.0899358000", \ - "0.7397059000, 0.7503205000, 0.7744227000, 0.8178387000, 0.8919962000, 1.0325997000, 1.3616001000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0682380000, 0.0739285000, 0.0873089000, 0.1186968000, 0.2005189000, 0.4341102000, 1.1171725000", \ - "0.0732138000, 0.0788570000, 0.0922363000, 0.1236491000, 0.2054875000, 0.4387286000, 1.1237249000", \ - "0.0846657000, 0.0902716000, 0.1035972000, 0.1349805000, 0.2170720000, 0.4519006000, 1.1400463000", \ - "0.1097726000, 0.1154401000, 0.1288101000, 0.1600632000, 0.2422684000, 0.4765587000, 1.1509399000", \ - "0.1481122000, 0.1549919000, 0.1700657000, 0.2027980000, 0.2852538000, 0.5192386000, 1.1937642000", \ - "0.1917071000, 0.2007591000, 0.2199631000, 0.2571225000, 0.3410169000, 0.5747003000, 1.2534415000", \ - "0.2269714000, 0.2387016000, 0.2641886000, 0.3118572000, 0.4017679000, 0.6350652000, 1.3106353000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0423634000, 0.0474199000, 0.0589227000, 0.0811461000, 0.1342805000, 0.2688529000, 0.6626342000", \ - "0.0420289000, 0.0470298000, 0.0591286000, 0.0812220000, 0.1341662000, 0.2685524000, 0.6619351000", \ - "0.0421485000, 0.0473767000, 0.0584117000, 0.0810839000, 0.1343054000, 0.2687122000, 0.6639446000", \ - "0.0425609000, 0.0475756000, 0.0579466000, 0.0812177000, 0.1349067000, 0.2688243000, 0.6628104000", \ - "0.0420543000, 0.0471667000, 0.0590413000, 0.0811248000, 0.1331540000, 0.2676717000, 0.6641169000", \ - "0.0453205000, 0.0501665000, 0.0602949000, 0.0825290000, 0.1352233000, 0.2693523000, 0.6644321000", \ - "0.0631228000, 0.0697780000, 0.0816037000, 0.1033079000, 0.1520249000, 0.2792274000, 0.6686026000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0200722000, 0.0245489000, 0.0370619000, 0.0740243000, 0.1873470000, 0.5248376000, 1.5035910000", \ - "0.0200894000, 0.0245336000, 0.0370803000, 0.0740306000, 0.1873460000, 0.5231253000, 1.5038364000", \ - "0.0200817000, 0.0245385000, 0.0371756000, 0.0742471000, 0.1871749000, 0.5235646000, 1.4989497000", \ - "0.0212107000, 0.0254417000, 0.0378606000, 0.0744958000, 0.1871307000, 0.5235003000, 1.4965209000", \ - "0.0275541000, 0.0315655000, 0.0431042000, 0.0775198000, 0.1880258000, 0.5235511000, 1.4949896000", \ - "0.0388365000, 0.0432995000, 0.0545857000, 0.0860307000, 0.1908677000, 0.5219922000, 1.4992853000", \ - "0.0543745000, 0.0605566000, 0.0750959000, 0.1076369000, 0.1995252000, 0.5241374000, 1.4924216000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221o_4") { - leakage_power () { - value : 0.0048020000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0088948000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0048025000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0096033000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0048009000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0102735000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0251463000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0422681000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0048012000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0060180000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0048011000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0067691000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0047993000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0064033000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0021035000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0044814000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0048012000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0058405000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0048010000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0065917000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0048011000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0062239000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0021035000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0044814000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0021024000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0043889000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0021032000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0043021000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0021028000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0043684000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0251013000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0021183000; - when : "A1&A2&B1&B2&!C1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a221o"; - cell_leakage_power : 0.0074062540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092947000, 0.0092975000, 0.0093039000, 0.0093032000, 0.0093017000, 0.0092982000, 0.0092901000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007062000, -0.007073800, -0.007100900, -0.007083800, -0.007044500, -0.006953500, -0.006744000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046600000; - } - pin ("A2") { - capacitance : 0.0043610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080383000, 0.0080284000, 0.0080056000, 0.0080032000, 0.0079975000, 0.0079845000, 0.0079546000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007939500, -0.007939300, -0.007938900, -0.007938300, -0.007937100, -0.007934100, -0.007927200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046260000; - } - pin ("B1") { - capacitance : 0.0042340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091369000, 0.0091375000, 0.0091390000, 0.0091418000, 0.0091482000, 0.0091631000, 0.0091973000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006492200, -0.006503100, -0.006528300, -0.006511600, -0.006473100, -0.006384400, -0.006179900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044700000; - } - pin ("B2") { - capacitance : 0.0042700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079273000, 0.0079142000, 0.0078840000, 0.0078841000, 0.0078843000, 0.0078848000, 0.0078858000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007884400, -0.007878000, -0.007863300, -0.007865200, -0.007869600, -0.007879900, -0.007903400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045980000; - } - pin ("C1") { - capacitance : 0.0043110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044322000, 0.0044310000, 0.0044283000, 0.0044604000, 0.0045344000, 0.0047048000, 0.0050978000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003531100, -0.003526000, -0.003514100, -0.003511700, -0.003506400, -0.003494200, -0.003465700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046770000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0393167000, 0.0375542000, 0.0323322000, 0.0172425000, -0.035207500, -0.217920600, -0.815617300", \ - "0.0389494000, 0.0371450000, 0.0318161000, 0.0168152000, -0.035548400, -0.218159700, -0.815886900", \ - "0.0383543000, 0.0365510000, 0.0312412000, 0.0164365000, -0.036121700, -0.218574100, -0.816370700", \ - "0.0377638000, 0.0359774000, 0.0306018000, 0.0156013000, -0.036696900, -0.219222200, -0.816987300", \ - "0.0373424000, 0.0353950000, 0.0302129000, 0.0152097000, -0.037180700, -0.219874400, -0.817479600", \ - "0.0372851000, 0.0354404000, 0.0300378000, 0.0150567000, -0.037544900, -0.220104600, -0.817617900", \ - "0.0476969000, 0.0456955000, 0.0395404000, 0.0214559000, -0.036992400, -0.220271800, -0.817600300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0374336000, 0.0393576000, 0.0454948000, 0.0648983000, 0.1237758000, 0.3095918000, 0.9007152000", \ - "0.0372709000, 0.0392045000, 0.0453260000, 0.0647229000, 0.1236088000, 0.3093896000, 0.9004196000", \ - "0.0370040000, 0.0389425000, 0.0450834000, 0.0644451000, 0.1234591000, 0.3090494000, 0.9006694000", \ - "0.0367217000, 0.0386449000, 0.0447752000, 0.0640964000, 0.1230529000, 0.3085198000, 0.9010636000", \ - "0.0368263000, 0.0387135000, 0.0446647000, 0.0637406000, 0.1226538000, 0.3083797000, 0.9040361000", \ - "0.0389554000, 0.0406872000, 0.0463295000, 0.0642253000, 0.1227576000, 0.3078765000, 0.9002835000", \ - "0.0418982000, 0.0435648000, 0.0490080000, 0.0671471000, 0.1251530000, 0.3103735000, 0.9020783000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0452384000, 0.0437792000, 0.0383515000, 0.0232606000, -0.029484800, -0.212526800, -0.810463300", \ - "0.0451071000, 0.0431795000, 0.0377567000, 0.0230596000, -0.029686900, -0.212679000, -0.810623200", \ - "0.0450523000, 0.0432747000, 0.0374986000, 0.0228102000, -0.029919700, -0.212951200, -0.810874100", \ - "0.0445688000, 0.0427308000, 0.0373229000, 0.0221827000, -0.030412200, -0.213207300, -0.811049800", \ - "0.0442122000, 0.0423760000, 0.0368925000, 0.0219053000, -0.030792400, -0.213656600, -0.811428200", \ - "0.0443526000, 0.0425123000, 0.0369542000, 0.0218144000, -0.030812800, -0.213771800, -0.811497900", \ - "0.0529081000, 0.0507834000, 0.0446469000, 0.0259276000, -0.031811700, -0.213687500, -0.811262600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0384772000, 0.0404077000, 0.0465307000, 0.0659203000, 0.1246597000, 0.3100446000, 0.9008526000", \ - "0.0382743000, 0.0402091000, 0.0463444000, 0.0656805000, 0.1245613000, 0.3097113000, 0.9010778000", \ - "0.0380145000, 0.0399224000, 0.0460760000, 0.0654872000, 0.1242595000, 0.3095617000, 0.9010344000", \ - "0.0378200000, 0.0397524000, 0.0458756000, 0.0652214000, 0.1239861000, 0.3093824000, 0.9008178000", \ - "0.0378038000, 0.0396709000, 0.0457634000, 0.0649323000, 0.1238671000, 0.3091422000, 0.9051084000", \ - "0.0394910000, 0.0412448000, 0.0469924000, 0.0651722000, 0.1237414000, 0.3082379000, 0.9010245000", \ - "0.0415151000, 0.0432169000, 0.0488759000, 0.0668499000, 0.1252085000, 0.3106564000, 0.9041559000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0333818000, 0.0315999000, 0.0264142000, 0.0112698000, -0.041344100, -0.224359100, -0.822254200", \ - "0.0330574000, 0.0312367000, 0.0259867000, 0.0108847000, -0.041636700, -0.224552200, -0.822444500", \ - "0.0327749000, 0.0310012000, 0.0256743000, 0.0107103000, -0.041961900, -0.224947400, -0.822794300", \ - "0.0319469000, 0.0301571000, 0.0248125000, 0.0098881000, -0.042738200, -0.225514900, -0.823428800", \ - "0.0313839000, 0.0295701000, 0.0242507000, 0.0091935000, -0.043351400, -0.226158000, -0.823913200", \ - "0.0316589000, 0.0297026000, 0.0242004000, 0.0089527000, -0.043366100, -0.226329900, -0.823994300", \ - "0.0412632000, 0.0391707000, 0.0328818000, 0.0139873000, -0.044538400, -0.226729900, -0.824155000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0340370000, 0.0359527000, 0.0421004000, 0.0615146000, 0.1207453000, 0.3070146000, 0.8993243000", \ - "0.0339852000, 0.0358837000, 0.0420636000, 0.0614891000, 0.1207952000, 0.3070879000, 0.9033042000", \ - "0.0338872000, 0.0357809000, 0.0419386000, 0.0612984000, 0.1206555000, 0.3068006000, 0.8988068000", \ - "0.0335916000, 0.0355104000, 0.0416554000, 0.0609382000, 0.1201382000, 0.3063401000, 0.8993349000", \ - "0.0334210000, 0.0352648000, 0.0412879000, 0.0603110000, 0.1192966000, 0.3057047000, 0.9025832000", \ - "0.0346926000, 0.0364665000, 0.0421408000, 0.0603674000, 0.1189245000, 0.3041682000, 0.8979926000", \ - "0.0368405000, 0.0384931000, 0.0440008000, 0.0620624000, 0.1203870000, 0.3059662000, 0.8991494000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0400470000, 0.0381496000, 0.0331952000, 0.0179878000, -0.034702200, -0.217496200, -0.815118500", \ - "0.0401129000, 0.0382273000, 0.0328345000, 0.0176760000, -0.034877900, -0.217675400, -0.815273300", \ - "0.0397349000, 0.0378486000, 0.0324582000, 0.0174073000, -0.035221500, -0.217903300, -0.815376100", \ - "0.0393261000, 0.0375182000, 0.0321056000, 0.0170002000, -0.035633500, -0.218168500, -0.815842900", \ - "0.0389925000, 0.0370696000, 0.0316337000, 0.0168001000, -0.035914200, -0.218625500, -0.816100300", \ - "0.0395974000, 0.0376612000, 0.0321648000, 0.0169054000, -0.036020400, -0.218772800, -0.816180400", \ - "0.0489334000, 0.0468195000, 0.0403904000, 0.0214274000, -0.036952600, -0.218950200, -0.816222600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0355391000, 0.0374337000, 0.0436028000, 0.0630166000, 0.1223025000, 0.3085542000, 0.9050340000", \ - "0.0354829000, 0.0374014000, 0.0435310000, 0.0628618000, 0.1223390000, 0.3085540000, 0.9049752000", \ - "0.0353798000, 0.0372738000, 0.0434378000, 0.0627874000, 0.1221362000, 0.3083226000, 0.9006002000", \ - "0.0350765000, 0.0369711000, 0.0431282000, 0.0624398000, 0.1217769000, 0.3080448000, 0.9000011000", \ - "0.0347449000, 0.0366217000, 0.0427064000, 0.0617927000, 0.1210259000, 0.3074119000, 0.9003603000", \ - "0.0357377000, 0.0375439000, 0.0432972000, 0.0616980000, 0.1203856000, 0.3059902000, 0.8987427000", \ - "0.0374471000, 0.0391288000, 0.0447318000, 0.0628389000, 0.1215255000, 0.3072247000, 0.8977268000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0389789000, 0.0371190000, 0.0317649000, 0.0166735000, -0.035799900, -0.218278300, -0.815523000", \ - "0.0386449000, 0.0367433000, 0.0313545000, 0.0164851000, -0.036008700, -0.218506700, -0.815773600", \ - "0.0380907000, 0.0363091000, 0.0309782000, 0.0158983000, -0.036553300, -0.219059800, -0.816284300", \ - "0.0375211000, 0.0357232000, 0.0303234000, 0.0152085000, -0.037156300, -0.219560500, -0.816824500", \ - "0.0371885000, 0.0353172000, 0.0300660000, 0.0149979000, -0.037547300, -0.219889400, -0.817171700", \ - "0.0385592000, 0.0366849000, 0.0306069000, 0.0154288000, -0.037405700, -0.219928300, -0.816993700", \ - "0.0514704000, 0.0492909000, 0.0415241000, 0.0236009000, -0.035642700, -0.218021500, -0.815419300"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016002750, 0.0051217590, 0.0163924400, 0.0524648300, 0.1679163000, 0.5374244000"); - values("0.0253548000, 0.0273413000, 0.0335763000, 0.0528704000, 0.1118235000, 0.2974297000, 0.8938236000", \ - "0.0253629000, 0.0273423000, 0.0335995000, 0.0528581000, 0.1118474000, 0.2975230000, 0.8845480000", \ - "0.0252566000, 0.0272653000, 0.0334578000, 0.0525809000, 0.1115767000, 0.2971688000, 0.8850692000", \ - "0.0250949000, 0.0269997000, 0.0330807000, 0.0520216000, 0.1109488000, 0.2970082000, 0.8904426000", \ - "0.0252175000, 0.0270105000, 0.0329673000, 0.0517217000, 0.1102565000, 0.2963734000, 0.8900578000", \ - "0.0266912000, 0.0284184000, 0.0341220000, 0.0525076000, 0.1103672000, 0.2947405000, 0.8846824000", \ - "0.0296640000, 0.0313189000, 0.0367823000, 0.0547043000, 0.1128218000, 0.2975752000, 0.8866761000"); - } - } - max_capacitance : 0.5374240000; - max_transition : 1.5046820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.3464217000, 0.3518557000, 0.3658939000, 0.3967628000, 0.4596249000, 0.5925662000, 0.9253375000", \ - "0.3507587000, 0.3561827000, 0.3702082000, 0.4013398000, 0.4641059000, 0.5965062000, 0.9290657000", \ - "0.3613834000, 0.3667966000, 0.3807894000, 0.4115830000, 0.4746191000, 0.6071273000, 0.9401021000", \ - "0.3863350000, 0.3918072000, 0.4057682000, 0.4365975000, 0.4988607000, 0.6320558000, 0.9650390000", \ - "0.4399207000, 0.4453003000, 0.4594160000, 0.4903203000, 0.5531295000, 0.6857855000, 1.0184130000", \ - "0.5518964000, 0.5573588000, 0.5715844000, 0.6027366000, 0.6658518000, 0.7985021000, 1.1312374000", \ - "0.7481433000, 0.7540601000, 0.7699731000, 0.8042277000, 0.8726704000, 1.0125635000, 1.3512473000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.1152505000, 0.1202567000, 0.1332866000, 0.1646865000, 0.2427692000, 0.4697270000, 1.1853456000", \ - "0.1193474000, 0.1243422000, 0.1373896000, 0.1687371000, 0.2468142000, 0.4736707000, 1.1899023000", \ - "0.1293987000, 0.1343494000, 0.1474266000, 0.1787234000, 0.2568034000, 0.4834290000, 1.2005379000", \ - "0.1543518000, 0.1592329000, 0.1721667000, 0.2032939000, 0.2810673000, 0.5087415000, 1.2243745000", \ - "0.2058786000, 0.2108836000, 0.2240073000, 0.2551500000, 0.3327169000, 0.5594718000, 1.2777630000", \ - "0.2748931000, 0.2808357000, 0.2957956000, 0.3289755000, 0.4080522000, 0.6352526000, 1.3513854000", \ - "0.3446929000, 0.3521208000, 0.3709928000, 0.4112827000, 0.4944782000, 0.7216449000, 1.4380679000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0431060000, 0.0463558000, 0.0548923000, 0.0748084000, 0.1209866000, 0.2484048000, 0.6458831000", \ - "0.0429074000, 0.0460487000, 0.0546531000, 0.0746229000, 0.1214528000, 0.2487836000, 0.6457728000", \ - "0.0429754000, 0.0461814000, 0.0547767000, 0.0740072000, 0.1207766000, 0.2489512000, 0.6441788000", \ - "0.0431137000, 0.0463489000, 0.0546351000, 0.0739272000, 0.1227337000, 0.2489743000, 0.6445909000", \ - "0.0428998000, 0.0462471000, 0.0545222000, 0.0750351000, 0.1211342000, 0.2486371000, 0.6456166000", \ - "0.0444939000, 0.0478098000, 0.0557178000, 0.0752346000, 0.1229887000, 0.2489224000, 0.6450688000", \ - "0.0523832000, 0.0555612000, 0.0644394000, 0.0852572000, 0.1338571000, 0.2606567000, 0.6514964000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0297265000, 0.0332929000, 0.0435943000, 0.0734905000, 0.1675916000, 0.4820512000, 1.4980597000", \ - "0.0295523000, 0.0331784000, 0.0434715000, 0.0733396000, 0.1675221000, 0.4819848000, 1.4961433000", \ - "0.0297039000, 0.0330412000, 0.0433956000, 0.0732509000, 0.1671973000, 0.4817086000, 1.4988369000", \ - "0.0292200000, 0.0327995000, 0.0429619000, 0.0729032000, 0.1669867000, 0.4811362000, 1.5021042000", \ - "0.0312804000, 0.0346710000, 0.0441557000, 0.0733448000, 0.1668930000, 0.4809652000, 1.5013024000", \ - "0.0396471000, 0.0427072000, 0.0517057000, 0.0790402000, 0.1698286000, 0.4808596000, 1.5005549000", \ - "0.0534642000, 0.0573711000, 0.0677336000, 0.0946561000, 0.1765924000, 0.4838241000, 1.5000071000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.3844048000, 0.3903275000, 0.4052450000, 0.4376886000, 0.5020598000, 0.6367841000, 0.9714113000", \ - "0.3891395000, 0.3950087000, 0.4100269000, 0.4424137000, 0.5068583000, 0.6415289000, 0.9761196000", \ - "0.4016669000, 0.4075334000, 0.4224523000, 0.4548906000, 0.5192806000, 0.6540307000, 0.9886930000", \ - "0.4296205000, 0.4354836000, 0.4504203000, 0.4830292000, 0.5473111000, 0.6813435000, 1.0162293000", \ - "0.4883287000, 0.4941765000, 0.5091720000, 0.5417247000, 0.6060597000, 0.7403387000, 1.0750204000", \ - "0.6107082000, 0.6166395000, 0.6315519000, 0.6640924000, 0.7285648000, 0.8634579000, 1.1979936000", \ - "0.8386296000, 0.8448746000, 0.8617533000, 0.8970429000, 0.9659912000, 1.1068204000, 1.4454890000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.1205333000, 0.1255288000, 0.1385771000, 0.1699240000, 0.2478381000, 0.4742080000, 1.1900738000", \ - "0.1247299000, 0.1296882000, 0.1427815000, 0.1740974000, 0.2520624000, 0.4783558000, 1.1951480000", \ - "0.1333462000, 0.1383043000, 0.1513262000, 0.1826863000, 0.2605730000, 0.4876052000, 1.2021018000", \ - "0.1530726000, 0.1580271000, 0.1709262000, 0.2020902000, 0.2798375000, 0.5069668000, 1.2214152000", \ - "0.1930248000, 0.1980710000, 0.2113420000, 0.2427994000, 0.3207085000, 0.5470447000, 1.2645565000", \ - "0.2541325000, 0.2597490000, 0.2742611000, 0.3077242000, 0.3869841000, 0.6138134000, 1.3302522000", \ - "0.3188460000, 0.3258703000, 0.3436618000, 0.3822828000, 0.4656182000, 0.6933569000, 1.4082674000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0472274000, 0.0505285000, 0.0591248000, 0.0782502000, 0.1245600000, 0.2519810000, 0.6477529000", \ - "0.0472886000, 0.0506319000, 0.0588197000, 0.0784520000, 0.1250813000, 0.2519472000, 0.6480607000", \ - "0.0470559000, 0.0509768000, 0.0588193000, 0.0782250000, 0.1245650000, 0.2519706000, 0.6477718000", \ - "0.0474533000, 0.0503903000, 0.0597707000, 0.0790217000, 0.1261456000, 0.2519712000, 0.6491639000", \ - "0.0471507000, 0.0505060000, 0.0587163000, 0.0793528000, 0.1249847000, 0.2517770000, 0.6494807000", \ - "0.0476304000, 0.0510722000, 0.0593174000, 0.0783363000, 0.1250638000, 0.2515449000, 0.6480411000", \ - "0.0554344000, 0.0589611000, 0.0684143000, 0.0882428000, 0.1351152000, 0.2612466000, 0.6518869000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0295852000, 0.0332053000, 0.0434852000, 0.0733584000, 0.1675016000, 0.4819657000, 1.4964736000", \ - "0.0298050000, 0.0331535000, 0.0434851000, 0.0733640000, 0.1672160000, 0.4815885000, 1.4991177000", \ - "0.0296496000, 0.0331655000, 0.0434590000, 0.0733762000, 0.1675876000, 0.4820530000, 1.4998077000", \ - "0.0292155000, 0.0328315000, 0.0431660000, 0.0731038000, 0.1674430000, 0.4819969000, 1.4996518000", \ - "0.0308759000, 0.0342790000, 0.0445441000, 0.0734158000, 0.1669027000, 0.4811339000, 1.5016712000", \ - "0.0361524000, 0.0396369000, 0.0496299000, 0.0780650000, 0.1691763000, 0.4812837000, 1.5022035000", \ - "0.0481688000, 0.0518187000, 0.0619230000, 0.0899110000, 0.1753829000, 0.4826527000, 1.4981044000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.3200536000, 0.3254948000, 0.3394739000, 0.3702936000, 0.4329894000, 0.5656701000, 0.8984707000", \ - "0.3237118000, 0.3291254000, 0.3430813000, 0.3741776000, 0.4367837000, 0.5689580000, 0.9015699000", \ - "0.3332686000, 0.3386839000, 0.3526334000, 0.3834732000, 0.4461809000, 0.5789578000, 0.9117649000", \ - "0.3587999000, 0.3642403000, 0.3782674000, 0.4091124000, 0.4718030000, 0.6041146000, 0.9369215000", \ - "0.4188271000, 0.4242901000, 0.4382784000, 0.4690831000, 0.5315060000, 0.6643291000, 0.9972330000", \ - "0.5561053000, 0.5616625000, 0.5756843000, 0.6070692000, 0.6691458000, 0.8023126000, 1.1350002000", \ - "0.8096689000, 0.8160280000, 0.8327038000, 0.8684482000, 0.9386272000, 1.0802671000, 1.4191369000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.1120162000, 0.1167356000, 0.1292581000, 0.1597508000, 0.2366666000, 0.4633991000, 1.1777741000", \ - "0.1162114000, 0.1209200000, 0.1335135000, 0.1639816000, 0.2409141000, 0.4677213000, 1.1846157000", \ - "0.1264774000, 0.1311830000, 0.1437329000, 0.1742205000, 0.2511876000, 0.4777797000, 1.1912800000", \ - "0.1503184000, 0.1550228000, 0.1675376000, 0.1979371000, 0.2747187000, 0.5013631000, 1.2148971000", \ - "0.1975557000, 0.2024317000, 0.2153668000, 0.2461662000, 0.3232438000, 0.5501122000, 1.2664491000", \ - "0.2580532000, 0.2639057000, 0.2788408000, 0.3122422000, 0.3908168000, 0.6179037000, 1.3343309000", \ - "0.3106430000, 0.3181650000, 0.3370300000, 0.3785317000, 0.4622392000, 0.6894080000, 1.4050354000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0430234000, 0.0463006000, 0.0549753000, 0.0747002000, 0.1209509000, 0.2486037000, 0.6463764000", \ - "0.0428683000, 0.0460332000, 0.0548592000, 0.0745688000, 0.1214271000, 0.2487674000, 0.6463109000", \ - "0.0430358000, 0.0463544000, 0.0544063000, 0.0746055000, 0.1209478000, 0.2483667000, 0.6464298000", \ - "0.0429913000, 0.0462584000, 0.0546151000, 0.0740214000, 0.1212848000, 0.2485933000, 0.6455338000", \ - "0.0429543000, 0.0462188000, 0.0544862000, 0.0738163000, 0.1217613000, 0.2481896000, 0.6456946000", \ - "0.0454734000, 0.0483841000, 0.0571443000, 0.0760392000, 0.1224702000, 0.2488651000, 0.6460081000", \ - "0.0580494000, 0.0612595000, 0.0706292000, 0.0909290000, 0.1374251000, 0.2616526000, 0.6518152000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0274916000, 0.0309539000, 0.0410922000, 0.0705482000, 0.1645362000, 0.4796226000, 1.4985110000", \ - "0.0274792000, 0.0310761000, 0.0410551000, 0.0705922000, 0.1642893000, 0.4797626000, 1.5004316000", \ - "0.0274373000, 0.0310675000, 0.0409767000, 0.0703902000, 0.1645325000, 0.4800270000, 1.4959596000", \ - "0.0275733000, 0.0309778000, 0.0409632000, 0.0705043000, 0.1645451000, 0.4800029000, 1.4964605000", \ - "0.0302686000, 0.0334122000, 0.0431778000, 0.0719938000, 0.1649239000, 0.4797329000, 1.5018159000", \ - "0.0389270000, 0.0421020000, 0.0511629000, 0.0784764000, 0.1684893000, 0.4800311000, 1.4998157000", \ - "0.0533233000, 0.0579323000, 0.0686965000, 0.0951624000, 0.1764669000, 0.4824210000, 1.4976571000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.3592620000, 0.3651168000, 0.3801318000, 0.4125408000, 0.4769408000, 0.6117701000, 0.9465517000", \ - "0.3631396000, 0.3689713000, 0.3840032000, 0.4164646000, 0.4808761000, 0.6155859000, 0.9505017000", \ - "0.3735796000, 0.3794328000, 0.3943836000, 0.4269952000, 0.4913846000, 0.6259913000, 0.9604716000", \ - "0.3999910000, 0.4058512000, 0.4208555000, 0.4531930000, 0.5178257000, 0.6518380000, 0.9870404000", \ - "0.4579054000, 0.4637493000, 0.4787805000, 0.5109748000, 0.5754453000, 0.7101242000, 1.0452706000", \ - "0.5889561000, 0.5948112000, 0.6098035000, 0.6423349000, 0.7067564000, 0.8419275000, 1.1766577000", \ - "0.8332724000, 0.8399993000, 0.8572228000, 0.8942549000, 0.9652056000, 1.1069710000, 1.4470360000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.1181824000, 0.1228927000, 0.1354357000, 0.1659215000, 0.2427805000, 0.4695894000, 1.1851037000", \ - "0.1229357000, 0.1276234000, 0.1401817000, 0.1706612000, 0.2477401000, 0.4743785000, 1.1902003000", \ - "0.1323438000, 0.1370521000, 0.1495913000, 0.1800903000, 0.2570415000, 0.4837264000, 1.1981045000", \ - "0.1528809000, 0.1575689000, 0.1701004000, 0.2005205000, 0.2774456000, 0.5039156000, 1.2182113000", \ - "0.1938033000, 0.1987465000, 0.2117114000, 0.2425399000, 0.3197643000, 0.5458320000, 1.2615998000", \ - "0.2556529000, 0.2612385000, 0.2757471000, 0.3089046000, 0.3879266000, 0.6145653000, 1.3307906000", \ - "0.3225520000, 0.3296718000, 0.3474636000, 0.3870858000, 0.4710366000, 0.6987703000, 1.4136823000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0472971000, 0.0507115000, 0.0592188000, 0.0783891000, 0.1246678000, 0.2518698000, 0.6478978000", \ - "0.0470418000, 0.0506258000, 0.0589275000, 0.0781785000, 0.1247007000, 0.2518521000, 0.6484216000", \ - "0.0472055000, 0.0505958000, 0.0587913000, 0.0794430000, 0.1249190000, 0.2518839000, 0.6491248000", \ - "0.0473827000, 0.0507280000, 0.0592260000, 0.0782712000, 0.1244379000, 0.2519182000, 0.6481419000", \ - "0.0473960000, 0.0507550000, 0.0588300000, 0.0793405000, 0.1252830000, 0.2519154000, 0.6484131000", \ - "0.0486031000, 0.0519730000, 0.0602255000, 0.0789597000, 0.1249090000, 0.2514550000, 0.6486181000", \ - "0.0602593000, 0.0639699000, 0.0729583000, 0.0928121000, 0.1386204000, 0.2635828000, 0.6533864000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0274901000, 0.0309927000, 0.0410986000, 0.0705918000, 0.1642721000, 0.4797458000, 1.5011163000", \ - "0.0275779000, 0.0310054000, 0.0410400000, 0.0704315000, 0.1641060000, 0.4797741000, 1.5014219000", \ - "0.0274402000, 0.0310545000, 0.0410217000, 0.0704544000, 0.1645372000, 0.4795929000, 1.4986559000", \ - "0.0274845000, 0.0310538000, 0.0409530000, 0.0703950000, 0.1644510000, 0.4803427000, 1.4951551000", \ - "0.0292834000, 0.0327784000, 0.0428150000, 0.0716118000, 0.1647976000, 0.4794715000, 1.5008554000", \ - "0.0354172000, 0.0392589000, 0.0488176000, 0.0769748000, 0.1676436000, 0.4790502000, 1.4986228000", \ - "0.0483116000, 0.0525266000, 0.0632345000, 0.0905118000, 0.1754872000, 0.4815190000, 1.4956237000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.2967760000, 0.3026405000, 0.3177805000, 0.3501663000, 0.4141191000, 0.5492211000, 0.8844618000", \ - "0.2990411000, 0.3048930000, 0.3199375000, 0.3523765000, 0.4168753000, 0.5519672000, 0.8868545000", \ - "0.3064946000, 0.3122037000, 0.3274283000, 0.3597965000, 0.4241733000, 0.5590545000, 0.8942697000", \ - "0.3283663000, 0.3343377000, 0.3492940000, 0.3816332000, 0.4467106000, 0.5815824000, 0.9163535000", \ - "0.3901187000, 0.3959398000, 0.4110427000, 0.4434889000, 0.5080647000, 0.6430432000, 0.9779750000", \ - "0.5390816000, 0.5449350000, 0.5595147000, 0.5913137000, 0.6554415000, 0.7904962000, 1.1255243000", \ - "0.8105999000, 0.8179239000, 0.8352329000, 0.8747717000, 0.9449539000, 1.0829160000, 1.4221549000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0720098000, 0.0758647000, 0.0863328000, 0.1129561000, 0.1854349000, 0.4095517000, 1.1295165000", \ - "0.0766729000, 0.0805274000, 0.0910126000, 0.1176054000, 0.1900667000, 0.4139937000, 1.1279886000", \ - "0.0877833000, 0.0916673000, 0.1020426000, 0.1285090000, 0.2009452000, 0.4262327000, 1.1386978000", \ - "0.1118964000, 0.1157782000, 0.1262184000, 0.1526405000, 0.2252365000, 0.4498414000, 1.1625938000", \ - "0.1476243000, 0.1521875000, 0.1640625000, 0.1921065000, 0.2653784000, 0.4903695000, 1.2076683000", \ - "0.1846928000, 0.1907756000, 0.2061692000, 0.2385804000, 0.3141084000, 0.5387112000, 1.2558323000", \ - "0.2031015000, 0.2108075000, 0.2307060000, 0.2736157000, 0.3567041000, 0.5814056000, 1.2950849000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0472344000, 0.0506351000, 0.0594945000, 0.0782015000, 0.1260407000, 0.2518463000, 0.6472191000", \ - "0.0472437000, 0.0506699000, 0.0588375000, 0.0781596000, 0.1245888000, 0.2517520000, 0.6481777000", \ - "0.0476614000, 0.0507086000, 0.0591750000, 0.0783399000, 0.1251515000, 0.2516187000, 0.6476473000", \ - "0.0473724000, 0.0507371000, 0.0593319000, 0.0782260000, 0.1244958000, 0.2515372000, 0.6482918000", \ - "0.0476751000, 0.0511018000, 0.0600413000, 0.0783915000, 0.1244775000, 0.2515945000, 0.6479774000", \ - "0.0476288000, 0.0509111000, 0.0588367000, 0.0776655000, 0.1244908000, 0.2513502000, 0.6478927000", \ - "0.0673191000, 0.0711152000, 0.0818570000, 0.0996817000, 0.1396778000, 0.2607943000, 0.6533068000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016002700, 0.0051217600, 0.0163924000, 0.0524648000, 0.1679160000, 0.5374240000"); - values("0.0214339000, 0.0244152000, 0.0334145000, 0.0620709000, 0.1583126000, 0.4770599000, 1.5046822000", \ - "0.0214395000, 0.0243973000, 0.0334001000, 0.0620884000, 0.1584360000, 0.4775103000, 1.4973917000", \ - "0.0214939000, 0.0243341000, 0.0334766000, 0.0622244000, 0.1584390000, 0.4779426000, 1.4920675000", \ - "0.0226485000, 0.0254311000, 0.0342940000, 0.0627442000, 0.1585996000, 0.4783252000, 1.4968172000", \ - "0.0292081000, 0.0316994000, 0.0399747000, 0.0664780000, 0.1595460000, 0.4762687000, 1.5030469000", \ - "0.0407565000, 0.0438335000, 0.0523451000, 0.0763149000, 0.1635060000, 0.4760393000, 1.4942886000", \ - "0.0560714000, 0.0607372000, 0.0714394000, 0.0984788000, 0.1746920000, 0.4772001000, 1.4894673000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221oi_1") { - leakage_power () { - value : 0.0029956000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0003730000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0006432000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0006424000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002996000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0028331000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0006277000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0008980000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0008971000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002996000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0028331000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0005802000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0008505000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0029956000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0008496000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002996000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0028331000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0004348000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0041349000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0004361000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0040958000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0004363000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0040061000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0001882000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0004438000; - when : "A1&A2&B1&B2&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a221oi"; - cell_leakage_power : 0.0017779970; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046994000, 0.0046965000, 0.0046899000, 0.0046903000, 0.0046910000, 0.0046928000, 0.0046968000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003736500, -0.003738400, -0.003742700, -0.003736700, -0.003722700, -0.003690500, -0.003616200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023910000; - } - pin ("A2") { - capacitance : 0.0023040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041883000, 0.0041969000, 0.0042168000, 0.0042187000, 0.0042231000, 0.0042332000, 0.0042566000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004214300, -0.004211000, -0.004203300, -0.004203100, -0.004202800, -0.004202100, -0.004200300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024240000; - } - pin ("B1") { - capacitance : 0.0023250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047516000, 0.0047504000, 0.0047476000, 0.0047479000, 0.0047485000, 0.0047499000, 0.0047530000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003919500, -0.003921400, -0.003925900, -0.003918700, -0.003902100, -0.003863900, -0.003775900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024460000; - } - pin ("B2") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041163000, 0.0041129000, 0.0041052000, 0.0041063000, 0.0041089000, 0.0041150000, 0.0041291000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004111200, -0.004111700, -0.004112700, -0.004113200, -0.004114300, -0.004117000, -0.004123200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025060000; - } - pin ("C1") { - capacitance : 0.0022490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021460000, 0.0021422000, 0.0021334000, 0.0021469000, 0.0021780000, 0.0022497000, 0.0024149000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001750100, -0.001749700, -0.001748700, -0.001748100, -0.001746600, -0.001743200, -0.001735500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024210000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A1&!B2&!C1) | (!A2&!B1&!C1) | (!A2&!B2&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0080782000, 0.0071216000, 0.0050341000, 0.0004432000, -0.009528800, -0.031399700, -0.079496400", \ - "0.0079748000, 0.0070315000, 0.0049303000, 0.0003583000, -0.009624300, -0.031485000, -0.079570100", \ - "0.0078517000, 0.0068991000, 0.0047823000, 0.0002103000, -0.009737300, -0.031589700, -0.079664300", \ - "0.0076757000, 0.0067392000, 0.0046532000, 7.180000e-05, -0.009870100, -0.031726600, -0.079793200", \ - "0.0075230000, 0.0065768000, 0.0044979000, -6.14000e-05, -0.009981300, -0.031865300, -0.079887000", \ - "0.0078032000, 0.0067942000, 0.0046960000, 3.570000e-05, -0.010069700, -0.031723800, -0.079833900", \ - "0.0093406000, 0.0083585000, 0.0062297000, 0.0013941000, -0.008746700, -0.030943200, -0.079501900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0163342000, 0.0173000000, 0.0194379000, 0.0240522000, 0.0340880000, 0.0559412000, 0.1036243000", \ - "0.0161484000, 0.0171403000, 0.0192837000, 0.0239464000, 0.0340187000, 0.0558606000, 0.1036068000", \ - "0.0158875000, 0.0168889000, 0.0190350000, 0.0237239000, 0.0338517000, 0.0557685000, 0.1035777000", \ - "0.0156386000, 0.0166060000, 0.0187582000, 0.0234317000, 0.0335878000, 0.0555647000, 0.1034305000", \ - "0.0154754000, 0.0164317000, 0.0185677000, 0.0231794000, 0.0332612000, 0.0552829000, 0.1031534000", \ - "0.0155018000, 0.0164362000, 0.0185378000, 0.0231163000, 0.0331334000, 0.0550176000, 0.1029329000", \ - "0.0152904000, 0.0162352000, 0.0185869000, 0.0232013000, 0.0332576000, 0.0551042000, 0.1027067000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0085242000, 0.0075604000, 0.0054640000, 0.0008895000, -0.009086000, -0.030942100, -0.079034000", \ - "0.0084297000, 0.0074697000, 0.0053662000, 0.0007922000, -0.009177300, -0.031041800, -0.079132600", \ - "0.0083000000, 0.0073416000, 0.0052550000, 0.0006725000, -0.009296500, -0.031160900, -0.079245000", \ - "0.0081564000, 0.0072237000, 0.0051402000, 0.0005627000, -0.009415100, -0.031266700, -0.079337400", \ - "0.0079763000, 0.0070428000, 0.0049794000, 0.0004600000, -0.009452900, -0.031266700, -0.079379100", \ - "0.0081656000, 0.0071998000, 0.0050947000, 0.0005020000, -0.009651300, -0.031374700, -0.079463600", \ - "0.0091304000, 0.0081617000, 0.0060446000, 0.0013410000, -0.008874400, -0.031085600, -0.079382600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0194243000, 0.0203864000, 0.0225166000, 0.0271064000, 0.0371229000, 0.0589779000, 0.1066714000", \ - "0.0193042000, 0.0202501000, 0.0223792000, 0.0270000000, 0.0370481000, 0.0589134000, 0.1066629000", \ - "0.0190828000, 0.0200583000, 0.0221993000, 0.0268496000, 0.0369130000, 0.0587860000, 0.1066203000", \ - "0.0188914000, 0.0198590000, 0.0219994000, 0.0266415000, 0.0367455000, 0.0586869000, 0.1064806000", \ - "0.0187508000, 0.0197148000, 0.0218266000, 0.0264446000, 0.0365235000, 0.0584622000, 0.1063292000", \ - "0.0187386000, 0.0197218000, 0.0217921000, 0.0264000000, 0.0364242000, 0.0583462000, 0.1062074000", \ - "0.0184790000, 0.0195111000, 0.0218466000, 0.0264650000, 0.0365634000, 0.0584099000, 0.1060116000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0055649000, 0.0046170000, 0.0025386000, -0.002028200, -0.012051900, -0.034057400, -0.082306500", \ - "0.0055291000, 0.0045860000, 0.0025129000, -0.002045000, -0.012055800, -0.034058100, -0.082312600", \ - "0.0054206000, 0.0044828000, 0.0024282000, -0.002112300, -0.012107100, -0.034071900, -0.082308600", \ - "0.0051675000, 0.0042584000, 0.0022281000, -0.002259600, -0.012194400, -0.034145900, -0.082339600", \ - "0.0049885000, 0.0040689000, 0.0021147000, -0.002380500, -0.012283300, -0.034201800, -0.082403800", \ - "0.0053787000, 0.0043983000, 0.0023330000, -0.002193600, -0.012401500, -0.034249600, -0.082472700", \ - "0.0064972000, 0.0054989000, 0.0032874000, -0.001437300, -0.011569300, -0.033808400, -0.082348400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0138609000, 0.0148395000, 0.0169566000, 0.0216079000, 0.0316146000, 0.0534813000, 0.1009993000", \ - "0.0136771000, 0.0146708000, 0.0168108000, 0.0214920000, 0.0315464000, 0.0534688000, 0.1011923000", \ - "0.0134021000, 0.0143829000, 0.0165566000, 0.0212463000, 0.0313724000, 0.0533301000, 0.1011274000", \ - "0.0131542000, 0.0141366000, 0.0162765000, 0.0209538000, 0.0310998000, 0.0530797000, 0.1009532000", \ - "0.0129752000, 0.0139296000, 0.0160578000, 0.0206929000, 0.0307931000, 0.0527721000, 0.1006885000", \ - "0.0129373000, 0.0139087000, 0.0159915000, 0.0206723000, 0.0307633000, 0.0525489000, 0.1004645000", \ - "0.0132387000, 0.0142004000, 0.0162492000, 0.0207643000, 0.0307931000, 0.0528515000, 0.1005098000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0059033000, 0.0049514000, 0.0028740000, -0.001697200, -0.011725800, -0.033734600, -0.081984100", \ - "0.0058766000, 0.0049303000, 0.0028595000, -0.001700600, -0.011726100, -0.033726500, -0.081983200", \ - "0.0057787000, 0.0048432000, 0.0027857000, -0.001758500, -0.011756900, -0.033744600, -0.081984000", \ - "0.0055595000, 0.0046325000, 0.0025941000, -0.001889900, -0.011841800, -0.033792500, -0.082006100", \ - "0.0053066000, 0.0043792000, 0.0023404000, -0.002120800, -0.012005800, -0.033869600, -0.082033500", \ - "0.0054002000, 0.0044499000, 0.0023688000, -0.002184800, -0.012258400, -0.034084400, -0.082176500", \ - "0.0061220000, 0.0051375000, 0.0029871000, -0.001666600, -0.011814700, -0.033896800, -0.082197000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0168514000, 0.0178023000, 0.0198914000, 0.0244977000, 0.0345158000, 0.0563651000, 0.1040744000", \ - "0.0167326000, 0.0176876000, 0.0197985000, 0.0244283000, 0.0344588000, 0.0563320000, 0.1040595000", \ - "0.0165310000, 0.0175109000, 0.0196544000, 0.0242877000, 0.0343542000, 0.0562552000, 0.1040096000", \ - "0.0163579000, 0.0173167000, 0.0194604000, 0.0241065000, 0.0341779000, 0.0561003000, 0.1039534000", \ - "0.0162103000, 0.0171681000, 0.0192889000, 0.0239016000, 0.0339730000, 0.0559373000, 0.1037700000", \ - "0.0161765000, 0.0171566000, 0.0192368000, 0.0239141000, 0.0339625000, 0.0557764000, 0.1035928000", \ - "0.0163359000, 0.0172893000, 0.0193474000, 0.0239344000, 0.0339100000, 0.0559685000, 0.1037451000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0007032000, -0.000224300, -0.002293200, -0.006857000, -0.016913300, -0.038973000, -0.087294000", \ - "0.0006112000, -0.000302200, -0.002322900, -0.006847000, -0.016854800, -0.038889700, -0.087192100", \ - "0.0004820000, -0.000418200, -0.002415500, -0.006884400, -0.016843300, -0.038819700, -0.087091900", \ - "0.0002874000, -0.000583200, -0.002592300, -0.007015000, -0.016903500, -0.038823600, -0.087045500", \ - "0.0003274000, -0.000600500, -0.002626400, -0.007216600, -0.017012400, -0.038884900, -0.087059000", \ - "0.0007522000, -0.000198500, -0.002360300, -0.007085200, -0.017063300, -0.039057200, -0.087039800", \ - "0.0021901000, 0.0011690000, -0.001131400, -0.005901800, -0.016145900, -0.038571500, -0.086644600"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010942720, 0.0023948620, 0.0052412600, 0.0114707300, 0.0251041900, 0.0549416200"); - values("0.0163945000, 0.0173652000, 0.0195060000, 0.0241443000, 0.0341982000, 0.0560467000, 0.1037723000", \ - "0.0162161000, 0.0171846000, 0.0193425000, 0.0239975000, 0.0340856000, 0.0560066000, 0.1037796000", \ - "0.0159354000, 0.0169056000, 0.0190945000, 0.0237877000, 0.0339490000, 0.0559034000, 0.1037266000", \ - "0.0157948000, 0.0167902000, 0.0188976000, 0.0235476000, 0.0336523000, 0.0556735000, 0.1035652000", \ - "0.0157387000, 0.0166955000, 0.0187960000, 0.0234160000, 0.0334615000, 0.0554270000, 0.1033537000", \ - "0.0160818000, 0.0170154000, 0.0190652000, 0.0236061000, 0.0335371000, 0.0553045000, 0.1031621000", \ - "0.0182159000, 0.0191199000, 0.0211620000, 0.0256429000, 0.0349215000, 0.0563981000, 0.1034942000"); - } - } - max_capacitance : 0.0549420000; - max_transition : 1.7517130000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0405322000, 0.0446357000, 0.0533557000, 0.0710996000, 0.1073316000, 0.1817625000, 0.3388987000", \ - "0.0450159000, 0.0491156000, 0.0576603000, 0.0753726000, 0.1114944000, 0.1859808000, 0.3430271000", \ - "0.0563960000, 0.0602879000, 0.0682772000, 0.0856512000, 0.1216407000, 0.1959436000, 0.3530827000", \ - "0.0823228000, 0.0866457000, 0.0949428000, 0.1115972000, 0.1463858000, 0.2203664000, 0.3772568000", \ - "0.1189978000, 0.1250556000, 0.1372937000, 0.1612027000, 0.2034134000, 0.2774147000, 0.4338621000", \ - "0.1643436000, 0.1732711000, 0.1914616000, 0.2263837000, 0.2891170000, 0.3923547000, 0.5651396000", \ - "0.2021412000, 0.2152915000, 0.2422610000, 0.2934742000, 0.3877240000, 0.5486463000, 0.8066320000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1914678000, 0.2047903000, 0.2335093000, 0.2961001000, 0.4314362000, 0.7261988000, 1.3700867000", \ - "0.1950901000, 0.2084107000, 0.2377045000, 0.3007089000, 0.4366557000, 0.7313705000, 1.3747892000", \ - "0.2053449000, 0.2188971000, 0.2480320000, 0.3114203000, 0.4480088000, 0.7437670000, 1.3883361000", \ - "0.2300020000, 0.2433149000, 0.2723117000, 0.3354131000, 0.4723416000, 0.7688465000, 1.4140172000", \ - "0.2813623000, 0.2946932000, 0.3236999000, 0.3863714000, 0.5224683000, 0.8191339000, 1.4682882000", \ - "0.3734624000, 0.3891668000, 0.4220098000, 0.4908017000, 0.6292910000, 0.9246860000, 1.5712170000", \ - "0.5188113000, 0.5393483000, 0.5828756000, 0.6682301000, 0.8368145000, 1.1602643000, 1.8085542000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0463343000, 0.0511143000, 0.0609830000, 0.0818947000, 0.1255324000, 0.2203974000, 0.4262263000", \ - "0.0455659000, 0.0502641000, 0.0604626000, 0.0816391000, 0.1254615000, 0.2202686000, 0.4254691000", \ - "0.0449683000, 0.0494058000, 0.0592474000, 0.0804523000, 0.1251100000, 0.2199745000, 0.4260284000", \ - "0.0554490000, 0.0588758000, 0.0664022000, 0.0840600000, 0.1250645000, 0.2194730000, 0.4245412000", \ - "0.0829138000, 0.0875493000, 0.0967394000, 0.1148203000, 0.1476474000, 0.2277811000, 0.4254221000", \ - "0.1301872000, 0.1369969000, 0.1505649000, 0.1761511000, 0.2213802000, 0.3056444000, 0.4620019000", \ - "0.2132902000, 0.2238372000, 0.2447022000, 0.2841990000, 0.3509872000, 0.4656094000, 0.6470610000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1422050000, 0.1591203000, 0.1977276000, 0.2812803000, 0.4630588000, 0.8636559000, 1.7334926000", \ - "0.1415417000, 0.1591029000, 0.1976185000, 0.2817672000, 0.4649574000, 0.8607486000, 1.7280530000", \ - "0.1422604000, 0.1598870000, 0.1976387000, 0.2812113000, 0.4631083000, 0.8606864000, 1.7276666000", \ - "0.1422894000, 0.1593308000, 0.1982028000, 0.2812907000, 0.4634524000, 0.8607124000, 1.7282441000", \ - "0.1451574000, 0.1620533000, 0.1996960000, 0.2824159000, 0.4632212000, 0.8603371000, 1.7308762000", \ - "0.1739296000, 0.1913395000, 0.2270216000, 0.3033485000, 0.4744302000, 0.8616557000, 1.7345939000", \ - "0.2402624000, 0.2583822000, 0.2982785000, 0.3804881000, 0.5528019000, 0.9106880000, 1.7417674000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0452096000, 0.0493329000, 0.0579729000, 0.0757632000, 0.1118864000, 0.1862912000, 0.3433222000", \ - "0.0497579000, 0.0538720000, 0.0624602000, 0.0801899000, 0.1162680000, 0.1906733000, 0.3477403000", \ - "0.0598206000, 0.0638150000, 0.0722152000, 0.0898016000, 0.1258202000, 0.2002856000, 0.3573115000", \ - "0.0823739000, 0.0866726000, 0.0952232000, 0.1125820000, 0.1480916000, 0.2222572000, 0.3794492000", \ - "0.1181656000, 0.1236980000, 0.1348338000, 0.1567364000, 0.1970856000, 0.2735758000, 0.4307648000", \ - "0.1651524000, 0.1731483000, 0.1893852000, 0.2201676000, 0.2768959000, 0.3756583000, 0.5470907000", \ - "0.2076264000, 0.2198062000, 0.2442412000, 0.2909884000, 0.3802206000, 0.5247102000, 0.7604274000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.2145101000, 0.2268642000, 0.2552897000, 0.3159030000, 0.4480993000, 0.7362102000, 1.3655955000", \ - "0.2187110000, 0.2314009000, 0.2594945000, 0.3210122000, 0.4535091000, 0.7418797000, 1.3702526000", \ - "0.2296763000, 0.2430708000, 0.2711611000, 0.3326104000, 0.4656980000, 0.7542651000, 1.3835445000", \ - "0.2560103000, 0.2684649000, 0.2972826000, 0.3581779000, 0.4914958000, 0.7806530000, 1.4104494000", \ - "0.3085430000, 0.3212769000, 0.3490586000, 0.4107924000, 0.5434115000, 0.8325866000, 1.4626936000", \ - "0.4069065000, 0.4221448000, 0.4529290000, 0.5183373000, 0.6524962000, 0.9411644000, 1.5716010000", \ - "0.5675784000, 0.5863302000, 0.6273642000, 0.7080609000, 0.8687145000, 1.1814471000, 1.8145073000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0460295000, 0.0507337000, 0.0608318000, 0.0817498000, 0.1258579000, 0.2201151000, 0.4239505000", \ - "0.0456267000, 0.0503809000, 0.0604659000, 0.0815167000, 0.1253549000, 0.2198139000, 0.4249287000", \ - "0.0451661000, 0.0495730000, 0.0595284000, 0.0807897000, 0.1249526000, 0.2199769000, 0.4248458000", \ - "0.0517813000, 0.0554992000, 0.0636767000, 0.0826755000, 0.1250512000, 0.2193487000, 0.4258918000", \ - "0.0721259000, 0.0762513000, 0.0853099000, 0.1026453000, 0.1399773000, 0.2251751000, 0.4244241000", \ - "0.1128774000, 0.1184787000, 0.1299984000, 0.1533291000, 0.1933224000, 0.2755876000, 0.4489653000", \ - "0.1861422000, 0.1949345000, 0.2111064000, 0.2438398000, 0.2993923000, 0.3988212000, 0.5780724000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1603487000, 0.1777334000, 0.2158647000, 0.2972345000, 0.4769690000, 0.8678109000, 1.7158006000", \ - "0.1606524000, 0.1777322000, 0.2153049000, 0.2973620000, 0.4763162000, 0.8677137000, 1.7157532000", \ - "0.1604487000, 0.1779841000, 0.2154710000, 0.2974652000, 0.4767703000, 0.8645806000, 1.7140481000", \ - "0.1602676000, 0.1777717000, 0.2154366000, 0.2973017000, 0.4756668000, 0.8648967000, 1.7134285000", \ - "0.1623354000, 0.1792051000, 0.2159328000, 0.2972267000, 0.4759991000, 0.8646923000, 1.7129418000", \ - "0.1888315000, 0.2061496000, 0.2408504000, 0.3159468000, 0.4853445000, 0.8655134000, 1.7171479000", \ - "0.2542387000, 0.2725342000, 0.3108361000, 0.3915314000, 0.5595723000, 0.9132675000, 1.7264140000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0381991000, 0.0416507000, 0.0489139000, 0.0642222000, 0.0967557000, 0.1667321000, 0.3183715000", \ - "0.0428019000, 0.0461302000, 0.0533038000, 0.0685391000, 0.1012186000, 0.1710488000, 0.3227510000", \ - "0.0531391000, 0.0565307000, 0.0637572000, 0.0788684000, 0.1115142000, 0.1815112000, 0.3332241000", \ - "0.0747059000, 0.0789365000, 0.0874483000, 0.1036700000, 0.1360889000, 0.2056404000, 0.3574544000", \ - "0.1021196000, 0.1086540000, 0.1207189000, 0.1453013000, 0.1887533000, 0.2623496000, 0.4130091000", \ - "0.1291249000, 0.1388355000, 0.1583617000, 0.1952166000, 0.2630314000, 0.3716212000, 0.5459692000", \ - "0.1390187000, 0.1539023000, 0.1832705000, 0.2411072000, 0.3434326000, 0.5114821000, 0.7759343000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1717335000, 0.1853484000, 0.2142261000, 0.2769045000, 0.4126390000, 0.7079527000, 1.3546613000", \ - "0.1746432000, 0.1881690000, 0.2174722000, 0.2805417000, 0.4168272000, 0.7123109000, 1.3568514000", \ - "0.1835521000, 0.1972468000, 0.2265376000, 0.2900066000, 0.4269417000, 0.7234573000, 1.3707264000", \ - "0.2078179000, 0.2210926000, 0.2503871000, 0.3135123000, 0.4506231000, 0.7478791000, 1.3942439000", \ - "0.2622685000, 0.2756221000, 0.3049208000, 0.3675841000, 0.5041774000, 0.8012911000, 1.4483615000", \ - "0.3632671000, 0.3806382000, 0.4163324000, 0.4899348000, 0.6309135000, 0.9272138000, 1.5752138000", \ - "0.5267428000, 0.5527520000, 0.6045384000, 0.7034920000, 0.8862485000, 1.2231872000, 1.8710888000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0430193000, 0.0468704000, 0.0554138000, 0.0743177000, 0.1161310000, 0.2083969000, 0.4106188000", \ - "0.0428073000, 0.0467240000, 0.0553228000, 0.0743462000, 0.1163280000, 0.2083876000, 0.4103272000", \ - "0.0432310000, 0.0469383000, 0.0551121000, 0.0740633000, 0.1160650000, 0.2089453000, 0.4106205000", \ - "0.0553881000, 0.0582594000, 0.0648315000, 0.0803038000, 0.1181571000, 0.2083971000, 0.4109857000", \ - "0.0843166000, 0.0884869000, 0.0973537000, 0.1142001000, 0.1464640000, 0.2210666000, 0.4118831000", \ - "0.1379355000, 0.1440344000, 0.1562825000, 0.1811261000, 0.2231006000, 0.2991808000, 0.4547447000", \ - "0.2304199000, 0.2398960000, 0.2590274000, 0.2938337000, 0.3586540000, 0.4648983000, 0.6445091000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1422962000, 0.1607947000, 0.1988926000, 0.2831880000, 0.4682312000, 0.8691041000, 1.7451512000", \ - "0.1424573000, 0.1607222000, 0.1988155000, 0.2831596000, 0.4682342000, 0.8675575000, 1.7420191000", \ - "0.1429847000, 0.1601532000, 0.1992983000, 0.2831994000, 0.4668044000, 0.8683458000, 1.7492282000", \ - "0.1431721000, 0.1601544000, 0.1997144000, 0.2832174000, 0.4667760000, 0.8676067000, 1.7419215000", \ - "0.1505859000, 0.1673745000, 0.2031827000, 0.2842479000, 0.4666026000, 0.8670005000, 1.7423267000", \ - "0.1939611000, 0.2105076000, 0.2454723000, 0.3178138000, 0.4828308000, 0.8679969000, 1.7485812000", \ - "0.2913136000, 0.3105876000, 0.3518366000, 0.4305105000, 0.5905774000, 0.9351960000, 1.7517132000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0424840000, 0.0459537000, 0.0531273000, 0.0684856000, 0.1009998000, 0.1709057000, 0.3226003000", \ - "0.0469413000, 0.0504645000, 0.0576092000, 0.0729752000, 0.1055709000, 0.1754698000, 0.3271231000", \ - "0.0563554000, 0.0596977000, 0.0669831000, 0.0823871000, 0.1150433000, 0.1850202000, 0.3367448000", \ - "0.0752029000, 0.0790064000, 0.0871025000, 0.1036131000, 0.1366295000, 0.2067714000, 0.3588072000", \ - "0.1017129000, 0.1074145000, 0.1188650000, 0.1408506000, 0.1811412000, 0.2559068000, 0.4086621000", \ - "0.1293870000, 0.1382161000, 0.1560575000, 0.1898684000, 0.2494585000, 0.3493897000, 0.5211467000", \ - "0.1365029000, 0.1503550000, 0.1788409000, 0.2324596000, 0.3261860000, 0.4794182000, 0.7190062000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1948983000, 0.2078162000, 0.2352615000, 0.2965675000, 0.4287369000, 0.7163980000, 1.3449418000", \ - "0.1985911000, 0.2116685000, 0.2394569000, 0.3008156000, 0.4332729000, 0.7211626000, 1.3500749000", \ - "0.2088395000, 0.2222164000, 0.2505566000, 0.3114047000, 0.4444642000, 0.7331214000, 1.3623558000", \ - "0.2358033000, 0.2484161000, 0.2768293000, 0.3378162000, 0.4710920000, 0.7601551000, 1.3898390000", \ - "0.2955844000, 0.3080169000, 0.3361587000, 0.3976758000, 0.5304159000, 0.8195988000, 1.4496233000", \ - "0.4177551000, 0.4339975000, 0.4663290000, 0.5346859000, 0.6688974000, 0.9578697000, 1.5879899000", \ - "0.6209182000, 0.6435930000, 0.6913161000, 0.7847312000, 0.9571068000, 1.2794105000, 1.9110418000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0429088000, 0.0467838000, 0.0553887000, 0.0742728000, 0.1162517000, 0.2083842000, 0.4104555000", \ - "0.0428364000, 0.0467166000, 0.0553492000, 0.0743451000, 0.1162036000, 0.2081981000, 0.4110277000", \ - "0.0429757000, 0.0468725000, 0.0552401000, 0.0741349000, 0.1160735000, 0.2083755000, 0.4103967000", \ - "0.0504276000, 0.0536613000, 0.0608934000, 0.0778926000, 0.1175832000, 0.2084259000, 0.4106208000", \ - "0.0725038000, 0.0761661000, 0.0840406000, 0.1003399000, 0.1349546000, 0.2168453000, 0.4112216000", \ - "0.1175230000, 0.1221214000, 0.1319267000, 0.1523935000, 0.1920081000, 0.2703812000, 0.4384750000", \ - "0.1996819000, 0.2066901000, 0.2216774000, 0.2508567000, 0.3036333000, 0.3990009000, 0.5718575000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1606992000, 0.1774621000, 0.2152812000, 0.2972684000, 0.4774929000, 0.8646907000, 1.7136201000", \ - "0.1607405000, 0.1774980000, 0.2154390000, 0.2973206000, 0.4774661000, 0.8645285000, 1.7135224000", \ - "0.1604528000, 0.1780492000, 0.2152715000, 0.2973628000, 0.4755177000, 0.8648062000, 1.7122930000", \ - "0.1603097000, 0.1777221000, 0.2158281000, 0.2975043000, 0.4768742000, 0.8647628000, 1.7155564000", \ - "0.1645083000, 0.1813789000, 0.2170884000, 0.2975246000, 0.4757559000, 0.8650101000, 1.7131000000", \ - "0.2061421000, 0.2226566000, 0.2545007000, 0.3259186000, 0.4882079000, 0.8643689000, 1.7146587000", \ - "0.3074427000, 0.3267135000, 0.3654298000, 0.4429350000, 0.5946273000, 0.9249697000, 1.7214919000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0207836000, 0.0229062000, 0.0272983000, 0.0368995000, 0.0576886000, 0.1029333000, 0.2018273000", \ - "0.0255602000, 0.0276764000, 0.0321647000, 0.0418604000, 0.0625995000, 0.1079634000, 0.2068356000", \ - "0.0356810000, 0.0383448000, 0.0435399000, 0.0533128000, 0.0738969000, 0.1193209000, 0.2182169000", \ - "0.0488764000, 0.0531782000, 0.0614634000, 0.0760354000, 0.1009995000, 0.1460899000, 0.2439489000", \ - "0.0628854000, 0.0695555000, 0.0823710000, 0.1057735000, 0.1438997000, 0.2049830000, 0.3055503000", \ - "0.0693377000, 0.0795205000, 0.1001706000, 0.1370225000, 0.1986452000, 0.2942757000, 0.4368996000", \ - "0.0461656000, 0.0628146000, 0.0944989000, 0.1526924000, 0.2495250000, 0.4005003000, 0.6246833000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1431426000, 0.1559804000, 0.1847072000, 0.2453940000, 0.3780965000, 0.6663907000, 1.2953144000", \ - "0.1458977000, 0.1589253000, 0.1874003000, 0.2488106000, 0.3816398000, 0.6703239000, 1.2995349000", \ - "0.1537024000, 0.1661995000, 0.1953651000, 0.2573023000, 0.3905583000, 0.6808227000, 1.3098220000", \ - "0.1771168000, 0.1905185000, 0.2185668000, 0.2797751000, 0.4136592000, 0.7035885000, 1.3332926000", \ - "0.2402270000, 0.2522580000, 0.2794545000, 0.3398508000, 0.4724798000, 0.7613926000, 1.3925117000", \ - "0.3622619000, 0.3793079000, 0.4138631000, 0.4820173000, 0.6129701000, 0.8997286000, 1.5289353000", \ - "0.5537195000, 0.5784270000, 0.6303364000, 0.7292437000, 0.9133698000, 1.2330199000, 1.8517381000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.0248953000, 0.0275702000, 0.0334024000, 0.0460932000, 0.0737519000, 0.1345397000, 0.2667369000", \ - "0.0251202000, 0.0276345000, 0.0334163000, 0.0461109000, 0.0737544000, 0.1339887000, 0.2665487000", \ - "0.0304035000, 0.0322756000, 0.0367972000, 0.0476973000, 0.0738047000, 0.1341251000, 0.2663664000", \ - "0.0479671000, 0.0498030000, 0.0536950000, 0.0619167000, 0.0824622000, 0.1363571000, 0.2667172000", \ - "0.0798779000, 0.0822612000, 0.0877686000, 0.0985215000, 0.1205652000, 0.1626561000, 0.2736495000", \ - "0.1372182000, 0.1411022000, 0.1482988000, 0.1641733000, 0.1948917000, 0.2495273000, 0.3453942000", \ - "0.2397650000, 0.2447466000, 0.2566661000, 0.2797289000, 0.3263362000, 0.4070597000, 0.5418567000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010942700, 0.0023948600, 0.0052412600, 0.0114707000, 0.0251042000, 0.0549416000"); - values("0.1599598000, 0.1774011000, 0.2151986000, 0.2974990000, 0.4756857000, 0.8646593000, 1.7130322000", \ - "0.1596464000, 0.1770815000, 0.2150386000, 0.2978240000, 0.4758938000, 0.8645262000, 1.7153652000", \ - "0.1591540000, 0.1768591000, 0.2150062000, 0.2975752000, 0.4756091000, 0.8692780000, 1.7161425000", \ - "0.1562680000, 0.1747579000, 0.2138295000, 0.2970497000, 0.4757845000, 0.8649312000, 1.7127521000", \ - "0.1676519000, 0.1832514000, 0.2177635000, 0.2961212000, 0.4751693000, 0.8648357000, 1.7198318000", \ - "0.2234446000, 0.2405093000, 0.2761452000, 0.3429490000, 0.4958869000, 0.8654564000, 1.7200583000", \ - "0.3221290000, 0.3446325000, 0.3914169000, 0.4811877000, 0.6428726000, 0.9587069000, 1.7267741000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221oi_2") { - leakage_power () { - value : 0.0077009000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0033766000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0077002000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0044064000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0077014000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0051737000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002993000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0027224000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0020124000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0030938000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0028134000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002990000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0027223000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0016856000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0027564000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0077024000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0024886000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002990000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0027223000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0002848000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0024238000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0002850000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0023323000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0002852000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0023923000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0001514000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0002804000; - when : "A1&A2&B1&B2&!C1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__a221oi"; - cell_leakage_power : 0.0035819810; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087847000, 0.0087828000, 0.0087784000, 0.0087825000, 0.0087919000, 0.0088135000, 0.0088635000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006598600, -0.006603700, -0.006615400, -0.006601400, -0.006569000, -0.006494200, -0.006322000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044790000; - } - pin ("A2") { - capacitance : 0.0047660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082159000, 0.0082117000, 0.0082021000, 0.0082038000, 0.0082079000, 0.0082173000, 0.0082389000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008179600, -0.008180700, -0.008183100, -0.008182800, -0.008182100, -0.008180400, -0.008176400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050000000; - } - pin ("B1") { - capacitance : 0.0042760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088508000, 0.0088559000, 0.0088677000, 0.0088684000, 0.0088701000, 0.0088740000, 0.0088829000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006770600, -0.006768000, -0.006762200, -0.006748900, -0.006718100, -0.006647400, -0.006484200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045270000; - } - pin ("B2") { - capacitance : 0.0047580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084710000, 0.0084635000, 0.0084463000, 0.0084443000, 0.0084396000, 0.0084288000, 0.0084039000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008430700, -0.008430400, -0.008429700, -0.008427300, -0.008421500, -0.008408300, -0.008378000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050710000; - } - pin ("C1") { - capacitance : 0.0042930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050389000, 0.0050264000, 0.0049976000, 0.0050253000, 0.0050891000, 0.0052361000, 0.0055750000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003535600, -0.003533600, -0.003528900, -0.003531100, -0.003536000, -0.003547300, -0.003573500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046470000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A1&!B2&!C1) | (!A2&!B1&!C1) | (!A2&!B2&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0151905000, 0.0140684000, 0.0113454000, 0.0047945000, -0.010841200, -0.048279000, -0.138617400", \ - "0.0150621000, 0.0139189000, 0.0112149000, 0.0046680000, -0.010951600, -0.048417500, -0.138786500", \ - "0.0148467000, 0.0137036000, 0.0110065000, 0.0044957000, -0.011155900, -0.048610900, -0.138944000", \ - "0.0144400000, 0.0133654000, 0.0106964000, 0.0042908000, -0.011400800, -0.048832300, -0.139202300", \ - "0.0142391000, 0.0131152000, 0.0104484000, 0.0040634000, -0.011529300, -0.048842800, -0.139266700", \ - "0.0148820000, 0.0137316000, 0.0109771000, 0.0043452000, -0.011547500, -0.049046900, -0.139416700", \ - "0.0172600000, 0.0160917000, 0.0132889000, 0.0067039000, -0.009875300, -0.048089500, -0.139096300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0277148000, 0.0288808000, 0.0316652000, 0.0382762000, 0.0539412000, 0.0914129000, 0.1811723000", \ - "0.0273987000, 0.0285971000, 0.0313684000, 0.0380217000, 0.0538332000, 0.0913568000, 0.1811527000", \ - "0.0269371000, 0.0281436000, 0.0309377000, 0.0376012000, 0.0535282000, 0.0912470000, 0.1808908000", \ - "0.0265994000, 0.0277440000, 0.0304806000, 0.0371546000, 0.0530491000, 0.0908001000, 0.1808488000", \ - "0.0262868000, 0.0274204000, 0.0301537000, 0.0367687000, 0.0525309000, 0.0902248000, 0.1804915000", \ - "0.0262455000, 0.0273920000, 0.0300897000, 0.0366093000, 0.0523337000, 0.0899097000, 0.1799979000", \ - "0.0256045000, 0.0268858000, 0.0299159000, 0.0365591000, 0.0523388000, 0.0897681000, 0.1794972000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0167206000, 0.0155922000, 0.0128762000, 0.0063356000, -0.009309200, -0.046746100, -0.137131400", \ - "0.0165571000, 0.0154290000, 0.0127162000, 0.0061811000, -0.009467900, -0.046904500, -0.137276700", \ - "0.0163329000, 0.0151915000, 0.0124547000, 0.0059395000, -0.009707800, -0.047139600, -0.137490500", \ - "0.0159968000, 0.0148877000, 0.0122154000, 0.0057647000, -0.009992400, -0.047359200, -0.137735400", \ - "0.0156159000, 0.0145202000, 0.0118682000, 0.0054474000, -0.010031900, -0.047333100, -0.137775200", \ - "0.0159707000, 0.0148602000, 0.0121012000, 0.0054630000, -0.010296900, -0.047620200, -0.137926500", \ - "0.0176226000, 0.0164549000, 0.0136787000, 0.0070419000, -0.008814100, -0.046857000, -0.137914900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0344215000, 0.0355647000, 0.0382920000, 0.0448538000, 0.0605255000, 0.0979892000, 0.1878082000", \ - "0.0341997000, 0.0353761000, 0.0380901000, 0.0447052000, 0.0604007000, 0.0978534000, 0.1876668000", \ - "0.0338544000, 0.0350882000, 0.0378152000, 0.0444157000, 0.0601751000, 0.0978066000, 0.1875729000", \ - "0.0336280000, 0.0347425000, 0.0375032000, 0.0441237000, 0.0598770000, 0.0975449000, 0.1875791000", \ - "0.0334156000, 0.0345172000, 0.0372085000, 0.0438083000, 0.0595389000, 0.0971928000, 0.1872069000", \ - "0.0332790000, 0.0344006000, 0.0372275000, 0.0436836000, 0.0594107000, 0.0969917000, 0.1870396000", \ - "0.0327114000, 0.0339744000, 0.0369608000, 0.0436307000, 0.0595525000, 0.0970167000, 0.1867199000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0086408000, 0.0075242000, 0.0048433000, -0.001644900, -0.017266000, -0.054919200, -0.145658800", \ - "0.0085528000, 0.0074381000, 0.0047615000, -0.001697900, -0.017276900, -0.054952700, -0.145665600", \ - "0.0083673000, 0.0072740000, 0.0046180000, -0.001792300, -0.017343300, -0.054980400, -0.145652900", \ - "0.0079489000, 0.0068599000, 0.0042701000, -0.002119300, -0.017543100, -0.055079600, -0.145706700", \ - "0.0077909000, 0.0066791000, 0.0040088000, -0.002394900, -0.017751800, -0.055213900, -0.145777200", \ - "0.0083110000, 0.0071836000, 0.0044724000, -0.001993700, -0.017685700, -0.055444900, -0.145989500", \ - "0.0102031000, 0.0090647000, 0.0062467000, -0.000548500, -0.016468800, -0.054188700, -0.145677700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0223921000, 0.0235582000, 0.0263681000, 0.0329947000, 0.0487050000, 0.0862864000, 0.1759583000", \ - "0.0220385000, 0.0232411000, 0.0260720000, 0.0327392000, 0.0485770000, 0.0861111000, 0.1760278000", \ - "0.0215434000, 0.0227487000, 0.0255530000, 0.0322526000, 0.0481619000, 0.0859219000, 0.1757920000", \ - "0.0211810000, 0.0223479000, 0.0251214000, 0.0317730000, 0.0476467000, 0.0854992000, 0.1755090000", \ - "0.0209149000, 0.0220680000, 0.0247904000, 0.0313510000, 0.0471827000, 0.0848767000, 0.1751147000", \ - "0.0208624000, 0.0220059000, 0.0247164000, 0.0312655000, 0.0470962000, 0.0845405000, 0.1745646000", \ - "0.0212753000, 0.0223840000, 0.0250373000, 0.0315413000, 0.0471419000, 0.0848994000, 0.1746524000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0100328000, 0.0089102000, 0.0062229000, -0.000256500, -0.015883400, -0.053552900, -0.144319200", \ - "0.0099437000, 0.0088350000, 0.0061603000, -0.000304000, -0.015909200, -0.053576700, -0.144319400", \ - "0.0097500000, 0.0086648000, 0.0059915000, -0.000419000, -0.015974200, -0.053601700, -0.144305900", \ - "0.0092646000, 0.0081959000, 0.0055957000, -0.000737700, -0.016168300, -0.053690600, -0.144343300", \ - "0.0090296000, 0.0078877000, 0.0051478000, -0.001185500, -0.016502900, -0.053856900, -0.144384800", \ - "0.0091830000, 0.0080845000, 0.0053943000, -0.001092700, -0.016684900, -0.054301300, -0.144670800", \ - "0.0108542000, 0.0096798000, 0.0068718000, 0.0001946000, -0.015757400, -0.053696000, -0.144622800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0289401000, 0.0301050000, 0.0328005000, 0.0393542000, 0.0550304000, 0.0925053000, 0.1822989000", \ - "0.0286282000, 0.0297889000, 0.0325665000, 0.0391616000, 0.0549174000, 0.0924386000, 0.1822668000", \ - "0.0283347000, 0.0294426000, 0.0322144000, 0.0388560000, 0.0546815000, 0.0922755000, 0.1822567000", \ - "0.0279851000, 0.0291190000, 0.0318980000, 0.0385227000, 0.0543314000, 0.0919893000, 0.1819835000", \ - "0.0277188000, 0.0288796000, 0.0316688000, 0.0382244000, 0.0539747000, 0.0916034000, 0.1816545000", \ - "0.0277231000, 0.0288338000, 0.0315757000, 0.0381669000, 0.0540278000, 0.0914389000, 0.1814558000", \ - "0.0282087000, 0.0293056000, 0.0319552000, 0.0384217000, 0.0541416000, 0.0918736000, 0.1818811000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("-0.000282600, -0.001339100, -0.003946600, -0.010379500, -0.026035000, -0.063815900, -0.154700700", \ - "-0.000571200, -0.001598000, -0.004116100, -0.010430900, -0.025974300, -0.063652200, -0.154493300", \ - "-0.000898700, -0.001903900, -0.004383700, -0.010608000, -0.025995200, -0.063559600, -0.154319100", \ - "-0.001133500, -0.002167900, -0.004769500, -0.010922300, -0.026134900, -0.063578700, -0.154247700", \ - "-0.000718300, -0.001827700, -0.004463300, -0.010804600, -0.026403800, -0.063728200, -0.154233400", \ - "0.0002787000, -0.000897500, -0.003625500, -0.010276900, -0.025985000, -0.063620600, -0.154341600", \ - "0.0040746000, 0.0027877000, -0.000263500, -0.007368600, -0.023663900, -0.061396600, -0.152870900"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012012290, 0.0028859040, 0.0069332650, 0.0166568800, 0.0400174800, 0.0961403400"); - values("0.0266918000, 0.0278436000, 0.0306247000, 0.0373125000, 0.0531873000, 0.0907567000, 0.1806763000", \ - "0.0264109000, 0.0275493000, 0.0302900000, 0.0369704000, 0.0529161000, 0.0906057000, 0.1805513000", \ - "0.0260138000, 0.0271671000, 0.0298939000, 0.0365811000, 0.0525514000, 0.0903773000, 0.1804246000", \ - "0.0257502000, 0.0268677000, 0.0294688000, 0.0361478000, 0.0520484000, 0.0898890000, 0.1800201000", \ - "0.0257137000, 0.0268443000, 0.0295592000, 0.0360990000, 0.0518030000, 0.0894178000, 0.1796953000", \ - "0.0269257000, 0.0280477000, 0.0306228000, 0.0369383000, 0.0524756000, 0.0895825000, 0.1794968000", \ - "0.0301772000, 0.0312318000, 0.0338085000, 0.0399854000, 0.0552431000, 0.0916840000, 0.1805106000"); - } - } - max_capacitance : 0.0961400000; - max_transition : 1.7379920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0270524000, 0.0296018000, 0.0354161000, 0.0484605000, 0.0769857000, 0.1391792000, 0.2797094000", \ - "0.0318463000, 0.0342541000, 0.0399454000, 0.0528040000, 0.0811191000, 0.1432759000, 0.2840322000", \ - "0.0443182000, 0.0464372000, 0.0515017000, 0.0636635000, 0.0913777000, 0.1532756000, 0.2937148000", \ - "0.0659973000, 0.0689771000, 0.0755414000, 0.0894854000, 0.1159243000, 0.1767386000, 0.3169956000", \ - "0.0944599000, 0.0986356000, 0.1079287000, 0.1273613000, 0.1650040000, 0.2327752000, 0.3718114000", \ - "0.1221434000, 0.1281145000, 0.1415308000, 0.1699178000, 0.2256576000, 0.3266946000, 0.4977112000", \ - "0.1257085000, 0.1344995000, 0.1543478000, 0.1968457000, 0.2812719000, 0.4335264000, 0.6919209000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1833923000, 0.1920924000, 0.2137536000, 0.2638469000, 0.3820795000, 0.6635916000, 1.3383615000", \ - "0.1871651000, 0.1962708000, 0.2176200000, 0.2682486000, 0.3872429000, 0.6693960000, 1.3438448000", \ - "0.1982327000, 0.2075819000, 0.2287498000, 0.2797104000, 0.3993742000, 0.6825115000, 1.3619681000", \ - "0.2265946000, 0.2354061000, 0.2569900000, 0.3071044000, 0.4268599000, 0.7105969000, 1.3871608000", \ - "0.2863219000, 0.2951419000, 0.3162109000, 0.3662917000, 0.4849516000, 0.7687798000, 1.4457758000", \ - "0.3952400000, 0.4059281000, 0.4301326000, 0.4860305000, 0.6082992000, 0.8907645000, 1.5675400000", \ - "0.5784931000, 0.5924027000, 0.6244887000, 0.6958734000, 0.8458219000, 1.1587178000, 1.8379092000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0341626000, 0.0372129000, 0.0440849000, 0.0596716000, 0.0946554000, 0.1735912000, 0.3601950000", \ - "0.0330202000, 0.0359608000, 0.0430965000, 0.0590183000, 0.0941305000, 0.1733397000, 0.3599332000", \ - "0.0350179000, 0.0375280000, 0.0435430000, 0.0583085000, 0.0930269000, 0.1729538000, 0.3597262000", \ - "0.0475711000, 0.0501039000, 0.0557838000, 0.0674100000, 0.0965464000, 0.1722148000, 0.3599971000", \ - "0.0714708000, 0.0746601000, 0.0820837000, 0.0976310000, 0.1267535000, 0.1893213000, 0.3612308000", \ - "0.1141756000, 0.1191751000, 0.1298096000, 0.1508768000, 0.1914789000, 0.2674700000, 0.4121675000", \ - "0.1878604000, 0.1955216000, 0.2120655000, 0.2451483000, 0.3052495000, 0.4139008000, 0.5988040000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1191899000, 0.1312257000, 0.1588598000, 0.2262361000, 0.3851073000, 0.7667921000, 1.6830662000", \ - "0.1197788000, 0.1310053000, 0.1586850000, 0.2257558000, 0.3854559000, 0.7662379000, 1.6802076000", \ - "0.1198851000, 0.1315110000, 0.1593814000, 0.2257489000, 0.3854343000, 0.7670654000, 1.6835671000", \ - "0.1194568000, 0.1310939000, 0.1595900000, 0.2258249000, 0.3860529000, 0.7669366000, 1.6820829000", \ - "0.1217328000, 0.1329151000, 0.1605441000, 0.2268596000, 0.3855109000, 0.7697522000, 1.6861533000", \ - "0.1475355000, 0.1589981000, 0.1850709000, 0.2467313000, 0.3954319000, 0.7675294000, 1.6846634000", \ - "0.2107023000, 0.2228613000, 0.2506663000, 0.3176504000, 0.4676390000, 0.8130273000, 1.6878791000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0325134000, 0.0350848000, 0.0408567000, 0.0538821000, 0.0823881000, 0.1445809000, 0.2851654000", \ - "0.0371950000, 0.0397086000, 0.0454743000, 0.0583992000, 0.0867511000, 0.1489512000, 0.2894529000", \ - "0.0478445000, 0.0501720000, 0.0556227000, 0.0682105000, 0.0963166000, 0.1584065000, 0.2989243000", \ - "0.0681149000, 0.0709521000, 0.0773089000, 0.0909368000, 0.1183923000, 0.1802867000, 0.3206480000", \ - "0.0983072000, 0.1020897000, 0.1103603000, 0.1280166000, 0.1635410000, 0.2306865000, 0.3715714000", \ - "0.1330912000, 0.1386476000, 0.1508707000, 0.1767957000, 0.2262961000, 0.3195371000, 0.4834808000", \ - "0.1509740000, 0.1593560000, 0.1781384000, 0.2175322000, 0.2932420000, 0.4344295000, 0.6687095000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.2074574000, 0.2156958000, 0.2348422000, 0.2822706000, 0.3943025000, 0.6607288000, 1.2990180000", \ - "0.2108612000, 0.2199006000, 0.2402313000, 0.2874853000, 0.3995776000, 0.6661560000, 1.3080379000", \ - "0.2233663000, 0.2320198000, 0.2525137000, 0.2999319000, 0.4123517000, 0.6793932000, 1.3203068000", \ - "0.2525001000, 0.2613449000, 0.2813153000, 0.3287870000, 0.4413004000, 0.7090007000, 1.3486389000", \ - "0.3119712000, 0.3199709000, 0.3398013000, 0.3869481000, 0.4998419000, 0.7675796000, 1.4074614000", \ - "0.4243437000, 0.4337112000, 0.4555940000, 0.5070233000, 0.6219876000, 0.8892744000, 1.5290232000", \ - "0.6109334000, 0.6231432000, 0.6514203000, 0.7173084000, 0.8578857000, 1.1533189000, 1.7974048000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0341374000, 0.0370590000, 0.0439936000, 0.0595834000, 0.0946078000, 0.1736089000, 0.3603120000", \ - "0.0335298000, 0.0365279000, 0.0435625000, 0.0593375000, 0.0941915000, 0.1734797000, 0.3600343000", \ - "0.0343642000, 0.0370389000, 0.0434897000, 0.0587180000, 0.0936767000, 0.1733169000, 0.3600495000", \ - "0.0435332000, 0.0459473000, 0.0513616000, 0.0639739000, 0.0953244000, 0.1723752000, 0.3603311000", \ - "0.0639436000, 0.0666916000, 0.0732208000, 0.0872464000, 0.1162009000, 0.1833522000, 0.3609999000", \ - "0.1020315000, 0.1058327000, 0.1140539000, 0.1317870000, 0.1691821000, 0.2389123000, 0.3936158000", \ - "0.1701173000, 0.1755629000, 0.1878537000, 0.2139247000, 0.2641565000, 0.3560677000, 0.5296047000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1374218000, 0.1485617000, 0.1752984000, 0.2388983000, 0.3901846000, 0.7536400000, 1.6193803000", \ - "0.1377995000, 0.1486350000, 0.1751947000, 0.2395722000, 0.3908834000, 0.7522684000, 1.6237113000", \ - "0.1376700000, 0.1486257000, 0.1752156000, 0.2395248000, 0.3902701000, 0.7520179000, 1.6231045000", \ - "0.1374451000, 0.1489944000, 0.1752060000, 0.2387667000, 0.3901544000, 0.7544647000, 1.6241745000", \ - "0.1391114000, 0.1498393000, 0.1762572000, 0.2395436000, 0.3905954000, 0.7550520000, 1.6206230000", \ - "0.1631779000, 0.1738510000, 0.2000287000, 0.2577182000, 0.4004411000, 0.7527696000, 1.6222250000", \ - "0.2267711000, 0.2389904000, 0.2665446000, 0.3301726000, 0.4738593000, 0.8013208000, 1.6275353000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0278692000, 0.0298899000, 0.0346080000, 0.0453634000, 0.0697757000, 0.1262949000, 0.2600205000", \ - "0.0320939000, 0.0340879000, 0.0388839000, 0.0495968000, 0.0739854000, 0.1305294000, 0.2642070000", \ - "0.0426535000, 0.0446662000, 0.0490827000, 0.0596767000, 0.0841121000, 0.1404688000, 0.2742338000", \ - "0.0590208000, 0.0619640000, 0.0686461000, 0.0818840000, 0.1077134000, 0.1641203000, 0.2975070000", \ - "0.0757532000, 0.0802045000, 0.0900882000, 0.1107027000, 0.1495559000, 0.2183443000, 0.3523936000", \ - "0.0836244000, 0.0903210000, 0.1052723000, 0.1363164000, 0.1969111000, 0.3018960000, 0.4764487000", \ - "0.0532903000, 0.0634765000, 0.0875652000, 0.1347083000, 0.2275523000, 0.3887519000, 0.6560987000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1589933000, 0.1681005000, 0.1905550000, 0.2423129000, 0.3646050000, 0.6551641000, 1.3505493000", \ - "0.1615312000, 0.1712907000, 0.1934542000, 0.2459529000, 0.3686224000, 0.6597762000, 1.3557744000", \ - "0.1708199000, 0.1804674000, 0.2025069000, 0.2550079000, 0.3787321000, 0.6708923000, 1.3676091000", \ - "0.1977697000, 0.2073095000, 0.2290213000, 0.2810911000, 0.4043293000, 0.6970622000, 1.3947430000", \ - "0.2590662000, 0.2681575000, 0.2899901000, 0.3416597000, 0.4643431000, 0.7565359000, 1.4547535000", \ - "0.3722757000, 0.3844904000, 0.4131019000, 0.4744025000, 0.6053510000, 0.8970613000, 1.5960674000", \ - "0.5600221000, 0.5790034000, 0.6212181000, 0.7107867000, 0.8855253000, 1.2240496000, 1.9226729000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0332974000, 0.0354015000, 0.0405568000, 0.0531290000, 0.0838805000, 0.1587067000, 0.3389596000", \ - "0.0326493000, 0.0348610000, 0.0402111000, 0.0529729000, 0.0838951000, 0.1586480000, 0.3391585000", \ - "0.0347676000, 0.0366440000, 0.0413380000, 0.0531901000, 0.0837200000, 0.1590408000, 0.3392895000", \ - "0.0474765000, 0.0494894000, 0.0541054000, 0.0640532000, 0.0894009000, 0.1588664000, 0.3391067000", \ - "0.0740865000, 0.0766653000, 0.0824985000, 0.0956596000, 0.1228672000, 0.1813413000, 0.3422723000", \ - "0.1221041000, 0.1260487000, 0.1349531000, 0.1541337000, 0.1911804000, 0.2623611000, 0.4009915000", \ - "0.2073784000, 0.2140981000, 0.2272742000, 0.2556776000, 0.3125299000, 0.4157120000, 0.5912953000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1235381000, 0.1359487000, 0.1643156000, 0.2333690000, 0.3987791000, 0.7931136000, 1.7373339000", \ - "0.1240262000, 0.1361096000, 0.1642714000, 0.2339439000, 0.3982454000, 0.7914945000, 1.7375714000", \ - "0.1241412000, 0.1361016000, 0.1640820000, 0.2331062000, 0.3972652000, 0.7903810000, 1.7321335000", \ - "0.1240300000, 0.1361663000, 0.1649674000, 0.2330109000, 0.3973294000, 0.7901227000, 1.7313191000", \ - "0.1306121000, 0.1416187000, 0.1692710000, 0.2346280000, 0.3978511000, 0.7924770000, 1.7353357000", \ - "0.1725814000, 0.1838516000, 0.2099707000, 0.2699531000, 0.4148827000, 0.7910367000, 1.7379924000", \ - "0.2667973000, 0.2815875000, 0.3124953000, 0.3803790000, 0.5287559000, 0.8590168000, 1.7377599000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0327539000, 0.0347556000, 0.0394474000, 0.0501915000, 0.0745970000, 0.1311427000, 0.2648887000", \ - "0.0371178000, 0.0391236000, 0.0439131000, 0.0546699000, 0.0790538000, 0.1355618000, 0.2693184000", \ - "0.0464825000, 0.0484909000, 0.0532506000, 0.0639590000, 0.0884963000, 0.1451452000, 0.2788491000", \ - "0.0623835000, 0.0650370000, 0.0709463000, 0.0834967000, 0.1094530000, 0.1665649000, 0.3005485000", \ - "0.0820342000, 0.0859864000, 0.0946970000, 0.1127975000, 0.1478926000, 0.2138791000, 0.3496901000", \ - "0.0958017000, 0.1018865000, 0.1159368000, 0.1437380000, 0.1975321000, 0.2922403000, 0.4565578000", \ - "0.0766893000, 0.0862216000, 0.1075442000, 0.1523891000, 0.2375290000, 0.3857015000, 0.6281897000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1792320000, 0.1881111000, 0.2080884000, 0.2551871000, 0.3670515000, 0.6339545000, 1.2731427000", \ - "0.1833268000, 0.1916486000, 0.2110235000, 0.2588892000, 0.3711819000, 0.6380964000, 1.2770348000", \ - "0.1937196000, 0.2022240000, 0.2213546000, 0.2693692000, 0.3823376000, 0.6497349000, 1.2888618000", \ - "0.2205286000, 0.2288678000, 0.2485447000, 0.2963208000, 0.4089053000, 0.6767678000, 1.3162571000", \ - "0.2798317000, 0.2879606000, 0.3081057000, 0.3553669000, 0.4679557000, 0.7358435000, 1.3757896000", \ - "0.3967047000, 0.4070809000, 0.4308240000, 0.4867433000, 0.6048600000, 0.8726284000, 1.5132072000", \ - "0.5925264000, 0.6073496000, 0.6429014000, 0.7193775000, 0.8753521000, 1.1875400000, 1.8325967000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0331237000, 0.0352544000, 0.0404573000, 0.0531126000, 0.0838394000, 0.1587053000, 0.3393155000", \ - "0.0329365000, 0.0351208000, 0.0403272000, 0.0530169000, 0.0838973000, 0.1594469000, 0.3392823000", \ - "0.0338868000, 0.0358946000, 0.0408028000, 0.0530444000, 0.0837912000, 0.1587020000, 0.3390875000", \ - "0.0426196000, 0.0444007000, 0.0489123000, 0.0597073000, 0.0871504000, 0.1589282000, 0.3391858000", \ - "0.0640376000, 0.0661532000, 0.0712995000, 0.0831916000, 0.1096638000, 0.1737440000, 0.3413342000", \ - "0.1059486000, 0.1090005000, 0.1160131000, 0.1318137000, 0.1650084000, 0.2325471000, 0.3785783000", \ - "0.1831055000, 0.1877676000, 0.1984897000, 0.2212275000, 0.2679195000, 0.3551692000, 0.5197595000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1375136000, 0.1488252000, 0.1752385000, 0.2391227000, 0.3908956000, 0.7521924000, 1.6190144000", \ - "0.1374290000, 0.1485662000, 0.1754088000, 0.2388668000, 0.3906580000, 0.7521512000, 1.6200229000", \ - "0.1375942000, 0.1486064000, 0.1753656000, 0.2389529000, 0.3902149000, 0.7538378000, 1.6217371000", \ - "0.1375029000, 0.1486125000, 0.1754082000, 0.2388747000, 0.3905604000, 0.7518223000, 1.6175650000", \ - "0.1429511000, 0.1532352000, 0.1787206000, 0.2399143000, 0.3911154000, 0.7541304000, 1.6194442000", \ - "0.1815629000, 0.1922952000, 0.2173235000, 0.2716403000, 0.4078529000, 0.7559005000, 1.6241866000", \ - "0.2746356000, 0.2875516000, 0.3172110000, 0.3824690000, 0.5164700000, 0.8252438000, 1.6302362000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0152214000, 0.0164355000, 0.0192440000, 0.0257454000, 0.0407610000, 0.0766827000, 0.1625730000", \ - "0.0198809000, 0.0211071000, 0.0238849000, 0.0304013000, 0.0456127000, 0.0815301000, 0.1674554000", \ - "0.0272115000, 0.0291415000, 0.0333181000, 0.0415398000, 0.0570037000, 0.0929000000, 0.1785616000", \ - "0.0353881000, 0.0384930000, 0.0454339000, 0.0579167000, 0.0804051000, 0.1190766000, 0.2045993000", \ - "0.0404356000, 0.0454059000, 0.0558104000, 0.0764784000, 0.1123656000, 0.1712000000, 0.2655336000", \ - "0.0325971000, 0.0402935000, 0.0567173000, 0.0887871000, 0.1455484000, 0.2383189000, 0.3830259000", \ - "-0.013339200, -0.001995900, 0.0234743000, 0.0728491000, 0.1624525000, 0.3069106000, 0.5349147000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1222484000, 0.1306203000, 0.1513957000, 0.1990708000, 0.3124334000, 0.5797666000, 1.2187018000", \ - "0.1251377000, 0.1331666000, 0.1532014000, 0.2015533000, 0.3151356000, 0.5831543000, 1.2227012000", \ - "0.1332349000, 0.1413321000, 0.1615416000, 0.2098342000, 0.3232873000, 0.5919408000, 1.2334398000", \ - "0.1577722000, 0.1658391000, 0.1845664000, 0.2321999000, 0.3455764000, 0.6141210000, 1.2549971000", \ - "0.2204218000, 0.2283412000, 0.2475131000, 0.2922824000, 0.4039172000, 0.6713566000, 1.3118479000", \ - "0.3323207000, 0.3440816000, 0.3719669000, 0.4296466000, 0.5470889000, 0.8090522000, 1.4463940000", \ - "0.5151496000, 0.5315964000, 0.5690685000, 0.6522330000, 0.8195056000, 1.1375199000, 1.7668762000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.0164166000, 0.0179011000, 0.0215472000, 0.0301632000, 0.0502167000, 0.0975257000, 0.2105877000", \ - "0.0174731000, 0.0187185000, 0.0220072000, 0.0301988000, 0.0502467000, 0.0974431000, 0.2109809000", \ - "0.0253055000, 0.0259453000, 0.0278928000, 0.0340886000, 0.0514017000, 0.0975636000, 0.2114787000", \ - "0.0423931000, 0.0433638000, 0.0456483000, 0.0514873000, 0.0646185000, 0.1024939000, 0.2115664000", \ - "0.0727661000, 0.0740190000, 0.0773215000, 0.0852313000, 0.1027154000, 0.1369472000, 0.2247020000", \ - "0.1278254000, 0.1295581000, 0.1336842000, 0.1451490000, 0.1702868000, 0.2194619000, 0.3085581000", \ - "0.2265222000, 0.2301865000, 0.2362774000, 0.2523349000, 0.2900533000, 0.3643156000, 0.4930747000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012012300, 0.0028859000, 0.0069332700, 0.0166569000, 0.0400175000, 0.0961403000"); - values("0.1361273000, 0.1475213000, 0.1745522000, 0.2389861000, 0.3901086000, 0.7534740000, 1.6237737000", \ - "0.1359145000, 0.1471450000, 0.1744079000, 0.2385553000, 0.3904189000, 0.7518667000, 1.6195874000", \ - "0.1348632000, 0.1462310000, 0.1738687000, 0.2381404000, 0.3903615000, 0.7525384000, 1.6207443000", \ - "0.1312198000, 0.1428783000, 0.1706053000, 0.2371442000, 0.3915458000, 0.7517858000, 1.6186180000", \ - "0.1461929000, 0.1555190000, 0.1798270000, 0.2389409000, 0.3877793000, 0.7529518000, 1.6214585000", \ - "0.1952048000, 0.2063489000, 0.2343692000, 0.2948465000, 0.4206896000, 0.7544004000, 1.6232322000", \ - "0.2764159000, 0.2928787000, 0.3289413000, 0.4077158000, 0.5630976000, 0.8639990000, 1.6367614000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a221oi_4") { - leakage_power () { - value : 0.0071124000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0024622000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0047797000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0041742000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0003793000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0034749000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0047183000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0070353000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0064321000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0003790000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0034749000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0038862000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0062035000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0071124000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0056003000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0003790000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0034749000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0003628000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0031478000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0003627000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0030308000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0022636000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0031141000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0174297000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0481591000; - when : "A1&A2&B1&B2&!C1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__a221oi"; - cell_leakage_power : 0.0062105020; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0084210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0174714000, 0.0174696000, 0.0174655000, 0.0174592000, 0.0174448000, 0.0174115000, 0.0173350000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013026100, -0.013037900, -0.013065100, -0.013033700, -0.012961100, -0.012793900, -0.012408400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087790000; - } - pin ("A2") { - capacitance : 0.0091650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0087040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162362000, 0.0162298000, 0.0162151000, 0.0162140000, 0.0162117000, 0.0162060000, 0.0161934000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016211900, -0.016199900, -0.016172100, -0.016168300, -0.016159500, -0.016139300, -0.016092700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0096260000; - } - pin ("B1") { - capacitance : 0.0083010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0176664000, 0.0176701000, 0.0176786000, 0.0176709000, 0.0176532000, 0.0176123000, 0.0175184000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012419200, -0.012425800, -0.012440800, -0.012409300, -0.012336600, -0.012169000, -0.011782700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087690000; - } - pin ("B2") { - capacitance : 0.0088370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0164219000, 0.0164101000, 0.0163829000, 0.0163831000, 0.0163835000, 0.0163843000, 0.0163864000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016346700, -0.016343000, -0.016334400, -0.016335700, -0.016338500, -0.016345000, -0.016360100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0094130000; - } - pin ("C1") { - capacitance : 0.0084180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083351000, 0.0083166000, 0.0082740000, 0.0083241000, 0.0084396000, 0.0087059000, 0.0093198000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006844300, -0.006843600, -0.006842000, -0.006837200, -0.006826100, -0.006800300, -0.006740800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091500000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A1&!B2&!C1) | (!A2&!B1&!C1) | (!A2&!B2&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0297108000, 0.0283942000, 0.0249014000, 0.0157713000, -0.008235400, -0.071216000, -0.237566600", \ - "0.0294124000, 0.0280954000, 0.0246542000, 0.0155243000, -0.008488400, -0.071474300, -0.237725600", \ - "0.0290451000, 0.0277189000, 0.0242536000, 0.0151255000, -0.008874000, -0.071855900, -0.238167400", \ - "0.0283578000, 0.0269977000, 0.0236157000, 0.0145799000, -0.009271100, -0.072334400, -0.238550600", \ - "0.0276582000, 0.0263368000, 0.0229417000, 0.0141377000, -0.009690900, -0.072386500, -0.238815900", \ - "0.0277574000, 0.0264297000, 0.0229275000, 0.0137363000, -0.010334800, -0.073200000, -0.238879900", \ - "0.0324631000, 0.0311268000, 0.0275786000, 0.0183884000, -0.006995100, -0.071484900, -0.239054600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0548559000, 0.0561342000, 0.0596504000, 0.0688953000, 0.0928943000, 0.1559590000, 0.3215563000", \ - "0.0542450000, 0.0556343000, 0.0591467000, 0.0684778000, 0.0926789000, 0.1557843000, 0.3211999000", \ - "0.0532727000, 0.0546845000, 0.0582637000, 0.0676912000, 0.0920846000, 0.1554608000, 0.3209820000", \ - "0.0525301000, 0.0538696000, 0.0574632000, 0.0667958000, 0.0912070000, 0.1548698000, 0.3208694000", \ - "0.0519531000, 0.0532484000, 0.0566772000, 0.0659856000, 0.0901976000, 0.1537566000, 0.3198207000", \ - "0.0518409000, 0.0531572000, 0.0565768000, 0.0657681000, 0.0898851000, 0.1531514000, 0.3191591000", \ - "0.0517503000, 0.0531636000, 0.0566119000, 0.0658048000, 0.0901222000, 0.1529600000, 0.3185947000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0326977000, 0.0313898000, 0.0279205000, 0.0187924000, -0.005240600, -0.068237900, -0.234592000", \ - "0.0323778000, 0.0310576000, 0.0275836000, 0.0184673000, -0.005607100, -0.068571000, -0.234794000", \ - "0.0319043000, 0.0305969000, 0.0270868000, 0.0179592000, -0.006057600, -0.069022500, -0.235388000", \ - "0.0312837000, 0.0299979000, 0.0265583000, 0.0175218000, -0.006523700, -0.069494800, -0.235819900", \ - "0.0306052000, 0.0293422000, 0.0259225000, 0.0169147000, -0.006780600, -0.069562400, -0.235999700", \ - "0.0306966000, 0.0293554000, 0.0258574000, 0.0166347000, -0.007527100, -0.070040700, -0.236334000", \ - "0.0335981000, 0.0322443000, 0.0286903000, 0.0194194000, -0.005051300, -0.069044700, -0.236246100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0684629000, 0.0698345000, 0.0732731000, 0.0824718000, 0.1064515000, 0.1697738000, 0.3349794000", \ - "0.0680898000, 0.0693837000, 0.0727876000, 0.0820663000, 0.1061657000, 0.1692665000, 0.3346808000", \ - "0.0674537000, 0.0686991000, 0.0722578000, 0.0815716000, 0.1057731000, 0.1690005000, 0.3344782000", \ - "0.0668283000, 0.0682076000, 0.0716276000, 0.0809507000, 0.1052461000, 0.1686282000, 0.3342938000", \ - "0.0662922000, 0.0675291000, 0.0711026000, 0.0803387000, 0.1045552000, 0.1678526000, 0.3336480000", \ - "0.0661058000, 0.0673974000, 0.0710939000, 0.0801454000, 0.1043103000, 0.1677101000, 0.3335114000", \ - "0.0658048000, 0.0671861000, 0.0708875000, 0.0800795000, 0.1045109000, 0.1674283000, 0.3329100000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0161517000, 0.0148482000, 0.0114158000, 0.0023510000, -0.021546000, -0.084813900, -0.251869400", \ - "0.0159981000, 0.0147130000, 0.0112873000, 0.0022638000, -0.021607800, -0.084836700, -0.251885000", \ - "0.0156499000, 0.0143573000, 0.0109748000, 0.0020179000, -0.021741200, -0.084873900, -0.251879900", \ - "0.0148176000, 0.0135483000, 0.0102122000, 0.0014287000, -0.022116600, -0.085133500, -0.251958100", \ - "0.0142145000, 0.0129380000, 0.0094979000, 0.0006350000, -0.022634200, -0.085414700, -0.252158200", \ - "0.0150733000, 0.0137503000, 0.0102815000, 0.0012311000, -0.022532000, -0.085826200, -0.252504500", \ - "0.0182730000, 0.0168400000, 0.0132049000, 0.0036860000, -0.020767400, -0.084380300, -0.252185900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0436623000, 0.0449475000, 0.0485115000, 0.0577918000, 0.0820071000, 0.1449827000, 0.3101752000", \ - "0.0429092000, 0.0443727000, 0.0478995000, 0.0573379000, 0.0817015000, 0.1448812000, 0.3102810000", \ - "0.0419591000, 0.0432870000, 0.0468938000, 0.0563890000, 0.0809263000, 0.1443983000, 0.3103368000", \ - "0.0410593000, 0.0424060000, 0.0460108000, 0.0553918000, 0.0798923000, 0.1436063000, 0.3098052000", \ - "0.0404268000, 0.0417754000, 0.0453257000, 0.0546208000, 0.0787705000, 0.1423545000, 0.3087158000", \ - "0.0404140000, 0.0417040000, 0.0451647000, 0.0543734000, 0.0786090000, 0.1419405000, 0.3079692000", \ - "0.0410789000, 0.0423934000, 0.0458529000, 0.0548168000, 0.0787976000, 0.1423977000, 0.3079282000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0198471000, 0.0185419000, 0.0151116000, 0.0060434000, -0.017885200, -0.081140200, -0.248192400", \ - "0.0196954000, 0.0184078000, 0.0149917000, 0.0059602000, -0.017933900, -0.081168000, -0.248222400", \ - "0.0193214000, 0.0180384000, 0.0146705000, 0.0056939000, -0.018086900, -0.081234800, -0.248229400", \ - "0.0184458000, 0.0171860000, 0.0138666000, 0.0050511000, -0.018518000, -0.081437200, -0.248305500", \ - "0.0175106000, 0.0162332000, 0.0129053000, 0.0040919000, -0.019272000, -0.081836400, -0.248422600", \ - "0.0181665000, 0.0168377000, 0.0133970000, 0.0043396000, -0.019491300, -0.082710600, -0.248939200", \ - "0.0207689000, 0.0194136000, 0.0158069000, 0.0064341000, -0.017952100, -0.081577700, -0.248916200"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0576843000, 0.0590563000, 0.0624543000, 0.0716618000, 0.0957699000, 0.1588862000, 0.3243088000", \ - "0.0570895000, 0.0584744000, 0.0619457000, 0.0712173000, 0.0953773000, 0.1585448000, 0.3239530000", \ - "0.0563584000, 0.0577134000, 0.0612862000, 0.0706004000, 0.0948858000, 0.1581472000, 0.3239045000", \ - "0.0557450000, 0.0570705000, 0.0605162000, 0.0698773000, 0.0942125000, 0.1577656000, 0.3234160000", \ - "0.0551460000, 0.0565436000, 0.0600350000, 0.0692163000, 0.0933264000, 0.1568147000, 0.3229526000", \ - "0.0548755000, 0.0562076000, 0.0597576000, 0.0691326000, 0.0932561000, 0.1564565000, 0.3222352000", \ - "0.0557607000, 0.0569417000, 0.0603915000, 0.0694495000, 0.0936297000, 0.1570962000, 0.3229217000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0005319000, -0.000669700, -0.003923500, -0.012772600, -0.036676100, -0.100091500, -0.267434900", \ - "5.470000e-05, -0.001128800, -0.004260900, -0.012964800, -0.036602300, -0.099831500, -0.267058600", \ - "-0.000632000, -0.001736100, -0.004815700, -0.013380100, -0.036735000, -0.099642500, -0.266709700", \ - "-0.001177800, -0.002393500, -0.005520400, -0.014079200, -0.037220000, -0.099728100, -0.266512100", \ - "-0.000551300, -0.001836800, -0.005124000, -0.013917300, -0.037762400, -0.100146300, -0.266621400", \ - "0.0009911000, -0.000373100, -0.003936900, -0.013082800, -0.036912900, -0.099718000, -0.266806200", \ - "0.0070933000, 0.0055604000, 0.0017028000, -0.008228400, -0.033009300, -0.097032900, -0.264586500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0545748000, 0.0559755000, 0.0596674000, 0.0691469000, 0.0936921000, 0.1571488000, 0.3227403000", \ - "0.0539084000, 0.0553769000, 0.0590448000, 0.0685205000, 0.0930647000, 0.1567083000, 0.3225368000", \ - "0.0533818000, 0.0547078000, 0.0580997000, 0.0675276000, 0.0922062000, 0.1561577000, 0.3222201000", \ - "0.0527780000, 0.0540414000, 0.0576388000, 0.0669208000, 0.0913465000, 0.1551409000, 0.3216590000", \ - "0.0525836000, 0.0539242000, 0.0574051000, 0.0666001000, 0.0906410000, 0.1540664000, 0.3204043000", \ - "0.0547072000, 0.0559860000, 0.0593081000, 0.0683770000, 0.0923035000, 0.1537592000, 0.3192558000", \ - "0.0595369000, 0.0607756000, 0.0640117000, 0.0731180000, 0.0962004000, 0.1605103000, 0.3213224000"); - } - } - max_capacitance : 0.1666360000; - max_transition : 1.7603270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0291711000, 0.0309384000, 0.0352060000, 0.0461457000, 0.0719774000, 0.1332022000, 0.2828984000", \ - "0.0338521000, 0.0354925000, 0.0397578000, 0.0504263000, 0.0761346000, 0.1372533000, 0.2867317000", \ - "0.0460693000, 0.0475036000, 0.0513206000, 0.0614047000, 0.0863612000, 0.1469290000, 0.2963394000", \ - "0.0681700000, 0.0700539000, 0.0751181000, 0.0864943000, 0.1112255000, 0.1705300000, 0.3191579000", \ - "0.0969160000, 0.0996779000, 0.1065813000, 0.1225570000, 0.1573166000, 0.2253343000, 0.3719521000", \ - "0.1233799000, 0.1273632000, 0.1373337000, 0.1608975000, 0.2120071000, 0.3128977000, 0.4968550000", \ - "0.1205875000, 0.1263844000, 0.1409610000, 0.1759441000, 0.2517594000, 0.4065400000, 0.6838234000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.2093514000, 0.2156399000, 0.2317288000, 0.2737935000, 0.3820080000, 0.6639158000, 1.4034971000", \ - "0.2128114000, 0.2192705000, 0.2357002000, 0.2778495000, 0.3870314000, 0.6695387000, 1.4133894000", \ - "0.2236642000, 0.2299319000, 0.2461189000, 0.2889332000, 0.3988418000, 0.6825366000, 1.4247297000", \ - "0.2509484000, 0.2575195000, 0.2732137000, 0.3158638000, 0.4258955000, 0.7108417000, 1.4537673000", \ - "0.3106562000, 0.3167650000, 0.3326557000, 0.3745877000, 0.4838775000, 0.7685365000, 1.5117199000", \ - "0.4234237000, 0.4305287000, 0.4484874000, 0.4945019000, 0.6065538000, 0.8897118000, 1.6342017000", \ - "0.6160303000, 0.6250840000, 0.6478975000, 0.7055868000, 0.8409281000, 1.1532001000, 1.8986741000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0418371000, 0.0437595000, 0.0489611000, 0.0623203000, 0.0952793000, 0.1771599000, 0.3886325000", \ - "0.0402952000, 0.0423809000, 0.0477076000, 0.0614268000, 0.0947654000, 0.1768566000, 0.3887477000", \ - "0.0412727000, 0.0430915000, 0.0478037000, 0.0604580000, 0.0931792000, 0.1761094000, 0.3885276000", \ - "0.0522235000, 0.0539578000, 0.0585038000, 0.0695086000, 0.0972287000, 0.1752290000, 0.3880087000", \ - "0.0742163000, 0.0765531000, 0.0823170000, 0.0964824000, 0.1257082000, 0.1949129000, 0.3895781000", \ - "0.1164612000, 0.1201329000, 0.1281086000, 0.1463088000, 0.1845805000, 0.2640257000, 0.4436999000", \ - "0.1915225000, 0.1966262000, 0.2092419000, 0.2362247000, 0.2945911000, 0.4004775000, 0.6128835000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1388747000, 0.1465198000, 0.1670678000, 0.2225560000, 0.3680572000, 0.7495966000, 1.7479591000", \ - "0.1388957000, 0.1469703000, 0.1673088000, 0.2232979000, 0.3680463000, 0.7484905000, 1.7524294000", \ - "0.1387453000, 0.1468006000, 0.1680017000, 0.2233986000, 0.3693943000, 0.7508011000, 1.7490481000", \ - "0.1385447000, 0.1465296000, 0.1676204000, 0.2228331000, 0.3682487000, 0.7499878000, 1.7525249000", \ - "0.1398504000, 0.1480384000, 0.1689631000, 0.2237733000, 0.3681239000, 0.7515176000, 1.7504119000", \ - "0.1634932000, 0.1706763000, 0.1904631000, 0.2409024000, 0.3781493000, 0.7492802000, 1.7528243000", \ - "0.2207687000, 0.2291915000, 0.2498320000, 0.3053222000, 0.4443916000, 0.7929820000, 1.7603272000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0352415000, 0.0368984000, 0.0412479000, 0.0520151000, 0.0780180000, 0.1390907000, 0.2888186000", \ - "0.0396106000, 0.0414253000, 0.0456809000, 0.0564334000, 0.0822912000, 0.1434820000, 0.2924860000", \ - "0.0496043000, 0.0512051000, 0.0553169000, 0.0657770000, 0.0912937000, 0.1522944000, 0.3017016000", \ - "0.0688949000, 0.0707387000, 0.0753982000, 0.0866303000, 0.1119554000, 0.1724742000, 0.3215676000", \ - "0.0975383000, 0.1000347000, 0.1062307000, 0.1208770000, 0.1528683000, 0.2186940000, 0.3679459000", \ - "0.1297073000, 0.1332047000, 0.1419715000, 0.1622948000, 0.2073655000, 0.2985334000, 0.4715577000", \ - "0.1414253000, 0.1466437000, 0.1597633000, 0.1917152000, 0.2603809000, 0.3945866000, 0.6398884000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.2301307000, 0.2357737000, 0.2505782000, 0.2881295000, 0.3884047000, 0.6476931000, 1.3300393000", \ - "0.2334655000, 0.2395305000, 0.2549025000, 0.2930662000, 0.3930237000, 0.6526353000, 1.3325300000", \ - "0.2459118000, 0.2520681000, 0.2667956000, 0.3054920000, 0.4058895000, 0.6657906000, 1.3474077000", \ - "0.2738513000, 0.2800798000, 0.2954841000, 0.3338747000, 0.4341197000, 0.6950585000, 1.3758775000", \ - "0.3336057000, 0.3392851000, 0.3532949000, 0.3924363000, 0.4924501000, 0.7535160000, 1.4351308000", \ - "0.4467925000, 0.4528782000, 0.4688629000, 0.5091950000, 0.6122771000, 0.8726360000, 1.5543621000", \ - "0.6387617000, 0.6475275000, 0.6679118000, 0.7185033000, 0.8415373000, 1.1297794000, 1.8156001000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0415114000, 0.0435010000, 0.0486909000, 0.0621541000, 0.0952547000, 0.1769394000, 0.3882666000", \ - "0.0409532000, 0.0428973000, 0.0481298000, 0.0616598000, 0.0947164000, 0.1768466000, 0.3882568000", \ - "0.0411617000, 0.0431184000, 0.0480411000, 0.0610833000, 0.0940514000, 0.1763714000, 0.3880742000", \ - "0.0486542000, 0.0503019000, 0.0548050000, 0.0660930000, 0.0958654000, 0.1759439000, 0.3884408000", \ - "0.0675955000, 0.0695369000, 0.0743493000, 0.0859644000, 0.1155594000, 0.1870631000, 0.3888849000", \ - "0.1039165000, 0.1064603000, 0.1128405000, 0.1284319000, 0.1630366000, 0.2371842000, 0.4221342000", \ - "0.1711959000, 0.1746813000, 0.1831806000, 0.2052426000, 0.2505766000, 0.3451795000, 0.5423694000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1569376000, 0.1643626000, 0.1834429000, 0.2349548000, 0.3684330000, 0.7192527000, 1.6439787000", \ - "0.1571498000, 0.1641872000, 0.1833997000, 0.2347326000, 0.3682753000, 0.7190665000, 1.6385211000", \ - "0.1567862000, 0.1644736000, 0.1836363000, 0.2347232000, 0.3681832000, 0.7191062000, 1.6400483000", \ - "0.1571254000, 0.1641551000, 0.1834629000, 0.2347516000, 0.3683104000, 0.7197271000, 1.6385999000", \ - "0.1574268000, 0.1646012000, 0.1846579000, 0.2349193000, 0.3693684000, 0.7212895000, 1.6409402000", \ - "0.1795182000, 0.1864399000, 0.2056421000, 0.2520276000, 0.3788303000, 0.7202054000, 1.6434801000", \ - "0.2379916000, 0.2444560000, 0.2641308000, 0.3159068000, 0.4447006000, 0.7663790000, 1.6479133000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0316357000, 0.0331314000, 0.0368862000, 0.0463462000, 0.0696351000, 0.1283463000, 0.2795529000", \ - "0.0358067000, 0.0372584000, 0.0411479000, 0.0504554000, 0.0738260000, 0.1325024000, 0.2837486000", \ - "0.0461741000, 0.0474938000, 0.0511075000, 0.0602732000, 0.0836319000, 0.1423549000, 0.2936291000", \ - "0.0636438000, 0.0656576000, 0.0706241000, 0.0824257000, 0.1069232000, 0.1653964000, 0.3166503000", \ - "0.0824071000, 0.0853539000, 0.0924829000, 0.1099252000, 0.1467367000, 0.2187693000, 0.3697901000", \ - "0.0903177000, 0.0948561000, 0.1062529000, 0.1322776000, 0.1885478000, 0.2985603000, 0.4928561000", \ - "0.0570907000, 0.0646176000, 0.0816955000, 0.1225178000, 0.2102172000, 0.3783831000, 0.6746127000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1728635000, 0.1791361000, 0.1953506000, 0.2371011000, 0.3443406000, 0.6228568000, 1.3532857000", \ - "0.1751917000, 0.1817346000, 0.1981580000, 0.2403474000, 0.3485058000, 0.6276821000, 1.3583227000", \ - "0.1843093000, 0.1906375000, 0.2068528000, 0.2494508000, 0.3583437000, 0.6389604000, 1.3704554000", \ - "0.2104585000, 0.2165997000, 0.2322746000, 0.2745656000, 0.3834342000, 0.6654431000, 1.3985637000", \ - "0.2712491000, 0.2773105000, 0.2934642000, 0.3349203000, 0.4425538000, 0.7235847000, 1.4587400000", \ - "0.3880502000, 0.3960108000, 0.4157795000, 0.4651987000, 0.5820259000, 0.8620440000, 1.5959720000", \ - "0.5867111000, 0.5986317000, 0.6283381000, 0.6988577000, 0.8535914000, 1.1856182000, 1.9212318000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0396959000, 0.0412210000, 0.0454322000, 0.0565596000, 0.0864986000, 0.1664396000, 0.3787557000", \ - "0.0391657000, 0.0408046000, 0.0450948000, 0.0564096000, 0.0864008000, 0.1666044000, 0.3787767000", \ - "0.0402685000, 0.0417209000, 0.0456213000, 0.0563864000, 0.0863549000, 0.1663269000, 0.3786726000", \ - "0.0523191000, 0.0537310000, 0.0575397000, 0.0667577000, 0.0923333000, 0.1668388000, 0.3785572000", \ - "0.0784508000, 0.0803944000, 0.0852467000, 0.0967503000, 0.1247270000, 0.1890177000, 0.3804402000", \ - "0.1281342000, 0.1308445000, 0.1376684000, 0.1539137000, 0.1917289000, 0.2674058000, 0.4369202000", \ - "0.2171913000, 0.2202131000, 0.2308967000, 0.2563688000, 0.3087646000, 0.4163050000, 0.6206506000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1348717000, 0.1424567000, 0.1626839000, 0.2180621000, 0.3609208000, 0.7388676000, 1.7253406000", \ - "0.1348490000, 0.1428240000, 0.1627743000, 0.2182024000, 0.3617153000, 0.7367653000, 1.7260426000", \ - "0.1349714000, 0.1424735000, 0.1627485000, 0.2173416000, 0.3605017000, 0.7364716000, 1.7239290000", \ - "0.1346970000, 0.1426051000, 0.1630997000, 0.2174492000, 0.3608947000, 0.7389115000, 1.7293056000", \ - "0.1405863000, 0.1478513000, 0.1674312000, 0.2191484000, 0.3620945000, 0.7367684000, 1.7289464000", \ - "0.1792507000, 0.1869836000, 0.2056469000, 0.2530974000, 0.3806571000, 0.7383119000, 1.7291203000", \ - "0.2704401000, 0.2789901000, 0.3009859000, 0.3567272000, 0.4863204000, 0.8056340000, 1.7334375000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0392014000, 0.0406462000, 0.0443974000, 0.0538227000, 0.0771379000, 0.1358826000, 0.2871258000", \ - "0.0434479000, 0.0449466000, 0.0487057000, 0.0581577000, 0.0814640000, 0.1402173000, 0.2914434000", \ - "0.0523003000, 0.0537516000, 0.0575480000, 0.0669390000, 0.0903252000, 0.1491215000, 0.3004552000", \ - "0.0680547000, 0.0697809000, 0.0742033000, 0.0850132000, 0.1098505000, 0.1691025000, 0.3206521000", \ - "0.0879766000, 0.0904624000, 0.0968800000, 0.1119023000, 0.1444804000, 0.2124854000, 0.3660483000", \ - "0.1015517000, 0.1053101000, 0.1150777000, 0.1382832000, 0.1880115000, 0.2838414000, 0.4658869000", \ - "0.0788873000, 0.0850097000, 0.1011980000, 0.1372440000, 0.2157766000, 0.3656416000, 0.6272896000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.2019040000, 0.2080460000, 0.2235173000, 0.2620436000, 0.3615142000, 0.6210537000, 1.3009250000", \ - "0.2049372000, 0.2111614000, 0.2266726000, 0.2652719000, 0.3653935000, 0.6250960000, 1.3051269000", \ - "0.2160381000, 0.2212696000, 0.2357393000, 0.2756114000, 0.3761200000, 0.6365501000, 1.3176855000", \ - "0.2412210000, 0.2473943000, 0.2628225000, 0.3013803000, 0.4022246000, 0.6633244000, 1.3446019000", \ - "0.3014816000, 0.3073198000, 0.3219847000, 0.3611262000, 0.4614138000, 0.7223649000, 1.4044768000", \ - "0.4228898000, 0.4295476000, 0.4461273000, 0.4921867000, 0.5975026000, 0.8583331000, 1.5404644000", \ - "0.6319333000, 0.6416616000, 0.6667436000, 0.7274735000, 0.8671335000, 1.1703939000, 1.8579429000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0394443000, 0.0410248000, 0.0451984000, 0.0564069000, 0.0864170000, 0.1663551000, 0.3782117000", \ - "0.0392949000, 0.0409261000, 0.0451139000, 0.0563869000, 0.0865752000, 0.1664592000, 0.3786410000", \ - "0.0398348000, 0.0413274000, 0.0454177000, 0.0564036000, 0.0864967000, 0.1664980000, 0.3782473000", \ - "0.0472935000, 0.0487790000, 0.0524221000, 0.0621374000, 0.0895588000, 0.1669958000, 0.3787334000", \ - "0.0677961000, 0.0694568000, 0.0736007000, 0.0838806000, 0.1106784000, 0.1798963000, 0.3809514000", \ - "0.1104661000, 0.1124635000, 0.1176330000, 0.1311251000, 0.1630860000, 0.2339587000, 0.4143905000", \ - "0.1896321000, 0.1926712000, 0.1999103000, 0.2197187000, 0.2631063000, 0.3531077000, 0.5465834000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1576365000, 0.1643307000, 0.1834717000, 0.2346428000, 0.3686248000, 0.7201995000, 1.6396362000", \ - "0.1572214000, 0.1642832000, 0.1834186000, 0.2347000000, 0.3682202000, 0.7188624000, 1.6388745000", \ - "0.1566642000, 0.1641100000, 0.1839015000, 0.2346159000, 0.3684749000, 0.7212363000, 1.6432677000", \ - "0.1571092000, 0.1641689000, 0.1834367000, 0.2347323000, 0.3682432000, 0.7194010000, 1.6385889000", \ - "0.1608044000, 0.1677033000, 0.1859555000, 0.2355910000, 0.3687316000, 0.7208740000, 1.6425914000", \ - "0.1967213000, 0.2038822000, 0.2218269000, 0.2669470000, 0.3869339000, 0.7217038000, 1.6386789000", \ - "0.2882246000, 0.2963994000, 0.3174487000, 0.3671698000, 0.4927153000, 0.7920219000, 1.6484929000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0150803000, 0.0158927000, 0.0179456000, 0.0230666000, 0.0359282000, 0.0688961000, 0.1553177000", \ - "0.0196640000, 0.0204705000, 0.0225292000, 0.0277164000, 0.0406118000, 0.0736606000, 0.1601065000", \ - "0.0268538000, 0.0282127000, 0.0312386000, 0.0382189000, 0.0517829000, 0.0848064000, 0.1711476000", \ - "0.0344861000, 0.0365670000, 0.0413698000, 0.0522396000, 0.0734483000, 0.1106072000, 0.1965527000", \ - "0.0386155000, 0.0418762000, 0.0490086000, 0.0660149000, 0.0993313000, 0.1579629000, 0.2567896000", \ - "0.0259227000, 0.0309485000, 0.0430966000, 0.0706109000, 0.1224838000, 0.2148005000, 0.3678520000", \ - "-0.031301400, -0.023483800, -0.004918200, 0.0376597000, 0.1192456000, 0.2646358000, 0.5050760000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1408609000, 0.1459105000, 0.1621476000, 0.2018091000, 0.3030299000, 0.5640539000, 1.2447202000", \ - "0.1430935000, 0.1490019000, 0.1635221000, 0.2039918000, 0.3051858000, 0.5674844000, 1.2496107000", \ - "0.1511396000, 0.1569602000, 0.1720804000, 0.2110482000, 0.3135089000, 0.5759302000, 1.2584770000", \ - "0.1752662000, 0.1806383000, 0.1958368000, 0.2341055000, 0.3358699000, 0.5984142000, 1.2820071000", \ - "0.2401040000, 0.2451996000, 0.2591840000, 0.2965471000, 0.3948211000, 0.6560161000, 1.3395315000", \ - "0.3681453000, 0.3754802000, 0.3940898000, 0.4382497000, 0.5439230000, 0.7949677000, 1.4749185000", \ - "0.5735815000, 0.5842423000, 0.6113069000, 0.6767212000, 0.8266694000, 1.1386719000, 1.8105600000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0159149000, 0.0170051000, 0.0198620000, 0.0271073000, 0.0449826000, 0.0896445000, 0.2058098000", \ - "0.0168972000, 0.0178472000, 0.0203558000, 0.0271605000, 0.0450267000, 0.0895789000, 0.2055449000", \ - "0.0256644000, 0.0259248000, 0.0271188000, 0.0318864000, 0.0467807000, 0.0896457000, 0.2053637000", \ - "0.0430280000, 0.0436167000, 0.0453306000, 0.0499684000, 0.0615751000, 0.0960239000, 0.2050499000", \ - "0.0744832000, 0.0752341000, 0.0773409000, 0.0835057000, 0.0986954000, 0.1329695000, 0.2199614000", \ - "0.1315305000, 0.1324801000, 0.1353167000, 0.1431239000, 0.1649056000, 0.2120110000, 0.3056705000", \ - "0.2345623000, 0.2358789000, 0.2404219000, 0.2518087000, 0.2823670000, 0.3534438000, 0.4883803000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.1557064000, 0.1632013000, 0.1829163000, 0.2345199000, 0.3682180000, 0.7197818000, 1.6390093000", \ - "0.1555690000, 0.1626794000, 0.1834452000, 0.2344417000, 0.3684687000, 0.7193560000, 1.6438855000", \ - "0.1550680000, 0.1622504000, 0.1820668000, 0.2343444000, 0.3682403000, 0.7194773000, 1.6399112000", \ - "0.1508232000, 0.1587929000, 0.1797795000, 0.2332922000, 0.3680757000, 0.7196453000, 1.6438472000", \ - "0.1607096000, 0.1674459000, 0.1854814000, 0.2336503000, 0.3655165000, 0.7207422000, 1.6435371000", \ - "0.2096213000, 0.2174586000, 0.2380629000, 0.2863703000, 0.3987381000, 0.7224994000, 1.6435775000", \ - "0.2973100000, 0.3080723000, 0.3349099000, 0.3972698000, 0.5357219000, 0.8358348000, 1.6536112000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a222oi_1") { - leakage_power () { - value : 0.0007259000; - when : "!A1&!A2&!B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0002046000; - when : "!A1&!A2&!B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&!A2&!B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0007770000; - when : "!A1&!A2&!B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0015811000; - when : "!A1&!A2&!B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0010598000; - when : "!A1&!A2&!B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&!A2&!B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0016323000; - when : "!A1&!A2&!B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0013895000; - when : "!A1&!A2&B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0008682000; - when : "!A1&!A2&B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&!A2&B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0014407000; - when : "!A1&!A2&B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0023719000; - when : "!A1&!A2&B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0024386000; - when : "!A1&!A2&B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002728000; - when : "!A1&!A2&B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0023719000; - when : "!A1&!A2&B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0015345000; - when : "!A1&A2&!B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0010132000; - when : "!A1&A2&!B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&A2&!B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0015857000; - when : "!A1&A2&!B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0023899000; - when : "!A1&A2&!B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0018684000; - when : "!A1&A2&!B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&A2&!B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0024409000; - when : "!A1&A2&!B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0021982000; - when : "!A1&A2&B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0016768000; - when : "!A1&A2&B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&A2&B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0022493000; - when : "!A1&A2&B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0023719000; - when : "!A1&A2&B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0024386000; - when : "!A1&A2&B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002728000; - when : "!A1&A2&B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0023719000; - when : "!A1&A2&B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0011394000; - when : "A1&!A2&!B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0006181000; - when : "A1&!A2&!B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "A1&!A2&!B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0011906000; - when : "A1&!A2&!B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0019946000; - when : "A1&!A2&!B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0014733000; - when : "A1&!A2&!B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "A1&!A2&!B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0020458000; - when : "A1&!A2&!B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0018030000; - when : "A1&!A2&B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0012817000; - when : "A1&!A2&B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0079443000; - when : "A1&!A2&B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0018542000; - when : "A1&!A2&B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0023719000; - when : "A1&!A2&B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0024386000; - when : "A1&!A2&B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002728000; - when : "A1&!A2&B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0023719000; - when : "A1&!A2&B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0022640000; - when : "A1&A2&!B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0022832000; - when : "A1&A2&!B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002735000; - when : "A1&A2&!B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0022640000; - when : "A1&A2&!B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0021739000; - when : "A1&A2&!B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0021810000; - when : "A1&A2&!B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002735000; - when : "A1&A2&!B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0021739000; - when : "A1&A2&!B1&B2&C1&!C2"; - } - leakage_power () { - value : 0.0022432000; - when : "A1&A2&B1&!B2&!C1&C2"; - } - leakage_power () { - value : 0.0022581000; - when : "A1&A2&B1&!B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002733000; - when : "A1&A2&B1&!B2&C1&C2"; - } - leakage_power () { - value : 0.0022432000; - when : "A1&A2&B1&!B2&C1&!C2"; - } - leakage_power () { - value : 0.0002613000; - when : "A1&A2&B1&B2&!C1&C2"; - } - leakage_power () { - value : 0.0002621000; - when : "A1&A2&B1&B2&!C1&!C2"; - } - leakage_power () { - value : 0.0002340000; - when : "A1&A2&B1&B2&C1&C2"; - } - leakage_power () { - value : 0.0002613000; - when : "A1&A2&B1&B2&C1&!C2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a222oi"; - cell_leakage_power : 0.0024347500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044191000, 0.0044186000, 0.0044175000, 0.0044175000, 0.0044177000, 0.0044180000, 0.0044187000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003428900, -0.003431600, -0.003437900, -0.003430300, -0.003413000, -0.003373100, -0.003280900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022720000; - } - pin ("A2") { - capacitance : 0.0022470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039867000, 0.0039860000, 0.0039844000, 0.0039868000, 0.0039925000, 0.0040057000, 0.0040359000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003992900, -0.003988900, -0.003979600, -0.003980400, -0.003982000, -0.003985900, -0.003994800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023530000; - } - pin ("B1") { - capacitance : 0.0022360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045529000, 0.0045451000, 0.0045270000, 0.0045264000, 0.0045251000, 0.0045222000, 0.0045154000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003695400, -0.003702800, -0.003719800, -0.003713500, -0.003699000, -0.003665400, -0.003588100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023460000; - } - pin ("B2") { - capacitance : 0.0022960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041906000, 0.0041910000, 0.0041921000, 0.0041919000, 0.0041915000, 0.0041904000, 0.0041879000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004190300, -0.004188800, -0.004185600, -0.004185600, -0.004185800, -0.004186100, -0.004186900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024600000; - } - pin ("C1") { - capacitance : 0.0022600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047448000, 0.0047440000, 0.0047422000, 0.0047413000, 0.0047391000, 0.0047341000, 0.0047225000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003943600, -0.003947600, -0.003956800, -0.003949700, -0.003933400, -0.003895900, -0.003809300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024100000; - } - pin ("C2") { - capacitance : 0.0022990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042487000, 0.0042474000, 0.0042445000, 0.0042437000, 0.0042420000, 0.0042381000, 0.0042290000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004249600, -0.004248800, -0.004247100, -0.004246900, -0.004246500, -0.004245500, -0.004243300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024920000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A1&!B1&!C2) | (!A1&!B2&!C1) | (!A2&!B1&!C1) | (!A1&!B2&!C2) | (!A2&!B1&!C2) | (!A2&!B2&!C1) | (!A2&!B2&!C2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0080884000, 0.0070789000, 0.0048109000, -0.000322200, -0.011929700, -0.038196400, -0.097553900", \ - "0.0080843000, 0.0070933000, 0.0048186000, -0.000305000, -0.011908700, -0.038165500, -0.097527300", \ - "0.0080264000, 0.0070224000, 0.0047747000, -0.000331200, -0.011909400, -0.038152100, -0.097499300", \ - "0.0078406000, 0.0068507000, 0.0046451000, -0.000429000, -0.011970700, -0.038169400, -0.097498000", \ - "0.0076090000, 0.0066232000, 0.0044125000, -0.000672700, -0.012157300, -0.038262500, -0.097539700", \ - "0.0077054000, 0.0066874000, 0.0044168000, -0.000710300, -0.012360400, -0.038447700, -0.097594500", \ - "0.0084456000, 0.0074074000, 0.0050802000, -0.000162700, -0.011898300, -0.038271300, -0.097641000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0186427000, 0.0196537000, 0.0219946000, 0.0271324000, 0.0387213000, 0.0647921000, 0.1235284000", \ - "0.0185396000, 0.0195587000, 0.0218730000, 0.0270390000, 0.0386736000, 0.0647716000, 0.1235818000", \ - "0.0183709000, 0.0194149000, 0.0217089000, 0.0269302000, 0.0385885000, 0.0646946000, 0.1235427000", \ - "0.0182012000, 0.0192331000, 0.0215413000, 0.0267573000, 0.0384139000, 0.0646007000, 0.1233842000", \ - "0.0180764000, 0.0190936000, 0.0213590000, 0.0265684000, 0.0382407000, 0.0644222000, 0.1232276000", \ - "0.0180441000, 0.0190363000, 0.0213977000, 0.0265860000, 0.0381822000, 0.0643103000, 0.1231121000", \ - "0.0182027000, 0.0191993000, 0.0214566000, 0.0267382000, 0.0382328000, 0.0644716000, 0.1232927000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0041623000, 0.0031823000, 0.0009336000, -0.004184100, -0.015832200, -0.042149200, -0.101592500", \ - "0.0040747000, 0.0031161000, 0.0009031000, -0.004166700, -0.015761900, -0.042067400, -0.101487500", \ - "0.0039337000, 0.0029857000, 0.0008033000, -0.004212400, -0.015742800, -0.041984100, -0.101381500", \ - "0.0037076000, 0.0027795000, 0.0006135000, -0.004351100, -0.015831900, -0.041996700, -0.101348200", \ - "0.0035562000, 0.0025772000, 0.0003995000, -0.004579200, -0.016004700, -0.042120400, -0.101399600", \ - "0.0039987000, 0.0029956000, 0.0007967000, -0.004603600, -0.016226400, -0.042138700, -0.101424000", \ - "0.0051038000, 0.0040108000, 0.0015539000, -0.003837700, -0.015653600, -0.041755700, -0.101465900"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0130122000, 0.0140474000, 0.0163803000, 0.0215765000, 0.0331949000, 0.0592761000, 0.1180899000", \ - "0.0128191000, 0.0138596000, 0.0162094000, 0.0214465000, 0.0331276000, 0.0592278000, 0.1181200000", \ - "0.0125411000, 0.0135660000, 0.0159056000, 0.0212178000, 0.0329513000, 0.0591201000, 0.1179500000", \ - "0.0122890000, 0.0133078000, 0.0156642000, 0.0209097000, 0.0326695000, 0.0589692000, 0.1177940000", \ - "0.0121940000, 0.0131986000, 0.0155196000, 0.0207006000, 0.0323899000, 0.0586656000, 0.1176152000", \ - "0.0125800000, 0.0135492000, 0.0157881000, 0.0208785000, 0.0324150000, 0.0584906000, 0.1173575000", \ - "0.0139455000, 0.0149114000, 0.0170693000, 0.0220149000, 0.0333410000, 0.0588991000, 0.1175780000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0044804000, 0.0034918000, 0.0012253000, -0.003912600, -0.015567100, -0.041899800, -0.101352600", \ - "0.0044098000, 0.0034412000, 0.0012161000, -0.003880000, -0.015494700, -0.041808400, -0.101243900", \ - "0.0042396000, 0.0032965000, 0.0011157000, -0.003916500, -0.015463900, -0.041732400, -0.101139700", \ - "0.0039743000, 0.0030480000, 0.0008876000, -0.004076800, -0.015530500, -0.041726400, -0.101085400", \ - "0.0037709000, 0.0027867000, 0.0006122000, -0.004356000, -0.015759200, -0.041832500, -0.101116200", \ - "0.0039391000, 0.0029357000, 0.0006814000, -0.004387300, -0.015960800, -0.042033100, -0.101240600", \ - "0.0049660000, 0.0038935000, 0.0014897000, -0.003815700, -0.015586500, -0.041888000, -0.101290600"); - } - related_pin : "C2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0159104000, 0.0169080000, 0.0192006000, 0.0243801000, 0.0360035000, 0.0620862000, 0.1208793000", \ - "0.0157426000, 0.0167850000, 0.0190903000, 0.0242913000, 0.0359263000, 0.0620145000, 0.1207715000", \ - "0.0155496000, 0.0165735000, 0.0188742000, 0.0241289000, 0.0358048000, 0.0619410000, 0.1207075000", \ - "0.0153590000, 0.0164364000, 0.0186894000, 0.0239192000, 0.0356320000, 0.0618366000, 0.1206745000", \ - "0.0153066000, 0.0163319000, 0.0186327000, 0.0238063000, 0.0355003000, 0.0616672000, 0.1205939000", \ - "0.0156908000, 0.0166695000, 0.0189369000, 0.0240444000, 0.0356014000, 0.0616339000, 0.1204508000", \ - "0.0178886000, 0.0187423000, 0.0206692000, 0.0256047000, 0.0368467000, 0.0630412000, 0.1208141000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0110704000, 0.0100803000, 0.0077910000, 0.0026543000, -0.008900600, -0.034994400, -0.094207000", \ - "0.0109830000, 0.0099916000, 0.0076962000, 0.0025877000, -0.008959000, -0.035107600, -0.094235300", \ - "0.0108910000, 0.0098923000, 0.0075942000, 0.0024420000, -0.009074500, -0.035155200, -0.094365200", \ - "0.0107143000, 0.0097508000, 0.0074655000, 0.0022949000, -0.009203900, -0.035301700, -0.094460100", \ - "0.0105787000, 0.0095787000, 0.0073169000, 0.0022184000, -0.009242200, -0.035447100, -0.094536700", \ - "0.0107239000, 0.0096934000, 0.0073796000, 0.0021586000, -0.009422000, -0.035501900, -0.094600700", \ - "0.0120522000, 0.0110231000, 0.0086375000, 0.0035368000, -0.008724100, -0.034800800, -0.094611800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0185066000, 0.0195384000, 0.0218305000, 0.0270151000, 0.0386266000, 0.0646709000, 0.1234029000", \ - "0.0183733000, 0.0194130000, 0.0217202000, 0.0269259000, 0.0385626000, 0.0646337000, 0.1234092000", \ - "0.0181466000, 0.0191961000, 0.0215357000, 0.0267508000, 0.0384492000, 0.0645325000, 0.1233386000", \ - "0.0178921000, 0.0189370000, 0.0212637000, 0.0264914000, 0.0382181000, 0.0643621000, 0.1232632000", \ - "0.0177234000, 0.0187379000, 0.0210281000, 0.0262410000, 0.0379034000, 0.0641381000, 0.1230245000", \ - "0.0176719000, 0.0186864000, 0.0209847000, 0.0261339000, 0.0377713000, 0.0639436000, 0.1227578000", \ - "0.0176179000, 0.0186880000, 0.0209795000, 0.0261893000, 0.0378003000, 0.0637544000, 0.1225662000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0115809000, 0.0105717000, 0.0082845000, 0.0031533000, -0.008402500, -0.034496500, -0.093710600", \ - "0.0114996000, 0.0104864000, 0.0081898000, 0.0030546000, -0.008491700, -0.034587100, -0.093784300", \ - "0.0113740000, 0.0103628000, 0.0080840000, 0.0029432000, -0.008607100, -0.034735100, -0.093933100", \ - "0.0112705000, 0.0102624000, 0.0079726000, 0.0028275000, -0.008727700, -0.034801900, -0.094016000", \ - "0.0111025000, 0.0100962000, 0.0078430000, 0.0027934000, -0.008829500, -0.034876300, -0.094067900", \ - "0.0112164000, 0.0101951000, 0.0078699000, 0.0026930000, -0.008904700, -0.034964500, -0.094062800", \ - "0.0120496000, 0.0110150000, 0.0086885000, 0.0034556000, -0.008269200, -0.034714500, -0.094018500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0215479000, 0.0225916000, 0.0248692000, 0.0300442000, 0.0416438000, 0.0676803000, 0.1264469000", \ - "0.0214666000, 0.0225244000, 0.0247981000, 0.0299883000, 0.0415957000, 0.0676543000, 0.1263587000", \ - "0.0213471000, 0.0223817000, 0.0246860000, 0.0298860000, 0.0414892000, 0.0676230000, 0.1263363000", \ - "0.0212097000, 0.0222218000, 0.0245444000, 0.0297214000, 0.0413769000, 0.0675335000, 0.1263032000", \ - "0.0210586000, 0.0221091000, 0.0243757000, 0.0295815000, 0.0412236000, 0.0673693000, 0.1261713000", \ - "0.0210278000, 0.0220442000, 0.0243334000, 0.0295210000, 0.0411279000, 0.0672561000, 0.1262467000", \ - "0.0209613000, 0.0220207000, 0.0242837000, 0.0295672000, 0.0411582000, 0.0671647000, 0.1259118000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0075501000, 0.0065386000, 0.0042708000, -0.000858400, -0.012467600, -0.038735800, -0.098092500", \ - "0.0075183000, 0.0065205000, 0.0042764000, -0.000833100, -0.012432600, -0.038699700, -0.098056400", \ - "0.0075135000, 0.0065205000, 0.0042331000, -0.000860500, -0.012422600, -0.038653600, -0.098005600", \ - "0.0073341000, 0.0063498000, 0.0041205000, -0.000984200, -0.012519400, -0.038691300, -0.098000600", \ - "0.0071452000, 0.0062180000, 0.0039817000, -0.001122200, -0.012535500, -0.038817600, -0.098054700", \ - "0.0073005000, 0.0062846000, 0.0039999000, -0.001152800, -0.012833300, -0.038770400, -0.098102500", \ - "0.0082112000, 0.0071704000, 0.0048370000, -0.000510000, -0.011974600, -0.038599500, -0.098060500"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0157472000, 0.0167718000, 0.0190751000, 0.0242604000, 0.0358894000, 0.0620039000, 0.1206852000", \ - "0.0156308000, 0.0166377000, 0.0189650000, 0.0241772000, 0.0358184000, 0.0619560000, 0.1206444000", \ - "0.0153773000, 0.0164239000, 0.0187735000, 0.0239976000, 0.0357091000, 0.0618510000, 0.1207470000", \ - "0.0151216000, 0.0161573000, 0.0184796000, 0.0237272000, 0.0354471000, 0.0616916000, 0.1205271000", \ - "0.0149401000, 0.0159643000, 0.0182617000, 0.0234673000, 0.0351377000, 0.0613837000, 0.1203002000", \ - "0.0149023000, 0.0159261000, 0.0182205000, 0.0234498000, 0.0350449000, 0.0611360000, 0.1200971000", \ - "0.0150417000, 0.0160110000, 0.0183135000, 0.0234686000, 0.0350244000, 0.0612909000, 0.1200962000"); - } - } - max_capacitance : 0.0659280000; - max_transition : 2.1354590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0535556000, 0.0578479000, 0.0669363000, 0.0865058000, 0.1276936000, 0.2152164000, 0.4069360000", \ - "0.0577231000, 0.0620175000, 0.0712290000, 0.0907311000, 0.1316582000, 0.2193989000, 0.4113528000", \ - "0.0684809000, 0.0725940000, 0.0815811000, 0.1007484000, 0.1416475000, 0.2291393000, 0.4211147000", \ - "0.0947198000, 0.0985035000, 0.1071250000, 0.1254707000, 0.1658885000, 0.2534123000, 0.4454417000", \ - "0.1370827000, 0.1427053000, 0.1545265000, 0.1782516000, 0.2229690000, 0.3100743000, 0.5001861000", \ - "0.1917397000, 0.2000392000, 0.2175793000, 0.2527304000, 0.3180192000, 0.4288120000, 0.6287170000", \ - "0.2391096000, 0.2515119000, 0.2776351000, 0.3297946000, 0.4318659000, 0.6033160000, 0.8956671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.2310211000, 0.2458561000, 0.2777128000, 0.3491754000, 0.5085208000, 0.8664926000, 1.6729935000", \ - "0.2354964000, 0.2502455000, 0.2822156000, 0.3542071000, 0.5141526000, 0.8735533000, 1.6787274000", \ - "0.2474892000, 0.2620257000, 0.2943142000, 0.3662545000, 0.5266991000, 0.8859722000, 1.6932560000", \ - "0.2754150000, 0.2893907000, 0.3219938000, 0.3940181000, 0.5547469000, 0.9147760000, 1.7225688000", \ - "0.3342840000, 0.3485502000, 0.3808487000, 0.4523613000, 0.6132385000, 0.9736592000, 1.7822788000", \ - "0.4509869000, 0.4664777000, 0.5015072000, 0.5753681000, 0.7351768000, 1.0942165000, 1.9024089000", \ - "0.6476300000, 0.6689997000, 0.7126905000, 0.8034058000, 0.9889213000, 1.3621039000, 2.1726256000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0545403000, 0.0595494000, 0.0697792000, 0.0930323000, 0.1429935000, 0.2540548000, 0.5040049000", \ - "0.0540219000, 0.0588079000, 0.0697181000, 0.0927865000, 0.1423099000, 0.2542770000, 0.5061289000", \ - "0.0523116000, 0.0572081000, 0.0680150000, 0.0920063000, 0.1418486000, 0.2537649000, 0.5037384000", \ - "0.0582066000, 0.0624387000, 0.0719248000, 0.0931827000, 0.1415975000, 0.2531812000, 0.5056958000", \ - "0.0859428000, 0.0906892000, 0.1004276000, 0.1207432000, 0.1591492000, 0.2595548000, 0.5039540000", \ - "0.1336404000, 0.1407101000, 0.1551188000, 0.1828604000, 0.2332167000, 0.3246698000, 0.5291957000", \ - "0.2200062000, 0.2302219000, 0.2539292000, 0.2951633000, 0.3675982000, 0.4976649000, 0.7060911000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1704179000, 0.1898861000, 0.2326918000, 0.3305943000, 0.5465627000, 1.0338974000, 2.1327120000", \ - "0.1706239000, 0.1899255000, 0.2327624000, 0.3292065000, 0.5470140000, 1.0376554000, 2.1326525000", \ - "0.1709251000, 0.1895097000, 0.2327017000, 0.3293886000, 0.5466068000, 1.0341551000, 2.1316375000", \ - "0.1703346000, 0.1895720000, 0.2328075000, 0.3299234000, 0.5466094000, 1.0342256000, 2.1312658000", \ - "0.1712834000, 0.1901235000, 0.2328647000, 0.3296593000, 0.5481390000, 1.0376837000, 2.1347850000", \ - "0.1934736000, 0.2118972000, 0.2509051000, 0.3412829000, 0.5507007000, 1.0358030000, 2.1325486000", \ - "0.2591329000, 0.2788030000, 0.3213750000, 0.4158359000, 0.6130219000, 1.0649618000, 2.1354594000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0584228000, 0.0626758000, 0.0717887000, 0.0914415000, 0.1325268000, 0.2200007000, 0.4117895000", \ - "0.0629731000, 0.0672591000, 0.0764798000, 0.0959632000, 0.1370658000, 0.2245279000, 0.4164766000", \ - "0.0730929000, 0.0773367000, 0.0864742000, 0.1059593000, 0.1467392000, 0.2345955000, 0.4263394000", \ - "0.0965723000, 0.1008751000, 0.1099260000, 0.1289658000, 0.1696971000, 0.2575064000, 0.4494295000", \ - "0.1402106000, 0.1453894000, 0.1563834000, 0.1780959000, 0.2223681000, 0.3114035000, 0.5029251000", \ - "0.2019898000, 0.2093232000, 0.2245891000, 0.2568669000, 0.3161724000, 0.4242361000, 0.6263718000", \ - "0.2716351000, 0.2838109000, 0.3078812000, 0.3546951000, 0.4465696000, 0.6053895000, 0.8714343000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.2523141000, 0.2667996000, 0.2986172000, 0.3683781000, 0.5244784000, 0.8765604000, 1.6685855000", \ - "0.2573154000, 0.2717867000, 0.3036989000, 0.3732926000, 0.5300104000, 0.8821145000, 1.6744324000", \ - "0.2710692000, 0.2842731000, 0.3156238000, 0.3858457000, 0.5436523000, 0.8961492000, 1.6878503000", \ - "0.2986089000, 0.3116219000, 0.3440720000, 0.4139264000, 0.5714065000, 0.9240799000, 1.7162238000", \ - "0.3531512000, 0.3682768000, 0.3995957000, 0.4697796000, 0.6269154000, 0.9796152000, 1.7726792000", \ - "0.4625789000, 0.4775018000, 0.5095999000, 0.5824602000, 0.7393641000, 1.0918104000, 1.8849255000", \ - "0.6423151000, 0.6610771000, 0.7007810000, 0.7893693000, 0.9694048000, 1.3368369000, 2.1298034000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0543305000, 0.0589963000, 0.0695352000, 0.0929260000, 0.1429148000, 0.2542838000, 0.5041593000", \ - "0.0539983000, 0.0588010000, 0.0697104000, 0.0926813000, 0.1427359000, 0.2542203000, 0.5040778000", \ - "0.0530891000, 0.0578428000, 0.0688233000, 0.0922908000, 0.1423303000, 0.2542466000, 0.5057072000", \ - "0.0559243000, 0.0603722000, 0.0702415000, 0.0922591000, 0.1419503000, 0.2538843000, 0.5052416000", \ - "0.0752553000, 0.0796063000, 0.0888349000, 0.1105135000, 0.1513920000, 0.2565774000, 0.5039954000", \ - "0.1163519000, 0.1221919000, 0.1341349000, 0.1587296000, 0.2048029000, 0.2984364000, 0.5211377000", \ - "0.1912894000, 0.1992859000, 0.2161841000, 0.2516137000, 0.3148817000, 0.4269314000, 0.6380204000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1902889000, 0.2092043000, 0.2518058000, 0.3480750000, 0.5610175000, 1.0402220000, 2.1190207000", \ - "0.1902646000, 0.2092377000, 0.2517634000, 0.3479213000, 0.5607783000, 1.0407768000, 2.1201425000", \ - "0.1901636000, 0.2092334000, 0.2518450000, 0.3473796000, 0.5608748000, 1.0410837000, 2.1190516000", \ - "0.1901380000, 0.2092033000, 0.2520361000, 0.3471049000, 0.5608427000, 1.0427815000, 2.1205602000", \ - "0.1908965000, 0.2098877000, 0.2519138000, 0.3471210000, 0.5608621000, 1.0416867000, 2.1206998000", \ - "0.2118058000, 0.2299430000, 0.2689690000, 0.3591024000, 0.5657111000, 1.0409480000, 2.1212267000", \ - "0.2757112000, 0.2955132000, 0.3380154000, 0.4302492000, 0.6277353000, 1.0735451000, 2.1250632000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0461211000, 0.0496360000, 0.0575224000, 0.0746462000, 0.1121263000, 0.1954012000, 0.3817223000", \ - "0.0504571000, 0.0540144000, 0.0618506000, 0.0790507000, 0.1165685000, 0.1998099000, 0.3861165000", \ - "0.0610246000, 0.0646338000, 0.0721959000, 0.0893809000, 0.1270277000, 0.2102963000, 0.3966245000", \ - "0.0844065000, 0.0884203000, 0.0967807000, 0.1132704000, 0.1508930000, 0.2343434000, 0.4207238000", \ - "0.1170676000, 0.1222394000, 0.1348943000, 0.1607009000, 0.2062791000, 0.2909725000, 0.4758908000", \ - "0.1520414000, 0.1612637000, 0.1805758000, 0.2188361000, 0.2890235000, 0.4073428000, 0.6075717000", \ - "0.1697531000, 0.1838786000, 0.2135969000, 0.2728346000, 0.3799306000, 0.5647167000, 0.8609158000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.2015097000, 0.2153683000, 0.2462998000, 0.3163357000, 0.4726384000, 0.8233279000, 1.6132297000", \ - "0.2048698000, 0.2190254000, 0.2501733000, 0.3206472000, 0.4772726000, 0.8279315000, 1.6167305000", \ - "0.2146069000, 0.2289681000, 0.2606629000, 0.3312240000, 0.4881963000, 0.8396224000, 1.6292934000", \ - "0.2401896000, 0.2545576000, 0.2862481000, 0.3568443000, 0.5144855000, 0.8669252000, 1.6572591000", \ - "0.3000356000, 0.3139301000, 0.3451524000, 0.4155146000, 0.5729145000, 0.9255849000, 1.7166235000", \ - "0.4233502000, 0.4405933000, 0.4756467000, 0.5528905000, 0.7095796000, 1.0619432000, 1.8525524000", \ - "0.6322523000, 0.6557374000, 0.7078936000, 0.8100434000, 1.0070328000, 1.3825739000, 2.1734607000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0474888000, 0.0516634000, 0.0610515000, 0.0823433000, 0.1309483000, 0.2398470000, 0.4870941000", \ - "0.0474806000, 0.0516357000, 0.0610653000, 0.0823745000, 0.1308387000, 0.2399930000, 0.4871042000", \ - "0.0473937000, 0.0514164000, 0.0608256000, 0.0822768000, 0.1309565000, 0.2399109000, 0.4870793000", \ - "0.0570006000, 0.0603037000, 0.0680308000, 0.0867484000, 0.1319018000, 0.2399317000, 0.4870521000", \ - "0.0863112000, 0.0915431000, 0.1003039000, 0.1180654000, 0.1558724000, 0.2485296000, 0.4867490000", \ - "0.1397236000, 0.1459777000, 0.1592113000, 0.1855051000, 0.2329345000, 0.3221778000, 0.5184648000", \ - "0.2334779000, 0.2433408000, 0.2635289000, 0.3038182000, 0.3764469000, 0.4968317000, 0.6995236000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1670644000, 0.1857861000, 0.2281023000, 0.3224601000, 0.5345254000, 1.0112547000, 2.0903972000", \ - "0.1674473000, 0.1856813000, 0.2280401000, 0.3224379000, 0.5346663000, 1.0113858000, 2.0842326000", \ - "0.1673894000, 0.1859231000, 0.2279660000, 0.3223966000, 0.5347914000, 1.0111950000, 2.0837780000", \ - "0.1671757000, 0.1861656000, 0.2279218000, 0.3226710000, 0.5364930000, 1.0108052000, 2.0874831000", \ - "0.1709378000, 0.1890124000, 0.2294328000, 0.3232832000, 0.5359885000, 1.0147395000, 2.0873117000", \ - "0.2091255000, 0.2264222000, 0.2617065000, 0.3460318000, 0.5445049000, 1.0122054000, 2.0892186000", \ - "0.3091234000, 0.3284366000, 0.3711488000, 0.4583939000, 0.6351666000, 1.0539342000, 2.0886239000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0510397000, 0.0545637000, 0.0623812000, 0.0794912000, 0.1170393000, 0.2003352000, 0.3866129000", \ - "0.0556446000, 0.0592697000, 0.0670036000, 0.0841975000, 0.1217161000, 0.2049999000, 0.3914638000", \ - "0.0652984000, 0.0688370000, 0.0767253000, 0.0939361000, 0.1316042000, 0.2149179000, 0.4012299000", \ - "0.0859078000, 0.0897899000, 0.0982611000, 0.1157469000, 0.1536966000, 0.2374472000, 0.4239434000", \ - "0.1185827000, 0.1239653000, 0.1353538000, 0.1579748000, 0.2017071000, 0.2882436000, 0.4757957000", \ - "0.1579049000, 0.1661323000, 0.1834121000, 0.2176287000, 0.2809472000, 0.3910991000, 0.5934988000", \ - "0.1873168000, 0.2000582000, 0.2270039000, 0.2804391000, 0.3788865000, 0.5456989000, 0.8168026000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.2292560000, 0.2424303000, 0.2745512000, 0.3437736000, 0.5009644000, 0.8529991000, 1.6451660000", \ - "0.2324509000, 0.2465091000, 0.2787289000, 0.3481873000, 0.5052909000, 0.8576409000, 1.6511953000", \ - "0.2439028000, 0.2579226000, 0.2885707000, 0.3596985000, 0.5164634000, 0.8690885000, 1.6613606000", \ - "0.2695069000, 0.2835258000, 0.3139418000, 0.3853373000, 0.5429397000, 0.8959408000, 1.6888773000", \ - "0.3256162000, 0.3398064000, 0.3703896000, 0.4410836000, 0.5986079000, 0.9517799000, 1.7486410000", \ - "0.4453848000, 0.4595453000, 0.4969349000, 0.5708692000, 0.7284331000, 1.0815423000, 1.8755348000", \ - "0.6477434000, 0.6695424000, 0.7168097000, 0.8173363000, 1.0067649000, 1.3827901000, 2.1766069000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0475076000, 0.0516607000, 0.0610251000, 0.0823807000, 0.1308410000, 0.2399434000, 0.4869879000", \ - "0.0474804000, 0.0516507000, 0.0610266000, 0.0823634000, 0.1308136000, 0.2398491000, 0.4869706000", \ - "0.0473547000, 0.0514596000, 0.0609072000, 0.0823338000, 0.1309549000, 0.2399522000, 0.4868532000", \ - "0.0528169000, 0.0564906000, 0.0650545000, 0.0846279000, 0.1313764000, 0.2400024000, 0.4871316000", \ - "0.0745758000, 0.0784325000, 0.0869576000, 0.1055621000, 0.1457799000, 0.2456190000, 0.4872059000", \ - "0.1192734000, 0.1244751000, 0.1356504000, 0.1579653000, 0.2026112000, 0.2929495000, 0.5087051000", \ - "0.1999027000, 0.2080729000, 0.2245882000, 0.2570616000, 0.3177179000, 0.4274134000, 0.6337708000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1901496000, 0.2091710000, 0.2523813000, 0.3473922000, 0.5618860000, 1.0428889000, 2.1249722000", \ - "0.1902273000, 0.2093428000, 0.2519910000, 0.3470323000, 0.5612219000, 1.0427422000, 2.1271276000", \ - "0.1901477000, 0.2090658000, 0.2517654000, 0.3471558000, 0.5610958000, 1.0404950000, 2.1199622000", \ - "0.1906143000, 0.2091304000, 0.2518938000, 0.3470703000, 0.5607079000, 1.0409639000, 2.1244513000", \ - "0.1929113000, 0.2110951000, 0.2528455000, 0.3472134000, 0.5608297000, 1.0410328000, 2.1273534000", \ - "0.2293402000, 0.2453789000, 0.2833962000, 0.3688926000, 0.5708012000, 1.0410925000, 2.1226831000", \ - "0.3274656000, 0.3470500000, 0.3882646000, 0.4784765000, 0.6592472000, 1.0859553000, 2.1237394000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0305462000, 0.0342107000, 0.0415031000, 0.0586551000, 0.0962719000, 0.1808546000, 0.3715769000", \ - "0.0350384000, 0.0384649000, 0.0460794000, 0.0630112000, 0.1008762000, 0.1856872000, 0.3765774000", \ - "0.0454247000, 0.0489124000, 0.0567066000, 0.0739783000, 0.1114680000, 0.1964803000, 0.3874507000", \ - "0.0627674000, 0.0681560000, 0.0788216000, 0.0991636000, 0.1366825000, 0.2215208000, 0.4124368000", \ - "0.0833447000, 0.0913945000, 0.1078962000, 0.1393142000, 0.1914227000, 0.2797608000, 0.4703506000", \ - "0.1008903000, 0.1131436000, 0.1384682000, 0.1865565000, 0.2681148000, 0.3968190000, 0.6038607000", \ - "0.0988907000, 0.1182028000, 0.1574784000, 0.2310262000, 0.3564205000, 0.5562416000, 0.8668194000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1481668000, 0.1622033000, 0.1938223000, 0.2641045000, 0.4210845000, 0.7723211000, 1.5631832000", \ - "0.1505250000, 0.1648395000, 0.1964827000, 0.2673700000, 0.4247921000, 0.7764538000, 1.5676330000", \ - "0.1580359000, 0.1717004000, 0.2039664000, 0.2753140000, 0.4334304000, 0.7863069000, 1.5782891000", \ - "0.1805883000, 0.1944844000, 0.2265146000, 0.2975234000, 0.4558963000, 0.8092768000, 1.6049273000", \ - "0.2422453000, 0.2553174000, 0.2857857000, 0.3554082000, 0.5130255000, 0.8667465000, 1.6602403000", \ - "0.3627308000, 0.3815788000, 0.4200323000, 0.4971406000, 0.6515677000, 1.0024674000, 1.7944977000", \ - "0.5470416000, 0.5746611000, 0.6306639000, 0.7439236000, 0.9567340000, 1.3263990000, 2.1121553000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0404436000, 0.0448254000, 0.0545562000, 0.0766033000, 0.1266999000, 0.2386282000, 0.4923221000", \ - "0.0404750000, 0.0447750000, 0.0545995000, 0.0767315000, 0.1264246000, 0.2387211000, 0.4922455000", \ - "0.0429155000, 0.0465966000, 0.0554488000, 0.0767114000, 0.1263654000, 0.2400718000, 0.4924463000", \ - "0.0587218000, 0.0614510000, 0.0679434000, 0.0847750000, 0.1286327000, 0.2386209000, 0.4927059000", \ - "0.0928322000, 0.0963172000, 0.1042792000, 0.1215754000, 0.1564875000, 0.2491545000, 0.4928106000", \ - "0.1541949000, 0.1596959000, 0.1716955000, 0.1935176000, 0.2387559000, 0.3271044000, 0.5248644000", \ - "0.2651866000, 0.2718537000, 0.2869152000, 0.3205479000, 0.3847567000, 0.5055974000, 0.7082772000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1674580000, 0.1862966000, 0.2286882000, 0.3237317000, 0.5374906000, 1.0110904000, 2.0833530000", \ - "0.1671182000, 0.1860836000, 0.2289584000, 0.3238921000, 0.5372141000, 1.0118657000, 2.0837458000", \ - "0.1666014000, 0.1858636000, 0.2284391000, 0.3231908000, 0.5359216000, 1.0114930000, 2.0861324000", \ - "0.1636332000, 0.1835583000, 0.2270170000, 0.3229825000, 0.5354022000, 1.0120267000, 2.0893778000", \ - "0.1745931000, 0.1912822000, 0.2296804000, 0.3213320000, 0.5348998000, 1.0147110000, 2.0839173000", \ - "0.2327949000, 0.2512385000, 0.2897034000, 0.3652832000, 0.5514081000, 1.0103995000, 2.0828836000", \ - "0.3360023000, 0.3591987000, 0.4100734000, 0.5107781000, 0.6969272000, 1.0848770000, 2.0860293000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0347150000, 0.0383578000, 0.0456915000, 0.0625607000, 0.1001197000, 0.1847732000, 0.3755281000", \ - "0.0391415000, 0.0427004000, 0.0504048000, 0.0671904000, 0.1050125000, 0.1896987000, 0.3804755000", \ - "0.0483485000, 0.0519269000, 0.0597133000, 0.0768624000, 0.1150035000, 0.1997793000, 0.3906124000", \ - "0.0646425000, 0.0691970000, 0.0786890000, 0.0985944000, 0.1368367000, 0.2221629000, 0.4132407000", \ - "0.0849203000, 0.0921926000, 0.1067953000, 0.1337200000, 0.1821291000, 0.2726972000, 0.4647790000", \ - "0.1034216000, 0.1147942000, 0.1377379000, 0.1800748000, 0.2533219000, 0.3718600000, 0.5800939000", \ - "0.1011903000, 0.1199058000, 0.1550800000, 0.2220628000, 0.3365030000, 0.5178400000, 0.7997402000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1748191000, 0.1885293000, 0.2196665000, 0.2897889000, 0.4465178000, 0.7984585000, 1.5904139000", \ - "0.1772610000, 0.1914058000, 0.2233995000, 0.2937620000, 0.4507717000, 0.8025785000, 1.5946128000", \ - "0.1857509000, 0.2003904000, 0.2311199000, 0.3021751000, 0.4597797000, 0.8126322000, 1.6050746000", \ - "0.2093245000, 0.2236758000, 0.2546153000, 0.3257735000, 0.4836531000, 0.8369713000, 1.6312226000", \ - "0.2703105000, 0.2839786000, 0.3151752000, 0.3851112000, 0.5421663000, 0.8955542000, 1.6889216000", \ - "0.4026222000, 0.4195255000, 0.4551321000, 0.5267562000, 0.6820124000, 1.0329372000, 1.8249005000", \ - "0.6099601000, 0.6342963000, 0.6858478000, 0.7914391000, 0.9940642000, 1.3614884000, 2.1398199000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0404994000, 0.0448268000, 0.0545919000, 0.0767126000, 0.1263548000, 0.2387738000, 0.4926093000", \ - "0.0404896000, 0.0448316000, 0.0546337000, 0.0766801000, 0.1264259000, 0.2400059000, 0.4920550000", \ - "0.0417783000, 0.0457431000, 0.0550183000, 0.0767542000, 0.1268014000, 0.2387555000, 0.4924951000", \ - "0.0517571000, 0.0550568000, 0.0625493000, 0.0816788000, 0.1277921000, 0.2387263000, 0.4919971000", \ - "0.0777628000, 0.0810760000, 0.0888241000, 0.1062789000, 0.1458143000, 0.2451398000, 0.4924360000", \ - "0.1288126000, 0.1332071000, 0.1425353000, 0.1632680000, 0.2058059000, 0.2964641000, 0.5149276000", \ - "0.2224628000, 0.2281131000, 0.2408516000, 0.2682962000, 0.3244096000, 0.4295071000, 0.6370537000"); - } - related_pin : "C2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1901869000, 0.2089188000, 0.2520872000, 0.3471085000, 0.5607171000, 1.0408284000, 2.1205120000", \ - "0.1897704000, 0.2091317000, 0.2515561000, 0.3470580000, 0.5629930000, 1.0409494000, 2.1210087000", \ - "0.1896439000, 0.2084545000, 0.2515000000, 0.3469324000, 0.5612152000, 1.0409790000, 2.1209403000", \ - "0.1877877000, 0.2075636000, 0.2507778000, 0.3466721000, 0.5608281000, 1.0408733000, 2.1271118000", \ - "0.1922490000, 0.2100489000, 0.2510100000, 0.3443047000, 0.5603805000, 1.0439044000, 2.1212989000", \ - "0.2490418000, 0.2672620000, 0.3034174000, 0.3822724000, 0.5729547000, 1.0416935000, 2.1198578000", \ - "0.3534276000, 0.3805314000, 0.4264584000, 0.5238086000, 0.7091915000, 1.1090958000, 2.1268902000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22o_1") { - leakage_power () { - value : 0.0032049000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0029598000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0084432000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0031466000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0034788000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0032337000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0084432000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0034205000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0034866000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0032415000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0084432000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0034283000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0031227000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0032003000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0006321000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0031188000; - when : "A1&A2&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a22o"; - cell_leakage_power : 0.0040627470; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046748000, 0.0046798000, 0.0046915000, 0.0046915000, 0.0046915000, 0.0046914000, 0.0046914000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003650100, -0.003651700, -0.003655200, -0.003648500, -0.003633000, -0.003597300, -0.003515000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024340000; - } - pin ("A2") { - capacitance : 0.0023920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022570000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043861000, 0.0043836000, 0.0043777000, 0.0043786000, 0.0043806000, 0.0043853000, 0.0043961000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004376300, -0.004375100, -0.004372500, -0.004372100, -0.004371400, -0.004369700, -0.004365700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025270000; - } - pin ("B1") { - capacitance : 0.0023750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046919000, 0.0046910000, 0.0046890000, 0.0046883000, 0.0046866000, 0.0046828000, 0.0046739000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003839700, -0.003842200, -0.003847900, -0.003841700, -0.003827500, -0.003794700, -0.003719100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025060000; - } - pin ("B2") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040431000, 0.0040422000, 0.0040399000, 0.0040397000, 0.0040391000, 0.0040377000, 0.0040344000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004048200, -0.004045500, -0.004039200, -0.004039600, -0.004040500, -0.004042500, -0.004047300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024870000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0143428000, 0.0134584000, 0.0110747000, 0.0034700000, -0.019016800, -0.079735900, -0.238950600", \ - "0.0142111000, 0.0132961000, 0.0108942000, 0.0032999000, -0.019167800, -0.079892600, -0.239127900", \ - "0.0139504000, 0.0130661000, 0.0106555000, 0.0030615000, -0.019438300, -0.080165200, -0.239393500", \ - "0.0136600000, 0.0127775000, 0.0103793000, 0.0027857000, -0.019727100, -0.080430700, -0.239646300", \ - "0.0134625000, 0.0125871000, 0.0101238000, 0.0025082000, -0.020000500, -0.080664600, -0.239850200", \ - "0.0146885000, 0.0133799000, 0.0099914000, 0.0021917000, -0.020118800, -0.080748000, -0.239913700", \ - "0.0165295000, 0.0151968000, 0.0117899000, 0.0030043000, -0.020120200, -0.080510900, -0.239606600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0147502000, 0.0161516000, 0.0196794000, 0.0285590000, 0.0515775000, 0.1123966000, 0.2705444000", \ - "0.0146136000, 0.0160079000, 0.0195405000, 0.0284368000, 0.0514612000, 0.1117151000, 0.2692233000", \ - "0.0144415000, 0.0158512000, 0.0193905000, 0.0282967000, 0.0513536000, 0.1121629000, 0.2703143000", \ - "0.0142231000, 0.0156283000, 0.0191623000, 0.0280910000, 0.0511686000, 0.1114771000, 0.2702005000", \ - "0.0141862000, 0.0156045000, 0.0191135000, 0.0280354000, 0.0511370000, 0.1114643000, 0.2701403000", \ - "0.0148699000, 0.0161885000, 0.0196232000, 0.0283133000, 0.0515291000, 0.1114054000, 0.2704458000", \ - "0.0162313000, 0.0174194000, 0.0208071000, 0.0297625000, 0.0528175000, 0.1132643000, 0.2693977000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0171250000, 0.0162110000, 0.0137685000, 0.0059686000, -0.016827400, -0.077751300, -0.237095600", \ - "0.0170094000, 0.0160766000, 0.0136506000, 0.0058286000, -0.016956200, -0.077867600, -0.237215100", \ - "0.0168384000, 0.0159076000, 0.0134516000, 0.0056815000, -0.017106300, -0.078053500, -0.237396700", \ - "0.0165934000, 0.0156650000, 0.0132352000, 0.0054432000, -0.017289800, -0.078233000, -0.237557000", \ - "0.0164070000, 0.0154638000, 0.0129970000, 0.0052216000, -0.017490600, -0.078357100, -0.237660600", \ - "0.0165401000, 0.0152033000, 0.0125302000, 0.0051131000, -0.017453100, -0.078247100, -0.237564700", \ - "0.0194770000, 0.0181349000, 0.0146848000, 0.0057683000, -0.017484400, -0.078033900, -0.237285400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0163395000, 0.0177183000, 0.0212054000, 0.0300042000, 0.0528616000, 0.1134075000, 0.2701644000", \ - "0.0162569000, 0.0176294000, 0.0211157000, 0.0299256000, 0.0528087000, 0.1128837000, 0.2715264000", \ - "0.0160946000, 0.0174724000, 0.0209697000, 0.0297770000, 0.0526597000, 0.1127800000, 0.2701089000", \ - "0.0158850000, 0.0172576000, 0.0207427000, 0.0295835000, 0.0527539000, 0.1126817000, 0.2699833000", \ - "0.0156877000, 0.0170669000, 0.0206026000, 0.0294733000, 0.0524999000, 0.1126742000, 0.2700939000", \ - "0.0159621000, 0.0172993000, 0.0207146000, 0.0294086000, 0.0525812000, 0.1129242000, 0.2700146000", \ - "0.0168366000, 0.0180676000, 0.0214472000, 0.0303841000, 0.0536458000, 0.1139274000, 0.2697039000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0116889000, 0.0108345000, 0.0083349000, 0.0005599000, -0.022117600, -0.082931300, -0.242131500", \ - "0.0115220000, 0.0105504000, 0.0081150000, 0.0003436000, -0.022295600, -0.083090900, -0.242353400", \ - "0.0111988000, 0.0103171000, 0.0078416000, 9.780000e-05, -0.022536500, -0.083362300, -0.242610700", \ - "0.0109694000, 0.0100436000, 0.0075815000, -0.000168600, -0.022771600, -0.083592200, -0.242850700", \ - "0.0108613000, 0.0099465000, 0.0074631000, -0.000308500, -0.022952200, -0.083702700, -0.242933200", \ - "0.0131151000, 0.0117892000, 0.0083696000, 0.0001754000, -0.022236200, -0.082961700, -0.242198300", \ - "0.0159734000, 0.0146083000, 0.0108946000, 0.0019775000, -0.021268800, -0.081773600, -0.241041700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0125921000, 0.0140265000, 0.0176689000, 0.0267823000, 0.0502506000, 0.1105686000, 0.2676911000", \ - "0.0125357000, 0.0139724000, 0.0176177000, 0.0267382000, 0.0499942000, 0.1110269000, 0.2681536000", \ - "0.0123586000, 0.0137932000, 0.0174204000, 0.0265280000, 0.0497989000, 0.1108260000, 0.2677829000", \ - "0.0120635000, 0.0134721000, 0.0170448000, 0.0261098000, 0.0494133000, 0.1098285000, 0.2675521000", \ - "0.0119646000, 0.0132905000, 0.0168601000, 0.0258062000, 0.0490862000, 0.1097140000, 0.2677513000", \ - "0.0123779000, 0.0137029000, 0.0171890000, 0.0260198000, 0.0492715000, 0.1093084000, 0.2676658000", \ - "0.0140562000, 0.0152750000, 0.0186256000, 0.0276506000, 0.0508110000, 0.1114933000, 0.2677833000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0144695000, 0.0135528000, 0.0111065000, 0.0033690000, -0.019249900, -0.080015200, -0.239213400", \ - "0.0143693000, 0.0134328000, 0.0109814000, 0.0032504000, -0.019395700, -0.080128600, -0.239353600", \ - "0.0141293000, 0.0132319000, 0.0107504000, 0.0030460000, -0.019573400, -0.080312900, -0.239528500", \ - "0.0140097000, 0.0130809000, 0.0106269000, 0.0029173000, -0.019689400, -0.080407300, -0.239620800", \ - "0.0139110000, 0.0129913000, 0.0105182000, 0.0027991000, -0.019805400, -0.080489400, -0.239694000", \ - "0.0152766000, 0.0139506000, 0.0104888000, 0.0030233000, -0.019470500, -0.080159100, -0.239333300", \ - "0.0192735000, 0.0178944000, 0.0144197000, 0.0054492000, -0.017864300, -0.078389800, -0.237609600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0129036000, 0.0143457000, 0.0179808000, 0.0271087000, 0.0503650000, 0.1114056000, 0.2684366000", \ - "0.0128604000, 0.0142979000, 0.0179401000, 0.0270612000, 0.0503118000, 0.1108813000, 0.2692660000", \ - "0.0126686000, 0.0141018000, 0.0177374000, 0.0268543000, 0.0503406000, 0.1106460000, 0.2676530000", \ - "0.0123616000, 0.0137792000, 0.0173750000, 0.0264553000, 0.0497745000, 0.1108631000, 0.2677319000", \ - "0.0121497000, 0.0134875000, 0.0170703000, 0.0260654000, 0.0493393000, 0.1104575000, 0.2676820000", \ - "0.0124276000, 0.0137493000, 0.0172602000, 0.0260988000, 0.0493562000, 0.1100157000, 0.2675923000", \ - "0.0135011000, 0.0147541000, 0.0181597000, 0.0271883000, 0.0504091000, 0.1110948000, 0.2674000000"); - } - } - max_capacitance : 0.1593120000; - max_transition : 1.5047820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1695021000, 0.1769289000, 0.1922991000, 0.2217916000, 0.2806262000, 0.4101679000, 0.7341606000", \ - "0.1742285000, 0.1816289000, 0.1969741000, 0.2268700000, 0.2853671000, 0.4148178000, 0.7383320000", \ - "0.1858878000, 0.1933385000, 0.2086375000, 0.2383498000, 0.2971011000, 0.4265728000, 0.7501821000", \ - "0.2121395000, 0.2195533000, 0.2347127000, 0.2644920000, 0.3233604000, 0.4529685000, 0.7769334000", \ - "0.2687924000, 0.2760595000, 0.2913440000, 0.3212131000, 0.3800038000, 0.5097051000, 0.8339090000", \ - "0.3731247000, 0.3815356000, 0.3986679000, 0.4311958000, 0.4934145000, 0.6251815000, 0.9491741000", \ - "0.5419592000, 0.5522599000, 0.5732764000, 0.6115721000, 0.6810901000, 0.8188723000, 1.1452714000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0898781000, 0.0976838000, 0.1148350000, 0.1531252000, 0.2475561000, 0.4937036000, 1.1370700000", \ - "0.0939577000, 0.1017403000, 0.1189156000, 0.1572496000, 0.2520101000, 0.4976549000, 1.1399418000", \ - "0.1040172000, 0.1118349000, 0.1290166000, 0.1674267000, 0.2619220000, 0.5080119000, 1.1512453000", \ - "0.1285707000, 0.1363715000, 0.1535559000, 0.1919956000, 0.2866131000, 0.5320781000, 1.1749983000", \ - "0.1699456000, 0.1783458000, 0.1962944000, 0.2355872000, 0.3306690000, 0.5762369000, 1.2196606000", \ - "0.2217406000, 0.2319296000, 0.2521555000, 0.2932171000, 0.3889459000, 0.6348175000, 1.2776150000", \ - "0.2685510000, 0.2818219000, 0.3076855000, 0.3542203000, 0.4513774000, 0.6975336000, 1.3388042000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0266949000, 0.0315816000, 0.0430683000, 0.0686346000, 0.1278684000, 0.2834925000, 0.7132379000", \ - "0.0266365000, 0.0316123000, 0.0434281000, 0.0683682000, 0.1276568000, 0.2836874000, 0.7108892000", \ - "0.0268450000, 0.0317367000, 0.0430554000, 0.0686520000, 0.1276755000, 0.2836968000, 0.7108185000", \ - "0.0267399000, 0.0315611000, 0.0432894000, 0.0687040000, 0.1280437000, 0.2831243000, 0.7135590000", \ - "0.0269572000, 0.0322037000, 0.0433822000, 0.0688218000, 0.1278957000, 0.2837633000, 0.7131513000", \ - "0.0324255000, 0.0377788000, 0.0501603000, 0.0746543000, 0.1327130000, 0.2859087000, 0.7162891000", \ - "0.0440194000, 0.0499269000, 0.0626948000, 0.0896693000, 0.1476377000, 0.2958209000, 0.7105967000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0271754000, 0.0342739000, 0.0524220000, 0.1005958000, 0.2322199000, 0.5837557000, 1.5019874000", \ - "0.0271874000, 0.0343202000, 0.0523119000, 0.1004130000, 0.2325564000, 0.5837252000, 1.5005442000", \ - "0.0271496000, 0.0342752000, 0.0523874000, 0.1005265000, 0.2322910000, 0.5836682000, 1.5021653000", \ - "0.0271135000, 0.0342003000, 0.0523475000, 0.1004754000, 0.2324147000, 0.5828467000, 1.5019479000", \ - "0.0308940000, 0.0375478000, 0.0548202000, 0.1019649000, 0.2326498000, 0.5834187000, 1.5023044000", \ - "0.0395797000, 0.0457121000, 0.0615751000, 0.1055123000, 0.2336035000, 0.5816853000, 1.5010584000", \ - "0.0542306000, 0.0611997000, 0.0769084000, 0.1167111000, 0.2370272000, 0.5854333000, 1.4967455000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1893934000, 0.1968596000, 0.2122836000, 0.2420809000, 0.3005215000, 0.4298290000, 0.7533002000", \ - "0.1943909000, 0.2018919000, 0.2173421000, 0.2470763000, 0.3055592000, 0.4348592000, 0.7583146000", \ - "0.2070075000, 0.2145246000, 0.2299306000, 0.2596880000, 0.3182682000, 0.4476388000, 0.7710047000", \ - "0.2350221000, 0.2424977000, 0.2579212000, 0.2876652000, 0.3461030000, 0.4754233000, 0.7992492000", \ - "0.2955147000, 0.3030421000, 0.3184587000, 0.3482808000, 0.4070297000, 0.5363354000, 0.8605393000", \ - "0.4154076000, 0.4237758000, 0.4406882000, 0.4726723000, 0.5338482000, 0.6649198000, 0.9886278000", \ - "0.6193528000, 0.6296411000, 0.6501418000, 0.6875270000, 0.7557343000, 0.8924106000, 1.2184773000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0975127000, 0.1045962000, 0.1206820000, 0.1578147000, 0.2514599000, 0.4975653000, 1.1382711000", \ - "0.1018560000, 0.1089698000, 0.1250483000, 0.1621793000, 0.2557301000, 0.5006049000, 1.1433293000", \ - "0.1109645000, 0.1180852000, 0.1341465000, 0.1713077000, 0.2652980000, 0.5103198000, 1.1520970000", \ - "0.1314434000, 0.1385269000, 0.1545446000, 0.1918434000, 0.2861302000, 0.5312900000, 1.1724524000", \ - "0.1694800000, 0.1770181000, 0.1936760000, 0.2316820000, 0.3262390000, 0.5715730000, 1.2123194000", \ - "0.2205009000, 0.2291075000, 0.2473030000, 0.2864332000, 0.3813279000, 0.6269517000, 1.2692619000", \ - "0.2663358000, 0.2772975000, 0.2992213000, 0.3416571000, 0.4371655000, 0.6834971000, 1.3237899000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0284916000, 0.0333411000, 0.0449736000, 0.0698435000, 0.1288313000, 0.2843825000, 0.7113461000", \ - "0.0282864000, 0.0331924000, 0.0449231000, 0.0695518000, 0.1288725000, 0.2843380000, 0.7114838000", \ - "0.0281527000, 0.0331941000, 0.0445913000, 0.0699348000, 0.1288009000, 0.2843702000, 0.7113252000", \ - "0.0283670000, 0.0332419000, 0.0449574000, 0.0694191000, 0.1290994000, 0.2841101000, 0.7146127000", \ - "0.0286164000, 0.0331657000, 0.0446270000, 0.0695094000, 0.1288523000, 0.2842164000, 0.7096273000", \ - "0.0330663000, 0.0382949000, 0.0496836000, 0.0748468000, 0.1325618000, 0.2860576000, 0.7115595000", \ - "0.0438223000, 0.0498560000, 0.0620502000, 0.0883844000, 0.1462250000, 0.2945229000, 0.7110780000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0245572000, 0.0317433000, 0.0501357000, 0.0992450000, 0.2322019000, 0.5831856000, 1.5016850000", \ - "0.0246164000, 0.0317943000, 0.0501439000, 0.0991926000, 0.2323584000, 0.5834236000, 1.5022928000", \ - "0.0245038000, 0.0317194000, 0.0501083000, 0.0993256000, 0.2326195000, 0.5838449000, 1.4993148000", \ - "0.0246945000, 0.0317957000, 0.0499924000, 0.0993126000, 0.2321514000, 0.5832897000, 1.4966267000", \ - "0.0266999000, 0.0336952000, 0.0516621000, 0.0999624000, 0.2325133000, 0.5818181000, 1.4996687000", \ - "0.0316431000, 0.0388663000, 0.0557735000, 0.1021951000, 0.2331248000, 0.5815277000, 1.4994213000", \ - "0.0422534000, 0.0495336000, 0.0658402000, 0.1087445000, 0.2347868000, 0.5851632000, 1.4967447000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1451744000, 0.1525065000, 0.1677771000, 0.1974039000, 0.2559516000, 0.3854163000, 0.7092592000", \ - "0.1485482000, 0.1559701000, 0.1712227000, 0.2007202000, 0.2593465000, 0.3887313000, 0.7124695000", \ - "0.1579404000, 0.1653366000, 0.1802846000, 0.2099949000, 0.2686327000, 0.3982248000, 0.7216799000", \ - "0.1837670000, 0.1911553000, 0.2064460000, 0.2360802000, 0.2947634000, 0.4243046000, 0.7480098000", \ - "0.2475675000, 0.2549814000, 0.2701787000, 0.2998410000, 0.3586113000, 0.4882537000, 0.8121071000", \ - "0.3602230000, 0.3691533000, 0.3869649000, 0.4192256000, 0.4809932000, 0.6130910000, 0.9370292000", \ - "0.5315697000, 0.5431163000, 0.5652266000, 0.6046560000, 0.6721892000, 0.8060346000, 1.1328753000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0788010000, 0.0866264000, 0.1040243000, 0.1428493000, 0.2383187000, 0.4839187000, 1.1367418000", \ - "0.0832642000, 0.0910778000, 0.1084911000, 0.1474229000, 0.2428621000, 0.4897525000, 1.1302472000", \ - "0.0935024000, 0.1013587000, 0.1186592000, 0.1575562000, 0.2529823000, 0.5001279000, 1.1414626000", \ - "0.1164968000, 0.1243312000, 0.1416254000, 0.1804217000, 0.2756259000, 0.5247986000, 1.1655392000", \ - "0.1514752000, 0.1601349000, 0.1784777000, 0.2182781000, 0.3141482000, 0.5602485000, 1.2022142000", \ - "0.1923943000, 0.2033567000, 0.2246253000, 0.2666540000, 0.3629433000, 0.6098574000, 1.2517467000", \ - "0.2237880000, 0.2382372000, 0.2659039000, 0.3154067000, 0.4135612000, 0.6600794000, 1.3026160000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0270614000, 0.0325689000, 0.0435196000, 0.0687524000, 0.1283198000, 0.2841291000, 0.7135690000", \ - "0.0272300000, 0.0319809000, 0.0435548000, 0.0687594000, 0.1280946000, 0.2836506000, 0.7111178000", \ - "0.0271165000, 0.0320721000, 0.0438623000, 0.0691280000, 0.1283890000, 0.2837862000, 0.7110358000", \ - "0.0269793000, 0.0319921000, 0.0435830000, 0.0687617000, 0.1281075000, 0.2833759000, 0.7164021000", \ - "0.0276850000, 0.0330273000, 0.0438957000, 0.0695749000, 0.1284354000, 0.2834795000, 0.7160212000", \ - "0.0371730000, 0.0422526000, 0.0527333000, 0.0770380000, 0.1338954000, 0.2870784000, 0.7112748000", \ - "0.0521547000, 0.0586136000, 0.0711200000, 0.0938003000, 0.1472562000, 0.2947428000, 0.7122072000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0258912000, 0.0328865000, 0.0508658000, 0.0992172000, 0.2318279000, 0.5838255000, 1.5019773000", \ - "0.0258892000, 0.0329498000, 0.0508663000, 0.0990998000, 0.2316107000, 0.5848977000, 1.5047822000", \ - "0.0258189000, 0.0328731000, 0.0508329000, 0.0992404000, 0.2316614000, 0.5846416000, 1.4958637000", \ - "0.0267028000, 0.0335955000, 0.0514679000, 0.0993104000, 0.2315573000, 0.5844382000, 1.5010218000", \ - "0.0317894000, 0.0381331000, 0.0551019000, 0.1016834000, 0.2321644000, 0.5823705000, 1.5009471000", \ - "0.0423529000, 0.0484424000, 0.0639210000, 0.1064910000, 0.2341281000, 0.5819562000, 1.4990169000", \ - "0.0587370000, 0.0663206000, 0.0822451000, 0.1210265000, 0.2381746000, 0.5852077000, 1.4961364000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1620750000, 0.1695908000, 0.1850384000, 0.2149156000, 0.2738526000, 0.4036166000, 0.7272526000", \ - "0.1657842000, 0.1733188000, 0.1887874000, 0.2186385000, 0.2775422000, 0.4073283000, 0.7310972000", \ - "0.1758301000, 0.1833670000, 0.1988086000, 0.2287418000, 0.2877142000, 0.4174434000, 0.7410901000", \ - "0.2024308000, 0.2099406000, 0.2254343000, 0.2552640000, 0.3142409000, 0.4440019000, 0.7678222000", \ - "0.2674677000, 0.2749804000, 0.2903142000, 0.3201719000, 0.3790013000, 0.5087370000, 0.8328700000", \ - "0.3910046000, 0.3998592000, 0.4173245000, 0.4492383000, 0.5103286000, 0.6419467000, 0.9664956000", \ - "0.5790353000, 0.5907337000, 0.6134400000, 0.6519089000, 0.7184439000, 0.8527021000, 1.1792530000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0829781000, 0.0908598000, 0.1082169000, 0.1471420000, 0.2425574000, 0.4890367000, 1.1293607000", \ - "0.0875777000, 0.0954001000, 0.1128083000, 0.1516858000, 0.2471148000, 0.4926393000, 1.1413774000", \ - "0.0969963000, 0.1048049000, 0.1221205000, 0.1610398000, 0.2566075000, 0.5022886000, 1.1540163000", \ - "0.1170463000, 0.1249178000, 0.1422301000, 0.1810732000, 0.2763554000, 0.5232306000, 1.1647169000", \ - "0.1506041000, 0.1591905000, 0.1775176000, 0.2172589000, 0.3131292000, 0.5606555000, 1.2006623000", \ - "0.1935066000, 0.2038711000, 0.2247595000, 0.2666317000, 0.3628240000, 0.6093535000, 1.2543830000", \ - "0.2296202000, 0.2432799000, 0.2700846000, 0.3183746000, 0.4170493000, 0.6640418000, 1.3055876000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0285578000, 0.0331770000, 0.0445820000, 0.0698696000, 0.1286205000, 0.2842082000, 0.7113242000", \ - "0.0286995000, 0.0333510000, 0.0445624000, 0.0699595000, 0.1288702000, 0.2835462000, 0.7158554000", \ - "0.0285126000, 0.0332777000, 0.0445048000, 0.0697607000, 0.1284849000, 0.2842705000, 0.7112897000", \ - "0.0283594000, 0.0333057000, 0.0447579000, 0.0697270000, 0.1285582000, 0.2842439000, 0.7113095000", \ - "0.0281436000, 0.0337090000, 0.0445680000, 0.0698738000, 0.1288084000, 0.2840055000, 0.7114911000", \ - "0.0373503000, 0.0419958000, 0.0521032000, 0.0762315000, 0.1333531000, 0.2864542000, 0.7122832000", \ - "0.0530547000, 0.0589688000, 0.0701943000, 0.0926039000, 0.1457647000, 0.2931985000, 0.7116149000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0258041000, 0.0328586000, 0.0508259000, 0.0992044000, 0.2316758000, 0.5847494000, 1.4991551000", \ - "0.0258695000, 0.0329516000, 0.0508084000, 0.0993177000, 0.2316638000, 0.5841648000, 1.5034635000", \ - "0.0259068000, 0.0329807000, 0.0508677000, 0.0991702000, 0.2317022000, 0.5834471000, 1.5045246000", \ - "0.0263738000, 0.0333612000, 0.0512958000, 0.0993031000, 0.2316435000, 0.5845912000, 1.4971869000", \ - "0.0303724000, 0.0371072000, 0.0543450000, 0.1009665000, 0.2315400000, 0.5840221000, 1.4997442000", \ - "0.0389224000, 0.0452706000, 0.0618744000, 0.1055850000, 0.2333818000, 0.5814713000, 1.4973509000", \ - "0.0545014000, 0.0618014000, 0.0781502000, 0.1185821000, 0.2375946000, 0.5837605000, 1.4942778000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22o_2") { - leakage_power () { - value : 0.0037702000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0035251000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0087179000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0037119000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0040542000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0038090000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0087178000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0039958000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0040780000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0038329000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0087178000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0040197000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0030896000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0031547000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0010404000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0030896000; - when : "A1&A2&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a22o"; - cell_leakage_power : 0.0044577760; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047169000, 0.0047173000, 0.0047184000, 0.0047206000, 0.0047256000, 0.0047371000, 0.0047637000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003712300, -0.003713300, -0.003715600, -0.003708700, -0.003692800, -0.003656300, -0.003572000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024280000; - } - pin ("A2") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043539000, 0.0043553000, 0.0043585000, 0.0043576000, 0.0043557000, 0.0043514000, 0.0043413000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004350200, -0.004348500, -0.004344700, -0.004344400, -0.004343600, -0.004341800, -0.004337600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025170000; - } - pin ("B1") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047291000, 0.0047283000, 0.0047266000, 0.0047257000, 0.0047238000, 0.0047194000, 0.0047092000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003874000, -0.003877200, -0.003884600, -0.003878600, -0.003864500, -0.003832200, -0.003757700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025060000; - } - pin ("B2") { - capacitance : 0.0023200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040774000, 0.0040756000, 0.0040717000, 0.0040714000, 0.0040707000, 0.0040692000, 0.0040657000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004080700, -0.004079400, -0.004076400, -0.004076600, -0.004077100, -0.004078300, -0.004081100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024950000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0174882000, 0.0160417000, 0.0125030000, 0.0017206000, -0.033989700, -0.143226000, -0.463066200", \ - "0.0174390000, 0.0160001000, 0.0124531000, 0.0016344000, -0.034069400, -0.143425500, -0.463219800", \ - "0.0171382000, 0.0157357000, 0.0122809000, 0.0013621000, -0.034312600, -0.143579500, -0.463457800", \ - "0.0168401000, 0.0153920000, 0.0118650000, 0.0010598000, -0.034673200, -0.143946900, -0.463728500", \ - "0.0165908000, 0.0151530000, 0.0116091000, 0.0007611000, -0.034965500, -0.144230400, -0.463999400", \ - "0.0166192000, 0.0149938000, 0.0112105000, 0.0006060000, -0.035148500, -0.144366600, -0.464077900", \ - "0.0219389000, 0.0202413000, 0.0156000000, 0.0025506000, -0.035087200, -0.144296300, -0.463909400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0199169000, 0.0215753000, 0.0263408000, 0.0395792000, 0.0771717000, 0.1861663000, 0.5021155000", \ - "0.0198108000, 0.0214534000, 0.0262114000, 0.0395135000, 0.0770740000, 0.1860269000, 0.5017455000", \ - "0.0196705000, 0.0213110000, 0.0260741000, 0.0393731000, 0.0768873000, 0.1859052000, 0.5016236000", \ - "0.0194589000, 0.0211031000, 0.0258608000, 0.0391431000, 0.0767218000, 0.1856246000, 0.5018147000", \ - "0.0195126000, 0.0211268000, 0.0258207000, 0.0390100000, 0.0766408000, 0.1865833000, 0.5041183000", \ - "0.0202169000, 0.0217338000, 0.0262400000, 0.0390523000, 0.0766562000, 0.1852867000, 0.5041389000", \ - "0.0219068000, 0.0233694000, 0.0277214000, 0.0407778000, 0.0783011000, 0.1872766000, 0.5038507000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0202682000, 0.0188312000, 0.0152175000, 0.0044210000, -0.031575900, -0.141249300, -0.461239700", \ - "0.0201574000, 0.0187145000, 0.0151653000, 0.0042003000, -0.031733500, -0.141281900, -0.461250100", \ - "0.0199954000, 0.0185275000, 0.0149189000, 0.0040141000, -0.031875900, -0.141541200, -0.461393800", \ - "0.0198399000, 0.0183834000, 0.0147956000, 0.0038191000, -0.032165400, -0.141736700, -0.461706300", \ - "0.0195439000, 0.0180962000, 0.0144998000, 0.0035407000, -0.032399000, -0.141918600, -0.461821700", \ - "0.0193663000, 0.0178591000, 0.0145516000, 0.0035035000, -0.032426100, -0.141894700, -0.461782500", \ - "0.0252251000, 0.0235330000, 0.0188555000, 0.0056872000, -0.032191800, -0.141694800, -0.461525000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0215606000, 0.0231892000, 0.0278312000, 0.0410016000, 0.0784857000, 0.1873511000, 0.5037146000", \ - "0.0214164000, 0.0230536000, 0.0277030000, 0.0408940000, 0.0783948000, 0.1871705000, 0.5033316000", \ - "0.0213144000, 0.0229546000, 0.0276770000, 0.0407838000, 0.0782459000, 0.1870799000, 0.5032325000", \ - "0.0211260000, 0.0227642000, 0.0274711000, 0.0406617000, 0.0781445000, 0.1868317000, 0.5029393000", \ - "0.0208658000, 0.0225292000, 0.0271921000, 0.0402833000, 0.0778630000, 0.1870441000, 0.5033794000", \ - "0.0214143000, 0.0229533000, 0.0274975000, 0.0404369000, 0.0780486000, 0.1862726000, 0.5031260000", \ - "0.0223108000, 0.0238145000, 0.0282303000, 0.0412626000, 0.0789041000, 0.1881372000, 0.5037813000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0147663000, 0.0133332000, 0.0097720000, -0.001175100, -0.037097500, -0.146485700, -0.466389600", \ - "0.0146691000, 0.0132492000, 0.0096609000, -0.001280900, -0.037178900, -0.146638000, -0.466510600", \ - "0.0143678000, 0.0129469000, 0.0093641000, -0.001581600, -0.037456400, -0.146875400, -0.466774900", \ - "0.0141226000, 0.0126718000, 0.0091179000, -0.001809000, -0.037677100, -0.147135700, -0.467041400", \ - "0.0139863000, 0.0125463000, 0.0089224000, -0.001733100, -0.037753800, -0.147214100, -0.467106900", \ - "0.0147319000, 0.0130392000, 0.0088295000, -0.001957100, -0.037806500, -0.147141500, -0.466904600", \ - "0.0212527000, 0.0194670000, 0.0146488000, 0.0014524000, -0.036397500, -0.145632800, -0.465535600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0178432000, 0.0195417000, 0.0243977000, 0.0379030000, 0.0758595000, 0.1851680000, 0.4994124000", \ - "0.0178410000, 0.0195410000, 0.0243849000, 0.0378973000, 0.0758580000, 0.1850605000, 0.5045968000", \ - "0.0177007000, 0.0193993000, 0.0242527000, 0.0377428000, 0.0757241000, 0.1849662000, 0.5004755000", \ - "0.0175258000, 0.0191841000, 0.0239504000, 0.0373568000, 0.0753277000, 0.1847751000, 0.5020419000", \ - "0.0173432000, 0.0189949000, 0.0237121000, 0.0369214000, 0.0747755000, 0.1852073000, 0.5012218000", \ - "0.0182353000, 0.0197478000, 0.0242566000, 0.0373061000, 0.0749899000, 0.1837189000, 0.5013351000", \ - "0.0198653000, 0.0213394000, 0.0256290000, 0.0389151000, 0.0764961000, 0.1858218000, 0.5007174000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0175604000, 0.0161568000, 0.0125472000, 0.0015972000, -0.034253900, -0.143637600, -0.463452300", \ - "0.0174773000, 0.0160486000, 0.0124421000, 0.0014646000, -0.034345100, -0.143725700, -0.463550300", \ - "0.0172840000, 0.0158283000, 0.0122207000, 0.0013754000, -0.034515300, -0.143863400, -0.463636600", \ - "0.0171596000, 0.0156983000, 0.0120897000, 0.0012118000, -0.034625200, -0.144007200, -0.463884200", \ - "0.0172163000, 0.0157327000, 0.0121314000, 0.0010857000, -0.034768300, -0.144129000, -0.463939900", \ - "0.0173572000, 0.0159114000, 0.0121547000, 0.0012554000, -0.034651300, -0.143978000, -0.463703500", \ - "0.0246272000, 0.0228504000, 0.0180375000, 0.0047805000, -0.033143900, -0.142258700, -0.462146400"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0181652000, 0.0198586000, 0.0246966000, 0.0382176000, 0.0761908000, 0.1855560000, 0.5026898000", \ - "0.0181442000, 0.0198384000, 0.0247101000, 0.0382283000, 0.0761927000, 0.1854104000, 0.4997745000", \ - "0.0180237000, 0.0197169000, 0.0245683000, 0.0381045000, 0.0760633000, 0.1853620000, 0.5049487000", \ - "0.0177745000, 0.0194499000, 0.0242500000, 0.0376906000, 0.0756554000, 0.1851178000, 0.5002191000", \ - "0.0175334000, 0.0191723000, 0.0239351000, 0.0372467000, 0.0752677000, 0.1854530000, 0.4993143000", \ - "0.0180765000, 0.0196107000, 0.0242227000, 0.0373158000, 0.0750921000, 0.1833653000, 0.5010710000", \ - "0.0194368000, 0.0208885000, 0.0253151000, 0.0385116000, 0.0762548000, 0.1856138000, 0.4999127000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5071530000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1999927000, 0.2064789000, 0.2209400000, 0.2499710000, 0.3062150000, 0.4291194000, 0.7488590000", \ - "0.2049276000, 0.2114044000, 0.2259717000, 0.2548385000, 0.3116297000, 0.4345568000, 0.7542277000", \ - "0.2168904000, 0.2233875000, 0.2378319000, 0.2667614000, 0.3235856000, 0.4461458000, 0.7659969000", \ - "0.2432949000, 0.2497625000, 0.2642010000, 0.2932192000, 0.3495679000, 0.4726360000, 0.7922383000", \ - "0.3006987000, 0.3071312000, 0.3216166000, 0.3505869000, 0.4073231000, 0.5302953000, 0.8496856000", \ - "0.4160632000, 0.4231838000, 0.4389856000, 0.4700881000, 0.5294217000, 0.6536448000, 0.9732272000", \ - "0.6085173000, 0.6170326000, 0.6362547000, 0.6726923000, 0.7400192000, 0.8731577000, 1.1973706000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0996642000, 0.1060833000, 0.1208656000, 0.1541568000, 0.2369780000, 0.4717516000, 1.1473313000", \ - "0.1037761000, 0.1101571000, 0.1249659000, 0.1583387000, 0.2412694000, 0.4752597000, 1.1516214000", \ - "0.1138500000, 0.1202201000, 0.1350407000, 0.1684025000, 0.2513456000, 0.4849232000, 1.1617228000", \ - "0.1384948000, 0.1448674000, 0.1596337000, 0.1929499000, 0.2759416000, 0.5099262000, 1.1871405000", \ - "0.1851514000, 0.1920904000, 0.2076152000, 0.2416913000, 0.3250447000, 0.5593248000, 1.2386661000", \ - "0.2460191000, 0.2545364000, 0.2730738000, 0.3100237000, 0.3947529000, 0.6289920000, 1.3082225000", \ - "0.3053019000, 0.3164053000, 0.3403315000, 0.3854542000, 0.4744111000, 0.7087797000, 1.3855967000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0293029000, 0.0333958000, 0.0429420000, 0.0632778000, 0.1137920000, 0.2503609000, 0.6674249000", \ - "0.0291811000, 0.0332186000, 0.0428842000, 0.0631821000, 0.1137213000, 0.2500145000, 0.6686193000", \ - "0.0291737000, 0.0334602000, 0.0428360000, 0.0639193000, 0.1135063000, 0.2504063000, 0.6684613000", \ - "0.0293766000, 0.0335194000, 0.0430680000, 0.0632250000, 0.1137647000, 0.2502361000, 0.6687473000", \ - "0.0293085000, 0.0335656000, 0.0428676000, 0.0633969000, 0.1134430000, 0.2502580000, 0.6689370000", \ - "0.0343035000, 0.0386789000, 0.0479182000, 0.0697075000, 0.1173927000, 0.2526620000, 0.6697010000", \ - "0.0460125000, 0.0503546000, 0.0610610000, 0.0835942000, 0.1343136000, 0.2655048000, 0.6696860000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0248481000, 0.0296924000, 0.0428468000, 0.0793252000, 0.1902242000, 0.5245882000, 1.4967940000", \ - "0.0247067000, 0.0297675000, 0.0428571000, 0.0794550000, 0.1900120000, 0.5246996000, 1.4979699000", \ - "0.0248377000, 0.0297257000, 0.0428424000, 0.0794444000, 0.1901204000, 0.5238351000, 1.4979684000", \ - "0.0248000000, 0.0297028000, 0.0428205000, 0.0793762000, 0.1898024000, 0.5242339000, 1.4995211000", \ - "0.0283998000, 0.0331473000, 0.0457049000, 0.0810760000, 0.1904781000, 0.5257083000, 1.5026725000", \ - "0.0378019000, 0.0422745000, 0.0546396000, 0.0873086000, 0.1934812000, 0.5244698000, 1.5029342000", \ - "0.0518886000, 0.0581216000, 0.0721092000, 0.1037575000, 0.1994158000, 0.5257629000, 1.4944743000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2196925000, 0.2264166000, 0.2412643000, 0.2703001000, 0.3270068000, 0.4503838000, 0.7698357000", \ - "0.2249072000, 0.2316301000, 0.2464847000, 0.2758638000, 0.3322772000, 0.4554173000, 0.7753963000", \ - "0.2378419000, 0.2445477000, 0.2593742000, 0.2887738000, 0.3452238000, 0.4686384000, 0.7883693000", \ - "0.2663599000, 0.2730876000, 0.2879836000, 0.3171872000, 0.3742445000, 0.4973956000, 0.8172351000", \ - "0.3283463000, 0.3350606000, 0.3498631000, 0.3791302000, 0.4362365000, 0.5593657000, 0.8793078000", \ - "0.4584136000, 0.4656611000, 0.4822113000, 0.5130489000, 0.5715601000, 0.6957790000, 1.0158354000", \ - "0.6869799000, 0.6957795000, 0.7147798000, 0.7511295000, 0.8172745000, 0.9493248000, 1.2724121000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1077862000, 0.1136229000, 0.1274310000, 0.1593604000, 0.2411863000, 0.4747462000, 1.1519669000", \ - "0.1120472000, 0.1179078000, 0.1316815000, 0.1636583000, 0.2454396000, 0.4791079000, 1.1563291000", \ - "0.1211897000, 0.1270861000, 0.1408428000, 0.1727884000, 0.2546281000, 0.4893353000, 1.1645550000", \ - "0.1418521000, 0.1476714000, 0.1614593000, 0.1933685000, 0.2754165000, 0.5083498000, 1.1846397000", \ - "0.1822349000, 0.1884461000, 0.2025614000, 0.2353376000, 0.3176913000, 0.5512577000, 1.2287453000", \ - "0.2395063000, 0.2466700000, 0.2627170000, 0.2974369000, 0.3807930000, 0.6145843000, 1.2929185000", \ - "0.2950438000, 0.3044899000, 0.3249371000, 0.3642536000, 0.4505183000, 0.6854545000, 1.3610811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0311866000, 0.0353575000, 0.0447347000, 0.0653202000, 0.1152087000, 0.2513059000, 0.6692149000", \ - "0.0312958000, 0.0355408000, 0.0442744000, 0.0648955000, 0.1154361000, 0.2511243000, 0.6679605000", \ - "0.0312502000, 0.0355260000, 0.0441260000, 0.0649535000, 0.1150839000, 0.2512717000, 0.6681129000", \ - "0.0310405000, 0.0350995000, 0.0449127000, 0.0647508000, 0.1148834000, 0.2510409000, 0.6690745000", \ - "0.0312500000, 0.0354664000, 0.0442885000, 0.0647761000, 0.1148696000, 0.2512724000, 0.6686485000", \ - "0.0354180000, 0.0391418000, 0.0487046000, 0.0689863000, 0.1174787000, 0.2520786000, 0.6692008000", \ - "0.0467134000, 0.0509361000, 0.0616950000, 0.0832734000, 0.1330238000, 0.2644257000, 0.6713408000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0222921000, 0.0272939000, 0.0405507000, 0.0775055000, 0.1896800000, 0.5253555000, 1.5019940000", \ - "0.0222791000, 0.0272337000, 0.0405824000, 0.0775367000, 0.1896136000, 0.5250091000, 1.5009399000", \ - "0.0222957000, 0.0272878000, 0.0404930000, 0.0774761000, 0.1896422000, 0.5246482000, 1.4989963000", \ - "0.0223596000, 0.0273518000, 0.0404130000, 0.0774594000, 0.1891736000, 0.5249053000, 1.4963530000", \ - "0.0242513000, 0.0291583000, 0.0426615000, 0.0788773000, 0.1899022000, 0.5254732000, 1.5018795000", \ - "0.0296298000, 0.0346639000, 0.0479442000, 0.0828520000, 0.1916790000, 0.5243804000, 1.5015568000", \ - "0.0407025000, 0.0466362000, 0.0600941000, 0.0930744000, 0.1955565000, 0.5258675000, 1.4982735000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1767070000, 0.1832373000, 0.1977802000, 0.2268886000, 0.2839394000, 0.4072315000, 0.7271403000", \ - "0.1801842000, 0.1867455000, 0.2013390000, 0.2304305000, 0.2875272000, 0.4108532000, 0.7307252000", \ - "0.1895163000, 0.1959966000, 0.2105233000, 0.2396557000, 0.2968090000, 0.4201000000, 0.7400026000", \ - "0.2152091000, 0.2217376000, 0.2363376000, 0.2653808000, 0.3222366000, 0.4456649000, 0.7654058000", \ - "0.2789960000, 0.2855018000, 0.2999601000, 0.3289191000, 0.3857457000, 0.5093481000, 0.8292710000", \ - "0.4065946000, 0.4141761000, 0.4308619000, 0.4625778000, 0.5223620000, 0.6477599000, 0.9677421000", \ - "0.6015430000, 0.6111840000, 0.6324248000, 0.6729054000, 0.7420360000, 0.8729674000, 1.1969964000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0890351000, 0.0953799000, 0.1101519000, 0.1437062000, 0.2269122000, 0.4613986000, 1.1387250000", \ - "0.0934614000, 0.0998041000, 0.1146121000, 0.1481208000, 0.2315082000, 0.4656710000, 1.1455411000", \ - "0.1040100000, 0.1103713000, 0.1251240000, 0.1585759000, 0.2418277000, 0.4768491000, 1.1635976000", \ - "0.1283069000, 0.1346037000, 0.1492562000, 0.1826123000, 0.2658669000, 0.5000786000, 1.1778890000", \ - "0.1704938000, 0.1775741000, 0.1934118000, 0.2279599000, 0.3115643000, 0.5458854000, 1.2232229000", \ - "0.2224181000, 0.2313845000, 0.2507803000, 0.2888065000, 0.3742539000, 0.6088886000, 1.2881770000", \ - "0.2706037000, 0.2822647000, 0.3071629000, 0.3552282000, 0.4460556000, 0.6809318000, 1.3578870000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0297033000, 0.0340285000, 0.0430307000, 0.0643172000, 0.1145945000, 0.2513137000, 0.6690128000", \ - "0.0299173000, 0.0338056000, 0.0432754000, 0.0639643000, 0.1147055000, 0.2509965000, 0.6689801000", \ - "0.0295891000, 0.0336945000, 0.0429689000, 0.0644596000, 0.1145741000, 0.2509598000, 0.6689608000", \ - "0.0297357000, 0.0339174000, 0.0429695000, 0.0642773000, 0.1147751000, 0.2511762000, 0.6664350000", \ - "0.0295788000, 0.0336764000, 0.0431458000, 0.0645337000, 0.1150703000, 0.2511401000, 0.6686203000", \ - "0.0388441000, 0.0430086000, 0.0524555000, 0.0722217000, 0.1197574000, 0.2537030000, 0.6694010000", \ - "0.0561193000, 0.0623563000, 0.0730681000, 0.0938024000, 0.1386502000, 0.2663901000, 0.6726459000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0239436000, 0.0288275000, 0.0418192000, 0.0784256000, 0.1893982000, 0.5241380000, 1.4984733000", \ - "0.0239718000, 0.0288178000, 0.0418197000, 0.0784011000, 0.1890200000, 0.5253765000, 1.5063437000", \ - "0.0239611000, 0.0288011000, 0.0419038000, 0.0782596000, 0.1893250000, 0.5239343000, 1.5002350000", \ - "0.0241073000, 0.0289823000, 0.0420983000, 0.0786188000, 0.1895107000, 0.5246076000, 1.5035549000", \ - "0.0288944000, 0.0337222000, 0.0461744000, 0.0811091000, 0.1904094000, 0.5259796000, 1.5035015000", \ - "0.0396450000, 0.0442229000, 0.0562304000, 0.0888349000, 0.1935513000, 0.5236656000, 1.5030098000", \ - "0.0551311000, 0.0614557000, 0.0762233000, 0.1088797000, 0.2018753000, 0.5270518000, 1.4955717000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1925965000, 0.1993503000, 0.2141533000, 0.2434884000, 0.3007086000, 0.4238958000, 0.7439947000", \ - "0.1965139000, 0.2032309000, 0.2180460000, 0.2473029000, 0.3045116000, 0.4277048000, 0.7479199000", \ - "0.2065421000, 0.2132591000, 0.2280831000, 0.2574720000, 0.3141757000, 0.4375363000, 0.7576447000", \ - "0.2323878000, 0.2391169000, 0.2539579000, 0.2831720000, 0.3403954000, 0.4635601000, 0.7835009000", \ - "0.2975934000, 0.3043165000, 0.3191488000, 0.3483166000, 0.4052459000, 0.5289487000, 0.8489726000", \ - "0.4324988000, 0.4404917000, 0.4570491000, 0.4885357000, 0.5474014000, 0.6717648000, 0.9917549000", \ - "0.6415297000, 0.6514756000, 0.6729419000, 0.7132198000, 0.7810519000, 0.9108927000, 1.2340382000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0932533000, 0.0995748000, 0.1143492000, 0.1478838000, 0.2312068000, 0.4652693000, 1.1421566000", \ - "0.0979057000, 0.1042383000, 0.1190758000, 0.1526137000, 0.2359959000, 0.4701959000, 1.1482922000", \ - "0.1074922000, 0.1138373000, 0.1286502000, 0.1621728000, 0.2455564000, 0.4799134000, 1.1575778000", \ - "0.1285945000, 0.1349080000, 0.1496068000, 0.1830142000, 0.2662960000, 0.5002584000, 1.1837232000", \ - "0.1669009000, 0.1737804000, 0.1895752000, 0.2240321000, 0.3076572000, 0.5422394000, 1.2196057000", \ - "0.2195603000, 0.2278954000, 0.2464013000, 0.2838205000, 0.3693423000, 0.6034834000, 1.2809938000", \ - "0.2723594000, 0.2833329000, 0.3073455000, 0.3525653000, 0.4427882000, 0.6777506000, 1.3541959000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0310994000, 0.0351664000, 0.0442021000, 0.0652336000, 0.1147339000, 0.2512526000, 0.6684591000", \ - "0.0311676000, 0.0351569000, 0.0441925000, 0.0655452000, 0.1148050000, 0.2509135000, 0.6683906000", \ - "0.0312345000, 0.0354499000, 0.0440564000, 0.0651749000, 0.1151861000, 0.2510441000, 0.6681548000", \ - "0.0312580000, 0.0354876000, 0.0440882000, 0.0653039000, 0.1150514000, 0.2511186000, 0.6656876000", \ - "0.0310225000, 0.0352850000, 0.0445339000, 0.0656371000, 0.1148025000, 0.2508866000, 0.6688237000", \ - "0.0391495000, 0.0429188000, 0.0518933000, 0.0711769000, 0.1188903000, 0.2525473000, 0.6663157000", \ - "0.0563787000, 0.0618658000, 0.0730043000, 0.0927271000, 0.1367098000, 0.2652423000, 0.6717119000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0239669000, 0.0287815000, 0.0417854000, 0.0783656000, 0.1894638000, 0.5246256000, 1.5044935000", \ - "0.0239897000, 0.0287931000, 0.0418419000, 0.0784570000, 0.1889720000, 0.5252339000, 1.4987814000", \ - "0.0239960000, 0.0287789000, 0.0418236000, 0.0784864000, 0.1890489000, 0.5244397000, 1.5071532000", \ - "0.0240985000, 0.0289410000, 0.0420052000, 0.0784723000, 0.1894338000, 0.5244293000, 1.5010820000", \ - "0.0273734000, 0.0324627000, 0.0452035000, 0.0804936000, 0.1896438000, 0.5253895000, 1.4987553000", \ - "0.0356865000, 0.0406223000, 0.0534520000, 0.0871309000, 0.1925898000, 0.5234900000, 1.4999428000", \ - "0.0495249000, 0.0558693000, 0.0700155000, 0.1025592000, 0.1999601000, 0.5252903000, 1.4972747000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22o_4") { - leakage_power () { - value : 0.0113302000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0102736000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0061161000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0120943000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0093744000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0082771000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0061161000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0091020000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0090448000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0079480000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0061173000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0087723000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0043867000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0044935000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0022843000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0044550000; - when : "A1&A2&B1&!B2"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__a22o"; - cell_leakage_power : 0.0075116040; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087632000, 0.0087694000, 0.0087837000, 0.0087878000, 0.0087973000, 0.0088191000, 0.0088692000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006599000, -0.006605200, -0.006619200, -0.006606000, -0.006575300, -0.006504700, -0.006341900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045180000; - } - pin ("A2") { - capacitance : 0.0047870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082199000, 0.0082125000, 0.0081953000, 0.0081981000, 0.0082045000, 0.0082194000, 0.0082536000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008185400, -0.008183800, -0.008179900, -0.008178800, -0.008176500, -0.008171100, -0.008158600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050320000; - } - pin ("B1") { - capacitance : 0.0043360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088787000, 0.0088744000, 0.0088645000, 0.0088622000, 0.0088569000, 0.0088447000, 0.0088165000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006744400, -0.006747500, -0.006754700, -0.006740300, -0.006707100, -0.006630500, -0.006454100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046260000; - } - pin ("B2") { - capacitance : 0.0048580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086077000, 0.0086001000, 0.0085826000, 0.0085824000, 0.0085822000, 0.0085816000, 0.0085801000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008558600, -0.008559900, -0.008562800, -0.008563000, -0.008563300, -0.008564000, -0.008565700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0052230000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (A1&A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0353936000, 0.0335352000, 0.0282869000, 0.0128063000, -0.042249400, -0.232990900, -0.853784900", \ - "0.0350140000, 0.0332082000, 0.0277792000, 0.0124077000, -0.042581100, -0.233200400, -0.853939100", \ - "0.0346298000, 0.0328359000, 0.0274054000, 0.0119944000, -0.043030400, -0.233639600, -0.854654200", \ - "0.0342764000, 0.0325427000, 0.0271305000, 0.0116217000, -0.043536300, -0.234084600, -0.855006200", \ - "0.0342624000, 0.0324673000, 0.0270040000, 0.0114034000, -0.043903800, -0.234562600, -0.855240000", \ - "0.0357446000, 0.0338951000, 0.0281348000, 0.0124344000, -0.043073200, -0.233639700, -0.854108400", \ - "0.0469745000, 0.0448363000, 0.0383170000, 0.0190875000, -0.040694700, -0.231402900, -0.852113500"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0319483000, 0.0339116000, 0.0401724000, 0.0596387000, 0.1196136000, 0.3106195000, 0.9270565000", \ - "0.0318752000, 0.0338285000, 0.0400903000, 0.0595805000, 0.1195763000, 0.3107998000, 0.9221629000", \ - "0.0316183000, 0.0335713000, 0.0398256000, 0.0592622000, 0.1193148000, 0.3106374000, 0.9262385000", \ - "0.0311194000, 0.0330536000, 0.0392349000, 0.0585241000, 0.1186960000, 0.3099405000, 0.9266482000", \ - "0.0307494000, 0.0326028000, 0.0386751000, 0.0578306000, 0.1179410000, 0.3093318000, 0.9206863000", \ - "0.0317057000, 0.0335125000, 0.0392859000, 0.0581651000, 0.1173558000, 0.3078341000, 0.9288231000", \ - "0.0342789000, 0.0359669000, 0.0416549000, 0.0600361000, 0.1199693000, 0.3106345000, 0.9252558000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0343112000, 0.0325446000, 0.0271752000, 0.0118191000, -0.043124300, -0.233880200, -0.854864900", \ - "0.0342718000, 0.0325934000, 0.0271757000, 0.0117948000, -0.043277500, -0.234056300, -0.855108200", \ - "0.0337509000, 0.0319511000, 0.0265678000, 0.0112308000, -0.043691900, -0.234503000, -0.855542200", \ - "0.0334202000, 0.0315676000, 0.0262144000, 0.0107392000, -0.044287500, -0.234821700, -0.856110000", \ - "0.0328569000, 0.0310427000, 0.0256904000, 0.0102608000, -0.044853800, -0.235485000, -0.856476100", \ - "0.0324706000, 0.0306889000, 0.0251074000, 0.0102916000, -0.045224500, -0.235778900, -0.856657700", \ - "0.0417172000, 0.0396433000, 0.0334036000, 0.0145739000, -0.044915300, -0.236087500, -0.856691100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0357267000, 0.0376945000, 0.0439747000, 0.0637147000, 0.1244793000, 0.3166912000, 0.9354572000", \ - "0.0355656000, 0.0375281000, 0.0438089000, 0.0635549000, 0.1242915000, 0.3166570000, 0.9353318000", \ - "0.0352887000, 0.0372508000, 0.0435418000, 0.0632680000, 0.1239941000, 0.3163195000, 0.9348198000", \ - "0.0349533000, 0.0368818000, 0.0431386000, 0.0627069000, 0.1233713000, 0.3156548000, 0.9293578000", \ - "0.0349681000, 0.0368623000, 0.0429616000, 0.0622899000, 0.1227206000, 0.3164195000, 0.9301355000", \ - "0.0369700000, 0.0387363000, 0.0445099000, 0.0632875000, 0.1228041000, 0.3141841000, 0.9309220000", \ - "0.0397126000, 0.0412146000, 0.0467914000, 0.0652647000, 0.1250973000, 0.3159731000, 0.9286844000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0409641000, 0.0394591000, 0.0340495000, 0.0185669000, -0.036643400, -0.227314900, -0.848279200", \ - "0.0407998000, 0.0389613000, 0.0336584000, 0.0181464000, -0.036908000, -0.227522000, -0.848616500", \ - "0.0407339000, 0.0389438000, 0.0335038000, 0.0180260000, -0.037054100, -0.227828100, -0.848678700", \ - "0.0402444000, 0.0384111000, 0.0329928000, 0.0176202000, -0.037428500, -0.228099800, -0.848843100", \ - "0.0398832000, 0.0380756000, 0.0326248000, 0.0172267000, -0.037865600, -0.228557600, -0.849334200", \ - "0.0402510000, 0.0384206000, 0.0328585000, 0.0169373000, -0.038323600, -0.228735900, -0.849467900", \ - "0.0490133000, 0.0469256000, 0.0407154000, 0.0218135000, -0.037943100, -0.229035500, -0.849445500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0390874000, 0.0410066000, 0.0471843000, 0.0667453000, 0.1275045000, 0.3192417000, 0.9347616000", \ - "0.0388248000, 0.0407799000, 0.0470311000, 0.0666237000, 0.1273763000, 0.3196729000, 0.9369637000", \ - "0.0386193000, 0.0405731000, 0.0468383000, 0.0663990000, 0.1271639000, 0.3194009000, 0.9326831000", \ - "0.0383344000, 0.0402850000, 0.0465099000, 0.0660579000, 0.1266764000, 0.3190053000, 0.9377033000", \ - "0.0379426000, 0.0398702000, 0.0459580000, 0.0653026000, 0.1257649000, 0.3183134000, 0.9372547000", \ - "0.0390929000, 0.0409241000, 0.0468617000, 0.0655520000, 0.1253719000, 0.3167204000, 0.9332807000", \ - "0.0407914000, 0.0425874000, 0.0485437000, 0.0670169000, 0.1268690000, 0.3186801000, 0.9296196000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0288654000, 0.0270635000, 0.0217383000, 0.0063165000, -0.048697400, -0.239370600, -0.860335400", \ - "0.0285247000, 0.0267500000, 0.0213287000, 0.0059556000, -0.049024800, -0.239637500, -0.860471900", \ - "0.0280464000, 0.0262609000, 0.0208741000, 0.0054247000, -0.049524200, -0.240144300, -0.861014600", \ - "0.0275711000, 0.0257520000, 0.0203224000, 0.0049032000, -0.050143500, -0.240782500, -0.861730500", \ - "0.0277442000, 0.0259905000, 0.0204955000, 0.0049157000, -0.050338400, -0.240877300, -0.861738400", \ - "0.0284614000, 0.0264784000, 0.0208042000, 0.0050137000, -0.050436700, -0.240840400, -0.861462800", \ - "0.0401737000, 0.0379881000, 0.0313843000, 0.0120984000, -0.047873700, -0.238596600, -0.859405300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0303920000, 0.0323602000, 0.0386135000, 0.0580925000, 0.1182446000, 0.3097294000, 0.9260125000", \ - "0.0303224000, 0.0322859000, 0.0385201000, 0.0580364000, 0.1182314000, 0.3097112000, 0.9260646000", \ - "0.0301089000, 0.0320751000, 0.0383212000, 0.0577651000, 0.1179672000, 0.3095672000, 0.9218057000", \ - "0.0297880000, 0.0317143000, 0.0378516000, 0.0571068000, 0.1171849000, 0.3088424000, 0.9241136000", \ - "0.0296441000, 0.0314548000, 0.0375289000, 0.0565883000, 0.1164400000, 0.3081938000, 0.9252519000", \ - "0.0308631000, 0.0326202000, 0.0383785000, 0.0571151000, 0.1163039000, 0.3070571000, 0.9236232000", \ - "0.0340970000, 0.0357240000, 0.0413361000, 0.0593831000, 0.1191455000, 0.3096785000, 0.9215306000"); - } - } - max_capacitance : 0.5566500000; - max_transition : 1.5092770000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.2086092000, 0.2128471000, 0.2238946000, 0.2485439000, 0.2996216000, 0.4166649000, 0.7435960000", \ - "0.2137310000, 0.2179814000, 0.2290124000, 0.2536847000, 0.3052143000, 0.4217356000, 0.7482968000", \ - "0.2263040000, 0.2305457000, 0.2415512000, 0.2661818000, 0.3173087000, 0.4343454000, 0.7610682000", \ - "0.2549899000, 0.2592146000, 0.2701972000, 0.2947878000, 0.3461398000, 0.4630773000, 0.7899553000", \ - "0.3168798000, 0.3211149000, 0.3321280000, 0.3569301000, 0.4084043000, 0.5253216000, 0.8524487000", \ - "0.4434832000, 0.4480488000, 0.4598075000, 0.4862306000, 0.5396315000, 0.6580130000, 0.9852815000", \ - "0.6653493000, 0.6707044000, 0.6847632000, 0.7155322000, 0.7766816000, 0.9039762000, 1.2354451000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0900997000, 0.0942027000, 0.1053732000, 0.1333575000, 0.2070436000, 0.4315213000, 1.1488147000", \ - "0.0940743000, 0.0982506000, 0.1093838000, 0.1373681000, 0.2111417000, 0.4355625000, 1.1521513000", \ - "0.1040560000, 0.1081754000, 0.1193423000, 0.1472704000, 0.2209555000, 0.4454733000, 1.1634614000", \ - "0.1276529000, 0.1317933000, 0.1428325000, 0.1705561000, 0.2442027000, 0.4694078000, 1.1830023000", \ - "0.1679142000, 0.1723687000, 0.1840805000, 0.2124474000, 0.2865181000, 0.5113884000, 1.2267333000", \ - "0.2146968000, 0.2200690000, 0.2338468000, 0.2647931000, 0.3400101000, 0.5645440000, 1.2811061000", \ - "0.2470712000, 0.2539202000, 0.2717226000, 0.3101698000, 0.3897708000, 0.6142775000, 1.3297441000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0301835000, 0.0327909000, 0.0396684000, 0.0561430000, 0.0990216000, 0.2243746000, 0.6466051000", \ - "0.0301091000, 0.0326678000, 0.0395258000, 0.0566054000, 0.0989161000, 0.2247061000, 0.6484165000", \ - "0.0301312000, 0.0326951000, 0.0395471000, 0.0564707000, 0.0990415000, 0.2242748000, 0.6484266000", \ - "0.0304248000, 0.0326438000, 0.0394828000, 0.0564336000, 0.0991397000, 0.2242508000, 0.6473625000", \ - "0.0303855000, 0.0326536000, 0.0399604000, 0.0564836000, 0.0987593000, 0.2245356000, 0.6476097000", \ - "0.0346469000, 0.0373164000, 0.0440490000, 0.0609066000, 0.1023288000, 0.2261149000, 0.6480832000", \ - "0.0459691000, 0.0492735000, 0.0574567000, 0.0750185000, 0.1180361000, 0.2393244000, 0.6492831000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0235617000, 0.0266947000, 0.0362478000, 0.0650194000, 0.1597339000, 0.4772549000, 1.5051268000", \ - "0.0236014000, 0.0266995000, 0.0362294000, 0.0650580000, 0.1599126000, 0.4773085000, 1.5044088000", \ - "0.0235159000, 0.0266270000, 0.0361267000, 0.0649921000, 0.1598114000, 0.4773206000, 1.5034169000", \ - "0.0235192000, 0.0266241000, 0.0361368000, 0.0650114000, 0.1595984000, 0.4766637000, 1.5006598000", \ - "0.0271234000, 0.0300255000, 0.0390813000, 0.0672397000, 0.1605165000, 0.4778349000, 1.5029634000", \ - "0.0354690000, 0.0383331000, 0.0470050000, 0.0729867000, 0.1631544000, 0.4768397000, 1.5030335000", \ - "0.0490778000, 0.0526997000, 0.0631417000, 0.0887335000, 0.1699493000, 0.4784231000, 1.5000984000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.2191499000, 0.2234763000, 0.2345614000, 0.2589813000, 0.3095332000, 0.4252621000, 0.7518649000", \ - "0.2244673000, 0.2288311000, 0.2398750000, 0.2643564000, 0.3150889000, 0.4302919000, 0.7567223000", \ - "0.2375369000, 0.2418626000, 0.2529520000, 0.2774320000, 0.3281724000, 0.4437449000, 0.7703093000", \ - "0.2670804000, 0.2713919000, 0.2825002000, 0.3069393000, 0.3572723000, 0.4729611000, 0.7991985000", \ - "0.3292193000, 0.3335326000, 0.3446347000, 0.3691163000, 0.4198549000, 0.5354567000, 0.8620633000", \ - "0.4580996000, 0.4627549000, 0.4745949000, 0.5002430000, 0.5526307000, 0.6691006000, 0.9958459000", \ - "0.6812710000, 0.6868324000, 0.7010715000, 0.7318318000, 0.7915787000, 0.9168181000, 1.2468162000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0976290000, 0.1014049000, 0.1116931000, 0.1380905000, 0.2107049000, 0.4351188000, 1.1511126000", \ - "0.1019486000, 0.1057512000, 0.1160438000, 0.1425132000, 0.2152701000, 0.4392852000, 1.1550664000", \ - "0.1112245000, 0.1150132000, 0.1253441000, 0.1517321000, 0.2244374000, 0.4484256000, 1.1629577000", \ - "0.1323342000, 0.1361121000, 0.1464103000, 0.1727779000, 0.2454164000, 0.4696231000, 1.1860561000", \ - "0.1717592000, 0.1757124000, 0.1863738000, 0.2133301000, 0.2862124000, 0.5106655000, 1.2277392000", \ - "0.2249470000, 0.2295660000, 0.2416378000, 0.2701260000, 0.3436970000, 0.5679358000, 1.2849303000", \ - "0.2726759000, 0.2787038000, 0.2942067000, 0.3272932000, 0.4035429000, 0.6277905000, 1.3431907000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0306192000, 0.0335174000, 0.0397497000, 0.0558937000, 0.0974541000, 0.2223470000, 0.6476895000", \ - "0.0307817000, 0.0333498000, 0.0397998000, 0.0560742000, 0.0971593000, 0.2223239000, 0.6466349000", \ - "0.0306269000, 0.0331601000, 0.0396784000, 0.0555469000, 0.0972905000, 0.2223262000, 0.6473708000", \ - "0.0310608000, 0.0336480000, 0.0396520000, 0.0561368000, 0.0975213000, 0.2224382000, 0.6474830000", \ - "0.0309752000, 0.0335092000, 0.0396297000, 0.0556395000, 0.0974842000, 0.2223189000, 0.6473045000", \ - "0.0348874000, 0.0377793000, 0.0441760000, 0.0596946000, 0.1000992000, 0.2238078000, 0.6476514000", \ - "0.0462567000, 0.0489463000, 0.0569052000, 0.0742259000, 0.1155720000, 0.2355883000, 0.6484627000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0209484000, 0.0241942000, 0.0337797000, 0.0626976000, 0.1588506000, 0.4776284000, 1.5040409000", \ - "0.0210789000, 0.0242131000, 0.0337475000, 0.0627814000, 0.1587114000, 0.4773311000, 1.5022553000", \ - "0.0209428000, 0.0241210000, 0.0336795000, 0.0627452000, 0.1590087000, 0.4769995000, 1.5005870000", \ - "0.0209872000, 0.0240730000, 0.0336918000, 0.0627715000, 0.1587347000, 0.4774534000, 1.5043988000", \ - "0.0229291000, 0.0261528000, 0.0355367000, 0.0642366000, 0.1595294000, 0.4774960000, 1.5052858000", \ - "0.0281669000, 0.0313100000, 0.0407580000, 0.0682085000, 0.1611100000, 0.4764269000, 1.5043417000", \ - "0.0388420000, 0.0427211000, 0.0530989000, 0.0787546000, 0.1654484000, 0.4786933000, 1.5002380000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1855716000, 0.1899348000, 0.2011920000, 0.2262893000, 0.2783845000, 0.3957863000, 0.7225594000", \ - "0.1893765000, 0.1936919000, 0.2049055000, 0.2299411000, 0.2815940000, 0.3992477000, 0.7264162000", \ - "0.1989394000, 0.2032528000, 0.2144655000, 0.2394904000, 0.2911954000, 0.4088585000, 0.7360317000", \ - "0.2251566000, 0.2294078000, 0.2406466000, 0.2654601000, 0.3173639000, 0.4359277000, 0.7631084000", \ - "0.2930485000, 0.2973913000, 0.3086446000, 0.3335899000, 0.3856172000, 0.5033003000, 0.8304551000", \ - "0.4384917000, 0.4434692000, 0.4561895000, 0.4832000000, 0.5370593000, 0.6563417000, 0.9832856000", \ - "0.6740430000, 0.6803135000, 0.6960520000, 0.7311042000, 0.7953733000, 0.9201644000, 1.2511152000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0763085000, 0.0802411000, 0.0909519000, 0.1179355000, 0.1902059000, 0.4128630000, 1.1320175000", \ - "0.0804559000, 0.0844096000, 0.0951326000, 0.1221282000, 0.1944341000, 0.4170269000, 1.1362868000", \ - "0.0904389000, 0.0943797000, 0.1050776000, 0.1320218000, 0.2043814000, 0.4273270000, 1.1511226000", \ - "0.1124879000, 0.1164739000, 0.1271636000, 0.1540308000, 0.2263599000, 0.4500340000, 1.1633673000", \ - "0.1448715000, 0.1493607000, 0.1610610000, 0.1890760000, 0.2623712000, 0.4865842000, 1.2056931000", \ - "0.1770261000, 0.1827545000, 0.1973770000, 0.2290431000, 0.3037850000, 0.5275297000, 1.2453836000", \ - "0.1840993000, 0.1915076000, 0.2103821000, 0.2508120000, 0.3323272000, 0.5558973000, 1.2702864000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0314723000, 0.0338220000, 0.0405960000, 0.0571803000, 0.0999079000, 0.2251817000, 0.6479451000", \ - "0.0312053000, 0.0338638000, 0.0409552000, 0.0575403000, 0.1002024000, 0.2251727000, 0.6474894000", \ - "0.0312632000, 0.0339326000, 0.0410254000, 0.0574996000, 0.1001227000, 0.2252847000, 0.6474811000", \ - "0.0311915000, 0.0338104000, 0.0408047000, 0.0577120000, 0.1000619000, 0.2250769000, 0.6470515000", \ - "0.0311525000, 0.0336282000, 0.0405294000, 0.0570838000, 0.0998101000, 0.2247814000, 0.6480690000", \ - "0.0395318000, 0.0423001000, 0.0496772000, 0.0642073000, 0.1045485000, 0.2272458000, 0.6487939000", \ - "0.0579974000, 0.0613334000, 0.0706563000, 0.0876860000, 0.1248923000, 0.2410480000, 0.6513063000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0220009000, 0.0251042000, 0.0344677000, 0.0630021000, 0.1581055000, 0.4761367000, 1.5081061000", \ - "0.0220636000, 0.0251027000, 0.0345001000, 0.0630346000, 0.1581613000, 0.4759773000, 1.5083357000", \ - "0.0220356000, 0.0251597000, 0.0344885000, 0.0631083000, 0.1579727000, 0.4762942000, 1.5025973000", \ - "0.0229108000, 0.0258650000, 0.0350686000, 0.0636064000, 0.1582730000, 0.4759437000, 1.5019733000", \ - "0.0277105000, 0.0307425000, 0.0394488000, 0.0666928000, 0.1595993000, 0.4752377000, 1.5091276000", \ - "0.0383677000, 0.0413222000, 0.0499675000, 0.0746607000, 0.1625496000, 0.4747630000, 1.5068335000", \ - "0.0528026000, 0.0578000000, 0.0688818000, 0.0934097000, 0.1721415000, 0.4779502000, 1.4990712000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1906399000, 0.1949825000, 0.2060978000, 0.2306113000, 0.2813006000, 0.3968695000, 0.7233993000", \ - "0.1944330000, 0.1987531000, 0.2098675000, 0.2344011000, 0.2850726000, 0.4003181000, 0.7266468000", \ - "0.2044283000, 0.2087389000, 0.2198391000, 0.2442870000, 0.2950268000, 0.4103264000, 0.7367980000", \ - "0.2316712000, 0.2360053000, 0.2472290000, 0.2715929000, 0.3221410000, 0.4378419000, 0.7641117000", \ - "0.2985983000, 0.3029281000, 0.3140618000, 0.3383474000, 0.3889150000, 0.5047356000, 0.8313015000", \ - "0.4425991000, 0.4476679000, 0.4601263000, 0.4867045000, 0.5388279000, 0.6559859000, 0.9823626000", \ - "0.6768356000, 0.6831234000, 0.6989392000, 0.7337105000, 0.7954856000, 0.9181720000, 1.2477972000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0814564000, 0.0854099000, 0.0961252000, 0.1230953000, 0.1951769000, 0.4185704000, 1.1370425000", \ - "0.0858556000, 0.0898049000, 0.1005303000, 0.1275077000, 0.1996571000, 0.4220803000, 1.1425519000", \ - "0.0949695000, 0.0989251000, 0.1096361000, 0.1365581000, 0.2087646000, 0.4313433000, 1.1479093000", \ - "0.1142244000, 0.1182084000, 0.1289221000, 0.1558238000, 0.2281029000, 0.4516016000, 1.1707288000", \ - "0.1452280000, 0.1496291000, 0.1612639000, 0.1893486000, 0.2626469000, 0.4866489000, 1.2003204000", \ - "0.1800315000, 0.1854522000, 0.1993871000, 0.2307037000, 0.3059127000, 0.5295269000, 1.2452495000", \ - "0.1949123000, 0.2019840000, 0.2201991000, 0.2597103000, 0.3407232000, 0.5650809000, 1.2790184000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0307918000, 0.0333389000, 0.0403591000, 0.0557101000, 0.0973443000, 0.2222519000, 0.6471873000", \ - "0.0309373000, 0.0335635000, 0.0396619000, 0.0560577000, 0.0971245000, 0.2223914000, 0.6472159000", \ - "0.0309008000, 0.0335343000, 0.0396363000, 0.0561171000, 0.0970980000, 0.2223518000, 0.6463383000", \ - "0.0308407000, 0.0334294000, 0.0400295000, 0.0553282000, 0.0972961000, 0.2221623000, 0.6470200000", \ - "0.0306758000, 0.0331381000, 0.0399252000, 0.0561953000, 0.0974213000, 0.2224490000, 0.6470928000", \ - "0.0383951000, 0.0407847000, 0.0471771000, 0.0619932000, 0.1007963000, 0.2239441000, 0.6477184000", \ - "0.0560220000, 0.0595167000, 0.0687326000, 0.0844233000, 0.1200374000, 0.2354132000, 0.6495919000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0220875000, 0.0251077000, 0.0344935000, 0.0630535000, 0.1581865000, 0.4757255000, 1.5092286000", \ - "0.0220442000, 0.0250996000, 0.0344137000, 0.0631502000, 0.1579503000, 0.4761570000, 1.5055849000", \ - "0.0220497000, 0.0250833000, 0.0344254000, 0.0631544000, 0.1579815000, 0.4762002000, 1.5072813000", \ - "0.0226632000, 0.0256292000, 0.0349828000, 0.0633033000, 0.1582520000, 0.4763674000, 1.5092766000", \ - "0.0262918000, 0.0294400000, 0.0385209000, 0.0661974000, 0.1593918000, 0.4751327000, 1.5014384000", \ - "0.0351339000, 0.0382481000, 0.0470772000, 0.0729645000, 0.1625394000, 0.4756791000, 1.5081270000", \ - "0.0490066000, 0.0532856000, 0.0643942000, 0.0907023000, 0.1705645000, 0.4783113000, 1.4950877000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22oi_1") { - leakage_power () { - value : 0.0003040000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 5.8899391e-05; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0079443000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0002457000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0005546000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0003095000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0079442000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0004963000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0005183000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0002731000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0079443000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0004599000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0045073000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0046373000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0005067000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0045073000; - when : "A1&A2&B1&!B2"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__a22oi"; - cell_leakage_power : 0.0025757180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046905000, 0.0046941000, 0.0047025000, 0.0047027000, 0.0047032000, 0.0047044000, 0.0047072000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003877000, -0.003879700, -0.003886000, -0.003880400, -0.003867600, -0.003838100, -0.003770100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024350000; - } - pin ("A2") { - capacitance : 0.0023770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042726000, 0.0042718000, 0.0042699000, 0.0042720000, 0.0042769000, 0.0042880000, 0.0043138000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004272700, -0.004270000, -0.004263700, -0.004263500, -0.004262900, -0.004261700, -0.004258700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024970000; - } - pin ("B1") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047243000, 0.0047270000, 0.0047335000, 0.0047330000, 0.0047320000, 0.0047298000, 0.0047245000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003881800, -0.003883900, -0.003888900, -0.003882600, -0.003868200, -0.003835000, -0.003758300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024670000; - } - pin ("B2") { - capacitance : 0.0023220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040737000, 0.0040744000, 0.0040758000, 0.0040763000, 0.0040777000, 0.0040809000, 0.0040881000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004076500, -0.004076900, -0.004077700, -0.004077700, -0.004077600, -0.004077500, -0.004077100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024850000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A2&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0079020000, 0.0068110000, 0.0042180000, -0.001983900, -0.016686600, -0.051680100, -0.134780700", \ - "0.0077762000, 0.0066835000, 0.0041161000, -0.002033100, -0.016758700, -0.051753700, -0.134817000", \ - "0.0075808000, 0.0065127000, 0.0039606000, -0.002168400, -0.016834800, -0.051824500, -0.134889200", \ - "0.0074300000, 0.0063456000, 0.0037838000, -0.002336700, -0.016961300, -0.051902500, -0.134952500", \ - "0.0074134000, 0.0062633000, 0.0036291000, -0.002468500, -0.017096500, -0.051992600, -0.135022300", \ - "0.0079154000, 0.0065552000, 0.0039124000, -0.002333700, -0.017135600, -0.051957100, -0.135000000", \ - "0.0092354000, 0.0080739000, 0.0051762000, -0.001183400, -0.016094400, -0.051565300, -0.134890700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0122442000, 0.0133770000, 0.0160557000, 0.0223013000, 0.0369483000, 0.0715829000, 0.1537503000", \ - "0.0120602000, 0.0132031000, 0.0159003000, 0.0221711000, 0.0368901000, 0.0716004000, 0.1536285000", \ - "0.0117754000, 0.0129320000, 0.0156263000, 0.0219435000, 0.0367330000, 0.0715032000, 0.1535816000", \ - "0.0115427000, 0.0126720000, 0.0153577000, 0.0216879000, 0.0365148000, 0.0713459000, 0.1535357000", \ - "0.0114073000, 0.0125234000, 0.0151463000, 0.0214154000, 0.0361695000, 0.0710534000, 0.1532452000", \ - "0.0114241000, 0.0125376000, 0.0151831000, 0.0213740000, 0.0361702000, 0.0708181000, 0.1531511000", \ - "0.0117027000, 0.0127746000, 0.0153167000, 0.0216131000, 0.0363780000, 0.0712166000, 0.1532220000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0082599000, 0.0071672000, 0.0045720000, -0.001588600, -0.016317700, -0.051310900, -0.134436400", \ - "0.0081560000, 0.0070638000, 0.0044789000, -0.001680500, -0.016389600, -0.051388100, -0.134498700", \ - "0.0079991000, 0.0069190000, 0.0043463000, -0.001813200, -0.016495100, -0.051460500, -0.134540200", \ - "0.0077857000, 0.0067444000, 0.0041874000, -0.001948600, -0.016579300, -0.051529200, -0.134597100", \ - "0.0076634000, 0.0065540000, 0.0039560000, -0.002141300, -0.016761100, -0.051618700, -0.134652000", \ - "0.0078654000, 0.0067683000, 0.0041355000, -0.002065300, -0.016860100, -0.051729100, -0.134713300", \ - "0.0088221000, 0.0076646000, 0.0049942000, -0.001370600, -0.016302900, -0.051582100, -0.134604100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0151536000, 0.0162833000, 0.0189142000, 0.0251299000, 0.0398191000, 0.0744822000, 0.1565828000", \ - "0.0150386000, 0.0161377000, 0.0188100000, 0.0250448000, 0.0397696000, 0.0744183000, 0.1565481000", \ - "0.0148192000, 0.0159585000, 0.0186215000, 0.0248961000, 0.0396573000, 0.0743704000, 0.1565567000", \ - "0.0146494000, 0.0157729000, 0.0184348000, 0.0247127000, 0.0394790000, 0.0742833000, 0.1564419000", \ - "0.0145227000, 0.0156250000, 0.0182567000, 0.0245047000, 0.0392551000, 0.0741039000, 0.1562544000", \ - "0.0144774000, 0.0156094000, 0.0183034000, 0.0245484000, 0.0391950000, 0.0739874000, 0.1562578000", \ - "0.0147176000, 0.0157714000, 0.0183181000, 0.0246972000, 0.0395524000, 0.0741937000, 0.1563944000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0048805000, 0.0038092000, 0.0012259000, -0.004968600, -0.019733800, -0.054801400, -0.137989100", \ - "0.0047826000, 0.0037322000, 0.0011939000, -0.004953500, -0.019676000, -0.054722900, -0.137893000", \ - "0.0045772000, 0.0035483000, 0.0010438000, -0.005037400, -0.019683600, -0.054678200, -0.137822500", \ - "0.0042904000, 0.0032571000, 0.0007683000, -0.005240900, -0.019820400, -0.054722800, -0.137826300", \ - "0.0041039000, 0.0030416000, 0.0005256000, -0.005483400, -0.020012700, -0.054871300, -0.137897900", \ - "0.0046609000, 0.0035370000, 0.0009114000, -0.005194700, -0.020224200, -0.054933800, -0.137951400", \ - "0.0061584000, 0.0049473000, 0.0020909000, -0.004450800, -0.019514000, -0.054811100, -0.138030200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0094693000, 0.0105985000, 0.0132828000, 0.0195449000, 0.0341967000, 0.0688720000, 0.1509176000", \ - "0.0092340000, 0.0103965000, 0.0130920000, 0.0194100000, 0.0341661000, 0.0688647000, 0.1509320000", \ - "0.0089162000, 0.0100722000, 0.0127439000, 0.0191377000, 0.0339696000, 0.0687782000, 0.1508986000", \ - "0.0087195000, 0.0098576000, 0.0124888000, 0.0188439000, 0.0336793000, 0.0685568000, 0.1507633000", \ - "0.0086730000, 0.0097758000, 0.0123944000, 0.0186382000, 0.0333686000, 0.0682769000, 0.1506140000", \ - "0.0096093000, 0.0108229000, 0.0128272000, 0.0189069000, 0.0334302000, 0.0680885000, 0.1502906000", \ - "0.0111535000, 0.0119964000, 0.0143964000, 0.0202921000, 0.0346700000, 0.0692518000, 0.1503748000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0052104000, 0.0041309000, 0.0015381000, -0.004658100, -0.019423300, -0.054498200, -0.137682700", \ - "0.0051221000, 0.0040675000, 0.0015133000, -0.004638700, -0.019365900, -0.054415200, -0.137592300", \ - "0.0049061000, 0.0038666000, 0.0013604000, -0.004719000, -0.019380300, -0.054376700, -0.137530400", \ - "0.0045706000, 0.0035407000, 0.0010668000, -0.004932400, -0.019508400, -0.054431300, -0.137529500", \ - "0.0044765000, 0.0033604000, 0.0007861000, -0.005241400, -0.019766100, -0.054577200, -0.137597700", \ - "0.0045753000, 0.0034660000, 0.0008659000, -0.005292800, -0.020019500, -0.054808300, -0.137711900", \ - "0.0057382000, 0.0045402000, 0.0017640000, -0.004654100, -0.019606100, -0.054780700, -0.137811700"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0124673000, 0.0135875000, 0.0162194000, 0.0224479000, 0.0371095000, 0.0717924000, 0.1538465000", \ - "0.0123259000, 0.0134303000, 0.0161023000, 0.0223461000, 0.0370481000, 0.0717877000, 0.1538489000", \ - "0.0120360000, 0.0131979000, 0.0158881000, 0.0221636000, 0.0369387000, 0.0716725000, 0.1538240000", \ - "0.0119405000, 0.0130084000, 0.0156560000, 0.0219861000, 0.0367544000, 0.0715631000, 0.1537665000", \ - "0.0119061000, 0.0129536000, 0.0156407000, 0.0218685000, 0.0365821000, 0.0713617000, 0.1536621000", \ - "0.0123768000, 0.0134772000, 0.0160409000, 0.0221394000, 0.0367005000, 0.0712695000, 0.1535045000", \ - "0.0148478000, 0.0159848000, 0.0180336000, 0.0238195000, 0.0382474000, 0.0729831000, 0.1536849000"); - } - } - max_capacitance : 0.0888160000; - max_transition : 1.8611700000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0465203000, 0.0504282000, 0.0593373000, 0.0803187000, 0.1283089000, 0.2409005000, 0.5059853000", \ - "0.0505797000, 0.0546264000, 0.0637347000, 0.0845642000, 0.1327484000, 0.2451769000, 0.5103617000", \ - "0.0606922000, 0.0645769000, 0.0737749000, 0.0946425000, 0.1429528000, 0.2554253000, 0.5205162000", \ - "0.0836990000, 0.0883321000, 0.0983105000, 0.1193003000, 0.1672615000, 0.2796774000, 0.5447927000", \ - "0.1167042000, 0.1234663000, 0.1385997000, 0.1683101000, 0.2239225000, 0.3365925000, 0.6014100000", \ - "0.1539787000, 0.1640553000, 0.1867541000, 0.2324160000, 0.3168556000, 0.4628078000, 0.7316027000", \ - "0.1812486000, 0.1961057000, 0.2312154000, 0.3001762000, 0.4285924000, 0.6528539000, 1.0229030000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1120582000, 0.1225287000, 0.1467386000, 0.2036030000, 0.3369855000, 0.6518459000, 1.3972095000", \ - "0.1163447000, 0.1270168000, 0.1515127000, 0.2087640000, 0.3424611000, 0.6574447000, 1.4024643000", \ - "0.1279001000, 0.1382562000, 0.1630377000, 0.2207599000, 0.3548954000, 0.6707134000, 1.4158764000", \ - "0.1534918000, 0.1637900000, 0.1882848000, 0.2457191000, 0.3804349000, 0.6968861000, 1.4425510000", \ - "0.2055476000, 0.2171694000, 0.2435089000, 0.3006804000, 0.4349295000, 0.7516655000, 1.4999402000", \ - "0.2940041000, 0.3094104000, 0.3430848000, 0.4147475000, 0.5609516000, 0.8776881000, 1.6257975000", \ - "0.4315850000, 0.4558742000, 0.5067948000, 0.6085815000, 0.8018517000, 1.1682040000, 1.9184319000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0394416000, 0.0444367000, 0.0559189000, 0.0824950000, 0.1457102000, 0.2962057000, 0.6524022000", \ - "0.0394019000, 0.0443817000, 0.0555974000, 0.0827791000, 0.1461287000, 0.2962170000, 0.6528126000", \ - "0.0393122000, 0.0440658000, 0.0554525000, 0.0824714000, 0.1462118000, 0.2959275000, 0.6522761000", \ - "0.0499115000, 0.0534228000, 0.0625347000, 0.0857487000, 0.1465414000, 0.2963176000, 0.6525945000", \ - "0.0760714000, 0.0810682000, 0.0928183000, 0.1166036000, 0.1657634000, 0.3001842000, 0.6526859000", \ - "0.1216865000, 0.1295314000, 0.1465468000, 0.1808029000, 0.2441028000, 0.3629773000, 0.6663418000", \ - "0.1991640000, 0.2121485000, 0.2398693000, 0.2909703000, 0.3855523000, 0.5436369000, 0.8188175000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0922440000, 0.1060433000, 0.1385205000, 0.2156006000, 0.3982094000, 0.8315701000, 1.8593341000", \ - "0.0921982000, 0.1060292000, 0.1384760000, 0.2157287000, 0.3979571000, 0.8302555000, 1.8532879000", \ - "0.0922468000, 0.1060578000, 0.1385876000, 0.2159680000, 0.3980424000, 0.8296503000, 1.8530456000", \ - "0.0924967000, 0.1061449000, 0.1384940000, 0.2157092000, 0.3982784000, 0.8296353000, 1.8541252000", \ - "0.1062240000, 0.1188856000, 0.1475879000, 0.2200168000, 0.3982372000, 0.8301968000, 1.8597618000", \ - "0.1478569000, 0.1608599000, 0.1913632000, 0.2596315000, 0.4202206000, 0.8326511000, 1.8534172000", \ - "0.2364426000, 0.2518186000, 0.2880095000, 0.3682308000, 0.5296509000, 0.8984222000, 1.8611700000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0509773000, 0.0549171000, 0.0638634000, 0.0847697000, 0.1329355000, 0.2453362000, 0.5103237000", \ - "0.0552972000, 0.0592365000, 0.0682119000, 0.0890957000, 0.1371946000, 0.2497557000, 0.5148695000", \ - "0.0646678000, 0.0686320000, 0.0777471000, 0.0986878000, 0.1468574000, 0.2593404000, 0.5245636000", \ - "0.0850076000, 0.0889816000, 0.0989043000, 0.1202827000, 0.1689040000, 0.2815163000, 0.5467912000", \ - "0.1172700000, 0.1232056000, 0.1363075000, 0.1631042000, 0.2174410000, 0.3324250000, 0.5978511000", \ - "0.1564172000, 0.1660025000, 0.1857624000, 0.2260167000, 0.3027383000, 0.4414105000, 0.7145922000", \ - "0.1878899000, 0.2016236000, 0.2325653000, 0.2963850000, 0.4144871000, 0.6165843000, 0.9652713000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1257948000, 0.1355664000, 0.1594514000, 0.2140123000, 0.3431943000, 0.6478663000, 1.3690342000", \ - "0.1309482000, 0.1410665000, 0.1642696000, 0.2193871000, 0.3489538000, 0.6535284000, 1.3748593000", \ - "0.1428102000, 0.1529980000, 0.1768411000, 0.2322182000, 0.3616220000, 0.6668964000, 1.3891711000", \ - "0.1691121000, 0.1793689000, 0.2027279000, 0.2581187000, 0.3881824000, 0.6936786000, 1.4154158000", \ - "0.2246130000, 0.2355941000, 0.2593391000, 0.3143232000, 0.4442626000, 0.7501022000, 1.4756444000", \ - "0.3203653000, 0.3342637000, 0.3664430000, 0.4338896000, 0.5719566000, 0.8797787000, 1.6025080000", \ - "0.4783102000, 0.4989904000, 0.5442794000, 0.6373456000, 0.8231160000, 1.1714270000, 1.8994466000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0394058000, 0.0444116000, 0.0556576000, 0.0827981000, 0.1461497000, 0.2963381000, 0.6539170000", \ - "0.0394049000, 0.0443694000, 0.0556308000, 0.0827649000, 0.1462610000, 0.2962151000, 0.6522504000", \ - "0.0392518000, 0.0440939000, 0.0554100000, 0.0823874000, 0.1462614000, 0.2971022000, 0.6524712000", \ - "0.0453639000, 0.0495296000, 0.0595860000, 0.0845362000, 0.1464161000, 0.2967893000, 0.6528298000", \ - "0.0649442000, 0.0705518000, 0.0809976000, 0.1045171000, 0.1582377000, 0.2992661000, 0.6528367000", \ - "0.1048170000, 0.1113416000, 0.1262176000, 0.1549936000, 0.2135444000, 0.3370954000, 0.6630041000", \ - "0.1757016000, 0.1854223000, 0.2073635000, 0.2488942000, 0.3281049000, 0.4733471000, 0.7656894000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1033161000, 0.1167263000, 0.1485897000, 0.2231765000, 0.4005798000, 0.8188998000, 1.8115021000", \ - "0.1035163000, 0.1166586000, 0.1483850000, 0.2234097000, 0.4007778000, 0.8193304000, 1.8109608000", \ - "0.1033324000, 0.1167070000, 0.1483817000, 0.2245208000, 0.4001352000, 0.8185155000, 1.8155364000", \ - "0.1034373000, 0.1169129000, 0.1483333000, 0.2234619000, 0.4004348000, 0.8191900000, 1.8100836000", \ - "0.1141973000, 0.1263699000, 0.1557530000, 0.2265522000, 0.4001328000, 0.8190883000, 1.8167895000", \ - "0.1546936000, 0.1673960000, 0.1974444000, 0.2637774000, 0.4218943000, 0.8206024000, 1.8145452000", \ - "0.2416558000, 0.2578369000, 0.2928495000, 0.3677894000, 0.5300475000, 0.8853416000, 1.8198557000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0306176000, 0.0344129000, 0.0430970000, 0.0634550000, 0.1111089000, 0.2239917000, 0.4913413000", \ - "0.0349085000, 0.0387334000, 0.0475102000, 0.0678674000, 0.1157946000, 0.2287398000, 0.4961246000", \ - "0.0450693000, 0.0488957000, 0.0577953000, 0.0781582000, 0.1263447000, 0.2393696000, 0.5068253000", \ - "0.0614674000, 0.0673387000, 0.0795715000, 0.1029967000, 0.1508040000, 0.2636091000, 0.5305401000", \ - "0.0795245000, 0.0886268000, 0.1075900000, 0.1437029000, 0.2062317000, 0.3206874000, 0.5878829000", \ - "0.0940810000, 0.1079653000, 0.1365810000, 0.1908347000, 0.2882320000, 0.4448202000, 0.7183309000", \ - "0.0865979000, 0.1073702000, 0.1512860000, 0.2356780000, 0.3833946000, 0.6255425000, 1.0067200000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0879110000, 0.0981041000, 0.1217551000, 0.1770260000, 0.3067846000, 0.6125285000, 1.3369141000", \ - "0.0909829000, 0.1013195000, 0.1250016000, 0.1808498000, 0.3110391000, 0.6173610000, 1.3421401000", \ - "0.1001745000, 0.1103241000, 0.1343517000, 0.1906619000, 0.3212985000, 0.6279980000, 1.3526025000", \ - "0.1267264000, 0.1367413000, 0.1598398000, 0.2154129000, 0.3463315000, 0.6537196000, 1.3804323000", \ - "0.1862628000, 0.1982847000, 0.2243105000, 0.2796610000, 0.4096433000, 0.7170100000, 1.4429636000", \ - "0.2799244000, 0.2974706000, 0.3373225000, 0.4163218000, 0.5598232000, 0.8648122000, 1.5898587000", \ - "0.4261381000, 0.4523724000, 0.5109458000, 0.6296577000, 0.8469227000, 1.2168927000, 1.9319071000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0333585000, 0.0381562000, 0.0496039000, 0.0767030000, 0.1406852000, 0.2923718000, 0.6526888000", \ - "0.0333665000, 0.0381857000, 0.0496138000, 0.0766841000, 0.1406944000, 0.2923576000, 0.6524992000", \ - "0.0358658000, 0.0399973000, 0.0503234000, 0.0765914000, 0.1406946000, 0.2924280000, 0.6526090000", \ - "0.0508901000, 0.0546907000, 0.0628092000, 0.0838166000, 0.1418136000, 0.2925211000, 0.6524846000", \ - "0.0809615000, 0.0857972000, 0.0964795000, 0.1191645000, 0.1669922000, 0.2980130000, 0.6524296000", \ - "0.1342113000, 0.1413046000, 0.1567499000, 0.1894664000, 0.2478811000, 0.3656218000, 0.6683393000", \ - "0.2280652000, 0.2393496000, 0.2614317000, 0.3076620000, 0.3943286000, 0.5460863000, 0.8225086000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0896748000, 0.1033614000, 0.1352202000, 0.2112075000, 0.3904630000, 0.8147831000, 1.8196277000", \ - "0.0897668000, 0.1033393000, 0.1354351000, 0.2111655000, 0.3906063000, 0.8156283000, 1.8257222000", \ - "0.0895261000, 0.1032209000, 0.1353325000, 0.2114718000, 0.3906057000, 0.8154227000, 1.8203296000", \ - "0.0913913000, 0.1041852000, 0.1350960000, 0.2111425000, 0.3914712000, 0.8155316000, 1.8273735000", \ - "0.1207317000, 0.1309695000, 0.1556044000, 0.2196867000, 0.3905147000, 0.8155772000, 1.8222484000", \ - "0.1772685000, 0.1921547000, 0.2253574000, 0.2901472000, 0.4295602000, 0.8186118000, 1.8269470000", \ - "0.2713875000, 0.2929831000, 0.3402493000, 0.4335740000, 0.6001440000, 0.9285052000, 1.8288170000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0351545000, 0.0388619000, 0.0474281000, 0.0677775000, 0.1154595000, 0.2283816000, 0.4956422000", \ - "0.0394793000, 0.0433527000, 0.0520604000, 0.0724548000, 0.1203346000, 0.2334185000, 0.5006702000", \ - "0.0486972000, 0.0526290000, 0.0615723000, 0.0822150000, 0.1302775000, 0.2433498000, 0.5107541000", \ - "0.0646846000, 0.0698932000, 0.0808347000, 0.1038046000, 0.1524012000, 0.2659661000, 0.5335796000", \ - "0.0856521000, 0.0935218000, 0.1099392000, 0.1416531000, 0.2009879000, 0.3172951000, 0.5853631000", \ - "0.1050437000, 0.1175452000, 0.1435921000, 0.1928780000, 0.2790171000, 0.4259047000, 0.7053061000", \ - "0.1045052000, 0.1243881000, 0.1657614000, 0.2447000000, 0.3791885000, 0.5977943000, 0.9510482000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1037065000, 0.1136016000, 0.1373437000, 0.1919472000, 0.3210961000, 0.6259860000, 1.3469397000", \ - "0.1076706000, 0.1172143000, 0.1408966000, 0.1959740000, 0.3254157000, 0.6303319000, 1.3521746000", \ - "0.1168402000, 0.1274275000, 0.1509165000, 0.2064610000, 0.3362076000, 0.6414822000, 1.3628577000", \ - "0.1438368000, 0.1532675000, 0.1768166000, 0.2320904000, 0.3619995000, 0.6675984000, 1.3899605000", \ - "0.2084748000, 0.2186022000, 0.2429462000, 0.2972294000, 0.4266144000, 0.7319568000, 1.4545034000", \ - "0.3147846000, 0.3308389000, 0.3668068000, 0.4398462000, 0.5774222000, 0.8782235000, 1.5991823000", \ - "0.4788143000, 0.5034249000, 0.5570942000, 0.6672988000, 0.8742445000, 1.2303701000, 1.9457782000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0333539000, 0.0381750000, 0.0496018000, 0.0765832000, 0.1405580000, 0.2925422000, 0.6526688000", \ - "0.0333872000, 0.0381815000, 0.0496203000, 0.0766647000, 0.1406881000, 0.2922438000, 0.6529730000", \ - "0.0346595000, 0.0391069000, 0.0500025000, 0.0765895000, 0.1406722000, 0.2924402000, 0.6525689000", \ - "0.0444065000, 0.0483751000, 0.0573896000, 0.0809383000, 0.1413635000, 0.2925793000, 0.6525473000", \ - "0.0684010000, 0.0727427000, 0.0826378000, 0.1048882000, 0.1574337000, 0.2959676000, 0.6528380000", \ - "0.1144660000, 0.1203114000, 0.1331318000, 0.1605519000, 0.2159401000, 0.3392437000, 0.6645660000", \ - "0.1988076000, 0.2066683000, 0.2247653000, 0.2620294000, 0.3359570000, 0.4761544000, 0.7660580000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1033040000, 0.1166880000, 0.1482639000, 0.2230255000, 0.3999921000, 0.8191310000, 1.8109633000", \ - "0.1032576000, 0.1167166000, 0.1488349000, 0.2232213000, 0.4005532000, 0.8190563000, 1.8101375000", \ - "0.1032299000, 0.1168420000, 0.1483890000, 0.2233636000, 0.4010324000, 0.8195539000, 1.8132150000", \ - "0.1037036000, 0.1166148000, 0.1480917000, 0.2231929000, 0.4005221000, 0.8191980000, 1.8140124000", \ - "0.1272664000, 0.1376374000, 0.1636334000, 0.2290849000, 0.4005828000, 0.8189673000, 1.8153211000", \ - "0.1870291000, 0.2016386000, 0.2322605000, 0.2935160000, 0.4347557000, 0.8214873000, 1.8119596000", \ - "0.2850883000, 0.3065335000, 0.3538682000, 0.4424627000, 0.6044047000, 0.9270884000, 1.8202684000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22oi_2") { - leakage_power () { - value : 0.0008302000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0001445000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0074111000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0006657000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0015164000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0008307000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0074111000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0013518000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0013522000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0006661000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0074111000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0011892000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0046626000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0047947000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0005212000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0046625000; - when : "A1&A2&B1&!B2"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__a22oi"; - cell_leakage_power : 0.0028388210; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091423000, 0.0091517000, 0.0091733000, 0.0091736000, 0.0091743000, 0.0091758000, 0.0091793000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006301800, -0.006311300, -0.006333300, -0.006314800, -0.006272400, -0.006174500, -0.005948900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044030000; - } - pin ("A2") { - capacitance : 0.0043650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079336000, 0.0079336000, 0.0079335000, 0.0079346000, 0.0079371000, 0.0079428000, 0.0079561000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007913700, -0.007914600, -0.007916800, -0.007915000, -0.007911000, -0.007901800, -0.007880500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045850000; - } - pin ("B1") { - capacitance : 0.0042340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091440000, 0.0091502000, 0.0091646000, 0.0091660000, 0.0091690000, 0.0091761000, 0.0091925000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006371200, -0.006374800, -0.006383300, -0.006367300, -0.006330500, -0.006245600, -0.006050000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044680000; - } - pin ("B2") { - capacitance : 0.0042690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079050000, 0.0079011000, 0.0078920000, 0.0078909000, 0.0078884000, 0.0078826000, 0.0078692000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007874900, -0.007873300, -0.007869600, -0.007868500, -0.007866000, -0.007860200, -0.007846800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045830000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A2&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0136941000, 0.0123689000, 0.0088757000, -0.000236100, -0.024548800, -0.089216200, -0.260467600", \ - "0.0134712000, 0.0121722000, 0.0087017000, -0.000371700, -0.024713200, -0.089400000, -0.260574000", \ - "0.0131608000, 0.0118657000, 0.0084365000, -0.000639600, -0.024899400, -0.089469300, -0.260643200", \ - "0.0126709000, 0.0112805000, 0.0078772000, -0.001018500, -0.025264900, -0.089652400, -0.260774900", \ - "0.0125069000, 0.0111883000, 0.0077264000, -0.001220600, -0.025509800, -0.089851800, -0.260818200", \ - "0.0133177000, 0.0118992000, 0.0083191000, -0.000963200, -0.025727400, -0.090137900, -0.261107200", \ - "0.0157641000, 0.0143748000, 0.0107304000, 0.0011826000, -0.023441800, -0.089653300, -0.260498700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0207497000, 0.0221197000, 0.0257216000, 0.0351241000, 0.0595550000, 0.1237208000, 0.2929757000", \ - "0.0204118000, 0.0218028000, 0.0254554000, 0.0349224000, 0.0594507000, 0.1238623000, 0.2931371000", \ - "0.0198928000, 0.0213034000, 0.0249320000, 0.0344417000, 0.0591410000, 0.1235252000, 0.2929248000", \ - "0.0194649000, 0.0208701000, 0.0244790000, 0.0339926000, 0.0586465000, 0.1233121000, 0.2926934000", \ - "0.0192499000, 0.0205851000, 0.0241379000, 0.0335079000, 0.0580371000, 0.1226812000, 0.2924067000", \ - "0.0192204000, 0.0205517000, 0.0240725000, 0.0334279000, 0.0579476000, 0.1223957000, 0.2919065000", \ - "0.0194257000, 0.0206914000, 0.0241048000, 0.0332580000, 0.0581685000, 0.1227321000, 0.2918831000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0152778000, 0.0139516000, 0.0104940000, 0.0013243000, -0.023040000, -0.087652900, -0.258855700", \ - "0.0150927000, 0.0137718000, 0.0103211000, 0.0011665000, -0.023185600, -0.087799700, -0.259117500", \ - "0.0148013000, 0.0134983000, 0.0100474000, 0.0009547000, -0.023353200, -0.087923900, -0.259099800", \ - "0.0143713000, 0.0130842000, 0.0097214000, 0.0006236000, -0.023581100, -0.088100600, -0.259253700", \ - "0.0140811000, 0.0127817000, 0.0093356000, 0.0002851000, -0.023698000, -0.088238500, -0.259263400", \ - "0.0144719000, 0.0131351000, 0.0096447000, 0.0003992000, -0.024156500, -0.088505700, -0.259453600", \ - "0.0161031000, 0.0147173000, 0.0110981000, 0.0017002000, -0.023133000, -0.088337900, -0.259503500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0281134000, 0.0294357000, 0.0329433000, 0.0422631000, 0.0666987000, 0.1309546000, 0.3001679000", \ - "0.0278117000, 0.0291592000, 0.0327589000, 0.0420777000, 0.0665975000, 0.1307956000, 0.2999875000", \ - "0.0274534000, 0.0288194000, 0.0324597000, 0.0417959000, 0.0663864000, 0.1306811000, 0.2999458000", \ - "0.0271628000, 0.0285511000, 0.0321104000, 0.0414707000, 0.0660676000, 0.1304455000, 0.2999232000", \ - "0.0269173000, 0.0282571000, 0.0317569000, 0.0411360000, 0.0657356000, 0.1300649000, 0.2996300000", \ - "0.0268654000, 0.0282397000, 0.0317743000, 0.0411295000, 0.0656955000, 0.1299215000, 0.2994509000", \ - "0.0269538000, 0.0282116000, 0.0316524000, 0.0410456000, 0.0659145000, 0.1305571000, 0.2996174000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0062229000, 0.0050005000, 0.0016464000, -0.007472300, -0.031905400, -0.096727700, -0.268193100", \ - "0.0059191000, 0.0047246000, 0.0014715000, -0.007513900, -0.031840700, -0.096599100, -0.268027600", \ - "0.0055284000, 0.0043553000, 0.0011268000, -0.007730800, -0.031881100, -0.096521900, -0.267897900", \ - "0.0050960000, 0.0038694000, 0.0005659000, -0.008140600, -0.032157100, -0.096620100, -0.267882800", \ - "0.0050398000, 0.0037611000, 0.0003760000, -0.008556000, -0.032570800, -0.096890800, -0.267976900", \ - "0.0060394000, 0.0046391000, 0.0010462000, -0.008191800, -0.032779100, -0.097278300, -0.268259600", \ - "0.0089279000, 0.0074329000, 0.0035294000, -0.006289500, -0.031388500, -0.097044700, -0.267946600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0149157000, 0.0163246000, 0.0199769000, 0.0294338000, 0.0539293000, 0.1181076000, 0.2873203000", \ - "0.0145136000, 0.0158807000, 0.0195620000, 0.0291177000, 0.0537843000, 0.1181093000, 0.2874069000", \ - "0.0140011000, 0.0153914000, 0.0190103000, 0.0286545000, 0.0533587000, 0.1178811000, 0.2873463000", \ - "0.0135988000, 0.0149756000, 0.0186103000, 0.0277805000, 0.0527312000, 0.1176024000, 0.2873354000", \ - "0.0135414000, 0.0148682000, 0.0185865000, 0.0278373000, 0.0522225000, 0.1169679000, 0.2868028000", \ - "0.0147041000, 0.0159954000, 0.0194114000, 0.0286880000, 0.0528491000, 0.1168765000, 0.2863155000", \ - "0.0178042000, 0.0189653000, 0.0221371000, 0.0307463000, 0.0546094000, 0.1178879000, 0.2868183000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0078991000, 0.0066418000, 0.0032345000, -0.005934800, -0.030413300, -0.095257200, -0.266731600", \ - "0.0076270000, 0.0064022000, 0.0030982000, -0.005951700, -0.030326000, -0.095122600, -0.266558100", \ - "0.0071470000, 0.0059723000, 0.0027393000, -0.006153500, -0.030356500, -0.095041300, -0.266430500", \ - "0.0065818000, 0.0053766000, 0.0021298000, -0.006645900, -0.030623600, -0.095108100, -0.266400300", \ - "0.0065353000, 0.0052706000, 0.0017061000, -0.007212100, -0.031115600, -0.095362600, -0.266466800", \ - "0.0067183000, 0.0053946000, 0.0019178000, -0.007260300, -0.031655800, -0.095857000, -0.266776100", \ - "0.0088379000, 0.0073997000, 0.0036529000, -0.006004600, -0.030825300, -0.095846900, -0.266930400"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("0.0222557000, 0.0236008000, 0.0271516000, 0.0365373000, 0.0609546000, 0.1251481000, 0.2944266000", \ - "0.0218878000, 0.0232437000, 0.0267960000, 0.0362251000, 0.0607881000, 0.1250185000, 0.2943806000", \ - "0.0215074000, 0.0228775000, 0.0264431000, 0.0358711000, 0.0605644000, 0.1249566000, 0.2942949000", \ - "0.0211475000, 0.0224928000, 0.0261292000, 0.0354439000, 0.0601030000, 0.1246315000, 0.2942254000", \ - "0.0210592000, 0.0223880000, 0.0259751000, 0.0352739000, 0.0597879000, 0.1243172000, 0.2940121000", \ - "0.0222192000, 0.0235429000, 0.0269932000, 0.0360682000, 0.0603528000, 0.1242280000, 0.2937864000", \ - "0.0253721000, 0.0266246000, 0.0297633000, 0.0385450000, 0.0623568000, 0.1261273000, 0.2942414000"); - } - } - max_capacitance : 0.1702980000; - max_transition : 1.9552060000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0421782000, 0.0448446000, 0.0515205000, 0.0688988000, 0.1126086000, 0.2251632000, 0.5195483000", \ - "0.0460677000, 0.0488645000, 0.0556473000, 0.0731942000, 0.1167532000, 0.2293376000, 0.5236545000", \ - "0.0560682000, 0.0587835000, 0.0657040000, 0.0830487000, 0.1267964000, 0.2394082000, 0.5336773000", \ - "0.0779320000, 0.0805323000, 0.0883653000, 0.1063408000, 0.1500817000, 0.2626107000, 0.5575690000", \ - "0.1070600000, 0.1118676000, 0.1236348000, 0.1497148000, 0.2045251000, 0.3186732000, 0.6132189000", \ - "0.1357297000, 0.1430788000, 0.1604912000, 0.2008994000, 0.2842524000, 0.4406974000, 0.7414501000", \ - "0.1447044000, 0.1553877000, 0.1818583000, 0.2427473000, 0.3687074000, 0.6092759000, 1.0222753000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.1077597000, 0.1146122000, 0.1329025000, 0.1794219000, 0.3004827000, 0.6172912000, 1.4545951000", \ - "0.1122030000, 0.1193507000, 0.1373310000, 0.1846544000, 0.3060347000, 0.6235312000, 1.4590509000", \ - "0.1243176000, 0.1312563000, 0.1495781000, 0.1968545000, 0.3188702000, 0.6367724000, 1.4727223000", \ - "0.1521616000, 0.1588507000, 0.1769476000, 0.2237069000, 0.3463576000, 0.6650661000, 1.5014839000", \ - "0.2083333000, 0.2160067000, 0.2356719000, 0.2827056000, 0.4045544000, 0.7233957000, 1.5616051000", \ - "0.3020498000, 0.3123304000, 0.3376935000, 0.3992075000, 0.5361643000, 0.8557633000, 1.6936080000", \ - "0.4501425000, 0.4670221000, 0.5073584000, 0.5967885000, 0.7828728000, 1.1588791000, 2.0009330000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0345132000, 0.0377862000, 0.0460416000, 0.0681136000, 0.1252731000, 0.2768773000, 0.6770925000", \ - "0.0344206000, 0.0376431000, 0.0460293000, 0.0677340000, 0.1251830000, 0.2770056000, 0.6760086000", \ - "0.0342979000, 0.0373766000, 0.0455346000, 0.0677057000, 0.1252052000, 0.2768502000, 0.6751702000", \ - "0.0440643000, 0.0472779000, 0.0543010000, 0.0728891000, 0.1259966000, 0.2765930000, 0.6763316000", \ - "0.0664321000, 0.0705559000, 0.0803875000, 0.1026884000, 0.1497134000, 0.2820046000, 0.6761625000", \ - "0.1068869000, 0.1128883000, 0.1280160000, 0.1605676000, 0.2237099000, 0.3480481000, 0.6894975000", \ - "0.1765317000, 0.1862124000, 0.2091092000, 0.2601636000, 0.3564893000, 0.5242724000, 0.8424153000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0749059000, 0.0838757000, 0.1077232000, 0.1701075000, 0.3351348000, 0.7685707000, 1.9209885000", \ - "0.0748832000, 0.0839821000, 0.1075642000, 0.1702321000, 0.3350063000, 0.7687551000, 1.9146473000", \ - "0.0749686000, 0.0839391000, 0.1077308000, 0.1701251000, 0.3348740000, 0.7680953000, 1.9122008000", \ - "0.0752623000, 0.0841442000, 0.1077084000, 0.1702528000, 0.3346650000, 0.7682311000, 1.9123556000", \ - "0.0877417000, 0.0954515000, 0.1166256000, 0.1750154000, 0.3351527000, 0.7679956000, 1.9196447000", \ - "0.1245771000, 0.1337512000, 0.1571502000, 0.2147775000, 0.3587766000, 0.7707210000, 1.9134296000", \ - "0.2065131000, 0.2178294000, 0.2465850000, 0.3132428000, 0.4679290000, 0.8363426000, 1.9201192000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0481648000, 0.0508964000, 0.0575923000, 0.0749838000, 0.1185669000, 0.2312125000, 0.5254469000", \ - "0.0525724000, 0.0551779000, 0.0620686000, 0.0794901000, 0.1230784000, 0.2357065000, 0.5299847000", \ - "0.0617031000, 0.0644561000, 0.0713398000, 0.0888223000, 0.1324146000, 0.2450455000, 0.5394982000", \ - "0.0809216000, 0.0839956000, 0.0913732000, 0.1096366000, 0.1537236000, 0.2664791000, 0.5611658000", \ - "0.1104308000, 0.1146466000, 0.1249388000, 0.1484623000, 0.2001534000, 0.3154294000, 0.6106229000", \ - "0.1435571000, 0.1497613000, 0.1657659000, 0.2011905000, 0.2743670000, 0.4187145000, 0.7246746000", \ - "0.1601055000, 0.1704240000, 0.1934932000, 0.2495159000, 0.3646819000, 0.5775646000, 0.9605292000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.1319063000, 0.1391147000, 0.1569770000, 0.2038662000, 0.3252897000, 0.6441560000, 1.4843562000", \ - "0.1368250000, 0.1437715000, 0.1618555000, 0.2084377000, 0.3302663000, 0.6495229000, 1.4915488000", \ - "0.1496144000, 0.1565263000, 0.1743164000, 0.2211661000, 0.3435853000, 0.6629836000, 1.5035843000", \ - "0.1779031000, 0.1839401000, 0.2026484000, 0.2496776000, 0.3721211000, 0.6919266000, 1.5331164000", \ - "0.2368234000, 0.2440104000, 0.2617366000, 0.3084012000, 0.4306861000, 0.7512652000, 1.5927308000", \ - "0.3411076000, 0.3503185000, 0.3726421000, 0.4311761000, 0.5633324000, 0.8838879000, 1.7256736000", \ - "0.5111238000, 0.5251774000, 0.5600302000, 0.6412877000, 0.8172625000, 1.1874211000, 2.0322448000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0344651000, 0.0377197000, 0.0460563000, 0.0678626000, 0.1251703000, 0.2761827000, 0.6752054000", \ - "0.0344762000, 0.0376697000, 0.0460412000, 0.0678919000, 0.1251928000, 0.2766418000, 0.6771525000", \ - "0.0343781000, 0.0374527000, 0.0457460000, 0.0676498000, 0.1251681000, 0.2768928000, 0.6767127000", \ - "0.0398628000, 0.0428339000, 0.0504833000, 0.0702503000, 0.1255673000, 0.2765330000, 0.6767237000", \ - "0.0577241000, 0.0610083000, 0.0695843000, 0.0901340000, 0.1402511000, 0.2796135000, 0.6763860000", \ - "0.0939009000, 0.0987277000, 0.1106227000, 0.1371582000, 0.1932572000, 0.3227529000, 0.6842079000", \ - "0.1599799000, 0.1673012000, 0.1841675000, 0.2229876000, 0.3007408000, 0.4523304000, 0.7833291000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0946506000, 0.1036645000, 0.1276137000, 0.1912633000, 0.3570903000, 0.7965856000, 1.9456299000", \ - "0.0942844000, 0.1034103000, 0.1279215000, 0.1909383000, 0.3575304000, 0.7944250000, 1.9487965000", \ - "0.0944147000, 0.1034481000, 0.1279744000, 0.1909865000, 0.3574378000, 0.7939674000, 1.9456528000", \ - "0.0941961000, 0.1038070000, 0.1277282000, 0.1910446000, 0.3572115000, 0.7934261000, 1.9464892000", \ - "0.1028313000, 0.1114107000, 0.1340359000, 0.1940405000, 0.3575240000, 0.7953779000, 1.9475845000", \ - "0.1393408000, 0.1481917000, 0.1715103000, 0.2295307000, 0.3767050000, 0.7967990000, 1.9461066000", \ - "0.2218860000, 0.2326443000, 0.2606076000, 0.3270681000, 0.4815804000, 0.8572366000, 1.9535267000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0238102000, 0.0263642000, 0.0324772000, 0.0486333000, 0.0900711000, 0.1993605000, 0.4877124000", \ - "0.0277902000, 0.0302305000, 0.0366823000, 0.0529131000, 0.0946057000, 0.2039062000, 0.4923502000", \ - "0.0368435000, 0.0399675000, 0.0466310000, 0.0628950000, 0.1049183000, 0.2145043000, 0.5030907000", \ - "0.0481016000, 0.0525060000, 0.0633899000, 0.0847905000, 0.1287335000, 0.2385377000, 0.5269979000", \ - "0.0577204000, 0.0647832000, 0.0810368000, 0.1156225000, 0.1786106000, 0.2940363000, 0.5825956000", \ - "0.0568766000, 0.0673028000, 0.0924279000, 0.1443947000, 0.2419464000, 0.4100557000, 0.7112809000", \ - "0.0206273000, 0.0368504000, 0.0751351000, 0.1545184000, 0.3044999000, 0.5618455000, 0.9880914000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0776268000, 0.0843415000, 0.1028672000, 0.1497842000, 0.2706490000, 0.5866600000, 1.4195711000", \ - "0.0808056000, 0.0876204000, 0.1061093000, 0.1534174000, 0.2749058000, 0.5917177000, 1.4247628000", \ - "0.0904884000, 0.0976787000, 0.1155453000, 0.1629775000, 0.2851522000, 0.6024315000, 1.4359830000", \ - "0.1176736000, 0.1243782000, 0.1421627000, 0.1879446000, 0.3104513000, 0.6285873000, 1.4629330000", \ - "0.1769812000, 0.1856436000, 0.2068699000, 0.2538618000, 0.3745589000, 0.6923992000, 1.5281303000", \ - "0.2715637000, 0.2849737000, 0.3167447000, 0.3879750000, 0.5287737000, 0.8425899000, 1.6760039000", \ - "0.4248907000, 0.4439305000, 0.4899014000, 0.5960474000, 0.8110466000, 1.2002167000, 2.0265347000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0281387000, 0.0312101000, 0.0393176000, 0.0605236000, 0.1165623000, 0.2645282000, 0.6558970000", \ - "0.0280674000, 0.0311593000, 0.0392974000, 0.0605148000, 0.1164649000, 0.2644246000, 0.6551227000", \ - "0.0323462000, 0.0347385000, 0.0414790000, 0.0609714000, 0.1165996000, 0.2645288000, 0.6558546000", \ - "0.0475514000, 0.0501156000, 0.0564505000, 0.0723483000, 0.1192510000, 0.2644867000, 0.6552427000", \ - "0.0766369000, 0.0797353000, 0.0876672000, 0.1071092000, 0.1500836000, 0.2727831000, 0.6555012000", \ - "0.1284590000, 0.1330619000, 0.1445539000, 0.1719863000, 0.2286338000, 0.3451597000, 0.6716016000", \ - "0.2199751000, 0.2277143000, 0.2442156000, 0.2836971000, 0.3673617000, 0.5258096000, 0.8315629000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0744368000, 0.0836169000, 0.1072532000, 0.1696904000, 0.3335860000, 0.7650389000, 1.9040645000", \ - "0.0745413000, 0.0836190000, 0.1073841000, 0.1698056000, 0.3336421000, 0.7678211000, 1.9051181000", \ - "0.0739211000, 0.0832541000, 0.1071570000, 0.1697464000, 0.3339221000, 0.7656125000, 1.9044162000", \ - "0.0761565000, 0.0845665000, 0.1069964000, 0.1691873000, 0.3337098000, 0.7666996000, 1.9044335000", \ - "0.1038290000, 0.1123534000, 0.1307855000, 0.1820275000, 0.3343954000, 0.7653783000, 1.9094260000", \ - "0.1533883000, 0.1646535000, 0.1907966000, 0.2503169000, 0.3765937000, 0.7675616000, 1.9048139000", \ - "0.2350982000, 0.2513333000, 0.2916893000, 0.3792144000, 0.5427799000, 0.8751275000, 1.9169717000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0300747000, 0.0324039000, 0.0387024000, 0.0545346000, 0.0959780000, 0.2052522000, 0.4935243000", \ - "0.0343471000, 0.0367642000, 0.0430928000, 0.0592286000, 0.1009288000, 0.2101436000, 0.4985832000", \ - "0.0428499000, 0.0454731000, 0.0521105000, 0.0685586000, 0.1103723000, 0.2198901000, 0.5083290000", \ - "0.0553976000, 0.0591527000, 0.0680115000, 0.0878272000, 0.1314502000, 0.2414690000, 0.5301765000", \ - "0.0688261000, 0.0746853000, 0.0886120000, 0.1174621000, 0.1738778000, 0.2901850000, 0.5797512000", \ - "0.0732996000, 0.0828844000, 0.1051163000, 0.1508832000, 0.2367535000, 0.3889890000, 0.6912043000", \ - "0.0427571000, 0.0582965000, 0.0937468000, 0.1675563000, 0.3040153000, 0.5351535000, 0.9274179000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.1027106000, 0.1094347000, 0.1276784000, 0.1742858000, 0.2956839000, 0.6153277000, 1.4588174000", \ - "0.1053944000, 0.1127984000, 0.1308571000, 0.1779493000, 0.2998597000, 0.6191440000, 1.4596803000", \ - "0.1160588000, 0.1223469000, 0.1409346000, 0.1884821000, 0.3107120000, 0.6302186000, 1.4707795000", \ - "0.1433025000, 0.1499635000, 0.1679891000, 0.2139898000, 0.3370249000, 0.6569366000, 1.4979363000", \ - "0.2089540000, 0.2160380000, 0.2349278000, 0.2807745000, 0.4018694000, 0.7217701000, 1.5637728000", \ - "0.3208701000, 0.3321365000, 0.3600268000, 0.4227328000, 0.5580574000, 0.8728545000, 1.7130922000", \ - "0.4989887000, 0.5156974000, 0.5562311000, 0.6519243000, 0.8533469000, 1.2341721000, 2.0639541000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0280265000, 0.0311115000, 0.0392027000, 0.0604056000, 0.1162969000, 0.2644525000, 0.6554606000", \ - "0.0280585000, 0.0311440000, 0.0392156000, 0.0604369000, 0.1164563000, 0.2641612000, 0.6557738000", \ - "0.0299269000, 0.0326947000, 0.0401369000, 0.0605445000, 0.1164621000, 0.2643502000, 0.6551811000", \ - "0.0402163000, 0.0426772000, 0.0492626000, 0.0666896000, 0.1181004000, 0.2643605000, 0.6557598000", \ - "0.0632824000, 0.0660424000, 0.0732132000, 0.0913426000, 0.1369800000, 0.2696605000, 0.6555416000", \ - "0.1085124000, 0.1120579000, 0.1212413000, 0.1438768000, 0.1960338000, 0.3174138000, 0.6685524000", \ - "0.1941800000, 0.1985870000, 0.2106284000, 0.2416853000, 0.3089391000, 0.4515554000, 0.7722415000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0941757000, 0.1033816000, 0.1278126000, 0.1912664000, 0.3570691000, 0.7941625000, 1.9502508000", \ - "0.0944871000, 0.1035352000, 0.1275584000, 0.1909944000, 0.3572316000, 0.7939027000, 1.9468649000", \ - "0.0944391000, 0.1035243000, 0.1277074000, 0.1908827000, 0.3572597000, 0.7940446000, 1.9456268000", \ - "0.0937797000, 0.1027324000, 0.1268958000, 0.1908546000, 0.3572594000, 0.7941831000, 1.9473754000", \ - "0.1154411000, 0.1225956000, 0.1424991000, 0.1979573000, 0.3570234000, 0.7944509000, 1.9517445000", \ - "0.1690734000, 0.1794334000, 0.2044881000, 0.2622857000, 0.3947289000, 0.7958114000, 1.9463886000", \ - "0.2593867000, 0.2751221000, 0.3124466000, 0.3926242000, 0.5563461000, 0.8989355000, 1.9552060000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a22oi_4") { - leakage_power () { - value : 0.0020851000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0303796000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0052827000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0016600000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0038277000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0316658000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0052827000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0034003000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0034013000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0516426000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0052827000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0029795000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0030315000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0726102000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0034066000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0031381000; - when : "A1&A2&B1&!B2"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a22oi"; - cell_leakage_power : 0.0143172700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0083100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178772000, 0.0178987000, 0.0179483000, 0.0179495000, 0.0179525000, 0.0179596000, 0.0179759000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012679300, -0.012695000, -0.012731400, -0.012697500, -0.012619300, -0.012439100, -0.012023600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086130000; - } - pin ("A2") { - capacitance : 0.0086170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156594000, 0.0156545000, 0.0156434000, 0.0156434000, 0.0156435000, 0.0156437000, 0.0156443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015608100, -0.015607000, -0.015604400, -0.015604500, -0.015604800, -0.015605500, -0.015607100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090810000; - } - pin ("B1") { - capacitance : 0.0083380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181848000, 0.0181864000, 0.0181902000, 0.0181943000, 0.0182038000, 0.0182258000, 0.0182763000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012980600, -0.012988800, -0.013007300, -0.012978200, -0.012910700, -0.012755200, -0.012396800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087950000; - } - pin ("B2") { - capacitance : 0.0085430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157805000, 0.0157648000, 0.0157285000, 0.0157282000, 0.0157273000, 0.0157254000, 0.0157209000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015714000, -0.015708500, -0.015695700, -0.015695200, -0.015693800, -0.015690400, -0.015682800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092040000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A2&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0253393000, 0.0238166000, 0.0194834000, 0.0067331000, -0.029981200, -0.137263900, -0.448252100", \ - "0.0250118000, 0.0234531000, 0.0191466000, 0.0064756000, -0.030277500, -0.137523700, -0.448488500", \ - "0.0243290000, 0.0228136000, 0.0185291000, 0.0059329000, -0.030655100, -0.137760300, -0.448838500", \ - "0.0234157000, 0.0219365000, 0.0176373000, 0.0051878000, -0.031252900, -0.138015200, -0.448920400", \ - "0.0227697000, 0.0212915000, 0.0169648000, 0.0043793000, -0.031945300, -0.138336600, -0.449000200", \ - "0.0236092000, 0.0220708000, 0.0176135000, 0.0047512000, -0.032514900, -0.138894100, -0.449434700", \ - "0.0269242000, 0.0253514000, 0.0210235000, 0.0075713000, -0.029903300, -0.138814700, -0.448752700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0402919000, 0.0418603000, 0.0463599000, 0.0593540000, 0.0963766000, 0.2030235000, 0.5105981000", \ - "0.0396315000, 0.0412097000, 0.0457499000, 0.0589367000, 0.0962026000, 0.2030137000, 0.5105751000", \ - "0.0385817000, 0.0401560000, 0.0447798000, 0.0580144000, 0.0956433000, 0.2025323000, 0.5105666000", \ - "0.0377043000, 0.0392728000, 0.0438029000, 0.0569959000, 0.0947207000, 0.2019771000, 0.5101401000", \ - "0.0370570000, 0.0386016000, 0.0431381000, 0.0561964000, 0.0935107000, 0.2009108000, 0.5094441000", \ - "0.0369368000, 0.0385339000, 0.0429972000, 0.0559685000, 0.0932598000, 0.2000615000, 0.5086143000", \ - "0.0364563000, 0.0380043000, 0.0423323000, 0.0551678000, 0.0932039000, 0.2001956000, 0.5080979000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0279718000, 0.0264536000, 0.0220841000, 0.0093661000, -0.027352700, -0.134523600, -0.445687500", \ - "0.0276738000, 0.0261202000, 0.0217565000, 0.0090579000, -0.027753600, -0.134936700, -0.445806000", \ - "0.0271093000, 0.0256049000, 0.0212433000, 0.0086208000, -0.028008200, -0.135231600, -0.446230200", \ - "0.0263951000, 0.0249059000, 0.0205521000, 0.0080843000, -0.028525200, -0.135513800, -0.446425400", \ - "0.0257699000, 0.0242467000, 0.0199182000, 0.0074354000, -0.028796600, -0.135582000, -0.446381300", \ - "0.0263242000, 0.0247945000, 0.0203930000, 0.0076328000, -0.029703900, -0.136231700, -0.446575800", \ - "0.0290966000, 0.0275283000, 0.0229168000, 0.0098408000, -0.027593600, -0.135669800, -0.446629300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0546029000, 0.0560109000, 0.0604943000, 0.0734170000, 0.1105456000, 0.2170325000, 0.5246839000", \ - "0.0539013000, 0.0556769000, 0.0600105000, 0.0729848000, 0.1101896000, 0.2168797000, 0.5244711000", \ - "0.0533042000, 0.0549145000, 0.0595183000, 0.0724907000, 0.1098150000, 0.2165619000, 0.5242626000", \ - "0.0527949000, 0.0543645000, 0.0587675000, 0.0717847000, 0.1092680000, 0.2162712000, 0.5242186000", \ - "0.0521650000, 0.0537193000, 0.0582479000, 0.0712470000, 0.1084787000, 0.2156312000, 0.5236947000", \ - "0.0521116000, 0.0536901000, 0.0582176000, 0.0713985000, 0.1083180000, 0.2151139000, 0.5234957000", \ - "0.0517065000, 0.0531488000, 0.0576538000, 0.0706600000, 0.1084715000, 0.2156389000, 0.5234586000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0099202000, 0.0085240000, 0.0043539000, -0.008147200, -0.045132000, -0.152700600, -0.464295100", \ - "0.0093598000, 0.0080191000, 0.0040004000, -0.008269100, -0.044987300, -0.152402700, -0.463908700", \ - "0.0086646000, 0.0073704000, 0.0032791000, -0.008713100, -0.045064400, -0.152192600, -0.463572900", \ - "0.0076887000, 0.0063839000, 0.0025116000, -0.009553400, -0.045594400, -0.152355600, -0.463497600", \ - "0.0076197000, 0.0061578000, 0.0019488000, -0.010198400, -0.046345500, -0.152799600, -0.463589300", \ - "0.0089823000, 0.0074544000, 0.0029330000, -0.009858200, -0.046881000, -0.153635800, -0.464135200", \ - "0.0133372000, 0.0115279000, 0.0066488000, -0.007016800, -0.045056400, -0.151575400, -0.464439800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0286357000, 0.0302416000, 0.0349134000, 0.0481555000, 0.0853579000, 0.1918005000, 0.4997312000", \ - "0.0277371000, 0.0293301000, 0.0339826000, 0.0473716000, 0.0851219000, 0.1918103000, 0.4995425000", \ - "0.0263707000, 0.0280376000, 0.0328773000, 0.0461488000, 0.0842712000, 0.1913577000, 0.4993692000", \ - "0.0256030000, 0.0272195000, 0.0318664000, 0.0452329000, 0.0829353000, 0.1906211000, 0.4990588000", \ - "0.0259316000, 0.0274899000, 0.0319098000, 0.0449138000, 0.0821702000, 0.1894037000, 0.4985164000", \ - "0.0269195000, 0.0284220000, 0.0327692000, 0.0454918000, 0.0819551000, 0.1878909000, 0.4974165000", \ - "0.0314679000, 0.0328687000, 0.0369521000, 0.0489235000, 0.0849531000, 0.1903373000, 0.4950249000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0131204000, 0.0117030000, 0.0074898000, -0.005056400, -0.042057800, -0.149630300, -0.461187300", \ - "0.0125771000, 0.0112149000, 0.0071690000, -0.005139900, -0.041888900, -0.149302900, -0.460822900", \ - "0.0116771000, 0.0103438000, 0.0063885000, -0.005615400, -0.041979000, -0.149140300, -0.460534700", \ - "0.0106193000, 0.0092544000, 0.0052450000, -0.006628200, -0.042569300, -0.149298900, -0.460446000", \ - "0.0106015000, 0.0091561000, 0.0046974000, -0.007697900, -0.043541100, -0.149831900, -0.460566800", \ - "0.0108807000, 0.0093532000, 0.0049454000, -0.007693000, -0.044258700, -0.150816700, -0.461151000", \ - "0.0145946000, 0.0129212000, 0.0081711000, -0.005213300, -0.042997600, -0.150556700, -0.461570000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0431284000, 0.0446411000, 0.0492576000, 0.0621391000, 0.0992362000, 0.2059276000, 0.5134908000", \ - "0.0422546000, 0.0438113000, 0.0483958000, 0.0615141000, 0.0988625000, 0.2055256000, 0.5132624000", \ - "0.0415875000, 0.0429713000, 0.0476036000, 0.0607664000, 0.0983289000, 0.2052475000, 0.5132364000", \ - "0.0408873000, 0.0425818000, 0.0468208000, 0.0599476000, 0.0975134000, 0.2048133000, 0.5130078000", \ - "0.0405113000, 0.0420736000, 0.0466158000, 0.0595140000, 0.0968406000, 0.2042165000, 0.5125959000", \ - "0.0439760000, 0.0454630000, 0.0478574000, 0.0606996000, 0.0973025000, 0.2038405000, 0.5123072000", \ - "0.0479204000, 0.0492427000, 0.0530556000, 0.0653258000, 0.1012893000, 0.2072600000, 0.5150428000"); - } - } - max_capacitance : 0.2938940000; - max_transition : 1.9330300000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0417445000, 0.0435681000, 0.0485145000, 0.0619497000, 0.0985133000, 0.2003095000, 0.4901049000", \ - "0.0458038000, 0.0475463000, 0.0524354000, 0.0660325000, 0.1025963000, 0.2043993000, 0.4942327000", \ - "0.0554042000, 0.0571813000, 0.0622079000, 0.0758136000, 0.1123753000, 0.2143615000, 0.5041227000", \ - "0.0770916000, 0.0792248000, 0.0849485000, 0.0993265000, 0.1358835000, 0.2372621000, 0.5274726000", \ - "0.1041311000, 0.1072230000, 0.1156826000, 0.1368496000, 0.1862697000, 0.2923346000, 0.5813445000", \ - "0.1277344000, 0.1324649000, 0.1453635000, 0.1775102000, 0.2529581000, 0.4045462000, 0.7077506000", \ - "0.1215629000, 0.1286769000, 0.1480033000, 0.1989488000, 0.3141817000, 0.5482430000, 0.9758004000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1164222000, 0.1210808000, 0.1345229000, 0.1723089000, 0.2790601000, 0.5843661000, 1.4653841000", \ - "0.1209319000, 0.1255380000, 0.1388080000, 0.1774753000, 0.2847454000, 0.5904908000, 1.4716270000", \ - "0.1326454000, 0.1375862000, 0.1509966000, 0.1898092000, 0.2977342000, 0.6043214000, 1.4864336000", \ - "0.1623014000, 0.1668592000, 0.1806140000, 0.2189379000, 0.3271789000, 0.6349473000, 1.5178909000", \ - "0.2251698000, 0.2303825000, 0.2444336000, 0.2823281000, 0.3895800000, 0.6978479000, 1.5811403000", \ - "0.3346391000, 0.3413004000, 0.3599990000, 0.4094291000, 0.5310003000, 0.8397888000, 1.7239398000", \ - "0.5172891000, 0.5269347000, 0.5561922000, 0.6296463000, 0.7973325000, 1.1625448000, 2.0547104000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0340878000, 0.0361235000, 0.0422447000, 0.0592769000, 0.1086477000, 0.2511921000, 0.6649156000", \ - "0.0339891000, 0.0361047000, 0.0421220000, 0.0593126000, 0.1084602000, 0.2512084000, 0.6650505000", \ - "0.0337524000, 0.0358148000, 0.0417741000, 0.0588173000, 0.1084213000, 0.2511625000, 0.6650423000", \ - "0.0430323000, 0.0451689000, 0.0508253000, 0.0651425000, 0.1099980000, 0.2509584000, 0.6655157000", \ - "0.0634686000, 0.0662911000, 0.0739823000, 0.0930318000, 0.1371711000, 0.2590482000, 0.6650379000", \ - "0.1025690000, 0.1067395000, 0.1178916000, 0.1449141000, 0.2048187000, 0.3308241000, 0.6837850000", \ - "0.1706656000, 0.1772532000, 0.1956361000, 0.2374549000, 0.3231373000, 0.4923946000, 0.8448724000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0779312000, 0.0839445000, 0.1010797000, 0.1512969000, 0.2956210000, 0.7134809000, 1.9131829000", \ - "0.0779733000, 0.0839049000, 0.1011784000, 0.1511343000, 0.2954056000, 0.7137815000, 1.9184689000", \ - "0.0779562000, 0.0839733000, 0.1012305000, 0.1509693000, 0.2955611000, 0.7106135000, 1.9199820000", \ - "0.0780272000, 0.0839978000, 0.1013013000, 0.1510399000, 0.2955087000, 0.7138344000, 1.9173543000", \ - "0.0873177000, 0.0924887000, 0.1082702000, 0.1552651000, 0.2962257000, 0.7142522000, 1.9131268000", \ - "0.1226244000, 0.1287622000, 0.1455350000, 0.1923661000, 0.3182650000, 0.7143448000, 1.9134858000", \ - "0.2027936000, 0.2099108000, 0.2309023000, 0.2855137000, 0.4225924000, 0.7759873000, 1.9221404000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0474738000, 0.0491836000, 0.0541107000, 0.0676458000, 0.1042513000, 0.2059293000, 0.4956935000", \ - "0.0517628000, 0.0534818000, 0.0583649000, 0.0719101000, 0.1085038000, 0.2102347000, 0.4997607000", \ - "0.0602761000, 0.0620712000, 0.0669906000, 0.0805443000, 0.1171903000, 0.2190245000, 0.5088149000", \ - "0.0778102000, 0.0797662000, 0.0851350000, 0.0994629000, 0.1365885000, 0.2387385000, 0.5286689000", \ - "0.1045198000, 0.1068015000, 0.1139547000, 0.1328730000, 0.1771505000, 0.2833234000, 0.5745071000", \ - "0.1312719000, 0.1352654000, 0.1462351000, 0.1740410000, 0.2381320000, 0.3732429000, 0.6790359000", \ - "0.1339625000, 0.1401325000, 0.1569483000, 0.2007458000, 0.3010077000, 0.5036428000, 0.8899688000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1403011000, 0.1449765000, 0.1580999000, 0.1948136000, 0.3006424000, 0.6038869000, 1.4792638000", \ - "0.1448539000, 0.1488527000, 0.1630592000, 0.1999835000, 0.3061056000, 0.6093294000, 1.4862901000", \ - "0.1579123000, 0.1623242000, 0.1756708000, 0.2126936000, 0.3194477000, 0.6229902000, 1.4983709000", \ - "0.1864067000, 0.1915839000, 0.2049051000, 0.2424699000, 0.3491344000, 0.6530611000, 1.5273720000", \ - "0.2475735000, 0.2526837000, 0.2657055000, 0.3028457000, 0.4097611000, 0.7138452000, 1.5882202000", \ - "0.3585175000, 0.3649444000, 0.3819160000, 0.4265593000, 0.5437800000, 0.8484420000, 1.7242338000", \ - "0.5465813000, 0.5558322000, 0.5802979000, 0.6451184000, 0.7994862000, 1.1551017000, 2.0362965000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0340117000, 0.0361221000, 0.0421537000, 0.0593012000, 0.1083913000, 0.2512797000, 0.6646033000", \ - "0.0339587000, 0.0360765000, 0.0421134000, 0.0592495000, 0.1085006000, 0.2511415000, 0.6641467000", \ - "0.0338392000, 0.0359198000, 0.0419009000, 0.0590302000, 0.1084856000, 0.2510722000, 0.6653167000", \ - "0.0391383000, 0.0411208000, 0.0467295000, 0.0623502000, 0.1095170000, 0.2512552000, 0.6651164000", \ - "0.0552646000, 0.0573132000, 0.0636014000, 0.0805666000, 0.1257285000, 0.2559055000, 0.6643457000", \ - "0.0894548000, 0.0926127000, 0.1008802000, 0.1225156000, 0.1734830000, 0.3007174000, 0.6756755000", \ - "0.1529864000, 0.1575951000, 0.1698229000, 0.2010118000, 0.2692203000, 0.4199210000, 0.7748576000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0995492000, 0.1053329000, 0.1224722000, 0.1724776000, 0.3162268000, 0.7306545000, 1.9279787000", \ - "0.0992519000, 0.1057550000, 0.1224851000, 0.1724560000, 0.3161712000, 0.7313938000, 1.9287429000", \ - "0.0992181000, 0.1051971000, 0.1228983000, 0.1723709000, 0.3161570000, 0.7293468000, 1.9263071000", \ - "0.0996254000, 0.1054479000, 0.1224923000, 0.1726829000, 0.3163019000, 0.7324892000, 1.9253423000", \ - "0.1060969000, 0.1115181000, 0.1276325000, 0.1752453000, 0.3161072000, 0.7321900000, 1.9278825000", \ - "0.1397020000, 0.1457288000, 0.1623346000, 0.2094295000, 0.3365938000, 0.7337920000, 1.9310664000", \ - "0.2176954000, 0.2245951000, 0.2445315000, 0.2978962000, 0.4341381000, 0.7934992000, 1.9312560000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0226582000, 0.0243244000, 0.0286888000, 0.0411025000, 0.0756606000, 0.1747282000, 0.4606694000", \ - "0.0264655000, 0.0281009000, 0.0326891000, 0.0452622000, 0.0800505000, 0.1792922000, 0.4653158000", \ - "0.0350289000, 0.0370553000, 0.0425992000, 0.0551419000, 0.0902112000, 0.1897405000, 0.4758414000", \ - "0.0446733000, 0.0479641000, 0.0558396000, 0.0748424000, 0.1139526000, 0.2133936000, 0.4995565000", \ - "0.0505388000, 0.0554023000, 0.0681669000, 0.0979096000, 0.1572587000, 0.2685965000, 0.5544695000", \ - "0.0411346000, 0.0486037000, 0.0681659000, 0.1137236000, 0.2054904000, 0.3736105000, 0.6819510000", \ - "-0.014818300, -0.003589400, 0.0262403000, 0.0971367000, 0.2386578000, 0.4962242000, 0.9470810000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0818341000, 0.0867306000, 0.1004277000, 0.1386571000, 0.2455902000, 0.5505721000, 1.4286211000", \ - "0.0846807000, 0.0894617000, 0.1032309000, 0.1417232000, 0.2495788000, 0.5553151000, 1.4350769000", \ - "0.0937343000, 0.0986598000, 0.1127356000, 0.1513680000, 0.2598005000, 0.5661975000, 1.4453764000", \ - "0.1221416000, 0.1268239000, 0.1401532000, 0.1785294000, 0.2859888000, 0.5936474000, 1.4735303000", \ - "0.1870806000, 0.1928977000, 0.2079373000, 0.2469413000, 0.3513157000, 0.6607772000, 1.5411797000", \ - "0.2931430000, 0.3021253000, 0.3253662000, 0.3841138000, 0.5130201000, 0.8160209000, 1.6963490000", \ - "0.4714806000, 0.4841497000, 0.5203987000, 0.6081065000, 0.8046320000, 1.1918719000, 2.0601643000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0271302000, 0.0291179000, 0.0348428000, 0.0514067000, 0.0990824000, 0.2364862000, 0.6343001000", \ - "0.0270728000, 0.0290501000, 0.0348112000, 0.0513865000, 0.0989437000, 0.2361088000, 0.6341374000", \ - "0.0319334000, 0.0334337000, 0.0378968000, 0.0524807000, 0.0990795000, 0.2361028000, 0.6343665000", \ - "0.0467995000, 0.0484578000, 0.0534186000, 0.0659123000, 0.1044442000, 0.2362197000, 0.6341406000", \ - "0.0759947000, 0.0779900000, 0.0836371000, 0.0993737000, 0.1385738000, 0.2490606000, 0.6337847000", \ - "0.1286285000, 0.1314959000, 0.1395542000, 0.1611897000, 0.2128991000, 0.3278816000, 0.6554654000", \ - "0.2214663000, 0.2251100000, 0.2379311000, 0.2688567000, 0.3448621000, 0.5052693000, 0.8229272000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0761138000, 0.0821411000, 0.0993721000, 0.1496950000, 0.2937522000, 0.7106578000, 1.9181785000", \ - "0.0759807000, 0.0820037000, 0.0994890000, 0.1494486000, 0.2938463000, 0.7099293000, 1.9193587000", \ - "0.0755900000, 0.0817584000, 0.0991945000, 0.1492965000, 0.2936813000, 0.7096602000, 1.9119042000", \ - "0.0766757000, 0.0821098000, 0.0984037000, 0.1488819000, 0.2935907000, 0.7105493000, 1.9130819000", \ - "0.1027698000, 0.1077609000, 0.1204742000, 0.1609890000, 0.2943774000, 0.7121881000, 1.9127455000", \ - "0.1516066000, 0.1588885000, 0.1785447000, 0.2270490000, 0.3396299000, 0.7117802000, 1.9121646000", \ - "0.2340882000, 0.2450353000, 0.2752829000, 0.3475464000, 0.4984683000, 0.8203409000, 1.9191428000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0286168000, 0.0302352000, 0.0346828000, 0.0470228000, 0.0814442000, 0.1805408000, 0.4665177000", \ - "0.0327393000, 0.0343488000, 0.0388934000, 0.0514307000, 0.0861342000, 0.1853438000, 0.4713586000", \ - "0.0404568000, 0.0422719000, 0.0472108000, 0.0601012000, 0.0950977000, 0.1944753000, 0.4806038000", \ - "0.0510488000, 0.0535689000, 0.0601617000, 0.0767240000, 0.1144013000, 0.2144196000, 0.5010608000", \ - "0.0608858000, 0.0648255000, 0.0754091000, 0.0992794000, 0.1505566000, 0.2594478000, 0.5467063000", \ - "0.0578355000, 0.0642254000, 0.0806415000, 0.1190568000, 0.1975495000, 0.3450590000, 0.6504912000", \ - "0.0107234000, 0.0209699000, 0.0476450000, 0.1098294000, 0.2351581000, 0.4604083000, 0.8599036000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1082230000, 0.1128985000, 0.1260021000, 0.1629210000, 0.2691893000, 0.5723120000, 1.4489692000", \ - "0.1111734000, 0.1157078000, 0.1291604000, 0.1663824000, 0.2728969000, 0.5763287000, 1.4512963000", \ - "0.1213297000, 0.1257096000, 0.1390407000, 0.1768964000, 0.2839203000, 0.5877378000, 1.4631052000", \ - "0.1481713000, 0.1531951000, 0.1650106000, 0.2029967000, 0.3101978000, 0.6147316000, 1.4891648000", \ - "0.2159227000, 0.2207934000, 0.2340453000, 0.2708777000, 0.3760712000, 0.6806518000, 1.5560234000", \ - "0.3354750000, 0.3426383000, 0.3623801000, 0.4140233000, 0.5349186000, 0.8361730000, 1.7102157000", \ - "0.5304325000, 0.5410480000, 0.5707648000, 0.6471319000, 0.8287259000, 1.1998541000, 2.0650193000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0271085000, 0.0290808000, 0.0348123000, 0.0513670000, 0.0989957000, 0.2360353000, 0.6343288000", \ - "0.0271474000, 0.0291171000, 0.0348236000, 0.0513541000, 0.0990049000, 0.2361856000, 0.6340432000", \ - "0.0292271000, 0.0309813000, 0.0361743000, 0.0518462000, 0.0990294000, 0.2363313000, 0.6337351000", \ - "0.0392879000, 0.0408697000, 0.0455711000, 0.0592449000, 0.1019316000, 0.2360102000, 0.6335341000", \ - "0.0617096000, 0.0635309000, 0.0685524000, 0.0827801000, 0.1229871000, 0.2438975000, 0.6335307000", \ - "0.1064480000, 0.1087860000, 0.1150951000, 0.1329393000, 0.1779336000, 0.2949763000, 0.6493002000", \ - "0.1924056000, 0.1948004000, 0.2029130000, 0.2260323000, 0.2856071000, 0.4205707000, 0.7542081000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0993889000, 0.1051368000, 0.1229124000, 0.1723519000, 0.3160406000, 0.7294441000, 1.9306530000", \ - "0.0990583000, 0.1051396000, 0.1224240000, 0.1724492000, 0.3161502000, 0.7304130000, 1.9322841000", \ - "0.0992892000, 0.1050649000, 0.1226380000, 0.1723956000, 0.3163194000, 0.7298038000, 1.9323505000", \ - "0.0983218000, 0.1043340000, 0.1215959000, 0.1721562000, 0.3169159000, 0.7295715000, 1.9249191000", \ - "0.1174946000, 0.1222487000, 0.1366366000, 0.1801790000, 0.3164289000, 0.7307575000, 1.9295123000", \ - "0.1700676000, 0.1770157000, 0.1965383000, 0.2435186000, 0.3573708000, 0.7333417000, 1.9313051000", \ - "0.2592366000, 0.2695661000, 0.2966724000, 0.3631665000, 0.5132976000, 0.8368187000, 1.9330302000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2o_1") { - leakage_power () { - value : 0.0023499000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0023499000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0016457000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0023499000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0078802000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0076079000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0022078000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0081152000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0074059000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0071336000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0017335000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0076408000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0071031000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0068308000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0014307000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0073381000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a2bb2o"; - cell_leakage_power : 0.0050702070; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0013830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084833000, 0.0084129000, 0.0082505000, 0.0082609000, 0.0082846000, 0.0083394000, 0.0084656000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024068000, 0.0023673000, 0.0022761000, 0.0023179000, 0.0024144000, 0.0026367000, 0.0031491000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014180000; - } - pin ("A2_N") { - capacitance : 0.0014370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077209000, 0.0076270000, 0.0074107000, 0.0074649000, 0.0075898000, 0.0078778000, 0.0085417000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017582000, 0.0017106000, 0.0016008000, 0.0016448000, 0.0017460000, 0.0019795000, 0.0025176000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015300000; - } - pin ("B1") { - capacitance : 0.0014910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020135000, 0.0020132000, 0.0020127000, 0.0020123000, 0.0020116000, 0.0020098000, 0.0020058000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002013000, -0.002011500, -0.002008200, -0.002008600, -0.002009500, -0.002011800, -0.002016900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015320000; - } - pin ("B2") { - capacitance : 0.0015660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022268000, 0.0022242000, 0.0022182000, 0.0022189000, 0.0022204000, 0.0022240000, 0.0022322000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002215600, -0.002216500, -0.002218400, -0.002217800, -0.002216300, -0.002213000, -0.002205400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015970000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (!A1_N&!A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0087523000, 0.0076176000, 0.0048593000, -0.003020000, -0.025323000, -0.085519100, -0.243650600", \ - "0.0087484000, 0.0075980000, 0.0048924000, -0.003010800, -0.025335600, -0.085545600, -0.243660100", \ - "0.0087291000, 0.0076121000, 0.0048297000, -0.003077300, -0.025414400, -0.085601300, -0.243719300", \ - "0.0083980000, 0.0072837000, 0.0045357000, -0.003351800, -0.025690600, -0.085888600, -0.243992600", \ - "0.0082322000, 0.0070844000, 0.0043180000, -0.003538300, -0.025924700, -0.086118200, -0.244230300", \ - "0.0096323000, 0.0083147000, 0.0049648000, -0.003768000, -0.026157000, -0.086388800, -0.244491800", \ - "0.0103904000, 0.0091690000, 0.0057247000, -0.002947700, -0.025866100, -0.086343700, -0.244559200"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0098078000, 0.0112869000, 0.0149609000, 0.0241101000, 0.0474767000, 0.1073410000, 0.2641578000", \ - "0.0097327000, 0.0112136000, 0.0149037000, 0.0240632000, 0.0472211000, 0.1072867000, 0.2641400000", \ - "0.0098034000, 0.0112840000, 0.0149692000, 0.0241325000, 0.0472960000, 0.1072931000, 0.2632272000", \ - "0.0097162000, 0.0111918000, 0.0148799000, 0.0240398000, 0.0471987000, 0.1071954000, 0.2631475000", \ - "0.0095577000, 0.0110342000, 0.0147146000, 0.0238791000, 0.0470311000, 0.1070573000, 0.2630347000", \ - "0.0092180000, 0.0107224000, 0.0144660000, 0.0236553000, 0.0468252000, 0.1068161000, 0.2639678000", \ - "0.0098958000, 0.0112438000, 0.0147282000, 0.0237496000, 0.0468884000, 0.1067224000, 0.2630976000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0087160000, 0.0076388000, 0.0048706000, -0.002964200, -0.025277600, -0.085521900, -0.243677700", \ - "0.0087480000, 0.0076465000, 0.0049086000, -0.002969700, -0.025312400, -0.085544600, -0.243682000", \ - "0.0087069000, 0.0076189000, 0.0048445000, -0.003027100, -0.025364100, -0.085584400, -0.243747100", \ - "0.0084461000, 0.0073606000, 0.0045855000, -0.003295500, -0.025632100, -0.085840500, -0.244004400", \ - "0.0081038000, 0.0070236000, 0.0042693000, -0.003599300, -0.025961700, -0.086183700, -0.244304000", \ - "0.0098839000, 0.0085753000, 0.0052098000, -0.003572600, -0.026062400, -0.086310200, -0.244442500", \ - "0.0105762000, 0.0093718000, 0.0059221000, -0.002758700, -0.025683100, -0.086164300, -0.244389300"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0095495000, 0.0110214000, 0.0146970000, 0.0238619000, 0.0470261000, 0.1069896000, 0.2639792000", \ - "0.0094495000, 0.0109175000, 0.0146046000, 0.0237571000, 0.0471285000, 0.1069737000, 0.2637830000", \ - "0.0095109000, 0.0109884000, 0.0146774000, 0.0238382000, 0.0469970000, 0.1069910000, 0.2629219000", \ - "0.0093819000, 0.0108422000, 0.0145427000, 0.0236889000, 0.0468358000, 0.1069051000, 0.2636946000", \ - "0.0091456000, 0.0106057000, 0.0142930000, 0.0234428000, 0.0468098000, 0.1066663000, 0.2634652000", \ - "0.0088773000, 0.0103428000, 0.0141228000, 0.0233025000, 0.0464227000, 0.1063201000, 0.2623771000", \ - "0.0095329000, 0.0108891000, 0.0143544000, 0.0233358000, 0.0464825000, 0.1065082000, 0.2630520000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0098643000, 0.0087447000, 0.0059680000, -0.001920400, -0.024280700, -0.084517900, -0.242674800", \ - "0.0099167000, 0.0087669000, 0.0059231000, -0.001947800, -0.024301100, -0.084560700, -0.242736400", \ - "0.0097369000, 0.0085830000, 0.0057953000, -0.002049200, -0.024384500, -0.084644200, -0.242816500", \ - "0.0097232000, 0.0085677000, 0.0057811000, -0.002141900, -0.024502300, -0.084748900, -0.242917000", \ - "0.0095297000, 0.0084189000, 0.0056127000, -0.002277500, -0.024636900, -0.084862200, -0.243022600", \ - "0.0094301000, 0.0082827000, 0.0055660000, -0.002276200, -0.024668700, -0.084907900, -0.243065800", \ - "0.0120041000, 0.0106375000, 0.0075707000, -0.001373000, -0.024566400, -0.084825400, -0.242976800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0104504000, 0.0118155000, 0.0154300000, 0.0245337000, 0.0478204000, 0.1083321000, 0.2656914000", \ - "0.0103905000, 0.0117709000, 0.0153738000, 0.0245006000, 0.0477457000, 0.1083496000, 0.2655433000", \ - "0.0103128000, 0.0117089000, 0.0153137000, 0.0244024000, 0.0478736000, 0.1078403000, 0.2643326000", \ - "0.0102668000, 0.0116314000, 0.0152046000, 0.0243133000, 0.0475556000, 0.1077307000, 0.2642367000", \ - "0.0101285000, 0.0115274000, 0.0150661000, 0.0240617000, 0.0473792000, 0.1075324000, 0.2639819000", \ - "0.0104227000, 0.0117372000, 0.0151764000, 0.0239319000, 0.0472469000, 0.1072049000, 0.2652817000", \ - "0.0108988000, 0.0122311000, 0.0155917000, 0.0245348000, 0.0476783000, 0.1082019000, 0.2634508000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0082929000, 0.0071750000, 0.0044037000, -0.003471100, -0.025870300, -0.086162500, -0.244451400", \ - "0.0081500000, 0.0070517000, 0.0043081000, -0.003533500, -0.025977200, -0.086301200, -0.244530500", \ - "0.0079903000, 0.0068988000, 0.0041510000, -0.003752800, -0.026148200, -0.086463500, -0.244680800", \ - "0.0078590000, 0.0067611000, 0.0039727000, -0.003901100, -0.026314100, -0.086625500, -0.244849000", \ - "0.0076990000, 0.0065777000, 0.0038164000, -0.004125200, -0.026530300, -0.086823500, -0.245029500", \ - "0.0074394000, 0.0063423000, 0.0035966000, -0.004252700, -0.026609200, -0.086892400, -0.245092200", \ - "0.0100105000, 0.0086317000, 0.0051517000, -0.003698200, -0.026751600, -0.086929600, -0.245055600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0107427000, 0.0121451000, 0.0157183000, 0.0248281000, 0.0481092000, 0.1086390000, 0.2657433000", \ - "0.0106490000, 0.0120554000, 0.0156665000, 0.0247652000, 0.0480048000, 0.1081546000, 0.2646759000", \ - "0.0105830000, 0.0119780000, 0.0155806000, 0.0246555000, 0.0479412000, 0.1080404000, 0.2646025000", \ - "0.0104981000, 0.0118747000, 0.0154420000, 0.0244781000, 0.0477671000, 0.1079064000, 0.2645007000", \ - "0.0104297000, 0.0118267000, 0.0153696000, 0.0242081000, 0.0474884000, 0.1076919000, 0.2643321000", \ - "0.0107857000, 0.0120670000, 0.0154967000, 0.0241846000, 0.0474653000, 0.1073070000, 0.2639786000", \ - "0.0115156000, 0.0127828000, 0.0161375000, 0.0249622000, 0.0480433000, 0.1084115000, 0.2638571000"); - } - } - max_capacitance : 0.1583960000; - max_transition : 1.5038910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2401693000, 0.2493548000, 0.2679793000, 0.3024145000, 0.3678690000, 0.5034463000, 0.8305054000", \ - "0.2447132000, 0.2539161000, 0.2724928000, 0.3073226000, 0.3726284000, 0.5080832000, 0.8349749000", \ - "0.2542568000, 0.2634277000, 0.2819840000, 0.3168412000, 0.3820896000, 0.5178049000, 0.8446571000", \ - "0.2712983000, 0.2804712000, 0.2989582000, 0.3338641000, 0.3989583000, 0.5346795000, 0.8614905000", \ - "0.2948863000, 0.3040104000, 0.3226611000, 0.3573511000, 0.4226513000, 0.5583752000, 0.8851008000", \ - "0.3212151000, 0.3303463000, 0.3488664000, 0.3834036000, 0.4484397000, 0.5834673000, 0.9103276000", \ - "0.3286811000, 0.3379137000, 0.3564564000, 0.3912080000, 0.4565321000, 0.5918982000, 0.9178266000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2152600000, 0.2224640000, 0.2388954000, 0.2768726000, 0.3726678000, 0.6193081000, 1.2639007000", \ - "0.2192364000, 0.2266038000, 0.2429385000, 0.2809767000, 0.3765759000, 0.6233660000, 1.2681691000", \ - "0.2309429000, 0.2383118000, 0.2546381000, 0.2926834000, 0.3881034000, 0.6342515000, 1.2761913000", \ - "0.2577709000, 0.2651272000, 0.2814539000, 0.3194838000, 0.4148649000, 0.6610918000, 1.3031100000", \ - "0.3175896000, 0.3249577000, 0.3412947000, 0.3793323000, 0.4748959000, 0.7213551000, 1.3630582000", \ - "0.4312468000, 0.4387641000, 0.4553227000, 0.4935656000, 0.5892302000, 0.8355580000, 1.4806697000", \ - "0.6267110000, 0.6349958000, 0.6523330000, 0.6908285000, 0.7870977000, 1.0337911000, 1.6751083000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0370043000, 0.0424336000, 0.0549129000, 0.0822966000, 0.1412827000, 0.2947715000, 0.7208776000", \ - "0.0370652000, 0.0424513000, 0.0556521000, 0.0814312000, 0.1415204000, 0.2935506000, 0.7161081000", \ - "0.0365976000, 0.0425105000, 0.0557486000, 0.0810208000, 0.1413713000, 0.2941583000, 0.7175806000", \ - "0.0370561000, 0.0430025000, 0.0556802000, 0.0810929000, 0.1414463000, 0.2931524000, 0.7164850000", \ - "0.0369911000, 0.0425025000, 0.0553063000, 0.0822251000, 0.1412256000, 0.2941353000, 0.7172899000", \ - "0.0370030000, 0.0423128000, 0.0547174000, 0.0811716000, 0.1408911000, 0.2939702000, 0.7163088000", \ - "0.0367556000, 0.0427399000, 0.0548645000, 0.0810540000, 0.1415093000, 0.2936243000, 0.7115464000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0253525000, 0.0319003000, 0.0494545000, 0.0985606000, 0.2320043000, 0.5826000000, 1.5008297000", \ - "0.0253754000, 0.0318460000, 0.0494953000, 0.0986141000, 0.2318959000, 0.5829062000, 1.5011448000", \ - "0.0253607000, 0.0318327000, 0.0494743000, 0.0986954000, 0.2316375000, 0.5827573000, 1.5017443000", \ - "0.0253480000, 0.0318413000, 0.0494911000, 0.0988149000, 0.2318492000, 0.5826223000, 1.5022029000", \ - "0.0254770000, 0.0319497000, 0.0495761000, 0.0988501000, 0.2320822000, 0.5819380000, 1.5024622000", \ - "0.0270014000, 0.0332396000, 0.0505174000, 0.0993906000, 0.2323064000, 0.5813207000, 1.5002067000", \ - "0.0306125000, 0.0363845000, 0.0529004000, 0.1004396000, 0.2335832000, 0.5817904000, 1.4989637000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2362244000, 0.2453956000, 0.2639005000, 0.2986982000, 0.3634044000, 0.4987780000, 0.8257701000", \ - "0.2408444000, 0.2499634000, 0.2685676000, 0.3032349000, 0.3685215000, 0.5038508000, 0.8308147000", \ - "0.2502123000, 0.2593510000, 0.2778923000, 0.3126018000, 0.3779443000, 0.5133500000, 0.8402816000", \ - "0.2659673000, 0.2751058000, 0.2936517000, 0.3283483000, 0.3937000000, 0.5291336000, 0.8560735000", \ - "0.2854594000, 0.2944701000, 0.3130834000, 0.3477675000, 0.4129022000, 0.5485071000, 0.8751579000", \ - "0.3028054000, 0.3120058000, 0.3304429000, 0.3652501000, 0.4303779000, 0.5656488000, 0.8927339000", \ - "0.2990847000, 0.3082899000, 0.3268235000, 0.3615369000, 0.4268702000, 0.5622718000, 0.8889014000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2057366000, 0.2130323000, 0.2293715000, 0.2674337000, 0.3631660000, 0.6096329000, 1.2554007000", \ - "0.2076504000, 0.2149973000, 0.2313009000, 0.2692898000, 0.3651342000, 0.6117245000, 1.2564587000", \ - "0.2171386000, 0.2245113000, 0.2408185000, 0.2788557000, 0.3743433000, 0.6206241000, 1.2624146000", \ - "0.2446492000, 0.2520047000, 0.2683016000, 0.3062866000, 0.4021573000, 0.6487708000, 1.2932380000", \ - "0.3109229000, 0.3182985000, 0.3345942000, 0.3725764000, 0.4683923000, 0.7151072000, 1.3587975000", \ - "0.4337755000, 0.4413586000, 0.4579892000, 0.4961968000, 0.5918381000, 0.8388025000, 1.4803839000", \ - "0.6328756000, 0.6413581000, 0.6589198000, 0.6975389000, 0.7938499000, 1.0403362000, 1.6821393000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0364445000, 0.0423605000, 0.0546742000, 0.0807505000, 0.1409950000, 0.2942822000, 0.7202403000", \ - "0.0369180000, 0.0422952000, 0.0554933000, 0.0806716000, 0.1406259000, 0.2935515000, 0.7162201000", \ - "0.0367395000, 0.0428006000, 0.0546652000, 0.0805631000, 0.1410893000, 0.2939033000, 0.7201220000", \ - "0.0367398000, 0.0427618000, 0.0547115000, 0.0805376000, 0.1410836000, 0.2938802000, 0.7203366000", \ - "0.0367069000, 0.0424255000, 0.0551119000, 0.0813288000, 0.1408035000, 0.2936447000, 0.7169922000", \ - "0.0369095000, 0.0427364000, 0.0548178000, 0.0818798000, 0.1405760000, 0.2941171000, 0.7197979000", \ - "0.0366959000, 0.0426736000, 0.0548467000, 0.0809179000, 0.1413840000, 0.2938273000, 0.7125606000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0253712000, 0.0318265000, 0.0495284000, 0.0987892000, 0.2320792000, 0.5813369000, 1.5038908000", \ - "0.0253333000, 0.0318099000, 0.0494236000, 0.0985262000, 0.2319285000, 0.5827653000, 1.5001735000", \ - "0.0253480000, 0.0318195000, 0.0495197000, 0.0988183000, 0.2319878000, 0.5824021000, 1.5031864000", \ - "0.0253375000, 0.0318528000, 0.0493977000, 0.0985307000, 0.2317734000, 0.5829431000, 1.5015651000", \ - "0.0254580000, 0.0319421000, 0.0495053000, 0.0985859000, 0.2320237000, 0.5829351000, 1.5031458000", \ - "0.0273463000, 0.0335761000, 0.0506955000, 0.0993645000, 0.2322531000, 0.5819629000, 1.4997861000", \ - "0.0314232000, 0.0376026000, 0.0535999000, 0.1005991000, 0.2329673000, 0.5822949000, 1.4988324000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2318699000, 0.2411087000, 0.2596007000, 0.2944249000, 0.3597975000, 0.4952126000, 0.8222545000", \ - "0.2368397000, 0.2459850000, 0.2646116000, 0.2993324000, 0.3647264000, 0.5002577000, 0.8271557000", \ - "0.2494333000, 0.2585096000, 0.2771186000, 0.3120242000, 0.3768916000, 0.5123932000, 0.8394059000", \ - "0.2767899000, 0.2859180000, 0.3044322000, 0.3392502000, 0.4042224000, 0.5401011000, 0.8669946000", \ - "0.3349232000, 0.3440903000, 0.3626807000, 0.3974792000, 0.4628181000, 0.5983577000, 0.9254119000", \ - "0.4546880000, 0.4644343000, 0.4840332000, 0.5202884000, 0.5869050000, 0.7234172000, 1.0500106000", \ - "0.6602791000, 0.6719021000, 0.6947248000, 0.7360867000, 0.8096887000, 0.9523490000, 1.2812089000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0894407000, 0.0970296000, 0.1141758000, 0.1530111000, 0.2491049000, 0.4970268000, 1.1382656000", \ - "0.0939130000, 0.1015527000, 0.1186980000, 0.1576337000, 0.2534535000, 0.5011866000, 1.1452699000", \ - "0.1036054000, 0.1112655000, 0.1283620000, 0.1672448000, 0.2634559000, 0.5102844000, 1.1529608000", \ - "0.1250565000, 0.1326324000, 0.1496483000, 0.1885062000, 0.2846903000, 0.5309405000, 1.1732877000", \ - "0.1637262000, 0.1716212000, 0.1894920000, 0.2286027000, 0.3245336000, 0.5718117000, 1.2140422000", \ - "0.2169488000, 0.2262091000, 0.2451088000, 0.2860848000, 0.3822188000, 0.6290532000, 1.2736916000", \ - "0.2686828000, 0.2811014000, 0.3049505000, 0.3500218000, 0.4471916000, 0.6952365000, 1.3363813000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0370019000, 0.0430012000, 0.0550593000, 0.0820721000, 0.1409626000, 0.2940015000, 0.7163796000", \ - "0.0366486000, 0.0425583000, 0.0552413000, 0.0810705000, 0.1415336000, 0.2941488000, 0.7172560000", \ - "0.0367932000, 0.0424551000, 0.0548481000, 0.0810357000, 0.1414181000, 0.2948189000, 0.7198609000", \ - "0.0370733000, 0.0425131000, 0.0557252000, 0.0810404000, 0.1415376000, 0.2940989000, 0.7173148000", \ - "0.0370468000, 0.0423797000, 0.0549290000, 0.0811101000, 0.1410629000, 0.2944807000, 0.7200899000", \ - "0.0406031000, 0.0466569000, 0.0592906000, 0.0854544000, 0.1444048000, 0.2950776000, 0.7174431000", \ - "0.0517767000, 0.0593284000, 0.0722965000, 0.1001586000, 0.1592763000, 0.3054556000, 0.7180047000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0253084000, 0.0325474000, 0.0509144000, 0.0999790000, 0.2334476000, 0.5838420000, 1.5025600000", \ - "0.0252121000, 0.0325077000, 0.0508826000, 0.0999488000, 0.2325166000, 0.5852735000, 1.5023430000", \ - "0.0253328000, 0.0325059000, 0.0508450000, 0.0997585000, 0.2331724000, 0.5849901000, 1.5023430000", \ - "0.0254089000, 0.0326892000, 0.0509711000, 0.0999906000, 0.2329071000, 0.5828043000, 1.4995348000", \ - "0.0281151000, 0.0353552000, 0.0532292000, 0.1009716000, 0.2333388000, 0.5844243000, 1.5005605000", \ - "0.0345313000, 0.0414647000, 0.0589819000, 0.1042937000, 0.2344875000, 0.5837316000, 1.5024799000", \ - "0.0469630000, 0.0548797000, 0.0717698000, 0.1137000000, 0.2370396000, 0.5857319000, 1.4945221000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2044878000, 0.2132557000, 0.2311637000, 0.2650185000, 0.3287087000, 0.4628997000, 0.7889580000", \ - "0.2085858000, 0.2173643000, 0.2352937000, 0.2690417000, 0.3327542000, 0.4668431000, 0.7931614000", \ - "0.2198316000, 0.2286228000, 0.2464817000, 0.2799410000, 0.3440163000, 0.4782436000, 0.8040941000", \ - "0.2471256000, 0.2558645000, 0.2736096000, 0.3075537000, 0.3711866000, 0.5054512000, 0.8313601000", \ - "0.3084427000, 0.3171945000, 0.3350741000, 0.3688181000, 0.4328095000, 0.5669115000, 0.8924622000", \ - "0.4312423000, 0.4408357000, 0.4601823000, 0.4961686000, 0.5621565000, 0.6977112000, 1.0235859000", \ - "0.6392655000, 0.6506116000, 0.6735498000, 0.7156054000, 0.7897538000, 0.9322908000, 1.2602823000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0859182000, 0.0936095000, 0.1106881000, 0.1495485000, 0.2455346000, 0.4932789000, 1.1374760000", \ - "0.0900730000, 0.0977297000, 0.1148513000, 0.1538338000, 0.2499624000, 0.4966795000, 1.1392447000", \ - "0.1004354000, 0.1080983000, 0.1251870000, 0.1640099000, 0.2601431000, 0.5068650000, 1.1495784000", \ - "0.1243213000, 0.1319543000, 0.1489130000, 0.1875565000, 0.2836865000, 0.5306039000, 1.1733120000", \ - "0.1632301000, 0.1713778000, 0.1889132000, 0.2278487000, 0.3240275000, 0.5711047000, 1.2138874000", \ - "0.2094127000, 0.2187614000, 0.2381411000, 0.2784381000, 0.3741412000, 0.6215155000, 1.2644538000", \ - "0.2425730000, 0.2551543000, 0.2798963000, 0.3246346000, 0.4205405000, 0.6688813000, 1.3105732000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0339708000, 0.0397080000, 0.0520050000, 0.0781911000, 0.1384607000, 0.2913836000, 0.7199740000", \ - "0.0340027000, 0.0399501000, 0.0521961000, 0.0784995000, 0.1384151000, 0.2922049000, 0.7151422000", \ - "0.0338622000, 0.0396776000, 0.0527642000, 0.0790995000, 0.1382588000, 0.2914373000, 0.7154648000", \ - "0.0340047000, 0.0400705000, 0.0522556000, 0.0780633000, 0.1387211000, 0.2914588000, 0.7154364000", \ - "0.0338797000, 0.0401306000, 0.0522666000, 0.0782992000, 0.1381874000, 0.2905521000, 0.7168559000", \ - "0.0391597000, 0.0453314000, 0.0580056000, 0.0846315000, 0.1429608000, 0.2929124000, 0.7155672000", \ - "0.0519711000, 0.0592922000, 0.0726085000, 0.1005124000, 0.1599811000, 0.3050329000, 0.7170012000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0252306000, 0.0324007000, 0.0509261000, 0.1000474000, 0.2333478000, 0.5845096000, 1.4991101000", \ - "0.0252631000, 0.0325375000, 0.0508546000, 0.0999362000, 0.2327826000, 0.5849501000, 1.5023851000", \ - "0.0253275000, 0.0325009000, 0.0508461000, 0.0999252000, 0.2334628000, 0.5847363000, 1.5032746000", \ - "0.0255631000, 0.0327661000, 0.0510627000, 0.1000764000, 0.2334727000, 0.5848192000, 1.5033317000", \ - "0.0289360000, 0.0356552000, 0.0534972000, 0.1014760000, 0.2335946000, 0.5844086000, 1.5031365000", \ - "0.0375282000, 0.0436902000, 0.0598952000, 0.1049877000, 0.2343756000, 0.5828442000, 1.4974698000", \ - "0.0509012000, 0.0588033000, 0.0745606000, 0.1151538000, 0.2371915000, 0.5863766000, 1.4992546000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2o_2") { - leakage_power () { - value : 0.0035813000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0035813000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0021756000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0035813000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0069163000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0066415000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0037877000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0071549000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0059918000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0057170000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0028631000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0062304000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0055850000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0053102000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0024563000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0058236000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a2bb2o"; - cell_leakage_power : 0.0048373300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0016570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0100018000, 0.0099289000, 0.0097610000, 0.0097743000, 0.0098049000, 0.0098753000, 0.0100378000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032612000, 0.0031977000, 0.0030512000, 0.0031046000, 0.0032275000, 0.0035109000, 0.0041641000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017180000; - } - pin ("A2_N") { - capacitance : 0.0017070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087200000, 0.0086204000, 0.0083910000, 0.0084739000, 0.0086651000, 0.0091057000, 0.0101214000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022406000, 0.0021636000, 0.0019861000, 0.0020517000, 0.0022029000, 0.0025514000, 0.0033548000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018240000; - } - pin ("B1") { - capacitance : 0.0017260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016570000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028075000, 0.0028066000, 0.0028047000, 0.0028042000, 0.0028031000, 0.0028006000, 0.0027948000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002805700, -0.002804400, -0.002801400, -0.002802100, -0.002803500, -0.002807000, -0.002814800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017950000; - } - pin ("B2") { - capacitance : 0.0017960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030428000, 0.0030433000, 0.0030444000, 0.0030457000, 0.0030486000, 0.0030553000, 0.0030708000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003017300, -0.003023500, -0.003037800, -0.003039500, -0.003043600, -0.003052900, -0.003074400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018480000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (!A1_N&!A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0121579000, 0.0106000000, 0.0068112000, -0.004529000, -0.040341900, -0.149135500, -0.467765000", \ - "0.0121486000, 0.0105912000, 0.0068011000, -0.004499700, -0.040364100, -0.149143100, -0.467777000", \ - "0.0121246000, 0.0105752000, 0.0066530000, -0.004577400, -0.040391500, -0.149150300, -0.467779100", \ - "0.0118983000, 0.0103715000, 0.0064216000, -0.004851000, -0.040700200, -0.149492800, -0.468088700", \ - "0.0115207000, 0.0099661000, 0.0060067000, -0.005269800, -0.041034300, -0.149830700, -0.468417500", \ - "0.0137963000, 0.0121994000, 0.0076671000, -0.005226600, -0.041309500, -0.150093300, -0.468710700", \ - "0.0154628000, 0.0138466000, 0.0094294000, -0.003302000, -0.040572300, -0.149961300, -0.468747800"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0155037000, 0.0171774000, 0.0219624000, 0.0354258000, 0.0733462000, 0.1820108000, 0.4987290000", \ - "0.0154795000, 0.0171601000, 0.0219244000, 0.0353908000, 0.0733013000, 0.1822417000, 0.5008525000", \ - "0.0155319000, 0.0171884000, 0.0219905000, 0.0354188000, 0.0733550000, 0.1818593000, 0.4987085000", \ - "0.0154133000, 0.0171021000, 0.0218944000, 0.0352921000, 0.0732581000, 0.1821651000, 0.4960262000", \ - "0.0152377000, 0.0169030000, 0.0216920000, 0.0351010000, 0.0730760000, 0.1818785000, 0.4959684000", \ - "0.0147463000, 0.0164379000, 0.0213148000, 0.0349261000, 0.0726471000, 0.1812755000, 0.4977940000", \ - "0.0154647000, 0.0170618000, 0.0216546000, 0.0349388000, 0.0725378000, 0.1817168000, 0.4962545000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0121244000, 0.0106149000, 0.0067052000, -0.004604800, -0.040386900, -0.149120800, -0.467787500", \ - "0.0121253000, 0.0106092000, 0.0066973000, -0.004570600, -0.040377300, -0.149122000, -0.467819400", \ - "0.0120807000, 0.0105457000, 0.0066616000, -0.004518000, -0.040305400, -0.149141300, -0.467824100", \ - "0.0118205000, 0.0103120000, 0.0064901000, -0.004822500, -0.040704200, -0.149527400, -0.468180900", \ - "0.0114252000, 0.0099085000, 0.0060286000, -0.005292100, -0.041076100, -0.149899300, -0.468533500", \ - "0.0141626000, 0.0126021000, 0.0081310000, -0.004749400, -0.041230600, -0.150078300, -0.468739600", \ - "0.0156432000, 0.0140360000, 0.0095936000, -0.003133400, -0.040457900, -0.149792300, -0.468635200"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0152581000, 0.0169532000, 0.0217392000, 0.0351594000, 0.0731423000, 0.1818756000, 0.4961269000", \ - "0.0152068000, 0.0168604000, 0.0216666000, 0.0350823000, 0.0730642000, 0.1818183000, 0.4958365000", \ - "0.0152562000, 0.0169203000, 0.0217066000, 0.0351751000, 0.0730928000, 0.1816242000, 0.4984623000", \ - "0.0150694000, 0.0167491000, 0.0215304000, 0.0349608000, 0.0729299000, 0.1816783000, 0.4958720000", \ - "0.0147677000, 0.0164136000, 0.0212121000, 0.0346116000, 0.0725782000, 0.1812250000, 0.4954549000", \ - "0.0144480000, 0.0160164000, 0.0208367000, 0.0344995000, 0.0721758000, 0.1809696000, 0.4975955000", \ - "0.0149230000, 0.0165208000, 0.0210989000, 0.0343668000, 0.0719010000, 0.1815140000, 0.4953963000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0137254000, 0.0121566000, 0.0082263000, -0.002998100, -0.038809700, -0.147675300, -0.466403500", \ - "0.0136733000, 0.0121521000, 0.0081889000, -0.003113900, -0.038922600, -0.147702800, -0.466430700", \ - "0.0137041000, 0.0120422000, 0.0081434000, -0.003202600, -0.038953200, -0.147805200, -0.466525900", \ - "0.0135330000, 0.0119777000, 0.0081807000, -0.003144300, -0.039035600, -0.147905400, -0.466603800", \ - "0.0134044000, 0.0118441000, 0.0079382000, -0.003433700, -0.039279200, -0.148046800, -0.466733400", \ - "0.0133419000, 0.0117609000, 0.0078205000, -0.003387000, -0.039298900, -0.148140800, -0.466776800", \ - "0.0183138000, 0.0165527000, 0.0117641000, -0.001421300, -0.039072800, -0.148171800, -0.466746000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0163179000, 0.0179503000, 0.0227104000, 0.0361214000, 0.0741646000, 0.1833880000, 0.4991400000", \ - "0.0162353000, 0.0178791000, 0.0225936000, 0.0360481000, 0.0741048000, 0.1831292000, 0.4988918000", \ - "0.0161431000, 0.0177994000, 0.0225050000, 0.0359687000, 0.0740171000, 0.1830292000, 0.4987566000", \ - "0.0160398000, 0.0176886000, 0.0224361000, 0.0358534000, 0.0738978000, 0.1829420000, 0.4982658000", \ - "0.0159856000, 0.0176047000, 0.0222622000, 0.0355660000, 0.0735576000, 0.1828112000, 0.4985506000", \ - "0.0166339000, 0.0181781000, 0.0227186000, 0.0354247000, 0.0733387000, 0.1823369000, 0.5001822000", \ - "0.0174656000, 0.0189435000, 0.0233637000, 0.0365036000, 0.0737394000, 0.1828026000, 0.4968854000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0122042000, 0.0106760000, 0.0067857000, -0.004464100, -0.040330800, -0.149359400, -0.468147200", \ - "0.0120818000, 0.0105436000, 0.0066466000, -0.004504200, -0.040395600, -0.149394000, -0.468125100", \ - "0.0119659000, 0.0104623000, 0.0065640000, -0.004704300, -0.040548100, -0.149584100, -0.468352400", \ - "0.0117607000, 0.0102420000, 0.0063327000, -0.004847400, -0.040756900, -0.149750100, -0.468474600", \ - "0.0115935000, 0.0100512000, 0.0061131000, -0.005160300, -0.041052600, -0.149995200, -0.468702500", \ - "0.0113867000, 0.0097884000, 0.0058708000, -0.005378200, -0.041288900, -0.150100500, -0.468811000", \ - "0.0164155000, 0.0146213000, 0.0098352000, -0.003276600, -0.040779500, -0.149966000, -0.468645400"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0167063000, 0.0183619000, 0.0230991000, 0.0364541000, 0.0744694000, 0.1836211000, 0.5011907000", \ - "0.0166081000, 0.0182564000, 0.0230078000, 0.0363811000, 0.0744093000, 0.1835079000, 0.5010752000", \ - "0.0164929000, 0.0181298000, 0.0228077000, 0.0362610000, 0.0743114000, 0.1832932000, 0.4993447000", \ - "0.0163088000, 0.0179761000, 0.0227155000, 0.0361621000, 0.0740780000, 0.1831670000, 0.5009308000", \ - "0.0163506000, 0.0179499000, 0.0225969000, 0.0357313000, 0.0736522000, 0.1829991000, 0.5000468000", \ - "0.0172704000, 0.0187680000, 0.0232095000, 0.0361103000, 0.0736059000, 0.1824653000, 0.5005334000", \ - "0.0183632000, 0.0198182000, 0.0240805000, 0.0368804000, 0.0745668000, 0.1833999000, 0.4996248000"); - } - } - max_capacitance : 0.3003030000; - max_transition : 1.5036600000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.2333361000, 0.2404753000, 0.2562690000, 0.2873976000, 0.3467564000, 0.4723946000, 0.7913724000", \ - "0.2380189000, 0.2451499000, 0.2609164000, 0.2921121000, 0.3514678000, 0.4771117000, 0.7961138000", \ - "0.2485445000, 0.2556615000, 0.2714569000, 0.3023409000, 0.3620703000, 0.4876908000, 0.8066603000", \ - "0.2684023000, 0.2755195000, 0.2913360000, 0.3225879000, 0.3818929000, 0.5075971000, 0.8265810000", \ - "0.2960062000, 0.3031039000, 0.3188989000, 0.3502169000, 0.4098716000, 0.5354774000, 0.8544798000", \ - "0.3283034000, 0.3353891000, 0.3511211000, 0.3821975000, 0.4415973000, 0.5665545000, 0.8859496000", \ - "0.3477850000, 0.3549112000, 0.3706563000, 0.4017451000, 0.4614216000, 0.5870548000, 0.9055354000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.2036405000, 0.2094352000, 0.2229134000, 0.2542754000, 0.3363968000, 0.5693473000, 1.2485725000", \ - "0.2086331000, 0.2144504000, 0.2278770000, 0.2592417000, 0.3413011000, 0.5744664000, 1.2526472000", \ - "0.2209415000, 0.2267423000, 0.2402554000, 0.2715870000, 0.3536711000, 0.5868282000, 1.2653149000", \ - "0.2482698000, 0.2541068000, 0.2675566000, 0.2988952000, 0.3809325000, 0.6149924000, 1.2896122000", \ - "0.3075595000, 0.3134446000, 0.3269616000, 0.3583254000, 0.4403121000, 0.6743958000, 1.3482087000", \ - "0.4160029000, 0.4221620000, 0.4359258000, 0.4675505000, 0.5494549000, 0.7831673000, 1.4587428000", \ - "0.5969631000, 0.6036074000, 0.6181855000, 0.6504868000, 0.7328622000, 0.9661758000, 1.6412764000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0342219000, 0.0386102000, 0.0486791000, 0.0698547000, 0.1200818000, 0.2530827000, 0.6602083000", \ - "0.0342210000, 0.0386086000, 0.0486954000, 0.0698354000, 0.1200884000, 0.2530521000, 0.6603896000", \ - "0.0342847000, 0.0387419000, 0.0490145000, 0.0707715000, 0.1200156000, 0.2537095000, 0.6614240000", \ - "0.0341988000, 0.0386129000, 0.0485798000, 0.0701116000, 0.1196973000, 0.2530584000, 0.6609103000", \ - "0.0341462000, 0.0386149000, 0.0489408000, 0.0701916000, 0.1193875000, 0.2527288000, 0.6605571000", \ - "0.0342620000, 0.0385583000, 0.0482337000, 0.0701557000, 0.1194952000, 0.2526102000, 0.6630970000", \ - "0.0343185000, 0.0385917000, 0.0492214000, 0.0697573000, 0.1198398000, 0.2529646000, 0.6577147000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0222170000, 0.0265402000, 0.0387389000, 0.0751106000, 0.1876746000, 0.5224123000, 1.5017740000", \ - "0.0221870000, 0.0265369000, 0.0387984000, 0.0750634000, 0.1876177000, 0.5221643000, 1.5009993000", \ - "0.0221551000, 0.0265557000, 0.0388619000, 0.0751400000, 0.1875280000, 0.5220925000, 1.5015678000", \ - "0.0221829000, 0.0265279000, 0.0388223000, 0.0752361000, 0.1875852000, 0.5221225000, 1.4989002000", \ - "0.0224438000, 0.0267721000, 0.0389203000, 0.0752995000, 0.1878390000, 0.5228079000, 1.4994428000", \ - "0.0234815000, 0.0280103000, 0.0400031000, 0.0759572000, 0.1877686000, 0.5223137000, 1.5036603000", \ - "0.0264709000, 0.0308192000, 0.0424695000, 0.0773956000, 0.1885936000, 0.5207987000, 1.4944374000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.2270551000, 0.2341485000, 0.2498300000, 0.2808147000, 0.3402809000, 0.4651181000, 0.7840102000", \ - "0.2317313000, 0.2388214000, 0.2545200000, 0.2855255000, 0.3450282000, 0.4702756000, 0.7890615000", \ - "0.2419727000, 0.2490633000, 0.2647982000, 0.2956170000, 0.3548880000, 0.4802831000, 0.7990168000", \ - "0.2591662000, 0.2662609000, 0.2819311000, 0.3130401000, 0.3721147000, 0.4976941000, 0.8165537000", \ - "0.2815568000, 0.2886545000, 0.3044299000, 0.3354243000, 0.3947333000, 0.5202845000, 0.8391401000", \ - "0.3040980000, 0.3112479000, 0.3269560000, 0.3578420000, 0.4173092000, 0.5426413000, 0.8618168000", \ - "0.3120426000, 0.3191422000, 0.3348782000, 0.3659395000, 0.4255019000, 0.5510729000, 0.8698544000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1918730000, 0.1977517000, 0.2112456000, 0.2425821000, 0.3244890000, 0.5584774000, 1.2389804000", \ - "0.1948178000, 0.2006206000, 0.2141343000, 0.2454749000, 0.3274506000, 0.5614382000, 1.2354232000", \ - "0.2045056000, 0.2103178000, 0.2237925000, 0.2550997000, 0.3372511000, 0.5703054000, 1.2494414000", \ - "0.2324300000, 0.2382178000, 0.2517148000, 0.2830499000, 0.3649270000, 0.5989843000, 1.2766432000", \ - "0.2953031000, 0.3011530000, 0.3146992000, 0.3460609000, 0.4279271000, 0.6614538000, 1.3364657000", \ - "0.4025563000, 0.4087294000, 0.4224979000, 0.4541530000, 0.5360624000, 0.7696223000, 1.4501003000", \ - "0.5762877000, 0.5828467000, 0.5975698000, 0.6296937000, 0.7121014000, 0.9458232000, 1.6209770000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0341871000, 0.0384919000, 0.0481226000, 0.0700793000, 0.1193411000, 0.2529137000, 0.6614278000", \ - "0.0341725000, 0.0384897000, 0.0481264000, 0.0701203000, 0.1192666000, 0.2521639000, 0.6615468000", \ - "0.0340750000, 0.0384628000, 0.0484219000, 0.0699136000, 0.1186645000, 0.2526372000, 0.6600324000", \ - "0.0340537000, 0.0383492000, 0.0487768000, 0.0696164000, 0.1196253000, 0.2524216000, 0.6608740000", \ - "0.0341437000, 0.0384449000, 0.0482890000, 0.0693822000, 0.1192445000, 0.2528422000, 0.6613337000", \ - "0.0344322000, 0.0385113000, 0.0482047000, 0.0700816000, 0.1193095000, 0.2517044000, 0.6623495000", \ - "0.0343611000, 0.0388196000, 0.0483861000, 0.0696696000, 0.1196032000, 0.2531711000, 0.6599115000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0222828000, 0.0265851000, 0.0388276000, 0.0752154000, 0.1879566000, 0.5231471000, 1.4959513000", \ - "0.0221322000, 0.0265281000, 0.0388590000, 0.0752025000, 0.1878917000, 0.5231312000, 1.4955591000", \ - "0.0221488000, 0.0264765000, 0.0387726000, 0.0752381000, 0.1875593000, 0.5221785000, 1.5024025000", \ - "0.0221630000, 0.0265918000, 0.0387430000, 0.0752057000, 0.1879600000, 0.5229656000, 1.4943867000", \ - "0.0224495000, 0.0267376000, 0.0390297000, 0.0752961000, 0.1878422000, 0.5216823000, 1.4993314000", \ - "0.0235293000, 0.0280813000, 0.0400787000, 0.0760276000, 0.1877887000, 0.5221904000, 1.4989996000", \ - "0.0266223000, 0.0307930000, 0.0425233000, 0.0774455000, 0.1887116000, 0.5212307000, 1.4943897000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.2202854000, 0.2273959000, 0.2431715000, 0.2743440000, 0.3334978000, 0.4590864000, 0.7780099000", \ - "0.2257284000, 0.2328344000, 0.2485908000, 0.2797218000, 0.3394021000, 0.4644258000, 0.7835529000", \ - "0.2386501000, 0.2457236000, 0.2615380000, 0.2926198000, 0.3518819000, 0.4774623000, 0.7965772000", \ - "0.2655451000, 0.2725926000, 0.2883234000, 0.3196447000, 0.3787410000, 0.5045351000, 0.8234487000", \ - "0.3224900000, 0.3296074000, 0.3453639000, 0.3764636000, 0.4361604000, 0.5618966000, 0.8807642000", \ - "0.4391110000, 0.4466294000, 0.4639892000, 0.4964106000, 0.5576128000, 0.6842827000, 1.0035905000", \ - "0.6358984000, 0.6448500000, 0.6644935000, 0.7023949000, 0.7714149000, 0.9064718000, 1.2292931000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1160620000, 0.1227042000, 0.1381480000, 0.1724821000, 0.2568683000, 0.4911946000, 1.1672969000", \ - "0.1204676000, 0.1271291000, 0.1425240000, 0.1768679000, 0.2612528000, 0.4963537000, 1.1713641000", \ - "0.1300528000, 0.1366990000, 0.1520861000, 0.1864197000, 0.2708041000, 0.5059085000, 1.1809119000", \ - "0.1518892000, 0.1585081000, 0.1738699000, 0.2081846000, 0.2924463000, 0.5277402000, 1.2061069000", \ - "0.1969090000, 0.2038643000, 0.2197106000, 0.2543314000, 0.3387209000, 0.5735489000, 1.2502862000", \ - "0.2668436000, 0.2749433000, 0.2925367000, 0.3293518000, 0.4147653000, 0.6488878000, 1.3279704000", \ - "0.3511328000, 0.3614657000, 0.3836772000, 0.4265602000, 0.5148224000, 0.7489054000, 1.4252063000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0342319000, 0.0386458000, 0.0487594000, 0.0699630000, 0.1201871000, 0.2538250000, 0.6614547000", \ - "0.0343222000, 0.0386747000, 0.0484195000, 0.0704725000, 0.1197195000, 0.2532554000, 0.6615676000", \ - "0.0342387000, 0.0387911000, 0.0483525000, 0.0704081000, 0.1200242000, 0.2536466000, 0.6603864000", \ - "0.0341203000, 0.0386528000, 0.0489351000, 0.0699960000, 0.1199603000, 0.2530178000, 0.6607784000", \ - "0.0342015000, 0.0385665000, 0.0490998000, 0.0696164000, 0.1197796000, 0.2530039000, 0.6610270000", \ - "0.0390890000, 0.0433635000, 0.0530577000, 0.0753081000, 0.1233433000, 0.2545390000, 0.6606938000", \ - "0.0508793000, 0.0561354000, 0.0667248000, 0.0902580000, 0.1402955000, 0.2677294000, 0.6631682000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0252360000, 0.0302964000, 0.0439321000, 0.0807674000, 0.1911133000, 0.5250904000, 1.4981877000", \ - "0.0250584000, 0.0304046000, 0.0439637000, 0.0807956000, 0.1911939000, 0.5245461000, 1.4967001000", \ - "0.0250244000, 0.0304184000, 0.0439127000, 0.0807723000, 0.1912187000, 0.5246233000, 1.4974794000", \ - "0.0251069000, 0.0304094000, 0.0438821000, 0.0807420000, 0.1914519000, 0.5249633000, 1.4988636000", \ - "0.0268376000, 0.0321371000, 0.0456116000, 0.0817817000, 0.1912618000, 0.5255810000, 1.4996729000", \ - "0.0329370000, 0.0384491000, 0.0522138000, 0.0876930000, 0.1939869000, 0.5245412000, 1.5004085000", \ - "0.0457407000, 0.0518010000, 0.0663790000, 0.0996035000, 0.2002136000, 0.5261548000, 1.4969918000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1979912000, 0.2047320000, 0.2197889000, 0.2497463000, 0.3073789000, 0.4307045000, 0.7483207000", \ - "0.2031874000, 0.2098993000, 0.2249690000, 0.2549328000, 0.3124482000, 0.4358158000, 0.7540217000", \ - "0.2156390000, 0.2224091000, 0.2374436000, 0.2673937000, 0.3249951000, 0.4484126000, 0.7660524000", \ - "0.2432100000, 0.2498336000, 0.2648576000, 0.2949376000, 0.3523650000, 0.4757549000, 0.7938684000", \ - "0.3038857000, 0.3106099000, 0.3256495000, 0.3555436000, 0.4133409000, 0.5366929000, 0.8546585000", \ - "0.4275479000, 0.4349380000, 0.4512712000, 0.4832398000, 0.5436263000, 0.6682483000, 0.9867178000", \ - "0.6353051000, 0.6440576000, 0.6634400000, 0.7013256000, 0.7698848000, 0.9037445000, 1.2260013000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1126657000, 0.1193346000, 0.1346954000, 0.1689598000, 0.2532430000, 0.4887090000, 1.1659778000", \ - "0.1167306000, 0.1234093000, 0.1387259000, 0.1730617000, 0.2573082000, 0.4927606000, 1.1700948000", \ - "0.1266339000, 0.1332754000, 0.1485708000, 0.1829692000, 0.2672895000, 0.5024013000, 1.1779374000", \ - "0.1508689000, 0.1575556000, 0.1729152000, 0.2072069000, 0.2912586000, 0.5262462000, 1.2031497000", \ - "0.2008338000, 0.2078510000, 0.2236179000, 0.2582798000, 0.3423183000, 0.5766408000, 1.2528455000", \ - "0.2677747000, 0.2761225000, 0.2945888000, 0.3314835000, 0.4162156000, 0.6505826000, 1.3281850000", \ - "0.3366335000, 0.3476256000, 0.3714333000, 0.4156598000, 0.5046156000, 0.7377858000, 1.4142395000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0317001000, 0.0357534000, 0.0453764000, 0.0670755000, 0.1160455000, 0.2495614000, 0.6585191000", \ - "0.0314252000, 0.0357614000, 0.0456862000, 0.0664639000, 0.1165179000, 0.2497106000, 0.6589679000", \ - "0.0316960000, 0.0357542000, 0.0453510000, 0.0670903000, 0.1160038000, 0.2495389000, 0.6583524000", \ - "0.0314359000, 0.0357212000, 0.0456479000, 0.0664724000, 0.1160122000, 0.2498203000, 0.6581742000", \ - "0.0314492000, 0.0356959000, 0.0453831000, 0.0664596000, 0.1161052000, 0.2488455000, 0.6609162000", \ - "0.0369276000, 0.0415575000, 0.0512403000, 0.0731803000, 0.1204238000, 0.2514860000, 0.6615815000", \ - "0.0502440000, 0.0553949000, 0.0673522000, 0.0890577000, 0.1390638000, 0.2667558000, 0.6634506000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0250133000, 0.0303591000, 0.0439520000, 0.0807258000, 0.1914691000, 0.5244228000, 1.5010040000", \ - "0.0250826000, 0.0303590000, 0.0437880000, 0.0808464000, 0.1914558000, 0.5248889000, 1.5009874000", \ - "0.0251451000, 0.0304620000, 0.0440169000, 0.0807871000, 0.1909325000, 0.5239678000, 1.4985805000", \ - "0.0250073000, 0.0302945000, 0.0438276000, 0.0807921000, 0.1911890000, 0.5263879000, 1.5002312000", \ - "0.0276900000, 0.0329108000, 0.0460895000, 0.0823891000, 0.1914888000, 0.5258157000, 1.4947834000", \ - "0.0368678000, 0.0419274000, 0.0545937000, 0.0882377000, 0.1946121000, 0.5254830000, 1.4971381000", \ - "0.0506996000, 0.0578342000, 0.0717021000, 0.1041785000, 0.2008270000, 0.5272707000, 1.4953992000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2o_4") { - leakage_power () { - value : 0.0076036000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0076022000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0047386000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0076036000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0074979000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0068503000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0063325000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0078283000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0077883000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0071407000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0066229000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0081189000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0062568000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0056092000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0050914000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0065873000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__a2bb2o"; - cell_leakage_power : 0.0068295290; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0049000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0278574000, 0.0276228000, 0.0270821000, 0.0271445000, 0.0272884000, 0.0276201000, 0.0283845000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053596000, 0.0051463000, 0.0046544000, 0.0048403000, 0.0052688000, 0.0062565000, 0.0085333000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051410000; - } - pin ("A2_N") { - capacitance : 0.0044270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0230574000, 0.0227685000, 0.0221024000, 0.0223078000, 0.0227814000, 0.0238730000, 0.0263892000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020278000, 0.0018581000, 0.0014670000, 0.0016478000, 0.0020646000, 0.0030254000, 0.0052399000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047100000; - } - pin ("B1") { - capacitance : 0.0047680000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082890000, 0.0082899000, 0.0082921000, 0.0082953000, 0.0083028000, 0.0083200000, 0.0083597000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008313200, -0.008301800, -0.008275700, -0.008277400, -0.008281400, -0.008290600, -0.008311800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050020000; - } - pin ("B2") { - capacitance : 0.0043600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075709000, 0.0075693000, 0.0075654000, 0.0075631000, 0.0075579000, 0.0075459000, 0.0075181000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007572500, -0.007564000, -0.007544600, -0.007541500, -0.007534600, -0.007518600, -0.007481900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045390000; - } - pin ("X") { - direction : "output"; - function : "(B1&B2) | (!A1_N&!A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0323165000, 0.0305573000, 0.0254494000, 0.0107493000, -0.040389500, -0.213909800, -0.770061800", \ - "0.0321204000, 0.0306888000, 0.0254917000, 0.0108620000, -0.040288900, -0.214075000, -0.770238300", \ - "0.0322610000, 0.0305085000, 0.0254340000, 0.0107101000, -0.040388100, -0.213945000, -0.770213700", \ - "0.0314792000, 0.0298244000, 0.0246320000, 0.0099746000, -0.041052500, -0.214791600, -0.770956700", \ - "0.0309119000, 0.0292581000, 0.0241147000, 0.0093729000, -0.041694000, -0.215461100, -0.771551100", \ - "0.0366395000, 0.0349030000, 0.0295632000, 0.0127515000, -0.041983000, -0.215972800, -0.772086800", \ - "0.0378807000, 0.0361480000, 0.0309127000, 0.0139949000, -0.040290300, -0.215284500, -0.771912200"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0302697000, 0.0322524000, 0.0384436000, 0.0570356000, 0.1132173000, 0.2879976000, 0.8402169000", \ - "0.0300439000, 0.0320358000, 0.0382543000, 0.0568404000, 0.1129866000, 0.2876188000, 0.8357736000", \ - "0.0301627000, 0.0321360000, 0.0383539000, 0.0569477000, 0.1130572000, 0.2876874000, 0.8359631000", \ - "0.0297729000, 0.0317448000, 0.0379566000, 0.0565822000, 0.1126505000, 0.2872521000, 0.8357990000", \ - "0.0291298000, 0.0310985000, 0.0373014000, 0.0558740000, 0.1119945000, 0.2866992000, 0.8350848000", \ - "0.0281262000, 0.0299588000, 0.0356076000, 0.0549394000, 0.1109248000, 0.2856672000, 0.8340111000", \ - "0.0293831000, 0.0312189000, 0.0370126000, 0.0551023000, 0.1113418000, 0.2868924000, 0.8360326000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0329228000, 0.0311826000, 0.0260438000, 0.0114195000, -0.039646600, -0.213383200, -0.769864800", \ - "0.0330128000, 0.0313357000, 0.0262189000, 0.0115946000, -0.039561900, -0.213461800, -0.769781600", \ - "0.0328731000, 0.0310996000, 0.0261315000, 0.0113556000, -0.039655400, -0.213413100, -0.769925300", \ - "0.0320358000, 0.0302668000, 0.0251452000, 0.0105192000, -0.040631400, -0.214228000, -0.770647100", \ - "0.0311774000, 0.0295234000, 0.0243369000, 0.0097811000, -0.041346100, -0.215129400, -0.771397000", \ - "0.0370681000, 0.0353011000, 0.0299705000, 0.0130435000, -0.041493700, -0.215720300, -0.772033300", \ - "0.0383221000, 0.0366337000, 0.0314170000, 0.0144458000, -0.040084000, -0.214698200, -0.771550400"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0296997000, 0.0316812000, 0.0378923000, 0.0564860000, 0.1125915000, 0.2872007000, 0.8351577000", \ - "0.0294611000, 0.0314483000, 0.0376442000, 0.0562531000, 0.1124456000, 0.2870244000, 0.8391289000", \ - "0.0295965000, 0.0315860000, 0.0377944000, 0.0564027000, 0.1125696000, 0.2872508000, 0.8355389000", \ - "0.0290149000, 0.0309834000, 0.0371948000, 0.0557828000, 0.1119185000, 0.2865432000, 0.8346786000", \ - "0.0282360000, 0.0302220000, 0.0364318000, 0.0550049000, 0.1110828000, 0.2857607000, 0.8338320000", \ - "0.0276289000, 0.0294400000, 0.0351152000, 0.0542422000, 0.1103715000, 0.2848539000, 0.8342153000", \ - "0.0291957000, 0.0311059000, 0.0367890000, 0.0548255000, 0.1107809000, 0.2859858000, 0.8354000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0351194000, 0.0333439000, 0.0283012000, 0.0135748000, -0.037599700, -0.211312100, -0.767726900", \ - "0.0349394000, 0.0332931000, 0.0280223000, 0.0133685000, -0.037760800, -0.211604500, -0.768227100", \ - "0.0346374000, 0.0328901000, 0.0277233000, 0.0130711000, -0.038061400, -0.211902600, -0.768478300", \ - "0.0343079000, 0.0326521000, 0.0275306000, 0.0127341000, -0.038341200, -0.212226800, -0.768709600", \ - "0.0340671000, 0.0323479000, 0.0271497000, 0.0123674000, -0.038891900, -0.212764300, -0.769032500", \ - "0.0331015000, 0.0313257000, 0.0259739000, 0.0114010000, -0.039502000, -0.212877300, -0.769138100", \ - "0.0414386000, 0.0394852000, 0.0336185000, 0.0160219000, -0.038933000, -0.213276200, -0.768919800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0345718000, 0.0364822000, 0.0425960000, 0.0610973000, 0.1176301000, 0.2928181000, 0.8442256000", \ - "0.0342924000, 0.0362255000, 0.0422004000, 0.0608859000, 0.1174591000, 0.2927641000, 0.8435968000", \ - "0.0339279000, 0.0358574000, 0.0419247000, 0.0605120000, 0.1170625000, 0.2921882000, 0.8436940000", \ - "0.0336661000, 0.0355668000, 0.0414538000, 0.0599095000, 0.1164864000, 0.2917010000, 0.8431427000", \ - "0.0333716000, 0.0353475000, 0.0412681000, 0.0594459000, 0.1156060000, 0.2911183000, 0.8420561000", \ - "0.0344605000, 0.0362440000, 0.0419673000, 0.0594305000, 0.1150235000, 0.2896430000, 0.8421426000", \ - "0.0364945000, 0.0381598000, 0.0437974000, 0.0614359000, 0.1168876000, 0.2918859000, 0.8409365000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0298508000, 0.0282418000, 0.0231228000, 0.0085247000, -0.042607500, -0.216574600, -0.773317600", \ - "0.0294205000, 0.0279571000, 0.0227780000, 0.0083196000, -0.042854400, -0.216978200, -0.773584800", \ - "0.0291404000, 0.0275188000, 0.0224035000, 0.0078045000, -0.043328500, -0.217411500, -0.774013200", \ - "0.0286944000, 0.0270479000, 0.0219157000, 0.0072164000, -0.043925100, -0.217875100, -0.774458300", \ - "0.0284434000, 0.0267870000, 0.0216217000, 0.0067385000, -0.044476200, -0.218331200, -0.774921600", \ - "0.0286302000, 0.0267110000, 0.0214447000, 0.0057924000, -0.044888100, -0.218556100, -0.774927000", \ - "0.0358400000, 0.0338557000, 0.0280113000, 0.0104445000, -0.044370100, -0.218827300, -0.774650000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015825240, 0.0050087660, 0.0158529900, 0.0501754700, 0.1588078000, 0.5026343000"); - values("0.0339403000, 0.0358929000, 0.0419667000, 0.0604432000, 0.1170041000, 0.2919003000, 0.8439185000", \ - "0.0336213000, 0.0355477000, 0.0416143000, 0.0602418000, 0.1168625000, 0.2921273000, 0.8427336000", \ - "0.0333217000, 0.0352559000, 0.0413260000, 0.0599084000, 0.1164473000, 0.2916929000, 0.8433081000", \ - "0.0331914000, 0.0350902000, 0.0409995000, 0.0593003000, 0.1157805000, 0.2910394000, 0.8426510000", \ - "0.0330275000, 0.0348660000, 0.0408315000, 0.0586907000, 0.1150819000, 0.2905472000, 0.8413806000", \ - "0.0345343000, 0.0363097000, 0.0418899000, 0.0596473000, 0.1144322000, 0.2894923000, 0.8414125000", \ - "0.0370730000, 0.0387354000, 0.0442726000, 0.0615688000, 0.1172539000, 0.2918811000, 0.8409611000"); - } - } - max_capacitance : 0.5026340000; - max_transition : 1.5045660000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1812610000, 0.1852033000, 0.1952684000, 0.2175679000, 0.2638536000, 0.3705279000, 0.6698899000", \ - "0.1858589000, 0.1897823000, 0.1998833000, 0.2222378000, 0.2686923000, 0.3753406000, 0.6750271000", \ - "0.1962532000, 0.2001951000, 0.2102637000, 0.2325911000, 0.2788858000, 0.3855981000, 0.6848581000", \ - "0.2139762000, 0.2179139000, 0.2279842000, 0.2501680000, 0.2967764000, 0.4034162000, 0.7032850000", \ - "0.2347944000, 0.2386233000, 0.2485787000, 0.2708004000, 0.3172033000, 0.4242022000, 0.7234984000", \ - "0.2528099000, 0.2567236000, 0.2667510000, 0.2890031000, 0.3355522000, 0.4421618000, 0.7417389000", \ - "0.2441395000, 0.2480549000, 0.2581288000, 0.2803808000, 0.3269595000, 0.4338373000, 0.7336718000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1824226000, 0.1860255000, 0.1956822000, 0.2213225000, 0.2947436000, 0.5205480000, 1.2368203000", \ - "0.1867734000, 0.1903485000, 0.2000419000, 0.2256768000, 0.2991186000, 0.5247163000, 1.2371056000", \ - "0.1990939000, 0.2026934000, 0.2123735000, 0.2380258000, 0.3115148000, 0.5372138000, 1.2494737000", \ - "0.2264985000, 0.2300219000, 0.2397595000, 0.2653641000, 0.3388854000, 0.5646577000, 1.2771347000", \ - "0.2841544000, 0.2877657000, 0.2974600000, 0.3231024000, 0.3965533000, 0.6222400000, 1.3348850000", \ - "0.3865151000, 0.3901513000, 0.4000870000, 0.4259103000, 0.4993993000, 0.7254375000, 1.4385320000", \ - "0.5620023000, 0.5660107000, 0.5763886000, 0.6025792000, 0.6765027000, 0.9025882000, 1.6156780000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0272758000, 0.0296727000, 0.0360078000, 0.0508259000, 0.0910198000, 0.2086603000, 0.6017411000", \ - "0.0275356000, 0.0295664000, 0.0357445000, 0.0510662000, 0.0910329000, 0.2084289000, 0.6008078000", \ - "0.0272592000, 0.0296384000, 0.0358992000, 0.0509376000, 0.0910643000, 0.2086215000, 0.5988084000", \ - "0.0272169000, 0.0295094000, 0.0356818000, 0.0516760000, 0.0910885000, 0.2086468000, 0.6010752000", \ - "0.0271890000, 0.0295709000, 0.0360172000, 0.0508740000, 0.0911764000, 0.2086268000, 0.5982201000", \ - "0.0272823000, 0.0295988000, 0.0357263000, 0.0508421000, 0.0908837000, 0.2076126000, 0.6015757000", \ - "0.0274010000, 0.0296989000, 0.0363008000, 0.0513626000, 0.0910893000, 0.2087313000, 0.6007771000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0202336000, 0.0232279000, 0.0324526000, 0.0624682000, 0.1616113000, 0.4827844000, 1.5032696000", \ - "0.0202150000, 0.0231697000, 0.0324161000, 0.0624597000, 0.1617578000, 0.4827989000, 1.5000770000", \ - "0.0202620000, 0.0232406000, 0.0324581000, 0.0623352000, 0.1619234000, 0.4826979000, 1.5004742000", \ - "0.0202755000, 0.0232055000, 0.0324603000, 0.0623458000, 0.1620417000, 0.4825131000, 1.5020135000", \ - "0.0204634000, 0.0234344000, 0.0326253000, 0.0624816000, 0.1620069000, 0.4828038000, 1.5017680000", \ - "0.0215738000, 0.0244295000, 0.0335427000, 0.0630982000, 0.1619973000, 0.4824850000, 1.4991157000", \ - "0.0240575000, 0.0268462000, 0.0355111000, 0.0642467000, 0.1631057000, 0.4822050000, 1.4986121000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1822825000, 0.1862167000, 0.1962834000, 0.2185939000, 0.2652104000, 0.3717345000, 0.6713780000", \ - "0.1868372000, 0.1907816000, 0.2008805000, 0.2232203000, 0.2697154000, 0.3765788000, 0.6766055000", \ - "0.1964574000, 0.2003889000, 0.2104753000, 0.2327846000, 0.2792445000, 0.3859301000, 0.6856138000", \ - "0.2113896000, 0.2153215000, 0.2253858000, 0.2477037000, 0.2941588000, 0.4010264000, 0.7011700000", \ - "0.2279148000, 0.2317978000, 0.2418286000, 0.2641193000, 0.3105803000, 0.4174112000, 0.7172130000", \ - "0.2369783000, 0.2408986000, 0.2509851000, 0.2732104000, 0.3196493000, 0.4268016000, 0.7269091000", \ - "0.2160743000, 0.2200039000, 0.2300966000, 0.2524422000, 0.2987782000, 0.4059462000, 0.7062007000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1655555000, 0.1691459000, 0.1788201000, 0.2044676000, 0.2779781000, 0.5038446000, 1.2159201000", \ - "0.1684302000, 0.1719607000, 0.1816799000, 0.2072486000, 0.2805023000, 0.5072162000, 1.2218718000", \ - "0.1786103000, 0.1821955000, 0.1918917000, 0.2175345000, 0.2909892000, 0.5165509000, 1.2292439000", \ - "0.2075203000, 0.2111209000, 0.2207970000, 0.2464456000, 0.3199261000, 0.5455973000, 1.2581258000", \ - "0.2728460000, 0.2764479000, 0.2861684000, 0.3118189000, 0.3852970000, 0.6110517000, 1.3235582000", \ - "0.3851472000, 0.3888103000, 0.3986720000, 0.4244023000, 0.4980326000, 0.7241714000, 1.4364657000", \ - "0.5752232000, 0.5792071000, 0.5896179000, 0.6158729000, 0.6895162000, 0.9157875000, 1.6282844000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0272993000, 0.0296853000, 0.0358498000, 0.0509247000, 0.0904921000, 0.2088181000, 0.6016163000", \ - "0.0271602000, 0.0295058000, 0.0356824000, 0.0509440000, 0.0909749000, 0.2085710000, 0.6012919000", \ - "0.0272910000, 0.0296682000, 0.0359575000, 0.0510633000, 0.0909354000, 0.2088417000, 0.6013569000", \ - "0.0272873000, 0.0296464000, 0.0358130000, 0.0509477000, 0.0910013000, 0.2088441000, 0.6007365000", \ - "0.0273778000, 0.0296528000, 0.0356064000, 0.0512050000, 0.0911795000, 0.2087047000, 0.5999983000", \ - "0.0276008000, 0.0297946000, 0.0359221000, 0.0514218000, 0.0911216000, 0.2089825000, 0.6018152000", \ - "0.0277500000, 0.0301583000, 0.0360224000, 0.0514395000, 0.0912500000, 0.2091380000, 0.6015667000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0202436000, 0.0232260000, 0.0324498000, 0.0623287000, 0.1620334000, 0.4824611000, 1.4944298000", \ - "0.0201850000, 0.0231806000, 0.0324696000, 0.0622199000, 0.1619947000, 0.4824139000, 1.5022836000", \ - "0.0202346000, 0.0231790000, 0.0324096000, 0.0624588000, 0.1617336000, 0.4828315000, 1.5016131000", \ - "0.0202398000, 0.0232302000, 0.0324152000, 0.0624434000, 0.1618740000, 0.4827348000, 1.4998565000", \ - "0.0205044000, 0.0234190000, 0.0326399000, 0.0624228000, 0.1619002000, 0.4827233000, 1.4993775000", \ - "0.0216136000, 0.0245511000, 0.0335465000, 0.0629855000, 0.1626201000, 0.4812334000, 1.5018957000", \ - "0.0245481000, 0.0274302000, 0.0359098000, 0.0643876000, 0.1628658000, 0.4824696000, 1.4966000000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1832677000, 0.1871899000, 0.1972930000, 0.2195867000, 0.2657564000, 0.3723799000, 0.6715818000", \ - "0.1884592000, 0.1923844000, 0.2024134000, 0.2247268000, 0.2713312000, 0.3777033000, 0.6768715000", \ - "0.2012875000, 0.2051929000, 0.2152417000, 0.2375440000, 0.2841492000, 0.3905490000, 0.6896697000", \ - "0.2294062000, 0.2333433000, 0.2433886000, 0.2654468000, 0.3119119000, 0.4186300000, 0.7179067000", \ - "0.2899330000, 0.2938747000, 0.3039225000, 0.3262085000, 0.3727103000, 0.4795057000, 0.7791087000", \ - "0.4078901000, 0.4121949000, 0.4233002000, 0.4475785000, 0.4968193000, 0.6057806000, 0.9058223000", \ - "0.6075947000, 0.6129514000, 0.6263973000, 0.6557050000, 0.7122333000, 0.8294899000, 1.1332602000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0874570000, 0.0912668000, 0.1016947000, 0.1285348000, 0.2031202000, 0.4307015000, 1.1446318000", \ - "0.0916983000, 0.0955198000, 0.1058678000, 0.1328092000, 0.2074045000, 0.4346563000, 1.1491892000", \ - "0.1008996000, 0.1047587000, 0.1151176000, 0.1420274000, 0.2166610000, 0.4441100000, 1.1582209000", \ - "0.1216649000, 0.1254562000, 0.1357051000, 0.1624611000, 0.2368858000, 0.4644932000, 1.1809712000", \ - "0.1575424000, 0.1615903000, 0.1723703000, 0.1998444000, 0.2744607000, 0.5027982000, 1.2157336000", \ - "0.2028766000, 0.2076627000, 0.2199482000, 0.2488787000, 0.3240270000, 0.5515226000, 1.2681981000", \ - "0.2372363000, 0.2435110000, 0.2592370000, 0.2933702000, 0.3713470000, 0.5992233000, 1.3124750000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0272731000, 0.0296895000, 0.0357828000, 0.0507589000, 0.0911377000, 0.2086786000, 0.6013721000", \ - "0.0272286000, 0.0295815000, 0.0358464000, 0.0510711000, 0.0905280000, 0.2086257000, 0.6005728000", \ - "0.0273304000, 0.0297067000, 0.0358527000, 0.0510310000, 0.0904901000, 0.2086234000, 0.6006809000", \ - "0.0272012000, 0.0295235000, 0.0356983000, 0.0513976000, 0.0911446000, 0.2087204000, 0.5988943000", \ - "0.0275334000, 0.0296876000, 0.0357807000, 0.0510464000, 0.0906990000, 0.2086315000, 0.6002530000", \ - "0.0327861000, 0.0355581000, 0.0415285000, 0.0574785000, 0.0961118000, 0.2120244000, 0.6009643000", \ - "0.0447861000, 0.0476984000, 0.0550899000, 0.0715436000, 0.1110040000, 0.2233819000, 0.6017117000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0209540000, 0.0242483000, 0.0341076000, 0.0646292000, 0.1639472000, 0.4862745000, 1.5041085000", \ - "0.0208504000, 0.0242109000, 0.0341468000, 0.0645977000, 0.1639251000, 0.4859760000, 1.5042531000", \ - "0.0210096000, 0.0242758000, 0.0341581000, 0.0645560000, 0.1639896000, 0.4858194000, 1.5044034000", \ - "0.0210204000, 0.0243200000, 0.0343614000, 0.0647621000, 0.1641279000, 0.4854330000, 1.5042104000", \ - "0.0235496000, 0.0268917000, 0.0366359000, 0.0662944000, 0.1642557000, 0.4859042000, 1.5018760000", \ - "0.0295181000, 0.0327747000, 0.0423258000, 0.0708572000, 0.1661045000, 0.4838154000, 1.5042033000", \ - "0.0406088000, 0.0446235000, 0.0547955000, 0.0819446000, 0.1702493000, 0.4874301000, 1.5001632000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.1702127000, 0.1741091000, 0.1840822000, 0.2065363000, 0.2533614000, 0.3612158000, 0.6607177000", \ - "0.1750437000, 0.1788742000, 0.1888635000, 0.2113796000, 0.2583751000, 0.3660531000, 0.6657034000", \ - "0.1872954000, 0.1911535000, 0.2010708000, 0.2235583000, 0.2705599000, 0.3781002000, 0.6779639000", \ - "0.2150837000, 0.2189451000, 0.2289053000, 0.2512846000, 0.2981699000, 0.4060560000, 0.7057155000", \ - "0.2755499000, 0.2793739000, 0.2893368000, 0.3116957000, 0.3586855000, 0.4665607000, 0.7663435000", \ - "0.3909991000, 0.3953231000, 0.4063924000, 0.4309555000, 0.4812717000, 0.5917445000, 0.8927923000", \ - "0.5894414000, 0.5946347000, 0.6080097000, 0.6374939000, 0.6955500000, 0.8153180000, 1.1193858000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0822472000, 0.0860652000, 0.0964554000, 0.1233319000, 0.1979896000, 0.4249381000, 1.1394222000", \ - "0.0862175000, 0.0900196000, 0.1003956000, 0.1272997000, 0.2018228000, 0.4300120000, 1.1425511000", \ - "0.0962197000, 0.1000743000, 0.1104338000, 0.1373281000, 0.2119496000, 0.4394332000, 1.1537176000", \ - "0.1195205000, 0.1232833000, 0.1335707000, 0.1601844000, 0.2346224000, 0.4620599000, 1.1789925000", \ - "0.1555624000, 0.1595543000, 0.1703106000, 0.1974903000, 0.2719112000, 0.5006506000, 1.2134276000", \ - "0.1960956000, 0.2009849000, 0.2131793000, 0.2417964000, 0.3161753000, 0.5438435000, 1.2580605000", \ - "0.2173330000, 0.2237495000, 0.2398292000, 0.2739040000, 0.3508231000, 0.5774936000, 1.2917118000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0266137000, 0.0289259000, 0.0352627000, 0.0514061000, 0.0918973000, 0.2096584000, 0.6014580000", \ - "0.0264699000, 0.0288846000, 0.0352264000, 0.0511827000, 0.0920069000, 0.2097849000, 0.5986128000", \ - "0.0267024000, 0.0288242000, 0.0354694000, 0.0511405000, 0.0920107000, 0.2100717000, 0.5999802000", \ - "0.0266235000, 0.0289143000, 0.0353763000, 0.0511613000, 0.0920282000, 0.2101115000, 0.6011577000", \ - "0.0267299000, 0.0291147000, 0.0355821000, 0.0510656000, 0.0919617000, 0.2099276000, 0.6002916000", \ - "0.0324466000, 0.0349604000, 0.0422635000, 0.0583436000, 0.0976720000, 0.2138224000, 0.6013415000", \ - "0.0449421000, 0.0478249000, 0.0556585000, 0.0728937000, 0.1143831000, 0.2270420000, 0.6038857000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015825200, 0.0050087700, 0.0158530000, 0.0501755000, 0.1588080000, 0.5026340000"); - values("0.0208685000, 0.0242575000, 0.0341108000, 0.0645947000, 0.1641248000, 0.4846235000, 1.5045658000", \ - "0.0209097000, 0.0243180000, 0.0341864000, 0.0646124000, 0.1640981000, 0.4856112000, 1.5013609000", \ - "0.0209883000, 0.0242255000, 0.0341365000, 0.0645834000, 0.1638339000, 0.4858472000, 1.5044791000", \ - "0.0210857000, 0.0243931000, 0.0344188000, 0.0647935000, 0.1638821000, 0.4852158000, 1.5023398000", \ - "0.0239007000, 0.0271725000, 0.0367082000, 0.0666904000, 0.1645811000, 0.4855289000, 1.5005689000", \ - "0.0311271000, 0.0342270000, 0.0432145000, 0.0709573000, 0.1664819000, 0.4845334000, 1.5018551000", \ - "0.0435989000, 0.0474942000, 0.0573894000, 0.0833269000, 0.1704882000, 0.4876212000, 1.5008146000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2oi_1") { - leakage_power () { - value : 0.0029310000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0029310000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0010888000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0029310000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0050337000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0047996000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0069166000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0052427000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0035501000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0033160000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0054330000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0037590000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0010844000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0008503000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0029673000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0012933000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a2bb2oi"; - cell_leakage_power : 0.0033829740; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0023790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0146984000, 0.0145980000, 0.0143666000, 0.0144200000, 0.0145433000, 0.0148275000, 0.0154824000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046331000, 0.0045317000, 0.0042980000, 0.0044193000, 0.0046990000, 0.0053437000, 0.0068298000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024790000; - } - pin ("A2_N") { - capacitance : 0.0024790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0124968000, 0.0123542000, 0.0120255000, 0.0122062000, 0.0126229000, 0.0135833000, 0.0157972000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031957000, 0.0030706000, 0.0027822000, 0.0029253000, 0.0032551000, 0.0040153000, 0.0057676000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026470000; - } - pin ("B1") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040144000, 0.0040148000, 0.0040158000, 0.0040157000, 0.0040156000, 0.0040152000, 0.0040144000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004008700, -0.004007300, -0.004004200, -0.004002400, -0.003998500, -0.003989300, -0.003968200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024570000; - } - pin ("B2") { - capacitance : 0.0024190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042190000, 0.0042181000, 0.0042160000, 0.0042176000, 0.0042212000, 0.0042296000, 0.0042490000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004217000, -0.004218200, -0.004220900, -0.004219900, -0.004217500, -0.004212100, -0.004199600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024950000; - } - pin ("Y") { - direction : "output"; - function : "(A1_N&!B1) | (A1_N&!B2) | (A2_N&!B1) | (A2_N&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0018964000, 0.0011502000, -0.000670800, -0.005417300, -0.017123600, -0.044671700, -0.107818300", \ - "0.0018247000, 0.0010714000, -0.000785400, -0.005488200, -0.017184600, -0.044742800, -0.107883500", \ - "0.0018899000, 0.0011747000, -0.000698500, -0.005418100, -0.017123700, -0.044665800, -0.107813100", \ - "0.0016491000, 0.0008989000, -0.000940400, -0.005654400, -0.017335000, -0.044873000, -0.107992700", \ - "0.0012579000, 0.0005034000, -0.001347200, -0.005999800, -0.017607200, -0.045107600, -0.108219100", \ - "0.0018230000, 0.0008710000, -0.001320200, -0.006444200, -0.018342300, -0.045431200, -0.108463800", \ - "0.0026110000, 0.0015763000, -0.000836600, -0.006022400, -0.017929400, -0.045374800, -0.108111500"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0082519000, 0.0093643000, 0.0118352000, 0.0173750000, 0.0296264000, 0.0572174000, 0.1196506000", \ - "0.0082156000, 0.0093192000, 0.0118080000, 0.0173173000, 0.0295734000, 0.0571631000, 0.1196342000", \ - "0.0081986000, 0.0092929000, 0.0117700000, 0.0172694000, 0.0295642000, 0.0571829000, 0.1196346000", \ - "0.0077484000, 0.0088339000, 0.0112826000, 0.0167785000, 0.0290932000, 0.0567642000, 0.1192405000", \ - "0.0073453000, 0.0084056000, 0.0108324000, 0.0162916000, 0.0286134000, 0.0562994000, 0.1188511000", \ - "0.0072555000, 0.0082779000, 0.0105747000, 0.0159340000, 0.0282481000, 0.0559009000, 0.1186105000", \ - "0.0076592000, 0.0087094000, 0.0109954000, 0.0163584000, 0.0284460000, 0.0563112000, 0.1186707000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0019406000, 0.0011793000, -0.000637400, -0.005362700, -0.017087500, -0.044642500, -0.107775200", \ - "0.0017939000, 0.0010444000, -0.000799000, -0.005519900, -0.017231600, -0.044776300, -0.107910500", \ - "0.0018996000, 0.0011567000, -0.000711800, -0.005417000, -0.017112900, -0.044662200, -0.107786200", \ - "0.0016257000, 0.0008522000, -0.001031200, -0.005741300, -0.017422100, -0.044946900, -0.108058600", \ - "0.0011466000, 0.0004006000, -0.001507200, -0.006253700, -0.017822800, -0.045280100, -0.108344900", \ - "0.0017617000, 0.0007745000, -0.001462000, -0.006583100, -0.018551300, -0.045570700, -0.108568500", \ - "0.0019016000, 0.0008655000, -0.001397500, -0.006498500, -0.018452700, -0.045959400, -0.108682500"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0082237000, 0.0093028000, 0.0117097000, 0.0170695000, 0.0291322000, 0.0565166000, 0.1187464000", \ - "0.0081762000, 0.0092576000, 0.0116792000, 0.0170615000, 0.0291491000, 0.0565742000, 0.1188703000", \ - "0.0081192000, 0.0091979000, 0.0116091000, 0.0170554000, 0.0292000000, 0.0566316000, 0.1189371000", \ - "0.0075725000, 0.0086518000, 0.0110576000, 0.0165015000, 0.0286972000, 0.0562249000, 0.1185832000", \ - "0.0071509000, 0.0082096000, 0.0105247000, 0.0159473000, 0.0281842000, 0.0558127000, 0.1182478000", \ - "0.0072104000, 0.0081828000, 0.0105078000, 0.0157794000, 0.0280375000, 0.0555824000, 0.1180561000", \ - "0.0081807000, 0.0092407000, 0.0115724000, 0.0168467000, 0.0288478000, 0.0564258000, 0.1187566000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0050310000, 0.0040205000, 0.0016963000, -0.003602100, -0.015723500, -0.043404600, -0.106526200", \ - "0.0049074000, 0.0038986000, 0.0015763000, -0.003708800, -0.015828100, -0.043512800, -0.106616000", \ - "0.0047437000, 0.0037403000, 0.0014352000, -0.003833000, -0.015915400, -0.043583900, -0.106727000", \ - "0.0045388000, 0.0035525000, 0.0012804000, -0.003957200, -0.016015900, -0.043654300, -0.106760700", \ - "0.0045587000, 0.0035496000, 0.0011772000, -0.004161000, -0.016164200, -0.043739100, -0.106804700", \ - "0.0047889000, 0.0037593000, 0.0013884000, -0.003970100, -0.016110700, -0.043826400, -0.106838200", \ - "0.0058687000, 0.0047861000, 0.0023328000, -0.003159100, -0.015542500, -0.043456400, -0.106755200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0105861000, 0.0116241000, 0.0139942000, 0.0193254000, 0.0314125000, 0.0588561000, 0.1211723000", \ - "0.0104498000, 0.0114957000, 0.0138915000, 0.0192322000, 0.0313580000, 0.0587666000, 0.1211422000", \ - "0.0102967000, 0.0113435000, 0.0137416000, 0.0191056000, 0.0312607000, 0.0587487000, 0.1211310000", \ - "0.0101914000, 0.0112351000, 0.0136057000, 0.0189652000, 0.0311141000, 0.0586201000, 0.1210423000", \ - "0.0100864000, 0.0111421000, 0.0135233000, 0.0188446000, 0.0309592000, 0.0584865000, 0.1209470000", \ - "0.0100715000, 0.0110838000, 0.0134491000, 0.0188164000, 0.0310041000, 0.0584547000, 0.1208429000", \ - "0.0103669000, 0.0113620000, 0.0136338000, 0.0188190000, 0.0311926000, 0.0587366000, 0.1212691000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0053302000, 0.0043296000, 0.0020141000, -0.003276200, -0.015410400, -0.043078600, -0.106175100", \ - "0.0051874000, 0.0041853000, 0.0018923000, -0.003384100, -0.015488700, -0.043159700, -0.106260300", \ - "0.0049754000, 0.0039804000, 0.0017295000, -0.003534200, -0.015596600, -0.043234600, -0.106353200", \ - "0.0047601000, 0.0037812000, 0.0014964000, -0.003681600, -0.015720800, -0.043326500, -0.106396900", \ - "0.0047653000, 0.0037535000, 0.0014174000, -0.003774600, -0.015835200, -0.043435500, -0.106485800", \ - "0.0052740000, 0.0042211000, 0.0019888000, -0.003594400, -0.015775100, -0.043337000, -0.106429700", \ - "0.0067479000, 0.0056461000, 0.0031485000, -0.002418600, -0.014754100, -0.042771900, -0.106264500"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0077037000, 0.0088233000, 0.0112464000, 0.0166433000, 0.0287616000, 0.0561955000, 0.1185592000", \ - "0.0074612000, 0.0085860000, 0.0110555000, 0.0165201000, 0.0286486000, 0.0563426000, 0.1194861000", \ - "0.0072499000, 0.0083443000, 0.0107927000, 0.0163175000, 0.0286717000, 0.0561881000, 0.1185319000", \ - "0.0071259000, 0.0081843000, 0.0105792000, 0.0160270000, 0.0282957000, 0.0560948000, 0.1188871000", \ - "0.0070086000, 0.0080659000, 0.0104231000, 0.0157933000, 0.0280544000, 0.0555553000, 0.1191338000", \ - "0.0070043000, 0.0080360000, 0.0103932000, 0.0157534000, 0.0279528000, 0.0556243000, 0.1186187000", \ - "0.0072724000, 0.0082325000, 0.0105391000, 0.0157089000, 0.0280824000, 0.0557731000, 0.1184099000"); - } - } - max_capacitance : 0.0695900000; - max_transition : 1.4942230000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.1111415000, 0.1154701000, 0.1239808000, 0.1396402000, 0.1686284000, 0.2249226000, 0.3451324000", \ - "0.1160721000, 0.1203943000, 0.1289170000, 0.1445338000, 0.1735560000, 0.2299009000, 0.3500404000", \ - "0.1276640000, 0.1322772000, 0.1406176000, 0.1564070000, 0.1854206000, 0.2417337000, 0.3619886000", \ - "0.1534033000, 0.1579232000, 0.1663883000, 0.1821544000, 0.2111611000, 0.2675672000, 0.3877624000", \ - "0.2047048000, 0.2091118000, 0.2183404000, 0.2352032000, 0.2647292000, 0.3215943000, 0.4418911000", \ - "0.2883558000, 0.2936834000, 0.3043273000, 0.3233985000, 0.3565780000, 0.4166767000, 0.5387409000", \ - "0.4251904000, 0.4319152000, 0.4450878000, 0.4684088000, 0.5073971000, 0.5734328000, 0.6985780000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.1016376000, 0.1120047000, 0.1350522000, 0.1861222000, 0.2997900000, 0.5548120000, 1.1326634000", \ - "0.1062037000, 0.1164503000, 0.1396069000, 0.1907536000, 0.3042517000, 0.5593641000, 1.1373328000", \ - "0.1168338000, 0.1271052000, 0.1500059000, 0.2011440000, 0.3147958000, 0.5701323000, 1.1513779000", \ - "0.1361542000, 0.1465308000, 0.1693554000, 0.2202490000, 0.3340147000, 0.5897888000, 1.1706044000", \ - "0.1630373000, 0.1731082000, 0.1957694000, 0.2465357000, 0.3601626000, 0.6161379000, 1.1963941000", \ - "0.1936568000, 0.2032661000, 0.2254902000, 0.2758373000, 0.3892014000, 0.6450622000, 1.2244337000", \ - "0.2130845000, 0.2230796000, 0.2448727000, 0.2946385000, 0.4073978000, 0.6629732000, 1.2425178000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0306494000, 0.0330352000, 0.0386226000, 0.0513320000, 0.0792586000, 0.1438345000, 0.2970293000", \ - "0.0306552000, 0.0330770000, 0.0387230000, 0.0514435000, 0.0793166000, 0.1445239000, 0.2967399000", \ - "0.0306678000, 0.0330376000, 0.0386865000, 0.0512946000, 0.0792382000, 0.1444969000, 0.2965254000", \ - "0.0307070000, 0.0330926000, 0.0387103000, 0.0512642000, 0.0792460000, 0.1437777000, 0.2968163000", \ - "0.0343313000, 0.0366182000, 0.0420472000, 0.0542194000, 0.0814072000, 0.1446251000, 0.2970571000", \ - "0.0431056000, 0.0453205000, 0.0506471000, 0.0628321000, 0.0895151000, 0.1515371000, 0.3005791000", \ - "0.0595475000, 0.0620383000, 0.0676939000, 0.0800907000, 0.1060652000, 0.1637922000, 0.3073391000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0688322000, 0.0820539000, 0.1120092000, 0.1800975000, 0.3340153000, 0.6835135000, 1.4740639000", \ - "0.0687159000, 0.0821103000, 0.1120553000, 0.1799139000, 0.3334102000, 0.6830734000, 1.4750529000", \ - "0.0687149000, 0.0821489000, 0.1119521000, 0.1796755000, 0.3341415000, 0.6814138000, 1.4787466000", \ - "0.0687407000, 0.0820674000, 0.1121385000, 0.1797452000, 0.3339982000, 0.6809829000, 1.4781276000", \ - "0.0689042000, 0.0823644000, 0.1126322000, 0.1801524000, 0.3337781000, 0.6813132000, 1.4779761000", \ - "0.0699207000, 0.0829870000, 0.1126566000, 0.1805940000, 0.3338096000, 0.6815518000, 1.4741851000", \ - "0.0760182000, 0.0879511000, 0.1156969000, 0.1815698000, 0.3350941000, 0.6845421000, 1.4752034000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0999285000, 0.1043033000, 0.1128539000, 0.1286150000, 0.1574329000, 0.2137291000, 0.3339391000", \ - "0.1029940000, 0.1071139000, 0.1156882000, 0.1315280000, 0.1603964000, 0.2167607000, 0.3369332000", \ - "0.1133437000, 0.1176779000, 0.1261948000, 0.1421743000, 0.1710271000, 0.2274626000, 0.3475977000", \ - "0.1410908000, 0.1454618000, 0.1539742000, 0.1696134000, 0.1986011000, 0.2551049000, 0.3752279000", \ - "0.1979656000, 0.2028347000, 0.2115981000, 0.2284041000, 0.2580026000, 0.3147635000, 0.4351368000", \ - "0.2880549000, 0.2937498000, 0.3048929000, 0.3236178000, 0.3558022000, 0.4144315000, 0.5374853000", \ - "0.4339974000, 0.4412159000, 0.4544426000, 0.4778520000, 0.5158117000, 0.5777655000, 0.7003452000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0953433000, 0.1054268000, 0.1280676000, 0.1780824000, 0.2901094000, 0.5436975000, 1.1213566000", \ - "0.0998315000, 0.1098324000, 0.1325104000, 0.1827216000, 0.2949305000, 0.5486510000, 1.1267438000", \ - "0.1092866000, 0.1194715000, 0.1421828000, 0.1926019000, 0.3053047000, 0.5600083000, 1.1386563000", \ - "0.1249494000, 0.1350644000, 0.1575674000, 0.2080773000, 0.3211766000, 0.5759228000, 1.1536343000", \ - "0.1439297000, 0.1540998000, 0.1760655000, 0.2266202000, 0.3397638000, 0.5951171000, 1.1733396000", \ - "0.1609914000, 0.1704264000, 0.1928278000, 0.2431791000, 0.3562508000, 0.6116045000, 1.1900723000", \ - "0.1590946000, 0.1690324000, 0.1910097000, 0.2402784000, 0.3522434000, 0.6070666000, 1.1860570000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0306454000, 0.0330416000, 0.0386479000, 0.0511677000, 0.0794170000, 0.1436869000, 0.2967407000", \ - "0.0306550000, 0.0330731000, 0.0386352000, 0.0513950000, 0.0793010000, 0.1438104000, 0.2968728000", \ - "0.0306437000, 0.0330984000, 0.0387113000, 0.0513740000, 0.0793010000, 0.1435971000, 0.2968578000", \ - "0.0308023000, 0.0332467000, 0.0388375000, 0.0514113000, 0.0792919000, 0.1436766000, 0.2971486000", \ - "0.0358535000, 0.0379898000, 0.0431177000, 0.0551208000, 0.0823819000, 0.1452377000, 0.2974561000", \ - "0.0482660000, 0.0500228000, 0.0541687000, 0.0644475000, 0.0897366000, 0.1519578000, 0.3014985000", \ - "0.0659634000, 0.0679877000, 0.0728235000, 0.0834127000, 0.1056278000, 0.1616299000, 0.3055877000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0685717000, 0.0819304000, 0.1118866000, 0.1794468000, 0.3332228000, 0.6819605000, 1.4774901000", \ - "0.0685912000, 0.0819583000, 0.1118802000, 0.1796764000, 0.3329860000, 0.6811079000, 1.4733732000", \ - "0.0686317000, 0.0818103000, 0.1117880000, 0.1796742000, 0.3334046000, 0.6822241000, 1.4791187000", \ - "0.0686667000, 0.0819620000, 0.1117985000, 0.1796654000, 0.3330540000, 0.6808758000, 1.4716729000", \ - "0.0689248000, 0.0822073000, 0.1123632000, 0.1801435000, 0.3331939000, 0.6816607000, 1.4764919000", \ - "0.0703493000, 0.0832404000, 0.1127630000, 0.1805700000, 0.3339300000, 0.6839764000, 1.4770157000", \ - "0.0789722000, 0.0904797000, 0.1174332000, 0.1826902000, 0.3348435000, 0.6828696000, 1.4734677000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0323587000, 0.0359830000, 0.0439006000, 0.0608027000, 0.0978872000, 0.1804666000, 0.3669202000", \ - "0.0366759000, 0.0403275000, 0.0481697000, 0.0651702000, 0.1023072000, 0.1848710000, 0.3715136000", \ - "0.0463640000, 0.0499753000, 0.0578086000, 0.0747904000, 0.1119719000, 0.1946566000, 0.3811514000", \ - "0.0636839000, 0.0683732000, 0.0778960000, 0.0965470000, 0.1343058000, 0.2171530000, 0.4037947000", \ - "0.0870286000, 0.0938935000, 0.1073255000, 0.1336986000, 0.1806066000, 0.2684128000, 0.4557904000", \ - "0.1091296000, 0.1196773000, 0.1412565000, 0.1819360000, 0.2524011000, 0.3691674000, 0.5748202000", \ - "0.1118479000, 0.1283173000, 0.1617749000, 0.2258197000, 0.3366134000, 0.5155092000, 0.7969144000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0938234000, 0.1037033000, 0.1258436000, 0.1754735000, 0.2875242000, 0.5415340000, 1.1193414000", \ - "0.0987514000, 0.1084996000, 0.1308193000, 0.1806902000, 0.2929786000, 0.5470041000, 1.1251405000", \ - "0.1110253000, 0.1209884000, 0.1432719000, 0.1933848000, 0.3058485000, 0.5602029000, 1.1380927000", \ - "0.1379304000, 0.1477145000, 0.1699277000, 0.2199616000, 0.3325332000, 0.5872003000, 1.1651373000", \ - "0.1887861000, 0.2005350000, 0.2253253000, 0.2765923000, 0.3891100000, 0.6439452000, 1.2223448000", \ - "0.2723480000, 0.2888294000, 0.3220043000, 0.3880531000, 0.5169808000, 0.7741751000, 1.3524510000", \ - "0.4030976000, 0.4278942000, 0.4794206000, 0.5762737000, 0.7511233000, 1.0627181000, 1.6524265000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0247276000, 0.0288683000, 0.0381614000, 0.0590299000, 0.1066106000, 0.2153406000, 0.4631432000", \ - "0.0245110000, 0.0287077000, 0.0380577000, 0.0589030000, 0.1067928000, 0.2159734000, 0.4629705000", \ - "0.0254277000, 0.0293169000, 0.0382519000, 0.0587957000, 0.1067564000, 0.2149431000, 0.4636845000", \ - "0.0339663000, 0.0376929000, 0.0455988000, 0.0633543000, 0.1078327000, 0.2151910000, 0.4627873000", \ - "0.0528753000, 0.0572508000, 0.0672129000, 0.0867048000, 0.1267405000, 0.2226218000, 0.4630098000", \ - "0.0879473000, 0.0947178000, 0.1086957000, 0.1347919000, 0.1842854000, 0.2761181000, 0.4864453000", \ - "0.1510213000, 0.1619192000, 0.1836350000, 0.2228106000, 0.2911469000, 0.4080418000, 0.6182835000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0687836000, 0.0820786000, 0.1119010000, 0.1796769000, 0.3337545000, 0.6831695000, 1.4778541000", \ - "0.0688410000, 0.0820631000, 0.1120764000, 0.1798769000, 0.3333348000, 0.6811366000, 1.4742713000", \ - "0.0687183000, 0.0820888000, 0.1118958000, 0.1796520000, 0.3328313000, 0.6806594000, 1.4728603000", \ - "0.0695549000, 0.0825259000, 0.1121272000, 0.1798236000, 0.3331738000, 0.6809518000, 1.4726683000", \ - "0.0846738000, 0.0968107000, 0.1234028000, 0.1857525000, 0.3331826000, 0.6824645000, 1.4755729000", \ - "0.1231942000, 0.1368632000, 0.1658532000, 0.2272887000, 0.3600115000, 0.6866172000, 1.4742810000", \ - "0.2048097000, 0.2217553000, 0.2578375000, 0.3295671000, 0.4745648000, 0.7696304000, 1.4942229000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0283184000, 0.0319725000, 0.0398706000, 0.0568721000, 0.0939537000, 0.1765426000, 0.3629918000", \ - "0.0323103000, 0.0359784000, 0.0439041000, 0.0608845000, 0.0980513000, 0.1805943000, 0.3671223000", \ - "0.0426013000, 0.0461389000, 0.0539549000, 0.0708034000, 0.1079536000, 0.1905752000, 0.3770573000", \ - "0.0595169000, 0.0642648000, 0.0744599000, 0.0946835000, 0.1317613000, 0.2135687000, 0.4001926000", \ - "0.0777684000, 0.0855482000, 0.1010788000, 0.1307744000, 0.1822397000, 0.2696027000, 0.4555943000", \ - "0.0897813000, 0.1016583000, 0.1254567000, 0.1701925000, 0.2492227000, 0.3752725000, 0.5814179000", \ - "0.0705264000, 0.0885825000, 0.1251494000, 0.1937130000, 0.3144163000, 0.5125567000, 0.8214047000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0735112000, 0.0831808000, 0.1048340000, 0.1522813000, 0.2584638000, 0.4992394000, 1.0464879000", \ - "0.0776720000, 0.0874686000, 0.1091983000, 0.1573968000, 0.2652508000, 0.5099017000, 1.0600451000", \ - "0.0900076000, 0.0995824000, 0.1211831000, 0.1694892000, 0.2788442000, 0.5207338000, 1.0650238000", \ - "0.1183675000, 0.1278749000, 0.1492284000, 0.1972357000, 0.3054511000, 0.5484059000, 1.1025418000", \ - "0.1691937000, 0.1816882000, 0.2073812000, 0.2582663000, 0.3656697000, 0.6070424000, 1.1603820000", \ - "0.2499783000, 0.2691764000, 0.3070897000, 0.3769383000, 0.5056666000, 0.7501447000, 1.3047959000", \ - "0.3758550000, 0.4066637000, 0.4675780000, 0.5770803000, 0.7599294000, 1.0727630000, 1.6316318000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0246436000, 0.0288180000, 0.0380258000, 0.0589978000, 0.1067886000, 0.2159201000, 0.4626711000", \ - "0.0241404000, 0.0283608000, 0.0377430000, 0.0587233000, 0.1066384000, 0.2151958000, 0.4626058000", \ - "0.0262993000, 0.0298258000, 0.0382794000, 0.0586302000, 0.1065487000, 0.2158029000, 0.4631605000", \ - "0.0381156000, 0.0425742000, 0.0511389000, 0.0668649000, 0.1088131000, 0.2157937000, 0.4627033000", \ - "0.0597607000, 0.0655998000, 0.0775686000, 0.1005394000, 0.1380304000, 0.2277402000, 0.4633434000", \ - "0.0983285000, 0.1076159000, 0.1253177000, 0.1572366000, 0.2141192000, 0.3082853000, 0.4995412000", \ - "0.1654841000, 0.1797563000, 0.2087731000, 0.2585471000, 0.3418052000, 0.4744314000, 0.6891110000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0499654000, 0.0621490000, 0.0903702000, 0.1541409000, 0.2987266000, 0.6280724000, 1.3755177000", \ - "0.0500102000, 0.0622872000, 0.0906204000, 0.1541740000, 0.2990276000, 0.6297939000, 1.3866492000", \ - "0.0500613000, 0.0622815000, 0.0905238000, 0.1547509000, 0.3014425000, 0.6294435000, 1.3756626000", \ - "0.0520485000, 0.0635672000, 0.0909603000, 0.1543413000, 0.2997904000, 0.6298896000, 1.3810024000", \ - "0.0700955000, 0.0814745000, 0.1053836000, 0.1617122000, 0.3004521000, 0.6285400000, 1.3856998000", \ - "0.1103609000, 0.1238420000, 0.1522454000, 0.2100191000, 0.3299566000, 0.6344144000, 1.3846777000", \ - "0.1948519000, 0.2117738000, 0.2475377000, 0.3185492000, 0.4540238000, 0.7262140000, 1.3997140000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2oi_2") { - leakage_power () { - value : 0.0051601000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0051574000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0022952000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0051601000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0053221000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0048742000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0063400000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0056486000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0042684000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0039038000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0052863000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0045950000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0021498000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0017055000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0031677000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0024764000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__a2bb2oi"; - cell_leakage_power : 0.0042194160; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0045730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0281200000, 0.0278816000, 0.0273322000, 0.0273962000, 0.0275438000, 0.0278839000, 0.0286679000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055130000, 0.0052957000, 0.0047947000, 0.0049771000, 0.0053975000, 0.0063666000, 0.0086004000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048570000; - } - pin ("A2_N") { - capacitance : 0.0044340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0231082000, 0.0228582000, 0.0222819000, 0.0225310000, 0.0231050000, 0.0244282000, 0.0274783000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011842000, 0.0010336000, 0.0006864000, 0.0008767000, 0.0013154000, 0.0023265000, 0.0046572000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047530000; - } - pin ("B1") { - capacitance : 0.0047990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083804000, 0.0083776000, 0.0083713000, 0.0083687000, 0.0083628000, 0.0083491000, 0.0083176000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008356400, -0.008358400, -0.008363100, -0.008361700, -0.008358400, -0.008350900, -0.008333500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050270000; - } - pin ("B2") { - capacitance : 0.0043360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075667000, 0.0075594000, 0.0075425000, 0.0075461000, 0.0075544000, 0.0075737000, 0.0076180000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007557100, -0.007553900, -0.007546700, -0.007543900, -0.007537500, -0.007522600, -0.007488500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044960000; - } - pin ("Y") { - direction : "output"; - function : "(A1_N&!B1) | (A1_N&!B2) | (A2_N&!B1) | (A2_N&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0010386000, 0.0001982000, -0.002088000, -0.008474300, -0.026989500, -0.076635100, -0.203729300", \ - "0.0008628000, 3.150000e-05, -0.002246700, -0.008674300, -0.027151300, -0.076836100, -0.203882300", \ - "0.0010354000, 0.0001675000, -0.002099700, -0.008514500, -0.027014100, -0.076667900, -0.203732600", \ - "0.0006824000, -0.000184500, -0.002482800, -0.008993100, -0.027407400, -0.077040400, -0.204059700", \ - "6.140000e-05, -0.000836600, -0.003093600, -0.009585300, -0.027929800, -0.077466000, -0.204445300", \ - "0.0014397000, 0.0002606000, -0.002482700, -0.010087600, -0.029134700, -0.077912300, -0.204794500", \ - "0.0030120000, 0.0017844000, -0.001295600, -0.008965900, -0.028407400, -0.078171200, -0.204369100"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0176279000, 0.0188675000, 0.0220981000, 0.0301226000, 0.0499711000, 0.0998658000, 0.2255460000", \ - "0.0175258000, 0.0188272000, 0.0220492000, 0.0300527000, 0.0499859000, 0.0998399000, 0.2253960000", \ - "0.0176178000, 0.0188840000, 0.0221047000, 0.0301429000, 0.0500677000, 0.1000101000, 0.2256773000", \ - "0.0167652000, 0.0180555000, 0.0212706000, 0.0293135000, 0.0493206000, 0.0993125000, 0.2250298000", \ - "0.0158674000, 0.0171785000, 0.0203808000, 0.0284519000, 0.0485147000, 0.0985117000, 0.2242209000", \ - "0.0163111000, 0.0175319000, 0.0205173000, 0.0280909000, 0.0481243000, 0.0982510000, 0.2239913000", \ - "0.0171809000, 0.0185187000, 0.0215755000, 0.0293947000, 0.0492492000, 0.0990750000, 0.2246370000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0010637000, 0.0001914000, -0.002138500, -0.008532300, -0.027020100, -0.076678800, -0.203743900", \ - "0.0008763000, 1.260000e-05, -0.002287800, -0.008750300, -0.027237300, -0.076880400, -0.203927700", \ - "0.0010663000, 0.0002129000, -0.002095200, -0.008539500, -0.027033800, -0.076652300, -0.203711900", \ - "0.0007111000, -0.000186900, -0.002478000, -0.009001400, -0.027450600, -0.077119900, -0.204125100", \ - "-4.42000e-05, -0.000990100, -0.003368200, -0.009869200, -0.028179800, -0.077647200, -0.204585700", \ - "0.0021514000, 0.0009385000, -0.002097800, -0.009665000, -0.029222100, -0.077958600, -0.204725300", \ - "0.0029954000, 0.0017127000, -0.001387600, -0.009143600, -0.028487800, -0.078330100, -0.204507100"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0181572000, 0.0194724000, 0.0227529000, 0.0309115000, 0.0508580000, 0.1005831000, 0.2262537000", \ - "0.0181149000, 0.0194265000, 0.0227094000, 0.0308598000, 0.0508553000, 0.1006682000, 0.2263329000", \ - "0.0179773000, 0.0192805000, 0.0225395000, 0.0306833000, 0.0507469000, 0.1006957000, 0.2263885000", \ - "0.0171160000, 0.0184074000, 0.0216576000, 0.0297422000, 0.0498314000, 0.0999975000, 0.2256595000", \ - "0.0160975000, 0.0173666000, 0.0206082000, 0.0286820000, 0.0487804000, 0.0989298000, 0.2245252000", \ - "0.0163267000, 0.0174914000, 0.0206536000, 0.0282946000, 0.0483834000, 0.0984354000, 0.2244305000", \ - "0.0175694000, 0.0188384000, 0.0219553000, 0.0297611000, 0.0496660000, 0.0994190000, 0.2252305000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0094244000, 0.0081993000, 0.0051230000, -0.002667800, -0.022447300, -0.072604700, -0.199679100", \ - "0.0091650000, 0.0079421000, 0.0048675000, -0.002891700, -0.022632900, -0.072779500, -0.199818900", \ - "0.0087811000, 0.0075860000, 0.0045363000, -0.003177900, -0.022857700, -0.072973600, -0.200015800", \ - "0.0082822000, 0.0071087000, 0.0041346000, -0.003501600, -0.023090400, -0.073174500, -0.200134300", \ - "0.0083744000, 0.0071835000, 0.0041321000, -0.003836400, -0.023351500, -0.073223300, -0.200088300", \ - "0.0086910000, 0.0074693000, 0.0043708000, -0.003525600, -0.023397700, -0.073572000, -0.200368900", \ - "0.0106198000, 0.0093161000, 0.0061201000, -0.002012600, -0.022284700, -0.072899600, -0.200243000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0195753000, 0.0208003000, 0.0239697000, 0.0318886000, 0.0516419000, 0.1014736000, 0.2270582000", \ - "0.0192487000, 0.0204828000, 0.0236821000, 0.0316498000, 0.0515531000, 0.1013304000, 0.2268336000", \ - "0.0188807000, 0.0201436000, 0.0233209000, 0.0313475000, 0.0512985000, 0.1012094000, 0.2268310000", \ - "0.0186567000, 0.0199094000, 0.0230650000, 0.0310150000, 0.0509975000, 0.1010504000, 0.2267633000", \ - "0.0184455000, 0.0196848000, 0.0228678000, 0.0307744000, 0.0506236000, 0.1006349000, 0.2264933000", \ - "0.0184033000, 0.0196336000, 0.0227960000, 0.0307884000, 0.0507438000, 0.1007073000, 0.2264365000", \ - "0.0188075000, 0.0199965000, 0.0229692000, 0.0307026000, 0.0508235000, 0.1008626000, 0.2261879000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0087466000, 0.0075263000, 0.0044440000, -0.003340700, -0.023094800, -0.073261000, -0.200282700", \ - "0.0084968000, 0.0072655000, 0.0042053000, -0.003558800, -0.023258600, -0.073433900, -0.200530300", \ - "0.0081148000, 0.0069101000, 0.0038683000, -0.003817100, -0.023489000, -0.073584800, -0.200633500", \ - "0.0077078000, 0.0065121000, 0.0035421000, -0.004103800, -0.023749700, -0.073807500, -0.200779800", \ - "0.0078772000, 0.0066608000, 0.0036317000, -0.004146600, -0.023788500, -0.073818300, -0.200796700", \ - "0.0089471000, 0.0076186000, 0.0045053000, -0.003445300, -0.023583400, -0.073864400, -0.200878300", \ - "0.0116632000, 0.0102702000, 0.0070435000, -0.001331900, -0.021257400, -0.072149100, -0.200247200"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0139319000, 0.0153030000, 0.0186373000, 0.0267483000, 0.0465967000, 0.0963194000, 0.2220526000", \ - "0.0135270000, 0.0148553000, 0.0182268000, 0.0263247000, 0.0463524000, 0.0962985000, 0.2220002000", \ - "0.0132211000, 0.0144938000, 0.0177891000, 0.0258505000, 0.0463088000, 0.0969533000, 0.2237850000", \ - "0.0129921000, 0.0142903000, 0.0174600000, 0.0254922000, 0.0455164000, 0.0957432000, 0.2217618000", \ - "0.0127833000, 0.0140653000, 0.0172020000, 0.0251104000, 0.0450062000, 0.0956788000, 0.2212960000", \ - "0.0127433000, 0.0139830000, 0.0171373000, 0.0250692000, 0.0449506000, 0.0951392000, 0.2208176000", \ - "0.0131669000, 0.0143279000, 0.0172465000, 0.0249919000, 0.0450606000, 0.0952229000, 0.2213779000"); - } - } - max_capacitance : 0.1300150000; - max_transition : 1.4986590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.1274651000, 0.1308839000, 0.1380992000, 0.1527826000, 0.1810170000, 0.2372808000, 0.3632509000", \ - "0.1315319000, 0.1349165000, 0.1421343000, 0.1569570000, 0.1850194000, 0.2413424000, 0.3672850000", \ - "0.1434148000, 0.1468530000, 0.1540691000, 0.1687465000, 0.1969396000, 0.2532342000, 0.3791041000", \ - "0.1706035000, 0.1739601000, 0.1813075000, 0.1962825000, 0.2242068000, 0.2805451000, 0.4065068000", \ - "0.2256967000, 0.2292713000, 0.2369748000, 0.2522278000, 0.2809852000, 0.3377933000, 0.4639231000", \ - "0.3194289000, 0.3235878000, 0.3321698000, 0.3494479000, 0.3816577000, 0.4425769000, 0.5713382000", \ - "0.4745557000, 0.4795883000, 0.4904127000, 0.5122887000, 0.5506860000, 0.6186351000, 0.7523411000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0875078000, 0.0935383000, 0.1091636000, 0.1469264000, 0.2403064000, 0.4742157000, 1.0640064000", \ - "0.0920104000, 0.0981819000, 0.1136364000, 0.1514636000, 0.2449201000, 0.4788612000, 1.0698002000", \ - "0.1026087000, 0.1089319000, 0.1240890000, 0.1622022000, 0.2559141000, 0.4900321000, 1.0797324000", \ - "0.1209598000, 0.1270612000, 0.1423795000, 0.1804158000, 0.2742976000, 0.5088686000, 1.0987973000", \ - "0.1431668000, 0.1494027000, 0.1647591000, 0.2027597000, 0.2967627000, 0.5318109000, 1.1238850000", \ - "0.1645366000, 0.1704197000, 0.1850484000, 0.2226823000, 0.3166458000, 0.5516387000, 1.1433977000", \ - "0.1611566000, 0.1673864000, 0.1824984000, 0.2196728000, 0.3127466000, 0.5476356000, 1.1402089000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0304778000, 0.0319216000, 0.0358481000, 0.0461547000, 0.0706713000, 0.1308391000, 0.2867011000", \ - "0.0304808000, 0.0319871000, 0.0360299000, 0.0462051000, 0.0706683000, 0.1306749000, 0.2865565000", \ - "0.0305173000, 0.0319664000, 0.0358818000, 0.0461860000, 0.0707485000, 0.1308623000, 0.2874369000", \ - "0.0305168000, 0.0320288000, 0.0360255000, 0.0462548000, 0.0706454000, 0.1310431000, 0.2868559000", \ - "0.0333922000, 0.0347729000, 0.0386953000, 0.0483847000, 0.0721594000, 0.1316966000, 0.2871557000", \ - "0.0409777000, 0.0423718000, 0.0464194000, 0.0562884000, 0.0804003000, 0.1387961000, 0.2912372000", \ - "0.0567122000, 0.0581264000, 0.0620679000, 0.0725610000, 0.0966881000, 0.1526647000, 0.2987108000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0561927000, 0.0643135000, 0.0847500000, 0.1358406000, 0.2635503000, 0.5842112000, 1.3947655000", \ - "0.0561548000, 0.0643803000, 0.0848551000, 0.1357169000, 0.2632231000, 0.5856789000, 1.3983946000", \ - "0.0561015000, 0.0642802000, 0.0847984000, 0.1358495000, 0.2636147000, 0.5843453000, 1.3947724000", \ - "0.0560717000, 0.0642710000, 0.0847501000, 0.1358355000, 0.2641842000, 0.5843540000, 1.3944953000", \ - "0.0561490000, 0.0643689000, 0.0849917000, 0.1366298000, 0.2636909000, 0.5845839000, 1.3980284000", \ - "0.0570643000, 0.0650978000, 0.0852974000, 0.1362049000, 0.2649962000, 0.5848746000, 1.3954055000", \ - "0.0626091000, 0.0698673000, 0.0885696000, 0.1375507000, 0.2647884000, 0.5854971000, 1.3947795000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.1026576000, 0.1061915000, 0.1134007000, 0.1281864000, 0.1562845000, 0.2124615000, 0.3383851000", \ - "0.1055580000, 0.1090588000, 0.1163939000, 0.1311773000, 0.1591228000, 0.2154407000, 0.3413446000", \ - "0.1161078000, 0.1194579000, 0.1267696000, 0.1414361000, 0.1697623000, 0.2259761000, 0.3519403000", \ - "0.1436876000, 0.1470854000, 0.1543643000, 0.1689710000, 0.1971902000, 0.2537288000, 0.3796674000", \ - "0.2049148000, 0.2081325000, 0.2157676000, 0.2312320000, 0.2597050000, 0.3165363000, 0.4423688000", \ - "0.3025668000, 0.3070235000, 0.3161142000, 0.3338351000, 0.3649067000, 0.4241710000, 0.5535742000", \ - "0.4624311000, 0.4679512000, 0.4794227000, 0.5016607000, 0.5392291000, 0.6035351000, 0.7329644000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0836226000, 0.0899928000, 0.1058511000, 0.1442726000, 0.2385032000, 0.4732434000, 1.0631741000", \ - "0.0880833000, 0.0946457000, 0.1102196000, 0.1488915000, 0.2432227000, 0.4779303000, 1.0676504000", \ - "0.0978396000, 0.1040160000, 0.1198017000, 0.1582328000, 0.2529062000, 0.4879184000, 1.0784019000", \ - "0.1129816000, 0.1190515000, 0.1347131000, 0.1729850000, 0.2677458000, 0.5031032000, 1.0943694000", \ - "0.1303899000, 0.1364643000, 0.1519951000, 0.1905081000, 0.2849345000, 0.5206564000, 1.1131549000", \ - "0.1448312000, 0.1508420000, 0.1660230000, 0.2034591000, 0.2979055000, 0.5339665000, 1.1254545000", \ - "0.1344326000, 0.1404490000, 0.1561721000, 0.1932015000, 0.2871566000, 0.5219102000, 1.1146124000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0304824000, 0.0318885000, 0.0358508000, 0.0461195000, 0.0708384000, 0.1305416000, 0.2868852000", \ - "0.0304813000, 0.0318693000, 0.0358394000, 0.0462204000, 0.0707186000, 0.1308872000, 0.2873220000", \ - "0.0305236000, 0.0319928000, 0.0359514000, 0.0461133000, 0.0707494000, 0.1307139000, 0.2866570000", \ - "0.0304838000, 0.0319803000, 0.0360320000, 0.0462249000, 0.0708601000, 0.1305444000, 0.2869720000", \ - "0.0345982000, 0.0358795000, 0.0394435000, 0.0491423000, 0.0728786000, 0.1320698000, 0.2870688000", \ - "0.0467520000, 0.0477829000, 0.0507184000, 0.0585158000, 0.0802446000, 0.1381379000, 0.2920824000", \ - "0.0643296000, 0.0654453000, 0.0688068000, 0.0773772000, 0.0975066000, 0.1495084000, 0.2961158000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0558789000, 0.0641497000, 0.0845153000, 0.1356536000, 0.2631501000, 0.5847251000, 1.3972805000", \ - "0.0559205000, 0.0641580000, 0.0845718000, 0.1357743000, 0.2631686000, 0.5860288000, 1.3930610000", \ - "0.0559554000, 0.0640159000, 0.0844553000, 0.1355947000, 0.2630081000, 0.5840423000, 1.3938372000", \ - "0.0559003000, 0.0641122000, 0.0845950000, 0.1355318000, 0.2632560000, 0.5837116000, 1.3979776000", \ - "0.0560540000, 0.0642140000, 0.0847250000, 0.1362373000, 0.2633714000, 0.5855747000, 1.3980570000", \ - "0.0577357000, 0.0656215000, 0.0853769000, 0.1360264000, 0.2641949000, 0.5845415000, 1.3968461000", \ - "0.0663736000, 0.0738405000, 0.0914802000, 0.1388303000, 0.2647320000, 0.5855927000, 1.3948785000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0290002000, 0.0313374000, 0.0370161000, 0.0501052000, 0.0812390000, 0.1569506000, 0.3461020000", \ - "0.0332243000, 0.0355775000, 0.0412524000, 0.0543997000, 0.0855350000, 0.1613324000, 0.3501710000", \ - "0.0425779000, 0.0450276000, 0.0506340000, 0.0637785000, 0.0949295000, 0.1707376000, 0.3599862000", \ - "0.0579240000, 0.0610928000, 0.0683399000, 0.0838534000, 0.1164993000, 0.1926676000, 0.3820156000", \ - "0.0767297000, 0.0814832000, 0.0919802000, 0.1143950000, 0.1577578000, 0.2421165000, 0.4330492000", \ - "0.0899246000, 0.0972071000, 0.1138133000, 0.1487657000, 0.2149619000, 0.3323820000, 0.5471346000", \ - "0.0729800000, 0.0841963000, 0.1106062000, 0.1657020000, 0.2706209000, 0.4530139000, 0.7537834000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0883524000, 0.0943873000, 0.1097336000, 0.1471448000, 0.2406230000, 0.4746309000, 1.0645190000", \ - "0.0930442000, 0.0991354000, 0.1144433000, 0.1522668000, 0.2459722000, 0.4803693000, 1.0709524000", \ - "0.1055285000, 0.1119147000, 0.1269161000, 0.1650257000, 0.2590384000, 0.4937674000, 1.0853822000", \ - "0.1341143000, 0.1401276000, 0.1553408000, 0.1932455000, 0.2871927000, 0.5221532000, 1.1169381000", \ - "0.1884583000, 0.1957008000, 0.2137602000, 0.2541296000, 0.3479942000, 0.5829966000, 1.1739569000", \ - "0.2783125000, 0.2886215000, 0.3140925000, 0.3685697000, 0.4824638000, 0.7220883000, 1.3135160000", \ - "0.4202807000, 0.4374563000, 0.4767792000, 0.5604068000, 0.7220540000, 1.0259780000, 1.6352604000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0213501000, 0.0238187000, 0.0301067000, 0.0458242000, 0.0856613000, 0.1868498000, 0.4423514000", \ - "0.0210208000, 0.0235659000, 0.0298858000, 0.0456849000, 0.0855071000, 0.1865878000, 0.4420793000", \ - "0.0223605000, 0.0245737000, 0.0304533000, 0.0458070000, 0.0854167000, 0.1867423000, 0.4422657000", \ - "0.0306056000, 0.0329506000, 0.0387745000, 0.0525546000, 0.0880811000, 0.1869131000, 0.4423363000", \ - "0.0480955000, 0.0511271000, 0.0587971000, 0.0745672000, 0.1097096000, 0.1965609000, 0.4426652000", \ - "0.0807863000, 0.0854671000, 0.0961757000, 0.1184806000, 0.1637015000, 0.2533155000, 0.4674642000", \ - "0.1411385000, 0.1485272000, 0.1646038000, 0.1989980000, 0.2625027000, 0.3788876000, 0.6042171000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0563333000, 0.0644180000, 0.0848019000, 0.1355425000, 0.2634140000, 0.5854626000, 1.3938518000", \ - "0.0563598000, 0.0644294000, 0.0847381000, 0.1354777000, 0.2630660000, 0.5847837000, 1.3980755000", \ - "0.0562888000, 0.0644709000, 0.0847379000, 0.1356006000, 0.2631858000, 0.5834456000, 1.3959646000", \ - "0.0569937000, 0.0649194000, 0.0849577000, 0.1356919000, 0.2632552000, 0.5844415000, 1.3969548000", \ - "0.0719813000, 0.0796380000, 0.0977420000, 0.1433097000, 0.2644126000, 0.5839166000, 1.3942414000", \ - "0.1084626000, 0.1172810000, 0.1384618000, 0.1871280000, 0.2980795000, 0.5908539000, 1.3931211000", \ - "0.1866989000, 0.1988328000, 0.2266402000, 0.2852468000, 0.4114354000, 0.6812911000, 1.4143808000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0237196000, 0.0261151000, 0.0317251000, 0.0448548000, 0.0759670000, 0.1516969000, 0.3410260000", \ - "0.0278731000, 0.0301480000, 0.0357569000, 0.0489260000, 0.0799499000, 0.1557239000, 0.3447956000", \ - "0.0382336000, 0.0407000000, 0.0461805000, 0.0590163000, 0.0897807000, 0.1655686000, 0.3544597000", \ - "0.0526151000, 0.0561935000, 0.0641005000, 0.0811396000, 0.1131668000, 0.1891393000, 0.3781702000", \ - "0.0669837000, 0.0722498000, 0.0844078000, 0.1098884000, 0.1583089000, 0.2443052000, 0.4329081000", \ - "0.0720205000, 0.0800948000, 0.0984950000, 0.1365089000, 0.2115336000, 0.3409944000, 0.5599806000", \ - "0.0394002000, 0.0513500000, 0.0786998000, 0.1395171000, 0.2519927000, 0.4519289000, 0.7829078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0697545000, 0.0768295000, 0.0936231000, 0.1349939000, 0.2362099000, 0.4866581000, 1.1202800000", \ - "0.0738824000, 0.0808593000, 0.0978630000, 0.1392916000, 0.2403449000, 0.4922308000, 1.1263778000", \ - "0.0866415000, 0.0933357000, 0.1099491000, 0.1510514000, 0.2541316000, 0.5090297000, 1.1485790000", \ - "0.1149932000, 0.1217029000, 0.1384880000, 0.1789715000, 0.2798689000, 0.5335429000, 1.1687767000", \ - "0.1640680000, 0.1732069000, 0.1937555000, 0.2391813000, 0.3405581000, 0.5969246000, 1.2305342000", \ - "0.2430601000, 0.2568969000, 0.2883075000, 0.3503413000, 0.4750981000, 0.7333401000, 1.3699559000", \ - "0.3669230000, 0.3894114000, 0.4394981000, 0.5397097000, 0.7172815000, 1.0448723000, 1.6918675000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0213135000, 0.0237924000, 0.0299888000, 0.0458045000, 0.0856535000, 0.1863136000, 0.4425676000", \ - "0.0204366000, 0.0229774000, 0.0295652000, 0.0455935000, 0.0855104000, 0.1866587000, 0.4428738000", \ - "0.0236930000, 0.0256726000, 0.0310364000, 0.0457381000, 0.0852593000, 0.1866673000, 0.4418096000", \ - "0.0339260000, 0.0367330000, 0.0436860000, 0.0573847000, 0.0903443000, 0.1863679000, 0.4424625000", \ - "0.0536139000, 0.0577661000, 0.0669816000, 0.0867156000, 0.1232347000, 0.2036484000, 0.4426952000", \ - "0.0885696000, 0.0949101000, 0.1099381000, 0.1387682000, 0.1888634000, 0.2837979000, 0.4832760000", \ - "0.1483215000, 0.1593184000, 0.1834051000, 0.2270216000, 0.3080206000, 0.4441135000, 0.6733765000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0427360000, 0.0513872000, 0.0728407000, 0.1280627000, 0.2652538000, 0.6102490000, 1.4846393000", \ - "0.0428226000, 0.0513423000, 0.0730452000, 0.1276322000, 0.2647573000, 0.6107203000, 1.4788636000", \ - "0.0428307000, 0.0514366000, 0.0732058000, 0.1277531000, 0.2666955000, 0.6153504000, 1.4962768000", \ - "0.0451174000, 0.0531862000, 0.0738845000, 0.1278993000, 0.2644918000, 0.6089958000, 1.4807878000", \ - "0.0612315000, 0.0695127000, 0.0893563000, 0.1369408000, 0.2665485000, 0.6146830000, 1.4827640000", \ - "0.0980476000, 0.1071543000, 0.1298877000, 0.1813100000, 0.3004394000, 0.6179653000, 1.4854243000", \ - "0.1776112000, 0.1899178000, 0.2177000000, 0.2806297000, 0.4134899000, 0.7032890000, 1.4986594000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a2bb2oi_4") { - leakage_power () { - value : 0.0083212000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0083169000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0048861000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0083212000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0080573000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0108887000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0074817000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0088884000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0068163000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0116828000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0062407000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0076474000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0044426000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0073549000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0038670000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0052738000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__a2bb2oi"; - cell_leakage_power : 0.0074054400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0087620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0556216000, 0.0551134000, 0.0539421000, 0.0540220000, 0.0542062000, 0.0546308000, 0.0556096000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102057000, 0.0097930000, 0.0088418000, 0.0091615000, 0.0098984000, 0.0115970000, 0.0155127000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092290000; - } - pin ("A2_N") { - capacitance : 0.0087550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0456988000, 0.0451550000, 0.0439016000, 0.0442933000, 0.0451960000, 0.0472768000, 0.0520733000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025406000, 0.0022623000, 0.0016208000, 0.0019459000, 0.0026952000, 0.0044224000, 0.0084035000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0094240000; - } - pin ("B1") { - capacitance : 0.0091800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0087280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162435000, 0.0162423000, 0.0162396000, 0.0162417000, 0.0162466000, 0.0162579000, 0.0162838000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016243600, -0.016237200, -0.016222700, -0.016220000, -0.016213700, -0.016199500, -0.016166400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0096330000; - } - pin ("B2") { - capacitance : 0.0085110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150595000, 0.0150451000, 0.0150119000, 0.0150187000, 0.0150344000, 0.0150706000, 0.0151539000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015015300, -0.015015000, -0.015014300, -0.015018300, -0.015027700, -0.015049300, -0.015099000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088480000; - } - pin ("Y") { - direction : "output"; - function : "(A1_N&!B1) | (A1_N&!B2) | (A2_N&!B1) | (A2_N&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0042095000, 0.0032138000, 0.0003528000, -0.008360100, -0.035893700, -0.118840300, -0.352577300", \ - "0.0038274000, 0.0028333000, -7.10000e-05, -0.008767700, -0.036248700, -0.119195100, -0.352896400", \ - "0.0042324000, 0.0031486000, 0.0003082000, -0.008358200, -0.035944900, -0.118870800, -0.352550700", \ - "0.0035245000, 0.0023801000, -0.000453500, -0.009236300, -0.036691700, -0.119593400, -0.353146500", \ - "0.0025703000, 0.0015154000, -0.001572100, -0.010197300, -0.037648800, -0.120360700, -0.353886600", \ - "0.0033758000, 0.0020357000, -0.001726400, -0.012135400, -0.039514200, -0.121181300, -0.354359100", \ - "0.0069495000, 0.0055306000, 0.0016169000, -0.008855200, -0.038479900, -0.121654200, -0.353513600"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0334924000, 0.0350264000, 0.0389766000, 0.0500108000, 0.0802687000, 0.1635932000, 0.3949988000", \ - "0.0335161000, 0.0349175000, 0.0389533000, 0.0499614000, 0.0801835000, 0.1635314000, 0.3945959000", \ - "0.0338304000, 0.0354048000, 0.0393652000, 0.0504722000, 0.0807662000, 0.1641805000, 0.3952607000", \ - "0.0324591000, 0.0338924000, 0.0379431000, 0.0490892000, 0.0794901000, 0.1630454000, 0.3940847000", \ - "0.0310210000, 0.0324964000, 0.0365645000, 0.0477882000, 0.0783073000, 0.1620062000, 0.3934014000", \ - "0.0316158000, 0.0330356000, 0.0367255000, 0.0473150000, 0.0780184000, 0.1616054000, 0.3927758000", \ - "0.0331312000, 0.0344679000, 0.0383731000, 0.0490924000, 0.0797538000, 0.1625968000, 0.3935406000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0041475000, 0.0030910000, 0.0002624000, -0.008401600, -0.035941800, -0.118858800, -0.352531500", \ - "0.0037101000, 0.0027330000, -0.000153200, -0.008791100, -0.036290800, -0.119205100, -0.352848200", \ - "0.0042600000, 0.0032083000, 0.0002947000, -0.008316600, -0.035910800, -0.118768000, -0.352411000", \ - "0.0031676000, 0.0020434000, -0.000943900, -0.009578700, -0.037127400, -0.119869500, -0.353404800", \ - "0.0023466000, 0.0012556000, -0.001802700, -0.010638500, -0.038113800, -0.120580500, -0.353997500", \ - "0.0048764000, 0.0034060000, -0.000580600, -0.010818000, -0.039116600, -0.120470000, -0.353611300", \ - "0.0071417000, 0.0056644000, 0.0016576000, -0.009093000, -0.038468800, -0.121886700, -0.353522500"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0353345000, 0.0369507000, 0.0410513000, 0.0523849000, 0.0828736000, 0.1664484000, 0.3976297000", \ - "0.0352438000, 0.0368562000, 0.0410291000, 0.0524049000, 0.0829573000, 0.1666217000, 0.3978114000", \ - "0.0349204000, 0.0364354000, 0.0405986000, 0.0520067000, 0.0828839000, 0.1666353000, 0.3976491000", \ - "0.0331782000, 0.0346729000, 0.0387868000, 0.0501771000, 0.0811024000, 0.1651131000, 0.3964303000", \ - "0.0313580000, 0.0328417000, 0.0369804000, 0.0482078000, 0.0792116000, 0.1636365000, 0.3950165000", \ - "0.0314669000, 0.0329266000, 0.0369969000, 0.0478610000, 0.0783138000, 0.1624937000, 0.3946137000", \ - "0.0336754000, 0.0354174000, 0.0390921000, 0.0503073000, 0.0806163000, 0.1635643000, 0.3955040000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0188025000, 0.0173796000, 0.0134668000, 0.0025939000, -0.027609900, -0.111751800, -0.345486200", \ - "0.0182571000, 0.0168573000, 0.0129470000, 0.0021249000, -0.028011200, -0.112158300, -0.345777500", \ - "0.0175590000, 0.0161776000, 0.0123099000, 0.0015139000, -0.028498000, -0.112509200, -0.346171700", \ - "0.0166388000, 0.0152812000, 0.0114281000, 0.0008765000, -0.029033900, -0.112873000, -0.346419500", \ - "0.0164281000, 0.0150023000, 0.0110539000, 0.0002002000, -0.029596000, -0.113063700, -0.346514200", \ - "0.0173950000, 0.0159458000, 0.0119028000, 0.0009335000, -0.029243700, -0.113776900, -0.346834900", \ - "0.0204892000, 0.0190201000, 0.0149147000, 0.0035289000, -0.027429000, -0.112413000, -0.346700800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0389041000, 0.0403591000, 0.0444189000, 0.0553943000, 0.0857182000, 0.1693192000, 0.4005907000", \ - "0.0382415000, 0.0396794000, 0.0437150000, 0.0549191000, 0.0853324000, 0.1691159000, 0.4000705000", \ - "0.0374959000, 0.0389422000, 0.0430293000, 0.0542859000, 0.0848740000, 0.1686979000, 0.4002774000", \ - "0.0369872000, 0.0384263000, 0.0425134000, 0.0536420000, 0.0842719000, 0.1682973000, 0.3996023000", \ - "0.0365922000, 0.0380343000, 0.0420177000, 0.0530429000, 0.0835653000, 0.1674131000, 0.3992191000", \ - "0.0363929000, 0.0378403000, 0.0418723000, 0.0530163000, 0.0835863000, 0.1674232000, 0.3986968000", \ - "0.0367316000, 0.0381439000, 0.0419625000, 0.0526621000, 0.0836553000, 0.1677354000, 0.3994072000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0179066000, 0.0164941000, 0.0125875000, 0.0016944000, -0.028449400, -0.112538900, -0.346421500", \ - "0.0173742000, 0.0159766000, 0.0120969000, 0.0012751000, -0.028801200, -0.112963200, -0.346683000", \ - "0.0166598000, 0.0152741000, 0.0114746000, 0.0007173000, -0.029328600, -0.113226200, -0.347041400", \ - "0.0156538000, 0.0143115000, 0.0105567000, -5.90000e-06, -0.029833300, -0.113619400, -0.347189200", \ - "0.0159089000, 0.0145385000, 0.0107553000, -8.77000e-05, -0.029957700, -0.113621700, -0.347191900", \ - "0.0175552000, 0.0161034000, 0.0121141000, 0.0006538000, -0.029623400, -0.113753200, -0.347285100", \ - "0.0223660000, 0.0207969000, 0.0165358000, 0.0049942000, -0.025915400, -0.110834900, -0.346256800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013852860, 0.0038380370, 0.0106335600, 0.0294610500, 0.0816239800, 0.2261452000"); - values("0.0271960000, 0.0288229000, 0.0330934000, 0.0444360000, 0.0749256000, 0.1585417000, 0.3897718000", \ - "0.0263053000, 0.0279172000, 0.0322151000, 0.0438625000, 0.0745589000, 0.1584570000, 0.3898368000", \ - "0.0255591000, 0.0271530000, 0.0313318000, 0.0428018000, 0.0739841000, 0.1586611000, 0.3930156000", \ - "0.0251669000, 0.0266493000, 0.0306990000, 0.0420717000, 0.0728006000, 0.1575359000, 0.3892952000", \ - "0.0247442000, 0.0262193000, 0.0302501000, 0.0412850000, 0.0719877000, 0.1562817000, 0.3884458000", \ - "0.0246407000, 0.0260757000, 0.0300558000, 0.0412428000, 0.0719633000, 0.1560336000, 0.3875943000", \ - "0.0251487000, 0.0264818000, 0.0300989000, 0.0407907000, 0.0717313000, 0.1561475000, 0.3877962000"); - } - } - max_capacitance : 0.2261450000; - max_transition : 1.4947280000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.1354253000, 0.1378961000, 0.1438628000, 0.1572142000, 0.1846833000, 0.2430794000, 0.3822626000", \ - "0.1393996000, 0.1416599000, 0.1479257000, 0.1611871000, 0.1886811000, 0.2471217000, 0.3863370000", \ - "0.1514291000, 0.1539181000, 0.1596362000, 0.1730668000, 0.2006474000, 0.2590816000, 0.3983149000", \ - "0.1788453000, 0.1813406000, 0.1871256000, 0.2003458000, 0.2279930000, 0.2862846000, 0.4257093000", \ - "0.2349268000, 0.2373393000, 0.2435162000, 0.2571300000, 0.2852441000, 0.3440507000, 0.4834779000", \ - "0.3328479000, 0.3356704000, 0.3426917000, 0.3578970000, 0.3888999000, 0.4517941000, 0.5944993000", \ - "0.4994719000, 0.5029067000, 0.5112846000, 0.5302941000, 0.5670820000, 0.6374808000, 0.7851451000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0947069000, 0.0989362000, 0.1095689000, 0.1393114000, 0.2197788000, 0.4411359000, 1.0542964000", \ - "0.0993493000, 0.1032951000, 0.1144162000, 0.1441753000, 0.2245696000, 0.4459459000, 1.0598052000", \ - "0.1099726000, 0.1143020000, 0.1250314000, 0.1550168000, 0.2357708000, 0.4571896000, 1.0699384000", \ - "0.1293784000, 0.1333044000, 0.1444736000, 0.1742728000, 0.2553444000, 0.4769940000, 1.0899719000", \ - "0.1521973000, 0.1561657000, 0.1672431000, 0.1975182000, 0.2790005000, 0.5008583000, 1.1138149000", \ - "0.1730955000, 0.1770984000, 0.1879411000, 0.2174145000, 0.2988352000, 0.5213879000, 1.1343501000", \ - "0.1667251000, 0.1701478000, 0.1812752000, 0.2106847000, 0.2915621000, 0.5143921000, 1.1287483000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0341067000, 0.0351732000, 0.0381042000, 0.0466836000, 0.0701567000, 0.1328159000, 0.3111436000", \ - "0.0341671000, 0.0351510000, 0.0381613000, 0.0467479000, 0.0701247000, 0.1330306000, 0.3110475000", \ - "0.0341147000, 0.0351506000, 0.0381415000, 0.0466071000, 0.0701583000, 0.1330106000, 0.3110454000", \ - "0.0341435000, 0.0351754000, 0.0381169000, 0.0467746000, 0.0700864000, 0.1326463000, 0.3109394000", \ - "0.0365273000, 0.0374604000, 0.0402510000, 0.0485788000, 0.0713470000, 0.1334548000, 0.3109187000", \ - "0.0436890000, 0.0446433000, 0.0474539000, 0.0558847000, 0.0790901000, 0.1407304000, 0.3150951000", \ - "0.0593999000, 0.0602694000, 0.0630755000, 0.0715482000, 0.0943359000, 0.1533546000, 0.3224956000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0613919000, 0.0667214000, 0.0813321000, 0.1216061000, 0.2319784000, 0.5350451000, 1.3766649000", \ - "0.0614467000, 0.0666581000, 0.0813963000, 0.1214246000, 0.2315334000, 0.5356692000, 1.3796920000", \ - "0.0613849000, 0.0667104000, 0.0813282000, 0.1216071000, 0.2318740000, 0.5354455000, 1.3769286000", \ - "0.0614498000, 0.0666385000, 0.0813133000, 0.1214349000, 0.2316130000, 0.5367731000, 1.3794761000", \ - "0.0615396000, 0.0669005000, 0.0814815000, 0.1223547000, 0.2320890000, 0.5364329000, 1.3774069000", \ - "0.0623876000, 0.0676332000, 0.0820325000, 0.1220798000, 0.2326222000, 0.5358224000, 1.3792185000", \ - "0.0674961000, 0.0726155000, 0.0859048000, 0.1237570000, 0.2328732000, 0.5364806000, 1.3764330000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.1131290000, 0.1156881000, 0.1216988000, 0.1350429000, 0.1624224000, 0.2207372000, 0.3601275000", \ - "0.1157843000, 0.1181749000, 0.1241559000, 0.1375062000, 0.1651635000, 0.2236500000, 0.3628974000", \ - "0.1262453000, 0.1286670000, 0.1346483000, 0.1477774000, 0.1753955000, 0.2336683000, 0.3730196000", \ - "0.1541685000, 0.1565537000, 0.1625054000, 0.1756649000, 0.2034929000, 0.2617129000, 0.4010846000", \ - "0.2181547000, 0.2206477000, 0.2263781000, 0.2401365000, 0.2683724000, 0.3274165000, 0.4670324000", \ - "0.3234562000, 0.3265004000, 0.3338487000, 0.3494389000, 0.3802113000, 0.4420172000, 0.5854506000", \ - "0.4975127000, 0.5012540000, 0.5105069000, 0.5302769000, 0.5675434000, 0.6349522000, 0.7787422000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0919634000, 0.0962175000, 0.1076468000, 0.1382918000, 0.2199534000, 0.4421294000, 1.0557752000", \ - "0.0963274000, 0.1007890000, 0.1121730000, 0.1428790000, 0.2245953000, 0.4468880000, 1.0609152000", \ - "0.1058959000, 0.1100450000, 0.1217226000, 0.1525565000, 0.2346388000, 0.4575244000, 1.0712974000", \ - "0.1208086000, 0.1249363000, 0.1362545000, 0.1670394000, 0.2495069000, 0.4732882000, 1.0871862000", \ - "0.1373971000, 0.1414660000, 0.1528766000, 0.1831972000, 0.2661202000, 0.4901287000, 1.1045654000", \ - "0.1490993000, 0.1530869000, 0.1644893000, 0.1947166000, 0.2765827000, 0.5013285000, 1.1165103000", \ - "0.1317365000, 0.1363246000, 0.1475012000, 0.1774374000, 0.2580933000, 0.4816316000, 1.0974548000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0341349000, 0.0351650000, 0.0381009000, 0.0467041000, 0.0701748000, 0.1332363000, 0.3110052000", \ - "0.0341689000, 0.0351415000, 0.0381052000, 0.0467964000, 0.0700973000, 0.1330613000, 0.3110981000", \ - "0.0341625000, 0.0351374000, 0.0380619000, 0.0467039000, 0.0702608000, 0.1330032000, 0.3109573000", \ - "0.0342415000, 0.0352451000, 0.0381418000, 0.0467430000, 0.0701832000, 0.1330705000, 0.3111684000", \ - "0.0378875000, 0.0387503000, 0.0414806000, 0.0495486000, 0.0720735000, 0.1338805000, 0.3109662000", \ - "0.0502751000, 0.0508958000, 0.0529525000, 0.0599086000, 0.0799767000, 0.1405512000, 0.3162982000", \ - "0.0693419000, 0.0700433000, 0.0723043000, 0.0791631000, 0.0982680000, 0.1519491000, 0.3209057000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0612121000, 0.0665552000, 0.0810459000, 0.1211998000, 0.2315833000, 0.5356587000, 1.3789050000", \ - "0.0611916000, 0.0665441000, 0.0811913000, 0.1214014000, 0.2314234000, 0.5363079000, 1.3760312000", \ - "0.0610908000, 0.0664464000, 0.0810310000, 0.1212036000, 0.2313912000, 0.5363706000, 1.3751150000", \ - "0.0611997000, 0.0665609000, 0.0810538000, 0.1212632000, 0.2315082000, 0.5367613000, 1.3757562000", \ - "0.0614501000, 0.0667182000, 0.0813584000, 0.1219739000, 0.2318873000, 0.5357507000, 1.3749879000", \ - "0.0628413000, 0.0679845000, 0.0820518000, 0.1219996000, 0.2322420000, 0.5359075000, 1.3786227000", \ - "0.0708850000, 0.0751917000, 0.0881568000, 0.1250186000, 0.2332185000, 0.5365755000, 1.3760160000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0311282000, 0.0327288000, 0.0368553000, 0.0475018000, 0.0746965000, 0.1464447000, 0.3414915000", \ - "0.0352322000, 0.0368097000, 0.0409928000, 0.0516624000, 0.0787714000, 0.1505795000, 0.3457818000", \ - "0.0440487000, 0.0456668000, 0.0498332000, 0.0603915000, 0.0875955000, 0.1593170000, 0.3544554000", \ - "0.0586347000, 0.0605974000, 0.0657491000, 0.0786288000, 0.1075242000, 0.1797699000, 0.3751837000", \ - "0.0764732000, 0.0794898000, 0.0869956000, 0.1046666000, 0.1434831000, 0.2253637000, 0.4221830000", \ - "0.0867694000, 0.0913273000, 0.1030544000, 0.1310407000, 0.1906432000, 0.3044813000, 0.5294937000", \ - "0.0631228000, 0.0702413000, 0.0891477000, 0.1328587000, 0.2269964000, 0.4039412000, 0.7166283000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0958201000, 0.0999465000, 0.1112395000, 0.1411028000, 0.2221349000, 0.4442295000, 1.0577740000", \ - "0.1004321000, 0.1044370000, 0.1156871000, 0.1458819000, 0.2274115000, 0.4498095000, 1.0634760000", \ - "0.1128341000, 0.1168922000, 0.1281325000, 0.1584623000, 0.2405042000, 0.4632803000, 1.0773623000", \ - "0.1413854000, 0.1454214000, 0.1565211000, 0.1865053000, 0.2683905000, 0.4916015000, 1.1072346000", \ - "0.1968080000, 0.2014698000, 0.2141332000, 0.2471047000, 0.3287854000, 0.5521530000, 1.1669459000", \ - "0.2901398000, 0.2964992000, 0.3146382000, 0.3574306000, 0.4589449000, 0.6893250000, 1.3050595000", \ - "0.4431708000, 0.4537099000, 0.4811592000, 0.5474226000, 0.6905942000, 0.9867633000, 1.6253212000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0231988000, 0.0248576000, 0.0293108000, 0.0420434000, 0.0772499000, 0.1758112000, 0.4499320000", \ - "0.0229577000, 0.0245378000, 0.0291932000, 0.0419058000, 0.0771907000, 0.1758549000, 0.4503029000", \ - "0.0240200000, 0.0255592000, 0.0298330000, 0.0421251000, 0.0770830000, 0.1758114000, 0.4504337000", \ - "0.0314309000, 0.0330302000, 0.0373843000, 0.0488803000, 0.0803019000, 0.1758396000, 0.4501909000", \ - "0.0484758000, 0.0504425000, 0.0558919000, 0.0688840000, 0.1012075000, 0.1869901000, 0.4511320000", \ - "0.0811204000, 0.0839209000, 0.0914450000, 0.1096956000, 0.1510729000, 0.2409694000, 0.4778407000", \ - "0.1406908000, 0.1451499000, 0.1568563000, 0.1846483000, 0.2427167000, 0.3594391000, 0.6027385000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0615719000, 0.0667391000, 0.0813502000, 0.1213981000, 0.2314243000, 0.5347034000, 1.3752263000", \ - "0.0615385000, 0.0667511000, 0.0812533000, 0.1214122000, 0.2315344000, 0.5367874000, 1.3734835000", \ - "0.0615161000, 0.0667367000, 0.0813305000, 0.1213695000, 0.2321068000, 0.5346686000, 1.3772026000", \ - "0.0618991000, 0.0671529000, 0.0814725000, 0.1214413000, 0.2314093000, 0.5350111000, 1.3794101000", \ - "0.0758574000, 0.0808319000, 0.0937975000, 0.1297202000, 0.2336147000, 0.5357017000, 1.3782051000", \ - "0.1097782000, 0.1153273000, 0.1306525000, 0.1698676000, 0.2679934000, 0.5443811000, 1.3796602000", \ - "0.1865709000, 0.1938578000, 0.2131081000, 0.2597290000, 0.3700620000, 0.6355417000, 1.3943194000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0253204000, 0.0268810000, 0.0310538000, 0.0417599000, 0.0688895000, 0.1405238000, 0.3356658000", \ - "0.0292807000, 0.0308821000, 0.0350345000, 0.0457105000, 0.0728136000, 0.1446683000, 0.3396256000", \ - "0.0395393000, 0.0411724000, 0.0452619000, 0.0555474000, 0.0825585000, 0.1542146000, 0.3494262000", \ - "0.0541514000, 0.0564205000, 0.0623959000, 0.0763697000, 0.1060414000, 0.1769818000, 0.3721317000", \ - "0.0678947000, 0.0712211000, 0.0798187000, 0.1010801000, 0.1458213000, 0.2317507000, 0.4257032000", \ - "0.0704145000, 0.0756529000, 0.0892912000, 0.1216491000, 0.1898165000, 0.3181257000, 0.5505554000", \ - "0.0312214000, 0.0390992000, 0.0593938000, 0.1079028000, 0.2135519000, 0.4127104000, 0.7669163000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0764909000, 0.0812894000, 0.0939253000, 0.1271147000, 0.2171862000, 0.4587051000, 1.1287744000", \ - "0.0801710000, 0.0849917000, 0.0976537000, 0.1317271000, 0.2210186000, 0.4646113000, 1.1347335000", \ - "0.0926680000, 0.0971861000, 0.1095242000, 0.1429885000, 0.2338495000, 0.4802753000, 1.1583539000", \ - "0.1215655000, 0.1261837000, 0.1383642000, 0.1710256000, 0.2606992000, 0.5096031000, 1.1791419000", \ - "0.1725208000, 0.1783708000, 0.1934966000, 0.2314414000, 0.3214936000, 0.5658638000, 1.2400411000", \ - "0.2567967000, 0.2657464000, 0.2875468000, 0.3404835000, 0.4543893000, 0.7061624000, 1.3801605000", \ - "0.3926455000, 0.4070994000, 0.4426537000, 0.5257806000, 0.6914706000, 1.0160528000, 1.7055843000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0232730000, 0.0249104000, 0.0294541000, 0.0420808000, 0.0773216000, 0.1757352000, 0.4505714000", \ - "0.0222893000, 0.0240506000, 0.0288104000, 0.0418111000, 0.0771574000, 0.1758837000, 0.4499137000", \ - "0.0249452000, 0.0263488000, 0.0303776000, 0.0421076000, 0.0767777000, 0.1757663000, 0.4502309000", \ - "0.0345889000, 0.0365562000, 0.0416579000, 0.0535602000, 0.0827754000, 0.1756595000, 0.4503196000", \ - "0.0541310000, 0.0569455000, 0.0641108000, 0.0801499000, 0.1162156000, 0.1954871000, 0.4506411000", \ - "0.0888767000, 0.0931751000, 0.1040160000, 0.1276170000, 0.1783571000, 0.2756267000, 0.4942272000", \ - "0.1494559000, 0.1563394000, 0.1745322000, 0.2125149000, 0.2867950000, 0.4250358000, 0.6798170000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013852900, 0.0038380400, 0.0106336000, 0.0294610000, 0.0816240000, 0.2261450000"); - values("0.0459677000, 0.0516783000, 0.0672976000, 0.1110813000, 0.2316182000, 0.5632186000, 1.4771047000", \ - "0.0460823000, 0.0517103000, 0.0673858000, 0.1109780000, 0.2311902000, 0.5631665000, 1.4840030000", \ - "0.0461927000, 0.0518628000, 0.0676066000, 0.1110636000, 0.2315113000, 0.5651321000, 1.4942887000", \ - "0.0476548000, 0.0530137000, 0.0680697000, 0.1114555000, 0.2312583000, 0.5649680000, 1.4814626000", \ - "0.0634547000, 0.0687903000, 0.0836265000, 0.1215533000, 0.2345455000, 0.5647436000, 1.4807072000", \ - "0.0986990000, 0.1048536000, 0.1214192000, 0.1634172000, 0.2691035000, 0.5723181000, 1.4800516000", \ - "0.1763009000, 0.1844642000, 0.2063255000, 0.2561083000, 0.3771322000, 0.6629259000, 1.4947281000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311o_1") { - leakage_power () { - value : 0.0025248000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0028009000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0028230000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0028211000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0033112000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0028255000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0031925000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025248000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0031549000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0004016000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0008348000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004831000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0015461000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0003897000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0004643000; - when : "A1&A2&A3&B1&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a311o"; - cell_leakage_power : 0.0015669190; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045535000, 0.0045549000, 0.0045582000, 0.0045606000, 0.0045662000, 0.0045790000, 0.0046086000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003259200, -0.003261300, -0.003266200, -0.003258000, -0.003239400, -0.003196300, -0.003097000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023540000; - } - pin ("A2") { - capacitance : 0.0023030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043419000, 0.0043345000, 0.0043175000, 0.0043318000, 0.0043648000, 0.0044408000, 0.0046159000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004066300, -0.004066000, -0.004065300, -0.004064500, -0.004062600, -0.004058300, -0.004048200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024010000; - } - pin ("A3") { - capacitance : 0.0023750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044019000, 0.0043983000, 0.0043900000, 0.0043903000, 0.0043909000, 0.0043922000, 0.0043953000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004389700, -0.004388500, -0.004385800, -0.004386400, -0.004387700, -0.004390900, -0.004398200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025290000; - } - pin ("B1") { - capacitance : 0.0023380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038171000, 0.0038157000, 0.0038126000, 0.0038138000, 0.0038164000, 0.0038225000, 0.0038366000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003470400, -0.003531700, -0.003673200, -0.003677100, -0.003686000, -0.003706600, -0.003754000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025140000; - } - pin ("C1") { - capacitance : 0.0022530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027920000, 0.0027884000, 0.0027801000, 0.0027874000, 0.0028041000, 0.0028427000, 0.0029317000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001749500, -0.001747600, -0.001743500, -0.001745600, -0.001750400, -0.001761700, -0.001787600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024460000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0135142000, 0.0127730000, 0.0106676000, 0.0039613000, -0.016158800, -0.070783800, -0.211938700", \ - "0.0133483000, 0.0125805000, 0.0104568000, 0.0038072000, -0.016317800, -0.070924500, -0.212091300", \ - "0.0130947000, 0.0123474000, 0.0102367000, 0.0034975000, -0.016593000, -0.071210600, -0.212361100", \ - "0.0128547000, 0.0120560000, 0.0099513000, 0.0032581000, -0.016883900, -0.071478500, -0.212641700", \ - "0.0125766000, 0.0118046000, 0.0096384000, 0.0029712000, -0.017147300, -0.071732000, -0.212859100", \ - "0.0120479000, 0.0112871000, 0.0093696000, 0.0027546000, -0.017243500, -0.071806600, -0.212932300", \ - "0.0163972000, 0.0151089000, 0.0118747000, 0.0037368000, -0.017428700, -0.071871600, -0.212955100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0138863000, 0.0152612000, 0.0187227000, 0.0272282000, 0.0487182000, 0.1034679000, 0.2438639000", \ - "0.0137897000, 0.0151948000, 0.0186390000, 0.0271573000, 0.0484736000, 0.1028646000, 0.2437263000", \ - "0.0136351000, 0.0150378000, 0.0184881000, 0.0270109000, 0.0483258000, 0.1029144000, 0.2424830000", \ - "0.0135170000, 0.0149064000, 0.0183882000, 0.0268665000, 0.0481840000, 0.1027007000, 0.2424873000", \ - "0.0134228000, 0.0147948000, 0.0181688000, 0.0266533000, 0.0479668000, 0.1025119000, 0.2420734000", \ - "0.0139255000, 0.0151997000, 0.0184457000, 0.0265188000, 0.0480284000, 0.1027688000, 0.2430082000", \ - "0.0151617000, 0.0163510000, 0.0195900000, 0.0279055000, 0.0487142000, 0.1033971000, 0.2418868000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0164584000, 0.0156567000, 0.0135502000, 0.0069138000, -0.013002700, -0.067487900, -0.208529000", \ - "0.0163201000, 0.0155260000, 0.0134181000, 0.0067863000, -0.013145900, -0.067574000, -0.208631400", \ - "0.0161277000, 0.0152804000, 0.0132119000, 0.0065603000, -0.013341700, -0.067801200, -0.208856700", \ - "0.0158565000, 0.0150988000, 0.0129440000, 0.0062858000, -0.013622400, -0.068056400, -0.209113700", \ - "0.0156198000, 0.0148123000, 0.0126344000, 0.0060370000, -0.013904200, -0.068349600, -0.209385600", \ - "0.0154261000, 0.0146389000, 0.0124816000, 0.0058623000, -0.014061600, -0.068492200, -0.209505400", \ - "0.0194711000, 0.0181940000, 0.0149553000, 0.0066983000, -0.014560500, -0.068697700, -0.209668500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0146634000, 0.0160672000, 0.0195099000, 0.0279407000, 0.0491466000, 0.1035077000, 0.2430634000", \ - "0.0145410000, 0.0159273000, 0.0194198000, 0.0278636000, 0.0490714000, 0.1038705000, 0.2441759000", \ - "0.0144335000, 0.0158369000, 0.0192495000, 0.0277407000, 0.0489541000, 0.1032980000, 0.2439346000", \ - "0.0142977000, 0.0156934000, 0.0191428000, 0.0276136000, 0.0488362000, 0.1036298000, 0.2437738000", \ - "0.0142399000, 0.0156267000, 0.0189840000, 0.0275033000, 0.0487704000, 0.1031385000, 0.2429126000", \ - "0.0148329000, 0.0160796000, 0.0193250000, 0.0272932000, 0.0487416000, 0.1034859000, 0.2436549000", \ - "0.0155744000, 0.0166742000, 0.0198573000, 0.0281607000, 0.0493833000, 0.1040926000, 0.2424326000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0187237000, 0.0179036000, 0.0157348000, 0.0089403000, -0.011337500, -0.066411300, -0.207966400", \ - "0.0185913000, 0.0178135000, 0.0156058000, 0.0088277000, -0.011471500, -0.066554900, -0.208067300", \ - "0.0183951000, 0.0175702000, 0.0154165000, 0.0086378000, -0.011664000, -0.066723400, -0.208233400", \ - "0.0181482000, 0.0173304000, 0.0151588000, 0.0084433000, -0.011932000, -0.066936500, -0.208423800", \ - "0.0179906000, 0.0172037000, 0.0149961000, 0.0081991000, -0.012105200, -0.067082000, -0.208558400", \ - "0.0179128000, 0.0170900000, 0.0149029000, 0.0081258000, -0.012056800, -0.066941200, -0.208387000", \ - "0.0222992000, 0.0210025000, 0.0176727000, 0.0092657000, -0.012182900, -0.066654600, -0.208060000"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0150551000, 0.0164568000, 0.0198676000, 0.0283591000, 0.0493912000, 0.1035920000, 0.2430176000", \ - "0.0149451000, 0.0163490000, 0.0197608000, 0.0282105000, 0.0493256000, 0.1035035000, 0.2429444000", \ - "0.0148024000, 0.0161971000, 0.0196487000, 0.0280876000, 0.0491810000, 0.1033644000, 0.2430099000", \ - "0.0146059000, 0.0159963000, 0.0194456000, 0.0278879000, 0.0490351000, 0.1032747000, 0.2427237000", \ - "0.0144512000, 0.0158222000, 0.0192436000, 0.0276570000, 0.0489156000, 0.1032300000, 0.2426555000", \ - "0.0149864000, 0.0162472000, 0.0195007000, 0.0275089000, 0.0489500000, 0.1035344000, 0.2437137000", \ - "0.0156263000, 0.0168727000, 0.0201132000, 0.0282800000, 0.0494047000, 0.1040356000, 0.2424033000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0166075000, 0.0158671000, 0.0136506000, 0.0069442000, -0.013259900, -0.068023900, -0.209262900", \ - "0.0164933000, 0.0157062000, 0.0135009000, 0.0067336000, -0.013407200, -0.068160800, -0.209404500", \ - "0.0162868000, 0.0154897000, 0.0133047000, 0.0065557000, -0.013609800, -0.068350200, -0.209591000", \ - "0.0160442000, 0.0152864000, 0.0130682000, 0.0063378000, -0.013833200, -0.068533400, -0.209758200", \ - "0.0159119000, 0.0151368000, 0.0129485000, 0.0061859000, -0.013972300, -0.068646600, -0.209849100", \ - "0.0158623000, 0.0150177000, 0.0128348000, 0.0060914000, -0.013984600, -0.068627500, -0.209813700", \ - "0.0204775000, 0.0191557000, 0.0158388000, 0.0073827000, -0.014182800, -0.068328000, -0.209541800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0123456000, 0.0137534000, 0.0172317000, 0.0257889000, 0.0472530000, 0.1021922000, 0.2424975000", \ - "0.0123804000, 0.0137877000, 0.0172559000, 0.0258244000, 0.0472772000, 0.1022160000, 0.2414096000", \ - "0.0124261000, 0.0138200000, 0.0172692000, 0.0258157000, 0.0473128000, 0.1022821000, 0.2424248000", \ - "0.0121746000, 0.0135337000, 0.0169541000, 0.0254739000, 0.0469818000, 0.1016009000, 0.2413442000", \ - "0.0120557000, 0.0133074000, 0.0166889000, 0.0251354000, 0.0466035000, 0.1013272000, 0.2410626000", \ - "0.0123875000, 0.0136764000, 0.0169849000, 0.0252719000, 0.0467605000, 0.1015264000, 0.2419086000", \ - "0.0134480000, 0.0146801000, 0.0178866000, 0.0263331000, 0.0476403000, 0.1026231000, 0.2409958000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0153084000, 0.0144942000, 0.0123984000, 0.0056613000, -0.014422800, -0.068921200, -0.209988200", \ - "0.0151775000, 0.0143437000, 0.0122814000, 0.0054881000, -0.014548200, -0.069067700, -0.210126900", \ - "0.0149826000, 0.0141639000, 0.0119772000, 0.0052896000, -0.014771700, -0.069256500, -0.210315100", \ - "0.0147673000, 0.0139955000, 0.0118222000, 0.0051088000, -0.014921500, -0.069417100, -0.210473900", \ - "0.0146965000, 0.0138559000, 0.0117297000, 0.0050220000, -0.015024100, -0.069520200, -0.210592900", \ - "0.0149166000, 0.0140980000, 0.0119943000, 0.0055289000, -0.014533200, -0.069189500, -0.210319300", \ - "0.0214319000, 0.0200687000, 0.0167140000, 0.0082517000, -0.013057200, -0.067557100, -0.208810400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0088025000, 0.0102189000, 0.0137084000, 0.0222328000, 0.0435654000, 0.0980688000, 0.2377693000", \ - "0.0087537000, 0.0101646000, 0.0136462000, 0.0221796000, 0.0437426000, 0.0981220000, 0.2379965000", \ - "0.0086068000, 0.0099936000, 0.0134397000, 0.0219822000, 0.0433530000, 0.0979477000, 0.2376636000", \ - "0.0083446000, 0.0097031000, 0.0131114000, 0.0216415000, 0.0430765000, 0.0977088000, 0.2374364000", \ - "0.0082839000, 0.0095276000, 0.0128607000, 0.0212951000, 0.0427251000, 0.0975206000, 0.2385973000", \ - "0.0086871000, 0.0100130000, 0.0132949000, 0.0215857000, 0.0429671000, 0.0977311000, 0.2377518000", \ - "0.0103191000, 0.0115263000, 0.0147188000, 0.0231427000, 0.0444502000, 0.0992936000, 0.2374344000"); - } - } - max_capacitance : 0.1428320000; - max_transition : 1.5016510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2226796000, 0.2308025000, 0.2478031000, 0.2801207000, 0.3408397000, 0.4649972000, 0.7533936000", \ - "0.2270763000, 0.2354048000, 0.2520264000, 0.2844328000, 0.3452816000, 0.4694158000, 0.7577937000", \ - "0.2385053000, 0.2466070000, 0.2635876000, 0.2958696000, 0.3566146000, 0.4807932000, 0.7692059000", \ - "0.2663982000, 0.2747192000, 0.2916035000, 0.3237804000, 0.3844765000, 0.5087573000, 0.7972971000", \ - "0.3272130000, 0.3354627000, 0.3523574000, 0.3846312000, 0.4453938000, 0.5695393000, 0.8578132000", \ - "0.4440893000, 0.4529030000, 0.4711618000, 0.5048136000, 0.5678068000, 0.6932050000, 0.9820833000", \ - "0.6435592000, 0.6539141000, 0.6745907000, 0.7131760000, 0.7826882000, 0.9156797000, 1.2081355000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1075606000, 0.1163637000, 0.1355559000, 0.1773184000, 0.2758925000, 0.5252785000, 1.1607705000", \ - "0.1113070000, 0.1201133000, 0.1392393000, 0.1810448000, 0.2795478000, 0.5287518000, 1.1648656000", \ - "0.1207082000, 0.1294935000, 0.1486449000, 0.1904118000, 0.2892508000, 0.5374823000, 1.1709516000", \ - "0.1435738000, 0.1522991000, 0.1713277000, 0.2128880000, 0.3116260000, 0.5598937000, 1.1938264000", \ - "0.1854491000, 0.1943267000, 0.2135534000, 0.2561366000, 0.3545697000, 0.6022624000, 1.2358677000", \ - "0.2385575000, 0.2480546000, 0.2681979000, 0.3106804000, 0.4093147000, 0.6578114000, 1.2948532000", \ - "0.2773800000, 0.2895448000, 0.3134010000, 0.3583593000, 0.4566829000, 0.7053979000, 1.3389578000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0314896000, 0.0372776000, 0.0500753000, 0.0752816000, 0.1324759000, 0.2699942000, 0.6407364000", \ - "0.0315241000, 0.0370480000, 0.0495981000, 0.0752619000, 0.1324715000, 0.2699428000, 0.6397012000", \ - "0.0314949000, 0.0372657000, 0.0500483000, 0.0751527000, 0.1324692000, 0.2699715000, 0.6407614000", \ - "0.0314964000, 0.0371427000, 0.0497150000, 0.0760617000, 0.1325231000, 0.2697434000, 0.6385256000", \ - "0.0315655000, 0.0372016000, 0.0500251000, 0.0751965000, 0.1325041000, 0.2697524000, 0.6395568000", \ - "0.0352374000, 0.0409611000, 0.0543386000, 0.0799448000, 0.1360749000, 0.2719857000, 0.6408059000", \ - "0.0435075000, 0.0500362000, 0.0636340000, 0.0926276000, 0.1511152000, 0.2846932000, 0.6427409000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0314856000, 0.0398770000, 0.0596200000, 0.1101463000, 0.2431404000, 0.5925345000, 1.4943096000", \ - "0.0315495000, 0.0396601000, 0.0596227000, 0.1098708000, 0.2437115000, 0.5935277000, 1.4941698000", \ - "0.0315079000, 0.0396278000, 0.0595341000, 0.1099456000, 0.2429537000, 0.5922168000, 1.4889704000", \ - "0.0311084000, 0.0391041000, 0.0591181000, 0.1096267000, 0.2430383000, 0.5929991000, 1.4910028000", \ - "0.0329129000, 0.0409663000, 0.0603933000, 0.1104724000, 0.2433418000, 0.5919575000, 1.4893797000", \ - "0.0376623000, 0.0454112000, 0.0633226000, 0.1117270000, 0.2443121000, 0.5931262000, 1.4916401000", \ - "0.0495674000, 0.0572088000, 0.0750283000, 0.1184086000, 0.2456886000, 0.5952331000, 1.4912692000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2670134000, 0.2759333000, 0.2939742000, 0.3277145000, 0.3908224000, 0.5171312000, 0.8068082000", \ - "0.2715538000, 0.2804819000, 0.2984313000, 0.3323629000, 0.3948867000, 0.5212736000, 0.8111442000", \ - "0.2831259000, 0.2920283000, 0.3097904000, 0.3438738000, 0.4069336000, 0.5328519000, 0.8228059000", \ - "0.3109772000, 0.3198791000, 0.3379683000, 0.3711343000, 0.4342846000, 0.5606949000, 0.8504844000", \ - "0.3705830000, 0.3794680000, 0.3974154000, 0.4309401000, 0.4939513000, 0.6204682000, 0.9105176000", \ - "0.4905205000, 0.4998977000, 0.5184844000, 0.5531297000, 0.6165742000, 0.7441965000, 1.0344130000", \ - "0.7005497000, 0.7112038000, 0.7325384000, 0.7712648000, 0.8414096000, 0.9738201000, 1.2673500000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1163081000, 0.1250946000, 0.1442003000, 0.1858176000, 0.2839083000, 0.5311533000, 1.1656052000", \ - "0.1201864000, 0.1290282000, 0.1482242000, 0.1897694000, 0.2880079000, 0.5363396000, 1.1708551000", \ - "0.1291326000, 0.1379328000, 0.1569985000, 0.1986615000, 0.2966608000, 0.5444679000, 1.1806885000", \ - "0.1498459000, 0.1585422000, 0.1775621000, 0.2191078000, 0.3173900000, 0.5660081000, 1.2013669000", \ - "0.1902236000, 0.1992350000, 0.2184797000, 0.2603650000, 0.3588803000, 0.6069057000, 1.2399889000", \ - "0.2452826000, 0.2551528000, 0.2757015000, 0.3189306000, 0.4180110000, 0.6657928000, 1.3025000000", \ - "0.2922886000, 0.3051586000, 0.3293343000, 0.3754915000, 0.4751324000, 0.7233448000, 1.3570665000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0357690000, 0.0410866000, 0.0541790000, 0.0791645000, 0.1371724000, 0.2740108000, 0.6410107000", \ - "0.0355318000, 0.0414771000, 0.0533274000, 0.0791095000, 0.1368366000, 0.2742326000, 0.6412600000", \ - "0.0359633000, 0.0410046000, 0.0534832000, 0.0793567000, 0.1369184000, 0.2741700000, 0.6416197000", \ - "0.0358117000, 0.0416706000, 0.0534710000, 0.0805294000, 0.1371589000, 0.2742889000, 0.6406310000", \ - "0.0355793000, 0.0411489000, 0.0532864000, 0.0796256000, 0.1368835000, 0.2743013000, 0.6410792000", \ - "0.0381570000, 0.0438041000, 0.0560525000, 0.0814896000, 0.1390044000, 0.2755285000, 0.6427215000", \ - "0.0454746000, 0.0520280000, 0.0660442000, 0.0925794000, 0.1508503000, 0.2871582000, 0.6456893000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0315114000, 0.0396701000, 0.0596278000, 0.1101265000, 0.2435397000, 0.5924889000, 1.4934911000", \ - "0.0315905000, 0.0397070000, 0.0596991000, 0.1100397000, 0.2438131000, 0.5938028000, 1.4949608000", \ - "0.0315048000, 0.0395504000, 0.0596075000, 0.1098986000, 0.2436848000, 0.5935719000, 1.4947484000", \ - "0.0311892000, 0.0392822000, 0.0592218000, 0.1098738000, 0.2431443000, 0.5922922000, 1.4909570000", \ - "0.0328267000, 0.0408218000, 0.0605060000, 0.1103327000, 0.2429081000, 0.5936387000, 1.4908641000", \ - "0.0382222000, 0.0455838000, 0.0645277000, 0.1123462000, 0.2439693000, 0.5931254000, 1.4932806000", \ - "0.0498315000, 0.0571539000, 0.0756010000, 0.1193420000, 0.2459727000, 0.5967508000, 1.4909922000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.3040499000, 0.3133719000, 0.3320200000, 0.3662673000, 0.4286555000, 0.5555451000, 0.8456675000", \ - "0.3085079000, 0.3177148000, 0.3362087000, 0.3706042000, 0.4331315000, 0.5599710000, 0.8500752000", \ - "0.3200960000, 0.3294076000, 0.3480319000, 0.3822929000, 0.4448622000, 0.5717809000, 0.8619496000", \ - "0.3476778000, 0.3569996000, 0.3755237000, 0.4093439000, 0.4726992000, 0.5994429000, 0.8896203000", \ - "0.4060561000, 0.4153697000, 0.4338813000, 0.4681300000, 0.5311663000, 0.6580737000, 0.9482928000", \ - "0.5264084000, 0.5360019000, 0.5548875000, 0.5897767000, 0.6532900000, 0.7804683000, 1.0707478000", \ - "0.7393018000, 0.7503854000, 0.7717736000, 0.8107919000, 0.8804449000, 1.0138812000, 1.3074822000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1221608000, 0.1310324000, 0.1501175000, 0.1916884000, 0.2893410000, 0.5357955000, 1.1695293000", \ - "0.1262540000, 0.1350761000, 0.1541628000, 0.1957522000, 0.2933463000, 0.5397797000, 1.1737381000", \ - "0.1342999000, 0.1431713000, 0.1622396000, 0.2036882000, 0.3015874000, 0.5487719000, 1.1816028000", \ - "0.1513045000, 0.1601411000, 0.1791008000, 0.2205635000, 0.3185597000, 0.5655158000, 1.1979788000", \ - "0.1846707000, 0.1936958000, 0.2131428000, 0.2550623000, 0.3533395000, 0.6002325000, 1.2331695000", \ - "0.2333976000, 0.2431589000, 0.2639008000, 0.3071308000, 0.4061770000, 0.6535936000, 1.2900534000", \ - "0.2771922000, 0.2896464000, 0.3137829000, 0.3601908000, 0.4604081000, 0.7081840000, 1.3414218000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0387689000, 0.0446811000, 0.0576060000, 0.0839208000, 0.1416967000, 0.2783347000, 0.6451846000", \ - "0.0393585000, 0.0448354000, 0.0569089000, 0.0832926000, 0.1417932000, 0.2783846000, 0.6428822000", \ - "0.0387546000, 0.0445847000, 0.0577404000, 0.0827906000, 0.1417964000, 0.2784164000, 0.6433915000", \ - "0.0387261000, 0.0445397000, 0.0568460000, 0.0842545000, 0.1417167000, 0.2783487000, 0.6426201000", \ - "0.0386354000, 0.0445320000, 0.0569845000, 0.0830492000, 0.1415093000, 0.2783453000, 0.6437942000", \ - "0.0408809000, 0.0467789000, 0.0590454000, 0.0845416000, 0.1423014000, 0.2780135000, 0.6445223000", \ - "0.0484699000, 0.0548934000, 0.0680762000, 0.0950016000, 0.1545432000, 0.2890143000, 0.6484489000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0314455000, 0.0396851000, 0.0596628000, 0.1100393000, 0.2434528000, 0.5919994000, 1.4929440000", \ - "0.0316028000, 0.0396258000, 0.0596374000, 0.1100961000, 0.2436129000, 0.5924997000, 1.4934739000", \ - "0.0314137000, 0.0398007000, 0.0594716000, 0.1099541000, 0.2433899000, 0.5931327000, 1.4908276000", \ - "0.0311661000, 0.0395665000, 0.0592385000, 0.1099197000, 0.2431611000, 0.5916619000, 1.4894568000", \ - "0.0328940000, 0.0410336000, 0.0605292000, 0.1102308000, 0.2433335000, 0.5916850000, 1.4901663000", \ - "0.0371033000, 0.0456337000, 0.0645445000, 0.1127674000, 0.2440248000, 0.5917389000, 1.4938418000", \ - "0.0479916000, 0.0567153000, 0.0752820000, 0.1205725000, 0.2468636000, 0.5940894000, 1.4899453000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2758352000, 0.2851876000, 0.3036724000, 0.3375068000, 0.4014319000, 0.5287034000, 0.8194598000", \ - "0.2791814000, 0.2884997000, 0.3069354000, 0.3413751000, 0.4043344000, 0.5320179000, 0.8228059000", \ - "0.2890997000, 0.2984238000, 0.3169733000, 0.3513776000, 0.4142602000, 0.5420466000, 0.8328767000", \ - "0.3145814000, 0.3239245000, 0.3424235000, 0.3769355000, 0.4401421000, 0.5676721000, 0.8584617000", \ - "0.3757835000, 0.3849896000, 0.4032356000, 0.4378312000, 0.5015462000, 0.6291552000, 0.9199816000", \ - "0.5121613000, 0.5218158000, 0.5412043000, 0.5763306000, 0.6412227000, 0.7689836000, 1.0598505000", \ - "0.7569080000, 0.7686011000, 0.7915057000, 0.8319403000, 0.9030452000, 1.0371221000, 1.3317277000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0678302000, 0.0755676000, 0.0927225000, 0.1320982000, 0.2292958000, 0.4776728000, 1.1135534000", \ - "0.0726481000, 0.0803728000, 0.0975057000, 0.1368661000, 0.2340106000, 0.4825871000, 1.1158801000", \ - "0.0837282000, 0.0913938000, 0.1084243000, 0.1477411000, 0.2451531000, 0.4934003000, 1.1293266000", \ - "0.1070317000, 0.1147428000, 0.1317582000, 0.1710706000, 0.2690652000, 0.5163924000, 1.1502780000", \ - "0.1403408000, 0.1490739000, 0.1673067000, 0.2071534000, 0.3050088000, 0.5530062000, 1.1868728000", \ - "0.1749919000, 0.1863029000, 0.2077198000, 0.2497619000, 0.3474829000, 0.5952643000, 1.2327224000", \ - "0.1874508000, 0.2028586000, 0.2310768000, 0.2802001000, 0.3795719000, 0.6278146000, 1.2609475000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0388407000, 0.0448641000, 0.0569791000, 0.0843939000, 0.1411811000, 0.2781229000, 0.6432210000", \ - "0.0393989000, 0.0450314000, 0.0568958000, 0.0832243000, 0.1410304000, 0.2781463000, 0.6428603000", \ - "0.0387315000, 0.0445589000, 0.0578023000, 0.0840884000, 0.1415287000, 0.2781510000, 0.6429121000", \ - "0.0388171000, 0.0447694000, 0.0569411000, 0.0829469000, 0.1414005000, 0.2780097000, 0.6435214000", \ - "0.0392197000, 0.0446983000, 0.0572469000, 0.0832201000, 0.1408793000, 0.2771466000, 0.6446327000", \ - "0.0418131000, 0.0478980000, 0.0596857000, 0.0851561000, 0.1421519000, 0.2777469000, 0.6441261000", \ - "0.0535122000, 0.0604337000, 0.0729923000, 0.0990285000, 0.1547293000, 0.2891426000, 0.6464521000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0255601000, 0.0329904000, 0.0519951000, 0.1032131000, 0.2392189000, 0.5911829000, 1.4912612000", \ - "0.0255414000, 0.0329428000, 0.0519944000, 0.1031909000, 0.2393919000, 0.5908424000, 1.4929672000", \ - "0.0255210000, 0.0329685000, 0.0520253000, 0.1032076000, 0.2390339000, 0.5913965000, 1.4901352000", \ - "0.0267316000, 0.0338582000, 0.0523322000, 0.1033620000, 0.2396917000, 0.5888186000, 1.4923022000", \ - "0.0326436000, 0.0391598000, 0.0560739000, 0.1048960000, 0.2390380000, 0.5905897000, 1.4869723000", \ - "0.0446959000, 0.0506899000, 0.0653008000, 0.1093408000, 0.2405264000, 0.5889304000, 1.4897220000", \ - "0.0633445000, 0.0706320000, 0.0847471000, 0.1230965000, 0.2439013000, 0.5929635000, 1.4845662000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2319520000, 0.2412628000, 0.2596018000, 0.2942413000, 0.3580646000, 0.4861436000, 0.7772181000", \ - "0.2347368000, 0.2439537000, 0.2624774000, 0.2970222000, 0.3612556000, 0.4891411000, 0.7802778000", \ - "0.2425301000, 0.2518656000, 0.2702595000, 0.3047621000, 0.3687709000, 0.4968561000, 0.7879977000", \ - "0.2655725000, 0.2750289000, 0.2933931000, 0.3280046000, 0.3923027000, 0.5198927000, 0.8110765000", \ - "0.3263418000, 0.3356286000, 0.3541499000, 0.3888575000, 0.4528558000, 0.5808887000, 0.8719742000", \ - "0.4643432000, 0.4744390000, 0.4933206000, 0.5278504000, 0.5925365000, 0.7206103000, 1.0115810000", \ - "0.6912358000, 0.7039047000, 0.7279940000, 0.7683376000, 0.8356300000, 0.9666782000, 1.2614370000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0631436000, 0.0712051000, 0.0887841000, 0.1283166000, 0.2251889000, 0.4726800000, 1.1049963000", \ - "0.0680542000, 0.0760990000, 0.0936522000, 0.1331062000, 0.2302966000, 0.4786472000, 1.1103222000", \ - "0.0792341000, 0.0871887000, 0.1046320000, 0.1442139000, 0.2412648000, 0.4889574000, 1.1222145000", \ - "0.1014615000, 0.1095610000, 0.1271097000, 0.1667262000, 0.2640000000, 0.5118851000, 1.1446351000", \ - "0.1326036000, 0.1418795000, 0.1607841000, 0.2013373000, 0.2989453000, 0.5474957000, 1.1871329000", \ - "0.1656020000, 0.1777531000, 0.2004963000, 0.2436462000, 0.3417162000, 0.5893205000, 1.2264630000", \ - "0.1805884000, 0.1971455000, 0.2273388000, 0.2790068000, 0.3793848000, 0.6271417000, 1.2609815000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0387487000, 0.0445736000, 0.0572698000, 0.0831592000, 0.1406847000, 0.2771971000, 0.6440065000", \ - "0.0391971000, 0.0445584000, 0.0577338000, 0.0826892000, 0.1405265000, 0.2778868000, 0.6419220000", \ - "0.0387026000, 0.0444304000, 0.0568244000, 0.0831290000, 0.1407136000, 0.2771514000, 0.6440946000", \ - "0.0392136000, 0.0455781000, 0.0573173000, 0.0833614000, 0.1408559000, 0.2774781000, 0.6442473000", \ - "0.0384217000, 0.0444588000, 0.0567679000, 0.0826492000, 0.1404895000, 0.2778002000, 0.6425020000", \ - "0.0431487000, 0.0484973000, 0.0602077000, 0.0859488000, 0.1428938000, 0.2782073000, 0.6436184000", \ - "0.0598108000, 0.0661162000, 0.0778307000, 0.1001210000, 0.1528117000, 0.2867284000, 0.6476868000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0259956000, 0.0335625000, 0.0525143000, 0.1033745000, 0.2389357000, 0.5925261000, 1.4907449000", \ - "0.0260160000, 0.0335972000, 0.0525239000, 0.1033454000, 0.2396543000, 0.5945737000, 1.4938134000", \ - "0.0260980000, 0.0337209000, 0.0525759000, 0.1034083000, 0.2388267000, 0.5918563000, 1.4874392000", \ - "0.0278786000, 0.0350842000, 0.0534368000, 0.1036453000, 0.2389856000, 0.5922927000, 1.4903596000", \ - "0.0346599000, 0.0412089000, 0.0578611000, 0.1060484000, 0.2388924000, 0.5930672000, 1.5016509000", \ - "0.0484279000, 0.0547954000, 0.0688678000, 0.1113589000, 0.2409098000, 0.5891319000, 1.4904002000", \ - "0.0690753000, 0.0766049000, 0.0907138000, 0.1278889000, 0.2457038000, 0.5914374000, 1.4868878000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311o_2") { - leakage_power () { - value : 0.0029615000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0037972000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0029615000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0038196000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0029615000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0038199000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0029616000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0043208000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0029615000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0038241000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0029616000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0042041000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0029617000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0041880000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008914000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0013072000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0009541000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0018434000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0008762000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0009407000; - when : "A1&A2&A3&B1&!C1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a311o"; - cell_leakage_power : 0.0021471640; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045247000, 0.0045249000, 0.0045253000, 0.0045272000, 0.0045315000, 0.0045415000, 0.0045647000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003446700, -0.003449700, -0.003456600, -0.003449400, -0.003432700, -0.003394200, -0.003305400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023610000; - } - pin ("A2") { - capacitance : 0.0023050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043767000, 0.0043701000, 0.0043548000, 0.0043705000, 0.0044065000, 0.0044897000, 0.0046813000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004000600, -0.003999800, -0.003997900, -0.003998000, -0.003998100, -0.003998400, -0.003999100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024060000; - } - pin ("A3") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043035000, 0.0043025000, 0.0043001000, 0.0042996000, 0.0042984000, 0.0042956000, 0.0042892000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004293400, -0.004291600, -0.004287600, -0.004287700, -0.004288100, -0.004288900, -0.004290700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024870000; - } - pin ("B1") { - capacitance : 0.0022710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0037777000, 0.0037752000, 0.0037695000, 0.0037675000, 0.0037629000, 0.0037522000, 0.0037276000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003421400, -0.003482800, -0.003624200, -0.003628000, -0.003636800, -0.003657100, -0.003703800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024340000; - } - pin ("C1") { - capacitance : 0.0022340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027756000, 0.0027720000, 0.0027637000, 0.0027712000, 0.0027883000, 0.0028279000, 0.0029192000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001729300, -0.001730900, -0.001734600, -0.001736500, -0.001740700, -0.001750600, -0.001773400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024290000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0162455000, 0.0147410000, 0.0111431000, 0.0004263000, -0.034233600, -0.141787900, -0.458312100", \ - "0.0161312000, 0.0146280000, 0.0110405000, 0.0003123000, -0.034337500, -0.141887900, -0.458412900", \ - "0.0158869000, 0.0144354000, 0.0107926000, 0.0001136000, -0.034514800, -0.142147900, -0.458705500", \ - "0.0155856000, 0.0141972000, 0.0104444000, -0.000222800, -0.034896300, -0.142476300, -0.459026700", \ - "0.0153033000, 0.0138113000, 0.0102904000, -0.000550800, -0.035158500, -0.142779100, -0.459323300", \ - "0.0153236000, 0.0138051000, 0.0101380000, -0.000605700, -0.035347100, -0.142938300, -0.459427600", \ - "0.0212829000, 0.0195610000, 0.0148871000, 0.0019237000, -0.035457800, -0.143033700, -0.459432800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0191543000, 0.0208119000, 0.0255908000, 0.0388868000, 0.0764411000, 0.1845702000, 0.5000895000", \ - "0.0190538000, 0.0206961000, 0.0254295000, 0.0388283000, 0.0763369000, 0.1843851000, 0.5001461000", \ - "0.0189105000, 0.0205623000, 0.0253065000, 0.0386880000, 0.0761578000, 0.1842733000, 0.5000343000", \ - "0.0187411000, 0.0203911000, 0.0251920000, 0.0385812000, 0.0761285000, 0.1840421000, 0.4999427000", \ - "0.0189839000, 0.0205949000, 0.0252416000, 0.0385550000, 0.0758268000, 0.1841133000, 0.4992304000", \ - "0.0196229000, 0.0211284000, 0.0255880000, 0.0382358000, 0.0756779000, 0.1833228000, 0.4971957000", \ - "0.0212658000, 0.0227167000, 0.0270033000, 0.0400367000, 0.0764262000, 0.1848085000, 0.4960919000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0189467000, 0.0174381000, 0.0137701000, 0.0030180000, -0.031559600, -0.138907200, -0.455367300", \ - "0.0188455000, 0.0173440000, 0.0137014000, 0.0029387000, -0.031666600, -0.139005100, -0.455467500", \ - "0.0186761000, 0.0171429000, 0.0135550000, 0.0028522000, -0.031754300, -0.139212500, -0.455646400", \ - "0.0184058000, 0.0169145000, 0.0132675000, 0.0024943000, -0.032124900, -0.139449200, -0.455908700", \ - "0.0181526000, 0.0166242000, 0.0130195000, 0.0022572000, -0.032424100, -0.139787400, -0.456188000", \ - "0.0182376000, 0.0166735000, 0.0129542000, 0.0021163000, -0.032596100, -0.139997500, -0.456364700", \ - "0.0236653000, 0.0223688000, 0.0176166000, 0.0044832000, -0.033250200, -0.140271800, -0.456609000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0196856000, 0.0213511000, 0.0261292000, 0.0394215000, 0.0768473000, 0.1847866000, 0.5001878000", \ - "0.0196226000, 0.0212508000, 0.0260250000, 0.0393193000, 0.0767592000, 0.1847012000, 0.4998970000", \ - "0.0194622000, 0.0211032000, 0.0258520000, 0.0392166000, 0.0766259000, 0.1845683000, 0.5001624000", \ - "0.0192803000, 0.0209248000, 0.0257124000, 0.0390924000, 0.0765823000, 0.1843641000, 0.5001227000", \ - "0.0193335000, 0.0209398000, 0.0256455000, 0.0388826000, 0.0765209000, 0.1845603000, 0.4998415000", \ - "0.0201317000, 0.0216551000, 0.0261389000, 0.0387332000, 0.0759204000, 0.1840805000, 0.4998125000", \ - "0.0213606000, 0.0228308000, 0.0272128000, 0.0402105000, 0.0773631000, 0.1855438000, 0.4993740000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0215996000, 0.0200887000, 0.0163870000, 0.0057794000, -0.029071500, -0.137017000, -0.453796900", \ - "0.0216613000, 0.0201755000, 0.0164968000, 0.0056240000, -0.029304000, -0.137125800, -0.453913000", \ - "0.0215565000, 0.0200081000, 0.0163120000, 0.0055175000, -0.029476600, -0.137276000, -0.454026200", \ - "0.0213039000, 0.0196625000, 0.0160843000, 0.0052194000, -0.029687600, -0.137482300, -0.454253300", \ - "0.0210245000, 0.0195052000, 0.0158124000, 0.0048911000, -0.029906100, -0.137678900, -0.454413300", \ - "0.0209956000, 0.0194651000, 0.0156971000, 0.0048080000, -0.029956200, -0.137707500, -0.454377300", \ - "0.0268122000, 0.0250691000, 0.0203469000, 0.0071680000, -0.030455600, -0.137630400, -0.454232700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0199195000, 0.0215822000, 0.0262665000, 0.0396680000, 0.0770356000, 0.1847950000, 0.4996967000", \ - "0.0198733000, 0.0215083000, 0.0262701000, 0.0395653000, 0.0770199000, 0.1854470000, 0.4977019000", \ - "0.0197366000, 0.0213692000, 0.0261222000, 0.0394618000, 0.0768956000, 0.1846716000, 0.4999009000", \ - "0.0194871000, 0.0211401000, 0.0259074000, 0.0392967000, 0.0767404000, 0.1853600000, 0.4973231000", \ - "0.0194654000, 0.0211400000, 0.0258370000, 0.0390642000, 0.0765601000, 0.1845999000, 0.4974647000", \ - "0.0203092000, 0.0218427000, 0.0262817000, 0.0389471000, 0.0764380000, 0.1842761000, 0.4977108000", \ - "0.0210792000, 0.0225505000, 0.0269635000, 0.0398202000, 0.0773459000, 0.1854007000, 0.4965085000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0194999000, 0.0179470000, 0.0142701000, 0.0034685000, -0.031319300, -0.138893000, -0.455474000", \ - "0.0195036000, 0.0179639000, 0.0142929000, 0.0034346000, -0.031414900, -0.139078600, -0.455620100", \ - "0.0191855000, 0.0176352000, 0.0139371000, 0.0031419000, -0.031553800, -0.139192800, -0.455776200", \ - "0.0191134000, 0.0175499000, 0.0138938000, 0.0030296000, -0.031818500, -0.139439700, -0.455998900", \ - "0.0188396000, 0.0173343000, 0.0136758000, 0.0028422000, -0.032039200, -0.139606000, -0.456125500", \ - "0.0188360000, 0.0172597000, 0.0135630000, 0.0028286000, -0.032053700, -0.139686500, -0.456156900", \ - "0.0248935000, 0.0231255000, 0.0183024000, 0.0050290000, -0.032279300, -0.139534600, -0.455956800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0172746000, 0.0189821000, 0.0238176000, 0.0373037000, 0.0751484000, 0.1834692000, 0.4985841000", \ - "0.0173279000, 0.0190315000, 0.0238757000, 0.0373278000, 0.0752029000, 0.1835319000, 0.4991787000", \ - "0.0173971000, 0.0191056000, 0.0239255000, 0.0373626000, 0.0752085000, 0.1835918000, 0.4992366000", \ - "0.0172246000, 0.0188946000, 0.0236461000, 0.0369801000, 0.0748181000, 0.1832841000, 0.4985716000", \ - "0.0172073000, 0.0187874000, 0.0234494000, 0.0366325000, 0.0743625000, 0.1829437000, 0.4982931000", \ - "0.0178378000, 0.0193767000, 0.0238884000, 0.0369700000, 0.0744295000, 0.1823659000, 0.4986469000", \ - "0.0190717000, 0.0205216000, 0.0249065000, 0.0379511000, 0.0753779000, 0.1840850000, 0.4956231000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0183548000, 0.0168046000, 0.0131421000, 0.0022383000, -0.032468200, -0.139959400, -0.456373200", \ - "0.0182648000, 0.0167392000, 0.0130739000, 0.0022487000, -0.032599100, -0.140087400, -0.456488000", \ - "0.0179943000, 0.0163949000, 0.0127731000, 0.0019380000, -0.032819000, -0.140306900, -0.456717100", \ - "0.0177820000, 0.0162959000, 0.0125957000, 0.0017806000, -0.033022400, -0.140521800, -0.456929500", \ - "0.0176102000, 0.0160540000, 0.0123912000, 0.0015907000, -0.033209400, -0.140651200, -0.457048400", \ - "0.0180429000, 0.0164289000, 0.0127102000, 0.0017926000, -0.032460000, -0.140280500, -0.456780200", \ - "0.0260520000, 0.0241971000, 0.0192964000, 0.0064544000, -0.031468300, -0.139248000, -0.455805000"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0137708000, 0.0154737000, 0.0203497000, 0.0338511000, 0.0715924000, 0.1801236000, 0.4932931000", \ - "0.0137736000, 0.0154762000, 0.0203493000, 0.0338369000, 0.0716077000, 0.1801640000, 0.4906342000", \ - "0.0136919000, 0.0153878000, 0.0202281000, 0.0336608000, 0.0714401000, 0.1799736000, 0.4961722000", \ - "0.0135019000, 0.0151687000, 0.0199232000, 0.0332729000, 0.0709791000, 0.1796417000, 0.4922712000", \ - "0.0134300000, 0.0149908000, 0.0196505000, 0.0328721000, 0.0705044000, 0.1801400000, 0.4919431000", \ - "0.0141837000, 0.0157205000, 0.0202062000, 0.0333362000, 0.0706669000, 0.1794284000, 0.4901077000", \ - "0.0157038000, 0.0171570000, 0.0214212000, 0.0345960000, 0.0719119000, 0.1802598000, 0.4918902000"); - } - } - max_capacitance : 0.2984720000; - max_transition : 1.5071490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.2761387000, 0.2837482000, 0.3006614000, 0.3342587000, 0.3982002000, 0.5297224000, 0.8463810000", \ - "0.2810396000, 0.2886079000, 0.3055299000, 0.3391511000, 0.4031263000, 0.5346608000, 0.8513062000", \ - "0.2926751000, 0.3002927000, 0.3172342000, 0.3508955000, 0.4147754000, 0.5461809000, 0.8628208000", \ - "0.3202512000, 0.3280394000, 0.3447027000, 0.3780773000, 0.4427515000, 0.5738788000, 0.8905723000", \ - "0.3811766000, 0.3886146000, 0.4055289000, 0.4390382000, 0.5032830000, 0.6346661000, 0.9511794000", \ - "0.5062255000, 0.5139224000, 0.5314991000, 0.5656058000, 0.6305302000, 0.7623632000, 1.0791470000", \ - "0.7271605000, 0.7360320000, 0.7557386000, 0.7945099000, 0.8663932000, 1.0060018000, 1.3281124000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.1200203000, 0.1272043000, 0.1437376000, 0.1799983000, 0.2664454000, 0.5033254000, 1.1887564000", \ - "0.1236542000, 0.1308647000, 0.1473229000, 0.1836384000, 0.2701587000, 0.5079437000, 1.1912509000", \ - "0.1327904000, 0.1399726000, 0.1564894000, 0.1927046000, 0.2793518000, 0.5172118000, 1.2003046000", \ - "0.1554545000, 0.1626052000, 0.1790775000, 0.2152847000, 0.3018913000, 0.5398037000, 1.2224044000", \ - "0.2029433000, 0.2101644000, 0.2266505000, 0.2628950000, 0.3494539000, 0.5865541000, 1.2713760000", \ - "0.2654532000, 0.2735902000, 0.2918207000, 0.3285487000, 0.4162118000, 0.6536386000, 1.3363426000", \ - "0.3190545000, 0.3298373000, 0.3526176000, 0.3959528000, 0.4845708000, 0.7224007000, 1.4043351000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0369233000, 0.0414206000, 0.0521121000, 0.0749922000, 0.1275567000, 0.2573995000, 0.6431917000", \ - "0.0369093000, 0.0414251000, 0.0521056000, 0.0749727000, 0.1273067000, 0.2574161000, 0.6431802000", \ - "0.0368398000, 0.0412461000, 0.0523646000, 0.0752948000, 0.1284381000, 0.2570530000, 0.6430427000", \ - "0.0366178000, 0.0414250000, 0.0524070000, 0.0762416000, 0.1269281000, 0.2576631000, 0.6429821000", \ - "0.0366125000, 0.0418672000, 0.0523455000, 0.0764753000, 0.1282340000, 0.2571582000, 0.6426360000", \ - "0.0393836000, 0.0442000000, 0.0548645000, 0.0775980000, 0.1281976000, 0.2580358000, 0.6445786000", \ - "0.0478958000, 0.0529644000, 0.0654736000, 0.0900233000, 0.1422921000, 0.2730871000, 0.6500703000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0274802000, 0.0331575000, 0.0472315000, 0.0850759000, 0.1947460000, 0.5265138000, 1.4987601000", \ - "0.0274230000, 0.0332359000, 0.0473524000, 0.0848293000, 0.1950869000, 0.5278781000, 1.5016293000", \ - "0.0272857000, 0.0330448000, 0.0474286000, 0.0848690000, 0.1950603000, 0.5278691000, 1.5015645000", \ - "0.0272110000, 0.0329481000, 0.0470084000, 0.0844763000, 0.1947251000, 0.5274109000, 1.5010277000", \ - "0.0284852000, 0.0341659000, 0.0479872000, 0.0853205000, 0.1948600000, 0.5274857000, 1.4986202000", \ - "0.0350664000, 0.0405902000, 0.0534495000, 0.0896318000, 0.1968995000, 0.5258008000, 1.4996440000", \ - "0.0479268000, 0.0545160000, 0.0684903000, 0.1009053000, 0.2020938000, 0.5289502000, 1.4981425000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.3199903000, 0.3282464000, 0.3463968000, 0.3818616000, 0.4479082000, 0.5824265000, 0.9014202000", \ - "0.3248255000, 0.3330976000, 0.3512257000, 0.3866941000, 0.4528421000, 0.5873867000, 0.9063181000", \ - "0.3366427000, 0.3448935000, 0.3630864000, 0.3983455000, 0.4650423000, 0.5995200000, 0.9186277000", \ - "0.3648969000, 0.3731490000, 0.3912402000, 0.4266791000, 0.4929291000, 0.6274412000, 0.9462975000", \ - "0.4246365000, 0.4328733000, 0.4510448000, 0.4862010000, 0.5530366000, 0.6873306000, 1.0065552000", \ - "0.5508552000, 0.5591153000, 0.5775567000, 0.6132906000, 0.6802586000, 0.8141550000, 1.1333509000", \ - "0.7794345000, 0.7894249000, 0.8100275000, 0.8496191000, 0.9228600000, 1.0640900000, 1.3877615000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.1278215000, 0.1350835000, 0.1515277000, 0.1877932000, 0.2741897000, 0.5106555000, 1.1957072000", \ - "0.1318586000, 0.1390671000, 0.1554959000, 0.1917622000, 0.2781791000, 0.5147399000, 1.1996517000", \ - "0.1406043000, 0.1477648000, 0.1643225000, 0.2004992000, 0.2869428000, 0.5244108000, 1.2072201000", \ - "0.1611687000, 0.1683241000, 0.1847876000, 0.2209588000, 0.3074692000, 0.5451308000, 1.2273870000", \ - "0.2043334000, 0.2116771000, 0.2284064000, 0.2646139000, 0.3510003000, 0.5878016000, 1.2727513000", \ - "0.2672967000, 0.2755448000, 0.2938524000, 0.3309851000, 0.4192313000, 0.6565898000, 1.3416046000", \ - "0.3276545000, 0.3381952000, 0.3609577000, 0.4041105000, 0.4942121000, 0.7316351000, 1.4134179000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0412291000, 0.0461228000, 0.0569244000, 0.0798020000, 0.1329451000, 0.2631919000, 0.6459716000", \ - "0.0412449000, 0.0461117000, 0.0569452000, 0.0809940000, 0.1324755000, 0.2631732000, 0.6457751000", \ - "0.0411952000, 0.0463177000, 0.0570612000, 0.0802250000, 0.1318841000, 0.2625582000, 0.6476095000", \ - "0.0412470000, 0.0461033000, 0.0569445000, 0.0809794000, 0.1325018000, 0.2630906000, 0.6459472000", \ - "0.0412027000, 0.0463166000, 0.0569807000, 0.0804142000, 0.1315690000, 0.2630061000, 0.6477777000", \ - "0.0427211000, 0.0474761000, 0.0582765000, 0.0808767000, 0.1329237000, 0.2632318000, 0.6453688000", \ - "0.0514098000, 0.0564122000, 0.0681778000, 0.0928619000, 0.1450507000, 0.2744796000, 0.6514861000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0273388000, 0.0331291000, 0.0472292000, 0.0849785000, 0.1949927000, 0.5265351000, 1.4994783000", \ - "0.0272975000, 0.0330775000, 0.0472830000, 0.0849178000, 0.1950215000, 0.5261210000, 1.5006500000", \ - "0.0275108000, 0.0331685000, 0.0473390000, 0.0847695000, 0.1950963000, 0.5279067000, 1.5015533000", \ - "0.0270502000, 0.0329516000, 0.0470454000, 0.0845667000, 0.1947383000, 0.5274168000, 1.5008293000", \ - "0.0282845000, 0.0342207000, 0.0478636000, 0.0854278000, 0.1947895000, 0.5265475000, 1.4996892000", \ - "0.0337271000, 0.0394994000, 0.0534997000, 0.0899362000, 0.1967549000, 0.5272409000, 1.5002958000", \ - "0.0453050000, 0.0520043000, 0.0667874000, 0.1003372000, 0.2012089000, 0.5277367000, 1.4975060000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.3417731000, 0.3502457000, 0.3687743000, 0.4042222000, 0.4709763000, 0.6042221000, 0.9230869000", \ - "0.3465898000, 0.3550599000, 0.3735066000, 0.4092155000, 0.4759633000, 0.6089212000, 0.9276441000", \ - "0.3590891000, 0.3675109000, 0.3859141000, 0.4215901000, 0.4883683000, 0.6214677000, 0.9409691000", \ - "0.3877171000, 0.3961845000, 0.4146107000, 0.4503364000, 0.5170396000, 0.6500692000, 0.9688552000", \ - "0.4479077000, 0.4563753000, 0.4748750000, 0.5106016000, 0.5772262000, 0.7107708000, 1.0292450000", \ - "0.5741477000, 0.5825748000, 0.6013708000, 0.6371260000, 0.7033356000, 0.8373270000, 1.1562212000", \ - "0.8082402000, 0.8178141000, 0.8385847000, 0.8782570000, 0.9506059000, 1.0908299000, 1.4134256000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.1330275000, 0.1401993000, 0.1566616000, 0.1929988000, 0.2792742000, 0.5153301000, 1.2000115000", \ - "0.1370564000, 0.1442470000, 0.1608215000, 0.1969569000, 0.2833688000, 0.5204775000, 1.2018944000", \ - "0.1450323000, 0.1522350000, 0.1686911000, 0.2049038000, 0.2912133000, 0.5276530000, 1.2109660000", \ - "0.1617076000, 0.1688972000, 0.1854100000, 0.2215365000, 0.3079562000, 0.5451427000, 1.2255762000", \ - "0.1964610000, 0.2038218000, 0.2206049000, 0.2570478000, 0.3435629000, 0.5802394000, 1.2620497000", \ - "0.2493638000, 0.2575403000, 0.2757367000, 0.3136705000, 0.4019448000, 0.6387201000, 1.3210023000", \ - "0.3020929000, 0.3122432000, 0.3344435000, 0.3774676000, 0.4685821000, 0.7061721000, 1.3874552000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0430101000, 0.0482469000, 0.0584798000, 0.0817229000, 0.1339577000, 0.2634369000, 0.6454567000", \ - "0.0432547000, 0.0477632000, 0.0586623000, 0.0825412000, 0.1324524000, 0.2634237000, 0.6467353000", \ - "0.0428910000, 0.0478205000, 0.0587468000, 0.0824336000, 0.1320923000, 0.2635166000, 0.6471524000", \ - "0.0430730000, 0.0480203000, 0.0585955000, 0.0826741000, 0.1317667000, 0.2633632000, 0.6466301000", \ - "0.0432210000, 0.0477528000, 0.0585321000, 0.0825502000, 0.1334627000, 0.2636575000, 0.6474454000", \ - "0.0439392000, 0.0485646000, 0.0590656000, 0.0815008000, 0.1330815000, 0.2627691000, 0.6478859000", \ - "0.0523642000, 0.0571872000, 0.0689861000, 0.0927731000, 0.1440265000, 0.2722582000, 0.6520181000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0274557000, 0.0331657000, 0.0475445000, 0.0850488000, 0.1948161000, 0.5272349000, 1.4983844000", \ - "0.0272047000, 0.0329320000, 0.0473110000, 0.0849086000, 0.1948387000, 0.5270949000, 1.4994993000", \ - "0.0272904000, 0.0329919000, 0.0473325000, 0.0848197000, 0.1949100000, 0.5279265000, 1.5019475000", \ - "0.0271777000, 0.0327729000, 0.0472526000, 0.0847840000, 0.1944744000, 0.5275855000, 1.4963335000", \ - "0.0285092000, 0.0343361000, 0.0481087000, 0.0855011000, 0.1950265000, 0.5276082000, 1.4998530000", \ - "0.0324355000, 0.0383556000, 0.0530137000, 0.0895715000, 0.1969335000, 0.5272472000, 1.4985632000", \ - "0.0427263000, 0.0499633000, 0.0644727000, 0.0992377000, 0.2014993000, 0.5291124000, 1.4978990000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.3143103000, 0.3228085000, 0.3413589000, 0.3769840000, 0.4439941000, 0.5771714000, 0.8961001000", \ - "0.3180564000, 0.3265064000, 0.3449531000, 0.3807278000, 0.4474736000, 0.5813753000, 0.9003303000", \ - "0.3283394000, 0.3368764000, 0.3553117000, 0.3910056000, 0.4568431000, 0.5911148000, 0.9102409000", \ - "0.3540490000, 0.3622293000, 0.3809288000, 0.4166746000, 0.4834026000, 0.6165786000, 0.9354622000", \ - "0.4150031000, 0.4235638000, 0.4420967000, 0.4775458000, 0.5442108000, 0.6782184000, 0.9969952000", \ - "0.5553947000, 0.5640599000, 0.5823095000, 0.6186084000, 0.6847962000, 0.8191492000, 1.1380957000", \ - "0.8191788000, 0.8291670000, 0.8510870000, 0.8922313000, 0.9661244000, 1.1073262000, 1.4305546000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0703856000, 0.0761756000, 0.0897063000, 0.1213088000, 0.2042687000, 0.4399700000, 1.1243679000", \ - "0.0751876000, 0.0809691000, 0.0945090000, 0.1260900000, 0.2088526000, 0.4448574000, 1.1260771000", \ - "0.0862629000, 0.0920479000, 0.1055431000, 0.1370515000, 0.2200246000, 0.4558870000, 1.1370500000", \ - "0.1111356000, 0.1169192000, 0.1303670000, 0.1617438000, 0.2447266000, 0.4806535000, 1.1650806000", \ - "0.1491070000, 0.1560871000, 0.1711635000, 0.2038622000, 0.2867759000, 0.5229717000, 1.2075323000", \ - "0.1899989000, 0.1994458000, 0.2186848000, 0.2552943000, 0.3393769000, 0.5751740000, 1.2589391000", \ - "0.2140460000, 0.2265361000, 0.2523940000, 0.2988660000, 0.3880106000, 0.6242180000, 1.3045165000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0428962000, 0.0480466000, 0.0590092000, 0.0812280000, 0.1320514000, 0.2626095000, 0.6442480000", \ - "0.0430647000, 0.0477147000, 0.0586377000, 0.0827666000, 0.1335360000, 0.2624627000, 0.6476069000", \ - "0.0427917000, 0.0480571000, 0.0587818000, 0.0812536000, 0.1346358000, 0.2633042000, 0.6439688000", \ - "0.0430649000, 0.0477124000, 0.0586107000, 0.0827604000, 0.1334786000, 0.2634864000, 0.6465835000", \ - "0.0432110000, 0.0478166000, 0.0596758000, 0.0816197000, 0.1324318000, 0.2634391000, 0.6463374000", \ - "0.0448498000, 0.0498243000, 0.0600221000, 0.0823324000, 0.1350476000, 0.2631698000, 0.6466194000", \ - "0.0568521000, 0.0621707000, 0.0739525000, 0.0974450000, 0.1494099000, 0.2746670000, 0.6493011000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0202705000, 0.0249122000, 0.0374697000, 0.0743705000, 0.1877880000, 0.5238889000, 1.4950500000", \ - "0.0202806000, 0.0249800000, 0.0375571000, 0.0741913000, 0.1877508000, 0.5232427000, 1.4980726000", \ - "0.0202521000, 0.0249144000, 0.0374733000, 0.0743915000, 0.1877905000, 0.5232578000, 1.4977833000", \ - "0.0210748000, 0.0255592000, 0.0379242000, 0.0745625000, 0.1877269000, 0.5240164000, 1.4947854000", \ - "0.0273771000, 0.0315795000, 0.0428466000, 0.0770906000, 0.1881911000, 0.5239367000, 1.4947716000", \ - "0.0389502000, 0.0438294000, 0.0547133000, 0.0845282000, 0.1903243000, 0.5209931000, 1.4984166000", \ - "0.0557454000, 0.0624364000, 0.0750167000, 0.1035170000, 0.1975922000, 0.5250417000, 1.4929979000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.2728000000, 0.2812728000, 0.2997839000, 0.3355630000, 0.4023832000, 0.5364259000, 0.8556437000", \ - "0.2757043000, 0.2841690000, 0.3026570000, 0.3383800000, 0.4052749000, 0.5393812000, 0.8585760000", \ - "0.2836882000, 0.2921931000, 0.3106633000, 0.3464749000, 0.4132935000, 0.5470000000, 0.8661230000", \ - "0.3068903000, 0.3152343000, 0.3338954000, 0.3703284000, 0.4370696000, 0.5708387000, 0.8896493000", \ - "0.3667726000, 0.3751587000, 0.3938158000, 0.4295964000, 0.4965320000, 0.6306713000, 0.9497024000", \ - "0.5093759000, 0.5177553000, 0.5366327000, 0.5723764000, 0.6387613000, 0.7729334000, 1.0920452000", \ - "0.7580062000, 0.7685339000, 0.7916721000, 0.8351592000, 0.9087919000, 1.0471761000, 1.3701916000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0659373000, 0.0719601000, 0.0860420000, 0.1183116000, 0.2010862000, 0.4363957000, 1.1201410000", \ - "0.0707696000, 0.0767920000, 0.0908662000, 0.1231124000, 0.2059743000, 0.4412063000, 1.1227211000", \ - "0.0822072000, 0.0882149000, 0.1022270000, 0.1343755000, 0.2172092000, 0.4526995000, 1.1401332000", \ - "0.1067993000, 0.1128469000, 0.1268849000, 0.1589863000, 0.2420157000, 0.4774873000, 1.1737942000", \ - "0.1428811000, 0.1503243000, 0.1662300000, 0.1998925000, 0.2833402000, 0.5195816000, 1.2130739000", \ - "0.1832872000, 0.1933426000, 0.2137476000, 0.2518179000, 0.3369156000, 0.5725364000, 1.2575653000", \ - "0.2113077000, 0.2245279000, 0.2518530000, 0.3006733000, 0.3919937000, 0.6275806000, 1.3084903000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0428918000, 0.0479460000, 0.0584303000, 0.0826736000, 0.1316637000, 0.2629781000, 0.6471743000", \ - "0.0432240000, 0.0478366000, 0.0586439000, 0.0825455000, 0.1320881000, 0.2631463000, 0.6471281000", \ - "0.0427403000, 0.0476760000, 0.0596175000, 0.0815578000, 0.1333418000, 0.2629384000, 0.6471993000", \ - "0.0430285000, 0.0476695000, 0.0584439000, 0.0821352000, 0.1333091000, 0.2635231000, 0.6474908000", \ - "0.0429369000, 0.0483087000, 0.0593103000, 0.0812846000, 0.1318659000, 0.2627865000, 0.6466306000", \ - "0.0454490000, 0.0504478000, 0.0606455000, 0.0825125000, 0.1350011000, 0.2632337000, 0.6477313000", \ - "0.0639013000, 0.0704646000, 0.0819441000, 0.1045520000, 0.1485408000, 0.2742712000, 0.6503801000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0205197000, 0.0255954000, 0.0384100000, 0.0750072000, 0.1878090000, 0.5242268000, 1.4984867000", \ - "0.0205279000, 0.0255967000, 0.0384196000, 0.0749921000, 0.1878199000, 0.5243094000, 1.4944138000", \ - "0.0205591000, 0.0256213000, 0.0384688000, 0.0750920000, 0.1878155000, 0.5243471000, 1.5071487000", \ - "0.0219292000, 0.0267686000, 0.0392140000, 0.0753621000, 0.1873855000, 0.5223665000, 1.4970689000", \ - "0.0288647000, 0.0336283000, 0.0449054000, 0.0786887000, 0.1885308000, 0.5243311000, 1.4962938000", \ - "0.0413030000, 0.0466072000, 0.0572832000, 0.0872982000, 0.1913676000, 0.5222598000, 1.4958568000", \ - "0.0598615000, 0.0667575000, 0.0801013000, 0.1091710000, 0.2001923000, 0.5240319000, 1.4898824000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311o_4") { - leakage_power () { - value : 0.0060209000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0417042000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025761000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0060209000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0417080000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025766000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0060208000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0059077000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025761000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0060166000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0065861000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025765000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0060211000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0105316000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0255587000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0375639000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0060208000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0064212000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025765000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0060180000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0064781000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0025765000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047136000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0026338000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0052185000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0024666000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0026328000; - when : "A1&A2&A3&B1&!C1"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__a311o"; - cell_leakage_power : 0.0087903070; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091384000, 0.0091362000, 0.0091312000, 0.0091300000, 0.0091274000, 0.0091214000, 0.0091076000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006394200, -0.006405500, -0.006431700, -0.006414300, -0.006374100, -0.006281500, -0.006067800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043790000; - } - pin ("A2") { - capacitance : 0.0043190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084646000, 0.0084635000, 0.0084610000, 0.0084956000, 0.0085753000, 0.0087590000, 0.0091824000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007905500, -0.007903400, -0.007898500, -0.007897000, -0.007893500, -0.007885300, -0.007866300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044890000; - } - pin ("A3") { - capacitance : 0.0043800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080498000, 0.0080521000, 0.0080572000, 0.0080556000, 0.0080518000, 0.0080431000, 0.0080228000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008061500, -0.008055600, -0.008042000, -0.008042600, -0.008043900, -0.008046600, -0.008052900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046490000; - } - pin ("B1") { - capacitance : 0.0042840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082708000, 0.0082705000, 0.0082699000, 0.0082745000, 0.0082853000, 0.0083101000, 0.0083674000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007010200, -0.007139100, -0.007436300, -0.007446800, -0.007471000, -0.007526800, -0.007655400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046400000; - } - pin ("C1") { - capacitance : 0.0042640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0038830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038856000, 0.0038840000, 0.0038803000, 0.0038974000, 0.0039367000, 0.0040273000, 0.0042362000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003527700, -0.003532300, -0.003543100, -0.003543400, -0.003544100, -0.003545800, -0.003549500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046460000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1) | (C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0310501000, 0.0292719000, 0.0245031000, 0.0111181000, -0.034629400, -0.190548500, -0.687842800", \ - "0.0309355000, 0.0291440000, 0.0245147000, 0.0111607000, -0.034619100, -0.190721400, -0.687980800", \ - "0.0307652000, 0.0289536000, 0.0240944000, 0.0106300000, -0.035104100, -0.190959000, -0.688221000", \ - "0.0301783000, 0.0283374000, 0.0235510000, 0.0099842000, -0.035629200, -0.191627100, -0.688894000", \ - "0.0295612000, 0.0277488000, 0.0228717000, 0.0095347000, -0.036195300, -0.192220500, -0.689405900", \ - "0.0296718000, 0.0279119000, 0.0229971000, 0.0092859000, -0.036556000, -0.192450900, -0.689585800", \ - "0.0403084000, 0.0383346000, 0.0326780000, 0.0160407000, -0.034690100, -0.192686100, -0.689560000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0350424000, 0.0367947000, 0.0423464000, 0.0596786000, 0.1113796000, 0.2703263000, 0.7632977000", \ - "0.0348153000, 0.0366062000, 0.0422045000, 0.0593336000, 0.1111378000, 0.2700677000, 0.7630831000", \ - "0.0345397000, 0.0362955000, 0.0419338000, 0.0591095000, 0.1109540000, 0.2698710000, 0.7628511000", \ - "0.0341784000, 0.0359352000, 0.0415466000, 0.0589169000, 0.1108961000, 0.2697209000, 0.7622484000", \ - "0.0343973000, 0.0361477000, 0.0416698000, 0.0589119000, 0.1101782000, 0.2693852000, 0.7621567000", \ - "0.0362576000, 0.0379231000, 0.0430992000, 0.0592390000, 0.1102464000, 0.2690681000, 0.7619869000", \ - "0.0387399000, 0.0403755000, 0.0454986000, 0.0618726000, 0.1127697000, 0.2700062000, 0.7614079000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0377182000, 0.0359456000, 0.0308648000, 0.0173854000, -0.028266300, -0.184039900, -0.681290500", \ - "0.0374229000, 0.0356921000, 0.0307008000, 0.0171183000, -0.028598700, -0.184316100, -0.681522400", \ - "0.0372033000, 0.0353617000, 0.0304739000, 0.0170575000, -0.028806100, -0.184669400, -0.681803300", \ - "0.0368599000, 0.0349855000, 0.0298592000, 0.0163572000, -0.029385500, -0.185231700, -0.682308200", \ - "0.0360211000, 0.0342168000, 0.0291803000, 0.0157011000, -0.030130000, -0.185869100, -0.682986000", \ - "0.0359186000, 0.0339973000, 0.0291507000, 0.0153642000, -0.030466100, -0.186332200, -0.683284300", \ - "0.0451937000, 0.0432175000, 0.0373976000, 0.0205994000, -0.030452800, -0.186785700, -0.683680300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0369203000, 0.0386972000, 0.0442954000, 0.0614624000, 0.1133119000, 0.2716495000, 0.7636608000", \ - "0.0366748000, 0.0384022000, 0.0440569000, 0.0613266000, 0.1129816000, 0.2714428000, 0.7639090000", \ - "0.0364654000, 0.0382270000, 0.0438394000, 0.0610147000, 0.1128828000, 0.2711836000, 0.7632767000", \ - "0.0360329000, 0.0378422000, 0.0434460000, 0.0607268000, 0.1124953000, 0.2709262000, 0.7633669000", \ - "0.0361954000, 0.0379284000, 0.0434253000, 0.0607357000, 0.1122935000, 0.2710894000, 0.7633643000", \ - "0.0375036000, 0.0391749000, 0.0444082000, 0.0606998000, 0.1123359000, 0.2705387000, 0.7635033000", \ - "0.0390964000, 0.0407134000, 0.0458716000, 0.0622316000, 0.1133487000, 0.2716044000, 0.7615054000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0426546000, 0.0408458000, 0.0356659000, 0.0220717000, -0.023686400, -0.180330000, -0.677836800", \ - "0.0426924000, 0.0408010000, 0.0356994000, 0.0220087000, -0.024018300, -0.180550400, -0.678120500", \ - "0.0424701000, 0.0406289000, 0.0355690000, 0.0218322000, -0.024280800, -0.180785100, -0.678344100", \ - "0.0418474000, 0.0400939000, 0.0350046000, 0.0213486000, -0.024727500, -0.181021100, -0.678512000", \ - "0.0414762000, 0.0396521000, 0.0346772000, 0.0209553000, -0.025075200, -0.181478800, -0.678955500", \ - "0.0417390000, 0.0399320000, 0.0348375000, 0.0210984000, -0.025188800, -0.181501400, -0.678938200", \ - "0.0509129000, 0.0489534000, 0.0430795000, 0.0260261000, -0.025853000, -0.181135400, -0.678489500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0370211000, 0.0387647000, 0.0443571000, 0.0617459000, 0.1132784000, 0.2713097000, 0.7634021000", \ - "0.0369049000, 0.0386844000, 0.0442662000, 0.0614560000, 0.1131463000, 0.2712242000, 0.7631964000", \ - "0.0366360000, 0.0383954000, 0.0440089000, 0.0611883000, 0.1128860000, 0.2710064000, 0.7629875000", \ - "0.0361994000, 0.0379594000, 0.0435909000, 0.0609419000, 0.1126333000, 0.2708179000, 0.7628508000", \ - "0.0361686000, 0.0379094000, 0.0434723000, 0.0605536000, 0.1123738000, 0.2708451000, 0.7625013000", \ - "0.0373499000, 0.0390505000, 0.0443406000, 0.0606206000, 0.1122370000, 0.2703218000, 0.7629825000", \ - "0.0386961000, 0.0403377000, 0.0456526000, 0.0622206000, 0.1133722000, 0.2711308000, 0.7620157000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0375941000, 0.0357519000, 0.0305896000, 0.0169273000, -0.029021900, -0.185096900, -0.682221300", \ - "0.0371953000, 0.0354050000, 0.0302833000, 0.0166567000, -0.029367100, -0.185283000, -0.682423600", \ - "0.0369315000, 0.0351483000, 0.0300196000, 0.0163525000, -0.029578700, -0.185635700, -0.682750400", \ - "0.0365509000, 0.0347146000, 0.0296147000, 0.0159527000, -0.029752900, -0.186018900, -0.683103000", \ - "0.0361983000, 0.0343865000, 0.0292510000, 0.0156730000, -0.030389200, -0.186367600, -0.683584500", \ - "0.0363302000, 0.0345360000, 0.0292838000, 0.0155744000, -0.030226700, -0.186296800, -0.683518000", \ - "0.0467227000, 0.0446811000, 0.0387219000, 0.0214573000, -0.030501300, -0.186147100, -0.683164000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0324879000, 0.0343529000, 0.0401202000, 0.0571552000, 0.1083863000, 0.2667872000, 0.7589170000", \ - "0.0325384000, 0.0344216000, 0.0401711000, 0.0572410000, 0.1084779000, 0.2669281000, 0.7594519000", \ - "0.0326778000, 0.0345545000, 0.0403120000, 0.0573698000, 0.1086787000, 0.2672147000, 0.7591482000", \ - "0.0323424000, 0.0341784000, 0.0398707000, 0.0569181000, 0.1082461000, 0.2669582000, 0.7594321000", \ - "0.0322552000, 0.0340125000, 0.0395996000, 0.0565860000, 0.1079801000, 0.2667614000, 0.7587623000", \ - "0.0336051000, 0.0353226000, 0.0406535000, 0.0571920000, 0.1080999000, 0.2660179000, 0.7591450000", \ - "0.0364006000, 0.0379881000, 0.0431330000, 0.0596334000, 0.1107857000, 0.2688059000, 0.7586041000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0369897000, 0.0350425000, 0.0298622000, 0.0163066000, -0.029504800, -0.185313100, -0.682213700", \ - "0.0366090000, 0.0347949000, 0.0298954000, 0.0162429000, -0.029719100, -0.185559500, -0.682417700", \ - "0.0363631000, 0.0345031000, 0.0293894000, 0.0157598000, -0.030169400, -0.185852200, -0.682618500", \ - "0.0360140000, 0.0341903000, 0.0290728000, 0.0154296000, -0.030535900, -0.186228700, -0.683062000", \ - "0.0357330000, 0.0338829000, 0.0289143000, 0.0151872000, -0.030626100, -0.186265700, -0.683220800", \ - "0.0370693000, 0.0352785000, 0.0300472000, 0.0157498000, -0.030261700, -0.186152200, -0.682905400", \ - "0.0510035000, 0.0488697000, 0.0426873000, 0.0241511000, -0.027905900, -0.183705900, -0.680852700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388480, 0.0150531700, 0.0468289000, 0.1456800000, 0.4531959000"); - values("0.0246636000, 0.0265989000, 0.0325954000, 0.0502883000, 0.1023148000, 0.2612713000, 0.7558071000", \ - "0.0247141000, 0.0266450000, 0.0326279000, 0.0502901000, 0.1023558000, 0.2613238000, 0.7507471000", \ - "0.0245871000, 0.0265341000, 0.0324401000, 0.0499526000, 0.1020819000, 0.2610402000, 0.7508923000", \ - "0.0243754000, 0.0262194000, 0.0319861000, 0.0491775000, 0.1012251000, 0.2607926000, 0.7522682000", \ - "0.0242693000, 0.0259854000, 0.0315355000, 0.0486305000, 0.1005137000, 0.2600658000, 0.7550933000", \ - "0.0254458000, 0.0271200000, 0.0325095000, 0.0492667000, 0.1003560000, 0.2589868000, 0.7533019000", \ - "0.0285365000, 0.0300862000, 0.0351886000, 0.0517017000, 0.1029004000, 0.2611139000, 0.7522716000"); - } - } - max_capacitance : 0.4531960000; - max_transition : 1.5010910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.2778678000, 0.2828052000, 0.2954121000, 0.3231684000, 0.3791983000, 0.4970880000, 0.7848061000", \ - "0.2832090000, 0.2881830000, 0.3006897000, 0.3284021000, 0.3847730000, 0.5023995000, 0.7900204000", \ - "0.2949339000, 0.2998582000, 0.3124067000, 0.3401316000, 0.3965549000, 0.5139627000, 0.8018274000", \ - "0.3201525000, 0.3250569000, 0.3375469000, 0.3652578000, 0.4212979000, 0.5392039000, 0.8265713000", \ - "0.3731729000, 0.3781076000, 0.3906434000, 0.4182178000, 0.4744162000, 0.5922830000, 0.8799688000", \ - "0.4784617000, 0.4835679000, 0.4966971000, 0.5250659000, 0.5820188000, 0.7010758000, 0.9891117000", \ - "0.6594487000, 0.6649455000, 0.6790404000, 0.7107646000, 0.7730866000, 0.8998565000, 1.1943524000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.1364019000, 0.1419037000, 0.1561248000, 0.1898778000, 0.2712710000, 0.4998281000, 1.1955279000", \ - "0.1398313000, 0.1453713000, 0.1596458000, 0.1933125000, 0.2749753000, 0.5031349000, 1.1984215000", \ - "0.1490601000, 0.1545876000, 0.1689008000, 0.2025859000, 0.2842182000, 0.5125953000, 1.2070624000", \ - "0.1716416000, 0.1771672000, 0.1915084000, 0.2251219000, 0.3067493000, 0.5348165000, 1.2337350000", \ - "0.2215443000, 0.2270397000, 0.2412346000, 0.2747126000, 0.3559268000, 0.5839987000, 1.2798159000", \ - "0.2933102000, 0.2992313000, 0.3140351000, 0.3481678000, 0.4294372000, 0.6579418000, 1.3531951000", \ - "0.3676275000, 0.3751200000, 0.3930187000, 0.4316536000, 0.5150854000, 0.7422346000, 1.4380795000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0367224000, 0.0397694000, 0.0477614000, 0.0663971000, 0.1094277000, 0.2221983000, 0.5643000000", \ - "0.0367073000, 0.0395005000, 0.0474267000, 0.0660604000, 0.1089396000, 0.2230593000, 0.5652360000", \ - "0.0364494000, 0.0394567000, 0.0474804000, 0.0659583000, 0.1103235000, 0.2225767000, 0.5645268000", \ - "0.0368145000, 0.0398985000, 0.0477750000, 0.0664801000, 0.1099211000, 0.2226038000, 0.5640364000", \ - "0.0364877000, 0.0395197000, 0.0474146000, 0.0667879000, 0.1093625000, 0.2229876000, 0.5646565000", \ - "0.0390887000, 0.0421955000, 0.0508012000, 0.0687107000, 0.1123951000, 0.2243724000, 0.5656360000", \ - "0.0464559000, 0.0498032000, 0.0580701000, 0.0783339000, 0.1253354000, 0.2369592000, 0.5709354000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0318030000, 0.0361165000, 0.0482145000, 0.0814675000, 0.1799941000, 0.4975771000, 1.4992884000", \ - "0.0319084000, 0.0363466000, 0.0485563000, 0.0813798000, 0.1801507000, 0.4968180000, 1.5004913000", \ - "0.0318756000, 0.0363293000, 0.0484837000, 0.0814155000, 0.1799391000, 0.4973333000, 1.5007442000", \ - "0.0314804000, 0.0359420000, 0.0481436000, 0.0811870000, 0.1793835000, 0.4970532000, 1.4993827000", \ - "0.0316274000, 0.0360259000, 0.0481436000, 0.0809998000, 0.1797241000, 0.4968556000, 1.4992982000", \ - "0.0366523000, 0.0409374000, 0.0525803000, 0.0841044000, 0.1818822000, 0.4975688000, 1.5001812000", \ - "0.0487243000, 0.0536259000, 0.0650555000, 0.0943111000, 0.1857656000, 0.4992413000, 1.4988233000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.3311768000, 0.3366173000, 0.3503051000, 0.3799208000, 0.4377138000, 0.5584587000, 0.8485435000", \ - "0.3355914000, 0.3410863000, 0.3548270000, 0.3842685000, 0.4429263000, 0.5626948000, 0.8526631000", \ - "0.3473939000, 0.3528185000, 0.3665331000, 0.3958674000, 0.4545853000, 0.5745239000, 0.8645856000", \ - "0.3746331000, 0.3800939000, 0.3937643000, 0.4232866000, 0.4818043000, 0.6016755000, 0.8918069000", \ - "0.4323948000, 0.4378542000, 0.4515541000, 0.4808352000, 0.5393986000, 0.6597942000, 0.9500339000", \ - "0.5530203000, 0.5588155000, 0.5727146000, 0.6024871000, 0.6610794000, 0.7815733000, 1.0715995000", \ - "0.7742124000, 0.7802616000, 0.7951420000, 0.8282988000, 0.8917374000, 1.0192491000, 1.3145256000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.1478868000, 0.1534407000, 0.1677087000, 0.2012949000, 0.2828481000, 0.5100245000, 1.2078633000", \ - "0.1520377000, 0.1575378000, 0.1718031000, 0.2055043000, 0.2867963000, 0.5147004000, 1.2095548000", \ - "0.1610481000, 0.1665865000, 0.1808857000, 0.2144486000, 0.2959806000, 0.5235798000, 1.2216133000", \ - "0.1817633000, 0.1873021000, 0.2016149000, 0.2352246000, 0.3166858000, 0.5443564000, 1.2394237000", \ - "0.2277024000, 0.2332023000, 0.2474620000, 0.2810647000, 0.3624562000, 0.5893172000, 1.2872831000", \ - "0.2994887000, 0.3054892000, 0.3207067000, 0.3556796000, 0.4382189000, 0.6663555000, 1.3623074000", \ - "0.3790893000, 0.3865793000, 0.4048724000, 0.4440829000, 0.5294801000, 0.7577721000, 1.4534507000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0415887000, 0.0447958000, 0.0532834000, 0.0719727000, 0.1156586000, 0.2277964000, 0.5673527000", \ - "0.0417976000, 0.0447518000, 0.0529935000, 0.0711257000, 0.1141509000, 0.2275196000, 0.5683791000", \ - "0.0413844000, 0.0446625000, 0.0528199000, 0.0713844000, 0.1137451000, 0.2275839000, 0.5683304000", \ - "0.0413509000, 0.0445291000, 0.0528345000, 0.0722339000, 0.1143044000, 0.2278609000, 0.5671961000", \ - "0.0415470000, 0.0446995000, 0.0531537000, 0.0717518000, 0.1139583000, 0.2273125000, 0.5671987000", \ - "0.0428356000, 0.0463912000, 0.0540899000, 0.0721333000, 0.1150875000, 0.2279999000, 0.5686878000", \ - "0.0504207000, 0.0536337000, 0.0624648000, 0.0820626000, 0.1265000000, 0.2390694000, 0.5738177000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0318379000, 0.0362607000, 0.0484301000, 0.0814172000, 0.1796894000, 0.4974401000, 1.5009330000", \ - "0.0317873000, 0.0361367000, 0.0483510000, 0.0814615000, 0.1799864000, 0.4975951000, 1.4997712000", \ - "0.0317321000, 0.0361799000, 0.0483178000, 0.0814791000, 0.1796908000, 0.4967302000, 1.4991547000", \ - "0.0315217000, 0.0360605000, 0.0483333000, 0.0811315000, 0.1798422000, 0.4966997000, 1.5001205000", \ - "0.0322678000, 0.0366684000, 0.0487524000, 0.0813451000, 0.1797609000, 0.4965857000, 1.4999690000", \ - "0.0363912000, 0.0406058000, 0.0531076000, 0.0847833000, 0.1818155000, 0.4968940000, 1.4964463000", \ - "0.0470682000, 0.0518232000, 0.0644857000, 0.0954078000, 0.1866015000, 0.4987577000, 1.4976447000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.3601981000, 0.3659040000, 0.3801831000, 0.4106371000, 0.4696777000, 0.5906892000, 0.8819830000", \ - "0.3648958000, 0.3705746000, 0.3848596000, 0.4153037000, 0.4748176000, 0.5958153000, 0.8865112000", \ - "0.3775835000, 0.3830572000, 0.3975001000, 0.4279601000, 0.4874096000, 0.6084518000, 0.8991266000", \ - "0.4061784000, 0.4120199000, 0.4262280000, 0.4567531000, 0.5162114000, 0.6370505000, 0.9285490000", \ - "0.4653683000, 0.4710644000, 0.4854858000, 0.5158687000, 0.5748843000, 0.6963876000, 0.9875172000", \ - "0.5894232000, 0.5950939000, 0.6093360000, 0.6398183000, 0.6994850000, 0.8211402000, 1.1123150000", \ - "0.8196077000, 0.8259760000, 0.8416938000, 0.8751501000, 0.9394242000, 1.0664782000, 1.3623582000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.1526935000, 0.1582436000, 0.1725885000, 0.2063351000, 0.2876758000, 0.5148817000, 1.2084906000", \ - "0.1567254000, 0.1622472000, 0.1765888000, 0.2101689000, 0.2915536000, 0.5188499000, 1.2132575000", \ - "0.1641622000, 0.1696983000, 0.1840062000, 0.2175890000, 0.2989766000, 0.5263237000, 1.2208132000", \ - "0.1791965000, 0.1847096000, 0.1990449000, 0.2327428000, 0.3139473000, 0.5414081000, 1.2362361000", \ - "0.2107313000, 0.2163325000, 0.2307316000, 0.2644488000, 0.3458989000, 0.5730090000, 1.2708834000", \ - "0.2618155000, 0.2678087000, 0.2830705000, 0.3182405000, 0.4011572000, 0.6285782000, 1.3245690000", \ - "0.3194975000, 0.3264969000, 0.3440868000, 0.3829970000, 0.4688382000, 0.6969165000, 1.3919844000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0446828000, 0.0479952000, 0.0559495000, 0.0744692000, 0.1185850000, 0.2306774000, 0.5701944000", \ - "0.0444682000, 0.0483946000, 0.0559726000, 0.0744476000, 0.1171526000, 0.2308436000, 0.5710720000", \ - "0.0445508000, 0.0481438000, 0.0560675000, 0.0743174000, 0.1167191000, 0.2310808000, 0.5707314000", \ - "0.0447359000, 0.0477953000, 0.0567721000, 0.0749058000, 0.1184004000, 0.2304924000, 0.5701860000", \ - "0.0449887000, 0.0483931000, 0.0564675000, 0.0743188000, 0.1182378000, 0.2303998000, 0.5701755000", \ - "0.0455161000, 0.0485993000, 0.0568668000, 0.0751824000, 0.1173267000, 0.2304981000, 0.5710326000", \ - "0.0527541000, 0.0567156000, 0.0650593000, 0.0840548000, 0.1271925000, 0.2405253000, 0.5753205000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0317456000, 0.0360578000, 0.0483990000, 0.0814057000, 0.1799199000, 0.4974148000, 1.5005795000", \ - "0.0317291000, 0.0360931000, 0.0482989000, 0.0815165000, 0.1799469000, 0.4976148000, 1.4992819000", \ - "0.0317028000, 0.0361532000, 0.0483316000, 0.0815020000, 0.1799395000, 0.4975997000, 1.4991043000", \ - "0.0318190000, 0.0362482000, 0.0481585000, 0.0811960000, 0.1799344000, 0.4970313000, 1.4982142000", \ - "0.0325115000, 0.0368082000, 0.0486068000, 0.0814136000, 0.1796703000, 0.4973948000, 1.5010911000", \ - "0.0350612000, 0.0396659000, 0.0522184000, 0.0846545000, 0.1816986000, 0.4970591000, 1.4981428000", \ - "0.0439093000, 0.0488287000, 0.0614043000, 0.0932343000, 0.1865874000, 0.4977963000, 1.4981811000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.3349499000, 0.3406934000, 0.3550026000, 0.3855996000, 0.4450484000, 0.5659802000, 0.8575373000", \ - "0.3380933000, 0.3438151000, 0.3581435000, 0.3886433000, 0.4484001000, 0.5693251000, 0.8609367000", \ - "0.3480177000, 0.3537328000, 0.3680249000, 0.3986192000, 0.4580862000, 0.5790263000, 0.8706119000", \ - "0.3726306000, 0.3783459000, 0.3927211000, 0.4231038000, 0.4822469000, 0.6040052000, 0.8952225000", \ - "0.4290871000, 0.4347898000, 0.4488890000, 0.4792733000, 0.5388779000, 0.6606413000, 0.9520436000", \ - "0.5599724000, 0.5657924000, 0.5802732000, 0.6109070000, 0.6698718000, 0.7916987000, 1.0832569000", \ - "0.7997380000, 0.8063062000, 0.8229590000, 0.8585435000, 0.9247370000, 1.0542209000, 1.3513667000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0680973000, 0.0723924000, 0.0840190000, 0.1124524000, 0.1865611000, 0.4095546000, 1.1038802000", \ - "0.0726438000, 0.0769502000, 0.0885971000, 0.1170736000, 0.1911486000, 0.4141001000, 1.1055803000", \ - "0.0837331000, 0.0880333000, 0.0996531000, 0.1280860000, 0.2024595000, 0.4254972000, 1.1191449000", \ - "0.1077088000, 0.1119998000, 0.1235624000, 0.1520455000, 0.2264152000, 0.4494088000, 1.1415314000", \ - "0.1423087000, 0.1472450000, 0.1600081000, 0.1896896000, 0.2647957000, 0.4882991000, 1.1820676000", \ - "0.1801726000, 0.1867375000, 0.2027597000, 0.2360696000, 0.3129748000, 0.5362762000, 1.2284014000", \ - "0.1984458000, 0.2073155000, 0.2290884000, 0.2714993000, 0.3546726000, 0.5787135000, 1.2688590000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0444891000, 0.0479967000, 0.0558214000, 0.0753921000, 0.1186456000, 0.2302415000, 0.5703039000", \ - "0.0448195000, 0.0481785000, 0.0567118000, 0.0743738000, 0.1174436000, 0.2302469000, 0.5706025000", \ - "0.0448489000, 0.0476759000, 0.0558445000, 0.0753293000, 0.1186550000, 0.2303001000, 0.5703066000", \ - "0.0447594000, 0.0481287000, 0.0563334000, 0.0743544000, 0.1187197000, 0.2307574000, 0.5707523000", \ - "0.0445971000, 0.0480106000, 0.0562660000, 0.0749690000, 0.1176378000, 0.2301284000, 0.5710369000", \ - "0.0466488000, 0.0496099000, 0.0577676000, 0.0754933000, 0.1197156000, 0.2312510000, 0.5704657000", \ - "0.0581373000, 0.0623748000, 0.0707162000, 0.0898506000, 0.1319936000, 0.2423625000, 0.5761654000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0216596000, 0.0258261000, 0.0373849000, 0.0689324000, 0.1681476000, 0.4888130000, 1.4907620000", \ - "0.0216289000, 0.0258603000, 0.0373863000, 0.0688760000, 0.1681751000, 0.4891473000, 1.4888978000", \ - "0.0216291000, 0.0257901000, 0.0373552000, 0.0690308000, 0.1678543000, 0.4882575000, 1.4921357000", \ - "0.0224191000, 0.0265259000, 0.0378408000, 0.0692111000, 0.1680404000, 0.4891947000, 1.4868370000", \ - "0.0276761000, 0.0316250000, 0.0421490000, 0.0718989000, 0.1690877000, 0.4883638000, 1.4920707000", \ - "0.0388465000, 0.0431106000, 0.0533457000, 0.0795753000, 0.1719862000, 0.4874331000, 1.4897398000", \ - "0.0566702000, 0.0620908000, 0.0739389000, 0.0984933000, 0.1808004000, 0.4908051000, 1.4847061000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.2789421000, 0.2847884000, 0.2991080000, 0.3296515000, 0.3887216000, 0.5107076000, 0.8024962000", \ - "0.2818326000, 0.2875808000, 0.3019597000, 0.3324923000, 0.3921112000, 0.5137641000, 0.8058321000", \ - "0.2904347000, 0.2961531000, 0.3104461000, 0.3408303000, 0.4007508000, 0.5221160000, 0.8139437000", \ - "0.3133536000, 0.3190859000, 0.3333808000, 0.3638676000, 0.4234193000, 0.5451581000, 0.8370060000", \ - "0.3748724000, 0.3805656000, 0.3950152000, 0.4252881000, 0.4849720000, 0.6069543000, 0.8985211000", \ - "0.5213301000, 0.5270840000, 0.5413857000, 0.5707299000, 0.6300791000, 0.7517540000, 1.0436341000", \ - "0.7805023000, 0.7874732000, 0.8053270000, 0.8418961000, 0.9081967000, 1.0324250000, 1.3278024000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0622151000, 0.0665977000, 0.0785290000, 0.1077384000, 0.1829118000, 0.4065612000, 1.1034303000", \ - "0.0670242000, 0.0714022000, 0.0833256000, 0.1125201000, 0.1877163000, 0.4110714000, 1.1026283000", \ - "0.0783201000, 0.0826656000, 0.0944857000, 0.1235315000, 0.1988520000, 0.4232810000, 1.1153561000", \ - "0.1009000000, 0.1052854000, 0.1170864000, 0.1461883000, 0.2214767000, 0.4460100000, 1.1480082000", \ - "0.1327299000, 0.1378638000, 0.1510337000, 0.1812863000, 0.2571753000, 0.4816585000, 1.1794750000", \ - "0.1658825000, 0.1728409000, 0.1898763000, 0.2243333000, 0.3023312000, 0.5267035000, 1.2205740000", \ - "0.1809064000, 0.1901602000, 0.2129386000, 0.2573925000, 0.3423693000, 0.5669337000, 1.2583190000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0447950000, 0.0479613000, 0.0559232000, 0.0743240000, 0.1185921000, 0.2301042000, 0.5708226000", \ - "0.0447240000, 0.0479789000, 0.0560935000, 0.0744123000, 0.1165913000, 0.2302400000, 0.5693320000", \ - "0.0448039000, 0.0480887000, 0.0564002000, 0.0743873000, 0.1168396000, 0.2300801000, 0.5703121000", \ - "0.0447841000, 0.0479638000, 0.0567227000, 0.0748400000, 0.1176059000, 0.2298668000, 0.5699801000", \ - "0.0450251000, 0.0483544000, 0.0565778000, 0.0742788000, 0.1185318000, 0.2294995000, 0.5703472000", \ - "0.0459717000, 0.0491887000, 0.0568653000, 0.0746221000, 0.1170939000, 0.2301845000, 0.5694635000", \ - "0.0648421000, 0.0687097000, 0.0777291000, 0.0967548000, 0.1327699000, 0.2400841000, 0.5763062000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015554500, 0.0048388500, 0.0150532000, 0.0468289000, 0.1456800000, 0.4531960000"); - values("0.0211803000, 0.0253667000, 0.0368382000, 0.0682955000, 0.1673830000, 0.4884279000, 1.4970017000", \ - "0.0212011000, 0.0254033000, 0.0368812000, 0.0683059000, 0.1676984000, 0.4894066000, 1.4918358000", \ - "0.0212562000, 0.0254209000, 0.0369521000, 0.0683925000, 0.1678259000, 0.4890781000, 1.4912631000", \ - "0.0227226000, 0.0267149000, 0.0379046000, 0.0688874000, 0.1674693000, 0.4889734000, 1.4944698000", \ - "0.0288340000, 0.0326316000, 0.0430293000, 0.0722909000, 0.1689493000, 0.4881047000, 1.4955892000", \ - "0.0415765000, 0.0458461000, 0.0561127000, 0.0813930000, 0.1726997000, 0.4877873000, 1.4925480000", \ - "0.0605377000, 0.0661096000, 0.0783569000, 0.1030045000, 0.1831129000, 0.4901877000, 1.4865832000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311oi_1") { - leakage_power () { - value : 0.0023704000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0008307000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257337e-05; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0008524000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257337e-05; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0008433000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257337e-05; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0013056000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257337e-05; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0008478000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257351e-05; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0011731000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257351e-05; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0023704000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0010700000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 6.9257337e-05; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005870000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0002654000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0023770000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 5.7723391e-05; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0002046000; - when : "A1&A2&A3&B1&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a311oi"; - cell_leakage_power : 0.0009691861; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045843000, 0.0045840000, 0.0045832000, 0.0045831000, 0.0045829000, 0.0045824000, 0.0045812000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003645700, -0.003650200, -0.003660600, -0.003653900, -0.003638500, -0.003602900, -0.003520800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024420000; - } - pin ("A2") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043828000, 0.0043799000, 0.0043731000, 0.0043894000, 0.0044268000, 0.0045130000, 0.0047118000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003903700, -0.003905600, -0.003909900, -0.003908800, -0.003906200, -0.003900100, -0.003886200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024220000; - } - pin ("A3") { - capacitance : 0.0023110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040321000, 0.0040295000, 0.0040234000, 0.0040239000, 0.0040250000, 0.0040276000, 0.0040334000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004009100, -0.004010500, -0.004013900, -0.004013800, -0.004013700, -0.004013500, -0.004013000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024160000; - } - pin ("B1") { - capacitance : 0.0023310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039251000, 0.0039269000, 0.0039309000, 0.0039331000, 0.0039383000, 0.0039501000, 0.0039772000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003522800, -0.003601600, -0.003783100, -0.003787700, -0.003798200, -0.003822700, -0.003879000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024830000; - } - pin ("C1") { - capacitance : 0.0022830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026922000, 0.0026856000, 0.0026704000, 0.0026770000, 0.0026922000, 0.0027273000, 0.0028083000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001729500, -0.001729600, -0.001729900, -0.001730100, -0.001730400, -0.001731100, -0.001732800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024650000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1) | (!A3&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0064142000, 0.0055211000, 0.0036454000, -0.000302000, -0.008631900, -0.026237200, -0.063515900", \ - "0.0063103000, 0.0054195000, 0.0035424000, -0.000411300, -0.008729700, -0.026335800, -0.063613400", \ - "0.0061384000, 0.0052562000, 0.0033946000, -0.000550400, -0.008847700, -0.026457600, -0.063739800", \ - "0.0059487000, 0.0050680000, 0.0032182000, -0.000699600, -0.009028700, -0.026592600, -0.063837500", \ - "0.0057415000, 0.0048667000, 0.0030617000, -0.000871800, -0.009152200, -0.026696300, -0.063967100", \ - "0.0060391000, 0.0051320000, 0.0032008000, -0.000842100, -0.009230500, -0.026741300, -0.063997900", \ - "0.0070855000, 0.0061329000, 0.0041424000, 0.0001571000, -0.008346100, -0.026307300, -0.063834300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0114897000, 0.0124170000, 0.0143845000, 0.0183902000, 0.0267601000, 0.0443643000, 0.0813639000", \ - "0.0112587000, 0.0122418000, 0.0141955000, 0.0183177000, 0.0268536000, 0.0443253000, 0.0813047000", \ - "0.0110107000, 0.0119555000, 0.0139189000, 0.0180943000, 0.0265267000, 0.0442095000, 0.0816126000", \ - "0.0107912000, 0.0117228000, 0.0136708000, 0.0177588000, 0.0262320000, 0.0439814000, 0.0815049000", \ - "0.0106319000, 0.0115500000, 0.0134679000, 0.0175044000, 0.0259840000, 0.0436453000, 0.0814909000", \ - "0.0106350000, 0.0115362000, 0.0134575000, 0.0174133000, 0.0257723000, 0.0435613000, 0.0805844000", \ - "0.0103695000, 0.0112482000, 0.0131573000, 0.0173635000, 0.0259245000, 0.0434043000, 0.0807371000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0066020000, 0.0057088000, 0.0038275000, -0.000128700, -0.008444600, -0.026052900, -0.063332600", \ - "0.0064895000, 0.0056024000, 0.0037257000, -0.000229000, -0.008547900, -0.026159000, -0.063430500", \ - "0.0063615000, 0.0054660000, 0.0035880000, -0.000357800, -0.008668700, -0.026273400, -0.063554600", \ - "0.0062327000, 0.0053499000, 0.0034706000, -0.000460900, -0.008778300, -0.026373100, -0.063656700", \ - "0.0061024000, 0.0052240000, 0.0033794000, -0.000521300, -0.008802000, -0.026383300, -0.063673200", \ - "0.0062369000, 0.0053873000, 0.0034770000, -0.000554500, -0.008933500, -0.026513600, -0.063760900", \ - "0.0069516000, 0.0060309000, 0.0041021000, 5.380000e-05, -0.008425600, -0.026278200, -0.063690600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0143923000, 0.0152915000, 0.0172000000, 0.0211754000, 0.0294921000, 0.0470469000, 0.0840504000", \ - "0.0142285000, 0.0151447000, 0.0170551000, 0.0210799000, 0.0294425000, 0.0469973000, 0.0840415000", \ - "0.0140102000, 0.0149331000, 0.0168568000, 0.0209094000, 0.0293324000, 0.0469418000, 0.0840003000", \ - "0.0138085000, 0.0147092000, 0.0166377000, 0.0206708000, 0.0290972000, 0.0467686000, 0.0838795000", \ - "0.0136258000, 0.0145192000, 0.0164272000, 0.0204196000, 0.0288364000, 0.0464910000, 0.0836027000", \ - "0.0135324000, 0.0144226000, 0.0163061000, 0.0202861000, 0.0286905000, 0.0462721000, 0.0833432000", \ - "0.0130322000, 0.0138987000, 0.0159860000, 0.0200446000, 0.0285374000, 0.0461146000, 0.0829850000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0064617000, 0.0055675000, 0.0036883000, -0.000264200, -0.008593100, -0.026200900, -0.063479800", \ - "0.0063447000, 0.0054582000, 0.0035795000, -0.000377200, -0.008697100, -0.026300100, -0.063582900", \ - "0.0062187000, 0.0053275000, 0.0034538000, -0.000504900, -0.008817300, -0.026423600, -0.063710100", \ - "0.0060896000, 0.0051936000, 0.0033240000, -0.000617900, -0.008931200, -0.026528600, -0.063796200", \ - "0.0059799000, 0.0050944000, 0.0032471000, -0.000661800, -0.008936200, -0.026597500, -0.063859000", \ - "0.0061381000, 0.0052427000, 0.0033734000, -0.000629200, -0.009084900, -0.026651200, -0.063894800", \ - "0.0068828000, 0.0059940000, 0.0040545000, -1.95000e-05, -0.008496800, -0.026278300, -0.063795600"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0173120000, 0.0182209000, 0.0201083000, 0.0240870000, 0.0324604000, 0.0500232000, 0.0870006000", \ - "0.0172081000, 0.0180918000, 0.0200200000, 0.0240014000, 0.0323777000, 0.0499734000, 0.0869482000", \ - "0.0170912000, 0.0179900000, 0.0199167000, 0.0239049000, 0.0322971000, 0.0499002000, 0.0869660000", \ - "0.0169481000, 0.0178598000, 0.0197763000, 0.0238096000, 0.0322071000, 0.0498354000, 0.0868586000", \ - "0.0168192000, 0.0177304000, 0.0196441000, 0.0236427000, 0.0320408000, 0.0496991000, 0.0867588000", \ - "0.0168275000, 0.0177306000, 0.0196361000, 0.0236230000, 0.0320013000, 0.0496025000, 0.0867394000", \ - "0.0165767000, 0.0174525000, 0.0194246000, 0.0235986000, 0.0321520000, 0.0496945000, 0.0867356000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0036549000, 0.0027760000, 0.0009026000, -0.003050300, -0.011426100, -0.029128600, -0.066518000", \ - "0.0037005000, 0.0028210000, 0.0009622000, -0.002988000, -0.011344700, -0.029034700, -0.066417100", \ - "0.0037614000, 0.0029000000, 0.0010679000, -0.002857100, -0.011180000, -0.028850400, -0.066215200", \ - "0.0035452000, 0.0027037000, 0.0008844000, -0.002981300, -0.011271900, -0.028890500, -0.066228900", \ - "0.0035852000, 0.0027173000, 0.0008734000, -0.002950200, -0.011318900, -0.028911400, -0.066213500", \ - "0.0038640000, 0.0029987000, 0.0011441000, -0.002972300, -0.011320200, -0.028865600, -0.066237500", \ - "0.0049853000, 0.0040360000, 0.0020835000, -0.002002000, -0.010487700, -0.028215400, -0.065849900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0150060000, 0.0159282000, 0.0178279000, 0.0218836000, 0.0303036000, 0.0479038000, 0.0849415000", \ - "0.0148311000, 0.0157356000, 0.0176899000, 0.0217253000, 0.0301519000, 0.0478123000, 0.0848574000", \ - "0.0146106000, 0.0155055000, 0.0174655000, 0.0215136000, 0.0300003000, 0.0476909000, 0.0848258000", \ - "0.0144242000, 0.0153524000, 0.0172689000, 0.0213042000, 0.0297552000, 0.0474759000, 0.0846747000", \ - "0.0143259000, 0.0152316000, 0.0171449000, 0.0211520000, 0.0295674000, 0.0472458000, 0.0844088000", \ - "0.0142703000, 0.0151656000, 0.0170455000, 0.0210949000, 0.0295226000, 0.0471429000, 0.0843145000", \ - "0.0146067000, 0.0154806000, 0.0173122000, 0.0212493000, 0.0295831000, 0.0471009000, 0.0844296000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0002324000, -0.000633000, -0.002484000, -0.006428900, -0.014812900, -0.032533600, -0.069951000", \ - "0.0001011000, -0.000733600, -0.002541100, -0.006442700, -0.014766500, -0.032455000, -0.069858900", \ - "-6.23000e-05, -0.000887600, -0.002667100, -0.006506400, -0.014783400, -0.032410600, -0.069772300", \ - "-0.000294300, -0.001102900, -0.002854400, -0.006662000, -0.014871700, -0.032445500, -0.069774700", \ - "-0.000149000, -0.001113100, -0.002929600, -0.006770100, -0.015008400, -0.032537800, -0.069794400", \ - "0.0001866000, -0.000695300, -0.002556400, -0.006743800, -0.015056500, -0.032699300, -0.069799600", \ - "0.0016774000, 0.0007250000, -0.001383000, -0.005572300, -0.014149800, -0.032211200, -0.069132100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010543310, 0.0022232270, 0.0046880330, 0.0098854730, 0.0208451200, 0.0439553000"); - values("0.0138894000, 0.0148244000, 0.0167797000, 0.0208351000, 0.0292703000, 0.0469235000, 0.0839260000", \ - "0.0137132000, 0.0146529000, 0.0165709000, 0.0206539000, 0.0291449000, 0.0468105000, 0.0839351000", \ - "0.0134814000, 0.0144002000, 0.0163534000, 0.0204208000, 0.0289396000, 0.0466952000, 0.0838187000", \ - "0.0133185000, 0.0142351000, 0.0161528000, 0.0201977000, 0.0286843000, 0.0464554000, 0.0835807000", \ - "0.0133743000, 0.0143597000, 0.0161894000, 0.0201655000, 0.0285524000, 0.0461963000, 0.0834083000", \ - "0.0140594000, 0.0149534000, 0.0168494000, 0.0208198000, 0.0286704000, 0.0461934000, 0.0832198000", \ - "0.0152991000, 0.0161299000, 0.0178011000, 0.0215734000, 0.0296589000, 0.0468916000, 0.0832297000"); - } - } - max_capacitance : 0.0439550000; - max_transition : 1.4899030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0430119000, 0.0477281000, 0.0571925000, 0.0758366000, 0.1128822000, 0.1873518000, 0.3401084000", \ - "0.0467859000, 0.0513995000, 0.0609000000, 0.0795652000, 0.1165632000, 0.1910536000, 0.3437489000", \ - "0.0564144000, 0.0609868000, 0.0702450000, 0.0887466000, 0.1257987000, 0.2000926000, 0.3531238000", \ - "0.0795569000, 0.0844299000, 0.0937959000, 0.1117306000, 0.1474993000, 0.2217946000, 0.3746521000", \ - "0.1099247000, 0.1169290000, 0.1305031000, 0.1556754000, 0.1989562000, 0.2742084000, 0.4265843000", \ - "0.1398899000, 0.1504261000, 0.1706173000, 0.2074315000, 0.2720966000, 0.3763397000, 0.5456097000", \ - "0.1447299000, 0.1604318000, 0.1908961000, 0.2458364000, 0.3429780000, 0.5039625000, 0.7560508000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1403010000, 0.1532606000, 0.1796961000, 0.2338974000, 0.3473332000, 0.5847661000, 1.0844684000", \ - "0.1436442000, 0.1568652000, 0.1837510000, 0.2393680000, 0.3546543000, 0.5907067000, 1.0911972000", \ - "0.1548701000, 0.1675694000, 0.1946003000, 0.2504382000, 0.3649121000, 0.6038144000, 1.1056891000", \ - "0.1826555000, 0.1954099000, 0.2219043000, 0.2776291000, 0.3919296000, 0.6320255000, 1.1346499000", \ - "0.2417679000, 0.2547668000, 0.2812950000, 0.3357314000, 0.4511079000, 0.6893701000, 1.1983388000", \ - "0.3423930000, 0.3591651000, 0.3914674000, 0.4549536000, 0.5752333000, 0.8146531000, 1.3198247000", \ - "0.5055222000, 0.5289795000, 0.5756382000, 0.6618973000, 0.8167335000, 1.0909658000, 1.6006951000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0486345000, 0.0535533000, 0.0644016000, 0.0862858000, 0.1316836000, 0.2274708000, 0.4290154000", \ - "0.0477414000, 0.0529608000, 0.0637132000, 0.0859859000, 0.1314215000, 0.2270457000, 0.4290221000", \ - "0.0465813000, 0.0515592000, 0.0623724000, 0.0850084000, 0.1313182000, 0.2271746000, 0.4294843000", \ - "0.0556737000, 0.0596411000, 0.0684016000, 0.0878969000, 0.1312674000, 0.2268549000, 0.4285190000", \ - "0.0791937000, 0.0849427000, 0.0966628000, 0.1163531000, 0.1538911000, 0.2353271000, 0.4291300000", \ - "0.1245781000, 0.1324518000, 0.1479062000, 0.1758685000, 0.2251216000, 0.3085149000, 0.4695509000", \ - "0.2038979000, 0.2175758000, 0.2410044000, 0.2846624000, 0.3521257000, 0.4652999000, 0.6492906000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0955263000, 0.1116518000, 0.1458961000, 0.2178401000, 0.3696887000, 0.6885034000, 1.3589081000", \ - "0.0953582000, 0.1118390000, 0.1459769000, 0.2180839000, 0.3719393000, 0.6888879000, 1.3587553000", \ - "0.0956049000, 0.1117925000, 0.1459511000, 0.2184914000, 0.3705059000, 0.6890467000, 1.3650039000", \ - "0.0957296000, 0.1119421000, 0.1459901000, 0.2184498000, 0.3703755000, 0.6880732000, 1.3654983000", \ - "0.1018421000, 0.1167344000, 0.1491092000, 0.2191496000, 0.3706626000, 0.6887659000, 1.3720256000", \ - "0.1327813000, 0.1485638000, 0.1812023000, 0.2464112000, 0.3842157000, 0.6923824000, 1.3620914000", \ - "0.2069036000, 0.2238844000, 0.2599503000, 0.3299771000, 0.4724546000, 0.7508887000, 1.3782815000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0497273000, 0.0544036000, 0.0638074000, 0.0824326000, 0.1194754000, 0.1939093000, 0.3466226000", \ - "0.0537636000, 0.0584025000, 0.0677958000, 0.0864464000, 0.1234218000, 0.1978321000, 0.3510042000", \ - "0.0630718000, 0.0675800000, 0.0768342000, 0.0953766000, 0.1324543000, 0.2067831000, 0.3597011000", \ - "0.0836686000, 0.0884513000, 0.0981801000, 0.1168124000, 0.1535326000, 0.2280837000, 0.3808712000", \ - "0.1157368000, 0.1221305000, 0.1347162000, 0.1582935000, 0.2002409000, 0.2768800000, 0.4299370000", \ - "0.1519988000, 0.1615652000, 0.1796555000, 0.2139676000, 0.2738826000, 0.3730376000, 0.5415205000", \ - "0.1691632000, 0.1837958000, 0.2122852000, 0.2648282000, 0.3552246000, 0.5046590000, 0.7392994000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1771798000, 0.1904207000, 0.2181501000, 0.2755980000, 0.3961012000, 0.6489752000, 1.1817561000", \ - "0.1811000000, 0.1947966000, 0.2225909000, 0.2806067000, 0.4014433000, 0.6551549000, 1.1871165000", \ - "0.1923124000, 0.2061331000, 0.2341829000, 0.2925823000, 0.4139798000, 0.6678427000, 1.2012725000", \ - "0.2201992000, 0.2334754000, 0.2611687000, 0.3195129000, 0.4413073000, 0.6958709000, 1.2301204000", \ - "0.2774162000, 0.2907441000, 0.3181444000, 0.3765961000, 0.4978221000, 0.7522968000, 1.2867194000", \ - "0.3824311000, 0.3981170000, 0.4301187000, 0.4937972000, 0.6180016000, 0.8718417000, 1.4085667000", \ - "0.5571343000, 0.5784881000, 0.6206824000, 0.7021570000, 0.8550815000, 1.1364562000, 1.6753141000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0477088000, 0.0528095000, 0.0636644000, 0.0858456000, 0.1315876000, 0.2271333000, 0.4291245000", \ - "0.0472196000, 0.0524715000, 0.0632680000, 0.0855669000, 0.1314235000, 0.2272242000, 0.4292663000", \ - "0.0468900000, 0.0519857000, 0.0626967000, 0.0851056000, 0.1311909000, 0.2270809000, 0.4290782000", \ - "0.0527814000, 0.0575549000, 0.0664931000, 0.0871598000, 0.1313732000, 0.2268343000, 0.4289942000", \ - "0.0732779000, 0.0785250000, 0.0886683000, 0.1079132000, 0.1465449000, 0.2331814000, 0.4292037000", \ - "0.1139091000, 0.1213859000, 0.1338132000, 0.1575438000, 0.2030964000, 0.2854668000, 0.4564254000", \ - "0.1882688000, 0.1977322000, 0.2163938000, 0.2514268000, 0.3119159000, 0.4146973000, 0.5914193000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1274358000, 0.1452489000, 0.1816332000, 0.2586037000, 0.4198848000, 0.7591291000, 1.4782843000", \ - "0.1277062000, 0.1455176000, 0.1816539000, 0.2585447000, 0.4202971000, 0.7613857000, 1.4739097000", \ - "0.1277184000, 0.1455046000, 0.1816368000, 0.2585314000, 0.4198731000, 0.7591817000, 1.4785835000", \ - "0.1281849000, 0.1449787000, 0.1817671000, 0.2585168000, 0.4200360000, 0.7591153000, 1.4784282000", \ - "0.1311071000, 0.1475953000, 0.1837883000, 0.2597869000, 0.4197903000, 0.7589772000, 1.4736893000", \ - "0.1589186000, 0.1757155000, 0.2096271000, 0.2801855000, 0.4315595000, 0.7619604000, 1.4803110000", \ - "0.2274571000, 0.2457879000, 0.2828372000, 0.3580237000, 0.5086434000, 0.8126385000, 1.4899034000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0534049000, 0.0579934000, 0.0674694000, 0.0861469000, 0.1231280000, 0.1975600000, 0.3501716000", \ - "0.0575572000, 0.0621617000, 0.0715901000, 0.0902089000, 0.1271574000, 0.2015736000, 0.3545558000", \ - "0.0661699000, 0.0707838000, 0.0801307000, 0.0987098000, 0.1355809000, 0.2100975000, 0.3629326000", \ - "0.0843265000, 0.0889110000, 0.0983887000, 0.1169176000, 0.1536497000, 0.2280589000, 0.3808346000", \ - "0.1143766000, 0.1197782000, 0.1313158000, 0.1529023000, 0.1933672000, 0.2689863000, 0.4220877000", \ - "0.1523757000, 0.1602725000, 0.1763123000, 0.2067087000, 0.2589344000, 0.3502445000, 0.5154731000", \ - "0.1781284000, 0.1916421000, 0.2160525000, 0.2609213000, 0.3413528000, 0.4728919000, 0.6844605000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1875915000, 0.2006298000, 0.2270658000, 0.2812688000, 0.3953672000, 0.6342913000, 1.1355693000", \ - "0.1929188000, 0.2055447000, 0.2317233000, 0.2868592000, 0.4006906000, 0.6397065000, 1.1416990000", \ - "0.2054066000, 0.2174364000, 0.2440828000, 0.2994551000, 0.4136090000, 0.6530998000, 1.1544191000", \ - "0.2312285000, 0.2441058000, 0.2708482000, 0.3257207000, 0.4402642000, 0.6798619000, 1.1820617000", \ - "0.2851578000, 0.2977518000, 0.3236768000, 0.3786614000, 0.4933198000, 0.7329339000, 1.2350893000", \ - "0.3820851000, 0.3958422000, 0.4265809000, 0.4858418000, 0.6033466000, 0.8426636000, 1.3448969000", \ - "0.5392130000, 0.5584542000, 0.5961817000, 0.6719301000, 0.8148123000, 1.0821360000, 1.5906734000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0472961000, 0.0525190000, 0.0633111000, 0.0854273000, 0.1315532000, 0.2273365000, 0.4294738000", \ - "0.0470176000, 0.0523067000, 0.0630214000, 0.0853796000, 0.1313481000, 0.2270313000, 0.4287426000", \ - "0.0467041000, 0.0518384000, 0.0627862000, 0.0852331000, 0.1312024000, 0.2273047000, 0.4291352000", \ - "0.0504682000, 0.0551463000, 0.0650377000, 0.0862508000, 0.1312394000, 0.2269841000, 0.4290494000", \ - "0.0662983000, 0.0708600000, 0.0809403000, 0.1008895000, 0.1418774000, 0.2310984000, 0.4293318000", \ - "0.1028034000, 0.1077295000, 0.1200225000, 0.1420878000, 0.1848053000, 0.2695541000, 0.4479241000", \ - "0.1733060000, 0.1813889000, 0.1972246000, 0.2259493000, 0.2787974000, 0.3758766000, 0.5514046000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1409610000, 0.1574035000, 0.1921305000, 0.2647404000, 0.4173521000, 0.7388352000, 1.4114480000", \ - "0.1410651000, 0.1571497000, 0.1921564000, 0.2645099000, 0.4169263000, 0.7391732000, 1.4150672000", \ - "0.1410006000, 0.1574564000, 0.1920069000, 0.2644913000, 0.4172475000, 0.7393287000, 1.4120222000", \ - "0.1409000000, 0.1573791000, 0.1921841000, 0.2651187000, 0.4169322000, 0.7390237000, 1.4164315000", \ - "0.1435275000, 0.1597218000, 0.1934557000, 0.2649687000, 0.4177103000, 0.7400493000, 1.4126974000", \ - "0.1700735000, 0.1861979000, 0.2192112000, 0.2863195000, 0.4291416000, 0.7399329000, 1.4130741000", \ - "0.2356382000, 0.2531697000, 0.2888390000, 0.3611399000, 0.5056208000, 0.7957763000, 1.4310190000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0216340000, 0.0236881000, 0.0278532000, 0.0362246000, 0.0532232000, 0.0884877000, 0.1620241000", \ - "0.0264882000, 0.0285313000, 0.0326360000, 0.0408817000, 0.0579318000, 0.0931765000, 0.1667648000", \ - "0.0372111000, 0.0395238000, 0.0439881000, 0.0519628000, 0.0689743000, 0.1042196000, 0.1777926000", \ - "0.0517072000, 0.0555156000, 0.0621902000, 0.0742728000, 0.0943167000, 0.1298592000, 0.2032807000", \ - "0.0666372000, 0.0722485000, 0.0829583000, 0.1015407000, 0.1337396000, 0.1846074000, 0.2631021000", \ - "0.0722714000, 0.0808841000, 0.0974974000, 0.1284141000, 0.1792591000, 0.2580039000, 0.3783662000", \ - "0.0417690000, 0.0552783000, 0.0821466000, 0.1302504000, 0.2108365000, 0.3360786000, 0.5251767000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1714631000, 0.1843246000, 0.2107553000, 0.2661848000, 0.3805010000, 0.6198774000, 1.1217917000", \ - "0.1746918000, 0.1877122000, 0.2137141000, 0.2699314000, 0.3848383000, 0.6242653000, 1.1265097000", \ - "0.1847093000, 0.1975298000, 0.2245248000, 0.2801430000, 0.3952617000, 0.6359549000, 1.1385253000", \ - "0.2109350000, 0.2239596000, 0.2499479000, 0.3057469000, 0.4211008000, 0.6613021000, 1.1648608000", \ - "0.2722849000, 0.2846083000, 0.3110800000, 0.3664344000, 0.4812505000, 0.7213782000, 1.2250473000", \ - "0.3934793000, 0.4097612000, 0.4411648000, 0.5050680000, 0.6235581000, 0.8636755000, 1.3664172000", \ - "0.5997497000, 0.6232755000, 0.6690827000, 0.7569671000, 0.9117784000, 1.1877369000, 1.6986890000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0209000000, 0.0232537000, 0.0281868000, 0.0384791000, 0.0601379000, 0.1060046000, 0.2027830000", \ - "0.0206734000, 0.0229826000, 0.0279931000, 0.0383697000, 0.0601309000, 0.1058933000, 0.2029564000", \ - "0.0249847000, 0.0267423000, 0.0307814000, 0.0398167000, 0.0603358000, 0.1061754000, 0.2028316000", \ - "0.0396274000, 0.0417591000, 0.0459004000, 0.0539771000, 0.0701278000, 0.1091558000, 0.2028109000", \ - "0.0655779000, 0.0687373000, 0.0746717000, 0.0868160000, 0.1070570000, 0.1404079000, 0.2166664000", \ - "0.1122792000, 0.1172493000, 0.1269364000, 0.1439422000, 0.1736449000, 0.2242746000, 0.3007567000", \ - "0.1963468000, 0.2039193000, 0.2183247000, 0.2452425000, 0.2910622000, 0.3670729000, 0.4795411000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1408788000, 0.1575946000, 0.1917289000, 0.2652722000, 0.4171966000, 0.7371598000, 1.4142724000", \ - "0.1410219000, 0.1570449000, 0.1919733000, 0.2645587000, 0.4171594000, 0.7373788000, 1.4100575000", \ - "0.1410645000, 0.1571560000, 0.1922825000, 0.2645312000, 0.4170170000, 0.7376051000, 1.4107546000", \ - "0.1409368000, 0.1575184000, 0.1920135000, 0.2644722000, 0.4170224000, 0.7376844000, 1.4109875000", \ - "0.1470779000, 0.1623637000, 0.1953910000, 0.2651741000, 0.4170976000, 0.7386289000, 1.4156122000", \ - "0.1913251000, 0.2067721000, 0.2367117000, 0.2988006000, 0.4345107000, 0.7394499000, 1.4129597000", \ - "0.2887182000, 0.3063519000, 0.3417067000, 0.4160176000, 0.5437194000, 0.8083055000, 1.4322373000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0179694000, 0.0198885000, 0.0239240000, 0.0321818000, 0.0494041000, 0.0854919000, 0.1612370000", \ - "0.0227086000, 0.0246965000, 0.0286498000, 0.0369904000, 0.0543401000, 0.0903901000, 0.1662347000", \ - "0.0316283000, 0.0344344000, 0.0395947000, 0.0484628000, 0.0657567000, 0.1016242000, 0.1775404000", \ - "0.0426172000, 0.0468364000, 0.0549885000, 0.0689745000, 0.0914275000, 0.1282991000, 0.2028856000", \ - "0.0513509000, 0.0589018000, 0.0719235000, 0.0942574000, 0.1291796000, 0.1833072000, 0.2647666000", \ - "0.0506828000, 0.0616874000, 0.0822118000, 0.1178320000, 0.1744867000, 0.2596234000, 0.3827917000", \ - "0.0145119000, 0.0308717000, 0.0639785000, 0.1194937000, 0.2090932000, 0.3437850000, 0.5370834000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1329190000, 0.1466503000, 0.1728627000, 0.2288326000, 0.3436713000, 0.5832340000, 1.0852215000", \ - "0.1356483000, 0.1489001000, 0.1757001000, 0.2316230000, 0.3471102000, 0.5867701000, 1.0892488000", \ - "0.1435501000, 0.1559919000, 0.1828329000, 0.2389279000, 0.3548581000, 0.5958213000, 1.0990620000", \ - "0.1672537000, 0.1801117000, 0.2066572000, 0.2617972000, 0.3769946000, 0.6180007000, 1.1222293000", \ - "0.2295421000, 0.2421996000, 0.2670912000, 0.3212752000, 0.4356504000, 0.6749812000, 1.1787767000", \ - "0.3490893000, 0.3664278000, 0.3991347000, 0.4640668000, 0.5799025000, 0.8164249000, 1.3174912000", \ - "0.5348192000, 0.5590373000, 0.6072601000, 0.7013825000, 0.8669525000, 1.1471774000, 1.6412420000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.0156987000, 0.0183527000, 0.0237504000, 0.0347108000, 0.0573517000, 0.1049492000, 0.2052245000", \ - "0.0161577000, 0.0185925000, 0.0237709000, 0.0347013000, 0.0572874000, 0.1049913000, 0.2051239000", \ - "0.0228059000, 0.0242480000, 0.0280255000, 0.0369291000, 0.0576858000, 0.1050296000, 0.2051671000", \ - "0.0378635000, 0.0400258000, 0.0443223000, 0.0523827000, 0.0681299000, 0.1083008000, 0.2051258000", \ - "0.0651271000, 0.0677751000, 0.0736618000, 0.0849625000, 0.1060088000, 0.1399896000, 0.2185441000", \ - "0.1131018000, 0.1175830000, 0.1273764000, 0.1435155000, 0.1731153000, 0.2224494000, 0.3042568000", \ - "0.2015805000, 0.2080553000, 0.2218722000, 0.2479230000, 0.2929818000, 0.3674057000, 0.4854807000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010543300, 0.0022232300, 0.0046880300, 0.0098854700, 0.0208451000, 0.0439553000"); - values("0.1405509000, 0.1572235000, 0.1920552000, 0.2644654000, 0.4171789000, 0.7370592000, 1.4105948000", \ - "0.1406517000, 0.1572957000, 0.1917472000, 0.2644931000, 0.4183294000, 0.7373722000, 1.4119795000", \ - "0.1404280000, 0.1568900000, 0.1917826000, 0.2644213000, 0.4171735000, 0.7372381000, 1.4117195000", \ - "0.1378472000, 0.1551235000, 0.1908621000, 0.2641365000, 0.4168517000, 0.7373131000, 1.4114332000", \ - "0.1517170000, 0.1658974000, 0.1972492000, 0.2653852000, 0.4159635000, 0.7373143000, 1.4137638000", \ - "0.2045778000, 0.2221200000, 0.2547395000, 0.3183134000, 0.4443988000, 0.7429373000, 1.4154635000", \ - "0.2966324000, 0.3186331000, 0.3627235000, 0.4453682000, 0.5905759000, 0.8505249000, 1.4409981000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311oi_2") { - leakage_power () { - value : 0.0034799000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0019063000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0019359000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0019387000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0026814000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0019506000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0024609000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0034799000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0024464000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002465000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0022524000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004861000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0046281000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0001728000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0004677000; - when : "A1&A2&A3&B1&!C1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__a311oi"; - cell_leakage_power : 0.0019664690; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093531000, 0.0093516000, 0.0093482000, 0.0093486000, 0.0093494000, 0.0093513000, 0.0093556000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007130300, -0.007135900, -0.007148800, -0.007133200, -0.007097100, -0.007013900, -0.006822000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045120000; - } - pin ("A2") { - capacitance : 0.0043240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085078000, 0.0084961000, 0.0084691000, 0.0085000000, 0.0085712000, 0.0087353000, 0.0091137000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007833800, -0.007832400, -0.007829300, -0.007827200, -0.007822500, -0.007811600, -0.007786400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044680000; - } - pin ("A3") { - capacitance : 0.0043690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078567000, 0.0078490000, 0.0078311000, 0.0078346000, 0.0078427000, 0.0078614000, 0.0079044000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007813600, -0.007812900, -0.007811300, -0.007810300, -0.007808100, -0.007802900, -0.007791000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045820000; - } - pin ("B1") { - capacitance : 0.0043140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080363000, 0.0080382000, 0.0080424000, 0.0080467000, 0.0080565000, 0.0080792000, 0.0081314000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007227900, -0.007334300, -0.007579800, -0.007587000, -0.007603700, -0.007642100, -0.007730800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046140000; - } - pin ("C1") { - capacitance : 0.0043080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055789000, 0.0055717000, 0.0055552000, 0.0055793000, 0.0056350000, 0.0057633000, 0.0060591000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003538000, -0.003538200, -0.003538700, -0.003536800, -0.003532500, -0.003522600, -0.003499600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046550000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1) | (!A3&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0128690000, 0.0117839000, 0.0092353000, 0.0032309000, -0.010790300, -0.043859300, -0.121822900", \ - "0.0126402000, 0.0115591000, 0.0089988000, 0.0030175000, -0.011024700, -0.044056200, -0.122018500", \ - "0.0123159000, 0.0112433000, 0.0086961000, 0.0027070000, -0.011282100, -0.044298300, -0.122352400", \ - "0.0119221000, 0.0108694000, 0.0083411000, 0.0024055000, -0.011594000, -0.044562900, -0.122560200", \ - "0.0115098000, 0.0104363000, 0.0079424000, 0.0020966000, -0.011812900, -0.044800400, -0.122696300", \ - "0.0118147000, 0.0107123000, 0.0081196000, 0.0020655000, -0.011928700, -0.044855100, -0.122753800", \ - "0.0142156000, 0.0130995000, 0.0104059000, 0.0043498000, -0.010227200, -0.044140100, -0.122485200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0227360000, 0.0239047000, 0.0265771000, 0.0327209000, 0.0468966000, 0.0798735000, 0.1580581000", \ - "0.0223195000, 0.0235342000, 0.0262086000, 0.0324797000, 0.0467969000, 0.0798749000, 0.1574092000", \ - "0.0217549000, 0.0229560000, 0.0257057000, 0.0320429000, 0.0464088000, 0.0798558000, 0.1577631000", \ - "0.0213176000, 0.0224743000, 0.0251241000, 0.0313355000, 0.0458385000, 0.0795191000, 0.1574114000", \ - "0.0209891000, 0.0220855000, 0.0247108000, 0.0308094000, 0.0452240000, 0.0785719000, 0.1575301000", \ - "0.0209670000, 0.0220835000, 0.0246768000, 0.0306470000, 0.0448008000, 0.0782053000, 0.1565388000", \ - "0.0204723000, 0.0215466000, 0.0241191000, 0.0306298000, 0.0449847000, 0.0778307000, 0.1556657000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0136707000, 0.0125823000, 0.0100156000, 0.0040111000, -0.009994800, -0.043030800, -0.121017400", \ - "0.0134468000, 0.0123714000, 0.0098039000, 0.0038128000, -0.010200200, -0.043219300, -0.121239100", \ - "0.0132075000, 0.0121194000, 0.0095552000, 0.0035716000, -0.010444100, -0.043488200, -0.121500900", \ - "0.0129429000, 0.0118716000, 0.0093299000, 0.0033155000, -0.010700500, -0.043677400, -0.121672100", \ - "0.0126823000, 0.0116124000, 0.0091142000, 0.0032070000, -0.010702000, -0.043755600, -0.121685600", \ - "0.0125845000, 0.0114724000, 0.0089082000, 0.0029228000, -0.011053800, -0.043922900, -0.121874300", \ - "0.0139586000, 0.0128535000, 0.0102771000, 0.0041344000, -0.010182300, -0.043768000, -0.121853100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0288036000, 0.0299072000, 0.0324415000, 0.0384890000, 0.0525223000, 0.0855412000, 0.1630200000", \ - "0.0285168000, 0.0296416000, 0.0322565000, 0.0383218000, 0.0524805000, 0.0855478000, 0.1628792000", \ - "0.0281690000, 0.0292767000, 0.0319181000, 0.0380318000, 0.0523089000, 0.0854456000, 0.1626849000", \ - "0.0277279000, 0.0288473000, 0.0314593000, 0.0375676000, 0.0518613000, 0.0851085000, 0.1627708000", \ - "0.0273264000, 0.0284533000, 0.0310292000, 0.0371156000, 0.0513433000, 0.0844945000, 0.1621892000", \ - "0.0271399000, 0.0282492000, 0.0307946000, 0.0368038000, 0.0509685000, 0.0840667000, 0.1617508000", \ - "0.0261053000, 0.0271820000, 0.0299740000, 0.0363570000, 0.0507076000, 0.0836874000, 0.1610640000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0134551000, 0.0123445000, 0.0097923000, 0.0037796000, -0.010227300, -0.043255200, -0.121237800", \ - "0.0132259000, 0.0121401000, 0.0095736000, 0.0035780000, -0.010434200, -0.043471700, -0.121459000", \ - "0.0129847000, 0.0118852000, 0.0093354000, 0.0033502000, -0.010677200, -0.043705000, -0.121710800", \ - "0.0126818000, 0.0116070000, 0.0090555000, 0.0030583000, -0.010920700, -0.043918800, -0.121924600", \ - "0.0124749000, 0.0114195000, 0.0088997000, 0.0029720000, -0.010952300, -0.043940400, -0.121927000", \ - "0.0124850000, 0.0114102000, 0.0088751000, 0.0027302000, -0.011274300, -0.044181000, -0.122152300", \ - "0.0137299000, 0.0128079000, 0.0101901000, 0.0039594000, -0.010253700, -0.043828400, -0.121942800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0353683000, 0.0364285000, 0.0390449000, 0.0450179000, 0.0592017000, 0.0922566000, 0.1697788000", \ - "0.0351445000, 0.0361849000, 0.0387653000, 0.0448123000, 0.0589439000, 0.0920553000, 0.1695689000", \ - "0.0347850000, 0.0358829000, 0.0384914000, 0.0445724000, 0.0588310000, 0.0919643000, 0.1695010000", \ - "0.0344745000, 0.0355821000, 0.0382288000, 0.0442973000, 0.0585374000, 0.0917723000, 0.1693742000", \ - "0.0342299000, 0.0353103000, 0.0379197000, 0.0439770000, 0.0582055000, 0.0914126000, 0.1691346000", \ - "0.0341892000, 0.0352585000, 0.0378047000, 0.0438905000, 0.0580785000, 0.0912723000, 0.1688340000", \ - "0.0335213000, 0.0346128000, 0.0375161000, 0.0437693000, 0.0581642000, 0.0912465000, 0.1687045000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0079646000, 0.0068920000, 0.0043758000, -0.001587700, -0.015650800, -0.048841200, -0.127079800", \ - "0.0079870000, 0.0069223000, 0.0043990000, -0.001521200, -0.015572200, -0.048740600, -0.126963600", \ - "0.0080023000, 0.0069544000, 0.0044711000, -0.001430200, -0.015411900, -0.048520000, -0.126708000", \ - "0.0075481000, 0.0065112000, 0.0040794000, -0.001720900, -0.015603500, -0.048632800, -0.126758200", \ - "0.0077457000, 0.0066362000, 0.0041337000, -0.001797200, -0.015712300, -0.048674300, -0.126754300", \ - "0.0084809000, 0.0074065000, 0.0048880000, -0.001096800, -0.015521800, -0.048454300, -0.126733300", \ - "0.0111948000, 0.0100292000, 0.0073725000, 0.0010793000, -0.013399300, -0.046563600, -0.125741300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0298702000, 0.0310222000, 0.0336793000, 0.0398333000, 0.0540776000, 0.0872594000, 0.1648735000", \ - "0.0295618000, 0.0307109000, 0.0333329000, 0.0395235000, 0.0539035000, 0.0871568000, 0.1647895000", \ - "0.0291869000, 0.0302292000, 0.0329189000, 0.0390478000, 0.0534599000, 0.0868256000, 0.1645942000", \ - "0.0288235000, 0.0299001000, 0.0324912000, 0.0386296000, 0.0529531000, 0.0863524000, 0.1642649000", \ - "0.0284532000, 0.0295641000, 0.0321601000, 0.0382567000, 0.0525292000, 0.0858445000, 0.1637806000", \ - "0.0284103000, 0.0294958000, 0.0320937000, 0.0381780000, 0.0525378000, 0.0857513000, 0.1634023000", \ - "0.0292105000, 0.0302566000, 0.0327407000, 0.0386792000, 0.0527577000, 0.0857722000, 0.1636166000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("-4.39000e-05, -0.001073800, -0.003554800, -0.009502700, -0.023615500, -0.056907800, -0.135267700", \ - "-0.000311700, -0.001313300, -0.003724800, -0.009549200, -0.023544700, -0.056750000, -0.135058600", \ - "-0.000660300, -0.001654200, -0.004004500, -0.009725000, -0.023567600, -0.056653000, -0.134892700", \ - "-0.000869800, -0.002014200, -0.004318200, -0.009980300, -0.023699300, -0.056691200, -0.134814300", \ - "-0.000668000, -0.001712600, -0.004173200, -0.009973500, -0.024017000, -0.056858200, -0.134855300", \ - "-0.000161100, -0.001115500, -0.003744000, -0.009585600, -0.023800400, -0.056833800, -0.134980900", \ - "0.0028456000, 0.0016428000, -0.001184400, -0.007664000, -0.022180300, -0.055430700, -0.133897700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615330, 0.0064899340, 0.0152521300, 0.0358443300, 0.0842384900"); - values("0.0275808000, 0.0286911000, 0.0313385000, 0.0375676000, 0.0519099000, 0.0851447000, 0.1627965000", \ - "0.0271408000, 0.0283265000, 0.0309814000, 0.0371687000, 0.0516484000, 0.0849864000, 0.1625853000", \ - "0.0268229000, 0.0279324000, 0.0304682000, 0.0367224000, 0.0511902000, 0.0846200000, 0.1624783000", \ - "0.0263997000, 0.0275054000, 0.0301365000, 0.0362519000, 0.0506002000, 0.0840629000, 0.1620830000", \ - "0.0264537000, 0.0275490000, 0.0301286000, 0.0361425000, 0.0502923000, 0.0835796000, 0.1615135000", \ - "0.0271119000, 0.0282107000, 0.0307640000, 0.0367451000, 0.0507924000, 0.0837384000, 0.1611046000", \ - "0.0294870000, 0.0305510000, 0.0329061000, 0.0386267000, 0.0523544000, 0.0846327000, 0.1607804000"); - } - } - max_capacitance : 0.0842380000; - max_transition : 1.5083280000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0497650000, 0.0535324000, 0.0619952000, 0.0805388000, 0.1208090000, 0.2097721000, 0.4107689000", \ - "0.0534765000, 0.0572685000, 0.0657235000, 0.0841910000, 0.1245831000, 0.2133999000, 0.4145067000", \ - "0.0630907000, 0.0667173000, 0.0751117000, 0.0934769000, 0.1337732000, 0.2224194000, 0.4241636000", \ - "0.0880832000, 0.0916860000, 0.0995913000, 0.1168320000, 0.1565428000, 0.2450923000, 0.4466100000", \ - "0.1250142000, 0.1302159000, 0.1414335000, 0.1639672000, 0.2103852000, 0.2979559000, 0.4988416000", \ - "0.1645295000, 0.1720568000, 0.1886313000, 0.2231642000, 0.2900646000, 0.4114933000, 0.6197398000", \ - "0.1877738000, 0.1988024000, 0.2234260000, 0.2735148000, 0.3731777000, 0.5559225000, 0.8638704000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1430240000, 0.1517501000, 0.1712971000, 0.2171663000, 0.3212748000, 0.5644946000, 1.1346082000", \ - "0.1461524000, 0.1550650000, 0.1751498000, 0.2216349000, 0.3266176000, 0.5704230000, 1.1412388000", \ - "0.1567956000, 0.1655126000, 0.1857913000, 0.2323606000, 0.3399849000, 0.5868320000, 1.1587887000", \ - "0.1825419000, 0.1911573000, 0.2109729000, 0.2568565000, 0.3642787000, 0.6148360000, 1.1878079000", \ - "0.2366760000, 0.2453916000, 0.2653312000, 0.3107249000, 0.4171707000, 0.6624447000, 1.2409218000", \ - "0.3260679000, 0.3364800000, 0.3612248000, 0.4144745000, 0.5279154000, 0.7745772000, 1.3534056000", \ - "0.4649028000, 0.4804963000, 0.5164332000, 0.5857402000, 0.7284193000, 1.0123523000, 1.5961752000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0608145000, 0.0644839000, 0.0736148000, 0.0947191000, 0.1435083000, 0.2583377000, 0.5278294000", \ - "0.0597463000, 0.0637686000, 0.0728566000, 0.0941688000, 0.1433804000, 0.2581918000, 0.5273461000", \ - "0.0570064000, 0.0612041000, 0.0707629000, 0.0931883000, 0.1429242000, 0.2576246000, 0.5279906000", \ - "0.0635316000, 0.0669743000, 0.0748169000, 0.0942179000, 0.1417821000, 0.2573664000, 0.5276800000", \ - "0.0862592000, 0.0907701000, 0.1013007000, 0.1225253000, 0.1621783000, 0.2631098000, 0.5274222000", \ - "0.1332520000, 0.1392673000, 0.1522858000, 0.1790258000, 0.2312139000, 0.3306509000, 0.5552499000", \ - "0.2137278000, 0.2229964000, 0.2431569000, 0.2882539000, 0.3585117000, 0.4915650000, 0.7277554000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0912506000, 0.1022611000, 0.1281090000, 0.1873540000, 0.3274304000, 0.6555387000, 1.4323404000", \ - "0.0908438000, 0.1017178000, 0.1271983000, 0.1873510000, 0.3274253000, 0.6561008000, 1.4249045000", \ - "0.0914773000, 0.1024293000, 0.1276262000, 0.1873927000, 0.3277972000, 0.6565576000, 1.4283956000", \ - "0.0911454000, 0.1019403000, 0.1275040000, 0.1881615000, 0.3278725000, 0.6600249000, 1.4306273000", \ - "0.0973156000, 0.1076521000, 0.1315603000, 0.1890896000, 0.3282762000, 0.6553542000, 1.4381557000", \ - "0.1237975000, 0.1345580000, 0.1594245000, 0.2166028000, 0.3441875000, 0.6600039000, 1.4329379000", \ - "0.1882500000, 0.1997420000, 0.2270253000, 0.2864595000, 0.4227441000, 0.7205553000, 1.4470248000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0579580000, 0.0617197000, 0.0701021000, 0.0885257000, 0.1287071000, 0.2174753000, 0.4187882000", \ - "0.0619198000, 0.0656603000, 0.0739343000, 0.0924783000, 0.1326090000, 0.2213795000, 0.4231286000", \ - "0.0705686000, 0.0741755000, 0.0825042000, 0.1008702000, 0.1409415000, 0.2298782000, 0.4312896000", \ - "0.0900717000, 0.0938853000, 0.1023951000, 0.1204816000, 0.1602991000, 0.2490519000, 0.4505616000", \ - "0.1238830000, 0.1285153000, 0.1385312000, 0.1602062000, 0.2043802000, 0.2937401000, 0.4963603000", \ - "0.1647538000, 0.1715593000, 0.1861211000, 0.2164303000, 0.2754691000, 0.3873999000, 0.6002147000", \ - "0.1911655000, 0.2006164000, 0.2238037000, 0.2692529000, 0.3585094000, 0.5214565000, 0.7989089000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1788222000, 0.1871436000, 0.2067400000, 0.2525088000, 0.3586238000, 0.6066158000, 1.1884744000", \ - "0.1833150000, 0.1914364000, 0.2117449000, 0.2576039000, 0.3643496000, 0.6127767000, 1.1941335000", \ - "0.1946952000, 0.2031330000, 0.2235964000, 0.2699115000, 0.3772996000, 0.6262998000, 1.2094442000", \ - "0.2224595000, 0.2311659000, 0.2510261000, 0.2975132000, 0.4050489000, 0.6548040000, 1.2378278000", \ - "0.2806177000, 0.2893829000, 0.3088983000, 0.3550251000, 0.4621928000, 0.7121443000, 1.2963394000", \ - "0.3883001000, 0.3978845000, 0.4211125000, 0.4718591000, 0.5834483000, 0.8328953000, 1.4179499000", \ - "0.5669775000, 0.5804153000, 0.6113051000, 0.6759355000, 0.8134325000, 1.0938368000, 1.6844679000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0591162000, 0.0631847000, 0.0722947000, 0.0939434000, 0.1431509000, 0.2576747000, 0.5275557000", \ - "0.0586898000, 0.0627601000, 0.0719378000, 0.0935864000, 0.1429753000, 0.2578145000, 0.5284370000", \ - "0.0579299000, 0.0618487000, 0.0713031000, 0.0930608000, 0.1427269000, 0.2576063000, 0.5280248000", \ - "0.0619539000, 0.0654159000, 0.0737604000, 0.0941770000, 0.1426095000, 0.2574989000, 0.5277795000", \ - "0.0790306000, 0.0827907000, 0.0915701000, 0.1112509000, 0.1547395000, 0.2617793000, 0.5274013000", \ - "0.1188622000, 0.1233682000, 0.1335912000, 0.1563117000, 0.2053833000, 0.3050538000, 0.5433957000", \ - "0.1928855000, 0.1996069000, 0.2141787000, 0.2466507000, 0.3078974000, 0.4250405000, 0.6575150000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1205049000, 0.1311691000, 0.1573799000, 0.2187728000, 0.3619081000, 0.6985483000, 1.4868902000", \ - "0.1199206000, 0.1313329000, 0.1575315000, 0.2190191000, 0.3632235000, 0.6971024000, 1.4813362000", \ - "0.1201290000, 0.1313438000, 0.1575023000, 0.2190087000, 0.3628252000, 0.6971811000, 1.4837368000", \ - "0.1206212000, 0.1312608000, 0.1573763000, 0.2187621000, 0.3618853000, 0.6967554000, 1.4836680000", \ - "0.1228634000, 0.1336712000, 0.1589999000, 0.2200923000, 0.3619282000, 0.6970903000, 1.4824583000", \ - "0.1473602000, 0.1582910000, 0.1835250000, 0.2410360000, 0.3742758000, 0.6997394000, 1.4875255000", \ - "0.2089697000, 0.2210175000, 0.2480876000, 0.3097893000, 0.4477095000, 0.7494266000, 1.4972393000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0631959000, 0.0669396000, 0.0752776000, 0.0936630000, 0.1339270000, 0.2228332000, 0.4240830000", \ - "0.0674034000, 0.0711222000, 0.0793970000, 0.0978863000, 0.1380482000, 0.2269890000, 0.4281264000", \ - "0.0757444000, 0.0794192000, 0.0876966000, 0.1060961000, 0.1463041000, 0.2351597000, 0.4365343000", \ - "0.0924716000, 0.0960011000, 0.1043672000, 0.1225499000, 0.1625337000, 0.2512230000, 0.4526691000", \ - "0.1202813000, 0.1242468000, 0.1338189000, 0.1540475000, 0.1967935000, 0.2865925000, 0.4881821000", \ - "0.1569188000, 0.1627558000, 0.1756996000, 0.2014385000, 0.2545754000, 0.3581762000, 0.5687125000", \ - "0.1802434000, 0.1896643000, 0.2091409000, 0.2477365000, 0.3249180000, 0.4673160000, 0.7236101000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.2047562000, 0.2129420000, 0.2335329000, 0.2786447000, 0.3840905000, 0.6287622000, 1.2002512000", \ - "0.2094889000, 0.2176720000, 0.2374354000, 0.2836155000, 0.3890672000, 0.6337834000, 1.2056681000", \ - "0.2209024000, 0.2296926000, 0.2497967000, 0.2960299000, 0.4016965000, 0.6462740000, 1.2181831000", \ - "0.2478202000, 0.2565312000, 0.2771222000, 0.3230098000, 0.4287742000, 0.6741028000, 1.2463675000", \ - "0.3037110000, 0.3120494000, 0.3321048000, 0.3778487000, 0.4833843000, 0.7292695000, 1.3015974000", \ - "0.4066878000, 0.4160899000, 0.4375358000, 0.4877007000, 0.5968030000, 0.8416700000, 1.4145539000", \ - "0.5781784000, 0.5908727000, 0.6188218000, 0.6789480000, 0.8110765000, 1.0830605000, 1.6631736000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0587195000, 0.0626051000, 0.0718765000, 0.0936645000, 0.1429116000, 0.2580135000, 0.5277521000", \ - "0.0583724000, 0.0624948000, 0.0717078000, 0.0934923000, 0.1426431000, 0.2579482000, 0.5280040000", \ - "0.0578836000, 0.0618295000, 0.0713330000, 0.0930956000, 0.1427802000, 0.2578542000, 0.5276339000", \ - "0.0601897000, 0.0639003000, 0.0727694000, 0.0937023000, 0.1427132000, 0.2574357000, 0.5282798000", \ - "0.0729685000, 0.0763780000, 0.0851863000, 0.1051515000, 0.1511139000, 0.2607955000, 0.5277215000", \ - "0.1060425000, 0.1104210000, 0.1194441000, 0.1406210000, 0.1866161000, 0.2909954000, 0.5401818000", \ - "0.1756386000, 0.1811392000, 0.1939643000, 0.2184346000, 0.2755519000, 0.3820997000, 0.6243673000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1447495000, 0.1556272000, 0.1816344000, 0.2414349000, 0.3823277000, 0.7130959000, 1.4840685000", \ - "0.1447842000, 0.1557451000, 0.1813018000, 0.2414912000, 0.3821924000, 0.7117807000, 1.4863860000", \ - "0.1445969000, 0.1553714000, 0.1814342000, 0.2414682000, 0.3834849000, 0.7119088000, 1.4821718000", \ - "0.1445483000, 0.1555903000, 0.1815780000, 0.2419695000, 0.3826039000, 0.7115681000, 1.4827293000", \ - "0.1461328000, 0.1568305000, 0.1822312000, 0.2420608000, 0.3829496000, 0.7125034000, 1.4835256000", \ - "0.1699201000, 0.1804775000, 0.2054272000, 0.2608545000, 0.3938286000, 0.7140764000, 1.4841969000", \ - "0.2287150000, 0.2401157000, 0.2673218000, 0.3279889000, 0.4636606000, 0.7661693000, 1.4980303000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0213812000, 0.0227920000, 0.0261240000, 0.0333800000, 0.0496051000, 0.0862099000, 0.1709280000", \ - "0.0261925000, 0.0276415000, 0.0308456000, 0.0380488000, 0.0541648000, 0.0908445000, 0.1755521000", \ - "0.0370126000, 0.0386264000, 0.0422005000, 0.0492479000, 0.0650747000, 0.1017516000, 0.1864366000", \ - "0.0515117000, 0.0539733000, 0.0593942000, 0.0700851000, 0.0902256000, 0.1271034000, 0.2117085000", \ - "0.0665549000, 0.0699464000, 0.0782376000, 0.0950944000, 0.1257601000, 0.1803190000, 0.2708352000", \ - "0.0710891000, 0.0769039000, 0.0896037000, 0.1156141000, 0.1657500000, 0.2500877000, 0.3875134000", \ - "0.0399692000, 0.0490809000, 0.0699409000, 0.1098576000, 0.1874378000, 0.3196242000, 0.5352482000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1847295000, 0.1931817000, 0.2129608000, 0.2598380000, 0.3661104000, 0.6114675000, 1.1832934000", \ - "0.1865439000, 0.1959790000, 0.2154751000, 0.2630516000, 0.3695655000, 0.6150541000, 1.1879588000", \ - "0.1969869000, 0.2046868000, 0.2259662000, 0.2721952000, 0.3794520000, 0.6260776000, 1.1997813000", \ - "0.2224085000, 0.2307858000, 0.2503702000, 0.2972983000, 0.4039693000, 0.6507368000, 1.2248205000", \ - "0.2798887000, 0.2883203000, 0.3083126000, 0.3537536000, 0.4596973000, 0.7063364000, 1.2808732000", \ - "0.3920624000, 0.4029303000, 0.4271075000, 0.4805953000, 0.5937478000, 0.8391283000, 1.4126782000", \ - "0.5849330000, 0.6007490000, 0.6332250000, 0.7064616000, 0.8541002000, 1.1408116000, 1.7233331000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0224256000, 0.0239820000, 0.0276534000, 0.0362625000, 0.0563090000, 0.1036416000, 0.2154381000", \ - "0.0220081000, 0.0235325000, 0.0272101000, 0.0359998000, 0.0562167000, 0.1036528000, 0.2155487000", \ - "0.0261444000, 0.0273104000, 0.0301915000, 0.0376177000, 0.0564595000, 0.1037049000, 0.2152766000", \ - "0.0407701000, 0.0421534000, 0.0452601000, 0.0521526000, 0.0666145000, 0.1072036000, 0.2158963000", \ - "0.0667116000, 0.0687247000, 0.0732956000, 0.0829294000, 0.1033031000, 0.1388460000, 0.2281823000", \ - "0.1128738000, 0.1161118000, 0.1233292000, 0.1386778000, 0.1672589000, 0.2202292000, 0.3100945000", \ - "0.1958547000, 0.2009429000, 0.2120382000, 0.2354542000, 0.2799212000, 0.3605302000, 0.4908772000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1442732000, 0.1553607000, 0.1812312000, 0.2415053000, 0.3821659000, 0.7118560000, 1.4885208000", \ - "0.1447148000, 0.1555509000, 0.1814152000, 0.2415154000, 0.3835750000, 0.7118943000, 1.4831245000", \ - "0.1447611000, 0.1556415000, 0.1816367000, 0.2413622000, 0.3824369000, 0.7119345000, 1.4881967000", \ - "0.1448335000, 0.1557612000, 0.1811593000, 0.2414922000, 0.3824049000, 0.7119292000, 1.4839380000", \ - "0.1502841000, 0.1605893000, 0.1848883000, 0.2426696000, 0.3825959000, 0.7118884000, 1.4830840000", \ - "0.1893924000, 0.2000253000, 0.2243045000, 0.2771633000, 0.4022868000, 0.7154906000, 1.4827324000", \ - "0.2801949000, 0.2919700000, 0.3204235000, 0.3805318000, 0.5103987000, 0.7881512000, 1.5007815000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0170375000, 0.0183376000, 0.0212924000, 0.0280201000, 0.0433285000, 0.0791259000, 0.1630460000", \ - "0.0217004000, 0.0230094000, 0.0260361000, 0.0326741000, 0.0482358000, 0.0840421000, 0.1679411000", \ - "0.0298726000, 0.0317883000, 0.0358922000, 0.0439691000, 0.0595064000, 0.0953279000, 0.1791128000", \ - "0.0386472000, 0.0422185000, 0.0485452000, 0.0611254000, 0.0832547000, 0.1214700000, 0.2044108000", \ - "0.0451253000, 0.0501405000, 0.0601234000, 0.0802047000, 0.1156779000, 0.1737054000, 0.2652337000", \ - "0.0376384000, 0.0455378000, 0.0617500000, 0.0930354000, 0.1494799000, 0.2401296000, 0.3816144000", \ - "-0.012318500, 0.0005128000, 0.0252296000, 0.0757589000, 0.1647423000, 0.3074239000, 0.5296493000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1356900000, 0.1446085000, 0.1648108000, 0.2115098000, 0.3176783000, 0.5634469000, 1.1358707000", \ - "0.1373178000, 0.1466216000, 0.1673091000, 0.2132666000, 0.3204332000, 0.5667798000, 1.1398100000", \ - "0.1462327000, 0.1548055000, 0.1743742000, 0.2216587000, 0.3285615000, 0.5756333000, 1.1494775000", \ - "0.1703641000, 0.1785474000, 0.1985945000, 0.2442078000, 0.3511618000, 0.5985564000, 1.1729215000", \ - "0.2353442000, 0.2429146000, 0.2617388000, 0.3066194000, 0.4108610000, 0.6573335000, 1.2312081000", \ - "0.3595005000, 0.3708046000, 0.3961974000, 0.4498268000, 0.5590686000, 0.7996722000, 1.3711582000", \ - "0.5591067000, 0.5750847000, 0.6114751000, 0.6886917000, 0.8478911000, 1.1359728000, 1.7004288000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.0146345000, 0.0164058000, 0.0204604000, 0.0295535000, 0.0500670000, 0.0975949000, 0.2094711000", \ - "0.0152782000, 0.0168570000, 0.0206312000, 0.0295673000, 0.0500683000, 0.0976050000, 0.2091581000", \ - "0.0225607000, 0.0235557000, 0.0259781000, 0.0328468000, 0.0509064000, 0.0977107000, 0.2094828000", \ - "0.0376880000, 0.0388770000, 0.0421138000, 0.0490912000, 0.0637276000, 0.1018464000, 0.2106227000", \ - "0.0644898000, 0.0665099000, 0.0711188000, 0.0807924000, 0.0999875000, 0.1360264000, 0.2230167000", \ - "0.1124852000, 0.1153853000, 0.1220879000, 0.1373841000, 0.1652545000, 0.2180183000, 0.3057372000", \ - "0.2019531000, 0.2054652000, 0.2161302000, 0.2368938000, 0.2797565000, 0.3582352000, 0.4902868000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011750600, 0.0027615300, 0.0064899300, 0.0152521000, 0.0358443000, 0.0842385000"); - values("0.1442649000, 0.1551789000, 0.1808756000, 0.2419100000, 0.3822528000, 0.7116081000, 1.4868037000", \ - "0.1439468000, 0.1549201000, 0.1809162000, 0.2413624000, 0.3822165000, 0.7116631000, 1.4832694000", \ - "0.1436412000, 0.1546878000, 0.1808909000, 0.2416785000, 0.3824074000, 0.7117368000, 1.4874136000", \ - "0.1402489000, 0.1520195000, 0.1792488000, 0.2409903000, 0.3825904000, 0.7118441000, 1.4848707000", \ - "0.1513006000, 0.1611981000, 0.1844966000, 0.2417086000, 0.3809172000, 0.7139580000, 1.4836153000", \ - "0.2013438000, 0.2131059000, 0.2395745000, 0.2928799000, 0.4102307000, 0.7165835000, 1.4855184000", \ - "0.2911164000, 0.3069654000, 0.3421179000, 0.4137134000, 0.5548010000, 0.8239130000, 1.5083282000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a311oi_4") { - leakage_power () { - value : 0.0040734000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0044586000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0019761000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0062757000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0045346000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002918000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0045388000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002918000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0063446000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002918000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0045603000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002851000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0058524000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002851000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0040741000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0058280000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0002851000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0026345000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0005775000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0056543000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0170022000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005746000; - when : "A1&A2&A3&B1&!C1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__a311oi"; - cell_leakage_power : 0.0035697990; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0084310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0182479000, 0.0182539000, 0.0182678000, 0.0182699000, 0.0182747000, 0.0182856000, 0.0183110000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013823500, -0.013826300, -0.013832800, -0.013801900, -0.013730900, -0.013567000, -0.013189300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086470000; - } - pin ("A2") { - capacitance : 0.0084220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171745000, 0.0171579000, 0.0171198000, 0.0171811000, 0.0173225000, 0.0176483000, 0.0183993000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015589600, -0.015593600, -0.015602900, -0.015600300, -0.015594300, -0.015580500, -0.015548800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087100000; - } - pin ("A3") { - capacitance : 0.0086050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156409000, 0.0156384000, 0.0156328000, 0.0156393000, 0.0156543000, 0.0156889000, 0.0157687000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015627900, -0.015626100, -0.015622000, -0.015617300, -0.015606600, -0.015582000, -0.015525100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090460000; - } - pin ("B1") { - capacitance : 0.0082960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0152723000, 0.0152723000, 0.0152722000, 0.0152684000, 0.0152595000, 0.0152391000, 0.0151920000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013922700, -0.014174600, -0.014755300, -0.014776700, -0.014826100, -0.014939900, -0.015202200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089010000; - } - pin ("C1") { - capacitance : 0.0084540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0124633000, 0.0124481000, 0.0124132000, 0.0124514000, 0.0125393000, 0.0127420000, 0.0132093000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006902700, -0.006909500, -0.006925000, -0.006922800, -0.006917500, -0.006905200, -0.006877100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092180000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1&!C1) | (!A2&!B1&!C1) | (!A3&!B1&!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0008578000, -0.000317800, -0.003336200, -0.011168300, -0.031393200, -0.082986000, -0.214131400", \ - "0.0003154000, -0.000814400, -0.003684100, -0.011363600, -0.031334900, -0.082714400, -0.213737100", \ - "-0.000319000, -0.001466000, -0.004335400, -0.011801300, -0.031419000, -0.082518700, -0.213389400", \ - "-0.001102200, -0.002237200, -0.005053200, -0.012483300, -0.031960500, -0.082681200, -0.213255800", \ - "-0.000681700, -0.001853300, -0.004843500, -0.012352400, -0.032270500, -0.082958300, -0.213338800", \ - "0.0004872000, -0.000780100, -0.004015900, -0.011757000, -0.032423000, -0.083264600, -0.213485200", \ - "0.0054757000, 0.0040362000, 0.0005324000, -0.008151700, -0.028997700, -0.080661300, -0.211610700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0503484000, 0.0517970000, 0.0550932000, 0.0633403000, 0.0841247000, 0.1357541000, 0.2658558000", \ - "0.0495996000, 0.0508227000, 0.0541733000, 0.0624807000, 0.0833580000, 0.1353645000, 0.2656508000", \ - "0.0490239000, 0.0503657000, 0.0534734000, 0.0616464000, 0.0825978000, 0.1347068000, 0.2652305000", \ - "0.0481789000, 0.0495757000, 0.0527342000, 0.0608511000, 0.0815590000, 0.1337390000, 0.2646396000", \ - "0.0479147000, 0.0491923000, 0.0523503000, 0.0605055000, 0.0805727000, 0.1324884000, 0.2635202000", \ - "0.0498873000, 0.0511372000, 0.0542456000, 0.0623653000, 0.0814286000, 0.1326597000, 0.2624962000", \ - "0.0537480000, 0.0549216000, 0.0578402000, 0.0654715000, 0.0870795000, 0.1363888000, 0.2634706000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0250242000, 0.0238331000, 0.0206891000, 0.0126905000, -0.007488000, -0.058625700, -0.189031400", \ - "0.0245845000, 0.0233476000, 0.0202164000, 0.0122534000, -0.007988200, -0.059051500, -0.189488000", \ - "0.0239322000, 0.0227507000, 0.0195969000, 0.0116367000, -0.008514700, -0.059584000, -0.190027300", \ - "0.0230824000, 0.0220443000, 0.0188997000, 0.0109409000, -0.009213200, -0.060202700, -0.190613900", \ - "0.0224819000, 0.0212656000, 0.0183191000, 0.0103945000, -0.009414100, -0.060513200, -0.191004600", \ - "0.0229003000, 0.0216821000, 0.0185372000, 0.0100336000, -0.010155400, -0.061098900, -0.191192700", \ - "0.0268217000, 0.0255332000, 0.0222853000, 0.0143559000, -0.006197800, -0.058538400, -0.190745800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0420009000, 0.0433371000, 0.0468027000, 0.0549767000, 0.0754040000, 0.1267405000, 0.2564346000", \ - "0.0412565000, 0.0426375000, 0.0461030000, 0.0545520000, 0.0751746000, 0.1267470000, 0.2566129000", \ - "0.0401984000, 0.0416039000, 0.0449272000, 0.0535792000, 0.0744083000, 0.1263740000, 0.2563197000", \ - "0.0393157000, 0.0406586000, 0.0439434000, 0.0522771000, 0.0734826000, 0.1254901000, 0.2558373000", \ - "0.0386189000, 0.0398952000, 0.0431804000, 0.0513263000, 0.0720983000, 0.1247382000, 0.2553147000", \ - "0.0384593000, 0.0397217000, 0.0429703000, 0.0509320000, 0.0712368000, 0.1231092000, 0.2535246000", \ - "0.0374234000, 0.0386555000, 0.0418632000, 0.0509727000, 0.0715348000, 0.1228240000, 0.2528161000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0267867000, 0.0255622000, 0.0224082000, 0.0144296000, -0.005783600, -0.056866900, -0.187301600", \ - "0.0263522000, 0.0251111000, 0.0219726000, 0.0139936000, -0.006213300, -0.057322100, -0.187724400", \ - "0.0258105000, 0.0245799000, 0.0214493000, 0.0134580000, -0.006711600, -0.057826100, -0.188239700", \ - "0.0253537000, 0.0241256000, 0.0209504000, 0.0129491000, -0.007252200, -0.058327400, -0.188809200", \ - "0.0248074000, 0.0235962000, 0.0204924000, 0.0127276000, -0.007437300, -0.058362400, -0.188783000", \ - "0.0243804000, 0.0231492000, 0.0200171000, 0.0121258000, -0.007989700, -0.059093300, -0.189358700", \ - "0.0268988000, 0.0256239000, 0.0224302000, 0.0143248000, -0.006211800, -0.058196200, -0.188892400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0544470000, 0.0556391000, 0.0588034000, 0.0668167000, 0.0870262000, 0.1381811000, 0.2678749000", \ - "0.0538210000, 0.0551154000, 0.0583779000, 0.0664633000, 0.0868037000, 0.1381130000, 0.2677489000", \ - "0.0530342000, 0.0543294000, 0.0576373000, 0.0657841000, 0.0863672000, 0.1377841000, 0.2677253000", \ - "0.0521597000, 0.0534857000, 0.0566972000, 0.0647903000, 0.0854863000, 0.1371818000, 0.2672112000", \ - "0.0513742000, 0.0525904000, 0.0558207000, 0.0638831000, 0.0843342000, 0.1360310000, 0.2663474000", \ - "0.0508781000, 0.0521597000, 0.0552577000, 0.0633415000, 0.0837081000, 0.1351518000, 0.2653084000", \ - "0.0492045000, 0.0506439000, 0.0541701000, 0.0624188000, 0.0830407000, 0.1342011000, 0.2640683000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0264055000, 0.0251800000, 0.0220305000, 0.0140282000, -0.006165400, -0.057256800, -0.187713000", \ - "0.0259534000, 0.0247279000, 0.0215797000, 0.0135865000, -0.006618500, -0.057713900, -0.188154600", \ - "0.0254154000, 0.0241923000, 0.0210392000, 0.0130668000, -0.007128200, -0.058197200, -0.188686800", \ - "0.0248741000, 0.0235994000, 0.0204847000, 0.0125258000, -0.007618200, -0.058692800, -0.189106300", \ - "0.0243644000, 0.0231899000, 0.0202000000, 0.0122105000, -0.007836200, -0.058935900, -0.189248000", \ - "0.0243796000, 0.0230841000, 0.0198737000, 0.0118835000, -0.008361400, -0.059302300, -0.189680800", \ - "0.0265083000, 0.0252725000, 0.0222009000, 0.0141295000, -0.006509900, -0.058276900, -0.189333500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0672641000, 0.0685461000, 0.0715614000, 0.0796262000, 0.0999053000, 0.1513402000, 0.2811157000", \ - "0.0667549000, 0.0678947000, 0.0710983000, 0.0791808000, 0.0994802000, 0.1509037000, 0.2807772000", \ - "0.0661789000, 0.0674988000, 0.0705851000, 0.0786543000, 0.0990629000, 0.1506161000, 0.2804648000", \ - "0.0654464000, 0.0667087000, 0.0699944000, 0.0780936000, 0.0985762000, 0.1501431000, 0.2801031000", \ - "0.0650040000, 0.0663043000, 0.0693974000, 0.0775180000, 0.0979292000, 0.1495863000, 0.2795036000", \ - "0.0647165000, 0.0659535000, 0.0692283000, 0.0771308000, 0.0975900000, 0.1491776000, 0.2792249000", \ - "0.0642907000, 0.0659079000, 0.0690493000, 0.0771064000, 0.0979029000, 0.1489927000, 0.2790693000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0153148000, 0.0140920000, 0.0109834000, 0.0030589000, -0.017122200, -0.068541300, -0.199485300", \ - "0.0153952000, 0.0141679000, 0.0110863000, 0.0031991000, -0.016938700, -0.068312500, -0.199228800", \ - "0.0155792000, 0.0143720000, 0.0113469000, 0.0035394000, -0.016477000, -0.067774300, -0.198598600", \ - "0.0147934000, 0.0135978000, 0.0105567000, 0.0029057000, -0.016881300, -0.067970300, -0.198685300", \ - "0.0150699000, 0.0138987000, 0.0110365000, 0.0030297000, -0.017237000, -0.068202700, -0.198637800", \ - "0.0160999000, 0.0148719000, 0.0117402000, 0.0036764000, -0.016266800, -0.067831600, -0.198821300", \ - "0.0207888000, 0.0194309000, 0.0160957000, 0.0077810000, -0.013132300, -0.064589800, -0.196973300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0569941000, 0.0583315000, 0.0615604000, 0.0697373000, 0.0903902000, 0.1419613000, 0.2719022000", \ - "0.0562318000, 0.0576043000, 0.0608096000, 0.0690975000, 0.0898394000, 0.1415954000, 0.2716976000", \ - "0.0553612000, 0.0567886000, 0.0599878000, 0.0682878000, 0.0889846000, 0.1410731000, 0.2714398000", \ - "0.0549254000, 0.0559521000, 0.0591976000, 0.0675021000, 0.0880963000, 0.1401116000, 0.2708564000", \ - "0.0541207000, 0.0553770000, 0.0586190000, 0.0666973000, 0.0871851000, 0.1391024000, 0.2697424000", \ - "0.0539734000, 0.0553090000, 0.0585394000, 0.0666531000, 0.0871396000, 0.1385379000, 0.2687761000", \ - "0.0552969000, 0.0565325000, 0.0595892000, 0.0674427000, 0.0878245000, 0.1390089000, 0.2693080000"); - } - } - max_capacitance : 0.1336770000; - max_transition : 1.5063120000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0488678000, 0.0513423000, 0.0574262000, 0.0716297000, 0.1050599000, 0.1826748000, 0.3691983000", \ - "0.0525733000, 0.0549859000, 0.0610794000, 0.0753172000, 0.1084849000, 0.1858597000, 0.3722939000", \ - "0.0622445000, 0.0645290000, 0.0703628000, 0.0845230000, 0.1174467000, 0.1949490000, 0.3814558000", \ - "0.0872649000, 0.0901937000, 0.0953725000, 0.1080483000, 0.1396295000, 0.2166485000, 0.4032173000", \ - "0.1230510000, 0.1263987000, 0.1340656000, 0.1514440000, 0.1910869000, 0.2687449000, 0.4555142000", \ - "0.1587859000, 0.1635444000, 0.1751368000, 0.2027383000, 0.2606231000, 0.3702091000, 0.5755584000", \ - "0.1744275000, 0.1814377000, 0.1984881000, 0.2371769000, 0.3227869000, 0.4907874000, 0.7967534000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1563805000, 0.1623854000, 0.1779477000, 0.2149458000, 0.3065622000, 0.5406038000, 1.1158469000", \ - "0.1592059000, 0.1655967000, 0.1811581000, 0.2192351000, 0.3116523000, 0.5420135000, 1.1227524000", \ - "0.1692710000, 0.1755485000, 0.1909114000, 0.2292860000, 0.3239665000, 0.5585182000, 1.1372518000", \ - "0.1956818000, 0.2017174000, 0.2162586000, 0.2539899000, 0.3480918000, 0.5846389000, 1.1648292000", \ - "0.2504554000, 0.2565606000, 0.2716039000, 0.3085930000, 0.4012929000, 0.6364466000, 1.2239465000", \ - "0.3432316000, 0.3506896000, 0.3683563000, 0.4117570000, 0.5120139000, 0.7452131000, 1.3318279000", \ - "0.4919491000, 0.5021320000, 0.5269341000, 0.5849557000, 0.7088336000, 0.9764580000, 1.5740073000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0642942000, 0.0667216000, 0.0731232000, 0.0889511000, 0.1286267000, 0.2281419000, 0.4822958000", \ - "0.0629897000, 0.0655187000, 0.0721624000, 0.0882598000, 0.1281279000, 0.2280593000, 0.4816657000", \ - "0.0600580000, 0.0626274000, 0.0692050000, 0.0860806000, 0.1272617000, 0.2274482000, 0.4819187000", \ - "0.0661972000, 0.0687039000, 0.0739136000, 0.0885244000, 0.1265890000, 0.2268738000, 0.4819469000", \ - "0.0879750000, 0.0909171000, 0.0985155000, 0.1150891000, 0.1513447000, 0.2359417000, 0.4809637000", \ - "0.1332531000, 0.1377069000, 0.1472155000, 0.1678122000, 0.2125493000, 0.3078181000, 0.5167494000", \ - "0.2129669000, 0.2189767000, 0.2332868000, 0.2654809000, 0.3306239000, 0.4583602000, 0.6935797000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0987303000, 0.1063269000, 0.1252075000, 0.1732189000, 0.2956135000, 0.6069655000, 1.3874751000", \ - "0.0985216000, 0.1060437000, 0.1252209000, 0.1738480000, 0.2955099000, 0.6061517000, 1.3876946000", \ - "0.0987868000, 0.1062938000, 0.1252194000, 0.1738375000, 0.2959671000, 0.6058856000, 1.3872835000", \ - "0.0992229000, 0.1064885000, 0.1255148000, 0.1734637000, 0.2968005000, 0.6059142000, 1.3888987000", \ - "0.1044735000, 0.1110437000, 0.1290946000, 0.1754413000, 0.2965647000, 0.6092953000, 1.3907459000", \ - "0.1292128000, 0.1364442000, 0.1548399000, 0.2016670000, 0.3133147000, 0.6097230000, 1.3907633000", \ - "0.1896000000, 0.1972582000, 0.2165713000, 0.2652022000, 0.3840004000, 0.6697660000, 1.4081240000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0583363000, 0.0607502000, 0.0665498000, 0.0808335000, 0.1139413000, 0.1912226000, 0.3782001000", \ - "0.0621809000, 0.0645188000, 0.0703316000, 0.0845162000, 0.1175389000, 0.1951852000, 0.3818607000", \ - "0.0705321000, 0.0729263000, 0.0785874000, 0.0925834000, 0.1257280000, 0.2029898000, 0.3898124000", \ - "0.0896481000, 0.0920633000, 0.0978238000, 0.1117180000, 0.1441593000, 0.2215531000, 0.4083248000", \ - "0.1210528000, 0.1239572000, 0.1310081000, 0.1478225000, 0.1845302000, 0.2648947000, 0.4515424000", \ - "0.1584859000, 0.1627004000, 0.1729305000, 0.1971332000, 0.2468777000, 0.3468680000, 0.5496231000", \ - "0.1749274000, 0.1812554000, 0.1960502000, 0.2328903000, 0.3088750000, 0.4581641000, 0.7305005000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.2016808000, 0.2075952000, 0.2224741000, 0.2597035000, 0.3531536000, 0.5885800000, 1.1843527000", \ - "0.2056980000, 0.2116840000, 0.2263752000, 0.2642492000, 0.3581762000, 0.5939466000, 1.1894120000", \ - "0.2163006000, 0.2219576000, 0.2377945000, 0.2757743000, 0.3706397000, 0.6072824000, 1.2037713000", \ - "0.2431016000, 0.2494416000, 0.2646807000, 0.3028549000, 0.3976204000, 0.6352823000, 1.2330410000", \ - "0.3013209000, 0.3071282000, 0.3222734000, 0.3598659000, 0.4543425000, 0.6919518000, 1.2907673000", \ - "0.4091278000, 0.4154058000, 0.4324076000, 0.4736069000, 0.5728461000, 0.8096553000, 1.4092001000", \ - "0.5937521000, 0.6018014000, 0.6233498000, 0.6746839000, 0.7929514000, 1.0590334000, 1.6645375000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0623898000, 0.0649972000, 0.0713572000, 0.0877334000, 0.1278672000, 0.2280144000, 0.4823363000", \ - "0.0618302000, 0.0643623000, 0.0708284000, 0.0870769000, 0.1275610000, 0.2278293000, 0.4822810000", \ - "0.0610134000, 0.0635002000, 0.0698296000, 0.0863694000, 0.1270223000, 0.2273061000, 0.4816265000", \ - "0.0657359000, 0.0672340000, 0.0730489000, 0.0882939000, 0.1274054000, 0.2271245000, 0.4819939000", \ - "0.0814017000, 0.0839255000, 0.0901155000, 0.1053871000, 0.1409201000, 0.2330507000, 0.4816034000", \ - "0.1205452000, 0.1236434000, 0.1309575000, 0.1491095000, 0.1888098000, 0.2769609000, 0.5018915000", \ - "0.1946674000, 0.1990669000, 0.2092340000, 0.2334684000, 0.2855511000, 0.3918737000, 0.6228866000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1361900000, 0.1437041000, 0.1630160000, 0.2135107000, 0.3399568000, 0.6558222000, 1.4643836000", \ - "0.1359617000, 0.1437915000, 0.1635550000, 0.2129001000, 0.3386400000, 0.6560743000, 1.4587374000", \ - "0.1356012000, 0.1435823000, 0.1638519000, 0.2129114000, 0.3386732000, 0.6574745000, 1.4640724000", \ - "0.1361625000, 0.1441341000, 0.1631639000, 0.2133554000, 0.3399283000, 0.6583800000, 1.4628457000", \ - "0.1376392000, 0.1453627000, 0.1642466000, 0.2135061000, 0.3384694000, 0.6562405000, 1.4642845000", \ - "0.1601317000, 0.1676535000, 0.1863963000, 0.2331518000, 0.3508233000, 0.6610542000, 1.4642078000", \ - "0.2156771000, 0.2238947000, 0.2440533000, 0.2948325000, 0.4163944000, 0.7080560000, 1.4718525000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0631078000, 0.0655039000, 0.0714893000, 0.0855871000, 0.1187631000, 0.1959788000, 0.3826303000", \ - "0.0669984000, 0.0694441000, 0.0753320000, 0.0894705000, 0.1225179000, 0.1997757000, 0.3863027000", \ - "0.0746415000, 0.0771098000, 0.0828713000, 0.0969664000, 0.1298410000, 0.2073072000, 0.3936855000", \ - "0.0893872000, 0.0919267000, 0.0978059000, 0.1116923000, 0.1443642000, 0.2215934000, 0.4080916000", \ - "0.1135096000, 0.1163070000, 0.1231289000, 0.1381195000, 0.1735394000, 0.2525448000, 0.4392056000", \ - "0.1443384000, 0.1476547000, 0.1559342000, 0.1758953000, 0.2203857000, 0.3113112000, 0.5091745000", \ - "0.1550735000, 0.1604476000, 0.1736255000, 0.2031972000, 0.2664416000, 0.3937648000, 0.6363144000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.2350132000, 0.2409919000, 0.2562064000, 0.2926868000, 0.3872503000, 0.6227362000, 1.2156343000", \ - "0.2393386000, 0.2452699000, 0.2601434000, 0.2975581000, 0.3917685000, 0.6272111000, 1.2199288000", \ - "0.2503797000, 0.2569169000, 0.2723537000, 0.3093581000, 0.4042333000, 0.6401149000, 1.2332013000", \ - "0.2777802000, 0.2833926000, 0.2977754000, 0.3372433000, 0.4320120000, 0.6680504000, 1.2611773000", \ - "0.3320967000, 0.3382956000, 0.3529216000, 0.3912828000, 0.4857279000, 0.7225510000, 1.3171453000", \ - "0.4346214000, 0.4415381000, 0.4589738000, 0.4996041000, 0.5965680000, 0.8320202000, 1.4268030000", \ - "0.6124317000, 0.6206132000, 0.6417017000, 0.6900743000, 0.8035894000, 1.0647974000, 1.6654971000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0617866000, 0.0644320000, 0.0709253000, 0.0873235000, 0.1276325000, 0.2278717000, 0.4824328000", \ - "0.0613812000, 0.0640732000, 0.0705168000, 0.0869973000, 0.1272810000, 0.2276016000, 0.4817282000", \ - "0.0607892000, 0.0634769000, 0.0699527000, 0.0863554000, 0.1270319000, 0.2271795000, 0.4819673000", \ - "0.0633916000, 0.0657712000, 0.0717337000, 0.0874764000, 0.1271339000, 0.2272251000, 0.4819120000", \ - "0.0747971000, 0.0771746000, 0.0833352000, 0.0985025000, 0.1360713000, 0.2312200000, 0.4820278000", \ - "0.1062329000, 0.1089597000, 0.1151366000, 0.1306159000, 0.1685841000, 0.2608121000, 0.4962817000", \ - "0.1746281000, 0.1776451000, 0.1860757000, 0.2061829000, 0.2490425000, 0.3480058000, 0.5793963000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1680328000, 0.1760034000, 0.1950017000, 0.2448870000, 0.3696960000, 0.6860447000, 1.4885457000", \ - "0.1680445000, 0.1752871000, 0.1949774000, 0.2451478000, 0.3698307000, 0.6855891000, 1.4837753000", \ - "0.1677601000, 0.1758873000, 0.1950540000, 0.2447668000, 0.3696535000, 0.6860037000, 1.4887528000", \ - "0.1677154000, 0.1755487000, 0.1953685000, 0.2449682000, 0.3696177000, 0.6867086000, 1.4853406000", \ - "0.1684707000, 0.1764267000, 0.1956589000, 0.2449680000, 0.3697510000, 0.6863060000, 1.4868835000", \ - "0.1894958000, 0.1972158000, 0.2157097000, 0.2609025000, 0.3798910000, 0.6899906000, 1.4893831000", \ - "0.2409591000, 0.2499523000, 0.2692036000, 0.3186222000, 0.4416443000, 0.7362870000, 1.5016677000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0215046000, 0.0224084000, 0.0246530000, 0.0301297000, 0.0431420000, 0.0745707000, 0.1524245000", \ - "0.0261860000, 0.0271050000, 0.0293116000, 0.0347317000, 0.0477498000, 0.0791595000, 0.1570193000", \ - "0.0369388000, 0.0379713000, 0.0404320000, 0.0458192000, 0.0585813000, 0.0899349000, 0.1677929000", \ - "0.0508484000, 0.0524016000, 0.0561392000, 0.0646017000, 0.0816388000, 0.1150108000, 0.1927282000", \ - "0.0637769000, 0.0662072000, 0.0718880000, 0.0850228000, 0.1123976000, 0.1632790000, 0.2515236000", \ - "0.0648364000, 0.0686074000, 0.0776757000, 0.0982529000, 0.1409893000, 0.2211002000, 0.3575760000", \ - "0.0244452000, 0.0300998000, 0.0436056000, 0.0761432000, 0.1430676000, 0.2677561000, 0.4826467000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.2120221000, 0.2185210000, 0.2342746000, 0.2719610000, 0.3679606000, 0.6044460000, 1.1979679000", \ - "0.2134510000, 0.2202231000, 0.2365632000, 0.2749462000, 0.3711414000, 0.6080728000, 1.2024263000", \ - "0.2232807000, 0.2290670000, 0.2440750000, 0.2832981000, 0.3795209000, 0.6175725000, 1.2130319000", \ - "0.2482929000, 0.2546675000, 0.2695271000, 0.3081799000, 0.4030623000, 0.6414376000, 1.2377815000", \ - "0.3055868000, 0.3114678000, 0.3266649000, 0.3645531000, 0.4595568000, 0.6969351000, 1.2930871000", \ - "0.4222704000, 0.4292881000, 0.4485174000, 0.4921543000, 0.5929791000, 0.8293419000, 1.4249317000", \ - "0.6319977000, 0.6417561000, 0.6665805000, 0.7230948000, 0.8545076000, 1.1301841000, 1.7345201000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0232943000, 0.0242558000, 0.0267099000, 0.0330344000, 0.0490323000, 0.0896912000, 0.1940245000", \ - "0.0228012000, 0.0237462000, 0.0261770000, 0.0326710000, 0.0488935000, 0.0897723000, 0.1940397000", \ - "0.0267938000, 0.0275396000, 0.0294914000, 0.0349221000, 0.0494843000, 0.0896693000, 0.1940240000", \ - "0.0407777000, 0.0416960000, 0.0440297000, 0.0494650000, 0.0618609000, 0.0950264000, 0.1949086000", \ - "0.0666100000, 0.0679401000, 0.0714451000, 0.0788689000, 0.0954047000, 0.1295755000, 0.2103719000", \ - "0.1128428000, 0.1148467000, 0.1197645000, 0.1312794000, 0.1560704000, 0.2052011000, 0.2948084000", \ - "0.1957642000, 0.1986696000, 0.2077424000, 0.2249575000, 0.2639129000, 0.3375902000, 0.4680721000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1676743000, 0.1757843000, 0.1950800000, 0.2447386000, 0.3697265000, 0.6870969000, 1.4905567000", \ - "0.1680442000, 0.1754410000, 0.1950111000, 0.2445594000, 0.3696182000, 0.6853371000, 1.4892991000", \ - "0.1678387000, 0.1755280000, 0.1954366000, 0.2449307000, 0.3698248000, 0.6854152000, 1.4843156000", \ - "0.1683687000, 0.1753575000, 0.1950983000, 0.2453054000, 0.3700480000, 0.6858760000, 1.4851756000", \ - "0.1719125000, 0.1791662000, 0.1980633000, 0.2458088000, 0.3703178000, 0.6859871000, 1.4854906000", \ - "0.2092759000, 0.2167165000, 0.2348065000, 0.2780953000, 0.3898851000, 0.6922632000, 1.4884124000", \ - "0.2973402000, 0.3058401000, 0.3268106000, 0.3749273000, 0.4969037000, 0.7622571000, 1.4986602000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0160744000, 0.0168380000, 0.0187500000, 0.0233902000, 0.0348644000, 0.0632303000, 0.1349742000", \ - "0.0206649000, 0.0214392000, 0.0233396000, 0.0280523000, 0.0395470000, 0.0680824000, 0.1398731000", \ - "0.0281207000, 0.0292876000, 0.0322072000, 0.0386905000, 0.0504885000, 0.0790825000, 0.1509921000", \ - "0.0359970000, 0.0377325000, 0.0423982000, 0.0522271000, 0.0713434000, 0.1051961000, 0.1764670000", \ - "0.0393223000, 0.0424410000, 0.0497700000, 0.0656100000, 0.0953921000, 0.1487661000, 0.2362350000", \ - "0.0255779000, 0.0305262000, 0.0421577000, 0.0668611000, 0.1158696000, 0.2000549000, 0.3359774000", \ - "-0.038276100, -0.030532900, -0.012158200, 0.0274139000, 0.1046526000, 0.2375244000, 0.4534674000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1571997000, 0.1638106000, 0.1797607000, 0.2182234000, 0.3147806000, 0.5515737000, 1.1454279000", \ - "0.1589601000, 0.1653352000, 0.1798942000, 0.2200443000, 0.3163696000, 0.5540772000, 1.1486615000", \ - "0.1673128000, 0.1734039000, 0.1893071000, 0.2276787000, 0.3231948000, 0.5621273000, 1.1583849000", \ - "0.1909087000, 0.1970999000, 0.2120756000, 0.2508797000, 0.3463476000, 0.5846899000, 1.1811050000", \ - "0.2548001000, 0.2606929000, 0.2754409000, 0.3130974000, 0.4051673000, 0.6427147000, 1.2384205000", \ - "0.3916338000, 0.3990377000, 0.4172682000, 0.4607675000, 0.5563112000, 0.7889819000, 1.3813085000", \ - "0.6140679000, 0.6246171000, 0.6512109000, 0.7140116000, 0.8518101000, 1.1334320000, 1.7116903000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0131818000, 0.0142435000, 0.0169581000, 0.0236039000, 0.0393716000, 0.0777029000, 0.1747876000", \ - "0.0139800000, 0.0149194000, 0.0173370000, 0.0236350000, 0.0393506000, 0.0777084000, 0.1746595000", \ - "0.0216164000, 0.0222769000, 0.0238501000, 0.0283220000, 0.0413101000, 0.0777422000, 0.1744993000", \ - "0.0360588000, 0.0368754000, 0.0390696000, 0.0443863000, 0.0562240000, 0.0852993000, 0.1747536000", \ - "0.0624100000, 0.0635472000, 0.0664274000, 0.0737452000, 0.0898957000, 0.1223775000, 0.1954094000", \ - "0.1104722000, 0.1122214000, 0.1164794000, 0.1270586000, 0.1494168000, 0.1952438000, 0.2814634000", \ - "0.1990663000, 0.2026676000, 0.2085408000, 0.2240477000, 0.2576419000, 0.3275623000, 0.4513428000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1676203000, 0.1756265000, 0.1949993000, 0.2445718000, 0.3697194000, 0.6856879000, 1.4904182000", \ - "0.1673820000, 0.1749541000, 0.1950531000, 0.2444932000, 0.3696342000, 0.6855956000, 1.4847332000", \ - "0.1673969000, 0.1752351000, 0.1944790000, 0.2444298000, 0.3698748000, 0.6859224000, 1.4896759000", \ - "0.1655348000, 0.1732390000, 0.1935075000, 0.2437925000, 0.3701569000, 0.6870436000, 1.4850603000", \ - "0.1705960000, 0.1776360000, 0.1959569000, 0.2428996000, 0.3677536000, 0.6858802000, 1.4855808000", \ - "0.2198587000, 0.2280260000, 0.2480708000, 0.2922563000, 0.3967172000, 0.6901822000, 1.4851352000", \ - "0.3101674000, 0.3210235000, 0.3469900000, 0.4059959000, 0.5334748000, 0.7978961000, 1.5063120000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31o_1") { - leakage_power () { - value : 0.0021170000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0026581000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0026784000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0026775000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0031168000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0026821000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0030257000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0021170000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0030004000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0014963000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0018432000; - when : "A1&A2&A3&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a31o"; - cell_leakage_power : 0.0023748210; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045228000, 0.0045243000, 0.0045278000, 0.0045292000, 0.0045326000, 0.0045403000, 0.0045581000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003504300, -0.003507400, -0.003514500, -0.003507300, -0.003490600, -0.003452200, -0.003363600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024200000; - } - pin ("A2") { - capacitance : 0.0023720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043842000, 0.0043824000, 0.0043783000, 0.0043929000, 0.0044264000, 0.0045038000, 0.0046820000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003983300, -0.003984100, -0.003986000, -0.003984900, -0.003982300, -0.003976400, -0.003962600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024650000; - } - pin ("A3") { - capacitance : 0.0023830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042353000, 0.0042334000, 0.0042290000, 0.0042311000, 0.0042359000, 0.0042470000, 0.0042726000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004234200, -0.004233400, -0.004231700, -0.004231800, -0.004232000, -0.004232500, -0.004233700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025070000; - } - pin ("B1") { - capacitance : 0.0023210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042833000, 0.0042765000, 0.0042607000, 0.0042777000, 0.0043167000, 0.0044068000, 0.0046144000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001710300, -0.001709300, -0.001707200, -0.001707100, -0.001706900, -0.001706600, -0.001705700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024900000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0109134000, 0.0100362000, 0.0075236000, -0.000295600, -0.023146800, -0.084326000, -0.244653700", \ - "0.0107707000, 0.0098678000, 0.0073563000, -0.000487500, -0.023344400, -0.084495700, -0.244824700", \ - "0.0104909000, 0.0096025000, 0.0070920000, -0.000766000, -0.023616400, -0.084773400, -0.245081100", \ - "0.0102314000, 0.0093403000, 0.0067959000, -0.001047800, -0.023874100, -0.085037600, -0.245346100", \ - "0.0100042000, 0.0090818000, 0.0065344000, -0.001354900, -0.024164500, -0.085272300, -0.245552800", \ - "0.0111592000, 0.0098699000, 0.0065315000, -0.001863600, -0.024296300, -0.085348200, -0.245626400", \ - "0.0123088000, 0.0109873000, 0.0075580000, -0.001247400, -0.024539200, -0.085250300, -0.245453800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0130454000, 0.0144466000, 0.0179878000, 0.0269336000, 0.0501471000, 0.1112721000, 0.2707150000", \ - "0.0129259000, 0.0143390000, 0.0178925000, 0.0268526000, 0.0500505000, 0.1107656000, 0.2693049000", \ - "0.0127270000, 0.0141319000, 0.0176924000, 0.0266903000, 0.0499078000, 0.1110533000, 0.2704618000", \ - "0.0124956000, 0.0139212000, 0.0174787000, 0.0264719000, 0.0496648000, 0.1103750000, 0.2691484000", \ - "0.0123981000, 0.0137827000, 0.0173505000, 0.0261822000, 0.0495028000, 0.1105815000, 0.2699301000", \ - "0.0130524000, 0.0143783000, 0.0177842000, 0.0265479000, 0.0498434000, 0.1101029000, 0.2689422000", \ - "0.0140946000, 0.0154627000, 0.0189862000, 0.0277362000, 0.0506361000, 0.1115648000, 0.2682191000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0134915000, 0.0125783000, 0.0101045000, 0.0023467000, -0.020354600, -0.081405700, -0.241667900", \ - "0.0133115000, 0.0124302000, 0.0099551000, 0.0022015000, -0.020473700, -0.081529400, -0.241797200", \ - "0.0131392000, 0.0122350000, 0.0097345000, 0.0019875000, -0.020722600, -0.081768300, -0.242012800", \ - "0.0128854000, 0.0119665000, 0.0094992000, 0.0017306000, -0.020967800, -0.082002000, -0.242245700", \ - "0.0127002000, 0.0117662000, 0.0092379000, 0.0014796000, -0.021226000, -0.082239100, -0.242394800", \ - "0.0132950000, 0.0120200000, 0.0085850000, 0.0010586000, -0.021477100, -0.082414000, -0.242597700", \ - "0.0149874000, 0.0136154000, 0.0102238000, 0.0013750000, -0.021898400, -0.082570900, -0.242669600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0134923000, 0.0149027000, 0.0184188000, 0.0273339000, 0.0504256000, 0.1113645000, 0.2703565000", \ - "0.0133874000, 0.0147935000, 0.0183260000, 0.0272501000, 0.0503255000, 0.1113028000, 0.2706523000", \ - "0.0132374000, 0.0146254000, 0.0181840000, 0.0271156000, 0.0502179000, 0.1112214000, 0.2705517000", \ - "0.0130134000, 0.0144000000, 0.0179696000, 0.0269210000, 0.0500308000, 0.1106617000, 0.2691070000", \ - "0.0128453000, 0.0142588000, 0.0177993000, 0.0268161000, 0.0500134000, 0.1110138000, 0.2696666000", \ - "0.0131956000, 0.0145451000, 0.0179685000, 0.0267225000, 0.0500494000, 0.1102026000, 0.2688152000", \ - "0.0140275000, 0.0152938000, 0.0187930000, 0.0275760000, 0.0509000000, 0.1118465000, 0.2697557000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0161312000, 0.0151992000, 0.0126518000, 0.0048424000, -0.018028200, -0.079224300, -0.239527400", \ - "0.0160161000, 0.0150717000, 0.0125247000, 0.0047050000, -0.018148100, -0.079342700, -0.239636100", \ - "0.0158900000, 0.0149294000, 0.0124066000, 0.0045571000, -0.018328600, -0.079499500, -0.239796300", \ - "0.0156422000, 0.0147117000, 0.0121734000, 0.0043269000, -0.018505300, -0.079680800, -0.239917400", \ - "0.0154583000, 0.0145195000, 0.0119857000, 0.0041209000, -0.018686700, -0.079794700, -0.240001100", \ - "0.0158754000, 0.0145718000, 0.0114033000, 0.0039106000, -0.018750100, -0.079796600, -0.240040100", \ - "0.0181641000, 0.0167975000, 0.0133820000, 0.0044249000, -0.018895500, -0.079677700, -0.239847500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0136789000, 0.0150815000, 0.0186239000, 0.0275162000, 0.0504486000, 0.1112450000, 0.2704290000", \ - "0.0135815000, 0.0149864000, 0.0185315000, 0.0274280000, 0.0503741000, 0.1110578000, 0.2702358000", \ - "0.0134145000, 0.0148193000, 0.0183585000, 0.0272591000, 0.0502371000, 0.1109440000, 0.2696357000", \ - "0.0131781000, 0.0145889000, 0.0181302000, 0.0270452000, 0.0501031000, 0.1109615000, 0.2687853000", \ - "0.0130117000, 0.0143952000, 0.0179235000, 0.0268790000, 0.0501860000, 0.1104303000, 0.2687321000", \ - "0.0132682000, 0.0146091000, 0.0180483000, 0.0268110000, 0.0500703000, 0.1102404000, 0.2700524000", \ - "0.0138561000, 0.0151688000, 0.0186105000, 0.0275124000, 0.0507984000, 0.1114761000, 0.2684744000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0132759000, 0.0123542000, 0.0099282000, 0.0020559000, -0.020706000, -0.081736800, -0.241975800", \ - "0.0130785000, 0.0121461000, 0.0096790000, 0.0018770000, -0.020879000, -0.081909900, -0.242138100", \ - "0.0128971000, 0.0119980000, 0.0094468000, 0.0016161000, -0.021101400, -0.082157200, -0.242302900", \ - "0.0127060000, 0.0117885000, 0.0092650000, 0.0014467000, -0.021293100, -0.082307700, -0.242472900", \ - "0.0125793000, 0.0116469000, 0.0090904000, 0.0012609000, -0.021465400, -0.082436400, -0.242600800", \ - "0.0140729000, 0.0127345000, 0.0093006000, 0.0012895000, -0.021258100, -0.082210500, -0.242356500", \ - "0.0175164000, 0.0161049000, 0.0126126000, 0.0037191000, -0.019644500, -0.080411900, -0.240553300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0086751000, 0.0101377000, 0.0137997000, 0.0228902000, 0.0464389000, 0.1072141000, 0.2653896000", \ - "0.0085825000, 0.0100361000, 0.0136832000, 0.0227961000, 0.0463303000, 0.1065248000, 0.2651680000", \ - "0.0083464000, 0.0097721000, 0.0133800000, 0.0225005000, 0.0461279000, 0.1067353000, 0.2651812000", \ - "0.0079939000, 0.0093835000, 0.0129531000, 0.0220585000, 0.0457201000, 0.1067123000, 0.2669209000", \ - "0.0080650000, 0.0094131000, 0.0127807000, 0.0218539000, 0.0451549000, 0.1067510000, 0.2655308000", \ - "0.0084111000, 0.0097320000, 0.0131844000, 0.0222065000, 0.0455785000, 0.1057846000, 0.2647160000", \ - "0.0101733000, 0.0113677000, 0.0147515000, 0.0237695000, 0.0470358000, 0.1080590000, 0.2652037000"); - } - } - max_capacitance : 0.1602270000; - max_transition : 1.5021620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1381343000, 0.1447753000, 0.1585197000, 0.1859716000, 0.2416238000, 0.3682428000, 0.6909207000", \ - "0.1428928000, 0.1495243000, 0.1634435000, 0.1906860000, 0.2464237000, 0.3730734000, 0.6954657000", \ - "0.1551251000, 0.1617570000, 0.1756710000, 0.2028646000, 0.2586294000, 0.3852501000, 0.7072738000", \ - "0.1840785000, 0.1907597000, 0.2045317000, 0.2318520000, 0.2875931000, 0.4142417000, 0.7363095000", \ - "0.2464951000, 0.2532904000, 0.2673397000, 0.2948746000, 0.3507172000, 0.4774676000, 0.7998964000", \ - "0.3567638000, 0.3646534000, 0.3808203000, 0.4114758000, 0.4715632000, 0.6010271000, 0.9238269000", \ - "0.5356320000, 0.5457075000, 0.5661604000, 0.6041047000, 0.6727286000, 0.8084461000, 1.1325216000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0917325000, 0.0994441000, 0.1164929000, 0.1549714000, 0.2499468000, 0.4965977000, 1.1376391000", \ - "0.0954001000, 0.1031306000, 0.1202331000, 0.1587457000, 0.2534747000, 0.4990832000, 1.1415801000", \ - "0.1046673000, 0.1123581000, 0.1295017000, 0.1681356000, 0.2632335000, 0.5099436000, 1.1510026000", \ - "0.1266301000, 0.1343593000, 0.1514258000, 0.1900543000, 0.2850358000, 0.5308045000, 1.1725108000", \ - "0.1627875000, 0.1707565000, 0.1882449000, 0.2272447000, 0.3226541000, 0.5694859000, 1.2131798000", \ - "0.2039179000, 0.2125951000, 0.2311094000, 0.2711328000, 0.3664418000, 0.6133046000, 1.2557896000", \ - "0.2274339000, 0.2392450000, 0.2617210000, 0.3042591000, 0.3989150000, 0.6449806000, 1.2875871000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0224411000, 0.0276033000, 0.0380837000, 0.0626801000, 0.1206471000, 0.2757691000, 0.7010983000", \ - "0.0225169000, 0.0272004000, 0.0383774000, 0.0626573000, 0.1208351000, 0.2767609000, 0.7017133000", \ - "0.0225430000, 0.0276789000, 0.0380784000, 0.0625623000, 0.1208387000, 0.2777838000, 0.6966009000", \ - "0.0228543000, 0.0273639000, 0.0384929000, 0.0626672000, 0.1208083000, 0.2767475000, 0.6998405000", \ - "0.0239195000, 0.0289683000, 0.0389806000, 0.0635759000, 0.1208514000, 0.2767299000, 0.7011454000", \ - "0.0296230000, 0.0347615000, 0.0467760000, 0.0715866000, 0.1282333000, 0.2796720000, 0.7042514000", \ - "0.0415129000, 0.0479687000, 0.0613214000, 0.0877780000, 0.1450478000, 0.2889598000, 0.6998724000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0260670000, 0.0334204000, 0.0517989000, 0.1000562000, 0.2314817000, 0.5800165000, 1.4947968000", \ - "0.0261108000, 0.0333863000, 0.0518359000, 0.1001041000, 0.2310543000, 0.5801313000, 1.4954421000", \ - "0.0260937000, 0.0333427000, 0.0517520000, 0.1000308000, 0.2313967000, 0.5802702000, 1.4954611000", \ - "0.0261605000, 0.0335390000, 0.0516838000, 0.0999224000, 0.2314929000, 0.5792447000, 1.4906214000", \ - "0.0278306000, 0.0351268000, 0.0532765000, 0.1015257000, 0.2318733000, 0.5804636000, 1.4947775000", \ - "0.0339297000, 0.0406509000, 0.0570018000, 0.1029142000, 0.2334096000, 0.5802281000, 1.4922559000", \ - "0.0458234000, 0.0529044000, 0.0692920000, 0.1096978000, 0.2343018000, 0.5812807000, 1.4917103000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1666367000, 0.1737012000, 0.1882312000, 0.2169244000, 0.2736789000, 0.4015466000, 0.7246655000", \ - "0.1715987000, 0.1786489000, 0.1932927000, 0.2214681000, 0.2787613000, 0.4066676000, 0.7290258000", \ - "0.1841035000, 0.1911173000, 0.2056805000, 0.2343283000, 0.2912083000, 0.4190874000, 0.7419693000", \ - "0.2128273000, 0.2198584000, 0.2344747000, 0.2628424000, 0.3200306000, 0.4478999000, 0.7709434000", \ - "0.2759773000, 0.2829894000, 0.2974933000, 0.3260664000, 0.3832897000, 0.5113501000, 0.8343221000", \ - "0.3957523000, 0.4037595000, 0.4200178000, 0.4511188000, 0.5111765000, 0.6408334000, 0.9641030000", \ - "0.5966969000, 0.6067598000, 0.6267635000, 0.6639515000, 0.7312874000, 0.8666600000, 1.1913178000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0993331000, 0.1070584000, 0.1241375000, 0.1624241000, 0.2567632000, 0.5024695000, 1.1458398000", \ - "0.1032838000, 0.1110002000, 0.1280504000, 0.1664201000, 0.2609068000, 0.5070118000, 1.1478422000", \ - "0.1120850000, 0.1197755000, 0.1368789000, 0.1752089000, 0.2698153000, 0.5159632000, 1.1569445000", \ - "0.1320033000, 0.1396034000, 0.1567086000, 0.1952230000, 0.2898998000, 0.5353413000, 1.1770985000", \ - "0.1677929000, 0.1759745000, 0.1932377000, 0.2324920000, 0.3277608000, 0.5740558000, 1.2171403000", \ - "0.2123982000, 0.2215826000, 0.2408048000, 0.2812785000, 0.3770672000, 0.6230846000, 1.2661080000", \ - "0.2420628000, 0.2538506000, 0.2771139000, 0.3211441000, 0.4177052000, 0.6637180000, 1.3055189000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0253029000, 0.0300909000, 0.0405903000, 0.0653058000, 0.1239455000, 0.2783343000, 0.7038088000", \ - "0.0249492000, 0.0301347000, 0.0406336000, 0.0655653000, 0.1234935000, 0.2783377000, 0.7072667000", \ - "0.0251097000, 0.0301890000, 0.0406165000, 0.0651852000, 0.1236918000, 0.2785302000, 0.7044494000", \ - "0.0253019000, 0.0300637000, 0.0405877000, 0.0655181000, 0.1236395000, 0.2784526000, 0.7048771000", \ - "0.0253558000, 0.0304029000, 0.0408689000, 0.0658470000, 0.1235407000, 0.2781772000, 0.7000212000", \ - "0.0303585000, 0.0354689000, 0.0471601000, 0.0711991000, 0.1277829000, 0.2810251000, 0.7050189000", \ - "0.0416439000, 0.0476047000, 0.0599175000, 0.0863829000, 0.1428099000, 0.2884786000, 0.7020173000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0261008000, 0.0333445000, 0.0518186000, 0.1001854000, 0.2308484000, 0.5812245000, 1.4949660000", \ - "0.0260736000, 0.0333350000, 0.0517940000, 0.1000941000, 0.2314631000, 0.5807047000, 1.4956045000", \ - "0.0259888000, 0.0334304000, 0.0518369000, 0.1000614000, 0.2314627000, 0.5805894000, 1.4954294000", \ - "0.0259974000, 0.0336664000, 0.0517328000, 0.0999568000, 0.2314706000, 0.5802231000, 1.4911645000", \ - "0.0282325000, 0.0355351000, 0.0538396000, 0.1013373000, 0.2316861000, 0.5806914000, 1.4924358000", \ - "0.0337006000, 0.0412790000, 0.0578407000, 0.1033890000, 0.2324162000, 0.5786043000, 1.4958200000", \ - "0.0456954000, 0.0529588000, 0.0707816000, 0.1112325000, 0.2344978000, 0.5839777000, 1.4907261000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1768402000, 0.1838228000, 0.1983429000, 0.2260869000, 0.2826010000, 0.4101365000, 0.7335192000", \ - "0.1821182000, 0.1891311000, 0.2036079000, 0.2317706000, 0.2878988000, 0.4154408000, 0.7388255000", \ - "0.1950702000, 0.2021132000, 0.2165620000, 0.2447428000, 0.3010780000, 0.4286586000, 0.7514129000", \ - "0.2242350000, 0.2312127000, 0.2456710000, 0.2736928000, 0.3301702000, 0.4578059000, 0.7812604000", \ - "0.2867720000, 0.2937723000, 0.3082730000, 0.3365341000, 0.3932205000, 0.5207626000, 0.8438528000", \ - "0.4097486000, 0.4176053000, 0.4335461000, 0.4639903000, 0.5231749000, 0.6521261000, 0.9753981000", \ - "0.6191535000, 0.6288975000, 0.6482322000, 0.6840133000, 0.7498333000, 0.8837358000, 1.2081520000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1042957000, 0.1120295000, 0.1290775000, 0.1673452000, 0.2612812000, 0.5066648000, 1.1470258000", \ - "0.1083653000, 0.1160166000, 0.1331142000, 0.1712886000, 0.2652867000, 0.5105172000, 1.1536668000", \ - "0.1163150000, 0.1239668000, 0.1410521000, 0.1792481000, 0.2733474000, 0.5186662000, 1.1617850000", \ - "0.1327450000, 0.1404615000, 0.1575219000, 0.1957656000, 0.2901288000, 0.5358431000, 1.1765028000", \ - "0.1628836000, 0.1710480000, 0.1886987000, 0.2278513000, 0.3226994000, 0.5678827000, 1.2093939000", \ - "0.2036045000, 0.2128668000, 0.2321918000, 0.2727305000, 0.3685676000, 0.6139668000, 1.2571916000", \ - "0.2308632000, 0.2426603000, 0.2663394000, 0.3110771000, 0.4082544000, 0.6547297000, 1.2953495000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0257396000, 0.0303393000, 0.0414742000, 0.0657640000, 0.1238989000, 0.2789564000, 0.7032578000", \ - "0.0256071000, 0.0302251000, 0.0414685000, 0.0650221000, 0.1238698000, 0.2789636000, 0.7032827000", \ - "0.0259700000, 0.0302951000, 0.0410923000, 0.0654518000, 0.1235751000, 0.2782125000, 0.7022209000", \ - "0.0256886000, 0.0303049000, 0.0414767000, 0.0657800000, 0.1236057000, 0.2790163000, 0.7041571000", \ - "0.0256005000, 0.0303341000, 0.0410490000, 0.0658095000, 0.1233708000, 0.2785693000, 0.7005436000", \ - "0.0303192000, 0.0352410000, 0.0467883000, 0.0701091000, 0.1271446000, 0.2799248000, 0.7055184000", \ - "0.0407934000, 0.0464855000, 0.0581720000, 0.0833314000, 0.1402063000, 0.2877211000, 0.7013425000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0260408000, 0.0334434000, 0.0517943000, 0.1001086000, 0.2314682000, 0.5809210000, 1.4956146000", \ - "0.0260850000, 0.0333980000, 0.0517575000, 0.1000670000, 0.2314643000, 0.5800441000, 1.4929963000", \ - "0.0260758000, 0.0333781000, 0.0517090000, 0.0999340000, 0.2315149000, 0.5801281000, 1.4927529000", \ - "0.0261176000, 0.0334843000, 0.0518660000, 0.1001334000, 0.2312577000, 0.5796967000, 1.4942078000", \ - "0.0282375000, 0.0353751000, 0.0536138000, 0.1010628000, 0.2313054000, 0.5810487000, 1.4949333000", \ - "0.0334105000, 0.0406110000, 0.0579163000, 0.1038917000, 0.2324079000, 0.5778446000, 1.4961480000", \ - "0.0446499000, 0.0524751000, 0.0697124000, 0.1119172000, 0.2353616000, 0.5821150000, 1.4909257000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1505266000, 0.1575611000, 0.1719639000, 0.2004206000, 0.2568508000, 0.3847037000, 0.7074489000", \ - "0.1537311000, 0.1606911000, 0.1754665000, 0.2038207000, 0.2603525000, 0.3881854000, 0.7109897000", \ - "0.1639964000, 0.1710062000, 0.1854419000, 0.2136407000, 0.2700741000, 0.3980145000, 0.7213014000", \ - "0.1911618000, 0.1981868000, 0.2125917000, 0.2409096000, 0.2977197000, 0.4255451000, 0.7491393000", \ - "0.2579638000, 0.2649248000, 0.2793483000, 0.3075704000, 0.3643107000, 0.4922220000, 0.8151690000", \ - "0.3840470000, 0.3922972000, 0.4087518000, 0.4387774000, 0.4975723000, 0.6273834000, 0.9508681000", \ - "0.5812459000, 0.5922263000, 0.6133621000, 0.6503625000, 0.7131781000, 0.8452235000, 1.1709567000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0556523000, 0.0628784000, 0.0790102000, 0.1164773000, 0.2111763000, 0.4575290000, 1.0984124000", \ - "0.0604416000, 0.0676382000, 0.0836916000, 0.1212135000, 0.2161269000, 0.4638312000, 1.1062919000", \ - "0.0712625000, 0.0783756000, 0.0943269000, 0.1318772000, 0.2266560000, 0.4770052000, 1.1146947000", \ - "0.0919993000, 0.0994337000, 0.1156622000, 0.1531307000, 0.2484379000, 0.4958223000, 1.1409063000", \ - "0.1194355000, 0.1282268000, 0.1460030000, 0.1843807000, 0.2794397000, 0.5271203000, 1.1721560000", \ - "0.1463603000, 0.1581747000, 0.1801376000, 0.2212274000, 0.3165675000, 0.5625762000, 1.2044946000", \ - "0.1523472000, 0.1685282000, 0.1980184000, 0.2481255000, 0.3454478000, 0.5920681000, 1.2349046000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0255102000, 0.0302795000, 0.0410972000, 0.0653047000, 0.1236762000, 0.2781317000, 0.7025733000", \ - "0.0257522000, 0.0303352000, 0.0410828000, 0.0654257000, 0.1233052000, 0.2785023000, 0.7025288000", \ - "0.0257979000, 0.0308112000, 0.0409341000, 0.0649287000, 0.1236268000, 0.2789266000, 0.7064289000", \ - "0.0255007000, 0.0304577000, 0.0412170000, 0.0654888000, 0.1234188000, 0.2788693000, 0.7043858000", \ - "0.0256705000, 0.0303392000, 0.0409627000, 0.0656287000, 0.1234049000, 0.2784383000, 0.6991248000", \ - "0.0341846000, 0.0388272000, 0.0481630000, 0.0712019000, 0.1273426000, 0.2808705000, 0.7051755000", \ - "0.0491499000, 0.0541509000, 0.0649801000, 0.0858391000, 0.1375872000, 0.2859725000, 0.7025301000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0222080000, 0.0289900000, 0.0468172000, 0.0958913000, 0.2296172000, 0.5793446000, 1.4899613000", \ - "0.0222061000, 0.0290069000, 0.0467715000, 0.0959832000, 0.2295212000, 0.5813563000, 1.4919799000", \ - "0.0223382000, 0.0291678000, 0.0468827000, 0.0960015000, 0.2294698000, 0.5808047000, 1.4906015000", \ - "0.0248676000, 0.0310555000, 0.0480699000, 0.0961771000, 0.2295221000, 0.5824449000, 1.5021618000", \ - "0.0321913000, 0.0377375000, 0.0525749000, 0.0981907000, 0.2287860000, 0.5810967000, 1.4981243000", \ - "0.0455731000, 0.0515323000, 0.0639972000, 0.1036429000, 0.2306549000, 0.5766865000, 1.4907284000", \ - "0.0656492000, 0.0730171000, 0.0855130000, 0.1200638000, 0.2344055000, 0.5801294000, 1.4895813000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31o_2") { - leakage_power () { - value : 0.0025386000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0035004000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0025382000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0038532000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0025386000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0038419000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0009570000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0021622000; - when : "A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0025386000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0034749000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0025386000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0034955000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0025386000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0034959000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0025391000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0039408000; - when : "!A1&A2&A3&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a31o"; - cell_leakage_power : 0.0029057600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046520000, 0.0046511000, 0.0046491000, 0.0046503000, 0.0046529000, 0.0046589000, 0.0046728000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003647500, -0.003649000, -0.003652500, -0.003645600, -0.003629500, -0.003592400, -0.003506800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024580000; - } - pin ("A2") { - capacitance : 0.0023480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043208000, 0.0043160000, 0.0043050000, 0.0043204000, 0.0043560000, 0.0044381000, 0.0046272000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003876000, -0.003877300, -0.003880300, -0.003879400, -0.003877200, -0.003872100, -0.003860400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024450000; - } - pin ("A3") { - capacitance : 0.0023730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042154000, 0.0042148000, 0.0042135000, 0.0042146000, 0.0042170000, 0.0042226000, 0.0042354000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004211700, -0.004210300, -0.004207100, -0.004207200, -0.004207400, -0.004207900, -0.004209000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025070000; - } - pin ("B1") { - capacitance : 0.0023260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024701000, 0.0024612000, 0.0024408000, 0.0024562000, 0.0024917000, 0.0025735000, 0.0027621000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001751700, -0.001748000, -0.001739500, -0.001738200, -0.001735400, -0.001728900, -0.001713800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025040000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0139761000, 0.0125656000, 0.0091473000, -0.001116800, -0.034471700, -0.134088100, -0.420365000", \ - "0.0138147000, 0.0124508000, 0.0090002000, -0.001261900, -0.034563600, -0.134194300, -0.420431200", \ - "0.0135092000, 0.0121990000, 0.0087599000, -0.001530400, -0.034824100, -0.134446200, -0.420682400", \ - "0.0132548000, 0.0118580000, 0.0084538000, -0.001901800, -0.035227800, -0.134798300, -0.421040500", \ - "0.0130372000, 0.0116441000, 0.0081608000, -0.002189400, -0.035568900, -0.135150100, -0.421291000", \ - "0.0134658000, 0.0119289000, 0.0076324000, -0.002797200, -0.035820000, -0.135283600, -0.421398900", \ - "0.0171563000, 0.0155171000, 0.0110864000, -0.001125300, -0.035834400, -0.135287300, -0.421240000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0179133000, 0.0195236000, 0.0240710000, 0.0365903000, 0.0714607000, 0.1706552000, 0.4531696000", \ - "0.0178721000, 0.0194785000, 0.0240042000, 0.0364284000, 0.0713628000, 0.1704740000, 0.4531608000", \ - "0.0176616000, 0.0192728000, 0.0237709000, 0.0362615000, 0.0712058000, 0.1704951000, 0.4536706000", \ - "0.0174505000, 0.0190750000, 0.0235966000, 0.0361173000, 0.0710182000, 0.1701612000, 0.4545615000", \ - "0.0174334000, 0.0189933000, 0.0234741000, 0.0356778000, 0.0706793000, 0.1700983000, 0.4532694000", \ - "0.0182010000, 0.0197174000, 0.0239990000, 0.0359737000, 0.0708187000, 0.1699013000, 0.4533727000", \ - "0.0193536000, 0.0208055000, 0.0249612000, 0.0371023000, 0.0718580000, 0.1709805000, 0.4524854000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0164753000, 0.0150618000, 0.0115335000, 0.0013465000, -0.031773600, -0.131223200, -0.417337800", \ - "0.0164884000, 0.0150685000, 0.0114892000, 0.0013002000, -0.031868600, -0.131335000, -0.417447100", \ - "0.0161875000, 0.0147786000, 0.0112538000, 0.0010610000, -0.032058000, -0.131501600, -0.417607300", \ - "0.0159627000, 0.0145396000, 0.0110847000, 0.0007873000, -0.032300200, -0.131783300, -0.417870300", \ - "0.0156971000, 0.0142830000, 0.0107539000, 0.0004615000, -0.032655500, -0.132075500, -0.418149900", \ - "0.0152520000, 0.0138043000, 0.0102571000, 0.0001530000, -0.032977900, -0.132289900, -0.418265200", \ - "0.0199424000, 0.0182943000, 0.0138689000, 0.0016245000, -0.032695400, -0.132326900, -0.418330000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0181953000, 0.0198050000, 0.0243000000, 0.0368079000, 0.0716114000, 0.1706346000, 0.4529985000", \ - "0.0180523000, 0.0196262000, 0.0242085000, 0.0367141000, 0.0715211000, 0.1705777000, 0.4529502000", \ - "0.0179653000, 0.0195449000, 0.0240535000, 0.0365635000, 0.0714041000, 0.1703649000, 0.4527374000", \ - "0.0177903000, 0.0193976000, 0.0239344000, 0.0364312000, 0.0712520000, 0.1705266000, 0.4534125000", \ - "0.0177346000, 0.0192936000, 0.0237271000, 0.0362306000, 0.0710911000, 0.1704440000, 0.4533493000", \ - "0.0181813000, 0.0196904000, 0.0240636000, 0.0361128000, 0.0710402000, 0.1697869000, 0.4530831000", \ - "0.0190428000, 0.0205115000, 0.0247818000, 0.0370058000, 0.0718720000, 0.1709100000, 0.4526284000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0191570000, 0.0177333000, 0.0141910000, 0.0038168000, -0.029506100, -0.129169600, -0.415391100", \ - "0.0189914000, 0.0175745000, 0.0140541000, 0.0037153000, -0.029630600, -0.129270000, -0.415511700", \ - "0.0188691000, 0.0174551000, 0.0140139000, 0.0035432000, -0.029794400, -0.129424000, -0.415644600", \ - "0.0187260000, 0.0173385000, 0.0137750000, 0.0033817000, -0.029980800, -0.129651600, -0.415813600", \ - "0.0184230000, 0.0170118000, 0.0135049000, 0.0030984000, -0.030227600, -0.129851800, -0.415980000", \ - "0.0181706000, 0.0168202000, 0.0131837000, 0.0029954000, -0.030298200, -0.129767300, -0.415929900", \ - "0.0232389000, 0.0215841000, 0.0171070000, 0.0047625000, -0.030226200, -0.129773200, -0.415785800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0184843000, 0.0200965000, 0.0246209000, 0.0370474000, 0.0718282000, 0.1706921000, 0.4533951000", \ - "0.0183570000, 0.0199686000, 0.0245217000, 0.0369251000, 0.0717251000, 0.1705654000, 0.4532792000", \ - "0.0182186000, 0.0198396000, 0.0243686000, 0.0368025000, 0.0715976000, 0.1704597000, 0.4531855000", \ - "0.0180058000, 0.0196223000, 0.0241557000, 0.0366387000, 0.0714153000, 0.1703360000, 0.4528824000", \ - "0.0179526000, 0.0195370000, 0.0240625000, 0.0363829000, 0.0712773000, 0.1702616000, 0.4528072000", \ - "0.0183627000, 0.0198777000, 0.0242207000, 0.0362746000, 0.0711908000, 0.1699041000, 0.4529907000", \ - "0.0189582000, 0.0204312000, 0.0246780000, 0.0369755000, 0.0718558000, 0.1711611000, 0.4524993000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0183158000, 0.0168848000, 0.0134385000, 0.0030191000, -0.030241000, -0.129661400, -0.415787300", \ - "0.0181721000, 0.0167605000, 0.0132866000, 0.0028596000, -0.030390500, -0.129844200, -0.415915600", \ - "0.0178996000, 0.0164738000, 0.0129448000, 0.0026577000, -0.030579400, -0.130049500, -0.416135200", \ - "0.0178086000, 0.0163789000, 0.0128355000, 0.0024436000, -0.030788500, -0.130255900, -0.416321500", \ - "0.0179296000, 0.0165020000, 0.0127146000, 0.0024667000, -0.030975800, -0.130421400, -0.416493300", \ - "0.0181922000, 0.0167021000, 0.0125929000, 0.0026962000, -0.030951000, -0.130366300, -0.416352600", \ - "0.0240085000, 0.0222963000, 0.0185066000, 0.0052797000, -0.029089700, -0.128655600, -0.414670100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014285070, 0.0040812630, 0.0116602200, 0.0333134100, 0.0951768500, 0.2719215000"); - values("0.0138204000, 0.0155112000, 0.0201851000, 0.0329439000, 0.0681184000, 0.1668043000, 0.4498529000", \ - "0.0137816000, 0.0154723000, 0.0201637000, 0.0329027000, 0.0680417000, 0.1667555000, 0.4511403000", \ - "0.0136350000, 0.0153081000, 0.0199508000, 0.0326276000, 0.0678024000, 0.1677924000, 0.4510391000", \ - "0.0133125000, 0.0149366000, 0.0194694000, 0.0320889000, 0.0673006000, 0.1670385000, 0.4500520000", \ - "0.0133053000, 0.0148338000, 0.0192675000, 0.0317540000, 0.0668539000, 0.1665991000, 0.4504103000", \ - "0.0138807000, 0.0153783000, 0.0196340000, 0.0320129000, 0.0668620000, 0.1659041000, 0.4491894000", \ - "0.0155450000, 0.0169493000, 0.0211063000, 0.0334515000, 0.0683242000, 0.1674896000, 0.4504069000"); - } - } - max_capacitance : 0.2719220000; - max_transition : 1.5046910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1666241000, 0.1723239000, 0.1850309000, 0.2105018000, 0.2602995000, 0.3701794000, 0.6562474000", \ - "0.1717685000, 0.1774547000, 0.1900707000, 0.2155362000, 0.2653258000, 0.3753705000, 0.6613972000", \ - "0.1841338000, 0.1897830000, 0.2024859000, 0.2278182000, 0.2776177000, 0.3876754000, 0.6736007000", \ - "0.2123781000, 0.2180866000, 0.2307679000, 0.2563082000, 0.3063054000, 0.4161352000, 0.7025046000", \ - "0.2761428000, 0.2818327000, 0.2943679000, 0.3197315000, 0.3699036000, 0.4797013000, 0.7661519000", \ - "0.3981833000, 0.4046365000, 0.4189490000, 0.4466746000, 0.5005403000, 0.6122404000, 0.8991559000", \ - "0.6032352000, 0.6112236000, 0.6286783000, 0.6628681000, 0.7250137000, 0.8459575000, 1.1367798000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1065708000, 0.1131327000, 0.1282482000, 0.1624073000, 0.2457774000, 0.4761243000, 1.1331789000", \ - "0.1102398000, 0.1168475000, 0.1319638000, 0.1659977000, 0.2497136000, 0.4805069000, 1.1369836000", \ - "0.1192716000, 0.1258378000, 0.1409878000, 0.1750512000, 0.2586832000, 0.4901715000, 1.1455921000", \ - "0.1417356000, 0.1482989000, 0.1634015000, 0.1974294000, 0.2811956000, 0.5121616000, 1.1682900000", \ - "0.1838900000, 0.1906886000, 0.2062034000, 0.2407525000, 0.3246079000, 0.5559306000, 1.2116057000", \ - "0.2348523000, 0.2429127000, 0.2599380000, 0.2955234000, 0.3804141000, 0.6117524000, 1.2684901000", \ - "0.2740058000, 0.2843359000, 0.3059989000, 0.3475111000, 0.4341476000, 0.6652269000, 1.3209945000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0256677000, 0.0289966000, 0.0377819000, 0.0567589000, 0.1025396000, 0.2268186000, 0.6049588000", \ - "0.0254003000, 0.0289901000, 0.0373350000, 0.0562625000, 0.1024559000, 0.2269443000, 0.6020274000", \ - "0.0254057000, 0.0289818000, 0.0373750000, 0.0563916000, 0.1025066000, 0.2267212000, 0.6017851000", \ - "0.0257164000, 0.0291195000, 0.0375026000, 0.0565075000, 0.1024486000, 0.2268370000, 0.6038239000", \ - "0.0256876000, 0.0292641000, 0.0375564000, 0.0563497000, 0.1018846000, 0.2266396000, 0.6034124000", \ - "0.0314993000, 0.0357008000, 0.0446245000, 0.0633936000, 0.1079534000, 0.2311670000, 0.6041662000", \ - "0.0442550000, 0.0494199000, 0.0591011000, 0.0802498000, 0.1259107000, 0.2445857000, 0.6051796000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0253206000, 0.0309505000, 0.0453124000, 0.0840904000, 0.1981125000, 0.5346188000, 1.4984400000", \ - "0.0253169000, 0.0309059000, 0.0452275000, 0.0842089000, 0.1980231000, 0.5345783000, 1.4991446000", \ - "0.0253771000, 0.0309098000, 0.0452831000, 0.0841287000, 0.1975689000, 0.5346222000, 1.5015708000", \ - "0.0252058000, 0.0308099000, 0.0451860000, 0.0840336000, 0.1981358000, 0.5349842000, 1.5002446000", \ - "0.0272096000, 0.0328656000, 0.0471015000, 0.0857665000, 0.1981287000, 0.5345854000, 1.5013679000", \ - "0.0349200000, 0.0401020000, 0.0529699000, 0.0899798000, 0.2005521000, 0.5345718000, 1.5013875000", \ - "0.0476563000, 0.0541633000, 0.0679804000, 0.1017527000, 0.2052547000, 0.5369814000, 1.4989683000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1952670000, 0.2013923000, 0.2148667000, 0.2415676000, 0.2930641000, 0.4050159000, 0.6924280000", \ - "0.2005236000, 0.2066388000, 0.2201265000, 0.2466556000, 0.2984346000, 0.4102239000, 0.6976628000", \ - "0.2131761000, 0.2193047000, 0.2327781000, 0.2594747000, 0.3110165000, 0.4229687000, 0.7103959000", \ - "0.2422237000, 0.2483466000, 0.2617599000, 0.2884753000, 0.3401437000, 0.4520142000, 0.7394861000", \ - "0.3053430000, 0.3114874000, 0.3249372000, 0.3516054000, 0.4034962000, 0.5154310000, 0.8029870000", \ - "0.4345641000, 0.4412783000, 0.4559227000, 0.4842582000, 0.5386503000, 0.6519000000, 0.9390939000", \ - "0.6577990000, 0.6659933000, 0.6839510000, 0.7176973000, 0.7789095000, 0.9002679000, 1.1912391000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1133300000, 0.1198841000, 0.1350255000, 0.1691332000, 0.2525376000, 0.4824574000, 1.1378284000", \ - "0.1173000000, 0.1238394000, 0.1390246000, 0.1731412000, 0.2564507000, 0.4863353000, 1.1423810000", \ - "0.1261793000, 0.1327034000, 0.1478307000, 0.1818775000, 0.2654879000, 0.4958867000, 1.1506271000", \ - "0.1464116000, 0.1529816000, 0.1681018000, 0.2021341000, 0.2854698000, 0.5164703000, 1.1739226000", \ - "0.1856065000, 0.1924777000, 0.2082634000, 0.2429254000, 0.3266944000, 0.5576706000, 1.2151973000", \ - "0.2386786000, 0.2466050000, 0.2639800000, 0.3005744000, 0.3856387000, 0.6166522000, 1.2728667000", \ - "0.2824009000, 0.2926200000, 0.3142406000, 0.3562570000, 0.4439473000, 0.6747823000, 1.3304764000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0285752000, 0.0323887000, 0.0406634000, 0.0593965000, 0.1053801000, 0.2303470000, 0.6051148000", \ - "0.0285494000, 0.0323131000, 0.0405855000, 0.0597137000, 0.1060863000, 0.2306314000, 0.6042506000", \ - "0.0285899000, 0.0323978000, 0.0406503000, 0.0596183000, 0.1054521000, 0.2303629000, 0.6051579000", \ - "0.0287629000, 0.0321193000, 0.0407111000, 0.0601870000, 0.1059885000, 0.2304420000, 0.6052820000", \ - "0.0285155000, 0.0322083000, 0.0406498000, 0.0598011000, 0.1053190000, 0.2305161000, 0.6052979000", \ - "0.0332168000, 0.0372050000, 0.0457968000, 0.0650662000, 0.1093062000, 0.2321467000, 0.6049659000", \ - "0.0456903000, 0.0496169000, 0.0596534000, 0.0799378000, 0.1269700000, 0.2453254000, 0.6066342000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0252895000, 0.0308437000, 0.0453104000, 0.0842396000, 0.1981608000, 0.5350069000, 1.5004440000", \ - "0.0253213000, 0.0309473000, 0.0453365000, 0.0841949000, 0.1981662000, 0.5345523000, 1.4999750000", \ - "0.0253433000, 0.0310115000, 0.0453044000, 0.0840872000, 0.1980622000, 0.5353792000, 1.5007908000", \ - "0.0252737000, 0.0309494000, 0.0452260000, 0.0841436000, 0.1979641000, 0.5344677000, 1.4990889000", \ - "0.0274538000, 0.0330409000, 0.0475350000, 0.0854872000, 0.1982378000, 0.5344288000, 1.4991115000", \ - "0.0334174000, 0.0391466000, 0.0527737000, 0.0894733000, 0.2004809000, 0.5333563000, 1.5007452000", \ - "0.0457632000, 0.0520505000, 0.0664163000, 0.1010963000, 0.2053025000, 0.5365683000, 1.4988490000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.2076204000, 0.2138073000, 0.2273505000, 0.2539209000, 0.3050925000, 0.4165625000, 0.7042597000", \ - "0.2128672000, 0.2190627000, 0.2325960000, 0.2592653000, 0.3103797000, 0.4219276000, 0.7094893000", \ - "0.2260546000, 0.2322418000, 0.2457573000, 0.2724157000, 0.3235800000, 0.4351501000, 0.7227005000", \ - "0.2553716000, 0.2615611000, 0.2751491000, 0.3015966000, 0.3531112000, 0.4644930000, 0.7519649000", \ - "0.3188152000, 0.3250065000, 0.3385462000, 0.3650950000, 0.4167682000, 0.5283958000, 0.8159854000", \ - "0.4509911000, 0.4579951000, 0.4722227000, 0.5006331000, 0.5540678000, 0.6663983000, 0.9537409000", \ - "0.6833342000, 0.6914574000, 0.7089466000, 0.7420825000, 0.8027182000, 0.9227172000, 1.2135953000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1184532000, 0.1250305000, 0.1401820000, 0.1741626000, 0.2575176000, 0.4873524000, 1.1431343000", \ - "0.1223624000, 0.1289311000, 0.1441032000, 0.1780838000, 0.2614506000, 0.4914248000, 1.1474549000", \ - "0.1303132000, 0.1368804000, 0.1520446000, 0.1860246000, 0.2694222000, 0.4994316000, 1.1554379000", \ - "0.1468557000, 0.1534353000, 0.1685663000, 0.2025672000, 0.2860458000, 0.5164233000, 1.1725085000", \ - "0.1788929000, 0.1857381000, 0.2014573000, 0.2360816000, 0.3200493000, 0.5506546000, 1.2066762000", \ - "0.2247486000, 0.2325286000, 0.2498130000, 0.2863929000, 0.3715898000, 0.6022075000, 1.2587591000", \ - "0.2625654000, 0.2724755000, 0.2938857000, 0.3358328000, 0.4242147000, 0.6558932000, 1.3104819000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0293322000, 0.0330435000, 0.0413825000, 0.0601306000, 0.1058844000, 0.2305529000, 0.6051898000", \ - "0.0294230000, 0.0332283000, 0.0418021000, 0.0599241000, 0.1056419000, 0.2303250000, 0.6039978000", \ - "0.0293291000, 0.0330396000, 0.0412361000, 0.0599969000, 0.1056756000, 0.2302502000, 0.6054613000", \ - "0.0292677000, 0.0329795000, 0.0417701000, 0.0600964000, 0.1062816000, 0.2303771000, 0.6054450000", \ - "0.0294531000, 0.0332083000, 0.0413036000, 0.0601966000, 0.1060471000, 0.2300603000, 0.6056124000", \ - "0.0336716000, 0.0371609000, 0.0455592000, 0.0648742000, 0.1084424000, 0.2319354000, 0.6065796000", \ - "0.0445705000, 0.0489291000, 0.0584825000, 0.0779808000, 0.1238335000, 0.2426591000, 0.6066845000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0253208000, 0.0309720000, 0.0452290000, 0.0840527000, 0.1981372000, 0.5345784000, 1.4988464000", \ - "0.0253905000, 0.0309208000, 0.0452389000, 0.0841320000, 0.1979259000, 0.5344081000, 1.4970226000", \ - "0.0253230000, 0.0309834000, 0.0452281000, 0.0840477000, 0.1981509000, 0.5342901000, 1.4972353000", \ - "0.0252579000, 0.0308196000, 0.0452280000, 0.0841481000, 0.1982279000, 0.5341935000, 1.4983023000", \ - "0.0272929000, 0.0329066000, 0.0471437000, 0.0854789000, 0.1983364000, 0.5347231000, 1.4990111000", \ - "0.0319727000, 0.0376365000, 0.0520978000, 0.0895529000, 0.2007771000, 0.5345678000, 1.5000067000", \ - "0.0434076000, 0.0497637000, 0.0643101000, 0.1002298000, 0.2057509000, 0.5356740000, 1.4989513000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.1827449000, 0.1889132000, 0.2024692000, 0.2290738000, 0.2808849000, 0.3921436000, 0.6794715000", \ - "0.1862537000, 0.1924443000, 0.2059610000, 0.2325838000, 0.2843794000, 0.3957043000, 0.6832995000", \ - "0.1959535000, 0.2021142000, 0.2155656000, 0.2422474000, 0.2936518000, 0.4053961000, 0.6930869000", \ - "0.2228940000, 0.2291133000, 0.2427570000, 0.2692174000, 0.3209081000, 0.4325560000, 0.7201899000", \ - "0.2888421000, 0.2950250000, 0.3091090000, 0.3350847000, 0.3873752000, 0.4992962000, 0.7870768000", \ - "0.4280605000, 0.4354867000, 0.4503303000, 0.4793778000, 0.5324801000, 0.6454576000, 0.9334581000", \ - "0.6471659000, 0.6564499000, 0.6774700000, 0.7132585000, 0.7756578000, 0.8939282000, 1.1847300000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0628009000, 0.0685243000, 0.0819224000, 0.1133206000, 0.1952598000, 0.4247981000, 1.0925620000", \ - "0.0676883000, 0.0734121000, 0.0868101000, 0.1181558000, 0.2001153000, 0.4303222000, 1.0897520000", \ - "0.0789317000, 0.0846139000, 0.0979097000, 0.1291495000, 0.2112030000, 0.4429034000, 1.1021988000", \ - "0.1026288000, 0.1084655000, 0.1218469000, 0.1530787000, 0.2349796000, 0.4663350000, 1.1258791000", \ - "0.1362781000, 0.1435056000, 0.1589088000, 0.1914859000, 0.2737311000, 0.5040657000, 1.1604480000", \ - "0.1733754000, 0.1831049000, 0.2028407000, 0.2397543000, 0.3229833000, 0.5534037000, 1.2107805000", \ - "0.1965515000, 0.2093867000, 0.2358309000, 0.2830245000, 0.3718141000, 0.6020158000, 1.2571759000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0296501000, 0.0332988000, 0.0416476000, 0.0602593000, 0.1058821000, 0.2302101000, 0.6049380000", \ - "0.0293830000, 0.0330324000, 0.0416115000, 0.0602351000, 0.1059766000, 0.2305099000, 0.6054128000", \ - "0.0294640000, 0.0333287000, 0.0412163000, 0.0599548000, 0.1063476000, 0.2303562000, 0.6054555000", \ - "0.0292552000, 0.0328790000, 0.0413484000, 0.0605085000, 0.1057803000, 0.2304556000, 0.6055346000", \ - "0.0292504000, 0.0332881000, 0.0413142000, 0.0608576000, 0.1059989000, 0.2299984000, 0.6056236000", \ - "0.0375184000, 0.0409810000, 0.0492425000, 0.0664556000, 0.1099522000, 0.2324034000, 0.6049812000", \ - "0.0551121000, 0.0593569000, 0.0699027000, 0.0877438000, 0.1273234000, 0.2424116000, 0.6075855000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014285100, 0.0040812600, 0.0116602000, 0.0333134000, 0.0951769000, 0.2719220000"); - values("0.0203236000, 0.0253646000, 0.0386177000, 0.0773623000, 0.1938673000, 0.5325025000, 1.4958655000", \ - "0.0203234000, 0.0253630000, 0.0386458000, 0.0772613000, 0.1938094000, 0.5326808000, 1.5022390000", \ - "0.0203333000, 0.0253919000, 0.0387093000, 0.0773243000, 0.1938333000, 0.5336862000, 1.4988106000", \ - "0.0221970000, 0.0268828000, 0.0396290000, 0.0776130000, 0.1940502000, 0.5331262000, 1.5046910000", \ - "0.0296961000, 0.0341199000, 0.0453546000, 0.0808145000, 0.1945624000, 0.5316135000, 1.5031798000", \ - "0.0421919000, 0.0474152000, 0.0578302000, 0.0889993000, 0.1969231000, 0.5317708000, 1.4989816000", \ - "0.0605753000, 0.0672864000, 0.0800634000, 0.1094615000, 0.2049051000, 0.5322462000, 1.4958256000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31o_4") { - leakage_power () { - value : 0.0049246000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0068611000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0049246000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0069085000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0049246000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0068995000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0049251000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0079455000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0049246000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0069080000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0049244000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0076641000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0049247000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0075432000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0023308000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0052901000; - when : "A1&A2&A3&!B1"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__a31o"; - cell_leakage_power : 0.0058014510; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086645000, 0.0086592000, 0.0086469000, 0.0086462000, 0.0086445000, 0.0086405000, 0.0086315000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006771600, -0.006777600, -0.006791500, -0.006776400, -0.006741800, -0.006661900, -0.006477700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044540000; - } - pin ("A2") { - capacitance : 0.0047420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087574000, 0.0087524000, 0.0087407000, 0.0087722000, 0.0088447000, 0.0090117000, 0.0093968000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007849300, -0.007845500, -0.007836700, -0.007835500, -0.007832500, -0.007825800, -0.007810200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049410000; - } - pin ("A3") { - capacitance : 0.0049160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085177000, 0.0085185000, 0.0085202000, 0.0085181000, 0.0085132000, 0.0085020000, 0.0084762000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008530000, -0.008523600, -0.008509000, -0.008505500, -0.008497600, -0.008479300, -0.008437200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051540000; - } - pin ("B1") { - capacitance : 0.0044590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045958000, 0.0045836000, 0.0045557000, 0.0045884000, 0.0046637000, 0.0048374000, 0.0052377000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003417100, -0.003411400, -0.003398500, -0.003399100, -0.003400500, -0.003403700, -0.003411100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048140000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0280411000, 0.0263166000, 0.0213879000, 0.0072106000, -0.043310800, -0.216139400, -0.768460500", \ - "0.0277785000, 0.0261725000, 0.0211848000, 0.0070836000, -0.043460800, -0.216373800, -0.768634200", \ - "0.0274898000, 0.0259039000, 0.0209051000, 0.0065949000, -0.043959000, -0.216649400, -0.768997400", \ - "0.0270212000, 0.0252755000, 0.0202746000, 0.0060852000, -0.044431000, -0.217278900, -0.769526500", \ - "0.0264573000, 0.0249330000, 0.0197855000, 0.0054826000, -0.045225600, -0.217798500, -0.770003600", \ - "0.0256213000, 0.0238698000, 0.0186946000, 0.0049347000, -0.045582800, -0.218117500, -0.770154300", \ - "0.0348975000, 0.0329246000, 0.0270516000, 0.0094182000, -0.045352800, -0.218389700, -0.770085000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0339809000, 0.0358473000, 0.0418293000, 0.0600140000, 0.1160557000, 0.2902158000, 0.8367808000", \ - "0.0337656000, 0.0356130000, 0.0416106000, 0.0598185000, 0.1158669000, 0.2899506000, 0.8367097000", \ - "0.0333640000, 0.0352334000, 0.0411885000, 0.0595401000, 0.1155524000, 0.2895328000, 0.8369673000", \ - "0.0330731000, 0.0349427000, 0.0408709000, 0.0592249000, 0.1150525000, 0.2891849000, 0.8366563000", \ - "0.0331295000, 0.0349979000, 0.0407981000, 0.0587326000, 0.1140776000, 0.2885899000, 0.8353350000", \ - "0.0344102000, 0.0361582000, 0.0417169000, 0.0592520000, 0.1142055000, 0.2873641000, 0.8359845000", \ - "0.0367626000, 0.0384287000, 0.0438981000, 0.0611830000, 0.1159533000, 0.2888314000, 0.8339947000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0339096000, 0.0321709000, 0.0271024000, 0.0128805000, -0.037840200, -0.210556700, -0.762613300", \ - "0.0339022000, 0.0321419000, 0.0270931000, 0.0127785000, -0.037958800, -0.210793600, -0.762890900", \ - "0.0333255000, 0.0316692000, 0.0265895000, 0.0123003000, -0.038398900, -0.211122200, -0.763173500", \ - "0.0328734000, 0.0311303000, 0.0261644000, 0.0118813000, -0.038823700, -0.211631300, -0.763699200", \ - "0.0323740000, 0.0306118000, 0.0255812000, 0.0111521000, -0.039626700, -0.212227600, -0.764240700", \ - "0.0315439000, 0.0297620000, 0.0246472000, 0.0103885000, -0.040044800, -0.212628000, -0.764543200", \ - "0.0396981000, 0.0377304000, 0.0318459000, 0.0144029000, -0.040254300, -0.213454700, -0.764976600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0347813000, 0.0366088000, 0.0425406000, 0.0609844000, 0.1170317000, 0.2909249000, 0.8377248000", \ - "0.0346489000, 0.0365075000, 0.0423895000, 0.0607403000, 0.1168260000, 0.2905372000, 0.8378446000", \ - "0.0343198000, 0.0362212000, 0.0421803000, 0.0604492000, 0.1164609000, 0.2906395000, 0.8369966000", \ - "0.0339546000, 0.0358504000, 0.0417802000, 0.0601711000, 0.1161063000, 0.2901265000, 0.8367001000", \ - "0.0337279000, 0.0355982000, 0.0415906000, 0.0596473000, 0.1154407000, 0.2895494000, 0.8371669000", \ - "0.0347128000, 0.0364896000, 0.0421643000, 0.0599145000, 0.1149964000, 0.2883524000, 0.8358424000", \ - "0.0365974000, 0.0382678000, 0.0438093000, 0.0614390000, 0.1166182000, 0.2899135000, 0.8350688000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0395742000, 0.0378305000, 0.0327575000, 0.0186607000, -0.032080500, -0.204684100, -0.756532600", \ - "0.0394514000, 0.0377212000, 0.0326408000, 0.0182442000, -0.032361300, -0.204839000, -0.756824800", \ - "0.0393288000, 0.0375593000, 0.0324971000, 0.0182745000, -0.032588100, -0.205118400, -0.757032500", \ - "0.0388180000, 0.0371433000, 0.0320083000, 0.0176917000, -0.032914600, -0.205410400, -0.757337600", \ - "0.0385114000, 0.0367502000, 0.0317307000, 0.0173014000, -0.033335900, -0.205849300, -0.757665400", \ - "0.0384393000, 0.0366330000, 0.0313401000, 0.0169129000, -0.033722800, -0.206001000, -0.757749200", \ - "0.0467280000, 0.0447566000, 0.0389875000, 0.0212984000, -0.033483000, -0.205849200, -0.757470400"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0353609000, 0.0372175000, 0.0431950000, 0.0614318000, 0.1175002000, 0.2911568000, 0.8383628000", \ - "0.0350798000, 0.0369833000, 0.0429283000, 0.0611844000, 0.1172309000, 0.2912405000, 0.8371590000", \ - "0.0347693000, 0.0366515000, 0.0426256000, 0.0608667000, 0.1168509000, 0.2909818000, 0.8373534000", \ - "0.0343155000, 0.0361701000, 0.0421494000, 0.0605254000, 0.1164729000, 0.2904406000, 0.8374593000", \ - "0.0342233000, 0.0360701000, 0.0419397000, 0.0598753000, 0.1158949000, 0.2898058000, 0.8373250000", \ - "0.0352120000, 0.0369751000, 0.0427506000, 0.0603822000, 0.1152316000, 0.2884658000, 0.8357927000", \ - "0.0364317000, 0.0381143000, 0.0437876000, 0.0610950000, 0.1165595000, 0.2897811000, 0.8348342000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0375251000, 0.0359103000, 0.0308210000, 0.0165099000, -0.034072600, -0.206549500, -0.758403500", \ - "0.0372019000, 0.0355921000, 0.0305301000, 0.0162835000, -0.034281700, -0.206821500, -0.758665100", \ - "0.0371032000, 0.0352618000, 0.0301752000, 0.0159283000, -0.034670600, -0.207245400, -0.759087800", \ - "0.0365221000, 0.0347551000, 0.0297298000, 0.0153224000, -0.035330000, -0.207742500, -0.759621600", \ - "0.0370146000, 0.0352402000, 0.0301433000, 0.0156156000, -0.035409000, -0.208074600, -0.759863300", \ - "0.0369936000, 0.0350662000, 0.0297970000, 0.0163153000, -0.034712600, -0.207550100, -0.759241400", \ - "0.0483489000, 0.0462886000, 0.0401880000, 0.0222419000, -0.032710300, -0.205849300, -0.756866700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015805970, 0.0049965720, 0.0157951300, 0.0499314600, 0.1578430000, 0.4989722000"); - values("0.0247040000, 0.0266683000, 0.0327553000, 0.0509730000, 0.1060937000, 0.2780887000, 0.8219814000", \ - "0.0246205000, 0.0265851000, 0.0326576000, 0.0508679000, 0.1060560000, 0.2780580000, 0.8221090000", \ - "0.0243506000, 0.0262915000, 0.0322836000, 0.0504152000, 0.1057500000, 0.2778998000, 0.8218820000", \ - "0.0238951000, 0.0257638000, 0.0316138000, 0.0496068000, 0.1050701000, 0.2788634000, 0.8216755000", \ - "0.0239629000, 0.0257089000, 0.0312681000, 0.0491347000, 0.1043014000, 0.2780962000, 0.8215055000", \ - "0.0249920000, 0.0267336000, 0.0322739000, 0.0498900000, 0.1044919000, 0.2772045000, 0.8250773000", \ - "0.0292002000, 0.0308000000, 0.0360573000, 0.0533901000, 0.1084017000, 0.2806824000, 0.8251881000"); - } - } - max_capacitance : 0.4989720000; - max_transition : 1.5044100000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1833494000, 0.1872618000, 0.1973707000, 0.2201386000, 0.2675200000, 0.3753909000, 0.6701638000", \ - "0.1883310000, 0.1922445000, 0.2023598000, 0.2249734000, 0.2725459000, 0.3803836000, 0.6751742000", \ - "0.2007563000, 0.2046252000, 0.2147073000, 0.2374383000, 0.2849314000, 0.3927454000, 0.6869703000", \ - "0.2297025000, 0.2336012000, 0.2436665000, 0.2663622000, 0.3137458000, 0.4216656000, 0.7164612000", \ - "0.2930105000, 0.2969354000, 0.3070372000, 0.3296346000, 0.3774754000, 0.4850718000, 0.7796997000", \ - "0.4169481000, 0.4212500000, 0.4323452000, 0.4570735000, 0.5077408000, 0.6178046000, 0.9134348000", \ - "0.6288848000, 0.6340857000, 0.6475243000, 0.6770111000, 0.7357500000, 0.8559528000, 1.1565813000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1032693000, 0.1076521000, 0.1193829000, 0.1484235000, 0.2243103000, 0.4507915000, 1.1613078000", \ - "0.1068967000, 0.1112966000, 0.1230179000, 0.1520557000, 0.2280080000, 0.4543325000, 1.1657778000", \ - "0.1159563000, 0.1204656000, 0.1321217000, 0.1612544000, 0.2372363000, 0.4632974000, 1.1725623000", \ - "0.1380954000, 0.1424681000, 0.1541130000, 0.1831169000, 0.2588778000, 0.4853347000, 1.1940964000", \ - "0.1778348000, 0.1823160000, 0.1941841000, 0.2235876000, 0.2997665000, 0.5264155000, 1.2378785000", \ - "0.2247665000, 0.2299395000, 0.2429677000, 0.2728652000, 0.3499118000, 0.5768760000, 1.2868240000", \ - "0.2555917000, 0.2623382000, 0.2790448000, 0.3149890000, 0.3928870000, 0.6182187000, 1.3272877000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0270730000, 0.0295087000, 0.0359404000, 0.0521989000, 0.0933951000, 0.2106308000, 0.5952913000", \ - "0.0272812000, 0.0298085000, 0.0363013000, 0.0527591000, 0.0934679000, 0.2102509000, 0.5944583000", \ - "0.0273241000, 0.0298162000, 0.0363169000, 0.0522151000, 0.0929927000, 0.2106332000, 0.5965788000", \ - "0.0271094000, 0.0295669000, 0.0361009000, 0.0520774000, 0.0934635000, 0.2105936000, 0.5945485000", \ - "0.0273505000, 0.0298608000, 0.0360859000, 0.0520578000, 0.0929503000, 0.2107273000, 0.5962897000", \ - "0.0325377000, 0.0351072000, 0.0420028000, 0.0586278000, 0.0984365000, 0.2137125000, 0.5950033000", \ - "0.0453402000, 0.0481729000, 0.0564489000, 0.0736956000, 0.1157033000, 0.2287728000, 0.5994550000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0249389000, 0.0286219000, 0.0390471000, 0.0697794000, 0.1669309000, 0.4866164000, 1.5043238000", \ - "0.0249282000, 0.0285712000, 0.0389704000, 0.0697635000, 0.1670469000, 0.4870765000, 1.5003362000", \ - "0.0250152000, 0.0286541000, 0.0391042000, 0.0697431000, 0.1671647000, 0.4861045000, 1.5025012000", \ - "0.0248326000, 0.0284516000, 0.0389609000, 0.0696343000, 0.1670335000, 0.4870207000, 1.5016663000", \ - "0.0268550000, 0.0303332000, 0.0407478000, 0.0711422000, 0.1679562000, 0.4872410000, 1.5025816000", \ - "0.0333429000, 0.0369732000, 0.0463552000, 0.0754150000, 0.1699463000, 0.4863454000, 1.5028336000", \ - "0.0459108000, 0.0500861000, 0.0605545000, 0.0865796000, 0.1744996000, 0.4883753000, 1.5002247000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1934297000, 0.1973884000, 0.2075071000, 0.2299738000, 0.2764649000, 0.3826518000, 0.6767225000", \ - "0.1985138000, 0.2025102000, 0.2126132000, 0.2350654000, 0.2816709000, 0.3877504000, 0.6820738000", \ - "0.2112100000, 0.2151632000, 0.2252807000, 0.2477800000, 0.2943202000, 0.4005427000, 0.6946353000", \ - "0.2405741000, 0.2445319000, 0.2546537000, 0.2768932000, 0.3235699000, 0.4298129000, 0.7241140000", \ - "0.3036444000, 0.3075551000, 0.3176963000, 0.3401094000, 0.3869108000, 0.4930877000, 0.7873482000", \ - "0.4306900000, 0.4350402000, 0.4461490000, 0.4702726000, 0.5189828000, 0.6272308000, 0.9217174000", \ - "0.6493326000, 0.6546587000, 0.6679063000, 0.6969911000, 0.7532612000, 0.8699625000, 1.1689256000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1104839000, 0.1148516000, 0.1265433000, 0.1556329000, 0.2317051000, 0.4580653000, 1.1665499000", \ - "0.1144325000, 0.1188312000, 0.1304600000, 0.1595735000, 0.2355852000, 0.4617112000, 1.1707537000", \ - "0.1231140000, 0.1275344000, 0.1392319000, 0.1683027000, 0.2442981000, 0.4706329000, 1.1802073000", \ - "0.1432462000, 0.1476234000, 0.1593049000, 0.1883221000, 0.2642901000, 0.4912503000, 1.1980203000", \ - "0.1814392000, 0.1860347000, 0.1981649000, 0.2278435000, 0.3040906000, 0.5302289000, 1.2390745000", \ - "0.2321132000, 0.2373289000, 0.2507103000, 0.2814281000, 0.3586864000, 0.5852989000, 1.2961568000", \ - "0.2716845000, 0.2783061000, 0.2951731000, 0.3313295000, 0.4116487000, 0.6387658000, 1.3468094000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0276349000, 0.0300454000, 0.0363870000, 0.0516217000, 0.0918769000, 0.2087640000, 0.5957450000", \ - "0.0278691000, 0.0299469000, 0.0362397000, 0.0517770000, 0.0919799000, 0.2087683000, 0.5961041000", \ - "0.0278411000, 0.0302119000, 0.0364052000, 0.0517237000, 0.0919406000, 0.2088306000, 0.5955859000", \ - "0.0275877000, 0.0299394000, 0.0362141000, 0.0521653000, 0.0920503000, 0.2088025000, 0.5960720000", \ - "0.0275612000, 0.0300671000, 0.0362288000, 0.0517036000, 0.0917806000, 0.2088855000, 0.5948751000", \ - "0.0324840000, 0.0350780000, 0.0416903000, 0.0566814000, 0.0964153000, 0.2113215000, 0.5960099000", \ - "0.0441438000, 0.0474893000, 0.0544458000, 0.0710954000, 0.1117273000, 0.2236189000, 0.5982929000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0249730000, 0.0286110000, 0.0391484000, 0.0696425000, 0.1673188000, 0.4876551000, 1.5028264000", \ - "0.0249810000, 0.0286209000, 0.0390190000, 0.0696782000, 0.1672818000, 0.4867307000, 1.5027274000", \ - "0.0250392000, 0.0286720000, 0.0390160000, 0.0697156000, 0.1673338000, 0.4862665000, 1.5032079000", \ - "0.0249811000, 0.0285311000, 0.0388717000, 0.0695450000, 0.1671677000, 0.4875315000, 1.5019358000", \ - "0.0267633000, 0.0304120000, 0.0410101000, 0.0710875000, 0.1677517000, 0.4867465000, 1.5014220000", \ - "0.0324268000, 0.0361450000, 0.0463802000, 0.0755039000, 0.1700865000, 0.4869983000, 1.5036261000", \ - "0.0441442000, 0.0482044000, 0.0591867000, 0.0867300000, 0.1745828000, 0.4891137000, 1.4976167000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.2050415000, 0.2090544000, 0.2192364000, 0.2415317000, 0.2879866000, 0.3938720000, 0.6881342000", \ - "0.2103147000, 0.2143097000, 0.2244792000, 0.2469471000, 0.2936731000, 0.3993013000, 0.6935111000", \ - "0.2233650000, 0.2273604000, 0.2375524000, 0.2600654000, 0.3067407000, 0.4122402000, 0.7065139000", \ - "0.2529055000, 0.2568937000, 0.2670723000, 0.2895372000, 0.3361748000, 0.4417710000, 0.7361316000", \ - "0.3150142000, 0.3190093000, 0.3292085000, 0.3515891000, 0.3981716000, 0.5043393000, 0.7984900000", \ - "0.4413874000, 0.4457327000, 0.4567415000, 0.4808593000, 0.5295010000, 0.6361733000, 0.9311195000", \ - "0.6575757000, 0.6628363000, 0.6762745000, 0.7046701000, 0.7606077000, 0.8750088000, 1.1731133000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1157956000, 0.1201938000, 0.1319313000, 0.1609236000, 0.2368939000, 0.4628382000, 1.1717778000", \ - "0.1197348000, 0.1241437000, 0.1358525000, 0.1649420000, 0.2409357000, 0.4670164000, 1.1757448000", \ - "0.1276738000, 0.1320651000, 0.1438232000, 0.1728889000, 0.2488058000, 0.4752193000, 1.1853805000", \ - "0.1445221000, 0.1489219000, 0.1606402000, 0.1896221000, 0.2656221000, 0.4917347000, 1.2006348000", \ - "0.1770541000, 0.1816482000, 0.1937594000, 0.2232274000, 0.2995081000, 0.5254470000, 1.2345470000", \ - "0.2237077000, 0.2288302000, 0.2420337000, 0.2732815000, 0.3508515000, 0.5771760000, 1.2880241000", \ - "0.2638777000, 0.2703821000, 0.2872202000, 0.3233409000, 0.4044034000, 0.6313618000, 1.3392923000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0282387000, 0.0305715000, 0.0369591000, 0.0518923000, 0.0913561000, 0.2082537000, 0.5951306000", \ - "0.0283662000, 0.0307317000, 0.0367844000, 0.0522494000, 0.0910493000, 0.2079923000, 0.5942145000", \ - "0.0282516000, 0.0305920000, 0.0370208000, 0.0520172000, 0.0914041000, 0.2083014000, 0.5960045000", \ - "0.0283517000, 0.0307425000, 0.0370037000, 0.0519670000, 0.0915391000, 0.2081055000, 0.5958078000", \ - "0.0282548000, 0.0305731000, 0.0367971000, 0.0517338000, 0.0915009000, 0.2079995000, 0.5950158000", \ - "0.0327888000, 0.0353205000, 0.0412153000, 0.0563430000, 0.0948583000, 0.2104345000, 0.5942615000", \ - "0.0444761000, 0.0467760000, 0.0544680000, 0.0704326000, 0.1098810000, 0.2220146000, 0.5973779000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0249818000, 0.0286203000, 0.0390751000, 0.0696774000, 0.1672528000, 0.4865773000, 1.5025449000", \ - "0.0250525000, 0.0286844000, 0.0389660000, 0.0697416000, 0.1672636000, 0.4860614000, 1.5003084000", \ - "0.0250026000, 0.0285993000, 0.0390324000, 0.0697492000, 0.1673687000, 0.4867688000, 1.5044096000", \ - "0.0248342000, 0.0285401000, 0.0390575000, 0.0695960000, 0.1673090000, 0.4868662000, 1.5025772000", \ - "0.0266048000, 0.0302831000, 0.0408219000, 0.0709013000, 0.1679782000, 0.4866648000, 1.5016772000", \ - "0.0311461000, 0.0348358000, 0.0458939000, 0.0751681000, 0.1701208000, 0.4865454000, 1.5026471000", \ - "0.0420567000, 0.0465337000, 0.0578150000, 0.0863733000, 0.1753358000, 0.4874247000, 1.5004430000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.1758746000, 0.1798793000, 0.1900793000, 0.2126109000, 0.2593541000, 0.3651565000, 0.6595879000", \ - "0.1795033000, 0.1835115000, 0.1937268000, 0.2163369000, 0.2626740000, 0.3685778000, 0.6627803000", \ - "0.1897512000, 0.1937323000, 0.2038013000, 0.2262877000, 0.2729808000, 0.3787288000, 0.6732116000", \ - "0.2167954000, 0.2207741000, 0.2309655000, 0.2534958000, 0.3000229000, 0.4059693000, 0.7000586000", \ - "0.2836572000, 0.2876478000, 0.2977579000, 0.3200413000, 0.3665906000, 0.4725502000, 0.7667680000", \ - "0.4236710000, 0.4282956000, 0.4399378000, 0.4645681000, 0.5126270000, 0.6203420000, 0.9148099000", \ - "0.6481007000, 0.6540106000, 0.6690471000, 0.7006749000, 0.7581752000, 0.8707808000, 1.1667961000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0584161000, 0.0622635000, 0.0726477000, 0.0988440000, 0.1710801000, 0.3947480000, 1.1020740000", \ - "0.0629925000, 0.0668372000, 0.0772094000, 0.1034049000, 0.1757316000, 0.3994332000, 1.1068083000", \ - "0.0738632000, 0.0776657000, 0.0879403000, 0.1140546000, 0.1865489000, 0.4103737000, 1.1171259000", \ - "0.0950462000, 0.0989950000, 0.1094688000, 0.1357056000, 0.2084962000, 0.4333238000, 1.1390280000", \ - "0.1229965000, 0.1278125000, 0.1398490000, 0.1677781000, 0.2411510000, 0.4664811000, 1.1721017000", \ - "0.1486526000, 0.1552623000, 0.1710029000, 0.2032490000, 0.2784924000, 0.5030115000, 1.2128459000", \ - "0.1500490000, 0.1584204000, 0.1792040000, 0.2212892000, 0.3034233000, 0.5281440000, 1.2346044000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0284031000, 0.0308395000, 0.0367154000, 0.0520610000, 0.0908986000, 0.2083609000, 0.5955511000", \ - "0.0283925000, 0.0308125000, 0.0371862000, 0.0523053000, 0.0917372000, 0.2081758000, 0.5955585000", \ - "0.0282655000, 0.0306077000, 0.0368652000, 0.0520292000, 0.0918480000, 0.2083329000, 0.5962461000", \ - "0.0286514000, 0.0310373000, 0.0372300000, 0.0520278000, 0.0916528000, 0.2082178000, 0.5960807000", \ - "0.0284349000, 0.0307689000, 0.0370478000, 0.0520615000, 0.0918678000, 0.2082636000, 0.5952441000", \ - "0.0367527000, 0.0388135000, 0.0449158000, 0.0591544000, 0.0961787000, 0.2106071000, 0.5958961000", \ - "0.0534687000, 0.0566202000, 0.0655198000, 0.0793925000, 0.1134012000, 0.2203884000, 0.5987071000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015806000, 0.0049965700, 0.0157951000, 0.0499315000, 0.1578430000, 0.4989720000"); - values("0.0198651000, 0.0233027000, 0.0331875000, 0.0631752000, 0.1622570000, 0.4839468000, 1.4966313000", \ - "0.0198669000, 0.0233067000, 0.0331966000, 0.0631868000, 0.1622760000, 0.4838616000, 1.4952067000", \ - "0.0198919000, 0.0233406000, 0.0332518000, 0.0632394000, 0.1622558000, 0.4837928000, 1.4977233000", \ - "0.0220802000, 0.0252257000, 0.0345796000, 0.0636785000, 0.1622174000, 0.4841029000, 1.4997475000", \ - "0.0289602000, 0.0321671000, 0.0406589000, 0.0675272000, 0.1633298000, 0.4840019000, 1.4986572000", \ - "0.0416913000, 0.0450958000, 0.0538139000, 0.0768239000, 0.1664525000, 0.4820825000, 1.5008292000", \ - "0.0596911000, 0.0642470000, 0.0746897000, 0.0985182000, 0.1762623000, 0.4846276000, 1.4970420000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31oi_1") { - leakage_power () { - value : 0.0024357000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0003518000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0003716000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0003639000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0007808000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0003686000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0006717000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0024357000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0005842000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0002991000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0028949000; - when : "A1&A2&A3&!B1"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__a31oi"; - cell_leakage_power : 0.0014835190; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046302000, 0.0046323000, 0.0046373000, 0.0046344000, 0.0046277000, 0.0046123000, 0.0045769000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003557700, -0.003558500, -0.003560200, -0.003553000, -0.003536500, -0.003498400, -0.003410600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023640000; - } - pin ("A2") { - capacitance : 0.0024260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044647000, 0.0044554000, 0.0044341000, 0.0044505000, 0.0044883000, 0.0045753000, 0.0047760000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003973400, -0.003973700, -0.003974400, -0.003973400, -0.003971200, -0.003965900, -0.003953900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025130000; - } - pin ("A3") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039755000, 0.0039845000, 0.0040053000, 0.0040072000, 0.0040116000, 0.0040218000, 0.0040454000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004001300, -0.004000000, -0.003996800, -0.003997000, -0.003997500, -0.003998700, -0.004001500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024330000; - } - pin ("B1") { - capacitance : 0.0022850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041461000, 0.0041378000, 0.0041187000, 0.0041344000, 0.0041706000, 0.0042541000, 0.0044464000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001723000, -0.001724800, -0.001728900, -0.001727900, -0.001725500, -0.001719900, -0.001707100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024480000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0048575000, 0.0038501000, 0.0015950000, -0.003523800, -0.015130300, -0.041396800, -0.100742800", \ - "0.0047079000, 0.0037166000, 0.0014862000, -0.003623900, -0.015214000, -0.041473700, -0.100839900", \ - "0.0044972000, 0.0035109000, 0.0012917000, -0.003772800, -0.015318500, -0.041575100, -0.100912300", \ - "0.0042556000, 0.0033071000, 0.0010998000, -0.003950800, -0.015480600, -0.041669600, -0.100992600", \ - "0.0041471000, 0.0031763000, 0.0009272000, -0.004131500, -0.015611100, -0.041789700, -0.101072500", \ - "0.0045445000, 0.0035005000, 0.0011798000, -0.004017900, -0.015670300, -0.041807100, -0.101105600", \ - "0.0057292000, 0.0046669000, 0.0022447000, -0.003067900, -0.014928500, -0.041495600, -0.101076400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0074447000, 0.0085460000, 0.0109606000, 0.0162144000, 0.0279627000, 0.0542169000, 0.1124763000", \ - "0.0072095000, 0.0083207000, 0.0107787000, 0.0160947000, 0.0277699000, 0.0541156000, 0.1124736000", \ - "0.0069624000, 0.0080551000, 0.0104799000, 0.0157748000, 0.0275142000, 0.0538848000, 0.1133765000", \ - "0.0068003000, 0.0078512000, 0.0102027000, 0.0154701000, 0.0272534000, 0.0539370000, 0.1129470000", \ - "0.0066814000, 0.0077009000, 0.0100253000, 0.0152346000, 0.0270418000, 0.0531603000, 0.1121154000", \ - "0.0066591000, 0.0076847000, 0.0099912000, 0.0152201000, 0.0268544000, 0.0532615000, 0.1126165000", \ - "0.0068288000, 0.0078109000, 0.0100112000, 0.0150597000, 0.0269197000, 0.0534036000, 0.1124058000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0052581000, 0.0042562000, 0.0019936000, -0.003135600, -0.014734800, -0.041008400, -0.100371900", \ - "0.0051505000, 0.0041418000, 0.0018806000, -0.003236200, -0.014830200, -0.041103600, -0.100445800", \ - "0.0049882000, 0.0039885000, 0.0017472000, -0.003360400, -0.014929500, -0.041177900, -0.100547400", \ - "0.0047921000, 0.0038119000, 0.0015924000, -0.003481100, -0.015032500, -0.041269900, -0.100625000", \ - "0.0046758000, 0.0036989000, 0.0014410000, -0.003617800, -0.015092100, -0.041333500, -0.100646300", \ - "0.0048531000, 0.0038441000, 0.0015712000, -0.003607900, -0.015292100, -0.041450400, -0.100698400", \ - "0.0056227000, 0.0046119000, 0.0022411000, -0.003074300, -0.014850500, -0.041354500, -0.100673800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0105044000, 0.0115336000, 0.0138467000, 0.0190123000, 0.0305938000, 0.0566576000, 0.1152978000", \ - "0.0103186000, 0.0113680000, 0.0137188000, 0.0189277000, 0.0305435000, 0.0566270000, 0.1152695000", \ - "0.0101085000, 0.0111599000, 0.0135146000, 0.0187769000, 0.0304411000, 0.0565494000, 0.1153463000", \ - "0.0098967000, 0.0109322000, 0.0132767000, 0.0185288000, 0.0302112000, 0.0564422000, 0.1151728000", \ - "0.0097351000, 0.0107572000, 0.0130666000, 0.0182637000, 0.0299149000, 0.0561248000, 0.1150260000", \ - "0.0095739000, 0.0106168000, 0.0129439000, 0.0181525000, 0.0298411000, 0.0559879000, 0.1146599000", \ - "0.0094617000, 0.0104363000, 0.0126913000, 0.0178776000, 0.0296944000, 0.0557886000, 0.1148053000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0050386000, 0.0040365000, 0.0017772000, -0.003356600, -0.014961000, -0.041240200, -0.100599200", \ - "0.0049207000, 0.0039218000, 0.0016614000, -0.003469200, -0.015061700, -0.041322500, -0.100686700", \ - "0.0047737000, 0.0037727000, 0.0015255000, -0.003572900, -0.015152300, -0.041416800, -0.100787100", \ - "0.0045924000, 0.0036100000, 0.0013765000, -0.003697800, -0.015257200, -0.041494100, -0.100821700", \ - "0.0045155000, 0.0035200000, 0.0012760000, -0.003797200, -0.015349400, -0.041566200, -0.100899000", \ - "0.0046933000, 0.0037256000, 0.0014366000, -0.003753500, -0.015472400, -0.041637300, -0.100925600", \ - "0.0054709000, 0.0044180000, 0.0020926000, -0.003165700, -0.014950800, -0.041467100, -0.100846800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0133282000, 0.0143469000, 0.0166684000, 0.0218295000, 0.0334432000, 0.0595016000, 0.1182224000", \ - "0.0132051000, 0.0142617000, 0.0165574000, 0.0217422000, 0.0333834000, 0.0594335000, 0.1181608000", \ - "0.0130676000, 0.0140838000, 0.0164288000, 0.0216129000, 0.0332383000, 0.0593470000, 0.1181324000", \ - "0.0129267000, 0.0139546000, 0.0162898000, 0.0215098000, 0.0331737000, 0.0592686000, 0.1180301000", \ - "0.0128406000, 0.0138727000, 0.0161508000, 0.0213461000, 0.0329978000, 0.0591425000, 0.1179213000", \ - "0.0127488000, 0.0137703000, 0.0161060000, 0.0213306000, 0.0330275000, 0.0591750000, 0.1178307000", \ - "0.0129726000, 0.0139800000, 0.0161957000, 0.0212520000, 0.0331883000, 0.0593089000, 0.1181791000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0001940000, -0.000745300, -0.002937800, -0.008029400, -0.019662800, -0.045979500, -0.105424900", \ - "4.980000e-05, -0.000862000, -0.003011200, -0.008044300, -0.019609600, -0.045908500, -0.105328300", \ - "-0.000161200, -0.001057900, -0.003153800, -0.008131800, -0.019639400, -0.045872300, -0.105268100", \ - "-0.000422800, -0.001333900, -0.003419500, -0.008349300, -0.019786700, -0.045937400, -0.105277800", \ - "-0.000216000, -0.001204400, -0.003398800, -0.008496400, -0.019922200, -0.046080300, -0.105362100", \ - "0.0002793000, -0.000789000, -0.003121800, -0.008179700, -0.020021000, -0.046049600, -0.105349700", \ - "0.0020561000, 0.0008724000, -0.001695800, -0.007086600, -0.019082000, -0.045497100, -0.105305000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0106109000, 0.0116544000, 0.0140461000, 0.0192794000, 0.0310038000, 0.0571238000, 0.1158343000", \ - "0.0103885000, 0.0114831000, 0.0138224000, 0.0191073000, 0.0308986000, 0.0570233000, 0.1157900000", \ - "0.0101478000, 0.0112103000, 0.0135310000, 0.0188488000, 0.0306817000, 0.0569193000, 0.1157519000", \ - "0.0100599000, 0.0110996000, 0.0133713000, 0.0186215000, 0.0303849000, 0.0566666000, 0.1155888000", \ - "0.0100122000, 0.0110199000, 0.0133179000, 0.0184996000, 0.0301820000, 0.0563213000, 0.1153170000", \ - "0.0104560000, 0.0114401000, 0.0136688000, 0.0187372000, 0.0302281000, 0.0562308000, 0.1149740000", \ - "0.0125951000, 0.0136918000, 0.0150305000, 0.0213537000, 0.0317599000, 0.0572466000, 0.1153903000"); - } - } - max_capacitance : 0.0659280000; - max_transition : 1.4930320000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0378727000, 0.0426639000, 0.0531889000, 0.0757871000, 0.1243397000, 0.2323774000, 0.4737301000", \ - "0.0413618000, 0.0462801000, 0.0568261000, 0.0792912000, 0.1280167000, 0.2359870000, 0.4781243000", \ - "0.0504667000, 0.0553040000, 0.0658439000, 0.0884170000, 0.1374280000, 0.2453812000, 0.4874620000", \ - "0.0702364000, 0.0757636000, 0.0881464000, 0.1109384000, 0.1598135000, 0.2679122000, 0.5093467000", \ - "0.0929778000, 0.1017745000, 0.1195651000, 0.1527424000, 0.2111890000, 0.3197584000, 0.5614312000", \ - "0.1118195000, 0.1249750000, 0.1514090000, 0.2009871000, 0.2888195000, 0.4320461000, 0.6803142000", \ - "0.1018308000, 0.1217189000, 0.1608224000, 0.2373249000, 0.3704348000, 0.5884229000, 0.9369858000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0745366000, 0.0844091000, 0.1056786000, 0.1520636000, 0.2553117000, 0.4874864000, 1.0015456000", \ - "0.0789484000, 0.0887694000, 0.1103170000, 0.1572039000, 0.2614229000, 0.4964756000, 1.0082489000", \ - "0.0913259000, 0.1008260000, 0.1223358000, 0.1691824000, 0.2738779000, 0.5087046000, 1.0308722000", \ - "0.1203027000, 0.1297836000, 0.1507067000, 0.1974807000, 0.3011466000, 0.5355577000, 1.0560687000", \ - "0.1736584000, 0.1859364000, 0.2111824000, 0.2603199000, 0.3640539000, 0.5975310000, 1.1158470000", \ - "0.2582014000, 0.2773756000, 0.3147497000, 0.3830121000, 0.5064347000, 0.7408232000, 1.2661490000", \ - "0.3900017000, 0.4208301000, 0.4808997000, 0.5881194000, 0.7654230000, 1.0678005000, 1.6008015000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0353066000, 0.0407895000, 0.0532129000, 0.0814766000, 0.1447502000, 0.2879651000, 0.6099952000", \ - "0.0350682000, 0.0406220000, 0.0532302000, 0.0814258000, 0.1448403000, 0.2880577000, 0.6113243000", \ - "0.0348578000, 0.0405096000, 0.0526535000, 0.0811441000, 0.1447201000, 0.2885344000, 0.6116116000", \ - "0.0449254000, 0.0510226000, 0.0610376000, 0.0851855000, 0.1450817000, 0.2879682000, 0.6111642000", \ - "0.0672927000, 0.0744989000, 0.0882001000, 0.1157378000, 0.1666756000, 0.2931532000, 0.6105472000", \ - "0.1076861000, 0.1181775000, 0.1386392000, 0.1763251000, 0.2417921000, 0.3581425000, 0.6304436000", \ - "0.1782922000, 0.1948078000, 0.2290662000, 0.2833083000, 0.3752914000, 0.5341649000, 0.7928446000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0492712000, 0.0614271000, 0.0887711000, 0.1511295000, 0.2915366000, 0.6117107000, 1.3096066000", \ - "0.0491756000, 0.0614743000, 0.0888034000, 0.1510484000, 0.2906627000, 0.6079774000, 1.3125441000", \ - "0.0494031000, 0.0615100000, 0.0888437000, 0.1505497000, 0.2897216000, 0.6050784000, 1.3240510000", \ - "0.0511087000, 0.0623875000, 0.0892065000, 0.1508074000, 0.2901809000, 0.6092296000, 1.3137993000", \ - "0.0691382000, 0.0803232000, 0.1031161000, 0.1577421000, 0.2912007000, 0.6043102000, 1.3094937000", \ - "0.1101107000, 0.1229082000, 0.1502115000, 0.2060311000, 0.3209326000, 0.6108278000, 1.3196484000", \ - "0.1958590000, 0.2125171000, 0.2473129000, 0.3144203000, 0.4424596000, 0.7037738000, 1.3335933000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0451720000, 0.0501147000, 0.0605230000, 0.0829548000, 0.1316200000, 0.2395004000, 0.4816105000", \ - "0.0492550000, 0.0540396000, 0.0645909000, 0.0868882000, 0.1356716000, 0.2435935000, 0.4850749000", \ - "0.0581510000, 0.0629856000, 0.0734701000, 0.0959328000, 0.1447975000, 0.2527769000, 0.4942972000", \ - "0.0765893000, 0.0820590000, 0.0936692000, 0.1167871000, 0.1659565000, 0.2740740000, 0.5158708000", \ - "0.1022696000, 0.1103035000, 0.1258264000, 0.1562286000, 0.2127762000, 0.3229077000, 0.5655448000", \ - "0.1267734000, 0.1388469000, 0.1631107000, 0.2085488000, 0.2893483000, 0.4258944000, 0.6784608000", \ - "0.1258007000, 0.1444881000, 0.1828433000, 0.2543967000, 0.3779522000, 0.5823707000, 0.9075063000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1022718000, 0.1128218000, 0.1356714000, 0.1865906000, 0.3002021000, 0.5555301000, 1.1306988000", \ - "0.1067194000, 0.1174487000, 0.1404984000, 0.1918376000, 0.3058678000, 0.5611773000, 1.1359765000", \ - "0.1189296000, 0.1293216000, 0.1526590000, 0.2043038000, 0.3188925000, 0.5748364000, 1.1498870000", \ - "0.1470825000, 0.1574013000, 0.1804664000, 0.2320723000, 0.3469085000, 0.6034073000, 1.1790202000", \ - "0.2040384000, 0.2157504000, 0.2406162000, 0.2923437000, 0.4068843000, 0.6637401000, 1.2401362000", \ - "0.3012489000, 0.3178172000, 0.3506624000, 0.4171514000, 0.5439737000, 0.8008150000, 1.3788513000", \ - "0.4586946000, 0.4843455000, 0.5359129000, 0.6323647000, 0.8035834000, 1.1109780000, 1.6965458000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0350468000, 0.0405830000, 0.0531072000, 0.0813994000, 0.1449217000, 0.2882656000, 0.6106278000", \ - "0.0349415000, 0.0405850000, 0.0531425000, 0.0813221000, 0.1448603000, 0.2883702000, 0.6101298000", \ - "0.0350820000, 0.0405863000, 0.0529515000, 0.0811325000, 0.1448448000, 0.2882448000, 0.6106248000", \ - "0.0423203000, 0.0474268000, 0.0580573000, 0.0837754000, 0.1450922000, 0.2881845000, 0.6108742000", \ - "0.0615040000, 0.0674027000, 0.0798364000, 0.1051312000, 0.1587619000, 0.2917492000, 0.6101821000", \ - "0.1000440000, 0.1080380000, 0.1246434000, 0.1572118000, 0.2168642000, 0.3348037000, 0.6242613000", \ - "0.1692431000, 0.1811687000, 0.2062824000, 0.2526251000, 0.3336668000, 0.4741887000, 0.7375779000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0727070000, 0.0864534000, 0.1169614000, 0.1860025000, 0.3415814000, 0.6903667000, 1.4804625000", \ - "0.0727784000, 0.0864633000, 0.1170315000, 0.1860031000, 0.3410226000, 0.6894333000, 1.4751703000", \ - "0.0728064000, 0.0864363000, 0.1170130000, 0.1861037000, 0.3416011000, 0.6891207000, 1.4758972000", \ - "0.0730922000, 0.0865245000, 0.1170884000, 0.1860795000, 0.3407884000, 0.6902640000, 1.4749287000", \ - "0.0865443000, 0.0986928000, 0.1259222000, 0.1901462000, 0.3410140000, 0.6922542000, 1.4796082000", \ - "0.1244909000, 0.1382502000, 0.1675244000, 0.2296527000, 0.3638743000, 0.6926162000, 1.4808886000", \ - "0.2086293000, 0.2259133000, 0.2615695000, 0.3328414000, 0.4735319000, 0.7659134000, 1.4930318000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0482910000, 0.0532109000, 0.0636221000, 0.0860688000, 0.1348342000, 0.2427032000, 0.4844560000", \ - "0.0524105000, 0.0572593000, 0.0677430000, 0.0901419000, 0.1389741000, 0.2468750000, 0.4884050000", \ - "0.0607661000, 0.0656894000, 0.0761763000, 0.0986353000, 0.1474696000, 0.2555169000, 0.4969429000", \ - "0.0773502000, 0.0824367000, 0.0935835000, 0.1164991000, 0.1654378000, 0.2736298000, 0.5156156000", \ - "0.1026623000, 0.1095950000, 0.1230820000, 0.1505541000, 0.2049659000, 0.3144109000, 0.5566825000", \ - "0.1304985000, 0.1405685000, 0.1609696000, 0.2013303000, 0.2720058000, 0.4014081000, 0.6522026000", \ - "0.1399980000, 0.1559438000, 0.1890701000, 0.2509187000, 0.3603359000, 0.5391577000, 0.8420571000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1067420000, 0.1161952000, 0.1378286000, 0.1850134000, 0.2904207000, 0.5262297000, 1.0563411000", \ - "0.1116382000, 0.1215255000, 0.1430993000, 0.1906522000, 0.2958569000, 0.5319061000, 1.0622212000", \ - "0.1247764000, 0.1343877000, 0.1559836000, 0.2035842000, 0.3093718000, 0.5451529000, 1.0749103000", \ - "0.1515911000, 0.1615371000, 0.1830810000, 0.2306312000, 0.3363142000, 0.5725920000, 1.1029823000", \ - "0.2059093000, 0.2171774000, 0.2401946000, 0.2878824000, 0.3935738000, 0.6298991000, 1.1601498000", \ - "0.2997492000, 0.3137070000, 0.3431569000, 0.4034295000, 0.5211296000, 0.7593891000, 1.2906427000", \ - "0.4492663000, 0.4709248000, 0.5145900000, 0.5999393000, 0.7602763000, 1.0457377000, 1.5890412000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0349439000, 0.0405124000, 0.0531272000, 0.0812989000, 0.1449348000, 0.2878140000, 0.6111538000", \ - "0.0348025000, 0.0404936000, 0.0530268000, 0.0813724000, 0.1449385000, 0.2884240000, 0.6103477000", \ - "0.0350262000, 0.0404193000, 0.0530075000, 0.0812742000, 0.1447705000, 0.2878316000, 0.6119166000", \ - "0.0395937000, 0.0446178000, 0.0560518000, 0.0828269000, 0.1450164000, 0.2878539000, 0.6111442000", \ - "0.0547451000, 0.0602503000, 0.0724896000, 0.0979750000, 0.1545550000, 0.2906122000, 0.6114363000", \ - "0.0894668000, 0.0968370000, 0.1114878000, 0.1404619000, 0.1977266000, 0.3235530000, 0.6208484000", \ - "0.1561145000, 0.1667931000, 0.1870070000, 0.2259065000, 0.2978826000, 0.4320004000, 0.7095801000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0803636000, 0.0930180000, 0.1214322000, 0.1851695000, 0.3285814000, 0.6516920000, 1.3790930000", \ - "0.0803296000, 0.0930058000, 0.1214981000, 0.1856070000, 0.3289057000, 0.6507316000, 1.3784653000", \ - "0.0803039000, 0.0929893000, 0.1213757000, 0.1851409000, 0.3285521000, 0.6501550000, 1.3769118000", \ - "0.0803321000, 0.0930789000, 0.1214913000, 0.1854450000, 0.3289420000, 0.6504497000, 1.3758177000", \ - "0.0926599000, 0.1037787000, 0.1296821000, 0.1894315000, 0.3288698000, 0.6510746000, 1.3781667000", \ - "0.1293889000, 0.1420513000, 0.1698046000, 0.2280150000, 0.3534464000, 0.6571620000, 1.3775185000", \ - "0.2105201000, 0.2260680000, 0.2598899000, 0.3265750000, 0.4622100000, 0.7362915000, 1.4002204000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0162661000, 0.0184681000, 0.0233374000, 0.0339101000, 0.0574340000, 0.1103052000, 0.2292388000", \ - "0.0209533000, 0.0232270000, 0.0281437000, 0.0386722000, 0.0623292000, 0.1152228000, 0.2342302000", \ - "0.0288437000, 0.0321345000, 0.0386319000, 0.0501325000, 0.0735259000, 0.1264934000, 0.2455063000", \ - "0.0375491000, 0.0429966000, 0.0534998000, 0.0713180000, 0.1001089000, 0.1529936000, 0.2707184000", \ - "0.0442047000, 0.0528616000, 0.0690829000, 0.0977788000, 0.1427652000, 0.2132203000, 0.3328298000", \ - "0.0399215000, 0.0534286000, 0.0792417000, 0.1233787000, 0.1960328000, 0.3040733000, 0.4684660000", \ - "-0.000617700, 0.0211681000, 0.0612476000, 0.1314908000, 0.2448462000, 0.4177132000, 0.6747672000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0868784000, 0.0970621000, 0.1189161000, 0.1667953000, 0.2727664000, 0.5090702000, 1.0392847000", \ - "0.0903231000, 0.1002248000, 0.1218885000, 0.1703140000, 0.2767379000, 0.5133781000, 1.0440240000", \ - "0.0998490000, 0.1100033000, 0.1317183000, 0.1800647000, 0.2869821000, 0.5243096000, 1.0558431000", \ - "0.1275579000, 0.1374782000, 0.1583156000, 0.2059299000, 0.3122852000, 0.5496074000, 1.0816076000", \ - "0.1902940000, 0.2016563000, 0.2254372000, 0.2726659000, 0.3778934000, 0.6133919000, 1.1461952000", \ - "0.2918856000, 0.3089789000, 0.3443243000, 0.4119170000, 0.5324829000, 0.7665464000, 1.2958103000", \ - "0.4530502000, 0.4764500000, 0.5303235000, 0.6325723000, 0.8170156000, 1.1189447000, 1.6424568000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0132676000, 0.0163363000, 0.0228827000, 0.0368678000, 0.0677984000, 0.1373919000, 0.2950742000", \ - "0.0140146000, 0.0167518000, 0.0229258000, 0.0368724000, 0.0678328000, 0.1373745000, 0.2953384000", \ - "0.0215074000, 0.0233172000, 0.0275708000, 0.0388675000, 0.0678875000, 0.1373418000, 0.2951514000", \ - "0.0365074000, 0.0388326000, 0.0440298000, 0.0542922000, 0.0766540000, 0.1386210000, 0.2949382000", \ - "0.0628433000, 0.0664004000, 0.0740463000, 0.0878507000, 0.1144524000, 0.1641246000, 0.2992316000", \ - "0.1097230000, 0.1149740000, 0.1259297000, 0.1490551000, 0.1866477000, 0.2550993000, 0.3636254000", \ - "0.1949487000, 0.2036187000, 0.2204874000, 0.2527992000, 0.3112928000, 0.4099863000, 0.5632628000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0804123000, 0.0928519000, 0.1216244000, 0.1850273000, 0.3287054000, 0.6520252000, 1.3800847000", \ - "0.0802919000, 0.0929689000, 0.1212814000, 0.1850261000, 0.3288743000, 0.6501680000, 1.3767986000", \ - "0.0801169000, 0.0928659000, 0.1213751000, 0.1853380000, 0.3286137000, 0.6512136000, 1.3812305000", \ - "0.0809714000, 0.0933724000, 0.1208623000, 0.1852513000, 0.3287018000, 0.6504685000, 1.3762169000", \ - "0.1069773000, 0.1164817000, 0.1386339000, 0.1944035000, 0.3291927000, 0.6508163000, 1.3778632000", \ - "0.1571214000, 0.1731099000, 0.2040646000, 0.2620175000, 0.3729564000, 0.6589590000, 1.3767543000", \ - "0.2390592000, 0.2622752000, 0.3113963000, 0.3945715000, 0.5420259000, 0.7830692000, 1.4100728000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31oi_2") { - leakage_power () { - value : 0.0027951000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0008266000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0008558000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0008588000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0015629000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0008723000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0013812000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0027951000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0013766000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0003247000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0031468000; - when : "A1&A2&A3&!B1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__a31oi"; - cell_leakage_power : 0.0019232090; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0094098000, 0.0094125000, 0.0094188000, 0.0094151000, 0.0094066000, 0.0093870000, 0.0093419000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007150000, -0.007152300, -0.007157600, -0.007143600, -0.007111300, -0.007036900, -0.006865400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045620000; - } - pin ("A2") { - capacitance : 0.0043430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084257000, 0.0084129000, 0.0083835000, 0.0084147000, 0.0084868000, 0.0086530000, 0.0090360000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007789300, -0.007789100, -0.007788500, -0.007786500, -0.007781900, -0.007771200, -0.007746600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045190000; - } - pin ("A3") { - capacitance : 0.0044070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078495000, 0.0078554000, 0.0078692000, 0.0078732000, 0.0078825000, 0.0079038000, 0.0079530000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007877400, -0.007877800, -0.007878900, -0.007877400, -0.007873900, -0.007865800, -0.007847200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046550000; - } - pin ("B1") { - capacitance : 0.0043920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049663000, 0.0049504000, 0.0049138000, 0.0049500000, 0.0050336000, 0.0052262000, 0.0056701000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003516500, -0.003517900, -0.003521300, -0.003521000, -0.003520200, -0.003518500, -0.003514600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047080000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0098799000, 0.0086903000, 0.0057383000, -0.001544200, -0.019906600, -0.065693200, -0.179911100", \ - "0.0096331000, 0.0084551000, 0.0055546000, -0.001751900, -0.020102400, -0.065903800, -0.180093900", \ - "0.0091989000, 0.0080217000, 0.0051502000, -0.002093800, -0.020369800, -0.066073300, -0.180167700", \ - "0.0086756000, 0.0075326000, 0.0046464000, -0.002508200, -0.020709100, -0.066324800, -0.180400500", \ - "0.0082564000, 0.0071271000, 0.0043263000, -0.002888400, -0.021035700, -0.066569200, -0.180537200", \ - "0.0090202000, 0.0076992000, 0.0047001000, -0.003017300, -0.021131100, -0.066671100, -0.180673700", \ - "0.0107110000, 0.0093999000, 0.0062350000, -0.001331400, -0.020191000, -0.066530400, -0.180813800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0151280000, 0.0164596000, 0.0196623000, 0.0273473000, 0.0457473000, 0.0912960000, 0.2042296000", \ - "0.0146648000, 0.0160109000, 0.0192598000, 0.0269821000, 0.0456307000, 0.0912841000, 0.2043027000", \ - "0.0141442000, 0.0154436000, 0.0186976000, 0.0265156000, 0.0452746000, 0.0913990000, 0.2042526000", \ - "0.0137499000, 0.0150188000, 0.0181827000, 0.0258088000, 0.0446727000, 0.0907269000, 0.2040701000", \ - "0.0134945000, 0.0147407000, 0.0177767000, 0.0253208000, 0.0441100000, 0.0906237000, 0.2043750000", \ - "0.0134082000, 0.0146610000, 0.0176931000, 0.0252506000, 0.0437472000, 0.0898241000, 0.2042141000", \ - "0.0133907000, 0.0144573000, 0.0174570000, 0.0247172000, 0.0436857000, 0.0896745000, 0.2035164000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0107967000, 0.0096117000, 0.0066646000, -0.000694300, -0.019027300, -0.064854300, -0.179005000", \ - "0.0105867000, 0.0093977000, 0.0064486000, -0.000885400, -0.019209000, -0.065025900, -0.179150300", \ - "0.0102467000, 0.0090734000, 0.0061675000, -0.001138400, -0.019431800, -0.065183300, -0.179331300", \ - "0.0098133000, 0.0086622000, 0.0057888000, -0.001468600, -0.019714400, -0.065377400, -0.179447000", \ - "0.0094680000, 0.0082915000, 0.0054430000, -0.001759600, -0.019909500, -0.065538400, -0.179559200", \ - "0.0096648000, 0.0084802000, 0.0054999000, -0.001886700, -0.020350400, -0.065862700, -0.179804400", \ - "0.0107866000, 0.0095500000, 0.0065401000, -0.000988700, -0.019639100, -0.065856700, -0.179814200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0214001000, 0.0225943000, 0.0256062000, 0.0330372000, 0.0514638000, 0.0968632000, 0.2096911000", \ - "0.0211438000, 0.0223414000, 0.0253867000, 0.0328861000, 0.0513983000, 0.0968656000, 0.2097353000", \ - "0.0207248000, 0.0219689000, 0.0250418000, 0.0326138000, 0.0511642000, 0.0967639000, 0.2097393000", \ - "0.0203536000, 0.0215459000, 0.0245744000, 0.0321616000, 0.0507498000, 0.0965342000, 0.2095595000", \ - "0.0199379000, 0.0211690000, 0.0241971000, 0.0317107000, 0.0502033000, 0.0959978000, 0.2093558000", \ - "0.0196921000, 0.0209174000, 0.0239524000, 0.0314610000, 0.0499435000, 0.0955724000, 0.2086669000", \ - "0.0190553000, 0.0202163000, 0.0231896000, 0.0306716000, 0.0495243000, 0.0954283000, 0.2086831000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0107518000, 0.0095693000, 0.0066295000, -0.000719900, -0.019074200, -0.064847700, -0.179067700", \ - "0.0105257000, 0.0093461000, 0.0063907000, -0.000951700, -0.019293700, -0.065040600, -0.179230900", \ - "0.0101705000, 0.0090024000, 0.0060905000, -0.001205600, -0.019517000, -0.065252900, -0.179445800", \ - "0.0097143000, 0.0085546000, 0.0056344000, -0.001596200, -0.019769400, -0.065445400, -0.179566700", \ - "0.0093286000, 0.0081818000, 0.0053012000, -0.001889400, -0.020008300, -0.065609400, -0.179650400", \ - "0.0095460000, 0.0083293000, 0.0053971000, -0.001923200, -0.020501100, -0.065947200, -0.179854300", \ - "0.0106948000, 0.0094216000, 0.0064352000, -0.001097100, -0.019718700, -0.065936200, -0.179824500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0278990000, 0.0291234000, 0.0321141000, 0.0395739000, 0.0579984000, 0.1036207000, 0.2166322000", \ - "0.0276298000, 0.0288626000, 0.0318611000, 0.0393429000, 0.0577906000, 0.1034004000, 0.2164345000", \ - "0.0273012000, 0.0284929000, 0.0315694000, 0.0391145000, 0.0576334000, 0.1032332000, 0.2162572000", \ - "0.0269555000, 0.0282015000, 0.0312267000, 0.0387713000, 0.0573218000, 0.1030778000, 0.2161716000", \ - "0.0267133000, 0.0279199000, 0.0309500000, 0.0384838000, 0.0570225000, 0.1028799000, 0.2159619000", \ - "0.0265779000, 0.0278346000, 0.0309274000, 0.0384706000, 0.0570073000, 0.1027723000, 0.2158181000", \ - "0.0265091000, 0.0276404000, 0.0305824000, 0.0381250000, 0.0570330000, 0.1028396000, 0.2161931000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("-0.000295900, -0.001377500, -0.004183200, -0.011441000, -0.029814200, -0.075753700, -0.190101000", \ - "-0.000617300, -0.001661300, -0.004387000, -0.011492800, -0.029745900, -0.075612100, -0.189916400", \ - "-0.001008000, -0.002040700, -0.004701500, -0.011710300, -0.029778700, -0.075530200, -0.189768400", \ - "-0.001375400, -0.002363600, -0.005193200, -0.012111400, -0.030070800, -0.075602900, -0.189728900", \ - "-0.000944100, -0.002117600, -0.004988500, -0.012122800, -0.030403700, -0.075815900, -0.189816500", \ - "-0.000111800, -0.001472100, -0.004550800, -0.011872500, -0.029994700, -0.075964000, -0.189979900", \ - "0.0031092000, 0.0017263000, -0.001652900, -0.009599400, -0.028667800, -0.074318100, -0.189503300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012431530, 0.0030908590, 0.0076848220, 0.0191068200, 0.0475054100, 0.1181130000"); - values("0.0251162000, 0.0264515000, 0.0295459000, 0.0372352000, 0.0558975000, 0.1015963000, 0.2146825000", \ - "0.0247741000, 0.0260065000, 0.0291507000, 0.0368679000, 0.0556773000, 0.1015928000, 0.2146177000", \ - "0.0243392000, 0.0256134000, 0.0287105000, 0.0363821000, 0.0551817000, 0.1011823000, 0.2144933000", \ - "0.0240151000, 0.0252548000, 0.0282481000, 0.0358592000, 0.0545944000, 0.1007613000, 0.2141288000", \ - "0.0238519000, 0.0250303000, 0.0280653000, 0.0355753000, 0.0541417000, 0.1000092000, 0.2135297000", \ - "0.0250787000, 0.0261998000, 0.0291214000, 0.0365441000, 0.0549510000, 0.0997917000, 0.2127271000", \ - "0.0278534000, 0.0289992000, 0.0316533000, 0.0383481000, 0.0559975000, 0.1007906000, 0.2127658000"); - } - } - max_capacitance : 0.1181130000; - max_transition : 1.4952570000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0437825000, 0.0475475000, 0.0563683000, 0.0771605000, 0.1260529000, 0.2438415000, 0.5332076000", \ - "0.0472867000, 0.0510624000, 0.0600217000, 0.0809472000, 0.1296385000, 0.2477874000, 0.5371041000", \ - "0.0562562000, 0.0600454000, 0.0690206000, 0.0900067000, 0.1391126000, 0.2570586000, 0.5469041000", \ - "0.0780847000, 0.0822746000, 0.0918173000, 0.1126025000, 0.1617254000, 0.2798674000, 0.5687148000", \ - "0.1056485000, 0.1118654000, 0.1257022000, 0.1558597000, 0.2142027000, 0.3326056000, 0.6211858000", \ - "0.1299914000, 0.1393014000, 0.1603713000, 0.2060020000, 0.2919030000, 0.4494630000, 0.7455627000", \ - "0.1285278000, 0.1424212000, 0.1733546000, 0.2421298000, 0.3762751000, 0.6150253000, 1.0164897000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0811107000, 0.0876962000, 0.1037586000, 0.1419459000, 0.2334235000, 0.4594151000, 1.0191952000", \ - "0.0851469000, 0.0918385000, 0.1081451000, 0.1466303000, 0.2389881000, 0.4654094000, 1.0256389000", \ - "0.0973830000, 0.1040645000, 0.1201072000, 0.1592391000, 0.2521738000, 0.4810243000, 1.0401739000", \ - "0.1275798000, 0.1339421000, 0.1494874000, 0.1879548000, 0.2813753000, 0.5096445000, 1.0712580000", \ - "0.1845705000, 0.1926092000, 0.2111745000, 0.2520301000, 0.3451914000, 0.5752782000, 1.1368783000", \ - "0.2767551000, 0.2889379000, 0.3160762000, 0.3731505000, 0.4859095000, 0.7192901000, 1.2874336000", \ - "0.4192404000, 0.4390803000, 0.4850920000, 0.5754909000, 0.7427775000, 1.0431163000, 1.6224860000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0434670000, 0.0474350000, 0.0574800000, 0.0828449000, 0.1456033000, 0.3035531000, 0.6961279000", \ - "0.0432480000, 0.0471879000, 0.0573241000, 0.0827530000, 0.1459242000, 0.3034411000, 0.6964533000", \ - "0.0420014000, 0.0459185000, 0.0564229000, 0.0823896000, 0.1458708000, 0.3033531000, 0.6959283000", \ - "0.0510973000, 0.0545225000, 0.0630255000, 0.0852800000, 0.1458659000, 0.3030601000, 0.6960523000", \ - "0.0716376000, 0.0769936000, 0.0892497000, 0.1153558000, 0.1663500000, 0.3068157000, 0.6958849000", \ - "0.1138361000, 0.1218365000, 0.1386365000, 0.1729964000, 0.2423219000, 0.3691671000, 0.7072549000", \ - "0.1863940000, 0.1982003000, 0.2249184000, 0.2776813000, 0.3744375000, 0.5440797000, 0.8600605000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0477130000, 0.0559325000, 0.0763447000, 0.1268999000, 0.2512880000, 0.5609587000, 1.3320217000", \ - "0.0479342000, 0.0560943000, 0.0764465000, 0.1268952000, 0.2514159000, 0.5599007000, 1.3321869000", \ - "0.0480465000, 0.0561950000, 0.0763990000, 0.1269975000, 0.2512955000, 0.5623801000, 1.3260297000", \ - "0.0489565000, 0.0568268000, 0.0768644000, 0.1269841000, 0.2511498000, 0.5611802000, 1.3268856000", \ - "0.0642234000, 0.0720215000, 0.0892123000, 0.1341713000, 0.2527009000, 0.5641815000, 1.3312518000", \ - "0.1007891000, 0.1093828000, 0.1303660000, 0.1776898000, 0.2841120000, 0.5670919000, 1.3382354000", \ - "0.1800636000, 0.1927415000, 0.2197419000, 0.2772258000, 0.3971342000, 0.6587531000, 1.3495898000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0519063000, 0.0555187000, 0.0645168000, 0.0851480000, 0.1340065000, 0.2519625000, 0.5413185000", \ - "0.0558375000, 0.0594970000, 0.0683620000, 0.0891687000, 0.1380023000, 0.2560464000, 0.5451227000", \ - "0.0640300000, 0.0676575000, 0.0765732000, 0.0973642000, 0.1463398000, 0.2642221000, 0.5536359000", \ - "0.0811143000, 0.0851655000, 0.0948517000, 0.1164059000, 0.1655284000, 0.2838114000, 0.5738934000", \ - "0.1082115000, 0.1133171000, 0.1261514000, 0.1528659000, 0.2078507000, 0.3284851000, 0.6191600000", \ - "0.1362755000, 0.1442469000, 0.1629087000, 0.2019730000, 0.2789451000, 0.4235149000, 0.7237646000", \ - "0.1390885000, 0.1515853000, 0.1803450000, 0.2414311000, 0.3606028000, 0.5710172000, 0.9399518000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.1120437000, 0.1187694000, 0.1357593000, 0.1766832000, 0.2774264000, 0.5263233000, 1.1451744000", \ - "0.1169057000, 0.1237718000, 0.1406073000, 0.1822357000, 0.2831952000, 0.5323967000, 1.1503556000", \ - "0.1288580000, 0.1360125000, 0.1529230000, 0.1949584000, 0.2964967000, 0.5458905000, 1.1632337000", \ - "0.1587292000, 0.1654181000, 0.1826351000, 0.2243759000, 0.3264347000, 0.5765642000, 1.1946191000", \ - "0.2206564000, 0.2283182000, 0.2466021000, 0.2880612000, 0.3896434000, 0.6399418000, 1.2589297000", \ - "0.3285324000, 0.3387801000, 0.3627739000, 0.4171946000, 0.5318471000, 0.7835309000, 1.4059548000", \ - "0.5015469000, 0.5180543000, 0.5574318000, 0.6389112000, 0.7995859000, 1.1080024000, 1.7374010000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0428954000, 0.0470525000, 0.0571334000, 0.0824582000, 0.1458490000, 0.3031947000, 0.6960898000", \ - "0.0428038000, 0.0469153000, 0.0571100000, 0.0824757000, 0.1458158000, 0.3034394000, 0.6959947000", \ - "0.0426340000, 0.0465708000, 0.0567898000, 0.0823931000, 0.1457875000, 0.3034454000, 0.6954706000", \ - "0.0482340000, 0.0519602000, 0.0608575000, 0.0845899000, 0.1460915000, 0.3030973000, 0.6958492000", \ - "0.0648834000, 0.0688595000, 0.0790893000, 0.1030905000, 0.1581272000, 0.3065433000, 0.6956992000", \ - "0.1025215000, 0.1082205000, 0.1210601000, 0.1488861000, 0.2090084000, 0.3437231000, 0.7048042000", \ - "0.1714608000, 0.1799953000, 0.1991253000, 0.2395548000, 0.3176243000, 0.4709939000, 0.7991403000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0729178000, 0.0821080000, 0.1047185000, 0.1602937000, 0.2979253000, 0.6372682000, 1.4825833000", \ - "0.0730309000, 0.0820154000, 0.1046661000, 0.1604054000, 0.2976564000, 0.6376233000, 1.4824383000", \ - "0.0730377000, 0.0821677000, 0.1045370000, 0.1602221000, 0.2976483000, 0.6374802000, 1.4801164000", \ - "0.0732804000, 0.0822676000, 0.1047453000, 0.1604185000, 0.2986519000, 0.6386194000, 1.4801198000", \ - "0.0837979000, 0.0914900000, 0.1120462000, 0.1641823000, 0.2977405000, 0.6375720000, 1.4849160000", \ - "0.1198314000, 0.1289780000, 0.1511306000, 0.2027745000, 0.3208867000, 0.6417320000, 1.4874699000", \ - "0.2024464000, 0.2144188000, 0.2413422000, 0.3007654000, 0.4312690000, 0.7169590000, 1.4952567000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0574766000, 0.0612042000, 0.0700831000, 0.0908160000, 0.1397262000, 0.2575686000, 0.5469889000", \ - "0.0616058000, 0.0653471000, 0.0741838000, 0.0950288000, 0.1438918000, 0.2617904000, 0.5511353000", \ - "0.0696018000, 0.0733945000, 0.0823384000, 0.1031749000, 0.1521824000, 0.2701098000, 0.5592888000", \ - "0.0847024000, 0.0884255000, 0.0977656000, 0.1190149000, 0.1681076000, 0.2862555000, 0.5756670000", \ - "0.1077961000, 0.1127269000, 0.1235598000, 0.1482691000, 0.2015756000, 0.3213411000, 0.6114448000", \ - "0.1346315000, 0.1413463000, 0.1577502000, 0.1912478000, 0.2581215000, 0.3953219000, 0.6929061000", \ - "0.1393450000, 0.1492290000, 0.1732224000, 0.2261893000, 0.3279947000, 0.5131093000, 0.8620565000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.1297773000, 0.1365019000, 0.1529569000, 0.1939032000, 0.2931186000, 0.5358593000, 1.1364645000", \ - "0.1344239000, 0.1412300000, 0.1576995000, 0.1988587000, 0.2981196000, 0.5409549000, 1.1416257000", \ - "0.1468784000, 0.1536704000, 0.1708364000, 0.2111967000, 0.3107742000, 0.5541081000, 1.1548446000", \ - "0.1751966000, 0.1825649000, 0.1993134000, 0.2405027000, 0.3400878000, 0.5836382000, 1.1845567000", \ - "0.2360273000, 0.2433718000, 0.2603321000, 0.3012033000, 0.4006033000, 0.6443200000, 1.2459299000", \ - "0.3416107000, 0.3506525000, 0.3742955000, 0.4244322000, 0.5347581000, 0.7796682000, 1.3813007000", \ - "0.5160767000, 0.5303836000, 0.5634330000, 0.6357799000, 0.7866049000, 1.0822796000, 1.6953040000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0429050000, 0.0470330000, 0.0570731000, 0.0825861000, 0.1456931000, 0.3032144000, 0.6964472000", \ - "0.0428502000, 0.0469982000, 0.0571589000, 0.0825671000, 0.1457803000, 0.3032038000, 0.6960340000", \ - "0.0424865000, 0.0466547000, 0.0568890000, 0.0825472000, 0.1458424000, 0.3034020000, 0.6958692000", \ - "0.0458727000, 0.0497497000, 0.0592456000, 0.0837113000, 0.1458304000, 0.3030754000, 0.6960234000", \ - "0.0580094000, 0.0620776000, 0.0716327000, 0.0959706000, 0.1540634000, 0.3056299000, 0.6962083000", \ - "0.0906628000, 0.0954125000, 0.1064061000, 0.1324342000, 0.1905734000, 0.3325010000, 0.7035184000", \ - "0.1566774000, 0.1637725000, 0.1795081000, 0.2126149000, 0.2823337000, 0.4290307000, 0.7752199000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0902374000, 0.0992089000, 0.1211477000, 0.1754186000, 0.3090476000, 0.6413096000, 1.4629763000", \ - "0.0902409000, 0.0992175000, 0.1211619000, 0.1754086000, 0.3090132000, 0.6408131000, 1.4656776000", \ - "0.0902621000, 0.0991201000, 0.1211535000, 0.1753658000, 0.3094369000, 0.6412249000, 1.4619996000", \ - "0.0901280000, 0.0990966000, 0.1211294000, 0.1754394000, 0.3091820000, 0.6417249000, 1.4631593000", \ - "0.0979200000, 0.1065187000, 0.1266718000, 0.1782836000, 0.3094276000, 0.6413592000, 1.4653500000", \ - "0.1336698000, 0.1426408000, 0.1640669000, 0.2154207000, 0.3322891000, 0.6448266000, 1.4635108000", \ - "0.2156525000, 0.2259579000, 0.2520997000, 0.3098848000, 0.4387791000, 0.7204828000, 1.4791686000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0156217000, 0.0170860000, 0.0205675000, 0.0288992000, 0.0488834000, 0.0984892000, 0.2215380000", \ - "0.0202374000, 0.0217130000, 0.0252297000, 0.0334553000, 0.0536711000, 0.1033676000, 0.2263855000", \ - "0.0274274000, 0.0297536000, 0.0348125000, 0.0447569000, 0.0649272000, 0.1144667000, 0.2376112000", \ - "0.0346928000, 0.0385391000, 0.0467991000, 0.0624329000, 0.0901380000, 0.1407148000, 0.2629664000", \ - "0.0386264000, 0.0447062000, 0.0576315000, 0.0822423000, 0.1262741000, 0.1982725000, 0.3234072000", \ - "0.0281207000, 0.0374662000, 0.0578992000, 0.0973094000, 0.1658287000, 0.2791132000, 0.4566381000", \ - "-0.025259800, -0.010609400, 0.0214645000, 0.0833537000, 0.1928690000, 0.3694654000, 0.6484127000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0955063000, 0.1025673000, 0.1203252000, 0.1617189000, 0.2622577000, 0.5055536000, 1.1067455000", \ - "0.0985492000, 0.1054277000, 0.1231186000, 0.1647646000, 0.2654194000, 0.5096517000, 1.1111881000", \ - "0.1082756000, 0.1155317000, 0.1328890000, 0.1744831000, 0.2749046000, 0.5199491000, 1.1221827000", \ - "0.1356145000, 0.1424491000, 0.1590766000, 0.1996181000, 0.3000558000, 0.5452606000, 1.1482255000", \ - "0.2014743000, 0.2091937000, 0.2260920000, 0.2668554000, 0.3649670000, 0.6091955000, 1.2120993000", \ - "0.3135236000, 0.3245301000, 0.3509744000, 0.4081222000, 0.5206401000, 0.7590392000, 1.3583231000", \ - "0.4929637000, 0.5096065000, 0.5485095000, 0.6334137000, 0.8025596000, 1.1152995000, 1.7148811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0125840000, 0.0145729000, 0.0193333000, 0.0304904000, 0.0570256000, 0.1225286000, 0.2855954000", \ - "0.0134917000, 0.0152260000, 0.0195689000, 0.0304796000, 0.0570460000, 0.1228619000, 0.2855579000", \ - "0.0213654000, 0.0225624000, 0.0251886000, 0.0335943000, 0.0574788000, 0.1224199000, 0.2861478000", \ - "0.0362337000, 0.0378092000, 0.0414748000, 0.0499871000, 0.0685380000, 0.1246906000, 0.2854381000", \ - "0.0627079000, 0.0649569000, 0.0702177000, 0.0823922000, 0.1063706000, 0.1532229000, 0.2909062000", \ - "0.1099488000, 0.1131542000, 0.1209857000, 0.1388553000, 0.1754757000, 0.2410329000, 0.3575796000", \ - "0.1953855000, 0.2004130000, 0.2127621000, 0.2394867000, 0.2938400000, 0.3934418000, 0.5573174000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012431500, 0.0030908600, 0.0076848200, 0.0191068000, 0.0475054000, 0.1181130000"); - values("0.0898512000, 0.0989933000, 0.1211241000, 0.1751616000, 0.3088549000, 0.6408460000, 1.4628853000", \ - "0.0901719000, 0.0989548000, 0.1208967000, 0.1752624000, 0.3093849000, 0.6405423000, 1.4626642000", \ - "0.0897488000, 0.0987870000, 0.1209336000, 0.1754786000, 0.3093553000, 0.6398887000, 1.4631908000", \ - "0.0889860000, 0.0977496000, 0.1194656000, 0.1749624000, 0.3093976000, 0.6408331000, 1.4631101000", \ - "0.1102098000, 0.1175139000, 0.1353189000, 0.1826056000, 0.3097315000, 0.6405094000, 1.4660373000", \ - "0.1602252000, 0.1703338000, 0.1947324000, 0.2464635000, 0.3536301000, 0.6486627000, 1.4631081000", \ - "0.2420902000, 0.2581956000, 0.2943659000, 0.3676622000, 0.5073871000, 0.7696906000, 1.4857888000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a31oi_4") { - leakage_power () { - value : 0.0031158000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0020631000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0021385000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0021432000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0038798000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0021647000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0034546000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0031158000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0034296000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0004327000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0042707000; - when : "A1&A2&A3&!B1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a31oi"; - cell_leakage_power : 0.0028617010; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0084220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181798000, 0.0181836000, 0.0181924000, 0.0181861000, 0.0181715000, 0.0181380000, 0.0180608000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013762000, -0.013775900, -0.013808000, -0.013772900, -0.013692200, -0.013506000, -0.013076900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086580000; - } - pin ("A2") { - capacitance : 0.0084170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171112000, 0.0171103000, 0.0171081000, 0.0171673000, 0.0173037000, 0.0176181000, 0.0183429000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015574500, -0.015577300, -0.015583900, -0.015581200, -0.015575000, -0.015560700, -0.015527700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087250000; - } - pin ("A3") { - capacitance : 0.0086310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156974000, 0.0156960000, 0.0156929000, 0.0156965000, 0.0157047000, 0.0157237000, 0.0157675000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015685400, -0.015685300, -0.015685000, -0.015675200, -0.015652700, -0.015600800, -0.015481000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090820000; - } - pin ("B1") { - capacitance : 0.0085110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078526000, 0.0078318000, 0.0077837000, 0.0078425000, 0.0079778000, 0.0082899000, 0.0090091000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006887600, -0.006881600, -0.006867900, -0.006869500, -0.006873400, -0.006882400, -0.006903000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091560000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0194876000, 0.0180935000, 0.0143187000, 0.0038864000, -0.024797000, -0.103724500, -0.320892600", \ - "0.0190109000, 0.0176274000, 0.0138533000, 0.0035242000, -0.025123900, -0.104093300, -0.321252700", \ - "0.0182110000, 0.0168400000, 0.0131124000, 0.0028186000, -0.025668600, -0.104540100, -0.321609600", \ - "0.0171269000, 0.0159115000, 0.0122454000, 0.0019762000, -0.026365100, -0.104994800, -0.321931200", \ - "0.0163920000, 0.0150523000, 0.0113542000, 0.0013820000, -0.027046100, -0.105591600, -0.322395000", \ - "0.0173401000, 0.0159288000, 0.0119021000, 0.0014728000, -0.027554500, -0.106140100, -0.322668300", \ - "0.0206727000, 0.0192206000, 0.0151481000, 0.0041344000, -0.025563600, -0.105678400, -0.322906500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0270778000, 0.0286687000, 0.0329058000, 0.0439591000, 0.0728528000, 0.1514589000, 0.3662759000", \ - "0.0262118000, 0.0278272000, 0.0320763000, 0.0432682000, 0.0726925000, 0.1515362000, 0.3665441000", \ - "0.0252554000, 0.0268179000, 0.0310348000, 0.0423807000, 0.0723534000, 0.1519631000, 0.3664694000", \ - "0.0244880000, 0.0260207000, 0.0300831000, 0.0412235000, 0.0708177000, 0.1505232000, 0.3690260000", \ - "0.0240657000, 0.0254749000, 0.0294643000, 0.0401897000, 0.0696318000, 0.1493642000, 0.3677560000", \ - "0.0239189000, 0.0253396000, 0.0294067000, 0.0402450000, 0.0690057000, 0.1485248000, 0.3661569000", \ - "0.0238329000, 0.0249150000, 0.0287529000, 0.0391384000, 0.0690373000, 0.1483908000, 0.3653221000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0212107000, 0.0197952000, 0.0159754000, 0.0055090000, -0.023140400, -0.102083900, -0.319112800", \ - "0.0207417000, 0.0193502000, 0.0155541000, 0.0051063000, -0.023528400, -0.102457200, -0.319496300", \ - "0.0201080000, 0.0187590000, 0.0149297000, 0.0045765000, -0.024013900, -0.102924300, -0.320024200", \ - "0.0193368000, 0.0180200000, 0.0142740000, 0.0039402000, -0.024527300, -0.103309400, -0.320322200", \ - "0.0187073000, 0.0173324000, 0.0136914000, 0.0034633000, -0.024828700, -0.103491600, -0.320407000", \ - "0.0190722000, 0.0176662000, 0.0138412000, 0.0031634000, -0.025724500, -0.104168600, -0.320749900", \ - "0.0213255000, 0.0198793000, 0.0159670000, 0.0052450000, -0.024141500, -0.103984900, -0.320836100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0397243000, 0.0411642000, 0.0449674000, 0.0555542000, 0.0844176000, 0.1629296000, 0.3775397000", \ - "0.0390808000, 0.0405346000, 0.0444637000, 0.0551468000, 0.0842503000, 0.1626976000, 0.3774146000", \ - "0.0382176000, 0.0396539000, 0.0436351000, 0.0544817000, 0.0836277000, 0.1624740000, 0.3774048000", \ - "0.0372893000, 0.0387813000, 0.0426874000, 0.0534812000, 0.0828848000, 0.1619876000, 0.3770272000", \ - "0.0365777000, 0.0380153000, 0.0419130000, 0.0525856000, 0.0817478000, 0.1609475000, 0.3764486000", \ - "0.0360683000, 0.0374602000, 0.0413935000, 0.0522276000, 0.0812476000, 0.1599992000, 0.3754655000", \ - "0.0348007000, 0.0361926000, 0.0399696000, 0.0503132000, 0.0803602000, 0.1598504000, 0.3747782000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0209576000, 0.0195813000, 0.0157655000, 0.0053172000, -0.023360100, -0.102318200, -0.319452100", \ - "0.0205224000, 0.0191284000, 0.0153196000, 0.0048563000, -0.023768400, -0.102722200, -0.319833800", \ - "0.0198866000, 0.0185057000, 0.0147132000, 0.0043237000, -0.024272300, -0.103127100, -0.320251000", \ - "0.0190880000, 0.0177263000, 0.0139504000, 0.0036409000, -0.024798800, -0.103608100, -0.320518300", \ - "0.0184703000, 0.0171148000, 0.0133891000, 0.0030803000, -0.025248600, -0.103811100, -0.320705400", \ - "0.0189738000, 0.0176016000, 0.0137937000, 0.0032989000, -0.025896500, -0.104207900, -0.320928600", \ - "0.0208495000, 0.0194471000, 0.0154910000, 0.0047532000, -0.024447800, -0.104276400, -0.321054700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0522149000, 0.0536587000, 0.0575446000, 0.0681344000, 0.0971317000, 0.1760219000, 0.3906503000", \ - "0.0516245000, 0.0530652000, 0.0570204000, 0.0676785000, 0.0966800000, 0.1753827000, 0.3903673000", \ - "0.0510689000, 0.0525791000, 0.0565277000, 0.0672199000, 0.0963753000, 0.1753812000, 0.3901926000", \ - "0.0504439000, 0.0519224000, 0.0558507000, 0.0666217000, 0.0957940000, 0.1747008000, 0.3901853000", \ - "0.0499622000, 0.0513228000, 0.0552836000, 0.0660589000, 0.0950975000, 0.1744455000, 0.3895806000", \ - "0.0500152000, 0.0513344000, 0.0552043000, 0.0660886000, 0.0951400000, 0.1740204000, 0.3897502000", \ - "0.0495846000, 0.0509932000, 0.0546311000, 0.0650139000, 0.0949560000, 0.1742805000, 0.3894086000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("-0.000261000, -0.001488400, -0.005015300, -0.015178500, -0.043874000, -0.123147400, -0.340662500", \ - "-0.000889100, -0.002100300, -0.005499500, -0.015376900, -0.043801900, -0.122906100, -0.340333700", \ - "-0.001648700, -0.002861700, -0.006265500, -0.015977200, -0.043946900, -0.122787700, -0.340046300", \ - "-0.002319700, -0.003603400, -0.007131900, -0.016819600, -0.044576300, -0.122946200, -0.339988300", \ - "-0.001620400, -0.002980800, -0.006672700, -0.016686800, -0.045133900, -0.123391100, -0.340103300", \ - "-1.09000e-05, -0.001463200, -0.005404800, -0.016131400, -0.044612000, -0.123637900, -0.340473600", \ - "0.0060674000, 0.0044242000, 7.000000e-07, -0.011613100, -0.041885100, -0.120980900, -0.339881500"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0484172000, 0.0498668000, 0.0540460000, 0.0650474000, 0.0945426000, 0.1735922000, 0.3887407000", \ - "0.0476006000, 0.0491037000, 0.0532876000, 0.0643120000, 0.0940669000, 0.1733380000, 0.3887335000", \ - "0.0467527000, 0.0482860000, 0.0524002000, 0.0633871000, 0.0930446000, 0.1727969000, 0.3883548000", \ - "0.0462762000, 0.0477973000, 0.0517567000, 0.0624081000, 0.0919657000, 0.1716454000, 0.3876128000", \ - "0.0459857000, 0.0474115000, 0.0512976000, 0.0619712000, 0.0911030000, 0.1706533000, 0.3865565000", \ - "0.0477865000, 0.0491479000, 0.0529881000, 0.0634350000, 0.0923026000, 0.1710442000, 0.3846893000", \ - "0.0529524000, 0.0541388000, 0.0575351000, 0.0671777000, 0.0948849000, 0.1720701000, 0.3850177000"); - } - } - max_capacitance : 0.2114970000; - max_transition : 1.5022000000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0428614000, 0.0453677000, 0.0520402000, 0.0689655000, 0.1120614000, 0.2244097000, 0.5273142000", \ - "0.0462857000, 0.0488049000, 0.0554401000, 0.0724513000, 0.1156878000, 0.2279923000, 0.5310239000", \ - "0.0550202000, 0.0575787000, 0.0642148000, 0.0813060000, 0.1244927000, 0.2374660000, 0.5401638000", \ - "0.0765702000, 0.0796261000, 0.0871149000, 0.1038792000, 0.1463147000, 0.2592585000, 0.5617662000", \ - "0.1026150000, 0.1067575000, 0.1173482000, 0.1423167000, 0.1964854000, 0.3116404000, 0.6148137000", \ - "0.1234752000, 0.1296152000, 0.1450797000, 0.1825977000, 0.2650511000, 0.4207028000, 0.7341101000", \ - "0.1122973000, 0.1217507000, 0.1454960000, 0.2024997000, 0.3263249000, 0.5674539000, 1.0006677000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0855159000, 0.0904803000, 0.1032428000, 0.1362864000, 0.2230642000, 0.4563883000, 1.0949169000", \ - "0.0894742000, 0.0943921000, 0.1072753000, 0.1409205000, 0.2283306000, 0.4629762000, 1.1020765000", \ - "0.1012211000, 0.1062955000, 0.1189681000, 0.1528693000, 0.2414858000, 0.4813193000, 1.1172132000", \ - "0.1314468000, 0.1360625000, 0.1482288000, 0.1811195000, 0.2703025000, 0.5064856000, 1.1545398000", \ - "0.1879430000, 0.1934128000, 0.2081326000, 0.2440612000, 0.3319562000, 0.5703216000, 1.2164058000", \ - "0.2798517000, 0.2879274000, 0.3088962000, 0.3584142000, 0.4667400000, 0.7090428000, 1.3598879000", \ - "0.4242007000, 0.4369936000, 0.4724396000, 0.5516167000, 0.7096663000, 1.0178308000, 1.6790166000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0466987000, 0.0491564000, 0.0562076000, 0.0760112000, 0.1315848000, 0.2841718000, 0.7062089000", \ - "0.0461777000, 0.0487918000, 0.0559809000, 0.0758009000, 0.1313857000, 0.2842789000, 0.7059113000", \ - "0.0442412000, 0.0469110000, 0.0542944000, 0.0750405000, 0.1311271000, 0.2846596000, 0.7059839000", \ - "0.0528684000, 0.0557372000, 0.0620292000, 0.0793190000, 0.1312349000, 0.2843166000, 0.7064336000", \ - "0.0715082000, 0.0750835000, 0.0842017000, 0.1066594000, 0.1564798000, 0.2896347000, 0.7061794000", \ - "0.1115205000, 0.1167080000, 0.1297079000, 0.1607069000, 0.2248401000, 0.3576375000, 0.7199464000", \ - "0.1825348000, 0.1905322000, 0.2107970000, 0.2562765000, 0.3487255000, 0.5234793000, 0.8750246000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0490766000, 0.0548573000, 0.0707442000, 0.1140636000, 0.2320002000, 0.5537978000, 1.4340921000", \ - "0.0491195000, 0.0548249000, 0.0706484000, 0.1139464000, 0.2321668000, 0.5533272000, 1.4351325000", \ - "0.0492763000, 0.0549547000, 0.0708631000, 0.1141394000, 0.2322266000, 0.5584412000, 1.4348390000", \ - "0.0503577000, 0.0557578000, 0.0713218000, 0.1141977000, 0.2319366000, 0.5542410000, 1.4478481000", \ - "0.0645643000, 0.0701035000, 0.0836387000, 0.1216361000, 0.2334392000, 0.5566304000, 1.4454298000", \ - "0.0983954000, 0.1041648000, 0.1207188000, 0.1625305000, 0.2658860000, 0.5612177000, 1.4442363000", \ - "0.1746302000, 0.1825909000, 0.2032973000, 0.2541378000, 0.3699841000, 0.6470546000, 1.4511554000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0517796000, 0.0541960000, 0.0608226000, 0.0777641000, 0.1207995000, 0.2331670000, 0.5359643000", \ - "0.0554422000, 0.0579278000, 0.0645830000, 0.0815342000, 0.1244847000, 0.2370468000, 0.5404424000", \ - "0.0634483000, 0.0659532000, 0.0724891000, 0.0894661000, 0.1325698000, 0.2452149000, 0.5479410000", \ - "0.0797538000, 0.0826621000, 0.0896672000, 0.1075130000, 0.1508991000, 0.2636064000, 0.5666361000", \ - "0.1049671000, 0.1085261000, 0.1177426000, 0.1400773000, 0.1903750000, 0.3064505000, 0.6104872000", \ - "0.1286756000, 0.1339630000, 0.1473931000, 0.1804224000, 0.2509522000, 0.3943890000, 0.7095948000", \ - "0.1224165000, 0.1305273000, 0.1514808000, 0.2014506000, 0.3116202000, 0.5235690000, 0.9152718000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.1122825000, 0.1166791000, 0.1285381000, 0.1611958000, 0.2482007000, 0.4844300000, 1.1298193000", \ - "0.1167150000, 0.1212238000, 0.1334804000, 0.1662944000, 0.2536586000, 0.4903696000, 1.1372973000", \ - "0.1288732000, 0.1333507000, 0.1458384000, 0.1788112000, 0.2671341000, 0.5043265000, 1.1511178000", \ - "0.1583037000, 0.1630296000, 0.1749321000, 0.2081621000, 0.2966774000, 0.5346361000, 1.1811400000", \ - "0.2188386000, 0.2237968000, 0.2374677000, 0.2706139000, 0.3586648000, 0.5968961000, 1.2447251000", \ - "0.3246561000, 0.3311854000, 0.3484029000, 0.3918345000, 0.4935784000, 0.7359299000, 1.3840856000", \ - "0.4998089000, 0.5104134000, 0.5373524000, 0.6012880000, 0.7444969000, 1.0435386000, 1.7040580000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0456315000, 0.0483028000, 0.0555280000, 0.0757644000, 0.1311642000, 0.2842840000, 0.7064690000", \ - "0.0454631000, 0.0481377000, 0.0554083000, 0.0755528000, 0.1311239000, 0.2845779000, 0.7065606000", \ - "0.0453415000, 0.0478402000, 0.0549981000, 0.0753114000, 0.1310035000, 0.2844206000, 0.7063721000", \ - "0.0508721000, 0.0532341000, 0.0598840000, 0.0781032000, 0.1315710000, 0.2841821000, 0.7064753000", \ - "0.0663366000, 0.0691075000, 0.0766953000, 0.0963524000, 0.1462602000, 0.2880704000, 0.7060477000", \ - "0.1033213000, 0.1069444000, 0.1163195000, 0.1399966000, 0.1953346000, 0.3283414000, 0.7157523000", \ - "0.1709361000, 0.1766798000, 0.1912611000, 0.2245508000, 0.2976696000, 0.4529550000, 0.8120674000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0716629000, 0.0775768000, 0.0935168000, 0.1373608000, 0.2568517000, 0.5841019000, 1.4730356000", \ - "0.0716548000, 0.0774660000, 0.0936565000, 0.1373913000, 0.2568662000, 0.5820040000, 1.4747784000", \ - "0.0717187000, 0.0774628000, 0.0936711000, 0.1376328000, 0.2569840000, 0.5819654000, 1.4784582000", \ - "0.0717781000, 0.0778024000, 0.0937199000, 0.1374615000, 0.2574784000, 0.5835188000, 1.4728903000", \ - "0.0816557000, 0.0867387000, 0.1012077000, 0.1424199000, 0.2573456000, 0.5825211000, 1.4771074000", \ - "0.1137198000, 0.1198159000, 0.1359118000, 0.1780330000, 0.2838564000, 0.5896806000, 1.4734494000", \ - "0.1902393000, 0.1977728000, 0.2174996000, 0.2659482000, 0.3829034000, 0.6674703000, 1.4869455000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0567067000, 0.0592886000, 0.0657220000, 0.0826303000, 0.1258129000, 0.2384681000, 0.5411140000", \ - "0.0605734000, 0.0630692000, 0.0695683000, 0.0865374000, 0.1295184000, 0.2420572000, 0.5448511000", \ - "0.0678498000, 0.0704348000, 0.0769393000, 0.0939317000, 0.1370372000, 0.2496387000, 0.5523851000", \ - "0.0810865000, 0.0838954000, 0.0905521000, 0.1080369000, 0.1513193000, 0.2642326000, 0.5667824000", \ - "0.1013108000, 0.1042974000, 0.1120683000, 0.1320620000, 0.1795128000, 0.2948212000, 0.5980488000", \ - "0.1213111000, 0.1257975000, 0.1373992000, 0.1638211000, 0.2243283000, 0.3571703000, 0.6691380000", \ - "0.1118548000, 0.1194615000, 0.1363385000, 0.1786223000, 0.2701649000, 0.4499247000, 0.8148039000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.1308802000, 0.1357205000, 0.1483934000, 0.1806883000, 0.2682701000, 0.5034444000, 1.1425139000", \ - "0.1361021000, 0.1409311000, 0.1527309000, 0.1860871000, 0.2735872000, 0.5089112000, 1.1480057000", \ - "0.1489107000, 0.1530086000, 0.1660357000, 0.1987191000, 0.2867041000, 0.5219475000, 1.1618740000", \ - "0.1773192000, 0.1823439000, 0.1946139000, 0.2279597000, 0.3157860000, 0.5516573000, 1.1908045000", \ - "0.2371897000, 0.2420437000, 0.2546589000, 0.2874266000, 0.3753374000, 0.6106480000, 1.2504553000", \ - "0.3420757000, 0.3484394000, 0.3647115000, 0.4050534000, 0.5035304000, 0.7421638000, 1.3826299000", \ - "0.5215542000, 0.5302366000, 0.5531051000, 0.6087947000, 0.7413452000, 1.0287250000, 1.6838064000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0455310000, 0.0481976000, 0.0555265000, 0.0755897000, 0.1312013000, 0.2843253000, 0.7059475000", \ - "0.0454641000, 0.0481014000, 0.0554299000, 0.0756301000, 0.1310647000, 0.2841626000, 0.7064417000", \ - "0.0451931000, 0.0477939000, 0.0551026000, 0.0753553000, 0.1309330000, 0.2845482000, 0.7065714000", \ - "0.0485027000, 0.0510334000, 0.0581682000, 0.0770844000, 0.1314934000, 0.2844331000, 0.7064905000", \ - "0.0591927000, 0.0618689000, 0.0688671000, 0.0885097000, 0.1406707000, 0.2876008000, 0.7063675000", \ - "0.0899542000, 0.0930692000, 0.1010250000, 0.1217074000, 0.1739942000, 0.3160290000, 0.7148211000", \ - "0.1546505000, 0.1584734000, 0.1698866000, 0.1968042000, 0.2589624000, 0.4032025000, 0.7836443000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0929705000, 0.0988093000, 0.1147481000, 0.1582222000, 0.2763708000, 0.5991087000, 1.4821409000", \ - "0.0927086000, 0.0984870000, 0.1147789000, 0.1583226000, 0.2769821000, 0.5990999000, 1.4844165000", \ - "0.0930835000, 0.0987873000, 0.1147293000, 0.1581011000, 0.2768845000, 0.5987697000, 1.4852143000", \ - "0.0927773000, 0.0989413000, 0.1147445000, 0.1582219000, 0.2767141000, 0.5990784000, 1.4822353000", \ - "0.0998290000, 0.1053563000, 0.1199932000, 0.1616860000, 0.2766596000, 0.5995480000, 1.4827681000", \ - "0.1316539000, 0.1369615000, 0.1522703000, 0.1942747000, 0.3004768000, 0.6053427000, 1.4828276000", \ - "0.2046354000, 0.2121841000, 0.2297719000, 0.2768679000, 0.3939490000, 0.6782181000, 1.4992617000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0142939000, 0.0151931000, 0.0175935000, 0.0237542000, 0.0398552000, 0.0833914000, 0.2024686000", \ - "0.0187507000, 0.0197463000, 0.0221807000, 0.0283339000, 0.0445795000, 0.0882686000, 0.2073191000", \ - "0.0247543000, 0.0264110000, 0.0302912000, 0.0388360000, 0.0555109000, 0.0992862000, 0.2183649000", \ - "0.0301712000, 0.0328283000, 0.0391570000, 0.0524252000, 0.0780939000, 0.1245674000, 0.2436319000", \ - "0.0307823000, 0.0341956000, 0.0440183000, 0.0655538000, 0.1063535000, 0.1773284000, 0.3031028000", \ - "0.0121763000, 0.0186013000, 0.0341559000, 0.0679942000, 0.1320579000, 0.2442266000, 0.4292586000", \ - "-0.055739900, -0.045830700, -0.022251200, 0.0315186000, 0.1331743000, 0.3093892000, 0.6002498000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0995718000, 0.1045867000, 0.1166958000, 0.1508983000, 0.2400063000, 0.4762971000, 1.1159680000", \ - "0.1024317000, 0.1075168000, 0.1197922000, 0.1539705000, 0.2434693000, 0.4800481000, 1.1203827000", \ - "0.1123957000, 0.1168444000, 0.1300619000, 0.1641186000, 0.2530494000, 0.4905497000, 1.1316873000", \ - "0.1400733000, 0.1447419000, 0.1571722000, 0.1898673000, 0.2784502000, 0.5163129000, 1.1583730000", \ - "0.2081090000, 0.2129101000, 0.2252510000, 0.2583346000, 0.3452431000, 0.5818126000, 1.2236271000", \ - "0.3257878000, 0.3331870000, 0.3525563000, 0.3988406000, 0.5030797000, 0.7370614000, 1.3724423000", \ - "0.5188493000, 0.5294971000, 0.5574989000, 0.6263000000, 0.7828910000, 1.0984005000, 1.7370816000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0106563000, 0.0118721000, 0.0152523000, 0.0239343000, 0.0458615000, 0.1043635000, 0.2645117000", \ - "0.0119351000, 0.0129377000, 0.0158271000, 0.0239870000, 0.0458690000, 0.1045072000, 0.2643818000", \ - "0.0201429000, 0.0209008000, 0.0230295000, 0.0286525000, 0.0471691000, 0.1044947000, 0.2645042000", \ - "0.0347443000, 0.0356614000, 0.0382882000, 0.0450535000, 0.0609482000, 0.1084926000, 0.2642690000", \ - "0.0608668000, 0.0621674000, 0.0658025000, 0.0751698000, 0.0968844000, 0.1416418000, 0.2718829000", \ - "0.1077993000, 0.1096598000, 0.1148489000, 0.1284369000, 0.1608810000, 0.2239205000, 0.3450671000", \ - "0.1930527000, 0.1958534000, 0.2044107000, 0.2241848000, 0.2714266000, 0.3686815000, 0.5395123000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0928530000, 0.0985921000, 0.1148616000, 0.1579112000, 0.2762880000, 0.5991763000, 1.4849681000", \ - "0.0927007000, 0.0984726000, 0.1147293000, 0.1579820000, 0.2763177000, 0.6004691000, 1.4837637000", \ - "0.0926605000, 0.0985251000, 0.1147286000, 0.1580926000, 0.2768804000, 0.6001127000, 1.4852999000", \ - "0.0914203000, 0.0972081000, 0.1130496000, 0.1575336000, 0.2762966000, 0.5992477000, 1.4822158000", \ - "0.1115164000, 0.1161993000, 0.1290725000, 0.1668943000, 0.2768796000, 0.5993860000, 1.4822421000", \ - "0.1587565000, 0.1660106000, 0.1843130000, 0.2282104000, 0.3233447000, 0.6080458000, 1.4823552000", \ - "0.2414514000, 0.2518465000, 0.2782319000, 0.3408006000, 0.4722183000, 0.7342265000, 1.5022001000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32o_1") { - leakage_power () { - value : 0.0021040000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0016631000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019022000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0021258000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0016850000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0019240000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0021253000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0016844000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019235000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0026107000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0021698000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0024089000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0021296000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0016888000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019279000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0024979000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0020570000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0022961000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0024754000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0020346000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0033079000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0022736000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015496000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0016140000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0018622000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0015997000; - when : "A1&A2&A3&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a32o"; - cell_leakage_power : 0.0022965200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045458000, 0.0045474000, 0.0045512000, 0.0045511000, 0.0045508000, 0.0045499000, 0.0045481000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003349900, -0.003354200, -0.003364000, -0.003355400, -0.003335600, -0.003289900, -0.003184600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024280000; - } - pin ("A2") { - capacitance : 0.0023360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043483000, 0.0043481000, 0.0043477000, 0.0043630000, 0.0043983000, 0.0044796000, 0.0046671000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004005700, -0.004004500, -0.004001800, -0.004001000, -0.003999400, -0.003995500, -0.003986600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024420000; - } - pin ("A3") { - capacitance : 0.0023520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042872000, 0.0042842000, 0.0042772000, 0.0042786000, 0.0042817000, 0.0042888000, 0.0043053000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004269000, -0.004267800, -0.004265200, -0.004265800, -0.004267100, -0.004270000, -0.004276900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024910000; - } - pin ("B1") { - capacitance : 0.0023780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045478000, 0.0045462000, 0.0045426000, 0.0045438000, 0.0045464000, 0.0045524000, 0.0045662000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003705900, -0.003709500, -0.003717600, -0.003711400, -0.003696900, -0.003663600, -0.003586700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025190000; - } - pin ("B2") { - capacitance : 0.0022690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039625000, 0.0039594000, 0.0039523000, 0.0039523000, 0.0039523000, 0.0039523000, 0.0039522000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003960500, -0.003961200, -0.003962800, -0.003962300, -0.003961100, -0.003958400, -0.003952200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024280000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0142174000, 0.0133453000, 0.0109657000, 0.0036264000, -0.017898400, -0.075605800, -0.225774200", \ - "0.0141067000, 0.0132312000, 0.0108205000, 0.0034962000, -0.018020000, -0.075735400, -0.225900500", \ - "0.0138264000, 0.0129600000, 0.0105580000, 0.0032249000, -0.018278100, -0.075997800, -0.226163700", \ - "0.0135651000, 0.0126998000, 0.0103019000, 0.0029333000, -0.018608600, -0.076297900, -0.226456700", \ - "0.0132808000, 0.0124371000, 0.0100026000, 0.0026254000, -0.018917200, -0.076574900, -0.226717100", \ - "0.0134043000, 0.0121261000, 0.0094159000, 0.0023393000, -0.019020700, -0.076662800, -0.226784200", \ - "0.0161660000, 0.0148895000, 0.0115545000, 0.0030091000, -0.019186700, -0.076670300, -0.226707000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0141652000, 0.0155551000, 0.0190520000, 0.0277396000, 0.0499159000, 0.1073178000, 0.2570331000", \ - "0.0140694000, 0.0154588000, 0.0189562000, 0.0276670000, 0.0498771000, 0.1077605000, 0.2568790000", \ - "0.0139150000, 0.0153228000, 0.0188146000, 0.0275351000, 0.0497577000, 0.1076194000, 0.2570147000", \ - "0.0137294000, 0.0151288000, 0.0186328000, 0.0273439000, 0.0495181000, 0.1069735000, 0.2556775000", \ - "0.0135772000, 0.0149653000, 0.0184139000, 0.0271403000, 0.0493892000, 0.1072711000, 0.2565892000", \ - "0.0142857000, 0.0155750000, 0.0189020000, 0.0273091000, 0.0496223000, 0.1071822000, 0.2568895000", \ - "0.0153141000, 0.0165200000, 0.0197999000, 0.0283628000, 0.0505804000, 0.1080739000, 0.2564586000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0170664000, 0.0161971000, 0.0138257000, 0.0065565000, -0.014825100, -0.072450300, -0.222512300", \ - "0.0169618000, 0.0160991000, 0.0137094000, 0.0064176000, -0.014950300, -0.072571400, -0.222702100", \ - "0.0167449000, 0.0158664000, 0.0134911000, 0.0062247000, -0.015171100, -0.072790300, -0.222905800", \ - "0.0165128000, 0.0156643000, 0.0132885000, 0.0059872000, -0.015438700, -0.073057900, -0.223150800", \ - "0.0162104000, 0.0153560000, 0.0129491000, 0.0056522000, -0.015729800, -0.073348100, -0.223407900", \ - "0.0156393000, 0.0147994000, 0.0125414000, 0.0053789000, -0.015907200, -0.073512000, -0.223549800", \ - "0.0190276000, 0.0176959000, 0.0143866000, 0.0059405000, -0.016300800, -0.073736200, -0.223710200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0148338000, 0.0162278000, 0.0197219000, 0.0283864000, 0.0504426000, 0.1081459000, 0.2571557000", \ - "0.0147360000, 0.0161330000, 0.0196265000, 0.0283141000, 0.0503183000, 0.1076761000, 0.2564367000", \ - "0.0146040000, 0.0159974000, 0.0194865000, 0.0281805000, 0.0502161000, 0.1075799000, 0.2563399000", \ - "0.0144084000, 0.0157957000, 0.0192896000, 0.0279798000, 0.0501100000, 0.1074296000, 0.2569544000", \ - "0.0142026000, 0.0156059000, 0.0190676000, 0.0278031000, 0.0499476000, 0.1074004000, 0.2569230000", \ - "0.0146837000, 0.0159723000, 0.0193150000, 0.0277204000, 0.0499883000, 0.1076375000, 0.2571977000", \ - "0.0154911000, 0.0167561000, 0.0200213000, 0.0286289000, 0.0508041000, 0.1082716000, 0.2569781000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0195575000, 0.0186515000, 0.0162659000, 0.0088427000, -0.012823300, -0.070762800, -0.221009200", \ - "0.0195029000, 0.0186119000, 0.0161754000, 0.0087672000, -0.012979500, -0.070885800, -0.221088100", \ - "0.0193068000, 0.0184377000, 0.0160495000, 0.0085391000, -0.013161800, -0.071056500, -0.221266700", \ - "0.0190590000, 0.0181540000, 0.0158321000, 0.0083440000, -0.013345800, -0.071205900, -0.221448000", \ - "0.0188706000, 0.0179790000, 0.0155911000, 0.0080977000, -0.013532200, -0.071378000, -0.221575600", \ - "0.0184353000, 0.0175901000, 0.0153454000, 0.0080095000, -0.013530000, -0.071329300, -0.221510100", \ - "0.0219739000, 0.0206613000, 0.0173065000, 0.0086788000, -0.013679700, -0.071233400, -0.221366000"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0150403000, 0.0164314000, 0.0199283000, 0.0285764000, 0.0505210000, 0.1081612000, 0.2570430000", \ - "0.0149421000, 0.0163386000, 0.0198352000, 0.0284989000, 0.0503739000, 0.1075631000, 0.2560033000", \ - "0.0147881000, 0.0161848000, 0.0196810000, 0.0283275000, 0.0504395000, 0.1074536000, 0.2561003000", \ - "0.0145660000, 0.0159533000, 0.0194353000, 0.0281065000, 0.0501076000, 0.1074210000, 0.2555553000", \ - "0.0143948000, 0.0157894000, 0.0192597000, 0.0279673000, 0.0500719000, 0.1079028000, 0.2571094000", \ - "0.0147337000, 0.0160239000, 0.0193841000, 0.0278072000, 0.0501332000, 0.1070347000, 0.2560688000", \ - "0.0153582000, 0.0165991000, 0.0199939000, 0.0285808000, 0.0507279000, 0.1081851000, 0.2553745000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0139023000, 0.0129893000, 0.0105488000, 0.0031742000, -0.018365700, -0.076120500, -0.226226400", \ - "0.0137227000, 0.0128111000, 0.0103797000, 0.0030037000, -0.018529400, -0.076287100, -0.226390500", \ - "0.0134310000, 0.0125385000, 0.0101973000, 0.0027166000, -0.018871900, -0.076544500, -0.226629600", \ - "0.0131875000, 0.0122729000, 0.0098552000, 0.0024347000, -0.019108600, -0.076803000, -0.226884500", \ - "0.0131173000, 0.0122340000, 0.0098885000, 0.0024681000, -0.019142500, -0.076832400, -0.226922000", \ - "0.0138941000, 0.0125771000, 0.0099324000, 0.0027843000, -0.018733400, -0.076455300, -0.226538200", \ - "0.0175130000, 0.0161651000, 0.0129029000, 0.0042510000, -0.018108300, -0.075649700, -0.225757900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0112246000, 0.0126391000, 0.0162192000, 0.0250720000, 0.0473913000, 0.1055268000, 0.2537255000", \ - "0.0111606000, 0.0125764000, 0.0161515000, 0.0250016000, 0.0473068000, 0.1042231000, 0.2534509000", \ - "0.0110128000, 0.0124264000, 0.0159745000, 0.0247917000, 0.0471582000, 0.1047641000, 0.2546363000", \ - "0.0107247000, 0.0121075000, 0.0156082000, 0.0243957000, 0.0467844000, 0.1050094000, 0.2532617000", \ - "0.0105145000, 0.0118131000, 0.0153177000, 0.0239934000, 0.0463554000, 0.1041851000, 0.2530996000", \ - "0.0109997000, 0.0123020000, 0.0157006000, 0.0242684000, 0.0465660000, 0.1042626000, 0.2542383000", \ - "0.0123246000, 0.0135270000, 0.0167859000, 0.0254724000, 0.0477508000, 0.1055615000, 0.2538803000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0166598000, 0.0157900000, 0.0133956000, 0.0060010000, -0.015538900, -0.073187100, -0.223259000", \ - "0.0165532000, 0.0156263000, 0.0132456000, 0.0058793000, -0.015574900, -0.073271500, -0.223375100", \ - "0.0163729000, 0.0154888000, 0.0131107000, 0.0057223000, -0.015803000, -0.073435100, -0.223485800", \ - "0.0162836000, 0.0154188000, 0.0130164000, 0.0056172000, -0.015885100, -0.073551000, -0.223605900", \ - "0.0163611000, 0.0154852000, 0.0130456000, 0.0055734000, -0.015965200, -0.073635100, -0.223699800", \ - "0.0168285000, 0.0155013000, 0.0128908000, 0.0057450000, -0.015731000, -0.073378700, -0.223422300", \ - "0.0217863000, 0.0204159000, 0.0170099000, 0.0083342000, -0.014103500, -0.071658000, -0.221697100"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0114120000, 0.0128361000, 0.0163967000, 0.0252545000, 0.0475574000, 0.1053260000, 0.2553178000", \ - "0.0113713000, 0.0127961000, 0.0163667000, 0.0252141000, 0.0477392000, 0.1050939000, 0.2555066000", \ - "0.0112179000, 0.0126332000, 0.0161950000, 0.0250383000, 0.0473669000, 0.1055650000, 0.2537634000", \ - "0.0109165000, 0.0123179000, 0.0158136000, 0.0246290000, 0.0472172000, 0.1047112000, 0.2531003000", \ - "0.0107418000, 0.0120600000, 0.0155630000, 0.0242612000, 0.0466624000, 0.1044074000, 0.2528732000", \ - "0.0109730000, 0.0122906000, 0.0157015000, 0.0243022000, 0.0466500000, 0.1044478000, 0.2534201000", \ - "0.0120775000, 0.0132989000, 0.0166297000, 0.0253283000, 0.0476549000, 0.1052511000, 0.2542268000"); - } - } - max_capacitance : 0.1510720000; - max_transition : 1.5081820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1802803000, 0.1873099000, 0.2018241000, 0.2299172000, 0.2855682000, 0.4064765000, 0.7043113000", \ - "0.1853347000, 0.1923552000, 0.2068745000, 0.2349359000, 0.2906541000, 0.4115666000, 0.7092528000", \ - "0.1976540000, 0.2046688000, 0.2191711000, 0.2472574000, 0.3029245000, 0.4238376000, 0.7216704000", \ - "0.2268760000, 0.2338437000, 0.2483904000, 0.2766261000, 0.3322440000, 0.4532044000, 0.7510614000", \ - "0.2920465000, 0.2990410000, 0.3135316000, 0.3418254000, 0.3974513000, 0.5184770000, 0.8163716000", \ - "0.4172493000, 0.4250562000, 0.4411426000, 0.4719662000, 0.5298478000, 0.6525812000, 0.9500933000", \ - "0.6288154000, 0.6386417000, 0.6581631000, 0.6943670000, 0.7603488000, 0.8897167000, 1.1901174000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1085144000, 0.1173188000, 0.1362229000, 0.1773260000, 0.2748045000, 0.5230075000, 1.1659498000", \ - "0.1123008000, 0.1211005000, 0.1400116000, 0.1811486000, 0.2786764000, 0.5273260000, 1.1700559000", \ - "0.1214338000, 0.1302482000, 0.1491898000, 0.1903715000, 0.2879408000, 0.5366805000, 1.1795811000", \ - "0.1437572000, 0.1524174000, 0.1713920000, 0.2125554000, 0.3099070000, 0.5580037000, 1.1990846000", \ - "0.1848106000, 0.1937548000, 0.2131237000, 0.2549695000, 0.3527101000, 0.6012897000, 1.2444099000", \ - "0.2341305000, 0.2442404000, 0.2650375000, 0.3077782000, 0.4062638000, 0.6550765000, 1.2966214000", \ - "0.2694392000, 0.2824598000, 0.3085299000, 0.3552893000, 0.4543920000, 0.7029897000, 1.3442079000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0268033000, 0.0315240000, 0.0424265000, 0.0663820000, 0.1218370000, 0.2642801000, 0.6544756000", \ - "0.0267791000, 0.0315050000, 0.0426519000, 0.0662938000, 0.1219312000, 0.2639612000, 0.6534281000", \ - "0.0267829000, 0.0315121000, 0.0425727000, 0.0663531000, 0.1218137000, 0.2642455000, 0.6543869000", \ - "0.0271793000, 0.0319893000, 0.0422967000, 0.0658080000, 0.1218256000, 0.2643429000, 0.6546208000", \ - "0.0271781000, 0.0320713000, 0.0423736000, 0.0661739000, 0.1217915000, 0.2643897000, 0.6540660000", \ - "0.0319008000, 0.0368956000, 0.0479964000, 0.0715787000, 0.1260397000, 0.2663112000, 0.6532423000", \ - "0.0433827000, 0.0491739000, 0.0620136000, 0.0866376000, 0.1416588000, 0.2766280000, 0.6530779000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0327031000, 0.0403630000, 0.0591427000, 0.1078041000, 0.2387968000, 0.5907113000, 1.5005606000", \ - "0.0326958000, 0.0403644000, 0.0590882000, 0.1077865000, 0.2390197000, 0.5903890000, 1.4990930000", \ - "0.0326591000, 0.0402184000, 0.0591507000, 0.1075382000, 0.2391770000, 0.5900895000, 1.4989926000", \ - "0.0323432000, 0.0400472000, 0.0589297000, 0.1074840000, 0.2390445000, 0.5904177000, 1.4968058000", \ - "0.0344276000, 0.0419152000, 0.0606073000, 0.1088703000, 0.2393424000, 0.5903658000, 1.4996063000", \ - "0.0416337000, 0.0484353000, 0.0656219000, 0.1115524000, 0.2411183000, 0.5884007000, 1.5006574000", \ - "0.0551698000, 0.0629831000, 0.0799281000, 0.1210373000, 0.2436998000, 0.5927730000, 1.4933725000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.2052274000, 0.2125339000, 0.2275102000, 0.2563778000, 0.3126440000, 0.4344010000, 0.7323982000", \ - "0.2104265000, 0.2177401000, 0.2327207000, 0.2617351000, 0.3178356000, 0.4396203000, 0.7377045000", \ - "0.2231248000, 0.2303564000, 0.2453742000, 0.2744028000, 0.3304839000, 0.4522764000, 0.7503885000", \ - "0.2526978000, 0.2600341000, 0.2749686000, 0.3039328000, 0.3598792000, 0.4819211000, 0.7802606000", \ - "0.3179630000, 0.3252526000, 0.3401888000, 0.3691124000, 0.4255185000, 0.5473270000, 0.8457943000", \ - "0.4505719000, 0.4584452000, 0.4745556000, 0.5052350000, 0.5629482000, 0.6857454000, 0.9839159000", \ - "0.6786608000, 0.6884761000, 0.7080859000, 0.7425791000, 0.8079851000, 0.9369084000, 1.2372949000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1168619000, 0.1256797000, 0.1445618000, 0.1855356000, 0.2824023000, 0.5302996000, 1.1726590000", \ - "0.1208944000, 0.1296217000, 0.1486120000, 0.1896392000, 0.2862463000, 0.5339314000, 1.1735440000", \ - "0.1296517000, 0.1383712000, 0.1573526000, 0.1983914000, 0.2951455000, 0.5428091000, 1.1825335000", \ - "0.1496893000, 0.1584594000, 0.1773213000, 0.2184009000, 0.3155631000, 0.5630556000, 1.2055770000", \ - "0.1883851000, 0.1975708000, 0.2170353000, 0.2587155000, 0.3562785000, 0.6034744000, 1.2459127000", \ - "0.2404690000, 0.2508522000, 0.2719267000, 0.3151494000, 0.4135649000, 0.6614603000, 1.3027064000", \ - "0.2821840000, 0.2953604000, 0.3209008000, 0.3685220000, 0.4686895000, 0.7169892000, 1.3573934000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0289485000, 0.0335815000, 0.0444995000, 0.0673629000, 0.1231221000, 0.2655819000, 0.6548169000", \ - "0.0289453000, 0.0335565000, 0.0445797000, 0.0672223000, 0.1230006000, 0.2654743000, 0.6555621000", \ - "0.0292300000, 0.0336176000, 0.0446054000, 0.0673677000, 0.1229954000, 0.2654442000, 0.6521478000", \ - "0.0289262000, 0.0340924000, 0.0440791000, 0.0678906000, 0.1236441000, 0.2655522000, 0.6561731000", \ - "0.0290134000, 0.0336723000, 0.0444903000, 0.0683713000, 0.1234093000, 0.2657834000, 0.6545222000", \ - "0.0331407000, 0.0382408000, 0.0483884000, 0.0717806000, 0.1264921000, 0.2661009000, 0.6532064000", \ - "0.0443050000, 0.0494974000, 0.0610585000, 0.0860027000, 0.1406162000, 0.2765378000, 0.6547746000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0326514000, 0.0403111000, 0.0591659000, 0.1076504000, 0.2390277000, 0.5904080000, 1.4971190000", \ - "0.0325816000, 0.0403137000, 0.0591993000, 0.1076440000, 0.2393891000, 0.5893257000, 1.4975757000", \ - "0.0325630000, 0.0403039000, 0.0591827000, 0.1076938000, 0.2394316000, 0.5888462000, 1.4972767000", \ - "0.0325698000, 0.0402164000, 0.0589977000, 0.1077955000, 0.2387943000, 0.5906399000, 1.5007487000", \ - "0.0347717000, 0.0422229000, 0.0608233000, 0.1084991000, 0.2388676000, 0.5903437000, 1.5018293000", \ - "0.0405064000, 0.0479599000, 0.0659917000, 0.1119317000, 0.2405498000, 0.5891705000, 1.5015147000", \ - "0.0538521000, 0.0615387000, 0.0787809000, 0.1211114000, 0.2443062000, 0.5918496000, 1.4958950000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.2162608000, 0.2235593000, 0.2384638000, 0.2667276000, 0.3223799000, 0.4434747000, 0.7416893000", \ - "0.2214964000, 0.2287103000, 0.2436075000, 0.2721401000, 0.3276260000, 0.4490579000, 0.7472523000", \ - "0.2346127000, 0.2419592000, 0.2568589000, 0.2854445000, 0.3407788000, 0.4619183000, 0.7605030000", \ - "0.2648825000, 0.2721811000, 0.2869004000, 0.3155354000, 0.3711287000, 0.4923063000, 0.7904992000", \ - "0.3293562000, 0.3366832000, 0.3515150000, 0.3801827000, 0.4361128000, 0.5572742000, 0.8554485000", \ - "0.4640929000, 0.4719281000, 0.4878241000, 0.5181737000, 0.5752514000, 0.6972896000, 0.9955098000", \ - "0.6985440000, 0.7083213000, 0.7276381000, 0.7624803000, 0.8263696000, 0.9539802000, 1.2538570000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1219477000, 0.1307653000, 0.1496687000, 0.1905878000, 0.2870151000, 0.5342132000, 1.1762712000", \ - "0.1260032000, 0.1347191000, 0.1537140000, 0.1946582000, 0.2907759000, 0.5376194000, 1.1776193000", \ - "0.1339137000, 0.1426332000, 0.1616209000, 0.2025594000, 0.2987982000, 0.5458248000, 1.1851070000", \ - "0.1504103000, 0.1591458000, 0.1780109000, 0.2189982000, 0.3156601000, 0.5620588000, 1.2035511000", \ - "0.1822275000, 0.1914348000, 0.2109343000, 0.2525033000, 0.3497771000, 0.5970632000, 1.2374332000", \ - "0.2281375000, 0.2382248000, 0.2593820000, 0.3028205000, 0.4011577000, 0.6489351000, 1.2895497000", \ - "0.2658364000, 0.2783470000, 0.3037357000, 0.3515843000, 0.4521955000, 0.7005431000, 1.3403155000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0300217000, 0.0345888000, 0.0454722000, 0.0684150000, 0.1237539000, 0.2654832000, 0.6540430000", \ - "0.0300853000, 0.0347963000, 0.0454996000, 0.0691861000, 0.1239685000, 0.2661055000, 0.6570198000", \ - "0.0300117000, 0.0346144000, 0.0450952000, 0.0690606000, 0.1237431000, 0.2657954000, 0.6511209000", \ - "0.0299897000, 0.0345532000, 0.0458005000, 0.0682493000, 0.1237821000, 0.2657070000, 0.6540950000", \ - "0.0301052000, 0.0349915000, 0.0455625000, 0.0680782000, 0.1236101000, 0.2654763000, 0.6552906000", \ - "0.0337009000, 0.0383363000, 0.0486462000, 0.0715355000, 0.1260562000, 0.2665189000, 0.6540308000", \ - "0.0442579000, 0.0493842000, 0.0602637000, 0.0838658000, 0.1387892000, 0.2750975000, 0.6543338000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0326730000, 0.0403195000, 0.0591967000, 0.1077386000, 0.2393439000, 0.5901015000, 1.5001327000", \ - "0.0325865000, 0.0402430000, 0.0592075000, 0.1075469000, 0.2392460000, 0.5879258000, 1.5009036000", \ - "0.0325782000, 0.0402670000, 0.0592013000, 0.1075190000, 0.2390992000, 0.5894208000, 1.4968660000", \ - "0.0325726000, 0.0403204000, 0.0591454000, 0.1079179000, 0.2392554000, 0.5897030000, 1.5019058000", \ - "0.0345905000, 0.0421498000, 0.0607061000, 0.1087179000, 0.2395107000, 0.5905097000, 1.5002326000", \ - "0.0396939000, 0.0475501000, 0.0655734000, 0.1120948000, 0.2407375000, 0.5892524000, 1.4969223000", \ - "0.0520526000, 0.0597691000, 0.0787903000, 0.1213359000, 0.2447521000, 0.5918226000, 1.4953078000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1677024000, 0.1749038000, 0.1895717000, 0.2180279000, 0.2737758000, 0.3951066000, 0.6934838000", \ - "0.1714368000, 0.1785510000, 0.1933277000, 0.2216023000, 0.2774802000, 0.3989372000, 0.6968531000", \ - "0.1812817000, 0.1884885000, 0.2032243000, 0.2317295000, 0.2876398000, 0.4090472000, 0.7072146000", \ - "0.2084461000, 0.2155890000, 0.2303008000, 0.2587228000, 0.3147883000, 0.4360317000, 0.7343597000", \ - "0.2762365000, 0.2833334000, 0.2971065000, 0.3255768000, 0.3815721000, 0.5029828000, 0.8012282000", \ - "0.4151955000, 0.4236022000, 0.4397829000, 0.4698421000, 0.5274520000, 0.6501777000, 0.9480124000", \ - "0.6371767000, 0.6479778000, 0.6699297000, 0.7065031000, 0.7690453000, 0.8947753000, 1.1956235000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0772193000, 0.0857534000, 0.1042425000, 0.1446030000, 0.2412004000, 0.4904465000, 1.1287213000", \ - "0.0815284000, 0.0900642000, 0.1085233000, 0.1488909000, 0.2456254000, 0.4943406000, 1.1331778000", \ - "0.0914831000, 0.0999229000, 0.1182956000, 0.1585527000, 0.2554143000, 0.5034886000, 1.1449938000", \ - "0.1128845000, 0.1214278000, 0.1398528000, 0.1800761000, 0.2770190000, 0.5266103000, 1.1655221000", \ - "0.1438675000, 0.1534646000, 0.1731437000, 0.2145351000, 0.3120716000, 0.5613576000, 1.2013534000", \ - "0.1758346000, 0.1880281000, 0.2112186000, 0.2552647000, 0.3534130000, 0.6023008000, 1.2486931000", \ - "0.1848187000, 0.2010064000, 0.2314852000, 0.2841947000, 0.3851213000, 0.6333237000, 1.2747070000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0294068000, 0.0338483000, 0.0440119000, 0.0673957000, 0.1231922000, 0.2651825000, 0.6536400000", \ - "0.0292789000, 0.0336498000, 0.0445025000, 0.0676190000, 0.1232130000, 0.2652780000, 0.6539382000", \ - "0.0289238000, 0.0335016000, 0.0442013000, 0.0681188000, 0.1229044000, 0.2654562000, 0.6546955000", \ - "0.0291595000, 0.0336807000, 0.0439783000, 0.0678587000, 0.1230017000, 0.2656878000, 0.6566361000", \ - "0.0289371000, 0.0337034000, 0.0445055000, 0.0685095000, 0.1229480000, 0.2654867000, 0.6493689000", \ - "0.0369875000, 0.0411434000, 0.0505975000, 0.0733364000, 0.1263021000, 0.2661904000, 0.6541810000", \ - "0.0528416000, 0.0583635000, 0.0687460000, 0.0892378000, 0.1380233000, 0.2739367000, 0.6539196000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0297789000, 0.0369937000, 0.0550252000, 0.1033466000, 0.2364782000, 0.5906948000, 1.4958118000", \ - "0.0297463000, 0.0370023000, 0.0550172000, 0.1032940000, 0.2365796000, 0.5876434000, 1.4970908000", \ - "0.0298299000, 0.0370811000, 0.0551772000, 0.1036259000, 0.2362236000, 0.5889645000, 1.5009696000", \ - "0.0312157000, 0.0381882000, 0.0558736000, 0.1038905000, 0.2364261000, 0.5906370000, 1.4949779000", \ - "0.0374807000, 0.0441130000, 0.0603438000, 0.1064736000, 0.2372842000, 0.5901808000, 1.4995692000", \ - "0.0512866000, 0.0571401000, 0.0710968000, 0.1124431000, 0.2389962000, 0.5870673000, 1.5025438000", \ - "0.0719464000, 0.0791653000, 0.0931257000, 0.1298796000, 0.2449473000, 0.5888542000, 1.4938044000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1776460000, 0.1849585000, 0.1999144000, 0.2286104000, 0.2847112000, 0.4064288000, 0.7049993000", \ - "0.1816940000, 0.1890152000, 0.2039484000, 0.2323190000, 0.2885453000, 0.4103121000, 0.7085386000", \ - "0.1918975000, 0.1992101000, 0.2141241000, 0.2427316000, 0.2988709000, 0.4206585000, 0.7187791000", \ - "0.2189970000, 0.2263828000, 0.2413590000, 0.2699013000, 0.3261236000, 0.4477649000, 0.7459366000", \ - "0.2854267000, 0.2927727000, 0.3075085000, 0.3362218000, 0.3924165000, 0.5139418000, 0.8121901000", \ - "0.4218725000, 0.4301982000, 0.4464095000, 0.4763566000, 0.5339416000, 0.6568709000, 0.9551625000", \ - "0.6358339000, 0.6469944000, 0.6680628000, 0.7041323000, 0.7657957000, 0.8913092000, 1.1918595000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0811213000, 0.0896763000, 0.1081402000, 0.1485182000, 0.2455107000, 0.4946031000, 1.1406899000", \ - "0.0856440000, 0.0941990000, 0.1126536000, 0.1530470000, 0.2500893000, 0.4974486000, 1.1426753000", \ - "0.0950767000, 0.1035898000, 0.1219628000, 0.1623250000, 0.2591995000, 0.5077734000, 1.1468876000", \ - "0.1147847000, 0.1233242000, 0.1416494000, 0.1819601000, 0.2792134000, 0.5268234000, 1.1829688000", \ - "0.1468687000, 0.1562328000, 0.1757224000, 0.2169534000, 0.3142956000, 0.5622990000, 1.2051147000", \ - "0.1857602000, 0.1972709000, 0.2196650000, 0.2635800000, 0.3618081000, 0.6098903000, 1.2531933000", \ - "0.2126072000, 0.2279490000, 0.2572436000, 0.3080884000, 0.4094372000, 0.6582406000, 1.2985629000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0299048000, 0.0345351000, 0.0450845000, 0.0686701000, 0.1236140000, 0.2661315000, 0.6501799000", \ - "0.0300458000, 0.0345519000, 0.0455218000, 0.0688156000, 0.1236766000, 0.2656903000, 0.6533392000", \ - "0.0301004000, 0.0346148000, 0.0455235000, 0.0683746000, 0.1237403000, 0.2657722000, 0.6555761000", \ - "0.0299535000, 0.0349537000, 0.0449014000, 0.0687128000, 0.1233169000, 0.2655819000, 0.6545185000", \ - "0.0301557000, 0.0347145000, 0.0451828000, 0.0681784000, 0.1233011000, 0.2656113000, 0.6559836000", \ - "0.0368030000, 0.0412594000, 0.0503183000, 0.0730693000, 0.1256954000, 0.2666548000, 0.6542736000", \ - "0.0533462000, 0.0581871000, 0.0687494000, 0.0885752000, 0.1364608000, 0.2731066000, 0.6541366000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0297858000, 0.0368668000, 0.0549596000, 0.1035997000, 0.2367330000, 0.5902081000, 1.5081822000", \ - "0.0297874000, 0.0368790000, 0.0550047000, 0.1035653000, 0.2363349000, 0.5887774000, 1.5053990000", \ - "0.0298101000, 0.0370397000, 0.0550923000, 0.1033475000, 0.2366198000, 0.5908155000, 1.4967700000", \ - "0.0306006000, 0.0376697000, 0.0555054000, 0.1037996000, 0.2366377000, 0.5890691000, 1.5030808000", \ - "0.0353153000, 0.0423671000, 0.0592950000, 0.1056253000, 0.2367856000, 0.5871764000, 1.4979843000", \ - "0.0465139000, 0.0527190000, 0.0681950000, 0.1116825000, 0.2390358000, 0.5866532000, 1.4969179000", \ - "0.0658634000, 0.0732970000, 0.0880352000, 0.1262412000, 0.2440359000, 0.5897067000, 1.4918292000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32o_2") { - leakage_power () { - value : 0.0085240000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0080156000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041161000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0083968000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0085472000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0080388000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041161000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0084199000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0085371000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0080287000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041161000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0084098000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0090478000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0085393000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041159000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0089205000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0085415000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0080331000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041161000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0084142000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0088850000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0083766000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041159000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0087578000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0087723000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0082639000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041159000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0086451000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0032881000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0034224000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0011109000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0033903000; - when : "A1&A2&A3&B1&!B2"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a32o"; - cell_leakage_power : 0.0068168340; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044057000, 0.0044064000, 0.0044081000, 0.0044085000, 0.0044096000, 0.0044122000, 0.0044179000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003271100, -0.003273800, -0.003280000, -0.003273300, -0.003257700, -0.003221700, -0.003139000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023610000; - } - pin ("A2") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043079000, 0.0042965000, 0.0042703000, 0.0042870000, 0.0043257000, 0.0044147000, 0.0046198000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003902700, -0.003899700, -0.003892800, -0.003892500, -0.003891600, -0.003889500, -0.003884900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024360000; - } - pin ("A3") { - capacitance : 0.0023030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040017000, 0.0039984000, 0.0039908000, 0.0039880000, 0.0039817000, 0.0039671000, 0.0039334000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003984300, -0.003981700, -0.003975900, -0.003976900, -0.003979100, -0.003984300, -0.003996300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("B1") { - capacitance : 0.0022850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046086000, 0.0046091000, 0.0046103000, 0.0046114000, 0.0046138000, 0.0046194000, 0.0046322000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003553800, -0.003557900, -0.003567500, -0.003560700, -0.003545200, -0.003509500, -0.003427100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024290000; - } - pin ("B2") { - capacitance : 0.0024630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044886000, 0.0044886000, 0.0044887000, 0.0044900000, 0.0044930000, 0.0045000000, 0.0045160000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004491400, -0.004489400, -0.004484700, -0.004485300, -0.004486600, -0.004489700, -0.004497000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026560000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0186249000, 0.0172232000, 0.0137098000, 0.0037379000, -0.028403900, -0.125112800, -0.402741300", \ - "0.0185428000, 0.0171409000, 0.0136717000, 0.0036628000, -0.028495300, -0.125190300, -0.402771600", \ - "0.0184395000, 0.0170362000, 0.0135431000, 0.0034441000, -0.028713800, -0.125400900, -0.402987800", \ - "0.0181024000, 0.0167248000, 0.0132034000, 0.0030777000, -0.029047300, -0.125659500, -0.403323700", \ - "0.0177577000, 0.0163569000, 0.0128917000, 0.0027643000, -0.029409100, -0.125994800, -0.403595200", \ - "0.0177195000, 0.0163462000, 0.0127909000, 0.0026477000, -0.029615000, -0.126270600, -0.403752400", \ - "0.0226239000, 0.0210072000, 0.0165214000, 0.0042923000, -0.029703200, -0.126448000, -0.403803100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0191082000, 0.0207161000, 0.0252219000, 0.0377916000, 0.0724169000, 0.1698941000, 0.4450598000", \ - "0.0190080000, 0.0206100000, 0.0251129000, 0.0376862000, 0.0723205000, 0.1698020000, 0.4449810000", \ - "0.0188659000, 0.0204609000, 0.0249787000, 0.0375257000, 0.0722277000, 0.1694383000, 0.4448639000", \ - "0.0187081000, 0.0203039000, 0.0248072000, 0.0373125000, 0.0719517000, 0.1692409000, 0.4445445000", \ - "0.0186571000, 0.0202237000, 0.0246008000, 0.0370145000, 0.0715135000, 0.1690286000, 0.4443363000", \ - "0.0194641000, 0.0209306000, 0.0251455000, 0.0370415000, 0.0713819000, 0.1683417000, 0.4441727000", \ - "0.0211543000, 0.0225817000, 0.0266238000, 0.0387556000, 0.0727548000, 0.1698169000, 0.4438529000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0216522000, 0.0202361000, 0.0166975000, 0.0066354000, -0.025471700, -0.122100300, -0.399633500", \ - "0.0214464000, 0.0200169000, 0.0164650000, 0.0065202000, -0.025566200, -0.122202300, -0.399741200", \ - "0.0212896000, 0.0198644000, 0.0163136000, 0.0062827000, -0.025804200, -0.122352300, -0.399852900", \ - "0.0210540000, 0.0196265000, 0.0160912000, 0.0060427000, -0.025977300, -0.122583300, -0.400077800", \ - "0.0207994000, 0.0194099000, 0.0158713000, 0.0056901000, -0.026322100, -0.122901400, -0.400376600", \ - "0.0206565000, 0.0191962000, 0.0159442000, 0.0056637000, -0.026559100, -0.123126900, -0.400564600", \ - "0.0254080000, 0.0237492000, 0.0192752000, 0.0071244000, -0.026448400, -0.123371500, -0.400750100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0197474000, 0.0213474000, 0.0258728000, 0.0384243000, 0.0730604000, 0.1705330000, 0.4457132000", \ - "0.0196501000, 0.0212545000, 0.0257662000, 0.0383385000, 0.0729716000, 0.1704356000, 0.4456061000", \ - "0.0195086000, 0.0211215000, 0.0256239000, 0.0381953000, 0.0728033000, 0.1702821000, 0.4454303000", \ - "0.0193441000, 0.0209473000, 0.0254465000, 0.0379945000, 0.0725724000, 0.1698489000, 0.4447341000", \ - "0.0192590000, 0.0208443000, 0.0252602000, 0.0377502000, 0.0722307000, 0.1695921000, 0.4446012000", \ - "0.0198852000, 0.0213461000, 0.0256029000, 0.0374998000, 0.0720538000, 0.1690941000, 0.4447417000", \ - "0.0210746000, 0.0225212000, 0.0266460000, 0.0387844000, 0.0728674000, 0.1700131000, 0.4438904000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0242894000, 0.0229408000, 0.0193894000, 0.0092899000, -0.022700900, -0.119224700, -0.396583800", \ - "0.0242610000, 0.0228272000, 0.0192833000, 0.0093957000, -0.022716700, -0.119341500, -0.396769000", \ - "0.0242946000, 0.0228507000, 0.0193366000, 0.0091690000, -0.022872700, -0.119425100, -0.396780100", \ - "0.0240833000, 0.0226628000, 0.0191231000, 0.0089940000, -0.023060500, -0.119474000, -0.396917800", \ - "0.0238821000, 0.0224597000, 0.0189589000, 0.0088628000, -0.023232100, -0.119758700, -0.397161800", \ - "0.0237900000, 0.0223350000, 0.0190696000, 0.0087285000, -0.023384500, -0.119869500, -0.397214000", \ - "0.0289631000, 0.0273087000, 0.0228813000, 0.0107406000, -0.023286900, -0.120045100, -0.397196700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0196094000, 0.0212199000, 0.0257262000, 0.0383014000, 0.0729129000, 0.1703906000, 0.4464765000", \ - "0.0195302000, 0.0211266000, 0.0256395000, 0.0381810000, 0.0728985000, 0.1701763000, 0.4454132000", \ - "0.0193817000, 0.0209820000, 0.0254927000, 0.0380651000, 0.0726989000, 0.1701834000, 0.4453486000", \ - "0.0192166000, 0.0208179000, 0.0253176000, 0.0378779000, 0.0724723000, 0.1697236000, 0.4446623000", \ - "0.0191361000, 0.0207054000, 0.0251592000, 0.0376032000, 0.0722040000, 0.1695788000, 0.4448173000", \ - "0.0197197000, 0.0212172000, 0.0255037000, 0.0375074000, 0.0720347000, 0.1690990000, 0.4447108000", \ - "0.0208368000, 0.0222773000, 0.0263830000, 0.0386408000, 0.0728232000, 0.1699773000, 0.4435403000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0184795000, 0.0170553000, 0.0135838000, 0.0034623000, -0.028703900, -0.125407900, -0.402923700", \ - "0.0182388000, 0.0168429000, 0.0132874000, 0.0032183000, -0.028916000, -0.125564400, -0.403078500", \ - "0.0179496000, 0.0165269000, 0.0129946000, 0.0029472000, -0.029221100, -0.125844500, -0.403333300", \ - "0.0177301000, 0.0162988000, 0.0127468000, 0.0026571000, -0.029562000, -0.126060300, -0.403590900", \ - "0.0177022000, 0.0162921000, 0.0127390000, 0.0025177000, -0.029695600, -0.126276500, -0.403711000", \ - "0.0183709000, 0.0168952000, 0.0131119000, 0.0029239000, -0.029382700, -0.125930000, -0.403265500", \ - "0.0244641000, 0.0227159000, 0.0180256000, 0.0056469000, -0.028661200, -0.125457600, -0.402697800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0158547000, 0.0174900000, 0.0219868000, 0.0343511000, 0.0686280000, 0.1656941000, 0.4411693000", \ - "0.0158320000, 0.0174600000, 0.0219460000, 0.0343336000, 0.0686317000, 0.1654882000, 0.4384952000", \ - "0.0157124000, 0.0173361000, 0.0218267000, 0.0341745000, 0.0685026000, 0.1654192000, 0.4385130000", \ - "0.0155037000, 0.0170892000, 0.0215052000, 0.0338068000, 0.0681380000, 0.1644300000, 0.4380869000", \ - "0.0153571000, 0.0169064000, 0.0212920000, 0.0334024000, 0.0677418000, 0.1647715000, 0.4403369000", \ - "0.0161700000, 0.0176229000, 0.0218355000, 0.0338763000, 0.0678693000, 0.1644223000, 0.4380991000", \ - "0.0180965000, 0.0194899000, 0.0234709000, 0.0356349000, 0.0695356000, 0.1659652000, 0.4391794000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0213269000, 0.0199371000, 0.0164024000, 0.0063132000, -0.025780100, -0.122275200, -0.399731500", \ - "0.0213285000, 0.0198782000, 0.0163668000, 0.0062849000, -0.025844200, -0.122430100, -0.399839300", \ - "0.0210490000, 0.0196152000, 0.0161351000, 0.0060378000, -0.026091900, -0.122664600, -0.400143600", \ - "0.0208169000, 0.0193923000, 0.0158254000, 0.0058167000, -0.026321500, -0.122904000, -0.400309600", \ - "0.0206928000, 0.0192816000, 0.0156702000, 0.0055886000, -0.026633700, -0.123137200, -0.400517400", \ - "0.0211304000, 0.0196259000, 0.0159090000, 0.0057782000, -0.026560200, -0.123025300, -0.400286500", \ - "0.0278782000, 0.0261758000, 0.0215308000, 0.0097140000, -0.024825000, -0.121646300, -0.398826400"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0168419000, 0.0184222000, 0.0229423000, 0.0353195000, 0.0695159000, 0.1662324000, 0.4391818000", \ - "0.0167880000, 0.0184142000, 0.0229158000, 0.0352743000, 0.0694917000, 0.1662555000, 0.4392097000", \ - "0.0166218000, 0.0182403000, 0.0227298000, 0.0350742000, 0.0693234000, 0.1661373000, 0.4388052000", \ - "0.0163254000, 0.0179118000, 0.0223607000, 0.0346853000, 0.0690011000, 0.1652161000, 0.4414668000", \ - "0.0160942000, 0.0176343000, 0.0220768000, 0.0342357000, 0.0685446000, 0.1656964000, 0.4387816000", \ - "0.0166533000, 0.0181329000, 0.0224316000, 0.0345215000, 0.0685784000, 0.1649594000, 0.4408935000", \ - "0.0182356000, 0.0196448000, 0.0237595000, 0.0357752000, 0.0699981000, 0.1670127000, 0.4399069000"); - } - } - max_capacitance : 0.2645970000; - max_transition : 1.5022100000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.2055854000, 0.2110921000, 0.2236333000, 0.2493651000, 0.2996294000, 0.4075911000, 0.6808221000", \ - "0.2109408000, 0.2164478000, 0.2290216000, 0.2543667000, 0.3049625000, 0.4129570000, 0.6861518000", \ - "0.2236106000, 0.2291260000, 0.2416656000, 0.2673420000, 0.3175681000, 0.4255544000, 0.6987729000", \ - "0.2528429000, 0.2583272000, 0.2708249000, 0.2964682000, 0.3467771000, 0.4548456000, 0.7279137000", \ - "0.3163790000, 0.3219580000, 0.3344682000, 0.3600716000, 0.4106193000, 0.5187447000, 0.7916444000", \ - "0.4470668000, 0.4531790000, 0.4666452000, 0.4938867000, 0.5463802000, 0.6556837000, 0.9290985000", \ - "0.6718474000, 0.6792295000, 0.6953804000, 0.7276748000, 0.7877178000, 0.9053794000, 1.1826160000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1182213000, 0.1251615000, 0.1414062000, 0.1782550000, 0.2667622000, 0.5071378000, 1.1845129000", \ - "0.1218355000, 0.1287745000, 0.1450423000, 0.1818795000, 0.2704030000, 0.5107658000, 1.1883838000", \ - "0.1309177000, 0.1377942000, 0.1541154000, 0.1908344000, 0.2795387000, 0.5203856000, 1.1960810000", \ - "0.1532791000, 0.1601444000, 0.1764066000, 0.2130378000, 0.3015731000, 0.5415071000, 1.2183931000", \ - "0.1982168000, 0.2052352000, 0.2218045000, 0.2586178000, 0.3472067000, 0.5878067000, 1.2668486000", \ - "0.2550987000, 0.2633186000, 0.2818173000, 0.3203220000, 0.4098789000, 0.6499921000, 1.3298265000", \ - "0.3015443000, 0.3119622000, 0.3349925000, 0.3801940000, 0.4722037000, 0.7117169000, 1.3887402000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0305041000, 0.0341172000, 0.0425133000, 0.0603051000, 0.1051299000, 0.2229413000, 0.5753767000", \ - "0.0303991000, 0.0339600000, 0.0420544000, 0.0612709000, 0.1048515000, 0.2230665000, 0.5753582000", \ - "0.0304488000, 0.0337288000, 0.0424293000, 0.0602959000, 0.1048894000, 0.2229214000, 0.5757014000", \ - "0.0303915000, 0.0338385000, 0.0418004000, 0.0608236000, 0.1050620000, 0.2228725000, 0.5753378000", \ - "0.0303088000, 0.0340312000, 0.0418619000, 0.0603480000, 0.1049327000, 0.2228275000, 0.5740898000", \ - "0.0348172000, 0.0385512000, 0.0469105000, 0.0659280000, 0.1084704000, 0.2239489000, 0.5755436000", \ - "0.0471511000, 0.0513153000, 0.0607862000, 0.0808770000, 0.1247265000, 0.2383054000, 0.5775325000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0322325000, 0.0376553000, 0.0518548000, 0.0905344000, 0.2034135000, 0.5396604000, 1.4992125000", \ - "0.0321175000, 0.0376590000, 0.0518162000, 0.0905229000, 0.2034285000, 0.5396886000, 1.4994402000", \ - "0.0321981000, 0.0376070000, 0.0519032000, 0.0903789000, 0.2035084000, 0.5387992000, 1.4980109000", \ - "0.0320752000, 0.0375579000, 0.0518020000, 0.0903683000, 0.2035193000, 0.5388130000, 1.4986742000", \ - "0.0344882000, 0.0396678000, 0.0536040000, 0.0915998000, 0.2039419000, 0.5383244000, 1.4959374000", \ - "0.0428427000, 0.0480282000, 0.0607206000, 0.0966855000, 0.2062648000, 0.5374665000, 1.4983792000", \ - "0.0573512000, 0.0635482000, 0.0785530000, 0.1116196000, 0.2121167000, 0.5404130000, 1.4938167000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.2284532000, 0.2341581000, 0.2472548000, 0.2735050000, 0.3247070000, 0.4333937000, 0.7070260000", \ - "0.2339089000, 0.2396556000, 0.2526216000, 0.2786658000, 0.3296497000, 0.4385978000, 0.7124153000", \ - "0.2468927000, 0.2526438000, 0.2656122000, 0.2919061000, 0.3427346000, 0.4515147000, 0.7250987000", \ - "0.2763650000, 0.2821028000, 0.2950791000, 0.3213535000, 0.3722113000, 0.4809987000, 0.7546057000", \ - "0.3392990000, 0.3449331000, 0.3578965000, 0.3844792000, 0.4357815000, 0.5447099000, 0.8183959000", \ - "0.4726582000, 0.4787825000, 0.4925342000, 0.5198396000, 0.5722855000, 0.6818424000, 0.9556209000", \ - "0.7051930000, 0.7126387000, 0.7289978000, 0.7609529000, 0.8201367000, 0.9374570000, 1.2143031000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1264165000, 0.1333797000, 0.1497313000, 0.1864609000, 0.2749837000, 0.5152954000, 1.1926075000", \ - "0.1304753000, 0.1374076000, 0.1536602000, 0.1905105000, 0.2790154000, 0.5192122000, 1.1963688000", \ - "0.1393565000, 0.1463140000, 0.1625383000, 0.1993959000, 0.2878568000, 0.5278505000, 1.2046429000", \ - "0.1598204000, 0.1667624000, 0.1830580000, 0.2197524000, 0.3081871000, 0.5476916000, 1.2238471000", \ - "0.2015533000, 0.2086227000, 0.2253441000, 0.2623487000, 0.3507894000, 0.5909401000, 1.2676858000", \ - "0.2613224000, 0.2694420000, 0.2877946000, 0.3267334000, 0.4163748000, 0.6565676000, 1.3350724000", \ - "0.3178668000, 0.3280410000, 0.3507709000, 0.3957110000, 0.4885392000, 0.7284141000, 1.4052436000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0323756000, 0.0358227000, 0.0439288000, 0.0622489000, 0.1063838000, 0.2237113000, 0.5759031000", \ - "0.0327036000, 0.0357259000, 0.0443603000, 0.0623902000, 0.1065432000, 0.2240862000, 0.5764570000", \ - "0.0326911000, 0.0357436000, 0.0437084000, 0.0622581000, 0.1068890000, 0.2237145000, 0.5751005000", \ - "0.0327850000, 0.0357806000, 0.0437482000, 0.0622530000, 0.1068263000, 0.2237192000, 0.5751942000", \ - "0.0325003000, 0.0364642000, 0.0439879000, 0.0628169000, 0.1064610000, 0.2241659000, 0.5762126000", \ - "0.0360510000, 0.0395878000, 0.0482308000, 0.0657341000, 0.1088642000, 0.2250334000, 0.5758087000", \ - "0.0481863000, 0.0517842000, 0.0611217000, 0.0804789000, 0.1240977000, 0.2379044000, 0.5778434000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0323324000, 0.0375656000, 0.0519055000, 0.0905210000, 0.2034168000, 0.5397536000, 1.4991338000", \ - "0.0322117000, 0.0376492000, 0.0518485000, 0.0905315000, 0.2033636000, 0.5398229000, 1.4985775000", \ - "0.0322653000, 0.0376399000, 0.0518815000, 0.0905240000, 0.2031028000, 0.5395659000, 1.4969791000", \ - "0.0320662000, 0.0375672000, 0.0519484000, 0.0904438000, 0.2036458000, 0.5379020000, 1.4935435000", \ - "0.0342020000, 0.0396585000, 0.0532985000, 0.0915432000, 0.2034794000, 0.5384681000, 1.4952654000", \ - "0.0410641000, 0.0466852000, 0.0602345000, 0.0963388000, 0.2066925000, 0.5386586000, 1.4986413000", \ - "0.0543667000, 0.0604638000, 0.0750317000, 0.1099032000, 0.2121422000, 0.5400645000, 1.4914880000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.2269836000, 0.2327557000, 0.2453776000, 0.2710488000, 0.3208036000, 0.4282181000, 0.7016301000", \ - "0.2324312000, 0.2380691000, 0.2507623000, 0.2762235000, 0.3262260000, 0.4336531000, 0.7069259000", \ - "0.2457726000, 0.2514117000, 0.2641139000, 0.2898129000, 0.3395582000, 0.4469992000, 0.7202431000", \ - "0.2747203000, 0.2803101000, 0.2930035000, 0.3185201000, 0.3686273000, 0.4759800000, 0.7491352000", \ - "0.3346086000, 0.3402461000, 0.3529497000, 0.3786586000, 0.4288480000, 0.5362156000, 0.8093760000", \ - "0.4582212000, 0.4642606000, 0.4781270000, 0.5045407000, 0.5557532000, 0.6641063000, 0.9375404000", \ - "0.6702651000, 0.6774640000, 0.6934696000, 0.7246850000, 0.7827745000, 0.8980726000, 1.1745148000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1301089000, 0.1370481000, 0.1532899000, 0.1901520000, 0.2786217000, 0.5186041000, 1.1954466000", \ - "0.1342951000, 0.1411774000, 0.1574880000, 0.1942543000, 0.2829353000, 0.5237151000, 1.2023478000", \ - "0.1426532000, 0.1496081000, 0.1658487000, 0.2027081000, 0.2912513000, 0.5315168000, 1.2088665000", \ - "0.1603962000, 0.1673702000, 0.1836628000, 0.2203753000, 0.3088709000, 0.5486235000, 1.2251608000", \ - "0.1966352000, 0.2038006000, 0.2205112000, 0.2574026000, 0.3460650000, 0.5861741000, 1.2632682000", \ - "0.2530536000, 0.2609891000, 0.2792384000, 0.3183034000, 0.4082608000, 0.6481000000, 1.3266050000", \ - "0.3150981000, 0.3249968000, 0.3470988000, 0.3915029000, 0.4849980000, 0.7254973000, 1.4014684000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0318914000, 0.0353962000, 0.0429334000, 0.0609984000, 0.1046674000, 0.2218236000, 0.5757066000", \ - "0.0317330000, 0.0350600000, 0.0427337000, 0.0610477000, 0.1043061000, 0.2221821000, 0.5749551000", \ - "0.0320586000, 0.0350073000, 0.0428915000, 0.0608003000, 0.1047636000, 0.2220256000, 0.5750014000", \ - "0.0319770000, 0.0357053000, 0.0430791000, 0.0613133000, 0.1042543000, 0.2215619000, 0.5753457000", \ - "0.0317780000, 0.0351054000, 0.0430809000, 0.0609607000, 0.1042660000, 0.2219076000, 0.5739109000", \ - "0.0354203000, 0.0388467000, 0.0468887000, 0.0646051000, 0.1071151000, 0.2226487000, 0.5758864000", \ - "0.0464188000, 0.0502686000, 0.0589924000, 0.0774904000, 0.1214110000, 0.2338879000, 0.5758038000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0322308000, 0.0376534000, 0.0518664000, 0.0905262000, 0.2031032000, 0.5396087000, 1.4970706000", \ - "0.0321791000, 0.0376263000, 0.0518045000, 0.0904013000, 0.2035638000, 0.5387081000, 1.4958560000", \ - "0.0323229000, 0.0375975000, 0.0518791000, 0.0905207000, 0.2034860000, 0.5398067000, 1.4991132000", \ - "0.0322948000, 0.0375606000, 0.0519580000, 0.0904730000, 0.2036522000, 0.5375587000, 1.4945202000", \ - "0.0338496000, 0.0392740000, 0.0530390000, 0.0913815000, 0.2036108000, 0.5388451000, 1.4989123000", \ - "0.0391994000, 0.0450069000, 0.0590754000, 0.0961485000, 0.2059783000, 0.5385287000, 1.4991353000", \ - "0.0513433000, 0.0577102000, 0.0722486000, 0.1084650000, 0.2118647000, 0.5399328000, 1.4931166000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1882062000, 0.1937409000, 0.2061803000, 0.2317136000, 0.2813272000, 0.3886133000, 0.6615586000", \ - "0.1922477000, 0.1978128000, 0.2102915000, 0.2356271000, 0.2851860000, 0.3924042000, 0.6653422000", \ - "0.2020860000, 0.2076037000, 0.2201567000, 0.2452978000, 0.2952570000, 0.4024449000, 0.6755101000", \ - "0.2296672000, 0.2351515000, 0.2476049000, 0.2731247000, 0.3229680000, 0.4303095000, 0.7032443000", \ - "0.2966096000, 0.3021074000, 0.3146901000, 0.3400199000, 0.3898853000, 0.4973608000, 0.7704396000", \ - "0.4442908000, 0.4506784000, 0.4645146000, 0.4916325000, 0.5430475000, 0.6511280000, 0.9245701000", \ - "0.6843129000, 0.6923019000, 0.7100043000, 0.7443088000, 0.8036366000, 0.9170608000, 1.1934764000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0813524000, 0.0878791000, 0.1031341000, 0.1376076000, 0.2234476000, 0.4620663000, 1.1417712000", \ - "0.0857208000, 0.0922394000, 0.1074969000, 0.1419756000, 0.2278177000, 0.4666662000, 1.1413936000", \ - "0.0957668000, 0.1022772000, 0.1175033000, 0.1519132000, 0.2377323000, 0.4761578000, 1.1512031000", \ - "0.1183218000, 0.1248327000, 0.1400296000, 0.1744225000, 0.2602355000, 0.4988165000, 1.1744981000", \ - "0.1525599000, 0.1601454000, 0.1767221000, 0.2125444000, 0.2991762000, 0.5377833000, 1.2156139000", \ - "0.1881525000, 0.1980048000, 0.2187171000, 0.2583315000, 0.3465155000, 0.5849980000, 1.2616870000", \ - "0.2035003000, 0.2160375000, 0.2428693000, 0.2928038000, 0.3867628000, 0.6243722000, 1.2998924000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0312716000, 0.0346549000, 0.0423515000, 0.0603662000, 0.1040993000, 0.2218572000, 0.5745084000", \ - "0.0312723000, 0.0346677000, 0.0423065000, 0.0603637000, 0.1043720000, 0.2217377000, 0.5742566000", \ - "0.0312909000, 0.0343211000, 0.0426613000, 0.0611163000, 0.1040027000, 0.2218562000, 0.5755730000", \ - "0.0310627000, 0.0347278000, 0.0424063000, 0.0601763000, 0.1042410000, 0.2216842000, 0.5752570000", \ - "0.0310510000, 0.0344164000, 0.0428825000, 0.0604510000, 0.1040209000, 0.2215704000, 0.5751379000", \ - "0.0384751000, 0.0419893000, 0.0498148000, 0.0664216000, 0.1073956000, 0.2232157000, 0.5757952000", \ - "0.0565188000, 0.0607878000, 0.0704557000, 0.0883824000, 0.1252258000, 0.2342387000, 0.5770151000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0289043000, 0.0341693000, 0.0476923000, 0.0855263000, 0.1997875000, 0.5367517000, 1.5007774000", \ - "0.0288749000, 0.0341661000, 0.0476387000, 0.0854988000, 0.1998578000, 0.5361042000, 1.4953351000", \ - "0.0289058000, 0.0341747000, 0.0477077000, 0.0855823000, 0.1997018000, 0.5370337000, 1.4928601000", \ - "0.0298328000, 0.0349719000, 0.0481918000, 0.0858982000, 0.1995666000, 0.5349267000, 1.4904189000", \ - "0.0369973000, 0.0418069000, 0.0537691000, 0.0893350000, 0.2009709000, 0.5367758000, 1.4995108000", \ - "0.0505515000, 0.0559323000, 0.0669878000, 0.0981917000, 0.2039311000, 0.5356335000, 1.4925985000", \ - "0.0702332000, 0.0769211000, 0.0912055000, 0.1215252000, 0.2137915000, 0.5382449000, 1.4896063000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.2019866000, 0.2076768000, 0.2203626000, 0.2459821000, 0.2962456000, 0.4032251000, 0.6761630000", \ - "0.2057334000, 0.2113774000, 0.2240853000, 0.2498040000, 0.2999992000, 0.4068521000, 0.6801345000", \ - "0.2157536000, 0.2213869000, 0.2340823000, 0.2597596000, 0.3099851000, 0.4168931000, 0.6901738000", \ - "0.2420664000, 0.2477034000, 0.2603758000, 0.2860611000, 0.3361567000, 0.4437427000, 0.7169412000", \ - "0.3085664000, 0.3142198000, 0.3268607000, 0.3525164000, 0.4026262000, 0.5100246000, 0.7834656000", \ - "0.4529158000, 0.4591694000, 0.4729067000, 0.4998614000, 0.5512634000, 0.6593585000, 0.9331590000", \ - "0.6853177000, 0.6936265000, 0.7113244000, 0.7456479000, 0.8041402000, 0.9170186000, 1.1931693000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0870298000, 0.0935583000, 0.1088000000, 0.1432835000, 0.2288826000, 0.4673008000, 1.1418939000", \ - "0.0914013000, 0.0979200000, 0.1131730000, 0.1476029000, 0.2331816000, 0.4713299000, 1.1461926000", \ - "0.1004236000, 0.1069206000, 0.1221531000, 0.1565779000, 0.2422157000, 0.4804886000, 1.1574764000", \ - "0.1197516000, 0.1262727000, 0.1414273000, 0.1758986000, 0.2618090000, 0.4996811000, 1.1808642000", \ - "0.1514500000, 0.1586745000, 0.1750992000, 0.2108479000, 0.2974157000, 0.5361876000, 1.2108435000", \ - "0.1891430000, 0.1982157000, 0.2176763000, 0.2567448000, 0.3449430000, 0.5832477000, 1.2617946000", \ - "0.2116101000, 0.2234138000, 0.2488552000, 0.2966355000, 0.3899990000, 0.6290524000, 1.3037820000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0319562000, 0.0357568000, 0.0431368000, 0.0613971000, 0.1042656000, 0.2222587000, 0.5758915000", \ - "0.0320944000, 0.0349788000, 0.0428950000, 0.0608187000, 0.1043285000, 0.2221482000, 0.5763515000", \ - "0.0320234000, 0.0349938000, 0.0429004000, 0.0607759000, 0.1042899000, 0.2219869000, 0.5760368000", \ - "0.0319160000, 0.0352113000, 0.0432614000, 0.0613967000, 0.1044524000, 0.2221215000, 0.5749662000", \ - "0.0317260000, 0.0353096000, 0.0427451000, 0.0608560000, 0.1042809000, 0.2219889000, 0.5754255000", \ - "0.0384762000, 0.0418032000, 0.0494709000, 0.0663902000, 0.1071391000, 0.2230596000, 0.5756468000", \ - "0.0562030000, 0.0605446000, 0.0699977000, 0.0861699000, 0.1239265000, 0.2330434000, 0.5773531000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0288140000, 0.0339932000, 0.0475996000, 0.0856656000, 0.1998889000, 0.5361550000, 1.4949206000", \ - "0.0288884000, 0.0341541000, 0.0476751000, 0.0855692000, 0.1997318000, 0.5370010000, 1.4924439000", \ - "0.0287631000, 0.0340550000, 0.0477047000, 0.0856542000, 0.1997441000, 0.5369919000, 1.4956901000", \ - "0.0293235000, 0.0346295000, 0.0480911000, 0.0858246000, 0.1997325000, 0.5356141000, 1.5022100000", \ - "0.0342557000, 0.0394191000, 0.0522176000, 0.0887443000, 0.2004995000, 0.5365238000, 1.4925728000", \ - "0.0453122000, 0.0502509000, 0.0627251000, 0.0958885000, 0.2034524000, 0.5354723000, 1.4952349000", \ - "0.0630617000, 0.0697908000, 0.0832787000, 0.1141074000, 0.2117839000, 0.5375477000, 1.4919928000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32o_4") { - leakage_power () { - value : 0.0053900000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0047000000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057453000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0052260000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0054184000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0047285000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057453000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0052546000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0054237000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0047338000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057453000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0052599000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0061047000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0054147000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057453000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0059408000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0054350000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0047430000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057453000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0052703000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0059403000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0052501000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057462000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0057746000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0059702000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0052780000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0057452000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0058030000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0060543000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0062855000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0022874000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0062303000; - when : "A1&A2&A3&B1&!B2"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a32o"; - cell_leakage_power : 0.0054417170; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092163000, 0.0092109000, 0.0091985000, 0.0092000000, 0.0092035000, 0.0092117000, 0.0092305000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006441700, -0.006446300, -0.006456800, -0.006441100, -0.006404800, -0.006321100, -0.006128300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044410000; - } - pin ("A2") { - capacitance : 0.0042840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085840000, 0.0085770000, 0.0085610000, 0.0085894000, 0.0086551000, 0.0088063000, 0.0091550000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007914300, -0.007916600, -0.007922000, -0.007923900, -0.007928400, -0.007938800, -0.007962600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044700000; - } - pin ("A3") { - capacitance : 0.0044660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082592000, 0.0082553000, 0.0082462000, 0.0082495000, 0.0082572000, 0.0082749000, 0.0083156000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008244000, -0.008243400, -0.008242000, -0.008241000, -0.008238700, -0.008233500, -0.008221400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047390000; - } - pin ("B1") { - capacitance : 0.0043510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092281000, 0.0092271000, 0.0092248000, 0.0092216000, 0.0092143000, 0.0091974000, 0.0091584000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006491400, -0.006495200, -0.006503900, -0.006485600, -0.006443300, -0.006346000, -0.006121600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046390000; - } - pin ("B2") { - capacitance : 0.0042810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077717000, 0.0077680000, 0.0077593000, 0.0077584000, 0.0077564000, 0.0077517000, 0.0077410000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007742300, -0.007741400, -0.007739300, -0.007735300, -0.007726100, -0.007704700, -0.007655600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046120000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3) | (B1&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0342602000, 0.0324812000, 0.0273363000, 0.0123641000, -0.040934700, -0.225160000, -0.821915200", \ - "0.0341961000, 0.0324186000, 0.0272692000, 0.0123104000, -0.040965000, -0.225182900, -0.822047400", \ - "0.0338849000, 0.0321275000, 0.0270072000, 0.0120676000, -0.041331200, -0.225409200, -0.822335400", \ - "0.0331047000, 0.0313484000, 0.0261855000, 0.0113140000, -0.041926100, -0.226045000, -0.822926900", \ - "0.0324500000, 0.0307449000, 0.0255575000, 0.0105755000, -0.042728500, -0.226808600, -0.823571000", \ - "0.0323963000, 0.0305780000, 0.0256120000, 0.0104790000, -0.043137300, -0.227131300, -0.823892900", \ - "0.0414712000, 0.0394609000, 0.0331187000, 0.0147159000, -0.043242200, -0.227570400, -0.823863700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0367803000, 0.0386147000, 0.0446528000, 0.0638584000, 0.1225574000, 0.3074977000, 0.8978022000", \ - "0.0365757000, 0.0384107000, 0.0444249000, 0.0635840000, 0.1225380000, 0.3074990000, 0.8989715000", \ - "0.0362881000, 0.0381363000, 0.0441131000, 0.0633860000, 0.1222306000, 0.3072220000, 0.8989063000", \ - "0.0358637000, 0.0376619000, 0.0436121000, 0.0628937000, 0.1218678000, 0.3067918000, 0.9017991000", \ - "0.0357507000, 0.0375508000, 0.0434290000, 0.0625891000, 0.1212801000, 0.3062719000, 0.8978020000", \ - "0.0372539000, 0.0389869000, 0.0445177000, 0.0625099000, 0.1211604000, 0.3059143000, 0.8975955000", \ - "0.0402019000, 0.0417823000, 0.0472307000, 0.0651464000, 0.1232055000, 0.3078066000, 0.8986330000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0406982000, 0.0388763000, 0.0336620000, 0.0187075000, -0.034419800, -0.218372900, -0.815193300", \ - "0.0405417000, 0.0387226000, 0.0334967000, 0.0187613000, -0.034669900, -0.218660900, -0.815305100", \ - "0.0402788000, 0.0384838000, 0.0332886000, 0.0182985000, -0.034949700, -0.218943700, -0.815568900", \ - "0.0396771000, 0.0379598000, 0.0327238000, 0.0177098000, -0.035574800, -0.219448300, -0.816066000", \ - "0.0391040000, 0.0373330000, 0.0320585000, 0.0171549000, -0.036162000, -0.220115700, -0.816701700", \ - "0.0389067000, 0.0370816000, 0.0317935000, 0.0165979000, -0.036586100, -0.220535400, -0.817115900", \ - "0.0478645000, 0.0458626000, 0.0397333000, 0.0212808000, -0.036819800, -0.221195800, -0.817496500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0382928000, 0.0400848000, 0.0460118000, 0.0652828000, 0.1241118000, 0.3085949000, 0.9033375000", \ - "0.0380635000, 0.0398769000, 0.0459248000, 0.0651104000, 0.1237636000, 0.3085899000, 0.9032305000", \ - "0.0377800000, 0.0395677000, 0.0455807000, 0.0648351000, 0.1234881000, 0.3081372000, 0.8989100000", \ - "0.0373949000, 0.0392154000, 0.0452322000, 0.0643806000, 0.1232014000, 0.3079666000, 0.8999176000", \ - "0.0371942000, 0.0389797000, 0.0448958000, 0.0640265000, 0.1226791000, 0.3073637000, 0.9018149000", \ - "0.0383541000, 0.0400699000, 0.0456764000, 0.0637769000, 0.1225226000, 0.3071360000, 0.8988616000", \ - "0.0411334000, 0.0427850000, 0.0482253000, 0.0662490000, 0.1245978000, 0.3088585000, 0.9000456000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0458395000, 0.0440631000, 0.0388324000, 0.0237211000, -0.029784600, -0.214094400, -0.810911600", \ - "0.0458673000, 0.0440329000, 0.0387107000, 0.0236921000, -0.029877200, -0.214273900, -0.811106000", \ - "0.0454233000, 0.0436281000, 0.0382976000, 0.0233242000, -0.030120200, -0.214385600, -0.811372900", \ - "0.0451701000, 0.0433358000, 0.0381143000, 0.0230132000, -0.030586500, -0.214765600, -0.811571200", \ - "0.0447974000, 0.0430015000, 0.0377458000, 0.0226057000, -0.030988600, -0.215162200, -0.811909300", \ - "0.0448495000, 0.0429822000, 0.0376031000, 0.0224175000, -0.030977700, -0.215159000, -0.811918600", \ - "0.0542026000, 0.0521646000, 0.0461137000, 0.0275517000, -0.030665100, -0.215258300, -0.811440300"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0381963000, 0.0400792000, 0.0460699000, 0.0652183000, 0.1239121000, 0.3083924000, 0.9016084000", \ - "0.0380115000, 0.0398077000, 0.0457509000, 0.0650199000, 0.1238274000, 0.3080837000, 0.9025915000", \ - "0.0377220000, 0.0395542000, 0.0455985000, 0.0648277000, 0.1234268000, 0.3077976000, 0.8983268000", \ - "0.0373870000, 0.0392220000, 0.0452285000, 0.0644798000, 0.1230566000, 0.3074994000, 0.8978428000", \ - "0.0371723000, 0.0389579000, 0.0448935000, 0.0639645000, 0.1226568000, 0.3075062000, 0.8985005000", \ - "0.0385059000, 0.0402483000, 0.0459591000, 0.0639118000, 0.1227272000, 0.3070491000, 0.8989336000", \ - "0.0407633000, 0.0424292000, 0.0480372000, 0.0661054000, 0.1245128000, 0.3085683000, 0.8972162000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0334345000, 0.0315838000, 0.0263427000, 0.0112358000, -0.042139500, -0.226246400, -0.822851200", \ - "0.0332666000, 0.0315019000, 0.0262572000, 0.0111534000, -0.042268600, -0.226373400, -0.823036900", \ - "0.0328134000, 0.0309714000, 0.0258076000, 0.0106541000, -0.042736900, -0.226733000, -0.823471700", \ - "0.0323909000, 0.0306015000, 0.0253382000, 0.0102217000, -0.043240000, -0.227279000, -0.823915600", \ - "0.0319498000, 0.0301391000, 0.0248747000, 0.0098146000, -0.043637200, -0.227620500, -0.824243300", \ - "0.0329422000, 0.0311270000, 0.0255844000, 0.0100789000, -0.043712900, -0.227601600, -0.824122900", \ - "0.0438520000, 0.0417263000, 0.0353631000, 0.0164638000, -0.042150300, -0.226595400, -0.822996700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0295724000, 0.0314990000, 0.0377403000, 0.0572210000, 0.1163367000, 0.3018058000, 0.8940574000", \ - "0.0295869000, 0.0315135000, 0.0376458000, 0.0572199000, 0.1163331000, 0.3017897000, 0.8930922000", \ - "0.0294413000, 0.0313489000, 0.0375763000, 0.0570421000, 0.1161150000, 0.3010373000, 0.8944190000", \ - "0.0291291000, 0.0310400000, 0.0371145000, 0.0563254000, 0.1153577000, 0.3010185000, 0.8931337000", \ - "0.0291258000, 0.0309374000, 0.0369541000, 0.0557764000, 0.1146545000, 0.3002908000, 0.8927529000", \ - "0.0304353000, 0.0321403000, 0.0377754000, 0.0561030000, 0.1142667000, 0.2988762000, 0.8914739000", \ - "0.0332218000, 0.0347188000, 0.0400913000, 0.0579054000, 0.1161520000, 0.3007143000, 0.8884842000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0402889000, 0.0384835000, 0.0332772000, 0.0181770000, -0.035204300, -0.219166300, -0.815586300", \ - "0.0400539000, 0.0382423000, 0.0329340000, 0.0179101000, -0.035325700, -0.219230900, -0.815850700", \ - "0.0397343000, 0.0380156000, 0.0327456000, 0.0176554000, -0.035706700, -0.219644400, -0.816036100", \ - "0.0395351000, 0.0377482000, 0.0324621000, 0.0173349000, -0.036066300, -0.219966400, -0.816474600", \ - "0.0391355000, 0.0373593000, 0.0320564000, 0.0170511000, -0.036413000, -0.220297500, -0.816737200", \ - "0.0405927000, 0.0388001000, 0.0332952000, 0.0179491000, -0.035672000, -0.219616800, -0.815971600", \ - "0.0531150000, 0.0509894000, 0.0446231000, 0.0255108000, -0.033456900, -0.218059500, -0.814490000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0308567000, 0.0327835000, 0.0390184000, 0.0585138000, 0.1175976000, 0.3026992000, 0.8956743000", \ - "0.0308621000, 0.0327897000, 0.0390669000, 0.0584977000, 0.1176537000, 0.3030899000, 0.8952564000", \ - "0.0307657000, 0.0326820000, 0.0388490000, 0.0583100000, 0.1175007000, 0.3029111000, 0.8901727000", \ - "0.0303975000, 0.0323087000, 0.0384963000, 0.0578146000, 0.1168637000, 0.3024753000, 0.8946058000", \ - "0.0300892000, 0.0319176000, 0.0379877000, 0.0569514000, 0.1159969000, 0.3016563000, 0.8966604000", \ - "0.0312110000, 0.0329692000, 0.0386857000, 0.0571847000, 0.1155186000, 0.3000721000, 0.8926748000", \ - "0.0333859000, 0.0350250000, 0.0405285000, 0.0585219000, 0.1172163000, 0.3017095000, 0.8929161000"); - } - } - max_capacitance : 0.5365090000; - max_transition : 1.5014820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2416561000, 0.2462427000, 0.2580539000, 0.2842765000, 0.3385462000, 0.4578538000, 0.7790916000", \ - "0.2473248000, 0.2519134000, 0.2637716000, 0.2900513000, 0.3442046000, 0.4636069000, 0.7846774000", \ - "0.2598859000, 0.2644685000, 0.2762517000, 0.3025166000, 0.3565060000, 0.4760202000, 0.7972008000", \ - "0.2892658000, 0.2938495000, 0.3056414000, 0.3318431000, 0.3856349000, 0.5054288000, 0.8263091000", \ - "0.3527044000, 0.3572154000, 0.3690483000, 0.3951287000, 0.4492522000, 0.5690736000, 0.8903359000", \ - "0.4855028000, 0.4903440000, 0.5028156000, 0.5301869000, 0.5855470000, 0.7060894000, 1.0274767000", \ - "0.7219137000, 0.7276318000, 0.7420104000, 0.7738717000, 0.8369313000, 0.9664460000, 1.2909560000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1430799000, 0.1488374000, 0.1637321000, 0.1983809000, 0.2799113000, 0.5060163000, 1.2133828000", \ - "0.1466550000, 0.1523993000, 0.1673253000, 0.2019363000, 0.2835891000, 0.5092397000, 1.2176424000", \ - "0.1555708000, 0.1613320000, 0.1762867000, 0.2108645000, 0.2924821000, 0.5182105000, 1.2265018000", \ - "0.1778492000, 0.1835589000, 0.1984953000, 0.2331538000, 0.3147882000, 0.5402582000, 1.2513456000", \ - "0.2271172000, 0.2328971000, 0.2478252000, 0.2825618000, 0.3641053000, 0.5896944000, 1.2983088000", \ - "0.2994378000, 0.3058670000, 0.3221790000, 0.3586358000, 0.4419220000, 0.6690458000, 1.3785415000", \ - "0.3729763000, 0.3808916000, 0.4011399000, 0.4445302000, 0.5321041000, 0.7600154000, 1.4687367000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0323322000, 0.0347718000, 0.0426408000, 0.0597220000, 0.1041847000, 0.2293872000, 0.6398706000", \ - "0.0323309000, 0.0347720000, 0.0422523000, 0.0600065000, 0.1043010000, 0.2297711000, 0.6386693000", \ - "0.0321213000, 0.0348636000, 0.0421920000, 0.0603689000, 0.1043139000, 0.2293669000, 0.6388038000", \ - "0.0321028000, 0.0348794000, 0.0422345000, 0.0601940000, 0.1036255000, 0.2298274000, 0.6405084000", \ - "0.0321643000, 0.0350863000, 0.0424237000, 0.0604573000, 0.1041656000, 0.2296639000, 0.6396775000", \ - "0.0355747000, 0.0384926000, 0.0459177000, 0.0632207000, 0.1070741000, 0.2302070000, 0.6402187000", \ - "0.0466174000, 0.0493651000, 0.0576041000, 0.0765896000, 0.1216372000, 0.2436988000, 0.6450389000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0341971000, 0.0381731000, 0.0489996000, 0.0798409000, 0.1724192000, 0.4821035000, 1.4970271000", \ - "0.0343232000, 0.0381949000, 0.0492962000, 0.0799025000, 0.1723925000, 0.4818635000, 1.4998266000", \ - "0.0342000000, 0.0381081000, 0.0491956000, 0.0798715000, 0.1724526000, 0.4819005000, 1.4989029000", \ - "0.0342606000, 0.0379323000, 0.0489689000, 0.0797043000, 0.1719123000, 0.4815594000, 1.5011744000", \ - "0.0350193000, 0.0388211000, 0.0495338000, 0.0802542000, 0.1726920000, 0.4817421000, 1.5006497000", \ - "0.0426890000, 0.0460593000, 0.0562114000, 0.0854368000, 0.1762620000, 0.4831949000, 1.4995554000", \ - "0.0567031000, 0.0609340000, 0.0725126000, 0.1008409000, 0.1834747000, 0.4858817000, 1.4938366000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2643898000, 0.2691908000, 0.2814375000, 0.3082238000, 0.3623996000, 0.4826037000, 0.8043524000", \ - "0.2694225000, 0.2742227000, 0.2864641000, 0.3131558000, 0.3677345000, 0.4878720000, 0.8098181000", \ - "0.2815997000, 0.2864161000, 0.2987301000, 0.3253757000, 0.3802378000, 0.4998688000, 0.8215947000", \ - "0.3101980000, 0.3150295000, 0.3272696000, 0.3539822000, 0.4086583000, 0.5284272000, 0.8501921000", \ - "0.3702127000, 0.3749081000, 0.3871447000, 0.4138957000, 0.4685329000, 0.5885578000, 0.9104654000", \ - "0.4966444000, 0.5016977000, 0.5145908000, 0.5422808000, 0.5970947000, 0.7184672000, 1.0403780000", \ - "0.7199218000, 0.7258730000, 0.7408728000, 0.7728229000, 0.8351794000, 0.9642122000, 1.2902543000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1538872000, 0.1595954000, 0.1745014000, 0.2091492000, 0.2906290000, 0.5157426000, 1.2260749000", \ - "0.1578754000, 0.1636371000, 0.1785452000, 0.2131689000, 0.2946896000, 0.5200665000, 1.2286653000", \ - "0.1669053000, 0.1726407000, 0.1875931000, 0.2221984000, 0.3036428000, 0.5294954000, 1.2372778000", \ - "0.1874194000, 0.1931540000, 0.2080497000, 0.2426399000, 0.3240941000, 0.5498445000, 1.2578590000", \ - "0.2321897000, 0.2379923000, 0.2529904000, 0.2877840000, 0.3693243000, 0.5953603000, 1.3032939000", \ - "0.3040567000, 0.3105145000, 0.3270377000, 0.3638126000, 0.4475706000, 0.6744850000, 1.3835353000", \ - "0.3853828000, 0.3931788000, 0.4130881000, 0.4561596000, 0.5448453000, 0.7731076000, 1.4808901000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0343128000, 0.0371845000, 0.0447289000, 0.0619814000, 0.1056352000, 0.2301390000, 0.6409913000", \ - "0.0343036000, 0.0371861000, 0.0439876000, 0.0617079000, 0.1042750000, 0.2304438000, 0.6389216000", \ - "0.0342102000, 0.0370025000, 0.0445649000, 0.0612175000, 0.1051965000, 0.2300632000, 0.6404460000", \ - "0.0343341000, 0.0371531000, 0.0443795000, 0.0612429000, 0.1051863000, 0.2301268000, 0.6407875000", \ - "0.0342630000, 0.0374855000, 0.0441806000, 0.0615644000, 0.1055195000, 0.2301601000, 0.6399409000", \ - "0.0373561000, 0.0403627000, 0.0473919000, 0.0640855000, 0.1076332000, 0.2311983000, 0.6409986000", \ - "0.0471229000, 0.0503705000, 0.0584895000, 0.0765587000, 0.1204550000, 0.2425490000, 0.6440075000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0341657000, 0.0378577000, 0.0492545000, 0.0798146000, 0.1721292000, 0.4817140000, 1.5013508000", \ - "0.0340808000, 0.0381068000, 0.0491088000, 0.0797889000, 0.1724035000, 0.4811034000, 1.4997610000", \ - "0.0342335000, 0.0381648000, 0.0491854000, 0.0799000000, 0.1723064000, 0.4819026000, 1.4985477000", \ - "0.0341093000, 0.0381019000, 0.0492214000, 0.0798392000, 0.1724571000, 0.4818116000, 1.4997278000", \ - "0.0351337000, 0.0389628000, 0.0499733000, 0.0801321000, 0.1726785000, 0.4811606000, 1.4984950000", \ - "0.0407356000, 0.0446320000, 0.0556196000, 0.0853132000, 0.1757977000, 0.4827691000, 1.4998457000", \ - "0.0536338000, 0.0582029000, 0.0696358000, 0.0984033000, 0.1840911000, 0.4856254000, 1.4933028000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2759154000, 0.2808505000, 0.2933095000, 0.3202566000, 0.3752439000, 0.4951263000, 0.8178240000", \ - "0.2810306000, 0.2859393000, 0.2984021000, 0.3255012000, 0.3803582000, 0.5004517000, 0.8224548000", \ - "0.2939344000, 0.2988399000, 0.3113105000, 0.3383808000, 0.3928452000, 0.5131651000, 0.8355441000", \ - "0.3227266000, 0.3276244000, 0.3401843000, 0.3671034000, 0.4219501000, 0.5420564000, 0.8647754000", \ - "0.3816092000, 0.3865656000, 0.3990432000, 0.4259955000, 0.4806829000, 0.6012326000, 0.9236280000", \ - "0.5045989000, 0.5096064000, 0.5226957000, 0.5502771000, 0.6056314000, 0.7264793000, 1.0491783000", \ - "0.7246420000, 0.7303842000, 0.7454022000, 0.7770402000, 0.8387691000, 0.9669172000, 1.2928650000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1581201000, 0.1638444000, 0.1787613000, 0.2133777000, 0.2948544000, 0.5198452000, 1.2276802000", \ - "0.1619187000, 0.1676411000, 0.1825799000, 0.2172446000, 0.2987025000, 0.5235446000, 1.2334083000", \ - "0.1692836000, 0.1750500000, 0.1899610000, 0.2246173000, 0.3060277000, 0.5315409000, 1.2390131000", \ - "0.1840420000, 0.1897918000, 0.2047301000, 0.2393195000, 0.3207085000, 0.5462919000, 1.2535850000", \ - "0.2143597000, 0.2202101000, 0.2353865000, 0.2701561000, 0.3518360000, 0.5772876000, 1.2851795000", \ - "0.2642422000, 0.2705509000, 0.2867526000, 0.3235054000, 0.4073127000, 0.6340066000, 1.3423861000", \ - "0.3229904000, 0.3303442000, 0.3492312000, 0.3906589000, 0.4788823000, 0.7076381000, 1.4147957000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0356227000, 0.0384083000, 0.0462411000, 0.0623723000, 0.1061212000, 0.2312433000, 0.6423874000", \ - "0.0356204000, 0.0384640000, 0.0452858000, 0.0631626000, 0.1064278000, 0.2309664000, 0.6430431000", \ - "0.0357441000, 0.0387079000, 0.0453934000, 0.0624631000, 0.1065464000, 0.2312919000, 0.6422138000", \ - "0.0356015000, 0.0386347000, 0.0460684000, 0.0623591000, 0.1062078000, 0.2311442000, 0.6424422000", \ - "0.0355463000, 0.0383452000, 0.0458940000, 0.0623312000, 0.1063414000, 0.2311426000, 0.6429577000", \ - "0.0381116000, 0.0413987000, 0.0479860000, 0.0648253000, 0.1078615000, 0.2318818000, 0.6435458000", \ - "0.0469908000, 0.0506152000, 0.0583839000, 0.0762027000, 0.1196985000, 0.2418897000, 0.6457597000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0341320000, 0.0382984000, 0.0490482000, 0.0797596000, 0.1723459000, 0.4811385000, 1.4979705000", \ - "0.0343032000, 0.0380307000, 0.0490383000, 0.0798030000, 0.1723596000, 0.4817029000, 1.5014824000", \ - "0.0341055000, 0.0381672000, 0.0490682000, 0.0799159000, 0.1724084000, 0.4819113000, 1.4986073000", \ - "0.0342832000, 0.0381032000, 0.0491219000, 0.0798926000, 0.1724256000, 0.4819449000, 1.4981253000", \ - "0.0353769000, 0.0388659000, 0.0497296000, 0.0804273000, 0.1724447000, 0.4819224000, 1.5002024000", \ - "0.0389614000, 0.0427584000, 0.0542844000, 0.0847151000, 0.1757666000, 0.4820616000, 1.4993450000", \ - "0.0489755000, 0.0531112000, 0.0646945000, 0.0953690000, 0.1827642000, 0.4849585000, 1.4973804000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2218537000, 0.2266124000, 0.2388036000, 0.2654438000, 0.3201834000, 0.4402634000, 0.7627749000", \ - "0.2261330000, 0.2308938000, 0.2430931000, 0.2697410000, 0.3244753000, 0.4444941000, 0.7668950000", \ - "0.2364402000, 0.2411782000, 0.2529904000, 0.2796088000, 0.3338793000, 0.4543163000, 0.7765164000", \ - "0.2629673000, 0.2677205000, 0.2799118000, 0.3065389000, 0.3610904000, 0.4814359000, 0.8038041000", \ - "0.3295710000, 0.3342906000, 0.3463728000, 0.3730869000, 0.4277208000, 0.5481473000, 0.8705446000", \ - "0.4849878000, 0.4901369000, 0.5031560000, 0.5306400000, 0.5857735000, 0.7065230000, 1.0289363000", \ - "0.7454241000, 0.7519714000, 0.7689583000, 0.8040995000, 0.8682788000, 0.9950858000, 1.3223154000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0898754000, 0.0951194000, 0.1088585000, 0.1408565000, 0.2179114000, 0.4411974000, 1.1510239000", \ - "0.0942457000, 0.0994882000, 0.1132041000, 0.1451952000, 0.2222584000, 0.4456169000, 1.1522436000", \ - "0.1045682000, 0.1098164000, 0.1235591000, 0.1554858000, 0.2325546000, 0.4554602000, 1.1645449000", \ - "0.1280423000, 0.1332705000, 0.1469295000, 0.1786361000, 0.2557436000, 0.4792557000, 1.1842717000", \ - "0.1664695000, 0.1723183000, 0.1870561000, 0.2202328000, 0.2982614000, 0.5218901000, 1.2324310000", \ - "0.2115545000, 0.2190898000, 0.2375621000, 0.2750134000, 0.3560418000, 0.5805034000, 1.2912605000", \ - "0.2428068000, 0.2523992000, 0.2762938000, 0.3241185000, 0.4140256000, 0.6393264000, 1.3460904000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0344588000, 0.0372409000, 0.0444427000, 0.0613961000, 0.1053996000, 0.2305710000, 0.6411706000", \ - "0.0342966000, 0.0370466000, 0.0447007000, 0.0616273000, 0.1056650000, 0.2305510000, 0.6408770000", \ - "0.0344490000, 0.0373135000, 0.0444956000, 0.0622205000, 0.1060036000, 0.2304156000, 0.6420589000", \ - "0.0342539000, 0.0370341000, 0.0443671000, 0.0616676000, 0.1057710000, 0.2305137000, 0.6413757000", \ - "0.0346889000, 0.0374502000, 0.0448697000, 0.0624320000, 0.1057409000, 0.2311226000, 0.6415356000", \ - "0.0394243000, 0.0422671000, 0.0499031000, 0.0652788000, 0.1074845000, 0.2313920000, 0.6420229000", \ - "0.0586342000, 0.0622275000, 0.0700463000, 0.0872188000, 0.1256647000, 0.2434379000, 0.6470253000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0279339000, 0.0319919000, 0.0427107000, 0.0715719000, 0.1638420000, 0.4769756000, 1.4977037000", \ - "0.0279667000, 0.0318963000, 0.0424901000, 0.0715665000, 0.1638064000, 0.4762085000, 1.4930942000", \ - "0.0278589000, 0.0318126000, 0.0426424000, 0.0717922000, 0.1640733000, 0.4755537000, 1.4988193000", \ - "0.0281585000, 0.0321818000, 0.0428385000, 0.0719886000, 0.1641648000, 0.4761013000, 1.4975745000", \ - "0.0337627000, 0.0376067000, 0.0479663000, 0.0753742000, 0.1657603000, 0.4760543000, 1.4962469000", \ - "0.0473925000, 0.0512380000, 0.0607856000, 0.0854015000, 0.1707236000, 0.4780676000, 1.4945316000", \ - "0.0678609000, 0.0724745000, 0.0844264000, 0.1085634000, 0.1840091000, 0.4801596000, 1.4896590000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2365798000, 0.2415000000, 0.2540553000, 0.2809845000, 0.3360194000, 0.4566215000, 0.7791627000", \ - "0.2403787000, 0.2452901000, 0.2577697000, 0.2848572000, 0.3393468000, 0.4599661000, 0.7824662000", \ - "0.2509123000, 0.2558509000, 0.2683517000, 0.2953403000, 0.3504048000, 0.4708046000, 0.7936601000", \ - "0.2782403000, 0.2831815000, 0.2956977000, 0.3226238000, 0.3775488000, 0.4979285000, 0.8211837000", \ - "0.3437761000, 0.3486935000, 0.3611772000, 0.3882687000, 0.4429034000, 0.5639100000, 0.8863565000", \ - "0.4963432000, 0.5017700000, 0.5147052000, 0.5423955000, 0.5974141000, 0.7186124000, 1.0416122000", \ - "0.7537443000, 0.7605337000, 0.7776396000, 0.8128169000, 0.8759141000, 1.0020723000, 1.3285030000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0957302000, 0.1009796000, 0.1147306000, 0.1467346000, 0.2237388000, 0.4468995000, 1.1549355000", \ - "0.1004188000, 0.1056641000, 0.1194187000, 0.1514073000, 0.2285283000, 0.4518373000, 1.1573265000", \ - "0.1098388000, 0.1151086000, 0.1288851000, 0.1607783000, 0.2379867000, 0.4612408000, 1.1664533000", \ - "0.1298354000, 0.1350640000, 0.1487381000, 0.1806019000, 0.2577045000, 0.4811979000, 1.1856518000", \ - "0.1650038000, 0.1706827000, 0.1852445000, 0.2182133000, 0.2961244000, 0.5190788000, 1.2310265000", \ - "0.2107620000, 0.2176963000, 0.2349537000, 0.2715684000, 0.3524109000, 0.5762777000, 1.2863000000", \ - "0.2478312000, 0.2568249000, 0.2793485000, 0.3247997000, 0.4133104000, 0.6392684000, 1.3451318000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0357644000, 0.0386644000, 0.0461774000, 0.0624079000, 0.1060586000, 0.2308585000, 0.6426437000", \ - "0.0357499000, 0.0386741000, 0.0453791000, 0.0632610000, 0.1067183000, 0.2311186000, 0.6426344000", \ - "0.0357526000, 0.0385879000, 0.0458842000, 0.0623599000, 0.1060147000, 0.2310135000, 0.6421095000", \ - "0.0357294000, 0.0383714000, 0.0453791000, 0.0627917000, 0.1063421000, 0.2310926000, 0.6422176000", \ - "0.0357727000, 0.0387133000, 0.0452790000, 0.0628846000, 0.1064720000, 0.2305456000, 0.6432848000", \ - "0.0397560000, 0.0424652000, 0.0493480000, 0.0650028000, 0.1077454000, 0.2320846000, 0.6421599000", \ - "0.0584725000, 0.0616108000, 0.0699732000, 0.0863652000, 0.1234758000, 0.2414813000, 0.6470851000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0279260000, 0.0319952000, 0.0426704000, 0.0715666000, 0.1639796000, 0.4772453000, 1.4989895000", \ - "0.0279965000, 0.0319768000, 0.0426993000, 0.0716012000, 0.1639619000, 0.4762466000, 1.4972055000", \ - "0.0279001000, 0.0319305000, 0.0424887000, 0.0716576000, 0.1640528000, 0.4762471000, 1.4960497000", \ - "0.0281581000, 0.0321059000, 0.0429211000, 0.0717690000, 0.1640993000, 0.4759375000, 1.4976670000", \ - "0.0318366000, 0.0356293000, 0.0465338000, 0.0743421000, 0.1650793000, 0.4768403000, 1.4978638000", \ - "0.0415961000, 0.0457220000, 0.0560170000, 0.0826538000, 0.1699200000, 0.4772506000, 1.4949740000", \ - "0.0594015000, 0.0648303000, 0.0766495000, 0.1015189000, 0.1810019000, 0.4805714000, 1.4909654000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32oi_1") { - leakage_power () { - value : 0.0004824000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 5.6089539e-05; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0002863000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0005045000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 7.8171444e-05; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0003084000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0004950000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 6.8659217e-05; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0002989000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0009569000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0005306000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0007609000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0004995000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 7.3193005e-05; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0003034000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0008298000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0004035000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0006337000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0007217000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0002954000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0032770000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0005256000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0024445000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0025784000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0002760000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0025465000; - when : "A1&A2&A3&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a32oi"; - cell_leakage_power : 0.0012467940; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044649000, 0.0044674000, 0.0044731000, 0.0044720000, 0.0044695000, 0.0044638000, 0.0044506000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003630500, -0.003633700, -0.003640900, -0.003635000, -0.003621300, -0.003589600, -0.003516600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023700000; - } - pin ("A2") { - capacitance : 0.0023550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043291000, 0.0043253000, 0.0043165000, 0.0043327000, 0.0043700000, 0.0044559000, 0.0046540000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003858700, -0.003856000, -0.003849800, -0.003851000, -0.003853700, -0.003860000, -0.003874400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024410000; - } - pin ("A3") { - capacitance : 0.0023110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040213000, 0.0040239000, 0.0040299000, 0.0040307000, 0.0040325000, 0.0040366000, 0.0040461000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004017700, -0.004020100, -0.004025700, -0.004025200, -0.004023900, -0.004020900, -0.004014100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024210000; - } - pin ("B1") { - capacitance : 0.0023410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047500000, 0.0047481000, 0.0047437000, 0.0047452000, 0.0047485000, 0.0047561000, 0.0047737000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003886600, -0.003889800, -0.003897000, -0.003891100, -0.003877500, -0.003846100, -0.003773700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024620000; - } - pin ("B2") { - capacitance : 0.0023080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041800000, 0.0041776000, 0.0041720000, 0.0041720000, 0.0041719000, 0.0041717000, 0.0041711000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004176300, -0.004177700, -0.004180900, -0.004180800, -0.004180500, -0.004179900, -0.004178500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024670000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A3&!B1) | (!A2&!B2) | (!A3&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0070880000, 0.0059930000, 0.0034746000, -0.002550700, -0.016738600, -0.050302400, -0.129506700", \ - "0.0070180000, 0.0059531000, 0.0033735000, -0.002585200, -0.016792800, -0.050374700, -0.129545500", \ - "0.0068599000, 0.0057929000, 0.0032747000, -0.002705700, -0.016890600, -0.050439300, -0.129648100", \ - "0.0066278000, 0.0055970000, 0.0030564000, -0.002908100, -0.017010100, -0.050511500, -0.129697400", \ - "0.0064471000, 0.0054476000, 0.0029242000, -0.003012300, -0.017155700, -0.050629000, -0.129768500", \ - "0.0067706000, 0.0056611000, 0.0030596000, -0.002944700, -0.017292700, -0.050708200, -0.129779900", \ - "0.0078657000, 0.0068577000, 0.0042363000, -0.001821100, -0.016539100, -0.050134000, -0.129624100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0112796000, 0.0124123000, 0.0150260000, 0.0211159000, 0.0353513000, 0.0686303000, 0.1468920000", \ - "0.0111050000, 0.0122477000, 0.0149107000, 0.0210605000, 0.0353069000, 0.0686621000, 0.1469369000", \ - "0.0108171000, 0.0119671000, 0.0146310000, 0.0208280000, 0.0351488000, 0.0685618000, 0.1469323000", \ - "0.0105636000, 0.0117006000, 0.0143432000, 0.0205233000, 0.0349180000, 0.0683965000, 0.1468276000", \ - "0.0104400000, 0.0115410000, 0.0141425000, 0.0202694000, 0.0345541000, 0.0681162000, 0.1466430000", \ - "0.0103771000, 0.0115107000, 0.0140928000, 0.0201384000, 0.0344576000, 0.0679151000, 0.1463625000", \ - "0.0103100000, 0.0113784000, 0.0139134000, 0.0201622000, 0.0345180000, 0.0679131000, 0.1463066000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0072907000, 0.0062132000, 0.0036782000, -0.002329200, -0.016544500, -0.050098300, -0.129308900", \ - "0.0072206000, 0.0061415000, 0.0036056000, -0.002389000, -0.016604000, -0.050179900, -0.129383700", \ - "0.0070874000, 0.0060106000, 0.0034799000, -0.002495600, -0.016688500, -0.050230500, -0.129385000", \ - "0.0069184000, 0.0058561000, 0.0033197000, -0.002630900, -0.016772700, -0.050302500, -0.129510400", \ - "0.0066875000, 0.0056111000, 0.0031740000, -0.002802300, -0.016923100, -0.050385400, -0.129524300", \ - "0.0069205000, 0.0058324000, 0.0032477000, -0.002802800, -0.017046000, -0.050480100, -0.129562300", \ - "0.0076772000, 0.0065609000, 0.0039659000, -0.002209900, -0.016627000, -0.050426000, -0.129529400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0140120000, 0.0151132000, 0.0176939000, 0.0237395000, 0.0379451000, 0.0712378000, 0.1495786000", \ - "0.0138747000, 0.0149946000, 0.0175880000, 0.0236773000, 0.0379013000, 0.0712047000, 0.1495501000", \ - "0.0136681000, 0.0147828000, 0.0174067000, 0.0235379000, 0.0378221000, 0.0712261000, 0.1495111000", \ - "0.0134400000, 0.0145590000, 0.0171785000, 0.0233183000, 0.0376275000, 0.0709953000, 0.1495273000", \ - "0.0132561000, 0.0143596000, 0.0169639000, 0.0230672000, 0.0373371000, 0.0708060000, 0.1492935000", \ - "0.0131321000, 0.0142277000, 0.0168491000, 0.0229060000, 0.0372320000, 0.0705671000, 0.1490605000", \ - "0.0128252000, 0.0138934000, 0.0164181000, 0.0226865000, 0.0370206000, 0.0705992000, 0.1490688000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0071722000, 0.0061113000, 0.0035525000, -0.002449700, -0.016658800, -0.050216500, -0.129378500", \ - "0.0071064000, 0.0060199000, 0.0034777000, -0.002508300, -0.016726500, -0.050273100, -0.129522300", \ - "0.0069695000, 0.0058918000, 0.0033721000, -0.002609400, -0.016797400, -0.050339300, -0.129580800", \ - "0.0067848000, 0.0057124000, 0.0031957000, -0.002771200, -0.016908500, -0.050417100, -0.129622600", \ - "0.0066280000, 0.0056136000, 0.0030698000, -0.002826100, -0.016971200, -0.050516500, -0.129669400", \ - "0.0068165000, 0.0057147000, 0.0031475000, -0.002924000, -0.017186700, -0.050564100, -0.129691300", \ - "0.0075372000, 0.0064154000, 0.0038047000, -0.002327700, -0.016741300, -0.050575700, -0.129650600"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0169872000, 0.0180863000, 0.0206513000, 0.0267406000, 0.0409808000, 0.0742948000, 0.1526179000", \ - "0.0168903000, 0.0179819000, 0.0205621000, 0.0266454000, 0.0408801000, 0.0742732000, 0.1525595000", \ - "0.0167631000, 0.0178590000, 0.0204458000, 0.0265800000, 0.0408166000, 0.0742132000, 0.1525632000", \ - "0.0166083000, 0.0177248000, 0.0203313000, 0.0264489000, 0.0407117000, 0.0741266000, 0.1526132000", \ - "0.0164944000, 0.0175986000, 0.0201945000, 0.0263233000, 0.0405620000, 0.0739923000, 0.1523549000", \ - "0.0164591000, 0.0175749000, 0.0202054000, 0.0263032000, 0.0406082000, 0.0739271000, 0.1522996000", \ - "0.0164901000, 0.0175543000, 0.0200691000, 0.0263166000, 0.0407122000, 0.0742099000, 0.1524348000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0024497000, 0.0014176000, -0.001092800, -0.007110900, -0.021392500, -0.055082500, -0.134437800", \ - "0.0023140000, 0.0013111000, -0.001140300, -0.007101500, -0.021342900, -0.055005300, -0.134341800", \ - "0.0021408000, 0.0011704000, -0.001264100, -0.007160500, -0.021322200, -0.054939500, -0.134250200", \ - "0.0019088000, 0.0008972000, -0.001489200, -0.007334100, -0.021423700, -0.054961300, -0.134227300", \ - "0.0020320000, 0.0009494000, -0.001612400, -0.007504800, -0.021562400, -0.055074400, -0.134279200", \ - "0.0023387000, 0.0012624000, -0.001347200, -0.007532100, -0.021824600, -0.055154200, -0.134323600", \ - "0.0036699000, 0.0024426000, -0.000364700, -0.006663300, -0.021047200, -0.054939100, -0.134388900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0108551000, 0.0120220000, 0.0146761000, 0.0208098000, 0.0350712000, 0.0684311000, 0.1468822000", \ - "0.0106418000, 0.0118055000, 0.0144861000, 0.0206473000, 0.0349990000, 0.0684298000, 0.1467249000", \ - "0.0103700000, 0.0115138000, 0.0141780000, 0.0203909000, 0.0347932000, 0.0683063000, 0.1466975000", \ - "0.0101240000, 0.0112656000, 0.0139255000, 0.0200887000, 0.0345097000, 0.0681618000, 0.1466064000", \ - "0.0100304000, 0.0111328000, 0.0137230000, 0.0198291000, 0.0341825000, 0.0677730000, 0.1464172000", \ - "0.0106882000, 0.0117896000, 0.0144939000, 0.0199970000, 0.0341479000, 0.0675654000, 0.1460785000", \ - "0.0119300000, 0.0129432000, 0.0153330000, 0.0210937000, 0.0352259000, 0.0681461000, 0.1459120000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0028424000, 0.0017939000, -0.000727700, -0.006762300, -0.021048200, -0.054736900, -0.134088200", \ - "0.0027060000, 0.0016956000, -0.000772100, -0.006747300, -0.020992300, -0.054655900, -0.133998600", \ - "0.0024762000, 0.0014877000, -0.000918600, -0.006806200, -0.020977500, -0.054596000, -0.133910800", \ - "0.0022042000, 0.0012049000, -0.001196900, -0.007018000, -0.021075200, -0.054617200, -0.133885400", \ - "0.0021571000, 0.0011621000, -0.001376400, -0.007287600, -0.021326000, -0.054747600, -0.133934200", \ - "0.0023559000, 0.0012558000, -0.001289400, -0.007316900, -0.021552100, -0.054949100, -0.134052400", \ - "0.0035753000, 0.0023829000, -0.000373800, -0.006674500, -0.021130600, -0.054888300, -0.134116300"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011771790, 0.0027715010, 0.0065251060, 0.0153624400, 0.0361686800, 0.0851540200"); - values("0.0139333000, 0.0150149000, 0.0176283000, 0.0237177000, 0.0379754000, 0.0713727000, 0.1497693000", \ - "0.0137598000, 0.0148534000, 0.0175221000, 0.0236256000, 0.0379310000, 0.0713022000, 0.1496279000", \ - "0.0135285000, 0.0146252000, 0.0172660000, 0.0234415000, 0.0378059000, 0.0712564000, 0.1496835000", \ - "0.0133469000, 0.0144583000, 0.0170981000, 0.0232505000, 0.0375740000, 0.0710894000, 0.1495009000", \ - "0.0134460000, 0.0146356000, 0.0172138000, 0.0232890000, 0.0374318000, 0.0708428000, 0.1494692000", \ - "0.0143175000, 0.0153942000, 0.0179661000, 0.0234146000, 0.0375477000, 0.0709303000, 0.1492000000", \ - "0.0154414000, 0.0164876000, 0.0189355000, 0.0247410000, 0.0387269000, 0.0718045000, 0.1497035000"); - } - } - max_capacitance : 0.0851540000; - max_transition : 1.8643180000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0511088000, 0.0560668000, 0.0680286000, 0.0941493000, 0.1539693000, 0.2917982000, 0.6132582000", \ - "0.0548102000, 0.0601134000, 0.0715213000, 0.0980450000, 0.1577455000, 0.2956752000, 0.6171811000", \ - "0.0640186000, 0.0693130000, 0.0810491000, 0.1073634000, 0.1672704000, 0.3051179000, 0.6262111000", \ - "0.0857066000, 0.0911897000, 0.1032045000, 0.1288129000, 0.1892867000, 0.3271076000, 0.6484662000", \ - "0.1172556000, 0.1249297000, 0.1416353000, 0.1762556000, 0.2414068000, 0.3786840000, 0.6999041000", \ - "0.1483521000, 0.1602233000, 0.1863023000, 0.2364147000, 0.3326426000, 0.4952442000, 0.8169068000", \ - "0.1560484000, 0.1743834000, 0.2115010000, 0.2899488000, 0.4324558000, 0.6798254000, 1.0915600000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.1119629000, 0.1228477000, 0.1482734000, 0.2064965000, 0.3417004000, 0.6588167000, 1.4035093000", \ - "0.1167343000, 0.1276784000, 0.1532657000, 0.2119151000, 0.3475535000, 0.6644317000, 1.4091310000", \ - "0.1286330000, 0.1397767000, 0.1655958000, 0.2248315000, 0.3612469000, 0.6784973000, 1.4236358000", \ - "0.1580580000, 0.1695390000, 0.1949384000, 0.2539244000, 0.3906966000, 0.7091074000, 1.4547807000", \ - "0.2212732000, 0.2331271000, 0.2589861000, 0.3178356000, 0.4543161000, 0.7730477000, 1.5198820000", \ - "0.3283531000, 0.3449509000, 0.3804065000, 0.4527939000, 0.5977767000, 0.9161547000, 1.6633616000", \ - "0.5023644000, 0.5285997000, 0.5837517000, 0.6897931000, 0.8853805000, 1.2475366000, 1.9953781000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0469052000, 0.0527966000, 0.0669223000, 0.0999744000, 0.1776656000, 0.3611400000, 0.7930496000", \ - "0.0468158000, 0.0527972000, 0.0668390000, 0.0999722000, 0.1777751000, 0.3613347000, 0.7928012000", \ - "0.0459095000, 0.0520047000, 0.0664084000, 0.0997389000, 0.1778152000, 0.3615717000, 0.7935305000", \ - "0.0533545000, 0.0588909000, 0.0710100000, 0.1012870000, 0.1774876000, 0.3609721000, 0.7928646000", \ - "0.0757850000, 0.0831380000, 0.0978568000, 0.1282045000, 0.1922747000, 0.3621336000, 0.7927349000", \ - "0.1193226000, 0.1296194000, 0.1502882000, 0.1932241000, 0.2663409000, 0.4131489000, 0.8002961000", \ - "0.1938409000, 0.2103952000, 0.2426851000, 0.3055202000, 0.4125099000, 0.5936494000, 0.9311588000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0754931000, 0.0898828000, 0.1237717000, 0.2034053000, 0.3877272000, 0.8227298000, 1.8516065000", \ - "0.0756235000, 0.0898825000, 0.1237774000, 0.2027360000, 0.3879831000, 0.8231451000, 1.8496747000", \ - "0.0756203000, 0.0898380000, 0.1237671000, 0.2029281000, 0.3893344000, 0.8225992000, 1.8458413000", \ - "0.0758439000, 0.0900281000, 0.1238085000, 0.2033328000, 0.3879816000, 0.8227875000, 1.8509192000", \ - "0.0859659000, 0.0983472000, 0.1295816000, 0.2046191000, 0.3882790000, 0.8243135000, 1.8462524000", \ - "0.1247025000, 0.1391457000, 0.1703908000, 0.2391023000, 0.4036497000, 0.8230220000, 1.8457639000", \ - "0.2101724000, 0.2277145000, 0.2668694000, 0.3464435000, 0.5096804000, 0.8802175000, 1.8490272000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0575795000, 0.0629352000, 0.0746826000, 0.1012714000, 0.1607829000, 0.2986360000, 0.6199075000", \ - "0.0619014000, 0.0669503000, 0.0789166000, 0.1054016000, 0.1650041000, 0.3026713000, 0.6239488000", \ - "0.0706285000, 0.0758721000, 0.0877532000, 0.1142354000, 0.1739814000, 0.3117139000, 0.6329827000", \ - "0.0909019000, 0.0960380000, 0.1085711000, 0.1351785000, 0.1954047000, 0.3331276000, 0.6545825000", \ - "0.1232099000, 0.1302476000, 0.1464554000, 0.1785817000, 0.2429534000, 0.3825369000, 0.7046190000", \ - "0.1602224000, 0.1713501000, 0.1941865000, 0.2415753000, 0.3294374000, 0.4902452000, 0.8187019000", \ - "0.1789601000, 0.1956280000, 0.2327324000, 0.3057165000, 0.4392025000, 0.6703996000, 1.0664778000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.1301475000, 0.1410904000, 0.1657925000, 0.2238061000, 0.3584820000, 0.6744657000, 1.4167585000", \ - "0.1348817000, 0.1461544000, 0.1713430000, 0.2293668000, 0.3643090000, 0.6803669000, 1.4227202000", \ - "0.1475971000, 0.1588861000, 0.1838118000, 0.2422798000, 0.3774840000, 0.6945930000, 1.4365258000", \ - "0.1775895000, 0.1885095000, 0.2136924000, 0.2722456000, 0.4079896000, 0.7253688000, 1.4690832000", \ - "0.2413929000, 0.2522230000, 0.2771630000, 0.3359851000, 0.4715195000, 0.7886535000, 1.5319529000", \ - "0.3562546000, 0.3700662000, 0.4038064000, 0.4721383000, 0.6139666000, 0.9309306000, 1.6755782000", \ - "0.5439519000, 0.5672454000, 0.6161865000, 0.7150406000, 0.9040992000, 1.2586180000, 2.0039088000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0467108000, 0.0527524000, 0.0668982000, 0.1000861000, 0.1774873000, 0.3611003000, 0.7931964000", \ - "0.0467789000, 0.0527893000, 0.0667728000, 0.0998185000, 0.1777355000, 0.3614763000, 0.7925384000", \ - "0.0462612000, 0.0523349000, 0.0666365000, 0.0998871000, 0.1776854000, 0.3611191000, 0.7919696000", \ - "0.0511022000, 0.0566024000, 0.0693282000, 0.1008251000, 0.1773290000, 0.3606792000, 0.7931567000", \ - "0.0700475000, 0.0761364000, 0.0907341000, 0.1198348000, 0.1868401000, 0.3621528000, 0.7930119000", \ - "0.1096913000, 0.1184228000, 0.1356313000, 0.1718714000, 0.2430792000, 0.3952792000, 0.7958416000", \ - "0.1810380000, 0.1930170000, 0.2198233000, 0.2692441000, 0.3639613000, 0.5344117000, 0.8905610000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0914822000, 0.1060191000, 0.1396437000, 0.2187056000, 0.4046105000, 0.8409087000, 1.8643180000", \ - "0.0915564000, 0.1057699000, 0.1396130000, 0.2188089000, 0.4034432000, 0.8407565000, 1.8606127000", \ - "0.0915162000, 0.1060409000, 0.1396158000, 0.2187123000, 0.4037201000, 0.8389063000, 1.8636352000", \ - "0.0916312000, 0.1059729000, 0.1398880000, 0.2192406000, 0.4037272000, 0.8387793000, 1.8621100000", \ - "0.0985768000, 0.1118916000, 0.1441372000, 0.2199620000, 0.4038904000, 0.8395331000, 1.8620091000", \ - "0.1363353000, 0.1504838000, 0.1822794000, 0.2509740000, 0.4176557000, 0.8390027000, 1.8582088000", \ - "0.2227684000, 0.2396031000, 0.2771621000, 0.3560384000, 0.5231440000, 0.8931522000, 1.8621434000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0615531000, 0.0669741000, 0.0785406000, 0.1049936000, 0.1647164000, 0.3025682000, 0.6236934000", \ - "0.0660327000, 0.0711659000, 0.0830448000, 0.1095578000, 0.1689913000, 0.3068809000, 0.6280502000", \ - "0.0744547000, 0.0796880000, 0.0914902000, 0.1181002000, 0.1775869000, 0.3153952000, 0.6366819000", \ - "0.0919808000, 0.0973333000, 0.1093908000, 0.1357778000, 0.1957971000, 0.3336104000, 0.6550041000", \ - "0.1216372000, 0.1285146000, 0.1428962000, 0.1732277000, 0.2364936000, 0.3746973000, 0.6973384000", \ - "0.1610257000, 0.1699693000, 0.1899477000, 0.2317537000, 0.3110004000, 0.4670019000, 0.7920009000", \ - "0.1891058000, 0.2034862000, 0.2358977000, 0.2991592000, 0.4170695000, 0.6221729000, 1.0017198000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.1321123000, 0.1427532000, 0.1659860000, 0.2190499000, 0.3426470000, 0.6317777000, 1.3096986000", \ - "0.1376991000, 0.1481304000, 0.1709927000, 0.2247139000, 0.3485505000, 0.6374347000, 1.3163227000", \ - "0.1510702000, 0.1611406000, 0.1848371000, 0.2378247000, 0.3619645000, 0.6512252000, 1.3298682000", \ - "0.1802342000, 0.1899458000, 0.2135384000, 0.2672784000, 0.3915155000, 0.6809702000, 1.3592276000", \ - "0.2411343000, 0.2510772000, 0.2741883000, 0.3276227000, 0.4517753000, 0.7414813000, 1.4205122000", \ - "0.3487782000, 0.3608752000, 0.3916608000, 0.4548319000, 0.5858386000, 0.8757706000, 1.5560533000", \ - "0.5218314000, 0.5421490000, 0.5857614000, 0.6752564000, 0.8470540000, 1.1813692000, 1.8633834000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0467147000, 0.0527023000, 0.0668881000, 0.0999649000, 0.1777520000, 0.3611660000, 0.7919593000", \ - "0.0466963000, 0.0528071000, 0.0668091000, 0.0997844000, 0.1776842000, 0.3611553000, 0.7929174000", \ - "0.0464860000, 0.0525511000, 0.0667988000, 0.0999939000, 0.1777319000, 0.3610184000, 0.7932844000", \ - "0.0493697000, 0.0547930000, 0.0682728000, 0.1006503000, 0.1775064000, 0.3607716000, 0.7929321000", \ - "0.0633201000, 0.0696339000, 0.0827074000, 0.1135141000, 0.1840965000, 0.3620652000, 0.7927924000", \ - "0.0983994000, 0.1054286000, 0.1206955000, 0.1534680000, 0.2251244000, 0.3867609000, 0.7973535000", \ - "0.1662150000, 0.1764659000, 0.1981322000, 0.2419986000, 0.3257563000, 0.4926226000, 0.8667935000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0973976000, 0.1105964000, 0.1414252000, 0.2148168000, 0.3846026000, 0.7829248000, 1.7192335000", \ - "0.0973030000, 0.1104665000, 0.1414711000, 0.2141376000, 0.3857756000, 0.7825323000, 1.7230470000", \ - "0.0973107000, 0.1106475000, 0.1413222000, 0.2142083000, 0.3845941000, 0.7823779000, 1.7194957000", \ - "0.0972783000, 0.1105705000, 0.1418266000, 0.2147050000, 0.3855054000, 0.7848972000, 1.7221258000", \ - "0.1039711000, 0.1167402000, 0.1461415000, 0.2160018000, 0.3840398000, 0.7829543000, 1.7237243000", \ - "0.1409458000, 0.1538294000, 0.1837905000, 0.2485310000, 0.4016248000, 0.7847892000, 1.7254652000", \ - "0.2244915000, 0.2403312000, 0.2756079000, 0.3506311000, 0.5042927000, 0.8484539000, 1.7281241000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0228694000, 0.0264011000, 0.0346251000, 0.0533793000, 0.0972233000, 0.1998434000, 0.4412317000", \ - "0.0268721000, 0.0305576000, 0.0388707000, 0.0576656000, 0.1015302000, 0.2042820000, 0.4456988000", \ - "0.0356913000, 0.0402138000, 0.0488598000, 0.0680175000, 0.1117942000, 0.2146998000, 0.4561129000", \ - "0.0466622000, 0.0531261000, 0.0665959000, 0.0909702000, 0.1356001000, 0.2384758000, 0.4795114000", \ - "0.0546304000, 0.0649432000, 0.0855489000, 0.1229510000, 0.1861727000, 0.2938722000, 0.5348475000", \ - "0.0505047000, 0.0666455000, 0.0985403000, 0.1568277000, 0.2539096000, 0.4062613000, 0.6612903000", \ - "0.0062984000, 0.0309673000, 0.0798123000, 0.1693643000, 0.3190476000, 0.5568400000, 0.9255772000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0922065000, 0.1029739000, 0.1275415000, 0.1844726000, 0.3155811000, 0.6198095000, 1.3339465000", \ - "0.0954463000, 0.1064138000, 0.1316364000, 0.1882515000, 0.3195350000, 0.6244799000, 1.3392958000", \ - "0.1052723000, 0.1164270000, 0.1410882000, 0.1982789000, 0.3301706000, 0.6360274000, 1.3512449000", \ - "0.1332980000, 0.1439427000, 0.1683860000, 0.2245614000, 0.3564536000, 0.6629031000, 1.3788165000", \ - "0.2001767000, 0.2118778000, 0.2373083000, 0.2924206000, 0.4235030000, 0.7296320000, 1.4461679000", \ - "0.3123425000, 0.3309826000, 0.3680839000, 0.4440290000, 0.5826641000, 0.8846513000, 1.5995965000", \ - "0.4967919000, 0.5234281000, 0.5804764000, 0.6946184000, 0.9050002000, 1.2581735000, 1.9619693000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0242772000, 0.0287479000, 0.0393062000, 0.0641277000, 0.1227399000, 0.2595468000, 0.5825752000", \ - "0.0242643000, 0.0287449000, 0.0393171000, 0.0640273000, 0.1227828000, 0.2594640000, 0.5829789000", \ - "0.0290998000, 0.0325560000, 0.0412297000, 0.0643171000, 0.1223348000, 0.2591926000, 0.5822560000", \ - "0.0441977000, 0.0479225000, 0.0562695000, 0.0744994000, 0.1251420000, 0.2596376000, 0.5825241000", \ - "0.0724960000, 0.0777436000, 0.0886520000, 0.1115771000, 0.1544260000, 0.2688259000, 0.5828115000", \ - "0.1223339000, 0.1298938000, 0.1459782000, 0.1773734000, 0.2354790000, 0.3426367000, 0.6054769000", \ - "0.2116653000, 0.2219338000, 0.2456973000, 0.2927519000, 0.3796496000, 0.5272887000, 0.7779923000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0854996000, 0.0995556000, 0.1318614000, 0.2078311000, 0.3871942000, 0.8029595000, 1.7841146000", \ - "0.0855632000, 0.0995930000, 0.1317359000, 0.2077612000, 0.3865391000, 0.8029315000, 1.7845186000", \ - "0.0854150000, 0.0993786000, 0.1319702000, 0.2078817000, 0.3860252000, 0.8023837000, 1.7855131000", \ - "0.0850418000, 0.0987809000, 0.1311419000, 0.2079262000, 0.3857633000, 0.8034925000, 1.7913705000", \ - "0.1084229000, 0.1191299000, 0.1459010000, 0.2130084000, 0.3856960000, 0.8036991000, 1.7850069000", \ - "0.1618707000, 0.1787497000, 0.2102469000, 0.2742506000, 0.4155513000, 0.8053774000, 1.7860965000", \ - "0.2523236000, 0.2755074000, 0.3245079000, 0.4168967000, 0.5764292000, 0.8985317000, 1.7964658000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0275254000, 0.0310571000, 0.0392530000, 0.0578835000, 0.1016619000, 0.2043378000, 0.4455726000", \ - "0.0317464000, 0.0353669000, 0.0437670000, 0.0626689000, 0.1064556000, 0.2091910000, 0.4504828000", \ - "0.0406145000, 0.0446310000, 0.0531958000, 0.0723667000, 0.1164829000, 0.2193632000, 0.4606935000", \ - "0.0531617000, 0.0589973000, 0.0707898000, 0.0934883000, 0.1388292000, 0.2421301000, 0.4836775000", \ - "0.0673372000, 0.0766000000, 0.0946498000, 0.1277534000, 0.1852790000, 0.2937676000, 0.5357478000", \ - "0.0739781000, 0.0887040000, 0.1181039000, 0.1699149000, 0.2570303000, 0.3990156000, 0.6542855000", \ - "0.0504291000, 0.0743629000, 0.1208044000, 0.2034106000, 0.3410132000, 0.5566762000, 0.8946039000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.1032867000, 0.1142434000, 0.1369729000, 0.1909624000, 0.3144603000, 0.6037138000, 1.2822898000", \ - "0.1073882000, 0.1181256000, 0.1408356000, 0.1945903000, 0.3189504000, 0.6082829000, 1.2867273000", \ - "0.1182870000, 0.1277847000, 0.1510652000, 0.2050710000, 0.3296483000, 0.6196214000, 1.2982690000", \ - "0.1457016000, 0.1554421000, 0.1787460000, 0.2326689000, 0.3567947000, 0.6470057000, 1.3264634000", \ - "0.2118776000, 0.2207721000, 0.2451873000, 0.2979944000, 0.4203697000, 0.7102361000, 1.3891945000", \ - "0.3257420000, 0.3416531000, 0.3749170000, 0.4447534000, 0.5768349000, 0.8589693000, 1.5357339000", \ - "0.5050382000, 0.5285135000, 0.5801463000, 0.6856641000, 0.8818999000, 1.2209797000, 1.8929049000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0242740000, 0.0287670000, 0.0393179000, 0.0641329000, 0.1223116000, 0.2593960000, 0.5831867000", \ - "0.0243153000, 0.0287852000, 0.0393201000, 0.0641002000, 0.1222561000, 0.2591952000, 0.5824231000", \ - "0.0266979000, 0.0306050000, 0.0402489000, 0.0641379000, 0.1222844000, 0.2594300000, 0.5826686000", \ - "0.0378294000, 0.0413884000, 0.0497514000, 0.0699254000, 0.1237808000, 0.2594359000, 0.5823255000", \ - "0.0613799000, 0.0655337000, 0.0750183000, 0.0958611000, 0.1421320000, 0.2648398000, 0.5825154000", \ - "0.1057187000, 0.1114699000, 0.1240461000, 0.1506807000, 0.2034715000, 0.3142333000, 0.5962265000", \ - "0.1879224000, 0.1953869000, 0.2129698000, 0.2502097000, 0.3223699000, 0.4549993000, 0.7143218000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011771800, 0.0027715000, 0.0065251100, 0.0153624000, 0.0361687000, 0.0851540000"); - values("0.0973297000, 0.1104250000, 0.1414195000, 0.2140724000, 0.3847555000, 0.7826692000, 1.7200644000", \ - "0.0971829000, 0.1102790000, 0.1417488000, 0.2140867000, 0.3843141000, 0.7826013000, 1.7195083000", \ - "0.0967813000, 0.1104008000, 0.1415576000, 0.2140810000, 0.3844141000, 0.7829074000, 1.7216288000", \ - "0.0964732000, 0.1094601000, 0.1409206000, 0.2141930000, 0.3843193000, 0.7830245000, 1.7235685000", \ - "0.1177805000, 0.1286715000, 0.1542337000, 0.2189513000, 0.3839216000, 0.7832573000, 1.7210899000", \ - "0.1709832000, 0.1860122000, 0.2176222000, 0.2795873000, 0.4166285000, 0.7850345000, 1.7199048000", \ - "0.2645532000, 0.2866365000, 0.3323118000, 0.4195525000, 0.5786818000, 0.8860120000, 1.7304458000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32oi_2") { - leakage_power () { - value : 0.0007973000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0167322000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0006329000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0008306000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0018249000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0006652000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0008207000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0018471000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0006560000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015174000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0024733000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0013522000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0035251000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0028764000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0043939000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0013527000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0033431000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0011878000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0012316000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0042336000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0037690000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0010670000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0026624000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0069509000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0003049000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0027760000; - when : "A1&A2&A3&B1&!B2"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__a32oi"; - cell_leakage_power : 0.0028886930; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092225000, 0.0092220000, 0.0092210000, 0.0092167000, 0.0092070000, 0.0091847000, 0.0091331000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006443400, -0.006442800, -0.006441200, -0.006423600, -0.006383000, -0.006289400, -0.006073800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044730000; - } - pin ("A2") { - capacitance : 0.0043260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083516000, 0.0083521000, 0.0083534000, 0.0083836000, 0.0084532000, 0.0086136000, 0.0089834000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007765000, -0.007765100, -0.007765300, -0.007762700, -0.007756600, -0.007742500, -0.007710000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044750000; - } - pin ("A3") { - capacitance : 0.0044840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078930000, 0.0079037000, 0.0079282000, 0.0079323000, 0.0079418000, 0.0079638000, 0.0080143000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007914100, -0.007914400, -0.007915200, -0.007916500, -0.007919400, -0.007926000, -0.007941400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047300000; - } - pin ("B1") { - capacitance : 0.0042230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090018000, 0.0089995000, 0.0089942000, 0.0089983000, 0.0090078000, 0.0090297000, 0.0090802000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006279100, -0.006279500, -0.006280400, -0.006265400, -0.006230800, -0.006151100, -0.005967300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044560000; - } - pin ("B2") { - capacitance : 0.0042970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079033000, 0.0078973000, 0.0078835000, 0.0078851000, 0.0078886000, 0.0078968000, 0.0079155000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007885300, -0.007881400, -0.007872400, -0.007869900, -0.007864000, -0.007850400, -0.007819100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046100000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A3&!B1) | (!A2&!B2) | (!A3&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0136346000, 0.0123622000, 0.0090176000, 0.0003987000, -0.022288500, -0.081761500, -0.236688000", \ - "0.0134760000, 0.0121819000, 0.0088810000, 0.0002250000, -0.022475500, -0.081828700, -0.236775600", \ - "0.0131306000, 0.0118750000, 0.0085896000, -2.23000e-05, -0.022596400, -0.082027800, -0.237095200", \ - "0.0126427000, 0.0113829000, 0.0081211000, -0.000421000, -0.022945100, -0.082234100, -0.237057400", \ - "0.0121937000, 0.0109288000, 0.0076645000, -0.000860900, -0.023299700, -0.082472400, -0.237317700", \ - "0.0126477000, 0.0112434000, 0.0078610000, -0.000815700, -0.023493700, -0.082647600, -0.237410000", \ - "0.0140308000, 0.0126663000, 0.0092061000, 0.0002146000, -0.022733000, -0.082569800, -0.237033300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0213410000, 0.0226696000, 0.0261460000, 0.0350934000, 0.0579015000, 0.1168090000, 0.2701850000", \ - "0.0211154000, 0.0224556000, 0.0259643000, 0.0349661000, 0.0578983000, 0.1169636000, 0.2704089000", \ - "0.0206376000, 0.0220187000, 0.0255411000, 0.0346076000, 0.0576892000, 0.1168549000, 0.2703904000", \ - "0.0200906000, 0.0214355000, 0.0249280000, 0.0339760000, 0.0571825000, 0.1166491000, 0.2700673000", \ - "0.0197098000, 0.0210518000, 0.0244891000, 0.0333690000, 0.0565044000, 0.1159908000, 0.2699711000", \ - "0.0196218000, 0.0209424000, 0.0243614000, 0.0332350000, 0.0561249000, 0.1154661000, 0.2695192000", \ - "0.0193125000, 0.0206086000, 0.0239477000, 0.0330745000, 0.0561448000, 0.1154513000, 0.2690513000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0149690000, 0.0136804000, 0.0103702000, 0.0017070000, -0.021023600, -0.080432500, -0.235535900", \ - "0.0148161000, 0.0135638000, 0.0101881000, 0.0015842000, -0.021130800, -0.080520000, -0.235606700", \ - "0.0145771000, 0.0133215000, 0.0099958000, 0.0013658000, -0.021355900, -0.080726000, -0.235757700", \ - "0.0142103000, 0.0129552000, 0.0096579000, 0.0010600000, -0.021543800, -0.080820500, -0.235867100", \ - "0.0138366000, 0.0125676000, 0.0093304000, 0.0007416000, -0.021695200, -0.080933800, -0.235880200", \ - "0.0139056000, 0.0126253000, 0.0092400000, 0.0004017000, -0.022164300, -0.081200600, -0.236091900", \ - "0.0148598000, 0.0135376000, 0.0101515000, 0.0012830000, -0.021741700, -0.081391900, -0.236131000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0284049000, 0.0297020000, 0.0330621000, 0.0418622000, 0.0646841000, 0.1237271000, 0.2771789000", \ - "0.0281421000, 0.0294833000, 0.0328374000, 0.0417239000, 0.0646119000, 0.1236593000, 0.2770005000", \ - "0.0276494000, 0.0289910000, 0.0324682000, 0.0414347000, 0.0644443000, 0.1235495000, 0.2769752000", \ - "0.0271828000, 0.0285111000, 0.0319281000, 0.0409129000, 0.0639766000, 0.1232901000, 0.2767960000", \ - "0.0266836000, 0.0279872000, 0.0314862000, 0.0403488000, 0.0633867000, 0.1226990000, 0.2764783000", \ - "0.0264611000, 0.0277803000, 0.0311994000, 0.0400534000, 0.0629776000, 0.1223040000, 0.2760691000", \ - "0.0256756000, 0.0270213000, 0.0302759000, 0.0395535000, 0.0626211000, 0.1221600000, 0.2754338000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0149715000, 0.0137176000, 0.0103365000, 0.0017267000, -0.020996700, -0.080389800, -0.235524300", \ - "0.0148026000, 0.0135264000, 0.0101977000, 0.0015542000, -0.021148300, -0.080527100, -0.235582700", \ - "0.0145545000, 0.0132866000, 0.0099931000, 0.0013211000, -0.021396900, -0.080664200, -0.235747500", \ - "0.0141236000, 0.0128675000, 0.0095612000, 0.0009796000, -0.021621500, -0.080858700, -0.235878400", \ - "0.0138076000, 0.0125398000, 0.0093497000, 0.0007402000, -0.021795500, -0.080992600, -0.235724300", \ - "0.0138682000, 0.0125744000, 0.0092462000, 0.0004549000, -0.022266200, -0.081255500, -0.236024900", \ - "0.0148741000, 0.0135453000, 0.0101165000, 0.0013035000, -0.021691300, -0.081361700, -0.236048500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0339712000, 0.0352415000, 0.0387384000, 0.0475379000, 0.0704060000, 0.1295225000, 0.2830538000", \ - "0.0338570000, 0.0351890000, 0.0385060000, 0.0474644000, 0.0703352000, 0.1293786000, 0.2829689000", \ - "0.0335807000, 0.0349236000, 0.0382611000, 0.0472197000, 0.0701564000, 0.1293576000, 0.2827598000", \ - "0.0332691000, 0.0345828000, 0.0380946000, 0.0469998000, 0.0699595000, 0.1291038000, 0.2825228000", \ - "0.0330484000, 0.0343927000, 0.0378411000, 0.0466770000, 0.0696491000, 0.1288907000, 0.2824602000", \ - "0.0329177000, 0.0343113000, 0.0377663000, 0.0466108000, 0.0695989000, 0.1288923000, 0.2824290000", \ - "0.0326703000, 0.0339430000, 0.0372264000, 0.0465244000, 0.0696214000, 0.1291720000, 0.2823598000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0044062000, 0.0031929000, -4.56000e-05, -0.008714700, -0.031547100, -0.091159200, -0.246462000", \ - "0.0041294000, 0.0029736000, -0.000181100, -0.008732200, -0.031469100, -0.091029200, -0.246288100", \ - "0.0037924000, 0.0026633000, -0.000451600, -0.008871400, -0.031476300, -0.090921200, -0.246124800", \ - "0.0033906000, 0.0022389000, -0.000846500, -0.009243900, -0.031688200, -0.090951500, -0.246072500", \ - "0.0032975000, 0.0020610000, -0.001127100, -0.009615800, -0.032003900, -0.091146400, -0.246110800", \ - "0.0039564000, 0.0026381000, -0.000759300, -0.009410900, -0.032286400, -0.091607300, -0.246371600", \ - "0.0061332000, 0.0046547000, 0.0009442000, -0.008237400, -0.031466400, -0.090775700, -0.246534100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0206355000, 0.0219767000, 0.0255010000, 0.0345292000, 0.0575163000, 0.1166280000, 0.2701029000", \ - "0.0202826000, 0.0217078000, 0.0252140000, 0.0343212000, 0.0574407000, 0.1166248000, 0.2700968000", \ - "0.0198906000, 0.0212557000, 0.0248132000, 0.0338252000, 0.0570798000, 0.1166124000, 0.2700163000", \ - "0.0193945000, 0.0207489000, 0.0243023000, 0.0332062000, 0.0562713000, 0.1160484000, 0.2698544000", \ - "0.0192263000, 0.0205495000, 0.0239348000, 0.0328685000, 0.0559082000, 0.1153965000, 0.2694169000", \ - "0.0197293000, 0.0210083000, 0.0243627000, 0.0330895000, 0.0558717000, 0.1150858000, 0.2687773000", \ - "0.0237427000, 0.0231287000, 0.0262858000, 0.0347370000, 0.0571151000, 0.1155223000, 0.2684864000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0060755000, 0.0048519000, 0.0015825000, -0.007106900, -0.029949500, -0.089558600, -0.244847800", \ - "0.0058186000, 0.0046411000, 0.0014685000, -0.007102300, -0.029848600, -0.089411500, -0.244672600", \ - "0.0053876000, 0.0042336000, 0.0011548000, -0.007264100, -0.029845400, -0.089303900, -0.244500000", \ - "0.0048726000, 0.0037002000, 0.0006033000, -0.007704900, -0.030070200, -0.089349800, -0.244442700", \ - "0.0048524000, 0.0036244000, 0.0002596000, -0.008238700, -0.030488500, -0.089562600, -0.244509000", \ - "0.0050376000, 0.0037398000, 0.0003968000, -0.008289800, -0.031029500, -0.090057700, -0.244776300", \ - "0.0069757000, 0.0055664000, 0.0019665000, -0.007177800, -0.030350700, -0.090002100, -0.245000500"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0280204000, 0.0293568000, 0.0327814000, 0.0416598000, 0.0646245000, 0.1237732000, 0.2772448000", \ - "0.0277713000, 0.0290654000, 0.0325765000, 0.0413846000, 0.0644088000, 0.1236408000, 0.2770896000", \ - "0.0273181000, 0.0286474000, 0.0321102000, 0.0411010000, 0.0642672000, 0.1235703000, 0.2771363000", \ - "0.0270101000, 0.0283077000, 0.0318071000, 0.0407072000, 0.0638749000, 0.1232643000, 0.2768867000", \ - "0.0268045000, 0.0281482000, 0.0315353000, 0.0404444000, 0.0634481000, 0.1228437000, 0.2765995000", \ - "0.0274717000, 0.0287590000, 0.0321223000, 0.0408374000, 0.0635656000, 0.1227702000, 0.2762798000", \ - "0.0305353000, 0.0317352000, 0.0348809000, 0.0431276000, 0.0656819000, 0.1247319000, 0.2762801000"); - } - } - max_capacitance : 0.1556500000; - max_transition : 1.9190130000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0569036000, 0.0607645000, 0.0700704000, 0.0940991000, 0.1523542000, 0.3005744000, 0.6820212000", \ - "0.0607648000, 0.0643047000, 0.0740295000, 0.0973068000, 0.1560901000, 0.3044822000, 0.6859547000", \ - "0.0695766000, 0.0734790000, 0.0831338000, 0.1069520000, 0.1653946000, 0.3137558000, 0.6953947000", \ - "0.0922350000, 0.0959512000, 0.1052310000, 0.1288865000, 0.1875751000, 0.3360931000, 0.7189506000", \ - "0.1275691000, 0.1331283000, 0.1464452000, 0.1771437000, 0.2401004000, 0.3882062000, 0.7698881000", \ - "0.1641932000, 0.1725018000, 0.1918997000, 0.2374481000, 0.3317047000, 0.5092428000, 0.8909768000", \ - "0.1801657000, 0.1923714000, 0.2231456000, 0.2930186000, 0.4348162000, 0.7020420000, 1.1715496000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1160443000, 0.1232117000, 0.1417684000, 0.1881995000, 0.3070008000, 0.6131677000, 1.4071890000", \ - "0.1211853000, 0.1283322000, 0.1471043000, 0.1938762000, 0.3131929000, 0.6191944000, 1.4132757000", \ - "0.1336245000, 0.1409424000, 0.1594559000, 0.2067411000, 0.3266142000, 0.6336004000, 1.4280125000", \ - "0.1634422000, 0.1709522000, 0.1894594000, 0.2367157000, 0.3569341000, 0.6646284000, 1.4605437000", \ - "0.2282401000, 0.2360709000, 0.2547117000, 0.3012667000, 0.4208022000, 0.7295635000, 1.5253139000", \ - "0.3408078000, 0.3513172000, 0.3761429000, 0.4358337000, 0.5661462000, 0.8744024000, 1.6715871000", \ - "0.5250455000, 0.5419374000, 0.5821132000, 0.6704329000, 0.8499949000, 1.2075339000, 2.0108495000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0517678000, 0.0561893000, 0.0676121000, 0.0971048000, 0.1740351000, 0.3735088000, 0.8931955000", \ - "0.0519753000, 0.0563296000, 0.0676952000, 0.0971669000, 0.1737486000, 0.3737181000, 0.8935365000", \ - "0.0509856000, 0.0554910000, 0.0673915000, 0.0969752000, 0.1738479000, 0.3734263000, 0.8949035000", \ - "0.0564934000, 0.0602347000, 0.0703324000, 0.0978981000, 0.1736799000, 0.3735287000, 0.8937273000", \ - "0.0770974000, 0.0823867000, 0.0949501000, 0.1235638000, 0.1875023000, 0.3737448000, 0.8933443000", \ - "0.1204941000, 0.1279874000, 0.1453930000, 0.1826098000, 0.2588695000, 0.4217415000, 0.8961904000", \ - "0.1949270000, 0.2073074000, 0.2339523000, 0.2903956000, 0.3956266000, 0.6004056000, 1.0128732000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0746841000, 0.0839109000, 0.1081924000, 0.1705955000, 0.3333439000, 0.7522546000, 1.8463786000", \ - "0.0747124000, 0.0838855000, 0.1082096000, 0.1705200000, 0.3333649000, 0.7510104000, 1.8460147000", \ - "0.0747752000, 0.0840728000, 0.1082102000, 0.1705775000, 0.3321870000, 0.7522335000, 1.8450975000", \ - "0.0750139000, 0.0841164000, 0.1082855000, 0.1706945000, 0.3320609000, 0.7510939000, 1.8463155000", \ - "0.0833811000, 0.0917555000, 0.1139774000, 0.1731855000, 0.3318594000, 0.7540374000, 1.8406451000", \ - "0.1198623000, 0.1290143000, 0.1524302000, 0.2093589000, 0.3508558000, 0.7519377000, 1.8431479000", \ - "0.2017930000, 0.2132376000, 0.2419370000, 0.3080802000, 0.4571369000, 0.8122062000, 1.8439283000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0669239000, 0.0708910000, 0.0805462000, 0.1041985000, 0.1624737000, 0.3107037000, 0.6923114000", \ - "0.0713913000, 0.0752536000, 0.0845088000, 0.1084020000, 0.1667840000, 0.3150093000, 0.6965339000", \ - "0.0802044000, 0.0841754000, 0.0935921000, 0.1173171000, 0.1760402000, 0.3243845000, 0.7058013000", \ - "0.1005120000, 0.1047043000, 0.1143053000, 0.1381697000, 0.1971266000, 0.3455246000, 0.7272350000", \ - "0.1358640000, 0.1409077000, 0.1533639000, 0.1811709000, 0.2450029000, 0.3942253000, 0.7768587000", \ - "0.1789239000, 0.1863038000, 0.2042255000, 0.2456823000, 0.3315360000, 0.5047291000, 0.8905437000", \ - "0.2054078000, 0.2169333000, 0.2448770000, 0.3080066000, 0.4406634000, 0.6869920000, 1.1405171000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1423745000, 0.1494099000, 0.1675209000, 0.2142499000, 0.3334885000, 0.6415437000, 1.4408335000", \ - "0.1465083000, 0.1542238000, 0.1728853000, 0.2191904000, 0.3388490000, 0.6471646000, 1.4477112000", \ - "0.1597554000, 0.1669963000, 0.1858211000, 0.2326770000, 0.3523429000, 0.6611873000, 1.4606273000", \ - "0.1899296000, 0.1972368000, 0.2153986000, 0.2627614000, 0.3832408000, 0.6925918000, 1.4941534000", \ - "0.2555597000, 0.2621517000, 0.2807943000, 0.3273976000, 0.4476858000, 0.7580573000, 1.5588042000", \ - "0.3778708000, 0.3871804000, 0.4093926000, 0.4653418000, 0.5921785000, 0.9024286000, 1.7036395000", \ - "0.5846869000, 0.5987609000, 0.6336595000, 0.7125371000, 0.8821606000, 1.2359195000, 2.0412294000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0518144000, 0.0561666000, 0.0677324000, 0.0970402000, 0.1738560000, 0.3733772000, 0.8947258000", \ - "0.0517085000, 0.0561929000, 0.0675741000, 0.0972864000, 0.1738799000, 0.3733951000, 0.8937168000", \ - "0.0515003000, 0.0558921000, 0.0674974000, 0.0971002000, 0.1739254000, 0.3739455000, 0.8940416000", \ - "0.0545792000, 0.0586742000, 0.0694739000, 0.0978523000, 0.1736818000, 0.3733490000, 0.8941476000", \ - "0.0722412000, 0.0765115000, 0.0876899000, 0.1149983000, 0.1825067000, 0.3743927000, 0.8937471000", \ - "0.1120082000, 0.1173167000, 0.1317537000, 0.1636139000, 0.2352402000, 0.4068229000, 0.8957268000", \ - "0.1850320000, 0.1934913000, 0.2138265000, 0.2597653000, 0.3544595000, 0.5387871000, 0.9689536000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0953601000, 0.1045726000, 0.1290774000, 0.1924793000, 0.3560791000, 0.7791889000, 1.8823867000", \ - "0.0953850000, 0.1048779000, 0.1293041000, 0.1923146000, 0.3559810000, 0.7783528000, 1.8777586000", \ - "0.0949931000, 0.1045445000, 0.1292829000, 0.1928214000, 0.3560306000, 0.7788611000, 1.8748565000", \ - "0.0952850000, 0.1047029000, 0.1291226000, 0.1924115000, 0.3556890000, 0.7792271000, 1.8791857000", \ - "0.1003988000, 0.1094140000, 0.1328249000, 0.1936206000, 0.3559222000, 0.7794669000, 1.8807955000", \ - "0.1352364000, 0.1444884000, 0.1676916000, 0.2244330000, 0.3713599000, 0.7790871000, 1.8784154000", \ - "0.2180830000, 0.2291537000, 0.2562207000, 0.3215896000, 0.4705391000, 0.8340332000, 1.8811370000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0714429000, 0.0752892000, 0.0845504000, 0.1084646000, 0.1667790000, 0.3149657000, 0.6965448000", \ - "0.0755215000, 0.0793875000, 0.0888711000, 0.1127420000, 0.1710481000, 0.3191895000, 0.7006495000", \ - "0.0835437000, 0.0871629000, 0.0968198000, 0.1205129000, 0.1791233000, 0.3275155000, 0.7087851000", \ - "0.0990821000, 0.1030675000, 0.1127815000, 0.1364882000, 0.1953176000, 0.3437512000, 0.7254251000", \ - "0.1265333000, 0.1308020000, 0.1420370000, 0.1683733000, 0.2304346000, 0.3795671000, 0.7618144000", \ - "0.1642163000, 0.1703333000, 0.1852046000, 0.2195022000, 0.2946150000, 0.4594039000, 0.8444075000", \ - "0.1913298000, 0.2006170000, 0.2239448000, 0.2767905000, 0.3852751000, 0.5953715000, 1.0283254000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1551111000, 0.1618630000, 0.1800485000, 0.2250983000, 0.3422328000, 0.6429278000, 1.4210069000", \ - "0.1596940000, 0.1675369000, 0.1856608000, 0.2308360000, 0.3477086000, 0.6484184000, 1.4265910000", \ - "0.1729087000, 0.1808916000, 0.1990981000, 0.2448172000, 0.3613588000, 0.6621773000, 1.4408229000", \ - "0.2039284000, 0.2107907000, 0.2288471000, 0.2740563000, 0.3916978000, 0.6927778000, 1.4711098000", \ - "0.2658827000, 0.2729612000, 0.2908598000, 0.3368059000, 0.4539792000, 0.7554907000, 1.5338012000", \ - "0.3833218000, 0.3916539000, 0.4150021000, 0.4679055000, 0.5906890000, 0.8922472000, 1.6717471000", \ - "0.5820815000, 0.5946121000, 0.6255372000, 0.6981766000, 0.8592494000, 1.2038588000, 1.9866291000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0517168000, 0.0562159000, 0.0675911000, 0.0972584000, 0.1738843000, 0.3735415000, 0.8939117000", \ - "0.0516899000, 0.0561409000, 0.0676827000, 0.0970818000, 0.1739211000, 0.3735134000, 0.8933260000", \ - "0.0516920000, 0.0561244000, 0.0675183000, 0.0970819000, 0.1739301000, 0.3737600000, 0.8936169000", \ - "0.0535136000, 0.0576954000, 0.0687311000, 0.0977508000, 0.1737594000, 0.3733510000, 0.8943281000", \ - "0.0642897000, 0.0686265000, 0.0800254000, 0.1083391000, 0.1796908000, 0.3744022000, 0.8935475000", \ - "0.0943765000, 0.0992885000, 0.1114947000, 0.1409887000, 0.2134932000, 0.3945501000, 0.8973382000", \ - "0.1600918000, 0.1662070000, 0.1831799000, 0.2198715000, 0.3016833000, 0.4853823000, 0.9484754000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1093092000, 0.1187132000, 0.1432094000, 0.2047988000, 0.3645048000, 0.7776185000, 1.8476149000", \ - "0.1097318000, 0.1194035000, 0.1428166000, 0.2052159000, 0.3646606000, 0.7763261000, 1.8472780000", \ - "0.1097181000, 0.1194011000, 0.1428117000, 0.2049995000, 0.3644859000, 0.7767045000, 1.8520376000", \ - "0.1092740000, 0.1186860000, 0.1430823000, 0.2053050000, 0.3645686000, 0.7764027000, 1.8490647000", \ - "0.1141399000, 0.1228478000, 0.1458025000, 0.2058871000, 0.3649471000, 0.7783325000, 1.8493211000", \ - "0.1472479000, 0.1570147000, 0.1796302000, 0.2352509000, 0.3804954000, 0.7783202000, 1.8521562000", \ - "0.2280898000, 0.2389599000, 0.2659505000, 0.3296457000, 0.4772063000, 0.8360905000, 1.8548678000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0221796000, 0.0245342000, 0.0306291000, 0.0459262000, 0.0852760000, 0.1869791000, 0.4515194000", \ - "0.0261391000, 0.0285186000, 0.0347279000, 0.0502822000, 0.0896924000, 0.1915168000, 0.4562522000", \ - "0.0350278000, 0.0379750000, 0.0448101000, 0.0604942000, 0.0999169000, 0.2021385000, 0.4665348000", \ - "0.0451422000, 0.0497060000, 0.0603118000, 0.0823426000, 0.1240701000, 0.2260716000, 0.4910382000", \ - "0.0527207000, 0.0601353000, 0.0770602000, 0.1107679000, 0.1724431000, 0.2817855000, 0.5462625000", \ - "0.0470666000, 0.0585516000, 0.0843460000, 0.1366800000, 0.2321128000, 0.3943176000, 0.6750152000", \ - "-0.001095200, 0.0166167000, 0.0567705000, 0.1376835000, 0.2864529000, 0.5348162000, 0.9438361000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1000900000, 0.1078745000, 0.1268005000, 0.1758559000, 0.2985432000, 0.6120114000, 1.4251423000", \ - "0.1037672000, 0.1111469000, 0.1308540000, 0.1797331000, 0.3027049000, 0.6171040000, 1.4300515000", \ - "0.1143115000, 0.1218108000, 0.1412838000, 0.1899848000, 0.3134528000, 0.6285529000, 1.4414827000", \ - "0.1417204000, 0.1492339000, 0.1682222000, 0.2172739000, 0.3397256000, 0.6556831000, 1.4694757000", \ - "0.2103635000, 0.2181320000, 0.2377245000, 0.2846531000, 0.4070950000, 0.7218730000, 1.5369489000", \ - "0.3302390000, 0.3425661000, 0.3702677000, 0.4347794000, 0.5677492000, 0.8796400000, 1.6903353000", \ - "0.5270072000, 0.5441161000, 0.5876707000, 0.6860301000, 0.8844940000, 1.2521245000, 2.0581177000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0268395000, 0.0298979000, 0.0377773000, 0.0581531000, 0.1111629000, 0.2489279000, 0.6078971000", \ - "0.0267972000, 0.0298227000, 0.0377395000, 0.0581388000, 0.1109891000, 0.2500409000, 0.6082644000", \ - "0.0316166000, 0.0339196000, 0.0402871000, 0.0587626000, 0.1109973000, 0.2490802000, 0.6079210000", \ - "0.0466870000, 0.0492731000, 0.0556216000, 0.0705353000, 0.1147735000, 0.2488827000, 0.6078896000", \ - "0.0757359000, 0.0788212000, 0.0864610000, 0.1052380000, 0.1464318000, 0.2596941000, 0.6081941000", \ - "0.1285381000, 0.1328874000, 0.1438443000, 0.1700367000, 0.2240838000, 0.3341434000, 0.6287895000", \ - "0.2213138000, 0.2286077000, 0.2437190000, 0.2820987000, 0.3632414000, 0.5167452000, 0.7981150000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0937453000, 0.1034193000, 0.1282991000, 0.1927480000, 0.3592494000, 0.7915423000, 1.9190134000", \ - "0.0932489000, 0.1033967000, 0.1282498000, 0.1928142000, 0.3597227000, 0.7906011000, 1.9112356000", \ - "0.0935048000, 0.1033492000, 0.1282687000, 0.1927401000, 0.3597562000, 0.7910559000, 1.9165107000", \ - "0.0920914000, 0.1020660000, 0.1272989000, 0.1927043000, 0.3593613000, 0.7907016000, 1.9178212000", \ - "0.1113506000, 0.1192836000, 0.1400510000, 0.1978178000, 0.3590050000, 0.7910398000, 1.9158177000", \ - "0.1639491000, 0.1749586000, 0.2012714000, 0.2583295000, 0.3909016000, 0.7930058000, 1.9135493000", \ - "0.2541364000, 0.2714748000, 0.3095892000, 0.3906877000, 0.5487447000, 0.8827529000, 1.9187290000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0281836000, 0.0305889000, 0.0365614000, 0.0518332000, 0.0910477000, 0.1927897000, 0.4573442000", \ - "0.0324890000, 0.0349820000, 0.0412179000, 0.0565774000, 0.0960044000, 0.1978298000, 0.4623902000", \ - "0.0409782000, 0.0437316000, 0.0501772000, 0.0659798000, 0.1055864000, 0.2076856000, 0.4723127000", \ - "0.0529803000, 0.0567387000, 0.0656885000, 0.0851782000, 0.1267655000, 0.2294403000, 0.4942156000", \ - "0.0651768000, 0.0712540000, 0.0855510000, 0.1140523000, 0.1694888000, 0.2782945000, 0.5436623000", \ - "0.0674529000, 0.0772228000, 0.1000246000, 0.1454866000, 0.2295355000, 0.3745412000, 0.6561873000", \ - "0.0319449000, 0.0478586000, 0.0839703000, 0.1575870000, 0.2916235000, 0.5143939000, 0.8845850000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1208244000, 0.1278998000, 0.1454875000, 0.1919625000, 0.3082678000, 0.6090359000, 1.3885699000", \ - "0.1237259000, 0.1315924000, 0.1494578000, 0.1955234000, 0.3130095000, 0.6140993000, 1.3924343000", \ - "0.1346527000, 0.1410689000, 0.1596305000, 0.2057656000, 0.3232902000, 0.6246454000, 1.4036364000", \ - "0.1609800000, 0.1678437000, 0.1861174000, 0.2325474000, 0.3495986000, 0.6517058000, 1.4306892000", \ - "0.2283212000, 0.2358967000, 0.2534753000, 0.2986086000, 0.4158968000, 0.7176870000, 1.4968409000", \ - "0.3557724000, 0.3660255000, 0.3910187000, 0.4484307000, 0.5723173000, 0.8703320000, 1.6487360000", \ - "0.5575478000, 0.5728443000, 0.6101394000, 0.6963271000, 0.8812297000, 1.2321714000, 2.0046962000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0267925000, 0.0298079000, 0.0376905000, 0.0580713000, 0.1110283000, 0.2485692000, 0.6080661000", \ - "0.0268325000, 0.0298326000, 0.0376812000, 0.0580856000, 0.1109421000, 0.2489182000, 0.6077415000", \ - "0.0289169000, 0.0316073000, 0.0388183000, 0.0582155000, 0.1108794000, 0.2488716000, 0.6074914000", \ - "0.0394559000, 0.0418910000, 0.0482398000, 0.0647622000, 0.1130501000, 0.2489120000, 0.6079974000", \ - "0.0625461000, 0.0652808000, 0.0722668000, 0.0897511000, 0.1332674000, 0.2553065000, 0.6074319000", \ - "0.1075932000, 0.1113064000, 0.1202681000, 0.1423261000, 0.1925317000, 0.3044581000, 0.6234735000", \ - "0.1937237000, 0.1978421000, 0.2095524000, 0.2396549000, 0.3047028000, 0.4393317000, 0.7333680000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1091351000, 0.1185979000, 0.1427565000, 0.2047895000, 0.3641752000, 0.7786454000, 1.8527229000", \ - "0.1097608000, 0.1187201000, 0.1431845000, 0.2046863000, 0.3645307000, 0.7791765000, 1.8485951000", \ - "0.1090009000, 0.1185351000, 0.1426063000, 0.2046811000, 0.3646347000, 0.7778064000, 1.8478085000", \ - "0.1081140000, 0.1174719000, 0.1425140000, 0.2047216000, 0.3647219000, 0.7772913000, 1.8490752000", \ - "0.1225991000, 0.1308934000, 0.1515850000, 0.2083239000, 0.3642025000, 0.7781707000, 1.8492003000", \ - "0.1774709000, 0.1876786000, 0.2122323000, 0.2666152000, 0.3957324000, 0.7795615000, 1.8488255000", \ - "0.2710649000, 0.2858670000, 0.3208092000, 0.3979886000, 0.5518584000, 0.8747492000, 1.8532813000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a32oi_4") { - leakage_power () { - value : 0.0020017000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0002656000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0015811000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0020858000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0003500000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0016654000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0020610000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0003247000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0016402000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0038377000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0020941000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0034103000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0020858000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0003434000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0016653000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0034103000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0016713000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0029897000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0031021000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0013641000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0051337000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0026885000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0039808000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0041797000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0004544000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0041240000; - when : "A1&A2&A3&B1&!B2"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__a32oi"; - cell_leakage_power : 0.0027910300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0083290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0180689000, 0.0180753000, 0.0180902000, 0.0180910000, 0.0180930000, 0.0180975000, 0.0181080000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012790900, -0.012801500, -0.012825800, -0.012795500, -0.012725800, -0.012565000, -0.012194500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085390000; - } - pin ("A2") { - capacitance : 0.0082260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0170436000, 0.0170463000, 0.0170524000, 0.0171143000, 0.0172572000, 0.0175865000, 0.0183456000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015580600, -0.015563100, -0.015522800, -0.015520600, -0.015515700, -0.015504200, -0.015477700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085360000; - } - pin ("A3") { - capacitance : 0.0085060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156261000, 0.0156256000, 0.0156245000, 0.0156310000, 0.0156461000, 0.0156809000, 0.0157611000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015626000, -0.015623500, -0.015617800, -0.015605700, -0.015578000, -0.015514200, -0.015367000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089780000; - } - pin ("B1") { - capacitance : 0.0082430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0179179000, 0.0179139000, 0.0179046000, 0.0179095000, 0.0179207000, 0.0179466000, 0.0180062000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013000400, -0.013013200, -0.013042600, -0.013013900, -0.012947800, -0.012795500, -0.012444500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087320000; - } - pin ("B2") { - capacitance : 0.0084790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158960000, 0.0158818000, 0.0158489000, 0.0158494000, 0.0158507000, 0.0158537000, 0.0158606000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015838800, -0.015829300, -0.015807500, -0.015806300, -0.015803800, -0.015797800, -0.015784100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091650000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A3&!B1) | (!A2&!B2) | (!A3&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0278766000, 0.0264201000, 0.0222980000, 0.0109070000, -0.021786800, -0.114684400, -0.377348600", \ - "0.0275289000, 0.0260537000, 0.0219530000, 0.0104810000, -0.022150900, -0.115003200, -0.377570500", \ - "0.0268871000, 0.0254520000, 0.0214726000, 0.0100793000, -0.022487800, -0.115302300, -0.377778600", \ - "0.0260353000, 0.0246087000, 0.0206181000, 0.0092055000, -0.023207700, -0.115737000, -0.378136800", \ - "0.0252271000, 0.0238025000, 0.0197467000, 0.0084272000, -0.023928100, -0.116042800, -0.378226900", \ - "0.0253285000, 0.0238487000, 0.0196637000, 0.0079230000, -0.024711500, -0.116796200, -0.378893300", \ - "0.0289701000, 0.0274419000, 0.0231762000, 0.0113162000, -0.022496500, -0.116512700, -0.378185300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0410125000, 0.0425153000, 0.0467475000, 0.0586282000, 0.0917013000, 0.1839724000, 0.4439377000", \ - "0.0405943000, 0.0421112000, 0.0464076000, 0.0584278000, 0.0916548000, 0.1841829000, 0.4441066000", \ - "0.0397363000, 0.0412736000, 0.0456023000, 0.0577566000, 0.0912575000, 0.1840801000, 0.4442834000", \ - "0.0386007000, 0.0401267000, 0.0444189000, 0.0565431000, 0.0903480000, 0.1837342000, 0.4441581000", \ - "0.0377004000, 0.0391902000, 0.0434548000, 0.0553810000, 0.0889233000, 0.1824561000, 0.4433356000", \ - "0.0374857000, 0.0391039000, 0.0432051000, 0.0551072000, 0.0883531000, 0.1813678000, 0.4423273000", \ - "0.0366890000, 0.0381412000, 0.0422750000, 0.0544668000, 0.0882858000, 0.1811266000, 0.4419393000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0307081000, 0.0292893000, 0.0252044000, 0.0136874000, -0.019107800, -0.111937000, -0.374439200", \ - "0.0303897000, 0.0289353000, 0.0247893000, 0.0132089000, -0.019365100, -0.112178000, -0.374758500", \ - "0.0298725000, 0.0284395000, 0.0243794000, 0.0129363000, -0.019752000, -0.112549300, -0.375083500", \ - "0.0291630000, 0.0277158000, 0.0236573000, 0.0121711000, -0.020304700, -0.112898800, -0.375339400", \ - "0.0284397000, 0.0270150000, 0.0229908000, 0.0116320000, -0.020778100, -0.113087400, -0.375272200", \ - "0.0282484000, 0.0267933000, 0.0224719000, 0.0109428000, -0.021590700, -0.113838900, -0.375819300", \ - "0.0303459000, 0.0288439000, 0.0246433000, 0.0127830000, -0.020512200, -0.113992200, -0.375966000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0544658000, 0.0559562000, 0.0599835000, 0.0717614000, 0.1048586000, 0.1973518000, 0.4571095000", \ - "0.0540045000, 0.0555083000, 0.0595638000, 0.0714129000, 0.1045284000, 0.1970975000, 0.4574470000", \ - "0.0530197000, 0.0545277000, 0.0588307000, 0.0707566000, 0.1040973000, 0.1968323000, 0.4571198000", \ - "0.0520749000, 0.0534723000, 0.0577903000, 0.0697466000, 0.1032137000, 0.1961499000, 0.4566939000", \ - "0.0510458000, 0.0525347000, 0.0568070000, 0.0686036000, 0.1021390000, 0.1952136000, 0.4558781000", \ - "0.0505036000, 0.0519561000, 0.0562282000, 0.0681005000, 0.1010342000, 0.1941495000, 0.4550029000", \ - "0.0488229000, 0.0503015000, 0.0545728000, 0.0671363000, 0.1003978000, 0.1935604000, 0.4535081000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0302688000, 0.0288083000, 0.0247579000, 0.0131676000, -0.019475300, -0.112361000, -0.374933900", \ - "0.0299341000, 0.0284707000, 0.0243305000, 0.0127557000, -0.019839300, -0.112678800, -0.375234700", \ - "0.0294092000, 0.0279650000, 0.0239288000, 0.0123518000, -0.020262300, -0.112944100, -0.375520300", \ - "0.0287223000, 0.0272943000, 0.0231942000, 0.0117371000, -0.020738500, -0.113302900, -0.375759300", \ - "0.0282017000, 0.0267667000, 0.0226755000, 0.0112398000, -0.021160900, -0.113587200, -0.375843200", \ - "0.0282989000, 0.0268208000, 0.0226803000, 0.0109056000, -0.021806300, -0.114261600, -0.376347000", \ - "0.0298117000, 0.0283509000, 0.0241266000, 0.0122734000, -0.020800300, -0.114381500, -0.376567200"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0656566000, 0.0671949000, 0.0711356000, 0.0829324000, 0.1160739000, 0.2086735000, 0.4690819000", \ - "0.0652911000, 0.0666609000, 0.0707460000, 0.0825732000, 0.1157552000, 0.2083764000, 0.4687773000", \ - "0.0646514000, 0.0663538000, 0.0703813000, 0.0822300000, 0.1154985000, 0.2082918000, 0.4683546000", \ - "0.0641798000, 0.0656163000, 0.0700869000, 0.0817687000, 0.1149867000, 0.2077813000, 0.4685010000", \ - "0.0637448000, 0.0652511000, 0.0694875000, 0.0812767000, 0.1144962000, 0.2072476000, 0.4680689000", \ - "0.0636562000, 0.0651908000, 0.0694741000, 0.0812847000, 0.1142260000, 0.2071672000, 0.4676047000", \ - "0.0626060000, 0.0640273000, 0.0684984000, 0.0809993000, 0.1143476000, 0.2071161000, 0.4675350000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0102263000, 0.0088686000, 0.0049933000, -0.006373800, -0.039200700, -0.132401000, -0.395612800", \ - "0.0096843000, 0.0083805000, 0.0046204000, -0.006519800, -0.039082800, -0.132124400, -0.395284700", \ - "0.0089692000, 0.0076993000, 0.0039742000, -0.006955200, -0.039174200, -0.131924600, -0.394938800", \ - "0.0081225000, 0.0068616000, 0.0031360000, -0.007790500, -0.039708900, -0.132074100, -0.394845200", \ - "0.0079151000, 0.0065004000, 0.0025781000, -0.008374000, -0.040394300, -0.132533900, -0.394987800", \ - "0.0092460000, 0.0077176000, 0.0034984000, -0.008182800, -0.040718900, -0.133321700, -0.395526400", \ - "0.0132181000, 0.0115731000, 0.0069952000, -0.005371200, -0.039320600, -0.131611200, -0.395698600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0397343000, 0.0414025000, 0.0458187000, 0.0579274000, 0.0914463000, 0.1844203000, 0.4445760000", \ - "0.0391156000, 0.0406920000, 0.0451554000, 0.0572473000, 0.0910800000, 0.1839581000, 0.4442736000", \ - "0.0380187000, 0.0396739000, 0.0441225000, 0.0562301000, 0.0902209000, 0.1836820000, 0.4443456000", \ - "0.0372774000, 0.0388756000, 0.0431924000, 0.0550595000, 0.0890679000, 0.1826366000, 0.4439148000", \ - "0.0372482000, 0.0387278000, 0.0429049000, 0.0547830000, 0.0879884000, 0.1812268000, 0.4429036000", \ - "0.0378416000, 0.0393090000, 0.0434913000, 0.0552754000, 0.0885517000, 0.1809267000, 0.4417179000", \ - "0.0418625000, 0.0432153000, 0.0471429000, 0.0582656000, 0.0905266000, 0.1808693000, 0.4405905000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0132651000, 0.0118955000, 0.0079330000, -0.003528800, -0.036412200, -0.129638400, -0.392910400", \ - "0.0127093000, 0.0113932000, 0.0076019000, -0.003613700, -0.036263800, -0.129364900, -0.392545000", \ - "0.0118289000, 0.0105485000, 0.0068633000, -0.004070500, -0.036354600, -0.129175800, -0.392232900", \ - "0.0108067000, 0.0094992000, 0.0057612000, -0.005030700, -0.036897100, -0.129299400, -0.392090500", \ - "0.0107241000, 0.0093482000, 0.0051328000, -0.006110800, -0.037902800, -0.129823800, -0.392203600", \ - "0.0111736000, 0.0097096000, 0.0056337000, -0.005921400, -0.038358000, -0.130832700, -0.392761800", \ - "0.0146325000, 0.0130111000, 0.0085786000, -0.003699400, -0.037312600, -0.130475700, -0.393173100"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0537850000, 0.0551719000, 0.0594628000, 0.0712795000, 0.1044275000, 0.1972826000, 0.4574210000", \ - "0.0529348000, 0.0546709000, 0.0587288000, 0.0707145000, 0.1040372000, 0.1969175000, 0.4574128000", \ - "0.0521410000, 0.0537154000, 0.0581955000, 0.0702084000, 0.1037314000, 0.1968372000, 0.4573818000", \ - "0.0517419000, 0.0531286000, 0.0574055000, 0.0693654000, 0.1029324000, 0.1964982000, 0.4568732000", \ - "0.0512530000, 0.0527690000, 0.0569220000, 0.0688278000, 0.1021283000, 0.1954371000, 0.4564109000", \ - "0.0536827000, 0.0551697000, 0.0595200000, 0.0707031000, 0.1033649000, 0.1956224000, 0.4561915000", \ - "0.0574036000, 0.0587795000, 0.0627099000, 0.0739175000, 0.1062040000, 0.1978908000, 0.4578756000"); - } - } - max_capacitance : 0.2517800000; - max_transition : 1.9155600000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0630657000, 0.0654408000, 0.0722250000, 0.0909962000, 0.1402217000, 0.2735502000, 0.6444260000", \ - "0.0665302000, 0.0689019000, 0.0757836000, 0.0943391000, 0.1435266000, 0.2772597000, 0.6481833000", \ - "0.0752580000, 0.0777904000, 0.0848710000, 0.1034613000, 0.1528853000, 0.2864013000, 0.6578349000", \ - "0.0976183000, 0.1000441000, 0.1066723000, 0.1249241000, 0.1747367000, 0.3087677000, 0.6797549000", \ - "0.1327838000, 0.1362835000, 0.1457159000, 0.1698431000, 0.2254226000, 0.3590586000, 0.7304173000", \ - "0.1714766000, 0.1767238000, 0.1908316000, 0.2261385000, 0.3087844000, 0.4776692000, 0.8513563000", \ - "0.1855081000, 0.1933455000, 0.2139552000, 0.2675513000, 0.3926483000, 0.6468102000, 1.1234380000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1266089000, 0.1313370000, 0.1444580000, 0.1813859000, 0.2819532000, 0.5625286000, 1.3514893000", \ - "0.1317187000, 0.1364690000, 0.1499684000, 0.1869440000, 0.2883845000, 0.5698871000, 1.3586670000", \ - "0.1438973000, 0.1486142000, 0.1623210000, 0.1994360000, 0.3017912000, 0.5838810000, 1.3732124000", \ - "0.1731464000, 0.1778436000, 0.1917248000, 0.2289467000, 0.3314844000, 0.6148539000, 1.4051470000", \ - "0.2368378000, 0.2418173000, 0.2553190000, 0.2920380000, 0.3940128000, 0.6775875000, 1.4704280000", \ - "0.3486082000, 0.3548779000, 0.3728046000, 0.4185858000, 0.5323070000, 0.8161334000, 1.6089333000", \ - "0.5359468000, 0.5461029000, 0.5733357000, 0.6410683000, 0.7961520000, 1.1308794000, 1.9303530000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0577527000, 0.0607191000, 0.0690385000, 0.0926684000, 0.1588076000, 0.3438747000, 0.8675964000", \ - "0.0577628000, 0.0606605000, 0.0690083000, 0.0927139000, 0.1585741000, 0.3437919000, 0.8674793000", \ - "0.0572097000, 0.0603463000, 0.0688789000, 0.0925058000, 0.1586568000, 0.3440579000, 0.8674069000", \ - "0.0607231000, 0.0633508000, 0.0715150000, 0.0938015000, 0.1582614000, 0.3441498000, 0.8679141000", \ - "0.0818785000, 0.0854325000, 0.0946505000, 0.1184768000, 0.1751785000, 0.3454305000, 0.8679409000", \ - "0.1231947000, 0.1280580000, 0.1405956000, 0.1712885000, 0.2429569000, 0.3989612000, 0.8726148000", \ - "0.1988126000, 0.2060646000, 0.2249872000, 0.2707801000, 0.3700002000, 0.5704678000, 1.0067406000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0822411000, 0.0883106000, 0.1057198000, 0.1544289000, 0.2912195000, 0.6751363000, 1.7584443000", \ - "0.0822301000, 0.0882819000, 0.1058222000, 0.1543742000, 0.2912498000, 0.6771178000, 1.7560209000", \ - "0.0823610000, 0.0883258000, 0.1058442000, 0.1545631000, 0.2920006000, 0.6756536000, 1.7566049000", \ - "0.0823736000, 0.0885544000, 0.1058972000, 0.1546328000, 0.2913496000, 0.6754648000, 1.7545466000", \ - "0.0894775000, 0.0950810000, 0.1111683000, 0.1574837000, 0.2915996000, 0.6748923000, 1.7612699000", \ - "0.1225115000, 0.1288143000, 0.1455064000, 0.1914552000, 0.3120153000, 0.6773513000, 1.7550136000", \ - "0.2003166000, 0.2077214000, 0.2275378000, 0.2796592000, 0.4099772000, 0.7404953000, 1.7629052000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0741493000, 0.0767697000, 0.0835593000, 0.1020553000, 0.1511691000, 0.2848718000, 0.6562631000", \ - "0.0783165000, 0.0806582000, 0.0873394000, 0.1060780000, 0.1552259000, 0.2888473000, 0.6600450000", \ - "0.0866180000, 0.0892044000, 0.0961517000, 0.1147227000, 0.1640427000, 0.2974340000, 0.6684897000", \ - "0.1059908000, 0.1085132000, 0.1153248000, 0.1337805000, 0.1834287000, 0.3174092000, 0.6884195000", \ - "0.1395357000, 0.1427290000, 0.1514164000, 0.1738143000, 0.2272597000, 0.3627744000, 0.7360753000", \ - "0.1808510000, 0.1854912000, 0.1979486000, 0.2293609000, 0.3028022000, 0.4621385000, 0.8416398000", \ - "0.2020230000, 0.2091689000, 0.2283191000, 0.2766700000, 0.3895697000, 0.6198591000, 1.0740526000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1672817000, 0.1724475000, 0.1865223000, 0.2246793000, 0.3323867000, 0.6330334000, 1.4786321000", \ - "0.1721066000, 0.1770584000, 0.1913127000, 0.2298481000, 0.3379313000, 0.6386243000, 1.4830051000", \ - "0.1842831000, 0.1894627000, 0.2030960000, 0.2428649000, 0.3510533000, 0.6524219000, 1.4982323000", \ - "0.2134942000, 0.2187805000, 0.2326736000, 0.2723569000, 0.3812585000, 0.6833099000, 1.5330348000", \ - "0.2767469000, 0.2814365000, 0.2955551000, 0.3343506000, 0.4432583000, 0.7466389000, 1.5933176000", \ - "0.3979528000, 0.4029951000, 0.4208920000, 0.4647612000, 0.5809624000, 0.8833232000, 1.7308945000", \ - "0.6089800000, 0.6175745000, 0.6417589000, 0.7025645000, 0.8523728000, 1.1957992000, 2.0470872000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0575554000, 0.0605805000, 0.0691004000, 0.0925988000, 0.1586251000, 0.3442561000, 0.8684707000", \ - "0.0576427000, 0.0606380000, 0.0689536000, 0.0927303000, 0.1584761000, 0.3443620000, 0.8680608000", \ - "0.0573674000, 0.0604000000, 0.0689509000, 0.0923691000, 0.1585739000, 0.3439877000, 0.8675514000", \ - "0.0599300000, 0.0627796000, 0.0707367000, 0.0933468000, 0.1582924000, 0.3441448000, 0.8675381000", \ - "0.0758581000, 0.0788467000, 0.0872384000, 0.1098382000, 0.1682839000, 0.3451579000, 0.8685843000", \ - "0.1146300000, 0.1185688000, 0.1287653000, 0.1545956000, 0.2184952000, 0.3794771000, 0.8706168000", \ - "0.1885389000, 0.1940320000, 0.2082562000, 0.2452468000, 0.3278577000, 0.5085881000, 0.9569705000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1144142000, 0.1208270000, 0.1390101000, 0.1917489000, 0.3385895000, 0.7501653000, 1.9114126000", \ - "0.1145875000, 0.1207890000, 0.1390320000, 0.1916865000, 0.3384553000, 0.7507847000, 1.9053870000", \ - "0.1142566000, 0.1205075000, 0.1393398000, 0.1920321000, 0.3384999000, 0.7489070000, 1.9068571000", \ - "0.1140420000, 0.1210246000, 0.1393259000, 0.1915415000, 0.3384132000, 0.7496070000, 1.9097892000", \ - "0.1176752000, 0.1240193000, 0.1418895000, 0.1928720000, 0.3386913000, 0.7499905000, 1.9091264000", \ - "0.1482071000, 0.1547798000, 0.1728146000, 0.2210891000, 0.3533913000, 0.7503762000, 1.9057771000", \ - "0.2258288000, 0.2330775000, 0.2531194000, 0.3070152000, 0.4441484000, 0.8030375000, 1.9155597000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0779121000, 0.0804319000, 0.0875148000, 0.1056135000, 0.1549190000, 0.2886099000, 0.6594363000", \ - "0.0818014000, 0.0841068000, 0.0909169000, 0.1095809000, 0.1586909000, 0.2922841000, 0.6636789000", \ - "0.0888331000, 0.0914208000, 0.0985318000, 0.1168845000, 0.1661536000, 0.2998844000, 0.6709920000", \ - "0.1029832000, 0.1055433000, 0.1124803000, 0.1309619000, 0.1803626000, 0.3143191000, 0.6856697000", \ - "0.1271460000, 0.1301894000, 0.1375344000, 0.1578698000, 0.2105402000, 0.3453686000, 0.7177897000", \ - "0.1605339000, 0.1639826000, 0.1740447000, 0.1998106000, 0.2638474000, 0.4124352000, 0.7890070000", \ - "0.1776121000, 0.1834283000, 0.1991179000, 0.2385754000, 0.3296012000, 0.5226431000, 0.9460080000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1789357000, 0.1843792000, 0.1983718000, 0.2359599000, 0.3409948000, 0.6321601000, 1.4476842000", \ - "0.1846445000, 0.1895201000, 0.2034285000, 0.2408570000, 0.3456534000, 0.6374285000, 1.4532232000", \ - "0.1976066000, 0.2017601000, 0.2164060000, 0.2542436000, 0.3589384000, 0.6507277000, 1.4663430000", \ - "0.2275338000, 0.2324228000, 0.2447277000, 0.2843176000, 0.3895675000, 0.6811195000, 1.4968901000", \ - "0.2874144000, 0.2920739000, 0.3054593000, 0.3435585000, 0.4495730000, 0.7411936000, 1.5575325000", \ - "0.4034826000, 0.4092005000, 0.4233074000, 0.4666882000, 0.5777315000, 0.8696167000, 1.6867905000", \ - "0.6040872000, 0.6119435000, 0.6327228000, 0.6879160000, 0.8291991000, 1.1581146000, 1.9796800000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0575620000, 0.0605556000, 0.0690128000, 0.0926581000, 0.1585032000, 0.3442407000, 0.8675564000", \ - "0.0576069000, 0.0604886000, 0.0689377000, 0.0926796000, 0.1584495000, 0.3440454000, 0.8679918000", \ - "0.0574685000, 0.0604987000, 0.0689532000, 0.0926209000, 0.1586420000, 0.3443646000, 0.8671929000", \ - "0.0590806000, 0.0619066000, 0.0701702000, 0.0931906000, 0.1583072000, 0.3441145000, 0.8674279000", \ - "0.0686556000, 0.0719314000, 0.0802626000, 0.1029439000, 0.1650091000, 0.3453841000, 0.8684359000", \ - "0.0968441000, 0.1001727000, 0.1085859000, 0.1324772000, 0.1966347000, 0.3680520000, 0.8725299000", \ - "0.1615900000, 0.1657499000, 0.1771642000, 0.2061199000, 0.2763627000, 0.4500575000, 0.9287308000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1319592000, 0.1386206000, 0.1558127000, 0.2064446000, 0.3485766000, 0.7486793000, 1.8675359000", \ - "0.1321309000, 0.1375626000, 0.1554684000, 0.2064667000, 0.3486608000, 0.7468695000, 1.8711628000", \ - "0.1310299000, 0.1383956000, 0.1557712000, 0.2064539000, 0.3486796000, 0.7465225000, 1.8675961000", \ - "0.1309379000, 0.1374771000, 0.1563026000, 0.2064442000, 0.3488362000, 0.7486849000, 1.8669539000", \ - "0.1342162000, 0.1407284000, 0.1578258000, 0.2073534000, 0.3485236000, 0.7474032000, 1.8677289000", \ - "0.1619904000, 0.1681493000, 0.1864357000, 0.2340710000, 0.3644383000, 0.7489770000, 1.8698765000", \ - "0.2343623000, 0.2411975000, 0.2612291000, 0.3128327000, 0.4476143000, 0.8042446000, 1.8753150000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0228628000, 0.0243698000, 0.0287636000, 0.0400161000, 0.0712259000, 0.1583423000, 0.4035713000", \ - "0.0267291000, 0.0282752000, 0.0326503000, 0.0442090000, 0.0756659000, 0.1629010000, 0.4080534000", \ - "0.0353045000, 0.0372398000, 0.0425300000, 0.0541318000, 0.0857220000, 0.1734406000, 0.4185534000", \ - "0.0453721000, 0.0485177000, 0.0563905000, 0.0737827000, 0.1095528000, 0.1972618000, 0.4419445000", \ - "0.0515353000, 0.0562343000, 0.0683358000, 0.0961188000, 0.1509936000, 0.2524491000, 0.4974011000", \ - "0.0420613000, 0.0495576000, 0.0676598000, 0.1106520000, 0.1953875000, 0.3509191000, 0.6251089000", \ - "-0.013524200, -0.002595800, 0.0241975000, 0.0899586000, 0.2233417000, 0.4613413000, 0.8736000000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1136998000, 0.1186065000, 0.1340197000, 0.1737656000, 0.2804877000, 0.5744935000, 1.3979263000", \ - "0.1173851000, 0.1229418000, 0.1373077000, 0.1769244000, 0.2847414000, 0.5796778000, 1.4024243000", \ - "0.1270502000, 0.1316467000, 0.1468616000, 0.1860706000, 0.2948323000, 0.5906068000, 1.4142829000", \ - "0.1540890000, 0.1595307000, 0.1735387000, 0.2115879000, 0.3200727000, 0.6169341000, 1.4419161000", \ - "0.2212308000, 0.2271368000, 0.2421603000, 0.2799719000, 0.3846605000, 0.6833645000, 1.5107473000", \ - "0.3518417000, 0.3595153000, 0.3800608000, 0.4307447000, 0.5479623000, 0.8387391000, 1.6628048000", \ - "0.5616945000, 0.5725486000, 0.6032336000, 0.6810676000, 0.8573455000, 1.2105578000, 2.0276452000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0276447000, 0.0295649000, 0.0349438000, 0.0501059000, 0.0924258000, 0.2125546000, 0.5484127000", \ - "0.0275705000, 0.0295002000, 0.0349362000, 0.0500720000, 0.0925305000, 0.2116680000, 0.5484060000", \ - "0.0322993000, 0.0337509000, 0.0379314000, 0.0512665000, 0.0924049000, 0.2126024000, 0.5482601000", \ - "0.0470554000, 0.0486727000, 0.0532219000, 0.0646630000, 0.0985931000, 0.2119290000, 0.5484762000", \ - "0.0762059000, 0.0781390000, 0.0835346000, 0.0980672000, 0.1334511000, 0.2270089000, 0.5480060000", \ - "0.1291810000, 0.1318989000, 0.1399458000, 0.1597273000, 0.2083484000, 0.3094888000, 0.5764449000", \ - "0.2233058000, 0.2272196000, 0.2400696000, 0.2682402000, 0.3377887000, 0.4828309000, 0.7606898000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1079814000, 0.1147154000, 0.1324694000, 0.1825834000, 0.3254048000, 0.7235146000, 1.8475274000", \ - "0.1080164000, 0.1140606000, 0.1323451000, 0.1826349000, 0.3245940000, 0.7234882000, 1.8444714000", \ - "0.1078102000, 0.1144344000, 0.1324612000, 0.1828586000, 0.3246151000, 0.7245126000, 1.8454874000", \ - "0.1061760000, 0.1126199000, 0.1314782000, 0.1824914000, 0.3244301000, 0.7235148000, 1.8453477000", \ - "0.1227137000, 0.1276724000, 0.1423220000, 0.1877989000, 0.3239465000, 0.7233898000, 1.8537267000", \ - "0.1755682000, 0.1828397000, 0.2016059000, 0.2484398000, 0.3601431000, 0.7240319000, 1.8447206000", \ - "0.2677529000, 0.2785008000, 0.3060349000, 0.3724120000, 0.5159935000, 0.8248174000, 1.8530910000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0286764000, 0.0301934000, 0.0342822000, 0.0455736000, 0.0768841000, 0.1638776000, 0.4088483000", \ - "0.0326900000, 0.0342208000, 0.0385830000, 0.0499794000, 0.0813320000, 0.1686067000, 0.4135846000", \ - "0.0402271000, 0.0419776000, 0.0466441000, 0.0585483000, 0.0901436000, 0.1775979000, 0.4227503000", \ - "0.0506531000, 0.0532617000, 0.0595138000, 0.0745228000, 0.1090853000, 0.1970882000, 0.4427255000", \ - "0.0604525000, 0.0640546000, 0.0736809000, 0.0961773000, 0.1427820000, 0.2413537000, 0.4877563000", \ - "0.0567370000, 0.0628141000, 0.0786279000, 0.1139775000, 0.1865996000, 0.3197594000, 0.5904712000", \ - "0.0094019000, 0.0186559000, 0.0437334000, 0.1017818000, 0.2172943000, 0.4244050000, 0.7825129000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1428129000, 0.1482367000, 0.1623572000, 0.2000247000, 0.3055006000, 0.5963472000, 1.4131912000", \ - "0.1463693000, 0.1510980000, 0.1654645000, 0.2038497000, 0.3092663000, 0.6010220000, 1.4167282000", \ - "0.1564045000, 0.1614614000, 0.1745699000, 0.2133343000, 0.3194096000, 0.6116207000, 1.4285777000", \ - "0.1829183000, 0.1879877000, 0.2020005000, 0.2403837000, 0.3457387000, 0.6384091000, 1.4564789000", \ - "0.2504213000, 0.2553519000, 0.2684888000, 0.3063798000, 0.4120352000, 0.7045515000, 1.5239653000", \ - "0.3895200000, 0.3958117000, 0.4136028000, 0.4587492000, 0.5692063000, 0.8553145000, 1.6720798000", \ - "0.6122353000, 0.6221197000, 0.6488952000, 0.7176376000, 0.8821526000, 1.2265209000, 2.0311315000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0276202000, 0.0295423000, 0.0349271000, 0.0500310000, 0.0923760000, 0.2118897000, 0.5483888000", \ - "0.0276569000, 0.0295619000, 0.0349383000, 0.0500512000, 0.0924142000, 0.2118188000, 0.5485418000", \ - "0.0297162000, 0.0314112000, 0.0363381000, 0.0506109000, 0.0924344000, 0.2117120000, 0.5486273000", \ - "0.0396062000, 0.0411461000, 0.0455562000, 0.0580010000, 0.0956675000, 0.2118936000, 0.5485445000", \ - "0.0618745000, 0.0635622000, 0.0682401000, 0.0812287000, 0.1168194000, 0.2209088000, 0.5480907000", \ - "0.1066810000, 0.1088556000, 0.1144169000, 0.1303548000, 0.1712976000, 0.2716584000, 0.5668517000", \ - "0.1921372000, 0.1946776000, 0.2020090000, 0.2230917000, 0.2765496000, 0.3950065000, 0.6801013000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.1318296000, 0.1375300000, 0.1557944000, 0.2064068000, 0.3484968000, 0.7483363000, 1.8704487000", \ - "0.1309791000, 0.1381116000, 0.1554703000, 0.2064546000, 0.3488247000, 0.7467036000, 1.8674005000", \ - "0.1309437000, 0.1374439000, 0.1562095000, 0.2071143000, 0.3486143000, 0.7467579000, 1.8708943000", \ - "0.1306280000, 0.1368664000, 0.1553304000, 0.2062295000, 0.3486391000, 0.7473056000, 1.8706230000", \ - "0.1395991000, 0.1451272000, 0.1616725000, 0.2091450000, 0.3479345000, 0.7464853000, 1.8761086000", \ - "0.1959397000, 0.2027786000, 0.2221442000, 0.2647304000, 0.3843588000, 0.7501039000, 1.8724284000", \ - "0.2908698000, 0.3006607000, 0.3267835000, 0.3904190000, 0.5314923000, 0.8469735000, 1.8730781000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41o_1") { - leakage_power () { - value : 0.0027220000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0109879000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0109964000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0109930000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0110186000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0109933000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0110166000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0110062000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0115128000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0109985000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0110208000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0110108000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0113862000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0110158000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0113487000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027220000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0112406000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0006570000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0034383000; - when : "A1&A2&A3&A4&!B1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__a41o"; - cell_leakage_power : 0.0066084930; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044244000, 0.0044257000, 0.0044288000, 0.0044286000, 0.0044282000, 0.0044272000, 0.0044249000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003493900, -0.003496200, -0.003501400, -0.003494800, -0.003479600, -0.003444700, -0.003364100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023740000; - } - pin ("A2") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043182000, 0.0043180000, 0.0043176000, 0.0043336000, 0.0043706000, 0.0044558000, 0.0046523000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003866800, -0.003865400, -0.003862000, -0.003860500, -0.003857000, -0.003849000, -0.003830500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024450000; - } - pin ("A3") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038976000, 0.0039003000, 0.0039063000, 0.0039059000, 0.0039050000, 0.0039029000, 0.0038981000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003901600, -0.003901500, -0.003901100, -0.003900400, -0.003898600, -0.003894700, -0.003885500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024370000; - } - pin ("A4") { - capacitance : 0.0023120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040277000, 0.0040227000, 0.0040112000, 0.0040121000, 0.0040143000, 0.0040193000, 0.0040308000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003999600, -0.003999900, -0.004000700, -0.004001200, -0.004002300, -0.004004800, -0.004010500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024290000; - } - pin ("B1") { - capacitance : 0.0024140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026218000, 0.0026120000, 0.0025895000, 0.0026098000, 0.0026565000, 0.0027643000, 0.0030127000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001699100, -0.001704700, -0.001717700, -0.001720200, -0.001726000, -0.001739300, -0.001770000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026030000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3&A4) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0113389000, 0.0103988000, 0.0078976000, -7.72000e-05, -0.023497200, -0.086622500, -0.253042300", \ - "0.0112058000, 0.0102753000, 0.0077588000, -0.000207500, -0.023630200, -0.086720500, -0.253135600", \ - "0.0109645000, 0.0100249000, 0.0075196000, -0.000467200, -0.023875500, -0.086989900, -0.253364200", \ - "0.0107303000, 0.0097756000, 0.0072210000, -0.000776700, -0.024153000, -0.087215400, -0.253634900", \ - "0.0104695000, 0.0094999000, 0.0069347000, -0.001071800, -0.024469200, -0.087520900, -0.253869700", \ - "0.0115748000, 0.0102469000, 0.0068629000, -0.001554200, -0.024617300, -0.087613800, -0.253955900", \ - "0.0129614000, 0.0115785000, 0.0080860000, -0.000965400, -0.024792500, -0.087526700, -0.253783800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0137924000, 0.0152215000, 0.0189964000, 0.0284022000, 0.0525568000, 0.1154753000, 0.2799414000", \ - "0.0137015000, 0.0151172000, 0.0188391000, 0.0282982000, 0.0524391000, 0.1152253000, 0.2810719000", \ - "0.0135210000, 0.0149571000, 0.0186590000, 0.0281385000, 0.0522402000, 0.1156760000, 0.2810527000", \ - "0.0133390000, 0.0147782000, 0.0185059000, 0.0278796000, 0.0520188000, 0.1148544000, 0.2808274000", \ - "0.0132702000, 0.0146777000, 0.0183191000, 0.0275284000, 0.0516105000, 0.1145923000, 0.2791992000", \ - "0.0137781000, 0.0151247000, 0.0185683000, 0.0275009000, 0.0517574000, 0.1142209000, 0.2806814000", \ - "0.0153874000, 0.0167206000, 0.0201858000, 0.0291647000, 0.0527378000, 0.1158564000, 0.2804743000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0139115000, 0.0129481000, 0.0104353000, 0.0025334000, -0.020737000, -0.083734100, -0.250055500", \ - "0.0138296000, 0.0128570000, 0.0103324000, 0.0024375000, -0.020807900, -0.083826100, -0.250134100", \ - "0.0135478000, 0.0125990000, 0.0100808000, 0.0022026000, -0.021060300, -0.084050200, -0.250344000", \ - "0.0133218000, 0.0123573000, 0.0098404000, 0.0019387000, -0.021335000, -0.084311700, -0.250614700", \ - "0.0130737000, 0.0121421000, 0.0095332000, 0.0015951000, -0.021662900, -0.084604900, -0.250886600", \ - "0.0134406000, 0.0121142000, 0.0087307000, 0.0012769000, -0.021895800, -0.084803200, -0.251056400", \ - "0.0154635000, 0.0140693000, 0.0105788000, 0.0015052000, -0.022325200, -0.085035700, -0.251189700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0141388000, 0.0155783000, 0.0193455000, 0.0287508000, 0.0529123000, 0.1158026000, 0.2818302000", \ - "0.0140547000, 0.0154804000, 0.0192419000, 0.0286512000, 0.0528102000, 0.1156256000, 0.2815570000", \ - "0.0139309000, 0.0153796000, 0.0190910000, 0.0285143000, 0.0526711000, 0.1155628000, 0.2801298000", \ - "0.0137319000, 0.0151692000, 0.0188950000, 0.0282927000, 0.0524459000, 0.1152825000, 0.2812773000", \ - "0.0136247000, 0.0150539000, 0.0187119000, 0.0279686000, 0.0521458000, 0.1151002000, 0.2796961000", \ - "0.0140000000, 0.0153047000, 0.0188244000, 0.0278115000, 0.0520377000, 0.1145573000, 0.2807967000", \ - "0.0150168000, 0.0163201000, 0.0197793000, 0.0288585000, 0.0527662000, 0.1157745000, 0.2787528000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0167157000, 0.0157435000, 0.0132408000, 0.0054520000, -0.017636100, -0.080514100, -0.246768800", \ - "0.0166310000, 0.0156790000, 0.0131747000, 0.0053482000, -0.017778100, -0.080660000, -0.246868200", \ - "0.0164390000, 0.0155683000, 0.0130206000, 0.0051670000, -0.017975400, -0.080837800, -0.247046200", \ - "0.0162387000, 0.0153462000, 0.0128137000, 0.0049535000, -0.018189300, -0.081045300, -0.247240600", \ - "0.0160402000, 0.0150748000, 0.0125511000, 0.0047037000, -0.018435000, -0.081261200, -0.247449400", \ - "0.0159367000, 0.0146159000, 0.0121060000, 0.0044813000, -0.018607300, -0.081361100, -0.247528800", \ - "0.0189238000, 0.0175358000, 0.0140464000, 0.0049697000, -0.018862900, -0.081454000, -0.247512200"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0141887000, 0.0156296000, 0.0193356000, 0.0287390000, 0.0529573000, 0.1157888000, 0.2803499000", \ - "0.0140963000, 0.0155415000, 0.0192531000, 0.0286633000, 0.0528410000, 0.1156593000, 0.2802803000", \ - "0.0139444000, 0.0153612000, 0.0190731000, 0.0285340000, 0.0526873000, 0.1154688000, 0.2801896000", \ - "0.0137217000, 0.0151564000, 0.0188979000, 0.0282979000, 0.0524357000, 0.1153288000, 0.2813807000", \ - "0.0136020000, 0.0150506000, 0.0186557000, 0.0280490000, 0.0522088000, 0.1151082000, 0.2797305000", \ - "0.0139707000, 0.0153251000, 0.0187904000, 0.0278063000, 0.0520149000, 0.1145936000, 0.2809283000", \ - "0.0146351000, 0.0159748000, 0.0193627000, 0.0285884000, 0.0525122000, 0.1154923000, 0.2789242000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0187890000, 0.0178766000, 0.0153859000, 0.0076315000, -0.015378400, -0.078128100, -0.244246100", \ - "0.0187121000, 0.0177425000, 0.0152442000, 0.0075590000, -0.015430600, -0.078239800, -0.244337400", \ - "0.0185841000, 0.0176235000, 0.0152227000, 0.0074440000, -0.015585600, -0.078272500, -0.244430900", \ - "0.0185283000, 0.0176121000, 0.0151348000, 0.0073098000, -0.015670200, -0.078427000, -0.244513500", \ - "0.0183403000, 0.0173706000, 0.0148584000, 0.0071043000, -0.015893400, -0.078601000, -0.244684300", \ - "0.0184556000, 0.0171115000, 0.0144902000, 0.0069722000, -0.015951000, -0.078646400, -0.244737300", \ - "0.0216138000, 0.0202443000, 0.0167307000, 0.0076495000, -0.016199500, -0.078745000, -0.244700200"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0141741000, 0.0155977000, 0.0193634000, 0.0287723000, 0.0529463000, 0.1158441000, 0.2803340000", \ - "0.0140905000, 0.0155322000, 0.0192647000, 0.0286690000, 0.0528618000, 0.1156967000, 0.2802666000", \ - "0.0139193000, 0.0153417000, 0.0191096000, 0.0285179000, 0.0526543000, 0.1156133000, 0.2800951000", \ - "0.0136986000, 0.0151374000, 0.0188788000, 0.0282893000, 0.0524282000, 0.1153029000, 0.2812811000", \ - "0.0134835000, 0.0149302000, 0.0185921000, 0.0280264000, 0.0521319000, 0.1150882000, 0.2796230000", \ - "0.0140343000, 0.0153897000, 0.0188833000, 0.0278193000, 0.0520211000, 0.1146091000, 0.2794758000", \ - "0.0145689000, 0.0158776000, 0.0195099000, 0.0285481000, 0.0525231000, 0.1154567000, 0.2803424000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0175454000, 0.0165976000, 0.0141351000, 0.0063831000, -0.016655000, -0.079376100, -0.245456600", \ - "0.0173145000, 0.0163712000, 0.0139164000, 0.0061602000, -0.016868100, -0.079584300, -0.245566500", \ - "0.0170973000, 0.0161377000, 0.0136866000, 0.0059517000, -0.016998200, -0.079750400, -0.245861000", \ - "0.0168493000, 0.0158983000, 0.0134990000, 0.0057403000, -0.017254300, -0.079978300, -0.246078600", \ - "0.0167638000, 0.0158137000, 0.0132996000, 0.0055903000, -0.017489300, -0.080183900, -0.246244800", \ - "0.0182702000, 0.0169182000, 0.0136089000, 0.0061083000, -0.016942800, -0.079596000, -0.245599500", \ - "0.0219055000, 0.0204874000, 0.0168614000, 0.0077075000, -0.015911200, -0.078536900, -0.244593000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0084622000, 0.0098720000, 0.0133956000, 0.0223573000, 0.0459363000, 0.1087541000, 0.2728602000", \ - "0.0083612000, 0.0097653000, 0.0132838000, 0.0222873000, 0.0459279000, 0.1089979000, 0.2729248000", \ - "0.0081527000, 0.0095573000, 0.0130853000, 0.0221515000, 0.0458870000, 0.1088731000, 0.2727136000", \ - "0.0078880000, 0.0092641000, 0.0127743000, 0.0218798000, 0.0456694000, 0.1088739000, 0.2729390000", \ - "0.0079191000, 0.0092468000, 0.0126466000, 0.0218708000, 0.0456155000, 0.1077502000, 0.2746387000", \ - "0.0085781000, 0.0098926000, 0.0133378000, 0.0224276000, 0.0461971000, 0.1081006000, 0.2747685000", \ - "0.0108266000, 0.0120391000, 0.0157874000, 0.0248244000, 0.0486277000, 0.1113141000, 0.2738778000"); - } - } - max_capacitance : 0.1657200000; - max_transition : 1.5041780000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1409252000, 0.1475898000, 0.1615119000, 0.1894297000, 0.2464150000, 0.3771552000, 0.7123209000", \ - "0.1459884000, 0.1526387000, 0.1665663000, 0.1944711000, 0.2514819000, 0.3822388000, 0.7169884000", \ - "0.1585110000, 0.1650240000, 0.1790845000, 0.2068444000, 0.2639065000, 0.3946181000, 0.7290927000", \ - "0.1879588000, 0.1945064000, 0.2084704000, 0.2363567000, 0.2933208000, 0.4241125000, 0.7594467000", \ - "0.2515047000, 0.2580626000, 0.2721792000, 0.3001940000, 0.3573149000, 0.4880665000, 0.8226069000", \ - "0.3631385000, 0.3710507000, 0.3872725000, 0.4184120000, 0.4797175000, 0.6128368000, 0.9473945000", \ - "0.5427002000, 0.5524638000, 0.5725794000, 0.6110145000, 0.6813045000, 0.8208104000, 1.1579644000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1073293000, 0.1160195000, 0.1349265000, 0.1760054000, 0.2726878000, 0.5191153000, 1.1651464000", \ - "0.1108459000, 0.1195166000, 0.1384806000, 0.1795829000, 0.2761343000, 0.5246342000, 1.1708955000", \ - "0.1193125000, 0.1279711000, 0.1469256000, 0.1880929000, 0.2846604000, 0.5324973000, 1.1796883000", \ - "0.1399967000, 0.1486616000, 0.1675407000, 0.2084744000, 0.3050572000, 0.5521754000, 1.1992032000", \ - "0.1786789000, 0.1872592000, 0.2062502000, 0.2475410000, 0.3443954000, 0.5913340000, 1.2357708000", \ - "0.2255030000, 0.2348556000, 0.2542365000, 0.2957462000, 0.3928231000, 0.6407301000, 1.2874541000", \ - "0.2559966000, 0.2680994000, 0.2919253000, 0.3355600000, 0.4322262000, 0.6795773000, 1.3254213000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0225348000, 0.0273312000, 0.0382239000, 0.0633991000, 0.1230390000, 0.2842654000, 0.7196205000", \ - "0.0225126000, 0.0271498000, 0.0382478000, 0.0633813000, 0.1230447000, 0.2833877000, 0.7300325000", \ - "0.0225193000, 0.0273477000, 0.0382715000, 0.0631978000, 0.1230814000, 0.2856458000, 0.7239314000", \ - "0.0225311000, 0.0273736000, 0.0385547000, 0.0635395000, 0.1228209000, 0.2852580000, 0.7261220000", \ - "0.0237077000, 0.0285014000, 0.0394223000, 0.0640442000, 0.1235443000, 0.2843700000, 0.7239144000", \ - "0.0293917000, 0.0345637000, 0.0461061000, 0.0715519000, 0.1297380000, 0.2873710000, 0.7204278000", \ - "0.0416190000, 0.0478452000, 0.0614430000, 0.0885396000, 0.1478795000, 0.2967442000, 0.7245631000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0294357000, 0.0371448000, 0.0556078000, 0.1027501000, 0.2308711000, 0.5789636000, 1.4987924000", \ - "0.0296279000, 0.0372409000, 0.0555877000, 0.1027675000, 0.2313020000, 0.5800823000, 1.4965473000", \ - "0.0295727000, 0.0370875000, 0.0555781000, 0.1025396000, 0.2313882000, 0.5796557000, 1.4972101000", \ - "0.0293141000, 0.0369467000, 0.0554709000, 0.1027151000, 0.2313734000, 0.5804899000, 1.5002285000", \ - "0.0304104000, 0.0379519000, 0.0565954000, 0.1041154000, 0.2317600000, 0.5793945000, 1.4953864000", \ - "0.0360058000, 0.0428322000, 0.0600250000, 0.1056458000, 0.2336982000, 0.5800070000, 1.4995095000", \ - "0.0479561000, 0.0555393000, 0.0720028000, 0.1132488000, 0.2351983000, 0.5824286000, 1.4969299000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1694908000, 0.1764844000, 0.1911681000, 0.2200387000, 0.2785547000, 0.4104508000, 0.7460424000", \ - "0.1748281000, 0.1818742000, 0.1965670000, 0.2253649000, 0.2838780000, 0.4158814000, 0.7515470000", \ - "0.1874960000, 0.1945030000, 0.2089532000, 0.2380545000, 0.2966303000, 0.4285206000, 0.7640791000", \ - "0.2165377000, 0.2235398000, 0.2381934000, 0.2670454000, 0.3255833000, 0.4575803000, 0.7932488000", \ - "0.2807552000, 0.2877726000, 0.3024311000, 0.3314108000, 0.3900062000, 0.5221210000, 0.8577353000", \ - "0.4020135000, 0.4098468000, 0.4261800000, 0.4573396000, 0.5187091000, 0.6523460000, 0.9880059000", \ - "0.6042148000, 0.6139098000, 0.6338781000, 0.6712492000, 0.7404293000, 0.8799795000, 1.2170420000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1179507000, 0.1266725000, 0.1455873000, 0.1866961000, 0.2833919000, 0.5298385000, 1.1760465000", \ - "0.1216699000, 0.1303691000, 0.1493113000, 0.1904001000, 0.2870933000, 0.5343698000, 1.1813291000", \ - "0.1299997000, 0.1387656000, 0.1576046000, 0.1986470000, 0.2952683000, 0.5423513000, 1.1874522000", \ - "0.1496507000, 0.1582977000, 0.1772030000, 0.2181880000, 0.3148295000, 0.5620721000, 1.2087232000", \ - "0.1877544000, 0.1966248000, 0.2159109000, 0.2572478000, 0.3540164000, 0.6012006000, 1.2461132000", \ - "0.2385842000, 0.2482764000, 0.2689408000, 0.3112016000, 0.4085257000, 0.6559228000, 1.3044706000", \ - "0.2773350000, 0.2896816000, 0.3145168000, 0.3604495000, 0.4585001000, 0.7059183000, 1.3516048000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0250476000, 0.0299004000, 0.0408397000, 0.0663565000, 0.1263579000, 0.2861071000, 0.7290905000", \ - "0.0248835000, 0.0300508000, 0.0408036000, 0.0661844000, 0.1265620000, 0.2868080000, 0.7276793000", \ - "0.0250283000, 0.0298286000, 0.0414318000, 0.0664594000, 0.1260003000, 0.2862610000, 0.7287469000", \ - "0.0249699000, 0.0298527000, 0.0408351000, 0.0661313000, 0.1264386000, 0.2867533000, 0.7276701000", \ - "0.0254018000, 0.0302936000, 0.0409289000, 0.0661027000, 0.1263139000, 0.2858994000, 0.7293985000", \ - "0.0299855000, 0.0352252000, 0.0472834000, 0.0720340000, 0.1308323000, 0.2884832000, 0.7297927000", \ - "0.0412239000, 0.0472717000, 0.0601381000, 0.0877933000, 0.1454483000, 0.2967168000, 0.7263001000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0294800000, 0.0371185000, 0.0556042000, 0.1027311000, 0.2314511000, 0.5792904000, 1.4991677000", \ - "0.0296159000, 0.0371068000, 0.0555778000, 0.1027202000, 0.2314851000, 0.5805559000, 1.4995489000", \ - "0.0293533000, 0.0370582000, 0.0555340000, 0.1027672000, 0.2314939000, 0.5798541000, 1.4980509000", \ - "0.0294853000, 0.0369585000, 0.0554257000, 0.1026355000, 0.2314522000, 0.5805204000, 1.5003616000", \ - "0.0311256000, 0.0387974000, 0.0571064000, 0.1039636000, 0.2317387000, 0.5798366000, 1.4970636000", \ - "0.0363948000, 0.0435689000, 0.0612070000, 0.1063884000, 0.2332991000, 0.5797467000, 1.4996980000", \ - "0.0480576000, 0.0562184000, 0.0743463000, 0.1148148000, 0.2356529000, 0.5818465000, 1.4939541000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1880322000, 0.1952591000, 0.2103209000, 0.2396435000, 0.2989094000, 0.4316086000, 0.7672287000", \ - "0.1933353000, 0.2005378000, 0.2155680000, 0.2451992000, 0.3040646000, 0.4367397000, 0.7722590000", \ - "0.2062231000, 0.2132795000, 0.2283315000, 0.2579335000, 0.3170291000, 0.4498238000, 0.7853380000", \ - "0.2358848000, 0.2429516000, 0.2580264000, 0.2874117000, 0.3467117000, 0.4794963000, 0.8149451000", \ - "0.2993993000, 0.3066004000, 0.3215667000, 0.3511200000, 0.4103704000, 0.5431526000, 0.8792785000", \ - "0.4259041000, 0.4338123000, 0.4500813000, 0.4816004000, 0.5429661000, 0.6765396000, 1.0127932000", \ - "0.6399164000, 0.6493667000, 0.6689854000, 0.7057261000, 0.7737768000, 0.9130723000, 1.2502687000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1253497000, 0.1340628000, 0.1529293000, 0.1939777000, 0.2906753000, 0.5375255000, 1.1819177000", \ - "0.1291699000, 0.1379265000, 0.1567654000, 0.1978285000, 0.2944331000, 0.5411183000, 1.1859567000", \ - "0.1371175000, 0.1457888000, 0.1647015000, 0.2058251000, 0.3023884000, 0.5508141000, 1.1949099000", \ - "0.1539614000, 0.1626097000, 0.1815338000, 0.2225569000, 0.3192857000, 0.5659710000, 1.2124306000", \ - "0.1870668000, 0.1960030000, 0.2154534000, 0.2568099000, 0.3535391000, 0.6006163000, 1.2461253000", \ - "0.2346403000, 0.2447124000, 0.2654521000, 0.3083784000, 0.4058311000, 0.6530063000, 1.2992230000", \ - "0.2723676000, 0.2850504000, 0.3100571000, 0.3576251000, 0.4568384000, 0.7051105000, 1.3495620000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0262585000, 0.0311284000, 0.0424687000, 0.0677074000, 0.1272051000, 0.2865095000, 0.7305926000", \ - "0.0262986000, 0.0316233000, 0.0422836000, 0.0674139000, 0.1275973000, 0.2873230000, 0.7257535000", \ - "0.0265731000, 0.0317566000, 0.0423287000, 0.0678054000, 0.1275497000, 0.2868371000, 0.7237442000", \ - "0.0265908000, 0.0317417000, 0.0422845000, 0.0673261000, 0.1275668000, 0.2870257000, 0.7249570000", \ - "0.0262808000, 0.0313372000, 0.0427736000, 0.0669091000, 0.1274681000, 0.2873590000, 0.7301729000", \ - "0.0304138000, 0.0356208000, 0.0476183000, 0.0716923000, 0.1307631000, 0.2889206000, 0.7300899000", \ - "0.0406596000, 0.0466780000, 0.0596095000, 0.0851322000, 0.1445377000, 0.2963268000, 0.7281845000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0294676000, 0.0371349000, 0.0556003000, 0.1026351000, 0.2314530000, 0.5792687000, 1.4956546000", \ - "0.0293602000, 0.0370507000, 0.0555465000, 0.1027958000, 0.2314939000, 0.5791123000, 1.4954413000", \ - "0.0295551000, 0.0372983000, 0.0555504000, 0.1027705000, 0.2313622000, 0.5800684000, 1.4994975000", \ - "0.0295310000, 0.0369559000, 0.0555145000, 0.1026841000, 0.2309105000, 0.5798392000, 1.4999449000", \ - "0.0309294000, 0.0388765000, 0.0572057000, 0.1038843000, 0.2316680000, 0.5801348000, 1.4999356000", \ - "0.0358426000, 0.0438651000, 0.0619225000, 0.1069732000, 0.2333547000, 0.5787984000, 1.4998396000", \ - "0.0471688000, 0.0560650000, 0.0739282000, 0.1164309000, 0.2366040000, 0.5802329000, 1.4958996000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1972676000, 0.2045603000, 0.2198238000, 0.2496784000, 0.3087849000, 0.4420299000, 0.7785132000", \ - "0.2024933000, 0.2097467000, 0.2250177000, 0.2544346000, 0.3142565000, 0.4472353000, 0.7838266000", \ - "0.2155579000, 0.2228653000, 0.2378768000, 0.2676830000, 0.3273913000, 0.4605619000, 0.7968867000", \ - "0.2443545000, 0.2516332000, 0.2669137000, 0.2967520000, 0.3561647000, 0.4894390000, 0.8258312000", \ - "0.3044815000, 0.3117646000, 0.3269659000, 0.3568155000, 0.4163117000, 0.5496085000, 0.8863317000", \ - "0.4229539000, 0.4308569000, 0.4471707000, 0.4787205000, 0.5394599000, 0.6735056000, 1.0103113000", \ - "0.6203056000, 0.6298004000, 0.6489955000, 0.6852619000, 0.7528499000, 0.8920349000, 1.2294566000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1296017000, 0.1383034000, 0.1572454000, 0.1983378000, 0.2950671000, 0.5414406000, 1.1875319000", \ - "0.1336639000, 0.1424055000, 0.1612640000, 0.2022965000, 0.2989917000, 0.5459060000, 1.1905253000", \ - "0.1417520000, 0.1504421000, 0.1693668000, 0.2104808000, 0.3072264000, 0.5535021000, 1.1994632000", \ - "0.1576314000, 0.1662845000, 0.1852361000, 0.2263014000, 0.3230298000, 0.5701282000, 1.2168843000", \ - "0.1875381000, 0.1964918000, 0.2158653000, 0.2571854000, 0.3540369000, 0.6005552000, 1.2467360000", \ - "0.2332722000, 0.2429636000, 0.2637387000, 0.3067576000, 0.4042238000, 0.6508743000, 1.2972198000", \ - "0.2787672000, 0.2909827000, 0.3156765000, 0.3631668000, 0.4629954000, 0.7108487000, 1.3550796000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0273026000, 0.0326742000, 0.0432160000, 0.0681640000, 0.1281945000, 0.2872699000, 0.7225603000", \ - "0.0274217000, 0.0321277000, 0.0435647000, 0.0684974000, 0.1280325000, 0.2882637000, 0.7281643000", \ - "0.0270851000, 0.0319754000, 0.0437783000, 0.0680759000, 0.1281342000, 0.2869332000, 0.7304601000", \ - "0.0271206000, 0.0326281000, 0.0431506000, 0.0685731000, 0.1282244000, 0.2874042000, 0.7312168000", \ - "0.0272775000, 0.0320032000, 0.0434496000, 0.0685558000, 0.1280850000, 0.2885774000, 0.7292477000", \ - "0.0307935000, 0.0366764000, 0.0473388000, 0.0723100000, 0.1314177000, 0.2892177000, 0.7309687000", \ - "0.0402725000, 0.0460181000, 0.0581559000, 0.0841923000, 0.1432917000, 0.2963797000, 0.7271378000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0296543000, 0.0371143000, 0.0556051000, 0.1027312000, 0.2313427000, 0.5790813000, 1.4989708000", \ - "0.0294583000, 0.0370516000, 0.0555407000, 0.1025523000, 0.2314561000, 0.5794449000, 1.4964582000", \ - "0.0296388000, 0.0370976000, 0.0555877000, 0.1027317000, 0.2311680000, 0.5787967000, 1.4984264000", \ - "0.0295159000, 0.0370021000, 0.0555066000, 0.1026856000, 0.2312533000, 0.5804530000, 1.5003843000", \ - "0.0309754000, 0.0386139000, 0.0568254000, 0.1034571000, 0.2310753000, 0.5791250000, 1.4987643000", \ - "0.0348834000, 0.0430642000, 0.0613412000, 0.1068592000, 0.2329449000, 0.5779598000, 1.5000050000", \ - "0.0449831000, 0.0536749000, 0.0732149000, 0.1161059000, 0.2370198000, 0.5806817000, 1.4958265000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.1681932000, 0.1755355000, 0.1907993000, 0.2206230000, 0.2801669000, 0.4133581000, 0.7493332000", \ - "0.1714280000, 0.1787201000, 0.1939725000, 0.2238520000, 0.2834517000, 0.4165847000, 0.7530718000", \ - "0.1817174000, 0.1890309000, 0.2042570000, 0.2339334000, 0.2936336000, 0.4268246000, 0.7631391000", \ - "0.2082160000, 0.2155311000, 0.2306803000, 0.2605917000, 0.3202429000, 0.4534709000, 0.7896507000", \ - "0.2742519000, 0.2815191000, 0.2965772000, 0.3261006000, 0.3856680000, 0.5188945000, 0.8555154000", \ - "0.4088897000, 0.4170908000, 0.4334710000, 0.4642592000, 0.5251128000, 0.6595811000, 0.9962350000", \ - "0.6209249000, 0.6313334000, 0.6514796000, 0.6874687000, 0.7521888000, 0.8882922000, 1.2273501000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0524699000, 0.0597824000, 0.0764017000, 0.1135721000, 0.2064277000, 0.4528914000, 1.0960104000", \ - "0.0571199000, 0.0644040000, 0.0810835000, 0.1183397000, 0.2113243000, 0.4570103000, 1.0990489000", \ - "0.0677166000, 0.0749789000, 0.0917553000, 0.1292923000, 0.2223939000, 0.4691602000, 1.1108824000", \ - "0.0868426000, 0.0946511000, 0.1120622000, 0.1499615000, 0.2435299000, 0.4888285000, 1.1311364000", \ - "0.1103451000, 0.1201453000, 0.1401083000, 0.1798288000, 0.2738751000, 0.5184604000, 1.1650748000", \ - "0.1293868000, 0.1429809000, 0.1694622000, 0.2145151000, 0.3097162000, 0.5545183000, 1.2000640000", \ - "0.1218076000, 0.1404016000, 0.1774693000, 0.2355231000, 0.3362745000, 0.5813386000, 1.2257737000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0274990000, 0.0320515000, 0.0432118000, 0.0683512000, 0.1276290000, 0.2879343000, 0.7272797000", \ - "0.0272719000, 0.0320621000, 0.0431948000, 0.0680354000, 0.1278243000, 0.2882424000, 0.7304364000", \ - "0.0270762000, 0.0319829000, 0.0433537000, 0.0681850000, 0.1280518000, 0.2866777000, 0.7318878000", \ - "0.0272199000, 0.0323189000, 0.0437273000, 0.0676401000, 0.1277180000, 0.2875801000, 0.7239204000", \ - "0.0268226000, 0.0319282000, 0.0429012000, 0.0682879000, 0.1281028000, 0.2885067000, 0.7306012000", \ - "0.0337788000, 0.0383221000, 0.0486262000, 0.0725674000, 0.1316102000, 0.2895508000, 0.7309088000", \ - "0.0481069000, 0.0535962000, 0.0642497000, 0.0854451000, 0.1394805000, 0.2942925000, 0.7284610000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0226295000, 0.0305826000, 0.0493555000, 0.0967722000, 0.2268048000, 0.5787040000, 1.4963569000", \ - "0.0226377000, 0.0305917000, 0.0493724000, 0.0967574000, 0.2272205000, 0.5781934000, 1.4947800000", \ - "0.0227691000, 0.0307173000, 0.0494464000, 0.0968233000, 0.2272525000, 0.5784607000, 1.4929221000", \ - "0.0258168000, 0.0333501000, 0.0510172000, 0.0971448000, 0.2271824000, 0.5778589000, 1.4965147000", \ - "0.0341226000, 0.0415615000, 0.0577960000, 0.1007419000, 0.2277860000, 0.5773397000, 1.5041784000", \ - "0.0488236000, 0.0581340000, 0.0739499000, 0.1101319000, 0.2304991000, 0.5756852000, 1.5032025000", \ - "0.0703621000, 0.0831738000, 0.1039349000, 0.1349291000, 0.2388163000, 0.5792488000, 1.4909466000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41o_2") { - leakage_power () { - value : 0.0029176000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0082932000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0082991000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0082988000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0083156000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0083004000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0083188000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0083175000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0086075000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0083060000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0083248000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0083235000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029177000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0086332000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0083293000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0029176000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0086515000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0029175000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0086309000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0008650000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0036480000; - when : "A1&A2&A3&A4&!B1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__a41o"; - cell_leakage_power : 0.0054445730; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046217000, 0.0046225000, 0.0046244000, 0.0046261000, 0.0046298000, 0.0046384000, 0.0046581000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003698000, -0.003701200, -0.003708600, -0.003702100, -0.003687300, -0.003653100, -0.003574300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023390000; - } - pin ("A2") { - capacitance : 0.0023350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043559000, 0.0043522000, 0.0043435000, 0.0043573000, 0.0043892000, 0.0044625000, 0.0046315000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004009700, -0.004008400, -0.004005400, -0.004004600, -0.004002700, -0.003998400, -0.003988500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("A3") { - capacitance : 0.0023260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040049000, 0.0040071000, 0.0040122000, 0.0040118000, 0.0040108000, 0.0040087000, 0.0040036000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004012400, -0.004010500, -0.004006000, -0.004004500, -0.004001000, -0.003992900, -0.003974400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("A4") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040528000, 0.0040518000, 0.0040494000, 0.0040500000, 0.0040515000, 0.0040551000, 0.0040632000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004042800, -0.004041400, -0.004038200, -0.004038100, -0.004037900, -0.004037400, -0.004036300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024890000; - } - pin ("B1") { - capacitance : 0.0023360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027317000, 0.0027181000, 0.0026869000, 0.0027082000, 0.0027575000, 0.0028709000, 0.0031323000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001699300, -0.001701500, -0.001706600, -0.001708900, -0.001714100, -0.001726100, -0.001753800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025140000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3&A4) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0146375000, 0.0131818000, 0.0095882000, -0.001861500, -0.040033900, -0.157513900, -0.505017900", \ - "0.0146468000, 0.0131696000, 0.0094873000, -0.001946900, -0.040151800, -0.157588300, -0.505102300", \ - "0.0144659000, 0.0129871000, 0.0092975000, -0.002144000, -0.040361000, -0.157807600, -0.505280900", \ - "0.0141771000, 0.0127112000, 0.0090029000, -0.002441500, -0.040679700, -0.158117800, -0.505576700", \ - "0.0138627000, 0.0123686000, 0.0086594000, -0.002819600, -0.041040100, -0.158460600, -0.505885200", \ - "0.0149249000, 0.0132696000, 0.0085994000, -0.003186700, -0.041298400, -0.158616400, -0.506037300", \ - "0.0184877000, 0.0167272000, 0.0119220000, -0.001678000, -0.041452500, -0.158701800, -0.506002700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0184612000, 0.0200966000, 0.0250822000, 0.0393317000, 0.0795157000, 0.1965472000, 0.5408657000", \ - "0.0184488000, 0.0201350000, 0.0250324000, 0.0391494000, 0.0794430000, 0.1967353000, 0.5403592000", \ - "0.0182080000, 0.0198439000, 0.0248022000, 0.0390611000, 0.0792912000, 0.1965025000, 0.5409441000", \ - "0.0179687000, 0.0196104000, 0.0245540000, 0.0387422000, 0.0791064000, 0.1960908000, 0.5392340000", \ - "0.0181482000, 0.0197417000, 0.0245964000, 0.0386578000, 0.0786718000, 0.1959417000, 0.5401327000", \ - "0.0192395000, 0.0207829000, 0.0253289000, 0.0386059000, 0.0788177000, 0.1958315000, 0.5422735000", \ - "0.0208693000, 0.0223231000, 0.0267497000, 0.0403331000, 0.0799430000, 0.1968747000, 0.5388685000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0172926000, 0.0157873000, 0.0121035000, 0.0007054000, -0.037328700, -0.154673000, -0.502070400", \ - "0.0172368000, 0.0157327000, 0.0120533000, 0.0006608000, -0.037379100, -0.154735900, -0.502121300", \ - "0.0170904000, 0.0156342000, 0.0118971000, 0.0004535000, -0.037607200, -0.154914400, -0.502287200", \ - "0.0168272000, 0.0153572000, 0.0116312000, 0.0001898000, -0.037885000, -0.155170200, -0.502535900", \ - "0.0165161000, 0.0150474000, 0.0113166000, -0.000186000, -0.038242200, -0.155519100, -0.502875000", \ - "0.0160987000, 0.0145895000, 0.0108922000, -0.000540900, -0.038530000, -0.155735700, -0.503072700", \ - "0.0211220000, 0.0193672000, 0.0145348000, 0.0008997000, -0.038955500, -0.156122500, -0.503293700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0188852000, 0.0205537000, 0.0254782000, 0.0395582000, 0.0800022000, 0.1970905000, 0.5427569000", \ - "0.0188145000, 0.0205011000, 0.0254017000, 0.0394783000, 0.0798010000, 0.1970604000, 0.5433396000", \ - "0.0186718000, 0.0203596000, 0.0252590000, 0.0393463000, 0.0796687000, 0.1969248000, 0.5432089000", \ - "0.0184239000, 0.0200614000, 0.0250014000, 0.0392125000, 0.0795557000, 0.1965914000, 0.5402212000", \ - "0.0182773000, 0.0199079000, 0.0247970000, 0.0388101000, 0.0791860000, 0.1963333000, 0.5402664000", \ - "0.0191487000, 0.0206911000, 0.0253777000, 0.0387942000, 0.0788738000, 0.1960615000, 0.5424564000", \ - "0.0203925000, 0.0218437000, 0.0263854000, 0.0400241000, 0.0799505000, 0.1969646000, 0.5389392000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0200877000, 0.0186130000, 0.0150721000, 0.0035781000, -0.034407500, -0.151596600, -0.498894700", \ - "0.0201539000, 0.0186650000, 0.0148904000, 0.0034605000, -0.034505800, -0.151716400, -0.499002500", \ - "0.0199636000, 0.0184932000, 0.0146499000, 0.0033147000, -0.034648200, -0.151864200, -0.499150700", \ - "0.0196871000, 0.0181711000, 0.0144165000, 0.0029978000, -0.034867100, -0.152058200, -0.499392100", \ - "0.0194107000, 0.0179238000, 0.0141912000, 0.0027965000, -0.035182900, -0.152353500, -0.499597100", \ - "0.0193908000, 0.0178485000, 0.0140343000, 0.0025872000, -0.035285600, -0.152427600, -0.499692900", \ - "0.0244835000, 0.0227133000, 0.0178818000, 0.0041684000, -0.035709600, -0.152701400, -0.499768800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0189210000, 0.0205961000, 0.0254950000, 0.0395727000, 0.0798859000, 0.1970484000, 0.5433234000", \ - "0.0188245000, 0.0205103000, 0.0254079000, 0.0394924000, 0.0798111000, 0.1971005000, 0.5432820000", \ - "0.0186831000, 0.0203529000, 0.0252630000, 0.0393473000, 0.0796646000, 0.1968118000, 0.5431018000", \ - "0.0184222000, 0.0200539000, 0.0250136000, 0.0392170000, 0.0795093000, 0.1967863000, 0.5429297000", \ - "0.0184278000, 0.0200311000, 0.0249173000, 0.0389131000, 0.0792626000, 0.1963513000, 0.5401663000", \ - "0.0191186000, 0.0206674000, 0.0253118000, 0.0387154000, 0.0789604000, 0.1959159000, 0.5404783000", \ - "0.0201901000, 0.0216718000, 0.0261955000, 0.0397997000, 0.0796315000, 0.1969546000, 0.5409640000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0222834000, 0.0207662000, 0.0170726000, 0.0056896000, -0.032186800, -0.149313500, -0.496488300", \ - "0.0221470000, 0.0206657000, 0.0169744000, 0.0056216000, -0.032278500, -0.149401800, -0.496573700", \ - "0.0220143000, 0.0205275000, 0.0168534000, 0.0054536000, -0.032386600, -0.149488500, -0.496694700", \ - "0.0218375000, 0.0203562000, 0.0167644000, 0.0053578000, -0.032548700, -0.149665500, -0.496842400", \ - "0.0216436000, 0.0201970000, 0.0164893000, 0.0051308000, -0.032784500, -0.149855700, -0.496995900", \ - "0.0216485000, 0.0201104000, 0.0163790000, 0.0049899000, -0.032902200, -0.149979800, -0.497112800", \ - "0.0268690000, 0.0251089000, 0.0203182000, 0.0073278000, -0.032858600, -0.150000600, -0.497094700"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0189184000, 0.0205559000, 0.0254953000, 0.0397766000, 0.0800885000, 0.1972321000, 0.5415334000", \ - "0.0189100000, 0.0205925000, 0.0254899000, 0.0395775000, 0.0799011000, 0.1971663000, 0.5432692000", \ - "0.0187700000, 0.0204518000, 0.0253491000, 0.0394424000, 0.0797657000, 0.1970395000, 0.5431208000", \ - "0.0184772000, 0.0201170000, 0.0250939000, 0.0393561000, 0.0796310000, 0.1968250000, 0.5410940000", \ - "0.0183845000, 0.0200016000, 0.0249106000, 0.0390172000, 0.0792604000, 0.1964715000, 0.5427941000", \ - "0.0190929000, 0.0206968000, 0.0253184000, 0.0387662000, 0.0791881000, 0.1960712000, 0.5405311000", \ - "0.0198628000, 0.0215133000, 0.0260537000, 0.0396141000, 0.0796371000, 0.1967659000, 0.5387707000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0206737000, 0.0191755000, 0.0154353000, 0.0041091000, -0.033755500, -0.150832800, -0.497973800", \ - "0.0205791000, 0.0190630000, 0.0153341000, 0.0040123000, -0.033880400, -0.150952000, -0.498060400", \ - "0.0203324000, 0.0187847000, 0.0152632000, 0.0038053000, -0.034065900, -0.151101400, -0.498265400", \ - "0.0201369000, 0.0186412000, 0.0149309000, 0.0036390000, -0.034257400, -0.151332100, -0.498492500", \ - "0.0199854000, 0.0186314000, 0.0147522000, 0.0035501000, -0.034617700, -0.151619800, -0.498725100", \ - "0.0202951000, 0.0192584000, 0.0148245000, 0.0039271000, -0.034591600, -0.151615800, -0.498648000", \ - "0.0270941000, 0.0254513000, 0.0202757000, 0.0065119000, -0.033560800, -0.150597400, -0.497610600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014716140, 0.0043312940, 0.0127479800, 0.0375202100, 0.1104305000, 0.3250221000"); - values("0.0131670000, 0.0149261000, 0.0200239000, 0.0341551000, 0.0741075000, 0.1920941000, 0.5325179000", \ - "0.0131167000, 0.0148579000, 0.0199785000, 0.0340839000, 0.0740986000, 0.1911551000, 0.5358136000", \ - "0.0129576000, 0.0147155000, 0.0197792000, 0.0338020000, 0.0738934000, 0.1910196000, 0.5328290000", \ - "0.0127533000, 0.0144557000, 0.0194225000, 0.0334066000, 0.0734789000, 0.1905480000, 0.5336886000", \ - "0.0127491000, 0.0143649000, 0.0191770000, 0.0330592000, 0.0730801000, 0.1901333000, 0.5347912000", \ - "0.0135492000, 0.0151055000, 0.0197561000, 0.0334535000, 0.0732614000, 0.1896550000, 0.5365777000", \ - "0.0156851000, 0.0170778000, 0.0215399000, 0.0350718000, 0.0751408000, 0.1919565000, 0.5336023000"); - } - } - max_capacitance : 0.3250220000; - max_transition : 1.5009670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1761867000, 0.1824799000, 0.1965336000, 0.2252298000, 0.2827718000, 0.4137085000, 0.7681329000", \ - "0.1816162000, 0.1878941000, 0.2020227000, 0.2307618000, 0.2883540000, 0.4190095000, 0.7730819000", \ - "0.1941617000, 0.2003947000, 0.2145695000, 0.2432893000, 0.3008436000, 0.4315971000, 0.7854987000", \ - "0.2218845000, 0.2281719000, 0.2422670000, 0.2708948000, 0.3285703000, 0.4593019000, 0.8131309000", \ - "0.2805685000, 0.2868831000, 0.3009512000, 0.3295568000, 0.3872989000, 0.5179357000, 0.8724217000", \ - "0.3912882000, 0.3983045000, 0.4139012000, 0.4452597000, 0.5061173000, 0.6394474000, 0.9937288000", \ - "0.5708143000, 0.5793303000, 0.5982287000, 0.6356004000, 0.7057127000, 0.8477620000, 1.2048473000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1324705000, 0.1401871000, 0.1577949000, 0.1952367000, 0.2818014000, 0.5151351000, 1.1932850000", \ - "0.1359649000, 0.1436837000, 0.1612653000, 0.1987844000, 0.2853326000, 0.5188779000, 1.1991562000", \ - "0.1445870000, 0.1523063000, 0.1698768000, 0.2074812000, 0.2941459000, 0.5272099000, 1.2052065000", \ - "0.1661767000, 0.1739905000, 0.1915208000, 0.2291088000, 0.3157124000, 0.5490047000, 1.2260355000", \ - "0.2144279000, 0.2221635000, 0.2397015000, 0.2773207000, 0.3640306000, 0.5968084000, 1.2757643000", \ - "0.2828455000, 0.2916815000, 0.3107289000, 0.3494423000, 0.4369938000, 0.6712304000, 1.3520836000", \ - "0.3553947000, 0.3664853000, 0.3903454000, 0.4357208000, 0.5255734000, 0.7585704000, 1.4378282000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0253702000, 0.0292026000, 0.0391034000, 0.0606166000, 0.1140026000, 0.2635062000, 0.7307991000", \ - "0.0253868000, 0.0293119000, 0.0387338000, 0.0609084000, 0.1141270000, 0.2643384000, 0.7333944000", \ - "0.0253869000, 0.0293930000, 0.0390919000, 0.0604849000, 0.1140124000, 0.2642836000, 0.7332692000", \ - "0.0253802000, 0.0293222000, 0.0387181000, 0.0609838000, 0.1139240000, 0.2643200000, 0.7330779000", \ - "0.0253105000, 0.0297122000, 0.0390835000, 0.0606642000, 0.1140971000, 0.2638929000, 0.7317172000", \ - "0.0303969000, 0.0352920000, 0.0450525000, 0.0672461000, 0.1193577000, 0.2671936000, 0.7328094000", \ - "0.0415605000, 0.0472805000, 0.0594503000, 0.0830316000, 0.1363765000, 0.2794965000, 0.7319111000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0276589000, 0.0334447000, 0.0479627000, 0.0848250000, 0.1908561000, 0.5177696000, 1.4993049000", \ - "0.0275740000, 0.0335131000, 0.0480005000, 0.0848818000, 0.1908328000, 0.5176160000, 1.4995731000", \ - "0.0276568000, 0.0334405000, 0.0479208000, 0.0847944000, 0.1908287000, 0.5181683000, 1.4975959000", \ - "0.0276998000, 0.0334120000, 0.0481768000, 0.0847043000, 0.1906159000, 0.5173340000, 1.4971125000", \ - "0.0283293000, 0.0343086000, 0.0484945000, 0.0853435000, 0.1911981000, 0.5187770000, 1.4991036000", \ - "0.0350796000, 0.0406575000, 0.0539292000, 0.0894574000, 0.1938796000, 0.5193905000, 1.5004150000", \ - "0.0474336000, 0.0547544000, 0.0690718000, 0.1015051000, 0.1989028000, 0.5208173000, 1.4976830000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2037041000, 0.2103144000, 0.2250693000, 0.2542642000, 0.3133197000, 0.4454107000, 0.8003822000", \ - "0.2093419000, 0.2159526000, 0.2307190000, 0.2601178000, 0.3189906000, 0.4510820000, 0.8060670000", \ - "0.2224204000, 0.2290221000, 0.2437238000, 0.2733594000, 0.3321370000, 0.4641889000, 0.8192597000", \ - "0.2517284000, 0.2583616000, 0.2730696000, 0.3027042000, 0.3614690000, 0.4935411000, 0.8486333000", \ - "0.3146804000, 0.3212804000, 0.3360413000, 0.3655440000, 0.4246116000, 0.5566960000, 0.9116785000", \ - "0.4439366000, 0.4511306000, 0.4669646000, 0.4982980000, 0.5594333000, 0.6923472000, 1.0474057000", \ - "0.6644014000, 0.6731093000, 0.6920836000, 0.7292688000, 0.7985970000, 0.9403590000, 1.2979218000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1432249000, 0.1509882000, 0.1684576000, 0.2060133000, 0.2925843000, 0.5260095000, 1.2032616000", \ - "0.1469379000, 0.1546612000, 0.1722171000, 0.2097272000, 0.2962253000, 0.5299752000, 1.2085783000", \ - "0.1552486000, 0.1629719000, 0.1805278000, 0.2180371000, 0.3045253000, 0.5382801000, 1.2168050000", \ - "0.1748716000, 0.1826009000, 0.2001287000, 0.2377357000, 0.3243050000, 0.5574715000, 1.2351572000", \ - "0.2170109000, 0.2249040000, 0.2427148000, 0.2806826000, 0.3673406000, 0.6003297000, 1.2787847000", \ - "0.2819642000, 0.2907555000, 0.3100473000, 0.3497681000, 0.4378752000, 0.6715890000, 1.3516465000", \ - "0.3475792000, 0.3586778000, 0.3827667000, 0.4279499000, 0.5193214000, 0.7534762000, 1.4320140000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0273615000, 0.0315968000, 0.0412361000, 0.0636414000, 0.1166353000, 0.2658385000, 0.7323001000", \ - "0.0273643000, 0.0315893000, 0.0412078000, 0.0628242000, 0.1166434000, 0.2659771000, 0.7324367000", \ - "0.0274038000, 0.0315965000, 0.0410424000, 0.0629568000, 0.1166888000, 0.2652453000, 0.7310143000", \ - "0.0276532000, 0.0315691000, 0.0410356000, 0.0627254000, 0.1164065000, 0.2656192000, 0.7324426000", \ - "0.0272792000, 0.0314890000, 0.0414016000, 0.0632169000, 0.1163819000, 0.2653503000, 0.7327267000", \ - "0.0313564000, 0.0357885000, 0.0465144000, 0.0673452000, 0.1196477000, 0.2676880000, 0.7330482000", \ - "0.0422634000, 0.0472034000, 0.0586299000, 0.0824622000, 0.1364463000, 0.2792805000, 0.7328831000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0276562000, 0.0336311000, 0.0481933000, 0.0847854000, 0.1906386000, 0.5187749000, 1.4954573000", \ - "0.0275892000, 0.0335268000, 0.0479795000, 0.0845408000, 0.1910194000, 0.5188814000, 1.4999395000", \ - "0.0276013000, 0.0335330000, 0.0479746000, 0.0845235000, 0.1910639000, 0.5189688000, 1.4997112000", \ - "0.0276722000, 0.0334364000, 0.0482080000, 0.0846293000, 0.1906732000, 0.5179986000, 1.4985543000", \ - "0.0289480000, 0.0345309000, 0.0489428000, 0.0856239000, 0.1911020000, 0.5184897000, 1.4990464000", \ - "0.0339832000, 0.0398112000, 0.0545700000, 0.0897514000, 0.1939698000, 0.5184214000, 1.4989812000", \ - "0.0451718000, 0.0522269000, 0.0676677000, 0.1015675000, 0.1994348000, 0.5202116000, 1.4968078000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2262080000, 0.2330288000, 0.2481099000, 0.2783777000, 0.3381381000, 0.4713425000, 0.8268393000", \ - "0.2315690000, 0.2383736000, 0.2534827000, 0.2837809000, 0.3434437000, 0.4766599000, 0.8323342000", \ - "0.2445862000, 0.2513776000, 0.2665569000, 0.2968131000, 0.3564751000, 0.4896971000, 0.8453844000", \ - "0.2748172000, 0.2816022000, 0.2967630000, 0.3270289000, 0.3867811000, 0.5199248000, 0.8752687000", \ - "0.3387770000, 0.3456126000, 0.3609071000, 0.3912244000, 0.4511835000, 0.5842721000, 0.9398166000", \ - "0.4751863000, 0.4824103000, 0.4974487000, 0.5298637000, 0.5904968000, 0.7244938000, 1.0801783000", \ - "0.7131595000, 0.7216337000, 0.7408239000, 0.7777167000, 0.8470549000, 0.9880700000, 1.3461500000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1510802000, 0.1588736000, 0.1763801000, 0.2139053000, 0.3003895000, 0.5341492000, 1.2122170000", \ - "0.1550185000, 0.1627365000, 0.1803187000, 0.2178174000, 0.3043147000, 0.5380039000, 1.2169907000", \ - "0.1629160000, 0.1707168000, 0.1882234000, 0.2257476000, 0.3122199000, 0.5459748000, 1.2239054000", \ - "0.1794580000, 0.1871572000, 0.2048044000, 0.2422975000, 0.3286946000, 0.5624377000, 1.2417730000", \ - "0.2143931000, 0.2223418000, 0.2400405000, 0.2779014000, 0.3646377000, 0.5976479000, 1.2759499000", \ - "0.2699388000, 0.2786506000, 0.2981389000, 0.3375002000, 0.4263362000, 0.6600844000, 1.3387277000", \ - "0.3266313000, 0.3374097000, 0.3610369000, 0.4065793000, 0.4992822000, 0.7338452000, 1.4115049000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0291242000, 0.0335686000, 0.0433177000, 0.0647052000, 0.1185829000, 0.2678197000, 0.7341092000", \ - "0.0292384000, 0.0336862000, 0.0435449000, 0.0647970000, 0.1186824000, 0.2670439000, 0.7325585000", \ - "0.0291119000, 0.0332777000, 0.0432896000, 0.0647955000, 0.1186864000, 0.2671686000, 0.7327621000", \ - "0.0290274000, 0.0334453000, 0.0429480000, 0.0651890000, 0.1185729000, 0.2679419000, 0.7328202000", \ - "0.0292569000, 0.0336875000, 0.0429449000, 0.0648534000, 0.1184999000, 0.2676079000, 0.7346180000", \ - "0.0323905000, 0.0367730000, 0.0462126000, 0.0678261000, 0.1208874000, 0.2686862000, 0.7348234000", \ - "0.0425116000, 0.0480221000, 0.0589724000, 0.0816617000, 0.1350974000, 0.2788765000, 0.7352043000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0276708000, 0.0335628000, 0.0481282000, 0.0846964000, 0.1911363000, 0.5189123000, 1.4980358000", \ - "0.0275848000, 0.0335091000, 0.0479716000, 0.0846234000, 0.1909227000, 0.5185903000, 1.5004611000", \ - "0.0276890000, 0.0335714000, 0.0481048000, 0.0846534000, 0.1911455000, 0.5189245000, 1.4975186000", \ - "0.0277403000, 0.0334699000, 0.0480348000, 0.0844708000, 0.1910815000, 0.5189146000, 1.5006952000", \ - "0.0288540000, 0.0347209000, 0.0486925000, 0.0854492000, 0.1910580000, 0.5184514000, 1.4989525000", \ - "0.0330043000, 0.0390581000, 0.0539918000, 0.0903043000, 0.1946986000, 0.5195678000, 1.4980575000", \ - "0.0437675000, 0.0508941000, 0.0663954000, 0.1020031000, 0.2003120000, 0.5213488000, 1.4949886000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.2305364000, 0.2373333000, 0.2523685000, 0.2823645000, 0.3418062000, 0.4737138000, 0.8295198000", \ - "0.2358976000, 0.2427023000, 0.2577402000, 0.2877482000, 0.3471834000, 0.4790940000, 0.8348955000", \ - "0.2493523000, 0.2561501000, 0.2712549000, 0.3012102000, 0.3602407000, 0.4924473000, 0.8483244000", \ - "0.2799691000, 0.2868180000, 0.3017940000, 0.3317363000, 0.3911150000, 0.5232078000, 0.8790113000", \ - "0.3453927000, 0.3522601000, 0.3672339000, 0.3972506000, 0.4565140000, 0.5891229000, 0.9446159000", \ - "0.4846680000, 0.4918444000, 0.5078123000, 0.5387654000, 0.5987238000, 0.7317013000, 1.0872604000", \ - "0.7304422000, 0.7389959000, 0.7578448000, 0.7940066000, 0.8619878000, 1.0017017000, 1.3591689000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1554765000, 0.1631867000, 0.1807238000, 0.2183945000, 0.3048937000, 0.5374998000, 1.2161352000", \ - "0.1595082000, 0.1672237000, 0.1848407000, 0.2223282000, 0.3088255000, 0.5424193000, 1.2220333000", \ - "0.1672765000, 0.1749914000, 0.1926105000, 0.2301064000, 0.3165972000, 0.5501918000, 1.2300146000", \ - "0.1821457000, 0.1898549000, 0.2074348000, 0.2450366000, 0.3316358000, 0.5642942000, 1.2429724000", \ - "0.2112836000, 0.2191286000, 0.2369309000, 0.2747756000, 0.3614108000, 0.5950071000, 1.2724624000", \ - "0.2570577000, 0.2656019000, 0.2847016000, 0.3247292000, 0.4131659000, 0.6465908000, 1.3251059000", \ - "0.3067867000, 0.3172244000, 0.3399036000, 0.3848259000, 0.4773196000, 0.7122855000, 1.3895929000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0290604000, 0.0333556000, 0.0426417000, 0.0639820000, 0.1173117000, 0.2665422000, 0.7335695000", \ - "0.0290801000, 0.0333960000, 0.0426474000, 0.0640936000, 0.1172891000, 0.2665771000, 0.7337461000", \ - "0.0291108000, 0.0334645000, 0.0433833000, 0.0639861000, 0.1175221000, 0.2664593000, 0.7344029000", \ - "0.0292101000, 0.0334289000, 0.0430928000, 0.0640224000, 0.1172832000, 0.2665194000, 0.7334781000", \ - "0.0292090000, 0.0332588000, 0.0426962000, 0.0642469000, 0.1171361000, 0.2663104000, 0.7347798000", \ - "0.0321755000, 0.0360339000, 0.0458410000, 0.0667180000, 0.1192685000, 0.2670601000, 0.7346387000", \ - "0.0422050000, 0.0469873000, 0.0582637000, 0.0811218000, 0.1337245000, 0.2766134000, 0.7345039000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0275700000, 0.0334924000, 0.0482613000, 0.0846868000, 0.1909224000, 0.5184947000, 1.4980915000", \ - "0.0276211000, 0.0334683000, 0.0480313000, 0.0847568000, 0.1907091000, 0.5179805000, 1.5006389000", \ - "0.0276627000, 0.0334642000, 0.0480288000, 0.0847533000, 0.1907457000, 0.5178621000, 1.5005208000", \ - "0.0275856000, 0.0334621000, 0.0478780000, 0.0847650000, 0.1909083000, 0.5183837000, 1.4980810000", \ - "0.0287696000, 0.0343775000, 0.0486077000, 0.0851626000, 0.1912782000, 0.5189221000, 1.4962587000", \ - "0.0318101000, 0.0382144000, 0.0531383000, 0.0897031000, 0.1937304000, 0.5181744000, 1.4972831000", \ - "0.0406797000, 0.0478347000, 0.0633906000, 0.0999961000, 0.1998597000, 0.5212281000, 1.4957744000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.1956633000, 0.2024055000, 0.2174481000, 0.2474760000, 0.3069319000, 0.4391949000, 0.7947148000", \ - "0.1993289000, 0.2061821000, 0.2212989000, 0.2512930000, 0.3107664000, 0.4430938000, 0.7983363000", \ - "0.2094914000, 0.2162219000, 0.2312655000, 0.2610216000, 0.3203761000, 0.4528404000, 0.8083318000", \ - "0.2350939000, 0.2421903000, 0.2573085000, 0.2875369000, 0.3468130000, 0.4791172000, 0.8348461000", \ - "0.3008453000, 0.3073086000, 0.3226670000, 0.3523008000, 0.4120517000, 0.5444682000, 0.9002492000", \ - "0.4430214000, 0.4506613000, 0.4667212000, 0.4982476000, 0.5586262000, 0.6911700000, 1.0470420000", \ - "0.6700491000, 0.6803942000, 0.7001913000, 0.7397150000, 0.8065767000, 0.9432910000, 1.3014988000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0589109000, 0.0645962000, 0.0787619000, 0.1117248000, 0.1924293000, 0.4223469000, 1.0990101000", \ - "0.0637574000, 0.0694313000, 0.0836008000, 0.1165280000, 0.1974896000, 0.4275463000, 1.1079409000", \ - "0.0749350000, 0.0805970000, 0.0946679000, 0.1275617000, 0.2086233000, 0.4388627000, 1.1260405000", \ - "0.0985004000, 0.1044015000, 0.1186241000, 0.1515508000, 0.2327031000, 0.4637958000, 1.1524317000", \ - "0.1309933000, 0.1385515000, 0.1555659000, 0.1910725000, 0.2730699000, 0.5041517000, 1.1798637000", \ - "0.1662883000, 0.1766819000, 0.1998601000, 0.2425236000, 0.3278045000, 0.5585118000, 1.2379773000", \ - "0.1871065000, 0.2010967000, 0.2332300000, 0.2909181000, 0.3861958000, 0.6177429000, 1.2939808000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0290786000, 0.0334811000, 0.0428390000, 0.0648311000, 0.1170142000, 0.2663275000, 0.7347557000", \ - "0.0289560000, 0.0331796000, 0.0430006000, 0.0639719000, 0.1171508000, 0.2667532000, 0.7317874000", \ - "0.0292003000, 0.0331089000, 0.0430536000, 0.0649081000, 0.1173997000, 0.2667300000, 0.7338299000", \ - "0.0290914000, 0.0332119000, 0.0430017000, 0.0645305000, 0.1172913000, 0.2660267000, 0.7328308000", \ - "0.0289593000, 0.0332182000, 0.0430418000, 0.0641171000, 0.1170037000, 0.2661851000, 0.7343355000", \ - "0.0348980000, 0.0388869000, 0.0481080000, 0.0688274000, 0.1193775000, 0.2673758000, 0.7337886000", \ - "0.0507678000, 0.0553247000, 0.0664381000, 0.0862004000, 0.1341073000, 0.2759569000, 0.7336277000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014716100, 0.0043312900, 0.0127480000, 0.0375202000, 0.1104310000, 0.3250220000"); - values("0.0175903000, 0.0229565000, 0.0373982000, 0.0740412000, 0.1822031000, 0.5156106000, 1.4950134000", \ - "0.0175939000, 0.0229572000, 0.0374015000, 0.0740890000, 0.1821962000, 0.5132384000, 1.5009672000", \ - "0.0176287000, 0.0229848000, 0.0374395000, 0.0740614000, 0.1821738000, 0.5133977000, 1.4966319000", \ - "0.0195779000, 0.0246493000, 0.0384999000, 0.0745107000, 0.1820963000, 0.5149501000, 1.4989773000", \ - "0.0267900000, 0.0322278000, 0.0456418000, 0.0790521000, 0.1835827000, 0.5140972000, 1.4965659000", \ - "0.0389113000, 0.0462094000, 0.0616380000, 0.0913124000, 0.1880880000, 0.5122560000, 1.4970293000", \ - "0.0572977000, 0.0678697000, 0.0882168000, 0.1189229000, 0.2016623000, 0.5152390000, 1.4919785000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41o_4") { - leakage_power () { - value : 0.0046105000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0082481000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0082575000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0082581000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0082869000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0082599000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0082888000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0082912000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046109000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0089728000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0082703000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0083003000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0083028000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046103000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0088094000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0083167000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0046099000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0088056000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0046100000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0088092000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0021909000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0054482000; - when : "A1&A2&A3&A4&!B1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__a41o"; - cell_leakage_power : 0.0063521180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088935000, 0.0088876000, 0.0088741000, 0.0088719000, 0.0088668000, 0.0088551000, 0.0088282000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006171300, -0.006172800, -0.006176500, -0.006159500, -0.006120300, -0.006030100, -0.005822100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043280000; - } - pin ("A2") { - capacitance : 0.0042220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083726000, 0.0083698000, 0.0083633000, 0.0083959000, 0.0084713000, 0.0086448000, 0.0090450000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007752000, -0.007748400, -0.007740000, -0.007738100, -0.007733800, -0.007723800, -0.007700800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043620000; - } - pin ("A3") { - capacitance : 0.0043970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078491000, 0.0078549000, 0.0078680000, 0.0078667000, 0.0078637000, 0.0078566000, 0.0078404000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007845000, -0.007846300, -0.007849200, -0.007851100, -0.007855500, -0.007865600, -0.007889000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045650000; - } - pin ("A4") { - capacitance : 0.0044010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078615000, 0.0078653000, 0.0078740000, 0.0078766000, 0.0078825000, 0.0078961000, 0.0079274000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007869500, -0.007867900, -0.007864300, -0.007863400, -0.007861100, -0.007856000, -0.007844000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046380000; - } - pin ("B1") { - capacitance : 0.0045140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039355000, 0.0039187000, 0.0038799000, 0.0039153000, 0.0039970000, 0.0041851000, 0.0046188000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003398400, -0.003409200, -0.003434000, -0.003438100, -0.003447300, -0.003468700, -0.003518000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048960000; - } - pin ("X") { - direction : "output"; - function : "(A1&A2&A3&A4) | (B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0283566000, 0.0265670000, 0.0214184000, 0.0061189000, -0.049881000, -0.242562700, -0.868521400", \ - "0.0280678000, 0.0264028000, 0.0212607000, 0.0060403000, -0.049909300, -0.242778900, -0.868557800", \ - "0.0278946000, 0.0260994000, 0.0209503000, 0.0056863000, -0.050359400, -0.243007800, -0.868928700", \ - "0.0273414000, 0.0255613000, 0.0204113000, 0.0051336000, -0.050773500, -0.243517100, -0.869395100", \ - "0.0267200000, 0.0249667000, 0.0197803000, 0.0043789000, -0.051575000, -0.244261600, -0.869954200", \ - "0.0256060000, 0.0237654000, 0.0183663000, 0.0033590000, -0.052226000, -0.244540100, -0.870177700", \ - "0.0347086000, 0.0322526000, 0.0260554000, 0.0072155000, -0.052388500, -0.244896000, -0.870154200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0338333000, 0.0356243000, 0.0417639000, 0.0615851000, 0.1225181000, 0.3156794000, 0.9357667000", \ - "0.0333588000, 0.0351549000, 0.0412926000, 0.0611566000, 0.1224145000, 0.3154337000, 0.9362187000", \ - "0.0331112000, 0.0349775000, 0.0410904000, 0.0607144000, 0.1220379000, 0.3154240000, 0.9345519000", \ - "0.0326079000, 0.0344323000, 0.0405597000, 0.0603972000, 0.1215607000, 0.3147928000, 0.9353658000", \ - "0.0326094000, 0.0344464000, 0.0404429000, 0.0601711000, 0.1206257000, 0.3141379000, 0.9349147000", \ - "0.0338426000, 0.0355877000, 0.0412813000, 0.0597400000, 0.1204101000, 0.3134558000, 0.9329565000", \ - "0.0368070000, 0.0383718000, 0.0439586000, 0.0623088000, 0.1221448000, 0.3145637000, 0.9323754000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0346549000, 0.0328990000, 0.0275833000, 0.0122223000, -0.043399500, -0.235572200, -0.861250600", \ - "0.0346663000, 0.0328870000, 0.0275853000, 0.0121122000, -0.043512300, -0.235751700, -0.861420900", \ - "0.0343455000, 0.0324895000, 0.0272440000, 0.0120322000, -0.043778300, -0.236040400, -0.861652200", \ - "0.0336994000, 0.0319681000, 0.0266361000, 0.0112380000, -0.044396700, -0.236524600, -0.862184500", \ - "0.0330929000, 0.0312577000, 0.0259732000, 0.0104660000, -0.045260900, -0.237388600, -0.862906800", \ - "0.0324240000, 0.0305331000, 0.0251662000, 0.0097977000, -0.045780200, -0.237886300, -0.863273700", \ - "0.0403502000, 0.0382967000, 0.0321176000, 0.0133000000, -0.045885200, -0.238597500, -0.863777600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0352090000, 0.0370408000, 0.0431815000, 0.0628633000, 0.1241415000, 0.3173625000, 0.9370636000", \ - "0.0351157000, 0.0368996000, 0.0430367000, 0.0626601000, 0.1238578000, 0.3171228000, 0.9377107000", \ - "0.0347503000, 0.0365531000, 0.0426773000, 0.0622565000, 0.1236887000, 0.3170704000, 0.9404864000", \ - "0.0343557000, 0.0360742000, 0.0422013000, 0.0619166000, 0.1233850000, 0.3164428000, 0.9388132000", \ - "0.0344455000, 0.0362337000, 0.0422643000, 0.0617448000, 0.1228334000, 0.3160841000, 0.9384244000", \ - "0.0350807000, 0.0370292000, 0.0427457000, 0.0613545000, 0.1220861000, 0.3148963000, 0.9360292000", \ - "0.0378416000, 0.0395152000, 0.0450949000, 0.0637751000, 0.1234246000, 0.3159692000, 0.9328086000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0403557000, 0.0385641000, 0.0331159000, 0.0178161000, -0.037840100, -0.229758500, -0.855075300", \ - "0.0399791000, 0.0381966000, 0.0328705000, 0.0174838000, -0.037974900, -0.229871500, -0.855227900", \ - "0.0399757000, 0.0381705000, 0.0328181000, 0.0174059000, -0.038200600, -0.230231300, -0.855485900", \ - "0.0395812000, 0.0378202000, 0.0324444000, 0.0170309000, -0.038622000, -0.230500600, -0.855845800", \ - "0.0389614000, 0.0371668000, 0.0318093000, 0.0163859000, -0.039164000, -0.231141500, -0.856286100", \ - "0.0388110000, 0.0370585000, 0.0316474000, 0.0160690000, -0.039430300, -0.231320600, -0.856493200", \ - "0.0472567000, 0.0452092000, 0.0390311000, 0.0201257000, -0.039786400, -0.231862900, -0.856713700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0352324000, 0.0370341000, 0.0431742000, 0.0628031000, 0.1240054000, 0.3173077000, 0.9377950000", \ - "0.0350356000, 0.0368914000, 0.0429733000, 0.0625792000, 0.1238348000, 0.3171586000, 0.9376107000", \ - "0.0346191000, 0.0365214000, 0.0426178000, 0.0622063000, 0.1236449000, 0.3170022000, 0.9403905000", \ - "0.0343278000, 0.0361146000, 0.0422544000, 0.0618658000, 0.1233662000, 0.3164119000, 0.9387489000", \ - "0.0340978000, 0.0359312000, 0.0419462000, 0.0616662000, 0.1226481000, 0.3161689000, 0.9367587000", \ - "0.0351113000, 0.0368784000, 0.0426614000, 0.0612501000, 0.1224490000, 0.3152237000, 0.9351694000", \ - "0.0370366000, 0.0387233000, 0.0443706000, 0.0631729000, 0.1234732000, 0.3161723000, 0.9338160000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0450691000, 0.0432673000, 0.0379496000, 0.0225730000, -0.032708000, -0.224240900, -0.849146400", \ - "0.0448084000, 0.0429961000, 0.0376185000, 0.0222254000, -0.033043000, -0.224393300, -0.849350100", \ - "0.0443803000, 0.0425954000, 0.0372545000, 0.0220401000, -0.033293800, -0.224736900, -0.849649400", \ - "0.0443311000, 0.0425185000, 0.0371812000, 0.0218069000, -0.033464700, -0.224973400, -0.849939300", \ - "0.0438487000, 0.0420422000, 0.0366650000, 0.0212830000, -0.033968400, -0.225379700, -0.850250300", \ - "0.0444455000, 0.0426674000, 0.0371784000, 0.0214707000, -0.034050600, -0.225538000, -0.850406700", \ - "0.0529207000, 0.0508729000, 0.0447423000, 0.0257731000, -0.034195000, -0.226101300, -0.850570300"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0352459000, 0.0370984000, 0.0431815000, 0.0627875000, 0.1240433000, 0.3173460000, 0.9377597000", \ - "0.0348994000, 0.0367251000, 0.0428280000, 0.0626215000, 0.1238822000, 0.3170619000, 0.9363928000", \ - "0.0346165000, 0.0364723000, 0.0425521000, 0.0623546000, 0.1236541000, 0.3169981000, 0.9388711000", \ - "0.0342458000, 0.0361000000, 0.0422027000, 0.0618820000, 0.1233086000, 0.3165759000, 0.9399334000", \ - "0.0340523000, 0.0358858000, 0.0419435000, 0.0614765000, 0.1226252000, 0.3161127000, 0.9363976000", \ - "0.0354089000, 0.0371923000, 0.0429965000, 0.0612362000, 0.1224440000, 0.3152548000, 0.9373385000", \ - "0.0369649000, 0.0386596000, 0.0443766000, 0.0631184000, 0.1230420000, 0.3156195000, 0.9339815000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0430353000, 0.0411739000, 0.0358115000, 0.0205105000, -0.034691400, -0.226051600, -0.850947200", \ - "0.0427847000, 0.0409430000, 0.0358425000, 0.0203843000, -0.034834300, -0.226340600, -0.851186800", \ - "0.0424475000, 0.0405546000, 0.0353112000, 0.0198995000, -0.035236500, -0.226697300, -0.851573400", \ - "0.0420354000, 0.0403004000, 0.0349262000, 0.0195810000, -0.035663000, -0.227111100, -0.851946300", \ - "0.0415580000, 0.0398134000, 0.0344628000, 0.0190226000, -0.036367100, -0.227684700, -0.852493800", \ - "0.0423874000, 0.0405541000, 0.0350424000, 0.0193355000, -0.036321400, -0.227760300, -0.852331700", \ - "0.0542434000, 0.0520001000, 0.0454990000, 0.0261681000, -0.032659800, -0.225355000, -0.850275600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0240264000, 0.0260792000, 0.0325039000, 0.0520580000, 0.1118664000, 0.3039243000, 0.9233464000", \ - "0.0239445000, 0.0259866000, 0.0324230000, 0.0519706000, 0.1118424000, 0.3039011000, 0.9239186000", \ - "0.0237323000, 0.0257321000, 0.0320857000, 0.0515570000, 0.1116545000, 0.3039013000, 0.9275183000", \ - "0.0232338000, 0.0251642000, 0.0314041000, 0.0507404000, 0.1109710000, 0.3029268000, 0.9207356000", \ - "0.0233640000, 0.0251964000, 0.0311067000, 0.0504307000, 0.1104745000, 0.3030241000, 0.9235364000", \ - "0.0248931000, 0.0266617000, 0.0324365000, 0.0512065000, 0.1105823000, 0.3022687000, 0.9223149000", \ - "0.0286964000, 0.0302440000, 0.0357174000, 0.0540921000, 0.1141410000, 0.3053202000, 0.9213523000"); - } - } - max_capacitance : 0.5603130000; - max_transition : 1.5019620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.1752514000, 0.1791203000, 0.1892402000, 0.2123169000, 0.2610626000, 0.3765588000, 0.7077884000", \ - "0.1810962000, 0.1849696000, 0.1948706000, 0.2179863000, 0.2669347000, 0.3822915000, 0.7138947000", \ - "0.1943133000, 0.1982127000, 0.2083303000, 0.2312909000, 0.2802480000, 0.3955737000, 0.7265627000", \ - "0.2243421000, 0.2282099000, 0.2382933000, 0.2611022000, 0.3100811000, 0.4255340000, 0.7563434000", \ - "0.2892406000, 0.2930873000, 0.3031748000, 0.3260370000, 0.3750517000, 0.4905000000, 0.8220858000", \ - "0.4156313000, 0.4199282000, 0.4310825000, 0.4562251000, 0.5083077000, 0.6263552000, 0.9575946000", \ - "0.6293223000, 0.6346536000, 0.6483119000, 0.6784631000, 0.7396329000, 0.8676851000, 1.2019676000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.1461379000, 0.1516169000, 0.1660870000, 0.2001547000, 0.2814216000, 0.5072767000, 1.2164513000", \ - "0.1493791000, 0.1548650000, 0.1693780000, 0.2034896000, 0.2847993000, 0.5105574000, 1.2197858000", \ - "0.1579377000, 0.1634175000, 0.1779224000, 0.2119935000, 0.2933181000, 0.5188925000, 1.2305049000", \ - "0.1781200000, 0.1836060000, 0.1981581000, 0.2322415000, 0.3134594000, 0.5393937000, 1.2486778000", \ - "0.2264467000, 0.2318251000, 0.2462109000, 0.2802640000, 0.3618031000, 0.5874718000, 1.2963699000", \ - "0.2969285000, 0.3027674000, 0.3175987000, 0.3521641000, 0.4342047000, 0.6609791000, 1.3700651000", \ - "0.3666661000, 0.3739380000, 0.3924625000, 0.4317737000, 0.5154365000, 0.7413850000, 1.4522047000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0252063000, 0.0274268000, 0.0340146000, 0.0509178000, 0.0943433000, 0.2239810000, 0.6630501000", \ - "0.0251819000, 0.0277002000, 0.0341288000, 0.0513620000, 0.0945233000, 0.2242965000, 0.6644656000", \ - "0.0250751000, 0.0274864000, 0.0341061000, 0.0506719000, 0.0944516000, 0.2245173000, 0.6635229000", \ - "0.0249974000, 0.0274492000, 0.0339728000, 0.0508639000, 0.0946908000, 0.2246556000, 0.6640458000", \ - "0.0250869000, 0.0274996000, 0.0341027000, 0.0511351000, 0.0944645000, 0.2244578000, 0.6637077000", \ - "0.0306109000, 0.0333115000, 0.0404313000, 0.0571171000, 0.0998780000, 0.2275906000, 0.6639230000", \ - "0.0428126000, 0.0456007000, 0.0539458000, 0.0724845000, 0.1175443000, 0.2413572000, 0.6663838000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0312085000, 0.0353777000, 0.0469587000, 0.0780061000, 0.1705116000, 0.4794298000, 1.5005253000", \ - "0.0312782000, 0.0353818000, 0.0470021000, 0.0779977000, 0.1701456000, 0.4781017000, 1.4991723000", \ - "0.0311815000, 0.0355123000, 0.0470612000, 0.0780472000, 0.1706938000, 0.4792934000, 1.5018078000", \ - "0.0314397000, 0.0354191000, 0.0471003000, 0.0779307000, 0.1700635000, 0.4785637000, 1.4991850000", \ - "0.0317072000, 0.0357172000, 0.0473698000, 0.0785319000, 0.1705057000, 0.4791598000, 1.4980269000", \ - "0.0369726000, 0.0405209000, 0.0516069000, 0.0813609000, 0.1737468000, 0.4806289000, 1.4997764000", \ - "0.0495075000, 0.0540569000, 0.0656182000, 0.0928751000, 0.1787961000, 0.4822752000, 1.4960329000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.2084035000, 0.2125618000, 0.2232894000, 0.2473198000, 0.2976568000, 0.4147988000, 0.7474036000", \ - "0.2141028000, 0.2182475000, 0.2289846000, 0.2530054000, 0.3037750000, 0.4206382000, 0.7526624000", \ - "0.2270611000, 0.2312170000, 0.2419979000, 0.2658729000, 0.3163270000, 0.4335012000, 0.7659363000", \ - "0.2571079000, 0.2612625000, 0.2719950000, 0.2960239000, 0.3464045000, 0.4635673000, 0.7962131000", \ - "0.3218594000, 0.3260863000, 0.3367729000, 0.3607606000, 0.4113594000, 0.5287186000, 0.8613418000", \ - "0.4549048000, 0.4593880000, 0.4709315000, 0.4965186000, 0.5488238000, 0.6676411000, 1.0002996000", \ - "0.6881120000, 0.6935225000, 0.7074501000, 0.7378831000, 0.7979073000, 0.9253940000, 1.2614298000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.1626114000, 0.1680796000, 0.1825323000, 0.2166310000, 0.2979694000, 0.5234292000, 1.2326098000", \ - "0.1664008000, 0.1718874000, 0.1863561000, 0.2203952000, 0.3016112000, 0.5275075000, 1.2359093000", \ - "0.1749747000, 0.1804399000, 0.1948829000, 0.2290173000, 0.3103465000, 0.5357770000, 1.2469841000", \ - "0.1949106000, 0.2003215000, 0.2148216000, 0.2489157000, 0.3302970000, 0.5554036000, 1.2652615000", \ - "0.2395660000, 0.2450639000, 0.2596316000, 0.2937328000, 0.3750100000, 0.6003534000, 1.3094026000", \ - "0.3114933000, 0.3174848000, 0.3330377000, 0.3687185000, 0.4516343000, 0.6788103000, 1.3884410000", \ - "0.3895433000, 0.3970293000, 0.4159512000, 0.4567584000, 0.5429120000, 0.7698433000, 1.4798712000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0280233000, 0.0305922000, 0.0374384000, 0.0536687000, 0.0970564000, 0.2272409000, 0.6651744000", \ - "0.0280287000, 0.0305559000, 0.0371153000, 0.0540799000, 0.0970824000, 0.2270634000, 0.6651681000", \ - "0.0282405000, 0.0304380000, 0.0372756000, 0.0537527000, 0.0977265000, 0.2273754000, 0.6653935000", \ - "0.0280445000, 0.0306069000, 0.0374313000, 0.0536709000, 0.0970642000, 0.2272310000, 0.6652914000", \ - "0.0280469000, 0.0306168000, 0.0371371000, 0.0537485000, 0.0975663000, 0.2270545000, 0.6646811000", \ - "0.0320994000, 0.0348362000, 0.0413300000, 0.0586628000, 0.1009492000, 0.2286762000, 0.6659718000", \ - "0.0435616000, 0.0467400000, 0.0539672000, 0.0720928000, 0.1161741000, 0.2414245000, 0.6674505000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0313448000, 0.0354562000, 0.0469858000, 0.0779929000, 0.1701743000, 0.4784647000, 1.5004373000", \ - "0.0312862000, 0.0354547000, 0.0470087000, 0.0781229000, 0.1701113000, 0.4788263000, 1.4971424000", \ - "0.0314535000, 0.0356178000, 0.0472135000, 0.0780695000, 0.1705415000, 0.4792411000, 1.5019579000", \ - "0.0314156000, 0.0354174000, 0.0471454000, 0.0781241000, 0.1700027000, 0.4785948000, 1.4981526000", \ - "0.0321451000, 0.0361981000, 0.0477292000, 0.0789871000, 0.1703809000, 0.4781920000, 1.4969748000", \ - "0.0363647000, 0.0407751000, 0.0523461000, 0.0826262000, 0.1738623000, 0.4807431000, 1.4988446000", \ - "0.0483433000, 0.0531669000, 0.0656092000, 0.0953566000, 0.1800782000, 0.4828592000, 1.4953170000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.2208521000, 0.2250906000, 0.2359925000, 0.2602206000, 0.3111092000, 0.4279598000, 0.7610656000", \ - "0.2264531000, 0.2306852000, 0.2416375000, 0.2659224000, 0.3163745000, 0.4336926000, 0.7663901000", \ - "0.2399870000, 0.2442265000, 0.2551599000, 0.2793772000, 0.3302593000, 0.4471772000, 0.7802277000", \ - "0.2707384000, 0.2749689000, 0.2859101000, 0.3101157000, 0.3606507000, 0.4779604000, 0.8110062000", \ - "0.3355239000, 0.3397513000, 0.3506417000, 0.3749287000, 0.4257578000, 0.5430787000, 0.8761012000", \ - "0.4714280000, 0.4760451000, 0.4875532000, 0.5129129000, 0.5646264000, 0.6825269000, 1.0158043000", \ - "0.7116703000, 0.7171012000, 0.7307890000, 0.7604968000, 0.8199454000, 0.9462263000, 1.2816578000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.1708478000, 0.1763283000, 0.1907895000, 0.2248420000, 0.3060447000, 0.5318668000, 1.2401106000", \ - "0.1745980000, 0.1800890000, 0.1945498000, 0.2286021000, 0.3098011000, 0.5355830000, 1.2440716000", \ - "0.1821749000, 0.1876431000, 0.2020933000, 0.2362389000, 0.3175778000, 0.5429726000, 1.2541402000", \ - "0.1979189000, 0.2033833000, 0.2177978000, 0.2518881000, 0.3332880000, 0.5584118000, 1.2680612000", \ - "0.2311284000, 0.2366685000, 0.2512844000, 0.2857349000, 0.3670065000, 0.5927756000, 1.3014522000", \ - "0.2873981000, 0.2933862000, 0.3090629000, 0.3450936000, 0.4282101000, 0.6550773000, 1.3673691000", \ - "0.3519727000, 0.3591384000, 0.3775853000, 0.4181636000, 0.5054936000, 0.7335346000, 1.4430807000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0290173000, 0.0315223000, 0.0388297000, 0.0544612000, 0.0978407000, 0.2268872000, 0.6660019000", \ - "0.0292310000, 0.0318142000, 0.0385830000, 0.0545914000, 0.0976621000, 0.2273587000, 0.6655940000", \ - "0.0290988000, 0.0316338000, 0.0384238000, 0.0545525000, 0.0978899000, 0.2274636000, 0.6660046000", \ - "0.0290727000, 0.0316210000, 0.0383773000, 0.0545987000, 0.0975420000, 0.2273429000, 0.6658036000", \ - "0.0292295000, 0.0318581000, 0.0381006000, 0.0546394000, 0.0979172000, 0.2269566000, 0.6650637000", \ - "0.0326398000, 0.0351477000, 0.0416795000, 0.0582123000, 0.0998739000, 0.2283109000, 0.6642956000", \ - "0.0427398000, 0.0457445000, 0.0542537000, 0.0708891000, 0.1143660000, 0.2396836000, 0.6670784000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0313287000, 0.0354644000, 0.0470112000, 0.0781220000, 0.1702678000, 0.4791021000, 1.4981816000", \ - "0.0313246000, 0.0355038000, 0.0470115000, 0.0781049000, 0.1704204000, 0.4792357000, 1.4990194000", \ - "0.0311882000, 0.0354433000, 0.0472385000, 0.0780886000, 0.1705334000, 0.4792319000, 1.5019620000", \ - "0.0313997000, 0.0355936000, 0.0471749000, 0.0780951000, 0.1700144000, 0.4785612000, 1.4980901000", \ - "0.0319956000, 0.0362022000, 0.0477943000, 0.0785111000, 0.1705290000, 0.4792566000, 1.4978659000", \ - "0.0354013000, 0.0397251000, 0.0514088000, 0.0824821000, 0.1734943000, 0.4796122000, 1.5001551000", \ - "0.0460240000, 0.0505819000, 0.0626674000, 0.0940170000, 0.1800051000, 0.4826735000, 1.4964869000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.2410485000, 0.2454709000, 0.2568412000, 0.2819583000, 0.3340698000, 0.4524888000, 0.7864164000", \ - "0.2460859000, 0.2505167000, 0.2618473000, 0.2868881000, 0.3391378000, 0.4574795000, 0.7917172000", \ - "0.2592834000, 0.2636923000, 0.2750424000, 0.3000772000, 0.3520401000, 0.4707898000, 0.8049722000", \ - "0.2888771000, 0.2933018000, 0.3046834000, 0.3298137000, 0.3819035000, 0.5003815000, 0.8343762000", \ - "0.3502996000, 0.3547797000, 0.3660220000, 0.3910245000, 0.4431869000, 0.5621863000, 0.8961218000", \ - "0.4789627000, 0.4835849000, 0.4955052000, 0.5213801000, 0.5743657000, 0.6936326000, 1.0278260000", \ - "0.7046645000, 0.7099994000, 0.7241543000, 0.7539749000, 0.8138581000, 0.9405312000, 1.2772817000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.1761856000, 0.1816757000, 0.1961402000, 0.2301902000, 0.3113901000, 0.5371392000, 1.2456103000", \ - "0.1800949000, 0.1855772000, 0.2000881000, 0.2342394000, 0.3155481000, 0.5411459000, 1.2499256000", \ - "0.1879246000, 0.1934088000, 0.2079332000, 0.2421238000, 0.3234292000, 0.5485477000, 1.2577395000", \ - "0.2025091000, 0.2079813000, 0.2224550000, 0.2567253000, 0.3379951000, 0.5631967000, 1.2737137000", \ - "0.2303163000, 0.2358227000, 0.2503042000, 0.2846393000, 0.3659616000, 0.5916156000, 1.3003612000", \ - "0.2751373000, 0.2810445000, 0.2965994000, 0.3325309000, 0.4157631000, 0.6418768000, 1.3506855000", \ - "0.3292962000, 0.3361681000, 0.3540822000, 0.3940359000, 0.4812716000, 0.7094981000, 1.4178754000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0312560000, 0.0338341000, 0.0407997000, 0.0572744000, 0.1003391000, 0.2299890000, 0.6656039000", \ - "0.0311327000, 0.0336976000, 0.0411793000, 0.0567406000, 0.1001514000, 0.2294996000, 0.6677875000", \ - "0.0312299000, 0.0340222000, 0.0408639000, 0.0570483000, 0.1004597000, 0.2299502000, 0.6671865000", \ - "0.0312294000, 0.0337930000, 0.0407461000, 0.0572572000, 0.1002958000, 0.2298046000, 0.6682758000", \ - "0.0312520000, 0.0338740000, 0.0411378000, 0.0575608000, 0.0998021000, 0.2294376000, 0.6677904000", \ - "0.0339923000, 0.0365755000, 0.0432951000, 0.0595861000, 0.1022825000, 0.2306543000, 0.6678573000", \ - "0.0437593000, 0.0469199000, 0.0548762000, 0.0716434000, 0.1150917000, 0.2409118000, 0.6685779000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0313309000, 0.0355146000, 0.0470147000, 0.0781027000, 0.1704333000, 0.4792434000, 1.4991051000", \ - "0.0314525000, 0.0354559000, 0.0472843000, 0.0779579000, 0.1704301000, 0.4791403000, 1.5003612000", \ - "0.0315719000, 0.0356266000, 0.0472609000, 0.0779706000, 0.1704370000, 0.4789264000, 1.4975199000", \ - "0.0311329000, 0.0353449000, 0.0471723000, 0.0780804000, 0.1702056000, 0.4790275000, 1.5010134000", \ - "0.0317766000, 0.0358824000, 0.0474277000, 0.0785842000, 0.1708894000, 0.4793825000, 1.4997511000", \ - "0.0346567000, 0.0391544000, 0.0509248000, 0.0823933000, 0.1735508000, 0.4792481000, 1.4982235000", \ - "0.0428182000, 0.0472415000, 0.0599733000, 0.0917148000, 0.1800962000, 0.4822683000, 1.4981930000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.2072282000, 0.2116229000, 0.2229969000, 0.2480858000, 0.3003378000, 0.4191678000, 0.7535192000", \ - "0.2111326000, 0.2155620000, 0.2268983000, 0.2521068000, 0.3043012000, 0.4229365000, 0.7575783000", \ - "0.2214330000, 0.2258442000, 0.2372230000, 0.2620876000, 0.3139860000, 0.4330377000, 0.7671114000", \ - "0.2478567000, 0.2522755000, 0.2638543000, 0.2888894000, 0.3409798000, 0.4600459000, 0.7942103000", \ - "0.3142416000, 0.3186885000, 0.3299579000, 0.3549964000, 0.4071320000, 0.5261432000, 0.8605729000", \ - "0.4635771000, 0.4684100000, 0.4807453000, 0.5068427000, 0.5597615000, 0.6788016000, 1.0135619000", \ - "0.7089455000, 0.7152285000, 0.7309564000, 0.7640402000, 0.8240074000, 0.9478859000, 1.2849117000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0570989000, 0.0609560000, 0.0717899000, 0.1002234000, 0.1730440000, 0.3932248000, 1.0984375000", \ - "0.0618867000, 0.0657577000, 0.0765858000, 0.1050187000, 0.1779049000, 0.3978622000, 1.1054031000", \ - "0.0730108000, 0.0768356000, 0.0875808000, 0.1159710000, 0.1890914000, 0.4087506000, 1.1164475000", \ - "0.0951134000, 0.0991041000, 0.1101411000, 0.1386601000, 0.2119098000, 0.4315735000, 1.1478953000", \ - "0.1247925000, 0.1297778000, 0.1428091000, 0.1738966000, 0.2486437000, 0.4693222000, 1.1772505000", \ - "0.1552133000, 0.1620376000, 0.1798279000, 0.2180873000, 0.2970146000, 0.5180440000, 1.2279460000", \ - "0.1659175000, 0.1750542000, 0.1994561000, 0.2523741000, 0.3432131000, 0.5656097000, 1.2708894000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0313910000, 0.0340692000, 0.0403322000, 0.0574984000, 0.1002465000, 0.2292491000, 0.6677858000", \ - "0.0312936000, 0.0340093000, 0.0404162000, 0.0571154000, 0.1002455000, 0.2296427000, 0.6678712000", \ - "0.0315374000, 0.0337304000, 0.0404813000, 0.0573342000, 0.1004623000, 0.2296777000, 0.6678723000", \ - "0.0313809000, 0.0340219000, 0.0405700000, 0.0577597000, 0.1004392000, 0.2297419000, 0.6674458000", \ - "0.0312466000, 0.0336636000, 0.0411964000, 0.0574809000, 0.1002981000, 0.2295139000, 0.6651223000", \ - "0.0367009000, 0.0390709000, 0.0454577000, 0.0608918000, 0.1024936000, 0.2298953000, 0.6673047000", \ - "0.0539706000, 0.0576017000, 0.0645313000, 0.0808044000, 0.1185278000, 0.2392599000, 0.6693164000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0187345000, 0.0222924000, 0.0334262000, 0.0646484000, 0.1576572000, 0.4716914000, 1.4957987000", \ - "0.0187035000, 0.0222944000, 0.0333752000, 0.0646505000, 0.1576898000, 0.4721440000, 1.4942688000", \ - "0.0187314000, 0.0223507000, 0.0334839000, 0.0646321000, 0.1577190000, 0.4701748000, 1.5001480000", \ - "0.0209076000, 0.0243064000, 0.0348916000, 0.0652364000, 0.1576108000, 0.4714336000, 1.4966234000", \ - "0.0281409000, 0.0315719000, 0.0418864000, 0.0704077000, 0.1595496000, 0.4720082000, 1.4969825000", \ - "0.0410716000, 0.0456649000, 0.0577893000, 0.0839021000, 0.1653925000, 0.4708894000, 1.4938556000", \ - "0.0615857000, 0.0679530000, 0.0844398000, 0.1138514000, 0.1817333000, 0.4741884000, 1.4864959000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41oi_1") { - leakage_power () { - value : 0.0022593000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003614000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003679000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003678000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0003867000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003689000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003886000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003882000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0007368000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003745000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003943000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003939000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0007331000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003994000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0007391000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0022593000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0007256000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0002356000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0022626000; - when : "A1&A2&A3&A4&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__a41oi"; - cell_leakage_power : 0.0013598110; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0022370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046728000, 0.0046699000, 0.0046631000, 0.0046606000, 0.0046549000, 0.0046416000, 0.0046112000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003510200, -0.003514200, -0.003523500, -0.003515300, -0.003496500, -0.003453200, -0.003353300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022870000; - } - pin ("A2") { - capacitance : 0.0022940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043042000, 0.0043062000, 0.0043109000, 0.0043250000, 0.0043574000, 0.0044322000, 0.0046045000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003983800, -0.003981800, -0.003977100, -0.003976600, -0.003975300, -0.003972300, -0.003965400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023690000; - } - pin ("A3") { - capacitance : 0.0023330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039420000, 0.0039477000, 0.0039608000, 0.0039598000, 0.0039575000, 0.0039520000, 0.0039396000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003964400, -0.003962500, -0.003958100, -0.003957600, -0.003956500, -0.003954100, -0.003948500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024260000; - } - pin ("A4") { - capacitance : 0.0023820000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040334000, 0.0040330000, 0.0040320000, 0.0040290000, 0.0040219000, 0.0040057000, 0.0039684000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004015700, -0.004015300, -0.004014300, -0.004014600, -0.004015200, -0.004016500, -0.004019700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025040000; - } - pin ("B1") { - capacitance : 0.0023260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0054107000, 0.0053994000, 0.0053733000, 0.0053977000, 0.0054540000, 0.0055836000, 0.0058826000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001767000, -0.001768200, -0.001771100, -0.001770200, -0.001768000, -0.001763000, -0.001751500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024850000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1) | (!A4&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0060995000, 0.0050944000, 0.0028508000, -0.002247200, -0.013867700, -0.040077400, -0.099432000", \ - "0.0059815000, 0.0049906000, 0.0027370000, -0.002362600, -0.013941800, -0.040169900, -0.099470400", \ - "0.0058220000, 0.0048010000, 0.0025672000, -0.002502800, -0.014028800, -0.040258700, -0.099597600", \ - "0.0055912000, 0.0046033000, 0.0023779000, -0.002676300, -0.014198600, -0.040385400, -0.099659100", \ - "0.0054228000, 0.0044442000, 0.0022249000, -0.002853400, -0.014327400, -0.040498200, -0.099778300", \ - "0.0056049000, 0.0045696000, 0.0022675000, -0.002924700, -0.014407500, -0.040553200, -0.099779000", \ - "0.0068480000, 0.0058210000, 0.0033961000, -0.001915600, -0.013715000, -0.040184500, -0.099733600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0097889000, 0.0108533000, 0.0132186000, 0.0183847000, 0.0299775000, 0.0562534000, 0.1146711000", \ - "0.0096215000, 0.0107231000, 0.0131071000, 0.0183243000, 0.0299773000, 0.0560355000, 0.1147731000", \ - "0.0093839000, 0.0104620000, 0.0128851000, 0.0181462000, 0.0300802000, 0.0560573000, 0.1147966000", \ - "0.0091590000, 0.0102179000, 0.0125911000, 0.0179178000, 0.0296385000, 0.0558701000, 0.1147392000", \ - "0.0089997000, 0.0100442000, 0.0123640000, 0.0175979000, 0.0294180000, 0.0560040000, 0.1145298000", \ - "0.0089782000, 0.0100015000, 0.0123138000, 0.0175533000, 0.0291667000, 0.0555194000, 0.1147334000", \ - "0.0090043000, 0.0099550000, 0.0122557000, 0.0174049000, 0.0292480000, 0.0554480000, 0.1144380000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0066582000, 0.0056663000, 0.0033903000, -0.001719600, -0.013300800, -0.039524200, -0.098891000", \ - "0.0065561000, 0.0055565000, 0.0033044000, -0.001820000, -0.013397300, -0.039605800, -0.098933500", \ - "0.0064084000, 0.0054095000, 0.0031639000, -0.001937200, -0.013512100, -0.039716400, -0.099058800", \ - "0.0062162000, 0.0052248000, 0.0029938000, -0.002066500, -0.013606600, -0.039812800, -0.099090100", \ - "0.0060087000, 0.0050356000, 0.0027697000, -0.002232700, -0.013725200, -0.039896700, -0.099155800", \ - "0.0061325000, 0.0051151000, 0.0027680000, -0.002348300, -0.013882300, -0.040015900, -0.099226400", \ - "0.0068323000, 0.0057881000, 0.0034740000, -0.001828400, -0.013562000, -0.039985800, -0.099241400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0130060000, 0.0140372000, 0.0163445000, 0.0215075000, 0.0330634000, 0.0591273000, 0.1177617000", \ - "0.0128780000, 0.0139225000, 0.0162483000, 0.0214317000, 0.0330486000, 0.0591218000, 0.1177830000", \ - "0.0126264000, 0.0136803000, 0.0160409000, 0.0212876000, 0.0329658000, 0.0590813000, 0.1177699000", \ - "0.0123689000, 0.0133952000, 0.0157567000, 0.0210234000, 0.0327452000, 0.0589115000, 0.1176948000", \ - "0.0121787000, 0.0132019000, 0.0155028000, 0.0207258000, 0.0324223000, 0.0586423000, 0.1174961000", \ - "0.0120205000, 0.0130555000, 0.0153659000, 0.0205563000, 0.0322630000, 0.0584109000, 0.1171295000", \ - "0.0116730000, 0.0127064000, 0.0149476000, 0.0203037000, 0.0320814000, 0.0583172000, 0.1170165000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0066477000, 0.0056573000, 0.0033784000, -0.001735100, -0.013324700, -0.039534400, -0.098855300", \ - "0.0065550000, 0.0055661000, 0.0032919000, -0.001826500, -0.013413500, -0.039637800, -0.098963500", \ - "0.0064111000, 0.0054053000, 0.0031635000, -0.001939900, -0.013497000, -0.039709000, -0.099034000", \ - "0.0062046000, 0.0052148000, 0.0029694000, -0.002088600, -0.013614900, -0.039808600, -0.099147300", \ - "0.0060389000, 0.0050775000, 0.0028576000, -0.002201200, -0.013746900, -0.039914800, -0.099176100", \ - "0.0060696000, 0.0050579000, 0.0027897000, -0.002452000, -0.013868600, -0.040002500, -0.099254600", \ - "0.0065973000, 0.0055434000, 0.0032386000, -0.001956100, -0.013661900, -0.040071400, -0.099294700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0159427000, 0.0169552000, 0.0192771000, 0.0244351000, 0.0360545000, 0.0621035000, 0.1208094000", \ - "0.0158148000, 0.0168428000, 0.0191628000, 0.0243440000, 0.0359516000, 0.0620276000, 0.1207497000", \ - "0.0155936000, 0.0166425000, 0.0189697000, 0.0242000000, 0.0358433000, 0.0619530000, 0.1206935000", \ - "0.0153660000, 0.0164094000, 0.0187365000, 0.0239787000, 0.0356862000, 0.0618592000, 0.1207233000", \ - "0.0152092000, 0.0162389000, 0.0185630000, 0.0238036000, 0.0354858000, 0.0616576000, 0.1205076000", \ - "0.0151543000, 0.0161898000, 0.0185656000, 0.0237291000, 0.0354192000, 0.0614645000, 0.1203928000", \ - "0.0150161000, 0.0159977000, 0.0182418000, 0.0236940000, 0.0353799000, 0.0617054000, 0.1203812000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0067196000, 0.0057109000, 0.0034517000, -0.001673700, -0.013242800, -0.039470200, -0.098780000", \ - "0.0066319000, 0.0056215000, 0.0033655000, -0.001762500, -0.013317900, -0.039534400, -0.098885100", \ - "0.0064604000, 0.0054886000, 0.0032238000, -0.001877700, -0.013426800, -0.039628400, -0.098983200", \ - "0.0062252000, 0.0052415000, 0.0030167000, -0.002031100, -0.013548600, -0.039750100, -0.099057600", \ - "0.0060564000, 0.0050893000, 0.0028730000, -0.002172400, -0.013727200, -0.039846900, -0.099101300", \ - "0.0061063000, 0.0050869000, 0.0028093000, -0.002408200, -0.013874600, -0.039980200, -0.099187600", \ - "0.0065374000, 0.0055045000, 0.0031874000, -0.001991500, -0.013610400, -0.040040500, -0.099218500"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0182751000, 0.0192874000, 0.0216259000, 0.0268309000, 0.0384327000, 0.0645827000, 0.1233502000", \ - "0.0181569000, 0.0191962000, 0.0215488000, 0.0267275000, 0.0383902000, 0.0644968000, 0.1232192000", \ - "0.0180281000, 0.0190537000, 0.0213732000, 0.0265996000, 0.0382667000, 0.0645210000, 0.1232006000", \ - "0.0178823000, 0.0189058000, 0.0212355000, 0.0264782000, 0.0381546000, 0.0643540000, 0.1231505000", \ - "0.0177383000, 0.0187687000, 0.0211023000, 0.0263210000, 0.0380181000, 0.0642319000, 0.1229658000", \ - "0.0177137000, 0.0187549000, 0.0211055000, 0.0262818000, 0.0380580000, 0.0642663000, 0.1230137000", \ - "0.0176435000, 0.0186195000, 0.0208875000, 0.0263131000, 0.0380876000, 0.0642690000, 0.1231301000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0001685000, -0.000789000, -0.003001800, -0.008106800, -0.019741700, -0.046066000, -0.105508200", \ - "4.360000e-05, -0.000894400, -0.003068200, -0.008116800, -0.019702900, -0.046000500, -0.105425100", \ - "-0.000133500, -0.001031500, -0.003175400, -0.008198000, -0.019708800, -0.045953700, -0.105349300", \ - "-0.000381100, -0.001293600, -0.003413200, -0.008379700, -0.019830300, -0.045996100, -0.105343900", \ - "-0.000196100, -0.001164600, -0.003487900, -0.008615700, -0.020060800, -0.046120800, -0.105415500", \ - "0.0002234000, -0.000756100, -0.003074200, -0.008452700, -0.020061700, -0.046308300, -0.105384100", \ - "0.0018937000, 0.0007502000, -0.001765900, -0.007248400, -0.019276000, -0.045487100, -0.105106400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011280280, 0.0025448950, 0.0057414260, 0.0129529800, 0.0292226500, 0.0659279500"); - values("0.0139250000, 0.0149751000, 0.0173405000, 0.0226485000, 0.0344397000, 0.0606564000, 0.1194996000", \ - "0.0137809000, 0.0148128000, 0.0172167000, 0.0225001000, 0.0342671000, 0.0605538000, 0.1192591000", \ - "0.0135613000, 0.0146282000, 0.0169929000, 0.0222473000, 0.0341412000, 0.0604311000, 0.1193094000", \ - "0.0133699000, 0.0145121000, 0.0167801000, 0.0220217000, 0.0338066000, 0.0601767000, 0.1191596000", \ - "0.0133452000, 0.0143517000, 0.0166599000, 0.0218551000, 0.0335893000, 0.0599158000, 0.1188496000", \ - "0.0136380000, 0.0146394000, 0.0169034000, 0.0220693000, 0.0336303000, 0.0597378000, 0.1185179000", \ - "0.0154798000, 0.0163220000, 0.0183705000, 0.0231902000, 0.0346141000, 0.0601464000, 0.1189402000"); - } - } - max_capacitance : 0.0659280000; - max_transition : 1.4804940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0549117000, 0.0611283000, 0.0745896000, 0.1037092000, 0.1671110000, 0.3062582000, 0.6176848000", \ - "0.0583303000, 0.0644877000, 0.0782859000, 0.1075659000, 0.1704357000, 0.3098381000, 0.6217307000", \ - "0.0668982000, 0.0728736000, 0.0865879000, 0.1159094000, 0.1791167000, 0.3186731000, 0.6300858000", \ - "0.0885946000, 0.0951778000, 0.1082019000, 0.1370807000, 0.2007458000, 0.3405505000, 0.6520189000", \ - "0.1224387000, 0.1313887000, 0.1497953000, 0.1854619000, 0.2510298000, 0.3902353000, 0.7016868000", \ - "0.1580974000, 0.1713852000, 0.1982914000, 0.2508778000, 0.3457133000, 0.5043940000, 0.8161129000", \ - "0.1756700000, 0.1950606000, 0.2357616000, 0.3140271000, 0.4556041000, 0.6940489000, 1.0844970000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0950847000, 0.1050714000, 0.1270144000, 0.1756578000, 0.2833077000, 0.5276660000, 1.0723972000", \ - "0.0996092000, 0.1097354000, 0.1319580000, 0.1808193000, 0.2892780000, 0.5332060000, 1.0785431000", \ - "0.1117353000, 0.1219109000, 0.1441368000, 0.1935224000, 0.3043135000, 0.5457609000, 1.0921930000", \ - "0.1405073000, 0.1508378000, 0.1729552000, 0.2224408000, 0.3319336000, 0.5761985000, 1.1230328000", \ - "0.1977980000, 0.2093363000, 0.2335237000, 0.2834357000, 0.3924995000, 0.6381486000, 1.1850666000", \ - "0.2894799000, 0.3061516000, 0.3390299000, 0.4053506000, 0.5279498000, 0.7743912000, 1.3219186000", \ - "0.4289800000, 0.4554137000, 0.5088805000, 0.6075882000, 0.7811197000, 1.0824663000, 1.6398813000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0597870000, 0.0665832000, 0.0827981000, 0.1191467000, 0.2013245000, 0.3864311000, 0.8050489000", \ - "0.0594571000, 0.0665670000, 0.0826475000, 0.1192947000, 0.2010708000, 0.3868366000, 0.8050950000", \ - "0.0576433000, 0.0649640000, 0.0820963000, 0.1190083000, 0.2010924000, 0.3865435000, 0.8048111000", \ - "0.0633084000, 0.0694423000, 0.0844565000, 0.1187175000, 0.2007207000, 0.3864416000, 0.8042066000", \ - "0.0864356000, 0.0944976000, 0.1104226000, 0.1429519000, 0.2117680000, 0.3873843000, 0.8048436000", \ - "0.1321641000, 0.1426144000, 0.1643392000, 0.2055717000, 0.2841083000, 0.4326317000, 0.8106377000", \ - "0.2123989000, 0.2279524000, 0.2621500000, 0.3217611000, 0.4248329000, 0.6065353000, 0.9366534000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0650225000, 0.0778597000, 0.1070023000, 0.1722639000, 0.3191721000, 0.6532106000, 1.3953211000", \ - "0.0648011000, 0.0778787000, 0.1070476000, 0.1720072000, 0.3192732000, 0.6498659000, 1.3978464000", \ - "0.0650932000, 0.0779414000, 0.1070534000, 0.1724965000, 0.3209716000, 0.6525675000, 1.3970263000", \ - "0.0657266000, 0.0783154000, 0.1070906000, 0.1723184000, 0.3188553000, 0.6497018000, 1.3991419000", \ - "0.0795151000, 0.0906604000, 0.1156901000, 0.1763028000, 0.3200941000, 0.6553250000, 1.3976250000", \ - "0.1183483000, 0.1311897000, 0.1585744000, 0.2181772000, 0.3440099000, 0.6553990000, 1.4018826000", \ - "0.2026081000, 0.2193289000, 0.2543430000, 0.3219018000, 0.4579463000, 0.7360973000, 1.4190464000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0661880000, 0.0725304000, 0.0859071000, 0.1148953000, 0.1780707000, 0.3176423000, 0.6289337000", \ - "0.0698323000, 0.0761449000, 0.0896106000, 0.1186410000, 0.1819114000, 0.3213188000, 0.6328274000", \ - "0.0781979000, 0.0843980000, 0.0980991000, 0.1272537000, 0.1905396000, 0.3301218000, 0.6413005000", \ - "0.0973868000, 0.1039208000, 0.1176110000, 0.1471122000, 0.2105520000, 0.3502391000, 0.6623849000", \ - "0.1301083000, 0.1387197000, 0.1549000000, 0.1898550000, 0.2567581000, 0.3968322000, 0.7092024000", \ - "0.1668714000, 0.1790399000, 0.2047214000, 0.2529245000, 0.3420385000, 0.5010511000, 0.8176189000", \ - "0.1841726000, 0.2027701000, 0.2400810000, 0.3152944000, 0.4494088000, 0.6747096000, 1.0526566000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1203683000, 0.1303969000, 0.1526614000, 0.2020873000, 0.3126920000, 0.5610269000, 1.1202670000", \ - "0.1253203000, 0.1356281000, 0.1580995000, 0.2079888000, 0.3188955000, 0.5673047000, 1.1269630000", \ - "0.1378279000, 0.1481648000, 0.1708692000, 0.2209240000, 0.3324047000, 0.5812792000, 1.1410473000", \ - "0.1679412000, 0.1779355000, 0.2005043000, 0.2509297000, 0.3627885000, 0.6124114000, 1.1728308000", \ - "0.2317737000, 0.2426665000, 0.2651954000, 0.3151104000, 0.4267573000, 0.6768173000, 1.2378174000", \ - "0.3435208000, 0.3586471000, 0.3892008000, 0.4506182000, 0.5714393000, 0.8218215000, 1.3858987000", \ - "0.5278284000, 0.5509861000, 0.5970541000, 0.6880642000, 0.8528505000, 1.1505490000, 1.7181232000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0590540000, 0.0661301000, 0.0824082000, 0.1188907000, 0.2010647000, 0.3864173000, 0.8051277000", \ - "0.0590553000, 0.0661422000, 0.0824817000, 0.1189633000, 0.2011495000, 0.3862877000, 0.8048742000", \ - "0.0586115000, 0.0657956000, 0.0823586000, 0.1188975000, 0.2009692000, 0.3863600000, 0.8048777000", \ - "0.0622837000, 0.0689091000, 0.0842548000, 0.1193932000, 0.2009667000, 0.3863674000, 0.8044954000", \ - "0.0813591000, 0.0886697000, 0.1031423000, 0.1359749000, 0.2089573000, 0.3870013000, 0.8046385000", \ - "0.1238984000, 0.1328963000, 0.1518609000, 0.1899548000, 0.2618877000, 0.4172830000, 0.8097448000", \ - "0.2023426000, 0.2152732000, 0.2412243000, 0.2928275000, 0.3854082000, 0.5566152000, 0.8983139000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0840423000, 0.0974252000, 0.1272488000, 0.1942215000, 0.3445093000, 0.6828572000, 1.4445297000", \ - "0.0841001000, 0.0974203000, 0.1271575000, 0.1939959000, 0.3458455000, 0.6830074000, 1.4449925000", \ - "0.0840041000, 0.0974484000, 0.1271708000, 0.1940001000, 0.3450257000, 0.6827578000, 1.4445621000", \ - "0.0843751000, 0.0975208000, 0.1272066000, 0.1940674000, 0.3445627000, 0.6829410000, 1.4486291000", \ - "0.0923618000, 0.1045650000, 0.1322612000, 0.1960513000, 0.3449580000, 0.6835722000, 1.4475799000", \ - "0.1316821000, 0.1445306000, 0.1722411000, 0.2308446000, 0.3626725000, 0.6862288000, 1.4518501000", \ - "0.2180545000, 0.2340596000, 0.2688328000, 0.3359566000, 0.4709770000, 0.7571869000, 1.4596921000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0733881000, 0.0797332000, 0.0931504000, 0.1222624000, 0.1855084000, 0.3247112000, 0.6361006000", \ - "0.0772350000, 0.0835430000, 0.0970246000, 0.1261643000, 0.1893774000, 0.3288839000, 0.6399608000", \ - "0.0851703000, 0.0912895000, 0.1050150000, 0.1339447000, 0.1972372000, 0.3367184000, 0.6483317000", \ - "0.1014232000, 0.1079012000, 0.1215194000, 0.1507524000, 0.2141554000, 0.3537736000, 0.6653536000", \ - "0.1296749000, 0.1376047000, 0.1532232000, 0.1857666000, 0.2521046000, 0.3922863000, 0.7044873000", \ - "0.1641392000, 0.1745082000, 0.1974883000, 0.2402958000, 0.3237842000, 0.4782338000, 0.7937195000", \ - "0.1763742000, 0.1930432000, 0.2280772000, 0.2954142000, 0.4163632000, 0.6221060000, 0.9840891000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1393479000, 0.1494059000, 0.1720791000, 0.2223117000, 0.3342367000, 0.5849456000, 1.1481376000", \ - "0.1444674000, 0.1547146000, 0.1771945000, 0.2278406000, 0.3398886000, 0.5905317000, 1.1540379000", \ - "0.1571991000, 0.1670759000, 0.1902998000, 0.2411164000, 0.3533735000, 0.6042929000, 1.1686719000", \ - "0.1872261000, 0.1975738000, 0.2206298000, 0.2713043000, 0.3844519000, 0.6357623000, 1.1993050000", \ - "0.2527991000, 0.2628938000, 0.2857411000, 0.3363200000, 0.4490132000, 0.7008597000, 1.2654241000", \ - "0.3749440000, 0.3878420000, 0.4177084000, 0.4770005000, 0.5952235000, 0.8471956000, 1.4120837000", \ - "0.5789684000, 0.5983537000, 0.6427591000, 0.7285262000, 0.8853125000, 1.1797250000, 1.7486224000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0589515000, 0.0660782000, 0.0824121000, 0.1188576000, 0.2012262000, 0.3864916000, 0.8041814000", \ - "0.0590136000, 0.0660242000, 0.0823722000, 0.1189415000, 0.2010373000, 0.3865227000, 0.8048418000", \ - "0.0586188000, 0.0658472000, 0.0821813000, 0.1188931000, 0.2007332000, 0.3865335000, 0.8047203000", \ - "0.0612432000, 0.0680593000, 0.0837420000, 0.1193521000, 0.2009223000, 0.3868381000, 0.8050001000", \ - "0.0760667000, 0.0829332000, 0.0979497000, 0.1312891000, 0.2066883000, 0.3871321000, 0.8047069000", \ - "0.1144891000, 0.1220860000, 0.1397242000, 0.1738789000, 0.2491539000, 0.4112963000, 0.8097726000", \ - "0.1906008000, 0.2014170000, 0.2238167000, 0.2692944000, 0.3536003000, 0.5203817000, 0.8823239000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1003786000, 0.1136694000, 0.1438262000, 0.2111415000, 0.3628488000, 0.7042045000, 1.4692291000", \ - "0.1002674000, 0.1137309000, 0.1438134000, 0.2113418000, 0.3626137000, 0.7030190000, 1.4682839000", \ - "0.1003741000, 0.1136484000, 0.1437878000, 0.2114947000, 0.3626147000, 0.7029373000, 1.4757832000", \ - "0.1003344000, 0.1136496000, 0.1437944000, 0.2112863000, 0.3625499000, 0.7031689000, 1.4704521000", \ - "0.1055278000, 0.1183135000, 0.1469751000, 0.2118811000, 0.3630692000, 0.7025248000, 1.4706519000", \ - "0.1428724000, 0.1557340000, 0.1839144000, 0.2431242000, 0.3778052000, 0.7051378000, 1.4712130000", \ - "0.2300160000, 0.2456103000, 0.2787824000, 0.3463421000, 0.4813538000, 0.7716852000, 1.4804943000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0780667000, 0.0841888000, 0.0978169000, 0.1267545000, 0.1899541000, 0.3295287000, 0.6407870000", \ - "0.0820585000, 0.0881581000, 0.1018266000, 0.1307819000, 0.1939916000, 0.3334978000, 0.6447570000", \ - "0.0895535000, 0.0959315000, 0.1095173000, 0.1387356000, 0.2019565000, 0.3415210000, 0.6527706000", \ - "0.1043350000, 0.1106526000, 0.1242621000, 0.1536514000, 0.2170310000, 0.3569446000, 0.6683814000", \ - "0.1278906000, 0.1353515000, 0.1506179000, 0.1824190000, 0.2481161000, 0.3880830000, 0.7003985000", \ - "0.1592041000, 0.1678954000, 0.1876036000, 0.2272960000, 0.3044655000, 0.4563918000, 0.7708512000", \ - "0.1697516000, 0.1839793000, 0.2141679000, 0.2731766000, 0.3812078000, 0.5698604000, 0.9238159000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1465076000, 0.1562719000, 0.1779090000, 0.2263824000, 0.3326070000, 0.5690062000, 1.0993726000", \ - "0.1516609000, 0.1612977000, 0.1837142000, 0.2315392000, 0.3380632000, 0.5748153000, 1.1046378000", \ - "0.1647499000, 0.1751493000, 0.1969079000, 0.2453091000, 0.3519768000, 0.5883400000, 1.1186790000", \ - "0.1956606000, 0.2060982000, 0.2278065000, 0.2761396000, 0.3830322000, 0.6201328000, 1.1504748000", \ - "0.2625363000, 0.2726457000, 0.2946607000, 0.3428568000, 0.4498561000, 0.6868243000, 1.2174514000", \ - "0.3913351000, 0.4035785000, 0.4306704000, 0.4867923000, 0.5983677000, 0.8353719000, 1.3665128000", \ - "0.6072396000, 0.6256473000, 0.6663196000, 0.7447131000, 0.8958767000, 1.1724153000, 1.7095803000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0589177000, 0.0662417000, 0.0825178000, 0.1189528000, 0.2010232000, 0.3862410000, 0.8040770000", \ - "0.0588855000, 0.0662156000, 0.0825104000, 0.1189461000, 0.2009721000, 0.3861135000, 0.8044141000", \ - "0.0588700000, 0.0659295000, 0.0822513000, 0.1189302000, 0.2011141000, 0.3860557000, 0.8046756000", \ - "0.0603290000, 0.0672641000, 0.0831596000, 0.1191265000, 0.2006640000, 0.3860458000, 0.8051568000", \ - "0.0706916000, 0.0777173000, 0.0935111000, 0.1279546000, 0.2054432000, 0.3870703000, 0.8040535000", \ - "0.1011043000, 0.1079343000, 0.1246320000, 0.1599044000, 0.2365985000, 0.4058505000, 0.8090601000", \ - "0.1703427000, 0.1794406000, 0.1995755000, 0.2396916000, 0.3230702000, 0.4916815000, 0.8678150000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1081894000, 0.1210390000, 0.1493365000, 0.2128478000, 0.3552837000, 0.6746171000, 1.3943193000", \ - "0.1084085000, 0.1208945000, 0.1492439000, 0.2128098000, 0.3547655000, 0.6743933000, 1.3941860000", \ - "0.1083279000, 0.1208308000, 0.1492596000, 0.2129629000, 0.3557207000, 0.6749210000, 1.3927522000", \ - "0.1082580000, 0.1209100000, 0.1492404000, 0.2127338000, 0.3549668000, 0.6751215000, 1.3942273000", \ - "0.1122330000, 0.1245829000, 0.1513119000, 0.2130271000, 0.3550582000, 0.6747899000, 1.3940943000", \ - "0.1493723000, 0.1612928000, 0.1873839000, 0.2424553000, 0.3701489000, 0.6762019000, 1.3933843000", \ - "0.2375659000, 0.2520708000, 0.2832906000, 0.3474776000, 0.4749190000, 0.7434292000, 1.4068995000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0179243000, 0.0201601000, 0.0250365000, 0.0355972000, 0.0593138000, 0.1126013000, 0.2326429000", \ - "0.0226047000, 0.0248595000, 0.0297983000, 0.0404985000, 0.0643217000, 0.1174725000, 0.2375616000", \ - "0.0315792000, 0.0344230000, 0.0405639000, 0.0518101000, 0.0755745000, 0.1287884000, 0.2489111000", \ - "0.0423246000, 0.0470506000, 0.0567083000, 0.0737568000, 0.1021468000, 0.1552940000, 0.2744399000", \ - "0.0512514000, 0.0588715000, 0.0745809000, 0.1015992000, 0.1460747000, 0.2157834000, 0.3361211000", \ - "0.0508727000, 0.0632671000, 0.0869262000, 0.1301059000, 0.2004047000, 0.3093363000, 0.4714276000", \ - "0.0180831000, 0.0370814000, 0.0747406000, 0.1411155000, 0.2509768000, 0.4217445000, 0.6781356000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1072137000, 0.1169902000, 0.1397082000, 0.1883199000, 0.2954942000, 0.5325089000, 1.0628706000", \ - "0.1108251000, 0.1208258000, 0.1432858000, 0.1923034000, 0.2995109000, 0.5367754000, 1.0674397000", \ - "0.1210082000, 0.1315568000, 0.1536783000, 0.2021208000, 0.3096821000, 0.5476313000, 1.0785978000", \ - "0.1475996000, 0.1575663000, 0.1791391000, 0.2280936000, 0.3353246000, 0.5736123000, 1.1053501000", \ - "0.2144625000, 0.2244666000, 0.2461935000, 0.2934284000, 0.3999203000, 0.6370904000, 1.1687211000", \ - "0.3327097000, 0.3476577000, 0.3782726000, 0.4400771000, 0.5531790000, 0.7868707000, 1.3167903000", \ - "0.5188726000, 0.5405788000, 0.5854994000, 0.6777531000, 0.8468435000, 1.1352197000, 1.6632783000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.0159435000, 0.0191264000, 0.0261915000, 0.0415933000, 0.0749120000, 0.1461465000, 0.3048059000", \ - "0.0164330000, 0.0193723000, 0.0261583000, 0.0416080000, 0.0749394000, 0.1461390000, 0.3047933000", \ - "0.0235352000, 0.0253203000, 0.0302984000, 0.0432643000, 0.0749568000, 0.1461635000, 0.3048681000", \ - "0.0418940000, 0.0439973000, 0.0486815000, 0.0586502000, 0.0832924000, 0.1472612000, 0.3050758000", \ - "0.0765849000, 0.0793394000, 0.0845785000, 0.0973089000, 0.1219998000, 0.1713193000, 0.3092391000", \ - "0.1335698000, 0.1371598000, 0.1461384000, 0.1635011000, 0.1983054000, 0.2603127000, 0.3758517000", \ - "0.2351591000, 0.2401783000, 0.2524807000, 0.2784296000, 0.3301401000, 0.4241383000, 0.5753784000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011280300, 0.0025449000, 0.0057414300, 0.0129530000, 0.0292227000, 0.0659279000"); - values("0.1082258000, 0.1209009000, 0.1492278000, 0.2124325000, 0.3549051000, 0.6749585000, 1.3932095000", \ - "0.1080750000, 0.1208131000, 0.1492105000, 0.2129485000, 0.3550461000, 0.6741958000, 1.3936790000", \ - "0.1079228000, 0.1208205000, 0.1493011000, 0.2127288000, 0.3551061000, 0.6744700000, 1.3947195000", \ - "0.1059422000, 0.1187270000, 0.1477407000, 0.2124527000, 0.3548638000, 0.6749032000, 1.3940301000", \ - "0.1228237000, 0.1333479000, 0.1583566000, 0.2158182000, 0.3541501000, 0.6745177000, 1.3930535000", \ - "0.1766572000, 0.1905569000, 0.2188487000, 0.2737529000, 0.3883923000, 0.6781091000, 1.3938852000", \ - "0.2716360000, 0.2927600000, 0.3341459000, 0.4104467000, 0.5457790000, 0.7944038000, 1.4216056000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41oi_2") { - leakage_power () { - value : 0.0027870000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0005851000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0005945000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0005952000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0006239000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0005976000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0006255000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0006284000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0013101000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0006073000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0006369000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0006408000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0011464000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0006549000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0011425000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027870000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0011452000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0003672000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0036311000; - when : "A1&A2&A3&A4&!B1"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__a41oi"; - cell_leakage_power : 0.0017917810; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0042020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088944000, 0.0088913000, 0.0088842000, 0.0088892000, 0.0089007000, 0.0089272000, 0.0089883000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006186500, -0.006189400, -0.006196000, -0.006177400, -0.006134600, -0.006035900, -0.005808300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0042980000; - } - pin ("A2") { - capacitance : 0.0042180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083915000, 0.0083859000, 0.0083729000, 0.0084054000, 0.0084804000, 0.0086531000, 0.0090513000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007747800, -0.007748400, -0.007749800, -0.007749400, -0.007748300, -0.007745900, -0.007740400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043440000; - } - pin ("A3") { - capacitance : 0.0044070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078703000, 0.0078685000, 0.0078644000, 0.0078661000, 0.0078700000, 0.0078791000, 0.0079000000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007866400, -0.007865300, -0.007862900, -0.007862100, -0.007860000, -0.007855400, -0.007844600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045630000; - } - pin ("A4") { - capacitance : 0.0044300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078698000, 0.0078774000, 0.0078950000, 0.0078967000, 0.0079008000, 0.0079102000, 0.0079318000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007902200, -0.007895900, -0.007881300, -0.007881200, -0.007881000, -0.007880500, -0.007879300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046590000; - } - pin ("B1") { - capacitance : 0.0044770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042672000, 0.0042562000, 0.0042306000, 0.0042687000, 0.0043565000, 0.0045588000, 0.0050252000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003443700, -0.003440000, -0.003431500, -0.003430500, -0.003428200, -0.003423000, -0.003411100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048210000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1) | (!A4&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0101480000, 0.0089211000, 0.0059303000, -0.001642300, -0.020770100, -0.068855000, -0.189867000", \ - "0.0099167000, 0.0087192000, 0.0057303000, -0.001803700, -0.020939600, -0.069005100, -0.190036600", \ - "0.0095501000, 0.0083641000, 0.0053357000, -0.002114600, -0.021141500, -0.069210600, -0.190219800", \ - "0.0090114000, 0.0078364000, 0.0049172000, -0.002552400, -0.021492700, -0.069468200, -0.190452200", \ - "0.0085945000, 0.0074299000, 0.0045532000, -0.002944300, -0.021823700, -0.069751300, -0.190544800", \ - "0.0088385000, 0.0078847000, 0.0045016000, -0.003137400, -0.022061300, -0.069833300, -0.190827600", \ - "0.0106820000, 0.0094348000, 0.0062665000, -0.001656000, -0.021300100, -0.069792300, -0.190896400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0143894000, 0.0157355000, 0.0189862000, 0.0268481000, 0.0461742000, 0.0939977000, 0.2135740000", \ - "0.0140594000, 0.0154261000, 0.0187261000, 0.0266549000, 0.0459924000, 0.0945623000, 0.2140622000", \ - "0.0136796000, 0.0150279000, 0.0183077000, 0.0263068000, 0.0458198000, 0.0938986000, 0.2138231000", \ - "0.0132930000, 0.0145892000, 0.0178157000, 0.0258251000, 0.0453642000, 0.0936590000, 0.2141766000", \ - "0.0130137000, 0.0142788000, 0.0174169000, 0.0252357000, 0.0448171000, 0.0935288000, 0.2134107000", \ - "0.0129329000, 0.0141725000, 0.0172781000, 0.0251523000, 0.0443081000, 0.0927336000, 0.2128287000", \ - "0.0126145000, 0.0138734000, 0.0167680000, 0.0244398000, 0.0441593000, 0.0924525000, 0.2131976000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0117065000, 0.0104942000, 0.0074915000, -0.000112700, -0.019187300, -0.067361800, -0.188343800", \ - "0.0115075000, 0.0102980000, 0.0073001000, -0.000284400, -0.019368500, -0.067487700, -0.188495700", \ - "0.0111889000, 0.0100031000, 0.0070008000, -0.000534700, -0.019626300, -0.067680700, -0.188697600", \ - "0.0107615000, 0.0095804000, 0.0066251000, -0.000868400, -0.019884100, -0.067925500, -0.188843500", \ - "0.0104049000, 0.0092625000, 0.0063515000, -0.001160000, -0.020066800, -0.068010900, -0.188869800", \ - "0.0102963000, 0.0090987000, 0.0060617000, -0.001494300, -0.020479400, -0.068342700, -0.189188100", \ - "0.0114785000, 0.0102354000, 0.0071123000, -0.000647600, -0.020018700, -0.068389400, -0.189198500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0217512000, 0.0229644000, 0.0260332000, 0.0337492000, 0.0529057000, 0.1006432000, 0.2202819000", \ - "0.0214616000, 0.0227166000, 0.0258293000, 0.0336135000, 0.0528225000, 0.1006189000, 0.2204439000", \ - "0.0209654000, 0.0222205000, 0.0254222000, 0.0333052000, 0.0527034000, 0.1006324000, 0.2204450000", \ - "0.0203944000, 0.0216369000, 0.0247915000, 0.0327344000, 0.0521924000, 0.1003595000, 0.2203554000", \ - "0.0199493000, 0.0211736000, 0.0243259000, 0.0321072000, 0.0515360000, 0.0998325000, 0.2198153000", \ - "0.0195892000, 0.0208163000, 0.0239657000, 0.0318142000, 0.0510215000, 0.0991858000, 0.2193010000", \ - "0.0189238000, 0.0200101000, 0.0230659000, 0.0306770000, 0.0505781000, 0.0986489000, 0.2189089000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0116754000, 0.0104607000, 0.0074596000, -0.000135900, -0.019241500, -0.067358600, -0.188350800", \ - "0.0114698000, 0.0102722000, 0.0072590000, -0.000337100, -0.019415000, -0.067524200, -0.188548500", \ - "0.0111432000, 0.0099455000, 0.0069516000, -0.000596800, -0.019683600, -0.067731100, -0.188751600", \ - "0.0107050000, 0.0095281000, 0.0065484000, -0.000939300, -0.019932900, -0.067929700, -0.188898300", \ - "0.0104117000, 0.0092392000, 0.0063036000, -0.001154800, -0.020131300, -0.067992400, -0.188907300", \ - "0.0103436000, 0.0090924000, 0.0059811000, -0.001647600, -0.020437000, -0.068373900, -0.189233500", \ - "0.0111375000, 0.0099121000, 0.0068537000, -0.000877200, -0.020190200, -0.068525500, -0.189215300"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0274648000, 0.0287208000, 0.0317681000, 0.0394653000, 0.0586852000, 0.1065272000, 0.2264162000", \ - "0.0272462000, 0.0285156000, 0.0315991000, 0.0393313000, 0.0585589000, 0.1064487000, 0.2262525000", \ - "0.0269135000, 0.0281926000, 0.0312851000, 0.0390718000, 0.0583559000, 0.1063026000, 0.2262308000", \ - "0.0264733000, 0.0276815000, 0.0308536000, 0.0387185000, 0.0581013000, 0.1061613000, 0.2260029000", \ - "0.0261354000, 0.0274026000, 0.0304890000, 0.0382919000, 0.0576788000, 0.1057997000, 0.2259756000", \ - "0.0260068000, 0.0272678000, 0.0303830000, 0.0382667000, 0.0575196000, 0.1056287000, 0.2257045000", \ - "0.0257589000, 0.0269281000, 0.0299735000, 0.0376967000, 0.0575028000, 0.1056200000, 0.2258243000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0117358000, 0.0105137000, 0.0074996000, -0.000108100, -0.019196400, -0.067329200, -0.188304400", \ - "0.0114874000, 0.0102850000, 0.0072772000, -0.000316700, -0.019397200, -0.067504400, -0.188508000", \ - "0.0111303000, 0.0099469000, 0.0069464000, -0.000588500, -0.019680600, -0.067723500, -0.188729200", \ - "0.0106701000, 0.0094878000, 0.0065230000, -0.000954000, -0.019939600, -0.067943500, -0.188869500", \ - "0.0103575000, 0.0091957000, 0.0062123000, -0.001250700, -0.020164600, -0.068137300, -0.188874600", \ - "0.0103225000, 0.0090947000, 0.0061543000, -0.001664800, -0.020567700, -0.068419200, -0.189215100", \ - "0.0112339000, 0.0099403000, 0.0069809000, -0.000858000, -0.020175300, -0.068401100, -0.189304100"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0329412000, 0.0341082000, 0.0372242000, 0.0449703000, 0.0643244000, 0.1123249000, 0.2322275000", \ - "0.0326450000, 0.0338727000, 0.0370473000, 0.0447582000, 0.0640435000, 0.1121311000, 0.2323111000", \ - "0.0323683000, 0.0336322000, 0.0366890000, 0.0444775000, 0.0638679000, 0.1119376000, 0.2320382000", \ - "0.0320786000, 0.0333056000, 0.0364093000, 0.0442269000, 0.0635991000, 0.1118043000, 0.2318183000", \ - "0.0317626000, 0.0329812000, 0.0361263000, 0.0439362000, 0.0633551000, 0.1115394000, 0.2315546000", \ - "0.0317174000, 0.0329428000, 0.0360952000, 0.0439454000, 0.0633142000, 0.1115739000, 0.2317475000", \ - "0.0315557000, 0.0327098000, 0.0357199000, 0.0437432000, 0.0633671000, 0.1117197000, 0.2316400000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("-0.000524000, -0.001578600, -0.004403900, -0.011864900, -0.031009100, -0.079301300, -0.200581800", \ - "-0.000888400, -0.001915700, -0.004651400, -0.011958100, -0.030960600, -0.079184200, -0.200413600", \ - "-0.001275400, -0.002339900, -0.005060600, -0.012223100, -0.031044200, -0.079122900, -0.200271900", \ - "-0.001600500, -0.002763300, -0.005519400, -0.012683600, -0.031274500, -0.079238100, -0.200257400", \ - "-0.001339800, -0.002506400, -0.005419100, -0.012830100, -0.031827700, -0.079408900, -0.200328900", \ - "-0.000540700, -0.001751100, -0.004831400, -0.012501200, -0.031471800, -0.079932800, -0.200649200", \ - "0.0025634000, 0.0011673000, -0.002276500, -0.010487900, -0.030227600, -0.078094900, -0.199946900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0302170000, 0.0314953000, 0.0347917000, 0.0427029000, 0.0622507000, 0.1104035000, 0.2302769000", \ - "0.0299508000, 0.0312341000, 0.0344391000, 0.0424858000, 0.0620342000, 0.1103262000, 0.2304133000", \ - "0.0296678000, 0.0309069000, 0.0340408000, 0.0419585000, 0.0616452000, 0.1100918000, 0.2303484000", \ - "0.0294003000, 0.0306791000, 0.0338046000, 0.0415806000, 0.0611503000, 0.1096513000, 0.2299769000", \ - "0.0290479000, 0.0303307000, 0.0333790000, 0.0412662000, 0.0607235000, 0.1089912000, 0.2295195000", \ - "0.0295970000, 0.0308040000, 0.0338524000, 0.0415067000, 0.0607164000, 0.1088472000, 0.2287757000", \ - "0.0324542000, 0.0335503000, 0.0363407000, 0.0434788000, 0.0622640000, 0.1097547000, 0.2298483000"); - } - } - max_capacitance : 0.1245220000; - max_transition : 1.5020360000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0510090000, 0.0559514000, 0.0677888000, 0.0953389000, 0.1612171000, 0.3205100000, 0.7147376000", \ - "0.0543536000, 0.0593816000, 0.0711747000, 0.0988285000, 0.1646091000, 0.3235385000, 0.7183714000", \ - "0.0623021000, 0.0674055000, 0.0791813000, 0.1070803000, 0.1729747000, 0.3322423000, 0.7281568000", \ - "0.0844638000, 0.0894314000, 0.1008053000, 0.1280874000, 0.1942280000, 0.3538006000, 0.7486845000", \ - "0.1168988000, 0.1239398000, 0.1398945000, 0.1746166000, 0.2436449000, 0.4031397000, 0.7981106000", \ - "0.1488350000, 0.1585405000, 0.1825539000, 0.2340694000, 0.3311051000, 0.5179263000, 0.9111689000", \ - "0.1568194000, 0.1724663000, 0.2083901000, 0.2850006000, 0.4357243000, 0.7091996000, 1.1826671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0797582000, 0.0866623000, 0.1030200000, 0.1423690000, 0.2385528000, 0.4782681000, 1.0725167000", \ - "0.0845235000, 0.0913743000, 0.1082514000, 0.1480068000, 0.2442489000, 0.4854970000, 1.0844625000", \ - "0.0974388000, 0.1042538000, 0.1208920000, 0.1611363000, 0.2581098000, 0.4973882000, 1.0932616000", \ - "0.1277928000, 0.1344985000, 0.1504953000, 0.1908123000, 0.2891207000, 0.5285034000, 1.1301902000", \ - "0.1858961000, 0.1941232000, 0.2133733000, 0.2554041000, 0.3531442000, 0.5965443000, 1.1916839000", \ - "0.2777873000, 0.2905176000, 0.3192754000, 0.3778590000, 0.4950047000, 0.7396977000, 1.3405217000", \ - "0.4182251000, 0.4412544000, 0.4873251000, 0.5824836000, 0.7546291000, 1.0656522000, 1.6777205000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0611677000, 0.0661176000, 0.0790542000, 0.1126064000, 0.1981041000, 0.4124916000, 0.9524052000", \ - "0.0605808000, 0.0658508000, 0.0791381000, 0.1125437000, 0.1979902000, 0.4124365000, 0.9528696000", \ - "0.0575202000, 0.0629894000, 0.0771785000, 0.1122273000, 0.1979934000, 0.4124679000, 0.9538098000", \ - "0.0620882000, 0.0669109000, 0.0798578000, 0.1119986000, 0.1972129000, 0.4127551000, 0.9525581000", \ - "0.0795932000, 0.0862579000, 0.1019802000, 0.1355849000, 0.2083735000, 0.4126789000, 0.9528861000", \ - "0.1218855000, 0.1309804000, 0.1506873000, 0.1918655000, 0.2784704000, 0.4563509000, 0.9542979000", \ - "0.1964863000, 0.2102222000, 0.2404794000, 0.3010360000, 0.4143862000, 0.6274430000, 1.0619126000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0451656000, 0.0534722000, 0.0740416000, 0.1266501000, 0.2580709000, 0.5849100000, 1.4027745000", \ - "0.0452782000, 0.0535448000, 0.0743311000, 0.1266125000, 0.2568898000, 0.5867311000, 1.4048686000", \ - "0.0453575000, 0.0536135000, 0.0743944000, 0.1265092000, 0.2567599000, 0.5836873000, 1.4005450000", \ - "0.0463023000, 0.0542961000, 0.0747783000, 0.1268491000, 0.2570787000, 0.5836197000, 1.4060856000", \ - "0.0610601000, 0.0686208000, 0.0865116000, 0.1327039000, 0.2580250000, 0.5872115000, 1.4027202000", \ - "0.0969699000, 0.1052115000, 0.1266448000, 0.1763450000, 0.2868811000, 0.5896345000, 1.4039250000", \ - "0.1756367000, 0.1861345000, 0.2146853000, 0.2753983000, 0.4002732000, 0.6750022000, 1.4171896000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0673936000, 0.0723863000, 0.0842129000, 0.1119190000, 0.1771440000, 0.3366683000, 0.7312324000", \ - "0.0711733000, 0.0761756000, 0.0879195000, 0.1154953000, 0.1809934000, 0.3406627000, 0.7347397000", \ - "0.0796289000, 0.0847442000, 0.0963545000, 0.1242552000, 0.1899433000, 0.3493208000, 0.7437496000", \ - "0.0991623000, 0.1044007000, 0.1163101000, 0.1442649000, 0.2102525000, 0.3699948000, 0.7643735000", \ - "0.1327940000, 0.1393929000, 0.1548564000, 0.1869845000, 0.2568844000, 0.4179850000, 0.8129630000", \ - "0.1719519000, 0.1819493000, 0.2038740000, 0.2501435000, 0.3441568000, 0.5250406000, 0.9241649000", \ - "0.1900090000, 0.2043827000, 0.2380731000, 0.3109916000, 0.4540553000, 0.7107123000, 1.1740554000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1103541000, 0.1169602000, 0.1335290000, 0.1738111000, 0.2735344000, 0.5217057000, 1.1441260000", \ - "0.1152405000, 0.1219990000, 0.1385205000, 0.1796780000, 0.2796866000, 0.5279445000, 1.1490314000", \ - "0.1275356000, 0.1343422000, 0.1509605000, 0.1925665000, 0.2932176000, 0.5421831000, 1.1632844000", \ - "0.1570900000, 0.1638562000, 0.1808529000, 0.2223401000, 0.3237979000, 0.5737169000, 1.1960404000", \ - "0.2203847000, 0.2282428000, 0.2460096000, 0.2870820000, 0.3879357000, 0.6384113000, 1.2610175000", \ - "0.3296836000, 0.3398460000, 0.3643735000, 0.4176828000, 0.5315969000, 0.7835457000, 1.4079897000", \ - "0.5084033000, 0.5245132000, 0.5626476000, 0.6437168000, 0.8033688000, 1.1096158000, 1.7424515000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0595821000, 0.0648856000, 0.0782905000, 0.1124507000, 0.1978350000, 0.4128675000, 0.9527925000", \ - "0.0595138000, 0.0648638000, 0.0782243000, 0.1123675000, 0.1978763000, 0.4127455000, 0.9523099000", \ - "0.0591469000, 0.0644771000, 0.0781873000, 0.1122860000, 0.1978677000, 0.4129967000, 0.9525893000", \ - "0.0619941000, 0.0669412000, 0.0797754000, 0.1126425000, 0.1976416000, 0.4128717000, 0.9517273000", \ - "0.0789768000, 0.0842847000, 0.0980149000, 0.1286815000, 0.2049706000, 0.4128820000, 0.9525778000", \ - "0.1199756000, 0.1269610000, 0.1431295000, 0.1786350000, 0.2571634000, 0.4407212000, 0.9554098000", \ - "0.1955706000, 0.2050171000, 0.2290556000, 0.2797458000, 0.3793775000, 0.5793054000, 1.0301699000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0673268000, 0.0760148000, 0.0979558000, 0.1523896000, 0.2885161000, 0.6280658000, 1.4814858000", \ - "0.0673211000, 0.0760628000, 0.0979047000, 0.1524456000, 0.2885251000, 0.6287493000, 1.4779735000", \ - "0.0673878000, 0.0759998000, 0.0978399000, 0.1525385000, 0.2885750000, 0.6283532000, 1.4813027000", \ - "0.0674362000, 0.0762476000, 0.0980005000, 0.1523848000, 0.2896025000, 0.6286783000, 1.4798388000", \ - "0.0771613000, 0.0847460000, 0.1045264000, 0.1559440000, 0.2886864000, 0.6290815000, 1.4801470000", \ - "0.1121792000, 0.1211374000, 0.1424799000, 0.1937777000, 0.3113301000, 0.6322242000, 1.4814240000", \ - "0.1914539000, 0.2033494000, 0.2299102000, 0.2896647000, 0.4191508000, 0.7061520000, 1.4895083000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0756016000, 0.0806051000, 0.0922869000, 0.1198879000, 0.1855815000, 0.3448646000, 0.7392262000", \ - "0.0795586000, 0.0843599000, 0.0961014000, 0.1238350000, 0.1891692000, 0.3484486000, 0.7430187000", \ - "0.0867983000, 0.0918276000, 0.1034993000, 0.1314144000, 0.1970198000, 0.3562852000, 0.7509695000", \ - "0.1022772000, 0.1073943000, 0.1192978000, 0.1469742000, 0.2130346000, 0.3725505000, 0.7670543000", \ - "0.1283548000, 0.1339843000, 0.1483715000, 0.1789199000, 0.2479762000, 0.4081881000, 0.8031911000", \ - "0.1623890000, 0.1703563000, 0.1889022000, 0.2294518000, 0.3142394000, 0.4882555000, 0.8862574000", \ - "0.1755069000, 0.1875876000, 0.2167197000, 0.2783137000, 0.4010249000, 0.6265214000, 1.0744704000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1234288000, 0.1299696000, 0.1459661000, 0.1859654000, 0.2838546000, 0.5255153000, 1.1276005000", \ - "0.1282278000, 0.1350654000, 0.1519494000, 0.1913683000, 0.2894231000, 0.5310253000, 1.1338326000", \ - "0.1417758000, 0.1484719000, 0.1647044000, 0.2052861000, 0.3034537000, 0.5455575000, 1.1486376000", \ - "0.1721300000, 0.1786890000, 0.1956459000, 0.2359388000, 0.3345107000, 0.5767912000, 1.1791782000", \ - "0.2370469000, 0.2440218000, 0.2605156000, 0.3007692000, 0.3990738000, 0.6417825000, 1.2449939000", \ - "0.3540368000, 0.3632129000, 0.3838008000, 0.4347848000, 0.5431129000, 0.7863033000, 1.3906898000", \ - "0.5503031000, 0.5641661000, 0.5958002000, 0.6678829000, 0.8181624000, 1.1099927000, 1.7228460000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0594972000, 0.0648372000, 0.0782228000, 0.1123342000, 0.1976963000, 0.4128366000, 0.9522650000", \ - "0.0594477000, 0.0649344000, 0.0785231000, 0.1124319000, 0.1976793000, 0.4128275000, 0.9524935000", \ - "0.0591781000, 0.0647627000, 0.0781144000, 0.1122365000, 0.1977739000, 0.4128630000, 0.9526712000", \ - "0.0615286000, 0.0666937000, 0.0798457000, 0.1127928000, 0.1976684000, 0.4129674000, 0.9514254000", \ - "0.0734987000, 0.0786605000, 0.0917294000, 0.1238002000, 0.2033882000, 0.4132989000, 0.9531648000", \ - "0.1072569000, 0.1132945000, 0.1271223000, 0.1600067000, 0.2398491000, 0.4334390000, 0.9552695000", \ - "0.1790817000, 0.1869918000, 0.2065415000, 0.2477937000, 0.3362419000, 0.5304796000, 1.0066136000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0822556000, 0.0908533000, 0.1121232000, 0.1651265000, 0.2978685000, 0.6277144000, 1.4557728000", \ - "0.0822960000, 0.0908435000, 0.1121556000, 0.1651402000, 0.2972596000, 0.6267157000, 1.4544616000", \ - "0.0822629000, 0.0908627000, 0.1121058000, 0.1650773000, 0.2971050000, 0.6277652000, 1.4571053000", \ - "0.0823638000, 0.0907936000, 0.1121537000, 0.1652070000, 0.2977749000, 0.6273250000, 1.4550638000", \ - "0.0888671000, 0.0967369000, 0.1168649000, 0.1670805000, 0.2973614000, 0.6270509000, 1.4534428000", \ - "0.1227612000, 0.1311316000, 0.1523080000, 0.2013203000, 0.3172649000, 0.6303434000, 1.4553446000", \ - "0.2012225000, 0.2121236000, 0.2379075000, 0.2953214000, 0.4210312000, 0.7019816000, 1.4648518000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0811474000, 0.0859561000, 0.0977561000, 0.1254876000, 0.1909853000, 0.3504858000, 0.7456506000", \ - "0.0852602000, 0.0900640000, 0.1018076000, 0.1295461000, 0.1949056000, 0.3541607000, 0.7501630000", \ - "0.0927122000, 0.0978237000, 0.1094076000, 0.1373408000, 0.2029567000, 0.3622310000, 0.7582194000", \ - "0.1070679000, 0.1120794000, 0.1239569000, 0.1518798000, 0.2178712000, 0.3774946000, 0.7726752000", \ - "0.1297061000, 0.1356715000, 0.1484372000, 0.1784430000, 0.2466178000, 0.4068091000, 0.8017286000", \ - "0.1597505000, 0.1666463000, 0.1839955000, 0.2188836000, 0.2971744000, 0.4686559000, 0.8663743000", \ - "0.1731349000, 0.1828820000, 0.2074735000, 0.2604064000, 0.3673839000, 0.5771969000, 1.0087706000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1399643000, 0.1469404000, 0.1635840000, 0.2054337000, 0.3049321000, 0.5502632000, 1.1572361000", \ - "0.1450474000, 0.1518234000, 0.1691424000, 0.2101743000, 0.3104789000, 0.5549964000, 1.1617904000", \ - "0.1580402000, 0.1651069000, 0.1819024000, 0.2237685000, 0.3233483000, 0.5684657000, 1.1752304000", \ - "0.1868722000, 0.1945333000, 0.2114283000, 0.2532594000, 0.3535959000, 0.5983973000, 1.2055220000", \ - "0.2493161000, 0.2563235000, 0.2733919000, 0.3145305000, 0.4149033000, 0.6600918000, 1.2674229000", \ - "0.3618923000, 0.3706718000, 0.3914178000, 0.4408216000, 0.5501006000, 0.7953450000, 1.4034413000", \ - "0.5510297000, 0.5634020000, 0.5942582000, 0.6618421000, 0.8059967000, 1.1000473000, 1.7168668000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0596738000, 0.0648311000, 0.0782226000, 0.1122185000, 0.1977428000, 0.4126849000, 0.9532702000", \ - "0.0594500000, 0.0649364000, 0.0785258000, 0.1124178000, 0.1975623000, 0.4127859000, 0.9536310000", \ - "0.0593684000, 0.0646600000, 0.0782788000, 0.1122926000, 0.1977763000, 0.4128384000, 0.9532293000", \ - "0.0603644000, 0.0657822000, 0.0790202000, 0.1125182000, 0.1976328000, 0.4124634000, 0.9528462000", \ - "0.0688166000, 0.0741369000, 0.0875892000, 0.1200780000, 0.2016399000, 0.4128958000, 0.9528699000", \ - "0.0939391000, 0.0996300000, 0.1131820000, 0.1463886000, 0.2277549000, 0.4288024000, 0.9553349000", \ - "0.1589893000, 0.1657936000, 0.1820698000, 0.2193269000, 0.3022930000, 0.5034304000, 0.9977028000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1012194000, 0.1096325000, 0.1314137000, 0.1850637000, 0.3182433000, 0.6517578000, 1.4844083000", \ - "0.1007984000, 0.1095440000, 0.1314031000, 0.1848481000, 0.3176297000, 0.6502049000, 1.4835939000", \ - "0.1013358000, 0.1097997000, 0.1315007000, 0.1851079000, 0.3182144000, 0.6505572000, 1.4826889000", \ - "0.1009246000, 0.1098182000, 0.1312906000, 0.1848338000, 0.3176284000, 0.6506602000, 1.4832527000", \ - "0.1061903000, 0.1141519000, 0.1346198000, 0.1864608000, 0.3178282000, 0.6497303000, 1.4835418000", \ - "0.1388466000, 0.1473579000, 0.1682871000, 0.2188068000, 0.3374197000, 0.6547015000, 1.4834424000", \ - "0.2165877000, 0.2269267000, 0.2520226000, 0.3091042000, 0.4359422000, 0.7254715000, 1.5001892000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0142755000, 0.0157430000, 0.0192786000, 0.0274721000, 0.0476565000, 0.0977992000, 0.2233662000", \ - "0.0189658000, 0.0204837000, 0.0240097000, 0.0323815000, 0.0525194000, 0.1027766000, 0.2283717000", \ - "0.0256701000, 0.0281658000, 0.0336574000, 0.0437787000, 0.0640741000, 0.1142016000, 0.2397942000", \ - "0.0329240000, 0.0370825000, 0.0454755000, 0.0615851000, 0.0893122000, 0.1409116000, 0.2657459000", \ - "0.0370583000, 0.0434443000, 0.0569531000, 0.0821557000, 0.1274778000, 0.1990432000, 0.3271603000", \ - "0.0287005000, 0.0386132000, 0.0600910000, 0.1008121000, 0.1709491000, 0.2855443000, 0.4642955000", \ - "-0.018456600, -0.001892600, 0.0309080000, 0.0950947000, 0.2074390000, 0.3858251000, 0.6675391000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1044084000, 0.1115795000, 0.1293743000, 0.1715130000, 0.2722268000, 0.5172885000, 1.1256756000", \ - "0.1077521000, 0.1153174000, 0.1332883000, 0.1757347000, 0.2765751000, 0.5218224000, 1.1298676000", \ - "0.1189083000, 0.1256081000, 0.1431804000, 0.1858988000, 0.2865573000, 0.5327826000, 1.1409500000", \ - "0.1461190000, 0.1532188000, 0.1706199000, 0.2116066000, 0.3128676000, 0.5590222000, 1.1678288000", \ - "0.2146342000, 0.2202665000, 0.2386443000, 0.2791635000, 0.3785409000, 0.6244376000, 1.2333795000", \ - "0.3359939000, 0.3461956000, 0.3711039000, 0.4256509000, 0.5355684000, 0.7777782000, 1.3822987000", \ - "0.5278256000, 0.5433042000, 0.5794223000, 0.6607699000, 0.8264842000, 1.1348947000, 1.7390032000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0104839000, 0.0125683000, 0.0177305000, 0.0301488000, 0.0598867000, 0.1294482000, 0.2986630000", \ - "0.0116008000, 0.0133801000, 0.0180181000, 0.0301783000, 0.0599056000, 0.1294685000, 0.2986485000", \ - "0.0202830000, 0.0214158000, 0.0242950000, 0.0334780000, 0.0604680000, 0.1294581000, 0.2986883000", \ - "0.0384113000, 0.0393918000, 0.0425982000, 0.0510406000, 0.0718449000, 0.1314197000, 0.2983749000", \ - "0.0737364000, 0.0748555000, 0.0782976000, 0.0887370000, 0.1109496000, 0.1596695000, 0.3031821000", \ - "0.1320593000, 0.1337124000, 0.1383683000, 0.1520991000, 0.1845584000, 0.2463810000, 0.3674934000", \ - "0.2353232000, 0.2372134000, 0.2439554000, 0.2634874000, 0.3098142000, 0.4040557000, 0.5679797000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1010583000, 0.1097546000, 0.1315286000, 0.1846109000, 0.3178852000, 0.6497986000, 1.4844119000", \ - "0.1011762000, 0.1098307000, 0.1315598000, 0.1848319000, 0.3186966000, 0.6497967000, 1.4853774000", \ - "0.1011525000, 0.1098379000, 0.1314247000, 0.1844921000, 0.3183918000, 0.6506573000, 1.4860847000", \ - "0.0989626000, 0.1076958000, 0.1296752000, 0.1843989000, 0.3179837000, 0.6506009000, 1.4829278000", \ - "0.1151049000, 0.1227066000, 0.1408606000, 0.1899307000, 0.3174659000, 0.6498593000, 1.4816044000", \ - "0.1654776000, 0.1758350000, 0.1996152000, 0.2499295000, 0.3556899000, 0.6553455000, 1.4832343000", \ - "0.2539643000, 0.2694377000, 0.3037927000, 0.3748667000, 0.5114722000, 0.7735684000, 1.5020355000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__a41oi_4") { - leakage_power () { - value : 0.0035623000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0017470000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0029806000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0030025000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0004870000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0048485000; - when : "A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0035618000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015894000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035616000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0016137000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0016153000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0016893000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0016184000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0016927000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0016996000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0034253000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0035615000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0016390000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0017099000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0017191000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0035623000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0030054000; - when : "A1&!A2&A3&A4&!B1"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__a41oi"; - cell_leakage_power : 0.0027973540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0083200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081270000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181588000, 0.0181538000, 0.0181422000, 0.0181360000, 0.0181217000, 0.0180888000, 0.0180128000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013116700, -0.013142000, -0.013200400, -0.013166100, -0.013087100, -0.012905000, -0.012485200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085120000; - } - pin ("A2") { - capacitance : 0.0083460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172103000, 0.0172160000, 0.0172292000, 0.0172914000, 0.0174348000, 0.0177654000, 0.0185273000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015611900, -0.015610800, -0.015608100, -0.015606800, -0.015603900, -0.015597000, -0.015581300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085660000; - } - pin ("A3") { - capacitance : 0.0082840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0154083000, 0.0154089000, 0.0154105000, 0.0154108000, 0.0154115000, 0.0154131000, 0.0154169000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015386000, -0.015374200, -0.015347000, -0.015344300, -0.015338100, -0.015323900, -0.015291000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086400000; - } - pin ("A4") { - capacitance : 0.0085280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155199000, 0.0155295000, 0.0155519000, 0.0155562000, 0.0155661000, 0.0155889000, 0.0156415000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015535100, -0.015536100, -0.015538300, -0.015537900, -0.015536800, -0.015534500, -0.015529000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089860000; - } - pin ("B1") { - capacitance : 0.0084790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091441000, 0.0091140000, 0.0090446000, 0.0091221000, 0.0093007000, 0.0097122000, 0.0106609000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006956200, -0.006955100, -0.006952500, -0.006954500, -0.006958900, -0.006969200, -0.006992800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091750000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!B1) | (!A2&!B1) | (!A3&!B1) | (!A4&!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0210996000, 0.0197451000, 0.0161122000, 0.0062555000, -0.020592600, -0.093409000, -0.290829500", \ - "0.0207013000, 0.0193759000, 0.0156957000, 0.0058453000, -0.020904500, -0.093700600, -0.291148100", \ - "0.0200656000, 0.0187407000, 0.0150535000, 0.0052855000, -0.021348300, -0.094102300, -0.291485300", \ - "0.0190481000, 0.0178196000, 0.0141959000, 0.0044204000, -0.022129600, -0.094633500, -0.291847000", \ - "0.0184450000, 0.0171078000, 0.0135699000, 0.0039578000, -0.022542800, -0.094982500, -0.292459900", \ - "0.0189410000, 0.0175752000, 0.0136563000, 0.0037359000, -0.022894100, -0.095607800, -0.292689600", \ - "0.0220921000, 0.0206461000, 0.0166883000, 0.0065846000, -0.021018500, -0.094304000, -0.292966600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0269287000, 0.0285283000, 0.0325341000, 0.0431330000, 0.0702773000, 0.1438896000, 0.3394828000", \ - "0.0262417000, 0.0278448000, 0.0319115000, 0.0425987000, 0.0702381000, 0.1431038000, 0.3389101000", \ - "0.0254292000, 0.0269665000, 0.0310770000, 0.0418832000, 0.0697554000, 0.1430219000, 0.3391501000", \ - "0.0246653000, 0.0261977000, 0.0301397000, 0.0407674000, 0.0686356000, 0.1433042000, 0.3387925000", \ - "0.0241405000, 0.0254732000, 0.0293263000, 0.0395481000, 0.0674588000, 0.1411128000, 0.3390321000", \ - "0.0240046000, 0.0253986000, 0.0291954000, 0.0394726000, 0.0666225000, 0.1401490000, 0.3383349000", \ - "0.0234588000, 0.0248138000, 0.0285130000, 0.0383690000, 0.0664813000, 0.1406958000, 0.3369995000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0236449000, 0.0222833000, 0.0186220000, 0.0086891000, -0.018145400, -0.090968300, -0.288470100", \ - "0.0232881000, 0.0218938000, 0.0182214000, 0.0082949000, -0.018551100, -0.091278600, -0.288728200", \ - "0.0226125000, 0.0212635000, 0.0176403000, 0.0078113000, -0.018997100, -0.091727600, -0.289147100", \ - "0.0218389000, 0.0204926000, 0.0168688000, 0.0070706000, -0.019598800, -0.092230300, -0.289499800", \ - "0.0211118000, 0.0197931000, 0.0163200000, 0.0065680000, -0.019961500, -0.092441300, -0.289505300", \ - "0.0210083000, 0.0196403000, 0.0160063000, 0.0060868000, -0.020806000, -0.093147500, -0.290115500", \ - "0.0231352000, 0.0217560000, 0.0180415000, 0.0077534000, -0.019542700, -0.093137700, -0.290251000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0409951000, 0.0424013000, 0.0461126000, 0.0562054000, 0.0832303000, 0.1559318000, 0.3511684000", \ - "0.0404576000, 0.0418184000, 0.0456881000, 0.0559045000, 0.0831857000, 0.1558992000, 0.3511670000", \ - "0.0394725000, 0.0409864000, 0.0447955000, 0.0551511000, 0.0826898000, 0.1555924000, 0.3513504000", \ - "0.0382833000, 0.0397609000, 0.0436157000, 0.0540247000, 0.0817327000, 0.1551692000, 0.3508013000", \ - "0.0373301000, 0.0387243000, 0.0425219000, 0.0527757000, 0.0802755000, 0.1537956000, 0.3503297000", \ - "0.0367771000, 0.0380884000, 0.0419490000, 0.0521681000, 0.0793226000, 0.1525423000, 0.3489013000", \ - "0.0351514000, 0.0364607000, 0.0400957000, 0.0500105000, 0.0783653000, 0.1512880000, 0.3479411000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0235919000, 0.0221920000, 0.0185118000, 0.0085964000, -0.018262400, -0.091018400, -0.288447000", \ - "0.0231376000, 0.0217772000, 0.0181280000, 0.0082282000, -0.018642400, -0.091466700, -0.288803800", \ - "0.0224918000, 0.0211305000, 0.0175160000, 0.0076799000, -0.019163500, -0.091902600, -0.289278600", \ - "0.0216476000, 0.0203217000, 0.0166981000, 0.0069049000, -0.019733600, -0.092318200, -0.289638500", \ - "0.0210241000, 0.0197092000, 0.0161359000, 0.0064054000, -0.020212400, -0.092636400, -0.289752900", \ - "0.0207013000, 0.0193382000, 0.0156451000, 0.0058859000, -0.020840200, -0.093100400, -0.290150000", \ - "0.0224255000, 0.0209554000, 0.0172381000, 0.0070864000, -0.020119100, -0.093566700, -0.290427000"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0529691000, 0.0543472000, 0.0582282000, 0.0681957000, 0.0953214000, 0.1681049000, 0.3641367000", \ - "0.0525497000, 0.0540296000, 0.0578370000, 0.0678713000, 0.0949789000, 0.1678380000, 0.3634923000", \ - "0.0517781000, 0.0532116000, 0.0570898000, 0.0672701000, 0.0946285000, 0.1674925000, 0.3633252000", \ - "0.0508815000, 0.0523792000, 0.0562559000, 0.0665113000, 0.0940441000, 0.1670235000, 0.3629655000", \ - "0.0501598000, 0.0515863000, 0.0553671000, 0.0656118000, 0.0930257000, 0.1664024000, 0.3628354000", \ - "0.0500363000, 0.0514826000, 0.0553783000, 0.0655112000, 0.0927738000, 0.1657205000, 0.3621062000", \ - "0.0491210000, 0.0505517000, 0.0543277000, 0.0650332000, 0.0925824000, 0.1658629000, 0.3619161000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0233025000, 0.0219401000, 0.0182752000, 0.0083830000, -0.018496500, -0.091323600, -0.288696500", \ - "0.0229090000, 0.0215502000, 0.0178260000, 0.0079341000, -0.018935400, -0.091695100, -0.289126700", \ - "0.0222518000, 0.0209159000, 0.0172631000, 0.0073930000, -0.019407600, -0.092145200, -0.289536300", \ - "0.0214678000, 0.0201401000, 0.0165040000, 0.0066815000, -0.019917800, -0.092600200, -0.289906000", \ - "0.0209405000, 0.0196193000, 0.0160138000, 0.0061968000, -0.020374300, -0.092815700, -0.289995300", \ - "0.0209269000, 0.0196783000, 0.0159774000, 0.0056902000, -0.020968100, -0.093338100, -0.290250800", \ - "0.0225386000, 0.0212092000, 0.0173924000, 0.0072984000, -0.020048900, -0.093578800, -0.290603700"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0633504000, 0.0647317000, 0.0686156000, 0.0786465000, 0.1058574000, 0.1789756000, 0.3747835000", \ - "0.0630036000, 0.0643636000, 0.0680213000, 0.0782862000, 0.1055897000, 0.1787537000, 0.3750160000", \ - "0.0624420000, 0.0637591000, 0.0676258000, 0.0776838000, 0.1049724000, 0.1781006000, 0.3744684000", \ - "0.0618389000, 0.0632219000, 0.0669727000, 0.0772304000, 0.1046420000, 0.1777779000, 0.3738908000", \ - "0.0612624000, 0.0626409000, 0.0663749000, 0.0766417000, 0.1041629000, 0.1772347000, 0.3737618000", \ - "0.0613581000, 0.0624542000, 0.0664947000, 0.0766935000, 0.1039171000, 0.1772820000, 0.3738887000", \ - "0.0603609000, 0.0617041000, 0.0656434000, 0.0765368000, 0.1039453000, 0.1774838000, 0.3735353000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("-0.000207900, -0.001374700, -0.004710100, -0.014278800, -0.041078600, -0.114212900, -0.312177000", \ - "-0.000836600, -0.001997800, -0.005175000, -0.014509800, -0.041022600, -0.113980700, -0.311828800", \ - "-0.001575100, -0.002669600, -0.005930100, -0.015096900, -0.041182100, -0.113834800, -0.311550700", \ - "-0.002049900, -0.003410800, -0.006787700, -0.015929000, -0.041811100, -0.113980600, -0.311470500", \ - "-0.001617100, -0.002969600, -0.006447500, -0.015933800, -0.042582500, -0.114575300, -0.311640200", \ - "-3.60000e-05, -0.001483200, -0.005357500, -0.015496400, -0.042378200, -0.115201600, -0.312062700", \ - "0.0053024000, 0.0036914000, -0.000470200, -0.011280700, -0.039653800, -0.112805300, -0.311210700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013504540, 0.0036474540, 0.0098514400, 0.0266078400, 0.0718653400, 0.1941017000"); - values("0.0573521000, 0.0588112000, 0.0626932000, 0.0731982000, 0.1010249000, 0.1745929000, 0.3709590000", \ - "0.0567285000, 0.0581183000, 0.0619852000, 0.0726275000, 0.1003738000, 0.1740850000, 0.3704827000", \ - "0.0563596000, 0.0577053000, 0.0615370000, 0.0717868000, 0.0997729000, 0.1737676000, 0.3701033000", \ - "0.0556436000, 0.0570335000, 0.0608689000, 0.0712311000, 0.0988264000, 0.1728969000, 0.3695204000", \ - "0.0553328000, 0.0567300000, 0.0605486000, 0.0707100000, 0.0976659000, 0.1711605000, 0.3683524000", \ - "0.0572905000, 0.0586395000, 0.0624893000, 0.0725964000, 0.0990462000, 0.1715790000, 0.3672085000", \ - "0.0643458000, 0.0653273000, 0.0680435000, 0.0765530000, 0.1022747000, 0.1740364000, 0.3671860000"); - } - } - max_capacitance : 0.1941020000; - max_transition : 1.4951550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0530923000, 0.0562778000, 0.0645032000, 0.0856371000, 0.1385133000, 0.2736954000, 0.6332653000", \ - "0.0562041000, 0.0595061000, 0.0677353000, 0.0887991000, 0.1419823000, 0.2772830000, 0.6363858000", \ - "0.0640364000, 0.0672600000, 0.0755751000, 0.0970074000, 0.1500519000, 0.2854898000, 0.6446537000", \ - "0.0866097000, 0.0902618000, 0.0975717000, 0.1174750000, 0.1706140000, 0.3064547000, 0.6654097000", \ - "0.1183276000, 0.1227582000, 0.1339203000, 0.1605233000, 0.2191927000, 0.3549805000, 0.7153390000", \ - "0.1490663000, 0.1556216000, 0.1718002000, 0.2115635000, 0.2958952000, 0.4660740000, 0.8279867000", \ - "0.1521763000, 0.1617640000, 0.1858470000, 0.2446227000, 0.3744825000, 0.6270390000, 1.0916016000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0873878000, 0.0922667000, 0.1046624000, 0.1363570000, 0.2172988000, 0.4354779000, 1.0187614000", \ - "0.0916230000, 0.0965637000, 0.1091658000, 0.1413442000, 0.2232999000, 0.4400429000, 1.0216830000", \ - "0.1039195000, 0.1086349000, 0.1212384000, 0.1536418000, 0.2366945000, 0.4543870000, 1.0360054000", \ - "0.1341466000, 0.1387784000, 0.1507497000, 0.1827149000, 0.2661782000, 0.4866261000, 1.0684653000", \ - "0.1922970000, 0.1977637000, 0.2117182000, 0.2458405000, 0.3285338000, 0.5474739000, 1.1353456000", \ - "0.2870074000, 0.2945028000, 0.3148425000, 0.3607123000, 0.4623463000, 0.6875482000, 1.2729705000", \ - "0.4345158000, 0.4470002000, 0.4796276000, 0.5531882000, 0.7031411000, 0.9930939000, 1.5972303000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0662862000, 0.0691635000, 0.0780522000, 0.1019986000, 0.1690955000, 0.3515754000, 0.8478181000", \ - "0.0657016000, 0.0689337000, 0.0777405000, 0.1020538000, 0.1691642000, 0.3518935000, 0.8475759000", \ - "0.0620882000, 0.0653983000, 0.0750994000, 0.1013171000, 0.1689262000, 0.3516678000, 0.8471649000", \ - "0.0657510000, 0.0693549000, 0.0777707000, 0.1013113000, 0.1676023000, 0.3516940000, 0.8470279000", \ - "0.0819693000, 0.0863021000, 0.0975268000, 0.1257407000, 0.1835462000, 0.3528115000, 0.8469866000", \ - "0.1225321000, 0.1282674000, 0.1429248000, 0.1767299000, 0.2529283000, 0.4075427000, 0.8523430000", \ - "0.1952183000, 0.2037691000, 0.2258678000, 0.2758929000, 0.3749026000, 0.5734200000, 0.9807418000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0481460000, 0.0536505000, 0.0686774000, 0.1097140000, 0.2196486000, 0.5183554000, 1.3143420000", \ - "0.0483109000, 0.0537893000, 0.0686916000, 0.1095831000, 0.2191027000, 0.5135174000, 1.3124914000", \ - "0.0485433000, 0.0540628000, 0.0690406000, 0.1096446000, 0.2193509000, 0.5144998000, 1.3112599000", \ - "0.0492946000, 0.0545516000, 0.0695034000, 0.1095291000, 0.2193039000, 0.5179702000, 1.3112497000", \ - "0.0629613000, 0.0683007000, 0.0808426000, 0.1167316000, 0.2203808000, 0.5141697000, 1.3118781000", \ - "0.0946753000, 0.1003876000, 0.1155132000, 0.1551599000, 0.2521263000, 0.5226122000, 1.3150281000", \ - "0.1695366000, 0.1765229000, 0.1957600000, 0.2434647000, 0.3544946000, 0.6115157000, 1.3284313000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0696841000, 0.0728650000, 0.0813675000, 0.1021293000, 0.1549233000, 0.2902436000, 0.6495340000", \ - "0.0733279000, 0.0763782000, 0.0847749000, 0.1057495000, 0.1583277000, 0.2940018000, 0.6530181000", \ - "0.0813352000, 0.0845622000, 0.0927231000, 0.1137435000, 0.1667055000, 0.3023031000, 0.6614432000", \ - "0.0998989000, 0.1032758000, 0.1117130000, 0.1326944000, 0.1855720000, 0.3218028000, 0.6817236000", \ - "0.1320422000, 0.1360918000, 0.1464158000, 0.1717273000, 0.2296243000, 0.3670214000, 0.7276906000", \ - "0.1678065000, 0.1737955000, 0.1897859000, 0.2255365000, 0.3041209000, 0.4663397000, 0.8332832000", \ - "0.1793291000, 0.1889776000, 0.2119944000, 0.2660721000, 0.3869711000, 0.6221116000, 1.0635689000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1205834000, 0.1249720000, 0.1367141000, 0.1685795000, 0.2518458000, 0.4749006000, 1.0755405000", \ - "0.1253600000, 0.1298108000, 0.1418033000, 0.1738656000, 0.2578876000, 0.4812384000, 1.0824014000", \ - "0.1371202000, 0.1417926000, 0.1538424000, 0.1865608000, 0.2713772000, 0.4955159000, 1.0961401000", \ - "0.1665334000, 0.1709576000, 0.1829943000, 0.2159124000, 0.3011156000, 0.5258623000, 1.1284420000", \ - "0.2286458000, 0.2337935000, 0.2466795000, 0.2787726000, 0.3636345000, 0.5893708000, 1.1920104000", \ - "0.3376991000, 0.3444110000, 0.3609259000, 0.4017088000, 0.4987563000, 0.7273407000, 1.3328845000", \ - "0.5187945000, 0.5294494000, 0.5550771000, 0.6162563000, 0.7506151000, 1.0307184000, 1.6503712000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0641800000, 0.0675001000, 0.0765781000, 0.1014406000, 0.1688425000, 0.3515545000, 0.8477761000", \ - "0.0640467000, 0.0675889000, 0.0765118000, 0.1013984000, 0.1685556000, 0.3518947000, 0.8474118000", \ - "0.0638029000, 0.0670203000, 0.0765000000, 0.1010843000, 0.1687300000, 0.3518275000, 0.8472746000", \ - "0.0664756000, 0.0695776000, 0.0782765000, 0.1024659000, 0.1683731000, 0.3515681000, 0.8476928000", \ - "0.0823435000, 0.0858112000, 0.0955271000, 0.1194126000, 0.1786460000, 0.3531744000, 0.8474237000", \ - "0.1223266000, 0.1265249000, 0.1375831000, 0.1654706000, 0.2309255000, 0.3874728000, 0.8518401000", \ - "0.1972112000, 0.2039931000, 0.2205208000, 0.2590468000, 0.3431285000, 0.5236706000, 0.9402258000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0730009000, 0.0788288000, 0.0945165000, 0.1366828000, 0.2503192000, 0.5552522000, 1.3821142000", \ - "0.0730074000, 0.0787442000, 0.0945198000, 0.1369336000, 0.2502387000, 0.5551096000, 1.3782993000", \ - "0.0730788000, 0.0789061000, 0.0945004000, 0.1367221000, 0.2503382000, 0.5563244000, 1.3767786000", \ - "0.0734012000, 0.0789312000, 0.0946496000, 0.1369447000, 0.2502049000, 0.5553343000, 1.3798075000", \ - "0.0810012000, 0.0861873000, 0.1006157000, 0.1405698000, 0.2505348000, 0.5574022000, 1.3780396000", \ - "0.1124018000, 0.1180305000, 0.1337907000, 0.1744061000, 0.2747907000, 0.5614404000, 1.3821102000", \ - "0.1870672000, 0.1945360000, 0.2132603000, 0.2593319000, 0.3704617000, 0.6367900000, 1.3927993000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0787714000, 0.0818068000, 0.0901644000, 0.1110343000, 0.1638003000, 0.2992975000, 0.6579408000", \ - "0.0822579000, 0.0854382000, 0.0939272000, 0.1147387000, 0.1671613000, 0.3031381000, 0.6617102000", \ - "0.0895279000, 0.0927671000, 0.1009153000, 0.1218841000, 0.1748419000, 0.3101757000, 0.6704858000", \ - "0.1040788000, 0.1073946000, 0.1157481000, 0.1367576000, 0.1896705000, 0.3254813000, 0.6846221000", \ - "0.1285641000, 0.1321132000, 0.1413215000, 0.1653279000, 0.2212440000, 0.3585181000, 0.7181364000", \ - "0.1592810000, 0.1640723000, 0.1764801000, 0.2088043000, 0.2761401000, 0.4296001000, 0.7946379000", \ - "0.1644445000, 0.1723393000, 0.1906908000, 0.2377115000, 0.3405479000, 0.5448099000, 0.9626416000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1510060000, 0.1560213000, 0.1682257000, 0.2027719000, 0.2920396000, 0.5291405000, 1.1654336000", \ - "0.1556466000, 0.1599188000, 0.1734880000, 0.2079150000, 0.2974466000, 0.5345020000, 1.1703919000", \ - "0.1682460000, 0.1727384000, 0.1856253000, 0.2203626000, 0.3105921000, 0.5483164000, 1.1849601000", \ - "0.1977486000, 0.2019321000, 0.2158256000, 0.2498725000, 0.3403944000, 0.5792337000, 1.2155974000", \ - "0.2607644000, 0.2656265000, 0.2786369000, 0.3131403000, 0.4032839000, 0.6420205000, 1.2794273000", \ - "0.3780976000, 0.3839576000, 0.3987109000, 0.4401732000, 0.5392699000, 0.7785460000, 1.4168617000", \ - "0.5803269000, 0.5889874000, 0.6127007000, 0.6682157000, 0.7980768000, 1.0826008000, 1.7308774000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0640408000, 0.0675909000, 0.0765258000, 0.1013591000, 0.1687534000, 0.3518702000, 0.8470908000", \ - "0.0640397000, 0.0673376000, 0.0764267000, 0.1013293000, 0.1686874000, 0.3517538000, 0.8462242000", \ - "0.0637079000, 0.0670664000, 0.0764883000, 0.1013260000, 0.1686622000, 0.3514901000, 0.8481187000", \ - "0.0659458000, 0.0691696000, 0.0778883000, 0.1019963000, 0.1684701000, 0.3517454000, 0.8470740000", \ - "0.0772052000, 0.0804838000, 0.0889059000, 0.1132738000, 0.1755237000, 0.3532671000, 0.8471572000", \ - "0.1102247000, 0.1137814000, 0.1230950000, 0.1482450000, 0.2106105000, 0.3777839000, 0.8522694000", \ - "0.1819686000, 0.1873431000, 0.2005881000, 0.2317467000, 0.3056446000, 0.4728227000, 0.9182493000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1004379000, 0.1062720000, 0.1232936000, 0.1678419000, 0.2880585000, 0.6112821000, 1.4811716000", \ - "0.1001576000, 0.1066144000, 0.1231854000, 0.1678448000, 0.2882627000, 0.6112923000, 1.4805845000", \ - "0.1004376000, 0.1063509000, 0.1232808000, 0.1677787000, 0.2880484000, 0.6121826000, 1.4850339000", \ - "0.1000851000, 0.1065285000, 0.1231928000, 0.1679017000, 0.2883090000, 0.6109180000, 1.4811298000", \ - "0.1049050000, 0.1106119000, 0.1265543000, 0.1697291000, 0.2883137000, 0.6118522000, 1.4808013000", \ - "0.1345934000, 0.1409532000, 0.1576764000, 0.1997117000, 0.3068384000, 0.6145005000, 1.4858879000", \ - "0.2089709000, 0.2170463000, 0.2349670000, 0.2819351000, 0.3976673000, 0.6818899000, 1.4951547000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0831762000, 0.0863924000, 0.0948232000, 0.1156474000, 0.1680505000, 0.3040017000, 0.6624434000", \ - "0.0869881000, 0.0900258000, 0.0983194000, 0.1191928000, 0.1719337000, 0.3072613000, 0.6675812000", \ - "0.0939015000, 0.0972166000, 0.1052201000, 0.1262015000, 0.1791795000, 0.3145037000, 0.6745699000", \ - "0.1065730000, 0.1098173000, 0.1181210000, 0.1392555000, 0.1920321000, 0.3281684000, 0.6872923000", \ - "0.1261504000, 0.1296034000, 0.1383035000, 0.1610499000, 0.2162801000, 0.3528886000, 0.7124101000", \ - "0.1490386000, 0.1541388000, 0.1646939000, 0.1909840000, 0.2542284000, 0.4023739000, 0.7659684000", \ - "0.1505794000, 0.1572514000, 0.1729369000, 0.2110742000, 0.2984293000, 0.4788007000, 0.8789223000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1625279000, 0.1678106000, 0.1810343000, 0.2150458000, 0.3033923000, 0.5344193000, 1.1503136000", \ - "0.1679079000, 0.1727670000, 0.1857063000, 0.2197664000, 0.3074151000, 0.5386393000, 1.1547755000", \ - "0.1807952000, 0.1857789000, 0.1976528000, 0.2325259000, 0.3213572000, 0.5525277000, 1.1682644000", \ - "0.2100490000, 0.2149185000, 0.2276068000, 0.2623112000, 0.3506996000, 0.5825482000, 1.1987474000", \ - "0.2704230000, 0.2751319000, 0.2882329000, 0.3224802000, 0.4095689000, 0.6421215000, 1.2585915000", \ - "0.3828522000, 0.3893551000, 0.4049467000, 0.4437629000, 0.5393404000, 0.7712702000, 1.3884408000", \ - "0.5820697000, 0.5901075000, 0.6101613000, 0.6601852000, 0.7833955000, 1.0556319000, 1.6831312000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0640324000, 0.0673475000, 0.0764207000, 0.1013609000, 0.1687221000, 0.3517585000, 0.8468868000", \ - "0.0640470000, 0.0673410000, 0.0764788000, 0.1012975000, 0.1686031000, 0.3514728000, 0.8475461000", \ - "0.0638742000, 0.0670979000, 0.0765811000, 0.1011410000, 0.1686735000, 0.3514169000, 0.8474879000", \ - "0.0648765000, 0.0683665000, 0.0771196000, 0.1017265000, 0.1686653000, 0.3516342000, 0.8474732000", \ - "0.0726359000, 0.0759796000, 0.0849165000, 0.1090596000, 0.1735248000, 0.3528744000, 0.8472210000", \ - "0.0954960000, 0.0989114000, 0.1078789000, 0.1324030000, 0.1971806000, 0.3712689000, 0.8517831000", \ - "0.1584155000, 0.1625824000, 0.1725157000, 0.2000714000, 0.2660934000, 0.4363842000, 0.8978009000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1187874000, 0.1247748000, 0.1417435000, 0.1843587000, 0.3007526000, 0.6136441000, 1.4570587000", \ - "0.1192259000, 0.1252030000, 0.1411246000, 0.1848555000, 0.3010424000, 0.6137093000, 1.4549328000", \ - "0.1190289000, 0.1246713000, 0.1413272000, 0.1847522000, 0.3007431000, 0.6132809000, 1.4583859000", \ - "0.1189809000, 0.1249827000, 0.1411905000, 0.1849026000, 0.3016245000, 0.6139514000, 1.4588439000", \ - "0.1218830000, 0.1276961000, 0.1435797000, 0.1858676000, 0.3009991000, 0.6136613000, 1.4579793000", \ - "0.1508147000, 0.1555374000, 0.1721435000, 0.2134527000, 0.3182430000, 0.6176828000, 1.4556751000", \ - "0.2195134000, 0.2260808000, 0.2439667000, 0.2894032000, 0.4042216000, 0.6839001000, 1.4753619000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0139201000, 0.0147929000, 0.0170526000, 0.0228135000, 0.0375962000, 0.0770815000, 0.1832229000", \ - "0.0184397000, 0.0194160000, 0.0216777000, 0.0274816000, 0.0424872000, 0.0819488000, 0.1881928000", \ - "0.0244993000, 0.0261202000, 0.0299340000, 0.0379616000, 0.0535289000, 0.0932631000, 0.1995685000", \ - "0.0302844000, 0.0328834000, 0.0390988000, 0.0517762000, 0.0760483000, 0.1188856000, 0.2250975000", \ - "0.0320327000, 0.0354329000, 0.0450131000, 0.0657665000, 0.1043671000, 0.1709488000, 0.2858461000", \ - "0.0161002000, 0.0224952000, 0.0371998000, 0.0700939000, 0.1317640000, 0.2369666000, 0.4099182000", \ - "-0.047025600, -0.037098500, -0.013468800, 0.0387152000, 0.1366509000, 0.3028460000, 0.5747524000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1242895000, 0.1294140000, 0.1433708000, 0.1785351000, 0.2672481000, 0.4994049000, 1.1159752000", \ - "0.1276775000, 0.1328813000, 0.1454131000, 0.1812575000, 0.2711824000, 0.5036495000, 1.1203017000", \ - "0.1382974000, 0.1435033000, 0.1568400000, 0.1914459000, 0.2802888000, 0.5138448000, 1.1317360000", \ - "0.1649345000, 0.1695727000, 0.1832371000, 0.2172114000, 0.3065768000, 0.5396875000, 1.1581380000", \ - "0.2345044000, 0.2388629000, 0.2514190000, 0.2849294000, 0.3707515000, 0.6035237000, 1.2220156000", \ - "0.3678848000, 0.3747183000, 0.3908372000, 0.4334926000, 0.5297549000, 0.7573826000, 1.3715927000", \ - "0.5815742000, 0.5922757000, 0.6174434000, 0.6827597000, 0.8280323000, 1.1196831000, 1.7357924000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.0104760000, 0.0117560000, 0.0150543000, 0.0237915000, 0.0460590000, 0.1025857000, 0.2477178000", \ - "0.0118209000, 0.0127791000, 0.0157177000, 0.0238431000, 0.0460796000, 0.1026128000, 0.2476473000", \ - "0.0205801000, 0.0212519000, 0.0232169000, 0.0285837000, 0.0475929000, 0.1026060000, 0.2475988000", \ - "0.0380136000, 0.0384438000, 0.0403971000, 0.0463163000, 0.0617884000, 0.1075378000, 0.2476192000", \ - "0.0725255000, 0.0732079000, 0.0752531000, 0.0817151000, 0.1000530000, 0.1416801000, 0.2573909000", \ - "0.1309884000, 0.1318571000, 0.1350298000, 0.1434505000, 0.1676085000, 0.2231564000, 0.3342462000", \ - "0.2354857000, 0.2363042000, 0.2405327000, 0.2518671000, 0.2869990000, 0.3686941000, 0.5221759000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013504500, 0.0036474500, 0.0098514400, 0.0266078000, 0.0718653000, 0.1941020000"); - values("0.1192859000, 0.1251851000, 0.1411621000, 0.1844973000, 0.3008295000, 0.6131080000, 1.4544256000", \ - "0.1191252000, 0.1248050000, 0.1410409000, 0.1844719000, 0.3006306000, 0.6136238000, 1.4553424000", \ - "0.1192094000, 0.1248768000, 0.1407065000, 0.1844191000, 0.3008007000, 0.6136983000, 1.4582499000", \ - "0.1165067000, 0.1230146000, 0.1402851000, 0.1844750000, 0.3013359000, 0.6139853000, 1.4554596000", \ - "0.1275370000, 0.1327269000, 0.1471907000, 0.1874562000, 0.2999428000, 0.6134227000, 1.4569046000", \ - "0.1801594000, 0.1871363000, 0.2029633000, 0.2456498000, 0.3391263000, 0.6195948000, 1.4555108000", \ - "0.2670231000, 0.2773666000, 0.3032793000, 0.3650697000, 0.4877294000, 0.7390091000, 1.4771695000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2_0") { - leakage_power () { - value : 0.0021372000; - when : "!A&B"; - } - leakage_power () { - value : 0.0018183000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0015938000; - when : "A&B"; - } - leakage_power () { - value : 0.0021392000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__and2"; - cell_leakage_power : 0.0019221380; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028340000, 0.0028350000, 0.0028374000, 0.0028381000, 0.0028398000, 0.0028435000, 0.0028523000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002302000, -0.002304800, -0.002311300, -0.002307200, -0.002297900, -0.002276400, -0.002226700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016370000; - } - pin ("B") { - capacitance : 0.0016360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025515000, 0.0025532000, 0.0025572000, 0.0025558000, 0.0025526000, 0.0025452000, 0.0025281000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002545400, -0.002548200, -0.002554800, -0.002555000, -0.002555300, -0.002556000, -0.002557800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017000000; - } - pin ("X") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0068630000, 0.0059641000, 0.0034585000, -0.003322300, -0.020559700, -0.063152600, -0.167691700", \ - "0.0066871000, 0.0057835000, 0.0032842000, -0.003494100, -0.020735400, -0.063314700, -0.167859300", \ - "0.0064781000, 0.0055575000, 0.0030561000, -0.003729000, -0.020955500, -0.063546000, -0.168052400", \ - "0.0063337000, 0.0053756000, 0.0028382000, -0.003937000, -0.021150600, -0.063698000, -0.168211100", \ - "0.0062827000, 0.0052787000, 0.0027192000, -0.004051100, -0.021225900, -0.063745400, -0.168253700", \ - "0.0066738000, 0.0056145000, 0.0027544000, -0.004114500, -0.021092300, -0.063584200, -0.168067100", \ - "0.0074301000, 0.0062662000, 0.0034132000, -0.003578500, -0.020809100, -0.063052700, -0.167495900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0077923000, 0.0090531000, 0.0120271000, 0.0190883000, 0.0362965000, 0.0786425000, 0.1818601000", \ - "0.0077295000, 0.0089727000, 0.0119073000, 0.0190206000, 0.0363941000, 0.0785095000, 0.1815409000", \ - "0.0075919000, 0.0088343000, 0.0118033000, 0.0188749000, 0.0362529000, 0.0783741000, 0.1817688000", \ - "0.0073747000, 0.0086018000, 0.0115622000, 0.0186649000, 0.0361236000, 0.0786334000, 0.1811487000", \ - "0.0073489000, 0.0085215000, 0.0114117000, 0.0184971000, 0.0357264000, 0.0784030000, 0.1820081000", \ - "0.0075486000, 0.0087513000, 0.0116978000, 0.0185427000, 0.0358685000, 0.0780268000, 0.1816720000", \ - "0.0083457000, 0.0095439000, 0.0123670000, 0.0194622000, 0.0365510000, 0.0790413000, 0.1818882000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0085800000, 0.0076357000, 0.0051448000, -0.001623200, -0.018871700, -0.061409600, -0.166002400", \ - "0.0084238000, 0.0074777000, 0.0050088000, -0.001781500, -0.019019500, -0.061593900, -0.166117300", \ - "0.0082587000, 0.0073054000, 0.0048247000, -0.001952100, -0.019190500, -0.061757600, -0.166270300", \ - "0.0080808000, 0.0071188000, 0.0046032000, -0.002162700, -0.019370000, -0.061917400, -0.166405100", \ - "0.0079866000, 0.0070050000, 0.0044719000, -0.002302800, -0.019470800, -0.061984600, -0.166467900", \ - "0.0085642000, 0.0073705000, 0.0044944000, -0.002158000, -0.019245300, -0.061713100, -0.166204300", \ - "0.0093088000, 0.0080996000, 0.0053040000, -0.001694800, -0.019015500, -0.061266400, -0.165699400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0081737000, 0.0094241000, 0.0123840000, 0.0193884000, 0.0365666000, 0.0791169000, 0.1823453000", \ - "0.0081051000, 0.0093528000, 0.0123094000, 0.0193290000, 0.0365000000, 0.0784453000, 0.1824440000", \ - "0.0079694000, 0.0092148000, 0.0121650000, 0.0192203000, 0.0365796000, 0.0789408000, 0.1829798000", \ - "0.0077740000, 0.0090144000, 0.0119642000, 0.0190415000, 0.0364607000, 0.0783908000, 0.1826486000", \ - "0.0076979000, 0.0088834000, 0.0118371000, 0.0188813000, 0.0362912000, 0.0783911000, 0.1818888000", \ - "0.0077805000, 0.0089813000, 0.0119114000, 0.0188437000, 0.0362022000, 0.0784672000, 0.1818060000", \ - "0.0081169000, 0.0093889000, 0.0122890000, 0.0193746000, 0.0366712000, 0.0790474000, 0.1812274000"); - } - } - max_capacitance : 0.1089580000; - max_transition : 1.4991510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0958489000, 0.1029531000, 0.1171505000, 0.1456513000, 0.2064491000, 0.3498526000, 0.7025407000", \ - "0.1004987000, 0.1076292000, 0.1217150000, 0.1500706000, 0.2107952000, 0.3543048000, 0.7052036000", \ - "0.1128805000, 0.1199499000, 0.1342692000, 0.1625595000, 0.2233618000, 0.3669182000, 0.7184491000", \ - "0.1439616000, 0.1510409000, 0.1651600000, 0.1936321000, 0.2543728000, 0.3980555000, 0.7501326000", \ - "0.2108664000, 0.2184642000, 0.2335919000, 0.2628943000, 0.3242742000, 0.4677775000, 0.8186170000", \ - "0.3188114000, 0.3285782000, 0.3466414000, 0.3792925000, 0.4426598000, 0.5873800000, 0.9394070000", \ - "0.4881419000, 0.5008112000, 0.5245182000, 0.5645225000, 0.6343834000, 0.7783185000, 1.1299963000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0752522000, 0.0837830000, 0.1025016000, 0.1450376000, 0.2468896000, 0.4975805000, 1.1065879000", \ - "0.0794461000, 0.0879569000, 0.1065199000, 0.1491176000, 0.2509502000, 0.5002284000, 1.1227542000", \ - "0.0896535000, 0.0981665000, 0.1168216000, 0.1596975000, 0.2620836000, 0.5117828000, 1.1219243000", \ - "0.1121272000, 0.1206645000, 0.1393833000, 0.1819769000, 0.2842487000, 0.5346603000, 1.1435894000", \ - "0.1440993000, 0.1531844000, 0.1724720000, 0.2155254000, 0.3182551000, 0.5696880000, 1.1843247000", \ - "0.1810733000, 0.1918736000, 0.2124717000, 0.2559865000, 0.3584718000, 0.6083926000, 1.2214584000", \ - "0.2062279000, 0.2208046000, 0.2463838000, 0.2933893000, 0.3944339000, 0.6447692000, 1.2560825000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0230778000, 0.0287967000, 0.0414891000, 0.0709270000, 0.1453383000, 0.3340702000, 0.8047703000", \ - "0.0231011000, 0.0288550000, 0.0416559000, 0.0709072000, 0.1450551000, 0.3353646000, 0.8000125000", \ - "0.0230670000, 0.0289730000, 0.0415030000, 0.0709142000, 0.1448154000, 0.3337124000, 0.7998350000", \ - "0.0233435000, 0.0290475000, 0.0416021000, 0.0710441000, 0.1447398000, 0.3352974000, 0.8034225000", \ - "0.0275765000, 0.0329239000, 0.0449186000, 0.0731241000, 0.1456387000, 0.3344580000, 0.8046232000", \ - "0.0382062000, 0.0439881000, 0.0557166000, 0.0831890000, 0.1521169000, 0.3349588000, 0.8034549000", \ - "0.0559984000, 0.0623168000, 0.0754523000, 0.1020050000, 0.1647797000, 0.3414649000, 0.8003451000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0274992000, 0.0366333000, 0.0595508000, 0.1173182000, 0.2624949000, 0.6204234000, 1.4924092000", \ - "0.0274641000, 0.0367120000, 0.0594145000, 0.1171731000, 0.2626016000, 0.6211412000, 1.4940631000", \ - "0.0274866000, 0.0367100000, 0.0595502000, 0.1170192000, 0.2618886000, 0.6194957000, 1.4923682000", \ - "0.0286739000, 0.0376392000, 0.0600514000, 0.1174412000, 0.2631610000, 0.6217848000, 1.4923507000", \ - "0.0319919000, 0.0406756000, 0.0626975000, 0.1189916000, 0.2626313000, 0.6204083000, 1.4973701000", \ - "0.0410414000, 0.0486958000, 0.0680830000, 0.1214559000, 0.2646635000, 0.6178478000, 1.4919401000", \ - "0.0573377000, 0.0660958000, 0.0833266000, 0.1301706000, 0.2655788000, 0.6223080000, 1.4866247000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1126999000, 0.1199489000, 0.1343062000, 0.1630200000, 0.2240139000, 0.3677476000, 0.7195449000", \ - "0.1173471000, 0.1245710000, 0.1389256000, 0.1676634000, 0.2286660000, 0.3724204000, 0.7246753000", \ - "0.1304566000, 0.1375008000, 0.1520297000, 0.1808161000, 0.2418786000, 0.3856503000, 0.7379672000", \ - "0.1623976000, 0.1696073000, 0.1840509000, 0.2128420000, 0.2740032000, 0.4179159000, 0.7702495000", \ - "0.2362592000, 0.2436170000, 0.2583560000, 0.2873330000, 0.3487008000, 0.4927621000, 0.8438623000", \ - "0.3645999000, 0.3738300000, 0.3913209000, 0.4235730000, 0.4874733000, 0.6319180000, 0.9830288000", \ - "0.5710318000, 0.5832477000, 0.6057349000, 0.6448904000, 0.7134323000, 0.8595282000, 1.2113196000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0803792000, 0.0889442000, 0.1075194000, 0.1498586000, 0.2516419000, 0.5013673000, 1.1159204000", \ - "0.0846716000, 0.0932035000, 0.1118141000, 0.1542319000, 0.2559783000, 0.5045606000, 1.1198444000", \ - "0.0936200000, 0.1020834000, 0.1206927000, 0.1631720000, 0.2649174000, 0.5139220000, 1.1265442000", \ - "0.1125423000, 0.1211529000, 0.1398727000, 0.1824676000, 0.2842930000, 0.5384062000, 1.1448866000", \ - "0.1424705000, 0.1515920000, 0.1712244000, 0.2145392000, 0.3170356000, 0.5678666000, 1.1781190000", \ - "0.1790546000, 0.1894161000, 0.2104380000, 0.2544176000, 0.3569176000, 0.6069732000, 1.2211507000", \ - "0.2008568000, 0.2147890000, 0.2404958000, 0.2878161000, 0.3908465000, 0.6406112000, 1.2515926000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0243607000, 0.0301199000, 0.0430418000, 0.0721899000, 0.1460550000, 0.3347599000, 0.8049927000", \ - "0.0246222000, 0.0299565000, 0.0430313000, 0.0722380000, 0.1455552000, 0.3359477000, 0.8038880000", \ - "0.0246108000, 0.0302531000, 0.0430030000, 0.0721967000, 0.1458831000, 0.3357112000, 0.8038936000", \ - "0.0243757000, 0.0299630000, 0.0426697000, 0.0722586000, 0.1457936000, 0.3367742000, 0.8067698000", \ - "0.0264904000, 0.0317361000, 0.0440506000, 0.0729494000, 0.1458915000, 0.3359634000, 0.8034433000", \ - "0.0367133000, 0.0419991000, 0.0536667000, 0.0811936000, 0.1502534000, 0.3375589000, 0.8001194000", \ - "0.0535745000, 0.0604539000, 0.0728338000, 0.0990822000, 0.1621616000, 0.3410443000, 0.8009410000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0274653000, 0.0366912000, 0.0593641000, 0.1173513000, 0.2618662000, 0.6226599000, 1.4965975000", \ - "0.0274582000, 0.0366192000, 0.0595104000, 0.1174119000, 0.2620522000, 0.6200324000, 1.4964113000", \ - "0.0274832000, 0.0366858000, 0.0595240000, 0.1171425000, 0.2629552000, 0.6209246000, 1.4991507000", \ - "0.0283206000, 0.0374047000, 0.0598450000, 0.1171074000, 0.2632298000, 0.6216443000, 1.4933768000", \ - "0.0314397000, 0.0402645000, 0.0621731000, 0.1187061000, 0.2624588000, 0.6227732000, 1.4942578000", \ - "0.0387352000, 0.0467951000, 0.0673129000, 0.1211942000, 0.2634451000, 0.6169676000, 1.4929702000", \ - "0.0537890000, 0.0629611000, 0.0819241000, 0.1290368000, 0.2649888000, 0.6216637000, 1.4902407000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2_1") { - leakage_power () { - value : 0.0031719000; - when : "!A&B"; - } - leakage_power () { - value : 0.0028440000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0014741000; - when : "A&B"; - } - leakage_power () { - value : 0.0031700000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__and2"; - cell_leakage_power : 0.0026650080; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025379000, 0.0025400000, 0.0025448000, 0.0025448000, 0.0025447000, 0.0025445000, 0.0025440000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001956100, -0.001957000, -0.001959300, -0.001955200, -0.001945900, -0.001924400, -0.001874800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014920000; - } - pin ("B") { - capacitance : 0.0014960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022875000, 0.0022876000, 0.0022879000, 0.0022886000, 0.0022901000, 0.0022938000, 0.0023021000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002284200, -0.002283900, -0.002283100, -0.002283200, -0.002283500, -0.002284000, -0.002285200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015600000; - } - pin ("X") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0085240000, 0.0074664000, 0.0046369000, -0.003676900, -0.026596400, -0.087127000, -0.245422400", \ - "0.0083931000, 0.0073403000, 0.0045021000, -0.003805000, -0.026716700, -0.087233700, -0.245554800", \ - "0.0082197000, 0.0071245000, 0.0042612000, -0.004033200, -0.026937400, -0.087455000, -0.245748300", \ - "0.0079991000, 0.0069151000, 0.0040167000, -0.004303500, -0.027186600, -0.087673800, -0.245952000", \ - "0.0080176000, 0.0068765000, 0.0039774000, -0.004402800, -0.027255800, -0.087711400, -0.245954800", \ - "0.0088907000, 0.0075031000, 0.0041860000, -0.004514700, -0.027130700, -0.087510900, -0.245699200", \ - "0.0097210000, 0.0083623000, 0.0048614000, -0.003959300, -0.026952200, -0.087195000, -0.245292000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0094704000, 0.0108522000, 0.0143551000, 0.0232112000, 0.0462251000, 0.1062811000, 0.2614212000", \ - "0.0093983000, 0.0107825000, 0.0142948000, 0.0232034000, 0.0462224000, 0.1062042000, 0.2627313000", \ - "0.0092865000, 0.0106624000, 0.0141663000, 0.0231015000, 0.0461635000, 0.1061495000, 0.2630470000", \ - "0.0091534000, 0.0105032000, 0.0139926000, 0.0228474000, 0.0459524000, 0.1059391000, 0.2624917000", \ - "0.0090617000, 0.0104091000, 0.0138378000, 0.0227020000, 0.0458110000, 0.1059986000, 0.2611088000", \ - "0.0093870000, 0.0107110000, 0.0141771000, 0.0227496000, 0.0458959000, 0.1060684000, 0.2626684000", \ - "0.0102133000, 0.0114561000, 0.0148248000, 0.0237647000, 0.0465589000, 0.1068110000, 0.2629192000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0101951000, 0.0090964000, 0.0061835000, -0.002195800, -0.025150600, -0.085714800, -0.243986000", \ - "0.0100591000, 0.0089721000, 0.0060136000, -0.002323200, -0.025284600, -0.085834800, -0.244153700", \ - "0.0099392000, 0.0088303000, 0.0058713000, -0.002460900, -0.025428100, -0.085962400, -0.244240000", \ - "0.0097425000, 0.0086176000, 0.0056732000, -0.002675700, -0.025604700, -0.086115800, -0.244393500", \ - "0.0096279000, 0.0084970000, 0.0055326000, -0.002829200, -0.025731000, -0.086200000, -0.244446800", \ - "0.0101414000, 0.0088554000, 0.0057637000, -0.002614100, -0.025418700, -0.085861200, -0.244071200", \ - "0.0115284000, 0.0101688000, 0.0071464000, -0.002204000, -0.025332000, -0.085656700, -0.243846800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0099540000, 0.0113288000, 0.0148601000, 0.0237230000, 0.0466245000, 0.1064193000, 0.2628997000", \ - "0.0099071000, 0.0112947000, 0.0147963000, 0.0235943000, 0.0465181000, 0.1070239000, 0.2636375000", \ - "0.0097941000, 0.0111693000, 0.0146685000, 0.0235634000, 0.0465247000, 0.1069565000, 0.2629234000", \ - "0.0096171000, 0.0109888000, 0.0144687000, 0.0233895000, 0.0463804000, 0.1063675000, 0.2643670000", \ - "0.0095336000, 0.0108720000, 0.0143180000, 0.0231603000, 0.0462240000, 0.1062808000, 0.2632289000", \ - "0.0097039000, 0.0110450000, 0.0144742000, 0.0232250000, 0.0463406000, 0.1059751000, 0.2629322000", \ - "0.0100696000, 0.0112933000, 0.0147459000, 0.0236581000, 0.0468086000, 0.1071174000, 0.2634866000"); - } - } - max_capacitance : 0.1583960000; - max_transition : 1.5104930000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.1031383000, 0.1090369000, 0.1213519000, 0.1458819000, 0.1983965000, 0.3245319000, 0.6507022000", \ - "0.1078665000, 0.1139983000, 0.1263610000, 0.1508638000, 0.2034434000, 0.3294200000, 0.6551888000", \ - "0.1206382000, 0.1264383000, 0.1387166000, 0.1632862000, 0.2158505000, 0.3420344000, 0.6674351000", \ - "0.1518939000, 0.1576136000, 0.1699008000, 0.1946328000, 0.2471551000, 0.3730970000, 0.6997410000", \ - "0.2217431000, 0.2278479000, 0.2405078000, 0.2657816000, 0.3188938000, 0.4447553000, 0.7715348000", \ - "0.3381809000, 0.3460206000, 0.3619098000, 0.3912823000, 0.4477396000, 0.5756008000, 0.8998989000", \ - "0.5209776000, 0.5311577000, 0.5518847000, 0.5890423000, 0.6537268000, 0.7846471000, 1.1087463000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0794242000, 0.0864667000, 0.1026603000, 0.1403230000, 0.2350631000, 0.4803423000, 1.1196789000", \ - "0.0835845000, 0.0906672000, 0.1068781000, 0.1445428000, 0.2394144000, 0.4849028000, 1.1245087000", \ - "0.0941941000, 0.1012077000, 0.1174051000, 0.1552419000, 0.2499132000, 0.4948990000, 1.1391017000", \ - "0.1176439000, 0.1247226000, 0.1408894000, 0.1787277000, 0.2738498000, 0.5216426000, 1.1591080000", \ - "0.1531869000, 0.1607167000, 0.1775795000, 0.2162935000, 0.3111585000, 0.5577310000, 1.1975008000", \ - "0.1957092000, 0.2050777000, 0.2236305000, 0.2628502000, 0.3577440000, 0.6035356000, 1.2459085000", \ - "0.2281206000, 0.2408570000, 0.2647271000, 0.3094159000, 0.4035527000, 0.6494337000, 1.2897596000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0234153000, 0.0276024000, 0.0374098000, 0.0604597000, 0.1196515000, 0.2827106000, 0.7157019000", \ - "0.0233323000, 0.0278020000, 0.0374386000, 0.0605734000, 0.1193361000, 0.2823191000, 0.7152689000", \ - "0.0236597000, 0.0276025000, 0.0373997000, 0.0604277000, 0.1196194000, 0.2826888000, 0.7158011000", \ - "0.0234196000, 0.0278806000, 0.0376073000, 0.0605204000, 0.1195282000, 0.2822352000, 0.7153240000", \ - "0.0272264000, 0.0310681000, 0.0402238000, 0.0623276000, 0.1203398000, 0.2819205000, 0.7129985000", \ - "0.0383181000, 0.0427394000, 0.0521954000, 0.0735420000, 0.1279992000, 0.2841739000, 0.7151715000", \ - "0.0565871000, 0.0622415000, 0.0731304000, 0.0952605000, 0.1458810000, 0.2922328000, 0.7139613000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0273098000, 0.0343713000, 0.0528321000, 0.1021536000, 0.2350815000, 0.5873246000, 1.4968455000", \ - "0.0273840000, 0.0345314000, 0.0528703000, 0.1020276000, 0.2352878000, 0.5844607000, 1.5043444000", \ - "0.0272861000, 0.0344569000, 0.0528450000, 0.1020791000, 0.2354850000, 0.5860426000, 1.5063638000", \ - "0.0281736000, 0.0351018000, 0.0533746000, 0.1020422000, 0.2353452000, 0.5880494000, 1.4962932000", \ - "0.0322034000, 0.0387938000, 0.0565736000, 0.1041765000, 0.2354808000, 0.5855712000, 1.5004152000", \ - "0.0416308000, 0.0483148000, 0.0637518000, 0.1082114000, 0.2369543000, 0.5852857000, 1.5016702000", \ - "0.0592551000, 0.0662234000, 0.0807632000, 0.1200596000, 0.2402845000, 0.5869897000, 1.4960598000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.1209156000, 0.1267669000, 0.1392474000, 0.1641813000, 0.2170752000, 0.3433146000, 0.6697209000", \ - "0.1256830000, 0.1315514000, 0.1440896000, 0.1689204000, 0.2217300000, 0.3480779000, 0.6741255000", \ - "0.1389034000, 0.1447728000, 0.1571298000, 0.1822106000, 0.2351275000, 0.3612713000, 0.6883352000", \ - "0.1707242000, 0.1765896000, 0.1891511000, 0.2141875000, 0.2671949000, 0.3935670000, 0.7206127000", \ - "0.2458760000, 0.2518757000, 0.2643657000, 0.2895802000, 0.3426674000, 0.4691481000, 0.7961913000", \ - "0.3811535000, 0.3887241000, 0.4037608000, 0.4324255000, 0.4886735000, 0.6161632000, 0.9428820000", \ - "0.5985440000, 0.6084658000, 0.6283749000, 0.6649080000, 0.7281128000, 0.8587321000, 1.1855078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0850944000, 0.0921667000, 0.1083601000, 0.1458898000, 0.2402782000, 0.4848659000, 1.1236686000", \ - "0.0895209000, 0.0965853000, 0.1127460000, 0.1502857000, 0.2446479000, 0.4893743000, 1.1342737000", \ - "0.0986120000, 0.1056416000, 0.1217442000, 0.1594235000, 0.2536776000, 0.4999385000, 1.1385588000", \ - "0.1181221000, 0.1252344000, 0.1413930000, 0.1790957000, 0.2739872000, 0.5188981000, 1.1647858000", \ - "0.1507703000, 0.1583374000, 0.1753158000, 0.2136513000, 0.3088211000, 0.5540685000, 1.1962887000", \ - "0.1919068000, 0.2007971000, 0.2194776000, 0.2593621000, 0.3543002000, 0.6003611000, 1.2398564000", \ - "0.2215551000, 0.2331939000, 0.2570880000, 0.3014003000, 0.3978440000, 0.6441577000, 1.2831414000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0247853000, 0.0292438000, 0.0387901000, 0.0620392000, 0.1209422000, 0.2836178000, 0.7178857000", \ - "0.0248114000, 0.0293590000, 0.0386992000, 0.0620453000, 0.1208171000, 0.2830563000, 0.7159824000", \ - "0.0251101000, 0.0293904000, 0.0389104000, 0.0620770000, 0.1207057000, 0.2830010000, 0.7188303000", \ - "0.0248417000, 0.0293683000, 0.0387121000, 0.0619855000, 0.1210290000, 0.2832596000, 0.7174237000", \ - "0.0263278000, 0.0301791000, 0.0395620000, 0.0626238000, 0.1210035000, 0.2826644000, 0.7209016000", \ - "0.0372131000, 0.0416577000, 0.0506625000, 0.0722733000, 0.1267676000, 0.2838049000, 0.7191795000", \ - "0.0552276000, 0.0607121000, 0.0714424000, 0.0921616000, 0.1430103000, 0.2911559000, 0.7147608000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0273552000, 0.0344671000, 0.0528882000, 0.1019307000, 0.2352126000, 0.5862400000, 1.5035762000", \ - "0.0273356000, 0.0344320000, 0.0528311000, 0.1021694000, 0.2347287000, 0.5867600000, 1.5065106000", \ - "0.0274144000, 0.0344779000, 0.0527378000, 0.1020965000, 0.2352505000, 0.5875913000, 1.5000867000", \ - "0.0280319000, 0.0350671000, 0.0532333000, 0.1021433000, 0.2352442000, 0.5851101000, 1.5104931000", \ - "0.0312514000, 0.0380700000, 0.0560639000, 0.1036146000, 0.2350764000, 0.5868111000, 1.5016937000", \ - "0.0386276000, 0.0457767000, 0.0620114000, 0.1072882000, 0.2371053000, 0.5845895000, 1.5012384000", \ - "0.0545211000, 0.0615401000, 0.0773975000, 0.1178962000, 0.2399373000, 0.5878344000, 1.4954710000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2_2") { - leakage_power () { - value : 0.0039778000; - when : "!A&B"; - } - leakage_power () { - value : 0.0036338000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0018727000; - when : "A&B"; - } - leakage_power () { - value : 0.0039927000; - when : "A&!B"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__and2"; - cell_leakage_power : 0.0033692280; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025787000, 0.0025778000, 0.0025757000, 0.0025755000, 0.0025752000, 0.0025746000, 0.0025730000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001982600, -0.001985500, -0.001992300, -0.001988000, -0.001978000, -0.001955200, -0.001902400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014830000; - } - pin ("B") { - capacitance : 0.0014720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022826000, 0.0022812000, 0.0022779000, 0.0022784000, 0.0022795000, 0.0022822000, 0.0022883000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002279600, -0.002276700, -0.002270000, -0.002270200, -0.002270400, -0.002271000, -0.002272400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015410000; - } - pin ("X") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0117543000, 0.0103079000, 0.0064083000, -0.005064600, -0.041817800, -0.152068000, -0.474139400", \ - "0.0116692000, 0.0102267000, 0.0063563000, -0.005214300, -0.041882300, -0.152187300, -0.474213500", \ - "0.0115564000, 0.0100950000, 0.0061755000, -0.005380300, -0.042084300, -0.152341000, -0.474376700", \ - "0.0113755000, 0.0098629000, 0.0059359000, -0.005661300, -0.042342500, -0.152546900, -0.474589400", \ - "0.0111773000, 0.0096786000, 0.0059532000, -0.005749100, -0.042600500, -0.152773100, -0.474742800", \ - "0.0117980000, 0.0103075000, 0.0054038000, -0.005842200, -0.042640800, -0.152844200, -0.474706200", \ - "0.0153806000, 0.0135958000, 0.0087413000, -0.004558300, -0.042453700, -0.152586100, -0.474325400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0146731000, 0.0162788000, 0.0209847000, 0.0344096000, 0.0723212000, 0.1818844000, 0.5006528000", \ - "0.0146472000, 0.0162724000, 0.0210165000, 0.0342933000, 0.0723475000, 0.1817968000, 0.5006438000", \ - "0.0145676000, 0.0162075000, 0.0209238000, 0.0342467000, 0.0722084000, 0.1817449000, 0.5031501000", \ - "0.0145392000, 0.0161674000, 0.0208704000, 0.0342218000, 0.0720574000, 0.1817553000, 0.5011114000", \ - "0.0144982000, 0.0161072000, 0.0207718000, 0.0339634000, 0.0715973000, 0.1815939000, 0.4984059000", \ - "0.0150638000, 0.0166019000, 0.0210662000, 0.0340177000, 0.0716022000, 0.1804869000, 0.5007694000", \ - "0.0163117000, 0.0177632000, 0.0221268000, 0.0352554000, 0.0727947000, 0.1819054000, 0.4987252000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0134696000, 0.0120180000, 0.0079642000, -0.003653300, -0.040532700, -0.150791100, -0.472886600", \ - "0.0132903000, 0.0117997000, 0.0078386000, -0.003739800, -0.040629400, -0.150896800, -0.472993900", \ - "0.0131979000, 0.0116908000, 0.0077379000, -0.003941800, -0.040758500, -0.150997600, -0.473079600", \ - "0.0130356000, 0.0115439000, 0.0075622000, -0.004091500, -0.040877300, -0.151177100, -0.473183100", \ - "0.0130784000, 0.0115552000, 0.0075391000, -0.004243200, -0.041127200, -0.151343600, -0.473301800", \ - "0.0130149000, 0.0114388000, 0.0072822000, -0.004059600, -0.040986900, -0.151287400, -0.473258600", \ - "0.0170820000, 0.0152849000, 0.0104698000, -0.002581800, -0.040647300, -0.150932700, -0.472868300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0151865000, 0.0168168000, 0.0215584000, 0.0347919000, 0.0727728000, 0.1822645000, 0.5024664000", \ - "0.0151702000, 0.0168151000, 0.0214851000, 0.0348589000, 0.0726719000, 0.1822710000, 0.5010122000", \ - "0.0150463000, 0.0166822000, 0.0213946000, 0.0347023000, 0.0726703000, 0.1822337000, 0.5033337000", \ - "0.0149685000, 0.0166021000, 0.0213348000, 0.0346575000, 0.0724922000, 0.1821337000, 0.5014783000", \ - "0.0149247000, 0.0165151000, 0.0212182000, 0.0343565000, 0.0723027000, 0.1820207000, 0.5014984000", \ - "0.0155276000, 0.0170649000, 0.0216251000, 0.0345882000, 0.0720163000, 0.1814026000, 0.5026486000", \ - "0.0162574000, 0.0177564000, 0.0221687000, 0.0352553000, 0.0729662000, 0.1827096000, 0.5008285000"); - } - } - max_capacitance : 0.3030490000; - max_transition : 1.5057800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.1364071000, 0.1418157000, 0.1541442000, 0.1792684000, 0.2293132000, 0.3450230000, 0.6619946000", \ - "0.1416111000, 0.1470187000, 0.1593495000, 0.1845761000, 0.2345699000, 0.3504547000, 0.6673611000", \ - "0.1542877000, 0.1596582000, 0.1719276000, 0.1971277000, 0.2470832000, 0.3628070000, 0.6799235000", \ - "0.1851654000, 0.1905413000, 0.2028390000, 0.2278691000, 0.2780798000, 0.3938639000, 0.7109625000", \ - "0.2595029000, 0.2648475000, 0.2769676000, 0.3019138000, 0.3522006000, 0.4680429000, 0.7847200000", \ - "0.4005576000, 0.4070511000, 0.4219907000, 0.4509234000, 0.5053586000, 0.6234845000, 0.9403769000", \ - "0.6243880000, 0.6330449000, 0.6524813000, 0.6902249000, 0.7569049000, 0.8837219000, 1.2016257000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0979053000, 0.1038914000, 0.1182502000, 0.1513566000, 0.2339801000, 0.4672650000, 1.1413402000", \ - "0.1022707000, 0.1082777000, 0.1226557000, 0.1555695000, 0.2383861000, 0.4718838000, 1.1487145000", \ - "0.1128362000, 0.1189557000, 0.1332549000, 0.1662914000, 0.2490047000, 0.4817577000, 1.1572244000", \ - "0.1377473000, 0.1438027000, 0.1580598000, 0.1909931000, 0.2735761000, 0.5066922000, 1.1843485000", \ - "0.1840116000, 0.1903861000, 0.2055685000, 0.2393427000, 0.3223771000, 0.5565326000, 1.2317655000", \ - "0.2442716000, 0.2524390000, 0.2698434000, 0.3065319000, 0.3910942000, 0.6235067000, 1.2984965000", \ - "0.3030587000, 0.3138884000, 0.3379232000, 0.3826174000, 0.4700909000, 0.7018189000, 1.3771542000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0277559000, 0.0310736000, 0.0391022000, 0.0573323000, 0.1044718000, 0.2406137000, 0.6627560000", \ - "0.0276743000, 0.0310357000, 0.0389816000, 0.0573615000, 0.1045062000, 0.2410272000, 0.6599468000", \ - "0.0278697000, 0.0313137000, 0.0389624000, 0.0576597000, 0.1046146000, 0.2407712000, 0.6597430000", \ - "0.0278804000, 0.0312867000, 0.0393970000, 0.0573128000, 0.1045276000, 0.2409501000, 0.6595259000", \ - "0.0282353000, 0.0314154000, 0.0402463000, 0.0580400000, 0.1049777000, 0.2414620000, 0.6647693000", \ - "0.0404417000, 0.0441529000, 0.0522760000, 0.0700773000, 0.1130105000, 0.2439002000, 0.6609731000", \ - "0.0616221000, 0.0656455000, 0.0758334000, 0.0967075000, 0.1385238000, 0.2602116000, 0.6622231000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0262547000, 0.0313493000, 0.0446448000, 0.0812598000, 0.1918287000, 0.5261477000, 1.5011272000", \ - "0.0262657000, 0.0312228000, 0.0445179000, 0.0810991000, 0.1919225000, 0.5251414000, 1.4996066000", \ - "0.0263817000, 0.0313686000, 0.0445823000, 0.0812658000, 0.1919214000, 0.5249874000, 1.5030975000", \ - "0.0262734000, 0.0312734000, 0.0444390000, 0.0812956000, 0.1917528000, 0.5269601000, 1.5053194000", \ - "0.0306689000, 0.0357580000, 0.0481469000, 0.0835879000, 0.1926219000, 0.5253208000, 1.4981015000", \ - "0.0415067000, 0.0463481000, 0.0585462000, 0.0907611000, 0.1961538000, 0.5255698000, 1.5002397000", \ - "0.0589621000, 0.0654241000, 0.0797694000, 0.1111835000, 0.2045499000, 0.5278779000, 1.4969760000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.1558299000, 0.1614587000, 0.1741890000, 0.1996477000, 0.2506957000, 0.3670645000, 0.6843777000", \ - "0.1607572000, 0.1663703000, 0.1790987000, 0.2045177000, 0.2556772000, 0.3720091000, 0.6893619000", \ - "0.1740037000, 0.1795904000, 0.1923255000, 0.2180000000, 0.2688531000, 0.3852432000, 0.7025615000", \ - "0.2058436000, 0.2114687000, 0.2242208000, 0.2498287000, 0.3008377000, 0.4173971000, 0.7345343000", \ - "0.2822132000, 0.2877884000, 0.3004429000, 0.3260738000, 0.3772591000, 0.4937820000, 0.8112417000", \ - "0.4390603000, 0.4456899000, 0.4604577000, 0.4890418000, 0.5427345000, 0.6601903000, 0.9775145000", \ - "0.6954046000, 0.7039635000, 0.7236417000, 0.7609182000, 0.8259712000, 0.9519316000, 1.2699251000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.1034967000, 0.1095161000, 0.1238951000, 0.1568059000, 0.2394919000, 0.4719508000, 1.1479453000", \ - "0.1080419000, 0.1140426000, 0.1282747000, 0.1613830000, 0.2439290000, 0.4775650000, 1.1508836000", \ - "0.1170988000, 0.1231137000, 0.1374552000, 0.1704393000, 0.2531770000, 0.4856827000, 1.1602203000", \ - "0.1376836000, 0.1436330000, 0.1579747000, 0.1908991000, 0.2734294000, 0.5073726000, 1.1842225000", \ - "0.1763889000, 0.1828160000, 0.1978548000, 0.2318321000, 0.3149285000, 0.5477792000, 1.2263611000", \ - "0.2313141000, 0.2387638000, 0.2559056000, 0.2921681000, 0.3765182000, 0.6096989000, 1.2891400000", \ - "0.2845534000, 0.2945381000, 0.3166900000, 0.3593771000, 0.4476765000, 0.6810682000, 1.3550648000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0299345000, 0.0330403000, 0.0415794000, 0.0602454000, 0.1064846000, 0.2422293000, 0.6638477000", \ - "0.0296371000, 0.0330950000, 0.0414024000, 0.0605492000, 0.1063452000, 0.2419041000, 0.6641499000", \ - "0.0299386000, 0.0330109000, 0.0415399000, 0.0595342000, 0.1065693000, 0.2421634000, 0.6644975000", \ - "0.0296639000, 0.0330590000, 0.0410142000, 0.0599194000, 0.1065710000, 0.2421447000, 0.6639496000", \ - "0.0300756000, 0.0332108000, 0.0414059000, 0.0596753000, 0.1064786000, 0.2416065000, 0.6633563000", \ - "0.0401013000, 0.0432791000, 0.0514824000, 0.0692921000, 0.1118586000, 0.2435755000, 0.6636997000", \ - "0.0614068000, 0.0653008000, 0.0753478000, 0.0955680000, 0.1374687000, 0.2587044000, 0.6627545000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0262797000, 0.0311947000, 0.0444734000, 0.0812766000, 0.1915664000, 0.5251167000, 1.5010247000", \ - "0.0263118000, 0.0312779000, 0.0446028000, 0.0812698000, 0.1918466000, 0.5249897000, 1.5006529000", \ - "0.0262559000, 0.0312214000, 0.0445993000, 0.0812137000, 0.1916287000, 0.5252688000, 1.5057801000", \ - "0.0264730000, 0.0312215000, 0.0445229000, 0.0812302000, 0.1917469000, 0.5251012000, 1.5041181000", \ - "0.0293697000, 0.0343510000, 0.0473197000, 0.0832465000, 0.1922883000, 0.5271021000, 1.5053249000", \ - "0.0371512000, 0.0420075000, 0.0551279000, 0.0892049000, 0.1957395000, 0.5247283000, 1.5004159000", \ - "0.0519232000, 0.0581657000, 0.0724698000, 0.1044502000, 0.2020811000, 0.5270284000, 1.4948588000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2_4") { - leakage_power () { - value : 0.0045182000; - when : "!A&B"; - } - leakage_power () { - value : 0.0042181000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0049141000; - when : "A&B"; - } - leakage_power () { - value : 0.0045368000; - when : "A&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__and2"; - cell_leakage_power : 0.0045468170; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046441000, 0.0046450000, 0.0046471000, 0.0046473000, 0.0046477000, 0.0046486000, 0.0046508000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003813900, -0.003815400, -0.003818900, -0.003812800, -0.003798900, -0.003766900, -0.003693100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023990000; - } - pin ("B") { - capacitance : 0.0024240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043132000, 0.0043138000, 0.0043151000, 0.0043147000, 0.0043138000, 0.0043118000, 0.0043072000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004314400, -0.004314000, -0.004313200, -0.004313100, -0.004312900, -0.004312500, -0.004311400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025590000; - } - pin ("X") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0219934000, 0.0203575000, 0.0153407000, -0.000571600, -0.056486100, -0.243191300, -0.843738500", \ - "0.0218637000, 0.0202414000, 0.0152177000, -0.000721400, -0.056630900, -0.243270800, -0.843826200", \ - "0.0216027000, 0.0199616000, 0.0148455000, -0.000961400, -0.056924000, -0.243539000, -0.844065200", \ - "0.0213800000, 0.0197347000, 0.0145553000, -0.001499200, -0.057400200, -0.243932800, -0.844342500", \ - "0.0217083000, 0.0199763000, 0.0145601000, -0.001760400, -0.057926300, -0.244305500, -0.844611500", \ - "0.0235541000, 0.0215797000, 0.0157522000, -0.002316000, -0.058359200, -0.243979100, -0.844365700", \ - "0.0291198000, 0.0269686000, 0.0199042000, 0.0011556000, -0.057032300, -0.243583300, -0.843218800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0268359000, 0.0287043000, 0.0347671000, 0.0535348000, 0.1121659000, 0.2986388000, 0.8936575000", \ - "0.0267891000, 0.0286378000, 0.0345587000, 0.0535035000, 0.1123113000, 0.2984654000, 0.8886216000", \ - "0.0265147000, 0.0283975000, 0.0344192000, 0.0534200000, 0.1121571000, 0.2983078000, 0.8937819000", \ - "0.0264661000, 0.0283159000, 0.0343476000, 0.0532022000, 0.1118517000, 0.2980327000, 0.8925930000", \ - "0.0265940000, 0.0284016000, 0.0342972000, 0.0525095000, 0.1109989000, 0.2977092000, 0.8935497000", \ - "0.0281363000, 0.0298973000, 0.0355536000, 0.0536864000, 0.1110265000, 0.2967123000, 0.8928317000", \ - "0.0300397000, 0.0317357000, 0.0372010000, 0.0551988000, 0.1127392000, 0.2987017000, 0.8901778000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0242342000, 0.0226232000, 0.0174575000, 0.0013143000, -0.054620700, -0.241329300, -0.841892600", \ - "0.0241061000, 0.0224827000, 0.0172657000, 0.0013069000, -0.054743600, -0.241436100, -0.842009200", \ - "0.0239825000, 0.0223074000, 0.0171334000, 0.0009634000, -0.055016900, -0.241636800, -0.842178200", \ - "0.0237839000, 0.0221014000, 0.0168350000, 0.0006720000, -0.055315700, -0.241879000, -0.842381100", \ - "0.0239839000, 0.0222619000, 0.0168394000, 0.0003758000, -0.055343300, -0.241928800, -0.842348400", \ - "0.0241729000, 0.0222595000, 0.0164405000, -0.000333700, -0.055474400, -0.241754300, -0.841946200", \ - "0.0310029000, 0.0288509000, 0.0225415000, 0.0047170000, -0.054509000, -0.241373200, -0.841389900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0274649000, 0.0293370000, 0.0352974000, 0.0541880000, 0.1129284000, 0.2988462000, 0.8976207000", \ - "0.0274234000, 0.0292947000, 0.0353569000, 0.0541434000, 0.1128546000, 0.2989904000, 0.8934235000", \ - "0.0271964000, 0.0290773000, 0.0350998000, 0.0540511000, 0.1127472000, 0.2986478000, 0.8940299000", \ - "0.0270387000, 0.0288931000, 0.0349200000, 0.0538420000, 0.1124182000, 0.2984832000, 0.8906550000", \ - "0.0269662000, 0.0288491000, 0.0347595000, 0.0531925000, 0.1118951000, 0.2983111000, 0.8934664000", \ - "0.0278650000, 0.0296570000, 0.0353535000, 0.0535465000, 0.1117268000, 0.2970995000, 0.8926131000", \ - "0.0291608000, 0.0308249000, 0.0364298000, 0.0544184000, 0.1126395000, 0.2987646000, 0.8925423000"); - } - } - max_capacitance : 0.5392550000; - max_transition : 1.5073040000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1075722000, 0.1108711000, 0.1194063000, 0.1385359000, 0.1792587000, 0.2814725000, 0.5909777000", \ - "0.1128001000, 0.1160923000, 0.1245839000, 0.1437462000, 0.1845300000, 0.2868012000, 0.5967698000", \ - "0.1254879000, 0.1292502000, 0.1377147000, 0.1568275000, 0.1976561000, 0.2999596000, 0.6103894000", \ - "0.1569157000, 0.1602705000, 0.1687679000, 0.1878012000, 0.2287325000, 0.3310373000, 0.6413503000", \ - "0.2290461000, 0.2324625000, 0.2411661000, 0.2602894000, 0.3015657000, 0.4041014000, 0.7136133000", \ - "0.3514737000, 0.3558933000, 0.3672617000, 0.3916203000, 0.4386747000, 0.5434140000, 0.8522572000", \ - "0.5428690000, 0.5485799000, 0.5634483000, 0.5957725000, 0.6554340000, 0.7709175000, 1.0814671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1001052000, 0.1044490000, 0.1158731000, 0.1439631000, 0.2175814000, 0.4404515000, 1.1489737000", \ - "0.1042852000, 0.1085675000, 0.1199086000, 0.1480933000, 0.2216752000, 0.4448077000, 1.1530928000", \ - "0.1145495000, 0.1188651000, 0.1303157000, 0.1584149000, 0.2319022000, 0.4550954000, 1.1663756000", \ - "0.1389479000, 0.1432470000, 0.1546415000, 0.1827197000, 0.2562166000, 0.4799561000, 1.1956172000", \ - "0.1854124000, 0.1900212000, 0.2022073000, 0.2309741000, 0.3050086000, 0.5274398000, 1.2392685000", \ - "0.2445943000, 0.2506001000, 0.2655731000, 0.2977021000, 0.3730493000, 0.5964311000, 1.3060746000", \ - "0.3022301000, 0.3098472000, 0.3292155000, 0.3698066000, 0.4514374000, 0.6732024000, 1.3816840000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0217115000, 0.0234817000, 0.0291566000, 0.0426379000, 0.0811186000, 0.2037033000, 0.6203453000", \ - "0.0214940000, 0.0235378000, 0.0291617000, 0.0428483000, 0.0810571000, 0.2035903000, 0.6206806000", \ - "0.0215759000, 0.0235712000, 0.0288988000, 0.0429835000, 0.0811935000, 0.2035723000, 0.6187569000", \ - "0.0215966000, 0.0236828000, 0.0291780000, 0.0429033000, 0.0810994000, 0.2037923000, 0.6189805000", \ - "0.0241568000, 0.0261043000, 0.0312016000, 0.0443087000, 0.0822326000, 0.2042058000, 0.6222320000", \ - "0.0363429000, 0.0388287000, 0.0446289000, 0.0585859000, 0.0932091000, 0.2086272000, 0.6198016000", \ - "0.0564236000, 0.0588638000, 0.0670648000, 0.0834888000, 0.1181764000, 0.2244491000, 0.6188730000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0249653000, 0.0284283000, 0.0381845000, 0.0673825000, 0.1621492000, 0.4790814000, 1.5012275000", \ - "0.0249947000, 0.0283563000, 0.0383610000, 0.0673585000, 0.1621393000, 0.4793477000, 1.5013665000", \ - "0.0249919000, 0.0284311000, 0.0383725000, 0.0672879000, 0.1619728000, 0.4793616000, 1.5033943000", \ - "0.0249676000, 0.0284299000, 0.0382230000, 0.0673482000, 0.1619671000, 0.4784575000, 1.5049285000", \ - "0.0293278000, 0.0325243000, 0.0420544000, 0.0700699000, 0.1630664000, 0.4788117000, 1.5054440000", \ - "0.0399405000, 0.0435059000, 0.0532515000, 0.0787437000, 0.1672937000, 0.4788523000, 1.5021409000", \ - "0.0576111000, 0.0612524000, 0.0734685000, 0.0982774000, 0.1780262000, 0.4818362000, 1.4969254000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1255966000, 0.1291250000, 0.1381782000, 0.1582270000, 0.2002370000, 0.3035514000, 0.6133271000", \ - "0.1310570000, 0.1345455000, 0.1434573000, 0.1634322000, 0.2055105000, 0.3088259000, 0.6187498000", \ - "0.1438751000, 0.1472799000, 0.1570833000, 0.1771827000, 0.2192748000, 0.3225942000, 0.6325042000", \ - "0.1762233000, 0.1797537000, 0.1888648000, 0.2088671000, 0.2507718000, 0.3541753000, 0.6643017000", \ - "0.2523053000, 0.2557794000, 0.2647994000, 0.2847366000, 0.3259102000, 0.4294096000, 0.7400690000", \ - "0.3940385000, 0.3985494000, 0.4100280000, 0.4343532000, 0.4810699000, 0.5871086000, 0.8975454000", \ - "0.6222710000, 0.6279829000, 0.6433246000, 0.6759321000, 0.7356510000, 0.8508389000, 1.1626645000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1052030000, 0.1095009000, 0.1209242000, 0.1491337000, 0.2226441000, 0.4451655000, 1.1547054000", \ - "0.1094998000, 0.1138446000, 0.1252630000, 0.1533589000, 0.2269185000, 0.4495909000, 1.1581007000", \ - "0.1185689000, 0.1228791000, 0.1343074000, 0.1624743000, 0.2358514000, 0.4586717000, 1.1697386000", \ - "0.1389187000, 0.1432541000, 0.1546988000, 0.1827786000, 0.2561527000, 0.4791273000, 1.1967589000", \ - "0.1778365000, 0.1824616000, 0.1945080000, 0.2235293000, 0.2976709000, 0.5202719000, 1.2281585000", \ - "0.2311435000, 0.2367548000, 0.2508218000, 0.2824046000, 0.3587645000, 0.5815975000, 1.2940511000", \ - "0.2793611000, 0.2865273000, 0.3049423000, 0.3435750000, 0.4241753000, 0.6473023000, 1.3555471000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0241419000, 0.0259677000, 0.0318131000, 0.0454388000, 0.0839345000, 0.2055038000, 0.6209739000", \ - "0.0241401000, 0.0262818000, 0.0314745000, 0.0455130000, 0.0838626000, 0.2055502000, 0.6215251000", \ - "0.0239680000, 0.0260806000, 0.0315359000, 0.0455867000, 0.0839582000, 0.2055777000, 0.6211461000", \ - "0.0241108000, 0.0262833000, 0.0314738000, 0.0458092000, 0.0839025000, 0.2055762000, 0.6216975000", \ - "0.0246488000, 0.0267049000, 0.0324516000, 0.0460825000, 0.0844081000, 0.2057645000, 0.6185589000", \ - "0.0371110000, 0.0395494000, 0.0451100000, 0.0582432000, 0.0934432000, 0.2088847000, 0.6175619000", \ - "0.0573322000, 0.0602757000, 0.0679052000, 0.0842567000, 0.1184644000, 0.2241975000, 0.6199924000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0249482000, 0.0283355000, 0.0382583000, 0.0674461000, 0.1619367000, 0.4789714000, 1.5073039000", \ - "0.0249776000, 0.0284419000, 0.0381678000, 0.0673835000, 0.1621627000, 0.4791031000, 1.5024892000", \ - "0.0249770000, 0.0284064000, 0.0383676000, 0.0672702000, 0.1618237000, 0.4792354000, 1.5032409000", \ - "0.0249320000, 0.0283174000, 0.0383013000, 0.0672791000, 0.1617747000, 0.4792219000, 1.5017381000", \ - "0.0279188000, 0.0314126000, 0.0412130000, 0.0695779000, 0.1629917000, 0.4805606000, 1.5029451000", \ - "0.0358768000, 0.0395254000, 0.0489308000, 0.0766307000, 0.1666984000, 0.4782073000, 1.5043545000", \ - "0.0512571000, 0.0550663000, 0.0661057000, 0.0927317000, 0.1760204000, 0.4814027000, 1.4971808000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2b_1") { - leakage_power () { - value : 0.0011725000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0064238000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0069574000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0066454000; - when : "A_N&!B"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__and2b"; - cell_leakage_power : 0.0052998180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0064953000, 0.0063858000, 0.0061335000, 0.0061711000, 0.0062576000, 0.0064572000, 0.0069170000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022895000, 0.0022114000, 0.0020313000, 0.0020622000, 0.0021334000, 0.0022975000, 0.0026757000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016200000; - } - pin ("B") { - capacitance : 0.0016410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027312000, 0.0027277000, 0.0027197000, 0.0027198000, 0.0027198000, 0.0027200000, 0.0027203000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002728500, -0.002722700, -0.002709400, -0.002709600, -0.002710100, -0.002711200, -0.002713800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017100000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0074935000, 0.0063767000, 0.0034907000, -0.005056500, -0.029153200, -0.093596400, -0.263855300", \ - "0.0074615000, 0.0063473000, 0.0034617000, -0.005088800, -0.029187500, -0.093631300, -0.264031400", \ - "0.0074080000, 0.0063151000, 0.0034000000, -0.005160700, -0.029252100, -0.093707900, -0.264134800", \ - "0.0070621000, 0.0059710000, 0.0030545000, -0.005501000, -0.029594100, -0.094028400, -0.264467200", \ - "0.0067670000, 0.0056730000, 0.0027625000, -0.005808100, -0.029885500, -0.094320200, -0.264753400", \ - "0.0077758000, 0.0066284000, 0.0032824000, -0.005677700, -0.029961900, -0.094385000, -0.264800500", \ - "0.0080097000, 0.0067373000, 0.0033607000, -0.005765000, -0.029866000, -0.094216000, -0.264709000"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0107229000, 0.0121567000, 0.0157871000, 0.0250888000, 0.0492976000, 0.1130790000, 0.2833514000", \ - "0.0106409000, 0.0120710000, 0.0156960000, 0.0250075000, 0.0492152000, 0.1136795000, 0.2834403000", \ - "0.0107082000, 0.0121188000, 0.0157694000, 0.0250929000, 0.0493041000, 0.1138411000, 0.2817097000", \ - "0.0105537000, 0.0119603000, 0.0156124000, 0.0249333000, 0.0491499000, 0.1136807000, 0.2814867000", \ - "0.0103154000, 0.0117464000, 0.0154094000, 0.0246977000, 0.0488982000, 0.1134589000, 0.2815859000", \ - "0.0102670000, 0.0116193000, 0.0151769000, 0.0246308000, 0.0487984000, 0.1125745000, 0.2815379000", \ - "0.0104464000, 0.0118109000, 0.0153750000, 0.0246923000, 0.0486490000, 0.1129486000, 0.2819707000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0079535000, 0.0068127000, 0.0037296000, -0.005028500, -0.029246400, -0.093751500, -0.264195900", \ - "0.0078302000, 0.0066852000, 0.0036332000, -0.005133400, -0.029355600, -0.093849300, -0.264271400", \ - "0.0076646000, 0.0065152000, 0.0034400000, -0.005323900, -0.029505300, -0.094004600, -0.264458400", \ - "0.0075132000, 0.0063450000, 0.0032648000, -0.005498800, -0.029690700, -0.094144300, -0.264577000", \ - "0.0075533000, 0.0063529000, 0.0032511000, -0.005557400, -0.029729100, -0.094161200, -0.264560000", \ - "0.0079112000, 0.0065782000, 0.0030516000, -0.005624900, -0.029706400, -0.094081200, -0.264467000", \ - "0.0090901000, 0.0077078000, 0.0040932000, -0.005091400, -0.029483800, -0.093712200, -0.264085800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0110563000, 0.0125044000, 0.0161606000, 0.0253488000, 0.0494525000, 0.1132007000, 0.2816314000", \ - "0.0109835000, 0.0124374000, 0.0160377000, 0.0253371000, 0.0494307000, 0.1138509000, 0.2834915000", \ - "0.0108426000, 0.0122828000, 0.0159265000, 0.0251935000, 0.0493201000, 0.1131013000, 0.2831438000", \ - "0.0106853000, 0.0120959000, 0.0157381000, 0.0250403000, 0.0492392000, 0.1130062000, 0.2820709000", \ - "0.0106267000, 0.0119908000, 0.0155867000, 0.0248663000, 0.0490749000, 0.1136625000, 0.2830712000", \ - "0.0109476000, 0.0122623000, 0.0157790000, 0.0248220000, 0.0491127000, 0.1131103000, 0.2814059000", \ - "0.0113153000, 0.0126001000, 0.0161412000, 0.0253813000, 0.0496870000, 0.1136278000, 0.2821418000"); - } - } - max_capacitance : 0.1693830000; - max_transition : 1.5054720000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1392650000, 0.1458357000, 0.1593139000, 0.1860438000, 0.2419807000, 0.3768078000, 0.7286305000", \ - "0.1439327000, 0.1504916000, 0.1639517000, 0.1906770000, 0.2466204000, 0.3814537000, 0.7333245000", \ - "0.1545366000, 0.1611028000, 0.1746691000, 0.2012972000, 0.2572374000, 0.3919094000, 0.7436498000", \ - "0.1746736000, 0.1812186000, 0.1947530000, 0.2214205000, 0.2773547000, 0.4121894000, 0.7641930000", \ - "0.2036706000, 0.2102273000, 0.2238358000, 0.2504734000, 0.3064524000, 0.4414209000, 0.7934335000", \ - "0.2392959000, 0.2455047000, 0.2592673000, 0.2861039000, 0.3422300000, 0.4769604000, 0.8288117000", \ - "0.2733526000, 0.2799868000, 0.2935377000, 0.3203983000, 0.3766646000, 0.5115428000, 0.8643506000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1492003000, 0.1564235000, 0.1725819000, 0.2099364000, 0.3030909000, 0.5486901000, 1.1914337000", \ - "0.1536454000, 0.1609205000, 0.1770845000, 0.2142684000, 0.3072854000, 0.5510123000, 1.1956970000", \ - "0.1664387000, 0.1736225000, 0.1899007000, 0.2272088000, 0.3200731000, 0.5638116000, 1.2061662000", \ - "0.1981163000, 0.2052915000, 0.2215710000, 0.2588745000, 0.3518001000, 0.5950800000, 1.2392886000", \ - "0.2639613000, 0.2712435000, 0.2875205000, 0.3248054000, 0.4179941000, 0.6613859000, 1.3083492000", \ - "0.3708452000, 0.3782895000, 0.3947194000, 0.4321646000, 0.5255128000, 0.7693361000, 1.4148568000", \ - "0.5401635000, 0.5480243000, 0.5649956000, 0.6030036000, 0.6965747000, 0.9404294000, 1.5831167000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0229365000, 0.0271649000, 0.0375263000, 0.0616576000, 0.1235068000, 0.2968437000, 0.7630824000", \ - "0.0229216000, 0.0274942000, 0.0375277000, 0.0616572000, 0.1235014000, 0.2969376000, 0.7718066000", \ - "0.0229698000, 0.0270342000, 0.0374335000, 0.0618211000, 0.1237793000, 0.2987758000, 0.7640988000", \ - "0.0227934000, 0.0271371000, 0.0375491000, 0.0616255000, 0.1237057000, 0.2969390000, 0.7695316000", \ - "0.0228061000, 0.0273095000, 0.0374318000, 0.0617115000, 0.1238234000, 0.2988951000, 0.7665937000", \ - "0.0230600000, 0.0279017000, 0.0380791000, 0.0619374000, 0.1239544000, 0.2943655000, 0.7700216000", \ - "0.0238065000, 0.0281861000, 0.0389182000, 0.0624980000, 0.1242564000, 0.2972474000, 0.7656155000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0241662000, 0.0310191000, 0.0485768000, 0.0960339000, 0.2266130000, 0.5766232000, 1.5031136000", \ - "0.0240961000, 0.0309602000, 0.0487198000, 0.0961521000, 0.2262074000, 0.5774111000, 1.5046057000", \ - "0.0241192000, 0.0310659000, 0.0486482000, 0.0960338000, 0.2265092000, 0.5784240000, 1.4968609000", \ - "0.0241428000, 0.0310903000, 0.0486816000, 0.0960221000, 0.2264206000, 0.5782594000, 1.4972334000", \ - "0.0245398000, 0.0313107000, 0.0488383000, 0.0962749000, 0.2264389000, 0.5780660000, 1.5047629000", \ - "0.0254376000, 0.0322740000, 0.0496234000, 0.0969410000, 0.2259456000, 0.5752397000, 1.5001612000", \ - "0.0281758000, 0.0347108000, 0.0514864000, 0.0978821000, 0.2269993000, 0.5736586000, 1.4927060000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1199863000, 0.1265781000, 0.1400131000, 0.1666531000, 0.2224236000, 0.3570231000, 0.7099723000", \ - "0.1250548000, 0.1316339000, 0.1452184000, 0.1716032000, 0.2274099000, 0.3621982000, 0.7145364000", \ - "0.1379036000, 0.1444814000, 0.1580019000, 0.1845344000, 0.2403661000, 0.3751293000, 0.7278572000", \ - "0.1694781000, 0.1760865000, 0.1896301000, 0.2161382000, 0.2720285000, 0.4068058000, 0.7591652000", \ - "0.2458634000, 0.2524315000, 0.2658675000, 0.2925810000, 0.3485419000, 0.4834041000, 0.8373479000", \ - "0.3838306000, 0.3921876000, 0.4088603000, 0.4390783000, 0.4983279000, 0.6343951000, 0.9872323000", \ - "0.6065288000, 0.6179148000, 0.6395095000, 0.6781659000, 0.7451771000, 0.8840089000, 1.2363512000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0838781000, 0.0911042000, 0.1072763000, 0.1442256000, 0.2366408000, 0.4805009000, 1.1243945000", \ - "0.0882505000, 0.0954667000, 0.1115282000, 0.1487114000, 0.2411155000, 0.4848837000, 1.1286794000", \ - "0.0967619000, 0.1039781000, 0.1201182000, 0.1572448000, 0.2501456000, 0.4934158000, 1.1372914000", \ - "0.1150863000, 0.1223202000, 0.1385309000, 0.1757465000, 0.2687521000, 0.5120033000, 1.1563656000", \ - "0.1460576000, 0.1538838000, 0.1709790000, 0.2088468000, 0.3023193000, 0.5465656000, 1.1936251000", \ - "0.1858267000, 0.1949655000, 0.2141958000, 0.2538680000, 0.3476875000, 0.5917902000, 1.2352768000", \ - "0.2123323000, 0.2249135000, 0.2497402000, 0.2948591000, 0.3904713000, 0.6353933000, 1.2774820000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0234037000, 0.0278373000, 0.0380796000, 0.0620759000, 0.1241979000, 0.2967690000, 0.7654454000", \ - "0.0236030000, 0.0279404000, 0.0381719000, 0.0621983000, 0.1240991000, 0.2979788000, 0.7661394000", \ - "0.0234166000, 0.0277736000, 0.0379419000, 0.0621270000, 0.1239001000, 0.2991705000, 0.7670851000", \ - "0.0237789000, 0.0280063000, 0.0381488000, 0.0621028000, 0.1242366000, 0.2974057000, 0.7646313000", \ - "0.0246207000, 0.0288136000, 0.0387680000, 0.0626422000, 0.1240993000, 0.2971583000, 0.7674734000", \ - "0.0349228000, 0.0397025000, 0.0493984000, 0.0722056000, 0.1296210000, 0.2985638000, 0.7692271000", \ - "0.0518292000, 0.0580550000, 0.0698601000, 0.0927064000, 0.1459282000, 0.3053101000, 0.7645866000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0237516000, 0.0306288000, 0.0484043000, 0.0960915000, 0.2264680000, 0.5761326000, 1.4949072000", \ - "0.0237342000, 0.0306288000, 0.0484193000, 0.0960477000, 0.2265569000, 0.5785052000, 1.5040148000", \ - "0.0237889000, 0.0306684000, 0.0483784000, 0.0960552000, 0.2265904000, 0.5765163000, 1.5020080000", \ - "0.0243544000, 0.0312152000, 0.0486778000, 0.0960202000, 0.2264808000, 0.5765746000, 1.5013124000", \ - "0.0273969000, 0.0342241000, 0.0515200000, 0.0979892000, 0.2265500000, 0.5788929000, 1.5054720000", \ - "0.0349308000, 0.0413823000, 0.0576584000, 0.1019669000, 0.2287239000, 0.5751755000, 1.5006382000", \ - "0.0493190000, 0.0568586000, 0.0746315000, 0.1130123000, 0.2315859000, 0.5774929000, 1.4931757000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2b_2") { - leakage_power () { - value : 0.0015416000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0059357000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0064236000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0060981000; - when : "A_N&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__and2b"; - cell_leakage_power : 0.0049997770; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0064813000, 0.0063732000, 0.0061239000, 0.0061612000, 0.0062472000, 0.0064452000, 0.0069018000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022962000, 0.0022188000, 0.0020405000, 0.0020716000, 0.0021433000, 0.0023085000, 0.0026894000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016140000; - } - pin ("B") { - capacitance : 0.0016150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027262000, 0.0027243000, 0.0027198000, 0.0027199000, 0.0027202000, 0.0027208000, 0.0027221000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002710100, -0.002710800, -0.002712300, -0.002712100, -0.002711700, -0.002710700, -0.002708400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016890000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0108792000, 0.0094126000, 0.0054275000, -0.006232900, -0.043590600, -0.156254400, -0.486800900", \ - "0.0108308000, 0.0093985000, 0.0053140000, -0.006342200, -0.043610300, -0.156300000, -0.486769300", \ - "0.0107778000, 0.0092629000, 0.0053128000, -0.006348100, -0.043652300, -0.156319700, -0.486842300", \ - "0.0105191000, 0.0090044000, 0.0049527000, -0.006711000, -0.043993300, -0.156676700, -0.487184000", \ - "0.0101963000, 0.0087101000, 0.0046716000, -0.007022000, -0.044321100, -0.157009700, -0.487485000", \ - "0.0124212000, 0.0108659000, 0.0064972000, -0.006419200, -0.044510700, -0.157127400, -0.487644600", \ - "0.0127006000, 0.0111210000, 0.0067206000, -0.006268700, -0.044214200, -0.157013100, -0.487567300"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0155175000, 0.0171418000, 0.0219818000, 0.0355831000, 0.0741804000, 0.1862382000, 0.5137075000", \ - "0.0154663000, 0.0171357000, 0.0218730000, 0.0354698000, 0.0740790000, 0.1860376000, 0.5139083000", \ - "0.0155659000, 0.0172119000, 0.0219543000, 0.0355559000, 0.0742195000, 0.1862010000, 0.5159220000", \ - "0.0153662000, 0.0170012000, 0.0218045000, 0.0354153000, 0.0740529000, 0.1862345000, 0.5163918000", \ - "0.0152050000, 0.0168890000, 0.0216786000, 0.0352736000, 0.0738608000, 0.1859678000, 0.5108036000", \ - "0.0150623000, 0.0166123000, 0.0214041000, 0.0351211000, 0.0735112000, 0.1855893000, 0.5135332000", \ - "0.0157211000, 0.0173135000, 0.0219765000, 0.0352086000, 0.0734418000, 0.1862541000, 0.5121162000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0113806000, 0.0098560000, 0.0057794000, -0.006146600, -0.043783300, -0.156513100, -0.487087800", \ - "0.0113027000, 0.0098028000, 0.0056985000, -0.006236500, -0.043839100, -0.156605300, -0.487170600", \ - "0.0111453000, 0.0096247000, 0.0055308000, -0.006377700, -0.043952400, -0.156756400, -0.487313900", \ - "0.0110554000, 0.0095119000, 0.0053740000, -0.006559200, -0.044155800, -0.156956300, -0.487471600", \ - "0.0110127000, 0.0094304000, 0.0052755000, -0.006737000, -0.044439100, -0.157052100, -0.487506200", \ - "0.0114175000, 0.0098331000, 0.0054978000, -0.006637800, -0.044396600, -0.156963400, -0.487440200", \ - "0.0148845000, 0.0130182000, 0.0080482000, -0.005472600, -0.044016500, -0.156927100, -0.487249700"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0159053000, 0.0175599000, 0.0223863000, 0.0360007000, 0.0743126000, 0.1862654000, 0.5135810000", \ - "0.0158601000, 0.0175341000, 0.0222775000, 0.0358765000, 0.0744294000, 0.1863308000, 0.5136738000", \ - "0.0157938000, 0.0174182000, 0.0222373000, 0.0358409000, 0.0743407000, 0.1861464000, 0.5137789000", \ - "0.0156762000, 0.0173154000, 0.0221337000, 0.0357178000, 0.0742875000, 0.1864110000, 0.5140683000", \ - "0.0155829000, 0.0171979000, 0.0219188000, 0.0354100000, 0.0739139000, 0.1859981000, 0.5139336000", \ - "0.0163628000, 0.0179149000, 0.0225114000, 0.0356838000, 0.0739361000, 0.1855171000, 0.5159234000", \ - "0.0168520000, 0.0182865000, 0.0226891000, 0.0361789000, 0.0747322000, 0.1867609000, 0.5132093000"); - } - } - max_capacitance : 0.3103740000; - max_transition : 1.5057120000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.1765197000, 0.1826900000, 0.1964538000, 0.2238739000, 0.2770446000, 0.3992628000, 0.7336132000", \ - "0.1812401000, 0.1874475000, 0.2012143000, 0.2284999000, 0.2817818000, 0.4040056000, 0.7389081000", \ - "0.1920104000, 0.1981920000, 0.2119543000, 0.2392622000, 0.2924937000, 0.4146393000, 0.7489811000", \ - "0.2122167000, 0.2183911000, 0.2321217000, 0.2592470000, 0.3127891000, 0.4348031000, 0.7688479000", \ - "0.2405787000, 0.2467121000, 0.2604159000, 0.2878207000, 0.3412467000, 0.4634101000, 0.7977892000", \ - "0.2760639000, 0.2822936000, 0.2960673000, 0.3233853000, 0.3770129000, 0.4993315000, 0.8339669000", \ - "0.3090702000, 0.3152641000, 0.3290872000, 0.3555608000, 0.4093780000, 0.5316387000, 0.8663003000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.1700012000, 0.1764596000, 0.1914246000, 0.2248580000, 0.3074179000, 0.5403244000, 1.2168544000", \ - "0.1745668000, 0.1810082000, 0.1958455000, 0.2293528000, 0.3120524000, 0.5445739000, 1.2214870000", \ - "0.1874478000, 0.1939096000, 0.2087614000, 0.2422800000, 0.3250639000, 0.5585487000, 1.2357744000", \ - "0.2193295000, 0.2257749000, 0.2407577000, 0.2741757000, 0.3569918000, 0.5895782000, 1.2677824000", \ - "0.2855137000, 0.2920449000, 0.3069631000, 0.3404786000, 0.4231627000, 0.6565340000, 1.3352207000", \ - "0.3939680000, 0.4005561000, 0.4157922000, 0.4494802000, 0.5322542000, 0.7650081000, 1.4412966000", \ - "0.5672018000, 0.5740460000, 0.5896172000, 0.6236842000, 0.7065830000, 0.9393776000, 1.6174574000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0275449000, 0.0311855000, 0.0400301000, 0.0598609000, 0.1088450000, 0.2512204000, 0.6985473000", \ - "0.0274724000, 0.0315213000, 0.0401271000, 0.0596366000, 0.1088919000, 0.2517871000, 0.6968691000", \ - "0.0273229000, 0.0311943000, 0.0399298000, 0.0597897000, 0.1088531000, 0.2518135000, 0.6950513000", \ - "0.0273571000, 0.0312749000, 0.0399482000, 0.0600923000, 0.1086337000, 0.2517471000, 0.6987399000", \ - "0.0275425000, 0.0315245000, 0.0401670000, 0.0601009000, 0.1088526000, 0.2522600000, 0.6990807000", \ - "0.0276124000, 0.0315115000, 0.0401721000, 0.0604002000, 0.1089065000, 0.2502583000, 0.6992885000", \ - "0.0280589000, 0.0319782000, 0.0405452000, 0.0605014000, 0.1091105000, 0.2519601000, 0.6930780000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0241164000, 0.0294162000, 0.0426465000, 0.0789264000, 0.1885448000, 0.5233995000, 1.5029606000", \ - "0.0242268000, 0.0293478000, 0.0426587000, 0.0788475000, 0.1886505000, 0.5215075000, 1.5023333000", \ - "0.0242517000, 0.0294196000, 0.0426909000, 0.0789661000, 0.1884785000, 0.5210411000, 1.5051221000", \ - "0.0241711000, 0.0295066000, 0.0425804000, 0.0787838000, 0.1886021000, 0.5218548000, 1.5027881000", \ - "0.0243175000, 0.0294999000, 0.0426559000, 0.0789893000, 0.1887480000, 0.5225230000, 1.4983328000", \ - "0.0254398000, 0.0304469000, 0.0435469000, 0.0796179000, 0.1887182000, 0.5211069000, 1.5009949000", \ - "0.0272476000, 0.0325890000, 0.0451597000, 0.0809771000, 0.1893824000, 0.5202188000, 1.4981324000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.1564695000, 0.1627235000, 0.1766041000, 0.2038083000, 0.2571247000, 0.3791034000, 0.7136676000", \ - "0.1616480000, 0.1679492000, 0.1817965000, 0.2090265000, 0.2622648000, 0.3843298000, 0.7189223000", \ - "0.1748777000, 0.1811492000, 0.1948327000, 0.2220547000, 0.2753445000, 0.3969962000, 0.7320680000", \ - "0.2066890000, 0.2129821000, 0.2267970000, 0.2539117000, 0.3072141000, 0.4293031000, 0.7636931000", \ - "0.2835548000, 0.2898588000, 0.3035320000, 0.3307198000, 0.3840480000, 0.5055241000, 0.8406457000", \ - "0.4431867000, 0.4505371000, 0.4664087000, 0.4964100000, 0.5521855000, 0.6748083000, 1.0097071000", \ - "0.7058621000, 0.7154256000, 0.7360412000, 0.7755994000, 0.8426595000, 0.9744512000, 1.3107380000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.1041473000, 0.1106062000, 0.1255237000, 0.1589402000, 0.2413441000, 0.4742567000, 1.1530479000", \ - "0.1085822000, 0.1150315000, 0.1298314000, 0.1632795000, 0.2458584000, 0.4784904000, 1.1575024000", \ - "0.1172795000, 0.1236506000, 0.1385256000, 0.1719698000, 0.2543676000, 0.4865210000, 1.1651460000", \ - "0.1365768000, 0.1430329000, 0.1579463000, 0.1912442000, 0.2738140000, 0.5063004000, 1.1864466000", \ - "0.1735315000, 0.1804587000, 0.1962489000, 0.2305827000, 0.3137835000, 0.5464035000, 1.2258224000", \ - "0.2269366000, 0.2352428000, 0.2532024000, 0.2900981000, 0.3746165000, 0.6075824000, 1.2877264000", \ - "0.2782292000, 0.2890176000, 0.3121403000, 0.3562502000, 0.4450668000, 0.6776250000, 1.3545746000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0282495000, 0.0322083000, 0.0407479000, 0.0602929000, 0.1088637000, 0.2512010000, 0.6936987000", \ - "0.0284679000, 0.0321021000, 0.0406383000, 0.0602939000, 0.1088866000, 0.2512373000, 0.6936955000", \ - "0.0282731000, 0.0321590000, 0.0408664000, 0.0605419000, 0.1090090000, 0.2513964000, 0.6925337000", \ - "0.0284941000, 0.0321223000, 0.0407259000, 0.0603876000, 0.1088850000, 0.2514856000, 0.6988451000", \ - "0.0284399000, 0.0321190000, 0.0411502000, 0.0603762000, 0.1088499000, 0.2518471000, 0.6957749000", \ - "0.0374613000, 0.0414614000, 0.0502299000, 0.0685562000, 0.1142293000, 0.2532353000, 0.6936869000", \ - "0.0576871000, 0.0628522000, 0.0737636000, 0.0940272000, 0.1379205000, 0.2664464000, 0.6958203000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0240450000, 0.0292072000, 0.0424155000, 0.0787000000, 0.1886049000, 0.5227538000, 1.5022815000", \ - "0.0240257000, 0.0291248000, 0.0423920000, 0.0788752000, 0.1887371000, 0.5227566000, 1.5028242000", \ - "0.0240263000, 0.0292938000, 0.0423970000, 0.0788919000, 0.1883724000, 0.5214431000, 1.5033279000", \ - "0.0241072000, 0.0291038000, 0.0424409000, 0.0788079000, 0.1887295000, 0.5219845000, 1.5052749000", \ - "0.0269120000, 0.0321105000, 0.0454773000, 0.0808025000, 0.1892352000, 0.5217343000, 1.5011768000", \ - "0.0338178000, 0.0393770000, 0.0528795000, 0.0866986000, 0.1925336000, 0.5219295000, 1.5057117000", \ - "0.0481104000, 0.0550341000, 0.0694728000, 0.1029067000, 0.1994503000, 0.5243244000, 1.4979014000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and2b_4") { - leakage_power () { - value : 0.0054714000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0041313000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0044127000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0041132000; - when : "A_N&!B"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__and2b"; - cell_leakage_power : 0.0045321500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0014540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0069181000, 0.0068267000, 0.0066159000, 0.0066588000, 0.0067576000, 0.0069855000, 0.0075106000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050925000, 0.0050377000, 0.0049115000, 0.0049469000, 0.0050286000, 0.0052168000, 0.0056507000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015110000; - } - pin ("B") { - capacitance : 0.0024580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043432000, 0.0043435000, 0.0043443000, 0.0043440000, 0.0043435000, 0.0043421000, 0.0043391000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004348900, -0.004349100, -0.004349500, -0.004350000, -0.004351000, -0.004353200, -0.004358500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026040000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015642280, 0.0048936190, 0.0153094700, 0.0478950100, 0.1498374000, 0.4687599000"); - values("0.0214844000, 0.0199401000, 0.0150008000, 0.0004092000, -0.049443900, -0.213402300, -0.729670700", \ - "0.0214899000, 0.0199418000, 0.0150411000, 0.0004189000, -0.049444500, -0.213348400, -0.729760800", \ - "0.0213677000, 0.0198618000, 0.0149783000, 0.0003388000, -0.049494400, -0.213402300, -0.729663500", \ - "0.0210931000, 0.0194732000, 0.0146011000, -6.33000e-05, -0.049892300, -0.213790400, -0.730176500", \ - "0.0207515000, 0.0191785000, 0.0143269000, -0.000402700, -0.050269900, -0.214214400, -0.730480600", \ - "0.0241251000, 0.0225347000, 0.0174741000, 0.0014506000, -0.050355800, -0.214494100, -0.730766700", \ - "0.0246035000, 0.0229025000, 0.0178074000, 0.0016917000, -0.050025900, -0.214207900, -0.730746700"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015642280, 0.0048936190, 0.0153094700, 0.0478950100, 0.1498374000, 0.4687599000"); - values("0.0288406000, 0.0306420000, 0.0361764000, 0.0535890000, 0.1065358000, 0.2702767000, 0.7815690000", \ - "0.0287390000, 0.0305591000, 0.0361332000, 0.0535413000, 0.1065131000, 0.2701249000, 0.7815219000", \ - "0.0287716000, 0.0305924000, 0.0361678000, 0.0535745000, 0.1065484000, 0.2701647000, 0.7815829000", \ - "0.0285645000, 0.0303986000, 0.0360654000, 0.0533311000, 0.1063256000, 0.2699368000, 0.7811642000", \ - "0.0284143000, 0.0301710000, 0.0357929000, 0.0532866000, 0.1060729000, 0.2698771000, 0.7817430000", \ - "0.0280377000, 0.0298441000, 0.0354905000, 0.0528951000, 0.1056788000, 0.2694481000, 0.7817898000", \ - "0.0291359000, 0.0308635000, 0.0363579000, 0.0535204000, 0.1054638000, 0.2694952000, 0.7800839000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015642280, 0.0048936190, 0.0153094700, 0.0478950100, 0.1498374000, 0.4687599000"); - values("0.0223316000, 0.0206939000, 0.0156312000, 0.0007665000, -0.049634400, -0.213915800, -0.730453800", \ - "0.0222662000, 0.0205346000, 0.0155544000, 0.0005715000, -0.049784400, -0.214048700, -0.730555700", \ - "0.0219147000, 0.0203632000, 0.0152287000, 0.0003549000, -0.050001100, -0.214225700, -0.730731400", \ - "0.0218287000, 0.0201232000, 0.0150372000, 0.0001153000, -0.050192900, -0.214391400, -0.730901400", \ - "0.0219508000, 0.0202555000, 0.0150905000, -0.000148600, -0.050505100, -0.214634000, -0.730999700", \ - "0.0217128000, 0.0199013000, 0.0144801000, -0.000698400, -0.050215000, -0.214327000, -0.730720300", \ - "0.0287738000, 0.0267308000, 0.0207150000, 0.0033202000, -0.049179300, -0.213765400, -0.729719400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015642280, 0.0048936190, 0.0153094700, 0.0478950100, 0.1498374000, 0.4687599000"); - values("0.0291431000, 0.0309616000, 0.0366713000, 0.0539651000, 0.1069154000, 0.2704652000, 0.7818152000", \ - "0.0290457000, 0.0308822000, 0.0365904000, 0.0538623000, 0.1068531000, 0.2704659000, 0.7818133000", \ - "0.0288127000, 0.0306313000, 0.0363510000, 0.0538437000, 0.1067072000, 0.2702150000, 0.7817056000", \ - "0.0286126000, 0.0304313000, 0.0361218000, 0.0536087000, 0.1064102000, 0.2700218000, 0.7784069000", \ - "0.0285004000, 0.0302659000, 0.0358464000, 0.0531117000, 0.1058226000, 0.2698109000, 0.7817476000", \ - "0.0293982000, 0.0311254000, 0.0365500000, 0.0536773000, 0.1057829000, 0.2689911000, 0.7807458000", \ - "0.0307100000, 0.0323451000, 0.0375953000, 0.0542615000, 0.1066638000, 0.2706210000, 0.7789450000"); - } - } - max_capacitance : 0.4687600000; - max_transition : 1.5039480000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.1525040000, 0.1559737000, 0.1647313000, 0.1839920000, 0.2238943000, 0.3180468000, 0.5880077000", \ - "0.1574602000, 0.1608749000, 0.1696388000, 0.1888790000, 0.2287818000, 0.3229747000, 0.5929557000", \ - "0.1685003000, 0.1719269000, 0.1806698000, 0.1998986000, 0.2398791000, 0.3341059000, 0.6040799000", \ - "0.1906725000, 0.1940988000, 0.2028259000, 0.2220486000, 0.2620339000, 0.3562932000, 0.6262795000", \ - "0.2230246000, 0.2264390000, 0.2351853000, 0.2542172000, 0.2943167000, 0.3885509000, 0.6585468000", \ - "0.2621152000, 0.2655511000, 0.2742631000, 0.2935395000, 0.3335723000, 0.4278102000, 0.6977170000", \ - "0.2969825000, 0.3004292000, 0.3091984000, 0.3286188000, 0.3686643000, 0.4631193000, 0.7328454000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.2071954000, 0.2117725000, 0.2237393000, 0.2527170000, 0.3277657000, 0.5502360000, 1.2431863000", \ - "0.2121058000, 0.2167007000, 0.2286616000, 0.2578730000, 0.3329941000, 0.5553165000, 1.2486631000", \ - "0.2248281000, 0.2294259000, 0.2413418000, 0.2705588000, 0.3457127000, 0.5680223000, 1.2616226000", \ - "0.2564942000, 0.2610872000, 0.2730822000, 0.3022027000, 0.3773448000, 0.5997841000, 1.2920109000", \ - "0.3281263000, 0.3326966000, 0.3446962000, 0.3738955000, 0.4489795000, 0.6715041000, 1.3650522000", \ - "0.4584035000, 0.4630132000, 0.4752512000, 0.5046477000, 0.5798538000, 0.8021922000, 1.4978307000", \ - "0.6680334000, 0.6729010000, 0.6854993000, 0.7152617000, 0.7908580000, 1.0128874000, 1.7057079000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.0227500000, 0.0248082000, 0.0302902000, 0.0437735000, 0.0799080000, 0.1879645000, 0.5446730000", \ - "0.0226964000, 0.0248792000, 0.0301707000, 0.0440669000, 0.0799268000, 0.1877311000, 0.5448509000", \ - "0.0227802000, 0.0249406000, 0.0304015000, 0.0441955000, 0.0799434000, 0.1878192000, 0.5474244000", \ - "0.0228119000, 0.0249689000, 0.0305511000, 0.0441906000, 0.0798973000, 0.1877699000, 0.5448685000", \ - "0.0228221000, 0.0249039000, 0.0304525000, 0.0439730000, 0.0800149000, 0.1877735000, 0.5438209000", \ - "0.0229147000, 0.0250126000, 0.0307691000, 0.0439690000, 0.0800412000, 0.1882724000, 0.5429543000", \ - "0.0237342000, 0.0255906000, 0.0310960000, 0.0449497000, 0.0805503000, 0.1882627000, 0.5459009000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.0269578000, 0.0307501000, 0.0413454000, 0.0720925000, 0.1704095000, 0.4900977000, 1.4963489000", \ - "0.0270504000, 0.0306544000, 0.0413375000, 0.0720693000, 0.1701250000, 0.4903706000, 1.5000575000", \ - "0.0270451000, 0.0306383000, 0.0413474000, 0.0720985000, 0.1701321000, 0.4903658000, 1.5000636000", \ - "0.0270770000, 0.0307595000, 0.0411919000, 0.0721366000, 0.1701710000, 0.4905040000, 1.4984753000", \ - "0.0269287000, 0.0306832000, 0.0413161000, 0.0721215000, 0.1699670000, 0.4900300000, 1.4977520000", \ - "0.0280898000, 0.0316972000, 0.0421293000, 0.0727140000, 0.1707749000, 0.4904914000, 1.5002463000", \ - "0.0299873000, 0.0338858000, 0.0440934000, 0.0742429000, 0.1716449000, 0.4896025000, 1.4963113000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.1316848000, 0.1353687000, 0.1446318000, 0.1646666000, 0.2053472000, 0.3002324000, 0.5702737000", \ - "0.1368973000, 0.1405009000, 0.1497083000, 0.1697061000, 0.2106561000, 0.3054147000, 0.5751543000", \ - "0.1498903000, 0.1535133000, 0.1626718000, 0.1825710000, 0.2232676000, 0.3188307000, 0.5887690000", \ - "0.1818070000, 0.1855153000, 0.1947889000, 0.2147852000, 0.2554761000, 0.3503776000, 0.6204108000", \ - "0.2575673000, 0.2611591000, 0.2702720000, 0.2898364000, 0.3307886000, 0.4257503000, 0.6958826000", \ - "0.4005018000, 0.4050661000, 0.4164728000, 0.4403961000, 0.4853533000, 0.5828694000, 0.8527630000", \ - "0.6309823000, 0.6368745000, 0.6516854000, 0.6834482000, 0.7415251000, 0.8488748000, 1.1218860000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.1126149000, 0.1171492000, 0.1290753000, 0.1580426000, 0.2332015000, 0.4560989000, 1.1510907000", \ - "0.1168597000, 0.1214189000, 0.1333474000, 0.1623051000, 0.2374840000, 0.4602490000, 1.1536586000", \ - "0.1251996000, 0.1297538000, 0.1416854000, 0.1708282000, 0.2457424000, 0.4675100000, 1.1614438000", \ - "0.1441378000, 0.1486807000, 0.1606255000, 0.1896591000, 0.2646975000, 0.4879173000, 1.1777442000", \ - "0.1813179000, 0.1860696000, 0.1986890000, 0.2284873000, 0.3039277000, 0.5265917000, 1.2197450000", \ - "0.2338768000, 0.2395614000, 0.2538344000, 0.2860876000, 0.3633202000, 0.5859109000, 1.2808907000", \ - "0.2821475000, 0.2895083000, 0.3078029000, 0.3462197000, 0.4272819000, 0.6498858000, 1.3406442000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.0254696000, 0.0275229000, 0.0330268000, 0.0468471000, 0.0821608000, 0.1889444000, 0.5464345000", \ - "0.0255051000, 0.0275906000, 0.0330790000, 0.0469069000, 0.0821081000, 0.1890600000, 0.5444505000", \ - "0.0255198000, 0.0277278000, 0.0329718000, 0.0464588000, 0.0821965000, 0.1890135000, 0.5472589000", \ - "0.0253296000, 0.0276053000, 0.0329490000, 0.0464879000, 0.0821208000, 0.1887900000, 0.5463523000", \ - "0.0256870000, 0.0278278000, 0.0332897000, 0.0469608000, 0.0823739000, 0.1893795000, 0.5469289000", \ - "0.0375423000, 0.0400833000, 0.0457497000, 0.0588215000, 0.0916776000, 0.1932875000, 0.5463462000", \ - "0.0576362000, 0.0606146000, 0.0683231000, 0.0845489000, 0.1166568000, 0.2100481000, 0.5485254000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015642300, 0.0048936200, 0.0153095000, 0.0478950000, 0.1498370000, 0.4687600000"); - values("0.0265600000, 0.0303376000, 0.0408401000, 0.0717029000, 0.1699974000, 0.4909175000, 1.5039482000", \ - "0.0266234000, 0.0303500000, 0.0408469000, 0.0718285000, 0.1702302000, 0.4907297000, 1.5013677000", \ - "0.0265218000, 0.0302323000, 0.0409758000, 0.0718230000, 0.1697708000, 0.4907164000, 1.5024723000", \ - "0.0265729000, 0.0300668000, 0.0406489000, 0.0717591000, 0.1701623000, 0.4908553000, 1.4974944000", \ - "0.0290170000, 0.0330289000, 0.0436105000, 0.0735908000, 0.1707801000, 0.4905532000, 1.5038558000", \ - "0.0362491000, 0.0401865000, 0.0508487000, 0.0799830000, 0.1744595000, 0.4893246000, 1.5023079000", \ - "0.0506595000, 0.0552971000, 0.0668132000, 0.0950531000, 0.1826581000, 0.4931102000, 1.4975469000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3_1") { - leakage_power () { - value : 0.0059791000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0059611000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0063057000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0059811000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0063200000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0059870000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0018855000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0063318000; - when : "A&B&!C"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__and3"; - cell_leakage_power : 0.0055939080; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025175000, 0.0025209000, 0.0025288000, 0.0025289000, 0.0025293000, 0.0025302000, 0.0025323000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001984000, -0.001985900, -0.001990200, -0.001986300, -0.001977400, -0.001956700, -0.001909200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014990000; - } - pin ("B") { - capacitance : 0.0015200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027027000, 0.0026959000, 0.0026801000, 0.0026894000, 0.0027108000, 0.0027601000, 0.0028737000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002389100, -0.002394000, -0.002405100, -0.002404100, -0.002401800, -0.002396300, -0.002383800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015510000; - } - pin ("C") { - capacitance : 0.0015560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023167000, 0.0023138000, 0.0023070000, 0.0023073000, 0.0023078000, 0.0023091000, 0.0023120000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002309800, -0.002308300, -0.002304900, -0.002304800, -0.002304700, -0.002304400, -0.002303600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016240000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0079591000, 0.0069016000, 0.0041333000, -0.004004800, -0.026733100, -0.086929200, -0.244208800", \ - "0.0078368000, 0.0068112000, 0.0040469000, -0.004115700, -0.026841800, -0.087010700, -0.244306300", \ - "0.0076379000, 0.0065846000, 0.0038218000, -0.004329800, -0.027052600, -0.087217600, -0.244511200", \ - "0.0074157000, 0.0063574000, 0.0035409000, -0.004617000, -0.027338700, -0.087477700, -0.244735100", \ - "0.0073011000, 0.0062042000, 0.0033256000, -0.004857300, -0.027477600, -0.087571500, -0.244813700", \ - "0.0082094000, 0.0069211000, 0.0035671000, -0.004851000, -0.027456900, -0.087556700, -0.244749200", \ - "0.0093231000, 0.0079316000, 0.0044698000, -0.004348100, -0.027283100, -0.087189900, -0.244238300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0099484000, 0.0113282000, 0.0148021000, 0.0237481000, 0.0465995000, 0.1061573000, 0.2630164000", \ - "0.0098782000, 0.0112581000, 0.0147689000, 0.0236898000, 0.0465504000, 0.1061796000, 0.2628614000", \ - "0.0097657000, 0.0111319000, 0.0146572000, 0.0235813000, 0.0464714000, 0.1061150000, 0.2632041000", \ - "0.0096793000, 0.0110306000, 0.0145517000, 0.0234296000, 0.0463570000, 0.1066080000, 0.2619525000", \ - "0.0096458000, 0.0109906000, 0.0144563000, 0.0232069000, 0.0460608000, 0.1064469000, 0.2631040000", \ - "0.0100722000, 0.0113709000, 0.0147444000, 0.0232932000, 0.0462732000, 0.1053867000, 0.2618003000", \ - "0.0108857000, 0.0121249000, 0.0154770000, 0.0242861000, 0.0468162000, 0.1067347000, 0.2608365000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0094584000, 0.0083958000, 0.0056013000, -0.002473500, -0.025136400, -0.085258300, -0.242463200", \ - "0.0093781000, 0.0082680000, 0.0055086000, -0.002551500, -0.025231700, -0.085338500, -0.242569200", \ - "0.0092404000, 0.0081684000, 0.0053775000, -0.002719900, -0.025365000, -0.085457500, -0.242682900", \ - "0.0090614000, 0.0079702000, 0.0051735000, -0.002930400, -0.025575300, -0.085658700, -0.242886100", \ - "0.0091200000, 0.0079814000, 0.0051021000, -0.003087600, -0.025745800, -0.085779000, -0.242962700", \ - "0.0094160000, 0.0081090000, 0.0046986000, -0.003320600, -0.025908300, -0.085893400, -0.243017500", \ - "0.0108710000, 0.0094817000, 0.0059996000, -0.002836800, -0.025788000, -0.085652800, -0.242712300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0099147000, 0.0112923000, 0.0147693000, 0.0237033000, 0.0465084000, 0.1059662000, 0.2627823000", \ - "0.0098827000, 0.0112446000, 0.0147924000, 0.0236625000, 0.0464521000, 0.1060418000, 0.2628214000", \ - "0.0098106000, 0.0111996000, 0.0147280000, 0.0236241000, 0.0464664000, 0.1060728000, 0.2617348000", \ - "0.0097168000, 0.0110962000, 0.0146156000, 0.0235191000, 0.0463516000, 0.1059634000, 0.2618352000", \ - "0.0096763000, 0.0110398000, 0.0144460000, 0.0232915000, 0.0462509000, 0.1064321000, 0.2607953000", \ - "0.0098856000, 0.0111867000, 0.0147461000, 0.0233593000, 0.0462490000, 0.1055074000, 0.2627723000", \ - "0.0103783000, 0.0116476000, 0.0149782000, 0.0238460000, 0.0467468000, 0.1066603000, 0.2606039000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0108581000, 0.0097785000, 0.0069203000, -0.001377500, -0.024246600, -0.084511000, -0.241815200", \ - "0.0107658000, 0.0096616000, 0.0068003000, -0.001476800, -0.024369600, -0.084591000, -0.241876200", \ - "0.0106820000, 0.0095281000, 0.0066593000, -0.001617300, -0.024447600, -0.084698300, -0.241944100", \ - "0.0104385000, 0.0093431000, 0.0064543000, -0.001788600, -0.024620100, -0.084839500, -0.242082500", \ - "0.0103492000, 0.0092190000, 0.0063389000, -0.001912700, -0.024766300, -0.084932700, -0.242169800", \ - "0.0107044000, 0.0093699000, 0.0063229000, -0.001775600, -0.024579300, -0.084749500, -0.242021500", \ - "0.0125955000, 0.0112092000, 0.0077233000, -0.001199300, -0.024327400, -0.084409500, -0.241647700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0103750000, 0.0117527000, 0.0152379000, 0.0241500000, 0.0468720000, 0.1062111000, 0.2629190000", \ - "0.0103467000, 0.0117156000, 0.0152513000, 0.0240599000, 0.0467889000, 0.1062247000, 0.2619417000", \ - "0.0102366000, 0.0116056000, 0.0150901000, 0.0239556000, 0.0467445000, 0.1061871000, 0.2616938000", \ - "0.0100592000, 0.0114309000, 0.0149266000, 0.0238081000, 0.0465812000, 0.1061006000, 0.2618848000", \ - "0.0099068000, 0.0112721000, 0.0147774000, 0.0236419000, 0.0464997000, 0.1062013000, 0.2632089000", \ - "0.0100767000, 0.0113866000, 0.0147742000, 0.0234515000, 0.0464552000, 0.1057970000, 0.2625461000", \ - "0.0103883000, 0.0116684000, 0.0150436000, 0.0240744000, 0.0469329000, 0.1067017000, 0.2618429000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.5053390000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1083644000, 0.1148132000, 0.1280945000, 0.1541908000, 0.2077484000, 0.3339220000, 0.6588955000", \ - "0.1134520000, 0.1199842000, 0.1333333000, 0.1591938000, 0.2128517000, 0.3387175000, 0.6644090000", \ - "0.1258838000, 0.1323797000, 0.1457519000, 0.1716193000, 0.2252295000, 0.3513714000, 0.6766833000", \ - "0.1567403000, 0.1631986000, 0.1764898000, 0.2025454000, 0.2562221000, 0.3822332000, 0.7065754000", \ - "0.2269361000, 0.2337714000, 0.2474835000, 0.2740940000, 0.3274571000, 0.4535345000, 0.7772504000", \ - "0.3466176000, 0.3552846000, 0.3723922000, 0.4030041000, 0.4612133000, 0.5892301000, 0.9146230000", \ - "0.5330224000, 0.5441280000, 0.5666359000, 0.6062530000, 0.6735289000, 0.8064658000, 1.1278064000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1005342000, 0.1092199000, 0.1278068000, 0.1683631000, 0.2642585000, 0.5090176000, 1.1495983000", \ - "0.1043445000, 0.1130145000, 0.1316905000, 0.1722275000, 0.2679977000, 0.5135202000, 1.1553096000", \ - "0.1140175000, 0.1226777000, 0.1414103000, 0.1819093000, 0.2778698000, 0.5235624000, 1.1631248000", \ - "0.1371514000, 0.1457491000, 0.1644002000, 0.2048432000, 0.3007429000, 0.5465196000, 1.1905975000", \ - "0.1779930000, 0.1870012000, 0.2064705000, 0.2475711000, 0.3437210000, 0.5906438000, 1.2302944000", \ - "0.2291398000, 0.2398036000, 0.2612877000, 0.3040434000, 0.4008314000, 0.6480485000, 1.2876443000", \ - "0.2748843000, 0.2891072000, 0.3173745000, 0.3657223000, 0.4628249000, 0.7102788000, 1.3492407000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0225883000, 0.0270847000, 0.0374123000, 0.0607917000, 0.1192907000, 0.2786106000, 0.7103301000", \ - "0.0224923000, 0.0270035000, 0.0371381000, 0.0608677000, 0.1191496000, 0.2795097000, 0.7058879000", \ - "0.0228574000, 0.0274384000, 0.0372516000, 0.0606853000, 0.1191281000, 0.2788043000, 0.7130345000", \ - "0.0227264000, 0.0270741000, 0.0371965000, 0.0608399000, 0.1191177000, 0.2799263000, 0.7095730000", \ - "0.0255522000, 0.0297329000, 0.0395250000, 0.0620951000, 0.1204486000, 0.2813839000, 0.7168445000", \ - "0.0360710000, 0.0415212000, 0.0512884000, 0.0740600000, 0.1283752000, 0.2822260000, 0.7128049000", \ - "0.0533091000, 0.0594661000, 0.0721495000, 0.0953411000, 0.1468775000, 0.2909538000, 0.7085594000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0298816000, 0.0375939000, 0.0564026000, 0.1042366000, 0.2338930000, 0.5830416000, 1.5015632000", \ - "0.0298966000, 0.0375792000, 0.0563789000, 0.1040544000, 0.2345145000, 0.5838894000, 1.4969995000", \ - "0.0300407000, 0.0376644000, 0.0563730000, 0.1042608000, 0.2344894000, 0.5837034000, 1.5010662000", \ - "0.0300898000, 0.0377852000, 0.0564884000, 0.1042708000, 0.2344968000, 0.5857460000, 1.5053251000", \ - "0.0334687000, 0.0410532000, 0.0594284000, 0.1067380000, 0.2352649000, 0.5844480000, 1.5036578000", \ - "0.0426199000, 0.0498862000, 0.0671307000, 0.1113983000, 0.2382994000, 0.5844812000, 1.4998291000", \ - "0.0589443000, 0.0676463000, 0.0861363000, 0.1245421000, 0.2417835000, 0.5873227000, 1.4970163000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1270775000, 0.1338058000, 0.1477053000, 0.1744611000, 0.2288944000, 0.3552230000, 0.6802516000", \ - "0.1320901000, 0.1389335000, 0.1527736000, 0.1794640000, 0.2339755000, 0.3603412000, 0.6853510000", \ - "0.1449623000, 0.1517265000, 0.1655502000, 0.1922083000, 0.2467649000, 0.3733010000, 0.6984414000", \ - "0.1764082000, 0.1831344000, 0.1968537000, 0.2236559000, 0.2782032000, 0.4047569000, 0.7296285000", \ - "0.2515829000, 0.2583438000, 0.2722590000, 0.2990722000, 0.3537299000, 0.4804148000, 0.8049701000", \ - "0.3912279000, 0.3996813000, 0.4165057000, 0.4470040000, 0.5049187000, 0.6325626000, 0.9566712000", \ - "0.6148241000, 0.6259261000, 0.6479861000, 0.6867250000, 0.7528517000, 0.8852169000, 1.2104735000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1074713000, 0.1161445000, 0.1347404000, 0.1752171000, 0.2708483000, 0.5153075000, 1.1560978000", \ - "0.1117715000, 0.1203267000, 0.1390910000, 0.1794665000, 0.2751337000, 0.5201720000, 1.1592958000", \ - "0.1207271000, 0.1293582000, 0.1480492000, 0.1885163000, 0.2838871000, 0.5298097000, 1.1695407000", \ - "0.1408847000, 0.1495598000, 0.1682326000, 0.2086642000, 0.3043304000, 0.5494624000, 1.1877256000", \ - "0.1779791000, 0.1871981000, 0.2066551000, 0.2480852000, 0.3440500000, 0.5902206000, 1.2389274000", \ - "0.2275874000, 0.2382184000, 0.2600906000, 0.3032412000, 0.4005345000, 0.6466199000, 1.2880937000", \ - "0.2692713000, 0.2833388000, 0.3105594000, 0.3596478000, 0.4593640000, 0.7062497000, 1.3448589000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0244598000, 0.0291280000, 0.0394184000, 0.0626104000, 0.1208858000, 0.2805345000, 0.7145224000", \ - "0.0246179000, 0.0289019000, 0.0394258000, 0.0626817000, 0.1208519000, 0.2805612000, 0.7157776000", \ - "0.0245448000, 0.0289151000, 0.0392291000, 0.0627991000, 0.1207507000, 0.2804360000, 0.7144439000", \ - "0.0244996000, 0.0289044000, 0.0392214000, 0.0627709000, 0.1207766000, 0.2804371000, 0.7159232000", \ - "0.0256119000, 0.0298496000, 0.0400208000, 0.0631585000, 0.1207914000, 0.2798825000, 0.7110564000", \ - "0.0353272000, 0.0402651000, 0.0502193000, 0.0726139000, 0.1265192000, 0.2826727000, 0.7093746000", \ - "0.0521480000, 0.0585210000, 0.0708599000, 0.0932432000, 0.1450120000, 0.2898358000, 0.7098185000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0298742000, 0.0375765000, 0.0564143000, 0.1042244000, 0.2338886000, 0.5832124000, 1.5019617000", \ - "0.0299534000, 0.0376812000, 0.0563318000, 0.1043235000, 0.2344770000, 0.5840186000, 1.5021535000", \ - "0.0300071000, 0.0377620000, 0.0564175000, 0.1040863000, 0.2344293000, 0.5845848000, 1.5020670000", \ - "0.0300593000, 0.0377260000, 0.0563604000, 0.1041284000, 0.2346034000, 0.5847700000, 1.5033202000", \ - "0.0329425000, 0.0408015000, 0.0593877000, 0.1062959000, 0.2350080000, 0.5846152000, 1.4984132000", \ - "0.0407442000, 0.0480853000, 0.0659895000, 0.1105592000, 0.2375985000, 0.5840515000, 1.5017619000", \ - "0.0555829000, 0.0643179000, 0.0828101000, 0.1237605000, 0.2419391000, 0.5861184000, 1.4958595000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1420706000, 0.1489870000, 0.1627567000, 0.1896398000, 0.2442742000, 0.3709743000, 0.6959196000", \ - "0.1469684000, 0.1538224000, 0.1677921000, 0.1944859000, 0.2492155000, 0.3758074000, 0.7013592000", \ - "0.1599558000, 0.1668164000, 0.1807780000, 0.2075157000, 0.2622455000, 0.3890796000, 0.7136429000", \ - "0.1915097000, 0.1983875000, 0.2123335000, 0.2392393000, 0.2941269000, 0.4208366000, 0.7453322000", \ - "0.2669717000, 0.2737909000, 0.2877943000, 0.3147329000, 0.3696976000, 0.4965270000, 0.8211804000", \ - "0.4161713000, 0.4245002000, 0.4409330000, 0.4708274000, 0.5282617000, 0.6562484000, 0.9814639000", \ - "0.6559058000, 0.6669608000, 0.6883550000, 0.7267679000, 0.7917500000, 0.9235570000, 1.2486647000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1141056000, 0.1227794000, 0.1414072000, 0.1818464000, 0.2771886000, 0.5211537000, 1.1615957000", \ - "0.1183111000, 0.1268831000, 0.1456152000, 0.1859943000, 0.2811724000, 0.5276213000, 1.1665053000", \ - "0.1262212000, 0.1347964000, 0.1534357000, 0.1938794000, 0.2889260000, 0.5343123000, 1.1725921000", \ - "0.1424150000, 0.1510634000, 0.1696372000, 0.2099439000, 0.3053995000, 0.5501259000, 1.1937563000", \ - "0.1717762000, 0.1809830000, 0.2005176000, 0.2419307000, 0.3380594000, 0.5837316000, 1.2247401000", \ - "0.2146484000, 0.2250164000, 0.2459455000, 0.2896639000, 0.3872392000, 0.6329077000, 1.2796686000", \ - "0.2498559000, 0.2633566000, 0.2896605000, 0.3382184000, 0.4382535000, 0.6845978000, 1.3237218000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0258123000, 0.0306047000, 0.0411487000, 0.0647544000, 0.1225536000, 0.2815175000, 0.7157800000", \ - "0.0259468000, 0.0305717000, 0.0407237000, 0.0646678000, 0.1225208000, 0.2813747000, 0.7134217000", \ - "0.0261344000, 0.0305525000, 0.0408801000, 0.0646183000, 0.1222899000, 0.2810386000, 0.7141479000", \ - "0.0258151000, 0.0304102000, 0.0409329000, 0.0646570000, 0.1221398000, 0.2813389000, 0.7167629000", \ - "0.0263988000, 0.0309690000, 0.0411910000, 0.0644727000, 0.1223632000, 0.2812076000, 0.7148259000", \ - "0.0352361000, 0.0400821000, 0.0500595000, 0.0720340000, 0.1270989000, 0.2834043000, 0.7134149000", \ - "0.0519025000, 0.0577870000, 0.0697241000, 0.0917938000, 0.1437275000, 0.2903285000, 0.7117657000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0298819000, 0.0375525000, 0.0564219000, 0.1041640000, 0.2340061000, 0.5833353000, 1.5018957000", \ - "0.0299849000, 0.0376691000, 0.0563494000, 0.1043317000, 0.2346213000, 0.5849528000, 1.5025610000", \ - "0.0299770000, 0.0376734000, 0.0564387000, 0.1043685000, 0.2343580000, 0.5838433000, 1.5010327000", \ - "0.0300264000, 0.0377919000, 0.0564081000, 0.1043590000, 0.2345433000, 0.5847648000, 1.4987723000", \ - "0.0327792000, 0.0405719000, 0.0590167000, 0.1061121000, 0.2351178000, 0.5836726000, 1.5053386000", \ - "0.0384447000, 0.0461594000, 0.0652089000, 0.1105152000, 0.2374954000, 0.5828670000, 1.5021128000", \ - "0.0521083000, 0.0611445000, 0.0794257000, 0.1226451000, 0.2419497000, 0.5860785000, 1.4927156000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3_2") { - leakage_power () { - value : 0.0054309000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0054126000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0057657000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0054343000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0057854000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0054402000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0023742000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0058099000; - when : "A&B&!C"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__and3"; - cell_leakage_power : 0.0051816490; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024964000, 0.0024986000, 0.0025035000, 0.0025033000, 0.0025028000, 0.0025015000, 0.0024987000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001971900, -0.001972600, -0.001974200, -0.001970200, -0.001961100, -0.001940000, -0.001891300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014470000; - } - pin ("B") { - capacitance : 0.0015050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027080000, 0.0027010000, 0.0026848000, 0.0026943000, 0.0027164000, 0.0027672000, 0.0028843000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002436200, -0.002431700, -0.002421200, -0.002420500, -0.002419100, -0.002415700, -0.002408000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015350000; - } - pin ("C") { - capacitance : 0.0015240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023208000, 0.0023147000, 0.0023008000, 0.0023010000, 0.0023017000, 0.0023031000, 0.0023063000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002312900, -0.002307600, -0.002295500, -0.002296100, -0.002297500, -0.002300700, -0.002308000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015930000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0113670000, 0.0098307000, 0.0058694000, -0.005690100, -0.043022600, -0.155431200, -0.484902400", \ - "0.0112677000, 0.0097384000, 0.0057982000, -0.005876500, -0.043136200, -0.155442000, -0.484956200", \ - "0.0111121000, 0.0096183000, 0.0055932000, -0.005987900, -0.043316900, -0.155571900, -0.485053300", \ - "0.0108376000, 0.0093357000, 0.0053760000, -0.006285400, -0.043530700, -0.155873200, -0.485298500", \ - "0.0106487000, 0.0091323000, 0.0053901000, -0.006658800, -0.043836700, -0.156171400, -0.485535800", \ - "0.0109253000, 0.0092464000, 0.0049139000, -0.006885900, -0.043820500, -0.156151200, -0.485483500", \ - "0.0151234000, 0.0132615000, 0.0083233000, -0.005222300, -0.043769800, -0.156037100, -0.485192000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0149010000, 0.0164931000, 0.0212902000, 0.0348269000, 0.0733988000, 0.1851806000, 0.5112451000", \ - "0.0148611000, 0.0164987000, 0.0212078000, 0.0349093000, 0.0733477000, 0.1851470000, 0.5112490000", \ - "0.0147910000, 0.0164146000, 0.0211326000, 0.0347311000, 0.0733895000, 0.1850727000, 0.5110059000", \ - "0.0146524000, 0.0162983000, 0.0210157000, 0.0346303000, 0.0731856000, 0.1849178000, 0.5132251000", \ - "0.0147157000, 0.0163146000, 0.0209726000, 0.0345520000, 0.0727777000, 0.1848094000, 0.5114236000", \ - "0.0155191000, 0.0170101000, 0.0214104000, 0.0344507000, 0.0727533000, 0.1839457000, 0.5113532000", \ - "0.0167644000, 0.0181654000, 0.0227371000, 0.0357455000, 0.0739887000, 0.1849603000, 0.5110434000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0127515000, 0.0112228000, 0.0072992000, -0.004406300, -0.041462600, -0.153809300, -0.483184500", \ - "0.0126853000, 0.0111651000, 0.0071912000, -0.004388100, -0.041621400, -0.153833800, -0.483248100", \ - "0.0126080000, 0.0110888000, 0.0070823000, -0.004516500, -0.041627100, -0.153926400, -0.483325600", \ - "0.0124628000, 0.0109708000, 0.0069597000, -0.004754600, -0.041958600, -0.154118200, -0.483501600", \ - "0.0123670000, 0.0108655000, 0.0067974000, -0.004962900, -0.042191400, -0.154363500, -0.483617400", \ - "0.0124908000, 0.0113761000, 0.0070702000, -0.005169700, -0.042208800, -0.154586300, -0.483794200", \ - "0.0166289000, 0.0147915000, 0.0098640000, -0.003711300, -0.042243500, -0.154498200, -0.483606000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0149152000, 0.0164969000, 0.0212875000, 0.0348915000, 0.0734643000, 0.1850817000, 0.5133565000", \ - "0.0148643000, 0.0164716000, 0.0212049000, 0.0349071000, 0.0733007000, 0.1849877000, 0.5112015000", \ - "0.0148710000, 0.0164785000, 0.0211199000, 0.0347065000, 0.0732390000, 0.1848215000, 0.5107494000", \ - "0.0146895000, 0.0163314000, 0.0210520000, 0.0347337000, 0.0731842000, 0.1848600000, 0.5137041000", \ - "0.0147605000, 0.0163470000, 0.0209590000, 0.0345248000, 0.0729973000, 0.1848509000, 0.5113559000", \ - "0.0155668000, 0.0170876000, 0.0215453000, 0.0345905000, 0.0728299000, 0.1844694000, 0.5110752000", \ - "0.0163752000, 0.0178176000, 0.0221598000, 0.0353158000, 0.0731055000, 0.1849965000, 0.5113902000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0143450000, 0.0128364000, 0.0087855000, -0.002885100, -0.040253400, -0.152663200, -0.482120500", \ - "0.0142581000, 0.0127197000, 0.0086622000, -0.002944100, -0.040333800, -0.152749000, -0.482186400", \ - "0.0143128000, 0.0127392000, 0.0086889000, -0.003087000, -0.040467600, -0.152841800, -0.482263300", \ - "0.0140142000, 0.0124840000, 0.0084606000, -0.003279500, -0.040639800, -0.153003100, -0.482403200", \ - "0.0138679000, 0.0123326000, 0.0082510000, -0.003528500, -0.040881700, -0.153182900, -0.482520000", \ - "0.0142955000, 0.0126739000, 0.0084825000, -0.003547300, -0.040833200, -0.153146900, -0.482470200", \ - "0.0185543000, 0.0167058000, 0.0117548000, -0.002003400, -0.040681000, -0.152959300, -0.482216700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0153735000, 0.0169878000, 0.0217298000, 0.0353307000, 0.0737002000, 0.1852839000, 0.5135755000", \ - "0.0153073000, 0.0169314000, 0.0216335000, 0.0353280000, 0.0737064000, 0.1852669000, 0.5111155000", \ - "0.0151969000, 0.0167788000, 0.0215844000, 0.0351810000, 0.0736678000, 0.1852486000, 0.5108290000", \ - "0.0150558000, 0.0166369000, 0.0214329000, 0.0350999000, 0.0735843000, 0.1850486000, 0.5117422000", \ - "0.0150349000, 0.0165643000, 0.0212575000, 0.0348483000, 0.0733646000, 0.1849289000, 0.5117822000", \ - "0.0155762000, 0.0171211000, 0.0218441000, 0.0348037000, 0.0731239000, 0.1847182000, 0.5108398000", \ - "0.0162270000, 0.0176723000, 0.0220938000, 0.0354218000, 0.0736504000, 0.1855838000, 0.5093804000"); - } - } - max_capacitance : 0.3094580000; - max_transition : 1.5082440000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1399989000, 0.1459394000, 0.1592845000, 0.1858997000, 0.2386768000, 0.3599186000, 0.6917405000", \ - "0.1453554000, 0.1512893000, 0.1646392000, 0.1914123000, 0.2441291000, 0.3653078000, 0.6973701000", \ - "0.1579656000, 0.1638605000, 0.1771013000, 0.2033583000, 0.2564839000, 0.3776252000, 0.7096329000", \ - "0.1883983000, 0.1943758000, 0.2076887000, 0.2346216000, 0.2872279000, 0.4085289000, 0.7404167000", \ - "0.2623253000, 0.2682373000, 0.2814251000, 0.3073434000, 0.3608008000, 0.4821112000, 0.8138012000", \ - "0.4040357000, 0.4112656000, 0.4272800000, 0.4581023000, 0.5149960000, 0.6382777000, 0.9701165000", \ - "0.6274317000, 0.6366185000, 0.6575767000, 0.6974303000, 0.7674713000, 0.9003036000, 1.2335672000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1259505000, 0.1335603000, 0.1509985000, 0.1884266000, 0.2748027000, 0.5087379000, 1.1858320000", \ - "0.1299265000, 0.1375503000, 0.1549376000, 0.1924924000, 0.2788331000, 0.5127960000, 1.1916973000", \ - "0.1395581000, 0.1469926000, 0.1645719000, 0.2019839000, 0.2885404000, 0.5213279000, 1.2030731000", \ - "0.1630475000, 0.1706844000, 0.1881331000, 0.2255741000, 0.3120597000, 0.5448912000, 1.2253862000", \ - "0.2125856000, 0.2203885000, 0.2382337000, 0.2762435000, 0.3633522000, 0.5963031000, 1.2753890000", \ - "0.2831603000, 0.2927376000, 0.3128627000, 0.3537016000, 0.4426685000, 0.6768831000, 1.3525360000", \ - "0.3581449000, 0.3701555000, 0.3972373000, 0.4464253000, 0.5399474000, 0.7736822000, 1.4507147000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0265291000, 0.0303568000, 0.0390277000, 0.0584549000, 0.1077463000, 0.2497730000, 0.6873090000", \ - "0.0267609000, 0.0305846000, 0.0390500000, 0.0583902000, 0.1076434000, 0.2494280000, 0.6915342000", \ - "0.0267963000, 0.0302480000, 0.0390179000, 0.0585444000, 0.1076940000, 0.2494595000, 0.6917220000", \ - "0.0268205000, 0.0304530000, 0.0390779000, 0.0586449000, 0.1077141000, 0.2495788000, 0.6881166000", \ - "0.0269233000, 0.0306373000, 0.0400845000, 0.0586365000, 0.1078360000, 0.2499117000, 0.6922837000", \ - "0.0382610000, 0.0427030000, 0.0514647000, 0.0701119000, 0.1157278000, 0.2522739000, 0.6921931000", \ - "0.0584036000, 0.0634952000, 0.0743485000, 0.0968798000, 0.1419324000, 0.2688899000, 0.6905597000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0302485000, 0.0360995000, 0.0504289000, 0.0876557000, 0.1949329000, 0.5230008000, 1.5016748000", \ - "0.0303490000, 0.0362922000, 0.0505596000, 0.0875233000, 0.1950276000, 0.5234385000, 1.5010857000", \ - "0.0303508000, 0.0362483000, 0.0506905000, 0.0874479000, 0.1947617000, 0.5240900000, 1.5006775000", \ - "0.0303174000, 0.0360984000, 0.0505898000, 0.0874586000, 0.1947524000, 0.5241778000, 1.5022725000", \ - "0.0329376000, 0.0387542000, 0.0526967000, 0.0890080000, 0.1954920000, 0.5241091000, 1.5040105000", \ - "0.0428065000, 0.0486370000, 0.0624773000, 0.0967304000, 0.1998904000, 0.5253650000, 1.5006328000", \ - "0.0595177000, 0.0670999000, 0.0836359000, 0.1159541000, 0.2097742000, 0.5281184000, 1.4958409000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1592076000, 0.1654224000, 0.1794002000, 0.2069911000, 0.2608231000, 0.3831253000, 0.7157246000", \ - "0.1645404000, 0.1707685000, 0.1846597000, 0.2120397000, 0.2661845000, 0.3883727000, 0.7204790000", \ - "0.1778060000, 0.1840253000, 0.1979477000, 0.2255782000, 0.2794452000, 0.4017840000, 0.7338439000", \ - "0.2085926000, 0.2148996000, 0.2288161000, 0.2563072000, 0.3104443000, 0.4325920000, 0.7649953000", \ - "0.2845917000, 0.2907938000, 0.3047509000, 0.3322946000, 0.3853597000, 0.5088264000, 0.8415000000", \ - "0.4412825000, 0.4486305000, 0.4645497000, 0.4951509000, 0.5516135000, 0.6757113000, 1.0073010000", \ - "0.6963421000, 0.7056414000, 0.7267683000, 0.7665744000, 0.8358058000, 0.9679820000, 1.3018259000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1327410000, 0.1403460000, 0.1577845000, 0.1952443000, 0.2816418000, 0.5144200000, 1.1905130000", \ - "0.1370200000, 0.1446368000, 0.1620169000, 0.1995600000, 0.2857903000, 0.5196153000, 1.1970782000", \ - "0.1461622000, 0.1538707000, 0.1711594000, 0.2085883000, 0.2950824000, 0.5281915000, 1.2079568000", \ - "0.1667469000, 0.1743742000, 0.1919050000, 0.2292943000, 0.3155991000, 0.5493018000, 1.2251010000", \ - "0.2095504000, 0.2174973000, 0.2352329000, 0.2733168000, 0.3599495000, 0.5938715000, 1.2686067000", \ - "0.2744779000, 0.2835527000, 0.3036578000, 0.3443137000, 0.4329067000, 0.6668788000, 1.3452337000", \ - "0.3444786000, 0.3559809000, 0.3814395000, 0.4296417000, 0.5223195000, 0.7570643000, 1.4323703000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0288481000, 0.0328117000, 0.0415070000, 0.0613028000, 0.1102810000, 0.2511482000, 0.6897024000", \ - "0.0287479000, 0.0325644000, 0.0412925000, 0.0616595000, 0.1101600000, 0.2512311000, 0.6890011000", \ - "0.0288419000, 0.0327267000, 0.0417215000, 0.0615183000, 0.1101227000, 0.2511563000, 0.6886839000", \ - "0.0288600000, 0.0329163000, 0.0413343000, 0.0612681000, 0.1099595000, 0.2512586000, 0.6881423000", \ - "0.0287419000, 0.0329331000, 0.0417290000, 0.0609987000, 0.1101064000, 0.2515901000, 0.6917714000", \ - "0.0382113000, 0.0423978000, 0.0509191000, 0.0694767000, 0.1153525000, 0.2523403000, 0.6930814000", \ - "0.0584190000, 0.0628527000, 0.0740413000, 0.0954377000, 0.1405604000, 0.2670156000, 0.6917525000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0304759000, 0.0363498000, 0.0506607000, 0.0873404000, 0.1947822000, 0.5235597000, 1.5013137000", \ - "0.0303451000, 0.0360825000, 0.0506666000, 0.0874935000, 0.1950464000, 0.5236422000, 1.5022282000", \ - "0.0303908000, 0.0362024000, 0.0507441000, 0.0874247000, 0.1947691000, 0.5235630000, 1.5014469000", \ - "0.0303355000, 0.0361919000, 0.0506240000, 0.0875218000, 0.1944728000, 0.5233554000, 1.5082439000", \ - "0.0324454000, 0.0379470000, 0.0525540000, 0.0889674000, 0.1954876000, 0.5233984000, 1.5025282000", \ - "0.0394648000, 0.0456010000, 0.0599725000, 0.0953093000, 0.1989691000, 0.5243340000, 1.5029468000", \ - "0.0540160000, 0.0614480000, 0.0773506000, 0.1111278000, 0.2096718000, 0.5276759000, 1.4981882000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1734749000, 0.1797965000, 0.1938684000, 0.2217501000, 0.2758014000, 0.3982955000, 0.7307365000", \ - "0.1785066000, 0.1848182000, 0.1989135000, 0.2267589000, 0.2808895000, 0.4034570000, 0.7359974000", \ - "0.1916303000, 0.1979075000, 0.2118272000, 0.2395256000, 0.2934998000, 0.4163239000, 0.7487313000", \ - "0.2228920000, 0.2292403000, 0.2432781000, 0.2708724000, 0.3261743000, 0.4487862000, 0.7813126000", \ - "0.2993266000, 0.3056702000, 0.3197485000, 0.3475683000, 0.4020419000, 0.5248382000, 0.8578423000", \ - "0.4629779000, 0.4700530000, 0.4858323000, 0.5157501000, 0.5720760000, 0.6955262000, 1.0282810000", \ - "0.7352111000, 0.7446247000, 0.7652103000, 0.8039769000, 0.8721756000, 1.0037676000, 1.3373124000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1395737000, 0.1472937000, 0.1646421000, 0.2021017000, 0.2884234000, 0.5210623000, 1.1958335000", \ - "0.1438072000, 0.1514123000, 0.1687612000, 0.2063167000, 0.2925640000, 0.5260339000, 1.2047127000", \ - "0.1518021000, 0.1594153000, 0.1768501000, 0.2142987000, 0.3006171000, 0.5331061000, 1.2096648000", \ - "0.1682642000, 0.1758511000, 0.1933469000, 0.2308384000, 0.3171651000, 0.5498697000, 1.2280751000", \ - "0.2014057000, 0.2091892000, 0.2272189000, 0.2651958000, 0.3520331000, 0.5850848000, 1.2635218000", \ - "0.2534195000, 0.2622397000, 0.2821322000, 0.3226227000, 0.4117917000, 0.6456664000, 1.3281259000", \ - "0.3117052000, 0.3226391000, 0.3467518000, 0.3935917000, 0.4870839000, 0.7224860000, 1.3976240000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0296558000, 0.0337071000, 0.0423612000, 0.0620490000, 0.1110219000, 0.2520029000, 0.6890891000", \ - "0.0298198000, 0.0338252000, 0.0423241000, 0.0620973000, 0.1111115000, 0.2517282000, 0.6882104000", \ - "0.0297700000, 0.0336009000, 0.0429845000, 0.0622661000, 0.1112584000, 0.2519225000, 0.6932047000", \ - "0.0297634000, 0.0336445000, 0.0423948000, 0.0627304000, 0.1109826000, 0.2518975000, 0.6885969000", \ - "0.0298782000, 0.0337170000, 0.0425690000, 0.0622840000, 0.1108621000, 0.2515875000, 0.6913329000", \ - "0.0375049000, 0.0414895000, 0.0500022000, 0.0685456000, 0.1147934000, 0.2532191000, 0.6888501000", \ - "0.0572465000, 0.0627932000, 0.0739827000, 0.0934332000, 0.1385368000, 0.2661566000, 0.6922610000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0304110000, 0.0362282000, 0.0507438000, 0.0874605000, 0.1947312000, 0.5229014000, 1.5049068000", \ - "0.0303588000, 0.0364023000, 0.0505396000, 0.0876350000, 0.1950221000, 0.5238688000, 1.5006412000", \ - "0.0303373000, 0.0363727000, 0.0504416000, 0.0875629000, 0.1948546000, 0.5238265000, 1.4981454000", \ - "0.0303339000, 0.0363699000, 0.0505414000, 0.0874791000, 0.1947236000, 0.5235546000, 1.5047594000", \ - "0.0321930000, 0.0380836000, 0.0522649000, 0.0888150000, 0.1951621000, 0.5230542000, 1.5058301000", \ - "0.0371003000, 0.0433125000, 0.0586372000, 0.0948315000, 0.1991194000, 0.5238780000, 1.5021852000", \ - "0.0499702000, 0.0572094000, 0.0727763000, 0.1081606000, 0.2077082000, 0.5270422000, 1.4977233000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3_4") { - leakage_power () { - value : 0.0042559000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0039331000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0042789000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0039392000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0049811000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0042932000; - when : "A&B&!C"; - } - leakage_power () { - value : 0.0039306000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0039122000; - when : "!A&!B&!C"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__and3"; - cell_leakage_power : 0.0041905290; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0024040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051349000, 0.0051372000, 0.0051424000, 0.0051409000, 0.0051374000, 0.0051294000, 0.0051108000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004027000, -0.004030400, -0.004038100, -0.004030700, -0.004013800, -0.003974700, -0.003884700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025400000; - } - pin ("B") { - capacitance : 0.0023830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044755000, 0.0044717000, 0.0044629000, 0.0044767000, 0.0045086000, 0.0045820000, 0.0047513000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004064600, -0.004062700, -0.004058500, -0.004058100, -0.004057300, -0.004055300, -0.004050800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("C") { - capacitance : 0.0024070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043091000, 0.0043098000, 0.0043114000, 0.0043091000, 0.0043037000, 0.0042914000, 0.0042629000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004312700, -0.004311300, -0.004308100, -0.004307700, -0.004306700, -0.004304300, -0.004298800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025400000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0225850000, 0.0209644000, 0.0157295000, 0.0002470000, -0.054956800, -0.239495700, -0.832371700", \ - "0.0224587000, 0.0208180000, 0.0156780000, 0.0001067000, -0.055049400, -0.239614100, -0.832349300", \ - "0.0221840000, 0.0205991000, 0.0154280000, -0.000269300, -0.055285100, -0.239799900, -0.832689200", \ - "0.0219560000, 0.0202503000, 0.0150878000, -0.000717900, -0.055750300, -0.240207900, -0.832950400", \ - "0.0221768000, 0.0203665000, 0.0147660000, -0.000815000, -0.056429200, -0.240735600, -0.833324300", \ - "0.0235311000, 0.0216224000, 0.0157538000, -0.002138300, -0.056142400, -0.240433700, -0.833014400", \ - "0.0292414000, 0.0269504000, 0.0205621000, 0.0019517000, -0.055691000, -0.240160400, -0.832156100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0281984000, 0.0300139000, 0.0359616000, 0.0548615000, 0.1128240000, 0.2968729000, 0.8879999000", \ - "0.0281036000, 0.0299738000, 0.0358394000, 0.0547609000, 0.1130736000, 0.2969332000, 0.8887007000", \ - "0.0278949000, 0.0296990000, 0.0356326000, 0.0546573000, 0.1129668000, 0.2968335000, 0.8844410000", \ - "0.0276645000, 0.0294341000, 0.0353838000, 0.0542092000, 0.1125419000, 0.2964591000, 0.8878142000", \ - "0.0277961000, 0.0296036000, 0.0353953000, 0.0537361000, 0.1119904000, 0.2961638000, 0.8847197000", \ - "0.0294258000, 0.0311432000, 0.0367784000, 0.0546556000, 0.1118405000, 0.2957279000, 0.8843381000", \ - "0.0319205000, 0.0335141000, 0.0389073000, 0.0565368000, 0.1135980000, 0.2974668000, 0.8804212000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0251215000, 0.0234258000, 0.0181728000, 0.0025213000, -0.052433000, -0.236570400, -0.829309200", \ - "0.0250331000, 0.0232756000, 0.0181793000, 0.0023555000, -0.052393700, -0.236691800, -0.829380900", \ - "0.0248987000, 0.0231762000, 0.0180037000, 0.0023481000, -0.052586000, -0.236858800, -0.829613200", \ - "0.0246641000, 0.0229106000, 0.0176660000, 0.0019555000, -0.053027500, -0.237219300, -0.829864700", \ - "0.0246439000, 0.0227879000, 0.0176201000, 0.0014800000, -0.053335200, -0.237560500, -0.830072800", \ - "0.0248143000, 0.0227682000, 0.0173852000, 0.0011839000, -0.053961200, -0.237874900, -0.830159700", \ - "0.0316497000, 0.0295213000, 0.0234275000, 0.0047631000, -0.053076000, -0.237586700, -0.829660600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0286070000, 0.0304200000, 0.0363546000, 0.0552118000, 0.1134147000, 0.2970044000, 0.8840938000", \ - "0.0286020000, 0.0304069000, 0.0363382000, 0.0550809000, 0.1131036000, 0.2968835000, 0.8842847000", \ - "0.0284564000, 0.0302925000, 0.0362143000, 0.0549756000, 0.1133032000, 0.2970049000, 0.8842048000", \ - "0.0281202000, 0.0298940000, 0.0358436000, 0.0546731000, 0.1130499000, 0.2968477000, 0.8841786000", \ - "0.0281771000, 0.0299658000, 0.0356696000, 0.0544305000, 0.1125473000, 0.2965996000, 0.8838977000", \ - "0.0294072000, 0.0311341000, 0.0367020000, 0.0543173000, 0.1124445000, 0.2961559000, 0.8831550000", \ - "0.0308210000, 0.0324539000, 0.0379013000, 0.0557420000, 0.1143143000, 0.2971202000, 0.8832769000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0273607000, 0.0256983000, 0.0203092000, 0.0044320000, -0.050584100, -0.234928700, -0.827755300", \ - "0.0274142000, 0.0257122000, 0.0202359000, 0.0043609000, -0.050695600, -0.235065700, -0.827905800", \ - "0.0271344000, 0.0253465000, 0.0201096000, 0.0041092000, -0.050967200, -0.235246100, -0.827996100", \ - "0.0269880000, 0.0252881000, 0.0199173000, 0.0038731000, -0.051236600, -0.235426900, -0.828118600", \ - "0.0270037000, 0.0251614000, 0.0197754000, 0.0041117000, -0.051504200, -0.235786600, -0.828392200", \ - "0.0270112000, 0.0255823000, 0.0200467000, 0.0037390000, -0.051313900, -0.235686600, -0.828265600", \ - "0.0354998000, 0.0326390000, 0.0263836000, 0.0076294000, -0.049680800, -0.234665900, -0.827185200"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0288811000, 0.0306947000, 0.0366415000, 0.0555533000, 0.1134194000, 0.2970561000, 0.8875795000", \ - "0.0287654000, 0.0306023000, 0.0364582000, 0.0554255000, 0.1136495000, 0.2972510000, 0.8833801000", \ - "0.0286067000, 0.0304335000, 0.0363776000, 0.0552031000, 0.1135074000, 0.2971033000, 0.8840194000", \ - "0.0283508000, 0.0301255000, 0.0360764000, 0.0548893000, 0.1132393000, 0.2968654000, 0.8794756000", \ - "0.0282780000, 0.0301043000, 0.0359767000, 0.0546081000, 0.1127473000, 0.2967030000, 0.8837102000", \ - "0.0293827000, 0.0313559000, 0.0370289000, 0.0548746000, 0.1127775000, 0.2961417000, 0.8875729000", \ - "0.0304733000, 0.0321818000, 0.0376970000, 0.0557506000, 0.1142832000, 0.2975456000, 0.8817977000"); - } - } - max_capacitance : 0.5328470000; - max_transition : 1.5077670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1176624000, 0.1211953000, 0.1302119000, 0.1504058000, 0.1927356000, 0.2959856000, 0.6031842000", \ - "0.1230620000, 0.1265467000, 0.1356027000, 0.1557674000, 0.1983010000, 0.3014897000, 0.6088806000", \ - "0.1362588000, 0.1397258000, 0.1488244000, 0.1690206000, 0.2113689000, 0.3146443000, 0.6218698000", \ - "0.1671590000, 0.1706760000, 0.1795174000, 0.2000300000, 0.2423069000, 0.3456893000, 0.6525671000", \ - "0.2403789000, 0.2438929000, 0.2524743000, 0.2724942000, 0.3157611000, 0.4187666000, 0.7262591000", \ - "0.3693820000, 0.3739397000, 0.3858142000, 0.4109687000, 0.4588423000, 0.5655961000, 0.8725635000", \ - "0.5720747000, 0.5781848000, 0.5927933000, 0.6261505000, 0.6882516000, 0.8061523000, 1.1158997000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1340763000, 0.1393270000, 0.1531677000, 0.1856525000, 0.2643026000, 0.4891171000, 1.1990191000", \ - "0.1378671000, 0.1431018000, 0.1568382000, 0.1894099000, 0.2682454000, 0.4924377000, 1.2045442000", \ - "0.1472179000, 0.1524737000, 0.1662910000, 0.1987366000, 0.2775485000, 0.5018227000, 1.2143205000", \ - "0.1696199000, 0.1748860000, 0.1887813000, 0.2212735000, 0.2999053000, 0.5247459000, 1.2356726000", \ - "0.2196725000, 0.2250672000, 0.2390340000, 0.2718083000, 0.3508999000, 0.5753048000, 1.2867362000", \ - "0.2899079000, 0.2963531000, 0.3125250000, 0.3483308000, 0.4292096000, 0.6539372000, 1.3658370000", \ - "0.3627692000, 0.3709281000, 0.3919285000, 0.4358308000, 0.5227573000, 0.7481811000, 1.4570243000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0229469000, 0.0250952000, 0.0307727000, 0.0452383000, 0.0837912000, 0.2046444000, 0.6158934000", \ - "0.0231319000, 0.0250296000, 0.0309189000, 0.0452554000, 0.0837586000, 0.2044359000, 0.6119869000", \ - "0.0230371000, 0.0250940000, 0.0310449000, 0.0453760000, 0.0837914000, 0.2046090000, 0.6157672000", \ - "0.0230382000, 0.0252683000, 0.0306832000, 0.0454021000, 0.0837584000, 0.2045494000, 0.6145139000", \ - "0.0246318000, 0.0268010000, 0.0324608000, 0.0464677000, 0.0843488000, 0.2047378000, 0.6111346000", \ - "0.0367968000, 0.0393522000, 0.0457113000, 0.0598095000, 0.0958726000, 0.2091593000, 0.6117996000", \ - "0.0571156000, 0.0599535000, 0.0687328000, 0.0855754000, 0.1213103000, 0.2269871000, 0.6145401000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0318369000, 0.0357385000, 0.0468336000, 0.0769581000, 0.1698014000, 0.4824757000, 1.5060750000", \ - "0.0320573000, 0.0357851000, 0.0468233000, 0.0770289000, 0.1695583000, 0.4822201000, 1.5077671000", \ - "0.0316870000, 0.0356099000, 0.0467802000, 0.0770180000, 0.1695917000, 0.4820878000, 1.5038971000", \ - "0.0317929000, 0.0357566000, 0.0468538000, 0.0769830000, 0.1698987000, 0.4810902000, 1.5056097000", \ - "0.0338949000, 0.0376806000, 0.0483406000, 0.0787425000, 0.1705395000, 0.4826682000, 1.5061586000", \ - "0.0440737000, 0.0479575000, 0.0584061000, 0.0867194000, 0.1756460000, 0.4836797000, 1.5053370000", \ - "0.0615800000, 0.0669115000, 0.0792771000, 0.1064354000, 0.1881244000, 0.4862012000, 1.4997754000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1359565000, 0.1396689000, 0.1492386000, 0.1700226000, 0.2143244000, 0.3183809000, 0.6259408000", \ - "0.1413544000, 0.1450709000, 0.1546215000, 0.1757347000, 0.2196924000, 0.3236059000, 0.6312798000", \ - "0.1548157000, 0.1585121000, 0.1677815000, 0.1887002000, 0.2322355000, 0.3366315000, 0.6443373000", \ - "0.1866876000, 0.1901470000, 0.2000052000, 0.2209877000, 0.2646539000, 0.3688401000, 0.6762538000", \ - "0.2626976000, 0.2657046000, 0.2759215000, 0.2968464000, 0.3396162000, 0.4444486000, 0.7518973000", \ - "0.4102824000, 0.4153270000, 0.4266339000, 0.4516502000, 0.5003866000, 0.6072751000, 0.9145803000", \ - "0.6500261000, 0.6558750000, 0.6715567000, 0.7050849000, 0.7665708000, 0.8840779000, 1.1934486000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1413094000, 0.1465486000, 0.1603386000, 0.1928597000, 0.2714039000, 0.4959720000, 1.2081963000", \ - "0.1454501000, 0.1507121000, 0.1645203000, 0.1969231000, 0.2757359000, 0.4996989000, 1.2120310000", \ - "0.1541238000, 0.1594017000, 0.1731951000, 0.2056292000, 0.2844261000, 0.5083565000, 1.2168315000", \ - "0.1740558000, 0.1793654000, 0.1931983000, 0.2256948000, 0.3044672000, 0.5284735000, 1.2370853000", \ - "0.2163721000, 0.2218114000, 0.2357964000, 0.2687423000, 0.3476789000, 0.5724896000, 1.2861576000", \ - "0.2801762000, 0.2863977000, 0.3023365000, 0.3379085000, 0.4194913000, 0.6449998000, 1.3573733000", \ - "0.3446815000, 0.3524749000, 0.3724984000, 0.4151260000, 0.5023190000, 0.7288417000, 1.4369101000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0254384000, 0.0277563000, 0.0335643000, 0.0482841000, 0.0859561000, 0.2059903000, 0.6126439000", \ - "0.0253164000, 0.0275687000, 0.0336115000, 0.0477444000, 0.0860646000, 0.2061037000, 0.6166605000", \ - "0.0253245000, 0.0275907000, 0.0335511000, 0.0478728000, 0.0863612000, 0.2062060000, 0.6133797000", \ - "0.0253257000, 0.0274571000, 0.0334929000, 0.0477311000, 0.0860630000, 0.2062706000, 0.6157208000", \ - "0.0259922000, 0.0278997000, 0.0339873000, 0.0481977000, 0.0867450000, 0.2061078000, 0.6156615000", \ - "0.0371672000, 0.0393218000, 0.0464858000, 0.0592353000, 0.0944703000, 0.2090278000, 0.6163081000", \ - "0.0575287000, 0.0605187000, 0.0683342000, 0.0858129000, 0.1208752000, 0.2256639000, 0.6157173000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0318695000, 0.0358283000, 0.0468862000, 0.0768902000, 0.1698781000, 0.4818674000, 1.5013298000", \ - "0.0318180000, 0.0357527000, 0.0467176000, 0.0771061000, 0.1699917000, 0.4820259000, 1.5023308000", \ - "0.0317292000, 0.0357395000, 0.0467174000, 0.0770136000, 0.1697009000, 0.4822380000, 1.5036692000", \ - "0.0317952000, 0.0357728000, 0.0469011000, 0.0769553000, 0.1695789000, 0.4822560000, 1.5028707000", \ - "0.0336174000, 0.0374186000, 0.0484465000, 0.0782071000, 0.1704859000, 0.4822355000, 1.5047241000", \ - "0.0411861000, 0.0450079000, 0.0558206000, 0.0858962000, 0.1749957000, 0.4824572000, 1.5006988000", \ - "0.0563722000, 0.0616121000, 0.0735963000, 0.1017686000, 0.1855476000, 0.4862266000, 1.4980526000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1463793000, 0.1501818000, 0.1599430000, 0.1814873000, 0.2258389000, 0.3307140000, 0.6382643000", \ - "0.1516765000, 0.1554792000, 0.1652955000, 0.1867589000, 0.2312042000, 0.3360996000, 0.6434325000", \ - "0.1647378000, 0.1685901000, 0.1782668000, 0.2005377000, 0.2448620000, 0.3499950000, 0.6577169000", \ - "0.1970174000, 0.2017078000, 0.2114547000, 0.2328421000, 0.2762625000, 0.3813738000, 0.6892688000", \ - "0.2742508000, 0.2771595000, 0.2868535000, 0.3080985000, 0.3534604000, 0.4587778000, 0.7664901000", \ - "0.4292484000, 0.4335562000, 0.4452826000, 0.4701610000, 0.5181920000, 0.6248703000, 0.9330694000", \ - "0.6834484000, 0.6889978000, 0.7045986000, 0.7376001000, 0.7985659000, 0.9154420000, 1.2250092000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1461514000, 0.1514042000, 0.1652431000, 0.1977486000, 0.2763633000, 0.5006842000, 1.2115609000", \ - "0.1501494000, 0.1554074000, 0.1691529000, 0.2017424000, 0.2804681000, 0.5043301000, 1.2153831000", \ - "0.1580085000, 0.1632249000, 0.1770173000, 0.2095514000, 0.2882395000, 0.5122807000, 1.2231666000", \ - "0.1740834000, 0.1793860000, 0.1932420000, 0.2257365000, 0.3044238000, 0.5284793000, 1.2364118000", \ - "0.2076969000, 0.2131234000, 0.2273186000, 0.2601973000, 0.3392449000, 0.5640593000, 1.2765784000", \ - "0.2596807000, 0.2658394000, 0.2814085000, 0.3169973000, 0.3986289000, 0.6238294000, 1.3330604000", \ - "0.3130191000, 0.3206668000, 0.3398999000, 0.3811383000, 0.4683718000, 0.6952622000, 1.4036469000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0266935000, 0.0290497000, 0.0349898000, 0.0491600000, 0.0875808000, 0.2071880000, 0.6157102000", \ - "0.0265098000, 0.0287434000, 0.0345559000, 0.0494573000, 0.0875377000, 0.2071500000, 0.6144041000", \ - "0.0266206000, 0.0287208000, 0.0346443000, 0.0493539000, 0.0876090000, 0.2071038000, 0.6128622000", \ - "0.0265612000, 0.0290123000, 0.0349111000, 0.0494729000, 0.0875919000, 0.2073620000, 0.6131180000", \ - "0.0267277000, 0.0288112000, 0.0347677000, 0.0495456000, 0.0876008000, 0.2070598000, 0.6156083000", \ - "0.0369957000, 0.0398173000, 0.0455767000, 0.0591666000, 0.0943562000, 0.2095610000, 0.6143105000", \ - "0.0571428000, 0.0602045000, 0.0685627000, 0.0849131000, 0.1198252000, 0.2255216000, 0.6161894000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0318313000, 0.0357206000, 0.0468039000, 0.0769674000, 0.1700028000, 0.4821328000, 1.5038950000", \ - "0.0319539000, 0.0357699000, 0.0469898000, 0.0769861000, 0.1697882000, 0.4821613000, 1.4991854000", \ - "0.0320042000, 0.0356360000, 0.0468606000, 0.0770101000, 0.1698551000, 0.4817081000, 1.5049189000", \ - "0.0317713000, 0.0357611000, 0.0468840000, 0.0769974000, 0.1697960000, 0.4820889000, 1.5021002000", \ - "0.0334629000, 0.0373941000, 0.0480144000, 0.0781122000, 0.1704180000, 0.4824395000, 1.5041959000", \ - "0.0387963000, 0.0429279000, 0.0545034000, 0.0844813000, 0.1743957000, 0.4829192000, 1.5069104000", \ - "0.0524485000, 0.0575287000, 0.0691846000, 0.0990066000, 0.1844223000, 0.4860258000, 1.4950077000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3b_1") { - leakage_power () { - value : 0.0066987000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0063668000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0023160000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0067094000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0085140000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0084961000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0088380000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0085160000; - when : "A_N&B&!C"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__and3b"; - cell_leakage_power : 0.0070568720; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0062489000, 0.0061565000, 0.0059437000, 0.0060033000, 0.0061408000, 0.0064575000, 0.0071878000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019112000, 0.0018313000, 0.0016473000, 0.0017058000, 0.0018406000, 0.0021512000, 0.0028673000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015780000; - } - pin ("B") { - capacitance : 0.0015200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029147000, 0.0029130000, 0.0029091000, 0.0029111000, 0.0029158000, 0.0029265000, 0.0029514000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002678400, -0.002672100, -0.002657500, -0.002652900, -0.002642300, -0.002617900, -0.002561700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015500000; - } - pin ("C") { - capacitance : 0.0015480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023377000, 0.0023392000, 0.0023426000, 0.0023427000, 0.0023430000, 0.0023435000, 0.0023451000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002332500, -0.002333000, -0.002333900, -0.002334000, -0.002334300, -0.002334800, -0.002336200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016170000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0079048000, 0.0068964000, 0.0041293000, -0.004035600, -0.026751800, -0.086941100, -0.244216600", \ - "0.0079007000, 0.0068633000, 0.0040983000, -0.004067000, -0.026808400, -0.086963500, -0.244253500", \ - "0.0078495000, 0.0068304000, 0.0040624000, -0.004075400, -0.026840200, -0.086998700, -0.244275800", \ - "0.0075403000, 0.0064913000, 0.0037002000, -0.004427400, -0.027147300, -0.087317600, -0.244590800", \ - "0.0072093000, 0.0061500000, 0.0033798000, -0.004743900, -0.027466100, -0.087635200, -0.244903500", \ - "0.0084028000, 0.0071717000, 0.0039532000, -0.004579300, -0.027544300, -0.087677600, -0.244949800", \ - "0.0084524000, 0.0071400000, 0.0040553000, -0.004575700, -0.027427600, -0.087600200, -0.244968500"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0116701000, 0.0130812000, 0.0166448000, 0.0255698000, 0.0484696000, 0.1081078000, 0.2625884000", \ - "0.0115941000, 0.0129875000, 0.0165750000, 0.0254965000, 0.0484123000, 0.1086725000, 0.2622055000", \ - "0.0116527000, 0.0130446000, 0.0165678000, 0.0255285000, 0.0484546000, 0.1087055000, 0.2621832000", \ - "0.0115082000, 0.0128978000, 0.0164449000, 0.0253609000, 0.0482841000, 0.1085483000, 0.2637534000", \ - "0.0112812000, 0.0126855000, 0.0162616000, 0.0251608000, 0.0480978000, 0.1083780000, 0.2645409000", \ - "0.0111488000, 0.0124672000, 0.0159151000, 0.0250300000, 0.0478184000, 0.1081273000, 0.2617305000", \ - "0.0115083000, 0.0128340000, 0.0163023000, 0.0251092000, 0.0479137000, 0.1078933000, 0.2623444000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0079836000, 0.0068887000, 0.0040760000, -0.004128600, -0.026820500, -0.086955100, -0.244310600", \ - "0.0079048000, 0.0067876000, 0.0039510000, -0.004218200, -0.026902800, -0.087051900, -0.244286300", \ - "0.0077831000, 0.0066805000, 0.0038438000, -0.004340000, -0.027046100, -0.087164400, -0.244383400", \ - "0.0076069000, 0.0065194000, 0.0036445000, -0.004549600, -0.027229700, -0.087339000, -0.244570400", \ - "0.0075596000, 0.0064362000, 0.0036368000, -0.004655700, -0.027361400, -0.087434900, -0.244617700", \ - "0.0080817000, 0.0067560000, 0.0033422000, -0.004837900, -0.027464900, -0.087485100, -0.244620100", \ - "0.0094027000, 0.0080130000, 0.0045460000, -0.004321800, -0.027292100, -0.087144600, -0.244210100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0117052000, 0.0130844000, 0.0166550000, 0.0255428000, 0.0484249000, 0.1079694000, 0.2638624000", \ - "0.0116696000, 0.0130700000, 0.0166037000, 0.0255077000, 0.0483714000, 0.1079938000, 0.2634589000", \ - "0.0115559000, 0.0129378000, 0.0165010000, 0.0253856000, 0.0482561000, 0.1083515000, 0.2650858000", \ - "0.0114518000, 0.0128443000, 0.0164114000, 0.0253125000, 0.0481869000, 0.1082787000, 0.2635676000", \ - "0.0114670000, 0.0128637000, 0.0162856000, 0.0251771000, 0.0480957000, 0.1083802000, 0.2644184000", \ - "0.0118575000, 0.0131496000, 0.0165820000, 0.0251813000, 0.0481162000, 0.1074470000, 0.2645064000", \ - "0.0122016000, 0.0134601000, 0.0168079000, 0.0256588000, 0.0485889000, 0.1084330000, 0.2624291000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0094675000, 0.0083288000, 0.0053763000, -0.003019200, -0.025982400, -0.086247300, -0.243535400", \ - "0.0093371000, 0.0081949000, 0.0052319000, -0.003156300, -0.026092800, -0.086342400, -0.243625800", \ - "0.0092079000, 0.0080716000, 0.0050914000, -0.003285300, -0.026179500, -0.086455400, -0.243772400", \ - "0.0090024000, 0.0078713000, 0.0049354000, -0.003470700, -0.026336700, -0.086588100, -0.243900500", \ - "0.0090358000, 0.0078514000, 0.0048717000, -0.003527800, -0.026442300, -0.086651600, -0.243927100", \ - "0.0091920000, 0.0078664000, 0.0046871000, -0.003505700, -0.026372400, -0.086572700, -0.243845400", \ - "0.0113667000, 0.0096061000, 0.0060969000, -0.002837500, -0.026002800, -0.086090800, -0.243359200"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0122333000, 0.0136287000, 0.0171998000, 0.0260460000, 0.0487947000, 0.1081867000, 0.2651499000", \ - "0.0121637000, 0.0135611000, 0.0171150000, 0.0259559000, 0.0487437000, 0.1081533000, 0.2649151000", \ - "0.0120540000, 0.0134515000, 0.0170043000, 0.0258235000, 0.0486449000, 0.1086056000, 0.2635002000", \ - "0.0118872000, 0.0132835000, 0.0168244000, 0.0257366000, 0.0485282000, 0.1080782000, 0.2638563000", \ - "0.0117037000, 0.0130756000, 0.0166325000, 0.0255244000, 0.0483857000, 0.1079873000, 0.2636101000", \ - "0.0119714000, 0.0133515000, 0.0167618000, 0.0254347000, 0.0483706000, 0.1077146000, 0.2631660000", \ - "0.0123165000, 0.0136136000, 0.0171418000, 0.0260480000, 0.0488869000, 0.1086334000, 0.2637912000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.5051830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1364309000, 0.1430427000, 0.1565571000, 0.1825796000, 0.2362757000, 0.3619381000, 0.6861240000", \ - "0.1413928000, 0.1479341000, 0.1614436000, 0.1874733000, 0.2411637000, 0.3668254000, 0.6910433000", \ - "0.1521143000, 0.1587125000, 0.1721456000, 0.1983483000, 0.2519378000, 0.3775946000, 0.7018640000", \ - "0.1718547000, 0.1783457000, 0.1917561000, 0.2180272000, 0.2716669000, 0.3973547000, 0.7215161000", \ - "0.1993723000, 0.2058849000, 0.2193509000, 0.2454953000, 0.2992367000, 0.4252667000, 0.7491948000", \ - "0.2346703000, 0.2411387000, 0.2545564000, 0.2808462000, 0.3346786000, 0.4605022000, 0.7834649000", \ - "0.2708093000, 0.2773528000, 0.2908497000, 0.3172595000, 0.3712645000, 0.4972364000, 0.8201757000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1628892000, 0.1716745000, 0.1904753000, 0.2312422000, 0.3271335000, 0.5723732000, 1.2126234000", \ - "0.1676258000, 0.1763362000, 0.1952221000, 0.2359169000, 0.3319478000, 0.5769012000, 1.2206509000", \ - "0.1800974000, 0.1887347000, 0.2075162000, 0.2482837000, 0.3443108000, 0.5890251000, 1.2305588000", \ - "0.2100713000, 0.2187244000, 0.2375121000, 0.2782553000, 0.3743003000, 0.6195156000, 1.2612575000", \ - "0.2678257000, 0.2766397000, 0.2954416000, 0.3361777000, 0.4322843000, 0.6775126000, 1.3251400000", \ - "0.3578312000, 0.3666816000, 0.3856955000, 0.4266400000, 0.5227810000, 0.7687072000, 1.4094499000", \ - "0.4981591000, 0.5070578000, 0.5263080000, 0.5674328000, 0.6641319000, 0.9102548000, 1.5476974000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0231240000, 0.0273554000, 0.0374140000, 0.0607343000, 0.1192413000, 0.2790699000, 0.7131827000", \ - "0.0228377000, 0.0273407000, 0.0374161000, 0.0607307000, 0.1193474000, 0.2790475000, 0.7125172000", \ - "0.0230935000, 0.0273341000, 0.0375383000, 0.0606155000, 0.1193953000, 0.2790410000, 0.7123164000", \ - "0.0227505000, 0.0272088000, 0.0375342000, 0.0608293000, 0.1191619000, 0.2789408000, 0.7139195000", \ - "0.0232262000, 0.0274167000, 0.0374675000, 0.0608854000, 0.1191179000, 0.2807507000, 0.7088760000", \ - "0.0230870000, 0.0275177000, 0.0377780000, 0.0612392000, 0.1192732000, 0.2771369000, 0.7149834000", \ - "0.0239976000, 0.0282250000, 0.0387123000, 0.0616184000, 0.1195782000, 0.2805600000, 0.7100129000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0303440000, 0.0381489000, 0.0568567000, 0.1047750000, 0.2346117000, 0.5845245000, 1.4968561000", \ - "0.0304546000, 0.0380758000, 0.0567505000, 0.1047323000, 0.2341237000, 0.5861439000, 1.4981407000", \ - "0.0303388000, 0.0381583000, 0.0567199000, 0.1046672000, 0.2342700000, 0.5859678000, 1.4976814000", \ - "0.0303569000, 0.0381605000, 0.0568554000, 0.1047769000, 0.2343822000, 0.5859128000, 1.5038910000", \ - "0.0306332000, 0.0383105000, 0.0570691000, 0.1049335000, 0.2341888000, 0.5860448000, 1.5046235000", \ - "0.0311316000, 0.0388197000, 0.0575063000, 0.1052018000, 0.2340450000, 0.5842613000, 1.4962822000", \ - "0.0326267000, 0.0400957000, 0.0586079000, 0.1061715000, 0.2348756000, 0.5829816000, 1.4947487000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1253434000, 0.1321035000, 0.1460631000, 0.1727192000, 0.2272459000, 0.3534695000, 0.6768605000", \ - "0.1304592000, 0.1372112000, 0.1509850000, 0.1779100000, 0.2322870000, 0.3585831000, 0.6829197000", \ - "0.1435006000, 0.1502375000, 0.1641089000, 0.1909012000, 0.2453433000, 0.3714472000, 0.6955818000", \ - "0.1750078000, 0.1817984000, 0.1956096000, 0.2224081000, 0.2768300000, 0.4030033000, 0.7271532000", \ - "0.2492558000, 0.2560203000, 0.2697086000, 0.2964132000, 0.3509970000, 0.4774172000, 0.8008360000", \ - "0.3870213000, 0.3956175000, 0.4123620000, 0.4429017000, 0.5006530000, 0.6281247000, 0.9526321000", \ - "0.6062962000, 0.6175308000, 0.6395141000, 0.6784165000, 0.7442517000, 0.8766445000, 1.2012181000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1106570000, 0.1192897000, 0.1381551000, 0.1788013000, 0.2744204000, 0.5199261000, 1.1575255000", \ - "0.1148966000, 0.1236219000, 0.1423584000, 0.1830307000, 0.2786817000, 0.5240689000, 1.1625019000", \ - "0.1234016000, 0.1320143000, 0.1508451000, 0.1915382000, 0.2872411000, 0.5328384000, 1.1717092000", \ - "0.1425313000, 0.1512421000, 0.1700041000, 0.2106010000, 0.3064977000, 0.5525597000, 1.1939766000", \ - "0.1787431000, 0.1879907000, 0.2075607000, 0.2489276000, 0.3452587000, 0.5904874000, 1.2404817000", \ - "0.2286310000, 0.2391394000, 0.2606975000, 0.3039321000, 0.4013703000, 0.6471421000, 1.2865405000", \ - "0.2711122000, 0.2849921000, 0.3120738000, 0.3611839000, 0.4609340000, 0.7077838000, 1.3460872000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0248391000, 0.0289685000, 0.0393545000, 0.0625528000, 0.1203550000, 0.2803196000, 0.7085478000", \ - "0.0246394000, 0.0293816000, 0.0395455000, 0.0627488000, 0.1204548000, 0.2797985000, 0.7087769000", \ - "0.0247658000, 0.0291815000, 0.0397195000, 0.0625323000, 0.1204662000, 0.2798572000, 0.7147766000", \ - "0.0245269000, 0.0290544000, 0.0393070000, 0.0625740000, 0.1204824000, 0.2798418000, 0.7150364000", \ - "0.0256185000, 0.0301566000, 0.0400009000, 0.0636992000, 0.1209752000, 0.2814142000, 0.7138415000", \ - "0.0357349000, 0.0405384000, 0.0505222000, 0.0726437000, 0.1265511000, 0.2815969000, 0.7109376000", \ - "0.0525019000, 0.0585800000, 0.0711296000, 0.0930941000, 0.1441545000, 0.2895151000, 0.7080289000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0302242000, 0.0381040000, 0.0567313000, 0.1048407000, 0.2347602000, 0.5833349000, 1.5021990000", \ - "0.0302758000, 0.0380396000, 0.0567836000, 0.1048215000, 0.2347622000, 0.5829930000, 1.4997467000", \ - "0.0302812000, 0.0381563000, 0.0567715000, 0.1048410000, 0.2347267000, 0.5845683000, 1.5010587000", \ - "0.0303985000, 0.0379833000, 0.0566971000, 0.1046809000, 0.2347056000, 0.5839410000, 1.5035542000", \ - "0.0333693000, 0.0409401000, 0.0595743000, 0.1065765000, 0.2347791000, 0.5861057000, 1.5051834000", \ - "0.0408857000, 0.0481879000, 0.0659424000, 0.1108512000, 0.2373792000, 0.5831161000, 1.5004247000", \ - "0.0555630000, 0.0641031000, 0.0828055000, 0.1237657000, 0.2419814000, 0.5858660000, 1.4951932000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1411211000, 0.1479848000, 0.1619404000, 0.1887478000, 0.2430980000, 0.3693171000, 0.6935545000", \ - "0.1459316000, 0.1527893000, 0.1667209000, 0.1937185000, 0.2479260000, 0.3742048000, 0.6988007000", \ - "0.1589376000, 0.1658176000, 0.1797165000, 0.2064774000, 0.2609941000, 0.3873334000, 0.7113272000", \ - "0.1900901000, 0.1969508000, 0.2109015000, 0.2378369000, 0.2923662000, 0.4187541000, 0.7427269000", \ - "0.2656935000, 0.2724499000, 0.2863550000, 0.3131679000, 0.3678635000, 0.4943245000, 0.8184557000", \ - "0.4122432000, 0.4206064000, 0.4371353000, 0.4669812000, 0.5243121000, 0.6518374000, 0.9762037000", \ - "0.6489051000, 0.6596023000, 0.6811224000, 0.7188115000, 0.7838463000, 0.9153325000, 1.2396267000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1186061000, 0.1273061000, 0.1461061000, 0.1866979000, 0.2821344000, 0.5279817000, 1.1671225000", \ - "0.1226391000, 0.1313289000, 0.1501480000, 0.1907134000, 0.2860870000, 0.5307727000, 1.1684740000", \ - "0.1303008000, 0.1390129000, 0.1578251000, 0.1983499000, 0.2936488000, 0.5387225000, 1.1772496000", \ - "0.1457480000, 0.1544055000, 0.1731084000, 0.2137172000, 0.3090868000, 0.5542902000, 1.1912834000", \ - "0.1739927000, 0.1832094000, 0.2027690000, 0.2443840000, 0.3406168000, 0.5859593000, 1.2240119000", \ - "0.2161071000, 0.2262565000, 0.2475617000, 0.2913163000, 0.3890026000, 0.6345952000, 1.2806444000", \ - "0.2522202000, 0.2655359000, 0.2918872000, 0.3405294000, 0.4405879000, 0.6861873000, 1.3251471000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0259202000, 0.0304848000, 0.0408401000, 0.0639694000, 0.1220460000, 0.2805476000, 0.7137916000", \ - "0.0260706000, 0.0306556000, 0.0405982000, 0.0641697000, 0.1220706000, 0.2806200000, 0.7099062000", \ - "0.0259195000, 0.0309933000, 0.0411136000, 0.0645104000, 0.1219452000, 0.2806392000, 0.7136707000", \ - "0.0260873000, 0.0307073000, 0.0412615000, 0.0642762000, 0.1219070000, 0.2806422000, 0.7137803000", \ - "0.0267417000, 0.0310050000, 0.0412056000, 0.0643544000, 0.1220790000, 0.2816769000, 0.7097584000", \ - "0.0355566000, 0.0403443000, 0.0501777000, 0.0720775000, 0.1267925000, 0.2826958000, 0.7127217000", \ - "0.0523489000, 0.0587698000, 0.0699446000, 0.0917114000, 0.1434033000, 0.2890650000, 0.7097377000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0302767000, 0.0380612000, 0.0566645000, 0.1048311000, 0.2346381000, 0.5843949000, 1.5031406000", \ - "0.0303923000, 0.0380345000, 0.0566747000, 0.1048733000, 0.2347210000, 0.5842981000, 1.4994915000", \ - "0.0303890000, 0.0380248000, 0.0566779000, 0.1048661000, 0.2345642000, 0.5845672000, 1.4997491000", \ - "0.0302888000, 0.0381176000, 0.0567960000, 0.1047027000, 0.2342314000, 0.5845433000, 1.5026181000", \ - "0.0329133000, 0.0407300000, 0.0592393000, 0.1066072000, 0.2352435000, 0.5840346000, 1.5016499000", \ - "0.0386877000, 0.0470999000, 0.0648278000, 0.1106241000, 0.2380887000, 0.5825579000, 1.5013121000", \ - "0.0519538000, 0.0608389000, 0.0803517000, 0.1222078000, 0.2424240000, 0.5856258000, 1.4952395000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3b_2") { - leakage_power () { - value : 0.0061073000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0057627000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0025947000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0061314000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0078875000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0078692000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0082219000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0078908000; - when : "A_N&B&!C"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__and3b"; - cell_leakage_power : 0.0065581650; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0014120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0057799000, 0.0056919000, 0.0054890000, 0.0055536000, 0.0057026000, 0.0060461000, 0.0068376000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020778000, 0.0020090000, 0.0018504000, 0.0019179000, 0.0020735000, 0.0024322000, 0.0032589000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014540000; - } - pin ("B") { - capacitance : 0.0015010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028938000, 0.0028918000, 0.0028873000, 0.0028901000, 0.0028965000, 0.0029114000, 0.0029457000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002657400, -0.002649200, -0.002630500, -0.002626300, -0.002616800, -0.002594900, -0.002544600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015320000; - } - pin ("C") { - capacitance : 0.0015160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022938000, 0.0022914000, 0.0022861000, 0.0022867000, 0.0022881000, 0.0022915000, 0.0022991000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002290100, -0.002287100, -0.002280300, -0.002280500, -0.002280900, -0.002281900, -0.002284300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015840000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0112701000, 0.0097731000, 0.0058765000, -0.005759500, -0.042990800, -0.155337700, -0.484839900", \ - "0.0113053000, 0.0098118000, 0.0058703000, -0.005757900, -0.043004900, -0.155414500, -0.484884300", \ - "0.0112215000, 0.0097495000, 0.0057629000, -0.005833100, -0.043115300, -0.155368600, -0.484842500", \ - "0.0109524000, 0.0094808000, 0.0055244000, -0.006127300, -0.043325100, -0.155731000, -0.485183100", \ - "0.0106139000, 0.0091402000, 0.0051804000, -0.006451000, -0.043695000, -0.156080700, -0.485498800", \ - "0.0128631000, 0.0113495000, 0.0070022000, -0.005844000, -0.043951700, -0.156273500, -0.485708500", \ - "0.0130665000, 0.0115992000, 0.0070856000, -0.005822300, -0.043704600, -0.156209800, -0.485708600"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0165414000, 0.0181299000, 0.0229514000, 0.0367023000, 0.0752885000, 0.1868232000, 0.5154782000", \ - "0.0164607000, 0.0180758000, 0.0228781000, 0.0366273000, 0.0752211000, 0.1868512000, 0.5129833000", \ - "0.0165374000, 0.0181347000, 0.0229221000, 0.0366839000, 0.0751846000, 0.1868583000, 0.5134717000", \ - "0.0163875000, 0.0180002000, 0.0227806000, 0.0364545000, 0.0750554000, 0.1867963000, 0.5127843000", \ - "0.0161711000, 0.0177800000, 0.0225706000, 0.0362982000, 0.0748372000, 0.1865288000, 0.5130162000", \ - "0.0159538000, 0.0175388000, 0.0223784000, 0.0360758000, 0.0744805000, 0.1862851000, 0.5132473000", \ - "0.0169215000, 0.0185114000, 0.0229715000, 0.0363035000, 0.0746389000, 0.1870846000, 0.5117741000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0113792000, 0.0098714000, 0.0058212000, -0.005956700, -0.043198800, -0.155539400, -0.484897300", \ - "0.0113095000, 0.0097787000, 0.0057263000, -0.006036000, -0.043277800, -0.155615200, -0.484966400", \ - "0.0112125000, 0.0096902000, 0.0056583000, -0.006105500, -0.043377100, -0.155690900, -0.485079900", \ - "0.0110708000, 0.0095491000, 0.0054644000, -0.006302400, -0.043558100, -0.155863000, -0.485242700", \ - "0.0110101000, 0.0094750000, 0.0054390000, -0.006537500, -0.043864500, -0.156122500, -0.485430300", \ - "0.0116153000, 0.0099316000, 0.0052498000, -0.006447500, -0.043899300, -0.156155900, -0.485395900", \ - "0.0150875000, 0.0132508000, 0.0082379000, -0.005204000, -0.043795500, -0.156018100, -0.485166600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0164971000, 0.0180918000, 0.0229184000, 0.0366029000, 0.0750247000, 0.1867997000, 0.5133944000", \ - "0.0164622000, 0.0180717000, 0.0228772000, 0.0365711000, 0.0750175000, 0.1866769000, 0.5131706000", \ - "0.0164211000, 0.0180380000, 0.0228168000, 0.0363410000, 0.0748914000, 0.1866555000, 0.5147538000", \ - "0.0162316000, 0.0178982000, 0.0226551000, 0.0363455000, 0.0748813000, 0.1865929000, 0.5130266000", \ - "0.0162939000, 0.0178698000, 0.0225626000, 0.0361749000, 0.0746024000, 0.1864474000, 0.5131865000", \ - "0.0171715000, 0.0186824000, 0.0231424000, 0.0360017000, 0.0744589000, 0.1859213000, 0.5127907000", \ - "0.0180237000, 0.0194643000, 0.0238153000, 0.0369713000, 0.0756159000, 0.1869357000, 0.5126198000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0129459000, 0.0113829000, 0.0073053000, -0.004608100, -0.042003900, -0.154448200, -0.483879300", \ - "0.0129138000, 0.0114211000, 0.0071908000, -0.004678400, -0.042161600, -0.154526900, -0.483977500", \ - "0.0127571000, 0.0111925000, 0.0071608000, -0.004737300, -0.042190200, -0.154629000, -0.484062900", \ - "0.0126232000, 0.0110819000, 0.0069915000, -0.004946300, -0.042364900, -0.154808300, -0.484198900", \ - "0.0124413000, 0.0109132000, 0.0068185000, -0.005168300, -0.042616200, -0.154959100, -0.484313600", \ - "0.0128888000, 0.0112686000, 0.0071837000, -0.004961300, -0.042536800, -0.154913500, -0.484280000", \ - "0.0167773000, 0.0149361000, 0.0098670000, -0.003666200, -0.042416400, -0.154730900, -0.483996500"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("0.0169667000, 0.0186659000, 0.0233675000, 0.0370699000, 0.0754777000, 0.1870274000, 0.5158084000", \ - "0.0169556000, 0.0185717000, 0.0233544000, 0.0371036000, 0.0753610000, 0.1869049000, 0.5132870000", \ - "0.0168979000, 0.0185131000, 0.0232959000, 0.0369080000, 0.0753634000, 0.1868905000, 0.5132532000", \ - "0.0166911000, 0.0182806000, 0.0231114000, 0.0368442000, 0.0752924000, 0.1868334000, 0.5128613000", \ - "0.0166566000, 0.0182222000, 0.0229437000, 0.0366143000, 0.0750974000, 0.1867412000, 0.5127613000", \ - "0.0174897000, 0.0190090000, 0.0235061000, 0.0364046000, 0.0750266000, 0.1865368000, 0.5132042000", \ - "0.0179826000, 0.0194470000, 0.0238676000, 0.0371050000, 0.0757763000, 0.1873277000, 0.5113313000"); - } - } - max_capacitance : 0.3094580000; - max_transition : 1.5048830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1682981000, 0.1742941000, 0.1877613000, 0.2147268000, 0.2677237000, 0.3894584000, 0.7227766000", \ - "0.1730536000, 0.1790349000, 0.1924802000, 0.2194355000, 0.2724321000, 0.3942118000, 0.7268723000", \ - "0.1839900000, 0.1899908000, 0.2034404000, 0.2304011000, 0.2835190000, 0.4051459000, 0.7383006000", \ - "0.2034424000, 0.2094555000, 0.2228640000, 0.2497664000, 0.3030784000, 0.4246393000, 0.7579167000", \ - "0.2300583000, 0.2360386000, 0.2493366000, 0.2762299000, 0.3296418000, 0.4512725000, 0.7843755000", \ - "0.2635050000, 0.2695096000, 0.2829674000, 0.3098808000, 0.3631951000, 0.4851042000, 0.8176496000", \ - "0.2963481000, 0.3023626000, 0.3158595000, 0.3428657000, 0.3963579000, 0.5182438000, 0.8516045000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1869359000, 0.1945706000, 0.2121667000, 0.2497989000, 0.3364400000, 0.5695280000, 1.2446533000", \ - "0.1917084000, 0.1993672000, 0.2169651000, 0.2545572000, 0.3412214000, 0.5740511000, 1.2565845000", \ - "0.2044040000, 0.2120208000, 0.2295453000, 0.2672605000, 0.3538076000, 0.5874582000, 1.2632967000", \ - "0.2345119000, 0.2421376000, 0.2596817000, 0.2972869000, 0.3839516000, 0.6165791000, 1.2939348000", \ - "0.2921611000, 0.2997928000, 0.3172846000, 0.3549717000, 0.4415733000, 0.6751142000, 1.3531331000", \ - "0.3815740000, 0.3893098000, 0.4068174000, 0.4444609000, 0.5312151000, 0.7645438000, 1.4418261000", \ - "0.5225398000, 0.5303784000, 0.5479971000, 0.5859639000, 0.6730393000, 0.9067970000, 1.5820117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0266919000, 0.0304851000, 0.0396631000, 0.0587872000, 0.1081217000, 0.2501604000, 0.6936862000", \ - "0.0267062000, 0.0305166000, 0.0392475000, 0.0593103000, 0.1083131000, 0.2506942000, 0.6906598000", \ - "0.0267841000, 0.0306549000, 0.0394078000, 0.0587340000, 0.1082292000, 0.2504011000, 0.6939874000", \ - "0.0267316000, 0.0305295000, 0.0391695000, 0.0592571000, 0.1080492000, 0.2506255000, 0.6894301000", \ - "0.0268516000, 0.0306352000, 0.0396697000, 0.0588165000, 0.1083555000, 0.2504097000, 0.6902271000", \ - "0.0270520000, 0.0308282000, 0.0395043000, 0.0595194000, 0.1083940000, 0.2493858000, 0.6956594000", \ - "0.0274228000, 0.0312999000, 0.0398691000, 0.0593526000, 0.1086170000, 0.2506039000, 0.6902721000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0306810000, 0.0363836000, 0.0509420000, 0.0879604000, 0.1946843000, 0.5223191000, 1.5040865000", \ - "0.0304499000, 0.0363901000, 0.0509903000, 0.0879522000, 0.1947979000, 0.5230769000, 1.5015951000", \ - "0.0304470000, 0.0365773000, 0.0507365000, 0.0878091000, 0.1950231000, 0.5238676000, 1.5019536000", \ - "0.0307769000, 0.0363611000, 0.0509644000, 0.0878317000, 0.1948917000, 0.5234704000, 1.4996773000", \ - "0.0307541000, 0.0366326000, 0.0509859000, 0.0877385000, 0.1947620000, 0.5239195000, 1.5016069000", \ - "0.0310915000, 0.0369359000, 0.0513813000, 0.0882618000, 0.1950166000, 0.5226371000, 1.5031700000", \ - "0.0319493000, 0.0378030000, 0.0523432000, 0.0889217000, 0.1955432000, 0.5229567000, 1.4945640000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1591908000, 0.1654951000, 0.1795851000, 0.2073026000, 0.2615496000, 0.3843963000, 0.7179055000", \ - "0.1645438000, 0.1708333000, 0.1848569000, 0.2125307000, 0.2669566000, 0.3896932000, 0.7231495000", \ - "0.1778555000, 0.1841352000, 0.1974459000, 0.2259520000, 0.2803290000, 0.4030170000, 0.7363309000", \ - "0.2090212000, 0.2153258000, 0.2297216000, 0.2570083000, 0.3113693000, 0.4341322000, 0.7677630000", \ - "0.2846970000, 0.2909486000, 0.3049406000, 0.3326354000, 0.3869941000, 0.5098196000, 0.8432282000", \ - "0.4416306000, 0.4489293000, 0.4646737000, 0.4955110000, 0.5523579000, 0.6762909000, 1.0099976000", \ - "0.6965725000, 0.7059121000, 0.7270182000, 0.7670587000, 0.8364965000, 0.9692166000, 1.3041385000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1358929000, 0.1435636000, 0.1610549000, 0.1986936000, 0.2851418000, 0.5186079000, 1.1978272000", \ - "0.1402058000, 0.1478505000, 0.1653388000, 0.2029773000, 0.2894424000, 0.5229093000, 1.2022083000", \ - "0.1488407000, 0.1565781000, 0.1739988000, 0.2114625000, 0.2981246000, 0.5311512000, 1.2091262000", \ - "0.1685061000, 0.1761842000, 0.1937688000, 0.2313249000, 0.3177517000, 0.5513218000, 1.2253992000", \ - "0.2101572000, 0.2181569000, 0.2361123000, 0.2741924000, 0.3609905000, 0.5947359000, 1.2690128000", \ - "0.2747094000, 0.2838088000, 0.3039908000, 0.3439348000, 0.4334264000, 0.6672042000, 1.3457896000", \ - "0.3445867000, 0.3560808000, 0.3815297000, 0.4296137000, 0.5233905000, 0.7580572000, 1.4323377000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0293012000, 0.0329047000, 0.0420826000, 0.0612644000, 0.1104363000, 0.2522254000, 0.6946015000", \ - "0.0289785000, 0.0328962000, 0.0419789000, 0.0614429000, 0.1103527000, 0.2520039000, 0.6903597000", \ - "0.0290218000, 0.0328779000, 0.0421654000, 0.0613785000, 0.1104912000, 0.2524385000, 0.6948856000", \ - "0.0290559000, 0.0331139000, 0.0422084000, 0.0613903000, 0.1104351000, 0.2519945000, 0.6894275000", \ - "0.0289834000, 0.0329672000, 0.0417266000, 0.0612706000, 0.1103985000, 0.2526074000, 0.6953959000", \ - "0.0382521000, 0.0421120000, 0.0511785000, 0.0699024000, 0.1156229000, 0.2534936000, 0.6930373000", \ - "0.0585180000, 0.0629814000, 0.0743231000, 0.0952225000, 0.1409193000, 0.2675669000, 0.6934396000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0306560000, 0.0363470000, 0.0508890000, 0.0879888000, 0.1950883000, 0.5229205000, 1.5031709000", \ - "0.0305309000, 0.0363044000, 0.0509423000, 0.0879997000, 0.1950758000, 0.5230424000, 1.5018105000", \ - "0.0306352000, 0.0364829000, 0.0510057000, 0.0877087000, 0.1947074000, 0.5235911000, 1.5006053000", \ - "0.0305545000, 0.0364104000, 0.0508613000, 0.0877753000, 0.1947475000, 0.5224991000, 1.5000396000", \ - "0.0324315000, 0.0384717000, 0.0524299000, 0.0889831000, 0.1955658000, 0.5239451000, 1.5012923000", \ - "0.0393205000, 0.0454483000, 0.0595912000, 0.0963518000, 0.1994067000, 0.5241381000, 1.5015024000", \ - "0.0538440000, 0.0612569000, 0.0770808000, 0.1109934000, 0.2079642000, 0.5264162000, 1.4930278000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1734304000, 0.1797851000, 0.1939625000, 0.2219107000, 0.2761421000, 0.3991878000, 0.7325276000", \ - "0.1784979000, 0.1848521000, 0.1990100000, 0.2270255000, 0.2814395000, 0.4042534000, 0.7376321000", \ - "0.1915705000, 0.1979027000, 0.2117119000, 0.2396489000, 0.2939633000, 0.4168955000, 0.7504602000", \ - "0.2228915000, 0.2292784000, 0.2440571000, 0.2719606000, 0.3264758000, 0.4495208000, 0.7832427000", \ - "0.2993227000, 0.3056998000, 0.3199911000, 0.3478533000, 0.4024548000, 0.5254636000, 0.8594182000", \ - "0.4628645000, 0.4700088000, 0.4860478000, 0.5161225000, 0.5723643000, 0.6960061000, 1.0293477000", \ - "0.7350130000, 0.7444083000, 0.7651384000, 0.8041582000, 0.8723702000, 1.0042950000, 1.3396266000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.1434287000, 0.1510880000, 0.1685646000, 0.2062128000, 0.2926211000, 0.5258000000, 1.2037533000", \ - "0.1476384000, 0.1552894000, 0.1727553000, 0.2104144000, 0.2967486000, 0.5297898000, 1.2052054000", \ - "0.1554882000, 0.1632388000, 0.1806789000, 0.2182119000, 0.3047225000, 0.5377377000, 1.2143042000", \ - "0.1710967000, 0.1787413000, 0.1963389000, 0.2339565000, 0.3204194000, 0.5527853000, 1.2351348000", \ - "0.2030433000, 0.2109196000, 0.2289771000, 0.2670959000, 0.3540297000, 0.5866495000, 1.2696670000", \ - "0.2543133000, 0.2630951000, 0.2829051000, 0.3232887000, 0.4127328000, 0.6467612000, 1.3211018000", \ - "0.3121192000, 0.3229891000, 0.3470359000, 0.3933936000, 0.4873438000, 0.7226589000, 1.3970787000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0300070000, 0.0341722000, 0.0425046000, 0.0626008000, 0.1113205000, 0.2527143000, 0.6957019000", \ - "0.0299857000, 0.0342779000, 0.0432024000, 0.0620894000, 0.1112633000, 0.2526352000, 0.6912125000", \ - "0.0303141000, 0.0341716000, 0.0427517000, 0.0621284000, 0.1113355000, 0.2524451000, 0.6953962000", \ - "0.0304644000, 0.0343353000, 0.0428980000, 0.0628093000, 0.1112513000, 0.2521715000, 0.6937508000", \ - "0.0299037000, 0.0338515000, 0.0428549000, 0.0622391000, 0.1109038000, 0.2523062000, 0.6941166000", \ - "0.0376737000, 0.0415543000, 0.0502217000, 0.0689255000, 0.1151867000, 0.2539008000, 0.6956330000", \ - "0.0572677000, 0.0624960000, 0.0728751000, 0.0933991000, 0.1387150000, 0.2667237000, 0.6948337000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0307466000, 0.0363392000, 0.0510072000, 0.0880145000, 0.1950791000, 0.5228699000, 1.5048830000", \ - "0.0304941000, 0.0365417000, 0.0509535000, 0.0879346000, 0.1950306000, 0.5239282000, 1.5012930000", \ - "0.0306234000, 0.0364587000, 0.0509072000, 0.0880128000, 0.1947511000, 0.5241177000, 1.5019789000", \ - "0.0306684000, 0.0363464000, 0.0508672000, 0.0878660000, 0.1948412000, 0.5234553000, 1.5023885000", \ - "0.0321707000, 0.0383172000, 0.0524148000, 0.0891109000, 0.1953468000, 0.5234199000, 1.5024292000", \ - "0.0370353000, 0.0431698000, 0.0582470000, 0.0947996000, 0.1995102000, 0.5241901000, 1.4999270000", \ - "0.0499675000, 0.0570042000, 0.0725720000, 0.1091202000, 0.2070704000, 0.5267303000, 1.4955259000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and3b_4") { - leakage_power () { - value : 0.0039207000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0035795000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0053832000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0039380000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0037504000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0037320000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0040781000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0037533000; - when : "A_N&B&!C"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__and3b"; - cell_leakage_power : 0.0040169030; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079176000, 0.0078176000, 0.0075870000, 0.0076307000, 0.0077314000, 0.0079636000, 0.0084987000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0052167000, 0.0051572000, 0.0050199000, 0.0050512000, 0.0051233000, 0.0052896000, 0.0056729000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016410000; - } - pin ("B") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046442000, 0.0046439000, 0.0046432000, 0.0046461000, 0.0046528000, 0.0046683000, 0.0047039000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004336800, -0.004335000, -0.004331000, -0.004326500, -0.004316100, -0.004292200, -0.004237100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024650000; - } - pin ("C") { - capacitance : 0.0023900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042951000, 0.0042940000, 0.0042916000, 0.0042896000, 0.0042851000, 0.0042747000, 0.0042508000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004285300, -0.004286100, -0.004288000, -0.004287800, -0.004287300, -0.004286200, -0.004283600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025300000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0223514000, 0.0207171000, 0.0158446000, 0.0013463000, -0.047582800, -0.208777600, -0.715307400", \ - "0.0223093000, 0.0207188000, 0.0158344000, 0.0013239000, -0.047577000, -0.208775700, -0.715308600", \ - "0.0223233000, 0.0206565000, 0.0158385000, 0.0013270000, -0.047632000, -0.208751900, -0.715325800", \ - "0.0219393000, 0.0203751000, 0.0154692000, 0.0009634000, -0.048013900, -0.209114800, -0.715781100", \ - "0.0215629000, 0.0200078000, 0.0150626000, 0.0005028000, -0.048399500, -0.209602300, -0.716059700", \ - "0.0252608000, 0.0235945000, 0.0184824000, 0.0025844000, -0.048668300, -0.209899100, -0.716377900", \ - "0.0257952000, 0.0240423000, 0.0188821000, 0.0030218000, -0.048020900, -0.209684400, -0.716351700"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0305587000, 0.0323155000, 0.0377873000, 0.0551506000, 0.1072990000, 0.2681378000, 0.7708354000", \ - "0.0305497000, 0.0323015000, 0.0376984000, 0.0551659000, 0.1073153000, 0.2684254000, 0.7702713000", \ - "0.0305337000, 0.0323184000, 0.0378965000, 0.0550445000, 0.1074315000, 0.2683779000, 0.7696154000", \ - "0.0303257000, 0.0320952000, 0.0376719000, 0.0548427000, 0.1071851000, 0.2681092000, 0.7692421000", \ - "0.0299584000, 0.0316906000, 0.0372228000, 0.0545033000, 0.1068092000, 0.2679090000, 0.7698627000", \ - "0.0300543000, 0.0317621000, 0.0371684000, 0.0545574000, 0.1066968000, 0.2675748000, 0.7668668000", \ - "0.0310822000, 0.0327933000, 0.0381791000, 0.0547779000, 0.1064349000, 0.2674164000, 0.7682393000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0227710000, 0.0210829000, 0.0160987000, 0.0015965000, -0.047409100, -0.208419400, -0.714914900", \ - "0.0226614000, 0.0209764000, 0.0160071000, 0.0015315000, -0.047431400, -0.208485400, -0.714936300", \ - "0.0223783000, 0.0208205000, 0.0158050000, 0.0013569000, -0.047582300, -0.208673700, -0.715171800", \ - "0.0222169000, 0.0206711000, 0.0156747000, 0.0009672000, -0.047973800, -0.208908000, -0.715354900", \ - "0.0223827000, 0.0207806000, 0.0154093000, 0.0007464000, -0.048402400, -0.209322900, -0.715680400", \ - "0.0226399000, 0.0208655000, 0.0152751000, 0.0004911000, -0.048568300, -0.209227900, -0.715171600", \ - "0.0293799000, 0.0273374000, 0.0212337000, 0.0041864000, -0.047727500, -0.209136600, -0.714880000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0309283000, 0.0327374000, 0.0381691000, 0.0555397000, 0.1076947000, 0.2685702000, 0.7705446000", \ - "0.0308547000, 0.0326387000, 0.0382268000, 0.0555457000, 0.1074846000, 0.2681563000, 0.7700074000", \ - "0.0307067000, 0.0324485000, 0.0380494000, 0.0553338000, 0.1073450000, 0.2685187000, 0.7697825000", \ - "0.0304119000, 0.0322049000, 0.0377889000, 0.0551340000, 0.1073973000, 0.2682899000, 0.7697869000", \ - "0.0304240000, 0.0321311000, 0.0375728000, 0.0548093000, 0.1068858000, 0.2678633000, 0.7674508000", \ - "0.0317899000, 0.0334549000, 0.0385678000, 0.0550925000, 0.1069524000, 0.2675210000, 0.7701870000", \ - "0.0329781000, 0.0345695000, 0.0397102000, 0.0561428000, 0.1080398000, 0.2681794000, 0.7675769000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0249741000, 0.0232663000, 0.0180743000, 0.0033246000, -0.046104600, -0.207459800, -0.714071800", \ - "0.0248142000, 0.0231260000, 0.0180108000, 0.0032049000, -0.046196100, -0.207582000, -0.714182300", \ - "0.0246923000, 0.0229881000, 0.0177927000, 0.0030276000, -0.046361300, -0.207719400, -0.714328300", \ - "0.0244082000, 0.0226917000, 0.0175957000, 0.0027309000, -0.046564700, -0.207912900, -0.714509600", \ - "0.0244506000, 0.0227350000, 0.0175414000, 0.0029860000, -0.046540100, -0.207907200, -0.714423000", \ - "0.0245547000, 0.0227574000, 0.0173519000, 0.0027568000, -0.046698600, -0.207455800, -0.714011500", \ - "0.0317729000, 0.0297476000, 0.0250808000, 0.0067399000, -0.045533000, -0.207316100, -0.713611200"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015596110, 0.0048647760, 0.0151743200, 0.0473320900, 0.1476394000, 0.4605201000"); - values("0.0313264000, 0.0330834000, 0.0386739000, 0.0557806000, 0.1079486000, 0.2684031000, 0.7702439000", \ - "0.0311895000, 0.0329251000, 0.0385466000, 0.0556430000, 0.1078023000, 0.2684615000, 0.7699958000", \ - "0.0311212000, 0.0328603000, 0.0383617000, 0.0557210000, 0.1077909000, 0.2685589000, 0.7670616000", \ - "0.0307747000, 0.0325114000, 0.0380992000, 0.0555094000, 0.1076233000, 0.2684069000, 0.7669895000", \ - "0.0305992000, 0.0323862000, 0.0378821000, 0.0551077000, 0.1071985000, 0.2681731000, 0.7670809000", \ - "0.0318213000, 0.0334888000, 0.0387549000, 0.0549509000, 0.1071490000, 0.2678660000, 0.7695688000", \ - "0.0335536000, 0.0351747000, 0.0403783000, 0.0568024000, 0.1087094000, 0.2690884000, 0.7677044000"); - } - } - max_capacitance : 0.4605200000; - max_transition : 1.5062610000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.1658345000, 0.1694336000, 0.1787394000, 0.1990043000, 0.2405217000, 0.3359291000, 0.6035871000", \ - "0.1707209000, 0.1743577000, 0.1836058000, 0.2038608000, 0.2453925000, 0.3408067000, 0.6084470000", \ - "0.1818042000, 0.1854295000, 0.1946664000, 0.2149318000, 0.2564701000, 0.3519462000, 0.6195922000", \ - "0.2043527000, 0.2080248000, 0.2172343000, 0.2375792000, 0.2790151000, 0.3745289000, 0.6422237000", \ - "0.2370744000, 0.2407413000, 0.2498512000, 0.2702170000, 0.3117875000, 0.4072291000, 0.6750158000", \ - "0.2763746000, 0.2799510000, 0.2891752000, 0.3094766000, 0.3510776000, 0.4465978000, 0.7146837000", \ - "0.3104761000, 0.3146234000, 0.3239105000, 0.3441353000, 0.3859975000, 0.4816103000, 0.7491373000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.2483533000, 0.2538199000, 0.2679431000, 0.3012115000, 0.3812453000, 0.6056254000, 1.3009334000", \ - "0.2530307000, 0.2585680000, 0.2729580000, 0.3063063000, 0.3864336000, 0.6107362000, 1.3003832000", \ - "0.2654715000, 0.2710675000, 0.2852679000, 0.3185077000, 0.3986030000, 0.6231339000, 1.3155783000", \ - "0.2972281000, 0.3027835000, 0.3169964000, 0.3502363000, 0.4302214000, 0.6548342000, 1.3463994000", \ - "0.3698022000, 0.3753255000, 0.3895212000, 0.4228862000, 0.5030477000, 0.7272059000, 1.4187659000", \ - "0.5038107000, 0.5095743000, 0.5237656000, 0.5571999000, 0.6371315000, 0.8619455000, 1.5571527000", \ - "0.7225435000, 0.7282284000, 0.7428421000, 0.7764834000, 0.8570710000, 1.0817216000, 1.7745297000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0243038000, 0.0265939000, 0.0321472000, 0.0463124000, 0.0824061000, 0.1889534000, 0.5387794000", \ - "0.0242471000, 0.0264883000, 0.0321429000, 0.0468459000, 0.0824307000, 0.1889388000, 0.5387805000", \ - "0.0242455000, 0.0267903000, 0.0327535000, 0.0465892000, 0.0824229000, 0.1885715000, 0.5388459000", \ - "0.0242330000, 0.0267702000, 0.0323040000, 0.0465013000, 0.0825610000, 0.1887256000, 0.5399632000", \ - "0.0243838000, 0.0265547000, 0.0324363000, 0.0463029000, 0.0825830000, 0.1885940000, 0.5380242000", \ - "0.0244835000, 0.0267267000, 0.0328116000, 0.0464049000, 0.0826569000, 0.1885290000, 0.5398688000", \ - "0.0252093000, 0.0272522000, 0.0330576000, 0.0474668000, 0.0829562000, 0.1888490000, 0.5381732000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0335047000, 0.0377963000, 0.0496990000, 0.0814838000, 0.1782472000, 0.4937827000, 1.5062610000", \ - "0.0334867000, 0.0377428000, 0.0493828000, 0.0814288000, 0.1785060000, 0.4945296000, 1.4999878000", \ - "0.0333433000, 0.0378130000, 0.0495551000, 0.0813628000, 0.1781301000, 0.4942656000, 1.5031462000", \ - "0.0334691000, 0.0377154000, 0.0494311000, 0.0815770000, 0.1782811000, 0.4940544000, 1.5019416000", \ - "0.0336178000, 0.0379015000, 0.0497018000, 0.0815249000, 0.1784208000, 0.4949373000, 1.5037730000", \ - "0.0339261000, 0.0382591000, 0.0501233000, 0.0817797000, 0.1783161000, 0.4946213000, 1.5041068000", \ - "0.0353381000, 0.0394507000, 0.0513073000, 0.0831765000, 0.1790956000, 0.4961787000, 1.5003663000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.1431374000, 0.1469967000, 0.1566889000, 0.1778176000, 0.2205564000, 0.3167069000, 0.5850114000", \ - "0.1486611000, 0.1525585000, 0.1623221000, 0.1835004000, 0.2260444000, 0.3224362000, 0.5904242000", \ - "0.1614734000, 0.1653212000, 0.1750721000, 0.1960638000, 0.2386971000, 0.3350156000, 0.6031863000", \ - "0.1934082000, 0.1973084000, 0.2068358000, 0.2280784000, 0.2707610000, 0.3669099000, 0.6352389000", \ - "0.2689862000, 0.2728402000, 0.2817934000, 0.3034693000, 0.3461116000, 0.4425735000, 0.7107478000", \ - "0.4180409000, 0.4227458000, 0.4350371000, 0.4591922000, 0.5060907000, 0.6044626000, 0.8705339000", \ - "0.6604541000, 0.6665682000, 0.6819884000, 0.7145676000, 0.7743197000, 0.8838971000, 1.1557874000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.1487384000, 0.1542468000, 0.1684161000, 0.2017495000, 0.2817828000, 0.5051977000, 1.1983532000", \ - "0.1529351000, 0.1585343000, 0.1726867000, 0.2059786000, 0.2858867000, 0.5098049000, 1.2014590000", \ - "0.1612229000, 0.1667367000, 0.1809292000, 0.2141898000, 0.2939440000, 0.5184365000, 1.2118984000", \ - "0.1800226000, 0.1856421000, 0.1998502000, 0.2331477000, 0.3131067000, 0.5372743000, 1.2290349000", \ - "0.2206964000, 0.2263520000, 0.2408087000, 0.2743815000, 0.3545805000, 0.5793795000, 1.2754470000", \ - "0.2838386000, 0.2903956000, 0.3063504000, 0.3423896000, 0.4248569000, 0.6496793000, 1.3445821000", \ - "0.3489636000, 0.3569215000, 0.3769638000, 0.4193793000, 0.5068862000, 0.7328308000, 1.4231906000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0268340000, 0.0291732000, 0.0350805000, 0.0493126000, 0.0844545000, 0.1900674000, 0.5403532000", \ - "0.0270080000, 0.0290450000, 0.0349770000, 0.0490244000, 0.0845919000, 0.1899109000, 0.5401845000", \ - "0.0270608000, 0.0293741000, 0.0348282000, 0.0493505000, 0.0845991000, 0.1903081000, 0.5404150000", \ - "0.0268054000, 0.0293482000, 0.0352887000, 0.0491465000, 0.0841060000, 0.1898825000, 0.5403161000", \ - "0.0271864000, 0.0291501000, 0.0349801000, 0.0489577000, 0.0845599000, 0.1901969000, 0.5400563000", \ - "0.0378492000, 0.0404618000, 0.0471047000, 0.0599947000, 0.0922326000, 0.1932528000, 0.5402732000", \ - "0.0579343000, 0.0610567000, 0.0687738000, 0.0858248000, 0.1185401000, 0.2116261000, 0.5420129000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0332541000, 0.0375472000, 0.0491762000, 0.0812410000, 0.1784309000, 0.4940043000, 1.5034103000", \ - "0.0331469000, 0.0375600000, 0.0493733000, 0.0813487000, 0.1780468000, 0.4940590000, 1.4982217000", \ - "0.0333305000, 0.0376387000, 0.0493647000, 0.0811995000, 0.1783476000, 0.4946384000, 1.5045550000", \ - "0.0331339000, 0.0373480000, 0.0493358000, 0.0812025000, 0.1779507000, 0.4948505000, 1.5053677000", \ - "0.0346116000, 0.0387788000, 0.0505051000, 0.0821550000, 0.1785512000, 0.4947778000, 1.5038689000", \ - "0.0412924000, 0.0458149000, 0.0574656000, 0.0884965000, 0.1830236000, 0.4955324000, 1.5052884000", \ - "0.0564220000, 0.0618807000, 0.0742924000, 0.1039844000, 0.1926223000, 0.4984053000, 1.4985103000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.1541259000, 0.1581048000, 0.1680454000, 0.1893817000, 0.2326256000, 0.3294033000, 0.5979630000", \ - "0.1592916000, 0.1633346000, 0.1732601000, 0.1946914000, 0.2378475000, 0.3347196000, 0.6032954000", \ - "0.1723337000, 0.1762696000, 0.1869552000, 0.2082769000, 0.2515363000, 0.3483475000, 0.6169517000", \ - "0.2043840000, 0.2084040000, 0.2184049000, 0.2403817000, 0.2833323000, 0.3802187000, 0.6487888000", \ - "0.2809949000, 0.2849415000, 0.2948974000, 0.3154937000, 0.3586240000, 0.4556439000, 0.7237134000", \ - "0.4372470000, 0.4419522000, 0.4536868000, 0.4778923000, 0.5244801000, 0.6217516000, 0.8900526000", \ - "0.6940447000, 0.7001897000, 0.7162710000, 0.7480143000, 0.8070514000, 0.9165527000, 1.1877505000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.1553608000, 0.1609084000, 0.1750701000, 0.2082713000, 0.2882770000, 0.5120337000, 1.2045231000", \ - "0.1593475000, 0.1648605000, 0.1790961000, 0.2122582000, 0.2922585000, 0.5162669000, 1.2056450000", \ - "0.1670194000, 0.1725246000, 0.1866870000, 0.2200300000, 0.3000288000, 0.5234645000, 1.2133586000", \ - "0.1819304000, 0.1874514000, 0.2017362000, 0.2350301000, 0.3150469000, 0.5384267000, 1.2288829000", \ - "0.2135801000, 0.2192572000, 0.2338182000, 0.2674184000, 0.3476986000, 0.5715142000, 1.2615533000", \ - "0.2641577000, 0.2703734000, 0.2863338000, 0.3221203000, 0.4048085000, 0.6296230000, 1.3204310000", \ - "0.3174393000, 0.3250990000, 0.3444294000, 0.3857208000, 0.4732111000, 0.6992401000, 1.3897821000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0282305000, 0.0305652000, 0.0363489000, 0.0510150000, 0.0860878000, 0.1909712000, 0.5407793000", \ - "0.0282655000, 0.0305642000, 0.0364086000, 0.0511230000, 0.0861068000, 0.1912622000, 0.5407899000", \ - "0.0284910000, 0.0309028000, 0.0364074000, 0.0510426000, 0.0861183000, 0.1910046000, 0.5407474000", \ - "0.0281938000, 0.0305044000, 0.0363651000, 0.0506674000, 0.0861339000, 0.1910671000, 0.5407613000", \ - "0.0282866000, 0.0305193000, 0.0364490000, 0.0507111000, 0.0862581000, 0.1909182000, 0.5381683000", \ - "0.0381976000, 0.0408877000, 0.0464297000, 0.0598239000, 0.0918666000, 0.1943261000, 0.5409584000", \ - "0.0585175000, 0.0617949000, 0.0691604000, 0.0853771000, 0.1178983000, 0.2109724000, 0.5422597000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015596100, 0.0048647800, 0.0151743000, 0.0473321000, 0.1476390000, 0.4605200000"); - values("0.0332883000, 0.0375716000, 0.0493272000, 0.0814981000, 0.1780927000, 0.4942314000, 1.5019388000", \ - "0.0334061000, 0.0376925000, 0.0493521000, 0.0813195000, 0.1781954000, 0.4946710000, 1.5030206000", \ - "0.0333705000, 0.0375198000, 0.0491262000, 0.0813299000, 0.1783351000, 0.4931838000, 1.4994070000", \ - "0.0331975000, 0.0374428000, 0.0492230000, 0.0812545000, 0.1784421000, 0.4941853000, 1.4979743000", \ - "0.0345903000, 0.0387525000, 0.0503200000, 0.0822880000, 0.1786432000, 0.4932084000, 1.5001340000", \ - "0.0394524000, 0.0441186000, 0.0557485000, 0.0881163000, 0.1823349000, 0.4953749000, 1.5021503000", \ - "0.0527957000, 0.0573827000, 0.0702949000, 0.1012600000, 0.1916096000, 0.4979865000, 1.4959464000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4_1") { - leakage_power () { - value : 0.0033794000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0033726000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0033985000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0033794000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0034023000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0033811000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0037379000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0034026000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0034086000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0033868000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0037718000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0034089000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0037989000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0034148000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0019642000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0037953000; - when : "A&B&C&!D"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__and4"; - cell_leakage_power : 0.0034001940; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028536000, 0.0028540000, 0.0028550000, 0.0028538000, 0.0028511000, 0.0028448000, 0.0028302000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002227600, -0.002229600, -0.002234300, -0.002230200, -0.002220600, -0.002198700, -0.002148100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015510000; - } - pin ("B") { - capacitance : 0.0015500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024024000, 0.0024004000, 0.0023959000, 0.0024046000, 0.0024246000, 0.0024708000, 0.0025773000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002193500, -0.002186300, -0.002169600, -0.002169600, -0.002169600, -0.002169700, -0.002169800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015770000; - } - pin ("C") { - capacitance : 0.0015410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019154000, 0.0019157000, 0.0019166000, 0.0019164000, 0.0019159000, 0.0019147000, 0.0019121000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001919100, -0.001918400, -0.001916700, -0.001916400, -0.001915500, -0.001913500, -0.001909000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015720000; - } - pin ("D") { - capacitance : 0.0015660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021820000, 0.0021786000, 0.0021707000, 0.0021708000, 0.0021711000, 0.0021718000, 0.0021735000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002162700, -0.002163700, -0.002166100, -0.002166300, -0.002166700, -0.002167700, -0.002170000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016230000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0077931000, 0.0067601000, 0.0039696000, -0.004233200, -0.027361000, -0.088864000, -0.250149700", \ - "0.0077289000, 0.0067047000, 0.0039403000, -0.004305400, -0.027462500, -0.088893800, -0.250244100", \ - "0.0075167000, 0.0065274000, 0.0037375000, -0.004486200, -0.027592700, -0.089089200, -0.250392100", \ - "0.0073004000, 0.0062658000, 0.0034772000, -0.004778100, -0.027863700, -0.089329100, -0.250648700", \ - "0.0071691000, 0.0061463000, 0.0032682000, -0.004996800, -0.028083100, -0.089482400, -0.250736700", \ - "0.0081069000, 0.0067355000, 0.0033439000, -0.005351700, -0.028216100, -0.089556300, -0.250741000", \ - "0.0092780000, 0.0078849000, 0.0044001000, -0.004549000, -0.027900600, -0.089096800, -0.250205500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0102741000, 0.0116720000, 0.0153171000, 0.0244465000, 0.0477430000, 0.1086676000, 0.2685155000", \ - "0.0102327000, 0.0116246000, 0.0152536000, 0.0243285000, 0.0477942000, 0.1088480000, 0.2684708000", \ - "0.0101022000, 0.0115101000, 0.0151414000, 0.0242685000, 0.0476466000, 0.1085435000, 0.2684881000", \ - "0.0099705000, 0.0113690000, 0.0150031000, 0.0241335000, 0.0474485000, 0.1084268000, 0.2683678000", \ - "0.0099121000, 0.0112915000, 0.0147960000, 0.0238646000, 0.0472803000, 0.1083203000, 0.2686257000", \ - "0.0104828000, 0.0117639000, 0.0151786000, 0.0239162000, 0.0473474000, 0.1080347000, 0.2684710000", \ - "0.0111498000, 0.0125672000, 0.0159515000, 0.0248887000, 0.0477511000, 0.1088753000, 0.2673818000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0094108000, 0.0083780000, 0.0056144000, -0.002539100, -0.025565700, -0.086971400, -0.248237300", \ - "0.0093477000, 0.0083187000, 0.0055515000, -0.002605600, -0.025625300, -0.087043000, -0.248310700", \ - "0.0092545000, 0.0082100000, 0.0054228000, -0.002730300, -0.025757800, -0.087159400, -0.248449800", \ - "0.0089906000, 0.0079396000, 0.0051753000, -0.003019700, -0.026016600, -0.087413700, -0.248667500", \ - "0.0090007000, 0.0079131000, 0.0050767000, -0.003169100, -0.026215100, -0.087573600, -0.248807700", \ - "0.0091685000, 0.0078425000, 0.0045124000, -0.003519800, -0.026362000, -0.087684400, -0.248894800", \ - "0.0108899000, 0.0095025000, 0.0060051000, -0.002981800, -0.026356700, -0.087560700, -0.248649500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0104807000, 0.0118784000, 0.0155041000, 0.0246404000, 0.0479453000, 0.1088038000, 0.2698716000", \ - "0.0104496000, 0.0118358000, 0.0154814000, 0.0245924000, 0.0479004000, 0.1087546000, 0.2684291000", \ - "0.0103550000, 0.0117509000, 0.0153931000, 0.0244449000, 0.0478522000, 0.1087934000, 0.2685872000", \ - "0.0102127000, 0.0116057000, 0.0152523000, 0.0243511000, 0.0476780000, 0.1092481000, 0.2697894000", \ - "0.0102604000, 0.0116270000, 0.0151432000, 0.0242252000, 0.0475929000, 0.1085779000, 0.2684614000", \ - "0.0105452000, 0.0118558000, 0.0152992000, 0.0241608000, 0.0474126000, 0.1082526000, 0.2683713000", \ - "0.0109953000, 0.0122356000, 0.0156286000, 0.0246263000, 0.0479771000, 0.1090520000, 0.2672906000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0111669000, 0.0101424000, 0.0074125000, -0.000679900, -0.023605000, -0.084960800, -0.246154200", \ - "0.0111505000, 0.0100979000, 0.0072915000, -0.000786500, -0.023703100, -0.085038100, -0.246233400", \ - "0.0110044000, 0.0099633000, 0.0072211000, -0.000894700, -0.023809800, -0.085146100, -0.246338000", \ - "0.0108422000, 0.0097857000, 0.0070248000, -0.001107500, -0.024033900, -0.085325700, -0.246513700", \ - "0.0107689000, 0.0096819000, 0.0069023000, -0.001247100, -0.024234700, -0.085510700, -0.246653000", \ - "0.0107315000, 0.0095077000, 0.0067549000, -0.001334200, -0.024265700, -0.085514100, -0.246619400", \ - "0.0131609000, 0.0117735000, 0.0082845000, -0.000683000, -0.024080600, -0.085246700, -0.246303400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0102626000, 0.0116650000, 0.0152891000, 0.0243450000, 0.0476530000, 0.1085208000, 0.2681352000", \ - "0.0102043000, 0.0115897000, 0.0152119000, 0.0243497000, 0.0476288000, 0.1084191000, 0.2694193000", \ - "0.0101256000, 0.0115403000, 0.0151705000, 0.0242870000, 0.0475730000, 0.1083647000, 0.2693878000", \ - "0.0100282000, 0.0114323000, 0.0150588000, 0.0241614000, 0.0474533000, 0.1084081000, 0.2678750000", \ - "0.0099745000, 0.0113375000, 0.0149281000, 0.0240271000, 0.0473930000, 0.1083539000, 0.2685471000", \ - "0.0102838000, 0.0116231000, 0.0150741000, 0.0238783000, 0.0472017000, 0.1081476000, 0.2693164000", \ - "0.0106106000, 0.0118938000, 0.0152962000, 0.0244172000, 0.0477543000, 0.1088093000, 0.2670653000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0123486000, 0.0112876000, 0.0085168000, 0.0003668000, -0.022661700, -0.084030800, -0.245241900", \ - "0.0122696000, 0.0112093000, 0.0084963000, 0.0002797000, -0.022735200, -0.084106700, -0.245310900", \ - "0.0121483000, 0.0110880000, 0.0083563000, 0.0001695000, -0.022816700, -0.084200800, -0.245423500", \ - "0.0120284000, 0.0109974000, 0.0081826000, 2.990000e-05, -0.022959100, -0.084319400, -0.245506700", \ - "0.0120219000, 0.0109446000, 0.0081249000, -5.03000e-05, -0.023111200, -0.084426900, -0.245601300", \ - "0.0120762000, 0.0109531000, 0.0081853000, 2.490000e-05, -0.022967300, -0.084301600, -0.245450800", \ - "0.0147561000, 0.0133574000, 0.0098256000, 0.0008096000, -0.022794100, -0.084047800, -0.245189100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0104433000, 0.0118392000, 0.0154797000, 0.0245382000, 0.0478820000, 0.1086887000, 0.2683096000", \ - "0.0103979000, 0.0117961000, 0.0153781000, 0.0244760000, 0.0478045000, 0.1085026000, 0.2694742000", \ - "0.0103225000, 0.0117037000, 0.0153287000, 0.0244677000, 0.0477228000, 0.1084538000, 0.2693532000", \ - "0.0101880000, 0.0115808000, 0.0152210000, 0.0243347000, 0.0476191000, 0.1089731000, 0.2695201000", \ - "0.0100835000, 0.0114717000, 0.0150622000, 0.0241414000, 0.0474883000, 0.1084315000, 0.2671038000", \ - "0.0104402000, 0.0117324000, 0.0152229000, 0.0240454000, 0.0473890000, 0.1081919000, 0.2691792000", \ - "0.0107538000, 0.0120456000, 0.0156188000, 0.0244862000, 0.0476913000, 0.1087444000, 0.2671058000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5027250000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1122445000, 0.1187579000, 0.1321894000, 0.1583718000, 0.2114639000, 0.3348840000, 0.6522878000", \ - "0.1174052000, 0.1239165000, 0.1373688000, 0.1635160000, 0.2169045000, 0.3400554000, 0.6571486000", \ - "0.1302705000, 0.1367903000, 0.1500662000, 0.1762541000, 0.2294850000, 0.3528058000, 0.6699389000", \ - "0.1611011000, 0.1677079000, 0.1811595000, 0.2072562000, 0.2604533000, 0.3838600000, 0.7011785000", \ - "0.2320432000, 0.2393098000, 0.2529982000, 0.2794724000, 0.3329383000, 0.4564749000, 0.7740647000", \ - "0.3545692000, 0.3633736000, 0.3807194000, 0.4118880000, 0.4698522000, 0.5952818000, 0.9081939000", \ - "0.5457734000, 0.5571226000, 0.5800760000, 0.6203836000, 0.6881268000, 0.8195566000, 1.1337354000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1229093000, 0.1328418000, 0.1539556000, 0.1979537000, 0.2961481000, 0.5430635000, 1.1855353000", \ - "0.1264385000, 0.1364274000, 0.1575197000, 0.2014821000, 0.2996844000, 0.5455315000, 1.1904919000", \ - "0.1351892000, 0.1451990000, 0.1662893000, 0.2103262000, 0.3086558000, 0.5551936000, 1.1969816000", \ - "0.1575042000, 0.1673554000, 0.1885501000, 0.2324012000, 0.3305553000, 0.5773372000, 1.2187362000", \ - "0.2020452000, 0.2121717000, 0.2333118000, 0.2779617000, 0.3764470000, 0.6225588000, 1.2666247000", \ - "0.2613347000, 0.2727816000, 0.2954147000, 0.3414937000, 0.4415567000, 0.6904594000, 1.3344522000", \ - "0.3194185000, 0.3348757000, 0.3636750000, 0.4156391000, 0.5160587000, 0.7647588000, 1.4074987000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0230153000, 0.0273933000, 0.0375764000, 0.0602611000, 0.1159653000, 0.2704480000, 0.6896262000", \ - "0.0227439000, 0.0271729000, 0.0373580000, 0.0602173000, 0.1162845000, 0.2714932000, 0.6891205000", \ - "0.0226762000, 0.0271153000, 0.0376167000, 0.0603734000, 0.1163159000, 0.2703781000, 0.6891037000", \ - "0.0229755000, 0.0273636000, 0.0374942000, 0.0600221000, 0.1162153000, 0.2719713000, 0.6872388000", \ - "0.0252823000, 0.0294092000, 0.0388298000, 0.0613460000, 0.1167268000, 0.2713884000, 0.6846519000", \ - "0.0358809000, 0.0409745000, 0.0510165000, 0.0723435000, 0.1251293000, 0.2737038000, 0.6851679000", \ - "0.0530833000, 0.0592555000, 0.0721349000, 0.0948041000, 0.1454356000, 0.2829941000, 0.6889062000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0347676000, 0.0430121000, 0.0620852000, 0.1093335000, 0.2355327000, 0.5812804000, 1.4955743000", \ - "0.0345489000, 0.0429431000, 0.0621503000, 0.1093891000, 0.2355162000, 0.5800395000, 1.4956031000", \ - "0.0345727000, 0.0429264000, 0.0619894000, 0.1090856000, 0.2349771000, 0.5815222000, 1.4935819000", \ - "0.0346310000, 0.0429771000, 0.0621176000, 0.1092447000, 0.2350102000, 0.5817296000, 1.4955230000", \ - "0.0367352000, 0.0448231000, 0.0644363000, 0.1111074000, 0.2360553000, 0.5803500000, 1.4973409000", \ - "0.0449389000, 0.0526651000, 0.0716052000, 0.1159187000, 0.2396107000, 0.5809550000, 1.5000329000", \ - "0.0617510000, 0.0706003000, 0.0885120000, 0.1290345000, 0.2448195000, 0.5851440000, 1.4931134000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1352758000, 0.1422235000, 0.1563801000, 0.1832850000, 0.2377837000, 0.3616641000, 0.6788962000", \ - "0.1407778000, 0.1477291000, 0.1618900000, 0.1886473000, 0.2430680000, 0.3671047000, 0.6848789000", \ - "0.1537306000, 0.1606538000, 0.1747854000, 0.2018012000, 0.2562568000, 0.3802131000, 0.6976306000", \ - "0.1851020000, 0.1920074000, 0.2062195000, 0.2333471000, 0.2877798000, 0.4118076000, 0.7295208000", \ - "0.2596960000, 0.2666040000, 0.2807012000, 0.3079503000, 0.3623221000, 0.4865142000, 0.8040173000", \ - "0.4044050000, 0.4129758000, 0.4299407000, 0.4607799000, 0.5172133000, 0.6427341000, 0.9604906000", \ - "0.6365563000, 0.6479912000, 0.6705569000, 0.7101458000, 0.7770046000, 0.9079237000, 1.2261714000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1341481000, 0.1440997000, 0.1653178000, 0.2091996000, 0.3073470000, 0.5531747000, 1.1945258000", \ - "0.1381766000, 0.1480933000, 0.1692742000, 0.2131842000, 0.3113446000, 0.5572007000, 1.1983246000", \ - "0.1467571000, 0.1567420000, 0.1778616000, 0.2217092000, 0.3197755000, 0.5660269000, 1.2091832000", \ - "0.1663281000, 0.1763365000, 0.1974126000, 0.2413222000, 0.3395347000, 0.5862785000, 1.2355442000", \ - "0.2060114000, 0.2163281000, 0.2381108000, 0.2827228000, 0.3810978000, 0.6273945000, 1.2686987000", \ - "0.2629478000, 0.2746064000, 0.2981965000, 0.3446134000, 0.4449840000, 0.6926102000, 1.3338288000", \ - "0.3158214000, 0.3308510000, 0.3600252000, 0.4123687000, 0.5155933000, 0.7632041000, 1.4065464000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0249698000, 0.0295148000, 0.0400504000, 0.0627383000, 0.1186073000, 0.2719021000, 0.6840716000", \ - "0.0249542000, 0.0294879000, 0.0395060000, 0.0629903000, 0.1187001000, 0.2714478000, 0.6930481000", \ - "0.0250199000, 0.0295874000, 0.0395200000, 0.0628790000, 0.1186096000, 0.2719298000, 0.6850081000", \ - "0.0250067000, 0.0295705000, 0.0399986000, 0.0624537000, 0.1185998000, 0.2718271000, 0.6934393000", \ - "0.0258313000, 0.0303203000, 0.0403093000, 0.0630364000, 0.1188625000, 0.2726318000, 0.6877415000", \ - "0.0359729000, 0.0402476000, 0.0502941000, 0.0723590000, 0.1245074000, 0.2745060000, 0.6909893000", \ - "0.0522190000, 0.0587695000, 0.0712212000, 0.0932515000, 0.1434140000, 0.2826161000, 0.6899795000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0348013000, 0.0431594000, 0.0623067000, 0.1092253000, 0.2354716000, 0.5811052000, 1.5000960000", \ - "0.0348766000, 0.0430721000, 0.0623071000, 0.1092183000, 0.2354712000, 0.5811161000, 1.4998804000", \ - "0.0346343000, 0.0429636000, 0.0620991000, 0.1092872000, 0.2351554000, 0.5800611000, 1.4952044000", \ - "0.0345605000, 0.0429384000, 0.0620192000, 0.1091369000, 0.2354279000, 0.5818186000, 1.5027247000", \ - "0.0372749000, 0.0453095000, 0.0643514000, 0.1110819000, 0.2357035000, 0.5812383000, 1.5001294000", \ - "0.0436047000, 0.0519616000, 0.0706187000, 0.1155730000, 0.2393161000, 0.5814936000, 1.4943023000", \ - "0.0590995000, 0.0683562000, 0.0875524000, 0.1291202000, 0.2451142000, 0.5849723000, 1.4918401000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1493024000, 0.1564982000, 0.1710311000, 0.1985001000, 0.2537124000, 0.3785527000, 0.6960182000", \ - "0.1545121000, 0.1616249000, 0.1763227000, 0.2038134000, 0.2590236000, 0.3838393000, 0.7011811000", \ - "0.1680556000, 0.1752504000, 0.1898240000, 0.2176572000, 0.2725727000, 0.3973664000, 0.7156534000", \ - "0.1998228000, 0.2069610000, 0.2215100000, 0.2492145000, 0.3044339000, 0.4289902000, 0.7470152000", \ - "0.2759012000, 0.2830068000, 0.2975085000, 0.3252822000, 0.3804865000, 0.5053958000, 0.8236524000", \ - "0.4311347000, 0.4397007000, 0.4563857000, 0.4868516000, 0.5440541000, 0.6696462000, 0.9877048000", \ - "0.6843677000, 0.6956705000, 0.7177495000, 0.7566409000, 0.8223595000, 0.9533226000, 1.2710042000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1405070000, 0.1504995000, 0.1715673000, 0.2154608000, 0.3134283000, 0.5594763000, 1.2005655000", \ - "0.1446089000, 0.1545100000, 0.1757166000, 0.2195974000, 0.3176464000, 0.5632252000, 1.2045799000", \ - "0.1529105000, 0.1629008000, 0.1840313000, 0.2279482000, 0.3260559000, 0.5719771000, 1.2129557000", \ - "0.1698479000, 0.1798546000, 0.2009299000, 0.2447403000, 0.3429488000, 0.5887754000, 1.2301276000", \ - "0.2029320000, 0.2133584000, 0.2350956000, 0.2796150000, 0.3779390000, 0.6241163000, 1.2699236000", \ - "0.2533790000, 0.2648075000, 0.2880749000, 0.3350556000, 0.4354046000, 0.6825093000, 1.3299890000", \ - "0.2998933000, 0.3145833000, 0.3431927000, 0.3956840000, 0.4992909000, 0.7471315000, 1.3888813000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0263252000, 0.0309732000, 0.0415054000, 0.0646640000, 0.1201093000, 0.2728104000, 0.6907584000", \ - "0.0267558000, 0.0311010000, 0.0415754000, 0.0644371000, 0.1199453000, 0.2727055000, 0.6914090000", \ - "0.0265560000, 0.0313521000, 0.0413145000, 0.0638816000, 0.1198338000, 0.2734761000, 0.6932363000", \ - "0.0264527000, 0.0309926000, 0.0416440000, 0.0641850000, 0.1201098000, 0.2729902000, 0.6857790000", \ - "0.0265757000, 0.0312681000, 0.0413900000, 0.0642503000, 0.1201323000, 0.2732298000, 0.6932377000", \ - "0.0348081000, 0.0396282000, 0.0495085000, 0.0707473000, 0.1242511000, 0.2736893000, 0.6922128000", \ - "0.0513325000, 0.0576037000, 0.0695613000, 0.0912320000, 0.1414475000, 0.2825027000, 0.6918355000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0346001000, 0.0429280000, 0.0621690000, 0.1090936000, 0.2352391000, 0.5818518000, 1.4975753000", \ - "0.0347219000, 0.0431434000, 0.0623150000, 0.1092302000, 0.2354882000, 0.5810741000, 1.5004112000", \ - "0.0349183000, 0.0428807000, 0.0621962000, 0.1091630000, 0.2353343000, 0.5813747000, 1.5014089000", \ - "0.0346467000, 0.0428869000, 0.0621332000, 0.1091148000, 0.2351249000, 0.5816356000, 1.4920992000", \ - "0.0369422000, 0.0449261000, 0.0638420000, 0.1106445000, 0.2355211000, 0.5814162000, 1.5010712000", \ - "0.0422568000, 0.0512740000, 0.0705815000, 0.1156264000, 0.2389766000, 0.5815646000, 1.5002627000", \ - "0.0566621000, 0.0661062000, 0.0853208000, 0.1293553000, 0.2453943000, 0.5838158000, 1.4929037000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1590220000, 0.1662932000, 0.1810145000, 0.2088693000, 0.2641725000, 0.3893211000, 0.7075475000", \ - "0.1641868000, 0.1714548000, 0.1859562000, 0.2141195000, 0.2694028000, 0.3945016000, 0.7128139000", \ - "0.1768762000, 0.1841348000, 0.1996916000, 0.2277226000, 0.2829918000, 0.4080932000, 0.7268424000", \ - "0.2098036000, 0.2169632000, 0.2316327000, 0.2596654000, 0.3151561000, 0.4402852000, 0.7591319000", \ - "0.2864395000, 0.2935898000, 0.3082524000, 0.3362566000, 0.3917386000, 0.5170082000, 0.8355220000", \ - "0.4476517000, 0.4560964000, 0.4724918000, 0.5027083000, 0.5595430000, 0.6853127000, 1.0035373000", \ - "0.7138391000, 0.7248878000, 0.7468793000, 0.7844748000, 0.8495115000, 0.9796921000, 1.2981620000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1465466000, 0.1565317000, 0.1776552000, 0.2215045000, 0.3193205000, 0.5648633000, 1.2074978000", \ - "0.1507670000, 0.1607347000, 0.1817659000, 0.2256817000, 0.3235963000, 0.5686792000, 1.2119520000", \ - "0.1586966000, 0.1685789000, 0.1897998000, 0.2336814000, 0.3316581000, 0.5769231000, 1.2181856000", \ - "0.1737676000, 0.1837912000, 0.2048572000, 0.2486763000, 0.3467696000, 0.5929540000, 1.2398964000", \ - "0.2011553000, 0.2114798000, 0.2330897000, 0.2774379000, 0.3756618000, 0.6214335000, 1.2636564000", \ - "0.2424201000, 0.2536444000, 0.2767951000, 0.3234651000, 0.4236556000, 0.6704138000, 1.3188990000", \ - "0.2827737000, 0.2966853000, 0.3242588000, 0.3760208000, 0.4796689000, 0.7271770000, 1.3689962000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0274755000, 0.0321472000, 0.0429408000, 0.0654848000, 0.1212444000, 0.2737288000, 0.6901529000", \ - "0.0274665000, 0.0321264000, 0.0426408000, 0.0654901000, 0.1211230000, 0.2737708000, 0.6965167000", \ - "0.0274476000, 0.0320810000, 0.0428291000, 0.0657402000, 0.1216016000, 0.2737870000, 0.6910748000", \ - "0.0274560000, 0.0326405000, 0.0425274000, 0.0657971000, 0.1214629000, 0.2738721000, 0.6927491000", \ - "0.0277832000, 0.0323062000, 0.0429448000, 0.0653616000, 0.1213427000, 0.2738193000, 0.6944987000", \ - "0.0345371000, 0.0392699000, 0.0494064000, 0.0706627000, 0.1239397000, 0.2742984000, 0.6888127000", \ - "0.0510530000, 0.0572341000, 0.0684165000, 0.0902673000, 0.1401277000, 0.2822385000, 0.6907221000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0346152000, 0.0429627000, 0.0620999000, 0.1092458000, 0.2353127000, 0.5796004000, 1.4958100000", \ - "0.0347670000, 0.0430365000, 0.0622710000, 0.1092245000, 0.2355468000, 0.5806889000, 1.4970030000", \ - "0.0347556000, 0.0431686000, 0.0623166000, 0.1092264000, 0.2355161000, 0.5809868000, 1.5005552000", \ - "0.0345568000, 0.0430102000, 0.0620664000, 0.1091443000, 0.2351501000, 0.5817535000, 1.5026038000", \ - "0.0362504000, 0.0444551000, 0.0634717000, 0.1104267000, 0.2357382000, 0.5805414000, 1.4999176000", \ - "0.0406243000, 0.0494148000, 0.0687683000, 0.1149311000, 0.2385613000, 0.5814871000, 1.4986673000", \ - "0.0521487000, 0.0619329000, 0.0824527000, 0.1261088000, 0.2447737000, 0.5828880000, 1.4888427000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4_2") { - leakage_power () { - value : 0.0034361000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0034293000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0034555000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0034364000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0034597000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0034381000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0037988000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0034609000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0034660000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0034439000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0038356000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0034673000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0038674000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0034733000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0023631000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0038733000; - when : "A&B&C&!D"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__and4"; - cell_leakage_power : 0.0034815480; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028438000, 0.0028443000, 0.0028454000, 0.0028458000, 0.0028465000, 0.0028483000, 0.0028523000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002204700, -0.002207900, -0.002215200, -0.002210900, -0.002201000, -0.002178200, -0.002125700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015100000; - } - pin ("B") { - capacitance : 0.0015240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023960000, 0.0023930000, 0.0023861000, 0.0023947000, 0.0024145000, 0.0024602000, 0.0025655000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002164600, -0.002162600, -0.002157800, -0.002158000, -0.002158400, -0.002159200, -0.002161200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015510000; - } - pin ("C") { - capacitance : 0.0015200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019128000, 0.0019131000, 0.0019140000, 0.0019137000, 0.0019130000, 0.0019115000, 0.0019081000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001919200, -0.001915200, -0.001906000, -0.001905900, -0.001905500, -0.001904700, -0.001902700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015510000; - } - pin ("D") { - capacitance : 0.0015370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021528000, 0.0021531000, 0.0021538000, 0.0021538000, 0.0021540000, 0.0021543000, 0.0021550000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002148500, -0.002149600, -0.002152000, -0.002152200, -0.002152700, -0.002154000, -0.002156800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015930000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0110362000, 0.0094787000, 0.0057099000, -0.005682000, -0.041889600, -0.151072000, -0.469922600", \ - "0.0109912000, 0.0095155000, 0.0057127000, -0.005602600, -0.041917300, -0.151120500, -0.469968100", \ - "0.0108474000, 0.0093802000, 0.0055626000, -0.005843900, -0.042053100, -0.151255000, -0.470107800", \ - "0.0106175000, 0.0091906000, 0.0053401000, -0.006057400, -0.042333400, -0.151496400, -0.470338100", \ - "0.0103794000, 0.0089079000, 0.0050518000, -0.006450600, -0.042667700, -0.151786100, -0.470614100", \ - "0.0106031000, 0.0089480000, 0.0046913000, -0.006712900, -0.043027800, -0.152044900, -0.470569500", \ - "0.0148535000, 0.0130494000, 0.0082078000, -0.005012100, -0.042426600, -0.151620400, -0.469953500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0150321000, 0.0166030000, 0.0212820000, 0.0347874000, 0.0725678000, 0.1812905000, 0.4973927000", \ - "0.0150492000, 0.0166072000, 0.0212959000, 0.0348429000, 0.0727180000, 0.1812514000, 0.4976965000", \ - "0.0148783000, 0.0164388000, 0.0212035000, 0.0347149000, 0.0725260000, 0.1812928000, 0.4944704000", \ - "0.0147291000, 0.0162649000, 0.0210126000, 0.0345673000, 0.0723863000, 0.1810250000, 0.4970241000", \ - "0.0148215000, 0.0163912000, 0.0209719000, 0.0343137000, 0.0721488000, 0.1808141000, 0.4970785000", \ - "0.0153544000, 0.0168151000, 0.0210696000, 0.0344349000, 0.0720473000, 0.1799597000, 0.4988728000", \ - "0.0170375000, 0.0184632000, 0.0229878000, 0.0357307000, 0.0729858000, 0.1808353000, 0.4981379000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0127271000, 0.0112044000, 0.0073036000, -0.004026600, -0.040160200, -0.149294200, -0.468085700", \ - "0.0125565000, 0.0110670000, 0.0073539000, -0.004179500, -0.040241100, -0.149330600, -0.468115300", \ - "0.0125595000, 0.0110441000, 0.0071574000, -0.004114900, -0.040397900, -0.149419400, -0.468214200", \ - "0.0123172000, 0.0107977000, 0.0068690000, -0.004479400, -0.040577400, -0.149658600, -0.468434600", \ - "0.0121158000, 0.0106238000, 0.0067612000, -0.004739600, -0.040968100, -0.149941300, -0.468670100", \ - "0.0121819000, 0.0106297000, 0.0064965000, -0.005050000, -0.041298100, -0.150237400, -0.468835600", \ - "0.0164830000, 0.0146890000, 0.0103625000, -0.002893300, -0.040626300, -0.149745400, -0.468241200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0151901000, 0.0167452000, 0.0214126000, 0.0349980000, 0.0727863000, 0.1815463000, 0.4996279000", \ - "0.0151801000, 0.0168214000, 0.0214715000, 0.0350080000, 0.0725906000, 0.1813004000, 0.4971458000", \ - "0.0151116000, 0.0167594000, 0.0214209000, 0.0349454000, 0.0728306000, 0.1813144000, 0.4976570000", \ - "0.0150118000, 0.0165220000, 0.0212509000, 0.0347017000, 0.0726097000, 0.1812749000, 0.4965114000", \ - "0.0149888000, 0.0165355000, 0.0211268000, 0.0346455000, 0.0724873000, 0.1810680000, 0.4969946000", \ - "0.0155035000, 0.0169709000, 0.0212758000, 0.0343874000, 0.0717363000, 0.1806358000, 0.4975139000", \ - "0.0167544000, 0.0181910000, 0.0224394000, 0.0354850000, 0.0731945000, 0.1818987000, 0.4981157000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0143985000, 0.0130375000, 0.0091195000, -0.002326900, -0.038326400, -0.147315800, -0.466027100", \ - "0.0143574000, 0.0128499000, 0.0089889000, -0.002267800, -0.038425500, -0.147358200, -0.466074300", \ - "0.0142612000, 0.0127639000, 0.0088969000, -0.002374400, -0.038488900, -0.147482100, -0.466186000", \ - "0.0141413000, 0.0126575000, 0.0087467000, -0.002618200, -0.038724500, -0.147664300, -0.466322500", \ - "0.0139708000, 0.0124645000, 0.0085698000, -0.002895900, -0.038975600, -0.147882400, -0.466503000", \ - "0.0143946000, 0.0127227000, 0.0086634000, -0.002934500, -0.039156700, -0.148017100, -0.466533700", \ - "0.0186738000, 0.0168582000, 0.0119870000, -0.001247700, -0.039009000, -0.147954600, -0.466368000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0150361000, 0.0165970000, 0.0213546000, 0.0347061000, 0.0724523000, 0.1811043000, 0.4971996000", \ - "0.0149458000, 0.0165046000, 0.0211513000, 0.0346658000, 0.0725396000, 0.1812386000, 0.4992165000", \ - "0.0149165000, 0.0164777000, 0.0211944000, 0.0346704000, 0.0724323000, 0.1810357000, 0.4970404000", \ - "0.0147727000, 0.0163288000, 0.0211069000, 0.0344995000, 0.0724083000, 0.1809439000, 0.4969102000", \ - "0.0147763000, 0.0163313000, 0.0209313000, 0.0344798000, 0.0722859000, 0.1808019000, 0.4968095000", \ - "0.0154889000, 0.0169914000, 0.0213428000, 0.0342710000, 0.0719086000, 0.1808168000, 0.4969022000", \ - "0.0165391000, 0.0179895000, 0.0223831000, 0.0352043000, 0.0724845000, 0.1811387000, 0.4980124000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0156492000, 0.0141255000, 0.0102430000, -0.001188000, -0.037387700, -0.146474300, -0.465176100", \ - "0.0155785000, 0.0140675000, 0.0101719000, -0.001177400, -0.037441300, -0.146527800, -0.465248000", \ - "0.0155478000, 0.0140292000, 0.0100945000, -0.001345800, -0.037551500, -0.146631500, -0.465345600", \ - "0.0154430000, 0.0139388000, 0.0100065000, -0.001437600, -0.037684700, -0.146743400, -0.465442500", \ - "0.0152466000, 0.0137293000, 0.0098315000, -0.001641200, -0.037851600, -0.146890900, -0.465558100", \ - "0.0159598000, 0.0143656000, 0.0103272000, -0.001143300, -0.037551900, -0.146677100, -0.465364800", \ - "0.0204206000, 0.0186350000, 0.0137981000, 9.150000e-05, -0.037809400, -0.146758700, -0.465335700"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0152054000, 0.0168191000, 0.0214699000, 0.0350000000, 0.0728619000, 0.1811963000, 0.4974811000", \ - "0.0151969000, 0.0168031000, 0.0214989000, 0.0349971000, 0.0728492000, 0.1811921000, 0.4996951000", \ - "0.0151352000, 0.0166230000, 0.0212793000, 0.0348786000, 0.0726617000, 0.1812899000, 0.4991227000", \ - "0.0150057000, 0.0165836000, 0.0212566000, 0.0346457000, 0.0725619000, 0.1812544000, 0.4992347000", \ - "0.0149206000, 0.0164587000, 0.0211240000, 0.0344983000, 0.0723089000, 0.1809207000, 0.4968989000", \ - "0.0155825000, 0.0170134000, 0.0214937000, 0.0344759000, 0.0721927000, 0.1808010000, 0.4974373000", \ - "0.0161823000, 0.0176470000, 0.0220426000, 0.0351787000, 0.0728743000, 0.1812546000, 0.4953162000"); - } - } - max_capacitance : 0.3003030000; - max_transition : 1.5088210000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1439006000, 0.1498602000, 0.1631129000, 0.1893829000, 0.2404104000, 0.3545403000, 0.6604106000", \ - "0.1492820000, 0.1552104000, 0.1683628000, 0.1947434000, 0.2458399000, 0.3598492000, 0.6660071000", \ - "0.1625071000, 0.1684572000, 0.1815795000, 0.2076911000, 0.2590065000, 0.3729889000, 0.6791892000", \ - "0.1930727000, 0.1990569000, 0.2122190000, 0.2383452000, 0.2898161000, 0.4038004000, 0.7098170000", \ - "0.2669442000, 0.2728811000, 0.2859721000, 0.3120346000, 0.3634746000, 0.4776673000, 0.7836952000", \ - "0.4109409000, 0.4181891000, 0.4340591000, 0.4644262000, 0.5196815000, 0.6358923000, 0.9404197000", \ - "0.6392744000, 0.6486617000, 0.6693517000, 0.7090644000, 0.7774078000, 0.9043031000, 1.2101872000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1561482000, 0.1651011000, 0.1852611000, 0.2277625000, 0.3208165000, 0.5592614000, 1.2388742000", \ - "0.1599025000, 0.1688951000, 0.1892483000, 0.2316453000, 0.3247320000, 0.5628961000, 1.2459872000", \ - "0.1687122000, 0.1776380000, 0.1979405000, 0.2403890000, 0.3334426000, 0.5718336000, 1.2552758000", \ - "0.1910249000, 0.1999276000, 0.2204135000, 0.2627903000, 0.3559326000, 0.5939595000, 1.2756424000", \ - "0.2421129000, 0.2510226000, 0.2714529000, 0.3138282000, 0.4069419000, 0.6451224000, 1.3253989000", \ - "0.3213409000, 0.3315905000, 0.3534253000, 0.3982857000, 0.4938661000, 0.7341472000, 1.4202810000", \ - "0.4104822000, 0.4233424000, 0.4516707000, 0.5044405000, 0.6035923000, 0.8438069000, 1.5244942000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0263981000, 0.0302305000, 0.0385749000, 0.0573991000, 0.1032598000, 0.2311659000, 0.6304057000", \ - "0.0266860000, 0.0303039000, 0.0393077000, 0.0573474000, 0.1029063000, 0.2320449000, 0.6303764000", \ - "0.0264799000, 0.0303039000, 0.0392731000, 0.0580147000, 0.1027924000, 0.2318402000, 0.6298208000", \ - "0.0265101000, 0.0303104000, 0.0387402000, 0.0579819000, 0.1028447000, 0.2321086000, 0.6276972000", \ - "0.0268052000, 0.0303036000, 0.0392107000, 0.0582394000, 0.1027863000, 0.2317642000, 0.6321822000", \ - "0.0376236000, 0.0414724000, 0.0505867000, 0.0685665000, 0.1102590000, 0.2345935000, 0.6332410000", \ - "0.0571327000, 0.0622560000, 0.0733900000, 0.0950067000, 0.1371931000, 0.2528797000, 0.6317059000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0362225000, 0.0429598000, 0.0594175000, 0.0976664000, 0.2040689000, 0.5274232000, 1.5009899000", \ - "0.0365097000, 0.0428887000, 0.0589996000, 0.0976697000, 0.2037458000, 0.5287286000, 1.5054005000", \ - "0.0361992000, 0.0428236000, 0.0591364000, 0.0976563000, 0.2040688000, 0.5280417000, 1.4985820000", \ - "0.0362173000, 0.0428178000, 0.0590481000, 0.0976078000, 0.2039577000, 0.5288775000, 1.5034298000", \ - "0.0370996000, 0.0437412000, 0.0596934000, 0.0987082000, 0.2037963000, 0.5286497000, 1.5032291000", \ - "0.0457438000, 0.0522038000, 0.0677855000, 0.1049331000, 0.2091291000, 0.5307380000, 1.5043435000", \ - "0.0627884000, 0.0707378000, 0.0883733000, 0.1230427000, 0.2186402000, 0.5350209000, 1.4976378000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1696447000, 0.1760320000, 0.1901181000, 0.2175587000, 0.2704082000, 0.3861980000, 0.6927764000", \ - "0.1751309000, 0.1814905000, 0.1954735000, 0.2231991000, 0.2758755000, 0.3915683000, 0.6981745000", \ - "0.1886635000, 0.1949983000, 0.2090434000, 0.2366048000, 0.2892646000, 0.4050052000, 0.7116427000", \ - "0.2197822000, 0.2261768000, 0.2404011000, 0.2680092000, 0.3207739000, 0.4366294000, 0.7430783000", \ - "0.2955622000, 0.3018660000, 0.3158776000, 0.3433327000, 0.3965025000, 0.5123795000, 0.8187345000", \ - "0.4568396000, 0.4643051000, 0.4799469000, 0.5100706000, 0.5654033000, 0.6825607000, 0.9892752000", \ - "0.7239129000, 0.7334410000, 0.7541367000, 0.7929248000, 0.8616914000, 0.9884887000, 1.2975510000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1672908000, 0.1762155000, 0.1964777000, 0.2390384000, 0.3320599000, 0.5702577000, 1.2539146000", \ - "0.1713460000, 0.1804128000, 0.2007431000, 0.2431033000, 0.3361908000, 0.5740765000, 1.2562023000", \ - "0.1800765000, 0.1891515000, 0.2095169000, 0.2518646000, 0.3449682000, 0.5830697000, 1.2661077000", \ - "0.2000438000, 0.2088313000, 0.2293536000, 0.2716733000, 0.3647361000, 0.6030292000, 1.2893692000", \ - "0.2440360000, 0.2530667000, 0.2735815000, 0.3163118000, 0.4093832000, 0.6478560000, 1.3273100000", \ - "0.3165556000, 0.3266526000, 0.3490504000, 0.3931004000, 0.4892165000, 0.7289672000, 1.4121735000", \ - "0.3997439000, 0.4119913000, 0.4395710000, 0.4915705000, 0.5913746000, 0.8320482000, 1.5132361000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0294647000, 0.0332775000, 0.0421536000, 0.0610945000, 0.1069645000, 0.2347176000, 0.6340173000", \ - "0.0294643000, 0.0333601000, 0.0425699000, 0.0610501000, 0.1070634000, 0.2345870000, 0.6305958000", \ - "0.0293741000, 0.0332262000, 0.0419416000, 0.0611059000, 0.1068495000, 0.2341223000, 0.6335918000", \ - "0.0294389000, 0.0333093000, 0.0424638000, 0.0612801000, 0.1065162000, 0.2345385000, 0.6300439000", \ - "0.0293716000, 0.0332344000, 0.0419394000, 0.0608736000, 0.1064226000, 0.2344989000, 0.6306639000", \ - "0.0380494000, 0.0419897000, 0.0505133000, 0.0687001000, 0.1113247000, 0.2354973000, 0.6349700000", \ - "0.0577684000, 0.0628408000, 0.0736779000, 0.0952811000, 0.1364857000, 0.2513015000, 0.6331184000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0360881000, 0.0427502000, 0.0593443000, 0.0978051000, 0.2039959000, 0.5285833000, 1.5024072000", \ - "0.0362573000, 0.0431424000, 0.0590754000, 0.0977606000, 0.2043346000, 0.5291632000, 1.5025891000", \ - "0.0362391000, 0.0431223000, 0.0590035000, 0.0977447000, 0.2038504000, 0.5285609000, 1.5069753000", \ - "0.0362391000, 0.0428716000, 0.0590764000, 0.0976288000, 0.2043335000, 0.5283270000, 1.5046955000", \ - "0.0374138000, 0.0439482000, 0.0600187000, 0.0984746000, 0.2044216000, 0.5281333000, 1.4987245000", \ - "0.0434058000, 0.0501515000, 0.0663735000, 0.1057186000, 0.2094114000, 0.5289586000, 1.5023885000", \ - "0.0583279000, 0.0663668000, 0.0837925000, 0.1201906000, 0.2180252000, 0.5343343000, 1.4991741000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1847760000, 0.1912889000, 0.2056436000, 0.2339832000, 0.2875182000, 0.4040908000, 0.7112480000", \ - "0.1901220000, 0.1967025000, 0.2111693000, 0.2390660000, 0.2929835000, 0.4096185000, 0.7167446000", \ - "0.2036420000, 0.2101890000, 0.2246923000, 0.2528144000, 0.3064360000, 0.4232440000, 0.7303754000", \ - "0.2350713000, 0.2422406000, 0.2566743000, 0.2848801000, 0.3387499000, 0.4555108000, 0.7623507000", \ - "0.3116540000, 0.3183479000, 0.3327960000, 0.3609437000, 0.4148568000, 0.5319147000, 0.8384652000", \ - "0.4798283000, 0.4877058000, 0.5035366000, 0.5333418000, 0.5883864000, 0.7058856000, 1.0118976000", \ - "0.7664216000, 0.7760407000, 0.7965741000, 0.8358976000, 0.9026852000, 1.0288227000, 1.3376902000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1735709000, 0.1825499000, 0.2028722000, 0.2452322000, 0.3382641000, 0.5763987000, 1.2559562000", \ - "0.1777894000, 0.1867329000, 0.2069630000, 0.2495572000, 0.3425456000, 0.5806230000, 1.2642174000", \ - "0.1863096000, 0.1952542000, 0.2154932000, 0.2579907000, 0.3509872000, 0.5892012000, 1.2686261000", \ - "0.2032576000, 0.2122221000, 0.2325852000, 0.2749496000, 0.3681051000, 0.6056856000, 1.2884641000", \ - "0.2394094000, 0.2483025000, 0.2687782000, 0.3115627000, 0.4046581000, 0.6428224000, 1.3243259000", \ - "0.3000459000, 0.3100749000, 0.3321563000, 0.3772599000, 0.4727552000, 0.7122296000, 1.3914950000", \ - "0.3725376000, 0.3847629000, 0.4110746000, 0.4625926000, 0.5627672000, 0.8035057000, 1.4836637000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0310024000, 0.0349356000, 0.0438356000, 0.0624976000, 0.1084049000, 0.2354036000, 0.6302515000", \ - "0.0310682000, 0.0350778000, 0.0439093000, 0.0629557000, 0.1086316000, 0.2349323000, 0.6305006000", \ - "0.0310626000, 0.0350415000, 0.0441733000, 0.0630220000, 0.1082781000, 0.2360417000, 0.6343185000", \ - "0.0310222000, 0.0348471000, 0.0436562000, 0.0625964000, 0.1083697000, 0.2356298000, 0.6319686000", \ - "0.0309396000, 0.0349964000, 0.0443938000, 0.0625348000, 0.1084203000, 0.2352903000, 0.6310594000", \ - "0.0374007000, 0.0420546000, 0.0499097000, 0.0674765000, 0.1110049000, 0.2359264000, 0.6315815000", \ - "0.0573523000, 0.0623953000, 0.0728480000, 0.0929186000, 0.1340299000, 0.2514366000, 0.6344754000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0360394000, 0.0428029000, 0.0590191000, 0.0977033000, 0.2040942000, 0.5279885000, 1.5016485000", \ - "0.0361167000, 0.0427057000, 0.0592918000, 0.0978694000, 0.2040152000, 0.5285660000, 1.5028918000", \ - "0.0361181000, 0.0428712000, 0.0593540000, 0.0976635000, 0.2041560000, 0.5274349000, 1.5012905000", \ - "0.0361319000, 0.0427762000, 0.0589420000, 0.0977740000, 0.2039425000, 0.5292038000, 1.5014519000", \ - "0.0373778000, 0.0441899000, 0.0600259000, 0.0982520000, 0.2040446000, 0.5283348000, 1.5031417000", \ - "0.0420800000, 0.0492781000, 0.0652152000, 0.1044397000, 0.2082206000, 0.5303904000, 1.4991139000", \ - "0.0552859000, 0.0628693000, 0.0802212000, 0.1174609000, 0.2180184000, 0.5331601000, 1.4976794000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1946516000, 0.2012745000, 0.2159046000, 0.2443457000, 0.2981863000, 0.4151804000, 0.7223835000", \ - "0.1998945000, 0.2065239000, 0.2211294000, 0.2495122000, 0.3033585000, 0.4204506000, 0.7280389000", \ - "0.2127878000, 0.2194027000, 0.2340379000, 0.2624249000, 0.3161763000, 0.4334914000, 0.7403144000", \ - "0.2451845000, 0.2518135000, 0.2663369000, 0.2956833000, 0.3495680000, 0.4666986000, 0.7736217000", \ - "0.3223256000, 0.3289218000, 0.3435185000, 0.3721033000, 0.4263588000, 0.5433472000, 0.8506700000", \ - "0.4950903000, 0.5022422000, 0.5177365000, 0.5461351000, 0.6009002000, 0.7181321000, 1.0255844000", \ - "0.7931334000, 0.8025201000, 0.8230167000, 0.8612602000, 0.9272516000, 1.0530274000, 1.3614511000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1795201000, 0.1885042000, 0.2088883000, 0.2512457000, 0.3443069000, 0.5820969000, 1.2650933000", \ - "0.1837813000, 0.1927333000, 0.2130833000, 0.2554914000, 0.3485429000, 0.5864570000, 1.2680548000", \ - "0.1919312000, 0.2008156000, 0.2210528000, 0.2636268000, 0.3566155000, 0.5945772000, 1.2782229000", \ - "0.2070882000, 0.2160621000, 0.2364458000, 0.2787255000, 0.3717259000, 0.6099565000, 1.2940125000", \ - "0.2363556000, 0.2453466000, 0.2656838000, 0.3083950000, 0.4015525000, 0.6394253000, 1.3218105000", \ - "0.2839018000, 0.2934357000, 0.3155420000, 0.3604421000, 0.4560217000, 0.6954322000, 1.3746867000", \ - "0.3427513000, 0.3541413000, 0.3795061000, 0.4291574000, 0.5296489000, 0.7706664000, 1.4510715000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0320692000, 0.0362488000, 0.0446177000, 0.0642411000, 0.1095516000, 0.2362584000, 0.6321831000", \ - "0.0319932000, 0.0360659000, 0.0451929000, 0.0641310000, 0.1094127000, 0.2367748000, 0.6319672000", \ - "0.0319265000, 0.0360223000, 0.0453674000, 0.0635119000, 0.1092990000, 0.2362996000, 0.6316588000", \ - "0.0320481000, 0.0360019000, 0.0446420000, 0.0638862000, 0.1092757000, 0.2363049000, 0.6318269000", \ - "0.0319925000, 0.0358290000, 0.0446792000, 0.0641371000, 0.1090993000, 0.2366124000, 0.6323211000", \ - "0.0373720000, 0.0409389000, 0.0497497000, 0.0677646000, 0.1112008000, 0.2368372000, 0.6328285000", \ - "0.0567533000, 0.0611903000, 0.0716472000, 0.0915187000, 0.1328058000, 0.2493639000, 0.6340760000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0363037000, 0.0430898000, 0.0590050000, 0.0976802000, 0.2040173000, 0.5287212000, 1.5048167000", \ - "0.0365166000, 0.0430303000, 0.0589054000, 0.0975200000, 0.2039578000, 0.5280481000, 1.5088212000", \ - "0.0360182000, 0.0426994000, 0.0593427000, 0.0978278000, 0.2040086000, 0.5284278000, 1.5032456000", \ - "0.0362151000, 0.0428867000, 0.0591886000, 0.0977537000, 0.2038378000, 0.5292686000, 1.5050878000", \ - "0.0371774000, 0.0436197000, 0.0595133000, 0.0982838000, 0.2044145000, 0.5288629000, 1.5017571000", \ - "0.0411242000, 0.0481088000, 0.0648436000, 0.1032961000, 0.2076834000, 0.5285557000, 1.5014794000", \ - "0.0508141000, 0.0586356000, 0.0757667000, 0.1156499000, 0.2166704000, 0.5329967000, 1.4955370000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4_4") { - leakage_power () { - value : 0.0040885000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0040826000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0041054000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0040890000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0041100000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0040910000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0044086000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0041123000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0041161000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0040967000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0044373000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0041185000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0044719000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0041245000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0059705000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0044864000; - when : "A&B&C&!D"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__and4"; - cell_leakage_power : 0.0043068320; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049085000, 0.0049057000, 0.0048994000, 0.0049006000, 0.0049034000, 0.0049100000, 0.0049251000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004021500, -0.004023400, -0.004027800, -0.004021400, -0.004006700, -0.003972700, -0.003894200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023970000; - } - pin ("B") { - capacitance : 0.0024100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045905000, 0.0045862000, 0.0045764000, 0.0045897000, 0.0046203000, 0.0046909000, 0.0048537000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004173700, -0.004173900, -0.004174400, -0.004173800, -0.004172300, -0.004168800, -0.004160800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024870000; - } - pin ("C") { - capacitance : 0.0023630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039295000, 0.0039276000, 0.0039232000, 0.0039233000, 0.0039235000, 0.0039240000, 0.0039250000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003933000, -0.003930600, -0.003925100, -0.003924700, -0.003923800, -0.003921700, -0.003917000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024540000; - } - pin ("D") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041907000, 0.0041865000, 0.0041768000, 0.0041775000, 0.0041791000, 0.0041829000, 0.0041916000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004179100, -0.004178000, -0.004175300, -0.004175300, -0.004175300, -0.004175200, -0.004174900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024690000; - } - pin ("X") { - direction : "output"; - function : "(A&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0223359000, 0.0206942000, 0.0156045000, 4.220000e-05, -0.055116100, -0.239300300, -0.831073400", \ - "0.0223127000, 0.0206209000, 0.0155582000, 1.590000e-05, -0.055126100, -0.239430000, -0.831212900", \ - "0.0220741000, 0.0204953000, 0.0153623000, -0.000200200, -0.055301500, -0.239506100, -0.831285300", \ - "0.0218765000, 0.0202375000, 0.0151509000, -0.000573000, -0.055799900, -0.239957500, -0.831625400", \ - "0.0219509000, 0.0201994000, 0.0149125000, -0.001217400, -0.056130300, -0.240440400, -0.831948100", \ - "0.0235522000, 0.0216341000, 0.0158156000, -0.001528300, -0.056570800, -0.240284400, -0.831719400", \ - "0.0286287000, 0.0265396000, 0.0202548000, 0.0016847000, -0.055205300, -0.240054900, -0.830997900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0284573000, 0.0302812000, 0.0361407000, 0.0551465000, 0.1131036000, 0.2967632000, 0.8872369000", \ - "0.0283793000, 0.0302197000, 0.0361439000, 0.0548561000, 0.1132597000, 0.2969647000, 0.8872511000", \ - "0.0281455000, 0.0299734000, 0.0358226000, 0.0547779000, 0.1131833000, 0.2968166000, 0.8833840000", \ - "0.0278921000, 0.0296821000, 0.0354694000, 0.0543895000, 0.1130761000, 0.2963908000, 0.8833783000", \ - "0.0279423000, 0.0297159000, 0.0353788000, 0.0541404000, 0.1125677000, 0.2960288000, 0.8826487000", \ - "0.0291382000, 0.0307874000, 0.0363953000, 0.0549625000, 0.1120965000, 0.2959301000, 0.8783530000", \ - "0.0327781000, 0.0343445000, 0.0396643000, 0.0571872000, 0.1141342000, 0.2967248000, 0.8824727000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0247975000, 0.0230256000, 0.0177456000, 0.0022381000, -0.052691800, -0.236785000, -0.828399900", \ - "0.0245758000, 0.0228916000, 0.0176975000, 0.0020692000, -0.052857600, -0.236828700, -0.828438100", \ - "0.0244854000, 0.0227397000, 0.0175535000, 0.0019372000, -0.053008900, -0.236900500, -0.828564000", \ - "0.0241787000, 0.0226117000, 0.0173402000, 0.0015960000, -0.053480900, -0.237280800, -0.828831100", \ - "0.0242279000, 0.0225580000, 0.0172231000, 0.0011121000, -0.053687600, -0.237787600, -0.829263900", \ - "0.0240097000, 0.0222137000, 0.0165476000, 0.0011577000, -0.054455100, -0.237849900, -0.829189600", \ - "0.0310476000, 0.0289285000, 0.0226919000, 0.0040641000, -0.053836000, -0.237849800, -0.828842400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0287368000, 0.0305589000, 0.0363073000, 0.0554486000, 0.1134856000, 0.2970398000, 0.8875170000", \ - "0.0287187000, 0.0305341000, 0.0363965000, 0.0554072000, 0.1133914000, 0.2966236000, 0.8869823000", \ - "0.0285719000, 0.0304274000, 0.0363002000, 0.0550271000, 0.1136625000, 0.2967996000, 0.8826101000", \ - "0.0283737000, 0.0300647000, 0.0358767000, 0.0549079000, 0.1131893000, 0.2967619000, 0.8830748000", \ - "0.0283272000, 0.0300946000, 0.0358856000, 0.0547419000, 0.1128290000, 0.2964197000, 0.8781726000", \ - "0.0288607000, 0.0305274000, 0.0359438000, 0.0544730000, 0.1126375000, 0.2959417000, 0.8821440000", \ - "0.0317283000, 0.0333317000, 0.0386184000, 0.0567437000, 0.1146472000, 0.2973207000, 0.8800286000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0275123000, 0.0258557000, 0.0205512000, 0.0048590000, -0.049819500, -0.233648700, -0.825195000", \ - "0.0272980000, 0.0256433000, 0.0203339000, 0.0048576000, -0.049970800, -0.233745800, -0.825316600", \ - "0.0272095000, 0.0254446000, 0.0202116000, 0.0047170000, -0.050084300, -0.233892400, -0.825445800", \ - "0.0271271000, 0.0252294000, 0.0199679000, 0.0042639000, -0.050564000, -0.234187200, -0.825666000", \ - "0.0272945000, 0.0255937000, 0.0201600000, 0.0041259000, -0.051013200, -0.234538600, -0.825980400", \ - "0.0276065000, 0.0258002000, 0.0201196000, 0.0039484000, -0.050730600, -0.234467600, -0.825598100", \ - "0.0346538000, 0.0325391000, 0.0263123000, 0.0076375000, -0.050474600, -0.234347900, -0.825299400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0285316000, 0.0302937000, 0.0360872000, 0.0549935000, 0.1135903000, 0.2965637000, 0.8820369000", \ - "0.0284849000, 0.0303065000, 0.0361660000, 0.0551784000, 0.1131561000, 0.2964668000, 0.8866325000", \ - "0.0283377000, 0.0301509000, 0.0358885000, 0.0549302000, 0.1134166000, 0.2964336000, 0.8819552000", \ - "0.0281039000, 0.0299271000, 0.0356834000, 0.0546334000, 0.1130690000, 0.2962549000, 0.8819636000", \ - "0.0280097000, 0.0297767000, 0.0356227000, 0.0544653000, 0.1127741000, 0.2962287000, 0.8824468000", \ - "0.0287986000, 0.0304903000, 0.0363632000, 0.0546483000, 0.1125316000, 0.2958767000, 0.8777816000", \ - "0.0309454000, 0.0325917000, 0.0380269000, 0.0566377000, 0.1138781000, 0.2975539000, 0.8786315000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0295029000, 0.0277243000, 0.0223330000, 0.0065108000, -0.048418300, -0.232191300, -0.823779000", \ - "0.0293547000, 0.0277766000, 0.0223429000, 0.0064388000, -0.048441800, -0.232363700, -0.823941600", \ - "0.0291749000, 0.0274524000, 0.0220927000, 0.0063285000, -0.048581300, -0.232493700, -0.824035100", \ - "0.0289766000, 0.0272429000, 0.0218735000, 0.0060872000, -0.048835300, -0.232760800, -0.824198400", \ - "0.0291639000, 0.0273747000, 0.0220145000, 0.0059390000, -0.048941200, -0.232811500, -0.824181900", \ - "0.0293125000, 0.0274215000, 0.0217878000, 0.0064300000, -0.048985300, -0.233072900, -0.824342800", \ - "0.0376705000, 0.0355602000, 0.0294144000, 0.0105823000, -0.048334400, -0.232522200, -0.823691700"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0288300000, 0.0306251000, 0.0365994000, 0.0553208000, 0.1137850000, 0.2968700000, 0.8782827000", \ - "0.0287686000, 0.0305736000, 0.0363999000, 0.0553072000, 0.1137779000, 0.2966361000, 0.8817872000", \ - "0.0285933000, 0.0304391000, 0.0361491000, 0.0551900000, 0.1136417000, 0.2965250000, 0.8817338000", \ - "0.0283295000, 0.0301529000, 0.0359643000, 0.0548340000, 0.1132877000, 0.2963190000, 0.8858348000", \ - "0.0282773000, 0.0299772000, 0.0358158000, 0.0545154000, 0.1129950000, 0.2963205000, 0.8824244000", \ - "0.0292814000, 0.0309908000, 0.0366533000, 0.0544459000, 0.1128973000, 0.2959466000, 0.8779109000", \ - "0.0312342000, 0.0328978000, 0.0383677000, 0.0565755000, 0.1138979000, 0.2971594000, 0.8800971000"); - } - } - max_capacitance : 0.5319310000; - max_transition : 1.5064790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1154774000, 0.1190116000, 0.1280661000, 0.1482224000, 0.1906042000, 0.2941229000, 0.6026539000", \ - "0.1209914000, 0.1244771000, 0.1335243000, 0.1536304000, 0.1962033000, 0.2996587000, 0.6083357000", \ - "0.1344616000, 0.1379507000, 0.1470132000, 0.1671641000, 0.2094988000, 0.3130463000, 0.6213901000", \ - "0.1651074000, 0.1686253000, 0.1776673000, 0.1976197000, 0.2408588000, 0.3444690000, 0.6528954000", \ - "0.2379787000, 0.2415085000, 0.2505905000, 0.2707340000, 0.3128440000, 0.4172132000, 0.7253331000", \ - "0.3641999000, 0.3688039000, 0.3805657000, 0.4056281000, 0.4546638000, 0.5612088000, 0.8693620000", \ - "0.5606758000, 0.5666413000, 0.5815357000, 0.6151660000, 0.6764486000, 0.7954639000, 1.1058705000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1618261000, 0.1679806000, 0.1839951000, 0.2204500000, 0.3046404000, 0.5313414000, 1.2394471000", \ - "0.1655860000, 0.1716438000, 0.1874874000, 0.2239701000, 0.3084047000, 0.5355444000, 1.2425126000", \ - "0.1742364000, 0.1803098000, 0.1961552000, 0.2326986000, 0.3171080000, 0.5442905000, 1.2515931000", \ - "0.1953239000, 0.2014007000, 0.2172416000, 0.2538579000, 0.3383099000, 0.5654400000, 1.2733906000", \ - "0.2456526000, 0.2517511000, 0.2673804000, 0.3043313000, 0.3885100000, 0.6159130000, 1.3227206000", \ - "0.3247661000, 0.3316766000, 0.3493024000, 0.3879140000, 0.4743006000, 0.7021113000, 1.4099921000", \ - "0.4132198000, 0.4217016000, 0.4435591000, 0.4901514000, 0.5817319000, 0.8106626000, 1.5193804000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0223430000, 0.0246128000, 0.0302678000, 0.0447774000, 0.0839331000, 0.2067106000, 0.6206612000", \ - "0.0224414000, 0.0247306000, 0.0304966000, 0.0449268000, 0.0838303000, 0.2063415000, 0.6234084000", \ - "0.0225930000, 0.0248214000, 0.0302851000, 0.0448801000, 0.0839642000, 0.2067321000, 0.6235474000", \ - "0.0223715000, 0.0245504000, 0.0306676000, 0.0450458000, 0.0837382000, 0.2064086000, 0.6205630000", \ - "0.0242041000, 0.0262011000, 0.0317512000, 0.0458043000, 0.0847194000, 0.2067239000, 0.6210005000", \ - "0.0362849000, 0.0388967000, 0.0450792000, 0.0596848000, 0.0956427000, 0.2113232000, 0.6210835000", \ - "0.0560531000, 0.0590802000, 0.0682859000, 0.0852594000, 0.1221502000, 0.2295372000, 0.6230528000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0372432000, 0.0419585000, 0.0541341000, 0.0858497000, 0.1783996000, 0.4843728000, 1.5059395000", \ - "0.0378340000, 0.0421830000, 0.0540432000, 0.0859591000, 0.1780799000, 0.4852774000, 1.5064787000", \ - "0.0375571000, 0.0421381000, 0.0539184000, 0.0860002000, 0.1780113000, 0.4852298000, 1.5018781000", \ - "0.0373231000, 0.0416442000, 0.0539614000, 0.0857794000, 0.1780061000, 0.4852910000, 1.5028785000", \ - "0.0382461000, 0.0427789000, 0.0551857000, 0.0870226000, 0.1786032000, 0.4845545000, 1.5027720000", \ - "0.0470706000, 0.0512691000, 0.0630987000, 0.0935239000, 0.1837430000, 0.4871425000, 1.4978636000", \ - "0.0647691000, 0.0700653000, 0.0844120000, 0.1126638000, 0.1963986000, 0.4913058000, 1.4985062000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1351915000, 0.1389019000, 0.1485162000, 0.1697996000, 0.2135846000, 0.3186717000, 0.6274285000", \ - "0.1410176000, 0.1447536000, 0.1543887000, 0.1753174000, 0.2195334000, 0.3243526000, 0.6325538000", \ - "0.1543166000, 0.1580446000, 0.1676197000, 0.1888534000, 0.2329599000, 0.3377335000, 0.6465828000", \ - "0.1859124000, 0.1896633000, 0.1992416000, 0.2202925000, 0.2651539000, 0.3691993000, 0.6775268000", \ - "0.2616216000, 0.2653380000, 0.2748951000, 0.2959567000, 0.3389735000, 0.4453091000, 0.7542109000", \ - "0.4075644000, 0.4122339000, 0.4240982000, 0.4491530000, 0.4981723000, 0.6051046000, 0.9139862000", \ - "0.6422922000, 0.6484000000, 0.6643088000, 0.6979367000, 0.7596609000, 0.8782939000, 1.1893055000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1721604000, 0.1782389000, 0.1940718000, 0.2307657000, 0.3150447000, 0.5420279000, 1.2507295000", \ - "0.1760492000, 0.1821361000, 0.1981470000, 0.2346042000, 0.3187217000, 0.5458507000, 1.2531877000", \ - "0.1843256000, 0.1905312000, 0.2064318000, 0.2429241000, 0.3272191000, 0.5541517000, 1.2656965000", \ - "0.2037948000, 0.2097282000, 0.2255944000, 0.2622454000, 0.3464831000, 0.5737610000, 1.2839647000", \ - "0.2472558000, 0.2533271000, 0.2693571000, 0.3060782000, 0.3904609000, 0.6176755000, 1.3242690000", \ - "0.3184426000, 0.3252217000, 0.3427058000, 0.3820121000, 0.4688517000, 0.6974830000, 1.4083676000", \ - "0.3982398000, 0.4064995000, 0.4279381000, 0.4739034000, 0.5658620000, 0.7961810000, 1.5036268000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0251216000, 0.0271957000, 0.0331307000, 0.0475818000, 0.0870770000, 0.2085749000, 0.6220923000", \ - "0.0249486000, 0.0271277000, 0.0330501000, 0.0480071000, 0.0867113000, 0.2089156000, 0.6224971000", \ - "0.0249382000, 0.0272322000, 0.0333251000, 0.0475917000, 0.0869425000, 0.2087537000, 0.6214944000", \ - "0.0251704000, 0.0274912000, 0.0330891000, 0.0477161000, 0.0867175000, 0.2088642000, 0.6216837000", \ - "0.0256924000, 0.0280091000, 0.0338933000, 0.0481644000, 0.0875700000, 0.2085049000, 0.6214717000", \ - "0.0366500000, 0.0393035000, 0.0452899000, 0.0600462000, 0.0952301000, 0.2117258000, 0.6221924000", \ - "0.0569307000, 0.0601477000, 0.0679122000, 0.0857381000, 0.1221010000, 0.2292605000, 0.6229365000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0375159000, 0.0419584000, 0.0543740000, 0.0856344000, 0.1781312000, 0.4853711000, 1.5060595000", \ - "0.0372849000, 0.0419663000, 0.0541703000, 0.0858733000, 0.1781817000, 0.4851320000, 1.5036611000", \ - "0.0372287000, 0.0419800000, 0.0541149000, 0.0860041000, 0.1782209000, 0.4852842000, 1.5003345000", \ - "0.0372291000, 0.0420371000, 0.0541510000, 0.0859437000, 0.1781561000, 0.4848589000, 1.5018692000", \ - "0.0385373000, 0.0426319000, 0.0549865000, 0.0866198000, 0.1786371000, 0.4854170000, 1.5012249000", \ - "0.0447787000, 0.0493413000, 0.0616251000, 0.0928859000, 0.1833954000, 0.4866011000, 1.5001472000", \ - "0.0609331000, 0.0652768000, 0.0790307000, 0.1097115000, 0.1943653000, 0.4910508000, 1.4984546000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1467733000, 0.1506427000, 0.1604906000, 0.1822487000, 0.2269433000, 0.3324958000, 0.6418012000", \ - "0.1522968000, 0.1561561000, 0.1660702000, 0.1877981000, 0.2323981000, 0.3380900000, 0.6471736000", \ - "0.1659313000, 0.1697819000, 0.1796604000, 0.2014667000, 0.2463371000, 0.3517104000, 0.6610225000", \ - "0.1974322000, 0.2021729000, 0.2120709000, 0.2337972000, 0.2788411000, 0.3842824000, 0.6933276000", \ - "0.2745976000, 0.2784324000, 0.2882573000, 0.3098543000, 0.3547526000, 0.4606526000, 0.7696250000", \ - "0.4297298000, 0.4344347000, 0.4462285000, 0.4702170000, 0.5192097000, 0.6261978000, 0.9355638000", \ - "0.6830261000, 0.6891629000, 0.7048563000, 0.7381142000, 0.7995490000, 0.9176295000, 1.2279751000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1783762000, 0.1844398000, 0.2002593000, 0.2369980000, 0.3212374000, 0.5479327000, 1.2592144000", \ - "0.1824067000, 0.1884947000, 0.2045085000, 0.2409701000, 0.3250851000, 0.5515412000, 1.2591125000", \ - "0.1902349000, 0.1963027000, 0.2121906000, 0.2487674000, 0.3331153000, 0.5598687000, 1.2711220000", \ - "0.2066470000, 0.2127142000, 0.2284306000, 0.2652193000, 0.3494184000, 0.5759780000, 1.2874829000", \ - "0.2421498000, 0.2483131000, 0.2642153000, 0.3010931000, 0.3854069000, 0.6126727000, 1.3226501000", \ - "0.3014214000, 0.3081482000, 0.3256763000, 0.3648332000, 0.4516741000, 0.6800546000, 1.3868733000", \ - "0.3685673000, 0.3766190000, 0.3975054000, 0.4429028000, 0.5352314000, 0.7660645000, 1.4731832000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0265051000, 0.0286030000, 0.0345934000, 0.0490009000, 0.0882838000, 0.2095363000, 0.6204924000", \ - "0.0264966000, 0.0285103000, 0.0346652000, 0.0493510000, 0.0884379000, 0.2096043000, 0.6215546000", \ - "0.0263002000, 0.0286381000, 0.0347175000, 0.0491521000, 0.0882315000, 0.2097685000, 0.6219056000", \ - "0.0263728000, 0.0286422000, 0.0348037000, 0.0492261000, 0.0880355000, 0.2095390000, 0.6215962000", \ - "0.0262971000, 0.0286593000, 0.0347612000, 0.0496866000, 0.0882156000, 0.2097182000, 0.6225412000", \ - "0.0362948000, 0.0392622000, 0.0449315000, 0.0589184000, 0.0950662000, 0.2119952000, 0.6223052000", \ - "0.0567096000, 0.0593829000, 0.0678020000, 0.0847376000, 0.1198340000, 0.2275281000, 0.6230826000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0372637000, 0.0417578000, 0.0543704000, 0.0859265000, 0.1782664000, 0.4852940000, 1.4995483000", \ - "0.0372771000, 0.0419621000, 0.0541402000, 0.0858434000, 0.1783607000, 0.4842125000, 1.5060915000", \ - "0.0376651000, 0.0422270000, 0.0540110000, 0.0861249000, 0.1780867000, 0.4852967000, 1.5002769000", \ - "0.0372280000, 0.0418129000, 0.0543025000, 0.0859234000, 0.1780014000, 0.4851013000, 1.5014644000", \ - "0.0384114000, 0.0428638000, 0.0546844000, 0.0868713000, 0.1784206000, 0.4844460000, 1.5015821000", \ - "0.0433935000, 0.0479994000, 0.0610742000, 0.0922001000, 0.1827716000, 0.4866322000, 1.4998501000", \ - "0.0576642000, 0.0622372000, 0.0755365000, 0.1071419000, 0.1942394000, 0.4906868000, 1.4962470000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1573006000, 0.1612686000, 0.1714377000, 0.1935999000, 0.2389674000, 0.3454555000, 0.6547476000", \ - "0.1627098000, 0.1666576000, 0.1768172000, 0.1989982000, 0.2444384000, 0.3510948000, 0.6605469000", \ - "0.1758312000, 0.1797927000, 0.1899100000, 0.2118921000, 0.2575107000, 0.3641410000, 0.6735976000", \ - "0.2090542000, 0.2130220000, 0.2231443000, 0.2451683000, 0.2907863000, 0.3972706000, 0.7070287000", \ - "0.2856593000, 0.2895906000, 0.2996870000, 0.3218956000, 0.3668066000, 0.4734129000, 0.7832026000", \ - "0.4467613000, 0.4514132000, 0.4631630000, 0.4878943000, 0.5355014000, 0.6438808000, 0.9530251000", \ - "0.7133423000, 0.7194712000, 0.7350763000, 0.7681912000, 0.8291262000, 0.9467468000, 1.2571830000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.1842908000, 0.1903569000, 0.2062439000, 0.2427593000, 0.3271351000, 0.5537282000, 1.2602774000", \ - "0.1883339000, 0.1944191000, 0.2102990000, 0.2468808000, 0.3312116000, 0.5577258000, 1.2687689000", \ - "0.1960028000, 0.2021220000, 0.2178991000, 0.2545672000, 0.3389055000, 0.5654638000, 1.2765531000", \ - "0.2104510000, 0.2165937000, 0.2323287000, 0.2689965000, 0.3532473000, 0.5796046000, 1.2889553000", \ - "0.2390992000, 0.2451672000, 0.2611567000, 0.2979038000, 0.3822558000, 0.6092126000, 1.3184660000", \ - "0.2856425000, 0.2923259000, 0.3095852000, 0.3483366000, 0.4351952000, 0.6631895000, 1.3702808000", \ - "0.3390478000, 0.3467710000, 0.3666790000, 0.4106173000, 0.5028266000, 0.7336816000, 1.4408439000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0278960000, 0.0299277000, 0.0359874000, 0.0510382000, 0.0899998000, 0.2109438000, 0.6244767000", \ - "0.0278874000, 0.0303126000, 0.0361616000, 0.0512903000, 0.0902048000, 0.2109901000, 0.6222870000", \ - "0.0276530000, 0.0299756000, 0.0360118000, 0.0509640000, 0.0900843000, 0.2107631000, 0.6225013000", \ - "0.0276258000, 0.0299550000, 0.0359931000, 0.0514513000, 0.0899380000, 0.2105676000, 0.6231552000", \ - "0.0276784000, 0.0301239000, 0.0365527000, 0.0511559000, 0.0899401000, 0.2113352000, 0.6226322000", \ - "0.0367716000, 0.0392981000, 0.0450006000, 0.0596711000, 0.0945710000, 0.2123526000, 0.6235052000", \ - "0.0565349000, 0.0598234000, 0.0673152000, 0.0840537000, 0.1197179000, 0.2275397000, 0.6246642000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0373436000, 0.0418522000, 0.0542189000, 0.0860799000, 0.1780215000, 0.4852720000, 1.4993400000", \ - "0.0378065000, 0.0422919000, 0.0544099000, 0.0861325000, 0.1781413000, 0.4853052000, 1.4993682000", \ - "0.0377594000, 0.0416635000, 0.0539754000, 0.0861313000, 0.1780879000, 0.4853051000, 1.4999236000", \ - "0.0374317000, 0.0417922000, 0.0543889000, 0.0860905000, 0.1781392000, 0.4850739000, 1.5030414000", \ - "0.0381582000, 0.0426319000, 0.0547076000, 0.0866277000, 0.1785996000, 0.4850013000, 1.5023307000", \ - "0.0421045000, 0.0469784000, 0.0600019000, 0.0919297000, 0.1827630000, 0.4865288000, 1.4990891000", \ - "0.0530331000, 0.0583227000, 0.0721163000, 0.1046794000, 0.1927545000, 0.4898557000, 1.4964625000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4b_1") { - leakage_power () { - value : 0.0059278000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0059068000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0062725000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0059270000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0062987000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0059328000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0017214000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0062838000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0063887000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0063821000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0064070000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0063885000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0064106000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0063900000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0067416000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0064098000; - when : "A_N&B&C&!D"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__and4b"; - cell_leakage_power : 0.0059868220; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0067855000, 0.0066678000, 0.0063963000, 0.0064313000, 0.0065118000, 0.0066975000, 0.0071255000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020445000, 0.0019594000, 0.0017631000, 0.0017934000, 0.0018632000, 0.0020242000, 0.0023952000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016510000; - } - pin ("B") { - capacitance : 0.0015740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026934000, 0.0026918000, 0.0026880000, 0.0026906000, 0.0026967000, 0.0027107000, 0.0027430000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002382900, -0.002383600, -0.002385300, -0.002378300, -0.002362300, -0.002325300, -0.002240000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016030000; - } - pin ("C") { - capacitance : 0.0015470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019856000, 0.0019836000, 0.0019788000, 0.0019895000, 0.0020142000, 0.0020712000, 0.0022025000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001906300, -0.001906000, -0.001905500, -0.001905600, -0.001905600, -0.001905700, -0.001905900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015770000; - } - pin ("D") { - capacitance : 0.0015940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023389000, 0.0023402000, 0.0023432000, 0.0023435000, 0.0023443000, 0.0023460000, 0.0023501000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002332400, -0.002334300, -0.002338900, -0.002338100, -0.002336500, -0.002332600, -0.002323800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016560000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0077176000, 0.0066742000, 0.0039223000, -0.004097700, -0.026563900, -0.086035700, -0.241307800", \ - "0.0076969000, 0.0066548000, 0.0039157000, -0.004116000, -0.026553700, -0.086051800, -0.241311900", \ - "0.0076905000, 0.0066531000, 0.0038997000, -0.004116700, -0.026593800, -0.086066800, -0.241348200", \ - "0.0074140000, 0.0063606000, 0.0036127000, -0.004437800, -0.026871300, -0.086363600, -0.241617800", \ - "0.0070958000, 0.0060293000, 0.0032694000, -0.004730300, -0.027186800, -0.086677700, -0.241927400", \ - "0.0084133000, 0.0072093000, 0.0040074000, -0.004519000, -0.027242300, -0.086709300, -0.241951500", \ - "0.0084447000, 0.0072393000, 0.0039682000, -0.004642500, -0.027094700, -0.086714200, -0.242007300"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0116931000, 0.0130826000, 0.0166714000, 0.0256233000, 0.0483946000, 0.1078225000, 0.2611682000", \ - "0.0116007000, 0.0130090000, 0.0166110000, 0.0255373000, 0.0482870000, 0.1072703000, 0.2597069000", \ - "0.0116909000, 0.0130802000, 0.0166778000, 0.0256334000, 0.0484004000, 0.1078423000, 0.2612602000", \ - "0.0115503000, 0.0129429000, 0.0165324000, 0.0254869000, 0.0482564000, 0.1077006000, 0.2611087000", \ - "0.0113791000, 0.0127874000, 0.0164034000, 0.0253204000, 0.0480951000, 0.1075731000, 0.2606744000", \ - "0.0111720000, 0.0126037000, 0.0162841000, 0.0252278000, 0.0479456000, 0.1068716000, 0.2609774000", \ - "0.0118416000, 0.0130831000, 0.0165242000, 0.0253333000, 0.0480047000, 0.1071585000, 0.2615287000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0080101000, 0.0069121000, 0.0041068000, -0.003999700, -0.026438100, -0.085906900, -0.241118200", \ - "0.0079503000, 0.0068624000, 0.0040363000, -0.004070400, -0.026497300, -0.085974300, -0.241182700", \ - "0.0078342000, 0.0067469000, 0.0039382000, -0.004167500, -0.026635300, -0.086100700, -0.241306400", \ - "0.0076418000, 0.0065582000, 0.0036934000, -0.004443400, -0.026867800, -0.086327100, -0.241509200", \ - "0.0074748000, 0.0063600000, 0.0034766000, -0.004625800, -0.027078200, -0.086481400, -0.241658700", \ - "0.0077598000, 0.0064720000, 0.0032611000, -0.004876400, -0.027191300, -0.086571000, -0.241708300", \ - "0.0092704000, 0.0078733000, 0.0044105000, -0.004399000, -0.027154600, -0.086155100, -0.241437800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0121400000, 0.0135244000, 0.0171442000, 0.0260557000, 0.0486957000, 0.1081015000, 0.2611714000", \ - "0.0121182000, 0.0135091000, 0.0171277000, 0.0259581000, 0.0486741000, 0.1074613000, 0.2623430000", \ - "0.0120377000, 0.0134072000, 0.0170339000, 0.0258853000, 0.0485723000, 0.1074584000, 0.2610299000", \ - "0.0118983000, 0.0132841000, 0.0168992000, 0.0258346000, 0.0484924000, 0.1079392000, 0.2610123000", \ - "0.0117756000, 0.0131494000, 0.0167195000, 0.0256381000, 0.0483642000, 0.1072442000, 0.2623142000", \ - "0.0124014000, 0.0136717000, 0.0170423000, 0.0256213000, 0.0482342000, 0.1070579000, 0.2610455000", \ - "0.0126413000, 0.0138968000, 0.0172609000, 0.0259937000, 0.0486645000, 0.1077392000, 0.2599938000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0098052000, 0.0086982000, 0.0058576000, -0.002211300, -0.024576000, -0.083970800, -0.239144700", \ - "0.0097118000, 0.0086218000, 0.0058057000, -0.002252600, -0.024665900, -0.084053800, -0.239221100", \ - "0.0096008000, 0.0085198000, 0.0057046000, -0.002356700, -0.024771200, -0.084147100, -0.239320400", \ - "0.0094314000, 0.0083275000, 0.0054963000, -0.002589500, -0.024951100, -0.084342400, -0.239492000", \ - "0.0093271000, 0.0082240000, 0.0053425000, -0.002769700, -0.025189600, -0.084532600, -0.239654200", \ - "0.0092513000, 0.0080190000, 0.0051756000, -0.002891400, -0.025291400, -0.084602100, -0.239675900", \ - "0.0111141000, 0.0097352000, 0.0062849000, -0.002518200, -0.025302400, -0.084508700, -0.239513100"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0119961000, 0.0133881000, 0.0170066000, 0.0258275000, 0.0484962000, 0.1071513000, 0.2619654000", \ - "0.0119792000, 0.0133738000, 0.0169567000, 0.0258581000, 0.0484681000, 0.1078085000, 0.2606442000", \ - "0.0118960000, 0.0133013000, 0.0168846000, 0.0258102000, 0.0484111000, 0.1077447000, 0.2608184000", \ - "0.0117623000, 0.0131763000, 0.0167724000, 0.0256907000, 0.0483463000, 0.1071801000, 0.2609230000", \ - "0.0117637000, 0.0131270000, 0.0166699000, 0.0255656000, 0.0482783000, 0.1076742000, 0.2608206000", \ - "0.0122743000, 0.0135537000, 0.0169677000, 0.0254694000, 0.0481357000, 0.1069421000, 0.2606673000", \ - "0.0125160000, 0.0137803000, 0.0171234000, 0.0260924000, 0.0487042000, 0.1076750000, 0.2596974000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0109338000, 0.0098183000, 0.0069254000, -0.001326700, -0.023950500, -0.083512300, -0.238728200", \ - "0.0108660000, 0.0097653000, 0.0068557000, -0.001381200, -0.024037500, -0.083589500, -0.238831700", \ - "0.0106829000, 0.0096026000, 0.0066824000, -0.001529400, -0.024156100, -0.083708400, -0.238908200", \ - "0.0105419000, 0.0094430000, 0.0065386000, -0.001696200, -0.024300700, -0.083827300, -0.239043200", \ - "0.0105137000, 0.0094010000, 0.0064507000, -0.001755000, -0.024396700, -0.083894100, -0.239108800", \ - "0.0104733000, 0.0093085000, 0.0064828000, -0.001710800, -0.024263400, -0.083784400, -0.238998000", \ - "0.0126797000, 0.0112867000, 0.0078093000, -0.001066300, -0.024032700, -0.083447100, -0.238672100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0124277000, 0.0138152000, 0.0174276000, 0.0263338000, 0.0488995000, 0.1080770000, 0.2610488000", \ - "0.0123726000, 0.0137929000, 0.0173432000, 0.0262995000, 0.0488624000, 0.1080148000, 0.2610415000", \ - "0.0123016000, 0.0136854000, 0.0173037000, 0.0262201000, 0.0487819000, 0.1079573000, 0.2608305000", \ - "0.0121495000, 0.0135368000, 0.0171433000, 0.0260390000, 0.0486668000, 0.1077963000, 0.2606927000", \ - "0.0120263000, 0.0134114000, 0.0169413000, 0.0258352000, 0.0485456000, 0.1072572000, 0.2618787000", \ - "0.0124560000, 0.0137563000, 0.0171754000, 0.0257219000, 0.0484382000, 0.1070499000, 0.2608874000", \ - "0.0126280000, 0.0139123000, 0.0172662000, 0.0260284000, 0.0487323000, 0.1078503000, 0.2601296000"); - } - } - max_capacitance : 0.1556500000; - max_transition : 1.4988650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1506207000, 0.1576010000, 0.1716470000, 0.1990473000, 0.2539979000, 0.3794822000, 0.6994728000", \ - "0.1554675000, 0.1624584000, 0.1766768000, 0.2038851000, 0.2587418000, 0.3843327000, 0.7035277000", \ - "0.1663873000, 0.1734225000, 0.1876435000, 0.2150076000, 0.2699124000, 0.3952663000, 0.7152764000", \ - "0.1871328000, 0.1940566000, 0.2082105000, 0.2356893000, 0.2905221000, 0.4159794000, 0.7364307000", \ - "0.2159816000, 0.2229509000, 0.2371213000, 0.2644068000, 0.3194703000, 0.4450200000, 0.7655171000", \ - "0.2510777000, 0.2580161000, 0.2722636000, 0.2997015000, 0.3547498000, 0.4803148000, 0.8002976000", \ - "0.2841504000, 0.2911306000, 0.3053498000, 0.3328580000, 0.3879542000, 0.5134893000, 0.8334746000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1931937000, 0.2031924000, 0.2243902000, 0.2685366000, 0.3668202000, 0.6121395000, 1.2487539000", \ - "0.1977331000, 0.2077844000, 0.2289544000, 0.2729623000, 0.3713072000, 0.6159888000, 1.2520964000", \ - "0.2100854000, 0.2200840000, 0.2414021000, 0.2855499000, 0.3838244000, 0.6291433000, 1.2665057000", \ - "0.2419218000, 0.2518857000, 0.2730845000, 0.3172314000, 0.4155086000, 0.6608292000, 1.2981397000", \ - "0.3071172000, 0.3171461000, 0.3382816000, 0.3823207000, 0.4807088000, 0.7261578000, 1.3617069000", \ - "0.4140249000, 0.4240343000, 0.4453938000, 0.4895953000, 0.5876724000, 0.8325357000, 1.4720977000", \ - "0.5844192000, 0.5944724000, 0.6159508000, 0.6604904000, 0.7591752000, 1.0047608000, 1.6408375000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0245215000, 0.0291671000, 0.0400020000, 0.0634632000, 0.1207806000, 0.2767430000, 0.6971916000", \ - "0.0245206000, 0.0290870000, 0.0399030000, 0.0635047000, 0.1206272000, 0.2767589000, 0.6944442000", \ - "0.0246275000, 0.0293055000, 0.0396327000, 0.0635285000, 0.1206083000, 0.2765091000, 0.6979812000", \ - "0.0246984000, 0.0293336000, 0.0395693000, 0.0630084000, 0.1206516000, 0.2774497000, 0.6997244000", \ - "0.0250339000, 0.0294106000, 0.0396216000, 0.0634000000, 0.1207527000, 0.2782138000, 0.6986591000", \ - "0.0247892000, 0.0294460000, 0.0400982000, 0.0636512000, 0.1207316000, 0.2745338000, 0.7034824000", \ - "0.0253000000, 0.0300555000, 0.0402318000, 0.0639709000, 0.1211012000, 0.2767869000, 0.6980478000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0353646000, 0.0439177000, 0.0632996000, 0.1111524000, 0.2379537000, 0.5822808000, 1.4942105000", \ - "0.0354825000, 0.0437460000, 0.0632869000, 0.1110569000, 0.2376493000, 0.5828638000, 1.4891297000", \ - "0.0353704000, 0.0438644000, 0.0633115000, 0.1111575000, 0.2379665000, 0.5824152000, 1.4969126000", \ - "0.0354296000, 0.0439183000, 0.0633165000, 0.1111591000, 0.2379667000, 0.5824426000, 1.4968047000", \ - "0.0351456000, 0.0437761000, 0.0632750000, 0.1111547000, 0.2378871000, 0.5824908000, 1.4881933000", \ - "0.0358177000, 0.0443108000, 0.0637687000, 0.1114502000, 0.2377701000, 0.5818530000, 1.4988653000", \ - "0.0366812000, 0.0451410000, 0.0645588000, 0.1122716000, 0.2386121000, 0.5814211000, 1.4879737000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1344868000, 0.1415291000, 0.1557212000, 0.1833386000, 0.2382918000, 0.3639850000, 0.6847328000", \ - "0.1400667000, 0.1471077000, 0.1610742000, 0.1886917000, 0.2436471000, 0.3693481000, 0.6900744000", \ - "0.1532312000, 0.1602700000, 0.1746637000, 0.2021239000, 0.2571056000, 0.3826743000, 0.7032445000", \ - "0.1848490000, 0.1919079000, 0.2061642000, 0.2338880000, 0.2889296000, 0.4144749000, 0.7349099000", \ - "0.2601795000, 0.2672313000, 0.2815298000, 0.3092600000, 0.3643184000, 0.4901581000, 0.8093546000", \ - "0.4072945000, 0.4159039000, 0.4331704000, 0.4640054000, 0.5212725000, 0.6481979000, 0.9698554000", \ - "0.6444568000, 0.6561025000, 0.6785863000, 0.7180088000, 0.7855522000, 0.9155828000, 1.2386354000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1362414000, 0.1462373000, 0.1674470000, 0.2114506000, 0.3095044000, 0.5542749000, 1.1882280000", \ - "0.1403042000, 0.1502624000, 0.1714140000, 0.2152870000, 0.3131868000, 0.5575656000, 1.1933502000", \ - "0.1485450000, 0.1584355000, 0.1796586000, 0.2235884000, 0.3216415000, 0.5666452000, 1.2028092000", \ - "0.1675532000, 0.1775397000, 0.1986440000, 0.2426433000, 0.3406967000, 0.5858394000, 1.2198040000", \ - "0.2063176000, 0.2167066000, 0.2385422000, 0.2833361000, 0.3819312000, 0.6273614000, 1.2656982000", \ - "0.2634668000, 0.2751366000, 0.2985761000, 0.3451300000, 0.4453587000, 0.6914441000, 1.3258774000", \ - "0.3163598000, 0.3313362000, 0.3606370000, 0.4129195000, 0.5162248000, 0.7626142000, 1.3986032000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0254461000, 0.0300210000, 0.0409260000, 0.0638705000, 0.1207325000, 0.2767942000, 0.7026031000", \ - "0.0257168000, 0.0305204000, 0.0409624000, 0.0639292000, 0.1208438000, 0.2766646000, 0.7026512000", \ - "0.0256861000, 0.0304446000, 0.0406013000, 0.0638498000, 0.1210932000, 0.2766362000, 0.6992383000", \ - "0.0260013000, 0.0306501000, 0.0403817000, 0.0636580000, 0.1209936000, 0.2769871000, 0.7019765000", \ - "0.0258816000, 0.0304021000, 0.0406533000, 0.0643974000, 0.1210035000, 0.2771996000, 0.6949503000", \ - "0.0357945000, 0.0408229000, 0.0508290000, 0.0730248000, 0.1266798000, 0.2782559000, 0.7012821000", \ - "0.0532249000, 0.0592768000, 0.0716191000, 0.0946915000, 0.1458029000, 0.2882146000, 0.6983679000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0354797000, 0.0438511000, 0.0633765000, 0.1109310000, 0.2375890000, 0.5831048000, 1.4912226000", \ - "0.0353413000, 0.0437724000, 0.0631765000, 0.1110552000, 0.2379554000, 0.5823715000, 1.4942824000", \ - "0.0353346000, 0.0438753000, 0.0630978000, 0.1109806000, 0.2375512000, 0.5819984000, 1.4913323000", \ - "0.0352483000, 0.0437212000, 0.0630796000, 0.1110851000, 0.2378372000, 0.5833725000, 1.4907032000", \ - "0.0377217000, 0.0462570000, 0.0654677000, 0.1126904000, 0.2383402000, 0.5827164000, 1.4955639000", \ - "0.0442805000, 0.0527945000, 0.0717826000, 0.1176211000, 0.2418581000, 0.5837710000, 1.4914054000", \ - "0.0593936000, 0.0689086000, 0.0886412000, 0.1308890000, 0.2475891000, 0.5862277000, 1.4864832000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1464747000, 0.1536477000, 0.1683887000, 0.1962478000, 0.2518409000, 0.3778689000, 0.6980996000", \ - "0.1518771000, 0.1590874000, 0.1737379000, 0.2016333000, 0.2570062000, 0.3831144000, 0.7037743000", \ - "0.1655049000, 0.1727059000, 0.1873971000, 0.2152378000, 0.2706642000, 0.3967403000, 0.7175257000", \ - "0.1975638000, 0.2047420000, 0.2193606000, 0.2473199000, 0.3027538000, 0.4285906000, 0.7493338000", \ - "0.2740565000, 0.2811588000, 0.2956891000, 0.3236058000, 0.3791744000, 0.5054104000, 0.8258991000", \ - "0.4291563000, 0.4376426000, 0.4544939000, 0.4851000000, 0.5427980000, 0.6696756000, 0.9896678000", \ - "0.6824337000, 0.6936359000, 0.7157943000, 0.7547610000, 0.8207067000, 0.9526978000, 1.2730195000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1428179000, 0.1527829000, 0.1739434000, 0.2177861000, 0.3155050000, 0.5595912000, 1.1949379000", \ - "0.1469365000, 0.1569732000, 0.1780958000, 0.2221154000, 0.3199375000, 0.5644990000, 1.1998819000", \ - "0.1551972000, 0.1651871000, 0.1863442000, 0.2303736000, 0.3282701000, 0.5726382000, 1.2063891000", \ - "0.1714927000, 0.1815413000, 0.2026517000, 0.2465337000, 0.3445537000, 0.5887044000, 1.2258291000", \ - "0.2038458000, 0.2141688000, 0.2358403000, 0.2804465000, 0.3787871000, 0.6238052000, 1.2577611000", \ - "0.2536394000, 0.2652114000, 0.2885724000, 0.3353802000, 0.4355615000, 0.6812883000, 1.3175421000", \ - "0.3005959000, 0.3151822000, 0.3438642000, 0.3964603000, 0.4998935000, 0.7461857000, 1.3806298000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0270742000, 0.0313078000, 0.0418987000, 0.0649291000, 0.1218628000, 0.2778561000, 0.7007875000", \ - "0.0266470000, 0.0316316000, 0.0417425000, 0.0647924000, 0.1215509000, 0.2782448000, 0.7024255000", \ - "0.0268811000, 0.0316514000, 0.0417411000, 0.0646702000, 0.1218958000, 0.2783832000, 0.7030180000", \ - "0.0266455000, 0.0312087000, 0.0419128000, 0.0647973000, 0.1219165000, 0.2777946000, 0.7039502000", \ - "0.0269040000, 0.0314907000, 0.0416166000, 0.0648960000, 0.1220798000, 0.2783132000, 0.6993321000", \ - "0.0349366000, 0.0399612000, 0.0499394000, 0.0722895000, 0.1261826000, 0.2794116000, 0.6978790000", \ - "0.0514631000, 0.0578517000, 0.0699682000, 0.0922444000, 0.1429039000, 0.2870618000, 0.7020945000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0353540000, 0.0437938000, 0.0631916000, 0.1110529000, 0.2379042000, 0.5821789000, 1.4939802000", \ - "0.0351967000, 0.0435646000, 0.0633911000, 0.1111439000, 0.2375690000, 0.5824779000, 1.4890985000", \ - "0.0352381000, 0.0437002000, 0.0632143000, 0.1111282000, 0.2379077000, 0.5835012000, 1.4919017000", \ - "0.0350050000, 0.0436880000, 0.0630970000, 0.1110403000, 0.2375601000, 0.5829485000, 1.4954403000", \ - "0.0374360000, 0.0453892000, 0.0649288000, 0.1122311000, 0.2383696000, 0.5835150000, 1.4926517000", \ - "0.0429138000, 0.0515261000, 0.0711730000, 0.1174088000, 0.2413892000, 0.5825835000, 1.4867289000", \ - "0.0569336000, 0.0665309000, 0.0861632000, 0.1306251000, 0.2475921000, 0.5853897000, 1.4876487000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1619657000, 0.1693325000, 0.1841121000, 0.2123488000, 0.2678896000, 0.3941870000, 0.7143898000", \ - "0.1669579000, 0.1743433000, 0.1892421000, 0.2173937000, 0.2729626000, 0.3993000000, 0.7200622000", \ - "0.1793684000, 0.1866560000, 0.2015011000, 0.2297693000, 0.2855015000, 0.4119508000, 0.7330965000", \ - "0.2117841000, 0.2191963000, 0.2339947000, 0.2622156000, 0.3182757000, 0.4446939000, 0.7653708000", \ - "0.2881075000, 0.2953958000, 0.3101577000, 0.3384378000, 0.3944824000, 0.5209704000, 0.8419035000", \ - "0.4481900000, 0.4566540000, 0.4733927000, 0.5037994000, 0.5613187000, 0.6883514000, 1.0088845000", \ - "0.7122064000, 0.7233920000, 0.7451267000, 0.7834672000, 0.8488076000, 0.9801013000, 1.3011671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1508552000, 0.1608782000, 0.1820940000, 0.2260938000, 0.3238402000, 0.5676963000, 1.2008168000", \ - "0.1550264000, 0.1651698000, 0.1861303000, 0.2302032000, 0.3279645000, 0.5719467000, 1.2046684000", \ - "0.1628123000, 0.1728115000, 0.1940356000, 0.2380064000, 0.3357657000, 0.5797928000, 1.2127664000", \ - "0.1776088000, 0.1875297000, 0.2087229000, 0.2525590000, 0.3503941000, 0.5946620000, 1.2273701000", \ - "0.2041530000, 0.2145452000, 0.2360403000, 0.2805021000, 0.3788015000, 0.6235655000, 1.2652634000", \ - "0.2448253000, 0.2559833000, 0.2792440000, 0.3257475000, 0.4259353000, 0.6714336000, 1.3049506000", \ - "0.2861571000, 0.2999294000, 0.3275261000, 0.3783550000, 0.4826172000, 0.7291760000, 1.3632773000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0287284000, 0.0335274000, 0.0435808000, 0.0669721000, 0.1240456000, 0.2796210000, 0.6987289000", \ - "0.0283092000, 0.0331408000, 0.0439767000, 0.0670568000, 0.1244037000, 0.2793556000, 0.7021649000", \ - "0.0283219000, 0.0332840000, 0.0441592000, 0.0668589000, 0.1244213000, 0.2793965000, 0.7018180000", \ - "0.0286983000, 0.0337120000, 0.0437620000, 0.0676203000, 0.1241904000, 0.2796200000, 0.7025683000", \ - "0.0283434000, 0.0334995000, 0.0442559000, 0.0670117000, 0.1240782000, 0.2789540000, 0.7047642000", \ - "0.0354043000, 0.0404684000, 0.0505705000, 0.0724479000, 0.1272310000, 0.2797270000, 0.6992525000", \ - "0.0518164000, 0.0577917000, 0.0697170000, 0.0919717000, 0.1435134000, 0.2870597000, 0.6995743000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0353741000, 0.0438401000, 0.0633734000, 0.1109176000, 0.2375743000, 0.5829270000, 1.4921985000", \ - "0.0354281000, 0.0436845000, 0.0633348000, 0.1108168000, 0.2375215000, 0.5822745000, 1.4895982000", \ - "0.0353775000, 0.0438548000, 0.0633846000, 0.1108430000, 0.2375179000, 0.5825153000, 1.4908117000", \ - "0.0353200000, 0.0438707000, 0.0632091000, 0.1108862000, 0.2379606000, 0.5821871000, 1.4896626000", \ - "0.0366367000, 0.0449891000, 0.0646957000, 0.1121589000, 0.2381979000, 0.5828434000, 1.4961858000", \ - "0.0408228000, 0.0501306000, 0.0695450000, 0.1168287000, 0.2410794000, 0.5832648000, 1.4906318000", \ - "0.0524142000, 0.0623732000, 0.0821483000, 0.1285165000, 0.2470997000, 0.5846276000, 1.4849749000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4b_2") { - leakage_power () { - value : 0.0052725000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0052512000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0056250000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0052734000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0056597000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0052794000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0020549000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0056624000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0057188000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0057122000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0057373000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0057190000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0057417000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0057208000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0060776000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0057426000; - when : "A_N&B&C&!D"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__and4b"; - cell_leakage_power : 0.0053905410; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0063676000, 0.0062571000, 0.0060022000, 0.0060395000, 0.0061253000, 0.0063231000, 0.0067791000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021365000, 0.0020570000, 0.0018738000, 0.0019064000, 0.0019816000, 0.0021549000, 0.0025544000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015880000; - } - pin ("B") { - capacitance : 0.0015670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027000000, 0.0026942000, 0.0026806000, 0.0026834000, 0.0026898000, 0.0027045000, 0.0027385000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002366000, -0.002370300, -0.002380100, -0.002373300, -0.002357700, -0.002321600, -0.002238400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015920000; - } - pin ("C") { - capacitance : 0.0015620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019958000, 0.0019934000, 0.0019881000, 0.0019983000, 0.0020220000, 0.0020764000, 0.0022019000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001917800, -0.001917600, -0.001917000, -0.001916900, -0.001916600, -0.001915900, -0.001914400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015940000; - } - pin ("D") { - capacitance : 0.0015620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022942000, 0.0022930000, 0.0022904000, 0.0022903000, 0.0022902000, 0.0022899000, 0.0022893000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002290900, -0.002289900, -0.002287300, -0.002287200, -0.002286900, -0.002286300, -0.002284800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016250000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0113340000, 0.0098432000, 0.0059461000, -0.005408300, -0.041381200, -0.149643200, -0.465319600", \ - "0.0112524000, 0.0098548000, 0.0059708000, -0.005368100, -0.041384600, -0.149667900, -0.465396200", \ - "0.0112556000, 0.0097650000, 0.0059093000, -0.005396400, -0.041381400, -0.149672400, -0.465365800", \ - "0.0110666000, 0.0095757000, 0.0056701000, -0.005639800, -0.041629800, -0.149926300, -0.465615800", \ - "0.0107654000, 0.0092645000, 0.0053775000, -0.005966900, -0.041942000, -0.150245300, -0.465876300", \ - "0.0130819000, 0.0115546000, 0.0072121000, -0.005383500, -0.042183700, -0.150391500, -0.466073500", \ - "0.0135328000, 0.0119481000, 0.0075527000, -0.004866400, -0.041918100, -0.150292500, -0.466017100"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0167157000, 0.0182698000, 0.0229985000, 0.0365116000, 0.0740536000, 0.1817243000, 0.4965443000", \ - "0.0166718000, 0.0182123000, 0.0229516000, 0.0364641000, 0.0739603000, 0.1817162000, 0.4942168000", \ - "0.0167434000, 0.0183401000, 0.0229590000, 0.0364513000, 0.0740623000, 0.1817580000, 0.4964218000", \ - "0.0166215000, 0.0182187000, 0.0228363000, 0.0363313000, 0.0739405000, 0.1816461000, 0.4962615000", \ - "0.0164635000, 0.0180308000, 0.0227809000, 0.0362822000, 0.0737815000, 0.1815084000, 0.4939706000", \ - "0.0164106000, 0.0179520000, 0.0226622000, 0.0361053000, 0.0737675000, 0.1814519000, 0.4941898000", \ - "0.0175390000, 0.0189928000, 0.0234472000, 0.0365186000, 0.0736401000, 0.1817454000, 0.4956846000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0115855000, 0.0100868000, 0.0061185000, -0.005365800, -0.041456700, -0.149684300, -0.465289200", \ - "0.0115623000, 0.0100532000, 0.0060901000, -0.005397800, -0.041473100, -0.149679300, -0.465349700", \ - "0.0114401000, 0.0099301000, 0.0060148000, -0.005488800, -0.041532800, -0.149822000, -0.465450800", \ - "0.0112820000, 0.0097847000, 0.0058428000, -0.005630300, -0.041717100, -0.149944800, -0.465593700", \ - "0.0111165000, 0.0096003000, 0.0056259000, -0.005971700, -0.042147400, -0.150312500, -0.465840400", \ - "0.0113203000, 0.0097201000, 0.0055663000, -0.006170600, -0.042346900, -0.150376000, -0.465864300", \ - "0.0150071000, 0.0131979000, 0.0083472000, -0.004848900, -0.042301800, -0.150461400, -0.465806600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0170688000, 0.0186337000, 0.0233272000, 0.0368576000, 0.0743410000, 0.1819551000, 0.4965675000", \ - "0.0170404000, 0.0186281000, 0.0233074000, 0.0368407000, 0.0743421000, 0.1819963000, 0.4964890000", \ - "0.0170433000, 0.0187005000, 0.0233863000, 0.0367434000, 0.0742028000, 0.1818478000, 0.4970424000", \ - "0.0168758000, 0.0184554000, 0.0231210000, 0.0365877000, 0.0741921000, 0.1818624000, 0.4942586000", \ - "0.0168967000, 0.0184752000, 0.0231330000, 0.0365434000, 0.0740910000, 0.1818020000, 0.4947563000", \ - "0.0173136000, 0.0187736000, 0.0230677000, 0.0364586000, 0.0737660000, 0.1816584000, 0.4943153000", \ - "0.0186879000, 0.0201047000, 0.0244145000, 0.0373536000, 0.0744955000, 0.1820769000, 0.4931123000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0133765000, 0.0118916000, 0.0079414000, -0.003540400, -0.039592000, -0.147772900, -0.463345400", \ - "0.0133613000, 0.0118692000, 0.0078786000, -0.003662100, -0.039682900, -0.147841500, -0.463407500", \ - "0.0131855000, 0.0116936000, 0.0077333000, -0.003765700, -0.039819000, -0.147884400, -0.463465400", \ - "0.0131628000, 0.0116362000, 0.0076443000, -0.003890700, -0.039873400, -0.148042200, -0.463615900", \ - "0.0128975000, 0.0113781000, 0.0073772000, -0.004148900, -0.040236400, -0.148325700, -0.463810500", \ - "0.0132917000, 0.0116750000, 0.0080421000, -0.004279000, -0.040128500, -0.148342800, -0.463786900", \ - "0.0168788000, 0.0150612000, 0.0102256000, -0.003041400, -0.040507900, -0.148574700, -0.463867900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0170091000, 0.0186173000, 0.0232386000, 0.0367680000, 0.0740333000, 0.1816540000, 0.4944804000", \ - "0.0169704000, 0.0184924000, 0.0231510000, 0.0366279000, 0.0741889000, 0.1817433000, 0.4939210000", \ - "0.0169221000, 0.0185212000, 0.0232601000, 0.0366348000, 0.0740761000, 0.1816426000, 0.4967446000", \ - "0.0167860000, 0.0183498000, 0.0230868000, 0.0365821000, 0.0739784000, 0.1816385000, 0.4945169000", \ - "0.0167328000, 0.0183490000, 0.0229883000, 0.0364062000, 0.0738640000, 0.1815212000, 0.4941195000", \ - "0.0175295000, 0.0189834000, 0.0232926000, 0.0362802000, 0.0736917000, 0.1813139000, 0.4938601000", \ - "0.0185320000, 0.0199644000, 0.0242791000, 0.0370895000, 0.0744508000, 0.1821174000, 0.4922133000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0145708000, 0.0130001000, 0.0090123000, -0.002637500, -0.038934500, -0.147306900, -0.463001500", \ - "0.0144624000, 0.0129794000, 0.0089313000, -0.002730200, -0.038981500, -0.147415800, -0.463080800", \ - "0.0143977000, 0.0128620000, 0.0088118000, -0.002848100, -0.039088700, -0.147517100, -0.463185100", \ - "0.0142739000, 0.0127321000, 0.0087608000, -0.002899800, -0.039197800, -0.147585800, -0.463238000", \ - "0.0141122000, 0.0126065000, 0.0085398000, -0.003149600, -0.039397000, -0.147759900, -0.463411100", \ - "0.0146397000, 0.0130331000, 0.0088462000, -0.002987100, -0.039375400, -0.147785100, -0.463400100", \ - "0.0182522000, 0.0165612000, 0.0116075000, -0.001658500, -0.039306300, -0.147491000, -0.463075000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0173639000, 0.0189258000, 0.0236027000, 0.0371386000, 0.0745954000, 0.1820488000, 0.4963531000", \ - "0.0173455000, 0.0189377000, 0.0236098000, 0.0370915000, 0.0745595000, 0.1820326000, 0.4962090000", \ - "0.0172660000, 0.0188545000, 0.0235046000, 0.0370232000, 0.0745196000, 0.1819913000, 0.4968827000", \ - "0.0171935000, 0.0187774000, 0.0234070000, 0.0367840000, 0.0743769000, 0.1818201000, 0.4940063000", \ - "0.0170680000, 0.0186147000, 0.0232273000, 0.0366704000, 0.0741956000, 0.1816654000, 0.4966651000", \ - "0.0177392000, 0.0192565000, 0.0236227000, 0.0365307000, 0.0739723000, 0.1816477000, 0.4939325000", \ - "0.0184956000, 0.0199443000, 0.0246233000, 0.0376247000, 0.0748681000, 0.1821242000, 0.4919244000"); - } - } - max_capacitance : 0.2975560000; - max_transition : 1.5041630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1854323000, 0.1916643000, 0.2055912000, 0.2334226000, 0.2872628000, 0.4072249000, 0.7263872000", \ - "0.1902967000, 0.1964805000, 0.2104137000, 0.2383833000, 0.2922940000, 0.4120202000, 0.7315418000", \ - "0.2015746000, 0.2077710000, 0.2217160000, 0.2492759000, 0.3033958000, 0.4230667000, 0.7429569000", \ - "0.2219690000, 0.2281508000, 0.2421183000, 0.2698985000, 0.3238245000, 0.4435596000, 0.7634149000", \ - "0.2501778000, 0.2563984000, 0.2703920000, 0.2982409000, 0.3522472000, 0.4719156000, 0.7915857000", \ - "0.2844410000, 0.2906646000, 0.3046305000, 0.3324132000, 0.3867643000, 0.5065851000, 0.8265593000", \ - "0.3146760000, 0.3209448000, 0.3348603000, 0.3628345000, 0.4171005000, 0.5372576000, 0.8561687000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2252908000, 0.2338512000, 0.2540956000, 0.2961210000, 0.3885084000, 0.6247314000, 1.3002843000", \ - "0.2298833000, 0.2385934000, 0.2586580000, 0.3007996000, 0.3931636000, 0.6291302000, 1.3077806000", \ - "0.2424691000, 0.2512344000, 0.2712849000, 0.3132637000, 0.4056846000, 0.6419154000, 1.3184195000", \ - "0.2743155000, 0.2830781000, 0.3031258000, 0.3451036000, 0.4375219000, 0.6737513000, 1.3505880000", \ - "0.3386526000, 0.3474297000, 0.3675145000, 0.4095883000, 0.5019691000, 0.7380977000, 1.4156667000", \ - "0.4457033000, 0.4543576000, 0.4744121000, 0.5166949000, 0.6091424000, 0.8454450000, 1.5173504000", \ - "0.6162983000, 0.6249223000, 0.6453434000, 0.6875033000, 0.7801802000, 1.0166352000, 1.6907371000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0295475000, 0.0332805000, 0.0421448000, 0.0617004000, 0.1100525000, 0.2455434000, 0.6667281000", \ - "0.0293288000, 0.0331683000, 0.0421222000, 0.0618339000, 0.1101088000, 0.2463434000, 0.6663264000", \ - "0.0292935000, 0.0331233000, 0.0421120000, 0.0626603000, 0.1103962000, 0.2465401000, 0.6665878000", \ - "0.0295705000, 0.0335304000, 0.0421286000, 0.0624281000, 0.1103018000, 0.2465528000, 0.6669983000", \ - "0.0297372000, 0.0334977000, 0.0428436000, 0.0620175000, 0.1103188000, 0.2464559000, 0.6682377000", \ - "0.0295421000, 0.0335364000, 0.0422834000, 0.0625134000, 0.1102812000, 0.2452300000, 0.6682171000", \ - "0.0297483000, 0.0337317000, 0.0425862000, 0.0626846000, 0.1103373000, 0.2456451000, 0.6676036000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0372768000, 0.0438046000, 0.0600171000, 0.0986385000, 0.2051710000, 0.5297508000, 1.5000846000", \ - "0.0373795000, 0.0439780000, 0.0598709000, 0.0986244000, 0.2055082000, 0.5287201000, 1.4984761000", \ - "0.0372444000, 0.0438487000, 0.0600537000, 0.0986096000, 0.2050748000, 0.5297604000, 1.4986776000", \ - "0.0372566000, 0.0438579000, 0.0600572000, 0.0986345000, 0.2050221000, 0.5297692000, 1.4981525000", \ - "0.0371590000, 0.0438023000, 0.0598278000, 0.0985903000, 0.2053823000, 0.5294271000, 1.4973084000", \ - "0.0375805000, 0.0444584000, 0.0603981000, 0.0986571000, 0.2056552000, 0.5287979000, 1.4981143000", \ - "0.0381444000, 0.0451772000, 0.0609926000, 0.0994203000, 0.2058902000, 0.5286729000, 1.4976135000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1693743000, 0.1757046000, 0.1898627000, 0.2177300000, 0.2723088000, 0.3922400000, 0.7119628000", \ - "0.1749811000, 0.1813112000, 0.1954915000, 0.2235783000, 0.2779512000, 0.3978618000, 0.7177253000", \ - "0.1886964000, 0.1950276000, 0.2090499000, 0.2371325000, 0.2914902000, 0.4115620000, 0.7308621000", \ - "0.2198706000, 0.2261666000, 0.2403271000, 0.2683807000, 0.3225910000, 0.4428944000, 0.7623592000", \ - "0.2966989000, 0.3030334000, 0.3171495000, 0.3451191000, 0.3996155000, 0.5197919000, 0.8394336000", \ - "0.4599038000, 0.4670913000, 0.4829004000, 0.5133979000, 0.5699877000, 0.6894478000, 1.0089541000", \ - "0.7328418000, 0.7422394000, 0.7629500000, 0.8029101000, 0.8717806000, 1.0022386000, 1.3241571000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1696809000, 0.1784533000, 0.1984253000, 0.2405804000, 0.3328248000, 0.5688684000, 1.2443987000", \ - "0.1738136000, 0.1825652000, 0.2025722000, 0.2447156000, 0.3369656000, 0.5730698000, 1.2491631000", \ - "0.1823051000, 0.1910781000, 0.2111340000, 0.2531123000, 0.3455236000, 0.5816478000, 1.2546555000", \ - "0.2015960000, 0.2103852000, 0.2304915000, 0.2724714000, 0.3648263000, 0.6006914000, 1.2801135000", \ - "0.2450752000, 0.2539062000, 0.2741727000, 0.3164283000, 0.4089041000, 0.6449759000, 1.3172458000", \ - "0.3171626000, 0.3269917000, 0.3489286000, 0.3935539000, 0.4885306000, 0.7257832000, 1.4015310000", \ - "0.4011669000, 0.4132261000, 0.4402266000, 0.4913154000, 0.5904707000, 0.8289321000, 1.5028981000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0305389000, 0.0344112000, 0.0431393000, 0.0635415000, 0.1107859000, 0.2467622000, 0.6686950000", \ - "0.0304524000, 0.0343049000, 0.0432870000, 0.0633581000, 0.1109591000, 0.2466962000, 0.6688425000", \ - "0.0304825000, 0.0344197000, 0.0434941000, 0.0635321000, 0.1109110000, 0.2471469000, 0.6650916000", \ - "0.0304092000, 0.0348473000, 0.0433736000, 0.0636679000, 0.1107961000, 0.2463882000, 0.6637940000", \ - "0.0304986000, 0.0343986000, 0.0432241000, 0.0635238000, 0.1107752000, 0.2469811000, 0.6639732000", \ - "0.0386707000, 0.0427507000, 0.0516107000, 0.0702536000, 0.1151936000, 0.2481850000, 0.6688780000", \ - "0.0589264000, 0.0640636000, 0.0750187000, 0.0961797000, 0.1401615000, 0.2628209000, 0.6690163000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0370939000, 0.0437886000, 0.0602576000, 0.0985572000, 0.2053372000, 0.5297920000, 1.5003335000", \ - "0.0371512000, 0.0437301000, 0.0602746000, 0.0986068000, 0.2053921000, 0.5298144000, 1.4994763000", \ - "0.0376259000, 0.0440152000, 0.0597639000, 0.0987770000, 0.2054539000, 0.5284748000, 1.5032752000", \ - "0.0371256000, 0.0437778000, 0.0600266000, 0.0985777000, 0.2053375000, 0.5285694000, 1.4994963000", \ - "0.0384455000, 0.0450836000, 0.0606285000, 0.0993452000, 0.2053427000, 0.5293687000, 1.4991475000", \ - "0.0447620000, 0.0515552000, 0.0676765000, 0.1058027000, 0.2102127000, 0.5310212000, 1.4991614000", \ - "0.0601660000, 0.0678883000, 0.0846363000, 0.1223318000, 0.2191529000, 0.5339348000, 1.4956130000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1826513000, 0.1891035000, 0.2035396000, 0.2321806000, 0.2870345000, 0.4071599000, 0.7270882000", \ - "0.1880046000, 0.1944608000, 0.2088009000, 0.2371530000, 0.2921560000, 0.4126554000, 0.7329005000", \ - "0.2015835000, 0.2080942000, 0.2225041000, 0.2510261000, 0.3058183000, 0.4262653000, 0.7466212000", \ - "0.2333232000, 0.2398038000, 0.2542725000, 0.2833450000, 0.3373383000, 0.4579282000, 0.7780446000", \ - "0.3104364000, 0.3169131000, 0.3313189000, 0.3599178000, 0.4147248000, 0.5353608000, 0.8553588000", \ - "0.4792181000, 0.4863728000, 0.5020489000, 0.5325191000, 0.5883549000, 0.7096027000, 1.0300711000", \ - "0.7676511000, 0.7769703000, 0.7975593000, 0.8365630000, 0.9046207000, 1.0342652000, 1.3560427000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1763888000, 0.1852822000, 0.2052502000, 0.2472774000, 0.3395922000, 0.5750693000, 1.2486936000", \ - "0.1806931000, 0.1894090000, 0.2093385000, 0.2515703000, 0.3437995000, 0.5791361000, 1.2563220000", \ - "0.1891211000, 0.1978852000, 0.2179653000, 0.2599408000, 0.3523046000, 0.5882481000, 1.2614666000", \ - "0.2053706000, 0.2141608000, 0.2342450000, 0.2763012000, 0.3686152000, 0.6039708000, 1.2779151000", \ - "0.2406144000, 0.2494945000, 0.2696920000, 0.3119314000, 0.4044348000, 0.6400469000, 1.3165308000", \ - "0.3006244000, 0.3103293000, 0.3322406000, 0.3766865000, 0.4715551000, 0.7085835000, 1.3857259000", \ - "0.3729904000, 0.3846903000, 0.4108758000, 0.4613206000, 0.5609823000, 0.7994982000, 1.4730762000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0317729000, 0.0355528000, 0.0444359000, 0.0642405000, 0.1117541000, 0.2471389000, 0.6689821000", \ - "0.0316785000, 0.0356106000, 0.0453170000, 0.0648974000, 0.1119164000, 0.2479018000, 0.6684657000", \ - "0.0320461000, 0.0356689000, 0.0444329000, 0.0646208000, 0.1120502000, 0.2471844000, 0.6685787000", \ - "0.0316833000, 0.0356864000, 0.0447690000, 0.0640028000, 0.1120302000, 0.2473612000, 0.6693344000", \ - "0.0316145000, 0.0357996000, 0.0444518000, 0.0639674000, 0.1117358000, 0.2477267000, 0.6649815000", \ - "0.0386794000, 0.0420660000, 0.0513890000, 0.0689939000, 0.1149857000, 0.2482657000, 0.6687308000", \ - "0.0584875000, 0.0627784000, 0.0735269000, 0.0943608000, 0.1389034000, 0.2622665000, 0.6699959000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0373216000, 0.0439155000, 0.0599615000, 0.0986083000, 0.2056478000, 0.5295220000, 1.4991867000", \ - "0.0371932000, 0.0436763000, 0.0601669000, 0.0987577000, 0.2051638000, 0.5289083000, 1.4967646000", \ - "0.0373106000, 0.0437542000, 0.0598017000, 0.0987439000, 0.2055118000, 0.5281925000, 1.5032086000", \ - "0.0371879000, 0.0437427000, 0.0599554000, 0.0986072000, 0.2056596000, 0.5289930000, 1.5002138000", \ - "0.0383987000, 0.0447600000, 0.0605246000, 0.0992606000, 0.2054176000, 0.5295789000, 1.4984822000", \ - "0.0433584000, 0.0499835000, 0.0659068000, 0.1049355000, 0.2094107000, 0.5307033000, 1.4971450000", \ - "0.0562494000, 0.0636734000, 0.0813292000, 0.1186099000, 0.2189514000, 0.5343453000, 1.4962515000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2007484000, 0.2073963000, 0.2222589000, 0.2513625000, 0.3069477000, 0.4285231000, 0.7489542000", \ - "0.2058514000, 0.2125913000, 0.2273808000, 0.2564884000, 0.3121244000, 0.4336219000, 0.7544776000", \ - "0.2186255000, 0.2253066000, 0.2400758000, 0.2691836000, 0.3248519000, 0.4463642000, 0.7672448000", \ - "0.2506362000, 0.2573147000, 0.2720195000, 0.3010497000, 0.3568999000, 0.4784511000, 0.7993523000", \ - "0.3275890000, 0.3342867000, 0.3490277000, 0.3781239000, 0.4339328000, 0.5556045000, 0.8759863000", \ - "0.5004105000, 0.5075618000, 0.5233279000, 0.5531682000, 0.6095078000, 0.7315735000, 1.0524147000", \ - "0.7995058000, 0.8094653000, 0.8292286000, 0.8683747000, 0.9365032000, 1.0656708000, 1.3875062000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1839427000, 0.1926996000, 0.2126963000, 0.2548483000, 0.3470520000, 0.5827191000, 1.2580570000", \ - "0.1882465000, 0.1969962000, 0.2169876000, 0.2590772000, 0.3513020000, 0.5867647000, 1.2628248000", \ - "0.1962038000, 0.2050490000, 0.2249729000, 0.2670887000, 0.3593514000, 0.5951206000, 1.2664316000", \ - "0.2111112000, 0.2199172000, 0.2397661000, 0.2817859000, 0.3741077000, 0.6097290000, 1.2861011000", \ - "0.2393480000, 0.2481789000, 0.2682830000, 0.3106106000, 0.4030254000, 0.6390042000, 1.3117970000", \ - "0.2858349000, 0.2953821000, 0.3169285000, 0.3615675000, 0.4562579000, 0.6929257000, 1.3699949000", \ - "0.3447856000, 0.3558134000, 0.3810263000, 0.4302276000, 0.5296761000, 0.7684513000, 1.4416086000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0337966000, 0.0381957000, 0.0467267000, 0.0671872000, 0.1149155000, 0.2492591000, 0.6697956000", \ - "0.0337676000, 0.0378568000, 0.0467210000, 0.0672282000, 0.1146456000, 0.2491777000, 0.6679050000", \ - "0.0338126000, 0.0378523000, 0.0467187000, 0.0671914000, 0.1146901000, 0.2492332000, 0.6679192000", \ - "0.0338774000, 0.0380995000, 0.0479026000, 0.0675452000, 0.1145505000, 0.2496844000, 0.6700064000", \ - "0.0338839000, 0.0379143000, 0.0467461000, 0.0669481000, 0.1143434000, 0.2496032000, 0.6658243000", \ - "0.0386994000, 0.0426345000, 0.0511888000, 0.0699372000, 0.1162679000, 0.2495787000, 0.6691943000", \ - "0.0586719000, 0.0632318000, 0.0742781000, 0.0942698000, 0.1388747000, 0.2621102000, 0.6699224000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0371880000, 0.0437341000, 0.0602705000, 0.0985791000, 0.2053482000, 0.5298142000, 1.4999101000", \ - "0.0372103000, 0.0440963000, 0.0601257000, 0.0986509000, 0.2051873000, 0.5291707000, 1.4986314000", \ - "0.0371199000, 0.0440726000, 0.0602480000, 0.0986615000, 0.2054480000, 0.5297999000, 1.5041627000", \ - "0.0373031000, 0.0439792000, 0.0600684000, 0.0986485000, 0.2052316000, 0.5296700000, 1.4974311000", \ - "0.0382897000, 0.0447001000, 0.0605597000, 0.0993726000, 0.2055282000, 0.5290334000, 1.5033129000", \ - "0.0419179000, 0.0489719000, 0.0656130000, 0.1040659000, 0.2089059000, 0.5305738000, 1.4974448000", \ - "0.0517494000, 0.0595721000, 0.0769197000, 0.1156798000, 0.2176584000, 0.5330623000, 1.4956291000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4b_4") { - leakage_power () { - value : 0.0035608000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0035400000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0039067000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0035623000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0039328000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0035682000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0062576000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0039416000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0038140000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0038076000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0038322000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0038144000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0038361000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0038162000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0041360000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0038376000; - when : "A_N&B&C&!D"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__and4b"; - cell_leakage_power : 0.0039477660; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076431000, 0.0075521000, 0.0073424000, 0.0073840000, 0.0074801000, 0.0077015000, 0.0082119000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055745000, 0.0055170000, 0.0053845000, 0.0054162000, 0.0054895000, 0.0056584000, 0.0060478000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016000000; - } - pin ("B") { - capacitance : 0.0022910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045252000, 0.0045238000, 0.0045207000, 0.0045254000, 0.0045363000, 0.0045615000, 0.0046195000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004124800, -0.004125300, -0.004126700, -0.004115100, -0.004088400, -0.004026900, -0.003885000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023760000; - } - pin ("C") { - capacitance : 0.0023140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040518000, 0.0040494000, 0.0040440000, 0.0040588000, 0.0040930000, 0.0041717000, 0.0043533000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003960700, -0.003960400, -0.003959600, -0.003958900, -0.003957300, -0.003953700, -0.003945200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024140000; - } - pin ("D") { - capacitance : 0.0023350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041830000, 0.0041802000, 0.0041738000, 0.0041721000, 0.0041683000, 0.0041594000, 0.0041389000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004183500, -0.004180900, -0.004174800, -0.004174700, -0.004174500, -0.004174100, -0.004173200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024690000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&B&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0223359000, 0.0207418000, 0.0158172000, 0.0015119000, -0.047630400, -0.209620500, -0.719415700", \ - "0.0223333000, 0.0207839000, 0.0158226000, 0.0015172000, -0.047649200, -0.209606300, -0.719383400", \ - "0.0222878000, 0.0207538000, 0.0158772000, 0.0014559000, -0.047618800, -0.209571400, -0.719327200", \ - "0.0220570000, 0.0204046000, 0.0155585000, 0.0011406000, -0.047904900, -0.209842400, -0.719617300", \ - "0.0216661000, 0.0201458000, 0.0152243000, 0.0007462000, -0.048303300, -0.210320500, -0.720055100", \ - "0.0254464000, 0.0238305000, 0.0187257000, 0.0027760000, -0.048583500, -0.210617000, -0.720348900", \ - "0.0260178000, 0.0242974000, 0.0191326000, 0.0032420000, -0.047966700, -0.210474000, -0.720368800"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0302561000, 0.0319710000, 0.0374194000, 0.0548139000, 0.1077208000, 0.2694500000, 0.7739470000", \ - "0.0302592000, 0.0319326000, 0.0373755000, 0.0549316000, 0.1074917000, 0.2692340000, 0.7740175000", \ - "0.0302846000, 0.0319826000, 0.0374697000, 0.0548351000, 0.1076834000, 0.2694457000, 0.7745858000", \ - "0.0300305000, 0.0317307000, 0.0371813000, 0.0547233000, 0.1073006000, 0.2690301000, 0.7738081000", \ - "0.0297475000, 0.0314409000, 0.0369074000, 0.0543453000, 0.1071518000, 0.2689120000, 0.7741094000", \ - "0.0294920000, 0.0312107000, 0.0365968000, 0.0540882000, 0.1066341000, 0.2684664000, 0.7739427000", \ - "0.0313053000, 0.0330039000, 0.0383965000, 0.0549329000, 0.1068928000, 0.2685232000, 0.7726460000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0228341000, 0.0211371000, 0.0162042000, 0.0016792000, -0.047373200, -0.209334700, -0.718956600", \ - "0.0228605000, 0.0211837000, 0.0161888000, 0.0016782000, -0.047412700, -0.209332400, -0.719050900", \ - "0.0227131000, 0.0210939000, 0.0160115000, 0.0014762000, -0.047609800, -0.209478900, -0.719199500", \ - "0.0224460000, 0.0207424000, 0.0157367000, 0.0012051000, -0.047931200, -0.209704500, -0.719407400", \ - "0.0225001000, 0.0208071000, 0.0156994000, 0.0009105000, -0.048423400, -0.210217300, -0.719793900", \ - "0.0224858000, 0.0206985000, 0.0153159000, 0.0012175000, -0.048368800, -0.210144700, -0.719608600", \ - "0.0294334000, 0.0274008000, 0.0214545000, 0.0041813000, -0.047983000, -0.210169200, -0.719248900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0307641000, 0.0324742000, 0.0380072000, 0.0553269000, 0.1079004000, 0.2695186000, 0.7739668000", \ - "0.0307518000, 0.0324803000, 0.0379974000, 0.0552287000, 0.1077895000, 0.2694910000, 0.7738703000", \ - "0.0306333000, 0.0323551000, 0.0378791000, 0.0551122000, 0.1077108000, 0.2693288000, 0.7743770000", \ - "0.0303100000, 0.0320569000, 0.0374933000, 0.0549395000, 0.1075859000, 0.2693470000, 0.7745035000", \ - "0.0301647000, 0.0318703000, 0.0372660000, 0.0547568000, 0.1073578000, 0.2689592000, 0.7736338000", \ - "0.0303016000, 0.0323885000, 0.0377135000, 0.0550660000, 0.1067219000, 0.2686673000, 0.7734386000", \ - "0.0335410000, 0.0351157000, 0.0402001000, 0.0566599000, 0.1085491000, 0.2695395000, 0.7721936000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0255338000, 0.0238126000, 0.0188401000, 0.0043988000, -0.044643000, -0.206437000, -0.715965100", \ - "0.0254604000, 0.0238454000, 0.0186445000, 0.0042429000, -0.044822100, -0.206518800, -0.716122400", \ - "0.0252806000, 0.0235803000, 0.0186267000, 0.0040751000, -0.044939400, -0.206661900, -0.716237000", \ - "0.0251149000, 0.0233774000, 0.0183456000, 0.0037849000, -0.045101600, -0.206913900, -0.716501500", \ - "0.0254017000, 0.0237114000, 0.0180726000, 0.0034043000, -0.045519100, -0.207200900, -0.716770900", \ - "0.0256829000, 0.0238478000, 0.0180988000, 0.0039868000, -0.045876100, -0.207305000, -0.716524300", \ - "0.0323519000, 0.0302980000, 0.0240330000, 0.0067959000, -0.045252300, -0.207386200, -0.716442800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0308536000, 0.0325523000, 0.0381128000, 0.0554672000, 0.1081826000, 0.2694522000, 0.7734836000", \ - "0.0308055000, 0.0324805000, 0.0381579000, 0.0554098000, 0.1079961000, 0.2694204000, 0.7734830000", \ - "0.0306964000, 0.0323754000, 0.0377931000, 0.0553137000, 0.1078761000, 0.2693436000, 0.7734626000", \ - "0.0304424000, 0.0321100000, 0.0376101000, 0.0549990000, 0.1078191000, 0.2691151000, 0.7733955000", \ - "0.0302994000, 0.0319559000, 0.0375509000, 0.0548856000, 0.1073940000, 0.2690168000, 0.7703157000", \ - "0.0309223000, 0.0325654000, 0.0376783000, 0.0549287000, 0.1072062000, 0.2686668000, 0.7735851000", \ - "0.0330271000, 0.0346143000, 0.0397519000, 0.0562510000, 0.1083729000, 0.2693079000, 0.7719048000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0273260000, 0.0255816000, 0.0205174000, 0.0057129000, -0.043704300, -0.205792400, -0.715496400", \ - "0.0271805000, 0.0255162000, 0.0204121000, 0.0056520000, -0.043808700, -0.205890400, -0.715618400", \ - "0.0271776000, 0.0254632000, 0.0202670000, 0.0055101000, -0.043937600, -0.206007500, -0.715741300", \ - "0.0268638000, 0.0251908000, 0.0200820000, 0.0052748000, -0.044120000, -0.206221400, -0.715832800", \ - "0.0269105000, 0.0251610000, 0.0200967000, 0.0052303000, -0.044211700, -0.206371900, -0.716025800", \ - "0.0272273000, 0.0254376000, 0.0206316000, 0.0054717000, -0.044080300, -0.206170100, -0.715890700", \ - "0.0355552000, 0.0335058000, 0.0267659000, 0.0094473000, -0.043135500, -0.205173600, -0.714928300"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015611580, 0.0048744290, 0.0152195000, 0.0475201000, 0.1483728000, 0.4632667000"); - values("0.0310742000, 0.0327557000, 0.0383334000, 0.0556858000, 0.1084085000, 0.2695266000, 0.7732776000", \ - "0.0309705000, 0.0326538000, 0.0381670000, 0.0555019000, 0.1083672000, 0.2694391000, 0.7732308000", \ - "0.0309720000, 0.0326899000, 0.0382358000, 0.0554923000, 0.1080444000, 0.2693969000, 0.7733044000", \ - "0.0306114000, 0.0323173000, 0.0377904000, 0.0551965000, 0.1078832000, 0.2691622000, 0.7731440000", \ - "0.0304038000, 0.0321199000, 0.0376012000, 0.0548226000, 0.1077173000, 0.2689556000, 0.7738895000", \ - "0.0311095000, 0.0327474000, 0.0380459000, 0.0550909000, 0.1074798000, 0.2690655000, 0.7732735000", \ - "0.0333576000, 0.0343875000, 0.0395869000, 0.0564392000, 0.1083980000, 0.2692772000, 0.7720187000"); - } - } - max_capacitance : 0.4632670000; - max_transition : 1.5040990000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1655257000, 0.1692213000, 0.1785461000, 0.1990895000, 0.2411548000, 0.3376517000, 0.6082960000", \ - "0.1702919000, 0.1740108000, 0.1833774000, 0.2039145000, 0.2460132000, 0.3425129000, 0.6131275000", \ - "0.1816404000, 0.1853266000, 0.1946941000, 0.2151943000, 0.2572699000, 0.3539274000, 0.6241477000", \ - "0.2046757000, 0.2083579000, 0.2176654000, 0.2381867000, 0.2802772000, 0.3769525000, 0.6471833000", \ - "0.2383196000, 0.2419707000, 0.2512747000, 0.2718201000, 0.3141428000, 0.4105596000, 0.6810267000", \ - "0.2793566000, 0.2830589000, 0.2924007000, 0.3129524000, 0.3551647000, 0.4517505000, 0.7224202000", \ - "0.3179544000, 0.3216339000, 0.3310500000, 0.3515443000, 0.3939879000, 0.4907794000, 0.7608854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.2740234000, 0.2805126000, 0.2968185000, 0.3342082000, 0.4201837000, 0.6480741000, 1.3456551000", \ - "0.2790441000, 0.2854679000, 0.3018232000, 0.3392962000, 0.4252440000, 0.6528900000, 1.3524006000", \ - "0.2918267000, 0.2982152000, 0.3145438000, 0.3521873000, 0.4379980000, 0.6658695000, 1.3603587000", \ - "0.3232196000, 0.3297024000, 0.3460431000, 0.3835831000, 0.4694500000, 0.6972302000, 1.3969325000", \ - "0.3954079000, 0.4017965000, 0.4181594000, 0.4556025000, 0.5415799000, 0.7694755000, 1.4639316000", \ - "0.5274939000, 0.5339005000, 0.5501310000, 0.5877021000, 0.6736387000, 0.9016191000, 1.5967325000", \ - "0.7420825000, 0.7483945000, 0.7648243000, 0.8033475000, 0.8896812000, 1.1179423000, 1.8134921000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0237045000, 0.0260217000, 0.0320655000, 0.0463065000, 0.0833730000, 0.1914019000, 0.5482287000", \ - "0.0237588000, 0.0260477000, 0.0320072000, 0.0462729000, 0.0833344000, 0.1912338000, 0.5481445000", \ - "0.0237980000, 0.0260487000, 0.0322380000, 0.0466676000, 0.0833507000, 0.1909245000, 0.5472376000", \ - "0.0238513000, 0.0261468000, 0.0319191000, 0.0466082000, 0.0833352000, 0.1913098000, 0.5470382000", \ - "0.0237711000, 0.0263384000, 0.0320107000, 0.0464780000, 0.0833767000, 0.1912107000, 0.5484428000", \ - "0.0239893000, 0.0262452000, 0.0324803000, 0.0463885000, 0.0835093000, 0.1911402000, 0.5454827000", \ - "0.0246496000, 0.0268020000, 0.0327528000, 0.0475417000, 0.0838649000, 0.1916941000, 0.5452599000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0386428000, 0.0434578000, 0.0567438000, 0.0899304000, 0.1858757000, 0.4967630000, 1.5019705000", \ - "0.0385017000, 0.0435126000, 0.0567405000, 0.0898932000, 0.1859397000, 0.4961365000, 1.5009317000", \ - "0.0386214000, 0.0433645000, 0.0566469000, 0.0900285000, 0.1860280000, 0.4967540000, 1.4995477000", \ - "0.0386796000, 0.0434599000, 0.0567329000, 0.0898802000, 0.1859411000, 0.4963497000, 1.5005835000", \ - "0.0385213000, 0.0433648000, 0.0567329000, 0.0897925000, 0.1859693000, 0.4967741000, 1.4983375000", \ - "0.0388607000, 0.0435608000, 0.0563115000, 0.0900060000, 0.1865552000, 0.4965235000, 1.5002241000", \ - "0.0396426000, 0.0448633000, 0.0577898000, 0.0911595000, 0.1870536000, 0.4959785000, 1.5003168000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1472672000, 0.1512692000, 0.1613276000, 0.1830937000, 0.2267653000, 0.3248082000, 0.5953669000", \ - "0.1531407000, 0.1571373000, 0.1671871000, 0.1889972000, 0.2326082000, 0.3306189000, 0.6011269000", \ - "0.1661110000, 0.1700953000, 0.1801277000, 0.2019193000, 0.2455816000, 0.3434304000, 0.6144849000", \ - "0.1977303000, 0.2017359000, 0.2117763000, 0.2333876000, 0.2769776000, 0.3748005000, 0.6458700000", \ - "0.2732063000, 0.2771630000, 0.2871133000, 0.3086867000, 0.3524343000, 0.4504833000, 0.7211977000", \ - "0.4237431000, 0.4285326000, 0.4405050000, 0.4653899000, 0.5127336000, 0.6128787000, 0.8840199000", \ - "0.6681350000, 0.6743613000, 0.6900672000, 0.7232380000, 0.7839625000, 0.8955627000, 1.1704896000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1819428000, 0.1883192000, 0.2046909000, 0.2420687000, 0.3279298000, 0.5550486000, 1.2522551000", \ - "0.1859068000, 0.1922749000, 0.2087009000, 0.2459800000, 0.3318258000, 0.5592357000, 1.2540202000", \ - "0.1938903000, 0.2002903000, 0.2167246000, 0.2539510000, 0.3397388000, 0.5674989000, 1.2600611000", \ - "0.2120310000, 0.2185278000, 0.2347190000, 0.2722011000, 0.3579503000, 0.5857991000, 1.2800915000", \ - "0.2534928000, 0.2599619000, 0.2764544000, 0.3139984000, 0.3997976000, 0.6272142000, 1.3239120000", \ - "0.3236735000, 0.3309639000, 0.3487424000, 0.3884780000, 0.4764787000, 0.7056548000, 1.4043848000", \ - "0.4029403000, 0.4115656000, 0.4329924000, 0.4790052000, 0.5722604000, 0.8031644000, 1.4972911000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0271177000, 0.0295302000, 0.0356861000, 0.0498012000, 0.0863322000, 0.1933414000, 0.5487786000", \ - "0.0271922000, 0.0294124000, 0.0353892000, 0.0497820000, 0.0863083000, 0.1932525000, 0.5462675000", \ - "0.0271870000, 0.0296482000, 0.0354762000, 0.0500840000, 0.0860219000, 0.1934397000, 0.5483983000", \ - "0.0270402000, 0.0294838000, 0.0356956000, 0.0501019000, 0.0862231000, 0.1933866000, 0.5484392000", \ - "0.0272150000, 0.0295082000, 0.0355272000, 0.0498138000, 0.0864243000, 0.1933729000, 0.5471115000", \ - "0.0374535000, 0.0402571000, 0.0462971000, 0.0609390000, 0.0937437000, 0.1968770000, 0.5475157000", \ - "0.0571913000, 0.0607558000, 0.0693128000, 0.0862904000, 0.1197408000, 0.2152541000, 0.5509047000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0386345000, 0.0434197000, 0.0559928000, 0.0899404000, 0.1859629000, 0.4960769000, 1.5033803000", \ - "0.0386023000, 0.0433987000, 0.0564616000, 0.0898769000, 0.1859367000, 0.4965866000, 1.5040992000", \ - "0.0384470000, 0.0435300000, 0.0564734000, 0.0898864000, 0.1857955000, 0.4970924000, 1.5035195000", \ - "0.0385773000, 0.0436097000, 0.0565845000, 0.0897201000, 0.1856594000, 0.4967510000, 1.4985992000", \ - "0.0394922000, 0.0442233000, 0.0567957000, 0.0903224000, 0.1859855000, 0.4963115000, 1.5040026000", \ - "0.0452052000, 0.0501401000, 0.0628793000, 0.0962088000, 0.1903148000, 0.4981197000, 1.5005857000", \ - "0.0599204000, 0.0658552000, 0.0795460000, 0.1127584000, 0.2004076000, 0.5014824000, 1.4993194000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1598824000, 0.1640037000, 0.1742956000, 0.1965965000, 0.2408179000, 0.3391369000, 0.6100311000", \ - "0.1652782000, 0.1693873000, 0.1795562000, 0.2016972000, 0.2460795000, 0.3444171000, 0.6157189000", \ - "0.1784449000, 0.1825537000, 0.1928404000, 0.2150376000, 0.2592530000, 0.3575917000, 0.6288763000", \ - "0.2100049000, 0.2141756000, 0.2243303000, 0.2475250000, 0.2905572000, 0.3900167000, 0.6612210000", \ - "0.2865601000, 0.2906584000, 0.3007312000, 0.3228101000, 0.3673197000, 0.4657921000, 0.7370807000", \ - "0.4449104000, 0.4500335000, 0.4616732000, 0.4862810000, 0.5333838000, 0.6330188000, 0.9040793000", \ - "0.7065307000, 0.7127928000, 0.7284214000, 0.7616177000, 0.8214848000, 0.9325010000, 1.2066066000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1900821000, 0.1964770000, 0.2128847000, 0.2503023000, 0.3361350000, 0.5633206000, 1.2623177000", \ - "0.1941451000, 0.2005303000, 0.2169835000, 0.2543563000, 0.3402030000, 0.5673293000, 1.2663619000", \ - "0.2020007000, 0.2084176000, 0.2247075000, 0.2621905000, 0.3480357000, 0.5751053000, 1.2738400000", \ - "0.2173948000, 0.2237803000, 0.2400982000, 0.2776702000, 0.3634677000, 0.5908597000, 1.2897313000", \ - "0.2510811000, 0.2575430000, 0.2740531000, 0.3115310000, 0.3973223000, 0.6252194000, 1.3180355000", \ - "0.3090554000, 0.3161484000, 0.3338525000, 0.3735899000, 0.4618586000, 0.6906157000, 1.3844053000", \ - "0.3760791000, 0.3843881000, 0.4054190000, 0.4507342000, 0.5441659000, 0.7756609000, 1.4696833000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0282336000, 0.0306372000, 0.0367890000, 0.0509132000, 0.0873310000, 0.1940380000, 0.5484538000", \ - "0.0285178000, 0.0305851000, 0.0368617000, 0.0516378000, 0.0873706000, 0.1941615000, 0.5487811000", \ - "0.0282517000, 0.0307195000, 0.0370759000, 0.0509590000, 0.0874481000, 0.1936730000, 0.5488823000", \ - "0.0282195000, 0.0306541000, 0.0368597000, 0.0510269000, 0.0873093000, 0.1940264000, 0.5489100000", \ - "0.0284760000, 0.0309997000, 0.0366807000, 0.0514909000, 0.0875233000, 0.1939509000, 0.5489582000", \ - "0.0369932000, 0.0398184000, 0.0457990000, 0.0602922000, 0.0924475000, 0.1962834000, 0.5488841000", \ - "0.0570792000, 0.0598163000, 0.0680432000, 0.0849452000, 0.1184751000, 0.2134480000, 0.5502668000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0387843000, 0.0434754000, 0.0567412000, 0.0900083000, 0.1859526000, 0.4962725000, 1.5004628000", \ - "0.0384133000, 0.0431689000, 0.0567045000, 0.0899721000, 0.1859589000, 0.4960242000, 1.5007253000", \ - "0.0387691000, 0.0433585000, 0.0567519000, 0.0898955000, 0.1859621000, 0.4956808000, 1.5012755000", \ - "0.0384190000, 0.0432172000, 0.0566748000, 0.0900528000, 0.1860352000, 0.4964850000, 1.5007632000", \ - "0.0391183000, 0.0440939000, 0.0570013000, 0.0904757000, 0.1860064000, 0.4969191000, 1.4994485000", \ - "0.0438541000, 0.0489927000, 0.0621286000, 0.0957944000, 0.1901564000, 0.4974492000, 1.5032176000", \ - "0.0569473000, 0.0625203000, 0.0764323000, 0.1091322000, 0.2003624000, 0.5022640000, 1.4977263000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1703924000, 0.1746238000, 0.1852005000, 0.2078559000, 0.2526948000, 0.3518864000, 0.6235985000", \ - "0.1756482000, 0.1798880000, 0.1905012000, 0.2131448000, 0.2579433000, 0.3571783000, 0.6289220000", \ - "0.1887056000, 0.1929312000, 0.2035388000, 0.2261597000, 0.2710401000, 0.3702304000, 0.6419421000", \ - "0.2214490000, 0.2256888000, 0.2360500000, 0.2586264000, 0.3036370000, 0.4031923000, 0.6749369000", \ - "0.2974455000, 0.3016451000, 0.3113461000, 0.3338336000, 0.3787900000, 0.4791391000, 0.7509763000", \ - "0.4607797000, 0.4656041000, 0.4778132000, 0.5012605000, 0.5486200000, 0.6496590000, 0.9209631000", \ - "0.7337808000, 0.7400771000, 0.7555881000, 0.7884797000, 0.8481505000, 0.9584638000, 1.2330719000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.1953068000, 0.2017054000, 0.2181136000, 0.2555299000, 0.3413622000, 0.5684230000, 1.2671498000", \ - "0.1993552000, 0.2057018000, 0.2220533000, 0.2596512000, 0.3454369000, 0.5726191000, 1.2713636000", \ - "0.2070770000, 0.2134600000, 0.2298464000, 0.2672144000, 0.3530631000, 0.5798297000, 1.2767732000", \ - "0.2209338000, 0.2273293000, 0.2436994000, 0.2811823000, 0.3669674000, 0.5941277000, 1.2923499000", \ - "0.2482619000, 0.2546455000, 0.2711980000, 0.3086491000, 0.3945338000, 0.6217959000, 1.3157568000", \ - "0.2937604000, 0.3006667000, 0.3182642000, 0.3579911000, 0.4459804000, 0.6749634000, 1.3723715000", \ - "0.3471915000, 0.3548088000, 0.3750801000, 0.4198400000, 0.5127124000, 0.7444381000, 1.4374689000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0298297000, 0.0323410000, 0.0384417000, 0.0527523000, 0.0894812000, 0.1956249000, 0.5490221000", \ - "0.0299085000, 0.0325093000, 0.0383869000, 0.0534119000, 0.0892770000, 0.1953641000, 0.5495853000", \ - "0.0300993000, 0.0326243000, 0.0384206000, 0.0534473000, 0.0893548000, 0.1952563000, 0.5494445000", \ - "0.0300989000, 0.0325956000, 0.0387953000, 0.0530265000, 0.0896082000, 0.1957630000, 0.5484533000", \ - "0.0297929000, 0.0321841000, 0.0384756000, 0.0533909000, 0.0893273000, 0.1957141000, 0.5492208000", \ - "0.0379693000, 0.0400796000, 0.0468058000, 0.0599186000, 0.0938796000, 0.1974113000, 0.5494449000", \ - "0.0574852000, 0.0608594000, 0.0686708000, 0.0851482000, 0.1183731000, 0.2149844000, 0.5523757000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015611600, 0.0048744300, 0.0152195000, 0.0475201000, 0.1483730000, 0.4632670000"); - values("0.0387599000, 0.0434187000, 0.0567355000, 0.0900080000, 0.1859407000, 0.4964478000, 1.5003112000", \ - "0.0385088000, 0.0433433000, 0.0566164000, 0.0900841000, 0.1859427000, 0.4967030000, 1.4998056000", \ - "0.0387798000, 0.0437308000, 0.0563377000, 0.0898759000, 0.1859681000, 0.4961588000, 1.5031162000", \ - "0.0386463000, 0.0434434000, 0.0561892000, 0.0899137000, 0.1859397000, 0.4963190000, 1.5011257000", \ - "0.0391837000, 0.0439425000, 0.0568775000, 0.0904660000, 0.1861136000, 0.4962752000, 1.4983080000", \ - "0.0429453000, 0.0479285000, 0.0618560000, 0.0951164000, 0.1896254000, 0.4983200000, 1.5018994000", \ - "0.0532411000, 0.0587129000, 0.0730615000, 0.1059858000, 0.1991499000, 0.5016913000, 1.4993149000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4bb_1") { - leakage_power () { - value : 0.0067942000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0064161000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0026822000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0067813000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0068678000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0068462000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0072293000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0068674000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0067287000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0067074000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0070757000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0067283000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0071632000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0071563000; - when : "A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0071825000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0071630000; - when : "A_N&B_N&C&!D"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__and4bb"; - cell_leakage_power : 0.0066493550; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073661000, 0.0072670000, 0.0070385000, 0.0070879000, 0.0072018000, 0.0074643000, 0.0080692000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033283000, 0.0032652000, 0.0031196000, 0.0031576000, 0.0032451000, 0.0034467000, 0.0039114000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015630000; - } - pin ("B_N") { - capacitance : 0.0015210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0065603000, 0.0064774000, 0.0062862000, 0.0063366000, 0.0064529000, 0.0067209000, 0.0073385000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030534000, 0.0029986000, 0.0028722000, 0.0029175000, 0.0030220000, 0.0032629000, 0.0038180000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015690000; - } - pin ("C") { - capacitance : 0.0014820000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024340000, 0.0024316000, 0.0024260000, 0.0024279000, 0.0024323000, 0.0024424000, 0.0024657000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002217600, -0.002217800, -0.002218200, -0.002215500, -0.002209400, -0.002195300, -0.002162900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015150000; - } - pin ("D") { - capacitance : 0.0015130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022134000, 0.0022088000, 0.0021982000, 0.0021984000, 0.0021990000, 0.0022002000, 0.0022031000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002197600, -0.002198000, -0.002199000, -0.002199000, -0.002199100, -0.002199400, -0.002200000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015720000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&!B_N&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0072342000, 0.0061576000, 0.0033297000, -0.004805900, -0.027431200, -0.087238200, -0.243508400", \ - "0.0072074000, 0.0061280000, 0.0033307000, -0.004818300, -0.027437900, -0.087276900, -0.243540700", \ - "0.0071995000, 0.0061368000, 0.0032948000, -0.004854700, -0.027458700, -0.087276800, -0.243560100", \ - "0.0069216000, 0.0058400000, 0.0030578000, -0.005127500, -0.027721500, -0.087569300, -0.243834300", \ - "0.0066491000, 0.0055671000, 0.0027242000, -0.005427900, -0.028018800, -0.087848600, -0.244112700", \ - "0.0075926000, 0.0063838000, 0.0032193000, -0.005301300, -0.028153300, -0.087944900, -0.244205100", \ - "0.0077734000, 0.0065226000, 0.0034080000, -0.005192100, -0.027953300, -0.087804100, -0.244122700"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0112564000, 0.0126730000, 0.0163228000, 0.0253182000, 0.0482217000, 0.1074487000, 0.2635833000", \ - "0.0111841000, 0.0126016000, 0.0162515000, 0.0252469000, 0.0481510000, 0.1073704000, 0.2635329000", \ - "0.0112459000, 0.0126325000, 0.0162890000, 0.0253397000, 0.0482332000, 0.1080187000, 0.2624999000", \ - "0.0110856000, 0.0124772000, 0.0161418000, 0.0251528000, 0.0480284000, 0.1073595000, 0.2633363000", \ - "0.0108459000, 0.0122567000, 0.0159438000, 0.0249840000, 0.0477979000, 0.1071991000, 0.2619858000", \ - "0.0109634000, 0.0124262000, 0.0160783000, 0.0250441000, 0.0479793000, 0.1073016000, 0.2617155000", \ - "0.0113957000, 0.0126556000, 0.0161179000, 0.0250308000, 0.0477920000, 0.1071353000, 0.2628586000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0083883000, 0.0072795000, 0.0044763000, -0.003612900, -0.026115000, -0.085920300, -0.242128700", \ - "0.0083786000, 0.0072733000, 0.0044661000, -0.003597100, -0.026153600, -0.085912500, -0.242156000", \ - "0.0083741000, 0.0072794000, 0.0044608000, -0.003624900, -0.026150300, -0.085953000, -0.242180600", \ - "0.0080829000, 0.0069779000, 0.0041668000, -0.003932900, -0.026460100, -0.086239900, -0.242504600", \ - "0.0077548000, 0.0066591000, 0.0038448000, -0.004244500, -0.026784000, -0.086556700, -0.242790900", \ - "0.0088937000, 0.0076366000, 0.0044129000, -0.004135400, -0.026925300, -0.086691000, -0.242902500", \ - "0.0089899000, 0.0076921000, 0.0043980000, -0.004127400, -0.026899300, -0.086629300, -0.242911700"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0138311000, 0.0152251000, 0.0188852000, 0.0279190000, 0.0507227000, 0.1103706000, 0.2647399000", \ - "0.0137708000, 0.0151875000, 0.0188090000, 0.0278079000, 0.0506371000, 0.1097928000, 0.2659493000", \ - "0.0138374000, 0.0152411000, 0.0188652000, 0.0278583000, 0.0507073000, 0.1098429000, 0.2658873000", \ - "0.0136677000, 0.0150723000, 0.0187100000, 0.0277192000, 0.0505403000, 0.1096492000, 0.2658045000", \ - "0.0134102000, 0.0148167000, 0.0184919000, 0.0275080000, 0.0503021000, 0.1100524000, 0.2643206000", \ - "0.0132300000, 0.0146761000, 0.0183390000, 0.0272615000, 0.0501939000, 0.1093124000, 0.2640902000", \ - "0.0139587000, 0.0152631000, 0.0186748000, 0.0275296000, 0.0503042000, 0.1095676000, 0.2652161000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0084713000, 0.0073501000, 0.0044590000, -0.003692900, -0.026229000, -0.085959900, -0.242141000", \ - "0.0083983000, 0.0072692000, 0.0043870000, -0.003762800, -0.026294400, -0.086030300, -0.242211500", \ - "0.0082831000, 0.0071409000, 0.0042485000, -0.003907300, -0.026391700, -0.086128200, -0.242325900", \ - "0.0081365000, 0.0069910000, 0.0040894000, -0.004079700, -0.026594300, -0.086303300, -0.242479700", \ - "0.0080670000, 0.0069061000, 0.0039741000, -0.004233100, -0.026776300, -0.086459400, -0.242606300", \ - "0.0080454000, 0.0068224000, 0.0038908000, -0.004282800, -0.026820800, -0.086483100, -0.242574000", \ - "0.0098260000, 0.0084352000, 0.0049720000, -0.003857000, -0.026721900, -0.086246300, -0.242278500"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0134948000, 0.0148991000, 0.0185565000, 0.0275160000, 0.0502992000, 0.1094327000, 0.2643298000", \ - "0.0134586000, 0.0148670000, 0.0185307000, 0.0275130000, 0.0502402000, 0.1093493000, 0.2641410000", \ - "0.0133676000, 0.0147766000, 0.0184291000, 0.0274506000, 0.0501786000, 0.1093421000, 0.2641925000", \ - "0.0132604000, 0.0146703000, 0.0183210000, 0.0273612000, 0.0500786000, 0.1092608000, 0.2640541000", \ - "0.0132023000, 0.0146145000, 0.0182120000, 0.0271842000, 0.0499861000, 0.1092415000, 0.2640404000", \ - "0.0137998000, 0.0150814000, 0.0184867000, 0.0270519000, 0.0498820000, 0.1090313000, 0.2648531000", \ - "0.0140799000, 0.0153571000, 0.0187165000, 0.0276779000, 0.0504190000, 0.1098275000, 0.2631594000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0098635000, 0.0086992000, 0.0056981000, -0.002641500, -0.025380600, -0.085296900, -0.241565400", \ - "0.0097648000, 0.0086010000, 0.0056308000, -0.002704500, -0.025485500, -0.085370300, -0.241669900", \ - "0.0096818000, 0.0085116000, 0.0055486000, -0.002790800, -0.025560400, -0.085441900, -0.241688800", \ - "0.0094884000, 0.0083182000, 0.0053631000, -0.002954300, -0.025672600, -0.085565900, -0.241807000", \ - "0.0095100000, 0.0083203000, 0.0053074000, -0.003003500, -0.025765600, -0.085624200, -0.241870700", \ - "0.0095432000, 0.0083321000, 0.0053917000, -0.002910300, -0.025621200, -0.085489600, -0.241730500", \ - "0.0114335000, 0.0102121000, 0.0067243000, -0.002346600, -0.025405300, -0.085158500, -0.241407000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0138633000, 0.0152698000, 0.0189505000, 0.0278476000, 0.0506106000, 0.1095198000, 0.2653937000", \ - "0.0138115000, 0.0152243000, 0.0189067000, 0.0278103000, 0.0505782000, 0.1094473000, 0.2651974000", \ - "0.0137483000, 0.0151657000, 0.0187759000, 0.0277920000, 0.0504754000, 0.1095422000, 0.2642437000", \ - "0.0135811000, 0.0149917000, 0.0186639000, 0.0276279000, 0.0504002000, 0.1098803000, 0.2638815000", \ - "0.0134587000, 0.0148822000, 0.0184870000, 0.0275286000, 0.0502521000, 0.1093477000, 0.2641619000", \ - "0.0140021000, 0.0153340000, 0.0187622000, 0.0273669000, 0.0501413000, 0.1097686000, 0.2639588000", \ - "0.0142700000, 0.0155801000, 0.0189211000, 0.0275703000, 0.0503719000, 0.1097844000, 0.2645994000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.5054310000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1430712000, 0.1497756000, 0.1635866000, 0.1903187000, 0.2445338000, 0.3700349000, 0.6923059000", \ - "0.1478600000, 0.1545561000, 0.1684160000, 0.1951056000, 0.2493354000, 0.3748119000, 0.6968829000", \ - "0.1587241000, 0.1654460000, 0.1792261000, 0.2058525000, 0.2600655000, 0.3857009000, 0.7074397000", \ - "0.1788656000, 0.1855409000, 0.1992871000, 0.2259267000, 0.2802991000, 0.4057963000, 0.7278213000", \ - "0.2062053000, 0.2129245000, 0.2266190000, 0.2533513000, 0.3076239000, 0.4333220000, 0.7541573000", \ - "0.2375006000, 0.2441927000, 0.2579993000, 0.2847181000, 0.3389868000, 0.4645910000, 0.7854765000", \ - "0.2591933000, 0.2658830000, 0.2796781000, 0.3065632000, 0.3610408000, 0.4865899000, 0.8078414000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1983017000, 0.2083259000, 0.2294781000, 0.2737358000, 0.3728035000, 0.6192897000, 1.2584226000", \ - "0.2028507000, 0.2128835000, 0.2340417000, 0.2782991000, 0.3773674000, 0.6238663000, 1.2625422000", \ - "0.2156284000, 0.2255223000, 0.2467433000, 0.2911482000, 0.3900975000, 0.6367488000, 1.2779326000", \ - "0.2474214000, 0.2574163000, 0.2786482000, 0.3229259000, 0.4219396000, 0.6679298000, 1.3112849000", \ - "0.3152559000, 0.3252614000, 0.3465877000, 0.3909454000, 0.4897735000, 0.7363060000, 1.3783413000", \ - "0.4284944000, 0.4385501000, 0.4598037000, 0.5041768000, 0.6030919000, 0.8493155000, 1.4973168000", \ - "0.6125891000, 0.6224839000, 0.6439782000, 0.6884550000, 0.7877315000, 1.0345869000, 1.6741130000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0241539000, 0.0287361000, 0.0387027000, 0.0622905000, 0.1202645000, 0.2785203000, 0.7067512000", \ - "0.0238314000, 0.0283962000, 0.0387743000, 0.0622976000, 0.1202685000, 0.2783423000, 0.7083301000", \ - "0.0240980000, 0.0282952000, 0.0387855000, 0.0625071000, 0.1201533000, 0.2789731000, 0.7070790000", \ - "0.0239231000, 0.0284604000, 0.0390155000, 0.0624430000, 0.1205571000, 0.2782368000, 0.7091355000", \ - "0.0239544000, 0.0284919000, 0.0386836000, 0.0623179000, 0.1203375000, 0.2793127000, 0.7045446000", \ - "0.0239981000, 0.0285750000, 0.0390574000, 0.0623819000, 0.1203661000, 0.2771666000, 0.7111565000", \ - "0.0249079000, 0.0291673000, 0.0398331000, 0.0629509000, 0.1206743000, 0.2785679000, 0.7064024000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0357695000, 0.0442580000, 0.0639402000, 0.1121208000, 0.2390311000, 0.5857468000, 1.5041918000", \ - "0.0357506000, 0.0442575000, 0.0639369000, 0.1121170000, 0.2389983000, 0.5857058000, 1.5048938000", \ - "0.0358402000, 0.0443624000, 0.0638331000, 0.1121281000, 0.2394992000, 0.5858410000, 1.4997774000", \ - "0.0356655000, 0.0442958000, 0.0639010000, 0.1120072000, 0.2393694000, 0.5858967000, 1.5033027000", \ - "0.0359917000, 0.0441525000, 0.0639236000, 0.1120299000, 0.2389474000, 0.5864983000, 1.4992476000", \ - "0.0360571000, 0.0444460000, 0.0641145000, 0.1121529000, 0.2397705000, 0.5858917000, 1.5039958000", \ - "0.0369772000, 0.0456894000, 0.0651281000, 0.1132069000, 0.2402096000, 0.5856081000, 1.4991447000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1701660000, 0.1772166000, 0.1916589000, 0.2192185000, 0.2744428000, 0.4006638000, 0.7229325000", \ - "0.1750331000, 0.1819608000, 0.1963638000, 0.2240768000, 0.2793247000, 0.4054721000, 0.7274870000", \ - "0.1858492000, 0.1929344000, 0.2073379000, 0.2348158000, 0.2901820000, 0.4161421000, 0.7380548000", \ - "0.2059753000, 0.2130093000, 0.2273907000, 0.2550974000, 0.3102845000, 0.4362176000, 0.7577111000", \ - "0.2338579000, 0.2408913000, 0.2551675000, 0.2828424000, 0.3381565000, 0.4643393000, 0.7855233000", \ - "0.2677782000, 0.2747853000, 0.2892143000, 0.3169471000, 0.3722976000, 0.4985229000, 0.8200020000", \ - "0.2947701000, 0.3018811000, 0.3161961000, 0.3440209000, 0.3995071000, 0.5257890000, 0.8478844000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.2148088000, 0.2247902000, 0.2462200000, 0.2904831000, 0.3893031000, 0.6355125000, 1.2754714000", \ - "0.2196058000, 0.2296846000, 0.2508619000, 0.2951647000, 0.3939482000, 0.6399398000, 1.2804294000", \ - "0.2326048000, 0.2426426000, 0.2638341000, 0.3080993000, 0.4069310000, 0.6530337000, 1.2919711000", \ - "0.2640546000, 0.2740512000, 0.2952494000, 0.3395131000, 0.4383729000, 0.6845476000, 1.3227197000", \ - "0.3309215000, 0.3409850000, 0.3623341000, 0.4067089000, 0.5054733000, 0.7518748000, 1.3897236000", \ - "0.4430071000, 0.4531917000, 0.4745254000, 0.5190662000, 0.6180997000, 0.8646952000, 1.5033180000", \ - "0.6248598000, 0.6351774000, 0.6570577000, 0.7018805000, 0.8012206000, 1.0477843000, 1.6876668000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0260380000, 0.0306180000, 0.0411549000, 0.0648115000, 0.1221911000, 0.2790907000, 0.7075858000", \ - "0.0262444000, 0.0309019000, 0.0414395000, 0.0648270000, 0.1221826000, 0.2793452000, 0.7049183000", \ - "0.0263271000, 0.0309247000, 0.0409993000, 0.0646160000, 0.1224227000, 0.2797606000, 0.7106640000", \ - "0.0261935000, 0.0307836000, 0.0408795000, 0.0644697000, 0.1224228000, 0.2797167000, 0.7112163000", \ - "0.0261716000, 0.0308338000, 0.0411028000, 0.0645271000, 0.1222902000, 0.2804287000, 0.7051260000", \ - "0.0264989000, 0.0309271000, 0.0414209000, 0.0648518000, 0.1222122000, 0.2779140000, 0.7059075000", \ - "0.0268962000, 0.0313827000, 0.0416941000, 0.0650048000, 0.1225357000, 0.2791493000, 0.7046216000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0362010000, 0.0446732000, 0.0641930000, 0.1118888000, 0.2391686000, 0.5848607000, 1.5005168000", \ - "0.0361317000, 0.0444237000, 0.0641858000, 0.1121356000, 0.2394500000, 0.5858784000, 1.5010870000", \ - "0.0360285000, 0.0443881000, 0.0642011000, 0.1121626000, 0.2392562000, 0.5857091000, 1.5040582000", \ - "0.0360938000, 0.0445336000, 0.0641243000, 0.1120938000, 0.2390538000, 0.5852498000, 1.5054313000", \ - "0.0363142000, 0.0444801000, 0.0641686000, 0.1122361000, 0.2396267000, 0.5855777000, 1.5010064000", \ - "0.0365326000, 0.0450343000, 0.0645713000, 0.1121923000, 0.2397331000, 0.5855580000, 1.4959523000", \ - "0.0379338000, 0.0464248000, 0.0658560000, 0.1136785000, 0.2404390000, 0.5860851000, 1.4986015000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1489472000, 0.1562325000, 0.1710257000, 0.1991665000, 0.2550790000, 0.3819032000, 0.7040852000", \ - "0.1543258000, 0.1616153000, 0.1764035000, 0.2044925000, 0.2605294000, 0.3873021000, 0.7097148000", \ - "0.1676893000, 0.1749368000, 0.1897087000, 0.2178799000, 0.2739584000, 0.4007324000, 0.7225212000", \ - "0.1995204000, 0.2067606000, 0.2215031000, 0.2497592000, 0.3056862000, 0.4323271000, 0.7547322000", \ - "0.2756746000, 0.2828221000, 0.2974714000, 0.3255450000, 0.3816606000, 0.5086152000, 0.8306225000", \ - "0.4306530000, 0.4391993000, 0.4559629000, 0.4867398000, 0.5447273000, 0.6721976000, 0.9946853000", \ - "0.6834165000, 0.6946047000, 0.7166778000, 0.7554780000, 0.8216729000, 0.9540032000, 1.2764183000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1437130000, 0.1537512000, 0.1749381000, 0.2191939000, 0.3174630000, 0.5630553000, 1.2002798000", \ - "0.1479296000, 0.1579331000, 0.1791679000, 0.2234248000, 0.3219831000, 0.5677053000, 1.2054011000", \ - "0.1558787000, 0.1658879000, 0.1871237000, 0.2314473000, 0.3300209000, 0.5756025000, 1.2131225000", \ - "0.1717348000, 0.1817145000, 0.2029054000, 0.2471812000, 0.3456465000, 0.5917025000, 1.2294289000", \ - "0.2035702000, 0.2139699000, 0.2356699000, 0.2804220000, 0.3794058000, 0.6250331000, 1.2657824000", \ - "0.2527510000, 0.2642117000, 0.2878285000, 0.3346814000, 0.4356207000, 0.6825760000, 1.3272177000", \ - "0.2984838000, 0.3130230000, 0.3416019000, 0.3941684000, 0.4982182000, 0.7459469000, 1.3843607000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0278699000, 0.0324661000, 0.0427314000, 0.0661930000, 0.1234415000, 0.2814211000, 0.7078031000", \ - "0.0276529000, 0.0326499000, 0.0427912000, 0.0660563000, 0.1236032000, 0.2814737000, 0.7075605000", \ - "0.0275841000, 0.0321539000, 0.0429482000, 0.0660818000, 0.1236362000, 0.2808973000, 0.7071046000", \ - "0.0275938000, 0.0322135000, 0.0423771000, 0.0660207000, 0.1236859000, 0.2807217000, 0.7103744000", \ - "0.0277198000, 0.0323644000, 0.0426945000, 0.0660112000, 0.1238704000, 0.2812873000, 0.7067933000", \ - "0.0360027000, 0.0408787000, 0.0509122000, 0.0733701000, 0.1277722000, 0.2818936000, 0.7078562000", \ - "0.0533003000, 0.0592718000, 0.0713040000, 0.0935427000, 0.1453671000, 0.2900496000, 0.7061374000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0358800000, 0.0442912000, 0.0637897000, 0.1121749000, 0.2395986000, 0.5849958000, 1.5024287000", \ - "0.0358624000, 0.0442160000, 0.0638133000, 0.1121458000, 0.2394029000, 0.5865875000, 1.5016508000", \ - "0.0357794000, 0.0443155000, 0.0638743000, 0.1121380000, 0.2395817000, 0.5862059000, 1.5022366000", \ - "0.0359539000, 0.0444532000, 0.0639607000, 0.1119884000, 0.2389676000, 0.5864911000, 1.5025895000", \ - "0.0375776000, 0.0460863000, 0.0656000000, 0.1132539000, 0.2399553000, 0.5857665000, 1.5032433000", \ - "0.0432958000, 0.0520690000, 0.0716901000, 0.1185991000, 0.2426673000, 0.5855118000, 1.5022090000", \ - "0.0578543000, 0.0674114000, 0.0870414000, 0.1318161000, 0.2493715000, 0.5888301000, 1.4956086000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1617611000, 0.1691392000, 0.1839911000, 0.2123414000, 0.2683127000, 0.3953252000, 0.7179159000", \ - "0.1668225000, 0.1741878000, 0.1891219000, 0.2174344000, 0.2733570000, 0.4003991000, 0.7230164000", \ - "0.1797174000, 0.1870875000, 0.2020488000, 0.2303441000, 0.2862519000, 0.4132214000, 0.7353762000", \ - "0.2121389000, 0.2195028000, 0.2342360000, 0.2626092000, 0.3188646000, 0.4459079000, 0.7686825000", \ - "0.2884296000, 0.2957274000, 0.3105766000, 0.3389432000, 0.3952515000, 0.5223577000, 0.8446290000", \ - "0.4491409000, 0.4575366000, 0.4741921000, 0.5045769000, 0.5622041000, 0.6897514000, 1.0117287000", \ - "0.7141328000, 0.7248462000, 0.7465768000, 0.7847296000, 0.8500970000, 0.9819872000, 1.3042468000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1515942000, 0.1615701000, 0.1828235000, 0.2269654000, 0.3251883000, 0.5701822000, 1.2104456000", \ - "0.1557474000, 0.1658048000, 0.1870243000, 0.2311620000, 0.3294156000, 0.5748196000, 1.2125726000", \ - "0.1635773000, 0.1736352000, 0.1948010000, 0.2391328000, 0.3375751000, 0.5826055000, 1.2198365000", \ - "0.1779203000, 0.1880388000, 0.2092194000, 0.2533918000, 0.3518817000, 0.5976392000, 1.2343124000", \ - "0.2039550000, 0.2144015000, 0.2360094000, 0.2807448000, 0.3795611000, 0.6245726000, 1.2665492000", \ - "0.2440764000, 0.2552230000, 0.2785462000, 0.3252867000, 0.4260269000, 0.6723794000, 1.3138474000", \ - "0.2843860000, 0.2981443000, 0.3258644000, 0.3770402000, 0.4814895000, 0.7294462000, 1.3674128000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0291730000, 0.0339380000, 0.0448548000, 0.0681503000, 0.1258523000, 0.2821006000, 0.7072997000", \ - "0.0291279000, 0.0338172000, 0.0446656000, 0.0682593000, 0.1258249000, 0.2822095000, 0.7082965000", \ - "0.0290657000, 0.0338486000, 0.0448072000, 0.0678608000, 0.1256886000, 0.2821839000, 0.7082006000", \ - "0.0290527000, 0.0337760000, 0.0444667000, 0.0684162000, 0.1257006000, 0.2821186000, 0.7094306000", \ - "0.0291360000, 0.0338984000, 0.0447612000, 0.0678108000, 0.1254146000, 0.2817929000, 0.7120090000", \ - "0.0361702000, 0.0411682000, 0.0510850000, 0.0731107000, 0.1283742000, 0.2823624000, 0.7098142000", \ - "0.0532180000, 0.0592177000, 0.0708088000, 0.0931043000, 0.1444948000, 0.2906700000, 0.7070001000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0359255000, 0.0443657000, 0.0639435000, 0.1120216000, 0.2395812000, 0.5853192000, 1.4996808000", \ - "0.0359758000, 0.0444175000, 0.0638980000, 0.1121755000, 0.2396454000, 0.5840228000, 1.5014398000", \ - "0.0357742000, 0.0442926000, 0.0638842000, 0.1121709000, 0.2395359000, 0.5859040000, 1.5023207000", \ - "0.0358797000, 0.0444289000, 0.0639032000, 0.1118156000, 0.2395417000, 0.5850831000, 1.4983899000", \ - "0.0372943000, 0.0457541000, 0.0654178000, 0.1130702000, 0.2399793000, 0.5854552000, 1.5022754000", \ - "0.0414292000, 0.0507226000, 0.0702538000, 0.1177589000, 0.2424828000, 0.5862311000, 1.4995594000", \ - "0.0532621000, 0.0630952000, 0.0830109000, 0.1299815000, 0.2489081000, 0.5883971000, 1.4959395000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4bb_2") { - leakage_power () { - value : 0.0039208000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0035549000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0024095000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0039125000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0038587000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0038379000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0042041000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0038586000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0038795000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0038590000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0042110000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0038793000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0041671000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0041606000; - when : "A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0041854000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0041670000; - when : "A_N&B_N&C&!D"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__and4bb"; - cell_leakage_power : 0.0038791200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0070961000, 0.0069941000, 0.0067591000, 0.0068064000, 0.0069155000, 0.0071670000, 0.0077467000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031427000, 0.0030744000, 0.0029172000, 0.0029553000, 0.0030432000, 0.0032457000, 0.0037127000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015590000; - } - pin ("B_N") { - capacitance : 0.0014970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061757000, 0.0060815000, 0.0058645000, 0.0059150000, 0.0060313000, 0.0062996000, 0.0069179000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026656000, 0.0026004000, 0.0024501000, 0.0024933000, 0.0025929000, 0.0028226000, 0.0033520000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015540000; - } - pin ("C") { - capacitance : 0.0014950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023955000, 0.0023959000, 0.0023967000, 0.0023980000, 0.0024010000, 0.0024079000, 0.0024238000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002209200, -0.002206900, -0.002201600, -0.002199800, -0.002195500, -0.002185800, -0.002163200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015280000; - } - pin ("D") { - capacitance : 0.0015200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019615000, 0.0019614000, 0.0019612000, 0.0019614000, 0.0019616000, 0.0019622000, 0.0019636000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001968400, -0.001965100, -0.001957300, -0.001956900, -0.001955900, -0.001953800, -0.001948800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015660000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&!B_N&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0107085000, 0.0093291000, 0.0055300000, -0.005280800, -0.038984200, -0.138228600, -0.422445300", \ - "0.0106870000, 0.0092517000, 0.0055009000, -0.005296200, -0.038990200, -0.138239500, -0.422431000", \ - "0.0107862000, 0.0092169000, 0.0054742000, -0.005308400, -0.038990200, -0.138236500, -0.422427800", \ - "0.0104136000, 0.0089672000, 0.0051888000, -0.005625100, -0.039335600, -0.138487800, -0.422674600", \ - "0.0101629000, 0.0086693000, 0.0048788000, -0.005952300, -0.039588600, -0.138835000, -0.422972200", \ - "0.0122901000, 0.0108115000, 0.0066162000, -0.005323900, -0.039817700, -0.139051100, -0.423214200", \ - "0.0126379000, 0.0111390000, 0.0069131000, -0.005013300, -0.039465500, -0.138888700, -0.423210500"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0161701000, 0.0176688000, 0.0222714000, 0.0351688000, 0.0702865000, 0.1690011000, 0.4503910000", \ - "0.0160740000, 0.0176595000, 0.0221547000, 0.0349823000, 0.0701401000, 0.1688657000, 0.4499513000", \ - "0.0161593000, 0.0176884000, 0.0222768000, 0.0351652000, 0.0702119000, 0.1690508000, 0.4489263000", \ - "0.0160276000, 0.0175699000, 0.0220509000, 0.0348781000, 0.0700761000, 0.1688872000, 0.4499506000", \ - "0.0157971000, 0.0173760000, 0.0218792000, 0.0347041000, 0.0698661000, 0.1686845000, 0.4498375000", \ - "0.0156407000, 0.0171958000, 0.0217403000, 0.0344359000, 0.0696012000, 0.1684362000, 0.4499343000", \ - "0.0166557000, 0.0181961000, 0.0225833000, 0.0348590000, 0.0694387000, 0.1683613000, 0.4489024000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0110031000, 0.0095230000, 0.0057412000, -0.005061700, -0.038584900, -0.137530500, -0.421607200", \ - "0.0109649000, 0.0095317000, 0.0057427000, -0.005065600, -0.038555000, -0.137536400, -0.421657600", \ - "0.0109658000, 0.0095074000, 0.0057409000, -0.005016200, -0.038522300, -0.137523600, -0.421602100", \ - "0.0107272000, 0.0092943000, 0.0055448000, -0.005256900, -0.038761100, -0.137757200, -0.421858400", \ - "0.0104873000, 0.0090164000, 0.0052872000, -0.005511500, -0.038995600, -0.138038300, -0.422064300", \ - "0.0125439000, 0.0110686000, 0.0069086000, -0.004970400, -0.039237000, -0.138172800, -0.422213000", \ - "0.0130290000, 0.0115365000, 0.0073933000, -0.004440200, -0.038818800, -0.137997800, -0.422115100"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0178402000, 0.0193879000, 0.0238656000, 0.0367669000, 0.0718474000, 0.1706462000, 0.4523211000", \ - "0.0177850000, 0.0193272000, 0.0238014000, 0.0366978000, 0.0717983000, 0.1705996000, 0.4517273000", \ - "0.0178308000, 0.0193736000, 0.0238463000, 0.0367431000, 0.0718491000, 0.1706491000, 0.4517839000", \ - "0.0176411000, 0.0191384000, 0.0237420000, 0.0366203000, 0.0716183000, 0.1704743000, 0.4522902000", \ - "0.0174467000, 0.0189486000, 0.0235490000, 0.0364271000, 0.0714818000, 0.1702751000, 0.4520134000", \ - "0.0173366000, 0.0189114000, 0.0233887000, 0.0362087000, 0.0713406000, 0.1701263000, 0.4517655000", \ - "0.0184232000, 0.0199576000, 0.0242556000, 0.0366596000, 0.0713423000, 0.1703512000, 0.4511864000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0114127000, 0.0099679000, 0.0061329000, -0.004732700, -0.038281300, -0.137156100, -0.421179500", \ - "0.0113435000, 0.0098702000, 0.0060410000, -0.004803700, -0.038315600, -0.137227900, -0.421244000", \ - "0.0112577000, 0.0097864000, 0.0059802000, -0.004898100, -0.038383200, -0.137326500, -0.421326800", \ - "0.0112008000, 0.0097416000, 0.0059228000, -0.005047600, -0.038574900, -0.137455200, -0.421458300", \ - "0.0110111000, 0.0095266000, 0.0056928000, -0.005200900, -0.038751800, -0.137672300, -0.421611700", \ - "0.0112757000, 0.0097387000, 0.0062511000, -0.005012500, -0.038783600, -0.137720800, -0.421611900", \ - "0.0145370000, 0.0128204000, 0.0082397000, -0.004141900, -0.038952100, -0.137423700, -0.421302400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0177162000, 0.0193023000, 0.0238572000, 0.0367449000, 0.0716607000, 0.1705144000, 0.4521823000", \ - "0.0176807000, 0.0192493000, 0.0238243000, 0.0365402000, 0.0717786000, 0.1705323000, 0.4516192000", \ - "0.0176516000, 0.0192392000, 0.0238016000, 0.0365886000, 0.0715899000, 0.1705624000, 0.4520103000", \ - "0.0175324000, 0.0191040000, 0.0236430000, 0.0365430000, 0.0715984000, 0.1703706000, 0.4521876000", \ - "0.0175204000, 0.0190464000, 0.0235173000, 0.0363899000, 0.0715050000, 0.1702503000, 0.4516905000", \ - "0.0182185000, 0.0196653000, 0.0238314000, 0.0363093000, 0.0712510000, 0.1700108000, 0.4515213000", \ - "0.0191217000, 0.0205491000, 0.0247426000, 0.0369848000, 0.0716456000, 0.1703961000, 0.4502569000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0128823000, 0.0114570000, 0.0075410000, -0.003245100, -0.036684700, -0.135464400, -0.419404800", \ - "0.0127687000, 0.0113496000, 0.0075292000, -0.003253900, -0.036699900, -0.135556800, -0.419483800", \ - "0.0127572000, 0.0113132000, 0.0074830000, -0.003361200, -0.036790100, -0.135592700, -0.419516000", \ - "0.0126526000, 0.0111765000, 0.0073458000, -0.003463200, -0.036876800, -0.135716100, -0.419647300", \ - "0.0125341000, 0.0110586000, 0.0072446000, -0.003604000, -0.037042800, -0.135855000, -0.419723400", \ - "0.0127803000, 0.0112998000, 0.0073253000, -0.003412700, -0.037054400, -0.135920100, -0.419740600", \ - "0.0164841000, 0.0147577000, 0.0101900000, -0.002357300, -0.037084700, -0.135775500, -0.419491600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014268990, 0.0040720810, 0.0116209000, 0.0331636900, 0.0946424700, 0.2700905000"); - values("0.0176547000, 0.0192922000, 0.0238279000, 0.0367229000, 0.0715849000, 0.1705867000, 0.4519486000", \ - "0.0176808000, 0.0192697000, 0.0237166000, 0.0366344000, 0.0716964000, 0.1705946000, 0.4521895000", \ - "0.0176135000, 0.0191465000, 0.0237046000, 0.0366005000, 0.0716666000, 0.1705514000, 0.4519895000", \ - "0.0175322000, 0.0190499000, 0.0236059000, 0.0365359000, 0.0716187000, 0.1704770000, 0.4504203000", \ - "0.0174924000, 0.0190063000, 0.0235059000, 0.0363943000, 0.0714443000, 0.1703566000, 0.4503499000", \ - "0.0181736000, 0.0196621000, 0.0238789000, 0.0362623000, 0.0712674000, 0.1701361000, 0.4517060000", \ - "0.0189390000, 0.0203769000, 0.0246315000, 0.0372145000, 0.0718140000, 0.1703012000, 0.4499385000"); - } - } - max_capacitance : 0.2700900000; - max_transition : 1.5033030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1862667000, 0.1926589000, 0.2066461000, 0.2338705000, 0.2858106000, 0.3989092000, 0.6938405000", \ - "0.1911694000, 0.1975346000, 0.2115102000, 0.2388217000, 0.2906627000, 0.4037532000, 0.6988742000", \ - "0.2021261000, 0.2084765000, 0.2224576000, 0.2493614000, 0.3014233000, 0.4145366000, 0.7093190000", \ - "0.2220207000, 0.2283871000, 0.2423383000, 0.2695018000, 0.3216158000, 0.4347309000, 0.7294392000", \ - "0.2495272000, 0.2558291000, 0.2697667000, 0.2969406000, 0.3488977000, 0.4620451000, 0.7568431000", \ - "0.2812844000, 0.2876397000, 0.3015539000, 0.3287267000, 0.3808268000, 0.4940389000, 0.7894819000", \ - "0.3049214000, 0.3112047000, 0.3251235000, 0.3523835000, 0.4045656000, 0.5180705000, 0.8130019000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.2366742000, 0.2456543000, 0.2663620000, 0.3088855000, 0.4016880000, 0.6360954000, 1.2924170000", \ - "0.2411537000, 0.2504657000, 0.2707066000, 0.3132919000, 0.4059809000, 0.6404240000, 1.3033548000", \ - "0.2541019000, 0.2632825000, 0.2838635000, 0.3263818000, 0.4191779000, 0.6534235000, 1.3096378000", \ - "0.2858316000, 0.2950707000, 0.3154463000, 0.3579197000, 0.4507336000, 0.6852971000, 1.3465676000", \ - "0.3519882000, 0.3612927000, 0.3816184000, 0.4241174000, 0.5168612000, 0.7514402000, 1.4117448000", \ - "0.4665896000, 0.4759116000, 0.4963411000, 0.5387659000, 0.6314900000, 0.8655072000, 1.5266398000", \ - "0.6518687000, 0.6610983000, 0.6817517000, 0.7244901000, 0.8175811000, 1.0518554000, 1.7096948000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0284149000, 0.0321259000, 0.0411616000, 0.0609977000, 0.1070321000, 0.2349179000, 0.6233860000", \ - "0.0282356000, 0.0323063000, 0.0414183000, 0.0608791000, 0.1070685000, 0.2351835000, 0.6224702000", \ - "0.0284142000, 0.0321689000, 0.0410418000, 0.0610023000, 0.1074510000, 0.2351311000, 0.6228450000", \ - "0.0282575000, 0.0322601000, 0.0413558000, 0.0604808000, 0.1070503000, 0.2345007000, 0.6228534000", \ - "0.0285400000, 0.0323829000, 0.0417348000, 0.0605253000, 0.1074183000, 0.2351462000, 0.6201696000", \ - "0.0285685000, 0.0326240000, 0.0415164000, 0.0606084000, 0.1073082000, 0.2344996000, 0.6230876000", \ - "0.0288496000, 0.0327699000, 0.0419439000, 0.0610228000, 0.1075286000, 0.2355594000, 0.6230195000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0364820000, 0.0433367000, 0.0599941000, 0.1001056000, 0.2098483000, 0.5379461000, 1.5008983000", \ - "0.0363125000, 0.0435266000, 0.0602753000, 0.0999708000, 0.2099149000, 0.5378495000, 1.4996214000", \ - "0.0364341000, 0.0433405000, 0.0600401000, 0.1001780000, 0.2103502000, 0.5379912000, 1.4955785000", \ - "0.0364794000, 0.0434451000, 0.0601571000, 0.1000665000, 0.2101409000, 0.5378416000, 1.5009038000", \ - "0.0363229000, 0.0434529000, 0.0602091000, 0.1000032000, 0.2101837000, 0.5378041000, 1.5011941000", \ - "0.0365446000, 0.0436926000, 0.0603188000, 0.0999126000, 0.2101650000, 0.5366645000, 1.5030960000", \ - "0.0375346000, 0.0445363000, 0.0608965000, 0.1011828000, 0.2110044000, 0.5380967000, 1.4965799000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1991974000, 0.2058266000, 0.2201847000, 0.2479513000, 0.3005535000, 0.4140220000, 0.7094944000", \ - "0.2040738000, 0.2106995000, 0.2250734000, 0.2528192000, 0.3051961000, 0.4191170000, 0.7139437000", \ - "0.2150663000, 0.2216637000, 0.2361364000, 0.2639723000, 0.3164791000, 0.4301508000, 0.7253740000", \ - "0.2347107000, 0.2414313000, 0.2557702000, 0.2835589000, 0.3359882000, 0.4498358000, 0.7447127000", \ - "0.2612827000, 0.2679001000, 0.2822223000, 0.3099883000, 0.3626115000, 0.4762823000, 0.7712445000", \ - "0.2896476000, 0.2962339000, 0.3106542000, 0.3384610000, 0.3912704000, 0.5048051000, 0.8003931000", \ - "0.3088063000, 0.3154410000, 0.3298738000, 0.3576677000, 0.4103523000, 0.5243423000, 0.8196571000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.2426924000, 0.2519165000, 0.2723949000, 0.3148817000, 0.4075845000, 0.6421374000, 1.3000681000", \ - "0.2475183000, 0.2567449000, 0.2771959000, 0.3196794000, 0.4123707000, 0.6470220000, 1.3104055000", \ - "0.2602820000, 0.2695101000, 0.2899523000, 0.3324387000, 0.4251304000, 0.6598093000, 1.3226841000", \ - "0.2918751000, 0.3008580000, 0.3216030000, 0.3641288000, 0.4569090000, 0.6907758000, 1.3513167000", \ - "0.3581242000, 0.3672601000, 0.3878402000, 0.4303639000, 0.5230404000, 0.7575590000, 1.4151634000", \ - "0.4679579000, 0.4773125000, 0.4977164000, 0.5402834000, 0.6331487000, 0.8673158000, 1.5285319000", \ - "0.6474057000, 0.6567619000, 0.6774027000, 0.7201814000, 0.8130829000, 1.0475841000, 1.7033971000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0304892000, 0.0340877000, 0.0430007000, 0.0625335000, 0.1082037000, 0.2353380000, 0.6231133000", \ - "0.0301551000, 0.0341322000, 0.0429885000, 0.0621470000, 0.1084237000, 0.2347374000, 0.6232863000", \ - "0.0307147000, 0.0347080000, 0.0429280000, 0.0623950000, 0.1080112000, 0.2352654000, 0.6233959000", \ - "0.0305020000, 0.0341271000, 0.0429356000, 0.0620349000, 0.1081122000, 0.2347395000, 0.6233359000", \ - "0.0306031000, 0.0342311000, 0.0435123000, 0.0623485000, 0.1080193000, 0.2354038000, 0.6228031000", \ - "0.0303966000, 0.0346186000, 0.0434806000, 0.0627526000, 0.1081215000, 0.2342453000, 0.6229033000", \ - "0.0306946000, 0.0347770000, 0.0432449000, 0.0623584000, 0.1082954000, 0.2355411000, 0.6236850000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0365345000, 0.0435029000, 0.0602171000, 0.1001851000, 0.2098329000, 0.5378887000, 1.4982315000", \ - "0.0366238000, 0.0434932000, 0.0602163000, 0.1001508000, 0.2098936000, 0.5380283000, 1.4991067000", \ - "0.0366241000, 0.0434889000, 0.0602163000, 0.1000846000, 0.2099015000, 0.5380646000, 1.4996746000", \ - "0.0366040000, 0.0434056000, 0.0601720000, 0.1002137000, 0.2101090000, 0.5365300000, 1.5018530000", \ - "0.0365462000, 0.0437411000, 0.0601728000, 0.1002165000, 0.2097870000, 0.5377574000, 1.4958240000", \ - "0.0366302000, 0.0437340000, 0.0604585000, 0.0999471000, 0.2099764000, 0.5368526000, 1.5033035000", \ - "0.0373554000, 0.0442615000, 0.0610824000, 0.1008043000, 0.2102180000, 0.5383576000, 1.4991703000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1825911000, 0.1893441000, 0.2039134000, 0.2320258000, 0.2851163000, 0.3991446000, 0.6950376000", \ - "0.1879897000, 0.1947140000, 0.2092820000, 0.2371548000, 0.2904378000, 0.4044809000, 0.7004028000", \ - "0.2016716000, 0.2083924000, 0.2230070000, 0.2505967000, 0.3038760000, 0.4179308000, 0.7138450000", \ - "0.2336359000, 0.2404134000, 0.2550002000, 0.2829709000, 0.3360534000, 0.4501444000, 0.7459101000", \ - "0.3099555000, 0.3166351000, 0.3312566000, 0.3594121000, 0.4125625000, 0.5265411000, 0.8222235000", \ - "0.4783916000, 0.4858278000, 0.5016089000, 0.5314633000, 0.5857883000, 0.7007513000, 0.9965780000", \ - "0.7640730000, 0.7738548000, 0.7945919000, 0.8333240000, 0.8986872000, 1.0199146000, 1.3169940000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1776697000, 0.1869927000, 0.2074024000, 0.2499010000, 0.3426280000, 0.5766791000, 1.2353112000", \ - "0.1820376000, 0.1912126000, 0.2116942000, 0.2540908000, 0.3468227000, 0.5813910000, 1.2434346000", \ - "0.1901500000, 0.1994606000, 0.2199248000, 0.2623533000, 0.3552067000, 0.5893863000, 1.2499498000", \ - "0.2059557000, 0.2152008000, 0.2358647000, 0.2783419000, 0.3710400000, 0.6053857000, 1.2639073000", \ - "0.2409917000, 0.2502473000, 0.2708309000, 0.3136002000, 0.4063893000, 0.6411130000, 1.2999899000", \ - "0.3007150000, 0.3108354000, 0.3331330000, 0.3780465000, 0.4731487000, 0.7085575000, 1.3655352000", \ - "0.3732795000, 0.3856278000, 0.4122272000, 0.4627919000, 0.5619455000, 0.7984395000, 1.4560940000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0314091000, 0.0351999000, 0.0438383000, 0.0632052000, 0.1088883000, 0.2359979000, 0.6237461000", \ - "0.0311984000, 0.0353204000, 0.0444989000, 0.0637658000, 0.1090368000, 0.2362563000, 0.6232623000", \ - "0.0314880000, 0.0354623000, 0.0443327000, 0.0637486000, 0.1090280000, 0.2362704000, 0.6230754000", \ - "0.0310928000, 0.0352109000, 0.0446075000, 0.0635590000, 0.1091118000, 0.2358801000, 0.6226276000", \ - "0.0312290000, 0.0353493000, 0.0442916000, 0.0631713000, 0.1088997000, 0.2362107000, 0.6234832000", \ - "0.0380407000, 0.0415276000, 0.0509058000, 0.0682041000, 0.1124802000, 0.2365088000, 0.6232647000", \ - "0.0569421000, 0.0625902000, 0.0731514000, 0.0927800000, 0.1348590000, 0.2520692000, 0.6258180000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0364145000, 0.0434635000, 0.0601563000, 0.1000285000, 0.2099049000, 0.5364161000, 1.4966217000", \ - "0.0364253000, 0.0436425000, 0.0602308000, 0.1001328000, 0.2100576000, 0.5379883000, 1.5001796000", \ - "0.0363716000, 0.0434561000, 0.0599014000, 0.1002598000, 0.2102912000, 0.5372726000, 1.5028310000", \ - "0.0368302000, 0.0434480000, 0.0600687000, 0.1000476000, 0.2097825000, 0.5374858000, 1.4978924000", \ - "0.0373696000, 0.0442948000, 0.0608239000, 0.1006675000, 0.2102676000, 0.5367123000, 1.5014616000", \ - "0.0419784000, 0.0491973000, 0.0663092000, 0.1060941000, 0.2145093000, 0.5391247000, 1.4988731000", \ - "0.0548478000, 0.0627824000, 0.0807038000, 0.1197827000, 0.2229403000, 0.5421677000, 1.4950448000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1917877000, 0.1986200000, 0.2133231000, 0.2417270000, 0.2950864000, 0.4095560000, 0.7058911000", \ - "0.1970600000, 0.2038600000, 0.2186246000, 0.2470423000, 0.3003482000, 0.4148493000, 0.7109116000", \ - "0.2100836000, 0.2168759000, 0.2316478000, 0.2602426000, 0.3139219000, 0.4283507000, 0.7247191000", \ - "0.2416302000, 0.2484396000, 0.2631848000, 0.2930161000, 0.3465468000, 0.4610856000, 0.7572317000", \ - "0.3196117000, 0.3264393000, 0.3412021000, 0.3697428000, 0.4231301000, 0.5378178000, 0.8342010000", \ - "0.4907522000, 0.4983054000, 0.5139180000, 0.5431226000, 0.5971959000, 0.7123844000, 1.0085455000", \ - "0.7837958000, 0.7935748000, 0.8141668000, 0.8523463000, 0.9181593000, 1.0406986000, 1.3378887000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.1814270000, 0.1907217000, 0.2111504000, 0.2536740000, 0.3464609000, 0.5807352000, 1.2407275000", \ - "0.1858805000, 0.1951201000, 0.2155327000, 0.2581068000, 0.3509551000, 0.5852592000, 1.2437086000", \ - "0.1940653000, 0.2032415000, 0.2237382000, 0.2662999000, 0.3591457000, 0.5934943000, 1.2503357000", \ - "0.2088351000, 0.2180208000, 0.2385971000, 0.2811226000, 0.3739082000, 0.6081244000, 1.2645243000", \ - "0.2375283000, 0.2467851000, 0.2672159000, 0.3099996000, 0.4028434000, 0.6371352000, 1.2934636000", \ - "0.2852964000, 0.2953913000, 0.3173458000, 0.3620715000, 0.4569582000, 0.6915403000, 1.3505619000", \ - "0.3459282000, 0.3575156000, 0.3828744000, 0.4323812000, 0.5318628000, 0.7682611000, 1.4248361000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0318759000, 0.0359702000, 0.0445277000, 0.0637858000, 0.1097994000, 0.2365068000, 0.6241735000", \ - "0.0320076000, 0.0358500000, 0.0448903000, 0.0637917000, 0.1096250000, 0.2373057000, 0.6243391000", \ - "0.0319524000, 0.0359120000, 0.0451676000, 0.0646368000, 0.1097362000, 0.2368826000, 0.6237872000", \ - "0.0319842000, 0.0361286000, 0.0445937000, 0.0646380000, 0.1097445000, 0.2370075000, 0.6244928000", \ - "0.0319912000, 0.0361233000, 0.0451563000, 0.0638770000, 0.1096323000, 0.2368122000, 0.6245486000", \ - "0.0373368000, 0.0417390000, 0.0501237000, 0.0678476000, 0.1117793000, 0.2375271000, 0.6240113000", \ - "0.0562590000, 0.0609312000, 0.0719480000, 0.0911806000, 0.1339855000, 0.2505386000, 0.6253200000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014269000, 0.0040720800, 0.0116209000, 0.0331637000, 0.0946425000, 0.2700900000"); - values("0.0364251000, 0.0434491000, 0.0600645000, 0.1001464000, 0.2103203000, 0.5375269000, 1.5024145000", \ - "0.0365457000, 0.0432211000, 0.0597094000, 0.1001546000, 0.2103818000, 0.5379322000, 1.4986061000", \ - "0.0364238000, 0.0436463000, 0.0600078000, 0.1000978000, 0.2103929000, 0.5380629000, 1.4990459000", \ - "0.0365412000, 0.0433677000, 0.0600219000, 0.1001875000, 0.2098400000, 0.5376262000, 1.4953201000", \ - "0.0371389000, 0.0442173000, 0.0604623000, 0.1008216000, 0.2105205000, 0.5378428000, 1.4967196000", \ - "0.0412989000, 0.0482869000, 0.0653664000, 0.1050909000, 0.2132248000, 0.5377051000, 1.4972383000", \ - "0.0504708000, 0.0586298000, 0.0763564000, 0.1162166000, 0.2214762000, 0.5407692000, 1.4948780000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__and4bb_4") { - leakage_power () { - value : 0.0044753000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0044582000; - when : "A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0041850000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0038272000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0055008000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0041955000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0040912000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0040710000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0044245000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0040931000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0042079000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0041884000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0045071000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0042097000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0044578000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0044517000; - when : "A_N&B_N&!C&!D"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__and4bb"; - cell_leakage_power : 0.0043340310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0014860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083431000, 0.0082432000, 0.0080130000, 0.0080580000, 0.0081615000, 0.0084003000, 0.0089506000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049290000, 0.0048663000, 0.0047218000, 0.0047493000, 0.0048127000, 0.0049588000, 0.0052957000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015450000; - } - pin ("B_N") { - capacitance : 0.0015430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073121000, 0.0072185000, 0.0070028000, 0.0070507000, 0.0071612000, 0.0074160000, 0.0080033000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055482000, 0.0054908000, 0.0053584000, 0.0053946000, 0.0054778000, 0.0056698000, 0.0061123000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016050000; - } - pin ("C") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045814000, 0.0045827000, 0.0045856000, 0.0045879000, 0.0045932000, 0.0046053000, 0.0046333000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004299700, -0.004298900, -0.004297000, -0.004293500, -0.004285300, -0.004266500, -0.004223100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024650000; - } - pin ("D") { - capacitance : 0.0024020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043889000, 0.0043872000, 0.0043834000, 0.0043841000, 0.0043856000, 0.0043892000, 0.0043974000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004375900, -0.004375700, -0.004375100, -0.004375100, -0.004375200, -0.004375200, -0.004375300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025390000; - } - pin ("X") { - direction : "output"; - function : "(!A_N&!B_N&C&D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0216314000, 0.0200731000, 0.0151817000, 0.0008545000, -0.048351600, -0.210034200, -0.717666200", \ - "0.0216567000, 0.0200669000, 0.0152286000, 0.0008792000, -0.048426400, -0.209998400, -0.717710200", \ - "0.0215806000, 0.0201128000, 0.0152188000, 0.0008569000, -0.048488100, -0.209958600, -0.717757800", \ - "0.0213211000, 0.0197794000, 0.0149375000, 0.0005240000, -0.048705500, -0.210254100, -0.718035900", \ - "0.0210157000, 0.0194010000, 0.0145341000, 0.0001536000, -0.049073900, -0.210688900, -0.718355200", \ - "0.0244725000, 0.0228430000, 0.0178375000, 0.0019691000, -0.049263500, -0.210770700, -0.718443200", \ - "0.0248874000, 0.0232354000, 0.0181118000, 0.0022303000, -0.048888300, -0.210724300, -0.718475900"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0283745000, 0.0300614000, 0.0355346000, 0.0531436000, 0.1055725000, 0.2667799000, 0.7696016000", \ - "0.0283693000, 0.0300449000, 0.0355302000, 0.0531005000, 0.1056405000, 0.2669269000, 0.7698181000", \ - "0.0284043000, 0.0301658000, 0.0355812000, 0.0531314000, 0.1056825000, 0.2669574000, 0.7700509000", \ - "0.0282249000, 0.0299025000, 0.0353572000, 0.0528893000, 0.1055430000, 0.2667256000, 0.7699692000", \ - "0.0279578000, 0.0296376000, 0.0350959000, 0.0526381000, 0.1052741000, 0.2662584000, 0.7696083000", \ - "0.0277639000, 0.0294965000, 0.0349927000, 0.0522590000, 0.1049660000, 0.2660684000, 0.7689276000", \ - "0.0294713000, 0.0312304000, 0.0364842000, 0.0534917000, 0.1048124000, 0.2659359000, 0.7680741000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0227262000, 0.0211187000, 0.0161678000, 0.0016230000, -0.047371500, -0.208578500, -0.716073400", \ - "0.0227955000, 0.0211707000, 0.0161700000, 0.0016548000, -0.047316800, -0.208539100, -0.716058200", \ - "0.0228391000, 0.0211360000, 0.0161259000, 0.0016090000, -0.047321800, -0.208549300, -0.716066200", \ - "0.0224601000, 0.0209112000, 0.0158564000, 0.0013813000, -0.047559400, -0.208812300, -0.716313100", \ - "0.0221837000, 0.0205296000, 0.0155259000, 0.0009487000, -0.047899700, -0.209185400, -0.716718500", \ - "0.0257020000, 0.0240301000, 0.0188322000, 0.0027139000, -0.048256800, -0.209476200, -0.716959100", \ - "0.0266061000, 0.0248706000, 0.0197603000, 0.0036570000, -0.047409900, -0.209357700, -0.717045100"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0323523000, 0.0340357000, 0.0396696000, 0.0570493000, 0.1095079000, 0.2704133000, 0.7727715000", \ - "0.0323956000, 0.0340051000, 0.0394586000, 0.0569119000, 0.1095906000, 0.2705603000, 0.7738145000", \ - "0.0323771000, 0.0340757000, 0.0394885000, 0.0570894000, 0.1095530000, 0.2704725000, 0.7729198000", \ - "0.0321819000, 0.0338431000, 0.0393376000, 0.0568711000, 0.1093411000, 0.2702570000, 0.7727954000", \ - "0.0318558000, 0.0335795000, 0.0390095000, 0.0565524000, 0.1090235000, 0.2699553000, 0.7693652000", \ - "0.0315946000, 0.0332830000, 0.0387368000, 0.0560783000, 0.1085035000, 0.2696572000, 0.7690293000", \ - "0.0332792000, 0.0350091000, 0.0402043000, 0.0570493000, 0.1088257000, 0.2694565000, 0.7715606000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0234956000, 0.0217644000, 0.0166856000, 0.0021840000, -0.046818900, -0.208046100, -0.715535300", \ - "0.0234067000, 0.0217485000, 0.0166286000, 0.0020336000, -0.046881700, -0.208153000, -0.715664300", \ - "0.0231188000, 0.0215208000, 0.0164481000, 0.0019471000, -0.047029200, -0.208294000, -0.715773100", \ - "0.0230184000, 0.0213079000, 0.0162841000, 0.0017282000, -0.047215800, -0.208467400, -0.715944900", \ - "0.0233133000, 0.0216260000, 0.0164069000, 0.0015637000, -0.047602900, -0.208795800, -0.716243500", \ - "0.0234344000, 0.0217378000, 0.0164530000, 0.0014039000, -0.047909500, -0.208568200, -0.715882300", \ - "0.0300933000, 0.0280401000, 0.0221323000, 0.0049224000, -0.047198800, -0.208860600, -0.715705000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0325545000, 0.0342248000, 0.0397440000, 0.0570442000, 0.1098269000, 0.2704111000, 0.7723660000", \ - "0.0325092000, 0.0341980000, 0.0396498000, 0.0571955000, 0.1096074000, 0.2704139000, 0.7722816000", \ - "0.0324559000, 0.0341338000, 0.0397206000, 0.0571936000, 0.1093260000, 0.2703138000, 0.7732145000", \ - "0.0322059000, 0.0339463000, 0.0394108000, 0.0568729000, 0.1094409000, 0.2702657000, 0.7731623000", \ - "0.0320654000, 0.0338017000, 0.0392972000, 0.0566069000, 0.1091192000, 0.2701446000, 0.7730799000", \ - "0.0325861000, 0.0341890000, 0.0392975000, 0.0563684000, 0.1089541000, 0.2695662000, 0.7729026000", \ - "0.0355698000, 0.0371624000, 0.0423192000, 0.0586749000, 0.1099828000, 0.2708889000, 0.7711607000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0255155000, 0.0238026000, 0.0187292000, 0.0039137000, -0.045559000, -0.207158800, -0.714744900", \ - "0.0253877000, 0.0236536000, 0.0185393000, 0.0037738000, -0.045661500, -0.207262600, -0.714877900", \ - "0.0253406000, 0.0236433000, 0.0184485000, 0.0036357000, -0.045831100, -0.207386700, -0.714998200", \ - "0.0249918000, 0.0233308000, 0.0181894000, 0.0033878000, -0.045994300, -0.207621700, -0.715191300", \ - "0.0250091000, 0.0234515000, 0.0182731000, 0.0033532000, -0.046126600, -0.207663500, -0.715222200", \ - "0.0261488000, 0.0239497000, 0.0186695000, 0.0034840000, -0.045592700, -0.207247900, -0.714833300", \ - "0.0322584000, 0.0302184000, 0.0242933000, 0.0070478000, -0.045320800, -0.207310000, -0.714639400"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015601280, 0.0048679980, 0.0151894000, 0.0473948100, 0.1478839000, 0.4614356000"); - values("0.0330282000, 0.0347027000, 0.0403058000, 0.0576828000, 0.1100887000, 0.2707566000, 0.7723028000", \ - "0.0329279000, 0.0346374000, 0.0402220000, 0.0577159000, 0.1099274000, 0.2707901000, 0.7730277000", \ - "0.0328943000, 0.0346458000, 0.0401488000, 0.0574378000, 0.1098447000, 0.2705202000, 0.7726878000", \ - "0.0326011000, 0.0342998000, 0.0398793000, 0.0572125000, 0.1096429000, 0.2704424000, 0.7729272000", \ - "0.0323964000, 0.0341297000, 0.0396216000, 0.0570308000, 0.1092787000, 0.2702270000, 0.7694626000", \ - "0.0330400000, 0.0347187000, 0.0398740000, 0.0568710000, 0.1092991000, 0.2700229000, 0.7726822000", \ - "0.0349240000, 0.0365263000, 0.0417559000, 0.0583343000, 0.1098848000, 0.2706974000, 0.7709903000"); - } - } - max_capacitance : 0.4614360000; - max_transition : 1.5021000000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1573647000, 0.1609516000, 0.1700417000, 0.1899120000, 0.2308713000, 0.3260213000, 0.5959435000", \ - "0.1621888000, 0.1657815000, 0.1748657000, 0.1947748000, 0.2357463000, 0.3308724000, 0.6012473000", \ - "0.1735812000, 0.1772231000, 0.1862720000, 0.2062134000, 0.2472176000, 0.3424907000, 0.6122340000", \ - "0.1972499000, 0.2008295000, 0.2099271000, 0.2298493000, 0.2708291000, 0.3661530000, 0.6358452000", \ - "0.2317380000, 0.2353287000, 0.2443675000, 0.2643157000, 0.3054009000, 0.4006697000, 0.6708404000", \ - "0.2752306000, 0.2788328000, 0.2879702000, 0.3079271000, 0.3489881000, 0.4443744000, 0.7143677000", \ - "0.3185968000, 0.3222071000, 0.3313966000, 0.3512929000, 0.3926226000, 0.4879520000, 0.7577873000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.2527794000, 0.2590967000, 0.2753494000, 0.3125502000, 0.3979594000, 0.6252864000, 1.3179275000", \ - "0.2578280000, 0.2640837000, 0.2803663000, 0.3175337000, 0.4029010000, 0.6305272000, 1.3239397000", \ - "0.2705686000, 0.2769245000, 0.2931246000, 0.3302788000, 0.4156664000, 0.6431900000, 1.3367906000", \ - "0.3025889000, 0.3089105000, 0.3251145000, 0.3622635000, 0.4477602000, 0.6751206000, 1.3686180000", \ - "0.3736449000, 0.3799510000, 0.3961517000, 0.4333023000, 0.5188076000, 0.7461144000, 1.4396836000", \ - "0.4982149000, 0.5046044000, 0.5208730000, 0.5577809000, 0.6434338000, 0.8707353000, 1.5641687000", \ - "0.6987806000, 0.7052655000, 0.7214566000, 0.7586792000, 0.8441682000, 1.0719908000, 1.7663476000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0228841000, 0.0250990000, 0.0307970000, 0.0449549000, 0.0813193000, 0.1900604000, 0.5461969000", \ - "0.0229289000, 0.0251762000, 0.0310164000, 0.0447913000, 0.0813798000, 0.1898828000, 0.5484523000", \ - "0.0229698000, 0.0253378000, 0.0311150000, 0.0447634000, 0.0813456000, 0.1892540000, 0.5457810000", \ - "0.0228627000, 0.0250699000, 0.0307911000, 0.0452524000, 0.0810695000, 0.1894744000, 0.5456501000", \ - "0.0230446000, 0.0252100000, 0.0311468000, 0.0451574000, 0.0814839000, 0.1899841000, 0.5483374000", \ - "0.0232158000, 0.0254693000, 0.0314239000, 0.0453699000, 0.0813315000, 0.1892553000, 0.5483339000", \ - "0.0237900000, 0.0257843000, 0.0316413000, 0.0459575000, 0.0818258000, 0.1901312000, 0.5457549000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0385261000, 0.0428149000, 0.0556458000, 0.0891305000, 0.1850935000, 0.4959401000, 1.5018898000", \ - "0.0385329000, 0.0429636000, 0.0555773000, 0.0893176000, 0.1852944000, 0.4962028000, 1.4955704000", \ - "0.0382808000, 0.0428926000, 0.0556162000, 0.0893495000, 0.1853014000, 0.4960119000, 1.4962903000", \ - "0.0379461000, 0.0430001000, 0.0555678000, 0.0893651000, 0.1851135000, 0.4957527000, 1.4963836000", \ - "0.0380350000, 0.0429810000, 0.0555598000, 0.0893283000, 0.1850342000, 0.4956228000, 1.4957974000", \ - "0.0381053000, 0.0432748000, 0.0558459000, 0.0890969000, 0.1854204000, 0.4959261000, 1.5021004000", \ - "0.0387947000, 0.0437908000, 0.0567866000, 0.0900321000, 0.1856994000, 0.4964167000, 1.4974560000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1902416000, 0.1942658000, 0.2044910000, 0.2264204000, 0.2706852000, 0.3693259000, 0.6409564000", \ - "0.1950891000, 0.1991124000, 0.2092618000, 0.2313054000, 0.2752972000, 0.3742852000, 0.6455905000", \ - "0.2064550000, 0.2104967000, 0.2206888000, 0.2426743000, 0.2868010000, 0.3854818000, 0.6573463000", \ - "0.2295737000, 0.2336145000, 0.2437082000, 0.2657413000, 0.3097587000, 0.4087386000, 0.6801067000", \ - "0.2644263000, 0.2684814000, 0.2786268000, 0.3006271000, 0.3449658000, 0.4436678000, 0.7152481000", \ - "0.3071369000, 0.3111751000, 0.3213463000, 0.3433700000, 0.3874997000, 0.4863515000, 0.7579519000", \ - "0.3468430000, 0.3509090000, 0.3610140000, 0.3829705000, 0.4272286000, 0.5262587000, 0.7980118000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.2831284000, 0.2895229000, 0.3058829000, 0.3430043000, 0.4284429000, 0.6555056000, 1.3526784000", \ - "0.2882196000, 0.2944481000, 0.3106778000, 0.3480329000, 0.4334373000, 0.6606263000, 1.3560215000", \ - "0.3007080000, 0.3070758000, 0.3233190000, 0.3605585000, 0.4459820000, 0.6727549000, 1.3667549000", \ - "0.3322717000, 0.3385683000, 0.3548422000, 0.3920428000, 0.4774746000, 0.7044634000, 1.3976398000", \ - "0.4046245000, 0.4110236000, 0.4272367000, 0.4644361000, 0.5498517000, 0.7770583000, 1.4686800000", \ - "0.5365640000, 0.5428743000, 0.5591194000, 0.5962979000, 0.6820663000, 0.9093383000, 1.6006307000", \ - "0.7511622000, 0.7576208000, 0.7739788000, 0.8116625000, 0.8974151000, 1.1250453000, 1.8188092000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0274193000, 0.0299132000, 0.0358057000, 0.0501371000, 0.0871598000, 0.1950310000, 0.5508927000", \ - "0.0271244000, 0.0295025000, 0.0356855000, 0.0506294000, 0.0874699000, 0.1947838000, 0.5487532000", \ - "0.0271247000, 0.0295741000, 0.0357161000, 0.0505077000, 0.0868552000, 0.1950921000, 0.5507783000", \ - "0.0272766000, 0.0298196000, 0.0357765000, 0.0506030000, 0.0875050000, 0.1947538000, 0.5484682000", \ - "0.0272745000, 0.0295248000, 0.0356873000, 0.0505939000, 0.0873030000, 0.1950797000, 0.5503938000", \ - "0.0274355000, 0.0297430000, 0.0361804000, 0.0509712000, 0.0870816000, 0.1950222000, 0.5480667000", \ - "0.0274855000, 0.0299189000, 0.0363732000, 0.0512780000, 0.0877479000, 0.1952287000, 0.5507044000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0383036000, 0.0432059000, 0.0561093000, 0.0894522000, 0.1853782000, 0.4955326000, 1.4986018000", \ - "0.0383154000, 0.0430069000, 0.0563568000, 0.0895937000, 0.1852546000, 0.4959880000, 1.5011178000", \ - "0.0388167000, 0.0432113000, 0.0559534000, 0.0893005000, 0.1852941000, 0.4954920000, 1.5018063000", \ - "0.0384054000, 0.0430991000, 0.0559359000, 0.0893697000, 0.1852686000, 0.4958917000, 1.5020928000", \ - "0.0383500000, 0.0431443000, 0.0558999000, 0.0894009000, 0.1852430000, 0.4962020000, 1.4969461000", \ - "0.0385349000, 0.0432088000, 0.0563154000, 0.0898347000, 0.1856846000, 0.4962917000, 1.4966052000", \ - "0.0391797000, 0.0442415000, 0.0570765000, 0.0905811000, 0.1860427000, 0.4954906000, 1.4976829000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1598173000, 0.1638519000, 0.1743019000, 0.1962798000, 0.2407123000, 0.3392568000, 0.6111329000", \ - "0.1652696000, 0.1693836000, 0.1795940000, 0.2017921000, 0.2460680000, 0.3447140000, 0.6165648000", \ - "0.1786036000, 0.1827034000, 0.1931899000, 0.2151967000, 0.2595266000, 0.3581260000, 0.6299790000", \ - "0.2102472000, 0.2143439000, 0.2246304000, 0.2465616000, 0.2907179000, 0.3894595000, 0.6612257000", \ - "0.2865555000, 0.2906560000, 0.3008815000, 0.3229104000, 0.3673447000, 0.4660102000, 0.7374907000", \ - "0.4445193000, 0.4493148000, 0.4614451000, 0.4863797000, 0.5337875000, 0.6324741000, 0.9041330000", \ - "0.7069135000, 0.7129505000, 0.7289426000, 0.7621238000, 0.8218978000, 0.9328686000, 1.2082414000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1887677000, 0.1950973000, 0.2113530000, 0.2484586000, 0.3340250000, 0.5607224000, 1.2575807000", \ - "0.1928044000, 0.1991498000, 0.2153816000, 0.2526475000, 0.3380600000, 0.5647040000, 1.2609641000", \ - "0.2003611000, 0.2066366000, 0.2229717000, 0.2600735000, 0.3452555000, 0.5724318000, 1.2649932000", \ - "0.2149659000, 0.2213362000, 0.2375453000, 0.2747044000, 0.3600520000, 0.5872389000, 1.2831401000", \ - "0.2484626000, 0.2548141000, 0.2711601000, 0.3083679000, 0.3938191000, 0.6211956000, 1.3162265000", \ - "0.3061507000, 0.3130952000, 0.3308375000, 0.3700997000, 0.4583497000, 0.6867004000, 1.3827077000", \ - "0.3727611000, 0.3810062000, 0.4019429000, 0.4469528000, 0.5397266000, 0.7706166000, 1.4624113000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0282668000, 0.0311029000, 0.0371216000, 0.0516748000, 0.0871658000, 0.1947900000, 0.5500424000", \ - "0.0285659000, 0.0310490000, 0.0370838000, 0.0510109000, 0.0875982000, 0.1950513000, 0.5505449000", \ - "0.0287031000, 0.0312649000, 0.0367697000, 0.0518010000, 0.0875152000, 0.1950106000, 0.5505739000", \ - "0.0282909000, 0.0307017000, 0.0368258000, 0.0510956000, 0.0876761000, 0.1949243000, 0.5506350000", \ - "0.0285330000, 0.0310691000, 0.0369758000, 0.0516461000, 0.0877727000, 0.1946649000, 0.5492950000", \ - "0.0375176000, 0.0402398000, 0.0465784000, 0.0598146000, 0.0928117000, 0.1970833000, 0.5512052000", \ - "0.0571486000, 0.0606160000, 0.0682700000, 0.0850498000, 0.1189475000, 0.2144595000, 0.5528048000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0380964000, 0.0428955000, 0.0561805000, 0.0894818000, 0.1854534000, 0.4954516000, 1.4986251000", \ - "0.0384278000, 0.0431573000, 0.0562713000, 0.0894688000, 0.1854229000, 0.4952411000, 1.4995670000", \ - "0.0382777000, 0.0428536000, 0.0560058000, 0.0894434000, 0.1851887000, 0.4961691000, 1.4971454000", \ - "0.0380120000, 0.0432103000, 0.0561318000, 0.0894357000, 0.1853646000, 0.4962098000, 1.5020960000", \ - "0.0390875000, 0.0436740000, 0.0566371000, 0.0898737000, 0.1854331000, 0.4960641000, 1.5009617000", \ - "0.0436847000, 0.0487500000, 0.0615478000, 0.0959124000, 0.1896933000, 0.4976875000, 1.5015713000", \ - "0.0566193000, 0.0618545000, 0.0758456000, 0.1087840000, 0.2000980000, 0.5015577000, 1.4961996000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1683951000, 0.1726098000, 0.1830781000, 0.2055305000, 0.2501211000, 0.3491307000, 0.6210488000", \ - "0.1736389000, 0.1778304000, 0.1883309000, 0.2108138000, 0.2553301000, 0.3543986000, 0.6265743000", \ - "0.1866492000, 0.1908418000, 0.2013090000, 0.2237913000, 0.2683676000, 0.3674482000, 0.6395775000", \ - "0.2193963000, 0.2234641000, 0.2339336000, 0.2562770000, 0.3009491000, 0.4002638000, 0.6722199000", \ - "0.2954966000, 0.2988508000, 0.3093364000, 0.3317075000, 0.3763724000, 0.4756442000, 0.7477292000", \ - "0.4587966000, 0.4626010000, 0.4744777000, 0.4993453000, 0.5458428000, 0.6455589000, 0.9173171000", \ - "0.7298397000, 0.7363023000, 0.7520936000, 0.7849549000, 0.8443329000, 0.9546879000, 1.2302002000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.1953275000, 0.2017336000, 0.2179646000, 0.2550882000, 0.3405206000, 0.5667204000, 1.2619501000", \ - "0.1993508000, 0.2057088000, 0.2219721000, 0.2591539000, 0.3443727000, 0.5714159000, 1.2637142000", \ - "0.2068414000, 0.2132153000, 0.2295119000, 0.2664806000, 0.3518985000, 0.5786731000, 1.2693565000", \ - "0.2200260000, 0.2263735000, 0.2426848000, 0.2797658000, 0.3651220000, 0.5921270000, 1.2871453000", \ - "0.2463788000, 0.2527667000, 0.2691530000, 0.3063540000, 0.3916073000, 0.6189575000, 1.3096710000", \ - "0.2907794000, 0.2976751000, 0.3152830000, 0.3546412000, 0.4424688000, 0.6707028000, 1.3618275000", \ - "0.3433510000, 0.3511770000, 0.3714923000, 0.4156097000, 0.5082783000, 0.7394841000, 1.4317426000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0294619000, 0.0319237000, 0.0379932000, 0.0529994000, 0.0889417000, 0.1954931000, 0.5500668000", \ - "0.0294984000, 0.0320133000, 0.0384155000, 0.0529450000, 0.0887512000, 0.1958557000, 0.5509372000", \ - "0.0297860000, 0.0322728000, 0.0379766000, 0.0529715000, 0.0891193000, 0.1954438000, 0.5509813000", \ - "0.0297407000, 0.0318504000, 0.0386461000, 0.0525376000, 0.0890384000, 0.1958564000, 0.5511553000", \ - "0.0297402000, 0.0317773000, 0.0381027000, 0.0530488000, 0.0888589000, 0.1960245000, 0.5498464000", \ - "0.0375904000, 0.0403250000, 0.0467201000, 0.0599591000, 0.0941927000, 0.1975218000, 0.5488145000", \ - "0.0574096000, 0.0610890000, 0.0683878000, 0.0847378000, 0.1185292000, 0.2141488000, 0.5532981000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015601300, 0.0048680000, 0.0151894000, 0.0473948000, 0.1478840000, 0.4614360000"); - values("0.0381973000, 0.0429556000, 0.0561017000, 0.0892551000, 0.1853523000, 0.4953188000, 1.5003969000", \ - "0.0381526000, 0.0430599000, 0.0561384000, 0.0894586000, 0.1854165000, 0.4961984000, 1.4959740000", \ - "0.0382099000, 0.0431736000, 0.0560315000, 0.0893783000, 0.1852860000, 0.4962690000, 1.5005754000", \ - "0.0380948000, 0.0429070000, 0.0560820000, 0.0895317000, 0.1853159000, 0.4961254000, 1.5015634000", \ - "0.0390031000, 0.0439246000, 0.0564985000, 0.0898164000, 0.1855614000, 0.4953618000, 1.4961868000", \ - "0.0432423000, 0.0483798000, 0.0614864000, 0.0947681000, 0.1891534000, 0.4961911000, 1.5007009000", \ - "0.0529029000, 0.0581981000, 0.0723372000, 0.1067401000, 0.1991793000, 0.5006260000, 1.4948426000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_1") { - leakage_power () { - value : 0.0011810000; - when : "A"; - } - leakage_power () { - value : 0.0011810000; - when : "!A"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0011810180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020150000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0021910000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0108054000, 0.0097834000, 0.0069418000, -0.000808000, -0.020725600, -0.071111700, -0.198366400", \ - "0.0105490000, 0.0095435000, 0.0066983000, -0.001032800, -0.020903300, -0.071322800, -0.198572800", \ - "0.0103270000, 0.0093022000, 0.0064758000, -0.001239900, -0.021126200, -0.071476300, -0.198740200", \ - "0.0102095000, 0.0091712000, 0.0063456000, -0.001333800, -0.021148000, -0.071505900, -0.198745900", \ - "0.0100561000, 0.0088657000, 0.0061667000, -0.001306700, -0.021101500, -0.071399700, -0.198641200", \ - "0.0109558000, 0.0097739000, 0.0068849000, -0.001026800, -0.020488100, -0.070778700, -0.197991500", \ - "0.0130202000, 0.0117825000, 0.0085657000, 0.0007253000, -0.018986900, -0.069230600, -0.196265500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0055419000, 0.0068503000, 0.0100473000, 0.0178595000, 0.0375954000, 0.0871212000, 0.2131056000", \ - "0.0053503000, 0.0066616000, 0.0098534000, 0.0176911000, 0.0374077000, 0.0870674000, 0.2132897000", \ - "0.0050781000, 0.0063676000, 0.0095487000, 0.0174572000, 0.0372335000, 0.0874168000, 0.2141486000", \ - "0.0048520000, 0.0061368000, 0.0093023000, 0.0171699000, 0.0372440000, 0.0873148000, 0.2129033000", \ - "0.0049546000, 0.0062219000, 0.0091832000, 0.0171287000, 0.0369737000, 0.0872763000, 0.2114916000", \ - "0.0056157000, 0.0068724000, 0.0099311000, 0.0177538000, 0.0375448000, 0.0874654000, 0.2136360000", \ - "0.0076352000, 0.0087407000, 0.0118673000, 0.0196942000, 0.0394077000, 0.0893026000, 0.2147773000"); - } - } - max_capacitance : 0.1300150000; - max_transition : 1.5061030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0593383000, 0.0643396000, 0.0749824000, 0.0973634000, 0.1492992000, 0.2787939000, 0.6061452000", \ - "0.0642426000, 0.0692853000, 0.0799011000, 0.1024859000, 0.1544812000, 0.2841778000, 0.6104910000", \ - "0.0775104000, 0.0825737000, 0.0932367000, 0.1157306000, 0.1676768000, 0.2973737000, 0.6245092000", \ - "0.1077616000, 0.1129200000, 0.1237785000, 0.1465237000, 0.1985575000, 0.3280511000, 0.6562919000", \ - "0.1578797000, 0.1640413000, 0.1763553000, 0.2008799000, 0.2542707000, 0.3828144000, 0.7146603000", \ - "0.2342690000, 0.2423609000, 0.2577376000, 0.2850985000, 0.3398958000, 0.4700387000, 0.7969230000", \ - "0.3559006000, 0.3662604000, 0.3859527000, 0.4198348000, 0.4788887000, 0.6104675000, 0.9385767000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0490569000, 0.0558265000, 0.0717435000, 0.1104504000, 0.2075838000, 0.4514763000, 1.0684844000", \ - "0.0536074000, 0.0603471000, 0.0762774000, 0.1149897000, 0.2116108000, 0.4563259000, 1.0785807000", \ - "0.0642037000, 0.0708758000, 0.0866203000, 0.1255204000, 0.2235220000, 0.4693128000, 1.0892596000", \ - "0.0819207000, 0.0888360000, 0.1049964000, 0.1440040000, 0.2421219000, 0.4876812000, 1.1038942000", \ - "0.1041913000, 0.1115879000, 0.1278155000, 0.1672534000, 0.2646072000, 0.5103125000, 1.1274786000", \ - "0.1259206000, 0.1349041000, 0.1524062000, 0.1916016000, 0.2898473000, 0.5344468000, 1.1529084000", \ - "0.1292959000, 0.1413072000, 0.1638067000, 0.2061120000, 0.3024876000, 0.5484357000, 1.1667728000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0148871000, 0.0193113000, 0.0295451000, 0.0550503000, 0.1221799000, 0.2947354000, 0.7299648000", \ - "0.0149669000, 0.0193011000, 0.0296604000, 0.0550240000, 0.1216383000, 0.2941434000, 0.7294372000", \ - "0.0148895000, 0.0193335000, 0.0296440000, 0.0552030000, 0.1215139000, 0.2953373000, 0.7259581000", \ - "0.0160523000, 0.0203110000, 0.0303481000, 0.0553778000, 0.1213409000, 0.2931113000, 0.7299997000", \ - "0.0210846000, 0.0252021000, 0.0349793000, 0.0592462000, 0.1230172000, 0.2943069000, 0.7270705000", \ - "0.0302076000, 0.0347994000, 0.0445488000, 0.0668841000, 0.1277289000, 0.2943685000, 0.7330043000", \ - "0.0437670000, 0.0497366000, 0.0604570000, 0.0823759000, 0.1373515000, 0.2985862000, 0.7278568000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0199796000, 0.0284097000, 0.0500678000, 0.1054104000, 0.2462960000, 0.6007088000, 1.4976728000", \ - "0.0200424000, 0.0284104000, 0.0500598000, 0.1055191000, 0.2465992000, 0.6007418000, 1.4982898000", \ - "0.0201431000, 0.0285117000, 0.0500371000, 0.1053906000, 0.2469039000, 0.6047496000, 1.5061026000", \ - "0.0215548000, 0.0297102000, 0.0507718000, 0.1054864000, 0.2473741000, 0.6047852000, 1.4980543000", \ - "0.0249477000, 0.0322865000, 0.0523515000, 0.1064977000, 0.2460664000, 0.6010622000, 1.4926799000", \ - "0.0326877000, 0.0396409000, 0.0572465000, 0.1079538000, 0.2475174000, 0.5992588000, 1.5009650000", \ - "0.0467759000, 0.0543678000, 0.0709174000, 0.1149097000, 0.2482231000, 0.6031189000, 1.4938381000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_12") { - leakage_power () { - value : 0.0081264000; - when : "!A"; - } - leakage_power () { - value : 0.0106673000; - when : "A"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0093968470; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0091870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0087510000; - max_transition : 5.0000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0096230000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.0845295000, 0.0820553000, 0.0701132000, 0.0134388000, -0.274977100, -1.642889500, -7.997506400", \ - "0.0835640000, 0.0811442000, 0.0692298000, 0.0126691000, -0.275680200, -1.643526800, -7.998352900", \ - "0.0827306000, 0.0802787000, 0.0681703000, 0.0113923000, -0.276833300, -1.644430300, -7.999068500", \ - "0.0829302000, 0.0801578000, 0.0674770000, 0.0093441000, -0.278229500, -1.645021500, -7.999331300", \ - "0.0882843000, 0.0850476000, 0.0711066000, 0.0084375000, -0.278058300, -1.643332200, -7.997528100", \ - "0.1053451000, 0.1017648000, 0.0863334000, 0.0220579000, -0.272025800, -1.636704600, -7.990387100", \ - "0.1425625000, 0.1384592000, 0.1211598000, 0.0513344000, -0.239387800, -1.605944500, -7.957940800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.0620334000, 0.0654014000, 0.0806191000, 0.1479065000, 0.4431781000, 1.8013914000, 8.0753762000", \ - "0.0614370000, 0.0647659000, 0.0799535000, 0.1471886000, 0.4426693000, 1.8008019000, 8.0748341000", \ - "0.0605373000, 0.0637722000, 0.0787201000, 0.1451670000, 0.4413537000, 1.8015678000, 8.0855365000", \ - "0.0600135000, 0.0631292000, 0.0775817000, 0.1420690000, 0.4385360000, 1.7996347000, 8.1049749000", \ - "0.0635240000, 0.0665334000, 0.0803772000, 0.1440405000, 0.4380485000, 1.7947636000, 8.0981878000", \ - "0.0727430000, 0.0754100000, 0.0887289000, 0.1520489000, 0.4473673000, 1.7952139000, 8.0980638000", \ - "0.1104480000, 0.1124938000, 0.1239041000, 0.1845408000, 0.4746102000, 1.8290743000, 8.1093992000"); - } - } - max_capacitance : 5.0000000000; - max_transition : 5.3987540000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0949892000, 0.0969633000, 0.1046134000, 0.1279145000, 0.1966168000, 0.4678506000, 1.7175281000", \ - "0.1025689000, 0.1045411000, 0.1122052000, 0.1354764000, 0.2042515000, 0.4756746000, 1.7231814000", \ - "0.1255348000, 0.1275642000, 0.1351161000, 0.1582046000, 0.2269068000, 0.4986806000, 1.7456755000", \ - "0.1927474000, 0.1947159000, 0.2023256000, 0.2255138000, 0.2945059000, 0.5656756000, 1.8136015000", \ - "0.3307603000, 0.3334811000, 0.3438259000, 0.3733021000, 0.4485304000, 0.7199566000, 1.9725541000", \ - "0.5829514000, 0.5866292000, 0.6008373000, 0.6424990000, 0.7366560000, 1.0135535000, 2.2596505000", \ - "1.0913156000, 1.0959489000, 1.1145755000, 1.1709795000, 1.3002396000, 1.6008217000, 2.8480049000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0650638000, 0.0674117000, 0.0768585000, 0.1114816000, 0.2514564000, 0.8908578000, 3.8409733000", \ - "0.0713476000, 0.0736797000, 0.0832443000, 0.1178472000, 0.2578924000, 0.8969483000, 3.8472141000", \ - "0.0898608000, 0.0921825000, 0.1015178000, 0.1358464000, 0.2761783000, 0.9189151000, 3.8970014000", \ - "0.1242959000, 0.1267950000, 0.1366756000, 0.1717450000, 0.3125261000, 0.9535477000, 3.9106594000", \ - "0.1646814000, 0.1679549000, 0.1801210000, 0.2176404000, 0.3586583000, 0.9978574000, 3.9592343000", \ - "0.1720261000, 0.1766313000, 0.1941311000, 0.2431584000, 0.3871028000, 1.0229786000, 3.9844092000", \ - "0.0189083000, 0.0248574000, 0.0487934000, 0.1204249000, 0.2900516000, 0.9268094000, 3.8755106000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0188065000, 0.0200502000, 0.0251049000, 0.0431682000, 0.1186776000, 0.4858429000, 2.2073519000", \ - "0.0187993000, 0.0200397000, 0.0250788000, 0.0432387000, 0.1187297000, 0.4849536000, 2.2126707000", \ - "0.0188645000, 0.0201678000, 0.0250437000, 0.0432999000, 0.1187651000, 0.4858813000, 2.2136801000", \ - "0.0201325000, 0.0213063000, 0.0260948000, 0.0441702000, 0.1188103000, 0.4859662000, 2.2089581000", \ - "0.0332266000, 0.0344399000, 0.0401701000, 0.0573838000, 0.1266752000, 0.4862756000, 2.2204474000", \ - "0.0562236000, 0.0576208000, 0.0649062000, 0.0869760000, 0.1514301000, 0.4916945000, 2.2118438000", \ - "0.0951367000, 0.0971284000, 0.1053148000, 0.1360943000, 0.2064867000, 0.5099419000, 2.2162143000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0189041000, 0.0209278000, 0.0299881000, 0.0706864000, 0.2656687000, 1.1809174000, 5.3821241000", \ - "0.0189170000, 0.0209368000, 0.0299694000, 0.0706965000, 0.2656746000, 1.1809158000, 5.3803393000", \ - "0.0190231000, 0.0210741000, 0.0301710000, 0.0707973000, 0.2662922000, 1.1822107000, 5.3935314000", \ - "0.0222837000, 0.0242461000, 0.0329869000, 0.0725724000, 0.2658119000, 1.1829101000, 5.3965397000", \ - "0.0320236000, 0.0342046000, 0.0422819000, 0.0783372000, 0.2669940000, 1.1765062000, 5.3974536000", \ - "0.0512623000, 0.0543692000, 0.0641832000, 0.0986279000, 0.2710747000, 1.1776644000, 5.3987543000", \ - "0.0857587000, 0.0893657000, 0.1039385000, 0.1483427000, 0.2969043000, 1.1828638000, 5.3802660000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_16") { - leakage_power () { - value : 0.0139726000; - when : "A"; - } - leakage_power () { - value : 0.0113831000; - when : "!A"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0126778200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0136390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0129700000; - max_transition : 5.0000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0143080000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.1246978000, 0.1220913000, 0.1104641000, 0.0538971000, -0.234671400, -1.602576300, -7.957318900", \ - "0.1234288000, 0.1208317000, 0.1090858000, 0.0527313000, -0.235890900, -1.603727600, -7.958118600", \ - "0.1221183000, 0.1195552000, 0.1076350000, 0.0510193000, -0.237189400, -1.604830300, -7.959301700", \ - "0.1212383000, 0.1185006000, 0.1058806000, 0.0488954000, -0.238548800, -1.605060900, -7.959295600", \ - "0.1239764000, 0.1209791000, 0.1070879000, 0.0475257000, -0.238189700, -1.603509800, -7.957640700", \ - "0.1459304000, 0.1424503000, 0.1272265000, 0.0623106000, -0.230399300, -1.592447100, -7.946090100", \ - "0.1995127000, 0.1953813000, 0.1777306000, 0.1065620000, -0.191103100, -1.558831100, -7.903618900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.0855181000, 0.0889249000, 0.1043875000, 0.1718084000, 0.4658471000, 1.8193522000, 8.1144291000", \ - "0.0845629000, 0.0879728000, 0.1034413000, 0.1709328000, 0.4649818000, 1.8206075000, 8.1002763000", \ - "0.0832347000, 0.0865134000, 0.1015727000, 0.1685777000, 0.4632598000, 1.8152654000, 8.0982328000", \ - "0.0817534000, 0.0849143000, 0.0993675000, 0.1653603000, 0.4608835000, 1.8179774000, 8.1146199000", \ - "0.0859527000, 0.0889201000, 0.1029112000, 0.1669121000, 0.4611070000, 1.8167909000, 8.0971373000", \ - "0.0989076000, 0.1016914000, 0.1149179000, 0.1785657000, 0.4730205000, 1.8277568000, 8.1082682000", \ - "0.1509171000, 0.1532284000, 0.1643944000, 0.2246167000, 0.5135391000, 1.8656588000, 8.1511384000"); - } - } - max_capacitance : 5.0000000000; - max_transition : 5.0073100000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0988300000, 0.1005500000, 0.1074841000, 0.1299030000, 0.1986581000, 0.4693248000, 1.7130586000", \ - "0.1062454000, 0.1079605000, 0.1148681000, 0.1373817000, 0.2061646000, 0.4769360000, 1.7191242000", \ - "0.1293577000, 0.1310702000, 0.1379407000, 0.1604263000, 0.2291486000, 0.5008881000, 1.7450741000", \ - "0.1961166000, 0.1978042000, 0.2046897000, 0.2266695000, 0.2958042000, 0.5663478000, 1.8105072000", \ - "0.3343349000, 0.3366060000, 0.3456134000, 0.3732534000, 0.4479846000, 0.7205929000, 1.9640718000", \ - "0.5895854000, 0.5927187000, 0.6045447000, 0.6425749000, 0.7348270000, 1.0127071000, 2.2523436000", \ - "1.1099183000, 1.1135470000, 1.1288707000, 1.1788674000, 1.3022902000, 1.6021292000, 2.8411489000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0699465000, 0.0720265000, 0.0806863000, 0.1123300000, 0.2371367000, 0.8045733000, 3.4296477000", \ - "0.0761547000, 0.0782439000, 0.0868256000, 0.1185513000, 0.2433967000, 0.8112872000, 3.4485761000", \ - "0.0941300000, 0.0961656000, 0.1046878000, 0.1361711000, 0.2615364000, 0.8345354000, 3.4633343000", \ - "0.1264587000, 0.1286038000, 0.1373975000, 0.1696380000, 0.2955609000, 0.8647546000, 3.4934911000", \ - "0.1638667000, 0.1664669000, 0.1767662000, 0.2109544000, 0.3371712000, 0.9042485000, 3.5293068000", \ - "0.1643597000, 0.1679857000, 0.1822371000, 0.2262780000, 0.3553059000, 0.9229272000, 3.5579750000", \ - "-0.006149700, -0.001543900, 0.0176675000, 0.0804246000, 0.2339132000, 0.7999581000, 3.4244187000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0215181000, 0.0225003000, 0.0273300000, 0.0470790000, 0.1348187000, 0.5550561000, 2.5366818000", \ - "0.0214673000, 0.0225938000, 0.0273514000, 0.0471413000, 0.1350093000, 0.5551501000, 2.5337594000", \ - "0.0214186000, 0.0225075000, 0.0274148000, 0.0472801000, 0.1346374000, 0.5555522000, 2.5332130000", \ - "0.0227291000, 0.0238694000, 0.0285113000, 0.0481077000, 0.1351350000, 0.5548976000, 2.5356408000", \ - "0.0361482000, 0.0374594000, 0.0420970000, 0.0605439000, 0.1418320000, 0.5563526000, 2.5355942000", \ - "0.0600952000, 0.0615765000, 0.0678731000, 0.0893322000, 0.1646243000, 0.5619279000, 2.5323117000", \ - "0.1011759000, 0.1028323000, 0.1101437000, 0.1361253000, 0.2153841000, 0.5790518000, 2.5394404000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0230588000, 0.0248546000, 0.0332228000, 0.0712671000, 0.2512469000, 1.0954657000, 5.0065481000", \ - "0.0230843000, 0.0249191000, 0.0332189000, 0.0712122000, 0.2514922000, 1.0968062000, 4.9953122000", \ - "0.0231802000, 0.0249681000, 0.0333393000, 0.0712893000, 0.2516783000, 1.0954793000, 4.9848872000", \ - "0.0260728000, 0.0278695000, 0.0359157000, 0.0735272000, 0.2517448000, 1.0954602000, 5.0073101000", \ - "0.0356272000, 0.0372748000, 0.0444349000, 0.0786669000, 0.2530062000, 1.0931542000, 4.9964970000", \ - "0.0557360000, 0.0578185000, 0.0667516000, 0.0981551000, 0.2580237000, 1.0953476000, 4.9966862000", \ - "0.0922075000, 0.0948970000, 0.1066020000, 0.1470978000, 0.2859251000, 1.0980127000, 5.0024260000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_2") { - leakage_power () { - value : 0.0022662000; - when : "A"; - } - leakage_power () { - value : 0.0056021000; - when : "!A"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0039341160; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0017270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016470000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018070000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0140552000, 0.0126442000, 0.0087911000, -0.003411300, -0.042009300, -0.156917700, -0.493912600", \ - "0.0139263000, 0.0125071000, 0.0086699000, -0.003513500, -0.042160300, -0.157048900, -0.493994300", \ - "0.0137287000, 0.0123189000, 0.0084174000, -0.003752100, -0.042330400, -0.157214000, -0.494144400", \ - "0.0135482000, 0.0121169000, 0.0081683000, -0.004023800, -0.042588200, -0.157377600, -0.494321700", \ - "0.0135475000, 0.0119986000, 0.0079343000, -0.004322900, -0.042768800, -0.157394400, -0.494357600", \ - "0.0152041000, 0.0135653000, 0.0089886000, -0.004284200, -0.042783600, -0.157390300, -0.494036900", \ - "0.0175151000, 0.0157242000, 0.0108343000, -0.002649900, -0.041709900, -0.156306300, -0.492936900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0116392000, 0.0133460000, 0.0181670000, 0.0317444000, 0.0708086000, 0.1847454000, 0.5207413000", \ - "0.0115450000, 0.0132567000, 0.0180731000, 0.0317090000, 0.0707365000, 0.1848036000, 0.5181148000", \ - "0.0113765000, 0.0130574000, 0.0178759000, 0.0315052000, 0.0706164000, 0.1845360000, 0.5185803000", \ - "0.0112172000, 0.0128696000, 0.0176085000, 0.0310245000, 0.0702931000, 0.1844760000, 0.5164646000", \ - "0.0111513000, 0.0127277000, 0.0175003000, 0.0308402000, 0.0697736000, 0.1841383000, 0.5173316000", \ - "0.0119311000, 0.0135030000, 0.0180230000, 0.0312097000, 0.0699882000, 0.1832520000, 0.5201987000", \ - "0.0132045000, 0.0146753000, 0.0190707000, 0.0324496000, 0.0710814000, 0.1853545000, 0.5186740000"); - } - } - max_capacitance : 0.3158670000; - max_transition : 1.5103890000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0893825000, 0.0940128000, 0.1043020000, 0.1253087000, 0.1706670000, 0.2867790000, 0.6215225000", \ - "0.0947109000, 0.0992768000, 0.1095723000, 0.1305028000, 0.1759432000, 0.2920352000, 0.6262424000", \ - "0.1073098000, 0.1122147000, 0.1224900000, 0.1435736000, 0.1888902000, 0.3050100000, 0.6394017000", \ - "0.1390839000, 0.1436487000, 0.1538906000, 0.1749740000, 0.2204538000, 0.3366603000, 0.6718233000", \ - "0.2069192000, 0.2119847000, 0.2231280000, 0.2451737000, 0.2912927000, 0.4071439000, 0.7431974000", \ - "0.3151437000, 0.3217471000, 0.3360783000, 0.3632810000, 0.4144178000, 0.5330332000, 0.8664172000", \ - "0.4806499000, 0.4891128000, 0.5079365000, 0.5444191000, 0.6065489000, 0.7308373000, 1.0635163000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0668910000, 0.0718924000, 0.0840012000, 0.1134072000, 0.1935354000, 0.4261705000, 1.1063915000", \ - "0.0716767000, 0.0766803000, 0.0887568000, 0.1182065000, 0.1984368000, 0.4311861000, 1.1152972000", \ - "0.0829645000, 0.0879570000, 0.0999870000, 0.1294499000, 0.2100037000, 0.4433682000, 1.1281723000", \ - "0.1086829000, 0.1137214000, 0.1257475000, 0.1551004000, 0.2355409000, 0.4675719000, 1.1647491000", \ - "0.1485626000, 0.1544699000, 0.1680141000, 0.1985122000, 0.2787439000, 0.5129941000, 1.1919699000", \ - "0.1975048000, 0.2056084000, 0.2226795000, 0.2560802000, 0.3372415000, 0.5701722000, 1.2502678000", \ - "0.2460262000, 0.2566468000, 0.2796226000, 0.3221350000, 0.4059333000, 0.6372368000, 1.3161603000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0178310000, 0.0207207000, 0.0278897000, 0.0455429000, 0.0939806000, 0.2427863000, 0.6972716000", \ - "0.0175943000, 0.0207175000, 0.0279071000, 0.0458368000, 0.0940654000, 0.2429276000, 0.6955793000", \ - "0.0178137000, 0.0205648000, 0.0279116000, 0.0457148000, 0.0938515000, 0.2421597000, 0.6948925000", \ - "0.0177391000, 0.0207459000, 0.0279198000, 0.0456478000, 0.0938481000, 0.2423421000, 0.6983182000", \ - "0.0218519000, 0.0246050000, 0.0314674000, 0.0480329000, 0.0950875000, 0.2430947000, 0.6911738000", \ - "0.0325958000, 0.0363413000, 0.0443101000, 0.0605935000, 0.1048121000, 0.2452953000, 0.6901063000", \ - "0.0498742000, 0.0548127000, 0.0644672000, 0.0838614000, 0.1254033000, 0.2553391000, 0.6907858000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0173427000, 0.0217460000, 0.0342817000, 0.0713277000, 0.1844091000, 0.5209731000, 1.5096145000", \ - "0.0172691000, 0.0217777000, 0.0342816000, 0.0713081000, 0.1846570000, 0.5218083000, 1.5055296000", \ - "0.0173301000, 0.0217210000, 0.0341901000, 0.0713260000, 0.1844059000, 0.5209821000, 1.5073524000", \ - "0.0181680000, 0.0224998000, 0.0347377000, 0.0715538000, 0.1849883000, 0.5212006000, 1.5081902000", \ - "0.0238874000, 0.0279114000, 0.0392879000, 0.0740700000, 0.1850683000, 0.5226318000, 1.5055001000", \ - "0.0337211000, 0.0383696000, 0.0494030000, 0.0810920000, 0.1869322000, 0.5191824000, 1.5103887000", \ - "0.0482771000, 0.0551313000, 0.0683274000, 0.0976699000, 0.1936813000, 0.5238303000, 1.4991499000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_4") { - leakage_power () { - value : 0.0041507000; - when : "A"; - } - leakage_power () { - value : 0.0054587000; - when : "!A"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0048047400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022760000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025240000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016118760, 0.0051962870, 0.0167515400, 0.0540028000, 0.1740916000, 0.5612281000"); - values("0.0250387000, 0.0233860000, 0.0180599000, 0.0018219000, -0.056422600, -0.250180600, -0.877232400", \ - "0.0248583000, 0.0231565000, 0.0179592000, 0.0015346000, -0.056581000, -0.250323600, -0.877487500", \ - "0.0245577000, 0.0228640000, 0.0176583000, 0.0013406000, -0.056846800, -0.250677000, -0.877688000", \ - "0.0244145000, 0.0227070000, 0.0173772000, 0.0008926000, -0.057188000, -0.250845800, -0.877855800", \ - "0.0246491000, 0.0229037000, 0.0176337000, 0.0007448000, -0.057488900, -0.251136400, -0.877964600", \ - "0.0275949000, 0.0256361000, 0.0191608000, 0.0006189000, -0.057703700, -0.250607900, -0.877240100", \ - "0.0316715000, 0.0295242000, 0.0237961000, 0.0044928000, -0.055795900, -0.249579000, -0.876104200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016118760, 0.0051962870, 0.0167515400, 0.0540028000, 0.1740916000, 0.5612281000"); - values("0.0222015000, 0.0241544000, 0.0303931000, 0.0496628000, 0.1100583000, 0.3028661000, 0.9189129000", \ - "0.0220592000, 0.0239981000, 0.0302094000, 0.0494518000, 0.1100018000, 0.3028923000, 0.9244028000", \ - "0.0218224000, 0.0237731000, 0.0299566000, 0.0493260000, 0.1096749000, 0.3025119000, 0.9233273000", \ - "0.0217116000, 0.0234869000, 0.0297142000, 0.0487619000, 0.1092315000, 0.3008271000, 0.9243422000", \ - "0.0215443000, 0.0233946000, 0.0294358000, 0.0484112000, 0.1084514000, 0.3008764000, 0.9181804000", \ - "0.0230364000, 0.0248108000, 0.0305407000, 0.0489520000, 0.1083488000, 0.3004039000, 0.9226661000", \ - "0.0249862000, 0.0266607000, 0.0324804000, 0.0509590000, 0.1104343000, 0.3028834000, 0.9232268000"); - } - } - max_capacitance : 0.5612280000; - max_transition : 1.5123900000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016118800, 0.0051962900, 0.0167515000, 0.0540028000, 0.1740920000, 0.5612280000"); - values("0.1033063000, 0.1066731000, 0.1151227000, 0.1343826000, 0.1753918000, 0.2799389000, 0.6006557000", \ - "0.1084570000, 0.1117917000, 0.1203476000, 0.1395818000, 0.1805146000, 0.2850405000, 0.6055256000", \ - "0.1211782000, 0.1244793000, 0.1334734000, 0.1526797000, 0.1937010000, 0.2982015000, 0.6186466000", \ - "0.1526276000, 0.1559945000, 0.1646440000, 0.1836851000, 0.2248794000, 0.3292693000, 0.6504507000", \ - "0.2244431000, 0.2279846000, 0.2368191000, 0.2561077000, 0.2976850000, 0.4024615000, 0.7229223000", \ - "0.3438407000, 0.3483518000, 0.3599956000, 0.3847228000, 0.4322217000, 0.5388950000, 0.8605761000", \ - "0.5304358000, 0.5363137000, 0.5516937000, 0.5844639000, 0.6445210000, 0.7617060000, 1.0810598000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016118800, 0.0051962900, 0.0167515000, 0.0540028000, 0.1740920000, 0.5612280000"); - values("0.0716590000, 0.0752438000, 0.0849344000, 0.1099593000, 0.1808649000, 0.4047891000, 1.1215164000", \ - "0.0763630000, 0.0799324000, 0.0896053000, 0.1146095000, 0.1853259000, 0.4086105000, 1.1279410000", \ - "0.0875039000, 0.0910776000, 0.1007494000, 0.1258084000, 0.1968163000, 0.4196898000, 1.1396052000", \ - "0.1130382000, 0.1164395000, 0.1261740000, 0.1512323000, 0.2221358000, 0.4449059000, 1.1665179000", \ - "0.1533121000, 0.1576147000, 0.1683870000, 0.1946475000, 0.2658182000, 0.4885611000, 1.2060772000", \ - "0.2017864000, 0.2074067000, 0.2210664000, 0.2507004000, 0.3234487000, 0.5466355000, 1.2618463000", \ - "0.2433957000, 0.2508014000, 0.2694802000, 0.3080674000, 0.3864523000, 0.6084016000, 1.3232415000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016118800, 0.0051962900, 0.0167515000, 0.0540028000, 0.1740920000, 0.5612280000"); - values("0.0199814000, 0.0220302000, 0.0275210000, 0.0415439000, 0.0806252000, 0.2066597000, 0.6386869000", \ - "0.0199761000, 0.0221205000, 0.0274545000, 0.0413562000, 0.0807757000, 0.2065725000, 0.6364259000", \ - "0.0201105000, 0.0220996000, 0.0275774000, 0.0418800000, 0.0804895000, 0.2068652000, 0.6375794000", \ - "0.0200461000, 0.0220183000, 0.0276151000, 0.0417760000, 0.0806683000, 0.2071212000, 0.6333999000", \ - "0.0228421000, 0.0247955000, 0.0302302000, 0.0433868000, 0.0818280000, 0.2071985000, 0.6406692000", \ - "0.0343573000, 0.0370809000, 0.0431339000, 0.0569227000, 0.0926200000, 0.2119176000, 0.6396464000", \ - "0.0530288000, 0.0561621000, 0.0646432000, 0.0811796000, 0.1164011000, 0.2261130000, 0.6370017000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016118800, 0.0051962900, 0.0167515000, 0.0540028000, 0.1740920000, 0.5612280000"); - values("0.0180426000, 0.0210630000, 0.0302983000, 0.0591957000, 0.1559694000, 0.4765683000, 1.5057069000", \ - "0.0181188000, 0.0211893000, 0.0303639000, 0.0592243000, 0.1561384000, 0.4762130000, 1.5111720000", \ - "0.0181283000, 0.0211047000, 0.0303460000, 0.0592145000, 0.1562200000, 0.4762723000, 1.5057129000", \ - "0.0187293000, 0.0218962000, 0.0308559000, 0.0594536000, 0.1560576000, 0.4761896000, 1.5123900000", \ - "0.0245098000, 0.0271357000, 0.0356889000, 0.0626464000, 0.1566824000, 0.4751168000, 1.5006379000", \ - "0.0343299000, 0.0375858000, 0.0459286000, 0.0712919000, 0.1600246000, 0.4747910000, 1.5061080000", \ - "0.0491897000, 0.0536030000, 0.0650059000, 0.0893642000, 0.1692217000, 0.4772340000, 1.4982489000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_6") { - leakage_power () { - value : 0.0059433000; - when : "A"; - } - leakage_power () { - value : 0.0061571000; - when : "!A"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0060501820; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0046200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043800000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048590000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017047830, 0.0058125680, 0.0198183300, 0.0675718800, 0.2303907000, 0.7855322000"); - values("0.0410958000, 0.0394076000, 0.0335474000, 0.0137790000, -0.060156400, -0.322879300, -1.222024400", \ - "0.0407792000, 0.0390401000, 0.0332687000, 0.0135127000, -0.060484900, -0.323186100, -1.222363500", \ - "0.0402705000, 0.0386535000, 0.0327937000, 0.0129622000, -0.060995900, -0.323566900, -1.222733500", \ - "0.0400754000, 0.0385200000, 0.0324699000, 0.0124273000, -0.061502900, -0.323884600, -1.222882600", \ - "0.0399797000, 0.0380668000, 0.0318388000, 0.0115198000, -0.062351000, -0.324389800, -1.223039000", \ - "0.0439877000, 0.0419187000, 0.0351732000, 0.0141735000, -0.061384900, -0.322873800, -1.221288300", \ - "0.0509448000, 0.0485590000, 0.0411514000, 0.0181800000, -0.058425300, -0.320768500, -1.218104300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017047830, 0.0058125680, 0.0198183300, 0.0675718800, 0.2303907000, 0.7855322000"); - values("0.0309284000, 0.0331016000, 0.0404483000, 0.0644458000, 0.1421501000, 0.4040732000, 1.2876311000", \ - "0.0307060000, 0.0328894000, 0.0402369000, 0.0641599000, 0.1420706000, 0.4038353000, 1.2873082000", \ - "0.0303114000, 0.0324686000, 0.0397652000, 0.0635606000, 0.1414501000, 0.4013511000, 1.2862776000", \ - "0.0298117000, 0.0318938000, 0.0390987000, 0.0624620000, 0.1405548000, 0.4012079000, 1.2861280000", \ - "0.0302840000, 0.0322450000, 0.0389291000, 0.0621197000, 0.1394295000, 0.3998940000, 1.2859619000", \ - "0.0321492000, 0.0340933000, 0.0409488000, 0.0637567000, 0.1394336000, 0.4010440000, 1.2929148000", \ - "0.0355326000, 0.0373323000, 0.0438561000, 0.0663298000, 0.1429672000, 0.4034557000, 1.2896164000"); - } - } - max_capacitance : 0.7855320000; - max_transition : 1.5036720000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017047800, 0.0058125700, 0.0198183000, 0.0675719000, 0.2303910000, 0.7855320000"); - values("0.0866196000, 0.0889450000, 0.0954202000, 0.1110403000, 0.1470002000, 0.2440858000, 0.5612475000", \ - "0.0920289000, 0.0943130000, 0.1007752000, 0.1165350000, 0.1524297000, 0.2495327000, 0.5667647000", \ - "0.1052675000, 0.1075627000, 0.1139968000, 0.1295865000, 0.1655161000, 0.2625742000, 0.5797202000", \ - "0.1371043000, 0.1394536000, 0.1459464000, 0.1615588000, 0.1975687000, 0.2948051000, 0.6131079000", \ - "0.2058970000, 0.2084441000, 0.2155304000, 0.2321438000, 0.2691912000, 0.3665685000, 0.6822245000", \ - "0.3174095000, 0.3207223000, 0.3297536000, 0.3511192000, 0.3937737000, 0.4946175000, 0.8121505000", \ - "0.4964400000, 0.5007537000, 0.5124683000, 0.5405323000, 0.5949274000, 0.7043303000, 1.0186356000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017047800, 0.0058125700, 0.0198183000, 0.0675719000, 0.2303910000, 0.7855320000"); - values("0.0607531000, 0.0633961000, 0.0712457000, 0.0931469000, 0.1584737000, 0.3750356000, 1.1094687000", \ - "0.0653147000, 0.0679577000, 0.0757964000, 0.0976782000, 0.1629046000, 0.3794187000, 1.1161272000", \ - "0.0764469000, 0.0790886000, 0.0868781000, 0.1086514000, 0.1741652000, 0.3911227000, 1.1252476000", \ - "0.0992592000, 0.1019290000, 0.1098215000, 0.1318524000, 0.1970181000, 0.4140646000, 1.1494384000", \ - "0.1310743000, 0.1341438000, 0.1428467000, 0.1657268000, 0.2315333000, 0.4479207000, 1.1835268000", \ - "0.1647555000, 0.1687765000, 0.1798396000, 0.2055263000, 0.2723498000, 0.4886884000, 1.2229964000", \ - "0.1813885000, 0.1867587000, 0.2016069000, 0.2345243000, 0.3061421000, 0.5213365000, 1.2557148000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017047800, 0.0058125700, 0.0198183000, 0.0675719000, 0.2303910000, 0.7855320000"); - values("0.0168567000, 0.0183581000, 0.0225054000, 0.0345517000, 0.0693052000, 0.1892649000, 0.6185099000", \ - "0.0168007000, 0.0182716000, 0.0226377000, 0.0344061000, 0.0693940000, 0.1891767000, 0.6183432000", \ - "0.0168569000, 0.0182181000, 0.0226735000, 0.0342659000, 0.0694258000, 0.1894607000, 0.6194768000", \ - "0.0169351000, 0.0184136000, 0.0226505000, 0.0344229000, 0.0693196000, 0.1894837000, 0.6139492000", \ - "0.0211247000, 0.0226393000, 0.0264643000, 0.0374248000, 0.0709852000, 0.1898038000, 0.6161411000", \ - "0.0315710000, 0.0334424000, 0.0382497000, 0.0500632000, 0.0814117000, 0.1945696000, 0.6160023000", \ - "0.0484980000, 0.0503664000, 0.0570122000, 0.0715602000, 0.1031100000, 0.2064109000, 0.6181992000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017047800, 0.0058125700, 0.0198183000, 0.0675719000, 0.2303910000, 0.7855320000"); - values("0.0167216000, 0.0190790000, 0.0266142000, 0.0520083000, 0.1410429000, 0.4512884000, 1.4982426000", \ - "0.0167189000, 0.0190796000, 0.0266139000, 0.0520775000, 0.1411037000, 0.4510127000, 1.5033604000", \ - "0.0166962000, 0.0190120000, 0.0266381000, 0.0520079000, 0.1408869000, 0.4492311000, 1.5001498000", \ - "0.0179411000, 0.0201847000, 0.0276287000, 0.0524867000, 0.1411491000, 0.4513689000, 1.4988819000", \ - "0.0223945000, 0.0247663000, 0.0316450000, 0.0551652000, 0.1419787000, 0.4501069000, 1.4984118000", \ - "0.0315071000, 0.0337916000, 0.0410130000, 0.0626233000, 0.1445939000, 0.4492556000, 1.5036725000", \ - "0.0461165000, 0.0489115000, 0.0575499000, 0.0793419000, 0.1525300000, 0.4508870000, 1.4987658000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__buf_8") { - leakage_power () { - value : 0.0076474000; - when : "A"; - } - leakage_power () { - value : 0.0071930000; - when : "!A"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0074201990; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0070070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0066760000; - max_transition : 5.0000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0073370000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.0594648000, 0.0569737000, 0.0451290000, -0.012488100, -0.304828900, -1.673602300, -8.028393200", \ - "0.0589364000, 0.0562515000, 0.0444163000, -0.013240900, -0.305520300, -1.674224500, -8.028995100", \ - "0.0581356000, 0.0555284000, 0.0434447000, -0.014452600, -0.306389600, -1.675074000, -8.029740200", \ - "0.0584278000, 0.0556579000, 0.0430897000, -0.015692200, -0.307194800, -1.675310300, -8.030067200", \ - "0.0627816000, 0.0596428000, 0.0459259000, -0.016393900, -0.306569300, -1.674148000, -8.028590900", \ - "0.0743088000, 0.0706798000, 0.0558629000, -0.008329800, -0.301726400, -1.667720100, -8.022229700", \ - "0.1021201000, 0.0982151000, 0.0810371000, 0.0136848000, -0.278867000, -1.645589300, -7.999159600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0281726900, 0.0793700500, 0.2236068000, 0.6299605000, 1.7747680000, 5.0000000000"); - index_2("0.0005000000, 0.0023207940, 0.0107721700, 0.0500000000, 0.2320794000, 1.0772170000, 5.0000000000"); - values("0.0427107000, 0.0460135000, 0.0610513000, 0.1266503000, 0.4200511000, 1.7760417000, 8.0648437000", \ - "0.0421951000, 0.0455223000, 0.0605754000, 0.1261224000, 0.4191578000, 1.7668657000, 8.0626328000", \ - "0.0414089000, 0.0446402000, 0.0591473000, 0.1245859000, 0.4166932000, 1.7659490000, 8.0627551000", \ - "0.0408571000, 0.0440200000, 0.0584826000, 0.1222705000, 0.4152294000, 1.7661451000, 8.0523737000", \ - "0.0430943000, 0.0460533000, 0.0599271000, 0.1230448000, 0.4155668000, 1.7649929000, 8.0577062000", \ - "0.0501280000, 0.0528782000, 0.0663153000, 0.1296669000, 0.4206021000, 1.7696591000, 8.0617707000", \ - "0.0791212000, 0.0814390000, 0.0932837000, 0.1536334000, 0.4446522000, 1.7951581000, 8.0824963000"); - } - } - max_capacitance : 5.0000000000; - max_transition : 7.6522390000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0898758000, 0.0926007000, 0.1023709000, 0.1310611000, 0.2217777000, 0.6103413000, 2.4076046000", \ - "0.0972142000, 0.0999246000, 0.1096444000, 0.1382519000, 0.2290637000, 0.6170997000, 2.4183229000", \ - "0.1199870000, 0.1226775000, 0.1323263000, 0.1607603000, 0.2517571000, 0.6393114000, 2.4340354000", \ - "0.1861122000, 0.1888561000, 0.1986590000, 0.2274883000, 0.3185937000, 0.7064965000, 2.5103484000", \ - "0.3178306000, 0.3216539000, 0.3352763000, 0.3713545000, 0.4680375000, 0.8571459000, 2.6518570000", \ - "0.5573670000, 0.5625915000, 0.5813042000, 0.6318730000, 0.7458290000, 1.1346160000, 2.9290783000", \ - "1.0403164000, 1.0467943000, 1.0714550000, 1.1408591000, 1.2921527000, 1.6904512000, 3.4862067000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0612234000, 0.0643212000, 0.0764559000, 0.1219139000, 0.3173798000, 1.2234274000, 5.3912519000", \ - "0.0676434000, 0.0707376000, 0.0829084000, 0.1283858000, 0.3240240000, 1.2232362000, 5.4256497000", \ - "0.0859690000, 0.0890238000, 0.1009935000, 0.1463633000, 0.3417019000, 1.2410657000, 5.4493232000", \ - "0.1199811000, 0.1233260000, 0.1360820000, 0.1824243000, 0.3783367000, 1.2818745000, 5.4515108000", \ - "0.1592457000, 0.1637711000, 0.1797083000, 0.2278973000, 0.4239317000, 1.3241658000, 5.4973266000", \ - "0.1652575000, 0.1717478000, 0.1941631000, 0.2547364000, 0.4509668000, 1.3530214000, 5.5215943000", \ - "0.0161652000, 0.0246055000, 0.0567909000, 0.1439944000, 0.3571018000, 1.2588504000, 5.4248739000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0176236000, 0.0191398000, 0.0256832000, 0.0505653000, 0.1598651000, 0.6960770000, 3.1832885000", \ - "0.0174651000, 0.0192454000, 0.0258406000, 0.0505902000, 0.1599342000, 0.6935716000, 3.1895941000", \ - "0.0176052000, 0.0191666000, 0.0257988000, 0.0505520000, 0.1597837000, 0.6934592000, 3.1853375000", \ - "0.0194796000, 0.0210842000, 0.0273309000, 0.0515301000, 0.1601077000, 0.6928711000, 3.1936236000", \ - "0.0322104000, 0.0339113000, 0.0413675000, 0.0636939000, 0.1657876000, 0.6944166000, 3.1828833000", \ - "0.0541379000, 0.0565577000, 0.0668154000, 0.0937494000, 0.1853528000, 0.6973335000, 3.1897851000", \ - "0.0914298000, 0.0943024000, 0.1068330000, 0.1424247000, 0.2337197000, 0.7069229000, 3.2030785000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0281727000, 0.0793701000, 0.2236070000, 0.6299610000, 1.7747700000, 5.0000000000"); - index_2("0.0005000000, 0.0023207900, 0.0107722000, 0.0500000000, 0.2320790000, 1.0772200000, 5.0000000000"); - values("0.0172973000, 0.0200772000, 0.0325186000, 0.0909194000, 0.3695902000, 1.6673350000, 7.6423667000", \ - "0.0172754000, 0.0200440000, 0.0325830000, 0.0909815000, 0.3701521000, 1.6571479000, 7.6522388000", \ - "0.0174418000, 0.0201777000, 0.0327355000, 0.0910592000, 0.3697503000, 1.6607066000, 7.6499953000", \ - "0.0212271000, 0.0239302000, 0.0357275000, 0.0922210000, 0.3689166000, 1.6622439000, 7.6486346000", \ - "0.0315809000, 0.0342105000, 0.0448285000, 0.0964010000, 0.3705766000, 1.6651750000, 7.6519324000", \ - "0.0500362000, 0.0540572000, 0.0683488000, 0.1137048000, 0.3724115000, 1.6607993000, 7.6407058000", \ - "0.0834987000, 0.0889313000, 0.1085243000, 0.1634299000, 0.3866372000, 1.6719754000, 7.6396258000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__bufbuf_16") { - leakage_power () { - value : 0.0239328000; - when : "A"; - } - leakage_power () { - value : 0.0149801000; - when : "!A"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0194564300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022280000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024260000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018976120, 0.0072018610, 0.0273326700, 0.1037336000, 0.3936923000, 1.4941500000"); - values("0.1474101000, 0.1454249000, 0.1376606000, 0.1084471000, -0.007331500, -0.473891700, -2.255758200", \ - "0.1469807000, 0.1449954000, 0.1375156000, 0.1082541000, -0.007473100, -0.473927400, -2.255953300", \ - "0.1469086000, 0.1448649000, 0.1372384000, 0.1078675000, -0.007891400, -0.474385200, -2.256254100", \ - "0.1466315000, 0.1446513000, 0.1369158000, 0.1075812000, -0.008099700, -0.474678600, -2.256488300", \ - "0.1457827000, 0.1437857000, 0.1362698000, 0.1069393000, -0.008778100, -0.475323300, -2.257129900", \ - "0.1459637000, 0.1439409000, 0.1362808000, 0.1071274000, -0.008640000, -0.475098000, -2.256979600", \ - "0.1544240000, 0.1522195000, 0.1443727000, 0.1140021000, -0.005838900, -0.473347500, -2.255301500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018976120, 0.0072018610, 0.0273326700, 0.1037336000, 0.3936923000, 1.4941500000"); - values("0.1495313000, 0.1520217000, 0.1614888000, 0.1960418000, 0.3210555000, 0.7859663000, 2.5473034000", \ - "0.1493993000, 0.1518865000, 0.1612410000, 0.1958408000, 0.3209616000, 0.7862374000, 2.5507304000", \ - "0.1490077000, 0.1514989000, 0.1608586000, 0.1954886000, 0.3206630000, 0.7859705000, 2.5482003000", \ - "0.1484344000, 0.1509238000, 0.1602831000, 0.1949207000, 0.3201069000, 0.7854349000, 2.5476102000", \ - "0.1479547000, 0.1504256000, 0.1596407000, 0.1942405000, 0.3191846000, 0.7840812000, 2.5479596000", \ - "0.1496598000, 0.1520351000, 0.1609988000, 0.1946844000, 0.3201318000, 0.7841330000, 2.5473828000", \ - "0.1518713000, 0.1542938000, 0.1633180000, 0.1975048000, 0.3231260000, 0.7873442000, 2.5422669000"); - } - } - max_capacitance : 1.4941500000; - max_transition : 1.5046560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018976100, 0.0072018600, 0.0273327000, 0.1037340000, 0.3936920000, 1.4941500000"); - values("0.2313378000, 0.2327983000, 0.2376243000, 0.2518812000, 0.2882345000, 0.3889778000, 0.7385356000", \ - "0.2364090000, 0.2378139000, 0.2426585000, 0.2570172000, 0.2932805000, 0.3941125000, 0.7438285000", \ - "0.2492266000, 0.2506430000, 0.2555318000, 0.2696920000, 0.3061902000, 0.4071641000, 0.7566485000", \ - "0.2792145000, 0.2806784000, 0.2855113000, 0.2997604000, 0.3361211000, 0.4368836000, 0.7865295000", \ - "0.3445286000, 0.3459369000, 0.3507604000, 0.3650124000, 0.4012688000, 0.5021324000, 0.8518321000", \ - "0.4488483000, 0.4502567000, 0.4550974000, 0.4692646000, 0.5057129000, 0.6063743000, 0.9559399000", \ - "0.6028557000, 0.6041662000, 0.6090033000, 0.6231710000, 0.6595744000, 0.7605003000, 1.1102111000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018976100, 0.0072018600, 0.0273327000, 0.1037340000, 0.3936920000, 1.4941500000"); - values("0.2093312000, 0.2110150000, 0.2168923000, 0.2351989000, 0.2912958000, 0.4876797000, 1.2264619000", \ - "0.2140891000, 0.2157667000, 0.2216443000, 0.2399657000, 0.2961085000, 0.4923698000, 1.2336416000", \ - "0.2253998000, 0.2270803000, 0.2329606000, 0.2512694000, 0.3073953000, 0.5037526000, 1.2449553000", \ - "0.2509577000, 0.2526387000, 0.2585185000, 0.2768283000, 0.3329456000, 0.5293386000, 1.2704503000", \ - "0.2940475000, 0.2957211000, 0.3015500000, 0.3198324000, 0.3758668000, 0.5728715000, 1.3126759000", \ - "0.3534062000, 0.3550784000, 0.3609299000, 0.3792586000, 0.4354436000, 0.6313116000, 1.3723520000", \ - "0.4274704000, 0.4291436000, 0.4349738000, 0.4532870000, 0.5094507000, 0.7058774000, 1.4439825000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018976100, 0.0072018600, 0.0273327000, 0.1037340000, 0.3936920000, 1.4941500000"); - values("0.0236894000, 0.0247142000, 0.0278469000, 0.0384577000, 0.0753844000, 0.2125321000, 0.7508694000", \ - "0.0237568000, 0.0246937000, 0.0278676000, 0.0385902000, 0.0754373000, 0.2124043000, 0.7500288000", \ - "0.0237927000, 0.0246833000, 0.0278534000, 0.0385808000, 0.0753530000, 0.2125150000, 0.7505235000", \ - "0.0237309000, 0.0247020000, 0.0278556000, 0.0387332000, 0.0753937000, 0.2125325000, 0.7512004000", \ - "0.0236238000, 0.0245528000, 0.0278648000, 0.0385974000, 0.0754468000, 0.2123832000, 0.7501548000", \ - "0.0237962000, 0.0247230000, 0.0279207000, 0.0385236000, 0.0753646000, 0.2122799000, 0.7495283000", \ - "0.0239330000, 0.0247262000, 0.0280481000, 0.0386180000, 0.0755388000, 0.2124390000, 0.7495301000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018976100, 0.0072018600, 0.0273327000, 0.1037340000, 0.3936920000, 1.4941500000"); - values("0.0251537000, 0.0265845000, 0.0319589000, 0.0515040000, 0.1247369000, 0.4109753000, 1.5035586000", \ - "0.0251441000, 0.0265886000, 0.0319735000, 0.0514637000, 0.1250828000, 0.4109833000, 1.5039944000", \ - "0.0251519000, 0.0265894000, 0.0319699000, 0.0514914000, 0.1249494000, 0.4110821000, 1.5017790000", \ - "0.0251522000, 0.0265890000, 0.0319710000, 0.0514941000, 0.1249038000, 0.4111081000, 1.5012412000", \ - "0.0250835000, 0.0265571000, 0.0319082000, 0.0514833000, 0.1250697000, 0.4110852000, 1.5025603000", \ - "0.0251675000, 0.0266334000, 0.0320330000, 0.0515147000, 0.1251340000, 0.4097112000, 1.5046560000", \ - "0.0252310000, 0.0266633000, 0.0320507000, 0.0515292000, 0.1250823000, 0.4110347000, 1.4997297000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__bufbuf_8") { - leakage_power () { - value : 0.0099004000; - when : "A"; - } - leakage_power () { - value : 0.0129496000; - when : "!A"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0114249900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0017490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016680000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018300000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017569250, 0.0061735690, 0.0216929900, 0.0762259100, 0.2678464000, 0.9411718000"); - values("0.0727515000, 0.0708474000, 0.0646167000, 0.0424549000, -0.041114500, -0.350095700, -1.440605800", \ - "0.0725248000, 0.0706861000, 0.0644508000, 0.0422830000, -0.041216800, -0.350232800, -1.440711400", \ - "0.0723437000, 0.0705028000, 0.0642118000, 0.0421412000, -0.041423100, -0.350407800, -1.440923900", \ - "0.0722325000, 0.0704376000, 0.0641021000, 0.0419456000, -0.041548500, -0.350545000, -1.441192000", \ - "0.0720627000, 0.0702781000, 0.0638251000, 0.0417239000, -0.041778000, -0.350752900, -1.441252300", \ - "0.0718775000, 0.0701083000, 0.0637610000, 0.0416369000, -0.041772700, -0.350620900, -1.441130200", \ - "0.0775048000, 0.0756534000, 0.0691491000, 0.0455848000, -0.040494200, -0.349729400, -1.440143800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017569250, 0.0061735690, 0.0216929900, 0.0762259100, 0.2678464000, 0.9411718000"); - values("0.0738684000, 0.0761396000, 0.0839665000, 0.1101961000, 0.1992261000, 0.5063747000, 1.5865196000", \ - "0.0737092000, 0.0759427000, 0.0835598000, 0.1099101000, 0.1989303000, 0.5064782000, 1.5867404000", \ - "0.0735136000, 0.0757257000, 0.0835772000, 0.1097362000, 0.1987894000, 0.5056960000, 1.5860782000", \ - "0.0732252000, 0.0754318000, 0.0832730000, 0.1093970000, 0.1984439000, 0.5055548000, 1.5854233000", \ - "0.0728537000, 0.0751149000, 0.0829407000, 0.1093574000, 0.1982462000, 0.5054227000, 1.5786973000", \ - "0.0741746000, 0.0763539000, 0.0839697000, 0.1098292000, 0.1985952000, 0.5051759000, 1.5856453000", \ - "0.0751846000, 0.0774340000, 0.0848974000, 0.1108789000, 0.2005960000, 0.5075553000, 1.5821130000"); - } - } - max_capacitance : 0.9411720000; - max_transition : 1.5078310000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017569200, 0.0061735700, 0.0216930000, 0.0762259000, 0.2678460000, 0.9411720000"); - values("0.2141982000, 0.2162146000, 0.2221122000, 0.2373713000, 0.2734660000, 0.3713289000, 0.6980782000", \ - "0.2192626000, 0.2212116000, 0.2271486000, 0.2423382000, 0.2784238000, 0.3763581000, 0.7023069000", \ - "0.2321627000, 0.2341179000, 0.2400252000, 0.2552556000, 0.2912857000, 0.3891792000, 0.7149307000", \ - "0.2633625000, 0.2653575000, 0.2712550000, 0.2864770000, 0.3226062000, 0.4204098000, 0.7461811000", \ - "0.3254086000, 0.3273578000, 0.3332901000, 0.3484629000, 0.3845385000, 0.4824547000, 0.8084429000", \ - "0.4231850000, 0.4251879000, 0.4310712000, 0.4462963000, 0.4823389000, 0.5802440000, 0.9070406000", \ - "0.5745908000, 0.5765496000, 0.5824510000, 0.5976581000, 0.6337210000, 0.7316516000, 1.0565442000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017569200, 0.0061735700, 0.0216930000, 0.0762259000, 0.2678460000, 0.9411720000"); - values("0.2016824000, 0.2039658000, 0.2110887000, 0.2316601000, 0.2943241000, 0.5058314000, 1.2468719000", \ - "0.2063083000, 0.2085904000, 0.2156493000, 0.2362832000, 0.2988717000, 0.5098661000, 1.2526090000", \ - "0.2175453000, 0.2198435000, 0.2269441000, 0.2474806000, 0.3100996000, 0.5215748000, 1.2621486000", \ - "0.2401972000, 0.2424847000, 0.2495837000, 0.2701046000, 0.3327125000, 0.5440791000, 1.2855010000", \ - "0.2735165000, 0.2758117000, 0.2829253000, 0.3035711000, 0.3661646000, 0.5774453000, 1.3184689000", \ - "0.3155085000, 0.3177876000, 0.3249139000, 0.3455727000, 0.4082210000, 0.6192839000, 1.3635250000", \ - "0.3594220000, 0.3617098000, 0.3688172000, 0.3893588000, 0.4519666000, 0.6632265000, 1.4015875000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017569200, 0.0061735700, 0.0216930000, 0.0762259000, 0.2678460000, 0.9411720000"); - values("0.0195565000, 0.0206287000, 0.0245086000, 0.0360785000, 0.0714827000, 0.1960545000, 0.6536692000", \ - "0.0193121000, 0.0205648000, 0.0246504000, 0.0359459000, 0.0713573000, 0.1959872000, 0.6537353000", \ - "0.0195422000, 0.0207861000, 0.0245483000, 0.0359071000, 0.0714040000, 0.1960593000, 0.6525023000", \ - "0.0195541000, 0.0206393000, 0.0244901000, 0.0361055000, 0.0713206000, 0.1960286000, 0.6536122000", \ - "0.0193131000, 0.0205629000, 0.0245137000, 0.0359544000, 0.0713677000, 0.1960536000, 0.6536466000", \ - "0.0193625000, 0.0206145000, 0.0246819000, 0.0359592000, 0.0713932000, 0.1960067000, 0.6536972000", \ - "0.0196647000, 0.0209251000, 0.0246998000, 0.0360385000, 0.0715058000, 0.1961007000, 0.6537154000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017569200, 0.0061735700, 0.0216930000, 0.0762259000, 0.2678460000, 0.9411720000"); - values("0.0203702000, 0.0223586000, 0.0290474000, 0.0522239000, 0.1364620000, 0.4385152000, 1.5059857000", \ - "0.0204234000, 0.0223338000, 0.0290977000, 0.0522987000, 0.1364443000, 0.4381689000, 1.5078307000", \ - "0.0203694000, 0.0222895000, 0.0290732000, 0.0522715000, 0.1363736000, 0.4383329000, 1.5046806000", \ - "0.0203198000, 0.0222860000, 0.0290867000, 0.0522842000, 0.1363076000, 0.4387007000, 1.5064121000", \ - "0.0204211000, 0.0223546000, 0.0290685000, 0.0522940000, 0.1364477000, 0.4388442000, 1.5042654000", \ - "0.0204434000, 0.0224666000, 0.0291530000, 0.0523469000, 0.1363593000, 0.4372029000, 1.5061806000", \ - "0.0204632000, 0.0223799000, 0.0291665000, 0.0523059000, 0.1363496000, 0.4388541000, 1.5019410000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__bufinv_16") { - leakage_power () { - value : 0.0147876000; - when : "A"; - } - leakage_power () { - value : 0.0134796000; - when : "!A"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0141336100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0067840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0064130000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0071560000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019008920, 0.0072267810, 0.0274746600, 0.1044527000, 0.3971067000, 1.5097140000"); - values("0.1169168000, 0.1150397000, 0.1075233000, 0.0783250000, -0.038067500, -0.508996700, -2.310632600", \ - "0.1167468000, 0.1147055000, 0.1071288000, 0.0778406000, -0.038444300, -0.509512300, -2.311027200", \ - "0.1159736000, 0.1139395000, 0.1063267000, 0.0770466000, -0.039228300, -0.510251600, -2.311786400", \ - "0.1146726000, 0.1126598000, 0.1049301000, 0.0756342000, -0.040627200, -0.511432400, -2.313020700", \ - "0.1134151000, 0.1116410000, 0.1039796000, 0.0746515000, -0.041799000, -0.512471000, -2.313950700", \ - "0.1212090000, 0.1191051000, 0.1112122000, 0.0805782000, -0.040462900, -0.511780500, -2.313185900", \ - "0.1259766000, 0.1238221000, 0.1157544000, 0.0848309000, -0.036160600, -0.506842000, -2.308789500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019008920, 0.0072267810, 0.0274746600, 0.1044527000, 0.3971067000, 1.5097140000"); - values("0.1514875000, 0.1539432000, 0.1635882000, 0.1985556000, 0.3247483000, 0.7945191000, 2.5750685000", \ - "0.1508743000, 0.1533433000, 0.1627982000, 0.1978043000, 0.3240816000, 0.7936628000, 2.5756527000", \ - "0.1501264000, 0.1526149000, 0.1619618000, 0.1969649000, 0.3232998000, 0.7933581000, 2.5739219000", \ - "0.1493960000, 0.1518880000, 0.1612431000, 0.1962150000, 0.3225448000, 0.7925891000, 2.5726560000", \ - "0.1483345000, 0.1507986000, 0.1601883000, 0.1950350000, 0.3213873000, 0.7915378000, 2.5729938000", \ - "0.1484691000, 0.1510342000, 0.1605748000, 0.1953469000, 0.3225422000, 0.7920656000, 2.5709438000", \ - "0.1554502000, 0.1578221000, 0.1667929000, 0.1998792000, 0.3266747000, 0.7980409000, 2.5752429000"); - } - } - max_capacitance : 1.5097140000; - max_transition : 1.5031750000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019008900, 0.0072267800, 0.0274747000, 0.1044530000, 0.3971070000, 1.5097100000"); - values("0.1434932000, 0.1448749000, 0.1496160000, 0.1636005000, 0.1992372000, 0.2988925000, 0.6467082000", \ - "0.1479537000, 0.1493451000, 0.1541451000, 0.1680488000, 0.2038874000, 0.3034095000, 0.6508137000", \ - "0.1586367000, 0.1600275000, 0.1648199000, 0.1787148000, 0.2145586000, 0.3140552000, 0.6614503000", \ - "0.1795081000, 0.1808928000, 0.1856634000, 0.1995520000, 0.2353640000, 0.3349298000, 0.6828118000", \ - "0.2072771000, 0.2087144000, 0.2134474000, 0.2273530000, 0.2631621000, 0.3630007000, 0.7104522000", \ - "0.2368432000, 0.2382202000, 0.2429590000, 0.2568425000, 0.2926999000, 0.3925581000, 0.7403166000", \ - "0.2503754000, 0.2517775000, 0.2565860000, 0.2706368000, 0.3065716000, 0.4068145000, 0.7541687000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019008900, 0.0072267800, 0.0274747000, 0.1044530000, 0.3971070000, 1.5097100000"); - values("0.1546277000, 0.1562714000, 0.1620191000, 0.1800902000, 0.2359886000, 0.4315537000, 1.1693518000", \ - "0.1597651000, 0.1614102000, 0.1671131000, 0.1851766000, 0.2409178000, 0.4370116000, 1.1761861000", \ - "0.1726963000, 0.1743352000, 0.1800738000, 0.1981724000, 0.2539806000, 0.4497548000, 1.1888178000", \ - "0.2043324000, 0.2059702000, 0.2117122000, 0.2297938000, 0.2855933000, 0.4813741000, 1.2211164000", \ - "0.2739785000, 0.2756233000, 0.2813538000, 0.2994074000, 0.3553101000, 0.5511070000, 1.2952056000", \ - "0.3912753000, 0.3929458000, 0.3987149000, 0.4169057000, 0.4729044000, 0.6690968000, 1.4150940000", \ - "0.5835194000, 0.5852515000, 0.5912424000, 0.6097382000, 0.6662145000, 0.8628099000, 1.6002981000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019008900, 0.0072267800, 0.0274747000, 0.1044530000, 0.3971070000, 1.5097100000"); - values("0.0228727000, 0.0237796000, 0.0270337000, 0.0375715000, 0.0739485000, 0.2098561000, 0.7469478000", \ - "0.0230434000, 0.0239232000, 0.0270223000, 0.0375794000, 0.0739709000, 0.2103211000, 0.7474734000", \ - "0.0230265000, 0.0239096000, 0.0270182000, 0.0375859000, 0.0739769000, 0.2103198000, 0.7473470000", \ - "0.0230209000, 0.0239125000, 0.0270230000, 0.0375658000, 0.0740469000, 0.2099313000, 0.7469361000", \ - "0.0232563000, 0.0241464000, 0.0271964000, 0.0376177000, 0.0739249000, 0.2100619000, 0.7474903000", \ - "0.0233042000, 0.0242256000, 0.0274327000, 0.0379143000, 0.0742598000, 0.2099563000, 0.7463060000", \ - "0.0240932000, 0.0249507000, 0.0280847000, 0.0386427000, 0.0747058000, 0.2107375000, 0.7481522000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019008900, 0.0072267800, 0.0274747000, 0.1044530000, 0.3971070000, 1.5097100000"); - values("0.0243931000, 0.0258417000, 0.0309859000, 0.0504961000, 0.1238284000, 0.4086661000, 1.5028350000", \ - "0.0244003000, 0.0257831000, 0.0310437000, 0.0503360000, 0.1238434000, 0.4100495000, 1.5002816000", \ - "0.0243190000, 0.0257681000, 0.0310201000, 0.0504680000, 0.1239478000, 0.4097899000, 1.5024031000", \ - "0.0243481000, 0.0257872000, 0.0310553000, 0.0504675000, 0.1239573000, 0.4097472000, 1.4986676000", \ - "0.0245024000, 0.0259005000, 0.0311948000, 0.0504994000, 0.1238808000, 0.4085469000, 1.5012902000", \ - "0.0253430000, 0.0267441000, 0.0319465000, 0.0513921000, 0.1242503000, 0.4083729000, 1.5031753000", \ - "0.0277708000, 0.0291111000, 0.0341969000, 0.0531345000, 0.1254565000, 0.4096794000, 1.4978019000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__bufinv_8") { - leakage_power () { - value : 0.0176473000; - when : "A"; - } - leakage_power () { - value : 0.0078400000; - when : "!A"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0127436300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022300000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024260000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017572090, 0.0061755700, 0.0217035400, 0.0762753300, 0.2680635000, 0.9420873000"); - values("0.0605045000, 0.0585868000, 0.0524069000, 0.0303620000, -0.053099900, -0.362327400, -1.454011000", \ - "0.0602131000, 0.0584498000, 0.0522095000, 0.0302378000, -0.053301600, -0.362502800, -1.454094200", \ - "0.0597741000, 0.0580176000, 0.0519105000, 0.0298112000, -0.053711700, -0.362861100, -1.454482800", \ - "0.0593956000, 0.0575615000, 0.0513115000, 0.0292142000, -0.054294100, -0.363496800, -1.455091500", \ - "0.0588665000, 0.0570661000, 0.0506467000, 0.0286324000, -0.054988300, -0.363869600, -1.455345500", \ - "0.0639777000, 0.0620812000, 0.0554933000, 0.0318284000, -0.054536700, -0.363661100, -1.455015700", \ - "0.0656695000, 0.0637616000, 0.0569970000, 0.0336224000, -0.052613600, -0.361521000, -1.453075200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017572090, 0.0061755700, 0.0217035400, 0.0762753300, 0.2680635000, 0.9420873000"); - values("0.0756781000, 0.0777910000, 0.0855769000, 0.1119959000, 0.2012092000, 0.5090853000, 1.5894876000", \ - "0.0755230000, 0.0777998000, 0.0855367000, 0.1119222000, 0.2012161000, 0.5092959000, 1.5911492000", \ - "0.0751178000, 0.0774658000, 0.0852705000, 0.1115186000, 0.2006384000, 0.5085648000, 1.5891162000", \ - "0.0747841000, 0.0770083000, 0.0848035000, 0.1114047000, 0.2004461000, 0.5083822000, 1.5818052000", \ - "0.0742928000, 0.0765259000, 0.0843149000, 0.1106651000, 0.1996640000, 0.5080593000, 1.5815580000", \ - "0.0751483000, 0.0772702000, 0.0847237000, 0.1101909000, 0.1999272000, 0.5071854000, 1.5890629000", \ - "0.0776645000, 0.0797616000, 0.0869863000, 0.1129644000, 0.2016860000, 0.5108139000, 1.5874697000"); - } - } - max_capacitance : 0.9420870000; - max_transition : 1.5104440000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017572100, 0.0061755700, 0.0217035000, 0.0762753000, 0.2680630000, 0.9420870000"); - values("0.1448033000, 0.1468072000, 0.1526641000, 0.1678096000, 0.2037530000, 0.3011045000, 0.6259931000", \ - "0.1495941000, 0.1515928000, 0.1574465000, 0.1726041000, 0.2084577000, 0.3059508000, 0.6309611000", \ - "0.1608937000, 0.1628302000, 0.1687457000, 0.1838826000, 0.2197359000, 0.3172307000, 0.6419469000", \ - "0.1864299000, 0.1883993000, 0.1942391000, 0.2093553000, 0.2452855000, 0.3425783000, 0.6676649000", \ - "0.2293508000, 0.2312655000, 0.2371169000, 0.2521361000, 0.2881131000, 0.3852400000, 0.7110862000", \ - "0.2882087000, 0.2901564000, 0.2960449000, 0.3112067000, 0.3472681000, 0.4450601000, 0.7692239000", \ - "0.3611814000, 0.3632098000, 0.3692766000, 0.3850280000, 0.4215387000, 0.5193048000, 0.8438634000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017572100, 0.0061755700, 0.0217035000, 0.0762753000, 0.2680630000, 0.9420870000"); - values("0.1495999000, 0.1518023000, 0.1588123000, 0.1792849000, 0.2416144000, 0.4528161000, 1.1914473000", \ - "0.1547314000, 0.1569710000, 0.1639839000, 0.1844059000, 0.2469104000, 0.4584221000, 1.1976800000", \ - "0.1674652000, 0.1697079000, 0.1767766000, 0.1972023000, 0.2596517000, 0.4705228000, 1.2111618000", \ - "0.1974532000, 0.1996927000, 0.2067057000, 0.2272194000, 0.2897496000, 0.5003760000, 1.2384641000", \ - "0.2628192000, 0.2650665000, 0.2721109000, 0.2925393000, 0.3548252000, 0.5662707000, 1.3035355000", \ - "0.3670699000, 0.3693765000, 0.3765857000, 0.3971931000, 0.4597873000, 0.6709516000, 1.4106634000", \ - "0.5213635000, 0.5239269000, 0.5316720000, 0.5529589000, 0.6158216000, 0.8266634000, 1.5645021000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017572100, 0.0061755700, 0.0217035000, 0.0762753000, 0.2680630000, 0.9420870000"); - values("0.0196088000, 0.0207949000, 0.0245825000, 0.0360959000, 0.0711881000, 0.1956703000, 0.6518628000", \ - "0.0196171000, 0.0209033000, 0.0246026000, 0.0359333000, 0.0713016000, 0.1955193000, 0.6521276000", \ - "0.0195243000, 0.0207767000, 0.0247036000, 0.0360260000, 0.0713101000, 0.1953895000, 0.6529624000", \ - "0.0196945000, 0.0209961000, 0.0245794000, 0.0360974000, 0.0713305000, 0.1952559000, 0.6520269000", \ - "0.0196457000, 0.0208794000, 0.0246513000, 0.0359075000, 0.0715654000, 0.1956923000, 0.6528882000", \ - "0.0202016000, 0.0213901000, 0.0253940000, 0.0366533000, 0.0716841000, 0.1956330000, 0.6528468000", \ - "0.0218565000, 0.0230849000, 0.0271029000, 0.0382471000, 0.0728538000, 0.1960461000, 0.6523136000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017572100, 0.0061755700, 0.0217035000, 0.0762753000, 0.2680630000, 0.9420870000"); - values("0.0201127000, 0.0221324000, 0.0288566000, 0.0520388000, 0.1362632000, 0.4390025000, 1.5075663000", \ - "0.0200929000, 0.0220666000, 0.0288457000, 0.0521273000, 0.1362603000, 0.4391270000, 1.5035692000", \ - "0.0201572000, 0.0220703000, 0.0287556000, 0.0520263000, 0.1363034000, 0.4379790000, 1.5029713000", \ - "0.0201677000, 0.0221524000, 0.0288510000, 0.0520751000, 0.1359941000, 0.4386833000, 1.5042130000", \ - "0.0204221000, 0.0223771000, 0.0290488000, 0.0521905000, 0.1362757000, 0.4395613000, 1.5016447000", \ - "0.0218646000, 0.0237126000, 0.0303048000, 0.0530673000, 0.1366368000, 0.4379845000, 1.5104439000", \ - "0.0255676000, 0.0273337000, 0.0337399000, 0.0553200000, 0.1376852000, 0.4382422000, 1.5006942000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkbuf_1") { - leakage_power () { - value : 0.0011810000; - when : "A"; - } - leakage_power () { - value : 0.0011810000; - when : "!A"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__clkbuf"; - cell_leakage_power : 0.0011810180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0020980000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020100000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0021860000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0107832000, 0.0097595000, 0.0069169000, -0.000834000, -0.020750900, -0.071137900, -0.198390100", \ - "0.0105264000, 0.0095202000, 0.0066742000, -0.001057500, -0.020928000, -0.071347800, -0.198597500", \ - "0.0103060000, 0.0092806000, 0.0064532000, -0.001263100, -0.021149700, -0.071480700, -0.198762800", \ - "0.0101860000, 0.0091515000, 0.0063249000, -0.001355700, -0.021170300, -0.071528400, -0.198768500", \ - "0.0100386000, 0.0088481000, 0.0061443000, -0.001328000, -0.021123600, -0.071421900, -0.198647000", \ - "0.0109359000, 0.0097542000, 0.0068615000, -0.001047200, -0.020509400, -0.070800500, -0.198015200", \ - "0.0130013000, 0.0117639000, 0.0085483000, 0.0007093000, -0.019010000, -0.069249600, -0.196285900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0055347000, 0.0068431000, 0.0100390000, 0.0178493000, 0.0375527000, 0.0871147000, 0.2126276000", \ - "0.0053434000, 0.0066540000, 0.0098449000, 0.0176825000, 0.0373994000, 0.0870575000, 0.2132792000", \ - "0.0050721000, 0.0063608000, 0.0095416000, 0.0174493000, 0.0372151000, 0.0875248000, 0.2141309000", \ - "0.0048470000, 0.0061317000, 0.0092979000, 0.0171627000, 0.0372362000, 0.0869569000, 0.2124959000", \ - "0.0049506000, 0.0062250000, 0.0092704000, 0.0171337000, 0.0368971000, 0.0872933000, 0.2136015000", \ - "0.0056127000, 0.0068693000, 0.0099280000, 0.0177502000, 0.0375374000, 0.0874596000, 0.2136300000", \ - "0.0076314000, 0.0087447000, 0.0118640000, 0.0196892000, 0.0394029000, 0.0892978000, 0.2147705000"); - } - } - max_capacitance : 0.1300150000; - max_transition : 1.5064550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0592259000, 0.0642513000, 0.0748942000, 0.0972813000, 0.1492422000, 0.2788013000, 0.6062921000", \ - "0.0641555000, 0.0691985000, 0.0798142000, 0.1024084000, 0.1544307000, 0.2842055000, 0.6107023000", \ - "0.0774288000, 0.0824930000, 0.0931572000, 0.1156574000, 0.1676275000, 0.2972603000, 0.6246369000", \ - "0.1076586000, 0.1128278000, 0.1236900000, 0.1464433000, 0.1985064000, 0.3280456000, 0.6565997000", \ - "0.1577475000, 0.1639106000, 0.1762243000, 0.2007543000, 0.2541695000, 0.3827842000, 0.7110144000", \ - "0.2340805000, 0.2421729000, 0.2575544000, 0.2849163000, 0.3397340000, 0.4699444000, 0.7970801000", \ - "0.3556399000, 0.3660085000, 0.3857001000, 0.4195785000, 0.4791168000, 0.6102937000, 0.9385269000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0489976000, 0.0557706000, 0.0716849000, 0.1103869000, 0.2074964000, 0.4513024000, 1.0688679000", \ - "0.0535470000, 0.0602856000, 0.0762179000, 0.1149403000, 0.2115812000, 0.4563649000, 1.0788538000", \ - "0.0641421000, 0.0708147000, 0.0865609000, 0.1254701000, 0.2225740000, 0.4687161000, 1.0898558000", \ - "0.0818408000, 0.0887571000, 0.1049198000, 0.1439399000, 0.2420734000, 0.4882801000, 1.1062276000", \ - "0.1040857000, 0.1114389000, 0.1279342000, 0.1669223000, 0.2645230000, 0.5100902000, 1.1276735000", \ - "0.1257715000, 0.1347576000, 0.1522623000, 0.1914677000, 0.2897410000, 0.5344319000, 1.1532661000", \ - "0.1290849000, 0.1411185000, 0.1636020000, 0.2059111000, 0.3023249000, 0.5483574000, 1.1669063000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0148634000, 0.0193017000, 0.0295383000, 0.0550680000, 0.1222172000, 0.2948546000, 0.7301220000", \ - "0.0149530000, 0.0192939000, 0.0296532000, 0.0550493000, 0.1216939000, 0.2943367000, 0.7298736000", \ - "0.0148764000, 0.0193230000, 0.0296409000, 0.0552154000, 0.1215747000, 0.2964073000, 0.7262715000", \ - "0.0160559000, 0.0203036000, 0.0303508000, 0.0553759000, 0.1214418000, 0.2930896000, 0.7303547000", \ - "0.0210718000, 0.0251900000, 0.0349878000, 0.0592648000, 0.1229421000, 0.2944478000, 0.7275211000", \ - "0.0301798000, 0.0347785000, 0.0445136000, 0.0668789000, 0.1277532000, 0.2945307000, 0.7338570000", \ - "0.0437432000, 0.0497079000, 0.0604185000, 0.0823395000, 0.1375341000, 0.2987351000, 0.7282525000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0199727000, 0.0284057000, 0.0500754000, 0.1054724000, 0.2464573000, 0.6007445000, 1.4984419000", \ - "0.0200327000, 0.0284043000, 0.0500627000, 0.1055465000, 0.2466837000, 0.6009164000, 1.4987117000", \ - "0.0201306000, 0.0285084000, 0.0500400000, 0.1054141000, 0.2466287000, 0.6049375000, 1.5064545000", \ - "0.0215448000, 0.0297059000, 0.0507580000, 0.1055325000, 0.2474657000, 0.6046492000, 1.4979125000", \ - "0.0249366000, 0.0323243000, 0.0523305000, 0.1063798000, 0.2454741000, 0.6018497000, 1.4974466000", \ - "0.0326711000, 0.0396237000, 0.0572395000, 0.1079738000, 0.2475863000, 0.5993888000, 1.5013142000", \ - "0.0467517000, 0.0543266000, 0.0708954000, 0.1149295000, 0.2482871000, 0.6033045000, 1.4943530000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkbuf_16") { - leakage_power () { - value : 0.0141674000; - when : "A"; - } - leakage_power () { - value : 0.0104788000; - when : "!A"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__clkbuf"; - cell_leakage_power : 0.0123231100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0073970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0069000000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0078940000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019054750, 0.0072616730, 0.0276738800, 0.1054638000, 0.4019172000, 1.5316870000"); - values("0.0892438000, 0.0873585000, 0.0798327000, 0.0512375000, -0.066287300, -0.542857300, -2.372215900", \ - "0.0888013000, 0.0869134000, 0.0792662000, 0.0510788000, -0.066713200, -0.543154800, -2.371812400", \ - "0.0882813000, 0.0862969000, 0.0786808000, 0.0502908000, -0.067252800, -0.543608500, -2.372428600", \ - "0.0876977000, 0.0856661000, 0.0779800000, 0.0491635000, -0.068692000, -0.544470800, -2.373101300", \ - "0.0883907000, 0.0864069000, 0.0769338000, 0.0472944000, -0.070559300, -0.545718100, -2.373778000", \ - "0.0881862000, 0.0858777000, 0.0771893000, 0.0464367000, -0.072447100, -0.546660800, -2.373648500", \ - "0.0992035000, 0.0965979000, 0.0871300000, 0.0533862000, -0.070421400, -0.545247000, -2.371148500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019054750, 0.0072616730, 0.0276738800, 0.1054638000, 0.4019172000, 1.5316870000"); - values("0.0779259000, 0.0805015000, 0.0898766000, 0.1252153000, 0.2539896000, 0.7305273000, 2.5324463000", \ - "0.0775966000, 0.0800923000, 0.0893862000, 0.1249002000, 0.2537403000, 0.7303010000, 2.5325837000", \ - "0.0770308000, 0.0795403000, 0.0889991000, 0.1243204000, 0.2530068000, 0.7303003000, 2.5322665000", \ - "0.0765756000, 0.0791276000, 0.0883956000, 0.1233356000, 0.2517683000, 0.7289429000, 2.5372738000", \ - "0.0761284000, 0.0785082000, 0.0875751000, 0.1214972000, 0.2492309000, 0.7271398000, 2.5327842000", \ - "0.0798476000, 0.0821153000, 0.0908180000, 0.1240775000, 0.2478604000, 0.7244379000, 2.5405380000", \ - "0.0852927000, 0.0874109000, 0.0957195000, 0.1280790000, 0.2548248000, 0.7261965000, 2.5361984000"); - } - } - max_capacitance : 1.5316870000; - max_transition : 1.5081860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019054800, 0.0072616700, 0.0276739000, 0.1054640000, 0.4019170000, 1.5316900000"); - values("0.1140055000, 0.1157308000, 0.1214219000, 0.1379821000, 0.1813718000, 0.3083371000, 0.7699346000", \ - "0.1194265000, 0.1211497000, 0.1268422000, 0.1433524000, 0.1867260000, 0.3138878000, 0.7753811000", \ - "0.1326455000, 0.1343418000, 0.1405106000, 0.1571173000, 0.2003236000, 0.3274866000, 0.7888625000", \ - "0.1652728000, 0.1669264000, 0.1726332000, 0.1892064000, 0.2323584000, 0.3596272000, 0.8214312000", \ - "0.2389966000, 0.2406908000, 0.2462980000, 0.2628903000, 0.3060643000, 0.4334864000, 0.8954381000", \ - "0.3677665000, 0.3699379000, 0.3772389000, 0.3969053000, 0.4454995000, 0.5756912000, 1.0363066000", \ - "0.5712533000, 0.5740693000, 0.5836772000, 0.6102327000, 0.6703756000, 0.8080292000, 1.2692706000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019054800, 0.0072616700, 0.0276739000, 0.1054640000, 0.4019170000, 1.5316900000"); - values("0.0925527000, 0.0944568000, 0.1008882000, 0.1205128000, 0.1787117000, 0.3805414000, 1.1408930000", \ - "0.0969900000, 0.0988577000, 0.1052745000, 0.1249262000, 0.1831285000, 0.3849491000, 1.1449817000", \ - "0.1078884000, 0.1097683000, 0.1162092000, 0.1358306000, 0.1940645000, 0.3958863000, 1.1567394000", \ - "0.1335737000, 0.1354388000, 0.1418590000, 0.1612603000, 0.2193619000, 0.4215236000, 1.1922539000", \ - "0.1803963000, 0.1824398000, 0.1893747000, 0.2097006000, 0.2686406000, 0.4711603000, 1.2346238000", \ - "0.2409254000, 0.2435099000, 0.2521326000, 0.2760641000, 0.3374131000, 0.5394857000, 1.3006430000", \ - "0.3012765000, 0.3046818000, 0.3160694000, 0.3469812000, 0.4178014000, 0.6200891000, 1.3799851000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019054800, 0.0072616700, 0.0276739000, 0.1054640000, 0.4019170000, 1.5316900000"); - values("0.0231864000, 0.0243136000, 0.0283301000, 0.0408749000, 0.0843111000, 0.2514862000, 0.9142117000", \ - "0.0231992000, 0.0243124000, 0.0282936000, 0.0409580000, 0.0842969000, 0.2514526000, 0.9140927000", \ - "0.0233643000, 0.0244565000, 0.0282345000, 0.0409459000, 0.0843016000, 0.2514697000, 0.9139139000", \ - "0.0233778000, 0.0243652000, 0.0283493000, 0.0411758000, 0.0844682000, 0.2514826000, 0.9119126000", \ - "0.0253054000, 0.0262699000, 0.0300055000, 0.0424624000, 0.0852643000, 0.2510528000, 0.9124512000", \ - "0.0369103000, 0.0381666000, 0.0422953000, 0.0544229000, 0.0938249000, 0.2546181000, 0.9130494000", \ - "0.0569045000, 0.0578926000, 0.0633547000, 0.0782564000, 0.1161798000, 0.2652438000, 0.9134366000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019054800, 0.0072616700, 0.0276739000, 0.1054640000, 0.4019170000, 1.5316900000"); - values("0.0244145000, 0.0258982000, 0.0311957000, 0.0504665000, 0.1229834000, 0.4085845000, 1.5005076000", \ - "0.0243806000, 0.0258864000, 0.0311864000, 0.0504848000, 0.1228388000, 0.4089202000, 1.5015728000", \ - "0.0243044000, 0.0257783000, 0.0311651000, 0.0504919000, 0.1231290000, 0.4096725000, 1.5059948000", \ - "0.0244488000, 0.0259356000, 0.0312255000, 0.0505529000, 0.1231489000, 0.4084040000, 1.5059430000", \ - "0.0295480000, 0.0309296000, 0.0357280000, 0.0542600000, 0.1245374000, 0.4090207000, 1.5081856000", \ - "0.0406586000, 0.0420786000, 0.0471337000, 0.0639122000, 0.1298328000, 0.4093889000, 1.5076468000", \ - "0.0589831000, 0.0609899000, 0.0673859000, 0.0861324000, 0.1447679000, 0.4127985000, 1.5034097000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkbuf_2") { - leakage_power () { - value : 0.0036593000; - when : "A"; - } - leakage_power () { - value : 0.0046480000; - when : "!A"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__clkbuf"; - cell_leakage_power : 0.0041536310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020650000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022950000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0149023000, 0.0136837000, 0.0100205000, -0.001924400, -0.037666300, -0.140992000, -0.437784000", \ - "0.0147288000, 0.0135331000, 0.0098541000, -0.002062400, -0.037799700, -0.141118000, -0.437990800", \ - "0.0145186000, 0.0132782000, 0.0095604000, -0.002340200, -0.038048300, -0.141308800, -0.438178700", \ - "0.0142655000, 0.0129780000, 0.0092258000, -0.002644400, -0.038221300, -0.141412300, -0.438213600", \ - "0.0138554000, 0.0126025000, 0.0089452000, -0.002891700, -0.038379900, -0.141458500, -0.438233300", \ - "0.0148530000, 0.0133812000, 0.0091544000, -0.003093700, -0.038283000, -0.141266700, -0.437921400", \ - "0.0168930000, 0.0152959000, 0.0109516000, -0.001340600, -0.036970400, -0.139653900, -0.436266400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0108107000, 0.0124642000, 0.0171040000, 0.0297824000, 0.0654056000, 0.1677499000, 0.4614270000", \ - "0.0106370000, 0.0122917000, 0.0169062000, 0.0296177000, 0.0652445000, 0.1675618000, 0.4613095000", \ - "0.0103226000, 0.0119776000, 0.0165905000, 0.0292766000, 0.0649740000, 0.1672452000, 0.4611907000", \ - "0.0100450000, 0.0116800000, 0.0161852000, 0.0288415000, 0.0646418000, 0.1669209000, 0.4587361000", \ - "0.0100195000, 0.0115644000, 0.0160256000, 0.0285990000, 0.0641786000, 0.1668194000, 0.4588579000", \ - "0.0107564000, 0.0122801000, 0.0166001000, 0.0291916000, 0.0646445000, 0.1667150000, 0.4607544000", \ - "0.0121278000, 0.0136362000, 0.0178608000, 0.0303830000, 0.0658677000, 0.1683054000, 0.4594940000"); - } - } - max_capacitance : 0.2810770000; - max_transition : 1.5064040000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0715455000, 0.0763967000, 0.0874878000, 0.1121315000, 0.1732773000, 0.3441029000, 0.8356337000", \ - "0.0769644000, 0.0818215000, 0.0928298000, 0.1175851000, 0.1787316000, 0.3495579000, 0.8401411000", \ - "0.0900539000, 0.0947513000, 0.1057613000, 0.1304979000, 0.1916595000, 0.3624542000, 0.8544541000", \ - "0.1213416000, 0.1261116000, 0.1371333000, 0.1616166000, 0.2229276000, 0.3937075000, 0.8862640000", \ - "0.1797649000, 0.1853307000, 0.1976411000, 0.2240136000, 0.2863648000, 0.4569685000, 0.9462775000", \ - "0.2679674000, 0.2752934000, 0.2908089000, 0.3209856000, 0.3859637000, 0.5572721000, 1.0450026000", \ - "0.3993197000, 0.4090175000, 0.4298385000, 0.4685859000, 0.5399322000, 0.7118506000, 1.2009326000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0662163000, 0.0714230000, 0.0838709000, 0.1136824000, 0.1939208000, 0.4238545000, 1.0849718000", \ - "0.0705854000, 0.0757885000, 0.0882884000, 0.1181916000, 0.1984797000, 0.4281069000, 1.0875054000", \ - "0.0814050000, 0.0866105000, 0.0989495000, 0.1288524000, 0.2089679000, 0.4387360000, 1.0983581000", \ - "0.1065003000, 0.1117772000, 0.1242473000, 0.1541242000, 0.2348755000, 0.4647866000, 1.1332087000", \ - "0.1448172000, 0.1511556000, 0.1649346000, 0.1959158000, 0.2768002000, 0.5066385000, 1.1617454000", \ - "0.1922081000, 0.2003711000, 0.2174669000, 0.2518387000, 0.3333480000, 0.5618555000, 1.2207700000", \ - "0.2397060000, 0.2509717000, 0.2742588000, 0.3171372000, 0.4009552000, 0.6290706000, 1.2859528000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0154265000, 0.0190168000, 0.0286364000, 0.0546980000, 0.1313735000, 0.3596761000, 1.0183778000", \ - "0.0154765000, 0.0191428000, 0.0287511000, 0.0546706000, 0.1314359000, 0.3600606000, 1.0189631000", \ - "0.0154658000, 0.0191086000, 0.0288248000, 0.0547414000, 0.1313404000, 0.3618959000, 1.0129988000", \ - "0.0156464000, 0.0193014000, 0.0289334000, 0.0548446000, 0.1311622000, 0.3609529000, 1.0154152000", \ - "0.0206227000, 0.0243860000, 0.0334569000, 0.0578154000, 0.1322547000, 0.3614455000, 1.0198979000", \ - "0.0303647000, 0.0346578000, 0.0437343000, 0.0669294000, 0.1372084000, 0.3596617000, 1.0170109000", \ - "0.0451522000, 0.0509120000, 0.0625359000, 0.0858699000, 0.1489119000, 0.3639232000, 1.0143166000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0173436000, 0.0221799000, 0.0355709000, 0.0745499000, 0.1913238000, 0.5302312000, 1.5064037000", \ - "0.0173705000, 0.0221636000, 0.0355633000, 0.0747020000, 0.1909094000, 0.5301696000, 1.5011482000", \ - "0.0173927000, 0.0221323000, 0.0354693000, 0.0747678000, 0.1913624000, 0.5288327000, 1.5042423000", \ - "0.0185151000, 0.0231120000, 0.0362193000, 0.0747716000, 0.1912108000, 0.5297286000, 1.5044358000", \ - "0.0242697000, 0.0286167000, 0.0405678000, 0.0774116000, 0.1918092000, 0.5284798000, 1.4985770000", \ - "0.0339827000, 0.0389704000, 0.0506462000, 0.0835470000, 0.1933769000, 0.5284553000, 1.5006499000", \ - "0.0488169000, 0.0555929000, 0.0687040000, 0.0999539000, 0.1993825000, 0.5317950000, 1.4994096000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkbuf_4") { - leakage_power () { - value : 0.0043252000; - when : "A"; - } - leakage_power () { - value : 0.0048763000; - when : "!A"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__clkbuf"; - cell_leakage_power : 0.0046007730; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019840000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022280000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015901190, 0.0050569580, 0.0160823300, 0.0511456500, 0.1626553000, 0.5172828000"); - values("0.0222729000, 0.0207027000, 0.0159148000, 4.5783562e-05, -0.055463400, -0.235633300, -0.809879800", \ - "0.0221503000, 0.0205703000, 0.0158006000, -0.000101700, -0.055590600, -0.235745200, -0.809989300", \ - "0.0219991000, 0.0203954000, 0.0156315000, -0.000325900, -0.055724000, -0.235874900, -0.810327700", \ - "0.0217480000, 0.0201789000, 0.0152887000, -0.000753700, -0.056139100, -0.236142000, -0.810399900", \ - "0.0218947000, 0.0202093000, 0.0151196000, -0.001179200, -0.056585800, -0.236274300, -0.810588800", \ - "0.0235918000, 0.0218792000, 0.0162464000, -0.001286300, -0.056613500, -0.236272700, -0.810433400", \ - "0.0259392000, 0.0240931000, 0.0179044000, -0.000138800, -0.056477100, -0.235697400, -0.809528200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015901190, 0.0050569580, 0.0160823300, 0.0511456500, 0.1626553000, 0.5172828000"); - values("0.0208021000, 0.0226807000, 0.0286406000, 0.0471890000, 0.1039644000, 0.2830627000, 0.8527353000", \ - "0.0206310000, 0.0225192000, 0.0285389000, 0.0469270000, 0.1038271000, 0.2828527000, 0.8522082000", \ - "0.0204488000, 0.0223309000, 0.0282993000, 0.0467993000, 0.1036362000, 0.2826957000, 0.8520225000", \ - "0.0202970000, 0.0221787000, 0.0281061000, 0.0464691000, 0.1031954000, 0.2812671000, 0.8474285000", \ - "0.0200954000, 0.0219300000, 0.0278700000, 0.0459216000, 0.1023930000, 0.2808915000, 0.8479728000", \ - "0.0213478000, 0.0230903000, 0.0286401000, 0.0463812000, 0.1025987000, 0.2808099000, 0.8471670000", \ - "0.0228845000, 0.0246703000, 0.0301191000, 0.0476421000, 0.1037346000, 0.2826979000, 0.8488298000"); - } - } - max_capacitance : 0.5172830000; - max_transition : 1.5083400000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015901200, 0.0050569600, 0.0160823000, 0.0511456000, 0.1626550000, 0.5172830000"); - values("0.1025052000, 0.1064255000, 0.1165853000, 0.1396352000, 0.1939519000, 0.3460363000, 0.8245146000", \ - "0.1079128000, 0.1118363000, 0.1219609000, 0.1451357000, 0.1993825000, 0.3514017000, 0.8305131000", \ - "0.1213600000, 0.1252668000, 0.1353542000, 0.1584980000, 0.2126335000, 0.3649607000, 0.8450909000", \ - "0.1524429000, 0.1564359000, 0.1669153000, 0.1899847000, 0.2439154000, 0.3964348000, 0.8768524000", \ - "0.2235564000, 0.2277078000, 0.2380935000, 0.2614546000, 0.3163021000, 0.4686934000, 0.9512199000", \ - "0.3397118000, 0.3451386000, 0.3585268000, 0.3867278000, 0.4457333000, 0.5988942000, 1.0791332000", \ - "0.5161570000, 0.5234488000, 0.5411083000, 0.5783223000, 0.6488245000, 0.8067453000, 1.2847917000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015901200, 0.0050569600, 0.0160823000, 0.0511456000, 0.1626550000, 0.5172830000"); - values("0.0913500000, 0.0957113000, 0.1069565000, 0.1344774000, 0.2074873000, 0.4310310000, 1.1436324000", \ - "0.0959316000, 0.1003133000, 0.1116235000, 0.1390777000, 0.2121059000, 0.4363517000, 1.1470124000", \ - "0.1069348000, 0.1112831000, 0.1225512000, 0.1500151000, 0.2230944000, 0.4474278000, 1.1578212000", \ - "0.1333786000, 0.1376603000, 0.1488676000, 0.1762407000, 0.2492691000, 0.4726047000, 1.1806395000", \ - "0.1839123000, 0.1888019000, 0.2011908000, 0.2296071000, 0.3031710000, 0.5262145000, 1.2419760000", \ - "0.2507145000, 0.2573184000, 0.2729238000, 0.3060847000, 0.3820850000, 0.6050476000, 1.3132591000", \ - "0.3282425000, 0.3368944000, 0.3579237000, 0.4009142000, 0.4839829000, 0.7089512000, 1.4145048000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015901200, 0.0050569600, 0.0160823000, 0.0511456000, 0.1626550000, 0.5172830000"); - values("0.0205112000, 0.0232649000, 0.0303525000, 0.0500122000, 0.1090162000, 0.3073318000, 0.9552273000", \ - "0.0205676000, 0.0232185000, 0.0304822000, 0.0500785000, 0.1092417000, 0.3069343000, 0.9551601000", \ - "0.0207257000, 0.0233507000, 0.0304938000, 0.0498846000, 0.1090597000, 0.3067001000, 0.9473157000", \ - "0.0207050000, 0.0231869000, 0.0304960000, 0.0499061000, 0.1088736000, 0.3067467000, 0.9479135000", \ - "0.0236324000, 0.0260143000, 0.0329316000, 0.0516677000, 0.1097796000, 0.3074008000, 0.9517337000", \ - "0.0348812000, 0.0380331000, 0.0457274000, 0.0640193000, 0.1182500000, 0.3086164000, 0.9481194000", \ - "0.0529562000, 0.0570791000, 0.0668688000, 0.0878507000, 0.1380510000, 0.3160412000, 0.9490548000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015901200, 0.0050569600, 0.0160823000, 0.0511456000, 0.1626550000, 0.5172830000"); - values("0.0220686000, 0.0253667000, 0.0352570000, 0.0646148000, 0.1617831000, 0.4819556000, 1.5083399000", \ - "0.0221242000, 0.0254894000, 0.0351856000, 0.0646678000, 0.1616000000, 0.4830253000, 1.5071288000", \ - "0.0222756000, 0.0255125000, 0.0352953000, 0.0645480000, 0.1618156000, 0.4831407000, 1.5073632000", \ - "0.0222332000, 0.0256223000, 0.0353131000, 0.0647675000, 0.1619364000, 0.4819058000, 1.5048874000", \ - "0.0279743000, 0.0308479000, 0.0399481000, 0.0675373000, 0.1623019000, 0.4821623000, 1.5060381000", \ - "0.0394751000, 0.0429464000, 0.0525688000, 0.0783135000, 0.1669829000, 0.4811563000, 1.5046431000", \ - "0.0568396000, 0.0624212000, 0.0739159000, 0.0996620000, 0.1791079000, 0.4843484000, 1.5014531000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkbuf_8") { - leakage_power () { - value : 0.0075141000; - when : "A"; - } - leakage_power () { - value : 0.0068657000; - when : "!A"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__clkbuf"; - cell_leakage_power : 0.0071899020; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0039170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0036770000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0041570000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017468110, 0.0061026960, 0.0213205100, 0.0744857900, 0.2602252000, 0.9091283000"); - values("0.0439196000, 0.0422305000, 0.0361121000, 0.0147630000, -0.067420200, -0.366737900, -1.417325800", \ - "0.0437916000, 0.0420063000, 0.0359728000, 0.0146529000, -0.067614500, -0.366945700, -1.417537200", \ - "0.0434898000, 0.0417389000, 0.0355348000, 0.0142134000, -0.067963000, -0.367231800, -1.417949600", \ - "0.0430287000, 0.0412896000, 0.0350847000, 0.0135535000, -0.068787600, -0.367721100, -1.418271200", \ - "0.0435281000, 0.0417360000, 0.0353924000, 0.0131402000, -0.069600100, -0.368332900, -1.418571500", \ - "0.0461712000, 0.0440706000, 0.0372477000, 0.0127932000, -0.070083600, -0.368438800, -1.418446300", \ - "0.0501803000, 0.0479384000, 0.0404519000, 0.0172455000, -0.069555400, -0.367216900, -1.416593400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017468110, 0.0061026960, 0.0213205100, 0.0744857900, 0.2602252000, 0.9091283000"); - values("0.0392681000, 0.0414887000, 0.0490122000, 0.0751107000, 0.1622916000, 0.4611430000, 1.4956856000", \ - "0.0391502000, 0.0412274000, 0.0488541000, 0.0748691000, 0.1620777000, 0.4610076000, 1.5030615000", \ - "0.0386655000, 0.0408745000, 0.0484531000, 0.0745524000, 0.1617005000, 0.4604706000, 1.4945235000", \ - "0.0383921000, 0.0405307000, 0.0481800000, 0.0738617000, 0.1608397000, 0.4605267000, 1.4949479000", \ - "0.0383882000, 0.0404859000, 0.0478278000, 0.0731045000, 0.1590260000, 0.4592713000, 1.5032196000", \ - "0.0402810000, 0.0422948000, 0.0493531000, 0.0745419000, 0.1587542000, 0.4568355000, 1.5008394000", \ - "0.0429582000, 0.0447908000, 0.0516027000, 0.0762731000, 0.1618782000, 0.4582257000, 1.4947426000"); - } - } - max_capacitance : 0.9091280000; - max_transition : 1.5142470000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017468100, 0.0061027000, 0.0213205000, 0.0744858000, 0.2602250000, 0.9091280000"); - values("0.1032238000, 0.1057764000, 0.1132007000, 0.1321387000, 0.1787291000, 0.3127927000, 0.7708767000", \ - "0.1088701000, 0.1113654000, 0.1187928000, 0.1378564000, 0.1842500000, 0.3184958000, 0.7762466000", \ - "0.1220698000, 0.1245346000, 0.1318632000, 0.1513332000, 0.1977364000, 0.3319057000, 0.7894952000", \ - "0.1545639000, 0.1570349000, 0.1644291000, 0.1833382000, 0.2299216000, 0.3643497000, 0.8206332000", \ - "0.2265578000, 0.2291526000, 0.2367556000, 0.2557977000, 0.3025825000, 0.4372515000, 0.8939933000", \ - "0.3479511000, 0.3513252000, 0.3610938000, 0.3845738000, 0.4358061000, 0.5727983000, 1.0319524000", \ - "0.5364469000, 0.5409415000, 0.5538488000, 0.5849771000, 0.6484324000, 0.7909523000, 1.2474557000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017468100, 0.0061027000, 0.0213205000, 0.0744858000, 0.2602250000, 0.9091280000"); - values("0.0873982000, 0.0902000000, 0.0985632000, 0.1215397000, 0.1866671000, 0.4012755000, 1.1458812000", \ - "0.0918925000, 0.0946695000, 0.1030297000, 0.1260336000, 0.1911202000, 0.4055206000, 1.1556069000", \ - "0.1029230000, 0.1057123000, 0.1141331000, 0.1370277000, 0.2021565000, 0.4173891000, 1.1612002000", \ - "0.1287652000, 0.1315656000, 0.1398996000, 0.1627709000, 0.2277114000, 0.4426435000, 1.1870251000", \ - "0.1763462000, 0.1795294000, 0.1888237000, 0.2129772000, 0.2784062000, 0.4938256000, 1.2436772000", \ - "0.2382740000, 0.2424159000, 0.2541788000, 0.2822469000, 0.3498567000, 0.5644328000, 1.3103293000", \ - "0.3032267000, 0.3086452000, 0.3243595000, 0.3609786000, 0.4374858000, 0.6521989000, 1.3945283000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017468100, 0.0061027000, 0.0213205000, 0.0744858000, 0.2602250000, 0.9091280000"); - values("0.0209900000, 0.0224645000, 0.0276527000, 0.0426982000, 0.0899723000, 0.2611759000, 0.8849450000", \ - "0.0211284000, 0.0224236000, 0.0277463000, 0.0425912000, 0.0899897000, 0.2612005000, 0.8840557000", \ - "0.0208912000, 0.0225161000, 0.0275141000, 0.0425875000, 0.0900036000, 0.2616951000, 0.8799486000", \ - "0.0208517000, 0.0224385000, 0.0277352000, 0.0426761000, 0.0899355000, 0.2607210000, 0.8861957000", \ - "0.0236109000, 0.0252378000, 0.0301154000, 0.0443205000, 0.0907661000, 0.2615641000, 0.8771955000", \ - "0.0350799000, 0.0369991000, 0.0426903000, 0.0565522000, 0.0999796000, 0.2640375000, 0.8838059000", \ - "0.0542660000, 0.0567169000, 0.0638486000, 0.0811250000, 0.1218388000, 0.2728307000, 0.8790218000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017468100, 0.0061027000, 0.0213205000, 0.0744858000, 0.2602250000, 0.9091280000"); - values("0.0220288000, 0.0241858000, 0.0314808000, 0.0549380000, 0.1387776000, 0.4436266000, 1.5080432000", \ - "0.0220880000, 0.0243628000, 0.0314611000, 0.0549991000, 0.1387719000, 0.4437010000, 1.5142466000", \ - "0.0220922000, 0.0242852000, 0.0314265000, 0.0549429000, 0.1387031000, 0.4426261000, 1.5061696000", \ - "0.0221786000, 0.0244903000, 0.0315513000, 0.0551121000, 0.1388361000, 0.4435214000, 1.5097914000", \ - "0.0277979000, 0.0298462000, 0.0366090000, 0.0584021000, 0.1396855000, 0.4424494000, 1.5122539000", \ - "0.0389640000, 0.0413380000, 0.0481627000, 0.0689124000, 0.1446469000, 0.4418877000, 1.5076616000", \ - "0.0571696000, 0.0602601000, 0.0688954000, 0.0903741000, 0.1585852000, 0.4443420000, 1.4995185000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s15_1") { - leakage_power () { - value : 0.0045328000; - when : "A"; - } - leakage_power () { - value : 0.0045782000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0045555110; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020880000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023090000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0266052000, 0.0255791000, 0.0225076000, 0.0137312000, -0.009650700, -0.071029400, -0.231347100", \ - "0.0263922000, 0.0253967000, 0.0223151000, 0.0135452000, -0.009851100, -0.071220800, -0.231593600", \ - "0.0261448000, 0.0251215000, 0.0220475000, 0.0132799000, -0.010148600, -0.071465100, -0.231828900", \ - "0.0258984000, 0.0248785000, 0.0218074000, 0.0130453000, -0.010372200, -0.071707700, -0.232083900", \ - "0.0257428000, 0.0247205000, 0.0216570000, 0.0128843000, -0.010524400, -0.071847100, -0.232186700", \ - "0.0261537000, 0.0249720000, 0.0217045000, 0.0130026000, -0.010189100, -0.071495200, -0.231879400", \ - "0.0275993000, 0.0263957000, 0.0231509000, 0.0143489000, -0.009063300, -0.070011800, -0.230365400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0209230000, 0.0223597000, 0.0258877000, 0.0348017000, 0.0578928000, 0.1185056000, 0.2771312000", \ - "0.0206895000, 0.0221246000, 0.0256531000, 0.0345710000, 0.0576331000, 0.1183947000, 0.2770276000", \ - "0.0203439000, 0.0217886000, 0.0253146000, 0.0341997000, 0.0573421000, 0.1180661000, 0.2766365000", \ - "0.0199990000, 0.0214415000, 0.0249803000, 0.0338554000, 0.0569866000, 0.1181170000, 0.2767269000", \ - "0.0198532000, 0.0213037000, 0.0248373000, 0.0337540000, 0.0568435000, 0.1180564000, 0.2762289000", \ - "0.0204379000, 0.0218157000, 0.0253261000, 0.0340302000, 0.0572843000, 0.1174099000, 0.2762932000", \ - "0.0217468000, 0.0231554000, 0.0266850000, 0.0355955000, 0.0589440000, 0.1195957000, 0.2779719000"); - } - } - max_capacitance : 0.1602270000; - max_transition : 1.5058640000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1475420000, 0.1542741000, 0.1689973000, 0.2015366000, 0.2806218000, 0.4862768000, 1.0242375000", \ - "0.1529136000, 0.1596284000, 0.1743621000, 0.2068932000, 0.2860227000, 0.4923638000, 1.0313412000", \ - "0.1659695000, 0.1726952000, 0.1874449000, 0.2200087000, 0.2991772000, 0.5043826000, 1.0416217000", \ - "0.1959358000, 0.2026615000, 0.2174259000, 0.2499772000, 0.3292014000, 0.5351501000, 1.0732523000", \ - "0.2463342000, 0.2530160000, 0.2677435000, 0.3003146000, 0.3796126000, 0.5856536000, 1.1240638000", \ - "0.3233313000, 0.3300352000, 0.3447778000, 0.3773480000, 0.4565386000, 0.6620041000, 1.2012824000", \ - "0.4390513000, 0.4457585000, 0.4605403000, 0.4932287000, 0.5725742000, 0.7785059000, 1.3148344000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1448714000, 0.1510559000, 0.1658456000, 0.2024025000, 0.2965347000, 0.5430122000, 1.1865111000", \ - "0.1491139000, 0.1552913000, 0.1700829000, 0.2066430000, 0.3007977000, 0.5473773000, 1.1928419000", \ - "0.1598778000, 0.1661095000, 0.1808983000, 0.2174674000, 0.3115832000, 0.5580769000, 1.2024753000", \ - "0.1828590000, 0.1890776000, 0.2038737000, 0.2404669000, 0.3342646000, 0.5820292000, 1.2291514000", \ - "0.2169887000, 0.2232150000, 0.2379693000, 0.2746100000, 0.3685335000, 0.6151032000, 1.2575854000", \ - "0.2608235000, 0.2670600000, 0.2818551000, 0.3184289000, 0.4125740000, 0.6582940000, 1.3025371000", \ - "0.3076364000, 0.3138705000, 0.3286663000, 0.3651872000, 0.4593247000, 0.7050942000, 1.3478632000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0194258000, 0.0252148000, 0.0398003000, 0.0773994000, 0.1807179000, 0.4530253000, 1.1646872000", \ - "0.0192991000, 0.0253852000, 0.0399117000, 0.0776386000, 0.1804528000, 0.4547039000, 1.1680612000", \ - "0.0192566000, 0.0252398000, 0.0398372000, 0.0777068000, 0.1798586000, 0.4516493000, 1.1737552000", \ - "0.0193321000, 0.0253176000, 0.0398151000, 0.0776720000, 0.1813287000, 0.4537434000, 1.1715532000", \ - "0.0194898000, 0.0253272000, 0.0400773000, 0.0777108000, 0.1815865000, 0.4537524000, 1.1658253000", \ - "0.0193607000, 0.0254452000, 0.0398831000, 0.0777043000, 0.1790299000, 0.4522671000, 1.1842177000", \ - "0.0194474000, 0.0254632000, 0.0399700000, 0.0777498000, 0.1807957000, 0.4523660000, 1.1652902000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0187569000, 0.0258350000, 0.0447545000, 0.0953708000, 0.2292510000, 0.5807397000, 1.5054509000", \ - "0.0187585000, 0.0258251000, 0.0447825000, 0.0953528000, 0.2292141000, 0.5814632000, 1.5000210000", \ - "0.0187231000, 0.0258366000, 0.0447353000, 0.0953146000, 0.2293844000, 0.5809068000, 1.5034074000", \ - "0.0187498000, 0.0258047000, 0.0448182000, 0.0954902000, 0.2296519000, 0.5831222000, 1.5058644000", \ - "0.0187625000, 0.0258469000, 0.0447320000, 0.0954503000, 0.2294952000, 0.5831394000, 1.5026975000", \ - "0.0188228000, 0.0258845000, 0.0447517000, 0.0955057000, 0.2290487000, 0.5799099000, 1.5054953000", \ - "0.0189545000, 0.0259776000, 0.0449270000, 0.0955513000, 0.2295846000, 0.5831611000, 1.4976353000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s15_2") { - leakage_power () { - value : 0.0058182000; - when : "A"; - } - leakage_power () { - value : 0.0037174000; - when : "!A"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0047678160; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0022040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020890000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023190000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014356320, 0.0041220770, 0.0118355700, 0.0339830300, 0.0975742200, 0.2801613000"); - values("0.0290343000, 0.0277752000, 0.0241442000, 0.0124586000, -0.023135200, -0.126127600, -0.421965400", \ - "0.0288496000, 0.0275554000, 0.0239620000, 0.0122835000, -0.023312000, -0.126352900, -0.422188000", \ - "0.0286208000, 0.0273461000, 0.0237276000, 0.0120214000, -0.023564100, -0.126576200, -0.422389300", \ - "0.0284051000, 0.0271236000, 0.0235007000, 0.0117985000, -0.023784400, -0.126794900, -0.422595200", \ - "0.0282747000, 0.0269966000, 0.0233851000, 0.0117173000, -0.023895100, -0.126880500, -0.422655100", \ - "0.0293833000, 0.0280047000, 0.0239084000, 0.0117073000, -0.023534400, -0.126527700, -0.422333300", \ - "0.0309304000, 0.0294515000, 0.0254146000, 0.0132764000, -0.022335300, -0.124988900, -0.420776800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014356320, 0.0041220770, 0.0118355700, 0.0339830300, 0.0975742200, 0.2801613000"); - values("0.0254717000, 0.0271863000, 0.0317967000, 0.0444497000, 0.0800107000, 0.1820936000, 0.4746672000", \ - "0.0252201000, 0.0269287000, 0.0315766000, 0.0442095000, 0.0798037000, 0.1817773000, 0.4743675000", \ - "0.0248632000, 0.0265702000, 0.0312145000, 0.0438609000, 0.0794376000, 0.1812942000, 0.4743319000", \ - "0.0245258000, 0.0262323000, 0.0308748000, 0.0435291000, 0.0791018000, 0.1811247000, 0.4739376000", \ - "0.0243871000, 0.0260561000, 0.0307200000, 0.0433609000, 0.0789419000, 0.1810072000, 0.4756773000", \ - "0.0250662000, 0.0266946000, 0.0312657000, 0.0437636000, 0.0794345000, 0.1807226000, 0.4713480000", \ - "0.0264439000, 0.0280476000, 0.0326015000, 0.0453356000, 0.0812176000, 0.1834721000, 0.4758381000"); - } - } - max_capacitance : 0.2801610000; - max_transition : 1.5070320000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014356300, 0.0041220800, 0.0118356000, 0.0339830000, 0.0975742000, 0.2801610000"); - values("0.1642094000, 0.1696894000, 0.1821439000, 0.2089448000, 0.2710766000, 0.4389723000, 0.9184269000", \ - "0.1694885000, 0.1749626000, 0.1874316000, 0.2142057000, 0.2763274000, 0.4442615000, 0.9267268000", \ - "0.1823997000, 0.1878837000, 0.2003837000, 0.2271176000, 0.2892915000, 0.4569888000, 0.9365597000", \ - "0.2120333000, 0.2175160000, 0.2300038000, 0.2567228000, 0.3188636000, 0.4866437000, 0.9666155000", \ - "0.2616856000, 0.2671518000, 0.2795946000, 0.3063502000, 0.3686066000, 0.5365278000, 1.0179817000", \ - "0.3370523000, 0.3425241000, 0.3549210000, 0.3817270000, 0.4439585000, 0.6116562000, 1.0954780000", \ - "0.4493714000, 0.4548520000, 0.4673137000, 0.4941297000, 0.5563930000, 0.7243825000, 1.2039661000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014356300, 0.0041220800, 0.0118356000, 0.0339830000, 0.0975742000, 0.2801610000"); - values("0.1571399000, 0.1621186000, 0.1741598000, 0.2043890000, 0.2867641000, 0.5237674000, 1.1983349000", \ - "0.1613246000, 0.1663272000, 0.1784078000, 0.2086215000, 0.2911582000, 0.5273419000, 1.2045575000", \ - "0.1720246000, 0.1770254000, 0.1891067000, 0.2193270000, 0.3018769000, 0.5383117000, 1.2149426000", \ - "0.1950847000, 0.2000810000, 0.2121630000, 0.2423826000, 0.3249050000, 0.5612274000, 1.2382977000", \ - "0.2291415000, 0.2340940000, 0.2461538000, 0.2763939000, 0.3590666000, 0.5943425000, 1.2769436000", \ - "0.2734263000, 0.2783939000, 0.2904567000, 0.3206772000, 0.4033389000, 0.6385246000, 1.3154386000", \ - "0.3223817000, 0.3273860000, 0.3394470000, 0.3696734000, 0.4521021000, 0.6882060000, 1.3625058000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014356300, 0.0041220800, 0.0118356000, 0.0339830000, 0.0975742000, 0.2801610000"); - values("0.0184063000, 0.0226118000, 0.0325644000, 0.0583356000, 0.1318743000, 0.3542606000, 1.0034532000", \ - "0.0183612000, 0.0224610000, 0.0326684000, 0.0583428000, 0.1314964000, 0.3537693000, 0.9971901000", \ - "0.0184250000, 0.0225465000, 0.0324889000, 0.0583878000, 0.1315636000, 0.3551414000, 1.0051634000", \ - "0.0183911000, 0.0226027000, 0.0324179000, 0.0583980000, 0.1319306000, 0.3551067000, 1.0025240000", \ - "0.0183660000, 0.0223485000, 0.0325527000, 0.0585118000, 0.1315821000, 0.3532157000, 0.9977639000", \ - "0.0183796000, 0.0225400000, 0.0326131000, 0.0584385000, 0.1316764000, 0.3526944000, 0.9902571000", \ - "0.0185165000, 0.0227364000, 0.0325225000, 0.0584717000, 0.1319469000, 0.3512565000, 0.9899489000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014356300, 0.0041220800, 0.0118356000, 0.0339830000, 0.0975742000, 0.2801610000"); - values("0.0161815000, 0.0209072000, 0.0343143000, 0.0738009000, 0.1907700000, 0.5316231000, 1.5022874000", \ - "0.0162595000, 0.0209581000, 0.0342568000, 0.0739565000, 0.1907952000, 0.5294999000, 1.5031547000", \ - "0.0162657000, 0.0209436000, 0.0343027000, 0.0738931000, 0.1907606000, 0.5283185000, 1.5033081000", \ - "0.0162662000, 0.0209507000, 0.0343107000, 0.0738603000, 0.1907819000, 0.5303180000, 1.5024252000", \ - "0.0162250000, 0.0209078000, 0.0342806000, 0.0739775000, 0.1905092000, 0.5296794000, 1.5070324000", \ - "0.0162652000, 0.0210224000, 0.0342964000, 0.0738649000, 0.1904057000, 0.5279427000, 1.4965156000", \ - "0.0163513000, 0.0210912000, 0.0344305000, 0.0740032000, 0.1905709000, 0.5296388000, 1.4954880000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s18_1") { - leakage_power () { - value : 0.0043114000; - when : "A"; - } - leakage_power () { - value : 0.0042517000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0042815450; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0022010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020920000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023110000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0272446000, 0.0262207000, 0.0231923000, 0.0144416000, -0.008952500, -0.070287900, -0.230678300", \ - "0.0270501000, 0.0260299000, 0.0229855000, 0.0142490000, -0.009167400, -0.070513600, -0.230906700", \ - "0.0267812000, 0.0257585000, 0.0227279000, 0.0139843000, -0.009421500, -0.070754700, -0.231128400", \ - "0.0265320000, 0.0255085000, 0.0224755000, 0.0136958000, -0.009717600, -0.071046000, -0.231416000", \ - "0.0263619000, 0.0253522000, 0.0223126000, 0.0135240000, -0.009875400, -0.071209200, -0.231563700", \ - "0.0268106000, 0.0256112000, 0.0223518000, 0.0139895000, -0.009303300, -0.070638200, -0.230964500", \ - "0.0282394000, 0.0270297000, 0.0237833000, 0.0150044000, -0.008431000, -0.069287800, -0.229658000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0216766000, 0.0231276000, 0.0266856000, 0.0355889000, 0.0586721000, 0.1193819000, 0.2791193000", \ - "0.0214183000, 0.0228783000, 0.0264314000, 0.0353282000, 0.0584545000, 0.1190857000, 0.2781134000", \ - "0.0211024000, 0.0225637000, 0.0261177000, 0.0350108000, 0.0581377000, 0.1187770000, 0.2777777000", \ - "0.0207337000, 0.0222094000, 0.0257653000, 0.0346563000, 0.0577267000, 0.1182074000, 0.2776320000", \ - "0.0205673000, 0.0220316000, 0.0255764000, 0.0345001000, 0.0577998000, 0.1182312000, 0.2766559000", \ - "0.0211642000, 0.0225527000, 0.0260631000, 0.0347698000, 0.0579774000, 0.1182422000, 0.2785436000", \ - "0.0224268000, 0.0238299000, 0.0273588000, 0.0362999000, 0.0597708000, 0.1204189000, 0.2785392000"); - } - } - max_capacitance : 0.1602270000; - max_transition : 1.5056410000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1601309000, 0.1670110000, 0.1820362000, 0.2149422000, 0.2942774000, 0.4995324000, 1.0401193000", \ - "0.1655510000, 0.1723567000, 0.1874454000, 0.2203586000, 0.2996971000, 0.5053480000, 1.0422966000", \ - "0.1785633000, 0.1854431000, 0.2004919000, 0.2334070000, 0.3127460000, 0.5180313000, 1.0553149000", \ - "0.2087265000, 0.2156040000, 0.2306470000, 0.2634807000, 0.3428702000, 0.5483557000, 1.0890383000", \ - "0.2604392000, 0.2673121000, 0.2822966000, 0.3152022000, 0.3945763000, 0.6004146000, 1.1370832000", \ - "0.3395066000, 0.3463765000, 0.3614199000, 0.3945100000, 0.4739237000, 0.6791467000, 1.2163414000", \ - "0.4587110000, 0.4655683000, 0.4806025000, 0.5135620000, 0.5930457000, 0.7985758000, 1.3355441000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1586736000, 0.1649786000, 0.1799063000, 0.2165194000, 0.3103829000, 0.5556987000, 1.1996036000", \ - "0.1628206000, 0.1691583000, 0.1840652000, 0.2206639000, 0.3146175000, 0.5604225000, 1.2066814000", \ - "0.1736424000, 0.1799824000, 0.1948904000, 0.2314980000, 0.3254227000, 0.5713359000, 1.2175213000", \ - "0.1970717000, 0.2033669000, 0.2182956000, 0.2549900000, 0.3489741000, 0.5966482000, 1.2426074000", \ - "0.2324570000, 0.2387521000, 0.2536805000, 0.2903611000, 0.3844558000, 0.6306103000, 1.2731631000", \ - "0.2782563000, 0.2846123000, 0.2995530000, 0.3362103000, 0.4302849000, 0.6754737000, 1.3201495000", \ - "0.3293646000, 0.3357032000, 0.3506769000, 0.3874627000, 0.4815727000, 0.7277968000, 1.3692130000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0201129000, 0.0259433000, 0.0406893000, 0.0781913000, 0.1803825000, 0.4583635000, 1.1705076000", \ - "0.0199524000, 0.0259926000, 0.0405284000, 0.0784045000, 0.1815932000, 0.4556939000, 1.1674293000", \ - "0.0200612000, 0.0258241000, 0.0404742000, 0.0781479000, 0.1805806000, 0.4580576000, 1.1716600000", \ - "0.0200614000, 0.0258362000, 0.0405024000, 0.0781733000, 0.1815148000, 0.4582763000, 1.1696587000", \ - "0.0200251000, 0.0260135000, 0.0406532000, 0.0781923000, 0.1814614000, 0.4531070000, 1.1693088000", \ - "0.0201091000, 0.0259026000, 0.0405551000, 0.0781297000, 0.1793036000, 0.4552041000, 1.1704430000", \ - "0.0200612000, 0.0262660000, 0.0407635000, 0.0783850000, 0.1817114000, 0.4542726000, 1.1710500000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0192022000, 0.0262805000, 0.0450800000, 0.0956750000, 0.2294641000, 0.5805328000, 1.5015692000", \ - "0.0192689000, 0.0263121000, 0.0451689000, 0.0956149000, 0.2294747000, 0.5828621000, 1.5027655000", \ - "0.0192712000, 0.0263122000, 0.0451684000, 0.0956372000, 0.2294869000, 0.5827684000, 1.5026399000", \ - "0.0192950000, 0.0262378000, 0.0451147000, 0.0955522000, 0.2289782000, 0.5824441000, 1.5050420000", \ - "0.0192283000, 0.0262786000, 0.0451216000, 0.0954549000, 0.2295377000, 0.5818896000, 1.4956502000", \ - "0.0193305000, 0.0263327000, 0.0450946000, 0.0955561000, 0.2288220000, 0.5802709000, 1.5056414000", \ - "0.0194301000, 0.0264041000, 0.0452457000, 0.0956502000, 0.2292362000, 0.5817281000, 1.4973256000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s18_2") { - leakage_power () { - value : 0.0056127000; - when : "A"; - } - leakage_power () { - value : 0.0042917000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0049522000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0022060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020970000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023160000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0299015000, 0.0286243000, 0.0249267000, 0.0129070000, -0.024243300, -0.133094100, -0.448981800", \ - "0.0296601000, 0.0283755000, 0.0247071000, 0.0127081000, -0.024459600, -0.133318800, -0.449107200", \ - "0.0294065000, 0.0281164000, 0.0244678000, 0.0124424000, -0.024712400, -0.133577700, -0.449338800", \ - "0.0291469000, 0.0278770000, 0.0241646000, 0.0121607000, -0.024997000, -0.133862500, -0.449618800", \ - "0.0289807000, 0.0276965000, 0.0240055000, 0.0119916000, -0.025162300, -0.134000700, -0.449819400", \ - "0.0300245000, 0.0286297000, 0.0244814000, 0.0119546000, -0.024874400, -0.133688900, -0.449517600", \ - "0.0315764000, 0.0301419000, 0.0259855000, 0.0136347000, -0.023683700, -0.132168100, -0.447984300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0259920000, 0.0277205000, 0.0325060000, 0.0456211000, 0.0827483000, 0.1903330000, 0.5005356000", \ - "0.0257600000, 0.0274951000, 0.0322401000, 0.0453951000, 0.0825479000, 0.1901800000, 0.5032978000", \ - "0.0254276000, 0.0271614000, 0.0318859000, 0.0449789000, 0.0822371000, 0.1898742000, 0.5004633000", \ - "0.0250594000, 0.0267907000, 0.0315628000, 0.0446524000, 0.0818903000, 0.1895503000, 0.5021157000", \ - "0.0248656000, 0.0266034000, 0.0313902000, 0.0445033000, 0.0816806000, 0.1895494000, 0.5027799000", \ - "0.0256096000, 0.0272765000, 0.0319655000, 0.0448702000, 0.0822305000, 0.1893407000, 0.5024173000", \ - "0.0269716000, 0.0285748000, 0.0332576000, 0.0464633000, 0.0839843000, 0.1917898000, 0.5039006000"); - } - } - max_capacitance : 0.2975560000; - max_transition : 1.5151690000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1727073000, 0.1782241000, 0.1909765000, 0.2187490000, 0.2839887000, 0.4625739000, 0.9789232000", \ - "0.1780168000, 0.1834989000, 0.1962452000, 0.2240261000, 0.2893556000, 0.4681527000, 0.9849378000", \ - "0.1909209000, 0.1964700000, 0.2092225000, 0.2369807000, 0.3021932000, 0.4810196000, 0.9971602000", \ - "0.2207655000, 0.2262672000, 0.2389405000, 0.2667098000, 0.3319411000, 0.5108129000, 1.0270421000", \ - "0.2708275000, 0.2763641000, 0.2891457000, 0.3168763000, 0.3822005000, 0.5607784000, 1.0779414000", \ - "0.3467611000, 0.3522867000, 0.3650466000, 0.3926786000, 0.4580688000, 0.6364800000, 1.1542023000", \ - "0.4606014000, 0.4661036000, 0.4788278000, 0.5066211000, 0.5719822000, 0.7503727000, 1.2658896000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1619170000, 0.1668150000, 0.1787529000, 0.2085414000, 0.2902463000, 0.5247637000, 1.2066319000", \ - "0.1661579000, 0.1710489000, 0.1829822000, 0.2127525000, 0.2942531000, 0.5300329000, 1.2134387000", \ - "0.1769759000, 0.1818763000, 0.1937796000, 0.2234999000, 0.3049226000, 0.5408505000, 1.2233601000", \ - "0.2004336000, 0.2053546000, 0.2172959000, 0.2469591000, 0.3286511000, 0.5641278000, 1.2457488000", \ - "0.2357841000, 0.2406810000, 0.2526219000, 0.2823870000, 0.3639525000, 0.5984536000, 1.2869472000", \ - "0.2822092000, 0.2871247000, 0.2990624000, 0.3287819000, 0.4104689000, 0.6449356000, 1.3268051000", \ - "0.3353205000, 0.3402435000, 0.3521998000, 0.3820146000, 0.4637562000, 0.6990492000, 1.3778052000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0191424000, 0.0233200000, 0.0335267000, 0.0601397000, 0.1373015000, 0.3756722000, 1.0745347000", \ - "0.0191214000, 0.0234488000, 0.0335290000, 0.0600800000, 0.1375418000, 0.3737828000, 1.0704024000", \ - "0.0192457000, 0.0232000000, 0.0335562000, 0.0600216000, 0.1376117000, 0.3736605000, 1.0676069000", \ - "0.0190969000, 0.0232939000, 0.0335367000, 0.0600577000, 0.1374776000, 0.3730330000, 1.0683545000", \ - "0.0190842000, 0.0233245000, 0.0332874000, 0.0602506000, 0.1375851000, 0.3754851000, 1.0664193000", \ - "0.0191752000, 0.0233382000, 0.0334287000, 0.0603075000, 0.1371682000, 0.3736098000, 1.0627257000", \ - "0.0192370000, 0.0232660000, 0.0336408000, 0.0602494000, 0.1374797000, 0.3710811000, 1.0607779000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0165624000, 0.0210814000, 0.0339756000, 0.0726012000, 0.1878837000, 0.5257051000, 1.5055314000", \ - "0.0165208000, 0.0210588000, 0.0340170000, 0.0724509000, 0.1881689000, 0.5264050000, 1.5126742000", \ - "0.0164511000, 0.0210471000, 0.0340402000, 0.0726356000, 0.1881550000, 0.5260041000, 1.5075764000", \ - "0.0165270000, 0.0210876000, 0.0340510000, 0.0724462000, 0.1879487000, 0.5263582000, 1.5098770000", \ - "0.0165154000, 0.0210675000, 0.0340736000, 0.0726330000, 0.1881602000, 0.5268799000, 1.5151690000", \ - "0.0165715000, 0.0211193000, 0.0340867000, 0.0725822000, 0.1877956000, 0.5253253000, 1.5106827000", \ - "0.0167522000, 0.0212453000, 0.0340871000, 0.0726697000, 0.1879135000, 0.5256184000, 1.4996508000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s25_1") { - leakage_power () { - value : 0.0048215000; - when : "A"; - } - leakage_power () { - value : 0.0027172000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0037693760; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0022080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020960000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023210000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012965110, 0.0033618830, 0.0087174390, 0.0226045200, 0.0586140200, 0.1519875000"); - values("0.0294447000, 0.0284653000, 0.0256198000, 0.0172616000, -0.005172900, -0.063579600, -0.214901100", \ - "0.0292603000, 0.0282833000, 0.0254285000, 0.0170713000, -0.005378500, -0.063772700, -0.215072500", \ - "0.0290075000, 0.0280060000, 0.0251558000, 0.0168070000, -0.005637600, -0.064037100, -0.215375400", \ - "0.0287227000, 0.0277239000, 0.0248733000, 0.0165246000, -0.005926500, -0.064330600, -0.215625600", \ - "0.0285525000, 0.0275795000, 0.0246793000, 0.0163407000, -0.006105400, -0.064500000, -0.215833800", \ - "0.0291449000, 0.0279378000, 0.0246925000, 0.0166882000, -0.005754800, -0.064144500, -0.215451700", \ - "0.0305054000, 0.0292743000, 0.0261220000, 0.0176012000, -0.004847600, -0.062922600, -0.214219900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012965110, 0.0033618830, 0.0087174390, 0.0226045200, 0.0586140200, 0.1519875000"); - values("0.0237801000, 0.0252565000, 0.0287833000, 0.0374465000, 0.0596076000, 0.1171852000, 0.2672780000", \ - "0.0235561000, 0.0250265000, 0.0285512000, 0.0372415000, 0.0595998000, 0.1175315000, 0.2667272000", \ - "0.0231775000, 0.0246572000, 0.0282047000, 0.0368850000, 0.0589747000, 0.1166560000, 0.2667178000", \ - "0.0227973000, 0.0242693000, 0.0277892000, 0.0364817000, 0.0588362000, 0.1167759000, 0.2661722000", \ - "0.0225736000, 0.0240637000, 0.0276198000, 0.0362775000, 0.0584402000, 0.1160657000, 0.2661756000", \ - "0.0232068000, 0.0245452000, 0.0278928000, 0.0364790000, 0.0585594000, 0.1160931000, 0.2660990000", \ - "0.0244972000, 0.0258762000, 0.0292537000, 0.0379707000, 0.0601390000, 0.1178825000, 0.2663021000"); - } - } - max_capacitance : 0.1519870000; - max_transition : 1.5088010000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012965100, 0.0033618800, 0.0087174400, 0.0226045000, 0.0586140000, 0.1519870000"); - values("0.2082778000, 0.2152867000, 0.2306441000, 0.2635193000, 0.3386665000, 0.5286411000, 1.0212748000", \ - "0.2135772000, 0.2205776000, 0.2359329000, 0.2688147000, 0.3439430000, 0.5338784000, 1.0247986000", \ - "0.2265824000, 0.2334619000, 0.2488182000, 0.2816846000, 0.3568322000, 0.5468611000, 1.0393335000", \ - "0.2569186000, 0.2638345000, 0.2792016000, 0.3120268000, 0.3871634000, 0.5769390000, 1.0692698000", \ - "0.3113429000, 0.3183462000, 0.3335837000, 0.3664597000, 0.4415747000, 0.6315122000, 1.1249014000", \ - "0.3945561000, 0.4015240000, 0.4168422000, 0.4497408000, 0.5249531000, 0.7147425000, 1.2071092000", \ - "0.5201776000, 0.5271235000, 0.5424748000, 0.5753274000, 0.6505626000, 0.8403707000, 1.3314112000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012965100, 0.0033618800, 0.0087174400, 0.0226045000, 0.0586140000, 0.1519870000"); - values("0.2129309000, 0.2195064000, 0.2350954000, 0.2728174000, 0.3680223000, 0.6142645000, 1.2557803000", \ - "0.2171841000, 0.2237844000, 0.2393148000, 0.2770489000, 0.3722035000, 0.6186719000, 1.2571638000", \ - "0.2277189000, 0.2343590000, 0.2498695000, 0.2874578000, 0.3829007000, 0.6290688000, 1.2726254000", \ - "0.2517516000, 0.2583414000, 0.2738460000, 0.3115714000, 0.4067048000, 0.6533079000, 1.2949940000", \ - "0.2901077000, 0.2967414000, 0.3122800000, 0.3500157000, 0.4452530000, 0.6915544000, 1.3349264000", \ - "0.3414299000, 0.3479844000, 0.3635598000, 0.4012892000, 0.4964454000, 0.7438180000, 1.3830814000", \ - "0.4037811000, 0.4103696000, 0.4259907000, 0.4637630000, 0.5590108000, 0.8049453000, 1.4432101000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012965100, 0.0033618800, 0.0087174400, 0.0226045000, 0.0586140000, 0.1519870000"); - values("0.0252720000, 0.0309681000, 0.0451204000, 0.0800968000, 0.1735552000, 0.4264966000, 1.0918062000", \ - "0.0252504000, 0.0308360000, 0.0451472000, 0.0800958000, 0.1727007000, 0.4263627000, 1.0774941000", \ - "0.0250326000, 0.0309010000, 0.0450787000, 0.0800970000, 0.1733802000, 0.4263922000, 1.0770443000", \ - "0.0250936000, 0.0309525000, 0.0453330000, 0.0800269000, 0.1732998000, 0.4229702000, 1.0864448000", \ - "0.0250271000, 0.0310915000, 0.0451695000, 0.0802430000, 0.1731858000, 0.4263900000, 1.0826293000", \ - "0.0252722000, 0.0308265000, 0.0452229000, 0.0801452000, 0.1724058000, 0.4249536000, 1.0733850000", \ - "0.0252257000, 0.0310887000, 0.0454604000, 0.0801892000, 0.1733360000, 0.4232177000, 1.0762610000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012965100, 0.0033618800, 0.0087174400, 0.0226045000, 0.0586140000, 0.1519870000"); - values("0.0242592000, 0.0315155000, 0.0507595000, 0.1017972000, 0.2363794000, 0.5891164000, 1.5006447000", \ - "0.0242383000, 0.0315573000, 0.0507816000, 0.1018469000, 0.2364249000, 0.5890283000, 1.4994983000", \ - "0.0243167000, 0.0316166000, 0.0506793000, 0.1017796000, 0.2360383000, 0.5871254000, 1.5044088000", \ - "0.0242471000, 0.0315323000, 0.0507912000, 0.1017696000, 0.2364147000, 0.5893364000, 1.5088013000", \ - "0.0243483000, 0.0315297000, 0.0507503000, 0.1015993000, 0.2363386000, 0.5877164000, 1.5062632000", \ - "0.0243165000, 0.0315250000, 0.0508146000, 0.1018857000, 0.2354560000, 0.5882609000, 1.5016127000", \ - "0.0243646000, 0.0316093000, 0.0507361000, 0.1019537000, 0.2363437000, 0.5867514000, 1.4963196000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s25_2") { - leakage_power () { - value : 0.0055573000; - when : "A"; - } - leakage_power () { - value : 0.0043928000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0049750230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0022090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020910000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023270000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0317599000, 0.0304441000, 0.0267952000, 0.0150108000, -0.021995500, -0.131117300, -0.448014600", \ - "0.0315785000, 0.0302522000, 0.0265952000, 0.0148156000, -0.022177500, -0.131308900, -0.448183600", \ - "0.0313321000, 0.0300058000, 0.0263490000, 0.0145722000, -0.022426800, -0.131537600, -0.448439100", \ - "0.0310685000, 0.0297869000, 0.0260954000, 0.0142889000, -0.022659700, -0.131811100, -0.448757500", \ - "0.0308656000, 0.0295549000, 0.0258755000, 0.0141247000, -0.022898500, -0.131995800, -0.448874400", \ - "0.0312514000, 0.0297809000, 0.0257913000, 0.0142840000, -0.022735400, -0.131814100, -0.448715500", \ - "0.0336536000, 0.0322035000, 0.0279042000, 0.0154088000, -0.021717700, -0.130511200, -0.447390200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162100, 0.0354480400, 0.1028603000, 0.2984718000"); - values("0.0281218000, 0.0298910000, 0.0347636000, 0.0480748000, 0.0853590000, 0.1933231000, 0.5094841000", \ - "0.0278924000, 0.0296553000, 0.0345334000, 0.0478561000, 0.0851280000, 0.1929841000, 0.5069158000", \ - "0.0275714000, 0.0293173000, 0.0342208000, 0.0474564000, 0.0848213000, 0.1925054000, 0.5065460000", \ - "0.0271444000, 0.0289157000, 0.0338000000, 0.0470046000, 0.0843398000, 0.1922992000, 0.5033316000", \ - "0.0268840000, 0.0286377000, 0.0334683000, 0.0467253000, 0.0840784000, 0.1927716000, 0.5057107000", \ - "0.0277897000, 0.0294378000, 0.0340218000, 0.0469699000, 0.0842959000, 0.1921814000, 0.5062916000", \ - "0.0290598000, 0.0306620000, 0.0353267000, 0.0486441000, 0.0861095000, 0.1943192000, 0.5057790000"); - } - } - max_capacitance : 0.2984720000; - max_transition : 1.5053620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.2320593000, 0.2383253000, 0.2526334000, 0.2830350000, 0.3517334000, 0.5317689000, 1.0493246000", \ - "0.2372284000, 0.2434730000, 0.2577819000, 0.2881924000, 0.3568618000, 0.5369358000, 1.0540786000", \ - "0.2500241000, 0.2562689000, 0.2705771000, 0.3009871000, 0.3696684000, 0.5497339000, 1.0672416000", \ - "0.2801764000, 0.2864337000, 0.3007224000, 0.3311670000, 0.3997842000, 0.5798260000, 1.0980243000", \ - "0.3343337000, 0.3405662000, 0.3547331000, 0.3852631000, 0.4538654000, 0.6340705000, 1.1513958000", \ - "0.4165880000, 0.4227996000, 0.4370845000, 0.4675142000, 0.5360875000, 0.7163538000, 1.2339938000", \ - "0.5405628000, 0.5468255000, 0.5610837000, 0.5914735000, 0.6601863000, 0.8402026000, 1.3573483000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.2221131000, 0.2273998000, 0.2400569000, 0.2705993000, 0.3521583000, 0.5864022000, 1.2655308000", \ - "0.2262701000, 0.2315608000, 0.2441429000, 0.2746914000, 0.3560859000, 0.5894558000, 1.2687759000", \ - "0.2368684000, 0.2421244000, 0.2548019000, 0.2852918000, 0.3670468000, 0.6005322000, 1.2797735000", \ - "0.2607615000, 0.2660432000, 0.2786604000, 0.3090888000, 0.3905835000, 0.6241483000, 1.3037266000", \ - "0.2986053000, 0.3038854000, 0.3164471000, 0.3469339000, 0.4285429000, 0.6620636000, 1.3392635000", \ - "0.3496491000, 0.3549350000, 0.3675044000, 0.3980363000, 0.4795027000, 0.7137165000, 1.3898053000", \ - "0.4120860000, 0.4173387000, 0.4300120000, 0.4605727000, 0.5423256000, 0.7764178000, 1.4518068000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0242260000, 0.0284228000, 0.0394207000, 0.0667045000, 0.1429071000, 0.3782578000, 1.0741625000", \ - "0.0242298000, 0.0285776000, 0.0392148000, 0.0666628000, 0.1429783000, 0.3770990000, 1.0798112000", \ - "0.0242294000, 0.0285767000, 0.0392320000, 0.0666846000, 0.1429488000, 0.3774675000, 1.0792035000", \ - "0.0244708000, 0.0288439000, 0.0392187000, 0.0669041000, 0.1427183000, 0.3778130000, 1.0674157000", \ - "0.0245026000, 0.0288519000, 0.0394102000, 0.0668041000, 0.1430945000, 0.3762459000, 1.0786936000", \ - "0.0243862000, 0.0285559000, 0.0396617000, 0.0668433000, 0.1428747000, 0.3785981000, 1.0686014000", \ - "0.0245195000, 0.0289031000, 0.0393937000, 0.0669342000, 0.1430542000, 0.3766722000, 1.0679359000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014508600, 0.0042099900, 0.0122162000, 0.0354480000, 0.1028600000, 0.2984720000"); - values("0.0194055000, 0.0239085000, 0.0367551000, 0.0744424000, 0.1884572000, 0.5240126000, 1.5049735000", \ - "0.0193849000, 0.0239102000, 0.0368279000, 0.0744064000, 0.1882490000, 0.5245436000, 1.5053624000", \ - "0.0192988000, 0.0240084000, 0.0368316000, 0.0745036000, 0.1884740000, 0.5233376000, 1.5045146000", \ - "0.0192767000, 0.0238896000, 0.0367765000, 0.0745278000, 0.1881726000, 0.5246377000, 1.4996213000", \ - "0.0192646000, 0.0238405000, 0.0368498000, 0.0745383000, 0.1884086000, 0.5235498000, 1.5034985000", \ - "0.0192983000, 0.0238955000, 0.0368661000, 0.0745125000, 0.1878626000, 0.5245513000, 1.5019068000", \ - "0.0193725000, 0.0240205000, 0.0368429000, 0.0744872000, 0.1884070000, 0.5239245000, 1.4957389000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s50_1") { - leakage_power () { - value : 0.0044360000; - when : "A"; - } - leakage_power () { - value : 0.0033888000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0039124260; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020550000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022860000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0356694000, 0.0347865000, 0.0321712000, 0.0242457000, 0.0015850000, -0.058454100, -0.214946200", \ - "0.0355259000, 0.0346390000, 0.0320273000, 0.0241081000, 0.0014384000, -0.058631700, -0.215092400", \ - "0.0353066000, 0.0344061000, 0.0318337000, 0.0238498000, 0.0011742000, -0.058862000, -0.215338600", \ - "0.0350185000, 0.0341747000, 0.0315360000, 0.0235914000, 0.0009471000, -0.059154700, -0.215592400", \ - "0.0347329000, 0.0338543000, 0.0312172000, 0.0232650000, 0.0005983000, -0.059462200, -0.215920500", \ - "0.0347417000, 0.0338365000, 0.0312608000, 0.0233159000, 0.0006236000, -0.059419100, -0.215908400", \ - "0.0377215000, 0.0364629000, 0.0332317000, 0.0245921000, 0.0019215000, -0.058052200, -0.214495300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0291934000, 0.0309049000, 0.0351352000, 0.0448053000, 0.0677513000, 0.1266838000, 0.2824883000", \ - "0.0290784000, 0.0308061000, 0.0350471000, 0.0446335000, 0.0676203000, 0.1266248000, 0.2810716000", \ - "0.0287823000, 0.0305020000, 0.0347651000, 0.0443399000, 0.0673336000, 0.1263268000, 0.2820978000", \ - "0.0283122000, 0.0300352000, 0.0343012000, 0.0438814000, 0.0668363000, 0.1258999000, 0.2816289000", \ - "0.0277581000, 0.0294924000, 0.0337668000, 0.0433700000, 0.0663719000, 0.1252529000, 0.2811110000", \ - "0.0278175000, 0.0295314000, 0.0338087000, 0.0434701000, 0.0664175000, 0.1259060000, 0.2798105000", \ - "0.0310595000, 0.0323685000, 0.0358129000, 0.0447211000, 0.0672502000, 0.1261994000, 0.2821123000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.4953150000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.3773694000, 0.3866315000, 0.4059351000, 0.4460350000, 0.5308621000, 0.7307884000, 1.2462394000", \ - "0.3827907000, 0.3920035000, 0.4113206000, 0.4514379000, 0.5363058000, 0.7363902000, 1.2523417000", \ - "0.3957985000, 0.4050356000, 0.4246235000, 0.4643653000, 0.5490737000, 0.7493524000, 1.2642087000", \ - "0.4264131000, 0.4354225000, 0.4550432000, 0.4950519000, 0.5798348000, 0.7797263000, 1.2956545000", \ - "0.4899625000, 0.4991952000, 0.5187372000, 0.5585674000, 0.6433798000, 0.8431870000, 1.3596501000", \ - "0.5922047000, 0.6013856000, 0.6209706000, 0.6609322000, 0.7456171000, 0.9457167000, 1.4619773000", \ - "0.7490191000, 0.7582726000, 0.7778595000, 0.8177564000, 0.9025245000, 1.1023615000, 1.6169032000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.4338853000, 0.4419386000, 0.4598301000, 0.4994158000, 0.5958226000, 0.8412734000, 1.4799054000", \ - "0.4382267000, 0.4463970000, 0.4642392000, 0.5037932000, 0.6002258000, 0.8456745000, 1.4838808000", \ - "0.4483291000, 0.4564497000, 0.4743768000, 0.5139720000, 0.6104150000, 0.8558570000, 1.4945366000", \ - "0.4716155000, 0.4797333000, 0.4976726000, 0.5372944000, 0.6337137000, 0.8791722000, 1.5180681000", \ - "0.5163753000, 0.5245345000, 0.5424525000, 0.5822786000, 0.6784374000, 0.9238412000, 1.5635842000", \ - "0.5815561000, 0.5897093000, 0.6075742000, 0.6472572000, 0.7434043000, 0.9887656000, 1.6259988000", \ - "0.6654859000, 0.6735275000, 0.6914279000, 0.7310315000, 0.8274398000, 1.0729262000, 1.7124713000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0316835000, 0.0388641000, 0.0549857000, 0.0928791000, 0.1875223000, 0.4420750000, 1.1274486000", \ - "0.0316710000, 0.0389587000, 0.0552536000, 0.0928749000, 0.1869992000, 0.4419652000, 1.1307008000", \ - "0.0320343000, 0.0387162000, 0.0552029000, 0.0931895000, 0.1868753000, 0.4420961000, 1.1277218000", \ - "0.0316108000, 0.0392974000, 0.0548875000, 0.0928749000, 0.1875972000, 0.4425213000, 1.1285571000", \ - "0.0319514000, 0.0388730000, 0.0546436000, 0.0931587000, 0.1873998000, 0.4437640000, 1.1342893000", \ - "0.0320745000, 0.0388654000, 0.0551964000, 0.0929497000, 0.1874806000, 0.4441730000, 1.1316580000", \ - "0.0322273000, 0.0391140000, 0.0546263000, 0.0930356000, 0.1875851000, 0.4402832000, 1.1261767000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0276344000, 0.0351738000, 0.0537110000, 0.1024539000, 0.2339757000, 0.5807068000, 1.4935095000", \ - "0.0276508000, 0.0351528000, 0.0536777000, 0.1026704000, 0.2336994000, 0.5802373000, 1.4923178000", \ - "0.0276189000, 0.0351725000, 0.0537572000, 0.1025695000, 0.2340395000, 0.5807012000, 1.4946661000", \ - "0.0275801000, 0.0351757000, 0.0537524000, 0.1025093000, 0.2340426000, 0.5808007000, 1.4953152000", \ - "0.0276200000, 0.0351283000, 0.0537263000, 0.1024870000, 0.2343969000, 0.5810189000, 1.4948855000", \ - "0.0276904000, 0.0350172000, 0.0536907000, 0.1024864000, 0.2343737000, 0.5812389000, 1.4898336000", \ - "0.0277196000, 0.0351690000, 0.0537398000, 0.1025453000, 0.2341415000, 0.5807450000, 1.4922109000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkdlybuf4s50_2") { - leakage_power () { - value : 0.0049600000; - when : "A"; - } - leakage_power () { - value : 0.0037643000; - when : "!A"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0043621410; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020480000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022780000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0383701000, 0.0369668000, 0.0333379000, 0.0221214000, -0.013492500, -0.120477300, -0.431155300", \ - "0.0382382000, 0.0368254000, 0.0331611000, 0.0220014000, -0.013631800, -0.120616400, -0.431295200", \ - "0.0380825000, 0.0366625000, 0.0330077000, 0.0218009000, -0.013858400, -0.120894700, -0.431581500", \ - "0.0377203000, 0.0363170000, 0.0326893000, 0.0214688000, -0.014145900, -0.121132200, -0.431806200", \ - "0.0373916000, 0.0359934000, 0.0323341000, 0.0211362000, -0.014487000, -0.121473700, -0.432128200", \ - "0.0376830000, 0.0362956000, 0.0326903000, 0.0215237000, -0.014131300, -0.121148100, -0.431675500", \ - "0.0410555000, 0.0395205000, 0.0353160000, 0.0227424000, -0.013615300, -0.120470000, -0.431137400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0343124000, 0.0360471000, 0.0411531000, 0.0551321000, 0.0923919000, 0.1982947000, 0.5052354000", \ - "0.0341649000, 0.0359164000, 0.0410359000, 0.0549152000, 0.0922051000, 0.1981304000, 0.5050724000", \ - "0.0338678000, 0.0356237000, 0.0407398000, 0.0546185000, 0.0918980000, 0.1978081000, 0.5046376000", \ - "0.0333774000, 0.0351298000, 0.0402474000, 0.0541272000, 0.0914148000, 0.1973356000, 0.5042507000", \ - "0.0329133000, 0.0346620000, 0.0398161000, 0.0536982000, 0.0909423000, 0.1968682000, 0.5058711000", \ - "0.0328070000, 0.0345700000, 0.0396984000, 0.0536547000, 0.0909280000, 0.1968555000, 0.5037660000", \ - "0.0360148000, 0.0376103000, 0.0422299000, 0.0552015000, 0.0916385000, 0.1975417000, 0.5046604000"); - } - } - max_capacitance : 0.2929790000; - max_transition : 1.4962560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.4359881000, 0.4447042000, 0.4638161000, 0.5023029000, 0.5810699000, 0.7654710000, 1.2724614000", \ - "0.4414019000, 0.4501133000, 0.4692197000, 0.5077238000, 0.5864321000, 0.7709011000, 1.2778396000", \ - "0.4543728000, 0.4630956000, 0.4821782000, 0.5205568000, 0.5994980000, 0.7840965000, 1.2901378000", \ - "0.4850239000, 0.4937432000, 0.5128555000, 0.5513426000, 0.6300983000, 0.8144980000, 1.3214930000", \ - "0.5481747000, 0.5569677000, 0.5760386000, 0.6144626000, 0.6931171000, 0.8776495000, 1.3844806000", \ - "0.6499350000, 0.6582659000, 0.6773764000, 0.7156109000, 0.7947975000, 0.9794399000, 1.4850584000", \ - "0.8045387000, 0.8132747000, 0.8321545000, 0.8705885000, 0.9493204000, 1.1341575000, 1.6407440000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.4516314000, 0.4587200000, 0.4748357000, 0.5100185000, 0.5951438000, 0.8296256000, 1.5039497000", \ - "0.4560478000, 0.4631880000, 0.4792637000, 0.5144637000, 0.5996160000, 0.8341140000, 1.5112789000", \ - "0.4662508000, 0.4733881000, 0.4894690000, 0.5246694000, 0.6098118000, 0.8443092000, 1.5215081000", \ - "0.4896086000, 0.4967469000, 0.5128262000, 0.5480259000, 0.6331731000, 0.8676689000, 1.5447855000", \ - "0.5342555000, 0.5413868000, 0.5575027000, 0.5926842000, 0.6779026000, 0.9126911000, 1.5883977000", \ - "0.5991040000, 0.6062543000, 0.6223271000, 0.6575255000, 0.7427706000, 0.9773010000, 1.6537411000", \ - "0.6815608000, 0.6886974000, 0.7048143000, 0.7400265000, 0.8252534000, 1.0601161000, 1.7340727000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0354654000, 0.0410010000, 0.0542620000, 0.0827060000, 0.1594262000, 0.3782999000, 1.0458977000", \ - "0.0354552000, 0.0410202000, 0.0535460000, 0.0829017000, 0.1594933000, 0.3785375000, 1.0464409000", \ - "0.0356161000, 0.0412680000, 0.0542871000, 0.0827740000, 0.1596412000, 0.3784040000, 1.0553443000", \ - "0.0354643000, 0.0410053000, 0.0542621000, 0.0827078000, 0.1594320000, 0.3783340000, 1.0452813000", \ - "0.0357671000, 0.0411731000, 0.0536928000, 0.0838031000, 0.1595595000, 0.3782802000, 1.0454534000", \ - "0.0354258000, 0.0411118000, 0.0542381000, 0.0830443000, 0.1593943000, 0.3787758000, 1.0502140000", \ - "0.0354288000, 0.0410975000, 0.0538718000, 0.0831152000, 0.1591991000, 0.3767684000, 1.0475598000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0252296000, 0.0307799000, 0.0444623000, 0.0816741000, 0.1924377000, 0.5232896000, 1.4950523000", \ - "0.0251479000, 0.0307195000, 0.0444338000, 0.0817618000, 0.1926058000, 0.5243724000, 1.4953667000", \ - "0.0251469000, 0.0307173000, 0.0444385000, 0.0817660000, 0.1926023000, 0.5243620000, 1.4955474000", \ - "0.0251478000, 0.0307205000, 0.0444366000, 0.0817646000, 0.1925927000, 0.5243800000, 1.4953231000", \ - "0.0251663000, 0.0306469000, 0.0444545000, 0.0817529000, 0.1925081000, 0.5236723000, 1.4962557000", \ - "0.0251230000, 0.0305296000, 0.0443785000, 0.0817538000, 0.1927955000, 0.5241079000, 1.4956910000", \ - "0.0251971000, 0.0307249000, 0.0444955000, 0.0818072000, 0.1926417000, 0.5242277000, 1.4928627000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinv_1") { - leakage_power () { - value : 0.0028987000; - when : "A"; - } - leakage_power () { - value : 0.0002364000; - when : "!A"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__clkinv"; - cell_leakage_power : 0.0015675820; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0030770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029030000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0032510000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("-0.004254200, -0.005376300, -0.008760700, -0.018465200, -0.045110300, -0.117093800, -0.311005900", \ - "-0.004705100, -0.005827400, -0.009113800, -0.018663100, -0.045227500, -0.117138100, -0.311018900", \ - "-0.005060200, -0.006253000, -0.009572800, -0.019034500, -0.045399300, -0.117211200, -0.311044000", \ - "-0.005183600, -0.006460500, -0.009945000, -0.019435100, -0.045699800, -0.117372900, -0.311121700", \ - "-0.004849100, -0.006215900, -0.009995900, -0.019798100, -0.046107100, -0.117642800, -0.311263100", \ - "-0.003924000, -0.005436700, -0.009358600, -0.019326400, -0.046188200, -0.117956500, -0.311455800", \ - "-0.001238300, -0.003405500, -0.007539200, -0.018105800, -0.045332000, -0.117606000, -0.311517800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0107401000, 0.0122870000, 0.0161564000, 0.0261613000, 0.0527221000, 0.1236883000, 0.3173350000", \ - "0.0104921000, 0.0120470000, 0.0159431000, 0.0260541000, 0.0525332000, 0.1240475000, 0.3173706000", \ - "0.0103535000, 0.0118689000, 0.0156721000, 0.0257812000, 0.0524659000, 0.1243616000, 0.3164176000", \ - "0.0103376000, 0.0118422000, 0.0155225000, 0.0255704000, 0.0520343000, 0.1238096000, 0.3160199000", \ - "0.0105936000, 0.0118966000, 0.0155513000, 0.0255054000, 0.0520953000, 0.1233491000, 0.3157957000", \ - "0.0113758000, 0.0122160000, 0.0161796000, 0.0253998000, 0.0522247000, 0.1235751000, 0.3164786000", \ - "0.0135256000, 0.0147491000, 0.0181029000, 0.0270342000, 0.0530916000, 0.1234263000, 0.3158540000"); - } - } - max_capacitance : 0.1904400000; - max_transition : 1.4907830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0241554000, 0.0298103000, 0.0438860000, 0.0794526000, 0.1734056000, 0.4266369000, 1.1077180000", \ - "0.0278767000, 0.0334803000, 0.0476880000, 0.0837578000, 0.1786628000, 0.4303806000, 1.1094801000", \ - "0.0376465000, 0.0440447000, 0.0579757000, 0.0945424000, 0.1892714000, 0.4455122000, 1.1259143000", \ - "0.0520658000, 0.0618247000, 0.0815335000, 0.1204915000, 0.2164326000, 0.4697517000, 1.1443705000", \ - "0.0707744000, 0.0857707000, 0.1169704000, 0.1755665000, 0.2780551000, 0.5319993000, 1.2095068000", \ - "0.0933027000, 0.1161096000, 0.1639385000, 0.2536688000, 0.4079394000, 0.6766814000, 1.3579167000", \ - "0.1181818000, 0.1519682000, 0.2230063000, 0.3589587000, 0.5963642000, 0.9895124000, 1.6937405000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0173211000, 0.0209827000, 0.0301774000, 0.0539531000, 0.1162420000, 0.2841294000, 0.7369781000", \ - "0.0228190000, 0.0264154000, 0.0355887000, 0.0594053000, 0.1222859000, 0.2918918000, 0.7428970000", \ - "0.0332379000, 0.0386218000, 0.0487820000, 0.0721595000, 0.1355147000, 0.3027018000, 0.7596375000", \ - "0.0479160000, 0.0566713000, 0.0738055000, 0.1036936000, 0.1658719000, 0.3347418000, 0.7890523000", \ - "0.0676104000, 0.0818619000, 0.1103192000, 0.1594681000, 0.2385659000, 0.4060275000, 0.8604862000", \ - "0.0937306000, 0.1154594000, 0.1610148000, 0.2424121000, 0.3715618000, 0.5718877000, 1.0199016000", \ - "0.1267940000, 0.1598127000, 0.2296432000, 0.3575344000, 0.5722002000, 0.8957089000, 1.4063141000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0138175000, 0.0201100000, 0.0374332000, 0.0837844000, 0.2084849000, 0.5427905000, 1.4534830000", \ - "0.0136655000, 0.0202732000, 0.0371725000, 0.0835321000, 0.2081415000, 0.5465129000, 1.4575395000", \ - "0.0184022000, 0.0229179000, 0.0381299000, 0.0839272000, 0.2097561000, 0.5441556000, 1.4626605000", \ - "0.0303540000, 0.0370188000, 0.0513983000, 0.0878259000, 0.2080048000, 0.5460878000, 1.4521702000", \ - "0.0507284000, 0.0611052000, 0.0822638000, 0.1226141000, 0.2191967000, 0.5479680000, 1.4558104000", \ - "0.0849603000, 0.1011378000, 0.1353136000, 0.1928431000, 0.2982353000, 0.5649992000, 1.4526159000", \ - "0.1471776000, 0.1724496000, 0.2231269000, 0.3128515000, 0.4668217000, 0.7286866000, 1.4907834000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0104362000, 0.0151209000, 0.0276810000, 0.0615003000, 0.1521654000, 0.3960007000, 1.0534302000", \ - "0.0110689000, 0.0151874000, 0.0276031000, 0.0614634000, 0.1525232000, 0.3979924000, 1.0522682000", \ - "0.0180743000, 0.0213102000, 0.0301583000, 0.0612463000, 0.1522122000, 0.3960008000, 1.0552412000", \ - "0.0303416000, 0.0354302000, 0.0461564000, 0.0699014000, 0.1520825000, 0.3964254000, 1.0524130000", \ - "0.0523110000, 0.0604462000, 0.0771281000, 0.1081665000, 0.1710228000, 0.3951927000, 1.0519798000", \ - "0.0894715000, 0.1038959000, 0.1303044000, 0.1782385000, 0.2559946000, 0.4329671000, 1.0500332000", \ - "0.1542095000, 0.1752656000, 0.2207036000, 0.3000446000, 0.4258260000, 0.6251449000, 1.1136533000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinv_16") { - leakage_power () { - value : 0.0128005000; - when : "A"; - } - leakage_power () { - value : 0.0100213000; - when : "!A"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__clkinv"; - cell_leakage_power : 0.0114109000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0377460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0350970000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0403950000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0020461390, 0.0083733670, 0.0342661400, 0.1402265000, 0.5738459000, 2.3483370000"); - values("-0.044155400, -0.045845900, -0.053596500, -0.090386500, -0.258416900, -0.959729100, -3.833611400", \ - "-0.049387200, -0.051270700, -0.059167600, -0.094738100, -0.260068400, -0.960085200, -3.834029000", \ - "-0.053872800, -0.055868200, -0.064586600, -0.100848000, -0.263506900, -0.961135600, -3.834264100", \ - "-0.055216600, -0.057625300, -0.067178100, -0.105875500, -0.268930400, -0.963224600, -3.834778800", \ - "-0.052282800, -0.055049700, -0.065539300, -0.107426200, -0.274518000, -0.967311700, -3.836196600", \ - "-0.043162100, -0.045918800, -0.056825200, -0.099801700, -0.272653100, -0.972026000, -3.838103500", \ - "-0.018928100, -0.022456400, -0.034800600, -0.080452100, -0.260137800, -0.969545000, -3.839632700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0020461390, 0.0083733670, 0.0342661400, 0.1402265000, 0.5738459000, 2.3483370000"); - values("0.1187620000, 0.1220310000, 0.1348486000, 0.1813914000, 0.3545976000, 1.0522997000, 3.9001995000", \ - "0.1167562000, 0.1197837000, 0.1318742000, 0.1782319000, 0.3534478000, 1.0515270000, 3.8818205000", \ - "0.1157233000, 0.1184506000, 0.1296284000, 0.1745509000, 0.3503438000, 1.0504535000, 3.8828570000", \ - "0.1167191000, 0.1193848000, 0.1297059000, 0.1724648000, 0.3458485000, 1.0479412000, 3.8834386000", \ - "0.1191543000, 0.1215482000, 0.1314572000, 0.1726371000, 0.3443291000, 1.0424021000, 3.8808743000", \ - "0.1291652000, 0.1356503000, 0.1419080000, 0.1805943000, 0.3491355000, 1.0400104000, 3.8739341000", \ - "0.1570078000, 0.1587921000, 0.1662107000, 0.2000774000, 0.3583198000, 1.0480747000, 3.8797397000"); - } - } - max_capacitance : 2.3483370000; - max_transition : 1.4995270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020461400, 0.0083733700, 0.0342661000, 0.1402270000, 0.5738460000, 2.3483400000"); - values("0.0247696000, 0.0257162000, 0.0294088000, 0.0425687000, 0.0910152000, 0.2849100000, 1.0770099000", \ - "0.0277483000, 0.0286874000, 0.0323207000, 0.0457487000, 0.0947924000, 0.2887799000, 1.0800612000", \ - "0.0352556000, 0.0364640000, 0.0409054000, 0.0549318000, 0.1047756000, 0.2992526000, 1.0919022000", \ - "0.0439113000, 0.0458239000, 0.0526580000, 0.0740601000, 0.1286966000, 0.3240472000, 1.1164534000", \ - "0.0504977000, 0.0534765000, 0.0641644000, 0.0972933000, 0.1795768000, 0.3826388000, 1.1778333000", \ - "0.0468002000, 0.0512118000, 0.0676040000, 0.1185987000, 0.2457924000, 0.5181126000, 1.3106261000", \ - "0.0134034000, 0.0199368000, 0.0445759000, 0.1210000000, 0.3162700000, 0.7370576000, 1.6269109000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020461400, 0.0083733700, 0.0342661000, 0.1402270000, 0.5738460000, 2.3483400000"); - values("0.0213260000, 0.0222852000, 0.0259557000, 0.0388156000, 0.0859854000, 0.2745695000, 1.0488995000", \ - "0.0264047000, 0.0273046000, 0.0308290000, 0.0435966000, 0.0912839000, 0.2803190000, 1.0500029000", \ - "0.0378483000, 0.0390718000, 0.0434691000, 0.0565345000, 0.1040490000, 0.2935565000, 1.0634398000", \ - "0.0551743000, 0.0571168000, 0.0641101000, 0.0845440000, 0.1353767000, 0.3255565000, 1.0989692000", \ - "0.0822009000, 0.0852525000, 0.0962975000, 0.1292325000, 0.2062104000, 0.3970348000, 1.1655469000", \ - "0.1271747000, 0.1318205000, 0.1488000000, 0.2001968000, 0.3236804000, 0.5700317000, 1.3365988000", \ - "0.2083795000, 0.2150153000, 0.2393439000, 0.3171056000, 0.5100367000, 0.9053095000, 1.7333922000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020461400, 0.0083733700, 0.0342661000, 0.1402270000, 0.5738460000, 2.3483400000"); - values("0.0105051000, 0.0114223000, 0.0152351000, 0.0310737000, 0.0963359000, 0.3640606000, 1.4558795000", \ - "0.0106291000, 0.0115419000, 0.0153145000, 0.0311628000, 0.0965330000, 0.3633117000, 1.4565579000", \ - "0.0152381000, 0.0161460000, 0.0190719000, 0.0323033000, 0.0963843000, 0.3632760000, 1.4570883000", \ - "0.0249078000, 0.0262631000, 0.0308719000, 0.0460988000, 0.0996026000, 0.3631855000, 1.4573421000", \ - "0.0425321000, 0.0443263000, 0.0519903000, 0.0742112000, 0.1316696000, 0.3657277000, 1.4602991000", \ - "0.0722861000, 0.0754531000, 0.0871602000, 0.1229746000, 0.2065147000, 0.4175319000, 1.4566858000", \ - "0.1278219000, 0.1331598000, 0.1500382000, 0.2035308000, 0.3322073000, 0.6115940000, 1.4995273000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020461400, 0.0083733700, 0.0342661000, 0.1402270000, 0.5738460000, 2.3483400000"); - values("0.0116231000, 0.0124973000, 0.0163877000, 0.0326151000, 0.0994180000, 0.3731503000, 1.4885928000", \ - "0.0118522000, 0.0128002000, 0.0165745000, 0.0326613000, 0.0992288000, 0.3727092000, 1.4848481000", \ - "0.0178209000, 0.0183984000, 0.0208602000, 0.0338631000, 0.0994157000, 0.3725542000, 1.4839050000", \ - "0.0283418000, 0.0295514000, 0.0338203000, 0.0478223000, 0.1013612000, 0.3726913000, 1.4836297000", \ - "0.0476189000, 0.0494700000, 0.0563082000, 0.0765839000, 0.1296655000, 0.3716293000, 1.4821506000", \ - "0.0805879000, 0.0832546000, 0.0943245000, 0.1274468000, 0.2034673000, 0.4068251000, 1.4829811000", \ - "0.1399888000, 0.1442299000, 0.1599215000, 0.2114923000, 0.3351883000, 0.5854802000, 1.4978252000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinv_2") { - leakage_power () { - value : 0.0071803000; - when : "A"; - } - leakage_power () { - value : 0.0006400000; - when : "!A"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__clkinv"; - cell_leakage_power : 0.0039101590; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0051740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0048320000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0055160000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015205570, 0.0046241860, 0.0140626800, 0.0427662000, 0.1300569000, 0.3955177000"); - values("-0.005626100, -0.006944100, -0.011401800, -0.026210600, -0.072515000, -0.213823100, -0.643890500", \ - "-0.006363800, -0.007709500, -0.012101800, -0.026629100, -0.072657100, -0.213898700, -0.643888700", \ - "-0.006976000, -0.008423300, -0.012898700, -0.027275300, -0.072960100, -0.214020200, -0.643929300", \ - "-0.007215400, -0.008740800, -0.013424800, -0.028031400, -0.073507700, -0.214229200, -0.643999300", \ - "-0.006604500, -0.008266700, -0.013237100, -0.028565600, -0.074147900, -0.214633600, -0.644184000", \ - "-0.004715200, -0.006769800, -0.012185000, -0.027535900, -0.074189200, -0.215113000, -0.644452600", \ - "-0.000478100, -0.003247500, -0.009043900, -0.025470900, -0.072778900, -0.214272700, -0.644308000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015205570, 0.0046241860, 0.0140626800, 0.0427662000, 0.1300569000, 0.3955177000"); - values("0.0165086000, 0.0184551000, 0.0238667000, 0.0393375000, 0.0856142000, 0.2242671000, 0.6486000000", \ - "0.0161433000, 0.0180006000, 0.0234062000, 0.0390431000, 0.0854763000, 0.2258633000, 0.6541154000", \ - "0.0159517000, 0.0177270000, 0.0229668000, 0.0386573000, 0.0850335000, 0.2255695000, 0.6508207000", \ - "0.0159688000, 0.0178384000, 0.0229482000, 0.0381563000, 0.0845243000, 0.2248691000, 0.6515076000", \ - "0.0164029000, 0.0179983000, 0.0228823000, 0.0381464000, 0.0843411000, 0.2234949000, 0.6526424000", \ - "0.0171291000, 0.0185442000, 0.0231736000, 0.0378119000, 0.0847043000, 0.2233757000, 0.6472325000", \ - "0.0214730000, 0.0227459000, 0.0277334000, 0.0411663000, 0.0857538000, 0.2244057000, 0.6453278000"); - } - } - max_capacitance : 0.3955180000; - max_transition : 1.4982580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0195011000, 0.0228918000, 0.0323994000, 0.0594117000, 0.1384928000, 0.3778522000, 1.1063067000", \ - "0.0234002000, 0.0267152000, 0.0362482000, 0.0635184000, 0.1429297000, 0.3824774000, 1.1106389000", \ - "0.0318669000, 0.0362711000, 0.0468159000, 0.0738283000, 0.1545038000, 0.3938716000, 1.1214603000", \ - "0.0427874000, 0.0496509000, 0.0660869000, 0.1001432000, 0.1805924000, 0.4217377000, 1.1510333000", \ - "0.0552463000, 0.0659529000, 0.0913576000, 0.1444127000, 0.2421235000, 0.4815611000, 1.2097062000", \ - "0.0654874000, 0.0817862000, 0.1209161000, 0.2028470000, 0.3534379000, 0.6247180000, 1.3519335000", \ - "0.0649103000, 0.0888851000, 0.1474965000, 0.2719669000, 0.5055065000, 0.9156598000, 1.6818035000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0167881000, 0.0196658000, 0.0277110000, 0.0507441000, 0.1190711000, 0.3250584000, 0.9619882000", \ - "0.0224008000, 0.0251409000, 0.0331390000, 0.0560451000, 0.1251964000, 0.3322355000, 0.9632675000", \ - "0.0328769000, 0.0370057000, 0.0465172000, 0.0692521000, 0.1379542000, 0.3458972000, 0.9719845000", \ - "0.0479342000, 0.0546703000, 0.0702439000, 0.1009530000, 0.1692303000, 0.3762842000, 1.0063872000", \ - "0.0692714000, 0.0804498000, 0.1060864000, 0.1561458000, 0.2416857000, 0.4469564000, 1.0744087000", \ - "0.1014953000, 0.1181755000, 0.1586056000, 0.2396745000, 0.3820892000, 0.6173118000, 1.2385757000", \ - "0.1521750000, 0.1768313000, 0.2375165000, 0.3637167000, 0.5925330000, 0.9696280000, 1.6240017000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0101255000, 0.0140091000, 0.0252286000, 0.0610076000, 0.1656995000, 0.4873187000, 1.4651298000", \ - "0.0103103000, 0.0138867000, 0.0253035000, 0.0602029000, 0.1657055000, 0.4854896000, 1.4575431000", \ - "0.0158248000, 0.0188962000, 0.0275220000, 0.0605450000, 0.1657416000, 0.4863829000, 1.4595007000", \ - "0.0265925000, 0.0310691000, 0.0421387000, 0.0678509000, 0.1654636000, 0.4940754000, 1.4644174000", \ - "0.0444669000, 0.0518563000, 0.0690845000, 0.1038877000, 0.1831005000, 0.4924098000, 1.4627154000", \ - "0.0756352000, 0.0871499000, 0.1159161000, 0.1677079000, 0.2676135000, 0.5170611000, 1.4732912000", \ - "0.1333658000, 0.1495429000, 0.1912969000, 0.2745460000, 0.4246446000, 0.6961144000, 1.4982583000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0099703000, 0.0134787000, 0.0241354000, 0.0564986000, 0.1550056000, 0.4512630000, 1.3552078000", \ - "0.0106629000, 0.0135978000, 0.0241178000, 0.0564957000, 0.1545403000, 0.4550134000, 1.3644410000", \ - "0.0176937000, 0.0201338000, 0.0272090000, 0.0563944000, 0.1545893000, 0.4531705000, 1.3554583000", \ - "0.0290602000, 0.0331956000, 0.0429441000, 0.0654432000, 0.1543214000, 0.4517346000, 1.3604216000", \ - "0.0494769000, 0.0562193000, 0.0712902000, 0.1021800000, 0.1725449000, 0.4518554000, 1.3593348000", \ - "0.0836734000, 0.0948874000, 0.1200107000, 0.1682429000, 0.2567938000, 0.4777464000, 1.3582662000", \ - "0.1447353000, 0.1608643000, 0.2006286000, 0.2820738000, 0.4191001000, 0.6551605000, 1.3854429000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinv_4") { - leakage_power () { - value : 0.0063418000; - when : "A"; - } - leakage_power () { - value : 0.0018948000; - when : "!A"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__clkinv"; - cell_leakage_power : 0.0041183060; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0102180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0095360000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0109000000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017037880, 0.0058057850, 0.0197836500, 0.0674142800, 0.2297192000, 0.7827856000"); - values("-0.011682600, -0.013143400, -0.018734700, -0.040267900, -0.116907800, -0.379706600, -1.275487900", \ - "-0.013090200, -0.014640000, -0.020172700, -0.041203800, -0.117281400, -0.379795700, -1.275569300", \ - "-0.014258300, -0.015962000, -0.021734300, -0.042576700, -0.117939100, -0.380031000, -1.275689500", \ - "-0.014696800, -0.016521500, -0.022662600, -0.044090800, -0.119109100, -0.380341300, -1.275785300", \ - "-0.013108700, -0.015511000, -0.022098600, -0.044916900, -0.120176700, -0.381182300, -1.276112500", \ - "-0.009961200, -0.012262500, -0.020185800, -0.043046500, -0.120435200, -0.382239000, -1.276819300", \ - "-0.002294500, -0.004400500, -0.014140900, -0.038675800, -0.117685500, -0.381129600, -1.276702300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017037880, 0.0058057850, 0.0197836500, 0.0674142800, 0.2297192000, 0.7827856000"); - values("0.0325206000, 0.0349450000, 0.0424356000, 0.0656409000, 0.1428126000, 0.4026392000, 1.2889252000", \ - "0.0318490000, 0.0341155000, 0.0415030000, 0.0649474000, 0.1424615000, 0.4007965000, 1.2923360000", \ - "0.0314567000, 0.0335913000, 0.0407329000, 0.0642262000, 0.1420540000, 0.4004242000, 1.2890338000", \ - "0.0315527000, 0.0339006000, 0.0405799000, 0.0633727000, 0.1405276000, 0.4010623000, 1.2901502000", \ - "0.0329753000, 0.0351105000, 0.0415046000, 0.0641511000, 0.1403538000, 0.4009049000, 1.2873505000", \ - "0.0342201000, 0.0363253000, 0.0426448000, 0.0645736000, 0.1413715000, 0.4005528000, 1.2875600000", \ - "0.0413073000, 0.0427385000, 0.0484078000, 0.0690694000, 0.1432920000, 0.4058210000, 1.2919266000"); - } - } - max_capacitance : 0.7827860000; - max_transition : 1.4996850000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0185589000, 0.0206206000, 0.0271811000, 0.0474953000, 0.1132965000, 0.3352268000, 1.0925765000", \ - "0.0224105000, 0.0244184000, 0.0309703000, 0.0514176000, 0.1175760000, 0.3397478000, 1.0971299000", \ - "0.0299192000, 0.0328302000, 0.0409952000, 0.0617039000, 0.1283769000, 0.3510398000, 1.1080533000", \ - "0.0388834000, 0.0433898000, 0.0559624000, 0.0858347000, 0.1539251000, 0.3775338000, 1.1360634000", \ - "0.0472984000, 0.0542374000, 0.0738286000, 0.1198858000, 0.2128829000, 0.4373556000, 1.1934191000", \ - "0.0484620000, 0.0593570000, 0.0894413000, 0.1608767000, 0.3052937000, 0.5779796000, 1.3359052000", \ - "0.0278356000, 0.0440061000, 0.0885083000, 0.1978393000, 0.4227213000, 0.8405716000, 1.6567576000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0170208000, 0.0189927000, 0.0250756000, 0.0439411000, 0.1066992000, 0.3163114000, 1.0303773000", \ - "0.0227300000, 0.0245489000, 0.0305208000, 0.0493780000, 0.1122055000, 0.3238016000, 1.0448669000", \ - "0.0336743000, 0.0365469000, 0.0441301000, 0.0630337000, 0.1253306000, 0.3347876000, 1.0488050000", \ - "0.0498946000, 0.0543736000, 0.0669235000, 0.0942201000, 0.1576034000, 0.3671975000, 1.0843725000", \ - "0.0744713000, 0.0819359000, 0.1019062000, 0.1476094000, 0.2321530000, 0.4412151000, 1.1556819000", \ - "0.1137680000, 0.1249420000, 0.1566304000, 0.2285969000, 0.3663274000, 0.6131894000, 1.3265524000", \ - "0.1807070000, 0.1977693000, 0.2448110000, 0.3565090000, 0.5810400000, 0.9757378000, 1.7244272000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0089661000, 0.0112672000, 0.0187645000, 0.0445762000, 0.1323884000, 0.4317705000, 1.4480183000", \ - "0.0092753000, 0.0112428000, 0.0187082000, 0.0444741000, 0.1322224000, 0.4336467000, 1.4479659000", \ - "0.0147923000, 0.0168957000, 0.0224167000, 0.0451334000, 0.1327441000, 0.4309568000, 1.4501909000", \ - "0.0248366000, 0.0278669000, 0.0362913000, 0.0572182000, 0.1335471000, 0.4335282000, 1.4601724000", \ - "0.0421278000, 0.0469465000, 0.0602373000, 0.0906022000, 0.1578119000, 0.4366178000, 1.4658962000", \ - "0.0731604000, 0.0803285000, 0.1009011000, 0.1478758000, 0.2415478000, 0.4701842000, 1.4707403000", \ - "0.1290069000, 0.1389024000, 0.1707310000, 0.2436602000, 0.3892208000, 0.6636490000, 1.4996847000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0095734000, 0.0118322000, 0.0195226000, 0.0457565000, 0.1351577000, 0.4378130000, 1.4687332000", \ - "0.0100801000, 0.0120140000, 0.0195511000, 0.0456994000, 0.1351455000, 0.4379076000, 1.4783735000", \ - "0.0169635000, 0.0186711000, 0.0234385000, 0.0460265000, 0.1350498000, 0.4373780000, 1.4687354000", \ - "0.0279805000, 0.0307080000, 0.0383561000, 0.0575784000, 0.1350045000, 0.4397840000, 1.4738100000", \ - "0.0477223000, 0.0523268000, 0.0642378000, 0.0927811000, 0.1559990000, 0.4368377000, 1.4726572000", \ - "0.0811319000, 0.0881936000, 0.1079307000, 0.1519479000, 0.2376396000, 0.4637174000, 1.4695677000", \ - "0.1405122000, 0.1512866000, 0.1850245000, 0.2543976000, 0.3914867000, 0.6450144000, 1.4920718000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinv_8") { - leakage_power () { - value : 0.0094544000; - when : "A"; - } - leakage_power () { - value : 0.0043300000; - when : "!A"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__clkinv"; - cell_leakage_power : 0.0068922350; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0202110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0188400000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0215810000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018729910, 0.0070161870, 0.0262825100, 0.0984537800, 0.3688060000, 1.3815400000"); - values("-0.022937700, -0.024524400, -0.031150900, -0.060026800, -0.175732700, -0.613345400, -2.252803000", \ - "-0.025712300, -0.027467100, -0.034117400, -0.062053300, -0.176480600, -0.613604500, -2.254012500", \ - "-0.028028200, -0.029894500, -0.037138700, -0.064996900, -0.178025000, -0.614130100, -2.254178600", \ - "-0.029048600, -0.031069700, -0.038743700, -0.067593300, -0.180495500, -0.615124300, -2.254633300", \ - "-0.026800900, -0.029050700, -0.037294000, -0.068960700, -0.182782000, -0.616528200, -2.254850000", \ - "-0.021342700, -0.024363100, -0.033659600, -0.065662300, -0.183555600, -0.618649000, -2.255969700", \ - "-0.006552500, -0.008745200, -0.021336400, -0.056269900, -0.177268800, -0.617989500, -2.256539100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018729910, 0.0070161870, 0.0262825100, 0.0984537800, 0.3688060000, 1.3815400000"); - values("0.0630495000, 0.0659096000, 0.0758688000, 0.1086190000, 0.2256900000, 0.6565823000, 2.2736691000", \ - "0.0617673000, 0.0644314000, 0.0740106000, 0.1073837000, 0.2241983000, 0.6563425000, 2.2726868000", \ - "0.0611556000, 0.0635938000, 0.0726154000, 0.1053682000, 0.2238251000, 0.6593237000, 2.2748890000", \ - "0.0613382000, 0.0636681000, 0.0722616000, 0.1037164000, 0.2209130000, 0.6568986000, 2.2835470000", \ - "0.0633015000, 0.0653048000, 0.0733812000, 0.1042725000, 0.2207748000, 0.6546834000, 2.2806540000", \ - "0.0650476000, 0.0670801000, 0.0745786000, 0.1045511000, 0.2219670000, 0.6527743000, 2.2752806000", \ - "0.0793989000, 0.0809641000, 0.0875143000, 0.1155077000, 0.2257769000, 0.6574567000, 2.2761687000"); - } - } - max_capacitance : 1.3815400000; - max_transition : 1.4998770000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018729900, 0.0070161900, 0.0262825000, 0.0984538000, 0.3688060000, 1.3815400000"); - values("0.0192440000, 0.0206098000, 0.0253028000, 0.0406968000, 0.0946377000, 0.2942822000, 1.0465543000", \ - "0.0229456000, 0.0242390000, 0.0288599000, 0.0447274000, 0.0989467000, 0.3003239000, 1.0447632000", \ - "0.0302668000, 0.0321359000, 0.0380752000, 0.0547223000, 0.1099780000, 0.3109701000, 1.0656681000", \ - "0.0385935000, 0.0414760000, 0.0507625000, 0.0759184000, 0.1347804000, 0.3361002000, 1.0822802000", \ - "0.0454095000, 0.0498705000, 0.0641811000, 0.1032113000, 0.1893518000, 0.3944041000, 1.1412632000", \ - "0.0436211000, 0.0504027000, 0.0722844000, 0.1326779000, 0.2665769000, 0.5344066000, 1.2798386000", \ - "0.0157523000, 0.0259368000, 0.0587664000, 0.1490291000, 0.3568910000, 0.7704869000, 1.6012225000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018729900, 0.0070161900, 0.0262825000, 0.0984538000, 0.3688060000, 1.3815400000"); - values("0.0177579000, 0.0191105000, 0.0237426000, 0.0388445000, 0.0924732000, 0.2919732000, 1.0281902000", \ - "0.0234327000, 0.0246892000, 0.0291029000, 0.0442252000, 0.0977820000, 0.2955247000, 1.0333374000", \ - "0.0345963000, 0.0364781000, 0.0422477000, 0.0576902000, 0.1114129000, 0.3103402000, 1.0587555000", \ - "0.0511016000, 0.0541050000, 0.0635857000, 0.0873279000, 0.1431687000, 0.3412164000, 1.0816088000", \ - "0.0767011000, 0.0814665000, 0.0966020000, 0.1355095000, 0.2169523000, 0.4155459000, 1.1536216000", \ - "0.1184378000, 0.1257243000, 0.1490739000, 0.2107275000, 0.3418482000, 0.5872300000, 1.3279225000", \ - "0.1925032000, 0.2029590000, 0.2371578000, 0.3317487000, 0.5409673000, 0.9351867000, 1.7217072000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018729900, 0.0070161900, 0.0262825000, 0.0984538000, 0.3688060000, 1.3815400000"); - values("0.0090220000, 0.0103905000, 0.0155407000, 0.0350839000, 0.1087736000, 0.3842276000, 1.4180845000", \ - "0.0091902000, 0.0104555000, 0.0155372000, 0.0352758000, 0.1084640000, 0.3844178000, 1.4128989000", \ - "0.0146351000, 0.0159682000, 0.0202252000, 0.0361854000, 0.1087140000, 0.3875122000, 1.4211932000", \ - "0.0242918000, 0.0262315000, 0.0325910000, 0.0503970000, 0.1111205000, 0.3831243000, 1.4173819000", \ - "0.0417013000, 0.0449549000, 0.0546593000, 0.0802167000, 0.1409364000, 0.3845405000, 1.4141629000", \ - "0.0713135000, 0.0759088000, 0.0913162000, 0.1313933000, 0.2193626000, 0.4323723000, 1.4156001000", \ - "0.1260508000, 0.1336016000, 0.1568927000, 0.2182608000, 0.3531939000, 0.6248144000, 1.4595324000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018729900, 0.0070161900, 0.0262825000, 0.0984538000, 0.3688060000, 1.3815400000"); - values("0.0099528000, 0.0113974000, 0.0168750000, 0.0375243000, 0.1145778000, 0.4032754000, 1.4828426000", \ - "0.0102969000, 0.0115634000, 0.0168654000, 0.0375163000, 0.1143545000, 0.4029649000, 1.4813722000", \ - "0.0173709000, 0.0182974000, 0.0214742000, 0.0382451000, 0.1143407000, 0.4026037000, 1.4841955000", \ - "0.0278233000, 0.0296008000, 0.0354872000, 0.0511297000, 0.1155774000, 0.4025510000, 1.4848099000", \ - "0.0476162000, 0.0504105000, 0.0593163000, 0.0827468000, 0.1408735000, 0.4016901000, 1.4848156000", \ - "0.0804163000, 0.0853350000, 0.0995451000, 0.1374595000, 0.2187090000, 0.4345558000, 1.4836434000", \ - "0.1406325000, 0.1458702000, 0.1684351000, 0.2307668000, 0.3600246000, 0.6099336000, 1.4998773000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinvlp_2") { - leakage_power () { - value : 0.0001159000; - when : "A"; - } - leakage_power () { - value : 4.4398181e-05; - when : "!A"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 8.012643e-05; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0045310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041810000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048810000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("-0.005731800, -0.006754500, -0.009794500, -0.018329400, -0.041018600, -0.100290000, -0.254560300", \ - "-0.006373100, -0.007358000, -0.010243800, -0.018570400, -0.041126300, -0.100334300, -0.254594800", \ - "-0.007009100, -0.008030900, -0.010893000, -0.019016200, -0.041343400, -0.100428700, -0.254615200", \ - "-0.007483200, -0.008589200, -0.011566200, -0.019661600, -0.041774400, -0.100652800, -0.254673100", \ - "-0.007757400, -0.008945800, -0.012037300, -0.020328300, -0.042419800, -0.101006900, -0.254861900", \ - "-0.007544200, -0.008788100, -0.012035300, -0.020805000, -0.043093000, -0.101657600, -0.255180100", \ - "-0.007256700, -0.008575000, -0.011954800, -0.020641600, -0.043484100, -0.102270600, -0.255774000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0148444000, 0.0163445000, 0.0199738000, 0.0287219000, 0.0512657000, 0.1104855000, 0.2630551000", \ - "0.0144289000, 0.0159616000, 0.0196229000, 0.0285822000, 0.0511587000, 0.1096342000, 0.2626876000", \ - "0.0140539000, 0.0155592000, 0.0191856000, 0.0282611000, 0.0513546000, 0.1094993000, 0.2626380000", \ - "0.0138510000, 0.0152954000, 0.0188699000, 0.0279890000, 0.0507177000, 0.1103149000, 0.2635070000", \ - "0.0137696000, 0.0151103000, 0.0186196000, 0.0275316000, 0.0504805000, 0.1090393000, 0.2634343000", \ - "0.0142542000, 0.0151745000, 0.0185456000, 0.0273168000, 0.0501642000, 0.1091796000, 0.2614995000", \ - "0.0135891000, 0.0150279000, 0.0184094000, 0.0266945000, 0.0499325000, 0.1089235000, 0.2611467000"); - } - } - max_capacitance : 0.1547340000; - max_transition : 1.4917990000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0387518000, 0.0455537000, 0.0616805000, 0.1005431000, 0.1999083000, 0.4546818000, 1.1213499000", \ - "0.0419455000, 0.0488453000, 0.0656349000, 0.1050643000, 0.2043910000, 0.4601986000, 1.1242635000", \ - "0.0527456000, 0.0594717000, 0.0762389000, 0.1165331000, 0.2166127000, 0.4728992000, 1.1372934000", \ - "0.0763085000, 0.0853808000, 0.1042638000, 0.1446773000, 0.2463778000, 0.5045162000, 1.1729338000", \ - "0.1099888000, 0.1247762000, 0.1555743000, 0.2108755000, 0.3139972000, 0.5722570000, 1.2447368000", \ - "0.1533545000, 0.1780827000, 0.2287579000, 0.3190363000, 0.4684705000, 0.7329474000, 1.4030879000", \ - "0.1975983000, 0.2393407000, 0.3231894000, 0.4733116000, 0.7190513000, 1.0992538000, 1.7755516000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0280131000, 0.0330608000, 0.0449848000, 0.0737911000, 0.1476402000, 0.3409681000, 0.8376198000", \ - "0.0335452000, 0.0386436000, 0.0505593000, 0.0798901000, 0.1541453000, 0.3457142000, 0.8431933000", \ - "0.0482309000, 0.0530480000, 0.0647901000, 0.0942402000, 0.1696592000, 0.3615167000, 0.8582721000", \ - "0.0755362000, 0.0834573000, 0.0992749000, 0.1292322000, 0.2040286000, 0.3977869000, 0.8977932000", \ - "0.1201865000, 0.1334894000, 0.1598962000, 0.2062327000, 0.2852343000, 0.4766770000, 0.9789803000", \ - "0.1919964000, 0.2157121000, 0.2611889000, 0.3399794000, 0.4640978000, 0.6651968000, 1.1626661000", \ - "0.3114289000, 0.3510058000, 0.4271672000, 0.5609705000, 0.7698455000, 1.0853132000, 1.5974061000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0205878000, 0.0282039000, 0.0481897000, 0.0984942000, 0.2315755000, 0.5760445000, 1.4678568000", \ - "0.0205754000, 0.0280869000, 0.0482383000, 0.0981834000, 0.2307050000, 0.5729361000, 1.4636455000", \ - "0.0208671000, 0.0280661000, 0.0479113000, 0.0987046000, 0.2314460000, 0.5749029000, 1.4688590000", \ - "0.0317295000, 0.0380347000, 0.0525854000, 0.0995783000, 0.2339200000, 0.5763214000, 1.4733305000", \ - "0.0530886000, 0.0628619000, 0.0838808000, 0.1215407000, 0.2342769000, 0.5737689000, 1.4849455000", \ - "0.0923262000, 0.1075259000, 0.1398518000, 0.1948972000, 0.2930700000, 0.5833372000, 1.4847692000", \ - "0.1632396000, 0.1892867000, 0.2389900000, 0.3240628000, 0.4716639000, 0.7229066000, 1.4917986000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0167157000, 0.0224944000, 0.0376683000, 0.0766464000, 0.1785408000, 0.4481635000, 1.1342364000", \ - "0.0165646000, 0.0223720000, 0.0374387000, 0.0765450000, 0.1781099000, 0.4424206000, 1.1302160000", \ - "0.0179496000, 0.0228064000, 0.0374070000, 0.0765110000, 0.1790599000, 0.4423817000, 1.1295949000", \ - "0.0301504000, 0.0352487000, 0.0451228000, 0.0781912000, 0.1784233000, 0.4473210000, 1.1381343000", \ - "0.0513578000, 0.0587425000, 0.0741825000, 0.1028143000, 0.1842825000, 0.4422187000, 1.1354667000", \ - "0.0919665000, 0.1030052000, 0.1271271000, 0.1699214000, 0.2453810000, 0.4558455000, 1.1326325000", \ - "0.1617202000, 0.1809713000, 0.2220150000, 0.2924139000, 0.4023225000, 0.5986179000, 1.1521833000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__clkinvlp_4") { - leakage_power () { - value : 0.0001981000; - when : "A"; - } - leakage_power () { - value : 9.5549138e-05; - when : "!A"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0001468200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079750000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0093980000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014688370, 0.0043149650, 0.0126759600, 0.0372378500, 0.1093927000, 0.3213600000"); - values("-0.010149800, -0.011281600, -0.015146300, -0.028003400, -0.067446000, -0.184072700, -0.527474900", \ - "-0.011373600, -0.012491400, -0.016167300, -0.028576400, -0.067664800, -0.184268200, -0.527545900", \ - "-0.012540100, -0.013734000, -0.017474600, -0.029580000, -0.068171800, -0.184448300, -0.527622200", \ - "-0.013413900, -0.014737700, -0.018719200, -0.030955400, -0.069069700, -0.184886400, -0.527780100", \ - "-0.013915500, -0.015329000, -0.019573400, -0.032195300, -0.070434700, -0.185630100, -0.528133500", \ - "-0.013423800, -0.014963300, -0.019402500, -0.032846800, -0.071706100, -0.186915000, -0.528780800", \ - "-0.012956200, -0.014532100, -0.019134400, -0.032541100, -0.072153700, -0.188253200, -0.529907900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014688370, 0.0043149650, 0.0126759600, 0.0372378500, 0.1093927000, 0.3213600000"); - values("0.0269260000, 0.0289369000, 0.0341953000, 0.0479687000, 0.0873727000, 0.2029803000, 0.5444188000", \ - "0.0261606000, 0.0281325000, 0.0333833000, 0.0477535000, 0.0875694000, 0.2036089000, 0.5445549000", \ - "0.0254801000, 0.0273550000, 0.0326344000, 0.0468977000, 0.0868469000, 0.2022222000, 0.5428558000", \ - "0.0251657000, 0.0268700000, 0.0319080000, 0.0462032000, 0.0860247000, 0.2034299000, 0.5393811000", \ - "0.0255064000, 0.0270315000, 0.0316562000, 0.0453865000, 0.0857446000, 0.2011584000, 0.5453192000", \ - "0.0253668000, 0.0269287000, 0.0315914000, 0.0451290000, 0.0849052000, 0.2008056000, 0.5420846000", \ - "0.0248290000, 0.0263559000, 0.0307098000, 0.0439307000, 0.0850491000, 0.1996141000, 0.5432347000"); - } - } - max_capacitance : 0.3213600000; - max_transition : 1.4968490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014688400, 0.0043149600, 0.0126760000, 0.0372378000, 0.1093930000, 0.3213600000"); - values("0.0366131000, 0.0407797000, 0.0518162000, 0.0813524000, 0.1645916000, 0.4102750000, 1.1187183000", \ - "0.0396715000, 0.0438522000, 0.0553133000, 0.0856318000, 0.1696285000, 0.4128365000, 1.1257422000", \ - "0.0504074000, 0.0544416000, 0.0658129000, 0.0969734000, 0.1815943000, 0.4323102000, 1.1497040000", \ - "0.0716999000, 0.0777585000, 0.0925023000, 0.1245381000, 0.2103555000, 0.4566917000, 1.1680327000", \ - "0.1009779000, 0.1109235000, 0.1350366000, 0.1843662000, 0.2780332000, 0.5233800000, 1.2371844000", \ - "0.1360531000, 0.1527641000, 0.1924762000, 0.2740414000, 0.4201988000, 0.6832717000, 1.4035331000", \ - "0.1638017000, 0.1920266000, 0.2583126000, 0.3969614000, 0.6345400000, 1.0319019000, 1.7703602000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014688400, 0.0043149600, 0.0126760000, 0.0372378000, 0.1093930000, 0.3213600000"); - values("0.0287655000, 0.0323682000, 0.0416768000, 0.0660491000, 0.1351948000, 0.3375965000, 0.9300706000", \ - "0.0341413000, 0.0376447000, 0.0469003000, 0.0719777000, 0.1429383000, 0.3477393000, 0.9408349000", \ - "0.0487877000, 0.0521233000, 0.0612552000, 0.0859382000, 0.1567706000, 0.3580116000, 0.9595598000", \ - "0.0759712000, 0.0816802000, 0.0947704000, 0.1210031000, 0.1913597000, 0.3947533000, 0.9857243000", \ - "0.1201642000, 0.1300444000, 0.1522022000, 0.1954486000, 0.2720794000, 0.4756262000, 1.0726595000", \ - "0.1953483000, 0.2114619000, 0.2491414000, 0.3230085000, 0.4488810000, 0.6658489000, 1.2682482000", \ - "0.3204703000, 0.3478737000, 0.4112204000, 0.5372600000, 0.7515299000, 1.0907489000, 1.7011555000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014688400, 0.0043149600, 0.0126760000, 0.0372378000, 0.1093930000, 0.3213600000"); - values("0.0169420000, 0.0213824000, 0.0343817000, 0.0726099000, 0.1844912000, 0.5167011000, 1.4766208000", \ - "0.0169584000, 0.0213939000, 0.0343657000, 0.0725425000, 0.1843439000, 0.5128744000, 1.4772464000", \ - "0.0176495000, 0.0216685000, 0.0344356000, 0.0726669000, 0.1844400000, 0.5173826000, 1.4819267000", \ - "0.0279065000, 0.0323373000, 0.0425421000, 0.0745895000, 0.1841320000, 0.5206325000, 1.4796576000", \ - "0.0469810000, 0.0535314000, 0.0695135000, 0.1031050000, 0.1920220000, 0.5146047000, 1.4812662000", \ - "0.0829975000, 0.0934883000, 0.1184331000, 0.1685408000, 0.2629114000, 0.5269848000, 1.4816423000", \ - "0.1466313000, 0.1644020000, 0.2054421000, 0.2884196000, 0.4254798000, 0.6787345000, 1.4968485000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014688400, 0.0043149600, 0.0126760000, 0.0372378000, 0.1093930000, 0.3213600000"); - values("0.0152896000, 0.0189586000, 0.0298880000, 0.0618434000, 0.1559651000, 0.4309381000, 1.2496114000", \ - "0.0151764000, 0.0187590000, 0.0296389000, 0.0620414000, 0.1570294000, 0.4359598000, 1.2423582000", \ - "0.0166136000, 0.0195645000, 0.0297278000, 0.0616073000, 0.1557724000, 0.4309230000, 1.2541660000", \ - "0.0282235000, 0.0316740000, 0.0391689000, 0.0639612000, 0.1558942000, 0.4351387000, 1.2404258000", \ - "0.0486818000, 0.0539590000, 0.0661614000, 0.0919132000, 0.1634710000, 0.4314389000, 1.2509745000", \ - "0.0862207000, 0.0946915000, 0.1157131000, 0.1539913000, 0.2289018000, 0.4440532000, 1.2491433000", \ - "0.1515801000, 0.1663517000, 0.2027362000, 0.2660055000, 0.3845697000, 0.5809205000, 1.2605900000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__conb_1") { - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__conb"; - cell_leakage_power : 0.0032400370; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("HI") { - direction : "output"; - function : "1"; - max_capacitance : 1.9038000000; - max_transition : 1.0000000000; - power_down_function : "!VPWR"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - pin ("LO") { - direction : "output"; - function : "0"; - max_capacitance : 2.0468000000; - max_transition : 1.0000000000; - power_down_function : "VGND"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__decap_12") { - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400940; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__decap_3") { - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400370; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__decap_4") { - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400440; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__decap_6") { - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400560; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__decap_8") { - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400690; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__dfbbn_1") { - leakage_power () { - value : 0.0136348000; - when : "!SET_B&RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0128989000; - when : "!SET_B&!RESET_B&!CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0130481000; - when : "!SET_B&RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0150767000; - when : "SET_B&RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0124114000; - when : "!SET_B&!RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0156363000; - when : "SET_B&RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0124824000; - when : "!SET_B&!RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0122795000; - when : "!SET_B&!RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0113434000; - when : "SET_B&!RESET_B&CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0139753000; - when : "SET_B&RESET_B&!CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0114706000; - when : "SET_B&!RESET_B&CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0145845000; - when : "SET_B&RESET_B&CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0149796000; - when : "SET_B&RESET_B&!CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0136553000; - when : "SET_B&RESET_B&CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0136674000; - when : "!SET_B&RESET_B&!CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0116633000; - when : "SET_B&!RESET_B&!CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0160527000; - when : "SET_B&RESET_B&!CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0154334000; - when : "SET_B&RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0132510000; - when : "!SET_B&RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0126676000; - when : "SET_B&!RESET_B&!CLK_N&D&!Q&Q_N"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__dfbbn"; - cell_leakage_power : 0.0135106100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0017710000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0337081000, 0.0336211000, 0.0334203000, 0.0334695000, 0.0335830000, 0.0338446000, 0.0344475000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0159707000, 0.0158877000, 0.0156965000, 0.0157104000, 0.0157428000, 0.0158175000, 0.0159897000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018470000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2741431000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1994444000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0056395000, 0.0055576000, 0.0053688000, 0.0054478000, 0.0056301000, 0.0060502000, 0.0070187000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("2.2508441e-05, -5.4855369e-05, -0.000233100, -0.000189400, -8.8237148e-05, 0.0001448000, 0.0006819000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016490000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1460430000, 0.3602682000, 0.6524232000", \ - "0.0172669000, 0.2253887000, 0.5089987000", \ - "-0.135727900, 0.0760560000, 0.3535625000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0813457000, 0.1954733000, 0.2813294000", \ - "-0.131658800, -0.016310500, 0.0707663000", \ - "-0.371323600, -0.254754600, -0.166457000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.127394500, -0.340399100, -0.626450500", \ - "0.0038229000, -0.204298800, -0.484246800", \ - "0.1604798000, -0.050083300, -0.326369100"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0447246000, -0.068182300, -0.151597000", \ - "0.2369772000, 0.1289531000, 0.0479798000", \ - "0.4571107000, 0.3564108000, 0.2827617000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.013118900, -0.007925300, 0.0017496000, 0.0125051000, 0.0081486000, -0.042748300, -0.205585900", \ - "-0.013075800, -0.007886100, 0.0017967000, 0.0125318000, 0.0081961000, -0.042706900, -0.205543400", \ - "-0.012990000, -0.007819500, 0.0018260000, 0.0125101000, 0.0081195000, -0.042806800, -0.205665700", \ - "-0.013023600, -0.007865700, 0.0017554000, 0.0123789000, 0.0079284000, -0.043044700, -0.205905600", \ - "-0.013092400, -0.007944200, 0.0016419000, 0.0122261000, 0.0077211000, -0.043277700, -0.206151800", \ - "-0.013221500, -0.008080800, 0.0015101000, 0.0120980000, 0.0076264000, -0.043353700, -0.206238600", \ - "-0.013459100, -0.008221700, 0.0015555000, 0.0124078000, 0.0082200000, -0.042551000, -0.205355400"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.014617300, -0.011243900, -0.003595500, 0.0123659000, 0.0431276000, 0.1107379000, 0.2824599000", \ - "-0.014583400, -0.011219500, -0.003596300, 0.0123405000, 0.0430464000, 0.1106403000, 0.2820950000", \ - "-0.014495200, -0.011150900, -0.003558600, 0.0122880000, 0.0429966000, 0.1111801000, 0.2819773000", \ - "-0.014529400, -0.011194400, -0.003634300, 0.0121937000, 0.0427935000, 0.1109298000, 0.2802180000", \ - "-0.014599900, -0.011293700, -0.003778700, 0.0119873000, 0.0425458000, 0.1106366000, 0.2818473000", \ - "-0.014725100, -0.011406800, -0.003872600, 0.0118935000, 0.0424727000, 0.1106190000, 0.2801155000", \ - "-0.014936700, -0.011489400, -0.003708600, 0.0119663000, 0.0429633000, 0.1110483000, 0.2804747000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002154400, 0.0038245000, 0.0150837000, 0.0282220000, 0.0265387000, -0.021936400, -0.183889600", \ - "-0.002117100, 0.0038523000, 0.0151043000, 0.0282125000, 0.0265001000, -0.022017700, -0.183956600", \ - "-0.002023400, 0.0039316000, 0.0151626000, 0.0282332000, 0.0264782000, -0.022059800, -0.184024600", \ - "-0.002054600, 0.0038969000, 0.0151099000, 0.0281524000, 0.0263836000, -0.022172400, -0.184145800", \ - "-0.002130600, 0.0038070000, 0.0149959000, 0.0279895000, 0.0261604000, -0.022441200, -0.184423700", \ - "-0.002282000, 0.0036305000, 0.0147812000, 0.0277047000, 0.0258056000, -0.022831400, -0.184864400", \ - "-0.002546100, 0.0034603000, 0.0147850000, 0.0279794000, 0.0260189000, -0.022801700, -0.184825600"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0059601000, 0.0107906000, 0.0197367000, 0.0293410000, 0.0241999000, -0.026539000, -0.189585300", \ - "0.0059783000, 0.0108086000, 0.0197492000, 0.0293507000, 0.0242058000, -0.026547000, -0.189617500", \ - "0.0060211000, 0.0108428000, 0.0197759000, 0.0293756000, 0.0241776000, -0.026596200, -0.189682200", \ - "0.0059985000, 0.0107810000, 0.0196333000, 0.0290937000, 0.0238127000, -0.027051900, -0.190163800", \ - "0.0059673000, 0.0107088000, 0.0194741000, 0.0288108000, 0.0233371000, -0.027664300, -0.190844000", \ - "0.0059571000, 0.0106557000, 0.0193402000, 0.0285765000, 0.0229695000, -0.028236600, -0.191439700", \ - "0.0060389000, 0.0108310000, 0.0196885000, 0.0292292000, 0.0236159000, -0.028321400, -0.191565900"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-7.85000e-06, 0.0038148000, 0.0123335000, 0.0301004000, 0.0629439000, 0.1317667000, 0.3020845000", \ - "-1.73500e-05, 0.0037856000, 0.0122737000, 0.0299779000, 0.0627595000, 0.1315190000, 0.3017892000", \ - "-1.28000e-05, 0.0037672000, 0.0122050000, 0.0298550000, 0.0625505000, 0.1312915000, 0.3030018000", \ - "-2.88500e-05, 0.0037364000, 0.0121453000, 0.0297570000, 0.0623081000, 0.1316585000, 0.3028561000", \ - "-6.15000e-05, 0.0036696000, 0.0120446000, 0.0295616000, 0.0620329000, 0.1307639000, 0.3025353000", \ - "-0.000124500, 0.0035727000, 0.0118715000, 0.0292698000, 0.0616901000, 0.1303403000, 0.3020232000", \ - "-0.000195800, 0.0035257000, 0.0118245000, 0.0294352000, 0.0621746000, 0.1310316000, 0.3026413000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5056960000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.5180351000, 0.5233249000, 0.5345825000, 0.5577999000, 0.6101612000, 0.7438868000, 1.0967318000", \ - "0.5229801000, 0.5283169000, 0.5394920000, 0.5627560000, 0.6151611000, 0.7488364000, 1.1014918000", \ - "0.5359026000, 0.5411940000, 0.5524545000, 0.5756685000, 0.6280489000, 0.7617846000, 1.1146027000", \ - "0.5665681000, 0.5718932000, 0.5830810000, 0.6063570000, 0.6587572000, 0.7924406000, 1.1453667000", \ - "0.6369824000, 0.6423173000, 0.6534947000, 0.6767559000, 0.7291617000, 0.8628444000, 1.2156370000", \ - "0.7625178000, 0.7678350000, 0.7790286000, 0.8023088000, 0.8547609000, 0.9884565000, 1.3413308000", \ - "0.9574813000, 0.9628160000, 0.9739946000, 0.9972614000, 1.0496674000, 1.1832638000, 1.5361579000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4196785000, 0.4263593000, 0.4414610000, 0.4774378000, 0.5704403000, 0.8147020000, 1.4604230000", \ - "0.4242280000, 0.4309002000, 0.4460303000, 0.4818546000, 0.5751117000, 0.8196684000, 1.4635920000", \ - "0.4371639000, 0.4438522000, 0.4590250000, 0.4948741000, 0.5881437000, 0.8327289000, 1.4764002000", \ - "0.4680765000, 0.4747426000, 0.4898704000, 0.5256942000, 0.6189738000, 0.8634777000, 1.5079367000", \ - "0.5379648000, 0.5446284000, 0.5597990000, 0.5956249000, 0.6888364000, 0.9335230000, 1.5785173000", \ - "0.6613912000, 0.6680977000, 0.6832083000, 0.7190224000, 0.8120922000, 1.0566903000, 1.7022148000", \ - "0.8513130000, 0.8580370000, 0.8730250000, 0.9091449000, 1.0017882000, 1.2459436000, 1.8952520000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0176032000, 0.0217563000, 0.0308584000, 0.0543639000, 0.1182422000, 0.2941650000, 0.7660847000", \ - "0.0178200000, 0.0216202000, 0.0311543000, 0.0545215000, 0.1180621000, 0.2940278000, 0.7679949000", \ - "0.0175742000, 0.0217579000, 0.0310342000, 0.0544136000, 0.1182512000, 0.2941697000, 0.7695827000", \ - "0.0175723000, 0.0217170000, 0.0311570000, 0.0544546000, 0.1181397000, 0.2942622000, 0.7696122000", \ - "0.0178095000, 0.0216266000, 0.0311534000, 0.0545336000, 0.1181377000, 0.2942685000, 0.7689317000", \ - "0.0176191000, 0.0217934000, 0.0311661000, 0.0544672000, 0.1176449000, 0.2941619000, 0.7699258000", \ - "0.0178201000, 0.0216265000, 0.0311543000, 0.0545048000, 0.1182650000, 0.2930556000, 0.7696241000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0234945000, 0.0296093000, 0.0464369000, 0.0944435000, 0.2265095000, 0.5739141000, 1.5023117000", \ - "0.0234273000, 0.0295811000, 0.0465949000, 0.0945060000, 0.2265088000, 0.5744835000, 1.5056955000", \ - "0.0236229000, 0.0297792000, 0.0465889000, 0.0942645000, 0.2259887000, 0.5743669000, 1.5039712000", \ - "0.0234389000, 0.0295812000, 0.0465956000, 0.0945141000, 0.2263018000, 0.5742228000, 1.5016998000", \ - "0.0235898000, 0.0297791000, 0.0466851000, 0.0945373000, 0.2264350000, 0.5752580000, 1.5021120000", \ - "0.0235127000, 0.0295708000, 0.0466014000, 0.0944304000, 0.2258319000, 0.5744031000, 1.4993907000", \ - "0.0234895000, 0.0295441000, 0.0466866000, 0.0945043000, 0.2264349000, 0.5736470000, 1.5015317000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2977234000, 0.3030614000, 0.3143852000, 0.3378161000, 0.3903258000, 0.5241114000, 0.8765873000", \ - "0.3028653000, 0.3081985000, 0.3195896000, 0.3429373000, 0.3954337000, 0.5291723000, 0.8814233000", \ - "0.3153412000, 0.3206732000, 0.3320652000, 0.3554121000, 0.4079271000, 0.5416437000, 0.8938935000", \ - "0.3468358000, 0.3521800000, 0.3634746000, 0.3869397000, 0.4394665000, 0.5732152000, 0.9254234000", \ - "0.4169812000, 0.4223492000, 0.4337039000, 0.4571362000, 0.5096675000, 0.6433050000, 0.9955831000", \ - "0.5440443000, 0.5493195000, 0.5606315000, 0.5841116000, 0.6367259000, 0.7705344000, 1.1226631000", \ - "0.7433728000, 0.7487408000, 0.7601532000, 0.7836598000, 0.8362692000, 0.9701819000, 1.3220783000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0181323000, 0.0222635000, 0.0316722000, 0.0549123000, 0.1182262000, 0.2935464000, 0.7632870000", \ - "0.0182107000, 0.0222136000, 0.0314937000, 0.0550292000, 0.1181257000, 0.2935452000, 0.7620384000", \ - "0.0182031000, 0.0222152000, 0.0314983000, 0.0550298000, 0.1182128000, 0.2935558000, 0.7627947000", \ - "0.0180388000, 0.0221018000, 0.0315055000, 0.0549181000, 0.1182240000, 0.2934013000, 0.7631649000", \ - "0.0181355000, 0.0219196000, 0.0316683000, 0.0548868000, 0.1183149000, 0.2933887000, 0.7628067000", \ - "0.0181325000, 0.0220125000, 0.0316669000, 0.0550895000, 0.1183730000, 0.2935994000, 0.7634567000", \ - "0.0181976000, 0.0221852000, 0.0318775000, 0.0550942000, 0.1182590000, 0.2938075000, 0.7619939000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2006709000, 0.2059951000, 0.2173790000, 0.2407884000, 0.2933465000, 0.4271308000, 0.7793231000", \ - "0.2054638000, 0.2107880000, 0.2221708000, 0.2455806000, 0.2981369000, 0.4319231000, 0.7842617000", \ - "0.2153451000, 0.2207143000, 0.2320699000, 0.2554371000, 0.3080746000, 0.4416886000, 0.7941024000", \ - "0.2367400000, 0.2420797000, 0.2533734000, 0.2768369000, 0.3293861000, 0.4631800000, 0.8155175000", \ - "0.2838036000, 0.2892078000, 0.3005436000, 0.3240167000, 0.3766293000, 0.5103523000, 0.8627468000", \ - "0.3622627000, 0.3677938000, 0.3792997000, 0.4029804000, 0.4559090000, 0.5896066000, 0.9419692000", \ - "0.4609748000, 0.4669309000, 0.4791672000, 0.5033871000, 0.5566558000, 0.6907097000, 1.0428505000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3300887000, 0.3373925000, 0.3532256000, 0.3895396000, 0.4825501000, 0.7271255000, 1.3714623000", \ - "0.3351995000, 0.3425049000, 0.3583458000, 0.3946438000, 0.4876834000, 0.7321337000, 1.3753657000", \ - "0.3480795000, 0.3554645000, 0.3712504000, 0.4075831000, 0.5006325000, 0.7452338000, 1.3905450000", \ - "0.3798780000, 0.3872734000, 0.4030561000, 0.4393869000, 0.5324446000, 0.7770249000, 1.4224204000", \ - "0.4560595000, 0.4634380000, 0.4792819000, 0.5156174000, 0.6086446000, 0.8531071000, 1.4980971000", \ - "0.6347878000, 0.6421049000, 0.6579813000, 0.6943139000, 0.7873437000, 1.0316390000, 1.6771919000", \ - "0.9888976000, 0.9971117000, 1.0139394000, 1.0507694000, 1.1435058000, 1.3881732000, 2.0334101000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0179294000, 0.0221700000, 0.0314614000, 0.0549518000, 0.1180863000, 0.2935449000, 0.7627353000", \ - "0.0179284000, 0.0221664000, 0.0314625000, 0.0549512000, 0.1181119000, 0.2935441000, 0.7630649000", \ - "0.0180264000, 0.0222520000, 0.0316087000, 0.0549814000, 0.1179052000, 0.2931835000, 0.7621098000", \ - "0.0180071000, 0.0221052000, 0.0314395000, 0.0549313000, 0.1182318000, 0.2938865000, 0.7624429000", \ - "0.0180057000, 0.0221137000, 0.0316455000, 0.0548995000, 0.1182925000, 0.2935304000, 0.7614261000", \ - "0.0189472000, 0.0228080000, 0.0323953000, 0.0557002000, 0.1186871000, 0.2937020000, 0.7643067000", \ - "0.0213179000, 0.0252150000, 0.0344248000, 0.0577447000, 0.1196200000, 0.2938303000, 0.7601352000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0267420000, 0.0326136000, 0.0486417000, 0.0953440000, 0.2261496000, 0.5757559000, 1.4996626000", \ - "0.0267484000, 0.0326232000, 0.0486566000, 0.0952879000, 0.2263766000, 0.5755616000, 1.4995368000", \ - "0.0267985000, 0.0326136000, 0.0485424000, 0.0954489000, 0.2266398000, 0.5755250000, 1.4996197000", \ - "0.0268230000, 0.0326320000, 0.0485766000, 0.0953917000, 0.2266013000, 0.5752018000, 1.5002098000", \ - "0.0266908000, 0.0327023000, 0.0486874000, 0.0954074000, 0.2262224000, 0.5738892000, 1.4986681000", \ - "0.0266834000, 0.0327446000, 0.0486814000, 0.0954047000, 0.2264533000, 0.5745057000, 1.4990971000", \ - "0.0313034000, 0.0374024000, 0.0517816000, 0.0964806000, 0.2262485000, 0.5750520000, 1.4997914000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.012995500, -0.007794200, 0.0017451000, 0.0123222000, 0.0090980000, -0.036481800, -0.183011100", \ - "-0.012958400, -0.007759900, 0.0017753000, 0.0123351000, 0.0090787000, -0.036480700, -0.183012400", \ - "-0.012870200, -0.007678800, 0.0018031000, 0.0123546000, 0.0090455000, -0.036555700, -0.183116500", \ - "-0.012907000, -0.007746300, 0.0017131000, 0.0121766000, 0.0088281000, -0.036855200, -0.183419300", \ - "-0.012979400, -0.007835800, 0.0015732000, 0.0119666000, 0.0085881000, -0.037125000, -0.183711600", \ - "-0.013111000, -0.007972400, 0.0014400000, 0.0118370000, 0.0084115000, -0.037299600, -0.183876800", \ - "-0.013382000, -0.008190800, 0.0013107000, 0.0118578000, 0.0085249000, -0.036888100, -0.183404800"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.014429700, -0.010881800, -0.003054000, 0.0124911000, 0.0418205000, 0.1048422000, 0.2590148000", \ - "-0.014388500, -0.010843900, -0.003016400, 0.0125219000, 0.0418477000, 0.1052250000, 0.2603546000", \ - "-0.014299500, -0.010772500, -0.002982300, 0.0124899000, 0.0417114000, 0.1052237000, 0.2598449000", \ - "-0.014336500, -0.010825100, -0.003061900, 0.0123752000, 0.0416289000, 0.1044912000, 0.2599381000", \ - "-0.014403200, -0.010905500, -0.003172600, 0.0122124000, 0.0414286000, 0.1043705000, 0.2580854000", \ - "-0.014533200, -0.011036200, -0.003305700, 0.0121014000, 0.0413079000, 0.1042661000, 0.2596633000", \ - "-0.014771000, -0.011183600, -0.003264600, 0.0123794000, 0.0419744000, 0.1048420000, 0.2604415000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.003671400, 0.0003568000, 0.0090831000, 0.0281336000, 0.0608991000, 0.1254417000, 0.2802019000", \ - "-0.003632900, 0.0003774000, 0.0091252000, 0.0281208000, 0.0608385000, 0.1253540000, 0.2798081000", \ - "-0.003531400, 0.0004804000, 0.0092033000, 0.0282114000, 0.0608835000, 0.1253939000, 0.2799643000", \ - "-0.003572300, 0.0004212000, 0.0091130000, 0.0280592000, 0.0606872000, 0.1251640000, 0.2797859000", \ - "-0.003640000, 0.0003359000, 0.0090086000, 0.0278244000, 0.0604577000, 0.1248986000, 0.2796913000", \ - "-0.003795300, 0.0001658000, 0.0087967000, 0.0276239000, 0.0601186000, 0.1244490000, 0.2801330000", \ - "-0.003806300, 0.0005988000, 0.0101368000, 0.0280963000, 0.0602104000, 0.1246705000, 0.2794334000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0016731000, 0.0073970000, 0.0179427000, 0.0300304000, 0.0285625000, -0.015571300, -0.161379500", \ - "0.0016670000, 0.0073697000, 0.0178813000, 0.0299205000, 0.0284012000, -0.015791800, -0.161594800", \ - "0.0016717000, 0.0073472000, 0.0178251000, 0.0297652000, 0.0281864000, -0.016031300, -0.161868400", \ - "0.0016543000, 0.0073142000, 0.0177701000, 0.0296749000, 0.0280425000, -0.016207200, -0.162016900", \ - "0.0016199000, 0.0072608000, 0.0176651000, 0.0294890000, 0.0277775000, -0.016518300, -0.162354700", \ - "0.0015681000, 0.0071760000, 0.0175044000, 0.0292099000, 0.0273448000, -0.016999600, -0.162802600", \ - "0.0015393000, 0.0072071000, 0.0176072000, 0.0293402000, 0.0276721000, -0.016605200, -0.162356500"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0044038000, 0.0072433000, 0.0136547000, 0.0292313000, 0.0585152000, 0.1209384000, 0.2743025000", \ - "0.0044231000, 0.0072613000, 0.0136686000, 0.0292411000, 0.0585191000, 0.1208893000, 0.2739825000", \ - "0.0044697000, 0.0072995000, 0.0136811000, 0.0292279000, 0.0584920000, 0.1209078000, 0.2739967000", \ - "0.0044422000, 0.0072326000, 0.0135628000, 0.0289729000, 0.0581150000, 0.1201908000, 0.2734707000", \ - "0.0044265000, 0.0071909000, 0.0134522000, 0.0286991000, 0.0575920000, 0.1196264000, 0.2735024000", \ - "0.0044501000, 0.0072240000, 0.0135005000, 0.0285040000, 0.0570917000, 0.1189221000, 0.2722495000", \ - "0.0047344000, 0.0078900000, 0.0149406000, 0.0291925000, 0.0571480000, 0.1189946000, 0.2716955000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.5013840000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.3481749000, 0.3575085000, 0.3766972000, 0.4132324000, 0.4824068000, 0.6211589000, 0.9512588000", \ - "0.3532533000, 0.3625979000, 0.3817241000, 0.4183318000, 0.4874523000, 0.6262101000, 0.9566112000", \ - "0.3656498000, 0.3749793000, 0.3941110000, 0.4304736000, 0.4996658000, 0.6383931000, 0.9685180000", \ - "0.3963867000, 0.4057056000, 0.4248694000, 0.4615248000, 0.5306698000, 0.6693849000, 0.9995640000", \ - "0.4666586000, 0.4759553000, 0.4950673000, 0.5317617000, 0.6008926000, 0.7396264000, 1.0697362000", \ - "0.5907117000, 0.6000445000, 0.6192221000, 0.6557904000, 0.7249482000, 0.8637051000, 1.1935923000", \ - "0.7797389000, 0.7890985000, 0.8082977000, 0.8448628000, 0.9140397000, 1.0528218000, 1.3826106000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.4602863000, 0.4694324000, 0.4892493000, 0.5318499000, 0.6311791000, 0.8776550000, 1.5163582000", \ - "0.4653396000, 0.4743892000, 0.4941687000, 0.5367666000, 0.6361012000, 0.8824604000, 1.5221376000", \ - "0.4781583000, 0.4873036000, 0.5071203000, 0.5497208000, 0.6490609000, 0.8961863000, 1.5361979000", \ - "0.5088252000, 0.5179578000, 0.5377616000, 0.5803621000, 0.6797127000, 0.9263058000, 1.5645605000", \ - "0.5791356000, 0.5882900000, 0.6080699000, 0.6506687000, 0.7500197000, 0.9966502000, 1.6346251000", \ - "0.7048294000, 0.7139465000, 0.7337072000, 0.7763123000, 0.8756540000, 1.1223376000, 1.7622477000", \ - "0.8997437000, 0.9088486000, 0.9286832000, 0.9712742000, 1.0705961000, 1.3169784000, 1.9588104000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0362804000, 0.0425112000, 0.0561448000, 0.0844662000, 0.1457486000, 0.2981817000, 0.7252713000", \ - "0.0361321000, 0.0425687000, 0.0561557000, 0.0842942000, 0.1457993000, 0.2990236000, 0.7282444000", \ - "0.0362929000, 0.0422542000, 0.0558699000, 0.0844008000, 0.1460249000, 0.2988044000, 0.7248183000", \ - "0.0361646000, 0.0423712000, 0.0558260000, 0.0843185000, 0.1459849000, 0.2988518000, 0.7252426000", \ - "0.0361380000, 0.0422927000, 0.0558737000, 0.0843037000, 0.1460520000, 0.2981272000, 0.7236755000", \ - "0.0362548000, 0.0423951000, 0.0559720000, 0.0844239000, 0.1460858000, 0.2983374000, 0.7241814000", \ - "0.0363250000, 0.0426775000, 0.0562526000, 0.0844421000, 0.1461184000, 0.2985644000, 0.7233893000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0332768000, 0.0409842000, 0.0598917000, 0.1093272000, 0.2390118000, 0.5855177000, 1.4993016000", \ - "0.0331544000, 0.0410076000, 0.0599572000, 0.1093175000, 0.2390430000, 0.5856524000, 1.4965029000", \ - "0.0332738000, 0.0409847000, 0.0599004000, 0.1093348000, 0.2389455000, 0.5849604000, 1.4978243000", \ - "0.0333361000, 0.0410238000, 0.0600985000, 0.1092827000, 0.2395263000, 0.5844384000, 1.5013841000", \ - "0.0331647000, 0.0410036000, 0.0599583000, 0.1093221000, 0.2387535000, 0.5842233000, 1.4948799000", \ - "0.0331327000, 0.0409611000, 0.0600342000, 0.1092989000, 0.2397670000, 0.5855911000, 1.4935948000", \ - "0.0331290000, 0.0410232000, 0.0598751000, 0.1093471000, 0.2389366000, 0.5847323000, 1.4977015000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2393759000, 0.2489567000, 0.2697361000, 0.3141343000, 0.4172389000, 0.6668904000, 1.3048309000", \ - "0.2444034000, 0.2540059000, 0.2747168000, 0.3191333000, 0.4222449000, 0.6718295000, 1.3099447000", \ - "0.2571860000, 0.2667761000, 0.2875758000, 0.3319679000, 0.4350655000, 0.6847565000, 1.3228046000", \ - "0.2882983000, 0.2978922000, 0.3186488000, 0.3630789000, 0.4661817000, 0.7158713000, 1.3540856000", \ - "0.3579442000, 0.3675454000, 0.3882865000, 0.4333124000, 0.5364280000, 0.7861610000, 1.4244975000", \ - "0.4856320000, 0.4953379000, 0.5162690000, 0.5609306000, 0.6642169000, 0.9136941000, 1.5511995000", \ - "0.6845004000, 0.6945481000, 0.7159091000, 0.7611781000, 0.8652029000, 1.1148595000, 1.7524906000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0350831000, 0.0433346000, 0.0628988000, 0.1140332000, 0.2463338000, 0.5867331000, 1.4922141000", \ - "0.0351216000, 0.0432563000, 0.0629340000, 0.1138691000, 0.2466862000, 0.5892409000, 1.4951977000", \ - "0.0350563000, 0.0433911000, 0.0629194000, 0.1139984000, 0.2468653000, 0.5873637000, 1.4945405000", \ - "0.0351171000, 0.0433642000, 0.0629483000, 0.1139440000, 0.2468853000, 0.5874856000, 1.4948630000", \ - "0.0351672000, 0.0433500000, 0.0629743000, 0.1139960000, 0.2465873000, 0.5875861000, 1.4954338000", \ - "0.0358561000, 0.0440332000, 0.0635791000, 0.1145205000, 0.2466110000, 0.5873491000, 1.4948879000", \ - "0.0377214000, 0.0458589000, 0.0653740000, 0.1163602000, 0.2477663000, 0.5876252000, 1.4915941000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2465430000, 0.2580592000, 0.2823831000, 0.3284402000, 0.4111073000, 0.5600623000, 0.8937315000", \ - "0.2516328000, 0.2631607000, 0.2874896000, 0.3335367000, 0.4161826000, 0.5651348000, 0.8989036000", \ - "0.2644337000, 0.2760075000, 0.3004189000, 0.3464543000, 0.4290885000, 0.5779924000, 0.9122260000", \ - "0.2962597000, 0.3079114000, 0.3321961000, 0.3782334000, 0.4608330000, 0.6097672000, 0.9434271000", \ - "0.3725735000, 0.3840824000, 0.4083623000, 0.4542983000, 0.5369306000, 0.6859581000, 1.0200242000", \ - "0.5504185000, 0.5621963000, 0.5866647000, 0.6325303000, 0.7149561000, 0.8639969000, 1.1981248000", \ - "0.8824479000, 0.8990724000, 0.9322326000, 0.9888147000, 1.0812390000, 1.2367529000, 1.5722447000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1419570000, 0.1515393000, 0.1722648000, 0.2166458000, 0.3195485000, 0.5690324000, 1.2076676000", \ - "0.1467483000, 0.1563305000, 0.1770560000, 0.2214396000, 0.3243590000, 0.5738486000, 1.2117806000", \ - "0.1567100000, 0.1662946000, 0.1869694000, 0.2313643000, 0.3342920000, 0.5838097000, 1.2220470000", \ - "0.1780335000, 0.1875940000, 0.2083534000, 0.2526602000, 0.3556284000, 0.6052141000, 1.2430390000", \ - "0.2243055000, 0.2341585000, 0.2551254000, 0.2996797000, 0.4027992000, 0.6523285000, 1.2904465000", \ - "0.2973940000, 0.3087439000, 0.3322051000, 0.3796051000, 0.4848363000, 0.7340557000, 1.3720186000", \ - "0.3823481000, 0.3973559000, 0.4270940000, 0.4825704000, 0.5933259000, 0.8432074000, 1.4807456000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0477885000, 0.0557240000, 0.0721976000, 0.1064428000, 0.1689308000, 0.3132860000, 0.7280668000", \ - "0.0478157000, 0.0557667000, 0.0722085000, 0.1065480000, 0.1685762000, 0.3134115000, 0.7292764000", \ - "0.0478417000, 0.0558366000, 0.0722711000, 0.1065291000, 0.1688424000, 0.3136168000, 0.7296686000", \ - "0.0479384000, 0.0557638000, 0.0725344000, 0.1065726000, 0.1685422000, 0.3127562000, 0.7283439000", \ - "0.0477983000, 0.0557748000, 0.0722878000, 0.1066086000, 0.1686331000, 0.3133393000, 0.7293963000", \ - "0.0504162000, 0.0578960000, 0.0738779000, 0.1072996000, 0.1688769000, 0.3134912000, 0.7325642000", \ - "0.0793076000, 0.0884472000, 0.1051326000, 0.1349901000, 0.1887523000, 0.3237997000, 0.7309207000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0349462000, 0.0432202000, 0.0628163000, 0.1138325000, 0.2468777000, 0.5875716000, 1.4933644000", \ - "0.0349446000, 0.0432222000, 0.0628158000, 0.1138324000, 0.2468876000, 0.5876373000, 1.4926078000", \ - "0.0348473000, 0.0429952000, 0.0628561000, 0.1138326000, 0.2466209000, 0.5871476000, 1.4913646000", \ - "0.0348651000, 0.0432149000, 0.0627781000, 0.1138523000, 0.2467079000, 0.5871689000, 1.4915753000", \ - "0.0361597000, 0.0443375000, 0.0638245000, 0.1143652000, 0.2466808000, 0.5873372000, 1.4924713000", \ - "0.0434384000, 0.0518206000, 0.0712488000, 0.1205725000, 0.2488895000, 0.5872272000, 1.4932159000", \ - "0.0596611000, 0.0696235000, 0.0895158000, 0.1370562000, 0.2574123000, 0.5889797000, 1.4946339000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0016230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0128885000, 0.0127980000, 0.0125896000, 0.0126427000, 0.0127652000, 0.0130477000, 0.0136989000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081258000, 0.0080711000, 0.0079450000, 0.0079748000, 0.0080433000, 0.0082014000, 0.0085660000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017040000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0703594000, 0.1966940000, 0.2935365000", \ - "-0.147528000, -0.019972700, 0.0768698000", \ - "-0.395737600, -0.268182300, -0.170119100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0728008000, -0.051092400, -0.138169300", \ - "0.2711569000, 0.1472637000, 0.0601868000", \ - "0.5108216000, 0.3881491000, 0.3010723000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2192176000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.060874400, -0.073895200", \ - "-0.226873700, -0.166457000, -0.175815800", \ - "-0.331040400, -0.252313200, -0.247023400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.1027161000, 0.1865378000", \ - "0.2699362000, 0.2156230000, 0.2493958000", \ - "0.4009583000, 0.3258932000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051165000, 0.0051001000, 0.0050622000, 0.0050755000, 0.0051066000, 0.0051783000, 0.0053435000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004958400, -0.004999900, -0.005095500, -0.005099000, -0.005106900, -0.005125000, -0.005166700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035560000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.060255900, 0.0318991000, 0.1189759000", \ - "-0.246404900, -0.156691400, -0.102573600", \ - "-0.450669300, -0.360955700, -0.326369100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0666973000, -0.021795600, -0.055161500", \ - "0.2516257000, 0.1643535000, 0.1309876000", \ - "0.4558900000, 0.3673971000, 0.3401348000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.2699362000, 0.4009583000", \ - "0.1027161000, 0.2156230000, 0.3258932000", \ - "0.1865378000, 0.2493958000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2543700000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.226873700, -0.331040400", \ - "-0.060874400, -0.166457000, -0.252313200", \ - "-0.073895200, -0.175815800, -0.247023400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfbbn_2") { - leakage_power () { - value : 0.0117983000; - when : "!SET_B&RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0137929000; - when : "SET_B&RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0116202000; - when : "!SET_B&!RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0143473000; - when : "SET_B&RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0116884000; - when : "!SET_B&!RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0114876000; - when : "!SET_B&!RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0116142000; - when : "SET_B&!RESET_B&CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0137305000; - when : "SET_B&RESET_B&!CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0117410000; - when : "SET_B&!RESET_B&CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0143260000; - when : "SET_B&RESET_B&CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0147321000; - when : "SET_B&RESET_B&!CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0134107000; - when : "SET_B&RESET_B&CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0124126000; - when : "!SET_B&RESET_B&!CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0119341000; - when : "SET_B&!RESET_B&!CLK_N&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0147607000; - when : "SET_B&RESET_B&!CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0141465000; - when : "SET_B&RESET_B&CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0119992000; - when : "!SET_B&RESET_B&!CLK_N&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0129356000; - when : "SET_B&!RESET_B&!CLK_N&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0123327000; - when : "!SET_B&RESET_B&CLK_N&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0121019000; - when : "!SET_B&!RESET_B&!CLK_N&!D&Q&!Q_N"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__dfbbn"; - cell_leakage_power : 0.0128456200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0017970000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0338824000, 0.0337452000, 0.0334290000, 0.0334754000, 0.0335827000, 0.0338300000, 0.0343999000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161190000, 0.0160333000, 0.0158358000, 0.0158482000, 0.0158771000, 0.0159436000, 0.0160970000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018660000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2884238000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1994444000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055914000, 0.0055096000, 0.0053212000, 0.0053975000, 0.0055737000, 0.0059798000, 0.0069158000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("1.6588513e-05, -5.5872937e-05, -0.000222800, -0.000179400, -7.9130524e-05, 0.0001520000, 0.0006848000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016480000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1460430000, 0.3590475000, 0.6512025000", \ - "0.0148255000, 0.2253887000, 0.5077780000", \ - "-0.138169300, 0.0723939000, 0.3499004000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0837871000, 0.1991354000, 0.2849915000", \ - "-0.129217500, -0.012648400, 0.0732077000", \ - "-0.367661500, -0.252313200, -0.164015600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.126173800, -0.339178400, -0.625229800", \ - "0.0062643000, -0.203078100, -0.481805300", \ - "0.1629212000, -0.046421200, -0.322707000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0471660000, -0.066961600, -0.149155600", \ - "0.2394186000, 0.1301738000, 0.0504212000", \ - "0.4607728000, 0.3600729000, 0.2864238000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.013582700, -0.007945000, 0.0038542000, 0.0173618000, 0.0056755000, -0.091616700, -0.418048700", \ - "-0.013520600, -0.007899200, 0.0038800000, 0.0173497000, 0.0056181000, -0.091695900, -0.418134300", \ - "-0.013364900, -0.007747300, 0.0040084000, 0.0174511000, 0.0056757000, -0.091682400, -0.418128000", \ - "-0.013396400, -0.007796100, 0.0039343000, 0.0173054000, 0.0055037000, -0.091949800, -0.418361800", \ - "-0.013459700, -0.007869500, 0.0038093000, 0.0171715000, 0.0052897000, -0.092112400, -0.418594600", \ - "-0.013580100, -0.007986700, 0.0037205000, 0.0170762000, 0.0052348000, -0.092219300, -0.418698700", \ - "-0.013838000, -0.008196800, 0.0036139000, 0.0171538000, 0.0055752000, -0.091695100, -0.418122800"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.015157100, -0.011889400, -0.003284300, 0.0171469000, 0.0632073000, 0.1801531000, 0.5123678000", \ - "-0.015091400, -0.011834400, -0.003229300, 0.0171669000, 0.0633156000, 0.1800816000, 0.5143452000", \ - "-0.014938700, -0.011691700, -0.003124500, 0.0172421000, 0.0632012000, 0.1798299000, 0.5117702000", \ - "-0.014975600, -0.011747100, -0.003218000, 0.0170543000, 0.0630194000, 0.1805871000, 0.5112811000", \ - "-0.015037300, -0.011829200, -0.003355100, 0.0168557000, 0.0629699000, 0.1803904000, 0.5133650000", \ - "-0.015165900, -0.011959200, -0.003479000, 0.0167173000, 0.0625888000, 0.1790431000, 0.5130447000", \ - "-0.015341300, -0.011971800, -0.003290800, 0.0166937000, 0.0632292000, 0.1793322000, 0.5112425000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.002733600, 0.0035533000, 0.0168500000, 0.0327309000, 0.0242815000, -0.070676400, -0.396364300", \ - "-0.002689200, 0.0035894000, 0.0168347000, 0.0327097000, 0.0241419000, -0.070794000, -0.396312200", \ - "-0.002593600, 0.0036745000, 0.0168923000, 0.0327279000, 0.0241175000, -0.070840400, -0.396453300", \ - "-0.002623000, 0.0036443000, 0.0168624000, 0.0326993000, 0.0241267000, -0.070887500, -0.396613500", \ - "-0.002689900, 0.0035573000, 0.0167598000, 0.0325112000, 0.0238976000, -0.071129200, -0.396860200", \ - "-0.002834900, 0.0033971000, 0.0165593000, 0.0322492000, 0.0235593000, -0.071584900, -0.397295900", \ - "-0.003063800, 0.0033043000, 0.0167832000, 0.0330063000, 0.0237330000, -0.071541900, -0.397248700"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("0.0056062000, 0.0108587000, 0.0217829000, 0.0338720000, 0.0215949000, -0.075581600, -0.402235300", \ - "0.0056264000, 0.0108826000, 0.0217990000, 0.0338825000, 0.0215742000, -0.075603100, -0.402244100", \ - "0.0056639000, 0.0109032000, 0.0218122000, 0.0338656000, 0.0215658000, -0.075649200, -0.402287600", \ - "0.0056481000, 0.0108581000, 0.0217071000, 0.0336587000, 0.0211804000, -0.076116200, -0.402722700", \ - "0.0056312000, 0.0108023000, 0.0215591000, 0.0333552000, 0.0207464000, -0.076706600, -0.403433500", \ - "0.0056385000, 0.0108127000, 0.0215393000, 0.0333563000, 0.0204697000, -0.077246500, -0.404004300", \ - "0.0057374000, 0.0110437000, 0.0220861000, 0.0343416000, 0.0211170000, -0.077332700, -0.404203200"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.000512900, 0.0031516000, 0.0127026000, 0.0349354000, 0.0829933000, 0.2008713000, 0.5334206000", \ - "-0.000515500, 0.0031364000, 0.0126336000, 0.0347823000, 0.0830971000, 0.2010458000, 0.5350268000", \ - "-0.000515000, 0.0031144000, 0.0125490000, 0.0346452000, 0.0828610000, 0.2007271000, 0.5329991000", \ - "-0.000530000, 0.0030857000, 0.0125237000, 0.0345623000, 0.0825600000, 0.2011088000, 0.5343497000", \ - "-0.000559200, 0.0030381000, 0.0123850000, 0.0343584000, 0.0823033000, 0.2004075000, 0.5314888000", \ - "-0.000614200, 0.0029516000, 0.0122477000, 0.0340774000, 0.0817771000, 0.1998085000, 0.5317224000", \ - "-0.000677900, 0.0029207000, 0.0123101000, 0.0344652000, 0.0825377000, 0.2006496000, 0.5349586000"); - } - } - max_capacitance : 0.3131200000; - max_transition : 1.4976940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.5715146000, 0.5764608000, 0.5872999000, 0.6094978000, 0.6562273000, 0.7728852000, 1.1070838000", \ - "0.5763654000, 0.5813140000, 0.5921482000, 0.6143386000, 0.6610686000, 0.7777333000, 1.1119631000", \ - "0.5888512000, 0.5937825000, 0.6047230000, 0.6268766000, 0.6736517000, 0.7902700000, 1.1248132000", \ - "0.6198478000, 0.6247883000, 0.6357509000, 0.6578812000, 0.7045739000, 0.8213871000, 1.1548854000", \ - "0.6903620000, 0.6953002000, 0.7062560000, 0.7282338000, 0.7750668000, 0.8917673000, 1.2255494000", \ - "0.8164339000, 0.8213774000, 0.8323279000, 0.8544688000, 0.9011354000, 1.0179231000, 1.3516137000", \ - "1.0122578000, 1.0172030000, 1.0280993000, 1.0502539000, 1.0970421000, 1.2136561000, 1.5477983000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.4959562000, 0.5023387000, 0.5161479000, 0.5469950000, 0.6271237000, 0.8580184000, 1.5340924000", \ - "0.5006354000, 0.5070349000, 0.5209054000, 0.5518923000, 0.6322072000, 0.8632844000, 1.5393135000", \ - "0.5131978000, 0.5195176000, 0.5335894000, 0.5643231000, 0.6445486000, 0.8759715000, 1.5501265000", \ - "0.5441849000, 0.5505837000, 0.5644421000, 0.5954131000, 0.6757394000, 0.9068185000, 1.5835114000", \ - "0.6145719000, 0.6209193000, 0.6348982000, 0.6657329000, 0.7461110000, 0.9769409000, 1.6530290000", \ - "0.7392129000, 0.7456168000, 0.7594805000, 0.7904654000, 0.8707812000, 1.1018603000, 1.7758524000", \ - "0.9295227000, 0.9358828000, 0.9497857000, 0.9805695000, 1.0610020000, 1.2916317000, 1.9667528000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0201573000, 0.0232459000, 0.0306186000, 0.0486452000, 0.0965352000, 0.2431940000, 0.6940848000", \ - "0.0201437000, 0.0232326000, 0.0306586000, 0.0486549000, 0.0965757000, 0.2431721000, 0.6876032000", \ - "0.0201667000, 0.0232569000, 0.0306308000, 0.0486124000, 0.0960247000, 0.2429552000, 0.6900953000", \ - "0.0202455000, 0.0233484000, 0.0308481000, 0.0484582000, 0.0961830000, 0.2426410000, 0.6931582000", \ - "0.0202019000, 0.0233392000, 0.0305482000, 0.0483223000, 0.0964494000, 0.2421681000, 0.6853469000", \ - "0.0201581000, 0.0232498000, 0.0308296000, 0.0482484000, 0.0962860000, 0.2430605000, 0.6859591000", \ - "0.0201717000, 0.0232519000, 0.0309418000, 0.0486065000, 0.0960826000, 0.2419765000, 0.6944766000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0251050000, 0.0294903000, 0.0409939000, 0.0752368000, 0.1855240000, 0.5167228000, 1.4945660000", \ - "0.0251651000, 0.0295626000, 0.0409769000, 0.0753114000, 0.1853144000, 0.5173152000, 1.4937516000", \ - "0.0251410000, 0.0297028000, 0.0410298000, 0.0752777000, 0.1852855000, 0.5176567000, 1.4939925000", \ - "0.0252007000, 0.0296153000, 0.0409639000, 0.0753174000, 0.1853070000, 0.5171768000, 1.4944919000", \ - "0.0251212000, 0.0297909000, 0.0410251000, 0.0752155000, 0.1853753000, 0.5164013000, 1.4976937000", \ - "0.0251700000, 0.0295755000, 0.0409753000, 0.0753103000, 0.1853055000, 0.5171507000, 1.4917667000", \ - "0.0252085000, 0.0295810000, 0.0411068000, 0.0752978000, 0.1851638000, 0.5174594000, 1.4949680000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.3569500000, 0.3619844000, 0.3731203000, 0.3956128000, 0.4426570000, 0.5597244000, 0.8931262000", \ - "0.3622413000, 0.3672809000, 0.3783640000, 0.4008872000, 0.4480329000, 0.5649282000, 0.8983347000", \ - "0.3747519000, 0.3797861000, 0.3908745000, 0.4133839000, 0.4605446000, 0.5774463000, 0.9108437000", \ - "0.4064584000, 0.4114798000, 0.4225946000, 0.4451139000, 0.4922558000, 0.6092485000, 0.9423490000", \ - "0.4776291000, 0.4826729000, 0.4937882000, 0.5163199000, 0.5633441000, 0.6804374000, 1.0136628000", \ - "0.6092404000, 0.6143447000, 0.6254986000, 0.6480298000, 0.6950774000, 0.8121235000, 1.1454626000", \ - "0.8190955000, 0.8241580000, 0.8353403000, 0.8578829000, 0.9050162000, 1.0220408000, 1.3553527000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0210729000, 0.0239388000, 0.0316691000, 0.0491964000, 0.0973032000, 0.2428239000, 0.6870486000", \ - "0.0208970000, 0.0240413000, 0.0314562000, 0.0494659000, 0.0968653000, 0.2427730000, 0.6874631000", \ - "0.0208662000, 0.0240445000, 0.0314135000, 0.0495144000, 0.0968391000, 0.2428051000, 0.6881803000", \ - "0.0208755000, 0.0240514000, 0.0314949000, 0.0494066000, 0.0971266000, 0.2428580000, 0.6877711000", \ - "0.0210764000, 0.0243349000, 0.0315942000, 0.0492395000, 0.0973115000, 0.2426421000, 0.6885970000", \ - "0.0211746000, 0.0241588000, 0.0316939000, 0.0492636000, 0.0970446000, 0.2428679000, 0.6881231000", \ - "0.0209860000, 0.0241299000, 0.0321432000, 0.0493834000, 0.0966777000, 0.2428122000, 0.6875218000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.2564176000, 0.2614302000, 0.2725387000, 0.2950076000, 0.3421301000, 0.4591907000, 0.7924238000", \ - "0.2612437000, 0.2662476000, 0.2773562000, 0.2998325000, 0.3470260000, 0.4640048000, 0.7973817000", \ - "0.2711862000, 0.2762307000, 0.2873224000, 0.3098577000, 0.3568919000, 0.4740291000, 0.8071379000", \ - "0.2926458000, 0.2976569000, 0.3087689000, 0.3312862000, 0.3784337000, 0.4953704000, 0.8288411000", \ - "0.3408331000, 0.3458815000, 0.3569794000, 0.3795236000, 0.4265699000, 0.5437021000, 0.8769099000", \ - "0.4302336000, 0.4353806000, 0.4467414000, 0.4693780000, 0.5167812000, 0.6339890000, 0.9672280000", \ - "0.5529300000, 0.5583712000, 0.5702434000, 0.5937570000, 0.6416908000, 0.7590423000, 1.0925317000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.4224749000, 0.4293239000, 0.4441836000, 0.4758974000, 0.5563016000, 0.7871183000, 1.4626006000", \ - "0.4277420000, 0.4345400000, 0.4494435000, 0.4810595000, 0.5615504000, 0.7921701000, 1.4684824000", \ - "0.4408006000, 0.4476916000, 0.4624884000, 0.4941161000, 0.5745947000, 0.8057763000, 1.4800906000", \ - "0.4725484000, 0.4794249000, 0.4942122000, 0.5259663000, 0.6062797000, 0.8372941000, 1.5144710000", \ - "0.5485211000, 0.5554448000, 0.5701400000, 0.6019671000, 0.6822549000, 0.9132370000, 1.5878433000", \ - "0.7268801000, 0.7337704000, 0.7485358000, 0.7801466000, 0.8606407000, 1.0917617000, 1.7661357000", \ - "1.1070097000, 1.1143877000, 1.1301959000, 1.1625885000, 1.2432194000, 1.4740369000, 2.1501847000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0208376000, 0.0239501000, 0.0314154000, 0.0493645000, 0.0969845000, 0.2427779000, 0.6871465000", \ - "0.0208271000, 0.0239649000, 0.0313758000, 0.0494088000, 0.0968049000, 0.2427891000, 0.6869477000", \ - "0.0209953000, 0.0242384000, 0.0314810000, 0.0492280000, 0.0972327000, 0.2427051000, 0.6877030000", \ - "0.0210263000, 0.0242703000, 0.0314585000, 0.0493937000, 0.0969478000, 0.2427619000, 0.6885201000", \ - "0.0210291000, 0.0242992000, 0.0314454000, 0.0492789000, 0.0972438000, 0.2424513000, 0.6875051000", \ - "0.0216658000, 0.0248560000, 0.0320964000, 0.0501723000, 0.0970783000, 0.2425572000, 0.6878934000", \ - "0.0238759000, 0.0271400000, 0.0346973000, 0.0518432000, 0.0986450000, 0.2434849000, 0.6856774000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0280258000, 0.0323414000, 0.0436556000, 0.0766772000, 0.1857171000, 0.5163333000, 1.4912522000", \ - "0.0278694000, 0.0321259000, 0.0438937000, 0.0767928000, 0.1855847000, 0.5176554000, 1.4942477000", \ - "0.0278744000, 0.0324466000, 0.0435953000, 0.0767825000, 0.1854573000, 0.5177235000, 1.4913802000", \ - "0.0278548000, 0.0325195000, 0.0438040000, 0.0767411000, 0.1855839000, 0.5174336000, 1.4899287000", \ - "0.0279749000, 0.0324133000, 0.0435580000, 0.0768631000, 0.1858638000, 0.5168027000, 1.4892525000", \ - "0.0278495000, 0.0324141000, 0.0438861000, 0.0767792000, 0.1859082000, 0.5173258000, 1.4936221000", \ - "0.0305126000, 0.0349375000, 0.0463838000, 0.0784154000, 0.1860613000, 0.5173134000, 1.4933341000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.013476100, -0.007808700, 0.0038433000, 0.0171758000, 0.0065654000, -0.081863800, -0.379520200", \ - "-0.013413300, -0.007758400, 0.0038717000, 0.0171706000, 0.0064893000, -0.081951100, -0.379598300", \ - "-0.013259300, -0.007611400, 0.0040074000, 0.0172783000, 0.0065403000, -0.081860900, -0.379524200", \ - "-0.013296300, -0.007675400, 0.0038984000, 0.0170793000, 0.0062984000, -0.082157100, -0.379820700", \ - "-0.013354200, -0.007735700, 0.0038050000, 0.0169635000, 0.0061589000, -0.082334900, -0.380016000", \ - "-0.013480200, -0.007877700, 0.0036513000, 0.0167671000, 0.0059716000, -0.082507300, -0.380098300", \ - "-0.013736600, -0.008091600, 0.0035349000, 0.0167024000, 0.0060748000, -0.081939800, -0.379541200"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.014966100, -0.011481700, -0.002692200, 0.0173191000, 0.0612639000, 0.1706042000, 0.4775002000", \ - "-0.014900900, -0.011420700, -0.002646600, 0.0173734000, 0.0614351000, 0.1705743000, 0.4750387000", \ - "-0.014748900, -0.011282700, -0.002544800, 0.0174225000, 0.0614160000, 0.1704346000, 0.4750288000", \ - "-0.014780600, -0.011332100, -0.002622100, 0.0172729000, 0.0611449000, 0.1702684000, 0.4746105000", \ - "-0.014842800, -0.011400100, -0.002726200, 0.0171496000, 0.0609693000, 0.1704520000, 0.4735776000", \ - "-0.014966300, -0.011527300, -0.002845600, 0.0170281000, 0.0609239000, 0.1698528000, 0.4761877000", \ - "-0.015228400, -0.011747200, -0.002996600, 0.0170494000, 0.0612463000, 0.1704112000, 0.4744893000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.004178200, -0.000159300, 0.0097846000, 0.0326144000, 0.0804297000, 0.1912296000, 0.4951224000", \ - "-0.004137000, -0.000126900, 0.0097786000, 0.0326240000, 0.0803886000, 0.1915080000, 0.4956842000", \ - "-0.004037400, -3.84500e-05, 0.0098461000, 0.0326603000, 0.0803854000, 0.1911351000, 0.4951339000", \ - "-0.004068300, -7.90000e-05, 0.0098098000, 0.0326044000, 0.0803131000, 0.1911612000, 0.4957210000", \ - "-0.004134400, -0.000155400, 0.0096869000, 0.0324272000, 0.0800889000, 0.1908029000, 0.4947644000", \ - "-0.004269800, -0.000299700, 0.0095395000, 0.0321836000, 0.0797697000, 0.1904695000, 0.4949565000", \ - "-0.004411000, -0.000143100, 0.0103750000, 0.0330539000, 0.0796050000, 0.1902904000, 0.4951534000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0012235000, 0.0073562000, 0.0200119000, 0.0348383000, 0.0259699000, -0.060895200, -0.357806900", \ - "0.0012190000, 0.0073384000, 0.0199611000, 0.0347551000, 0.0258022000, -0.061127600, -0.358110200", \ - "0.0012171000, 0.0073185000, 0.0198962000, 0.0345811000, 0.0255906000, -0.061374500, -0.358364500", \ - "0.0012026000, 0.0072897000, 0.0198529000, 0.0344933000, 0.0255109000, -0.061532200, -0.358517000", \ - "0.0011749000, 0.0072404000, 0.0197402000, 0.0342966000, 0.0251183000, -0.061896100, -0.358855500", \ - "0.0011241000, 0.0071628000, 0.0196107000, 0.0340021000, 0.0247226000, -0.062439900, -0.359336500", \ - "0.0011122000, 0.0072628000, 0.0198846000, 0.0344209000, 0.0250764000, -0.062106000, -0.358990800"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0041299000, 0.0070904000, 0.0146812000, 0.0337384000, 0.0778454000, 0.1861175000, 0.4889928000", \ - "0.0041507000, 0.0071087000, 0.0146959000, 0.0337497000, 0.0778442000, 0.1858724000, 0.4892711000", \ - "0.0041933000, 0.0071467000, 0.0147064000, 0.0337361000, 0.0777015000, 0.1861670000, 0.4895061000", \ - "0.0041774000, 0.0070978000, 0.0146046000, 0.0335392000, 0.0774036000, 0.1857269000, 0.4886537000", \ - "0.0041681000, 0.0070683000, 0.0144972000, 0.0332385000, 0.0768523000, 0.1850578000, 0.4883267000", \ - "0.0041890000, 0.0071046000, 0.0145781000, 0.0332356000, 0.0764008000, 0.1844872000, 0.4881155000", \ - "0.0043723000, 0.0075617000, 0.0156551000, 0.0343006000, 0.0765542000, 0.1846870000, 0.4876137000"); - } - } - max_capacitance : 0.2884010000; - max_transition : 1.5033670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3763170000, 0.3843919000, 0.4022006000, 0.4373844000, 0.5041373000, 0.6392230000, 0.9662938000", \ - "0.3808234000, 0.3888878000, 0.4067260000, 0.4419132000, 0.5086438000, 0.6437326000, 0.9705128000", \ - "0.3939042000, 0.4019684000, 0.4197971000, 0.4549827000, 0.5217258000, 0.6568194000, 0.9838784000", \ - "0.4246916000, 0.4327795000, 0.4505756000, 0.4857624000, 0.5525091000, 0.6875935000, 1.0146693000", \ - "0.4944100000, 0.5024735000, 0.5203009000, 0.5554834000, 0.6222327000, 0.7573190000, 1.0843944000", \ - "0.6187532000, 0.6267971000, 0.6446536000, 0.6798690000, 0.7465731000, 0.8816615000, 1.2084892000", \ - "0.8099303000, 0.8180147000, 0.8358883000, 0.8710416000, 0.9377908000, 1.0729271000, 1.3998034000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4754696000, 0.4830780000, 0.5008433000, 0.5392443000, 0.6287660000, 0.8655988000, 1.5396003000", \ - "0.4805815000, 0.4882857000, 0.5060173000, 0.5444646000, 0.6339805000, 0.8713137000, 1.5456157000", \ - "0.4931007000, 0.5008496000, 0.5185862000, 0.5570550000, 0.6465295000, 0.8841574000, 1.5580285000", \ - "0.5235747000, 0.5313353000, 0.5490779000, 0.5875020000, 0.6769806000, 0.9139453000, 1.5898461000", \ - "0.5945758000, 0.6022753000, 0.6199652000, 0.6584014000, 0.7478982000, 0.9848462000, 1.6619591000", \ - "0.7205400000, 0.7282464000, 0.7460075000, 0.7844685000, 0.8739461000, 1.1111632000, 1.7870448000", \ - "0.9166170000, 0.9243228000, 0.9420562000, 0.9805304000, 1.0700153000, 1.3070661000, 1.9858468000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0370523000, 0.0419324000, 0.0533276000, 0.0772435000, 0.1307089000, 0.2660635000, 0.6779193000", \ - "0.0370687000, 0.0419386000, 0.0534289000, 0.0767435000, 0.1306876000, 0.2660154000, 0.6764859000", \ - "0.0370633000, 0.0419384000, 0.0533073000, 0.0768195000, 0.1306748000, 0.2659988000, 0.6776751000", \ - "0.0370477000, 0.0419122000, 0.0532975000, 0.0768258000, 0.1306663000, 0.2660959000, 0.6747758000", \ - "0.0370646000, 0.0419414000, 0.0533103000, 0.0768253000, 0.1306870000, 0.2661036000, 0.6780513000", \ - "0.0369792000, 0.0419855000, 0.0533307000, 0.0768537000, 0.1306940000, 0.2661192000, 0.6766238000", \ - "0.0370948000, 0.0420519000, 0.0532604000, 0.0777762000, 0.1305829000, 0.2660807000, 0.6781769000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0305772000, 0.0364714000, 0.0513931000, 0.0896778000, 0.2007032000, 0.5296048000, 1.5033670000", \ - "0.0305755000, 0.0364470000, 0.0513472000, 0.0896054000, 0.2001613000, 0.5278695000, 1.4977162000", \ - "0.0305543000, 0.0364010000, 0.0512663000, 0.0896626000, 0.2001110000, 0.5286631000, 1.4981242000", \ - "0.0305773000, 0.0363822000, 0.0513131000, 0.0896417000, 0.2005884000, 0.5287522000, 1.4961706000", \ - "0.0305969000, 0.0363960000, 0.0512587000, 0.0896154000, 0.2005280000, 0.5286129000, 1.4948237000", \ - "0.0306586000, 0.0364783000, 0.0513742000, 0.0897105000, 0.2004444000, 0.5291740000, 1.4993334000", \ - "0.0305771000, 0.0364532000, 0.0512186000, 0.0895857000, 0.2001291000, 0.5276284000, 1.4972554000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.2579718000, 0.2662404000, 0.2849825000, 0.3252107000, 0.4183699000, 0.6589023000, 1.3327327000", \ - "0.2631244000, 0.2713303000, 0.2900478000, 0.3302696000, 0.4235161000, 0.6641178000, 1.3385035000", \ - "0.2759796000, 0.2842035000, 0.3029214000, 0.3432003000, 0.4364481000, 0.6767924000, 1.3501018000", \ - "0.3070084000, 0.3151611000, 0.3338586000, 0.3741493000, 0.4673684000, 0.7078765000, 1.3825232000", \ - "0.3782418000, 0.3864337000, 0.4051553000, 0.4453937000, 0.5386382000, 0.7790814000, 1.4524060000", \ - "0.5102199000, 0.5184727000, 0.5371878000, 0.5774532000, 0.6708721000, 0.9113459000, 1.5859747000", \ - "0.7187809000, 0.7272160000, 0.7465111000, 0.7874764000, 0.8811937000, 1.1216489000, 1.7961473000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0326389000, 0.0389085000, 0.0545597000, 0.0940370000, 0.2072846000, 0.5333507000, 1.4960871000", \ - "0.0326196000, 0.0390445000, 0.0545900000, 0.0938518000, 0.2073848000, 0.5314798000, 1.4942110000", \ - "0.0325565000, 0.0390432000, 0.0545643000, 0.0938117000, 0.2074500000, 0.5318563000, 1.4957408000", \ - "0.0327080000, 0.0388376000, 0.0544156000, 0.0940721000, 0.2075588000, 0.5316399000, 1.4920928000", \ - "0.0326710000, 0.0390309000, 0.0546622000, 0.0939512000, 0.2076845000, 0.5319357000, 1.4956139000", \ - "0.0332866000, 0.0391823000, 0.0545846000, 0.0941880000, 0.2073648000, 0.5316025000, 1.4936953000", \ - "0.0348623000, 0.0413633000, 0.0567728000, 0.0958143000, 0.2078697000, 0.5309524000, 1.4938975000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.2840244000, 0.2940421000, 0.3156840000, 0.3568763000, 0.4336555000, 0.5791062000, 0.9118324000", \ - "0.2892669000, 0.2993277000, 0.3209460000, 0.3621923000, 0.4388827000, 0.5843513000, 0.9173692000", \ - "0.3024941000, 0.3125306000, 0.3340317000, 0.3752088000, 0.4519465000, 0.5973877000, 0.9304499000", \ - "0.3343806000, 0.3443502000, 0.3658794000, 0.4070605000, 0.4837159000, 0.6291659000, 0.9621020000", \ - "0.4102363000, 0.4202280000, 0.4417694000, 0.4829302000, 0.5596233000, 0.7051197000, 1.0381752000", \ - "0.5894699000, 0.5993039000, 0.6205453000, 0.6613042000, 0.7377268000, 0.8832052000, 1.2163378000", \ - "0.9502040000, 0.9613732000, 0.9857726000, 1.0330520000, 1.1179807000, 1.2701173000, 1.6047741000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1571745000, 0.1653154000, 0.1840620000, 0.2242950000, 0.3173657000, 0.5576715000, 1.2317614000", \ - "0.1619898000, 0.1701290000, 0.1888710000, 0.2291084000, 0.3221931000, 0.5625730000, 1.2359485000", \ - "0.1718952000, 0.1801483000, 0.1988399000, 0.2390926000, 0.3321684000, 0.5725935000, 1.2474715000", \ - "0.1934017000, 0.2015734000, 0.2202813000, 0.2604924000, 0.3536291000, 0.5940646000, 1.2676989000", \ - "0.2413692000, 0.2496410000, 0.2684963000, 0.3087541000, 0.4019135000, 0.6422802000, 1.3152959000", \ - "0.3228895000, 0.3323538000, 0.3536570000, 0.3973344000, 0.4929182000, 0.7328386000, 1.4074725000", \ - "0.4257004000, 0.4379832000, 0.4651272000, 0.5172880000, 0.6196997000, 0.8604086000, 1.5340766000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0519080000, 0.0569859000, 0.0680630000, 0.0931940000, 0.1481292000, 0.2807891000, 0.6830574000", \ - "0.0519784000, 0.0569527000, 0.0680881000, 0.0931880000, 0.1480642000, 0.2809579000, 0.6816239000", \ - "0.0518302000, 0.0568045000, 0.0680587000, 0.0929660000, 0.1480467000, 0.2808311000, 0.6819342000", \ - "0.0518008000, 0.0567819000, 0.0678475000, 0.0930791000, 0.1480207000, 0.2808920000, 0.6819548000", \ - "0.0518260000, 0.0568121000, 0.0680332000, 0.0930991000, 0.1481966000, 0.2805039000, 0.6826213000", \ - "0.0514759000, 0.0565259000, 0.0676343000, 0.0928684000, 0.1480915000, 0.2807626000, 0.6825895000", \ - "0.0692583000, 0.0740596000, 0.0853881000, 0.1121941000, 0.1650567000, 0.2907655000, 0.6834641000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0325712000, 0.0387431000, 0.0543530000, 0.0938335000, 0.2075386000, 0.5317147000, 1.4935027000", \ - "0.0325354000, 0.0387433000, 0.0543381000, 0.0938543000, 0.2074263000, 0.5317742000, 1.4930300000", \ - "0.0324105000, 0.0388797000, 0.0544411000, 0.0939312000, 0.2069821000, 0.5321171000, 1.4963973000", \ - "0.0325088000, 0.0388857000, 0.0544555000, 0.0939149000, 0.2076045000, 0.5314267000, 1.4957734000", \ - "0.0332692000, 0.0394543000, 0.0547731000, 0.0942030000, 0.2068993000, 0.5317229000, 1.4946612000", \ - "0.0399578000, 0.0466155000, 0.0620999000, 0.1008018000, 0.2100010000, 0.5311183000, 1.4964007000", \ - "0.0548367000, 0.0632438000, 0.0810785000, 0.1188394000, 0.2200218000, 0.5333459000, 1.4950472000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0016230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0129392000, 0.0128486000, 0.0126395000, 0.0126902000, 0.0128071000, 0.0130768000, 0.0136983000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081727000, 0.0081196000, 0.0079971000, 0.0080244000, 0.0080871000, 0.0082320000, 0.0085661000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017090000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0728008000, 0.1966940000, 0.2886536000", \ - "-0.145086600, -0.019972700, 0.0719870000", \ - "-0.394516900, -0.269403000, -0.176222700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0764629000, -0.044988900, -0.125962200", \ - "0.2748190000, 0.1545879000, 0.0723939000", \ - "0.5157044000, 0.3954733000, 0.3145000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2532714000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.059653600, -0.076336600", \ - "-0.226873700, -0.167677700, -0.179477900", \ - "-0.332261100, -0.254754600, -0.253126900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1582500000, 0.1429994000, 0.2463522000", \ - "0.2967917000, 0.2534648000, 0.3104310000", \ - "0.4473450000, 0.3747214000, 0.3999492000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050604000, 0.0050512000, 0.0050299000, 0.0050437000, 0.0050756000, 0.0051492000, 0.0053189000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004934000, -0.004974100, -0.005066600, -0.005069800, -0.005077400, -0.005094600, -0.005134200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035170000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.061476600, 0.0306784000, 0.1519349000", \ - "-0.247625700, -0.156691400, -0.086704400", \ - "-0.454331400, -0.363397100, -0.325148400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0679180000, -0.021795600, -0.053940800", \ - "0.2528463000, 0.1643535000, 0.1322083000", \ - "0.4595521000, 0.3698385000, 0.3413555000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1582500000, 0.2967917000, 0.4473450000", \ - "0.1429994000, 0.2534648000, 0.3747214000", \ - "0.2463522000, 0.3104310000, 0.3999492000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3060000000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.226873700, -0.332261100", \ - "-0.059653600, -0.167677700, -0.254754600", \ - "-0.076336600, -0.179477900, -0.253126900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfbbp_1") { - leakage_power () { - value : 0.0122989000; - when : "!SET_B&!RESET_B&!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0156955000; - when : "SET_B&RESET_B&CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0124999000; - when : "!SET_B&!RESET_B&CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0114743000; - when : "SET_B&!RESET_B&!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0113470000; - when : "SET_B&!RESET_B&!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0140189000; - when : "SET_B&RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0146139000; - when : "SET_B&RESET_B&!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0150225000; - when : "SET_B&RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0136989000; - when : "SET_B&RESET_B&!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0137824000; - when : "!SET_B&RESET_B&CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0116669000; - when : "SET_B&!RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0161108000; - when : "SET_B&RESET_B&CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0154945000; - when : "SET_B&RESET_B&!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0133672000; - when : "!SET_B&RESET_B&CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0126706000; - when : "SET_B&!RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0131661000; - when : "!SET_B&RESET_B&!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0151411000; - when : "SET_B&RESET_B&!CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0124308000; - when : "!SET_B&!RESET_B&!CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0136997000; - when : "!SET_B&RESET_B&!CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0129152000; - when : "!SET_B&!RESET_B&CLK&!D&Q&!Q_N"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__dfbbp"; - cell_leakage_power : 0.0135557500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017920000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0229054000, 0.0227829000, 0.0225003000, 0.0225653000, 0.0227156000, 0.0230618000, 0.0238599000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0278962000, 0.0277581000, 0.0274399000, 0.0274694000, 0.0275375000, 0.0276944000, 0.0280562000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018890000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2697491000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2093310000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0052217000, 0.0051462000, 0.0049723000, 0.0050504000, 0.0052307000, 0.0056465000, 0.0066047000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0003622000, 0.0002965000, 0.0001449000, 0.0001882000, 0.0002883000, 0.0005189000, 0.0010505000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017000000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.3834616000, 0.6804994000", \ - "0.0392396000, 0.2498027000, 0.5480612000", \ - "-0.058823600, 0.1480775000, 0.4475566000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0715801000, 0.1893698000, 0.2764466000", \ - "-0.002264300, 0.1057598000, 0.1806296000", \ - "-0.029526700, 0.0760560000, 0.1472637000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.085890600, -0.298895200, -0.592270900", \ - "0.0233542000, -0.184767600, -0.476922500", \ - "0.1043275000, -0.098911500, -0.388625000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.046828100, -0.163397100, -0.241929000", \ - "0.0209128000, -0.085890600, -0.155877600", \ - "0.0493958000, -0.054966100, -0.122511700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.010614900, -0.005994400, 0.0025284000, 0.0115247000, 0.0054269000, -0.046618700, -0.210030200", \ - "-0.010547300, -0.005938700, 0.0025695000, 0.0115473000, 0.0054589000, -0.046606900, -0.210027700", \ - "-0.010409600, -0.005826500, 0.0026395000, 0.0115192000, 0.0053256000, -0.046790200, -0.210238500", \ - "-0.010439300, -0.005881200, 0.0025367000, 0.0113361000, 0.0050711000, -0.047084000, -0.210558400", \ - "-0.010494600, -0.005962900, 0.0023937000, 0.0111065000, 0.0047817000, -0.047447800, -0.210941900", \ - "-0.010568200, -0.006024700, 0.0023484000, 0.0110754000, 0.0047357000, -0.047451900, -0.210956300", \ - "-0.010695600, -0.006082700, 0.0024409000, 0.0114108000, 0.0052491000, -0.046982300, -0.210396100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.012007800, -0.009054100, -0.002251500, 0.0123952000, 0.0419431000, 0.1089023000, 0.2781323000", \ - "-0.011948000, -0.009015000, -0.002257800, 0.0123935000, 0.0418045000, 0.1085775000, 0.2798717000", \ - "-0.011797600, -0.008875500, -0.002126200, 0.0124582000, 0.0418808000, 0.1092446000, 0.2780983000", \ - "-0.011826400, -0.008925900, -0.002232000, 0.0122516000, 0.0415903000, 0.1083095000, 0.2794371000", \ - "-0.011879100, -0.009002200, -0.002348200, 0.0120437000, 0.0412581000, 0.1081317000, 0.2790388000", \ - "-0.011955000, -0.009078400, -0.002425200, 0.0120361000, 0.0413669000, 0.1079210000, 0.2775125000", \ - "-0.012008400, -0.008944200, -0.001923000, 0.0126207000, 0.0419091000, 0.1084299000, 0.2799343000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002131300, 0.0038374000, 0.0150881000, 0.0281786000, 0.0264407000, -0.022080000, -0.184037700", \ - "-0.002091300, 0.0038662000, 0.0150890000, 0.0281473000, 0.0263956000, -0.022121100, -0.184101800", \ - "-0.001997200, 0.0039575000, 0.0151518000, 0.0281844000, 0.0263980000, -0.022120800, -0.184146000", \ - "-0.002038200, 0.0038979000, 0.0150797000, 0.0280688000, 0.0262270000, -0.022345800, -0.184380900", \ - "-0.002112400, 0.0038076000, 0.0149590000, 0.0278974000, 0.0260103000, -0.022610100, -0.184617300", \ - "-0.002257000, 0.0036510000, 0.0147908000, 0.0277233000, 0.0258115000, -0.022826000, -0.184843900", \ - "-0.002541300, 0.0034543000, 0.0147493000, 0.0278976000, 0.0258813000, -0.023014500, -0.185015300"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0001757000, 0.0049898000, 0.0139016000, 0.0234541000, 0.0182650000, -0.032500200, -0.195612100", \ - "0.0002171000, 0.0050332000, 0.0139314000, 0.0234852000, 0.0182892000, -0.032484200, -0.195611100", \ - "0.0003171000, 0.0051200000, 0.0140064000, 0.0235441000, 0.0183091000, -0.032480600, -0.195578500", \ - "0.0002991000, 0.0050584000, 0.0138756000, 0.0232853000, 0.0179519000, -0.032917600, -0.196053100", \ - "0.0002770000, 0.0049920000, 0.0137192000, 0.0230151000, 0.0174995000, -0.033522700, -0.196715600", \ - "0.0002868000, 0.0049700000, 0.0136446000, 0.0228221000, 0.0171698000, -0.034064700, -0.197295500", \ - "0.0004307000, 0.0052052000, 0.0140395000, 0.0235184000, 0.0178819000, -0.034075300, -0.197330600"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-3.45000e-06, 0.0037956000, 0.0123012000, 0.0300241000, 0.0628374000, 0.1322039000, 0.3033411000", \ - "-1.02000e-05, 0.0037701000, 0.0122463000, 0.0299008000, 0.0626734000, 0.1315139000, 0.3016417000", \ - "-7.10000e-06, 0.0037537000, 0.0121719000, 0.0297630000, 0.0624311000, 0.1311480000, 0.3014002000", \ - "-2.32500e-05, 0.0037280000, 0.0121092000, 0.0296702000, 0.0622163000, 0.1309944000, 0.3023649000", \ - "-5.82000e-05, 0.0036607000, 0.0119981000, 0.0294675000, 0.0619391000, 0.1307431000, 0.3008701000", \ - "-0.000120500, 0.0035646000, 0.0118405000, 0.0291969000, 0.0615091000, 0.1304738000, 0.3018860000", \ - "-0.000197100, 0.0034972000, 0.0117853000, 0.0293411000, 0.0620760000, 0.1309289000, 0.3023457000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5025880000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4039533000, 0.4092296000, 0.4204419000, 0.4436846000, 0.4961129000, 0.6296842000, 0.9821381000", \ - "0.4086175000, 0.4138886000, 0.4251073000, 0.4483200000, 0.5008106000, 0.6343516000, 0.9868231000", \ - "0.4195532000, 0.4248875000, 0.4360719000, 0.4593400000, 0.5117256000, 0.6454468000, 0.9983931000", \ - "0.4452836000, 0.4505566000, 0.4617675000, 0.4849847000, 0.5374570000, 0.6710937000, 1.0234057000", \ - "0.4934014000, 0.4987052000, 0.5098993000, 0.5331193000, 0.5856108000, 0.7191925000, 1.0716139000", \ - "0.5639728000, 0.5692679000, 0.5804762000, 0.6036952000, 0.6560980000, 0.7897050000, 1.1418574000", \ - "0.6552036000, 0.6604736000, 0.6716790000, 0.6948981000, 0.7473747000, 0.8810654000, 1.2331584000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4636423000, 0.4703978000, 0.4854080000, 0.5212972000, 0.6144507000, 0.8591190000, 1.5076738000", \ - "0.4685876000, 0.4752219000, 0.4902113000, 0.5262274000, 0.6192438000, 0.8636630000, 1.5094608000", \ - "0.4795922000, 0.4862304000, 0.5013462000, 0.5372556000, 0.6301383000, 0.8742134000, 1.5190521000", \ - "0.5055953000, 0.5122447000, 0.5273450000, 0.5632610000, 0.6561883000, 0.9006798000, 1.5470619000", \ - "0.5530906000, 0.5598074000, 0.5749050000, 0.6106542000, 0.7037665000, 0.9483704000, 1.5947870000", \ - "0.6202767000, 0.6270074000, 0.6421615000, 0.6780352000, 0.7713262000, 1.0155202000, 1.6592367000", \ - "0.7034734000, 0.7101449000, 0.7253207000, 0.7611444000, 0.8544684000, 1.0989282000, 1.7449191000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0176110000, 0.0217340000, 0.0310132000, 0.0544944000, 0.1180586000, 0.2941295000, 0.7627906000", \ - "0.0175409000, 0.0216467000, 0.0311814000, 0.0544284000, 0.1182901000, 0.2936109000, 0.7652771000", \ - "0.0176047000, 0.0217536000, 0.0311438000, 0.0544421000, 0.1181374000, 0.2939531000, 0.7634909000", \ - "0.0175771000, 0.0216742000, 0.0312100000, 0.0545539000, 0.1179132000, 0.2941286000, 0.7624151000", \ - "0.0175140000, 0.0217741000, 0.0311640000, 0.0544746000, 0.1178652000, 0.2937115000, 0.7626537000", \ - "0.0177662000, 0.0215713000, 0.0309825000, 0.0545130000, 0.1184243000, 0.2941531000, 0.7638183000", \ - "0.0175267000, 0.0217793000, 0.0311899000, 0.0545224000, 0.1179324000, 0.2941825000, 0.7648072000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0234667000, 0.0297125000, 0.0464813000, 0.0945516000, 0.2263394000, 0.5749123000, 1.5005779000", \ - "0.0234154000, 0.0295935000, 0.0464097000, 0.0945352000, 0.2265070000, 0.5748585000, 1.5023726000", \ - "0.0234268000, 0.0295356000, 0.0463298000, 0.0945196000, 0.2262740000, 0.5755212000, 1.5017431000", \ - "0.0234323000, 0.0295437000, 0.0463372000, 0.0944841000, 0.2265388000, 0.5749890000, 1.5025884000", \ - "0.0234252000, 0.0296051000, 0.0464400000, 0.0944117000, 0.2264147000, 0.5751394000, 1.5024757000", \ - "0.0235713000, 0.0297262000, 0.0465383000, 0.0944795000, 0.2260090000, 0.5750500000, 1.4963725000", \ - "0.0234269000, 0.0295138000, 0.0465050000, 0.0945337000, 0.2265600000, 0.5733328000, 1.5005919000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2967494000, 0.3021147000, 0.3134580000, 0.3368799000, 0.3893941000, 0.5230161000, 0.8752900000", \ - "0.3018110000, 0.3071289000, 0.3185061000, 0.3419162000, 0.3943494000, 0.5281043000, 0.8803492000", \ - "0.3149259000, 0.3202734000, 0.3316190000, 0.3550180000, 0.4075392000, 0.5413351000, 0.8935410000", \ - "0.3457712000, 0.3511369000, 0.3624720000, 0.3858941000, 0.4384025000, 0.5722836000, 0.9243149000", \ - "0.4155792000, 0.4209445000, 0.4322934000, 0.4557108000, 0.5082337000, 0.6418609000, 0.9941435000", \ - "0.5426722000, 0.5479656000, 0.5592729000, 0.5827214000, 0.6352980000, 0.7690713000, 1.1213674000", \ - "0.7419366000, 0.7473708000, 0.7587431000, 0.7822518000, 0.8348028000, 0.9686356000, 1.3208046000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0181109000, 0.0219011000, 0.0316433000, 0.0548725000, 0.1183088000, 0.2933212000, 0.7621715000", \ - "0.0179439000, 0.0221820000, 0.0314588000, 0.0549111000, 0.1183012000, 0.2933603000, 0.7625383000", \ - "0.0182641000, 0.0223547000, 0.0316907000, 0.0548511000, 0.1182577000, 0.2935737000, 0.7633681000", \ - "0.0181293000, 0.0219364000, 0.0316052000, 0.0549264000, 0.1183097000, 0.2932350000, 0.7619276000", \ - "0.0181082000, 0.0219282000, 0.0316527000, 0.0548397000, 0.1183098000, 0.2934127000, 0.7635063000", \ - "0.0180267000, 0.0221004000, 0.0315310000, 0.0549698000, 0.1182687000, 0.2934627000, 0.7639789000", \ - "0.0182976000, 0.0225243000, 0.0318738000, 0.0550260000, 0.1185022000, 0.2935618000, 0.7625653000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2002031000, 0.2055225000, 0.2168776000, 0.2402256000, 0.2928631000, 0.4264809000, 0.7788506000", \ - "0.2049883000, 0.2103103000, 0.2216675000, 0.2450143000, 0.2976534000, 0.4312711000, 0.7836132000", \ - "0.2148875000, 0.2202070000, 0.2315771000, 0.2549178000, 0.3074457000, 0.4412357000, 0.7935430000", \ - "0.2362131000, 0.2415570000, 0.2528683000, 0.2762757000, 0.3288325000, 0.4626183000, 0.8150761000", \ - "0.2830661000, 0.2884894000, 0.2998254000, 0.3232644000, 0.3758116000, 0.5095308000, 0.8618591000", \ - "0.3611619000, 0.3666896000, 0.3782653000, 0.4019654000, 0.4548248000, 0.5885110000, 0.9407782000", \ - "0.4591993000, 0.4651643000, 0.4773944000, 0.5016277000, 0.5552154000, 0.6888285000, 1.0410232000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3274920000, 0.3348437000, 0.3506624000, 0.3869837000, 0.4800038000, 0.7243806000, 1.3699463000", \ - "0.3326263000, 0.3399802000, 0.3558311000, 0.3921558000, 0.4851859000, 0.7295820000, 1.3746964000", \ - "0.3456709000, 0.3529467000, 0.3687302000, 0.4050282000, 0.4980201000, 0.7425951000, 1.3864568000", \ - "0.3774392000, 0.3847477000, 0.4005508000, 0.4368691000, 0.5298927000, 0.7744824000, 1.4199690000", \ - "0.4536521000, 0.4609321000, 0.4767149000, 0.5130131000, 0.6060015000, 0.8505902000, 1.4954322000", \ - "0.6320851000, 0.6395222000, 0.6553318000, 0.6916367000, 0.7846634000, 1.0291191000, 1.6753965000", \ - "0.9841062000, 0.9924723000, 1.0093232000, 1.0460272000, 1.1390712000, 1.3832775000, 2.0287656000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0179101000, 0.0222051000, 0.0315170000, 0.0548707000, 0.1179701000, 0.2932213000, 0.7630406000", \ - "0.0179129000, 0.0222017000, 0.0315071000, 0.0548853000, 0.1180039000, 0.2932354000, 0.7623958000", \ - "0.0179146000, 0.0221806000, 0.0314753000, 0.0548856000, 0.1181198000, 0.2939375000, 0.7619537000", \ - "0.0180729000, 0.0221647000, 0.0315931000, 0.0549127000, 0.1182247000, 0.2931578000, 0.7637985000", \ - "0.0183086000, 0.0221011000, 0.0316655000, 0.0548761000, 0.1183032000, 0.2932861000, 0.7627259000", \ - "0.0188332000, 0.0227821000, 0.0323829000, 0.0557304000, 0.1188458000, 0.2937264000, 0.7631682000", \ - "0.0212370000, 0.0251822000, 0.0345114000, 0.0572635000, 0.1197706000, 0.2935571000, 0.7597689000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0265332000, 0.0324946000, 0.0485333000, 0.0952848000, 0.2266342000, 0.5753942000, 1.4999639000", \ - "0.0264523000, 0.0324688000, 0.0485327000, 0.0953747000, 0.2261401000, 0.5740494000, 1.4991522000", \ - "0.0266518000, 0.0325106000, 0.0485532000, 0.0952770000, 0.2260631000, 0.5757561000, 1.4995526000", \ - "0.0264272000, 0.0324516000, 0.0485013000, 0.0953984000, 0.2265856000, 0.5752716000, 1.4969032000", \ - "0.0266500000, 0.0325132000, 0.0485542000, 0.0952778000, 0.2259917000, 0.5740220000, 1.4993594000", \ - "0.0266091000, 0.0326940000, 0.0486461000, 0.0953800000, 0.2262089000, 0.5740090000, 1.4963828000", \ - "0.0311481000, 0.0369449000, 0.0517973000, 0.0965856000, 0.2265411000, 0.5740936000, 1.4980801000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.010395600, -0.005620000, 0.0030618000, 0.0123932000, 0.0079016000, -0.038555000, -0.185511400", \ - "-0.010336000, -0.005566100, 0.0031065000, 0.0124106000, 0.0078689000, -0.038569100, -0.185555800", \ - "-0.010183500, -0.005433100, 0.0032166000, 0.0124791000, 0.0078932000, -0.038553900, -0.185592200", \ - "-0.010225300, -0.005504200, 0.0030748000, 0.0122317000, 0.0075658000, -0.038987500, -0.186006300", \ - "-0.010273700, -0.005572700, 0.0029742000, 0.0120845000, 0.0073438000, -0.039231300, -0.186276700", \ - "-0.010341400, -0.005635400, 0.0029243000, 0.0120604000, 0.0073798000, -0.039192400, -0.186210900", \ - "-0.010463300, -0.005665100, 0.0030564000, 0.0124531000, 0.0079825000, -0.038748700, -0.185718100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.011941500, -0.008979500, -0.002307400, 0.0115129000, 0.0391310000, 0.1009413000, 0.2554813000", \ - "-0.011878500, -0.008923800, -0.002263500, 0.0115289000, 0.0390896000, 0.1008731000, 0.2556975000", \ - "-0.011738300, -0.008809500, -0.002201000, 0.0115263000, 0.0390305000, 0.1008905000, 0.2548255000", \ - "-0.011772000, -0.008870300, -0.002315700, 0.0113225000, 0.0387367000, 0.1009614000, 0.2549831000", \ - "-0.011823300, -0.008944700, -0.002433300, 0.0111503000, 0.0384910000, 0.1006777000, 0.2546497000", \ - "-0.011907200, -0.009032300, -0.002538300, 0.0110159000, 0.0383999000, 0.1000332000, 0.2533281000", \ - "-0.012020200, -0.009053800, -0.002355900, 0.0114085000, 0.0387563000, 0.1005819000, 0.2535738000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.003648500, 0.0003524000, 0.0090323000, 0.0280329000, 0.0607363000, 0.1252276000, 0.2797601000", \ - "-0.003613900, 0.0003686000, 0.0090554000, 0.0280122000, 0.0607072000, 0.1254051000, 0.2799709000", \ - "-0.003515000, 0.0004703000, 0.0091391000, 0.0281102000, 0.0607291000, 0.1252003000, 0.2797542000", \ - "-0.003556000, 0.0004134000, 0.0090537000, 0.0279539000, 0.0605305000, 0.1249706000, 0.2795542000", \ - "-0.003628400, 0.0003254000, 0.0089323000, 0.0278000000, 0.0603171000, 0.1246850000, 0.2790320000", \ - "-0.003777700, 0.0001722000, 0.0087645000, 0.0275901000, 0.0600790000, 0.1243913000, 0.2787535000", \ - "-0.003807700, 0.0005801000, 0.0100719000, 0.0279767000, 0.0600177000, 0.1244732000, 0.2792338000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0016838000, 0.0073933000, 0.0179177000, 0.0299693000, 0.0284358000, -0.015720200, -0.161503300", \ - "0.0016739000, 0.0073629000, 0.0178514000, 0.0298493000, 0.0282750000, -0.015943100, -0.161741800", \ - "0.0016754000, 0.0073392000, 0.0177752000, 0.0296932000, 0.0280736000, -0.016180500, -0.162010300", \ - "0.0016589000, 0.0073080000, 0.0177272000, 0.0295847000, 0.0279279000, -0.016342100, -0.162182400", \ - "0.0016263000, 0.0072488000, 0.0176080000, 0.0293980000, 0.0276497000, -0.016663000, -0.162510100", \ - "0.0015696000, 0.0071647000, 0.0174706000, 0.0291350000, 0.0272352000, -0.017126700, -0.162938900", \ - "0.0015396000, 0.0071944000, 0.0175627000, 0.0292501000, 0.0275971000, -0.016686300, -0.162434900"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.001386100, 0.0014424000, 0.0078112000, 0.0233515000, 0.0526226000, 0.1148037000, 0.2679652000", \ - "-0.001341600, 0.0014847000, 0.0078615000, 0.0233905000, 0.0526379000, 0.1150668000, 0.2683634000", \ - "-0.001241900, 0.0015759000, 0.0079242000, 0.0234404000, 0.0527125000, 0.1148554000, 0.2683034000", \ - "-0.001260100, 0.0015140000, 0.0078088000, 0.0231948000, 0.0523084000, 0.1143291000, 0.2676387000", \ - "-0.001264600, 0.0014836000, 0.0077092000, 0.0229345000, 0.0518112000, 0.1139114000, 0.2670776000", \ - "-0.001219900, 0.0015492000, 0.0077944000, 0.0227782000, 0.0513487000, 0.1132609000, 0.2664771000", \ - "-0.000873700, 0.0022695000, 0.0093067000, 0.0235111000, 0.0513825000, 0.1133925000, 0.2661127000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.5004800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.3931175000, 0.4023883000, 0.4214331000, 0.4578175000, 0.5266816000, 0.6651807000, 0.9951560000", \ - "0.3977427000, 0.4069947000, 0.4260284000, 0.4624481000, 0.5313278000, 0.6697969000, 0.9993718000", \ - "0.4087553000, 0.4180210000, 0.4371030000, 0.4734775000, 0.5423611000, 0.6808427000, 1.0104344000", \ - "0.4346894000, 0.4439281000, 0.4629115000, 0.4994100000, 0.5682889000, 0.7067529000, 1.0366895000", \ - "0.4822269000, 0.4915004000, 0.5105728000, 0.5469286000, 0.6158065000, 0.7543056000, 1.0840331000", \ - "0.5495100000, 0.5587697000, 0.5777837000, 0.6142423000, 0.6831086000, 0.8216151000, 1.1514264000", \ - "0.6325974000, 0.6418331000, 0.6609048000, 0.6972878000, 0.7661742000, 0.9046758000, 1.2344549000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.3465939000, 0.3556435000, 0.3753984000, 0.4179360000, 0.5172140000, 0.7641695000, 1.4043884000", \ - "0.3512091000, 0.3602956000, 0.3800513000, 0.4225941000, 0.5218870000, 0.7685330000, 1.4054787000", \ - "0.3621631000, 0.3712761000, 0.3910239000, 0.4335713000, 0.5328449000, 0.7795686000, 1.4176900000", \ - "0.3878091000, 0.3968942000, 0.4166447000, 0.4591943000, 0.5584879000, 0.8055728000, 1.4451529000", \ - "0.4361983000, 0.4453033000, 0.4650506000, 0.5076116000, 0.6069221000, 0.8538156000, 1.4934668000", \ - "0.5063581000, 0.5154568000, 0.5352089000, 0.5777472000, 0.6770446000, 0.9241370000, 1.5635034000", \ - "0.5977575000, 0.6068733000, 0.6266288000, 0.6691873000, 0.7684818000, 1.0156903000, 1.6547206000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0363835000, 0.0422603000, 0.0556885000, 0.0841618000, 0.1457096000, 0.2979125000, 0.7271648000", \ - "0.0363956000, 0.0422507000, 0.0556096000, 0.0841542000, 0.1455508000, 0.2975634000, 0.7269619000", \ - "0.0361580000, 0.0421165000, 0.0557146000, 0.0841615000, 0.1455553000, 0.2976979000, 0.7239611000", \ - "0.0360721000, 0.0421373000, 0.0557712000, 0.0839962000, 0.1456077000, 0.2979377000, 0.7292654000", \ - "0.0362254000, 0.0426438000, 0.0558859000, 0.0840772000, 0.1457267000, 0.2981101000, 0.7232062000", \ - "0.0360656000, 0.0421524000, 0.0555211000, 0.0840845000, 0.1456280000, 0.2980349000, 0.7298426000", \ - "0.0361350000, 0.0421209000, 0.0557299000, 0.0840748000, 0.1457133000, 0.2981022000, 0.7213380000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0332469000, 0.0409900000, 0.0599744000, 0.1093995000, 0.2390713000, 0.5850410000, 1.4973788000", \ - "0.0331778000, 0.0409676000, 0.0599714000, 0.1093747000, 0.2387962000, 0.5849085000, 1.5004799000", \ - "0.0331777000, 0.0410046000, 0.0599174000, 0.1093323000, 0.2390003000, 0.5843763000, 1.4951687000", \ - "0.0331639000, 0.0409779000, 0.0598748000, 0.1093087000, 0.2390299000, 0.5854448000, 1.4975506000", \ - "0.0333056000, 0.0410591000, 0.0599779000, 0.1093274000, 0.2391751000, 0.5848795000, 1.4970949000", \ - "0.0332717000, 0.0411040000, 0.0598534000, 0.1093602000, 0.2390122000, 0.5860264000, 1.4907339000", \ - "0.0332557000, 0.0410863000, 0.0600782000, 0.1093720000, 0.2387102000, 0.5842072000, 1.4953185000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2385995000, 0.2481496000, 0.2688600000, 0.3131994000, 0.4162598000, 0.6657416000, 1.3028342000", \ - "0.2435845000, 0.2531546000, 0.2738246000, 0.3181782000, 0.4212483000, 0.6707470000, 1.3084304000", \ - "0.2564480000, 0.2660029000, 0.2867427000, 0.3310867000, 0.4341423000, 0.6837132000, 1.3216841000", \ - "0.2875788000, 0.2971377000, 0.3178919000, 0.3622266000, 0.4652875000, 0.7148779000, 1.3530171000", \ - "0.3573035000, 0.3668590000, 0.3876172000, 0.4319509000, 0.5350134000, 0.7844905000, 1.4218271000", \ - "0.4845214000, 0.4941962000, 0.5150514000, 0.5596619000, 0.6629053000, 0.9123096000, 1.5497659000", \ - "0.6828862000, 0.6928831000, 0.7142192000, 0.7594926000, 0.8635104000, 1.1129231000, 1.7506068000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0351234000, 0.0433882000, 0.0629475000, 0.1140430000, 0.2460782000, 0.5871504000, 1.4944840000", \ - "0.0351852000, 0.0432924000, 0.0629607000, 0.1139346000, 0.2467565000, 0.5868377000, 1.4936452000", \ - "0.0351233000, 0.0433782000, 0.0628907000, 0.1140388000, 0.2468674000, 0.5872465000, 1.4945200000", \ - "0.0351381000, 0.0434400000, 0.0629625000, 0.1139832000, 0.2468949000, 0.5875046000, 1.4945408000", \ - "0.0351444000, 0.0434108000, 0.0629251000, 0.1140574000, 0.2467742000, 0.5866523000, 1.4905107000", \ - "0.0358719000, 0.0440401000, 0.0636084000, 0.1145421000, 0.2464876000, 0.5872652000, 1.4943407000", \ - "0.0376570000, 0.0458641000, 0.0654704000, 0.1162860000, 0.2479127000, 0.5878166000, 1.4927245000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2450007000, 0.2564841000, 0.2804037000, 0.3260429000, 0.4085008000, 0.5572215000, 0.8909883000", \ - "0.2501011000, 0.2615943000, 0.2855231000, 0.3311930000, 0.4136338000, 0.5623345000, 0.8962810000", \ - "0.2630551000, 0.2744238000, 0.2984699000, 0.3441408000, 0.4265384000, 0.5752310000, 0.9089647000", \ - "0.2948286000, 0.3063463000, 0.3302965000, 0.3759225000, 0.4583370000, 0.6070217000, 0.9408768000", \ - "0.3710681000, 0.3824317000, 0.4064322000, 0.4519978000, 0.5344124000, 0.6832104000, 1.0171461000", \ - "0.5487699000, 0.5604088000, 0.5845471000, 0.6300692000, 0.7123053000, 0.8611340000, 1.1949282000", \ - "0.8787109000, 0.8951058000, 0.9280147000, 0.9846163000, 1.0770945000, 1.2323657000, 1.5677386000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1418101000, 0.1513665000, 0.1720296000, 0.2163608000, 0.3192191000, 0.5686082000, 1.2063777000", \ - "0.1465985000, 0.1561545000, 0.1768164000, 0.2211521000, 0.3240293000, 0.5734266000, 1.2118834000", \ - "0.1564957000, 0.1660468000, 0.1867191000, 0.2310458000, 0.3339485000, 0.5833729000, 1.2202522000", \ - "0.1778370000, 0.1873642000, 0.2080642000, 0.2523301000, 0.3552589000, 0.6047386000, 1.2422062000", \ - "0.2238891000, 0.2337048000, 0.2546323000, 0.2991403000, 0.4022189000, 0.6515353000, 1.2895321000", \ - "0.2967399000, 0.3080394000, 0.3314164000, 0.3787469000, 0.4839245000, 0.7331225000, 1.3710711000", \ - "0.3810673000, 0.3959570000, 0.4257815000, 0.4808799000, 0.5915932000, 0.8414084000, 1.4787864000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0474586000, 0.0551601000, 0.0715627000, 0.1058876000, 0.1686415000, 0.3134767000, 0.7304584000", \ - "0.0474971000, 0.0551633000, 0.0715830000, 0.1059572000, 0.1684913000, 0.3132981000, 0.7268736000", \ - "0.0473999000, 0.0552227000, 0.0715750000, 0.1058508000, 0.1685534000, 0.3131231000, 0.7310630000", \ - "0.0474777000, 0.0551555000, 0.0717285000, 0.1059356000, 0.1685794000, 0.3133005000, 0.7270700000", \ - "0.0472987000, 0.0551365000, 0.0715644000, 0.1059663000, 0.1686753000, 0.3130269000, 0.7297014000", \ - "0.0500130000, 0.0574539000, 0.0732910000, 0.1068802000, 0.1684653000, 0.3130181000, 0.7265465000", \ - "0.0783504000, 0.0876334000, 0.1047964000, 0.1351386000, 0.1884475000, 0.3235185000, 0.7308282000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0350127000, 0.0431593000, 0.0628836000, 0.1138162000, 0.2468309000, 0.5878543000, 1.4891128000", \ - "0.0349979000, 0.0431822000, 0.0628791000, 0.1138234000, 0.2468423000, 0.5872328000, 1.4918446000", \ - "0.0349870000, 0.0432054000, 0.0628226000, 0.1138558000, 0.2468067000, 0.5872309000, 1.4920619000", \ - "0.0349076000, 0.0432292000, 0.0627766000, 0.1139136000, 0.2466366000, 0.5867717000, 1.4931402000", \ - "0.0362516000, 0.0443930000, 0.0638647000, 0.1144140000, 0.2467956000, 0.5867428000, 1.4952128000", \ - "0.0434374000, 0.0517450000, 0.0712668000, 0.1206896000, 0.2489325000, 0.5869861000, 1.4919568000", \ - "0.0596089000, 0.0696599000, 0.0896787000, 0.1369158000, 0.2571940000, 0.5887652000, 1.4942992000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0015970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0128103000, 0.0127233000, 0.0125227000, 0.0125776000, 0.0127042000, 0.0129960000, 0.0136688000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080234000, 0.0079710000, 0.0078502000, 0.0078814000, 0.0079534000, 0.0081194000, 0.0085020000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016670000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0642559000, 0.1905905000, 0.2837708000", \ - "-0.054754600, 0.0679180000, 0.1574362000", \ - "-0.139390000, -0.017938200, 0.0679180000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.038283200, -0.160955700, -0.249253300", \ - "0.0782858000, -0.041945300, -0.127801400", \ - "0.1653626000, 0.0426901000, -0.041945300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2181191000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.060874400, -0.075115900", \ - "-0.226873700, -0.167677700, -0.175815800", \ - "-0.331040400, -0.253533800, -0.248244100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.1039368000, 0.1865378000", \ - "0.2687155000, 0.2144023000, 0.2481751000", \ - "0.3985169000, 0.3246725000, 0.3267070000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050813000, 0.0050664000, 0.0050320000, 0.0050459000, 0.0050782000, 0.0051526000, 0.0053243000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0065908000, 0.0065005000, 0.0062924000, 0.0062799000, 0.0062513000, 0.0061854000, 0.0060335000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035270000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.039503900, 0.0758444000, 0.2422669000", \ - "-0.191473300, -0.073683600, 0.0732077000", \ - "-0.309067700, -0.192498700, -0.054152300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1167461000, 0.0331361000, 0.0022116000", \ - "0.2504049000, 0.1655742000, 0.1358704000", \ - "0.3557923000, 0.2697409000, 0.2388164000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.2687155000, 0.3985169000", \ - "0.1039368000, 0.2144023000, 0.3246725000", \ - "0.1865378000, 0.2481751000, 0.3267070000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2521729000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.226873700, -0.331040400", \ - "-0.060874400, -0.167677700, -0.253533800", \ - "-0.075115900, -0.175815800, -0.248244100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrbp_1") { - leakage_power () { - value : 0.0111839000; - when : "RESET_B&CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0124264000; - when : "RESET_B&!CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0125420000; - when : "!RESET_B&!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0139328000; - when : "RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0125817000; - when : "RESET_B&!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0120825000; - when : "!RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0117324000; - when : "RESET_B&CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0109345000; - when : "RESET_B&!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0131347000; - when : "!RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0127085000; - when : "RESET_B&!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0128806000; - when : "RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0122071000; - when : "!RESET_B&!CLK&!D&!Q&Q_N"; - } - area : 28.777600000; - cell_footprint : "sky130_fd_sc_hd__dfrbp"; - cell_leakage_power : 0.0123622800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017940000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0248024000, 0.0246802000, 0.0243985000, 0.0244781000, 0.0246614000, 0.0250842000, 0.0260588000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162697000, 0.0161893000, 0.0160041000, 0.0160188000, 0.0160527000, 0.0161308000, 0.0163109000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018740000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2093310000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1653906000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061313000, 0.0060924000, 0.0060027000, 0.0060656000, 0.0062104000, 0.0065444000, 0.0073142000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000822400, -0.000892900, -0.001055300, -0.001005200, -0.000889700, -0.000623100, -8.8221101e-06"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020050000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1057598000, 0.3199850000, 0.6255677000", \ - "-0.005926400, 0.2021953000, 0.5016745000", \ - "-0.091782600, 0.1126771000, 0.4072734000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0581523000, 0.1735006000, 0.2495911000", \ - "-0.014471400, 0.0874492000, 0.1501120000", \ - "-0.047837200, 0.0492005000, 0.1057598000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.038283200, -0.237860000, -0.490952500", \ - "0.0734030000, -0.124953100, -0.387811200", \ - "0.1519349000, -0.041538400, -0.305617200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.033400400, -0.135321000, -0.188218100", \ - "0.0343405000, -0.062697300, -0.113153000", \ - "0.0603822000, -0.032993500, -0.084669900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("-0.004905900, -0.000471000, 0.0076381000, 0.0159960000, 0.0094758000, -0.041957500, -0.202547100", \ - "-0.004870000, -0.000439600, 0.0076443000, 0.0159610000, 0.0094273000, -0.042060600, -0.202673200", \ - "-0.004788700, -0.000377500, 0.0076982000, 0.0160021000, 0.0093689000, -0.042149400, -0.202772000", \ - "-0.004819400, -0.000436900, 0.0075520000, 0.0157474000, 0.0090744000, -0.042524400, -0.203174400", \ - "-0.004841100, -0.000475700, 0.0074988000, 0.0156357000, 0.0089598000, -0.042633500, -0.203292200", \ - "-0.004879800, -0.000509500, 0.0074851000, 0.0156388000, 0.0089527000, -0.042645700, -0.203304700", \ - "-0.004903000, -0.000436000, 0.0077332000, 0.0161881000, 0.0097322000, -0.041906600, -0.202499800"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("-0.006478800, -0.003950000, 0.0019636000, 0.0148746000, 0.0424996000, 0.1083191000, 0.2751654000", \ - "-0.006446500, -0.003928200, 0.0019629000, 0.0148445000, 0.0424725000, 0.1082630000, 0.2731554000", \ - "-0.006361600, -0.003855700, 0.0020120000, 0.0148683000, 0.0424410000, 0.1080511000, 0.2726225000", \ - "-0.006390300, -0.003913900, 0.0018880000, 0.0146443000, 0.0421464000, 0.1076327000, 0.2742219000", \ - "-0.006424700, -0.003974200, 0.0017845000, 0.0144721000, 0.0419050000, 0.1069689000, 0.2741783000", \ - "-0.006466200, -0.004017400, 0.0017337000, 0.0144044000, 0.0417886000, 0.1068688000, 0.2741551000", \ - "-0.006493100, -0.003953300, 0.0019869000, 0.0149066000, 0.0423707000, 0.1076247000, 0.2741253000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013153390, 0.0034602330, 0.0091027580, 0.0239464200, 0.0629953200, 0.1657204000"); - values("0.0003771000, 0.0041353000, 0.0109073000, 0.0172830000, 0.0089144000, -0.043831600, -0.204908000", \ - "0.0003609000, 0.0041098000, 0.0108562000, 0.0171889000, 0.0087606000, -0.043973200, -0.205138600", \ - "0.0003337000, 0.0040694000, 0.0107858000, 0.0170864000, 0.0086568000, -0.044123500, -0.205275000", \ - "0.0003259000, 0.0040621000, 0.0107718000, 0.0170532000, 0.0085817000, -0.044179500, -0.205368300", \ - "0.0003042000, 0.0040252000, 0.0106972000, 0.0169029000, 0.0083902000, -0.044400900, -0.205589900", \ - "0.0002742000, 0.0039783000, 0.0106184000, 0.0167558000, 0.0081285000, -0.044653400, -0.205820400", \ - "0.0002400000, 0.0039731000, 0.0105961000, 0.0166813000, 0.0080836000, -0.044598100, -0.205659800"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1657200000; - max_transition : 1.5057720000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.3644992000, 0.3739564000, 0.3932935000, 0.4304887000, 0.5015714000, 0.6499142000, 1.0182091000", \ - "0.3691780000, 0.3786388000, 0.3980105000, 0.4351888000, 0.5062704000, 0.6545862000, 1.0240584000", \ - "0.3803041000, 0.3897211000, 0.4091110000, 0.4462366000, 0.5173166000, 0.6657023000, 1.0341915000", \ - "0.4058747000, 0.4152776000, 0.4347148000, 0.4719041000, 0.5429658000, 0.6912781000, 1.0597900000", \ - "0.4540370000, 0.4634334000, 0.4828878000, 0.5199925000, 0.5910972000, 0.7394333000, 1.1076551000", \ - "0.5214895000, 0.5308934000, 0.5502835000, 0.5874721000, 0.6585765000, 0.8069002000, 1.1750444000", \ - "0.6048132000, 0.6142002000, 0.6336306000, 0.6707999000, 0.7419089000, 0.8902175000, 1.2583128000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.3076994000, 0.3169023000, 0.3367975000, 0.3794658000, 0.4783668000, 0.7249946000, 1.3754472000", \ - "0.3121820000, 0.3213808000, 0.3413150000, 0.3839798000, 0.4828852000, 0.7292094000, 1.3746825000", \ - "0.3234654000, 0.3326525000, 0.3525921000, 0.3952810000, 0.4941809000, 0.7411278000, 1.3871985000", \ - "0.3492452000, 0.3584748000, 0.3784210000, 0.4210580000, 0.5199696000, 0.7667539000, 1.4143710000", \ - "0.3986236000, 0.4078457000, 0.4277842000, 0.4704468000, 0.5693585000, 0.8157889000, 1.4632278000", \ - "0.4698812000, 0.4790757000, 0.4989848000, 0.5416499000, 0.6405836000, 0.8868521000, 1.5345402000", \ - "0.5617770000, 0.5710096000, 0.5909608000, 0.6336449000, 0.7325568000, 0.9795232000, 1.6240075000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0372427000, 0.0432042000, 0.0567442000, 0.0861443000, 0.1508642000, 0.3202688000, 0.8014491000", \ - "0.0374464000, 0.0435556000, 0.0570285000, 0.0860099000, 0.1508941000, 0.3210253000, 0.8077980000", \ - "0.0370930000, 0.0434071000, 0.0564778000, 0.0860305000, 0.1512306000, 0.3206351000, 0.8026236000", \ - "0.0370856000, 0.0437012000, 0.0570072000, 0.0859474000, 0.1508491000, 0.3206838000, 0.8032969000", \ - "0.0373343000, 0.0432163000, 0.0565683000, 0.0859655000, 0.1510422000, 0.3202035000, 0.8024821000", \ - "0.0374710000, 0.0432360000, 0.0564288000, 0.0858732000, 0.1509636000, 0.3200237000, 0.8002932000", \ - "0.0373079000, 0.0432774000, 0.0566546000, 0.0862285000, 0.1509445000, 0.3199671000, 0.8025716000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0340767000, 0.0415566000, 0.0599241000, 0.1078784000, 0.2348914000, 0.5811386000, 1.5054573000", \ - "0.0340202000, 0.0415521000, 0.0597920000, 0.1078934000, 0.2350171000, 0.5804311000, 1.4999703000", \ - "0.0339730000, 0.0415079000, 0.0598607000, 0.1078938000, 0.2350465000, 0.5814695000, 1.4972560000", \ - "0.0339991000, 0.0415096000, 0.0598878000, 0.1079358000, 0.2346659000, 0.5807842000, 1.5010471000", \ - "0.0339027000, 0.0415689000, 0.0598032000, 0.1079374000, 0.2349141000, 0.5797299000, 1.5050430000", \ - "0.0341197000, 0.0416288000, 0.0598448000, 0.1078997000, 0.2351976000, 0.5802080000, 1.5057720000", \ - "0.0340173000, 0.0416575000, 0.0599646000, 0.1079745000, 0.2350508000, 0.5788147000, 1.5049852000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.2012696000, 0.2114335000, 0.2325252000, 0.2742530000, 0.3456171000, 0.4888243000, 0.8564897000", \ - "0.2062230000, 0.2163612000, 0.2374682000, 0.2792503000, 0.3506315000, 0.4938361000, 0.8617051000", \ - "0.2187812000, 0.2289187000, 0.2500342000, 0.2917798000, 0.3632136000, 0.5063638000, 0.8743279000", \ - "0.2504467000, 0.2606125000, 0.2817211000, 0.3234371000, 0.3949051000, 0.5381117000, 0.9054082000", \ - "0.3266864000, 0.3368322000, 0.3578830000, 0.3994489000, 0.4708453000, 0.6141219000, 0.9815154000", \ - "0.4971302000, 0.5081946000, 0.5309034000, 0.5739000000, 0.6453446000, 0.7886358000, 1.1561926000", \ - "0.7885678000, 0.8033285000, 0.8337165000, 0.8897974000, 0.9670176000, 1.1109482000, 1.4785917000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013153400, 0.0034602300, 0.0091027600, 0.0239464000, 0.0629953000, 0.1657200000"); - values("0.0402155000, 0.0472826000, 0.0623455000, 0.0927738000, 0.1478021000, 0.3131600000, 0.8009649000", \ - "0.0397163000, 0.0472815000, 0.0622886000, 0.0928716000, 0.1478166000, 0.3129727000, 0.7999089000", \ - "0.0397647000, 0.0467474000, 0.0623804000, 0.0927923000, 0.1475186000, 0.3126843000, 0.8038123000", \ - "0.0398204000, 0.0467278000, 0.0621278000, 0.0929700000, 0.1478920000, 0.3124892000, 0.7973354000", \ - "0.0397264000, 0.0467678000, 0.0622527000, 0.0929812000, 0.1479218000, 0.3130399000, 0.8000611000", \ - "0.0469282000, 0.0539084000, 0.0680645000, 0.0961712000, 0.1485390000, 0.3131105000, 0.7997724000", \ - "0.0694778000, 0.0774987000, 0.0968522000, 0.1222284000, 0.1601867000, 0.3145033000, 0.8004665000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("-0.005075000, -0.000826600, 0.0069927000, 0.0148821000, 0.0075399000, -0.046206900, -0.212976500", \ - "-0.005039000, -0.000792600, 0.0069812000, 0.0148450000, 0.0074500000, -0.046282500, -0.213075300", \ - "-0.004953000, -0.000720900, 0.0070405000, 0.0148502000, 0.0074351000, -0.046330700, -0.213123900", \ - "-0.004981200, -0.000783100, 0.0069161000, 0.0146467000, 0.0071191000, -0.046707100, -0.213538800", \ - "-0.005019400, -0.000843200, 0.0068185000, 0.0144743000, 0.0068831000, -0.046990700, -0.213862200", \ - "-0.005061200, -0.000892700, 0.0067417000, 0.0143916000, 0.0067685000, -0.047113200, -0.213980500", \ - "-0.005088700, -0.000831300, 0.0069908000, 0.0149126000, 0.0074797000, -0.046420300, -0.213223900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("-0.006423800, -0.003789000, 0.0023751000, 0.0159577000, 0.0445583000, 0.1120499000, 0.2852239000", \ - "-0.006387600, -0.003760600, 0.0023905000, 0.0159912000, 0.0446059000, 0.1121952000, 0.2852108000", \ - "-0.006305000, -0.003694800, 0.0024195000, 0.0159408000, 0.0444447000, 0.1114836000, 0.2834499000", \ - "-0.006334400, -0.003752400, 0.0023043000, 0.0157530000, 0.0441636000, 0.1116548000, 0.2843777000", \ - "-0.006361600, -0.003796600, 0.0022165000, 0.0156398000, 0.0440866000, 0.1115039000, 0.2846144000", \ - "-0.006397000, -0.003823800, 0.0022096000, 0.0156382000, 0.0440979000, 0.1114491000, 0.2838508000", \ - "-0.006394900, -0.003690400, 0.0026326000, 0.0161722000, 0.0446208000, 0.1115816000, 0.2851936000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("-0.001111100, 0.0008869000, 0.0057484000, 0.0172774000, 0.0438723000, 0.1098192000, 0.2809835000", \ - "-0.001126000, 0.0008574000, 0.0056984000, 0.0171913000, 0.0437148000, 0.1101123000, 0.2812043000", \ - "-0.001153000, 0.0008182000, 0.0056331000, 0.0170871000, 0.0436958000, 0.1093941000, 0.2805623000", \ - "-0.001160200, 0.0008062000, 0.0056090000, 0.0170575000, 0.0435343000, 0.1098744000, 0.2819187000", \ - "-0.001183300, 0.0007627000, 0.0055264000, 0.0169106000, 0.0433440000, 0.1093847000, 0.2808309000", \ - "-0.001224900, 0.0007031000, 0.0054224000, 0.0167573000, 0.0430881000, 0.1090489000, 0.2812277000", \ - "-0.001259600, 0.0007034000, 0.0054868000, 0.0166975000, 0.0434389000, 0.1088933000, 0.2803935000"); - } - } - max_capacitance : 0.1712140000; - max_transition : 1.5003750000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.3663202000, 0.3717062000, 0.3830510000, 0.4066616000, 0.4600790000, 0.5969754000, 0.9584501000", \ - "0.3708275000, 0.3762103000, 0.3875568000, 0.4111690000, 0.4645830000, 0.6014240000, 0.9625800000", \ - "0.3820987000, 0.3874782000, 0.3988339000, 0.4223908000, 0.4759258000, 0.6127249000, 0.9748926000", \ - "0.4079562000, 0.4133047000, 0.4246174000, 0.4482403000, 0.5016533000, 0.6383832000, 1.0000997000", \ - "0.4573014000, 0.4626832000, 0.4740308000, 0.4976397000, 0.5510554000, 0.6878090000, 1.0494275000", \ - "0.5284008000, 0.5337587000, 0.5450933000, 0.5686618000, 0.6220559000, 0.7588223000, 1.1209679000", \ - "0.6204545000, 0.6258247000, 0.6372071000, 0.6607449000, 0.7142629000, 0.8508581000, 1.2121731000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.4313586000, 0.4379866000, 0.4528710000, 0.4884860000, 0.5802273000, 0.8231106000, 1.4644602000", \ - "0.4360210000, 0.4427506000, 0.4576879000, 0.4932447000, 0.5850987000, 0.8276391000, 1.4689537000", \ - "0.4471139000, 0.4537407000, 0.4686233000, 0.5040373000, 0.5960917000, 0.8385298000, 1.4806238000", \ - "0.4729201000, 0.4795055000, 0.4944439000, 0.5300096000, 0.6219379000, 0.8641288000, 1.5079271000", \ - "0.5206782000, 0.5272927000, 0.5421643000, 0.5777779000, 0.6699906000, 0.9125355000, 1.5534741000", \ - "0.5882202000, 0.5949245000, 0.6098504000, 0.6453735000, 0.7376213000, 0.9802865000, 1.6232470000", \ - "0.6716503000, 0.6782921000, 0.6932781000, 0.7287650000, 0.8210069000, 1.0638617000, 1.7052161000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0174935000, 0.0215958000, 0.0312893000, 0.0550348000, 0.1200968000, 0.3007294000, 0.7898132000", \ - "0.0174948000, 0.0216292000, 0.0313009000, 0.0550659000, 0.1202076000, 0.3009076000, 0.7850597000", \ - "0.0175689000, 0.0215493000, 0.0312750000, 0.0551559000, 0.1203194000, 0.3010606000, 0.7893424000", \ - "0.0176330000, 0.0216404000, 0.0311260000, 0.0551423000, 0.1203245000, 0.3004834000, 0.7897495000", \ - "0.0174928000, 0.0216492000, 0.0313154000, 0.0550540000, 0.1202049000, 0.3011151000, 0.7835412000", \ - "0.0175039000, 0.0214362000, 0.0311066000, 0.0551656000, 0.1205784000, 0.3009387000, 0.7843733000", \ - "0.0175946000, 0.0215479000, 0.0313113000, 0.0551268000, 0.1203188000, 0.3000745000, 0.7859650000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0227035000, 0.0287871000, 0.0454762000, 0.0930307000, 0.2236873000, 0.5713581000, 1.5001872000", \ - "0.0225518000, 0.0287533000, 0.0455465000, 0.0930548000, 0.2236641000, 0.5708087000, 1.5002055000", \ - "0.0227358000, 0.0287372000, 0.0455955000, 0.0930181000, 0.2234079000, 0.5708992000, 1.4973142000", \ - "0.0226855000, 0.0287315000, 0.0454943000, 0.0930459000, 0.2237346000, 0.5714285000, 1.4931839000", \ - "0.0227217000, 0.0287336000, 0.0455150000, 0.0930429000, 0.2236498000, 0.5704114000, 1.5003753000", \ - "0.0226694000, 0.0288094000, 0.0454872000, 0.0929839000, 0.2237264000, 0.5703656000, 1.4934539000", \ - "0.0228424000, 0.0288754000, 0.0455761000, 0.0931460000, 0.2234984000, 0.5712938000, 1.4981187000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.2715543000, 0.2784190000, 0.2936470000, 0.3295604000, 0.4215784000, 0.6644303000, 1.3063917000", \ - "0.2765144000, 0.2833103000, 0.2985739000, 0.3342821000, 0.4265008000, 0.6693498000, 1.3114810000", \ - "0.2890437000, 0.2959452000, 0.3111684000, 0.3470767000, 0.4390655000, 0.6815000000, 1.3237952000", \ - "0.3206193000, 0.3274825000, 0.3427701000, 0.3784929000, 0.4707111000, 0.7135981000, 1.3561193000", \ - "0.3968332000, 0.4036202000, 0.4188952000, 0.4546244000, 0.5468350000, 0.7898043000, 1.4330843000", \ - "0.5708568000, 0.5777896000, 0.5930990000, 0.6289603000, 0.7211607000, 0.9634055000, 1.6079815000", \ - "0.8803145000, 0.8885391000, 0.9047146000, 0.9411260000, 1.0332778000, 1.2755049000, 1.9180997000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0239380000, 0.0300070000, 0.0465832000, 0.0935510000, 0.2236627000, 0.5711094000, 1.4949375000", \ - "0.0239936000, 0.0301154000, 0.0465584000, 0.0935842000, 0.2236993000, 0.5709132000, 1.4927053000", \ - "0.0239190000, 0.0299695000, 0.0465881000, 0.0935493000, 0.2238278000, 0.5719343000, 1.4947965000", \ - "0.0241895000, 0.0300880000, 0.0465326000, 0.0935839000, 0.2237105000, 0.5714401000, 1.4954412000", \ - "0.0240842000, 0.0300946000, 0.0465213000, 0.0935198000, 0.2237657000, 0.5723291000, 1.4958559000", \ - "0.0246511000, 0.0305878000, 0.0468504000, 0.0935590000, 0.2238487000, 0.5711646000, 1.4915478000", \ - "0.0295886000, 0.0354363000, 0.0507161000, 0.0950934000, 0.2243978000, 0.5710017000, 1.4953232000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0035570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047575000, 0.0047731000, 0.0048092000, 0.0048187000, 0.0048408000, 0.0048917000, 0.0050092000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005543200, -0.005587100, -0.005688300, -0.005691400, -0.005698500, -0.005714700, -0.005752100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036190000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.225050800, -0.086509100, 0.2276185000", \ - "-0.374578800, -0.247023400, 0.0329245000", \ - "-0.500718100, -0.379266300, -0.123732400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4359681000, 0.7028952000", \ - "0.4359518000, 0.5684063000, 0.8292298000", \ - "0.5547669000, 0.6835593000, 0.9370586000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2323997000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrbp_2") { - leakage_power () { - value : 0.0109677000; - when : "RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0096383000; - when : "RESET_B&!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0091173000; - when : "!RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0103999000; - when : "RESET_B&CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0096019000; - when : "RESET_B&!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0101696000; - when : "!RESET_B&CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0097544000; - when : "RESET_B&!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0099155000; - when : "RESET_B&CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0092637000; - when : "!RESET_B&!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0098513000; - when : "RESET_B&CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0111421000; - when : "RESET_B&!CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0095879000; - when : "!RESET_B&!CLK&D&!Q&Q_N"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__dfrbp"; - cell_leakage_power : 0.0099507900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0018000000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0247885000, 0.0246654000, 0.0243817000, 0.0244533000, 0.0246183000, 0.0249988000, 0.0258759000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162728000, 0.0161928000, 0.0160083000, 0.0160284000, 0.0160747000, 0.0161816000, 0.0164281000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018740000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2104295000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1774742000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061315000, 0.0060925000, 0.0060028000, 0.0060651000, 0.0062085000, 0.0065393000, 0.0073019000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000823300, -0.000892800, -0.001052900, -0.001002500, -0.000886200, -0.000618000, 3.2670112e-07"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020060000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1069805000, 0.3212057000, 0.6280091000", \ - "-0.004705700, 0.2034160000, 0.5041159000", \ - "-0.090561800, 0.1138978000, 0.4097148000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0581523000, 0.1722799000, 0.2483705000", \ - "-0.014471400, 0.0862285000, 0.1488913000", \ - "-0.047837200, 0.0492005000, 0.1057598000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.038283200, -0.237860000, -0.492173200", \ - "0.0734030000, -0.124953100, -0.389031900", \ - "0.1519349000, -0.041538400, -0.305617200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.135321000, -0.188218100", \ - "0.0343405000, -0.061476600, -0.113153000", \ - "0.0603822000, -0.032993500, -0.083449200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("-0.004912400, 0.0001440000, 0.0102231000, 0.0210937000, 0.0107906000, -0.068122400, -0.326630000", \ - "-0.004874700, 0.0001710000, 0.0102666000, 0.0211051000, 0.0107580000, -0.068165000, -0.326719400", \ - "-0.004790100, 0.0002433000, 0.0102981000, 0.0211196000, 0.0106240000, -0.068316100, -0.326823900", \ - "-0.004819500, 0.0001947000, 0.0101782000, 0.0208654000, 0.0103752000, -0.068761000, -0.327318400", \ - "-0.004852100, 0.0001593000, 0.0100916000, 0.0207695000, 0.0101465000, -0.068911800, -0.327504600", \ - "-0.004900000, 0.0001127000, 0.0100754000, 0.0207763000, 0.0101425000, -0.068922700, -0.327413500", \ - "-0.004951500, 0.0001602000, 0.0103488000, 0.0214027000, 0.0112047000, -0.068214800, -0.326677100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("-0.006513000, -0.003726800, 0.0033187000, 0.0199595000, 0.0581184000, 0.1541227000, 0.4182336000", \ - "-0.006476500, -0.003698100, 0.0033259000, 0.0199514000, 0.0580520000, 0.1540508000, 0.4181601000", \ - "-0.006392000, -0.003623400, 0.0033860000, 0.0199742000, 0.0581636000, 0.1540056000, 0.4183692000", \ - "-0.006421100, -0.003685300, 0.0032588000, 0.0197410000, 0.0576814000, 0.1535272000, 0.4187129000", \ - "-0.006456600, -0.003733900, 0.0031611000, 0.0195473000, 0.0575311000, 0.1532510000, 0.4179635000", \ - "-0.006510900, -0.003793800, 0.0030828000, 0.0194766000, 0.0572673000, 0.1531942000, 0.4168823000", \ - "-0.006543600, -0.003678700, 0.0035008000, 0.0201231000, 0.0579020000, 0.1539889000, 0.4178439000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("0.0004682000, 0.0049110000, 0.0136244000, 0.0223287000, 0.0097856000, -0.070699700, -0.329807100", \ - "0.0004522000, 0.0048853000, 0.0135647000, 0.0222265000, 0.0097026000, -0.070855900, -0.330008100", \ - "0.0004269000, 0.0048461000, 0.0134969000, 0.0221358000, 0.0095944000, -0.070985600, -0.330150900", \ - "0.0004211000, 0.0048381000, 0.0134947000, 0.0221081000, 0.0095339000, -0.071010300, -0.330170100", \ - "0.0004020000, 0.0048039000, 0.0134352000, 0.0219894000, 0.0093041000, -0.071236800, -0.330402700", \ - "0.0003772000, 0.0047745000, 0.0133786000, 0.0218022000, 0.0089823000, -0.071629700, -0.330708000", \ - "0.0003637000, 0.0048237000, 0.0134849000, 0.0218965000, 0.0090074000, -0.071622400, -0.330682900"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.2536110000; - max_transition : 1.5036290000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.3750218000, 0.3827018000, 0.3993438000, 0.4316703000, 0.4920138000, 0.6119065000, 0.8916552000", \ - "0.3797575000, 0.3874059000, 0.4041366000, 0.4364091000, 0.4967755000, 0.6166837000, 0.8963069000", \ - "0.3908320000, 0.3984300000, 0.4151392000, 0.4474233000, 0.5077836000, 0.6276644000, 0.9075385000", \ - "0.4165462000, 0.4241646000, 0.4408818000, 0.4731570000, 0.5335239000, 0.6534142000, 0.9332538000", \ - "0.4643122000, 0.4719879000, 0.4886934000, 0.5209966000, 0.5813354000, 0.7012169000, 0.9808055000", \ - "0.5319638000, 0.5396055000, 0.5562855000, 0.5885686000, 0.6489364000, 0.7687978000, 1.0485707000", \ - "0.6153743000, 0.6230517000, 0.6396912000, 0.6719856000, 0.7324141000, 0.8522693000, 1.1318625000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.3287315000, 0.3371092000, 0.3560996000, 0.3968400000, 0.4913176000, 0.7308129000, 1.3944776000", \ - "0.3332426000, 0.3415758000, 0.3605100000, 0.4013722000, 0.4957664000, 0.7351584000, 1.3940117000", \ - "0.3444811000, 0.3528801000, 0.3717980000, 0.4126517000, 0.5070220000, 0.7464020000, 1.4055788000", \ - "0.3702577000, 0.3786589000, 0.3975984000, 0.4384692000, 0.5328541000, 0.7722568000, 1.4332089000", \ - "0.4195694000, 0.4280006000, 0.4469650000, 0.4877060000, 0.5821690000, 0.8215027000, 1.4826185000", \ - "0.4908987000, 0.4993095000, 0.5182434000, 0.5589220000, 0.6534511000, 0.8928175000, 1.5523803000", \ - "0.5827753000, 0.5911211000, 0.6100752000, 0.6509521000, 0.7452993000, 0.9847912000, 1.6419607000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0349067000, 0.0396163000, 0.0498968000, 0.0717465000, 0.1209608000, 0.2389145000, 0.5878253000", \ - "0.0348774000, 0.0395309000, 0.0498955000, 0.0724141000, 0.1208292000, 0.2387473000, 0.5876803000", \ - "0.0348814000, 0.0396452000, 0.0501158000, 0.0717535000, 0.1204692000, 0.2383791000, 0.5877521000", \ - "0.0347745000, 0.0395305000, 0.0503982000, 0.0715852000, 0.1209752000, 0.2382899000, 0.5874061000", \ - "0.0349255000, 0.0397046000, 0.0500908000, 0.0717554000, 0.1205795000, 0.2383644000, 0.5872517000", \ - "0.0347657000, 0.0395644000, 0.0500745000, 0.0716968000, 0.1208852000, 0.2383286000, 0.5875072000", \ - "0.0349168000, 0.0396863000, 0.0499002000, 0.0719512000, 0.1208132000, 0.2390555000, 0.5845296000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0336280000, 0.0402270000, 0.0565966000, 0.0989872000, 0.2163850000, 0.5448580000, 1.4996966000", \ - "0.0336512000, 0.0402007000, 0.0565606000, 0.0989392000, 0.2163598000, 0.5471942000, 1.5006069000", \ - "0.0335591000, 0.0401426000, 0.0565528000, 0.0989504000, 0.2163704000, 0.5447219000, 1.5029711000", \ - "0.0336409000, 0.0402629000, 0.0566089000, 0.0989416000, 0.2163857000, 0.5458125000, 1.5012891000", \ - "0.0337031000, 0.0403272000, 0.0567000000, 0.0989678000, 0.2163700000, 0.5466726000, 1.5036286000", \ - "0.0336093000, 0.0402292000, 0.0565156000, 0.0988475000, 0.2163701000, 0.5471031000, 1.5010717000", \ - "0.0337356000, 0.0402818000, 0.0566719000, 0.0989935000, 0.2164457000, 0.5446222000, 1.4978706000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.2151135000, 0.2232139000, 0.2411547000, 0.2761873000, 0.3412790000, 0.4541424000, 0.7282459000", \ - "0.2201978000, 0.2283082000, 0.2462495000, 0.2813103000, 0.3464035000, 0.4592895000, 0.7333479000", \ - "0.2329246000, 0.2410103000, 0.2590009000, 0.2940912000, 0.3591503000, 0.4720448000, 0.7462038000", \ - "0.2644511000, 0.2725311000, 0.2904945000, 0.3255510000, 0.3906705000, 0.5035496000, 0.7776840000", \ - "0.3398284000, 0.3479166000, 0.3658502000, 0.4007461000, 0.4658238000, 0.5787353000, 0.8529041000", \ - "0.5123360000, 0.5209939000, 0.5396999000, 0.5753176000, 0.6408609000, 0.7537808000, 1.0278233000", \ - "0.8115572000, 0.8229812000, 0.8479382000, 0.8953939000, 0.9757523000, 1.0920397000, 1.3662377000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0377890000, 0.0429614000, 0.0550681000, 0.0788634000, 0.1236998000, 0.2272537000, 0.5787851000", \ - "0.0378412000, 0.0429827000, 0.0551929000, 0.0789968000, 0.1236318000, 0.2269841000, 0.5800272000", \ - "0.0381257000, 0.0430006000, 0.0545491000, 0.0792846000, 0.1238377000, 0.2269082000, 0.5794498000", \ - "0.0380877000, 0.0430498000, 0.0544541000, 0.0791572000, 0.1239754000, 0.2271450000, 0.5778361000", \ - "0.0377795000, 0.0429557000, 0.0550662000, 0.0789376000, 0.1235909000, 0.2275439000, 0.5797030000", \ - "0.0427478000, 0.0478576000, 0.0586850000, 0.0819653000, 0.1249775000, 0.2276119000, 0.5798194000", \ - "0.0650289000, 0.0715783000, 0.0854173000, 0.1133138000, 0.1482841000, 0.2336720000, 0.5810534000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.005152800, -0.000290700, 0.0095772000, 0.0199881000, 0.0067346000, -0.084139200, -0.381886600", \ - "-0.005118200, -0.000265400, 0.0095889000, 0.0199834000, 0.0066582000, -0.084256000, -0.382003200", \ - "-0.005032400, -0.000186400, 0.0096475000, 0.0200075000, 0.0066549000, -0.084293500, -0.382039200", \ - "-0.005059100, -0.000244100, 0.0095163000, 0.0197743000, 0.0063068000, -0.084692200, -0.382387900", \ - "-0.005094100, -0.000302800, 0.0094096000, 0.0195768000, 0.0060840000, -0.084919100, -0.382730800", \ - "-0.005149600, -0.000363300, 0.0093391000, 0.0194731000, 0.0059543000, -0.085077800, -0.382884100", \ - "-0.005214600, -0.000325400, 0.0096054000, 0.0201568000, 0.0068664000, -0.084399000, -0.382109000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.006596300, -0.003825300, 0.0034699000, 0.0211197000, 0.0622547000, 0.1695894000, 0.4705227000", \ - "-0.006558400, -0.003785700, 0.0035057000, 0.0211409000, 0.0622927000, 0.1689042000, 0.4709691000", \ - "-0.006474400, -0.003719500, 0.0035517000, 0.0211406000, 0.0622241000, 0.1687196000, 0.4732607000", \ - "-0.006502200, -0.003777600, 0.0034253000, 0.0208766000, 0.0618394000, 0.1691694000, 0.4722253000", \ - "-0.006533100, -0.003825300, 0.0033568000, 0.0207864000, 0.0617034000, 0.1688639000, 0.4726649000", \ - "-0.006581200, -0.003860600, 0.0033297000, 0.0207907000, 0.0617426000, 0.1690692000, 0.4694948000", \ - "-0.006586700, -0.003685200, 0.0037887000, 0.0214200000, 0.0622710000, 0.1685795000, 0.4731011000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.001183600, 0.0010088000, 0.0069931000, 0.0223172000, 0.0611865000, 0.1664123000, 0.4677455000", \ - "-0.001199500, 0.0009796000, 0.0069506000, 0.0222403000, 0.0609714000, 0.1662322000, 0.4695551000", \ - "-0.001222300, 0.0009447000, 0.0068906000, 0.0221413000, 0.0608202000, 0.1662221000, 0.4669570000", \ - "-0.001229800, 0.0009421000, 0.0068795000, 0.0221204000, 0.0607473000, 0.1659663000, 0.4669906000", \ - "-0.001250200, 0.0009015000, 0.0067963000, 0.0219779000, 0.0605564000, 0.1659139000, 0.4690256000", \ - "-0.001289100, 0.0008409000, 0.0066898000, 0.0217922000, 0.0602952000, 0.1662621000, 0.4670330000", \ - "-0.001311700, 0.0008586000, 0.0066696000, 0.0219068000, 0.0606736000, 0.1659398000, 0.4690497000"); - } - } - max_capacitance : 0.2874860000; - max_transition : 1.4978490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.4444617000, 0.4495632000, 0.4608365000, 0.4833460000, 0.5292952000, 0.6377331000, 0.9376793000", \ - "0.4488485000, 0.4539771000, 0.4651830000, 0.4878793000, 0.5338599000, 0.6422071000, 0.9417331000", \ - "0.4601230000, 0.4652232000, 0.4764465000, 0.4991223000, 0.5451271000, 0.6534892000, 0.9528112000", \ - "0.4859582000, 0.4910385000, 0.5022719000, 0.5249329000, 0.5709566000, 0.6793287000, 0.9784070000", \ - "0.5352741000, 0.5403815000, 0.5516985000, 0.5742239000, 0.6201437000, 0.7285808000, 1.0285528000", \ - "0.6064396000, 0.6115426000, 0.6228331000, 0.6454580000, 0.6913936000, 0.7998152000, 1.0997454000", \ - "0.6984217000, 0.7034331000, 0.7147363000, 0.7373466000, 0.7832981000, 0.8917804000, 1.1909173000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.5091128000, 0.5150327000, 0.5290557000, 0.5608269000, 0.6431697000, 0.8766453000, 1.5522718000", \ - "0.5139127000, 0.5200007000, 0.5338728000, 0.5657935000, 0.6480682000, 0.8816763000, 1.5558392000", \ - "0.5248753000, 0.5309547000, 0.5450994000, 0.5769181000, 0.6591900000, 0.8932169000, 1.5676589000", \ - "0.5505368000, 0.5566826000, 0.5707882000, 0.6025039000, 0.6847399000, 0.9181192000, 1.5938323000", \ - "0.5984396000, 0.6045294000, 0.6186711000, 0.6504708000, 0.7327161000, 0.9665221000, 1.6406222000", \ - "0.6660443000, 0.6722374000, 0.6862178000, 0.7181171000, 0.8004733000, 1.0338498000, 1.7086877000", \ - "0.7494573000, 0.7556372000, 0.7695858000, 0.8013248000, 0.8834701000, 1.1173266000, 1.7924551000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0238601000, 0.0270532000, 0.0343562000, 0.0520093000, 0.0957604000, 0.2253816000, 0.6233958000", \ - "0.0238018000, 0.0275474000, 0.0346027000, 0.0518428000, 0.0957069000, 0.2256872000, 0.6194541000", \ - "0.0238221000, 0.0275916000, 0.0345926000, 0.0518765000, 0.0957375000, 0.2256754000, 0.6197134000", \ - "0.0238267000, 0.0276128000, 0.0345822000, 0.0518848000, 0.0957654000, 0.2255237000, 0.6225588000", \ - "0.0238146000, 0.0269382000, 0.0342992000, 0.0518862000, 0.0959524000, 0.2261832000, 0.6248491000", \ - "0.0239054000, 0.0270759000, 0.0343446000, 0.0517673000, 0.0957054000, 0.2256249000, 0.6251185000", \ - "0.0238029000, 0.0269242000, 0.0342466000, 0.0520645000, 0.0958811000, 0.2257965000, 0.6185886000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0265913000, 0.0315751000, 0.0434840000, 0.0793870000, 0.1921284000, 0.5250628000, 1.4920953000", \ - "0.0267268000, 0.0310952000, 0.0433873000, 0.0793394000, 0.1923410000, 0.5242928000, 1.4932569000", \ - "0.0266143000, 0.0310800000, 0.0434692000, 0.0794102000, 0.1918319000, 0.5254466000, 1.4978487000", \ - "0.0267036000, 0.0312000000, 0.0434627000, 0.0795286000, 0.1917921000, 0.5253613000, 1.4940023000", \ - "0.0266177000, 0.0311351000, 0.0434178000, 0.0793558000, 0.1921098000, 0.5251247000, 1.4974310000", \ - "0.0266827000, 0.0310882000, 0.0432751000, 0.0792681000, 0.1919655000, 0.5252783000, 1.4863309000", \ - "0.0266717000, 0.0314192000, 0.0434597000, 0.0794617000, 0.1920046000, 0.5245480000, 1.4976218000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.3591467000, 0.3653671000, 0.3793474000, 0.4111615000, 0.4932298000, 0.7263921000, 1.4025161000", \ - "0.3641279000, 0.3703992000, 0.3844144000, 0.4160639000, 0.4981908000, 0.7316658000, 1.4095377000", \ - "0.3769269000, 0.3832428000, 0.3972297000, 0.4288333000, 0.5107956000, 0.7448138000, 1.4188557000", \ - "0.4083950000, 0.4147346000, 0.4286925000, 0.4603372000, 0.5423095000, 0.7760879000, 1.4510124000", \ - "0.4836705000, 0.4898944000, 0.5038788000, 0.5356986000, 0.6177703000, 0.8511475000, 1.5289715000", \ - "0.6590759000, 0.6652836000, 0.6792784000, 0.7110895000, 0.7932759000, 1.0270262000, 1.7038765000", \ - "0.9979385000, 1.0045696000, 1.0191461000, 1.0512449000, 1.1336030000, 1.3667927000, 2.0443258000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0272248000, 0.0318839000, 0.0435165000, 0.0793941000, 0.1915594000, 0.5247791000, 1.4946353000", \ - "0.0273734000, 0.0316127000, 0.0435538000, 0.0793460000, 0.1915622000, 0.5241099000, 1.4945482000", \ - "0.0272340000, 0.0315257000, 0.0436186000, 0.0793063000, 0.1917807000, 0.5243422000, 1.4886162000", \ - "0.0273313000, 0.0318344000, 0.0435523000, 0.0793500000, 0.1916519000, 0.5243906000, 1.4908457000", \ - "0.0272493000, 0.0319063000, 0.0435329000, 0.0794082000, 0.1915806000, 0.5255293000, 1.4930526000", \ - "0.0273581000, 0.0319904000, 0.0435985000, 0.0794389000, 0.1915477000, 0.5254915000, 1.4956003000", \ - "0.0303613000, 0.0341291000, 0.0455938000, 0.0803116000, 0.1919709000, 0.5246381000, 1.4951477000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0035500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047550000, 0.0047710000, 0.0048079000, 0.0048177000, 0.0048403000, 0.0048926000, 0.0050132000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005487700, -0.005474000, -0.005442300, -0.005456800, -0.005490200, -0.005567400, -0.005745200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036090000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.225050800, -0.080405600, 0.2752259000", \ - "-0.374578800, -0.239699200, 0.0829733000", \ - "-0.500718100, -0.371942000, -0.076125000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4359681000, 0.7028952000", \ - "0.4359518000, 0.5684063000, 0.8292298000", \ - "0.5547669000, 0.6835593000, 0.9370586000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2697491000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrtn_1") { - leakage_power () { - value : 0.0154627000; - when : "RESET_B&!CLK_N&D&!Q"; - } - leakage_power () { - value : 0.0141340000; - when : "RESET_B&CLK_N&!D&!Q"; - } - leakage_power () { - value : 0.0136124000; - when : "!RESET_B&!CLK_N&!D&!Q"; - } - leakage_power () { - value : 0.0065133000; - when : "RESET_B&!CLK_N&!D&Q"; - } - leakage_power () { - value : 0.0057154000; - when : "RESET_B&CLK_N&D&Q"; - } - leakage_power () { - value : 0.0146646000; - when : "!RESET_B&!CLK_N&D&!Q"; - } - leakage_power () { - value : 0.0059648000; - when : "RESET_B&!CLK_N&D&Q"; - } - leakage_power () { - value : 0.0072568000; - when : "RESET_B&CLK_N&!D&Q"; - } - leakage_power () { - value : 0.0142499000; - when : "RESET_B&CLK_N&D&!Q"; - } - leakage_power () { - value : 0.0144105000; - when : "RESET_B&!CLK_N&!D&!Q"; - } - leakage_power () { - value : 0.0137594000; - when : "!RESET_B&CLK_N&!D&!Q"; - } - leakage_power () { - value : 0.0140834000; - when : "!RESET_B&CLK_N&D&!Q"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__dfrtn"; - cell_leakage_power : 0.0116522800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "!CLK_N"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0017890000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0225281000, 0.0224120000, 0.0221443000, 0.0221748000, 0.0222450000, 0.0224070000, 0.0227804000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0187193000, 0.0186475000, 0.0184820000, 0.0184990000, 0.0185380000, 0.0186282000, 0.0188361000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018800000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1840653000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2071340000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0057573000, 0.0057020000, 0.0055745000, 0.0056373000, 0.0057820000, 0.0061159000, 0.0068853000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000427600, -0.000502000, -0.000673300, -0.000620900, -0.000500300, -0.000221900, 0.0004199000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0021120000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1460430000, 0.3614889000, 0.6585267000", \ - "0.0099427000, 0.2205059000, 0.5065573000", \ - "-0.151597000, 0.0601868000, 0.3413555000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, 0.0880514000, 0.1787904000", \ - "-0.231756500, -0.117628900, -0.031772800", \ - "-0.459214200, -0.357293600, -0.283644500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.073683600, -0.275701800, -0.527573600", \ - "0.0831686000, -0.122511700, -0.371942000", \ - "0.2386048000, 0.0317038000, -0.218947300"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0752422000, -0.015692100, -0.053940800", \ - "0.2687155000, 0.1777813000, 0.1358704000", \ - "0.4961732000, 0.4076804000, 0.3645488000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0154319000, 0.0144481000, 0.0118110000, 0.0034904000, -0.020953700, -0.087253000, -0.263723900", \ - "0.0153978000, 0.0143919000, 0.0117462000, 0.0034347000, -0.021006200, -0.087302300, -0.263779900", \ - "0.0154516000, 0.0144620000, 0.0118304000, 0.0034990000, -0.020933900, -0.087231700, -0.263718200", \ - "0.0152727000, 0.0142643000, 0.0116231000, 0.0033110000, -0.021128900, -0.087425200, -0.263907000", \ - "0.0148865000, 0.0138977000, 0.0112706000, 0.0029441000, -0.021489400, -0.087783000, -0.264280000", \ - "0.0145613000, 0.0135716000, 0.0110095000, 0.0027191000, -0.021698800, -0.087980800, -0.264459300", \ - "0.0173960000, 0.0161152000, 0.0127156000, 0.0035516000, -0.021269000, -0.087316500, -0.263781000"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0227051000, 0.0242595000, 0.0281913000, 0.0379395000, 0.0629158000, 0.1294958000, 0.3048992000", \ - "0.0226619000, 0.0242164000, 0.0281508000, 0.0378961000, 0.0628671000, 0.1294105000, 0.3053559000", \ - "0.0226923000, 0.0242460000, 0.0281909000, 0.0379419000, 0.0629413000, 0.1286969000, 0.3048337000", \ - "0.0225378000, 0.0240819000, 0.0280392000, 0.0377786000, 0.0627525000, 0.1292518000, 0.3031904000", \ - "0.0224570000, 0.0239906000, 0.0279398000, 0.0376871000, 0.0627533000, 0.1290815000, 0.3037245000", \ - "0.0230322000, 0.0245820000, 0.0285377000, 0.0382902000, 0.0633577000, 0.1296623000, 0.3043299000", \ - "0.0250618000, 0.0264380000, 0.0300899000, 0.0396815000, 0.0649239000, 0.1302148000, 0.3051568000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0158038000, 0.0161602000, 0.0152226000, 0.0074828000, -0.017062500, -0.083323800, -0.259916400", \ - "0.0156083000, 0.0159689000, 0.0150574000, 0.0073162000, -0.017235500, -0.083545100, -0.260017000", \ - "0.0153826000, 0.0157049000, 0.0148149000, 0.0070899000, -0.017448500, -0.083756600, -0.260232800", \ - "0.0153497000, 0.0156042000, 0.0147656000, 0.0070348000, -0.017511400, -0.083804300, -0.260262600", \ - "0.0151749000, 0.0155229000, 0.0145456000, 0.0067324000, -0.017822500, -0.084080700, -0.260505200", \ - "0.0177043000, 0.0166353000, 0.0143462000, 0.0063824000, -0.018197600, -0.084414500, -0.260799700", \ - "0.0211602000, 0.0196974000, 0.0160281000, 0.0065085000, -0.018436300, -0.084340100, -0.260669000"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1748760000; - max_transition : 1.5006590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.2885729000, 0.2965947000, 0.3130828000, 0.3445776000, 0.4072565000, 0.5514649000, 0.9264135000", \ - "0.2934764000, 0.3015031000, 0.3179348000, 0.3495277000, 0.4121355000, 0.5563783000, 0.9313100000", \ - "0.3062396000, 0.3142722000, 0.3307674000, 0.3622962000, 0.4249279000, 0.5691521000, 0.9440638000", \ - "0.3372338000, 0.3452668000, 0.3616891000, 0.3932894000, 0.4558938000, 0.6001361000, 0.9750705000", \ - "0.4078952000, 0.4159277000, 0.4324154000, 0.4639620000, 0.5265973000, 0.6707553000, 1.0444862000", \ - "0.5327440000, 0.5408137000, 0.5571368000, 0.5886922000, 0.6514392000, 0.7956216000, 1.1699663000", \ - "0.7235008000, 0.7315450000, 0.7479805000, 0.7794685000, 0.8422915000, 0.9865009000, 1.3600018000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.3460874000, 0.3544971000, 0.3727258000, 0.4120474000, 0.5057078000, 0.7494156000, 1.3964826000", \ - "0.3510378000, 0.3594461000, 0.3776766000, 0.4169754000, 0.5107535000, 0.7545490000, 1.3989819000", \ - "0.3632527000, 0.3716680000, 0.3899051000, 0.4292718000, 0.5228645000, 0.7665408000, 1.4133008000", \ - "0.3945113000, 0.4029400000, 0.4211727000, 0.4605004000, 0.5542551000, 0.7980857000, 1.4422686000", \ - "0.4654884000, 0.4739222000, 0.4921477000, 0.5314938000, 0.6253408000, 0.8691770000, 1.5137300000", \ - "0.5956380000, 0.6040610000, 0.6222979000, 0.6616637000, 0.7555288000, 0.9993665000, 1.6443277000", \ - "0.7972025000, 0.8056067000, 0.8238200000, 0.8631903000, 0.9568557000, 1.2007597000, 1.8478353000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0277025000, 0.0328228000, 0.0443850000, 0.0703359000, 0.1349290000, 0.3145553000, 0.8120971000", \ - "0.0277114000, 0.0328637000, 0.0442322000, 0.0706595000, 0.1347078000, 0.3142801000, 0.8061568000", \ - "0.0276585000, 0.0328511000, 0.0444198000, 0.0706072000, 0.1349290000, 0.3145128000, 0.8065462000", \ - "0.0277089000, 0.0328626000, 0.0442324000, 0.0706559000, 0.1347307000, 0.3143278000, 0.8127568000", \ - "0.0277013000, 0.0328604000, 0.0444594000, 0.0706296000, 0.1348518000, 0.3145599000, 0.8105924000", \ - "0.0276924000, 0.0331307000, 0.0445407000, 0.0707077000, 0.1347761000, 0.3146001000, 0.8094894000", \ - "0.0278130000, 0.0329780000, 0.0443714000, 0.0708307000, 0.1348300000, 0.3150613000, 0.8086927000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0281388000, 0.0351500000, 0.0525769000, 0.0980472000, 0.2249386000, 0.5706225000, 1.4988450000", \ - "0.0281382000, 0.0351512000, 0.0526164000, 0.0978803000, 0.2250252000, 0.5717996000, 1.4989691000", \ - "0.0281050000, 0.0351032000, 0.0524967000, 0.0981102000, 0.2248146000, 0.5702079000, 1.5002044000", \ - "0.0281507000, 0.0352181000, 0.0525809000, 0.0980667000, 0.2249960000, 0.5722066000, 1.5003607000", \ - "0.0280784000, 0.0352332000, 0.0525678000, 0.0980439000, 0.2244995000, 0.5722934000, 1.5006589000", \ - "0.0280208000, 0.0351428000, 0.0524781000, 0.0980254000, 0.2244360000, 0.5720076000, 1.4996381000", \ - "0.0281519000, 0.0352715000, 0.0525533000, 0.0980177000, 0.2247181000, 0.5691002000, 1.4990430000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.1585458000, 0.1673024000, 0.1852631000, 0.2202321000, 0.2851402000, 0.4273683000, 0.8015792000", \ - "0.1632717000, 0.1719763000, 0.1899767000, 0.2249401000, 0.2898699000, 0.4320793000, 0.8055122000", \ - "0.1756459000, 0.1843606000, 0.2023403000, 0.2373178000, 0.3022911000, 0.4444834000, 0.8179444000", \ - "0.2072113000, 0.2159339000, 0.2338665000, 0.2688407000, 0.3338173000, 0.4761155000, 0.8496272000", \ - "0.2833534000, 0.2919687000, 0.3098392000, 0.3447241000, 0.4096155000, 0.5519779000, 0.9256516000", \ - "0.4387484000, 0.4490443000, 0.4696940000, 0.5081408000, 0.5739857000, 0.7161222000, 1.0896599000", \ - "0.6930522000, 0.7066508000, 0.7341007000, 0.7834317000, 0.8540855000, 0.9964383000, 1.3697719000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0306440000, 0.0364617000, 0.0495730000, 0.0767944000, 0.1357889000, 0.3113584000, 0.8110241000", \ - "0.0303725000, 0.0365792000, 0.0496135000, 0.0768288000, 0.1357010000, 0.3118744000, 0.8079229000", \ - "0.0303456000, 0.0365104000, 0.0496127000, 0.0768489000, 0.1356178000, 0.3109338000, 0.8053417000", \ - "0.0303066000, 0.0362851000, 0.0495480000, 0.0769805000, 0.1357763000, 0.3132288000, 0.8098486000", \ - "0.0302752000, 0.0362804000, 0.0494859000, 0.0770907000, 0.1357743000, 0.3133461000, 0.8098709000", \ - "0.0396581000, 0.0459311000, 0.0590640000, 0.0839838000, 0.1377112000, 0.3130846000, 0.8071004000", \ - "0.0587900000, 0.0667760000, 0.0833960000, 0.1059696000, 0.1467576000, 0.3130688000, 0.8092227000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048086000, 0.0048127000, 0.0048222000, 0.0048314000, 0.0048528000, 0.0049022000, 0.0050159000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004804100, -0.004855400, -0.004973700, -0.004976200, -0.004981600, -0.004994000, -0.005022800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036270000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.305617200, -0.180503200, 0.0689271000", \ - "-0.527166700, -0.410597700, -0.197788400", \ - "-0.796128200, -0.689324900, -0.510695300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4109356000, 0.5470521000, 0.8225241000", \ - "0.6068503000, 0.7429668000, 1.0184388000", \ - "0.8440736000, 0.9801901000, 1.2520000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3114925000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrtp_1") { - leakage_power () { - value : 0.0154627000; - when : "RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0141340000; - when : "RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0136124000; - when : "!RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0065133000; - when : "RESET_B&CLK&!D&Q"; - } - leakage_power () { - value : 0.0057154000; - when : "RESET_B&!CLK&D&Q"; - } - leakage_power () { - value : 0.0146646000; - when : "!RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0142499000; - when : "RESET_B&!CLK&D&!Q"; - } - leakage_power () { - value : 0.0144105000; - when : "RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0137594000; - when : "!RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0059648000; - when : "RESET_B&CLK&D&Q"; - } - leakage_power () { - value : 0.0072568000; - when : "RESET_B&!CLK&!D&Q"; - } - leakage_power () { - value : 0.0140834000; - when : "!RESET_B&!CLK&D&!Q"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__dfrtp"; - cell_leakage_power : 0.0116522800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017880000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0248210000, 0.0247001000, 0.0244213000, 0.0244951000, 0.0246650000, 0.0250570000, 0.0259605000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162692000, 0.0161886000, 0.0160027000, 0.0160178000, 0.0160523000, 0.0161321000, 0.0163162000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018710000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2104295000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1544055000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061325000, 0.0060934000, 0.0060032000, 0.0060645000, 0.0062060000, 0.0065322000, 0.0072841000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000819900, -0.000893900, -0.001064500, -0.001014100, -0.000898100, -0.000630300, -1.3189464e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020060000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1069805000, 0.3212057000, 0.6280091000", \ - "-0.004705700, 0.2034160000, 0.5028952000", \ - "-0.090561800, 0.1126771000, 0.4084941000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0569316000, 0.1710592000, 0.2459290000", \ - "-0.015692100, 0.0850078000, 0.1476706000", \ - "-0.047837200, 0.0479798000, 0.1045391000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.039503900, -0.239080700, -0.495835300", \ - "0.0721823000, -0.126173800, -0.391473300", \ - "0.1507142000, -0.042759100, -0.309279300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.135321000, -0.186997400", \ - "0.0343405000, -0.062697300, -0.113153000", \ - "0.0603822000, -0.032993500, -0.083449200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0171284000, 0.0161019000, 0.0134161000, 0.0050389000, -0.019435800, -0.085739000, -0.262223400", \ - "0.0171220000, 0.0160981000, 0.0134081000, 0.0050168000, -0.019439800, -0.085740600, -0.262226800", \ - "0.0170997000, 0.0160716000, 0.0134012000, 0.0049959000, -0.019465100, -0.085772300, -0.262252300", \ - "0.0166261000, 0.0156011000, 0.0129013000, 0.0045399000, -0.019934800, -0.086229000, -0.262711400", \ - "0.0164124000, 0.0154028000, 0.0126979000, 0.0043304000, -0.020137500, -0.086443700, -0.262923300", \ - "0.0164342000, 0.0154124000, 0.0127181000, 0.0043237000, -0.020138600, -0.086443900, -0.262905400", \ - "0.0193898000, 0.0181215000, 0.0147324000, 0.0055818000, -0.019217600, -0.085666500, -0.262151500"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0181001000, 0.0196323000, 0.0235918000, 0.0333490000, 0.0583454000, 0.1249740000, 0.2997154000", \ - "0.0180276000, 0.0195799000, 0.0235335000, 0.0332873000, 0.0583111000, 0.1247668000, 0.2998356000", \ - "0.0180662000, 0.0196191000, 0.0235692000, 0.0333254000, 0.0583847000, 0.1240887000, 0.2991403000", \ - "0.0176395000, 0.0191792000, 0.0231335000, 0.0328865000, 0.0579609000, 0.1243084000, 0.2989525000", \ - "0.0172669000, 0.0188108000, 0.0227650000, 0.0325182000, 0.0575923000, 0.1239702000, 0.2989076000", \ - "0.0171415000, 0.0186787000, 0.0226226000, 0.0323315000, 0.0574034000, 0.1231545000, 0.2992284000", \ - "0.0187935000, 0.0201246000, 0.0237750000, 0.0333800000, 0.0581135000, 0.1242391000, 0.2991597000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228150, 0.0093508200, 0.0248204500, 0.0658824100, 0.1748757000"); - values("0.0157396000, 0.0160886000, 0.0151579000, 0.0074613000, -0.017052400, -0.083407400, -0.259878600", \ - "0.0157506000, 0.0160269000, 0.0151828000, 0.0074831000, -0.017040600, -0.083344400, -0.259832400", \ - "0.0154112000, 0.0158284000, 0.0149179000, 0.0072427000, -0.017263300, -0.083566000, -0.260043800", \ - "0.0152317000, 0.0155280000, 0.0146973000, 0.0070043000, -0.017508800, -0.083800700, -0.260270200", \ - "0.0150600000, 0.0155137000, 0.0145255000, 0.0067589000, -0.017766400, -0.084013900, -0.260450100", \ - "0.0176150000, 0.0166375000, 0.0143447000, 0.0064045000, -0.018140600, -0.084353100, -0.260733200", \ - "0.0211636000, 0.0197054000, 0.0160321000, 0.0065233000, -0.018429200, -0.084329300, -0.260661300"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1748760000; - max_transition : 1.5010180000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.3205468000, 0.3285705000, 0.3448832000, 0.3764707000, 0.4390814000, 0.5833211000, 0.9579996000", \ - "0.3252292000, 0.3332476000, 0.3495743000, 0.3810462000, 0.4437363000, 0.5878614000, 0.9613251000", \ - "0.3363183000, 0.3443343000, 0.3607777000, 0.3922170000, 0.4547698000, 0.5989648000, 0.9739256000", \ - "0.3619220000, 0.3699697000, 0.3863539000, 0.4178805000, 0.4804604000, 0.6245426000, 0.9986276000", \ - "0.4100587000, 0.4180828000, 0.4345367000, 0.4659638000, 0.5286447000, 0.6727341000, 1.0476536000", \ - "0.4774894000, 0.4854940000, 0.5019464000, 0.5332472000, 0.5958751000, 0.7399742000, 1.1139184000", \ - "0.5606871000, 0.5687483000, 0.5851437000, 0.6165748000, 0.6791321000, 0.8234491000, 1.1979370000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.2806588000, 0.2890743000, 0.3072760000, 0.3466627000, 0.4402498000, 0.6838601000, 1.3306278000", \ - "0.2851479000, 0.2935534000, 0.3117610000, 0.3510728000, 0.4448996000, 0.6887731000, 1.3326139000", \ - "0.2963803000, 0.3047824000, 0.3229582000, 0.3623298000, 0.4561983000, 0.6998975000, 1.3451157000", \ - "0.3222365000, 0.3306552000, 0.3488612000, 0.3881908000, 0.4820307000, 0.7259022000, 1.3702723000", \ - "0.3716069000, 0.3800257000, 0.3982319000, 0.4375540000, 0.5313842000, 0.7752501000, 1.4192134000", \ - "0.4425989000, 0.4509998000, 0.4692233000, 0.5085277000, 0.6023855000, 0.8458345000, 1.4923173000", \ - "0.5344707000, 0.5429029000, 0.5611386000, 0.6004795000, 0.6943219000, 0.9381940000, 1.5814352000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0276161000, 0.0327961000, 0.0443505000, 0.0702501000, 0.1346911000, 0.3147595000, 0.8093448000", \ - "0.0276049000, 0.0327057000, 0.0443627000, 0.0707660000, 0.1353094000, 0.3143154000, 0.8115072000", \ - "0.0275794000, 0.0328550000, 0.0444471000, 0.0699646000, 0.1349504000, 0.3144397000, 0.8066293000", \ - "0.0276285000, 0.0331049000, 0.0440596000, 0.0705573000, 0.1346817000, 0.3141206000, 0.8079590000", \ - "0.0276098000, 0.0327899000, 0.0442510000, 0.0703644000, 0.1350273000, 0.3145899000, 0.8074086000", \ - "0.0275945000, 0.0327394000, 0.0443622000, 0.0697951000, 0.1343934000, 0.3140920000, 0.8160825000", \ - "0.0277090000, 0.0329696000, 0.0441116000, 0.0707307000, 0.1345890000, 0.3131818000, 0.8067984000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0279461000, 0.0350404000, 0.0524217000, 0.0980541000, 0.2246004000, 0.5702736000, 1.4934123000", \ - "0.0279429000, 0.0350485000, 0.0525160000, 0.0978729000, 0.2248743000, 0.5723755000, 1.4983123000", \ - "0.0280579000, 0.0351981000, 0.0524830000, 0.0979726000, 0.2248406000, 0.5714472000, 1.4948329000", \ - "0.0279864000, 0.0351077000, 0.0524946000, 0.0979653000, 0.2246793000, 0.5724363000, 1.5009838000", \ - "0.0279830000, 0.0350984000, 0.0525039000, 0.0979317000, 0.2247952000, 0.5724641000, 1.5010179000", \ - "0.0280710000, 0.0350901000, 0.0525728000, 0.0980851000, 0.2248230000, 0.5703548000, 1.5008843000", \ - "0.0280645000, 0.0352020000, 0.0526385000, 0.0980108000, 0.2248394000, 0.5701389000, 1.4981630000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.1585677000, 0.1672655000, 0.1852319000, 0.2202003000, 0.2851021000, 0.4273302000, 0.8008631000", \ - "0.1633044000, 0.1720068000, 0.1899906000, 0.2250131000, 0.2899422000, 0.4320554000, 0.8062587000", \ - "0.1758231000, 0.1845706000, 0.2025034000, 0.2375044000, 0.3024684000, 0.4445744000, 0.8187774000", \ - "0.2072126000, 0.2159280000, 0.2338763000, 0.2688247000, 0.3338096000, 0.4759512000, 0.8502536000", \ - "0.2833229000, 0.2919706000, 0.3098116000, 0.3447088000, 0.4095877000, 0.5519251000, 0.9262172000", \ - "0.4387697000, 0.4491228000, 0.4697206000, 0.5081588000, 0.5740097000, 0.7161883000, 1.0901755000", \ - "0.6928376000, 0.7064248000, 0.7338690000, 0.7836662000, 0.8538858000, 0.9963302000, 1.3694934000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013271800, 0.0035228100, 0.0093508200, 0.0248204000, 0.0658824000, 0.1748760000"); - values("0.0303011000, 0.0364808000, 0.0495752000, 0.0767955000, 0.1356754000, 0.3112656000, 0.8078213000", \ - "0.0306832000, 0.0362277000, 0.0494782000, 0.0769424000, 0.1357306000, 0.3113617000, 0.8113011000", \ - "0.0304888000, 0.0363916000, 0.0495733000, 0.0768220000, 0.1358196000, 0.3112784000, 0.8112468000", \ - "0.0302470000, 0.0362041000, 0.0495517000, 0.0768931000, 0.1358454000, 0.3113406000, 0.8114990000", \ - "0.0305797000, 0.0361349000, 0.0493996000, 0.0769136000, 0.1357311000, 0.3115150000, 0.8109726000", \ - "0.0396964000, 0.0466957000, 0.0593671000, 0.0838815000, 0.1378089000, 0.3112067000, 0.8140101000", \ - "0.0588429000, 0.0668196000, 0.0833944000, 0.1061842000, 0.1467717000, 0.3133334000, 0.8108602000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048033000, 0.0048080000, 0.0048188000, 0.0048281000, 0.0048499000, 0.0049002000, 0.0050162000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005448600, -0.005518700, -0.005680300, -0.005681800, -0.005685000, -0.005692200, -0.005709000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036320000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.228712900, -0.101157600, 0.1690247000", \ - "-0.378240900, -0.260451200, -0.024448600", \ - "-0.503159500, -0.392694000, -0.176222700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4359681000, 0.7028952000", \ - "0.4347311000, 0.5684063000, 0.8292298000", \ - "0.5547669000, 0.6835593000, 0.9370586000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1807697000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrtp_2") { - leakage_power () { - value : 0.0137865000; - when : "RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0124578000; - when : "RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0119361000; - when : "!RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0068843000; - when : "RESET_B&CLK&!D&Q"; - } - leakage_power () { - value : 0.0060864000; - when : "RESET_B&!CLK&D&Q"; - } - leakage_power () { - value : 0.0129884000; - when : "!RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0125736000; - when : "RESET_B&!CLK&D&!Q"; - } - leakage_power () { - value : 0.0127343000; - when : "RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0120832000; - when : "!RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0063358000; - when : "RESET_B&CLK&D&Q"; - } - leakage_power () { - value : 0.0076278000; - when : "RESET_B&!CLK&!D&Q"; - } - leakage_power () { - value : 0.0124072000; - when : "!RESET_B&!CLK&D&!Q"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__dfrtp"; - cell_leakage_power : 0.0106584500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017960000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0247991000, 0.0246767000, 0.0243946000, 0.0244701000, 0.0246440000, 0.0250452000, 0.0259699000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162695000, 0.0161891000, 0.0160039000, 0.0160187000, 0.0160527000, 0.0161313000, 0.0163124000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018700000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2115280000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1697846000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061322000, 0.0060926000, 0.0060011000, 0.0060643000, 0.0062100000, 0.0065459000, 0.0073203000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000821700, -0.000891100, -0.001050900, -0.001000400, -0.000884200, -0.000616000, 2.2639846e-06"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020050000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1082012000, 0.3236471000, 0.6292298000", \ - "-0.004705700, 0.2046367000, 0.5041159000", \ - "-0.089341100, 0.1138978000, 0.4097148000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0605937000, 0.1759421000, 0.2532533000", \ - "-0.013250700, 0.0898906000, 0.1525534000", \ - "-0.046616500, 0.0504212000, 0.1082012000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.035841800, -0.235418600, -0.486069600", \ - "0.0758444000, -0.122511700, -0.384149100", \ - "0.1543763000, -0.039097000, -0.300734400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.134100300, -0.186997400", \ - "0.0343405000, -0.061476600, -0.111932300", \ - "0.0603822000, -0.032993500, -0.083449200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014695340, 0.0043190590, 0.0126940100, 0.0373085400, 0.1096523000, 0.3222755000"); - values("0.0203484000, 0.0188107000, 0.0148470000, 0.0033013000, -0.034778300, -0.151311300, -0.495530100", \ - "0.0203521000, 0.0188224000, 0.0149099000, 0.0032598000, -0.034760500, -0.151273700, -0.495511300", \ - "0.0202778000, 0.0187803000, 0.0147992000, 0.0032225000, -0.034807900, -0.151318500, -0.495552500", \ - "0.0198559000, 0.0182973000, 0.0143677000, 0.0027531000, -0.035245700, -0.151788700, -0.496008900", \ - "0.0195965000, 0.0180628000, 0.0141282000, 0.0025195000, -0.035487500, -0.152004200, -0.496248300", \ - "0.0196293000, 0.0181043000, 0.0141667000, 0.0025616000, -0.035466800, -0.151977300, -0.496208900", \ - "0.0242052000, 0.0226387000, 0.0181005000, 0.0049447000, -0.034322500, -0.151224600, -0.495443400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014695340, 0.0043190590, 0.0126940100, 0.0373085400, 0.1096523000, 0.3222755000"); - values("0.0229966000, 0.0246952000, 0.0296325000, 0.0438738000, 0.0838429000, 0.1998328000, 0.5430187000", \ - "0.0229625000, 0.0246099000, 0.0295749000, 0.0437746000, 0.0837712000, 0.1996722000, 0.5407323000", \ - "0.0229555000, 0.0246372000, 0.0295796000, 0.0437837000, 0.0837843000, 0.1998680000, 0.5430884000", \ - "0.0225530000, 0.0242160000, 0.0291592000, 0.0433758000, 0.0833498000, 0.1995060000, 0.5430637000", \ - "0.0221852000, 0.0238499000, 0.0288084000, 0.0430058000, 0.0830055000, 0.1993583000, 0.5414476000", \ - "0.0220745000, 0.0237263000, 0.0287381000, 0.0428349000, 0.0828826000, 0.1990134000, 0.5397984000", \ - "0.0239697000, 0.0255818000, 0.0303188000, 0.0440760000, 0.0837570000, 0.2003888000, 0.5414610000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014695340, 0.0043190590, 0.0126940100, 0.0373085400, 0.1096523000, 0.3222755000"); - values("0.0186151000, 0.0172151000, 0.0157756000, 0.0058797000, -0.032212700, -0.148905600, -0.493020400", \ - "0.0184793000, 0.0170967000, 0.0156035000, 0.0057285000, -0.032352700, -0.149003700, -0.493235600", \ - "0.0182068000, 0.0168926000, 0.0153485000, 0.0055083000, -0.032575000, -0.149222600, -0.493465400", \ - "0.0180679000, 0.0167215000, 0.0152630000, 0.0053455000, -0.032751000, -0.149386800, -0.493604800", \ - "0.0178179000, 0.0165285000, 0.0150328000, 0.0050330000, -0.033112100, -0.149693100, -0.493861800", \ - "0.0181921000, 0.0169493000, 0.0153766000, 0.0046922000, -0.033573900, -0.150122000, -0.494169800", \ - "0.0269531000, 0.0250634000, 0.0199545000, 0.0060357000, -0.033885200, -0.150209700, -0.494207100"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.3222760000; - max_transition : 1.5043160000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.3506981000, 0.3578429000, 0.3736053000, 0.4046606000, 0.4644471000, 0.5966773000, 0.9533240000", \ - "0.3555128000, 0.3626774000, 0.3784652000, 0.4094500000, 0.4692706000, 0.6013078000, 0.9575990000", \ - "0.3664820000, 0.3736011000, 0.3894114000, 0.4204237000, 0.4802677000, 0.6124308000, 0.9688592000", \ - "0.3922195000, 0.3993820000, 0.4151598000, 0.4461916000, 0.5061010000, 0.6382483000, 0.9948533000", \ - "0.4400264000, 0.4471581000, 0.4629913000, 0.4939760000, 0.5538471000, 0.6859292000, 1.0426708000", \ - "0.5076085000, 0.5147565000, 0.5305347000, 0.5614457000, 0.6213486000, 0.7535439000, 1.1102849000", \ - "0.5910465000, 0.5981828000, 0.6139850000, 0.6450667000, 0.7050003000, 0.8369819000, 1.1935279000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.3026401000, 0.3099117000, 0.3266614000, 0.3627330000, 0.4471993000, 0.6798129000, 1.3584693000", \ - "0.3070760000, 0.3144207000, 0.3311246000, 0.3671863000, 0.4516074000, 0.6838397000, 1.3629281000", \ - "0.3182307000, 0.3256407000, 0.3424118000, 0.3784590000, 0.4629895000, 0.6955224000, 1.3738345000", \ - "0.3441165000, 0.3514454000, 0.3682279000, 0.4042456000, 0.4887977000, 0.7209295000, 1.3994731000", \ - "0.3935284000, 0.4008723000, 0.4175835000, 0.4536468000, 0.5380756000, 0.7701418000, 1.4497047000", \ - "0.4647741000, 0.4720636000, 0.4888340000, 0.5249087000, 0.6093643000, 0.8413126000, 1.5209098000", \ - "0.5564326000, 0.5638225000, 0.5806547000, 0.6166566000, 0.7011877000, 0.9334818000, 1.6102851000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.0302114000, 0.0345965000, 0.0445766000, 0.0665179000, 0.1179698000, 0.2669787000, 0.7376070000", \ - "0.0301657000, 0.0348103000, 0.0449336000, 0.0655740000, 0.1178836000, 0.2681788000, 0.7333332000", \ - "0.0301107000, 0.0346662000, 0.0444555000, 0.0656977000, 0.1180596000, 0.2677971000, 0.7323838000", \ - "0.0302036000, 0.0345440000, 0.0444469000, 0.0656107000, 0.1184822000, 0.2674249000, 0.7394285000", \ - "0.0301603000, 0.0348230000, 0.0444397000, 0.0658097000, 0.1177101000, 0.2681557000, 0.7396042000", \ - "0.0301706000, 0.0347782000, 0.0444565000, 0.0656046000, 0.1183138000, 0.2678191000, 0.7375676000", \ - "0.0301341000, 0.0348777000, 0.0445355000, 0.0658491000, 0.1179025000, 0.2675720000, 0.7326744000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.0275277000, 0.0328535000, 0.0465860000, 0.0823164000, 0.1885026000, 0.5181492000, 1.5043161000", \ - "0.0275251000, 0.0328850000, 0.0465020000, 0.0821602000, 0.1883643000, 0.5185988000, 1.5024184000", \ - "0.0274507000, 0.0328705000, 0.0465488000, 0.0821606000, 0.1882022000, 0.5177475000, 1.5042572000", \ - "0.0274971000, 0.0329008000, 0.0465969000, 0.0822955000, 0.1885780000, 0.5177135000, 1.4983594000", \ - "0.0275243000, 0.0328452000, 0.0464902000, 0.0821579000, 0.1884169000, 0.5186088000, 1.4998617000", \ - "0.0275645000, 0.0329245000, 0.0465879000, 0.0821158000, 0.1887496000, 0.5183242000, 1.4990490000", \ - "0.0276212000, 0.0329258000, 0.0465952000, 0.0823719000, 0.1885167000, 0.5186943000, 1.4987313000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.1904505000, 0.1980985000, 0.2151574000, 0.2490607000, 0.3127762000, 0.4400064000, 0.7943649000", \ - "0.1954828000, 0.2030190000, 0.2201839000, 0.2539823000, 0.3178135000, 0.4451570000, 0.8001195000", \ - "0.2082668000, 0.2158824000, 0.2329416000, 0.2668514000, 0.3306072000, 0.4578488000, 0.8121519000", \ - "0.2394956000, 0.2471597000, 0.2642371000, 0.2979553000, 0.3617978000, 0.4891957000, 0.8438656000", \ - "0.3151543000, 0.3228215000, 0.3398559000, 0.3735199000, 0.4372757000, 0.5646794000, 0.9191252000", \ - "0.4830110000, 0.4914439000, 0.5099097000, 0.5456875000, 0.6102654000, 0.7374980000, 1.0925341000", \ - "0.7665527000, 0.7774704000, 0.8016584000, 0.8484792000, 0.9241213000, 1.0525529000, 1.4065683000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014695300, 0.0043190600, 0.0126940000, 0.0373085000, 0.1096520000, 0.3222760000"); - values("0.0330795000, 0.0378862000, 0.0488921000, 0.0726617000, 0.1193341000, 0.2604055000, 0.7370696000", \ - "0.0332974000, 0.0379373000, 0.0487879000, 0.0727741000, 0.1195585000, 0.2599789000, 0.7319402000", \ - "0.0331832000, 0.0380939000, 0.0489242000, 0.0729451000, 0.1195080000, 0.2602983000, 0.7370345000", \ - "0.0330989000, 0.0382788000, 0.0492634000, 0.0728516000, 0.1196872000, 0.2597813000, 0.7369373000", \ - "0.0330131000, 0.0381402000, 0.0489100000, 0.0728797000, 0.1196449000, 0.2599179000, 0.7370473000", \ - "0.0401218000, 0.0448571000, 0.0561750000, 0.0779993000, 0.1211739000, 0.2604540000, 0.7343290000", \ - "0.0612523000, 0.0670147000, 0.0804231000, 0.1064808000, 0.1383758000, 0.2636759000, 0.7335820000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0036030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047655000, 0.0047821000, 0.0048205000, 0.0048299000, 0.0048518000, 0.0049023000, 0.0050187000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005485000, -0.005544200, -0.005680600, -0.005682000, -0.005685100, -0.005692200, -0.005708500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036120000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.218947300, -0.071860700, 0.2801087000", \ - "-0.368475300, -0.233595700, 0.0793112000", \ - "-0.494614600, -0.367059300, -0.081007800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4347474000, 0.7028952000", \ - "0.4359518000, 0.5684063000, 0.8292298000", \ - "0.5547669000, 0.6835593000, 0.9370586000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2313012000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfrtp_4") { - leakage_power () { - value : 0.0134502000; - when : "RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0121215000; - when : "RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0115999000; - when : "!RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0078330000; - when : "RESET_B&CLK&!D&Q"; - } - leakage_power () { - value : 0.0070350000; - when : "RESET_B&!CLK&D&Q"; - } - leakage_power () { - value : 0.0126521000; - when : "!RESET_B&CLK&D&!Q"; - } - leakage_power () { - value : 0.0122373000; - when : "RESET_B&!CLK&D&!Q"; - } - leakage_power () { - value : 0.0123980000; - when : "RESET_B&CLK&!D&!Q"; - } - leakage_power () { - value : 0.0117469000; - when : "!RESET_B&!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0072844000; - when : "RESET_B&CLK&D&Q"; - } - leakage_power () { - value : 0.0085764000; - when : "RESET_B&!CLK&!D&Q"; - } - leakage_power () { - value : 0.0120709000; - when : "!RESET_B&!CLK&D&!Q"; - } - area : 28.777600000; - cell_footprint : "sky130_fd_sc_hd__dfrtp"; - cell_leakage_power : 0.0107504600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017940000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0247727000, 0.0246491000, 0.0243641000, 0.0244335000, 0.0245934000, 0.0249623000, 0.0258124000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163760000, 0.0162584000, 0.0159874000, 0.0160035000, 0.0160404000, 0.0161257000, 0.0163223000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018700000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2104295000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1972474000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0019770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0061312000, 0.0060923000, 0.0060027000, 0.0060655000, 0.0062100000, 0.0065434000, 0.0073120000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000826300, -0.000895100, -0.001053500, -0.001002700, -0.000885600, -0.000615600, 6.746164e-06"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020060000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1069805000, 0.3212057000, 0.6280091000", \ - "-0.004705700, 0.2034160000, 0.5028952000", \ - "-0.090561800, 0.1126771000, 0.4084941000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0605937000, 0.1759421000, 0.2532533000", \ - "-0.013250700, 0.0898906000, 0.1537741000", \ - "-0.046616500, 0.0504212000, 0.1082012000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.035841800, -0.234197900, -0.484849000", \ - "0.0758444000, -0.122511700, -0.384149100", \ - "0.1543763000, -0.039097000, -0.300734400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.135321000, -0.188218100", \ - "0.0343405000, -0.062697300, -0.113153000", \ - "0.0603822000, -0.032993500, -0.083449200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0299695000, 0.0279332000, 0.0219585000, 0.0054091000, -0.050107800, -0.238744700, -0.853077600", \ - "0.0299944000, 0.0279360000, 0.0220453000, 0.0054443000, -0.050062500, -0.238642800, -0.853007100", \ - "0.0300718000, 0.0280837000, 0.0221125000, 0.0055147000, -0.049969800, -0.238632800, -0.852971800", \ - "0.0296403000, 0.0276000000, 0.0216699000, 0.0050146000, -0.050430700, -0.239058000, -0.853392800", \ - "0.0293773000, 0.0273888000, 0.0214311000, 0.0048182000, -0.050663500, -0.239325900, -0.853667900", \ - "0.0293486000, 0.0273638000, 0.0214234000, 0.0048024000, -0.050621400, -0.239305600, -0.853608600", \ - "0.0370078000, 0.0349519000, 0.0288566000, 0.0103630000, -0.048337400, -0.238551500, -0.852885200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0347175000, 0.0365158000, 0.0424081000, 0.0616755000, 0.1218193000, 0.3131402000, 0.9192339000", \ - "0.0347044000, 0.0364778000, 0.0423421000, 0.0616478000, 0.1218964000, 0.3127662000, 0.9197844000", \ - "0.0348540000, 0.0366139000, 0.0425371000, 0.0618122000, 0.1220448000, 0.3116969000, 0.9213186000", \ - "0.0343887000, 0.0361597000, 0.0420608000, 0.0613458000, 0.1215771000, 0.3117331000, 0.9209227000", \ - "0.0339810000, 0.0357782000, 0.0416577000, 0.0609860000, 0.1211210000, 0.3114851000, 0.9245174000", \ - "0.0339275000, 0.0357173000, 0.0415838000, 0.0608545000, 0.1210585000, 0.3112393000, 0.9247014000", \ - "0.0364558000, 0.0382480000, 0.0440252000, 0.0627561000, 0.1219810000, 0.3120629000, 0.9195208000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0338738000, 0.0318746000, 0.0259394000, 0.0084556000, -0.046990300, -0.236451000, -0.850829300", \ - "0.0337973000, 0.0317783000, 0.0258342000, 0.0082823000, -0.047123000, -0.236609600, -0.851038100", \ - "0.0335307000, 0.0315160000, 0.0255985000, 0.0080700000, -0.047353400, -0.236766800, -0.851209200", \ - "0.0335631000, 0.0315661000, 0.0256394000, 0.0081175000, -0.047320100, -0.236794600, -0.851200100", \ - "0.0333516000, 0.0313601000, 0.0254519000, 0.0078388000, -0.047657200, -0.237097500, -0.851416500", \ - "0.0333880000, 0.0313433000, 0.0253175000, 0.0075635000, -0.048187700, -0.237681000, -0.851803800", \ - "0.0363885000, 0.0341078000, 0.0274030000, 0.0081871000, -0.048051600, -0.237911200, -0.852013100"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.5511570000; - max_transition : 1.5066460000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.4278874000, 0.4333774000, 0.4478247000, 0.4798925000, 0.5433685000, 0.6765929000, 1.0213966000", \ - "0.4326854000, 0.4382105000, 0.4526138000, 0.4847573000, 0.5484528000, 0.6811902000, 1.0260175000", \ - "0.4436976000, 0.4491410000, 0.4635965000, 0.4956470000, 0.5594823000, 0.6923557000, 1.0370583000", \ - "0.4694380000, 0.4749215000, 0.4893426000, 0.5214400000, 0.5852945000, 0.7182639000, 1.0626089000", \ - "0.5172320000, 0.5226768000, 0.5371328000, 0.5691848000, 0.6330212000, 0.7658952000, 1.1105971000", \ - "0.5847856000, 0.5902963000, 0.6047497000, 0.6368280000, 0.7008215000, 0.8336002000, 1.1780426000", \ - "0.6682113000, 0.6737185000, 0.6881254000, 0.7202116000, 0.7840909000, 0.9170253000, 1.2613036000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.3572830000, 0.3631876000, 0.3786668000, 0.4143570000, 0.4970749000, 0.7233552000, 1.4371371000", \ - "0.3617534000, 0.3676758000, 0.3831430000, 0.4188302000, 0.5014407000, 0.7284192000, 1.4434673000", \ - "0.3729384000, 0.3788586000, 0.3944281000, 0.4301267000, 0.5128277000, 0.7393517000, 1.4570324000", \ - "0.3988477000, 0.4047517000, 0.4202051000, 0.4559296000, 0.5385452000, 0.7655248000, 1.4803054000", \ - "0.4482011000, 0.4541415000, 0.4696181000, 0.5053349000, 0.5880437000, 0.8144909000, 1.5291550000", \ - "0.5194781000, 0.5253744000, 0.5409241000, 0.5765455000, 0.6592902000, 0.8861345000, 1.5992812000", \ - "0.6114050000, 0.6173301000, 0.6328089000, 0.6685227000, 0.7512245000, 0.9777996000, 1.6934989000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0474066000, 0.0505642000, 0.0593778000, 0.0785944000, 0.1249593000, 0.2533997000, 0.6811097000", \ - "0.0473712000, 0.0505077000, 0.0591728000, 0.0788036000, 0.1247328000, 0.2530802000, 0.6820092000", \ - "0.0475022000, 0.0504711000, 0.0592665000, 0.0785787000, 0.1243856000, 0.2534271000, 0.6820495000", \ - "0.0473406000, 0.0505583000, 0.0588699000, 0.0784091000, 0.1246490000, 0.2531278000, 0.6811394000", \ - "0.0475053000, 0.0504704000, 0.0592665000, 0.0785743000, 0.1243768000, 0.2518425000, 0.6820486000", \ - "0.0474097000, 0.0506080000, 0.0591290000, 0.0795225000, 0.1255951000, 0.2530649000, 0.6814603000", \ - "0.0472337000, 0.0505736000, 0.0589243000, 0.0784877000, 0.1249136000, 0.2530928000, 0.6793409000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0386571000, 0.0426187000, 0.0541777000, 0.0841579000, 0.1750732000, 0.4824007000, 1.4984988000", \ - "0.0385766000, 0.0425911000, 0.0540197000, 0.0843471000, 0.1750427000, 0.4816626000, 1.5013254000", \ - "0.0386927000, 0.0428007000, 0.0540112000, 0.0844763000, 0.1749538000, 0.4823544000, 1.5066455000", \ - "0.0386188000, 0.0425989000, 0.0539225000, 0.0844749000, 0.1750902000, 0.4818559000, 1.5024750000", \ - "0.0385050000, 0.0426073000, 0.0540259000, 0.0843623000, 0.1750873000, 0.4822105000, 1.5017908000", \ - "0.0385929000, 0.0423346000, 0.0539535000, 0.0845894000, 0.1750607000, 0.4815070000, 1.5060172000", \ - "0.0386478000, 0.0425863000, 0.0540873000, 0.0842954000, 0.1750144000, 0.4808806000, 1.5000137000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.2726160000, 0.2784066000, 0.2938796000, 0.3284342000, 0.3968920000, 0.5207850000, 0.8564664000", \ - "0.2778151000, 0.2836729000, 0.2990899000, 0.3336493000, 0.4021628000, 0.5260182000, 0.8617533000", \ - "0.2909576000, 0.2967514000, 0.3122574000, 0.3467697000, 0.4152801000, 0.5391452000, 0.8749398000", \ - "0.3224239000, 0.3282123000, 0.3436771000, 0.3782305000, 0.4467129000, 0.5706233000, 0.9061194000", \ - "0.3973799000, 0.4032437000, 0.4186159000, 0.4531827000, 0.5216273000, 0.6455099000, 0.9812883000", \ - "0.5742110000, 0.5800556000, 0.5953559000, 0.6297496000, 0.6979708000, 0.8217648000, 1.1575997000", \ - "0.9124713000, 0.9197019000, 0.9385788000, 0.9806795000, 1.0600536000, 1.1860584000, 1.5207570000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0516987000, 0.0550003000, 0.0642348000, 0.0861671000, 0.1273802000, 0.2358921000, 0.6706659000", \ - "0.0519331000, 0.0553446000, 0.0648162000, 0.0867895000, 0.1271400000, 0.2362608000, 0.6703673000", \ - "0.0516173000, 0.0554186000, 0.0642397000, 0.0863431000, 0.1274503000, 0.2362114000, 0.6711176000", \ - "0.0517273000, 0.0550219000, 0.0642619000, 0.0861693000, 0.1272256000, 0.2363089000, 0.6703250000", \ - "0.0521422000, 0.0552000000, 0.0647128000, 0.0865526000, 0.1274985000, 0.2362744000, 0.6704258000", \ - "0.0526795000, 0.0559651000, 0.0653596000, 0.0872004000, 0.1275650000, 0.2362612000, 0.6702304000", \ - "0.0795400000, 0.0830614000, 0.0923383000, 0.1153623000, 0.1486292000, 0.2409714000, 0.6689861000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047825000, 0.0047938000, 0.0048198000, 0.0048295000, 0.0048520000, 0.0049039000, 0.0050236000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005531400, -0.005506400, -0.005448700, -0.005463200, -0.005496700, -0.005573700, -0.005751000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036380000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.217726600, -0.058432900, 0.3643372000", \ - "-0.368475300, -0.220168000, 0.1635397000", \ - "-0.494614600, -0.354852200, 0.0020000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4359681000, 0.7028952000", \ - "0.4359518000, 0.5684063000, 0.8292298000", \ - "0.5547669000, 0.6835593000, 0.9370586000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3213791000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfsbp_1") { - leakage_power () { - value : 0.0134321000; - when : "CLK&D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0113719000; - when : "!CLK&!D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0189673000; - when : "CLK&!D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0193286000; - when : "CLK&!D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0198350000; - when : "!CLK&D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0194834000; - when : "CLK&D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0127316000; - when : "!CLK&D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0114902000; - when : "CLK&!D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0191175000; - when : "!CLK&!D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0198447000; - when : "CLK&D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0191811000; - when : "!CLK&!D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0190979000; - when : "!CLK&D&!SET_B&Q&!Q_N"; - } - area : 28.777600000; - cell_footprint : "sky130_fd_sc_hd__dfsbp"; - cell_leakage_power : 0.0169900900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017720000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0231981000, 0.0231169000, 0.0229298000, 0.0229748000, 0.0230789000, 0.0233188000, 0.0238718000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172321000, 0.0171624000, 0.0170018000, 0.0170326000, 0.0171038000, 0.0172679000, 0.0176461000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018520000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1928533000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4125555000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073564000, 0.0072833000, 0.0071148000, 0.0072676000, 0.0076202000, 0.0084329000, 0.0103061000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000138000, -0.000310500, -0.000708100, -0.000569900, -0.000250900, 0.0004843000, 0.0021789000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0642559000, 0.2418600000, 0.4522279000", \ - "-0.043768200, 0.1240703000, 0.3271139000", \ - "-0.123520800, 0.0357728000, 0.2351543000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0508281000, 0.1564108000, 0.2361634000", \ - "-0.015692100, 0.0813457000, 0.1501120000", \ - "-0.042954400, 0.0504212000, 0.1167461000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.011427700, -0.168279900, -0.339585300", \ - "0.0953757000, -0.059035200, -0.238885400", \ - "0.1653626000, 0.0158346000, -0.165236300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.130438200, -0.194321600", \ - "0.0282370000, -0.065138700, -0.127801400", \ - "0.0506165000, -0.041538400, -0.104201200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("3.515000e-05, 0.0039177000, 0.0126039000, 0.0298313000, 0.0617193000, 0.1301414000, 0.2983422000", \ - "9.100000e-06, 0.0038751000, 0.0125316000, 0.0297197000, 0.0616970000, 0.1296774000, 0.2989173000", \ - "-4.82500e-05, 0.0037934000, 0.0124056000, 0.0295084000, 0.0612787000, 0.1293410000, 0.2987367000", \ - "-4.88000e-05, 0.0037959000, 0.0124130000, 0.0295217000, 0.0612874000, 0.1297194000, 0.2968148000", \ - "-4.12000e-05, 0.0038219000, 0.0124774000, 0.0296594000, 0.0615676000, 0.1294767000, 0.2977142000", \ - "-3.63500e-05, 0.0038540000, 0.0125539000, 0.0298199000, 0.0617099000, 0.1296706000, 0.2982476000", \ - "3.350000e-05, 0.0040655000, 0.0130081000, 0.0305667000, 0.0630352000, 0.1316031000, 0.3013449000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("-0.005282000, -0.000682000, 0.0077794000, 0.0166734000, 0.0106840000, -0.040771800, -0.202176400", \ - "-0.005252800, -0.000669700, 0.0077919000, 0.0166554000, 0.0106662000, -0.040828500, -0.202245300", \ - "-0.005182300, -0.000604700, 0.0078366000, 0.0166307000, 0.0106061000, -0.040905100, -0.202305800", \ - "-0.005219200, -0.000669800, 0.0077071000, 0.0164173000, 0.0102984000, -0.041276500, -0.202749200", \ - "-0.005264400, -0.000724200, 0.0076169000, 0.0163017000, 0.0101311000, -0.041468100, -0.202936400", \ - "-0.005341800, -0.000801600, 0.0075449000, 0.0162557000, 0.0101018000, -0.041480300, -0.202942500", \ - "-0.005472300, -0.000845800, 0.0076764000, 0.0166413000, 0.0106195000, -0.040984600, -0.202392700"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("-0.006835400, -0.004131300, 0.0021514000, 0.0161003000, 0.0455878000, 0.1115422000, 0.2794613000", \ - "-0.006807400, -0.004108900, 0.0021718000, 0.0160992000, 0.0455421000, 0.1115909000, 0.2795423000", \ - "-0.006738400, -0.004068500, 0.0021639000, 0.0160308000, 0.0452346000, 0.1113497000, 0.2775920000", \ - "-0.006772500, -0.004113600, 0.0020535000, 0.0158570000, 0.0450231000, 0.1110924000, 0.2772558000", \ - "-0.006829200, -0.004193700, 0.0019346000, 0.0156660000, 0.0447151000, 0.1107516000, 0.2772103000", \ - "-0.006912700, -0.004300800, 0.0018057000, 0.0154877000, 0.0445909000, 0.1105134000, 0.2786008000", \ - "-0.006980300, -0.004183200, 0.0022749000, 0.0158988000, 0.0450058000, 0.1109856000, 0.2787556000"); - } - } - max_capacitance : 0.1666360000; - max_transition : 1.5033150000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.3534951000, 0.3590465000, 0.3706871000, 0.3944776000, 0.4475048000, 0.5815337000, 0.9348584000", \ - "0.3581355000, 0.3637010000, 0.3753339000, 0.3991115000, 0.4521342000, 0.5861965000, 0.9382307000", \ - "0.3692874000, 0.3748426000, 0.3864789000, 0.4102685000, 0.4632795000, 0.5973448000, 0.9509432000", \ - "0.3949417000, 0.4004940000, 0.4121342000, 0.4359242000, 0.4889371000, 0.6230313000, 0.9760615000", \ - "0.4429323000, 0.4484789000, 0.4601147000, 0.4839056000, 0.5369178000, 0.6710110000, 1.0233021000", \ - "0.5114730000, 0.5170215000, 0.5285590000, 0.5524105000, 0.6054723000, 0.7395858000, 1.0923044000", \ - "0.5958123000, 0.6013642000, 0.6129364000, 0.6367649000, 0.6898205000, 0.8238461000, 1.1759211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.5657977000, 0.5748298000, 0.5927237000, 0.6301706000, 0.7231439000, 0.9676244000, 1.6094922000", \ - "0.5706453000, 0.5795838000, 0.5974403000, 0.6349216000, 0.7280196000, 0.9725284000, 1.6153854000", \ - "0.5816583000, 0.5906941000, 0.6085406000, 0.6460561000, 0.7389891000, 0.9840130000, 1.6264388000", \ - "0.6068564000, 0.6157832000, 0.6336882000, 0.6711203000, 0.7641018000, 1.0091947000, 1.6514279000", \ - "0.6541023000, 0.6630156000, 0.6808718000, 0.7183297000, 0.8113624000, 1.0564037000, 1.6987300000", \ - "0.7228717000, 0.7317724000, 0.7496238000, 0.7870804000, 0.8802190000, 1.1249955000, 1.7675561000", \ - "0.8116735000, 0.8207270000, 0.8385670000, 0.8760837000, 0.9689808000, 1.2139183000, 1.8561379000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0188658000, 0.0231827000, 0.0325165000, 0.0557400000, 0.1198839000, 0.2962165000, 0.7651708000", \ - "0.0188245000, 0.0229571000, 0.0325147000, 0.0560633000, 0.1197140000, 0.2961951000, 0.7684137000", \ - "0.0188400000, 0.0228175000, 0.0325217000, 0.0560647000, 0.1194918000, 0.2954673000, 0.7678048000", \ - "0.0188219000, 0.0231824000, 0.0325179000, 0.0560333000, 0.1195800000, 0.2951770000, 0.7724306000", \ - "0.0188035000, 0.0231633000, 0.0325186000, 0.0560394000, 0.1196129000, 0.2956440000, 0.7680034000", \ - "0.0188550000, 0.0228205000, 0.0321994000, 0.0561207000, 0.1197224000, 0.2957103000, 0.7721849000", \ - "0.0188780000, 0.0228435000, 0.0323410000, 0.0561283000, 0.1197721000, 0.2961806000, 0.7622312000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0341896000, 0.0399840000, 0.0547042000, 0.0982738000, 0.2275807000, 0.5749576000, 1.4961218000", \ - "0.0341662000, 0.0404142000, 0.0547963000, 0.0981882000, 0.2276361000, 0.5756169000, 1.4921433000", \ - "0.0341160000, 0.0399388000, 0.0547728000, 0.0984198000, 0.2272029000, 0.5750364000, 1.4960819000", \ - "0.0342505000, 0.0401033000, 0.0547863000, 0.0983603000, 0.2277775000, 0.5752060000, 1.4953251000", \ - "0.0343742000, 0.0405210000, 0.0548288000, 0.0982462000, 0.2271875000, 0.5752336000, 1.4955533000", \ - "0.0343690000, 0.0405005000, 0.0548258000, 0.0982485000, 0.2280472000, 0.5760561000, 1.4920873000", \ - "0.0341201000, 0.0399576000, 0.0547918000, 0.0983879000, 0.2274918000, 0.5759853000, 1.4911741000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.3433988000, 0.3500834000, 0.3652084000, 0.4012805000, 0.4944236000, 0.7382737000, 1.3812987000", \ - "0.3481629000, 0.3547717000, 0.3699146000, 0.4059869000, 0.4989876000, 0.7429636000, 1.3860240000", \ - "0.3606546000, 0.3673191000, 0.3824310000, 0.4185100000, 0.5116392000, 0.7551719000, 1.4009204000", \ - "0.3938441000, 0.4005064000, 0.4156184000, 0.4516911000, 0.5448178000, 0.7884100000, 1.4314965000", \ - "0.4710785000, 0.4777199000, 0.4927864000, 0.5289164000, 0.6220303000, 0.8658917000, 1.5090165000", \ - "0.6351247000, 0.6417223000, 0.6568332000, 0.6928798000, 0.7859017000, 1.0298159000, 1.6739279000", \ - "0.9333746000, 0.9402150000, 0.9555824000, 0.9917447000, 1.0849325000, 1.3286715000, 1.9720419000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0234538000, 0.0296750000, 0.0468861000, 0.0952136000, 0.2264641000, 0.5764731000, 1.5021114000", \ - "0.0233235000, 0.0295695000, 0.0467683000, 0.0950708000, 0.2267160000, 0.5762625000, 1.5032504000", \ - "0.0233615000, 0.0295956000, 0.0467402000, 0.0950858000, 0.2269195000, 0.5773980000, 1.4986062000", \ - "0.0233401000, 0.0295807000, 0.0467173000, 0.0951059000, 0.2268880000, 0.5754953000, 1.4944493000", \ - "0.0232783000, 0.0294908000, 0.0466830000, 0.0951862000, 0.2268439000, 0.5771051000, 1.4990120000", \ - "0.0232211000, 0.0294908000, 0.0467173000, 0.0950203000, 0.2267361000, 0.5762435000, 1.4959806000", \ - "0.0247078000, 0.0306446000, 0.0474553000, 0.0954508000, 0.2268929000, 0.5760369000, 1.5033154000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013317720, 0.0035472360, 0.0094482210, 0.0251657600, 0.0670301400, 0.1785378000"); - values("-0.005364700, -0.000809700, 0.0075720000, 0.0161353000, 0.0094018000, -0.045470200, -0.219897100", \ - "-0.005330100, -0.000791200, 0.0075746000, 0.0161451000, 0.0093926000, -0.045515100, -0.219925000", \ - "-0.005265200, -0.000743600, 0.0075863000, 0.0160486000, 0.0092480000, -0.045665100, -0.220121000", \ - "-0.005300700, -0.000805500, 0.0074650000, 0.0158790000, 0.0089801000, -0.046019000, -0.220486900", \ - "-0.005351100, -0.000879200, 0.0073470000, 0.0156883000, 0.0087072000, -0.046310500, -0.220799800", \ - "-0.005438400, -0.000964500, 0.0072375000, 0.0155403000, 0.0085264000, -0.046511700, -0.221005000", \ - "-0.005577500, -0.001034100, 0.0073472000, 0.0158864000, 0.0089137000, -0.046058300, -0.220453300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013317720, 0.0035472360, 0.0094482210, 0.0251657600, 0.0670301400, 0.1785378000"); - values("-0.006816100, -0.004024400, 0.0025082000, 0.0166896000, 0.0465773000, 0.1171631000, 0.2970906000", \ - "-0.006782500, -0.003998100, 0.0025148000, 0.0166617000, 0.0464818000, 0.1171487000, 0.2981241000", \ - "-0.006712600, -0.003942400, 0.0025474000, 0.0166411000, 0.0464491000, 0.1164590000, 0.2971767000", \ - "-0.006750700, -0.004007600, 0.0024230000, 0.0164244000, 0.0461425000, 0.1168243000, 0.2966117000", \ - "-0.006793100, -0.004061800, 0.0023473000, 0.0163132000, 0.0460070000, 0.1165339000, 0.2965898000", \ - "-0.006871800, -0.004135000, 0.0022882000, 0.0162590000, 0.0459102000, 0.1159213000, 0.2973502000", \ - "-0.007001600, -0.004178400, 0.0024238000, 0.0166456000, 0.0463206000, 0.1168597000, 0.2959758000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013317720, 0.0035472360, 0.0094482210, 0.0251657600, 0.0670301400, 0.1785378000"); - values("0.0014115000, 0.0070468000, 0.0177122000, 0.0298212000, 0.0261162000, -0.027081400, -0.200527700", \ - "0.0013774000, 0.0069880000, 0.0176046000, 0.0296182000, 0.0258305000, -0.027461100, -0.200936100", \ - "0.0013236000, 0.0069250000, 0.0175107000, 0.0294775000, 0.0256416000, -0.027647400, -0.201142500", \ - "0.0013253000, 0.0069186000, 0.0175092000, 0.0295000000, 0.0256518000, -0.027659200, -0.201160900", \ - "0.0013364000, 0.0069501000, 0.0175711000, 0.0296639000, 0.0258990000, -0.027401500, -0.200867400", \ - "0.0013340000, 0.0069806000, 0.0176608000, 0.0298278000, 0.0261460000, -0.027057900, -0.200541800", \ - "0.0013708000, 0.0070997000, 0.0179481000, 0.0303826000, 0.0270155000, -0.026003500, -0.199442600"); - } - related_pin : "SET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1785380000; - max_transition : 1.4985560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.4599957000, 0.4765002000, 0.5123019000, 0.5806305000, 0.6900161000, 0.8770491000, 1.2794694000", \ - "0.4645575000, 0.4812232000, 0.5170203000, 0.5854097000, 0.6947338000, 0.8818161000, 1.2843568000", \ - "0.4756043000, 0.4922323000, 0.5280579000, 0.5964362000, 0.7058008000, 0.8928473000, 1.2954543000", \ - "0.5008730000, 0.5173761000, 0.5531693000, 0.6215270000, 0.7308957000, 0.9178982000, 1.3204264000", \ - "0.5481474000, 0.5647277000, 0.6004683000, 0.6687753000, 0.7781589000, 0.9651987000, 1.3679490000", \ - "0.6172850000, 0.6337659000, 0.6695193000, 0.7378092000, 0.8471120000, 1.0341906000, 1.4369788000", \ - "0.7058375000, 0.7224470000, 0.7582029000, 0.8265312000, 0.9359323000, 1.1231086000, 1.5257270000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.2857217000, 0.2955489000, 0.3166672000, 0.3623690000, 0.4633193000, 0.7079184000, 1.3539818000", \ - "0.2905215000, 0.3001904000, 0.3213068000, 0.3670189000, 0.4679810000, 0.7127152000, 1.3591284000", \ - "0.3015930000, 0.3113544000, 0.3324747000, 0.3781739000, 0.4791214000, 0.7245639000, 1.3702296000", \ - "0.3271592000, 0.3370172000, 0.3581136000, 0.4038199000, 0.5047729000, 0.7493285000, 1.3983859000", \ - "0.3752261000, 0.3849731000, 0.4060981000, 0.4517859000, 0.5527308000, 0.7974887000, 1.4433980000", \ - "0.4437641000, 0.4535338000, 0.4746524000, 0.5203601000, 0.6213366000, 0.8658605000, 1.5127597000", \ - "0.5280139000, 0.5378324000, 0.5589739000, 0.6047152000, 0.7057254000, 0.9501591000, 1.5974526000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.0755538000, 0.0875596000, 0.1127104000, 0.1539867000, 0.2179917000, 0.3800007000, 0.8548887000", \ - "0.0757584000, 0.0872833000, 0.1126192000, 0.1539314000, 0.2182098000, 0.3794102000, 0.8533871000", \ - "0.0757425000, 0.0872697000, 0.1127046000, 0.1540958000, 0.2181105000, 0.3792270000, 0.8564605000", \ - "0.0755547000, 0.0875634000, 0.1127189000, 0.1541041000, 0.2182953000, 0.3803091000, 0.8552722000", \ - "0.0754121000, 0.0873596000, 0.1126450000, 0.1539058000, 0.2177238000, 0.3799344000, 0.8524809000", \ - "0.0753964000, 0.0873181000, 0.1127167000, 0.1540652000, 0.2182526000, 0.3794575000, 0.8514336000", \ - "0.0755168000, 0.0874505000, 0.1128148000, 0.1540683000, 0.2184009000, 0.3776452000, 0.8549843000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.0356763000, 0.0434135000, 0.0627722000, 0.1116646000, 0.2342627000, 0.5708221000, 1.4939755000", \ - "0.0358099000, 0.0435219000, 0.0628236000, 0.1117048000, 0.2334039000, 0.5716046000, 1.4983732000", \ - "0.0360635000, 0.0433476000, 0.0627828000, 0.1116820000, 0.2339481000, 0.5711432000, 1.4935401000", \ - "0.0356514000, 0.0434775000, 0.0627867000, 0.1116723000, 0.2333752000, 0.5703967000, 1.4985563000", \ - "0.0357545000, 0.0433669000, 0.0626040000, 0.1116354000, 0.2341467000, 0.5715697000, 1.4971658000", \ - "0.0361281000, 0.0434031000, 0.0628070000, 0.1116934000, 0.2333379000, 0.5695807000, 1.4982473000", \ - "0.0362790000, 0.0435162000, 0.0629201000, 0.1117841000, 0.2333470000, 0.5698842000, 1.4936847000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.2770823000, 0.2857072000, 0.3042413000, 0.3416572000, 0.4123024000, 0.5636779000, 0.9497406000", \ - "0.2817774000, 0.2904383000, 0.3089619000, 0.3462060000, 0.4165711000, 0.5678557000, 0.9542650000", \ - "0.2949161000, 0.3035447000, 0.3220634000, 0.3592174000, 0.4296656000, 0.5809241000, 0.9673976000", \ - "0.3277286000, 0.3363581000, 0.3548755000, 0.3919612000, 0.4623225000, 0.6135447000, 1.0001548000", \ - "0.4047742000, 0.4135227000, 0.4320133000, 0.4690688000, 0.5393396000, 0.6905185000, 1.0769187000", \ - "0.5688961000, 0.5775693000, 0.5961673000, 0.6331720000, 0.7033478000, 0.8544638000, 1.2407986000", \ - "0.8599675000, 0.8702539000, 0.8918928000, 0.9333002000, 1.0071719000, 1.1601842000, 1.5464852000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013317700, 0.0035472400, 0.0094482200, 0.0251658000, 0.0670301000, 0.1785380000"); - values("0.0324883000, 0.0389002000, 0.0531714000, 0.0834511000, 0.1476708000, 0.3235331000, 0.8304726000", \ - "0.0326521000, 0.0389017000, 0.0531048000, 0.0831884000, 0.1475301000, 0.3242766000, 0.8283336000", \ - "0.0324477000, 0.0389109000, 0.0530106000, 0.0829519000, 0.1469442000, 0.3232270000, 0.8304596000", \ - "0.0324416000, 0.0389084000, 0.0529681000, 0.0828009000, 0.1468755000, 0.3238596000, 0.8322620000", \ - "0.0326283000, 0.0389381000, 0.0527704000, 0.0825294000, 0.1469524000, 0.3242679000, 0.8373361000", \ - "0.0322972000, 0.0386020000, 0.0528029000, 0.0826343000, 0.1469933000, 0.3232976000, 0.8323280000", \ - "0.0408692000, 0.0475736000, 0.0623732000, 0.0916456000, 0.1533078000, 0.3267559000, 0.8305380000"); - } - related_pin : "SET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("SET_B") { - capacitance : 0.0033800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051285000, 0.0051618000, 0.0052383000, 0.0052434000, 0.0052552000, 0.0052823000, 0.0053448000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012463000, 0.0011314000, 0.0008664000, 0.0008679000, 0.0008712000, 0.0008790000, 0.0008968000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034240000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.131056600, -0.081626300, -0.099530000", \ - "-0.267156900, -0.216505900, -0.234409500", \ - "-0.373765000, -0.323113900, -0.336134800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1484844000, 0.1051576000, 0.1291647000", \ - "0.2821432000, 0.2363750000, 0.2603821000", \ - "0.3875306000, 0.3417624000, 0.3621074000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2071340000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfsbp_2") { - leakage_power () { - value : 0.0126493000; - when : "CLK&D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0105890000; - when : "!CLK&!D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0178765000; - when : "CLK&!D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0182378000; - when : "CLK&!D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0187442000; - when : "!CLK&D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0183926000; - when : "CLK&D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0119487000; - when : "!CLK&D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0107073000; - when : "CLK&!D&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0180267000; - when : "!CLK&!D&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0187539000; - when : "CLK&D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0180903000; - when : "!CLK&!D&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0180071000; - when : "!CLK&D&!SET_B&Q&!Q_N"; - } - area : 30.015200000; - cell_footprint : "sky130_fd_sc_hd__dfsbp"; - cell_leakage_power : 0.0160019600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017720000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0231749000, 0.0230940000, 0.0229077000, 0.0229508000, 0.0230505000, 0.0232804000, 0.0238103000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172395000, 0.0171652000, 0.0169939000, 0.0170220000, 0.0170869000, 0.0172366000, 0.0175816000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018520000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1950504000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.5235051000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073636000, 0.0072879000, 0.0071134000, 0.0072643000, 0.0076124000, 0.0084149000, 0.0102645000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000134100, -0.000308900, -0.000711700, -0.000571700, -0.000248700, 0.0004957000, 0.0022118000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0666973000, 0.2455221000, 0.4558900000", \ - "-0.042547500, 0.1252910000, 0.3307760000", \ - "-0.122300100, 0.0382142000, 0.2375957000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0508281000, 0.1564108000, 0.2361634000", \ - "-0.015692100, 0.0813457000, 0.1501120000", \ - "-0.042954400, 0.0504212000, 0.1155254000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.011427700, -0.168279900, -0.342026700", \ - "0.0941550000, -0.060255900, -0.240106100", \ - "0.1653626000, 0.0146139000, -0.166457000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.030959000, -0.127996700, -0.190659500", \ - "0.0294577000, -0.063918000, -0.125360000", \ - "0.0518372000, -0.040317700, -0.101759800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("-0.000484700, 0.0032524000, 0.0128973000, 0.0352528000, 0.0828704000, 0.2000387000, 0.5341460000", \ - "-0.000510400, 0.0032142000, 0.0128369000, 0.0351301000, 0.0826856000, 0.1999917000, 0.5332230000", \ - "-0.000565400, 0.0031381000, 0.0127133000, 0.0349090000, 0.0824546000, 0.2002780000, 0.5334005000", \ - "-0.000565700, 0.0031335000, 0.0127048000, 0.0349286000, 0.0825012000, 0.2006688000, 0.5313616000", \ - "-0.000553500, 0.0031759000, 0.0128001000, 0.0350785000, 0.0827917000, 0.2000660000, 0.5312889000", \ - "-0.000510800, 0.0032950000, 0.0130958000, 0.0356855000, 0.0835793000, 0.2009598000, 0.5346542000", \ - "-0.000436700, 0.0035076000, 0.0134882000, 0.0361088000, 0.0845623000, 0.2020548000, 0.5333271000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("-0.005501100, -0.000281900, 0.0105554000, 0.0225163000, 0.0094505000, -0.088020500, -0.412718800", \ - "-0.005466900, -0.000256000, 0.0105699000, 0.0225127000, 0.0094274000, -0.088058400, -0.412744600", \ - "-0.005385900, -0.000183500, 0.0106193000, 0.0225355000, 0.0093901000, -0.088162000, -0.412836400", \ - "-0.005416000, -0.000243000, 0.0104955000, 0.0223130000, 0.0090452000, -0.088546600, -0.413263600", \ - "-0.005455100, -0.000292600, 0.0104185000, 0.0221843000, 0.0089152000, -0.088715500, -0.413444100", \ - "-0.005527900, -0.000363400, 0.0103609000, 0.0221701000, 0.0088848000, -0.088687900, -0.413432400", \ - "-0.005638100, -0.000363600, 0.0106033000, 0.0228095000, 0.0095993000, -0.088190300, -0.412848200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("-0.007094200, -0.004312500, 0.0030374000, 0.0216652000, 0.0675618000, 0.1845352000, 0.5122889000", \ - "-0.007060700, -0.004272800, 0.0030613000, 0.0216802000, 0.0675619000, 0.1845486000, 0.5122758000", \ - "-0.006983800, -0.004224800, 0.0030527000, 0.0216113000, 0.0674935000, 0.1842715000, 0.5121572000", \ - "-0.007011700, -0.004271700, 0.0029562000, 0.0214020000, 0.0671452000, 0.1844656000, 0.5146399000", \ - "-0.007057500, -0.004343800, 0.0028534000, 0.0212111000, 0.0668539000, 0.1841557000, 0.5144813000", \ - "-0.007138400, -0.004432100, 0.0027354000, 0.0210573000, 0.0666766000, 0.1836747000, 0.5136660000", \ - "-0.007233100, -0.004391700, 0.0030753000, 0.0212978000, 0.0672892000, 0.1836704000, 0.5144297000"); - } - } - max_capacitance : 0.3112890000; - max_transition : 1.5036500000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.3933822000, 0.3978355000, 0.4077041000, 0.4279520000, 0.4719731000, 0.5859965000, 0.9146557000", \ - "0.3980572000, 0.4024895000, 0.4123653000, 0.4326370000, 0.4766435000, 0.5906080000, 0.9194083000", \ - "0.4092538000, 0.4137129000, 0.4235629000, 0.4438446000, 0.4878392000, 0.6018565000, 0.9317201000", \ - "0.4348456000, 0.4392929000, 0.4491644000, 0.4694262000, 0.5134358000, 0.6275530000, 0.9560491000", \ - "0.4828660000, 0.4873152000, 0.4971866000, 0.5174153000, 0.5614498000, 0.6755593000, 1.0038729000", \ - "0.5515125000, 0.5559548000, 0.5659064000, 0.5861186000, 0.6300935000, 0.7441894000, 1.0724281000", \ - "0.6360261000, 0.6405074000, 0.6503662000, 0.6706423000, 0.7146104000, 0.8286697000, 1.1579523000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.6808338000, 0.6886895000, 0.7057437000, 0.7394572000, 0.8210916000, 1.0565737000, 1.7377517000", \ - "0.6855566000, 0.6934997000, 0.7104766000, 0.7441925000, 0.8258316000, 1.0612818000, 1.7425039000", \ - "0.6966421000, 0.7046275000, 0.7217024000, 0.7554920000, 0.8370630000, 1.0727722000, 1.7538390000", \ - "0.7219915000, 0.7298858000, 0.7470078000, 0.7808313000, 0.8623832000, 1.0981497000, 1.7782895000", \ - "0.7694399000, 0.7774464000, 0.7944818000, 0.8282209000, 0.9097852000, 1.1437371000, 1.8259779000", \ - "0.8384154000, 0.8463260000, 0.8634359000, 0.8972399000, 0.9788141000, 1.2131753000, 1.8945325000", \ - "0.9265664000, 0.9345619000, 0.9516157000, 0.9853814000, 1.0668890000, 1.3008191000, 1.9836366000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0184301000, 0.0211154000, 0.0276938000, 0.0444739000, 0.0913345000, 0.2381876000, 0.6767421000", \ - "0.0184659000, 0.0211330000, 0.0276790000, 0.0446167000, 0.0913230000, 0.2379206000, 0.6816332000", \ - "0.0184820000, 0.0212801000, 0.0280521000, 0.0444471000, 0.0916680000, 0.2375188000, 0.6814349000", \ - "0.0184337000, 0.0210687000, 0.0276933000, 0.0445430000, 0.0915297000, 0.2375843000, 0.6764345000", \ - "0.0183989000, 0.0214001000, 0.0277063000, 0.0443497000, 0.0914938000, 0.2368331000, 0.6797676000", \ - "0.0183901000, 0.0211407000, 0.0281000000, 0.0444419000, 0.0915636000, 0.2384595000, 0.6829074000", \ - "0.0184517000, 0.0211176000, 0.0276485000, 0.0442426000, 0.0917056000, 0.2379735000, 0.6750502000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0348538000, 0.0394744000, 0.0503043000, 0.0807876000, 0.1873163000, 0.5208142000, 1.4916685000", \ - "0.0347509000, 0.0394678000, 0.0502458000, 0.0807174000, 0.1873362000, 0.5208908000, 1.4921474000", \ - "0.0347368000, 0.0394899000, 0.0504090000, 0.0810025000, 0.1868945000, 0.5215572000, 1.4905196000", \ - "0.0346820000, 0.0392715000, 0.0507952000, 0.0810773000, 0.1871523000, 0.5201762000, 1.4904487000", \ - "0.0346946000, 0.0392686000, 0.0507735000, 0.0809848000, 0.1871727000, 0.5199322000, 1.4904276000", \ - "0.0346594000, 0.0393207000, 0.0507796000, 0.0808974000, 0.1869759000, 0.5205825000, 1.4941114000", \ - "0.0347236000, 0.0394538000, 0.0508003000, 0.0810185000, 0.1870867000, 0.5193846000, 1.4942225000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.3747343000, 0.3798757000, 0.3921703000, 0.4219259000, 0.5029383000, 0.7366808000, 1.4210519000", \ - "0.3795791000, 0.3847727000, 0.3971378000, 0.4268080000, 0.5079557000, 0.7420309000, 1.4239623000", \ - "0.3922160000, 0.3974032000, 0.4097315000, 0.4394160000, 0.5205583000, 0.7544725000, 1.4409431000", \ - "0.4254745000, 0.4308178000, 0.4430250000, 0.4726997000, 0.5538611000, 0.7875714000, 1.4724022000", \ - "0.5029843000, 0.5082807000, 0.5205399000, 0.5502082000, 0.6313814000, 0.8648647000, 1.5487787000", \ - "0.6687316000, 0.6740316000, 0.6862776000, 0.7159468000, 0.7971364000, 1.0314160000, 1.7132282000", \ - "0.9796592000, 0.9851712000, 0.9978552000, 1.0277270000, 1.1088412000, 1.3427676000, 2.0260933000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0210155000, 0.0250404000, 0.0366712000, 0.0727388000, 0.1853627000, 0.5189212000, 1.4992769000", \ - "0.0211005000, 0.0252754000, 0.0367227000, 0.0728678000, 0.1850406000, 0.5190093000, 1.5036501000", \ - "0.0210659000, 0.0252377000, 0.0366736000, 0.0728732000, 0.1854442000, 0.5178273000, 1.5031453000", \ - "0.0211968000, 0.0251402000, 0.0366498000, 0.0727942000, 0.1852535000, 0.5172338000, 1.4920513000", \ - "0.0209573000, 0.0251840000, 0.0366511000, 0.0728277000, 0.1854752000, 0.5177938000, 1.4955265000", \ - "0.0211874000, 0.0251598000, 0.0366155000, 0.0728253000, 0.1855020000, 0.5182805000, 1.5027587000", \ - "0.0226282000, 0.0266095000, 0.0380504000, 0.0734738000, 0.1853195000, 0.5184406000, 1.4968459000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014674390, 0.0043067540, 0.0126398000, 0.0370962600, 0.1088730000, 0.3195289000"); - values("-0.005469100, -0.000223900, 0.0105004000, 0.0216502000, 0.0079690000, -0.090669100, -0.424271100", \ - "-0.005436500, -0.000181700, 0.0105364000, 0.0216923000, 0.0079390000, -0.090679200, -0.424342200", \ - "-0.005361900, -0.000145200, 0.0105142000, 0.0216022000, 0.0078660000, -0.090823500, -0.424529800", \ - "-0.005388300, -0.000183400, 0.0104397000, 0.0214157000, 0.0075996000, -0.091165800, -0.424814200", \ - "-0.005429900, -0.000240700, 0.0103174000, 0.0212229000, 0.0073346000, -0.091479200, -0.425183700", \ - "-0.005509700, -0.000333600, 0.0102071000, 0.0210799000, 0.0070617000, -0.091710100, -0.425408200", \ - "-0.005649400, -0.000424600, 0.0102255000, 0.0213143000, 0.0075319000, -0.091201300, -0.424855300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014674390, 0.0043067540, 0.0126398000, 0.0370962600, 0.1088730000, 0.3195289000"); - values("-0.007019500, -0.004091700, 0.0035816000, 0.0225308000, 0.0675393000, 0.1858401000, 0.5274809000", \ - "-0.006985500, -0.004062700, 0.0035988000, 0.0225184000, 0.0676030000, 0.1866311000, 0.5256110000", \ - "-0.006906500, -0.003988600, 0.0036450000, 0.0225469000, 0.0676405000, 0.1856760000, 0.5279777000", \ - "-0.006936300, -0.004052400, 0.0035109000, 0.0223216000, 0.0672022000, 0.1854702000, 0.5248166000", \ - "-0.006975500, -0.004097300, 0.0034329000, 0.0221908000, 0.0669430000, 0.1853449000, 0.5268493000", \ - "-0.007048900, -0.004169700, 0.0033944000, 0.0221793000, 0.0669733000, 0.1853368000, 0.5274741000", \ - "-0.007142100, -0.004118000, 0.0037808000, 0.0228177000, 0.0674569000, 0.1861322000, 0.5243171000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014674390, 0.0043067540, 0.0126398000, 0.0370962600, 0.1088730000, 0.3195289000"); - values("0.0010652000, 0.0071695000, 0.0200490000, 0.0352620000, 0.0244904000, -0.073425100, -0.406663300", \ - "0.0010340000, 0.0071341000, 0.0199872000, 0.0351250000, 0.0243068000, -0.073647200, -0.406887200", \ - "0.0009830000, 0.0070559000, 0.0198530000, 0.0349366000, 0.0240481000, -0.073990300, -0.407247300", \ - "0.0009800000, 0.0070538000, 0.0198475000, 0.0349090000, 0.0240306000, -0.074008500, -0.407274800", \ - "0.0009917000, 0.0070952000, 0.0199273000, 0.0351019000, 0.0243193000, -0.073676500, -0.406941900", \ - "0.0010367000, 0.0072195000, 0.0202547000, 0.0357155000, 0.0252560000, -0.072563300, -0.405806500", \ - "0.0010711000, 0.0073038000, 0.0204670000, 0.0360743000, 0.0259352000, -0.071642400, -0.404868900"); - } - related_pin : "SET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.3195290000; - max_transition : 1.5023970000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.5438694000, 0.5578763000, 0.5905484000, 0.6585216000, 0.7780779000, 0.9716022000, 1.3726251000", \ - "0.5486649000, 0.5627609000, 0.5953316000, 0.6632918000, 0.7828456000, 0.9762953000, 1.3773709000", \ - "0.5596740000, 0.5737975000, 0.6065858000, 0.6743817000, 0.7939353000, 0.9873855000, 1.3881838000", \ - "0.5851078000, 0.5991783000, 0.6317889000, 0.6997250000, 0.8192730000, 1.0127671000, 1.4138126000", \ - "0.6325898000, 0.6467730000, 0.6792606000, 0.7471930000, 0.8667532000, 1.0602723000, 1.4613523000", \ - "0.7013594000, 0.7154760000, 0.7481966000, 0.8161041000, 0.9356391000, 1.1291088000, 1.5301125000", \ - "0.7897414000, 0.8038919000, 0.8364584000, 0.9044584000, 1.0240482000, 1.2176840000, 1.6186351000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.3089188000, 0.3176469000, 0.3379077000, 0.3818189000, 0.4786935000, 0.7166961000, 1.4024799000", \ - "0.3135780000, 0.3223272000, 0.3425720000, 0.3864833000, 0.4833533000, 0.7216078000, 1.4054828000", \ - "0.3247302000, 0.3335487000, 0.3538448000, 0.3976789000, 0.4945334000, 0.7331045000, 1.4142223000", \ - "0.3503816000, 0.3591097000, 0.3793709000, 0.4232801000, 0.5201530000, 0.7584580000, 1.4415986000", \ - "0.3983443000, 0.4071838000, 0.4274175000, 0.4713021000, 0.5681625000, 0.8064789000, 1.4893902000", \ - "0.4668613000, 0.4757977000, 0.4961587000, 0.5399648000, 0.6368017000, 0.8754006000, 1.5571452000", \ - "0.5512989000, 0.5602588000, 0.5805239000, 0.6244662000, 0.7213766000, 0.9600100000, 1.6422775000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.0811856000, 0.0905232000, 0.1130463000, 0.1576296000, 0.2216182000, 0.3602329000, 0.7870289000", \ - "0.0814516000, 0.0902204000, 0.1130157000, 0.1576674000, 0.2217887000, 0.3608109000, 0.7869710000", \ - "0.0811061000, 0.0904722000, 0.1130551000, 0.1577591000, 0.2219082000, 0.3607986000, 0.7887923000", \ - "0.0814701000, 0.0903125000, 0.1128119000, 0.1577959000, 0.2217491000, 0.3589690000, 0.7883575000", \ - "0.0808597000, 0.0902091000, 0.1131601000, 0.1577339000, 0.2217078000, 0.3586035000, 0.7869086000", \ - "0.0808500000, 0.0903809000, 0.1126602000, 0.1575997000, 0.2217356000, 0.3606382000, 0.7886747000", \ - "0.0810260000, 0.0906110000, 0.1133479000, 0.1578437000, 0.2216881000, 0.3584223000, 0.7886702000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.0347659000, 0.0414292000, 0.0574272000, 0.0984751000, 0.2043309000, 0.5218038000, 1.4984182000", \ - "0.0348178000, 0.0414975000, 0.0573998000, 0.0984154000, 0.2043523000, 0.5227393000, 1.4953765000", \ - "0.0348169000, 0.0413312000, 0.0574684000, 0.0982237000, 0.2043490000, 0.5227281000, 1.5008311000", \ - "0.0347681000, 0.0414305000, 0.0574265000, 0.0984638000, 0.2043959000, 0.5212804000, 1.5008028000", \ - "0.0347161000, 0.0412743000, 0.0575174000, 0.0983960000, 0.2050465000, 0.5233771000, 1.5023967000", \ - "0.0349920000, 0.0414474000, 0.0574222000, 0.0983008000, 0.2042077000, 0.5218723000, 1.4980639000", \ - "0.0349843000, 0.0416014000, 0.0575148000, 0.0983549000, 0.2044382000, 0.5208713000, 1.4960374000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.2934971000, 0.3010244000, 0.3182646000, 0.3535854000, 0.4217937000, 0.5603069000, 0.9234535000", \ - "0.2983694000, 0.3059095000, 0.3231275000, 0.3584472000, 0.4264147000, 0.5648534000, 0.9279058000", \ - "0.3111401000, 0.3187259000, 0.3358468000, 0.3711930000, 0.4389735000, 0.5773578000, 0.9402407000", \ - "0.3444356000, 0.3519660000, 0.3692218000, 0.4044229000, 0.4721321000, 0.6105018000, 0.9736575000", \ - "0.4219771000, 0.4295152000, 0.4467105000, 0.4819984000, 0.5496121000, 0.6879269000, 1.0517450000", \ - "0.5879541000, 0.5953831000, 0.6128618000, 0.6476951000, 0.7152421000, 0.8534967000, 1.2164091000", \ - "0.8894431000, 0.8980811000, 0.9180621000, 0.9582529000, 1.0310388000, 1.1723434000, 1.5356318000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014674400, 0.0043067500, 0.0126398000, 0.0370963000, 0.1088730000, 0.3195290000"); - values("0.0323085000, 0.0374815000, 0.0493765000, 0.0752876000, 0.1286156000, 0.2732698000, 0.7413712000", \ - "0.0322676000, 0.0374301000, 0.0493122000, 0.0750766000, 0.1285007000, 0.2737417000, 0.7464739000", \ - "0.0321140000, 0.0371499000, 0.0489434000, 0.0751352000, 0.1284138000, 0.2732099000, 0.7406054000", \ - "0.0319150000, 0.0374852000, 0.0493579000, 0.0749415000, 0.1279695000, 0.2728499000, 0.7412638000", \ - "0.0321767000, 0.0373966000, 0.0493113000, 0.0748237000, 0.1280700000, 0.2728161000, 0.7429482000", \ - "0.0318148000, 0.0371542000, 0.0491004000, 0.0747689000, 0.1276882000, 0.2727171000, 0.7418636000", \ - "0.0403265000, 0.0460208000, 0.0592118000, 0.0856873000, 0.1362141000, 0.2759649000, 0.7483257000"); - } - related_pin : "SET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("SET_B") { - capacitance : 0.0034010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051146000, 0.0051522000, 0.0052387000, 0.0052400000, 0.0052429000, 0.0052497000, 0.0052653000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012802000, 0.0012374000, 0.0011384000, 0.0011269000, 0.0011002000, 0.0010388000, 0.0008972000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034370000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.128615200, -0.077964200, -0.093426400", \ - "-0.265936200, -0.212843800, -0.229526700", \ - "-0.372544300, -0.320672500, -0.332472600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1484844000, 0.1051576000, 0.1303854000", \ - "0.2821432000, 0.2363750000, 0.2603821000", \ - "0.3875306000, 0.3417624000, 0.3608867000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2598625000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfstp_1") { - leakage_power () { - value : 0.0132377000; - when : "CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0111782000; - when : "!CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0085129000; - when : "CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0088743000; - when : "CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0093814000; - when : "!CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0090289000; - when : "CLK&D&!SET_B&Q"; - } - leakage_power () { - value : 0.0125383000; - when : "!CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0112962000; - when : "CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0086638000; - when : "!CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0093902000; - when : "CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0087275000; - when : "!CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0086434000; - when : "!CLK&D&!SET_B&Q"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__dfstp"; - cell_leakage_power : 0.0099560720; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017760000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0232874000, 0.0232031000, 0.0230086000, 0.0230599000, 0.0231782000, 0.0234508000, 0.0240793000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172651000, 0.0171931000, 0.0170272000, 0.0170437000, 0.0170817000, 0.0171697000, 0.0173723000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1917548000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3268717000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073654000, 0.0072897000, 0.0071151000, 0.0072662000, 0.0076142000, 0.0084168000, 0.0102668000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-8.7227731e-05, -0.000282000, -0.000730900, -0.000590800, -0.000267700, 0.0004769000, 0.0021934000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0642559000, 0.2406393000, 0.4510072000", \ - "-0.044988900, 0.1228496000, 0.3258932000", \ - "-0.124741500, 0.0345521000, 0.2339336000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0520488000, 0.1576315000, 0.2373841000", \ - "-0.015692100, 0.0813457000, 0.1501120000", \ - "-0.042954400, 0.0504212000, 0.1155254000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.010207000, -0.165838500, -0.334702500", \ - "0.0965964000, -0.056593700, -0.236444000", \ - "0.1690247000, 0.0194967000, -0.161574200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.130438200, -0.195542300", \ - "0.0282370000, -0.065138700, -0.126580700", \ - "0.0506165000, -0.041538400, -0.104201200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0539824000, 0.0556098000, 0.0595558000, 0.0689472000, 0.0932006000, 0.1559491000, 0.3242016000", \ - "0.0537387000, 0.0553762000, 0.0593107000, 0.0687216000, 0.0929182000, 0.1563345000, 0.3235540000", \ - "0.0533628000, 0.0550022000, 0.0589257000, 0.0683893000, 0.0923000000, 0.1552907000, 0.3233905000", \ - "0.0533069000, 0.0549440000, 0.0588589000, 0.0682703000, 0.0922483000, 0.1551841000, 0.3221753000", \ - "0.0537780000, 0.0554320000, 0.0593318000, 0.0687223000, 0.0926999000, 0.1565909000, 0.3228509000", \ - "0.0537722000, 0.0553958000, 0.0593270000, 0.0687235000, 0.0927932000, 0.1556991000, 0.3227492000", \ - "0.0549835000, 0.0563408000, 0.0598838000, 0.0690969000, 0.0936927000, 0.1569053000, 0.3247273000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0242767000, 0.0232424000, 0.0204310000, 0.0118600000, -0.012107100, -0.075911700, -0.244298800", \ - "0.0242457000, 0.0232091000, 0.0203718000, 0.0118221000, -0.012146100, -0.075958300, -0.244323900", \ - "0.0242553000, 0.0232237000, 0.0203942000, 0.0118320000, -0.012134100, -0.075935700, -0.244336500", \ - "0.0238203000, 0.0227947000, 0.0199659000, 0.0114081000, -0.012560900, -0.076359000, -0.244760000", \ - "0.0235309000, 0.0225012000, 0.0196890000, 0.0111266000, -0.012839800, -0.076654600, -0.245022700", \ - "0.0236003000, 0.0225572000, 0.0197219000, 0.0111695000, -0.012794100, -0.076609100, -0.245006700", \ - "0.0256415000, 0.0244081000, 0.0210526000, 0.0120432000, -0.012111100, -0.076061600, -0.244446300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0243577000, 0.0259624000, 0.0302741000, 0.0405421000, 0.0651145000, 0.1279971000, 0.2960108000", \ - "0.0243558000, 0.0259959000, 0.0302665000, 0.0405388000, 0.0652136000, 0.1280657000, 0.2956460000", \ - "0.0242012000, 0.0258356000, 0.0300811000, 0.0403928000, 0.0649896000, 0.1285049000, 0.2954306000", \ - "0.0238597000, 0.0254641000, 0.0297711000, 0.0400112000, 0.0646971000, 0.1275611000, 0.2952407000", \ - "0.0234985000, 0.0251206000, 0.0293752000, 0.0396562000, 0.0644558000, 0.1272163000, 0.2952615000", \ - "0.0232904000, 0.0249112000, 0.0292009000, 0.0394525000, 0.0641169000, 0.1269758000, 0.2945420000", \ - "0.0265701000, 0.0279158000, 0.0314608000, 0.0406705000, 0.0646751000, 0.1274180000, 0.2940128000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5053390000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3205806000, 0.3260139000, 0.3374271000, 0.3610056000, 0.4140508000, 0.5488554000, 0.9031145000", \ - "0.3252190000, 0.3306410000, 0.3420113000, 0.3656414000, 0.4187105000, 0.5531316000, 0.9065623000", \ - "0.3364000000, 0.3418019000, 0.3531689000, 0.3767932000, 0.4298646000, 0.5642479000, 0.9172703000", \ - "0.3620546000, 0.3674893000, 0.3788806000, 0.4024633000, 0.4555086000, 0.5897138000, 0.9435008000", \ - "0.4100392000, 0.4154410000, 0.4267980000, 0.4504388000, 0.5034891000, 0.6378230000, 0.9912174000", \ - "0.4786396000, 0.4840577000, 0.4954219000, 0.5190611000, 0.5721408000, 0.7065581000, 1.0598695000", \ - "0.5629012000, 0.5683209000, 0.5796971000, 0.6032856000, 0.6563791000, 0.7907307000, 1.1441933000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4593320000, 0.4676287000, 0.4846373000, 0.5216755000, 0.6150914000, 0.8596938000, 1.5037713000", \ - "0.4640982000, 0.4723930000, 0.4892892000, 0.5264076000, 0.6197741000, 0.8644291000, 1.5085977000", \ - "0.4750744000, 0.4834026000, 0.5002925000, 0.5374015000, 0.6313590000, 0.8750576000, 1.5184991000", \ - "0.5000088000, 0.5082834000, 0.5252947000, 0.5622764000, 0.6558195000, 0.9003243000, 1.5443362000", \ - "0.5473708000, 0.5557716000, 0.5726555000, 0.6097141000, 0.7035386000, 0.9473405000, 1.5918359000", \ - "0.6164346000, 0.6247037000, 0.6417227000, 0.6787338000, 0.7720781000, 1.0168353000, 1.6611075000", \ - "0.7061959000, 0.7146088000, 0.7315004000, 0.7685605000, 0.8623794000, 1.1063159000, 1.7493716000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0179382000, 0.0220275000, 0.0314915000, 0.0552886000, 0.1193376000, 0.2964892000, 0.7650560000", \ - "0.0176687000, 0.0219604000, 0.0315562000, 0.0552213000, 0.1194744000, 0.2963542000, 0.7684670000", \ - "0.0176715000, 0.0219627000, 0.0315403000, 0.0552586000, 0.1194646000, 0.2964927000, 0.7700125000", \ - "0.0177061000, 0.0218118000, 0.0315460000, 0.0554199000, 0.1193899000, 0.2984558000, 0.7746160000", \ - "0.0177072000, 0.0220126000, 0.0314901000, 0.0552981000, 0.1194482000, 0.2961811000, 0.7674588000", \ - "0.0176632000, 0.0220261000, 0.0315744000, 0.0549172000, 0.1198710000, 0.2971095000, 0.7665488000", \ - "0.0179653000, 0.0219900000, 0.0313149000, 0.0554320000, 0.1195163000, 0.2963006000, 0.7626230000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0309407000, 0.0363109000, 0.0517074000, 0.0969500000, 0.2275347000, 0.5750482000, 1.4959300000", \ - "0.0305842000, 0.0364581000, 0.0516029000, 0.0967728000, 0.2281433000, 0.5739050000, 1.4965666000", \ - "0.0305487000, 0.0363371000, 0.0516338000, 0.0966612000, 0.2276956000, 0.5753160000, 1.4951763000", \ - "0.0310595000, 0.0363269000, 0.0516291000, 0.0967310000, 0.2283064000, 0.5742352000, 1.4949295000", \ - "0.0305236000, 0.0363790000, 0.0516510000, 0.0969156000, 0.2276615000, 0.5753209000, 1.4962842000", \ - "0.0310594000, 0.0367780000, 0.0516689000, 0.0966530000, 0.2277468000, 0.5746149000, 1.4984531000", \ - "0.0305585000, 0.0364039000, 0.0516714000, 0.0969244000, 0.2277041000, 0.5742100000, 1.4989154000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3120374000, 0.3185968000, 0.3336050000, 0.3697329000, 0.4628333000, 0.7066601000, 1.3537745000", \ - "0.3166351000, 0.3231850000, 0.3382059000, 0.3743958000, 0.4675056000, 0.7123689000, 1.3552146000", \ - "0.3296823000, 0.3362350000, 0.3511940000, 0.3873753000, 0.4803981000, 0.7243533000, 1.3680229000", \ - "0.3623515000, 0.3688936000, 0.3839172000, 0.4200559000, 0.5131769000, 0.7577744000, 1.4011426000", \ - "0.4381918000, 0.4447354000, 0.4597000000, 0.4959049000, 0.5889398000, 0.8328419000, 1.4796407000", \ - "0.6010942000, 0.6076186000, 0.6226007000, 0.6588295000, 0.7517357000, 0.9960196000, 1.6398604000", \ - "0.8872225000, 0.8938859000, 0.9090711000, 0.9454166000, 1.0385339000, 1.2822131000, 1.9277580000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0220898000, 0.0284290000, 0.0458262000, 0.0945578000, 0.2259214000, 0.5755764000, 1.5029805000", \ - "0.0220789000, 0.0284151000, 0.0457524000, 0.0945877000, 0.2258230000, 0.5766276000, 1.5039351000", \ - "0.0220373000, 0.0283879000, 0.0457337000, 0.0944702000, 0.2260386000, 0.5759497000, 1.5053391000", \ - "0.0219267000, 0.0283442000, 0.0457894000, 0.0945810000, 0.2258483000, 0.5755924000, 1.5005019000", \ - "0.0219230000, 0.0283187000, 0.0457878000, 0.0943555000, 0.2260241000, 0.5759168000, 1.4947295000", \ - "0.0219222000, 0.0282900000, 0.0457462000, 0.0944412000, 0.2264859000, 0.5746009000, 1.4980671000", \ - "0.0230372000, 0.0292681000, 0.0463250000, 0.0948709000, 0.2268814000, 0.5741250000, 1.5020211000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SET_B") { - capacitance : 0.0034020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051299000, 0.0051636000, 0.0052414000, 0.0052464000, 0.0052577000, 0.0052836000, 0.0053437000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012188000, 0.0011928000, 0.0011329000, 0.0011236000, 0.0011023000, 0.0010531000, 0.0009400000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034390000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.131056600, -0.084067700, -0.104412800", \ - "-0.268377600, -0.218947300, -0.239292300", \ - "-0.374985700, -0.325555300, -0.341017600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1484844000, 0.1051576000, 0.1303854000", \ - "0.2833639000, 0.2375957000, 0.2616029000", \ - "0.3887513000, 0.3429831000, 0.3633281000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2148236000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfstp_2") { - leakage_power () { - value : 0.0120992000; - when : "CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0100389000; - when : "!CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0099227000; - when : "CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0102841000; - when : "CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0107911000; - when : "!CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0104389000; - when : "CLK&D&!SET_B&Q"; - } - leakage_power () { - value : 0.0113986000; - when : "!CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0101572000; - when : "CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0100733000; - when : "!CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0108003000; - when : "CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0101376000; - when : "!CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0100532000; - when : "!CLK&D&!SET_B&Q"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__dfstp"; - cell_leakage_power : 0.0105162700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017930000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0234358000, 0.0233531000, 0.0231625000, 0.0232085000, 0.0233144000, 0.0235586000, 0.0241217000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173823000, 0.0173101000, 0.0171437000, 0.0171752000, 0.0172477000, 0.0174150000, 0.0178006000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018760000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1961489000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3565315000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073562000, 0.0072832000, 0.0071150000, 0.0072679000, 0.0076203000, 0.0084329000, 0.0103059000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000124700, -0.000308900, -0.000733600, -0.000592500, -0.000267400, 0.0004822000, 0.0022101000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0666973000, 0.2443014000, 0.4546693000", \ - "-0.043768200, 0.1240703000, 0.3283346000", \ - "-0.125962200, 0.0345521000, 0.2351543000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0520488000, 0.1576315000, 0.2386048000", \ - "-0.015692100, 0.0813457000, 0.1501120000", \ - "-0.045395800, 0.0492005000, 0.1143047000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.005324200, -0.156072900, -0.318833300", \ - "0.1039206000, -0.048048800, -0.223016300", \ - "0.1763490000, 0.0280417000, -0.148146500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.029738300, -0.126776000, -0.189438800", \ - "0.0318991000, -0.061476600, -0.124139300", \ - "0.0542786000, -0.037876300, -0.099318400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("0.0600722000, 0.0619209000, 0.0672085000, 0.0811812000, 0.1199086000, 0.2331948000, 0.5623304000", \ - "0.0596831000, 0.0615436000, 0.0667785000, 0.0807750000, 0.1194241000, 0.2327847000, 0.5621371000", \ - "0.0593171000, 0.0611574000, 0.0663783000, 0.0803143000, 0.1191189000, 0.2322501000, 0.5618529000", \ - "0.0594674000, 0.0613074000, 0.0665313000, 0.0804713000, 0.1191194000, 0.2313217000, 0.5606111000", \ - "0.0597990000, 0.0616391000, 0.0668603000, 0.0808113000, 0.1197739000, 0.2314769000, 0.5601247000", \ - "0.0598351000, 0.0616777000, 0.0668897000, 0.0807989000, 0.1195111000, 0.2316005000, 0.5625592000", \ - "0.0620522000, 0.0636835000, 0.0683841000, 0.0817720000, 0.1211944000, 0.2325352000, 0.5614315000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("0.0301161000, 0.0287396000, 0.0249888000, 0.0131732000, -0.024771700, -0.138001400, -0.469584000", \ - "0.0301050000, 0.0287213000, 0.0249630000, 0.0131838000, -0.024792300, -0.138005100, -0.469606900", \ - "0.0300878000, 0.0286836000, 0.0249071000, 0.0131352000, -0.024828100, -0.138057400, -0.469623600", \ - "0.0296484000, 0.0282672000, 0.0244844000, 0.0127098000, -0.025258700, -0.138472500, -0.470054600", \ - "0.0293391000, 0.0279403000, 0.0241866000, 0.0124182000, -0.025555200, -0.138770200, -0.470369300", \ - "0.0292275000, 0.0278643000, 0.0240732000, 0.0123187000, -0.025638200, -0.138850500, -0.470454500", \ - "0.0318578000, 0.0304202000, 0.0261683000, 0.0133623000, -0.025080000, -0.138500500, -0.470096800"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014610630, 0.0042694120, 0.0124757600, 0.0364557500, 0.1065283000, 0.3112892000"); - values("0.0307645000, 0.0324699000, 0.0377242000, 0.0524240000, 0.0921383000, 0.2044172000, 0.5314663000", \ - "0.0307570000, 0.0324665000, 0.0377357000, 0.0524453000, 0.0921334000, 0.2053296000, 0.5347665000", \ - "0.0306073000, 0.0323072000, 0.0375185000, 0.0522513000, 0.0921247000, 0.2042337000, 0.5340674000", \ - "0.0302206000, 0.0319717000, 0.0372001000, 0.0519120000, 0.0916753000, 0.2044722000, 0.5341346000", \ - "0.0298344000, 0.0315809000, 0.0367694000, 0.0515499000, 0.0912980000, 0.2033213000, 0.5340969000", \ - "0.0295243000, 0.0312639000, 0.0364878000, 0.0511719000, 0.0909711000, 0.2030188000, 0.5336223000", \ - "0.0331754000, 0.0347459000, 0.0393766000, 0.0528241000, 0.0914200000, 0.2035425000, 0.5310531000"); - } - } - max_capacitance : 0.3112890000; - max_transition : 1.5034140000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.3313717000, 0.3354600000, 0.3447309000, 0.3640655000, 0.4070862000, 0.5206822000, 0.8489545000", \ - "0.3360316000, 0.3401235000, 0.3493851000, 0.3687305000, 0.4117633000, 0.5252304000, 0.8552052000", \ - "0.3471954000, 0.3512992000, 0.3605439000, 0.3798925000, 0.4229402000, 0.5365371000, 0.8651256000", \ - "0.3728473000, 0.3769643000, 0.3861877000, 0.4055332000, 0.4485955000, 0.5621738000, 0.8901077000", \ - "0.4211551000, 0.4252463000, 0.4345112000, 0.4538541000, 0.4968916000, 0.6103418000, 0.9402840000", \ - "0.4903756000, 0.4944678000, 0.5037348000, 0.5230809000, 0.5661199000, 0.6797263000, 1.0081777000", \ - "0.5755733000, 0.5796580000, 0.5889308000, 0.6082729000, 0.6513026000, 0.7649325000, 1.0933204000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.4806466000, 0.4871936000, 0.5016070000, 0.5326479000, 0.6137829000, 0.8484091000, 1.5299739000", \ - "0.4854916000, 0.4920430000, 0.5064488000, 0.5375071000, 0.6185313000, 0.8528893000, 1.5363216000", \ - "0.4964604000, 0.5030097000, 0.5174103000, 0.5484670000, 0.6294834000, 0.8641394000, 1.5457943000", \ - "0.5214898000, 0.5281496000, 0.5425058000, 0.5734627000, 0.6547854000, 0.8887093000, 1.5742843000", \ - "0.5691015000, 0.5757366000, 0.5900680000, 0.6211252000, 0.7022705000, 0.9364802000, 1.6199786000", \ - "0.6386289000, 0.6452552000, 0.6596698000, 0.6905914000, 0.7719536000, 1.0060000000, 1.6894388000", \ - "0.7290930000, 0.7356518000, 0.7500633000, 0.7811343000, 0.8621720000, 1.0967149000, 1.7795531000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0162528000, 0.0187835000, 0.0254020000, 0.0422814000, 0.0899093000, 0.2374522000, 0.6850271000", \ - "0.0163797000, 0.0187918000, 0.0255546000, 0.0423518000, 0.0898235000, 0.2375093000, 0.6764913000", \ - "0.0164268000, 0.0187340000, 0.0256088000, 0.0423668000, 0.0898954000, 0.2371721000, 0.6828656000", \ - "0.0161629000, 0.0187965000, 0.0253812000, 0.0424056000, 0.0900060000, 0.2374597000, 0.6841462000", \ - "0.0163432000, 0.0187464000, 0.0255047000, 0.0423365000, 0.0898150000, 0.2372503000, 0.6766835000", \ - "0.0163807000, 0.0188041000, 0.0255440000, 0.0419899000, 0.0899561000, 0.2375844000, 0.6833507000", \ - "0.0162659000, 0.0188383000, 0.0255096000, 0.0424547000, 0.0896279000, 0.2376065000, 0.6737224000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0276240000, 0.0319094000, 0.0424851000, 0.0754458000, 0.1860291000, 0.5173653000, 1.4968061000", \ - "0.0276645000, 0.0316040000, 0.0423913000, 0.0753639000, 0.1857900000, 0.5175180000, 1.4960390000", \ - "0.0277096000, 0.0316476000, 0.0424149000, 0.0753633000, 0.1856016000, 0.5173938000, 1.4965001000", \ - "0.0275151000, 0.0318242000, 0.0425471000, 0.0753474000, 0.1862248000, 0.5179916000, 1.4978147000", \ - "0.0275939000, 0.0317006000, 0.0425353000, 0.0751638000, 0.1857163000, 0.5173839000, 1.4955797000", \ - "0.0275816000, 0.0318594000, 0.0424966000, 0.0753544000, 0.1859170000, 0.5176954000, 1.4948774000", \ - "0.0277280000, 0.0316092000, 0.0424286000, 0.0753448000, 0.1855750000, 0.5179911000, 1.4941721000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.3148366000, 0.3196613000, 0.3314483000, 0.3605709000, 0.4415176000, 0.6757294000, 1.3586036000", \ - "0.3195025000, 0.3242722000, 0.3359878000, 0.3651898000, 0.4460386000, 0.6802150000, 1.3628028000", \ - "0.3323510000, 0.3371728000, 0.3488539000, 0.3780208000, 0.4590651000, 0.6934859000, 1.3764661000", \ - "0.3652767000, 0.3700523000, 0.3817408000, 0.4109325000, 0.4920159000, 0.7257134000, 1.4087144000", \ - "0.4420241000, 0.4467926000, 0.4584739000, 0.4876601000, 0.5687472000, 0.8023945000, 1.4864229000", \ - "0.6046628000, 0.6094752000, 0.6211349000, 0.6503459000, 0.7312607000, 0.9653375000, 1.6474199000", \ - "0.8939784000, 0.8989637000, 0.9108777000, 0.9401659000, 1.0212855000, 1.2551268000, 1.9391477000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014610600, 0.0042694100, 0.0124758000, 0.0364557000, 0.1065280000, 0.3112890000"); - values("0.0185019000, 0.0225088000, 0.0345124000, 0.0715218000, 0.1851031000, 0.5193018000, 1.5033990000", \ - "0.0184572000, 0.0224639000, 0.0344834000, 0.0713898000, 0.1846885000, 0.5185468000, 1.5034139000", \ - "0.0184553000, 0.0224640000, 0.0343652000, 0.0714664000, 0.1849176000, 0.5200989000, 1.5031612000", \ - "0.0184192000, 0.0224221000, 0.0344302000, 0.0714417000, 0.1846353000, 0.5194750000, 1.5017296000", \ - "0.0184019000, 0.0224072000, 0.0344081000, 0.0714616000, 0.1847523000, 0.5191152000, 1.5008216000", \ - "0.0183140000, 0.0224936000, 0.0343587000, 0.0715118000, 0.1847813000, 0.5181185000, 1.5021405000", \ - "0.0197678000, 0.0236421000, 0.0352582000, 0.0718639000, 0.1846305000, 0.5184929000, 1.5016998000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SET_B") { - capacitance : 0.0033620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051270000, 0.0051586000, 0.0052315000, 0.0052321000, 0.0052334000, 0.0052365000, 0.0052438000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012622000, 0.0012189000, 0.0011192000, 0.0011099000, 0.0010885000, 0.0010394000, 0.0009261000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034200000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.129835900, -0.081626300, -0.100750600", \ - "-0.268377600, -0.217726600, -0.236850900", \ - "-0.376206400, -0.326776000, -0.342238300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1497051000, 0.1063783000, 0.1316061000", \ - "0.2845846000, 0.2388164000, 0.2628236000", \ - "0.3911927000, 0.3454245000, 0.3657695000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2258087000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfstp_4") { - leakage_power () { - value : 0.0137195000; - when : "CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0116592000; - when : "!CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0097567000; - when : "CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0101180000; - when : "CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0106245000; - when : "!CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0102729000; - when : "CLK&D&!SET_B&Q"; - } - leakage_power () { - value : 0.0130189000; - when : "!CLK&D&SET_B&!Q"; - } - leakage_power () { - value : 0.0117775000; - when : "CLK&!D&SET_B&!Q"; - } - leakage_power () { - value : 0.0099070000; - when : "!CLK&!D&!SET_B&Q"; - } - leakage_power () { - value : 0.0106342000; - when : "CLK&D&SET_B&Q"; - } - leakage_power () { - value : 0.0099706000; - when : "!CLK&!D&SET_B&Q"; - } - leakage_power () { - value : 0.0098873000; - when : "!CLK&D&!SET_B&Q"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__dfstp"; - cell_leakage_power : 0.0109455200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017760000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0232686000, 0.0231860000, 0.0229957000, 0.0230470000, 0.0231652000, 0.0234380000, 0.0240668000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172554000, 0.0171832000, 0.0170168000, 0.0170337000, 0.0170725000, 0.0171621000, 0.0173687000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1928533000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3796002000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0073635000, 0.0072883000, 0.0071149000, 0.0072660000, 0.0076142000, 0.0084169000, 0.0102673000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000121800, -0.000306100, -0.000731100, -0.000592000, -0.000271500, 0.0004675000, 0.0021711000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024880000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0642559000, 0.2418600000, 0.4510072000", \ - "-0.044988900, 0.1228496000, 0.3271139000", \ - "-0.124741500, 0.0357728000, 0.2339336000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0520488000, 0.1588522000, 0.2386048000", \ - "-0.014471400, 0.0825664000, 0.1513327000", \ - "-0.042954400, 0.0516419000, 0.1167461000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.006544900, -0.158514300, -0.322495400", \ - "0.1014792000, -0.050490200, -0.226678400", \ - "0.1726869000, 0.0243796000, -0.153029300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.032179700, -0.130438200, -0.194321600", \ - "0.0282370000, -0.065138700, -0.127801400", \ - "0.0506165000, -0.041538400, -0.102980500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016399840, 0.0053790920, 0.0176432500, 0.0578692800, 0.1898093000, 0.6225684000"); - values("0.0771726000, 0.0791071000, 0.0852948000, 0.1057173000, 0.1706499000, 0.3821558000, 1.0761255000", \ - "0.0767719000, 0.0786339000, 0.0848185000, 0.1051668000, 0.1704811000, 0.3837635000, 1.0805878000", \ - "0.0763454000, 0.0781876000, 0.0845166000, 0.1049720000, 0.1701005000, 0.3831408000, 1.0793313000", \ - "0.0764802000, 0.0783781000, 0.0846643000, 0.1051368000, 0.1702346000, 0.3816382000, 1.0768124000", \ - "0.0768287000, 0.0786569000, 0.0849341000, 0.1052710000, 0.1704958000, 0.3819774000, 1.0698654000", \ - "0.0767680000, 0.0787412000, 0.0849465000, 0.1053341000, 0.1704507000, 0.3818011000, 1.0766770000", \ - "0.0781065000, 0.0799810000, 0.0859369000, 0.1059022000, 0.1718116000, 0.3822543000, 1.0767176000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016399840, 0.0053790920, 0.0176432500, 0.0578692800, 0.1898093000, 0.6225684000"); - values("0.0433419000, 0.0414575000, 0.0354933000, 0.0172290000, -0.044194500, -0.255907800, -0.956502100", \ - "0.0433064000, 0.0414535000, 0.0354470000, 0.0172435000, -0.044264500, -0.255912000, -0.956476800", \ - "0.0433349000, 0.0414240000, 0.0354909000, 0.0172677000, -0.044343000, -0.255923000, -0.956471900", \ - "0.0428454000, 0.0408816000, 0.0349298000, 0.0167896000, -0.044696700, -0.256338600, -0.956929200", \ - "0.0425830000, 0.0407013000, 0.0347944000, 0.0166174000, -0.044911900, -0.256617200, -0.957152800", \ - "0.0426975000, 0.0408423000, 0.0347541000, 0.0165389000, -0.044889200, -0.256485400, -0.957171000", \ - "0.0484822000, 0.0465386000, 0.0404538000, 0.0210941000, -0.043076500, -0.256025800, -0.956605100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016399840, 0.0053790920, 0.0176432500, 0.0578692800, 0.1898093000, 0.6225684000"); - values("0.0490495000, 0.0508989000, 0.0571053000, 0.0775204000, 0.1427179000, 0.3553499000, 1.0524642000", \ - "0.0489720000, 0.0507552000, 0.0570165000, 0.0774362000, 0.1427736000, 0.3535812000, 1.0476493000", \ - "0.0488576000, 0.0507099000, 0.0567990000, 0.0773255000, 0.1426942000, 0.3543849000, 1.0513180000", \ - "0.0485259000, 0.0503820000, 0.0564485000, 0.0770206000, 0.1418549000, 0.3534555000, 1.0520203000", \ - "0.0481845000, 0.0500706000, 0.0561003000, 0.0765821000, 0.1415671000, 0.3528701000, 1.0443870000", \ - "0.0479770000, 0.0497329000, 0.0559182000, 0.0764541000, 0.1415934000, 0.3544899000, 1.0461071000", \ - "0.0501290000, 0.0519469000, 0.0579307000, 0.0779220000, 0.1420391000, 0.3527414000, 1.0467670000"); - } - } - max_capacitance : 0.6225680000; - max_transition : 1.5019950000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.4284925000, 0.4321941000, 0.4423047000, 0.4659346000, 0.5151804000, 0.6272079000, 0.9447566000", \ - "0.4331685000, 0.4368633000, 0.4470976000, 0.4707306000, 0.5202038000, 0.6319299000, 0.9497633000", \ - "0.4443255000, 0.4480489000, 0.4582560000, 0.4819148000, 0.5314576000, 0.6430140000, 0.9609673000", \ - "0.4699173000, 0.4736653000, 0.4838367000, 0.5076669000, 0.5568392000, 0.6686635000, 0.9860633000", \ - "0.5179819000, 0.5217022000, 0.5319227000, 0.5555842000, 0.6050702000, 0.7166566000, 1.0342954000", \ - "0.5865703000, 0.5903557000, 0.6005407000, 0.6242005000, 0.6734555000, 0.7853897000, 1.1027536000", \ - "0.6709817000, 0.6747072000, 0.6848607000, 0.7085558000, 0.7581344000, 0.8697149000, 1.1872144000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.5717622000, 0.5765045000, 0.5893120000, 0.6190649000, 0.6924932000, 0.9136427000, 1.6341102000", \ - "0.5762104000, 0.5809723000, 0.5936487000, 0.6235505000, 0.6973653000, 0.9176381000, 1.6383025000", \ - "0.5874511000, 0.5922746000, 0.6048618000, 0.6349319000, 0.7086817000, 0.9293988000, 1.6504240000", \ - "0.6123801000, 0.6172082000, 0.6297872000, 0.6598624000, 0.7334103000, 0.9536896000, 1.6746365000", \ - "0.6597666000, 0.6645022000, 0.6770449000, 0.7070663000, 0.7806367000, 1.0008995000, 1.7207104000", \ - "0.7290220000, 0.7337266000, 0.7466210000, 0.7763912000, 0.8503242000, 1.0712047000, 1.7929405000", \ - "0.8186149000, 0.8233222000, 0.8360287000, 0.8660978000, 0.9398573000, 1.1600250000, 1.8817088000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.0360117000, 0.0380370000, 0.0446432000, 0.0593286000, 0.0987997000, 0.2173298000, 0.6311101000", \ - "0.0360349000, 0.0381436000, 0.0443646000, 0.0594668000, 0.0984293000, 0.2170178000, 0.6310075000", \ - "0.0360619000, 0.0383774000, 0.0443498000, 0.0601324000, 0.0981054000, 0.2168160000, 0.6312500000", \ - "0.0363050000, 0.0384261000, 0.0446557000, 0.0594409000, 0.0990135000, 0.2171381000, 0.6274269000", \ - "0.0357993000, 0.0381389000, 0.0443522000, 0.0601772000, 0.0991845000, 0.2174672000, 0.6321128000", \ - "0.0361063000, 0.0383930000, 0.0441314000, 0.0593441000, 0.0991100000, 0.2170476000, 0.6283670000", \ - "0.0360744000, 0.0383484000, 0.0445071000, 0.0601710000, 0.0987109000, 0.2174121000, 0.6270097000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.0390928000, 0.0420609000, 0.0507045000, 0.0757399000, 0.1620567000, 0.4683606000, 1.4944875000", \ - "0.0389755000, 0.0419461000, 0.0507103000, 0.0757944000, 0.1619539000, 0.4680689000, 1.4927245000", \ - "0.0393475000, 0.0418872000, 0.0504232000, 0.0758617000, 0.1619926000, 0.4675559000, 1.4954976000", \ - "0.0393080000, 0.0420011000, 0.0504184000, 0.0758780000, 0.1617079000, 0.4678594000, 1.4947664000", \ - "0.0389229000, 0.0420632000, 0.0505382000, 0.0761564000, 0.1621217000, 0.4676407000, 1.4945839000", \ - "0.0391077000, 0.0421535000, 0.0508203000, 0.0759162000, 0.1619707000, 0.4688219000, 1.4941088000", \ - "0.0392064000, 0.0423718000, 0.0504592000, 0.0758573000, 0.1620008000, 0.4679588000, 1.4958811000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.3906759000, 0.3947574000, 0.4059705000, 0.4337536000, 0.5061108000, 0.7268277000, 1.4478989000", \ - "0.3951418000, 0.3989618000, 0.4101809000, 0.4381290000, 0.5106534000, 0.7309117000, 1.4517330000", \ - "0.4075777000, 0.4115141000, 0.4227912000, 0.4506797000, 0.5231020000, 0.7436625000, 1.4648177000", \ - "0.4401818000, 0.4444075000, 0.4556580000, 0.4835905000, 0.5559058000, 0.7770359000, 1.4968637000", \ - "0.5169347000, 0.5207990000, 0.5319921000, 0.5598734000, 0.6324171000, 0.8536604000, 1.5730965000", \ - "0.6793061000, 0.6833747000, 0.6945112000, 0.7224204000, 0.7948366000, 1.0161770000, 1.7356486000", \ - "0.9691504000, 0.9733365000, 0.9845822000, 1.0126103000, 1.0850896000, 1.3052686000, 2.0249802000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016399800, 0.0053790900, 0.0176432000, 0.0578693000, 0.1898090000, 0.6225680000"); - values("0.0318401000, 0.0349739000, 0.0437718000, 0.0700532000, 0.1587046000, 0.4690467000, 1.4937702000", \ - "0.0316945000, 0.0347259000, 0.0433704000, 0.0700053000, 0.1591753000, 0.4695433000, 1.4985602000", \ - "0.0316039000, 0.0346788000, 0.0435802000, 0.0700766000, 0.1592733000, 0.4703238000, 1.4987888000", \ - "0.0318493000, 0.0348725000, 0.0434566000, 0.0700030000, 0.1593679000, 0.4688346000, 1.4973740000", \ - "0.0316487000, 0.0348440000, 0.0436162000, 0.0702510000, 0.1590421000, 0.4695487000, 1.4927148000", \ - "0.0317936000, 0.0347784000, 0.0436296000, 0.0700047000, 0.1593451000, 0.4698462000, 1.4976833000", \ - "0.0322716000, 0.0355918000, 0.0441644000, 0.0701699000, 0.1592196000, 0.4669418000, 1.5019950000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SET_B") { - capacitance : 0.0033590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051231000, 0.0051557000, 0.0052307000, 0.0052374000, 0.0052529000, 0.0052886000, 0.0053710000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012562000, 0.0012139000, 0.0011164000, 0.0011072000, 0.0010859000, 0.0010369000, 0.0009240000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034190000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.131056600, -0.082847000, -0.103192100", \ - "-0.268377600, -0.218947300, -0.238071600", \ - "-0.374985700, -0.325555300, -0.341017600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1484844000, 0.1051576000, 0.1303854000", \ - "0.2833639000, 0.2375957000, 0.2603821000", \ - "0.3887513000, 0.3429831000, 0.3621074000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2400893000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dfxbp_1") { - leakage_power () { - value : 0.0113768000; - when : "CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0103024000; - when : "!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0142233000; - when : "CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0139049000; - when : "!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0114806000; - when : "!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0102975000; - when : "CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0137965000; - when : "CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0141522000; - when : "!CLK&!D&Q&!Q_N"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__dfxbp"; - cell_leakage_power : 0.0124417900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017830000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226934000, 0.0225795000, 0.0223169000, 0.0223888000, 0.0225547000, 0.0229371000, 0.0238187000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178186000, 0.0176958000, 0.0174127000, 0.0174241000, 0.0174501000, 0.0175104000, 0.0176494000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018650000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2071340000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1752772000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0054745000, 0.0054208000, 0.0052971000, 0.0053513000, 0.0054764000, 0.0057648000, 0.0064296000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000453100, -0.000515100, -0.000658000, -0.000610000, -0.000499500, -0.000244600, 0.0003431000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016730000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1033184000, 0.3175436000, 0.6206849000", \ - "-0.009588500, 0.1985332000, 0.4967917000", \ - "-0.097886100, 0.1090150000, 0.4023906000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0532695000, 0.1686178000, 0.2495911000", \ - "-0.016912800, 0.0850078000, 0.1501120000", \ - "-0.045395800, 0.0504212000, 0.1106426000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.043166000, -0.245184200, -0.506821600", \ - "0.0672995000, -0.135939500, -0.408563100", \ - "0.1433900000, -0.056186800, -0.330031300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.029738300, -0.131658800, -0.186997400", \ - "0.0355612000, -0.061476600, -0.114373700", \ - "0.0579408000, -0.035434900, -0.089552700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("-0.005482600, -0.000827600, 0.0076783000, 0.0166138000, 0.0111326000, -0.037797300, -0.191146100", \ - "-0.005428400, -0.000778300, 0.0077238000, 0.0166149000, 0.0111391000, -0.037796000, -0.191150200", \ - "-0.005296400, -0.000661300, 0.0077942000, 0.0166789000, 0.0110975000, -0.037843800, -0.191233100", \ - "-0.005328100, -0.000725000, 0.0076764000, 0.0164379000, 0.0107791000, -0.038249700, -0.191654000", \ - "-0.005352200, -0.000766200, 0.0076080000, 0.0163051000, 0.0106096000, -0.038421300, -0.191851600", \ - "-0.005378700, -0.000788900, 0.0075817000, 0.0163228000, 0.0106333000, -0.038427700, -0.191847000", \ - "-0.005383400, -0.000702000, 0.0078525000, 0.0168274000, 0.0114336000, -0.037697600, -0.191049500"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("-0.007101200, -0.004391200, 0.0018312000, 0.0150061000, 0.0421667000, 0.1055146000, 0.2651636000", \ - "-0.007052100, -0.004357100, 0.0018340000, 0.0149370000, 0.0420855000, 0.1053308000, 0.2651834000", \ - "-0.006921000, -0.004241000, 0.0019214000, 0.0149823000, 0.0421199000, 0.1053274000, 0.2649489000", \ - "-0.006945900, -0.004293800, 0.0018044000, 0.0147902000, 0.0418075000, 0.1044370000, 0.2633489000", \ - "-0.006973900, -0.004342200, 0.0017219000, 0.0146365000, 0.0416035000, 0.1042305000, 0.2632410000", \ - "-0.007004700, -0.004374300, 0.0016857000, 0.0146065000, 0.0415478000, 0.1046532000, 0.2643858000", \ - "-0.007017600, -0.004306100, 0.0019204000, 0.0150399000, 0.0419939000, 0.1049076000, 0.2642877000"); - } - } - max_capacitance : 0.1593120000; - max_transition : 1.4988650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.2809787000, 0.2867570000, 0.2988770000, 0.3237131000, 0.3776950000, 0.5072104000, 0.8436098000", \ - "0.2856670000, 0.2914494000, 0.3035988000, 0.3283958000, 0.3823747000, 0.5118743000, 0.8475957000", \ - "0.2967450000, 0.3025200000, 0.3146503000, 0.3394728000, 0.3934367000, 0.5229461000, 0.8593626000", \ - "0.3224458000, 0.3282324000, 0.3403559000, 0.3651870000, 0.4191361000, 0.5486627000, 0.8844088000", \ - "0.3696210000, 0.3754011000, 0.3875209000, 0.4123563000, 0.4663307000, 0.5958402000, 0.9317997000", \ - "0.4365058000, 0.4422571000, 0.4544123000, 0.4792260000, 0.5331922000, 0.6627159000, 0.9986502000", \ - "0.5190540000, 0.5248428000, 0.5369900000, 0.5617795000, 0.6157582000, 0.7452864000, 1.0810280000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.2835835000, 0.2906255000, 0.3064312000, 0.3434594000, 0.4380692000, 0.6827338000, 1.3211768000", \ - "0.2882511000, 0.2952951000, 0.3110846000, 0.3481273000, 0.4427539000, 0.6871723000, 1.3290893000", \ - "0.2991458000, 0.3061884000, 0.3219847000, 0.3590263000, 0.4536291000, 0.6979838000, 1.3404438000", \ - "0.3252240000, 0.3321953000, 0.3480001000, 0.3850240000, 0.4796027000, 0.7241311000, 1.3637290000", \ - "0.3733506000, 0.3803894000, 0.3961789000, 0.4332012000, 0.5277985000, 0.7720062000, 1.4170620000", \ - "0.4444641000, 0.4514607000, 0.4672712000, 0.5042922000, 0.5989051000, 0.8435533000, 1.4838540000", \ - "0.5371599000, 0.5442308000, 0.5600476000, 0.5971221000, 0.6917789000, 0.9364369000, 1.5749455000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0203386000, 0.0245776000, 0.0345697000, 0.0588278000, 0.1199722000, 0.2846436000, 0.7340124000", \ - "0.0203152000, 0.0246358000, 0.0346446000, 0.0588665000, 0.1195673000, 0.2844780000, 0.7303312000", \ - "0.0203605000, 0.0247328000, 0.0347731000, 0.0588051000, 0.1197663000, 0.2842201000, 0.7307692000", \ - "0.0203210000, 0.0245823000, 0.0347770000, 0.0587565000, 0.1198229000, 0.2850881000, 0.7334354000", \ - "0.0203502000, 0.0245674000, 0.0348373000, 0.0587400000, 0.1194722000, 0.2844647000, 0.7318172000", \ - "0.0204782000, 0.0246980000, 0.0347232000, 0.0587306000, 0.1197791000, 0.2846501000, 0.7307787000", \ - "0.0203677000, 0.0246424000, 0.0345796000, 0.0588340000, 0.1195391000, 0.2847425000, 0.7256828000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0258237000, 0.0324822000, 0.0498493000, 0.0992239000, 0.2315568000, 0.5783737000, 1.4988651000", \ - "0.0258572000, 0.0325466000, 0.0499697000, 0.0992956000, 0.2314060000, 0.5797111000, 1.4960296000", \ - "0.0258523000, 0.0325384000, 0.0499396000, 0.0992688000, 0.2313582000, 0.5793692000, 1.4973291000", \ - "0.0259825000, 0.0325182000, 0.0499102000, 0.0992766000, 0.2313689000, 0.5778562000, 1.4974409000", \ - "0.0258572000, 0.0325147000, 0.0498740000, 0.0992182000, 0.2313167000, 0.5794848000, 1.4942682000", \ - "0.0260790000, 0.0325772000, 0.0499779000, 0.0992633000, 0.2310322000, 0.5798421000, 1.4960533000", \ - "0.0261166000, 0.0326542000, 0.0501039000, 0.0993451000, 0.2313845000, 0.5777602000, 1.4952563000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("-0.005770700, -0.001388900, 0.0067081000, 0.0150120000, 0.0078847000, -0.046254700, -0.214952600", \ - "-0.005717500, -0.001358000, 0.0066941000, 0.0149394000, 0.0077642000, -0.046383400, -0.215135600", \ - "-0.005587600, -0.001242200, 0.0067793000, 0.0149800000, 0.0077522000, -0.046418300, -0.215194000", \ - "-0.005605700, -0.001279000, 0.0067012000, 0.0148387000, 0.0075370000, -0.046662600, -0.215456100", \ - "-0.005640400, -0.001341800, 0.0065828000, 0.0146372000, 0.0072604000, -0.046996200, -0.215829800", \ - "-0.005669800, -0.001367100, 0.0065609000, 0.0146179000, 0.0072371000, -0.047016100, -0.215850200", \ - "-0.005686400, -0.001307300, 0.0067876000, 0.0150623000, 0.0078029000, -0.046469100, -0.215223800"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("-0.007043800, -0.004178400, 0.0024957000, 0.0166137000, 0.0461416000, 0.1141123000, 0.2897863000", \ - "-0.006987500, -0.004128200, 0.0025371000, 0.0166189000, 0.0461271000, 0.1142570000, 0.2896594000", \ - "-0.006856200, -0.004010200, 0.0026266000, 0.0166864000, 0.0459782000, 0.1142184000, 0.2894493000", \ - "-0.006885400, -0.004079100, 0.0024937000, 0.0164347000, 0.0456322000, 0.1144894000, 0.2879126000", \ - "-0.006910200, -0.004115400, 0.0024136000, 0.0163003000, 0.0454265000, 0.1136218000, 0.2876046000", \ - "-0.006935400, -0.004136900, 0.0024062000, 0.0163249000, 0.0456577000, 0.1142418000, 0.2877297000", \ - "-0.006940500, -0.004048000, 0.0026652000, 0.0168298000, 0.0462420000, 0.1146942000, 0.2895345000"); - } - } - max_capacitance : 0.1730450000; - max_transition : 1.4992970000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.3338745000, 0.3389951000, 0.3499357000, 0.3730743000, 0.4262632000, 0.5634303000, 0.9271915000", \ - "0.3385464000, 0.3436858000, 0.3546276000, 0.3777234000, 0.4308944000, 0.5681980000, 0.9312953000", \ - "0.3496367000, 0.3547738000, 0.3657161000, 0.3888233000, 0.4420513000, 0.5792888000, 0.9424141000", \ - "0.3755705000, 0.3806655000, 0.3916091000, 0.4147481000, 0.4679139000, 0.6051619000, 0.9693605000", \ - "0.4234686000, 0.4286023000, 0.4395430000, 0.4626644000, 0.5158821000, 0.6531177000, 1.0163410000", \ - "0.4944894000, 0.4995984000, 0.5105695000, 0.5336831000, 0.5868222000, 0.7240459000, 1.0879475000", \ - "0.5874014000, 0.5925397000, 0.6034811000, 0.6265902000, 0.6798225000, 0.8170652000, 1.1815259000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.3345255000, 0.3405901000, 0.3550149000, 0.3903184000, 0.4825244000, 0.7257558000, 1.3714991000", \ - "0.3392322000, 0.3453386000, 0.3596949000, 0.3949095000, 0.4871072000, 0.7306131000, 1.3757807000", \ - "0.3503169000, 0.3564175000, 0.3707851000, 0.4060152000, 0.4980437000, 0.7417982000, 1.3885403000", \ - "0.3759796000, 0.3820352000, 0.3964514000, 0.4318712000, 0.5238999000, 0.7672147000, 1.4133655000", \ - "0.4231102000, 0.4292331000, 0.4436566000, 0.4789792000, 0.5710782000, 0.8143639000, 1.4600308000", \ - "0.4900329000, 0.4961618000, 0.5105051000, 0.5458497000, 0.6378149000, 0.8819899000, 1.5275773000", \ - "0.5726364000, 0.5786926000, 0.5930476000, 0.6283518000, 0.7204251000, 0.9648345000, 1.6084142000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0164052000, 0.0206578000, 0.0302986000, 0.0542539000, 0.1200449000, 0.3020092000, 0.7923853000", \ - "0.0166487000, 0.0204884000, 0.0302659000, 0.0543965000, 0.1202049000, 0.3019864000, 0.7887255000", \ - "0.0166706000, 0.0205383000, 0.0302767000, 0.0543956000, 0.1201909000, 0.3019893000, 0.7863020000", \ - "0.0163929000, 0.0206241000, 0.0301651000, 0.0543524000, 0.1203208000, 0.3017577000, 0.7880359000", \ - "0.0166908000, 0.0205974000, 0.0302837000, 0.0543437000, 0.1201348000, 0.3019918000, 0.7893919000", \ - "0.0163865000, 0.0206182000, 0.0302176000, 0.0540498000, 0.1201929000, 0.3022156000, 0.7922470000", \ - "0.0166720000, 0.0205281000, 0.0302824000, 0.0544029000, 0.1202110000, 0.3018188000, 0.7864883000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0200068000, 0.0264557000, 0.0438055000, 0.0920966000, 0.2224881000, 0.5697788000, 1.4992970000", \ - "0.0200112000, 0.0264344000, 0.0437807000, 0.0920713000, 0.2226008000, 0.5704149000, 1.4954517000", \ - "0.0199832000, 0.0264282000, 0.0437766000, 0.0920968000, 0.2229777000, 0.5712931000, 1.4964505000", \ - "0.0200019000, 0.0264286000, 0.0438610000, 0.0920271000, 0.2228837000, 0.5732534000, 1.4942347000", \ - "0.0200178000, 0.0264558000, 0.0438145000, 0.0920887000, 0.2230886000, 0.5729094000, 1.4957212000", \ - "0.0199993000, 0.0264797000, 0.0438492000, 0.0921370000, 0.2230236000, 0.5722164000, 1.4910694000", \ - "0.0199907000, 0.0264320000, 0.0438281000, 0.0921197000, 0.2230087000, 0.5713494000, 1.4944617000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dfxbp_2") { - leakage_power () { - value : 0.0119064000; - when : "CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0108319000; - when : "!CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0134870000; - when : "CLK&!D&Q&!Q_N"; - } - leakage_power () { - value : 0.0131686000; - when : "!CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0120101000; - when : "!CLK&D&!Q&Q_N"; - } - leakage_power () { - value : 0.0108270000; - when : "CLK&!D&!Q&Q_N"; - } - leakage_power () { - value : 0.0130602000; - when : "CLK&D&Q&!Q_N"; - } - leakage_power () { - value : 0.0134159000; - when : "!CLK&!D&Q&!Q_N"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__dfxbp"; - cell_leakage_power : 0.0123383900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017800000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226628000, 0.0225479000, 0.0222832000, 0.0223632000, 0.0225475000, 0.0229725000, 0.0239523000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178197000, 0.0176966000, 0.0174129000, 0.0174501000, 0.0175357000, 0.0177334000, 0.0181890000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018650000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2093310000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1851638000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055389000, 0.0054574000, 0.0052694000, 0.0053319000, 0.0054760000, 0.0058082000, 0.0065740000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000455300, -0.000515100, -0.000652700, -0.000604900, -0.000494700, -0.000240400, 0.0003457000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016730000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1045391000, 0.3199850000, 0.6219056000", \ - "-0.008367800, 0.2009746000, 0.4992331000", \ - "-0.096665400, 0.1090150000, 0.4048320000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0544902000, 0.1710592000, 0.2544740000", \ - "-0.015692100, 0.0862285000, 0.1513327000", \ - "-0.045395800, 0.0516419000, 0.1118633000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.040724600, -0.242742800, -0.500718100", \ - "0.0685202000, -0.133498000, -0.403680400", \ - "0.1446107000, -0.054966100, -0.327589900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.028517600, -0.130438200, -0.184556000", \ - "0.0355612000, -0.060255900, -0.114373700", \ - "0.0579408000, -0.035434900, -0.089552700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014456210, 0.0041796400, 0.0120843500, 0.0349387800, 0.1010165000, 0.2920631000"); - values("-0.005746100, -0.000554700, 0.0101077000, 0.0217896000, 0.0092629000, -0.082375300, -0.385012600", \ - "-0.005684500, -0.000511000, 0.0101369000, 0.0218088000, 0.0093105000, -0.082316500, -0.384993000", \ - "-0.005549000, -0.000380900, 0.0102170000, 0.0218235000, 0.0092582000, -0.082443800, -0.385156400", \ - "-0.005590000, -0.000451400, 0.0100912000, 0.0216018000, 0.0088505000, -0.082874000, -0.385586500", \ - "-0.005643700, -0.000520200, 0.0099935000, 0.0214542000, 0.0086827000, -0.083102900, -0.385870200", \ - "-0.005740500, -0.000604900, 0.0099037000, 0.0213946000, 0.0086319000, -0.083117700, -0.385877900", \ - "-0.005914100, -0.000697700, 0.0100129000, 0.0218508000, 0.0094369000, -0.082497700, -0.385270600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014456210, 0.0041796400, 0.0120843500, 0.0349387800, 0.1010165000, 0.2920631000"); - values("-0.007368300, -0.004603000, 0.0026009000, 0.0200155000, 0.0613637000, 0.1692873000, 0.4763728000", \ - "-0.007316400, -0.004562000, 0.0025962000, 0.0199795000, 0.0613405000, 0.1692190000, 0.4794763000", \ - "-0.007182300, -0.004442600, 0.0026952000, 0.0200202000, 0.0612611000, 0.1696448000, 0.4776952000", \ - "-0.007216800, -0.004504800, 0.0025657000, 0.0197987000, 0.0609143000, 0.1690306000, 0.4775162000", \ - "-0.007271500, -0.004578300, 0.0024493000, 0.0196147000, 0.0606326000, 0.1693911000, 0.4748742000", \ - "-0.007370500, -0.004678500, 0.0023446000, 0.0195079000, 0.0606021000, 0.1685264000, 0.4780004000", \ - "-0.007539900, -0.004748600, 0.0024999000, 0.0199316000, 0.0609999000, 0.1692889000, 0.4788320000"); - } - } - max_capacitance : 0.2920630000; - max_transition : 1.5026260000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014456200, 0.0041796400, 0.0120844000, 0.0349388000, 0.1010160000, 0.2920630000"); - values("0.2939337000, 0.2991456000, 0.3105704000, 0.3338237000, 0.3828770000, 0.5017026000, 0.8331890000", \ - "0.2986641000, 0.3038158000, 0.3152867000, 0.3383178000, 0.3875935000, 0.5064137000, 0.8379199000", \ - "0.3097049000, 0.3148803000, 0.3263292000, 0.3496073000, 0.3986365000, 0.5174657000, 0.8483946000", \ - "0.3354556000, 0.3405949000, 0.3520446000, 0.3752912000, 0.4243495000, 0.5431761000, 0.8750231000", \ - "0.3825875000, 0.3877902000, 0.3992241000, 0.4224771000, 0.4715326000, 0.5903603000, 0.9218285000", \ - "0.4494993000, 0.4546689000, 0.4660974000, 0.4893612000, 0.5384150000, 0.6572429000, 0.9885449000", \ - "0.5320565000, 0.5372565000, 0.5487030000, 0.5719559000, 0.6210189000, 0.7398491000, 1.0713375000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014456200, 0.0041796400, 0.0120844000, 0.0349388000, 0.1010160000, 0.2920630000"); - values("0.2915415000, 0.2974732000, 0.3111724000, 0.3428633000, 0.4263008000, 0.6614584000, 1.3434092000", \ - "0.2963151000, 0.3021714000, 0.3158973000, 0.3476527000, 0.4310308000, 0.6660844000, 1.3439048000", \ - "0.3070964000, 0.3130338000, 0.3267790000, 0.3584773000, 0.4419116000, 0.6769550000, 1.3543232000", \ - "0.3331387000, 0.3390565000, 0.3527865000, 0.3845348000, 0.4678624000, 0.7029640000, 1.3811806000", \ - "0.3814105000, 0.3873324000, 0.4010140000, 0.4327500000, 0.5161817000, 0.7511866000, 1.4292345000", \ - "0.4523299000, 0.4582610000, 0.4719295000, 0.5036253000, 0.5871542000, 0.8222781000, 1.4993913000", \ - "0.5449576000, 0.5509430000, 0.5646837000, 0.5963235000, 0.6797641000, 0.9150148000, 1.5924395000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014456200, 0.0041796400, 0.0120844000, 0.0349388000, 0.1010160000, 0.2920630000"); - values("0.0198373000, 0.0231327000, 0.0309251000, 0.0498398000, 0.0997312000, 0.2437546000, 0.6823145000", \ - "0.0196640000, 0.0230318000, 0.0308999000, 0.0501471000, 0.0995483000, 0.2437247000, 0.6822563000", \ - "0.0198109000, 0.0230543000, 0.0311045000, 0.0501161000, 0.0994619000, 0.2439108000, 0.6830778000", \ - "0.0196387000, 0.0230427000, 0.0309121000, 0.0502598000, 0.0996850000, 0.2441380000, 0.6856588000", \ - "0.0198104000, 0.0231680000, 0.0309211000, 0.0498269000, 0.0997233000, 0.2437237000, 0.6874989000", \ - "0.0197163000, 0.0231023000, 0.0310053000, 0.0501585000, 0.0994668000, 0.2441724000, 0.6866173000", \ - "0.0198658000, 0.0230767000, 0.0310097000, 0.0502092000, 0.0994081000, 0.2439696000, 0.6793464000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014456200, 0.0041796400, 0.0120844000, 0.0349388000, 0.1010160000, 0.2920630000"); - values("0.0228861000, 0.0274590000, 0.0402981000, 0.0773530000, 0.1918802000, 0.5256561000, 1.5026261000", \ - "0.0227768000, 0.0274077000, 0.0401665000, 0.0773535000, 0.1917161000, 0.5254573000, 1.4945482000", \ - "0.0229023000, 0.0274904000, 0.0402333000, 0.0773668000, 0.1916745000, 0.5253888000, 1.4970435000", \ - "0.0229005000, 0.0273991000, 0.0401264000, 0.0773527000, 0.1912976000, 0.5252174000, 1.4933316000", \ - "0.0228419000, 0.0274808000, 0.0401537000, 0.0773541000, 0.1916395000, 0.5240703000, 1.4943603000", \ - "0.0229576000, 0.0276408000, 0.0402595000, 0.0774330000, 0.1914362000, 0.5244811000, 1.5008912000", \ - "0.0230037000, 0.0275850000, 0.0402911000, 0.0775002000, 0.1916715000, 0.5243518000, 1.5016002000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014681390, 0.0043108630, 0.0126578900, 0.0371670900, 0.1091329000, 0.3204445000"); - values("-0.005990500, -0.001073900, 0.0091447000, 0.0200345000, 0.0052049000, -0.096170000, -0.431829400", \ - "-0.005934900, -0.001032300, 0.0091507000, 0.0200077000, 0.0051357000, -0.096286600, -0.431961400", \ - "-0.005803400, -0.000913600, 0.0092290000, 0.0200410000, 0.0051192000, -0.096315400, -0.432047400", \ - "-0.005832500, -0.000963100, 0.0091367000, 0.0198648000, 0.0048579000, -0.096618000, -0.432330600", \ - "-0.005890700, -0.001045800, 0.0090095000, 0.0196516000, 0.0045285000, -0.097008300, -0.432747400", \ - "-0.005988500, -0.001145400, 0.0089047000, 0.0195553000, 0.0044387000, -0.097105100, -0.432807400", \ - "-0.006169300, -0.001241900, 0.0089971000, 0.0199684000, 0.0048968000, -0.096703500, -0.432337100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014681390, 0.0043108630, 0.0126578900, 0.0371670900, 0.1091329000, 0.3204445000"); - values("-0.007361000, -0.004489900, 0.0031840000, 0.0218063000, 0.0663540000, 0.1856135000, 0.5269221000", \ - "-0.007303200, -0.004441400, 0.0032150000, 0.0218290000, 0.0663637000, 0.1856424000, 0.5271029000", \ - "-0.007166700, -0.004313200, 0.0033147000, 0.0218378000, 0.0662840000, 0.1853440000, 0.5282354000", \ - "-0.007204100, -0.004380500, 0.0031588000, 0.0216322000, 0.0659281000, 0.1852988000, 0.5277705000", \ - "-0.007256300, -0.004450300, 0.0030777000, 0.0214638000, 0.0657698000, 0.1846813000, 0.5262124000", \ - "-0.007352400, -0.004544500, 0.0029827000, 0.0213871000, 0.0656759000, 0.1838250000, 0.5251569000", \ - "-0.007506200, -0.004581600, 0.0031514000, 0.0218117000, 0.0661818000, 0.1847365000, 0.5233616000"); - } - } - max_capacitance : 0.3204440000; - max_transition : 1.5000040000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014681400, 0.0043108600, 0.0126579000, 0.0371671000, 0.1091330000, 0.3204440000"); - values("0.3731912000, 0.3778953000, 0.3884605000, 0.4101524000, 0.4564214000, 0.5735504000, 0.9111091000", \ - "0.3779075000, 0.3826397000, 0.3931673000, 0.4148214000, 0.4611629000, 0.5782286000, 0.9153185000", \ - "0.3890191000, 0.3937645000, 0.4042767000, 0.4259400000, 0.4721960000, 0.5893718000, 0.9270197000", \ - "0.4143366000, 0.4190992000, 0.4296436000, 0.4512953000, 0.4975888000, 0.6145358000, 0.9511834000", \ - "0.4628384000, 0.4675429000, 0.4781117000, 0.4997537000, 0.5460413000, 0.6631465000, 1.0007911000", \ - "0.5338146000, 0.5385105000, 0.5489842000, 0.5705450000, 0.6168849000, 0.7339707000, 1.0713894000", \ - "0.6267308000, 0.6315005000, 0.6420655000, 0.6636441000, 0.7099950000, 0.8271099000, 1.1647078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014681400, 0.0043108600, 0.0126579000, 0.0371671000, 0.1091330000, 0.3204440000"); - values("0.3774744000, 0.3827781000, 0.3953425000, 0.4250546000, 0.5052750000, 0.7373323000, 1.4205001000", \ - "0.3821422000, 0.3874530000, 0.3999971000, 0.4298188000, 0.5100953000, 0.7423455000, 1.4252451000", \ - "0.3932538000, 0.3985847000, 0.4111124000, 0.4408532000, 0.5210570000, 0.7531054000, 1.4362779000", \ - "0.4189314000, 0.4242763000, 0.4366814000, 0.4665681000, 0.5467103000, 0.7787018000, 1.4618713000", \ - "0.4660918000, 0.4714143000, 0.4839641000, 0.5136814000, 0.5937965000, 0.8259054000, 1.5089726000", \ - "0.5329846000, 0.5382764000, 0.5507867000, 0.5806411000, 0.6607120000, 0.8930132000, 1.5757120000", \ - "0.6156549000, 0.6209541000, 0.6335176000, 0.6631512000, 0.7434952000, 0.9765194000, 1.6592211000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014681400, 0.0043108600, 0.0126579000, 0.0371671000, 0.1091330000, 0.3204440000"); - values("0.0187029000, 0.0218779000, 0.0289293000, 0.0468728000, 0.0953051000, 0.2454093000, 0.7025816000", \ - "0.0186896000, 0.0216368000, 0.0288264000, 0.0470670000, 0.0956636000, 0.2444467000, 0.7022690000", \ - "0.0187617000, 0.0216733000, 0.0288741000, 0.0470651000, 0.0957222000, 0.2452724000, 0.7025432000", \ - "0.0187542000, 0.0216799000, 0.0288893000, 0.0470978000, 0.0954611000, 0.2446547000, 0.7032816000", \ - "0.0185553000, 0.0215163000, 0.0293217000, 0.0471148000, 0.0956309000, 0.2452111000, 0.6978825000", \ - "0.0185762000, 0.0215259000, 0.0290220000, 0.0470565000, 0.0959132000, 0.2451253000, 0.7007563000", \ - "0.0185898000, 0.0215943000, 0.0288889000, 0.0471331000, 0.0955531000, 0.2451730000, 0.6958025000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014681400, 0.0043108600, 0.0126579000, 0.0371671000, 0.1091330000, 0.3204440000"); - values("0.0198138000, 0.0241140000, 0.0360235000, 0.0717001000, 0.1830411000, 0.5148825000, 1.4977699000", \ - "0.0199296000, 0.0240958000, 0.0360666000, 0.0716995000, 0.1830006000, 0.5160203000, 1.4997453000", \ - "0.0196496000, 0.0239790000, 0.0359694000, 0.0717413000, 0.1830314000, 0.5149990000, 1.4967306000", \ - "0.0198208000, 0.0240416000, 0.0359606000, 0.0717954000, 0.1826920000, 0.5155061000, 1.4979881000", \ - "0.0198502000, 0.0241582000, 0.0360400000, 0.0716244000, 0.1830282000, 0.5155956000, 1.4983632000", \ - "0.0196348000, 0.0240388000, 0.0360382000, 0.0717838000, 0.1828325000, 0.5159727000, 1.5000038000", \ - "0.0197884000, 0.0241350000, 0.0360132000, 0.0718167000, 0.1828389000, 0.5155632000, 1.4953894000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dfxtp_1") { - leakage_power () { - value : 0.0091260000; - when : "CLK&D&!Q"; - } - leakage_power () { - value : 0.0080516000; - when : "!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0084678000; - when : "CLK&!D&Q"; - } - leakage_power () { - value : 0.0081494000; - when : "!CLK&D&Q"; - } - leakage_power () { - value : 0.0092298000; - when : "!CLK&D&!Q"; - } - leakage_power () { - value : 0.0080467000; - when : "CLK&!D&!Q"; - } - leakage_power () { - value : 0.0080410000; - when : "CLK&D&Q"; - } - leakage_power () { - value : 0.0083967000; - when : "!CLK&!D&Q"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__dfxtp"; - cell_leakage_power : 0.0084386350; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017940000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0227158000, 0.0226016000, 0.0223385000, 0.0224266000, 0.0226296000, 0.0230975000, 0.0241762000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178184000, 0.0176956000, 0.0174124000, 0.0174497000, 0.0175356000, 0.0177335000, 0.0181899000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018770000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2082325000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1686861000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0054714000, 0.0054188000, 0.0052975000, 0.0053518000, 0.0054769000, 0.0057650000, 0.0064295000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000426700, -0.000495200, -0.000653100, -0.000605300, -0.000495300, -0.000241700, 0.0003431000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016740000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1033184000, 0.3187643000, 0.6206849000", \ - "-0.010809200, 0.1997539000, 0.4980123000", \ - "-0.096665400, 0.1090150000, 0.4036113000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0508281000, 0.1649557000, 0.2434876000", \ - "-0.018133500, 0.0837871000, 0.1476706000", \ - "-0.045395800, 0.0504212000, 0.1106426000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.046828100, -0.251287800, -0.517807900", \ - "0.0636374000, -0.140822300, -0.414666700", \ - "0.1409486000, -0.059849000, -0.334914100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.028517600, -0.131658800, -0.185776700", \ - "0.0355612000, -0.060255900, -0.114373700", \ - "0.0579408000, -0.035434900, -0.089552700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0190634000, 0.0180793000, 0.0153023000, 0.0068343000, -0.016624000, -0.078544100, -0.240887700", \ - "0.0190768000, 0.0180948000, 0.0153314000, 0.0068509000, -0.016597900, -0.078512900, -0.240860100", \ - "0.0191492000, 0.0181883000, 0.0154150000, 0.0069405000, -0.016520500, -0.078434100, -0.240788600", \ - "0.0186857000, 0.0176924000, 0.0149297000, 0.0064486000, -0.017002900, -0.078920100, -0.241269200", \ - "0.0183710000, 0.0173865000, 0.0146105000, 0.0061428000, -0.017315400, -0.079239400, -0.241577500", \ - "0.0192369000, 0.0179868000, 0.0145973000, 0.0059922000, -0.017445200, -0.079360300, -0.241720600", \ - "0.0201970000, 0.0189707000, 0.0156635000, 0.0067443000, -0.016860900, -0.078901100, -0.241268900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0177646000, 0.0193971000, 0.0233851000, 0.0327475000, 0.0562523000, 0.1177991000, 0.2778807000", \ - "0.0176630000, 0.0192938000, 0.0232755000, 0.0326502000, 0.0559730000, 0.1175683000, 0.2790250000", \ - "0.0177510000, 0.0193724000, 0.0233518000, 0.0327256000, 0.0560518000, 0.1176326000, 0.2794671000", \ - "0.0174417000, 0.0190740000, 0.0230712000, 0.0323867000, 0.0557982000, 0.1167644000, 0.2775787000", \ - "0.0169781000, 0.0185996000, 0.0225870000, 0.0319373000, 0.0553063000, 0.1163212000, 0.2771098000", \ - "0.0169381000, 0.0185222000, 0.0224544000, 0.0318620000, 0.0552467000, 0.1161432000, 0.2768812000", \ - "0.0185061000, 0.0198623000, 0.0233271000, 0.0323516000, 0.0555884000, 0.1166932000, 0.2765244000"); - } - } - max_capacitance : 0.1620580000; - max_transition : 1.4979510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2652426000, 0.2704631000, 0.2814136000, 0.3040849000, 0.3548850000, 0.4829165000, 0.8184850000", \ - "0.2698856000, 0.2750948000, 0.2860738000, 0.3087274000, 0.3594963000, 0.4876597000, 0.8231034000", \ - "0.2810230000, 0.2861993000, 0.2971512000, 0.3198187000, 0.3706330000, 0.4986082000, 0.8341430000", \ - "0.3066856000, 0.3118962000, 0.3228766000, 0.3455267000, 0.3962939000, 0.5242380000, 0.8597210000", \ - "0.3538829000, 0.3591000000, 0.3700543000, 0.3927264000, 0.4435225000, 0.5715469000, 0.9069842000", \ - "0.4207567000, 0.4259731000, 0.4369489000, 0.4595964000, 0.5104241000, 0.6382177000, 0.9734934000", \ - "0.5033737000, 0.5085845000, 0.5194807000, 0.5421503000, 0.5929778000, 0.7209600000, 1.0553800000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2692208000, 0.2759120000, 0.2912889000, 0.3279992000, 0.4217970000, 0.6665245000, 1.3109124000", \ - "0.2739075000, 0.2806270000, 0.2959557000, 0.3326931000, 0.4264703000, 0.6709840000, 1.3137214000", \ - "0.2850037000, 0.2917141000, 0.3070411000, 0.3437776000, 0.4375723000, 0.6820410000, 1.3251137000", \ - "0.3109157000, 0.3177000000, 0.3330731000, 0.3697138000, 0.4634656000, 0.7081447000, 1.3505562000", \ - "0.3588843000, 0.3656163000, 0.3810043000, 0.4176165000, 0.5115445000, 0.7560778000, 1.3983928000", \ - "0.4302250000, 0.4370071000, 0.4523242000, 0.4890442000, 0.5826956000, 0.8274527000, 1.4692350000", \ - "0.5228102000, 0.5296081000, 0.5449542000, 0.5816437000, 0.6755747000, 0.9208264000, 1.5599231000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0170130000, 0.0209158000, 0.0305161000, 0.0532956000, 0.1140993000, 0.2828197000, 0.7291198000", \ - "0.0170204000, 0.0208936000, 0.0304365000, 0.0532848000, 0.1141926000, 0.2823546000, 0.7286334000", \ - "0.0170521000, 0.0208928000, 0.0304488000, 0.0531171000, 0.1141636000, 0.2818789000, 0.7296576000", \ - "0.0170249000, 0.0208895000, 0.0304105000, 0.0532922000, 0.1142203000, 0.2810162000, 0.7330789000", \ - "0.0170145000, 0.0209623000, 0.0305155000, 0.0532973000, 0.1141109000, 0.2834042000, 0.7304687000", \ - "0.0170612000, 0.0210305000, 0.0304362000, 0.0533915000, 0.1136621000, 0.2818343000, 0.7244916000", \ - "0.0169871000, 0.0209343000, 0.0304787000, 0.0534007000, 0.1145486000, 0.2807576000, 0.7217655000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0234424000, 0.0298911000, 0.0475084000, 0.0964473000, 0.2281124000, 0.5769554000, 1.4974917000", \ - "0.0233802000, 0.0299373000, 0.0474781000, 0.0964878000, 0.2280204000, 0.5776107000, 1.4979508000", \ - "0.0234508000, 0.0299402000, 0.0474791000, 0.0964980000, 0.2280563000, 0.5776538000, 1.4968740000", \ - "0.0233737000, 0.0299111000, 0.0474168000, 0.0964358000, 0.2283930000, 0.5766957000, 1.4968595000", \ - "0.0233381000, 0.0299148000, 0.0474966000, 0.0964763000, 0.2280841000, 0.5770273000, 1.4966087000", \ - "0.0234295000, 0.0300408000, 0.0474620000, 0.0962365000, 0.2283888000, 0.5762835000, 1.4972330000", \ - "0.0236097000, 0.0300974000, 0.0475865000, 0.0964619000, 0.2286190000, 0.5760052000, 1.4919925000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dfxtp_2") { - leakage_power () { - value : 0.0096452000; - when : "CLK&D&!Q"; - } - leakage_power () { - value : 0.0085707000; - when : "!CLK&!D&!Q"; - } - leakage_power () { - value : 0.0079604000; - when : "CLK&!D&Q"; - } - leakage_power () { - value : 0.0076421000; - when : "!CLK&D&Q"; - } - leakage_power () { - value : 0.0097489000; - when : "!CLK&D&!Q"; - } - leakage_power () { - value : 0.0085659000; - when : "CLK&!D&!Q"; - } - leakage_power () { - value : 0.0075337000; - when : "CLK&D&Q"; - } - leakage_power () { - value : 0.0078894000; - when : "!CLK&!D&Q"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__dfxtp"; - cell_leakage_power : 0.0084445270; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017870000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226814000, 0.0225677000, 0.0223054000, 0.0223900000, 0.0225848000, 0.0230339000, 0.0240693000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178185000, 0.0176956000, 0.0174125000, 0.0174244000, 0.0174521000, 0.0175156000, 0.0176624000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018770000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2093310000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1785727000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0054663000, 0.0054155000, 0.0052985000, 0.0053543000, 0.0054830000, 0.0057795000, 0.0064631000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000453900, -0.000515800, -0.000658700, -0.000610700, -0.000500100, -0.000245400, 0.0003421000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016740000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1057598000, 0.3199850000, 0.6231263000", \ - "-0.008367800, 0.2009746000, 0.4992331000", \ - "-0.096665400, 0.1102357000, 0.4048320000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0557109000, 0.1722799000, 0.2556946000", \ - "-0.015692100, 0.0862285000, 0.1525534000", \ - "-0.045395800, 0.0516419000, 0.1118633000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.039503900, -0.240301400, -0.497056000", \ - "0.0697409000, -0.132277300, -0.402459600", \ - "0.1458314000, -0.053745400, -0.326369100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.028517600, -0.130438200, -0.184556000", \ - "0.0355612000, -0.060255900, -0.113153000", \ - "0.0579408000, -0.035434900, -0.088332000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0228197000, 0.0214479000, 0.0177281000, 0.0061374000, -0.031095700, -0.141634000, -0.463766900", \ - "0.0228573000, 0.0214312000, 0.0177256000, 0.0061362000, -0.031066700, -0.141608800, -0.463732000", \ - "0.0229357000, 0.0215561000, 0.0178018000, 0.0062280000, -0.030980300, -0.141517600, -0.463649000", \ - "0.0224730000, 0.0210603000, 0.0173468000, 0.0057838000, -0.031446900, -0.141986400, -0.464120000", \ - "0.0221963000, 0.0208463000, 0.0171261000, 0.0055235000, -0.031701600, -0.142239200, -0.464371900", \ - "0.0227450000, 0.0212380000, 0.0171301000, 0.0055124000, -0.031686900, -0.142230800, -0.464357600", \ - "0.0253895000, 0.0239679000, 0.0197260000, 0.0070594000, -0.030712700, -0.141402700, -0.463598100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014545450, 0.0042314040, 0.0123095400, 0.0358095600, 0.1041733000, 0.3030494000"); - values("0.0230390000, 0.0247664000, 0.0297915000, 0.0434849000, 0.0813527000, 0.1916590000, 0.5081785000", \ - "0.0229655000, 0.0246906000, 0.0297126000, 0.0434013000, 0.0812681000, 0.1904434000, 0.5116607000", \ - "0.0230207000, 0.0247482000, 0.0297628000, 0.0434599000, 0.0813613000, 0.1904532000, 0.5088325000", \ - "0.0227271000, 0.0244661000, 0.0294862000, 0.0431743000, 0.0810124000, 0.1912006000, 0.5094204000", \ - "0.0223497000, 0.0240690000, 0.0290966000, 0.0427864000, 0.0806954000, 0.1907905000, 0.5089236000", \ - "0.0223152000, 0.0240289000, 0.0289908000, 0.0427565000, 0.0805890000, 0.1895692000, 0.5080376000", \ - "0.0243142000, 0.0258854000, 0.0304875000, 0.0437307000, 0.0814834000, 0.1908396000, 0.5080981000"); - } - } - max_capacitance : 0.3030490000; - max_transition : 1.5035290000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.2795616000, 0.2841125000, 0.2942010000, 0.3149094000, 0.3594390000, 0.4727498000, 0.7983809000", \ - "0.2842579000, 0.2888093000, 0.2989315000, 0.3195862000, 0.3641682000, 0.4772693000, 0.8016181000", \ - "0.2953230000, 0.2998833000, 0.3099785000, 0.3307426000, 0.3752246000, 0.4884096000, 0.8138323000", \ - "0.3210279000, 0.3255841000, 0.3357010000, 0.3564503000, 0.4009351000, 0.5140751000, 0.8396123000", \ - "0.3682029000, 0.3727567000, 0.3828441000, 0.4035163000, 0.4480865000, 0.5613935000, 0.8870422000", \ - "0.4351280000, 0.4396260000, 0.4497359000, 0.4705039000, 0.5149845000, 0.6281191000, 0.9525851000", \ - "0.5176687000, 0.5222068000, 0.5323268000, 0.5530301000, 0.5975534000, 0.7107622000, 1.0352513000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.2792339000, 0.2847200000, 0.2975762000, 0.3279108000, 0.4094114000, 0.6433676000, 1.3230015000", \ - "0.2838874000, 0.2893809000, 0.3021559000, 0.3324817000, 0.4141691000, 0.6476517000, 1.3297279000", \ - "0.2950091000, 0.3004876000, 0.3133279000, 0.3435017000, 0.4249499000, 0.6589563000, 1.3425838000", \ - "0.3203534000, 0.3258430000, 0.3387028000, 0.3689726000, 0.4505780000, 0.6843520000, 1.3655790000", \ - "0.3689354000, 0.3743940000, 0.3872474000, 0.4175316000, 0.4991633000, 0.7328872000, 1.4142169000", \ - "0.4399090000, 0.4454017000, 0.4582228000, 0.4885338000, 0.5698912000, 0.8039221000, 1.4892577000", \ - "0.5327795000, 0.5382492000, 0.5510782000, 0.5813615000, 0.6627552000, 0.8968980000, 1.5772934000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0171319000, 0.0200545000, 0.0269521000, 0.0444305000, 0.0914008000, 0.2356388000, 0.6632985000", \ - "0.0170833000, 0.0200305000, 0.0270855000, 0.0443957000, 0.0915485000, 0.2347225000, 0.6701127000", \ - "0.0171181000, 0.0200280000, 0.0271128000, 0.0444161000, 0.0915577000, 0.2344551000, 0.6632783000", \ - "0.0170921000, 0.0200207000, 0.0270818000, 0.0444044000, 0.0915514000, 0.2343707000, 0.6625780000", \ - "0.0171479000, 0.0199621000, 0.0269877000, 0.0443700000, 0.0913969000, 0.2356017000, 0.6631085000", \ - "0.0171052000, 0.0201017000, 0.0270415000, 0.0444582000, 0.0910585000, 0.2347783000, 0.6656244000", \ - "0.0170238000, 0.0200991000, 0.0271344000, 0.0445470000, 0.0911988000, 0.2341863000, 0.6609164000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014545500, 0.0042314000, 0.0123095000, 0.0358096000, 0.1041730000, 0.3030490000"); - values("0.0207924000, 0.0250128000, 0.0372263000, 0.0737691000, 0.1870318000, 0.5211080000, 1.4975174000", \ - "0.0208246000, 0.0251676000, 0.0372314000, 0.0737100000, 0.1870793000, 0.5211611000, 1.5014349000", \ - "0.0207863000, 0.0250060000, 0.0371499000, 0.0737817000, 0.1865098000, 0.5218005000, 1.5035291000", \ - "0.0208196000, 0.0250770000, 0.0372513000, 0.0737636000, 0.1868316000, 0.5215758000, 1.4992965000", \ - "0.0207773000, 0.0249961000, 0.0372319000, 0.0737688000, 0.1867752000, 0.5217680000, 1.4988655000", \ - "0.0208188000, 0.0251549000, 0.0372389000, 0.0736757000, 0.1868050000, 0.5219233000, 1.5032332000", \ - "0.0208355000, 0.0251925000, 0.0373854000, 0.0737629000, 0.1869371000, 0.5206598000, 1.4994747000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dfxtp_4") { - leakage_power () { - value : 0.0083293000; - when : "CLK&!D&Q"; - } - leakage_power () { - value : 0.0080413000; - when : "!CLK&D&Q"; - } - leakage_power () { - value : 0.0100255000; - when : "!CLK&D&!Q"; - } - leakage_power () { - value : 0.0088792000; - when : "CLK&!D&!Q"; - } - leakage_power () { - value : 0.0079211000; - when : "CLK&D&Q"; - } - leakage_power () { - value : 0.0082837000; - when : "!CLK&!D&Q"; - } - leakage_power () { - value : 0.0099385000; - when : "CLK&D&!Q"; - } - leakage_power () { - value : 0.0088461000; - when : "!CLK&!D&!Q"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__dfxtp"; - cell_leakage_power : 0.0087830730; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017750000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0215156000, 0.0214006000, 0.0211353000, 0.0212090000, 0.0213791000, 0.0217709000, 0.0226744000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163159000, 0.0161908000, 0.0159023000, 0.0159198000, 0.0159602000, 0.0160533000, 0.0162681000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018480000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2016414000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1895578000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049067000, 0.0048332000, 0.0046638000, 0.0047201000, 0.0048498000, 0.0051487000, 0.0058380000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("4.5862743e-06, -5.9611988e-05, -0.000207600, -0.000158700, -4.6108282e-05, 0.0002135000, 0.0008119000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015970000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1045391000, 0.3187643000, 0.6145814000", \ - "-0.005926400, 0.2021953000, 0.4943503000", \ - "-0.085679000, 0.1187806000, 0.4060527000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0569316000, 0.1747214000, 0.2569154000", \ - "-0.014471400, 0.0886699000, 0.1562155000", \ - "-0.042954400, 0.0553040000, 0.1167461000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.038283200, -0.237860000, -0.486069600", \ - "0.0648581000, -0.134718700, -0.396356100", \ - "0.1336244000, -0.062290400, -0.327589900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.028517600, -0.131658800, -0.185776700", \ - "0.0343405000, -0.061476600, -0.115594400", \ - "0.0567201000, -0.037876300, -0.091994100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016047860, 0.0051506790, 0.0165314800, 0.0530589900, 0.1702967000, 0.5465797000"); - values("0.0325915000, 0.0308688000, 0.0255683000, 0.0092707000, -0.046987400, -0.235887600, -0.845214800", \ - "0.0325283000, 0.0309160000, 0.0255453000, 0.0092825000, -0.046977600, -0.235860400, -0.845192200", \ - "0.0326638000, 0.0309763000, 0.0256880000, 0.0094334000, -0.046863500, -0.235767900, -0.845093000", \ - "0.0322145000, 0.0304730000, 0.0252135000, 0.0089116000, -0.047353200, -0.236251200, -0.845550100", \ - "0.0319152000, 0.0302867000, 0.0249496000, 0.0086724000, -0.047567300, -0.236471200, -0.845805000", \ - "0.0320546000, 0.0303536000, 0.0249884000, 0.0088424000, -0.047508100, -0.236396500, -0.845744200", \ - "0.0368505000, 0.0351573000, 0.0297109000, 0.0120326000, -0.046139000, -0.235628000, -0.845086200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016047860, 0.0051506790, 0.0165314800, 0.0530589900, 0.1702967000, 0.5465797000"); - values("0.0360772000, 0.0380032000, 0.0440492000, 0.0631591000, 0.1223195000, 0.3099228000, 0.9141283000", \ - "0.0360516000, 0.0380029000, 0.0440639000, 0.0631722000, 0.1223545000, 0.3099230000, 0.9194788000", \ - "0.0362177000, 0.0381220000, 0.0441914000, 0.0632922000, 0.1224452000, 0.3101700000, 0.9170330000", \ - "0.0357324000, 0.0376431000, 0.0437066000, 0.0628049000, 0.1219554000, 0.3095204000, 0.9134385000", \ - "0.0353261000, 0.0372813000, 0.0433476000, 0.0624429000, 0.1215846000, 0.3090473000, 0.9103406000", \ - "0.0352455000, 0.0371233000, 0.0432971000, 0.0624707000, 0.1215812000, 0.3087925000, 0.9140495000", \ - "0.0371598000, 0.0389855000, 0.0448687000, 0.0636276000, 0.1229831000, 0.3110095000, 0.9114014000"); - } - } - max_capacitance : 0.5465800000; - max_transition : 1.5072410000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016047900, 0.0051506800, 0.0165315000, 0.0530590000, 0.1702970000, 0.5465800000"); - values("0.3049624000, 0.3085415000, 0.3178988000, 0.3386857000, 0.3829389000, 0.4904024000, 0.8119742000", \ - "0.3096234000, 0.3132014000, 0.3225409000, 0.3434068000, 0.3876060000, 0.4950955000, 0.8173437000", \ - "0.3208047000, 0.3243626000, 0.3336722000, 0.3545471000, 0.3986181000, 0.5062199000, 0.8284514000", \ - "0.3464531000, 0.3500527000, 0.3594342000, 0.3802832000, 0.4244696000, 0.5319589000, 0.8549259000", \ - "0.3926958000, 0.3962367000, 0.4055965000, 0.4264785000, 0.4706843000, 0.5781396000, 0.9009751000", \ - "0.4571456000, 0.4606838000, 0.4700447000, 0.4909137000, 0.5352387000, 0.6426148000, 0.9648238000", \ - "0.5352493000, 0.5388660000, 0.5481988000, 0.5690108000, 0.6132437000, 0.7207601000, 1.0424230000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016047900, 0.0051506800, 0.0165315000, 0.0530590000, 0.1702970000, 0.5465800000"); - values("0.3036754000, 0.3076816000, 0.3183963000, 0.3450651000, 0.4173999000, 0.6421093000, 1.3662941000", \ - "0.3082892000, 0.3123284000, 0.3230377000, 0.3496917000, 0.4220244000, 0.6467577000, 1.3692040000", \ - "0.3193385000, 0.3232853000, 0.3340500000, 0.3607293000, 0.4330705000, 0.6577638000, 1.3819251000", \ - "0.3449731000, 0.3489183000, 0.3596802000, 0.3863653000, 0.4587125000, 0.6833926000, 1.4076605000", \ - "0.3922779000, 0.3963088000, 0.4070815000, 0.4337645000, 0.5061230000, 0.7307539000, 1.4492644000", \ - "0.4599940000, 0.4640512000, 0.4748102000, 0.5014663000, 0.5737781000, 0.7984674000, 1.5172652000", \ - "0.5475814000, 0.5515320000, 0.5623177000, 0.5890354000, 0.6614193000, 0.8859746000, 1.6055151000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016047900, 0.0051506800, 0.0165315000, 0.0530590000, 0.1702970000, 0.5465800000"); - values("0.0248724000, 0.0270659000, 0.0328093000, 0.0472901000, 0.0868302000, 0.2110268000, 0.6402268000", \ - "0.0249009000, 0.0271889000, 0.0327922000, 0.0474050000, 0.0870755000, 0.2106803000, 0.6343376000", \ - "0.0248607000, 0.0270856000, 0.0328353000, 0.0474125000, 0.0868028000, 0.2105795000, 0.6343514000", \ - "0.0251094000, 0.0271272000, 0.0330610000, 0.0477060000, 0.0870384000, 0.2107602000, 0.6364916000", \ - "0.0249102000, 0.0271312000, 0.0330175000, 0.0473735000, 0.0870776000, 0.2107678000, 0.6408650000", \ - "0.0249287000, 0.0271549000, 0.0328394000, 0.0476896000, 0.0862904000, 0.2106304000, 0.6355685000", \ - "0.0251143000, 0.0271376000, 0.0330894000, 0.0473594000, 0.0869250000, 0.2105509000, 0.6342062000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016047900, 0.0051506800, 0.0165315000, 0.0530590000, 0.1702970000, 0.5465800000"); - values("0.0253058000, 0.0285074000, 0.0372656000, 0.0650833000, 0.1600722000, 0.4768411000, 1.5051608000", \ - "0.0255086000, 0.0283707000, 0.0372961000, 0.0650920000, 0.1599277000, 0.4764398000, 1.5072412000", \ - "0.0252954000, 0.0284443000, 0.0372562000, 0.0650629000, 0.1600551000, 0.4769070000, 1.5031556000", \ - "0.0252985000, 0.0284381000, 0.0372488000, 0.0650498000, 0.1600406000, 0.4769751000, 1.5048108000", \ - "0.0255825000, 0.0284138000, 0.0373266000, 0.0650019000, 0.1599855000, 0.4772211000, 1.4988961000", \ - "0.0255681000, 0.0284190000, 0.0372491000, 0.0650777000, 0.1597754000, 0.4765168000, 1.5062674000", \ - "0.0254853000, 0.0285354000, 0.0374050000, 0.0651745000, 0.1598625000, 0.4772151000, 1.5028120000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__diode_2") { - leakage_power () { - value : 9.4057935e-06; - when : "DIODE"; - } - leakage_power () { - value : 3.2710485e-06; - when : "!DIODE"; - } - area : 2.5024000000; - cell_footprint : "sky130_fd_sc_hd__diode"; - cell_leakage_power : 6.338421e-06; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("DIODE") { - capacitance : 0.0008780000; - direction : "input"; - fall_capacitance : 0.0008570000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0006468000, 0.0006511000, 0.0006611000, 0.0006633000, 0.0006685000, 0.0006804000, 0.0007080000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000643900, -0.000647900, -0.000657400, -0.000659800, -0.000665400, -0.000678400, -0.000708200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0009000000; - } - } - - cell ("sky130_fd_sc_hd__dlclkp_1") { - leakage_power () { - value : 0.0088174000; - when : "!CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0048565000; - when : "CLK&GATE&GCLK"; - } - leakage_power () { - value : 0.0109370000; - when : "!CLK&!GATE&!GCLK"; - } - leakage_power () { - value : 0.0117618000; - when : "CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0050974000; - when : "CLK&!GATE&GCLK"; - } - leakage_power () { - value : 0.0113947000; - when : "CLK&!GATE&!GCLK"; - } - clock_gating_integrated_cell : "latch_posedge"; - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__dlclkp"; - cell_leakage_power : 0.0088107860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0041510000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0040020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0200236000, 0.0199046000, 0.0196302000, 0.0196958000, 0.0198467000, 0.0201949000, 0.0209974000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0063223000, 0.0062238000, 0.0059968000, 0.0060155000, 0.0060584000, 0.0061578000, 0.0063867000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043010000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1328031000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0017780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0214934000, 0.0214346000, 0.0212990000, 0.0213283000, 0.0213956000, 0.0215508000, 0.0219086000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0131737000, 0.0131189000, 0.0129925000, 0.0130067000, 0.0130394000, 0.0131147000, 0.0132886000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017250000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1265117000, 0.2748190000, 0.4790833000", \ - "0.0184876000, 0.1655742000, 0.3698385000", \ - "-0.044175100, 0.1053529000, 0.3083965000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1008770000, 0.2198874000, 0.3240541000", \ - "0.0416810000, 0.1521465000, 0.2477682000", \ - "0.0876608000, 0.1956849000, 0.2900859000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.121291000, -0.269598300, -0.471421200", \ - "-0.014487600, -0.161574200, -0.365838500", \ - "0.0493958000, -0.100132200, -0.303175800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.054152300, -0.171942100, -0.265122400", \ - "-0.013266900, -0.115187500, -0.198602200", \ - "-0.020184200, -0.117222000, -0.193312500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0067229000, 0.0058168000, 0.0031969000, -0.005001700, -0.027517700, -0.086202000, -0.238504400", \ - "0.0067649000, 0.0058430000, 0.0032151000, -0.004987600, -0.027479400, -0.086153000, -0.238424600", \ - "0.0066597000, 0.0057395000, 0.0031010000, -0.005089700, -0.027564900, -0.086219200, -0.238490100", \ - "0.0062559000, 0.0053268000, 0.0026772000, -0.005472300, -0.027968900, -0.086624800, -0.238920900", \ - "0.0060819000, 0.0050556000, 0.0023617000, -0.005752000, -0.028159800, -0.086762900, -0.239001700", \ - "0.0073388000, 0.0059187000, 0.0027159000, -0.006055900, -0.027854500, -0.086459100, -0.238729700", \ - "0.0086876000, 0.0070613000, 0.0038209000, -0.005016500, -0.027554000, -0.084610300, -0.237890400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0120474000, 0.0135513000, 0.0171209000, 0.0258402000, 0.0480501000, 0.1060835000, 0.2563545000", \ - "0.0119327000, 0.0134393000, 0.0170138000, 0.0257401000, 0.0482058000, 0.1057521000, 0.2565315000", \ - "0.0114695000, 0.0129867000, 0.0165593000, 0.0252946000, 0.0476011000, 0.1053263000, 0.2569889000", \ - "0.0108717000, 0.0124064000, 0.0160097000, 0.0247388000, 0.0471224000, 0.1049131000, 0.2566571000", \ - "0.0105495000, 0.0120468000, 0.0156809000, 0.0243720000, 0.0467302000, 0.1048751000, 0.2553687000", \ - "0.0112863000, 0.0126014000, 0.0159721000, 0.0245047000, 0.0468481000, 0.1044854000, 0.2554202000", \ - "0.0126817000, 0.0139388000, 0.0172474000, 0.0259440000, 0.0484080000, 0.1066281000, 0.2556529000"); - } - } - max_capacitance : 0.1529030000; - max_transition : 1.5003650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0934324000, 0.0989415000, 0.1103527000, 0.1333273000, 0.1832901000, 0.3055592000, 0.6213860000", \ - "0.0985372000, 0.1040539000, 0.1155050000, 0.1384999000, 0.1884634000, 0.3108188000, 0.6282738000", \ - "0.1116955000, 0.1171496000, 0.1286459000, 0.1515222000, 0.2015369000, 0.3239618000, 0.6413326000", \ - "0.1438246000, 0.1493082000, 0.1606968000, 0.1837974000, 0.2338758000, 0.3562452000, 0.6720567000", \ - "0.2138184000, 0.2198398000, 0.2319639000, 0.2558531000, 0.3063939000, 0.4289895000, 0.7462673000", \ - "0.3288199000, 0.3365620000, 0.3517825000, 0.3793492000, 0.4332444000, 0.5572185000, 0.8737972000", \ - "0.5101193000, 0.5204429000, 0.5411261000, 0.5761467000, 0.6371507000, 0.7639177000, 1.0810782000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0897527000, 0.0973261000, 0.1142261000, 0.1524466000, 0.2473108000, 0.4931102000, 1.1302784000", \ - "0.0938840000, 0.1014490000, 0.1183359000, 0.1565838000, 0.2515255000, 0.4970914000, 1.1356908000", \ - "0.1023934000, 0.1099451000, 0.1267402000, 0.1651060000, 0.2602208000, 0.5058461000, 1.1449741000", \ - "0.1212897000, 0.1288897000, 0.1457290000, 0.1841238000, 0.2795136000, 0.5253268000, 1.1642859000", \ - "0.1543105000, 0.1624340000, 0.1801642000, 0.2195254000, 0.3154445000, 0.5614010000, 1.1991143000", \ - "0.1979164000, 0.2075026000, 0.2272119000, 0.2681304000, 0.3645292000, 0.6110408000, 1.2496799000", \ - "0.2340375000, 0.2467056000, 0.2715200000, 0.3170557000, 0.4146233000, 0.6608738000, 1.2991628000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0191506000, 0.0231374000, 0.0326326000, 0.0550587000, 0.1135196000, 0.2736108000, 0.6935850000", \ - "0.0191360000, 0.0234294000, 0.0326149000, 0.0551269000, 0.1137869000, 0.2737110000, 0.6972602000", \ - "0.0191263000, 0.0233340000, 0.0325759000, 0.0551599000, 0.1137401000, 0.2735862000, 0.6960873000", \ - "0.0191015000, 0.0233451000, 0.0326224000, 0.0549382000, 0.1135810000, 0.2741875000, 0.6933072000", \ - "0.0224315000, 0.0263869000, 0.0352751000, 0.0568775000, 0.1143296000, 0.2737692000, 0.6984464000", \ - "0.0321605000, 0.0367288000, 0.0454431000, 0.0660669000, 0.1206767000, 0.2753028000, 0.6966428000", \ - "0.0480837000, 0.0537215000, 0.0642997000, 0.0848669000, 0.1346361000, 0.2816785000, 0.6946519000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0256547000, 0.0330676000, 0.0516186000, 0.1010925000, 0.2350363000, 0.5857898000, 1.4942272000", \ - "0.0257136000, 0.0330416000, 0.0515623000, 0.1011627000, 0.2350190000, 0.5857386000, 1.4969155000", \ - "0.0256596000, 0.0330375000, 0.0516967000, 0.1010816000, 0.2345687000, 0.5867690000, 1.5003654000", \ - "0.0260617000, 0.0333276000, 0.0519571000, 0.1012222000, 0.2343761000, 0.5865338000, 1.5001052000", \ - "0.0291988000, 0.0364306000, 0.0545710000, 0.1029330000, 0.2352977000, 0.5851809000, 1.4937868000", \ - "0.0367085000, 0.0438950000, 0.0603495000, 0.1062651000, 0.2363414000, 0.5860089000, 1.4943351000", \ - "0.0511156000, 0.0590263000, 0.0758242000, 0.1163475000, 0.2399148000, 0.5867489000, 1.4947801000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - statetable ("CLK GATE","M0") { - table : "L L : - : L,L H : - : H,H - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__dlclkp_2") { - leakage_power () { - value : 0.0110797000; - when : "CLK&!GATE&!GCLK"; - } - leakage_power () { - value : 0.0084447000; - when : "!CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0051329000; - when : "CLK&GATE&GCLK"; - } - leakage_power () { - value : 0.0106095000; - when : "!CLK&!GATE&!GCLK"; - } - leakage_power () { - value : 0.0114467000; - when : "CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0053727000; - when : "CLK&!GATE&GCLK"; - } - clock_gating_integrated_cell : "latch_posedge"; - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__dlclkp"; - cell_leakage_power : 0.0086810420; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0041320000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0039920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0200461000, 0.0199198000, 0.0196285000, 0.0196939000, 0.0198446000, 0.0201921000, 0.0209931000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0063649000, 0.0062686000, 0.0060467000, 0.0060681000, 0.0061176000, 0.0062316000, 0.0064945000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0042730000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1328031000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0018130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0214976000, 0.0214369000, 0.0212970000, 0.0213265000, 0.0213945000, 0.0215511000, 0.0219123000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0131525000, 0.0131013000, 0.0129833000, 0.0129905000, 0.0130073000, 0.0130458000, 0.0131347000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017560000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1265117000, 0.2748190000, 0.4790833000", \ - "0.0184876000, 0.1655742000, 0.3698385000", \ - "-0.044175100, 0.1041322000, 0.3071758000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1179668000, 0.2369772000, 0.3411439000", \ - "0.0465638000, 0.1582500000, 0.2550924000", \ - "0.0913229000, 0.1981263000, 0.2925274000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.112746100, -0.258612000, -0.453110700", \ - "-0.008384100, -0.155470700, -0.356072900", \ - "0.0518372000, -0.096470100, -0.298293000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.054152300, -0.171942100, -0.265122400", \ - "-0.013266900, -0.115187500, -0.198602200", \ - "-0.020184200, -0.117222000, -0.193312500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0111505000, 0.0097324000, 0.0058568000, -0.005701700, -0.042290900, -0.150381300, -0.464089300", \ - "0.0109747000, 0.0095435000, 0.0057091000, -0.005880300, -0.042466200, -0.150551500, -0.464239500", \ - "0.0108861000, 0.0094804000, 0.0056143000, -0.005949700, -0.042509100, -0.150593300, -0.464277900", \ - "0.0105917000, 0.0091748000, 0.0052943000, -0.006302000, -0.042828500, -0.150895100, -0.464514500", \ - "0.0102055000, 0.0087280000, 0.0047728000, -0.006872200, -0.043377100, -0.151350500, -0.464926300", \ - "0.0108737000, 0.0092745000, 0.0047683000, -0.007377100, -0.043470100, -0.151382000, -0.464932200", \ - "0.0140567000, 0.0124133000, 0.0076996000, -0.005375200, -0.042661400, -0.150205300, -0.463709400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0170466000, 0.0186854000, 0.0234230000, 0.0366374000, 0.0737430000, 0.1807708000, 0.4909925000", \ - "0.0169755000, 0.0186145000, 0.0233448000, 0.0365684000, 0.0740315000, 0.1804359000, 0.4905642000", \ - "0.0165659000, 0.0182119000, 0.0229517000, 0.0361703000, 0.0733511000, 0.1805681000, 0.4906244000", \ - "0.0160592000, 0.0176969000, 0.0224622000, 0.0356037000, 0.0727941000, 0.1800184000, 0.4900841000", \ - "0.0156986000, 0.0173142000, 0.0219976000, 0.0350964000, 0.0723187000, 0.1794263000, 0.4918416000", \ - "0.0165377000, 0.0180807000, 0.0225140000, 0.0352202000, 0.0724458000, 0.1788223000, 0.4899078000", \ - "0.0179458000, 0.0195052000, 0.0237526000, 0.0366115000, 0.0738748000, 0.1812683000, 0.4914332000"); - } - } - max_capacitance : 0.2957250000; - max_transition : 1.5045060000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1184943000, 0.1235255000, 0.1347324000, 0.1572425000, 0.2037316000, 0.3151603000, 0.6265858000", \ - "0.1238251000, 0.1288524000, 0.1400469000, 0.1626198000, 0.2091079000, 0.3204925000, 0.6328925000", \ - "0.1371823000, 0.1422203000, 0.1533887000, 0.1759417000, 0.2224863000, 0.3339095000, 0.6461667000", \ - "0.1692841000, 0.1743137000, 0.1854557000, 0.2079960000, 0.2545259000, 0.3660489000, 0.6779697000", \ - "0.2444859000, 0.2495946000, 0.2608111000, 0.2834645000, 0.3300591000, 0.4416844000, 0.7531878000", \ - "0.3806598000, 0.3873801000, 0.4017531000, 0.4289709000, 0.4798479000, 0.5936131000, 0.9046626000", \ - "0.5976756000, 0.6066577000, 0.6258123000, 0.6620485000, 0.7242211000, 0.8450186000, 1.1573026000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1084853000, 0.1148944000, 0.1298295000, 0.1635678000, 0.2471463000, 0.4812349000, 1.1574837000", \ - "0.1127414000, 0.1191644000, 0.1340882000, 0.1678311000, 0.2514383000, 0.4851942000, 1.1621657000", \ - "0.1214380000, 0.1279233000, 0.1428122000, 0.1765394000, 0.2601744000, 0.4943950000, 1.1706298000", \ - "0.1410739000, 0.1474779000, 0.1624033000, 0.1960403000, 0.2797601000, 0.5139840000, 1.1902880000", \ - "0.1796196000, 0.1864264000, 0.2021124000, 0.2367295000, 0.3209088000, 0.5562631000, 1.2336587000", \ - "0.2360711000, 0.2440683000, 0.2619503000, 0.2990819000, 0.3848843000, 0.6195088000, 1.2970428000", \ - "0.2943304000, 0.3048806000, 0.3276496000, 0.3714881000, 0.4612276000, 0.6967517000, 1.3718597000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0219558000, 0.0251180000, 0.0325859000, 0.0502564000, 0.0962613000, 0.2329225000, 0.6535134000", \ - "0.0219880000, 0.0251075000, 0.0324755000, 0.0502874000, 0.0963958000, 0.2325624000, 0.6478021000", \ - "0.0219574000, 0.0250314000, 0.0326250000, 0.0502290000, 0.0963424000, 0.2327031000, 0.6481388000", \ - "0.0220694000, 0.0251284000, 0.0323847000, 0.0502603000, 0.0960944000, 0.2332310000, 0.6466155000", \ - "0.0230524000, 0.0260213000, 0.0335134000, 0.0508712000, 0.0964263000, 0.2323113000, 0.6509604000", \ - "0.0346431000, 0.0379836000, 0.0453518000, 0.0620539000, 0.1043952000, 0.2361137000, 0.6530219000", \ - "0.0528265000, 0.0580091000, 0.0674357000, 0.0861784000, 0.1260914000, 0.2476145000, 0.6476134000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0251001000, 0.0303643000, 0.0438878000, 0.0811501000, 0.1925417000, 0.5280900000, 1.5033857000", \ - "0.0250494000, 0.0303528000, 0.0439070000, 0.0811386000, 0.1925022000, 0.5263642000, 1.5045060000", \ - "0.0252131000, 0.0303322000, 0.0439008000, 0.0810681000, 0.1924121000, 0.5277969000, 1.5028506000", \ - "0.0250168000, 0.0304187000, 0.0439116000, 0.0810428000, 0.1921518000, 0.5270677000, 1.5017199000", \ - "0.0279265000, 0.0330947000, 0.0465073000, 0.0829637000, 0.1932306000, 0.5271945000, 1.5036413000", \ - "0.0350547000, 0.0407513000, 0.0535664000, 0.0887582000, 0.1961492000, 0.5276971000, 1.5030456000", \ - "0.0489183000, 0.0560285000, 0.0704453000, 0.1026055000, 0.2024708000, 0.5297430000, 1.4994922000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - statetable ("CLK GATE","M0") { - table : "L L : - : L,L H : - : H,H - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__dlclkp_4") { - leakage_power () { - value : 0.0092819000; - when : "CLK&!GATE&!GCLK"; - } - leakage_power () { - value : 0.0086403000; - when : "!CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0064920000; - when : "CLK&GATE&GCLK"; - } - leakage_power () { - value : 0.0089863000; - when : "!CLK&!GATE&!GCLK"; - } - leakage_power () { - value : 0.0096416000; - when : "CLK&GATE&!GCLK"; - } - leakage_power () { - value : 0.0067385000; - when : "CLK&!GATE&GCLK"; - } - clock_gating_integrated_cell : "latch_posedge"; - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__dlclkp"; - cell_leakage_power : 0.0082967620; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0048780000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0046800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213887000, 0.0212279000, 0.0208572000, 0.0209169000, 0.0210546000, 0.0213718000, 0.0221033000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0062034000, 0.0059925000, 0.0055063000, 0.0055344000, 0.0055992000, 0.0057485000, 0.0060930000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050750000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1352442000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0016640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0215948000, 0.0215389000, 0.0214102000, 0.0214328000, 0.0214848000, 0.0216045000, 0.0218806000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0137748000, 0.0136876000, 0.0134864000, 0.0135045000, 0.0135462000, 0.0136423000, 0.0138640000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017030000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1228496000, 0.2711569000, 0.4766419000", \ - "0.0087220000, 0.1582500000, 0.3649557000", \ - "-0.060044300, 0.0907044000, 0.2961895000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1301738000, 0.2443014000, 0.3387025000", \ - "0.0575501000, 0.1667949000, 0.2563132000", \ - "0.1242819000, 0.2310853000, 0.3181621000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.250067100, -0.442124300", \ - "0.0013815000, -0.146925800, -0.347528000", \ - "0.0677064000, -0.083042300, -0.284865200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.048048800, -0.158514300, -0.240708300", \ - "-0.002280600, -0.098097700, -0.169305300", \ - "-0.003094400, -0.092807900, -0.159132800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015853940, 0.0050269460, 0.0159393800, 0.0505403800, 0.1602528000, 0.5081275000"); - values("0.0231340000, 0.0214432000, 0.0162470000, 0.0007161000, -0.052691800, -0.229350700, -0.792763400", \ - "0.0229125000, 0.0212223000, 0.0160397000, 0.0004795000, -0.052829500, -0.229597900, -0.792903700", \ - "0.0228452000, 0.0211322000, 0.0159593000, 0.0003646000, -0.052937100, -0.229648200, -0.792908900", \ - "0.0223538000, 0.0206911000, 0.0154470000, -0.000108000, -0.053486800, -0.230103200, -0.793379100", \ - "0.0219401000, 0.0202658000, 0.0148959000, -0.000874200, -0.054299700, -0.230751300, -0.793880800", \ - "0.0217676000, 0.0199319000, 0.0144279000, -0.001410300, -0.054595600, -0.230927500, -0.793837300", \ - "0.0291267000, 0.0270538000, 0.0209300000, 0.0030846000, -0.052964500, -0.229535700, -0.792301300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015853940, 0.0050269460, 0.0159393800, 0.0505403800, 0.1602528000, 0.5081275000"); - values("0.0299720000, 0.0318239000, 0.0377359000, 0.0560264000, 0.1119624000, 0.2875115000, 0.8492428000", \ - "0.0299884000, 0.0318596000, 0.0377257000, 0.0559641000, 0.1123099000, 0.2872654000, 0.8444050000", \ - "0.0297426000, 0.0315953000, 0.0374737000, 0.0557648000, 0.1118555000, 0.2875266000, 0.8437501000", \ - "0.0291438000, 0.0309911000, 0.0368314000, 0.0550685000, 0.1111498000, 0.2873425000, 0.8438186000", \ - "0.0286869000, 0.0304958000, 0.0363444000, 0.0543719000, 0.1105259000, 0.2866172000, 0.8435510000", \ - "0.0298760000, 0.0316304000, 0.0371936000, 0.0548679000, 0.1105038000, 0.2856628000, 0.8432418000", \ - "0.0315553000, 0.0332647000, 0.0386962000, 0.0561284000, 0.1121972000, 0.2878034000, 0.8418735000"); - } - } - max_capacitance : 0.5081280000; - max_transition : 1.5017540000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015853900, 0.0050269500, 0.0159394000, 0.0505404000, 0.1602530000, 0.5081280000"); - values("0.1365121000, 0.1401157000, 0.1493948000, 0.1699048000, 0.2124712000, 0.3131267000, 0.6075944000", \ - "0.1419779000, 0.1455898000, 0.1548702000, 0.1753753000, 0.2179292000, 0.3187276000, 0.6133442000", \ - "0.1553858000, 0.1590263000, 0.1682820000, 0.1887646000, 0.2313064000, 0.3321492000, 0.6265110000", \ - "0.1876677000, 0.1912914000, 0.2005200000, 0.2209875000, 0.2636030000, 0.3643498000, 0.6588604000", \ - "0.2642405000, 0.2678203000, 0.2770298000, 0.2974399000, 0.3400094000, 0.4408335000, 0.7352998000", \ - "0.4138821000, 0.4183846000, 0.4298724000, 0.4541912000, 0.5011085000, 0.6043144000, 0.8988235000", \ - "0.6571448000, 0.6629522000, 0.6781560000, 0.7107488000, 0.7703888000, 0.8840615000, 1.1803295000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015853900, 0.0050269500, 0.0159394000, 0.0505404000, 0.1602530000, 0.5081280000"); - values("0.1153459000, 0.1197899000, 0.1316226000, 0.1606825000, 0.2356789000, 0.4599420000, 1.1705690000", \ - "0.1195353000, 0.1239831000, 0.1358393000, 0.1648576000, 0.2399326000, 0.4636924000, 1.1722743000", \ - "0.1281046000, 0.1325391000, 0.1443628000, 0.1734126000, 0.2485603000, 0.4736887000, 1.1824324000", \ - "0.1473059000, 0.1518057000, 0.1635350000, 0.1926169000, 0.2676564000, 0.4917254000, 1.1996911000", \ - "0.1857574000, 0.1905030000, 0.2029281000, 0.2327556000, 0.3084868000, 0.5331848000, 1.2400438000", \ - "0.2404413000, 0.2459550000, 0.2601905000, 0.2926036000, 0.3702975000, 0.5952651000, 1.3068763000", \ - "0.2908642000, 0.2981106000, 0.3162473000, 0.3553940000, 0.4382132000, 0.6640830000, 1.3708404000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015853900, 0.0050269500, 0.0159394000, 0.0505404000, 0.1602530000, 0.5081280000"); - values("0.0257871000, 0.0278682000, 0.0333054000, 0.0470988000, 0.0845594000, 0.1995978000, 0.5869456000", \ - "0.0256080000, 0.0278998000, 0.0332893000, 0.0470517000, 0.0844089000, 0.1993295000, 0.5860922000", \ - "0.0257574000, 0.0277104000, 0.0334627000, 0.0475310000, 0.0844137000, 0.1994120000, 0.5900990000", \ - "0.0258076000, 0.0277043000, 0.0333034000, 0.0471115000, 0.0845081000, 0.1996212000, 0.5870081000", \ - "0.0258032000, 0.0282294000, 0.0335014000, 0.0474564000, 0.0846739000, 0.1991863000, 0.5900471000", \ - "0.0373286000, 0.0396093000, 0.0454139000, 0.0587301000, 0.0922627000, 0.2025004000, 0.5901272000", \ - "0.0585313000, 0.0611221000, 0.0686585000, 0.0854677000, 0.1184031000, 0.2188113000, 0.5886615000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015853900, 0.0050269500, 0.0159394000, 0.0505404000, 0.1602530000, 0.5081280000"); - values("0.0268697000, 0.0305235000, 0.0406607000, 0.0706337000, 0.1666507000, 0.4849159000, 1.5012790000", \ - "0.0269728000, 0.0303368000, 0.0407197000, 0.0707358000, 0.1667613000, 0.4842650000, 1.5017537000", \ - "0.0268940000, 0.0305159000, 0.0407467000, 0.0706944000, 0.1668747000, 0.4848292000, 1.5008620000", \ - "0.0270197000, 0.0304452000, 0.0407016000, 0.0705775000, 0.1667813000, 0.4841376000, 1.5009424000", \ - "0.0295425000, 0.0333041000, 0.0432672000, 0.0726717000, 0.1670911000, 0.4857061000, 1.4989288000", \ - "0.0371425000, 0.0406447000, 0.0508185000, 0.0790031000, 0.1708568000, 0.4848842000, 1.5017041000", \ - "0.0522749000, 0.0562613000, 0.0679949000, 0.0943823000, 0.1795943000, 0.4866853000, 1.4968929000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - statetable ("CLK GATE","M0") { - table : "L L : - : L,L H : - : H,H - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__dlrbn_1") { - leakage_power () { - value : 0.0142827000; - when : "RESET_B&D&!GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0086278000; - when : "RESET_B&!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0084244000; - when : "!RESET_B&!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0087070000; - when : "RESET_B&!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0141881000; - when : "RESET_B&D&GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0100020000; - when : "!RESET_B&D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0083453000; - when : "!RESET_B&!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0097945000; - when : "!RESET_B&D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0100771000; - when : "RESET_B&D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0133618000; - when : "RESET_B&!D&GATE_N&Q&!Q_N"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__dlrbn"; - cell_leakage_power : 0.0105810700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181954000, 0.0180800000, 0.0178139000, 0.0178912000, 0.0180695000, 0.0184805000, 0.0194281000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092137000, 0.0090667000, 0.0087280000, 0.0087931000, 0.0089430000, 0.0092889000, 0.0100863000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018800000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1167461000, 0.2772604000, 0.4473450000", \ - "0.0770814000, 0.2351543000, 0.4015768000", \ - "0.0974264000, 0.2493958000, 0.4133770000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1802227000, 0.2638327000, 0.2959779000", \ - "0.0612122000, 0.1448223000, 0.1769674000", \ - "-0.012436800, 0.0723939000, 0.1045391000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.264715500, -0.437241500", \ - "-0.055991500, -0.217726600, -0.387811200", \ - "-0.054363900, -0.214878300, -0.383742200"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.167677700, -0.252508500, -0.285874300", \ - "-0.048667300, -0.133498000, -0.166863900", \ - "0.0237611000, -0.062290400, -0.094435500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017710000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173765000, 0.0172514000, 0.0169632000, 0.0170148000, 0.0171335000, 0.0174074000, 0.0180387000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104453000, 0.0103119000, 0.0100042000, 0.0100452000, 0.0101394000, 0.0103569000, 0.0108582000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1467159000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("-0.006151700, -0.002143400, 0.0051317000, 0.0122296000, 0.0047961000, -0.046197400, -0.203133000", \ - "-0.006106700, -0.002105000, 0.0051224000, 0.0122055000, 0.0047417000, -0.046273100, -0.203214300", \ - "-0.005981900, -0.001994300, 0.0052099000, 0.0122432000, 0.0047262000, -0.046353500, -0.203298200", \ - "-0.006025200, -0.002041600, 0.0051555000, 0.0121714000, 0.0046372000, -0.046420200, -0.203378500", \ - "-0.006108900, -0.002124500, 0.0050898000, 0.0121144000, 0.0046042000, -0.046455700, -0.203397500", \ - "-0.006305000, -0.002305400, 0.0049233000, 0.0120128000, 0.0045235000, -0.046489000, -0.203411600", \ - "-0.006725700, -0.002652700, 0.0047501000, 0.0120678000, 0.0048433000, -0.046010300, -0.202851600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("-0.003492200, -0.001746500, 0.0025683000, 0.0129380000, 0.0375933000, 0.0996541000, 0.2619123000", \ - "-0.003433700, -0.001707400, 0.0025759000, 0.0128794000, 0.0376230000, 0.1000071000, 0.2609338000", \ - "-0.003274800, -0.001563300, 0.0026921000, 0.0129526000, 0.0376498000, 0.1000204000, 0.2608972000", \ - "-0.003315200, -0.001612300, 0.0025917000, 0.0128190000, 0.0373450000, 0.0997293000, 0.2617725000", \ - "-0.003393300, -0.001704800, 0.0024984000, 0.0127195000, 0.0372364000, 0.0991813000, 0.2601380000", \ - "-0.003552900, -0.001836900, 0.0024158000, 0.0127074000, 0.0373175000, 0.0997142000, 0.2607374000", \ - "-0.003878900, -0.002070100, 0.0023844000, 0.0129456000, 0.0377235000, 0.1002805000, 0.2619775000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("-0.005310400, -0.000692600, 0.0077862000, 0.0167317000, 0.0111165000, -0.038675300, -0.194938600", \ - "-0.005263000, -0.000658900, 0.0077792000, 0.0166808000, 0.0110293000, -0.038792600, -0.195055900", \ - "-0.005124800, -0.000531100, 0.0079158000, 0.0167676000, 0.0111144000, -0.038720400, -0.195037700", \ - "-0.005160000, -0.000587100, 0.0078062000, 0.0166022000, 0.0109122000, -0.038955300, -0.195275100", \ - "-0.005236200, -0.000681300, 0.0076799000, 0.0164337000, 0.0106538000, -0.039229900, -0.195593100", \ - "-0.005369900, -0.000809000, 0.0075419000, 0.0163327000, 0.0105712000, -0.039343500, -0.195634300", \ - "-0.005630600, -0.000993100, 0.0075175000, 0.0165032000, 0.0109823000, -0.038703800, -0.194968500"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("-0.006838100, -0.004050500, 0.0023493000, 0.0158541000, 0.0437019000, 0.1077794000, 0.2700278000", \ - "-0.006785800, -0.004013700, 0.0023568000, 0.0158236000, 0.0436302000, 0.1082388000, 0.2710761000", \ - "-0.006652400, -0.003895200, 0.0024449000, 0.0158525000, 0.0435742000, 0.1082390000, 0.2711823000", \ - "-0.006685000, -0.003937800, 0.0023813000, 0.0157711000, 0.0434992000, 0.1081019000, 0.2709463000", \ - "-0.006750600, -0.004012300, 0.0022936000, 0.0156507000, 0.0433314000, 0.1077021000, 0.2709517000", \ - "-0.006877400, -0.004124500, 0.0022082000, 0.0156187000, 0.0433593000, 0.1079749000, 0.2698900000", \ - "-0.007137700, -0.004303900, 0.0021923000, 0.0158027000, 0.0440191000, 0.1079105000, 0.2704192000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0006721000, 0.0045805000, 0.0116346000, 0.0184020000, 0.0105373000, -0.040765000, -0.197830500", \ - "0.0006433000, 0.0045415000, 0.0115716000, 0.0182758000, 0.0103878000, -0.040936600, -0.198040500", \ - "0.0005968000, 0.0044851000, 0.0114795000, 0.0181831000, 0.0102724000, -0.041064500, -0.198155000", \ - "0.0005779000, 0.0044361000, 0.0113887000, 0.0179993000, 0.0100274000, -0.041338200, -0.198462600", \ - "0.0005537000, 0.0043786000, 0.0112467000, 0.0177412000, 0.0096829000, -0.041721100, -0.198829200", \ - "0.0005663000, 0.0044134000, 0.0113213000, 0.0178408000, 0.0098176000, -0.041527300, -0.198619700", \ - "0.0006100000, 0.0045212000, 0.0115266000, 0.0181710000, 0.0103420000, -0.040807000, -0.197833600"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0026461000, 0.0034830000, 0.0059691000, 0.0135412000, 0.0353303000, 0.0958441000, 0.2570291000", \ - "0.0026682000, 0.0034976000, 0.0059761000, 0.0135339000, 0.0353168000, 0.0959100000, 0.2558507000", \ - "0.0027075000, 0.0035207000, 0.0059682000, 0.0134829000, 0.0352044000, 0.0951939000, 0.2538089000", \ - "0.0026802000, 0.0034513000, 0.0058178000, 0.0132316000, 0.0348922000, 0.0947710000, 0.2567670000", \ - "0.0026705000, 0.0034173000, 0.0057349000, 0.0131080000, 0.0347735000, 0.0948687000, 0.2550025000", \ - "0.0027000000, 0.0034829000, 0.0058738000, 0.0132309000, 0.0350168000, 0.0948852000, 0.2553239000", \ - "0.0027602000, 0.0036060000, 0.0061735000, 0.0136790000, 0.0357293000, 0.0963308000, 0.2552991000"); - } - } - max_capacitance : 0.1620580000; - max_transition : 1.5071620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2246003000, 0.2306840000, 0.2433703000, 0.2688721000, 0.3223961000, 0.4471543000, 0.7692333000", \ - "0.2295762000, 0.2356460000, 0.2483298000, 0.2737897000, 0.3273511000, 0.4520843000, 0.7741695000", \ - "0.2427911000, 0.2487882000, 0.2615040000, 0.2869482000, 0.3405033000, 0.4652503000, 0.7877085000", \ - "0.2739355000, 0.2800164000, 0.2927021000, 0.3182027000, 0.3717491000, 0.4964879000, 0.8185019000", \ - "0.3309679000, 0.3370283000, 0.3497412000, 0.3751791000, 0.4287365000, 0.5534821000, 0.8759519000", \ - "0.4198230000, 0.4259155000, 0.4385513000, 0.4639924000, 0.5175690000, 0.6423359000, 0.9645201000", \ - "0.5599375000, 0.5660027000, 0.5787085000, 0.6041837000, 0.6577838000, 0.7825547000, 1.1047240000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.3272303000, 0.3350791000, 0.3525234000, 0.3916769000, 0.4878145000, 0.7335194000, 1.3745708000", \ - "0.3315984000, 0.3396131000, 0.3570097000, 0.3961502000, 0.4923139000, 0.7382269000, 1.3812217000", \ - "0.3428537000, 0.3508690000, 0.3682669000, 0.4074146000, 0.5035834000, 0.7494648000, 1.3926262000", \ - "0.3639453000, 0.3718074000, 0.3890982000, 0.4282886000, 0.5244305000, 0.7699180000, 1.4130584000", \ - "0.3911531000, 0.3988949000, 0.4163265000, 0.4555170000, 0.5516574000, 0.7972433000, 1.4398688000", \ - "0.4219167000, 0.4300370000, 0.4474026000, 0.4865953000, 0.5826944000, 0.8285897000, 1.4747898000", \ - "0.4451113000, 0.4529306000, 0.4703334000, 0.5095449000, 0.6056882000, 0.8507935000, 1.4932511000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0209972000, 0.0254676000, 0.0350383000, 0.0586625000, 0.1167694000, 0.2726297000, 0.6993918000", \ - "0.0210826000, 0.0256590000, 0.0353758000, 0.0588615000, 0.1169373000, 0.2726822000, 0.6993734000", \ - "0.0211472000, 0.0253331000, 0.0354353000, 0.0587731000, 0.1167055000, 0.2727061000, 0.6994842000", \ - "0.0209935000, 0.0254747000, 0.0353491000, 0.0586607000, 0.1163674000, 0.2726583000, 0.6986604000", \ - "0.0210250000, 0.0253639000, 0.0351307000, 0.0586257000, 0.1167282000, 0.2727198000, 0.7032899000", \ - "0.0210510000, 0.0256073000, 0.0352549000, 0.0586605000, 0.1164992000, 0.2724022000, 0.7005151000", \ - "0.0210803000, 0.0256861000, 0.0352353000, 0.0587982000, 0.1168991000, 0.2725579000, 0.6951386000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0292717000, 0.0361986000, 0.0536976000, 0.1022388000, 0.2326295000, 0.5797399000, 1.5067443000", \ - "0.0293739000, 0.0361770000, 0.0537809000, 0.1023522000, 0.2325975000, 0.5814283000, 1.5002960000", \ - "0.0293983000, 0.0361655000, 0.0537920000, 0.1023412000, 0.2326681000, 0.5814060000, 1.4985237000", \ - "0.0290752000, 0.0361719000, 0.0537472000, 0.1022425000, 0.2325178000, 0.5800774000, 1.5055660000", \ - "0.0291702000, 0.0363019000, 0.0537045000, 0.1022357000, 0.2326599000, 0.5798492000, 1.5059440000", \ - "0.0294175000, 0.0363643000, 0.0536833000, 0.1022512000, 0.2324730000, 0.5805167000, 1.5047937000", \ - "0.0292284000, 0.0362557000, 0.0536318000, 0.1022838000, 0.2327822000, 0.5802110000, 1.4978444000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2509917000, 0.2571405000, 0.2699483000, 0.2955779000, 0.3492188000, 0.4740022000, 0.7959798000", \ - "0.2558462000, 0.2620158000, 0.2748373000, 0.3004853000, 0.3541185000, 0.4789050000, 0.8007784000", \ - "0.2684325000, 0.2745569000, 0.2873956000, 0.3130386000, 0.3666744000, 0.4914621000, 0.8135467000", \ - "0.2994331000, 0.3055735000, 0.3183871000, 0.3440315000, 0.3976689000, 0.5224480000, 0.8443592000", \ - "0.3663856000, 0.3725211000, 0.3853396000, 0.4109870000, 0.4646228000, 0.5893969000, 0.9115121000", \ - "0.4792036000, 0.4853339000, 0.4981866000, 0.5238047000, 0.5774922000, 0.7023106000, 1.0241403000", \ - "0.6536831000, 0.6598683000, 0.6727119000, 0.6984341000, 0.7521684000, 0.8770119000, 1.1989038000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.3881394000, 0.3961187000, 0.4136916000, 0.4529467000, 0.5491070000, 0.7942738000, 1.4389611000", \ - "0.3927518000, 0.4007648000, 0.4183201000, 0.4575737000, 0.5537416000, 0.7997051000, 1.4442900000", \ - "0.4055986000, 0.4135753000, 0.4311388000, 0.4703752000, 0.5665544000, 0.8123155000, 1.4543535000", \ - "0.4364599000, 0.4444405000, 0.4619985000, 0.5012485000, 0.5974337000, 0.8434015000, 1.4859886000", \ - "0.5025424000, 0.5104921000, 0.5280734000, 0.5673209000, 0.6635144000, 0.9093334000, 1.5508727000", \ - "0.6092328000, 0.6172109000, 0.6347928000, 0.6740641000, 0.7702424000, 1.0161586000, 1.6600501000", \ - "0.7724577000, 0.7804226000, 0.7979796000, 0.8372362000, 0.9334163000, 1.1789708000, 1.8215335000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0214443000, 0.0257356000, 0.0357062000, 0.0590523000, 0.1171257000, 0.2726356000, 0.7015032000", \ - "0.0215627000, 0.0258253000, 0.0354777000, 0.0590375000, 0.1168298000, 0.2726255000, 0.7026652000", \ - "0.0215580000, 0.0259871000, 0.0354480000, 0.0590402000, 0.1169226000, 0.2730138000, 0.6990180000", \ - "0.0213906000, 0.0258379000, 0.0357672000, 0.0590294000, 0.1169095000, 0.2728747000, 0.7011952000", \ - "0.0215831000, 0.0257006000, 0.0358047000, 0.0589949000, 0.1168417000, 0.2728720000, 0.7015292000", \ - "0.0215250000, 0.0260705000, 0.0358644000, 0.0589831000, 0.1171652000, 0.2726065000, 0.7036538000", \ - "0.0216974000, 0.0259766000, 0.0357712000, 0.0592340000, 0.1171543000, 0.2727004000, 0.6975199000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0290359000, 0.0360989000, 0.0537774000, 0.1023029000, 0.2327008000, 0.5800371000, 1.4992581000", \ - "0.0290669000, 0.0360541000, 0.0537217000, 0.1023566000, 0.2325888000, 0.5812102000, 1.5037938000", \ - "0.0289580000, 0.0359722000, 0.0537431000, 0.1023093000, 0.2327867000, 0.5797032000, 1.5054989000", \ - "0.0289144000, 0.0360224000, 0.0538419000, 0.1022993000, 0.2324767000, 0.5806629000, 1.5049062000", \ - "0.0289832000, 0.0360823000, 0.0537268000, 0.1023169000, 0.2327650000, 0.5794586000, 1.5054222000", \ - "0.0290149000, 0.0360945000, 0.0537585000, 0.1023309000, 0.2324873000, 0.5810031000, 1.4970503000", \ - "0.0289586000, 0.0360057000, 0.0538139000, 0.1022934000, 0.2326491000, 0.5787922000, 1.5045210000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1022504000, 0.1084151000, 0.1213788000, 0.1473862000, 0.2032100000, 0.3280659000, 0.6497936000", \ - "0.1075031000, 0.1137051000, 0.1266172000, 0.1526787000, 0.2085059000, 0.3333799000, 0.6550115000", \ - "0.1205816000, 0.1267616000, 0.1397271000, 0.1657950000, 0.2216588000, 0.3465206000, 0.6683030000", \ - "0.1528941000, 0.1590314000, 0.1719275000, 0.1980278000, 0.2539279000, 0.3788408000, 0.7003716000", \ - "0.2256518000, 0.2322494000, 0.2457242000, 0.2722824000, 0.3283805000, 0.4532757000, 0.7750176000", \ - "0.3487885000, 0.3577692000, 0.3754845000, 0.4076088000, 0.4679158000, 0.5930280000, 0.9147590000", \ - "0.5460804000, 0.5582388000, 0.5824551000, 0.6259012000, 0.6956782000, 0.8209573000, 1.1428116000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0959440000, 0.1035332000, 0.1204228000, 0.1588354000, 0.2539987000, 0.4989833000, 1.1450377000", \ - "0.1002647000, 0.1077533000, 0.1246616000, 0.1630589000, 0.2582953000, 0.5033760000, 1.1460920000", \ - "0.1086566000, 0.1162696000, 0.1331245000, 0.1715649000, 0.2669469000, 0.5120607000, 1.1562740000", \ - "0.1268202000, 0.1343443000, 0.1512052000, 0.1897531000, 0.2853819000, 0.5307005000, 1.1766609000", \ - "0.1584941000, 0.1663802000, 0.1841935000, 0.2238166000, 0.3199994000, 0.5648884000, 1.2069296000", \ - "0.1997819000, 0.2092593000, 0.2292380000, 0.2707175000, 0.3680342000, 0.6138954000, 1.2555662000", \ - "0.2287346000, 0.2415411000, 0.2668292000, 0.3141092000, 0.4141507000, 0.6603970000, 1.3020824000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0217972000, 0.0261528000, 0.0365761000, 0.0612748000, 0.1195496000, 0.2727391000, 0.7018577000", \ - "0.0219422000, 0.0265050000, 0.0365101000, 0.0613117000, 0.1195226000, 0.2725735000, 0.7018550000", \ - "0.0218328000, 0.0263580000, 0.0366216000, 0.0612686000, 0.1195073000, 0.2727252000, 0.7057393000", \ - "0.0217370000, 0.0261863000, 0.0365197000, 0.0612515000, 0.1194612000, 0.2725258000, 0.7037913000", \ - "0.0247335000, 0.0288708000, 0.0387765000, 0.0623740000, 0.1196348000, 0.2725797000, 0.7000080000", \ - "0.0357012000, 0.0411996000, 0.0511073000, 0.0743386000, 0.1258336000, 0.2734665000, 0.7004092000", \ - "0.0527727000, 0.0599200000, 0.0736585000, 0.0997452000, 0.1400443000, 0.2751947000, 0.6958372000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0270289000, 0.0339641000, 0.0520509000, 0.1012074000, 0.2322802000, 0.5815283000, 1.5063885000", \ - "0.0268310000, 0.0340303000, 0.0519177000, 0.1012583000, 0.2319827000, 0.5816209000, 1.5031977000", \ - "0.0268055000, 0.0339371000, 0.0518585000, 0.1011901000, 0.2320329000, 0.5805937000, 1.5004544000", \ - "0.0271629000, 0.0341678000, 0.0520401000, 0.1012080000, 0.2321469000, 0.5811296000, 1.5071620000", \ - "0.0300485000, 0.0374497000, 0.0548042000, 0.1030277000, 0.2329101000, 0.5809629000, 1.5014703000", \ - "0.0370242000, 0.0438259000, 0.0609320000, 0.1071315000, 0.2353570000, 0.5814062000, 1.4989102000", \ - "0.0508644000, 0.0590246000, 0.0771728000, 0.1188229000, 0.2390200000, 0.5824358000, 1.4954054000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002092700, 0.0013530000, 0.0075170000, 0.0129354000, 0.0033015000, -0.051157800, -0.215761200", \ - "-0.002031400, 0.0014043000, 0.0075309000, 0.0128839000, 0.0031797000, -0.051310800, -0.215923300", \ - "-0.001873200, 0.0015475000, 0.0076454000, 0.0129542000, 0.0032066000, -0.051319000, -0.215948700", \ - "-0.001912700, 0.0014858000, 0.0075726000, 0.0128566000, 0.0030631000, -0.051456000, -0.216100000", \ - "-0.001994000, 0.0014008000, 0.0074592000, 0.0127197000, 0.0029029000, -0.051656100, -0.216323900", \ - "-0.002151100, 0.0012665000, 0.0073761000, 0.0127139000, 0.0029697000, -0.051558800, -0.216205900", \ - "-0.002480900, 0.0010297000, 0.0073389000, 0.0129636000, 0.0034128000, -0.051048200, -0.215616600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.007637700, -0.005370900, 7.930000e-05, 0.0122305000, 0.0394547000, 0.1048105000, 0.2745308000", \ - "-0.007588500, -0.005337200, 7.730000e-05, 0.0122089000, 0.0392494000, 0.1051166000, 0.2747256000", \ - "-0.007463700, -0.005225200, 0.0001694000, 0.0122418000, 0.0394063000, 0.1044423000, 0.2744399000", \ - "-0.007506500, -0.005271100, 0.0001163000, 0.0121721000, 0.0393054000, 0.1048574000, 0.2743456000", \ - "-0.007591800, -0.005353700, 4.485000e-05, 0.0121139000, 0.0392738000, 0.1049769000, 0.2730550000", \ - "-0.007787100, -0.005535000, -9.46500e-05, 0.0120145000, 0.0390605000, 0.1050529000, 0.2732250000", \ - "-0.008199000, -0.005855900, -0.000289500, 0.0120677000, 0.0393335000, 0.1050047000, 0.2744450000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.005451000, -0.000970100, 0.0072832000, 0.0158534000, 0.0093781000, -0.043009700, -0.206588400", \ - "-0.005398300, -0.000933400, 0.0072885000, 0.0158244000, 0.0093006000, -0.043111900, -0.206704800", \ - "-0.005263300, -0.000810100, 0.0073892000, 0.0158579000, 0.0092650000, -0.043144800, -0.206755100", \ - "-0.005297300, -0.000854500, 0.0073215000, 0.0157759000, 0.0091646000, -0.043292900, -0.206912500", \ - "-0.005363200, -0.000928700, 0.0072336000, 0.0156603000, 0.0090253000, -0.043466400, -0.207093900", \ - "-0.005490100, -0.001042500, 0.0071441000, 0.0156202000, 0.0090362000, -0.043418400, -0.207029600", \ - "-0.005753800, -0.001230600, 0.0070992000, 0.0158022000, 0.0093460000, -0.042794900, -0.206324500"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.006803900, -0.003932700, 0.0027381000, 0.0167149000, 0.0455981000, 0.1129810000, 0.2826595000", \ - "-0.006752100, -0.003902000, 0.0027341000, 0.0167310000, 0.0456811000, 0.1128947000, 0.2816793000", \ - "-0.006613200, -0.003770500, 0.0028485000, 0.0167737000, 0.0456166000, 0.1128283000, 0.2820284000", \ - "-0.006652300, -0.003824000, 0.0027486000, 0.0166020000, 0.0454499000, 0.1119219000, 0.2824830000", \ - "-0.006726000, -0.003918800, 0.0026269000, 0.0164286000, 0.0451081000, 0.1116474000, 0.2819688000", \ - "-0.006859800, -0.004049100, 0.0025041000, 0.0163333000, 0.0450370000, 0.1121599000, 0.2824936000", \ - "-0.007113600, -0.004216200, 0.0024732000, 0.0165022000, 0.0454826000, 0.1119858000, 0.2832843000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0040548000, 0.0065860000, 0.0109067000, 0.0135343000, 0.0010860000, -0.055239000, -0.220786200", \ - "0.0040733000, 0.0065983000, 0.0109067000, 0.0134411000, 0.0009457000, -0.055291300, -0.220815400", \ - "0.0041152000, 0.0066260000, 0.0108992000, 0.0133801000, 0.0008270000, -0.055404900, -0.220997200", \ - "0.0040907000, 0.0065661000, 0.0107712000, 0.0132361000, 0.0006176000, -0.055853400, -0.221457500", \ - "0.0040818000, 0.0065405000, 0.0107006000, 0.0131305000, 0.0004572000, -0.056022000, -0.221639900", \ - "0.0040943000, 0.0065653000, 0.0107578000, 0.0131748000, 0.0004291000, -0.055935400, -0.221540200", \ - "0.0041516000, 0.0066942000, 0.0110080000, 0.0137001000, 0.0012489000, -0.055014200, -0.220671400"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.000826600, 0.0013217000, 0.0065592000, 0.0183953000, 0.0451458000, 0.1103414000, 0.2799217000", \ - "-0.000855000, 0.0012727000, 0.0064938000, 0.0182744000, 0.0449728000, 0.1101574000, 0.2783729000", \ - "-0.000906300, 0.0012113000, 0.0063862000, 0.0181229000, 0.0447725000, 0.1099428000, 0.2784322000", \ - "-0.000918000, 0.0011753000, 0.0063206000, 0.0180080000, 0.0446112000, 0.1101912000, 0.2791404000", \ - "-0.000942300, 0.0011203000, 0.0061873000, 0.0177854000, 0.0442586000, 0.1093805000, 0.2777776000", \ - "-0.000964600, 0.0010695000, 0.0061170000, 0.0176630000, 0.0440781000, 0.1091381000, 0.2773482000", \ - "-0.000892400, 0.0012557000, 0.0064324000, 0.0181600000, 0.0449115000, 0.1102439000, 0.2782175000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5047490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3801154000, 0.3852877000, 0.3963588000, 0.4194152000, 0.4717415000, 0.6051701000, 0.9582442000", \ - "0.3845446000, 0.3897514000, 0.4008008000, 0.4238319000, 0.4761029000, 0.6097922000, 0.9625931000", \ - "0.3958339000, 0.4010426000, 0.4120858000, 0.4351272000, 0.4874435000, 0.6210738000, 0.9738933000", \ - "0.4167515000, 0.4218856000, 0.4329559000, 0.4560171000, 0.5083434000, 0.6418480000, 0.9946964000", \ - "0.4438861000, 0.4490598000, 0.4601402000, 0.4831686000, 0.5354977000, 0.6690560000, 1.0215641000", \ - "0.4749519000, 0.4801464000, 0.4911951000, 0.5142591000, 0.5665781000, 0.7002087000, 1.0532690000", \ - "0.4980777000, 0.5032854000, 0.5143400000, 0.5373612000, 0.5896261000, 0.7233067000, 1.0756116000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2807298000, 0.2869790000, 0.3015961000, 0.3374137000, 0.4302076000, 0.6742254000, 1.3183223000", \ - "0.2857215000, 0.2919420000, 0.3064781000, 0.3421940000, 0.4349961000, 0.6796278000, 1.3222656000", \ - "0.2988717000, 0.3050967000, 0.3196205000, 0.3553513000, 0.4481739000, 0.6917126000, 1.3380469000", \ - "0.3300730000, 0.3363052000, 0.3509225000, 0.3867399000, 0.4795243000, 0.7235446000, 1.3674957000", \ - "0.3870341000, 0.3932888000, 0.4078752000, 0.4436710000, 0.5366432000, 0.7804752000, 1.4244832000", \ - "0.4758994000, 0.4821128000, 0.4966896000, 0.5323778000, 0.6251923000, 0.8694396000, 1.5137805000", \ - "0.6161230000, 0.6223443000, 0.6369278000, 0.6727305000, 0.7658267000, 1.0096760000, 1.6550288000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0171130000, 0.0213115000, 0.0307600000, 0.0543014000, 0.1183562000, 0.2941899000, 0.7705692000", \ - "0.0170446000, 0.0213605000, 0.0308390000, 0.0543580000, 0.1182652000, 0.2944771000, 0.7644678000", \ - "0.0170439000, 0.0214082000, 0.0308404000, 0.0542997000, 0.1180383000, 0.2943605000, 0.7643778000", \ - "0.0170992000, 0.0213158000, 0.0307587000, 0.0543273000, 0.1183702000, 0.2944563000, 0.7711833000", \ - "0.0171202000, 0.0213058000, 0.0307166000, 0.0541864000, 0.1183767000, 0.2945724000, 0.7634266000", \ - "0.0171509000, 0.0211577000, 0.0308332000, 0.0539894000, 0.1184085000, 0.2947934000, 0.7692701000", \ - "0.0170396000, 0.0212999000, 0.0308384000, 0.0543810000, 0.1182016000, 0.2945399000, 0.7606939000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0205997000, 0.0271489000, 0.0448810000, 0.0937481000, 0.2258714000, 0.5762824000, 1.4995262000", \ - "0.0205498000, 0.0271017000, 0.0448209000, 0.0937774000, 0.2257367000, 0.5756249000, 1.5006987000", \ - "0.0205167000, 0.0270949000, 0.0449189000, 0.0936995000, 0.2260474000, 0.5751327000, 1.5016829000", \ - "0.0206147000, 0.0271483000, 0.0448813000, 0.0937525000, 0.2258319000, 0.5753866000, 1.5010662000", \ - "0.0206088000, 0.0271628000, 0.0449597000, 0.0938010000, 0.2260434000, 0.5757805000, 1.5022940000", \ - "0.0205391000, 0.0271260000, 0.0448388000, 0.0936410000, 0.2255600000, 0.5774792000, 1.4962886000", \ - "0.0205740000, 0.0270915000, 0.0448324000, 0.0938256000, 0.2255587000, 0.5738893000, 1.4965115000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4412629000, 0.4464550000, 0.4575042000, 0.4805640000, 0.5327826000, 0.6664347000, 1.0189551000", \ - "0.4458921000, 0.4510745000, 0.4620996000, 0.4851682000, 0.5374544000, 0.6711457000, 1.0241459000", \ - "0.4587231000, 0.4639200000, 0.4749525000, 0.4979421000, 0.5502782000, 0.6839374000, 1.0369072000", \ - "0.4895996000, 0.4947852000, 0.5058238000, 0.5288642000, 0.5811958000, 0.7149232000, 1.0670670000", \ - "0.5556453000, 0.5608464000, 0.5718832000, 0.5949437000, 0.6472828000, 0.7807857000, 1.1329659000", \ - "0.6623588000, 0.6675487000, 0.6785998000, 0.7016492000, 0.7538769000, 0.8875287000, 1.2400454000", \ - "0.8255172000, 0.8307164000, 0.8417280000, 0.8648339000, 0.9171582000, 1.0507915000, 1.4029460000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3074117000, 0.3136310000, 0.3282375000, 0.3639785000, 0.4570307000, 0.7009673000, 1.3452310000", \ - "0.3123342000, 0.3185025000, 0.3331096000, 0.3689753000, 0.4615584000, 0.7058743000, 1.3506363000", \ - "0.3248373000, 0.3310648000, 0.3457029000, 0.3814664000, 0.4744232000, 0.7187296000, 1.3615927000", \ - "0.3558789000, 0.3621436000, 0.3766294000, 0.4122850000, 0.5052520000, 0.7487093000, 1.3942928000", \ - "0.4228074000, 0.4290269000, 0.4436640000, 0.4794214000, 0.5724199000, 0.8171151000, 1.4589808000", \ - "0.5356702000, 0.5418791000, 0.5564508000, 0.5922793000, 0.6849392000, 0.9291765000, 1.5742690000", \ - "0.7102363000, 0.7164671000, 0.7311078000, 0.7668745000, 0.8598266000, 1.1041934000, 1.7484402000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0172945000, 0.0210871000, 0.0307983000, 0.0543034000, 0.1176986000, 0.2948076000, 0.7687350000", \ - "0.0170650000, 0.0212525000, 0.0305834000, 0.0542949000, 0.1180736000, 0.2943444000, 0.7611123000", \ - "0.0171358000, 0.0210873000, 0.0305851000, 0.0542364000, 0.1182832000, 0.2942327000, 0.7630241000", \ - "0.0171318000, 0.0210214000, 0.0305974000, 0.0542145000, 0.1181483000, 0.2942034000, 0.7729244000", \ - "0.0170417000, 0.0211513000, 0.0307583000, 0.0541984000, 0.1181398000, 0.2943475000, 0.7656615000", \ - "0.0172861000, 0.0210425000, 0.0306095000, 0.0541249000, 0.1177228000, 0.2948025000, 0.7686843000", \ - "0.0172724000, 0.0210485000, 0.0307261000, 0.0542828000, 0.1181285000, 0.2941231000, 0.7668715000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0205812000, 0.0271615000, 0.0449683000, 0.0938636000, 0.2260616000, 0.5751523000, 1.5041898000", \ - "0.0206011000, 0.0271695000, 0.0449399000, 0.0938421000, 0.2261464000, 0.5773306000, 1.4976046000", \ - "0.0206505000, 0.0272019000, 0.0448977000, 0.0938221000, 0.2263477000, 0.5769419000, 1.4979366000", \ - "0.0206020000, 0.0271416000, 0.0449477000, 0.0938241000, 0.2261304000, 0.5753750000, 1.4984581000", \ - "0.0206381000, 0.0271997000, 0.0449123000, 0.0938067000, 0.2261917000, 0.5768973000, 1.5047492000", \ - "0.0205721000, 0.0270084000, 0.0448607000, 0.0937994000, 0.2258391000, 0.5777020000, 1.4985181000", \ - "0.0206822000, 0.0272261000, 0.0448961000, 0.0938190000, 0.2261915000, 0.5732167000, 1.5017729000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.1481895000, 0.1533369000, 0.1644396000, 0.1874179000, 0.2397369000, 0.3732742000, 0.7252833000", \ - "0.1524190000, 0.1575329000, 0.1686119000, 0.1916963000, 0.2440080000, 0.3774551000, 0.7302863000", \ - "0.1609348000, 0.1660124000, 0.1770376000, 0.2001496000, 0.2523466000, 0.3859582000, 0.7381046000", \ - "0.1788897000, 0.1840952000, 0.1950899000, 0.2181347000, 0.2703874000, 0.4039916000, 0.7568127000", \ - "0.2120394000, 0.2172338000, 0.2283061000, 0.2515682000, 0.3038741000, 0.4372998000, 0.7898699000", \ - "0.2572627000, 0.2619333000, 0.2737723000, 0.2970744000, 0.3489407000, 0.4832083000, 0.8362595000", \ - "0.2962316000, 0.3016099000, 0.3133233000, 0.3373227000, 0.3897939000, 0.5235948000, 0.8756696000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.1595824000, 0.1658485000, 0.1804532000, 0.2162912000, 0.3092246000, 0.5533203000, 1.1977235000", \ - "0.1647875000, 0.1710450000, 0.1857367000, 0.2216505000, 0.3145486000, 0.5587846000, 1.2022560000", \ - "0.1780857000, 0.1843457000, 0.1989330000, 0.2347739000, 0.3276760000, 0.5716810000, 1.2147008000", \ - "0.2101383000, 0.2163287000, 0.2310386000, 0.2669998000, 0.3598529000, 0.6050336000, 1.2498814000", \ - "0.2843219000, 0.2905856000, 0.3051831000, 0.3411712000, 0.4338531000, 0.6780026000, 1.3217590000", \ - "0.4184992000, 0.4249652000, 0.4398833000, 0.4759946000, 0.5689201000, 0.8131444000, 1.4565823000", \ - "0.6353992000, 0.6422781000, 0.6578707000, 0.6941419000, 0.7871582000, 1.0312845000, 1.6764833000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0168963000, 0.0211262000, 0.0305935000, 0.0540968000, 0.1182631000, 0.2946041000, 0.7658267000", \ - "0.0169197000, 0.0211216000, 0.0306058000, 0.0542717000, 0.1181743000, 0.2942611000, 0.7698149000", \ - "0.0172004000, 0.0211233000, 0.0304523000, 0.0542581000, 0.1182289000, 0.2946038000, 0.7738871000", \ - "0.0169226000, 0.0211654000, 0.0306857000, 0.0541618000, 0.1181936000, 0.2941937000, 0.7719067000", \ - "0.0172784000, 0.0214361000, 0.0306074000, 0.0544454000, 0.1182889000, 0.2945832000, 0.7670998000", \ - "0.0177368000, 0.0220526000, 0.0314469000, 0.0546528000, 0.1185171000, 0.2932170000, 0.7691268000", \ - "0.0195905000, 0.0235641000, 0.0327509000, 0.0561915000, 0.1192680000, 0.2946283000, 0.7618375000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0207271000, 0.0272736000, 0.0451009000, 0.0940296000, 0.2258382000, 0.5751531000, 1.4980800000", \ - "0.0207975000, 0.0273324000, 0.0450930000, 0.0939169000, 0.2258528000, 0.5754206000, 1.4966417000", \ - "0.0207100000, 0.0272845000, 0.0451370000, 0.0939978000, 0.2259145000, 0.5749365000, 1.4937162000", \ - "0.0207644000, 0.0273721000, 0.0450803000, 0.0940409000, 0.2258604000, 0.5753997000, 1.4991652000", \ - "0.0208659000, 0.0274074000, 0.0451317000, 0.0939901000, 0.2255734000, 0.5758911000, 1.4986026000", \ - "0.0223838000, 0.0286835000, 0.0460608000, 0.0943730000, 0.2259101000, 0.5750365000, 1.4956408000", \ - "0.0259906000, 0.0323194000, 0.0483900000, 0.0954937000, 0.2256475000, 0.5738093000, 1.4976503000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0024650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044122000, 0.0044466000, 0.0045257000, 0.0045271000, 0.0045303000, 0.0045376000, 0.0045546000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004358900, -0.004404200, -0.004508600, -0.004510900, -0.004516200, -0.004528400, -0.004556400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025980000; - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.062697300, -0.004722000, -0.005535800", \ - "-0.178045600, -0.118849600, -0.118442700", \ - "-0.251694600, -0.191278000, -0.190871100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0789043000, 0.0197083000, 0.0193014000", \ - "0.1930319000, 0.1338359000, 0.1322083000", \ - "0.2679017000, 0.2050436000, 0.2046367000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1302382000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrbn_2") { - leakage_power () { - value : 0.0108737000; - when : "!RESET_B&D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0092184000; - when : "!RESET_B&!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0106677000; - when : "!RESET_B&D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0109512000; - when : "RESET_B&D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0135940000; - when : "RESET_B&!D&GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0145149000; - when : "RESET_B&D&!GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0095019000; - when : "RESET_B&!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0092976000; - when : "!RESET_B&!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0095810000; - when : "RESET_B&!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0144204000; - when : "RESET_B&D&GATE_N&Q&!Q_N"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__dlrbn"; - cell_leakage_power : 0.0112620800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181389000, 0.0180230000, 0.0177557000, 0.0178326000, 0.0180096000, 0.0184179000, 0.0193590000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092909000, 0.0091863000, 0.0089452000, 0.0090048000, 0.0091423000, 0.0094592000, 0.0101899000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018790000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1240703000, 0.2833639000, 0.4534486000", \ - "0.0819642000, 0.2388164000, 0.4064596000", \ - "0.1035300000, 0.2542786000, 0.4170391000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1948711000, 0.2784811000, 0.3106263000", \ - "0.0746400000, 0.1570293000, 0.1891745000", \ - "-0.001450500, 0.0821595000, 0.1143047000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.269598300, -0.442124300", \ - "-0.059653600, -0.221388700, -0.391473300", \ - "-0.059246700, -0.219761100, -0.388625000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.178664100, -0.263494800, -0.296860700", \ - "-0.059653600, -0.144484400, -0.176629600", \ - "0.0152161000, -0.070835300, -0.102980500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017750000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173037000, 0.0171758000, 0.0168811000, 0.0169425000, 0.0170840000, 0.0174104000, 0.0181628000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104272000, 0.0102935000, 0.0099855000, 0.0100270000, 0.0101225000, 0.0103430000, 0.0108512000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018580000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1555040000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("-0.006208300, -0.001573900, 0.0078467000, 0.0177267000, 0.0038858000, -0.086652500, -0.382371600", \ - "-0.006158400, -0.001524400, 0.0078684000, 0.0176227000, 0.0038124000, -0.086751000, -0.382498000", \ - "-0.006035100, -0.001410300, 0.0079508000, 0.0177112000, 0.0038471000, -0.086740200, -0.382481600", \ - "-0.006074600, -0.001456800, 0.0079102000, 0.0176607000, 0.0037298000, -0.086867500, -0.382625000", \ - "-0.006163200, -0.001539400, 0.0078384000, 0.0176054000, 0.0036863000, -0.086900100, -0.382642000", \ - "-0.006354300, -0.001722600, 0.0076731000, 0.0174666000, 0.0036363000, -0.086883000, -0.382564500", \ - "-0.006780200, -0.002074800, 0.0074813000, 0.0175566000, 0.0040685000, -0.086406300, -0.382042200"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("-0.003587300, -0.001643900, 0.0036377000, 0.0179890000, 0.0558263000, 0.1600859000, 0.4590790000", \ - "-0.003543500, -0.001615100, 0.0036648000, 0.0179431000, 0.0557960000, 0.1597019000, 0.4593262000", \ - "-0.003430500, -0.001513700, 0.0037360000, 0.0179672000, 0.0557740000, 0.1596037000, 0.4618387000", \ - "-0.003472900, -0.001571000, 0.0036431000, 0.0178250000, 0.0555061000, 0.1601909000, 0.4585739000", \ - "-0.003540000, -0.001641400, 0.0035696000, 0.0177487000, 0.0553725000, 0.1601165000, 0.4602914000", \ - "-0.003687800, -0.001765600, 0.0035020000, 0.0177569000, 0.0554523000, 0.1594719000, 0.4608911000", \ - "-0.003981000, -0.001944900, 0.0036029000, 0.0181592000, 0.0563075000, 0.1610233000, 0.4584438000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("-0.005462000, -0.000256000, 0.0103691000, 0.0221787000, 0.0104121000, -0.078846600, -0.374067000", \ - "-0.005404600, -0.000207300, 0.0104349000, 0.0222510000, 0.0104600000, -0.078885800, -0.373930600", \ - "-0.005266300, -7.84500e-05, 0.0105098000, 0.0222557000, 0.0103798000, -0.078935900, -0.374100800", \ - "-0.005299400, -0.000135600, 0.0104455000, 0.0221443000, 0.0101657000, -0.079180700, -0.374364500", \ - "-0.005380200, -0.000230900, 0.0103207000, 0.0219698000, 0.0099486000, -0.079460700, -0.374587300", \ - "-0.005543300, -0.000390400, 0.0101369000, 0.0217615000, 0.0098376000, -0.079522200, -0.374702800", \ - "-0.005887400, -0.000680700, 0.0099929000, 0.0218017000, 0.0101306000, -0.079172700, -0.374281000"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("-0.007033100, -0.004149700, 0.0032740000, 0.0209864000, 0.0622424000, 0.1693717000, 0.4708400000", \ - "-0.006977200, -0.004108000, 0.0032712000, 0.0209383000, 0.0621103000, 0.1686989000, 0.4712652000", \ - "-0.006836600, -0.003984500, 0.0033767000, 0.0209836000, 0.0621476000, 0.1685187000, 0.4690427000", \ - "-0.006873800, -0.004027000, 0.0033025000, 0.0208632000, 0.0620583000, 0.1684909000, 0.4708500000", \ - "-0.006949100, -0.004111700, 0.0032178000, 0.0207706000, 0.0618509000, 0.1688725000, 0.4706119000", \ - "-0.007104500, -0.004252100, 0.0030923000, 0.0207076000, 0.0619130000, 0.1681629000, 0.4711933000", \ - "-0.007420200, -0.004465500, 0.0031217000, 0.0209860000, 0.0622932000, 0.1685606000, 0.4713932000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0005844000, 0.0051262000, 0.0142936000, 0.0236391000, 0.0092179000, -0.081804300, -0.377753700", \ - "0.0005662000, 0.0051005000, 0.0142700000, 0.0236115000, 0.0091983000, -0.081863900, -0.377774400", \ - "0.0005203000, 0.0050380000, 0.0141657000, 0.0234334000, 0.0089833000, -0.082048700, -0.377911000", \ - "0.0005069000, 0.0050078000, 0.0140821000, 0.0232776000, 0.0087816000, -0.082268500, -0.378186600", \ - "0.0004882000, 0.0049572000, 0.0139354000, 0.0229632000, 0.0083745000, -0.082699100, -0.378615500", \ - "0.0004861000, 0.0049491000, 0.0138880000, 0.0228420000, 0.0081342000, -0.082925800, -0.378813800", \ - "0.0005420000, 0.0050966000, 0.0142188000, 0.0232760000, 0.0087529000, -0.082248100, -0.378112900"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0027524000, 0.0038582000, 0.0073286000, 0.0186541000, 0.0532959000, 0.1553417000, 0.4552877000", \ - "0.0027364000, 0.0038407000, 0.0072955000, 0.0185998000, 0.0532335000, 0.1552821000, 0.4535803000", \ - "0.0027003000, 0.0037901000, 0.0072155000, 0.0184569000, 0.0529879000, 0.1546424000, 0.4516539000", \ - "0.0026891000, 0.0037462000, 0.0070926000, 0.0182344000, 0.0527425000, 0.1548470000, 0.4527267000", \ - "0.0027001000, 0.0037490000, 0.0070770000, 0.0180746000, 0.0526307000, 0.1548538000, 0.4528870000", \ - "0.0027584000, 0.0038456000, 0.0072719000, 0.0182589000, 0.0527575000, 0.1548584000, 0.4562195000", \ - "0.0028832000, 0.0040307000, 0.0075882000, 0.0189530000, 0.0537999000, 0.1566179000, 0.4524672000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.4986490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2378108000, 0.2429029000, 0.2544590000, 0.2779692000, 0.3271603000, 0.4430739000, 0.7612790000", \ - "0.2427952000, 0.2478735000, 0.2594245000, 0.2829980000, 0.3321053000, 0.4480037000, 0.7660182000", \ - "0.2559655000, 0.2610544000, 0.2725666000, 0.2961473000, 0.3452547000, 0.4611554000, 0.7794861000", \ - "0.2872174000, 0.2922939000, 0.3038239000, 0.3273748000, 0.3765641000, 0.4924767000, 0.8106514000", \ - "0.3441464000, 0.3492324000, 0.3607574000, 0.3843040000, 0.4334974000, 0.5494120000, 0.8675765000", \ - "0.4330401000, 0.4381285000, 0.4496422000, 0.4733001000, 0.5224137000, 0.6383353000, 0.9564941000", \ - "0.5732805000, 0.5783345000, 0.5898790000, 0.6134434000, 0.6625770000, 0.7785421000, 1.0967077000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3421449000, 0.3488167000, 0.3640169000, 0.3985521000, 0.4840053000, 0.7187289000, 1.3939033000", \ - "0.3467528000, 0.3532985000, 0.3687385000, 0.4032011000, 0.4886185000, 0.7232778000, 1.3960629000", \ - "0.3580013000, 0.3645531000, 0.3799864000, 0.4144549000, 0.4998678000, 0.7345378000, 1.4073297000", \ - "0.3786828000, 0.3852643000, 0.4007110000, 0.4352402000, 0.5207105000, 0.7552027000, 1.4272193000", \ - "0.4060277000, 0.4126450000, 0.4279966000, 0.4625445000, 0.5479692000, 0.7824644000, 1.4549594000", \ - "0.4371535000, 0.4436855000, 0.4590371000, 0.4935917000, 0.5790161000, 0.8137211000, 1.4862951000", \ - "0.4596980000, 0.4662282000, 0.4816512000, 0.5161829000, 0.6016547000, 0.8362127000, 1.5063736000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0215630000, 0.0247741000, 0.0329708000, 0.0517854000, 0.1005459000, 0.2401010000, 0.6675936000", \ - "0.0215366000, 0.0249355000, 0.0330937000, 0.0518804000, 0.1003178000, 0.2400892000, 0.6629045000", \ - "0.0215086000, 0.0248387000, 0.0330585000, 0.0518895000, 0.1004506000, 0.2402265000, 0.6635986000", \ - "0.0215002000, 0.0251711000, 0.0328706000, 0.0517759000, 0.1005416000, 0.2400624000, 0.6643211000", \ - "0.0217881000, 0.0250660000, 0.0328756000, 0.0517926000, 0.1005476000, 0.2400606000, 0.6675786000", \ - "0.0218006000, 0.0250864000, 0.0328475000, 0.0519256000, 0.1004394000, 0.2401618000, 0.6674258000", \ - "0.0215783000, 0.0249419000, 0.0328177000, 0.0517446000, 0.1006832000, 0.2401927000, 0.6611970000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0282097000, 0.0334669000, 0.0473556000, 0.0844726000, 0.1968541000, 0.5269331000, 1.4967131000", \ - "0.0280826000, 0.0335892000, 0.0471194000, 0.0844700000, 0.1969163000, 0.5269806000, 1.4908210000", \ - "0.0280826000, 0.0335903000, 0.0471207000, 0.0844720000, 0.1969163000, 0.5270617000, 1.4909168000", \ - "0.0283198000, 0.0335858000, 0.0473391000, 0.0845118000, 0.1971959000, 0.5282640000, 1.4938495000", \ - "0.0283252000, 0.0335240000, 0.0472093000, 0.0844491000, 0.1970432000, 0.5264685000, 1.4929588000", \ - "0.0281733000, 0.0336551000, 0.0470663000, 0.0844874000, 0.1965903000, 0.5279612000, 1.4950895000", \ - "0.0283289000, 0.0336963000, 0.0473373000, 0.0845139000, 0.1972739000, 0.5283409000, 1.4908093000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2643328000, 0.2695295000, 0.2811503000, 0.3049295000, 0.3541503000, 0.4701310000, 0.7884156000", \ - "0.2692069000, 0.2743838000, 0.2860401000, 0.3098118000, 0.3590589000, 0.4750274000, 0.7930119000", \ - "0.2819226000, 0.2871250000, 0.2987432000, 0.3225507000, 0.3717772000, 0.4877464000, 0.8060426000", \ - "0.3126031000, 0.3177965000, 0.3294373000, 0.3531868000, 0.4024494000, 0.5184253000, 0.8362891000", \ - "0.3795199000, 0.3846787000, 0.3963451000, 0.4200892000, 0.4693647000, 0.5853427000, 0.9034799000", \ - "0.4925205000, 0.4977149000, 0.5093397000, 0.5330921000, 0.5823774000, 0.6983852000, 1.0164356000", \ - "0.6668838000, 0.6721150000, 0.6837632000, 0.7075740000, 0.7569018000, 0.8729255000, 1.1913385000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.4030007000, 0.4096488000, 0.4250068000, 0.4596781000, 0.5452004000, 0.7799237000, 1.4532827000", \ - "0.4075888000, 0.4142223000, 0.4296652000, 0.4642733000, 0.5498368000, 0.7845057000, 1.4585312000", \ - "0.4204433000, 0.4271034000, 0.4424838000, 0.4771282000, 0.5626630000, 0.7974137000, 1.4686756000", \ - "0.4513100000, 0.4579052000, 0.4733482000, 0.5079908000, 0.5935284000, 0.8282041000, 1.4988041000", \ - "0.5174304000, 0.5240043000, 0.5394393000, 0.5740850000, 0.6596518000, 0.8943798000, 1.5665014000", \ - "0.6241252000, 0.6307192000, 0.6461523000, 0.6808021000, 0.7663165000, 1.0009504000, 1.6723198000", \ - "0.7874130000, 0.7940295000, 0.8094518000, 0.8440973000, 0.9296461000, 1.1643742000, 1.8349641000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0219879000, 0.0253914000, 0.0331633000, 0.0520105000, 0.1005146000, 0.2408485000, 0.6637081000", \ - "0.0219306000, 0.0252805000, 0.0334665000, 0.0520761000, 0.1005307000, 0.2401920000, 0.6620480000", \ - "0.0219756000, 0.0253809000, 0.0332293000, 0.0521852000, 0.1007003000, 0.2402034000, 0.6677310000", \ - "0.0220952000, 0.0253758000, 0.0334626000, 0.0520639000, 0.1007308000, 0.2408061000, 0.6676075000", \ - "0.0221160000, 0.0253728000, 0.0331190000, 0.0520644000, 0.1007917000, 0.2400751000, 0.6668682000", \ - "0.0221289000, 0.0253812000, 0.0331336000, 0.0518575000, 0.1005168000, 0.2401128000, 0.6687396000", \ - "0.0223289000, 0.0253988000, 0.0333257000, 0.0523190000, 0.1006164000, 0.2407788000, 0.6624798000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0281157000, 0.0331967000, 0.0470562000, 0.0845603000, 0.1967760000, 0.5275037000, 1.4950514000", \ - "0.0281603000, 0.0333926000, 0.0470513000, 0.0846317000, 0.1965029000, 0.5273920000, 1.4928551000", \ - "0.0280904000, 0.0331745000, 0.0470712000, 0.0845388000, 0.1967931000, 0.5274970000, 1.4945954000", \ - "0.0280522000, 0.0333975000, 0.0470389000, 0.0845119000, 0.1967584000, 0.5275941000, 1.4962741000", \ - "0.0280937000, 0.0333180000, 0.0470147000, 0.0845926000, 0.1967456000, 0.5276077000, 1.4950277000", \ - "0.0280970000, 0.0333412000, 0.0470143000, 0.0845568000, 0.1970805000, 0.5274595000, 1.4986485000", \ - "0.0280598000, 0.0333527000, 0.0470539000, 0.0845976000, 0.1966870000, 0.5264745000, 1.4976986000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1174020000, 0.1227544000, 0.1347189000, 0.1590819000, 0.2103064000, 0.3262425000, 0.6436435000", \ - "0.1226884000, 0.1279835000, 0.1399921000, 0.1643765000, 0.2156296000, 0.3315740000, 0.6489746000", \ - "0.1356265000, 0.1409369000, 0.1529320000, 0.1773555000, 0.2286280000, 0.3445864000, 0.6621060000", \ - "0.1675341000, 0.1728407000, 0.1847465000, 0.2090916000, 0.2604483000, 0.3764428000, 0.6938412000", \ - "0.2421603000, 0.2475399000, 0.2596123000, 0.2840304000, 0.3355482000, 0.4515247000, 0.7690916000", \ - "0.3750771000, 0.3822660000, 0.3980671000, 0.4282267000, 0.4848709000, 0.6014536000, 0.9186962000", \ - "0.5873930000, 0.5969677000, 0.6183664000, 0.6589134000, 0.7292987000, 0.8479064000, 1.1649662000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1080250000, 0.1143536000, 0.1292203000, 0.1631211000, 0.2476526000, 0.4814314000, 1.1531285000", \ - "0.1122785000, 0.1186159000, 0.1334831000, 0.1673996000, 0.2519918000, 0.4859547000, 1.1575242000", \ - "0.1208482000, 0.1272272000, 0.1420951000, 0.1759831000, 0.2606342000, 0.4945031000, 1.1652623000", \ - "0.1397667000, 0.1460284000, 0.1608993000, 0.1947839000, 0.2795882000, 0.5137578000, 1.1854767000", \ - "0.1752395000, 0.1819873000, 0.1975726000, 0.2324946000, 0.3179717000, 0.5523855000, 1.2232072000", \ - "0.2244840000, 0.2325359000, 0.2501745000, 0.2876393000, 0.3750649000, 0.6104041000, 1.2835731000", \ - "0.2678657000, 0.2783763000, 0.3009697000, 0.3454425000, 0.4369826000, 0.6726210000, 1.3436908000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0230309000, 0.0265318000, 0.0344523000, 0.0543832000, 0.1040204000, 0.2393293000, 0.6617554000", \ - "0.0228443000, 0.0262761000, 0.0344534000, 0.0543808000, 0.1039589000, 0.2393303000, 0.6650275000", \ - "0.0232258000, 0.0263158000, 0.0344979000, 0.0543951000, 0.1038663000, 0.2393639000, 0.6668013000", \ - "0.0228346000, 0.0266428000, 0.0344261000, 0.0543735000, 0.1039548000, 0.2392987000, 0.6649168000", \ - "0.0243708000, 0.0277655000, 0.0354973000, 0.0552120000, 0.1039103000, 0.2392357000, 0.6669331000", \ - "0.0360740000, 0.0398342000, 0.0485762000, 0.0679059000, 0.1115706000, 0.2407920000, 0.6663969000", \ - "0.0542591000, 0.0594863000, 0.0715357000, 0.0947867000, 0.1316556000, 0.2441725000, 0.6610498000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0260714000, 0.0315515000, 0.0453414000, 0.0832847000, 0.1966728000, 0.5272365000, 1.4917083000", \ - "0.0260542000, 0.0315283000, 0.0453574000, 0.0832465000, 0.1965049000, 0.5270140000, 1.4966842000", \ - "0.0261201000, 0.0315021000, 0.0452967000, 0.0832942000, 0.1964307000, 0.5274470000, 1.4876698000", \ - "0.0262145000, 0.0315995000, 0.0452958000, 0.0832215000, 0.1965635000, 0.5274202000, 1.4940861000", \ - "0.0288313000, 0.0344069000, 0.0478634000, 0.0851710000, 0.1966689000, 0.5276403000, 1.4910574000", \ - "0.0356536000, 0.0414539000, 0.0553543000, 0.0904774000, 0.2002070000, 0.5285400000, 1.4960728000", \ - "0.0494880000, 0.0564085000, 0.0709820000, 0.1052343000, 0.2072041000, 0.5296046000, 1.4908869000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.002188000, 0.0019018000, 0.0101997000, 0.0179820000, 0.0004828000, -0.100761900, -0.429808700", \ - "-0.002139200, 0.0019433000, 0.0102230000, 0.0179645000, 0.0004365000, -0.100847700, -0.429899400", \ - "-0.002028100, 0.0020437000, 0.0102947000, 0.0179886000, 0.0004139000, -0.100901400, -0.429963500", \ - "-0.002067700, 0.0019833000, 0.0101964000, 0.0178532000, 0.0001813000, -0.101089600, -0.430207400", \ - "-0.002134600, 0.0019196000, 0.0101292000, 0.0177703000, 0.0001299000, -0.101170900, -0.430291700", \ - "-0.002282100, 0.0017876000, 0.0100434000, 0.0177742000, 0.0001992000, -0.101019100, -0.430109100", \ - "-0.002587900, 0.0015833000, 0.0100784000, 0.0181830000, 0.0007567000, -0.100564100, -0.429608000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.007799700, -0.005424900, 0.0010892000, 0.0177419000, 0.0597183000, 0.1747181000, 0.5090493000", \ - "-0.007750000, -0.005391700, 0.0010700000, 0.0176452000, 0.0597849000, 0.1741366000, 0.5090504000", \ - "-0.007623500, -0.005273700, 0.0011555000, 0.0177290000, 0.0596252000, 0.1747309000, 0.5092636000", \ - "-0.007662300, -0.005317000, 0.0011312000, 0.0176196000, 0.0595627000, 0.1753530000, 0.5070827000", \ - "-0.007748500, -0.005399100, 0.0010613000, 0.0176226000, 0.0595552000, 0.1745762000, 0.5092069000", \ - "-0.007945100, -0.005581400, 0.0008950000, 0.0174750000, 0.0594706000, 0.1745407000, 0.5062988000", \ - "-0.008348200, -0.005881000, 0.0007623000, 0.0175674000, 0.0597456000, 0.1751658000, 0.5092184000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.005654600, -0.000635600, 0.0097724000, 0.0210017000, 0.0069328000, -0.092163100, -0.420234900", \ - "-0.005597100, -0.000591800, 0.0097779000, 0.0209743000, 0.0068097000, -0.092266100, -0.420420500", \ - "-0.005457600, -0.000465900, 0.0098734000, 0.0210195000, 0.0068048000, -0.092301600, -0.420469300", \ - "-0.005494700, -0.000512500, 0.0098266000, 0.0209076000, 0.0066925000, -0.092446700, -0.420592600", \ - "-0.005570100, -0.000594100, 0.0097076000, 0.0207799000, 0.0065454000, -0.092626500, -0.420826500", \ - "-0.005726100, -0.000733700, 0.0096044000, 0.0207258000, 0.0065638000, -0.092578100, -0.420760000", \ - "-0.006052900, -0.000973600, 0.0095615000, 0.0210276000, 0.0068544000, -0.091918600, -0.420018000"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.007070300, -0.004152400, 0.0035853000, 0.0222161000, 0.0662386000, 0.1832342000, 0.5156061000", \ - "-0.007005800, -0.004090400, 0.0036466000, 0.0222454000, 0.0662680000, 0.1833924000, 0.5152014000", \ - "-0.006867800, -0.003968800, 0.0037284000, 0.0223086000, 0.0663891000, 0.1821414000, 0.5150387000", \ - "-0.006907900, -0.004026700, 0.0036317000, 0.0221315000, 0.0662145000, 0.1819428000, 0.5175879000", \ - "-0.006985100, -0.004113000, 0.0035226000, 0.0219945000, 0.0660019000, 0.1817458000, 0.5173868000", \ - "-0.007149000, -0.004284700, 0.0033390000, 0.0217965000, 0.0656433000, 0.1817176000, 0.5141735000", \ - "-0.007466800, -0.004512800, 0.0032228000, 0.0218151000, 0.0657915000, 0.1819267000, 0.5173836000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("0.0041778000, 0.0074465000, 0.0138878000, 0.0186739000, -0.001886500, -0.104980400, -0.434975000", \ - "0.0041627000, 0.0074319000, 0.0138674000, 0.0186186000, -0.001946800, -0.105017400, -0.435017500", \ - "0.0041221000, 0.0073650000, 0.0137392000, 0.0184201000, -0.002279300, -0.105359400, -0.435330000", \ - "0.0041152000, 0.0073383000, 0.0136645000, 0.0182338000, -0.002464200, -0.105671500, -0.435622500", \ - "0.0041226000, 0.0073187000, 0.0136153000, 0.0180821000, -0.002791200, -0.106030700, -0.435983800", \ - "0.0041627000, 0.0073908000, 0.0137167000, 0.0180686000, -0.002544700, -0.105891700, -0.436070000", \ - "0.0042743000, 0.0075689000, 0.0140009000, 0.0189027000, -0.001713700, -0.104653900, -0.434879800"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.001018200, 0.0012332000, 0.0074714000, 0.0236024000, 0.0652209000, 0.1807827000, 0.5109440000", \ - "-0.001042400, 0.0011913000, 0.0074095000, 0.0235132000, 0.0650362000, 0.1799178000, 0.5115972000", \ - "-0.001088300, 0.0011379000, 0.0073122000, 0.0233697000, 0.0648539000, 0.1795048000, 0.5110546000", \ - "-0.001099800, 0.0011084000, 0.0072578000, 0.0232469000, 0.0646266000, 0.1795778000, 0.5129134000", \ - "-0.001119800, 0.0010572000, 0.0071336000, 0.0230010000, 0.0642587000, 0.1791255000, 0.5124280000", \ - "-0.001135000, 0.0010248000, 0.0070581000, 0.0228080000, 0.0640682000, 0.1795325000, 0.5098674000", \ - "-0.001062200, 0.0012107000, 0.0073692000, 0.0233490000, 0.0648013000, 0.1796627000, 0.5110624000"); - } - } - max_capacitance : 0.3140360000; - max_transition : 1.5053990000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.4286606000, 0.4334144000, 0.4440618000, 0.4659587000, 0.5123955000, 0.6292741000, 0.9645803000", \ - "0.4332647000, 0.4380155000, 0.4486871000, 0.4705971000, 0.5170215000, 0.6338529000, 0.9690008000", \ - "0.4445172000, 0.4492670000, 0.4599406000, 0.4818519000, 0.5282753000, 0.6451026000, 0.9802548000", \ - "0.4653410000, 0.4701780000, 0.4807785000, 0.5026529000, 0.5491707000, 0.6658217000, 1.0008001000", \ - "0.4926450000, 0.4973893000, 0.5080413000, 0.5299419000, 0.5763718000, 0.6932475000, 1.0282517000", \ - "0.5235974000, 0.5283877000, 0.5390226000, 0.5607492000, 0.6073314000, 0.7239749000, 1.0582647000", \ - "0.5465974000, 0.5513198000, 0.5619912000, 0.5839006000, 0.6303169000, 0.7470736000, 1.0813666000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3239211000, 0.3292739000, 0.3419143000, 0.3717735000, 0.4519835000, 0.6837221000, 1.3614595000", \ - "0.3288306000, 0.3342225000, 0.3468190000, 0.3767100000, 0.4569732000, 0.6884410000, 1.3680990000", \ - "0.3419862000, 0.3473768000, 0.3599617000, 0.3898519000, 0.4698933000, 0.7012909000, 1.3787310000", \ - "0.3733502000, 0.3787025000, 0.3913068000, 0.4211983000, 0.5011330000, 0.7335071000, 1.4104755000", \ - "0.4302551000, 0.4356081000, 0.4482462000, 0.4780997000, 0.5581397000, 0.7892776000, 1.4667729000", \ - "0.5190974000, 0.5245011000, 0.5371660000, 0.5670786000, 0.6470713000, 0.8791666000, 1.5569354000", \ - "0.6593321000, 0.6647517000, 0.6773434000, 0.7073152000, 0.7875679000, 1.0185980000, 1.6966359000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0198841000, 0.0229701000, 0.0303201000, 0.0479967000, 0.0962756000, 0.2440620000, 0.6932089000", \ - "0.0198559000, 0.0230423000, 0.0302190000, 0.0479087000, 0.0960221000, 0.2438254000, 0.6894618000", \ - "0.0198607000, 0.0230492000, 0.0302083000, 0.0479017000, 0.0960071000, 0.2438137000, 0.6893801000", \ - "0.0197451000, 0.0229199000, 0.0300383000, 0.0480313000, 0.0958723000, 0.2432438000, 0.6938539000", \ - "0.0198776000, 0.0229795000, 0.0303009000, 0.0479769000, 0.0961271000, 0.2439267000, 0.6957499000", \ - "0.0199028000, 0.0229716000, 0.0300516000, 0.0477535000, 0.0960422000, 0.2436230000, 0.6971587000", \ - "0.0196325000, 0.0229909000, 0.0301758000, 0.0478684000, 0.0958824000, 0.2425090000, 0.6864470000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0207383000, 0.0251140000, 0.0371917000, 0.0731801000, 0.1848571000, 0.5176630000, 1.5006605000", \ - "0.0208080000, 0.0251306000, 0.0371710000, 0.0731783000, 0.1847275000, 0.5189139000, 1.5020264000", \ - "0.0207839000, 0.0251547000, 0.0372190000, 0.0731974000, 0.1849590000, 0.5190227000, 1.5000520000", \ - "0.0207470000, 0.0251524000, 0.0370796000, 0.0730396000, 0.1846261000, 0.5194911000, 1.5010461000", \ - "0.0207396000, 0.0251186000, 0.0371932000, 0.0731705000, 0.1849234000, 0.5191499000, 1.5029868000", \ - "0.0208830000, 0.0252321000, 0.0370534000, 0.0731008000, 0.1845675000, 0.5186268000, 1.4974488000", \ - "0.0207476000, 0.0250297000, 0.0371837000, 0.0731887000, 0.1850027000, 0.5176669000, 1.5007271000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.4897039000, 0.4944585000, 0.5051387000, 0.5269950000, 0.5734714000, 0.6902701000, 1.0253390000", \ - "0.4944974000, 0.4992645000, 0.5099309000, 0.5317196000, 0.5782800000, 0.6950924000, 1.0300538000", \ - "0.5070718000, 0.5118390000, 0.5225020000, 0.5442938000, 0.5908545000, 0.7076669000, 1.0426284000", \ - "0.5380931000, 0.5428638000, 0.5535485000, 0.5754525000, 0.6218895000, 0.7385878000, 1.0735982000", \ - "0.6040691000, 0.6087776000, 0.6194520000, 0.6412715000, 0.6876406000, 0.8042680000, 1.1392416000", \ - "0.7108352000, 0.7156014000, 0.7262868000, 0.7480462000, 0.7945722000, 0.9114033000, 1.2452607000", \ - "0.8739653000, 0.8787615000, 0.8894390000, 0.9112897000, 0.9577414000, 1.0745571000, 1.4086435000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3508231000, 0.3562621000, 0.3689187000, 0.3988138000, 0.4791478000, 0.7109920000, 1.3893675000", \ - "0.3557867000, 0.3612244000, 0.3738380000, 0.4036235000, 0.4840878000, 0.7160098000, 1.3947101000", \ - "0.3684918000, 0.3739194000, 0.3865697000, 0.4164605000, 0.4966762000, 0.7286454000, 1.4063419000", \ - "0.3992979000, 0.4047387000, 0.4173506000, 0.4472040000, 0.5275033000, 0.7588196000, 1.4363285000", \ - "0.4660782000, 0.4715098000, 0.4841627000, 0.5140562000, 0.5942564000, 0.8256116000, 1.5030512000", \ - "0.5790677000, 0.5844477000, 0.5971236000, 0.6270423000, 0.7072136000, 0.9391823000, 1.6180088000", \ - "0.7535956000, 0.7590014000, 0.7715892000, 0.8015467000, 0.8816910000, 1.1128692000, 1.7899264000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0196598000, 0.0227317000, 0.0299899000, 0.0480887000, 0.0958563000, 0.2439715000, 0.6954696000", \ - "0.0196677000, 0.0227966000, 0.0300050000, 0.0477340000, 0.0961633000, 0.2439395000, 0.6955108000", \ - "0.0196673000, 0.0227962000, 0.0300053000, 0.0477324000, 0.0961633000, 0.2439395000, 0.6955109000", \ - "0.0196726000, 0.0227240000, 0.0301624000, 0.0477891000, 0.0958498000, 0.2433274000, 0.6929301000", \ - "0.0196698000, 0.0229363000, 0.0300937000, 0.0479521000, 0.0955412000, 0.2434098000, 0.6889430000", \ - "0.0196014000, 0.0227510000, 0.0301697000, 0.0477935000, 0.0961152000, 0.2438839000, 0.6878012000", \ - "0.0199086000, 0.0227615000, 0.0300297000, 0.0479013000, 0.0958926000, 0.2437755000, 0.6920385000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0207494000, 0.0252018000, 0.0372340000, 0.0731214000, 0.1851450000, 0.5197487000, 1.5010101000", \ - "0.0206369000, 0.0251617000, 0.0371736000, 0.0732168000, 0.1852156000, 0.5190113000, 1.4963158000", \ - "0.0208275000, 0.0251530000, 0.0371691000, 0.0731523000, 0.1851346000, 0.5176927000, 1.5019819000", \ - "0.0206942000, 0.0251609000, 0.0371683000, 0.0732275000, 0.1851485000, 0.5182972000, 1.5053714000", \ - "0.0208360000, 0.0251221000, 0.0371716000, 0.0731811000, 0.1850910000, 0.5182964000, 1.5053992000", \ - "0.0208505000, 0.0250947000, 0.0371657000, 0.0732212000, 0.1849578000, 0.5192978000, 1.4986903000", \ - "0.0208518000, 0.0252124000, 0.0372747000, 0.0733502000, 0.1850366000, 0.5175271000, 1.5030612000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.1935860000, 0.1983474000, 0.2089850000, 0.2308445000, 0.2773391000, 0.3940339000, 0.7290691000", \ - "0.1978473000, 0.2026350000, 0.2132899000, 0.2351355000, 0.2815752000, 0.3983524000, 0.7327448000", \ - "0.2065075000, 0.2113065000, 0.2218973000, 0.2437066000, 0.2901967000, 0.4069264000, 0.7411483000", \ - "0.2250430000, 0.2298646000, 0.2404991000, 0.2623606000, 0.3087276000, 0.4256133000, 0.7606392000", \ - "0.2625677000, 0.2674823000, 0.2780046000, 0.2999298000, 0.3465534000, 0.4632603000, 0.7986400000", \ - "0.3179183000, 0.3228918000, 0.3336097000, 0.3551184000, 0.4023440000, 0.5193028000, 0.8532727000", \ - "0.3769521000, 0.3819381000, 0.3932329000, 0.4157374000, 0.4627611000, 0.5798776000, 0.9144917000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.2067050000, 0.2122148000, 0.2249506000, 0.2550740000, 0.3351570000, 0.5668689000, 1.2428288000", \ - "0.2119450000, 0.2174045000, 0.2301961000, 0.2602560000, 0.3403688000, 0.5719978000, 1.2492837000", \ - "0.2251310000, 0.2305981000, 0.2433455000, 0.2734433000, 0.3535572000, 0.5845853000, 1.2625475000", \ - "0.2566757000, 0.2621579000, 0.2749953000, 0.3051217000, 0.3850865000, 0.6167957000, 1.2966750000", \ - "0.3316452000, 0.3371338000, 0.3499681000, 0.3801079000, 0.4600491000, 0.6918003000, 1.3717372000", \ - "0.4810590000, 0.4867561000, 0.4998410000, 0.5300771000, 0.6102915000, 0.8418433000, 1.5183513000", \ - "0.7253738000, 0.7318799000, 0.7457092000, 0.7767308000, 0.8567745000, 1.0884160000, 1.7694014000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0197322000, 0.0227236000, 0.0300284000, 0.0479323000, 0.0959244000, 0.2437390000, 0.6924787000", \ - "0.0198250000, 0.0228898000, 0.0298702000, 0.0479048000, 0.0959739000, 0.2437440000, 0.6981372000", \ - "0.0197740000, 0.0226100000, 0.0302388000, 0.0479240000, 0.0959979000, 0.2437306000, 0.6979889000", \ - "0.0195323000, 0.0225239000, 0.0298567000, 0.0477084000, 0.0962120000, 0.2439207000, 0.6912044000", \ - "0.0197939000, 0.0227619000, 0.0299857000, 0.0478435000, 0.0959851000, 0.2433284000, 0.6918344000", \ - "0.0205143000, 0.0234513000, 0.0308635000, 0.0485784000, 0.0961650000, 0.2422823000, 0.6979582000", \ - "0.0219086000, 0.0250413000, 0.0320168000, 0.0498889000, 0.0973321000, 0.2443943000, 0.6897194000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0211758000, 0.0256721000, 0.0376963000, 0.0734123000, 0.1849882000, 0.5197414000, 1.4977458000", \ - "0.0213650000, 0.0258220000, 0.0377377000, 0.0735296000, 0.1847921000, 0.5195205000, 1.4973772000", \ - "0.0211682000, 0.0257196000, 0.0377563000, 0.0734104000, 0.1847645000, 0.5184713000, 1.4987952000", \ - "0.0214370000, 0.0258385000, 0.0376864000, 0.0734409000, 0.1849428000, 0.5191299000, 1.4994538000", \ - "0.0215290000, 0.0258517000, 0.0377423000, 0.0735287000, 0.1849280000, 0.5191463000, 1.4993180000", \ - "0.0227950000, 0.0272654000, 0.0388684000, 0.0739056000, 0.1850496000, 0.5193101000, 1.4978776000", \ - "0.0270609000, 0.0312379000, 0.0423667000, 0.0756636000, 0.1850645000, 0.5179843000, 1.4965644000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0024570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044247000, 0.0044577000, 0.0045338000, 0.0045353000, 0.0045387000, 0.0045467000, 0.0045653000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004384600, -0.004360900, -0.004306300, -0.004319300, -0.004349200, -0.004417800, -0.004576100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025960000; - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.049269500, 0.0184714000, 0.0335267000", \ - "-0.164617800, -0.095656300, -0.079380200", \ - "-0.239487600, -0.166863900, -0.151808600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0703594000, 0.0001771000, -0.017319700", \ - "0.1844870000, 0.1143047000, 0.0968079000", \ - "0.2593568000, 0.1867331000, 0.1692363000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1555040000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrbp_1") { - leakage_power () { - value : 0.0100815000; - when : "RESET_B&D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0133410000; - when : "RESET_B&!D&!GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142696000; - when : "RESET_B&D&GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0086193000; - when : "RESET_B&!D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0084161000; - when : "!RESET_B&!D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0086989000; - when : "RESET_B&!D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0141752000; - when : "RESET_B&D&!GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0099971000; - when : "!RESET_B&D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0097987000; - when : "!RESET_B&D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0083365000; - when : "!RESET_B&!D&!GATE&!Q&Q_N"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__dlrbp"; - cell_leakage_power : 0.0105733700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082995000, 0.0082066000, 0.0079926000, 0.0080632000, 0.0082260000, 0.0086014000, 0.0094668000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025778000, 0.0024425000, 0.0021306000, 0.0021911000, 0.0023305000, 0.0026520000, 0.0033932000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018810000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0422832000, 0.2027975000, 0.3728822000", \ - "-0.131658800, 0.0264141000, 0.1928366000", \ - "-0.311509100, -0.152215500, 0.0093242000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2107402000, 0.2943503000, 0.3277161000", \ - "0.1149232000, 0.1973125000, 0.2294577000", \ - "0.0571432000, 0.1358704000, 0.1643535000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.029738300, -0.191473300, -0.361557900", \ - "0.1442038000, -0.016310500, -0.183953800", \ - "0.3252747000, 0.1647604000, 0.0007793000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.198195300, -0.284246700, -0.316391900", \ - "-0.093833300, -0.179884800, -0.210809200", \ - "-0.004315100, -0.091587200, -0.123732400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017730000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173814000, 0.0172876000, 0.0170712000, 0.0171286000, 0.0172610000, 0.0175662000, 0.0182697000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101802000, 0.0100507000, 0.0097523000, 0.0097868000, 0.0098664000, 0.0100499000, 0.0104731000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018540000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1774742000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.001214600, 0.0027695000, 0.0099716000, 0.0170185000, 0.0096234000, -0.041120200, -0.197081200", \ - "-0.001182300, 0.0027922000, 0.0099777000, 0.0169741000, 0.0095018000, -0.041290600, -0.197204300", \ - "-0.001082500, 0.0028748000, 0.0100262000, 0.0170051000, 0.0094843000, -0.041300800, -0.197253100", \ - "-0.001122700, 0.0028340000, 0.0099961000, 0.0169422000, 0.0093820000, -0.041413500, -0.197396200", \ - "-0.001198500, 0.0027549000, 0.0099207000, 0.0168681000, 0.0093432000, -0.041433400, -0.197406100", \ - "-0.001377400, 0.0025996000, 0.0097813000, 0.0167956000, 0.0092696000, -0.041512500, -0.197456100", \ - "-0.001752400, 0.0022965000, 0.0096429000, 0.0168512000, 0.0096339000, -0.040952300, -0.196818600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.000143000, 0.0016463000, 0.0060464000, 0.0165270000, 0.0412299000, 0.1029502000, 0.2644325000", \ - "-9.05500e-05, 0.0016773000, 0.0060349000, 0.0164397000, 0.0412107000, 0.1033404000, 0.2632026000", \ - "5.510000e-05, 0.0018131000, 0.0061380000, 0.0165002000, 0.0412280000, 0.1033635000, 0.2631723000", \ - "1.415000e-05, 0.0017515000, 0.0060573000, 0.0163767000, 0.0409199000, 0.1031433000, 0.2647795000", \ - "-5.44500e-05, 0.0016850000, 0.0059834000, 0.0162998000, 0.0408514000, 0.1025843000, 0.2640714000", \ - "-0.000203100, 0.0015537000, 0.0058851000, 0.0162719000, 0.0409137000, 0.1025086000, 0.2633941000", \ - "-0.000500500, 0.0013502000, 0.0058846000, 0.0165464000, 0.0413643000, 0.1037164000, 0.2642375000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.002058000, 0.0020612000, 0.0095621000, 0.0170083000, 0.0100447000, -0.040396200, -0.196164900", \ - "-0.002002000, 0.0021128000, 0.0095779000, 0.0170189000, 0.0099687000, -0.040487500, -0.196278600", \ - "-0.001859900, 0.0022343000, 0.0096916000, 0.0170611000, 0.0099689000, -0.040526100, -0.196322000", \ - "-0.001901200, 0.0021665000, 0.0095516000, 0.0168269000, 0.0096551000, -0.040934000, -0.196767500", \ - "-0.001953200, 0.0021050000, 0.0094610000, 0.0167162000, 0.0094680000, -0.041128300, -0.196954500", \ - "-0.002034400, 0.0020285000, 0.0094048000, 0.0166948000, 0.0094818000, -0.041061800, -0.196905900", \ - "-0.002187100, 0.0019652000, 0.0095104000, 0.0170514000, 0.0101550000, -0.040463600, -0.196300400"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.003650800, -0.001448700, 0.0037751000, 0.0154845000, 0.0414930000, 0.1044786000, 0.2645960000", \ - "-0.003592400, -0.001397500, 0.0038059000, 0.0154966000, 0.0414632000, 0.1044802000, 0.2640180000", \ - "-0.003455200, -0.001280200, 0.0038891000, 0.0155339000, 0.0414339000, 0.1045632000, 0.2657222000", \ - "-0.003498200, -0.001358900, 0.0037420000, 0.0152752000, 0.0411771000, 0.1037312000, 0.2640505000", \ - "-0.003550400, -0.001428100, 0.0036357000, 0.0151174000, 0.0408665000, 0.1037782000, 0.2631501000", \ - "-0.003639800, -0.001513400, 0.0035552000, 0.0150487000, 0.0408000000, 0.1035310000, 0.2649445000", \ - "-0.003789600, -0.001576000, 0.0036736000, 0.0154093000, 0.0412619000, 0.1041086000, 0.2651451000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0006995000, 0.0045984000, 0.0116199000, 0.0183310000, 0.0104948000, -0.040498100, -0.196554200", \ - "0.0006705000, 0.0045585000, 0.0115470000, 0.0182098000, 0.0103476000, -0.040673400, -0.196751700", \ - "0.0006225000, 0.0044921000, 0.0114471000, 0.0180667000, 0.0101552000, -0.040896500, -0.196988000", \ - "0.0006103000, 0.0044583000, 0.0113809000, 0.0179638000, 0.0100328000, -0.041029500, -0.197122100", \ - "0.0005879000, 0.0044060000, 0.0112538000, 0.0177374000, 0.0097298000, -0.041369100, -0.197478300", \ - "0.0005796000, 0.0043951000, 0.0112092000, 0.0176394000, 0.0096151000, -0.041531600, -0.197640500", \ - "0.0006374000, 0.0045343000, 0.0114932000, 0.0181162000, 0.0102761000, -0.040603500, -0.196626500"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0026281000, 0.0034782000, 0.0059959000, 0.0136315000, 0.0353950000, 0.0956041000, 0.2544916000", \ - "0.0026490000, 0.0035016000, 0.0060206000, 0.0136259000, 0.0354014000, 0.0957104000, 0.2542702000", \ - "0.0026894000, 0.0035262000, 0.0060164000, 0.0135770000, 0.0352846000, 0.0955833000, 0.2557098000", \ - "0.0026629000, 0.0034564000, 0.0058651000, 0.0133259000, 0.0349679000, 0.0952499000, 0.2555634000", \ - "0.0026528000, 0.0034250000, 0.0057876000, 0.0132161000, 0.0348646000, 0.0945981000, 0.2553629000", \ - "0.0026817000, 0.0034853000, 0.0059175000, 0.0133229000, 0.0350607000, 0.0946719000, 0.2540634000", \ - "0.0027399000, 0.0036127000, 0.0061161000, 0.0138018000, 0.0357739000, 0.0959410000, 0.2537254000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5019140000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2241088000, 0.2301210000, 0.2427085000, 0.2680647000, 0.3214680000, 0.4454827000, 0.7651053000", \ - "0.2290204000, 0.2350293000, 0.2476107000, 0.2730053000, 0.3263998000, 0.4504237000, 0.7700185000", \ - "0.2421671000, 0.2481799000, 0.2607837000, 0.2861639000, 0.3395641000, 0.4635752000, 0.7832807000", \ - "0.2733943000, 0.2794172000, 0.2920200000, 0.3174113000, 0.3708164000, 0.4948372000, 0.8145293000", \ - "0.3304701000, 0.3364778000, 0.3490921000, 0.3744779000, 0.4278755000, 0.5518906000, 0.8723162000", \ - "0.4194970000, 0.4255278000, 0.4381644000, 0.4635004000, 0.5169019000, 0.6409354000, 0.9606472000", \ - "0.5598763000, 0.5659051000, 0.5784226000, 0.6038746000, 0.6573166000, 0.7813707000, 1.1011232000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3252349000, 0.3331106000, 0.3503884000, 0.3893149000, 0.4850846000, 0.7295183000, 1.3675832000", \ - "0.3296567000, 0.3375717000, 0.3548783000, 0.3938025000, 0.4895905000, 0.7341680000, 1.3730941000", \ - "0.3408819000, 0.3487991000, 0.3661068000, 0.4050328000, 0.5008181000, 0.7454058000, 1.3843116000", \ - "0.3617222000, 0.3697224000, 0.3869211000, 0.4258644000, 0.5216435000, 0.7659452000, 1.4033118000", \ - "0.3891598000, 0.3970936000, 0.4143129000, 0.4532489000, 0.5490209000, 0.7933016000, 1.4308733000", \ - "0.4202407000, 0.4281832000, 0.4454672000, 0.4844287000, 0.5802068000, 0.8245601000, 1.4636057000", \ - "0.4436034000, 0.4513394000, 0.4686224000, 0.5076100000, 0.6033731000, 0.8482133000, 1.4847519000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0214035000, 0.0254576000, 0.0357018000, 0.0589113000, 0.1166651000, 0.2714904000, 0.6934230000", \ - "0.0211998000, 0.0257540000, 0.0353052000, 0.0588867000, 0.1165643000, 0.2715619000, 0.6985962000", \ - "0.0212621000, 0.0257782000, 0.0353383000, 0.0589497000, 0.1166995000, 0.2714741000, 0.6941911000", \ - "0.0211859000, 0.0256636000, 0.0354199000, 0.0588092000, 0.1162245000, 0.2713830000, 0.6941286000", \ - "0.0211886000, 0.0257078000, 0.0353924000, 0.0588141000, 0.1162724000, 0.2714138000, 0.6964470000", \ - "0.0214860000, 0.0257818000, 0.0354068000, 0.0589827000, 0.1162934000, 0.2715096000, 0.6975816000", \ - "0.0213174000, 0.0256410000, 0.0354154000, 0.0588432000, 0.1163471000, 0.2712395000, 0.6919980000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0292786000, 0.0362248000, 0.0537913000, 0.1022797000, 0.2322392000, 0.5778824000, 1.4973037000", \ - "0.0294116000, 0.0364378000, 0.0537229000, 0.1023547000, 0.2320933000, 0.5789830000, 1.4910412000", \ - "0.0294002000, 0.0364394000, 0.0536986000, 0.1023567000, 0.2320980000, 0.5789872000, 1.4910795000", \ - "0.0294643000, 0.0364718000, 0.0538830000, 0.1023544000, 0.2319949000, 0.5770438000, 1.4981962000", \ - "0.0293526000, 0.0362496000, 0.0536267000, 0.1022478000, 0.2320478000, 0.5772660000, 1.4982886000", \ - "0.0295451000, 0.0363674000, 0.0538921000, 0.1023537000, 0.2322272000, 0.5777531000, 1.4934662000", \ - "0.0293188000, 0.0363430000, 0.0537480000, 0.1022828000, 0.2322774000, 0.5779814000, 1.4901322000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2701152000, 0.2761943000, 0.2889385000, 0.3144583000, 0.3679296000, 0.4919941000, 0.8116453000", \ - "0.2747026000, 0.2807855000, 0.2935145000, 0.3190440000, 0.3725144000, 0.4965708000, 0.8163379000", \ - "0.2858296000, 0.2919275000, 0.3046322000, 0.3301623000, 0.3836280000, 0.5076988000, 0.8275002000", \ - "0.3101730000, 0.3162620000, 0.3290116000, 0.3545335000, 0.4080101000, 0.5320741000, 0.8516373000", \ - "0.3487345000, 0.3548186000, 0.3675348000, 0.3930731000, 0.4465537000, 0.5706209000, 0.8905765000", \ - "0.4005107000, 0.4066066000, 0.4193483000, 0.4448484000, 0.4983168000, 0.6223669000, 0.9432386000", \ - "0.4575922000, 0.4636743000, 0.4764425000, 0.5019313000, 0.5554225000, 0.6794902000, 0.9993154000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2912512000, 0.2991637000, 0.3166064000, 0.3556502000, 0.4514272000, 0.6956191000, 1.3342503000", \ - "0.2958858000, 0.3037810000, 0.3212076000, 0.3602503000, 0.4560280000, 0.7003321000, 1.3390402000", \ - "0.3066492000, 0.3145515000, 0.3319892000, 0.3710408000, 0.4668383000, 0.7114126000, 1.3512830000", \ - "0.3305541000, 0.3384540000, 0.3558877000, 0.3949347000, 0.4907159000, 0.7347619000, 1.3742563000", \ - "0.3703137000, 0.3782228000, 0.3956630000, 0.4346875000, 0.5304751000, 0.7748259000, 1.4131512000", \ - "0.4256061000, 0.4335091000, 0.4509477000, 0.4899886000, 0.5857724000, 0.8303349000, 1.4702630000", \ - "0.4939070000, 0.5018027000, 0.5192670000, 0.5583320000, 0.6541087000, 0.8986462000, 1.5363972000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0217315000, 0.0259390000, 0.0358004000, 0.0590645000, 0.1169259000, 0.2712510000, 0.6962202000", \ - "0.0217284000, 0.0260119000, 0.0355939000, 0.0589799000, 0.1169223000, 0.2723658000, 0.6987155000", \ - "0.0215673000, 0.0258788000, 0.0356339000, 0.0591013000, 0.1163824000, 0.2719399000, 0.6986001000", \ - "0.0218185000, 0.0261099000, 0.0358213000, 0.0589596000, 0.1167041000, 0.2714542000, 0.6954574000", \ - "0.0215967000, 0.0258913000, 0.0356473000, 0.0590255000, 0.1168864000, 0.2714525000, 0.7027326000", \ - "0.0217538000, 0.0258706000, 0.0360012000, 0.0590101000, 0.1163113000, 0.2714945000, 0.6990228000", \ - "0.0216969000, 0.0260976000, 0.0357506000, 0.0590888000, 0.1167607000, 0.2715835000, 0.6919163000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0291869000, 0.0362633000, 0.0538561000, 0.1022945000, 0.2320139000, 0.5769879000, 1.4916862000", \ - "0.0291458000, 0.0361523000, 0.0538887000, 0.1023411000, 0.2322117000, 0.5775594000, 1.4879880000", \ - "0.0290747000, 0.0361193000, 0.0539032000, 0.1023087000, 0.2320480000, 0.5784962000, 1.4934717000", \ - "0.0291219000, 0.0361208000, 0.0538275000, 0.1023066000, 0.2323065000, 0.5789296000, 1.4937557000", \ - "0.0291658000, 0.0362761000, 0.0538569000, 0.1023192000, 0.2318997000, 0.5777980000, 1.4874911000", \ - "0.0291123000, 0.0362042000, 0.0538346000, 0.1023147000, 0.2319685000, 0.5786136000, 1.4933588000", \ - "0.0291786000, 0.0362498000, 0.0539177000, 0.1024085000, 0.2320288000, 0.5786701000, 1.4886470000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1022104000, 0.1083717000, 0.1211955000, 0.1470991000, 0.2027167000, 0.3268031000, 0.6464000000", \ - "0.1075162000, 0.1136564000, 0.1264654000, 0.1524199000, 0.2080547000, 0.3321542000, 0.6515224000", \ - "0.1208272000, 0.1269421000, 0.1397576000, 0.1657230000, 0.2213918000, 0.3454924000, 0.6647173000", \ - "0.1530687000, 0.1591957000, 0.1719756000, 0.1979523000, 0.2536569000, 0.3777955000, 0.6974186000", \ - "0.2259788000, 0.2324569000, 0.2458654000, 0.2723043000, 0.3281965000, 0.4523003000, 0.7718817000", \ - "0.3492103000, 0.3579902000, 0.3755158000, 0.4075257000, 0.4676410000, 0.5920323000, 0.9112218000", \ - "0.5467789000, 0.5589214000, 0.5829867000, 0.6263282000, 0.6960234000, 0.8205079000, 1.1399691000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0963654000, 0.1037270000, 0.1205425000, 0.1587517000, 0.2535804000, 0.4972651000, 1.1349840000", \ - "0.1005470000, 0.1080216000, 0.1247808000, 0.1629800000, 0.2578568000, 0.5015364000, 1.1432063000", \ - "0.1088834000, 0.1164730000, 0.1332463000, 0.1714939000, 0.2665104000, 0.5103536000, 1.1525079000", \ - "0.1269722000, 0.1344888000, 0.1512582000, 0.1896218000, 0.2848822000, 0.5289013000, 1.1712367000", \ - "0.1587876000, 0.1666894000, 0.1843359000, 0.2237503000, 0.3195525000, 0.5634823000, 1.2039933000", \ - "0.2003207000, 0.2095870000, 0.2294343000, 0.2708000000, 0.3677400000, 0.6122231000, 1.2503331000", \ - "0.2295475000, 0.2419610000, 0.2669928000, 0.3140658000, 0.4136951000, 0.6584740000, 1.2961109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0221010000, 0.0264971000, 0.0367222000, 0.0612770000, 0.1191728000, 0.2713470000, 0.6951599000", \ - "0.0220708000, 0.0266479000, 0.0364787000, 0.0613338000, 0.1191699000, 0.2713595000, 0.6927409000", \ - "0.0221656000, 0.0266239000, 0.0365827000, 0.0613004000, 0.1191657000, 0.2713242000, 0.6930427000", \ - "0.0219734000, 0.0263912000, 0.0367554000, 0.0614120000, 0.1192298000, 0.2708359000, 0.6957365000", \ - "0.0248627000, 0.0290315000, 0.0386726000, 0.0623903000, 0.1193773000, 0.2711683000, 0.6972395000", \ - "0.0359099000, 0.0414018000, 0.0513437000, 0.0745440000, 0.1255238000, 0.2718207000, 0.6972868000", \ - "0.0535290000, 0.0606571000, 0.0748320000, 0.1002576000, 0.1398134000, 0.2739122000, 0.6918272000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0270603000, 0.0342275000, 0.0522050000, 0.1013023000, 0.2316851000, 0.5793903000, 1.4969317000", \ - "0.0271158000, 0.0342496000, 0.0520855000, 0.1013107000, 0.2317009000, 0.5789565000, 1.4966612000", \ - "0.0271840000, 0.0340864000, 0.0520811000, 0.1012258000, 0.2318059000, 0.5787830000, 1.4981347000", \ - "0.0274159000, 0.0343840000, 0.0522049000, 0.1012421000, 0.2316878000, 0.5788743000, 1.4983149000", \ - "0.0303382000, 0.0376523000, 0.0549416000, 0.1030736000, 0.2324309000, 0.5793400000, 1.5019139000", \ - "0.0373431000, 0.0439904000, 0.0611376000, 0.1070986000, 0.2351460000, 0.5788919000, 1.4914375000", \ - "0.0515102000, 0.0596081000, 0.0769768000, 0.1189527000, 0.2389355000, 0.5809062000, 1.4894885000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0012548000, 0.0047449000, 0.0109760000, 0.0165288000, 0.0070099000, -0.047365800, -0.211946300", \ - "0.0013059000, 0.0047760000, 0.0109739000, 0.0164369000, 0.0068456000, -0.047574400, -0.212173400", \ - "0.0014553000, 0.0049125000, 0.0110836000, 0.0165038000, 0.0068536000, -0.047595300, -0.212200500", \ - "0.0014142000, 0.0048481000, 0.0109904000, 0.0163767000, 0.0066921000, -0.047796900, -0.212378700", \ - "0.0013408000, 0.0047817000, 0.0109171000, 0.0163040000, 0.0066187000, -0.047878500, -0.212544500", \ - "0.0011923000, 0.0046446000, 0.0108274000, 0.0162717000, 0.0066325000, -0.047804700, -0.212416400", \ - "0.0008905000, 0.0044440000, 0.0108270000, 0.0165499000, 0.0071288000, -0.047308900, -0.211845400"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002705900, -0.000469000, 0.0049317000, 0.0170223000, 0.0440277000, 0.1100091000, 0.2779141000", \ - "-0.002670800, -0.000449100, 0.0049241000, 0.0169820000, 0.0439150000, 0.1099096000, 0.2778004000", \ - "-0.002570500, -0.000361000, 0.0049883000, 0.0169990000, 0.0440030000, 0.1093207000, 0.2777794000", \ - "-0.002609100, -0.000402700, 0.0049394000, 0.0169442000, 0.0439053000, 0.1091373000, 0.2790866000", \ - "-0.002686800, -0.000474600, 0.0048780000, 0.0168702000, 0.0438647000, 0.1094490000, 0.2776277000", \ - "-0.002863900, -0.000634600, 0.0047535000, 0.0167968000, 0.0439330000, 0.1091423000, 0.2790197000", \ - "-0.003234800, -0.000916900, 0.0045996000, 0.0168578000, 0.0440707000, 0.1096569000, 0.2792382000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002261700, 0.0016332000, 0.0087144000, 0.0154991000, 0.0072149000, -0.046342300, -0.210505900", \ - "-0.002203900, 0.0016842000, 0.0087331000, 0.0154966000, 0.0071842000, -0.046389800, -0.210564300", \ - "-0.002066200, 0.0018009000, 0.0088215000, 0.0155301000, 0.0071843000, -0.046410900, -0.210590300", \ - "-0.002109900, 0.0017269000, 0.0086732000, 0.0152652000, 0.0067946000, -0.046905000, -0.211127700", \ - "-0.002158800, 0.0016571000, 0.0085608000, 0.0151169000, 0.0065927000, -0.047113100, -0.211361900", \ - "-0.002248100, 0.0015731000, 0.0084910000, 0.0150545000, 0.0065360000, -0.047162000, -0.211406800", \ - "-0.002396400, 0.0015161000, 0.0086204000, 0.0154611000, 0.0071636000, -0.046539700, -0.210719300"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.003549600, -0.001174800, 0.0044858000, 0.0169600000, 0.0443640000, 0.1099591000, 0.2791772000", \ - "-0.003496400, -0.001140200, 0.0044985000, 0.0169557000, 0.0442445000, 0.1106982000, 0.2801762000", \ - "-0.003360300, -0.001017700, 0.0045791000, 0.0169582000, 0.0442493000, 0.1103549000, 0.2799219000", \ - "-0.003392800, -0.001072800, 0.0044812000, 0.0168162000, 0.0441809000, 0.1093502000, 0.2800482000", \ - "-0.003439600, -0.001128800, 0.0044184000, 0.0167032000, 0.0438889000, 0.1094358000, 0.2796151000", \ - "-0.003527100, -0.001212700, 0.0043515000, 0.0166642000, 0.0439099000, 0.1094226000, 0.2795359000", \ - "-0.003666800, -0.001245200, 0.0044536000, 0.0170426000, 0.0443938000, 0.1104567000, 0.2778783000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0040318000, 0.0065825000, 0.0109394000, 0.0136497000, 0.0012346000, -0.055069400, -0.220586100", \ - "0.0040522000, 0.0065942000, 0.0109476000, 0.0136262000, 0.0012331000, -0.055104300, -0.220646400", \ - "0.0040982000, 0.0066259000, 0.0109398000, 0.0135662000, 0.0011259000, -0.055215700, -0.220773600", \ - "0.0040707000, 0.0065646000, 0.0108051000, 0.0133329000, 0.0007618000, -0.055645400, -0.221234400", \ - "0.0040625000, 0.0065371000, 0.0107466000, 0.0132125000, 0.0005969000, -0.055826100, -0.221419900", \ - "0.0040803000, 0.0065652000, 0.0108134000, 0.0133077000, 0.0006907000, -0.055752100, -0.221325200", \ - "0.0041423000, 0.0067043000, 0.0110857000, 0.0138053000, 0.0014190000, -0.054831700, -0.220457700"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.000803300, 0.0013308000, 0.0065472000, 0.0183427000, 0.0450408000, 0.1107988000, 0.2798083000", \ - "-0.000821700, 0.0013090000, 0.0065191000, 0.0183201000, 0.0449841000, 0.1107339000, 0.2797195000", \ - "-0.000874300, 0.0012351000, 0.0064110000, 0.0181381000, 0.0447466000, 0.1104760000, 0.2794401000", \ - "-0.000889000, 0.0012013000, 0.0063342000, 0.0179971000, 0.0445419000, 0.1102479000, 0.2791884000", \ - "-0.000912800, 0.0011451000, 0.0061992000, 0.0177791000, 0.0442032000, 0.1094137000, 0.2774844000", \ - "-0.000937300, 0.0010970000, 0.0061168000, 0.0176699000, 0.0440201000, 0.1092667000, 0.2775361000", \ - "-0.000872700, 0.0012672000, 0.0063979000, 0.0180402000, 0.0446942000, 0.1098719000, 0.2779640000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5031380000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3786698000, 0.3838925000, 0.3949639000, 0.4180367000, 0.4703204000, 0.6039007000, 0.9560764000", \ - "0.3831295000, 0.3883608000, 0.3994454000, 0.4224923000, 0.4747437000, 0.6083318000, 0.9610290000", \ - "0.3943885000, 0.3995823000, 0.4106342000, 0.4337350000, 0.4859904000, 0.6195056000, 0.9716675000", \ - "0.4151867000, 0.4204162000, 0.4315021000, 0.4545489000, 0.5068304000, 0.6402743000, 0.9923173000", \ - "0.4426027000, 0.4478301000, 0.4589053000, 0.4819725000, 0.5342583000, 0.6678051000, 1.0201676000", \ - "0.4737572000, 0.4789796000, 0.4900521000, 0.5131313000, 0.5654007000, 0.6990094000, 1.0519168000", \ - "0.4969863000, 0.5021952000, 0.5132885000, 0.5363739000, 0.5884945000, 0.7220873000, 1.0750881000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2807888000, 0.2870420000, 0.3016073000, 0.3373536000, 0.4300856000, 0.6743610000, 1.3192281000", \ - "0.2856778000, 0.2919001000, 0.3065481000, 0.3423293000, 0.4351073000, 0.6787718000, 1.3238652000", \ - "0.2988832000, 0.3050588000, 0.3197089000, 0.3555286000, 0.4483217000, 0.6924040000, 1.3366569000", \ - "0.3300837000, 0.3363079000, 0.3509579000, 0.3867517000, 0.4795037000, 0.7243874000, 1.3679438000", \ - "0.3871495000, 0.3933757000, 0.4080271000, 0.4438208000, 0.5364182000, 0.7808640000, 1.4254714000", \ - "0.4762712000, 0.4824991000, 0.4970327000, 0.5327295000, 0.6256998000, 0.8693214000, 1.5131699000", \ - "0.6165811000, 0.6228339000, 0.6374072000, 0.6731669000, 0.7661589000, 1.0096163000, 1.6542850000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0171498000, 0.0211984000, 0.0308784000, 0.0542320000, 0.1178398000, 0.2942416000, 0.7667379000", \ - "0.0171204000, 0.0213129000, 0.0308822000, 0.0543796000, 0.1180577000, 0.2943140000, 0.7645869000", \ - "0.0173172000, 0.0212860000, 0.0306304000, 0.0544030000, 0.1178877000, 0.2939044000, 0.7654439000", \ - "0.0171149000, 0.0213301000, 0.0308824000, 0.0543779000, 0.1181311000, 0.2938806000, 0.7665268000", \ - "0.0170908000, 0.0214486000, 0.0308789000, 0.0542769000, 0.1178941000, 0.2940962000, 0.7665504000", \ - "0.0171455000, 0.0212110000, 0.0308868000, 0.0540954000, 0.1181471000, 0.2942991000, 0.7686841000", \ - "0.0170864000, 0.0213214000, 0.0307767000, 0.0542528000, 0.1182214000, 0.2943185000, 0.7602957000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0205738000, 0.0271222000, 0.0448324000, 0.0937194000, 0.2255882000, 0.5774012000, 1.4976143000", \ - "0.0206202000, 0.0271275000, 0.0448250000, 0.0936962000, 0.2259549000, 0.5765354000, 1.5005226000", \ - "0.0205736000, 0.0271841000, 0.0448163000, 0.0937755000, 0.2255135000, 0.5763610000, 1.5010313000", \ - "0.0206177000, 0.0271443000, 0.0448255000, 0.0937471000, 0.2258220000, 0.5761603000, 1.5029318000", \ - "0.0206165000, 0.0271519000, 0.0448251000, 0.0938077000, 0.2262921000, 0.5781604000, 1.4967182000", \ - "0.0205639000, 0.0271140000, 0.0448325000, 0.0938035000, 0.2257589000, 0.5750080000, 1.5018938000", \ - "0.0205814000, 0.0271843000, 0.0447566000, 0.0937186000, 0.2258154000, 0.5747188000, 1.4983820000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3449586000, 0.3501802000, 0.3612375000, 0.3843100000, 0.4366271000, 0.5701980000, 0.9223845000", \ - "0.3494323000, 0.3546408000, 0.3657502000, 0.3887965000, 0.4410501000, 0.5746335000, 0.9275273000", \ - "0.3602493000, 0.3654572000, 0.3765690000, 0.3996125000, 0.4518738000, 0.5854091000, 0.9381129000", \ - "0.3840190000, 0.3892391000, 0.4003043000, 0.4233394000, 0.4757077000, 0.6090998000, 0.9620209000", \ - "0.4238676000, 0.4290787000, 0.4401440000, 0.4632227000, 0.5155446000, 0.6491153000, 1.0016687000", \ - "0.4793274000, 0.4845295000, 0.4956586000, 0.5186847000, 0.5709331000, 0.7044870000, 1.0571980000", \ - "0.5476334000, 0.5528448000, 0.5639246000, 0.5870174000, 0.6393060000, 0.7728023000, 1.1249855000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3271056000, 0.3333428000, 0.3478002000, 0.3835397000, 0.4764751000, 0.7200149000, 1.3656675000", \ - "0.3318120000, 0.3380400000, 0.3526769000, 0.3884125000, 0.4812631000, 0.7254343000, 1.3719960000", \ - "0.3427976000, 0.3490449000, 0.3635895000, 0.3992624000, 0.4920821000, 0.7363831000, 1.3816914000", \ - "0.3672899000, 0.3735170000, 0.3880667000, 0.4238862000, 0.5165182000, 0.7603442000, 1.4065976000", \ - "0.4054465000, 0.4116991000, 0.4263269000, 0.4621040000, 0.5547927000, 0.7998249000, 1.4460484000", \ - "0.4578584000, 0.4641107000, 0.4787243000, 0.5145329000, 0.6073476000, 0.8521835000, 1.4983971000", \ - "0.5148911000, 0.5211328000, 0.5356051000, 0.5711954000, 0.6638892000, 0.9090924000, 1.5519610000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0172406000, 0.0210919000, 0.0307001000, 0.0542656000, 0.1177881000, 0.2941953000, 0.7639658000", \ - "0.0170950000, 0.0212465000, 0.0306782000, 0.0542953000, 0.1180577000, 0.2943559000, 0.7630760000", \ - "0.0170974000, 0.0212573000, 0.0306725000, 0.0542874000, 0.1177114000, 0.2940288000, 0.7698657000", \ - "0.0170566000, 0.0211808000, 0.0307980000, 0.0542263000, 0.1182563000, 0.2941945000, 0.7692937000", \ - "0.0171977000, 0.0210956000, 0.0307060000, 0.0543178000, 0.1181840000, 0.2941322000, 0.7626968000", \ - "0.0171069000, 0.0212936000, 0.0306262000, 0.0540320000, 0.1182138000, 0.2942151000, 0.7696542000", \ - "0.0173420000, 0.0211358000, 0.0308501000, 0.0543150000, 0.1175715000, 0.2939820000, 0.7610050000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0206088000, 0.0271860000, 0.0449145000, 0.0938111000, 0.2260628000, 0.5765434000, 1.4987912000", \ - "0.0206647000, 0.0272155000, 0.0448518000, 0.0936460000, 0.2257380000, 0.5770533000, 1.5005509000", \ - "0.0205708000, 0.0271734000, 0.0449144000, 0.0936900000, 0.2254399000, 0.5773387000, 1.4973036000", \ - "0.0206218000, 0.0271625000, 0.0448991000, 0.0936217000, 0.2257866000, 0.5756203000, 1.5031385000", \ - "0.0207040000, 0.0272015000, 0.0449584000, 0.0937542000, 0.2258707000, 0.5769102000, 1.5017039000", \ - "0.0207185000, 0.0271712000, 0.0449737000, 0.0937735000, 0.2257454000, 0.5767505000, 1.5022269000", \ - "0.0205598000, 0.0271321000, 0.0449837000, 0.0936527000, 0.2265186000, 0.5756732000, 1.4976412000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.1490683000, 0.1542393000, 0.1653494000, 0.1884136000, 0.2406189000, 0.3740655000, 0.7260955000", \ - "0.1532710000, 0.1584501000, 0.1695258000, 0.1926229000, 0.2447812000, 0.3782714000, 0.7301462000", \ - "0.1617243000, 0.1669093000, 0.1779712000, 0.2009689000, 0.2532434000, 0.3867544000, 0.7394527000", \ - "0.1797383000, 0.1849378000, 0.1959391000, 0.2190279000, 0.2712184000, 0.4046454000, 0.7575512000", \ - "0.2128874000, 0.2180943000, 0.2292000000, 0.2522633000, 0.3046543000, 0.4381290000, 0.7908007000", \ - "0.2581626000, 0.2635440000, 0.2747260000, 0.2980764000, 0.3504814000, 0.4840761000, 0.8362465000", \ - "0.2972851000, 0.3028839000, 0.3145751000, 0.3383449000, 0.3910967000, 0.5248222000, 0.8768100000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.1601521000, 0.1664390000, 0.1810326000, 0.2167991000, 0.3097685000, 0.5538656000, 1.1983511000", \ - "0.1654624000, 0.1717535000, 0.1863480000, 0.2221197000, 0.3149702000, 0.5590873000, 1.2033775000", \ - "0.1784619000, 0.1847483000, 0.1994181000, 0.2353280000, 0.3281751000, 0.5722098000, 1.2166096000", \ - "0.2105557000, 0.2168465000, 0.2315252000, 0.2674150000, 0.3602578000, 0.6042156000, 1.2485576000", \ - "0.2848162000, 0.2910540000, 0.3056115000, 0.3416183000, 0.4344643000, 0.6783861000, 1.3210486000", \ - "0.4195956000, 0.4260335000, 0.4409239000, 0.4767224000, 0.5695655000, 0.8140810000, 1.4574372000", \ - "0.6366771000, 0.6437149000, 0.6593922000, 0.6953985000, 0.7884722000, 1.0323402000, 1.6758281000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0169453000, 0.0211740000, 0.0306295000, 0.0541494000, 0.1182238000, 0.2939610000, 0.7734403000", \ - "0.0169646000, 0.0211701000, 0.0304630000, 0.0542960000, 0.1179734000, 0.2943060000, 0.7654100000", \ - "0.0170638000, 0.0210985000, 0.0307141000, 0.0542986000, 0.1179175000, 0.2935564000, 0.7701218000", \ - "0.0169640000, 0.0210243000, 0.0307234000, 0.0540989000, 0.1181259000, 0.2938769000, 0.7674227000", \ - "0.0172951000, 0.0215023000, 0.0306838000, 0.0545597000, 0.1182614000, 0.2942436000, 0.7672388000", \ - "0.0178573000, 0.0219129000, 0.0314688000, 0.0546174000, 0.1184131000, 0.2931468000, 0.7655334000", \ - "0.0196176000, 0.0234587000, 0.0329851000, 0.0562850000, 0.1190509000, 0.2942861000, 0.7610657000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0207611000, 0.0273509000, 0.0451460000, 0.0939917000, 0.2259629000, 0.5766265000, 1.5009690000", \ - "0.0207403000, 0.0273510000, 0.0451425000, 0.0939037000, 0.2260354000, 0.5762893000, 1.5008204000", \ - "0.0208776000, 0.0273539000, 0.0451938000, 0.0939756000, 0.2260100000, 0.5764100000, 1.5007565000", \ - "0.0208855000, 0.0273539000, 0.0451911000, 0.0939616000, 0.2260238000, 0.5761664000, 1.5005396000", \ - "0.0208700000, 0.0274658000, 0.0451736000, 0.0940043000, 0.2259322000, 0.5746456000, 1.4970735000", \ - "0.0224179000, 0.0287270000, 0.0460772000, 0.0942611000, 0.2256346000, 0.5760177000, 1.4958788000", \ - "0.0262154000, 0.0324214000, 0.0483725000, 0.0954464000, 0.2260200000, 0.5745385000, 1.4963413000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0024390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043497000, 0.0043820000, 0.0044563000, 0.0044579000, 0.0044615000, 0.0044698000, 0.0044891000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004286500, -0.004333600, -0.004442200, -0.004444300, -0.004449100, -0.004460400, -0.004486100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025630000; - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.033400400, 0.0294577000, 0.0310853000", \ - "-0.196356100, -0.138380900, -0.137974000", \ - "-0.362778700, -0.309686200, -0.311720700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0483867000, -0.013250700, -0.016099000", \ - "0.2174460000, 0.1570293000, 0.1541810000", \ - "0.3948548000, 0.3356589000, 0.3340313000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1302382000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrbp_2") { - leakage_power () { - value : 0.0145136000; - when : "RESET_B&D&GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0096429000; - when : "RESET_B&!D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0094388000; - when : "!RESET_B&!D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0097225000; - when : "RESET_B&!D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0144190000; - when : "RESET_B&D&!GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0110206000; - when : "!RESET_B&D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0108214000; - when : "!RESET_B&D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0093592000; - when : "!RESET_B&!D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0111050000; - when : "RESET_B&D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0135851000; - when : "RESET_B&!D&!GATE&Q&!Q_N"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__dlrbp"; - cell_leakage_power : 0.0113628000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082670000, 0.0081743000, 0.0079607000, 0.0080332000, 0.0082003000, 0.0085855000, 0.0094736000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025840000, 0.0024914000, 0.0022779000, 0.0023320000, 0.0024565000, 0.0027439000, 0.0034062000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018810000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0496074000, 0.2089010000, 0.3789857000", \ - "-0.125555300, 0.0325176000, 0.1989401000", \ - "-0.306626300, -0.147332700, 0.0142070000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2229473000, 0.3065573000, 0.3387025000", \ - "0.1234681000, 0.2070781000, 0.2380026000", \ - "0.0656882000, 0.1444154000, 0.1716777000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.033400400, -0.195135400, -0.366440800", \ - "0.1405417000, -0.019972700, -0.187615900", \ - "0.3216126000, 0.1598776000, -0.004103500"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.207960900, -0.292791700, -0.326157600", \ - "-0.101157600, -0.185988300, -0.218133500", \ - "-0.011639300, -0.098911500, -0.129835900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017710000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172729000, 0.0171783000, 0.0169601000, 0.0170296000, 0.0171898000, 0.0175591000, 0.0184105000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101381000, 0.0100496000, 0.0098456000, 0.0098738000, 0.0099389000, 0.0100891000, 0.0104353000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018490000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1895578000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.001304100, 0.0032974000, 0.0126580000, 0.0222849000, 0.0082838000, -0.082935800, -0.380809400", \ - "-0.001264100, 0.0033279000, 0.0126556000, 0.0222758000, 0.0081688000, -0.083040800, -0.380922900", \ - "-0.001164500, 0.0034175000, 0.0127077000, 0.0223350000, 0.0082174000, -0.083048700, -0.380941400", \ - "-0.001204400, 0.0033759000, 0.0126723000, 0.0222770000, 0.0080733000, -0.083197900, -0.381092100", \ - "-0.001281800, 0.0032945000, 0.0125994000, 0.0222380000, 0.0080608000, -0.083202400, -0.381085300", \ - "-0.001468800, 0.0031244000, 0.0124442000, 0.0220950000, 0.0080669000, -0.083144900, -0.380964800", \ - "-0.001868200, 0.0028049000, 0.0122885000, 0.0222380000, 0.0084394000, -0.082717400, -0.380500100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.000232800, 0.0017157000, 0.0070551000, 0.0214408000, 0.0595035000, 0.1643617000, 0.4657851000", \ - "-0.000193700, 0.0017440000, 0.0070510000, 0.0214030000, 0.0593660000, 0.1647145000, 0.4653277000", \ - "-9.35500e-05, 0.0018295000, 0.0071065000, 0.0214090000, 0.0594278000, 0.1650086000, 0.4680695000", \ - "-0.000128500, 0.0017848000, 0.0070010000, 0.0212475000, 0.0591353000, 0.1644520000, 0.4649282000", \ - "-0.000194000, 0.0017047000, 0.0069309000, 0.0211841000, 0.0590608000, 0.1638190000, 0.4655004000", \ - "-0.000325400, 0.0016023000, 0.0068934000, 0.0212058000, 0.0591370000, 0.1638879000, 0.4652304000", \ - "-0.000585600, 0.0014643000, 0.0070445000, 0.0217083000, 0.0599172000, 0.1655192000, 0.4650481000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.002163200, 0.0025598000, 0.0121614000, 0.0223382000, 0.0086711000, -0.082242400, -0.379952000", \ - "-0.002125800, 0.0025941000, 0.0121845000, 0.0222930000, 0.0086360000, -0.082285500, -0.380023300", \ - "-0.002039300, 0.0026557000, 0.0121907000, 0.0222399000, 0.0084833000, -0.082509600, -0.380246400", \ - "-0.002062000, 0.0026149000, 0.0121122000, 0.0220780000, 0.0082996000, -0.082661500, -0.380418600", \ - "-0.002101100, 0.0025632000, 0.0120241000, 0.0219866000, 0.0080918000, -0.082988600, -0.380756500", \ - "-0.002172100, 0.0025090000, 0.0119944000, 0.0219128000, 0.0081916000, -0.082849400, -0.380598000", \ - "-0.002291600, 0.0024779000, 0.0121689000, 0.0224740000, 0.0089605000, -0.082145500, -0.379944900"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("-0.003788300, -0.001474800, 0.0046921000, 0.0204097000, 0.0597734000, 0.1653332000, 0.4674767000", \ - "-0.003749100, -0.001441500, 0.0047051000, 0.0203951000, 0.0597543000, 0.1661532000, 0.4674631000", \ - "-0.003657700, -0.001368400, 0.0047442000, 0.0203771000, 0.0596727000, 0.1653193000, 0.4686698000", \ - "-0.003692600, -0.001428300, 0.0046095000, 0.0201278000, 0.0592802000, 0.1654919000, 0.4686204000", \ - "-0.003734000, -0.001490400, 0.0045045000, 0.0199687000, 0.0590864000, 0.1653514000, 0.4684335000", \ - "-0.003806900, -0.001563000, 0.0044446000, 0.0199003000, 0.0589782000, 0.1643954000, 0.4663270000", \ - "-0.003917300, -0.001563500, 0.0046928000, 0.0204221000, 0.0596887000, 0.1657841000, 0.4657718000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("0.0005920000, 0.0051040000, 0.0142273000, 0.0234787000, 0.0088555000, -0.082815000, -0.380863000", \ - "0.0005686000, 0.0050673000, 0.0141660000, 0.0233737000, 0.0087211000, -0.082968200, -0.381027300", \ - "0.0005221000, 0.0050063000, 0.0140713000, 0.0232240000, 0.0085100000, -0.083165000, -0.381292000", \ - "0.0005108000, 0.0049824000, 0.0139994000, 0.0230875000, 0.0083686000, -0.083366000, -0.381331300", \ - "0.0004923000, 0.0049344000, 0.0138809000, 0.0228404000, 0.0080302000, -0.083655400, -0.381727500", \ - "0.0004760000, 0.0049105000, 0.0138059000, 0.0226331000, 0.0076928000, -0.083995700, -0.382025100", \ - "0.0005153000, 0.0050471000, 0.0141447000, 0.0231667000, 0.0084071000, -0.083204600, -0.381161200"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576890, 0.0119892800, 0.0345727500, 0.0996953600, 0.2874855000"); - values("0.0027222000, 0.0038264000, 0.0072876000, 0.0186319000, 0.0533568000, 0.1566860000, 0.4565202000", \ - "0.0027064000, 0.0038081000, 0.0072532000, 0.0185215000, 0.0531665000, 0.1560315000, 0.4548461000", \ - "0.0026623000, 0.0037386000, 0.0071263000, 0.0183575000, 0.0530670000, 0.1555708000, 0.4542318000", \ - "0.0026574000, 0.0037139000, 0.0070719000, 0.0182422000, 0.0529180000, 0.1553930000, 0.4543235000", \ - "0.0026691000, 0.0037199000, 0.0070653000, 0.0180430000, 0.0527328000, 0.1557355000, 0.4579126000", \ - "0.0027256000, 0.0038147000, 0.0072258000, 0.0182565000, 0.0529362000, 0.1554935000, 0.4587779000", \ - "0.0028336000, 0.0039641000, 0.0075169000, 0.0187979000, 0.0538253000, 0.1570238000, 0.4560948000"); - } - } - max_capacitance : 0.2874860000; - max_transition : 1.5032260000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.2368603000, 0.2420533000, 0.2536868000, 0.2775585000, 0.3271059000, 0.4440104000, 0.7653182000", \ - "0.2418415000, 0.2470231000, 0.2586573000, 0.2825314000, 0.3320746000, 0.4489788000, 0.7703384000", \ - "0.2549886000, 0.2601524000, 0.2718560000, 0.2956756000, 0.3452310000, 0.4621201000, 0.7834611000", \ - "0.2861426000, 0.2913644000, 0.3030505000, 0.3268202000, 0.3764580000, 0.4933632000, 0.8146381000", \ - "0.3431093000, 0.3483244000, 0.3600193000, 0.3837792000, 0.4334198000, 0.5503233000, 0.8714553000", \ - "0.4319341000, 0.4371216000, 0.4487661000, 0.4726309000, 0.5221631000, 0.6391029000, 0.9603762000", \ - "0.5720617000, 0.5772771000, 0.5889680000, 0.6127404000, 0.6624055000, 0.7793387000, 1.1006347000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.3389136000, 0.3455567000, 0.3610961000, 0.3958019000, 0.4815195000, 0.7169130000, 1.3905813000", \ - "0.3435547000, 0.3502250000, 0.3657334000, 0.4003955000, 0.4860715000, 0.7212015000, 1.3962047000", \ - "0.3548047000, 0.3614969000, 0.3769534000, 0.4116423000, 0.4973241000, 0.7326154000, 1.4069553000", \ - "0.3756327000, 0.3823362000, 0.3977078000, 0.4323816000, 0.5180691000, 0.7533167000, 1.4280429000", \ - "0.4028318000, 0.4093547000, 0.4249597000, 0.4596072000, 0.5453200000, 0.7805750000, 1.4548592000", \ - "0.4339806000, 0.4406381000, 0.4561651000, 0.4908137000, 0.5764902000, 0.8115388000, 1.4859647000", \ - "0.4570649000, 0.4636830000, 0.4791618000, 0.5138559000, 0.5995349000, 0.8349340000, 1.5088346000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0214305000, 0.0248114000, 0.0327292000, 0.0519970000, 0.1011800000, 0.2418024000, 0.6729196000", \ - "0.0214841000, 0.0249730000, 0.0331637000, 0.0520458000, 0.1011340000, 0.2418075000, 0.6735469000", \ - "0.0213798000, 0.0248090000, 0.0330608000, 0.0520527000, 0.1009373000, 0.2418447000, 0.6741241000", \ - "0.0213722000, 0.0246717000, 0.0331291000, 0.0519365000, 0.1010534000, 0.2418341000, 0.6729106000", \ - "0.0213796000, 0.0246668000, 0.0330433000, 0.0519443000, 0.1010540000, 0.2417122000, 0.6732121000", \ - "0.0214977000, 0.0248608000, 0.0327879000, 0.0518249000, 0.1009078000, 0.2418646000, 0.6736079000", \ - "0.0214356000, 0.0247705000, 0.0328364000, 0.0519874000, 0.1010839000, 0.2418772000, 0.6660635000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0278819000, 0.0332420000, 0.0469892000, 0.0843021000, 0.1967784000, 0.5282188000, 1.5012317000", \ - "0.0279916000, 0.0331918000, 0.0469373000, 0.0842296000, 0.1970481000, 0.5289928000, 1.4995368000", \ - "0.0279357000, 0.0331557000, 0.0468912000, 0.0842353000, 0.1970688000, 0.5282482000, 1.5029878000", \ - "0.0277653000, 0.0330482000, 0.0470442000, 0.0843026000, 0.1971240000, 0.5294665000, 1.4988820000", \ - "0.0279363000, 0.0335457000, 0.0470871000, 0.0842732000, 0.1970997000, 0.5284020000, 1.4975896000", \ - "0.0280211000, 0.0332483000, 0.0469356000, 0.0842371000, 0.1972225000, 0.5281787000, 1.4960276000", \ - "0.0278229000, 0.0332888000, 0.0467680000, 0.0842600000, 0.1965794000, 0.5287820000, 1.4947475000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.2823471000, 0.2876115000, 0.2994128000, 0.3233989000, 0.3730833000, 0.4900348000, 0.8111405000", \ - "0.2869358000, 0.2921962000, 0.3039910000, 0.3279696000, 0.3776615000, 0.4946189000, 0.8157903000", \ - "0.2980846000, 0.3033791000, 0.3151845000, 0.3391714000, 0.3888018000, 0.5057600000, 0.8266252000", \ - "0.3225828000, 0.3278595000, 0.3396537000, 0.3636397000, 0.4133421000, 0.5303039000, 0.8514051000", \ - "0.3607815000, 0.3660362000, 0.3778747000, 0.4018869000, 0.4515539000, 0.5685197000, 0.8899104000", \ - "0.4128834000, 0.4181721000, 0.4299463000, 0.4539284000, 0.5035579000, 0.6205430000, 0.9417049000", \ - "0.4696368000, 0.4749242000, 0.4867310000, 0.5107219000, 0.5604084000, 0.6773781000, 0.9984646000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.3034524000, 0.3101046000, 0.3256240000, 0.3604148000, 0.4462025000, 0.6815316000, 1.3570058000", \ - "0.3080368000, 0.3146728000, 0.3302086000, 0.3650147000, 0.4507893000, 0.6861036000, 1.3614132000", \ - "0.3187517000, 0.3254070000, 0.3409290000, 0.3757612000, 0.4615313000, 0.6968983000, 1.3737901000", \ - "0.3425817000, 0.3492820000, 0.3648259000, 0.3996530000, 0.4854149000, 0.7206325000, 1.3964966000", \ - "0.3824592000, 0.3891362000, 0.4046840000, 0.4395073000, 0.5252789000, 0.7606098000, 1.4358873000", \ - "0.4376306000, 0.4442833000, 0.4598086000, 0.4946493000, 0.5804314000, 0.8155022000, 1.4906230000", \ - "0.5055871000, 0.5122485000, 0.5277901000, 0.5626131000, 0.6483711000, 0.8837461000, 1.5561583000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0218745000, 0.0252383000, 0.0332790000, 0.0522593000, 0.1010362000, 0.2420518000, 0.6684786000", \ - "0.0218109000, 0.0251619000, 0.0331516000, 0.0520692000, 0.1012811000, 0.2417716000, 0.6739364000", \ - "0.0218873000, 0.0251925000, 0.0331924000, 0.0521799000, 0.1013547000, 0.2417312000, 0.6674321000", \ - "0.0217218000, 0.0253296000, 0.0331329000, 0.0523291000, 0.1013478000, 0.2418794000, 0.6740874000", \ - "0.0219384000, 0.0251252000, 0.0330860000, 0.0521805000, 0.1012236000, 0.2417962000, 0.6747804000", \ - "0.0219247000, 0.0251159000, 0.0331175000, 0.0522143000, 0.1010551000, 0.2417597000, 0.6699399000", \ - "0.0219115000, 0.0251879000, 0.0333158000, 0.0521858000, 0.1012270000, 0.2418362000, 0.6699357000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0275805000, 0.0330102000, 0.0467552000, 0.0843835000, 0.1971244000, 0.5286298000, 1.4993833000", \ - "0.0277696000, 0.0330198000, 0.0466751000, 0.0843467000, 0.1968292000, 0.5285883000, 1.4995966000", \ - "0.0276073000, 0.0330343000, 0.0466666000, 0.0842679000, 0.1965815000, 0.5274837000, 1.5004534000", \ - "0.0277489000, 0.0328430000, 0.0467471000, 0.0842435000, 0.1969617000, 0.5284528000, 1.4970241000", \ - "0.0276941000, 0.0328334000, 0.0467832000, 0.0842695000, 0.1967469000, 0.5285685000, 1.4996099000", \ - "0.0276052000, 0.0330634000, 0.0466648000, 0.0842315000, 0.1971114000, 0.5277800000, 1.5002349000", \ - "0.0275900000, 0.0331172000, 0.0467794000, 0.0843188000, 0.1967884000, 0.5278354000, 1.4966428000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.1169294000, 0.1223523000, 0.1344965000, 0.1590650000, 0.2108516000, 0.3276457000, 0.6477487000", \ - "0.1221847000, 0.1276018000, 0.1397433000, 0.1643567000, 0.2161792000, 0.3329818000, 0.6531439000", \ - "0.1352956000, 0.1407232000, 0.1529633000, 0.1774713000, 0.2293447000, 0.3461939000, 0.6667047000", \ - "0.1673032000, 0.1726766000, 0.1847837000, 0.2093789000, 0.2612912000, 0.3781515000, 0.6984934000", \ - "0.2420177000, 0.2475142000, 0.2597224000, 0.2844238000, 0.3364204000, 0.4532570000, 0.7737187000", \ - "0.3750999000, 0.3824332000, 0.3984243000, 0.4288237000, 0.4860115000, 0.6034386000, 0.9237215000", \ - "0.5878161000, 0.5974984000, 0.6192328000, 0.6604822000, 0.7313559000, 0.8506728000, 1.1705819000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.1076780000, 0.1140971000, 0.1291108000, 0.1632149000, 0.2480659000, 0.4824239000, 1.1583215000", \ - "0.1120269000, 0.1184310000, 0.1334375000, 0.1676023000, 0.2523540000, 0.4869005000, 1.1598238000", \ - "0.1206118000, 0.1269920000, 0.1419509000, 0.1760469000, 0.2610884000, 0.4956391000, 1.1679719000", \ - "0.1393322000, 0.1457511000, 0.1607631000, 0.1947927000, 0.2798674000, 0.5146767000, 1.1883523000", \ - "0.1747448000, 0.1815487000, 0.1973998000, 0.2322123000, 0.3181471000, 0.5531540000, 1.2286305000", \ - "0.2238437000, 0.2319924000, 0.2497896000, 0.2875108000, 0.3749865000, 0.6110670000, 1.2874990000", \ - "0.2667703000, 0.2775180000, 0.3006501000, 0.3450722000, 0.4376730000, 0.6742926000, 1.3477913000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0228392000, 0.0263130000, 0.0345965000, 0.0546143000, 0.1042295000, 0.2406623000, 0.6663695000", \ - "0.0227307000, 0.0264794000, 0.0344543000, 0.0546502000, 0.1042382000, 0.2405681000, 0.6655255000", \ - "0.0227410000, 0.0263531000, 0.0346190000, 0.0546024000, 0.1045352000, 0.2408104000, 0.6723583000", \ - "0.0228273000, 0.0261503000, 0.0348882000, 0.0545920000, 0.1042298000, 0.2407529000, 0.6710236000", \ - "0.0241253000, 0.0274510000, 0.0354323000, 0.0551596000, 0.1043754000, 0.2405715000, 0.6687930000", \ - "0.0354009000, 0.0396614000, 0.0485913000, 0.0678997000, 0.1118042000, 0.2417154000, 0.6713120000", \ - "0.0535454000, 0.0591114000, 0.0712732000, 0.0947353000, 0.1321020000, 0.2456281000, 0.6665988000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014418200, 0.0041576900, 0.0119893000, 0.0345728000, 0.0996954000, 0.2874860000"); - values("0.0260281000, 0.0311559000, 0.0452155000, 0.0831704000, 0.1966476000, 0.5272989000, 1.5016423000", \ - "0.0257745000, 0.0312570000, 0.0452018000, 0.0830562000, 0.1964274000, 0.5271681000, 1.4966995000", \ - "0.0257988000, 0.0313216000, 0.0452086000, 0.0831828000, 0.1966206000, 0.5280397000, 1.4945362000", \ - "0.0259272000, 0.0310572000, 0.0451346000, 0.0830486000, 0.1966082000, 0.5277539000, 1.4939062000", \ - "0.0286353000, 0.0339907000, 0.0477468000, 0.0850171000, 0.1970422000, 0.5278457000, 1.4992101000", \ - "0.0352089000, 0.0410066000, 0.0544902000, 0.0904635000, 0.2002458000, 0.5297357000, 1.5032258000", \ - "0.0487655000, 0.0555734000, 0.0706657000, 0.1054644000, 0.2070453000, 0.5315204000, 1.4943818000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("0.0011750000, 0.0052815000, 0.0136203000, 0.0214710000, 0.0039981000, -0.097150500, -0.426188300", \ - "0.0012178000, 0.0053125000, 0.0136174000, 0.0214225000, 0.0039479000, -0.097263800, -0.426320500", \ - "0.0013149000, 0.0053992000, 0.0136752000, 0.0214281000, 0.0039116000, -0.097350200, -0.426382600", \ - "0.0012821000, 0.0053460000, 0.0135925000, 0.0213068000, 0.0036884000, -0.097531900, -0.426639500", \ - "0.0012163000, 0.0052800000, 0.0135088000, 0.0212044000, 0.0035809000, -0.097654600, -0.426742500", \ - "0.0010839000, 0.0051728000, 0.0134557000, 0.0212409000, 0.0037154000, -0.097488900, -0.426562500", \ - "0.0008147000, 0.0050127000, 0.0135448000, 0.0217420000, 0.0043548000, -0.096832500, -0.425853900"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.002886500, -0.000550000, 0.0058415000, 0.0223042000, 0.0644157000, 0.1792786000, 0.5111095000", \ - "-0.002847100, -0.000525500, 0.0058565000, 0.0222967000, 0.0643091000, 0.1786275000, 0.5135102000", \ - "-0.002747600, -0.000434700, 0.0059128000, 0.0223519000, 0.0641131000, 0.1791674000, 0.5136458000", \ - "-0.002783700, -0.000474200, 0.0058927000, 0.0222892000, 0.0641234000, 0.1798956000, 0.5115000000", \ - "-0.002865300, -0.000552600, 0.0058259000, 0.0222548000, 0.0640565000, 0.1790023000, 0.5136078000", \ - "-0.003052200, -0.000727400, 0.0056626000, 0.0221138000, 0.0640244000, 0.1790457000, 0.5133473000", \ - "-0.003425500, -0.000994200, 0.0055775000, 0.0222530000, 0.0643289000, 0.1796664000, 0.5114168000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.002391700, 0.0020779000, 0.0112328000, 0.0204295000, 0.0042737000, -0.095997300, -0.424697400", \ - "-0.002350000, 0.0021064000, 0.0112496000, 0.0204223000, 0.0042729000, -0.096060000, -0.424761900", \ - "-0.002257300, 0.0021834000, 0.0112913000, 0.0204040000, 0.0042133000, -0.096190300, -0.424907100", \ - "-0.002290000, 0.0021235000, 0.0111510000, 0.0201512000, 0.0038112000, -0.096581300, -0.425325700", \ - "-0.002334000, 0.0020589000, 0.0110605000, 0.0199941000, 0.0036022000, -0.096895300, -0.425667900", \ - "-0.002406800, 0.0019934000, 0.0109946000, 0.0199440000, 0.0035802000, -0.096895500, -0.425633500", \ - "-0.002525900, 0.0019693000, 0.0111830000, 0.0204852000, 0.0042189000, -0.096296200, -0.424980400"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.003753300, -0.001296200, 0.0054056000, 0.0222636000, 0.0646121000, 0.1807523000, 0.5120145000", \ - "-0.003710900, -0.001263100, 0.0054233000, 0.0223165000, 0.0647314000, 0.1794690000, 0.5142775000", \ - "-0.003625200, -0.001199500, 0.0054000000, 0.0222284000, 0.0645996000, 0.1804339000, 0.5139769000", \ - "-0.003649100, -0.001241800, 0.0053459000, 0.0221156000, 0.0642103000, 0.1801739000, 0.5114656000", \ - "-0.003686400, -0.001286600, 0.0052841000, 0.0220398000, 0.0641086000, 0.1799134000, 0.5146861000", \ - "-0.003755100, -0.001346000, 0.0052157000, 0.0219736000, 0.0641092000, 0.1791930000, 0.5110504000", \ - "-0.003853500, -0.001329400, 0.0054461000, 0.0223927000, 0.0647452000, 0.1803403000, 0.5112068000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("0.0041496000, 0.0074284000, 0.0138883000, 0.0186810000, -0.001880500, -0.104883500, -0.434827500", \ - "0.0041332000, 0.0074100000, 0.0138542000, 0.0186191000, -0.001969000, -0.105001500, -0.434955500", \ - "0.0040988000, 0.0073603000, 0.0137741000, 0.0184807000, -0.002101500, -0.105190500, -0.435155500", \ - "0.0040876000, 0.0073190000, 0.0136591000, 0.0182634000, -0.002432100, -0.105619700, -0.435570700", \ - "0.0040922000, 0.0072988000, 0.0135953000, 0.0181120000, -0.002727000, -0.105940600, -0.435939700", \ - "0.0041336000, 0.0073577000, 0.0137074000, 0.0182684000, -0.002564900, -0.105705500, -0.435675900", \ - "0.0042565000, 0.0075553000, 0.0141109000, 0.0189479000, -0.001591100, -0.104770400, -0.434699800"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.001005600, 0.0012178000, 0.0074104000, 0.0234556000, 0.0648588000, 0.1794125000, 0.5135644000", \ - "-0.001029400, 0.0011798000, 0.0073474000, 0.0233558000, 0.0647627000, 0.1793512000, 0.5107090000", \ - "-0.001068800, 0.0011371000, 0.0072736000, 0.0232614000, 0.0646070000, 0.1801517000, 0.5133872000", \ - "-0.001087200, 0.0010918000, 0.0071908000, 0.0230851000, 0.0643769000, 0.1788766000, 0.5103216000", \ - "-0.001110900, 0.0010432000, 0.0070558000, 0.0228252000, 0.0639938000, 0.1794244000, 0.5125846000", \ - "-0.001137100, 0.0009890000, 0.0069672000, 0.0226492000, 0.0637828000, 0.1782770000, 0.5092962000", \ - "-0.001081200, 0.0011649000, 0.0073043000, 0.0232620000, 0.0646148000, 0.1790202000, 0.5140233000"); - } - } - max_capacitance : 0.3140360000; - max_transition : 1.5032170000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.4262428000, 0.4310812000, 0.4416838000, 0.4635325000, 0.5100315000, 0.6267016000, 0.9612068000", \ - "0.4308374000, 0.4355911000, 0.4462390000, 0.4681144000, 0.5145173000, 0.6313998000, 0.9664887000", \ - "0.4420838000, 0.4468395000, 0.4574862000, 0.4793609000, 0.5257644000, 0.6426477000, 0.9777291000", \ - "0.4628455000, 0.4676400000, 0.4782713000, 0.5001345000, 0.5466460000, 0.6633927000, 0.9987098000", \ - "0.4900656000, 0.4948735000, 0.5054889000, 0.5273433000, 0.5738460000, 0.6905531000, 1.0248401000", \ - "0.5212553000, 0.5260113000, 0.5366623000, 0.5584241000, 0.6049098000, 0.7216537000, 1.0561282000", \ - "0.5442106000, 0.5490481000, 0.5596525000, 0.5815027000, 0.6280039000, 0.7446749000, 1.0786992000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3234544000, 0.3288313000, 0.3414029000, 0.3712801000, 0.4512393000, 0.6834078000, 1.3613329000", \ - "0.3283813000, 0.3337824000, 0.3463883000, 0.3762821000, 0.4565163000, 0.6878510000, 1.3669427000", \ - "0.3415306000, 0.3469302000, 0.3595268000, 0.3894084000, 0.4694432000, 0.7008353000, 1.3787859000", \ - "0.3727958000, 0.3781580000, 0.3907993000, 0.4206461000, 0.5008695000, 0.7326733000, 1.4100954000", \ - "0.4297555000, 0.4351156000, 0.4477578000, 0.4776098000, 0.5576298000, 0.7888080000, 1.4653356000", \ - "0.5184916000, 0.5238716000, 0.5365300000, 0.5664586000, 0.6465344000, 0.8778366000, 1.5546089000", \ - "0.6587347000, 0.6640986000, 0.6767437000, 0.7066075000, 0.7867585000, 1.0181281000, 1.6954975000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0196435000, 0.0228319000, 0.0299289000, 0.0479551000, 0.0959277000, 0.2430290000, 0.6963873000", \ - "0.0197760000, 0.0228594000, 0.0302106000, 0.0478797000, 0.0960286000, 0.2439618000, 0.6962742000", \ - "0.0197750000, 0.0228565000, 0.0302132000, 0.0478828000, 0.0961731000, 0.2440036000, 0.6935416000", \ - "0.0198092000, 0.0228390000, 0.0302530000, 0.0479431000, 0.0960485000, 0.2428493000, 0.6948233000", \ - "0.0198300000, 0.0228351000, 0.0298756000, 0.0479653000, 0.0960443000, 0.2435434000, 0.6961534000", \ - "0.0198594000, 0.0228670000, 0.0298643000, 0.0478481000, 0.0961532000, 0.2431796000, 0.6977299000", \ - "0.0196287000, 0.0228360000, 0.0298781000, 0.0479573000, 0.0959390000, 0.2435247000, 0.6867960000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0206859000, 0.0250964000, 0.0370737000, 0.0729757000, 0.1845681000, 0.5182315000, 1.4954795000", \ - "0.0207340000, 0.0250566000, 0.0370844000, 0.0731047000, 0.1845767000, 0.5186140000, 1.5023235000", \ - "0.0207202000, 0.0250686000, 0.0371246000, 0.0731022000, 0.1848284000, 0.5186496000, 1.4981254000", \ - "0.0206647000, 0.0250422000, 0.0371130000, 0.0730928000, 0.1846567000, 0.5198267000, 1.5002530000", \ - "0.0206658000, 0.0250475000, 0.0371138000, 0.0730810000, 0.1848289000, 0.5188956000, 1.5017282000", \ - "0.0207056000, 0.0251196000, 0.0369795000, 0.0730384000, 0.1848148000, 0.5187535000, 1.5004755000", \ - "0.0206690000, 0.0250405000, 0.0371137000, 0.0730818000, 0.1848986000, 0.5175206000, 1.4971042000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3909046000, 0.3956898000, 0.4063741000, 0.4280671000, 0.4746524000, 0.5914528000, 0.9260896000", \ - "0.3954930000, 0.4001883000, 0.4109363000, 0.4327569000, 0.4792137000, 0.5961370000, 0.9311419000", \ - "0.4063312000, 0.4110563000, 0.4217298000, 0.4435673000, 0.4899784000, 0.6068082000, 0.9413749000", \ - "0.4301461000, 0.4349209000, 0.4455701000, 0.4673436000, 0.5138412000, 0.6306501000, 0.9654691000", \ - "0.4699260000, 0.4747041000, 0.4853412000, 0.5071628000, 0.5536542000, 0.6704560000, 1.0055274000", \ - "0.5250961000, 0.5298715000, 0.5405426000, 0.5622238000, 0.6087350000, 0.7255314000, 1.0604929000", \ - "0.5931703000, 0.5979324000, 0.6086125000, 0.6304520000, 0.6768963000, 0.7936476000, 1.1288969000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3694507000, 0.3748453000, 0.3874755000, 0.4171862000, 0.4974370000, 0.7290221000, 1.4064387000", \ - "0.3739496000, 0.3793964000, 0.3920626000, 0.4219176000, 0.5020885000, 0.7333530000, 1.4134560000", \ - "0.3851536000, 0.3905736000, 0.4030833000, 0.4330722000, 0.5132960000, 0.7450562000, 1.4236820000", \ - "0.4097215000, 0.4150865000, 0.4277051000, 0.4575815000, 0.5376238000, 0.7691349000, 1.4471122000", \ - "0.4482552000, 0.4536987000, 0.4663565000, 0.4962409000, 0.5762096000, 0.8081862000, 1.4859585000", \ - "0.4999293000, 0.5053181000, 0.5178227000, 0.5477566000, 0.6281135000, 0.8600168000, 1.5383980000", \ - "0.5566895000, 0.5621368000, 0.5747597000, 0.6045318000, 0.6845967000, 0.9161402000, 1.5948135000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0196638000, 0.0226343000, 0.0301953000, 0.0477577000, 0.0957870000, 0.2438032000, 0.6880606000", \ - "0.0195500000, 0.0226022000, 0.0299171000, 0.0479693000, 0.0957011000, 0.2443051000, 0.6892463000", \ - "0.0196987000, 0.0226667000, 0.0301649000, 0.0476736000, 0.0957283000, 0.2430488000, 0.6910909000", \ - "0.0196073000, 0.0226749000, 0.0298705000, 0.0475937000, 0.0961229000, 0.2426255000, 0.6884189000", \ - "0.0195692000, 0.0226101000, 0.0302455000, 0.0479596000, 0.0954835000, 0.2439749000, 0.6958338000", \ - "0.0197278000, 0.0227553000, 0.0298716000, 0.0477244000, 0.0958743000, 0.2439818000, 0.6948057000", \ - "0.0195422000, 0.0226770000, 0.0299526000, 0.0479929000, 0.0957971000, 0.2441930000, 0.6867962000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0205421000, 0.0250883000, 0.0371208000, 0.0731523000, 0.1848141000, 0.5192039000, 1.5028313000", \ - "0.0207184000, 0.0251063000, 0.0370434000, 0.0728821000, 0.1849619000, 0.5182516000, 1.4968513000", \ - "0.0206190000, 0.0250804000, 0.0372438000, 0.0729555000, 0.1846723000, 0.5175010000, 1.4997150000", \ - "0.0205020000, 0.0250884000, 0.0371221000, 0.0731022000, 0.1850571000, 0.5184945000, 1.5032170000", \ - "0.0207367000, 0.0250582000, 0.0370903000, 0.0730922000, 0.1845026000, 0.5192353000, 1.5017135000", \ - "0.0205777000, 0.0250747000, 0.0371153000, 0.0730517000, 0.1850827000, 0.5190002000, 1.4986470000", \ - "0.0206236000, 0.0250835000, 0.0371008000, 0.0731469000, 0.1845569000, 0.5178610000, 1.4944707000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.1940298000, 0.1988643000, 0.2094627000, 0.2313085000, 0.2777322000, 0.3944066000, 0.7285688000", \ - "0.1982796000, 0.2031122000, 0.2137100000, 0.2355508000, 0.2819840000, 0.3986360000, 0.7327606000", \ - "0.2068997000, 0.2116510000, 0.2222890000, 0.2441495000, 0.2905270000, 0.4073591000, 0.7426473000", \ - "0.2254624000, 0.2302265000, 0.2408390000, 0.2626736000, 0.3090572000, 0.4259289000, 0.7610262000", \ - "0.2630295000, 0.2678096000, 0.2784653000, 0.3003008000, 0.3468223000, 0.4635704000, 0.7989626000", \ - "0.3183082000, 0.3231646000, 0.3339481000, 0.3560049000, 0.4026983000, 0.5195588000, 0.8545963000", \ - "0.3769274000, 0.3819891000, 0.3932621000, 0.4155773000, 0.4628468000, 0.5800121000, 0.9147145000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.2067192000, 0.2122626000, 0.2250631000, 0.2551219000, 0.3352706000, 0.5671031000, 1.2439971000", \ - "0.2120969000, 0.2175173000, 0.2303656000, 0.2604887000, 0.3404070000, 0.5729291000, 1.2521184000", \ - "0.2250594000, 0.2305726000, 0.2433395000, 0.2734317000, 0.3535860000, 0.5853220000, 1.2616475000", \ - "0.2569463000, 0.2623670000, 0.2752177000, 0.3053418000, 0.3852602000, 0.6177940000, 1.2970436000", \ - "0.3320614000, 0.3376168000, 0.3503693000, 0.3804358000, 0.4605840000, 0.6924105000, 1.3691213000", \ - "0.4814940000, 0.4870309000, 0.5002724000, 0.5304986000, 0.6106686000, 0.8433894000, 1.5223122000", \ - "0.7265809000, 0.7326841000, 0.7470190000, 0.7779946000, 0.8582204000, 1.0901713000, 1.7659882000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0194898000, 0.0226311000, 0.0297334000, 0.0478737000, 0.0957565000, 0.2431192000, 0.6978083000", \ - "0.0194945000, 0.0226135000, 0.0297436000, 0.0478669000, 0.0957144000, 0.2431869000, 0.6904071000", \ - "0.0196479000, 0.0227422000, 0.0300734000, 0.0477548000, 0.0959131000, 0.2439227000, 0.6911431000", \ - "0.0196760000, 0.0226744000, 0.0301198000, 0.0478234000, 0.0960824000, 0.2441073000, 0.6918677000", \ - "0.0197892000, 0.0228011000, 0.0298435000, 0.0476761000, 0.0959573000, 0.2437471000, 0.6925026000", \ - "0.0202874000, 0.0234089000, 0.0307573000, 0.0484586000, 0.0965330000, 0.2424385000, 0.6982429000", \ - "0.0218855000, 0.0251824000, 0.0323182000, 0.0497930000, 0.0971635000, 0.2435956000, 0.6899287000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0214347000, 0.0257876000, 0.0377075000, 0.0734372000, 0.1849112000, 0.5201646000, 1.4994380000", \ - "0.0212014000, 0.0258335000, 0.0377525000, 0.0735961000, 0.1849170000, 0.5194111000, 1.4954645000", \ - "0.0213840000, 0.0257733000, 0.0377663000, 0.0735139000, 0.1849553000, 0.5200911000, 1.4979481000", \ - "0.0212171000, 0.0258454000, 0.0377576000, 0.0735977000, 0.1849170000, 0.5194354000, 1.4959743000", \ - "0.0214124000, 0.0256429000, 0.0376918000, 0.0735740000, 0.1849605000, 0.5201783000, 1.4983189000", \ - "0.0228896000, 0.0274719000, 0.0390211000, 0.0739194000, 0.1847843000, 0.5196456000, 1.4958407000", \ - "0.0273751000, 0.0314359000, 0.0424277000, 0.0756980000, 0.1849041000, 0.5167307000, 1.5018057000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0024270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043701000, 0.0044027000, 0.0044779000, 0.0044832000, 0.0044953000, 0.0045234000, 0.0045882000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004325100, -0.004300700, -0.004244400, -0.004257000, -0.004286200, -0.004353100, -0.004507400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025740000; - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.021193400, 0.0538717000, 0.0713685000", \ - "-0.182928400, -0.112746100, -0.095249300", \ - "-0.345688800, -0.280389300, -0.268996100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0398418000, -0.034002600, -0.053940800", \ - "0.2076803000, 0.1362773000, 0.1163392000", \ - "0.3838685000, 0.3136862000, 0.2949688000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1555040000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtn_1") { - leakage_power () { - value : 0.0083801000; - when : "RESET_B&D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0063420000; - when : "RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0061375000; - when : "!RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0064211000; - when : "RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0082856000; - when : "RESET_B&D&GATE_N&Q"; - } - leakage_power () { - value : 0.0077141000; - when : "!RESET_B&D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0060583000; - when : "!RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0075076000; - when : "!RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0077913000; - when : "RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0074593000; - when : "RESET_B&!D&GATE_N&Q"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__dlrtn"; - cell_leakage_power : 0.0072096790; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181794000, 0.0180656000, 0.0178032000, 0.0178827000, 0.0180661000, 0.0184888000, 0.0194630000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092039000, 0.0091026000, 0.0088692000, 0.0089263000, 0.0090579000, 0.0093612000, 0.0100605000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018800000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1130840000, 0.2723776000, 0.4436829000", \ - "0.0758607000, 0.2339336000, 0.4003561000", \ - "0.0986471000, 0.2493958000, 0.4121562000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.2540671000, 0.2862122000", \ - "0.0526673000, 0.1374980000, 0.1696432000", \ - "-0.018540400, 0.0662904000, 0.0996563000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.100539100, -0.262274100, -0.434800100", \ - "-0.054770800, -0.216505900, -0.385369800", \ - "-0.054363900, -0.214878300, -0.383742200"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.159132800, -0.245184200, -0.277329400", \ - "-0.042563800, -0.127394500, -0.160760400", \ - "0.0274232000, -0.057407600, -0.090773400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171556000, 0.0170282000, 0.0167343000, 0.0168041000, 0.0169648000, 0.0173352000, 0.0181889000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103342000, 0.0102020000, 0.0098973000, 0.0099397000, 0.0100375000, 0.0102628000, 0.0107821000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1412233000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0097278000, 0.0088516000, 0.0063177000, -0.001718500, -0.024607500, -0.085111900, -0.243382900", \ - "0.0096193000, 0.0087642000, 0.0062822000, -0.001817000, -0.024706300, -0.085188700, -0.243465300", \ - "0.0097337000, 0.0088583000, 0.0063503000, -0.001721200, -0.024623400, -0.085112800, -0.243372900", \ - "0.0096127000, 0.0087394000, 0.0061936000, -0.001845600, -0.024731500, -0.085204100, -0.243428800", \ - "0.0095039000, 0.0086148000, 0.0060790000, -0.001957700, -0.024839400, -0.085334400, -0.243611100", \ - "0.0104386000, 0.0092380000, 0.0060145000, -0.002232700, -0.025050200, -0.085555600, -0.243808500", \ - "0.0109456000, 0.0097143000, 0.0065883000, -0.002072200, -0.025117700, -0.085488600, -0.243716000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0140014000, 0.0155532000, 0.0193955000, 0.0285237000, 0.0515422000, 0.1119055000, 0.2689820000", \ - "0.0139111000, 0.0154242000, 0.0192328000, 0.0284022000, 0.0513822000, 0.1117958000, 0.2698627000", \ - "0.0139525000, 0.0154662000, 0.0192740000, 0.0284440000, 0.0514248000, 0.1118322000, 0.2696949000", \ - "0.0137061000, 0.0152593000, 0.0190855000, 0.0281765000, 0.0512189000, 0.1113287000, 0.2689930000", \ - "0.0134957000, 0.0150478000, 0.0188842000, 0.0280185000, 0.0510416000, 0.1109168000, 0.2677278000", \ - "0.0138678000, 0.0151609000, 0.0188180000, 0.0280311000, 0.0509464000, 0.1113397000, 0.2690842000", \ - "0.0148771000, 0.0161773000, 0.0196287000, 0.0285999000, 0.0515256000, 0.1116153000, 0.2671746000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0187241000, 0.0178618000, 0.0153460000, 0.0073118000, -0.015560300, -0.076073900, -0.234313400", \ - "0.0188133000, 0.0179317000, 0.0154077000, 0.0073531000, -0.015503500, -0.076005500, -0.234277900", \ - "0.0188791000, 0.0179735000, 0.0154823000, 0.0074342000, -0.015432100, -0.075935200, -0.234191500", \ - "0.0186112000, 0.0177077000, 0.0152147000, 0.0071677000, -0.015692800, -0.076206600, -0.234424300", \ - "0.0182828000, 0.0173747000, 0.0148569000, 0.0068184000, -0.016045600, -0.076550600, -0.234807900", \ - "0.0176626000, 0.0167856000, 0.0143940000, 0.0064844000, -0.016366100, -0.076862800, -0.235112000", \ - "0.0195006000, 0.0182962000, 0.0150901000, 0.0064517000, -0.016572400, -0.076861600, -0.235105100"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0199077000, 0.0214594000, 0.0252793000, 0.0344035000, 0.0574704000, 0.1172487000, 0.2740701000", \ - "0.0198428000, 0.0213972000, 0.0252129000, 0.0343639000, 0.0574889000, 0.1177481000, 0.2755231000", \ - "0.0199766000, 0.0215154000, 0.0253287000, 0.0344624000, 0.0575441000, 0.1173709000, 0.2741760000", \ - "0.0197801000, 0.0213159000, 0.0251363000, 0.0342755000, 0.0572921000, 0.1175336000, 0.2750419000", \ - "0.0195057000, 0.0210687000, 0.0248545000, 0.0340118000, 0.0570693000, 0.1175002000, 0.2736978000", \ - "0.0193176000, 0.0208770000, 0.0246746000, 0.0338397000, 0.0569217000, 0.1173042000, 0.2742038000", \ - "0.0202363000, 0.0215738000, 0.0250545000, 0.0340330000, 0.0572103000, 0.1168842000, 0.2750054000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0159852000, 0.0156966000, 0.0152834000, 0.0102784000, -0.012452600, -0.073047400, -0.231365900", \ - "0.0158261000, 0.0156387000, 0.0150631000, 0.0101495000, -0.012545900, -0.073123400, -0.231429100", \ - "0.0155011000, 0.0152051000, 0.0147947000, 0.0098136000, -0.012875000, -0.073436600, -0.231802900", \ - "0.0153487000, 0.0149645000, 0.0145753000, 0.0095967000, -0.013072000, -0.073640400, -0.231935900", \ - "0.0152830000, 0.0147756000, 0.0142308000, 0.0091539000, -0.013499900, -0.074014600, -0.232288700", \ - "0.0225128000, 0.0212278000, 0.0178793000, 0.0090797000, -0.013541400, -0.074048400, -0.232313300", \ - "0.0240057000, 0.0226713000, 0.0192342000, 0.0103679000, -0.012783900, -0.073114100, -0.231319800"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0155226000, 0.0170372000, 0.0207313000, 0.0297316000, 0.0525490000, 0.1128493000, 0.2705187000", \ - "0.0152109000, 0.0167161000, 0.0204224000, 0.0294187000, 0.0522614000, 0.1121660000, 0.2699181000", \ - "0.0149024000, 0.0164107000, 0.0200968000, 0.0290802000, 0.0519800000, 0.1118333000, 0.2700931000", \ - "0.0146571000, 0.0161036000, 0.0197888000, 0.0288144000, 0.0518090000, 0.1121461000, 0.2686605000", \ - "0.0146637000, 0.0159962000, 0.0196776000, 0.0285049000, 0.0515863000, 0.1114507000, 0.2685377000", \ - "0.0153050000, 0.0166181000, 0.0200073000, 0.0287715000, 0.0519230000, 0.1118771000, 0.2683634000", \ - "0.0165801000, 0.0178063000, 0.0212633000, 0.0300695000, 0.0531726000, 0.1132678000, 0.2695883000"); - } - } - max_capacitance : 0.1583960000; - max_transition : 1.5037500000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2080104000, 0.2133880000, 0.2247481000, 0.2474234000, 0.2960079000, 0.4140576000, 0.7206921000", \ - "0.2129298000, 0.2183798000, 0.2297058000, 0.2524047000, 0.3009654000, 0.4190799000, 0.7256507000", \ - "0.2260927000, 0.2315389000, 0.2428633000, 0.2655652000, 0.3141755000, 0.4323615000, 0.7394871000", \ - "0.2573300000, 0.2627273000, 0.2741081000, 0.2967613000, 0.3453496000, 0.4634075000, 0.7696513000", \ - "0.3143067000, 0.3196953000, 0.3310538000, 0.3537365000, 0.4023286000, 0.5203826000, 0.8267447000", \ - "0.4031190000, 0.4085620000, 0.4199063000, 0.4425844000, 0.4912190000, 0.6093314000, 0.9168781000", \ - "0.5434045000, 0.5487907000, 0.5601620000, 0.5828680000, 0.6314944000, 0.7495767000, 1.0558469000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.3107341000, 0.3183728000, 0.3351828000, 0.3735012000, 0.4687959000, 0.7145095000, 1.3574724000", \ - "0.3154972000, 0.3228730000, 0.3398209000, 0.3781138000, 0.4731246000, 0.7189764000, 1.3623761000", \ - "0.3267266000, 0.3341000000, 0.3510489000, 0.3893406000, 0.4843626000, 0.7301844000, 1.3738712000", \ - "0.3474451000, 0.3550343000, 0.3718796000, 0.4100554000, 0.5054093000, 0.7506890000, 1.3945739000", \ - "0.3746147000, 0.3822923000, 0.3991430000, 0.4374251000, 0.5327812000, 0.7783704000, 1.4195140000", \ - "0.4057756000, 0.4133765000, 0.4301192000, 0.4683908000, 0.5633266000, 0.8091654000, 1.4536087000", \ - "0.4287158000, 0.4361399000, 0.4531004000, 0.4914025000, 0.5864334000, 0.8323863000, 1.4712769000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0174158000, 0.0216363000, 0.0304412000, 0.0523278000, 0.1078761000, 0.2597983000, 0.6673912000", \ - "0.0174822000, 0.0216646000, 0.0307917000, 0.0521685000, 0.1075474000, 0.2616135000, 0.6686264000", \ - "0.0173997000, 0.0214891000, 0.0303846000, 0.0521555000, 0.1078469000, 0.2627054000, 0.6728536000", \ - "0.0176408000, 0.0213512000, 0.0305978000, 0.0523351000, 0.1078744000, 0.2610163000, 0.6673918000", \ - "0.0174614000, 0.0216502000, 0.0304667000, 0.0523200000, 0.1078765000, 0.2605673000, 0.6688834000", \ - "0.0174954000, 0.0213954000, 0.0305005000, 0.0522556000, 0.1072493000, 0.2620582000, 0.6725974000", \ - "0.0174969000, 0.0217284000, 0.0305448000, 0.0523675000, 0.1079055000, 0.2607936000, 0.6632349000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0263232000, 0.0332247000, 0.0509027000, 0.0993570000, 0.2309771000, 0.5793059000, 1.4957471000", \ - "0.0261672000, 0.0332075000, 0.0509774000, 0.0992493000, 0.2310547000, 0.5809053000, 1.5012830000", \ - "0.0261614000, 0.0332057000, 0.0509769000, 0.0992639000, 0.2310118000, 0.5808728000, 1.5012619000", \ - "0.0262454000, 0.0330156000, 0.0508630000, 0.0993337000, 0.2313730000, 0.5799633000, 1.4976118000", \ - "0.0262826000, 0.0331867000, 0.0508403000, 0.0993222000, 0.2307725000, 0.5793841000, 1.4995548000", \ - "0.0261557000, 0.0330746000, 0.0509623000, 0.0993583000, 0.2312101000, 0.5808117000, 1.5020983000", \ - "0.0261924000, 0.0332667000, 0.0509791000, 0.0990686000, 0.2313299000, 0.5807629000, 1.4951278000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.2328705000, 0.2384029000, 0.2498532000, 0.2727271000, 0.3213396000, 0.4396367000, 0.7478425000", \ - "0.2378389000, 0.2433511000, 0.2548007000, 0.2776907000, 0.3263270000, 0.4445572000, 0.7514329000", \ - "0.2505531000, 0.2561185000, 0.2675428000, 0.2904237000, 0.3390514000, 0.4572516000, 0.7641742000", \ - "0.2812302000, 0.2867826000, 0.2982106000, 0.3210747000, 0.3697502000, 0.4878664000, 0.7943329000", \ - "0.3479469000, 0.3534976000, 0.3649417000, 0.3878158000, 0.4364527000, 0.5546676000, 0.8616018000", \ - "0.4600858000, 0.4656301000, 0.4770889000, 0.5000059000, 0.5486397000, 0.6668649000, 0.9748993000", \ - "0.6335228000, 0.6391015000, 0.6506110000, 0.6735238000, 0.7223471000, 0.8410005000, 1.1477861000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.3703716000, 0.3780765000, 0.3949884000, 0.4333815000, 0.5287283000, 0.7737766000, 1.4157392000", \ - "0.3751755000, 0.3828418000, 0.3997741000, 0.4381803000, 0.5332257000, 0.7791863000, 1.4197016000", \ - "0.3880184000, 0.3956535000, 0.4125511000, 0.4509433000, 0.5461763000, 0.7915435000, 1.4339538000", \ - "0.4189617000, 0.4266448000, 0.4435639000, 0.4819486000, 0.5771944000, 0.8229166000, 1.4659716000", \ - "0.4847445000, 0.4924303000, 0.5093494000, 0.5477286000, 0.6429672000, 0.8883946000, 1.5305165000", \ - "0.5905645000, 0.5982281000, 0.6151601000, 0.6535382000, 0.7489065000, 0.9939600000, 1.6350937000", \ - "0.7527601000, 0.7604405000, 0.7773494000, 0.8157255000, 0.9109424000, 1.1565934000, 1.7987226000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0178733000, 0.0219505000, 0.0307609000, 0.0527602000, 0.1078608000, 0.2606722000, 0.6684909000", \ - "0.0179760000, 0.0218205000, 0.0309769000, 0.0527091000, 0.1080665000, 0.2613727000, 0.6666204000", \ - "0.0178439000, 0.0217833000, 0.0310558000, 0.0527502000, 0.1080625000, 0.2611600000, 0.6702660000", \ - "0.0178471000, 0.0217688000, 0.0310555000, 0.0527315000, 0.1079555000, 0.2625382000, 0.6673784000", \ - "0.0180047000, 0.0218575000, 0.0310634000, 0.0527719000, 0.1080535000, 0.2612596000, 0.6673723000", \ - "0.0181366000, 0.0219959000, 0.0311518000, 0.0528132000, 0.1080132000, 0.2612216000, 0.6681445000", \ - "0.0182248000, 0.0221408000, 0.0313710000, 0.0524352000, 0.1081804000, 0.2617747000, 0.6624480000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0259917000, 0.0330799000, 0.0509632000, 0.0991527000, 0.2312766000, 0.5790283000, 1.4987611000", \ - "0.0260520000, 0.0330528000, 0.0509624000, 0.0991946000, 0.2311977000, 0.5793107000, 1.5002979000", \ - "0.0260920000, 0.0330957000, 0.0509448000, 0.0991873000, 0.2313262000, 0.5801694000, 1.4963620000", \ - "0.0260726000, 0.0331290000, 0.0509453000, 0.0993181000, 0.2307248000, 0.5792098000, 1.4954545000", \ - "0.0261300000, 0.0330957000, 0.0508546000, 0.0992978000, 0.2308757000, 0.5804902000, 1.4975132000", \ - "0.0259977000, 0.0330884000, 0.0509412000, 0.0991531000, 0.2312857000, 0.5790549000, 1.4926048000", \ - "0.0260259000, 0.0330053000, 0.0509155000, 0.0992106000, 0.2308881000, 0.5788260000, 1.4958140000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0874533000, 0.0930372000, 0.1046178000, 0.1278226000, 0.1788733000, 0.2977784000, 0.6046808000", \ - "0.0926244000, 0.0981766000, 0.1097216000, 0.1329788000, 0.1840497000, 0.3029343000, 0.6099131000", \ - "0.1055788000, 0.1111278000, 0.1227332000, 0.1460082000, 0.1971331000, 0.3160440000, 0.6230268000", \ - "0.1380330000, 0.1435513000, 0.1550681000, 0.1784293000, 0.2296055000, 0.3485396000, 0.6549950000", \ - "0.2068699000, 0.2131440000, 0.2257334000, 0.2501315000, 0.3017580000, 0.4206273000, 0.7277132000", \ - "0.3192819000, 0.3277530000, 0.3441477000, 0.3734798000, 0.4289351000, 0.5480602000, 0.8548315000", \ - "0.4999155000, 0.5114623000, 0.5338119000, 0.5729571000, 0.6360837000, 0.7549752000, 1.0619149000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0818418000, 0.0889957000, 0.1053213000, 0.1429421000, 0.2376868000, 0.4827722000, 1.1262186000", \ - "0.0859488000, 0.0931858000, 0.1095418000, 0.1471090000, 0.2413840000, 0.4866915000, 1.1301768000", \ - "0.0942687000, 0.1015254000, 0.1177854000, 0.1555401000, 0.2501008000, 0.4952065000, 1.1376409000", \ - "0.1116565000, 0.1189025000, 0.1352982000, 0.1731295000, 0.2678730000, 0.5135735000, 1.1566116000", \ - "0.1394555000, 0.1473152000, 0.1645389000, 0.2031647000, 0.2983828000, 0.5434515000, 1.1840349000", \ - "0.1722269000, 0.1814683000, 0.2000485000, 0.2407844000, 0.3359478000, 0.5819020000, 1.2271727000", \ - "0.1872448000, 0.1997542000, 0.2232031000, 0.2685418000, 0.3656597000, 0.6120542000, 1.2518427000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0182392000, 0.0224376000, 0.0319671000, 0.0546233000, 0.1113802000, 0.2617249000, 0.6685472000", \ - "0.0182846000, 0.0226501000, 0.0316924000, 0.0546791000, 0.1112051000, 0.2612078000, 0.6688216000", \ - "0.0182529000, 0.0223268000, 0.0319782000, 0.0545977000, 0.1111565000, 0.2611127000, 0.6688075000", \ - "0.0183416000, 0.0224925000, 0.0321483000, 0.0546547000, 0.1113000000, 0.2616965000, 0.6723510000", \ - "0.0223436000, 0.0263193000, 0.0351224000, 0.0566657000, 0.1116330000, 0.2609998000, 0.6695984000", \ - "0.0324741000, 0.0373131000, 0.0467686000, 0.0675627000, 0.1177891000, 0.2617260000, 0.6709914000", \ - "0.0479305000, 0.0547114000, 0.0667838000, 0.0892640000, 0.1295010000, 0.2626807000, 0.6622877000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0236707000, 0.0308326000, 0.0490671000, 0.0981746000, 0.2313040000, 0.5812298000, 1.5014884000", \ - "0.0236106000, 0.0307044000, 0.0490633000, 0.0982940000, 0.2311137000, 0.5799173000, 1.4978536000", \ - "0.0237170000, 0.0307695000, 0.0490267000, 0.0982651000, 0.2308601000, 0.5791061000, 1.5037502000", \ - "0.0241418000, 0.0313297000, 0.0494571000, 0.0984070000, 0.2308786000, 0.5805296000, 1.4991871000", \ - "0.0270903000, 0.0341759000, 0.0518399000, 0.1000794000, 0.2311943000, 0.5811522000, 1.4971260000", \ - "0.0339769000, 0.0406330000, 0.0579097000, 0.1033214000, 0.2330296000, 0.5805590000, 1.5014213000", \ - "0.0471065000, 0.0550146000, 0.0736337000, 0.1127687000, 0.2356096000, 0.5826778000, 1.4935095000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0025130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043789000, 0.0044157000, 0.0045006000, 0.0045053000, 0.0045163000, 0.0045417000, 0.0046000000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004338600, -0.004314800, -0.004259800, -0.004273200, -0.004304100, -0.004375400, -0.004539600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026520000; - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.072462900, -0.025474000, -0.040936200", \ - "-0.186590500, -0.138380900, -0.152622400", \ - "-0.259018900, -0.209588500, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0850078000, 0.0380189000, 0.0522604000", \ - "0.1991354000, 0.1497051000, 0.1651673000", \ - "0.2715638000, 0.2221335000, 0.2363750000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1115636000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtn_2") { - leakage_power () { - value : 0.0088043000; - when : "RESET_B&D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0072749000; - when : "RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0071376000; - when : "!RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0074213000; - when : "RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0087098000; - when : "RESET_B&D&GATE_N&Q"; - } - leakage_power () { - value : 0.0087283000; - when : "!RESET_B&D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0069911000; - when : "!RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0084443000; - when : "!RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0087280000; - when : "RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0078809000; - when : "RESET_B&!D&GATE_N&Q"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__dlrtn"; - cell_leakage_power : 0.0080120490; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0180452000, 0.0179261000, 0.0176513000, 0.0177315000, 0.0179162000, 0.0183420000, 0.0193237000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092721000, 0.0091686000, 0.0089300000, 0.0089886000, 0.0091237000, 0.0094351000, 0.0101527000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018510000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1191875000, 0.2797018000, 0.4497864000", \ - "0.0795228000, 0.2375957000, 0.4052389000", \ - "0.1035300000, 0.2530580000, 0.4170391000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1838848000, 0.2674948000, 0.2996400000", \ - "0.0660950000, 0.1484844000, 0.1818503000", \ - "-0.007554000, 0.0772767000, 0.1094219000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.265936200, -0.438462300", \ - "-0.057212200, -0.218947300, -0.389031900", \ - "-0.056805300, -0.217319700, -0.387404300"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.168898400, -0.253729200, -0.287095100", \ - "-0.052329400, -0.135939500, -0.169305300", \ - "0.0200990000, -0.065952500, -0.098097700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171983000, 0.0171041000, 0.0168871000, 0.0169486000, 0.0170904000, 0.0174173000, 0.0181707000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103972000, 0.0102636000, 0.0099557000, 0.0099989000, 0.0100985000, 0.0103279000, 0.0108570000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1489129000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0140588000, 0.0127284000, 0.0091908000, -0.001725300, -0.037063400, -0.141609600, -0.443604500", \ - "0.0139483000, 0.0126276000, 0.0090999000, -0.001792600, -0.037142100, -0.141697400, -0.443692000", \ - "0.0140529000, 0.0127408000, 0.0092135000, -0.001698400, -0.037029700, -0.141592200, -0.443585000", \ - "0.0139610000, 0.0126231000, 0.0091077000, -0.001838500, -0.037139700, -0.141732000, -0.443702600", \ - "0.0138241000, 0.0125088000, 0.0089815000, -0.001962100, -0.037272600, -0.141841600, -0.443826400", \ - "0.0144042000, 0.0129762000, 0.0087917000, -0.002260000, -0.037498300, -0.142044300, -0.444039300", \ - "0.0159595000, 0.0145575000, 0.0104802000, -0.001600500, -0.037541700, -0.142061200, -0.443967000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0194545000, 0.0211670000, 0.0259580000, 0.0389058000, 0.0751638000, 0.1786281000, 0.4778817000", \ - "0.0194349000, 0.0210997000, 0.0259529000, 0.0389014000, 0.0751512000, 0.1794493000, 0.4763158000", \ - "0.0195156000, 0.0212282000, 0.0260250000, 0.0389909000, 0.0753205000, 0.1784725000, 0.4773534000", \ - "0.0191006000, 0.0207968000, 0.0255129000, 0.0386452000, 0.0748500000, 0.1783977000, 0.4768259000", \ - "0.0189782000, 0.0206557000, 0.0253534000, 0.0384376000, 0.0747319000, 0.1781382000, 0.4764611000", \ - "0.0189755000, 0.0206578000, 0.0253780000, 0.0384951000, 0.0745566000, 0.1780596000, 0.4768541000", \ - "0.0202709000, 0.0217951000, 0.0262734000, 0.0390732000, 0.0753692000, 0.1791001000, 0.4757931000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0229729000, 0.0216161000, 0.0180573000, 0.0071733000, -0.028142200, -0.132692300, -0.434678100", \ - "0.0228837000, 0.0215461000, 0.0179741000, 0.0070552000, -0.028246400, -0.132794900, -0.434778500", \ - "0.0230075000, 0.0216071000, 0.0180715000, 0.0071713000, -0.028154100, -0.132689600, -0.434687200", \ - "0.0226316000, 0.0212650000, 0.0177675000, 0.0068535000, -0.028449100, -0.132987100, -0.434997500", \ - "0.0222612000, 0.0209117000, 0.0173024000, 0.0064336000, -0.028885200, -0.133413200, -0.435397000", \ - "0.0218504000, 0.0204654000, 0.0170042000, 0.0061604000, -0.029151700, -0.133682200, -0.435659100", \ - "0.0246307000, 0.0232111000, 0.0190876000, 0.0069857000, -0.028927700, -0.133331300, -0.435293000"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0254411000, 0.0271434000, 0.0319139000, 0.0449548000, 0.0812096000, 0.1853089000, 0.4840355000", \ - "0.0253543000, 0.0270310000, 0.0318150000, 0.0448646000, 0.0811265000, 0.1849306000, 0.4840373000", \ - "0.0253688000, 0.0270280000, 0.0318200000, 0.0448522000, 0.0812131000, 0.1851486000, 0.4823693000", \ - "0.0251693000, 0.0268296000, 0.0316274000, 0.0447235000, 0.0809385000, 0.1851115000, 0.4833442000", \ - "0.0249042000, 0.0265898000, 0.0313893000, 0.0444225000, 0.0808872000, 0.1846950000, 0.4848799000", \ - "0.0247498000, 0.0264355000, 0.0312330000, 0.0442954000, 0.0805846000, 0.1841120000, 0.4843759000", \ - "0.0258469000, 0.0274109000, 0.0318974000, 0.0446686000, 0.0808658000, 0.1843447000, 0.4830779000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0205984000, 0.0194094000, 0.0168686000, 0.0095672000, -0.025199000, -0.129905600, -0.431925800", \ - "0.0203551000, 0.0191555000, 0.0165448000, 0.0093150000, -0.025412000, -0.130093500, -0.432120600", \ - "0.0201323000, 0.0190002000, 0.0163734000, 0.0091420000, -0.025609700, -0.130276900, -0.432328500", \ - "0.0198190000, 0.0185784000, 0.0159563000, 0.0087510000, -0.025929300, -0.130579300, -0.432533100", \ - "0.0196561000, 0.0184347000, 0.0155732000, 0.0083198000, -0.026397100, -0.130929900, -0.432867500", \ - "0.0262101000, 0.0247220000, 0.0204514000, 0.0081142000, -0.026275300, -0.130798400, -0.432714300", \ - "0.0296687000, 0.0277569000, 0.0231918000, 0.0106665000, -0.025699900, -0.130099400, -0.431962600"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0207670000, 0.0224094000, 0.0271680000, 0.0401655000, 0.0761572000, 0.1795098000, 0.4775544000", \ - "0.0206541000, 0.0222893000, 0.0270530000, 0.0400050000, 0.0760783000, 0.1791204000, 0.4777674000", \ - "0.0203212000, 0.0220376000, 0.0268083000, 0.0397722000, 0.0758515000, 0.1787352000, 0.4779411000", \ - "0.0198841000, 0.0215837000, 0.0263569000, 0.0393196000, 0.0754219000, 0.1786963000, 0.4790399000", \ - "0.0198012000, 0.0215456000, 0.0262704000, 0.0390106000, 0.0751980000, 0.1786708000, 0.4776645000", \ - "0.0208835000, 0.0224171000, 0.0268234000, 0.0391546000, 0.0753221000, 0.1784690000, 0.4775954000", \ - "0.0223451000, 0.0238169000, 0.0281058000, 0.0407096000, 0.0768508000, 0.1802859000, 0.4768966000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.5044040000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2227440000, 0.2272939000, 0.2374892000, 0.2585447000, 0.3027573000, 0.4109491000, 0.7143191000", \ - "0.2276745000, 0.2322376000, 0.2425037000, 0.2635411000, 0.3077099000, 0.4158701000, 0.7194403000", \ - "0.2408184000, 0.2453787000, 0.2556424000, 0.2766822000, 0.3208570000, 0.4290399000, 0.7326071000", \ - "0.2721420000, 0.2766745000, 0.2869294000, 0.3079424000, 0.3521446000, 0.4603431000, 0.7647180000", \ - "0.3291481000, 0.3336812000, 0.3439408000, 0.3649508000, 0.4091586000, 0.5173174000, 0.8216430000", \ - "0.4181956000, 0.4227316000, 0.4329412000, 0.4539981000, 0.4981744000, 0.6064000000, 0.9105504000", \ - "0.5586332000, 0.5630754000, 0.5733956000, 0.5944655000, 0.6386450000, 0.7469688000, 1.0514132000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3253202000, 0.3314779000, 0.3457122000, 0.3781787000, 0.4600296000, 0.6893051000, 1.3476956000", \ - "0.3297629000, 0.3358850000, 0.3501911000, 0.3826391000, 0.4643486000, 0.6938836000, 1.3517455000", \ - "0.3411189000, 0.3472752000, 0.3615129000, 0.3939768000, 0.4758257000, 0.7046290000, 1.3671658000", \ - "0.3620275000, 0.3681341000, 0.3822581000, 0.4148693000, 0.4967397000, 0.7254775000, 1.3836363000", \ - "0.3893015000, 0.3954319000, 0.4095354000, 0.4421395000, 0.5240289000, 0.7530787000, 1.4158524000", \ - "0.4203670000, 0.4264580000, 0.4406664000, 0.4731692000, 0.5547928000, 0.7838478000, 1.4441972000", \ - "0.4435279000, 0.4496068000, 0.4638801000, 0.4963918000, 0.5782717000, 0.8073882000, 1.4656800000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0189232000, 0.0218854000, 0.0289147000, 0.0464066000, 0.0920947000, 0.2267748000, 0.6393824000", \ - "0.0188116000, 0.0216804000, 0.0290363000, 0.0462256000, 0.0919215000, 0.2278987000, 0.6325750000", \ - "0.0188050000, 0.0217020000, 0.0290543000, 0.0461611000, 0.0919168000, 0.2279189000, 0.6327124000", \ - "0.0189448000, 0.0217881000, 0.0288580000, 0.0462905000, 0.0918725000, 0.2279521000, 0.6332552000", \ - "0.0188130000, 0.0219623000, 0.0288507000, 0.0462237000, 0.0918423000, 0.2279362000, 0.6331417000", \ - "0.0187957000, 0.0220358000, 0.0289062000, 0.0462511000, 0.0917051000, 0.2279907000, 0.6327516000", \ - "0.0188250000, 0.0218280000, 0.0289431000, 0.0463047000, 0.0918537000, 0.2282331000, 0.6319198000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0255413000, 0.0304922000, 0.0436463000, 0.0808954000, 0.1937820000, 0.5288043000, 1.4977179000", \ - "0.0256735000, 0.0306484000, 0.0436325000, 0.0808980000, 0.1933178000, 0.5276906000, 1.4959665000", \ - "0.0255437000, 0.0304876000, 0.0436277000, 0.0809084000, 0.1938218000, 0.5275765000, 1.5019644000", \ - "0.0252866000, 0.0305375000, 0.0437841000, 0.0810538000, 0.1937921000, 0.5282034000, 1.4996002000", \ - "0.0253342000, 0.0305050000, 0.0437764000, 0.0810004000, 0.1934176000, 0.5282152000, 1.5009440000", \ - "0.0256340000, 0.0305796000, 0.0437657000, 0.0810458000, 0.1936677000, 0.5288117000, 1.5027630000", \ - "0.0256080000, 0.0307067000, 0.0438545000, 0.0809134000, 0.1938652000, 0.5280518000, 1.4986123000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2478051000, 0.2524201000, 0.2628321000, 0.2839554000, 0.3283358000, 0.4364937000, 0.7405579000", \ - "0.2526951000, 0.2573383000, 0.2677296000, 0.2889000000, 0.3332683000, 0.4413995000, 0.7455772000", \ - "0.2652617000, 0.2698891000, 0.2802635000, 0.3013841000, 0.3457636000, 0.4539469000, 0.7576839000", \ - "0.2963070000, 0.3009664000, 0.3113502000, 0.3325229000, 0.3769096000, 0.4851262000, 0.7892856000", \ - "0.3630592000, 0.3677043000, 0.3780542000, 0.3992149000, 0.4435845000, 0.5517822000, 0.8554362000", \ - "0.4752235000, 0.4798807000, 0.4902860000, 0.5114160000, 0.5557673000, 0.6640218000, 0.9676975000", \ - "0.6488635000, 0.6535208000, 0.6639269000, 0.6852016000, 0.7296258000, 0.8379207000, 1.1425331000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3852113000, 0.3913391000, 0.4056572000, 0.4382298000, 0.5200708000, 0.7494838000, 1.4089946000", \ - "0.3900143000, 0.3961155000, 0.4104727000, 0.4431107000, 0.5250262000, 0.7537541000, 1.4144425000", \ - "0.4026592000, 0.4088280000, 0.4232112000, 0.4557676000, 0.5375728000, 0.7671374000, 1.4251768000", \ - "0.4336937000, 0.4398009000, 0.4541302000, 0.4867680000, 0.5686823000, 0.7980777000, 1.4568529000", \ - "0.4994358000, 0.5055732000, 0.5199484000, 0.5524833000, 0.6344823000, 0.8637789000, 1.5243626000", \ - "0.6051855000, 0.6113358000, 0.6256703000, 0.6583156000, 0.7403329000, 0.9698864000, 1.6286424000", \ - "0.7674529000, 0.7735786000, 0.7879141000, 0.8205013000, 0.9024121000, 1.1313228000, 1.7889955000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0194142000, 0.0223206000, 0.0294020000, 0.0466375000, 0.0921352000, 0.2276522000, 0.6401586000", \ - "0.0193516000, 0.0223023000, 0.0294095000, 0.0468098000, 0.0920720000, 0.2279055000, 0.6337265000", \ - "0.0193464000, 0.0222332000, 0.0293069000, 0.0465996000, 0.0921751000, 0.2278282000, 0.6337145000", \ - "0.0193767000, 0.0222387000, 0.0294053000, 0.0467890000, 0.0920556000, 0.2284988000, 0.6347595000", \ - "0.0193274000, 0.0223499000, 0.0292765000, 0.0466862000, 0.0922168000, 0.2279157000, 0.6413196000", \ - "0.0194165000, 0.0223816000, 0.0294519000, 0.0467521000, 0.0921286000, 0.2280088000, 0.6340194000", \ - "0.0195495000, 0.0225762000, 0.0294754000, 0.0469663000, 0.0924631000, 0.2284865000, 0.6323195000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0253957000, 0.0304221000, 0.0438017000, 0.0809666000, 0.1933869000, 0.5273966000, 1.5001196000", \ - "0.0254705000, 0.0303528000, 0.0437163000, 0.0810867000, 0.1938925000, 0.5283508000, 1.5000965000", \ - "0.0254034000, 0.0303818000, 0.0437297000, 0.0810755000, 0.1934395000, 0.5283649000, 1.4981180000", \ - "0.0254714000, 0.0303356000, 0.0437326000, 0.0810487000, 0.1939110000, 0.5288939000, 1.5012379000", \ - "0.0253871000, 0.0302833000, 0.0437556000, 0.0809361000, 0.1938421000, 0.5277653000, 1.5027749000", \ - "0.0254188000, 0.0303993000, 0.0437652000, 0.0810385000, 0.1941401000, 0.5289774000, 1.5010456000", \ - "0.0253222000, 0.0303945000, 0.0436850000, 0.0810168000, 0.1937185000, 0.5275865000, 1.5008143000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1020492000, 0.1067749000, 0.1174172000, 0.1390451000, 0.1851347000, 0.2943192000, 0.5977926000", \ - "0.1072771000, 0.1119891000, 0.1226467000, 0.1442723000, 0.1904062000, 0.2995999000, 0.6030264000", \ - "0.1202857000, 0.1250120000, 0.1356589000, 0.1573267000, 0.2034404000, 0.3126207000, 0.6162683000", \ - "0.1524697000, 0.1571829000, 0.1677185000, 0.1893197000, 0.2355111000, 0.3447392000, 0.6476642000", \ - "0.2255079000, 0.2305544000, 0.2415999000, 0.2636034000, 0.3100838000, 0.4192733000, 0.7222926000", \ - "0.3497368000, 0.3564374000, 0.3710770000, 0.3986798000, 0.4504335000, 0.5602480000, 0.8625231000", \ - "0.5490534000, 0.5576445000, 0.5774681000, 0.6148292000, 0.6786627000, 0.7895878000, 1.0914347000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0945267000, 0.1003792000, 0.1141913000, 0.1461758000, 0.2274363000, 0.4563368000, 1.1143632000", \ - "0.0988131000, 0.1045357000, 0.1183480000, 0.1503154000, 0.2314445000, 0.4600100000, 1.1194325000", \ - "0.1072434000, 0.1131300000, 0.1269290000, 0.1588443000, 0.2399481000, 0.4683736000, 1.1268829000", \ - "0.1256601000, 0.1314528000, 0.1452609000, 0.1771768000, 0.2584826000, 0.4873450000, 1.1495901000", \ - "0.1580596000, 0.1643817000, 0.1789777000, 0.2121500000, 0.2940968000, 0.5233417000, 1.1824078000", \ - "0.2004788000, 0.2080506000, 0.2249654000, 0.2598297000, 0.3434421000, 0.5727570000, 1.2308429000", \ - "0.2316912000, 0.2416257000, 0.2633933000, 0.3053067000, 0.3919702000, 0.6216958000, 1.2790038000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0198073000, 0.0231812000, 0.0305503000, 0.0481337000, 0.0951332000, 0.2273122000, 0.6353498000", \ - "0.0198043000, 0.0227919000, 0.0300932000, 0.0481080000, 0.0951231000, 0.2276448000, 0.6351401000", \ - "0.0197829000, 0.0228249000, 0.0305383000, 0.0481467000, 0.0950855000, 0.2271112000, 0.6359568000", \ - "0.0197929000, 0.0230620000, 0.0301267000, 0.0481666000, 0.0949773000, 0.2271140000, 0.6374781000", \ - "0.0226323000, 0.0255775000, 0.0322313000, 0.0493619000, 0.0950905000, 0.2269612000, 0.6372958000", \ - "0.0336350000, 0.0378227000, 0.0455225000, 0.0625052000, 0.1032334000, 0.2288843000, 0.6381614000", \ - "0.0508692000, 0.0558556000, 0.0663780000, 0.0871797000, 0.1213061000, 0.2313176000, 0.6309691000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0231696000, 0.0282930000, 0.0418511000, 0.0797506000, 0.1932030000, 0.5277470000, 1.4992703000", \ - "0.0230903000, 0.0284034000, 0.0418814000, 0.0796769000, 0.1929017000, 0.5284020000, 1.4984866000", \ - "0.0232474000, 0.0283423000, 0.0418065000, 0.0799141000, 0.1929834000, 0.5276974000, 1.4983319000", \ - "0.0234229000, 0.0283714000, 0.0418682000, 0.0797334000, 0.1932292000, 0.5286840000, 1.5044043000", \ - "0.0262118000, 0.0315493000, 0.0447838000, 0.0820815000, 0.1940788000, 0.5285332000, 1.4985704000", \ - "0.0331407000, 0.0386366000, 0.0513015000, 0.0874849000, 0.1957740000, 0.5291625000, 1.5033222000", \ - "0.0463184000, 0.0528162000, 0.0668229000, 0.1005155000, 0.2019676000, 0.5308193000, 1.4944517000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0024340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043349000, 0.0043706000, 0.0044528000, 0.0044541000, 0.0044571000, 0.0044641000, 0.0044801000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004306500, -0.004280300, -0.004219800, -0.004233100, -0.004263800, -0.004334400, -0.004497400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.056593700, 0.0026022000, 0.0054505000", \ - "-0.170721400, -0.109084000, -0.107456400", \ - "-0.244370500, -0.180291700, -0.178664100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0764629000, 0.0148255000, 0.0107565000", \ - "0.1893698000, 0.1277324000, 0.1236634000", \ - "0.2630189000, 0.2001608000, 0.1948711000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1346323000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtn_4") { - leakage_power () { - value : 0.0093991000; - when : "RESET_B&D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0082253000; - when : "RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0080082000; - when : "!RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0083044000; - when : "RESET_B&!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0093045000; - when : "RESET_B&D&GATE_N&Q"; - } - leakage_power () { - value : 0.0096075000; - when : "!RESET_B&D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0079291000; - when : "!RESET_B&!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0093784000; - when : "!RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0096746000; - when : "RESET_B&D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0084782000; - when : "RESET_B&!D&GATE_N&Q"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__dlrtn"; - cell_leakage_power : 0.0088309230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181508000, 0.0180358000, 0.0177706000, 0.0178469000, 0.0180228000, 0.0184282000, 0.0193627000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091830000, 0.0090812000, 0.0088466000, 0.0089063000, 0.0090438000, 0.0093608000, 0.0100917000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018790000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1350566000, 0.2931296000, 0.4632142000", \ - "0.0868470000, 0.2436992000, 0.4113424000", \ - "0.1084128000, 0.2591615000, 0.4219219000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2107402000, 0.2931296000, 0.3252747000", \ - "0.0892884000, 0.1716777000, 0.2038229000", \ - "0.0119772000, 0.0955872000, 0.1277324000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.111525400, -0.274481100, -0.448227900", \ - "-0.064536500, -0.226271500, -0.396356100", \ - "-0.065350300, -0.225864600, -0.395949200"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.189650400, -0.275701800, -0.307847000", \ - "-0.070640000, -0.155470700, -0.187615900", \ - "0.0042298000, -0.081821600, -0.113966800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171440000, 0.0170247000, 0.0167498000, 0.0168094000, 0.0169469000, 0.0172638000, 0.0179944000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102894000, 0.0101597000, 0.0098606000, 0.0099028000, 0.0100000000, 0.0102239000, 0.0107403000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1642921000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0230572000, 0.0213657000, 0.0161551000, 0.0003275000, -0.055521900, -0.243964600, -0.852123400", \ - "0.0230172000, 0.0213053000, 0.0160272000, 0.0002017000, -0.055610200, -0.244115800, -0.852228400", \ - "0.0231382000, 0.0214636000, 0.0161887000, 0.0002840000, -0.055530900, -0.244001400, -0.852100900", \ - "0.0229888000, 0.0212859000, 0.0159913000, 0.0001706000, -0.055637300, -0.244093700, -0.852231800", \ - "0.0228400000, 0.0211832000, 0.0159137000, 3.550000e-05, -0.055761500, -0.244167900, -0.852353500", \ - "0.0225951000, 0.0208701000, 0.0156432000, -7.59000e-05, -0.055956900, -0.244373100, -0.852537800", \ - "0.0272184000, 0.0255142000, 0.0200606000, 0.0024268000, -0.055463900, -0.244382100, -0.852408100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0308031000, 0.0327122000, 0.0387942000, 0.0578640000, 0.1169780000, 0.3044482000, 0.9080536000", \ - "0.0307310000, 0.0325984000, 0.0386128000, 0.0577585000, 0.1168632000, 0.3044029000, 0.9050412000", \ - "0.0307186000, 0.0326177000, 0.0385042000, 0.0577386000, 0.1168261000, 0.3042615000, 0.9061970000", \ - "0.0305041000, 0.0322502000, 0.0382768000, 0.0575050000, 0.1165597000, 0.3051607000, 0.9089499000", \ - "0.0302297000, 0.0321526000, 0.0381283000, 0.0573459000, 0.1164852000, 0.3036479000, 0.9024896000", \ - "0.0302336000, 0.0321322000, 0.0381097000, 0.0572029000, 0.1164372000, 0.3038338000, 0.9060484000", \ - "0.0321154000, 0.0339229000, 0.0397661000, 0.0584878000, 0.1176257000, 0.3053020000, 0.9047889000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0322498000, 0.0305067000, 0.0252099000, 0.0093730000, -0.046455000, -0.234817100, -0.842977700", \ - "0.0323264000, 0.0305775000, 0.0252835000, 0.0093937000, -0.046408900, -0.234792200, -0.842866500", \ - "0.0323423000, 0.0305033000, 0.0253609000, 0.0094649000, -0.046359000, -0.234718600, -0.842857600", \ - "0.0319833000, 0.0302729000, 0.0250322000, 0.0091312000, -0.046678500, -0.235065100, -0.843210400", \ - "0.0317257000, 0.0298694000, 0.0248062000, 0.0088837000, -0.046926200, -0.235333500, -0.843451000", \ - "0.0314149000, 0.0297087000, 0.0244232000, 0.0084898000, -0.047276800, -0.235655500, -0.843791500", \ - "0.0359269000, 0.0341912000, 0.0287196000, 0.0110207000, -0.046877500, -0.235567600, -0.843654900"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0366886000, 0.0384949000, 0.0445132000, 0.0637137000, 0.1228077000, 0.3114540000, 0.9142594000", \ - "0.0365857000, 0.0384569000, 0.0444888000, 0.0636264000, 0.1228740000, 0.3102443000, 0.9139797000", \ - "0.0366574000, 0.0385279000, 0.0445150000, 0.0637293000, 0.1230237000, 0.3114506000, 0.9180206000", \ - "0.0364633000, 0.0383080000, 0.0443603000, 0.0635544000, 0.1226861000, 0.3112591000, 0.9170514000", \ - "0.0362597000, 0.0380688000, 0.0440909000, 0.0633390000, 0.1227155000, 0.3100387000, 0.9166792000", \ - "0.0361093000, 0.0379642000, 0.0440136000, 0.0631736000, 0.1222211000, 0.3110431000, 0.9165077000", \ - "0.0376408000, 0.0394678000, 0.0452717000, 0.0639927000, 0.1227132000, 0.3098730000, 0.9121775000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0302401000, 0.0287768000, 0.0240452000, 0.0110338000, -0.043798000, -0.232681400, -0.840914300", \ - "0.0302980000, 0.0289072000, 0.0240142000, 0.0110308000, -0.043808300, -0.232697500, -0.840910900", \ - "0.0299039000, 0.0283693000, 0.0237357000, 0.0107977000, -0.044084000, -0.232950700, -0.841180300", \ - "0.0297655000, 0.0283616000, 0.0235440000, 0.0105611000, -0.044328000, -0.233152000, -0.841343800", \ - "0.0295056000, 0.0280476000, 0.0231713000, 0.0099799000, -0.044984200, -0.233612100, -0.841679900", \ - "0.0304966000, 0.0286024000, 0.0247096000, 0.0100886000, -0.045246200, -0.233907500, -0.841880500", \ - "0.0418584000, 0.0397536000, 0.0334091000, 0.0144444000, -0.044632900, -0.233431700, -0.841306300"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0316844000, 0.0335707000, 0.0395988000, 0.0588836000, 0.1179417000, 0.3049284000, 0.9071360000", \ - "0.0316768000, 0.0335489000, 0.0395468000, 0.0588849000, 0.1179400000, 0.3047569000, 0.9069447000", \ - "0.0315039000, 0.0334896000, 0.0395094000, 0.0586161000, 0.1176887000, 0.3046931000, 0.9103611000", \ - "0.0310142000, 0.0328656000, 0.0390091000, 0.0581751000, 0.1171749000, 0.3045947000, 0.9026243000", \ - "0.0311622000, 0.0329606000, 0.0389633000, 0.0577928000, 0.1169132000, 0.3042816000, 0.9109519000", \ - "0.0325408000, 0.0342784000, 0.0404725000, 0.0585617000, 0.1168296000, 0.3035703000, 0.9068395000", \ - "0.0347557000, 0.0364434000, 0.0419999000, 0.0601860000, 0.1189755000, 0.3060536000, 0.9035520000"); - } - } - max_capacitance : 0.5456640000; - max_transition : 1.5066200000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.2598086000, 0.2634733000, 0.2730879000, 0.2946955000, 0.3403465000, 0.4490313000, 0.7689268000", \ - "0.2647937000, 0.2684677000, 0.2780529000, 0.2996842000, 0.3453676000, 0.4539893000, 0.7738868000", \ - "0.2779513000, 0.2816243000, 0.2911868000, 0.3128086000, 0.3584165000, 0.4671182000, 0.7870679000", \ - "0.3091655000, 0.3128395000, 0.3224467000, 0.3440485000, 0.3897402000, 0.4984438000, 0.8184891000", \ - "0.3661463000, 0.3697890000, 0.3794083000, 0.4010094000, 0.4467730000, 0.5552367000, 0.8747975000", \ - "0.4549880000, 0.4586635000, 0.4682574000, 0.4898539000, 0.5355001000, 0.6441842000, 0.9635593000", \ - "0.5951116000, 0.5988080000, 0.6083669000, 0.6299101000, 0.6754900000, 0.7842469000, 1.1042550000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3603649000, 0.3650780000, 0.3775605000, 0.4075645000, 0.4825956000, 0.7034456000, 1.4092171000", \ - "0.3647961000, 0.3695276000, 0.3820252000, 0.4120143000, 0.4871725000, 0.7080256000, 1.4142235000", \ - "0.3761433000, 0.3808961000, 0.3933751000, 0.4232783000, 0.4982830000, 0.7198410000, 1.4250496000", \ - "0.3969581000, 0.4015165000, 0.4141893000, 0.4440949000, 0.5190967000, 0.7406665000, 1.4475333000", \ - "0.4240917000, 0.4287609000, 0.4413622000, 0.4713612000, 0.5463474000, 0.7676574000, 1.4709602000", \ - "0.4552269000, 0.4599365000, 0.4724695000, 0.5023689000, 0.5773435000, 0.7989093000, 1.5046794000", \ - "0.4783315000, 0.4830657000, 0.4955855000, 0.5255811000, 0.6007002000, 0.8215485000, 1.5261576000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0256245000, 0.0278754000, 0.0339497000, 0.0494457000, 0.0890714000, 0.2135166000, 0.6353593000", \ - "0.0256619000, 0.0279241000, 0.0339661000, 0.0490365000, 0.0894845000, 0.2135617000, 0.6402323000", \ - "0.0255880000, 0.0279384000, 0.0343268000, 0.0493454000, 0.0893724000, 0.2140584000, 0.6357174000", \ - "0.0256425000, 0.0279088000, 0.0339135000, 0.0489845000, 0.0891559000, 0.2139269000, 0.6360820000", \ - "0.0256154000, 0.0278780000, 0.0342772000, 0.0494828000, 0.0894333000, 0.2140500000, 0.6355734000", \ - "0.0257495000, 0.0279213000, 0.0341665000, 0.0490935000, 0.0885515000, 0.2136919000, 0.6397798000", \ - "0.0257132000, 0.0280012000, 0.0340464000, 0.0491851000, 0.0893507000, 0.2130556000, 0.6349297000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0306561000, 0.0341785000, 0.0440366000, 0.0727180000, 0.1647756000, 0.4778544000, 1.4989922000", \ - "0.0304356000, 0.0338250000, 0.0440303000, 0.0727015000, 0.1651198000, 0.4779739000, 1.5017831000", \ - "0.0305810000, 0.0339844000, 0.0442359000, 0.0726883000, 0.1653735000, 0.4782330000, 1.5015709000", \ - "0.0305747000, 0.0343181000, 0.0442295000, 0.0726969000, 0.1653645000, 0.4780607000, 1.4982707000", \ - "0.0306301000, 0.0341399000, 0.0441624000, 0.0727697000, 0.1653029000, 0.4786772000, 1.5007732000", \ - "0.0304566000, 0.0340886000, 0.0442474000, 0.0726627000, 0.1650580000, 0.4783169000, 1.5047914000", \ - "0.0303334000, 0.0338256000, 0.0440851000, 0.0727036000, 0.1650694000, 0.4775716000, 1.4965826000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.2850410000, 0.2887963000, 0.2985254000, 0.3202673000, 0.3659411000, 0.4748644000, 0.7944275000", \ - "0.2899979000, 0.2937207000, 0.3034013000, 0.3251295000, 0.3710177000, 0.4797966000, 0.7997996000", \ - "0.3026673000, 0.3064161000, 0.3161442000, 0.3378300000, 0.3837247000, 0.4924811000, 0.8121874000", \ - "0.3335995000, 0.3373031000, 0.3470596000, 0.3688067000, 0.4146005000, 0.5233263000, 0.8433056000", \ - "0.4000653000, 0.4037499000, 0.4134786000, 0.4351585000, 0.4811863000, 0.5897601000, 0.9096862000", \ - "0.5123869000, 0.5161127000, 0.5258684000, 0.5475873000, 0.5932774000, 0.7021395000, 1.0219592000", \ - "0.6858135000, 0.6895505000, 0.6993310000, 0.7211018000, 0.7668408000, 0.8757096000, 1.1954622000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.4198221000, 0.4245270000, 0.4370337000, 0.4671656000, 0.5421681000, 0.7634718000, 1.4676724000", \ - "0.4245735000, 0.4292975000, 0.4418254000, 0.4719056000, 0.5469498000, 0.7686078000, 1.4772806000", \ - "0.4374134000, 0.4421410000, 0.4546963000, 0.4847487000, 0.5598579000, 0.7807949000, 1.4873067000", \ - "0.4682673000, 0.4730246000, 0.4855111000, 0.5156373000, 0.5906625000, 0.8119578000, 1.5160032000", \ - "0.5341287000, 0.5388553000, 0.5513668000, 0.5814825000, 0.6564731000, 0.8779610000, 1.5831290000", \ - "0.6399621000, 0.6447330000, 0.6572168000, 0.6873279000, 0.7623102000, 0.9838146000, 1.6894602000", \ - "0.8022217000, 0.8069345000, 0.8194387000, 0.8495692000, 0.9245462000, 1.1458092000, 1.8529587000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0260023000, 0.0285264000, 0.0345857000, 0.0492431000, 0.0896083000, 0.2140817000, 0.6359347000", \ - "0.0261906000, 0.0284448000, 0.0344621000, 0.0492802000, 0.0896373000, 0.2139339000, 0.6416773000", \ - "0.0260073000, 0.0284986000, 0.0342971000, 0.0492202000, 0.0895735000, 0.2141054000, 0.6396624000", \ - "0.0259912000, 0.0284043000, 0.0343095000, 0.0491581000, 0.0892060000, 0.2139788000, 0.6363274000", \ - "0.0259857000, 0.0286137000, 0.0343773000, 0.0495876000, 0.0899028000, 0.2142010000, 0.6409300000", \ - "0.0261058000, 0.0284145000, 0.0343876000, 0.0494759000, 0.0896675000, 0.2140111000, 0.6395293000", \ - "0.0261857000, 0.0286180000, 0.0345683000, 0.0492598000, 0.0898966000, 0.2142419000, 0.6351850000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0303635000, 0.0338758000, 0.0438745000, 0.0726002000, 0.1652330000, 0.4782158000, 1.5033998000", \ - "0.0303901000, 0.0338150000, 0.0438918000, 0.0726080000, 0.1650524000, 0.4794255000, 1.5045557000", \ - "0.0304317000, 0.0338738000, 0.0437234000, 0.0725666000, 0.1649656000, 0.4778936000, 1.4991881000", \ - "0.0304221000, 0.0337695000, 0.0438686000, 0.0727109000, 0.1651523000, 0.4782612000, 1.5048115000", \ - "0.0303803000, 0.0338570000, 0.0437707000, 0.0725552000, 0.1652009000, 0.4779185000, 1.5046555000", \ - "0.0304508000, 0.0337115000, 0.0438660000, 0.0727356000, 0.1652989000, 0.4785442000, 1.5001707000", \ - "0.0303794000, 0.0338461000, 0.0438988000, 0.0727301000, 0.1654904000, 0.4768609000, 1.5025904000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.1387426000, 0.1425642000, 0.1526583000, 0.1751274000, 0.2224943000, 0.3309949000, 0.6490514000", \ - "0.1442002000, 0.1480379000, 0.1580639000, 0.1805810000, 0.2279530000, 0.3364692000, 0.6547584000", \ - "0.1572758000, 0.1611301000, 0.1712335000, 0.1937209000, 0.2410667000, 0.3496419000, 0.6683898000", \ - "0.1893286000, 0.1932138000, 0.2031608000, 0.2256897000, 0.2730013000, 0.3816362000, 0.7004149000", \ - "0.2652555000, 0.2690383000, 0.2790207000, 0.3013639000, 0.3486701000, 0.4572646000, 0.7754204000", \ - "0.4136350000, 0.4183076000, 0.4306917000, 0.4572834000, 0.5093306000, 0.6187326000, 0.9368200000", \ - "0.6516455000, 0.6578860000, 0.6742079000, 0.7099475000, 0.7765830000, 0.8912638000, 1.2085923000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.1242745000, 0.1287881000, 0.1409267000, 0.1706319000, 0.2452399000, 0.4659792000, 1.1719310000", \ - "0.1284854000, 0.1330833000, 0.1452512000, 0.1749109000, 0.2495555000, 0.4701454000, 1.1781193000", \ - "0.1372001000, 0.1417916000, 0.1539350000, 0.1835808000, 0.2581879000, 0.4793178000, 1.1824076000", \ - "0.1561299000, 0.1607027000, 0.1729790000, 0.2025413000, 0.2771523000, 0.4984692000, 1.2020128000", \ - "0.1945546000, 0.1993626000, 0.2120995000, 0.2421168000, 0.3170007000, 0.5387500000, 1.2427459000", \ - "0.2513843000, 0.2569445000, 0.2715274000, 0.3044028000, 0.3819926000, 0.6035716000, 1.3097290000", \ - "0.3090720000, 0.3161978000, 0.3344837000, 0.3742717000, 0.4574148000, 0.6797950000, 1.3834565000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0270212000, 0.0296194000, 0.0356418000, 0.0510688000, 0.0917699000, 0.2113515000, 0.6381062000", \ - "0.0270140000, 0.0296843000, 0.0361804000, 0.0510904000, 0.0918354000, 0.2112542000, 0.6379210000", \ - "0.0271908000, 0.0296141000, 0.0362896000, 0.0518148000, 0.0917150000, 0.2111654000, 0.6373244000", \ - "0.0270386000, 0.0297004000, 0.0359026000, 0.0513717000, 0.0919051000, 0.2112786000, 0.6369304000", \ - "0.0274361000, 0.0296102000, 0.0364831000, 0.0519350000, 0.0917691000, 0.2111756000, 0.6382162000", \ - "0.0387922000, 0.0414391000, 0.0481580000, 0.0630706000, 0.0994214000, 0.2124926000, 0.6378881000", \ - "0.0603494000, 0.0634674000, 0.0722538000, 0.0914659000, 0.1251654000, 0.2194517000, 0.6329420000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0286744000, 0.0324371000, 0.0426649000, 0.0714439000, 0.1643166000, 0.4787916000, 1.5032868000", \ - "0.0289241000, 0.0324211000, 0.0426552000, 0.0715271000, 0.1644174000, 0.4787612000, 1.5015462000", \ - "0.0286376000, 0.0322565000, 0.0423839000, 0.0713633000, 0.1647205000, 0.4784900000, 1.4985350000", \ - "0.0285801000, 0.0323136000, 0.0423600000, 0.0713914000, 0.1647934000, 0.4785551000, 1.5016871000", \ - "0.0307062000, 0.0342336000, 0.0444448000, 0.0729953000, 0.1651731000, 0.4775817000, 1.5066199000", \ - "0.0377043000, 0.0414080000, 0.0514536000, 0.0798101000, 0.1694093000, 0.4791705000, 1.5058560000", \ - "0.0527307000, 0.0563849000, 0.0676625000, 0.0956267000, 0.1791322000, 0.4818969000, 1.4971060000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0023930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042892000, 0.0043198000, 0.0043905000, 0.0043900000, 0.0043888000, 0.0043859000, 0.0043794000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004233200, -0.004214600, -0.004171700, -0.004183500, -0.004210700, -0.004273600, -0.004418400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025090000; - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.028517600, 0.0428854000, 0.0701478000", \ - "-0.143865900, -0.070021500, -0.041538400", \ - "-0.218735700, -0.140008500, -0.112746100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0593730000, -0.019354200, -0.050278600", \ - "0.1735006000, 0.0935527000, 0.0626283000", \ - "0.2471497000, 0.1647604000, 0.1338359000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1752772000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtp_1") { - leakage_power () { - value : 0.0073326000; - when : "RESET_B&D&GATE&Q"; - } - leakage_power () { - value : 0.0059624000; - when : "RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0060912000; - when : "!RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0063645000; - when : "RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0072337000; - when : "RESET_B&D&!GATE&Q"; - } - leakage_power () { - value : 0.0077750000; - when : "!RESET_B&D&GATE&!Q"; - } - leakage_power () { - value : 0.0070008000; - when : "!RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0056891000; - when : "!RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0072741000; - when : "RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0065733000; - when : "RESET_B&!D&!GATE&Q"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__dlrtp"; - cell_leakage_power : 0.0067296680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083442000, 0.0082609000, 0.0080690000, 0.0081420000, 0.0083102000, 0.0086981000, 0.0095920000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025566000, 0.0024223000, 0.0021129000, 0.0021810000, 0.0023378000, 0.0026994000, 0.0035328000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018680000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0386211000, 0.1991354000, 0.3692201000", \ - "-0.134100300, 0.0251934000, 0.1916159000", \ - "-0.310288400, -0.150994800, 0.0105449000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2217266000, 0.3053366000, 0.3362611000", \ - "0.1271302000, 0.2107402000, 0.2404440000", \ - "0.0669089000, 0.1468568000, 0.1728984000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.026076200, -0.187811200, -0.359116500", \ - "0.1466452000, -0.015089800, -0.182733100", \ - "0.3240541000, 0.1635397000, -0.000441400"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.209181600, -0.294012400, -0.324936800", \ - "-0.106040400, -0.190871100, -0.220574900", \ - "-0.020184200, -0.106235700, -0.135939500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017520000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173446000, 0.0172203000, 0.0169337000, 0.0170076000, 0.0171779000, 0.0175706000, 0.0184755000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103990000, 0.0102741000, 0.0099863000, 0.0100214000, 0.0101024000, 0.0102892000, 0.0107198000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018310000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1818682000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0194867000, 0.0185709000, 0.0160027000, 0.0078994000, -0.014915200, -0.075107900, -0.232393100", \ - "0.0193542000, 0.0184544000, 0.0158846000, 0.0077648000, -0.015056400, -0.075251900, -0.232503800", \ - "0.0193832000, 0.0184835000, 0.0159137000, 0.0077938000, -0.015027300, -0.075213500, -0.232466100", \ - "0.0192569000, 0.0183650000, 0.0158265000, 0.0076713000, -0.015142700, -0.075341600, -0.232582800", \ - "0.0191791000, 0.0182694000, 0.0156760000, 0.0075712000, -0.015249500, -0.075446200, -0.232690900", \ - "0.0199770000, 0.0187803000, 0.0155567000, 0.0073239000, -0.015421000, -0.075603700, -0.232820600", \ - "0.0204708000, 0.0192745000, 0.0160813000, 0.0074890000, -0.015450400, -0.075468900, -0.232709600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0206513000, 0.0221900000, 0.0259556000, 0.0350512000, 0.0578508000, 0.1177464000, 0.2747040000", \ - "0.0206578000, 0.0221962000, 0.0259633000, 0.0350554000, 0.0578564000, 0.1178234000, 0.2738536000", \ - "0.0208519000, 0.0224058000, 0.0261300000, 0.0351945000, 0.0582861000, 0.1180359000, 0.2735216000", \ - "0.0204082000, 0.0219470000, 0.0257150000, 0.0348068000, 0.0576163000, 0.1175510000, 0.2740229000", \ - "0.0202332000, 0.0217740000, 0.0255376000, 0.0346279000, 0.0574359000, 0.1174439000, 0.2740964000", \ - "0.0202429000, 0.0217206000, 0.0254602000, 0.0345879000, 0.0573802000, 0.1166389000, 0.2737924000", \ - "0.0214408000, 0.0227673000, 0.0261564000, 0.0350368000, 0.0578803000, 0.1174703000, 0.2736864000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0191797000, 0.0182664000, 0.0156761000, 0.0075570000, -0.015255600, -0.075438200, -0.232675500", \ - "0.0191928000, 0.0182757000, 0.0156836000, 0.0075707000, -0.015245700, -0.075430100, -0.232672400", \ - "0.0192696000, 0.0183387000, 0.0157718000, 0.0076454000, -0.015157800, -0.075345200, -0.232608000", \ - "0.0188168000, 0.0179256000, 0.0153511000, 0.0072045000, -0.015597800, -0.075779000, -0.233034900", \ - "0.0185707000, 0.0176603000, 0.0150766000, 0.0069572000, -0.015854700, -0.076043500, -0.233286800", \ - "0.0199706000, 0.0187828000, 0.0155951000, 0.0069791000, -0.015867500, -0.076049400, -0.233308900", \ - "0.0206733000, 0.0194850000, 0.0163019000, 0.0077098000, -0.015222800, -0.075493100, -0.232806400"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0184009000, 0.0199312000, 0.0237204000, 0.0328296000, 0.0557609000, 0.1155481000, 0.2705472000", \ - "0.0183922000, 0.0199277000, 0.0237173000, 0.0328367000, 0.0558575000, 0.1149600000, 0.2708990000", \ - "0.0184579000, 0.0199924000, 0.0237929000, 0.0329091000, 0.0558004000, 0.1156367000, 0.2707702000", \ - "0.0179366000, 0.0194874000, 0.0232902000, 0.0324073000, 0.0552404000, 0.1151585000, 0.2719093000", \ - "0.0176388000, 0.0191844000, 0.0229724000, 0.0320953000, 0.0549479000, 0.1142743000, 0.2714201000", \ - "0.0175699000, 0.0190782000, 0.0228218000, 0.0319649000, 0.0547707000, 0.1141861000, 0.2698367000", \ - "0.0191176000, 0.0204416000, 0.0238809000, 0.0327505000, 0.0553836000, 0.1150847000, 0.2696607000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0161231000, 0.0158659000, 0.0154928000, 0.0103063000, -0.012413900, -0.072690400, -0.229989200", \ - "0.0157794000, 0.0155219000, 0.0152222000, 0.0100749000, -0.012626100, -0.072900800, -0.230154900", \ - "0.0155314000, 0.0152849000, 0.0150442000, 0.0098151000, -0.012829000, -0.073120700, -0.230356300", \ - "0.0154373000, 0.0150076000, 0.0148005000, 0.0096200000, -0.013022800, -0.073271700, -0.230523900", \ - "0.0154344000, 0.0149411000, 0.0146772000, 0.0092336000, -0.013359800, -0.073562000, -0.230838100", \ - "0.0223652000, 0.0210819000, 0.0177468000, 0.0089720000, -0.013523000, -0.073705300, -0.230964600", \ - "0.0241904000, 0.0228484000, 0.0194299000, 0.0105668000, -0.012478400, -0.072440900, -0.229704600"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0156363000, 0.0171313000, 0.0207996000, 0.0296319000, 0.0521631000, 0.1113354000, 0.2674853000", \ - "0.0153849000, 0.0168825000, 0.0205183000, 0.0293455000, 0.0521416000, 0.1117419000, 0.2668592000", \ - "0.0151992000, 0.0166928000, 0.0203496000, 0.0292301000, 0.0518300000, 0.1111856000, 0.2683073000", \ - "0.0149307000, 0.0164089000, 0.0200865000, 0.0289914000, 0.0516760000, 0.1109973000, 0.2667600000", \ - "0.0148613000, 0.0162042000, 0.0198751000, 0.0287502000, 0.0517570000, 0.1108851000, 0.2667686000", \ - "0.0155170000, 0.0168312000, 0.0202628000, 0.0290551000, 0.0518918000, 0.1115112000, 0.2683764000", \ - "0.0166772000, 0.0178400000, 0.0210762000, 0.0299121000, 0.0528151000, 0.1126357000, 0.2677182000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.5063820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2059938000, 0.2114576000, 0.2228863000, 0.2459647000, 0.2959996000, 0.4191275000, 0.7398180000", \ - "0.2109205000, 0.2163872000, 0.2278050000, 0.2508747000, 0.3009119000, 0.4239406000, 0.7436882000", \ - "0.2241103000, 0.2295770000, 0.2409953000, 0.2640648000, 0.3141020000, 0.4371303000, 0.7568836000", \ - "0.2554638000, 0.2609310000, 0.2723470000, 0.2954101000, 0.3454567000, 0.4684903000, 0.7887424000", \ - "0.3126409000, 0.3180636000, 0.3295308000, 0.3525625000, 0.4025871000, 0.5256808000, 0.8454011000", \ - "0.4020602000, 0.4074693000, 0.4189192000, 0.4419799000, 0.4920234000, 0.6150448000, 0.9347076000", \ - "0.5430605000, 0.5485234000, 0.5599546000, 0.5830264000, 0.6331188000, 0.7562485000, 1.0771032000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.3280582000, 0.3357398000, 0.3526594000, 0.3910958000, 0.4864164000, 0.7314283000, 1.3743807000", \ - "0.3326046000, 0.3402849000, 0.3572045000, 0.3956344000, 0.4909445000, 0.7359843000, 1.3768572000", \ - "0.3435129000, 0.3513458000, 0.3681841000, 0.4066209000, 0.5019136000, 0.7470552000, 1.3886151000", \ - "0.3645546000, 0.3722349000, 0.3891534000, 0.4275789000, 0.5228790000, 0.7679989000, 1.4100490000", \ - "0.3916567000, 0.3993646000, 0.4162605000, 0.4546639000, 0.5499407000, 0.7951843000, 1.4363176000", \ - "0.4221740000, 0.4298515000, 0.4468432000, 0.4851611000, 0.5801292000, 0.8260707000, 1.4659054000", \ - "0.4437780000, 0.4514861000, 0.4683941000, 0.5068438000, 0.6021759000, 0.8476557000, 1.4878636000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0173704000, 0.0216021000, 0.0308888000, 0.0534588000, 0.1121155000, 0.2726598000, 0.7019822000", \ - "0.0173525000, 0.0215374000, 0.0306978000, 0.0533188000, 0.1117888000, 0.2717564000, 0.7029390000", \ - "0.0173528000, 0.0215374000, 0.0306975000, 0.0533203000, 0.1117888000, 0.2724391000, 0.7029667000", \ - "0.0173271000, 0.0215341000, 0.0310383000, 0.0533414000, 0.1118042000, 0.2717944000, 0.6991979000", \ - "0.0173306000, 0.0213919000, 0.0309042000, 0.0534344000, 0.1120659000, 0.2733074000, 0.6982713000", \ - "0.0174154000, 0.0216901000, 0.0309750000, 0.0533048000, 0.1113179000, 0.2721624000, 0.6974595000", \ - "0.0175313000, 0.0216118000, 0.0308984000, 0.0533287000, 0.1119179000, 0.2742622000, 0.6921788000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0269771000, 0.0339461000, 0.0518099000, 0.1002188000, 0.2321619000, 0.5812114000, 1.4972927000", \ - "0.0269777000, 0.0339462000, 0.0518202000, 0.1002284000, 0.2321270000, 0.5814031000, 1.4928414000", \ - "0.0269963000, 0.0339483000, 0.0518728000, 0.1002309000, 0.2321722000, 0.5817624000, 1.4980137000", \ - "0.0269783000, 0.0339467000, 0.0518222000, 0.1002378000, 0.2320834000, 0.5815379000, 1.5004953000", \ - "0.0269753000, 0.0339436000, 0.0518007000, 0.1002379000, 0.2320024000, 0.5816578000, 1.5013955000", \ - "0.0269761000, 0.0339465000, 0.0516735000, 0.1001427000, 0.2321702000, 0.5803194000, 1.5032479000", \ - "0.0269855000, 0.0339532000, 0.0517541000, 0.1001431000, 0.2322300000, 0.5816929000, 1.4945799000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2517718000, 0.2573070000, 0.2687941000, 0.2920043000, 0.3420734000, 0.4651640000, 0.7861600000", \ - "0.2563177000, 0.2618663000, 0.2733498000, 0.2965307000, 0.3466365000, 0.4697572000, 0.7908261000", \ - "0.2674697000, 0.2730252000, 0.2845463000, 0.3077250000, 0.3578014000, 0.4809398000, 0.8005647000", \ - "0.2917578000, 0.2973262000, 0.3088113000, 0.3320000000, 0.3820819000, 0.5052107000, 0.8265336000", \ - "0.3301881000, 0.3357330000, 0.3472209000, 0.3704329000, 0.4205145000, 0.5436785000, 0.8641024000", \ - "0.3818139000, 0.3873926000, 0.3988792000, 0.4220640000, 0.4721658000, 0.5950649000, 0.9148509000", \ - "0.4379482000, 0.4435160000, 0.4550242000, 0.4781386000, 0.5282383000, 0.6513233000, 0.9722324000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2880133000, 0.2958067000, 0.3129016000, 0.3514175000, 0.4467258000, 0.6923842000, 1.3328452000", \ - "0.2925299000, 0.3003243000, 0.3174524000, 0.3559940000, 0.4512890000, 0.6966291000, 1.3370330000", \ - "0.3032516000, 0.3110455000, 0.3281559000, 0.3665877000, 0.4615280000, 0.7074366000, 1.3474688000", \ - "0.3269474000, 0.3347393000, 0.3517985000, 0.3903413000, 0.4852923000, 0.7311842000, 1.3721031000", \ - "0.3671459000, 0.3748774000, 0.3919655000, 0.4304714000, 0.5256501000, 0.7709615000, 1.4155521000", \ - "0.4228720000, 0.4306583000, 0.4477625000, 0.4863115000, 0.5813028000, 0.8270043000, 1.4685496000", \ - "0.4923737000, 0.5001953000, 0.5172960000, 0.5558152000, 0.6511842000, 0.8963786000, 1.5360329000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0176971000, 0.0218305000, 0.0311703000, 0.0535735000, 0.1120475000, 0.2725696000, 0.7019491000", \ - "0.0177083000, 0.0218174000, 0.0312027000, 0.0535880000, 0.1119658000, 0.2726126000, 0.7042588000", \ - "0.0178963000, 0.0217917000, 0.0312942000, 0.0536842000, 0.1122515000, 0.2734268000, 0.7002912000", \ - "0.0178933000, 0.0218095000, 0.0312831000, 0.0536121000, 0.1120588000, 0.2726890000, 0.6988470000", \ - "0.0177226000, 0.0216892000, 0.0311861000, 0.0534572000, 0.1120571000, 0.2725450000, 0.7019997000", \ - "0.0178812000, 0.0217991000, 0.0311530000, 0.0532214000, 0.1120732000, 0.2729341000, 0.6955509000", \ - "0.0179113000, 0.0219161000, 0.0311368000, 0.0536090000, 0.1120640000, 0.2726918000, 0.6930023000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0267166000, 0.0338155000, 0.0517656000, 0.1002190000, 0.2318318000, 0.5804213000, 1.4991928000", \ - "0.0267382000, 0.0338204000, 0.0517129000, 0.1002429000, 0.2317853000, 0.5815149000, 1.5020662000", \ - "0.0267298000, 0.0338142000, 0.0517246000, 0.1000578000, 0.2321776000, 0.5805368000, 1.4959468000", \ - "0.0268340000, 0.0338575000, 0.0518566000, 0.1000356000, 0.2319810000, 0.5799998000, 1.4992161000", \ - "0.0267708000, 0.0338642000, 0.0517902000, 0.1002295000, 0.2321694000, 0.5800618000, 1.5004786000", \ - "0.0267801000, 0.0338692000, 0.0518617000, 0.1000774000, 0.2317111000, 0.5814033000, 1.4985202000", \ - "0.0268258000, 0.0339567000, 0.0518893000, 0.1001646000, 0.2321328000, 0.5804850000, 1.4937498000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0879041000, 0.0935910000, 0.1054650000, 0.1294876000, 0.1826043000, 0.3062859000, 0.6256982000", \ - "0.0929712000, 0.0986431000, 0.1105383000, 0.1346081000, 0.1877585000, 0.3114607000, 0.6313245000", \ - "0.1061161000, 0.1118087000, 0.1236388000, 0.1477885000, 0.2009937000, 0.3246862000, 0.6445774000", \ - "0.1384572000, 0.1441007000, 0.1559464000, 0.1800975000, 0.2333626000, 0.3571069000, 0.6769749000", \ - "0.2073107000, 0.2137177000, 0.2265817000, 0.2517646000, 0.3054048000, 0.4290433000, 0.7489415000", \ - "0.3193507000, 0.3279983000, 0.3448050000, 0.3749674000, 0.4322335000, 0.5560185000, 0.8758101000", \ - "0.4993716000, 0.5111842000, 0.5342396000, 0.5741210000, 0.6387764000, 0.7621839000, 1.0820799000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0848534000, 0.0921735000, 0.1085547000, 0.1459120000, 0.2396095000, 0.4839985000, 1.1268025000", \ - "0.0889972000, 0.0962946000, 0.1125932000, 0.1500546000, 0.2442364000, 0.4888067000, 1.1341275000", \ - "0.0971240000, 0.1044331000, 0.1207659000, 0.1583173000, 0.2523870000, 0.4973227000, 1.1386916000", \ - "0.1143052000, 0.1216643000, 0.1381345000, 0.1759076000, 0.2701569000, 0.5155337000, 1.1557096000", \ - "0.1421232000, 0.1501058000, 0.1674053000, 0.2061177000, 0.3012774000, 0.5461822000, 1.1896750000", \ - "0.1763686000, 0.1850923000, 0.2045383000, 0.2451654000, 0.3406177000, 0.5865249000, 1.2308884000", \ - "0.1938681000, 0.2062158000, 0.2297089000, 0.2759862000, 0.3732406000, 0.6190103000, 1.2587302000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0188048000, 0.0231134000, 0.0331011000, 0.0567780000, 0.1159220000, 0.2727241000, 0.7013208000", \ - "0.0189075000, 0.0229499000, 0.0330222000, 0.0567732000, 0.1161072000, 0.2722439000, 0.7002884000", \ - "0.0186115000, 0.0231320000, 0.0329198000, 0.0568156000, 0.1162538000, 0.2725798000, 0.6998747000", \ - "0.0187109000, 0.0231451000, 0.0330588000, 0.0568059000, 0.1161549000, 0.2729034000, 0.7001960000", \ - "0.0226941000, 0.0268374000, 0.0359614000, 0.0589383000, 0.1163152000, 0.2732374000, 0.6990457000", \ - "0.0329026000, 0.0379838000, 0.0476557000, 0.0697333000, 0.1217997000, 0.2737036000, 0.7008503000", \ - "0.0486345000, 0.0553051000, 0.0690480000, 0.0915071000, 0.1328102000, 0.2742781000, 0.6952895000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0242056000, 0.0314047000, 0.0497297000, 0.0990783000, 0.2316551000, 0.5818209000, 1.4971683000", \ - "0.0242759000, 0.0314312000, 0.0497794000, 0.0991419000, 0.2319707000, 0.5813369000, 1.5006186000", \ - "0.0242119000, 0.0314502000, 0.0497606000, 0.0991269000, 0.2319716000, 0.5810547000, 1.5063821000", \ - "0.0247672000, 0.0318888000, 0.0501287000, 0.0990925000, 0.2318677000, 0.5800873000, 1.4980952000", \ - "0.0279039000, 0.0349029000, 0.0526277000, 0.1008762000, 0.2325182000, 0.5820253000, 1.5041545000", \ - "0.0344306000, 0.0417703000, 0.0586134000, 0.1037952000, 0.2339139000, 0.5808957000, 1.5039107000", \ - "0.0474830000, 0.0553632000, 0.0733093000, 0.1148121000, 0.2363534000, 0.5829376000, 1.4942998000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0024350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042992000, 0.0042980000, 0.0042953000, 0.0043062000, 0.0043314000, 0.0043895000, 0.0045234000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004264200, -0.004303400, -0.004393800, -0.004394300, -0.004395400, -0.004397900, -0.004403700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025890000; - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.038283200, 0.0148092000, 0.0042298000", \ - "-0.203680300, -0.154250000, -0.164829400", \ - "-0.372544300, -0.327996800, -0.343459000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0520488000, 0.0001771000, 0.0095358000", \ - "0.2223288000, 0.1716777000, 0.1810365000", \ - "0.4021790000, 0.3527487000, 0.3633281000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1093665000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtp_2") { - leakage_power () { - value : 0.0086479000; - when : "RESET_B&D&GATE&Q"; - } - leakage_power () { - value : 0.0073569000; - when : "RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0071530000; - when : "!RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0074364000; - when : "RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0085534000; - when : "RESET_B&D&!GATE&Q"; - } - leakage_power () { - value : 0.0087372000; - when : "!RESET_B&D&GATE&!Q"; - } - leakage_power () { - value : 0.0085357000; - when : "!RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0070734000; - when : "!RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0088192000; - when : "RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0077190000; - when : "RESET_B&!D&!GATE&Q"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__dlrtp"; - cell_leakage_power : 0.0080032160; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084427000, 0.0083230000, 0.0080472000, 0.0081207000, 0.0082904000, 0.0086812000, 0.0095824000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025863000, 0.0024932000, 0.0022784000, 0.0023308000, 0.0024514000, 0.0027295000, 0.0033703000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018560000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0459453000, 0.2052389000, 0.3753236000", \ - "-0.129217500, 0.0300762000, 0.1964987000", \ - "-0.307847000, -0.149774100, 0.0129863000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2168438000, 0.3004538000, 0.3325990000", \ - "0.1210267000, 0.2046367000, 0.2355612000", \ - "0.0644674000, 0.1431947000, 0.1704570000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.030959000, -0.192694000, -0.363999300", \ - "0.1429831000, -0.018752000, -0.186395200", \ - "0.3228333000, 0.1623190000, -0.002882800"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.201857400, -0.286688200, -0.320054100", \ - "-0.097495400, -0.182326200, -0.214471400", \ - "-0.007977200, -0.095249300, -0.127394500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017650000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173698000, 0.0172779000, 0.0170660000, 0.0171305000, 0.0172791000, 0.0176215000, 0.0184109000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101267000, 0.0100374000, 0.0098316000, 0.0098589000, 0.0099218000, 0.0100669000, 0.0104012000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018300000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1818682000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0234196000, 0.0221218000, 0.0185581000, 0.0076904000, -0.027643600, -0.132190500, -0.434186200", \ - "0.0233550000, 0.0220191000, 0.0184901000, 0.0075918000, -0.027713800, -0.132286700, -0.434261500", \ - "0.0234442000, 0.0221131000, 0.0186021000, 0.0077012000, -0.027608400, -0.132174000, -0.434152500", \ - "0.0233368000, 0.0219879000, 0.0184763000, 0.0075753000, -0.027752200, -0.132309200, -0.434276900", \ - "0.0232271000, 0.0218929000, 0.0183900000, 0.0074537000, -0.027828100, -0.132416900, -0.434384600", \ - "0.0238109000, 0.0223762000, 0.0181962000, 0.0072012000, -0.028025800, -0.132566900, -0.434549500", \ - "0.0255201000, 0.0241169000, 0.0200440000, 0.0079461000, -0.027980700, -0.132503600, -0.434416000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0264990000, 0.0281536000, 0.0328762000, 0.0459876000, 0.0823059000, 0.1857739000, 0.4862452000", \ - "0.0264517000, 0.0281578000, 0.0329553000, 0.0459946000, 0.0821612000, 0.1864357000, 0.4832232000", \ - "0.0265272000, 0.0282171000, 0.0329079000, 0.0460106000, 0.0821379000, 0.1864405000, 0.4869196000", \ - "0.0260980000, 0.0277619000, 0.0325690000, 0.0455617000, 0.0817728000, 0.1859576000, 0.4838922000", \ - "0.0259773000, 0.0276573000, 0.0323629000, 0.0454977000, 0.0817288000, 0.1851116000, 0.4834522000", \ - "0.0260851000, 0.0277598000, 0.0324904000, 0.0456031000, 0.0816398000, 0.1851365000, 0.4839416000", \ - "0.0274032000, 0.0289512000, 0.0334684000, 0.0462712000, 0.0824627000, 0.1863466000, 0.4835580000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0234708000, 0.0221447000, 0.0186036000, 0.0077588000, -0.027543400, -0.132082700, -0.434070300", \ - "0.0235362000, 0.0221896000, 0.0186273000, 0.0077254000, -0.027564700, -0.132106900, -0.434082200", \ - "0.0233913000, 0.0220039000, 0.0184866000, 0.0075853000, -0.027719300, -0.132259600, -0.434251400", \ - "0.0231012000, 0.0217615000, 0.0181598000, 0.0073023000, -0.027998700, -0.132535900, -0.434518300", \ - "0.0228578000, 0.0214777000, 0.0179794000, 0.0070722000, -0.028223400, -0.132751700, -0.434747200", \ - "0.0245209000, 0.0230843000, 0.0189572000, 0.0071344000, -0.028229700, -0.132768400, -0.434750500", \ - "0.0261175000, 0.0247079000, 0.0206483000, 0.0085597000, -0.027363200, -0.132040700, -0.434127200"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0244157000, 0.0260673000, 0.0308443000, 0.0439757000, 0.0802181000, 0.1836565000, 0.4824718000", \ - "0.0243935000, 0.0260894000, 0.0308790000, 0.0439234000, 0.0801596000, 0.1838032000, 0.4820451000", \ - "0.0243716000, 0.0260373000, 0.0308189000, 0.0438687000, 0.0801595000, 0.1841217000, 0.4820757000", \ - "0.0238885000, 0.0255428000, 0.0303225000, 0.0433612000, 0.0797396000, 0.1830017000, 0.4821504000", \ - "0.0235541000, 0.0252006000, 0.0299959000, 0.0430329000, 0.0793889000, 0.1827733000, 0.4819152000", \ - "0.0235176000, 0.0251910000, 0.0299202000, 0.0430280000, 0.0791403000, 0.1827720000, 0.4830119000", \ - "0.0250866000, 0.0266334000, 0.0311099000, 0.0438664000, 0.0800283000, 0.1837679000, 0.4821763000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0204105000, 0.0192793000, 0.0166843000, 0.0095528000, -0.025153600, -0.129835000, -0.431868900", \ - "0.0201690000, 0.0190447000, 0.0165805000, 0.0093560000, -0.025361900, -0.130063100, -0.432059900", \ - "0.0199259000, 0.0188168000, 0.0162028000, 0.0090874000, -0.025561400, -0.130253100, -0.432226300", \ - "0.0196540000, 0.0185233000, 0.0158982000, 0.0087691000, -0.025888000, -0.130514300, -0.432521000", \ - "0.0195448000, 0.0183158000, 0.0155807000, 0.0083012000, -0.026338400, -0.130880300, -0.432822700", \ - "0.0258220000, 0.0243153000, 0.0200647000, 0.0078054000, -0.026525400, -0.131048400, -0.432962600", \ - "0.0295354000, 0.0278459000, 0.0232712000, 0.0106112000, -0.025694700, -0.130042200, -0.431903300"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0209910000, 0.0226689000, 0.0273765000, 0.0403343000, 0.0763583000, 0.1793446000, 0.4781059000", \ - "0.0208857000, 0.0225258000, 0.0272871000, 0.0403163000, 0.0762833000, 0.1794612000, 0.4779643000", \ - "0.0205695000, 0.0222421000, 0.0269975000, 0.0400166000, 0.0760465000, 0.1793681000, 0.4778978000", \ - "0.0201439000, 0.0217900000, 0.0265761000, 0.0395489000, 0.0755969000, 0.1789546000, 0.4779105000", \ - "0.0200063000, 0.0216910000, 0.0265064000, 0.0392397000, 0.0754013000, 0.1788768000, 0.4773848000", \ - "0.0209916000, 0.0226752000, 0.0271330000, 0.0397389000, 0.0756818000, 0.1787308000, 0.4776404000", \ - "0.0222636000, 0.0237475000, 0.0280714000, 0.0407227000, 0.0767432000, 0.1799512000, 0.4768799000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.5026050000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2234919000, 0.2280904000, 0.2383190000, 0.2594198000, 0.3037469000, 0.4118728000, 0.7160265000", \ - "0.2284246000, 0.2329723000, 0.2432589000, 0.2644006000, 0.3086779000, 0.4168102000, 0.7207466000", \ - "0.2415662000, 0.2461135000, 0.2564086000, 0.2775460000, 0.3218143000, 0.4299448000, 0.7338093000", \ - "0.2728711000, 0.2774447000, 0.2876820000, 0.3088185000, 0.3531174000, 0.4612454000, 0.7652407000", \ - "0.3299571000, 0.3345115000, 0.3448133000, 0.3659040000, 0.4101880000, 0.5183090000, 0.8222065000", \ - "0.4191112000, 0.4236673000, 0.4339301000, 0.4550663000, 0.4993240000, 0.6074540000, 0.9106197000", \ - "0.5596972000, 0.5642203000, 0.5745239000, 0.5956805000, 0.6399628000, 0.7480843000, 1.0508810000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3252167000, 0.3313518000, 0.3455619000, 0.3782090000, 0.4600444000, 0.6895987000, 1.3486240000", \ - "0.3297153000, 0.3358128000, 0.3501506000, 0.3827382000, 0.4643511000, 0.6937437000, 1.3513458000", \ - "0.3409675000, 0.3471713000, 0.3613121000, 0.3939488000, 0.4755319000, 0.7049500000, 1.3632007000", \ - "0.3617738000, 0.3679180000, 0.3822776000, 0.4147631000, 0.4964576000, 0.7257916000, 1.3867183000", \ - "0.3893026000, 0.3954224000, 0.4095891000, 0.4422541000, 0.5241227000, 0.7529500000, 1.4146262000", \ - "0.4203854000, 0.4265638000, 0.4408562000, 0.4733741000, 0.5549575000, 0.7840365000, 1.4425277000", \ - "0.4438960000, 0.4500311000, 0.4644329000, 0.4969489000, 0.5786494000, 0.8079775000, 1.4651151000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0188757000, 0.0217986000, 0.0293257000, 0.0464013000, 0.0921593000, 0.2276455000, 0.6383835000", \ - "0.0191767000, 0.0219742000, 0.0292253000, 0.0463330000, 0.0919522000, 0.2276565000, 0.6320902000", \ - "0.0189793000, 0.0220693000, 0.0292256000, 0.0463250000, 0.0919749000, 0.2276584000, 0.6319508000", \ - "0.0190120000, 0.0220041000, 0.0290382000, 0.0465623000, 0.0921219000, 0.2276858000, 0.6322359000", \ - "0.0189551000, 0.0219281000, 0.0289856000, 0.0464174000, 0.0919763000, 0.2276893000, 0.6322340000", \ - "0.0191833000, 0.0221833000, 0.0290311000, 0.0464020000, 0.0917502000, 0.2277443000, 0.6311578000", \ - "0.0189322000, 0.0219420000, 0.0292952000, 0.0464218000, 0.0920938000, 0.2276496000, 0.6325480000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0256727000, 0.0306910000, 0.0439436000, 0.0811740000, 0.1936345000, 0.5279985000, 1.5000737000", \ - "0.0255284000, 0.0307617000, 0.0438207000, 0.0810582000, 0.1932704000, 0.5271116000, 1.4940906000", \ - "0.0254959000, 0.0306094000, 0.0439741000, 0.0810336000, 0.1937882000, 0.5274102000, 1.4987429000", \ - "0.0257766000, 0.0307576000, 0.0439272000, 0.0810082000, 0.1931899000, 0.5281151000, 1.4948061000", \ - "0.0253968000, 0.0306649000, 0.0438820000, 0.0811405000, 0.1933462000, 0.5277204000, 1.5009689000", \ - "0.0255290000, 0.0306450000, 0.0438269000, 0.0809928000, 0.1935538000, 0.5287225000, 1.5018672000", \ - "0.0258188000, 0.0307712000, 0.0439644000, 0.0809280000, 0.1932569000, 0.5276664000, 1.4937903000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2693630000, 0.2740034000, 0.2844419000, 0.3056507000, 0.3500941000, 0.4581376000, 0.7610941000", \ - "0.2739372000, 0.2786130000, 0.2890306000, 0.3102606000, 0.3547182000, 0.4628162000, 0.7656887000", \ - "0.2850878000, 0.2897105000, 0.3001794000, 0.3213751000, 0.3658593000, 0.4740090000, 0.7779052000", \ - "0.3095559000, 0.3142205000, 0.3246219000, 0.3458482000, 0.3903063000, 0.4984809000, 0.8014301000", \ - "0.3480903000, 0.3527695000, 0.3631994000, 0.3844405000, 0.4287777000, 0.5369167000, 0.8407927000", \ - "0.3994753000, 0.4041332000, 0.4145675000, 0.4357541000, 0.4802039000, 0.5883290000, 0.8921122000", \ - "0.4560848000, 0.4607291000, 0.4711644000, 0.4923879000, 0.5368205000, 0.6449775000, 0.9484322000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2902383000, 0.2963837000, 0.3107467000, 0.3433995000, 0.4253311000, 0.6537894000, 1.3138881000", \ - "0.2947669000, 0.3009238000, 0.3153489000, 0.3480297000, 0.4299618000, 0.6586550000, 1.3188923000", \ - "0.3055810000, 0.3117541000, 0.3261363000, 0.3587867000, 0.4406271000, 0.6698412000, 1.3303254000", \ - "0.3294642000, 0.3355783000, 0.3499648000, 0.3826003000, 0.4644171000, 0.6936629000, 1.3536399000", \ - "0.3689667000, 0.3750986000, 0.3894745000, 0.4220923000, 0.5038686000, 0.7332727000, 1.3920912000", \ - "0.4238710000, 0.4300294000, 0.4443923000, 0.4770743000, 0.5587011000, 0.7881386000, 1.4475084000", \ - "0.4916354000, 0.4977782000, 0.5121802000, 0.5447768000, 0.6265862000, 0.8560072000, 1.5125188000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0193786000, 0.0222883000, 0.0293222000, 0.0466947000, 0.0923341000, 0.2273749000, 0.6383422000", \ - "0.0194272000, 0.0223902000, 0.0293095000, 0.0468108000, 0.0922071000, 0.2278423000, 0.6342762000", \ - "0.0194371000, 0.0223781000, 0.0295059000, 0.0468205000, 0.0922441000, 0.2281812000, 0.6340776000", \ - "0.0193854000, 0.0224083000, 0.0293991000, 0.0468250000, 0.0924347000, 0.2282018000, 0.6398328000", \ - "0.0194484000, 0.0222461000, 0.0294869000, 0.0468883000, 0.0922665000, 0.2277640000, 0.6333523000", \ - "0.0194447000, 0.0222897000, 0.0293845000, 0.0464764000, 0.0922053000, 0.2278114000, 0.6337459000", \ - "0.0194365000, 0.0222733000, 0.0296234000, 0.0465445000, 0.0922253000, 0.2271225000, 0.6330309000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0254165000, 0.0304747000, 0.0438338000, 0.0811816000, 0.1942838000, 0.5271932000, 1.4972020000", \ - "0.0254788000, 0.0304030000, 0.0438696000, 0.0810933000, 0.1934738000, 0.5270731000, 1.4946394000", \ - "0.0254060000, 0.0304131000, 0.0437989000, 0.0810652000, 0.1933508000, 0.5270129000, 1.4986822000", \ - "0.0254039000, 0.0304766000, 0.0438087000, 0.0810906000, 0.1933179000, 0.5300849000, 1.5005229000", \ - "0.0254482000, 0.0304893000, 0.0438783000, 0.0811105000, 0.1934399000, 0.5296518000, 1.4999590000", \ - "0.0254337000, 0.0303932000, 0.0437407000, 0.0811156000, 0.1933797000, 0.5276068000, 1.5013832000", \ - "0.0255839000, 0.0304946000, 0.0439187000, 0.0812222000, 0.1937862000, 0.5278376000, 1.4948993000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1030551000, 0.1078102000, 0.1185345000, 0.1402398000, 0.1863929000, 0.2954804000, 0.5984339000", \ - "0.1082551000, 0.1130273000, 0.1237179000, 0.1454582000, 0.1916243000, 0.3007073000, 0.6032135000", \ - "0.1213571000, 0.1260866000, 0.1367852000, 0.1585097000, 0.2047403000, 0.3138504000, 0.6163779000", \ - "0.1535532000, 0.1583014000, 0.1689266000, 0.1906535000, 0.2368683000, 0.3459965000, 0.6490535000", \ - "0.2269163000, 0.2319704000, 0.2430169000, 0.2650275000, 0.3115994000, 0.4206789000, 0.7231694000", \ - "0.3518972000, 0.3586117000, 0.3733017000, 0.4008973000, 0.4526818000, 0.5624395000, 0.8646406000", \ - "0.5527144000, 0.5615906000, 0.5814550000, 0.6186978000, 0.6827939000, 0.7937774000, 1.0956632000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0959029000, 0.1018118000, 0.1155437000, 0.1476033000, 0.2286823000, 0.4570304000, 1.1157885000", \ - "0.1000821000, 0.1058945000, 0.1197525000, 0.1518776000, 0.2328534000, 0.4614043000, 1.1200232000", \ - "0.1084194000, 0.1142937000, 0.1281764000, 0.1601503000, 0.2416215000, 0.4704550000, 1.1291804000", \ - "0.1268137000, 0.1326458000, 0.1464859000, 0.1784779000, 0.2598642000, 0.4886538000, 1.1471034000", \ - "0.1591270000, 0.1654708000, 0.1801268000, 0.2133746000, 0.2953263000, 0.5244628000, 1.1876151000", \ - "0.2016118000, 0.2089514000, 0.2258944000, 0.2609809000, 0.3444091000, 0.5735382000, 1.2332114000", \ - "0.2330717000, 0.2431677000, 0.2651852000, 0.3069186000, 0.3934031000, 0.6233528000, 1.2800597000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0199905000, 0.0230984000, 0.0303909000, 0.0482849000, 0.0951495000, 0.2273851000, 0.6343357000", \ - "0.0202222000, 0.0230099000, 0.0307511000, 0.0483629000, 0.0950339000, 0.2266849000, 0.6364709000", \ - "0.0200209000, 0.0229497000, 0.0302658000, 0.0482973000, 0.0950976000, 0.2270461000, 0.6362271000", \ - "0.0200582000, 0.0229732000, 0.0303654000, 0.0483218000, 0.0952160000, 0.2273120000, 0.6338081000", \ - "0.0226026000, 0.0254616000, 0.0323708000, 0.0495048000, 0.0951388000, 0.2268175000, 0.6367558000", \ - "0.0336715000, 0.0372586000, 0.0453848000, 0.0622741000, 0.1030500000, 0.2285959000, 0.6369200000", \ - "0.0513264000, 0.0558449000, 0.0664460000, 0.0879652000, 0.1213470000, 0.2317202000, 0.6303124000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0232259000, 0.0284883000, 0.0420690000, 0.0798723000, 0.1929573000, 0.5281764000, 1.4967240000", \ - "0.0232422000, 0.0285396000, 0.0420377000, 0.0800395000, 0.1926824000, 0.5284283000, 1.4966707000", \ - "0.0235397000, 0.0284495000, 0.0420098000, 0.0798878000, 0.1931149000, 0.5278184000, 1.5026052000", \ - "0.0235293000, 0.0286179000, 0.0420635000, 0.0798418000, 0.1932006000, 0.5282971000, 1.4962692000", \ - "0.0263381000, 0.0316644000, 0.0449618000, 0.0821485000, 0.1940159000, 0.5286031000, 1.4997086000", \ - "0.0333701000, 0.0391878000, 0.0522019000, 0.0872519000, 0.1963437000, 0.5283147000, 1.5005042000", \ - "0.0466392000, 0.0531259000, 0.0674992000, 0.1010838000, 0.2022667000, 0.5303774000, 1.4950146000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0024330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043828000, 0.0044177000, 0.0044981000, 0.0044997000, 0.0045034000, 0.0045119000, 0.0045316000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004350400, -0.004326400, -0.004271100, -0.004284000, -0.004313700, -0.004382100, -0.004539900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.027296900, 0.0380026000, 0.0432923000", \ - "-0.187811200, -0.127394500, -0.123325500", \ - "-0.349350900, -0.295037800, -0.297072300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0447246000, -0.019354200, -0.025864600", \ - "0.2125632000, 0.1509258000, 0.1444154000", \ - "0.3899720000, 0.3283346000, 0.3218242000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1357308000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlrtp_4") { - leakage_power () { - value : 0.0093991000; - when : "RESET_B&D&GATE&Q"; - } - leakage_power () { - value : 0.0082253000; - when : "RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0080082000; - when : "!RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0083044000; - when : "RESET_B&!D&GATE&!Q"; - } - leakage_power () { - value : 0.0093045000; - when : "RESET_B&D&!GATE&Q"; - } - leakage_power () { - value : 0.0096075000; - when : "!RESET_B&D&GATE&!Q"; - } - leakage_power () { - value : 0.0093784000; - when : "!RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0079291000; - when : "!RESET_B&!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0096746000; - when : "RESET_B&D&!GATE&!Q"; - } - leakage_power () { - value : 0.0084782000; - when : "RESET_B&!D&!GATE&Q"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__dlrtp"; - cell_leakage_power : 0.0088309230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - clear : "!RESET_B"; - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083520000, 0.0082373000, 0.0079730000, 0.0080685000, 0.0082889000, 0.0087967000, 0.0099674000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025884000, 0.0024958000, 0.0022822000, 0.0023369000, 0.0024630000, 0.0027536000, 0.0034237000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018940000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0605937000, 0.2186667000, 0.3887513000", \ - "-0.115789700, 0.0410625000, 0.2074850000", \ - "-0.298081400, -0.138787800, 0.0227520000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2375957000, 0.3212057000, 0.3533509000", \ - "0.1344544000, 0.2180645000, 0.2489889000", \ - "0.0778952000, 0.1566224000, 0.1838848000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.039503900, -0.201238900, -0.373765000", \ - "0.1344382000, -0.026076200, -0.194940100", \ - "0.3142884000, 0.1525534000, -0.011427700"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.218947300, -0.304998700, -0.337143900", \ - "-0.109702500, -0.194533200, -0.226678400", \ - "-0.021404900, -0.107456400, -0.138380900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017590000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0170715000, 0.0169825000, 0.0167774000, 0.0168357000, 0.0169702000, 0.0172802000, 0.0179948000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0099904000, 0.0099039000, 0.0097043000, 0.0097354000, 0.0098070000, 0.0099720000, 0.0103526000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018230000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2027400000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0325836000, 0.0308713000, 0.0256626000, 0.0097571000, -0.046037400, -0.234454900, -0.842636700", \ - "0.0325201000, 0.0308065000, 0.0255365000, 0.0097013000, -0.046154000, -0.234615500, -0.842730100", \ - "0.0326051000, 0.0309612000, 0.0256895000, 0.0097799000, -0.046035400, -0.234509500, -0.842610400", \ - "0.0324894000, 0.0307641000, 0.0254716000, 0.0096546000, -0.046162500, -0.234595400, -0.842763500", \ - "0.0323056000, 0.0305967000, 0.0253405000, 0.0095440000, -0.046305500, -0.234775000, -0.842907100", \ - "0.0319216000, 0.0302007000, 0.0249703000, 0.0092881000, -0.046626700, -0.235036300, -0.843183600", \ - "0.0363201000, 0.0346156000, 0.0291488000, 0.0115161000, -0.046374100, -0.235232400, -0.843318900"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0375249000, 0.0393653000, 0.0454458000, 0.0644659000, 0.1236367000, 0.3110341000, 0.9166858000", \ - "0.0374055000, 0.0393477000, 0.0452396000, 0.0643438000, 0.1235405000, 0.3110344000, 0.9125769000", \ - "0.0374395000, 0.0392149000, 0.0452473000, 0.0644633000, 0.1235754000, 0.3109261000, 0.9131505000", \ - "0.0372216000, 0.0390503000, 0.0451179000, 0.0641517000, 0.1233246000, 0.3107523000, 0.9164864000", \ - "0.0369501000, 0.0388528000, 0.0448247000, 0.0640542000, 0.1231549000, 0.3106065000, 0.9119107000", \ - "0.0369454000, 0.0388228000, 0.0447853000, 0.0639021000, 0.1230355000, 0.3105745000, 0.9142032000", \ - "0.0389254000, 0.0407331000, 0.0465274000, 0.0652169000, 0.1244497000, 0.3120691000, 0.9114737000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0326689000, 0.0310230000, 0.0257407000, 0.0098658000, -0.045954100, -0.234366700, -0.842491100", \ - "0.0327434000, 0.0309139000, 0.0257150000, 0.0098129000, -0.045997700, -0.234396900, -0.842520900", \ - "0.0325801000, 0.0307639000, 0.0255604000, 0.0096286000, -0.046185300, -0.234576300, -0.842670400", \ - "0.0322192000, 0.0305118000, 0.0252915000, 0.0093527000, -0.046439900, -0.234843200, -0.842940800", \ - "0.0320769000, 0.0302439000, 0.0250469000, 0.0091432000, -0.046709200, -0.235066600, -0.843176200", \ - "0.0320074000, 0.0302757000, 0.0250505000, 0.0090684000, -0.046703300, -0.235069400, -0.843218500", \ - "0.0373643000, 0.0356290000, 0.0302158000, 0.0125908000, -0.045317800, -0.234318000, -0.842557600"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0355155000, 0.0373747000, 0.0433983000, 0.0626131000, 0.1216488000, 0.3098682000, 0.9160646000", \ - "0.0354797000, 0.0373300000, 0.0433679000, 0.0625067000, 0.1219055000, 0.3092104000, 0.9116346000", \ - "0.0354629000, 0.0372814000, 0.0433422000, 0.0624771000, 0.1218071000, 0.3090802000, 0.9152402000", \ - "0.0349602000, 0.0368100000, 0.0428292000, 0.0619697000, 0.1213600000, 0.3088995000, 0.9111883000", \ - "0.0345858000, 0.0364700000, 0.0424701000, 0.0616683000, 0.1207586000, 0.3084927000, 0.9123530000", \ - "0.0344986000, 0.0363752000, 0.0424397000, 0.0615599000, 0.1207929000, 0.3081712000, 0.9106624000", \ - "0.0364891000, 0.0382859000, 0.0441199000, 0.0628424000, 0.1220248000, 0.3096445000, 0.9104628000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0301746000, 0.0287857000, 0.0236457000, 0.0109999000, -0.043866000, -0.232744500, -0.840996100", \ - "0.0300690000, 0.0286284000, 0.0237369000, 0.0107417000, -0.044058600, -0.232918200, -0.841133600", \ - "0.0298324000, 0.0283718000, 0.0233523000, 0.0106167000, -0.044172100, -0.233037700, -0.841302400", \ - "0.0295782000, 0.0281155000, 0.0231812000, 0.0103372000, -0.044497700, -0.233297900, -0.841482600", \ - "0.0296600000, 0.0281021000, 0.0232089000, 0.0099979000, -0.044946200, -0.233602500, -0.841734200", \ - "0.0300818000, 0.0285811000, 0.0243203000, 0.0098535000, -0.045456100, -0.234098700, -0.842068900", \ - "0.0422981000, 0.0401940000, 0.0332560000, 0.0143316000, -0.044745600, -0.233531200, -0.841397100"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0316767000, 0.0335631000, 0.0395935000, 0.0588469000, 0.1178632000, 0.3048123000, 0.9074291000", \ - "0.0315672000, 0.0335003000, 0.0396318000, 0.0587641000, 0.1178317000, 0.3047975000, 0.9062796000", \ - "0.0314072000, 0.0333471000, 0.0393924000, 0.0586077000, 0.1176881000, 0.3048288000, 0.9057111000", \ - "0.0310212000, 0.0329607000, 0.0389892000, 0.0581638000, 0.1171711000, 0.3045028000, 0.9024729000", \ - "0.0311367000, 0.0329541000, 0.0389560000, 0.0577849000, 0.1169074000, 0.3042896000, 0.9064031000", \ - "0.0327825000, 0.0345626000, 0.0404114000, 0.0585562000, 0.1168333000, 0.3040329000, 0.9069039000", \ - "0.0348732000, 0.0365629000, 0.0420519000, 0.0601454000, 0.1189661000, 0.3060459000, 0.9033224000"); - } - } - max_capacitance : 0.5456640000; - max_transition : 1.5058610000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.2592540000, 0.2629058000, 0.2725143000, 0.2940973000, 0.3396658000, 0.4482861000, 0.7677223000", \ - "0.2642074000, 0.2678805000, 0.2774584000, 0.2990862000, 0.3447170000, 0.4533075000, 0.7731247000", \ - "0.2773618000, 0.2810313000, 0.2905897000, 0.3121930000, 0.3577756000, 0.4664462000, 0.7863974000", \ - "0.3085851000, 0.3122465000, 0.3218491000, 0.3434349000, 0.3890319000, 0.4976689000, 0.8173264000", \ - "0.3655556000, 0.3692105000, 0.3788228000, 0.4004117000, 0.4460356000, 0.5546945000, 0.8745998000", \ - "0.4544163000, 0.4580856000, 0.4676771000, 0.4892552000, 0.5348765000, 0.6432835000, 0.9631945000", \ - "0.5945840000, 0.5982565000, 0.6078172000, 0.6294166000, 0.6749764000, 0.7835727000, 1.1035751000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3592354000, 0.3639392000, 0.3764630000, 0.4063767000, 0.4813865000, 0.7025906000, 1.4068700000", \ - "0.3636973000, 0.3683976000, 0.3808679000, 0.4107837000, 0.4857688000, 0.7072679000, 1.4129030000", \ - "0.3750037000, 0.3795720000, 0.3922136000, 0.4221084000, 0.4971838000, 0.7186687000, 1.4231148000", \ - "0.3959096000, 0.4006133000, 0.4131472000, 0.4430488000, 0.5180584000, 0.7392742000, 1.4433503000", \ - "0.4232139000, 0.4279248000, 0.4404822000, 0.4704854000, 0.5455981000, 0.7666232000, 1.4725717000", \ - "0.4540313000, 0.4588012000, 0.4711998000, 0.5011305000, 0.5760497000, 0.7975763000, 1.5046906000", \ - "0.4770719000, 0.4817933000, 0.4942852000, 0.5242753000, 0.5993902000, 0.8202443000, 1.5243911000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0258119000, 0.0279701000, 0.0340482000, 0.0494526000, 0.0892538000, 0.2140550000, 0.6396557000", \ - "0.0256192000, 0.0278821000, 0.0339492000, 0.0490714000, 0.0894311000, 0.2136756000, 0.6401739000", \ - "0.0255632000, 0.0279096000, 0.0342932000, 0.0493309000, 0.0893148000, 0.2140633000, 0.6356931000", \ - "0.0255189000, 0.0278834000, 0.0338792000, 0.0489495000, 0.0890293000, 0.2140774000, 0.6355565000", \ - "0.0255864000, 0.0278476000, 0.0338974000, 0.0494095000, 0.0890149000, 0.2139561000, 0.6359305000", \ - "0.0257338000, 0.0278758000, 0.0341146000, 0.0490488000, 0.0884293000, 0.2136041000, 0.6404147000", \ - "0.0255949000, 0.0279328000, 0.0340551000, 0.0491381000, 0.0890468000, 0.2137763000, 0.6342637000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0304603000, 0.0339947000, 0.0437434000, 0.0726732000, 0.1647679000, 0.4781623000, 1.4975273000", \ - "0.0303943000, 0.0340278000, 0.0441927000, 0.0726133000, 0.1653331000, 0.4786584000, 1.5021355000", \ - "0.0305012000, 0.0342404000, 0.0441540000, 0.0726750000, 0.1651369000, 0.4774683000, 1.5005612000", \ - "0.0304946000, 0.0340077000, 0.0438054000, 0.0726772000, 0.1647992000, 0.4781853000, 1.4977520000", \ - "0.0306048000, 0.0340999000, 0.0441158000, 0.0726935000, 0.1651194000, 0.4787559000, 1.5021961000", \ - "0.0302707000, 0.0338768000, 0.0441871000, 0.0726382000, 0.1654313000, 0.4786986000, 1.5028937000", \ - "0.0303372000, 0.0337799000, 0.0440044000, 0.0726953000, 0.1651093000, 0.4778529000, 1.4948461000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3039242000, 0.3076970000, 0.3173756000, 0.3390456000, 0.3850246000, 0.4936530000, 0.8135505000", \ - "0.3085756000, 0.3122209000, 0.3219584000, 0.3436326000, 0.3895360000, 0.4981682000, 0.8180900000", \ - "0.3196760000, 0.3233190000, 0.3330642000, 0.3547689000, 0.4006152000, 0.5093589000, 0.8293825000", \ - "0.3440898000, 0.3477876000, 0.3575332000, 0.3792666000, 0.4250343000, 0.5337746000, 0.8534929000", \ - "0.3823787000, 0.3860233000, 0.3957513000, 0.4175319000, 0.4632762000, 0.5719420000, 0.8918684000", \ - "0.4332676000, 0.4369961000, 0.4467542000, 0.4685035000, 0.5142344000, 0.6230020000, 0.9430684000", \ - "0.4889557000, 0.4926609000, 0.5023815000, 0.5240571000, 0.5699421000, 0.6785503000, 0.9981576000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3232573000, 0.3279640000, 0.3404931000, 0.3705561000, 0.4455618000, 0.6669288000, 1.3708393000", \ - "0.3278602000, 0.3325592000, 0.3450653000, 0.3751055000, 0.4502485000, 0.6713706000, 1.3775134000", \ - "0.3386215000, 0.3433141000, 0.3558687000, 0.3858628000, 0.4609988000, 0.6826053000, 1.3882464000", \ - "0.3623861000, 0.3671061000, 0.3796331000, 0.4096591000, 0.4848077000, 0.7059854000, 1.4104687000", \ - "0.4016729000, 0.4063877000, 0.4188877000, 0.4489744000, 0.5239270000, 0.7454488000, 1.4513987000", \ - "0.4561226000, 0.4608510000, 0.4733687000, 0.5034002000, 0.5784469000, 0.7998686000, 1.5068863000", \ - "0.5231893000, 0.5279083000, 0.5404043000, 0.5704809000, 0.6455036000, 0.8670991000, 1.5707090000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0259525000, 0.0284410000, 0.0342608000, 0.0492423000, 0.0897866000, 0.2132206000, 0.6411103000", \ - "0.0261196000, 0.0283270000, 0.0344531000, 0.0493015000, 0.0896391000, 0.2137033000, 0.6366535000", \ - "0.0261270000, 0.0283881000, 0.0342679000, 0.0492755000, 0.0896033000, 0.2138941000, 0.6419076000", \ - "0.0259441000, 0.0283773000, 0.0342226000, 0.0490323000, 0.0895036000, 0.2134918000, 0.6406374000", \ - "0.0261197000, 0.0283329000, 0.0344595000, 0.0490793000, 0.0896309000, 0.2141790000, 0.6406875000", \ - "0.0259551000, 0.0283758000, 0.0342335000, 0.0490825000, 0.0888681000, 0.2140924000, 0.6425303000", \ - "0.0259406000, 0.0284948000, 0.0343178000, 0.0492794000, 0.0898784000, 0.2133747000, 0.6363873000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0302573000, 0.0338594000, 0.0438063000, 0.0725356000, 0.1651502000, 0.4783517000, 1.5047724000", \ - "0.0302839000, 0.0337771000, 0.0438208000, 0.0726368000, 0.1651036000, 0.4783407000, 1.5010693000", \ - "0.0302998000, 0.0337970000, 0.0438012000, 0.0726624000, 0.1650787000, 0.4772230000, 1.5012299000", \ - "0.0302901000, 0.0337164000, 0.0437971000, 0.0726789000, 0.1651234000, 0.4782026000, 1.5002788000", \ - "0.0303813000, 0.0337249000, 0.0437345000, 0.0726658000, 0.1652573000, 0.4785745000, 1.5042972000", \ - "0.0302706000, 0.0337699000, 0.0438074000, 0.0726141000, 0.1652766000, 0.4785319000, 1.5030227000", \ - "0.0302714000, 0.0337991000, 0.0438638000, 0.0726998000, 0.1649272000, 0.4788598000, 1.4985033000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.1386765000, 0.1425154000, 0.1525142000, 0.1750121000, 0.2222974000, 0.3307208000, 0.6486648000", \ - "0.1440165000, 0.1479276000, 0.1579765000, 0.1804750000, 0.2277732000, 0.3362193000, 0.6547002000", \ - "0.1572564000, 0.1611784000, 0.1711721000, 0.1937405000, 0.2410527000, 0.3495132000, 0.6684614000", \ - "0.1893814000, 0.1932977000, 0.2032887000, 0.2257439000, 0.2730852000, 0.3815353000, 0.6997805000", \ - "0.2653955000, 0.2691659000, 0.2791583000, 0.3014574000, 0.3487303000, 0.4571964000, 0.7760060000", \ - "0.4132025000, 0.4178603000, 0.4302079000, 0.4569165000, 0.5088130000, 0.6182234000, 0.9366907000", \ - "0.6522091000, 0.6584164000, 0.6744508000, 0.7101927000, 0.7767227000, 0.8912276000, 1.2086224000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.1242144000, 0.1287265000, 0.1408581000, 0.1704520000, 0.2450837000, 0.4660692000, 1.1707022000", \ - "0.1284224000, 0.1330187000, 0.1451609000, 0.1747537000, 0.2493221000, 0.4705165000, 1.1816377000", \ - "0.1370486000, 0.1416338000, 0.1538297000, 0.1834652000, 0.2580189000, 0.4787064000, 1.1846496000", \ - "0.1560717000, 0.1606477000, 0.1728259000, 0.2024149000, 0.2769226000, 0.4985458000, 1.2017984000", \ - "0.1944185000, 0.1992253000, 0.2119589000, 0.2419839000, 0.3168700000, 0.5386038000, 1.2436228000", \ - "0.2513932000, 0.2569332000, 0.2712661000, 0.3043390000, 0.3817888000, 0.6033106000, 1.3097136000", \ - "0.3088624000, 0.3159729000, 0.3343814000, 0.3740049000, 0.4571546000, 0.6795240000, 1.3831900000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0270001000, 0.0296666000, 0.0356816000, 0.0510341000, 0.0916496000, 0.2109197000, 0.6381913000", \ - "0.0270180000, 0.0293964000, 0.0356075000, 0.0511958000, 0.0915939000, 0.2111977000, 0.6373669000", \ - "0.0270130000, 0.0293925000, 0.0356915000, 0.0512648000, 0.0918691000, 0.2109925000, 0.6366901000", \ - "0.0270224000, 0.0293824000, 0.0356499000, 0.0510697000, 0.0917017000, 0.2110374000, 0.6379350000", \ - "0.0273261000, 0.0295653000, 0.0363930000, 0.0512278000, 0.0917080000, 0.2109567000, 0.6370999000", \ - "0.0392096000, 0.0417501000, 0.0484242000, 0.0628359000, 0.0993752000, 0.2120050000, 0.6364849000", \ - "0.0598581000, 0.0631708000, 0.0717691000, 0.0912339000, 0.1248262000, 0.2190501000, 0.6327043000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0286474000, 0.0324141000, 0.0426376000, 0.0715017000, 0.1646935000, 0.4785302000, 1.5024553000", \ - "0.0286256000, 0.0324248000, 0.0425988000, 0.0715917000, 0.1648201000, 0.4784459000, 1.5028284000", \ - "0.0286830000, 0.0322540000, 0.0424522000, 0.0713265000, 0.1646919000, 0.4777093000, 1.5006064000", \ - "0.0285711000, 0.0321071000, 0.0423341000, 0.0713654000, 0.1646231000, 0.4785089000, 1.5024092000", \ - "0.0306914000, 0.0342127000, 0.0444342000, 0.0729764000, 0.1651563000, 0.4773620000, 1.5058614000", \ - "0.0378829000, 0.0414117000, 0.0519298000, 0.0799510000, 0.1694455000, 0.4792852000, 1.5036219000", \ - "0.0519165000, 0.0563819000, 0.0679552000, 0.0956159000, 0.1791019000, 0.4818964000, 1.4973961000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0023760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042879000, 0.0043187000, 0.0043897000, 0.0043957000, 0.0044094000, 0.0044411000, 0.0045143000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004232900, -0.004215200, -0.004174400, -0.004186400, -0.004214100, -0.004278100, -0.004425200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.006544900, 0.0770651000, 0.1079896000", \ - "-0.164617800, -0.085890600, -0.057407600", \ - "-0.322495400, -0.251092400, -0.229933600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0312969000, -0.052313200, -0.085679000", \ - "0.1966940000, 0.1167461000, 0.0821595000", \ - "0.3692201000, 0.2917135000, 0.2607891000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1752772000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxbn_1") { - leakage_power () { - value : 0.0145786000; - when : "D&!GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0099651000; - when : "!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0100455000; - when : "!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0144845000; - when : "D&GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0114278000; - when : "D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0136483000; - when : "!D&GATE_N&Q&!Q_N"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__dlxbn"; - cell_leakage_power : 0.0123583100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078340000, 0.0077200000, 0.0074572000, 0.0075363000, 0.0077189000, 0.0081398000, 0.0091100000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026870000, 0.0025841000, 0.0023468000, 0.0024067000, 0.0025447000, 0.0028631000, 0.0035968000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018820000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1130840000, 0.2735983000, 0.4436829000", \ - "0.0758607000, 0.2339336000, 0.4003561000", \ - "0.0974264000, 0.2481751000, 0.4121562000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.2528463000, 0.2849915000", \ - "0.0526673000, 0.1362773000, 0.1684225000", \ - "-0.017319700, 0.0662904000, 0.0984355000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.099318400, -0.262274100, -0.434800100", \ - "-0.053550100, -0.215285200, -0.385369800", \ - "-0.051922500, -0.212436800, -0.382521500"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.156691400, -0.241522100, -0.274888000", \ - "-0.040122400, -0.124953100, -0.158319000", \ - "0.0298646000, -0.056186800, -0.088332000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017640000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173096000, 0.0171801000, 0.0168816000, 0.0169314000, 0.0170459000, 0.0173102000, 0.0179195000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102563000, 0.0101642000, 0.0099518000, 0.0099915000, 0.0100829000, 0.0102936000, 0.0107795000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018380000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1434204000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.001036300, 0.0028675000, 0.0098890000, 0.0165975000, 0.0087438000, -0.042299300, -0.198393300", \ - "-0.000990500, 0.0029023000, 0.0098834000, 0.0165442000, 0.0086250000, -0.042449700, -0.198577200", \ - "-0.000867700, 0.0030117000, 0.0099846000, 0.0165977000, 0.0086509000, -0.042453300, -0.198593200", \ - "-0.000907800, 0.0029671000, 0.0099409000, 0.0165427000, 0.0085953000, -0.042533500, -0.198670600", \ - "-0.000998000, 0.0028843000, 0.0098578000, 0.0164799000, 0.0085559000, -0.042548300, -0.198705400", \ - "-0.001198200, 0.0026983000, 0.0096996000, 0.0163857000, 0.0084887000, -0.042578700, -0.198702500", \ - "-0.001628800, 0.0023460000, 0.0095126000, 0.0164295000, 0.0088196000, -0.042072300, -0.198096500"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.000256100, 0.0014485000, 0.0056747000, 0.0158483000, 0.0401926000, 0.1017364000, 0.2617810000", \ - "-0.000221500, 0.0014624000, 0.0056312000, 0.0157565000, 0.0401485000, 0.1019386000, 0.2629173000", \ - "-0.000108700, 0.0015613000, 0.0057118000, 0.0158075000, 0.0401933000, 0.1014819000, 0.2630088000", \ - "-0.000150200, 0.0015046000, 0.0056339000, 0.0156636000, 0.0400448000, 0.1017542000, 0.2614824000", \ - "-0.000220500, 0.0014326000, 0.0055633000, 0.0156018000, 0.0398081000, 0.1015944000, 0.2620369000", \ - "-0.000368200, 0.0013027000, 0.0054563000, 0.0155469000, 0.0398357000, 0.1012646000, 0.2613645000", \ - "-0.000654200, 0.0011300000, 0.0055129000, 0.0159150000, 0.0405509000, 0.1025241000, 0.2611137000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.005346700, -0.000837600, 0.0073951000, 0.0159573000, 0.0099264000, -0.039892100, -0.195340900", \ - "-0.005292300, -0.000797000, 0.0074129000, 0.0159017000, 0.0098208000, -0.040033900, -0.195529300", \ - "-0.005147300, -0.000657000, 0.0075284000, 0.0159947000, 0.0098934000, -0.039996900, -0.195497400", \ - "-0.005182200, -0.000715300, 0.0074410000, 0.0158422000, 0.0096911000, -0.040249400, -0.195710700", \ - "-0.005255200, -0.000808800, 0.0073037000, 0.0156480000, 0.0094042000, -0.040507500, -0.196048100", \ - "-0.005380700, -0.000919700, 0.0072107000, 0.0155918000, 0.0094263000, -0.040508800, -0.196019900", \ - "-0.005634000, -0.001100900, 0.0071781000, 0.0157605000, 0.0098357000, -0.039909100, -0.195289400"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.006827300, -0.004080500, 0.0022346000, 0.0155542000, 0.0430996000, 0.1071512000, 0.2688445000", \ - "-0.006767200, -0.004024000, 0.0022760000, 0.0155865000, 0.0430574000, 0.1071190000, 0.2678444000", \ - "-0.006628900, -0.003901800, 0.0023687000, 0.0156327000, 0.0431045000, 0.1065961000, 0.2675259000", \ - "-0.006664000, -0.003947900, 0.0022889000, 0.0155022000, 0.0430059000, 0.1064721000, 0.2674589000", \ - "-0.006729800, -0.004027700, 0.0021865000, 0.0153680000, 0.0427553000, 0.1067590000, 0.2678384000", \ - "-0.006845600, -0.004120400, 0.0021409000, 0.0153980000, 0.0428709000, 0.1068401000, 0.2685178000", \ - "-0.007097400, -0.004298600, 0.0021206000, 0.0155731000, 0.0433012000, 0.1071508000, 0.2690790000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5041590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2121299000, 0.2178201000, 0.2298804000, 0.2546786000, 0.3087234000, 0.4386143000, 0.7762855000", \ - "0.2170238000, 0.2227048000, 0.2347865000, 0.2595802000, 0.3136272000, 0.4435078000, 0.7813439000", \ - "0.2302148000, 0.2358900000, 0.2479804000, 0.2727700000, 0.3268149000, 0.4567019000, 0.7951620000", \ - "0.2614035000, 0.2671338000, 0.2791945000, 0.3039883000, 0.3580470000, 0.4879369000, 0.8264776000", \ - "0.3183588000, 0.3240853000, 0.3361661000, 0.3609468000, 0.4150128000, 0.5448955000, 0.8827167000", \ - "0.4072506000, 0.4129810000, 0.4250610000, 0.4498553000, 0.5039397000, 0.6338379000, 0.9717137000", \ - "0.5473628000, 0.5531031000, 0.5651777000, 0.5900067000, 0.6441215000, 0.7740388000, 1.1116525000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3046440000, 0.3116510000, 0.3274408000, 0.3644608000, 0.4590998000, 0.7039878000, 1.3464588000", \ - "0.3091490000, 0.3163449000, 0.3320437000, 0.3690777000, 0.4637169000, 0.7087113000, 1.3542087000", \ - "0.3203715000, 0.3275507000, 0.3432284000, 0.3802349000, 0.4749091000, 0.7200210000, 1.3629553000", \ - "0.3413932000, 0.3484587000, 0.3642053000, 0.4012042000, 0.4958682000, 0.7406677000, 1.3829939000", \ - "0.3687806000, 0.3758433000, 0.3915814000, 0.4285972000, 0.5232738000, 0.7680996000, 1.4123058000", \ - "0.3993792000, 0.4065864000, 0.4222708000, 0.4592797000, 0.5539513000, 0.7989073000, 1.4415029000", \ - "0.4227205000, 0.4297782000, 0.4454695000, 0.4824689000, 0.5771514000, 0.8222910000, 1.4617931000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0197952000, 0.0240791000, 0.0343544000, 0.0585616000, 0.1199408000, 0.2859699000, 0.7401371000", \ - "0.0196821000, 0.0240459000, 0.0343346000, 0.0585441000, 0.1199655000, 0.2857615000, 0.7362355000", \ - "0.0196744000, 0.0240513000, 0.0342917000, 0.0585437000, 0.1199858000, 0.2860108000, 0.7340559000", \ - "0.0197642000, 0.0243323000, 0.0343633000, 0.0585689000, 0.1201895000, 0.2865904000, 0.7396249000", \ - "0.0197608000, 0.0243821000, 0.0343079000, 0.0585778000, 0.1199610000, 0.2858792000, 0.7385619000", \ - "0.0198067000, 0.0243886000, 0.0341686000, 0.0586165000, 0.1198906000, 0.2855802000, 0.7388717000", \ - "0.0198530000, 0.0244217000, 0.0344441000, 0.0586247000, 0.1200589000, 0.2860247000, 0.7317622000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0260344000, 0.0324453000, 0.0495949000, 0.0987823000, 0.2307317000, 0.5799972000, 1.5002608000", \ - "0.0259969000, 0.0325370000, 0.0495784000, 0.0988184000, 0.2309248000, 0.5790584000, 1.5041592000", \ - "0.0261365000, 0.0325599000, 0.0496116000, 0.0987828000, 0.2309534000, 0.5787119000, 1.5005471000", \ - "0.0258265000, 0.0323775000, 0.0494599000, 0.0987377000, 0.2309838000, 0.5804910000, 1.4987562000", \ - "0.0258085000, 0.0323690000, 0.0495311000, 0.0987602000, 0.2310338000, 0.5804427000, 1.5023127000", \ - "0.0259923000, 0.0325543000, 0.0495907000, 0.0988013000, 0.2308942000, 0.5797983000, 1.4996198000", \ - "0.0258947000, 0.0324338000, 0.0494970000, 0.0988058000, 0.2308668000, 0.5787521000, 1.4967549000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2378622000, 0.2436512000, 0.2558948000, 0.2808294000, 0.3349515000, 0.4648634000, 0.8027816000", \ - "0.2427521000, 0.2485342000, 0.2607334000, 0.2857110000, 0.3398290000, 0.4697794000, 0.8076401000", \ - "0.2553341000, 0.2611240000, 0.2733099000, 0.2982740000, 0.3524080000, 0.4823310000, 0.8199064000", \ - "0.2863239000, 0.2921223000, 0.3043137000, 0.3292649000, 0.3834111000, 0.5133361000, 0.8509848000", \ - "0.3532083000, 0.3590210000, 0.3711636000, 0.3961367000, 0.4502718000, 0.5802236000, 0.9189006000", \ - "0.4658089000, 0.4716140000, 0.4838264000, 0.5088317000, 0.5629983000, 0.6929570000, 1.0306428000", \ - "0.6399313000, 0.6457670000, 0.6580412000, 0.6831332000, 0.7373931000, 0.8673597000, 1.2050209000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3685564000, 0.3756005000, 0.3915004000, 0.4285594000, 0.5232380000, 0.7679627000, 1.4127804000", \ - "0.3737323000, 0.3808185000, 0.3966855000, 0.4337644000, 0.5284454000, 0.7736364000, 1.4147696000", \ - "0.3863315000, 0.3934418000, 0.4093150000, 0.4464062000, 0.5410878000, 0.7856852000, 1.4277630000", \ - "0.4172978000, 0.4243875000, 0.4402496000, 0.4773388000, 0.5720190000, 0.8167094000, 1.4597010000", \ - "0.4816899000, 0.4887982000, 0.5046054000, 0.5416933000, 0.6363881000, 0.8813369000, 1.5247399000", \ - "0.5856223000, 0.5927348000, 0.6085945000, 0.6456937000, 0.7403804000, 0.9851673000, 1.6300097000", \ - "0.7453759000, 0.7524618000, 0.7683317000, 0.8054674000, 0.9001332000, 1.1451798000, 1.7875242000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0203140000, 0.0244896000, 0.0345116000, 0.0586840000, 0.1202712000, 0.2861728000, 0.7407130000", \ - "0.0201174000, 0.0244232000, 0.0344063000, 0.0588179000, 0.1202844000, 0.2857632000, 0.7375267000", \ - "0.0201167000, 0.0244136000, 0.0347620000, 0.0587617000, 0.1202657000, 0.2862937000, 0.7401652000", \ - "0.0201284000, 0.0244116000, 0.0344235000, 0.0588514000, 0.1203024000, 0.2860581000, 0.7363975000", \ - "0.0202802000, 0.0245966000, 0.0347612000, 0.0588998000, 0.1200031000, 0.2856223000, 0.7434009000", \ - "0.0204030000, 0.0245139000, 0.0345020000, 0.0588296000, 0.1204412000, 0.2860576000, 0.7391795000", \ - "0.0204979000, 0.0247004000, 0.0350302000, 0.0589950000, 0.1202800000, 0.2861398000, 0.7333866000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0258308000, 0.0323407000, 0.0496415000, 0.0987635000, 0.2306995000, 0.5801762000, 1.5013973000", \ - "0.0257440000, 0.0323707000, 0.0496518000, 0.0987825000, 0.2309191000, 0.5785483000, 1.5000825000", \ - "0.0257558000, 0.0323374000, 0.0496400000, 0.0988060000, 0.2310362000, 0.5787195000, 1.5013359000", \ - "0.0257563000, 0.0322763000, 0.0496168000, 0.0988155000, 0.2310615000, 0.5794060000, 1.4992940000", \ - "0.0257817000, 0.0323261000, 0.0496704000, 0.0988018000, 0.2310026000, 0.5802827000, 1.4953311000", \ - "0.0257199000, 0.0322911000, 0.0496184000, 0.0988132000, 0.2311795000, 0.5800465000, 1.5014163000", \ - "0.0257188000, 0.0322939000, 0.0496852000, 0.0988042000, 0.2309000000, 0.5781072000, 1.4998277000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0011357000, 0.0045331000, 0.0105938000, 0.0158558000, 0.0060231000, -0.048560100, -0.213242300", \ - "0.0011734000, 0.0045492000, 0.0105754000, 0.0157847000, 0.0058695000, -0.048770700, -0.213423000", \ - "0.0012883000, 0.0046605000, 0.0106471000, 0.0158040000, 0.0058900000, -0.048738500, -0.213432300", \ - "0.0012445000, 0.0045954000, 0.0105600000, 0.0156825000, 0.0056981000, -0.048970100, -0.213681000", \ - "0.0011722000, 0.0045197000, 0.0104751000, 0.0155889000, 0.0055941000, -0.049053300, -0.213780500", \ - "0.0010290000, 0.0044033000, 0.0104155000, 0.0155980000, 0.0057018000, -0.048914400, -0.213610600", \ - "0.0007287000, 0.0041934000, 0.0103956000, 0.0158613000, 0.0061362000, -0.048422700, -0.213036200"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002534400, -0.000382700, 0.0048093000, 0.0165983000, 0.0432570000, 0.1085162000, 0.2780763000", \ - "-0.002487500, -0.000350500, 0.0048223000, 0.0165494000, 0.0431866000, 0.1089310000, 0.2781665000", \ - "-0.002363900, -0.000237700, 0.0049112000, 0.0166053000, 0.0433330000, 0.1086594000, 0.2779708000", \ - "-0.002406000, -0.000285900, 0.0048531000, 0.0165308000, 0.0432729000, 0.1089256000, 0.2765999000", \ - "-0.002494100, -0.000365700, 0.0047837000, 0.0164765000, 0.0431030000, 0.1088580000, 0.2766386000", \ - "-0.002694000, -0.000551600, 0.0046313000, 0.0163745000, 0.0430399000, 0.1087365000, 0.2767452000", \ - "-0.003122000, -0.000899200, 0.0044306000, 0.0164304000, 0.0432924000, 0.1087699000, 0.2782444000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.005447100, -0.001015400, 0.0071425000, 0.0155713000, 0.0089070000, -0.043583200, -0.207211500", \ - "-0.005395900, -0.000969000, 0.0071586000, 0.0155279000, 0.0088301000, -0.043660800, -0.207298100", \ - "-0.005255800, -0.000851300, 0.0072515000, 0.0155903000, 0.0088458000, -0.043692900, -0.207361400", \ - "-0.005284400, -0.000885500, 0.0072129000, 0.0155297000, 0.0087783000, -0.043770900, -0.207434800", \ - "-0.005351300, -0.000959400, 0.0071048000, 0.0154574000, 0.0085715000, -0.043982600, -0.207668800", \ - "-0.005474100, -0.001086500, 0.0070059000, 0.0153311000, 0.0084969000, -0.043993500, -0.207680100", \ - "-0.005728600, -0.001260300, 0.0069788000, 0.0155122000, 0.0088435000, -0.043429100, -0.207008000"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.006851400, -0.004096700, 0.0023109000, 0.0159206000, 0.0446072000, 0.1109985000, 0.2813712000", \ - "-0.006790100, -0.004039600, 0.0023514000, 0.0159429000, 0.0446039000, 0.1112373000, 0.2803079000", \ - "-0.006652800, -0.003918700, 0.0024404000, 0.0159709000, 0.0444171000, 0.1115118000, 0.2809966000", \ - "-0.006687100, -0.003968200, 0.0023638000, 0.0158428000, 0.0442932000, 0.1109144000, 0.2800108000", \ - "-0.006755600, -0.004053500, 0.0022582000, 0.0157163000, 0.0440545000, 0.1108948000, 0.2805451000", \ - "-0.006885100, -0.004178100, 0.0021326000, 0.0155989000, 0.0439162000, 0.1103968000, 0.2806324000", \ - "-0.007146300, -0.004377000, 0.0020524000, 0.0156826000, 0.0443469000, 0.1106263000, 0.2793306000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5036670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3556919000, 0.3608323000, 0.3717662000, 0.3946686000, 0.4468007000, 0.5802704000, 0.9332556000", \ - "0.3602628000, 0.3654313000, 0.3763681000, 0.3992105000, 0.4513284000, 0.5849588000, 0.9369573000", \ - "0.3713272000, 0.3764715000, 0.3874112000, 0.4102666000, 0.4623787000, 0.5959902000, 0.9483060000", \ - "0.3921882000, 0.3973011000, 0.4082316000, 0.4311113000, 0.4832579000, 0.6167475000, 0.9694791000", \ - "0.4197036000, 0.4248205000, 0.4357286000, 0.4586344000, 0.5107733000, 0.6443565000, 0.9969999000", \ - "0.4504607000, 0.4556078000, 0.4665373000, 0.4894076000, 0.5415688000, 0.6751786000, 1.0279122000", \ - "0.4735901000, 0.4787152000, 0.4896435000, 0.5125403000, 0.5646670000, 0.6981866000, 1.0505007000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2656080000, 0.2718108000, 0.2862900000, 0.3220217000, 0.4149067000, 0.6590941000, 1.3028297000", \ - "0.2705118000, 0.2767126000, 0.2912240000, 0.3269259000, 0.4197348000, 0.6637337000, 1.3079693000", \ - "0.2837064000, 0.2899049000, 0.3044183000, 0.3401060000, 0.4328037000, 0.6778371000, 1.3239460000", \ - "0.3149339000, 0.3210652000, 0.3356564000, 0.3712515000, 0.4640858000, 0.7080529000, 1.3517297000", \ - "0.3719067000, 0.3780918000, 0.3925960000, 0.4282111000, 0.5210539000, 0.7645913000, 1.4091245000", \ - "0.4607994000, 0.4669666000, 0.4813733000, 0.5171207000, 0.6097232000, 0.8542625000, 1.4977146000", \ - "0.6009157000, 0.6070474000, 0.6216394000, 0.6572465000, 0.7500051000, 0.9943192000, 1.6385878000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0163987000, 0.0206549000, 0.0302192000, 0.0537172000, 0.1180329000, 0.2940821000, 0.7697785000", \ - "0.0166825000, 0.0204682000, 0.0302118000, 0.0538349000, 0.1178924000, 0.2941203000, 0.7660678000", \ - "0.0166209000, 0.0205330000, 0.0301088000, 0.0538874000, 0.1176843000, 0.2939077000, 0.7663857000", \ - "0.0165087000, 0.0205866000, 0.0299280000, 0.0538385000, 0.1178597000, 0.2932798000, 0.7701372000", \ - "0.0164223000, 0.0206255000, 0.0300328000, 0.0538245000, 0.1178889000, 0.2941595000, 0.7648198000", \ - "0.0163847000, 0.0206976000, 0.0300830000, 0.0536685000, 0.1177869000, 0.2939630000, 0.7673704000", \ - "0.0165228000, 0.0205110000, 0.0300054000, 0.0537382000, 0.1178059000, 0.2936369000, 0.7585907000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0200218000, 0.0266245000, 0.0444707000, 0.0934501000, 0.2256016000, 0.5759840000, 1.4998952000", \ - "0.0200217000, 0.0266345000, 0.0444960000, 0.0934995000, 0.2257570000, 0.5763250000, 1.5021052000", \ - "0.0200201000, 0.0266330000, 0.0444932000, 0.0934971000, 0.2252926000, 0.5742646000, 1.5007178000", \ - "0.0200434000, 0.0266912000, 0.0444213000, 0.0933835000, 0.2251118000, 0.5759274000, 1.5017151000", \ - "0.0200186000, 0.0265929000, 0.0444012000, 0.0934368000, 0.2253303000, 0.5771689000, 1.5014457000", \ - "0.0200358000, 0.0266208000, 0.0444332000, 0.0935403000, 0.2256020000, 0.5763010000, 1.4967054000", \ - "0.0200519000, 0.0266987000, 0.0444271000, 0.0934213000, 0.2257815000, 0.5740640000, 1.4991584000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4198065000, 0.4249283000, 0.4358128000, 0.4587964000, 0.5109308000, 0.6443367000, 0.9970674000", \ - "0.4245719000, 0.4296540000, 0.4406513000, 0.4636312000, 0.5156293000, 0.6491318000, 1.0020762000", \ - "0.4373277000, 0.4425245000, 0.4532760000, 0.4761393000, 0.5284690000, 0.6618930000, 1.0140251000", \ - "0.4682861000, 0.4734268000, 0.4843623000, 0.5072678000, 0.5594225000, 0.6928180000, 1.0453567000", \ - "0.5327545000, 0.5378756000, 0.5488121000, 0.5716039000, 0.6237575000, 0.7574560000, 1.1101147000", \ - "0.6367014000, 0.6420620000, 0.6526001000, 0.6755023000, 0.7280109000, 0.8612925000, 1.2147169000", \ - "0.7964515000, 0.8016319000, 0.8123632000, 0.8353115000, 0.8875858000, 1.0211086000, 1.3729720000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2916716000, 0.2978713000, 0.3123476000, 0.3480732000, 0.4406513000, 0.6850414000, 1.3316409000", \ - "0.2966153000, 0.3028166000, 0.3173077000, 0.3529755000, 0.4458230000, 0.6895871000, 1.3338144000", \ - "0.3093357000, 0.3155511000, 0.3300155000, 0.3656445000, 0.4587142000, 0.7029874000, 1.3451187000", \ - "0.3400278000, 0.3462431000, 0.3607663000, 0.3964568000, 0.4889573000, 0.7336372000, 1.3772355000", \ - "0.4068213000, 0.4130170000, 0.4275976000, 0.4633693000, 0.5557689000, 0.8009734000, 1.4433432000", \ - "0.5196037000, 0.5257952000, 0.5402601000, 0.5759814000, 0.6686954000, 0.9129431000, 1.5602292000", \ - "0.6935327000, 0.6997247000, 0.7142784000, 0.7500213000, 0.8425874000, 1.0868710000, 1.7312404000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0164320000, 0.0204612000, 0.0297987000, 0.0536778000, 0.1177750000, 0.2934461000, 0.7689879000", \ - "0.0163942000, 0.0203983000, 0.0299316000, 0.0536567000, 0.1177102000, 0.2940984000, 0.7630681000", \ - "0.0163927000, 0.0203981000, 0.0299810000, 0.0537847000, 0.1175414000, 0.2939727000, 0.7652878000", \ - "0.0165807000, 0.0204102000, 0.0300637000, 0.0536779000, 0.1176045000, 0.2933587000, 0.7682339000", \ - "0.0164073000, 0.0205551000, 0.0299701000, 0.0536614000, 0.1178548000, 0.2932540000, 0.7620121000", \ - "0.0163937000, 0.0204847000, 0.0300948000, 0.0536489000, 0.1177740000, 0.2942453000, 0.7628496000", \ - "0.0164570000, 0.0205040000, 0.0300745000, 0.0536870000, 0.1174564000, 0.2940625000, 0.7681760000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0200947000, 0.0266709000, 0.0444850000, 0.0934679000, 0.2252890000, 0.5761264000, 1.4996926000", \ - "0.0200691000, 0.0266726000, 0.0445097000, 0.0934458000, 0.2258862000, 0.5751812000, 1.5017967000", \ - "0.0200925000, 0.0266439000, 0.0444972000, 0.0933627000, 0.2255096000, 0.5772405000, 1.5036666000", \ - "0.0200928000, 0.0266449000, 0.0445304000, 0.0934901000, 0.2262234000, 0.5737144000, 1.5026941000", \ - "0.0201619000, 0.0267400000, 0.0444965000, 0.0933151000, 0.2253080000, 0.5759785000, 1.5035632000", \ - "0.0201145000, 0.0267220000, 0.0443658000, 0.0935193000, 0.2258769000, 0.5750735000, 1.5024603000", \ - "0.0201844000, 0.0267432000, 0.0445804000, 0.0935006000, 0.2257458000, 0.5735316000, 1.4991066000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxbn_2") { - leakage_power () { - value : 0.0137806000; - when : "D&!GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0104204000; - when : "!D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0104995000; - when : "!D&!GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0136861000; - when : "D&GATE_N&Q&!Q_N"; - } - leakage_power () { - value : 0.0118697000; - when : "D&GATE_N&!Q&Q_N"; - } - leakage_power () { - value : 0.0128598000; - when : "!D&GATE_N&Q&!Q_N"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__dlxbn"; - cell_leakage_power : 0.0121860000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077974000, 0.0076936000, 0.0074542000, 0.0075296000, 0.0077036000, 0.0081047000, 0.0090292000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026863000, 0.0025864000, 0.0023563000, 0.0024165000, 0.0025551000, 0.0028747000, 0.0036116000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018790000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1216289000, 0.2809225000, 0.4522279000", \ - "0.0819642000, 0.2400371000, 0.4064596000", \ - "0.1059714000, 0.2554994000, 0.4194805000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1826641000, 0.2662741000, 0.2971986000", \ - "0.0636536000, 0.1472637000, 0.1794089000", \ - "-0.008774700, 0.0760560000, 0.1082012000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.104201200, -0.267156900, -0.439682900", \ - "-0.059653600, -0.220168000, -0.390252600", \ - "-0.059246700, -0.219761100, -0.388625000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.166457000, -0.251287800, -0.284653600", \ - "-0.048667300, -0.134718700, -0.166863900", \ - "0.0213197000, -0.063511100, -0.096877000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017580000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172436000, 0.0171132000, 0.0168127000, 0.0168646000, 0.0169843000, 0.0172602000, 0.0178962000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103271000, 0.0101932000, 0.0098846000, 0.0099269000, 0.0100244000, 0.0102493000, 0.0107677000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018400000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1511099000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("-0.001125600, 0.0034152000, 0.0126106000, 0.0219867000, 0.0069957000, -0.086685900, -0.392135800", \ - "-0.001084100, 0.0034497000, 0.0126413000, 0.0219488000, 0.0069333000, -0.086839800, -0.392280700", \ - "-0.000971100, 0.0035383000, 0.0127128000, 0.0220044000, 0.0068975000, -0.086867900, -0.392321600", \ - "-0.001007900, 0.0035074000, 0.0126463000, 0.0219254000, 0.0068219000, -0.086938000, -0.392387000", \ - "-0.001091800, 0.0034253000, 0.0125952000, 0.0218642000, 0.0067983000, -0.086962300, -0.392409700", \ - "-0.001284400, 0.0032452000, 0.0124351000, 0.0217926000, 0.0067752000, -0.086930800, -0.392384900", \ - "-0.001704100, 0.0029061000, 0.0122584000, 0.0218555000, 0.0072027000, -0.086408700, -0.391768500"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("-0.000332700, 0.0015465000, 0.0067568000, 0.0209790000, 0.0593921000, 0.1666809000, 0.4748870000", \ - "-0.000288500, 0.0015822000, 0.0067630000, 0.0209719000, 0.0591905000, 0.1667441000, 0.4742527000", \ - "-0.000183000, 0.0016686000, 0.0068310000, 0.0209882000, 0.0593684000, 0.1659508000, 0.4741526000", \ - "-0.000221200, 0.0016151000, 0.0067173000, 0.0207752000, 0.0589293000, 0.1654430000, 0.4744280000", \ - "-0.000292600, 0.0015417000, 0.0066676000, 0.0207581000, 0.0589809000, 0.1655473000, 0.4767370000", \ - "-0.000442300, 0.0013970000, 0.0065442000, 0.0206826000, 0.0589250000, 0.1656786000, 0.4771818000", \ - "-0.000735900, 0.0012321000, 0.0066273000, 0.0212050000, 0.0597293000, 0.1671357000, 0.4738362000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("-0.005525400, -0.000438900, 0.0099701000, 0.0213090000, 0.0083984000, -0.084222300, -0.389099500", \ - "-0.005467300, -0.000400400, 0.0099715000, 0.0212582000, 0.0082160000, -0.084182000, -0.389074600", \ - "-0.005324200, -0.000262100, 0.0101071000, 0.0213363000, 0.0082469000, -0.084217400, -0.389104900", \ - "-0.005361500, -0.000314100, 0.0100192000, 0.0212063000, 0.0081180000, -0.084421300, -0.389368800", \ - "-0.005430400, -0.000408100, 0.0098920000, 0.0210007000, 0.0078970000, -0.084627900, -0.389543100", \ - "-0.005561500, -0.000527500, 0.0097701000, 0.0208751000, 0.0077610000, -0.084749100, -0.389670500", \ - "-0.005837800, -0.000726700, 0.0097391000, 0.0211810000, 0.0083194000, -0.084221000, -0.389085400"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("-0.007055800, -0.004237700, 0.0030807000, 0.0207225000, 0.0624825000, 0.1722359000, 0.4830113000", \ - "-0.006997000, -0.004196200, 0.0030847000, 0.0206899000, 0.0623948000, 0.1721248000, 0.4834655000", \ - "-0.006855300, -0.004064600, 0.0031892000, 0.0207430000, 0.0623923000, 0.1710940000, 0.4809445000", \ - "-0.006886800, -0.004095500, 0.0031494000, 0.0206951000, 0.0623626000, 0.1720556000, 0.4833768000", \ - "-0.006951900, -0.004181800, 0.0030317000, 0.0205334000, 0.0621859000, 0.1707113000, 0.4805563000", \ - "-0.007084800, -0.004305800, 0.0029418000, 0.0204631000, 0.0620894000, 0.1708755000, 0.4808748000", \ - "-0.007346400, -0.004474600, 0.0029786000, 0.0207983000, 0.0626851000, 0.1715393000, 0.4829394000"); - } - } - max_capacitance : 0.2938940000; - max_transition : 1.5026430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.2265558000, 0.2316121000, 0.2428099000, 0.2658178000, 0.3145826000, 0.4331925000, 0.7648480000", \ - "0.2315173000, 0.2365461000, 0.2478348000, 0.2708339000, 0.3195891000, 0.4381955000, 0.7693510000", \ - "0.2446349000, 0.2496228000, 0.2609707000, 0.2839127000, 0.3327428000, 0.4513445000, 0.7827641000", \ - "0.2759530000, 0.2810031000, 0.2922015000, 0.3152082000, 0.3639764000, 0.4825864000, 0.8138645000", \ - "0.3328558000, 0.3378988000, 0.3491125000, 0.3721203000, 0.4208901000, 0.5394996000, 0.8707412000", \ - "0.4217409000, 0.4267354000, 0.4380037000, 0.4609728000, 0.5097592000, 0.6283998000, 0.9596737000", \ - "0.5619326000, 0.5669544000, 0.5781630000, 0.6012009000, 0.6499857000, 0.7686292000, 1.0998531000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.3156103000, 0.3216708000, 0.3352906000, 0.3668345000, 0.4498071000, 0.6840657000, 1.3621433000", \ - "0.3205834000, 0.3265340000, 0.3401075000, 0.3715999000, 0.4546183000, 0.6888900000, 1.3665994000", \ - "0.3317321000, 0.3375674000, 0.3512135000, 0.3827580000, 0.4656813000, 0.7001217000, 1.3790856000", \ - "0.3525873000, 0.3585441000, 0.3719898000, 0.4034768000, 0.4864914000, 0.7207755000, 1.3955900000", \ - "0.3798742000, 0.3856979000, 0.3993244000, 0.4308583000, 0.5137871000, 0.7481202000, 1.4243068000", \ - "0.4108756000, 0.4165497000, 0.4302744000, 0.4618176000, 0.5447823000, 0.7791899000, 1.4573369000", \ - "0.4337141000, 0.4394275000, 0.4531338000, 0.4846554000, 0.5676551000, 0.8019458000, 1.4768500000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0195187000, 0.0226736000, 0.0310127000, 0.0499562000, 0.0999392000, 0.2457322000, 0.6921175000", \ - "0.0193763000, 0.0226005000, 0.0308973000, 0.0498929000, 0.0997356000, 0.2459176000, 0.6921216000", \ - "0.0193932000, 0.0226899000, 0.0306597000, 0.0498567000, 0.0997114000, 0.2457496000, 0.6899672000", \ - "0.0194263000, 0.0226629000, 0.0306623000, 0.0499552000, 0.0999402000, 0.2458734000, 0.6875915000", \ - "0.0195660000, 0.0229091000, 0.0310338000, 0.0499474000, 0.0999460000, 0.2458691000, 0.6870301000", \ - "0.0193569000, 0.0227434000, 0.0307454000, 0.0497631000, 0.0998217000, 0.2457491000, 0.6898321000", \ - "0.0193761000, 0.0227589000, 0.0310130000, 0.0497344000, 0.0999557000, 0.2455021000, 0.6857778000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0231428000, 0.0279297000, 0.0403775000, 0.0772087000, 0.1914287000, 0.5243492000, 1.4984338000", \ - "0.0231465000, 0.0277899000, 0.0402044000, 0.0772453000, 0.1908238000, 0.5250692000, 1.5010130000", \ - "0.0230860000, 0.0278579000, 0.0401830000, 0.0772432000, 0.1908425000, 0.5251171000, 1.5013307000", \ - "0.0230118000, 0.0275677000, 0.0404373000, 0.0772452000, 0.1909969000, 0.5237848000, 1.4946943000", \ - "0.0230420000, 0.0276270000, 0.0401996000, 0.0771712000, 0.1910618000, 0.5251685000, 1.4979895000", \ - "0.0229542000, 0.0277850000, 0.0403362000, 0.0772142000, 0.1910482000, 0.5242308000, 1.5008327000", \ - "0.0229681000, 0.0280906000, 0.0403539000, 0.0772278000, 0.1910310000, 0.5235387000, 1.4952387000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.2516889000, 0.2567748000, 0.2681383000, 0.2913223000, 0.3402157000, 0.4589176000, 0.7902925000", \ - "0.2565295000, 0.2616509000, 0.2730177000, 0.2961671000, 0.3451018000, 0.4637962000, 0.7951391000", \ - "0.2690931000, 0.2742129000, 0.2855997000, 0.3087711000, 0.3576496000, 0.4765536000, 0.8072711000", \ - "0.3001141000, 0.3052226000, 0.3165977000, 0.3397922000, 0.3886815000, 0.5073059000, 0.8386106000", \ - "0.3668955000, 0.3720035000, 0.3834271000, 0.4066099000, 0.4554913000, 0.5740190000, 0.9055041000", \ - "0.4792520000, 0.4843984000, 0.4957714000, 0.5189713000, 0.5678756000, 0.6865068000, 1.0181584000", \ - "0.6531468000, 0.6582854000, 0.6696905000, 0.6929077000, 0.7419440000, 0.8602717000, 1.1912136000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.3791911000, 0.3851438000, 0.3987617000, 0.4303120000, 0.5133963000, 0.7476781000, 1.4259692000", \ - "0.3839543000, 0.3899022000, 0.4035774000, 0.4351601000, 0.5181754000, 0.7525596000, 1.4278014000", \ - "0.3967530000, 0.4026603000, 0.4163416000, 0.4479163000, 0.5309665000, 0.7653362000, 1.4422046000", \ - "0.4276311000, 0.4335175000, 0.4471934000, 0.4788188000, 0.5617871000, 0.7961489000, 1.4716642000", \ - "0.4919820000, 0.4979167000, 0.5115930000, 0.5431988000, 0.6262528000, 0.8606424000, 1.5384050000", \ - "0.5955858000, 0.6014974000, 0.6151731000, 0.6467852000, 0.7298448000, 0.9642356000, 1.6413544000", \ - "0.7550360000, 0.7609497000, 0.7746078000, 0.8062143000, 0.8892552000, 1.1236478000, 1.8018107000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0197142000, 0.0232226000, 0.0310375000, 0.0501710000, 0.0998901000, 0.2458300000, 0.6883686000", \ - "0.0197847000, 0.0231637000, 0.0310934000, 0.0502839000, 0.1001989000, 0.2457163000, 0.6886148000", \ - "0.0198559000, 0.0231912000, 0.0311356000, 0.0502906000, 0.0999955000, 0.2457070000, 0.6862939000", \ - "0.0198202000, 0.0232256000, 0.0309212000, 0.0501898000, 0.0998910000, 0.2458712000, 0.6892103000", \ - "0.0199433000, 0.0231502000, 0.0309772000, 0.0501431000, 0.0999092000, 0.2457447000, 0.6887066000", \ - "0.0198776000, 0.0231546000, 0.0310550000, 0.0501569000, 0.1001964000, 0.2457635000, 0.6914395000", \ - "0.0200346000, 0.0234312000, 0.0311933000, 0.0505189000, 0.1003170000, 0.2458007000, 0.6865187000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0229411000, 0.0275554000, 0.0402503000, 0.0771904000, 0.1911777000, 0.5242561000, 1.5013477000", \ - "0.0229327000, 0.0274760000, 0.0402331000, 0.0771241000, 0.1911561000, 0.5249119000, 1.5026429000", \ - "0.0229229000, 0.0275998000, 0.0402300000, 0.0772261000, 0.1914399000, 0.5250910000, 1.5004835000", \ - "0.0229633000, 0.0275985000, 0.0402455000, 0.0771307000, 0.1912743000, 0.5247892000, 1.5018812000", \ - "0.0229128000, 0.0275754000, 0.0402305000, 0.0772744000, 0.1908894000, 0.5249957000, 1.4967210000", \ - "0.0229382000, 0.0275409000, 0.0401687000, 0.0771751000, 0.1915427000, 0.5241994000, 1.4997341000", \ - "0.0228227000, 0.0275775000, 0.0402000000, 0.0771736000, 0.1910119000, 0.5244167000, 1.4998532000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("0.0010997000, 0.0051582000, 0.0133811000, 0.0210498000, 0.0034705000, -0.097528600, -0.425587100", \ - "0.0011365000, 0.0051739000, 0.0133459000, 0.0209419000, 0.0032980000, -0.097743400, -0.425911100", \ - "0.0012460000, 0.0052752000, 0.0134209000, 0.0209713000, 0.0032873000, -0.097812800, -0.425907300", \ - "0.0012078000, 0.0052248000, 0.0133479000, 0.0208340000, 0.0031078000, -0.098012700, -0.426111500", \ - "0.0011372000, 0.0051513000, 0.0132733000, 0.0207920000, 0.0030178000, -0.098075800, -0.426185200", \ - "0.0009901000, 0.0050185000, 0.0131767000, 0.0207452000, 0.0030633000, -0.097982800, -0.426054800", \ - "0.0006803000, 0.0048104000, 0.0132054000, 0.0211826000, 0.0035923000, -0.097436000, -0.425491600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.002687700, -0.000422100, 0.0058198000, 0.0219890000, 0.0634982000, 0.1784322000, 0.5083013000", \ - "-0.002643100, -0.000387700, 0.0058183000, 0.0219609000, 0.0635224000, 0.1776150000, 0.5090291000", \ - "-0.002530100, -0.000283600, 0.0059196000, 0.0220118000, 0.0635048000, 0.1777833000, 0.5104629000", \ - "-0.002570000, -0.000330200, 0.0058577000, 0.0219279000, 0.0634441000, 0.1776029000, 0.5089393000", \ - "-0.002656000, -0.000412800, 0.0057830000, 0.0218673000, 0.0633961000, 0.1775721000, 0.5088784000", \ - "-0.002846800, -0.000586900, 0.0056548000, 0.0217971000, 0.0634146000, 0.1776193000, 0.5089687000", \ - "-0.003247300, -0.000894000, 0.0054966000, 0.0218602000, 0.0635507000, 0.1784877000, 0.5113116000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.005643200, -0.000662900, 0.0096545000, 0.0207482000, 0.0065795000, -0.092280400, -0.419402500", \ - "-0.005586200, -0.000621100, 0.0096778000, 0.0207068000, 0.0064842000, -0.092435300, -0.419588500", \ - "-0.005443900, -0.000487600, 0.0097618000, 0.0207575000, 0.0064924000, -0.092453100, -0.419652300", \ - "-0.005473300, -0.000521500, 0.0097218000, 0.0207107000, 0.0064278000, -0.092545500, -0.419698800", \ - "-0.005542700, -0.000607000, 0.0096024000, 0.0205232000, 0.0062290000, -0.092787000, -0.419957200", \ - "-0.005675300, -0.000727900, 0.0095006000, 0.0204583000, 0.0061605000, -0.092813700, -0.419995000", \ - "-0.005939000, -0.000900000, 0.0095426000, 0.0208747000, 0.0066310000, -0.092070300, -0.419173400"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.007100900, -0.004300500, 0.0031342000, 0.0212513000, 0.0647573000, 0.1814483000, 0.5110647000", \ - "-0.007037900, -0.004241400, 0.0032015000, 0.0213141000, 0.0647355000, 0.1803617000, 0.5145319000", \ - "-0.006897400, -0.004112200, 0.0033197000, 0.0213633000, 0.0647948000, 0.1803599000, 0.5114830000", \ - "-0.006929400, -0.004158600, 0.0032140000, 0.0212702000, 0.0646364000, 0.1801472000, 0.5135766000", \ - "-0.006998400, -0.004240200, 0.0031012000, 0.0210512000, 0.0643941000, 0.1800669000, 0.5144670000", \ - "-0.007135500, -0.004381400, 0.0029740000, 0.0209667000, 0.0642925000, 0.1807427000, 0.5112442000", \ - "-0.007399800, -0.004561300, 0.0029082000, 0.0210919000, 0.0645278000, 0.1798708000, 0.5145320000"); - } - } - max_capacitance : 0.3131200000; - max_transition : 1.5001250000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.3986607000, 0.4033885000, 0.4138998000, 0.4355383000, 0.4817410000, 0.5979814000, 0.9316996000", \ - "0.4033309000, 0.4079949000, 0.4185104000, 0.4401956000, 0.4863335000, 0.6027270000, 0.9365509000", \ - "0.4144808000, 0.4191456000, 0.4296809000, 0.4513834000, 0.4974975000, 0.6138666000, 0.9478055000", \ - "0.4352610000, 0.4399255000, 0.4504597000, 0.4721608000, 0.5183223000, 0.6346133000, 0.9682273000", \ - "0.4625613000, 0.4672214000, 0.4777906000, 0.4993452000, 0.5456155000, 0.6619199000, 0.9958596000", \ - "0.4934309000, 0.4980949000, 0.5086324000, 0.5303333000, 0.5763956000, 0.6927183000, 1.0264021000", \ - "0.5162827000, 0.5209666000, 0.5315200000, 0.5531512000, 0.5993707000, 0.7156373000, 1.0495573000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.3107031000, 0.3160290000, 0.3285954000, 0.3583986000, 0.4384469000, 0.6699907000, 1.3457059000", \ - "0.3157480000, 0.3210879000, 0.3335725000, 0.3633877000, 0.4434112000, 0.6746605000, 1.3510837000", \ - "0.3289298000, 0.3342298000, 0.3468104000, 0.3765205000, 0.4564285000, 0.6873509000, 1.3626474000", \ - "0.3600981000, 0.3654231000, 0.3779872000, 0.4078375000, 0.4877736000, 0.7186571000, 1.3949173000", \ - "0.4169800000, 0.4223242000, 0.4348943000, 0.4647429000, 0.5446705000, 0.7755381000, 1.4519369000", \ - "0.5059557000, 0.5112971000, 0.5238417000, 0.5535925000, 0.6334943000, 0.8644774000, 1.5407005000", \ - "0.6461397000, 0.6514708000, 0.6640164000, 0.6938695000, 0.7738058000, 1.0044628000, 1.6800692000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0191106000, 0.0221303000, 0.0292921000, 0.0474648000, 0.0953118000, 0.2421617000, 0.6911591000", \ - "0.0190253000, 0.0222373000, 0.0296220000, 0.0473537000, 0.0955077000, 0.2432297000, 0.6902082000", \ - "0.0190801000, 0.0223581000, 0.0295373000, 0.0472686000, 0.0953808000, 0.2432281000, 0.6876080000", \ - "0.0190750000, 0.0223504000, 0.0295435000, 0.0472766000, 0.0952291000, 0.2417642000, 0.6856087000", \ - "0.0190961000, 0.0220164000, 0.0295456000, 0.0472239000, 0.0955374000, 0.2432174000, 0.6900599000", \ - "0.0190885000, 0.0223733000, 0.0293503000, 0.0468060000, 0.0956545000, 0.2426145000, 0.6923591000", \ - "0.0192094000, 0.0223932000, 0.0297040000, 0.0471669000, 0.0952125000, 0.2426740000, 0.6842345000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0204202000, 0.0247174000, 0.0367954000, 0.0730258000, 0.1846520000, 0.5190021000, 1.4928249000", \ - "0.0204128000, 0.0246393000, 0.0367948000, 0.0728236000, 0.1841696000, 0.5174717000, 1.4954892000", \ - "0.0203143000, 0.0247236000, 0.0367622000, 0.0729121000, 0.1845801000, 0.5171097000, 1.4956143000", \ - "0.0204322000, 0.0247209000, 0.0368746000, 0.0729724000, 0.1844219000, 0.5179725000, 1.4968593000", \ - "0.0204058000, 0.0247833000, 0.0368744000, 0.0729523000, 0.1844223000, 0.5179795000, 1.4967719000", \ - "0.0202167000, 0.0245807000, 0.0368360000, 0.0727731000, 0.1845747000, 0.5179386000, 1.4913246000", \ - "0.0203159000, 0.0246464000, 0.0368078000, 0.0729514000, 0.1846795000, 0.5168421000, 1.4964295000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.4621998000, 0.4668292000, 0.4773082000, 0.4988899000, 0.5451640000, 0.6615030000, 0.9951026000", \ - "0.4671370000, 0.4718291000, 0.4823374000, 0.5040305000, 0.5501991000, 0.6665420000, 0.9993882000", \ - "0.4795104000, 0.4842019000, 0.4947123000, 0.5163418000, 0.5625002000, 0.6788263000, 1.0127705000", \ - "0.5105421000, 0.5152404000, 0.5257800000, 0.5473912000, 0.5935820000, 0.7099051000, 1.0428545000", \ - "0.5749544000, 0.5796124000, 0.5901188000, 0.6117362000, 0.6579374000, 0.7742534000, 1.1087500000", \ - "0.6786019000, 0.6833185000, 0.6938488000, 0.7154864000, 0.7616081000, 0.8779891000, 1.2116268000", \ - "0.8377883000, 0.8424701000, 0.8529866000, 0.8746159000, 0.9207610000, 1.0370375000, 1.3700409000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.3364264000, 0.3417312000, 0.3540460000, 0.3838587000, 0.4636377000, 0.6944012000, 1.3703411000", \ - "0.3412733000, 0.3466072000, 0.3591134000, 0.3889198000, 0.4687776000, 0.6995626000, 1.3756687000", \ - "0.3540246000, 0.3593637000, 0.3719336000, 0.4016352000, 0.4816980000, 0.7126695000, 1.3884658000", \ - "0.3846676000, 0.3900105000, 0.4024990000, 0.4323623000, 0.5123480000, 0.7431112000, 1.4180885000", \ - "0.4514769000, 0.4568106000, 0.4692292000, 0.4991016000, 0.5791358000, 0.8106075000, 1.4869249000", \ - "0.5638638000, 0.5691694000, 0.5816980000, 0.6115047000, 0.6913718000, 0.9222885000, 1.5977463000", \ - "0.7377459000, 0.7430747000, 0.7555465000, 0.7853868000, 0.8653335000, 1.0973937000, 1.7697710000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0189790000, 0.0220672000, 0.0292327000, 0.0472560000, 0.0957736000, 0.2412744000, 0.6914124000", \ - "0.0190766000, 0.0221119000, 0.0295644000, 0.0472081000, 0.0954713000, 0.2427412000, 0.6858782000", \ - "0.0192883000, 0.0222711000, 0.0295550000, 0.0472513000, 0.0957721000, 0.2429274000, 0.6867475000", \ - "0.0190278000, 0.0220557000, 0.0293243000, 0.0474453000, 0.0954022000, 0.2419462000, 0.6886224000", \ - "0.0190769000, 0.0220792000, 0.0292663000, 0.0475417000, 0.0957298000, 0.2412963000, 0.6886344000", \ - "0.0191107000, 0.0222508000, 0.0293966000, 0.0472195000, 0.0951727000, 0.2428254000, 0.6861237000", \ - "0.0191013000, 0.0222548000, 0.0294822000, 0.0474651000, 0.0953808000, 0.2424329000, 0.6891602000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0203911000, 0.0247683000, 0.0369042000, 0.0728803000, 0.1846199000, 0.5172959000, 1.4913055000", \ - "0.0204319000, 0.0248384000, 0.0368742000, 0.0730351000, 0.1847379000, 0.5168622000, 1.4974416000", \ - "0.0202404000, 0.0247093000, 0.0368260000, 0.0727903000, 0.1846234000, 0.5187255000, 1.4950319000", \ - "0.0204505000, 0.0246877000, 0.0368907000, 0.0729331000, 0.1846823000, 0.5184235000, 1.5001246000", \ - "0.0202322000, 0.0247252000, 0.0369807000, 0.0728257000, 0.1844478000, 0.5177483000, 1.4933078000", \ - "0.0204532000, 0.0248563000, 0.0369322000, 0.0729149000, 0.1847465000, 0.5184945000, 1.4984978000", \ - "0.0202677000, 0.0247935000, 0.0369733000, 0.0729412000, 0.1844582000, 0.5176445000, 1.4990545000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxbp_1") { - leakage_power () { - value : 0.0145768000; - when : "D&GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0099627000; - when : "!D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0100419000; - when : "!D&GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0144827000; - when : "D&!GATE&Q&!Q_N"; - } - leakage_power () { - value : 0.0114223000; - when : "D&!GATE&!Q&Q_N"; - } - leakage_power () { - value : 0.0136483000; - when : "!D&!GATE&Q&!Q_N"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__dlxbp"; - cell_leakage_power : 0.0123557900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0018060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080867000, 0.0079826000, 0.0077427000, 0.0078210000, 0.0080017000, 0.0084183000, 0.0093787000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024151000, 0.0023187000, 0.0020964000, 0.0021619000, 0.0023129000, 0.0026611000, 0.0034638000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018970000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0398418000, 0.2003561000, 0.3692201000", \ - "-0.134100300, 0.0251934000, 0.1903952000", \ - "-0.311509100, -0.153436200, 0.0093242000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2046367000, 0.2882467000, 0.3203919000", \ - "0.1124818000, 0.1948711000, 0.2270163000", \ - "0.0595846000, 0.1383119000, 0.1655742000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.027296900, -0.189031900, -0.359116500", \ - "0.1466452000, -0.015089800, -0.181512400", \ - "0.3252747000, 0.1647604000, 0.0007793000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.190871100, -0.276922500, -0.309067700", \ - "-0.091391900, -0.176222700, -0.207147100", \ - "-0.003094400, -0.090366500, -0.121291000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017560000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173274000, 0.0172369000, 0.0170283000, 0.0170909000, 0.0172350000, 0.0175676000, 0.0183341000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0100738000, 0.0099809000, 0.0097668000, 0.0098013000, 0.0098807000, 0.0100641000, 0.0104869000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018330000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1862623000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.001175100, 0.0027193000, 0.0097140000, 0.0163590000, 0.0084595000, -0.042621600, -0.198745500", \ - "-0.001134900, 0.0027463000, 0.0096971000, 0.0163369000, 0.0083725000, -0.042769200, -0.198896600", \ - "-0.001020700, 0.0028417000, 0.0097822000, 0.0163447000, 0.0083444000, -0.042794700, -0.198953000", \ - "-0.001064100, 0.0027993000, 0.0097313000, 0.0163034000, 0.0083290000, -0.042824000, -0.198969000", \ - "-0.001150000, 0.0027167000, 0.0096557000, 0.0162277000, 0.0082531000, -0.042897900, -0.199068300", \ - "-0.001347700, 0.0025373000, 0.0095072000, 0.0161369000, 0.0081882000, -0.042915100, -0.199041200", \ - "-0.001774700, 0.0021811000, 0.0093218000, 0.0161495000, 0.0084832000, -0.042441900, -0.198487600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.000107500, 0.0016139000, 0.0058703000, 0.0160981000, 0.0405018000, 0.1018425000, 0.2620111000", \ - "-7.28500e-05, 0.0016301000, 0.0058503000, 0.0160112000, 0.0404059000, 0.1019871000, 0.2629241000", \ - "2.540000e-05, 0.0017119000, 0.0058902000, 0.0160238000, 0.0404599000, 0.1016837000, 0.2620839000", \ - "-1.33500e-05, 0.0016647000, 0.0058363000, 0.0159366000, 0.0403080000, 0.1021842000, 0.2627540000", \ - "-9.39500e-05, 0.0015810000, 0.0057365000, 0.0158074000, 0.0400889000, 0.1014746000, 0.2620429000", \ - "-0.000249600, 0.0014453000, 0.0056477000, 0.0157941000, 0.0401166000, 0.1020749000, 0.2631286000", \ - "-0.000585200, 0.0012042000, 0.0055975000, 0.0160339000, 0.0405902000, 0.1026178000, 0.2612511000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.002070000, 0.0019651000, 0.0092187000, 0.0162812000, 0.0087960000, -0.042000000, -0.197981900", \ - "-0.002033300, 0.0019711000, 0.0092031000, 0.0162247000, 0.0086984000, -0.042126500, -0.198096700", \ - "-0.001940800, 0.0020548000, 0.0092518000, 0.0162216000, 0.0086209000, -0.042268800, -0.198236500", \ - "-0.001973800, 0.0019964000, 0.0091472000, 0.0160326000, 0.0083826000, -0.042542000, -0.198542800", \ - "-0.002022100, 0.0019502000, 0.0090893000, 0.0159473000, 0.0082594000, -0.042645100, -0.198674200", \ - "-0.002106200, 0.0018624000, 0.0090145000, 0.0159044000, 0.0082401000, -0.042664300, -0.198672300", \ - "-0.002246800, 0.0018278000, 0.0091852000, 0.0163738000, 0.0090475000, -0.041864000, -0.197858500"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("-0.003602400, -0.001408900, 0.0037897000, 0.0154503000, 0.0412921000, 0.1042877000, 0.2632626000", \ - "-0.003560900, -0.001374200, 0.0038135000, 0.0154530000, 0.0412795000, 0.1042570000, 0.2653408000", \ - "-0.003466800, -0.001296300, 0.0038528000, 0.0154276000, 0.0412078000, 0.1041558000, 0.2653342000", \ - "-0.003511500, -0.001381700, 0.0036923000, 0.0151608000, 0.0408157000, 0.1036800000, 0.2646256000", \ - "-0.003559900, -0.001441800, 0.0036074000, 0.0150306000, 0.0406243000, 0.1029755000, 0.2633263000", \ - "-0.003643700, -0.001516400, 0.0035507000, 0.0150036000, 0.0406584000, 0.1034600000, 0.2646184000", \ - "-0.003801400, -0.001593600, 0.0036315000, 0.0153093000, 0.0411294000, 0.1037983000, 0.2642040000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5074660000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2120791000, 0.2177621000, 0.2297887000, 0.2545351000, 0.3087580000, 0.4391578000, 0.7784307000", \ - "0.2170436000, 0.2227444000, 0.2347153000, 0.2595281000, 0.3137360000, 0.4441566000, 0.7834359000", \ - "0.2302489000, 0.2358795000, 0.2479144000, 0.2726724000, 0.3268743000, 0.4572888000, 0.7971787000", \ - "0.2614409000, 0.2671240000, 0.2791516000, 0.3038980000, 0.3581240000, 0.4885435000, 0.8278113000", \ - "0.3184823000, 0.3241641000, 0.3361942000, 0.3609389000, 0.4151648000, 0.5455791000, 0.8847898000", \ - "0.4075103000, 0.4131951000, 0.4252234000, 0.4499832000, 0.5042274000, 0.6346570000, 0.9739191000", \ - "0.5476012000, 0.5532956000, 0.5653253000, 0.5901180000, 0.6443877000, 0.7748326000, 1.1140777000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3047463000, 0.3117914000, 0.3274092000, 0.3643049000, 0.4590757000, 0.7040982000, 1.3519876000", \ - "0.3092771000, 0.3162490000, 0.3319298000, 0.3688415000, 0.4636184000, 0.7085085000, 1.3518379000", \ - "0.3202407000, 0.3273763000, 0.3429994000, 0.3799493000, 0.4747296000, 0.7199488000, 1.3637640000", \ - "0.3412706000, 0.3482675000, 0.3639400000, 0.4008524000, 0.4956259000, 0.7412568000, 1.3839531000", \ - "0.3685246000, 0.3755119000, 0.3912181000, 0.4281380000, 0.5229088000, 0.7680317000, 1.4120271000", \ - "0.3999362000, 0.4069273000, 0.4225814000, 0.4594966000, 0.5542648000, 0.7999066000, 1.4411919000", \ - "0.4226898000, 0.4297523000, 0.4454911000, 0.4824447000, 0.5772682000, 0.8222334000, 1.4635321000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0199128000, 0.0245126000, 0.0344214000, 0.0589054000, 0.1206677000, 0.2870650000, 0.7434167000", \ - "0.0198585000, 0.0242924000, 0.0345177000, 0.0588071000, 0.1207861000, 0.2872745000, 0.7425930000", \ - "0.0198264000, 0.0241842000, 0.0344020000, 0.0587665000, 0.1205704000, 0.2873634000, 0.7374912000", \ - "0.0199083000, 0.0245123000, 0.0344201000, 0.0589003000, 0.1206852000, 0.2873648000, 0.7428524000", \ - "0.0199071000, 0.0245190000, 0.0344222000, 0.0588468000, 0.1206207000, 0.2872597000, 0.7426678000", \ - "0.0199586000, 0.0245243000, 0.0342992000, 0.0588432000, 0.1204141000, 0.2872773000, 0.7456442000", \ - "0.0199978000, 0.0245610000, 0.0345582000, 0.0588497000, 0.1205696000, 0.2873537000, 0.7351411000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0261353000, 0.0325858000, 0.0496858000, 0.0990702000, 0.2317684000, 0.5801032000, 1.5045303000", \ - "0.0262079000, 0.0325930000, 0.0496549000, 0.0990744000, 0.2316366000, 0.5810051000, 1.5021527000", \ - "0.0261895000, 0.0327027000, 0.0497262000, 0.0991214000, 0.2314535000, 0.5815670000, 1.5025549000", \ - "0.0262096000, 0.0325874000, 0.0496394000, 0.0990606000, 0.2315582000, 0.5816505000, 1.5062723000", \ - "0.0261675000, 0.0325887000, 0.0496794000, 0.0990917000, 0.2314046000, 0.5818943000, 1.5010806000", \ - "0.0260998000, 0.0325554000, 0.0497195000, 0.0990725000, 0.2313233000, 0.5814080000, 1.5074656000", \ - "0.0263516000, 0.0325921000, 0.0497707000, 0.0990781000, 0.2316238000, 0.5802631000, 1.5001443000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2586902000, 0.2644426000, 0.2765564000, 0.3014530000, 0.3557282000, 0.4861933000, 0.8261172000", \ - "0.2633739000, 0.2691329000, 0.2812911000, 0.3061602000, 0.3604377000, 0.4909164000, 0.8302192000", \ - "0.2743011000, 0.2800213000, 0.2921522000, 0.3170651000, 0.3713392000, 0.5018099000, 0.8409859000", \ - "0.2987645000, 0.3045140000, 0.3166327000, 0.3415301000, 0.3958072000, 0.5262683000, 0.8654978000", \ - "0.3366825000, 0.3424386000, 0.3545750000, 0.3794547000, 0.4337368000, 0.5642068000, 0.9034020000", \ - "0.3885373000, 0.3942838000, 0.4064123000, 0.4312894000, 0.4855973000, 0.6160552000, 0.9550519000", \ - "0.4443464000, 0.4500727000, 0.4622043000, 0.4871167000, 0.5413875000, 0.6718531000, 1.0117327000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2875609000, 0.2945552000, 0.3103520000, 0.3473412000, 0.4421213000, 0.6876534000, 1.3297321000", \ - "0.2922012000, 0.2992432000, 0.3150058000, 0.3519946000, 0.4467814000, 0.6921484000, 1.3361920000", \ - "0.3028584000, 0.3098677000, 0.3256616000, 0.3626467000, 0.4574136000, 0.7029879000, 1.3456030000", \ - "0.3266799000, 0.3336868000, 0.3494827000, 0.3864697000, 0.4812532000, 0.7266215000, 1.3714833000", \ - "0.3661454000, 0.3731634000, 0.3889566000, 0.4259463000, 0.5207200000, 0.7659131000, 1.4101159000", \ - "0.4211171000, 0.4281407000, 0.4439245000, 0.4809070000, 0.5756812000, 0.8211295000, 1.4656909000", \ - "0.4890274000, 0.4960791000, 0.5118559000, 0.5488623000, 0.6436604000, 0.8890370000, 1.5311208000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0203792000, 0.0245708000, 0.0344361000, 0.0589639000, 0.1208279000, 0.2873508000, 0.7444091000", \ - "0.0203623000, 0.0246894000, 0.0348171000, 0.0589504000, 0.1208610000, 0.2875084000, 0.7443789000", \ - "0.0202439000, 0.0245507000, 0.0344858000, 0.0590381000, 0.1208577000, 0.2871712000, 0.7398747000", \ - "0.0203757000, 0.0244724000, 0.0344366000, 0.0589724000, 0.1208628000, 0.2874791000, 0.7478455000", \ - "0.0203551000, 0.0247512000, 0.0347130000, 0.0590589000, 0.1207427000, 0.2877510000, 0.7415692000", \ - "0.0203555000, 0.0244859000, 0.0344710000, 0.0588802000, 0.1205034000, 0.2874239000, 0.7432659000", \ - "0.0201994000, 0.0244897000, 0.0344681000, 0.0589880000, 0.1206151000, 0.2873928000, 0.7371770000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0258693000, 0.0324653000, 0.0497846000, 0.0990940000, 0.2315058000, 0.5803679000, 1.4997974000", \ - "0.0258986000, 0.0325004000, 0.0497821000, 0.0990913000, 0.2315909000, 0.5816599000, 1.5053906000", \ - "0.0258655000, 0.0324610000, 0.0498082000, 0.0990752000, 0.2315434000, 0.5811913000, 1.5062608000", \ - "0.0258710000, 0.0324679000, 0.0497913000, 0.0990849000, 0.2315949000, 0.5816597000, 1.5021470000", \ - "0.0259007000, 0.0324014000, 0.0497503000, 0.0992339000, 0.2316025000, 0.5819367000, 1.4996739000", \ - "0.0259883000, 0.0325204000, 0.0498399000, 0.0991140000, 0.2316407000, 0.5816521000, 1.5027830000", \ - "0.0259537000, 0.0325509000, 0.0497578000, 0.0990957000, 0.2317280000, 0.5822396000, 1.4988513000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0012832000, 0.0046956000, 0.0107907000, 0.0161007000, 0.0063495000, -0.048198700, -0.212865700", \ - "0.0013182000, 0.0047145000, 0.0107674000, 0.0160097000, 0.0061738000, -0.048413300, -0.213084900", \ - "0.0014234000, 0.0048073000, 0.0108226000, 0.0160234000, 0.0061391000, -0.048451300, -0.213139500", \ - "0.0013803000, 0.0047465000, 0.0107504000, 0.0159369000, 0.0060162000, -0.048623000, -0.213322800", \ - "0.0012983000, 0.0046656000, 0.0106567000, 0.0158058000, 0.0058734000, -0.048770300, -0.213468200", \ - "0.0011389000, 0.0045224000, 0.0105623000, 0.0157771000, 0.0059219000, -0.048666300, -0.213351000", \ - "0.0008072000, 0.0042907000, 0.0105366000, 0.0160576000, 0.0064048000, -0.048164700, -0.212780400"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002671800, -0.000533700, 0.0046264000, 0.0163576000, 0.0431593000, 0.1087789000, 0.2765262000", \ - "-0.002630400, -0.000507900, 0.0046284000, 0.0163410000, 0.0430775000, 0.1086960000, 0.2763927000", \ - "-0.002517800, -0.000407900, 0.0047077000, 0.0163524000, 0.0430360000, 0.1077432000, 0.2777406000", \ - "-0.002559000, -0.000450700, 0.0046470000, 0.0163017000, 0.0428288000, 0.1084175000, 0.2778490000", \ - "-0.002646100, -0.000534000, 0.0045823000, 0.0162295000, 0.0429556000, 0.1085204000, 0.2762571000", \ - "-0.002843700, -0.000717300, 0.0044326000, 0.0161299000, 0.0427418000, 0.1084234000, 0.2764420000", \ - "-0.003269800, -0.001056300, 0.0042192000, 0.0161632000, 0.0429946000, 0.1084979000, 0.2777030000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002218300, 0.0016628000, 0.0087010000, 0.0154313000, 0.0071116000, -0.046506300, -0.210698800", \ - "-0.002177300, 0.0016947000, 0.0087160000, 0.0154414000, 0.0070748000, -0.046554900, -0.210744900", \ - "-0.002081400, 0.0017793000, 0.0087671000, 0.0154446000, 0.0070462000, -0.046605800, -0.210837300", \ - "-0.002121900, 0.0016952000, 0.0086167000, 0.0151736000, 0.0066735000, -0.047053900, -0.211298700", \ - "-0.002175900, 0.0016278000, 0.0085166000, 0.0150194000, 0.0064600000, -0.047311600, -0.211540000", \ - "-0.002263800, 0.0015462000, 0.0084423000, 0.0149644000, 0.0064014000, -0.047345000, -0.211593800", \ - "-0.002413400, 0.0014861000, 0.0085606000, 0.0153356000, 0.0069517000, -0.046783100, -0.210961800"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.003568000, -0.001294100, 0.0041487000, 0.0162755000, 0.0433496000, 0.1089129000, 0.2789259000", \ - "-0.003528300, -0.001262900, 0.0041634000, 0.0163000000, 0.0432748000, 0.1088116000, 0.2787793000", \ - "-0.003439900, -0.001200100, 0.0041735000, 0.0162108000, 0.0433436000, 0.1093418000, 0.2769974000", \ - "-0.003471700, -0.001252500, 0.0040829000, 0.0160672000, 0.0429069000, 0.1089257000, 0.2784022000", \ - "-0.003518900, -0.001310300, 0.0040022000, 0.0159284000, 0.0429180000, 0.1078975000, 0.2766592000", \ - "-0.003602800, -0.001387800, 0.0039354000, 0.0159247000, 0.0427735000, 0.1081122000, 0.2779891000", \ - "-0.003749700, -0.001436400, 0.0040564000, 0.0163233000, 0.0432803000, 0.1091118000, 0.2764733000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5032770000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3558338000, 0.3609688000, 0.3719355000, 0.3948181000, 0.4469576000, 0.5804257000, 0.9330887000", \ - "0.3603808000, 0.3655264000, 0.3764662000, 0.3993738000, 0.4514800000, 0.5850058000, 0.9373274000", \ - "0.3714753000, 0.3765817000, 0.3875171000, 0.4104137000, 0.4625415000, 0.5960968000, 0.9486895000", \ - "0.3923952000, 0.3975444000, 0.4084819000, 0.4313854000, 0.4835277000, 0.6169901000, 0.9699787000", \ - "0.4196942000, 0.4248407000, 0.4357802000, 0.4586869000, 0.5107947000, 0.6443208000, 0.9966384000", \ - "0.4508874000, 0.4560408000, 0.4669920000, 0.4898508000, 0.5419193000, 0.6753933000, 1.0279739000", \ - "0.4740673000, 0.4792229000, 0.4901562000, 0.5130460000, 0.5651838000, 0.6986404000, 1.0510678000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2657219000, 0.2718930000, 0.2863550000, 0.3220115000, 0.4147978000, 0.6588499000, 1.3035277000", \ - "0.2706473000, 0.2768649000, 0.2913750000, 0.3270895000, 0.4200710000, 0.6636291000, 1.3085600000", \ - "0.2838331000, 0.2900247000, 0.3045334000, 0.3402033000, 0.4329218000, 0.6780420000, 1.3204953000", \ - "0.3150836000, 0.3212563000, 0.3357508000, 0.3713688000, 0.4642434000, 0.7089069000, 1.3520109000", \ - "0.3721222000, 0.3782993000, 0.3927960000, 0.4284073000, 0.5211918000, 0.7650948000, 1.4099527000", \ - "0.4611470000, 0.4673093000, 0.4817235000, 0.5174421000, 0.6100808000, 0.8545201000, 1.4983680000", \ - "0.6011825000, 0.6073794000, 0.6218502000, 0.6575684000, 0.7502484000, 0.9945591000, 1.6386342000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0165336000, 0.0207118000, 0.0302523000, 0.0538208000, 0.1179258000, 0.2941122000, 0.7700451000", \ - "0.0164632000, 0.0207767000, 0.0303356000, 0.0538031000, 0.1176789000, 0.2940512000, 0.7663593000", \ - "0.0165896000, 0.0207107000, 0.0300549000, 0.0539295000, 0.1179203000, 0.2934471000, 0.7663697000", \ - "0.0164942000, 0.0207914000, 0.0303319000, 0.0537773000, 0.1181194000, 0.2944585000, 0.7682948000", \ - "0.0164651000, 0.0207796000, 0.0303351000, 0.0537987000, 0.1176874000, 0.2940589000, 0.7694055000", \ - "0.0167597000, 0.0206362000, 0.0302787000, 0.0539233000, 0.1176820000, 0.2937680000, 0.7695459000", \ - "0.0164846000, 0.0208252000, 0.0303252000, 0.0538380000, 0.1175811000, 0.2942624000, 0.7590933000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0201669000, 0.0267428000, 0.0444719000, 0.0935164000, 0.2259131000, 0.5776842000, 1.4984538000", \ - "0.0202096000, 0.0268087000, 0.0444986000, 0.0933932000, 0.2260018000, 0.5779621000, 1.4970022000", \ - "0.0201324000, 0.0267425000, 0.0445908000, 0.0935867000, 0.2255527000, 0.5740567000, 1.5008580000", \ - "0.0201657000, 0.0267425000, 0.0444967000, 0.0935343000, 0.2254826000, 0.5760492000, 1.4974205000", \ - "0.0201298000, 0.0267010000, 0.0444954000, 0.0935574000, 0.2258277000, 0.5779115000, 1.4988460000", \ - "0.0201508000, 0.0267328000, 0.0444756000, 0.0935606000, 0.2258184000, 0.5767411000, 1.4956849000", \ - "0.0201437000, 0.0267521000, 0.0446046000, 0.0935940000, 0.2256396000, 0.5753731000, 1.4969269000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3387732000, 0.3438801000, 0.3548062000, 0.3777218000, 0.4298936000, 0.5633722000, 0.9157017000", \ - "0.3433381000, 0.3484943000, 0.3594111000, 0.3822851000, 0.4344797000, 0.5679167000, 0.9203643000", \ - "0.3541671000, 0.3593232000, 0.3702394000, 0.3931127000, 0.4452893000, 0.5788200000, 0.9316101000", \ - "0.3779376000, 0.3830885000, 0.3940149000, 0.4168942000, 0.4690395000, 0.6025577000, 0.9554720000", \ - "0.4174394000, 0.4226019000, 0.4335046000, 0.4564182000, 0.5085468000, 0.6421442000, 0.9949757000", \ - "0.4721761000, 0.4773088000, 0.4882360000, 0.5111468000, 0.5632757000, 0.6966513000, 1.0491338000", \ - "0.5403851000, 0.5455298000, 0.5564741000, 0.5792649000, 0.6314405000, 0.7648122000, 1.1188505000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3125596000, 0.3187247000, 0.3332797000, 0.3689246000, 0.4618448000, 0.7066780000, 1.3517523000", \ - "0.3171492000, 0.3233180000, 0.3378924000, 0.3735759000, 0.4663016000, 0.7120594000, 1.3572842000", \ - "0.3283342000, 0.3345101000, 0.3490893000, 0.3847763000, 0.4774995000, 0.7216266000, 1.3658877000", \ - "0.3526743000, 0.3588737000, 0.3734469000, 0.4091760000, 0.5016721000, 0.7464673000, 1.3905522000", \ - "0.3911507000, 0.3973840000, 0.4118887000, 0.4476416000, 0.5400503000, 0.7841940000, 1.4290681000", \ - "0.4421245000, 0.4482441000, 0.4627707000, 0.4985136000, 0.5909925000, 0.8362120000, 1.4798535000", \ - "0.4986337000, 0.5048331000, 0.5192539000, 0.5548231000, 0.6476852000, 0.8917823000, 1.5345109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0165843000, 0.0206113000, 0.0301571000, 0.0536738000, 0.1178237000, 0.2938710000, 0.7657884000", \ - "0.0165064000, 0.0206252000, 0.0302146000, 0.0535519000, 0.1179501000, 0.2940845000, 0.7684047000", \ - "0.0165086000, 0.0206261000, 0.0302101000, 0.0537096000, 0.1176136000, 0.2942976000, 0.7697434000", \ - "0.0164745000, 0.0206019000, 0.0302439000, 0.0538197000, 0.1174422000, 0.2942866000, 0.7628949000", \ - "0.0167030000, 0.0206150000, 0.0301422000, 0.0538337000, 0.1172889000, 0.2941520000, 0.7694416000", \ - "0.0165157000, 0.0206166000, 0.0302564000, 0.0537245000, 0.1180147000, 0.2933041000, 0.7681051000", \ - "0.0166886000, 0.0205608000, 0.0302773000, 0.0538871000, 0.1179726000, 0.2933681000, 0.7643448000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0201832000, 0.0267718000, 0.0446230000, 0.0935714000, 0.2253017000, 0.5765900000, 1.5002466000", \ - "0.0202526000, 0.0268101000, 0.0447501000, 0.0935417000, 0.2260135000, 0.5766368000, 1.5000331000", \ - "0.0202370000, 0.0268478000, 0.0445779000, 0.0934849000, 0.2258785000, 0.5775495000, 1.5009614000", \ - "0.0202809000, 0.0268453000, 0.0446084000, 0.0934516000, 0.2258849000, 0.5759488000, 1.5007370000", \ - "0.0202008000, 0.0268398000, 0.0444981000, 0.0935200000, 0.2255396000, 0.5751909000, 1.4997790000", \ - "0.0201456000, 0.0268373000, 0.0445361000, 0.0936114000, 0.2257202000, 0.5773994000, 1.5032772000", \ - "0.0201715000, 0.0267447000, 0.0445145000, 0.0935931000, 0.2253976000, 0.5749256000, 1.4976067000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxtn_1") { - leakage_power () { - value : 0.0085323000; - when : "D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0075450000; - when : "!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0076240000; - when : "!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0084382000; - when : "D&GATE_N&Q"; - } - leakage_power () { - value : 0.0090037000; - when : "D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0076041000; - when : "!D&GATE_N&Q"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__dlxtn"; - cell_leakage_power : 0.0081245310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078402000, 0.0077356000, 0.0074945000, 0.0075723000, 0.0077516000, 0.0081650000, 0.0091179000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027038000, 0.0025998000, 0.0023602000, 0.0024193000, 0.0025555000, 0.0028693000, 0.0035928000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018890000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1094219000, 0.2699362000, 0.4400208000", \ - "0.0746400000, 0.2327129000, 0.3991354000", \ - "0.0974264000, 0.2469544000, 0.4097148000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1594707000, 0.2443014000, 0.2764466000", \ - "0.0429017000, 0.1277324000, 0.1598776000", \ - "-0.025864600, 0.0589661000, 0.0911113000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.096877000, -0.259832700, -0.432358700", \ - "-0.051108700, -0.212843800, -0.382928400", \ - "-0.050701800, -0.211216100, -0.380080100"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.149367200, -0.234197900, -0.267563800", \ - "-0.034018900, -0.118849600, -0.150994800", \ - "0.0359681000, -0.050083300, -0.082228500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0174337000, 0.0173064000, 0.0170130000, 0.0170672000, 0.0171922000, 0.0174802000, 0.0181443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104621000, 0.0103328000, 0.0100349000, 0.0100801000, 0.0101843000, 0.0104243000, 0.0109779000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018240000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1390263000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0194427000, 0.0185018000, 0.0157110000, 0.0072134000, -0.016287900, -0.078214100, -0.240538100", \ - "0.0193613000, 0.0184013000, 0.0156379000, 0.0071405000, -0.016378700, -0.078299900, -0.240627400", \ - "0.0194416000, 0.0184853000, 0.0157203000, 0.0072065000, -0.016295400, -0.078217600, -0.240579300", \ - "0.0193294000, 0.0183498000, 0.0155876000, 0.0070911000, -0.016424000, -0.078348000, -0.240671800", \ - "0.0191249000, 0.0181865000, 0.0154174000, 0.0069142000, -0.016589200, -0.078518900, -0.240868700", \ - "0.0199591000, 0.0187432000, 0.0153932000, 0.0066971000, -0.016683400, -0.078596600, -0.240942700", \ - "0.0202932000, 0.0190979000, 0.0157550000, 0.0068691000, -0.016743100, -0.078497700, -0.240815400"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0198493000, 0.0214447000, 0.0252664000, 0.0344803000, 0.0580441000, 0.1194868000, 0.2808959000", \ - "0.0195915000, 0.0211771000, 0.0250548000, 0.0343613000, 0.0576939000, 0.1193281000, 0.2793952000", \ - "0.0197569000, 0.0213511000, 0.0251850000, 0.0343855000, 0.0577391000, 0.1193748000, 0.2803431000", \ - "0.0194685000, 0.0210889000, 0.0249856000, 0.0342127000, 0.0575671000, 0.1185320000, 0.2792915000", \ - "0.0192804000, 0.0208873000, 0.0247619000, 0.0339777000, 0.0572786000, 0.1182703000, 0.2793517000", \ - "0.0199776000, 0.0212543000, 0.0247897000, 0.0341466000, 0.0573642000, 0.1184286000, 0.2793541000", \ - "0.0207791000, 0.0221239000, 0.0255945000, 0.0346121000, 0.0579078000, 0.1192914000, 0.2785218000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0179207000, 0.0169453000, 0.0142031000, 0.0057122000, -0.017767900, -0.079672300, -0.242019700", \ - "0.0179667000, 0.0170172000, 0.0142508000, 0.0057701000, -0.017713700, -0.079621200, -0.241974300", \ - "0.0180552000, 0.0170850000, 0.0143327000, 0.0058457000, -0.017633800, -0.079551200, -0.241860300", \ - "0.0178089000, 0.0168445000, 0.0140734000, 0.0056015000, -0.017888100, -0.079804400, -0.242139000", \ - "0.0174822000, 0.0164910000, 0.0137383000, 0.0052570000, -0.018219400, -0.080129800, -0.242458100", \ - "0.0170820000, 0.0159988000, 0.0133743000, 0.0050757000, -0.018395500, -0.080298800, -0.242624400", \ - "0.0186768000, 0.0174287000, 0.0141052000, 0.0052197000, -0.018354500, -0.080042400, -0.242372100"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0192207000, 0.0208136000, 0.0247063000, 0.0339518000, 0.0573036000, 0.1182086000, 0.2792245000", \ - "0.0191399000, 0.0207262000, 0.0246340000, 0.0339374000, 0.0572832000, 0.1187637000, 0.2789263000", \ - "0.0192406000, 0.0208378000, 0.0247187000, 0.0339815000, 0.0573619000, 0.1188617000, 0.2801942000", \ - "0.0191115000, 0.0206930000, 0.0245790000, 0.0338439000, 0.0571809000, 0.1187230000, 0.2798466000", \ - "0.0188161000, 0.0204197000, 0.0243074000, 0.0336275000, 0.0569139000, 0.1185536000, 0.2798209000", \ - "0.0186896000, 0.0202746000, 0.0241575000, 0.0334022000, 0.0567682000, 0.1184161000, 0.2798004000", \ - "0.0198298000, 0.0211732000, 0.0246620000, 0.0336993000, 0.0571293000, 0.1179868000, 0.2790670000"); - } - } - max_capacitance : 0.1620580000; - max_transition : 1.4987460000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1977406000, 0.2029710000, 0.2139151000, 0.2366300000, 0.2873523000, 0.4152215000, 0.7501225000", \ - "0.2026872000, 0.2078935000, 0.2189108000, 0.2416028000, 0.2923631000, 0.4199729000, 0.7549407000", \ - "0.2158896000, 0.2210973000, 0.2320918000, 0.2547701000, 0.3055477000, 0.4332680000, 0.7671955000", \ - "0.2471454000, 0.2523324000, 0.2633652000, 0.2860300000, 0.3368027000, 0.4644545000, 0.7996424000", \ - "0.3041243000, 0.3093419000, 0.3203162000, 0.3430318000, 0.3938077000, 0.5215668000, 0.8554464000", \ - "0.3932923000, 0.3985302000, 0.4095237000, 0.4322085000, 0.4830111000, 0.6104779000, 0.9456652000", \ - "0.5335674000, 0.5387875000, 0.5498201000, 0.5725722000, 0.6233807000, 0.7510207000, 1.0858879000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2921861000, 0.2989597000, 0.3142699000, 0.3507253000, 0.4443991000, 0.6880339000, 1.3275501000", \ - "0.2965749000, 0.3035177000, 0.3189064000, 0.3554778000, 0.4490940000, 0.6928971000, 1.3334696000", \ - "0.3079650000, 0.3147597000, 0.3300657000, 0.3665316000, 0.4601078000, 0.7042761000, 1.3462291000", \ - "0.3287028000, 0.3355287000, 0.3509532000, 0.3875001000, 0.4808771000, 0.7249960000, 1.3652602000", \ - "0.3562342000, 0.3630836000, 0.3784681000, 0.4149837000, 0.5085998000, 0.7523037000, 1.3935374000", \ - "0.3872010000, 0.3937884000, 0.4092731000, 0.4458207000, 0.5392644000, 0.7834162000, 1.4242572000", \ - "0.4105344000, 0.4173810000, 0.4327745000, 0.4693564000, 0.5629273000, 0.8066080000, 1.4448049000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0165408000, 0.0207315000, 0.0300717000, 0.0531143000, 0.1141008000, 0.2823709000, 0.7305135000", \ - "0.0165219000, 0.0206894000, 0.0302187000, 0.0531655000, 0.1142728000, 0.2844138000, 0.7248920000", \ - "0.0165768000, 0.0207237000, 0.0302987000, 0.0532858000, 0.1143878000, 0.2824837000, 0.7257622000", \ - "0.0164718000, 0.0207949000, 0.0301533000, 0.0531699000, 0.1141895000, 0.2840460000, 0.7312637000", \ - "0.0165544000, 0.0207184000, 0.0302886000, 0.0532651000, 0.1145098000, 0.2828697000, 0.7289043000", \ - "0.0166596000, 0.0207361000, 0.0301304000, 0.0530895000, 0.1137211000, 0.2824451000, 0.7322187000", \ - "0.0166241000, 0.0208055000, 0.0303206000, 0.0532402000, 0.1142719000, 0.2843333000, 0.7210388000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0235216000, 0.0298754000, 0.0472344000, 0.0960146000, 0.2277257000, 0.5762649000, 1.4981640000", \ - "0.0235797000, 0.0301232000, 0.0471474000, 0.0960776000, 0.2273207000, 0.5762771000, 1.4987457000", \ - "0.0235292000, 0.0298468000, 0.0472283000, 0.0960335000, 0.2273280000, 0.5749948000, 1.4920184000", \ - "0.0236256000, 0.0299725000, 0.0471881000, 0.0957713000, 0.2278105000, 0.5754154000, 1.4929938000", \ - "0.0234564000, 0.0298341000, 0.0472192000, 0.0960111000, 0.2275768000, 0.5763014000, 1.4905256000", \ - "0.0235229000, 0.0301039000, 0.0472899000, 0.0958471000, 0.2271449000, 0.5760445000, 1.4922248000", \ - "0.0236710000, 0.0298418000, 0.0472342000, 0.0960094000, 0.2276230000, 0.5758365000, 1.4904025000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2235184000, 0.2288363000, 0.2399584000, 0.2627877000, 0.3136133000, 0.4413160000, 0.7749361000", \ - "0.2284364000, 0.2337396000, 0.2448348000, 0.2676752000, 0.3185075000, 0.4461173000, 0.7813942000", \ - "0.2411763000, 0.2464985000, 0.2576266000, 0.2804439000, 0.3312502000, 0.4588202000, 0.7941459000", \ - "0.2718841000, 0.2771880000, 0.2882735000, 0.3111064000, 0.3619804000, 0.4897526000, 0.8236034000", \ - "0.3384165000, 0.3437090000, 0.3548064000, 0.3776471000, 0.4284899000, 0.5560998000, 0.8904711000", \ - "0.4514674000, 0.4567998000, 0.4679305000, 0.4908160000, 0.5416680000, 0.6694449000, 1.0044237000", \ - "0.6257254000, 0.6310861000, 0.6423139000, 0.6652837000, 0.7162544000, 0.8439395000, 1.1774800000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.3558313000, 0.3627347000, 0.3781630000, 0.4148892000, 0.5084299000, 0.7524096000, 1.3925379000", \ - "0.3606996000, 0.3675758000, 0.3830263000, 0.4197361000, 0.5131250000, 0.7571747000, 1.3980729000", \ - "0.3733986000, 0.3803018000, 0.3957305000, 0.4324128000, 0.5260574000, 0.7694291000, 1.4132312000", \ - "0.4045115000, 0.4114193000, 0.4268727000, 0.4634562000, 0.5571565000, 0.8007912000, 1.4415891000", \ - "0.4687960000, 0.4756546000, 0.4911367000, 0.5278167000, 0.6214035000, 0.8650038000, 1.5073537000", \ - "0.5728787000, 0.5797529000, 0.5952243000, 0.6318397000, 0.7255596000, 0.9692701000, 1.6101026000", \ - "0.7326860000, 0.7395384000, 0.7550027000, 0.7916979000, 0.8851689000, 1.1291469000, 1.7686840000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0170946000, 0.0211233000, 0.0306130000, 0.0534920000, 0.1144274000, 0.2819626000, 0.7290630000", \ - "0.0170188000, 0.0210081000, 0.0305878000, 0.0535012000, 0.1144299000, 0.2851742000, 0.7329924000", \ - "0.0171071000, 0.0211018000, 0.0306585000, 0.0534509000, 0.1144079000, 0.2822488000, 0.7312548000", \ - "0.0169635000, 0.0210305000, 0.0305748000, 0.0535739000, 0.1147390000, 0.2834370000, 0.7274024000", \ - "0.0170045000, 0.0211518000, 0.0305670000, 0.0535697000, 0.1143493000, 0.2818290000, 0.7265917000", \ - "0.0172291000, 0.0211588000, 0.0305672000, 0.0535461000, 0.1140499000, 0.2844448000, 0.7319950000", \ - "0.0174525000, 0.0215613000, 0.0308684000, 0.0534563000, 0.1145851000, 0.2836060000, 0.7225581000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0233765000, 0.0299856000, 0.0473791000, 0.0960690000, 0.2277941000, 0.5754618000, 1.4910270000", \ - "0.0233331000, 0.0298347000, 0.0473508000, 0.0959204000, 0.2277172000, 0.5761531000, 1.4909562000", \ - "0.0233778000, 0.0299851000, 0.0473067000, 0.0959104000, 0.2278536000, 0.5757532000, 1.4950654000", \ - "0.0233878000, 0.0299915000, 0.0472935000, 0.0959467000, 0.2277667000, 0.5760465000, 1.4909501000", \ - "0.0233914000, 0.0299008000, 0.0472509000, 0.0959986000, 0.2275038000, 0.5760593000, 1.4927251000", \ - "0.0233840000, 0.0298768000, 0.0472551000, 0.0959432000, 0.2275976000, 0.5758924000, 1.4955789000", \ - "0.0233959000, 0.0298558000, 0.0472895000, 0.0958688000, 0.2277220000, 0.5748063000, 1.4916702000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxtn_2") { - leakage_power () { - value : 0.0081072000; - when : "D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0081600000; - when : "!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0082391000; - when : "!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0080127000; - when : "D&GATE_N&Q"; - } - leakage_power () { - value : 0.0096093000; - when : "D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0071863000; - when : "!D&GATE_N&Q"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__dlxtn"; - cell_leakage_power : 0.0082190830; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078002000, 0.0076953000, 0.0074535000, 0.0075281000, 0.0077000000, 0.0080964000, 0.0090101000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027046000, 0.0025991000, 0.0023559000, 0.0024120000, 0.0025415000, 0.0028398000, 0.0035273000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018800000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1179668000, 0.2772604000, 0.4473450000", \ - "0.0807435000, 0.2375957000, 0.4040182000", \ - "0.1071921000, 0.2542786000, 0.4158184000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1741191000, 0.2577292000, 0.2898743000", \ - "0.0575501000, 0.1399395000, 0.1720846000", \ - "-0.013657600, 0.0699525000, 0.1020977000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.264715500, -0.437241500", \ - "-0.055991500, -0.217726600, -0.387811200", \ - "-0.056805300, -0.216099000, -0.386183600"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.159132800, -0.243963600, -0.277329400", \ - "-0.042563800, -0.127394500, -0.160760400", \ - "0.0274232000, -0.058628300, -0.090773400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172260000, 0.0171026000, 0.0168182000, 0.0168699000, 0.0169889000, 0.0172633000, 0.0178959000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103317000, 0.0102005000, 0.0098980000, 0.0099419000, 0.0100429000, 0.0102756000, 0.0108122000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1467159000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014552770, 0.0042356610, 0.0123281200, 0.0358816500, 0.1044354000, 0.3039650000"); - values("0.0231537000, 0.0217908000, 0.0180865000, 0.0064502000, -0.030933800, -0.141813500, -0.464986900", \ - "0.0230832000, 0.0216953000, 0.0179965000, 0.0063487000, -0.031043100, -0.141900400, -0.465018900", \ - "0.0231523000, 0.0217892000, 0.0180633000, 0.0064326000, -0.030963200, -0.141837600, -0.464974500", \ - "0.0229973000, 0.0216323000, 0.0179363000, 0.0063143000, -0.031082300, -0.141951100, -0.465132600", \ - "0.0229176000, 0.0215280000, 0.0178369000, 0.0062421000, -0.031178900, -0.142050100, -0.465230900", \ - "0.0239031000, 0.0224489000, 0.0181833000, 0.0058786000, -0.031352800, -0.142205000, -0.465397500", \ - "0.0248764000, 0.0234546000, 0.0192047000, 0.0065461000, -0.031283800, -0.142166600, -0.465212200"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014552770, 0.0042356610, 0.0123281200, 0.0358816500, 0.1044354000, 0.3039650000"); - values("0.0251493000, 0.0269226000, 0.0318645000, 0.0454240000, 0.0834342000, 0.1928112000, 0.5150462000", \ - "0.0250866000, 0.0268058000, 0.0316920000, 0.0452922000, 0.0832265000, 0.1926102000, 0.5156674000", \ - "0.0251189000, 0.0268818000, 0.0317167000, 0.0452929000, 0.0832551000, 0.1928790000, 0.5149064000", \ - "0.0248642000, 0.0265838000, 0.0314572000, 0.0449870000, 0.0831747000, 0.1931395000, 0.5145192000", \ - "0.0246090000, 0.0263619000, 0.0313596000, 0.0449167000, 0.0828419000, 0.1923224000, 0.5147837000", \ - "0.0252318000, 0.0267693000, 0.0313264000, 0.0449544000, 0.0827346000, 0.1932402000, 0.5120162000", \ - "0.0261669000, 0.0278335000, 0.0324237000, 0.0456721000, 0.0837644000, 0.1935784000, 0.5140111000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014552770, 0.0042356610, 0.0123281200, 0.0358816500, 0.1044354000, 0.3039650000"); - values("0.0217687000, 0.0204162000, 0.0166636000, 0.0050929000, -0.032297100, -0.143168300, -0.466336500", \ - "0.0217826000, 0.0204233000, 0.0167362000, 0.0051307000, -0.032251500, -0.143102300, -0.466293400", \ - "0.0218912000, 0.0205646000, 0.0168392000, 0.0052074000, -0.032182500, -0.143031700, -0.466205600", \ - "0.0216601000, 0.0203141000, 0.0165548000, 0.0049399000, -0.032423600, -0.143280500, -0.466450700", \ - "0.0213267000, 0.0199525000, 0.0162252000, 0.0046190000, -0.032749800, -0.143610900, -0.466778100", \ - "0.0209274000, 0.0195885000, 0.0159228000, 0.0044440000, -0.032915400, -0.143749300, -0.466924200", \ - "0.0233452000, 0.0219028000, 0.0176428000, 0.0049342000, -0.032880900, -0.143562200, -0.466701100"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014552770, 0.0042356610, 0.0123281200, 0.0358816500, 0.1044354000, 0.3039650000"); - values("0.0246006000, 0.0263328000, 0.0312791000, 0.0448681000, 0.0828000000, 0.1931583000, 0.5144086000", \ - "0.0245278000, 0.0262473000, 0.0312349000, 0.0448230000, 0.0827791000, 0.1924894000, 0.5145286000", \ - "0.0246281000, 0.0263389000, 0.0312829000, 0.0449319000, 0.0828871000, 0.1925241000, 0.5155187000", \ - "0.0244610000, 0.0262171000, 0.0311538000, 0.0447687000, 0.0827215000, 0.1932073000, 0.5115310000", \ - "0.0241913000, 0.0259372000, 0.0309030000, 0.0444960000, 0.0825762000, 0.1920405000, 0.5145070000", \ - "0.0240377000, 0.0257864000, 0.0307395000, 0.0443892000, 0.0823504000, 0.1917708000, 0.5142921000", \ - "0.0253220000, 0.0269219000, 0.0315470000, 0.0448228000, 0.0826582000, 0.1920811000, 0.5115371000"); - } - } - max_capacitance : 0.3039650000; - max_transition : 1.5057880000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.2121812000, 0.2166480000, 0.2266485000, 0.2473505000, 0.2919738000, 0.4057235000, 0.7330521000", \ - "0.2172072000, 0.2216338000, 0.2316008000, 0.2521749000, 0.2968551000, 0.4106644000, 0.7365837000", \ - "0.2303512000, 0.2348116000, 0.2447572000, 0.2654059000, 0.3100446000, 0.4237013000, 0.7506525000", \ - "0.2615708000, 0.2659886000, 0.2759800000, 0.2966365000, 0.3412697000, 0.4550826000, 0.7824717000", \ - "0.3185154000, 0.3229350000, 0.3329271000, 0.3535168000, 0.3981984000, 0.5120401000, 0.8394331000", \ - "0.4073498000, 0.4117860000, 0.4218081000, 0.4424949000, 0.4870690000, 0.6006956000, 0.9274197000", \ - "0.5475674000, 0.5520284000, 0.5620366000, 0.5823576000, 0.6269600000, 0.7411821000, 1.0685696000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.3035817000, 0.3090276000, 0.3218174000, 0.3520171000, 0.4331745000, 0.6662761000, 1.3435418000", \ - "0.3080358000, 0.3135926000, 0.3261874000, 0.3563332000, 0.4376388000, 0.6705207000, 1.3492923000", \ - "0.3193955000, 0.3249284000, 0.3375498000, 0.3676604000, 0.4489692000, 0.6815620000, 1.3589777000", \ - "0.3401517000, 0.3457138000, 0.3583282000, 0.3884373000, 0.4697379000, 0.7021981000, 1.3818059000", \ - "0.3673244000, 0.3727558000, 0.3855811000, 0.4157953000, 0.4970805000, 0.7297572000, 1.4076197000", \ - "0.3983251000, 0.4036947000, 0.4165157000, 0.4467734000, 0.5279152000, 0.7611141000, 1.4393396000", \ - "0.4211606000, 0.4266382000, 0.4394427000, 0.4696780000, 0.5509210000, 0.7836049000, 1.4604977000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.0167038000, 0.0196443000, 0.0267994000, 0.0446159000, 0.0922787000, 0.2364903000, 0.6734689000", \ - "0.0167744000, 0.0197666000, 0.0269741000, 0.0446199000, 0.0924192000, 0.2379780000, 0.6803013000", \ - "0.0168269000, 0.0196298000, 0.0269929000, 0.0446167000, 0.0923714000, 0.2377980000, 0.6732740000", \ - "0.0168034000, 0.0196385000, 0.0268059000, 0.0446029000, 0.0922815000, 0.2382978000, 0.6725002000", \ - "0.0168846000, 0.0196438000, 0.0268109000, 0.0445322000, 0.0922285000, 0.2382749000, 0.6721226000", \ - "0.0167938000, 0.0196117000, 0.0269496000, 0.0442863000, 0.0922303000, 0.2378163000, 0.6766770000", \ - "0.0168433000, 0.0197301000, 0.0270169000, 0.0446912000, 0.0922735000, 0.2383186000, 0.6715058000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.0209960000, 0.0255437000, 0.0374161000, 0.0736398000, 0.1868527000, 0.5211414000, 1.5057883000", \ - "0.0210806000, 0.0252999000, 0.0374979000, 0.0736055000, 0.1865628000, 0.5215978000, 1.5015447000", \ - "0.0210465000, 0.0254832000, 0.0374985000, 0.0738331000, 0.1868540000, 0.5206455000, 1.5044482000", \ - "0.0212020000, 0.0254218000, 0.0374777000, 0.0737392000, 0.1867485000, 0.5217528000, 1.5036083000", \ - "0.0210292000, 0.0255752000, 0.0373815000, 0.0736585000, 0.1863180000, 0.5216479000, 1.5028722000", \ - "0.0211998000, 0.0256449000, 0.0375155000, 0.0737285000, 0.1860417000, 0.5212094000, 1.5026931000", \ - "0.0210702000, 0.0255138000, 0.0374080000, 0.0738058000, 0.1868415000, 0.5216823000, 1.4991658000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.2372596000, 0.2417848000, 0.2519019000, 0.2726657000, 0.3174336000, 0.4311969000, 0.7588147000", \ - "0.2421615000, 0.2467078000, 0.2568482000, 0.2775307000, 0.3223418000, 0.4361686000, 0.7622007000", \ - "0.2548733000, 0.2594048000, 0.2695403000, 0.2903337000, 0.3350623000, 0.4489080000, 0.7749181000", \ - "0.2855695000, 0.2901072000, 0.3002193000, 0.3209607000, 0.3657794000, 0.4795845000, 0.8071369000", \ - "0.3519608000, 0.3564912000, 0.3666180000, 0.3873699000, 0.4321840000, 0.5459533000, 0.8731152000", \ - "0.4646064000, 0.4691563000, 0.4792940000, 0.5000693000, 0.5448594000, 0.6587693000, 0.9851951000", \ - "0.6385268000, 0.6430937000, 0.6532403000, 0.6740616000, 0.7189483000, 0.8327457000, 1.1602774000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.3668934000, 0.3723876000, 0.3852395000, 0.4154933000, 0.4968662000, 0.7293126000, 1.4073779000", \ - "0.3717137000, 0.3771977000, 0.3900566000, 0.4203222000, 0.5014998000, 0.7344924000, 1.4137287000", \ - "0.3844691000, 0.3899767000, 0.4027981000, 0.4330862000, 0.5144296000, 0.7473789000, 1.4265420000", \ - "0.4153315000, 0.4208122000, 0.4336941000, 0.4639860000, 0.5453366000, 0.7782499000, 1.4557364000", \ - "0.4796996000, 0.4852115000, 0.4980668000, 0.5283651000, 0.6093833000, 0.8424090000, 1.5207313000", \ - "0.5833141000, 0.5888140000, 0.6016531000, 0.6319493000, 0.7133331000, 0.9461568000, 1.6247883000", \ - "0.7427181000, 0.7482230000, 0.7610830000, 0.7913573000, 0.8726912000, 1.1056681000, 1.7860708000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.0171280000, 0.0201662000, 0.0270508000, 0.0448006000, 0.0924487000, 0.2369028000, 0.6733462000", \ - "0.0172081000, 0.0201639000, 0.0271162000, 0.0448642000, 0.0923068000, 0.2378529000, 0.6815573000", \ - "0.0172161000, 0.0201426000, 0.0272789000, 0.0449942000, 0.0923456000, 0.2378814000, 0.6817766000", \ - "0.0170509000, 0.0201765000, 0.0272226000, 0.0448936000, 0.0925493000, 0.2386655000, 0.6769033000", \ - "0.0170640000, 0.0201832000, 0.0272457000, 0.0448462000, 0.0926016000, 0.2377839000, 0.6743754000", \ - "0.0173272000, 0.0203070000, 0.0273332000, 0.0449485000, 0.0921728000, 0.2384120000, 0.6835247000", \ - "0.0173390000, 0.0204621000, 0.0273874000, 0.0451070000, 0.0926556000, 0.2382992000, 0.6714114000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014552800, 0.0042356600, 0.0123281000, 0.0358816000, 0.1044350000, 0.3039650000"); - values("0.0208789000, 0.0252401000, 0.0373454000, 0.0737817000, 0.1867509000, 0.5214287000, 1.4994397000", \ - "0.0209121000, 0.0252739000, 0.0373356000, 0.0737144000, 0.1863657000, 0.5208572000, 1.4984578000", \ - "0.0209432000, 0.0253357000, 0.0373415000, 0.0736652000, 0.1870651000, 0.5207749000, 1.5013721000", \ - "0.0209672000, 0.0252966000, 0.0374046000, 0.0737481000, 0.1865038000, 0.5200566000, 1.4948646000", \ - "0.0208542000, 0.0252703000, 0.0373487000, 0.0737553000, 0.1870460000, 0.5215215000, 1.4975243000", \ - "0.0209532000, 0.0252705000, 0.0373433000, 0.0736497000, 0.1863470000, 0.5214513000, 1.5045565000", \ - "0.0208540000, 0.0252471000, 0.0373764000, 0.0737010000, 0.1866383000, 0.5199768000, 1.4971643000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxtn_4") { - leakage_power () { - value : 0.0085702000; - when : "D&!GATE_N&Q"; - } - leakage_power () { - value : 0.0087990000; - when : "!D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0088781000; - when : "!D&!GATE_N&!Q"; - } - leakage_power () { - value : 0.0084756000; - when : "D&GATE_N&Q"; - } - leakage_power () { - value : 0.0102483000; - when : "D&GATE_N&!Q"; - } - leakage_power () { - value : 0.0076493000; - when : "!D&GATE_N&Q"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__dlxtn"; - cell_leakage_power : 0.0087700780; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "!GATE_N"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078030000, 0.0076980000, 0.0074559000, 0.0075316000, 0.0077061000, 0.0081082000, 0.0090352000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027164000, 0.0026111000, 0.0023683000, 0.0024250000, 0.0025556000, 0.0028567000, 0.0035509000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018790000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1313945000, 0.2894674000, 0.4595521000", \ - "0.0856263000, 0.2424785000, 0.4101217000", \ - "0.1096335000, 0.2579408000, 0.4219219000"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1948711000, 0.2772604000, 0.3081849000", \ - "0.0746400000, 0.1570293000, 0.1891745000", \ - "-0.000229800, 0.0846009000, 0.1167461000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.109084000, -0.272039700, -0.445786400", \ - "-0.063315800, -0.225050800, -0.395135400", \ - "-0.064129600, -0.224643900, -0.393507800"); - } - related_pin : "GATE_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.173781300, -0.259832700, -0.293198600", \ - "-0.055991500, -0.140822300, -0.174188100", \ - "0.0164368000, -0.069614600, -0.101759800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE_N") { - capacitance : 0.0017450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172266000, 0.0171008000, 0.0168107000, 0.0168622000, 0.0169809000, 0.0172544000, 0.0178850000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103032000, 0.0102097000, 0.0099943000, 0.0100257000, 0.0100981000, 0.0102649000, 0.0106498000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1598980000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "GATE_N"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0323562000, 0.0306978000, 0.0254013000, 0.0093218000, -0.047044600, -0.235772100, -0.844056300", \ - "0.0322706000, 0.0305868000, 0.0253386000, 0.0092145000, -0.047111200, -0.235860300, -0.844141000", \ - "0.0323468000, 0.0306956000, 0.0253828000, 0.0093035000, -0.047012500, -0.235770600, -0.844062600", \ - "0.0322321000, 0.0305474000, 0.0252282000, 0.0091704000, -0.047187700, -0.235892900, -0.844224800", \ - "0.0321712000, 0.0304912000, 0.0251896000, 0.0090665000, -0.047311600, -0.235985100, -0.844312800", \ - "0.0317930000, 0.0301185000, 0.0248576000, 0.0088735000, -0.047456500, -0.236207700, -0.844473800", \ - "0.0360806000, 0.0343223000, 0.0287964000, 0.0110176000, -0.047063200, -0.236207600, -0.844322600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0367232000, 0.0385598000, 0.0445881000, 0.0637705000, 0.1226849000, 0.3110528000, 0.9141860000", \ - "0.0366439000, 0.0386175000, 0.0446331000, 0.0637572000, 0.1226600000, 0.3097460000, 0.9175669000", \ - "0.0367024000, 0.0386174000, 0.0446959000, 0.0635922000, 0.1225340000, 0.3099296000, 0.9127433000", \ - "0.0364404000, 0.0383530000, 0.0442735000, 0.0632747000, 0.1224339000, 0.3097067000, 0.9114330000", \ - "0.0362601000, 0.0381156000, 0.0440973000, 0.0631078000, 0.1222826000, 0.3095913000, 0.9108486000", \ - "0.0362911000, 0.0381998000, 0.0442605000, 0.0631907000, 0.1221408000, 0.3093698000, 0.9107099000", \ - "0.0377279000, 0.0395692000, 0.0455746000, 0.0642475000, 0.1234973000, 0.3118872000, 0.9097030000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0310354000, 0.0292443000, 0.0240194000, 0.0079488000, -0.048384200, -0.237090900, -0.845334400", \ - "0.0312027000, 0.0293590000, 0.0241466000, 0.0080129000, -0.048337300, -0.237026300, -0.845300000", \ - "0.0312212000, 0.0293953000, 0.0241843000, 0.0080530000, -0.048277700, -0.236946500, -0.845180400", \ - "0.0308385000, 0.0290894000, 0.0238573000, 0.0077478000, -0.048577700, -0.237293300, -0.845544400", \ - "0.0306240000, 0.0289476000, 0.0236690000, 0.0074993000, -0.048835900, -0.237505000, -0.845765200", \ - "0.0302856000, 0.0286895000, 0.0234031000, 0.0072661000, -0.049057600, -0.237770800, -0.846020300", \ - "0.0345697000, 0.0328203000, 0.0272434000, 0.0095220000, -0.048632500, -0.237552700, -0.845744500"); - } - related_pin : "GATE_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016043380, 0.0051478020, 0.0165176300, 0.0529997200, 0.1700589000, 0.5456641000"); - values("0.0361203000, 0.0379998000, 0.0440923000, 0.0631989000, 0.1222355000, 0.3106881000, 0.9155838000", \ - "0.0360547000, 0.0379224000, 0.0440473000, 0.0630868000, 0.1221921000, 0.3109873000, 0.9160814000", \ - "0.0361715000, 0.0380515000, 0.0440976000, 0.0632236000, 0.1221889000, 0.3106974000, 0.9163760000", \ - "0.0360866000, 0.0379723000, 0.0440465000, 0.0630820000, 0.1222267000, 0.3098875000, 0.9119964000", \ - "0.0357331000, 0.0375823000, 0.0436930000, 0.0627467000, 0.1221222000, 0.3087654000, 0.9120152000", \ - "0.0355970000, 0.0374866000, 0.0435689000, 0.0627007000, 0.1218660000, 0.3097534000, 0.9096674000", \ - "0.0369001000, 0.0387074000, 0.0445953000, 0.0633102000, 0.1220493000, 0.3092783000, 0.9159337000"); - } - } - max_capacitance : 0.5456640000; - max_transition : 1.5029060000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.2475619000, 0.2511780000, 0.2605122000, 0.2814000000, 0.3256432000, 0.4331991000, 0.7564027000", \ - "0.2525425000, 0.2561377000, 0.2654942000, 0.2863237000, 0.3305685000, 0.4382935000, 0.7607867000", \ - "0.2657365000, 0.2693168000, 0.2786633000, 0.2994887000, 0.3437592000, 0.4514520000, 0.7740115000", \ - "0.2968936000, 0.3005121000, 0.3098480000, 0.3307165000, 0.3749890000, 0.4825693000, 0.8046914000", \ - "0.3539077000, 0.3575318000, 0.3668504000, 0.3877506000, 0.4319745000, 0.5395362000, 0.8615660000", \ - "0.4428405000, 0.4464407000, 0.4557329000, 0.4766597000, 0.5207483000, 0.6284664000, 0.9510879000", \ - "0.5831920000, 0.5867953000, 0.5961113000, 0.6169370000, 0.6612222000, 0.7688605000, 1.0911015000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3306534000, 0.3346651000, 0.3457759000, 0.3727008000, 0.4445863000, 0.6677991000, 1.3833632000", \ - "0.3352458000, 0.3394223000, 0.3503760000, 0.3773525000, 0.4496264000, 0.6722097000, 1.3869107000", \ - "0.3464359000, 0.3507168000, 0.3616334000, 0.3885256000, 0.4605894000, 0.6834656000, 1.3979421000", \ - "0.3672900000, 0.3714948000, 0.3823228000, 0.4092448000, 0.4814406000, 0.7043697000, 1.4186383000", \ - "0.3944806000, 0.3986945000, 0.4095687000, 0.4364447000, 0.5086176000, 0.7316713000, 1.4489334000", \ - "0.4254579000, 0.4296946000, 0.4406642000, 0.4675879000, 0.5395945000, 0.7628094000, 1.4808617000", \ - "0.4484191000, 0.4526428000, 0.4636817000, 0.4905253000, 0.5626367000, 0.7858056000, 1.4976400000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0234685000, 0.0257109000, 0.0317567000, 0.0465572000, 0.0863999000, 0.2122282000, 0.6450527000", \ - "0.0233693000, 0.0256175000, 0.0315401000, 0.0463134000, 0.0863494000, 0.2123342000, 0.6392620000", \ - "0.0235797000, 0.0256588000, 0.0315231000, 0.0463394000, 0.0861828000, 0.2123856000, 0.6387346000", \ - "0.0234787000, 0.0257225000, 0.0316734000, 0.0464671000, 0.0864303000, 0.2121537000, 0.6437931000", \ - "0.0234317000, 0.0256911000, 0.0319297000, 0.0466017000, 0.0864428000, 0.2122687000, 0.6439547000", \ - "0.0235664000, 0.0255788000, 0.0316504000, 0.0464767000, 0.0859203000, 0.2123528000, 0.6375195000", \ - "0.0236087000, 0.0256752000, 0.0319174000, 0.0464247000, 0.0864773000, 0.2119492000, 0.6384053000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0249829000, 0.0284950000, 0.0373192000, 0.0649711000, 0.1591660000, 0.4758658000, 1.4982936000", \ - "0.0249054000, 0.0283179000, 0.0370795000, 0.0648732000, 0.1594591000, 0.4749818000, 1.5016969000", \ - "0.0252255000, 0.0280330000, 0.0370008000, 0.0649632000, 0.1591093000, 0.4747141000, 1.5016393000", \ - "0.0250266000, 0.0280278000, 0.0373190000, 0.0649417000, 0.1591538000, 0.4754701000, 1.5000881000", \ - "0.0250641000, 0.0280234000, 0.0374129000, 0.0649587000, 0.1594010000, 0.4751542000, 1.5021485000", \ - "0.0252752000, 0.0280603000, 0.0371855000, 0.0650114000, 0.1588009000, 0.4746950000, 1.5026019000", \ - "0.0250715000, 0.0281972000, 0.0372378000, 0.0649117000, 0.1594933000, 0.4750583000, 1.4965111000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.2726837000, 0.2763151000, 0.2857795000, 0.3067102000, 0.3512020000, 0.4589528000, 0.7813210000", \ - "0.2775841000, 0.2812403000, 0.2906599000, 0.3116149000, 0.3560857000, 0.4637860000, 0.7864820000", \ - "0.2903190000, 0.2939471000, 0.3034079000, 0.3243310000, 0.3688380000, 0.4765544000, 0.7988898000", \ - "0.3212375000, 0.3248565000, 0.3343032000, 0.3552498000, 0.3996987000, 0.5074016000, 0.8306167000", \ - "0.3877474000, 0.3913775000, 0.4008625000, 0.4217947000, 0.4662601000, 0.5739453000, 0.8963552000", \ - "0.5001267000, 0.5037434000, 0.5131953000, 0.5341018000, 0.5784712000, 0.6862471000, 1.0090285000", \ - "0.6737084000, 0.6773245000, 0.6867905000, 0.7077598000, 0.7523114000, 0.8600742000, 1.1822439000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.3938176000, 0.3979815000, 0.4089842000, 0.4359905000, 0.5081946000, 0.7313305000, 1.4469935000", \ - "0.3985638000, 0.4027174000, 0.4137571000, 0.4407217000, 0.5130802000, 0.7360188000, 1.4500537000", \ - "0.4113036000, 0.4154573000, 0.4264978000, 0.4534667000, 0.5256150000, 0.7488579000, 1.4631200000", \ - "0.4423017000, 0.4464568000, 0.4574902000, 0.4844197000, 0.5566434000, 0.7793085000, 1.4936833000", \ - "0.5066263000, 0.5108446000, 0.5218170000, 0.5488326000, 0.6210936000, 0.8441906000, 1.5592300000", \ - "0.6101438000, 0.6143247000, 0.6253108000, 0.6523088000, 0.7246209000, 0.9476806000, 1.6624911000", \ - "0.7695733000, 0.7737269000, 0.7847403000, 0.8116889000, 0.8838462000, 1.1066664000, 1.8191381000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0236802000, 0.0262856000, 0.0319337000, 0.0466434000, 0.0861516000, 0.2125107000, 0.6446006000", \ - "0.0238137000, 0.0262257000, 0.0321271000, 0.0466686000, 0.0868753000, 0.2122790000, 0.6382224000", \ - "0.0237133000, 0.0262425000, 0.0319204000, 0.0468562000, 0.0866800000, 0.2123461000, 0.6435811000", \ - "0.0237185000, 0.0260561000, 0.0319541000, 0.0467320000, 0.0871004000, 0.2121092000, 0.6467464000", \ - "0.0238740000, 0.0260908000, 0.0321866000, 0.0464530000, 0.0866458000, 0.2125797000, 0.6441970000", \ - "0.0237824000, 0.0263419000, 0.0320389000, 0.0464750000, 0.0867562000, 0.2123960000, 0.6399326000", \ - "0.0240949000, 0.0263214000, 0.0321447000, 0.0469708000, 0.0871421000, 0.2123124000, 0.6373966000"); - } - related_pin : "GATE_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016043400, 0.0051478000, 0.0165176000, 0.0529997000, 0.1700590000, 0.5456640000"); - values("0.0249560000, 0.0280533000, 0.0371257000, 0.0649335000, 0.1594597000, 0.4754160000, 1.4998961000", \ - "0.0249597000, 0.0280547000, 0.0370689000, 0.0649835000, 0.1592205000, 0.4752670000, 1.5010519000", \ - "0.0249598000, 0.0280582000, 0.0370719000, 0.0650073000, 0.1591183000, 0.4757317000, 1.5029058000", \ - "0.0249790000, 0.0280602000, 0.0370980000, 0.0649765000, 0.1594760000, 0.4763756000, 1.4994961000", \ - "0.0250131000, 0.0279654000, 0.0370123000, 0.0649786000, 0.1594407000, 0.4758091000, 1.4961533000", \ - "0.0249781000, 0.0280055000, 0.0371458000, 0.0648284000, 0.1592569000, 0.4745074000, 1.4959873000", \ - "0.0249149000, 0.0280026000, 0.0370754000, 0.0648963000, 0.1590891000, 0.4742852000, 1.5008801000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlxtp_1") { - leakage_power () { - value : 0.0085396000; - when : "D&GATE&Q"; - } - leakage_power () { - value : 0.0071637000; - when : "!D&!GATE&!Q"; - } - leakage_power () { - value : 0.0072605000; - when : "!D&GATE&!Q"; - } - leakage_power () { - value : 0.0084088000; - when : "D&!GATE&Q"; - } - leakage_power () { - value : 0.0086226000; - when : "D&!GATE&!Q"; - } - leakage_power () { - value : 0.0075741000; - when : "!D&!GATE&Q"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__dlxtp"; - cell_leakage_power : 0.0079282300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "GATE"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0017740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080639000, 0.0079551000, 0.0077045000, 0.0077816000, 0.0079595000, 0.0083695000, 0.0093146000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024834000, 0.0023809000, 0.0021447000, 0.0022073000, 0.0023516000, 0.0026843000, 0.0034509000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018500000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0374004000, 0.1966940000, 0.3655579000", \ - "-0.136541700, 0.0227520000, 0.1879538000", \ - "-0.312729800, -0.154656900, 0.0068828000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1948711000, 0.2797018000, 0.3118470000", \ - "0.1063783000, 0.1899883000, 0.2196921000", \ - "0.0473776000, 0.1273255000, 0.1558086000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.026076200, -0.186590500, -0.356675100", \ - "0.1478659000, -0.012648400, -0.179071000", \ - "0.3264954000, 0.1659811000, 0.0020000000"); - } - related_pin : "GATE"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.183546900, -0.269598300, -0.302964200", \ - "-0.085288400, -0.170119100, -0.202264300", \ - "0.0030091000, -0.084263000, -0.116408200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - capacitance : 0.0017510000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172155000, 0.0171230000, 0.0169098000, 0.0169665000, 0.0170973000, 0.0173986000, 0.0180935000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0099572000, 0.0098677000, 0.0096615000, 0.0096962000, 0.0097764000, 0.0099612000, 0.0103871000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018220000; - timing () { - related_output_pin : "Q"; - related_pin : "GATE"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1774742000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0183104000, 0.0173204000, 0.0145355000, 0.0060315000, -0.017259200, -0.078515500, -0.238812100", \ - "0.0182935000, 0.0173058000, 0.0144998000, 0.0060216000, -0.017265000, -0.078526000, -0.238838700", \ - "0.0182911000, 0.0173135000, 0.0144894000, 0.0060097000, -0.017288700, -0.078539000, -0.238852200", \ - "0.0178333000, 0.0168519000, 0.0140728000, 0.0055663000, -0.017721000, -0.078980400, -0.239284500", \ - "0.0175656000, 0.0165844000, 0.0137815000, 0.0053022000, -0.018000300, -0.079251900, -0.239564200", \ - "0.0187960000, 0.0175690000, 0.0142670000, 0.0053636000, -0.017980100, -0.079242300, -0.239535900", \ - "0.0193985000, 0.0181606000, 0.0148619000, 0.0060149000, -0.017382100, -0.078719300, -0.239092900"); - } - related_pin : "GATE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0188626000, 0.0204371000, 0.0242971000, 0.0335155000, 0.0566476000, 0.1169270000, 0.2759341000", \ - "0.0188355000, 0.0204045000, 0.0242773000, 0.0335375000, 0.0566228000, 0.1170107000, 0.2757732000", \ - "0.0188117000, 0.0203877000, 0.0242426000, 0.0334482000, 0.0566068000, 0.1170340000, 0.2754547000", \ - "0.0182919000, 0.0198706000, 0.0237319000, 0.0329958000, 0.0560580000, 0.1170069000, 0.2763332000", \ - "0.0179709000, 0.0195765000, 0.0234320000, 0.0326462000, 0.0559423000, 0.1162104000, 0.2748467000", \ - "0.0183152000, 0.0196281000, 0.0233430000, 0.0326070000, 0.0556951000, 0.1159098000, 0.2748451000", \ - "0.0195202000, 0.0208510000, 0.0243186000, 0.0332985000, 0.0562276000, 0.1168596000, 0.2761521000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0185126000, 0.0175513000, 0.0147481000, 0.0062653000, -0.017050300, -0.078317200, -0.238641700", \ - "0.0184031000, 0.0174564000, 0.0146528000, 0.0061644000, -0.017146600, -0.078420200, -0.238732200", \ - "0.0185163000, 0.0175529000, 0.0147499000, 0.0062656000, -0.017050000, -0.078319200, -0.238637600", \ - "0.0183578000, 0.0174091000, 0.0146031000, 0.0061159000, -0.017197000, -0.078466900, -0.238748200", \ - "0.0182609000, 0.0173047000, 0.0145025000, 0.0060187000, -0.017291600, -0.078560500, -0.238880000", \ - "0.0189475000, 0.0177286000, 0.0144036000, 0.0057111000, -0.017474800, -0.078723400, -0.239033500", \ - "0.0192833000, 0.0180623000, 0.0147728000, 0.0059159000, -0.017482800, -0.078574700, -0.238879700"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0201166000, 0.0217292000, 0.0255888000, 0.0347368000, 0.0579109000, 0.1186210000, 0.2777453000", \ - "0.0200823000, 0.0217062000, 0.0255693000, 0.0347337000, 0.0578741000, 0.1183976000, 0.2777190000", \ - "0.0201994000, 0.0217671000, 0.0256454000, 0.0347965000, 0.0579243000, 0.1188119000, 0.2784466000", \ - "0.0198358000, 0.0213727000, 0.0252218000, 0.0344692000, 0.0576597000, 0.1178161000, 0.2770193000", \ - "0.0196763000, 0.0212096000, 0.0250608000, 0.0342970000, 0.0574717000, 0.1176491000, 0.2763497000", \ - "0.0202174000, 0.0215458000, 0.0250561000, 0.0343001000, 0.0573047000, 0.1176728000, 0.2764661000", \ - "0.0209445000, 0.0222777000, 0.0257795000, 0.0347846000, 0.0578467000, 0.1185777000, 0.2758290000"); - } - } - max_capacitance : 0.1602270000; - max_transition : 1.4998690000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.1956779000, 0.2007484000, 0.2114909000, 0.2337785000, 0.2838228000, 0.4096937000, 0.7398072000", \ - "0.2006464000, 0.2057362000, 0.2164471000, 0.2387434000, 0.2888077000, 0.4149915000, 0.7453025000", \ - "0.2138190000, 0.2188893000, 0.2296347000, 0.2519184000, 0.3019593000, 0.4278740000, 0.7573207000", \ - "0.2450352000, 0.2501259000, 0.2608260000, 0.2831257000, 0.3332336000, 0.4593674000, 0.7895880000", \ - "0.3020378000, 0.3071162000, 0.3178570000, 0.3401388000, 0.3902163000, 0.5162122000, 0.8455597000", \ - "0.3909980000, 0.3960919000, 0.4068383000, 0.4291133000, 0.4792041000, 0.6051093000, 0.9343891000", \ - "0.5311448000, 0.5362405000, 0.5469755000, 0.5693151000, 0.6193808000, 0.7454488000, 1.0749442000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.2897848000, 0.2965617000, 0.3119340000, 0.3486242000, 0.4424752000, 0.6871566000, 1.3282956000", \ - "0.2944256000, 0.3011474000, 0.3165267000, 0.3532405000, 0.4470815000, 0.6918489000, 1.3309537000", \ - "0.3056690000, 0.3124450000, 0.3277803000, 0.3644517000, 0.4586222000, 0.7028413000, 1.3467548000", \ - "0.3263381000, 0.3328653000, 0.3483047000, 0.3849935000, 0.4791482000, 0.7233187000, 1.3641688000", \ - "0.3538375000, 0.3604514000, 0.3758217000, 0.4126217000, 0.5065501000, 0.7512085000, 1.3913161000", \ - "0.3848257000, 0.3915999000, 0.4069716000, 0.4436796000, 0.5375113000, 0.7823333000, 1.4229965000", \ - "0.4078935000, 0.4146049000, 0.4300053000, 0.4667164000, 0.5605648000, 0.8052757000, 1.4441415000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0163669000, 0.0205163000, 0.0299403000, 0.0526661000, 0.1130568000, 0.2786029000, 0.7238921000", \ - "0.0164261000, 0.0204367000, 0.0298988000, 0.0527299000, 0.1132432000, 0.2800721000, 0.7150719000", \ - "0.0163518000, 0.0204845000, 0.0299487000, 0.0526991000, 0.1131724000, 0.2795148000, 0.7188002000", \ - "0.0164486000, 0.0204429000, 0.0298311000, 0.0526271000, 0.1129427000, 0.2796830000, 0.7225254000", \ - "0.0164574000, 0.0204658000, 0.0299609000, 0.0527480000, 0.1133477000, 0.2795651000, 0.7187517000", \ - "0.0164329000, 0.0205113000, 0.0298189000, 0.0524697000, 0.1129583000, 0.2785544000, 0.7172974000", \ - "0.0165086000, 0.0205802000, 0.0299436000, 0.0526931000, 0.1131890000, 0.2776306000, 0.7140631000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0237742000, 0.0300597000, 0.0476671000, 0.0968298000, 0.2290845000, 0.5782642000, 1.4933628000", \ - "0.0236662000, 0.0300988000, 0.0476645000, 0.0967314000, 0.2294016000, 0.5767804000, 1.4963778000", \ - "0.0236807000, 0.0300969000, 0.0475886000, 0.0967016000, 0.2291797000, 0.5786722000, 1.4998689000", \ - "0.0235621000, 0.0302721000, 0.0476392000, 0.0966654000, 0.2291773000, 0.5773542000, 1.4981708000", \ - "0.0236265000, 0.0302641000, 0.0476282000, 0.0968710000, 0.2293573000, 0.5767912000, 1.4911320000", \ - "0.0236926000, 0.0300823000, 0.0475654000, 0.0967778000, 0.2285692000, 0.5776814000, 1.4974849000", \ - "0.0237280000, 0.0301534000, 0.0476384000, 0.0968764000, 0.2293897000, 0.5780705000, 1.4893545000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.2408861000, 0.2459875000, 0.2567938000, 0.2791576000, 0.3293162000, 0.4553846000, 0.7848088000", \ - "0.2454936000, 0.2505956000, 0.2614130000, 0.2837635000, 0.3338624000, 0.4599291000, 0.7907395000", \ - "0.2566185000, 0.2617138000, 0.2725135000, 0.2948354000, 0.3449692000, 0.4710901000, 0.8004751000", \ - "0.2808759000, 0.2859778000, 0.2967943000, 0.3191515000, 0.3692519000, 0.4953314000, 0.8261387000", \ - "0.3188427000, 0.3239643000, 0.3347380000, 0.3571037000, 0.4072429000, 0.5332983000, 0.8632153000", \ - "0.3702233000, 0.3753315000, 0.3861552000, 0.4085036000, 0.4586399000, 0.5845420000, 0.9140617000", \ - "0.4261492000, 0.4312617000, 0.4420564000, 0.4644319000, 0.5145670000, 0.6407230000, 0.9713635000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.2727443000, 0.2795717000, 0.2950170000, 0.3318136000, 0.4256409000, 0.6704344000, 1.3113387000", \ - "0.2773359000, 0.2841327000, 0.2995512000, 0.3364017000, 0.4302363000, 0.6749892000, 1.3143661000", \ - "0.2881232000, 0.2949556000, 0.3103703000, 0.3470869000, 0.4412568000, 0.6855770000, 1.3266492000", \ - "0.3119019000, 0.3187079000, 0.3341485000, 0.3710149000, 0.4648588000, 0.7090865000, 1.3530574000", \ - "0.3513700000, 0.3581870000, 0.3736341000, 0.4104507000, 0.5045135000, 0.7488073000, 1.3896402000", \ - "0.4060039000, 0.4128247000, 0.4282782000, 0.4650089000, 0.5588366000, 0.8036784000, 1.4433407000", \ - "0.4740605000, 0.4808421000, 0.4963239000, 0.5331252000, 0.6271225000, 0.8713793000, 1.5111470000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0167519000, 0.0207019000, 0.0300609000, 0.0526324000, 0.1135996000, 0.2801282000, 0.7240286000", \ - "0.0167541000, 0.0207384000, 0.0301395000, 0.0527942000, 0.1133371000, 0.2787838000, 0.7157553000", \ - "0.0166965000, 0.0206831000, 0.0301291000, 0.0529146000, 0.1135331000, 0.2786270000, 0.7239515000", \ - "0.0166762000, 0.0207455000, 0.0301108000, 0.0528059000, 0.1133309000, 0.2787705000, 0.7224172000", \ - "0.0166746000, 0.0206166000, 0.0300592000, 0.0528609000, 0.1134833000, 0.2783640000, 0.7239425000", \ - "0.0166381000, 0.0206598000, 0.0301537000, 0.0527273000, 0.1131373000, 0.2790785000, 0.7172305000", \ - "0.0168751000, 0.0205232000, 0.0300435000, 0.0527510000, 0.1131482000, 0.2783725000, 0.7127663000"); - } - related_pin : "GATE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0234764000, 0.0300381000, 0.0477196000, 0.0970673000, 0.2293570000, 0.5781378000, 1.4920603000", \ - "0.0234431000, 0.0300737000, 0.0476937000, 0.0968738000, 0.2293269000, 0.5771967000, 1.4966632000", \ - "0.0234843000, 0.0301266000, 0.0477406000, 0.0967641000, 0.2290958000, 0.5779417000, 1.4918156000", \ - "0.0235058000, 0.0300676000, 0.0477858000, 0.0966788000, 0.2289943000, 0.5784267000, 1.4977383000", \ - "0.0235220000, 0.0300372000, 0.0477103000, 0.0969389000, 0.2289846000, 0.5770432000, 1.4975939000", \ - "0.0235514000, 0.0301143000, 0.0477436000, 0.0968273000, 0.2293491000, 0.5776321000, 1.4963948000", \ - "0.0235126000, 0.0300728000, 0.0477353000, 0.0969363000, 0.2293026000, 0.5775836000, 1.4951985000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__dlygate4sd1_1") { - leakage_power () { - value : 0.0027621000; - when : "A"; - } - leakage_power () { - value : 0.0088226000; - when : "!A"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0057923300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015690000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017210000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0196266000, 0.0185267000, 0.0155787000, 0.0070945000, -0.016126200, -0.077128400, -0.236492200", \ - "0.0194133000, 0.0183201000, 0.0153729000, 0.0068613000, -0.016315500, -0.077332600, -0.236711700", \ - "0.0191962000, 0.0181154000, 0.0151698000, 0.0066725000, -0.016545600, -0.077540600, -0.236926700", \ - "0.0190680000, 0.0179413000, 0.0150008000, 0.0065164000, -0.016708400, -0.077691700, -0.237077600", \ - "0.0189480000, 0.0178404000, 0.0148750000, 0.0063860000, -0.016811700, -0.077789400, -0.237137800", \ - "0.0194656000, 0.0182090000, 0.0148490000, 0.0064959000, -0.016674500, -0.077639700, -0.237016500", \ - "0.0204923000, 0.0192690000, 0.0159665000, 0.0071232000, -0.016115400, -0.076897800, -0.236278700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0169028000, 0.0183115000, 0.0218160000, 0.0307253000, 0.0537864000, 0.1141206000, 0.2719509000", \ - "0.0167590000, 0.0181631000, 0.0216654000, 0.0306179000, 0.0538399000, 0.1139684000, 0.2715595000", \ - "0.0165412000, 0.0179431000, 0.0214575000, 0.0303696000, 0.0534369000, 0.1136813000, 0.2713144000", \ - "0.0162820000, 0.0176882000, 0.0211753000, 0.0300797000, 0.0531643000, 0.1134136000, 0.2710481000", \ - "0.0161498000, 0.0175534000, 0.0210363000, 0.0299677000, 0.0530251000, 0.1133954000, 0.2702661000", \ - "0.0164674000, 0.0178293000, 0.0213185000, 0.0300973000, 0.0532536000, 0.1132079000, 0.2708985000", \ - "0.0170806000, 0.0184913000, 0.0220057000, 0.0309956000, 0.0542347000, 0.1148125000, 0.2718985000"); - } - } - max_capacitance : 0.1593120000; - max_transition : 1.5053790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1975640000, 0.2036230000, 0.2160659000, 0.2408796000, 0.2936845000, 0.4216362000, 0.7544734000", \ - "0.2017308000, 0.2077924000, 0.2202663000, 0.2450910000, 0.2978939000, 0.4259046000, 0.7589463000", \ - "0.2141771000, 0.2202373000, 0.2327601000, 0.2575011000, 0.3102507000, 0.4382904000, 0.7714805000", \ - "0.2457716000, 0.2517561000, 0.2643128000, 0.2890808000, 0.3418432000, 0.4699103000, 0.8029942000", \ - "0.3093508000, 0.3154174000, 0.3278710000, 0.3527058000, 0.4054938000, 0.5335387000, 0.8668830000", \ - "0.4106152000, 0.4166569000, 0.4291519000, 0.4539510000, 0.5067227000, 0.6348027000, 0.9683863000", \ - "0.5704195000, 0.5764615000, 0.5889654000, 0.6138171000, 0.6666743000, 0.7948370000, 1.1279276000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1589621000, 0.1654411000, 0.1805831000, 0.2174793000, 0.3118832000, 0.5581778000, 1.2034234000", \ - "0.1634761000, 0.1699312000, 0.1850367000, 0.2219396000, 0.3162964000, 0.5627656000, 1.2064435000", \ - "0.1742990000, 0.1807922000, 0.1959269000, 0.2328669000, 0.3271722000, 0.5736568000, 1.2177241000", \ - "0.1940813000, 0.2005187000, 0.2156217000, 0.2525053000, 0.3467035000, 0.5932435000, 1.2365737000", \ - "0.2206460000, 0.2270897000, 0.2421461000, 0.2790035000, 0.3734385000, 0.6188841000, 1.2736469000", \ - "0.2511319000, 0.2576445000, 0.2727642000, 0.3096670000, 0.4041897000, 0.6494056000, 1.2910668000", \ - "0.2747205000, 0.2812165000, 0.2963713000, 0.3333110000, 0.4277879000, 0.6749628000, 1.3144654000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0207538000, 0.0251910000, 0.0354082000, 0.0588147000, 0.1188243000, 0.2850497000, 0.7288049000", \ - "0.0209912000, 0.0252981000, 0.0355108000, 0.0588961000, 0.1191241000, 0.2851272000, 0.7285680000", \ - "0.0210231000, 0.0253319000, 0.0354494000, 0.0588185000, 0.1193208000, 0.2846774000, 0.7276014000", \ - "0.0210242000, 0.0252539000, 0.0354058000, 0.0588468000, 0.1189867000, 0.2847199000, 0.7311814000", \ - "0.0211358000, 0.0254736000, 0.0352722000, 0.0587592000, 0.1188303000, 0.2863986000, 0.7293885000", \ - "0.0210230000, 0.0253110000, 0.0355105000, 0.0588972000, 0.1186565000, 0.2844580000, 0.7261569000", \ - "0.0210873000, 0.0253879000, 0.0356291000, 0.0589755000, 0.1191412000, 0.2849267000, 0.7225899000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0212820000, 0.0282721000, 0.0468836000, 0.0971184000, 0.2311503000, 0.5823602000, 1.5012577000", \ - "0.0213057000, 0.0282207000, 0.0468546000, 0.0972360000, 0.2312583000, 0.5839553000, 1.5046832000", \ - "0.0213332000, 0.0282669000, 0.0468953000, 0.0971952000, 0.2311193000, 0.5823459000, 1.5032714000", \ - "0.0213125000, 0.0282232000, 0.0468914000, 0.0972567000, 0.2311004000, 0.5824551000, 1.5046062000", \ - "0.0213302000, 0.0283447000, 0.0468662000, 0.0971269000, 0.2310736000, 0.5834025000, 1.5053794000", \ - "0.0214188000, 0.0283188000, 0.0469277000, 0.0970247000, 0.2307983000, 0.5807229000, 1.5012562000", \ - "0.0215041000, 0.0284405000, 0.0469380000, 0.0971372000, 0.2305759000, 0.5834145000, 1.4974206000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__dlygate4sd2_1") { - leakage_power () { - value : 0.0022656000; - when : "A"; - } - leakage_power () { - value : 0.0082558000; - when : "!A"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0052606790; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015980000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017540000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0204859000, 0.0194086000, 0.0164434000, 0.0079784000, -0.015199300, -0.076248200, -0.235590800", \ - "0.0202610000, 0.0191863000, 0.0162367000, 0.0077618000, -0.015434100, -0.076438500, -0.235781900", \ - "0.0200595000, 0.0189822000, 0.0160103000, 0.0075467000, -0.015643500, -0.076635400, -0.236023300", \ - "0.0198959000, 0.0187899000, 0.0158766000, 0.0074196000, -0.015796800, -0.076765900, -0.236178600", \ - "0.0198878000, 0.0188019000, 0.0158745000, 0.0074166000, -0.015788900, -0.076742700, -0.236162900", \ - "0.0199218000, 0.0186465000, 0.0156891000, 0.0073663000, -0.015798200, -0.076798800, -0.236157400", \ - "0.0213193000, 0.0200873000, 0.0167918000, 0.0079843000, -0.015300700, -0.076101000, -0.235469600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("0.0175555000, 0.0189614000, 0.0225274000, 0.0314743000, 0.0546859000, 0.1146796000, 0.2724435000", \ - "0.0174585000, 0.0188725000, 0.0224055000, 0.0313055000, 0.0543266000, 0.1151867000, 0.2722643000", \ - "0.0172336000, 0.0186446000, 0.0221431000, 0.0310811000, 0.0541397000, 0.1148983000, 0.2718647000", \ - "0.0169659000, 0.0183645000, 0.0218879000, 0.0308280000, 0.0538387000, 0.1140078000, 0.2719719000", \ - "0.0167844000, 0.0181868000, 0.0217143000, 0.0306488000, 0.0538912000, 0.1144713000, 0.2707501000", \ - "0.0171058000, 0.0184767000, 0.0219347000, 0.0307143000, 0.0538505000, 0.1143970000, 0.2717263000", \ - "0.0177544000, 0.0191417000, 0.0225800000, 0.0315749000, 0.0547938000, 0.1153007000, 0.2725011000"); - } - } - max_capacitance : 0.1593120000; - max_transition : 1.5059800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.2152495000, 0.2212911000, 0.2338365000, 0.2589552000, 0.3122380000, 0.4404295000, 0.7738766000", \ - "0.2195914000, 0.2256496000, 0.2381782000, 0.2632833000, 0.3165685000, 0.4447822000, 0.7781494000", \ - "0.2319021000, 0.2379378000, 0.2504831000, 0.2756803000, 0.3288854000, 0.4570007000, 0.7909802000", \ - "0.2636303000, 0.2696133000, 0.2822783000, 0.3073516000, 0.3605600000, 0.4889746000, 0.8220951000", \ - "0.3287440000, 0.3347907000, 0.3473583000, 0.3724614000, 0.4257518000, 0.5540960000, 0.8881413000", \ - "0.4344167000, 0.4404476000, 0.4530278000, 0.4781765000, 0.5314449000, 0.6598183000, 0.9927325000", \ - "0.6003781000, 0.6064377000, 0.6190925000, 0.6441942000, 0.6974902000, 0.8258068000, 1.1588015000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.1749470000, 0.1815183000, 0.1968922000, 0.2340600000, 0.3281204000, 0.5750993000, 1.2171829000", \ - "0.1796917000, 0.1862441000, 0.2015718000, 0.2384901000, 0.3328584000, 0.5782871000, 1.2183198000", \ - "0.1905885000, 0.1971423000, 0.2124090000, 0.2494167000, 0.3438344000, 0.5892762000, 1.2318024000", \ - "0.2108745000, 0.2174671000, 0.2327781000, 0.2698591000, 0.3642549000, 0.6092942000, 1.2542194000", \ - "0.2388776000, 0.2454383000, 0.2608154000, 0.2979162000, 0.3922046000, 0.6382360000, 1.2862547000", \ - "0.2721395000, 0.2787306000, 0.2940323000, 0.3311347000, 0.4255182000, 0.6705600000, 1.3112452000", \ - "0.2995326000, 0.3061119000, 0.3213728000, 0.3584234000, 0.4527978000, 0.6979580000, 1.3377858000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0220199000, 0.0262826000, 0.0366743000, 0.0601084000, 0.1204474000, 0.2854923000, 0.7289533000", \ - "0.0220844000, 0.0264184000, 0.0367269000, 0.0602079000, 0.1205168000, 0.2858378000, 0.7298408000", \ - "0.0219990000, 0.0262416000, 0.0365675000, 0.0601559000, 0.1202734000, 0.2861120000, 0.7318724000", \ - "0.0221361000, 0.0264090000, 0.0366019000, 0.0601782000, 0.1202041000, 0.2862283000, 0.7315449000", \ - "0.0219648000, 0.0263899000, 0.0366237000, 0.0601578000, 0.1204027000, 0.2867083000, 0.7256618000", \ - "0.0221979000, 0.0264865000, 0.0367548000, 0.0602102000, 0.1199006000, 0.2874255000, 0.7299266000", \ - "0.0224624000, 0.0267515000, 0.0367882000, 0.0602294000, 0.1204153000, 0.2844630000, 0.7241014000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0230205000, 0.0299426000, 0.0483600000, 0.0982503000, 0.2318818000, 0.5838951000, 1.5054279000", \ - "0.0229701000, 0.0299132000, 0.0482889000, 0.0983947000, 0.2312173000, 0.5845116000, 1.4996351000", \ - "0.0229376000, 0.0299128000, 0.0484272000, 0.0983677000, 0.2313074000, 0.5840949000, 1.5017396000", \ - "0.0230028000, 0.0299738000, 0.0482744000, 0.0984013000, 0.2312977000, 0.5840550000, 1.5059803000", \ - "0.0229209000, 0.0299431000, 0.0484272000, 0.0982304000, 0.2318264000, 0.5832707000, 1.5046070000", \ - "0.0229663000, 0.0299381000, 0.0483284000, 0.0984081000, 0.2312788000, 0.5821855000, 1.5029099000", \ - "0.0230736000, 0.0300138000, 0.0484601000, 0.0984498000, 0.2313729000, 0.5851531000, 1.4959051000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__dlygate4sd3_1") { - leakage_power () { - value : 0.0013724000; - when : "A"; - } - leakage_power () { - value : 0.0069809000; - when : "!A"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__buf"; - cell_leakage_power : 0.0041766900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015580000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017230000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0265141000, 0.0253941000, 0.0225833000, 0.0147722000, -0.007251200, -0.066455200, -0.220913100", \ - "0.0263363000, 0.0252785000, 0.0224508000, 0.0146301000, -0.007446000, -0.066668800, -0.221118100", \ - "0.0261633000, 0.0250191000, 0.0222019000, 0.0143479000, -0.007711800, -0.066926300, -0.221355100", \ - "0.0259145000, 0.0247909000, 0.0219711000, 0.0141853000, -0.007883400, -0.067064000, -0.221540800", \ - "0.0257533000, 0.0246350000, 0.0218170000, 0.0139637000, -0.008082500, -0.067244700, -0.221714200", \ - "0.0256730000, 0.0245498000, 0.0217343000, 0.0139079000, -0.008139500, -0.067359900, -0.221773400", \ - "0.0271705000, 0.0258477000, 0.0225425000, 0.0141627000, -0.007704000, -0.066920200, -0.221353800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0235480000, 0.0250823000, 0.0290122000, 0.0383056000, 0.0611256000, 0.1195137000, 0.2718900000", \ - "0.0234867000, 0.0250197000, 0.0288938000, 0.0382572000, 0.0611103000, 0.1195033000, 0.2730485000", \ - "0.0232679000, 0.0247965000, 0.0287106000, 0.0381030000, 0.0608995000, 0.1193713000, 0.2715476000", \ - "0.0229159000, 0.0244511000, 0.0283240000, 0.0376809000, 0.0605431000, 0.1187215000, 0.2721341000", \ - "0.0225317000, 0.0240471000, 0.0279698000, 0.0373345000, 0.0601065000, 0.1185640000, 0.2706896000", \ - "0.0223610000, 0.0239102000, 0.0278439000, 0.0371986000, 0.0600441000, 0.1184572000, 0.2707780000", \ - "0.0244849000, 0.0257903000, 0.0292222000, 0.0379588000, 0.0604143000, 0.1188196000, 0.2725151000"); - } - } - max_capacitance : 0.1547340000; - max_transition : 1.4950670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.5120638000, 0.5214328000, 0.5404421000, 0.5753458000, 0.6416054000, 0.7772634000, 1.0992397000", \ - "0.5167138000, 0.5260317000, 0.5449337000, 0.5804400000, 0.6461230000, 0.7815158000, 1.1038167000", \ - "0.5283844000, 0.5377204000, 0.5566605000, 0.5920545000, 0.6575812000, 0.7931211000, 1.1151986000", \ - "0.5599264000, 0.5692888000, 0.5881649000, 0.6231063000, 0.6893898000, 0.8250352000, 1.1469636000", \ - "0.6316707000, 0.6410206000, 0.6600098000, 0.6953290000, 0.7609479000, 0.8967246000, 1.2186561000", \ - "0.7651026000, 0.7745045000, 0.7933595000, 0.8283246000, 0.8945671000, 1.0302003000, 1.3520610000", \ - "0.9800700000, 0.9894486000, 1.0082368000, 1.0436276000, 1.1095078000, 1.2449383000, 1.5677241000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.4998114000, 0.5089495000, 0.5285765000, 0.5701394000, 0.6668673000, 0.9095528000, 1.5405252000", \ - "0.5045179000, 0.5136551000, 0.5331524000, 0.5748917000, 0.6716904000, 0.9148460000, 1.5447300000", \ - "0.5140869000, 0.5233344000, 0.5430380000, 0.5846870000, 0.6816028000, 0.9245619000, 1.5526628000", \ - "0.5343100000, 0.5434748000, 0.5629217000, 0.6046893000, 0.7011746000, 0.9444749000, 1.5746626000", \ - "0.5680223000, 0.5771998000, 0.5968143000, 0.6385586000, 0.7351774000, 0.9786373000, 1.6067756000", \ - "0.6128227000, 0.6221012000, 0.6416894000, 0.6833976000, 0.7799209000, 1.0234245000, 1.6514372000", \ - "0.6625758000, 0.6718174000, 0.6914005000, 0.7330232000, 0.8295155000, 1.0724920000, 1.7018963000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0401866000, 0.0464831000, 0.0582036000, 0.0857656000, 0.1451656000, 0.2952143000, 0.7095290000", \ - "0.0401731000, 0.0461160000, 0.0585152000, 0.0845620000, 0.1448873000, 0.2955323000, 0.7093720000", \ - "0.0404615000, 0.0459131000, 0.0582647000, 0.0844327000, 0.1450376000, 0.2957212000, 0.7101850000", \ - "0.0400993000, 0.0460410000, 0.0582683000, 0.0856849000, 0.1451886000, 0.2952692000, 0.7097207000", \ - "0.0398749000, 0.0463918000, 0.0585918000, 0.0854098000, 0.1449278000, 0.2956000000, 0.7104890000", \ - "0.0401238000, 0.0461017000, 0.0583057000, 0.0856571000, 0.1451668000, 0.2952485000, 0.7106083000", \ - "0.0402755000, 0.0465253000, 0.0588243000, 0.0848232000, 0.1447223000, 0.2945902000, 0.7135590000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0339005000, 0.0416114000, 0.0603369000, 0.1083437000, 0.2384302000, 0.5834385000, 1.4948045000", \ - "0.0338978000, 0.0416949000, 0.0604202000, 0.1082148000, 0.2382069000, 0.5847182000, 1.4948558000", \ - "0.0340282000, 0.0418314000, 0.0604427000, 0.1084344000, 0.2384207000, 0.5846014000, 1.4950673000", \ - "0.0338772000, 0.0416616000, 0.0604859000, 0.1082537000, 0.2385101000, 0.5849667000, 1.4935420000", \ - "0.0340028000, 0.0415702000, 0.0603255000, 0.1084170000, 0.2385477000, 0.5840190000, 1.4949906000", \ - "0.0337610000, 0.0416220000, 0.0602685000, 0.1083308000, 0.2383853000, 0.5841642000, 1.4946913000", \ - "0.0338192000, 0.0416265000, 0.0602386000, 0.1084174000, 0.2384781000, 0.5840423000, 1.4949493000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__dlymetal6s2s_1") { - leakage_power () { - value : 0.0039634000; - when : "A"; - } - leakage_power () { - value : 0.0221486000; - when : "!A"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__delay"; - cell_leakage_power : 0.0130559700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015870000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017450000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0227967000, 0.0216154000, 0.0185082000, 0.0113676000, -0.007192300, -0.062791800, -0.219854800", \ - "0.0225526000, 0.0213585000, 0.0183511000, 0.0111618000, -0.007333900, -0.062972800, -0.220126500", \ - "0.0223415000, 0.0211389000, 0.0180833000, 0.0109703000, -0.007526500, -0.063127200, -0.220197300", \ - "0.0221718000, 0.0209570000, 0.0179188000, 0.0108072000, -0.007662300, -0.063246500, -0.220338100", \ - "0.0221866000, 0.0209688000, 0.0178738000, 0.0108054000, -0.007648200, -0.063208900, -0.220147700", \ - "0.0239434000, 0.0218952000, 0.0180985000, 0.0111793000, -0.007475000, -0.062997500, -0.220018100", \ - "0.0346077000, 0.0332650000, 0.0297809000, 0.0209497000, -0.002205800, -0.062357000, -0.219291800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0245532000, 0.0275902000, 0.0352916000, 0.0453377000, 0.0679937000, 0.1273694000, 0.2837428000", \ - "0.0244607000, 0.0274860000, 0.0351902000, 0.0452514000, 0.0679552000, 0.1274284000, 0.2830940000", \ - "0.0242914000, 0.0272968000, 0.0350162000, 0.0451205000, 0.0678570000, 0.1273641000, 0.2836305000", \ - "0.0240288000, 0.0270369000, 0.0347742000, 0.0449106000, 0.0676956000, 0.1271025000, 0.2823906000", \ - "0.0242645000, 0.0271493000, 0.0346213000, 0.0446373000, 0.0674572000, 0.1270723000, 0.2827507000", \ - "0.0317136000, 0.0329659000, 0.0363334000, 0.0448951000, 0.0675388000, 0.1274063000, 0.2829254000", \ - "0.0322945000, 0.0335497000, 0.0369339000, 0.0456086000, 0.0686802000, 0.1279898000, 0.2833513000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.4975510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1074305000, 0.1121353000, 0.1227985000, 0.1460886000, 0.1977196000, 0.3241674000, 0.6523267000", \ - "0.1116445000, 0.1163296000, 0.1271037000, 0.1502595000, 0.2019342000, 0.3284294000, 0.6565482000", \ - "0.1241329000, 0.1288987000, 0.1396688000, 0.1628491000, 0.2145869000, 0.3410700000, 0.6692005000", \ - "0.1555073000, 0.1602539000, 0.1710668000, 0.1944138000, 0.2461542000, 0.3726190000, 0.7006510000", \ - "0.2247781000, 0.2297963000, 0.2410453000, 0.2648469000, 0.3170116000, 0.4436313000, 0.7715758000", \ - "0.3378096000, 0.3440554000, 0.3577018000, 0.3849561000, 0.4405442000, 0.5675171000, 0.8957451000", \ - "0.5134434000, 0.5216019000, 0.5392612000, 0.5733319000, 0.6358057000, 0.7670795000, 1.0930602000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0673933000, 0.0731165000, 0.0874881000, 0.1235179000, 0.2166476000, 0.4590270000, 1.0908540000", \ - "0.0721506000, 0.0779050000, 0.0922897000, 0.1284633000, 0.2215011000, 0.4638620000, 1.0956347000", \ - "0.0834270000, 0.0891813000, 0.1035200000, 0.1398649000, 0.2331748000, 0.4757236000, 1.1075340000", \ - "0.1060557000, 0.1118344000, 0.1261720000, 0.1626130000, 0.2562252000, 0.4988319000, 1.1307173000", \ - "0.1378094000, 0.1438404000, 0.1585919000, 0.1953296000, 0.2888276000, 0.5316040000, 1.1634755000", \ - "0.1756747000, 0.1824627000, 0.1982358000, 0.2350728000, 0.3288009000, 0.5716803000, 1.2035439000", \ - "0.2034476000, 0.2124750000, 0.2323581000, 0.2715859000, 0.3648821000, 0.6070069000, 1.2389491000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0285679000, 0.0324684000, 0.0415939000, 0.0645467000, 0.1246193000, 0.2881799000, 0.7229929000", \ - "0.0285050000, 0.0322195000, 0.0415532000, 0.0645233000, 0.1247104000, 0.2881997000, 0.7229042000", \ - "0.0286412000, 0.0324364000, 0.0416850000, 0.0646316000, 0.1246380000, 0.2881076000, 0.7230639000", \ - "0.0285074000, 0.0323882000, 0.0414956000, 0.0644730000, 0.1249524000, 0.2881098000, 0.7229135000", \ - "0.0324594000, 0.0358646000, 0.0447283000, 0.0666698000, 0.1254326000, 0.2882074000, 0.7231412000", \ - "0.0439304000, 0.0475829000, 0.0561517000, 0.0769108000, 0.1329663000, 0.2917137000, 0.7232818000", \ - "0.0630725000, 0.0673684000, 0.0771331000, 0.0972677000, 0.1482355000, 0.2984300000, 0.7270182000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0353022000, 0.0431570000, 0.0630181000, 0.1158313000, 0.2508896000, 0.5947172000, 1.4968431000", \ - "0.0353043000, 0.0428679000, 0.0631153000, 0.1158661000, 0.2509039000, 0.5945577000, 1.4927058000", \ - "0.0353090000, 0.0429710000, 0.0631828000, 0.1158513000, 0.2509099000, 0.5944010000, 1.4957552000", \ - "0.0364855000, 0.0438138000, 0.0636376000, 0.1159503000, 0.2509060000, 0.5946988000, 1.4975515000", \ - "0.0399652000, 0.0470667000, 0.0658317000, 0.1173764000, 0.2515010000, 0.5947952000, 1.4943492000", \ - "0.0490645000, 0.0549955000, 0.0715071000, 0.1196066000, 0.2524411000, 0.5956403000, 1.4960153000", \ - "0.0675130000, 0.0728801000, 0.0872304000, 0.1293513000, 0.2544329000, 0.5963971000, 1.4952235000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__dlymetal6s4s_1") { - leakage_power () { - value : 0.0039628000; - when : "A"; - } - leakage_power () { - value : 0.0221486000; - when : "!A"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__delay"; - cell_leakage_power : 0.0130556700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015850000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017430000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0322729000, 0.0310861000, 0.0291067000, 0.0203729000, -0.002171500, -0.062084600, -0.218033600", \ - "0.0319202000, 0.0307183000, 0.0288570000, 0.0201399000, -0.002392900, -0.062313800, -0.218258500", \ - "0.0318430000, 0.0304958000, 0.0286558000, 0.0199487000, -0.002597300, -0.062508500, -0.218461600", \ - "0.0316338000, 0.0303167000, 0.0284698000, 0.0197627000, -0.002777500, -0.062697100, -0.218633500", \ - "0.0316100000, 0.0304108000, 0.0285213000, 0.0198053000, -0.002735500, -0.062637500, -0.218608300", \ - "0.0315955000, 0.0304445000, 0.0285145000, 0.0198067000, -0.002717300, -0.062619200, -0.218475900", \ - "0.0347304000, 0.0334284000, 0.0300966000, 0.0212448000, -0.001852900, -0.061735800, -0.217283100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0321556000, 0.0334724000, 0.0368045000, 0.0454433000, 0.0680868000, 0.1271905000, 0.2826211000", \ - "0.0320478000, 0.0333642000, 0.0366882000, 0.0453445000, 0.0679516000, 0.1270664000, 0.2824049000", \ - "0.0318517000, 0.0331577000, 0.0365347000, 0.0451682000, 0.0678412000, 0.1269191000, 0.2823058000", \ - "0.0315992000, 0.0329159000, 0.0362586000, 0.0449186000, 0.0675083000, 0.1265771000, 0.2820153000", \ - "0.0314266000, 0.0327405000, 0.0360897000, 0.0447387000, 0.0673747000, 0.1264100000, 0.2807891000", \ - "0.0318141000, 0.0331022000, 0.0364275000, 0.0449380000, 0.0675819000, 0.1267677000, 0.2809877000", \ - "0.0324081000, 0.0337066000, 0.0370677000, 0.0458195000, 0.0685875000, 0.1277750000, 0.2829238000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.5065280000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.2205764000, 0.2253766000, 0.2362749000, 0.2596477000, 0.3115954000, 0.4387352000, 0.7682066000", \ - "0.2247699000, 0.2295587000, 0.2404270000, 0.2638667000, 0.3158545000, 0.4430094000, 0.7725395000", \ - "0.2373775000, 0.2422240000, 0.2529879000, 0.2764322000, 0.3284073000, 0.4557129000, 0.7851143000", \ - "0.2685895000, 0.2733739000, 0.2842462000, 0.3077679000, 0.3596938000, 0.4868350000, 0.8163232000", \ - "0.3386622000, 0.3434102000, 0.3542826000, 0.3777149000, 0.4296969000, 0.5569549000, 0.8863730000", \ - "0.4545683000, 0.4593913000, 0.4702401000, 0.4935962000, 0.5455673000, 0.6728076000, 1.0023219000", \ - "0.6356477000, 0.6404262000, 0.6513037000, 0.6748065000, 0.7268789000, 0.8542351000, 1.1839493000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1451251000, 0.1508976000, 0.1653745000, 0.2018985000, 0.2951755000, 0.5377954000, 1.1698190000", \ - "0.1498851000, 0.1556666000, 0.1701410000, 0.2066650000, 0.2999386000, 0.5425541000, 1.1746168000", \ - "0.1611792000, 0.1669326000, 0.1815313000, 0.2178999000, 0.3111756000, 0.5538195000, 1.1858898000", \ - "0.1839304000, 0.1896979000, 0.2041919000, 0.2406925000, 0.3339804000, 0.5765805000, 1.2086798000", \ - "0.2159076000, 0.2217508000, 0.2361707000, 0.2726380000, 0.3661311000, 0.6088052000, 1.2408696000", \ - "0.2548854000, 0.2606899000, 0.2751213000, 0.3117093000, 0.4051266000, 0.6477818000, 1.2799061000", \ - "0.2863518000, 0.2921891000, 0.3067756000, 0.3432640000, 0.4367119000, 0.6796074000, 1.3117887000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0291176000, 0.0328726000, 0.0421663000, 0.0651042000, 0.1257845000, 0.2902639000, 0.7272666000", \ - "0.0289586000, 0.0327521000, 0.0422752000, 0.0652477000, 0.1258213000, 0.2902859000, 0.7271781000", \ - "0.0291171000, 0.0326919000, 0.0421027000, 0.0651453000, 0.1261489000, 0.2904350000, 0.7271937000", \ - "0.0291354000, 0.0329549000, 0.0422519000, 0.0651993000, 0.1257781000, 0.2902806000, 0.7272435000", \ - "0.0288749000, 0.0327328000, 0.0422901000, 0.0652728000, 0.1261704000, 0.2903779000, 0.7271773000", \ - "0.0290106000, 0.0327976000, 0.0420172000, 0.0653629000, 0.1259384000, 0.2902988000, 0.7273321000", \ - "0.0291392000, 0.0329566000, 0.0422209000, 0.0653753000, 0.1262383000, 0.2903769000, 0.7275030000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0362079000, 0.0438822000, 0.0640930000, 0.1168229000, 0.2517709000, 0.5960594000, 1.4977269000", \ - "0.0361818000, 0.0438805000, 0.0640925000, 0.1168224000, 0.2517702000, 0.5967038000, 1.4954201000", \ - "0.0362257000, 0.0438014000, 0.0640556000, 0.1168344000, 0.2517759000, 0.5963061000, 1.4956143000", \ - "0.0362103000, 0.0438864000, 0.0640926000, 0.1168194000, 0.2517663000, 0.5966894000, 1.4965789000", \ - "0.0363262000, 0.0439738000, 0.0639348000, 0.1167862000, 0.2517919000, 0.5964260000, 1.5019060000", \ - "0.0362704000, 0.0441673000, 0.0639027000, 0.1168257000, 0.2517726000, 0.5962740000, 1.5065278000", \ - "0.0366430000, 0.0440724000, 0.0640806000, 0.1168372000, 0.2518062000, 0.5964818000, 1.4969370000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__dlymetal6s6s_1") { - leakage_power () { - value : 0.0039634000; - when : "A"; - } - leakage_power () { - value : 0.0221486000; - when : "!A"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__delay"; - cell_leakage_power : 0.0130559900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015860000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017440000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0338044000, 0.0326987000, 0.0297519000, 0.0212274000, -0.002103300, -0.063434700, -0.223814800", \ - "0.0335597000, 0.0324641000, 0.0295012000, 0.0209626000, -0.002350900, -0.063686600, -0.224059100", \ - "0.0333736000, 0.0322677000, 0.0293215000, 0.0207973000, -0.002533100, -0.063864300, -0.224243900", \ - "0.0331972000, 0.0320695000, 0.0291282000, 0.0206110000, -0.002722400, -0.064049700, -0.224451200", \ - "0.0332180000, 0.0321222000, 0.0291594000, 0.0206208000, -0.002691300, -0.064023700, -0.224399900", \ - "0.0332363000, 0.0321152000, 0.0291818000, 0.0206498000, -0.002682300, -0.064007000, -0.224380600", \ - "0.0348029000, 0.0335895000, 0.0302791000, 0.0214231000, -0.002015600, -0.063165300, -0.223547800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506210, 0.0234142800, 0.0612503600, 0.1602272000"); - values("0.0322433000, 0.0336354000, 0.0371159000, 0.0460875000, 0.0691932000, 0.1303346000, 0.2868806000", \ - "0.0321464000, 0.0335301000, 0.0370233000, 0.0459891000, 0.0690568000, 0.1302661000, 0.2879005000", \ - "0.0319489000, 0.0333102000, 0.0368263000, 0.0457770000, 0.0689051000, 0.1299788000, 0.2885186000", \ - "0.0316979000, 0.0330603000, 0.0365747000, 0.0455399000, 0.0686088000, 0.1298154000, 0.2864001000", \ - "0.0315197000, 0.0329131000, 0.0363927000, 0.0453357000, 0.0686728000, 0.1296108000, 0.2893030000", \ - "0.0318587000, 0.0332339000, 0.0367333000, 0.0456264000, 0.0686535000, 0.1297032000, 0.2881844000", \ - "0.0324644000, 0.0338483000, 0.0373249000, 0.0463565000, 0.0695832000, 0.1304081000, 0.2885130000"); - } - } - max_capacitance : 0.1602270000; - max_transition : 1.5127490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.3239534000, 0.3299171000, 0.3424128000, 0.3670781000, 0.4199639000, 0.5486604000, 0.8842942000", \ - "0.3281740000, 0.3341485000, 0.3465895000, 0.3712988000, 0.4242388000, 0.5529802000, 0.8884307000", \ - "0.3407476000, 0.3467098000, 0.3592142000, 0.3838729000, 0.4367576000, 0.5654540000, 0.9010883000", \ - "0.3720951000, 0.3780036000, 0.3903973000, 0.4151099000, 0.4679931000, 0.5967957000, 0.9321860000", \ - "0.4420370000, 0.4480120000, 0.4604483000, 0.4851621000, 0.5381074000, 0.6668485000, 1.0022976000", \ - "0.5580114000, 0.5639447000, 0.5763757000, 0.6011114000, 0.6540031000, 0.7827745000, 1.1170177000", \ - "0.7392536000, 0.7452166000, 0.7576632000, 0.7822634000, 0.8351304000, 0.9640420000, 1.2980963000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.2123933000, 0.2187296000, 0.2335888000, 0.2702598000, 0.3644496000, 0.6104905000, 1.2560418000", \ - "0.2171761000, 0.2234805000, 0.2383707000, 0.2750213000, 0.3690342000, 0.6166856000, 1.2592117000", \ - "0.2284732000, 0.2347208000, 0.2496694000, 0.2864464000, 0.3808765000, 0.6279693000, 1.2754162000", \ - "0.2512216000, 0.2574801000, 0.2724200000, 0.3090441000, 0.4030885000, 0.6506445000, 1.2943446000", \ - "0.2832029000, 0.2895288000, 0.3043744000, 0.3411106000, 0.4355856000, 0.6822065000, 1.3294817000", \ - "0.3222146000, 0.3285200000, 0.3434246000, 0.3801475000, 0.4745262000, 0.7204731000, 1.3689457000", \ - "0.3537354000, 0.3600633000, 0.3748854000, 0.4115098000, 0.5056719000, 0.7524138000, 1.3949354000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0214989000, 0.0258528000, 0.0356918000, 0.0591611000, 0.1200588000, 0.2867535000, 0.7301689000", \ - "0.0214610000, 0.0257093000, 0.0357515000, 0.0592633000, 0.1198361000, 0.2864240000, 0.7305596000", \ - "0.0215082000, 0.0258814000, 0.0356785000, 0.0591582000, 0.1200550000, 0.2867556000, 0.7301478000", \ - "0.0214097000, 0.0256037000, 0.0357151000, 0.0591885000, 0.1197043000, 0.2867529000, 0.7362420000", \ - "0.0214495000, 0.0256944000, 0.0357551000, 0.0592694000, 0.1198917000, 0.2865374000, 0.7306607000", \ - "0.0214418000, 0.0254790000, 0.0354382000, 0.0592438000, 0.1197509000, 0.2866460000, 0.7290550000", \ - "0.0211456000, 0.0258099000, 0.0354529000, 0.0592248000, 0.1195113000, 0.2869052000, 0.7317605000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013079700, 0.0034215700, 0.0089506200, 0.0234143000, 0.0612504000, 0.1602270000"); - values("0.0210344000, 0.0280473000, 0.0469001000, 0.0975219000, 0.2318559000, 0.5877880000, 1.5065192000", \ - "0.0210124000, 0.0280498000, 0.0468486000, 0.0975190000, 0.2315239000, 0.5888980000, 1.5052428000", \ - "0.0210143000, 0.0280942000, 0.0468329000, 0.0973931000, 0.2319255000, 0.5860041000, 1.5082332000", \ - "0.0210076000, 0.0280743000, 0.0468406000, 0.0975308000, 0.2315063000, 0.5889038000, 1.5038567000", \ - "0.0209988000, 0.0280686000, 0.0468607000, 0.0973462000, 0.2319838000, 0.5886304000, 1.5127486000", \ - "0.0210478000, 0.0280944000, 0.0468952000, 0.0974970000, 0.2317951000, 0.5853232000, 1.5098438000", \ - "0.0209836000, 0.0280682000, 0.0468637000, 0.0973920000, 0.2319499000, 0.5871029000, 1.5019942000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__ebufn_1") { - leakage_power () { - value : 0.0025423000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0027640000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0042767000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0028469000; - when : "A&!TE_B"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__ebufn"; - cell_leakage_power : 0.0031074740; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0018070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0100960000, 0.0099851000, 0.0097295000, 0.0097976000, 0.0099546000, 0.0103163000, 0.0111502000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028614000, 0.0027661000, 0.0025465000, 0.0026033000, 0.0027342000, 0.0030361000, 0.0037320000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018850000; - } - pin ("TE_B") { - capacitance : 0.0031340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029300000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033380000; - } - pin ("Z") { - capacitance : 0.0022600000; - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0042927000, 0.0033918000, 0.0012376000, -0.004096500, -0.016962500, -0.047065800, -0.116852600", \ - "0.0042629000, 0.0033576000, 0.0011888000, -0.004132600, -0.017005600, -0.047113500, -0.116864700", \ - "0.0042624000, 0.0033756000, 0.0012164000, -0.004102100, -0.016966000, -0.047057400, -0.116845100", \ - "0.0039465000, 0.0030511000, 0.0009499000, -0.004390900, -0.017233000, -0.047309200, -0.117059100", \ - "0.0036269000, 0.0027021000, 0.0005900000, -0.004694100, -0.017478500, -0.047521200, -0.117227200", \ - "0.0037401000, 0.0027249000, 0.0003745000, -0.005101100, -0.017551500, -0.047480600, -0.117080300", \ - "0.0040413000, 0.0031730000, 0.0008310000, -0.004838400, -0.017671300, -0.047614700, -0.116938900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0061601000, 0.0073294000, 0.0099984000, 0.0158862000, 0.0289839000, 0.0593744000, 0.1287680000", \ - "0.0061151000, 0.0073039000, 0.0099287000, 0.0158574000, 0.0291196000, 0.0592806000, 0.1286141000", \ - "0.0061274000, 0.0073049000, 0.0099313000, 0.0158428000, 0.0289561000, 0.0593718000, 0.1284095000", \ - "0.0057988000, 0.0068800000, 0.0094646000, 0.0153577000, 0.0285531000, 0.0586355000, 0.1275586000", \ - "0.0054756000, 0.0065837000, 0.0091247000, 0.0148410000, 0.0281339000, 0.0585951000, 0.1272792000", \ - "0.0056021000, 0.0066934000, 0.0091536000, 0.0148595000, 0.0279662000, 0.0581651000, 0.1278920000", \ - "0.0058674000, 0.0069494000, 0.0092791000, 0.0150161000, 0.0280317000, 0.0583686000, 0.1272380000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("-0.003468400, -0.003410000, -0.003309600, -0.003177100, -0.003057500, -0.002974200, -0.002928300", \ - "-0.003678500, -0.003622600, -0.003528100, -0.003403700, -0.003287500, -0.003206700, -0.003159100", \ - "-0.003973500, -0.003921300, -0.003828300, -0.003697300, -0.003570200, -0.003479700, -0.003428900", \ - "-0.004256800, -0.004213200, -0.004124400, -0.003997500, -0.003844100, -0.003728800, -0.003659500", \ - "-0.004344600, -0.004314300, -0.004251100, -0.004133500, -0.003971700, -0.003816000, -0.003707900", \ - "-0.004083700, -0.004074700, -0.004062300, -0.003998200, -0.003856400, -0.003691600, -0.003513400", \ - "-0.002830900, -0.002823600, -0.002806400, -0.002808500, -0.002714300, -0.002574400, -0.002344100"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0197133000, 0.0207666000, 0.0231903000, 0.0287946000, 0.0417604000, 0.0719525000, 0.1405361000", \ - "0.0195131000, 0.0205675000, 0.0229918000, 0.0285936000, 0.0415882000, 0.0717010000, 0.1408661000", \ - "0.0193600000, 0.0204047000, 0.0228312000, 0.0284326000, 0.0414240000, 0.0715297000, 0.1407203000", \ - "0.0192869000, 0.0203415000, 0.0227686000, 0.0283771000, 0.0413446000, 0.0713644000, 0.1406408000", \ - "0.0193989000, 0.0204487000, 0.0228647000, 0.0284626000, 0.0414417000, 0.0711838000, 0.1401599000", \ - "0.0194823000, 0.0207991000, 0.0233251000, 0.0289887000, 0.0418234000, 0.0717692000, 0.1411823000", \ - "0.0206534000, 0.0217001000, 0.0241248000, 0.0297125000, 0.0431547000, 0.0729200000, 0.1422799000"); - } - when : "A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0183263000, 0.0173370000, 0.0149545000, 0.0094204000, -0.003615000, -0.033829900, -0.103643000", \ - "0.0181309000, 0.0171396000, 0.0147742000, 0.0092242000, -0.003810800, -0.034030300, -0.103842600", \ - "0.0179893000, 0.0169838000, 0.0146193000, 0.0090585000, -0.003964000, -0.034186300, -0.103959700", \ - "0.0179141000, 0.0169138000, 0.0145923000, 0.0089995000, -0.004036900, -0.034251800, -0.104072700", \ - "0.0179914000, 0.0169478000, 0.0148045000, 0.0090816000, -0.003953300, -0.034154200, -0.103980000", \ - "0.0183099000, 0.0171720000, 0.0147832000, 0.0091073000, -0.003503300, -0.033710800, -0.103530900", \ - "0.0201633000, 0.0184972000, 0.0160435000, 0.0103882000, -0.002685500, -0.032928300, -0.102279800"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("-0.003191300, -0.003234500, -0.003321700, -0.003412200, -0.003544500, -0.003610200, -0.003644100", \ - "-0.003355000, -0.003404400, -0.003488400, -0.003605300, -0.003706500, -0.003772200, -0.003805400", \ - "-0.003641000, -0.003683700, -0.003756500, -0.003852700, -0.003944500, -0.004008100, -0.004042700", \ - "-0.003916700, -0.003927200, -0.003998400, -0.004069000, -0.004136100, -0.004191500, -0.004223200", \ - "-0.003983600, -0.004013900, -0.003971100, -0.004005700, -0.004070200, -0.004127800, -0.004148300", \ - "-0.003629400, -0.003665600, -0.003716600, -0.003776000, -0.003835100, -0.003876900, -0.003903100", \ - "-0.002457700, -0.002483800, -0.002519800, -0.002570800, -0.002617700, -0.002651100, -0.002673300"); - } - when : "!A"; - } - max_capacitance : 0.0759990000; - max_transition : 1.5167910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0929883000, 0.0982373000, 0.1086333000, 0.1294735000, 0.1724623000, 0.2676447000, 0.4865965000", \ - "0.0981475000, 0.1033002000, 0.1137337000, 0.1345919000, 0.1775845000, 0.2726771000, 0.4914177000", \ - "0.1106669000, 0.1156932000, 0.1261357000, 0.1469843000, 0.1899885000, 0.2849657000, 0.5036166000", \ - "0.1414341000, 0.1465493000, 0.1569559000, 0.1778876000, 0.2209764000, 0.3162774000, 0.5360344000", \ - "0.2029469000, 0.2084856000, 0.2193356000, 0.2411150000, 0.2849980000, 0.3802664000, 0.5983855000", \ - "0.2986436000, 0.3053728000, 0.3184874000, 0.3429096000, 0.3892842000, 0.4855838000, 0.7046508000", \ - "0.4412852000, 0.4500864000, 0.4670209000, 0.4969931000, 0.5484998000, 0.6473861000, 0.8654603000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0909645000, 0.1010643000, 0.1244607000, 0.1757507000, 0.2901714000, 0.5513164000, 1.1529521000", \ - "0.0956039000, 0.1057781000, 0.1289095000, 0.1804094000, 0.2947152000, 0.5558047000, 1.1565180000", \ - "0.1066152000, 0.1167866000, 0.1398778000, 0.1909757000, 0.3054707000, 0.5690244000, 1.1698742000", \ - "0.1300444000, 0.1395034000, 0.1619714000, 0.2130801000, 0.3277315000, 0.5924446000, 1.1890299000", \ - "0.1663584000, 0.1761622000, 0.1982735000, 0.2485848000, 0.3639692000, 0.6264075000, 1.2255273000", \ - "0.2139718000, 0.2239952000, 0.2460309000, 0.2955977000, 0.4094379000, 0.6713531000, 1.2761721000", \ - "0.2649075000, 0.2772052000, 0.2995786000, 0.3498051000, 0.4622201000, 0.7253887000, 1.3240560000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0266246000, 0.0310762000, 0.0410783000, 0.0633952000, 0.1156539000, 0.2410052000, 0.5295975000", \ - "0.0266097000, 0.0308660000, 0.0410392000, 0.0634028000, 0.1158140000, 0.2411341000, 0.5375177000", \ - "0.0266432000, 0.0311151000, 0.0410625000, 0.0634543000, 0.1157703000, 0.2411084000, 0.5301488000", \ - "0.0269145000, 0.0313485000, 0.0413170000, 0.0635903000, 0.1158268000, 0.2408953000, 0.5313846000", \ - "0.0312139000, 0.0354350000, 0.0449248000, 0.0663946000, 0.1172935000, 0.2407341000, 0.5313958000", \ - "0.0419349000, 0.0460536000, 0.0549117000, 0.0754891000, 0.1234689000, 0.2428370000, 0.5311430000", \ - "0.0597111000, 0.0656687000, 0.0749664000, 0.0942616000, 0.1381363000, 0.2502916000, 0.5340560000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0531210000, 0.0657421000, 0.0949297000, 0.1620959000, 0.3165753000, 0.6760424000, 1.4994852000", \ - "0.0530867000, 0.0657486000, 0.0951089000, 0.1623685000, 0.3172001000, 0.6743978000, 1.4980112000", \ - "0.0530195000, 0.0657420000, 0.0950936000, 0.1623410000, 0.3169912000, 0.6782108000, 1.4974015000", \ - "0.0530819000, 0.0658460000, 0.0947350000, 0.1624032000, 0.3163502000, 0.6742186000, 1.4992354000", \ - "0.0550382000, 0.0672832000, 0.0959693000, 0.1625547000, 0.3169037000, 0.6752329000, 1.4949483000", \ - "0.0610164000, 0.0718374000, 0.0983768000, 0.1637085000, 0.3185348000, 0.6728086000, 1.5028884000", \ - "0.0754930000, 0.0860131000, 0.1097020000, 0.1684729000, 0.3191127000, 0.6779118000, 1.4943009000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0724978000, 0.0767369000, 0.0858998000, 0.1053987000, 0.1476147000, 0.2424481000, 0.4620274000", \ - "0.0773022000, 0.0815371000, 0.0907031000, 0.1101903000, 0.1523967000, 0.2474221000, 0.4655507000", \ - "0.0902059000, 0.0944374000, 0.1036077000, 0.1230909000, 0.1652863000, 0.2603306000, 0.4795357000", \ - "0.1204033000, 0.1246478000, 0.1338171000, 0.1534783000, 0.1957306000, 0.2906301000, 0.5086371000", \ - "0.1708348000, 0.1754668000, 0.1853479000, 0.2057068000, 0.2489876000, 0.3443096000, 0.5642672000", \ - "0.2474142000, 0.2527243000, 0.2644624000, 0.2869831000, 0.3313170000, 0.4275796000, 0.6462631000", \ - "0.3652993000, 0.3729336000, 0.3875495000, 0.4141957000, 0.4625668000, 0.5603346000, 0.7792665000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0640551000, 0.0732700000, 0.0944533000, 0.1431857000, 0.2556402000, 0.5175719000, 1.1218912000", \ - "0.0699832000, 0.0791881000, 0.1004199000, 0.1491344000, 0.2617069000, 0.5241578000, 1.1243899000", \ - "0.0833793000, 0.0925241000, 0.1137245000, 0.1624514000, 0.2750532000, 0.5377174000, 1.1371106000", \ - "0.1102221000, 0.1198175000, 0.1411854000, 0.1899382000, 0.3024667000, 0.5671858000, 1.1637800000", \ - "0.1558546000, 0.1684307000, 0.1949678000, 0.2484807000, 0.3612452000, 0.6227490000, 1.2202602000", \ - "0.2257220000, 0.2453952000, 0.2845337000, 0.3580140000, 0.4927027000, 0.7560361000, 1.3586918000", \ - "0.3164121000, 0.3499697000, 0.4156324000, 0.5333409000, 0.7275419000, 1.0559904000, 1.6694385000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0232136000, 0.0278970000, 0.0383644000, 0.0615818000, 0.1148204000, 0.2408178000, 0.5384786000", \ - "0.0232446000, 0.0278395000, 0.0383404000, 0.0616060000, 0.1150870000, 0.2411849000, 0.5305582000", \ - "0.0231490000, 0.0278659000, 0.0383385000, 0.0615606000, 0.1150289000, 0.2398392000, 0.5307360000", \ - "0.0236806000, 0.0282449000, 0.0386912000, 0.0617594000, 0.1149130000, 0.2409987000, 0.5316297000", \ - "0.0270009000, 0.0313161000, 0.0412526000, 0.0638710000, 0.1165475000, 0.2402692000, 0.5317048000", \ - "0.0341303000, 0.0382720000, 0.0475864000, 0.0690021000, 0.1193417000, 0.2417249000, 0.5321620000", \ - "0.0465099000, 0.0509636000, 0.0602955000, 0.0804775000, 0.1275388000, 0.2446622000, 0.5341135000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0533811000, 0.0657988000, 0.0949959000, 0.1620577000, 0.3164851000, 0.6773121000, 1.4989748000", \ - "0.0534020000, 0.0658687000, 0.0950285000, 0.1622036000, 0.3173702000, 0.6769993000, 1.4990911000", \ - "0.0533802000, 0.0659622000, 0.0950396000, 0.1621666000, 0.3173048000, 0.6768036000, 1.4987922000", \ - "0.0566589000, 0.0685180000, 0.0962644000, 0.1621705000, 0.3166571000, 0.6756593000, 1.4979634000", \ - "0.0743542000, 0.0862526000, 0.1120314000, 0.1710534000, 0.3181429000, 0.6726035000, 1.4951383000", \ - "0.1163410000, 0.1301976000, 0.1597242000, 0.2207082000, 0.3493886000, 0.6788662000, 1.5071423000", \ - "0.2043819000, 0.2229447000, 0.2616797000, 0.3344184000, 0.4748940000, 0.7672847000, 1.5167910000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0296542000, 0.0299864000, 0.0318400000, 0.0318400000, 0.0318400000, 0.0318400000, 0.0318400000", \ - "0.0271283000, 0.0271283000, 0.0271771000, 0.0272235000, 0.0272235000, 0.0272235000, 0.0272235000", \ - "0.0283423000, 0.0283423000, 0.0283423000, 0.0283423000, 0.0285067000, 0.0285067000, 0.0285067000", \ - "0.0251287000, 0.0251610000, 0.0251696000, 0.0251696000, 0.0251696000, 0.0251696000, 0.0251696000", \ - "0.0155868000, 0.0156778000, 0.0160241000, 0.0160241000, 0.0160241000, 0.0160241000, 0.0160241000", \ - "-0.006421800, -0.006364800, -0.006364800, -0.006326300, -0.006008300, -0.006008300, -0.006008300", \ - "-0.058569200, -0.058569200, -0.058569200, -0.058569200, -0.058569200, -0.058522000, -0.058522000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0027599000, 0.0034149700, 0.0049282900, 0.0084242600, 0.0165005000, 0.0351577000, 0.0782586000"); - values("0.0356156000, 0.0356383000, 0.0357007000, 0.0357007000, 0.0357007000, 0.0357007000, 0.0357007000", \ - "0.0410189000, 0.0410189000, 0.0410189000, 0.0410189000, 0.0410189000, 0.0410189000, 0.0410189000", \ - "0.0524107000, 0.0524107000, 0.0524107000, 0.0524107000, 0.0524107000, 0.0524107000, 0.0524107000", \ - "0.0678328000, 0.0678328000, 0.0679656000, 0.0679656000, 0.0679656000, 0.0679656000, 0.0679968000", \ - "0.0840994000, 0.0849362000, 0.0849362000, 0.0849362000, 0.0849362000, 0.0849362000, 0.0849362000", \ - "0.1005898000, 0.1008028000, 0.1012301000, 0.1012301000, 0.1023847000, 0.1023847000, 0.1023847000", \ - "0.1018812000, 0.1018812000, 0.1020764000, 0.1069239000, 0.1069239000, 0.1069239000, 0.1069239000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__ebufn_2") { - leakage_power () { - value : 0.0023765000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0040487000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0039655000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0030441000; - when : "A&!TE_B"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__ebufn"; - cell_leakage_power : 0.0033587030; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0018180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0115475000, 0.0114426000, 0.0112008000, 0.0112772000, 0.0114533000, 0.0118592000, 0.0127949000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0060135000, 0.0059365000, 0.0057589000, 0.0058145000, 0.0059427000, 0.0062382000, 0.0069194000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018930000; - } - pin ("TE_B") { - capacitance : 0.0040830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0037550000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044100000; - } - pin ("Z") { - capacitance : 0.0027540000; - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("0.0057719000, 0.0047117000, 0.0021559000, -0.004743200, -0.023371900, -0.071701200, -0.193830100", \ - "0.0057486000, 0.0047208000, 0.0021157000, -0.004719600, -0.023390100, -0.071713000, -0.193809800", \ - "0.0057867000, 0.0048153000, 0.0021631000, -0.004762300, -0.023305300, -0.071638800, -0.193761100", \ - "0.0054767000, 0.0044162000, 0.0017646000, -0.005186200, -0.023696000, -0.071919900, -0.193994000", \ - "0.0050598000, 0.0039768000, 0.0012535000, -0.005747100, -0.024201000, -0.072277400, -0.194252800", \ - "0.0050208000, 0.0038200000, 0.0008404000, -0.006505300, -0.024763600, -0.072732300, -0.194557800", \ - "0.0061965000, 0.0047401000, 0.0015957000, -0.006033500, -0.024575600, -0.072641900, -0.194117000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("0.0070743000, 0.0084660000, 0.0119121000, 0.0201158000, 0.0401223000, 0.0888260000, 0.2107471000", \ - "0.0070801000, 0.0084720000, 0.0119053000, 0.0201825000, 0.0401798000, 0.0890640000, 0.2093387000", \ - "0.0071025000, 0.0085013000, 0.0118841000, 0.0201580000, 0.0399066000, 0.0884126000, 0.2093822000", \ - "0.0068739000, 0.0082102000, 0.0113985000, 0.0195654000, 0.0393561000, 0.0880108000, 0.2092214000", \ - "0.0066301000, 0.0079029000, 0.0111047000, 0.0189377000, 0.0387823000, 0.0879299000, 0.2086614000", \ - "0.0068164000, 0.0080621000, 0.0110798000, 0.0188186000, 0.0382600000, 0.0870633000, 0.2082544000", \ - "0.0074315000, 0.0085950000, 0.0116848000, 0.0193444000, 0.0383070000, 0.0873107000, 0.2082346000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("-0.006476200, -0.006381500, -0.006197600, -0.005924300, -0.005627800, -0.005441900, -0.005325400", \ - "-0.006680000, -0.006581700, -0.006403500, -0.006126900, -0.005844900, -0.005644200, -0.005544200", \ - "-0.007052000, -0.006962600, -0.006784300, -0.006501100, -0.006181500, -0.005967000, -0.005850300", \ - "-0.007454600, -0.007378300, -0.007251200, -0.006930500, -0.006612400, -0.006305300, -0.006176700", \ - "-0.007780900, -0.007726900, -0.007590800, -0.007363700, -0.006981500, -0.006633800, -0.006349600", \ - "-0.007612500, -0.007581000, -0.007591800, -0.007350700, -0.007142300, -0.006627700, -0.006374000", \ - "-0.006340400, -0.006316600, -0.006565300, -0.006182500, -0.006284400, -0.005686900, -0.005548200"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("0.0290880000, 0.0303196000, 0.0333150000, 0.0409509000, 0.0601469000, 0.1084422000, 0.2289764000", \ - "0.0289106000, 0.0301369000, 0.0331507000, 0.0407739000, 0.0599620000, 0.1083575000, 0.2288162000", \ - "0.0287431000, 0.0299583000, 0.0329696000, 0.0405968000, 0.0598030000, 0.1081530000, 0.2286448000", \ - "0.0286275000, 0.0298565000, 0.0328813000, 0.0405325000, 0.0596795000, 0.1077513000, 0.2286241000", \ - "0.0287448000, 0.0299427000, 0.0329997000, 0.0405885000, 0.0597630000, 0.1080873000, 0.2286288000", \ - "0.0289872000, 0.0302752000, 0.0333844000, 0.0410672000, 0.0601189000, 0.1083658000, 0.2302092000", \ - "0.0296077000, 0.0308136000, 0.0338774000, 0.0414448000, 0.0613432000, 0.1093282000, 0.2303496000"); - } - when : "A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("0.0274622000, 0.0262730000, 0.0232710000, 0.0157990000, -0.003383700, -0.052027400, -0.174300500", \ - "0.0272544000, 0.0260940000, 0.0230830000, 0.0156071000, -0.003566600, -0.052197200, -0.174504100", \ - "0.0271041000, 0.0259341000, 0.0229345000, 0.0154412000, -0.003742000, -0.052370700, -0.174676300", \ - "0.0270596000, 0.0258641000, 0.0228584000, 0.0153750000, -0.003808100, -0.052443300, -0.174722500", \ - "0.0271450000, 0.0259142000, 0.0229532000, 0.0154525000, -0.003728500, -0.052372800, -0.174653500", \ - "0.0273078000, 0.0260933000, 0.0230436000, 0.0153226000, -0.003396200, -0.051999700, -0.174266500", \ - "0.0285247000, 0.0279496000, 0.0248788000, 0.0170999000, -0.002823600, -0.051541800, -0.173113000"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012556810, 0.0031534710, 0.0079195070, 0.0198887500, 0.0499478700, 0.1254372000"); - values("-0.006438000, -0.006484300, -0.006584300, -0.006743600, -0.006938900, -0.007064700, -0.007127100", \ - "-0.006625700, -0.006684200, -0.006790300, -0.006947900, -0.007125100, -0.007268000, -0.007337800", \ - "-0.006865200, -0.006928000, -0.007032600, -0.007198200, -0.007379700, -0.007513300, -0.007582000", \ - "-0.007242100, -0.007284800, -0.007333700, -0.007472200, -0.007624100, -0.007744700, -0.007812700", \ - "-0.007365500, -0.007415900, -0.007455900, -0.007585100, -0.007715700, -0.007818100, -0.007877400", \ - "-0.007226800, -0.007246200, -0.007275900, -0.007379800, -0.007531500, -0.007630100, -0.007698700", \ - "-0.006282300, -0.006290500, -0.006369800, -0.006463200, -0.006565800, -0.006621900, -0.006663600"); - } - when : "!A"; - } - max_capacitance : 0.1254370000; - max_transition : 1.5154890000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.1023038000, 0.1069248000, 0.1165587000, 0.1359126000, 0.1745794000, 0.2608748000, 0.4726469000", \ - "0.1074358000, 0.1120323000, 0.1218535000, 0.1410930000, 0.1797465000, 0.2661376000, 0.4784745000", \ - "0.1204884000, 0.1251012000, 0.1348571000, 0.1541990000, 0.1928403000, 0.2790793000, 0.4907811000", \ - "0.1516795000, 0.1562217000, 0.1658837000, 0.1852109000, 0.2239573000, 0.3102768000, 0.5226203000", \ - "0.2201122000, 0.2249066000, 0.2349915000, 0.2546836000, 0.2939819000, 0.3806176000, 0.5927007000", \ - "0.3313283000, 0.3373884000, 0.3498778000, 0.3731435000, 0.4156986000, 0.5046798000, 0.7160178000", \ - "0.4996663000, 0.5076627000, 0.5237167000, 0.5538067000, 0.6049437000, 0.6985236000, 0.9108338000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0877519000, 0.0953426000, 0.1135720000, 0.1572915000, 0.2630819000, 0.5224313000, 1.1657837000", \ - "0.0926065000, 0.1002128000, 0.1184274000, 0.1621918000, 0.2677473000, 0.5260579000, 1.1653669000", \ - "0.1039800000, 0.1113623000, 0.1295070000, 0.1733740000, 0.2790275000, 0.5380334000, 1.1765954000", \ - "0.1298348000, 0.1371133000, 0.1543248000, 0.1976135000, 0.3027510000, 0.5607362000, 1.2019474000", \ - "0.1731899000, 0.1805471000, 0.1980070000, 0.2399376000, 0.3449514000, 0.6057412000, 1.2449366000", \ - "0.2302974000, 0.2388115000, 0.2569499000, 0.2989339000, 0.4013596000, 0.6590615000, 1.3044776000", \ - "0.2918919000, 0.3027940000, 0.3254643000, 0.3693517000, 0.4699504000, 0.7277423000, 1.3689265000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0232122000, 0.0265113000, 0.0342879000, 0.0518234000, 0.0951062000, 0.2064565000, 0.4931662000", \ - "0.0232841000, 0.0266837000, 0.0342096000, 0.0518520000, 0.0950391000, 0.2063821000, 0.4943738000", \ - "0.0233392000, 0.0265279000, 0.0342336000, 0.0517281000, 0.0950169000, 0.2064639000, 0.4941642000", \ - "0.0232959000, 0.0266446000, 0.0342501000, 0.0519633000, 0.0951033000, 0.2064625000, 0.4930376000", \ - "0.0270312000, 0.0299016000, 0.0370631000, 0.0538689000, 0.0960610000, 0.2068736000, 0.4936827000", \ - "0.0383216000, 0.0418144000, 0.0493006000, 0.0651962000, 0.1047889000, 0.2101341000, 0.4935580000", \ - "0.0575215000, 0.0617037000, 0.0708702000, 0.0881234000, 0.1256506000, 0.2217563000, 0.4974485000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0385017000, 0.0475828000, 0.0700857000, 0.1266822000, 0.2679972000, 0.6208182000, 1.5044416000", \ - "0.0385115000, 0.0475162000, 0.0701542000, 0.1264449000, 0.2673845000, 0.6212928000, 1.4950463000", \ - "0.0384789000, 0.0476466000, 0.0698953000, 0.1268239000, 0.2671473000, 0.6171207000, 1.4968542000", \ - "0.0388619000, 0.0477591000, 0.0702933000, 0.1267153000, 0.2675588000, 0.6169995000, 1.4990675000", \ - "0.0418853000, 0.0503479000, 0.0719923000, 0.1271615000, 0.2677335000, 0.6213077000, 1.4958242000", \ - "0.0499665000, 0.0580488000, 0.0776917000, 0.1294014000, 0.2683959000, 0.6173865000, 1.4982623000", \ - "0.0652281000, 0.0736847000, 0.0928300000, 0.1397249000, 0.2704181000, 0.6215702000, 1.4945336000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0783716000, 0.0817521000, 0.0894397000, 0.1062893000, 0.1433683000, 0.2293013000, 0.4412827000", \ - "0.0831106000, 0.0865550000, 0.0942278000, 0.1110649000, 0.1481277000, 0.2340240000, 0.4460124000", \ - "0.0961758000, 0.0995881000, 0.1072550000, 0.1240809000, 0.1611288000, 0.2470209000, 0.4591055000", \ - "0.1272127000, 0.1306477000, 0.1383172000, 0.1553353000, 0.1924225000, 0.2783441000, 0.4896857000", \ - "0.1837349000, 0.1876809000, 0.1962521000, 0.2140397000, 0.2520534000, 0.3383595000, 0.5505802000", \ - "0.2690093000, 0.2741179000, 0.2848227000, 0.3057469000, 0.3461791000, 0.4343065000, 0.6464346000", \ - "0.3982755000, 0.4051377000, 0.4194002000, 0.4458612000, 0.4930710000, 0.5852090000, 0.7985270000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0586916000, 0.0654487000, 0.0818677000, 0.1224278000, 0.2240519000, 0.4808592000, 1.1194425000", \ - "0.0646488000, 0.0713847000, 0.0877588000, 0.1283376000, 0.2299118000, 0.4860902000, 1.1247179000", \ - "0.0781745000, 0.0848502000, 0.1012513000, 0.1418661000, 0.2436180000, 0.5000309000, 1.1383464000", \ - "0.1052665000, 0.1125560000, 0.1295920000, 0.1701649000, 0.2720220000, 0.5268933000, 1.1665595000", \ - "0.1481740000, 0.1580614000, 0.1800857000, 0.2280068000, 0.3315345000, 0.5882991000, 1.2273010000", \ - "0.2130277000, 0.2290153000, 0.2631426000, 0.3308883000, 0.4607918000, 0.7234689000, 1.3704221000", \ - "0.2910137000, 0.3193568000, 0.3789984000, 0.4920805000, 0.6867959000, 1.0222534000, 1.6813619000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0179051000, 0.0212868000, 0.0295467000, 0.0484753000, 0.0934514000, 0.2058531000, 0.4934511000", \ - "0.0178747000, 0.0213380000, 0.0295308000, 0.0485582000, 0.0935040000, 0.2061702000, 0.4940919000", \ - "0.0178488000, 0.0213045000, 0.0295289000, 0.0484629000, 0.0934060000, 0.2061366000, 0.4943285000", \ - "0.0180336000, 0.0214430000, 0.0295518000, 0.0485282000, 0.0935263000, 0.2062258000, 0.4942387000", \ - "0.0215657000, 0.0248419000, 0.0326888000, 0.0508680000, 0.0948468000, 0.2066540000, 0.4932553000", \ - "0.0301163000, 0.0332356000, 0.0404741000, 0.0582232000, 0.0995756000, 0.2086559000, 0.4926993000", \ - "0.0444728000, 0.0476376000, 0.0552890000, 0.0721130000, 0.1118891000, 0.2145509000, 0.4952104000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0394356000, 0.0482064000, 0.0703239000, 0.1265016000, 0.2668533000, 0.6183522000, 1.4962874000", \ - "0.0394567000, 0.0480626000, 0.0704121000, 0.1264474000, 0.2669384000, 0.6199568000, 1.4976276000", \ - "0.0394604000, 0.0482773000, 0.0704544000, 0.1264640000, 0.2665884000, 0.6192993000, 1.4977134000", \ - "0.0430778000, 0.0510153000, 0.0720876000, 0.1269732000, 0.2669207000, 0.6179797000, 1.4978644000", \ - "0.0584946000, 0.0671806000, 0.0887161000, 0.1383082000, 0.2693220000, 0.6181413000, 1.4962555000", \ - "0.0957926000, 0.1061243000, 0.1313983000, 0.1859615000, 0.3051895000, 0.6258250000, 1.5071852000", \ - "0.1769004000, 0.1922341000, 0.2260252000, 0.2935421000, 0.4270747000, 0.7168953000, 1.5154888000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0373633000, 0.0375755000, 0.0377221000, 0.0377221000, 0.0377221000, 0.0377496000, 0.0377496000", \ - "0.0358347000, 0.0370633000, 0.0370633000, 0.0370633000, 0.0370633000, 0.0370633000, 0.0370633000", \ - "0.0352518000, 0.0382556000, 0.0382556000, 0.0385486000, 0.0385486000, 0.0385486000, 0.0385486000", \ - "0.0278589000, 0.0343726000, 0.0344490000, 0.0344490000, 0.0344490000, 0.0344490000, 0.0344490000", \ - "0.0118519000, 0.0223711000, 0.0223711000, 0.0223711000, 0.0223711000, 0.0223711000, 0.0226721000", \ - "-0.023197200, -0.002199600, -0.002191500, -0.002191500, -0.002191500, -0.002191500, -0.002191500", \ - "-0.103743100, -0.060899500, -0.060899500, -0.060899500, -0.060899500, -0.060899500, -0.060899500"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0032537000, 0.0040093800, 0.0059071700, 0.0106732000, 0.0226425000, 0.0527016000, 0.1281910000"); - values("0.0466680000, 0.0466680000, 0.0467142000, 0.0467142000, 0.0467142000, 0.0467299000, 0.0467299000", \ - "0.0519942000, 0.0519954000, 0.0520032000, 0.0520032000, 0.0520336000, 0.0520336000, 0.0520336000", \ - "0.0633918000, 0.0634192000, 0.0635058000, 0.0635254000, 0.0635970000, 0.0635970000, 0.0636611000", \ - "0.0835093000, 0.0835093000, 0.0835093000, 0.0835093000, 0.0835093000, 0.0835326000, 0.0835326000", \ - "0.1083979000, 0.1084031000, 0.1084163000, 0.1084163000, 0.1093770000, 0.1093770000, 0.1093770000", \ - "0.1370455000, 0.1370455000, 0.1370455000, 0.1370455000, 0.1370455000, 0.1370455000, 0.1370455000", \ - "0.1571110000, 0.1571540000, 0.1592801000, 0.1592801000, 0.1592801000, 0.1592801000, 0.1592801000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__ebufn_4") { - leakage_power () { - value : 0.0060665000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0044055000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0074530000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0058304000; - when : "A&!TE_B"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__ebufn"; - cell_leakage_power : 0.0059388620; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0183840000, 0.0182409000, 0.0179110000, 0.0180675000, 0.0184281000, 0.0192595000, 0.0211757000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0095670000, 0.0094616000, 0.0092185000, 0.0093263000, 0.0095748000, 0.0101474000, 0.0114674000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026010000; - } - pin ("TE_B") { - capacitance : 0.0068680000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0062590000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0074760000; - } - pin ("Z") { - capacitance : 0.0052040000; - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("-0.012608900, -0.012488100, -0.012195300, -0.011660300, -0.011030100, -0.010562500, -0.010300300", \ - "-0.013051100, -0.012922800, -0.012631500, -0.012109900, -0.011473900, -0.011066500, -0.010831900", \ - "-0.013649200, -0.013526300, -0.013239300, -0.012716100, -0.012075100, -0.011557700, -0.011285500", \ - "-0.014351700, -0.014241500, -0.013989600, -0.013472800, -0.012751900, -0.012122700, -0.011770600", \ - "-0.014875600, -0.014798300, -0.014607000, -0.014181800, -0.013435300, -0.012635700, -0.012111300", \ - "-0.014690200, -0.014642200, -0.014515200, -0.014220000, -0.013616100, -0.012766300, -0.011997700", \ - "-0.012728900, -0.012699400, -0.012603000, -0.012353500, -0.011901000, -0.011201300, -0.010324700"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0525960000, 0.0540240000, 0.0578881000, 0.0685844000, 0.0980748000, 0.1797182000, 0.4049193000", \ - "0.0523522000, 0.0537851000, 0.0576503000, 0.0683349000, 0.0978203000, 0.1796209000, 0.4030186000", \ - "0.0521012000, 0.0535134000, 0.0574018000, 0.0680848000, 0.0975753000, 0.1791840000, 0.4046436000", \ - "0.0520402000, 0.0533876000, 0.0572835000, 0.0679604000, 0.0974548000, 0.1791407000, 0.4029778000", \ - "0.0521022000, 0.0535573000, 0.0574402000, 0.0681269000, 0.0976100000, 0.1792284000, 0.4028349000", \ - "0.0528105000, 0.0542104000, 0.0581417000, 0.0688862000, 0.0983920000, 0.1797248000, 0.4036161000", \ - "0.0535855000, 0.0549620000, 0.0588245000, 0.0696261000, 0.1002331000, 0.1818963000, 0.4062150000"); - } - when : "A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0508673000, 0.0494504000, 0.0456050000, 0.0350560000, 0.0057532000, -0.076321900, -0.303172300", \ - "0.0506009000, 0.0492147000, 0.0453546000, 0.0347980000, 0.0054835000, -0.076588700, -0.303429800", \ - "0.0503513000, 0.0489442000, 0.0451464000, 0.0345898000, 0.0052509000, -0.076818900, -0.303630200", \ - "0.0502710000, 0.0488683000, 0.0449873000, 0.0344221000, 0.0051191000, -0.076974600, -0.303775100", \ - "0.0504122000, 0.0490846000, 0.0451554000, 0.0346291000, 0.0054486000, -0.076624400, -0.303449400", \ - "0.0508420000, 0.0493212000, 0.0454537000, 0.0346760000, 0.0057662000, -0.075739400, -0.302538200", \ - "0.0533309000, 0.0516941000, 0.0478324000, 0.0370649000, 0.0074754000, -0.075047500, -0.300590900"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("-0.012745200, -0.012801100, -0.012933300, -0.013207500, -0.013568400, -0.013873300, -0.014024700", \ - "-0.013010900, -0.013072800, -0.013219700, -0.013529300, -0.013925500, -0.014255100, -0.014427400", \ - "-0.013475600, -0.013544400, -0.013694500, -0.013983100, -0.014358400, -0.014661600, -0.014816000", \ - "-0.013943000, -0.014007100, -0.014139700, -0.014396000, -0.014725900, -0.015000000, -0.015150100", \ - "-0.014299200, -0.014348200, -0.014478500, -0.014688400, -0.014974000, -0.015222400, -0.015353800", \ - "-0.014056600, -0.014017200, -0.014131700, -0.014332000, -0.014566400, -0.014785900, -0.014957500", \ - "-0.012473200, -0.012458900, -0.012696600, -0.012824000, -0.012960700, -0.013120100, -0.013220600"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0126722000, 0.0114882000, 0.0082141000, -0.001339300, -0.029341900, -0.110517300, -0.336982700", \ - "0.0126802000, 0.0115405000, 0.0081319000, -0.001333800, -0.029321800, -0.110554300, -0.337005300", \ - "0.0127200000, 0.0115572000, 0.0082009000, -0.001243700, -0.029309400, -0.110416300, -0.336878500", \ - "0.0122655000, 0.0110616000, 0.0076811000, -0.001882700, -0.029885200, -0.110954000, -0.337262200", \ - "0.0115422000, 0.0102671000, 0.0067340000, -0.002972400, -0.030916800, -0.111784200, -0.337868200", \ - "0.0108582000, 0.0094379000, 0.0057741000, -0.004142000, -0.032024900, -0.112649900, -0.338492000", \ - "0.0130870000, 0.0116232000, 0.0080957000, -0.002214300, -0.031404300, -0.113426900, -0.338924600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0153047000, 0.0169122000, 0.0213793000, 0.0333478000, 0.0642715000, 0.1465180000, 0.3723705000", \ - "0.0153194000, 0.0169417000, 0.0214080000, 0.0333410000, 0.0642679000, 0.1465404000, 0.3729373000", \ - "0.0154033000, 0.0170095000, 0.0214138000, 0.0332491000, 0.0642061000, 0.1465423000, 0.3722662000", \ - "0.0149867000, 0.0165474000, 0.0208055000, 0.0324389000, 0.0632042000, 0.1466965000, 0.3705431000", \ - "0.0145057000, 0.0160037000, 0.0201827000, 0.0314915000, 0.0621478000, 0.1454610000, 0.3698455000", \ - "0.0149142000, 0.0163514000, 0.0202682000, 0.0310591000, 0.0610766000, 0.1437859000, 0.3690581000", \ - "0.0154784000, 0.0169214000, 0.0208134000, 0.0315001000, 0.0616066000, 0.1437341000, 0.3688011000"); - } - } - max_capacitance : 0.2197360000; - max_transition : 1.5199760000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.1149255000, 0.1182594000, 0.1261999000, 0.1435066000, 0.1794014000, 0.2621976000, 0.4791252000", \ - "0.1200205000, 0.1233917000, 0.1313370000, 0.1487107000, 0.1845900000, 0.2672957000, 0.4846111000", \ - "0.1329951000, 0.1364021000, 0.1443256000, 0.1616579000, 0.1976727000, 0.2804021000, 0.4974550000", \ - "0.1638803000, 0.1671765000, 0.1750590000, 0.1922302000, 0.2282795000, 0.3110634000, 0.5286851000", \ - "0.2347749000, 0.2381224000, 0.2460856000, 0.2633813000, 0.2997506000, 0.3827799000, 0.6009486000", \ - "0.3544641000, 0.3586965000, 0.3687057000, 0.3895948000, 0.4298205000, 0.5155218000, 0.7335433000", \ - "0.5378363000, 0.5430065000, 0.5564657000, 0.5835148000, 0.6334583000, 0.7236570000, 0.9421184000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0931247000, 0.0982667000, 0.1118656000, 0.1478312000, 0.2413614000, 0.4893734000, 1.1656867000", \ - "0.0978272000, 0.1030348000, 0.1166651000, 0.1527066000, 0.2463569000, 0.4941735000, 1.1801111000", \ - "0.1091550000, 0.1142340000, 0.1277920000, 0.1634938000, 0.2568692000, 0.5051237000, 1.1919775000", \ - "0.1346575000, 0.1395578000, 0.1528057000, 0.1876632000, 0.2807128000, 0.5308335000, 1.2062495000", \ - "0.1784412000, 0.1835770000, 0.1968519000, 0.2311620000, 0.3238268000, 0.5761045000, 1.2493176000", \ - "0.2357254000, 0.2415706000, 0.2556813000, 0.2899362000, 0.3806852000, 0.6278761000, 1.3052650000", \ - "0.2929643000, 0.3005136000, 0.3182493000, 0.3552434000, 0.4460424000, 0.6925852000, 1.3682133000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0259198000, 0.0280775000, 0.0340358000, 0.0477852000, 0.0853510000, 0.1892935000, 0.4882839000", \ - "0.0259959000, 0.0282271000, 0.0338118000, 0.0480683000, 0.0852708000, 0.1895726000, 0.4879205000", \ - "0.0260338000, 0.0279955000, 0.0338235000, 0.0480106000, 0.0853003000, 0.1894089000, 0.4882610000", \ - "0.0260331000, 0.0280645000, 0.0338135000, 0.0478875000, 0.0852256000, 0.1896505000, 0.4862058000", \ - "0.0284393000, 0.0306005000, 0.0358212000, 0.0493556000, 0.0862938000, 0.1897059000, 0.4876610000", \ - "0.0410809000, 0.0434982000, 0.0492732000, 0.0627835000, 0.0959842000, 0.1941683000, 0.4882271000", \ - "0.0614382000, 0.0646611000, 0.0715438000, 0.0870442000, 0.1193566000, 0.2101172000, 0.4914112000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0392873000, 0.0453710000, 0.0618428000, 0.1071766000, 0.2311050000, 0.5684255000, 1.5036670000", \ - "0.0393588000, 0.0453007000, 0.0618754000, 0.1072600000, 0.2308106000, 0.5686339000, 1.5126327000", \ - "0.0394082000, 0.0453082000, 0.0618193000, 0.1068964000, 0.2309538000, 0.5680670000, 1.5096161000", \ - "0.0397007000, 0.0456579000, 0.0619891000, 0.1071963000, 0.2310266000, 0.5721811000, 1.4981185000", \ - "0.0430421000, 0.0484032000, 0.0640807000, 0.1078064000, 0.2312350000, 0.5721657000, 1.4995346000", \ - "0.0511742000, 0.0565202000, 0.0709245000, 0.1115338000, 0.2322099000, 0.5684732000, 1.5023693000", \ - "0.0664883000, 0.0723523000, 0.0872889000, 0.1246317000, 0.2357960000, 0.5730348000, 1.4972052000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0813905000, 0.0837478000, 0.0896998000, 0.1040223000, 0.1375861000, 0.2194636000, 0.4365363000", \ - "0.0860825000, 0.0884471000, 0.0943149000, 0.1086726000, 0.1422580000, 0.2241227000, 0.4414702000", \ - "0.0988956000, 0.1012466000, 0.1072332000, 0.1214345000, 0.1551395000, 0.2370477000, 0.4551521000", \ - "0.1299342000, 0.1322927000, 0.1382792000, 0.1526049000, 0.1861807000, 0.2681197000, 0.4862889000", \ - "0.1874616000, 0.1901358000, 0.1968910000, 0.2121533000, 0.2464834000, 0.3290135000, 0.5471897000", \ - "0.2755760000, 0.2790126000, 0.2874945000, 0.3054346000, 0.3432147000, 0.4278716000, 0.6460567000", \ - "0.4113449000, 0.4161404000, 0.4273041000, 0.4509820000, 0.4959207000, 0.5854775000, 0.8052182000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0617656000, 0.0663995000, 0.0785755000, 0.1112609000, 0.2002138000, 0.4456290000, 1.1293180000", \ - "0.0674377000, 0.0721169000, 0.0843421000, 0.1170597000, 0.2059030000, 0.4510663000, 1.1307449000", \ - "0.0811675000, 0.0857948000, 0.0978643000, 0.1306635000, 0.2196403000, 0.4650992000, 1.1464052000", \ - "0.1077861000, 0.1130997000, 0.1258079000, 0.1588302000, 0.2477742000, 0.4931618000, 1.1690001000", \ - "0.1517599000, 0.1582913000, 0.1747083000, 0.2144738000, 0.3069211000, 0.5525901000, 1.2291705000", \ - "0.2186099000, 0.2291682000, 0.2548092000, 0.3119041000, 0.4310452000, 0.6878079000, 1.3647488000", \ - "0.3047341000, 0.3234915000, 0.3688720000, 0.4655376000, 0.6471896000, 0.9798612000, 1.6785845000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0185657000, 0.0209026000, 0.0271353000, 0.0430676000, 0.0829317000, 0.1892509000, 0.4883497000", \ - "0.0185616000, 0.0209207000, 0.0271784000, 0.0431189000, 0.0828969000, 0.1892695000, 0.4879238000", \ - "0.0185950000, 0.0209236000, 0.0271803000, 0.0430489000, 0.0828615000, 0.1888524000, 0.4866497000", \ - "0.0187754000, 0.0210828000, 0.0272295000, 0.0431159000, 0.0829451000, 0.1889089000, 0.4869470000", \ - "0.0224449000, 0.0246207000, 0.0304355000, 0.0454768000, 0.0841061000, 0.1894090000, 0.4871054000", \ - "0.0313988000, 0.0334840000, 0.0387812000, 0.0526774000, 0.0897822000, 0.1922353000, 0.4865852000", \ - "0.0465384000, 0.0485619000, 0.0539381000, 0.0678959000, 0.1027244000, 0.1995354000, 0.4884083000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0404073000, 0.0462863000, 0.0622998000, 0.1072643000, 0.2309012000, 0.5705887000, 1.5112268000", \ - "0.0403334000, 0.0462371000, 0.0624405000, 0.1072874000, 0.2308918000, 0.5712378000, 1.5019913000", \ - "0.0405621000, 0.0461246000, 0.0622589000, 0.1073260000, 0.2309304000, 0.5704849000, 1.5106717000", \ - "0.0439604000, 0.0492479000, 0.0646142000, 0.1080238000, 0.2309428000, 0.5707148000, 1.5067138000", \ - "0.0578448000, 0.0638715000, 0.0803653000, 0.1207746000, 0.2348869000, 0.5703728000, 1.5023632000", \ - "0.0935197000, 0.1005041000, 0.1192563000, 0.1648691000, 0.2735171000, 0.5797945000, 1.5016944000", \ - "0.1732278000, 0.1829150000, 0.2081673000, 0.2648584000, 0.3861906000, 0.6719230000, 1.5199760000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0413630000, 0.0421091000, 0.0421091000, 0.0421091000, 0.0421091000, 0.0421091000, 0.0421091000", \ - "0.0409809000, 0.0409809000, 0.0409809000, 0.0410081000, 0.0410081000, 0.0410081000, 0.0410081000", \ - "0.0413356000, 0.0418487000, 0.0428976000, 0.0428976000, 0.0429494000, 0.0429494000, 0.0429494000", \ - "0.0342400000, 0.0350030000, 0.0375927000, 0.0376196000, 0.0378868000, 0.0378868000, 0.0380626000", \ - "0.0172446000, 0.0191497000, 0.0239132000, 0.0240317000, 0.0240317000, 0.0240317000, 0.0240317000", \ - "-0.016831400, -0.014335100, -0.005711900, -0.004933200, -0.004933200, -0.004933200, -0.004933200", \ - "-0.094350600, -0.088057000, -0.070742700, -0.070742700, -0.070742700, -0.070742700, -0.070547600"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0057039000, 0.0065825600, 0.0090053300, 0.0156857000, 0.0341057000, 0.0848957000, 0.2249400000"); - values("0.0476136000, 0.0476141000, 0.0477552000, 0.0477552000, 0.0477552000, 0.0478065000, 0.0478065000", \ - "0.0529936000, 0.0529936000, 0.0529936000, 0.0529936000, 0.0529936000, 0.0529936000, 0.0529936000", \ - "0.0640902000, 0.0640902000, 0.0640902000, 0.0640902000, 0.0640979000, 0.0641154000, 0.0641154000", \ - "0.0837798000, 0.0837804000, 0.0838952000, 0.0838952000, 0.0839377000, 0.0839377000, 0.0839377000", \ - "0.1086178000, 0.1086178000, 0.1086178000, 0.1086178000, 0.1086178000, 0.1086518000, 0.1086518000", \ - "0.1352346000, 0.1352903000, 0.1354519000, 0.1354519000, 0.1354519000, 0.1358874000, 0.1358874000", \ - "0.1519787000, 0.1519823000, 0.1519900000, 0.1519900000, 0.1519900000, 0.1519900000, 0.1519900000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__ebufn_8") { - leakage_power () { - value : 0.0037873000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0061811000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0068191000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0085232000; - when : "A&!TE_B"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__ebufn"; - cell_leakage_power : 0.0063276490; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0044740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0328745000, 0.0326427000, 0.0321084000, 0.0323713000, 0.0329773000, 0.0343741000, 0.0375938000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0142226000, 0.0140780000, 0.0137447000, 0.0139324000, 0.0143649000, 0.0153619000, 0.0176601000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046950000; - } - pin ("TE_B") { - capacitance : 0.0105390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0094820000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0115960000; - } - pin ("Z") { - capacitance : 0.0097500000; - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("0.0273263000, 0.0259589000, 0.0218524000, 0.0090837000, -0.032592000, -0.166470500, -0.578278900", \ - "0.0273730000, 0.0259707000, 0.0219099000, 0.0090903000, -0.032667200, -0.166540300, -0.578323200", \ - "0.0273753000, 0.0259738000, 0.0218215000, 0.0091400000, -0.032525900, -0.166373600, -0.578152800", \ - "0.0265457000, 0.0252114000, 0.0210435000, 0.0080080000, -0.033605000, -0.167321200, -0.578804900", \ - "0.0252813000, 0.0237974000, 0.0193754000, 0.0061631000, -0.035671800, -0.168712600, -0.579831500", \ - "0.0248968000, 0.0232910000, 0.0186400000, 0.0048116000, -0.036282900, -0.169745400, -0.580410200", \ - "0.0297953000, 0.0280170000, 0.0228034000, 0.0078417000, -0.038580800, -0.172019600, -0.581818600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("0.0325657000, 0.0345456000, 0.0403295000, 0.0573337000, 0.1057614000, 0.2425720000, 0.6507960000", \ - "0.0325420000, 0.0345083000, 0.0404074000, 0.0574077000, 0.1055584000, 0.2440667000, 0.6508898000", \ - "0.0325117000, 0.0344416000, 0.0402883000, 0.0572250000, 0.1051692000, 0.2436652000, 0.6550374000", \ - "0.0319978000, 0.0338473000, 0.0393991000, 0.0558745000, 0.1034379000, 0.2424856000, 0.6507225000", \ - "0.0311997000, 0.0329375000, 0.0383230000, 0.0542450000, 0.1014222000, 0.2393511000, 0.6523242000", \ - "0.0314600000, 0.0331179000, 0.0381257000, 0.0526691000, 0.0992131000, 0.2372285000, 0.6501552000", \ - "0.0327887000, 0.0344269000, 0.0393335000, 0.0544197000, 0.0999979000, 0.2366043000, 0.6466984000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("-0.024482000, -0.024337700, -0.023905200, -0.022970000, -0.021611900, -0.020473800, -0.019878900", \ - "-0.025005600, -0.024848900, -0.024424900, -0.023498400, -0.022186100, -0.021045800, -0.020450100", \ - "-0.025752000, -0.025602700, -0.025196000, -0.024271500, -0.022870300, -0.021680200, -0.021020800", \ - "-0.026837700, -0.026706400, -0.026337500, -0.025455700, -0.023959800, -0.022489400, -0.021672500", \ - "-0.027506200, -0.027409900, -0.027133700, -0.026428800, -0.025015700, -0.023259500, -0.022047200", \ - "-0.028197100, -0.028131400, -0.027936600, -0.027445700, -0.026351800, -0.024542000, -0.022816900", \ - "-0.027018500, -0.026955100, -0.026748200, -0.026325400, -0.025509100, -0.024681700, -0.022756800"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("0.0953919000, 0.0970948000, 0.1022110000, 0.1171392000, 0.1618289000, 0.2968763000, 0.7042488000", \ - "0.0951609000, 0.0968782000, 0.1019531000, 0.1169236000, 0.1615454000, 0.2964408000, 0.7040799000", \ - "0.0948311000, 0.0965870000, 0.1016547000, 0.1166413000, 0.1612856000, 0.2963242000, 0.7036114000", \ - "0.0945582000, 0.0963654000, 0.1014394000, 0.1164690000, 0.1610738000, 0.2960920000, 0.7037895000", \ - "0.0945066000, 0.0962353000, 0.1014367000, 0.1164801000, 0.1611628000, 0.2961246000, 0.7036272000", \ - "0.0952546000, 0.0969571000, 0.1019329000, 0.1168792000, 0.1618665000, 0.2965438000, 0.7040271000", \ - "0.0951458000, 0.0968704000, 0.1016346000, 0.1164518000, 0.1634567000, 0.2987366000, 0.7074564000"); - } - when : "A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("0.0958947000, 0.0942471000, 0.0894349000, 0.0748540000, 0.0306481000, -0.105421600, -0.518124900", \ - "0.0956363000, 0.0940312000, 0.0892163000, 0.0746510000, 0.0303812000, -0.105665900, -0.518396000", \ - "0.0952386000, 0.0937123000, 0.0889172000, 0.0743517000, 0.0300717000, -0.105932900, -0.518708100", \ - "0.0951332000, 0.0935001000, 0.0887090000, 0.0741410000, 0.0298652000, -0.106144400, -0.518912000", \ - "0.0950016000, 0.0934021000, 0.0886234000, 0.0740533000, 0.0298414000, -0.106202900, -0.518971300", \ - "0.0930157000, 0.0915843000, 0.0871004000, 0.0735504000, 0.0304944000, -0.105529800, -0.518315700", \ - "0.0971523000, 0.0955060000, 0.0905482000, 0.0755963000, 0.0304097000, -0.105218400, -0.516709400"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015110230, 0.0045663790, 0.0137998000, 0.0417036400, 0.1260303000, 0.3808692000"); - values("-0.025255000, -0.025394600, -0.025550600, -0.025916400, -0.026536900, -0.027113000, -0.027444900", \ - "-0.025760900, -0.025817800, -0.025991700, -0.026390700, -0.027043500, -0.027638100, -0.027968600", \ - "-0.026157100, -0.026224200, -0.026454100, -0.026818500, -0.027495200, -0.028160300, -0.028527100", \ - "-0.026733700, -0.026804800, -0.026993700, -0.027400100, -0.028034000, -0.028628500, -0.028973500", \ - "-0.026966000, -0.027032800, -0.027205700, -0.027629300, -0.028066200, -0.028584700, -0.028904900", \ - "-0.027643500, -0.027706700, -0.027850200, -0.028163800, -0.028502600, -0.028954800, -0.029257200", \ - "-0.026257300, -0.026308700, -0.026433600, -0.026717400, -0.027097800, -0.027507800, -0.027747400"); - } - when : "!A"; - } - max_capacitance : 0.3808690000; - max_transition : 1.5205050000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.1204172000, 0.1227875000, 0.1292726000, 0.1451509000, 0.1813781000, 0.2690331000, 0.5185488000", \ - "0.1257269000, 0.1279296000, 0.1344749000, 0.1504695000, 0.1866001000, 0.2743905000, 0.5233244000", \ - "0.1384981000, 0.1408446000, 0.1472812000, 0.1632946000, 0.1995359000, 0.2876089000, 0.5370390000", \ - "0.1703799000, 0.1726847000, 0.1792031000, 0.1950242000, 0.2312974000, 0.3191540000, 0.5685363000", \ - "0.2420524000, 0.2444288000, 0.2508010000, 0.2666209000, 0.3030124000, 0.3911523000, 0.6411455000", \ - "0.3673220000, 0.3702159000, 0.3780670000, 0.3966431000, 0.4357283000, 0.5266126000, 0.7760533000", \ - "0.5647163000, 0.5683731000, 0.5782642000, 0.6021039000, 0.6499651000, 0.7475661000, 0.9977651000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0918757000, 0.0953930000, 0.1058788000, 0.1355275000, 0.2197681000, 0.4582282000, 1.1717322000", \ - "0.0965392000, 0.1000516000, 0.1103575000, 0.1403582000, 0.2246187000, 0.4644618000, 1.1792712000", \ - "0.1075082000, 0.1110468000, 0.1212566000, 0.1507943000, 0.2347606000, 0.4748913000, 1.1893931000", \ - "0.1322669000, 0.1356560000, 0.1455553000, 0.1743317000, 0.2572909000, 0.4992124000, 1.2077108000", \ - "0.1716515000, 0.1750293000, 0.1848907000, 0.2129493000, 0.2952328000, 0.5354925000, 1.2479309000", \ - "0.2209626000, 0.2246818000, 0.2349285000, 0.2627544000, 0.3434198000, 0.5827903000, 1.2978936000", \ - "0.2631786000, 0.2679861000, 0.2808593000, 0.3122841000, 0.3916210000, 0.6290123000, 1.3403879000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0286192000, 0.0303247000, 0.0349220000, 0.0480170000, 0.0854048000, 0.1974369000, 0.5463155000", \ - "0.0286195000, 0.0302494000, 0.0350892000, 0.0481002000, 0.0852083000, 0.1977651000, 0.5470394000", \ - "0.0286239000, 0.0302343000, 0.0350796000, 0.0480212000, 0.0854013000, 0.1976993000, 0.5466466000", \ - "0.0285983000, 0.0302076000, 0.0351924000, 0.0480932000, 0.0853449000, 0.1977067000, 0.5468306000", \ - "0.0306341000, 0.0321826000, 0.0368233000, 0.0497137000, 0.0864446000, 0.1977003000, 0.5464824000", \ - "0.0425794000, 0.0443376000, 0.0490134000, 0.0608520000, 0.0959906000, 0.2018837000, 0.5467605000", \ - "0.0630570000, 0.0651177000, 0.0706672000, 0.0844930000, 0.1180011000, 0.2153521000, 0.5510397000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0422406000, 0.0459658000, 0.0580660000, 0.0945990000, 0.2031696000, 0.5256226000, 1.5031085000", \ - "0.0420427000, 0.0459607000, 0.0581827000, 0.0946060000, 0.2029671000, 0.5291884000, 1.5010769000", \ - "0.0420246000, 0.0459156000, 0.0581945000, 0.0945860000, 0.2030476000, 0.5286425000, 1.5103013000", \ - "0.0424728000, 0.0462961000, 0.0582186000, 0.0945209000, 0.2033146000, 0.5292978000, 1.4994251000", \ - "0.0447870000, 0.0486678000, 0.0601289000, 0.0961576000, 0.2034014000, 0.5257194000, 1.5056419000", \ - "0.0520946000, 0.0555274000, 0.0662593000, 0.0991636000, 0.2042120000, 0.5262505000, 1.5045626000", \ - "0.0669657000, 0.0708851000, 0.0814653000, 0.1115436000, 0.2079069000, 0.5296706000, 1.4992858000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.1189062000, 0.1208139000, 0.1261325000, 0.1399563000, 0.1744885000, 0.2630015000, 0.5123171000", \ - "0.1234764000, 0.1254135000, 0.1306975000, 0.1445713000, 0.1791093000, 0.2676301000, 0.5169734000", \ - "0.1356297000, 0.1375429000, 0.1430336000, 0.1568785000, 0.1914215000, 0.2798964000, 0.5291669000", \ - "0.1665830000, 0.1684625000, 0.1738022000, 0.1876981000, 0.2222462000, 0.3107422000, 0.5600611000", \ - "0.2354769000, 0.2375193000, 0.2431412000, 0.2574595000, 0.2923023000, 0.3809423000, 0.6304956000", \ - "0.3490713000, 0.3517141000, 0.3586699000, 0.3760468000, 0.4146354000, 0.5065471000, 0.7566323000", \ - "0.5220401000, 0.5257039000, 0.5355615000, 0.5584914000, 0.6062080000, 0.7055356000, 0.9588793000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0727643000, 0.0759409000, 0.0851992000, 0.1116186000, 0.1898807000, 0.4246217000, 1.1328487000", \ - "0.0776097000, 0.0807859000, 0.0900408000, 0.1164746000, 0.1948304000, 0.4292973000, 1.1371117000", \ - "0.0904043000, 0.0937181000, 0.1029870000, 0.1294341000, 0.2078138000, 0.4422940000, 1.1504654000", \ - "0.1174346000, 0.1207617000, 0.1304323000, 0.1574010000, 0.2358815000, 0.4704829000, 1.1781904000", \ - "0.1617965000, 0.1662739000, 0.1785135000, 0.2108924000, 0.2943521000, 0.5294237000, 1.2375584000", \ - "0.2328737000, 0.2393587000, 0.2581854000, 0.3046559000, 0.4125536000, 0.6633363000, 1.3723422000", \ - "0.3258456000, 0.3390380000, 0.3718845000, 0.4509155000, 0.6186218000, 0.9453435000, 1.6831458000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0252141000, 0.0269583000, 0.0320134000, 0.0462804000, 0.0859376000, 0.1997864000, 0.5468370000", \ - "0.0252422000, 0.0269162000, 0.0319978000, 0.0463156000, 0.0859209000, 0.1995933000, 0.5469276000", \ - "0.0252084000, 0.0269061000, 0.0320323000, 0.0462994000, 0.0859208000, 0.1997862000, 0.5465731000", \ - "0.0252751000, 0.0269542000, 0.0320017000, 0.0463345000, 0.0859349000, 0.1997128000, 0.5463727000", \ - "0.0277038000, 0.0292199000, 0.0339768000, 0.0476636000, 0.0865526000, 0.1999364000, 0.5465934000", \ - "0.0387137000, 0.0401606000, 0.0443790000, 0.0567265000, 0.0935733000, 0.2034042000, 0.5469596000", \ - "0.0586960000, 0.0601396000, 0.0643253000, 0.0761723000, 0.1101700000, 0.2141150000, 0.5503721000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0450480000, 0.0486495000, 0.0602175000, 0.0956382000, 0.2033334000, 0.5265582000, 1.5009617000", \ - "0.0450005000, 0.0486565000, 0.0602525000, 0.0954381000, 0.2031271000, 0.5266766000, 1.5011700000", \ - "0.0449539000, 0.0486869000, 0.0603341000, 0.0955500000, 0.2033497000, 0.5256968000, 1.4991928000", \ - "0.0478956000, 0.0514417000, 0.0624041000, 0.0969116000, 0.2035336000, 0.5258388000, 1.5050609000", \ - "0.0616485000, 0.0655273000, 0.0767943000, 0.1102163000, 0.2090838000, 0.5265679000, 1.5020387000", \ - "0.0952977000, 0.0998566000, 0.1133386000, 0.1503275000, 0.2484731000, 0.5387435000, 1.5001536000", \ - "0.1761174000, 0.1820524000, 0.1985246000, 0.2454359000, 0.3538895000, 0.6305567000, 1.5205048000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0515148000, 0.0515718000, 0.0515718000, 0.0515718000, 0.0515718000, 0.0515718000, 0.0515838000", \ - "0.0526181000, 0.0526492000, 0.0527089000, 0.0527167000, 0.0527167000, 0.0527167000, 0.0527167000", \ - "0.0531431000, 0.0531431000, 0.0531543000, 0.0531543000, 0.0531614000, 0.0531614000, 0.0531713000", \ - "0.0484666000, 0.0485498000, 0.0485498000, 0.0485498000, 0.0485498000, 0.0485498000, 0.0485498000", \ - "0.0319229000, 0.0319229000, 0.0319229000, 0.0319229000, 0.0319229000, 0.0319229000, 0.0319229000", \ - "-0.000497100, -0.000497100, -0.000497100, -0.000497100, -0.000497100, -0.000497100, -0.000497100", \ - "-0.068781500, -0.068189100, -0.068189100, -0.068189100, -0.068189100, -0.068189100, -0.068189100"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0102496000, 0.0112606000, 0.0143160000, 0.0235494000, 0.0514532000, 0.1357800000, 0.3906190000"); - values("0.0704614000, 0.0704614000, 0.0704614000, 0.0704980000, 0.0705402000, 0.0705970000, 0.0705970000", \ - "0.0744856000, 0.0748383000, 0.0751300000, 0.0751300000, 0.0751300000, 0.0751300000, 0.0751300000", \ - "0.0844989000, 0.0849757000, 0.0850339000, 0.0850339000, 0.0851557000, 0.0851557000, 0.0855180000", \ - "0.1100318000, 0.1102288000, 0.1104987000, 0.1104987000, 0.1104987000, 0.1104987000, 0.1105077000", \ - "0.1491201000, 0.1491201000, 0.1502300000, 0.1502300000, 0.1502300000, 0.1502300000, 0.1502300000", \ - "0.2014919000, 0.2014919000, 0.2014919000, 0.2014919000, 0.2014919000, 0.2016540000, 0.2016540000", \ - "0.2513325000, 0.2538667000, 0.2538667000, 0.2538667000, 0.2538667000, 0.2538667000, 0.2538667000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__edfxbp_1") { - leakage_power () { - value : 0.0127426000; - when : "CLK&!D&DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0112053000; - when : "CLK&D&!DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0131897000; - when : "!CLK&D&DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0158255000; - when : "CLK&D&DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0121153000; - when : "CLK&!D&!DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0125423000; - when : "!CLK&!D&DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0123302000; - when : "CLK&D&!DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0128187000; - when : "CLK&!D&DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0118388000; - when : "!CLK&!D&!DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0120537000; - when : "!CLK&D&!DE&!Q&Q_N"; - } - leakage_power () { - value : 0.0121129000; - when : "!CLK&!D&!DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125317000; - when : "CLK&!D&!DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136084000; - when : "CLK&D&DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0107865000; - when : "!CLK&D&!DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0122842000; - when : "!CLK&!D&DE&Q&!Q_N"; - } - leakage_power () { - value : 0.0148037000; - when : "!CLK&D&DE&!Q&Q_N"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__edfxbp"; - cell_leakage_power : 0.0126743400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017620000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0256580000, 0.0255449000, 0.0252842000, 0.0253126000, 0.0253780000, 0.0255290000, 0.0258770000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0204122000, 0.0202897000, 0.0200073000, 0.0200111000, 0.0200198000, 0.0200401000, 0.0200868000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018480000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2686506000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3905853000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102961000, 0.0101910000, 0.0099488000, 0.0099944000, 0.0100996000, 0.0103420000, 0.0109010000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039588000, 0.0039190000, 0.0038270000, 0.0038485000, 0.0038979000, 0.0040121000, 0.0042753000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018900000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2424785000, 0.4359518000, 0.7329896000", \ - "0.1149232000, 0.3083965000, 0.6066549000", \ - "0.0156393000, 0.2091126000, 0.5073711000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1204082000, 0.2699362000, 0.4168275000", \ - "0.0563294000, 0.2009746000, 0.3429831000", \ - "0.0290671000, 0.1724915000, 0.3132793000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.166457000, -0.357488900, -0.642319700", \ - "-0.058432900, -0.250685500, -0.540399100", \ - "0.0249818000, -0.164829400, -0.456984400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.100539100, -0.243963600, -0.373765000", \ - "-0.037681000, -0.179884800, -0.313348300", \ - "-0.010418600, -0.152622400, -0.287306600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0032910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112291000, 0.0110891000, 0.0107665000, 0.0108315000, 0.0109813000, 0.0113268000, 0.0121232000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002188000, 6.8164521e-05, -0.000278900, -0.000224900, -0.000100300, 0.0001869000, 0.0008491000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034070000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2302715000, 0.4151999000, 0.7232240000", \ - "0.1149232000, 0.3010723000, 0.6115378000", \ - "0.0241842000, 0.2115540000, 0.5232402000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2803203000, 0.3688132000, 0.4046204000", \ - "0.1527650000, 0.2412578000, 0.2770651000", \ - "0.0534811000, 0.1419740000, 0.1790020000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.161574200, -0.330633500, -0.514145800", \ - "-0.095054000, -0.264113300, -0.447625600", \ - "-0.065350300, -0.233188800, -0.416701200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.113966800, -0.246404900, -0.383530600", \ - "-0.053550100, -0.182326200, -0.317010400", \ - "-0.026287800, -0.157505200, -0.290968800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("-0.006929500, -0.002395500, 0.0059589000, 0.0146229000, 0.0081900000, -0.044226900, -0.209520900", \ - "-0.006873800, -0.002342000, 0.0059842000, 0.0146379000, 0.0081729000, -0.044209400, -0.209585400", \ - "-0.006748500, -0.002243800, 0.0060263000, 0.0146128000, 0.0080395000, -0.044387900, -0.209769200", \ - "-0.006765300, -0.002284200, 0.0059477000, 0.0144520000, 0.0077899000, -0.044697400, -0.210078700", \ - "-0.006793100, -0.002346400, 0.0058096000, 0.0142202000, 0.0074828000, -0.045066600, -0.210497500", \ - "-0.006804300, -0.002353000, 0.0058051000, 0.0142032000, 0.0074237000, -0.045109600, -0.210511500", \ - "-0.006772600, -0.002244200, 0.0060676000, 0.0147185000, 0.0082568000, -0.044470400, -0.209883000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("-0.008202400, -0.005164900, 0.0018274000, 0.0165112000, 0.0464858000, 0.1145092000, 0.2859515000", \ - "-0.008149200, -0.005107500, 0.0018584000, 0.0164942000, 0.0465310000, 0.1146136000, 0.2870988000", \ - "-0.008013500, -0.004994500, 0.0019602000, 0.0165577000, 0.0465190000, 0.1139361000, 0.2871395000", \ - "-0.008040600, -0.005041800, 0.0018421000, 0.0163479000, 0.0461837000, 0.1135227000, 0.2870661000", \ - "-0.008056600, -0.005084500, 0.0017596000, 0.0161909000, 0.0459877000, 0.1133661000, 0.2864100000", \ - "-0.008071400, -0.005106200, 0.0017427000, 0.0161758000, 0.0458874000, 0.1133689000, 0.2851168000", \ - "-0.008023200, -0.004949200, 0.0021090000, 0.0167964000, 0.0465088000, 0.1142776000, 0.2849662000"); - } - } - max_capacitance : 0.1702980000; - max_transition : 1.4984530000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.3217189000, 0.3336975000, 0.3583564000, 0.4044817000, 0.4892736000, 0.6468821000, 0.9991500000", \ - "0.3263919000, 0.3383674000, 0.3629856000, 0.4091685000, 0.4939322000, 0.6515138000, 1.0041071000", \ - "0.3373373000, 0.3493088000, 0.3739395000, 0.4201018000, 0.5048688000, 0.6624822000, 1.0148774000", \ - "0.3625368000, 0.3748140000, 0.3995834000, 0.4455818000, 0.5303082000, 0.6879329000, 1.0403499000", \ - "0.4110341000, 0.4229999000, 0.4475999000, 0.4937276000, 0.5784783000, 0.7360995000, 1.0884883000", \ - "0.4847481000, 0.4967635000, 0.5213779000, 0.5674292000, 0.6522664000, 0.8099217000, 1.1622717000", \ - "0.5826212000, 0.5946678000, 0.6192361000, 0.6654232000, 0.7501788000, 0.9078957000, 1.2601907000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.2823183000, 0.2910784000, 0.3104198000, 0.3527374000, 0.4535365000, 0.7020418000, 1.3516106000", \ - "0.2868320000, 0.2956442000, 0.3149213000, 0.3572723000, 0.4580504000, 0.7064329000, 1.3521362000", \ - "0.2981184000, 0.3068666000, 0.3261914000, 0.3685036000, 0.4693329000, 0.7177311000, 1.3637056000", \ - "0.3237113000, 0.3326306000, 0.3518872000, 0.3942083000, 0.4950327000, 0.7434782000, 1.3896153000", \ - "0.3733213000, 0.3821359000, 0.4014430000, 0.4437737000, 0.5445653000, 0.7933027000, 1.4425952000", \ - "0.4452942000, 0.4542076000, 0.4734811000, 0.5157928000, 0.6165841000, 0.8650629000, 1.5143025000", \ - "0.5371678000, 0.5460978000, 0.5654340000, 0.6077733000, 0.7085959000, 0.9570627000, 1.5999471000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0499827000, 0.0575455000, 0.0746834000, 0.1060127000, 0.1733747000, 0.3236314000, 0.7585302000", \ - "0.0500336000, 0.0575675000, 0.0747087000, 0.1059332000, 0.1733465000, 0.3238485000, 0.7575736000", \ - "0.0500101000, 0.0575530000, 0.0746939000, 0.1059576000, 0.1733518000, 0.3246101000, 0.7582023000", \ - "0.0496562000, 0.0575239000, 0.0744921000, 0.1061559000, 0.1732540000, 0.3239511000, 0.7583262000", \ - "0.0500096000, 0.0575519000, 0.0746724000, 0.1059468000, 0.1733569000, 0.3246310000, 0.7582613000", \ - "0.0502422000, 0.0583342000, 0.0736246000, 0.1062319000, 0.1731890000, 0.3239933000, 0.7585104000", \ - "0.0499849000, 0.0585182000, 0.0739026000, 0.1065920000, 0.1734083000, 0.3248802000, 0.7570495000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0312680000, 0.0388242000, 0.0578550000, 0.1070535000, 0.2374456000, 0.5777822000, 1.4973958000", \ - "0.0312399000, 0.0389251000, 0.0577928000, 0.1069214000, 0.2372066000, 0.5780185000, 1.4966571000", \ - "0.0310827000, 0.0389539000, 0.0578418000, 0.1070324000, 0.2373415000, 0.5767917000, 1.4981897000", \ - "0.0312988000, 0.0390185000, 0.0579134000, 0.1069531000, 0.2372824000, 0.5773564000, 1.4955094000", \ - "0.0312947000, 0.0388917000, 0.0577574000, 0.1069891000, 0.2372690000, 0.5766687000, 1.4984530000", \ - "0.0313153000, 0.0390150000, 0.0579253000, 0.1068882000, 0.2373339000, 0.5776462000, 1.4954221000", \ - "0.0314168000, 0.0391304000, 0.0580809000, 0.1068841000, 0.2374438000, 0.5764365000, 1.4906509000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.006741300, -0.001934100, 0.0069701000, 0.0164931000, 0.0111782000, -0.040392400, -0.203597400", \ - "-0.006684600, -0.001890500, 0.0069957000, 0.0164911000, 0.0111510000, -0.040463800, -0.203676500", \ - "-0.006551300, -0.001764300, 0.0070996000, 0.0165542000, 0.0112021000, -0.040417600, -0.203634300", \ - "-0.006576000, -0.001821300, 0.0069758000, 0.0163452000, 0.0108883000, -0.040807000, -0.204073300", \ - "-0.006594400, -0.001864000, 0.0068880000, 0.0161863000, 0.0106736000, -0.041066300, -0.204332700", \ - "-0.006608100, -0.001879500, 0.0068685000, 0.0161663000, 0.0106155000, -0.041119700, -0.204395800", \ - "-0.006569200, -0.001748900, 0.0071833000, 0.0167937000, 0.0113079000, -0.040500400, -0.203712400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.008462600, -0.005761200, 0.0006941000, 0.0146118000, 0.0435472000, 0.1099825000, 0.2790310000", \ - "-0.008407200, -0.005710700, 0.0007187000, 0.0146358000, 0.0436505000, 0.1103800000, 0.2792140000", \ - "-0.008282100, -0.005610700, 0.0007693000, 0.0146127000, 0.0434174000, 0.1098385000, 0.2799694000", \ - "-0.008302400, -0.005653700, 0.0006785000, 0.0144514000, 0.0431886000, 0.1095296000, 0.2790957000", \ - "-0.008329400, -0.005718500, 0.0005455000, 0.0141995000, 0.0428253000, 0.1096069000, 0.2795428000", \ - "-0.008345600, -0.005737900, 0.0005159000, 0.0141565000, 0.0427845000, 0.1095918000, 0.2796186000", \ - "-0.008215500, -0.005429000, 0.0010222000, 0.0147127000, 0.0434669000, 0.1096287000, 0.2789439000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.4949190000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3962148000, 0.4036043000, 0.4189342000, 0.4489137000, 0.5085441000, 0.6440243000, 0.9938235000", \ - "0.4007700000, 0.4081425000, 0.4234719000, 0.4534562000, 0.5130896000, 0.6486962000, 0.9983581000", \ - "0.4120232000, 0.4193934000, 0.4348019000, 0.4647019000, 0.5242884000, 0.6599433000, 1.0091261000", \ - "0.4377422000, 0.4451549000, 0.4605252000, 0.4904214000, 0.5500186000, 0.6855614000, 1.0345693000", \ - "0.4873270000, 0.4946930000, 0.5101164000, 0.5400105000, 0.5996144000, 0.7352267000, 1.0841886000", \ - "0.5593701000, 0.5667865000, 0.5821579000, 0.6120597000, 0.6717096000, 0.8073301000, 1.1569520000", \ - "0.6512507000, 0.6586519000, 0.6740239000, 0.7039246000, 0.7635196000, 0.8991364000, 1.2476274000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4750195000, 0.4839513000, 0.5029261000, 0.5431098000, 0.6378163000, 0.8825055000, 1.5248514000", \ - "0.4796624000, 0.4885997000, 0.5075755000, 0.5477572000, 0.6425928000, 0.8872461000, 1.5303080000", \ - "0.4905997000, 0.4995415000, 0.5185148000, 0.5586994000, 0.6535339000, 0.8981914000, 1.5401714000", \ - "0.5160836000, 0.5250712000, 0.5440608000, 0.5842530000, 0.6791069000, 0.9237331000, 1.5664011000", \ - "0.5643523000, 0.5732848000, 0.5923002000, 0.6324140000, 0.7271582000, 0.9717490000, 1.6159096000", \ - "0.6380630000, 0.6470108000, 0.6660565000, 0.7061882000, 0.8009348000, 1.0455712000, 1.6898494000", \ - "0.7357803000, 0.7447108000, 0.7637376000, 0.8038459000, 0.8987081000, 1.1433521000, 1.7860948000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0283745000, 0.0330160000, 0.0440385000, 0.0692142000, 0.1294071000, 0.2971669000, 0.7547974000", \ - "0.0284135000, 0.0329843000, 0.0439664000, 0.0692081000, 0.1298256000, 0.2961581000, 0.7569029000", \ - "0.0282375000, 0.0330417000, 0.0442019000, 0.0692327000, 0.1297196000, 0.2972554000, 0.7587491000", \ - "0.0282393000, 0.0330899000, 0.0445220000, 0.0686691000, 0.1297468000, 0.2966983000, 0.7628781000", \ - "0.0282140000, 0.0330283000, 0.0440641000, 0.0691648000, 0.1298369000, 0.2960965000, 0.7533063000", \ - "0.0282135000, 0.0330943000, 0.0438858000, 0.0692673000, 0.1296146000, 0.2956163000, 0.7549782000", \ - "0.0283016000, 0.0334619000, 0.0440052000, 0.0688266000, 0.1298533000, 0.2967055000, 0.7597079000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0356551000, 0.0422072000, 0.0586686000, 0.1030157000, 0.2299886000, 0.5742322000, 1.4939970000", \ - "0.0356607000, 0.0422046000, 0.0586738000, 0.1031621000, 0.2293182000, 0.5751381000, 1.4888278000", \ - "0.0356641000, 0.0422023000, 0.0586769000, 0.1031620000, 0.2293526000, 0.5743556000, 1.4913681000", \ - "0.0356120000, 0.0423121000, 0.0585868000, 0.1031435000, 0.2296468000, 0.5749601000, 1.4895787000", \ - "0.0356337000, 0.0422124000, 0.0586957000, 0.1030394000, 0.2300129000, 0.5750660000, 1.4948914000", \ - "0.0356991000, 0.0421889000, 0.0586596000, 0.1031379000, 0.2300035000, 0.5751582000, 1.4949189000", \ - "0.0357735000, 0.0422661000, 0.0587721000, 0.1030359000, 0.2298721000, 0.5736977000, 1.4943413000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__edfxtp_1") { - leakage_power () { - value : 0.0071886000; - when : "CLK&!D&DE&Q"; - } - leakage_power () { - value : 0.0056513000; - when : "CLK&D&!DE&Q"; - } - leakage_power () { - value : 0.0078692000; - when : "!CLK&D&DE&Q"; - } - leakage_power () { - value : 0.0155372000; - when : "CLK&D&DE&!Q"; - } - leakage_power () { - value : 0.0118270000; - when : "CLK&!D&!DE&!Q"; - } - leakage_power () { - value : 0.0121521000; - when : "!CLK&!D&DE&!Q"; - } - leakage_power () { - value : 0.0120419000; - when : "CLK&D&!DE&!Q"; - } - leakage_power () { - value : 0.0125305000; - when : "CLK&!D&DE&!Q"; - } - leakage_power () { - value : 0.0114487000; - when : "!CLK&!D&!DE&!Q"; - } - leakage_power () { - value : 0.0116635000; - when : "!CLK&D&!DE&!Q"; - } - leakage_power () { - value : 0.0067925000; - when : "!CLK&!D&!DE&Q"; - } - leakage_power () { - value : 0.0069777000; - when : "CLK&!D&!DE&Q"; - } - leakage_power () { - value : 0.0080545000; - when : "CLK&D&DE&Q"; - } - leakage_power () { - value : 0.0054661000; - when : "!CLK&D&!DE&Q"; - } - leakage_power () { - value : 0.0069917000; - when : "!CLK&!D&DE&Q"; - } - leakage_power () { - value : 0.0143995000; - when : "!CLK&D&DE&!Q"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__edfxtp"; - cell_leakage_power : 0.0097870060; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017580000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0256916000, 0.0255763000, 0.0253103000, 0.0253385000, 0.0254036000, 0.0255534000, 0.0258989000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0204057000, 0.0202831000, 0.0200006000, 0.0200042000, 0.0200125000, 0.0200316000, 0.0200759000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018410000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2697491000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3774032000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103110000, 0.0102009000, 0.0099473000, 0.0100251000, 0.0102043000, 0.0106177000, 0.0115706000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039593000, 0.0039181000, 0.0038231000, 0.0038449000, 0.0038951000, 0.0040107000, 0.0042774000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018900000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2436992000, 0.4359518000, 0.7342103000", \ - "0.1161439000, 0.3096172000, 0.6078756000", \ - "0.0168600000, 0.2103333000, 0.5073711000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1204082000, 0.2699362000, 0.4168275000", \ - "0.0563294000, 0.2009746000, 0.3429831000", \ - "0.0290671000, 0.1737122000, 0.3132793000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.166457000, -0.357488900, -0.642319700", \ - "-0.058432900, -0.250685500, -0.540399100", \ - "0.0249818000, -0.166050100, -0.456984400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.100539100, -0.243963600, -0.373765000", \ - "-0.038901700, -0.179884800, -0.313348300", \ - "-0.011639300, -0.151401700, -0.287306600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0032900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112241000, 0.0110907000, 0.0107832000, 0.0108475000, 0.0109954000, 0.0113366000, 0.0121231000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002081000, 6.0104447e-05, -0.000281000, -0.000225100, -9.6229256e-05, 0.0002009000, 0.0008858000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034080000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2290508000, 0.4151999000, 0.7232240000", \ - "0.1149232000, 0.3010723000, 0.6115378000", \ - "0.0241842000, 0.2115540000, 0.5232402000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2815410000, 0.3700339000, 0.4058412000", \ - "0.1539857000, 0.2424785000, 0.2782858000", \ - "0.0547018000, 0.1431947000, 0.1802227000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.162794900, -0.330633500, -0.514145800", \ - "-0.096274700, -0.264113300, -0.448846400", \ - "-0.065350300, -0.233188800, -0.417921900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.113966800, -0.246404900, -0.383530600", \ - "-0.053550100, -0.183546900, -0.317010400", \ - "-0.027508500, -0.157505200, -0.292189500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("0.0172870000, 0.0160180000, 0.0128391000, 0.0058581000, -0.017028100, -0.081619700, -0.253928900", \ - "0.0173175000, 0.0160422000, 0.0128681000, 0.0058548000, -0.016965000, -0.081592900, -0.253900200", \ - "0.0172659000, 0.0159954000, 0.0128094000, 0.0057905000, -0.017031900, -0.081647600, -0.253955000", \ - "0.0169529000, 0.0156798000, 0.0125033000, 0.0054759000, -0.017358700, -0.081978300, -0.254291300", \ - "0.0165107000, 0.0152260000, 0.0120467000, 0.0050308000, -0.017820700, -0.082426300, -0.254728000", \ - "0.0165168000, 0.0152289000, 0.0120406000, 0.0050095000, -0.017821900, -0.082429700, -0.254732900", \ - "0.0217179000, 0.0203634000, 0.0168343000, 0.0076207000, -0.016794200, -0.081791500, -0.254077800"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("0.0242104000, 0.0256414000, 0.0296990000, 0.0395823000, 0.0642621000, 0.1287503000, 0.2996621000", \ - "0.0241791000, 0.0256825000, 0.0296773000, 0.0395592000, 0.0640960000, 0.1289117000, 0.2996894000", \ - "0.0242819000, 0.0257888000, 0.0297936000, 0.0397053000, 0.0642361000, 0.1294583000, 0.3000686000", \ - "0.0238707000, 0.0253661000, 0.0294077000, 0.0392642000, 0.0638206000, 0.1282804000, 0.2993990000", \ - "0.0235855000, 0.0251118000, 0.0291140000, 0.0389645000, 0.0636861000, 0.1279982000, 0.3003813000", \ - "0.0234679000, 0.0249796000, 0.0290034000, 0.0389029000, 0.0634576000, 0.1279425000, 0.2990317000", \ - "0.0254896000, 0.0268487000, 0.0304913000, 0.0399566000, 0.0643076000, 0.1290380000, 0.2991003000"); - } - } - max_capacitance : 0.1712140000; - max_transition : 1.5031540000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.3099280000, 0.3221374000, 0.3466937000, 0.3932877000, 0.4779282000, 0.6326026000, 0.9846171000", \ - "0.3148012000, 0.3268097000, 0.3513814000, 0.3979988000, 0.4826108000, 0.6373044000, 0.9889901000", \ - "0.3257958000, 0.3377864000, 0.3623443000, 0.4089450000, 0.4936611000, 0.6482576000, 1.0000328000", \ - "0.3513822000, 0.3632530000, 0.3878383000, 0.4343881000, 0.5190627000, 0.6737094000, 1.0255232000", \ - "0.3992665000, 0.4114660000, 0.4359951000, 0.4825639000, 0.5671517000, 0.7218533000, 1.0737011000", \ - "0.4730780000, 0.4849802000, 0.5096580000, 0.5561505000, 0.6408862000, 0.7955479000, 1.1472624000", \ - "0.5707111000, 0.5825300000, 0.6072938000, 0.6537462000, 0.7384788000, 0.8932239000, 1.2449580000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.2785875000, 0.2872594000, 0.3065269000, 0.3488984000, 0.4483747000, 0.6941020000, 1.3408512000", \ - "0.2830593000, 0.2917884000, 0.3110265000, 0.3534442000, 0.4529059000, 0.6988628000, 1.3481820000", \ - "0.2942504000, 0.3030820000, 0.3222734000, 0.3646696000, 0.4641351000, 0.7101550000, 1.3598392000", \ - "0.3199537000, 0.3287403000, 0.3479609000, 0.3903745000, 0.4898191000, 0.7355246000, 1.3822651000", \ - "0.3694574000, 0.3782727000, 0.3974567000, 0.4398711000, 0.5393059000, 0.7850510000, 1.4305418000", \ - "0.4411518000, 0.4499820000, 0.4691814000, 0.5115814000, 0.6110322000, 0.8567729000, 1.5034124000", \ - "0.5330731000, 0.5419730000, 0.5611839000, 0.6035324000, 0.7029838000, 0.9490192000, 1.5970022000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0487779000, 0.0566241000, 0.0732113000, 0.1066450000, 0.1712743000, 0.3213445000, 0.7573487000", \ - "0.0492711000, 0.0565550000, 0.0732603000, 0.1067845000, 0.1711078000, 0.3204375000, 0.7581102000", \ - "0.0491633000, 0.0565642000, 0.0732277000, 0.1067560000, 0.1707291000, 0.3206773000, 0.7581724000", \ - "0.0487556000, 0.0567983000, 0.0738642000, 0.1065978000, 0.1711504000, 0.3207294000, 0.7580823000", \ - "0.0487718000, 0.0565747000, 0.0731876000, 0.1067629000, 0.1711434000, 0.3215941000, 0.7578473000", \ - "0.0491616000, 0.0567660000, 0.0734814000, 0.1068278000, 0.1714701000, 0.3212108000, 0.7582407000", \ - "0.0497381000, 0.0571786000, 0.0739441000, 0.1071614000, 0.1712526000, 0.3207271000, 0.7578772000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0305865000, 0.0381082000, 0.0571859000, 0.1062868000, 0.2326004000, 0.5750624000, 1.5010133000", \ - "0.0306274000, 0.0381330000, 0.0572092000, 0.1063347000, 0.2328817000, 0.5747631000, 1.5021699000", \ - "0.0307567000, 0.0382994000, 0.0571682000, 0.1062032000, 0.2327943000, 0.5755469000, 1.4990825000", \ - "0.0305465000, 0.0383623000, 0.0573192000, 0.1062706000, 0.2330121000, 0.5757505000, 1.4981597000", \ - "0.0306293000, 0.0383752000, 0.0572888000, 0.1062748000, 0.2330058000, 0.5757485000, 1.5031536000", \ - "0.0308372000, 0.0383322000, 0.0570891000, 0.1061633000, 0.2330378000, 0.5758346000, 1.4983690000", \ - "0.0307581000, 0.0384567000, 0.0572184000, 0.1063175000, 0.2330270000, 0.5742254000, 1.4988364000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - } - - cell ("sky130_fd_sc_hd__einvn_0") { - leakage_power () { - value : 0.0009360000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0007048000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0010045000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0021564000; - when : "A&!TE_B"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__einvn"; - cell_leakage_power : 0.0012004280; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0018180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020636000, 0.0020629000, 0.0020612000, 0.0020637000, 0.0020692000, 0.0020821000, 0.0021116000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001820900, -0.001819000, -0.001814700, -0.001812100, -0.001806300, -0.001792800, -0.001761600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019040000; - } - pin ("TE_B") { - capacitance : 0.0024830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023240000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026420000; - } - pin ("Z") { - capacitance : 0.0014550000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0005489000, -0.000294300, -0.002218900, -0.006512200, -0.015879300, -0.036142200, -0.079885000", \ - "0.0004036000, -0.000412000, -0.002287600, -0.006533200, -0.015863900, -0.036111600, -0.079850600", \ - "0.0001908000, -0.000618500, -0.002454300, -0.006623500, -0.015910400, -0.036121900, -0.079847100", \ - "1.580000e-05, -0.000823700, -0.002659100, -0.006829300, -0.016037000, -0.036182000, -0.079877900", \ - "9.200000e-06, -0.000866400, -0.002844600, -0.007058700, -0.016246900, -0.036303000, -0.079930200", \ - "0.0003516000, -0.000615600, -0.002650300, -0.006923000, -0.016234200, -0.036390900, -0.079998800", \ - "0.0015872000, 0.0003353000, -0.001830300, -0.006082500, -0.015989600, -0.036368900, -0.080123100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0048943000, 0.0059500000, 0.0080645000, 0.0124799000, 0.0218288000, 0.0418925000, 0.0850413000", \ - "0.0046603000, 0.0056907000, 0.0078742000, 0.0123686000, 0.0217626000, 0.0418556000, 0.0855263000", \ - "0.0044658000, 0.0054888000, 0.0076483000, 0.0120894000, 0.0216029000, 0.0417735000, 0.0850524000", \ - "0.0043467000, 0.0053351000, 0.0073925000, 0.0118801000, 0.0213643000, 0.0419047000, 0.0856035000", \ - "0.0044141000, 0.0053345000, 0.0074265000, 0.0117118000, 0.0211530000, 0.0413215000, 0.0853593000", \ - "0.0047988000, 0.0057014000, 0.0078165000, 0.0119900000, 0.0213551000, 0.0413133000, 0.0844849000", \ - "0.0055782000, 0.0064299000, 0.0082382000, 0.0125762000, 0.0217115000, 0.0414263000, 0.0846002000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("-0.002185400, -0.002191100, -0.002143300, -0.002092600, -0.002012800, -0.001984800, -0.001970800", \ - "-0.002368800, -0.002334100, -0.002287000, -0.002235400, -0.002196000, -0.002165600, -0.002151700", \ - "-0.002621100, -0.002585900, -0.002532800, -0.002476300, -0.002423300, -0.002387100, -0.002366900", \ - "-0.002865700, -0.002835400, -0.002784200, -0.002709100, -0.002637800, -0.002584100, -0.002552400", \ - "-0.003012900, -0.002938100, -0.002896400, -0.002825000, -0.002733000, -0.002702800, -0.002646000", \ - "-0.002855000, -0.002853300, -0.002826100, -0.002794100, -0.002717700, -0.002613700, -0.002493100", \ - "-0.001967400, -0.001970700, -0.001971600, -0.001966700, -0.001936000, -0.001862300, -0.001762200"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0144364000, 0.0153513000, 0.0173533000, 0.0216705000, 0.0310032000, 0.0511954000, 0.0941869000", \ - "0.0142334000, 0.0151533000, 0.0171580000, 0.0214696000, 0.0307716000, 0.0508064000, 0.0940388000", \ - "0.0140821000, 0.0150031000, 0.0170057000, 0.0213153000, 0.0306288000, 0.0506464000, 0.0940185000", \ - "0.0140161000, 0.0149376000, 0.0169400000, 0.0212481000, 0.0305659000, 0.0506249000, 0.0938889000", \ - "0.0140663000, 0.0149999000, 0.0169825000, 0.0212864000, 0.0306121000, 0.0506174000, 0.0944718000", \ - "0.0139676000, 0.0152121000, 0.0172781000, 0.0215913000, 0.0308411000, 0.0509774000, 0.0945896000", \ - "0.0148368000, 0.0157469000, 0.0177457000, 0.0220107000, 0.0317633000, 0.0516606000, 0.0950925000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0113917000, 0.0104992000, 0.0085202000, 0.0041829000, -0.005224300, -0.025509200, -0.069273800", \ - "0.0111910000, 0.0102982000, 0.0083198000, 0.0039792000, -0.005420500, -0.025706200, -0.069472900", \ - "0.0110444000, 0.0101565000, 0.0081754000, 0.0038350000, -0.005563100, -0.025847300, -0.069616800", \ - "0.0109789000, 0.0100925000, 0.0081115000, 0.0037719000, -0.005628200, -0.025915800, -0.069673600", \ - "0.0109656000, 0.0101113000, 0.0081526000, 0.0038097000, -0.005575700, -0.025870500, -0.069616200", \ - "0.0110610000, 0.0100876000, 0.0080951000, 0.0036769000, -0.005316200, -0.025613600, -0.069358400", \ - "0.0118918000, 0.0109603000, 0.0089280000, 0.0045622000, -0.004846600, -0.024871700, -0.068539000"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("-0.002529700, -0.002537200, -0.002553600, -0.002572100, -0.002586300, -0.002594000, -0.002598800", \ - "-0.002760100, -0.002770500, -0.002787200, -0.002803800, -0.002817300, -0.002825600, -0.002828900", \ - "-0.002989600, -0.003002200, -0.003020200, -0.003040600, -0.003057800, -0.003068000, -0.003070800", \ - "-0.003192700, -0.003205300, -0.003220600, -0.003236800, -0.003251000, -0.003261100, -0.003266400", \ - "-0.003246900, -0.003252100, -0.003283900, -0.003275700, -0.003287600, -0.003296100, -0.003301100", \ - "-0.003099300, -0.003102500, -0.003064900, -0.003084100, -0.003095500, -0.003097500, -0.003102500", \ - "-0.002207900, -0.002216100, -0.002228900, -0.002239900, -0.002286900, -0.002262600, -0.002259000"); - } - when : "A"; - } - max_capacitance : 0.0503640000; - max_transition : 1.4870300000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0284043000, 0.0338038000, 0.0449326000, 0.0685895000, 0.1188956000, 0.2272472000, 0.4597925000", \ - "0.0325230000, 0.0378693000, 0.0492588000, 0.0731798000, 0.1236699000, 0.2321799000, 0.4647751000", \ - "0.0424935000, 0.0481945000, 0.0596993000, 0.0834387000, 0.1342459000, 0.2428553000, 0.4765810000", \ - "0.0566408000, 0.0656941000, 0.0815479000, 0.1082739000, 0.1590005000, 0.2676178000, 0.5037111000", \ - "0.0724068000, 0.0860723000, 0.1108189000, 0.1517134000, 0.2161433000, 0.3229872000, 0.5564805000", \ - "0.0840767000, 0.1051971000, 0.1429858000, 0.2052297000, 0.3021403000, 0.4542202000, 0.6903698000", \ - "0.0757059000, 0.1072285000, 0.1646493000, 0.2593399000, 0.4113580000, 0.6401622000, 0.9817854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0570526000, 0.0706554000, 0.0974758000, 0.1537119000, 0.2729434000, 0.5283765000, 1.0801402000", \ - "0.0592669000, 0.0723974000, 0.1001352000, 0.1572178000, 0.2769427000, 0.5330532000, 1.0959360000", \ - "0.0691013000, 0.0819745000, 0.1095140000, 0.1659059000, 0.2867168000, 0.5435641000, 1.0940939000", \ - "0.0958521000, 0.1085197000, 0.1344850000, 0.1915003000, 0.3124355000, 0.5726017000, 1.1280177000", \ - "0.1397160000, 0.1597030000, 0.1957315000, 0.2551847000, 0.3753546000, 0.6319747000, 1.1889657000", \ - "0.2071691000, 0.2377512000, 0.2927277000, 0.3823683000, 0.5258017000, 0.7809564000, 1.3305356000", \ - "0.3165062000, 0.3599909000, 0.4392482000, 0.5763261000, 0.7942654000, 1.1282733000, 1.6792517000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0206654000, 0.0274927000, 0.0421300000, 0.0734008000, 0.1410442000, 0.2854789000, 0.5988126000", \ - "0.0206597000, 0.0274914000, 0.0421063000, 0.0734224000, 0.1409522000, 0.2853747000, 0.5984890000", \ - "0.0237508000, 0.0292810000, 0.0425373000, 0.0734131000, 0.1401713000, 0.2874077000, 0.5960687000", \ - "0.0367034000, 0.0431282000, 0.0547126000, 0.0792690000, 0.1415789000, 0.2869457000, 0.5977345000", \ - "0.0600366000, 0.0697581000, 0.0850687000, 0.1130177000, 0.1633297000, 0.2905206000, 0.5957784000", \ - "0.1015202000, 0.1152239000, 0.1389446000, 0.1794399000, 0.2458808000, 0.3593310000, 0.6157063000", \ - "0.1737197000, 0.1957533000, 0.2329048000, 0.2939970000, 0.3883118000, 0.5343554000, 0.7858736000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0537785000, 0.0701398000, 0.1051925000, 0.1809336000, 0.3440705000, 0.6961860000, 1.4561158000", \ - "0.0537568000, 0.0702156000, 0.1056290000, 0.1813027000, 0.3442133000, 0.6962028000, 1.4706470000", \ - "0.0534304000, 0.0700819000, 0.1055473000, 0.1808784000, 0.3444222000, 0.6978449000, 1.4562119000", \ - "0.0630141000, 0.0758470000, 0.1070816000, 0.1814687000, 0.3451506000, 0.7008551000, 1.4677298000", \ - "0.0930649000, 0.1087024000, 0.1370023000, 0.1943555000, 0.3456139000, 0.6954730000, 1.4655812000", \ - "0.1418942000, 0.1636298000, 0.2031425000, 0.2697584000, 0.3938807000, 0.7057718000, 1.4615493000", \ - "0.2207537000, 0.2508641000, 0.3108278000, 0.4107727000, 0.5673430000, 0.8289661000, 1.4870297000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0854003000, 0.0911555000, 0.1029590000, 0.1270520000, 0.1774952000, 0.2855188000, 0.5199159000", \ - "0.0896729000, 0.0954188000, 0.1071940000, 0.1312931000, 0.1817314000, 0.2896807000, 0.5225500000", \ - "0.1024009000, 0.1082045000, 0.1199894000, 0.1440790000, 0.1945341000, 0.3026909000, 0.5368064000", \ - "0.1342004000, 0.1400313000, 0.1518259000, 0.1759324000, 0.2263909000, 0.3345688000, 0.5690391000", \ - "0.1916462000, 0.1980350000, 0.2104552000, 0.2352949000, 0.2861235000, 0.3940993000, 0.6285885000", \ - "0.2811113000, 0.2889275000, 0.3035532000, 0.3292124000, 0.3812491000, 0.4898076000, 0.7229173000", \ - "0.4246848000, 0.4343960000, 0.4517217000, 0.4817828000, 0.5366159000, 0.6459769000, 0.8793961000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0587631000, 0.0707896000, 0.0966960000, 0.1517770000, 0.2702829000, 0.5273164000, 1.0774378000", \ - "0.0647694000, 0.0767784000, 0.1026312000, 0.1577477000, 0.2760638000, 0.5310608000, 1.0810381000", \ - "0.0780445000, 0.0900742000, 0.1159543000, 0.1710289000, 0.2892544000, 0.5443605000, 1.1039281000", \ - "0.1049192000, 0.1174116000, 0.1433455000, 0.1984739000, 0.3166971000, 0.5726088000, 1.1242609000", \ - "0.1508798000, 0.1675352000, 0.1995279000, 0.2586972000, 0.3774126000, 0.6324491000, 1.1873929000", \ - "0.2211663000, 0.2478691000, 0.2943305000, 0.3755725000, 0.5133070000, 0.7709824000, 1.3269484000", \ - "0.3112168000, 0.3566716000, 0.4361298000, 0.5646542000, 0.7622603000, 1.0784339000, 1.6415178000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0251722000, 0.0316519000, 0.0455756000, 0.0753880000, 0.1413673000, 0.2862802000, 0.5971122000", \ - "0.0251575000, 0.0316371000, 0.0454687000, 0.0754338000, 0.1413296000, 0.2856581000, 0.5971549000", \ - "0.0252109000, 0.0316591000, 0.0455402000, 0.0753512000, 0.1410222000, 0.2867134000, 0.5973029000", \ - "0.0253180000, 0.0317526000, 0.0456009000, 0.0754373000, 0.1409790000, 0.2870741000, 0.5966532000", \ - "0.0286797000, 0.0348965000, 0.0481101000, 0.0771889000, 0.1420197000, 0.2857339000, 0.6050057000", \ - "0.0357935000, 0.0416465000, 0.0546346000, 0.0823018000, 0.1446664000, 0.2857844000, 0.5976213000", \ - "0.0483899000, 0.0544474000, 0.0665042000, 0.0925880000, 0.1507632000, 0.2881757000, 0.6007117000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0543557000, 0.0708485000, 0.1060058000, 0.1812735000, 0.3447886000, 0.6987172000, 1.4584712000", \ - "0.0543882000, 0.0708201000, 0.1059487000, 0.1812379000, 0.3441647000, 0.6951593000, 1.4568634000", \ - "0.0545847000, 0.0709253000, 0.1059887000, 0.1815761000, 0.3438122000, 0.6985618000, 1.4616421000", \ - "0.0591242000, 0.0741683000, 0.1072446000, 0.1814128000, 0.3442741000, 0.6980708000, 1.4591101000", \ - "0.0799734000, 0.0946295000, 0.1239972000, 0.1902241000, 0.3454918000, 0.6981148000, 1.4668849000", \ - "0.1266352000, 0.1431645000, 0.1773417000, 0.2410972000, 0.3746941000, 0.7026754000, 1.4657763000", \ - "0.2214355000, 0.2448825000, 0.2870759000, 0.3621575000, 0.5033760000, 0.7861724000, 1.4780958000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0158969000, 0.0158979000, 0.0158979000, 0.0159332000, 0.0159742000, 0.0159742000, 0.0159742000", \ - "0.0169538000, 0.0169570000, 0.0169662000, 0.0169741000, 0.0169741000, 0.0169742000, 0.0170780000", \ - "0.0178224000, 0.0178224000, 0.0178224000, 0.0178224000, 0.0178224000, 0.0178224000, 0.0178335000", \ - "0.0147759000, 0.0147768000, 0.0147915000, 0.0147961000, 0.0147999000, 0.0147999000, 0.0147999000", \ - "0.0045613000, 0.0045613000, 0.0045626000, 0.0045626000, 0.0045626000, 0.0045626000, 0.0045626000", \ - "-0.021781800, -0.021781800, -0.021781800, -0.021781800, -0.021781800, -0.021781800, -0.021746700", \ - "-0.083428400, -0.083386800, -0.083347300, -0.083324200, -0.083324200, -0.083324200, -0.083324200"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0019552000, 0.0025337200, 0.0037816100, 0.0064733700, 0.0122796000, 0.0248038000, 0.0518192000"); - values("0.0342787000, 0.0342787000, 0.0342787000, 0.0342787000, 0.0342797000, 0.0342797000, 0.0342797000", \ - "0.0396563000, 0.0397050000, 0.0397050000, 0.0397050000, 0.0397050000, 0.0397050000, 0.0397050000", \ - "0.0508512000, 0.0508654000, 0.0508832000, 0.0508832000, 0.0509715000, 0.0509715000, 0.0509715000", \ - "0.0662884000, 0.0662884000, 0.0662884000, 0.0662884000, 0.0662884000, 0.0662884000, 0.0664515000", \ - "0.0803440000, 0.0803699000, 0.0804289000, 0.0805491000, 0.0805491000, 0.0805491000, 0.0806338000", \ - "0.0920456000, 0.0920470000, 0.0920499000, 0.0920499000, 0.0920499000, 0.0920499000, 0.0920499000", \ - "0.0843090000, 0.0843146000, 0.0843196000, 0.0843196000, 0.0843196000, 0.0843196000, 0.0843196000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvn_1") { - leakage_power () { - value : 0.0014787000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0006894000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0015444000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0030638000; - when : "A&!TE_B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__einvn"; - cell_leakage_power : 0.0016940850; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032792000, 0.0032737000, 0.0032611000, 0.0032680000, 0.0032840000, 0.0033208000, 0.0034057000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002454400, -0.002459600, -0.002471700, -0.002469300, -0.002463700, -0.002450800, -0.002421200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025150000; - } - pin ("TE_B") { - capacitance : 0.0030030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0027780000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0032290000; - } - pin ("Z") { - capacitance : 0.0019930000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0011716000, 0.0002426000, -0.002019200, -0.007464500, -0.020233000, -0.049717300, -0.117632800", \ - "0.0009814000, 7.890000e-05, -0.002126400, -0.007493400, -0.020184600, -0.049651100, -0.117533800", \ - "0.0007503000, -0.000146900, -0.002335400, -0.007621100, -0.020230300, -0.049627900, -0.117473300", \ - "0.0005531000, -0.000418000, -0.002602900, -0.007890400, -0.020410900, -0.049711000, -0.117511500", \ - "0.0005602000, -0.000477800, -0.002701900, -0.008139700, -0.020676700, -0.049892300, -0.117596200", \ - "0.0013025000, 0.0001723000, -0.002347400, -0.007824200, -0.020823600, -0.049941800, -0.117646400", \ - "0.0031134000, 0.0018873000, -0.000860900, -0.006811700, -0.019991600, -0.049458300, -0.117665700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0054344000, 0.0066406000, 0.0092546000, 0.0150201000, 0.0277366000, 0.0569383000, 0.1239662000", \ - "0.0051395000, 0.0063043000, 0.0089772000, 0.0147792000, 0.0276937000, 0.0568975000, 0.1239627000", \ - "0.0049049000, 0.0060522000, 0.0086202000, 0.0144045000, 0.0275374000, 0.0569324000, 0.1238774000", \ - "0.0048318000, 0.0058964000, 0.0084085000, 0.0140309000, 0.0270268000, 0.0569005000, 0.1242502000", \ - "0.0051207000, 0.0060294000, 0.0084166000, 0.0139254000, 0.0267614000, 0.0560812000, 0.1235055000", \ - "0.0055999000, 0.0065735000, 0.0092485000, 0.0143459000, 0.0268976000, 0.0560153000, 0.1239371000", \ - "0.0072522000, 0.0080180000, 0.0103930000, 0.0156393000, 0.0281000000, 0.0568434000, 0.1241378000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("-0.003377300, -0.003320100, -0.003220000, -0.003097900, -0.002985400, -0.002916900, -0.002876500", \ - "-0.003609700, -0.003551800, -0.003456100, -0.003335900, -0.003226600, -0.003153100, -0.003113700", \ - "-0.003925600, -0.003880200, -0.003781500, -0.003654900, -0.003533400, -0.003450500, -0.003404000", \ - "-0.004262200, -0.004212600, -0.004115600, -0.003970400, -0.003842900, -0.003713400, -0.003636600", \ - "-0.004402300, -0.004347700, -0.004262800, -0.004124700, -0.003953500, -0.003804500, -0.003689300", \ - "-0.004243400, -0.004189200, -0.004184600, -0.004102900, -0.003961900, -0.003772100, -0.003601000", \ - "-0.003022200, -0.003036600, -0.003024000, -0.002997500, -0.002977500, -0.002841300, -0.002650000"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0185648000, 0.0196102000, 0.0220080000, 0.0275313000, 0.0402636000, 0.0696727000, 0.1369169000", \ - "0.0183690000, 0.0194119000, 0.0218086000, 0.0273335000, 0.0400655000, 0.0694824000, 0.1368142000", \ - "0.0182146000, 0.0192528000, 0.0216583000, 0.0271719000, 0.0399182000, 0.0690001000, 0.1360342000", \ - "0.0181461000, 0.0191983000, 0.0215952000, 0.0271121000, 0.0398559000, 0.0689333000, 0.1359885000", \ - "0.0182550000, 0.0192947000, 0.0216900000, 0.0271828000, 0.0399047000, 0.0693306000, 0.1360981000", \ - "0.0182778000, 0.0195990000, 0.0220558000, 0.0276368000, 0.0402242000, 0.0694819000, 0.1364132000", \ - "0.0193545000, 0.0203842000, 0.0228179000, 0.0283223000, 0.0415641000, 0.0706355000, 0.1380940000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0150591000, 0.0140838000, 0.0117437000, 0.0062115000, -0.006605800, -0.036124500, -0.104079400", \ - "0.0148587000, 0.0138801000, 0.0115465000, 0.0060168000, -0.006799900, -0.036321800, -0.104251100", \ - "0.0147152000, 0.0137341000, 0.0114005000, 0.0058725000, -0.006942400, -0.036465200, -0.104387400", \ - "0.0146689000, 0.0137014000, 0.0113260000, 0.0057953000, -0.007022400, -0.036542100, -0.104471500", \ - "0.0142175000, 0.0134932000, 0.0114771000, 0.0060078000, -0.006812100, -0.036330800, -0.104256700", \ - "0.0148143000, 0.0137587000, 0.0113327000, 0.0057536000, -0.006694200, -0.036083700, -0.104002700", \ - "0.0160997000, 0.0150091000, 0.0125787000, 0.0069986000, -0.005835500, -0.035354500, -0.102789100"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("-0.003835800, -0.003852800, -0.003873800, -0.003905300, -0.003931400, -0.003947300, -0.003952500", \ - "-0.004129300, -0.004142400, -0.004163000, -0.004208900, -0.004227900, -0.004234700, -0.004242500", \ - "-0.004420500, -0.004435200, -0.004458200, -0.004486100, -0.004508400, -0.004524200, -0.004532200", \ - "-0.004677600, -0.004687900, -0.004704600, -0.004729500, -0.004755000, -0.004766300, -0.004775400", \ - "-0.004748200, -0.004760900, -0.004761500, -0.004798500, -0.004815800, -0.004826000, -0.004832000", \ - "-0.004455800, -0.004470400, -0.004517300, -0.004531500, -0.004552400, -0.004573300, -0.004583800", \ - "-0.003370500, -0.003328400, -0.003344900, -0.003360100, -0.003378100, -0.003435100, -0.003427200"); - } - when : "A"; - } - max_capacitance : 0.0741680000; - max_transition : 1.4839370000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0215908000, 0.0250727000, 0.0327501000, 0.0498138000, 0.0885969000, 0.1780438000, 0.3821096000", \ - "0.0257721000, 0.0292759000, 0.0371385000, 0.0543441000, 0.0933990000, 0.1824126000, 0.3886963000", \ - "0.0343968000, 0.0388785000, 0.0473713000, 0.0648282000, 0.1038871000, 0.1931664000, 0.3999705000", \ - "0.0446204000, 0.0514689000, 0.0646395000, 0.0882195000, 0.1285851000, 0.2174961000, 0.4221736000", \ - "0.0531716000, 0.0639562000, 0.0839731000, 0.1203308000, 0.1793109000, 0.2745365000, 0.4791469000", \ - "0.0520471000, 0.0684430000, 0.1000376000, 0.1547353000, 0.2459003000, 0.3863867000, 0.6096326000", \ - "0.0174130000, 0.0422676000, 0.0906304000, 0.1753148000, 0.3154468000, 0.5329601000, 0.8672962000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0473367000, 0.0578424000, 0.0806448000, 0.1304658000, 0.2413876000, 0.4950347000, 1.0793877000", \ - "0.0499577000, 0.0600512000, 0.0832322000, 0.1332214000, 0.2456970000, 0.4997063000, 1.0833168000", \ - "0.0603900000, 0.0699786000, 0.0921628000, 0.1420263000, 0.2556368000, 0.5136634000, 1.0948926000", \ - "0.0867941000, 0.0976441000, 0.1189048000, 0.1673583000, 0.2791967000, 0.5383742000, 1.1232610000", \ - "0.1281422000, 0.1445708000, 0.1769399000, 0.2329424000, 0.3433210000, 0.5977965000, 1.1826933000", \ - "0.1932946000, 0.2177397000, 0.2663545000, 0.3516633000, 0.4944726000, 0.7473804000, 1.3332166000", \ - "0.3076683000, 0.3414033000, 0.4106371000, 0.5360434000, 0.7490860000, 1.0934043000, 1.6759076000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0144430000, 0.0187388000, 0.0286708000, 0.0514975000, 0.1033061000, 0.2219593000, 0.4958404000", \ - "0.0144644000, 0.0187222000, 0.0286206000, 0.0511950000, 0.1035423000, 0.2244237000, 0.4970239000", \ - "0.0199605000, 0.0228931000, 0.0307299000, 0.0518698000, 0.1036252000, 0.2242227000, 0.4969969000", \ - "0.0309656000, 0.0360178000, 0.0453854000, 0.0624537000, 0.1065316000, 0.2236613000, 0.4953277000", \ - "0.0519825000, 0.0596468000, 0.0726192000, 0.0956428000, 0.1369946000, 0.2341277000, 0.5001444000", \ - "0.0893467000, 0.1004961000, 0.1193038000, 0.1552739000, 0.2130447000, 0.3135638000, 0.5275430000", \ - "0.1581722000, 0.1741643000, 0.2046986000, 0.2576310000, 0.3447555000, 0.4848307000, 0.7105013000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0459983000, 0.0587525000, 0.0876343000, 0.1540195000, 0.3044932000, 0.6533869000, 1.4529488000", \ - "0.0458738000, 0.0585489000, 0.0877060000, 0.1540391000, 0.3045287000, 0.6527524000, 1.4543027000", \ - "0.0453807000, 0.0581083000, 0.0875436000, 0.1535158000, 0.3059170000, 0.6542114000, 1.4506647000", \ - "0.0575943000, 0.0668487000, 0.0909049000, 0.1529688000, 0.3053813000, 0.6588219000, 1.4547116000", \ - "0.0844022000, 0.0971067000, 0.1234863000, 0.1719125000, 0.3066151000, 0.6534743000, 1.4548968000", \ - "0.1269121000, 0.1463146000, 0.1810684000, 0.2476681000, 0.3622134000, 0.6613228000, 1.4592306000", \ - "0.1967449000, 0.2247447000, 0.2768650000, 0.3733261000, 0.5346080000, 0.7974106000, 1.4839374000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0689165000, 0.0728008000, 0.0810903000, 0.0989048000, 0.1380965000, 0.2271264000, 0.4326023000", \ - "0.0736599000, 0.0774833000, 0.0857762000, 0.1036052000, 0.1428006000, 0.2319298000, 0.4367000000", \ - "0.0866710000, 0.0904898000, 0.0987853000, 0.1165671000, 0.1557628000, 0.2447045000, 0.4502668000", \ - "0.1168731000, 0.1208311000, 0.1292064000, 0.1470883000, 0.1863201000, 0.2754714000, 0.4798770000", \ - "0.1664946000, 0.1710837000, 0.1804870000, 0.1993567000, 0.2394023000, 0.3287511000, 0.5331629000", \ - "0.2424315000, 0.2482477000, 0.2593989000, 0.2806961000, 0.3220809000, 0.4120984000, 0.6169685000", \ - "0.3613479000, 0.3690666000, 0.3834772000, 0.4092473000, 0.4550605000, 0.5468953000, 0.7522595000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0592691000, 0.0688119000, 0.0904106000, 0.1387448000, 0.2491466000, 0.5054502000, 1.0899840000", \ - "0.0652160000, 0.0747851000, 0.0963324000, 0.1446470000, 0.2550721000, 0.5106944000, 1.0923088000", \ - "0.0790602000, 0.0885584000, 0.1101092000, 0.1583321000, 0.2685974000, 0.5219440000, 1.1046318000", \ - "0.1070373000, 0.1170016000, 0.1387648000, 0.1871193000, 0.2974306000, 0.5506849000, 1.1333869000", \ - "0.1544451000, 0.1678639000, 0.1955190000, 0.2488997000, 0.3594232000, 0.6159221000, 1.1961836000", \ - "0.2278364000, 0.2491704000, 0.2907747000, 0.3652973000, 0.4976294000, 0.7545617000, 1.3380628000", \ - "0.3237498000, 0.3612068000, 0.4314072000, 0.5527933000, 0.7461642000, 1.0684212000, 1.6650544000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0187345000, 0.0228222000, 0.0322377000, 0.0538203000, 0.1042589000, 0.2232778000, 0.5025645000", \ - "0.0187227000, 0.0228361000, 0.0322137000, 0.0536839000, 0.1042479000, 0.2238968000, 0.4958098000", \ - "0.0186852000, 0.0228376000, 0.0321866000, 0.0538531000, 0.1041250000, 0.2229344000, 0.5027995000", \ - "0.0194182000, 0.0234626000, 0.0326167000, 0.0540194000, 0.1043141000, 0.2233613000, 0.4962443000", \ - "0.0229787000, 0.0268741000, 0.0358860000, 0.0565726000, 0.1057977000, 0.2233024000, 0.4970194000", \ - "0.0306398000, 0.0343565000, 0.0426150000, 0.0624050000, 0.1089903000, 0.2247536000, 0.4965577000", \ - "0.0426869000, 0.0469915000, 0.0554767000, 0.0744042000, 0.1174441000, 0.2271324000, 0.4996081000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0490631000, 0.0614552000, 0.0895843000, 0.1542445000, 0.3054325000, 0.6565218000, 1.4558087000", \ - "0.0490945000, 0.0614301000, 0.0895403000, 0.1543143000, 0.3054460000, 0.6568769000, 1.4558353000", \ - "0.0491966000, 0.0613814000, 0.0895351000, 0.1541199000, 0.3052758000, 0.6522227000, 1.4558985000", \ - "0.0530808000, 0.0644644000, 0.0908138000, 0.1545238000, 0.3050987000, 0.6521829000, 1.4547560000", \ - "0.0722530000, 0.0837621000, 0.1078218000, 0.1640299000, 0.3061997000, 0.6561386000, 1.4526954000", \ - "0.1154536000, 0.1293834000, 0.1569867000, 0.2140516000, 0.3370190000, 0.6587573000, 1.4582019000", \ - "0.2059652000, 0.2245074000, 0.2611210000, 0.3297794000, 0.4633821000, 0.7452196000, 1.4734020000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0244149000, 0.0244149000, 0.0244259000, 0.0244259000, 0.0244259000, 0.0244259000, 0.0244520000", \ - "0.0237437000, 0.0237437000, 0.0237750000, 0.0237963000, 0.0237963000, 0.0237963000, 0.0238110000", \ - "0.0246551000, 0.0246551000, 0.0246781000, 0.0248589000, 0.0248589000, 0.0248589000, 0.0248865000", \ - "0.0209981000, 0.0209981000, 0.0210917000, 0.0210917000, 0.0210917000, 0.0210917000, 0.0210917000", \ - "0.0095462000, 0.0095462000, 0.0095462000, 0.0095462000, 0.0095462000, 0.0095462000, 0.0095462000", \ - "-0.020099000, -0.020099000, -0.019999000, -0.019598100, -0.019598100, -0.019598100, -0.019598100", \ - "-0.089071400, -0.089071400, -0.088617700, -0.088512800, -0.088512800, -0.088512800, -0.088512800"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024934000, 0.0031437900, 0.0046401800, 0.0080830500, 0.0160043000, 0.0342294000, 0.0761611000"); - values("0.0359098000, 0.0359098000, 0.0359098000, 0.0359749000, 0.0359749000, 0.0359749000, 0.0359934000", \ - "0.0409610000, 0.0409610000, 0.0409610000, 0.0409610000, 0.0409610000, 0.0409610000, 0.0409628000", \ - "0.0522084000, 0.0522084000, 0.0522084000, 0.0522112000, 0.0522507000, 0.0522507000, 0.0522507000", \ - "0.0678597000, 0.0678597000, 0.0678883000, 0.0678883000, 0.0679317000, 0.0679317000, 0.0679518000", \ - "0.0867253000, 0.0867253000, 0.0867272000, 0.0867272000, 0.0868781000, 0.0868781000, 0.0868781000", \ - "0.1045225000, 0.1045225000, 0.1046023000, 0.1046023000, 0.1046023000, 0.1046023000, 0.1046023000", \ - "0.1105245000, 0.1105245000, 0.1108282000, 0.1108282000, 0.1109450000, 0.1109450000, 0.1116048000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvn_2") { - leakage_power () { - value : 0.0016933000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0009878000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0017688000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0081966000; - when : "A&!TE_B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__einvn"; - cell_leakage_power : 0.0031616220; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0042870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046013000, 0.0045887000, 0.0045596000, 0.0045594000, 0.0045589000, 0.0045577000, 0.0045549000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003481700, -0.003478500, -0.003471200, -0.003469900, -0.003466800, -0.003459700, -0.003443400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045290000; - } - pin ("TE_B") { - capacitance : 0.0040030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0036920000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043140000; - } - pin ("Z") { - capacitance : 0.0029180000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0008602000, -0.000158600, -0.002936200, -0.010418600, -0.029919000, -0.079528200, -0.204763800", \ - "0.0004750000, -0.000518400, -0.003220300, -0.010534100, -0.029886800, -0.079405100, -0.204603800", \ - "1.770000e-05, -0.001012400, -0.003659700, -0.010895900, -0.030049200, -0.079426000, -0.204532700", \ - "-0.000271400, -0.001354800, -0.004191100, -0.011473100, -0.030464800, -0.079614600, -0.204585300", \ - "2.420000e-05, -0.001154100, -0.004355300, -0.011830500, -0.030926700, -0.079936300, -0.204751600", \ - "0.0016190000, 0.0002777000, -0.002962100, -0.011009800, -0.030656400, -0.080240000, -0.204972100", \ - "0.0063763000, 0.0049659000, 0.0008201000, -0.007897600, -0.028710600, -0.079075500, -0.204742500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0089183000, 0.0104056000, 0.0139253000, 0.0221046000, 0.0421088000, 0.0910660000, 0.2147868000", \ - "0.0084673000, 0.0098765000, 0.0132886000, 0.0215867000, 0.0416618000, 0.0916194000, 0.2154972000", \ - "0.0081155000, 0.0094619000, 0.0128290000, 0.0210356000, 0.0413057000, 0.0908114000, 0.2156975000", \ - "0.0081674000, 0.0094450000, 0.0126635000, 0.0205699000, 0.0404269000, 0.0902960000, 0.2144723000", \ - "0.0086428000, 0.0098350000, 0.0128719000, 0.0205874000, 0.0402105000, 0.0896963000, 0.2141066000", \ - "0.0103400000, 0.0114533000, 0.0142788000, 0.0217558000, 0.0407221000, 0.0897239000, 0.2135715000", \ - "0.0145001000, 0.0154526000, 0.0180876000, 0.0251568000, 0.0435208000, 0.0917614000, 0.2140776000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("-0.006518200, -0.006418800, -0.006247600, -0.005997100, -0.005719900, -0.005549900, -0.005469300", \ - "-0.006718900, -0.006635100, -0.006467900, -0.006217100, -0.005969000, -0.005793700, -0.005704700", \ - "-0.007044100, -0.006959100, -0.006771200, -0.006513800, -0.006255900, -0.006072600, -0.005974800", \ - "-0.007447200, -0.007377200, -0.007233700, -0.006973500, -0.006643600, -0.006406100, -0.006270700", \ - "-0.007761200, -0.007704700, -0.007578700, -0.007345800, -0.007027900, -0.006619700, -0.006410700", \ - "-0.007626200, -0.007588600, -0.007511200, -0.007343500, -0.007054800, -0.006692700, -0.006380400", \ - "-0.006496000, -0.006470400, -0.006415400, -0.006296400, -0.006137900, -0.005889700, -0.005521600"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0282145000, 0.0294442000, 0.0324951000, 0.0402265000, 0.0597328000, 0.1090179000, 0.2324764000", \ - "0.0280355000, 0.0292580000, 0.0323094000, 0.0400520000, 0.0595680000, 0.1085798000, 0.2337761000", \ - "0.0278484000, 0.0290743000, 0.0321291000, 0.0398548000, 0.0593494000, 0.1087489000, 0.2320990000", \ - "0.0277401000, 0.0289764000, 0.0320524000, 0.0397682000, 0.0592414000, 0.1086188000, 0.2320315000", \ - "0.0278059000, 0.0290488000, 0.0321179000, 0.0398114000, 0.0592983000, 0.1086734000, 0.2327436000", \ - "0.0273558000, 0.0285516000, 0.0323478000, 0.0401801000, 0.0596278000, 0.1087970000, 0.2330059000", \ - "0.0285012000, 0.0297840000, 0.0328595000, 0.0405552000, 0.0606426000, 0.1099674000, 0.2338532000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0235179000, 0.0223973000, 0.0194637000, 0.0118119000, -0.007842300, -0.057526900, -0.182794100", \ - "0.0233464000, 0.0222187000, 0.0192741000, 0.0116392000, -0.008020500, -0.057704600, -0.182964500", \ - "0.0231440000, 0.0220165000, 0.0190992000, 0.0114417000, -0.008217600, -0.057905000, -0.183171700", \ - "0.0230471000, 0.0218963000, 0.0189995000, 0.0113413000, -0.008316300, -0.058001500, -0.183267800", \ - "0.0227309000, 0.0217632000, 0.0189646000, 0.0114026000, -0.008252600, -0.057934100, -0.183203200", \ - "0.0231875000, 0.0219611000, 0.0188567000, 0.0110295000, -0.008110800, -0.057551400, -0.182829300", \ - "0.0242325000, 0.0229996000, 0.0198919000, 0.0120617000, -0.007645600, -0.057379600, -0.181906000"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("-0.006762100, -0.006768800, -0.006791400, -0.006836400, -0.006883400, -0.006918000, -0.006931200", \ - "-0.007159300, -0.007173400, -0.007202600, -0.007251200, -0.007281200, -0.007290900, -0.007316400", \ - "-0.007470500, -0.007485200, -0.007513700, -0.007574300, -0.007623600, -0.007685400, -0.007692500", \ - "-0.007804500, -0.007829800, -0.007849900, -0.007874100, -0.007917200, -0.007957900, -0.007978800", \ - "-0.007974000, -0.007947000, -0.007974800, -0.008014900, -0.008069900, -0.008099800, -0.008117800", \ - "-0.007807400, -0.007830600, -0.007849900, -0.007909800, -0.007954700, -0.007979000, -0.007997200", \ - "-0.006783100, -0.006793000, -0.006802800, -0.006792100, -0.006792700, -0.006814000, -0.006827300"); - } - when : "A"; - } - max_capacitance : 0.1281840000; - max_transition : 1.4918400000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0190964000, 0.0215415000, 0.0273021000, 0.0411027000, 0.0750546000, 0.1605188000, 0.3766727000", \ - "0.0230844000, 0.0254642000, 0.0313423000, 0.0453231000, 0.0796809000, 0.1652987000, 0.3800304000", \ - "0.0304399000, 0.0337898000, 0.0409881000, 0.0554743000, 0.0897980000, 0.1755869000, 0.3917145000", \ - "0.0375751000, 0.0429186000, 0.0542146000, 0.0759554000, 0.1136428000, 0.1994993000, 0.4151808000", \ - "0.0411462000, 0.0493519000, 0.0668331000, 0.1002218000, 0.1583835000, 0.2549439000, 0.4703431000", \ - "0.0320563000, 0.0445358000, 0.0711772000, 0.1218623000, 0.2106694000, 0.3583474000, 0.5989224000", \ - "-0.014655400, 0.0046702000, 0.0436436000, 0.1210141000, 0.2571160000, 0.4827157000, 0.8436525000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0395557000, 0.0471409000, 0.0647426000, 0.1056920000, 0.2055471000, 0.4517710000, 1.0728254000", \ - "0.0422568000, 0.0493701000, 0.0663980000, 0.1079674000, 0.2084654000, 0.4574774000, 1.0805159000", \ - "0.0526934000, 0.0592102000, 0.0758496000, 0.1168733000, 0.2177250000, 0.4685279000, 1.0883612000", \ - "0.0756349000, 0.0845132000, 0.1030670000, 0.1424835000, 0.2422321000, 0.4936198000, 1.1136866000", \ - "0.1099429000, 0.1230114000, 0.1508031000, 0.2047395000, 0.3044066000, 0.5525160000, 1.1781588000", \ - "0.1662763000, 0.1849721000, 0.2254963000, 0.3049843000, 0.4465229000, 0.6993244000, 1.3194894000", \ - "0.2709444000, 0.2962802000, 0.3514535000, 0.4639669000, 0.6730727000, 1.0324736000, 1.6622688000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0113520000, 0.0142025000, 0.0215330000, 0.0399146000, 0.0863634000, 0.2026894000, 0.4965594000", \ - "0.0115160000, 0.0142416000, 0.0215183000, 0.0399803000, 0.0865714000, 0.2031270000, 0.4947053000", \ - "0.0163567000, 0.0192213000, 0.0248438000, 0.0407661000, 0.0863899000, 0.2030211000, 0.4946891000", \ - "0.0257993000, 0.0294752000, 0.0374049000, 0.0541452000, 0.0908876000, 0.2027051000, 0.4957271000", \ - "0.0436673000, 0.0493073000, 0.0607851000, 0.0832255000, 0.1255843000, 0.2166803000, 0.4955454000", \ - "0.0761174000, 0.0846890000, 0.1021864000, 0.1361258000, 0.1935961000, 0.2963202000, 0.5269911000", \ - "0.1367211000, 0.1503448000, 0.1792656000, 0.2286130000, 0.3138138000, 0.4594200000, 0.7114299000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0375811000, 0.0462925000, 0.0677011000, 0.1217028000, 0.2580593000, 0.5966417000, 1.4567811000", \ - "0.0372946000, 0.0461047000, 0.0674959000, 0.1214181000, 0.2571538000, 0.6017513000, 1.4597483000", \ - "0.0382596000, 0.0459586000, 0.0673302000, 0.1217926000, 0.2576358000, 0.5982905000, 1.4620377000", \ - "0.0535732000, 0.0590363000, 0.0749746000, 0.1225392000, 0.2574152000, 0.5979156000, 1.4550671000", \ - "0.0721058000, 0.0829363000, 0.1061493000, 0.1494148000, 0.2632811000, 0.5986922000, 1.4594644000", \ - "0.1071308000, 0.1218527000, 0.1538690000, 0.2160483000, 0.3282341000, 0.6148012000, 1.4570596000", \ - "0.1679286000, 0.1878365000, 0.2320207000, 0.3227119000, 0.4832090000, 0.7703658000, 1.4918400000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0764906000, 0.0795017000, 0.0863233000, 0.1017365000, 0.1371391000, 0.2229538000, 0.4388531000", \ - "0.0813235000, 0.0843372000, 0.0911900000, 0.1065435000, 0.1419968000, 0.2278315000, 0.4432929000", \ - "0.0941915000, 0.0971698000, 0.1040273000, 0.1193840000, 0.1548473000, 0.2406699000, 0.4555133000", \ - "0.1252183000, 0.1282463000, 0.1351349000, 0.1505984000, 0.1860612000, 0.2718841000, 0.4867605000", \ - "0.1803016000, 0.1839645000, 0.1918039000, 0.2086661000, 0.2451902000, 0.3315266000, 0.5475534000", \ - "0.2632423000, 0.2682400000, 0.2783459000, 0.2982954000, 0.3378774000, 0.4258054000, 0.6414517000", \ - "0.3870539000, 0.3935303000, 0.4076917000, 0.4333960000, 0.4811786000, 0.5726140000, 0.7888828000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0487884000, 0.0550879000, 0.0707975000, 0.1099153000, 0.2076884000, 0.4553581000, 1.0730227000", \ - "0.0548089000, 0.0611078000, 0.0767801000, 0.1159716000, 0.2135863000, 0.4596777000, 1.0857056000", \ - "0.0681226000, 0.0744165000, 0.0901780000, 0.1292210000, 0.2269893000, 0.4736300000, 1.0964452000", \ - "0.0923036000, 0.0995178000, 0.1163516000, 0.1557036000, 0.2534346000, 0.5004204000, 1.1189882000", \ - "0.1307976000, 0.1400914000, 0.1621209000, 0.2091438000, 0.3096345000, 0.5559548000, 1.1763041000", \ - "0.1854547000, 0.2014595000, 0.2354890000, 0.3016525000, 0.4278853000, 0.6832429000, 1.3134710000", \ - "0.2409948000, 0.2687054000, 0.3293001000, 0.4422398000, 0.6305284000, 0.9559363000, 1.5985181000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0174340000, 0.0202678000, 0.0272517000, 0.0446559000, 0.0889314000, 0.2035666000, 0.4947420000", \ - "0.0174350000, 0.0202601000, 0.0272549000, 0.0447764000, 0.0888018000, 0.2031225000, 0.4955934000", \ - "0.0174539000, 0.0202774000, 0.0272518000, 0.0446680000, 0.0889980000, 0.2033758000, 0.4946438000", \ - "0.0177548000, 0.0204667000, 0.0274562000, 0.0447693000, 0.0890347000, 0.2033385000, 0.4944642000", \ - "0.0216639000, 0.0243758000, 0.0309603000, 0.0477741000, 0.0905581000, 0.2033384000, 0.4971087000", \ - "0.0299747000, 0.0327231000, 0.0393695000, 0.0551638000, 0.0958400000, 0.2057661000, 0.4954824000", \ - "0.0431672000, 0.0461988000, 0.0537850000, 0.0698402000, 0.1090330000, 0.2118423000, 0.4966271000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0389553000, 0.0473220000, 0.0685590000, 0.1221059000, 0.2572797000, 0.5991537000, 1.4569869000", \ - "0.0390410000, 0.0474514000, 0.0686561000, 0.1221583000, 0.2573367000, 0.5972688000, 1.4692336000", \ - "0.0392910000, 0.0477384000, 0.0687515000, 0.1222508000, 0.2567617000, 0.6005471000, 1.4600982000", \ - "0.0450628000, 0.0522340000, 0.0719987000, 0.1230123000, 0.2570315000, 0.6001591000, 1.4567310000", \ - "0.0620228000, 0.0702824000, 0.0898736000, 0.1363864000, 0.2611137000, 0.6002736000, 1.4607904000", \ - "0.1024700000, 0.1124519000, 0.1345854000, 0.1842822000, 0.2982145000, 0.6085578000, 1.4653788000", \ - "0.1892328000, 0.2031917000, 0.2327689000, 0.2927800000, 0.4147103000, 0.7004988000, 1.4800384000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0333788000, 0.0333788000, 0.0333788000, 0.0333788000, 0.0333788000, 0.0333788000, 0.0333788000", \ - "0.0352450000, 0.0352450000, 0.0353182000, 0.0353182000, 0.0353182000, 0.0353182000, 0.0353182000", \ - "0.0369755000, 0.0369755000, 0.0372658000, 0.0372658000, 0.0372658000, 0.0372658000, 0.0372658000", \ - "0.0321060000, 0.0321060000, 0.0321060000, 0.0321298000, 0.0321298000, 0.0321298000, 0.0321298000", \ - "0.0220828000, 0.0220828000, 0.0220828000, 0.0220828000, 0.0220948000, 0.0221487000, 0.0223110000", \ - "0.0028257000, 0.0028257000, 0.0032642000, 0.0032642000, 0.0036460000, 0.0036460000, 0.0036460000", \ - "-0.039984200, -0.039984200, -0.039984200, -0.039984200, -0.038350300, -0.038350300, -0.038350300"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0034181000, 0.0041783200, 0.0060944200, 0.0109238000, 0.0230961000, 0.0537757000, 0.1311020000"); - values("0.0458856000, 0.0460834000, 0.0460834000, 0.0460834000, 0.0460834000, 0.0460834000, 0.0460834000", \ - "0.0510883000, 0.0510883000, 0.0511656000, 0.0511656000, 0.0512302000, 0.0512302000, 0.0512302000", \ - "0.0628612000, 0.0628612000, 0.0628612000, 0.0628612000, 0.0628612000, 0.0628612000, 0.0628612000", \ - "0.0830067000, 0.0830067000, 0.0830067000, 0.0830067000, 0.0830073000, 0.0830073000, 0.0830073000", \ - "0.1107863000, 0.1107863000, 0.1113097000, 0.1113097000, 0.1113097000, 0.1118834000, 0.1118834000", \ - "0.1435534000, 0.1435534000, 0.1435534000, 0.1435534000, 0.1445746000, 0.1445746000, 0.1445746000", \ - "0.1711483000, 0.1711483000, 0.1711483000, 0.1737373000, 0.1737373000, 0.1748638000, 0.1748638000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvn_4") { - leakage_power () { - value : 0.0028026000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0021273000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0027976000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0076017000; - when : "A&!TE_B"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__einvn"; - cell_leakage_power : 0.0038323040; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0082270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088256000, 0.0087986000, 0.0087365000, 0.0087481000, 0.0087749000, 0.0088367000, 0.0089791000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007159700, -0.007154800, -0.007143600, -0.007145000, -0.007148500, -0.007156400, -0.007174600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086550000; - } - pin ("TE_B") { - capacitance : 0.0066830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0060810000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0072840000; - } - pin ("Z") { - capacitance : 0.0046800000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("-0.001002800, -0.002127300, -0.005560900, -0.016229900, -0.047966300, -0.138550600, -0.393394400", \ - "-0.001687800, -0.002824600, -0.006196500, -0.016551300, -0.047950800, -0.138309800, -0.393076500", \ - "-0.002405500, -0.003635400, -0.007103100, -0.017335100, -0.048274000, -0.138329200, -0.392899400", \ - "-0.002656500, -0.004148700, -0.007923400, -0.018337600, -0.049096500, -0.138674800, -0.392941600", \ - "-0.002112600, -0.003798800, -0.007808000, -0.018672400, -0.050129300, -0.139358200, -0.393260100", \ - "0.0009535000, -0.000681700, -0.005188300, -0.017213200, -0.049259000, -0.139687800, -0.393539800", \ - "0.0092843000, 0.0074045000, 0.0024722000, -0.010673200, -0.044630200, -0.137277100, -0.393194600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("0.0163203000, 0.0182512000, 0.0233021000, 0.0360257000, 0.0689180000, 0.1593106000, 0.4107665000", \ - "0.0156725000, 0.0173377000, 0.0221949000, 0.0349786000, 0.0682739000, 0.1587793000, 0.4108910000", \ - "0.0153608000, 0.0169740000, 0.0213673000, 0.0337335000, 0.0674707000, 0.1586186000, 0.4107522000", \ - "0.0153387000, 0.0168207000, 0.0212045000, 0.0330650000, 0.0662264000, 0.1581765000, 0.4102156000", \ - "0.0162653000, 0.0176915000, 0.0216947000, 0.0331110000, 0.0654880000, 0.1558505000, 0.4123240000", \ - "0.0191262000, 0.0210213000, 0.0240742000, 0.0349216000, 0.0664751000, 0.1557790000, 0.4103063000", \ - "0.0273817000, 0.0282609000, 0.0317468000, 0.0418522000, 0.0718903000, 0.1590692000, 0.4093433000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("-0.012451000, -0.012324600, -0.012048100, -0.011554000, -0.010974100, -0.010577400, -0.010385000", \ - "-0.012786100, -0.012669900, -0.012400300, -0.011919400, -0.011358200, -0.010986300, -0.010791500", \ - "-0.013384200, -0.013270800, -0.013004700, -0.012513600, -0.011916500, -0.011489000, -0.011260700", \ - "-0.014073800, -0.013979400, -0.013737100, -0.013256900, -0.012586800, -0.012022200, -0.011707500", \ - "-0.014622000, -0.014550700, -0.014380700, -0.013979300, -0.013295100, -0.012571800, -0.012062700", \ - "-0.014540300, -0.014491500, -0.014377000, -0.014087800, -0.013543500, -0.012716700, -0.012020200", \ - "-0.013131600, -0.013094600, -0.013001000, -0.012859800, -0.012507900, -0.011907200, -0.011110300"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("0.0511272000, 0.0526115000, 0.0567618000, 0.0681150000, 0.1000499000, 0.1902101000, 0.4414740000", \ - "0.0508709000, 0.0523578000, 0.0564938000, 0.0678458000, 0.0997907000, 0.1899803000, 0.4412097000", \ - "0.0505701000, 0.0520556000, 0.0562007000, 0.0675549000, 0.0995659000, 0.1898055000, 0.4409106000", \ - "0.0503680000, 0.0518751000, 0.0560171000, 0.0674251000, 0.0993638000, 0.1894192000, 0.4407686000", \ - "0.0504661000, 0.0520102000, 0.0561384000, 0.0674953000, 0.0994241000, 0.1896092000, 0.4407437000", \ - "0.0497574000, 0.0511479000, 0.0561496000, 0.0680856000, 0.1000519000, 0.1898282000, 0.4413917000", \ - "0.0517167000, 0.0531761000, 0.0572615000, 0.0685943000, 0.1016438000, 0.1915760000, 0.4438570000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("0.0400329000, 0.0386817000, 0.0349211000, 0.0238712000, -0.008237000, -0.099005600, -0.353931300", \ - "0.0397170000, 0.0384415000, 0.0346585000, 0.0236075000, -0.008497100, -0.099259900, -0.354189600", \ - "0.0394768000, 0.0381388000, 0.0343746000, 0.0233484000, -0.008765500, -0.099533600, -0.354452400", \ - "0.0392575000, 0.0379687000, 0.0341689000, 0.0231585000, -0.008948300, -0.099722400, -0.354635800", \ - "0.0390695000, 0.0377807000, 0.0341107000, 0.0231989000, -0.008854900, -0.099642100, -0.354551300", \ - "0.0397078000, 0.0382414000, 0.0341382000, 0.0225901000, -0.008937700, -0.099049200, -0.353999400", \ - "0.0415377000, 0.0400798000, 0.0359724000, 0.0244274000, -0.007921300, -0.098727800, -0.352293700"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014033790, 0.0039389460, 0.0110556700, 0.0310306000, 0.0870953900, 0.2444557000"); - values("-0.013457400, -0.013468200, -0.013494200, -0.013542100, -0.013601200, -0.013653800, -0.013672200", \ - "-0.013932000, -0.013947000, -0.013977300, -0.014021500, -0.014086500, -0.014126900, -0.014157700", \ - "-0.014433400, -0.014445700, -0.014476200, -0.014529800, -0.014589900, -0.014644200, -0.014663300", \ - "-0.014860700, -0.014870900, -0.014892400, -0.014943600, -0.015011200, -0.015053900, -0.015079000", \ - "-0.015196900, -0.015211200, -0.015232500, -0.015253000, -0.015309500, -0.015349300, -0.015331700", \ - "-0.014985100, -0.014994300, -0.015005400, -0.015046200, -0.015076800, -0.015129000, -0.015149300", \ - "-0.013284400, -0.013298400, -0.013336600, -0.013374000, -0.013401300, -0.013431300, -0.013448200"); - } - when : "A"; - } - max_capacitance : 0.2444560000; - max_transition : 1.4982520000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0188427000, 0.0205437000, 0.0250086000, 0.0364640000, 0.0670749000, 0.1526979000, 0.3935968000", \ - "0.0226094000, 0.0242815000, 0.0287652000, 0.0404171000, 0.0713313000, 0.1569467000, 0.3964934000", \ - "0.0288689000, 0.0313934000, 0.0374412000, 0.0500404000, 0.0812750000, 0.1672205000, 0.4075284000", \ - "0.0337518000, 0.0378011000, 0.0472680000, 0.0672135000, 0.1048533000, 0.1907167000, 0.4323153000", \ - "0.0330901000, 0.0391527000, 0.0538009000, 0.0846966000, 0.1433669000, 0.2460298000, 0.4851682000", \ - "0.0154081000, 0.0246056000, 0.0470996000, 0.0942164000, 0.1838123000, 0.3414348000, 0.6126274000", \ - "-0.048815100, -0.034621400, -0.000559300, 0.0713266000, 0.2072357000, 0.4481659000, 0.8560242000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0347471000, 0.0398774000, 0.0532847000, 0.0873824000, 0.1754714000, 0.4170407000, 1.0884879000", \ - "0.0379307000, 0.0424056000, 0.0552480000, 0.0892527000, 0.1783056000, 0.4201250000, 1.0925389000", \ - "0.0494907000, 0.0535230000, 0.0650115000, 0.0979003000, 0.1873653000, 0.4314314000, 1.1039789000", \ - "0.0710451000, 0.0772556000, 0.0924620000, 0.1244468000, 0.2119724000, 0.4568895000, 1.1302337000", \ - "0.1045231000, 0.1138792000, 0.1364717000, 0.1845514000, 0.2766663000, 0.5185419000, 1.2012950000", \ - "0.1625969000, 0.1758824000, 0.2076535000, 0.2784770000, 0.4156544000, 0.6684742000, 1.3450783000", \ - "0.2749445000, 0.2925980000, 0.3366220000, 0.4352827000, 0.6363272000, 1.0024245000, 1.6921246000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0097052000, 0.0116053000, 0.0169363000, 0.0319519000, 0.0739059000, 0.1918306000, 0.5202859000", \ - "0.0100329000, 0.0117189000, 0.0169152000, 0.0319158000, 0.0740294000, 0.1917152000, 0.5201254000", \ - "0.0144503000, 0.0165093000, 0.0213599000, 0.0335686000, 0.0738344000, 0.1916822000, 0.5206142000", \ - "0.0231067000, 0.0257462000, 0.0321857000, 0.0470284000, 0.0806422000, 0.1910315000, 0.5213929000", \ - "0.0392729000, 0.0434584000, 0.0535646000, 0.0741825000, 0.1143624000, 0.2076956000, 0.5220347000", \ - "0.0692808000, 0.0755638000, 0.0918295000, 0.1220828000, 0.1807675000, 0.2890439000, 0.5495623000", \ - "0.1263677000, 0.1362348000, 0.1585842000, 0.2073520000, 0.2935223000, 0.4491098000, 0.7373998000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0304759000, 0.0361053000, 0.0514835000, 0.0941249000, 0.2123246000, 0.5435589000, 1.4714527000", \ - "0.0300734000, 0.0357913000, 0.0513059000, 0.0938809000, 0.2120749000, 0.5426877000, 1.4704400000", \ - "0.0314073000, 0.0362865000, 0.0506288000, 0.0939373000, 0.2127722000, 0.5434400000, 1.4732061000", \ - "0.0451419000, 0.0509268000, 0.0613786000, 0.0965724000, 0.2127144000, 0.5462099000, 1.4712066000", \ - "0.0616118000, 0.0688882000, 0.0879476000, 0.1280350000, 0.2211950000, 0.5439567000, 1.4833915000", \ - "0.0933814000, 0.1037380000, 0.1292800000, 0.1843964000, 0.2948815000, 0.5614695000, 1.4765242000", \ - "0.1517428000, 0.1651949000, 0.2007605000, 0.2799893000, 0.4323776000, 0.7191306000, 1.4982519000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0794324000, 0.0815883000, 0.0871631000, 0.1005741000, 0.1335497000, 0.2199074000, 0.4593974000", \ - "0.0840545000, 0.0863017000, 0.0918841000, 0.1052463000, 0.1382651000, 0.2246503000, 0.4642116000", \ - "0.0968288000, 0.0989933000, 0.1045632000, 0.1179279000, 0.1509314000, 0.2373510000, 0.4774977000", \ - "0.1278436000, 0.1301278000, 0.1357570000, 0.1491643000, 0.1821984000, 0.2686310000, 0.5088637000", \ - "0.1850354000, 0.1877338000, 0.1944905000, 0.2094018000, 0.2436469000, 0.3306546000, 0.5711983000", \ - "0.2717708000, 0.2754681000, 0.2844928000, 0.3030861000, 0.3416854000, 0.4310127000, 0.6713373000", \ - "0.4045368000, 0.4099877000, 0.4219523000, 0.4469178000, 0.4939599000, 0.5902022000, 0.8319602000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0502322000, 0.0542945000, 0.0655425000, 0.0965798000, 0.1822906000, 0.4216984000, 1.0935088000", \ - "0.0560074000, 0.0600936000, 0.0713370000, 0.1023841000, 0.1880820000, 0.4274165000, 1.0993891000", \ - "0.0697306000, 0.0738581000, 0.0851914000, 0.1161294000, 0.2018281000, 0.4414721000, 1.1130258000", \ - "0.0954493000, 0.1001949000, 0.1127194000, 0.1441910000, 0.2299139000, 0.4693909000, 1.1413589000", \ - "0.1368458000, 0.1432099000, 0.1596268000, 0.1988824000, 0.2893850000, 0.5294969000, 1.2014908000", \ - "0.1977463000, 0.2080805000, 0.2348056000, 0.2927796000, 0.4107990000, 0.6638273000, 1.3384215000", \ - "0.2669949000, 0.2867811000, 0.3347234000, 0.4349095000, 0.6186977000, 0.9487154000, 1.6479996000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0165836000, 0.0184561000, 0.0236565000, 0.0379219000, 0.0779748000, 0.1925766000, 0.5212845000", \ - "0.0165584000, 0.0184516000, 0.0236629000, 0.0379216000, 0.0779169000, 0.1924389000, 0.5202738000", \ - "0.0166320000, 0.0184414000, 0.0236566000, 0.0378901000, 0.0779646000, 0.1925019000, 0.5199856000", \ - "0.0168123000, 0.0186582000, 0.0238156000, 0.0379948000, 0.0779988000, 0.1925633000, 0.5199935000", \ - "0.0212257000, 0.0229003000, 0.0277861000, 0.0413294000, 0.0795684000, 0.1927839000, 0.5219920000", \ - "0.0301098000, 0.0320322000, 0.0368900000, 0.0495236000, 0.0862266000, 0.1955603000, 0.5203918000", \ - "0.0444325000, 0.0463899000, 0.0517365000, 0.0655267000, 0.0996917000, 0.2029684000, 0.5221986000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0326816000, 0.0380278000, 0.0528769000, 0.0949499000, 0.2127001000, 0.5445365000, 1.4705417000", \ - "0.0326499000, 0.0380415000, 0.0528739000, 0.0950071000, 0.2126469000, 0.5444634000, 1.4702936000", \ - "0.0328896000, 0.0382257000, 0.0529898000, 0.0949351000, 0.2127193000, 0.5443967000, 1.4703441000", \ - "0.0381229000, 0.0428089000, 0.0563318000, 0.0962882000, 0.2125212000, 0.5439004000, 1.4721675000", \ - "0.0537071000, 0.0590121000, 0.0733323000, 0.1109946000, 0.2178862000, 0.5444000000, 1.4689073000", \ - "0.0909753000, 0.0973212000, 0.1141803000, 0.1560796000, 0.2582712000, 0.5546940000, 1.4733976000", \ - "0.1713096000, 0.1804965000, 0.2040538000, 0.2576381000, 0.3708842000, 0.6487396000, 1.4908287000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0390618000, 0.0390618000, 0.0390618000, 0.0390618000, 0.0390618000, 0.0390618000, 0.0390618000", \ - "0.0404211000, 0.0404211000, 0.0404543000, 0.0404543000, 0.0404987000, 0.0404987000, 0.0404987000", \ - "0.0410535000, 0.0421800000, 0.0421800000, 0.0421800000, 0.0421800000, 0.0421800000, 0.0421800000", \ - "0.0333756000, 0.0343068000, 0.0359228000, 0.0359228000, 0.0360499000, 0.0360499000, 0.0360499000", \ - "0.0182914000, 0.0195210000, 0.0219643000, 0.0219643000, 0.0219643000, 0.0219643000, 0.0220423000", \ - "-0.012612400, -0.010010700, -0.006449500, -0.006424700, -0.006141200, -0.006141200, -0.005339900", \ - "-0.081167100, -0.076063200, -0.065832100, -0.065831600, -0.065831600, -0.065831600, -0.065831600"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0051797000, 0.0060830800, 0.0086186500, 0.0157354000, 0.0357103000, 0.0917751000, 0.2491350000"); - values("0.0484219000, 0.0485147000, 0.0485171000, 0.0485171000, 0.0485171000, 0.0485171000, 0.0485171000", \ - "0.0533949000, 0.0533949000, 0.0534247000, 0.0534247000, 0.0534247000, 0.0534251000, 0.0534251000", \ - "0.0646496000, 0.0647647000, 0.0648978000, 0.0648978000, 0.0648978000, 0.0648978000, 0.0648978000", \ - "0.0851130000, 0.0853863000, 0.0859265000, 0.0859265000, 0.0859265000, 0.0859265000, 0.0859265000", \ - "0.1130100000, 0.1130100000, 0.1132486000, 0.1133599000, 0.1134744000, 0.1134744000, 0.1134744000", \ - "0.1453320000, 0.1460437000, 0.1463829000, 0.1463829000, 0.1465336000, 0.1465336000, 0.1465486000", \ - "0.1716185000, 0.1716185000, 0.1716185000, 0.1716185000, 0.1716185000, 0.1716185000, 0.1716185000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvn_8") { - leakage_power () { - value : 0.0026638000; - when : "!A&TE_B"; - } - leakage_power () { - value : 0.0046739000; - when : "!A&!TE_B"; - } - leakage_power () { - value : 0.0025556000; - when : "A&TE_B"; - } - leakage_power () { - value : 0.0084718000; - when : "A&!TE_B"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__einvn"; - cell_leakage_power : 0.0045912690; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0166200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0157440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163744000, 0.0163647000, 0.0163423000, 0.0163508000, 0.0163703000, 0.0164152000, 0.0165187000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014209600, -0.014196800, -0.014167100, -0.014179100, -0.014206600, -0.014269900, -0.014416000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0174950000; - } - pin ("TE_B") { - capacitance : 0.0102150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0091740000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0112570000; - } - pin ("Z") { - capacitance : 0.0095480000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("-0.000542600, -0.001793800, -0.005879200, -0.019860100, -0.066268500, -0.212041800, -0.660221600", \ - "-0.001866800, -0.003184100, -0.007212300, -0.020727400, -0.066263000, -0.211621900, -0.659557400", \ - "-0.003413200, -0.004794300, -0.008956400, -0.022487600, -0.067185900, -0.211647600, -0.659250300", \ - "-0.004418600, -0.005914600, -0.010428900, -0.024601600, -0.069095500, -0.212449700, -0.659304500", \ - "-0.003510400, -0.005104300, -0.010049900, -0.024987600, -0.070854100, -0.213820800, -0.659737400", \ - "0.0013210000, -0.000477700, -0.006023000, -0.022108500, -0.069722700, -0.215430100, -0.660812100", \ - "0.0147968000, 0.0127216000, 0.0065356000, -0.011862300, -0.063097400, -0.210221100, -0.660233400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("0.0343436000, 0.0366913000, 0.0434385000, 0.0616894000, 0.1113029000, 0.2564261000, 0.7029611000", \ - "0.0325324000, 0.0346132000, 0.0410233000, 0.0593957000, 0.1100794000, 0.2576834000, 0.7029788000", \ - "0.0317095000, 0.0336170000, 0.0393120000, 0.0570863000, 0.1076207000, 0.2553684000, 0.7007957000", \ - "0.0318943000, 0.0336042000, 0.0391228000, 0.0549594000, 0.1045387000, 0.2541777000, 0.7030298000", \ - "0.0328678000, 0.0344745000, 0.0394374000, 0.0549732000, 0.1028702000, 0.2500307000, 0.7008630000", \ - "0.0378642000, 0.0392593000, 0.0438688000, 0.0586630000, 0.1051469000, 0.2483303000, 0.6941527000", \ - "0.0531830000, 0.0550033000, 0.0564246000, 0.0696020000, 0.1138904000, 0.2548542000, 0.6945260000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("-0.024404200, -0.024256700, -0.023854400, -0.022997600, -0.021821300, -0.020731100, -0.020265800", \ - "-0.024861200, -0.024721500, -0.024335500, -0.023488700, -0.022336200, -0.021315000, -0.020755400", \ - "-0.025552000, -0.025415300, -0.025039200, -0.024194300, -0.022979000, -0.021879800, -0.021397200", \ - "-0.026547000, -0.026427000, -0.026132100, -0.025331700, -0.024046600, -0.022762300, -0.022079400", \ - "-0.027245800, -0.027155200, -0.026895300, -0.026232600, -0.024944200, -0.023388000, -0.022338800", \ - "-0.028069900, -0.028009700, -0.027804200, -0.027342200, -0.026329000, -0.024715300, -0.023179900", \ - "-0.027167800, -0.027110900, -0.026939100, -0.026547900, -0.025745800, -0.024460900, -0.022744700"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("0.0931472000, 0.0949367000, 0.1004563000, 0.1164231000, 0.1638052000, 0.3086101000, 0.7508503000", \ - "0.0928179000, 0.0946647000, 0.1001807000, 0.1161661000, 0.1635245000, 0.3082732000, 0.7507280000", \ - "0.0924680000, 0.0943794000, 0.0998929000, 0.1158473000, 0.1631844000, 0.3080272000, 0.7505776000", \ - "0.0922188000, 0.0940484000, 0.0996295000, 0.1156386000, 0.1628968000, 0.3077392000, 0.7502870000", \ - "0.0919925000, 0.0939164000, 0.0994818000, 0.1155828000, 0.1629824000, 0.3076121000, 0.7533140000", \ - "0.0929694000, 0.0947154000, 0.1000852000, 0.1158676000, 0.1636338000, 0.3080053000, 0.7505275000", \ - "0.0932103000, 0.0948711000, 0.0998412000, 0.1154130000, 0.1641014000, 0.3096952000, 0.7538047000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("0.0719402000, 0.0705341000, 0.0660170000, 0.0516651000, 0.0052045000, -0.141009200, -0.589398800", \ - "0.0717348000, 0.0702724000, 0.0657622000, 0.0514502000, 0.0049285000, -0.141267900, -0.589615500", \ - "0.0713750000, 0.0699281000, 0.0653521000, 0.0510996000, 0.0046065000, -0.141587100, -0.589865800", \ - "0.0711363000, 0.0696393000, 0.0650553000, 0.0508484000, 0.0043139000, -0.141860200, -0.590122800", \ - "0.0710117000, 0.0695306000, 0.0649531000, 0.0507096000, 0.0043133000, -0.141884200, -0.590227600", \ - "0.0699747000, 0.0683010000, 0.0631555000, 0.0473341000, 0.0046667000, -0.141405300, -0.589762700", \ - "0.0743787000, 0.0725959000, 0.0674994000, 0.0518682000, 0.0040218000, -0.141513800, -0.588323800"); - } - related_pin : "TE_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015303700, 0.0046840630, 0.0143367000, 0.0438808900, 0.1343080000, 0.4110817000"); - values("-0.026414500, -0.026422800, -0.026454300, -0.026518000, -0.026619300, -0.026687900, -0.026740200", \ - "-0.026983400, -0.026996200, -0.027021400, -0.027092500, -0.027246100, -0.027348000, -0.027378500", \ - "-0.027619700, -0.027632800, -0.027673500, -0.027754300, -0.027862000, -0.027968800, -0.028024000", \ - "-0.028243800, -0.028257400, -0.028288600, -0.028364000, -0.028487200, -0.028594100, -0.028667300", \ - "-0.028363700, -0.028374200, -0.028404400, -0.028415800, -0.028506700, -0.028615900, -0.028669800", \ - "-0.028764400, -0.028775300, -0.028863000, -0.028894200, -0.028974900, -0.029043600, -0.029105200", \ - "-0.027633800, -0.027643500, -0.027668900, -0.027735700, -0.027843900, -0.027911100, -0.027947700"); - } - when : "A"; - } - max_capacitance : 0.4110820000; - max_transition : 1.4990900000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE_B)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0200785000, 0.0213269000, 0.0249244000, 0.0348871000, 0.0632746000, 0.1483306000, 0.4102300000", \ - "0.0238200000, 0.0250073000, 0.0285439000, 0.0387231000, 0.0674749000, 0.1529314000, 0.4143715000", \ - "0.0305476000, 0.0322422000, 0.0369782000, 0.0482123000, 0.0772671000, 0.1631300000, 0.4243771000", \ - "0.0359457000, 0.0385956000, 0.0458273000, 0.0635598000, 0.1002728000, 0.1863151000, 0.4487671000", \ - "0.0350484000, 0.0390967000, 0.0502813000, 0.0774414000, 0.1344316000, 0.2406000000, 0.5024188000", \ - "0.0151837000, 0.0213948000, 0.0382578000, 0.0793338000, 0.1660368000, 0.3296001000, 0.6277528000", \ - "-0.055534000, -0.045856500, -0.020442600, 0.0409927000, 0.1726441000, 0.4219640000, 0.8682309000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0386891000, 0.0422485000, 0.0527742000, 0.0816134000, 0.1602431000, 0.3918656000, 1.0926131000", \ - "0.0411820000, 0.0443209000, 0.0542250000, 0.0829337000, 0.1632846000, 0.3960668000, 1.1080978000", \ - "0.0526101000, 0.0554954000, 0.0641590000, 0.0917106000, 0.1715993000, 0.4057785000, 1.1129468000", \ - "0.0767737000, 0.0808594000, 0.0921242000, 0.1179492000, 0.1953700000, 0.4313495000, 1.1410801000", \ - "0.1134927000, 0.1193417000, 0.1357567000, 0.1758650000, 0.2607324000, 0.4922853000, 1.2039170000", \ - "0.1771918000, 0.1856443000, 0.2092536000, 0.2684798000, 0.3959658000, 0.6442429000, 1.3477317000", \ - "0.3015049000, 0.3129653000, 0.3450505000, 0.4267750000, 0.6128043000, 0.9779321000, 1.6958310000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0124242000, 0.0138034000, 0.0180263000, 0.0310390000, 0.0709349000, 0.1931130000, 0.5659596000", \ - "0.0124186000, 0.0137611000, 0.0179779000, 0.0310462000, 0.0708493000, 0.1930958000, 0.5660289000", \ - "0.0173610000, 0.0190448000, 0.0222803000, 0.0327330000, 0.0708054000, 0.1930828000, 0.5659435000", \ - "0.0248100000, 0.0267238000, 0.0321266000, 0.0458824000, 0.0785394000, 0.1932168000, 0.5662347000", \ - "0.0418850000, 0.0445091000, 0.0522130000, 0.0705354000, 0.1122652000, 0.2105576000, 0.5652069000", \ - "0.0721819000, 0.0764395000, 0.0880187000, 0.1160865000, 0.1736412000, 0.2904967000, 0.5936395000", \ - "0.1302762000, 0.1368934000, 0.1545725000, 0.1971347000, 0.2820989000, 0.4460610000, 0.7729616000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0350564000, 0.0388117000, 0.0503451000, 0.0846449000, 0.1883690000, 0.5041829000, 1.4760169000", \ - "0.0346796000, 0.0384621000, 0.0500557000, 0.0844519000, 0.1884524000, 0.5063990000, 1.4811029000", \ - "0.0349158000, 0.0382388000, 0.0493168000, 0.0841096000, 0.1884471000, 0.5035287000, 1.4703796000", \ - "0.0501949000, 0.0522522000, 0.0598364000, 0.0874369000, 0.1880971000, 0.5060959000, 1.4798759000", \ - "0.0654756000, 0.0705499000, 0.0845356000, 0.1198305000, 0.1992677000, 0.5037492000, 1.4790756000", \ - "0.0981762000, 0.1053352000, 0.1245395000, 0.1701850000, 0.2709481000, 0.5262291000, 1.4678336000", \ - "0.1594786000, 0.1658679000, 0.1911762000, 0.2562424000, 0.4010559000, 0.6793084000, 1.4990900000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.1132571000, 0.1150747000, 0.1202079000, 0.1333412000, 0.1662244000, 0.2553275000, 0.5166405000", \ - "0.1176696000, 0.1194776000, 0.1247487000, 0.1378449000, 0.1707286000, 0.2597295000, 0.5214629000", \ - "0.1298186000, 0.1316282000, 0.1368030000, 0.1499121000, 0.1828489000, 0.2718765000, 0.5334425000", \ - "0.1605454000, 0.1624992000, 0.1674605000, 0.1806056000, 0.2136622000, 0.3025160000, 0.5637624000", \ - "0.2283706000, 0.2303850000, 0.2359919000, 0.2499508000, 0.2834514000, 0.3726613000, 0.6347752000", \ - "0.3382103000, 0.3409167000, 0.3482551000, 0.3660113000, 0.4054149000, 0.4977986000, 0.7601167000", \ - "0.5047454000, 0.5084328000, 0.5188618000, 0.5434107000, 0.5928868000, 0.6945608000, 0.9608808000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0615433000, 0.0644310000, 0.0727848000, 0.0979924000, 0.1736542000, 0.4031527000, 1.1042974000", \ - "0.0664364000, 0.0692304000, 0.0776937000, 0.1028415000, 0.1786600000, 0.4079038000, 1.1117822000", \ - "0.0792817000, 0.0821923000, 0.0906529000, 0.1158720000, 0.1916570000, 0.4210106000, 1.1217877000", \ - "0.1056301000, 0.1088216000, 0.1180887000, 0.1439740000, 0.2199101000, 0.4492516000, 1.1500920000", \ - "0.1491474000, 0.1532846000, 0.1650890000, 0.1967720000, 0.2784279000, 0.5080976000, 1.2127463000", \ - "0.2147783000, 0.2212422000, 0.2408011000, 0.2870258000, 0.3932267000, 0.6398820000, 1.3441271000", \ - "0.2964906000, 0.3084152000, 0.3425143000, 0.4240038000, 0.5911752000, 0.9139303000, 1.6464120000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0245032000, 0.0257580000, 0.0298736000, 0.0421644000, 0.0797598000, 0.1973428000, 0.5669944000", \ - "0.0245360000, 0.0258231000, 0.0298931000, 0.0422246000, 0.0796898000, 0.1973378000, 0.5666837000", \ - "0.0245235000, 0.0258493000, 0.0298058000, 0.0421791000, 0.0797414000, 0.1974448000, 0.5669637000", \ - "0.0245740000, 0.0258563000, 0.0298187000, 0.0421473000, 0.0797599000, 0.1971290000, 0.5668001000", \ - "0.0275406000, 0.0287569000, 0.0324965000, 0.0439973000, 0.0806079000, 0.1975741000, 0.5655778000", \ - "0.0383843000, 0.0395834000, 0.0433467000, 0.0544946000, 0.0893675000, 0.2018272000, 0.5666393000", \ - "0.0570147000, 0.0581179000, 0.0618696000, 0.0735970000, 0.1069795000, 0.2125176000, 0.5696068000"); - } - related_pin : "TE_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0383790000, 0.0419054000, 0.0528031000, 0.0862700000, 0.1892126000, 0.5041806000, 1.4678057000", \ - "0.0383583000, 0.0419065000, 0.0528820000, 0.0862987000, 0.1892392000, 0.5036394000, 1.4707685000", \ - "0.0386120000, 0.0421465000, 0.0530026000, 0.0862713000, 0.1890251000, 0.5037910000, 1.4715893000", \ - "0.0426132000, 0.0458389000, 0.0558674000, 0.0879485000, 0.1892641000, 0.5038474000, 1.4714903000", \ - "0.0572571000, 0.0606630000, 0.0713266000, 0.1024303000, 0.1958530000, 0.5041518000, 1.4752350000", \ - "0.0932572000, 0.0974455000, 0.1094195000, 0.1433728000, 0.2364987000, 0.5173400000, 1.4699401000", \ - "0.1738269000, 0.1795826000, 0.1951380000, 0.2383064000, 0.3406264000, 0.6095058000, 1.4886078000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0493649000, 0.0493649000, 0.0494159000, 0.0494719000, 0.0494719000, 0.0494719000, 0.0494719000", \ - "0.0523882000, 0.0523882000, 0.0523882000, 0.0523882000, 0.0523882000, 0.0523882000, 0.0523882000", \ - "0.0554330000, 0.0554330000, 0.0554330000, 0.0555271000, 0.0555271000, 0.0555271000, 0.0555271000", \ - "0.0481344000, 0.0481344000, 0.0481344000, 0.0482617000, 0.0482617000, 0.0482617000, 0.0482617000", \ - "0.0323804000, 0.0323804000, 0.0323804000, 0.0327257000, 0.0327257000, 0.0327257000, 0.0327257000", \ - "0.0040551000, 0.0040551000, 0.0040551000, 0.0040551000, 0.0040551000, 0.0040551000, 0.0040551000", \ - "-0.058854800, -0.058854800, -0.058854800, -0.058854800, -0.058854800, -0.058854800, -0.058854800"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0100477000, 0.0110781000, 0.0142318000, 0.0238844000, 0.0534286000, 0.1438560000, 0.4206290000"); - values("0.0715976000, 0.0717451000, 0.0717451000, 0.0717451000, 0.0717451000, 0.0717451000, 0.0717451000", \ - "0.0761040000, 0.0761634000, 0.0761634000, 0.0761634000, 0.0761634000, 0.0761634000, 0.0761634000", \ - "0.0872207000, 0.0872207000, 0.0872207000, 0.0872207000, 0.0872207000, 0.0872207000, 0.0872207000", \ - "0.1126311000, 0.1129038000, 0.1129038000, 0.1129038000, 0.1129038000, 0.1129038000, 0.1129038000", \ - "0.1540013000, 0.1547439000, 0.1548757000, 0.1548757000, 0.1548757000, 0.1551113000, 0.1551560000", \ - "0.2121128000, 0.2121128000, 0.2121128000, 0.2121128000, 0.2121128000, 0.2121128000, 0.2121128000", \ - "0.2750643000, 0.2750643000, 0.2750643000, 0.2750643000, 0.2750643000, 0.2753209000, 0.2757243000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE_B"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvp_1") { - leakage_power () { - value : 0.0011295000; - when : "!A&TE"; - } - leakage_power () { - value : 0.0004082000; - when : "!A&!TE"; - } - leakage_power () { - value : 0.0034515000; - when : "A&TE"; - } - leakage_power () { - value : 0.0004579000; - when : "A&!TE"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__einvp"; - cell_leakage_power : 0.0013617660; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033756000, 0.0033690000, 0.0033538000, 0.0033574000, 0.0033657000, 0.0033850000, 0.0034294000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002512300, -0.002513700, -0.002516900, -0.002511300, -0.002498300, -0.002468300, -0.002399300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025280000; - } - pin ("TE") { - capacitance : 0.0025230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0025040000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025410000; - } - pin ("Z") { - capacitance : 0.0019260000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0008765000, -8.94000e-05, -0.002427100, -0.008042100, -0.021193400, -0.051738900, -0.122484200", \ - "0.0006663000, -0.000265700, -0.002542400, -0.008071900, -0.021166100, -0.051683300, -0.122425400", \ - "0.0003903000, -0.000541100, -0.002780900, -0.008220900, -0.021229000, -0.051680300, -0.122392300", \ - "0.0001374000, -0.000831000, -0.003081000, -0.008502700, -0.021413900, -0.051778100, -0.122410600", \ - "0.0001485000, -0.000849400, -0.003216300, -0.008806800, -0.021705600, -0.051946700, -0.122527700", \ - "0.0007789000, -0.000350300, -0.002891800, -0.008539900, -0.021684500, -0.052055000, -0.122628900", \ - "0.0028951000, 0.0019253000, -0.001414800, -0.007492900, -0.021098200, -0.051871700, -0.122726200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0057720000, 0.0069877000, 0.0096440000, 0.0154772000, 0.0286448000, 0.0588781000, 0.1287527000", \ - "0.0054773000, 0.0066455000, 0.0093804000, 0.0152440000, 0.0285351000, 0.0590695000, 0.1295636000", \ - "0.0052442000, 0.0064157000, 0.0090149000, 0.0149295000, 0.0284267000, 0.0587185000, 0.1287329000", \ - "0.0051653000, 0.0062461000, 0.0087998000, 0.0146080000, 0.0279276000, 0.0589001000, 0.1289854000", \ - "0.0054935000, 0.0065615000, 0.0090061000, 0.0146477000, 0.0277184000, 0.0580026000, 0.1291336000", \ - "0.0060624000, 0.0070333000, 0.0094520000, 0.0152577000, 0.0281691000, 0.0578583000, 0.1278804000", \ - "0.0075321000, 0.0085211000, 0.0107309000, 0.0160516000, 0.0288830000, 0.0586406000, 0.1283757000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0065138000, 0.0065983000, 0.0067331000, 0.0069263000, 0.0070405000, 0.0071303000, 0.0071704000", \ - "0.0063183000, 0.0064066000, 0.0065477000, 0.0067143000, 0.0068566000, 0.0069435000, 0.0069838000", \ - "0.0061028000, 0.0061883000, 0.0063270000, 0.0064986000, 0.0066418000, 0.0067303000, 0.0067769000", \ - "0.0059648000, 0.0060495000, 0.0061904000, 0.0063694000, 0.0065283000, 0.0066309000, 0.0066818000", \ - "0.0058976000, 0.0059750000, 0.0061435000, 0.0063305000, 0.0065144000, 0.0066385000, 0.0067047000", \ - "0.0059868000, 0.0060598000, 0.0061864000, 0.0063599000, 0.0066136000, 0.0067702000, 0.0068578000", \ - "0.0066937000, 0.0067613000, 0.0069150000, 0.0070846000, 0.0072738000, 0.0074346000, 0.0075237000"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0102566000, 0.0113193000, 0.0137528000, 0.0194259000, 0.0324071000, 0.0626120000, 0.1334510000", \ - "0.0101285000, 0.0111942000, 0.0136413000, 0.0192923000, 0.0322892000, 0.0624952000, 0.1323315000", \ - "0.0099635000, 0.0110306000, 0.0134765000, 0.0191431000, 0.0321179000, 0.0623274000, 0.1321921000", \ - "0.0098017000, 0.0108700000, 0.0133032000, 0.0189820000, 0.0319683000, 0.0621256000, 0.1319931000", \ - "0.0097311000, 0.0107954000, 0.0132354000, 0.0188414000, 0.0319537000, 0.0620809000, 0.1320816000", \ - "0.0101383000, 0.0111506000, 0.0136101000, 0.0191698000, 0.0322362000, 0.0624132000, 0.1327195000", \ - "0.0110013000, 0.0119496000, 0.0144001000, 0.0200526000, 0.0332205000, 0.0637037000, 0.1329077000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0045931000, 0.0035641000, 0.0011180000, -0.004578900, -0.017779700, -0.048355400, -0.119122000", \ - "0.0044645000, 0.0034349000, 0.0009909000, -0.004705500, -0.017906500, -0.048481100, -0.119231200", \ - "0.0042897000, 0.0032635000, 0.0008211000, -0.004879600, -0.018081700, -0.048652400, -0.119427100", \ - "0.0041262000, 0.0031024000, 0.0006556000, -0.005048500, -0.018252900, -0.048825500, -0.119596400", \ - "0.0041983000, 0.0031191000, 0.0006426000, -0.005107700, -0.018312500, -0.048879500, -0.119661900", \ - "0.0044075000, 0.0033483000, 0.0008503000, -0.004843500, -0.018086700, -0.048674100, -0.119468500", \ - "0.0052520000, 0.0041767000, 0.0016894000, -0.004026600, -0.017230700, -0.047811400, -0.118646900"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0063737000, 0.0063654000, 0.0063534000, 0.0063362000, 0.0063208000, 0.0063110000, 0.0063054000", \ - "0.0061304000, 0.0061281000, 0.0061303000, 0.0061198000, 0.0061098000, 0.0061021000, 0.0060975000", \ - "0.0059055000, 0.0059112000, 0.0059099000, 0.0059064000, 0.0058759000, 0.0058696000, 0.0058654000", \ - "0.0058047000, 0.0058048000, 0.0057664000, 0.0057615000, 0.0057654000, 0.0057632000, 0.0057605000", \ - "0.0057972000, 0.0058020000, 0.0058059000, 0.0058075000, 0.0058096000, 0.0058098000, 0.0058081000", \ - "0.0059581000, 0.0059485000, 0.0059616000, 0.0059743000, 0.0059859000, 0.0059876000, 0.0059876000", \ - "0.0066527000, 0.0066541000, 0.0066572000, 0.0066590000, 0.0066620000, 0.0066616000, 0.0066584000"); - } - when : "A"; - } - max_capacitance : 0.0769140000; - max_transition : 1.4956790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE')"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0223266000, 0.0260327000, 0.0341734000, 0.0524927000, 0.0943654000, 0.1903172000, 0.4147047000", \ - "0.0262551000, 0.0300544000, 0.0382723000, 0.0569253000, 0.0989941000, 0.1950696000, 0.4174192000", \ - "0.0349109000, 0.0395693000, 0.0483845000, 0.0669926000, 0.1092222000, 0.2057435000, 0.4298020000", \ - "0.0450880000, 0.0523065000, 0.0660931000, 0.0904723000, 0.1332810000, 0.2301472000, 0.4549277000", \ - "0.0538585000, 0.0647504000, 0.0857961000, 0.1236308000, 0.1850460000, 0.2849172000, 0.5076761000", \ - "0.0529381000, 0.0696592000, 0.1023228000, 0.1604135000, 0.2535533000, 0.4026699000, 0.6400114000", \ - "0.0203452000, 0.0457835000, 0.0942993000, 0.1828007000, 0.3288357000, 0.5562002000, 0.9063929000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0465366000, 0.0569142000, 0.0792561000, 0.1282820000, 0.2389581000, 0.4929033000, 1.0794897000", \ - "0.0494415000, 0.0592396000, 0.0820731000, 0.1319413000, 0.2432439000, 0.4995974000, 1.0945080000", \ - "0.0599530000, 0.0695034000, 0.0913286000, 0.1410716000, 0.2546259000, 0.5086210000, 1.0954879000", \ - "0.0866991000, 0.0971316000, 0.1183029000, 0.1663028000, 0.2785669000, 0.5373237000, 1.1279144000", \ - "0.1273004000, 0.1440078000, 0.1753482000, 0.2318366000, 0.3406466000, 0.5969679000, 1.1877952000", \ - "0.1916957000, 0.2160414000, 0.2643992000, 0.3500747000, 0.4933094000, 0.7420073000, 1.3301674000", \ - "0.3039370000, 0.3385333000, 0.4071403000, 0.5341831000, 0.7449804000, 1.0926747000, 1.6806500000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0154315000, 0.0198294000, 0.0302867000, 0.0543362000, 0.1095531000, 0.2381089000, 0.5386717000", \ - "0.0152704000, 0.0198008000, 0.0302069000, 0.0541818000, 0.1097448000, 0.2377966000, 0.5358289000", \ - "0.0204151000, 0.0235598000, 0.0320689000, 0.0544992000, 0.1096745000, 0.2377873000, 0.5342827000", \ - "0.0314595000, 0.0363410000, 0.0462493000, 0.0645976000, 0.1125985000, 0.2378462000, 0.5447098000", \ - "0.0525152000, 0.0605625000, 0.0739941000, 0.0979689000, 0.1425258000, 0.2483381000, 0.5418054000", \ - "0.0894961000, 0.1007286000, 0.1216853000, 0.1584162000, 0.2207041000, 0.3250878000, 0.5612714000", \ - "0.1581557000, 0.1738461000, 0.2073342000, 0.2609153000, 0.3523635000, 0.4977913000, 0.7362221000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0442746000, 0.0568734000, 0.0855355000, 0.1511456000, 0.3016360000, 0.6531520000, 1.4647397000", \ - "0.0442374000, 0.0567118000, 0.0854151000, 0.1510084000, 0.3021058000, 0.6541296000, 1.4775979000", \ - "0.0439356000, 0.0562309000, 0.0852262000, 0.1513740000, 0.3039994000, 0.6519797000, 1.4639673000", \ - "0.0567899000, 0.0655169000, 0.0889931000, 0.1507569000, 0.3020668000, 0.6568812000, 1.4644308000", \ - "0.0827414000, 0.0964463000, 0.1215713000, 0.1704485000, 0.3051229000, 0.6516133000, 1.4693590000", \ - "0.1258733000, 0.1444819000, 0.1803313000, 0.2439733000, 0.3615113000, 0.6642621000, 1.4628984000", \ - "0.1959032000, 0.2239057000, 0.2786789000, 0.3729352000, 0.5303680000, 0.7969249000, 1.4956791000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0228284000, 0.0262518000, 0.0341247000, 0.0523139000, 0.0939119000, 0.1900515000, 0.4169665000", \ - "0.0275263000, 0.0309529000, 0.0388376000, 0.0570211000, 0.0986161000, 0.1948166000, 0.4198072000", \ - "0.0359757000, 0.0399706000, 0.0483934000, 0.0666739000, 0.1083099000, 0.2048085000, 0.4285109000", \ - "0.0477014000, 0.0533803000, 0.0648173000, 0.0867600000, 0.1296300000, 0.2259272000, 0.4503113000", \ - "0.0587325000, 0.0680825000, 0.0859162000, 0.1183285000, 0.1734164000, 0.2745889000, 0.4987217000", \ - "0.0562574000, 0.0722359000, 0.1015708000, 0.1539652000, 0.2381124000, 0.3729858000, 0.6101766000", \ - "-0.001194500, 0.0258967000, 0.0783083000, 0.1664719000, 0.3048459000, 0.5131316000, 0.8351755000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0849459000, 0.0939274000, 0.1146115000, 0.1620553000, 0.2714891000, 0.5247028000, 1.1177302000", \ - "0.0895630000, 0.0985022000, 0.1192019000, 0.1670039000, 0.2761529000, 0.5293155000, 1.1159355000", \ - "0.1008529000, 0.1097254000, 0.1303958000, 0.1779803000, 0.2878102000, 0.5409103000, 1.1269099000", \ - "0.1206004000, 0.1295583000, 0.1501575000, 0.1978230000, 0.3071912000, 0.5610373000, 1.1481247000", \ - "0.1459842000, 0.1552759000, 0.1760220000, 0.2238060000, 0.3334603000, 0.5870056000, 1.1761182000", \ - "0.1733281000, 0.1829082000, 0.2039904000, 0.2517101000, 0.3613971000, 0.6147327000, 1.2067721000", \ - "0.1845846000, 0.1954631000, 0.2185333000, 0.2670935000, 0.3766547000, 0.6323662000, 1.2182962000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0157930000, 0.0202951000, 0.0306287000, 0.0545442000, 0.1098711000, 0.2380818000, 0.5379999000", \ - "0.0159918000, 0.0204176000, 0.0306730000, 0.0545545000, 0.1097931000, 0.2379805000, 0.5462570000", \ - "0.0193642000, 0.0230978000, 0.0323869000, 0.0548926000, 0.1097689000, 0.2398589000, 0.5345239000", \ - "0.0287218000, 0.0330326000, 0.0421973000, 0.0619191000, 0.1119954000, 0.2400973000, 0.5370345000", \ - "0.0479278000, 0.0535546000, 0.0651402000, 0.0869131000, 0.1319250000, 0.2440748000, 0.5351708000", \ - "0.0843481000, 0.0925576000, 0.1085410000, 0.1379907000, 0.1903953000, 0.2972216000, 0.5536734000", \ - "0.1569787000, 0.1690751000, 0.1927179000, 0.2338161000, 0.3051406000, 0.4342928000, 0.6853034000"); - } - related_pin : "TE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0449534000, 0.0573005000, 0.0854690000, 0.1513441000, 0.3022954000, 0.6528392000, 1.4736837000", \ - "0.0450390000, 0.0572498000, 0.0855794000, 0.1513825000, 0.3023044000, 0.6526131000, 1.4673934000", \ - "0.0451488000, 0.0572698000, 0.0856028000, 0.1509475000, 0.3025189000, 0.6525748000, 1.4644724000", \ - "0.0455333000, 0.0576674000, 0.0856877000, 0.1510688000, 0.3022771000, 0.6516891000, 1.4620725000", \ - "0.0462289000, 0.0582763000, 0.0862043000, 0.1511837000, 0.3023785000, 0.6533124000, 1.4649320000", \ - "0.0486661000, 0.0604411000, 0.0873929000, 0.1517591000, 0.3036300000, 0.6519800000, 1.4677347000", \ - "0.0568299000, 0.0676526000, 0.0932422000, 0.1546368000, 0.3035054000, 0.6555236000, 1.4594637000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0957091000, 0.0957272000, 0.0957272000, 0.0957272000, 0.0957272000, 0.0957344000, 0.0959150000", \ - "0.1008743000, 0.1008743000, 0.1008743000, 0.1008743000, 0.1008883000, 0.1008883000, 0.1008883000", \ - "0.1156881000, 0.1156902000, 0.1156902000, 0.1156902000, 0.1156902000, 0.1156902000, 0.1157016000", \ - "0.1487550000, 0.1487550000, 0.1494851000, 0.1494851000, 0.1494851000, 0.1494851000, 0.1494851000", \ - "0.2121328000, 0.2121328000, 0.2121328000, 0.2121328000, 0.2121328000, 0.2121328000, 0.2121328000", \ - "0.3090166000, 0.3090931000, 0.3090931000, 0.3090931000, 0.3090931000, 0.3092014000, 0.3092019000", \ - "0.4571019000, 0.4571019000, 0.4595216000, 0.4595216000, 0.4595216000, 0.4595216000, 0.4595216000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0024256000, 0.0030829800, 0.0046046600, 0.0081269800, 0.0162803000, 0.0351533000, 0.0788399000"); - values("0.0128623000, 0.0128646000, 0.0128646000, 0.0128646000, 0.0128646000, 0.0128646000, 0.0128646000", \ - "0.0139366000, 0.0139367000, 0.0139367000, 0.0139367000, 0.0139367000, 0.0139367000, 0.0139367000", \ - "0.0132378000, 0.0132378000, 0.0132378000, 0.0132378000, 0.0132817000, 0.0132817000, 0.0132817000", \ - "0.0164138000, 0.0164174000, 0.0164218000, 0.0164218000, 0.0164218000, 0.0164218000, 0.0164218000", \ - "0.0169801000, 0.0169801000, 0.0169810000, 0.0170204000, 0.0170204000, 0.0170204000, 0.0170352000", \ - "0.0283404000, 0.0283404000, 0.0283404000, 0.0283404000, 0.0283404000, 0.0283404000, 0.0283404000", \ - "0.0439027000, 0.0439027000, 0.0440720000, 0.0441733000, 0.0441733000, 0.0441733000, 0.0441733000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvp_2") { - leakage_power () { - value : 0.0055910000; - when : "!A&TE"; - } - leakage_power () { - value : 0.0004117000; - when : "!A&!TE"; - } - leakage_power () { - value : 0.0088478000; - when : "A&TE"; - } - leakage_power () { - value : 0.0004602000; - when : "A&!TE"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__einvp"; - cell_leakage_power : 0.0038276620; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0057934000, 0.0057726000, 0.0057248000, 0.0057386000, 0.0057706000, 0.0058444000, 0.0060144000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004058100, -0.004056700, -0.004053400, -0.004062400, -0.004083000, -0.004130700, -0.004240500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045290000; - } - pin ("TE") { - capacitance : 0.0036180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0036640000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035710000; - } - pin ("Z") { - capacitance : 0.0024370000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("-0.000322900, -0.001329900, -0.004151000, -0.011936200, -0.032353800, -0.084656300, -0.217851300", \ - "-0.000714600, -0.001694500, -0.004430200, -0.012025200, -0.032299100, -0.084520800, -0.217677400", \ - "-0.001127800, -0.002177400, -0.004918300, -0.012374500, -0.032413200, -0.084489900, -0.217582800", \ - "-0.001406100, -0.002550500, -0.005384600, -0.012880700, -0.032808100, -0.084643500, -0.217594800", \ - "-0.001127000, -0.002385800, -0.005416900, -0.013377400, -0.033276000, -0.084978200, -0.217729600", \ - "0.0001891000, -0.001132200, -0.004436400, -0.012624900, -0.033250700, -0.085276900, -0.217928800", \ - "0.0045490000, 0.0030728000, -0.001436300, -0.010328500, -0.031766100, -0.084576000, -0.217837600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("0.0075217000, 0.0091433000, 0.0128335000, 0.0213456000, 0.0419105000, 0.0937692000, 0.2253420000", \ - "0.0071486000, 0.0086753000, 0.0122047000, 0.0208006000, 0.0419421000, 0.0937220000, 0.2253611000", \ - "0.0068894000, 0.0082480000, 0.0117370000, 0.0202868000, 0.0412899000, 0.0935623000, 0.2256901000", \ - "0.0068911000, 0.0082025000, 0.0115016000, 0.0197476000, 0.0406458000, 0.0930538000, 0.2251201000", \ - "0.0072237000, 0.0084369000, 0.0115942000, 0.0198447000, 0.0401071000, 0.0924914000, 0.2253551000", \ - "0.0085567000, 0.0096732000, 0.0125961000, 0.0204217000, 0.0404120000, 0.0918753000, 0.2239929000", \ - "0.0121014000, 0.0120793000, 0.0149207000, 0.0222688000, 0.0424136000, 0.0933947000, 0.2239370000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("0.0080826000, 0.0082279000, 0.0084918000, 0.0088885000, 0.0092735000, 0.0095206000, 0.0096380000", \ - "0.0078811000, 0.0080202000, 0.0082923000, 0.0086855000, 0.0090690000, 0.0093195000, 0.0094436000", \ - "0.0076034000, 0.0077384000, 0.0080100000, 0.0084255000, 0.0088284000, 0.0090896000, 0.0092205000", \ - "0.0074169000, 0.0075440000, 0.0078011000, 0.0082035000, 0.0086234000, 0.0089063000, 0.0090541000", \ - "0.0072746000, 0.0074118000, 0.0076514000, 0.0080393000, 0.0084846000, 0.0088074000, 0.0089869000", \ - "0.0075315000, 0.0076313000, 0.0078242000, 0.0081619000, 0.0086585000, 0.0090140000, 0.0092527000", \ - "0.0088079000, 0.0088921000, 0.0091084000, 0.0094692000, 0.0099801000, 0.0103736000, 0.0106445000"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("0.0162005000, 0.0174484000, 0.0206004000, 0.0286293000, 0.0489153000, 0.1009884000, 0.2338434000", \ - "0.0160249000, 0.0172674000, 0.0204197000, 0.0284549000, 0.0487237000, 0.1010860000, 0.2320047000", \ - "0.0157913000, 0.0170338000, 0.0201832000, 0.0281888000, 0.0484813000, 0.1001981000, 0.2320118000", \ - "0.0155788000, 0.0168212000, 0.0199646000, 0.0279767000, 0.0484515000, 0.0999918000, 0.2315303000", \ - "0.0155795000, 0.0168294000, 0.0199596000, 0.0279044000, 0.0483390000, 0.1000194000, 0.2322795000", \ - "0.0161585000, 0.0173922000, 0.0205647000, 0.0283705000, 0.0488547000, 0.1004148000, 0.2319328000", \ - "0.0176812000, 0.0189240000, 0.0221041000, 0.0302217000, 0.0506008000, 0.1022752000, 0.2335691000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("0.0077079000, 0.0067538000, 0.0040383000, -0.003878900, -0.024445100, -0.076804600, -0.210030100", \ - "0.0075103000, 0.0065773000, 0.0038539000, -0.004053900, -0.024624200, -0.076975800, -0.210235000", \ - "0.0072595000, 0.0062944000, 0.0035976000, -0.004293900, -0.024862600, -0.077223800, -0.210451300", \ - "0.0073232000, 0.0061810000, 0.0033564000, -0.004488700, -0.025063700, -0.077425000, -0.210654900", \ - "0.0080765000, 0.0068341000, 0.0036543000, -0.004535700, -0.025075900, -0.077443600, -0.210670500", \ - "0.0085588000, 0.0073178000, 0.0041207000, -0.003985500, -0.024575700, -0.077011900, -0.210242800", \ - "0.0101163000, 0.0088432000, 0.0056742000, -0.002421400, -0.023041700, -0.075420800, -0.208723900"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012719470, 0.0032357010, 0.0082312820, 0.0209395200, 0.0532679300, 0.1355080000"); - values("0.0072581000, 0.0072467000, 0.0072201000, 0.0071819000, 0.0071523000, 0.0071240000, 0.0071161000", \ - "0.0070672000, 0.0070585000, 0.0070387000, 0.0070099000, 0.0069961000, 0.0069791000, 0.0069703000", \ - "0.0068230000, 0.0068196000, 0.0068124000, 0.0068022000, 0.0067935000, 0.0067833000, 0.0067764000", \ - "0.0066693000, 0.0066666000, 0.0066633000, 0.0066532000, 0.0066430000, 0.0066326000, 0.0066252000", \ - "0.0066126000, 0.0066112000, 0.0066068000, 0.0066043000, 0.0065999000, 0.0065923000, 0.0065879000", \ - "0.0070001000, 0.0069998000, 0.0069891000, 0.0069809000, 0.0069758000, 0.0069928000, 0.0069905000", \ - "0.0083516000, 0.0083523000, 0.0083458000, 0.0083288000, 0.0083112000, 0.0083150000, 0.0083030000"); - } - when : "A"; - } - max_capacitance : 0.1355080000; - max_transition : 1.5011470000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE')"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0181941000, 0.0209960000, 0.0275078000, 0.0429660000, 0.0811908000, 0.1775419000, 0.4217036000", \ - "0.0221828000, 0.0248845000, 0.0314998000, 0.0472833000, 0.0856958000, 0.1826289000, 0.4264070000", \ - "0.0291811000, 0.0331469000, 0.0414515000, 0.0575399000, 0.0960185000, 0.1927151000, 0.4369055000", \ - "0.0360491000, 0.0422184000, 0.0550245000, 0.0790308000, 0.1204351000, 0.2174841000, 0.4636624000", \ - "0.0394115000, 0.0489244000, 0.0683415000, 0.1058548000, 0.1687982000, 0.2742421000, 0.5187276000", \ - "0.0297921000, 0.0445077000, 0.0747516000, 0.1317909000, 0.2293079000, 0.3879708000, 0.6513637000", \ - "-0.017261200, 0.0052953000, 0.0504983000, 0.1371339000, 0.2885832000, 0.5329747000, 0.9230652000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0327226000, 0.0402957000, 0.0578624000, 0.0989983000, 0.1989255000, 0.4497841000, 1.0868619000", \ - "0.0360859000, 0.0431028000, 0.0599749000, 0.1019566000, 0.2032949000, 0.4547398000, 1.0923489000", \ - "0.0478177000, 0.0539123000, 0.0701025000, 0.1111115000, 0.2132610000, 0.4653596000, 1.1101672000", \ - "0.0697448000, 0.0790917000, 0.0981881000, 0.1375695000, 0.2376037000, 0.4924608000, 1.1298977000", \ - "0.1028425000, 0.1169301000, 0.1461216000, 0.2017927000, 0.3007937000, 0.5543219000, 1.1950589000", \ - "0.1577438000, 0.1781110000, 0.2215438000, 0.3047332000, 0.4479132000, 0.7044040000, 1.3419988000", \ - "0.2588841000, 0.2868751000, 0.3476446000, 0.4676260000, 0.6846000000, 1.0470037000, 1.6900298000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0105719000, 0.0137801000, 0.0218610000, 0.0422075000, 0.0944292000, 0.2261441000, 0.5596437000", \ - "0.0107978000, 0.0137551000, 0.0217801000, 0.0422892000, 0.0941946000, 0.2253562000, 0.5602520000", \ - "0.0155983000, 0.0187956000, 0.0250671000, 0.0429799000, 0.0940887000, 0.2255503000, 0.5587728000", \ - "0.0247949000, 0.0288416000, 0.0376240000, 0.0560946000, 0.0979532000, 0.2253548000, 0.5599562000", \ - "0.0418934000, 0.0482873000, 0.0620382000, 0.0855983000, 0.1304873000, 0.2361505000, 0.5592702000", \ - "0.0738134000, 0.0829285000, 0.1032616000, 0.1394582000, 0.2027720000, 0.3137186000, 0.5826951000", \ - "0.1318963000, 0.1471966000, 0.1796122000, 0.2344512000, 0.3266806000, 0.4834866000, 0.7573939000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0296844000, 0.0384644000, 0.0601278000, 0.1145921000, 0.2501884000, 0.5957205000, 1.4743637000", \ - "0.0293006000, 0.0381019000, 0.0597855000, 0.1141359000, 0.2511573000, 0.5952609000, 1.4737657000", \ - "0.0308027000, 0.0382279000, 0.0592510000, 0.1142317000, 0.2504825000, 0.5953840000, 1.4749590000", \ - "0.0443490000, 0.0521990000, 0.0674278000, 0.1144804000, 0.2505944000, 0.5961088000, 1.4744127000", \ - "0.0637600000, 0.0743784000, 0.0975179000, 0.1429543000, 0.2564732000, 0.5960038000, 1.4748546000", \ - "0.0987328000, 0.1140662000, 0.1469550000, 0.2079914000, 0.3210110000, 0.6093605000, 1.4770597000", \ - "0.1578072000, 0.1789683000, 0.2275902000, 0.3167981000, 0.4764659000, 0.7560439000, 1.5011471000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0197927000, 0.0221958000, 0.0282094000, 0.0433424000, 0.0814868000, 0.1774529000, 0.4217237000", \ - "0.0242845000, 0.0267576000, 0.0327858000, 0.0479192000, 0.0860372000, 0.1821394000, 0.4274885000", \ - "0.0313258000, 0.0343295000, 0.0412620000, 0.0568844000, 0.0950769000, 0.1911539000, 0.4353523000", \ - "0.0402988000, 0.0446275000, 0.0543458000, 0.0739006000, 0.1146235000, 0.2108312000, 0.4550539000", \ - "0.0465205000, 0.0541120000, 0.0695847000, 0.0988867000, 0.1522627000, 0.2555694000, 0.5022063000", \ - "0.0354250000, 0.0488555000, 0.0742841000, 0.1230810000, 0.2057853000, 0.3422682000, 0.6032738000", \ - "-0.038352900, -0.015109100, 0.0320137000, 0.1169310000, 0.2539864000, 0.4660895000, 0.8102914000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0882589000, 0.0945938000, 0.1103112000, 0.1493278000, 0.2476391000, 0.4980681000, 1.1403243000", \ - "0.0927674000, 0.0992006000, 0.1149782000, 0.1538737000, 0.2526112000, 0.5044619000, 1.1396721000", \ - "0.1039033000, 0.1103438000, 0.1261256000, 0.1652228000, 0.2635802000, 0.5135974000, 1.1546224000", \ - "0.1273076000, 0.1337305000, 0.1494787000, 0.1885290000, 0.2877759000, 0.5371469000, 1.1740035000", \ - "0.1607936000, 0.1674194000, 0.1834920000, 0.2228396000, 0.3215619000, 0.5715073000, 1.2090495000", \ - "0.2027016000, 0.2099370000, 0.2269864000, 0.2670044000, 0.3657057000, 0.6161022000, 1.2546461000", \ - "0.2447074000, 0.2532519000, 0.2726574000, 0.3154584000, 0.4152405000, 0.6668943000, 1.3021936000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0112045000, 0.0143508000, 0.0224488000, 0.0429116000, 0.0943553000, 0.2256106000, 0.5592832000", \ - "0.0116448000, 0.0145963000, 0.0225620000, 0.0429369000, 0.0943048000, 0.2253663000, 0.5593229000", \ - "0.0148876000, 0.0177002000, 0.0247165000, 0.0439809000, 0.0943717000, 0.2256441000, 0.5603498000", \ - "0.0227171000, 0.0258222000, 0.0334643000, 0.0515419000, 0.0972762000, 0.2256584000, 0.5604843000", \ - "0.0389993000, 0.0432288000, 0.0529886000, 0.0732470000, 0.1174255000, 0.2319620000, 0.5620342000", \ - "0.0716224000, 0.0777268000, 0.0910853000, 0.1180068000, 0.1698738000, 0.2794426000, 0.5737427000", \ - "0.1391306000, 0.1476065000, 0.1665553000, 0.2047681000, 0.2734971000, 0.4011959000, 0.6842755000"); - } - related_pin : "TE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0328998000, 0.0409505000, 0.0616221000, 0.1149116000, 0.2510851000, 0.5969013000, 1.4819693000", \ - "0.0328459000, 0.0408926000, 0.0617012000, 0.1148022000, 0.2506614000, 0.5988953000, 1.4718170000", \ - "0.0328470000, 0.0409138000, 0.0615061000, 0.1147375000, 0.2507840000, 0.5945498000, 1.4758333000", \ - "0.0331938000, 0.0412226000, 0.0617937000, 0.1148063000, 0.2508879000, 0.5954580000, 1.4765944000", \ - "0.0344105000, 0.0423308000, 0.0628060000, 0.1152901000, 0.2510114000, 0.5971263000, 1.4749624000", \ - "0.0376942000, 0.0453021000, 0.0651326000, 0.1166059000, 0.2513368000, 0.5953005000, 1.4738429000", \ - "0.0456294000, 0.0533345000, 0.0723654000, 0.1214890000, 0.2527930000, 0.5963772000, 1.4715660000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0982992000, 0.0982992000, 0.0982992000, 0.0983790000, 0.0983790000, 0.0983790000, 0.0983790000", \ - "0.1029321000, 0.1029321000, 0.1030107000, 0.1030136000, 0.1031264000, 0.1033322000, 0.1033322000", \ - "0.1182623000, 0.1182623000, 0.1182623000, 0.1182623000, 0.1182623000, 0.1182623000, 0.1182866000", \ - "0.1495663000, 0.1495663000, 0.1495663000, 0.1495663000, 0.1495663000, 0.1495663000, 0.1495663000", \ - "0.1996260000, 0.1996260000, 0.1996260000, 0.1996435000, 0.1996435000, 0.1996435000, 0.1996448000", \ - "0.2721437000, 0.2721437000, 0.2721437000, 0.2721689000, 0.2732844000, 0.2732844000, 0.2732844000", \ - "0.3809741000, 0.3809741000, 0.3809741000, 0.3809741000, 0.3809741000, 0.3809741000, 0.3809741000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0029373000, 0.0037092500, 0.0056730000, 0.0106686000, 0.0233768000, 0.0557052000, 0.1379450000"); - values("0.0152497000, 0.0152922000, 0.0153507000, 0.0153507000, 0.0153507000, 0.0153507000, 0.0153507000", \ - "0.0165651000, 0.0165651000, 0.0165913000, 0.0167957000, 0.0167957000, 0.0168643000, 0.0168643000", \ - "0.0144539000, 0.0144539000, 0.0144539000, 0.0146150000, 0.0146150000, 0.0146150000, 0.0146150000", \ - "0.0174756000, 0.0174756000, 0.0174756000, 0.0176771000, 0.0176841000, 0.0176841000, 0.0176841000", \ - "0.0224116000, 0.0224116000, 0.0224116000, 0.0224116000, 0.0224116000, 0.0224116000, 0.0224116000", \ - "0.0315604000, 0.0316151000, 0.0316851000, 0.0327374000, 0.0327374000, 0.0327374000, 0.0327374000", \ - "0.0555015000, 0.0555795000, 0.0556196000, 0.0556861000, 0.0557570000, 0.0558320000, 0.0558670000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvp_4") { - leakage_power () { - value : 0.0119876000; - when : "!A&TE"; - } - leakage_power () { - value : 0.0004927000; - when : "!A&!TE"; - } - leakage_power () { - value : 0.0146980000; - when : "A&TE"; - } - leakage_power () { - value : 0.0004683000; - when : "A&!TE"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__einvp"; - cell_leakage_power : 0.0069116490; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0084480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092782000, 0.0092580000, 0.0092114000, 0.0092249000, 0.0092558000, 0.0093272000, 0.0094917000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007783600, -0.007775900, -0.007758300, -0.007761400, -0.007768400, -0.007784700, -0.007822100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088880000; - } - pin ("TE") { - capacitance : 0.0060230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0061510000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0058960000; - } - pin ("Z") { - capacitance : 0.0048940000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0001199000, -0.000998500, -0.004410400, -0.014970600, -0.046020900, -0.133824900, -0.379303700", \ - "-0.000647600, -0.001708600, -0.005046500, -0.015265100, -0.045973200, -0.133569600, -0.378966400", \ - "-0.001424000, -0.002594300, -0.006004400, -0.016078000, -0.046343300, -0.133587900, -0.378789800", \ - "-0.001990800, -0.003282200, -0.006844600, -0.017245900, -0.047182700, -0.133941300, -0.378868000", \ - "-0.001720200, -0.003131800, -0.006969900, -0.018014200, -0.048255100, -0.134710000, -0.379193400", \ - "0.0006979000, -0.000835400, -0.005029200, -0.016692500, -0.047661300, -0.135358500, -0.379647700", \ - "0.0084532000, 0.0064386000, 0.0022166000, -0.012246000, -0.045273700, -0.133965600, -0.379748000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0164450000, 0.0183790000, 0.0234145000, 0.0358791000, 0.0681304000, 0.1552019000, 0.3986810000", \ - "0.0156382000, 0.0173824000, 0.0222198000, 0.0346858000, 0.0675201000, 0.1549365000, 0.3976885000", \ - "0.0152522000, 0.0168848000, 0.0213530000, 0.0333163000, 0.0660556000, 0.1547640000, 0.3975560000", \ - "0.0151443000, 0.0166405000, 0.0208102000, 0.0325982000, 0.0649564000, 0.1542511000, 0.3970874000", \ - "0.0158682000, 0.0172942000, 0.0212784000, 0.0329257000, 0.0645063000, 0.1524139000, 0.3990194000", \ - "0.0181018000, 0.0193788000, 0.0231374000, 0.0340017000, 0.0649828000, 0.1511471000, 0.3948186000", \ - "0.0258291000, 0.0284281000, 0.0287633000, 0.0389241000, 0.0685463000, 0.1541871000, 0.3937581000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0118598000, 0.0120076000, 0.0123455000, 0.0129822000, 0.0137604000, 0.0142743000, 0.0145621000", \ - "0.0115842000, 0.0117287000, 0.0120731000, 0.0127211000, 0.0135068000, 0.0140777000, 0.0143211000", \ - "0.0112436000, 0.0113822000, 0.0117325000, 0.0123846000, 0.0131560000, 0.0137326000, 0.0140230000", \ - "0.0108837000, 0.0110263000, 0.0113881000, 0.0120388000, 0.0128552000, 0.0134989000, 0.0138177000", \ - "0.0107872000, 0.0109166000, 0.0112328000, 0.0118948000, 0.0127451000, 0.0134607000, 0.0138426000", \ - "0.0113288000, 0.0114359000, 0.0117046000, 0.0122611000, 0.0131245000, 0.0139349000, 0.0144135000", \ - "0.0136354000, 0.0137355000, 0.0139807000, 0.0145479000, 0.0154289000, 0.0162508000, 0.0168179000"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0312987000, 0.0327278000, 0.0367641000, 0.0479551000, 0.0792246000, 0.1669785000, 0.4083602000", \ - "0.0310698000, 0.0325149000, 0.0365532000, 0.0477085000, 0.0789555000, 0.1656138000, 0.4110197000", \ - "0.0307560000, 0.0322079000, 0.0362197000, 0.0474446000, 0.0786518000, 0.1662903000, 0.4106263000", \ - "0.0304486000, 0.0319038000, 0.0358824000, 0.0470721000, 0.0783370000, 0.1661544000, 0.4084441000", \ - "0.0304672000, 0.0319341000, 0.0359526000, 0.0470484000, 0.0782904000, 0.1656667000, 0.4074906000", \ - "0.0314696000, 0.0328922000, 0.0369615000, 0.0479131000, 0.0792224000, 0.1659018000, 0.4083545000", \ - "0.0342422000, 0.0358083000, 0.0396186000, 0.0510368000, 0.0823845000, 0.1696934000, 0.4114242000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0165995000, 0.0154673000, 0.0122211000, 0.0017421000, -0.029711200, -0.117668300, -0.363203000", \ - "0.0163493000, 0.0152346000, 0.0119781000, 0.0014956000, -0.029953300, -0.117907200, -0.363456200", \ - "0.0159429000, 0.0148421000, 0.0115660000, 0.0011706000, -0.030278600, -0.118235500, -0.363770700", \ - "0.0161576000, 0.0148501000, 0.0112775000, 0.0008538000, -0.030575900, -0.118527700, -0.364075100", \ - "0.0177750000, 0.0163313000, 0.0122907000, 0.0009495000, -0.030555900, -0.118524800, -0.364030500", \ - "0.0187030000, 0.0172484000, 0.0132019000, 0.0018881000, -0.029677500, -0.117736400, -0.363278800", \ - "0.0214855000, 0.0199860000, 0.0159104000, 0.0046220000, -0.026972400, -0.114921900, -0.360567300"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013953820, 0.0038941840, 0.0108677500, 0.0303293300, 0.0846420200, 0.2362160000"); - values("0.0103717000, 0.0103573000, 0.0103187000, 0.0102527000, 0.0101764000, 0.0101224000, 0.0100967000", \ - "0.0100928000, 0.0100809000, 0.0100527000, 0.0100051000, 0.0099422000, 0.0098997000, 0.0098782000", \ - "0.0097571000, 0.0097491000, 0.0097294000, 0.0096981000, 0.0096516000, 0.0096047000, 0.0095804000", \ - "0.0094678000, 0.0094627000, 0.0094498000, 0.0094297000, 0.0094013000, 0.0093747000, 0.0093569000", \ - "0.0094989000, 0.0095199000, 0.0095095000, 0.0094631000, 0.0094443000, 0.0094831000, 0.0094455000", \ - "0.0102095000, 0.0102018000, 0.0102025000, 0.0102037000, 0.0101924000, 0.0101701000, 0.0101962000", \ - "0.0127020000, 0.0126967000, 0.0126858000, 0.0126638000, 0.0126376000, 0.0126083000, 0.0126083000"); - } - when : "A"; - } - max_capacitance : 0.2362160000; - max_transition : 1.5003820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE')"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0181309000, 0.0199564000, 0.0246042000, 0.0364937000, 0.0679596000, 0.1545967000, 0.3954289000", \ - "0.0220647000, 0.0237791000, 0.0284909000, 0.0406481000, 0.0724538000, 0.1591525000, 0.4003394000", \ - "0.0285667000, 0.0311644000, 0.0374599000, 0.0504730000, 0.0826284000, 0.1695562000, 0.4119925000", \ - "0.0343580000, 0.0383781000, 0.0479475000, 0.0685850000, 0.1064652000, 0.1942608000, 0.4354141000", \ - "0.0349466000, 0.0411734000, 0.0559603000, 0.0876508000, 0.1469156000, 0.2496923000, 0.4917115000", \ - "0.0189218000, 0.0284695000, 0.0512523000, 0.1000384000, 0.1913216000, 0.3498485000, 0.6212166000", \ - "-0.043312600, -0.028276600, 0.0065571000, 0.0793866000, 0.2210158000, 0.4659861000, 0.8738063000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0349786000, 0.0403151000, 0.0540064000, 0.0884363000, 0.1779523000, 0.4204551000, 1.1075706000", \ - "0.0382315000, 0.0428154000, 0.0560224000, 0.0904578000, 0.1814699000, 0.4252610000, 1.1017115000", \ - "0.0500432000, 0.0542708000, 0.0662178000, 0.0991588000, 0.1903220000, 0.4379013000, 1.1121308000", \ - "0.0732169000, 0.0793975000, 0.0940719000, 0.1263650000, 0.2152691000, 0.4656067000, 1.1393243000", \ - "0.1091721000, 0.1186056000, 0.1411942000, 0.1890008000, 0.2808303000, 0.5277005000, 1.2073259000", \ - "0.1699393000, 0.1835068000, 0.2165688000, 0.2874407000, 0.4245717000, 0.6775598000, 1.3537983000", \ - "0.2856660000, 0.3039635000, 0.3496787000, 0.4515162000, 0.6553251000, 1.0228449000, 1.7093884000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0105827000, 0.0125672000, 0.0181473000, 0.0335396000, 0.0765558000, 0.1958868000, 0.5275461000", \ - "0.0107604000, 0.0125875000, 0.0181190000, 0.0336249000, 0.0765131000, 0.1954980000, 0.5269130000", \ - "0.0154605000, 0.0176401000, 0.0223255000, 0.0349700000, 0.0763496000, 0.1961758000, 0.5286146000", \ - "0.0239823000, 0.0267904000, 0.0335017000, 0.0489199000, 0.0826026000, 0.1955618000, 0.5289671000", \ - "0.0408161000, 0.0450667000, 0.0551874000, 0.0757526000, 0.1169662000, 0.2107892000, 0.5280163000", \ - "0.0715021000, 0.0780689000, 0.0935773000, 0.1264053000, 0.1837559000, 0.2924230000, 0.5564565000", \ - "0.1294285000, 0.1393816000, 0.1620632000, 0.2121441000, 0.2990172000, 0.4550853000, 0.7411154000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0312783000, 0.0370482000, 0.0528618000, 0.0962985000, 0.2163256000, 0.5491377000, 1.4809957000", \ - "0.0308307000, 0.0366794000, 0.0525531000, 0.0961717000, 0.2167009000, 0.5481235000, 1.4755455000", \ - "0.0317519000, 0.0367541000, 0.0519084000, 0.0958749000, 0.2161165000, 0.5488303000, 1.4775230000", \ - "0.0465586000, 0.0509094000, 0.0614631000, 0.0981744000, 0.2160895000, 0.5519336000, 1.4750209000", \ - "0.0637069000, 0.0709053000, 0.0894162000, 0.1280412000, 0.2235102000, 0.5503764000, 1.4836075000", \ - "0.0976076000, 0.1082321000, 0.1335787000, 0.1873901000, 0.2943630000, 0.5638324000, 1.4808015000", \ - "0.1566212000, 0.1717757000, 0.2062415000, 0.2866256000, 0.4429180000, 0.7214939000, 1.5003824000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0208127000, 0.0223276000, 0.0265102000, 0.0378933000, 0.0693814000, 0.1558810000, 0.3988749000", \ - "0.0250921000, 0.0266889000, 0.0309103000, 0.0422983000, 0.0737856000, 0.1603395000, 0.4016119000", \ - "0.0316525000, 0.0335736000, 0.0385110000, 0.0507391000, 0.0823645000, 0.1688733000, 0.4117968000", \ - "0.0391816000, 0.0421631000, 0.0490205000, 0.0648873000, 0.1002385000, 0.1872576000, 0.4287264000", \ - "0.0424827000, 0.0472568000, 0.0588408000, 0.0831019000, 0.1312897000, 0.2284548000, 0.4709150000", \ - "0.0252577000, 0.0329380000, 0.0528973000, 0.0935733000, 0.1698988000, 0.3024553000, 0.5656495000", \ - "-0.064556100, -0.049241800, -0.014094300, 0.0581255000, 0.1871518000, 0.3973473000, 0.7483222000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0912272000, 0.0955188000, 0.1072967000, 0.1388266000, 0.2257037000, 0.4691288000, 1.1424880000", \ - "0.0956156000, 0.0999578000, 0.1116483000, 0.1432305000, 0.2304899000, 0.4740850000, 1.1520630000", \ - "0.1064807000, 0.1108764000, 0.1225186000, 0.1542683000, 0.2411711000, 0.4836720000, 1.1620370000", \ - "0.1292464000, 0.1335315000, 0.1453705000, 0.1769869000, 0.2642997000, 0.5073523000, 1.1887012000", \ - "0.1607305000, 0.1652623000, 0.1774117000, 0.2094619000, 0.2965315000, 0.5407427000, 1.2128223000", \ - "0.1981747000, 0.2030968000, 0.2160483000, 0.2488403000, 0.3364275000, 0.5781320000, 1.2529063000", \ - "0.2298543000, 0.2353097000, 0.2500890000, 0.2859253000, 0.3751164000, 0.6174830000, 1.2922745000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0115175000, 0.0134574000, 0.0189613000, 0.0344735000, 0.0769876000, 0.1951332000, 0.5292052000", \ - "0.0119747000, 0.0138026000, 0.0191327000, 0.0345751000, 0.0769678000, 0.1956010000, 0.5279047000", \ - "0.0150564000, 0.0168442000, 0.0217840000, 0.0359812000, 0.0770860000, 0.1952288000, 0.5290189000", \ - "0.0226910000, 0.0245837000, 0.0299329000, 0.0441058000, 0.0815889000, 0.1957356000, 0.5277264000", \ - "0.0390664000, 0.0416844000, 0.0484925000, 0.0648197000, 0.1025490000, 0.2048155000, 0.5297873000", \ - "0.0717040000, 0.0753736000, 0.0850477000, 0.1071265000, 0.1522837000, 0.2536980000, 0.5438370000", \ - "0.1405902000, 0.1449958000, 0.1588235000, 0.1894892000, 0.2512147000, 0.3711166000, 0.6546798000"); - } - related_pin : "TE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0348965000, 0.0402783000, 0.0553517000, 0.0975241000, 0.2164333000, 0.5518924000, 1.4750385000", \ - "0.0348241000, 0.0401565000, 0.0551551000, 0.0973575000, 0.2166039000, 0.5485408000, 1.4826859000", \ - "0.0348750000, 0.0401733000, 0.0551695000, 0.0975321000, 0.2161039000, 0.5514275000, 1.4823278000", \ - "0.0353111000, 0.0405013000, 0.0553642000, 0.0973340000, 0.2164335000, 0.5518032000, 1.4798782000", \ - "0.0364743000, 0.0416765000, 0.0564233000, 0.0984884000, 0.2164308000, 0.5508873000, 1.4777132000", \ - "0.0395954000, 0.0449965000, 0.0594408000, 0.1001081000, 0.2171756000, 0.5476029000, 1.4783352000", \ - "0.0473692000, 0.0524394000, 0.0667597000, 0.1060618000, 0.2194403000, 0.5509526000, 1.4732542000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.1077083000, 0.1082835000, 0.1082835000, 0.1082835000, 0.1082835000, 0.1082835000, 0.1082835000", \ - "0.1132482000, 0.1132689000, 0.1132689000, 0.1133536000, 0.1133536000, 0.1133536000, 0.1133536000", \ - "0.1249952000, 0.1255198000, 0.1267496000, 0.1273237000, 0.1273237000, 0.1273586000, 0.1273586000", \ - "0.1548304000, 0.1553198000, 0.1578345000, 0.1578345000, 0.1584154000, 0.1584154000, 0.1584154000", \ - "0.2076208000, 0.2078751000, 0.2112384000, 0.2112384000, 0.2112713000, 0.2112713000, 0.2112801000", \ - "0.2850996000, 0.2857049000, 0.2888941000, 0.2888941000, 0.2888941000, 0.2888941000, 0.2888941000", \ - "0.4061784000, 0.4070753000, 0.4115585000, 0.4115585000, 0.4115671000, 0.4115671000, 0.4115671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0053944000, 0.0062897800, 0.0087885800, 0.0157621000, 0.0352237000, 0.0895364000, 0.2411100000"); - values("0.0167183000, 0.0167261000, 0.0167261000, 0.0167261000, 0.0167261000, 0.0167261000, 0.0167261000", \ - "0.0187444000, 0.0187444000, 0.0187495000, 0.0188006000, 0.0188006000, 0.0188006000, 0.0188006000", \ - "0.0168440000, 0.0168597000, 0.0171805000, 0.0171805000, 0.0171805000, 0.0171805000, 0.0171805000", \ - "0.0208172000, 0.0208799000, 0.0208799000, 0.0208799000, 0.0208799000, 0.0208799000, 0.0208799000", \ - "0.0285281000, 0.0293879000, 0.0293879000, 0.0293879000, 0.0293879000, 0.0293879000, 0.0293879000", \ - "0.0441149000, 0.0445264000, 0.0447191000, 0.0447191000, 0.0447920000, 0.0447920000, 0.0447920000", \ - "0.0837502000, 0.0837502000, 0.0837502000, 0.0853543000, 0.0853543000, 0.0853543000, 0.0853612000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__einvp_8") { - leakage_power () { - value : 0.0142955000; - when : "!A&TE"; - } - leakage_power () { - value : 0.0007094000; - when : "!A&!TE"; - } - leakage_power () { - value : 0.0158942000; - when : "A&TE"; - } - leakage_power () { - value : 0.0005421000; - when : "A&!TE"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__einvp"; - cell_leakage_power : 0.0078603070; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0165350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0156860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0174220000, 0.0174025000, 0.0173576000, 0.0173758000, 0.0174177000, 0.0175144000, 0.0177373000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015257400, -0.015249500, -0.015231200, -0.015230700, -0.015229700, -0.015227200, -0.015221700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0173850000; - } - pin ("TE") { - capacitance : 0.0090710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0094200000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087230000; - } - pin ("Z") { - capacitance : 0.0094840000; - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0011019000, -0.000141500, -0.004187200, -0.018083700, -0.064091300, -0.207617100, -0.647185100", \ - "-0.000238100, -0.001549600, -0.005547100, -0.018918700, -0.064063700, -0.207109900, -0.646467000", \ - "-0.001860600, -0.003182700, -0.007319100, -0.020650500, -0.064973400, -0.207182400, -0.646162900", \ - "-0.003091700, -0.004522000, -0.008996200, -0.022905000, -0.066923400, -0.208066500, -0.646274600", \ - "-0.002985600, -0.004546400, -0.009295600, -0.024502400, -0.069071200, -0.209658800, -0.646838100", \ - "0.0013696000, -0.000478300, -0.005823300, -0.021588500, -0.068520800, -0.211287400, -0.648061600", \ - "0.0141448000, 0.0121063000, 0.0065178000, -0.012784700, -0.062975400, -0.209006700, -0.647968800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0326692000, 0.0350278000, 0.0417833000, 0.0599573000, 0.1085972000, 0.2528199000, 0.6860684000", \ - "0.0308462000, 0.0330479000, 0.0395098000, 0.0576914000, 0.1075239000, 0.2512502000, 0.6886439000", \ - "0.0301216000, 0.0320524000, 0.0380580000, 0.0553037000, 0.1053346000, 0.2503772000, 0.6865805000", \ - "0.0301769000, 0.0319695000, 0.0373335000, 0.0531789000, 0.1023173000, 0.2488205000, 0.6879927000", \ - "0.0318138000, 0.0334279000, 0.0382524000, 0.0532976000, 0.1014922000, 0.2462911000, 0.6839992000", \ - "0.0351158000, 0.0365717000, 0.0412231000, 0.0559937000, 0.1021258000, 0.2431437000, 0.6841589000", \ - "0.0492091000, 0.0511483000, 0.0559435000, 0.0653178000, 0.1088602000, 0.2477229000, 0.6773261000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0147225000, 0.0148746000, 0.0152959000, 0.0162915000, 0.0178985000, 0.0193295000, 0.0201026000", \ - "0.0145642000, 0.0147279000, 0.0151734000, 0.0161865000, 0.0177834000, 0.0192035000, 0.0199589000", \ - "0.0141957000, 0.0143545000, 0.0147933000, 0.0158114000, 0.0174574000, 0.0189128000, 0.0196875000", \ - "0.0138416000, 0.0139958000, 0.0144229000, 0.0154282000, 0.0170395000, 0.0185853000, 0.0194013000", \ - "0.0134893000, 0.0136335000, 0.0140355000, 0.0149921000, 0.0165996000, 0.0182303000, 0.0191440000", \ - "0.0137288000, 0.0138556000, 0.0141928000, 0.0150502000, 0.0164637000, 0.0184342000, 0.0196290000", \ - "0.0156215000, 0.0157351000, 0.0160511000, 0.0170306000, 0.0178707000, 0.0200694000, 0.0214567000"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0614055000, 0.0630714000, 0.0682412000, 0.0835578000, 0.1301988000, 0.2722882000, 0.7096983000", \ - "0.0612194000, 0.0628748000, 0.0679105000, 0.0833719000, 0.1299890000, 0.2721272000, 0.7062874000", \ - "0.0609321000, 0.0625977000, 0.0676242000, 0.0829971000, 0.1297058000, 0.2718361000, 0.7061431000", \ - "0.0606137000, 0.0622641000, 0.0672811000, 0.0826859000, 0.1294634000, 0.2725589000, 0.7062085000", \ - "0.0604051000, 0.0620782000, 0.0671593000, 0.0824097000, 0.1291938000, 0.2723646000, 0.7069436000", \ - "0.0612465000, 0.0628765000, 0.0678651000, 0.0830177000, 0.1298078000, 0.2719847000, 0.7059962000", \ - "0.0638222000, 0.0656473000, 0.0707328000, 0.0861212000, 0.1329596000, 0.2755346000, 0.7085904000"); - } - when : "!A"; - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0314963000, 0.0302809000, 0.0267189000, 0.0144470000, -0.030985800, -0.175027100, -0.614752400", \ - "0.0312800000, 0.0301083000, 0.0265049000, 0.0142529000, -0.031175300, -0.175209800, -0.614921000", \ - "0.0309303000, 0.0296974000, 0.0260460000, 0.0138669000, -0.031461900, -0.175495400, -0.615221800", \ - "0.0308703000, 0.0294720000, 0.0254142000, 0.0131020000, -0.031785000, -0.175847100, -0.615548800", \ - "0.0343366000, 0.0327465000, 0.0279280000, 0.0135541000, -0.031974800, -0.175996000, -0.615701900", \ - "0.0382330000, 0.0365448000, 0.0314748000, 0.0160083000, -0.031225700, -0.175394100, -0.615150300", \ - "0.0406129000, 0.0389648000, 0.0337882000, 0.0183706000, -0.028876900, -0.173023700, -0.612841700"); - } - related_pin : "TE"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015257910, 0.0046560770, 0.0142084000, 0.0433581100, 0.1323108000, 0.4037574000"); - values("0.0122732000, 0.0122528000, 0.0121985000, 0.0120822000, 0.0119538000, 0.0118384000, 0.0117906000", \ - "0.0120220000, 0.0120080000, 0.0119693000, 0.0118812000, 0.0117497000, 0.0116347000, 0.0115782000", \ - "0.0116267000, 0.0116128000, 0.0115861000, 0.0115310000, 0.0114372000, 0.0113482000, 0.0112976000", \ - "0.0112831000, 0.0112692000, 0.0112583000, 0.0112198000, 0.0111616000, 0.0110945000, 0.0110425000", \ - "0.0110737000, 0.0110665000, 0.0110484000, 0.0110084000, 0.0109566000, 0.0109121000, 0.0108770000", \ - "0.0118315000, 0.0118313000, 0.0118088000, 0.0117895000, 0.0117412000, 0.0117326000, 0.0117049000", \ - "0.0137194000, 0.0137118000, 0.0136981000, 0.0136575000, 0.0135972000, 0.0136095000, 0.0136085000"); - } - when : "A"; - } - max_capacitance : 0.4037570000; - max_transition : 1.4986050000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - three_state : "(TE')"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0206524000, 0.0219447000, 0.0257010000, 0.0361511000, 0.0654145000, 0.1524940000, 0.4191682000", \ - "0.0244115000, 0.0256491000, 0.0294368000, 0.0399301000, 0.0696502000, 0.1568218000, 0.4211402000", \ - "0.0313836000, 0.0331229000, 0.0379301000, 0.0493939000, 0.0793780000, 0.1672848000, 0.4337297000", \ - "0.0372856000, 0.0399916000, 0.0473586000, 0.0655621000, 0.1025673000, 0.1909878000, 0.4555173000", \ - "0.0369883000, 0.0411720000, 0.0527403000, 0.0805520000, 0.1385060000, 0.2454447000, 0.5101279000", \ - "0.0180315000, 0.0244582000, 0.0419172000, 0.0840795000, 0.1724346000, 0.3375855000, 0.6377791000", \ - "-0.051779500, -0.041998800, -0.015286400, 0.0470934000, 0.1830618000, 0.4368482000, 0.8857284000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0390562000, 0.0426576000, 0.0532685000, 0.0821938000, 0.1609955000, 0.3958602000, 1.1011614000", \ - "0.0415602000, 0.0448701000, 0.0549389000, 0.0838111000, 0.1645034000, 0.3985575000, 1.1095015000", \ - "0.0532955000, 0.0561636000, 0.0651985000, 0.0925057000, 0.1732709000, 0.4105247000, 1.1221357000", \ - "0.0781093000, 0.0822239000, 0.0932447000, 0.1192247000, 0.1973255000, 0.4349736000, 1.1456127000", \ - "0.1161403000, 0.1222030000, 0.1389567000, 0.1787858000, 0.2637367000, 0.4992126000, 1.2100180000", \ - "0.1816087000, 0.1901961000, 0.2146563000, 0.2747557000, 0.4021736000, 0.6514994000, 1.3634708000", \ - "0.3080360000, 0.3199750000, 0.3531775000, 0.4378245000, 0.6254391000, 0.9900069000, 1.7183927000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0129006000, 0.0143063000, 0.0187338000, 0.0322509000, 0.0731263000, 0.1974024000, 0.5754721000", \ - "0.0128013000, 0.0142772000, 0.0186769000, 0.0322708000, 0.0731763000, 0.1969186000, 0.5754683000", \ - "0.0178089000, 0.0194426000, 0.0226302000, 0.0336485000, 0.0729113000, 0.1972694000, 0.5757210000", \ - "0.0251648000, 0.0272525000, 0.0326182000, 0.0468366000, 0.0800599000, 0.1970022000, 0.5748586000", \ - "0.0426214000, 0.0450157000, 0.0530113000, 0.0714171000, 0.1138119000, 0.2139260000, 0.5748382000", \ - "0.0731774000, 0.0781657000, 0.0893095000, 0.1179989000, 0.1761644000, 0.2940473000, 0.6006183000", \ - "0.1309391000, 0.1376322000, 0.1560189000, 0.2009972000, 0.2861215000, 0.4528396000, 0.7795889000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0343849000, 0.0381417000, 0.0495450000, 0.0844460000, 0.1896110000, 0.5092114000, 1.4712250000", \ - "0.0340945000, 0.0378834000, 0.0492430000, 0.0843343000, 0.1894698000, 0.5058068000, 1.4751267000", \ - "0.0343188000, 0.0376443000, 0.0487975000, 0.0839911000, 0.1895091000, 0.5066157000, 1.4773817000", \ - "0.0493250000, 0.0514349000, 0.0588866000, 0.0867610000, 0.1887212000, 0.5073947000, 1.4761393000", \ - "0.0659511000, 0.0707272000, 0.0842415000, 0.1188080000, 0.1998375000, 0.5089980000, 1.4774421000", \ - "0.0996858000, 0.1068552000, 0.1262389000, 0.1723537000, 0.2710729000, 0.5267269000, 1.4806009000", \ - "0.1595332000, 0.1686229000, 0.1938255000, 0.2596469000, 0.4024385000, 0.6801782000, 1.4986048000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0258970000, 0.0270213000, 0.0304308000, 0.0402467000, 0.0691255000, 0.1563273000, 0.4210529000", \ - "0.0298526000, 0.0310031000, 0.0343958000, 0.0442455000, 0.0731967000, 0.1603387000, 0.4247155000", \ - "0.0365727000, 0.0378403000, 0.0416426000, 0.0521455000, 0.0813880000, 0.1685434000, 0.4330470000", \ - "0.0440739000, 0.0459004000, 0.0509798000, 0.0641749000, 0.0969105000, 0.1850408000, 0.4493979000", \ - "0.0462771000, 0.0495082000, 0.0574028000, 0.0778155000, 0.1218414000, 0.2203240000, 0.4857365000", \ - "0.0248564000, 0.0303372000, 0.0450557000, 0.0781800000, 0.1487260000, 0.2816855000, 0.5684924000", \ - "-0.070858000, -0.061341800, -0.035868000, 0.0241186000, 0.1441871000, 0.3543905000, 0.7259378000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.1207545000, 0.1238139000, 0.1329899000, 0.1593760000, 0.2363824000, 0.4688174000, 1.1754546000", \ - "0.1251352000, 0.1281967000, 0.1374648000, 0.1638519000, 0.2407309000, 0.4727918000, 1.1794180000", \ - "0.1359737000, 0.1390582000, 0.1481486000, 0.1746848000, 0.2514858000, 0.4836841000, 1.1912885000", \ - "0.1611772000, 0.1642147000, 0.1735023000, 0.2000844000, 0.2770455000, 0.5091882000, 1.2149297000", \ - "0.2038661000, 0.2071174000, 0.2164263000, 0.2433402000, 0.3209871000, 0.5531162000, 1.2667726000", \ - "0.2590635000, 0.2624843000, 0.2725322000, 0.3008450000, 0.3796067000, 0.6116886000, 1.3216449000", \ - "0.3164275000, 0.3204529000, 0.3319750000, 0.3634083000, 0.4460430000, 0.6794534000, 1.3855729000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0145949000, 0.0159776000, 0.0202407000, 0.0335451000, 0.0743073000, 0.1973284000, 0.5747147000", \ - "0.0148553000, 0.0162238000, 0.0204305000, 0.0336113000, 0.0743405000, 0.1971724000, 0.5742503000", \ - "0.0174632000, 0.0187445000, 0.0226002000, 0.0349859000, 0.0746738000, 0.1972445000, 0.5745397000", \ - "0.0243470000, 0.0256925000, 0.0297431000, 0.0420622000, 0.0791286000, 0.1978147000, 0.5749102000", \ - "0.0408216000, 0.0425088000, 0.0474963000, 0.0612217000, 0.0982795000, 0.2074022000, 0.5739795000", \ - "0.0748381000, 0.0765877000, 0.0836229000, 0.1018815000, 0.1447911000, 0.2527984000, 0.5896179000", \ - "0.1433703000, 0.1469086000, 0.1568563000, 0.1819666000, 0.2391488000, 0.3628506000, 0.6847435000"); - } - related_pin : "TE"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0410537000, 0.0446813000, 0.0553769000, 0.0888089000, 0.1910330000, 0.5073336000, 1.4778152000", \ - "0.0410786000, 0.0446299000, 0.0556137000, 0.0888016000, 0.1911824000, 0.5075453000, 1.4729230000", \ - "0.0411236000, 0.0446037000, 0.0556435000, 0.0888060000, 0.1911799000, 0.5074479000, 1.4768730000", \ - "0.0411332000, 0.0447244000, 0.0557041000, 0.0889098000, 0.1912556000, 0.5088970000, 1.4767633000", \ - "0.0427183000, 0.0460844000, 0.0570515000, 0.0898757000, 0.1916120000, 0.5087408000, 1.4799847000", \ - "0.0463533000, 0.0498529000, 0.0605991000, 0.0931934000, 0.1935099000, 0.5069705000, 1.4742734000", \ - "0.0553913000, 0.0589449000, 0.0694277000, 0.1010763000, 0.1982656000, 0.5089411000, 1.4726091000"); - } - timing_sense : "positive_unate"; - timing_type : "three_state_enable"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.1494525000, 0.1494525000, 0.1501381000, 0.1501381000, 0.1501381000, 0.1503454000, 0.1503555000", \ - "0.1533327000, 0.1533327000, 0.1544686000, 0.1546557000, 0.1546557000, 0.1546557000, 0.1546557000", \ - "0.1672137000, 0.1672137000, 0.1672137000, 0.1672137000, 0.1672137000, 0.1672137000, 0.1672137000", \ - "0.1965103000, 0.1965103000, 0.1965103000, 0.1965103000, 0.1965103000, 0.1965103000, 0.1965103000", \ - "0.2624226000, 0.2624226000, 0.2624226000, 0.2624226000, 0.2627962000, 0.2627962000, 0.2628310000", \ - "0.3666536000, 0.3666536000, 0.3684283000, 0.3694490000, 0.3694490000, 0.3694490000, 0.3694490000", \ - "0.5297963000, 0.5297963000, 0.5297963000, 0.5297963000, 0.5297963000, 0.5297963000, 0.5297963000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0099843000, 0.0110101000, 0.0141404000, 0.0236927000, 0.0528424000, 0.1417950000, 0.4132420000"); - values("0.0226792000, 0.0226792000, 0.0226792000, 0.0226843000, 0.0226843000, 0.0226843000, 0.0226843000", \ - "0.0250616000, 0.0253139000, 0.0253139000, 0.0253139000, 0.0253139000, 0.0253139000, 0.0253139000", \ - "0.0241636000, 0.0247005000, 0.0247005000, 0.0247005000, 0.0247636000, 0.0247636000, 0.0247636000", \ - "0.0267054000, 0.0280029000, 0.0280029000, 0.0287756000, 0.0287756000, 0.0287756000, 0.0287756000", \ - "0.0377619000, 0.0399775000, 0.0410675000, 0.0410675000, 0.0410675000, 0.0410675000, 0.0410675000", \ - "0.0638483000, 0.0676209000, 0.0676209000, 0.0676209000, 0.0676209000, 0.0676209000, 0.0676209000", \ - "0.1160790000, 0.1233489000, 0.1233489000, 0.1233489000, 0.1236820000, 0.1244866000, 0.1244866000"); - } - fall_transition ("scalar") { - values("0.0000000000"); - } - related_pin : "TE"; - rise_transition ("scalar") { - values("0.0000000000"); - } - timing_sense : "negative_unate"; - timing_type : "three_state_disable"; - } - } - } - - cell ("sky130_fd_sc_hd__fa_1") { - leakage_power () { - value : 0.0071181000; - when : "!A&!B&CIN"; - } - leakage_power () { - value : 0.0123163000; - when : "!A&!B&!CIN"; - } - leakage_power () { - value : 0.0073626000; - when : "!A&B&CIN"; - } - leakage_power () { - value : 0.0073177000; - when : "!A&B&!CIN"; - } - leakage_power () { - value : 0.0073668000; - when : "A&!B&CIN"; - } - leakage_power () { - value : 0.0075050000; - when : "A&!B&!CIN"; - } - leakage_power () { - value : 0.0016122000; - when : "A&B&CIN"; - } - leakage_power () { - value : 0.0077956000; - when : "A&B&!CIN"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__fa"; - cell_leakage_power : 0.0072992950; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0067290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0065610000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0068960000; - } - pin ("B") { - capacitance : 0.0060260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0058720000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0061810000; - } - pin ("CIN") { - capacitance : 0.0045230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044630000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045830000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B) | (A&CIN) | (B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0027228000, 0.0063543000, 0.0127806000, 0.0185775000, 0.0100417000, -0.039920200, -0.191430300", \ - "0.0027117000, 0.0063219000, 0.0127014000, 0.0184549000, 0.0098859000, -0.040111400, -0.191591500", \ - "0.0026869000, 0.0062697000, 0.0125955000, 0.0182595000, 0.0096055000, -0.040400600, -0.191909900", \ - "0.0026675000, 0.0062195000, 0.0124894000, 0.0180642000, 0.0093365000, -0.040681300, -0.192229900", \ - "0.0026444000, 0.0061722000, 0.0123822000, 0.0178723000, 0.0090493000, -0.041035400, -0.192517400", \ - "0.0026495000, 0.0061586000, 0.0123802000, 0.0178569000, 0.0089925000, -0.041042300, -0.192562600", \ - "0.0026614000, 0.0062021000, 0.0124186000, 0.0178907000, 0.0089329000, -0.040939400, -0.192444100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("9.8517168e-05, 0.0004098000, 0.0018330000, 0.0077894000, 0.0284887000, 0.0859850000, 0.2392087000", \ - "9.3668476e-05, 0.0003908000, 0.0018061000, 0.0077671000, 0.0284332000, 0.0858426000, 0.2388069000", \ - "8.4222007e-05, 0.0003738000, 0.0017666000, 0.0076751000, 0.0283175000, 0.0858265000, 0.2390000000", \ - "6.7809369e-05, 0.0003323000, 0.0016896000, 0.0075226000, 0.0280710000, 0.0855652000, 0.2387095000", \ - "5.0318791e-05, 0.0002948000, 0.0015754000, 0.0073440000, 0.0277915000, 0.0853337000, 0.2396206000", \ - "3.5245873e-05, 0.0002525000, 0.0014767000, 0.0071157000, 0.0274568000, 0.0847943000, 0.2392720000", \ - "9.7540714e-05, 0.0003921000, 0.0017746000, 0.0075621000, 0.0275492000, 0.0848219000, 0.2375927000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0026508000, 0.0061858000, 0.0124143000, 0.0179568000, 0.0091610000, -0.040871000, -0.192338900", \ - "0.0026463000, 0.0061860000, 0.0124084000, 0.0179192000, 0.0091116000, -0.040882000, -0.192373600", \ - "0.0026360000, 0.0061468000, 0.0123312000, 0.0177757000, 0.0089207000, -0.041107400, -0.192574600", \ - "0.0026159000, 0.0060950000, 0.0122250000, 0.0176154000, 0.0086669000, -0.041391800, -0.192853100", \ - "0.0025957000, 0.0060504000, 0.0121081000, 0.0173983000, 0.0083799000, -0.041715700, -0.193186200", \ - "0.0025947000, 0.0060447000, 0.0121009000, 0.0173630000, 0.0083600000, -0.041710000, -0.193173200", \ - "0.0026317000, 0.0061277000, 0.0122321000, 0.0175266000, 0.0085210000, -0.041325600, -0.192819600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("9.4600715e-05, 0.0003994000, 0.0018500000, 0.0078203000, 0.0285122000, 0.0861937000, 0.2405485000", \ - "9.4831734e-05, 0.0004000000, 0.0018464000, 0.0078274000, 0.0285213000, 0.0862132000, 0.2405910000", \ - "8.7548465e-05, 0.0003865000, 0.0018132000, 0.0077689000, 0.0284924000, 0.0860603000, 0.2388666000", \ - "7.1565812e-05, 0.0003434000, 0.0017086000, 0.0075840000, 0.0282045000, 0.0858648000, 0.2402514000", \ - "5.5395829e-05, 0.0003017000, 0.0015897000, 0.0073260000, 0.0278454000, 0.0854784000, 0.2401458000", \ - "3.376863e-05, 0.0002479000, 0.0014784000, 0.0070380000, 0.0275161000, 0.0848950000, 0.2392946000", \ - "9.1498259e-05, 0.0003815000, 0.0017565000, 0.0075421000, 0.0275931000, 0.0849245000, 0.2372588000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0025137000, 0.0058621000, 0.0117206000, 0.0167312000, 0.0076458000, -0.042325100, -0.193669900", \ - "0.0025075000, 0.0058445000, 0.0116866000, 0.0166640000, 0.0075608000, -0.042407300, -0.193755500", \ - "0.0024979000, 0.0058187000, 0.0116317000, 0.0165681000, 0.0074242000, -0.042613500, -0.193964300", \ - "0.0024850000, 0.0057910000, 0.0115644000, 0.0164414000, 0.0072363000, -0.042812600, -0.194200900", \ - "0.0024660000, 0.0057481000, 0.0114746000, 0.0162690000, 0.0069690000, -0.043140100, -0.194515600", \ - "0.0024590000, 0.0057275000, 0.0114233000, 0.0161638000, 0.0067996000, -0.043304600, -0.194614600", \ - "0.0024909000, 0.0058004000, 0.0115252000, 0.0162321000, 0.0067568000, -0.043262700, -0.194607100"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0002400000, 0.0007499000, 0.0025859000, 0.0091681000, 0.0304898000, 0.0885649000, 0.2430417000", \ - "0.0002399000, 0.0007498000, 0.0025874000, 0.0091655000, 0.0304834000, 0.0886760000, 0.2431004000", \ - "0.0002370000, 0.0007433000, 0.0025742000, 0.0091356000, 0.0304400000, 0.0885977000, 0.2430541000", \ - "0.0002272000, 0.0007114000, 0.0025064000, 0.0090032000, 0.0302273000, 0.0883509000, 0.2428266000", \ - "0.0002064000, 0.0006614000, 0.0023773000, 0.0087384000, 0.0298806000, 0.0876724000, 0.2410233000", \ - "0.0001920000, 0.0006243000, 0.0022862000, 0.0085808000, 0.0295661000, 0.0873732000, 0.2419935000", \ - "0.0002618000, 0.0007818000, 0.0025940000, 0.0091537000, 0.0297395000, 0.0875881000, 0.2407577000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.4955840000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.3697110000, 0.3821291000, 0.4064834000, 0.4505107000, 0.5292539000, 0.6791032000, 1.0085125000", \ - "0.3719932000, 0.3841175000, 0.4084383000, 0.4526750000, 0.5314104000, 0.6813136000, 1.0109074000", \ - "0.3792014000, 0.3912015000, 0.4158968000, 0.4601257000, 0.5389924000, 0.6889599000, 1.0185131000", \ - "0.4003194000, 0.4123080000, 0.4369864000, 0.4811505000, 0.5600475000, 0.7097676000, 1.0397132000", \ - "0.4569636000, 0.4689289000, 0.4933796000, 0.5374934000, 0.6163763000, 0.7664933000, 1.0963733000", \ - "0.5949612000, 0.6072993000, 0.6312072000, 0.6752661000, 0.7541716000, 0.9043776000, 1.2342581000", \ - "0.8575388000, 0.8715038000, 0.8992696000, 0.9491435000, 1.0354479000, 1.1928976000, 1.5260854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1233580000, 0.1319687000, 0.1504497000, 0.1909756000, 0.2873219000, 0.5347411000, 1.1745724000", \ - "0.1279499000, 0.1364813000, 0.1549654000, 0.1954973000, 0.2919207000, 0.5392474000, 1.1793275000", \ - "0.1376344000, 0.1461750000, 0.1646999000, 0.2052061000, 0.3015932000, 0.5490702000, 1.1889298000", \ - "0.1587946000, 0.1673710000, 0.1858725000, 0.2262856000, 0.3226828000, 0.5703567000, 1.2103419000", \ - "0.2003222000, 0.2094502000, 0.2286747000, 0.2698190000, 0.3664813000, 0.6143449000, 1.2535770000", \ - "0.2613006000, 0.2717501000, 0.2930585000, 0.3363127000, 0.4344899000, 0.6836418000, 1.3231184000", \ - "0.3241677000, 0.3378284000, 0.3646299000, 0.4128798000, 0.5135682000, 0.7627705000, 1.4043513000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0511932000, 0.0591574000, 0.0742803000, 0.1039026000, 0.1677521000, 0.3145278000, 0.7167490000", \ - "0.0512691000, 0.0589226000, 0.0743005000, 0.1038800000, 0.1677248000, 0.3144344000, 0.7157439000", \ - "0.0516731000, 0.0591442000, 0.0744220000, 0.1040973000, 0.1676281000, 0.3144721000, 0.7169683000", \ - "0.0516122000, 0.0590457000, 0.0744135000, 0.1040006000, 0.1676312000, 0.3147049000, 0.7179108000", \ - "0.0520881000, 0.0596834000, 0.0743697000, 0.1040181000, 0.1676502000, 0.3145722000, 0.7159336000", \ - "0.0519432000, 0.0594158000, 0.0751323000, 0.1045630000, 0.1678891000, 0.3150300000, 0.7178744000", \ - "0.0638079000, 0.0722192000, 0.0888189000, 0.1195394000, 0.1826556000, 0.3260739000, 0.7212288000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0288967000, 0.0364613000, 0.0548606000, 0.1028969000, 0.2338579000, 0.5840881000, 1.4902091000", \ - "0.0289706000, 0.0364366000, 0.0548181000, 0.1028554000, 0.2342291000, 0.5828681000, 1.4942312000", \ - "0.0289556000, 0.0364696000, 0.0548289000, 0.1029514000, 0.2338474000, 0.5841147000, 1.4900750000", \ - "0.0290540000, 0.0363817000, 0.0548358000, 0.1029916000, 0.2338407000, 0.5840418000, 1.4906811000", \ - "0.0313884000, 0.0390782000, 0.0571190000, 0.1041330000, 0.2343047000, 0.5825633000, 1.4945883000", \ - "0.0377170000, 0.0453841000, 0.0637608000, 0.1090725000, 0.2376277000, 0.5839453000, 1.4944895000", \ - "0.0512908000, 0.0602969000, 0.0787956000, 0.1222590000, 0.2421126000, 0.5864950000, 1.4928558000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.3404756000, 0.3524988000, 0.3769637000, 0.4211198000, 0.5002043000, 0.6503495000, 0.9801778000", \ - "0.3433348000, 0.3556426000, 0.3798627000, 0.4239534000, 0.5029080000, 0.6530538000, 0.9829935000", \ - "0.3513643000, 0.3633721000, 0.3878393000, 0.4319195000, 0.5109381000, 0.6611658000, 0.9911855000", \ - "0.3739788000, 0.3859591000, 0.4106995000, 0.4545816000, 0.5336961000, 0.6841335000, 1.0140271000", \ - "0.4381999000, 0.4502425000, 0.4741861000, 0.5184926000, 0.5976123000, 0.7479103000, 1.0780227000", \ - "0.5976993000, 0.6097984000, 0.6341097000, 0.6781723000, 0.7573414000, 0.9076040000, 1.2374853000", \ - "0.9081275000, 0.9232353000, 0.9525427000, 1.0043754000, 1.0915073000, 1.2479378000, 1.5798342000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1180304000, 0.1274550000, 0.1475776000, 0.1901270000, 0.2876224000, 0.5352770000, 1.1748305000", \ - "0.1229423000, 0.1324488000, 0.1525706000, 0.1950608000, 0.2925654000, 0.5402166000, 1.1796835000", \ - "0.1330144000, 0.1424319000, 0.1625906000, 0.2051044000, 0.3025655000, 0.5503380000, 1.1907281000", \ - "0.1541824000, 0.1636274000, 0.1836885000, 0.2260288000, 0.3237490000, 0.5714778000, 1.2109622000", \ - "0.1941855000, 0.2042094000, 0.2253355000, 0.2687902000, 0.3668405000, 0.6148230000, 1.2545848000", \ - "0.2541498000, 0.2650761000, 0.2880453000, 0.3339311000, 0.4337692000, 0.6833729000, 1.3234461000", \ - "0.3181514000, 0.3324599000, 0.3605110000, 0.4119659000, 0.5166619000, 0.7669535000, 1.4090834000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0523254000, 0.0598054000, 0.0745161000, 0.1040612000, 0.1675340000, 0.3143724000, 0.7164108000", \ - "0.0511772000, 0.0594174000, 0.0744499000, 0.1044929000, 0.1677581000, 0.3144776000, 0.7179062000", \ - "0.0511577000, 0.0587865000, 0.0743150000, 0.1042267000, 0.1676924000, 0.3143472000, 0.7170003000", \ - "0.0515044000, 0.0588800000, 0.0741881000, 0.1046393000, 0.1676918000, 0.3141142000, 0.7162446000", \ - "0.0509738000, 0.0586423000, 0.0744865000, 0.1042443000, 0.1676236000, 0.3139693000, 0.7160683000", \ - "0.0514288000, 0.0587231000, 0.0747573000, 0.1041484000, 0.1676028000, 0.3144526000, 0.7163026000", \ - "0.0714984000, 0.0795827000, 0.0951407000, 0.1242860000, 0.1840821000, 0.3249688000, 0.7187575000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0319778000, 0.0398991000, 0.0587041000, 0.1061775000, 0.2351831000, 0.5831888000, 1.4933410000", \ - "0.0321531000, 0.0399103000, 0.0586111000, 0.1061518000, 0.2351830000, 0.5845119000, 1.4943360000", \ - "0.0318791000, 0.0399765000, 0.0586371000, 0.1061687000, 0.2352124000, 0.5844739000, 1.4942269000", \ - "0.0320177000, 0.0399588000, 0.0586676000, 0.1061222000, 0.2352412000, 0.5848107000, 1.4945827000", \ - "0.0344146000, 0.0427749000, 0.0615958000, 0.1086599000, 0.2359759000, 0.5850045000, 1.4932944000", \ - "0.0400243000, 0.0481225000, 0.0675243000, 0.1147866000, 0.2405257000, 0.5852387000, 1.4918345000", \ - "0.0537899000, 0.0630973000, 0.0837380000, 0.1266061000, 0.2466445000, 0.5886104000, 1.4955839000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.3142887000, 0.3262123000, 0.3501174000, 0.3942426000, 0.4738746000, 0.6249912000, 0.9553228000", \ - "0.3173671000, 0.3292342000, 0.3532585000, 0.3974176000, 0.4771772000, 0.6282715000, 0.9589116000", \ - "0.3255445000, 0.3373526000, 0.3613433000, 0.4055155000, 0.4851441000, 0.6362472000, 0.9668307000", \ - "0.3504597000, 0.3623066000, 0.3862508000, 0.4303600000, 0.5101261000, 0.6611821000, 0.9918358000", \ - "0.4158643000, 0.4277804000, 0.4519043000, 0.4958522000, 0.5754419000, 0.7265755000, 1.0572533000", \ - "0.5763706000, 0.5881844000, 0.6122522000, 0.6563397000, 0.7359839000, 0.8870844000, 1.2178289000", \ - "0.8792226000, 0.8944478000, 0.9238068000, 0.9760841000, 1.0646952000, 1.2223476000, 1.5552110000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1127152000, 0.1222831000, 0.1424742000, 0.1851519000, 0.2826990000, 0.5303974000, 1.1705984000", \ - "0.1171133000, 0.1266871000, 0.1468987000, 0.1895485000, 0.2871272000, 0.5348413000, 1.1745728000", \ - "0.1276252000, 0.1371942000, 0.1574593000, 0.2000199000, 0.2976016000, 0.5453441000, 1.1851675000", \ - "0.1517220000, 0.1612616000, 0.1813815000, 0.2237757000, 0.3212998000, 0.5691563000, 1.2091045000", \ - "0.1986012000, 0.2088314000, 0.2298845000, 0.2731116000, 0.3709336000, 0.6189741000, 1.2594241000", \ - "0.2574836000, 0.2700069000, 0.2945927000, 0.3408851000, 0.4404420000, 0.6895059000, 1.3296927000", \ - "0.3080726000, 0.3246074000, 0.3566083000, 0.4124697000, 0.5164099000, 0.7655936000, 1.4068799000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0495271000, 0.0572260000, 0.0724024000, 0.1025337000, 0.1669524000, 0.3141055000, 0.7157069000", \ - "0.0491827000, 0.0566576000, 0.0721606000, 0.1026188000, 0.1669563000, 0.3142421000, 0.7170819000", \ - "0.0491862000, 0.0566611000, 0.0721420000, 0.1028914000, 0.1670972000, 0.3140967000, 0.7175907000", \ - "0.0491765000, 0.0567641000, 0.0721541000, 0.1029300000, 0.1668745000, 0.3141581000, 0.7168128000", \ - "0.0500207000, 0.0579778000, 0.0731080000, 0.1025614000, 0.1668014000, 0.3138833000, 0.7143717000", \ - "0.0497272000, 0.0576969000, 0.0726505000, 0.1031212000, 0.1671626000, 0.3137406000, 0.7153308000", \ - "0.0692586000, 0.0781350000, 0.0946552000, 0.1254097000, 0.1854109000, 0.3255190000, 0.7201962000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0327510000, 0.0403840000, 0.0589931000, 0.1063444000, 0.2352274000, 0.5827552000, 1.4937874000", \ - "0.0327467000, 0.0403812000, 0.0590345000, 0.1064005000, 0.2352442000, 0.5832970000, 1.4936842000", \ - "0.0327461000, 0.0403625000, 0.0589843000, 0.1064081000, 0.2352450000, 0.5832329000, 1.4942818000", \ - "0.0326918000, 0.0404242000, 0.0590274000, 0.1065013000, 0.2352374000, 0.5832323000, 1.4947524000", \ - "0.0371840000, 0.0444766000, 0.0619306000, 0.1083212000, 0.2357289000, 0.5831478000, 1.4936289000", \ - "0.0481397000, 0.0553578000, 0.0719018000, 0.1154904000, 0.2396997000, 0.5846636000, 1.4913101000", \ - "0.0662747000, 0.0757968000, 0.0944721000, 0.1343917000, 0.2476722000, 0.5867068000, 1.4926482000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B&!CIN) | (!A&B&!CIN) | (!A&!B&CIN) | (A&B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0014713000, 0.0033517000, 0.0064643000, 0.0077871000, -0.004599600, -0.057068900, -0.208713300", \ - "0.0014664000, 0.0033415000, 0.0064483000, 0.0077651000, -0.004638600, -0.057126000, -0.208747400", \ - "0.0014588000, 0.0033207000, 0.0064088000, 0.0076727000, -0.004760500, -0.057271700, -0.208920600", \ - "0.0014424000, 0.0032853000, 0.0063107000, 0.0075206000, -0.005008100, -0.057556800, -0.209243700", \ - "0.0014263000, 0.0032459000, 0.0062116000, 0.0073419000, -0.005248400, -0.057897800, -0.209587900", \ - "0.0014045000, 0.0031967000, 0.0060767000, 0.0071136000, -0.005587700, -0.058300200, -0.210043800", \ - "0.0015263000, 0.0034898000, 0.0065971000, 0.0075618000, -0.005461600, -0.058577700, -0.210317500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0011661000, 0.0029993000, 0.0076107000, 0.0185771000, 0.0435784000, 0.1039593000, 0.2590121000", \ - "0.0011545000, 0.0029712000, 0.0075505000, 0.0184539000, 0.0434057000, 0.1041736000, 0.2592334000", \ - "0.0011386000, 0.0029213000, 0.0074331000, 0.0182586000, 0.0431606000, 0.1033204000, 0.2575754000", \ - "0.0011122000, 0.0028712000, 0.0073249000, 0.0180633000, 0.0428468000, 0.1030737000, 0.2573633000", \ - "0.0010914000, 0.0028224000, 0.0072264000, 0.0178694000, 0.0425857000, 0.1027537000, 0.2580562000", \ - "0.0010899000, 0.0028151000, 0.0072108000, 0.0178564000, 0.0425471000, 0.1027074000, 0.2569871000", \ - "0.0010857000, 0.0027712000, 0.0070434000, 0.0178901000, 0.0426962000, 0.1028697000, 0.2569314000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0014528000, 0.0033511000, 0.0064773000, 0.0078175000, -0.004534600, -0.057009500, -0.208545300", \ - "0.0014540000, 0.0033531000, 0.0064821000, 0.0078248000, -0.004521100, -0.056979300, -0.208619600", \ - "0.0014474000, 0.0033358000, 0.0064513000, 0.0077669000, -0.004618800, -0.057074800, -0.208654800", \ - "0.0014312000, 0.0032931000, 0.0063509000, 0.0075822000, -0.004865400, -0.057359600, -0.208955900", \ - "0.0014002000, 0.0032226000, 0.0062051000, 0.0073234000, -0.005258500, -0.057839200, -0.209468800", \ - "0.0013754000, 0.0031436000, 0.0060483000, 0.0070351000, -0.005664900, -0.058354100, -0.210077100", \ - "0.0015281000, 0.0034893000, 0.0065998000, 0.0075416000, -0.005489700, -0.058566000, -0.210246900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0011006000, 0.0028389000, 0.0072560000, 0.0179565000, 0.0426913000, 0.1030177000, 0.2573601000", \ - "0.0010971000, 0.0028275000, 0.0072503000, 0.0179174000, 0.0426839000, 0.1028591000, 0.2582220000", \ - "0.0010821000, 0.0027940000, 0.0071732000, 0.0177752000, 0.0424678000, 0.1026770000, 0.2568906000", \ - "0.0010635000, 0.0027512000, 0.0070692000, 0.0176140000, 0.0422185000, 0.1021665000, 0.2564188000", \ - "0.0010420000, 0.0026966000, 0.0069498000, 0.0173973000, 0.0418901000, 0.1018641000, 0.2559707000", \ - "0.0010366000, 0.0026841000, 0.0069418000, 0.0173623000, 0.0418688000, 0.1019309000, 0.2559980000", \ - "0.0010254000, 0.0026300000, 0.0068991000, 0.0175240000, 0.0420932000, 0.1022932000, 0.2574805000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0015985000, 0.0036974000, 0.0072274000, 0.0091652000, -0.002584400, -0.054664100, -0.206067500", \ - "0.0015996000, 0.0036975000, 0.0072272000, 0.0091811000, -0.002589200, -0.054660900, -0.206051100", \ - "0.0015959000, 0.0036894000, 0.0072092000, 0.0091325000, -0.002626900, -0.054715900, -0.206125200", \ - "0.0015807000, 0.0036544000, 0.0071354000, 0.0090004000, -0.002830600, -0.054956400, -0.206391500", \ - "0.0015523000, 0.0035881000, 0.0069975000, 0.0087369000, -0.003212400, -0.055405500, -0.206915000", \ - "0.0015414000, 0.0035270000, 0.0068730000, 0.0085784000, -0.003420800, -0.055659500, -0.207184700", \ - "0.0016980000, 0.0039058000, 0.0074855000, 0.0091529000, -0.003177300, -0.055600000, -0.206959300"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0009756000, 0.0025377000, 0.0066133000, 0.0167295000, 0.0410035000, 0.1008994000, 0.2549404000", \ - "0.0009684000, 0.0025228000, 0.0065583000, 0.0166702000, 0.0408759000, 0.1005473000, 0.2547157000", \ - "0.0009586000, 0.0024968000, 0.0065084000, 0.0165658000, 0.0407175000, 0.1004098000, 0.2544211000", \ - "0.0009455000, 0.0024613000, 0.0064315000, 0.0164391000, 0.0405876000, 0.1001771000, 0.2543109000", \ - "0.0009245000, 0.0024148000, 0.0063454000, 0.0162681000, 0.0402857000, 0.1000145000, 0.2540709000", \ - "0.0009144000, 0.0023816000, 0.0062790000, 0.0161631000, 0.0401377000, 0.0997943000, 0.2537876000", \ - "0.0009084000, 0.0023398000, 0.0061973000, 0.0162309000, 0.0403531000, 0.1000601000, 0.2539499000"); - } - } - max_capacitance : 0.1556500000; - max_transition : 1.4982920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.4260766000, 0.4385881000, 0.4626894000, 0.5068111000, 0.5857918000, 0.7357021000, 1.0678344000", \ - "0.4274389000, 0.4399629000, 0.4641553000, 0.5084228000, 0.5872512000, 0.7376459000, 1.0695572000", \ - "0.4356284000, 0.4476548000, 0.4720219000, 0.5162831000, 0.5947480000, 0.7453371000, 1.0771845000", \ - "0.4574336000, 0.4695214000, 0.4941028000, 0.5382301000, 0.6170983000, 0.7671914000, 1.0996366000", \ - "0.5103359000, 0.5228596000, 0.5469203000, 0.5906575000, 0.6698886000, 0.8200043000, 1.1520143000", \ - "0.6282224000, 0.6402899000, 0.6644031000, 0.7087517000, 0.7876481000, 0.9379387000, 1.2700058000", \ - "0.8524262000, 0.8658340000, 0.8919628000, 0.9397484000, 1.0235957000, 1.1787697000, 1.5138910000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1221775000, 0.1308186000, 0.1496339000, 0.1901795000, 0.2854948000, 0.5307468000, 1.1682932000", \ - "0.1264587000, 0.1350466000, 0.1537535000, 0.1943145000, 0.2899631000, 0.5341560000, 1.1739663000", \ - "0.1345994000, 0.1431260000, 0.1618694000, 0.2024200000, 0.2981427000, 0.5426224000, 1.1823346000", \ - "0.1514510000, 0.1600310000, 0.1787370000, 0.2192601000, 0.3148873000, 0.5603688000, 1.1978702000", \ - "0.1835206000, 0.1925265000, 0.2118626000, 0.2531297000, 0.3494354000, 0.5945097000, 1.2336399000", \ - "0.2317103000, 0.2418505000, 0.2626210000, 0.3056597000, 0.4031679000, 0.6490932000, 1.2872057000", \ - "0.2773318000, 0.2901435000, 0.3151719000, 0.3629662000, 0.4623378000, 0.7086414000, 1.3466283000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0579993000, 0.0652021000, 0.0796000000, 0.1093114000, 0.1734488000, 0.3224609000, 0.7246836000", \ - "0.0576257000, 0.0657441000, 0.0800773000, 0.1089979000, 0.1735305000, 0.3213520000, 0.7248199000", \ - "0.0572543000, 0.0644770000, 0.0793523000, 0.1088570000, 0.1736220000, 0.3220671000, 0.7255640000", \ - "0.0576269000, 0.0652840000, 0.0803344000, 0.1090586000, 0.1735560000, 0.3224222000, 0.7247937000", \ - "0.0572582000, 0.0650185000, 0.0797012000, 0.1101728000, 0.1728671000, 0.3220387000, 0.7255438000", \ - "0.0571148000, 0.0654420000, 0.0794557000, 0.1093367000, 0.1712910000, 0.3207950000, 0.7243538000", \ - "0.0667457000, 0.0750635000, 0.0903055000, 0.1199072000, 0.1827102000, 0.3296688000, 0.7298842000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0309098000, 0.0384883000, 0.0571857000, 0.1053659000, 0.2355865000, 0.5856517000, 1.4957366000", \ - "0.0307674000, 0.0384986000, 0.0572223000, 0.1053971000, 0.2355605000, 0.5845061000, 1.4980217000", \ - "0.0308027000, 0.0386566000, 0.0571722000, 0.1052370000, 0.2353642000, 0.5846062000, 1.4982924000", \ - "0.0307870000, 0.0383953000, 0.0571698000, 0.1051790000, 0.2355400000, 0.5856699000, 1.4954206000", \ - "0.0328277000, 0.0406458000, 0.0593248000, 0.1068687000, 0.2360193000, 0.5845626000, 1.4972266000", \ - "0.0377859000, 0.0454871000, 0.0642930000, 0.1103018000, 0.2381854000, 0.5846933000, 1.4953137000", \ - "0.0499442000, 0.0584589000, 0.0778584000, 0.1203680000, 0.2419422000, 0.5869740000, 1.4907092000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3408776000, 0.3504909000, 0.3701108000, 0.4064606000, 0.4738336000, 0.6109917000, 0.9353631000", \ - "0.3454084000, 0.3551826000, 0.3746397000, 0.4112193000, 0.4785166000, 0.6155110000, 0.9398787000", \ - "0.3550571000, 0.3646208000, 0.3842603000, 0.4206079000, 0.4879652000, 0.6251503000, 0.9495335000", \ - "0.3749890000, 0.3846279000, 0.4041576000, 0.4405277000, 0.5079648000, 0.6450096000, 0.9696794000", \ - "0.4157815000, 0.4254491000, 0.4449242000, 0.4814745000, 0.5487637000, 0.6857647000, 1.0100160000", \ - "0.4826360000, 0.4924416000, 0.5117456000, 0.5477890000, 0.6147857000, 0.7520508000, 1.0764661000", \ - "0.5633679000, 0.5732450000, 0.5926901000, 0.6290602000, 0.6963418000, 0.8329208000, 1.1565812000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.4949451000, 0.5045389000, 0.5243310000, 0.5658496000, 0.6627745000, 0.9090774000, 1.5467657000", \ - "0.4971982000, 0.5067720000, 0.5264827000, 0.5679721000, 0.6648145000, 0.9110953000, 1.5495346000", \ - "0.5042330000, 0.5142295000, 0.5340687000, 0.5755665000, 0.6724183000, 0.9185895000, 1.5571706000", \ - "0.5256357000, 0.5352403000, 0.5550478000, 0.5965840000, 0.6934743000, 0.9398033000, 1.5773728000", \ - "0.5817865000, 0.5914179000, 0.6113557000, 0.6527585000, 0.7495461000, 0.9959644000, 1.6352842000", \ - "0.7185449000, 0.7281693000, 0.7479996000, 0.7895310000, 0.8864389000, 1.1327606000, 1.7701367000", \ - "0.9918300000, 1.0019717000, 1.0225293000, 1.0643195000, 1.1609316000, 1.4071077000, 2.0451187000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0411380000, 0.0472344000, 0.0606754000, 0.0869359000, 0.1461428000, 0.2965520000, 0.7131840000", \ - "0.0419228000, 0.0479797000, 0.0598347000, 0.0863261000, 0.1463380000, 0.2969207000, 0.7128352000", \ - "0.0415182000, 0.0482507000, 0.0602875000, 0.0867925000, 0.1461464000, 0.2964683000, 0.7129447000", \ - "0.0410172000, 0.0473043000, 0.0597182000, 0.0860409000, 0.1457439000, 0.2967233000, 0.7163169000", \ - "0.0419035000, 0.0481270000, 0.0598438000, 0.0863025000, 0.1461685000, 0.2968848000, 0.7130864000", \ - "0.0414800000, 0.0475029000, 0.0596537000, 0.0859966000, 0.1458125000, 0.2964193000, 0.7129460000", \ - "0.0418021000, 0.0477345000, 0.0599564000, 0.0861207000, 0.1460199000, 0.2958637000, 0.7064188000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0367750000, 0.0435675000, 0.0605150000, 0.1065177000, 0.2356558000, 0.5828709000, 1.4915362000", \ - "0.0364928000, 0.0435320000, 0.0604902000, 0.1064682000, 0.2354211000, 0.5827996000, 1.4934298000", \ - "0.0370197000, 0.0436626000, 0.0603856000, 0.1064057000, 0.2359326000, 0.5829360000, 1.4914125000", \ - "0.0369011000, 0.0436102000, 0.0604254000, 0.1064455000, 0.2356486000, 0.5827548000, 1.4936936000", \ - "0.0368641000, 0.0436940000, 0.0605774000, 0.1064795000, 0.2358460000, 0.5828125000, 1.4913375000", \ - "0.0369718000, 0.0436879000, 0.0606201000, 0.1065803000, 0.2355062000, 0.5827624000, 1.4938905000", \ - "0.0396878000, 0.0465785000, 0.0627424000, 0.1076927000, 0.2360350000, 0.5824933000, 1.4936904000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.4037395000, 0.4162677000, 0.4405226000, 0.4849551000, 0.5642249000, 0.7148142000, 1.0476475000", \ - "0.4065496000, 0.4186395000, 0.4431203000, 0.4874582000, 0.5662537000, 0.7174592000, 1.0501494000", \ - "0.4151356000, 0.4277415000, 0.4519937000, 0.4963084000, 0.5755044000, 0.7262411000, 1.0593568000", \ - "0.4387521000, 0.4513639000, 0.4756213000, 0.5198879000, 0.5991743000, 0.7498865000, 1.0830379000", \ - "0.4967015000, 0.5092046000, 0.5335352000, 0.5774983000, 0.6568416000, 0.8079836000, 1.1411371000", \ - "0.6332702000, 0.6463156000, 0.6707193000, 0.7151675000, 0.7947076000, 0.9460427000, 1.2792258000", \ - "0.9012590000, 0.9143790000, 0.9420930000, 0.9905210000, 1.0768137000, 1.2329623000, 1.5693166000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1154437000, 0.1241130000, 0.1429421000, 0.1835638000, 0.2793429000, 0.5253410000, 1.1636694000", \ - "0.1196064000, 0.1282048000, 0.1469378000, 0.1875850000, 0.2834607000, 0.5293066000, 1.1671696000", \ - "0.1284737000, 0.1371475000, 0.1559652000, 0.1965735000, 0.2924544000, 0.5385347000, 1.1755483000", \ - "0.1490250000, 0.1576565000, 0.1763478000, 0.2169798000, 0.3130269000, 0.5591164000, 1.1964797000", \ - "0.1889593000, 0.1980355000, 0.2173279000, 0.2584941000, 0.3549198000, 0.6012563000, 1.2391046000", \ - "0.2446483000, 0.2547243000, 0.2758354000, 0.3185482000, 0.4156422000, 0.6621320000, 1.3004516000", \ - "0.2958694000, 0.3089132000, 0.3348666000, 0.3817005000, 0.4808116000, 0.7272908000, 1.3654592000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0578207000, 0.0652368000, 0.0800962000, 0.1110080000, 0.1719996000, 0.3219497000, 0.7252840000", \ - "0.0578665000, 0.0648610000, 0.0798136000, 0.1093414000, 0.1741430000, 0.3228007000, 0.7265550000", \ - "0.0580315000, 0.0655418000, 0.0808224000, 0.1095259000, 0.1741812000, 0.3231507000, 0.7256385000", \ - "0.0580368000, 0.0655437000, 0.0809424000, 0.1097330000, 0.1741251000, 0.3232137000, 0.7255771000", \ - "0.0577545000, 0.0652185000, 0.0801605000, 0.1103973000, 0.1725982000, 0.3229652000, 0.7262018000", \ - "0.0580735000, 0.0651139000, 0.0801525000, 0.1098911000, 0.1739027000, 0.3232380000, 0.7257106000", \ - "0.0698295000, 0.0785155000, 0.0928779000, 0.1232753000, 0.1860820000, 0.3321915000, 0.7303588000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0309818000, 0.0385275000, 0.0572819000, 0.1055653000, 0.2358698000, 0.5859920000, 1.4961911000", \ - "0.0308252000, 0.0385496000, 0.0572942000, 0.1054605000, 0.2362020000, 0.5849886000, 1.4943035000", \ - "0.0309320000, 0.0385043000, 0.0573106000, 0.1055852000, 0.2361621000, 0.5857018000, 1.4929897000", \ - "0.0307424000, 0.0385372000, 0.0571956000, 0.1055952000, 0.2361786000, 0.5851104000, 1.4927450000", \ - "0.0328190000, 0.0407116000, 0.0594423000, 0.1068651000, 0.2364818000, 0.5858881000, 1.4950428000", \ - "0.0396623000, 0.0469371000, 0.0647647000, 0.1107043000, 0.2377473000, 0.5855903000, 1.4944881000", \ - "0.0529001000, 0.0610516000, 0.0798450000, 0.1218246000, 0.2415484000, 0.5878333000, 1.4942707000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3668359000, 0.3766910000, 0.3966321000, 0.4335831000, 0.5013459000, 0.6392130000, 0.9641519000", \ - "0.3727065000, 0.3825719000, 0.4025169000, 0.4394805000, 0.5073167000, 0.6451964000, 0.9702454000", \ - "0.3826718000, 0.3927361000, 0.4125088000, 0.4495753000, 0.5176362000, 0.6552143000, 0.9804070000", \ - "0.4003996000, 0.4101628000, 0.4301141000, 0.4669435000, 0.5351128000, 0.6727572000, 0.9974803000", \ - "0.4368400000, 0.4466798000, 0.4666113000, 0.5034948000, 0.5716985000, 0.7093472000, 1.0345590000", \ - "0.5016179000, 0.5112695000, 0.5309542000, 0.5673626000, 0.6349986000, 0.7724967000, 1.0977106000", \ - "0.5796710000, 0.5893135000, 0.6089827000, 0.6454270000, 0.7128231000, 0.8499672000, 1.1744781000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.4635034000, 0.4730468000, 0.4927908000, 0.5342896000, 0.6312098000, 0.8775071000, 1.5149026000", \ - "0.4661046000, 0.4757375000, 0.4955135000, 0.5369918000, 0.6337970000, 0.8802141000, 1.5194728000", \ - "0.4741349000, 0.4837251000, 0.5035187000, 0.5449641000, 0.6418102000, 0.8882066000, 1.5262593000", \ - "0.4967671000, 0.5063196000, 0.5261532000, 0.5675485000, 0.6643494000, 0.9103427000, 1.5496007000", \ - "0.5605704000, 0.5700959000, 0.5898527000, 0.6312866000, 0.7281290000, 0.9742976000, 1.6123821000", \ - "0.7194076000, 0.7289869000, 0.7488249000, 0.7902799000, 0.8871389000, 1.1335486000, 1.7719477000", \ - "1.0443857000, 1.0546627000, 1.0751322000, 1.1171715000, 1.2141002000, 1.4604863000, 2.0994142000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0427437000, 0.0491005000, 0.0614491000, 0.0875189000, 0.1472788000, 0.2976785000, 0.7170884000", \ - "0.0427721000, 0.0491385000, 0.0614840000, 0.0875965000, 0.1472568000, 0.2976345000, 0.7125214000", \ - "0.0430603000, 0.0495769000, 0.0617752000, 0.0879417000, 0.1476107000, 0.2974743000, 0.7167725000", \ - "0.0426617000, 0.0489352000, 0.0624440000, 0.0887214000, 0.1475418000, 0.2976548000, 0.7138130000", \ - "0.0428765000, 0.0492113000, 0.0615597000, 0.0879863000, 0.1474001000, 0.2976482000, 0.7181881000", \ - "0.0425508000, 0.0482936000, 0.0605213000, 0.0871174000, 0.1464887000, 0.2972045000, 0.7170650000", \ - "0.0416653000, 0.0478448000, 0.0607617000, 0.0870362000, 0.1463698000, 0.2965910000, 0.7083781000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0362443000, 0.0432253000, 0.0603522000, 0.1064466000, 0.2357075000, 0.5828175000, 1.4938079000", \ - "0.0361090000, 0.0429489000, 0.0603917000, 0.1064116000, 0.2358689000, 0.5828498000, 1.4915229000", \ - "0.0360070000, 0.0432863000, 0.0603637000, 0.1064545000, 0.2356721000, 0.5814041000, 1.4941386000", \ - "0.0363943000, 0.0434024000, 0.0603423000, 0.1065318000, 0.2356657000, 0.5819122000, 1.4902076000", \ - "0.0362603000, 0.0432803000, 0.0602270000, 0.1064500000, 0.2359717000, 0.5830131000, 1.4928347000", \ - "0.0361125000, 0.0429853000, 0.0603009000, 0.1064832000, 0.2357304000, 0.5813819000, 1.4940309000", \ - "0.0394939000, 0.0461023000, 0.0629609000, 0.1081180000, 0.2356292000, 0.5816274000, 1.4911645000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3939992000, 0.4062507000, 0.4302815000, 0.4746060000, 0.5535460000, 0.7044309000, 1.0369295000", \ - "0.3934876000, 0.4055179000, 0.4300529000, 0.4742012000, 0.5528713000, 0.7036064000, 1.0361825000", \ - "0.3960144000, 0.4080740000, 0.4321834000, 0.4765206000, 0.5556465000, 0.7054610000, 1.0380853000", \ - "0.4135781000, 0.4261971000, 0.4501519000, 0.4944566000, 0.5734225000, 0.7235891000, 1.0562291000", \ - "0.4730284000, 0.4851157000, 0.5093531000, 0.5538178000, 0.6325000000, 0.7831801000, 1.1154672000", \ - "0.6239024000, 0.6358322000, 0.6599224000, 0.7040091000, 0.7827853000, 0.9336391000, 1.2661059000", \ - "0.9335710000, 0.9476349000, 0.9752044000, 1.0240989000, 1.1069311000, 1.2612852000, 1.5957125000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1128877000, 0.1215451000, 0.1403321000, 0.1809772000, 0.2768346000, 0.5230038000, 1.1613235000", \ - "0.1171609000, 0.1257495000, 0.1444369000, 0.1851121000, 0.2812924000, 0.5262998000, 1.1667354000", \ - "0.1266839000, 0.1353822000, 0.1541125000, 0.1947944000, 0.2907047000, 0.5367763000, 1.1751112000", \ - "0.1491306000, 0.1577542000, 0.1765121000, 0.2171404000, 0.3133527000, 0.5595933000, 1.1998195000", \ - "0.1924346000, 0.2013168000, 0.2201066000, 0.2619333000, 0.3582863000, 0.6055835000, 1.2427409000", \ - "0.2461096000, 0.2564647000, 0.2766480000, 0.3190994000, 0.4159651000, 0.6627163000, 1.3013793000", \ - "0.2884734000, 0.3015638000, 0.3268688000, 0.3737120000, 0.4716735000, 0.7167500000, 1.3558767000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0578419000, 0.0654323000, 0.0798928000, 0.1088125000, 0.1736223000, 0.3214416000, 0.7251518000", \ - "0.0574733000, 0.0646191000, 0.0807114000, 0.1088269000, 0.1729833000, 0.3219505000, 0.7255102000", \ - "0.0577863000, 0.0649663000, 0.0796550000, 0.1104144000, 0.1732975000, 0.3221521000, 0.7245383000", \ - "0.0575889000, 0.0655192000, 0.0797809000, 0.1104807000, 0.1735725000, 0.3223620000, 0.7232079000", \ - "0.0572681000, 0.0643800000, 0.0792915000, 0.1099004000, 0.1726653000, 0.3218170000, 0.7253194000", \ - "0.0577861000, 0.0650296000, 0.0795678000, 0.1097666000, 0.1738256000, 0.3215050000, 0.7249724000", \ - "0.0735341000, 0.0813543000, 0.0963581000, 0.1231871000, 0.1839058000, 0.3293550000, 0.7275407000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0306379000, 0.0384719000, 0.0572561000, 0.1052780000, 0.2357123000, 0.5858437000, 1.4962575000", \ - "0.0307961000, 0.0384991000, 0.0572892000, 0.1054466000, 0.2353924000, 0.5843075000, 1.4982323000", \ - "0.0307787000, 0.0385839000, 0.0573344000, 0.1051828000, 0.2356055000, 0.5857458000, 1.4962880000", \ - "0.0307907000, 0.0383171000, 0.0570948000, 0.1052461000, 0.2359869000, 0.5861319000, 1.4952152000", \ - "0.0328155000, 0.0404543000, 0.0593715000, 0.1067546000, 0.2362968000, 0.5851705000, 1.4976244000", \ - "0.0401729000, 0.0473471000, 0.0650280000, 0.1098636000, 0.2383473000, 0.5855049000, 1.4963988000", \ - "0.0547590000, 0.0628108000, 0.0815765000, 0.1210271000, 0.2417789000, 0.5877419000, 1.4942778000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3617001000, 0.3715489000, 0.3914981000, 0.4284796000, 0.4963165000, 0.6342173000, 0.9592738000", \ - "0.3662484000, 0.3760692000, 0.3960051000, 0.4329966000, 0.5010570000, 0.6387623000, 0.9637671000", \ - "0.3763414000, 0.3861613000, 0.4060850000, 0.4430730000, 0.5108869000, 0.6488234000, 0.9738595000", \ - "0.3966774000, 0.4065087000, 0.4264237000, 0.4633361000, 0.5312186000, 0.6690666000, 0.9941845000", \ - "0.4395410000, 0.4496542000, 0.4694605000, 0.5064216000, 0.5744658000, 0.7120484000, 1.0371483000", \ - "0.5012490000, 0.5110659000, 0.5309702000, 0.5680121000, 0.6366702000, 0.7749615000, 1.1003001000", \ - "0.5624646000, 0.5720430000, 0.5915879000, 0.6282136000, 0.6963843000, 0.8349839000, 1.1632443000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.4423545000, 0.4508139000, 0.4692058000, 0.5090147000, 0.6055059000, 0.8520150000, 1.4903208000", \ - "0.4456424000, 0.4541693000, 0.4724431000, 0.5125362000, 0.6089892000, 0.8550146000, 1.4942342000", \ - "0.4535651000, 0.4620501000, 0.4804681000, 0.5206973000, 0.6169887000, 0.8633073000, 1.5013265000", \ - "0.4783702000, 0.4869958000, 0.5052769000, 0.5454869000, 0.6418323000, 0.8874970000, 1.5268045000", \ - "0.5433909000, 0.5520443000, 0.5704460000, 0.6103322000, 0.7068708000, 0.9532083000, 1.5907509000", \ - "0.7022589000, 0.7105795000, 0.7290757000, 0.7691603000, 0.8656417000, 1.1119662000, 1.7500323000", \ - "1.0189425000, 1.0278033000, 1.0469966000, 1.0872392000, 1.1833103000, 1.4299690000, 2.0690993000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0428382000, 0.0492033000, 0.0615534000, 0.0876431000, 0.1473950000, 0.2977930000, 0.7179623000", \ - "0.0429785000, 0.0492326000, 0.0615879000, 0.0889239000, 0.1473817000, 0.2980307000, 0.7163240000", \ - "0.0429504000, 0.0492259000, 0.0615816000, 0.0876652000, 0.1474623000, 0.2979482000, 0.7172886000", \ - "0.0428586000, 0.0492207000, 0.0615706000, 0.0877142000, 0.1472463000, 0.2976886000, 0.7181271000", \ - "0.0435149000, 0.0494456000, 0.0617491000, 0.0880709000, 0.1477309000, 0.2976686000, 0.7132864000", \ - "0.0419182000, 0.0484868000, 0.0614918000, 0.0890657000, 0.1483986000, 0.2981220000, 0.7144145000", \ - "0.0412454000, 0.0470259000, 0.0600064000, 0.0870001000, 0.1478272000, 0.3000520000, 0.7145208000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0322897000, 0.0393496000, 0.0568906000, 0.1043773000, 0.2350898000, 0.5820044000, 1.4941504000", \ - "0.0321492000, 0.0392845000, 0.0571171000, 0.1043606000, 0.2355838000, 0.5825964000, 1.4898578000", \ - "0.0322196000, 0.0391513000, 0.0571637000, 0.1042591000, 0.2356743000, 0.5832093000, 1.4935877000", \ - "0.0320832000, 0.0392291000, 0.0569203000, 0.1042738000, 0.2355166000, 0.5824426000, 1.4897666000", \ - "0.0323428000, 0.0394851000, 0.0568264000, 0.1042177000, 0.2355526000, 0.5831135000, 1.4941209000", \ - "0.0322807000, 0.0395848000, 0.0571566000, 0.1044567000, 0.2357277000, 0.5832235000, 1.4935695000", \ - "0.0352902000, 0.0422961000, 0.0592910000, 0.1054753000, 0.2352206000, 0.5830439000, 1.4909113000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__fa_2") { - leakage_power () { - value : 0.0064822000; - when : "!A&!B&CIN"; - } - leakage_power () { - value : 0.0097044000; - when : "!A&!B&!CIN"; - } - leakage_power () { - value : 0.0063809000; - when : "!A&B&CIN"; - } - leakage_power () { - value : 0.0065570000; - when : "!A&B&!CIN"; - } - leakage_power () { - value : 0.0063478000; - when : "A&!B&CIN"; - } - leakage_power () { - value : 0.0067062000; - when : "A&!B&!CIN"; - } - leakage_power () { - value : 0.0029148000; - when : "A&B&CIN"; - } - leakage_power () { - value : 0.0067163000; - when : "A&B&!CIN"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__fa"; - cell_leakage_power : 0.0064761880; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0077040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0074450000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0079620000; - } - pin ("B") { - capacitance : 0.0069540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0067320000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0071760000; - } - pin ("CIN") { - capacitance : 0.0050900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0050200000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051590000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B) | (A&CIN) | (B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0028483000, 0.0074906000, 0.0168336000, 0.0262464000, 0.0114966000, -0.081535400, -0.385852400", \ - "0.0028424000, 0.0074585000, 0.0167853000, 0.0261922000, 0.0113760000, -0.081631100, -0.385983700", \ - "0.0028245000, 0.0074207000, 0.0166945000, 0.0260037000, 0.0110855000, -0.081948800, -0.386274900", \ - "0.0028108000, 0.0073729000, 0.0165636000, 0.0258112000, 0.0108874000, -0.082246100, -0.386596400", \ - "0.0027907000, 0.0073340000, 0.0164589000, 0.0255734000, 0.0104007000, -0.082723700, -0.387024900", \ - "0.0027845000, 0.0073047000, 0.0163842000, 0.0254924000, 0.0102571000, -0.082790700, -0.387069900", \ - "0.0028071000, 0.0073676000, 0.0164640000, 0.0257279000, 0.0103347000, -0.082622500, -0.386973600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0001951000, 0.0006932000, 0.0028263000, 0.0120467000, 0.0469756000, 0.1514299000, 0.4577216000", \ - "0.0001927000, 0.0006868000, 0.0028267000, 0.0119479000, 0.0469151000, 0.1514157000, 0.4567347000", \ - "0.0001863000, 0.0006664000, 0.0027529000, 0.0118632000, 0.0467811000, 0.1512727000, 0.4551846000", \ - "0.0001713000, 0.0006331000, 0.0026716000, 0.0117773000, 0.0465882000, 0.1511368000, 0.4578002000", \ - "0.0001633000, 0.0006010000, 0.0026100000, 0.0114800000, 0.0461614000, 0.1505830000, 0.4567747000", \ - "0.0001448000, 0.0005503000, 0.0024508000, 0.0112169000, 0.0456600000, 0.1501459000, 0.4577932000", \ - "0.0002596000, 0.0008663000, 0.0031903000, 0.0125958000, 0.0461986000, 0.1501591000, 0.4557986000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0027820000, 0.0073030000, 0.0163822000, 0.0254377000, 0.0102499000, -0.082818000, -0.387220700", \ - "0.0027774000, 0.0072894000, 0.0163462000, 0.0253748000, 0.0102056000, -0.082892300, -0.387076000", \ - "0.0027728000, 0.0072791000, 0.0163271000, 0.0253295000, 0.0100834000, -0.082995400, -0.387271400", \ - "0.0027591000, 0.0072429000, 0.0162221000, 0.0251197000, 0.0098169000, -0.083310200, -0.387533200", \ - "0.0027375000, 0.0071808000, 0.0160791000, 0.0248431000, 0.0093964000, -0.083695300, -0.387991300", \ - "0.0027364000, 0.0071766000, 0.0160730000, 0.0250668000, 0.0095978000, -0.083600900, -0.387858600", \ - "0.0028051000, 0.0073384000, 0.0163933000, 0.0252323000, 0.0095901000, -0.083467600, -0.387744000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0001737000, 0.0006313000, 0.0026838000, 0.0117662000, 0.0467517000, 0.1512498000, 0.4580320000", \ - "0.0001752000, 0.0006343000, 0.0026972000, 0.0117962000, 0.0467186000, 0.1512116000, 0.4578669000", \ - "0.0001693000, 0.0006215000, 0.0026649000, 0.0117579000, 0.0466543000, 0.1511701000, 0.4567726000", \ - "0.0001565000, 0.0005907000, 0.0025867000, 0.0115629000, 0.0463540000, 0.1509209000, 0.4559671000", \ - "0.0001444000, 0.0005539000, 0.0024904000, 0.0113327000, 0.0459644000, 0.1504668000, 0.4562359000", \ - "0.0001297000, 0.0005053000, 0.0023671000, 0.0110559000, 0.0455872000, 0.1499946000, 0.4566532000", \ - "0.0002417000, 0.0008000000, 0.0030377000, 0.0125073000, 0.0461315000, 0.1500958000, 0.4550545000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0026526000, 0.0069503000, 0.0155398000, 0.0238826000, 0.0082017000, -0.084834900, -0.389038800", \ - "0.0026528000, 0.0069591000, 0.0155705000, 0.0238978000, 0.0081835000, -0.084845900, -0.389026600", \ - "0.0026456000, 0.0069408000, 0.0155085000, 0.0237881000, 0.0080126000, -0.085035300, -0.389208900", \ - "0.0026296000, 0.0068951000, 0.0154013000, 0.0236669000, 0.0078562000, -0.085216300, -0.389427400", \ - "0.0026158000, 0.0068488000, 0.0153274000, 0.0233985000, 0.0074734000, -0.085672000, -0.389841300", \ - "0.0026126000, 0.0068464000, 0.0152665000, 0.0232804000, 0.0072283000, -0.086023400, -0.390112200", \ - "0.0026869000, 0.0070315000, 0.0156488000, 0.0237733000, 0.0074648000, -0.085824400, -0.389934300"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014463750, 0.0041840030, 0.0121032800, 0.0350117600, 0.1012803000, 0.2929786000"); - values("0.0003334000, 0.0010651000, 0.0037299000, 0.0138095000, 0.0497298000, 0.1550502000, 0.4602415000", \ - "0.0003340000, 0.0010644000, 0.0037347000, 0.0138314000, 0.0497470000, 0.1549094000, 0.4605387000", \ - "0.0003329000, 0.0010628000, 0.0037332000, 0.0137723000, 0.0496742000, 0.1549550000, 0.4607699000", \ - "0.0003240000, 0.0010403000, 0.0036712000, 0.0136522000, 0.0495229000, 0.1546241000, 0.4617112000", \ - "0.0003163000, 0.0010199000, 0.0035934000, 0.0134352000, 0.0491001000, 0.1541469000, 0.4599515000", \ - "0.0003107000, 0.0009956000, 0.0035093000, 0.0132793000, 0.0486797000, 0.1537073000, 0.4597138000", \ - "0.0004328000, 0.0013135000, 0.0042433000, 0.0145836000, 0.0492084000, 0.1537097000, 0.4603890000"); - } - } - max_capacitance : 0.2929790000; - max_transition : 1.4973290000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.3338938000, 0.3429049000, 0.3627202000, 0.4013205000, 0.4725109000, 0.6138429000, 0.9439642000", \ - "0.3377826000, 0.3465959000, 0.3666735000, 0.4053072000, 0.4765040000, 0.6178393000, 0.9479770000", \ - "0.3480542000, 0.3571276000, 0.3770081000, 0.4157131000, 0.4870516000, 0.6283816000, 0.9586995000", \ - "0.3717982000, 0.3806268000, 0.4007410000, 0.4394153000, 0.5103103000, 0.6518042000, 0.9820532000", \ - "0.4299085000, 0.4389289000, 0.4587483000, 0.4972407000, 0.5684105000, 0.7099480000, 1.0403356000", \ - "0.5686161000, 0.5776459000, 0.5976493000, 0.6360275000, 0.7072440000, 0.8490190000, 1.1793824000", \ - "0.8272393000, 0.8376251000, 0.8609810000, 0.9063256000, 0.9853188000, 1.1352573000, 1.4699265000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.1513365000, 0.1586499000, 0.1756522000, 0.2125240000, 0.2991948000, 0.5354896000, 1.2112424000", \ - "0.1559275000, 0.1633366000, 0.1801656000, 0.2168930000, 0.3036458000, 0.5399883000, 1.2156440000", \ - "0.1654800000, 0.1728396000, 0.1896690000, 0.2265472000, 0.3132648000, 0.5496328000, 1.2250390000", \ - "0.1866102000, 0.1939883000, 0.2109023000, 0.2477673000, 0.3343903000, 0.5708148000, 1.2460695000", \ - "0.2323118000, 0.2398361000, 0.2569835000, 0.2940848000, 0.3807478000, 0.6172940000, 1.2932569000", \ - "0.3062651000, 0.3150586000, 0.3344018000, 0.3741544000, 0.4634115000, 0.7011710000, 1.3763952000", \ - "0.3967819000, 0.4077975000, 0.4323323000, 0.4785562000, 0.5724121000, 0.8109797000, 1.4885895000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0478259000, 0.0533904000, 0.0651551000, 0.0894783000, 0.1430685000, 0.2806954000, 0.6861873000", \ - "0.0477631000, 0.0532638000, 0.0649254000, 0.0893048000, 0.1430858000, 0.2806923000, 0.6860201000", \ - "0.0477306000, 0.0532161000, 0.0649225000, 0.0894263000, 0.1429331000, 0.2812970000, 0.6844339000", \ - "0.0478814000, 0.0528720000, 0.0649294000, 0.0893255000, 0.1434284000, 0.2810343000, 0.6867242000", \ - "0.0477095000, 0.0530753000, 0.0650155000, 0.0897001000, 0.1430030000, 0.2808896000, 0.6864733000", \ - "0.0494187000, 0.0544662000, 0.0659576000, 0.0910164000, 0.1439236000, 0.2809732000, 0.6861919000", \ - "0.0622199000, 0.0675071000, 0.0803599000, 0.1068851000, 0.1601786000, 0.2940896000, 0.6907690000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0293723000, 0.0353549000, 0.0495087000, 0.0864927000, 0.1958758000, 0.5286399000, 1.4920207000", \ - "0.0293148000, 0.0351029000, 0.0492566000, 0.0865307000, 0.1959025000, 0.5274793000, 1.4937559000", \ - "0.0295071000, 0.0351888000, 0.0495431000, 0.0863866000, 0.1958990000, 0.5284193000, 1.4907302000", \ - "0.0294664000, 0.0352173000, 0.0491414000, 0.0865536000, 0.1958137000, 0.5292460000, 1.4921091000", \ - "0.0308761000, 0.0363284000, 0.0502127000, 0.0871454000, 0.1959884000, 0.5282151000, 1.4915252000", \ - "0.0371414000, 0.0426279000, 0.0572897000, 0.0935160000, 0.2002033000, 0.5306341000, 1.4947490000", \ - "0.0504486000, 0.0570036000, 0.0728635000, 0.1083345000, 0.2078454000, 0.5320654000, 1.4945923000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.3065588000, 0.3155986000, 0.3355458000, 0.3740872000, 0.4454030000, 0.5869809000, 0.9174744000", \ - "0.3104574000, 0.3194645000, 0.3394517000, 0.3777553000, 0.4490203000, 0.5907078000, 0.9212473000", \ - "0.3203413000, 0.3291408000, 0.3492164000, 0.3878634000, 0.4591745000, 0.6008183000, 0.9310886000", \ - "0.3455358000, 0.3545248000, 0.3743915000, 0.4127407000, 0.4841109000, 0.6257698000, 0.9562848000", \ - "0.4099947000, 0.4189692000, 0.4387844000, 0.4774701000, 0.5485925000, 0.6903673000, 1.0207438000", \ - "0.5680698000, 0.5770453000, 0.5969529000, 0.6352036000, 0.7064533000, 0.8481862000, 1.1784240000", \ - "0.8637093000, 0.8748082000, 0.8998607000, 0.9467392000, 1.0278844000, 1.1775422000, 1.5111932000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.1433831000, 0.1515674000, 0.1699016000, 0.2091918000, 0.2984780000, 0.5352667000, 1.2112791000", \ - "0.1483126000, 0.1564997000, 0.1748474000, 0.2141522000, 0.3034148000, 0.5401922000, 1.2161719000", \ - "0.1582928000, 0.1663849000, 0.1849016000, 0.2241798000, 0.3134238000, 0.5502269000, 1.2263752000", \ - "0.1794649000, 0.1876033000, 0.2059882000, 0.2452672000, 0.3344603000, 0.5714051000, 1.2475144000", \ - "0.2238546000, 0.2322649000, 0.2511662000, 0.2908828000, 0.3802736000, 0.6172554000, 1.2926248000", \ - "0.2961866000, 0.3053063000, 0.3259187000, 0.3684240000, 0.4611312000, 0.6999703000, 1.3759629000", \ - "0.3868795000, 0.3984450000, 0.4236743000, 0.4720961000, 0.5705613000, 0.8112511000, 1.4891168000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0475178000, 0.0530841000, 0.0652823000, 0.0895646000, 0.1430493000, 0.2805577000, 0.6866094000", \ - "0.0477393000, 0.0532549000, 0.0649477000, 0.0903654000, 0.1439074000, 0.2809326000, 0.6861235000", \ - "0.0476593000, 0.0534143000, 0.0648063000, 0.0894311000, 0.1432899000, 0.2805410000, 0.6865761000", \ - "0.0474759000, 0.0528556000, 0.0646256000, 0.0895342000, 0.1430162000, 0.2804811000, 0.6865726000", \ - "0.0478772000, 0.0533996000, 0.0650424000, 0.0897657000, 0.1431947000, 0.2806717000, 0.6862609000", \ - "0.0488563000, 0.0538587000, 0.0663195000, 0.0911793000, 0.1441079000, 0.2812172000, 0.6866207000", \ - "0.0706376000, 0.0759487000, 0.0893589000, 0.1145611000, 0.1641869000, 0.2947403000, 0.6904106000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0324386000, 0.0384987000, 0.0532928000, 0.0909159000, 0.1990152000, 0.5300246000, 1.4952198000", \ - "0.0324372000, 0.0385441000, 0.0533319000, 0.0910177000, 0.1989760000, 0.5301312000, 1.4948938000", \ - "0.0326952000, 0.0384058000, 0.0532477000, 0.0908809000, 0.1986636000, 0.5300250000, 1.4956524000", \ - "0.0322664000, 0.0382472000, 0.0530663000, 0.0907947000, 0.1990127000, 0.5297263000, 1.4956640000", \ - "0.0338754000, 0.0398838000, 0.0548596000, 0.0920200000, 0.1993246000, 0.5298235000, 1.4936347000", \ - "0.0388710000, 0.0451642000, 0.0610656000, 0.0993505000, 0.2050184000, 0.5307502000, 1.4951667000", \ - "0.0525808000, 0.0601639000, 0.0766697000, 0.1132805000, 0.2143328000, 0.5358133000, 1.4973286000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.2877394000, 0.2965838000, 0.3162632000, 0.3544409000, 0.4256055000, 0.5675326000, 0.8983706000", \ - "0.2918317000, 0.3006855000, 0.3202809000, 0.3586051000, 0.4298057000, 0.5716438000, 0.9024744000", \ - "0.3017655000, 0.3106312000, 0.3300219000, 0.3684671000, 0.4397016000, 0.5814900000, 0.9123575000", \ - "0.3276861000, 0.3364923000, 0.3557470000, 0.3939952000, 0.4654331000, 0.6073589000, 0.9382044000", \ - "0.3933375000, 0.4021448000, 0.4215794000, 0.4599064000, 0.5308987000, 0.6728552000, 1.0034916000", \ - "0.5519306000, 0.5607122000, 0.5801205000, 0.6183662000, 0.6895051000, 0.8315615000, 1.1623533000", \ - "0.8410555000, 0.8520145000, 0.8768806000, 0.9238678000, 1.0048528000, 1.1553872000, 1.4898213000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.1386848000, 0.1468950000, 0.1654122000, 0.2048554000, 0.2941545000, 0.5309995000, 1.2071653000", \ - "0.1430873000, 0.1512930000, 0.1698478000, 0.2092891000, 0.2985911000, 0.5354188000, 1.2116073000", \ - "0.1532458000, 0.1614255000, 0.1800103000, 0.2193640000, 0.3086252000, 0.5455891000, 1.2214674000", \ - "0.1772500000, 0.1854577000, 0.2039655000, 0.2433508000, 0.3326062000, 0.5695346000, 1.2456665000", \ - "0.2307586000, 0.2391358000, 0.2578506000, 0.2973855000, 0.3867032000, 0.6236751000, 1.3000564000", \ - "0.3069184000, 0.3172188000, 0.3395159000, 0.3830808000, 0.4750850000, 0.7132008000, 1.3894039000", \ - "0.3881071000, 0.4012787000, 0.4299413000, 0.4846905000, 0.5835407000, 0.8232032000, 1.5000139000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0461524000, 0.0510963000, 0.0637298000, 0.0878997000, 0.1418612000, 0.2807339000, 0.6858361000", \ - "0.0460928000, 0.0517396000, 0.0629299000, 0.0879592000, 0.1420389000, 0.2807129000, 0.6862170000", \ - "0.0458739000, 0.0511390000, 0.0629029000, 0.0878208000, 0.1418325000, 0.2807204000, 0.6864839000", \ - "0.0459424000, 0.0514032000, 0.0629524000, 0.0885196000, 0.1420790000, 0.2808227000, 0.6861440000", \ - "0.0458897000, 0.0511502000, 0.0631064000, 0.0881774000, 0.1420524000, 0.2806937000, 0.6858799000", \ - "0.0473380000, 0.0524218000, 0.0649428000, 0.0886474000, 0.1425118000, 0.2809121000, 0.6850672000", \ - "0.0693434000, 0.0749826000, 0.0886161000, 0.1138039000, 0.1645485000, 0.2951614000, 0.6900401000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014463800, 0.0041840000, 0.0121033000, 0.0350118000, 0.1012800000, 0.2929790000"); - values("0.0330467000, 0.0390827000, 0.0536468000, 0.0910614000, 0.1991245000, 0.5292950000, 1.4957042000", \ - "0.0333134000, 0.0389631000, 0.0535510000, 0.0910661000, 0.1987577000, 0.5300381000, 1.4956845000", \ - "0.0331139000, 0.0389251000, 0.0534328000, 0.0910025000, 0.1990937000, 0.5296210000, 1.4956395000", \ - "0.0330404000, 0.0390761000, 0.0536370000, 0.0910578000, 0.1991428000, 0.5301099000, 1.4953127000", \ - "0.0352755000, 0.0408351000, 0.0550727000, 0.0920958000, 0.1994772000, 0.5301503000, 1.4956318000", \ - "0.0467082000, 0.0523903000, 0.0660789000, 0.1012855000, 0.2045237000, 0.5300659000, 1.4943587000", \ - "0.0642353000, 0.0720895000, 0.0892635000, 0.1242588000, 0.2165852000, 0.5349357000, 1.4955298000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B&!CIN) | (!A&B&!CIN) | (!A&!B&CIN) | (A&B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0016238000, 0.0041903000, 0.0090384000, 0.0120396000, -0.007754800, -0.102638900, -0.402979200", \ - "0.0016163000, 0.0041693000, 0.0089871000, 0.0119424000, -0.007852700, -0.102803400, -0.403103700", \ - "0.0016106000, 0.0041498000, 0.0089461000, 0.0118557000, -0.008000400, -0.102967200, -0.403263100", \ - "0.0016021000, 0.0041324000, 0.0088982000, 0.0117675000, -0.008156900, -0.103120600, -0.403460400", \ - "0.0015793000, 0.0040694000, 0.0087522000, 0.0114777000, -0.008601300, -0.103643800, -0.404036500", \ - "0.0015579000, 0.0040111000, 0.0086056000, 0.0112327000, -0.008950700, -0.104110100, -0.404548700", \ - "0.0017510000, 0.0045239000, 0.0097141000, 0.0125933000, -0.008214700, -0.104076800, -0.404507400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0012893000, 0.0036334000, 0.0099658000, 0.0262426000, 0.0666041000, 0.1737660000, 0.4770308000", \ - "0.0012855000, 0.0036211000, 0.0099375000, 0.0261889000, 0.0664553000, 0.1741422000, 0.4761549000", \ - "0.0012727000, 0.0035807000, 0.0098405000, 0.0260008000, 0.0661104000, 0.1731528000, 0.4783102000", \ - "0.0012522000, 0.0035338000, 0.0097418000, 0.0258069000, 0.0658348000, 0.1727968000, 0.4759268000", \ - "0.0012332000, 0.0034825000, 0.0096211000, 0.0255698000, 0.0654616000, 0.1723623000, 0.4754397000", \ - "0.0012305000, 0.0034704000, 0.0095876000, 0.0254896000, 0.0654649000, 0.1722607000, 0.4753359000", \ - "0.0012182000, 0.0034460000, 0.0095597000, 0.0257241000, 0.0658531000, 0.1729422000, 0.4752998000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0016048000, 0.0041377000, 0.0088949000, 0.0117584000, -0.008081800, -0.103005000, -0.403540300", \ - "0.0016069000, 0.0041453000, 0.0089099000, 0.0117912000, -0.008033000, -0.102987000, -0.403385600", \ - "0.0016021000, 0.0041288000, 0.0088783000, 0.0117441000, -0.008137000, -0.103074200, -0.403369600", \ - "0.0015879000, 0.0040917000, 0.0087997000, 0.0115539000, -0.008399500, -0.103428000, -0.403722300", \ - "0.0015693000, 0.0040385000, 0.0086725000, 0.0113251000, -0.008749500, -0.103843800, -0.404179200", \ - "0.0015441000, 0.0039735000, 0.0085059000, 0.0110458000, -0.009191400, -0.104365100, -0.404773700", \ - "0.0017477000, 0.0045121000, 0.0096775000, 0.0125071000, -0.008360900, -0.104236700, -0.404607100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0012200000, 0.0034504000, 0.0095518000, 0.0254322000, 0.0652745000, 0.1721104000, 0.4761892000", \ - "0.0012194000, 0.0034444000, 0.0095211000, 0.0253691000, 0.0652911000, 0.1721087000, 0.4752599000", \ - "0.0012123000, 0.0034266000, 0.0094933000, 0.0253263000, 0.0651112000, 0.1719348000, 0.4760858000", \ - "0.0011952000, 0.0033814000, 0.0093862000, 0.0251144000, 0.0648384000, 0.1715719000, 0.4759378000", \ - "0.0011758000, 0.0033267000, 0.0092436000, 0.0248394000, 0.0644311000, 0.1711040000, 0.4741205000", \ - "0.0011913000, 0.0033708000, 0.0093591000, 0.0250641000, 0.0647387000, 0.1713721000, 0.4739888000", \ - "0.0011850000, 0.0033537000, 0.0093263000, 0.0252143000, 0.0650010000, 0.1717939000, 0.4759535000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0017672000, 0.0045747000, 0.0099470000, 0.0138019000, -0.005063400, -0.099440500, -0.399576700", \ - "0.0017678000, 0.0045733000, 0.0099475000, 0.0138193000, -0.005068600, -0.099422800, -0.399513100", \ - "0.0017642000, 0.0045663000, 0.0099363000, 0.0137634000, -0.005124100, -0.099523000, -0.399619800", \ - "0.0017548000, 0.0045409000, 0.0098673000, 0.0136461000, -0.005299200, -0.099729200, -0.399858100", \ - "0.0017375000, 0.0044941000, 0.0097537000, 0.0134281000, -0.005632200, -0.100125300, -0.400270800", \ - "0.0017222000, 0.0044525000, 0.0096640000, 0.0132445000, -0.005867000, -0.100402900, -0.400590200", \ - "0.0019127000, 0.0049542000, 0.0107343000, 0.0145833000, -0.005248500, -0.100297600, -0.400328200"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("0.0011015000, 0.0031348000, 0.0087624000, 0.0238786000, 0.0630140000, 0.1694109000, 0.4737142000", \ - "0.0011034000, 0.0031312000, 0.0087609000, 0.0238955000, 0.0630138000, 0.1693378000, 0.4720395000", \ - "0.0010943000, 0.0031065000, 0.0087148000, 0.0237855000, 0.0628984000, 0.1693056000, 0.4722488000", \ - "0.0010837000, 0.0030756000, 0.0086450000, 0.0236634000, 0.0626458000, 0.1690378000, 0.4719253000", \ - "0.0010650000, 0.0030289000, 0.0085190000, 0.0234254000, 0.0623442000, 0.1685595000, 0.4709245000", \ - "0.0010525000, 0.0029962000, 0.0084514000, 0.0232676000, 0.0621205000, 0.1683284000, 0.4729260000", \ - "0.0010708000, 0.0030414000, 0.0085862000, 0.0237613000, 0.0628462000, 0.1692341000, 0.4712840000"); - } - } - max_capacitance : 0.2884010000; - max_transition : 1.5035440000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4141372000, 0.4234336000, 0.4441449000, 0.4847662000, 0.5592601000, 0.7027552000, 1.0294622000", \ - "0.4179037000, 0.4271631000, 0.4478773000, 0.4884184000, 0.5630549000, 0.7067392000, 1.0333229000", \ - "0.4284967000, 0.4378087000, 0.4585372000, 0.4989739000, 0.5728907000, 0.7168701000, 1.0439473000", \ - "0.4527764000, 0.4621620000, 0.4828241000, 0.5233147000, 0.5979303000, 0.7416799000, 1.0683198000", \ - "0.5073776000, 0.5166532000, 0.5373330000, 0.5776941000, 0.6517716000, 0.7955938000, 1.1227089000", \ - "0.6270763000, 0.6362438000, 0.6570947000, 0.6974921000, 0.7718869000, 0.9160269000, 1.2430414000", \ - "0.8563502000, 0.8662230000, 0.8896769000, 0.9336145000, 1.0129013000, 1.1622704000, 1.4933309000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1623641000, 0.1700271000, 0.1876882000, 0.2256516000, 0.3133574000, 0.5470894000, 1.2183640000", \ - "0.1663564000, 0.1740358000, 0.1915507000, 0.2295530000, 0.3172449000, 0.5513582000, 1.2217969000", \ - "0.1742375000, 0.1818656000, 0.1993726000, 0.2374894000, 0.3250960000, 0.5600016000, 1.2294596000", \ - "0.1906052000, 0.1982670000, 0.2159457000, 0.2539720000, 0.3417684000, 0.5764322000, 1.2482184000", \ - "0.2258629000, 0.2336616000, 0.2514396000, 0.2896799000, 0.3775372000, 0.6118053000, 1.2832551000", \ - "0.2847861000, 0.2933367000, 0.3125899000, 0.3530659000, 0.4428776000, 0.6782649000, 1.3489101000", \ - "0.3585157000, 0.3688875000, 0.3917927000, 0.4361684000, 0.5302896000, 0.7662213000, 1.4364449000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0598099000, 0.0654940000, 0.0774794000, 0.1030276000, 0.1546862000, 0.2883055000, 0.6706835000", \ - "0.0603708000, 0.0655451000, 0.0769400000, 0.1014205000, 0.1549302000, 0.2884048000, 0.6683218000", \ - "0.0600834000, 0.0648805000, 0.0773923000, 0.1014399000, 0.1553869000, 0.2887082000, 0.6696793000", \ - "0.0598013000, 0.0655694000, 0.0769346000, 0.1013874000, 0.1548868000, 0.2884242000, 0.6683823000", \ - "0.0601926000, 0.0652509000, 0.0770332000, 0.1013886000, 0.1563494000, 0.2890564000, 0.6692564000", \ - "0.0599049000, 0.0650109000, 0.0770143000, 0.1016592000, 0.1552229000, 0.2884579000, 0.6695521000", \ - "0.0709247000, 0.0761130000, 0.0883867000, 0.1148523000, 0.1692990000, 0.2972784000, 0.6740967000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0331300000, 0.0390608000, 0.0539525000, 0.0920591000, 0.2012440000, 0.5320150000, 1.5008942000", \ - "0.0332613000, 0.0392067000, 0.0540810000, 0.0920491000, 0.2013886000, 0.5312895000, 1.5003817000", \ - "0.0333243000, 0.0393026000, 0.0542621000, 0.0920324000, 0.2015624000, 0.5308506000, 1.5001727000", \ - "0.0331829000, 0.0389982000, 0.0540268000, 0.0920107000, 0.2010524000, 0.5325111000, 1.5027708000", \ - "0.0341566000, 0.0400549000, 0.0546920000, 0.0927064000, 0.2012859000, 0.5318573000, 1.5009870000", \ - "0.0385324000, 0.0446413000, 0.0600021000, 0.0974284000, 0.2043128000, 0.5322426000, 1.5007652000", \ - "0.0498887000, 0.0567748000, 0.0724824000, 0.1100451000, 0.2111687000, 0.5351778000, 1.4992471000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3767284000, 0.3840806000, 0.4004426000, 0.4329401000, 0.4944162000, 0.6208016000, 0.9337759000", \ - "0.3811994000, 0.3885310000, 0.4049272000, 0.4373385000, 0.4988141000, 0.6252119000, 0.9386304000", \ - "0.3907753000, 0.3980818000, 0.4145461000, 0.4469366000, 0.5085310000, 0.6348495000, 0.9480643000", \ - "0.4115657000, 0.4189386000, 0.4352851000, 0.4678146000, 0.5291295000, 0.6555614000, 0.9688784000", \ - "0.4562054000, 0.4635354000, 0.4799844000, 0.5124665000, 0.5737618000, 0.7001991000, 1.0136455000", \ - "0.5375227000, 0.5447715000, 0.5610715000, 0.5936073000, 0.6550326000, 0.7814407000, 1.0945183000", \ - "0.6480162000, 0.6554070000, 0.6719525000, 0.7045388000, 0.7658360000, 0.8921111000, 1.2047318000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.5205433000, 0.5286986000, 0.5471549000, 0.5851248000, 0.6722642000, 0.9070906000, 1.5768234000", \ - "0.5245360000, 0.5326856000, 0.5511221000, 0.5890927000, 0.6762118000, 0.9110540000, 1.5805581000", \ - "0.5347959000, 0.5432007000, 0.5614795000, 0.5995490000, 0.6866145000, 0.9210575000, 1.5933121000", \ - "0.5586542000, 0.5669142000, 0.5852299000, 0.6232198000, 0.7103030000, 0.9451788000, 1.6147733000", \ - "0.6163315000, 0.6245935000, 0.6429045000, 0.6809130000, 0.7679610000, 1.0028512000, 1.6718615000", \ - "0.7544927000, 0.7628642000, 0.7810124000, 0.8191179000, 0.9063960000, 1.1409835000, 1.8127194000", \ - "1.0338995000, 1.0424923000, 1.0615887000, 1.1001837000, 1.1875283000, 1.4217969000, 2.0922435000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0413646000, 0.0458048000, 0.0553566000, 0.0772890000, 0.1252053000, 0.2556547000, 0.6500120000", \ - "0.0413916000, 0.0457793000, 0.0562370000, 0.0772903000, 0.1256948000, 0.2556216000, 0.6515833000", \ - "0.0416211000, 0.0458496000, 0.0555056000, 0.0769081000, 0.1255415000, 0.2552657000, 0.6504752000", \ - "0.0415036000, 0.0457912000, 0.0553895000, 0.0773726000, 0.1249721000, 0.2560054000, 0.6508830000", \ - "0.0418338000, 0.0459550000, 0.0555002000, 0.0766610000, 0.1246367000, 0.2550833000, 0.6519970000", \ - "0.0413787000, 0.0457168000, 0.0559730000, 0.0766895000, 0.1260798000, 0.2561835000, 0.6493676000", \ - "0.0423449000, 0.0465634000, 0.0561274000, 0.0773145000, 0.1249024000, 0.2549251000, 0.6458915000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0383892000, 0.0437044000, 0.0567033000, 0.0921156000, 0.1995890000, 0.5295923000, 1.4961616000", \ - "0.0384004000, 0.0436831000, 0.0567005000, 0.0921092000, 0.1996354000, 0.5295919000, 1.4928069000", \ - "0.0385356000, 0.0435093000, 0.0565639000, 0.0921761000, 0.1997874000, 0.5287408000, 1.4962444000", \ - "0.0382651000, 0.0435268000, 0.0566098000, 0.0921546000, 0.1996896000, 0.5295797000, 1.4964751000", \ - "0.0383491000, 0.0435300000, 0.0566313000, 0.0921721000, 0.1997705000, 0.5293962000, 1.4970900000", \ - "0.0384576000, 0.0435356000, 0.0568930000, 0.0921338000, 0.1995531000, 0.5289688000, 1.4936143000", \ - "0.0410052000, 0.0463239000, 0.0586366000, 0.0937981000, 0.2001974000, 0.5293690000, 1.4969100000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3935728000, 0.4028973000, 0.4237282000, 0.4643015000, 0.5391567000, 0.6832221000, 1.0104524000", \ - "0.3972005000, 0.4064468000, 0.4274773000, 0.4681020000, 0.5427827000, 0.6867987000, 1.0140895000", \ - "0.4078444000, 0.4171241000, 0.4379065000, 0.4785374000, 0.5532225000, 0.6973346000, 1.0247275000", \ - "0.4329431000, 0.4423710000, 0.4630572000, 0.5035207000, 0.5785611000, 0.7226613000, 1.0500828000", \ - "0.4916169000, 0.5008524000, 0.5216728000, 0.5624552000, 0.6371371000, 0.7812211000, 1.1087803000", \ - "0.6293129000, 0.6385942000, 0.6593113000, 0.7006166000, 0.7750154000, 0.9194890000, 1.2474163000", \ - "0.8975999000, 0.9081078000, 0.9310200000, 0.9762392000, 1.0567551000, 1.2080784000, 1.5398172000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1556821000, 0.1632889000, 0.1809717000, 0.2191816000, 0.3070079000, 0.5424085000, 1.2123196000", \ - "0.1596765000, 0.1673468000, 0.1848500000, 0.2230049000, 0.3107988000, 0.5462004000, 1.2167576000", \ - "0.1683421000, 0.1760638000, 0.1936478000, 0.2318654000, 0.3197715000, 0.5551939000, 1.2286048000", \ - "0.1888054000, 0.1965625000, 0.2141632000, 0.2522931000, 0.3402048000, 0.5749284000, 1.2468537000", \ - "0.2338587000, 0.2416065000, 0.2592923000, 0.2977356000, 0.3858265000, 0.6210911000, 1.2935418000", \ - "0.3079158000, 0.3166104000, 0.3359255000, 0.3763519000, 0.4661025000, 0.7020887000, 1.3727673000", \ - "0.3960761000, 0.4068536000, 0.4305085000, 0.4766004000, 0.5696772000, 0.8049166000, 1.4764933000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0602100000, 0.0653934000, 0.0772959000, 0.1019205000, 0.1554959000, 0.2889341000, 0.6692960000", \ - "0.0603526000, 0.0656801000, 0.0778954000, 0.1016746000, 0.1548270000, 0.2886754000, 0.6711612000", \ - "0.0605840000, 0.0657598000, 0.0771178000, 0.1016810000, 0.1550966000, 0.2887732000, 0.6690058000", \ - "0.0603717000, 0.0657885000, 0.0777225000, 0.1022259000, 0.1550718000, 0.2889222000, 0.6714608000", \ - "0.0601514000, 0.0654009000, 0.0777091000, 0.1024587000, 0.1552980000, 0.2889896000, 0.6716025000", \ - "0.0608474000, 0.0659354000, 0.0780773000, 0.1023642000, 0.1557029000, 0.2886948000, 0.6699761000", \ - "0.0743950000, 0.0801568000, 0.0927523000, 0.1177928000, 0.1697440000, 0.2979396000, 0.6750152000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0332652000, 0.0395076000, 0.0541974000, 0.0921594000, 0.2018174000, 0.5317791000, 1.4999868000", \ - "0.0332931000, 0.0393636000, 0.0543276000, 0.0922075000, 0.2018445000, 0.5315208000, 1.5011409000", \ - "0.0332767000, 0.0394655000, 0.0540204000, 0.0922449000, 0.2016860000, 0.5319701000, 1.4998350000", \ - "0.0333691000, 0.0391160000, 0.0542428000, 0.0921110000, 0.2013158000, 0.5321583000, 1.5014696000", \ - "0.0342673000, 0.0401365000, 0.0549615000, 0.0928942000, 0.2016509000, 0.5330876000, 1.5035440000", \ - "0.0402976000, 0.0463658000, 0.0614154000, 0.0978349000, 0.2042458000, 0.5328319000, 1.4975331000", \ - "0.0542054000, 0.0609934000, 0.0761137000, 0.1113335000, 0.2117570000, 0.5349056000, 1.4991641000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3914076000, 0.3989144000, 0.4155711000, 0.4483030000, 0.5102159000, 0.6368886000, 0.9504170000", \ - "0.3971338000, 0.4046102000, 0.4212679000, 0.4540637000, 0.5159398000, 0.6427346000, 0.9563289000", \ - "0.4074014000, 0.4148753000, 0.4315833000, 0.4643430000, 0.5261898000, 0.6531443000, 0.9667113000", \ - "0.4273457000, 0.4348462000, 0.4515479000, 0.4842331000, 0.5462355000, 0.6729599000, 0.9866282000", \ - "0.4688184000, 0.4761829000, 0.4928737000, 0.5257039000, 0.5875687000, 0.7144405000, 1.0278316000", \ - "0.5467777000, 0.5542078000, 0.5707564000, 0.6035120000, 0.6653321000, 0.7920906000, 1.1053294000", \ - "0.6557896000, 0.6631758000, 0.6798014000, 0.7123802000, 0.7740774000, 0.9004010000, 1.2133941000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4914277000, 0.4995131000, 0.5178127000, 0.5559060000, 0.6431036000, 0.8772187000, 1.5487703000", \ - "0.4951136000, 0.5033693000, 0.5215464000, 0.5596316000, 0.6468754000, 0.8815692000, 1.5530525000", \ - "0.5050209000, 0.5131638000, 0.5314865000, 0.5695309000, 0.6566039000, 0.8909298000, 1.5623177000", \ - "0.5300049000, 0.5380787000, 0.5563725000, 0.5944696000, 0.6816465000, 0.9159284000, 1.5871010000", \ - "0.5943402000, 0.6026523000, 0.6208236000, 0.6588829000, 0.7459846000, 0.9808852000, 1.6500317000", \ - "0.7514856000, 0.7596529000, 0.7780286000, 0.8161304000, 0.9032991000, 1.1378616000, 1.8075861000", \ - "1.0754393000, 1.0840506000, 1.1030635000, 1.1419351000, 1.2292604000, 1.4636145000, 2.1342841000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0428214000, 0.0468822000, 0.0575077000, 0.0784932000, 0.1265974000, 0.2559274000, 0.6514340000", \ - "0.0428181000, 0.0472872000, 0.0577091000, 0.0785728000, 0.1265217000, 0.2557508000, 0.6515343000", \ - "0.0428597000, 0.0472293000, 0.0566591000, 0.0776086000, 0.1267436000, 0.2563243000, 0.6514824000", \ - "0.0427847000, 0.0469146000, 0.0573930000, 0.0785080000, 0.1267005000, 0.2561241000, 0.6518539000", \ - "0.0428816000, 0.0474482000, 0.0568576000, 0.0786732000, 0.1272229000, 0.2560022000, 0.6507995000", \ - "0.0426985000, 0.0468790000, 0.0564747000, 0.0775319000, 0.1269656000, 0.2565824000, 0.6501353000", \ - "0.0426611000, 0.0472363000, 0.0567239000, 0.0784613000, 0.1261770000, 0.2553963000, 0.6472529000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0378964000, 0.0431161000, 0.0564742000, 0.0920286000, 0.1995199000, 0.5295868000, 1.4939671000", \ - "0.0380827000, 0.0430499000, 0.0566094000, 0.0919545000, 0.1992982000, 0.5292597000, 1.4936865000", \ - "0.0378303000, 0.0431782000, 0.0563920000, 0.0921553000, 0.1997819000, 0.5295406000, 1.4929292000", \ - "0.0378922000, 0.0430977000, 0.0564940000, 0.0920391000, 0.1993590000, 0.5294228000, 1.4927982000", \ - "0.0379767000, 0.0431254000, 0.0566104000, 0.0920341000, 0.1997734000, 0.5293448000, 1.4969322000", \ - "0.0379757000, 0.0433820000, 0.0565358000, 0.0921678000, 0.1993887000, 0.5285538000, 1.4971688000", \ - "0.0410041000, 0.0460190000, 0.0588536000, 0.0938821000, 0.2003898000, 0.5295286000, 1.4963811000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3717646000, 0.3810061000, 0.4019706000, 0.4425741000, 0.5171937000, 0.6610811000, 0.9882980000", \ - "0.3739638000, 0.3832987000, 0.4040748000, 0.4445067000, 0.5186293000, 0.6628382000, 0.9902582000", \ - "0.3798525000, 0.3887800000, 0.4096969000, 0.4508106000, 0.5244306000, 0.6687914000, 0.9962958000", \ - "0.3996204000, 0.4090717000, 0.4298852000, 0.4698162000, 0.5448222000, 0.6889489000, 1.0159281000", \ - "0.4580234000, 0.4672732000, 0.4880182000, 0.5285478000, 0.6028917000, 0.7468542000, 1.0745705000", \ - "0.6074987000, 0.6168188000, 0.6372976000, 0.6770492000, 0.7520035000, 0.8964287000, 1.2234472000", \ - "0.9076819000, 0.9184397000, 0.9423797000, 0.9885307000, 1.0681450000, 1.2163531000, 1.5462867000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.1552180000, 0.1628881000, 0.1804181000, 0.2184431000, 0.3062176000, 0.5414176000, 1.2121913000", \ - "0.1594137000, 0.1670375000, 0.1846661000, 0.2228109000, 0.3105717000, 0.5457383000, 1.2189277000", \ - "0.1688674000, 0.1765214000, 0.1941018000, 0.2322472000, 0.3199821000, 0.5552963000, 1.2250596000", \ - "0.1903711000, 0.1981598000, 0.2157540000, 0.2538002000, 0.3416165000, 0.5759380000, 1.2476735000", \ - "0.2417104000, 0.2493863000, 0.2666856000, 0.3052361000, 0.3929546000, 0.6275985000, 1.2990360000", \ - "0.3193442000, 0.3281624000, 0.3476678000, 0.3874247000, 0.4768276000, 0.7120014000, 1.3830600000", \ - "0.4023753000, 0.4136530000, 0.4379138000, 0.4847233000, 0.5765983000, 0.8124849000, 1.4819312000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0600891000, 0.0654050000, 0.0776911000, 0.1032423000, 0.1547315000, 0.2883600000, 0.6708930000", \ - "0.0600881000, 0.0648874000, 0.0773942000, 0.1014310000, 0.1572679000, 0.2885958000, 0.6696266000", \ - "0.0600973000, 0.0651886000, 0.0768236000, 0.1014245000, 0.1561932000, 0.2886921000, 0.6694904000", \ - "0.0602451000, 0.0652415000, 0.0773462000, 0.1010841000, 0.1553102000, 0.2885168000, 0.6690107000", \ - "0.0600418000, 0.0650451000, 0.0772119000, 0.1018027000, 0.1566758000, 0.2885127000, 0.6693999000", \ - "0.0598588000, 0.0648041000, 0.0772119000, 0.1036505000, 0.1564652000, 0.2878002000, 0.6683366000", \ - "0.0805910000, 0.0853855000, 0.0977571000, 0.1210751000, 0.1708319000, 0.2967452000, 0.6734162000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0332632000, 0.0392924000, 0.0541054000, 0.0921339000, 0.2016073000, 0.5316061000, 1.5011580000", \ - "0.0331902000, 0.0394771000, 0.0541249000, 0.0920468000, 0.2014817000, 0.5316545000, 1.4997844000", \ - "0.0331834000, 0.0390523000, 0.0541569000, 0.0920096000, 0.2015413000, 0.5309418000, 1.4994697000", \ - "0.0331953000, 0.0390702000, 0.0540662000, 0.0918759000, 0.2010191000, 0.5320882000, 1.5010209000", \ - "0.0341322000, 0.0399161000, 0.0549000000, 0.0927871000, 0.2016377000, 0.5314684000, 1.5005168000", \ - "0.0421585000, 0.0476400000, 0.0617758000, 0.0987295000, 0.2054148000, 0.5327097000, 1.4990178000", \ - "0.0589752000, 0.0659152000, 0.0805135000, 0.1138219000, 0.2131951000, 0.5354053000, 1.4982182000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3874264000, 0.3949182000, 0.4115925000, 0.4443683000, 0.5063110000, 0.6330785000, 0.9467168000", \ - "0.3919084000, 0.3993869000, 0.4161252000, 0.4488711000, 0.5107181000, 0.6376476000, 0.9511758000", \ - "0.4021184000, 0.4096098000, 0.4263255000, 0.4590243000, 0.5210428000, 0.6477279000, 0.9613289000", \ - "0.4248595000, 0.4323534000, 0.4490101000, 0.4817595000, 0.5436872000, 0.6704611000, 0.9841048000", \ - "0.4747991000, 0.4822934000, 0.4989443000, 0.5317005000, 0.5936646000, 0.7204022000, 1.0340461000", \ - "0.5587080000, 0.5661504000, 0.5829939000, 0.6159276000, 0.6777472000, 0.8046498000, 1.1180868000", \ - "0.6587100000, 0.6659822000, 0.6824696000, 0.7150264000, 0.7769137000, 0.9043345000, 1.2196099000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4838137000, 0.4912062000, 0.5082950000, 0.5448945000, 0.6308946000, 0.8654409000, 1.5368573000", \ - "0.4877854000, 0.4952926000, 0.5121678000, 0.5488278000, 0.6349533000, 0.8697766000, 1.5393961000", \ - "0.4977413000, 0.5051817000, 0.5221373000, 0.5586580000, 0.6447853000, 0.8796092000, 1.5494231000", \ - "0.5236225000, 0.5310463000, 0.5477913000, 0.5844367000, 0.6705319000, 0.9056324000, 1.5756465000", \ - "0.5886454000, 0.5961890000, 0.6130434000, 0.6497526000, 0.7358934000, 0.9706507000, 1.6419507000", \ - "0.7451966000, 0.7527525000, 0.7698052000, 0.8064189000, 0.8925651000, 1.1266436000, 1.7988314000", \ - "1.0612851000, 1.0690934000, 1.0868433000, 1.1241283000, 1.2104098000, 1.4448560000, 2.1159914000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0428739000, 0.0473857000, 0.0576589000, 0.0786181000, 0.1266905000, 0.2560625000, 0.6517143000", \ - "0.0429204000, 0.0472491000, 0.0567267000, 0.0776755000, 0.1268264000, 0.2564137000, 0.6514926000", \ - "0.0427578000, 0.0469814000, 0.0572093000, 0.0783783000, 0.1266839000, 0.2561538000, 0.6515743000", \ - "0.0428831000, 0.0473902000, 0.0577130000, 0.0786415000, 0.1267036000, 0.2560547000, 0.6517403000", \ - "0.0429659000, 0.0474614000, 0.0578285000, 0.0786909000, 0.1267841000, 0.2561617000, 0.6517991000", \ - "0.0433893000, 0.0473031000, 0.0573769000, 0.0778601000, 0.1263082000, 0.2564330000, 0.6504681000", \ - "0.0422274000, 0.0465859000, 0.0567682000, 0.0784682000, 0.1268892000, 0.2574922000, 0.6499847000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0344701000, 0.0401133000, 0.0532100000, 0.0894596000, 0.1986036000, 0.5298243000, 1.4936373000", \ - "0.0345033000, 0.0397989000, 0.0534214000, 0.0893600000, 0.1985102000, 0.5298365000, 1.4974639000", \ - "0.0345220000, 0.0399371000, 0.0533315000, 0.0893607000, 0.1983694000, 0.5299128000, 1.4969924000", \ - "0.0344607000, 0.0399226000, 0.0532644000, 0.0893488000, 0.1986024000, 0.5299365000, 1.4964930000", \ - "0.0345611000, 0.0398109000, 0.0534213000, 0.0893566000, 0.1983238000, 0.5298954000, 1.4957886000", \ - "0.0349959000, 0.0398256000, 0.0533756000, 0.0894180000, 0.1984255000, 0.5299674000, 1.4965288000", \ - "0.0374759000, 0.0428703000, 0.0556563000, 0.0911467000, 0.1992273000, 0.5299642000, 1.4971258000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__fa_4") { - leakage_power () { - value : 0.0081707000; - when : "!A&!B&CIN"; - } - leakage_power () { - value : 0.0105142000; - when : "!A&!B&!CIN"; - } - leakage_power () { - value : 0.0078087000; - when : "!A&B&CIN"; - } - leakage_power () { - value : 0.0082912000; - when : "!A&B&!CIN"; - } - leakage_power () { - value : 0.0077645000; - when : "A&!B&CIN"; - } - leakage_power () { - value : 0.0084257000; - when : "A&!B&!CIN"; - } - leakage_power () { - value : 0.0050748000; - when : "A&B&CIN"; - } - leakage_power () { - value : 0.0084930000; - when : "A&B&!CIN"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__fa"; - cell_leakage_power : 0.0080678640; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0077000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0074500000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0079510000; - } - pin ("B") { - capacitance : 0.0069770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0067560000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0071990000; - } - pin ("CIN") { - capacitance : 0.0051040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0050330000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051750000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B) | (A&CIN) | (B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0030931000, 0.0090778000, 0.0226717000, 0.0381432000, 0.0134788000, -0.151403900, -0.736163800", \ - "0.0030849000, 0.0090650000, 0.0226002000, 0.0379120000, 0.0133786000, -0.151507600, -0.736395400", \ - "0.0030783000, 0.0090363000, 0.0225822000, 0.0377180000, 0.0128952000, -0.151919400, -0.736736200", \ - "0.0030708000, 0.0089984000, 0.0224846000, 0.0377422000, 0.0129034000, -0.152077500, -0.736949700", \ - "0.0030555000, 0.0089604000, 0.0223704000, 0.0373147000, 0.0123350000, -0.152603300, -0.737411000", \ - "0.0030444000, 0.0089356000, 0.0222848000, 0.0372038000, 0.0119946000, -0.153033500, -0.737462200", \ - "0.0030896000, 0.0090549000, 0.0225169000, 0.0374211000, 0.0120077000, -0.153087000, -0.737459700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0005458000, 0.0017951000, 0.0061606000, 0.0221681000, 0.0777845000, 0.2671443000, 0.8499414000", \ - "0.0005479000, 0.0017820000, 0.0061895000, 0.0220058000, 0.0777239000, 0.2669313000, 0.8488787000", \ - "0.0005423000, 0.0017932000, 0.0060869000, 0.0219407000, 0.0777397000, 0.2669154000, 0.8497334000", \ - "0.0005306000, 0.0017476000, 0.0060399000, 0.0218785000, 0.0774521000, 0.2662946000, 0.8477472000", \ - "0.0005295000, 0.0017381000, 0.0060490000, 0.0219141000, 0.0772153000, 0.2665190000, 0.8494146000", \ - "0.0005259000, 0.0017384000, 0.0059510000, 0.0215194000, 0.0766452000, 0.2658778000, 0.8489221000", \ - "0.0006098000, 0.0019719000, 0.0065870000, 0.0227582000, 0.0783212000, 0.2652900000, 0.8475604000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0030461000, 0.0089382000, 0.0222777000, 0.0370537000, 0.0119797000, -0.152925400, -0.737563900", \ - "0.0030425000, 0.0089276000, 0.0222654000, 0.0372470000, 0.0121836000, -0.152731100, -0.737556900", \ - "0.0030444000, 0.0089409000, 0.0223133000, 0.0371235000, 0.0119537000, -0.153030900, -0.737677800", \ - "0.0030316000, 0.0088865000, 0.0221721000, 0.0369642000, 0.0116816000, -0.153119700, -0.737955300", \ - "0.0030201000, 0.0088477000, 0.0220531000, 0.0366393000, 0.0113336000, -0.153723700, -0.738341100", \ - "0.0030150000, 0.0088445000, 0.0220269000, 0.0366503000, 0.0111185000, -0.153928300, -0.738500500", \ - "0.0031258000, 0.0091543000, 0.0227730000, 0.0377573000, 0.0122397000, -0.153146900, -0.737993200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0005337000, 0.0017470000, 0.0060679000, 0.0218907000, 0.0775237000, 0.2664391000, 0.8494201000", \ - "0.0005370000, 0.0017588000, 0.0060590000, 0.0219207000, 0.0775975000, 0.2665378000, 0.8497534000", \ - "0.0005244000, 0.0017519000, 0.0060764000, 0.0218654000, 0.0776089000, 0.2669526000, 0.8487116000", \ - "0.0005250000, 0.0017360000, 0.0059822000, 0.0217691000, 0.0775286000, 0.2664195000, 0.8496363000", \ - "0.0005224000, 0.0017236000, 0.0059455000, 0.0216825000, 0.0772841000, 0.2660865000, 0.8492019000", \ - "0.0005169000, 0.0017053000, 0.0058805000, 0.0214141000, 0.0762881000, 0.2654078000, 0.8475260000", \ - "0.0005794000, 0.0018809000, 0.0063205000, 0.0221437000, 0.0771797000, 0.2646198000, 0.8485113000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0029425000, 0.0086577000, 0.0215712000, 0.0354896000, 0.0099887000, -0.154788200, -0.738955600", \ - "0.0029360000, 0.0085996000, 0.0214559000, 0.0354539000, 0.0100595000, -0.154740500, -0.738765100", \ - "0.0029288000, 0.0086203000, 0.0214596000, 0.0354961000, 0.0099080000, -0.154955500, -0.739114400", \ - "0.0029303000, 0.0086034000, 0.0214971000, 0.0353835000, 0.0096245000, -0.155062600, -0.739464700", \ - "0.0029158000, 0.0085593000, 0.0212702000, 0.0351700000, 0.0092835000, -0.155633000, -0.739737200", \ - "0.0029472000, 0.0086551000, 0.0214708000, 0.0354597000, 0.0095666000, -0.155622500, -0.739850300", \ - "0.0029871000, 0.0087620000, 0.0217259000, 0.0356405000, 0.0094279000, -0.155961800, -0.740365700"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0006453000, 0.0021238000, 0.0070121000, 0.0239786000, 0.0807219000, 0.2706894000, 0.8519469000", \ - "0.0006556000, 0.0021295000, 0.0070190000, 0.0239942000, 0.0807459000, 0.2707005000, 0.8519906000", \ - "0.0006563000, 0.0021189000, 0.0070044000, 0.0239234000, 0.0808669000, 0.2703594000, 0.8538346000", \ - "0.0006506000, 0.0020959000, 0.0069916000, 0.0238306000, 0.0806429000, 0.2701225000, 0.8536142000", \ - "0.0006462000, 0.0021015000, 0.0069528000, 0.0237697000, 0.0804387000, 0.2701776000, 0.8529209000", \ - "0.0006535000, 0.0021112000, 0.0069438000, 0.0236987000, 0.0796799000, 0.2689274000, 0.8528371000", \ - "0.0007144000, 0.0022812000, 0.0073328000, 0.0242629000, 0.0808371000, 0.2691608000, 0.8521972000"); - } - } - max_capacitance : 0.5328470000; - max_transition : 1.4974510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4557165000, 0.4627956000, 0.4814853000, 0.5227298000, 0.6027241000, 0.7575376000, 1.1123690000", \ - "0.4602259000, 0.4673159000, 0.4860113000, 0.5273182000, 0.6073054000, 0.7621558000, 1.1169992000", \ - "0.4714627000, 0.4787152000, 0.4972647000, 0.5386941000, 0.6185677000, 0.7737029000, 1.1286354000", \ - "0.4959486000, 0.5030173000, 0.5216994000, 0.5629456000, 0.6431227000, 0.7979709000, 1.1528474000", \ - "0.5537693000, 0.5610327000, 0.5791783000, 0.6206737000, 0.7003793000, 0.8551294000, 1.2100627000", \ - "0.6944468000, 0.7015067000, 0.7200792000, 0.7613670000, 0.8412642000, 0.9962576000, 1.3513767000", \ - "0.9904716000, 0.9983020000, 1.0179230000, 1.0630942000, 1.1478672000, 1.3081690000, 1.6649531000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1993675000, 0.2053757000, 0.2210166000, 0.2571332000, 0.3407867000, 0.5686733000, 1.2822498000", \ - "0.2040550000, 0.2100749000, 0.2257335000, 0.2616610000, 0.3451745000, 0.5731696000, 1.2867978000", \ - "0.2137722000, 0.2197557000, 0.2354936000, 0.2713345000, 0.3548527000, 0.5829136000, 1.2966123000", \ - "0.2350410000, 0.2410660000, 0.2567343000, 0.2929294000, 0.3764630000, 0.6043632000, 1.3181799000", \ - "0.2835976000, 0.2896077000, 0.3052861000, 0.3412146000, 0.4245658000, 0.6524809000, 1.3663449000", \ - "0.3725254000, 0.3792892000, 0.3961868000, 0.4348925000, 0.5209504000, 0.7499196000, 1.4639374000", \ - "0.4961482000, 0.5041197000, 0.5248003000, 0.5699551000, 0.6621898000, 0.8944274000, 1.6096778000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0717933000, 0.0755576000, 0.0863444000, 0.1106760000, 0.1617343000, 0.2911693000, 0.6928780000", \ - "0.0718461000, 0.0756208000, 0.0863526000, 0.1104531000, 0.1617075000, 0.2911691000, 0.6926995000", \ - "0.0720301000, 0.0759579000, 0.0864242000, 0.1108966000, 0.1620519000, 0.2909385000, 0.6928597000", \ - "0.0720629000, 0.0755620000, 0.0863095000, 0.1104119000, 0.1618369000, 0.2909759000, 0.6929206000", \ - "0.0719429000, 0.0763464000, 0.0861818000, 0.1103330000, 0.1627031000, 0.2920046000, 0.6930108000", \ - "0.0721132000, 0.0759294000, 0.0859640000, 0.1099134000, 0.1618686000, 0.2910768000, 0.6937300000", \ - "0.0848750000, 0.0886108000, 0.0991366000, 0.1243734000, 0.1744988000, 0.2995285000, 0.6956313000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0383652000, 0.0425564000, 0.0546846000, 0.0852102000, 0.1767856000, 0.4855400000, 1.4935776000", \ - "0.0386898000, 0.0425118000, 0.0543177000, 0.0855364000, 0.1767808000, 0.4859109000, 1.4946089000", \ - "0.0382374000, 0.0426013000, 0.0543965000, 0.0853183000, 0.1767247000, 0.4852001000, 1.4937105000", \ - "0.0382404000, 0.0424849000, 0.0546860000, 0.0854502000, 0.1764966000, 0.4850988000, 1.4926133000", \ - "0.0382492000, 0.0426014000, 0.0542122000, 0.0851773000, 0.1768805000, 0.4852767000, 1.4938788000", \ - "0.0443299000, 0.0490699000, 0.0610846000, 0.0917976000, 0.1810490000, 0.4863227000, 1.4938817000", \ - "0.0585865000, 0.0637566000, 0.0774026000, 0.1080255000, 0.1936027000, 0.4926488000, 1.4970030000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4277878000, 0.4350693000, 0.4537365000, 0.4948164000, 0.5748542000, 0.7300578000, 1.0850488000", \ - "0.4322964000, 0.4393809000, 0.4580815000, 0.4994123000, 0.5796141000, 0.7345834000, 1.0894253000", \ - "0.4428061000, 0.4500663000, 0.4687120000, 0.5099230000, 0.5900705000, 0.7450167000, 1.0999962000", \ - "0.4687050000, 0.4758164000, 0.4939542000, 0.5354473000, 0.6151355000, 0.7700365000, 1.1250343000", \ - "0.5327123000, 0.5396872000, 0.5582035000, 0.5993540000, 0.6795391000, 0.8345379000, 1.1895755000", \ - "0.6894235000, 0.6964392000, 0.7152286000, 0.7563044000, 0.8367824000, 0.9913536000, 1.3464239000", \ - "1.0342406000, 1.0421657000, 1.0627147000, 1.1075971000, 1.1928654000, 1.3520850000, 1.7082544000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1944082000, 0.2009323000, 0.2178167000, 0.2565664000, 0.3438783000, 0.5740424000, 1.2884042000", \ - "0.1995131000, 0.2060356000, 0.2229058000, 0.2617139000, 0.3489398000, 0.5790898000, 1.2934115000", \ - "0.2096801000, 0.2161341000, 0.2330608000, 0.2718673000, 0.3589923000, 0.5892914000, 1.3036071000", \ - "0.2310671000, 0.2375699000, 0.2545344000, 0.2931378000, 0.3805315000, 0.6107469000, 1.3250789000", \ - "0.2793717000, 0.2859258000, 0.3027575000, 0.3413829000, 0.4286459000, 0.6588239000, 1.3732525000", \ - "0.3670754000, 0.3739978000, 0.3920829000, 0.4333292000, 0.5236803000, 0.7553353000, 1.4697981000", \ - "0.4937704000, 0.5020902000, 0.5235424000, 0.5700675000, 0.6664775000, 0.9030500000, 1.6190771000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0721067000, 0.0762627000, 0.0864590000, 0.1103197000, 0.1616914000, 0.2909807000, 0.6929107000", \ - "0.0718283000, 0.0755573000, 0.0862938000, 0.1103609000, 0.1618996000, 0.2912141000, 0.6933040000", \ - "0.0720825000, 0.0759792000, 0.0867294000, 0.1117728000, 0.1618948000, 0.2910181000, 0.6931103000", \ - "0.0723764000, 0.0763439000, 0.0862065000, 0.1103326000, 0.1628794000, 0.2921782000, 0.6933294000", \ - "0.0718590000, 0.0756922000, 0.0869788000, 0.1105653000, 0.1628916000, 0.2911095000, 0.6931434000", \ - "0.0718899000, 0.0755682000, 0.0862653000, 0.1101390000, 0.1617031000, 0.2909928000, 0.6928835000", \ - "0.0900358000, 0.0937340000, 0.1047611000, 0.1284687000, 0.1771962000, 0.2995997000, 0.6955689000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0420154000, 0.0462398000, 0.0587962000, 0.0907492000, 0.1822132000, 0.4879293000, 1.4965998000", \ - "0.0420145000, 0.0462162000, 0.0584740000, 0.0907315000, 0.1823249000, 0.4877947000, 1.4966803000", \ - "0.0416985000, 0.0460760000, 0.0589085000, 0.0907022000, 0.1823975000, 0.4879712000, 1.4961540000", \ - "0.0415393000, 0.0461398000, 0.0588577000, 0.0906572000, 0.1825058000, 0.4876167000, 1.4960412000", \ - "0.0423438000, 0.0465504000, 0.0586759000, 0.0906595000, 0.1824982000, 0.4878146000, 1.4966239000", \ - "0.0466553000, 0.0514373000, 0.0647607000, 0.0973460000, 0.1876657000, 0.4886711000, 1.4974506000", \ - "0.0612289000, 0.0671774000, 0.0798807000, 0.1124799000, 0.2018068000, 0.4973399000, 1.4970133000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.3894766000, 0.3962786000, 0.4143256000, 0.4540165000, 0.5316110000, 0.6824711000, 1.0333839000", \ - "0.3938811000, 0.4008630000, 0.4188362000, 0.4583977000, 0.5351410000, 0.6866172000, 1.0376063000", \ - "0.4045493000, 0.4113451000, 0.4290135000, 0.4689544000, 0.5463728000, 0.6974404000, 1.0484148000", \ - "0.4310239000, 0.4378156000, 0.4556771000, 0.4955992000, 0.5733782000, 0.7240538000, 1.0750788000", \ - "0.4961075000, 0.5028600000, 0.5208794000, 0.5608377000, 0.6379449000, 0.7890104000, 1.1399688000", \ - "0.6540569000, 0.6610279000, 0.6789301000, 0.7184305000, 0.7959257000, 0.9465749000, 1.2974821000", \ - "0.9863783000, 0.9940008000, 1.0140964000, 1.0590560000, 1.1431581000, 1.3004866000, 1.6528582000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1899553000, 0.1964575000, 0.2134509000, 0.2523470000, 0.3396451000, 0.5699206000, 1.2843678000", \ - "0.1944210000, 0.2009095000, 0.2179033000, 0.2568089000, 0.3440846000, 0.5743868000, 1.2888324000", \ - "0.2046806000, 0.2112528000, 0.2282347000, 0.2669383000, 0.3544177000, 0.5846617000, 1.2990693000", \ - "0.2285426000, 0.2350520000, 0.2520446000, 0.2909196000, 0.3781838000, 0.6084820000, 1.3227951000", \ - "0.2847425000, 0.2912613000, 0.3082104000, 0.3470244000, 0.4340719000, 0.6643673000, 1.3789535000", \ - "0.3860974000, 0.3934955000, 0.4127303000, 0.4544186000, 0.5440454000, 0.7751543000, 1.4896661000", \ - "0.5090444000, 0.5179633000, 0.5417985000, 0.5932309000, 0.6933433000, 0.9281779000, 1.6433187000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0669595000, 0.0706575000, 0.0814547000, 0.1059528000, 0.1559156000, 0.2833851000, 0.6875259000", \ - "0.0673093000, 0.0709584000, 0.0812240000, 0.1045242000, 0.1561283000, 0.2834141000, 0.6874045000", \ - "0.0670738000, 0.0707664000, 0.0814025000, 0.1049184000, 0.1556642000, 0.2837468000, 0.6875231000", \ - "0.0670779000, 0.0708841000, 0.0813476000, 0.1042375000, 0.1551348000, 0.2833573000, 0.6869606000", \ - "0.0672130000, 0.0705648000, 0.0810812000, 0.1053118000, 0.1552444000, 0.2831456000, 0.6866148000", \ - "0.0672107000, 0.0708525000, 0.0810329000, 0.1043816000, 0.1566775000, 0.2835819000, 0.6871167000", \ - "0.0876880000, 0.0911635000, 0.1025640000, 0.1254950000, 0.1737254000, 0.2939724000, 0.6899348000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0422167000, 0.0473151000, 0.0588333000, 0.0908655000, 0.1824271000, 0.4879261000, 1.4944893000", \ - "0.0422372000, 0.0473462000, 0.0588311000, 0.0908925000, 0.1824564000, 0.4879726000, 1.4955325000", \ - "0.0427192000, 0.0466423000, 0.0592587000, 0.0910006000, 0.1826134000, 0.4876667000, 1.4966357000", \ - "0.0421577000, 0.0471817000, 0.0588427000, 0.0908049000, 0.1824464000, 0.4871720000, 1.4932557000", \ - "0.0421689000, 0.0470850000, 0.0589650000, 0.0910585000, 0.1825876000, 0.4880837000, 1.4938061000", \ - "0.0536473000, 0.0574241000, 0.0693060000, 0.1002047000, 0.1869996000, 0.4889048000, 1.4941202000", \ - "0.0731537000, 0.0784764000, 0.0939448000, 0.1252651000, 0.2054638000, 0.4955155000, 1.4944660000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B&!CIN) | (!A&B&!CIN) | (!A&!B&CIN) | (A&B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0020852000, 0.0060336000, 0.0145713000, 0.0221453000, -0.006959100, -0.169914900, -0.739327300", \ - "0.0020778000, 0.0060198000, 0.0145276000, 0.0219966000, -0.007181800, -0.170149800, -0.739184800", \ - "0.0020748000, 0.0060090000, 0.0144976000, 0.0219203000, -0.007152800, -0.170294100, -0.739534000", \ - "0.0020709000, 0.0059908000, 0.0144573000, 0.0218593000, -0.007415900, -0.170491600, -0.739837900", \ - "0.0020700000, 0.0059973000, 0.0144720000, 0.0218925000, -0.007319600, -0.170364500, -0.739825700", \ - "0.0020538000, 0.0059385000, 0.0143104000, 0.0214797000, -0.007769200, -0.170907600, -0.740286400", \ - "0.0021877000, 0.0063362000, 0.0153342000, 0.0227607000, -0.007580600, -0.170846200, -0.740120400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0015025000, 0.0046400000, 0.0136968000, 0.0381335000, 0.1025208000, 0.2856893000, 0.8573001000", \ - "0.0014860000, 0.0046229000, 0.0135840000, 0.0379041000, 0.1019662000, 0.2866808000, 0.8566052000", \ - "0.0014825000, 0.0045591000, 0.0134994000, 0.0377100000, 0.1020408000, 0.2855726000, 0.8602203000", \ - "0.0014757000, 0.0045585000, 0.0135052000, 0.0376990000, 0.1016932000, 0.2854377000, 0.8577738000", \ - "0.0014527000, 0.0044936000, 0.0133091000, 0.0373713000, 0.1010438000, 0.2846359000, 0.8576876000", \ - "0.0014406000, 0.0044601000, 0.0132360000, 0.0371258000, 0.1008728000, 0.2843911000, 0.8549586000", \ - "0.0014576000, 0.0045098000, 0.0133571000, 0.0374192000, 0.1012959000, 0.2849225000, 0.8550821000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0020696000, 0.0060045000, 0.0144764000, 0.0218811000, -0.007478400, -0.170617600, -0.740136500", \ - "0.0020730000, 0.0060040000, 0.0144969000, 0.0218992000, -0.007393400, -0.170526700, -0.739956300", \ - "0.0020702000, 0.0060006000, 0.0144678000, 0.0218479000, -0.007454500, -0.170570700, -0.739846300", \ - "0.0020672000, 0.0059828000, 0.0144255000, 0.0217529000, -0.007487900, -0.170648200, -0.739844300", \ - "0.0020624000, 0.0059657000, 0.0143767000, 0.0216697000, -0.007591600, -0.170846200, -0.739888600", \ - "0.0020467000, 0.0059241000, 0.0142599000, 0.0214048000, -0.008112300, -0.171328500, -0.740542700", \ - "0.0021537000, 0.0062341000, 0.0150534000, 0.0221436000, -0.008168300, -0.171517300, -0.740771100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0014388000, 0.0044544000, 0.0131991000, 0.0370542000, 0.1008069000, 0.2840426000, 0.8550039000", \ - "0.0014442000, 0.0044736000, 0.0132625000, 0.0372811000, 0.1009250000, 0.2846506000, 0.8551750000", \ - "0.0014397000, 0.0044545000, 0.0132215000, 0.0371797000, 0.1007764000, 0.2840594000, 0.8555227000", \ - "0.0014258000, 0.0044137000, 0.0131046000, 0.0369053000, 0.1004662000, 0.2840024000, 0.8539967000", \ - "0.0014104000, 0.0043689000, 0.0129990000, 0.0367079000, 0.1000412000, 0.2835115000, 0.8532635000", \ - "0.0014070000, 0.0043585000, 0.0129690000, 0.0366217000, 0.0999253000, 0.2832647000, 0.8549123000", \ - "0.0014783000, 0.0045696000, 0.0135103000, 0.0377803000, 0.1017522000, 0.2853954000, 0.8602289000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0021988000, 0.0063694000, 0.0154570000, 0.0239587000, -0.004230100, -0.166654000, -0.735930700", \ - "0.0022003000, 0.0063736000, 0.0154686000, 0.0239746000, -0.004206100, -0.166617600, -0.735942300", \ - "0.0021961000, 0.0063715000, 0.0154536000, 0.0239160000, -0.004289700, -0.166751200, -0.735717300", \ - "0.0021957000, 0.0063620000, 0.0154238000, 0.0238146000, -0.004278100, -0.166736900, -0.735988000", \ - "0.0021863000, 0.0063327000, 0.0153584000, 0.0237497000, -0.004560300, -0.167047600, -0.736397200", \ - "0.0021802000, 0.0063230000, 0.0153494000, 0.0236931000, -0.004668900, -0.167269300, -0.736319800", \ - "0.0022818000, 0.0066173000, 0.0160617000, 0.0242643000, -0.004359200, -0.166784700, -0.735694700"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015910560, 0.0050629180, 0.0161107700, 0.0512662700, 0.1631350000, 0.5191138000"); - values("0.0013491000, 0.0041869000, 0.0125089000, 0.0354757000, 0.0983445000, 0.2810598000, 0.8522919000", \ - "0.0013455000, 0.0041753000, 0.0124733000, 0.0354576000, 0.0981996000, 0.2811884000, 0.8524453000", \ - "0.0013507000, 0.0041916000, 0.0125229000, 0.0354916000, 0.0982699000, 0.2812814000, 0.8526278000", \ - "0.0013399000, 0.0041514000, 0.0124244000, 0.0353771000, 0.0980510000, 0.2813309000, 0.8519903000", \ - "0.0013229000, 0.0041010000, 0.0122825000, 0.0351634000, 0.0976580000, 0.2806646000, 0.8519394000", \ - "0.0013446000, 0.0041684000, 0.0124482000, 0.0354582000, 0.0981680000, 0.2809940000, 0.8525302000", \ - "0.0013491000, 0.0041930000, 0.0125215000, 0.0356368000, 0.0984210000, 0.2815758000, 0.8562267000"); - } - } - max_capacitance : 0.5191140000; - max_transition : 1.5068080000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5920060000, 0.5993943000, 0.6194621000, 0.6644354000, 0.7522442000, 0.9172348000, 1.2771959000", \ - "0.5963902000, 0.6037978000, 0.6236325000, 0.6690513000, 0.7566381000, 0.9221952000, 1.2820529000", \ - "0.6078403000, 0.6152570000, 0.6354427000, 0.6803967000, 0.7679340000, 0.9335350000, 1.2933583000", \ - "0.6330764000, 0.6404799000, 0.6603296000, 0.7055346000, 0.7931579000, 0.9587268000, 1.3187825000", \ - "0.6875727000, 0.6950069000, 0.7146083000, 0.7598908000, 0.8474267000, 1.0129997000, 1.3727839000", \ - "0.8081648000, 0.8155900000, 0.8354946000, 0.8806946000, 0.9678262000, 1.1338439000, 1.4941062000", \ - "1.0692819000, 1.0769128000, 1.0976469000, 1.1437699000, 1.2333552000, 1.4001622000, 1.7619294000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.2242955000, 0.2307733000, 0.2476690000, 0.2863092000, 0.3738727000, 0.6036070000, 1.3120058000", \ - "0.2282326000, 0.2346777000, 0.2515244000, 0.2902442000, 0.3777760000, 0.6075163000, 1.3160421000", \ - "0.2361753000, 0.2426184000, 0.2595390000, 0.2982129000, 0.3857358000, 0.6155642000, 1.3239631000", \ - "0.2526690000, 0.2592170000, 0.2762240000, 0.3147722000, 0.4023102000, 0.6319133000, 1.3401350000", \ - "0.2895749000, 0.2960412000, 0.3129603000, 0.3517233000, 0.4390936000, 0.6686248000, 1.3761172000", \ - "0.3599226000, 0.3668547000, 0.3845790000, 0.4251164000, 0.5147965000, 0.7455126000, 1.4542646000", \ - "0.4623265000, 0.4700497000, 0.4904708000, 0.5352242000, 0.6300372000, 0.8638222000, 1.5722899000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0973854000, 0.1010454000, 0.1111900000, 0.1366643000, 0.1897777000, 0.3188292000, 0.6965389000", \ - "0.0972938000, 0.1007274000, 0.1112893000, 0.1371212000, 0.1887297000, 0.3187576000, 0.6964722000", \ - "0.0974967000, 0.1011216000, 0.1113648000, 0.1359700000, 0.1889180000, 0.3189175000, 0.6974565000", \ - "0.0973919000, 0.1008503000, 0.1112759000, 0.1369901000, 0.1922449000, 0.3185649000, 0.6962834000", \ - "0.0973129000, 0.1008793000, 0.1113472000, 0.1359861000, 0.1882871000, 0.3189297000, 0.6972040000", \ - "0.0972344000, 0.1009661000, 0.1112518000, 0.1364609000, 0.1890433000, 0.3188192000, 0.6968260000", \ - "0.1054869000, 0.1091903000, 0.1191718000, 0.1437803000, 0.1949434000, 0.3245476000, 0.6981211000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0449769000, 0.0493587000, 0.0621164000, 0.0950005000, 0.1874404000, 0.4931365000, 1.5064323000", \ - "0.0447587000, 0.0493104000, 0.0623631000, 0.0946816000, 0.1872562000, 0.4927947000, 1.5025762000", \ - "0.0447357000, 0.0492127000, 0.0624160000, 0.0946764000, 0.1872181000, 0.4929402000, 1.5019483000", \ - "0.0447755000, 0.0493331000, 0.0621735000, 0.0949161000, 0.1874236000, 0.4921258000, 1.5017034000", \ - "0.0452621000, 0.0498191000, 0.0623017000, 0.0946016000, 0.1873516000, 0.4924769000, 1.5040241000", \ - "0.0489805000, 0.0540020000, 0.0672033000, 0.0999028000, 0.1902615000, 0.4940966000, 1.5047109000", \ - "0.0602407000, 0.0651567000, 0.0797745000, 0.1114231000, 0.2008992000, 0.4984306000, 1.5027060000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5593748000, 0.5654228000, 0.5815096000, 0.6172621000, 0.6873588000, 0.8261706000, 1.1581872000", \ - "0.5639460000, 0.5700953000, 0.5860568000, 0.6218594000, 0.6921455000, 0.8312621000, 1.1627274000", \ - "0.5737124000, 0.5799092000, 0.5958588000, 0.6315404000, 0.7020166000, 0.8410609000, 1.1727004000", \ - "0.5950256000, 0.6010941000, 0.6171930000, 0.6530148000, 0.7230174000, 0.8621521000, 1.1938980000", \ - "0.6422690000, 0.6483191000, 0.6644326000, 0.7001394000, 0.7701794000, 0.9090491000, 1.2410150000", \ - "0.7381312000, 0.7441966000, 0.7602165000, 0.7960080000, 0.8660232000, 1.0049823000, 1.3367809000", \ - "0.8854995000, 0.8916126000, 0.9074191000, 0.9435239000, 1.0135239000, 1.1523472000, 1.4836123000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.7791559000, 0.7859320000, 0.8035329000, 0.8421722000, 0.9276987000, 1.1555389000, 1.8630069000", \ - "0.7838557000, 0.7905104000, 0.8081161000, 0.8467372000, 0.9322119000, 1.1605114000, 1.8675250000", \ - "0.7950298000, 0.8019265000, 0.8193493000, 0.8579911000, 0.9434042000, 1.1712771000, 1.8785513000", \ - "0.8193769000, 0.8261437000, 0.8436732000, 0.8821761000, 0.9677393000, 1.1960689000, 1.9038995000", \ - "0.8772028000, 0.8838971000, 0.9014642000, 0.9400186000, 1.0255148000, 1.2537951000, 1.9616913000", \ - "1.0172410000, 1.0240345000, 1.0415061000, 1.0800986000, 1.1658253000, 1.3940389000, 2.1018500000", \ - "1.3299292000, 1.3368007000, 1.3544302000, 1.3935922000, 1.4792202000, 1.7072502000, 2.4150155000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0644367000, 0.0675665000, 0.0766142000, 0.0988086000, 0.1438881000, 0.2669450000, 0.6539013000", \ - "0.0645424000, 0.0678837000, 0.0768309000, 0.0975454000, 0.1446134000, 0.2664701000, 0.6532064000", \ - "0.0646677000, 0.0679446000, 0.0768795000, 0.0974515000, 0.1445067000, 0.2668234000, 0.6532116000", \ - "0.0647143000, 0.0676032000, 0.0766293000, 0.0985155000, 0.1447923000, 0.2663839000, 0.6538791000", \ - "0.0647118000, 0.0675932000, 0.0766133000, 0.0987656000, 0.1439840000, 0.2664085000, 0.6539663000", \ - "0.0646933000, 0.0678414000, 0.0767627000, 0.0987539000, 0.1441415000, 0.2667118000, 0.6540517000", \ - "0.0652035000, 0.0683260000, 0.0773354000, 0.0975762000, 0.1442859000, 0.2647858000, 0.6541748000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0505142000, 0.0543615000, 0.0654654000, 0.0951359000, 0.1840108000, 0.4883446000, 1.4976552000", \ - "0.0509186000, 0.0544100000, 0.0656069000, 0.0953263000, 0.1837304000, 0.4892560000, 1.4979283000", \ - "0.0504833000, 0.0546873000, 0.0656037000, 0.0952481000, 0.1838891000, 0.4892235000, 1.4977904000", \ - "0.0507086000, 0.0544298000, 0.0656611000, 0.0951754000, 0.1840671000, 0.4887000000, 1.4945499000", \ - "0.0505408000, 0.0543381000, 0.0654053000, 0.0949167000, 0.1837334000, 0.4891320000, 1.4940614000", \ - "0.0502266000, 0.0542820000, 0.0659750000, 0.0952028000, 0.1839325000, 0.4883398000, 1.4939412000", \ - "0.0511634000, 0.0553051000, 0.0667430000, 0.0960880000, 0.1845532000, 0.4893103000, 1.4967627000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5715451000, 0.5789778000, 0.5986445000, 0.6441203000, 0.7316371000, 0.8976243000, 1.2576631000", \ - "0.5754981000, 0.5829329000, 0.6030206000, 0.6480761000, 0.7360157000, 0.9013411000, 1.2618133000", \ - "0.5866189000, 0.5940493000, 0.6139043000, 0.6593093000, 0.7471536000, 0.9128350000, 1.2733165000", \ - "0.6122922000, 0.6197265000, 0.6398965000, 0.6847825000, 0.7724341000, 0.9384354000, 1.2986325000", \ - "0.6708676000, 0.6783014000, 0.6983436000, 0.7434100000, 0.8314387000, 0.9965823000, 1.3572213000", \ - "0.8097023000, 0.8171138000, 0.8372826000, 0.8823166000, 0.9698352000, 1.1365194000, 1.4972187000", \ - "1.1171751000, 1.1248259000, 1.1457512000, 1.1921446000, 1.2819779000, 1.4495176000, 1.8118428000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.2178745000, 0.2243371000, 0.2412250000, 0.2801392000, 0.3676135000, 0.5979318000, 1.3082946000", \ - "0.2216023000, 0.2281450000, 0.2451879000, 0.2837950000, 0.3714717000, 0.6015263000, 1.3099072000", \ - "0.2304792000, 0.2370019000, 0.2538464000, 0.2925963000, 0.3802739000, 0.6105391000, 1.3197662000", \ - "0.2511759000, 0.2576321000, 0.2745582000, 0.3132556000, 0.4009152000, 0.6312474000, 1.3404379000", \ - "0.2986363000, 0.3050839000, 0.3219538000, 0.3609267000, 0.4482248000, 0.6787729000, 1.3884160000", \ - "0.3895321000, 0.3965299000, 0.4145194000, 0.4547018000, 0.5442935000, 0.7751988000, 1.4852227000", \ - "0.5165780000, 0.5246404000, 0.5456818000, 0.5914281000, 0.6860819000, 0.9193966000, 1.6288469000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0977088000, 0.1012704000, 0.1118234000, 0.1364863000, 0.1891030000, 0.3175757000, 0.6980905000", \ - "0.0977261000, 0.1013681000, 0.1114978000, 0.1370038000, 0.1901012000, 0.3192924000, 0.6970801000", \ - "0.0975366000, 0.1011179000, 0.1116432000, 0.1375669000, 0.1892029000, 0.3190802000, 0.6975248000", \ - "0.0979467000, 0.1010336000, 0.1120018000, 0.1363452000, 0.1887979000, 0.3174739000, 0.6979251000", \ - "0.0977747000, 0.1014172000, 0.1114809000, 0.1370330000, 0.1905810000, 0.3202043000, 0.6963133000", \ - "0.0977775000, 0.1013665000, 0.1112104000, 0.1374276000, 0.1897139000, 0.3193122000, 0.6974529000", \ - "0.1074248000, 0.1109028000, 0.1211389000, 0.1449363000, 0.1965132000, 0.3231065000, 0.6975044000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0454494000, 0.0495440000, 0.0619244000, 0.0947756000, 0.1876279000, 0.4935001000, 1.5068075000", \ - "0.0448545000, 0.0494403000, 0.0622784000, 0.0951159000, 0.1876574000, 0.4931097000, 1.5014624000", \ - "0.0447920000, 0.0495503000, 0.0619331000, 0.0947766000, 0.1874256000, 0.4934086000, 1.5034817000", \ - "0.0447581000, 0.0493750000, 0.0625571000, 0.0947819000, 0.1874127000, 0.4934277000, 1.5032118000", \ - "0.0447358000, 0.0492657000, 0.0619326000, 0.0947978000, 0.1875143000, 0.4935337000, 1.5052996000", \ - "0.0501074000, 0.0552398000, 0.0679683000, 0.1002655000, 0.1905088000, 0.4945145000, 1.5053837000", \ - "0.0656248000, 0.0714099000, 0.0835264000, 0.1157804000, 0.2015593000, 0.4977032000, 1.5050524000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5791106000, 0.5853976000, 0.6015847000, 0.6379838000, 0.7083452000, 0.8475562000, 1.1790148000", \ - "0.5850358000, 0.5913295000, 0.6076640000, 0.6438473000, 0.7142675000, 0.8535486000, 1.1850554000", \ - "0.5957316000, 0.6020162000, 0.6182138000, 0.6545844000, 0.7250200000, 0.8643251000, 1.1958959000", \ - "0.6167857000, 0.6229450000, 0.6393783000, 0.6754263000, 0.7463128000, 0.8856113000, 1.2172091000", \ - "0.6620521000, 0.6683576000, 0.6843416000, 0.7207536000, 0.7916169000, 0.9309063000, 1.2622969000", \ - "0.7547345000, 0.7610344000, 0.7772022000, 0.8135450000, 0.8839677000, 1.0233021000, 1.3549096000", \ - "0.9045729000, 0.9107230000, 0.9265871000, 0.9627852000, 1.0329109000, 1.1715939000, 1.5028943000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.7493993000, 0.7561340000, 0.7737341000, 0.8121996000, 0.8978788000, 1.1261834000, 1.8340414000", \ - "0.7538365000, 0.7607203000, 0.7780504000, 0.8167298000, 0.9022771000, 1.1306448000, 1.8384730000", \ - "0.7642927000, 0.7710925000, 0.7885283000, 0.8272230000, 0.9127112000, 1.1411539000, 1.8477556000", \ - "0.7899681000, 0.7967625000, 0.8142281000, 0.8529875000, 0.9384444000, 1.1667028000, 1.8745585000", \ - "0.8538098000, 0.8606065000, 0.8780595000, 0.9167793000, 1.0022471000, 1.2305617000, 1.9384245000", \ - "1.0102704000, 1.0170654000, 1.0345473000, 1.0731521000, 1.1588858000, 1.3870695000, 2.0932653000", \ - "1.3732204000, 1.3800729000, 1.3977671000, 1.4365510000, 1.5223306000, 1.7507272000, 2.4582580000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0663234000, 0.0694801000, 0.0786057000, 0.0997530000, 0.1459559000, 0.2669731000, 0.6524086000", \ - "0.0664383000, 0.0695623000, 0.0779919000, 0.1000873000, 0.1462341000, 0.2671254000, 0.6527578000", \ - "0.0663917000, 0.0695451000, 0.0786923000, 0.0999823000, 0.1460733000, 0.2671408000, 0.6528124000", \ - "0.0665363000, 0.0697754000, 0.0787501000, 0.0990589000, 0.1459238000, 0.2671724000, 0.6523188000", \ - "0.0665786000, 0.0695881000, 0.0784971000, 0.0990445000, 0.1461763000, 0.2672957000, 0.6531289000", \ - "0.0664665000, 0.0697241000, 0.0787995000, 0.0998813000, 0.1462351000, 0.2671669000, 0.6528077000", \ - "0.0660282000, 0.0691601000, 0.0775335000, 0.0982234000, 0.1447855000, 0.2644559000, 0.6540556000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0501647000, 0.0541041000, 0.0656523000, 0.0951271000, 0.1840300000, 0.4890948000, 1.4944095000", \ - "0.0500136000, 0.0546670000, 0.0655181000, 0.0948903000, 0.1840071000, 0.4887602000, 1.4945404000", \ - "0.0499687000, 0.0541177000, 0.0660003000, 0.0950219000, 0.1838554000, 0.4890139000, 1.4963125000", \ - "0.0499609000, 0.0542896000, 0.0657838000, 0.0949721000, 0.1838652000, 0.4891621000, 1.4952205000", \ - "0.0499401000, 0.0540684000, 0.0659754000, 0.0949978000, 0.1837866000, 0.4890948000, 1.4941436000", \ - "0.0499736000, 0.0540502000, 0.0658789000, 0.0949457000, 0.1839272000, 0.4893245000, 1.4965672000", \ - "0.0508261000, 0.0551452000, 0.0662204000, 0.0957645000, 0.1845317000, 0.4885101000, 1.4976438000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5497081000, 0.5571313000, 0.5769804000, 0.6223139000, 0.7100840000, 0.8751617000, 1.2355710000", \ - "0.5528929000, 0.5603333000, 0.5802434000, 0.6254814000, 0.7136447000, 0.8785202000, 1.2388098000", \ - "0.5605184000, 0.5679233000, 0.5881096000, 0.6330299000, 0.7199810000, 0.8862803000, 1.2468658000", \ - "0.5806735000, 0.5880814000, 0.6080650000, 0.6530834000, 0.7408834000, 0.9067287000, 1.2669897000", \ - "0.6387412000, 0.6461567000, 0.6662436000, 0.7096970000, 0.7971217000, 0.9640653000, 1.3244111000", \ - "0.7832259000, 0.7906496000, 0.8106387000, 0.8556371000, 0.9433418000, 1.1096849000, 1.4697418000", \ - "1.1246702000, 1.1323071000, 1.1533658000, 1.1994855000, 1.2879928000, 1.4546170000, 1.8159979000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.2171727000, 0.2237011000, 0.2405218000, 0.2792470000, 0.3668207000, 0.5969454000, 1.3058037000", \ - "0.2215815000, 0.2280796000, 0.2449221000, 0.2836483000, 0.3711979000, 0.6012528000, 1.3100996000", \ - "0.2313850000, 0.2378590000, 0.2547354000, 0.2934056000, 0.3809627000, 0.6109039000, 1.3184978000", \ - "0.2532181000, 0.2596697000, 0.2766358000, 0.3152984000, 0.4028185000, 0.6328491000, 1.3413840000", \ - "0.3054771000, 0.3119415000, 0.3288631000, 0.3675450000, 0.4549592000, 0.6853586000, 1.3940045000", \ - "0.4075131000, 0.4145045000, 0.4325477000, 0.4726025000, 0.5614269000, 0.7913579000, 1.5021238000", \ - "0.5350154000, 0.5434395000, 0.5653931000, 0.6134742000, 0.7074291000, 0.9399954000, 1.6499826000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0972710000, 0.1007772000, 0.1113194000, 0.1371552000, 0.1921703000, 0.3202635000, 0.6955648000", \ - "0.0973931000, 0.1008314000, 0.1112466000, 0.1368387000, 0.1907667000, 0.3193769000, 0.6959524000", \ - "0.0974488000, 0.1011074000, 0.1113734000, 0.1357634000, 0.1906343000, 0.3189863000, 0.6973734000", \ - "0.0974311000, 0.1010534000, 0.1110652000, 0.1359370000, 0.1920586000, 0.3184467000, 0.6968530000", \ - "0.0976105000, 0.1010127000, 0.1112803000, 0.1360862000, 0.1888749000, 0.3194298000, 0.6958815000", \ - "0.0974629000, 0.1009423000, 0.1109092000, 0.1373194000, 0.1896091000, 0.3177844000, 0.6959866000", \ - "0.1094973000, 0.1126507000, 0.1218328000, 0.1450919000, 0.1956736000, 0.3215571000, 0.6981291000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0453656000, 0.0495153000, 0.0622144000, 0.0947444000, 0.1873530000, 0.4931683000, 1.5022107000", \ - "0.0453562000, 0.0493875000, 0.0623162000, 0.0947119000, 0.1873211000, 0.4930276000, 1.5022007000", \ - "0.0452196000, 0.0498300000, 0.0622030000, 0.0949818000, 0.1873613000, 0.4930591000, 1.5031002000", \ - "0.0446697000, 0.0492190000, 0.0622889000, 0.0949066000, 0.1874835000, 0.4931342000, 1.5059529000", \ - "0.0446633000, 0.0492638000, 0.0619303000, 0.0943541000, 0.1870779000, 0.4918393000, 1.5049079000", \ - "0.0527086000, 0.0566680000, 0.0692972000, 0.1002002000, 0.1909652000, 0.4937855000, 1.5051371000", \ - "0.0719130000, 0.0772401000, 0.0900979000, 0.1217189000, 0.2051124000, 0.4988112000, 1.5033891000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.5757159000, 0.5818859000, 0.5982468000, 0.6343794000, 0.7049025000, 0.8439972000, 1.1757220000", \ - "0.5802832000, 0.5864541000, 0.6028223000, 0.6389553000, 0.7094693000, 0.8485646000, 1.1803223000", \ - "0.5906707000, 0.5970014000, 0.6131350000, 0.6493205000, 0.7200854000, 0.8594583000, 1.1906173000", \ - "0.6142239000, 0.6204074000, 0.6368748000, 0.6728520000, 0.7433203000, 0.8827800000, 1.2140481000", \ - "0.6676812000, 0.6738451000, 0.6902007000, 0.7263019000, 0.7967860000, 0.9358962000, 1.2676629000", \ - "0.7744378000, 0.7807450000, 0.7970070000, 0.8331617000, 0.9038560000, 1.0432090000, 1.3744500000", \ - "0.9256814000, 0.9318205000, 0.9473411000, 0.9831616000, 1.0538024000, 1.1935690000, 1.5263072000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.7132905000, 0.7197782000, 0.7364135000, 0.7731916000, 0.8575204000, 1.0852751000, 1.7921954000", \ - "0.7179383000, 0.7243748000, 0.7408983000, 0.7777611000, 0.8620216000, 1.0899475000, 1.7971453000", \ - "0.7282885000, 0.7347380000, 0.7512712000, 0.7881086000, 0.8723795000, 1.1003405000, 1.8068714000", \ - "0.7548790000, 0.7612833000, 0.7778926000, 0.8149666000, 0.8991630000, 1.1264646000, 1.8346382000", \ - "0.8198383000, 0.8262378000, 0.8428759000, 0.8798416000, 0.9640709000, 1.1916471000, 1.8986230000", \ - "0.9762386000, 0.9826981000, 0.9992666000, 1.0361392000, 1.1204893000, 1.3481727000, 2.0557309000", \ - "1.3316929000, 1.3382518000, 1.3550046000, 1.3922801000, 1.4767040000, 1.7045710000, 2.4127085000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0660729000, 0.0693149000, 0.0784583000, 0.1005694000, 0.1452113000, 0.2671172000, 0.6536571000", \ - "0.0660771000, 0.0693216000, 0.0784804000, 0.1005758000, 0.1452149000, 0.2671988000, 0.6535610000", \ - "0.0663956000, 0.0696887000, 0.0786480000, 0.0990745000, 0.1460460000, 0.2669532000, 0.6535693000", \ - "0.0663688000, 0.0695518000, 0.0780444000, 0.1005656000, 0.1450906000, 0.2672777000, 0.6536263000", \ - "0.0661449000, 0.0693400000, 0.0784705000, 0.1005842000, 0.1451497000, 0.2670907000, 0.6535962000", \ - "0.0664774000, 0.0697609000, 0.0786400000, 0.1005102000, 0.1459719000, 0.2669881000, 0.6526812000", \ - "0.0655997000, 0.0686526000, 0.0772243000, 0.0980790000, 0.1460540000, 0.2657513000, 0.6544850000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015910600, 0.0050629200, 0.0161108000, 0.0512663000, 0.1631350000, 0.5191140000"); - values("0.0466465000, 0.0507144000, 0.0619355000, 0.0922186000, 0.1820384000, 0.4888116000, 1.4986873000", \ - "0.0469411000, 0.0509159000, 0.0619554000, 0.0918142000, 0.1823927000, 0.4893086000, 1.4988216000", \ - "0.0471260000, 0.0506361000, 0.0619739000, 0.0920414000, 0.1819798000, 0.4891787000, 1.4989033000", \ - "0.0467444000, 0.0508224000, 0.0624342000, 0.0918145000, 0.1818725000, 0.4889343000, 1.4992010000", \ - "0.0467966000, 0.0508915000, 0.0623822000, 0.0919229000, 0.1819789000, 0.4886940000, 1.4962477000", \ - "0.0467582000, 0.0509405000, 0.0617954000, 0.0920258000, 0.1824613000, 0.4892295000, 1.4986385000", \ - "0.0477262000, 0.0516826000, 0.0631281000, 0.0923922000, 0.1822358000, 0.4878856000, 1.4990719000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__fah_1") { - leakage_power () { - value : 0.0171775000; - when : "!A&!B&CI"; - } - leakage_power () { - value : 0.0203413000; - when : "!A&!B&!CI"; - } - leakage_power () { - value : 0.0193215000; - when : "!A&B&CI"; - } - leakage_power () { - value : 0.0215092000; - when : "!A&B&!CI"; - } - leakage_power () { - value : 0.0194900000; - when : "A&!B&CI"; - } - leakage_power () { - value : 0.0195829000; - when : "A&!B&!CI"; - } - leakage_power () { - value : 0.0193396000; - when : "A&B&CI"; - } - leakage_power () { - value : 0.0240735000; - when : "A&B&!CI"; - } - area : 33.782400000; - cell_footprint : "sky130_fd_sc_hd__fah"; - cell_leakage_power : 0.0201044300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0046980000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044730000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049230000; - } - pin ("B") { - capacitance : 0.0067030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0064500000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0069560000; - } - pin ("CI") { - capacitance : 0.0023950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022640000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025260000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B) | (A&CI) | (B&CI)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0050274000, 0.0119927000, 0.0251749000, 0.0412402000, 0.0427843000, -0.002371600, -0.157271700", \ - "0.0050066000, 0.0119433000, 0.0250786000, 0.0410655000, 0.0425110000, -0.002715400, -0.157680700", \ - "0.0049854000, 0.0118923000, 0.0249675000, 0.0408670000, 0.0422203000, -0.003086100, -0.158061700", \ - "0.0049750000, 0.0118699000, 0.0249027000, 0.0407551000, 0.0420725000, -0.003262800, -0.158274000", \ - "0.0049682000, 0.0118461000, 0.0248628000, 0.0406565000, 0.0419343000, -0.003439200, -0.158448800", \ - "0.0050519000, 0.0120542000, 0.0253051000, 0.0414105000, 0.0429391000, -0.002082000, -0.157007300", \ - "0.0052674000, 0.0125742000, 0.0264077000, 0.0433920000, 0.0457816000, 0.0015403000, -0.153022000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0026235000, 0.0065101000, 0.0154022000, 0.0328123000, 0.0646454000, 0.1316146000, 0.2973145000", \ - "0.0026045000, 0.0064633000, 0.0152984000, 0.0326422000, 0.0643572000, 0.1319448000, 0.2961653000", \ - "0.0025811000, 0.0064052000, 0.0151898000, 0.0324497000, 0.0640872000, 0.1309265000, 0.2953931000", \ - "0.0025538000, 0.0063415000, 0.0150168000, 0.0321037000, 0.0636934000, 0.1302509000, 0.2948729000", \ - "0.0025324000, 0.0062935000, 0.0147908000, 0.0318119000, 0.0632647000, 0.1305892000, 0.2950775000", \ - "0.0025597000, 0.0063567000, 0.0147631000, 0.0319109000, 0.0633971000, 0.1307125000, 0.2936507000", \ - "0.0027709000, 0.0068598000, 0.0159286000, 0.0334169000, 0.0654390000, 0.1325751000, 0.2960756000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0043921000, 0.0104525000, 0.0218230000, 0.0351381000, 0.0340176000, -0.012978100, -0.168688300", \ - "0.0043676000, 0.0103937000, 0.0217042000, 0.0348819000, 0.0336647000, -0.013409700, -0.169253600", \ - "0.0043407000, 0.0103301000, 0.0215594000, 0.0346162000, 0.0333139000, -0.013847800, -0.169736300", \ - "0.0043351000, 0.0103188000, 0.0215206000, 0.0345561000, 0.0332341000, -0.013931400, -0.169827900", \ - "0.0043474000, 0.0103572000, 0.0216170000, 0.0346847000, 0.0334298000, -0.013704800, -0.169593000", \ - "0.0044414000, 0.0105762000, 0.0220648000, 0.0354868000, 0.0346691000, -0.012217600, -0.167972200", \ - "0.0046516000, 0.0110769000, 0.0231375000, 0.0373687000, 0.0368814000, -0.008814400, -0.164313600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0016723000, 0.0042131000, 0.0102186000, 0.0236297000, 0.0514019000, 0.1157526000, 0.2791352000", \ - "0.0016652000, 0.0041961000, 0.0101875000, 0.0235797000, 0.0513336000, 0.1162040000, 0.2790945000", \ - "0.0016528000, 0.0041643000, 0.0101234000, 0.0234756000, 0.0512093000, 0.1159469000, 0.2786152000", \ - "0.0016409000, 0.0041341000, 0.0100687000, 0.0233507000, 0.0509959000, 0.1158412000, 0.2783591000", \ - "0.0016522000, 0.0041658000, 0.0101787000, 0.0235123000, 0.0512174000, 0.1155427000, 0.2790463000", \ - "0.0017527000, 0.0044029000, 0.0106811000, 0.0243161000, 0.0522822000, 0.1173285000, 0.2816097000", \ - "0.0020136000, 0.0050299000, 0.0119275000, 0.0260767000, 0.0547567000, 0.1198348000, 0.2820534000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0031865000, 0.0075294000, 0.0154451000, 0.0235479000, 0.0170564000, -0.033412900, -0.190972600", \ - "0.0031790000, 0.0075115000, 0.0154066000, 0.0234813000, 0.0169583000, -0.033524200, -0.191097200", \ - "0.0031651000, 0.0074858000, 0.0153410000, 0.0233502000, 0.0167765000, -0.033756900, -0.191348600", \ - "0.0031548000, 0.0074583000, 0.0152801000, 0.0232432000, 0.0166406000, -0.033920700, -0.191505800", \ - "0.0031420000, 0.0074258000, 0.0151980000, 0.0230809000, 0.0163753000, -0.034207600, -0.191775400", \ - "0.0031814000, 0.0075119000, 0.0153517000, 0.0232936000, 0.0166702000, -0.033849600, -0.191374900", \ - "0.0032509000, 0.0076730000, 0.0156615000, 0.0237513000, 0.0170528000, -0.033144000, -0.190608400"); - } - related_pin : "CI"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0012675000, 0.0032332000, 0.0079567000, 0.0190971000, 0.0449122000, 0.1077638000, 0.2697947000", \ - "0.0012627000, 0.0032226000, 0.0079376000, 0.0190556000, 0.0448913000, 0.1075519000, 0.2700182000", \ - "0.0012537000, 0.0032003000, 0.0078872000, 0.0189733000, 0.0447182000, 0.1074403000, 0.2698143000", \ - "0.0012437000, 0.0031654000, 0.0078288000, 0.0188321000, 0.0445727000, 0.1073368000, 0.2708884000", \ - "0.0012340000, 0.0031411000, 0.0077608000, 0.0187134000, 0.0443914000, 0.1070100000, 0.2705151000", \ - "0.0012195000, 0.0031125000, 0.0076935000, 0.0185901000, 0.0441116000, 0.1066441000, 0.2707750000", \ - "0.0012999000, 0.0033092000, 0.0081104000, 0.0191735000, 0.0447616000, 0.1076833000, 0.2690519000"); - } - } - max_capacitance : 0.1629740000; - max_transition : 1.4968590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2945737000, 0.3017945000, 0.3169597000, 0.3470688000, 0.4073135000, 0.5392827000, 0.8647374000", \ - "0.2994545000, 0.3066951000, 0.3218806000, 0.3519441000, 0.4122456000, 0.5441539000, 0.8693951000", \ - "0.3124526000, 0.3196819000, 0.3348643000, 0.3649218000, 0.4252237000, 0.5571197000, 0.8823607000", \ - "0.3427301000, 0.3500124000, 0.3651876000, 0.3952487000, 0.4555368000, 0.5874791000, 0.9129820000", \ - "0.4002657000, 0.4075727000, 0.4227491000, 0.4529620000, 0.5133772000, 0.6453451000, 0.9705754000", \ - "0.4829576000, 0.4902708000, 0.5059952000, 0.5372584000, 0.5987529000, 0.7313387000, 1.0568275000", \ - "0.6109606000, 0.6180512000, 0.6329777000, 0.6631200000, 0.7242749000, 0.8589014000, 1.1850624000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2840097000, 0.2918432000, 0.3095374000, 0.3492960000, 0.4454712000, 0.6907493000, 1.3350581000", \ - "0.2887213000, 0.2965424000, 0.3142173000, 0.3541320000, 0.4502206000, 0.6957739000, 1.3367405000", \ - "0.2995864000, 0.3075233000, 0.3252731000, 0.3650045000, 0.4610186000, 0.7068265000, 1.3491332000", \ - "0.3203002000, 0.3282171000, 0.3459057000, 0.3856666000, 0.4818250000, 0.7274020000, 1.3699927000", \ - "0.3515266000, 0.3594526000, 0.3772481000, 0.4172822000, 0.5137178000, 0.7591728000, 1.4025339000", \ - "0.3912939000, 0.3991847000, 0.4170422000, 0.4575743000, 0.5545581000, 0.8003496000, 1.4437512000", \ - "0.4233677000, 0.4310686000, 0.4485788000, 0.4883646000, 0.5857558000, 0.8320911000, 1.4730867000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0294644000, 0.0344609000, 0.0454468000, 0.0710414000, 0.1314474000, 0.2859115000, 0.7117754000", \ - "0.0294620000, 0.0343399000, 0.0459714000, 0.0716273000, 0.1318265000, 0.2854033000, 0.7107812000", \ - "0.0295109000, 0.0343494000, 0.0459772000, 0.0716093000, 0.1318020000, 0.2856233000, 0.7107994000", \ - "0.0295405000, 0.0342215000, 0.0453855000, 0.0713922000, 0.1316648000, 0.2862486000, 0.7149840000", \ - "0.0295440000, 0.0347510000, 0.0456923000, 0.0711761000, 0.1316089000, 0.2859415000, 0.7108494000", \ - "0.0290558000, 0.0349078000, 0.0466338000, 0.0724903000, 0.1327303000, 0.2862633000, 0.7109885000", \ - "0.0280794000, 0.0330288000, 0.0444494000, 0.0709508000, 0.1333437000, 0.2886757000, 0.7078171000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0316228000, 0.0386117000, 0.0569530000, 0.1044815000, 0.2331068000, 0.5773541000, 1.4968592000", \ - "0.0316846000, 0.0386835000, 0.0568037000, 0.1044857000, 0.2326274000, 0.5784634000, 1.4913112000", \ - "0.0318084000, 0.0387015000, 0.0568908000, 0.1042968000, 0.2328503000, 0.5777988000, 1.4931636000", \ - "0.0315766000, 0.0386378000, 0.0566921000, 0.1043719000, 0.2329103000, 0.5770331000, 1.4944098000", \ - "0.0312576000, 0.0384118000, 0.0568280000, 0.1044328000, 0.2332099000, 0.5784831000, 1.4891310000", \ - "0.0304634000, 0.0377264000, 0.0563685000, 0.1046238000, 0.2334957000, 0.5784593000, 1.4877167000", \ - "0.0295721000, 0.0367484000, 0.0551641000, 0.1041013000, 0.2336886000, 0.5780217000, 1.4897173000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2774696000, 0.2846036000, 0.2996196000, 0.3296468000, 0.3898036000, 0.5216343000, 0.8471920000", \ - "0.2812595000, 0.2883982000, 0.3034335000, 0.3334533000, 0.3936054000, 0.5254488000, 0.8509516000", \ - "0.2925285000, 0.2996233000, 0.3147194000, 0.3445788000, 0.4047689000, 0.5366882000, 0.8621331000", \ - "0.3219848000, 0.3291057000, 0.3441595000, 0.3740807000, 0.4342822000, 0.5661704000, 0.8912555000", \ - "0.3918516000, 0.3989722000, 0.4139685000, 0.4438779000, 0.5040626000, 0.6359959000, 0.9610153000", \ - "0.5270330000, 0.5343800000, 0.5497049000, 0.5800604000, 0.6407435000, 0.7728849000, 1.0981599000", \ - "0.7564852000, 0.7647162000, 0.7819110000, 0.8154140000, 0.8809893000, 1.0183598000, 1.3460749000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2160915000, 0.2239383000, 0.2416700000, 0.2813791000, 0.3775518000, 0.6234502000, 1.2658823000", \ - "0.2210349000, 0.2288762000, 0.2466064000, 0.2863067000, 0.3824482000, 0.6282320000, 1.2694701000", \ - "0.2324076000, 0.2402290000, 0.2579252000, 0.2977791000, 0.3939227000, 0.6394490000, 1.2806038000", \ - "0.2588301000, 0.2666904000, 0.2843764000, 0.3241741000, 0.4202746000, 0.6660803000, 1.3080835000", \ - "0.3111172000, 0.3188426000, 0.3364868000, 0.3762009000, 0.4724022000, 0.7182945000, 1.3601502000", \ - "0.3774528000, 0.3856255000, 0.4039204000, 0.4445900000, 0.5414265000, 0.7872642000, 1.4303866000", \ - "0.4494283000, 0.4586049000, 0.4791018000, 0.5226271000, 0.6211741000, 0.8678151000, 1.5095430000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0292223000, 0.0341930000, 0.0459491000, 0.0712762000, 0.1314427000, 0.2866371000, 0.7115994000", \ - "0.0292454000, 0.0346473000, 0.0459848000, 0.0712762000, 0.1314489000, 0.2866924000, 0.7110157000", \ - "0.0293770000, 0.0342708000, 0.0454600000, 0.0709077000, 0.1314572000, 0.2861792000, 0.7153720000", \ - "0.0293406000, 0.0342289000, 0.0454084000, 0.0711886000, 0.1315761000, 0.2862208000, 0.7120168000", \ - "0.0293885000, 0.0348953000, 0.0461322000, 0.0714563000, 0.1315881000, 0.2860533000, 0.7129152000", \ - "0.0307474000, 0.0358084000, 0.0470725000, 0.0727857000, 0.1326133000, 0.2874430000, 0.7160306000", \ - "0.0358621000, 0.0413422000, 0.0540732000, 0.0810028000, 0.1422028000, 0.2949332000, 0.7138592000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0306753000, 0.0377190000, 0.0560879000, 0.1039378000, 0.2325074000, 0.5769290000, 1.4891728000", \ - "0.0306907000, 0.0377150000, 0.0560947000, 0.1039614000, 0.2327777000, 0.5778932000, 1.4961122000", \ - "0.0308543000, 0.0378601000, 0.0559814000, 0.1038110000, 0.2328379000, 0.5783509000, 1.4916119000", \ - "0.0308625000, 0.0378234000, 0.0559222000, 0.1038909000, 0.2326928000, 0.5773259000, 1.4919271000", \ - "0.0304696000, 0.0376900000, 0.0559429000, 0.1035524000, 0.2328391000, 0.5768396000, 1.4964714000", \ - "0.0319171000, 0.0392883000, 0.0578589000, 0.1053636000, 0.2335957000, 0.5787290000, 1.4958711000", \ - "0.0361532000, 0.0444041000, 0.0636481000, 0.1109072000, 0.2365982000, 0.5804295000, 1.4888181000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.1948453000, 0.2053915000, 0.2260506000, 0.2627595000, 0.3284120000, 0.4633700000, 0.7894111000", \ - "0.2001393000, 0.2106932000, 0.2313659000, 0.2680747000, 0.3337434000, 0.4687048000, 0.7947456000", \ - "0.2128602000, 0.2234426000, 0.2441500000, 0.2807493000, 0.3465079000, 0.4814849000, 0.8075131000", \ - "0.2442329000, 0.2548581000, 0.2755255000, 0.3121097000, 0.3778945000, 0.5128183000, 0.8388770000", \ - "0.3195187000, 0.3299440000, 0.3504800000, 0.3868839000, 0.4527448000, 0.5877721000, 0.9139013000", \ - "0.4698936000, 0.4818453000, 0.5047942000, 0.5437877000, 0.6111919000, 0.7468463000, 1.0730684000", \ - "0.7129969000, 0.7297599000, 0.7604013000, 0.8085490000, 0.8845399000, 1.0272957000, 1.3557943000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.1240302000, 0.1317831000, 0.1493761000, 0.1895707000, 0.2870579000, 0.5334003000, 1.1748479000", \ - "0.1287535000, 0.1365008000, 0.1540904000, 0.1942761000, 0.2917828000, 0.5380666000, 1.1790178000", \ - "0.1398966000, 0.1476458000, 0.1652306000, 0.2054018000, 0.3029197000, 0.5493186000, 1.1915878000", \ - "0.1663156000, 0.1740395000, 0.1916334000, 0.2317407000, 0.3292199000, 0.5757366000, 1.2180115000", \ - "0.2174907000, 0.2255224000, 0.2434922000, 0.2838598000, 0.3814493000, 0.6279672000, 1.2719189000", \ - "0.2921486000, 0.3015440000, 0.3218125000, 0.3649358000, 0.4641842000, 0.7112758000, 1.3550638000", \ - "0.3802789000, 0.3928622000, 0.4191363000, 0.4694178000, 0.5733003000, 0.8211049000, 1.4627257000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0483439000, 0.0530530000, 0.0633478000, 0.0853303000, 0.1409722000, 0.2902341000, 0.7137650000", \ - "0.0483633000, 0.0530677000, 0.0633504000, 0.0853491000, 0.1409764000, 0.2902358000, 0.7137570000", \ - "0.0483013000, 0.0529957000, 0.0634829000, 0.0854521000, 0.1409819000, 0.2902069000, 0.7160506000", \ - "0.0482271000, 0.0530290000, 0.0633139000, 0.0855628000, 0.1409956000, 0.2902509000, 0.7135995000", \ - "0.0481505000, 0.0530453000, 0.0633873000, 0.0857788000, 0.1405646000, 0.2901948000, 0.7134499000", \ - "0.0611165000, 0.0648732000, 0.0734331000, 0.0925979000, 0.1443621000, 0.2912265000, 0.7155828000", \ - "0.0949579000, 0.0986706000, 0.1045505000, 0.1169128000, 0.1628863000, 0.3028518000, 0.7141756000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0285445000, 0.0360027000, 0.0546900000, 0.1040592000, 0.2347647000, 0.5774806000, 1.4924024000", \ - "0.0286298000, 0.0359883000, 0.0547943000, 0.1040604000, 0.2341838000, 0.5777707000, 1.4882825000", \ - "0.0286046000, 0.0359753000, 0.0547800000, 0.1040668000, 0.2347973000, 0.5785951000, 1.4919285000", \ - "0.0285457000, 0.0359564000, 0.0548217000, 0.1041225000, 0.2341963000, 0.5772973000, 1.4924950000", \ - "0.0302669000, 0.0375186000, 0.0561732000, 0.1048096000, 0.2343693000, 0.5777996000, 1.4937416000", \ - "0.0370816000, 0.0446982000, 0.0630697000, 0.1103932000, 0.2377379000, 0.5791326000, 1.4947159000", \ - "0.0510446000, 0.0606574000, 0.0803071000, 0.1250347000, 0.2446942000, 0.5809639000, 1.4888593000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B&!CI) | (!A&B&!CI) | (!A&!B&CI) | (A&B&CI)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0041664000, 0.0098889000, 0.0205648000, 0.0328099000, 0.0306399000, -0.016416400, -0.170594400", \ - "0.0041514000, 0.0098547000, 0.0204756000, 0.0326395000, 0.0304166000, -0.016673400, -0.170836900", \ - "0.0041278000, 0.0097973000, 0.0203662000, 0.0324483000, 0.0300792000, -0.017096100, -0.171305000", \ - "0.0040924000, 0.0097136000, 0.0201859000, 0.0321066000, 0.0296003000, -0.017648300, -0.171952000", \ - "0.0040577000, 0.0096336000, 0.0199979000, 0.0318099000, 0.0291416000, -0.018201300, -0.172513900", \ - "0.0040733000, 0.0096580000, 0.0200502000, 0.0319066000, 0.0293497000, -0.017975800, -0.172266700", \ - "0.0042312000, 0.0100462000, 0.0209114000, 0.0334149000, 0.0314327000, -0.015830000, -0.169995600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0035581000, 0.0087527000, 0.0199550000, 0.0412256000, 0.0769155000, 0.1460213000, 0.3110054000", \ - "0.0035342000, 0.0086904000, 0.0198360000, 0.0410593000, 0.0766261000, 0.1454962000, 0.3104126000", \ - "0.0035136000, 0.0086422000, 0.0197260000, 0.0408606000, 0.0763360000, 0.1451567000, 0.3100491000", \ - "0.0035046000, 0.0086160000, 0.0196835000, 0.0407495000, 0.0762401000, 0.1449017000, 0.3100079000", \ - "0.0034888000, 0.0085980000, 0.0196092000, 0.0406530000, 0.0760080000, 0.1453734000, 0.3085161000", \ - "0.0035484000, 0.0087225000, 0.0200158000, 0.0414084000, 0.0770116000, 0.1460592000, 0.3113003000", \ - "0.0038703000, 0.0095048000, 0.0215591000, 0.0433915000, 0.0799219000, 0.1491380000, 0.3128446000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0031929000, 0.0075508000, 0.0154739000, 0.0236254000, 0.0172802000, -0.032464300, -0.188014500", \ - "0.0031859000, 0.0075350000, 0.0154467000, 0.0235800000, 0.0171803000, -0.032541900, -0.188119500", \ - "0.0031741000, 0.0075064000, 0.0153881000, 0.0234759000, 0.0170365000, -0.032757000, -0.188327800", \ - "0.0031630000, 0.0074735000, 0.0153299000, 0.0233483000, 0.0168692000, -0.032923500, -0.188508200", \ - "0.0031822000, 0.0075170000, 0.0154255000, 0.0235103000, 0.0171134000, -0.032673300, -0.188233200", \ - "0.0032688000, 0.0077266000, 0.0158744000, 0.0243120000, 0.0183257000, -0.031282600, -0.186702200", \ - "0.0034609000, 0.0081911000, 0.0168551000, 0.0260725000, 0.0209293000, -0.028450100, -0.183920200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0029184000, 0.0072134000, 0.0166141000, 0.0351325000, 0.0681155000, 0.1354768000, 0.2994498000", \ - "0.0028913000, 0.0071451000, 0.0164756000, 0.0348763000, 0.0677115000, 0.1353165000, 0.2972250000", \ - "0.0028648000, 0.0070844000, 0.0163413000, 0.0346117000, 0.0673725000, 0.1345086000, 0.2969706000", \ - "0.0028628000, 0.0070746000, 0.0163138000, 0.0345521000, 0.0673562000, 0.1348095000, 0.2967212000", \ - "0.0028772000, 0.0071108000, 0.0164223000, 0.0346796000, 0.0675342000, 0.1344946000, 0.2976040000", \ - "0.0029729000, 0.0073409000, 0.0169061000, 0.0354775000, 0.0687667000, 0.1363962000, 0.3004095000", \ - "0.0032237000, 0.0079394000, 0.0181613000, 0.0373682000, 0.0715863000, 0.1396177000, 0.3022499000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0027392000, 0.0064394000, 0.0130368000, 0.0191041000, 0.0109071000, -0.040484600, -0.196764400", \ - "0.0027323000, 0.0064283000, 0.0130217000, 0.0190492000, 0.0108309000, -0.040533200, -0.196810200", \ - "0.0027232000, 0.0064052000, 0.0129707000, 0.0189682000, 0.0107057000, -0.040720600, -0.197003600", \ - "0.0027115000, 0.0063751000, 0.0128987000, 0.0188291000, 0.0104963000, -0.040945800, -0.197260700", \ - "0.0026984000, 0.0063420000, 0.0128243000, 0.0187082000, 0.0103333000, -0.041171100, -0.197506000", \ - "0.0026867000, 0.0063130000, 0.0127645000, 0.0185860000, 0.0101588000, -0.041376800, -0.197713400", \ - "0.0027435000, 0.0064508000, 0.0130680000, 0.0191741000, 0.0107061000, -0.040877300, -0.197190800"); - } - related_pin : "CI"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0016950000, 0.0042592000, 0.0102404000, 0.0235453000, 0.0510604000, 0.1145247000, 0.2769765000", \ - "0.0016875000, 0.0042416000, 0.0102026000, 0.0234786000, 0.0509641000, 0.1143840000, 0.2768862000", \ - "0.0016775000, 0.0042159000, 0.0101391000, 0.0233477000, 0.0507557000, 0.1142483000, 0.2765230000", \ - "0.0016635000, 0.0041835000, 0.0100704000, 0.0232407000, 0.0505980000, 0.1140789000, 0.2761286000", \ - "0.0016455000, 0.0041414000, 0.0099866000, 0.0230787000, 0.0503535000, 0.1137006000, 0.2746963000", \ - "0.0016689000, 0.0041939000, 0.0100696000, 0.0232917000, 0.0506730000, 0.1141364000, 0.2751261000", \ - "0.0017782000, 0.0044603000, 0.0106446000, 0.0237520000, 0.0516138000, 0.1150503000, 0.2773362000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5012090000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2702396000, 0.2771109000, 0.2913574000, 0.3198568000, 0.3773000000, 0.5047683000, 0.8209084000", \ - "0.2750705000, 0.2818685000, 0.2962351000, 0.3246711000, 0.3821849000, 0.5096495000, 0.8257942000", \ - "0.2880708000, 0.2948729000, 0.3092354000, 0.3376782000, 0.3951885000, 0.5226530000, 0.8387995000", \ - "0.3184288000, 0.3253024000, 0.3395663000, 0.3680236000, 0.4255133000, 0.5529877000, 0.8690970000", \ - "0.3755441000, 0.3823050000, 0.3966355000, 0.4250174000, 0.4824650000, 0.6098433000, 0.9259090000", \ - "0.4614753000, 0.4682479000, 0.4824732000, 0.5105357000, 0.5675380000, 0.6943381000, 1.0102257000", \ - "0.5924807000, 0.5992767000, 0.6135832000, 0.6417276000, 0.6984625000, 0.8242437000, 1.1389556000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2799725000, 0.2877954000, 0.3051779000, 0.3438410000, 0.4390376000, 0.6846730000, 1.3263270000", \ - "0.2847654000, 0.2927080000, 0.3099744000, 0.3485481000, 0.4439845000, 0.6895556000, 1.3310394000", \ - "0.2958162000, 0.3037565000, 0.3209744000, 0.3595542000, 0.4549357000, 0.7001426000, 1.3420561000", \ - "0.3165764000, 0.3243221000, 0.3416363000, 0.3804989000, 0.4755691000, 0.7212865000, 1.3626895000", \ - "0.3484624000, 0.3560730000, 0.3734654000, 0.4122399000, 0.5074554000, 0.7531630000, 1.3945007000", \ - "0.3895975000, 0.3972879000, 0.4145502000, 0.4535484000, 0.5486636000, 0.7942377000, 1.4372832000", \ - "0.4226120000, 0.4302875000, 0.4473085000, 0.4862183000, 0.5811441000, 0.8265402000, 1.4670426000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0254746000, 0.0301720000, 0.0414399000, 0.0653144000, 0.1244207000, 0.2754358000, 0.6882058000", \ - "0.0256669000, 0.0301769000, 0.0410967000, 0.0661314000, 0.1245646000, 0.2756396000, 0.6807185000", \ - "0.0256600000, 0.0301805000, 0.0411359000, 0.0661531000, 0.1245619000, 0.2756274000, 0.6806217000", \ - "0.0253340000, 0.0300630000, 0.0414026000, 0.0662576000, 0.1243639000, 0.2755095000, 0.6817387000", \ - "0.0254238000, 0.0299656000, 0.0408831000, 0.0659229000, 0.1244852000, 0.2754235000, 0.6855627000", \ - "0.0249007000, 0.0295323000, 0.0405423000, 0.0649023000, 0.1233063000, 0.2742686000, 0.6871234000", \ - "0.0251872000, 0.0298417000, 0.0406466000, 0.0652037000, 0.1229491000, 0.2718617000, 0.6812444000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0298432000, 0.0366214000, 0.0539370000, 0.1012363000, 0.2317816000, 0.5790272000, 1.4949508000", \ - "0.0298536000, 0.0364565000, 0.0539382000, 0.1012560000, 0.2319184000, 0.5794122000, 1.4985019000", \ - "0.0298347000, 0.0364976000, 0.0540742000, 0.1014283000, 0.2318684000, 0.5795120000, 1.5012093000", \ - "0.0295922000, 0.0367996000, 0.0539190000, 0.1013529000, 0.2312249000, 0.5794409000, 1.4941285000", \ - "0.0292330000, 0.0362216000, 0.0537524000, 0.1011194000, 0.2315101000, 0.5793337000, 1.4937843000", \ - "0.0288482000, 0.0355295000, 0.0532323000, 0.1009192000, 0.2308430000, 0.5789473000, 1.4982463000", \ - "0.0278633000, 0.0346522000, 0.0528732000, 0.1006491000, 0.2315569000, 0.5797550000, 1.4933231000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2264463000, 0.2336452000, 0.2488322000, 0.2787842000, 0.3378993000, 0.4641423000, 0.7789631000", \ - "0.2312304000, 0.2384539000, 0.2535577000, 0.2835956000, 0.3426427000, 0.4688639000, 0.7838987000", \ - "0.2421666000, 0.2492938000, 0.2644466000, 0.2944715000, 0.3535531000, 0.4797923000, 0.7947998000", \ - "0.2673979000, 0.2746293000, 0.2898847000, 0.3199358000, 0.3789316000, 0.5051013000, 0.8200469000", \ - "0.3177931000, 0.3251600000, 0.3406443000, 0.3707005000, 0.4292849000, 0.5552449000, 0.8703449000", \ - "0.3946272000, 0.4019909000, 0.4171866000, 0.4465496000, 0.5041934000, 0.6300663000, 0.9457120000", \ - "0.4747459000, 0.4819730000, 0.4967309000, 0.5255864000, 0.5828618000, 0.7091129000, 1.0244806000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2733325000, 0.2812661000, 0.2990831000, 0.3394724000, 0.4359026000, 0.6821158000, 1.3241298000", \ - "0.2782132000, 0.2861421000, 0.3041147000, 0.3443758000, 0.4410254000, 0.6871221000, 1.3313242000", \ - "0.2910849000, 0.2990787000, 0.3169883000, 0.3572603000, 0.4539119000, 0.7000427000, 1.3440918000", \ - "0.3215766000, 0.3294794000, 0.3473158000, 0.3873782000, 0.4840626000, 0.7302592000, 1.3703982000", \ - "0.3895920000, 0.3975108000, 0.4153570000, 0.4553697000, 0.5519057000, 0.7979857000, 1.4401023000", \ - "0.5214839000, 0.5294370000, 0.5472243000, 0.5870799000, 0.6832977000, 0.9294500000, 1.5727810000", \ - "0.7384445000, 0.7466388000, 0.7645081000, 0.8037954000, 0.8988413000, 1.1435529000, 1.7853554000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0266496000, 0.0321443000, 0.0434426000, 0.0690135000, 0.1256493000, 0.2720970000, 0.6856982000", \ - "0.0269253000, 0.0320501000, 0.0433096000, 0.0687696000, 0.1257079000, 0.2720775000, 0.6846647000", \ - "0.0265452000, 0.0317970000, 0.0435955000, 0.0687559000, 0.1257088000, 0.2721373000, 0.6847131000", \ - "0.0267632000, 0.0322922000, 0.0436711000, 0.0689376000, 0.1253520000, 0.2720758000, 0.6834353000", \ - "0.0274460000, 0.0328601000, 0.0444254000, 0.0689220000, 0.1250027000, 0.2721145000, 0.6860240000", \ - "0.0282509000, 0.0334161000, 0.0439843000, 0.0679195000, 0.1233831000, 0.2724739000, 0.6810603000", \ - "0.0284778000, 0.0331430000, 0.0441296000, 0.0675022000, 0.1241324000, 0.2736652000, 0.6811267000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0288748000, 0.0360845000, 0.0547998000, 0.1033629000, 0.2330201000, 0.5796800000, 1.4970315000", \ - "0.0289288000, 0.0361809000, 0.0548350000, 0.1033032000, 0.2330500000, 0.5799422000, 1.4982755000", \ - "0.0289767000, 0.0362467000, 0.0548144000, 0.1033177000, 0.2330811000, 0.5800024000, 1.4982864000", \ - "0.0288409000, 0.0360771000, 0.0547428000, 0.1033004000, 0.2329517000, 0.5788938000, 1.4935525000", \ - "0.0290519000, 0.0362391000, 0.0547923000, 0.1032335000, 0.2328096000, 0.5796999000, 1.4957724000", \ - "0.0302827000, 0.0370789000, 0.0552032000, 0.1032318000, 0.2326067000, 0.5791217000, 1.4981181000", \ - "0.0332461000, 0.0401713000, 0.0571502000, 0.1042515000, 0.2336391000, 0.5781802000, 1.4967555000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2576722000, 0.2646620000, 0.2793211000, 0.3080522000, 0.3653458000, 0.4917954000, 0.8072191000", \ - "0.2616179000, 0.2686660000, 0.2833576000, 0.3120590000, 0.3693072000, 0.4957051000, 0.8114669000", \ - "0.2727185000, 0.2797518000, 0.2943907000, 0.3232015000, 0.3804398000, 0.5069349000, 0.8227262000", \ - "0.3022837000, 0.3093278000, 0.3240202000, 0.3527437000, 0.4100115000, 0.5364383000, 0.8522293000", \ - "0.3750046000, 0.3820096000, 0.3966915000, 0.4254180000, 0.4828004000, 0.6092232000, 0.9247702000", \ - "0.5085085000, 0.5155334000, 0.5302065000, 0.5587368000, 0.6160664000, 0.7426061000, 1.0585396000", \ - "0.7197842000, 0.7268187000, 0.7414550000, 0.7701034000, 0.8273083000, 0.9538627000, 1.2691606000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2148892000, 0.2228252000, 0.2400865000, 0.2787410000, 0.3743651000, 0.6199922000, 1.2632209000", \ - "0.2202041000, 0.2281348000, 0.2454085000, 0.2841300000, 0.3796921000, 0.6253648000, 1.2666284000", \ - "0.2320799000, 0.2398870000, 0.2572685000, 0.2960984000, 0.3913080000, 0.6370632000, 1.2780732000", \ - "0.2583562000, 0.2661374000, 0.2834315000, 0.3224085000, 0.4177666000, 0.6631460000, 1.3037391000", \ - "0.3114467000, 0.3193223000, 0.3367325000, 0.3754684000, 0.4707159000, 0.7163042000, 1.3574070000", \ - "0.3798793000, 0.3877106000, 0.4050026000, 0.4434973000, 0.5385858000, 0.7843646000, 1.4287763000", \ - "0.4462778000, 0.4540853000, 0.4713517000, 0.5102941000, 0.6051771000, 0.8504012000, 1.4909225000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0266926000, 0.0313588000, 0.0423262000, 0.0669598000, 0.1238425000, 0.2738500000, 0.6857198000", \ - "0.0265837000, 0.0313758000, 0.0423608000, 0.0665425000, 0.1239569000, 0.2739600000, 0.6879349000", \ - "0.0265990000, 0.0314251000, 0.0422636000, 0.0665156000, 0.1240950000, 0.2740634000, 0.6865021000", \ - "0.0266764000, 0.0314719000, 0.0424029000, 0.0668348000, 0.1239865000, 0.2740272000, 0.6875693000", \ - "0.0269554000, 0.0315899000, 0.0425322000, 0.0670312000, 0.1239193000, 0.2740250000, 0.6885330000", \ - "0.0267837000, 0.0315525000, 0.0423116000, 0.0667098000, 0.1237368000, 0.2741088000, 0.6882339000", \ - "0.0267577000, 0.0315418000, 0.0425367000, 0.0667646000, 0.1243283000, 0.2741961000, 0.6828780000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0293631000, 0.0361860000, 0.0537753000, 0.1012686000, 0.2318941000, 0.5798504000, 1.4980821000", \ - "0.0294147000, 0.0361653000, 0.0537886000, 0.1013591000, 0.2320417000, 0.5791823000, 1.4983995000", \ - "0.0297527000, 0.0362946000, 0.0538712000, 0.1012560000, 0.2313672000, 0.5797866000, 1.4954386000", \ - "0.0294904000, 0.0361419000, 0.0538831000, 0.1014282000, 0.2318128000, 0.5799803000, 1.4990222000", \ - "0.0296119000, 0.0362637000, 0.0537917000, 0.1013537000, 0.2315473000, 0.5798305000, 1.4940750000", \ - "0.0293014000, 0.0362109000, 0.0537384000, 0.1013850000, 0.2314507000, 0.5797302000, 1.4989803000", \ - "0.0292419000, 0.0361922000, 0.0538834000, 0.1014427000, 0.2318254000, 0.5799791000, 1.4936656000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1946602000, 0.2018575000, 0.2168331000, 0.2461418000, 0.3043430000, 0.4317986000, 0.7479191000", \ - "0.1988106000, 0.2060022000, 0.2209820000, 0.2503105000, 0.3085111000, 0.4359687000, 0.7521193000", \ - "0.2087830000, 0.2159984000, 0.2309408000, 0.2603615000, 0.3185369000, 0.4459367000, 0.7620231000", \ - "0.2326915000, 0.2399140000, 0.2549506000, 0.2843585000, 0.3425193000, 0.4699764000, 0.7860588000", \ - "0.2774515000, 0.2846033000, 0.2996751000, 0.3291138000, 0.3873894000, 0.5148307000, 0.8308928000", \ - "0.3349927000, 0.3420847000, 0.3569617000, 0.3864218000, 0.4449505000, 0.5726188000, 0.8887313000", \ - "0.3989540000, 0.4060471000, 0.4208609000, 0.4502191000, 0.5089970000, 0.6370244000, 0.9530864000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2353939000, 0.2432864000, 0.2611231000, 0.3013105000, 0.3982361000, 0.6445575000, 1.2884395000", \ - "0.2383805000, 0.2462778000, 0.2641335000, 0.3044175000, 0.4013620000, 0.6477166000, 1.2914171000", \ - "0.2475301000, 0.2554647000, 0.2732224000, 0.3134027000, 0.4103539000, 0.6565973000, 1.2977700000", \ - "0.2728249000, 0.2807046000, 0.2983790000, 0.3388408000, 0.4358408000, 0.6822128000, 1.3259067000", \ - "0.3361760000, 0.3440460000, 0.3618362000, 0.4021170000, 0.4991536000, 0.7452949000, 1.3857639000", \ - "0.4577045000, 0.4656379000, 0.4834477000, 0.5235801000, 0.6207894000, 0.8674643000, 1.5101076000", \ - "0.6470818000, 0.6554910000, 0.6735752000, 0.7138339000, 0.8112258000, 1.0585836000, 1.7000401000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0265974000, 0.0319125000, 0.0429745000, 0.0677058000, 0.1250934000, 0.2739514000, 0.6874737000", \ - "0.0265874000, 0.0318819000, 0.0429551000, 0.0677152000, 0.1251265000, 0.2741018000, 0.6876123000", \ - "0.0265048000, 0.0319192000, 0.0431388000, 0.0676013000, 0.1250092000, 0.2736912000, 0.6875814000", \ - "0.0263785000, 0.0316961000, 0.0431426000, 0.0676151000, 0.1250996000, 0.2738953000, 0.6877515000", \ - "0.0263460000, 0.0312700000, 0.0425112000, 0.0675446000, 0.1248791000, 0.2737669000, 0.6872699000", \ - "0.0260602000, 0.0313905000, 0.0427286000, 0.0674828000, 0.1254203000, 0.2742827000, 0.6865297000", \ - "0.0268472000, 0.0317734000, 0.0431054000, 0.0680941000, 0.1258688000, 0.2743810000, 0.6817616000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0282271000, 0.0356377000, 0.0544556000, 0.1033506000, 0.2330499000, 0.5791400000, 1.4985748000", \ - "0.0284258000, 0.0357094000, 0.0545315000, 0.1034046000, 0.2331298000, 0.5796755000, 1.4978766000", \ - "0.0281629000, 0.0355830000, 0.0543967000, 0.1032648000, 0.2329325000, 0.5792182000, 1.4950249000", \ - "0.0281712000, 0.0354364000, 0.0543096000, 0.1033306000, 0.2331811000, 0.5800159000, 1.4977284000", \ - "0.0281970000, 0.0354165000, 0.0542548000, 0.1031834000, 0.2332818000, 0.5789529000, 1.4964729000", \ - "0.0290072000, 0.0361287000, 0.0545337000, 0.1034083000, 0.2335658000, 0.5795573000, 1.4961411000", \ - "0.0317630000, 0.0385811000, 0.0560324000, 0.1040933000, 0.2341816000, 0.5804081000, 1.4929390000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1950637000, 0.2043715000, 0.2223318000, 0.2545851000, 0.3148578000, 0.4438505000, 0.7601402000", \ - "0.2003440000, 0.2097232000, 0.2276402000, 0.2598698000, 0.3202079000, 0.4491515000, 0.7655438000", \ - "0.2132037000, 0.2225357000, 0.2404252000, 0.2726271000, 0.3330631000, 0.4620239000, 0.7778025000", \ - "0.2447296000, 0.2540514000, 0.2719346000, 0.3041006000, 0.3644263000, 0.4934144000, 0.8097981000", \ - "0.3197405000, 0.3289397000, 0.3467300000, 0.3787919000, 0.4392673000, 0.5683272000, 0.8843610000", \ - "0.4724164000, 0.4826791000, 0.5022676000, 0.5363493000, 0.5983382000, 0.7282072000, 1.0445911000", \ - "0.7182315000, 0.7327000000, 0.7583510000, 0.7999698000, 0.8700554000, 1.0068810000, 1.3254684000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1247380000, 0.1329502000, 0.1514736000, 0.1923236000, 0.2882358000, 0.5340854000, 1.1745590000", \ - "0.1294665000, 0.1376816000, 0.1562025000, 0.1970522000, 0.2929396000, 0.5388809000, 1.1787938000", \ - "0.1404944000, 0.1487147000, 0.1672406000, 0.2080859000, 0.3041018000, 0.5496799000, 1.1911186000", \ - "0.1667898000, 0.1750152000, 0.1934845000, 0.2343205000, 0.3303486000, 0.5759893000, 1.2181649000", \ - "0.2176684000, 0.2262107000, 0.2450990000, 0.2862639000, 0.3822945000, 0.6281879000, 1.2696084000", \ - "0.2925137000, 0.3025615000, 0.3239400000, 0.3678244000, 0.4653125000, 0.7109016000, 1.3523114000", \ - "0.3812401000, 0.3948162000, 0.4223102000, 0.4736888000, 0.5748705000, 0.8215817000, 1.4614024000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0417858000, 0.0448097000, 0.0529580000, 0.0745643000, 0.1302060000, 0.2777844000, 0.6833480000", \ - "0.0419716000, 0.0447669000, 0.0531431000, 0.0744472000, 0.1301072000, 0.2774204000, 0.6893515000", \ - "0.0415597000, 0.0447578000, 0.0533595000, 0.0748801000, 0.1298895000, 0.2773987000, 0.6857795000", \ - "0.0418185000, 0.0447106000, 0.0529617000, 0.0744980000, 0.1301231000, 0.2775905000, 0.6813487000", \ - "0.0415920000, 0.0448725000, 0.0530530000, 0.0742935000, 0.1297158000, 0.2772085000, 0.6862074000", \ - "0.0536505000, 0.0552868000, 0.0609968000, 0.0800325000, 0.1332975000, 0.2784668000, 0.6877032000", \ - "0.0893717000, 0.0880352000, 0.0874449000, 0.1003682000, 0.1503789000, 0.2897110000, 0.6898217000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0284793000, 0.0363223000, 0.0557249000, 0.1036118000, 0.2326025000, 0.5800286000, 1.4999264000", \ - "0.0284659000, 0.0363275000, 0.0557474000, 0.1036425000, 0.2326055000, 0.5805254000, 1.5002211000", \ - "0.0285149000, 0.0364199000, 0.0556813000, 0.1038016000, 0.2324434000, 0.5795596000, 1.4990720000", \ - "0.0284903000, 0.0364496000, 0.0556669000, 0.1038779000, 0.2325246000, 0.5800391000, 1.4976503000", \ - "0.0301967000, 0.0379266000, 0.0572358000, 0.1045337000, 0.2327675000, 0.5802576000, 1.4994500000", \ - "0.0371443000, 0.0454290000, 0.0641315000, 0.1098295000, 0.2343849000, 0.5801038000, 1.4942982000", \ - "0.0510816000, 0.0618093000, 0.0818513000, 0.1238275000, 0.2407270000, 0.5820404000, 1.4960514000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2210752000, 0.2283849000, 0.2434517000, 0.2724010000, 0.3298120000, 0.4563088000, 0.7716783000", \ - "0.2258528000, 0.2331479000, 0.2481967000, 0.2771832000, 0.3346224000, 0.4611024000, 0.7764016000", \ - "0.2371868000, 0.2444596000, 0.2595101000, 0.2884847000, 0.3459009000, 0.4724030000, 0.7875718000", \ - "0.2639862000, 0.2713935000, 0.2863938000, 0.3154156000, 0.3728565000, 0.4992502000, 0.8150432000", \ - "0.3167716000, 0.3241612000, 0.3392407000, 0.3681791000, 0.4256297000, 0.5521534000, 0.8675116000", \ - "0.3971725000, 0.4046700000, 0.4199310000, 0.4490798000, 0.5066959000, 0.6333154000, 0.9491109000", \ - "0.4992449000, 0.5069742000, 0.5226196000, 0.5523427000, 0.6105519000, 0.7373740000, 1.0531696000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2447323000, 0.2524574000, 0.2697139000, 0.3084391000, 0.4034056000, 0.6487823000, 1.2914297000", \ - "0.2501226000, 0.2578450000, 0.2751018000, 0.3138259000, 0.4087917000, 0.6541667000, 1.2968691000", \ - "0.2631291000, 0.2708317000, 0.2879935000, 0.3267608000, 0.4217312000, 0.6670448000, 1.3077799000", \ - "0.2945092000, 0.3022459000, 0.3194645000, 0.3581831000, 0.4531484000, 0.6985197000, 1.3406868000", \ - "0.3693403000, 0.3770469000, 0.3942402000, 0.4329930000, 0.5279626000, 0.7732428000, 1.4135185000", \ - "0.5211435000, 0.5289935000, 0.5463299000, 0.5853043000, 0.6803128000, 0.9258093000, 1.5660689000", \ - "0.7700026000, 0.7782811000, 0.7962522000, 0.8357712000, 0.9310896000, 1.1768917000, 1.8182406000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0299136000, 0.0342121000, 0.0447199000, 0.0680310000, 0.1247565000, 0.2740987000, 0.6878909000", \ - "0.0301090000, 0.0342691000, 0.0449395000, 0.0677627000, 0.1249221000, 0.2735351000, 0.6867088000", \ - "0.0300013000, 0.0342231000, 0.0448616000, 0.0677330000, 0.1245462000, 0.2736554000, 0.6882043000", \ - "0.0296825000, 0.0342092000, 0.0445290000, 0.0682555000, 0.1251384000, 0.2745782000, 0.6874849000", \ - "0.0298138000, 0.0343620000, 0.0448254000, 0.0680041000, 0.1246971000, 0.2738505000, 0.6869973000", \ - "0.0304550000, 0.0349535000, 0.0454638000, 0.0692026000, 0.1244362000, 0.2748811000, 0.6882769000", \ - "0.0323415000, 0.0366727000, 0.0470255000, 0.0700260000, 0.1262816000, 0.2751237000, 0.6796310000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0273694000, 0.0347571000, 0.0528205000, 0.1006629000, 0.2314410000, 0.5795808000, 1.4974066000", \ - "0.0273688000, 0.0347548000, 0.0528258000, 0.1006596000, 0.2314143000, 0.5796185000, 1.4975248000", \ - "0.0273468000, 0.0346663000, 0.0529399000, 0.1008129000, 0.2316190000, 0.5787208000, 1.4986949000", \ - "0.0272904000, 0.0347626000, 0.0527988000, 0.1006956000, 0.2314881000, 0.5792926000, 1.4988787000", \ - "0.0274560000, 0.0346836000, 0.0529534000, 0.1008621000, 0.2315553000, 0.5792914000, 1.4929621000", \ - "0.0280490000, 0.0351954000, 0.0532655000, 0.1012057000, 0.2317124000, 0.5787171000, 1.4964961000", \ - "0.0300656000, 0.0372115000, 0.0552129000, 0.1024028000, 0.2321732000, 0.5787447000, 1.4954034000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__fahcin_1") { - leakage_power () { - value : 0.0222784000; - when : "!A&!B&CIN"; - } - leakage_power () { - value : 0.0142747000; - when : "!A&!B&!CIN"; - } - leakage_power () { - value : 0.0201665000; - when : "!A&B&CIN"; - } - leakage_power () { - value : 0.0172217000; - when : "!A&B&!CIN"; - } - leakage_power () { - value : 0.0182823000; - when : "A&!B&CIN"; - } - leakage_power () { - value : 0.0166736000; - when : "A&!B&!CIN"; - } - leakage_power () { - value : 0.0237029000; - when : "A&B&CIN"; - } - leakage_power () { - value : 0.0142838000; - when : "A&B&!CIN"; - } - area : 33.782400000; - cell_footprint : "sky130_fd_sc_hd__fahcin"; - cell_leakage_power : 0.0183604900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023020000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025790000; - } - pin ("B") { - capacitance : 0.0064330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0061760000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0066890000; - } - pin ("CIN") { - capacitance : 0.0047150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044700000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049600000; - } - pin ("COUT") { - direction : "output"; - function : "(A&!CIN) | (A&B) | (B&!CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0055675000, 0.0114178000, 0.0209417000, 0.0317423000, 0.0360750000, 0.0199052000, -0.038082700", \ - "0.0055563000, 0.0113918000, 0.0208792000, 0.0316558000, 0.0359653000, 0.0198115000, -0.038171100", \ - "0.0055384000, 0.0113557000, 0.0208150000, 0.0315408000, 0.0358000000, 0.0196204000, -0.038351600", \ - "0.0055247000, 0.0113251000, 0.0207503000, 0.0314462000, 0.0356746000, 0.0194688000, -0.038538900", \ - "0.0055039000, 0.0112844000, 0.0206733000, 0.0313041000, 0.0354869000, 0.0192449000, -0.038775700", \ - "0.0055352000, 0.0113404000, 0.0208948000, 0.0316251000, 0.0356374000, 0.0194716000, -0.038470400", \ - "0.0057553000, 0.0117970000, 0.0216065000, 0.0327531000, 0.0372392000, 0.0215644000, -0.036148800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0030802000, 0.0065716000, 0.0138161000, 0.0257224000, 0.0444567000, 0.0772045000, 0.1440451000", \ - "0.0030721000, 0.0065624000, 0.0137952000, 0.0257002000, 0.0444401000, 0.0774257000, 0.1442573000", \ - "0.0030615000, 0.0065279000, 0.0137343000, 0.0256114000, 0.0444405000, 0.0774057000, 0.1447082000", \ - "0.0030351000, 0.0064782000, 0.0136383000, 0.0254442000, 0.0441857000, 0.0770202000, 0.1444180000", \ - "0.0030153000, 0.0064311000, 0.0135433000, 0.0252565000, 0.0439239000, 0.0768671000, 0.1441221000", \ - "0.0030286000, 0.0064541000, 0.0135711000, 0.0252418000, 0.0437998000, 0.0766630000, 0.1437982000", \ - "0.0033154000, 0.0070702000, 0.0141308000, 0.0259488000, 0.0445820000, 0.0776111000, 0.1447604000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0059004000, 0.0121069000, 0.0222226000, 0.0338032000, 0.0387738000, 0.0230573000, -0.034710100", \ - "0.0058652000, 0.0120379000, 0.0220958000, 0.0336138000, 0.0385196000, 0.0227048000, -0.035090900", \ - "0.0058272000, 0.0119588000, 0.0219490000, 0.0333628000, 0.0381860000, 0.0222994000, -0.035547800", \ - "0.0057938000, 0.0118838000, 0.0218126000, 0.0331442000, 0.0379188000, 0.0220185000, -0.035808800", \ - "0.0057956000, 0.0118884000, 0.0218043000, 0.0331482000, 0.0379415000, 0.0221231000, -0.035660600", \ - "0.0059031000, 0.0121007000, 0.0222160000, 0.0337808000, 0.0388914000, 0.0233080000, -0.034287600", \ - "0.0062129000, 0.0127456000, 0.0234317000, 0.0357744000, 0.0411106000, 0.0267140000, -0.030557400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0026462000, 0.0057743000, 0.0118210000, 0.0222639000, 0.0395809000, 0.0713824000, 0.1377442000", \ - "0.0026403000, 0.0057513000, 0.0117801000, 0.0222219000, 0.0395361000, 0.0714129000, 0.1376527000", \ - "0.0026165000, 0.0057047000, 0.0116975000, 0.0220748000, 0.0393427000, 0.0711159000, 0.1374165000", \ - "0.0025864000, 0.0056361000, 0.0115597000, 0.0218190000, 0.0389998000, 0.0708562000, 0.1368714000", \ - "0.0025622000, 0.0055885000, 0.0114580000, 0.0216257000, 0.0388288000, 0.0705993000, 0.1370737000", \ - "0.0026543000, 0.0056921000, 0.0115278000, 0.0217519000, 0.0389315000, 0.0708067000, 0.1373402000", \ - "0.0029865000, 0.0063865000, 0.0128517000, 0.0238755000, 0.0415203000, 0.0740022000, 0.1407636000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0029798000, 0.0060291000, 0.0106938000, 0.0148031000, 0.0120943000, -0.009224500, -0.070190100", \ - "0.0029589000, 0.0059833000, 0.0106212000, 0.0146582000, 0.0119058000, -0.009452500, -0.070441300", \ - "0.0029278000, 0.0059196000, 0.0104960000, 0.0144881000, 0.0116607000, -0.009745400, -0.070759200", \ - "0.0028924000, 0.0058506000, 0.0103674000, 0.0142923000, 0.0114429000, -0.009977600, -0.071055100", \ - "0.0028810000, 0.0058257000, 0.0103135000, 0.0142144000, 0.0113842000, -0.009967700, -0.070980800", \ - "0.0029397000, 0.0059495000, 0.0105352000, 0.0145807000, 0.0116505000, -0.009682500, -0.070596100", \ - "0.0031584000, 0.0063998000, 0.0113766000, 0.0158986000, 0.0133803000, -0.007990800, -0.068776500"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0027334000, 0.0058974000, 0.0120564000, 0.0226068000, 0.0399283000, 0.0717082000, 0.1381574000", \ - "0.0027019000, 0.0058346000, 0.0119527000, 0.0224430000, 0.0397361000, 0.0714968000, 0.1378658000", \ - "0.0026667000, 0.0057607000, 0.0118207000, 0.0222196000, 0.0395002000, 0.0712181000, 0.1375865000", \ - "0.0026267000, 0.0056804000, 0.0116621000, 0.0219135000, 0.0391539000, 0.0708904000, 0.1371279000", \ - "0.0026167000, 0.0056495000, 0.0116261000, 0.0218966000, 0.0390190000, 0.0706951000, 0.1371749000", \ - "0.0026923000, 0.0058167000, 0.0119257000, 0.0223955000, 0.0396660000, 0.0713744000, 0.1378665000", \ - "0.0030861000, 0.0065922000, 0.0132735000, 0.0243807000, 0.0424594000, 0.0747554000, 0.1411834000"); - } - } - max_capacitance : 0.0714210000; - max_transition : 1.5153480000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.2282841000, 0.2394125000, 0.2609073000, 0.2993147000, 0.3610704000, 0.4702885000, 0.6990835000", \ - "0.2334306000, 0.2444304000, 0.2659618000, 0.3044458000, 0.3661306000, 0.4754077000, 0.7041799000", \ - "0.2457166000, 0.2567692000, 0.2782742000, 0.3167864000, 0.3784922000, 0.4877852000, 0.7166046000", \ - "0.2760357000, 0.2870245000, 0.3085475000, 0.3471005000, 0.4088412000, 0.5181730000, 0.7469780000", \ - "0.3480476000, 0.3589511000, 0.3803510000, 0.4190776000, 0.4812660000, 0.5907682000, 0.8196638000", \ - "0.4933058000, 0.5052357000, 0.5280846000, 0.5684535000, 0.6315611000, 0.7413015000, 0.9699945000", \ - "0.7297438000, 0.7446918000, 0.7728188000, 0.8199537000, 0.8885793000, 1.0023120000, 1.2320945000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1459818000, 0.1581706000, 0.1851215000, 0.2442464000, 0.3719952000, 0.5699305000, 0.9826571000", \ - "0.1504620000, 0.1626134000, 0.1896093000, 0.2487463000, 0.3765099000, 0.5746983000, 0.9875747000", \ - "0.1613700000, 0.1735794000, 0.2005151000, 0.2595744000, 0.3874326000, 0.5858762000, 0.9987188000", \ - "0.1861434000, 0.1982480000, 0.2249640000, 0.2838325000, 0.4119090000, 0.6110524000, 1.0241831000", \ - "0.2341468000, 0.2462206000, 0.2728291000, 0.3312746000, 0.4595527000, 0.6598475000, 1.0726898000", \ - "0.3024326000, 0.3154945000, 0.3431300000, 0.4020673000, 0.5306387000, 0.7315314000, 1.1448794000", \ - "0.3769298000, 0.3928275000, 0.4241072000, 0.4857599000, 0.6148451000, 0.8151817000, 1.2280273000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0531407000, 0.0610477000, 0.0772319000, 0.1096696000, 0.1710524000, 0.3057422000, 0.6258923000", \ - "0.0532727000, 0.0607929000, 0.0769602000, 0.1099500000, 0.1710167000, 0.3057261000, 0.6256369000", \ - "0.0533746000, 0.0609764000, 0.0771456000, 0.1099591000, 0.1709851000, 0.3057454000, 0.6257444000", \ - "0.0533140000, 0.0607874000, 0.0769847000, 0.1097414000, 0.1710470000, 0.3057179000, 0.6256474000", \ - "0.0534289000, 0.0612319000, 0.0775437000, 0.1099554000, 0.1712452000, 0.3057296000, 0.6256780000", \ - "0.0616509000, 0.0687692000, 0.0840138000, 0.1154912000, 0.1744595000, 0.3069951000, 0.6249489000", \ - "0.0853438000, 0.0917107000, 0.1064696000, 0.1362914000, 0.1923398000, 0.3214320000, 0.6318305000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0546314000, 0.0690501000, 0.1020112000, 0.1805354000, 0.3573387000, 0.7035963000, 1.5125746000", \ - "0.0546898000, 0.0691910000, 0.1020523000, 0.1805699000, 0.3572810000, 0.7044683000, 1.5122116000", \ - "0.0544770000, 0.0690407000, 0.1020089000, 0.1805948000, 0.3572098000, 0.7043634000, 1.5131016000", \ - "0.0545199000, 0.0690804000, 0.1020202000, 0.1805740000, 0.3575382000, 0.7041295000, 1.5137166000", \ - "0.0561824000, 0.0700896000, 0.1027854000, 0.1806098000, 0.3577373000, 0.7044177000, 1.5105370000", \ - "0.0625458000, 0.0762415000, 0.1073996000, 0.1834165000, 0.3591656000, 0.7038820000, 1.5145732000", \ - "0.0787388000, 0.0919880000, 0.1205659000, 0.1920537000, 0.3621109000, 0.7048193000, 1.5132691000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1864316000, 0.1947843000, 0.2109817000, 0.2412439000, 0.2977893000, 0.4054866000, 0.6336385000", \ - "0.1903460000, 0.1987155000, 0.2149272000, 0.2452245000, 0.3017790000, 0.4095233000, 0.6377599000", \ - "0.2009947000, 0.2093543000, 0.2256432000, 0.2560562000, 0.3126327000, 0.4204019000, 0.6486585000", \ - "0.2285739000, 0.2369497000, 0.2534076000, 0.2838514000, 0.3405254000, 0.4483380000, 0.6767614000", \ - "0.2961784000, 0.3046638000, 0.3210928000, 0.3517191000, 0.4085290000, 0.5164245000, 0.7450390000", \ - "0.4299375000, 0.4393615000, 0.4569105000, 0.4883913000, 0.5461923000, 0.6546151000, 0.8826351000", \ - "0.6380635000, 0.6497493000, 0.6708333000, 0.7071477000, 0.7696939000, 0.8811701000, 1.1103910000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1434981000, 0.1543762000, 0.1775327000, 0.2250196000, 0.3150908000, 0.4979243000, 0.9130389000", \ - "0.1481412000, 0.1589898000, 0.1822815000, 0.2299929000, 0.3202088000, 0.5031472000, 0.9188827000", \ - "0.1589221000, 0.1697797000, 0.1930672000, 0.2408835000, 0.3312390000, 0.5142707000, 0.9301607000", \ - "0.1825710000, 0.1933038000, 0.2164898000, 0.2643433000, 0.3548724000, 0.5383666000, 0.9543235000", \ - "0.2222977000, 0.2333573000, 0.2574546000, 0.3063687000, 0.3975606000, 0.5812323000, 0.9971061000", \ - "0.2722538000, 0.2835767000, 0.3079850000, 0.3578975000, 0.4495356000, 0.6323578000, 1.0480390000", \ - "0.3229990000, 0.3350105000, 0.3599219000, 0.4092978000, 0.5003669000, 0.6830401000, 1.0972508000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0530048000, 0.0609300000, 0.0768736000, 0.1086958000, 0.1711186000, 0.3061314000, 0.6262330000", \ - "0.0524937000, 0.0606197000, 0.0771046000, 0.1083673000, 0.1709641000, 0.3063557000, 0.6254932000", \ - "0.0516551000, 0.0601935000, 0.0761165000, 0.1076992000, 0.1704450000, 0.3061478000, 0.6261075000", \ - "0.0501110000, 0.0579406000, 0.0745943000, 0.1064088000, 0.1694889000, 0.3051363000, 0.6256518000", \ - "0.0477132000, 0.0561825000, 0.0729024000, 0.1050982000, 0.1684968000, 0.3046207000, 0.6255339000", \ - "0.0600341000, 0.0689225000, 0.0840688000, 0.1146100000, 0.1757238000, 0.3087923000, 0.6256142000", \ - "0.0849533000, 0.0937086000, 0.1116070000, 0.1427370000, 0.2000830000, 0.3269921000, 0.6353229000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0579466000, 0.0728473000, 0.1075383000, 0.1842121000, 0.3457414000, 0.6989271000, 1.5144450000", \ - "0.0577755000, 0.0727299000, 0.1073580000, 0.1844964000, 0.3458875000, 0.6998186000, 1.5142936000", \ - "0.0576512000, 0.0726250000, 0.1073219000, 0.1844793000, 0.3459286000, 0.6997939000, 1.5145999000", \ - "0.0574501000, 0.0725151000, 0.1071111000, 0.1845171000, 0.3457862000, 0.6990745000, 1.5149286000", \ - "0.0564311000, 0.0715778000, 0.1065967000, 0.1844832000, 0.3460194000, 0.6996065000, 1.5115235000", \ - "0.0564602000, 0.0716839000, 0.1070630000, 0.1853876000, 0.3485551000, 0.6998260000, 1.5135501000", \ - "0.0612658000, 0.0763553000, 0.1112831000, 0.1881366000, 0.3489353000, 0.7020181000, 1.5153476000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0479778000, 0.0522014000, 0.0615771000, 0.0824648000, 0.1294333000, 0.2303452000, 0.4519474000", \ - "0.0526198000, 0.0568657000, 0.0662873000, 0.0872014000, 0.1341295000, 0.2350526000, 0.4566771000", \ - "0.0638204000, 0.0680359000, 0.0773546000, 0.0981890000, 0.1451088000, 0.2460200000, 0.4676217000", \ - "0.0870825000, 0.0917468000, 0.1017664000, 0.1227676000, 0.1695921000, 0.2704960000, 0.4920465000", \ - "0.1203870000, 0.1269463000, 0.1402836000, 0.1666361000, 0.2190088000, 0.3219279000, 0.5449465000", \ - "0.1597506000, 0.1695358000, 0.1898813000, 0.2285735000, 0.3000821000, 0.4261312000, 0.6615214000", \ - "0.1953003000, 0.2098137000, 0.2401063000, 0.2994454000, 0.4085871000, 0.5925618000, 0.8975905000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0646230000, 0.0714589000, 0.0853597000, 0.1173631000, 0.1877325000, 0.3503720000, 0.7298871000", \ - "0.0698421000, 0.0762893000, 0.0909826000, 0.1226885000, 0.1931846000, 0.3558127000, 0.7353704000", \ - "0.0827463000, 0.0895803000, 0.1040214000, 0.1357382000, 0.2062162000, 0.3689270000, 0.7485673000", \ - "0.1151672000, 0.1217635000, 0.1357104000, 0.1664427000, 0.2367610000, 0.3994020000, 0.7786123000", \ - "0.1741303000, 0.1834178000, 0.2019159000, 0.2386635000, 0.3101980000, 0.4729775000, 0.8519367000", \ - "0.2651978000, 0.2790161000, 0.3079024000, 0.3620310000, 0.4581394000, 0.6344578000, 1.0173205000", \ - "0.4041980000, 0.4246843000, 0.4681988000, 0.5523776000, 0.6963913000, 0.9379194000, 1.3721837000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0323242000, 0.0369279000, 0.0485809000, 0.0774060000, 0.1418646000, 0.2817717000, 0.5995217000", \ - "0.0326083000, 0.0370947000, 0.0486629000, 0.0774452000, 0.1418788000, 0.2817660000, 0.5992570000", \ - "0.0343441000, 0.0384680000, 0.0492941000, 0.0775743000, 0.1418997000, 0.2818803000, 0.5995574000", \ - "0.0458484000, 0.0491872000, 0.0581726000, 0.0812496000, 0.1420274000, 0.2819637000, 0.6000809000", \ - "0.0723575000, 0.0758610000, 0.0845755000, 0.1043601000, 0.1535294000, 0.2837594000, 0.5994295000", \ - "0.1214955000, 0.1262300000, 0.1376651000, 0.1615145000, 0.2090852000, 0.3210534000, 0.6110555000", \ - "0.2111590000, 0.2193162000, 0.2363424000, 0.2714995000, 0.3373071000, 0.4553058000, 0.7206712000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0836400000, 0.0950385000, 0.1200957000, 0.1780679000, 0.3176804000, 0.6454339000, 1.4058220000", \ - "0.0838343000, 0.0950797000, 0.1200743000, 0.1781377000, 0.3179200000, 0.6452388000, 1.4068797000", \ - "0.0838680000, 0.0949875000, 0.1201633000, 0.1782256000, 0.3179766000, 0.6455388000, 1.4066818000", \ - "0.0925971000, 0.1027469000, 0.1254971000, 0.1807136000, 0.3187448000, 0.6458103000, 1.4079613000", \ - "0.1273324000, 0.1366034000, 0.1572849000, 0.2060294000, 0.3320627000, 0.6469089000, 1.4070262000", \ - "0.1919119000, 0.2035994000, 0.2282030000, 0.2795629000, 0.3964170000, 0.6836528000, 1.4087089000", \ - "0.2990291000, 0.3140736000, 0.3467358000, 0.4104485000, 0.5465543000, 0.8230743000, 1.4956235000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(!A&!B&!CIN) | (A&B&!CIN) | (A&!B&CIN) | (!A&B&CIN)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0594742000, 0.0585771000, 0.0563289000, 0.0488798000, 0.0263388000, -0.034989800, -0.196254000", \ - "0.0592667000, 0.0583994000, 0.0561333000, 0.0486566000, 0.0261182000, -0.035183400, -0.196423800", \ - "0.0590747000, 0.0581965000, 0.0559172000, 0.0484528000, 0.0259145000, -0.035387900, -0.196631800", \ - "0.0589434000, 0.0580474000, 0.0557961000, 0.0483470000, 0.0258050000, -0.035524900, -0.196794100", \ - "0.0588078000, 0.0579459000, 0.0556575000, 0.0481931000, 0.0256488000, -0.035642400, -0.196884200", \ - "0.0594324000, 0.0585591000, 0.0563234000, 0.0489138000, 0.0263760000, -0.034914100, -0.196173200", \ - "0.0648039000, 0.0635381000, 0.0602296000, 0.0514709000, 0.0282772000, -0.032750500, -0.193988900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0535314000, 0.0551691000, 0.0592307000, 0.0687090000, 0.0920945000, 0.1530389000, 0.3128492000", \ - "0.0534582000, 0.0551291000, 0.0592005000, 0.0686277000, 0.0920777000, 0.1535069000, 0.3142393000", \ - "0.0533234000, 0.0549568000, 0.0590205000, 0.0685030000, 0.0918834000, 0.1528137000, 0.3126354000", \ - "0.0531561000, 0.0548317000, 0.0588901000, 0.0683248000, 0.0917447000, 0.1532244000, 0.3140011000", \ - "0.0531851000, 0.0548561000, 0.0588886000, 0.0683738000, 0.0917273000, 0.1533210000, 0.3128677000", \ - "0.0535050000, 0.0552070000, 0.0593211000, 0.0687118000, 0.0921055000, 0.1530744000, 0.3127920000", \ - "0.0568644000, 0.0582013000, 0.0617046000, 0.0706977000, 0.0938230000, 0.1549715000, 0.3140276000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0586467000, 0.0578484000, 0.0555804000, 0.0482025000, 0.0257249000, -0.035620700, -0.196834000", \ - "0.0582841000, 0.0574341000, 0.0551701000, 0.0478069000, 0.0253025000, -0.036053900, -0.197375700", \ - "0.0579576000, 0.0571006000, 0.0548388000, 0.0474884000, 0.0249499000, -0.036398500, -0.197673700", \ - "0.0579985000, 0.0571636000, 0.0548738000, 0.0474885000, 0.0249639000, -0.036370300, -0.197654000", \ - "0.0587185000, 0.0578353000, 0.0555965000, 0.0481952000, 0.0256390000, -0.035763800, -0.197019400", \ - "0.0607157000, 0.0599235000, 0.0577238000, 0.0504351000, 0.0279483000, -0.033375800, -0.194618000", \ - "0.0687328000, 0.0674862000, 0.0641893000, 0.0554018000, 0.0320904000, -0.028542000, -0.189790800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0412471000, 0.0430395000, 0.0473394000, 0.0571173000, 0.0806806000, 0.1421856000, 0.3015574000", \ - "0.0411234000, 0.0429087000, 0.0472122000, 0.0570272000, 0.0805819000, 0.1413971000, 0.3011907000", \ - "0.0409794000, 0.0427740000, 0.0470332000, 0.0568727000, 0.0804450000, 0.1417982000, 0.3010732000", \ - "0.0410503000, 0.0428360000, 0.0471311000, 0.0569273000, 0.0804882000, 0.1412793000, 0.3010629000", \ - "0.0418995000, 0.0436576000, 0.0479268000, 0.0576105000, 0.0811205000, 0.1420384000, 0.3013988000", \ - "0.0452984000, 0.0466024000, 0.0499517000, 0.0593335000, 0.0826943000, 0.1437264000, 0.3046245000", \ - "0.0506319000, 0.0519665000, 0.0554902000, 0.0644227000, 0.0878614000, 0.1485726000, 0.3071332000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0031111000, 0.0073399000, 0.0149777000, 0.0225695000, 0.0155144000, -0.035124700, -0.190954600", \ - "0.0030924000, 0.0072951000, 0.0148818000, 0.0223947000, 0.0152816000, -0.035407400, -0.191269300", \ - "0.0030724000, 0.0072464000, 0.0147742000, 0.0222082000, 0.0150200000, -0.035712600, -0.191604000", \ - "0.0030447000, 0.0071790000, 0.0146274000, 0.0219517000, 0.0146707000, -0.036115400, -0.192031700", \ - "0.0030365000, 0.0071562000, 0.0145786000, 0.0218767000, 0.0145853000, -0.036206200, -0.192122300", \ - "0.0030940000, 0.0072883000, 0.0148532000, 0.0223512000, 0.0152595000, -0.035412400, -0.191298000", \ - "0.0033190000, 0.0078242000, 0.0159922000, 0.0243615000, 0.0181137000, -0.031988700, -0.187664000"); - } - related_pin : "CIN"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0008504000, 0.0022191000, 0.0057584000, 0.0147600000, 0.0377126000, 0.0978935000, 0.2585028000", \ - "0.0008353000, 0.0021853000, 0.0056794000, 0.0146233000, 0.0375455000, 0.0977406000, 0.2566669000", \ - "0.0008166000, 0.0021395000, 0.0055802000, 0.0144364000, 0.0373811000, 0.0980203000, 0.2581241000", \ - "0.0007972000, 0.0020932000, 0.0054798000, 0.0142982000, 0.0372427000, 0.0979938000, 0.2568522000", \ - "0.0007901000, 0.0020747000, 0.0054425000, 0.0142538000, 0.0373063000, 0.0981128000, 0.2582345000", \ - "0.0008171000, 0.0021369000, 0.0055886000, 0.0144375000, 0.0377643000, 0.0986248000, 0.2587162000", \ - "0.0009588000, 0.0024769000, 0.0063031000, 0.0158736000, 0.0397862000, 0.1007275000, 0.2589850000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5038680000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2215216000, 0.2283470000, 0.2426869000, 0.2710173000, 0.3289755000, 0.4596282000, 0.7894486000", \ - "0.2259713000, 0.2328140000, 0.2471008000, 0.2755184000, 0.3334514000, 0.4640513000, 0.7938328000", \ - "0.2367541000, 0.2436128000, 0.2579370000, 0.2863201000, 0.3442222000, 0.4747887000, 0.8045161000", \ - "0.2607881000, 0.2676336000, 0.2819205000, 0.3103220000, 0.3682286000, 0.4988304000, 0.8286092000", \ - "0.3068027000, 0.3136150000, 0.3279088000, 0.3563233000, 0.4141909000, 0.5447794000, 0.8745786000", \ - "0.3755075000, 0.3823609000, 0.3967776000, 0.4251563000, 0.4831018000, 0.6135901000, 0.9431640000", \ - "0.4557280000, 0.4626160000, 0.4771847000, 0.5057870000, 0.5639562000, 0.6947395000, 1.0245995000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3049101000, 0.3126487000, 0.3299183000, 0.3689684000, 0.4646446000, 0.7104446000, 1.3533011000", \ - "0.3098828000, 0.3177862000, 0.3351152000, 0.3741704000, 0.4697187000, 0.7154359000, 1.3582916000", \ - "0.3222083000, 0.3300477000, 0.3474350000, 0.3863200000, 0.4820620000, 0.7276922000, 1.3707077000", \ - "0.3526822000, 0.3603667000, 0.3776995000, 0.4167393000, 0.5124201000, 0.7581786000, 1.4011079000", \ - "0.4245861000, 0.4323586000, 0.4496977000, 0.4887323000, 0.5844009000, 0.8301883000, 1.4730546000", \ - "0.5737285000, 0.5816320000, 0.5989400000, 0.6380847000, 0.7337521000, 0.9794793000, 1.6224040000", \ - "0.8232429000, 0.8315323000, 0.8494305000, 0.8888186000, 0.9843374000, 1.2304469000, 1.8717170000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0248236000, 0.0299916000, 0.0406539000, 0.0659481000, 0.1259488000, 0.2844492000, 0.7161663000", \ - "0.0247579000, 0.0298670000, 0.0410856000, 0.0661994000, 0.1264747000, 0.2841489000, 0.7161066000", \ - "0.0248558000, 0.0295703000, 0.0406616000, 0.0656402000, 0.1263715000, 0.2843923000, 0.7157429000", \ - "0.0247699000, 0.0298796000, 0.0410875000, 0.0661412000, 0.1263909000, 0.2840740000, 0.7160654000", \ - "0.0248866000, 0.0296580000, 0.0408358000, 0.0661709000, 0.1262986000, 0.2837038000, 0.7161489000", \ - "0.0253100000, 0.0300519000, 0.0411563000, 0.0657892000, 0.1255113000, 0.2838846000, 0.7148068000", \ - "0.0266626000, 0.0317022000, 0.0422985000, 0.0671744000, 0.1272408000, 0.2845250000, 0.7121531000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0281583000, 0.0350233000, 0.0528197000, 0.1007698000, 0.2313278000, 0.5794967000, 1.4968357000", \ - "0.0284002000, 0.0350330000, 0.0528751000, 0.1010452000, 0.2316215000, 0.5781564000, 1.4946988000", \ - "0.0284137000, 0.0350395000, 0.0528676000, 0.1009707000, 0.2314287000, 0.5787386000, 1.4967297000", \ - "0.0282313000, 0.0351007000, 0.0528376000, 0.1007332000, 0.2312471000, 0.5793993000, 1.4968927000", \ - "0.0283937000, 0.0351123000, 0.0528195000, 0.1007618000, 0.2312710000, 0.5795147000, 1.4968047000", \ - "0.0289967000, 0.0355897000, 0.0531997000, 0.1009702000, 0.2313473000, 0.5787788000, 1.4966204000", \ - "0.0318242000, 0.0380844000, 0.0549212000, 0.1019581000, 0.2318487000, 0.5789471000, 1.4928688000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3448028000, 0.3519009000, 0.3666835000, 0.3956903000, 0.4539944000, 0.5849484000, 0.9153324000", \ - "0.3497277000, 0.3567844000, 0.3715158000, 0.4005734000, 0.4589344000, 0.5898246000, 0.9197044000", \ - "0.3623286000, 0.3693845000, 0.3841203000, 0.4131807000, 0.4715287000, 0.6024340000, 0.9323953000", \ - "0.3929147000, 0.4000179000, 0.4148006000, 0.4438070000, 0.5021119000, 0.6330665000, 0.9634501000", \ - "0.4657334000, 0.4728550000, 0.4876249000, 0.5166207000, 0.5749611000, 0.7059053000, 1.0360683000", \ - "0.6114140000, 0.6185157000, 0.6333066000, 0.6622400000, 0.7205375000, 0.8514465000, 1.1819061000", \ - "0.8493381000, 0.8563280000, 0.8710096000, 0.8998467000, 0.9582293000, 1.0889863000, 1.4186685000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3130251000, 0.3207614000, 0.3379592000, 0.3766059000, 0.4715403000, 0.7173279000, 1.3593481000", \ - "0.3176188000, 0.3255256000, 0.3426052000, 0.3810079000, 0.4761269000, 0.7212192000, 1.3631816000", \ - "0.3289301000, 0.3366577000, 0.3538574000, 0.3925198000, 0.4874642000, 0.7332636000, 1.3752766000", \ - "0.3544134000, 0.3622723000, 0.3793717000, 0.4177864000, 0.5128593000, 0.7580254000, 1.3993700000", \ - "0.4030263000, 0.4108179000, 0.4280578000, 0.4665695000, 0.5614240000, 0.8070378000, 1.4480454000", \ - "0.4731870000, 0.4809646000, 0.4982129000, 0.5366577000, 0.6319560000, 0.8773564000, 1.5188492000", \ - "0.5523715000, 0.5601237000, 0.5773828000, 0.6158651000, 0.7108711000, 0.9565103000, 1.5976535000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0266011000, 0.0313865000, 0.0425224000, 0.0674138000, 0.1266849000, 0.2844020000, 0.7222836000", \ - "0.0264525000, 0.0313802000, 0.0422927000, 0.0673461000, 0.1267270000, 0.2851069000, 0.7178619000", \ - "0.0264510000, 0.0313731000, 0.0422956000, 0.0672753000, 0.1266815000, 0.2850698000, 0.7171552000", \ - "0.0266056000, 0.0313868000, 0.0425266000, 0.0674163000, 0.1266637000, 0.2843964000, 0.7223731000", \ - "0.0266260000, 0.0313499000, 0.0424043000, 0.0672020000, 0.1266994000, 0.2847990000, 0.7141369000", \ - "0.0263423000, 0.0311934000, 0.0422943000, 0.0672811000, 0.1272278000, 0.2848099000, 0.7210049000", \ - "0.0264863000, 0.0312029000, 0.0423776000, 0.0670689000, 0.1266585000, 0.2843104000, 0.7181387000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0290659000, 0.0363018000, 0.0533973000, 0.1006277000, 0.2313558000, 0.5778991000, 1.4961821000", \ - "0.0294935000, 0.0359385000, 0.0534303000, 0.1007052000, 0.2314124000, 0.5794193000, 1.5009423000", \ - "0.0290703000, 0.0362802000, 0.0533797000, 0.1006372000, 0.2313268000, 0.5777649000, 1.4960514000", \ - "0.0293568000, 0.0359925000, 0.0533931000, 0.1006695000, 0.2313441000, 0.5794875000, 1.5015087000", \ - "0.0293463000, 0.0359346000, 0.0534008000, 0.1006389000, 0.2309423000, 0.5791658000, 1.4966121000", \ - "0.0292886000, 0.0359117000, 0.0532380000, 0.1004071000, 0.2310503000, 0.5794221000, 1.4982989000", \ - "0.0291253000, 0.0358474000, 0.0532106000, 0.1006655000, 0.2314259000, 0.5778885000, 1.4953105000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1994312000, 0.2063196000, 0.2208740000, 0.2497538000, 0.3085824000, 0.4401637000, 0.7702982000", \ - "0.2043681000, 0.2113002000, 0.2258634000, 0.2547147000, 0.3135575000, 0.4451171000, 0.7752441000", \ - "0.2154458000, 0.2223757000, 0.2369359000, 0.2657826000, 0.3246192000, 0.4561708000, 0.7862898000", \ - "0.2385302000, 0.2454493000, 0.2599570000, 0.2888725000, 0.3476391000, 0.4792065000, 0.8093217000", \ - "0.2846584000, 0.2916100000, 0.3061799000, 0.3350857000, 0.3938506000, 0.5253984000, 0.8554851000", \ - "0.3487663000, 0.3557087000, 0.3703144000, 0.3992162000, 0.4581510000, 0.5898170000, 0.9201109000", \ - "0.4212329000, 0.4283952000, 0.4431312000, 0.4723981000, 0.5316647000, 0.6634187000, 0.9934294000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2538863000, 0.2616095000, 0.2787513000, 0.3178183000, 0.4131552000, 0.6589874000, 1.3011260000", \ - "0.2575514000, 0.2653363000, 0.2826046000, 0.3214934000, 0.4170501000, 0.6631216000, 1.3048409000", \ - "0.2679061000, 0.2756463000, 0.2927606000, 0.3318281000, 0.4274462000, 0.6733230000, 1.3158026000", \ - "0.2943942000, 0.3021037000, 0.3192900000, 0.3582421000, 0.4535946000, 0.6991195000, 1.3419105000", \ - "0.3607920000, 0.3684891000, 0.3856517000, 0.4246036000, 0.5199937000, 0.7655608000, 1.4085517000", \ - "0.4991672000, 0.5070883000, 0.5243055000, 0.5631071000, 0.6587322000, 0.9049066000, 1.5460326000", \ - "0.7181259000, 0.7264179000, 0.7441140000, 0.7834564000, 0.8792275000, 1.1250492000, 1.7666981000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0256509000, 0.0305197000, 0.0416698000, 0.0675590000, 0.1279799000, 0.2860034000, 0.7163707000", \ - "0.0259292000, 0.0305186000, 0.0416834000, 0.0674721000, 0.1280045000, 0.2858823000, 0.7166250000", \ - "0.0259114000, 0.0305012000, 0.0416660000, 0.0674558000, 0.1279911000, 0.2858522000, 0.7166508000", \ - "0.0256658000, 0.0305553000, 0.0419606000, 0.0676626000, 0.1277553000, 0.2859358000, 0.7165789000", \ - "0.0254689000, 0.0306959000, 0.0414971000, 0.0675074000, 0.1278515000, 0.2856718000, 0.7168935000", \ - "0.0260386000, 0.0308051000, 0.0419334000, 0.0675612000, 0.1278462000, 0.2864242000, 0.7165604000", \ - "0.0274186000, 0.0321186000, 0.0436986000, 0.0678832000, 0.1284000000, 0.2866865000, 0.7132152000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0279097000, 0.0347844000, 0.0528198000, 0.1009206000, 0.2314189000, 0.5789221000, 1.4968963000", \ - "0.0279734000, 0.0349814000, 0.0526819000, 0.1007825000, 0.2311284000, 0.5795546000, 1.4983088000", \ - "0.0279731000, 0.0347711000, 0.0526810000, 0.1007759000, 0.2314101000, 0.5787552000, 1.4951069000", \ - "0.0278036000, 0.0347356000, 0.0525343000, 0.1008181000, 0.2314350000, 0.5793159000, 1.4968624000", \ - "0.0276861000, 0.0346235000, 0.0524690000, 0.1007363000, 0.2315361000, 0.5788517000, 1.4971396000", \ - "0.0285587000, 0.0353305000, 0.0530608000, 0.1008551000, 0.2315811000, 0.5794857000, 1.4976059000", \ - "0.0319379000, 0.0385091000, 0.0553058000, 0.1019596000, 0.2316581000, 0.5783996000, 1.4943915000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2573223000, 0.2644298000, 0.2790977000, 0.3081433000, 0.3664161000, 0.4972689000, 0.8274414000", \ - "0.2615591000, 0.2686016000, 0.2832713000, 0.3122712000, 0.3706175000, 0.5014691000, 0.8315231000", \ - "0.2732944000, 0.2803340000, 0.2950508000, 0.3240544000, 0.3824152000, 0.5132353000, 0.8430711000", \ - "0.3030104000, 0.3100542000, 0.3247608000, 0.3537794000, 0.4121433000, 0.5430136000, 0.8730442000", \ - "0.3741351000, 0.3812227000, 0.3960126000, 0.4249303000, 0.4833854000, 0.6142264000, 0.9445819000", \ - "0.5020198000, 0.5091242000, 0.5238842000, 0.5526997000, 0.6110312000, 0.7418590000, 1.0723564000", \ - "0.7001160000, 0.7071994000, 0.7219091000, 0.7508729000, 0.8091326000, 0.9399729000, 1.2697713000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2091025000, 0.2168337000, 0.2339654000, 0.2724621000, 0.3674112000, 0.6130866000, 1.2537914000", \ - "0.2144330000, 0.2221160000, 0.2392906000, 0.2780002000, 0.3732588000, 0.6186830000, 1.2603660000", \ - "0.2256392000, 0.2333561000, 0.2504621000, 0.2892402000, 0.3843238000, 0.6297147000, 1.2713258000", \ - "0.2495403000, 0.2572067000, 0.2743779000, 0.3130992000, 0.4083667000, 0.6537759000, 1.2953920000", \ - "0.2980267000, 0.3057514000, 0.3229269000, 0.3613451000, 0.4567190000, 0.7020219000, 1.3466805000", \ - "0.3545028000, 0.3620666000, 0.3792906000, 0.4179643000, 0.5129842000, 0.7582043000, 1.4032182000", \ - "0.4061132000, 0.4139481000, 0.4310054000, 0.4692819000, 0.5645776000, 0.8099034000, 1.4495117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0262341000, 0.0311965000, 0.0421132000, 0.0669800000, 0.1264482000, 0.2844452000, 0.7214445000", \ - "0.0263865000, 0.0314785000, 0.0426060000, 0.0666437000, 0.1264281000, 0.2846429000, 0.7145124000", \ - "0.0263065000, 0.0313036000, 0.0424634000, 0.0675600000, 0.1265638000, 0.2850330000, 0.7176740000", \ - "0.0266932000, 0.0316937000, 0.0427200000, 0.0666833000, 0.1265372000, 0.2847679000, 0.7149676000", \ - "0.0265862000, 0.0313793000, 0.0424143000, 0.0673942000, 0.1268607000, 0.2852688000, 0.7216130000", \ - "0.0263789000, 0.0311098000, 0.0421893000, 0.0669002000, 0.1269553000, 0.2856177000, 0.7194315000", \ - "0.0261945000, 0.0309695000, 0.0423440000, 0.0671040000, 0.1270191000, 0.2845162000, 0.7162468000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0285451000, 0.0352950000, 0.0530185000, 0.1004264000, 0.2310232000, 0.5785626000, 1.4970204000", \ - "0.0284480000, 0.0355703000, 0.0529160000, 0.1005373000, 0.2313972000, 0.5788784000, 1.4969065000", \ - "0.0285572000, 0.0352458000, 0.0528860000, 0.1004669000, 0.2312525000, 0.5778018000, 1.4937388000", \ - "0.0283852000, 0.0355250000, 0.0528882000, 0.1005226000, 0.2313752000, 0.5790187000, 1.4972090000", \ - "0.0283373000, 0.0351385000, 0.0527001000, 0.1005193000, 0.2307269000, 0.5794271000, 1.4983581000", \ - "0.0284900000, 0.0352530000, 0.0528978000, 0.1005238000, 0.2306196000, 0.5791489000, 1.4987515000", \ - "0.0282968000, 0.0351998000, 0.0527638000, 0.1004738000, 0.2309984000, 0.5795788000, 1.4932565000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1812918000, 0.1888957000, 0.2045697000, 0.2342581000, 0.2930936000, 0.4242387000, 0.7546737000", \ - "0.1858253000, 0.1935320000, 0.2091626000, 0.2388106000, 0.2977315000, 0.4289476000, 0.7594847000", \ - "0.1968618000, 0.2045441000, 0.2201735000, 0.2499024000, 0.3087655000, 0.4399973000, 0.7705571000", \ - "0.2191345000, 0.2267367000, 0.2423836000, 0.2721079000, 0.3310091000, 0.4621811000, 0.7926028000", \ - "0.2503060000, 0.2580647000, 0.2736369000, 0.3034305000, 0.3623641000, 0.4935262000, 0.8238752000", \ - "0.2896067000, 0.2972698000, 0.3128814000, 0.3426514000, 0.4015666000, 0.5325418000, 0.8624852000", \ - "0.3232399000, 0.3310823000, 0.3466259000, 0.3765562000, 0.4355889000, 0.5668326000, 0.8967837000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1753481000, 0.1827063000, 0.1994190000, 0.2376899000, 0.3326504000, 0.5783513000, 1.2186446000", \ - "0.1801033000, 0.1874508000, 0.2041657000, 0.2424551000, 0.3373452000, 0.5831998000, 1.2250227000", \ - "0.1927838000, 0.2002206000, 0.2169677000, 0.2552024000, 0.3498675000, 0.5947585000, 1.2361698000", \ - "0.2239782000, 0.2313343000, 0.2480749000, 0.2863058000, 0.3810051000, 0.6259894000, 1.2690642000", \ - "0.2894660000, 0.2968661000, 0.3136229000, 0.3518714000, 0.4465464000, 0.6913520000, 1.3318943000", \ - "0.3957205000, 0.4032538000, 0.4201261000, 0.4584388000, 0.5531827000, 0.7994779000, 1.4399851000", \ - "0.5644460000, 0.5722857000, 0.5896174000, 0.6282558000, 0.7233949000, 0.9688921000, 1.6095022000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0292407000, 0.0339947000, 0.0443665000, 0.0690992000, 0.1275564000, 0.2853740000, 0.7210691000", \ - "0.0294585000, 0.0339083000, 0.0444574000, 0.0685574000, 0.1281373000, 0.2859812000, 0.7202944000", \ - "0.0295160000, 0.0339850000, 0.0445357000, 0.0690520000, 0.1279880000, 0.2859744000, 0.7206268000", \ - "0.0292253000, 0.0342685000, 0.0443907000, 0.0684616000, 0.1277095000, 0.2855840000, 0.7209221000", \ - "0.0292958000, 0.0339888000, 0.0445531000, 0.0691674000, 0.1278175000, 0.2855689000, 0.7205311000", \ - "0.0294935000, 0.0342229000, 0.0446796000, 0.0684902000, 0.1277461000, 0.2849750000, 0.7184555000", \ - "0.0301063000, 0.0347347000, 0.0458261000, 0.0695094000, 0.1284851000, 0.2855981000, 0.7135997000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0252058000, 0.0323478000, 0.0505340000, 0.0990205000, 0.2305069000, 0.5802772000, 1.4994296000", \ - "0.0251680000, 0.0323160000, 0.0504892000, 0.0989822000, 0.2307935000, 0.5790632000, 1.4968561000", \ - "0.0251990000, 0.0323614000, 0.0505924000, 0.0990492000, 0.2303620000, 0.5795657000, 1.5038679000", \ - "0.0251872000, 0.0323661000, 0.0505965000, 0.0990809000, 0.2304077000, 0.5800782000, 1.4979763000", \ - "0.0253466000, 0.0324952000, 0.0506852000, 0.0990795000, 0.2302111000, 0.5794920000, 1.4965681000", \ - "0.0258429000, 0.0329870000, 0.0512118000, 0.0996207000, 0.2299812000, 0.5804821000, 1.5032912000", \ - "0.0275010000, 0.0345015000, 0.0525815000, 0.1002952000, 0.2308501000, 0.5784986000, 1.4915745000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1522528000, 0.1618742000, 0.1801170000, 0.2123391000, 0.2732998000, 0.4058489000, 0.7360748000", \ - "0.1571818000, 0.1667827000, 0.1850424000, 0.2173340000, 0.2782553000, 0.4108453000, 0.7410463000", \ - "0.1697479000, 0.1793643000, 0.1975454000, 0.2298896000, 0.2909383000, 0.4234630000, 0.7537172000", \ - "0.2001277000, 0.2097220000, 0.2278558000, 0.2602072000, 0.3212928000, 0.4538140000, 0.7840769000", \ - "0.2733222000, 0.2830672000, 0.3013342000, 0.3338345000, 0.3950457000, 0.5275617000, 0.8578054000", \ - "0.4027657000, 0.4148160000, 0.4367937000, 0.4729679000, 0.5374625000, 0.6716004000, 1.0016387000", \ - "0.6021532000, 0.6192236000, 0.6492215000, 0.6946415000, 0.7676630000, 0.9086055000, 1.2408211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1076979000, 0.1152496000, 0.1322416000, 0.1702359000, 0.2625022000, 0.5054071000, 1.1474052000", \ - "0.1123449000, 0.1198928000, 0.1368704000, 0.1748929000, 0.2672340000, 0.5101659000, 1.1525010000", \ - "0.1231752000, 0.1307277000, 0.1477011000, 0.1857636000, 0.2783097000, 0.5206952000, 1.1608429000", \ - "0.1478655000, 0.1554230000, 0.1723691000, 0.2106662000, 0.3038470000, 0.5470411000, 1.1853023000", \ - "0.1910480000, 0.1990955000, 0.2168848000, 0.2562486000, 0.3500412000, 0.5934420000, 1.2320204000", \ - "0.2499047000, 0.2595419000, 0.2798351000, 0.3218847000, 0.4170966000, 0.6608443000, 1.3007140000", \ - "0.3097163000, 0.3229263000, 0.3492924000, 0.3986483000, 0.4972588000, 0.7414231000, 1.3801285000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0393047000, 0.0439866000, 0.0536064000, 0.0764748000, 0.1331991000, 0.2883142000, 0.7154509000", \ - "0.0393086000, 0.0440073000, 0.0536782000, 0.0763749000, 0.1330182000, 0.2883212000, 0.7157464000", \ - "0.0393010000, 0.0439905000, 0.0535639000, 0.0757025000, 0.1332763000, 0.2882548000, 0.7162823000", \ - "0.0392388000, 0.0438945000, 0.0534375000, 0.0755753000, 0.1332044000, 0.2881990000, 0.7167608000", \ - "0.0407710000, 0.0454451000, 0.0541393000, 0.0766235000, 0.1333137000, 0.2881422000, 0.7176333000", \ - "0.0549161000, 0.0589745000, 0.0661531000, 0.0846457000, 0.1388948000, 0.2897063000, 0.7181734000", \ - "0.0813592000, 0.0869349000, 0.0942373000, 0.1074142000, 0.1565503000, 0.3011446000, 0.7194533000"); - } - related_pin : "CIN"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0265230000, 0.0341353000, 0.0531840000, 0.1014689000, 0.2307662000, 0.5792008000, 1.4977137000", \ - "0.0265655000, 0.0341838000, 0.0531724000, 0.1014828000, 0.2308258000, 0.5792062000, 1.4976936000", \ - "0.0265123000, 0.0341912000, 0.0531655000, 0.1016185000, 0.2310459000, 0.5788413000, 1.5000519000", \ - "0.0266593000, 0.0342588000, 0.0532709000, 0.1013877000, 0.2311549000, 0.5794401000, 1.4971511000", \ - "0.0288140000, 0.0364006000, 0.0551680000, 0.1027646000, 0.2310013000, 0.5795490000, 1.5005238000", \ - "0.0358842000, 0.0437512000, 0.0619405000, 0.1074923000, 0.2329753000, 0.5796517000, 1.4995321000", \ - "0.0494226000, 0.0590114000, 0.0789944000, 0.1208218000, 0.2376472000, 0.5792913000, 1.4920116000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__fahcon_1") { - leakage_power () { - value : 0.0206453000; - when : "!A&!B&CI"; - } - leakage_power () { - value : 0.0181386000; - when : "!A&!B&!CI"; - } - leakage_power () { - value : 0.0257888000; - when : "!A&B&CI"; - } - leakage_power () { - value : 0.0182928000; - when : "!A&B&!CI"; - } - leakage_power () { - value : 0.0231269000; - when : "A&!B&CI"; - } - leakage_power () { - value : 0.0142202000; - when : "A&!B&!CI"; - } - leakage_power () { - value : 0.0224823000; - when : "A&B&CI"; - } - leakage_power () { - value : 0.0214740000; - when : "A&B&!CI"; - } - area : 33.782400000; - cell_footprint : "sky130_fd_sc_hd__fahcon"; - cell_leakage_power : 0.0205211100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023010000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025830000; - } - pin ("B") { - capacitance : 0.0084420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080720000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088120000; - } - pin ("CI") { - capacitance : 0.0047060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044720000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049400000; - } - pin ("COUT_N") { - direction : "output"; - function : "(!A&!CI) | (!A&!B) | (!B&!CI)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0036774000, 0.0074351000, 0.0133350000, 0.0193058000, 0.0184672000, -0.000943800, -0.058681000", \ - "0.0036670000, 0.0074076000, 0.0132972000, 0.0192590000, 0.0184151000, -0.000961100, -0.058695900", \ - "0.0036579000, 0.0073922000, 0.0132592000, 0.0191937000, 0.0182989000, -0.001140500, -0.058876200", \ - "0.0036386000, 0.0073572000, 0.0131897000, 0.0190975000, 0.0181305000, -0.001351000, -0.059154000", \ - "0.0036350000, 0.0073435000, 0.0131723000, 0.0190652000, 0.0180941000, -0.001408000, -0.059225400", \ - "0.0036610000, 0.0073966000, 0.0132624000, 0.0192284000, 0.0182908000, -0.001241000, -0.059079700", \ - "0.0039381000, 0.0079503000, 0.0141853000, 0.0203713000, 0.0196336000, 0.0001236000, -0.057675600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0059768000, 0.0125083000, 0.0243200000, 0.0423211000, 0.0667363000, 0.1028123000, 0.1693296000", \ - "0.0059593000, 0.0124752000, 0.0242644000, 0.0422294000, 0.0666269000, 0.1027020000, 0.1691979000", \ - "0.0059420000, 0.0124394000, 0.0241962000, 0.0421177000, 0.0664706000, 0.1025022000, 0.1689917000", \ - "0.0059323000, 0.0124128000, 0.0241461000, 0.0420348000, 0.0663697000, 0.1023615000, 0.1688373000", \ - "0.0059148000, 0.0123855000, 0.0240920000, 0.0419592000, 0.0662452000, 0.1022225000, 0.1686583000", \ - "0.0059686000, 0.0124883000, 0.0242985000, 0.0423025000, 0.0667409000, 0.1028249000, 0.1692883000", \ - "0.0062242000, 0.0130110000, 0.0251597000, 0.0439042000, 0.0690555000, 0.1054969000, 0.1720851000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0020157000, 0.0039971000, 0.0069689000, 0.0092223000, 0.0047513000, -0.017217900, -0.076343700", \ - "0.0019891000, 0.0039498000, 0.0068625000, 0.0090233000, 0.0045120000, -0.017504100, -0.076648700", \ - "0.0019439000, 0.0038578000, 0.0066874000, 0.0087183000, 0.0040929000, -0.017995300, -0.077234200", \ - "0.0018917000, 0.0037369000, 0.0064647000, 0.0083426000, 0.0034692000, -0.018791200, -0.078047100", \ - "0.0019243000, 0.0038247000, 0.0066193000, 0.0085262000, 0.0036264000, -0.018748800, -0.078146600", \ - "0.0022142000, 0.0043887000, 0.0074819000, 0.0093614000, 0.0044195000, -0.017902700, -0.077267400", \ - "0.0026326000, 0.0052801000, 0.0091157000, 0.0121654000, 0.0081931000, -0.013974500, -0.073043200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0059974000, 0.0125360000, 0.0243996000, 0.0425619000, 0.0672958000, 0.1038466000, 0.1709385000", \ - "0.0059426000, 0.0124236000, 0.0241877000, 0.0422096000, 0.0667914000, 0.1032405000, 0.1702370000", \ - "0.0058996000, 0.0123375000, 0.0240261000, 0.0419249000, 0.0663811000, 0.1026987000, 0.1696855000", \ - "0.0058903000, 0.0123114000, 0.0239755000, 0.0418686000, 0.0662782000, 0.1025750000, 0.1695350000", \ - "0.0059386000, 0.0124213000, 0.0241815000, 0.0421871000, 0.0667341000, 0.1030181000, 0.1698907000", \ - "0.0060677000, 0.0126924000, 0.0247192000, 0.0430407000, 0.0679519000, 0.1044951000, 0.1713645000", \ - "0.0064511000, 0.0134836000, 0.0260805000, 0.0457346000, 0.0718341000, 0.1090620000, 0.1764182000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0016389000, 0.0032201000, 0.0053395000, 0.0061966000, 0.0006106000, -0.022109700, -0.081708400", \ - "0.0016164000, 0.0031717000, 0.0052475000, 0.0060528000, 0.0004300000, -0.022358800, -0.081859600", \ - "0.0015778000, 0.0030924000, 0.0051158000, 0.0058269000, 0.0001343000, -0.022647900, -0.082340700", \ - "0.0015312000, 0.0029977000, 0.0049409000, 0.0055757000, -0.000186900, -0.023072800, -0.082672500", \ - "0.0015142000, 0.0029655000, 0.0048859000, 0.0054791000, -0.000264800, -0.023122500, -0.082728600", \ - "0.0016393000, 0.0032186000, 0.0053605000, 0.0060982000, 8.8897326e-05, -0.022711700, -0.082220200", \ - "0.0019080000, 0.0037720000, 0.0063696000, 0.0077069000, 0.0021806000, -0.020553500, -0.079934300"); - } - related_pin : "CI"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0046293000, 0.0097245000, 0.0190618000, 0.0338546000, 0.0552417000, 0.0892332000, 0.1548322000", \ - "0.0045914000, 0.0096560000, 0.0189272000, 0.0336552000, 0.0550033000, 0.0889487000, 0.1544991000", \ - "0.0045565000, 0.0095808000, 0.0188021000, 0.0334622000, 0.0547306000, 0.0886689000, 0.1541164000", \ - "0.0045383000, 0.0095397000, 0.0187199000, 0.0333349000, 0.0545906000, 0.0885251000, 0.1540281000", \ - "0.0045271000, 0.0095174000, 0.0186632000, 0.0332142000, 0.0544372000, 0.0884135000, 0.1539318000", \ - "0.0046245000, 0.0097260000, 0.0190390000, 0.0337886000, 0.0551477000, 0.0892246000, 0.1548787000", \ - "0.0048527000, 0.0101806000, 0.0198546000, 0.0350054000, 0.0571805000, 0.0913092000, 0.1568943000"); - } - } - max_capacitance : 0.0686750000; - max_transition : 1.4934410000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.2340280000, 0.2402926000, 0.2528744000, 0.2775087000, 0.3236240000, 0.4160003000, 0.6206529000", \ - "0.2387260000, 0.2448733000, 0.2574487000, 0.2819349000, 0.3282566000, 0.4205588000, 0.6251646000", \ - "0.2498854000, 0.2562300000, 0.2687550000, 0.2933473000, 0.3393979000, 0.4317670000, 0.6362784000", \ - "0.2752533000, 0.2815291000, 0.2942504000, 0.3186567000, 0.3646250000, 0.4569276000, 0.6612357000", \ - "0.3236549000, 0.3297906000, 0.3424337000, 0.3668836000, 0.4127260000, 0.5049230000, 0.7093118000", \ - "0.3952041000, 0.4015963000, 0.4143547000, 0.4389888000, 0.4846635000, 0.5769738000, 0.7813048000", \ - "0.4782671000, 0.4849776000, 0.4983148000, 0.5234043000, 0.5689592000, 0.6616443000, 0.8661078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.2873398000, 0.2960358000, 0.3147364000, 0.3547916000, 0.4387008000, 0.6123290000, 0.9989410000", \ - "0.2923723000, 0.3011678000, 0.3198247000, 0.3598882000, 0.4437967000, 0.6173874000, 1.0053396000", \ - "0.3048149000, 0.3136159000, 0.3322570000, 0.3722982000, 0.4561821000, 0.6297566000, 1.0176914000", \ - "0.3354521000, 0.3440868000, 0.3628239000, 0.4028279000, 0.4866580000, 0.6601607000, 1.0481130000", \ - "0.4084939000, 0.4172877000, 0.4359032000, 0.4758551000, 0.5596157000, 0.7331312000, 1.1209839000", \ - "0.5557650000, 0.5647678000, 0.5840160000, 0.6250859000, 0.7103283000, 0.8843444000, 1.2721362000", \ - "0.7970622000, 0.8068736000, 0.8276706000, 0.8722725000, 0.9661850000, 1.1479293000, 1.5352134000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.1162238000, 0.1217979000, 0.1322824000, 0.1509841000, 0.1892028000, 0.2968306000, 0.5851988000", \ - "0.1162557000, 0.1224617000, 0.1325492000, 0.1511049000, 0.1892407000, 0.2967503000, 0.5848977000", \ - "0.1163869000, 0.1219780000, 0.1324516000, 0.1511068000, 0.1892155000, 0.2967377000, 0.5851992000", \ - "0.1174900000, 0.1225176000, 0.1331860000, 0.1515636000, 0.1895703000, 0.2967008000, 0.5854096000", \ - "0.1169062000, 0.1224220000, 0.1329597000, 0.1512643000, 0.1896013000, 0.2968711000, 0.5854648000", \ - "0.1151228000, 0.1209080000, 0.1309112000, 0.1491699000, 0.1876904000, 0.2963368000, 0.5854610000", \ - "0.1107787000, 0.1166113000, 0.1261937000, 0.1441681000, 0.1843752000, 0.2954376000, 0.5854150000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0743338000, 0.0878925000, 0.1182003000, 0.1878976000, 0.3421352000, 0.6807410000, 1.4492025000", \ - "0.0743011000, 0.0877286000, 0.1184222000, 0.1878994000, 0.3423777000, 0.6804662000, 1.4499055000", \ - "0.0743274000, 0.0877518000, 0.1184565000, 0.1879205000, 0.3423786000, 0.6804776000, 1.4499093000", \ - "0.0742303000, 0.0880187000, 0.1184713000, 0.1879847000, 0.3424384000, 0.6800511000, 1.4487549000", \ - "0.0745153000, 0.0879979000, 0.1186184000, 0.1879201000, 0.3423133000, 0.6805341000, 1.4499091000", \ - "0.0725804000, 0.0862372000, 0.1169567000, 0.1872379000, 0.3426569000, 0.6806775000, 1.4494985000", \ - "0.0694721000, 0.0837078000, 0.1146216000, 0.1861777000, 0.3463107000, 0.6887924000, 1.4526760000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.1364786000, 0.1433228000, 0.1568022000, 0.1825235000, 0.2318457000, 0.3302832000, 0.5446090000", \ - "0.1416707000, 0.1482369000, 0.1617044000, 0.1874907000, 0.2367639000, 0.3351468000, 0.5494045000", \ - "0.1520998000, 0.1587351000, 0.1721931000, 0.1979297000, 0.2472131000, 0.3455909000, 0.5598325000", \ - "0.1733337000, 0.1800360000, 0.1935029000, 0.2192882000, 0.2685452000, 0.3669981000, 0.5812491000", \ - "0.2182348000, 0.2244064000, 0.2371014000, 0.2615428000, 0.3098736000, 0.4076724000, 0.6215203000", \ - "0.2637650000, 0.2707907000, 0.2850584000, 0.3132750000, 0.3683732000, 0.4759221000, 0.6968167000", \ - "0.3026049000, 0.3118306000, 0.3318814000, 0.3756463000, 0.4657364000, 0.6313611000, 0.9205241000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.1805508000, 0.1900386000, 0.2100461000, 0.2529900000, 0.3418972000, 0.5198426000, 0.9101266000", \ - "0.1844892000, 0.1939699000, 0.2139164000, 0.2567562000, 0.3455006000, 0.5233379000, 0.9137290000", \ - "0.1962228000, 0.2055618000, 0.2253358000, 0.2678159000, 0.3560171000, 0.5335172000, 0.9237361000", \ - "0.2260888000, 0.2351175000, 0.2545547000, 0.2963897000, 0.3835729000, 0.5604578000, 0.9508999000", \ - "0.2931511000, 0.3023007000, 0.3216665000, 0.3633892000, 0.4501483000, 0.6264639000, 1.0172401000", \ - "0.4111628000, 0.4222625000, 0.4461552000, 0.4959169000, 0.5903347000, 0.7699033000, 1.1607797000", \ - "0.5988988000, 0.6157445000, 0.6534486000, 0.7314158000, 0.8689896000, 1.0971830000, 1.5309117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0846198000, 0.0893060000, 0.1006395000, 0.1220715000, 0.1714652000, 0.2948297000, 0.5990837000", \ - "0.0847454000, 0.0900721000, 0.1010525000, 0.1225279000, 0.1715845000, 0.2946577000, 0.5987876000", \ - "0.0841902000, 0.0896904000, 0.1007093000, 0.1224521000, 0.1716282000, 0.2947214000, 0.5992177000", \ - "0.0785025000, 0.0849812000, 0.0963023000, 0.1191603000, 0.1703814000, 0.2942770000, 0.5991838000", \ - "0.0787302000, 0.0840008000, 0.0948526000, 0.1173363000, 0.1683197000, 0.2934943000, 0.5989916000", \ - "0.0769744000, 0.0837082000, 0.0978686000, 0.1250510000, 0.1823211000, 0.3044076000, 0.6020204000", \ - "0.0801904000, 0.0914378000, 0.1164484000, 0.1671331000, 0.2588079000, 0.4121047000, 0.6946310000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0674124000, 0.0813448000, 0.1123726000, 0.1835344000, 0.3414867000, 0.6804123000, 1.4497832000", \ - "0.0676236000, 0.0815541000, 0.1125543000, 0.1836644000, 0.3414978000, 0.6804234000, 1.4496467000", \ - "0.0684432000, 0.0822832000, 0.1131385000, 0.1840908000, 0.3415233000, 0.6803847000, 1.4486033000", \ - "0.0698391000, 0.0835859000, 0.1144675000, 0.1849296000, 0.3416712000, 0.6804481000, 1.4486066000", \ - "0.0699727000, 0.0837199000, 0.1147204000, 0.1850477000, 0.3415758000, 0.6786776000, 1.4477349000", \ - "0.0748714000, 0.0909837000, 0.1246608000, 0.1967728000, 0.3512197000, 0.6829595000, 1.4494227000", \ - "0.0999845000, 0.1219032000, 0.1690836000, 0.2646949000, 0.4413691000, 0.7778889000, 1.4934407000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0465629000, 0.0505899000, 0.0594506000, 0.0785224000, 0.1195334000, 0.2127618000, 0.4262476000", \ - "0.0512217000, 0.0552658000, 0.0641322000, 0.0832158000, 0.1242353000, 0.2174813000, 0.4309427000", \ - "0.0624236000, 0.0664532000, 0.0752285000, 0.0942319000, 0.1352105000, 0.2284328000, 0.4419104000", \ - "0.0854986000, 0.0900019000, 0.0994847000, 0.1188512000, 0.1597921000, 0.2532613000, 0.4667880000", \ - "0.1179072000, 0.1242335000, 0.1373216000, 0.1625832000, 0.2106345000, 0.3090717000, 0.5232428000", \ - "0.1564304000, 0.1661745000, 0.1857044000, 0.2238783000, 0.2951791000, 0.4217796000, 0.6480513000", \ - "0.1898545000, 0.2045412000, 0.2343941000, 0.2948779000, 0.4143617000, 0.5917455000, 0.8852203000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0670574000, 0.0741303000, 0.0893107000, 0.1228974000, 0.2007259000, 0.3668857000, 0.7213656000", \ - "0.0722432000, 0.0792468000, 0.0944714000, 0.1281838000, 0.2061288000, 0.3722198000, 0.7271412000", \ - "0.0853439000, 0.0925155000, 0.1075616000, 0.1414227000, 0.2194940000, 0.3855984000, 0.7401312000", \ - "0.1172955000, 0.1241673000, 0.1387973000, 0.1723289000, 0.2501917000, 0.4163377000, 0.7709688000", \ - "0.1762276000, 0.1863447000, 0.2054649000, 0.2439577000, 0.3231050000, 0.4879750000, 0.8424352000", \ - "0.2674685000, 0.2821430000, 0.3125425000, 0.3693225000, 0.4724802000, 0.6423322000, 1.0042089000", \ - "0.4047892000, 0.4281802000, 0.4738037000, 0.5666856000, 0.7129421000, 0.9421237000, 1.3547184000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0309225000, 0.0351401000, 0.0457852000, 0.0707278000, 0.1292252000, 0.2652705000, 0.5766331000", \ - "0.0311463000, 0.0353509000, 0.0458869000, 0.0706662000, 0.1292390000, 0.2652086000, 0.5760423000", \ - "0.0329621000, 0.0366254000, 0.0464279000, 0.0708765000, 0.1292221000, 0.2656839000, 0.5766131000", \ - "0.0449821000, 0.0480633000, 0.0548580000, 0.0744885000, 0.1296878000, 0.2654219000, 0.5754475000", \ - "0.0718799000, 0.0755219000, 0.0830977000, 0.1000531000, 0.1455405000, 0.2703588000, 0.5770112000", \ - "0.1240322000, 0.1292168000, 0.1396927000, 0.1626506000, 0.2102733000, 0.3166656000, 0.5903382000", \ - "0.2159856000, 0.2237892000, 0.2442698000, 0.2855622000, 0.3446544000, 0.4503872000, 0.7018931000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0834861000, 0.0943942000, 0.1194660000, 0.1832598000, 0.3273278000, 0.6417640000, 1.3410633000", \ - "0.0835213000, 0.0943959000, 0.1195155000, 0.1832850000, 0.3278478000, 0.6417319000, 1.3449873000", \ - "0.0835954000, 0.0945865000, 0.1195388000, 0.1834582000, 0.3278152000, 0.6398193000, 1.3440853000", \ - "0.0925724000, 0.1024170000, 0.1248614000, 0.1857629000, 0.3279744000, 0.6403262000, 1.3436957000", \ - "0.1275004000, 0.1362818000, 0.1569167000, 0.2119274000, 0.3414981000, 0.6415934000, 1.3423521000", \ - "0.1937309000, 0.2049536000, 0.2313079000, 0.2897250000, 0.4034411000, 0.6704223000, 1.3405335000", \ - "0.3048251000, 0.3220963000, 0.3590783000, 0.4273389000, 0.5534732000, 0.8006202000, 1.4220358000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B&!CI) | (!A&B&!CI) | (!A&!B&CI) | (A&B&CI)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0381707000, 0.0371323000, 0.0345584000, 0.0268214000, 0.0042439000, -0.056029000, -0.213384700", \ - "0.0377278000, 0.0367004000, 0.0341123000, 0.0263855000, 0.0037529000, -0.056516700, -0.213867200", \ - "0.0372587000, 0.0362576000, 0.0336690000, 0.0259545000, 0.0033435000, -0.056917600, -0.214267300", \ - "0.0368339000, 0.0357961000, 0.0332345000, 0.0255158000, 0.0029658000, -0.057269100, -0.214617200", \ - "0.0369016000, 0.0358448000, 0.0332657000, 0.0255559000, 0.0030897000, -0.057119100, -0.214457100", \ - "0.0382259000, 0.0368628000, 0.0337843000, 0.0268162000, 0.0044690000, -0.055745600, -0.213087900", \ - "0.0452600000, 0.0438043000, 0.0402658000, 0.0312188000, 0.0079971000, -0.051728000, -0.209145900"); - } - related_pin : "CI"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0250403000, 0.0265996000, 0.0303605000, 0.0392478000, 0.0617347000, 0.1206736000, 0.2760021000", \ - "0.0246792000, 0.0262461000, 0.0299976000, 0.0388952000, 0.0613822000, 0.1203645000, 0.2757039000", \ - "0.0241779000, 0.0257464000, 0.0294927000, 0.0384206000, 0.0609429000, 0.1205040000, 0.2766855000", \ - "0.0236805000, 0.0252285000, 0.0289611000, 0.0378876000, 0.0605268000, 0.1197459000, 0.2750638000", \ - "0.0236951000, 0.0252337000, 0.0289152000, 0.0379018000, 0.0605974000, 0.1199417000, 0.2755544000", \ - "0.0253554000, 0.0266796000, 0.0300591000, 0.0385829000, 0.0614418000, 0.1206009000, 0.2775347000", \ - "0.0288281000, 0.0301155000, 0.0335076000, 0.0423043000, 0.0651368000, 0.1245494000, 0.2786142000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0022466000, 0.0052358000, 0.0104264000, 0.0145435000, 0.0045079000, -0.046815000, -0.199690500", \ - "0.0022401000, 0.0052269000, 0.0104060000, 0.0144993000, 0.0044437000, -0.046893400, -0.199776000", \ - "0.0022302000, 0.0052045000, 0.0103713000, 0.0144224000, 0.0043334000, -0.047018700, -0.199929300", \ - "0.0022199000, 0.0051732000, 0.0103038000, 0.0142963000, 0.0041688000, -0.047253700, -0.200134500", \ - "0.0022179000, 0.0051698000, 0.0102799000, 0.0142727000, 0.0041328000, -0.047293300, -0.200180200", \ - "0.0022363000, 0.0052112000, 0.0103749000, 0.0144329000, 0.0043607000, -0.046985300, -0.199858100", \ - "0.0023496000, 0.0054853000, 0.0109591000, 0.0154259000, 0.0058041000, -0.045524200, -0.198294800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0042857000, 0.0104724000, 0.0236157000, 0.0471082000, 0.0847237000, 0.1542073000, 0.3138867000", \ - "0.0042774000, 0.0104500000, 0.0235653000, 0.0470138000, 0.0845935000, 0.1539325000, 0.3140363000", \ - "0.0042654000, 0.0104211000, 0.0235031000, 0.0469005000, 0.0844300000, 0.1537321000, 0.3138185000", \ - "0.0042567000, 0.0104004000, 0.0234656000, 0.0468282000, 0.0843126000, 0.1537314000, 0.3149816000", \ - "0.0042478000, 0.0103804000, 0.0234117000, 0.0467391000, 0.0841824000, 0.1534711000, 0.3134953000", \ - "0.0042871000, 0.0104741000, 0.0236148000, 0.0470907000, 0.0846973000, 0.1541828000, 0.3155768000", \ - "0.0044675000, 0.0108993000, 0.0245318000, 0.0487485000, 0.0871247000, 0.1570165000, 0.3187551000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0013561000, 0.0031040000, 0.0058240000, 0.0062025000, -0.007415200, -0.061102600, -0.215246100", \ - "0.0013475000, 0.0030785000, 0.0057663000, 0.0061302000, -0.007527900, -0.061315900, -0.215416600", \ - "0.0013311000, 0.0030410000, 0.0056918000, 0.0059899000, -0.007744600, -0.061557000, -0.215684300", \ - "0.0013067000, 0.0029861000, 0.0055537000, 0.0057471000, -0.008083300, -0.061965800, -0.216123100", \ - "0.0013020000, 0.0029730000, 0.0055338000, 0.0056931000, -0.008151300, -0.062043000, -0.216167900", \ - "0.0013446000, 0.0030701000, 0.0057507000, 0.0060931000, -0.007573200, -0.061404800, -0.215474300", \ - "0.0016179000, 0.0037241000, 0.0071403000, 0.0086349000, -0.004053400, -0.057354500, -0.211674200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0043182000, 0.0105438000, 0.0237749000, 0.0474387000, 0.0851648000, 0.1548311000, 0.3150340000", \ - "0.0042780000, 0.0104551000, 0.0235774000, 0.0470780000, 0.0846394000, 0.1542427000, 0.3143525000", \ - "0.0042497000, 0.0103812000, 0.0234153000, 0.0467879000, 0.0842204000, 0.1537243000, 0.3152325000", \ - "0.0042412000, 0.0103605000, 0.0233795000, 0.0467144000, 0.0841493000, 0.1534694000, 0.3135974000", \ - "0.0042777000, 0.0104475000, 0.0235661000, 0.0470420000, 0.0846378000, 0.1540600000, 0.3142851000", \ - "0.0043710000, 0.0106715000, 0.0240449000, 0.0478826000, 0.0858943000, 0.1556159000, 0.3169024000", \ - "0.0046726000, 0.0113930000, 0.0255993000, 0.0506280000, 0.0901397000, 0.1606615000, 0.3210566000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.4685170000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.3455678000, 0.3525018000, 0.3667810000, 0.3952965000, 0.4530932000, 0.5820909000, 0.9051728000", \ - "0.3507591000, 0.3576849000, 0.3719436000, 0.4004619000, 0.4582531000, 0.5872567000, 0.9097780000", \ - "0.3630752000, 0.3699607000, 0.3843848000, 0.4127922000, 0.4706119000, 0.5997528000, 0.9228251000", \ - "0.3936038000, 0.4005290000, 0.4149599000, 0.4434565000, 0.5011398000, 0.6302884000, 0.9531991000", \ - "0.4666525000, 0.4735359000, 0.4879605000, 0.5163708000, 0.5741905000, 0.7033352000, 1.0264237000", \ - "0.6146088000, 0.6215481000, 0.6358659000, 0.6643219000, 0.7220217000, 0.8511526000, 1.1740969000", \ - "0.8574834000, 0.8644042000, 0.8787241000, 0.9069681000, 0.9645754000, 1.0935002000, 1.4162436000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.3034914000, 0.3111695000, 0.3281878000, 0.3665726000, 0.4598943000, 0.7005564000, 1.3265500000", \ - "0.3081266000, 0.3159449000, 0.3328300000, 0.3709965000, 0.4647526000, 0.7051938000, 1.3307292000", \ - "0.3192157000, 0.3270288000, 0.3440740000, 0.3823140000, 0.4757210000, 0.7165597000, 1.3425620000", \ - "0.3449238000, 0.3525941000, 0.3696073000, 0.4079823000, 0.5012040000, 0.7422873000, 1.3683269000", \ - "0.3939924000, 0.4016452000, 0.4186962000, 0.4570285000, 0.5504891000, 0.7912077000, 1.4173023000", \ - "0.4643441000, 0.4720451000, 0.4890719000, 0.5274825000, 0.6208035000, 0.8611671000, 1.4862699000", \ - "0.5437291000, 0.5514613000, 0.5685871000, 0.6068162000, 0.7003792000, 0.9409531000, 1.5649055000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0256180000, 0.0303684000, 0.0416871000, 0.0665973000, 0.1257210000, 0.2809434000, 0.7037672000", \ - "0.0258485000, 0.0305430000, 0.0418022000, 0.0657809000, 0.1257601000, 0.2809931000, 0.7034431000", \ - "0.0258497000, 0.0305253000, 0.0413975000, 0.0662990000, 0.1260307000, 0.2810915000, 0.7068374000", \ - "0.0257902000, 0.0305010000, 0.0414888000, 0.0664854000, 0.1255166000, 0.2806336000, 0.7070592000", \ - "0.0258729000, 0.0305317000, 0.0413978000, 0.0662980000, 0.1260349000, 0.2811431000, 0.7067829000", \ - "0.0258266000, 0.0304725000, 0.0416542000, 0.0656587000, 0.1254172000, 0.2804852000, 0.7068158000", \ - "0.0256097000, 0.0300065000, 0.0410439000, 0.0662396000, 0.1254680000, 0.2797883000, 0.7064910000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0289959000, 0.0356639000, 0.0530313000, 0.0999785000, 0.2279000000, 0.5678431000, 1.4610269000", \ - "0.0293930000, 0.0357122000, 0.0533525000, 0.1001401000, 0.2281869000, 0.5677435000, 1.4655527000", \ - "0.0291949000, 0.0360823000, 0.0531382000, 0.0999712000, 0.2277747000, 0.5672169000, 1.4619435000", \ - "0.0289942000, 0.0356569000, 0.0530726000, 0.0999886000, 0.2276673000, 0.5675797000, 1.4626987000", \ - "0.0289220000, 0.0360856000, 0.0531432000, 0.1000428000, 0.2276975000, 0.5675228000, 1.4625828000", \ - "0.0289386000, 0.0356290000, 0.0530684000, 0.0999063000, 0.2281670000, 0.5684402000, 1.4603806000", \ - "0.0290601000, 0.0356780000, 0.0530747000, 0.0999766000, 0.2281017000, 0.5667809000, 1.4607792000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2199660000, 0.2268620000, 0.2411852000, 0.2696609000, 0.3273470000, 0.4566209000, 0.7789150000", \ - "0.2245079000, 0.2314075000, 0.2457420000, 0.2742240000, 0.3319048000, 0.4611735000, 0.7834961000", \ - "0.2352259000, 0.2421650000, 0.2565023000, 0.2849133000, 0.3426076000, 0.4718933000, 0.7940481000", \ - "0.2593175000, 0.2661377000, 0.2805977000, 0.3089629000, 0.3666745000, 0.4959489000, 0.8180561000", \ - "0.3050221000, 0.3119326000, 0.3263970000, 0.3548987000, 0.4124400000, 0.5417656000, 0.8640968000", \ - "0.3726361000, 0.3795083000, 0.3939833000, 0.4224060000, 0.4801838000, 0.6096766000, 0.9320855000", \ - "0.4501216000, 0.4572145000, 0.4717486000, 0.5005745000, 0.5585489000, 0.6883626000, 1.0107494000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2909434000, 0.2986145000, 0.3155736000, 0.3540629000, 0.4477699000, 0.6879718000, 1.3128875000", \ - "0.2961455000, 0.3036888000, 0.3206672000, 0.3589129000, 0.4530087000, 0.6929503000, 1.3173512000", \ - "0.3084535000, 0.3159878000, 0.3329666000, 0.3712117000, 0.4653955000, 0.7052547000, 1.3296686000", \ - "0.3386625000, 0.3462707000, 0.3632621000, 0.4015750000, 0.4954288000, 0.7355196000, 1.3593592000", \ - "0.4109824000, 0.4185276000, 0.4355200000, 0.4738532000, 0.5679252000, 0.8078546000, 1.4324991000", \ - "0.5587699000, 0.5664539000, 0.5835213000, 0.6219418000, 0.7158348000, 0.9560152000, 1.5802520000", \ - "0.8036533000, 0.8118080000, 0.8291827000, 0.8678846000, 0.9617257000, 1.2022140000, 1.8268737000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0245910000, 0.0294147000, 0.0409575000, 0.0660991000, 0.1258574000, 0.2800968000, 0.7026933000", \ - "0.0246103000, 0.0294260000, 0.0410015000, 0.0661256000, 0.1257859000, 0.2801265000, 0.7024682000", \ - "0.0249626000, 0.0298669000, 0.0406429000, 0.0659148000, 0.1259900000, 0.2801307000, 0.7029785000", \ - "0.0247460000, 0.0295242000, 0.0406674000, 0.0659977000, 0.1259148000, 0.2800855000, 0.7059552000", \ - "0.0246422000, 0.0294976000, 0.0406664000, 0.0659601000, 0.1257123000, 0.2797057000, 0.7019478000", \ - "0.0253442000, 0.0299935000, 0.0410306000, 0.0663191000, 0.1258086000, 0.2802023000, 0.7016704000", \ - "0.0265050000, 0.0311106000, 0.0421436000, 0.0672559000, 0.1270014000, 0.2806576000, 0.6978977000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0271761000, 0.0341175000, 0.0517797000, 0.0992581000, 0.2282838000, 0.5674002000, 1.4566776000", \ - "0.0272111000, 0.0340706000, 0.0518078000, 0.0992762000, 0.2282155000, 0.5668583000, 1.4586864000", \ - "0.0272227000, 0.0340701000, 0.0518120000, 0.0992880000, 0.2280534000, 0.5668324000, 1.4588188000", \ - "0.0272854000, 0.0339805000, 0.0517429000, 0.0994047000, 0.2279374000, 0.5668356000, 1.4598258000", \ - "0.0272779000, 0.0340726000, 0.0518727000, 0.0994155000, 0.2276884000, 0.5665879000, 1.4597530000", \ - "0.0278121000, 0.0346814000, 0.0521974000, 0.0997710000, 0.2280263000, 0.5665468000, 1.4594781000", \ - "0.0307007000, 0.0369850000, 0.0537646000, 0.1002583000, 0.2287210000, 0.5673840000, 1.4565159000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2395787000, 0.2464872000, 0.2607528000, 0.2892459000, 0.3469516000, 0.4758350000, 0.7984017000", \ - "0.2434757000, 0.2504305000, 0.2646836000, 0.2931585000, 0.3508927000, 0.4798077000, 0.8024258000", \ - "0.2549372000, 0.2618853000, 0.2761562000, 0.3046601000, 0.3623866000, 0.4913217000, 0.8137831000", \ - "0.2842818000, 0.2912048000, 0.3054932000, 0.3340136000, 0.3917670000, 0.5207013000, 0.8431202000", \ - "0.3505608000, 0.3574805000, 0.3719252000, 0.4003004000, 0.4581246000, 0.5871488000, 0.9101356000", \ - "0.4621652000, 0.4690498000, 0.4834053000, 0.5116840000, 0.5693774000, 0.6983872000, 1.0211274000", \ - "0.6332516000, 0.6401598000, 0.6543380000, 0.6826831000, 0.7401856000, 0.8690868000, 1.1918131000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2074102000, 0.2150101000, 0.2320610000, 0.2704969000, 0.3643227000, 0.6049358000, 1.2299459000", \ - "0.2123926000, 0.2201047000, 0.2371477000, 0.2754380000, 0.3693260000, 0.6099103000, 1.2349418000", \ - "0.2227955000, 0.2305898000, 0.2475824000, 0.2858189000, 0.3798166000, 0.6203301000, 1.2475532000", \ - "0.2438007000, 0.2515498000, 0.2685370000, 0.3067296000, 0.4007383000, 0.6410911000, 1.2669241000", \ - "0.2858691000, 0.2935316000, 0.3105894000, 0.3489012000, 0.4429198000, 0.6832386000, 1.3087612000", \ - "0.3278645000, 0.3355338000, 0.3524877000, 0.3906087000, 0.4843774000, 0.7251504000, 1.3522877000", \ - "0.3575384000, 0.3651612000, 0.3821600000, 0.4202555000, 0.5139262000, 0.7549331000, 1.3787080000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0252935000, 0.0300457000, 0.0415038000, 0.0664666000, 0.1256783000, 0.2807483000, 0.7018133000", \ - "0.0256752000, 0.0304790000, 0.0412813000, 0.0662964000, 0.1256023000, 0.2809693000, 0.7082329000", \ - "0.0257197000, 0.0301040000, 0.0414562000, 0.0664372000, 0.1255994000, 0.2809725000, 0.7026560000", \ - "0.0254408000, 0.0301911000, 0.0415669000, 0.0665236000, 0.1256457000, 0.2809945000, 0.7030938000", \ - "0.0256012000, 0.0303495000, 0.0413110000, 0.0662084000, 0.1257719000, 0.2813347000, 0.7063146000", \ - "0.0252136000, 0.0298924000, 0.0410388000, 0.0656183000, 0.1256629000, 0.2801259000, 0.7006548000", \ - "0.0248141000, 0.0299395000, 0.0407033000, 0.0658155000, 0.1251558000, 0.2805204000, 0.6979232000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0283331000, 0.0355170000, 0.0527644000, 0.0997793000, 0.2281459000, 0.5677466000, 1.4635998000", \ - "0.0287940000, 0.0354720000, 0.0527193000, 0.0998132000, 0.2281571000, 0.5677009000, 1.4633974000", \ - "0.0285261000, 0.0352170000, 0.0527798000, 0.0998208000, 0.2280812000, 0.5684059000, 1.4632856000", \ - "0.0286043000, 0.0351618000, 0.0527064000, 0.0999003000, 0.2278138000, 0.5672145000, 1.4655565000", \ - "0.0282172000, 0.0348140000, 0.0524030000, 0.0996942000, 0.2278319000, 0.5672613000, 1.4656218000", \ - "0.0279902000, 0.0348935000, 0.0524157000, 0.0996817000, 0.2275265000, 0.5679304000, 1.4634555000", \ - "0.0279343000, 0.0347075000, 0.0523080000, 0.0997950000, 0.2276129000, 0.5679856000, 1.4583623000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1926087000, 0.1996062000, 0.2141371000, 0.2432325000, 0.3013219000, 0.4298857000, 0.7524872000", \ - "0.1973168000, 0.2043312000, 0.2189408000, 0.2477920000, 0.3061194000, 0.4346968000, 0.7569434000", \ - "0.2073761000, 0.2143386000, 0.2289962000, 0.2579610000, 0.3162000000, 0.4448386000, 0.7670770000", \ - "0.2282190000, 0.2352051000, 0.2497610000, 0.2788283000, 0.3369662000, 0.4655091000, 0.7880285000", \ - "0.2664969000, 0.2735478000, 0.2880406000, 0.3169985000, 0.3751994000, 0.5037890000, 0.8262933000", \ - "0.3179254000, 0.3249557000, 0.3396077000, 0.3687036000, 0.4269491000, 0.5555238000, 0.8785894000", \ - "0.3704714000, 0.3776112000, 0.3925140000, 0.4218427000, 0.4802378000, 0.6089027000, 0.9316473000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.2148381000, 0.2223570000, 0.2393618000, 0.2778227000, 0.3718643000, 0.6122267000, 1.2374156000", \ - "0.2181726000, 0.2257106000, 0.2427079000, 0.2811712000, 0.3753649000, 0.6155389000, 1.2406883000", \ - "0.2278434000, 0.2353467000, 0.2523523000, 0.2909801000, 0.3849589000, 0.6251826000, 1.2501338000", \ - "0.2535188000, 0.2610067000, 0.2779894000, 0.3164388000, 0.4102454000, 0.6504939000, 1.2751352000", \ - "0.3183779000, 0.3259101000, 0.3428287000, 0.3812724000, 0.4751163000, 0.7153024000, 1.3399166000", \ - "0.4380647000, 0.4457314000, 0.4628527000, 0.5013183000, 0.5953578000, 0.8357527000, 1.4601484000", \ - "0.6236195000, 0.6318202000, 0.6493912000, 0.6881343000, 0.7825619000, 1.0230625000, 1.6476743000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0250633000, 0.0300277000, 0.0415275000, 0.0672407000, 0.1259754000, 0.2806041000, 0.7057783000", \ - "0.0251433000, 0.0305359000, 0.0417691000, 0.0671715000, 0.1259182000, 0.2804005000, 0.7042184000", \ - "0.0255474000, 0.0304151000, 0.0417983000, 0.0672326000, 0.1259945000, 0.2796793000, 0.7026282000", \ - "0.0251313000, 0.0300686000, 0.0415100000, 0.0672026000, 0.1258344000, 0.2801430000, 0.7055118000", \ - "0.0251741000, 0.0302735000, 0.0416020000, 0.0674941000, 0.1261432000, 0.2803479000, 0.7049369000", \ - "0.0258459000, 0.0307833000, 0.0423820000, 0.0670561000, 0.1260657000, 0.2802482000, 0.7070843000", \ - "0.0266626000, 0.0318143000, 0.0431402000, 0.0683056000, 0.1264529000, 0.2805114000, 0.6985041000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0266444000, 0.0336121000, 0.0516122000, 0.0992924000, 0.2281137000, 0.5666935000, 1.4571833000", \ - "0.0266460000, 0.0335664000, 0.0515810000, 0.0993015000, 0.2281462000, 0.5664420000, 1.4581378000", \ - "0.0266043000, 0.0335789000, 0.0515784000, 0.0992333000, 0.2281915000, 0.5673022000, 1.4594510000", \ - "0.0263600000, 0.0334961000, 0.0514738000, 0.0991865000, 0.2276002000, 0.5672152000, 1.4596544000", \ - "0.0263350000, 0.0334832000, 0.0514608000, 0.0991380000, 0.2278792000, 0.5671967000, 1.4597301000", \ - "0.0278433000, 0.0346523000, 0.0523016000, 0.0994824000, 0.2282361000, 0.5672606000, 1.4568374000", \ - "0.0313821000, 0.0378286000, 0.0545106000, 0.1009296000, 0.2287935000, 0.5670917000, 1.4581476000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1522323000, 0.1609242000, 0.1777141000, 0.2082388000, 0.2671890000, 0.3965017000, 0.7193768000", \ - "0.1569790000, 0.1656637000, 0.1825093000, 0.2130656000, 0.2720207000, 0.4013667000, 0.7237530000", \ - "0.1696303000, 0.1783198000, 0.1951633000, 0.2257527000, 0.2847466000, 0.4141005000, 0.7364758000", \ - "0.2004841000, 0.2090816000, 0.2259398000, 0.2565856000, 0.3155424000, 0.4450117000, 0.7674179000", \ - "0.2716414000, 0.2804539000, 0.2973829000, 0.3282325000, 0.3874104000, 0.5169306000, 0.8397459000", \ - "0.3970738000, 0.4080788000, 0.4283015000, 0.4628622000, 0.5253831000, 0.6567945000, 0.9792263000", \ - "0.5903362000, 0.6060266000, 0.6334463000, 0.6764228000, 0.7475283000, 0.8855054000, 1.2105476000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1036420000, 0.1112574000, 0.1283404000, 0.1662024000, 0.2574331000, 0.4957095000, 1.1197003000", \ - "0.1082240000, 0.1158411000, 0.1329226000, 0.1707993000, 0.2620909000, 0.5005065000, 1.1244131000", \ - "0.1189592000, 0.1265712000, 0.1436310000, 0.1815502000, 0.2730546000, 0.5118382000, 1.1344959000", \ - "0.1433844000, 0.1509633000, 0.1679931000, 0.2060906000, 0.2979667000, 0.5362527000, 1.1611337000", \ - "0.1850624000, 0.1931992000, 0.2110421000, 0.2501193000, 0.3427403000, 0.5811341000, 1.2060488000", \ - "0.2399913000, 0.2498770000, 0.2702036000, 0.3119378000, 0.4060468000, 0.6450515000, 1.2677965000", \ - "0.2923286000, 0.3059099000, 0.3326696000, 0.3816068000, 0.4790740000, 0.7185060000, 1.3415681000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0358338000, 0.0400438000, 0.0493809000, 0.0726896000, 0.1294523000, 0.2825823000, 0.7063212000", \ - "0.0359891000, 0.0402396000, 0.0493164000, 0.0725408000, 0.1293260000, 0.2823903000, 0.7061730000", \ - "0.0359631000, 0.0402104000, 0.0493031000, 0.0725093000, 0.1293141000, 0.2823783000, 0.7061245000", \ - "0.0358514000, 0.0398215000, 0.0494573000, 0.0724016000, 0.1289915000, 0.2819368000, 0.7032170000", \ - "0.0376192000, 0.0413648000, 0.0504220000, 0.0730460000, 0.1294896000, 0.2825149000, 0.7063562000", \ - "0.0523286000, 0.0553758000, 0.0617522000, 0.0815951000, 0.1351110000, 0.2849546000, 0.7052005000", \ - "0.0822567000, 0.0849511000, 0.0891724000, 0.1028032000, 0.1524285000, 0.2951701000, 0.7038052000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0258561000, 0.0333446000, 0.0520224000, 0.0997255000, 0.2278077000, 0.5687247000, 1.4635556000", \ - "0.0257954000, 0.0333118000, 0.0519524000, 0.0997840000, 0.2278235000, 0.5686000000, 1.4636576000", \ - "0.0257683000, 0.0333531000, 0.0519797000, 0.0997035000, 0.2276110000, 0.5683686000, 1.4649821000", \ - "0.0259030000, 0.0334135000, 0.0520789000, 0.0998322000, 0.2278154000, 0.5691144000, 1.4619849000", \ - "0.0286426000, 0.0360188000, 0.0544596000, 0.1010955000, 0.2280027000, 0.5689989000, 1.4630096000", \ - "0.0359004000, 0.0437598000, 0.0614385000, 0.1060647000, 0.2298421000, 0.5689524000, 1.4685170000", \ - "0.0502344000, 0.0596752000, 0.0792921000, 0.1198371000, 0.2345358000, 0.5698861000, 1.4573953000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1784942000, 0.1858704000, 0.2008874000, 0.2300484000, 0.2877782000, 0.4164818000, 0.7394407000", \ - "0.1831579000, 0.1904501000, 0.2055741000, 0.2346384000, 0.2924448000, 0.4211308000, 0.7438625000", \ - "0.1941397000, 0.2015302000, 0.2166045000, 0.2456282000, 0.3035212000, 0.4322454000, 0.7552333000", \ - "0.2162214000, 0.2236126000, 0.2386095000, 0.2677655000, 0.3255249000, 0.4542706000, 0.7771915000", \ - "0.2472717000, 0.2546374000, 0.2696514000, 0.2988775000, 0.3567060000, 0.4854144000, 0.8085037000", \ - "0.2834157000, 0.2910187000, 0.3064765000, 0.3363599000, 0.3949408000, 0.5239179000, 0.8461267000", \ - "0.3124877000, 0.3201572000, 0.3355878000, 0.3653387000, 0.4245483000, 0.5556773000, 0.8787581000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1699434000, 0.1772287000, 0.1939194000, 0.2323800000, 0.3272922000, 0.5691799000, 1.1952405000", \ - "0.1746802000, 0.1820449000, 0.1986102000, 0.2370682000, 0.3322076000, 0.5739972000, 1.1998588000", \ - "0.1873870000, 0.1947836000, 0.2113395000, 0.2497654000, 0.3449120000, 0.5866859000, 1.2122724000", \ - "0.2184793000, 0.2258268000, 0.2423700000, 0.2808089000, 0.3759138000, 0.6176256000, 1.2429262000", \ - "0.2835322000, 0.2909154000, 0.3075478000, 0.3460262000, 0.4412506000, 0.6830920000, 1.3087882000", \ - "0.3882387000, 0.3957430000, 0.4126047000, 0.4512230000, 0.5468460000, 0.7897868000, 1.4150481000", \ - "0.5531978000, 0.5610092000, 0.5781688000, 0.6170700000, 0.7127214000, 0.9574889000, 1.5836631000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0273298000, 0.0321476000, 0.0426612000, 0.0673035000, 0.1260166000, 0.2806647000, 0.7068812000", \ - "0.0277799000, 0.0320823000, 0.0427971000, 0.0674502000, 0.1254776000, 0.2805625000, 0.6998086000", \ - "0.0274381000, 0.0320435000, 0.0427057000, 0.0672949000, 0.1260509000, 0.2807594000, 0.7068546000", \ - "0.0273856000, 0.0326201000, 0.0432833000, 0.0673518000, 0.1256589000, 0.2800255000, 0.7070484000", \ - "0.0274496000, 0.0326721000, 0.0428838000, 0.0678225000, 0.1260688000, 0.2813645000, 0.7058192000", \ - "0.0285262000, 0.0333873000, 0.0442527000, 0.0691885000, 0.1270756000, 0.2802686000, 0.7036063000", \ - "0.0292531000, 0.0340088000, 0.0453747000, 0.0695088000, 0.1294239000, 0.2831937000, 0.7021579000"); - } - related_pin : "CI"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0249220000, 0.0322714000, 0.0509266000, 0.1003403000, 0.2315960000, 0.5700238000, 1.4614693000", \ - "0.0248628000, 0.0321615000, 0.0509145000, 0.1004241000, 0.2315697000, 0.5697430000, 1.4588110000", \ - "0.0249149000, 0.0321750000, 0.0508591000, 0.1002712000, 0.2315715000, 0.5694348000, 1.4574376000", \ - "0.0248208000, 0.0321870000, 0.0508030000, 0.1004631000, 0.2317755000, 0.5698936000, 1.4594029000", \ - "0.0250354000, 0.0323285000, 0.0510410000, 0.1005917000, 0.2319882000, 0.5696503000, 1.4571981000", \ - "0.0258233000, 0.0332241000, 0.0517987000, 0.1013952000, 0.2324557000, 0.5713073000, 1.4605784000", \ - "0.0273338000, 0.0346547000, 0.0528526000, 0.1016536000, 0.2335213000, 0.5736113000, 1.4599589000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__ha_1") { - leakage_power () { - value : 0.0065943000; - when : "!A&B"; - } - leakage_power () { - value : 0.0115678000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0065599000; - when : "A&B"; - } - leakage_power () { - value : 0.0065369000; - when : "A&!B"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__ha"; - cell_leakage_power : 0.0078147000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0030260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029470000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0031050000; - } - pin ("B") { - capacitance : 0.0028380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0028440000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0028320000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0021934000, 0.0051054000, 0.0101257000, 0.0138491000, 0.0032477000, -0.048577600, -0.201638900", \ - "0.0021872000, 0.0050918000, 0.0100885000, 0.0137961000, 0.0031838000, -0.048652900, -0.201723900", \ - "0.0021765000, 0.0050677000, 0.0100375000, 0.0137016000, 0.0030342000, -0.048799700, -0.201881800", \ - "0.0021651000, 0.0050393000, 0.0099706000, 0.0135722000, 0.0029114000, -0.048870500, -0.202017000", \ - "0.0021590000, 0.0050285000, 0.0099474000, 0.0135125000, 0.0028421000, -0.048935000, -0.202093200", \ - "0.0021620000, 0.0050286000, 0.0099350000, 0.0134730000, 0.0027701000, -0.049016500, -0.202069100", \ - "0.0021858000, 0.0050783000, 0.0100108000, 0.0135782000, 0.0028631000, -0.048792000, -0.201871400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0001112000, 0.0004379000, 0.0019029000, 0.0079014000, 0.0278064000, 0.0850035000, 0.2408568000", \ - "0.0001084000, 0.0004323000, 0.0018811000, 0.0078697000, 0.0278188000, 0.0855791000, 0.2408220000", \ - "9.9547097e-05, 0.0004109000, 0.0018369000, 0.0077952000, 0.0276854000, 0.0849918000, 0.2416187000", \ - "8.8265739e-05, 0.0003859000, 0.0017873000, 0.0077083000, 0.0276340000, 0.0847781000, 0.2411612000", \ - "8.0189429e-05, 0.0003607000, 0.0017043000, 0.0075864000, 0.0274261000, 0.0848093000, 0.2410328000", \ - "7.8357423e-05, 0.0003534000, 0.0017202000, 0.0074748000, 0.0273394000, 0.0847585000, 0.2406350000", \ - "0.0001024000, 0.0004165000, 0.0018235000, 0.0077952000, 0.0277698000, 0.0853001000, 0.2387863000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0021599000, 0.0050317000, 0.0099806000, 0.0137272000, 0.0033779000, -0.048194400, -0.201222900", \ - "0.0021519000, 0.0050138000, 0.0099443000, 0.0137132000, 0.0032691000, -0.048336400, -0.201333800", \ - "0.0021414000, 0.0049909000, 0.0098891000, 0.0136034000, 0.0031153000, -0.048502000, -0.201527800", \ - "0.0021234000, 0.0049535000, 0.0097964000, 0.0134402000, 0.0028777000, -0.048782800, -0.201778800", \ - "0.0021111000, 0.0049083000, 0.0097058000, 0.0132176000, 0.0025611000, -0.049065800, -0.202096400", \ - "0.0021165000, 0.0049170000, 0.0096931000, 0.0130960000, 0.0023530000, -0.049340100, -0.202304400", \ - "0.0021275000, 0.0049321000, 0.0097059000, 0.0130766000, 0.0023270000, -0.049257900, -0.202152900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013042060, 0.0034019070, 0.0088735750, 0.0231459400, 0.0603741400, 0.1574807000"); - values("0.0001376000, 0.0005024000, 0.0020377000, 0.0081299000, 0.0282495000, 0.0861941000, 0.2417861000", \ - "0.0001329000, 0.0004929000, 0.0020250000, 0.0081294000, 0.0282094000, 0.0862476000, 0.2416215000", \ - "0.0001276000, 0.0004753000, 0.0019889000, 0.0080775000, 0.0281448000, 0.0861951000, 0.2415490000", \ - "0.0001177000, 0.0004560000, 0.0019470000, 0.0079810000, 0.0280481000, 0.0855806000, 0.2404296000", \ - "0.0001045000, 0.0004169000, 0.0018555000, 0.0078468000, 0.0278352000, 0.0858933000, 0.2403046000", \ - "0.0001201000, 0.0004512000, 0.0019326000, 0.0078285000, 0.0278395000, 0.0853763000, 0.2407443000", \ - "0.0001501000, 0.0005314000, 0.0020859000, 0.0081807000, 0.0283542000, 0.0861084000, 0.2403704000"); - } - } - max_capacitance : 0.1574810000; - max_transition : 1.5037590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1549832000, 0.1627848000, 0.1785946000, 0.2087596000, 0.2688784000, 0.3991691000, 0.7242471000", \ - "0.1600278000, 0.1678440000, 0.1834550000, 0.2136422000, 0.2738020000, 0.4041045000, 0.7292165000", \ - "0.1725391000, 0.1803245000, 0.1961487000, 0.2263652000, 0.2865650000, 0.4169173000, 0.7420423000", \ - "0.2040680000, 0.2118226000, 0.2276058000, 0.2578846000, 0.3181668000, 0.4485591000, 0.7736959000", \ - "0.2793187000, 0.2870854000, 0.3028210000, 0.3330111000, 0.3933484000, 0.5237925000, 0.8489587000", \ - "0.4349105000, 0.4442477000, 0.4627871000, 0.4965206000, 0.5596268000, 0.6908424000, 1.0159698000", \ - "0.6858491000, 0.6989569000, 0.7237966000, 0.7674738000, 0.8418767000, 0.9801676000, 1.3065526000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1013402000, 0.1095157000, 0.1274868000, 0.1670913000, 0.2635304000, 0.5099701000, 1.1541945000", \ - "0.1057889000, 0.1139350000, 0.1318732000, 0.1715464000, 0.2679175000, 0.5144485000, 1.1583031000", \ - "0.1148968000, 0.1230916000, 0.1409413000, 0.1806865000, 0.2771956000, 0.5236623000, 1.1690274000", \ - "0.1353730000, 0.1434604000, 0.1614256000, 0.2011404000, 0.2978424000, 0.5445611000, 1.1900897000", \ - "0.1730582000, 0.1817884000, 0.2005880000, 0.2411762000, 0.3383957000, 0.5853024000, 1.2282885000", \ - "0.2250436000, 0.2353564000, 0.2563681000, 0.2993803000, 0.3979343000, 0.6451575000, 1.2939243000", \ - "0.2738685000, 0.2874568000, 0.3142879000, 0.3633110000, 0.4642857000, 0.7122969000, 1.3550376000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0292531000, 0.0344553000, 0.0459727000, 0.0707862000, 0.1304828000, 0.2831624000, 0.7083690000", \ - "0.0295790000, 0.0344553000, 0.0465824000, 0.0709772000, 0.1305536000, 0.2831448000, 0.7135907000", \ - "0.0292450000, 0.0344622000, 0.0458542000, 0.0708102000, 0.1304657000, 0.2830993000, 0.7077964000", \ - "0.0292992000, 0.0345083000, 0.0458304000, 0.0708980000, 0.1304490000, 0.2828441000, 0.7083934000", \ - "0.0294966000, 0.0348123000, 0.0459342000, 0.0710009000, 0.1304927000, 0.2828260000, 0.7149474000", \ - "0.0389859000, 0.0443408000, 0.0556738000, 0.0793755000, 0.1352479000, 0.2845620000, 0.7136925000", \ - "0.0580452000, 0.0649127000, 0.0791567000, 0.1042055000, 0.1567682000, 0.2965211000, 0.7109212000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0279331000, 0.0356174000, 0.0542485000, 0.1030722000, 0.2350012000, 0.5818220000, 1.5012748000", \ - "0.0280634000, 0.0355221000, 0.0542959000, 0.1030920000, 0.2345085000, 0.5826190000, 1.5013206000", \ - "0.0279837000, 0.0354722000, 0.0541700000, 0.1030559000, 0.2344961000, 0.5829878000, 1.5029774000", \ - "0.0282444000, 0.0356733000, 0.0542415000, 0.1030660000, 0.2351435000, 0.5830856000, 1.5007086000", \ - "0.0313223000, 0.0388119000, 0.0573696000, 0.1047838000, 0.2348672000, 0.5831782000, 1.5030533000", \ - "0.0388201000, 0.0459658000, 0.0638261000, 0.1093467000, 0.2374000000, 0.5836967000, 1.5037593000", \ - "0.0533014000, 0.0621307000, 0.0810154000, 0.1218366000, 0.2426742000, 0.5844596000, 1.4966590000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.1392698000, 0.1469119000, 0.1623040000, 0.1920989000, 0.2518514000, 0.3827056000, 0.7078814000", \ - "0.1439873000, 0.1516319000, 0.1671993000, 0.1971112000, 0.2568254000, 0.3876725000, 0.7128437000", \ - "0.1567850000, 0.1644319000, 0.1799406000, 0.2096474000, 0.2694479000, 0.4003049000, 0.7254924000", \ - "0.1883025000, 0.1959074000, 0.2108623000, 0.2406589000, 0.3004124000, 0.4313134000, 0.7564837000", \ - "0.2643404000, 0.2719369000, 0.2873287000, 0.3170761000, 0.3769301000, 0.5079193000, 0.8331825000", \ - "0.4117009000, 0.4211182000, 0.4397794000, 0.4737277000, 0.5372325000, 0.6693215000, 0.9945044000", \ - "0.6504126000, 0.6628850000, 0.6878049000, 0.7323991000, 0.8084807000, 0.9484155000, 1.2750626000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0957512000, 0.1039727000, 0.1218422000, 0.1616094000, 0.2583253000, 0.5052723000, 1.1488807000", \ - "0.0999485000, 0.1081362000, 0.1261123000, 0.1658934000, 0.2626470000, 0.5095671000, 1.1535912000", \ - "0.1105340000, 0.1186243000, 0.1366161000, 0.1764206000, 0.2732711000, 0.5202536000, 1.1643011000", \ - "0.1352014000, 0.1433891000, 0.1612878000, 0.2010764000, 0.2979730000, 0.5450051000, 1.1872999000", \ - "0.1792083000, 0.1877874000, 0.2067343000, 0.2477074000, 0.3449731000, 0.5921632000, 1.2352956000", \ - "0.2338227000, 0.2446635000, 0.2666237000, 0.3097089000, 0.4081622000, 0.6561595000, 1.3037827000", \ - "0.2826784000, 0.2975116000, 0.3263647000, 0.3774469000, 0.4784901000, 0.7262410000, 1.3693877000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0277313000, 0.0324479000, 0.0442777000, 0.0685601000, 0.1287192000, 0.2834877000, 0.7142034000", \ - "0.0274776000, 0.0327147000, 0.0437787000, 0.0685803000, 0.1286203000, 0.2835238000, 0.7139448000", \ - "0.0276748000, 0.0326562000, 0.0435363000, 0.0682076000, 0.1286160000, 0.2835356000, 0.7077254000", \ - "0.0276486000, 0.0326834000, 0.0436223000, 0.0685244000, 0.1288805000, 0.2836807000, 0.7126584000", \ - "0.0281586000, 0.0332032000, 0.0445055000, 0.0686301000, 0.1289519000, 0.2834697000, 0.7126082000", \ - "0.0386099000, 0.0442613000, 0.0558452000, 0.0792426000, 0.1359168000, 0.2849002000, 0.7132795000", \ - "0.0578453000, 0.0645598000, 0.0811258000, 0.1058393000, 0.1593024000, 0.2978073000, 0.7107176000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013042100, 0.0034019100, 0.0088735700, 0.0231459000, 0.0603741000, 0.1574810000"); - values("0.0280545000, 0.0355961000, 0.0542876000, 0.1030503000, 0.2348428000, 0.5825218000, 1.4998658000", \ - "0.0281110000, 0.0355793000, 0.0542633000, 0.1030018000, 0.2347085000, 0.5828810000, 1.5012810000", \ - "0.0280319000, 0.0355744000, 0.0542705000, 0.1029936000, 0.2347210000, 0.5828767000, 1.5013546000", \ - "0.0282345000, 0.0357830000, 0.0543651000, 0.1029601000, 0.2344082000, 0.5824409000, 1.4962519000", \ - "0.0324017000, 0.0401477000, 0.0577053000, 0.1051404000, 0.2353572000, 0.5829975000, 1.4971022000", \ - "0.0426886000, 0.0497590000, 0.0667170000, 0.1104727000, 0.2378106000, 0.5830296000, 1.5012489000", \ - "0.0594059000, 0.0685281000, 0.0873623000, 0.1265234000, 0.2440916000, 0.5861326000, 1.4957371000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0015052000, 0.0035356000, 0.0068681000, 0.0079053000, -0.006599400, -0.066712800, -0.241859800", \ - "0.0014995000, 0.0035260000, 0.0068496000, 0.0078797000, -0.006655200, -0.066764000, -0.241883200", \ - "0.0014907000, 0.0035047000, 0.0067996000, 0.0078038000, -0.006785100, -0.066921600, -0.242087600", \ - "0.0014842000, 0.0034806000, 0.0067511000, 0.0077136000, -0.006898500, -0.067085800, -0.242269300", \ - "0.0014724000, 0.0034518000, 0.0066858000, 0.0075938000, -0.007118400, -0.067304300, -0.242479100", \ - "0.0014620000, 0.0034272000, 0.0066191000, 0.0074695000, -0.007234100, -0.067442700, -0.242680200", \ - "0.0014915000, 0.0035098000, 0.0067635000, 0.0078050000, -0.006915000, -0.067180000, -0.242390700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0006329000, 0.0017196000, 0.0048944000, 0.0138427000, 0.0384376000, 0.1045502000, 0.2824911000", \ - "0.0006279000, 0.0017073000, 0.0048673000, 0.0137913000, 0.0383649000, 0.1044832000, 0.2823510000", \ - "0.0006170000, 0.0016825000, 0.0048113000, 0.0136915000, 0.0382172000, 0.1043098000, 0.2821225000", \ - "0.0006086000, 0.0016579000, 0.0047513000, 0.0135784000, 0.0380605000, 0.1046641000, 0.2819065000", \ - "0.0006009000, 0.0016436000, 0.0047208000, 0.0135280000, 0.0379779000, 0.1040665000, 0.2811193000", \ - "0.0005999000, 0.0016390000, 0.0046914000, 0.0134707000, 0.0378595000, 0.1038693000, 0.2805689000", \ - "0.0006390000, 0.0017420000, 0.0048166000, 0.0135707000, 0.0381933000, 0.1040556000, 0.2811873000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0015280000, 0.0035923000, 0.0069937000, 0.0081469000, -0.006265800, -0.066330900, -0.241419500", \ - "0.0015252000, 0.0035877000, 0.0069862000, 0.0081294000, -0.006287100, -0.066334400, -0.241468000", \ - "0.0015200000, 0.0035750000, 0.0069586000, 0.0080776000, -0.006363100, -0.066447100, -0.241548000", \ - "0.0015099000, 0.0035513000, 0.0069036000, 0.0079847000, -0.006536000, -0.066579900, -0.241725800", \ - "0.0014993000, 0.0035151000, 0.0068368000, 0.0078487000, -0.006723800, -0.066835100, -0.241992600", \ - "0.0014979000, 0.0035161000, 0.0068214000, 0.0078246000, -0.006703300, -0.066825600, -0.241989500", \ - "0.0015319000, 0.0035995000, 0.0069998000, 0.0081644000, -0.006333700, -0.066413700, -0.241592200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013294860, 0.0035350670, 0.0093996470, 0.0249934000, 0.0664567700, 0.1767067000"); - values("0.0006206000, 0.0017108000, 0.0048558000, 0.0137468000, 0.0382557000, 0.1044048000, 0.2809818000", \ - "0.0006134000, 0.0016938000, 0.0048234000, 0.0137148000, 0.0382403000, 0.1043893000, 0.2823555000", \ - "0.0006030000, 0.0016660000, 0.0047697000, 0.0136008000, 0.0381104000, 0.1041871000, 0.2807145000", \ - "0.0005882000, 0.0016243000, 0.0046695000, 0.0134561000, 0.0378728000, 0.1038664000, 0.2805651000", \ - "0.0005662000, 0.0015756000, 0.0045568000, 0.0132093000, 0.0375166000, 0.1035198000, 0.2802653000", \ - "0.0005569000, 0.0015427000, 0.0044978000, 0.0131040000, 0.0373588000, 0.1037401000, 0.2812444000", \ - "0.0005867000, 0.0016062000, 0.0045436000, 0.0130816000, 0.0373738000, 0.1030322000, 0.2804703000"); - } - } - max_capacitance : 0.1767070000; - max_transition : 1.5026780000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2469392000, 0.2563823000, 0.2757736000, 0.3120057000, 0.3809705000, 0.5292639000, 0.9003345000", \ - "0.2518240000, 0.2612968000, 0.2806018000, 0.3169046000, 0.3860882000, 0.5345586000, 0.9054418000", \ - "0.2643002000, 0.2736755000, 0.2929253000, 0.3289861000, 0.3983299000, 0.5470109000, 0.9180389000", \ - "0.2918870000, 0.3013325000, 0.3206451000, 0.3569334000, 0.4259687000, 0.5743211000, 0.9452626000", \ - "0.3541113000, 0.3635343000, 0.3828198000, 0.4190909000, 0.4885120000, 0.6369448000, 1.0079355000", \ - "0.4905446000, 0.5003802000, 0.5204656000, 0.5575569000, 0.6274766000, 0.7762008000, 1.1468655000", \ - "0.7352982000, 0.7468992000, 0.7699464000, 0.8124127000, 0.8890893000, 1.0433723000, 1.4151996000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0895449000, 0.0969240000, 0.1135635000, 0.1512231000, 0.2445625000, 0.4886562000, 1.1373812000", \ - "0.0948890000, 0.1023803000, 0.1189114000, 0.1566521000, 0.2501693000, 0.4953934000, 1.1430029000", \ - "0.1054418000, 0.1128775000, 0.1295127000, 0.1672374000, 0.2604695000, 0.5048978000, 1.1526199000", \ - "0.1265947000, 0.1340006000, 0.1505236000, 0.1881745000, 0.2813781000, 0.5260088000, 1.1739301000", \ - "0.1642254000, 0.1721149000, 0.1893901000, 0.2275421000, 0.3213136000, 0.5659200000, 1.2146996000", \ - "0.2162208000, 0.2254650000, 0.2443076000, 0.2845539000, 0.3785497000, 0.6233365000, 1.2734418000", \ - "0.2641012000, 0.2764714000, 0.3007160000, 0.3460902000, 0.4417929000, 0.6873932000, 1.3345197000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0387571000, 0.0441704000, 0.0573117000, 0.0848503000, 0.1480774000, 0.3194633000, 0.7952215000", \ - "0.0385800000, 0.0446500000, 0.0577713000, 0.0847189000, 0.1487230000, 0.3195833000, 0.7963740000", \ - "0.0386580000, 0.0442508000, 0.0567754000, 0.0850722000, 0.1484398000, 0.3188903000, 0.8019458000", \ - "0.0387985000, 0.0449786000, 0.0570280000, 0.0848835000, 0.1481403000, 0.3192097000, 0.8038433000", \ - "0.0383118000, 0.0442492000, 0.0566531000, 0.0836356000, 0.1481727000, 0.3196399000, 0.7948582000", \ - "0.0413041000, 0.0473821000, 0.0597821000, 0.0868448000, 0.1497321000, 0.3194898000, 0.8048425000", \ - "0.0525217000, 0.0601447000, 0.0731373000, 0.1004156000, 0.1640027000, 0.3269551000, 0.8035484000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0239404000, 0.0307609000, 0.0482705000, 0.0949736000, 0.2235524000, 0.5711612000, 1.4993259000", \ - "0.0239887000, 0.0309003000, 0.0482447000, 0.0949175000, 0.2236634000, 0.5714432000, 1.4992344000", \ - "0.0240403000, 0.0309413000, 0.0482515000, 0.0948142000, 0.2235309000, 0.5711737000, 1.4967539000", \ - "0.0242034000, 0.0309903000, 0.0483383000, 0.0949840000, 0.2239320000, 0.5710169000, 1.4980193000", \ - "0.0268768000, 0.0337612000, 0.0505595000, 0.0959484000, 0.2242098000, 0.5722546000, 1.4997277000", \ - "0.0334547000, 0.0400024000, 0.0567460000, 0.1000391000, 0.2256469000, 0.5712481000, 1.4998016000", \ - "0.0467217000, 0.0546607000, 0.0715621000, 0.1112693000, 0.2292443000, 0.5740079000, 1.4912712000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.1930486000, 0.1995213000, 0.2130739000, 0.2400950000, 0.2974002000, 0.4372238000, 0.8055790000", \ - "0.1974861000, 0.2039657000, 0.2175475000, 0.2445270000, 0.3018732000, 0.4417841000, 0.8111432000", \ - "0.2064830000, 0.2129979000, 0.2265742000, 0.2535936000, 0.3108439000, 0.4505950000, 0.8199024000", \ - "0.2267392000, 0.2332307000, 0.2467627000, 0.2736907000, 0.3310877000, 0.4708723000, 0.8401534000", \ - "0.2672025000, 0.2737076000, 0.2872887000, 0.3143276000, 0.3716064000, 0.5114829000, 0.8805848000", \ - "0.3263328000, 0.3329256000, 0.3465742000, 0.3737334000, 0.4311747000, 0.5710815000, 0.9395487000", \ - "0.3934023000, 0.4001890000, 0.4141160000, 0.4414314000, 0.4990919000, 0.6391363000, 1.0077063000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2367835000, 0.2442152000, 0.2607158000, 0.2981553000, 0.3914454000, 0.6361062000, 1.2879474000", \ - "0.2416428000, 0.2490753000, 0.2655742000, 0.3030227000, 0.3962513000, 0.6409704000, 1.2925784000", \ - "0.2544168000, 0.2617742000, 0.2782790000, 0.3157112000, 0.4090449000, 0.6534419000, 1.3037452000", \ - "0.2859057000, 0.2932171000, 0.3096779000, 0.3471414000, 0.4404302000, 0.6851490000, 1.3374322000", \ - "0.3606848000, 0.3680357000, 0.3845112000, 0.4219594000, 0.5152991000, 0.7598726000, 1.4107929000", \ - "0.5231443000, 0.5306232000, 0.5471606000, 0.5845132000, 0.6780801000, 0.9223370000, 1.5700284000", \ - "0.7931665000, 0.8011561000, 0.8180394000, 0.8559128000, 0.9499390000, 1.1938593000, 1.8446941000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0229335000, 0.0271432000, 0.0375298000, 0.0620024000, 0.1259658000, 0.3043464000, 0.7907729000", \ - "0.0227540000, 0.0271302000, 0.0374417000, 0.0618521000, 0.1259942000, 0.3045735000, 0.7961763000", \ - "0.0226965000, 0.0271318000, 0.0376902000, 0.0619685000, 0.1260086000, 0.3055403000, 0.7958542000", \ - "0.0229766000, 0.0274990000, 0.0378025000, 0.0622386000, 0.1261348000, 0.3059876000, 0.7957911000", \ - "0.0230345000, 0.0272467000, 0.0378981000, 0.0621096000, 0.1257853000, 0.3052858000, 0.7945865000", \ - "0.0237294000, 0.0278824000, 0.0383120000, 0.0623552000, 0.1261054000, 0.3055366000, 0.7917920000", \ - "0.0243842000, 0.0293873000, 0.0390174000, 0.0633542000, 0.1266622000, 0.3056873000, 0.7900817000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0248083000, 0.0313920000, 0.0483314000, 0.0947133000, 0.2230807000, 0.5705355000, 1.4999733000", \ - "0.0248950000, 0.0314267000, 0.0483582000, 0.0947331000, 0.2232595000, 0.5703400000, 1.4990643000", \ - "0.0249148000, 0.0313350000, 0.0483246000, 0.0946831000, 0.2232469000, 0.5697955000, 1.5024234000", \ - "0.0248666000, 0.0314336000, 0.0483924000, 0.0947188000, 0.2229261000, 0.5711682000, 1.5014446000", \ - "0.0249807000, 0.0314311000, 0.0483844000, 0.0947409000, 0.2230749000, 0.5702815000, 1.5000829000", \ - "0.0257613000, 0.0320476000, 0.0488448000, 0.0950613000, 0.2235561000, 0.5710122000, 1.5012953000", \ - "0.0291309000, 0.0351902000, 0.0515088000, 0.0963038000, 0.2235515000, 0.5696264000, 1.4974034000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2329602000, 0.2425288000, 0.2616621000, 0.2977268000, 0.3670780000, 0.5157886000, 0.8868091000", \ - "0.2356508000, 0.2451034000, 0.2644735000, 0.3007466000, 0.3698159000, 0.5181595000, 0.8891410000", \ - "0.2451413000, 0.2546769000, 0.2739683000, 0.3103276000, 0.3793409000, 0.5277606000, 0.8988822000", \ - "0.2733652000, 0.2828606000, 0.3022004000, 0.3384530000, 0.4075578000, 0.5559481000, 0.9268344000", \ - "0.3427324000, 0.3521928000, 0.3713801000, 0.4077677000, 0.4768689000, 0.6255841000, 0.9967683000", \ - "0.5005219000, 0.5105146000, 0.5304067000, 0.5673124000, 0.6372160000, 0.7861264000, 1.1566467000", \ - "0.7709091000, 0.7837392000, 0.8088576000, 0.8530399000, 0.9289570000, 1.0830191000, 1.4551080000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0803997000, 0.0875159000, 0.1035729000, 0.1406980000, 0.2338133000, 0.4783257000, 1.1271656000", \ - "0.0858460000, 0.0929694000, 0.1090495000, 0.1461823000, 0.2393451000, 0.4834829000, 1.1314981000", \ - "0.0961899000, 0.1033422000, 0.1194618000, 0.1565216000, 0.2493873000, 0.4936360000, 1.1408854000", \ - "0.1161605000, 0.1233078000, 0.1394259000, 0.1764272000, 0.2695369000, 0.5132605000, 1.1630580000", \ - "0.1491754000, 0.1569396000, 0.1739104000, 0.2118227000, 0.3051416000, 0.5503946000, 1.2002327000", \ - "0.1903095000, 0.1996514000, 0.2190723000, 0.2587278000, 0.3522314000, 0.5968074000, 1.2455798000", \ - "0.2169479000, 0.2299510000, 0.2550622000, 0.3008135000, 0.3965315000, 0.6411804000, 1.2881486000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0387773000, 0.0445996000, 0.0567490000, 0.0851224000, 0.1484048000, 0.3187053000, 0.8017262000", \ - "0.0387029000, 0.0441560000, 0.0574409000, 0.0848332000, 0.1480306000, 0.3194914000, 0.7969211000", \ - "0.0384342000, 0.0442140000, 0.0574681000, 0.0836486000, 0.1486774000, 0.3192568000, 0.8029634000", \ - "0.0386611000, 0.0446615000, 0.0574966000, 0.0848542000, 0.1482081000, 0.3192908000, 0.7982320000", \ - "0.0389050000, 0.0444583000, 0.0568002000, 0.0838448000, 0.1485754000, 0.3189868000, 0.8029542000", \ - "0.0426897000, 0.0482570000, 0.0604130000, 0.0871358000, 0.1493509000, 0.3192348000, 0.8022638000", \ - "0.0611821000, 0.0677009000, 0.0809946000, 0.1062947000, 0.1644155000, 0.3267761000, 0.8079126000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0227005000, 0.0293324000, 0.0466407000, 0.0935155000, 0.2230374000, 0.5716080000, 1.4986952000", \ - "0.0227376000, 0.0293883000, 0.0466479000, 0.0935745000, 0.2229490000, 0.5719121000, 1.5022952000", \ - "0.0227103000, 0.0293789000, 0.0467404000, 0.0937018000, 0.2226058000, 0.5718400000, 1.5012713000", \ - "0.0232563000, 0.0298452000, 0.0470018000, 0.0936557000, 0.2233723000, 0.5702749000, 1.5026780000", \ - "0.0265452000, 0.0330276000, 0.0496982000, 0.0953080000, 0.2233924000, 0.5713351000, 1.4996681000", \ - "0.0342483000, 0.0406505000, 0.0568958000, 0.0996081000, 0.2249854000, 0.5698030000, 1.4962527000", \ - "0.0488386000, 0.0568649000, 0.0732062000, 0.1128697000, 0.2288947000, 0.5731469000, 1.4900331000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.1871968000, 0.1936892000, 0.2072697000, 0.2342384000, 0.2916392000, 0.4314752000, 0.8001513000", \ - "0.1915794000, 0.1980332000, 0.2115756000, 0.2385420000, 0.2959340000, 0.4357838000, 0.8047940000", \ - "0.2019948000, 0.2084668000, 0.2219819000, 0.2489352000, 0.3063223000, 0.4461728000, 0.8150945000", \ - "0.2261146000, 0.2326248000, 0.2462163000, 0.2731204000, 0.3303942000, 0.4703642000, 0.8391710000", \ - "0.2731593000, 0.2797090000, 0.2933317000, 0.3203116000, 0.3776962000, 0.5174199000, 0.8857235000", \ - "0.3369473000, 0.3434894000, 0.3572160000, 0.3843621000, 0.4417437000, 0.5813961000, 0.9508151000", \ - "0.4082716000, 0.4150816000, 0.4291645000, 0.4564905000, 0.5142905000, 0.6543390000, 1.0232504000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.2321827000, 0.2398592000, 0.2568507000, 0.2947655000, 0.3885391000, 0.6327402000, 1.2818723000", \ - "0.2371912000, 0.2448128000, 0.2618728000, 0.2998473000, 0.3936712000, 0.6384526000, 1.2873387000", \ - "0.2498254000, 0.2574944000, 0.2743858000, 0.3122544000, 0.4058877000, 0.6507709000, 1.3001762000", \ - "0.2806968000, 0.2882820000, 0.3052336000, 0.3432691000, 0.4371027000, 0.6818506000, 1.3305274000", \ - "0.3564240000, 0.3640515000, 0.3809134000, 0.4187301000, 0.5124927000, 0.7567825000, 1.4054696000", \ - "0.5118205000, 0.5195142000, 0.5365606000, 0.5745848000, 0.6684686000, 0.9136724000, 1.5622816000", \ - "0.7705979000, 0.7783963000, 0.7960302000, 0.8346638000, 0.9289772000, 1.1736141000, 1.8221278000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0229453000, 0.0271511000, 0.0376211000, 0.0618937000, 0.1259818000, 0.3044104000, 0.8004458000", \ - "0.0226955000, 0.0272247000, 0.0377117000, 0.0620031000, 0.1260280000, 0.3056666000, 0.7949211000", \ - "0.0227015000, 0.0272855000, 0.0377805000, 0.0620463000, 0.1260257000, 0.3052391000, 0.7944557000", \ - "0.0227154000, 0.0271556000, 0.0375747000, 0.0620380000, 0.1258600000, 0.3052696000, 0.8002394000", \ - "0.0231056000, 0.0274698000, 0.0378811000, 0.0622184000, 0.1257095000, 0.3056042000, 0.7903424000", \ - "0.0233958000, 0.0278258000, 0.0382326000, 0.0624349000, 0.1262654000, 0.3049863000, 0.7960287000", \ - "0.0246944000, 0.0291944000, 0.0394442000, 0.0641327000, 0.1269437000, 0.3049085000, 0.7868471000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013294900, 0.0035350700, 0.0093996500, 0.0249934000, 0.0664568000, 0.1767070000"); - values("0.0258370000, 0.0324538000, 0.0496658000, 0.0958268000, 0.2239182000, 0.5718870000, 1.4949597000", \ - "0.0258360000, 0.0324920000, 0.0496104000, 0.0959117000, 0.2240404000, 0.5699366000, 1.5014796000", \ - "0.0256245000, 0.0323806000, 0.0496259000, 0.0959598000, 0.2241529000, 0.5722910000, 1.5002759000", \ - "0.0257456000, 0.0326016000, 0.0495360000, 0.0959109000, 0.2241090000, 0.5699951000, 1.5013164000", \ - "0.0256470000, 0.0324945000, 0.0497374000, 0.0959822000, 0.2238529000, 0.5719527000, 1.4963178000", \ - "0.0266902000, 0.0331438000, 0.0501197000, 0.0964344000, 0.2244898000, 0.5711691000, 1.5008667000", \ - "0.0295406000, 0.0363098000, 0.0524767000, 0.0974012000, 0.2248529000, 0.5704255000, 1.4954329000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__ha_2") { - leakage_power () { - value : 0.0054882000; - when : "!A&B"; - } - leakage_power () { - value : 0.0083985000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0055881000; - when : "A&B"; - } - leakage_power () { - value : 0.0053729000; - when : "A&!B"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__ha"; - cell_leakage_power : 0.0062119190; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0034790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033550000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036040000; - } - pin ("B") { - capacitance : 0.0032770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032720000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0032820000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0022962000, 0.0060327000, 0.0134369000, 0.0198270000, 0.0018707000, -0.094264700, -0.402505300", \ - "0.0022964000, 0.0060272000, 0.0134222000, 0.0198223000, 0.0017883000, -0.094345600, -0.402646200", \ - "0.0022872000, 0.0060058000, 0.0133737000, 0.0196883000, 0.0017094000, -0.094443000, -0.402702700", \ - "0.0022812000, 0.0059808000, 0.0133215000, 0.0196272000, 0.0015345000, -0.094596200, -0.402902800", \ - "0.0022796000, 0.0059748000, 0.0132794000, 0.0194927000, 0.0014456000, -0.094742800, -0.403003100", \ - "0.0022945000, 0.0060187000, 0.0133211000, 0.0195179000, 0.0013739000, -0.094716900, -0.402989200", \ - "0.0023255000, 0.0060964000, 0.0134473000, 0.0196274000, 0.0015146000, -0.094539500, -0.402795900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0002562000, 0.0008566000, 0.0032198000, 0.0127988000, 0.0470200000, 0.1519640000, 0.4624377000", \ - "0.0002498000, 0.0008472000, 0.0031979000, 0.0128066000, 0.0469075000, 0.1510781000, 0.4594262000", \ - "0.0002476000, 0.0008349000, 0.0031610000, 0.0126589000, 0.0470084000, 0.1516799000, 0.4630064000", \ - "0.0002355000, 0.0007968000, 0.0030820000, 0.0126045000, 0.0467475000, 0.1515834000, 0.4611638000", \ - "0.0002356000, 0.0007951000, 0.0030617000, 0.0124278000, 0.0465408000, 0.1511917000, 0.4606815000", \ - "0.0002325000, 0.0007871000, 0.0030852000, 0.0124857000, 0.0462185000, 0.1510787000, 0.4611646000", \ - "0.0002864000, 0.0009129000, 0.0033099000, 0.0130336000, 0.0468019000, 0.1516190000, 0.4608241000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0022858000, 0.0059973000, 0.0133913000, 0.0198908000, 0.0022245000, -0.093547200, -0.401638700", \ - "0.0022827000, 0.0059906000, 0.0133635000, 0.0198739000, 0.0022273000, -0.093605800, -0.401682400", \ - "0.0022742000, 0.0059649000, 0.0133027000, 0.0197373000, 0.0019993000, -0.093814300, -0.401922800", \ - "0.0022606000, 0.0059339000, 0.0132122000, 0.0195328000, 0.0017187000, -0.094126800, -0.402237400", \ - "0.0022487000, 0.0058940000, 0.0131002000, 0.0192871000, 0.0013031000, -0.094527400, -0.402616900", \ - "0.0022511000, 0.0058923000, 0.0130512000, 0.0191369000, 0.0009327000, -0.094934100, -0.403015800", \ - "0.0022813000, 0.0059633000, 0.0131627000, 0.0191077000, 0.0009025000, -0.094962300, -0.402856200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0002960000, 0.0009713000, 0.0034974000, 0.0133936000, 0.0478724000, 0.1522088000, 0.4607072000", \ - "0.0002959000, 0.0009632000, 0.0034659000, 0.0133311000, 0.0477178000, 0.1529674000, 0.4637584000", \ - "0.0002912000, 0.0009541000, 0.0034481000, 0.0132269000, 0.0478703000, 0.1527483000, 0.4620326000", \ - "0.0002792000, 0.0009142000, 0.0033648000, 0.0131407000, 0.0474500000, 0.1527309000, 0.4635426000", \ - "0.0002783000, 0.0009116000, 0.0033182000, 0.0129299000, 0.0473349000, 0.1524448000, 0.4633218000", \ - "0.0002782000, 0.0009089000, 0.0032997000, 0.0129425000, 0.0472653000, 0.1522060000, 0.4617817000", \ - "0.0003483000, 0.0010895000, 0.0037768000, 0.0138357000, 0.0478732000, 0.1531105000, 0.4612217000"); - } - } - max_capacitance : 0.2957250000; - max_transition : 1.5019860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1427091000, 0.1487013000, 0.1618252000, 0.1876937000, 0.2389345000, 0.3560010000, 0.6670897000", \ - "0.1481905000, 0.1541272000, 0.1672818000, 0.1931531000, 0.2444563000, 0.3614813000, 0.6725490000", \ - "0.1615659000, 0.1675259000, 0.1806438000, 0.2065357000, 0.2578343000, 0.3749210000, 0.6859844000", \ - "0.1934243000, 0.1993026000, 0.2124445000, 0.2382835000, 0.2896154000, 0.4066927000, 0.7177945000", \ - "0.2694804000, 0.2754060000, 0.2884533000, 0.3142930000, 0.3656263000, 0.4828049000, 0.7939943000", \ - "0.4196434000, 0.4270323000, 0.4428687000, 0.4727583000, 0.5279243000, 0.6467412000, 0.9577429000", \ - "0.6619722000, 0.6717479000, 0.6929605000, 0.7330723000, 0.8015407000, 0.9305531000, 1.2441009000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1241079000, 0.1314257000, 0.1480819000, 0.1843537000, 0.2708165000, 0.5063102000, 1.1827520000", \ - "0.1283303000, 0.1356391000, 0.1523003000, 0.1887182000, 0.2751357000, 0.5107968000, 1.1866119000", \ - "0.1375148000, 0.1448166000, 0.1614025000, 0.1976129000, 0.2842118000, 0.5198697000, 1.1960735000", \ - "0.1580132000, 0.1653405000, 0.1820191000, 0.2183372000, 0.3048291000, 0.5405688000, 1.2178621000", \ - "0.2004757000, 0.2081204000, 0.2254692000, 0.2622642000, 0.3491155000, 0.5850581000, 1.2657512000", \ - "0.2654015000, 0.2744215000, 0.2939835000, 0.3339691000, 0.4229959000, 0.6599051000, 1.3368644000", \ - "0.3393545000, 0.3510330000, 0.3760462000, 0.4234420000, 0.5180397000, 0.7554549000, 1.4305847000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0253827000, 0.0288372000, 0.0372146000, 0.0564369000, 0.1030059000, 0.2351812000, 0.6430242000", \ - "0.0251100000, 0.0288312000, 0.0372666000, 0.0560692000, 0.1029518000, 0.2353887000, 0.6400788000", \ - "0.0250983000, 0.0288266000, 0.0372085000, 0.0565758000, 0.1029665000, 0.2351047000, 0.6427435000", \ - "0.0250748000, 0.0292065000, 0.0372734000, 0.0561501000, 0.1029725000, 0.2353945000, 0.6398321000", \ - "0.0254751000, 0.0292373000, 0.0375880000, 0.0566142000, 0.1030460000, 0.2353753000, 0.6437943000", \ - "0.0350837000, 0.0392883000, 0.0482481000, 0.0662009000, 0.1095748000, 0.2372078000, 0.6403451000", \ - "0.0540313000, 0.0599087000, 0.0708003000, 0.0921556000, 0.1345238000, 0.2528950000, 0.6410656000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0273987000, 0.0332149000, 0.0475801000, 0.0852209000, 0.1959728000, 0.5261275000, 1.4947235000", \ - "0.0277828000, 0.0334629000, 0.0475277000, 0.0852178000, 0.1961257000, 0.5269502000, 1.4976855000", \ - "0.0274171000, 0.0332722000, 0.0475298000, 0.0852630000, 0.1959742000, 0.5270063000, 1.5008409000", \ - "0.0274672000, 0.0330084000, 0.0475715000, 0.0849773000, 0.1959850000, 0.5254409000, 1.4966784000", \ - "0.0296428000, 0.0355875000, 0.0493489000, 0.0867066000, 0.1965219000, 0.5270521000, 1.4997976000", \ - "0.0364563000, 0.0424381000, 0.0572686000, 0.0930668000, 0.2005540000, 0.5280579000, 1.5019862000", \ - "0.0499090000, 0.0574493000, 0.0736869000, 0.1086901000, 0.2087267000, 0.5302618000, 1.4934199000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1323193000, 0.1380986000, 0.1508758000, 0.1759637000, 0.2263210000, 0.3426986000, 0.6539126000", \ - "0.1376323000, 0.1434760000, 0.1562585000, 0.1817372000, 0.2319399000, 0.3483371000, 0.6594866000", \ - "0.1509226000, 0.1566758000, 0.1694539000, 0.1947686000, 0.2449258000, 0.3613271000, 0.6725518000", \ - "0.1823661000, 0.1881195000, 0.2008309000, 0.2257962000, 0.2761882000, 0.3926118000, 0.7038528000", \ - "0.2580594000, 0.2638144000, 0.2764730000, 0.3017887000, 0.3521217000, 0.4686777000, 0.7800640000", \ - "0.4023941000, 0.4098009000, 0.4255743000, 0.4554608000, 0.5103910000, 0.6293006000, 0.9404716000", \ - "0.6339165000, 0.6435730000, 0.6646663000, 0.7045980000, 0.7736232000, 0.9033284000, 1.2173860000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.1202579000, 0.1275625000, 0.1442316000, 0.1806516000, 0.2671314000, 0.5029919000, 1.1790394000", \ - "0.1245078000, 0.1317663000, 0.1483691000, 0.1848071000, 0.2713178000, 0.5070573000, 1.1831930000", \ - "0.1348994000, 0.1421988000, 0.1587720000, 0.1949823000, 0.2816567000, 0.5175495000, 1.1980154000", \ - "0.1593081000, 0.1666297000, 0.1833343000, 0.2189168000, 0.3054258000, 0.5420855000, 1.2191421000", \ - "0.2117522000, 0.2194408000, 0.2366977000, 0.2732337000, 0.3602102000, 0.5960056000, 1.2734886000", \ - "0.2839416000, 0.2936133000, 0.3137925000, 0.3547073000, 0.4442101000, 0.6812956000, 1.3618301000", \ - "0.3636118000, 0.3762346000, 0.4031241000, 0.4544858000, 0.5504559000, 0.7883644000, 1.4642221000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0235491000, 0.0272691000, 0.0357790000, 0.0539985000, 0.1005778000, 0.2341743000, 0.6389546000", \ - "0.0236712000, 0.0271033000, 0.0353993000, 0.0541634000, 0.1004338000, 0.2343927000, 0.6424634000", \ - "0.0236479000, 0.0273446000, 0.0356644000, 0.0538931000, 0.1006409000, 0.2341395000, 0.6388303000", \ - "0.0237753000, 0.0273142000, 0.0354730000, 0.0542122000, 0.1005890000, 0.2341208000, 0.6388407000", \ - "0.0240391000, 0.0274424000, 0.0356512000, 0.0541468000, 0.1007071000, 0.2338990000, 0.6387846000", \ - "0.0345960000, 0.0390913000, 0.0475428000, 0.0660578000, 0.1088924000, 0.2372747000, 0.6384843000", \ - "0.0529847000, 0.0586611000, 0.0702872000, 0.0921755000, 0.1348364000, 0.2534087000, 0.6407658000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0277854000, 0.0334650000, 0.0475437000, 0.0852143000, 0.1961237000, 0.5269555000, 1.4977510000", \ - "0.0276409000, 0.0333930000, 0.0475977000, 0.0851901000, 0.1958950000, 0.5268706000, 1.4953359000", \ - "0.0274113000, 0.0332548000, 0.0475261000, 0.0852706000, 0.1959613000, 0.5269145000, 1.4995476000", \ - "0.0274870000, 0.0330243000, 0.0475696000, 0.0850282000, 0.1960100000, 0.5261196000, 1.4977508000", \ - "0.0305335000, 0.0360334000, 0.0498456000, 0.0869429000, 0.1964400000, 0.5258604000, 1.4987636000", \ - "0.0408716000, 0.0469701000, 0.0611211000, 0.0957181000, 0.2012396000, 0.5275660000, 1.4996894000", \ - "0.0571350000, 0.0651089000, 0.0830146000, 0.1164560000, 0.2117735000, 0.5304153000, 1.4956978000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0017111000, 0.0045074000, 0.0098514000, 0.0128306000, -0.009082000, -0.112451700, -0.440839500", \ - "0.0017122000, 0.0045023000, 0.0098540000, 0.0128375000, -0.009057900, -0.112469900, -0.440719900", \ - "0.0017041000, 0.0044802000, 0.0097919000, 0.0126977000, -0.009313600, -0.112712900, -0.440894300", \ - "0.0016960000, 0.0044678000, 0.0097560000, 0.0126386000, -0.009375200, -0.112790700, -0.441052000", \ - "0.0016824000, 0.0044256000, 0.0096718000, 0.0124639000, -0.009661900, -0.113122200, -0.441346300", \ - "0.0016793000, 0.0044147000, 0.0096329000, 0.0123660000, -0.009761000, -0.113297200, -0.441512600", \ - "0.0017154000, 0.0045131000, 0.0099112000, 0.0130399000, -0.009287300, -0.112842700, -0.441161500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0007409000, 0.0021935000, 0.0065784000, 0.0198154000, 0.0585999000, 0.1713119000, 0.5030451000", \ - "0.0007374000, 0.0021848000, 0.0065755000, 0.0198309000, 0.0585455000, 0.1714271000, 0.5030091000", \ - "0.0007323000, 0.0021683000, 0.0065256000, 0.0197244000, 0.0584146000, 0.1713827000, 0.5003777000", \ - "0.0007226000, 0.0021438000, 0.0064790000, 0.0196352000, 0.0583136000, 0.1709447000, 0.5004103000", \ - "0.0007148000, 0.0021228000, 0.0064084000, 0.0194819000, 0.0580990000, 0.1706179000, 0.5000944000", \ - "0.0007150000, 0.0021222000, 0.0064241000, 0.0195334000, 0.0580838000, 0.1707965000, 0.5028886000", \ - "0.0007559000, 0.0022206000, 0.0065892000, 0.0196244000, 0.0584534000, 0.1707010000, 0.4998814000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0017529000, 0.0046264000, 0.0101461000, 0.0134244000, -0.008181800, -0.111458600, -0.439577200", \ - "0.0017557000, 0.0046185000, 0.0101439000, 0.0133842000, -0.008251800, -0.111519900, -0.439675500", \ - "0.0017475000, 0.0046032000, 0.0100803000, 0.0132641000, -0.008429500, -0.111694800, -0.439803000", \ - "0.0017390000, 0.0045809000, 0.0100394000, 0.0131731000, -0.008548000, -0.111836200, -0.439976900", \ - "0.0017214000, 0.0045382000, 0.0099354000, 0.0129623000, -0.008780000, -0.112102400, -0.440257000", \ - "0.0017214000, 0.0045433000, 0.0099367000, 0.0129739000, -0.008939100, -0.112245100, -0.440373000", \ - "0.0017931000, 0.0047120000, 0.0103950000, 0.0138216000, -0.008288500, -0.111668600, -0.439883000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0007462000, 0.0022074000, 0.0066248000, 0.0198997000, 0.0587394000, 0.1716542000, 0.5032289000", \ - "0.0007448000, 0.0021971000, 0.0065988000, 0.0198912000, 0.0586423000, 0.1715530000, 0.5030513000", \ - "0.0007344000, 0.0021751000, 0.0065465000, 0.0197632000, 0.0585073000, 0.1713957000, 0.5001833000", \ - "0.0007185000, 0.0021317000, 0.0064441000, 0.0195451000, 0.0582199000, 0.1709260000, 0.5025091000", \ - "0.0006980000, 0.0020773000, 0.0062937000, 0.0192819000, 0.0577372000, 0.1710917000, 0.5016522000", \ - "0.0006868000, 0.0020443000, 0.0062227000, 0.0191192000, 0.0575299000, 0.1702481000, 0.5018118000", \ - "0.0007165000, 0.0021117000, 0.0063150000, 0.0191065000, 0.0576071000, 0.1698188000, 0.5011128000"); - } - } - max_capacitance : 0.3122050000; - max_transition : 1.5029310000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2339329000, 0.2413089000, 0.2576254000, 0.2893273000, 0.3498506000, 0.4789804000, 0.8122244000", \ - "0.2394018000, 0.2467881000, 0.2631061000, 0.2948500000, 0.3554533000, 0.4844242000, 0.8178567000", \ - "0.2526595000, 0.2600362000, 0.2763269000, 0.3080700000, 0.3685195000, 0.4976866000, 0.8310634000", \ - "0.2807905000, 0.2881849000, 0.3043772000, 0.3361435000, 0.3967074000, 0.5257670000, 0.8590847000", \ - "0.3434763000, 0.3509064000, 0.3670927000, 0.3988417000, 0.4596292000, 0.5887932000, 0.9226808000", \ - "0.4795159000, 0.4872770000, 0.5042949000, 0.5370655000, 0.5987182000, 0.7287302000, 1.0623115000", \ - "0.7225180000, 0.7316780000, 0.7517184000, 0.7899534000, 0.8593713000, 0.9965367000, 1.3327577000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.1203246000, 0.1271447000, 0.1427928000, 0.1777726000, 0.2622640000, 0.4968873000, 1.1801039000", \ - "0.1254271000, 0.1322732000, 0.1480910000, 0.1828662000, 0.2675488000, 0.5035017000, 1.1877330000", \ - "0.1359974000, 0.1428425000, 0.1585757000, 0.1935300000, 0.2781100000, 0.5129591000, 1.1963607000", \ - "0.1575508000, 0.1644230000, 0.1801330000, 0.2150337000, 0.2995850000, 0.5345090000, 1.2166330000", \ - "0.2012547000, 0.2084285000, 0.2246122000, 0.2598005000, 0.3444842000, 0.5804222000, 1.2651281000", \ - "0.2700665000, 0.2781704000, 0.2963509000, 0.3341019000, 0.4205969000, 0.6557778000, 1.3379806000", \ - "0.3520254000, 0.3626353000, 0.3852301000, 0.4292685000, 0.5195930000, 0.7551328000, 1.4375500000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0357243000, 0.0402232000, 0.0504276000, 0.0708782000, 0.1213884000, 0.2575907000, 0.6839334000", \ - "0.0360002000, 0.0402822000, 0.0500830000, 0.0708066000, 0.1214208000, 0.2579720000, 0.6839140000", \ - "0.0357077000, 0.0402020000, 0.0504972000, 0.0708944000, 0.1212592000, 0.2574966000, 0.6835981000", \ - "0.0358537000, 0.0402283000, 0.0498419000, 0.0719132000, 0.1203041000, 0.2581009000, 0.6830465000", \ - "0.0360828000, 0.0403405000, 0.0498857000, 0.0718060000, 0.1210071000, 0.2567937000, 0.6871620000", \ - "0.0395166000, 0.0442334000, 0.0536132000, 0.0745459000, 0.1235933000, 0.2589578000, 0.6834451000", \ - "0.0518128000, 0.0562670000, 0.0671714000, 0.0894441000, 0.1381110000, 0.2703184000, 0.6882598000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0255872000, 0.0309146000, 0.0445102000, 0.0808927000, 0.1897045000, 0.5210427000, 1.4953098000", \ - "0.0253781000, 0.0307860000, 0.0444488000, 0.0808028000, 0.1895415000, 0.5221834000, 1.5004202000", \ - "0.0254741000, 0.0310114000, 0.0444554000, 0.0808245000, 0.1897848000, 0.5207764000, 1.4973786000", \ - "0.0254554000, 0.0308868000, 0.0443870000, 0.0807820000, 0.1896073000, 0.5217494000, 1.4961778000", \ - "0.0272107000, 0.0327120000, 0.0458709000, 0.0818062000, 0.1898709000, 0.5223010000, 1.5005625000", \ - "0.0331276000, 0.0387914000, 0.0524699000, 0.0871612000, 0.1926886000, 0.5211096000, 1.4947807000", \ - "0.0455808000, 0.0523319000, 0.0669870000, 0.1010239000, 0.1994445000, 0.5237858000, 1.4960313000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2355338000, 0.2408163000, 0.2525211000, 0.2761283000, 0.3245444000, 0.4412484000, 0.7707413000", \ - "0.2399884000, 0.2452886000, 0.2569698000, 0.2806032000, 0.3289155000, 0.4457061000, 0.7753123000", \ - "0.2489128000, 0.2542358000, 0.2659347000, 0.2895846000, 0.3379320000, 0.4545491000, 0.7847373000", \ - "0.2694256000, 0.2747808000, 0.2864597000, 0.3100377000, 0.3584589000, 0.4751672000, 0.8047802000", \ - "0.3137125000, 0.3190230000, 0.3307733000, 0.3543776000, 0.4027642000, 0.5193895000, 0.8496384000", \ - "0.3872157000, 0.3926113000, 0.4044261000, 0.4282164000, 0.4768134000, 0.5935546000, 0.9239039000", \ - "0.4816954000, 0.4872880000, 0.4995213000, 0.5237357000, 0.5729240000, 0.6899798000, 1.0198579000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2706231000, 0.2775017000, 0.2930991000, 0.3273382000, 0.4111617000, 0.6459497000, 1.3306363000", \ - "0.2761001000, 0.2830164000, 0.2984942000, 0.3328376000, 0.4165915000, 0.6515828000, 1.3380484000", \ - "0.2895248000, 0.2963579000, 0.3119222000, 0.3461692000, 0.4299807000, 0.6648884000, 1.3471290000", \ - "0.3211267000, 0.3279965000, 0.3435384000, 0.3778569000, 0.4615597000, 0.6966080000, 1.3792362000", \ - "0.3968258000, 0.4037051000, 0.4192896000, 0.4535451000, 0.5373615000, 0.7720164000, 1.4544935000", \ - "0.5590670000, 0.5660275000, 0.5817569000, 0.6161723000, 0.6999439000, 0.9349733000, 1.6176628000", \ - "0.8359362000, 0.8433119000, 0.8598783000, 0.8950060000, 0.9790765000, 1.2138812000, 1.8956292000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0220822000, 0.0255462000, 0.0330176000, 0.0509023000, 0.0979578000, 0.2402777000, 0.6740414000", \ - "0.0221557000, 0.0256175000, 0.0330159000, 0.0507849000, 0.0981407000, 0.2407257000, 0.6794003000", \ - "0.0222855000, 0.0254676000, 0.0330062000, 0.0513104000, 0.0980617000, 0.2397639000, 0.6777338000", \ - "0.0221226000, 0.0255649000, 0.0330196000, 0.0508174000, 0.0979789000, 0.2395455000, 0.6763137000", \ - "0.0222982000, 0.0256383000, 0.0331114000, 0.0514486000, 0.0981033000, 0.2397407000, 0.6778197000", \ - "0.0227414000, 0.0261047000, 0.0344764000, 0.0519932000, 0.0984300000, 0.2401170000, 0.6782123000", \ - "0.0241436000, 0.0276115000, 0.0354306000, 0.0536102000, 0.0993285000, 0.2407861000, 0.6728518000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0264057000, 0.0315251000, 0.0443768000, 0.0798704000, 0.1881625000, 0.5193442000, 1.4962617000", \ - "0.0263941000, 0.0314086000, 0.0443435000, 0.0800550000, 0.1886446000, 0.5207382000, 1.5018882000", \ - "0.0263740000, 0.0315093000, 0.0443122000, 0.0799194000, 0.1883948000, 0.5201789000, 1.4988984000", \ - "0.0263476000, 0.0314264000, 0.0443399000, 0.0799842000, 0.1886237000, 0.5202822000, 1.5027583000", \ - "0.0265131000, 0.0315524000, 0.0444335000, 0.0799186000, 0.1882340000, 0.5192931000, 1.5002574000", \ - "0.0270097000, 0.0320937000, 0.0449239000, 0.0804170000, 0.1887867000, 0.5206537000, 1.4995239000", \ - "0.0304571000, 0.0352219000, 0.0478823000, 0.0822687000, 0.1894405000, 0.5178802000, 1.4951401000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2181416000, 0.2255585000, 0.2417657000, 0.2733303000, 0.3341710000, 0.4632294000, 0.7968423000", \ - "0.2219283000, 0.2293356000, 0.2455627000, 0.2775086000, 0.3381394000, 0.4669394000, 0.8006202000", \ - "0.2325705000, 0.2399430000, 0.2561625000, 0.2880715000, 0.3485421000, 0.4776298000, 0.8113329000", \ - "0.2608044000, 0.2681744000, 0.2843726000, 0.3160343000, 0.3767291000, 0.5058475000, 0.8395598000", \ - "0.3294136000, 0.3368192000, 0.3516306000, 0.3834555000, 0.4442426000, 0.5732861000, 0.9070543000", \ - "0.4842328000, 0.4921684000, 0.5093804000, 0.5422298000, 0.6036088000, 0.7333807000, 1.0665698000", \ - "0.7425140000, 0.7528602000, 0.7750161000, 0.8165160000, 0.8878661000, 1.0243166000, 1.3610126000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.1040067000, 0.1104782000, 0.1255631000, 0.1592561000, 0.2428613000, 0.4779745000, 1.1603563000", \ - "0.1096820000, 0.1161690000, 0.1311747000, 0.1649533000, 0.2485074000, 0.4828541000, 1.1661970000", \ - "0.1203441000, 0.1267531000, 0.1417810000, 0.1756765000, 0.2591850000, 0.4936568000, 1.1767199000", \ - "0.1414897000, 0.1479680000, 0.1630209000, 0.1967399000, 0.2800824000, 0.5148358000, 1.1977142000", \ - "0.1817214000, 0.1886410000, 0.2044961000, 0.2390779000, 0.3229003000, 0.5580866000, 1.2398752000", \ - "0.2397363000, 0.2480824000, 0.2655752000, 0.3029698000, 0.3888757000, 0.6234557000, 1.3054328000", \ - "0.2990738000, 0.3100331000, 0.3337078000, 0.3781045000, 0.4682543000, 0.7029420000, 1.3848112000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0360900000, 0.0401826000, 0.0498279000, 0.0720777000, 0.1218271000, 0.2570817000, 0.6830587000", \ - "0.0358121000, 0.0401767000, 0.0504233000, 0.0712059000, 0.1210462000, 0.2573649000, 0.6876091000", \ - "0.0358101000, 0.0402977000, 0.0499470000, 0.0713007000, 0.1214178000, 0.2573036000, 0.6867343000", \ - "0.0357972000, 0.0402698000, 0.0503902000, 0.0720437000, 0.1212727000, 0.2573598000, 0.6868427000", \ - "0.0359581000, 0.0400280000, 0.0498423000, 0.0713829000, 0.1210536000, 0.2570087000, 0.6866526000", \ - "0.0416702000, 0.0455681000, 0.0558744000, 0.0747629000, 0.1238563000, 0.2589694000, 0.6839566000", \ - "0.0616243000, 0.0669424000, 0.0775819000, 0.0992624000, 0.1430739000, 0.2709963000, 0.6862305000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0237536000, 0.0288664000, 0.0421252000, 0.0784491000, 0.1875107000, 0.5206318000, 1.5009898000", \ - "0.0238427000, 0.0289286000, 0.0421925000, 0.0783175000, 0.1879641000, 0.5206147000, 1.5029309000", \ - "0.0238837000, 0.0291286000, 0.0422666000, 0.0785176000, 0.1879202000, 0.5208058000, 1.5027459000", \ - "0.0239072000, 0.0290744000, 0.0421683000, 0.0783393000, 0.1875387000, 0.5209498000, 1.5026285000", \ - "0.0266164000, 0.0318328000, 0.0447575000, 0.0801239000, 0.1883790000, 0.5214218000, 1.5000610000", \ - "0.0336667000, 0.0390473000, 0.0529181000, 0.0864328000, 0.1916489000, 0.5198804000, 1.4976094000", \ - "0.0481259000, 0.0546394000, 0.0692623000, 0.1029660000, 0.1987000000, 0.5225543000, 1.4927999000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2318079000, 0.2370951000, 0.2488132000, 0.2724617000, 0.3207792000, 0.4375708000, 0.7673385000", \ - "0.2360240000, 0.2412827000, 0.2530014000, 0.2766445000, 0.3249420000, 0.4417098000, 0.7718331000", \ - "0.2461798000, 0.2514767000, 0.2632057000, 0.2868606000, 0.3352315000, 0.4518402000, 0.7820777000", \ - "0.2697552000, 0.2750512000, 0.2867692000, 0.3103325000, 0.3594214000, 0.4761234000, 0.8058697000", \ - "0.3243602000, 0.3296547000, 0.3413785000, 0.3649528000, 0.4137556000, 0.5304623000, 0.8603717000", \ - "0.4084898000, 0.4139801000, 0.4258187000, 0.4496430000, 0.4985493000, 0.6153005000, 0.9454407000", \ - "0.5149059000, 0.5205564000, 0.5329708000, 0.5573444000, 0.6060680000, 0.7232218000, 1.0531725000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2756571000, 0.2827544000, 0.2987862000, 0.3339840000, 0.4186706000, 0.6533943000, 1.3375381000", \ - "0.2813114000, 0.2882757000, 0.3043608000, 0.3395942000, 0.4243506000, 0.6599556000, 1.3438428000", \ - "0.2944893000, 0.3015834000, 0.3176161000, 0.3528032000, 0.4375035000, 0.6722642000, 1.3556032000", \ - "0.3253513000, 0.3324351000, 0.3484942000, 0.3836538000, 0.4684140000, 0.7031944000, 1.3873156000", \ - "0.4005381000, 0.4075438000, 0.4236481000, 0.4588598000, 0.5435871000, 0.7793543000, 1.4641260000", \ - "0.5583042000, 0.5654689000, 0.5816941000, 0.6170837000, 0.7019688000, 0.9374620000, 1.6200755000", \ - "0.8250371000, 0.8325906000, 0.8493854000, 0.8854000000, 0.9707034000, 1.2056415000, 1.8903117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0220765000, 0.0255543000, 0.0330322000, 0.0507723000, 0.0981528000, 0.2410294000, 0.6794840000", \ - "0.0220102000, 0.0255059000, 0.0331048000, 0.0507392000, 0.0978914000, 0.2409538000, 0.6748745000", \ - "0.0220584000, 0.0256667000, 0.0330003000, 0.0513346000, 0.0980658000, 0.2397346000, 0.6777727000", \ - "0.0219769000, 0.0253084000, 0.0334919000, 0.0510163000, 0.0979560000, 0.2396942000, 0.6765786000", \ - "0.0221115000, 0.0255466000, 0.0335496000, 0.0508831000, 0.0980060000, 0.2398099000, 0.6768388000", \ - "0.0231106000, 0.0262178000, 0.0340200000, 0.0521696000, 0.0978775000, 0.2400562000, 0.6762003000", \ - "0.0247653000, 0.0281066000, 0.0363580000, 0.0535303000, 0.1001918000, 0.2401548000, 0.6703845000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0271323000, 0.0324581000, 0.0457659000, 0.0817579000, 0.1899942000, 0.5215898000, 1.4978976000", \ - "0.0271296000, 0.0323630000, 0.0458384000, 0.0818937000, 0.1898689000, 0.5220772000, 1.5023017000", \ - "0.0271236000, 0.0324482000, 0.0457583000, 0.0817644000, 0.1900209000, 0.5215977000, 1.4942773000", \ - "0.0271082000, 0.0324000000, 0.0457477000, 0.0818001000, 0.1902022000, 0.5213193000, 1.4975514000", \ - "0.0272950000, 0.0326217000, 0.0459658000, 0.0819400000, 0.1901277000, 0.5208660000, 1.4998517000", \ - "0.0277571000, 0.0330634000, 0.0463641000, 0.0821718000, 0.1900566000, 0.5219084000, 1.5014177000", \ - "0.0307343000, 0.0359746000, 0.0490063000, 0.0837791000, 0.1911654000, 0.5208626000, 1.4984831000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__ha_4") { - leakage_power () { - value : 0.0074616000; - when : "!A&B"; - } - leakage_power () { - value : 0.0085120000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0078947000; - when : "A&B"; - } - leakage_power () { - value : 0.0074734000; - when : "A&!B"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__ha"; - cell_leakage_power : 0.0078354190; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0093100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0089140000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0097050000; - } - pin ("B") { - capacitance : 0.0080620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080240000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0081000000; - } - pin ("COUT") { - direction : "output"; - function : "(A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015933860, 0.0050777560, 0.0161816500, 0.0515672100, 0.1643329000, 0.5236914000"); - values("0.0034147000, 0.0100799000, 0.0255603000, 0.0448372000, 0.0250003000, -0.135546600, -0.708782200", \ - "0.0034068000, 0.0100360000, 0.0254758000, 0.0446615000, 0.0248901000, -0.135846300, -0.709117200", \ - "0.0033914000, 0.0099874000, 0.0253436000, 0.0443817000, 0.0244952000, -0.136307300, -0.709613100", \ - "0.0033705000, 0.0099371000, 0.0251662000, 0.0440047000, 0.0238721000, -0.136826400, -0.710177300", \ - "0.0033561000, 0.0098804000, 0.0250272000, 0.0435872000, 0.0232450000, -0.137411900, -0.710672400", \ - "0.0033677000, 0.0099174000, 0.0252324000, 0.0438319000, 0.0233732000, -0.137273200, -0.710525600", \ - "0.0034583000, 0.0101612000, 0.0255704000, 0.0443998000, 0.0242109000, -0.136135900, -0.708944500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015933860, 0.0050777560, 0.0161816500, 0.0515672100, 0.1643329000, 0.5236914000"); - values("0.0007238000, 0.0023338000, 0.0075933000, 0.0255174000, 0.0828417000, 0.2622702000, 0.8388538000", \ - "0.0007156000, 0.0023013000, 0.0075222000, 0.0253762000, 0.0827240000, 0.2621106000, 0.8368042000", \ - "0.0006985000, 0.0022580000, 0.0073990000, 0.0251527000, 0.0822478000, 0.2625178000, 0.8360046000", \ - "0.0006792000, 0.0021942000, 0.0072258000, 0.0247495000, 0.0816684000, 0.2613410000, 0.8375493000", \ - "0.0006671000, 0.0021638000, 0.0071059000, 0.0244774000, 0.0813223000, 0.2617072000, 0.8414172000", \ - "0.0007176000, 0.0023026000, 0.0074927000, 0.0249538000, 0.0809799000, 0.2606140000, 0.8415008000", \ - "0.0007643000, 0.0024469000, 0.0078960000, 0.0253753000, 0.0821434000, 0.2618919000, 0.8356368000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015933860, 0.0050777560, 0.0161816500, 0.0515672100, 0.1643329000, 0.5236914000"); - values("0.0032883000, 0.0096959000, 0.0245715000, 0.0428710000, 0.0225541000, -0.138163900, -0.711584800", \ - "0.0032833000, 0.0096614000, 0.0245084000, 0.0427075000, 0.0223555000, -0.138405800, -0.711667900", \ - "0.0032675000, 0.0096258000, 0.0243951000, 0.0424911000, 0.0219209000, -0.138839100, -0.712143100", \ - "0.0032491000, 0.0095607000, 0.0242053000, 0.0420680000, 0.0213466000, -0.139630800, -0.712638100", \ - "0.0032277000, 0.0094928000, 0.0240108000, 0.0415302000, 0.0203544000, -0.140531200, -0.713782800", \ - "0.0032326000, 0.0095014000, 0.0239065000, 0.0412059000, 0.0196264000, -0.141064300, -0.714109900", \ - "0.0033047000, 0.0096960000, 0.0243819000, 0.0419722000, 0.0204562000, -0.140063900, -0.712629300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015933860, 0.0050777560, 0.0161816500, 0.0515672100, 0.1643329000, 0.5236914000"); - values("0.0008346000, 0.0026651000, 0.0085122000, 0.0273882000, 0.0857244000, 0.2662589000, 0.8416844000", \ - "0.0008313000, 0.0026524000, 0.0084762000, 0.0273026000, 0.0856670000, 0.2661638000, 0.8425154000", \ - "0.0008179000, 0.0026138000, 0.0083598000, 0.0271789000, 0.0855728000, 0.2666207000, 0.8400551000", \ - "0.0008039000, 0.0025790000, 0.0082427000, 0.0269004000, 0.0849753000, 0.2655530000, 0.8423959000", \ - "0.0007986000, 0.0025540000, 0.0081184000, 0.0265017000, 0.0845076000, 0.2651700000, 0.8420390000", \ - "0.0008780000, 0.0027787000, 0.0087480000, 0.0274558000, 0.0845481000, 0.2649339000, 0.8424842000", \ - "0.0009363000, 0.0029512000, 0.0093016000, 0.0282268000, 0.0867003000, 0.2668530000, 0.8393991000"); - } - } - max_capacitance : 0.5236910000; - max_transition : 1.5048930000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.1251041000, 0.1285670000, 0.1375253000, 0.1573149000, 0.1997528000, 0.3044713000, 0.6083545000", \ - "0.1302771000, 0.1337473000, 0.1427030000, 0.1625061000, 0.2049306000, 0.3096481000, 0.6135326000", \ - "0.1431926000, 0.1467234000, 0.1556134000, 0.1754243000, 0.2178826000, 0.3226251000, 0.6265237000", \ - "0.1749728000, 0.1784837000, 0.1874240000, 0.2071492000, 0.2497024000, 0.3544313000, 0.6583421000", \ - "0.2499897000, 0.2535023000, 0.2624674000, 0.2822031000, 0.3248811000, 0.4297505000, 0.7335287000", \ - "0.3911764000, 0.3958860000, 0.4080118000, 0.4323362000, 0.4799581000, 0.5878676000, 0.8918878000", \ - "0.6199890000, 0.6263064000, 0.6421880000, 0.6757641000, 0.7369111000, 0.8552302000, 1.1619691000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0929949000, 0.0971950000, 0.1083309000, 0.1364828000, 0.2117817000, 0.4378119000, 1.1497178000", \ - "0.0972138000, 0.1012618000, 0.1125263000, 0.1406755000, 0.2160106000, 0.4421381000, 1.1552402000", \ - "0.1061559000, 0.1103504000, 0.1215468000, 0.1496483000, 0.2250477000, 0.4513088000, 1.1650331000", \ - "0.1261427000, 0.1303016000, 0.1414677000, 0.1695557000, 0.2450469000, 0.4715770000, 1.1836718000", \ - "0.1605039000, 0.1650457000, 0.1770947000, 0.2064248000, 0.2829424000, 0.5096047000, 1.2224887000", \ - "0.2029594000, 0.2084995000, 0.2224524000, 0.2543836000, 0.3328182000, 0.5608406000, 1.2780823000", \ - "0.2293716000, 0.2367482000, 0.2550859000, 0.2943799000, 0.3780211000, 0.6071811000, 1.3205556000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0210843000, 0.0231337000, 0.0287292000, 0.0433258000, 0.0828307000, 0.2037826000, 0.6048163000", \ - "0.0210672000, 0.0231338000, 0.0287068000, 0.0433473000, 0.0828549000, 0.2037837000, 0.6047338000", \ - "0.0208951000, 0.0230305000, 0.0287453000, 0.0433132000, 0.0828265000, 0.2037681000, 0.6044665000", \ - "0.0208886000, 0.0230613000, 0.0286818000, 0.0433419000, 0.0827280000, 0.2037590000, 0.6048120000", \ - "0.0219553000, 0.0239251000, 0.0294550000, 0.0436366000, 0.0829635000, 0.2036401000, 0.6042958000", \ - "0.0323052000, 0.0348346000, 0.0410223000, 0.0552067000, 0.0914657000, 0.2072024000, 0.6050453000", \ - "0.0495905000, 0.0532692000, 0.0617020000, 0.0788809000, 0.1151006000, 0.2204844000, 0.6056705000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0221426000, 0.0256245000, 0.0358499000, 0.0661962000, 0.1650658000, 0.4807090000, 1.5006626000", \ - "0.0221599000, 0.0256674000, 0.0358955000, 0.0662054000, 0.1650691000, 0.4810954000, 1.4973467000", \ - "0.0220948000, 0.0255858000, 0.0357628000, 0.0661919000, 0.1647106000, 0.4797123000, 1.4957504000", \ - "0.0224122000, 0.0257720000, 0.0359978000, 0.0662907000, 0.1650347000, 0.4806947000, 1.5005261000", \ - "0.0255077000, 0.0291087000, 0.0393529000, 0.0689925000, 0.1661766000, 0.4800505000, 1.5005451000", \ - "0.0325652000, 0.0361723000, 0.0464512000, 0.0747573000, 0.1690789000, 0.4825285000, 1.5048931000", \ - "0.0455560000, 0.0502624000, 0.0619427000, 0.0895118000, 0.1768003000, 0.4839029000, 1.4955998000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.1227338000, 0.1263522000, 0.1356594000, 0.1562691000, 0.2001318000, 0.3066704000, 0.6110467000", \ - "0.1277147000, 0.1313342000, 0.1406153000, 0.1612974000, 0.2052976000, 0.3118080000, 0.6161419000", \ - "0.1405826000, 0.1441816000, 0.1534565000, 0.1741131000, 0.2179814000, 0.3246489000, 0.6289976000", \ - "0.1716745000, 0.1752704000, 0.1844885000, 0.2050825000, 0.2490729000, 0.3556129000, 0.6598741000", \ - "0.2461951000, 0.2498829000, 0.2591197000, 0.2797755000, 0.3238027000, 0.4305089000, 0.7346702000", \ - "0.3821792000, 0.3870052000, 0.3990570000, 0.4246595000, 0.4744333000, 0.5846650000, 0.8888940000", \ - "0.6040778000, 0.6103585000, 0.6259513000, 0.6603555000, 0.7246997000, 0.8464761000, 1.1537803000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0864283000, 0.0906222000, 0.1018697000, 0.1299328000, 0.2054614000, 0.4320228000, 1.1451552000", \ - "0.0904506000, 0.0946472000, 0.1058822000, 0.1339475000, 0.2095157000, 0.4361143000, 1.1486146000", \ - "0.1002746000, 0.1044550000, 0.1157191000, 0.1438553000, 0.2194352000, 0.4461690000, 1.1587515000", \ - "0.1232159000, 0.1273794000, 0.1385831000, 0.1666326000, 0.2422565000, 0.4691080000, 1.1812648000", \ - "0.1598174000, 0.1644453000, 0.1761023000, 0.2053578000, 0.2820521000, 0.5090051000, 1.2241379000", \ - "0.1998151000, 0.2056945000, 0.2201023000, 0.2522291000, 0.3303952000, 0.5586559000, 1.2746069000", \ - "0.2187519000, 0.2264835000, 0.2460513000, 0.2862353000, 0.3700074000, 0.5984599000, 1.3118505000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0213927000, 0.0236464000, 0.0296068000, 0.0450647000, 0.0847047000, 0.2058898000, 0.6051153000", \ - "0.0217395000, 0.0239761000, 0.0299313000, 0.0449174000, 0.0846818000, 0.2058660000, 0.6045833000", \ - "0.0216072000, 0.0238298000, 0.0297856000, 0.0449217000, 0.0846481000, 0.2058647000, 0.6047179000", \ - "0.0214025000, 0.0237025000, 0.0299221000, 0.0446599000, 0.0846647000, 0.2053105000, 0.6058355000", \ - "0.0226696000, 0.0248252000, 0.0306430000, 0.0453282000, 0.0850671000, 0.2053494000, 0.6037431000", \ - "0.0334100000, 0.0361630000, 0.0426292000, 0.0576831000, 0.0947964000, 0.2094670000, 0.6036416000", \ - "0.0506633000, 0.0542603000, 0.0632455000, 0.0822818000, 0.1205016000, 0.2247892000, 0.6072511000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015933900, 0.0050777600, 0.0161816000, 0.0515672000, 0.1643330000, 0.5236910000"); - values("0.0220977000, 0.0255933000, 0.0358762000, 0.0661151000, 0.1650203000, 0.4808993000, 1.4982922000", \ - "0.0221026000, 0.0255718000, 0.0357853000, 0.0662161000, 0.1647215000, 0.4807445000, 1.5000539000", \ - "0.0221433000, 0.0256541000, 0.0358751000, 0.0661749000, 0.1649188000, 0.4804616000, 1.5003887000", \ - "0.0226408000, 0.0260042000, 0.0361477000, 0.0662923000, 0.1650395000, 0.4807253000, 1.5008010000", \ - "0.0262098000, 0.0297702000, 0.0400112000, 0.0692980000, 0.1665620000, 0.4807522000, 1.5029900000", \ - "0.0353084000, 0.0389174000, 0.0485076000, 0.0758672000, 0.1692661000, 0.4816477000, 1.5041181000", \ - "0.0500833000, 0.0544647000, 0.0666002000, 0.0932234000, 0.1777080000, 0.4832439000, 1.4991896000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("SUM") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016083510, 0.0051735840, 0.0166418700, 0.0535319300, 0.1721962000, 0.5539039000"); - values("0.0022145000, 0.0065486000, 0.0163493000, 0.0255615000, -0.005230300, -0.180748600, -0.792653400", \ - "0.0022070000, 0.0065235000, 0.0162850000, 0.0254227000, -0.005437500, -0.180992700, -0.792810200", \ - "0.0021894000, 0.0064720000, 0.0161500000, 0.0252046000, -0.005795400, -0.181437300, -0.793241300", \ - "0.0021685000, 0.0064103000, 0.0159823000, 0.0247980000, -0.006363700, -0.182126700, -0.794014400", \ - "0.0021515000, 0.0063638000, 0.0158500000, 0.0245320000, -0.006846300, -0.182635300, -0.794470300", \ - "0.0021797000, 0.0064365000, 0.0160636000, 0.0249604000, -0.006905900, -0.183048900, -0.794916800", \ - "0.0022136000, 0.0065447000, 0.0163126000, 0.0253690000, -0.005897500, -0.181808900, -0.794207700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016083510, 0.0051735840, 0.0166418700, 0.0535319300, 0.1721962000, 0.5539039000"); - values("0.0017956000, 0.0055941000, 0.0165832000, 0.0448620000, 0.1142344000, 0.3105621000, 0.9260821000", \ - "0.0017856000, 0.0055634000, 0.0165016000, 0.0446894000, 0.1139859000, 0.3102572000, 0.9257371000", \ - "0.0017696000, 0.0055142000, 0.0163691000, 0.0444080000, 0.1135425000, 0.3097423000, 0.9251477000", \ - "0.0017472000, 0.0054486000, 0.0161930000, 0.0440220000, 0.1130474000, 0.3091079000, 0.9240998000", \ - "0.0017221000, 0.0053819000, 0.0159909000, 0.0436153000, 0.1124059000, 0.3080526000, 0.9227033000", \ - "0.0017371000, 0.0054268000, 0.0161276000, 0.0438738000, 0.1128543000, 0.3085634000, 0.9269993000", \ - "0.0018123000, 0.0056414000, 0.0165978000, 0.0444303000, 0.1136984000, 0.3098557000, 0.9229774000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016083510, 0.0051735840, 0.0166418700, 0.0535319300, 0.1721962000, 0.5539039000"); - values("0.0023215000, 0.0068686000, 0.0172105000, 0.0274453000, -0.002386000, -0.177388500, -0.788973800", \ - "0.0023157000, 0.0068544000, 0.0171706000, 0.0273544000, -0.002526700, -0.177548400, -0.789139000", \ - "0.0023066000, 0.0068323000, 0.0171186000, 0.0272357000, -0.002731200, -0.177802200, -0.789412600", \ - "0.0022917000, 0.0067811000, 0.0169817000, 0.0269533000, -0.003124700, -0.178280300, -0.789917000", \ - "0.0022723000, 0.0067221000, 0.0168153000, 0.0265429000, -0.003793100, -0.179010200, -0.790650700", \ - "0.0023209000, 0.0068692000, 0.0172321000, 0.0274638000, -0.003108400, -0.178452900, -0.790083300", \ - "0.0023771000, 0.0070242000, 0.0176998000, 0.0282847000, -0.001507900, -0.176313600, -0.788133300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016083510, 0.0051735840, 0.0166418700, 0.0535319300, 0.1721962000, 0.5539039000"); - values("0.0016799000, 0.0052553000, 0.0156580000, 0.0428838000, 0.1112988000, 0.3065742000, 0.9252285000", \ - "0.0016748000, 0.0052400000, 0.0155942000, 0.0427386000, 0.1109590000, 0.3064653000, 0.9196801000", \ - "0.0016568000, 0.0051823000, 0.0154405000, 0.0424756000, 0.1105877000, 0.3059652000, 0.9195634000", \ - "0.0016314000, 0.0051004000, 0.0152605000, 0.0420955000, 0.1100371000, 0.3054273000, 0.9189822000", \ - "0.0015999000, 0.0050088000, 0.0150142000, 0.0415589000, 0.1092272000, 0.3042214000, 0.9219321000", \ - "0.0015772000, 0.0049420000, 0.0148553000, 0.0412309000, 0.1088816000, 0.3040206000, 0.9175828000", \ - "0.0016720000, 0.0052137000, 0.0154417000, 0.0419918000, 0.1097462000, 0.3048610000, 0.9225881000"); - } - } - max_capacitance : 0.5539040000; - max_transition : 1.5041970000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.2019689000, 0.2062367000, 0.2171258000, 0.2409919000, 0.2903694000, 0.4027092000, 0.7206771000", \ - "0.2067313000, 0.2109986000, 0.2217557000, 0.2455868000, 0.2947181000, 0.4073451000, 0.7250259000", \ - "0.2193375000, 0.2235837000, 0.2344725000, 0.2583396000, 0.3077338000, 0.4200935000, 0.7380764000", \ - "0.2478029000, 0.2520536000, 0.2629117000, 0.2867101000, 0.3357948000, 0.4484342000, 0.7661461000", \ - "0.3119799000, 0.3162428000, 0.3271036000, 0.3509327000, 0.4002502000, 0.5128705000, 0.8307134000", \ - "0.4452543000, 0.4499163000, 0.4617377000, 0.4871830000, 0.5386787000, 0.6525864000, 0.9705442000", \ - "0.6813278000, 0.6870103000, 0.7012894000, 0.7316824000, 0.7902941000, 0.9124523000, 1.2341987000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0934753000, 0.0974124000, 0.1080377000, 0.1348859000, 0.2077958000, 0.4324704000, 1.1515204000", \ - "0.0983264000, 0.1022664000, 0.1128793000, 0.1397365000, 0.2126724000, 0.4370541000, 1.1589665000", \ - "0.1081126000, 0.1120456000, 0.1227331000, 0.1495817000, 0.2225279000, 0.4471967000, 1.1663068000", \ - "0.1285614000, 0.1324775000, 0.1430698000, 0.1698754000, 0.2429113000, 0.4682789000, 1.1854665000", \ - "0.1642478000, 0.1685039000, 0.1797162000, 0.2073902000, 0.2810814000, 0.5060261000, 1.2250599000", \ - "0.2105066000, 0.2155170000, 0.2283959000, 0.2579585000, 0.3328488000, 0.5582011000, 1.2791221000", \ - "0.2433280000, 0.2499579000, 0.2666343000, 0.3025995000, 0.3810365000, 0.6063176000, 1.3251088000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0284817000, 0.0309773000, 0.0375444000, 0.0532187000, 0.0941376000, 0.2143859000, 0.6230649000", \ - "0.0284297000, 0.0309361000, 0.0377521000, 0.0532465000, 0.0939919000, 0.2147924000, 0.6228368000", \ - "0.0284502000, 0.0309918000, 0.0375431000, 0.0532188000, 0.0941343000, 0.2143578000, 0.6228888000", \ - "0.0287155000, 0.0312203000, 0.0373153000, 0.0535001000, 0.0943052000, 0.2145948000, 0.6228404000", \ - "0.0284444000, 0.0309602000, 0.0375286000, 0.0532121000, 0.0940407000, 0.2143367000, 0.6261352000", \ - "0.0333725000, 0.0355884000, 0.0422963000, 0.0586367000, 0.0976126000, 0.2163478000, 0.6233493000", \ - "0.0448107000, 0.0482054000, 0.0552044000, 0.0718556000, 0.1117089000, 0.2274670000, 0.6242570000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0203108000, 0.0236197000, 0.0333004000, 0.0624241000, 0.1582383000, 0.4759289000, 1.5008174000", \ - "0.0204120000, 0.0236625000, 0.0333268000, 0.0623901000, 0.1578780000, 0.4743527000, 1.5004959000", \ - "0.0204182000, 0.0237236000, 0.0332849000, 0.0624360000, 0.1582476000, 0.4754740000, 1.5013947000", \ - "0.0204552000, 0.0236416000, 0.0332884000, 0.0623820000, 0.1581298000, 0.4757572000, 1.4975453000", \ - "0.0226864000, 0.0261679000, 0.0356637000, 0.0642630000, 0.1585491000, 0.4765044000, 1.5014180000", \ - "0.0285887000, 0.0319112000, 0.0415503000, 0.0690166000, 0.1610737000, 0.4742063000, 1.5017458000", \ - "0.0405097000, 0.0446154000, 0.0551424000, 0.0816649000, 0.1664154000, 0.4773776000, 1.4970841000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.1713114000, 0.1742742000, 0.1818674000, 0.1991118000, 0.2376831000, 0.3388305000, 0.6528029000", \ - "0.1756360000, 0.1785965000, 0.1861827000, 0.2034470000, 0.2420274000, 0.3431941000, 0.6572443000", \ - "0.1846014000, 0.1875759000, 0.1951723000, 0.2124422000, 0.2509893000, 0.3522214000, 0.6668925000", \ - "0.2046595000, 0.2075957000, 0.2152067000, 0.2324511000, 0.2710306000, 0.3722116000, 0.6861139000", \ - "0.2423370000, 0.2453157000, 0.2529914000, 0.2702745000, 0.3089409000, 0.4101451000, 0.7239169000", \ - "0.2918306000, 0.2948055000, 0.3025415000, 0.3200064000, 0.3588660000, 0.4602856000, 0.7743529000", \ - "0.3353640000, 0.3385358000, 0.3466580000, 0.3646554000, 0.4038013000, 0.5055300000, 0.8200866000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.2237373000, 0.2279101000, 0.2391205000, 0.2670026000, 0.3408030000, 0.5657826000, 1.2851967000", \ - "0.2289346000, 0.2331071000, 0.2443178000, 0.2722081000, 0.3460199000, 0.5709544000, 1.2904994000", \ - "0.2418305000, 0.2460081000, 0.2572181000, 0.2851020000, 0.3589020000, 0.5838711000, 1.3033085000", \ - "0.2734983000, 0.2776742000, 0.2888839000, 0.3167498000, 0.3905039000, 0.6155583000, 1.3348244000", \ - "0.3482633000, 0.3524742000, 0.3637122000, 0.3916396000, 0.4654879000, 0.6901129000, 1.4101352000", \ - "0.5032844000, 0.5075743000, 0.5189041000, 0.5468588000, 0.6209356000, 0.8460054000, 1.5655769000", \ - "0.7612587000, 0.7657975000, 0.7776423000, 0.8063205000, 0.8808773000, 1.1059420000, 1.8252644000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0168048000, 0.0186841000, 0.0237991000, 0.0370371000, 0.0750700000, 0.1991356000, 0.6227429000", \ - "0.0168124000, 0.0186899000, 0.0237892000, 0.0370685000, 0.0750723000, 0.1991409000, 0.6228827000", \ - "0.0169025000, 0.0187965000, 0.0239630000, 0.0370821000, 0.0749205000, 0.1989489000, 0.6175433000", \ - "0.0168840000, 0.0186853000, 0.0239733000, 0.0371798000, 0.0750954000, 0.1992176000, 0.6225517000", \ - "0.0171642000, 0.0189576000, 0.0240608000, 0.0372527000, 0.0751858000, 0.1989997000, 0.6207772000", \ - "0.0176106000, 0.0196282000, 0.0249409000, 0.0378458000, 0.0755902000, 0.1981590000, 0.6167813000", \ - "0.0191473000, 0.0210586000, 0.0260723000, 0.0394020000, 0.0765999000, 0.1997121000, 0.6190651000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0225734000, 0.0259759000, 0.0355899000, 0.0646727000, 0.1593139000, 0.4748880000, 1.5001462000", \ - "0.0225696000, 0.0259938000, 0.0355982000, 0.0646665000, 0.1593336000, 0.4747216000, 1.4997227000", \ - "0.0225375000, 0.0259809000, 0.0355938000, 0.0646749000, 0.1593132000, 0.4748623000, 1.5002264000", \ - "0.0225777000, 0.0259702000, 0.0355898000, 0.0646916000, 0.1591608000, 0.4751343000, 1.5006201000", \ - "0.0226437000, 0.0258075000, 0.0357436000, 0.0647105000, 0.1593076000, 0.4742046000, 1.4979430000", \ - "0.0233404000, 0.0265239000, 0.0363249000, 0.0649504000, 0.1595533000, 0.4751003000, 1.5041969000", \ - "0.0264892000, 0.0293896000, 0.0388405000, 0.0670584000, 0.1604791000, 0.4749005000, 1.4994783000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.1809019000, 0.1851603000, 0.1960117000, 0.2198143000, 0.2690045000, 0.3817816000, 0.6993603000", \ - "0.1846485000, 0.1889091000, 0.1997602000, 0.2235810000, 0.2727814000, 0.3854387000, 0.7031452000", \ - "0.1953180000, 0.1995863000, 0.2104300000, 0.2342413000, 0.2835776000, 0.3959762000, 0.7140046000", \ - "0.2229602000, 0.2272294000, 0.2380771000, 0.2620091000, 0.3111057000, 0.4237552000, 0.7413402000", \ - "0.2916542000, 0.2958924000, 0.3066661000, 0.3305179000, 0.3797984000, 0.4924233000, 0.8101179000", \ - "0.4380198000, 0.4429395000, 0.4552521000, 0.4810475000, 0.5323208000, 0.6466753000, 0.9647422000", \ - "0.6769643000, 0.6835058000, 0.6997528000, 0.7331961000, 0.7939961000, 0.9143882000, 1.2358558000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0897904000, 0.0938348000, 0.1048259000, 0.1322758000, 0.2056940000, 0.4299693000, 1.1479450000", \ - "0.0948372000, 0.0989187000, 0.1098826000, 0.1374171000, 0.2107645000, 0.4351912000, 1.1540994000", \ - "0.1042738000, 0.1083595000, 0.1192626000, 0.1467996000, 0.2203506000, 0.4452791000, 1.1647456000", \ - "0.1223968000, 0.1264038000, 0.1373417000, 0.1647912000, 0.2383768000, 0.4635280000, 1.1821369000", \ - "0.1529015000, 0.1573148000, 0.1690367000, 0.1974433000, 0.2716972000, 0.4971104000, 1.2155930000", \ - "0.1905708000, 0.1959659000, 0.2095361000, 0.2402149000, 0.3159004000, 0.5412495000, 1.2609133000", \ - "0.2100522000, 0.2171229000, 0.2348609000, 0.2730546000, 0.3533598000, 0.5791843000, 1.2970179000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0284910000, 0.0309755000, 0.0373720000, 0.0536416000, 0.0941927000, 0.2144831000, 0.6230098000", \ - "0.0284739000, 0.0309770000, 0.0373363000, 0.0535747000, 0.0942362000, 0.2145412000, 0.6231073000", \ - "0.0284054000, 0.0308876000, 0.0378360000, 0.0530380000, 0.0940990000, 0.2146502000, 0.6248375000", \ - "0.0285295000, 0.0309967000, 0.0377328000, 0.0532772000, 0.0945184000, 0.2146479000, 0.6241453000", \ - "0.0286552000, 0.0310012000, 0.0377448000, 0.0533325000, 0.0941656000, 0.2145452000, 0.6233258000", \ - "0.0366723000, 0.0387180000, 0.0450369000, 0.0594748000, 0.0984440000, 0.2162314000, 0.6237501000", \ - "0.0543404000, 0.0578267000, 0.0651348000, 0.0819853000, 0.1164126000, 0.2277605000, 0.6249415000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0209042000, 0.0242610000, 0.0339999000, 0.0634155000, 0.1586626000, 0.4763001000, 1.4978410000", \ - "0.0209027000, 0.0242285000, 0.0340489000, 0.0634102000, 0.1585618000, 0.4757927000, 1.5017448000", \ - "0.0209283000, 0.0243344000, 0.0340979000, 0.0633414000, 0.1583200000, 0.4759552000, 1.5029621000", \ - "0.0212817000, 0.0245687000, 0.0344080000, 0.0635576000, 0.1584938000, 0.4757548000, 1.5040498000", \ - "0.0237012000, 0.0271556000, 0.0370486000, 0.0656930000, 0.1594654000, 0.4758448000, 1.5008091000", \ - "0.0304472000, 0.0339504000, 0.0434966000, 0.0714766000, 0.1621830000, 0.4740163000, 1.4975686000", \ - "0.0439198000, 0.0484689000, 0.0591592000, 0.0852895000, 0.1692258000, 0.4772223000, 1.4944176000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.1648585000, 0.1678007000, 0.1754038000, 0.1926623000, 0.2312123000, 0.3324422000, 0.6473972000", \ - "0.1688290000, 0.1717998000, 0.1794027000, 0.1966888000, 0.2352281000, 0.3364420000, 0.6511247000", \ - "0.1786845000, 0.1816694000, 0.1892876000, 0.2065541000, 0.2450911000, 0.3462748000, 0.6599060000", \ - "0.2015064000, 0.2044788000, 0.2120699000, 0.2293173000, 0.2678573000, 0.3690845000, 0.6839571000", \ - "0.2410046000, 0.2439695000, 0.2514679000, 0.2687887000, 0.3074240000, 0.4086694000, 0.7229383000", \ - "0.2894114000, 0.2924445000, 0.3001503000, 0.3176498000, 0.3565285000, 0.4578141000, 0.7717999000", \ - "0.3277665000, 0.3309741000, 0.3391691000, 0.3572771000, 0.3968214000, 0.4982232000, 0.8125076000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.2286952000, 0.2327548000, 0.2435753000, 0.2707447000, 0.3439611000, 0.5690038000, 1.2878841000", \ - "0.2337693000, 0.2378484000, 0.2486805000, 0.2758699000, 0.3490782000, 0.5743450000, 1.2938015000", \ - "0.2464902000, 0.2506066000, 0.2614152000, 0.2886388000, 0.3618539000, 0.5869993000, 1.3054398000", \ - "0.2772799000, 0.2813192000, 0.2921850000, 0.3194137000, 0.3927271000, 0.6171828000, 1.3361094000", \ - "0.3511605000, 0.3552290000, 0.3661153000, 0.3933686000, 0.4666956000, 0.6911922000, 1.4129060000", \ - "0.5005926000, 0.5047209000, 0.5157305000, 0.5431761000, 0.6168554000, 0.8421460000, 1.5613832000", \ - "0.7503879000, 0.7548389000, 0.7664626000, 0.7944377000, 0.8684045000, 1.0937904000, 1.8135967000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0168962000, 0.0187476000, 0.0239946000, 0.0371983000, 0.0751020000, 0.1991576000, 0.6174668000", \ - "0.0169501000, 0.0187613000, 0.0239573000, 0.0370391000, 0.0749425000, 0.1990404000, 0.6175594000", \ - "0.0168760000, 0.0187445000, 0.0237396000, 0.0373133000, 0.0749473000, 0.1990778000, 0.6222260000", \ - "0.0169128000, 0.0188003000, 0.0239807000, 0.0371296000, 0.0749953000, 0.1990112000, 0.6175538000", \ - "0.0170786000, 0.0189971000, 0.0243086000, 0.0375952000, 0.0752149000, 0.1999101000, 0.6155740000", \ - "0.0176691000, 0.0195215000, 0.0247213000, 0.0379218000, 0.0757323000, 0.1983436000, 0.6168423000", \ - "0.0196717000, 0.0216300000, 0.0263395000, 0.0394049000, 0.0768313000, 0.2000519000, 0.6202244000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016083500, 0.0051735800, 0.0166419000, 0.0535319000, 0.1721960000, 0.5539040000"); - values("0.0217860000, 0.0250487000, 0.0347132000, 0.0635778000, 0.1585524000, 0.4737863000, 1.5021629000", \ - "0.0217374000, 0.0250729000, 0.0345886000, 0.0636121000, 0.1587565000, 0.4752119000, 1.4980114000", \ - "0.0218542000, 0.0250632000, 0.0346501000, 0.0635695000, 0.1585075000, 0.4742857000, 1.4949946000", \ - "0.0218819000, 0.0252049000, 0.0346374000, 0.0635907000, 0.1588077000, 0.4753473000, 1.4980285000", \ - "0.0219703000, 0.0251988000, 0.0347743000, 0.0637071000, 0.1586343000, 0.4753813000, 1.5015497000", \ - "0.0226254000, 0.0259678000, 0.0353481000, 0.0640350000, 0.1592399000, 0.4750744000, 1.5017813000", \ - "0.0256956000, 0.0289269000, 0.0378467000, 0.0658126000, 0.1597834000, 0.4751843000, 1.4965075000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_1") { - leakage_power () { - value : 0.0104575000; - when : "A"; - } - leakage_power () { - value : 0.0001958000; - when : "!A"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0053266820; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023900000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013351650, 0.0035653330, 0.0095206180, 0.0254232000, 0.0678883500, 0.1812843000"); - values("-0.002015300, -0.003233700, -0.006682600, -0.016215100, -0.041923500, -0.110694300, -0.294385400", \ - "-0.002291600, -0.003484300, -0.006864100, -0.016312600, -0.041961800, -0.110705600, -0.294392800", \ - "-0.002504200, -0.003754200, -0.007122300, -0.016492800, -0.042058000, -0.110745100, -0.294413600", \ - "-0.002471200, -0.003758100, -0.007306000, -0.016724000, -0.042216900, -0.110798800, -0.294434500", \ - "-0.002055900, -0.003439600, -0.007209200, -0.016769900, -0.042305000, -0.110917500, -0.294457000", \ - "-0.001022000, -0.002580100, -0.006400700, -0.016127500, -0.042162700, -0.110909400, -0.294507900", \ - "0.0018716000, 0.0002414000, -0.004081800, -0.014581800, -0.040851400, -0.110170100, -0.294159900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013351650, 0.0035653330, 0.0095206180, 0.0254232000, 0.0678883500, 0.1812843000"); - values("0.0077341000, 0.0092285000, 0.0130076000, 0.0228389000, 0.0486009000, 0.1169039000, 0.2980101000", \ - "0.0075137000, 0.0089827000, 0.0128048000, 0.0225722000, 0.0483903000, 0.1157698000, 0.2983583000", \ - "0.0074664000, 0.0088070000, 0.0125411000, 0.0222793000, 0.0479465000, 0.1162597000, 0.2988481000", \ - "0.0074628000, 0.0088101000, 0.0124018000, 0.0220691000, 0.0478142000, 0.1160948000, 0.2978862000", \ - "0.0078037000, 0.0090867000, 0.0126015000, 0.0221454000, 0.0471764000, 0.1154567000, 0.2971936000", \ - "0.0085703000, 0.0097756000, 0.0131398000, 0.0225755000, 0.0477140000, 0.1159043000, 0.2976869000", \ - "0.0117396000, 0.0133470000, 0.0162555000, 0.0258334000, 0.0499281000, 0.1175191000, 0.2963656000"); - } - } - max_capacitance : 0.1812840000; - max_transition : 1.4983500000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0143656000, 0.0174314000, 0.0252454000, 0.0454996000, 0.0982781000, 0.2396302000, 0.6168033000", \ - "0.0188850000, 0.0219910000, 0.0299354000, 0.0501644000, 0.1030737000, 0.2443058000, 0.6211737000", \ - "0.0258174000, 0.0306806000, 0.0410519000, 0.0615784000, 0.1142486000, 0.2560606000, 0.6330331000", \ - "0.0343699000, 0.0422631000, 0.0579953000, 0.0872580000, 0.1417882000, 0.2823734000, 0.6608606000", \ - "0.0429306000, 0.0551406000, 0.0803595000, 0.1251743000, 0.2024078000, 0.3451943000, 0.7237922000", \ - "0.0467306000, 0.0653220000, 0.1038849000, 0.1743242000, 0.2939730000, 0.4885973000, 0.8661273000", \ - "0.0317479000, 0.0590882000, 0.1188517000, 0.2277923000, 0.4124719000, 0.7155372000, 1.2016104000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0203433000, 0.0255806000, 0.0388749000, 0.0728467000, 0.1628902000, 0.4016502000, 1.0383745000", \ - "0.0255253000, 0.0306373000, 0.0439316000, 0.0783240000, 0.1679452000, 0.4092315000, 1.0428830000", \ - "0.0373555000, 0.0435741000, 0.0566328000, 0.0903158000, 0.1807958000, 0.4194971000, 1.0619717000", \ - "0.0547083000, 0.0647747000, 0.0847049000, 0.1211221000, 0.2113354000, 0.4503315000, 1.0860455000", \ - "0.0801236000, 0.0963068000, 0.1281064000, 0.1863159000, 0.2799442000, 0.5189765000, 1.1578426000", \ - "0.1184431000, 0.1426164000, 0.1928426000, 0.2835618000, 0.4327621000, 0.6847846000, 1.3109622000", \ - "0.1833476000, 0.2165725000, 0.2904738000, 0.4311227000, 0.6701159000, 1.0433531000, 1.6968695000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0078064000, 0.0114862000, 0.0214097000, 0.0477227000, 0.1186008000, 0.3072657000, 0.8034127000", \ - "0.0090602000, 0.0121604000, 0.0214004000, 0.0478255000, 0.1185653000, 0.3042409000, 0.8075141000", \ - "0.0149965000, 0.0184620000, 0.0253538000, 0.0485230000, 0.1183136000, 0.3050132000, 0.8077053000", \ - "0.0252848000, 0.0304682000, 0.0408323000, 0.0598601000, 0.1207760000, 0.3047933000, 0.8058169000", \ - "0.0433758000, 0.0513324000, 0.0671383000, 0.0963828000, 0.1477217000, 0.3113176000, 0.8041146000", \ - "0.0756267000, 0.0875932000, 0.1123155000, 0.1572394000, 0.2319551000, 0.3682797000, 0.8125686000", \ - "0.1370231000, 0.1548396000, 0.1933634000, 0.2609415000, 0.3750985000, 0.5666359000, 0.9242953000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0145424000, 0.0213070000, 0.0395425000, 0.0876798000, 0.2171014000, 0.5586131000, 1.4687663000", \ - "0.0146713000, 0.0213043000, 0.0393699000, 0.0877615000, 0.2159054000, 0.5600529000, 1.4722740000", \ - "0.0211790000, 0.0256255000, 0.0404175000, 0.0878470000, 0.2163130000, 0.5577243000, 1.4753007000", \ - "0.0345207000, 0.0410610000, 0.0542730000, 0.0916769000, 0.2161580000, 0.5606987000, 1.4678798000", \ - "0.0568227000, 0.0674569000, 0.0881982000, 0.1265939000, 0.2258740000, 0.5582781000, 1.4769377000", \ - "0.0919248000, 0.1090963000, 0.1442140000, 0.2030622000, 0.2988102000, 0.5742777000, 1.4743026000", \ - "0.1521643000, 0.1785044000, 0.2319170000, 0.3280231000, 0.4842423000, 0.7386280000, 1.4983498000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_12") { - leakage_power () { - value : 0.0080708000; - when : "A"; - } - leakage_power () { - value : 0.0065197000; - when : "!A"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0072952340; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0260110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0247960000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0272270000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018809730, 0.0070761180, 0.0266199700, 0.1001429000, 0.3767321000, 1.4172460000"); - values("-0.022522000, -0.024231300, -0.031107900, -0.060176000, -0.177584000, -0.625069100, -2.310563600", \ - "-0.025421700, -0.027147000, -0.034024700, -0.062323500, -0.178422900, -0.625365700, -2.310629300", \ - "-0.027654600, -0.029567500, -0.036898100, -0.065311000, -0.180118400, -0.625786900, -2.310727800", \ - "-0.028510200, -0.030618000, -0.038151700, -0.068039100, -0.182832800, -0.626978000, -2.310986300", \ - "-0.025363700, -0.027544400, -0.035064700, -0.067351900, -0.184622400, -0.628597200, -2.311583700", \ - "-0.016717500, -0.016977400, -0.028630100, -0.060955900, -0.181597300, -0.628639400, -2.312055500", \ - "0.0116536000, 0.0055242000, -0.002296800, -0.043058400, -0.170615100, -0.623382700, -2.311704000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018809730, 0.0070761180, 0.0266199700, 0.1001429000, 0.3767321000, 1.4172460000"); - values("0.0742482000, 0.0771417000, 0.0875553000, 0.1228342000, 0.2448619000, 0.6860297000, 2.3578084000", \ - "0.0724747000, 0.0750598000, 0.0846380000, 0.1196370000, 0.2417134000, 0.6860361000, 2.3494230000", \ - "0.0724948000, 0.0747711000, 0.0835678000, 0.1169637000, 0.2382113000, 0.6836688000, 2.3452061000", \ - "0.0735167000, 0.0757829000, 0.0844056000, 0.1157342000, 0.2350232000, 0.6810167000, 2.3444703000", \ - "0.0756336000, 0.0778235000, 0.0857701000, 0.1169748000, 0.2351647000, 0.6793571000, 2.3414699000", \ - "0.0857049000, 0.0875782000, 0.0947952000, 0.1236911000, 0.2386874000, 0.6773138000, 2.3459190000", \ - "0.1061441000, 0.1077911000, 0.1141072000, 0.1410738000, 0.2511837000, 0.6877010000, 2.3439793000"); - } - } - max_capacitance : 1.4172460000; - max_transition : 1.4997670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018809700, 0.0070761200, 0.0266200000, 0.1001430000, 0.3767320000, 1.4172500000"); - values("0.0134568000, 0.0140150000, 0.0160170000, 0.0226690000, 0.0459600000, 0.1323039000, 0.4544274000", \ - "0.0170655000, 0.0177550000, 0.0200684000, 0.0269260000, 0.0503345000, 0.1370679000, 0.4591227000", \ - "0.0209872000, 0.0220936000, 0.0257524000, 0.0360351000, 0.0608447000, 0.1469974000, 0.4698110000", \ - "0.0234171000, 0.0251621000, 0.0308065000, 0.0472022000, 0.0842554000, 0.1725364000, 0.4939870000", \ - "0.0189496000, 0.0218966000, 0.0310262000, 0.0564721000, 0.1145687000, 0.2306673000, 0.5539201000", \ - "-0.005217100, -0.000922800, 0.0134875000, 0.0532908000, 0.1448801000, 0.3250146000, 0.6880480000", \ - "-0.081672400, -0.075048500, -0.053420200, 0.0073152000, 0.1501198000, 0.4354746000, 0.9750045000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018809700, 0.0070761200, 0.0266200000, 0.1001430000, 0.3767320000, 1.4172500000"); - values("0.0222009000, 0.0235264000, 0.0282525000, 0.0442345000, 0.0996235000, 0.2999233000, 1.0548541000", \ - "0.0274482000, 0.0286550000, 0.0330422000, 0.0488355000, 0.1043226000, 0.3061772000, 1.0690973000", \ - "0.0403636000, 0.0418538000, 0.0466903000, 0.0617842000, 0.1168165000, 0.3183527000, 1.0720190000", \ - "0.0603263000, 0.0627427000, 0.0707800000, 0.0927495000, 0.1483001000, 0.3501730000, 1.1048581000", \ - "0.0930741000, 0.0968540000, 0.1095235000, 0.1446591000, 0.2227919000, 0.4236666000, 1.1779668000", \ - "0.1518632000, 0.1574219000, 0.1761302000, 0.2305127000, 0.3543489000, 0.5973493000, 1.3502187000", \ - "0.2671627000, 0.2749497000, 0.3018162000, 0.3804795000, 0.5717922000, 0.9568082000, 1.7508425000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018809700, 0.0070761200, 0.0266200000, 0.1001430000, 0.3767320000, 1.4172500000"); - values("0.0054999000, 0.0060540000, 0.0082469000, 0.0165709000, 0.0481191000, 0.1667122000, 0.6099141000", \ - "0.0072262000, 0.0076467000, 0.0093223000, 0.0167010000, 0.0480989000, 0.1678896000, 0.6106698000", \ - "0.0117843000, 0.0126030000, 0.0150497000, 0.0223123000, 0.0489808000, 0.1661177000, 0.6109002000", \ - "0.0203622000, 0.0214711000, 0.0253095000, 0.0356660000, 0.0616239000, 0.1672489000, 0.6103792000", \ - "0.0362073000, 0.0377888000, 0.0431167000, 0.0596909000, 0.0961814000, 0.1879626000, 0.6101499000", \ - "0.0642847000, 0.0673080000, 0.0762185000, 0.1023528000, 0.1569489000, 0.2765521000, 0.6332964000", \ - "0.1181866000, 0.1223390000, 0.1359254000, 0.1773315000, 0.2620997000, 0.4363181000, 0.8019156000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018809700, 0.0070761200, 0.0266200000, 0.1001430000, 0.3767320000, 1.4172500000"); - values("0.0129195000, 0.0143484000, 0.0197363000, 0.0401105000, 0.1169362000, 0.4035376000, 1.4836571000", \ - "0.0130600000, 0.0144668000, 0.0197984000, 0.0401591000, 0.1165690000, 0.4025310000, 1.4839162000", \ - "0.0183877000, 0.0191611000, 0.0229456000, 0.0403582000, 0.1166603000, 0.4032047000, 1.4833866000", \ - "0.0300137000, 0.0316774000, 0.0372553000, 0.0521322000, 0.1171256000, 0.4032374000, 1.4801944000", \ - "0.0495353000, 0.0521707000, 0.0605320000, 0.0838027000, 0.1400626000, 0.4036818000, 1.4779666000", \ - "0.0800196000, 0.0840082000, 0.0978460000, 0.1356194000, 0.2172222000, 0.4331897000, 1.4861427000", \ - "0.1363140000, 0.1419993000, 0.1605072000, 0.2178177000, 0.3508469000, 0.6035469000, 1.4997668000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_16") { - leakage_power () { - value : 0.0106779000; - when : "A"; - } - leakage_power () { - value : 0.0088949000; - when : "!A"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0097863830; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0334420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0318840000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0349990000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019354060, 0.0074915960, 0.0289985600, 0.1122480000, 0.4344910000, 1.6818330000"); - values("-0.030674500, -0.032467200, -0.039748000, -0.071664200, -0.204577500, -0.725957200, -2.746443500", \ - "-0.034291900, -0.036135800, -0.043434800, -0.074455100, -0.205774200, -0.726450400, -2.746769000", \ - "-0.037187700, -0.039198400, -0.047016800, -0.078200400, -0.207941200, -0.727231500, -2.747056700", \ - "-0.038362800, -0.040592900, -0.049030100, -0.081728000, -0.211029500, -0.728448800, -2.747455000", \ - "-0.033762100, -0.036185600, -0.045457900, -0.079643200, -0.213383200, -0.730580500, -2.748166300", \ - "-0.022081300, -0.024792500, -0.035079300, -0.072970700, -0.210198800, -0.728775500, -2.748363600", \ - "0.0097426000, 0.0063139000, -0.005425700, -0.046842300, -0.193580100, -0.723880000, -2.746717800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019354060, 0.0074915960, 0.0289985600, 0.1122480000, 0.4344910000, 1.6818330000"); - values("0.0967107000, 0.0997483000, 0.1109936000, 0.1501386000, 0.2871024000, 0.8057040000, 2.7963814000", \ - "0.0944329000, 0.0971734000, 0.1076123000, 0.1461634000, 0.2850891000, 0.8039616000, 2.8025622000", \ - "0.0936338000, 0.0960910000, 0.1057220000, 0.1422643000, 0.2814786000, 0.8028242000, 2.8037671000", \ - "0.0941157000, 0.0965133000, 0.1071366000, 0.1409863000, 0.2776375000, 0.7989318000, 2.7958338000", \ - "0.1002031000, 0.1024628000, 0.1110491000, 0.1432086000, 0.2768670000, 0.7948048000, 2.7899073000", \ - "0.1095516000, 0.1114562000, 0.1191311000, 0.1511014000, 0.2812488000, 0.7933454000, 2.7910548000", \ - "0.1374594000, 0.1389749000, 0.1452969000, 0.1735626000, 0.2969403000, 0.8050621000, 2.7883007000"); - } - } - max_capacitance : 1.6818330000; - max_transition : 1.5007520000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019354100, 0.0074916000, 0.0289986000, 0.1122480000, 0.4344910000, 1.6818300000"); - values("0.0152930000, 0.0158333000, 0.0177892000, 0.0242292000, 0.0463429000, 0.1299108000, 0.4538259000", \ - "0.0188253000, 0.0194521000, 0.0215532000, 0.0281749000, 0.0504815000, 0.1343457000, 0.4582893000", \ - "0.0229632000, 0.0239117000, 0.0272025000, 0.0368235000, 0.0608603000, 0.1450231000, 0.4687391000", \ - "0.0254070000, 0.0268786000, 0.0320302000, 0.0471170000, 0.0826403000, 0.1696619000, 0.4924210000", \ - "0.0210408000, 0.0233437000, 0.0313762000, 0.0549018000, 0.1106650000, 0.2270754000, 0.5504865000", \ - "-0.003563900, 1.840000e-05, 0.0123568000, 0.0487574000, 0.1365364000, 0.3142955000, 0.6832507000", \ - "-0.080721300, -0.075057500, -0.056605800, -0.000913900, 0.1341887000, 0.4148222000, 0.9557204000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019354100, 0.0074916000, 0.0289986000, 0.1122480000, 0.4344910000, 1.6818300000"); - values("0.0244637000, 0.0256173000, 0.0298987000, 0.0444630000, 0.0949800000, 0.2856741000, 1.0256670000", \ - "0.0293181000, 0.0304239000, 0.0344107000, 0.0487690000, 0.0998363000, 0.2905712000, 1.0239755000", \ - "0.0418382000, 0.0431627000, 0.0475056000, 0.0612770000, 0.1121823000, 0.3035129000, 1.0346417000", \ - "0.0616400000, 0.0637383000, 0.0709355000, 0.0910300000, 0.1431699000, 0.3341031000, 1.0729195000", \ - "0.0944502000, 0.0976167000, 0.1086020000, 0.1408403000, 0.2159773000, 0.4070581000, 1.1408607000", \ - "0.1531090000, 0.1576815000, 0.1737020000, 0.2227999000, 0.3401355000, 0.5801024000, 1.3090837000", \ - "0.2686322000, 0.2748245000, 0.2970122000, 0.3678749000, 0.5477521000, 0.9217622000, 1.7041840000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019354100, 0.0074916000, 0.0289986000, 0.1122480000, 0.4344910000, 1.6818300000"); - values("0.0065605000, 0.0070460000, 0.0090156000, 0.0170993000, 0.0492442000, 0.1747627000, 0.6592694000", \ - "0.0077545000, 0.0081687000, 0.0098562000, 0.0173326000, 0.0493403000, 0.1748288000, 0.6599624000", \ - "0.0122431000, 0.0128359000, 0.0151293000, 0.0225164000, 0.0503217000, 0.1746397000, 0.6601223000", \ - "0.0208532000, 0.0216998000, 0.0249784000, 0.0349794000, 0.0630429000, 0.1749580000, 0.6604945000", \ - "0.0364075000, 0.0379101000, 0.0430022000, 0.0577685000, 0.0953186000, 0.1974999000, 0.6590105000", \ - "0.0650616000, 0.0669402000, 0.0747888000, 0.0981152000, 0.1536593000, 0.2800197000, 0.6833182000", \ - "0.1193746000, 0.1228139000, 0.1347092000, 0.1710026000, 0.2540403000, 0.4320174000, 0.8453999000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019354100, 0.0074916000, 0.0289986000, 0.1122480000, 0.4344910000, 1.6818300000"); - values("0.0138044000, 0.0150460000, 0.0198161000, 0.0386202000, 0.1116631000, 0.3939241000, 1.4836817000", \ - "0.0140210000, 0.0152017000, 0.0199031000, 0.0385668000, 0.1113631000, 0.3935619000, 1.4872183000", \ - "0.0188524000, 0.0196174000, 0.0230981000, 0.0391955000, 0.1115320000, 0.3936547000, 1.4838160000", \ - "0.0307897000, 0.0320439000, 0.0370288000, 0.0515338000, 0.1128347000, 0.3925901000, 1.4850964000", \ - "0.0495808000, 0.0517571000, 0.0593213000, 0.0811927000, 0.1383305000, 0.3924309000, 1.4797776000", \ - "0.0802118000, 0.0836347000, 0.0956465000, 0.1303082000, 0.2111467000, 0.4273958000, 1.4814652000", \ - "0.1361709000, 0.1405824000, 0.1566964000, 0.2082857000, 0.3366694000, 0.5981944000, 1.5007523000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_2") { - leakage_power () { - value : 0.0079423000; - when : "A"; - } - leakage_power () { - value : 0.0005535000; - when : "!A"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0042479070; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0044590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042760000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046420000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014764110, 0.0043595770, 0.0128730500, 0.0380118100, 0.1122421000, 0.3314308000"); - values("-0.004872900, -0.006180700, -0.010453400, -0.023931400, -0.064515700, -0.184718100, -0.539778600", \ - "-0.005354600, -0.006681800, -0.010863900, -0.024165200, -0.064604400, -0.184753500, -0.539797800", \ - "-0.005688900, -0.007092100, -0.011387800, -0.024547400, -0.064787200, -0.184817000, -0.539825700", \ - "-0.005417200, -0.007053000, -0.011521900, -0.024937800, -0.065092600, -0.184962400, -0.539885700", \ - "-0.004931500, -0.006566900, -0.011345100, -0.024948000, -0.065357200, -0.185164900, -0.539963400", \ - "-0.002729700, -0.004576800, -0.009821000, -0.023764500, -0.064850300, -0.185216200, -0.540020800", \ - "0.0026942000, 0.0005644000, -0.005112800, -0.020675300, -0.062857500, -0.184263200, -0.539774700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014764110, 0.0043595770, 0.0128730500, 0.0380118100, 0.1122421000, 0.3314308000"); - values("0.0129073000, 0.0147627000, 0.0198879000, 0.0340719000, 0.0747268000, 0.1938930000, 0.5478985000", \ - "0.0126104000, 0.0143517000, 0.0194124000, 0.0336506000, 0.0744926000, 0.1940106000, 0.5436985000", \ - "0.0125047000, 0.0143132000, 0.0190767000, 0.0331759000, 0.0742976000, 0.1924800000, 0.5446534000", \ - "0.0126884000, 0.0144153000, 0.0189569000, 0.0328509000, 0.0734457000, 0.1937375000, 0.5453426000", \ - "0.0135492000, 0.0149941000, 0.0194349000, 0.0329725000, 0.0731844000, 0.1931974000, 0.5464750000", \ - "0.0149532000, 0.0163193000, 0.0205688000, 0.0337550000, 0.0737759000, 0.1921072000, 0.5425809000", \ - "0.0206515000, 0.0217040000, 0.0253143000, 0.0377926000, 0.0767143000, 0.1949605000, 0.5439724000"); - } - } - max_capacitance : 0.3314310000; - max_transition : 1.4978170000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014764100, 0.0043595800, 0.0128730000, 0.0380118000, 0.1122420000, 0.3314310000"); - values("0.0119446000, 0.0137840000, 0.0188149000, 0.0327326000, 0.0729366000, 0.1922578000, 0.5454940000", \ - "0.0157429000, 0.0180991000, 0.0233701000, 0.0374622000, 0.0781416000, 0.1961942000, 0.5456924000", \ - "0.0203785000, 0.0240707000, 0.0324561000, 0.0487044000, 0.0892794000, 0.2076327000, 0.5571236000", \ - "0.0248258000, 0.0307580000, 0.0439276000, 0.0689207000, 0.1156458000, 0.2359077000, 0.5860208000", \ - "0.0262075000, 0.0354142000, 0.0559354000, 0.0961932000, 0.1673476000, 0.2955090000, 0.6455342000", \ - "0.0157468000, 0.0301166000, 0.0619237000, 0.1246900000, 0.2371069000, 0.4263973000, 0.7871234000", \ - "-0.027559700, -0.005392600, 0.0434940000, 0.1403033000, 0.3151930000, 0.6122458000, 1.1101468000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014764100, 0.0043595800, 0.0128730000, 0.0380118000, 0.1122420000, 0.3314310000"); - values("0.0175587000, 0.0211484000, 0.0310262000, 0.0584472000, 0.1371815000, 0.3662591000, 1.0435811000", \ - "0.0230691000, 0.0264576000, 0.0360719000, 0.0633862000, 0.1425054000, 0.3734522000, 1.0627602000", \ - "0.0339028000, 0.0388338000, 0.0493056000, 0.0760130000, 0.1545360000, 0.3864530000, 1.0598706000", \ - "0.0498930000, 0.0577606000, 0.0750599000, 0.1075488000, 0.1862726000, 0.4152755000, 1.0963705000", \ - "0.0744968000, 0.0868541000, 0.1145327000, 0.1673453000, 0.2583118000, 0.4867961000, 1.1619753000", \ - "0.1156072000, 0.1340389000, 0.1760385000, 0.2596266000, 0.4057179000, 0.6556388000, 1.3298844000", \ - "0.1928740000, 0.2183706000, 0.2783548000, 0.4048308000, 0.6381117000, 1.0233501000, 1.7170592000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014764100, 0.0043595800, 0.0128730000, 0.0380118000, 0.1122420000, 0.3314310000"); - values("0.0048909000, 0.0069497000, 0.0130525000, 0.0311683000, 0.0847074000, 0.2419201000, 0.7066229000", \ - "0.0069554000, 0.0084546000, 0.0135709000, 0.0312350000, 0.0846748000, 0.2428864000, 0.7101457000", \ - "0.0116927000, 0.0141965000, 0.0197198000, 0.0335758000, 0.0847194000, 0.2435099000, 0.7091378000", \ - "0.0203289000, 0.0240677000, 0.0323348000, 0.0495335000, 0.0902360000, 0.2418217000, 0.7064893000", \ - "0.0354595000, 0.0413981000, 0.0546071000, 0.0793592000, 0.1253289000, 0.2517686000, 0.7084765000", \ - "0.0637251000, 0.0731900000, 0.0941919000, 0.1324136000, 0.2017282000, 0.3250714000, 0.7157009000", \ - "0.1183897000, 0.1329738000, 0.1635937000, 0.2237756000, 0.3292207000, 0.5112171000, 0.8526758000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014764100, 0.0043595800, 0.0128730000, 0.0380118000, 0.1122420000, 0.3314310000"); - values("0.0102030000, 0.0145665000, 0.0274391000, 0.0655113000, 0.1778623000, 0.5106880000, 1.4869649000", \ - "0.0107758000, 0.0146772000, 0.0273936000, 0.0654823000, 0.1774442000, 0.5091666000, 1.4832895000", \ - "0.0176433000, 0.0206470000, 0.0298357000, 0.0653682000, 0.1774688000, 0.5082211000, 1.4799179000", \ - "0.0287666000, 0.0338285000, 0.0452178000, 0.0722948000, 0.1771081000, 0.5095251000, 1.4848178000", \ - "0.0472331000, 0.0557641000, 0.0742180000, 0.1079812000, 0.1903953000, 0.5072639000, 1.4842672000", \ - "0.0774171000, 0.0903774000, 0.1203311000, 0.1758978000, 0.2700296000, 0.5253227000, 1.4794522000", \ - "0.1325493000, 0.1519492000, 0.1976181000, 0.2847110000, 0.4388531000, 0.6966839000, 1.4978170000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_4") { - leakage_power () { - value : 0.0074091000; - when : "A"; - } - leakage_power () { - value : 0.0015164000; - when : "!A"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0044627330; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0090040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086000000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0094080000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016127510, 0.0052019320, 0.0167788400, 0.0541201900, 0.1745648000, 0.5630591000"); - values("-0.008451400, -0.009880900, -0.014971700, -0.032921400, -0.093053200, -0.288042800, -0.917349100", \ - "-0.009451600, -0.010960200, -0.015935200, -0.033523000, -0.093247600, -0.288115500, -0.917391700", \ - "-0.010269900, -0.011829900, -0.016978200, -0.034467100, -0.093737800, -0.288264700, -0.917419800", \ - "-0.010436900, -0.012138800, -0.017483800, -0.035422700, -0.094399700, -0.288565100, -0.917547500", \ - "-0.009055600, -0.010931200, -0.016856100, -0.035390000, -0.095277800, -0.289054500, -0.917716900", \ - "-0.005590600, -0.006977500, -0.013778700, -0.032831400, -0.094059800, -0.289007700, -0.917863100", \ - "0.0043734000, 0.0017246000, -0.005377400, -0.027012600, -0.090442300, -0.284430300, -0.916375900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016127510, 0.0052019320, 0.0167788400, 0.0541201900, 0.1745648000, 0.5630591000"); - values("0.0256205000, 0.0278349000, 0.0345681000, 0.0543527000, 0.1148598000, 0.3082690000, 0.9322412000", \ - "0.0250545000, 0.0271237000, 0.0334835000, 0.0534180000, 0.1143068000, 0.3084980000, 0.9313100000", \ - "0.0247994000, 0.0267260000, 0.0328323000, 0.0520222000, 0.1131029000, 0.3078423000, 0.9258184000", \ - "0.0250401000, 0.0268387000, 0.0326378000, 0.0519108000, 0.1121986000, 0.3066267000, 0.9276555000", \ - "0.0263479000, 0.0280637000, 0.0335432000, 0.0519775000, 0.1113991000, 0.3069891000, 0.9282885000", \ - "0.0290579000, 0.0307895000, 0.0351982000, 0.0532784000, 0.1129382000, 0.3043172000, 0.9301420000", \ - "0.0402571000, 0.0406549000, 0.0445595000, 0.0624209000, 0.1186249000, 0.3124213000, 0.9257100000"); - } - } - max_capacitance : 0.5630590000; - max_transition : 1.5002550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016127500, 0.0052019300, 0.0167788000, 0.0541202000, 0.1745650000, 0.5630590000"); - values("0.0119441000, 0.0131118000, 0.0165791000, 0.0269376000, 0.0588054000, 0.1629306000, 0.4909586000", \ - "0.0156473000, 0.0171343000, 0.0209993000, 0.0315480000, 0.0634309000, 0.1663003000, 0.4954380000", \ - "0.0198136000, 0.0221854000, 0.0283758000, 0.0422551000, 0.0746385000, 0.1770034000, 0.5087731000", \ - "0.0232107000, 0.0269733000, 0.0367368000, 0.0585419000, 0.1002393000, 0.2026346000, 0.5338917000", \ - "0.0216104000, 0.0276301000, 0.0429641000, 0.0770100000, 0.1427411000, 0.2629926000, 0.5917846000", \ - "0.0048442000, 0.0139726000, 0.0377789000, 0.0904055000, 0.1929853000, 0.3781642000, 0.7304123000", \ - "-0.053742200, -0.039839200, -0.003689300, 0.0783581000, 0.2392779000, 0.5265917000, 1.0342573000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016127500, 0.0052019300, 0.0167788000, 0.0541202000, 0.1745650000, 0.5630590000"); - values("0.0190114000, 0.0215393000, 0.0291288000, 0.0516131000, 0.1202000000, 0.3388957000, 1.0502127000", \ - "0.0245228000, 0.0268413000, 0.0340168000, 0.0565974000, 0.1254323000, 0.3475673000, 1.0493975000", \ - "0.0363076000, 0.0395220000, 0.0475006000, 0.0689426000, 0.1381457000, 0.3582837000, 1.0632979000", \ - "0.0540201000, 0.0592453000, 0.0722161000, 0.1008018000, 0.1697215000, 0.3898457000, 1.1047234000", \ - "0.0821914000, 0.0901583000, 0.1112681000, 0.1572504000, 0.2433978000, 0.4624623000, 1.1637457000", \ - "0.1312726000, 0.1430227000, 0.1746365000, 0.2465241000, 0.3849189000, 0.6321969000, 1.3318200000", \ - "0.2255666000, 0.2420417000, 0.2873321000, 0.3934108000, 0.6110205000, 1.0017863000, 1.7277610000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016127500, 0.0052019300, 0.0167788000, 0.0541202000, 0.1745650000, 0.5630590000"); - values("0.0049571000, 0.0062375000, 0.0103719000, 0.0238937000, 0.0668871000, 0.2087285000, 0.6548602000", \ - "0.0070977000, 0.0080130000, 0.0112236000, 0.0238611000, 0.0670169000, 0.2058758000, 0.6553406000", \ - "0.0116617000, 0.0131789000, 0.0173638000, 0.0276296000, 0.0669909000, 0.2060657000, 0.6575888000", \ - "0.0202925000, 0.0226678000, 0.0287989000, 0.0429853000, 0.0756389000, 0.2062924000, 0.6550083000", \ - "0.0354624000, 0.0390051000, 0.0489234000, 0.0703691000, 0.1125576000, 0.2207891000, 0.6543583000", \ - "0.0636220000, 0.0696130000, 0.0849741000, 0.1179729000, 0.1810032000, 0.3041805000, 0.6730234000", \ - "0.1177379000, 0.1271844000, 0.1500653000, 0.2014630000, 0.2996650000, 0.4817202000, 0.8318283000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016127500, 0.0052019300, 0.0167788000, 0.0541202000, 0.1745650000, 0.5630590000"); - values("0.0114302000, 0.0142771000, 0.0237116000, 0.0540961000, 0.1514573000, 0.4651357000, 1.4865850000", \ - "0.0115673000, 0.0143379000, 0.0237317000, 0.0540688000, 0.1513773000, 0.4700103000, 1.4776085000", \ - "0.0182523000, 0.0199466000, 0.0265154000, 0.0540666000, 0.1514956000, 0.4667554000, 1.4746315000", \ - "0.0294702000, 0.0329037000, 0.0417888000, 0.0631231000, 0.1514760000, 0.4667907000, 1.4800738000", \ - "0.0482627000, 0.0545717000, 0.0680175000, 0.0974604000, 0.1686737000, 0.4681324000, 1.4801701000", \ - "0.0791388000, 0.0869239000, 0.1099131000, 0.1596422000, 0.2484881000, 0.4876861000, 1.4865859000", \ - "0.1335121000, 0.1448872000, 0.1779738000, 0.2570885000, 0.4026016000, 0.6618689000, 1.5002554000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_6") { - leakage_power () { - value : 0.0063222000; - when : "A"; - } - leakage_power () { - value : 0.0027400000; - when : "!A"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0045311230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0132720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0126560000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0138880000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017037880, 0.0058057850, 0.0197836500, 0.0674142800, 0.2297192000, 0.7827856000"); - values("-0.012040500, -0.013536200, -0.019185500, -0.040635500, -0.117175700, -0.379877800, -1.275807700", \ - "-0.013435100, -0.015051500, -0.020647400, -0.041555200, -0.117520200, -0.380020900, -1.275826900", \ - "-0.014580100, -0.016273400, -0.022209600, -0.042960600, -0.118205000, -0.380211700, -1.275896400", \ - "-0.014917600, -0.016753300, -0.023091900, -0.044367900, -0.119257600, -0.380758200, -1.276055300", \ - "-0.012989400, -0.015027900, -0.021817900, -0.044217800, -0.120608700, -0.381304300, -1.276281600", \ - "-0.007528300, -0.010157500, -0.017823000, -0.041501400, -0.119599100, -0.381384900, -1.276548400", \ - "0.0053734000, 0.0025006000, -0.005930900, -0.032119700, -0.113754600, -0.378985900, -1.276226700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017037880, 0.0058057850, 0.0197836500, 0.0674142800, 0.2297192000, 0.7827856000"); - values("0.0372289000, 0.0396745000, 0.0475425000, 0.0717774000, 0.1486724000, 0.4106380000, 1.2969808000", \ - "0.0363842000, 0.0386355000, 0.0460013000, 0.0702128000, 0.1488077000, 0.4105570000, 1.2915005000", \ - "0.0363549000, 0.0383815000, 0.0451807000, 0.0689245000, 0.1472120000, 0.4067674000, 1.2961825000", \ - "0.0363385000, 0.0383716000, 0.0450749000, 0.0678419000, 0.1456459000, 0.4070054000, 1.2904290000", \ - "0.0379655000, 0.0397982000, 0.0461793000, 0.0683600000, 0.1444188000, 0.4050739000, 1.2852116000", \ - "0.0412776000, 0.0429827000, 0.0489436000, 0.0707427000, 0.1469712000, 0.4047435000, 1.2909248000", \ - "0.0545098000, 0.0557124000, 0.0607111000, 0.0806870000, 0.1535036000, 0.4113238000, 1.2919484000"); - } - } - max_capacitance : 0.7827860000; - max_transition : 1.4987990000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0121626000, 0.0130390000, 0.0158050000, 0.0243453000, 0.0520500000, 0.1460250000, 0.4636161000", \ - "0.0157169000, 0.0168518000, 0.0201011000, 0.0288332000, 0.0567592000, 0.1501568000, 0.4744309000", \ - "0.0194953000, 0.0213527000, 0.0265780000, 0.0389163000, 0.0674634000, 0.1612821000, 0.4794447000", \ - "0.0221779000, 0.0250280000, 0.0331905000, 0.0526953000, 0.0923631000, 0.1868675000, 0.5067819000", \ - "0.0188301000, 0.0233264000, 0.0361217000, 0.0669581000, 0.1293595000, 0.2459305000, 0.5634868000", \ - "-0.002575600, 0.0043257000, 0.0242317000, 0.0724837000, 0.1705254000, 0.3520171000, 0.7008762000", \ - "-0.071733700, -0.060923200, -0.030404600, 0.0434575000, 0.1969213000, 0.4830984000, 0.9949482000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0198874000, 0.0219117000, 0.0283486000, 0.0482353000, 0.1114341000, 0.3257839000, 1.0487834000", \ - "0.0254196000, 0.0272530000, 0.0332581000, 0.0529931000, 0.1173929000, 0.3319309000, 1.0567558000", \ - "0.0377313000, 0.0402749000, 0.0469218000, 0.0660069000, 0.1302518000, 0.3433506000, 1.0672999000", \ - "0.0563277000, 0.0603888000, 0.0715674000, 0.0978348000, 0.1609684000, 0.3756943000, 1.1008856000", \ - "0.0866407000, 0.0929499000, 0.1107897000, 0.1527173000, 0.2361139000, 0.4464785000, 1.1692750000", \ - "0.1405014000, 0.1496439000, 0.1765140000, 0.2420710000, 0.3759929000, 0.6214167000, 1.3457259000", \ - "0.2459307000, 0.2585686000, 0.2961936000, 0.3933225000, 0.6009813000, 0.9883367000, 1.7423613000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0049390000, 0.0058765000, 0.0090927000, 0.0202020000, 0.0582046000, 0.1879998000, 0.6266480000", \ - "0.0070209000, 0.0077683000, 0.0101933000, 0.0203458000, 0.0585240000, 0.1871754000, 0.6311019000", \ - "0.0115069000, 0.0126549000, 0.0161598000, 0.0251246000, 0.0585647000, 0.1874807000, 0.6277085000", \ - "0.0198473000, 0.0216621000, 0.0267878000, 0.0396990000, 0.0695373000, 0.1878979000, 0.6270980000", \ - "0.0348922000, 0.0379268000, 0.0466255000, 0.0649322000, 0.1054989000, 0.2055238000, 0.6276912000", \ - "0.0627123000, 0.0672251000, 0.0802171000, 0.1100470000, 0.1698476000, 0.2924350000, 0.6482923000", \ - "0.1172122000, 0.1235793000, 0.1429264000, 0.1895538000, 0.2832351000, 0.4582241000, 0.8137574000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017037900, 0.0058057800, 0.0197837000, 0.0674143000, 0.2297190000, 0.7827860000"); - values("0.0117548000, 0.0139830000, 0.0217198000, 0.0481809000, 0.1376070000, 0.4453319000, 1.4887607000", \ - "0.0118519000, 0.0140570000, 0.0217247000, 0.0481707000, 0.1385627000, 0.4457909000, 1.4845526000", \ - "0.0181901000, 0.0195191000, 0.0247008000, 0.0481613000, 0.1382910000, 0.4431177000, 1.4838308000", \ - "0.0294000000, 0.0321571000, 0.0396593000, 0.0583166000, 0.1380307000, 0.4454077000, 1.4806307000", \ - "0.0481114000, 0.0523180000, 0.0645136000, 0.0918628000, 0.1567508000, 0.4437891000, 1.4848648000", \ - "0.0786950000, 0.0853608000, 0.1043235000, 0.1497862000, 0.2361527000, 0.4681922000, 1.4838263000", \ - "0.1337186000, 0.1428984000, 0.1703253000, 0.2400066000, 0.3819317000, 0.6393036000, 1.4987989000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__inv_8") { - leakage_power () { - value : 0.0082791000; - when : "A"; - } - leakage_power () { - value : 0.0038210000; - when : "!A"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__inv"; - cell_leakage_power : 0.0060500540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0176530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0168400000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0184670000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017851090, 0.0063732260, 0.0227538000, 0.0812360200, 0.2900303000, 1.0354710000"); - values("-0.015426100, -0.017031700, -0.023203100, -0.048025700, -0.141756500, -0.479709900, -1.687156600", \ - "-0.017287400, -0.019023500, -0.025157200, -0.049371900, -0.142235500, -0.479822600, -1.687276100", \ - "-0.018889200, -0.020716100, -0.027260400, -0.051365100, -0.143363300, -0.480162500, -1.687365700", \ - "-0.019349100, -0.021354700, -0.028201800, -0.053315000, -0.145097800, -0.480914900, -1.687397500", \ - "-0.016866600, -0.019047500, -0.026670600, -0.052967000, -0.146290000, -0.481858200, -1.687955100", \ - "-0.009756300, -0.012544400, -0.021248200, -0.049267200, -0.143573400, -0.482199100, -1.688358100", \ - "0.0074301000, 0.0042855000, -0.005131200, -0.036199500, -0.136855400, -0.478916000, -1.688094700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017851090, 0.0063732260, 0.0227538000, 0.0812360200, 0.2900303000, 1.0354710000"); - values("0.0500517000, 0.0526781000, 0.0616626000, 0.0907907000, 0.1858872000, 0.5229385000, 1.7159675000", \ - "0.0489046000, 0.0513336000, 0.0597713000, 0.0884790000, 0.1843756000, 0.5199276000, 1.7200452000", \ - "0.0488000000, 0.0510048000, 0.0586787000, 0.0865749000, 0.1839729000, 0.5171257000, 1.7152928000", \ - "0.0488373000, 0.0510046000, 0.0583381000, 0.0856850000, 0.1809917000, 0.5195810000, 1.7148138000", \ - "0.0509897000, 0.0529823000, 0.0600315000, 0.0859068000, 0.1795073000, 0.5171847000, 1.7103024000", \ - "0.0552576000, 0.0570631000, 0.0636992000, 0.0889754000, 0.1826954000, 0.5123181000, 1.7093391000", \ - "0.0728096000, 0.0741087000, 0.0795625000, 0.1022556000, 0.1917460000, 0.5219979000, 1.7044405000"); - } - } - max_capacitance : 1.0354710000; - max_transition : 1.4996250000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017851100, 0.0063732300, 0.0227538000, 0.0812360000, 0.2900300000, 1.0354700000"); - values("0.0123297000, 0.0130319000, 0.0154135000, 0.0230701000, 0.0489012000, 0.1402316000, 0.4666703000", \ - "0.0159471000, 0.0168723000, 0.0196942000, 0.0275204000, 0.0536900000, 0.1451606000, 0.4703811000", \ - "0.0197728000, 0.0212245000, 0.0258394000, 0.0373346000, 0.0644274000, 0.1556234000, 0.4815072000", \ - "0.0224926000, 0.0248146000, 0.0318879000, 0.0500402000, 0.0889616000, 0.1814948000, 0.5052737000", \ - "0.0191159000, 0.0227360000, 0.0337779000, 0.0625044000, 0.1231077000, 0.2404573000, 0.5653590000", \ - "-0.002589400, 0.0030309000, 0.0201839000, 0.0651178000, 0.1601613000, 0.3434292000, 0.7014345000", \ - "-0.072666000, -0.063999000, -0.037823900, 0.0310945000, 0.1805251000, 0.4688840000, 0.9955849000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017851100, 0.0063732300, 0.0227538000, 0.0812360000, 0.2900300000, 1.0354700000"); - values("0.0202742000, 0.0219295000, 0.0275017000, 0.0455936000, 0.1049458000, 0.3147736000, 1.0550638000", \ - "0.0257929000, 0.0273028000, 0.0325167000, 0.0502622000, 0.1101536000, 0.3218706000, 1.0694470000", \ - "0.0382296000, 0.0403048000, 0.0461477000, 0.0631958000, 0.1234292000, 0.3310772000, 1.0747949000", \ - "0.0571632000, 0.0604406000, 0.0699357000, 0.0942658000, 0.1538116000, 0.3634873000, 1.1030601000", \ - "0.0880401000, 0.0931328000, 0.1086796000, 0.1474176000, 0.2291143000, 0.4343165000, 1.1747938000", \ - "0.1428338000, 0.1501958000, 0.1732611000, 0.2337166000, 0.3640337000, 0.6095962000, 1.3501105000", \ - "0.2501082000, 0.2603140000, 0.2927534000, 0.3813830000, 0.5841018000, 0.9721643000, 1.7479136000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017851100, 0.0063732300, 0.0227538000, 0.0812360000, 0.2900300000, 1.0354700000"); - values("0.0050158000, 0.0057564000, 0.0084430000, 0.0181318000, 0.0525400000, 0.1754386000, 0.6195076000", \ - "0.0070648000, 0.0076214000, 0.0095686000, 0.0181883000, 0.0527483000, 0.1765888000, 0.6151475000", \ - "0.0116018000, 0.0125604000, 0.0153961000, 0.0233952000, 0.0533055000, 0.1758861000, 0.6146265000", \ - "0.0200380000, 0.0216953000, 0.0260132000, 0.0374396000, 0.0647711000, 0.1753940000, 0.6144052000", \ - "0.0352642000, 0.0377053000, 0.0447282000, 0.0622156000, 0.1008997000, 0.1941964000, 0.6150727000", \ - "0.0632523000, 0.0669490000, 0.0782894000, 0.1059187000, 0.1652254000, 0.2829769000, 0.6345332000", \ - "0.1174102000, 0.1230575000, 0.1396005000, 0.1834808000, 0.2740662000, 0.4483394000, 0.8027686000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017851100, 0.0063732300, 0.0227538000, 0.0812360000, 0.2900300000, 1.0354700000"); - values("0.0119599000, 0.0138121000, 0.0203450000, 0.0438593000, 0.1268351000, 0.4257829000, 1.4839129000", \ - "0.0120751000, 0.0138756000, 0.0203696000, 0.0437900000, 0.1265724000, 0.4254328000, 1.4898222000", \ - "0.0180851000, 0.0192025000, 0.0235640000, 0.0438997000, 0.1280050000, 0.4225611000, 1.4858990000", \ - "0.0296468000, 0.0318590000, 0.0383461000, 0.0549473000, 0.1276238000, 0.4272980000, 1.4821471000", \ - "0.0485468000, 0.0519465000, 0.0622100000, 0.0877744000, 0.1483328000, 0.4255445000, 1.4844611000", \ - "0.0794384000, 0.0848726000, 0.1020007000, 0.1425726000, 0.2278606000, 0.4510004000, 1.4871820000", \ - "0.1345213000, 0.1419485000, 0.1656099000, 0.2296689000, 0.3676179000, 0.6189584000, 1.4996250000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_bleeder_1") { - leakage_power () { - value : 101865.71000; - when : "SHORT"; - } - leakage_power () { - value : 1.5808252e-05; - when : "!SHORT"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__bleeder"; - cell_leakage_power : 50932.860000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("SHORT") { - always_on : "true"; - capacitance : 0.0021860000; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.048912400, -0.167236200, -0.284881900, -0.401285200, -0.514504300, -0.620383500, -0.709343600"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0407359000, 0.0391999000, 0.0356593000, 0.0575931000, 0.1081521000, 0.2246933000, 0.4933273000"); - } - } - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0021380000; - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_1") { - leakage_power () { - value : 0.0011810000; - when : "A"; - } - leakage_power () { - value : 0.0011810000; - when : "!A"; - } - always_on : "true"; - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__clkbufkapwr"; - cell_leakage_power : 0.0011810180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0020970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020100000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0021850000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012646830, 0.0031988470, 0.0080910560, 0.0204652400, 0.0517641000, 0.1309304000"); - values("0.0109236000, 0.0099024000, 0.0070514000, -0.000731900, -0.020752800, -0.071473500, -0.199782000", \ - "0.0106888000, 0.0096613000, 0.0068073000, -0.000956100, -0.020934500, -0.071686500, -0.199930100", \ - "0.0104505000, 0.0094218000, 0.0065835000, -0.001160600, -0.021160000, -0.071841300, -0.200099300", \ - "0.0103318000, 0.0092847000, 0.0064471000, -0.001265200, -0.021185900, -0.071876900, -0.200108200", \ - "0.0101754000, 0.0089676000, 0.0062834000, -0.001240300, -0.021140000, -0.071773000, -0.200025400", \ - "0.0110656000, 0.0098791000, 0.0069820000, -0.000960100, -0.020529800, -0.071153300, -0.199357100", \ - "0.0131194000, 0.0118824000, 0.0086705000, 0.0007827000, -0.019035200, -0.069529700, -0.197628100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012646830, 0.0031988470, 0.0080910560, 0.0204652400, 0.0517641000, 0.1309304000"); - values("0.0056625000, 0.0069714000, 0.0101718000, 0.0180150000, 0.0378571000, 0.0877095000, 0.2146676000", \ - "0.0054706000, 0.0067828000, 0.0099809000, 0.0178435000, 0.0376617000, 0.0878595000, 0.2144578000", \ - "0.0051964000, 0.0064945000, 0.0096761000, 0.0176208000, 0.0374958000, 0.0880417000, 0.2151342000", \ - "0.0049778000, 0.0062629000, 0.0094336000, 0.0173357000, 0.0372716000, 0.0876729000, 0.2145099000", \ - "0.0050756000, 0.0063516000, 0.0094068000, 0.0173055000, 0.0371718000, 0.0879282000, 0.2139725000", \ - "0.0057466000, 0.0069988000, 0.0101452000, 0.0179191000, 0.0378803000, 0.0878130000, 0.2151992000", \ - "0.0077405000, 0.0088582000, 0.0119881000, 0.0198483000, 0.0396653000, 0.0899139000, 0.2163168000"); - } - } - max_capacitance : 0.1309300000; - max_transition : 1.5048300000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012646800, 0.0031988500, 0.0080910600, 0.0204652000, 0.0517641000, 0.1309300000"); - values("0.0597752000, 0.0648087000, 0.0754631000, 0.0979458000, 0.1501913000, 0.2806566000, 0.6104133000", \ - "0.0647452000, 0.0697583000, 0.0803774000, 0.1030746000, 0.1553850000, 0.2860113000, 0.6150983000", \ - "0.0780199000, 0.0830714000, 0.0937246000, 0.1163172000, 0.1685797000, 0.2992097000, 0.6290619000", \ - "0.1083181000, 0.1134532000, 0.1243078000, 0.1471400000, 0.1994631000, 0.3299487000, 0.6604344000", \ - "0.1586997000, 0.1648189000, 0.1771293000, 0.2017393000, 0.2554418000, 0.3849019000, 0.7154178000", \ - "0.2355097000, 0.2435301000, 0.2588723000, 0.2863268000, 0.3414032000, 0.4724898000, 0.8020601000", \ - "0.3576046000, 0.3679077000, 0.3875696000, 0.4216440000, 0.4813723000, 0.6134638000, 0.9441941000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012646800, 0.0031988500, 0.0080910600, 0.0204652000, 0.0517641000, 0.1309300000"); - values("0.0495450000, 0.0562766000, 0.0721427000, 0.1108310000, 0.2080660000, 0.4524981000, 1.0712415000", \ - "0.0541153000, 0.0608004000, 0.0766816000, 0.1153471000, 0.2120808000, 0.4593231000, 1.0764903000", \ - "0.0646658000, 0.0713398000, 0.0870399000, 0.1259932000, 0.2238772000, 0.4691099000, 1.0885717000", \ - "0.0825729000, 0.0894519000, 0.1055740000, 0.1445091000, 0.2431764000, 0.4894891000, 1.1082103000", \ - "0.1050800000, 0.1123840000, 0.1288357000, 0.1677908000, 0.2654047000, 0.5109333000, 1.1299768000", \ - "0.1271945000, 0.1360945000, 0.1538811000, 0.1927381000, 0.2910673000, 0.5360059000, 1.1556306000", \ - "0.1311566000, 0.1430638000, 0.1655261000, 0.2078080000, 0.3048816000, 0.5506122000, 1.1706536000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012646800, 0.0031988500, 0.0080910600, 0.0204652000, 0.0517641000, 0.1309300000"); - values("0.0151864000, 0.0195771000, 0.0298734000, 0.0554573000, 0.1229030000, 0.2970159000, 0.7358885000", \ - "0.0151386000, 0.0195753000, 0.0298881000, 0.0554187000, 0.1224622000, 0.2961846000, 0.7351432000", \ - "0.0151571000, 0.0195948000, 0.0299025000, 0.0555874000, 0.1223156000, 0.2973758000, 0.7316103000", \ - "0.0162744000, 0.0205511000, 0.0305954000, 0.0558095000, 0.1222031000, 0.2954658000, 0.7360981000", \ - "0.0213685000, 0.0254291000, 0.0352512000, 0.0595608000, 0.1240195000, 0.2964936000, 0.7339139000", \ - "0.0304840000, 0.0350455000, 0.0448111000, 0.0672711000, 0.1286269000, 0.2960232000, 0.7386328000", \ - "0.0441702000, 0.0501058000, 0.0607775000, 0.0826757000, 0.1383536000, 0.3005787000, 0.7335437000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012646800, 0.0031988500, 0.0080910600, 0.0204652000, 0.0517641000, 0.1309300000"); - values("0.0203281000, 0.0287410000, 0.0503554000, 0.1056378000, 0.2466223000, 0.6019099000, 1.5017801000", \ - "0.0203546000, 0.0287441000, 0.0503524000, 0.1057716000, 0.2469060000, 0.6045270000, 1.5012597000", \ - "0.0204572000, 0.0287914000, 0.0502751000, 0.1058520000, 0.2473959000, 0.6058691000, 1.5013557000", \ - "0.0219079000, 0.0300867000, 0.0510608000, 0.1058554000, 0.2470916000, 0.6055951000, 1.5017220000", \ - "0.0252875000, 0.0326643000, 0.0526388000, 0.1066835000, 0.2460179000, 0.6037190000, 1.5046464000", \ - "0.0330773000, 0.0399602000, 0.0573576000, 0.1082203000, 0.2479077000, 0.6006848000, 1.5048297000", \ - "0.0472400000, 0.0547569000, 0.0713040000, 0.1153719000, 0.2487775000, 0.6043901000, 1.4975244000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_16") { - leakage_power () { - value : 0.0141674000; - when : "A"; - } - leakage_power () { - value : 0.0104788000; - when : "!A"; - } - always_on : "true"; - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__clkbufkapwr"; - cell_leakage_power : 0.0123231100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0074310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0069550000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0079060000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019468260, 0.0075802600, 0.0295148900, 0.1149207000, 0.4474612000, 1.7422580000"); - values("0.0907350000, 0.0886142000, 0.0807989000, 0.0501683000, -0.079933800, -0.614897100, -2.711300200", \ - "0.0904772000, 0.0884468000, 0.0805530000, 0.0498039000, -0.080373400, -0.615148300, -2.711219300", \ - "0.0898615000, 0.0878674000, 0.0797941000, 0.0491688000, -0.080979700, -0.615670900, -2.712350300", \ - "0.0891777000, 0.0871684000, 0.0790765000, 0.0481610000, -0.082260400, -0.616574400, -2.712481100", \ - "0.0901622000, 0.0878292000, 0.0795600000, 0.0471332000, -0.084375400, -0.618037600, -2.713380200", \ - "0.0901195000, 0.0877702000, 0.0786716000, 0.0440546000, -0.086203600, -0.618980200, -2.713363300", \ - "0.1001273000, 0.0974900000, 0.0876856000, 0.0517808000, -0.084548600, -0.617549500, -2.710766800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019468260, 0.0075802600, 0.0295148900, 0.1149207000, 0.4474612000, 1.7422580000"); - values("0.0780847000, 0.0806054000, 0.0905175000, 0.1285558000, 0.2699064000, 0.8045055000, 2.8716680000", \ - "0.0777424000, 0.0802616000, 0.0901722000, 0.1282609000, 0.2695022000, 0.8041840000, 2.8691197000", \ - "0.0771485000, 0.0796884000, 0.0895942000, 0.1277346000, 0.2688092000, 0.8036420000, 2.8701199000", \ - "0.0768122000, 0.0793332000, 0.0891322000, 0.1266626000, 0.2674782000, 0.8020854000, 2.8777096000", \ - "0.0765402000, 0.0789161000, 0.0885485000, 0.1249918000, 0.2652665000, 0.8009476000, 2.8805126000", \ - "0.0803735000, 0.0826751000, 0.0917929000, 0.1275942000, 0.2638350000, 0.7976006000, 2.8760626000", \ - "0.0862546000, 0.0883846000, 0.0970767000, 0.1317861000, 0.2707791000, 0.7995469000, 2.8702862000"); - } - } - max_capacitance : 1.7422580000; - max_transition : 1.5106520000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019468300, 0.0075802600, 0.0295149000, 0.1149210000, 0.4474610000, 1.7422600000"); - values("0.1098075000, 0.1114814000, 0.1172031000, 0.1342470000, 0.1795411000, 0.3196717000, 0.8501815000", \ - "0.1153706000, 0.1170161000, 0.1227730000, 0.1396507000, 0.1852784000, 0.3257315000, 0.8544599000", \ - "0.1292180000, 0.1308642000, 0.1365658000, 0.1535479000, 0.1990041000, 0.3391851000, 0.8696274000", \ - "0.1616169000, 0.1632963000, 0.1689825000, 0.1858519000, 0.2312506000, 0.3716021000, 0.9013890000", \ - "0.2354309000, 0.2371197000, 0.2428947000, 0.2597832000, 0.3052948000, 0.4459131000, 0.9751886000", \ - "0.3634298000, 0.3656225000, 0.3730861000, 0.3941073000, 0.4445274000, 0.5875524000, 1.1164865000", \ - "0.5657298000, 0.5686396000, 0.5784484000, 0.6062861000, 0.6689772000, 0.8190893000, 1.3463756000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019468300, 0.0075802600, 0.0295149000, 0.1149210000, 0.4474610000, 1.7422600000"); - values("0.0915560000, 0.0933430000, 0.0995655000, 0.1187422000, 0.1751587000, 0.3720053000, 1.1314958000", \ - "0.0959647000, 0.0977521000, 0.1039825000, 0.1231534000, 0.1796037000, 0.3764609000, 1.1356135000", \ - "0.1068713000, 0.1086614000, 0.1148995000, 0.1340674000, 0.1904654000, 0.3872610000, 1.1469773000", \ - "0.1326075000, 0.1343766000, 0.1406171000, 0.1595690000, 0.2158874000, 0.4132878000, 1.1787691000", \ - "0.1796844000, 0.1816868000, 0.1884660000, 0.2083562000, 0.2656564000, 0.4632844000, 1.2275639000", \ - "0.2405209000, 0.2430168000, 0.2515957000, 0.2754810000, 0.3357479000, 0.5332779000, 1.2930331000", \ - "0.3014802000, 0.3047942000, 0.3160983000, 0.3471669000, 0.4179085000, 0.6163238000, 1.3744784000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019468300, 0.0075802600, 0.0295149000, 0.1149210000, 0.4474610000, 1.7422600000"); - values("0.0226507000, 0.0237630000, 0.0276984000, 0.0411025000, 0.0882766000, 0.2768437000, 1.0356588000", \ - "0.0225277000, 0.0236625000, 0.0277247000, 0.0409836000, 0.0881419000, 0.2765859000, 1.0374283000", \ - "0.0226632000, 0.0238039000, 0.0277491000, 0.0409752000, 0.0882770000, 0.2770919000, 1.0356664000", \ - "0.0225310000, 0.0236548000, 0.0277649000, 0.0408984000, 0.0883930000, 0.2771604000, 1.0358154000", \ - "0.0248039000, 0.0259019000, 0.0296810000, 0.0422732000, 0.0890698000, 0.2767855000, 1.0361536000", \ - "0.0364293000, 0.0376695000, 0.0418211000, 0.0548461000, 0.0975751000, 0.2789966000, 1.0377544000", \ - "0.0555926000, 0.0572457000, 0.0628691000, 0.0783069000, 0.1191547000, 0.2888653000, 1.0360349000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019468300, 0.0075802600, 0.0295149000, 0.1149210000, 0.4474610000, 1.7422600000"); - values("0.0233967000, 0.0247502000, 0.0298535000, 0.0480987000, 0.1175131000, 0.3993638000, 1.5023566000", \ - "0.0233692000, 0.0247547000, 0.0298504000, 0.0480325000, 0.1176042000, 0.3997687000, 1.5034607000", \ - "0.0233504000, 0.0247536000, 0.0298466000, 0.0480955000, 0.1176595000, 0.3997869000, 1.5036801000", \ - "0.0234868000, 0.0248720000, 0.0299134000, 0.0481167000, 0.1176764000, 0.3982417000, 1.5106522000", \ - "0.0284844000, 0.0297353000, 0.0347438000, 0.0519602000, 0.1193753000, 0.3988267000, 1.5066615000", \ - "0.0399487000, 0.0413988000, 0.0462700000, 0.0620486000, 0.1250167000, 0.3987129000, 1.5050353000", \ - "0.0584196000, 0.0604183000, 0.0664954000, 0.0844219000, 0.1411082000, 0.4036162000, 1.5032577000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_2") { - leakage_power () { - value : 0.0036588000; - when : "A"; - } - leakage_power () { - value : 0.0046480000; - when : "!A"; - } - always_on : "true"; - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__clkbufkapwr"; - cell_leakage_power : 0.0041533960; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020560000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0022840000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014371910, 0.0041310370, 0.0118741800, 0.0341309400, 0.0981053700, 0.2819923000"); - values("0.0149480000, 0.0137264000, 0.0100690000, -0.001910500, -0.037757600, -0.141371400, -0.439175100", \ - "0.0147776000, 0.0135816000, 0.0099112000, -0.002046700, -0.037865400, -0.141493900, -0.439305200", \ - "0.0145575000, 0.0133209000, 0.0096118000, -0.002315000, -0.038100400, -0.141704700, -0.439516200", \ - "0.0143100000, 0.0130473000, 0.0092708000, -0.002629600, -0.038291100, -0.141819200, -0.439669400", \ - "0.0138930000, 0.0126396000, 0.0089878000, -0.002885200, -0.038460100, -0.141837200, -0.439674400", \ - "0.0148944000, 0.0134218000, 0.0091893000, -0.003080900, -0.038358200, -0.141579700, -0.439333400", \ - "0.0169452000, 0.0153506000, 0.0109920000, -0.001323200, -0.037037000, -0.140180100, -0.437916000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014371910, 0.0041310370, 0.0118741800, 0.0341309400, 0.0981053700, 0.2819923000"); - values("0.0108906000, 0.0125750000, 0.0172167000, 0.0298965000, 0.0655883000, 0.1682550000, 0.4631459000", \ - "0.0107314000, 0.0123810000, 0.0170042000, 0.0297221000, 0.0654124000, 0.1681365000, 0.4630987000", \ - "0.0104116000, 0.0120801000, 0.0166892000, 0.0293955000, 0.0652064000, 0.1677237000, 0.4624808000", \ - "0.0101228000, 0.0117652000, 0.0162778000, 0.0289309000, 0.0648771000, 0.1674748000, 0.4606905000", \ - "0.0101814000, 0.0117355000, 0.0161918000, 0.0286899000, 0.0645870000, 0.1672115000, 0.4620762000", \ - "0.0107187000, 0.0122525000, 0.0166821000, 0.0293118000, 0.0646639000, 0.1670730000, 0.4619782000", \ - "0.0121638000, 0.0136357000, 0.0179275000, 0.0305832000, 0.0661600000, 0.1686653000, 0.4611023000"); - } - } - max_capacitance : 0.2819920000; - max_transition : 1.5053100000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014371900, 0.0041310400, 0.0118742000, 0.0341309000, 0.0981054000, 0.2819920000"); - values("0.0716015000, 0.0763899000, 0.0875026000, 0.1121150000, 0.1733989000, 0.3446792000, 0.8352690000", \ - "0.0770339000, 0.0818664000, 0.0928715000, 0.1176101000, 0.1788931000, 0.3502003000, 0.8414902000", \ - "0.0900543000, 0.0947134000, 0.1060304000, 0.1308139000, 0.1921727000, 0.3633843000, 0.8553820000", \ - "0.1214394000, 0.1262080000, 0.1371910000, 0.1616705000, 0.2231092000, 0.3949447000, 0.8859570000", \ - "0.1799247000, 0.1854615000, 0.1977499000, 0.2241256000, 0.2865788000, 0.4566277000, 0.9480640000", \ - "0.2682520000, 0.2755393000, 0.2910240000, 0.3212137000, 0.3863144000, 0.5576798000, 1.0507897000", \ - "0.3997725000, 0.4094347000, 0.4301978000, 0.4689681000, 0.5404556000, 0.7102394000, 1.2015631000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014371900, 0.0041310400, 0.0118742000, 0.0341309000, 0.0981054000, 0.2819920000"); - values("0.0664325000, 0.0716545000, 0.0839958000, 0.1137973000, 0.1937473000, 0.4229374000, 1.0810592000", \ - "0.0708009000, 0.0760067000, 0.0884353000, 0.1182771000, 0.1983222000, 0.4270950000, 1.0833632000", \ - "0.0818250000, 0.0870103000, 0.0993395000, 0.1290311000, 0.2093633000, 0.4385086000, 1.0980891000", \ - "0.1067796000, 0.1120560000, 0.1244518000, 0.1542440000, 0.2346855000, 0.4652857000, 1.1329345000", \ - "0.1451136000, 0.1514265000, 0.1651397000, 0.1959693000, 0.2766981000, 0.5067403000, 1.1670902000", \ - "0.1928313000, 0.2009778000, 0.2185236000, 0.2524978000, 0.3335347000, 0.5625999000, 1.2197580000", \ - "0.2406162000, 0.2517711000, 0.2749023000, 0.3177367000, 0.4014026000, 0.6303757000, 1.2853871000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014371900, 0.0041310400, 0.0118742000, 0.0341309000, 0.0981054000, 0.2819920000"); - values("0.0154727000, 0.0190965000, 0.0288345000, 0.0548727000, 0.1315777000, 0.3611575000, 1.0276668000", \ - "0.0155387000, 0.0192055000, 0.0288962000, 0.0547451000, 0.1317135000, 0.3604947000, 1.0229553000", \ - "0.0154951000, 0.0191583000, 0.0287407000, 0.0548265000, 0.1317595000, 0.3614254000, 1.0292400000", \ - "0.0157024000, 0.0194707000, 0.0290058000, 0.0549435000, 0.1314923000, 0.3601779000, 1.0168784000", \ - "0.0206613000, 0.0244101000, 0.0335030000, 0.0578767000, 0.1325533000, 0.3623940000, 1.0186327000", \ - "0.0303782000, 0.0346623000, 0.0437421000, 0.0669924000, 0.1375045000, 0.3603161000, 1.0205781000", \ - "0.0451225000, 0.0508914000, 0.0624974000, 0.0858820000, 0.1491341000, 0.3645286000, 1.0152580000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014371900, 0.0041310400, 0.0118742000, 0.0341309000, 0.0981054000, 0.2819920000"); - values("0.0175101000, 0.0222663000, 0.0355695000, 0.0747582000, 0.1907974000, 0.5299221000, 1.5042528000", \ - "0.0174792000, 0.0222443000, 0.0355332000, 0.0747596000, 0.1906620000, 0.5296232000, 1.5037815000", \ - "0.0174987000, 0.0222571000, 0.0356249000, 0.0747588000, 0.1912370000, 0.5284123000, 1.4986067000", \ - "0.0186565000, 0.0232087000, 0.0362998000, 0.0748493000, 0.1912039000, 0.5311085000, 1.5023579000", \ - "0.0241601000, 0.0286673000, 0.0405582000, 0.0774415000, 0.1915891000, 0.5304538000, 1.5053102000", \ - "0.0340562000, 0.0388462000, 0.0507461000, 0.0839073000, 0.1934370000, 0.5291393000, 1.5000503000", \ - "0.0487707000, 0.0553912000, 0.0687994000, 0.1009371000, 0.1994565000, 0.5309626000, 1.4990383000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_4") { - leakage_power () { - value : 0.0043253000; - when : "A"; - } - leakage_power () { - value : 0.0048763000; - when : "!A"; - } - always_on : "true"; - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__clkbufkapwr"; - cell_leakage_power : 0.0046007900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0021140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019930000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0022360000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0227218000, 0.0211209000, 0.0163197000, 0.0002744000, -0.055498400, -0.237090100, -0.816809300", \ - "0.0226501000, 0.0210223000, 0.0161997000, 0.0002190000, -0.055618000, -0.237205300, -0.816911000", \ - "0.0224144000, 0.0208132000, 0.0160349000, -5.8202923e-07, -0.055753800, -0.237344000, -0.817255200", \ - "0.0221670000, 0.0206529000, 0.0157418000, -0.000427500, -0.056138600, -0.237612000, -0.817337000", \ - "0.0219884000, 0.0203310000, 0.0152809000, -0.001037300, -0.056464400, -0.237760700, -0.817545600", \ - "0.0234020000, 0.0216240000, 0.0160188000, -0.001612600, -0.057014000, -0.237766600, -0.817390800", \ - "0.0266701000, 0.0247235000, 0.0187445000, 0.0002609000, -0.056200000, -0.237219800, -0.816499200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0209838000, 0.0228714000, 0.0288493000, 0.0474913000, 0.1046484000, 0.2851754000, 0.8602389000", \ - "0.0208133000, 0.0227085000, 0.0287421000, 0.0473559000, 0.1044901000, 0.2849028000, 0.8597446000", \ - "0.0206205000, 0.0225130000, 0.0284962000, 0.0471255000, 0.1043088000, 0.2847886000, 0.8595466000", \ - "0.0204896000, 0.0223460000, 0.0282911000, 0.0467910000, 0.1039400000, 0.2845523000, 0.8543201000", \ - "0.0202914000, 0.0221731000, 0.0280857000, 0.0462192000, 0.1030655000, 0.2830347000, 0.8543872000", \ - "0.0215338000, 0.0232776000, 0.0288500000, 0.0466759000, 0.1032640000, 0.2829184000, 0.8546065000", \ - "0.0231181000, 0.0247665000, 0.0302712000, 0.0479219000, 0.1043759000, 0.2848145000, 0.8562945000"); - } - } - max_capacitance : 0.5218600000; - max_transition : 1.5052410000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.1029407000, 0.1068293000, 0.1169257000, 0.1399582000, 0.1946097000, 0.3480062000, 0.8314640000", \ - "0.1083590000, 0.1122250000, 0.1222222000, 0.1455032000, 0.2000269000, 0.3532680000, 0.8368945000", \ - "0.1217727000, 0.1256701000, 0.1356996000, 0.1588750000, 0.2132953000, 0.3668353000, 0.8515296000", \ - "0.1530289000, 0.1569707000, 0.1670128000, 0.1901291000, 0.2447907000, 0.3982817000, 0.8831493000", \ - "0.2240703000, 0.2281864000, 0.2385982000, 0.2620027000, 0.3166120000, 0.4707482000, 0.9571055000", \ - "0.3404380000, 0.3458024000, 0.3591798000, 0.3877559000, 0.4469242000, 0.6010370000, 1.0858067000", \ - "0.5174792000, 0.5245335000, 0.5423504000, 0.5796040000, 0.6502185000, 0.8093084000, 1.2918642000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0921705000, 0.0964791000, 0.1076417000, 0.1350409000, 0.2078056000, 0.4304283000, 1.1414697000", \ - "0.0967452000, 0.1010759000, 0.1123087000, 0.1397388000, 0.2123764000, 0.4355046000, 1.1443033000", \ - "0.1077503000, 0.1120475000, 0.1232342000, 0.1505975000, 0.2233643000, 0.4468787000, 1.1556638000", \ - "0.1341268000, 0.1384031000, 0.1495488000, 0.1768264000, 0.2495753000, 0.4723100000, 1.1779877000", \ - "0.1849779000, 0.1897966000, 0.2020786000, 0.2303702000, 0.3036555000, 0.5258730000, 1.2323782000", \ - "0.2522736000, 0.2587439000, 0.2742280000, 0.3072672000, 0.3830168000, 0.6051735000, 1.3119125000", \ - "0.3304782000, 0.3391125000, 0.3597742000, 0.4028640000, 0.4856547000, 0.7099246000, 1.4138083000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0208185000, 0.0235855000, 0.0306000000, 0.0504471000, 0.1099397000, 0.3087383000, 0.9641764000", \ - "0.0208385000, 0.0234530000, 0.0308813000, 0.0503840000, 0.1099363000, 0.3092835000, 0.9633780000", \ - "0.0208548000, 0.0236002000, 0.0307291000, 0.0501635000, 0.1097371000, 0.3091165000, 0.9556228000", \ - "0.0210073000, 0.0236984000, 0.0306613000, 0.0503490000, 0.1098613000, 0.3085732000, 0.9559968000", \ - "0.0237869000, 0.0263275000, 0.0331452000, 0.0519016000, 0.1105009000, 0.3096477000, 0.9590055000", \ - "0.0354954000, 0.0381983000, 0.0457658000, 0.0642597000, 0.1183977000, 0.3109031000, 0.9563712000", \ - "0.0535571000, 0.0576547000, 0.0673204000, 0.0883647000, 0.1388192000, 0.3182807000, 0.9574493000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0223859000, 0.0256516000, 0.0354692000, 0.0645708000, 0.1613494000, 0.4799571000, 1.5052407000", \ - "0.0224636000, 0.0257845000, 0.0354012000, 0.0646665000, 0.1611811000, 0.4811350000, 1.5022226000", \ - "0.0226018000, 0.0257964000, 0.0355117000, 0.0646406000, 0.1612172000, 0.4814492000, 1.5041358000", \ - "0.0224732000, 0.0257078000, 0.0355565000, 0.0646605000, 0.1613200000, 0.4798568000, 1.4995193000", \ - "0.0281675000, 0.0311113000, 0.0401525000, 0.0676458000, 0.1619486000, 0.4801196000, 1.4966732000", \ - "0.0398743000, 0.0434136000, 0.0528185000, 0.0783672000, 0.1665721000, 0.4797778000, 1.5012368000", \ - "0.0573634000, 0.0630655000, 0.0741172000, 0.0997281000, 0.1788339000, 0.4829168000, 1.4976320000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkbufkapwr_8") { - leakage_power () { - value : 0.0075141000; - when : "A"; - } - leakage_power () { - value : 0.0068657000; - when : "!A"; - } - always_on : "true"; - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__clkbufkapwr"; - cell_leakage_power : 0.0071899220; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0039180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0036800000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0041560000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017597620, 0.0061935220, 0.0217982500, 0.0767194300, 0.2700158000, 0.9503271000"); - values("0.0444445000, 0.0426729000, 0.0363845000, 0.0145242000, -0.070483700, -0.382095300, -1.483571900", \ - "0.0442839000, 0.0424075000, 0.0363170000, 0.0144030000, -0.070690200, -0.382263800, -1.483772700", \ - "0.0439548000, 0.0422465000, 0.0359425000, 0.0139431000, -0.071058400, -0.382558700, -1.484096900", \ - "0.0435454000, 0.0417553000, 0.0354318000, 0.0132864000, -0.071893000, -0.383056000, -1.484466200", \ - "0.0442333000, 0.0424312000, 0.0356956000, 0.0128483000, -0.072737200, -0.383692300, -1.484797100", \ - "0.0466014000, 0.0448035000, 0.0375269000, 0.0124551000, -0.073231400, -0.383806500, -1.484657300", \ - "0.0505011000, 0.0482541000, 0.0407632000, 0.0167136000, -0.071450200, -0.382645700, -1.482847200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017597620, 0.0061935220, 0.0217982500, 0.0767194300, 0.2700158000, 0.9503271000"); - values("0.0393387000, 0.0415884000, 0.0492281000, 0.0760327000, 0.1660545000, 0.4767200000, 1.5606844000", \ - "0.0390829000, 0.0413273000, 0.0490611000, 0.0757225000, 0.1659548000, 0.4767027000, 1.5685044000", \ - "0.0387474000, 0.0409712000, 0.0487033000, 0.0754647000, 0.1654400000, 0.4761884000, 1.5602840000", \ - "0.0383755000, 0.0405633000, 0.0481742000, 0.0747874000, 0.1646048000, 0.4737417000, 1.5594985000", \ - "0.0381925000, 0.0403720000, 0.0479524000, 0.0739865000, 0.1626980000, 0.4749914000, 1.5689261000", \ - "0.0405609000, 0.0425870000, 0.0497722000, 0.0754991000, 0.1624261000, 0.4728247000, 1.5669254000", \ - "0.0433357000, 0.0452635000, 0.0522252000, 0.0772538000, 0.1656127000, 0.4751880000, 1.5623793000"); - } - } - max_capacitance : 0.9503270000; - max_transition : 1.5109380000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017597600, 0.0061935200, 0.0217982000, 0.0767194000, 0.2700160000, 0.9503270000"); - values("0.1033417000, 0.1058321000, 0.1132616000, 0.1324803000, 0.1802305000, 0.3194127000, 0.7992142000", \ - "0.1089445000, 0.1114343000, 0.1188957000, 0.1382283000, 0.1857591000, 0.3251060000, 0.8043545000", \ - "0.1220712000, 0.1245935000, 0.1324879000, 0.1517162000, 0.1992436000, 0.3386494000, 0.8177071000", \ - "0.1546570000, 0.1571277000, 0.1645650000, 0.1837420000, 0.2314453000, 0.3709406000, 0.8493982000", \ - "0.2266703000, 0.2292676000, 0.2369169000, 0.2562290000, 0.3041476000, 0.4438804000, 0.9228473000", \ - "0.3481482000, 0.3515179000, 0.3613508000, 0.3851386000, 0.4374874000, 0.5795195000, 1.0608566000", \ - "0.5367142000, 0.5411135000, 0.5542778000, 0.5859004000, 0.6504215000, 0.7977785000, 1.2761818000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017597600, 0.0061935200, 0.0217982000, 0.0767194000, 0.2700160000, 0.9503270000"); - values("0.0873268000, 0.0900734000, 0.0983150000, 0.1210155000, 0.1852843000, 0.3981862000, 1.1413898000", \ - "0.0917932000, 0.0945332000, 0.1027819000, 0.1254847000, 0.1897472000, 0.4024029000, 1.1507136000", \ - "0.1028520000, 0.1055883000, 0.1138978000, 0.1365168000, 0.2007753000, 0.4141271000, 1.1568686000", \ - "0.1287976000, 0.1315208000, 0.1397794000, 0.1622637000, 0.2263710000, 0.4389906000, 1.1830330000", \ - "0.1766482000, 0.1797558000, 0.1889084000, 0.2126374000, 0.2772364000, 0.4898476000, 1.2385152000", \ - "0.2383033000, 0.2423734000, 0.2540644000, 0.2822032000, 0.3491996000, 0.5621771000, 1.3064084000", \ - "0.3036578000, 0.3090339000, 0.3246291000, 0.3612352000, 0.4375046000, 0.6495622000, 1.3916343000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017597600, 0.0061935200, 0.0217982000, 0.0767194000, 0.2700160000, 0.9503270000"); - values("0.0209768000, 0.0226156000, 0.0279088000, 0.0431894000, 0.0920562000, 0.2704433000, 0.9238166000", \ - "0.0212033000, 0.0226038000, 0.0279333000, 0.0430956000, 0.0920605000, 0.2702371000, 0.9252100000", \ - "0.0211863000, 0.0226181000, 0.0277883000, 0.0431059000, 0.0921277000, 0.2710011000, 0.9255365000", \ - "0.0209579000, 0.0225551000, 0.0279252000, 0.0431758000, 0.0918912000, 0.2708710000, 0.9183651000", \ - "0.0237913000, 0.0253370000, 0.0302916000, 0.0448106000, 0.0926574000, 0.2713314000, 0.9166100000", \ - "0.0352162000, 0.0371292000, 0.0428772000, 0.0569923000, 0.1018994000, 0.2729647000, 0.9198131000", \ - "0.0547408000, 0.0572751000, 0.0640105000, 0.0814890000, 0.1237897000, 0.2815433000, 0.9191168000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017597600, 0.0061935200, 0.0217982000, 0.0767194000, 0.2700160000, 0.9503270000"); - values("0.0218934000, 0.0239846000, 0.0310631000, 0.0540276000, 0.1363078000, 0.4388064000, 1.5043430000", \ - "0.0219932000, 0.0241362000, 0.0310186000, 0.0540038000, 0.1364439000, 0.4390943000, 1.5109375000", \ - "0.0219234000, 0.0240701000, 0.0310798000, 0.0540058000, 0.1362725000, 0.4379833000, 1.5040965000", \ - "0.0221951000, 0.0242742000, 0.0312277000, 0.0542128000, 0.1364970000, 0.4375885000, 1.4991152000", \ - "0.0277340000, 0.0296951000, 0.0361074000, 0.0576236000, 0.1375860000, 0.4378644000, 1.5089693000", \ - "0.0393767000, 0.0413607000, 0.0484591000, 0.0682411000, 0.1426410000, 0.4374353000, 1.5037278000", \ - "0.0570687000, 0.0599508000, 0.0690395000, 0.0899178000, 0.1569612000, 0.4408681000, 1.4987550000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkinvkapwr_1") { - leakage_power () { - value : 0.0028987000; - when : "A"; - } - leakage_power () { - value : 0.0002364000; - when : "!A"; - } - always_on : "true"; - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__clkinvkapwr"; - cell_leakage_power : 0.0015675510; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0030170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0028420000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0031910000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301680, 0.0097814920, 0.0263562400, 0.0710169200, 0.1913552000"); - values("-0.004006600, -0.005138500, -0.008556300, -0.018304600, -0.045062400, -0.117372800, -0.312351300", \ - "-0.004436300, -0.005581900, -0.008893700, -0.018503500, -0.045176000, -0.117428500, -0.312314200", \ - "-0.004782400, -0.005979700, -0.009348200, -0.018846300, -0.045336100, -0.117485100, -0.312340700", \ - "-0.004882200, -0.006181000, -0.009684600, -0.019220000, -0.045632600, -0.117640000, -0.312419000", \ - "-0.004557800, -0.005933000, -0.009714700, -0.019582100, -0.045997300, -0.117887400, -0.312554000", \ - "-0.003641100, -0.005144200, -0.009071100, -0.019079400, -0.046064200, -0.118175100, -0.312728100", \ - "-0.000876000, -0.003083200, -0.007258100, -0.017843800, -0.045170600, -0.117796100, -0.312760200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301680, 0.0097814920, 0.0263562400, 0.0710169200, 0.1913552000"); - values("0.0104118000, 0.0119367000, 0.0157916000, 0.0258087000, 0.0524635000, 0.1237749000, 0.3183787000", \ - "0.0101763000, 0.0117164000, 0.0155944000, 0.0256867000, 0.0525163000, 0.1247438000, 0.3182940000", \ - "0.0100491000, 0.0115303000, 0.0153535000, 0.0254586000, 0.0522182000, 0.1239225000, 0.3154604000", \ - "0.0100502000, 0.0114830000, 0.0152005000, 0.0252613000, 0.0518025000, 0.1238772000, 0.3169946000", \ - "0.0102825000, 0.0116066000, 0.0152497000, 0.0252668000, 0.0520071000, 0.1233907000, 0.3165488000", \ - "0.0107101000, 0.0119201000, 0.0153640000, 0.0249953000, 0.0518661000, 0.1236526000, 0.3175409000", \ - "0.0132617000, 0.0145871000, 0.0180146000, 0.0268068000, 0.0529618000, 0.1235340000, 0.3176702000"); - } - } - max_capacitance : 0.1913550000; - max_transition : 1.4906250000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301700, 0.0097814900, 0.0263562000, 0.0710169000, 0.1913550000"); - values("0.0237124000, 0.0292626000, 0.0433504000, 0.0789214000, 0.1733448000, 0.4277163000, 1.1113881000", \ - "0.0274632000, 0.0330534000, 0.0472594000, 0.0834094000, 0.1785193000, 0.4333084000, 1.1171853000", \ - "0.0371965000, 0.0435942000, 0.0574400000, 0.0941923000, 0.1891194000, 0.4465403000, 1.1305535000", \ - "0.0515708000, 0.0613952000, 0.0810863000, 0.1200983000, 0.2152257000, 0.4697361000, 1.1498205000", \ - "0.0702921000, 0.0854167000, 0.1165861000, 0.1752731000, 0.2780086000, 0.5330519000, 1.2141342000", \ - "0.0929725000, 0.1156355000, 0.1636557000, 0.2535047000, 0.4080796000, 0.6778176000, 1.3626974000", \ - "0.1174110000, 0.1515030000, 0.2227677000, 0.3592048000, 0.5976672000, 0.9911025000, 1.6982613000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301700, 0.0097814900, 0.0263562000, 0.0710169000, 0.1913550000"); - values("0.0169834000, 0.0205999000, 0.0297679000, 0.0534838000, 0.1157393000, 0.2838584000, 0.7379880000", \ - "0.0225298000, 0.0260832000, 0.0351523000, 0.0587587000, 0.1218576000, 0.2917306000, 0.7424600000", \ - "0.0328563000, 0.0380462000, 0.0484487000, 0.0716990000, 0.1351039000, 0.3024985000, 0.7630830000", \ - "0.0475501000, 0.0560356000, 0.0732203000, 0.1032352000, 0.1655691000, 0.3345172000, 0.7890826000", \ - "0.0670335000, 0.0813651000, 0.1098933000, 0.1591729000, 0.2381949000, 0.4058876000, 0.8600468000", \ - "0.0929297000, 0.1149713000, 0.1603808000, 0.2422866000, 0.3712071000, 0.5715927000, 1.0207341000", \ - "0.1248887000, 0.1594783000, 0.2292515000, 0.3574086000, 0.5722873000, 0.8977825000, 1.4069715000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301700, 0.0097814900, 0.0263562000, 0.0710169000, 0.1913550000"); - values("0.0136695000, 0.0203052000, 0.0374007000, 0.0841127000, 0.2096932000, 0.5460887000, 1.4593917000", \ - "0.0136637000, 0.0201681000, 0.0373738000, 0.0841145000, 0.2090024000, 0.5463680000, 1.4589672000", \ - "0.0184921000, 0.0229985000, 0.0382391000, 0.0840756000, 0.2094994000, 0.5464017000, 1.4549416000", \ - "0.0305477000, 0.0369708000, 0.0515444000, 0.0880745000, 0.2101453000, 0.5491018000, 1.4621381000", \ - "0.0507394000, 0.0610759000, 0.0823719000, 0.1227583000, 0.2196550000, 0.5501704000, 1.4630858000", \ - "0.0850476000, 0.1012117000, 0.1355656000, 0.1932318000, 0.2987724000, 0.5669027000, 1.4598556000", \ - "0.1463707000, 0.1709414000, 0.2228897000, 0.3133294000, 0.4677402000, 0.7306161000, 1.4906253000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013472500, 0.0036301700, 0.0097814900, 0.0263562000, 0.0710169000, 0.1913550000"); - values("0.0103790000, 0.0150336000, 0.0276414000, 0.0615167000, 0.1523303000, 0.3973395000, 1.0569939000", \ - "0.0110960000, 0.0151688000, 0.0275674000, 0.0615592000, 0.1528645000, 0.3992133000, 1.0560823000", \ - "0.0180804000, 0.0212493000, 0.0302139000, 0.0612692000, 0.1525483000, 0.3970627000, 1.0549960000", \ - "0.0303208000, 0.0354580000, 0.0462025000, 0.0697502000, 0.1523940000, 0.3976289000, 1.0562460000", \ - "0.0524308000, 0.0605262000, 0.0771620000, 0.1085013000, 0.1713465000, 0.3962098000, 1.0562808000", \ - "0.0886534000, 0.1037551000, 0.1309662000, 0.1781846000, 0.2571610000, 0.4347607000, 1.0542378000", \ - "0.1541611000, 0.1757458000, 0.2208851000, 0.3002485000, 0.4260781000, 0.6233877000, 1.1170552000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkinvkapwr_16") { - leakage_power () { - value : 0.0128005000; - when : "A"; - } - leakage_power () { - value : 0.0100213000; - when : "!A"; - } - always_on : "true"; - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__clkinvkapwr"; - cell_leakage_power : 0.0114109000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0382660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0358100000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0407230000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0020465370, 0.0083766310, 0.0342861800, 0.1403359000, 0.5744052000, 2.3510840000"); - values("-0.043998000, -0.045817800, -0.053891200, -0.091229500, -0.259525600, -0.961453800, -3.840052000", \ - "-0.049113800, -0.051026600, -0.059171600, -0.095487500, -0.261438400, -0.962294700, -3.839720600", \ - "-0.052810200, -0.055079500, -0.063901000, -0.101169200, -0.264834600, -0.963454900, -3.840163900", \ - "-0.054115800, -0.056480700, -0.066098700, -0.105390200, -0.269733300, -0.965598200, -3.840642600", \ - "-0.052860500, -0.055408900, -0.065812900, -0.105908900, -0.274472000, -0.969305400, -3.842090700", \ - "-0.037706900, -0.041309300, -0.053825500, -0.099568000, -0.270403900, -0.972896100, -3.843840700", \ - "-0.009677500, -0.011536800, -0.027743700, -0.078908500, -0.259159900, -0.970352900, -3.845072800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0020465370, 0.0083766310, 0.0342861800, 0.1403359000, 0.5744052000, 2.3510840000"); - values("0.1194603000, 0.1227308000, 0.1354584000, 0.1819108000, 0.3552043000, 1.0525768000, 3.9051084000", \ - "0.1175437000, 0.1204943000, 0.1324985000, 0.1788567000, 0.3539240000, 1.0521254000, 3.9027037000", \ - "0.1163957000, 0.1192305000, 0.1305305000, 0.1752731000, 0.3507338000, 1.0508156000, 3.9030732000", \ - "0.1175096000, 0.1201514000, 0.1303529000, 0.1734377000, 0.3464611000, 1.0446545000, 3.8879932000", \ - "0.1199298000, 0.1223381000, 0.1322911000, 0.1735075000, 0.3444870000, 1.0451721000, 3.9004059000", \ - "0.1290276000, 0.1294679000, 0.1362042000, 0.1750457000, 0.3487453000, 1.0412102000, 3.8893844000", \ - "0.1586429000, 0.1604518000, 0.1678598000, 0.2022775000, 0.3606813000, 1.0507131000, 3.8818808000"); - } - } - max_capacitance : 2.3510840000; - max_transition : 1.5012540000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020465400, 0.0083766300, 0.0342862000, 0.1403360000, 0.5744050000, 2.3510800000"); - values("0.0245963000, 0.0255219000, 0.0291455000, 0.0421643000, 0.0908962000, 0.2846919000, 1.0774144000", \ - "0.0276317000, 0.0285485000, 0.0321258000, 0.0453541000, 0.0943668000, 0.2887227000, 1.0810846000", \ - "0.0353267000, 0.0364864000, 0.0408586000, 0.0547061000, 0.1045392000, 0.2990875000, 1.0993972000", \ - "0.0444362000, 0.0462418000, 0.0529583000, 0.0741344000, 0.1284442000, 0.3236657000, 1.1173715000", \ - "0.0514737000, 0.0543357000, 0.0648444000, 0.0977566000, 0.1795523000, 0.3828018000, 1.1780940000", \ - "0.0488783000, 0.0533754000, 0.0692762000, 0.1197208000, 0.2465531000, 0.5189353000, 1.3127198000", \ - "0.0178258000, 0.0242860000, 0.0478525000, 0.1236058000, 0.3179620000, 0.7384903000, 1.6274959000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020465400, 0.0083766300, 0.0342862000, 0.1403360000, 0.5744050000, 2.3510800000"); - values("0.0196403000, 0.0204266000, 0.0234776000, 0.0340721000, 0.0726361000, 0.2273734000, 0.8602651000", \ - "0.0248958000, 0.0256518000, 0.0285777000, 0.0391596000, 0.0778883000, 0.2328296000, 0.8633555000", \ - "0.0360856000, 0.0371736000, 0.0411321000, 0.0524848000, 0.0913710000, 0.2461153000, 0.8746665000", \ - "0.0531933000, 0.0548753000, 0.0612224000, 0.0796709000, 0.1235318000, 0.2783006000, 0.9159892000", \ - "0.0799136000, 0.0826900000, 0.0928280000, 0.1229054000, 0.1927258000, 0.3526754000, 0.9809341000", \ - "0.1243720000, 0.1285382000, 0.1443978000, 0.1920039000, 0.3056031000, 0.5288300000, 1.1565899000", \ - "0.2038394000, 0.2100303000, 0.2328986000, 0.3059399000, 0.4871616000, 0.8486639000, 1.5620473000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020465400, 0.0083766300, 0.0342862000, 0.1403360000, 0.5744050000, 2.3510800000"); - values("0.0109797000, 0.0118832000, 0.0156919000, 0.0315328000, 0.0970806000, 0.3637064000, 1.4587480000", \ - "0.0111050000, 0.0120304000, 0.0158075000, 0.0316188000, 0.0969622000, 0.3649278000, 1.4577964000", \ - "0.0158537000, 0.0168027000, 0.0196670000, 0.0328496000, 0.0973163000, 0.3639389000, 1.4593610000", \ - "0.0259166000, 0.0271533000, 0.0316947000, 0.0476161000, 0.1002623000, 0.3639881000, 1.4606569000", \ - "0.0437713000, 0.0457271000, 0.0530168000, 0.0752035000, 0.1323873000, 0.3659891000, 1.4624062000", \ - "0.0741648000, 0.0776710000, 0.0888103000, 0.1234480000, 0.2086041000, 0.4177576000, 1.4576085000", \ - "0.1300033000, 0.1334541000, 0.1501590000, 0.2043670000, 0.3349726000, 0.6095252000, 1.5012536000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0020465400, 0.0083766300, 0.0342862000, 0.1403360000, 0.5744050000, 2.3510800000"); - values("0.0097289000, 0.0104871000, 0.0135962000, 0.0268221000, 0.0818530000, 0.3067094000, 1.2266487000", \ - "0.0101117000, 0.0108454000, 0.0138932000, 0.0269422000, 0.0818750000, 0.3065007000, 1.2291955000", \ - "0.0162356000, 0.0168277000, 0.0189044000, 0.0288537000, 0.0817615000, 0.3073118000, 1.2303062000", \ - "0.0267470000, 0.0277551000, 0.0315169000, 0.0434040000, 0.0854704000, 0.3067880000, 1.2280541000", \ - "0.0461767000, 0.0478101000, 0.0538674000, 0.0718713000, 0.1161758000, 0.3077608000, 1.2295093000", \ - "0.0792713000, 0.0817626000, 0.0916283000, 0.1214162000, 0.1886892000, 0.3534292000, 1.2255744000", \ - "0.1389616000, 0.1428683000, 0.1573289000, 0.2049131000, 0.3164933000, 0.5374240000, 1.2611502000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkinvkapwr_2") { - leakage_power () { - value : 0.0071803000; - when : "A"; - } - leakage_power () { - value : 0.0006400000; - when : "!A"; - } - always_on : "true"; - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__clkinvkapwr"; - cell_leakage_power : 0.0039101540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0051870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0048490000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0055260000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015205570, 0.0046241860, 0.0140626800, 0.0427662000, 0.1300569000, 0.3955177000"); - values("-0.005292800, -0.006624300, -0.011107300, -0.025922200, -0.072242200, -0.213539600, -0.643617400", \ - "-0.006031000, -0.007371500, -0.011797200, -0.026343300, -0.072374200, -0.213619100, -0.643569700", \ - "-0.006648100, -0.008096700, -0.012586100, -0.026980900, -0.072676400, -0.213739500, -0.643649800", \ - "-0.006886500, -0.008431700, -0.013105100, -0.027732400, -0.073222800, -0.213973100, -0.643686700", \ - "-0.006291300, -0.007952000, -0.012925600, -0.028258000, -0.073853200, -0.214365900, -0.643899300", \ - "-0.004466600, -0.006443600, -0.011859400, -0.027224200, -0.073891300, -0.214824200, -0.644176700", \ - "-9.4888262e-05, -0.002971500, -0.008758800, -0.025166100, -0.072504800, -0.213975100, -0.644020600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015205570, 0.0046241860, 0.0140626800, 0.0427662000, 0.1300569000, 0.3955177000"); - values("0.0165900000, 0.0185196000, 0.0239074000, 0.0393757000, 0.0856538000, 0.2243117000, 0.6486487000", \ - "0.0162131000, 0.0180635000, 0.0234879000, 0.0390978000, 0.0854978000, 0.2259640000, 0.6521066000", \ - "0.0160106000, 0.0177864000, 0.0230182000, 0.0387004000, 0.0850588000, 0.2256083000, 0.6508945000", \ - "0.0160222000, 0.0178592000, 0.0229912000, 0.0382005000, 0.0845637000, 0.2249372000, 0.6485456000", \ - "0.0164380000, 0.0180348000, 0.0229236000, 0.0381899000, 0.0843850000, 0.2246677000, 0.6489693000", \ - "0.0171089000, 0.0185730000, 0.0232250000, 0.0378605000, 0.0847293000, 0.2233410000, 0.6470476000", \ - "0.0214806000, 0.0227664000, 0.0277707000, 0.0412183000, 0.0858706000, 0.2244208000, 0.6456816000"); - } - } - max_capacitance : 0.3955180000; - max_transition : 1.4985760000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0198380000, 0.0232077000, 0.0326596000, 0.0596757000, 0.1388195000, 0.3780019000, 1.1064915000", \ - "0.0237280000, 0.0270274000, 0.0365355000, 0.0637754000, 0.1431778000, 0.3827313000, 1.1106570000", \ - "0.0323502000, 0.0366826000, 0.0471105000, 0.0741045000, 0.1547120000, 0.3940910000, 1.1218380000", \ - "0.0435519000, 0.0503142000, 0.0665581000, 0.1004400000, 0.1808231000, 0.4204944000, 1.1493172000", \ - "0.0564549000, 0.0669825000, 0.0921374000, 0.1448714000, 0.2424037000, 0.4815574000, 1.2098951000", \ - "0.0674115000, 0.0833974000, 0.1221172000, 0.2036075000, 0.3538766000, 0.6249887000, 1.3520816000", \ - "0.0676527000, 0.0913606000, 0.1493216000, 0.2732014000, 0.5051696000, 0.9160503000, 1.6820830000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0169584000, 0.0197855000, 0.0277185000, 0.0504586000, 0.1180257000, 0.3214952000, 0.9509649000", \ - "0.0225739000, 0.0252705000, 0.0331366000, 0.0559070000, 0.1240782000, 0.3294249000, 0.9535863000", \ - "0.0332447000, 0.0372350000, 0.0465666000, 0.0690138000, 0.1368740000, 0.3424190000, 0.9611287000", \ - "0.0484179000, 0.0550930000, 0.0703935000, 0.1007663000, 0.1682728000, 0.3729350000, 0.9993603000", \ - "0.0703157000, 0.0812531000, 0.1064719000, 0.1559558000, 0.2408563000, 0.4444043000, 1.0646681000", \ - "0.1029050000, 0.1194771000, 0.1593250000, 0.2396037000, 0.3807946000, 0.6142933000, 1.2287485000", \ - "0.1545884000, 0.1787635000, 0.2385414000, 0.3637645000, 0.5911123000, 0.9658444000, 1.6126586000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0105300000, 0.0144186000, 0.0256471000, 0.0614530000, 0.1658932000, 0.4877126000, 1.4653825000", \ - "0.0106703000, 0.0143467000, 0.0257204000, 0.0606026000, 0.1661000000, 0.4858942000, 1.4625869000", \ - "0.0162031000, 0.0191732000, 0.0278840000, 0.0609676000, 0.1661226000, 0.4867231000, 1.4597940000", \ - "0.0269296000, 0.0314293000, 0.0425058000, 0.0681734000, 0.1667581000, 0.4868315000, 1.4657027000", \ - "0.0453424000, 0.0525820000, 0.0695579000, 0.1042287000, 0.1834353000, 0.4866951000, 1.4639556000", \ - "0.0770422000, 0.0882702000, 0.1167448000, 0.1682220000, 0.2678499000, 0.5174228000, 1.4734247000", \ - "0.1349465000, 0.1513047000, 0.1926260000, 0.2753375000, 0.4254571000, 0.6963537000, 1.4985762000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015205600, 0.0046241900, 0.0140627000, 0.0427662000, 0.1300570000, 0.3955180000"); - values("0.0101933000, 0.0136712000, 0.0242121000, 0.0562108000, 0.1536378000, 0.4467417000, 1.3401876000", \ - "0.0108472000, 0.0137628000, 0.0241848000, 0.0563300000, 0.1531031000, 0.4500783000, 1.3508222000", \ - "0.0178755000, 0.0202151000, 0.0272481000, 0.0561188000, 0.1533130000, 0.4486774000, 1.3411178000", \ - "0.0294987000, 0.0334982000, 0.0430148000, 0.0652008000, 0.1529663000, 0.4472960000, 1.3404494000", \ - "0.0501051000, 0.0566910000, 0.0714709000, 0.1019428000, 0.1713453000, 0.4467684000, 1.3456941000", \ - "0.0851050000, 0.0957357000, 0.1203941000, 0.1679249000, 0.2556980000, 0.4740033000, 1.3433712000", \ - "0.1464551000, 0.1622056000, 0.2014182000, 0.2820162000, 0.4177800000, 0.6520569000, 1.3734933000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkinvkapwr_4") { - leakage_power () { - value : 0.0063418000; - when : "A"; - } - leakage_power () { - value : 0.0018947000; - when : "!A"; - } - always_on : "true"; - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__clkinvkapwr"; - cell_leakage_power : 0.0041182940; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0102490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0095760000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0109240000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017044510, 0.0058103080, 0.0198067700, 0.0675193700, 0.2301669000, 0.7846167000"); - values("-0.011183100, -0.012660400, -0.018299900, -0.039896600, -0.116723800, -0.379980900, -1.278204000", \ - "-0.012591500, -0.014167600, -0.019801800, -0.040823800, -0.117062900, -0.380134400, -1.278143000", \ - "-0.013749800, -0.015462200, -0.021275300, -0.042083000, -0.117706700, -0.380318700, -1.278312900", \ - "-0.014209100, -0.016029100, -0.022185900, -0.043673900, -0.118838400, -0.380764800, -1.278476300", \ - "-0.013045100, -0.015018800, -0.021628400, -0.044489000, -0.119912400, -0.381482000, -1.278688700", \ - "-0.009714500, -0.011761000, -0.019626100, -0.042598400, -0.120166700, -0.382547300, -1.279217800", \ - "-0.001624900, -0.003813300, -0.013689000, -0.038192900, -0.117353600, -0.381401300, -1.279236000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017044510, 0.0058103080, 0.0198067700, 0.0675193700, 0.2301669000, 0.7846167000"); - values("0.0326694000, 0.0350701000, 0.0425406000, 0.0659138000, 0.1423205000, 0.4043543000, 1.2950186000", \ - "0.0319526000, 0.0342203000, 0.0416030000, 0.0650477000, 0.1426648000, 0.4036675000, 1.2953251000", \ - "0.0315645000, 0.0336819000, 0.0408285000, 0.0643276000, 0.1422117000, 0.4014288000, 1.2921909000", \ - "0.0316298000, 0.0339499000, 0.0406596000, 0.0634828000, 0.1407430000, 0.4018130000, 1.2928566000", \ - "0.0330031000, 0.0351842000, 0.0415655000, 0.0642078000, 0.1403442000, 0.4016056000, 1.2906759000", \ - "0.0343593000, 0.0363541000, 0.0426315000, 0.0646596000, 0.1416929000, 0.4012496000, 1.2902225000", \ - "0.0413165000, 0.0427726000, 0.0485005000, 0.0691570000, 0.1436238000, 0.4064570000, 1.2887131000"); - } - } - max_capacitance : 0.7846170000; - max_transition : 1.5030680000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017044500, 0.0058103100, 0.0198068000, 0.0675194000, 0.2301670000, 0.7846170000"); - values("0.0188051000, 0.0208469000, 0.0273894000, 0.0477081000, 0.1137228000, 0.3362283000, 1.0982375000", \ - "0.0226481000, 0.0246546000, 0.0310971000, 0.0516144000, 0.1178742000, 0.3405175000, 1.1009939000", \ - "0.0303519000, 0.0331703000, 0.0412571000, 0.0620280000, 0.1286799000, 0.3522097000, 1.1109375000", \ - "0.0395051000, 0.0439411000, 0.0563863000, 0.0861118000, 0.1542749000, 0.3785292000, 1.1374323000", \ - "0.0482222000, 0.0551179000, 0.0745692000, 0.1204105000, 0.2132588000, 0.4381372000, 1.1960923000", \ - "0.0501404000, 0.0607461000, 0.0906161000, 0.1616620000, 0.3059291000, 0.5787735000, 1.3356221000", \ - "0.0305296000, 0.0460764000, 0.0902600000, 0.1992069000, 0.4234132000, 0.8417857000, 1.6597590000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017044500, 0.0058103100, 0.0198068000, 0.0675194000, 0.2301670000, 0.7846170000"); - values("0.0170766000, 0.0189975000, 0.0249465000, 0.0436712000, 0.1043577000, 0.3130713000, 1.0196877000", \ - "0.0227946000, 0.0245729000, 0.0304275000, 0.0489633000, 0.1107510000, 0.3179879000, 1.0291428000", \ - "0.0338500000, 0.0366269000, 0.0440727000, 0.0626647000, 0.1238806000, 0.3299655000, 1.0325211000", \ - "0.0502997000, 0.0546374000, 0.0669221000, 0.0938804000, 0.1562658000, 0.3623935000, 1.0675513000", \ - "0.0752296000, 0.0825200000, 0.1020722000, 0.1471211000, 0.2308494000, 0.4366244000, 1.1390431000", \ - "0.1148712000, 0.1259255000, 0.1571951000, 0.2283072000, 0.3647897000, 0.6091102000, 1.3108880000", \ - "0.1824524000, 0.1992357000, 0.2455475000, 0.3569380000, 0.5790946000, 0.9704909000, 1.7110561000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017044500, 0.0058103100, 0.0198068000, 0.0675194000, 0.2301670000, 0.7846170000"); - values("0.0092860000, 0.0115755000, 0.0190915000, 0.0449754000, 0.1336259000, 0.4324962000, 1.4562428000", \ - "0.0095676000, 0.0115506000, 0.0190392000, 0.0448336000, 0.1327545000, 0.4347207000, 1.4528928000", \ - "0.0151296000, 0.0171970000, 0.0226978000, 0.0454950000, 0.1338016000, 0.4321677000, 1.4534302000", \ - "0.0252893000, 0.0283466000, 0.0366265000, 0.0574582000, 0.1341269000, 0.4391150000, 1.4703992000", \ - "0.0428790000, 0.0476337000, 0.0606862000, 0.0909183000, 0.1582172000, 0.4377077000, 1.4697294000", \ - "0.0734596000, 0.0813534000, 0.1017076000, 0.1483969000, 0.2420880000, 0.4710340000, 1.4666476000", \ - "0.1303158000, 0.1403746000, 0.1718475000, 0.2446308000, 0.3899860000, 0.6643567000, 1.5030679000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017044500, 0.0058103100, 0.0198068000, 0.0675194000, 0.2301670000, 0.7846170000"); - values("0.0096732000, 0.0118904000, 0.0194291000, 0.0453326000, 0.1325172000, 0.4328923000, 1.4567056000", \ - "0.0101322000, 0.0120655000, 0.0194835000, 0.0452297000, 0.1333029000, 0.4322318000, 1.4570806000", \ - "0.0170402000, 0.0186787000, 0.0233784000, 0.0456020000, 0.1333430000, 0.4314936000, 1.4466766000", \ - "0.0282002000, 0.0308114000, 0.0382711000, 0.0572432000, 0.1332605000, 0.4333672000, 1.4544808000", \ - "0.0481773000, 0.0527266000, 0.0642888000, 0.0923020000, 0.1541309000, 0.4304841000, 1.4467153000", \ - "0.0819002000, 0.0889293000, 0.1082921000, 0.1519352000, 0.2363468000, 0.4581813000, 1.4500590000", \ - "0.1417728000, 0.1523887000, 0.1861903000, 0.2540771000, 0.3897232000, 0.6411242000, 1.4729566000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_clkinvkapwr_8") { - leakage_power () { - value : 0.0094544000; - when : "A"; - } - leakage_power () { - value : 0.0043300000; - when : "!A"; - } - always_on : "true"; - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__clkinvkapwr"; - cell_leakage_power : 0.0068922350; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0203390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0190330000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0216450000; - } - pin ("Y") { - direction : "output"; - function : "(!A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882870, 0.0266886700, 0.1004876000, 0.3783539000, 1.4245700000"); - values("-0.022081500, -0.023711000, -0.030545000, -0.060078800, -0.178526100, -0.628268900, -2.322397300", \ - "-0.024801000, -0.026595800, -0.033441600, -0.062085500, -0.179256800, -0.628564600, -2.323251200", \ - "-0.027059900, -0.028831100, -0.036298400, -0.064973700, -0.180766500, -0.629102800, -2.323407700", \ - "-0.027991300, -0.030018100, -0.037867100, -0.067632800, -0.183120500, -0.630069900, -2.323523500", \ - "-0.025714800, -0.027956000, -0.036416400, -0.068691200, -0.185298200, -0.631458500, -2.323682900", \ - "-0.020416100, -0.022925000, -0.032658000, -0.065251600, -0.185987300, -0.633412600, -2.325122700", \ - "-0.004877200, -0.007421800, -0.020389800, -0.055800600, -0.179490500, -0.632522000, -2.325557100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882870, 0.0266886700, 0.1004876000, 0.3783539000, 1.4245700000"); - values("0.0633334000, 0.0662089000, 0.0762066000, 0.1094801000, 0.2290858000, 0.6719642000, 2.3539577000", \ - "0.0620795000, 0.0647239000, 0.0743751000, 0.1081931000, 0.2284264000, 0.6721732000, 2.3426430000", \ - "0.0614100000, 0.0638451000, 0.0729869000, 0.1062608000, 0.2269629000, 0.6745931000, 2.3412151000", \ - "0.0615316000, 0.0638533000, 0.0723942000, 0.1046516000, 0.2242668000, 0.6724300000, 2.3519385000", \ - "0.0634681000, 0.0654705000, 0.0736780000, 0.1050393000, 0.2236238000, 0.6699369000, 2.3493622000", \ - "0.0652564000, 0.0672612000, 0.0749300000, 0.1048718000, 0.2253579000, 0.6679996000, 2.3452486000", \ - "0.0796299000, 0.0811616000, 0.0878826000, 0.1163692000, 0.2293606000, 0.6735835000, 2.3441046000"); - } - } - max_capacitance : 1.4245700000; - max_transition : 1.4975290000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882900, 0.0266887000, 0.1004880000, 0.3783540000, 1.4245700000"); - values("0.0194371000, 0.0207884000, 0.0254488000, 0.0411578000, 0.0961184000, 0.3013675000, 1.0768618000", \ - "0.0231533000, 0.0244444000, 0.0290811000, 0.0452818000, 0.1004676000, 0.3075666000, 1.0763989000", \ - "0.0306570000, 0.0324502000, 0.0384030000, 0.0552250000, 0.1115428000, 0.3167251000, 1.0877312000", \ - "0.0392520000, 0.0420869000, 0.0513641000, 0.0766408000, 0.1363640000, 0.3433898000, 1.1139356000", \ - "0.0465814000, 0.0509822000, 0.0653124000, 0.1043565000, 0.1914433000, 0.4014769000, 1.1767786000", \ - "0.0455983000, 0.0523282000, 0.0742575000, 0.1347046000, 0.2697183000, 0.5418798000, 1.3111925000", \ - "0.0189856000, 0.0286479000, 0.0616196000, 0.1524281000, 0.3620259000, 0.7817139000, 1.6332131000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882900, 0.0266887000, 0.1004880000, 0.3783540000, 1.4245700000"); - values("0.0171969000, 0.0184510000, 0.0227580000, 0.0372353000, 0.0879004000, 0.2750790000, 0.9825432000", \ - "0.0229673000, 0.0241188000, 0.0282702000, 0.0425161000, 0.0936514000, 0.2809795000, 0.9925919000", \ - "0.0341136000, 0.0358999000, 0.0414277000, 0.0561734000, 0.1070440000, 0.2963655000, 1.0005976000", \ - "0.0507562000, 0.0536299000, 0.0625263000, 0.0857169000, 0.1390317000, 0.3273898000, 1.0360698000", \ - "0.0765883000, 0.0811762000, 0.0958401000, 0.1336106000, 0.2121491000, 0.4028477000, 1.1087901000", \ - "0.1186034000, 0.1256690000, 0.1483116000, 0.2087546000, 0.3371490000, 0.5760867000, 1.2829199000", \ - "0.1926338000, 0.2024886000, 0.2361291000, 0.3292292000, 0.5355268000, 0.9220743000, 1.6831847000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882900, 0.0266887000, 0.1004880000, 0.3783540000, 1.4245700000"); - values("0.0093945000, 0.0107982000, 0.0159857000, 0.0358328000, 0.1109081000, 0.3941220000, 1.4602687000", \ - "0.0095650000, 0.0108494000, 0.0160140000, 0.0359480000, 0.1109203000, 0.3948858000, 1.4572307000", \ - "0.0150115000, 0.0163768000, 0.0206456000, 0.0370188000, 0.1111785000, 0.3952005000, 1.4576464000", \ - "0.0250023000, 0.0269179000, 0.0331691000, 0.0510293000, 0.1134118000, 0.3932518000, 1.4585272000", \ - "0.0426768000, 0.0457546000, 0.0554146000, 0.0813336000, 0.1428259000, 0.3945846000, 1.4633078000", \ - "0.0730827000, 0.0778227000, 0.0924199000, 0.1326328000, 0.2224115000, 0.4396250000, 1.4605402000", \ - "0.1284171000, 0.1360226000, 0.1585892000, 0.2197291000, 0.3568676000, 0.6325549000, 1.4975294000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0018825900, 0.0070882900, 0.0266887000, 0.1004880000, 0.3783540000, 1.4245700000"); - values("0.0094415000, 0.0107665000, 0.0159359000, 0.0354194000, 0.1089663000, 0.3843392000, 1.4298891000", \ - "0.0098716000, 0.0110438000, 0.0159836000, 0.0354793000, 0.1087899000, 0.3844154000, 1.4241727000", \ - "0.0167201000, 0.0178347000, 0.0208408000, 0.0363169000, 0.1088108000, 0.3850114000, 1.4226782000", \ - "0.0275710000, 0.0292442000, 0.0345698000, 0.0496871000, 0.1099616000, 0.3838287000, 1.4266837000", \ - "0.0477960000, 0.0503067000, 0.0586340000, 0.0811577000, 0.1359035000, 0.3837974000, 1.4257850000", \ - "0.0807835000, 0.0854963000, 0.0991053000, 0.1357758000, 0.2142764000, 0.4195403000, 1.4248770000", \ - "0.1415403000, 0.1488555000, 0.1683489000, 0.2289422000, 0.3547744000, 0.5967419000, 1.4461506000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_decapkapwr_12") { - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400940; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__lpflow_decapkapwr_3") { - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400370; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__lpflow_decapkapwr_4") { - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400440; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__lpflow_decapkapwr_6") { - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400560; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__lpflow_decapkapwr_8") { - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__decap"; - cell_leakage_power : 0.0032400690; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__lpflow_inputiso0n_1") { - leakage_power () { - value : 0.0031700000; - when : "!SLEEP_B&A"; - } - leakage_power () { - value : 0.0028440000; - when : "!SLEEP_B&!A"; - } - leakage_power () { - value : 0.0014741000; - when : "SLEEP_B&A"; - } - leakage_power () { - value : 0.0031719000; - when : "SLEEP_B&!A"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__inputiso0n"; - cell_leakage_power : 0.0026650060; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025379000, 0.0025400000, 0.0025448000, 0.0025448000, 0.0025447000, 0.0025445000, 0.0025440000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001956100, -0.001957000, -0.001959300, -0.001955200, -0.001945900, -0.001924400, -0.001874800"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014920000; - } - pin ("SLEEP_B") { - capacitance : 0.0014960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022875000, 0.0022876000, 0.0022879000, 0.0022886000, 0.0022901000, 0.0022938000, 0.0023021000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002284200, -0.002283900, -0.002283100, -0.002283200, -0.002283500, -0.002284000, -0.002285200"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015600000; - } - pin ("X") { - direction : "output"; - function : "(SLEEP_B&A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0085240000, 0.0074664000, 0.0046369000, -0.003676900, -0.026596400, -0.087127000, -0.245422400", \ - "0.0083931000, 0.0073403000, 0.0045021000, -0.003805000, -0.026716700, -0.087233700, -0.245554800", \ - "0.0082197000, 0.0071245000, 0.0042612000, -0.004033200, -0.026937400, -0.087455000, -0.245748300", \ - "0.0079991000, 0.0069151000, 0.0040167000, -0.004303500, -0.027186600, -0.087673800, -0.245952000", \ - "0.0080176000, 0.0068765000, 0.0039774000, -0.004402800, -0.027255800, -0.087711400, -0.245954800", \ - "0.0088907000, 0.0075031000, 0.0041860000, -0.004514700, -0.027130700, -0.087510900, -0.245699200", \ - "0.0097210000, 0.0083623000, 0.0048614000, -0.003959300, -0.026952200, -0.087195000, -0.245292000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0094704000, 0.0108522000, 0.0143551000, 0.0232112000, 0.0462251000, 0.1062811000, 0.2614212000", \ - "0.0093983000, 0.0107825000, 0.0142948000, 0.0232034000, 0.0462224000, 0.1062042000, 0.2627313000", \ - "0.0092865000, 0.0106624000, 0.0141663000, 0.0231015000, 0.0461635000, 0.1061495000, 0.2630470000", \ - "0.0091534000, 0.0105032000, 0.0139926000, 0.0228474000, 0.0459524000, 0.1059391000, 0.2624917000", \ - "0.0090617000, 0.0104091000, 0.0138378000, 0.0227020000, 0.0458110000, 0.1059986000, 0.2611088000", \ - "0.0093870000, 0.0107110000, 0.0141771000, 0.0227496000, 0.0458959000, 0.1060684000, 0.2626684000", \ - "0.0102133000, 0.0114561000, 0.0148248000, 0.0237647000, 0.0465589000, 0.1068110000, 0.2629192000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0101951000, 0.0090964000, 0.0061835000, -0.002195800, -0.025150600, -0.085714800, -0.243986000", \ - "0.0100591000, 0.0089721000, 0.0060136000, -0.002323200, -0.025284600, -0.085834800, -0.244153700", \ - "0.0099392000, 0.0088303000, 0.0058713000, -0.002460900, -0.025428100, -0.085962400, -0.244240000", \ - "0.0097425000, 0.0086176000, 0.0056732000, -0.002675700, -0.025604700, -0.086115800, -0.244393500", \ - "0.0096279000, 0.0084970000, 0.0055326000, -0.002829200, -0.025731000, -0.086200000, -0.244446800", \ - "0.0101414000, 0.0088554000, 0.0057637000, -0.002614100, -0.025418700, -0.085861200, -0.244071200", \ - "0.0115284000, 0.0101688000, 0.0071464000, -0.002204000, -0.025332000, -0.085656700, -0.243846800"); - } - related_pin : "SLEEP_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013054670, 0.0034084860, 0.0088993300, 0.0232355600, 0.0606665000, 0.1583962000"); - values("0.0099540000, 0.0113288000, 0.0148601000, 0.0237230000, 0.0466245000, 0.1064193000, 0.2628997000", \ - "0.0099071000, 0.0112947000, 0.0147963000, 0.0235943000, 0.0465181000, 0.1070239000, 0.2636375000", \ - "0.0097941000, 0.0111693000, 0.0146685000, 0.0235634000, 0.0465247000, 0.1069565000, 0.2629234000", \ - "0.0096171000, 0.0109888000, 0.0144687000, 0.0233895000, 0.0463804000, 0.1063675000, 0.2643670000", \ - "0.0095336000, 0.0108720000, 0.0143180000, 0.0231603000, 0.0462240000, 0.1062808000, 0.2632289000", \ - "0.0097039000, 0.0110450000, 0.0144742000, 0.0232250000, 0.0463406000, 0.1059751000, 0.2629322000", \ - "0.0100696000, 0.0112933000, 0.0147459000, 0.0236581000, 0.0468086000, 0.1071174000, 0.2634866000"); - } - } - max_capacitance : 0.1583960000; - max_transition : 1.5104930000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.1031383000, 0.1090369000, 0.1213519000, 0.1458819000, 0.1983965000, 0.3245319000, 0.6507022000", \ - "0.1078665000, 0.1139983000, 0.1263610000, 0.1508638000, 0.2034434000, 0.3294200000, 0.6551888000", \ - "0.1206382000, 0.1264383000, 0.1387166000, 0.1632862000, 0.2158505000, 0.3420344000, 0.6674351000", \ - "0.1518939000, 0.1576136000, 0.1699008000, 0.1946328000, 0.2471551000, 0.3730970000, 0.6997410000", \ - "0.2217431000, 0.2278479000, 0.2405078000, 0.2657816000, 0.3188938000, 0.4447553000, 0.7715348000", \ - "0.3381809000, 0.3460206000, 0.3619098000, 0.3912823000, 0.4477396000, 0.5756008000, 0.8998989000", \ - "0.5209776000, 0.5311577000, 0.5518847000, 0.5890423000, 0.6537268000, 0.7846471000, 1.1087463000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0794242000, 0.0864667000, 0.1026603000, 0.1403230000, 0.2350631000, 0.4803423000, 1.1196789000", \ - "0.0835845000, 0.0906672000, 0.1068781000, 0.1445428000, 0.2394144000, 0.4849028000, 1.1245087000", \ - "0.0941941000, 0.1012077000, 0.1174051000, 0.1552419000, 0.2499132000, 0.4948990000, 1.1391017000", \ - "0.1176439000, 0.1247226000, 0.1408894000, 0.1787277000, 0.2738498000, 0.5216426000, 1.1591080000", \ - "0.1531869000, 0.1607167000, 0.1775795000, 0.2162935000, 0.3111585000, 0.5577310000, 1.1975008000", \ - "0.1957092000, 0.2050777000, 0.2236305000, 0.2628502000, 0.3577440000, 0.6035356000, 1.2459085000", \ - "0.2281206000, 0.2408570000, 0.2647271000, 0.3094159000, 0.4035527000, 0.6494337000, 1.2897596000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0234153000, 0.0276024000, 0.0374098000, 0.0604597000, 0.1196515000, 0.2827106000, 0.7157019000", \ - "0.0233323000, 0.0278020000, 0.0374386000, 0.0605734000, 0.1193361000, 0.2823191000, 0.7152689000", \ - "0.0236597000, 0.0276025000, 0.0373997000, 0.0604277000, 0.1196194000, 0.2826888000, 0.7158011000", \ - "0.0234196000, 0.0278806000, 0.0376073000, 0.0605204000, 0.1195282000, 0.2822352000, 0.7153240000", \ - "0.0272264000, 0.0310681000, 0.0402238000, 0.0623276000, 0.1203398000, 0.2819205000, 0.7129985000", \ - "0.0383181000, 0.0427394000, 0.0521954000, 0.0735420000, 0.1279992000, 0.2841739000, 0.7151715000", \ - "0.0565871000, 0.0622415000, 0.0731304000, 0.0952605000, 0.1458810000, 0.2922328000, 0.7139613000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0273098000, 0.0343713000, 0.0528321000, 0.1021536000, 0.2350815000, 0.5873246000, 1.4968455000", \ - "0.0273840000, 0.0345314000, 0.0528703000, 0.1020276000, 0.2352878000, 0.5844607000, 1.5043444000", \ - "0.0272861000, 0.0344569000, 0.0528450000, 0.1020791000, 0.2354850000, 0.5860426000, 1.5063638000", \ - "0.0281736000, 0.0351018000, 0.0533746000, 0.1020422000, 0.2353452000, 0.5880494000, 1.4962932000", \ - "0.0322034000, 0.0387938000, 0.0565736000, 0.1041765000, 0.2354808000, 0.5855712000, 1.5004152000", \ - "0.0416308000, 0.0483148000, 0.0637518000, 0.1082114000, 0.2369543000, 0.5852857000, 1.5016702000", \ - "0.0592551000, 0.0662234000, 0.0807632000, 0.1200596000, 0.2402845000, 0.5869897000, 1.4960598000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.1209156000, 0.1267669000, 0.1392474000, 0.1641813000, 0.2170752000, 0.3433146000, 0.6697209000", \ - "0.1256830000, 0.1315514000, 0.1440896000, 0.1689204000, 0.2217300000, 0.3480779000, 0.6741255000", \ - "0.1389034000, 0.1447728000, 0.1571298000, 0.1822106000, 0.2351275000, 0.3612713000, 0.6883352000", \ - "0.1707242000, 0.1765896000, 0.1891511000, 0.2141875000, 0.2671949000, 0.3935670000, 0.7206127000", \ - "0.2458760000, 0.2518757000, 0.2643657000, 0.2895802000, 0.3426674000, 0.4691481000, 0.7961913000", \ - "0.3811535000, 0.3887241000, 0.4037608000, 0.4324255000, 0.4886735000, 0.6161632000, 0.9428820000", \ - "0.5985440000, 0.6084658000, 0.6283749000, 0.6649080000, 0.7281128000, 0.8587321000, 1.1855078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0850944000, 0.0921667000, 0.1083601000, 0.1458898000, 0.2402782000, 0.4848659000, 1.1236686000", \ - "0.0895209000, 0.0965853000, 0.1127460000, 0.1502857000, 0.2446479000, 0.4893743000, 1.1342738000", \ - "0.0986120000, 0.1056416000, 0.1217442000, 0.1594235000, 0.2536776000, 0.4999385000, 1.1385588000", \ - "0.1181221000, 0.1252344000, 0.1413930000, 0.1790957000, 0.2739872000, 0.5188981000, 1.1647858000", \ - "0.1507703000, 0.1583374000, 0.1753158000, 0.2136513000, 0.3088211000, 0.5540685000, 1.1962887000", \ - "0.1919068000, 0.2007971000, 0.2194776000, 0.2593621000, 0.3543002000, 0.6003611000, 1.2398564000", \ - "0.2215551000, 0.2331939000, 0.2570880000, 0.3014003000, 0.3978440000, 0.6441577000, 1.2831414000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0247853000, 0.0292438000, 0.0387901000, 0.0620392000, 0.1209422000, 0.2836178000, 0.7178857000", \ - "0.0248114000, 0.0293590000, 0.0386992000, 0.0620453000, 0.1208171000, 0.2830563000, 0.7159824000", \ - "0.0251101000, 0.0293904000, 0.0389104000, 0.0620770000, 0.1207057000, 0.2830010000, 0.7188303000", \ - "0.0248417000, 0.0293683000, 0.0387121000, 0.0619855000, 0.1210290000, 0.2832596000, 0.7174237000", \ - "0.0263278000, 0.0301791000, 0.0395620000, 0.0626238000, 0.1210035000, 0.2826644000, 0.7209016000", \ - "0.0372131000, 0.0416577000, 0.0506625000, 0.0722733000, 0.1267676000, 0.2838049000, 0.7191795000", \ - "0.0552276000, 0.0607121000, 0.0714424000, 0.0921616000, 0.1430103000, 0.2911559000, 0.7147608000"); - } - related_pin : "SLEEP_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013054700, 0.0034084900, 0.0088993300, 0.0232356000, 0.0606665000, 0.1583960000"); - values("0.0273552000, 0.0344671000, 0.0528882000, 0.1019307000, 0.2352126000, 0.5862400000, 1.5035762000", \ - "0.0273356000, 0.0344320000, 0.0528311000, 0.1021694000, 0.2347287000, 0.5867600000, 1.5065106000", \ - "0.0274144000, 0.0344779000, 0.0527378000, 0.1020965000, 0.2352505000, 0.5875913000, 1.5000867000", \ - "0.0280319000, 0.0350671000, 0.0532333000, 0.1021433000, 0.2352442000, 0.5851101000, 1.5104931000", \ - "0.0312514000, 0.0380700000, 0.0560639000, 0.1036146000, 0.2350764000, 0.5868111000, 1.5016938000", \ - "0.0386276000, 0.0457767000, 0.0620114000, 0.1072882000, 0.2371053000, 0.5845895000, 1.5012384000", \ - "0.0545211000, 0.0615401000, 0.0773975000, 0.1178962000, 0.2399373000, 0.5878344000, 1.4954710000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_inputiso0p_1") { - leakage_power () { - value : 0.0011725000; - when : "!SLEEP&A"; - } - leakage_power () { - value : 0.0064238000; - when : "!SLEEP&!A"; - } - leakage_power () { - value : 0.0069574000; - when : "SLEEP&A"; - } - leakage_power () { - value : 0.0066454000; - when : "SLEEP&!A"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__inputiso0p"; - cell_leakage_power : 0.0052998180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0016410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027312000, 0.0027277000, 0.0027197000, 0.0027198000, 0.0027198000, 0.0027200000, 0.0027203000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002728500, -0.002722700, -0.002709400, -0.002709600, -0.002710100, -0.002711200, -0.002713800"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017100000; - } - pin ("SLEEP") { - capacitance : 0.0015580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0064953000, 0.0063858000, 0.0061335000, 0.0061711000, 0.0062576000, 0.0064572000, 0.0069170000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022895000, 0.0022114000, 0.0020313000, 0.0020622000, 0.0021334000, 0.0022975000, 0.0026757000"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016200000; - } - pin ("X") { - direction : "output"; - function : "(!SLEEP&A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0079535000, 0.0068127000, 0.0037296000, -0.005028500, -0.029246400, -0.093751500, -0.264195900", \ - "0.0078302000, 0.0066852000, 0.0036332000, -0.005133400, -0.029355600, -0.093849300, -0.264271400", \ - "0.0076646000, 0.0065152000, 0.0034400000, -0.005323900, -0.029505300, -0.094004600, -0.264458400", \ - "0.0075132000, 0.0063450000, 0.0032648000, -0.005498800, -0.029690700, -0.094144300, -0.264577000", \ - "0.0075533000, 0.0063529000, 0.0032511000, -0.005557400, -0.029729100, -0.094161200, -0.264560000", \ - "0.0079112000, 0.0065782000, 0.0030516000, -0.005624900, -0.029706400, -0.094081200, -0.264467000", \ - "0.0090901000, 0.0077078000, 0.0040932000, -0.005091400, -0.029483800, -0.093712200, -0.264085800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0110563000, 0.0125044000, 0.0161606000, 0.0253488000, 0.0494525000, 0.1132007000, 0.2816314000", \ - "0.0109835000, 0.0124374000, 0.0160377000, 0.0253371000, 0.0494307000, 0.1138509000, 0.2834915000", \ - "0.0108426000, 0.0122828000, 0.0159265000, 0.0251935000, 0.0493201000, 0.1131013000, 0.2831438000", \ - "0.0106853000, 0.0120959000, 0.0157381000, 0.0250403000, 0.0492392000, 0.1130062000, 0.2820709000", \ - "0.0106267000, 0.0119908000, 0.0155867000, 0.0248663000, 0.0490749000, 0.1136625000, 0.2830712000", \ - "0.0109476000, 0.0122623000, 0.0157790000, 0.0248220000, 0.0491127000, 0.1131103000, 0.2814059000", \ - "0.0113153000, 0.0126001000, 0.0161412000, 0.0253813000, 0.0496870000, 0.1136278000, 0.2821418000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0074935000, 0.0063767000, 0.0034907000, -0.005056500, -0.029153200, -0.093596400, -0.263855300", \ - "0.0074615000, 0.0063473000, 0.0034617000, -0.005088800, -0.029187500, -0.093631300, -0.264031400", \ - "0.0074080000, 0.0063151000, 0.0034000000, -0.005160700, -0.029252100, -0.093707900, -0.264134800", \ - "0.0070621000, 0.0059710000, 0.0030545000, -0.005501000, -0.029594100, -0.094028400, -0.264467200", \ - "0.0067670000, 0.0056730000, 0.0027625000, -0.005808100, -0.029885500, -0.094320200, -0.264753400", \ - "0.0077758000, 0.0066284000, 0.0032824000, -0.005677700, -0.029961900, -0.094385000, -0.264800500", \ - "0.0080097000, 0.0067373000, 0.0033607000, -0.005765000, -0.029866000, -0.094216000, -0.264709000"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0107229000, 0.0121567000, 0.0157871000, 0.0250888000, 0.0492976000, 0.1130790000, 0.2833514000", \ - "0.0106409000, 0.0120710000, 0.0156960000, 0.0250075000, 0.0492152000, 0.1136795000, 0.2834403000", \ - "0.0107082000, 0.0121188000, 0.0157694000, 0.0250929000, 0.0493041000, 0.1138411000, 0.2817097000", \ - "0.0105537000, 0.0119603000, 0.0156124000, 0.0249333000, 0.0491499000, 0.1136807000, 0.2814867000", \ - "0.0103154000, 0.0117464000, 0.0154094000, 0.0246977000, 0.0488982000, 0.1134589000, 0.2815859000", \ - "0.0102670000, 0.0116193000, 0.0151769000, 0.0246308000, 0.0487984000, 0.1125745000, 0.2815379000", \ - "0.0104464000, 0.0118109000, 0.0153750000, 0.0246923000, 0.0486490000, 0.1129486000, 0.2819707000"); - } - } - max_capacitance : 0.1693830000; - max_transition : 1.5054720000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1199863000, 0.1265781000, 0.1400131000, 0.1666531000, 0.2224236000, 0.3570231000, 0.7099723000", \ - "0.1250548000, 0.1316339000, 0.1452184000, 0.1716032000, 0.2274099000, 0.3621982000, 0.7145364000", \ - "0.1379036000, 0.1444814000, 0.1580019000, 0.1845344000, 0.2403661000, 0.3751293000, 0.7278572000", \ - "0.1694781000, 0.1760865000, 0.1896301000, 0.2161382000, 0.2720285000, 0.4068058000, 0.7591652000", \ - "0.2458634000, 0.2524315000, 0.2658675000, 0.2925810000, 0.3485419000, 0.4834041000, 0.8373479000", \ - "0.3838306000, 0.3921876000, 0.4088603000, 0.4390783000, 0.4983279000, 0.6343951000, 0.9872323000", \ - "0.6065288000, 0.6179148000, 0.6395095000, 0.6781659000, 0.7451771000, 0.8840089000, 1.2363512000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0838781000, 0.0911042000, 0.1072763000, 0.1442256000, 0.2366408000, 0.4805009000, 1.1243945000", \ - "0.0882505000, 0.0954667000, 0.1115282000, 0.1487114000, 0.2411155000, 0.4848837000, 1.1286794000", \ - "0.0967619000, 0.1039781000, 0.1201182000, 0.1572448000, 0.2501456000, 0.4934158000, 1.1372914000", \ - "0.1150863000, 0.1223202000, 0.1385309000, 0.1757465000, 0.2687521000, 0.5120033000, 1.1563656000", \ - "0.1460576000, 0.1538838000, 0.1709790000, 0.2088468000, 0.3023193000, 0.5465656000, 1.1936251000", \ - "0.1858267000, 0.1949655000, 0.2141958000, 0.2538680000, 0.3476875000, 0.5917902000, 1.2352768000", \ - "0.2123323000, 0.2249135000, 0.2497402000, 0.2948591000, 0.3904713000, 0.6353933000, 1.2774820000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0234037000, 0.0278373000, 0.0380796000, 0.0620759000, 0.1241979000, 0.2967690000, 0.7654454000", \ - "0.0236030000, 0.0279404000, 0.0381719000, 0.0621983000, 0.1240991000, 0.2979788000, 0.7661394000", \ - "0.0234166000, 0.0277736000, 0.0379419000, 0.0621270000, 0.1239001000, 0.2991705000, 0.7670851000", \ - "0.0237789000, 0.0280063000, 0.0381488000, 0.0621028000, 0.1242366000, 0.2974057000, 0.7646313000", \ - "0.0246207000, 0.0288136000, 0.0387680000, 0.0626422000, 0.1240993000, 0.2971583000, 0.7674734000", \ - "0.0349228000, 0.0397025000, 0.0493984000, 0.0722056000, 0.1296210000, 0.2985638000, 0.7692271000", \ - "0.0518292000, 0.0580550000, 0.0698601000, 0.0927064000, 0.1459282000, 0.3053101000, 0.7645866000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0237516000, 0.0306288000, 0.0484043000, 0.0960915000, 0.2264680000, 0.5761326000, 1.4949072000", \ - "0.0237342000, 0.0306288000, 0.0484193000, 0.0960477000, 0.2265569000, 0.5785052000, 1.5040148000", \ - "0.0237889000, 0.0306684000, 0.0483784000, 0.0960552000, 0.2265904000, 0.5765163000, 1.5020080000", \ - "0.0243544000, 0.0312152000, 0.0486778000, 0.0960202000, 0.2264808000, 0.5765746000, 1.5013124000", \ - "0.0273969000, 0.0342241000, 0.0515200000, 0.0979892000, 0.2265500000, 0.5788929000, 1.5054720000", \ - "0.0349308000, 0.0413823000, 0.0576584000, 0.1019669000, 0.2287239000, 0.5751755000, 1.5006382000", \ - "0.0493190000, 0.0568586000, 0.0746315000, 0.1130123000, 0.2315859000, 0.5774929000, 1.4931757000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1392650000, 0.1458357000, 0.1593139000, 0.1860438000, 0.2419807000, 0.3768078000, 0.7286305000", \ - "0.1439327000, 0.1504916000, 0.1639517000, 0.1906770000, 0.2466204000, 0.3814537000, 0.7333245000", \ - "0.1545366000, 0.1611028000, 0.1746691000, 0.2012972000, 0.2572374000, 0.3919094000, 0.7436498000", \ - "0.1746736000, 0.1812186000, 0.1947530000, 0.2214205000, 0.2773547000, 0.4121894000, 0.7641930000", \ - "0.2036706000, 0.2102273000, 0.2238358000, 0.2504734000, 0.3064524000, 0.4414209000, 0.7934335000", \ - "0.2392959000, 0.2455047000, 0.2592673000, 0.2861039000, 0.3422300000, 0.4769604000, 0.8288117000", \ - "0.2733526000, 0.2799868000, 0.2935377000, 0.3203983000, 0.3766646000, 0.5115428000, 0.8643506000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1492003000, 0.1564235000, 0.1725819000, 0.2099364000, 0.3030909000, 0.5486901000, 1.1914337000", \ - "0.1536454000, 0.1609205000, 0.1770845000, 0.2142684000, 0.3072854000, 0.5510123000, 1.1956970000", \ - "0.1664387000, 0.1736225000, 0.1899007000, 0.2272088000, 0.3200731000, 0.5638116000, 1.2061662000", \ - "0.1981163000, 0.2052915000, 0.2215710000, 0.2588745000, 0.3518001000, 0.5950800000, 1.2392886000", \ - "0.2639613000, 0.2712435000, 0.2875205000, 0.3248054000, 0.4179941000, 0.6613859000, 1.3083492000", \ - "0.3708452000, 0.3782895000, 0.3947194000, 0.4321646000, 0.5255128000, 0.7693361000, 1.4148568000", \ - "0.5401635000, 0.5480243000, 0.5649956000, 0.6030036000, 0.6965747000, 0.9404294000, 1.5831167000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0229365000, 0.0271649000, 0.0375263000, 0.0616576000, 0.1235068000, 0.2968437000, 0.7630824000", \ - "0.0229216000, 0.0274942000, 0.0375277000, 0.0616572000, 0.1235014000, 0.2969376000, 0.7718066000", \ - "0.0229698000, 0.0270342000, 0.0374335000, 0.0618211000, 0.1237793000, 0.2987758000, 0.7640988000", \ - "0.0227934000, 0.0271371000, 0.0375491000, 0.0616255000, 0.1237057000, 0.2969390000, 0.7695316000", \ - "0.0228061000, 0.0273095000, 0.0374318000, 0.0617115000, 0.1238234000, 0.2988951000, 0.7665937000", \ - "0.0230600000, 0.0279017000, 0.0380791000, 0.0619374000, 0.1239544000, 0.2943655000, 0.7700216000", \ - "0.0238065000, 0.0281861000, 0.0389182000, 0.0624980000, 0.1242564000, 0.2972474000, 0.7656155000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0241662000, 0.0310191000, 0.0485768000, 0.0960339000, 0.2266130000, 0.5766232000, 1.5031136000", \ - "0.0240961000, 0.0309602000, 0.0487198000, 0.0961521000, 0.2262074000, 0.5774111000, 1.5046057000", \ - "0.0241192000, 0.0310659000, 0.0486482000, 0.0960338000, 0.2265092000, 0.5784240000, 1.4968609000", \ - "0.0241428000, 0.0310903000, 0.0486816000, 0.0960221000, 0.2264206000, 0.5782594000, 1.4972334000", \ - "0.0245398000, 0.0313107000, 0.0488383000, 0.0962749000, 0.2264389000, 0.5780660000, 1.5047629000", \ - "0.0254376000, 0.0322740000, 0.0496234000, 0.0969410000, 0.2259456000, 0.5752397000, 1.5001612000", \ - "0.0281758000, 0.0347108000, 0.0514864000, 0.0978821000, 0.2269993000, 0.5736586000, 1.4927060000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_inputiso1n_1") { - leakage_power () { - value : 0.0091109000; - when : "!A&SLEEP_B"; - } - leakage_power () { - value : 0.0015600000; - when : "!A&!SLEEP_B"; - } - leakage_power () { - value : 0.0028829000; - when : "A&SLEEP_B"; - } - leakage_power () { - value : 0.0007476000; - when : "A&!SLEEP_B"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__inputiso1n"; - cell_leakage_power : 0.0035753310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0017300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030986000, 0.0030802000, 0.0030378000, 0.0030361000, 0.0030321000, 0.0030229000, 0.0030018000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002892600, -0.002921200, -0.002987000, -0.002988100, -0.002990500, -0.002996000, -0.003008700"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017970000; - } - pin ("SLEEP_B") { - capacitance : 0.0014180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072289000, 0.0071462000, 0.0069556000, 0.0070287000, 0.0071970000, 0.0075849000, 0.0084791000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0005812000, 0.0005066000, 0.0003346000, 0.0004029000, 0.0005605000, 0.0009238000, 0.0017612000"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014690000; - } - pin ("X") { - direction : "output"; - function : "(A) | (!SLEEP_B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0076180000, 0.0065644000, 0.0036783000, -0.004730600, -0.028640600, -0.093126300, -0.263501600", \ - "0.0075492000, 0.0064520000, 0.0035634000, -0.004807800, -0.028767000, -0.093274500, -0.263641300", \ - "0.0074577000, 0.0063172000, 0.0034369000, -0.004929500, -0.028893800, -0.093353500, -0.263852700", \ - "0.0072979000, 0.0061682000, 0.0032709000, -0.005111400, -0.029031000, -0.093479300, -0.263946500", \ - "0.0072299000, 0.0060920000, 0.0031856000, -0.005237800, -0.029134000, -0.093558500, -0.263981800", \ - "0.0075168000, 0.0061471000, 0.0028717000, -0.005319500, -0.029189100, -0.093540800, -0.263974500", \ - "0.0095286000, 0.0081187000, 0.0045382000, -0.004726700, -0.029101000, -0.093305800, -0.263689900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0095030000, 0.0109069000, 0.0144974000, 0.0237296000, 0.0478593000, 0.1115219000, 0.2813646000", \ - "0.0094728000, 0.0108774000, 0.0144655000, 0.0236944000, 0.0478711000, 0.1116195000, 0.2799064000", \ - "0.0094586000, 0.0108466000, 0.0144320000, 0.0236781000, 0.0478981000, 0.1116467000, 0.2799695000", \ - "0.0093251000, 0.0106589000, 0.0142070000, 0.0235141000, 0.0477664000, 0.1115009000, 0.2800344000", \ - "0.0093600000, 0.0106786000, 0.0140599000, 0.0233778000, 0.0475156000, 0.1114427000, 0.2796804000", \ - "0.0096198000, 0.0109857000, 0.0145118000, 0.0235838000, 0.0478353000, 0.1118081000, 0.2799276000", \ - "0.0102905000, 0.0116153000, 0.0150946000, 0.0240904000, 0.0485779000, 0.1126945000, 0.2808741000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0074098000, 0.0062858000, 0.0034083000, -0.004978000, -0.028847400, -0.093226900, -0.263622500", \ - "0.0073547000, 0.0063104000, 0.0033599000, -0.005000500, -0.028891200, -0.093270000, -0.263746600", \ - "0.0073624000, 0.0062445000, 0.0033665000, -0.005023800, -0.028915200, -0.093294900, -0.263726400", \ - "0.0070871000, 0.0059602000, 0.0030945000, -0.005270700, -0.029172500, -0.093563700, -0.263997900", \ - "0.0068940000, 0.0057571000, 0.0028711000, -0.005501000, -0.029389900, -0.093778900, -0.264197800", \ - "0.0086772000, 0.0073721000, 0.0039743000, -0.005152200, -0.029347300, -0.093736000, -0.264182500", \ - "0.0089561000, 0.0076160000, 0.0043330000, -0.004779600, -0.029089600, -0.093564700, -0.264022100"); - } - related_pin : "SLEEP_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0093548000, 0.0107950000, 0.0144553000, 0.0238651000, 0.0481652000, 0.1120690000, 0.2809578000", \ - "0.0092565000, 0.0107078000, 0.0144086000, 0.0238011000, 0.0481284000, 0.1121327000, 0.2807638000", \ - "0.0093118000, 0.0107609000, 0.0144095000, 0.0238243000, 0.0483840000, 0.1121537000, 0.2809352000", \ - "0.0091643000, 0.0105987000, 0.0142781000, 0.0236601000, 0.0480205000, 0.1118368000, 0.2808248000", \ - "0.0088637000, 0.0103019000, 0.0139771000, 0.0233688000, 0.0477459000, 0.1123822000, 0.2798486000", \ - "0.0086897000, 0.0100467000, 0.0136463000, 0.0231494000, 0.0475367000, 0.1112927000, 0.2818293000", \ - "0.0087999000, 0.0102002000, 0.0138217000, 0.0231717000, 0.0474091000, 0.1119591000, 0.2811932000"); - } - } - max_capacitance : 0.1693830000; - max_transition : 1.5052250000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1827175000, 0.1911866000, 0.2085506000, 0.2416795000, 0.3054609000, 0.4450723000, 0.7958804000", \ - "0.1863574000, 0.1948635000, 0.2122326000, 0.2452678000, 0.3091268000, 0.4486202000, 0.7996058000", \ - "0.1971171000, 0.2055551000, 0.2228775000, 0.2559461000, 0.3198181000, 0.4593202000, 0.8102953000", \ - "0.2228332000, 0.2311077000, 0.2486548000, 0.2816886000, 0.3456467000, 0.4850919000, 0.8362598000", \ - "0.2828147000, 0.2912530000, 0.3084875000, 0.3415973000, 0.4056804000, 0.5452236000, 0.8954111000", \ - "0.3989890000, 0.4084370000, 0.4275713000, 0.4635761000, 0.5308664000, 0.6720228000, 1.0227215000", \ - "0.5992223000, 0.6105448000, 0.6333423000, 0.6753255000, 0.7502746000, 0.8981512000, 1.2515036000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0578320000, 0.0638828000, 0.0782267000, 0.1137355000, 0.2062375000, 0.4506019000, 1.0957251000", \ - "0.0625460000, 0.0685856000, 0.0829339000, 0.1185949000, 0.2112872000, 0.4556407000, 1.1007854000", \ - "0.0739084000, 0.0798609000, 0.0942023000, 0.1299553000, 0.2227480000, 0.4671682000, 1.1123603000", \ - "0.0964967000, 0.1024277000, 0.1170532000, 0.1528964000, 0.2458775000, 0.4898994000, 1.1341750000", \ - "0.1272872000, 0.1338854000, 0.1491276000, 0.1850319000, 0.2781454000, 0.5226916000, 1.1666138000", \ - "0.1595451000, 0.1685168000, 0.1856449000, 0.2223179000, 0.3157267000, 0.5599682000, 1.2054252000", \ - "0.1726502000, 0.1843029000, 0.2073468000, 0.2476004000, 0.3405360000, 0.5854370000, 1.2294677000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0323800000, 0.0380363000, 0.0507963000, 0.0769428000, 0.1394173000, 0.3043676000, 0.7674248000", \ - "0.0325215000, 0.0380841000, 0.0506920000, 0.0764608000, 0.1393533000, 0.3047012000, 0.7674419000", \ - "0.0323191000, 0.0382675000, 0.0507411000, 0.0764162000, 0.1393972000, 0.3047077000, 0.7674262000", \ - "0.0327794000, 0.0380180000, 0.0502647000, 0.0765583000, 0.1391639000, 0.3045051000, 0.7686498000", \ - "0.0325755000, 0.0382426000, 0.0502809000, 0.0769086000, 0.1390998000, 0.3046123000, 0.7669475000", \ - "0.0388489000, 0.0447816000, 0.0575329000, 0.0839786000, 0.1440897000, 0.3072923000, 0.7672585000", \ - "0.0516863000, 0.0584792000, 0.0727906000, 0.1000341000, 0.1614214000, 0.3175368000, 0.7682240000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0189567000, 0.0256974000, 0.0438822000, 0.0934332000, 0.2254962000, 0.5753925000, 1.5003612000", \ - "0.0189016000, 0.0256782000, 0.0439069000, 0.0935912000, 0.2262504000, 0.5764313000, 1.5008208000", \ - "0.0189155000, 0.0256468000, 0.0438242000, 0.0935747000, 0.2262818000, 0.5764854000, 1.5012058000", \ - "0.0201868000, 0.0268045000, 0.0445116000, 0.0935837000, 0.2259902000, 0.5749565000, 1.4972388000", \ - "0.0241727000, 0.0302117000, 0.0467765000, 0.0944311000, 0.2259048000, 0.5749293000, 1.4962236000", \ - "0.0324831000, 0.0384576000, 0.0530740000, 0.0972637000, 0.2270195000, 0.5743536000, 1.5012053000", \ - "0.0461616000, 0.0531077000, 0.0684881000, 0.1070996000, 0.2288073000, 0.5794231000, 1.4968247000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1855699000, 0.1940474000, 0.2114429000, 0.2446774000, 0.3084756000, 0.4482210000, 0.7990666000", \ - "0.1901692000, 0.1986433000, 0.2159866000, 0.2487961000, 0.3129121000, 0.4526511000, 0.8030037000", \ - "0.1999247000, 0.2084395000, 0.2258464000, 0.2590083000, 0.3228526000, 0.4625804000, 0.8134340000", \ - "0.2157333000, 0.2241877000, 0.2416480000, 0.2748325000, 0.3387490000, 0.4782040000, 0.8294266000", \ - "0.2378082000, 0.2461970000, 0.2635533000, 0.2967134000, 0.3605831000, 0.5001640000, 0.8507047000", \ - "0.2610976000, 0.2695559000, 0.2868423000, 0.3199851000, 0.3841904000, 0.5239105000, 0.8751936000", \ - "0.2749161000, 0.2834088000, 0.3007491000, 0.3339582000, 0.3982462000, 0.5380760000, 0.8890909000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1143938000, 0.1205169000, 0.1351134000, 0.1713965000, 0.2646251000, 0.5120384000, 1.1565232000", \ - "0.1192435000, 0.1254001000, 0.1400493000, 0.1763133000, 0.2696009000, 0.5149999000, 1.1583901000", \ - "0.1317683000, 0.1379338000, 0.1524701000, 0.1887489000, 0.2821667000, 0.5275232000, 1.1747425000", \ - "0.1626610000, 0.1687685000, 0.1834178000, 0.2197681000, 0.3131095000, 0.5599241000, 1.2023558000", \ - "0.2212063000, 0.2273899000, 0.2420483000, 0.2781404000, 0.3714221000, 0.6166982000, 1.2722515000", \ - "0.3122213000, 0.3184332000, 0.3331819000, 0.3692582000, 0.4625626000, 0.7070304000, 1.3536171000", \ - "0.4553272000, 0.4621084000, 0.4771966000, 0.5136137000, 0.6069091000, 0.8520279000, 1.4960123000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0323302000, 0.0378943000, 0.0506948000, 0.0767050000, 0.1392018000, 0.3043340000, 0.7691875000", \ - "0.0323776000, 0.0382254000, 0.0506333000, 0.0770539000, 0.1393459000, 0.3043999000, 0.7670736000", \ - "0.0324982000, 0.0382359000, 0.0502082000, 0.0773185000, 0.1391087000, 0.3046761000, 0.7701900000", \ - "0.0327475000, 0.0384722000, 0.0502035000, 0.0772753000, 0.1388963000, 0.3043907000, 0.7680859000", \ - "0.0322880000, 0.0381690000, 0.0499745000, 0.0765653000, 0.1390371000, 0.3047242000, 0.7727575000", \ - "0.0326593000, 0.0385160000, 0.0509282000, 0.0764213000, 0.1393230000, 0.3038034000, 0.7693918000", \ - "0.0329987000, 0.0385869000, 0.0503368000, 0.0766206000, 0.1394895000, 0.3053660000, 0.7627707000"); - } - related_pin : "SLEEP_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0191016000, 0.0257904000, 0.0437899000, 0.0931943000, 0.2253136000, 0.5777535000, 1.5048444000", \ - "0.0191504000, 0.0258120000, 0.0438557000, 0.0933141000, 0.2253088000, 0.5772061000, 1.4995182000", \ - "0.0191371000, 0.0257920000, 0.0438041000, 0.0932245000, 0.2259144000, 0.5765231000, 1.5011506000", \ - "0.0191570000, 0.0257634000, 0.0438816000, 0.0932944000, 0.2257061000, 0.5777849000, 1.5049165000", \ - "0.0196569000, 0.0262558000, 0.0441719000, 0.0932970000, 0.2256878000, 0.5776513000, 1.5017404000", \ - "0.0207691000, 0.0272501000, 0.0447707000, 0.0934164000, 0.2254542000, 0.5743687000, 1.5052248000", \ - "0.0235383000, 0.0295345000, 0.0460928000, 0.0941077000, 0.2255391000, 0.5748724000, 1.4996832000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_inputiso1p_1") { - leakage_power () { - value : 0.0006548000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0052491000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0003472000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0011452000; - when : "A&!SLEEP"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__inputiso1p"; - cell_leakage_power : 0.0018491060; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011586000, 0.0011575000, 0.0011549000, 0.0011581000, 0.0011656000, 0.0011828000, 0.0012224000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000796100, -0.000793100, -0.000786000, -0.000786200, -0.000786600, -0.000787600, -0.000789700"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015470000; - } - pin ("SLEEP") { - capacitance : 0.0014710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016996000, 0.0016953000, 0.0016852000, 0.0016858000, 0.0016871000, 0.0016901000, 0.0016970000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001538500, -0.001566500, -0.001630900, -0.001632800, -0.001637300, -0.001647600, -0.001671200"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015430000; - } - pin ("X") { - direction : "output"; - function : "(A) | (SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0082542000, 0.0071384000, 0.0042447000, -0.004001400, -0.027349500, -0.090080400, -0.255470700", \ - "0.0081001000, 0.0069920000, 0.0040722000, -0.004175700, -0.027469300, -0.090244400, -0.255595000", \ - "0.0078551000, 0.0067518000, 0.0039350000, -0.004333000, -0.027650200, -0.090342600, -0.255730000", \ - "0.0078118000, 0.0066864000, 0.0037999000, -0.004476400, -0.027804700, -0.090482100, -0.255841300", \ - "0.0077405000, 0.0066067000, 0.0037098000, -0.004541800, -0.027858100, -0.090553000, -0.255874400", \ - "0.0079367000, 0.0065724000, 0.0036538000, -0.004351200, -0.027676000, -0.090320100, -0.255609200", \ - "0.0107681000, 0.0093063000, 0.0057204000, -0.003410800, -0.027077500, -0.089782600, -0.255107000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0084911000, 0.0099422000, 0.0136350000, 0.0229121000, 0.0467644000, 0.1090685000, 0.2728353000", \ - "0.0084730000, 0.0099184000, 0.0135909000, 0.0228780000, 0.0467011000, 0.1096846000, 0.2728155000", \ - "0.0083554000, 0.0097747000, 0.0134219000, 0.0226985000, 0.0466430000, 0.1090396000, 0.2723552000", \ - "0.0081585000, 0.0095423000, 0.0131350000, 0.0223343000, 0.0461053000, 0.1094534000, 0.2732780000", \ - "0.0080779000, 0.0094086000, 0.0128871000, 0.0220449000, 0.0458669000, 0.1084553000, 0.2723879000", \ - "0.0083008000, 0.0096282000, 0.0131395000, 0.0220997000, 0.0460528000, 0.1081646000, 0.2734355000", \ - "0.0089789000, 0.0102682000, 0.0136983000, 0.0225984000, 0.0465765000, 0.1090971000, 0.2708041000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0087496000, 0.0076222000, 0.0047719000, -0.003440000, -0.026862200, -0.089675200, -0.255093400", \ - "0.0085985000, 0.0074763000, 0.0046093000, -0.003592600, -0.027003300, -0.089815300, -0.255222500", \ - "0.0084328000, 0.0073186000, 0.0044639000, -0.003774900, -0.027163400, -0.089943800, -0.255395100", \ - "0.0082965000, 0.0071986000, 0.0043375000, -0.003932200, -0.027314100, -0.090092100, -0.255538500", \ - "0.0082384000, 0.0071116000, 0.0042094000, -0.004056400, -0.027414400, -0.090201300, -0.255546600", \ - "0.0082975000, 0.0069281000, 0.0039140000, -0.004187700, -0.027494700, -0.090209700, -0.255565800", \ - "0.0103520000, 0.0089754000, 0.0054510000, -0.003625500, -0.027455100, -0.090054300, -0.255339400"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0097395000, 0.0111229000, 0.0146617000, 0.0237150000, 0.0473419000, 0.1094527000, 0.2742520000", \ - "0.0097054000, 0.0110896000, 0.0146276000, 0.0237119000, 0.0473279000, 0.1094209000, 0.2728241000", \ - "0.0096768000, 0.0110598000, 0.0146009000, 0.0237030000, 0.0474050000, 0.1095138000, 0.2728375000", \ - "0.0094897000, 0.0108583000, 0.0143975000, 0.0235174000, 0.0472964000, 0.1094396000, 0.2727237000", \ - "0.0095685000, 0.0108714000, 0.0142818000, 0.0233859000, 0.0471188000, 0.1099142000, 0.2740395000", \ - "0.0097238000, 0.0110239000, 0.0144237000, 0.0234218000, 0.0472594000, 0.1091029000, 0.2737052000", \ - "0.0104243000, 0.0117175000, 0.0151188000, 0.0240722000, 0.0479246000, 0.1105488000, 0.2737236000"); - } - } - max_capacitance : 0.1648050000; - max_transition : 1.5039020000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.1725031000, 0.1807181000, 0.1975736000, 0.2300184000, 0.2936754000, 0.4313663000, 0.7740169000", \ - "0.1747533000, 0.1829721000, 0.1999481000, 0.2327820000, 0.2960763000, 0.4337455000, 0.7767721000", \ - "0.1838108000, 0.1919689000, 0.2089423000, 0.2422758000, 0.3055627000, 0.4432234000, 0.7861942000", \ - "0.2113854000, 0.2195175000, 0.2364662000, 0.2690460000, 0.3325148000, 0.4702345000, 0.8134618000", \ - "0.2781245000, 0.2862324000, 0.3030400000, 0.3354571000, 0.3987519000, 0.5362343000, 0.8795532000", \ - "0.4083673000, 0.4177363000, 0.4367286000, 0.4726639000, 0.5391279000, 0.6767730000, 1.0169202000", \ - "0.6129212000, 0.6246662000, 0.6487311000, 0.6917876000, 0.7654749000, 0.9085679000, 1.2559802000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0579334000, 0.0641360000, 0.0791173000, 0.1158324000, 0.2095510000, 0.4545797000, 1.0982594000", \ - "0.0629155000, 0.0690748000, 0.0840058000, 0.1207220000, 0.2150236000, 0.4594673000, 1.1033542000", \ - "0.0744534000, 0.0805720000, 0.0953857000, 0.1320271000, 0.2266472000, 0.4719370000, 1.1128860000", \ - "0.0968577000, 0.1030780000, 0.1179823000, 0.1543663000, 0.2484135000, 0.4961346000, 1.1420953000", \ - "0.1275259000, 0.1342911000, 0.1497404000, 0.1863441000, 0.2804570000, 0.5262206000, 1.1706781000", \ - "0.1621944000, 0.1709396000, 0.1883554000, 0.2254937000, 0.3196119000, 0.5643043000, 1.2108842000", \ - "0.1816322000, 0.1935230000, 0.2165707000, 0.2582129000, 0.3517420000, 0.5972302000, 1.2386342000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0352630000, 0.0404178000, 0.0531126000, 0.0795559000, 0.1398494000, 0.3010868000, 0.7545574000", \ - "0.0355952000, 0.0404739000, 0.0529724000, 0.0784269000, 0.1397764000, 0.3010788000, 0.7526275000", \ - "0.0355331000, 0.0404537000, 0.0529697000, 0.0784214000, 0.1397831000, 0.3014247000, 0.7513733000", \ - "0.0350985000, 0.0404364000, 0.0522709000, 0.0784450000, 0.1396806000, 0.3008159000, 0.7521222000", \ - "0.0354493000, 0.0408259000, 0.0525385000, 0.0793345000, 0.1400791000, 0.3012809000, 0.7522023000", \ - "0.0457423000, 0.0513731000, 0.0632017000, 0.0873335000, 0.1458167000, 0.3042553000, 0.7513327000", \ - "0.0647676000, 0.0713591000, 0.0845465000, 0.1100236000, 0.1649603000, 0.3164807000, 0.7508070000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0210835000, 0.0278963000, 0.0464762000, 0.0964323000, 0.2300657000, 0.5814482000, 1.5016379000", \ - "0.0210332000, 0.0278706000, 0.0464922000, 0.0966929000, 0.2303184000, 0.5824398000, 1.5037742000", \ - "0.0210793000, 0.0279788000, 0.0464721000, 0.0965122000, 0.2311161000, 0.5833692000, 1.4967140000", \ - "0.0226080000, 0.0291012000, 0.0471065000, 0.0966833000, 0.2295669000, 0.5851005000, 1.5039017000", \ - "0.0269303000, 0.0329646000, 0.0497410000, 0.0978490000, 0.2291641000, 0.5811172000, 1.5037807000", \ - "0.0363485000, 0.0422441000, 0.0569226000, 0.1009871000, 0.2307264000, 0.5784990000, 1.5020282000", \ - "0.0525431000, 0.0593908000, 0.0741068000, 0.1126656000, 0.2328990000, 0.5806248000, 1.4941075000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.1885577000, 0.1967326000, 0.2137617000, 0.2465743000, 0.3096562000, 0.4472914000, 0.7900766000", \ - "0.1921723000, 0.2002397000, 0.2173924000, 0.2502309000, 0.3133294000, 0.4509870000, 0.7938080000", \ - "0.2029727000, 0.2111408000, 0.2281235000, 0.2605030000, 0.3241254000, 0.4616264000, 0.8043228000", \ - "0.2288259000, 0.2369837000, 0.2537757000, 0.2864606000, 0.3498702000, 0.4875050000, 0.8303263000", \ - "0.2891506000, 0.2972977000, 0.3141020000, 0.3466948000, 0.4101577000, 0.5478141000, 0.8909675000", \ - "0.4071243000, 0.4161204000, 0.4348515000, 0.4704009000, 0.5367395000, 0.6759895000, 1.0189605000", \ - "0.6096482000, 0.6206529000, 0.6430004000, 0.6841634000, 0.7580208000, 0.9036409000, 1.2482992000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0606585000, 0.0667302000, 0.0812067000, 0.1170958000, 0.2100632000, 0.4544044000, 1.0969076000", \ - "0.0654409000, 0.0714631000, 0.0859661000, 0.1219468000, 0.2154804000, 0.4592337000, 1.1014820000", \ - "0.0768177000, 0.0828247000, 0.0972699000, 0.1333200000, 0.2266215000, 0.4710050000, 1.1131603000", \ - "0.1000566000, 0.1061861000, 0.1209522000, 0.1571110000, 0.2505223000, 0.4949947000, 1.1370738000", \ - "0.1324595000, 0.1391738000, 0.1542603000, 0.1905405000, 0.2840864000, 0.5291527000, 1.1725215000", \ - "0.1693712000, 0.1774268000, 0.1942095000, 0.2313390000, 0.3249926000, 0.5693109000, 1.2141221000", \ - "0.1898178000, 0.2009420000, 0.2229220000, 0.2639137000, 0.3565405000, 0.6012132000, 1.2422180000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0351224000, 0.0404105000, 0.0529540000, 0.0782356000, 0.1402009000, 0.3012660000, 0.7500792000", \ - "0.0354755000, 0.0403485000, 0.0523148000, 0.0782772000, 0.1402669000, 0.3012869000, 0.7490112000", \ - "0.0354876000, 0.0404145000, 0.0529525000, 0.0795539000, 0.1396803000, 0.3014555000, 0.7518672000", \ - "0.0351640000, 0.0404601000, 0.0531878000, 0.0783763000, 0.1400421000, 0.3012069000, 0.7526780000", \ - "0.0352467000, 0.0407376000, 0.0531529000, 0.0792173000, 0.1394190000, 0.3018020000, 0.7518697000", \ - "0.0424553000, 0.0476687000, 0.0606733000, 0.0858415000, 0.1450907000, 0.3037533000, 0.7481801000", \ - "0.0564137000, 0.0631384000, 0.0754753000, 0.1032245000, 0.1624607000, 0.3150284000, 0.7526586000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0213342000, 0.0282605000, 0.0467499000, 0.0967831000, 0.2293849000, 0.5790901000, 1.4998035000", \ - "0.0212964000, 0.0282208000, 0.0467237000, 0.0966054000, 0.2296960000, 0.5797392000, 1.5007627000", \ - "0.0212893000, 0.0282452000, 0.0466744000, 0.0967729000, 0.2300473000, 0.5799007000, 1.4995626000", \ - "0.0225485000, 0.0291812000, 0.0472478000, 0.0966989000, 0.2301138000, 0.5799035000, 1.4988603000", \ - "0.0262901000, 0.0325093000, 0.0495758000, 0.0978608000, 0.2292492000, 0.5801697000, 1.5010683000", \ - "0.0350460000, 0.0405292000, 0.0560401000, 0.1004511000, 0.2306336000, 0.5786151000, 1.4964698000", \ - "0.0498138000, 0.0562451000, 0.0709953000, 0.1105112000, 0.2325122000, 0.5810069000, 1.4965966000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_inputisolatch_1") { - leakage_power () { - value : 0.0040774000; - when : "D&SLEEP_B&Q"; - } - leakage_power () { - value : 0.0101694000; - when : "!D&!SLEEP_B&!Q"; - } - leakage_power () { - value : 0.0102055000; - when : "!D&SLEEP_B&!Q"; - } - leakage_power () { - value : 0.0032340000; - when : "D&!SLEEP_B&Q"; - } - leakage_power () { - value : 0.0105234000; - when : "D&!SLEEP_B&!Q"; - } - leakage_power () { - value : 0.0034794000; - when : "!D&!SLEEP_B&Q"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__inputisolatch"; - cell_leakage_power : 0.0069481680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - latch ("IQ","IQ_N") { - data_in : "D"; - enable : "SLEEP_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("D") { - capacitance : 0.0016200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028493000, 0.0028727000, 0.0029266000, 0.0029296000, 0.0029366000, 0.0029527000, 0.0029898000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002765200, -0.002766400, -0.002769200, -0.002780000, -0.002804700, -0.002861800, -0.002993500"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016760000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3035137000, 0.4359518000, 0.6096986000", \ - "0.2186829000, 0.3621074000, 0.5834616000", \ - "0.1511374000, 0.2884583000, 0.5122539000"); - } - related_pin : "SLEEP_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0007793000, 0.1210104000, 0.2202943000", \ - "-0.170721400, -0.060255900, 0.0329245000", \ - "-0.342026700, -0.247430300, -0.165236300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.352606100, -0.576401700", \ - "-0.097495400, -0.248244100, -0.462274100", \ - "-0.011639300, -0.151401700, -0.360548800"); - } - related_pin : "SLEEP_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0129863000, -0.106024100, -0.208970000", \ - "0.1857077000, 0.0752422000, -0.024041700", \ - "0.3618958000, 0.2648581000, 0.1765605000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0147106000, 0.0134772000, 0.0107830000, 0.0031675000, -0.019285400, -0.080787300, -0.243000200", \ - "0.0145810000, 0.0133411000, 0.0106603000, 0.0030493000, -0.019404400, -0.080905800, -0.243116500", \ - "0.0145655000, 0.0133278000, 0.0106309000, 0.0030470000, -0.019424700, -0.080919400, -0.243134400", \ - "0.0142508000, 0.0130287000, 0.0102973000, 0.0027264000, -0.019741400, -0.081254600, -0.243458100", \ - "0.0139388000, 0.0126697000, 0.0099841000, 0.0023649000, -0.020099000, -0.081597200, -0.243808100", \ - "0.0140021000, 0.0127493000, 0.0099905000, 0.0023828000, -0.020107700, -0.081598300, -0.243798900", \ - "0.0176330000, 0.0162845000, 0.0128472000, 0.0039812000, -0.019264800, -0.081062500, -0.243243200"); - } - related_pin : "SLEEP_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0202684000, 0.0217043000, 0.0254182000, 0.0346631000, 0.0584661000, 0.1197658000, 0.2807771000", \ - "0.0202721000, 0.0216895000, 0.0253930000, 0.0346920000, 0.0582642000, 0.1205940000, 0.2816093000", \ - "0.0201363000, 0.0215682000, 0.0252718000, 0.0345234000, 0.0581217000, 0.1198938000, 0.2816587000", \ - "0.0198250000, 0.0212436000, 0.0249466000, 0.0342440000, 0.0578174000, 0.1201490000, 0.2800504000", \ - "0.0196035000, 0.0210277000, 0.0247687000, 0.0340021000, 0.0576073000, 0.1199730000, 0.2802009000", \ - "0.0199798000, 0.0213192000, 0.0247657000, 0.0340634000, 0.0575678000, 0.1190489000, 0.2800021000", \ - "0.0208031000, 0.0221717000, 0.0257427000, 0.0349544000, 0.0584721000, 0.1204678000, 0.2814100000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0159321000, 0.0146882000, 0.0119619000, 0.0043584000, -0.018106900, -0.079590600, -0.241711700", \ - "0.0158975000, 0.0146408000, 0.0119216000, 0.0042971000, -0.018181800, -0.079662700, -0.241852200", \ - "0.0158656000, 0.0146065000, 0.0118964000, 0.0042811000, -0.018207300, -0.079686800, -0.241847500", \ - "0.0157642000, 0.0144760000, 0.0117986000, 0.0041542000, -0.018306300, -0.079790900, -0.241987000", \ - "0.0156618000, 0.0143868000, 0.0116969000, 0.0040353000, -0.018434000, -0.079902400, -0.242086900", \ - "0.0158490000, 0.0145718000, 0.0118400000, 0.0041144000, -0.018392200, -0.079851800, -0.242007400", \ - "0.0201855000, 0.0187408000, 0.0151271000, 0.0059922000, -0.017655300, -0.079090200, -0.241247300"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0204856000, 0.0218859000, 0.0256177000, 0.0349311000, 0.0586199000, 0.1206285000, 0.2817391000", \ - "0.0204453000, 0.0219002000, 0.0256190000, 0.0348988000, 0.0585633000, 0.1199212000, 0.2806091000", \ - "0.0204246000, 0.0218414000, 0.0255582000, 0.0348346000, 0.0584994000, 0.1205247000, 0.2822090000", \ - "0.0201753000, 0.0215885000, 0.0253006000, 0.0345631000, 0.0582227000, 0.1202624000, 0.2802180000", \ - "0.0201368000, 0.0215530000, 0.0252112000, 0.0344095000, 0.0580751000, 0.1202032000, 0.2813047000", \ - "0.0208043000, 0.0221236000, 0.0255479000, 0.0344466000, 0.0580953000, 0.1194351000, 0.2801452000", \ - "0.0218830000, 0.0231572000, 0.0265645000, 0.0355827000, 0.0590200000, 0.1206933000, 0.2802624000"); - } - } - max_capacitance : 0.1620580000; - max_transition : 1.5029160000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2577084000, 0.2703502000, 0.2962813000, 0.3423517000, 0.4169054000, 0.5614972000, 0.9000666000", \ - "0.2628777000, 0.2755144000, 0.3014101000, 0.3475066000, 0.4221762000, 0.5666295000, 0.9059217000", \ - "0.2740280000, 0.2864905000, 0.3125004000, 0.3586806000, 0.4332982000, 0.5777311000, 0.9170401000", \ - "0.2964534000, 0.3090303000, 0.3349560000, 0.3810279000, 0.4554760000, 0.6001896000, 0.9390566000", \ - "0.3459024000, 0.3584332000, 0.3843204000, 0.4303518000, 0.5048433000, 0.6495475000, 0.9885774000", \ - "0.4508345000, 0.4641330000, 0.4912919000, 0.5389302000, 0.6143704000, 0.7596881000, 1.0991137000", \ - "0.6331023000, 0.6485080000, 0.6795961000, 0.7338155000, 0.8168379000, 0.9682447000, 1.3096556000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1207077000, 0.1303909000, 0.1517406000, 0.1966027000, 0.2942917000, 0.5404242000, 1.1855530000", \ - "0.1250332000, 0.1348051000, 0.1561123000, 0.2009680000, 0.2988429000, 0.5459224000, 1.1877502000", \ - "0.1342096000, 0.1439073000, 0.1652364000, 0.2100750000, 0.3078544000, 0.5545400000, 1.1966611000", \ - "0.1550733000, 0.1647538000, 0.1860624000, 0.2308453000, 0.3286207000, 0.5754265000, 1.2175879000", \ - "0.1984569000, 0.2086653000, 0.2304127000, 0.2754632000, 0.3731407000, 0.6194560000, 1.2648262000", \ - "0.2663846000, 0.2781179000, 0.3021663000, 0.3497278000, 0.4487641000, 0.6955928000, 1.3380851000", \ - "0.3493174000, 0.3646704000, 0.3946459000, 0.4485377000, 0.5507815000, 0.7975847000, 1.4394427000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0482014000, 0.0567451000, 0.0733406000, 0.0999944000, 0.1558765000, 0.3068695000, 0.7376660000", \ - "0.0479475000, 0.0568918000, 0.0735237000, 0.1003071000, 0.1556116000, 0.3069774000, 0.7442696000", \ - "0.0479318000, 0.0564657000, 0.0735486000, 0.0999161000, 0.1556761000, 0.3068850000, 0.7445896000", \ - "0.0481562000, 0.0569569000, 0.0734787000, 0.1005567000, 0.1554858000, 0.3064584000, 0.7394139000", \ - "0.0478152000, 0.0565909000, 0.0734653000, 0.1004346000, 0.1554816000, 0.3070260000, 0.7382173000", \ - "0.0525802000, 0.0613800000, 0.0782296000, 0.1041630000, 0.1577878000, 0.3082900000, 0.7451783000", \ - "0.0633622000, 0.0737445000, 0.0931326000, 0.1200992000, 0.1732325000, 0.3179312000, 0.7409218000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0323402000, 0.0407252000, 0.0608580000, 0.1077608000, 0.2331260000, 0.5817499000, 1.4971172000", \ - "0.0320488000, 0.0407207000, 0.0608997000, 0.1078279000, 0.2330518000, 0.5809632000, 1.4977078000", \ - "0.0321364000, 0.0406507000, 0.0608964000, 0.1078144000, 0.2328359000, 0.5809660000, 1.4997655000", \ - "0.0321587000, 0.0406489000, 0.0608940000, 0.1078605000, 0.2328007000, 0.5807437000, 1.4997864000", \ - "0.0344193000, 0.0426684000, 0.0624972000, 0.1087678000, 0.2333274000, 0.5817992000, 1.4986641000", \ - "0.0409442000, 0.0500016000, 0.0692889000, 0.1139162000, 0.2352009000, 0.5802454000, 1.4978762000", \ - "0.0555899000, 0.0661191000, 0.0861031000, 0.1268416000, 0.2408908000, 0.5814942000, 1.4963025000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2685465000, 0.2811388000, 0.3072152000, 0.3531043000, 0.4275866000, 0.5720099000, 0.9113212000", \ - "0.2732197000, 0.2858480000, 0.3118938000, 0.3578943000, 0.4325872000, 0.5768596000, 0.9157622000", \ - "0.2838765000, 0.2965647000, 0.3225908000, 0.3685361000, 0.4431809000, 0.5874913000, 0.9267442000", \ - "0.3074713000, 0.3200952000, 0.3461154000, 0.3920811000, 0.4666857000, 0.6110557000, 0.9507586000", \ - "0.3454945000, 0.3581065000, 0.3841294000, 0.4301227000, 0.5046609000, 0.6490913000, 0.9880110000", \ - "0.3974850000, 0.4100978000, 0.4361454000, 0.4821465000, 0.5567237000, 0.7011320000, 1.0403968000", \ - "0.4601237000, 0.4727369000, 0.4987146000, 0.5445868000, 0.6193044000, 0.7637651000, 1.1028637000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.2205510000, 0.2302959000, 0.2515777000, 0.2964065000, 0.3942687000, 0.6416866000, 1.2833293000", \ - "0.2252874000, 0.2350597000, 0.2563166000, 0.3011514000, 0.3989800000, 0.6451671000, 1.2875864000", \ - "0.2365271000, 0.2462986000, 0.2675561000, 0.3123894000, 0.4102806000, 0.6577291000, 1.2978697000", \ - "0.2600971000, 0.2698690000, 0.2911256000, 0.3359599000, 0.4337867000, 0.6799645000, 1.3261570000", \ - "0.2975514000, 0.3073181000, 0.3286123000, 0.3734678000, 0.4716340000, 0.7176100000, 1.3606809000", \ - "0.3461142000, 0.3558369000, 0.3771347000, 0.4219874000, 0.5199605000, 0.7673720000, 1.4088454000", \ - "0.3984779000, 0.4081140000, 0.4294279000, 0.4742676000, 0.5722089000, 0.8189718000, 1.4590749000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0477086000, 0.0563225000, 0.0732186000, 0.0993418000, 0.1551248000, 0.3063161000, 0.7394141000", \ - "0.0476230000, 0.0563485000, 0.0731586000, 0.0996830000, 0.1551597000, 0.3066953000, 0.7392866000", \ - "0.0476028000, 0.0562551000, 0.0731141000, 0.0997120000, 0.1554079000, 0.3063462000, 0.7364250000", \ - "0.0475127000, 0.0563117000, 0.0731780000, 0.0995029000, 0.1551014000, 0.3064138000, 0.7405013000", \ - "0.0476434000, 0.0563132000, 0.0732089000, 0.0996560000, 0.1549519000, 0.3066892000, 0.7373323000", \ - "0.0479049000, 0.0564456000, 0.0733987000, 0.0998037000, 0.1545815000, 0.3067616000, 0.7415098000", \ - "0.0479841000, 0.0565106000, 0.0734594000, 0.0994881000, 0.1555894000, 0.3068217000, 0.7338340000"); - } - related_pin : "SLEEP_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0321794000, 0.0406142000, 0.0608073000, 0.1080131000, 0.2332823000, 0.5817820000, 1.5005993000", \ - "0.0320864000, 0.0406259000, 0.0608572000, 0.1078541000, 0.2333876000, 0.5823349000, 1.5029161000", \ - "0.0320857000, 0.0406262000, 0.0608574000, 0.1078490000, 0.2333056000, 0.5815025000, 1.5007124000", \ - "0.0320991000, 0.0406276000, 0.0608597000, 0.1078991000, 0.2333846000, 0.5823622000, 1.5012948000", \ - "0.0322787000, 0.0406463000, 0.0608217000, 0.1081928000, 0.2332599000, 0.5816413000, 1.4986566000", \ - "0.0323004000, 0.0407424000, 0.0608416000, 0.1079176000, 0.2326694000, 0.5819378000, 1.4954239000", \ - "0.0323212000, 0.0407590000, 0.0609046000, 0.1079535000, 0.2329614000, 0.5802995000, 1.4936823000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SLEEP_B") { - capacitance : 0.0016520000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0015730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163493000, 0.0162352000, 0.0159720000, 0.0160438000, 0.0162095000, 0.0165915000, 0.0174718000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092671000, 0.0091843000, 0.0089935000, 0.0090208000, 0.0090838000, 0.0092288000, 0.0095632000"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017310000; - timing () { - related_output_pin : "Q"; - related_pin : "SLEEP_B"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3114925000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrc_1") { - leakage_power () { - value : 0.0005469000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0039870000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0026465000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0015386000; - when : "A&!SLEEP"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__isobufsrc"; - cell_leakage_power : 0.0021797410; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084048000, 0.0083113000, 0.0080958000, 0.0081437000, 0.0082541000, 0.0085086000, 0.0090953000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021945000, 0.0021390000, 0.0020109000, 0.0020536000, 0.0021519000, 0.0023787000, 0.0029014000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015460000; - } - pin ("SLEEP") { - capacitance : 0.0023670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044630000, 0.0044628000, 0.0044622000, 0.0044611000, 0.0044586000, 0.0044528000, 0.0044395000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004251300, -0.004299700, -0.004411300, -0.004412800, -0.004416300, -0.004424300, -0.004442800"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024610000; - } - pin ("X") { - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0019959000, 0.0011170000, -0.000964600, -0.006432700, -0.020072500, -0.052620600, -0.129005000", \ - "0.0019420000, 0.0010652000, -0.001015900, -0.006480800, -0.020112100, -0.052657700, -0.129129300", \ - "0.0019951000, 0.0011313000, -0.000983700, -0.006429700, -0.020051800, -0.052584200, -0.129022700", \ - "0.0017984000, 0.0009013000, -0.001231800, -0.006668500, -0.020270200, -0.052736300, -0.129201300", \ - "0.0015340000, 0.0005998000, -0.001549700, -0.006885200, -0.020452900, -0.052901700, -0.129325000", \ - "0.0020690000, 0.0013346000, -0.001238400, -0.007006800, -0.020474000, -0.052843600, -0.129192800", \ - "0.0024784000, 0.0013661000, -0.001154700, -0.006988800, -0.020591500, -0.053028500, -0.128991900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0062081000, 0.0073988000, 0.0100980000, 0.0162584000, 0.0303019000, 0.0626561000, 0.1378758000", \ - "0.0061980000, 0.0073807000, 0.0100781000, 0.0161569000, 0.0302823000, 0.0626414000, 0.1386791000", \ - "0.0061758000, 0.0073419000, 0.0100109000, 0.0160928000, 0.0300649000, 0.0623920000, 0.1389796000", \ - "0.0058988000, 0.0069830000, 0.0096201000, 0.0157711000, 0.0298534000, 0.0621237000, 0.1376398000", \ - "0.0057037000, 0.0068282000, 0.0094304000, 0.0153823000, 0.0294037000, 0.0622404000, 0.1382294000", \ - "0.0057327000, 0.0068651000, 0.0094263000, 0.0152857000, 0.0291681000, 0.0616371000, 0.1372207000", \ - "0.0060595000, 0.0071433000, 0.0097275000, 0.0156200000, 0.0293949000, 0.0622398000, 0.1372300000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0043467000, 0.0032616000, 0.0007570000, -0.005155400, -0.019060100, -0.051674600, -0.128102900", \ - "0.0042298000, 0.0031698000, 0.0006738000, -0.005222400, -0.019080500, -0.051711300, -0.128122600", \ - "0.0041597000, 0.0031213000, 0.0006207000, -0.005225500, -0.019070700, -0.051654000, -0.128072100", \ - "0.0040279000, 0.0029579000, 0.0004872000, -0.005365000, -0.019160400, -0.051691600, -0.128092700", \ - "0.0041591000, 0.0030989000, 0.0006581000, -0.005295200, -0.019209700, -0.051750000, -0.128136900", \ - "0.0048380000, 0.0037489000, 0.0009825000, -0.005040200, -0.019010900, -0.051578800, -0.128010300", \ - "0.0065513000, 0.0053689000, 0.0026485000, -0.003573200, -0.017716500, -0.050744800, -0.127681400"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0066008000, 0.0077505000, 0.0103407000, 0.0164114000, 0.0301479000, 0.0624061000, 0.1388924000", \ - "0.0064208000, 0.0075552000, 0.0101613000, 0.0161884000, 0.0301438000, 0.0623883000, 0.1378779000", \ - "0.0063009000, 0.0074306000, 0.0100108000, 0.0160060000, 0.0299740000, 0.0623264000, 0.1388762000", \ - "0.0062060000, 0.0073141000, 0.0098810000, 0.0158368000, 0.0297455000, 0.0626333000, 0.1384202000", \ - "0.0061486000, 0.0072566000, 0.0098213000, 0.0157594000, 0.0297279000, 0.0623760000, 0.1382774000", \ - "0.0059391000, 0.0070962000, 0.0098080000, 0.0157697000, 0.0297043000, 0.0622016000, 0.1375295000", \ - "0.0071455000, 0.0081129000, 0.0104538000, 0.0161583000, 0.0299922000, 0.0623359000, 0.1380559000"); - } - } - max_capacitance : 0.0824070000; - max_transition : 1.4969190000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0964098000, 0.1010860000, 0.1102523000, 0.1273195000, 0.1600110000, 0.2280251000, 0.3827862000", \ - "0.1012241000, 0.1058767000, 0.1152085000, 0.1322784000, 0.1650034000, 0.2330573000, 0.3878352000", \ - "0.1142060000, 0.1188111000, 0.1279525000, 0.1451122000, 0.1778948000, 0.2459654000, 0.4008484000", \ - "0.1460100000, 0.1506360000, 0.1597965000, 0.1770128000, 0.2097790000, 0.2780579000, 0.4326710000", \ - "0.2146767000, 0.2196822000, 0.2294603000, 0.2469999000, 0.2804278000, 0.3492035000, 0.5036980000", \ - "0.3266986000, 0.3331350000, 0.3453720000, 0.3666815000, 0.4035157000, 0.4744856000, 0.6297366000", \ - "0.5031695000, 0.5116762000, 0.5271391000, 0.5547521000, 0.5997640000, 0.6754318000, 0.8304952000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0739826000, 0.0835647000, 0.1051338000, 0.1539338000, 0.2665917000, 0.5243608000, 1.1219606000", \ - "0.0788807000, 0.0883915000, 0.1099354000, 0.1587790000, 0.2706097000, 0.5276034000, 1.1328408000", \ - "0.0899662000, 0.0993038000, 0.1205752000, 0.1688996000, 0.2799708000, 0.5374332000, 1.1435738000", \ - "0.1110085000, 0.1198304000, 0.1409138000, 0.1895600000, 0.3036836000, 0.5581809000, 1.1587908000", \ - "0.1402031000, 0.1492857000, 0.1701274000, 0.2181786000, 0.3293248000, 0.5890536000, 1.1930470000", \ - "0.1748854000, 0.1844042000, 0.2052351000, 0.2524772000, 0.3625855000, 0.6200887000, 1.2236121000", \ - "0.1987370000, 0.2104141000, 0.2338083000, 0.2808738000, 0.3899273000, 0.6477113000, 1.2476300000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0228015000, 0.0257814000, 0.0330566000, 0.0485313000, 0.0830718000, 0.1671984000, 0.3719465000", \ - "0.0225309000, 0.0257804000, 0.0331338000, 0.0485782000, 0.0834598000, 0.1667683000, 0.3712204000", \ - "0.0225978000, 0.0258449000, 0.0330889000, 0.0485857000, 0.0833986000, 0.1671392000, 0.3725490000", \ - "0.0226441000, 0.0262253000, 0.0330380000, 0.0487171000, 0.0832926000, 0.1672811000, 0.3748068000", \ - "0.0269756000, 0.0299821000, 0.0365149000, 0.0514093000, 0.0847900000, 0.1677483000, 0.3732379000", \ - "0.0384616000, 0.0416982000, 0.0488214000, 0.0624021000, 0.0944999000, 0.1725085000, 0.3726053000", \ - "0.0557503000, 0.0608906000, 0.0693901000, 0.0842106000, 0.1141633000, 0.1857527000, 0.3789422000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0439679000, 0.0559289000, 0.0835110000, 0.1485700000, 0.3012280000, 0.6534101000, 1.4775490000", \ - "0.0439710000, 0.0557057000, 0.0835164000, 0.1481422000, 0.3014541000, 0.6529548000, 1.4901750000", \ - "0.0440178000, 0.0559424000, 0.0836399000, 0.1483531000, 0.2986190000, 0.6515350000, 1.4881395000", \ - "0.0445554000, 0.0562340000, 0.0836712000, 0.1485765000, 0.3010883000, 0.6526127000, 1.4787215000", \ - "0.0463223000, 0.0575298000, 0.0845476000, 0.1484604000, 0.2992479000, 0.6551769000, 1.4857059000", \ - "0.0527390000, 0.0625363000, 0.0872049000, 0.1496528000, 0.3006978000, 0.6504319000, 1.4771152000", \ - "0.0674572000, 0.0768115000, 0.0985232000, 0.1542040000, 0.3015296000, 0.6537398000, 1.4738359000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0183489000, 0.0207866000, 0.0262815000, 0.0385245000, 0.0660583000, 0.1295483000, 0.2774052000", \ - "0.0231083000, 0.0255211000, 0.0309801000, 0.0431542000, 0.0707510000, 0.1342357000, 0.2820796000", \ - "0.0331671000, 0.0362230000, 0.0421659000, 0.0543237000, 0.0817818000, 0.1452322000, 0.2932948000", \ - "0.0461717000, 0.0509465000, 0.0604657000, 0.0780251000, 0.1083926000, 0.1717014000, 0.3195342000", \ - "0.0604451000, 0.0671588000, 0.0821356000, 0.1097163000, 0.1567125000, 0.2325757000, 0.3795523000", \ - "0.0680601000, 0.0791785000, 0.1018504000, 0.1447535000, 0.2186241000, 0.3350328000, 0.5197788000", \ - "0.0465838000, 0.0639966000, 0.0993808000, 0.1664107000, 0.2814258000, 0.4674255000, 0.7530149000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0585989000, 0.0678814000, 0.0885699000, 0.1367331000, 0.2464649000, 0.5022917000, 1.1080010000", \ - "0.0634510000, 0.0725376000, 0.0935227000, 0.1412510000, 0.2535409000, 0.5082342000, 1.1080564000", \ - "0.0754452000, 0.0844244000, 0.1052602000, 0.1528361000, 0.2633951000, 0.5203508000, 1.1302007000", \ - "0.1004400000, 0.1100178000, 0.1308328000, 0.1785383000, 0.2889456000, 0.5488303000, 1.1496514000", \ - "0.1424253000, 0.1557518000, 0.1835740000, 0.2374200000, 0.3482676000, 0.6076660000, 1.2075241000", \ - "0.2079334000, 0.2288835000, 0.2704523000, 0.3456357000, 0.4844529000, 0.7447173000, 1.3459400000", \ - "0.3192730000, 0.3507592000, 0.4131745000, 0.5271756000, 0.7205905000, 1.0537584000, 1.6667543000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0134957000, 0.0163520000, 0.0229247000, 0.0380548000, 0.0737932000, 0.1573593000, 0.3520182000", \ - "0.0135807000, 0.0163069000, 0.0226884000, 0.0379357000, 0.0736306000, 0.1572279000, 0.3521806000", \ - "0.0190673000, 0.0212445000, 0.0261168000, 0.0392940000, 0.0735478000, 0.1571358000, 0.3520781000", \ - "0.0311575000, 0.0339252000, 0.0410443000, 0.0529005000, 0.0800221000, 0.1572172000, 0.3524833000", \ - "0.0504336000, 0.0558982000, 0.0669238000, 0.0843911000, 0.1166909000, 0.1772618000, 0.3544365000", \ - "0.0855817000, 0.0940684000, 0.1103094000, 0.1390548000, 0.1865902000, 0.2669858000, 0.4050399000", \ - "0.1489061000, 0.1623999000, 0.1897607000, 0.2345995000, 0.3089887000, 0.4266958000, 0.6085345000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0439501000, 0.0558995000, 0.0836571000, 0.1488991000, 0.2984583000, 0.6524895000, 1.4865060000", \ - "0.0440366000, 0.0559742000, 0.0835085000, 0.1479901000, 0.2999269000, 0.6506792000, 1.4751167000", \ - "0.0442104000, 0.0559832000, 0.0837208000, 0.1479644000, 0.2996045000, 0.6523395000, 1.4889139000", \ - "0.0491786000, 0.0598096000, 0.0853109000, 0.1483279000, 0.2989474000, 0.6557169000, 1.4807034000", \ - "0.0696060000, 0.0806421000, 0.1053322000, 0.1591477000, 0.3010932000, 0.6547448000, 1.4788468000", \ - "0.1129302000, 0.1258505000, 0.1541389000, 0.2119272000, 0.3378151000, 0.6581760000, 1.4835150000", \ - "0.1903240000, 0.2085342000, 0.2462656000, 0.3197626000, 0.4621437000, 0.7558062000, 1.4969191000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrc_16") { - leakage_power () { - value : 0.0722837000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0069600000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0147678000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0273559000; - when : "A&!SLEEP"; - } - area : 45.043200000; - cell_footprint : "sky130_fd_sc_hd__isobufsrc"; - cell_leakage_power : 0.0303418800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0087530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0749865000, 0.0746861000, 0.0739937000, 0.0743815000, 0.0752757000, 0.0773369000, 0.0820881000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0600982000, 0.0598271000, 0.0592023000, 0.0594977000, 0.0601787000, 0.0617486000, 0.0653675000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092030000; - } - pin ("SLEEP") { - capacitance : 0.0323230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0299990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0316257000, 0.0315764000, 0.0314630000, 0.0316032000, 0.0319267000, 0.0326723000, 0.0343911000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.028057600, -0.028045300, -0.028017000, -0.028027200, -0.028050700, -0.028104900, -0.028229900"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0346470000; - } - pin ("X") { - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016192410, 0.0052438840, 0.0169822300, 0.0549966400, 0.1781057000, 0.5767920000"); - values("0.0695820000, 0.0678177000, 0.0623785000, 0.0439268000, -0.015978000, -0.213266800, -0.857525500", \ - "0.0693421000, 0.0675760000, 0.0620927000, 0.0437789000, -0.016205300, -0.213488300, -0.857751000", \ - "0.0695742000, 0.0678491000, 0.0622331000, 0.0440679000, -0.015961300, -0.213291200, -0.857427900", \ - "0.0679270000, 0.0661857000, 0.0605137000, 0.0424321000, -0.017554400, -0.214564500, -0.857893500", \ - "0.0663085000, 0.0645962000, 0.0588246000, 0.0406173000, -0.019150700, -0.216271600, -0.860019400", \ - "0.0635521000, 0.0618183000, 0.0561624000, 0.0380224000, -0.021532000, -0.217701100, -0.860697400", \ - "0.0665169000, 0.0647031000, 0.0588148000, 0.0401277000, -0.020845100, -0.217338200, -0.859767300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016192410, 0.0052438840, 0.0169822300, 0.0549966400, 0.1781057000, 0.5767920000"); - values("0.0916799000, 0.0935915000, 0.0997514000, 0.1191619000, 0.1807177000, 0.3794335000, 1.0157415000", \ - "0.0916260000, 0.0935210000, 0.0996524000, 0.1190902000, 0.1807589000, 0.3793891000, 1.0154350000", \ - "0.0915520000, 0.0934401000, 0.0995188000, 0.1189664000, 0.1805611000, 0.3776501000, 1.0158186000", \ - "0.0899524000, 0.0918100000, 0.0978539000, 0.1174444000, 0.1794858000, 0.3766360000, 1.0141100000", \ - "0.0883930000, 0.0902499000, 0.0962665000, 0.1155396000, 0.1776884000, 0.3767272000, 1.0147835000", \ - "0.0873287000, 0.0891523000, 0.0951839000, 0.1146003000, 0.1763520000, 0.3745035000, 1.0126199000", \ - "0.0901867000, 0.0920266000, 0.0979351000, 0.1172623000, 0.1791467000, 0.3772340000, 1.0141209000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016192410, 0.0052438840, 0.0169822300, 0.0549966400, 0.1781057000, 0.5767920000"); - values("0.0065022000, 0.0048572000, -0.000549000, -0.018841500, -0.079696000, -0.278323500, -0.923875700", \ - "0.0047452000, 0.0031324000, -0.002212900, -0.020029000, -0.079672900, -0.277365900, -0.922477000", \ - "0.0016622000, -0.000101100, -0.005331300, -0.022757200, -0.081096200, -0.277207200, -0.921522300", \ - "-0.002969200, -0.004560700, -0.009778100, -0.026705800, -0.084082800, -0.278533900, -0.921498300", \ - "-0.004454400, -0.006130600, -0.011728900, -0.029677900, -0.087568600, -0.281486000, -0.922500200", \ - "0.0017727000, -0.000139900, -0.006321900, -0.025610300, -0.085686100, -0.283982700, -0.924033300", \ - "0.0220554000, 0.0199116000, 0.0131331000, -0.008393500, -0.074297900, -0.277310600, -0.923468300"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016192410, 0.0052438840, 0.0169822300, 0.0549966400, 0.1781057000, 0.5767920000"); - values("0.0924340000, 0.0948064000, 0.1020013000, 0.1238127000, 0.1880153000, 0.3883843000, 1.0248540000", \ - "0.0885415000, 0.0907501000, 0.0976766000, 0.1194475000, 0.1849379000, 0.3851062000, 1.0246468000", \ - "0.0857895000, 0.0877355000, 0.0942343000, 0.1149645000, 0.1801199000, 0.3836683000, 1.0232117000", \ - "0.0846450000, 0.0865056000, 0.0924711000, 0.1122887000, 0.1758497000, 0.3777191000, 1.0205847000", \ - "0.0857395000, 0.0875043000, 0.0932753000, 0.1121341000, 0.1732608000, 0.3735878000, 1.0159804000", \ - "0.0923697000, 0.0940190000, 0.0994308000, 0.1176378000, 0.1770442000, 0.3728858000, 1.0130118000", \ - "0.1116951000, 0.1133223000, 0.1183656000, 0.1350728000, 0.1916843000, 0.3833666000, 1.0142066000"); - } - } - max_capacitance : 0.5767920000; - max_transition : 1.5038860000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.1446968000, 0.1456491000, 0.1487949000, 0.1579676000, 0.1842385000, 0.2578618000, 0.4808803000", \ - "0.1498669000, 0.1508225000, 0.1539705000, 0.1631562000, 0.1894112000, 0.2630478000, 0.4860430000", \ - "0.1630255000, 0.1639888000, 0.1670451000, 0.1762732000, 0.2024337000, 0.2761575000, 0.4984852000", \ - "0.1947871000, 0.1957542000, 0.1988175000, 0.2080565000, 0.2342732000, 0.3081523000, 0.5314315000", \ - "0.2665664000, 0.2676409000, 0.2705539000, 0.2798911000, 0.3061252000, 0.3806320000, 0.6028347000", \ - "0.3977356000, 0.3988063000, 0.4020434000, 0.4122074000, 0.4399510000, 0.5160743000, 0.7400217000", \ - "0.6056527000, 0.6070456000, 0.6113282000, 0.6231924000, 0.6557592000, 0.7359547000, 0.9634167000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.1462669000, 0.1486647000, 0.1561552000, 0.1786613000, 0.2481326000, 0.4661822000, 1.1692326000", \ - "0.1508071000, 0.1531803000, 0.1605811000, 0.1830769000, 0.2524464000, 0.4714415000, 1.1732562000", \ - "0.1615886000, 0.1639367000, 0.1714286000, 0.1938026000, 0.2632079000, 0.4816553000, 1.1823684000", \ - "0.1851604000, 0.1875944000, 0.1948307000, 0.2176153000, 0.2868089000, 0.5044511000, 1.2054255000", \ - "0.2216230000, 0.2239557000, 0.2312250000, 0.2539192000, 0.3238755000, 0.5432886000, 1.2503852000", \ - "0.2651904000, 0.2675884000, 0.2751988000, 0.2983185000, 0.3686089000, 0.5866617000, 1.2877449000", \ - "0.2976239000, 0.3002449000, 0.3084712000, 0.3327583000, 0.4045677000, 0.6232559000, 1.3239980000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0448278000, 0.0459953000, 0.0497975000, 0.0612827000, 0.0985720000, 0.2224086000, 0.6351299000", \ - "0.0448779000, 0.0460378000, 0.0498262000, 0.0612789000, 0.0986205000, 0.2224245000, 0.6350748000", \ - "0.0450261000, 0.0461365000, 0.0497276000, 0.0615330000, 0.0986906000, 0.2221747000, 0.6340379000", \ - "0.0450466000, 0.0461492000, 0.0497559000, 0.0615599000, 0.0986810000, 0.2220353000, 0.6349741000", \ - "0.0457099000, 0.0468905000, 0.0503614000, 0.0620945000, 0.0991271000, 0.2224741000, 0.6360333000", \ - "0.0537073000, 0.0548962000, 0.0585998000, 0.0702448000, 0.1055762000, 0.2259368000, 0.6346416000", \ - "0.0706609000, 0.0719278000, 0.0760205000, 0.0877418000, 0.1222223000, 0.2365023000, 0.6405494000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0727802000, 0.0753309000, 0.0837727000, 0.1117405000, 0.2039368000, 0.5059259000, 1.4811730000", \ - "0.0728560000, 0.0754454000, 0.0838382000, 0.1117411000, 0.2036438000, 0.5059181000, 1.4794840000", \ - "0.0728990000, 0.0754896000, 0.0838838000, 0.1117375000, 0.2037493000, 0.5041603000, 1.4786402000", \ - "0.0729980000, 0.0755982000, 0.0841417000, 0.1117189000, 0.2040676000, 0.5049015000, 1.4765656000", \ - "0.0738957000, 0.0766012000, 0.0848444000, 0.1123915000, 0.2043735000, 0.5054133000, 1.4835470000", \ - "0.0764581000, 0.0789803000, 0.0872638000, 0.1145202000, 0.2051114000, 0.5036686000, 1.4760860000", \ - "0.0834975000, 0.0859637000, 0.0939673000, 0.1204006000, 0.2084918000, 0.5047209000, 1.4746270000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0192414000, 0.0197617000, 0.0213544000, 0.0260653000, 0.0393986000, 0.0801068000, 0.2095880000", \ - "0.0233402000, 0.0238613000, 0.0254824000, 0.0302300000, 0.0437605000, 0.0846733000, 0.2146233000", \ - "0.0305079000, 0.0312403000, 0.0335124000, 0.0396116000, 0.0540811000, 0.0950484000, 0.2247531000", \ - "0.0367529000, 0.0378868000, 0.0413386000, 0.0508240000, 0.0731516000, 0.1194286000, 0.2497349000", \ - "0.0364040000, 0.0381216000, 0.0434559000, 0.0582941000, 0.0936514000, 0.1648537000, 0.3062400000", \ - "0.0143228000, 0.0170337000, 0.0253278000, 0.0484718000, 0.1038399000, 0.2171107000, 0.4236159000", \ - "-0.066967200, -0.062734300, -0.049775800, -0.013577200, 0.0728021000, 0.2502205000, 0.5754723000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0636056000, 0.0664750000, 0.0744361000, 0.0989850000, 0.1704120000, 0.3903290000, 1.0891683000", \ - "0.0644826000, 0.0669135000, 0.0747749000, 0.0989886000, 0.1717418000, 0.3924009000, 1.0930966000", \ - "0.0739286000, 0.0760725000, 0.0834316000, 0.1062800000, 0.1786221000, 0.4027367000, 1.1037410000", \ - "0.1029064000, 0.1049294000, 0.1113810000, 0.1328363000, 0.2028936000, 0.4242057000, 1.1290989000", \ - "0.1542739000, 0.1575780000, 0.1677506000, 0.1966528000, 0.2684448000, 0.4870367000, 1.1918990000", \ - "0.2399972000, 0.2448534000, 0.2594538000, 0.3018649000, 0.4078657000, 0.6414154000, 1.3453400000", \ - "0.3988961000, 0.4054133000, 0.4257771000, 0.4847733000, 0.6381816000, 0.9812603000, 1.6992620000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0102197000, 0.0107166000, 0.0123837000, 0.0178461000, 0.0361651000, 0.0959033000, 0.2895865000", \ - "0.0104956000, 0.0109472000, 0.0125540000, 0.0180158000, 0.0362329000, 0.0957871000, 0.2896110000", \ - "0.0154872000, 0.0159654000, 0.0176030000, 0.0220917000, 0.0376714000, 0.0959060000, 0.2897643000", \ - "0.0248166000, 0.0254783000, 0.0277736000, 0.0339632000, 0.0513107000, 0.1007475000, 0.2891562000", \ - "0.0430049000, 0.0442395000, 0.0474770000, 0.0566162000, 0.0796595000, 0.1335142000, 0.2969439000", \ - "0.0776010000, 0.0792910000, 0.0847423000, 0.0981781000, 0.1316419000, 0.2055078000, 0.3674177000", \ - "0.1427702000, 0.1455222000, 0.1522143000, 0.1740569000, 0.2269341000, 0.3345183000, 0.5441344000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016192400, 0.0052438800, 0.0169822000, 0.0549966000, 0.1781060000, 0.5767920000"); - values("0.0686153000, 0.0712955000, 0.0804490000, 0.1092822000, 0.2029655000, 0.5061426000, 1.4755812000", \ - "0.0681910000, 0.0709948000, 0.0800989000, 0.1091745000, 0.2032386000, 0.5046243000, 1.4772117000", \ - "0.0672699000, 0.0699829000, 0.0792003000, 0.1086239000, 0.2026020000, 0.5057115000, 1.4752589000", \ - "0.0737691000, 0.0759648000, 0.0833026000, 0.1091716000, 0.2024075000, 0.5048877000, 1.4778613000", \ - "0.1012711000, 0.1044448000, 0.1145300000, 0.1368052000, 0.2116914000, 0.5056101000, 1.4784628000", \ - "0.1365480000, 0.1408653000, 0.1527414000, 0.1883787000, 0.2803610000, 0.5241289000, 1.4767287000", \ - "0.2028318000, 0.2080519000, 0.2242502000, 0.2723957000, 0.3985406000, 0.6817770000, 1.5038859000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrc_2") { - leakage_power () { - value : 0.0004672000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0039075000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0045917000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0038997000; - when : "A&!SLEEP"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__isobufsrc"; - cell_leakage_power : 0.0032165400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0113286000, 0.0112418000, 0.0110416000, 0.0111014000, 0.0112392000, 0.0115568000, 0.0122889000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0036756000, 0.0036283000, 0.0035192000, 0.0035750000, 0.0037036000, 0.0040001000, 0.0046834000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014970000; - } - pin ("SLEEP") { - capacitance : 0.0043250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082382000, 0.0082360000, 0.0082309000, 0.0082275000, 0.0082195000, 0.0082011000, 0.0081586000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007666700, -0.007719800, -0.007842100, -0.007845700, -0.007853900, -0.007873100, -0.007917100"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045380000; - } - pin ("X") { - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0019773000, 0.0008894000, -0.001835900, -0.008938900, -0.029202900, -0.083576500, -0.224554800", \ - "0.0019623000, 0.0008846000, -0.001777100, -0.008930100, -0.029187400, -0.083564600, -0.224571000", \ - "0.0020112000, 0.0008920000, -0.001767100, -0.008899500, -0.029142100, -0.083537900, -0.224508400", \ - "0.0017734000, 0.0006720000, -0.002021200, -0.009227300, -0.029497000, -0.083781400, -0.224757200", \ - "0.0015652000, 0.0004042000, -0.002363300, -0.009645800, -0.029881400, -0.084131400, -0.224998300", \ - "0.0023957000, 0.0011162000, -0.002091500, -0.010279400, -0.030470000, -0.084525700, -0.225249200", \ - "0.0041358000, 0.0027719000, -9.86000e-05, -0.008704900, -0.030326700, -0.084775000, -0.225317200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0110047000, 0.0123598000, 0.0158202000, 0.0244993000, 0.0461387000, 0.1015427000, 0.2404454000", \ - "0.0110199000, 0.0123639000, 0.0158282000, 0.0244937000, 0.0461430000, 0.1008110000, 0.2407682000", \ - "0.0110383000, 0.0123733000, 0.0158046000, 0.0244559000, 0.0462560000, 0.1014970000, 0.2406209000", \ - "0.0108948000, 0.0122061000, 0.0155791000, 0.0240453000, 0.0459114000, 0.1005815000, 0.2401687000", \ - "0.0105477000, 0.0118392000, 0.0151950000, 0.0235755000, 0.0452509000, 0.0999360000, 0.2398213000", \ - "0.0108543000, 0.0121172000, 0.0153525000, 0.0235553000, 0.0448561000, 0.0996035000, 0.2393984000", \ - "0.0110891000, 0.0123294000, 0.0155321000, 0.0238938000, 0.0448434000, 0.0999790000, 0.2392051000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0079985000, 0.0067413000, 0.0035105000, -0.004818600, -0.026161600, -0.081013200, -0.222111600", \ - "0.0076934000, 0.0064538000, 0.0032741000, -0.005016300, -0.026298700, -0.081160800, -0.222173900", \ - "0.0074126000, 0.0061968000, 0.0030406000, -0.005207400, -0.026411200, -0.081198900, -0.222252100", \ - "0.0068614000, 0.0056505000, 0.0025710000, -0.005512100, -0.026628800, -0.081363300, -0.222334600", \ - "0.0071687000, 0.0058998000, 0.0027311000, -0.005388100, -0.026913900, -0.081520900, -0.222399200", \ - "0.0082961000, 0.0070587000, 0.0037754000, -0.004638900, -0.026120400, -0.081381400, -0.222407000", \ - "0.0115054000, 0.0100427000, 0.0065630000, -0.002314800, -0.024369600, -0.080051200, -0.221917600"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0125463000, 0.0139197000, 0.0173578000, 0.0258754000, 0.0472672000, 0.1014963000, 0.2410120000", \ - "0.0122337000, 0.0135644000, 0.0169977000, 0.0255709000, 0.0471821000, 0.1014746000, 0.2410179000", \ - "0.0120044000, 0.0133202000, 0.0166693000, 0.0251792000, 0.0466831000, 0.1016121000, 0.2428835000", \ - "0.0118549000, 0.0131609000, 0.0164847000, 0.0249056000, 0.0464890000, 0.1013547000, 0.2406958000", \ - "0.0116996000, 0.0130082000, 0.0163068000, 0.0246357000, 0.0460334000, 0.1006361000, 0.2403290000", \ - "0.0117938000, 0.0130777000, 0.0163125000, 0.0247038000, 0.0460421000, 0.1008531000, 0.2400270000", \ - "0.0128783000, 0.0139969000, 0.0170514000, 0.0250311000, 0.0464620000, 0.1008679000, 0.2415851000"); - } - } - max_capacitance : 0.1428320000; - max_transition : 1.4931760000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1191507000, 0.1230982000, 0.1316109000, 0.1481851000, 0.1787895000, 0.2404221000, 0.3824831000", \ - "0.1241789000, 0.1280997000, 0.1365535000, 0.1529632000, 0.1837590000, 0.2456539000, 0.3876908000", \ - "0.1366735000, 0.1405968000, 0.1490155000, 0.1654451000, 0.1961940000, 0.2579473000, 0.3997786000", \ - "0.1672347000, 0.1711899000, 0.1796397000, 0.1961668000, 0.2271464000, 0.2889988000, 0.4307835000", \ - "0.2383217000, 0.2422754000, 0.2507481000, 0.2674242000, 0.2986436000, 0.3605578000, 0.5020364000", \ - "0.3603219000, 0.3652304000, 0.3761966000, 0.3962687000, 0.4318882000, 0.4976035000, 0.6402731000", \ - "0.5448403000, 0.5513525000, 0.5652900000, 0.5914524000, 0.6362436000, 0.7113335000, 0.8591082000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0850827000, 0.0915806000, 0.1077065000, 0.1477067000, 0.2471145000, 0.4983962000, 1.1352976000", \ - "0.0900440000, 0.0965464000, 0.1126415000, 0.1525025000, 0.2520509000, 0.5025037000, 1.1440479000", \ - "0.1017131000, 0.1082521000, 0.1241953000, 0.1639636000, 0.2639431000, 0.5156037000, 1.1547951000", \ - "0.1279568000, 0.1342575000, 0.1500619000, 0.1891261000, 0.2889944000, 0.5417804000, 1.1783942000", \ - "0.1717177000, 0.1782563000, 0.1941255000, 0.2332152000, 0.3318474000, 0.5829571000, 1.2209209000", \ - "0.2310062000, 0.2382372000, 0.2549623000, 0.2940025000, 0.3913674000, 0.6406796000, 1.2824904000", \ - "0.2973325000, 0.3069641000, 0.3274714000, 0.3695982000, 0.4649781000, 0.7149331000, 1.3520109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0254083000, 0.0276955000, 0.0333064000, 0.0450796000, 0.0720788000, 0.1388267000, 0.3183009000", \ - "0.0254099000, 0.0280855000, 0.0332918000, 0.0453896000, 0.0723231000, 0.1389905000, 0.3192530000", \ - "0.0256039000, 0.0276651000, 0.0330740000, 0.0456818000, 0.0720294000, 0.1390372000, 0.3184676000", \ - "0.0254888000, 0.0278462000, 0.0333572000, 0.0453043000, 0.0719044000, 0.1390676000, 0.3184578000", \ - "0.0273382000, 0.0294373000, 0.0346769000, 0.0460064000, 0.0730921000, 0.1388552000, 0.3186862000", \ - "0.0394351000, 0.0427221000, 0.0478363000, 0.0592400000, 0.0846775000, 0.1455955000, 0.3208909000", \ - "0.0586966000, 0.0621029000, 0.0694690000, 0.0840776000, 0.1085627000, 0.1665664000, 0.3295225000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0381011000, 0.0460886000, 0.0664559000, 0.1192002000, 0.2536772000, 0.6001803000, 1.4758188000", \ - "0.0380606000, 0.0460790000, 0.0663492000, 0.1190981000, 0.2537064000, 0.5975983000, 1.4793547000", \ - "0.0381432000, 0.0459972000, 0.0665279000, 0.1191819000, 0.2537545000, 0.5994495000, 1.4808624000", \ - "0.0383746000, 0.0464138000, 0.0666500000, 0.1190637000, 0.2545955000, 0.5979719000, 1.4765567000", \ - "0.0414338000, 0.0490315000, 0.0684923000, 0.1197716000, 0.2534887000, 0.5975594000, 1.4768212000", \ - "0.0494856000, 0.0566454000, 0.0740001000, 0.1223709000, 0.2546289000, 0.5966870000, 1.4775206000", \ - "0.0646317000, 0.0718417000, 0.0892738000, 0.1323175000, 0.2569990000, 0.6002753000, 1.4740861000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0159532000, 0.0176173000, 0.0216005000, 0.0309414000, 0.0531194000, 0.1078442000, 0.2462899000", \ - "0.0210041000, 0.0225194000, 0.0263262000, 0.0355495000, 0.0577057000, 0.1124223000, 0.2509850000", \ - "0.0305058000, 0.0325879000, 0.0373189000, 0.0469902000, 0.0686917000, 0.1233813000, 0.2619028000", \ - "0.0425369000, 0.0457016000, 0.0525812000, 0.0675312000, 0.0948940000, 0.1496354000, 0.2875701000", \ - "0.0548513000, 0.0594791000, 0.0700069000, 0.0929645000, 0.1356883000, 0.2085364000, 0.3476981000", \ - "0.0581121000, 0.0655313000, 0.0820781000, 0.1167581000, 0.1838952000, 0.2981516000, 0.4853830000", \ - "0.0276354000, 0.0389158000, 0.0654221000, 0.1208359000, 0.2254197000, 0.4057636000, 0.6965175000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0629015000, 0.0693818000, 0.0853190000, 0.1247011000, 0.2232979000, 0.4745219000, 1.1094585000", \ - "0.0674587000, 0.0739285000, 0.0897569000, 0.1292312000, 0.2286494000, 0.4773527000, 1.1145312000", \ - "0.0800053000, 0.0863115000, 0.1020384000, 0.1409270000, 0.2393839000, 0.4951237000, 1.1348560000", \ - "0.1061866000, 0.1126919000, 0.1285296000, 0.1673577000, 0.2659028000, 0.5164865000, 1.1546973000", \ - "0.1482228000, 0.1573663000, 0.1785699000, 0.2249118000, 0.3247594000, 0.5746900000, 1.2141327000", \ - "0.2147495000, 0.2301026000, 0.2617924000, 0.3272468000, 0.4548423000, 0.7127467000, 1.3517981000", \ - "0.3211601000, 0.3438257000, 0.3946903000, 0.4967494000, 0.6826497000, 1.0133467000, 1.6755601000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0121092000, 0.0140031000, 0.0185590000, 0.0296002000, 0.0572151000, 0.1284871000, 0.3130052000", \ - "0.0125308000, 0.0141061000, 0.0183185000, 0.0293277000, 0.0572436000, 0.1284171000, 0.3119147000", \ - "0.0183850000, 0.0198361000, 0.0229534000, 0.0316193000, 0.0572586000, 0.1283941000, 0.3122562000", \ - "0.0290410000, 0.0312239000, 0.0363334000, 0.0468043000, 0.0664812000, 0.1298479000, 0.3119242000", \ - "0.0478155000, 0.0515389000, 0.0586214000, 0.0749412000, 0.1026737000, 0.1550897000, 0.3153853000", \ - "0.0800461000, 0.0857045000, 0.0979205000, 0.1227889000, 0.1666031000, 0.2410588000, 0.3738677000", \ - "0.1388318000, 0.1477538000, 0.1676557000, 0.2070200000, 0.2755252000, 0.3882712000, 0.5762861000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0375697000, 0.0457917000, 0.0664683000, 0.1192484000, 0.2543825000, 0.5982128000, 1.4769065000", \ - "0.0377768000, 0.0457266000, 0.0663373000, 0.1192721000, 0.2540506000, 0.5960867000, 1.4718062000", \ - "0.0379283000, 0.0458727000, 0.0666592000, 0.1191320000, 0.2533675000, 0.5994884000, 1.4898314000", \ - "0.0413939000, 0.0488491000, 0.0679864000, 0.1196340000, 0.2540320000, 0.5974135000, 1.4805017000", \ - "0.0580488000, 0.0662753000, 0.0863986000, 0.1316793000, 0.2566153000, 0.5976237000, 1.4757716000", \ - "0.0951699000, 0.1050091000, 0.1280694000, 0.1795429000, 0.2949418000, 0.6059665000, 1.4804326000", \ - "0.1737441000, 0.1855470000, 0.2145073000, 0.2788963000, 0.4124565000, 0.6982971000, 1.4931761000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrc_4") { - leakage_power () { - value : 0.0004812000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0041047000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0115579000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0128825000; - when : "A&!SLEEP"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__isobufsrc"; - cell_leakage_power : 0.0072565730; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213266000, 0.0211943000, 0.0208892000, 0.0210859000, 0.0215390000, 0.0225837000, 0.0249919000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072082000, 0.0071060000, 0.0068704000, 0.0070089000, 0.0073282000, 0.0080641000, 0.0097604000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("SLEEP") { - capacitance : 0.0086810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163411000, 0.0163396000, 0.0163361000, 0.0163320000, 0.0163224000, 0.0163003000, 0.0162493000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015076600, -0.015208700, -0.015513300, -0.015529200, -0.015565800, -0.015650100, -0.015844500"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091070000; - } - pin ("X") { - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0065992000, 0.0053411000, 0.0018174000, -0.008193900, -0.039279600, -0.132432400, -0.398443500", \ - "0.0064967000, 0.0052380000, 0.0018190000, -0.008172400, -0.039459700, -0.132465900, -0.398516900", \ - "0.0065978000, 0.0053514000, 0.0018233000, -0.008160900, -0.039349800, -0.132365000, -0.398401000", \ - "0.0060898000, 0.0048298000, 0.0012016000, -0.008870400, -0.040103800, -0.132964200, -0.398832900", \ - "0.0053391000, 0.0039615000, 0.0002152000, -0.010052000, -0.041066500, -0.133678300, -0.399286600", \ - "0.0065224000, 0.0050538000, 0.0011078000, -0.010305300, -0.042868900, -0.134747000, -0.400086500", \ - "0.0081061000, 0.0064968000, 0.0026280000, -0.010261200, -0.043053300, -0.136051600, -0.400735000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0217529000, 0.0233573000, 0.0276966000, 0.0402582000, 0.0742913000, 0.1683187000, 0.4325166000", \ - "0.0217986000, 0.0232972000, 0.0277789000, 0.0402427000, 0.0742300000, 0.1683183000, 0.4352205000", \ - "0.0217274000, 0.0232999000, 0.0277585000, 0.0401276000, 0.0741001000, 0.1687842000, 0.4329226000", \ - "0.0213503000, 0.0227112000, 0.0270785000, 0.0394302000, 0.0732445000, 0.1674657000, 0.4325612000", \ - "0.0210015000, 0.0225164000, 0.0268145000, 0.0387879000, 0.0724291000, 0.1665589000, 0.4319569000", \ - "0.0212032000, 0.0226972000, 0.0268484000, 0.0383998000, 0.0715490000, 0.1657788000, 0.4296247000", \ - "0.0216327000, 0.0230409000, 0.0273182000, 0.0389346000, 0.0720717000, 0.1661579000, 0.4293406000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0156603000, 0.0141994000, 0.0100369000, -0.001723400, -0.034930800, -0.128921500, -0.394981000", \ - "0.0150968000, 0.0136758000, 0.0095519000, -0.002137600, -0.035224200, -0.129173400, -0.395237300", \ - "0.0145217000, 0.0131042000, 0.0091203000, -0.002464400, -0.035385500, -0.129164200, -0.395250200", \ - "0.0136036000, 0.0121971000, 0.0081973000, -0.003204400, -0.035903400, -0.129505700, -0.395382200", \ - "0.0140303000, 0.0125554000, 0.0085893000, -0.002827200, -0.036379300, -0.129800900, -0.395641900", \ - "0.0160356000, 0.0145337000, 0.0106329000, -0.001923400, -0.034878600, -0.129446000, -0.395321400", \ - "0.0218320000, 0.0201055000, 0.0156098000, 0.0031652000, -0.031595100, -0.127120800, -0.394530900"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0247316000, 0.0263646000, 0.0308575000, 0.0430409000, 0.0764052000, 0.1701704000, 0.4328045000", \ - "0.0240669000, 0.0256314000, 0.0300764000, 0.0423153000, 0.0759472000, 0.1698013000, 0.4325925000", \ - "0.0235703000, 0.0251247000, 0.0294647000, 0.0415909000, 0.0754951000, 0.1690164000, 0.4325206000", \ - "0.0233160000, 0.0248267000, 0.0290888000, 0.0410531000, 0.0747278000, 0.1683379000, 0.4354658000", \ - "0.0230170000, 0.0245450000, 0.0287602000, 0.0405454000, 0.0738977000, 0.1675413000, 0.4313818000", \ - "0.0231342000, 0.0245850000, 0.0287752000, 0.0406781000, 0.0741695000, 0.1676460000, 0.4305988000", \ - "0.0248213000, 0.0260731000, 0.0299101000, 0.0411290000, 0.0747645000, 0.1683236000, 0.4330686000"); - } - } - max_capacitance : 0.2545270000; - max_transition : 1.4979180000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0977795000, 0.1000745000, 0.1057360000, 0.1182200000, 0.1435915000, 0.1995470000, 0.3430505000", \ - "0.1029064000, 0.1051694000, 0.1107779000, 0.1232238000, 0.1487210000, 0.2046316000, 0.3481125000", \ - "0.1157972000, 0.1180654000, 0.1236615000, 0.1362116000, 0.1617395000, 0.2175533000, 0.3610767000", \ - "0.1460184000, 0.1483136000, 0.1539129000, 0.1662587000, 0.1918519000, 0.2483772000, 0.3919360000", \ - "0.2128946000, 0.2153297000, 0.2213365000, 0.2344356000, 0.2606241000, 0.3172042000, 0.4610178000", \ - "0.3175447000, 0.3206632000, 0.3284230000, 0.3448395000, 0.3762611000, 0.4372571000, 0.5819330000", \ - "0.4716567000, 0.4757089000, 0.4859146000, 0.5065637000, 0.5473381000, 0.6187582000, 0.7663011000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0928147000, 0.0971228000, 0.1088444000, 0.1413558000, 0.2293673000, 0.4721448000, 1.1573766000", \ - "0.0976597000, 0.1019375000, 0.1137729000, 0.1461654000, 0.2341311000, 0.4770579000, 1.1617509000", \ - "0.1089983000, 0.1133625000, 0.1252057000, 0.1574394000, 0.2453100000, 0.4886567000, 1.1716412000", \ - "0.1352985000, 0.1391838000, 0.1508148000, 0.1827285000, 0.2705369000, 0.5132372000, 1.2069526000", \ - "0.1804233000, 0.1847746000, 0.1965307000, 0.2280231000, 0.3147629000, 0.5573966000, 1.2497489000", \ - "0.2421779000, 0.2471262000, 0.2597159000, 0.2914139000, 0.3774774000, 0.6194486000, 1.3003699000", \ - "0.3121997000, 0.3183856000, 0.3343887000, 0.3694187000, 0.4550140000, 0.6956424000, 1.3740475000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0217630000, 0.0232819000, 0.0267479000, 0.0357588000, 0.0586312000, 0.1217876000, 0.3098992000", \ - "0.0218615000, 0.0231300000, 0.0268550000, 0.0357496000, 0.0586032000, 0.1214610000, 0.3095133000", \ - "0.0217502000, 0.0230926000, 0.0266367000, 0.0357751000, 0.0585859000, 0.1217457000, 0.3095334000", \ - "0.0217920000, 0.0231543000, 0.0266908000, 0.0358855000, 0.0586044000, 0.1215928000, 0.3100314000", \ - "0.0258091000, 0.0271669000, 0.0306292000, 0.0387756000, 0.0606655000, 0.1224058000, 0.3099714000", \ - "0.0382268000, 0.0398160000, 0.0441935000, 0.0525366000, 0.0732338000, 0.1311745000, 0.3119316000", \ - "0.0578787000, 0.0600356000, 0.0652876000, 0.0765388000, 0.0978922000, 0.1513007000, 0.3202323000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0402938000, 0.0455372000, 0.0601489000, 0.1019518000, 0.2194860000, 0.5491805000, 1.4829701000", \ - "0.0404023000, 0.0455187000, 0.0603164000, 0.1019973000, 0.2189524000, 0.5492034000, 1.4915129000", \ - "0.0404294000, 0.0454191000, 0.0600965000, 0.1019582000, 0.2189981000, 0.5497766000, 1.4835964000", \ - "0.0405595000, 0.0457808000, 0.0604103000, 0.1019422000, 0.2195089000, 0.5481779000, 1.4865011000", \ - "0.0436174000, 0.0485572000, 0.0624350000, 0.1026194000, 0.2193180000, 0.5492477000, 1.4870921000", \ - "0.0517941000, 0.0564574000, 0.0690430000, 0.1063531000, 0.2205822000, 0.5498084000, 1.4836515000", \ - "0.0678176000, 0.0723064000, 0.0851565000, 0.1187569000, 0.2242531000, 0.5530017000, 1.4771380000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0160142000, 0.0170734000, 0.0198829000, 0.0271018000, 0.0457914000, 0.0958116000, 0.2345839000", \ - "0.0209866000, 0.0219348000, 0.0245740000, 0.0316841000, 0.0503207000, 0.1003642000, 0.2391566000", \ - "0.0299907000, 0.0313558000, 0.0347635000, 0.0428326000, 0.0611732000, 0.1111690000, 0.2499775000", \ - "0.0412602000, 0.0432970000, 0.0485171000, 0.0606468000, 0.0855117000, 0.1368408000, 0.2754638000", \ - "0.0515882000, 0.0546736000, 0.0622945000, 0.0810431000, 0.1200626000, 0.1913945000, 0.3346948000", \ - "0.0502625000, 0.0544404000, 0.0668979000, 0.0957900000, 0.1564998000, 0.2696998000, 0.4662067000", \ - "0.0087570000, 0.0159149000, 0.0348840000, 0.0803524000, 0.1754637000, 0.3539455000, 0.6623609000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0662193000, 0.0705136000, 0.0824626000, 0.1142396000, 0.2004072000, 0.4450964000, 1.1203567000", \ - "0.0706108000, 0.0749167000, 0.0866971000, 0.1184609000, 0.2053472000, 0.4494732000, 1.1264516000", \ - "0.0832835000, 0.0875039000, 0.0989490000, 0.1304218000, 0.2186063000, 0.4599167000, 1.1387854000", \ - "0.1095241000, 0.1138829000, 0.1255076000, 0.1571845000, 0.2438716000, 0.4859879000, 1.1722459000", \ - "0.1533716000, 0.1594285000, 0.1747303000, 0.2127773000, 0.3023857000, 0.5442786000, 1.2249649000", \ - "0.2256687000, 0.2348646000, 0.2580656000, 0.3130748000, 0.4290167000, 0.6817599000, 1.3626476000", \ - "0.3433862000, 0.3580201000, 0.3950045000, 0.4795025000, 0.6499844000, 0.9812183000, 1.6839738000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0123489000, 0.0135213000, 0.0166915000, 0.0253564000, 0.0486799000, 0.1150753000, 0.3039048000", \ - "0.0127588000, 0.0137470000, 0.0166011000, 0.0249156000, 0.0486199000, 0.1146939000, 0.3035438000", \ - "0.0185441000, 0.0194579000, 0.0220905000, 0.0282152000, 0.0490440000, 0.1147665000, 0.3031523000", \ - "0.0293116000, 0.0307264000, 0.0343030000, 0.0425244000, 0.0606824000, 0.1171715000, 0.3027833000", \ - "0.0474978000, 0.0496781000, 0.0551350000, 0.0682077000, 0.0943336000, 0.1473979000, 0.3071406000", \ - "0.0790182000, 0.0829210000, 0.0916790000, 0.1126393000, 0.1538581000, 0.2288781000, 0.3717098000", \ - "0.1367200000, 0.1423041000, 0.1572647000, 0.1905674000, 0.2545258000, 0.3673546000, 0.5672125000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0398143000, 0.0450898000, 0.0601129000, 0.1017104000, 0.2191035000, 0.5514366000, 1.4809522000", \ - "0.0399204000, 0.0451002000, 0.0601251000, 0.1017833000, 0.2195716000, 0.5508926000, 1.4813050000", \ - "0.0399267000, 0.0453411000, 0.0601783000, 0.1017358000, 0.2198251000, 0.5492258000, 1.4773405000", \ - "0.0431195000, 0.0480103000, 0.0619661000, 0.1022664000, 0.2199237000, 0.5492981000, 1.4906449000", \ - "0.0588935000, 0.0643565000, 0.0789295000, 0.1159391000, 0.2236749000, 0.5507776000, 1.4812200000", \ - "0.0942630000, 0.1003789000, 0.1170014000, 0.1601011000, 0.2638580000, 0.5587811000, 1.4859255000", \ - "0.1712996000, 0.1784710000, 0.1994217000, 0.2516639000, 0.3731783000, 0.6569621000, 1.4979178000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrc_8") { - leakage_power () { - value : 0.0049245000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0041854000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0127058000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0168970000; - when : "A&!SLEEP"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__isobufsrc"; - cell_leakage_power : 0.0096781860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0046180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0382978000, 0.0381008000, 0.0376467000, 0.0378678000, 0.0383776000, 0.0395529000, 0.0422619000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0302519000, 0.0300983000, 0.0297441000, 0.0299797000, 0.0305228000, 0.0317745000, 0.0346597000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048350000; - } - pin ("SLEEP") { - capacitance : 0.0167970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0156170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0160546000, 0.0160248000, 0.0159561000, 0.0160232000, 0.0161779000, 0.0165345000, 0.0173566000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014123200, -0.014115100, -0.014096300, -0.014088500, -0.014070500, -0.014029100, -0.013933600"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0179770000; - } - pin ("X") { - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015359980, 0.0047185810, 0.0144954600, 0.0445300100, 0.1367960000, 0.4202369000"); - values("0.0337480000, 0.0321832000, 0.0273051000, 0.0121875000, -0.034692200, -0.182926500, -0.641206600", \ - "0.0337420000, 0.0322256000, 0.0273648000, 0.0120648000, -0.034713400, -0.183050600, -0.641258200", \ - "0.0337034000, 0.0321166000, 0.0273087000, 0.0121292000, -0.034888400, -0.183016800, -0.641155400", \ - "0.0328236000, 0.0312166000, 0.0264338000, 0.0112595000, -0.035515500, -0.183622100, -0.641707200", \ - "0.0311123000, 0.0295228000, 0.0246253000, 0.0095634000, -0.037212900, -0.184657000, -0.642532100", \ - "0.0309026000, 0.0292176000, 0.0241558000, 0.0086936000, -0.037339300, -0.184830100, -0.642575400", \ - "0.0341630000, 0.0324795000, 0.0273940000, 0.0117540000, -0.036225200, -0.185122900, -0.642021000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015359980, 0.0047185810, 0.0144954600, 0.0445300100, 0.1367960000, 0.4202369000"); - values("0.0461754000, 0.0479447000, 0.0533242000, 0.0695244000, 0.1186223000, 0.2676013000, 0.7249494000", \ - "0.0461239000, 0.0479093000, 0.0532836000, 0.0696576000, 0.1186956000, 0.2677917000, 0.7247716000", \ - "0.0461459000, 0.0479169000, 0.0532104000, 0.0695773000, 0.1186607000, 0.2678766000, 0.7249223000", \ - "0.0451994000, 0.0469556000, 0.0523289000, 0.0685553000, 0.1172383000, 0.2655969000, 0.7192469000", \ - "0.0442806000, 0.0460138000, 0.0512968000, 0.0672807000, 0.1163190000, 0.2645719000, 0.7205497000", \ - "0.0440535000, 0.0457291000, 0.0509005000, 0.0665223000, 0.1155539000, 0.2636452000, 0.7215739000", \ - "0.0454567000, 0.0472381000, 0.0524960000, 0.0685433000, 0.1175174000, 0.2654450000, 0.7196445000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015359980, 0.0047185810, 0.0144954600, 0.0445300100, 0.1367960000, 0.4202369000"); - values("0.0028373000, 0.0012880000, -0.003543400, -0.018950000, -0.067157700, -0.216257000, -0.675307200", \ - "0.0015635000, -8.50000e-06, -0.004696700, -0.019637300, -0.067174900, -0.215864500, -0.674652200", \ - "-0.000707800, -0.002224600, -0.006687900, -0.021218900, -0.067959400, -0.215815000, -0.674281800", \ - "-0.003190400, -0.004692700, -0.009307900, -0.023526200, -0.069642700, -0.216556900, -0.674444000", \ - "-0.001978300, -0.003619200, -0.008638400, -0.023802900, -0.070814300, -0.217802700, -0.674876200", \ - "0.0013109000, -0.000466500, -0.005934100, -0.022209500, -0.070049800, -0.217804500, -0.675271400", \ - "0.0138124000, 0.0117969000, 0.0059985000, -0.011959800, -0.063356800, -0.214678000, -0.674940200"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015359980, 0.0047185810, 0.0144954600, 0.0445300100, 0.1367960000, 0.4202369000"); - values("0.0456867000, 0.0477243000, 0.0538087000, 0.0709549000, 0.1206855000, 0.2699608000, 0.7227420000", \ - "0.0437861000, 0.0456725000, 0.0514086000, 0.0687612000, 0.1190046000, 0.2684465000, 0.7282821000", \ - "0.0429544000, 0.0447224000, 0.0500525000, 0.0667254000, 0.1169412000, 0.2686868000, 0.7272739000", \ - "0.0430245000, 0.0446574000, 0.0498077000, 0.0657284000, 0.1151485000, 0.2652976000, 0.7208653000", \ - "0.0432539000, 0.0448880000, 0.0499724000, 0.0656177000, 0.1148745000, 0.2623938000, 0.7188082000", \ - "0.0478262000, 0.0493768000, 0.0541872000, 0.0691898000, 0.1159982000, 0.2629109000, 0.7206038000", \ - "0.0598252000, 0.0611911000, 0.0655340000, 0.0797276000, 0.1255247000, 0.2703213000, 0.7174285000"); - } - } - max_capacitance : 0.4202370000; - max_transition : 1.4997680000; - power_down_function : "(!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.1176153000, 0.1187556000, 0.1220740000, 0.1310764000, 0.1536291000, 0.2093375000, 0.3639812000", \ - "0.1227279000, 0.1238772000, 0.1272344000, 0.1361698000, 0.1588797000, 0.2146611000, 0.3690467000", \ - "0.1356356000, 0.1367455000, 0.1399958000, 0.1490658000, 0.1715768000, 0.2274493000, 0.3818475000", \ - "0.1672099000, 0.1683380000, 0.1715578000, 0.1806508000, 0.2033074000, 0.2590664000, 0.4137655000", \ - "0.2373068000, 0.2384644000, 0.2418971000, 0.2511358000, 0.2739176000, 0.3301984000, 0.4849104000", \ - "0.3561729000, 0.3576262000, 0.3617887000, 0.3728439000, 0.3989258000, 0.4585539000, 0.6138058000", \ - "0.5392656000, 0.5411421000, 0.5465265000, 0.5605980000, 0.5936717000, 0.6618467000, 0.8221742000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.1200215000, 0.1230509000, 0.1317889000, 0.1579292000, 0.2342616000, 0.4663639000, 1.1704768000", \ - "0.1246414000, 0.1276498000, 0.1365853000, 0.1627591000, 0.2386551000, 0.4697788000, 1.1752853000", \ - "0.1356754000, 0.1386273000, 0.1474695000, 0.1735672000, 0.2496817000, 0.4804657000, 1.1859596000", \ - "0.1601982000, 0.1630623000, 0.1719398000, 0.1978064000, 0.2741516000, 0.5038007000, 1.2069153000", \ - "0.1987732000, 0.2017161000, 0.2104996000, 0.2364469000, 0.3132369000, 0.5430383000, 1.2507533000", \ - "0.2456241000, 0.2488679000, 0.2581500000, 0.2848911000, 0.3615682000, 0.5914909000, 1.2984261000", \ - "0.2865588000, 0.2901258000, 0.3006874000, 0.3295131000, 0.4077474000, 0.6385726000, 1.3404308000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0282232000, 0.0292411000, 0.0323246000, 0.0411972000, 0.0659696000, 0.1404132000, 0.3763801000", \ - "0.0283344000, 0.0295509000, 0.0325821000, 0.0411386000, 0.0657893000, 0.1403168000, 0.3755670000", \ - "0.0283578000, 0.0295366000, 0.0326365000, 0.0411320000, 0.0659080000, 0.1401820000, 0.3757510000", \ - "0.0283921000, 0.0294417000, 0.0326697000, 0.0410538000, 0.0659128000, 0.1403835000, 0.3764113000", \ - "0.0306266000, 0.0316597000, 0.0345939000, 0.0429315000, 0.0670584000, 0.1410215000, 0.3762651000", \ - "0.0411286000, 0.0422668000, 0.0454433000, 0.0541136000, 0.0770653000, 0.1479622000, 0.3782836000", \ - "0.0583794000, 0.0598582000, 0.0640793000, 0.0748860000, 0.0991246000, 0.1644558000, 0.3850136000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0488622000, 0.0523234000, 0.0630468000, 0.0958878000, 0.1979956000, 0.5147492000, 1.4861836000", \ - "0.0488292000, 0.0522458000, 0.0628536000, 0.0960924000, 0.1985228000, 0.5149061000, 1.4852531000", \ - "0.0488617000, 0.0522325000, 0.0629974000, 0.0961583000, 0.1983563000, 0.5149071000, 1.4857152000", \ - "0.0491200000, 0.0526251000, 0.0631247000, 0.0960377000, 0.1978236000, 0.5115606000, 1.4757697000", \ - "0.0501731000, 0.0535841000, 0.0641825000, 0.0964446000, 0.1982712000, 0.5112261000, 1.4779412000", \ - "0.0533307000, 0.0566154000, 0.0669405000, 0.0990517000, 0.1992613000, 0.5116630000, 1.4824465000", \ - "0.0624576000, 0.0654287000, 0.0752687000, 0.1058595000, 0.2022684000, 0.5127239000, 1.4743746000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0151477000, 0.0157850000, 0.0175852000, 0.0226871000, 0.0372872000, 0.0809346000, 0.2144949000", \ - "0.0194638000, 0.0201179000, 0.0219886000, 0.0271911000, 0.0418808000, 0.0855647000, 0.2189484000", \ - "0.0251299000, 0.0262198000, 0.0292236000, 0.0366500000, 0.0527069000, 0.0965852000, 0.2303309000", \ - "0.0297062000, 0.0314071000, 0.0361844000, 0.0480096000, 0.0731764000, 0.1217761000, 0.2555210000", \ - "0.0279075000, 0.0305868000, 0.0381107000, 0.0568895000, 0.0969087000, 0.1717748000, 0.3134649000", \ - "0.0059769000, 0.0102856000, 0.0222637000, 0.0518715000, 0.1148263000, 0.2318813000, 0.4394206000", \ - "-0.071275800, -0.064590300, -0.046385300, 0.0001831000, 0.0998642000, 0.2872593000, 0.6115468000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0471441000, 0.0502291000, 0.0596576000, 0.0867491000, 0.1641268000, 0.3953066000, 1.0965286000", \ - "0.0495680000, 0.0523994000, 0.0614297000, 0.0881877000, 0.1665012000, 0.3980345000, 1.1083564000", \ - "0.0607847000, 0.0635759000, 0.0719422000, 0.0977822000, 0.1755160000, 0.4098243000, 1.1179752000", \ - "0.0891551000, 0.0923513000, 0.1015943000, 0.1258876000, 0.2015377000, 0.4349084000, 1.1390494000", \ - "0.1339225000, 0.1388951000, 0.1529829000, 0.1888517000, 0.2690757000, 0.4977722000, 1.2033113000", \ - "0.2104500000, 0.2177512000, 0.2385703000, 0.2924356000, 0.4121318000, 0.6552009000, 1.3593182000", \ - "0.3543034000, 0.3642542000, 0.3921395000, 0.4682439000, 0.6441789000, 1.0019179000, 1.7188667000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0073211000, 0.0079835000, 0.0100144000, 0.0163960000, 0.0359377000, 0.0963312000, 0.2812108000", \ - "0.0083556000, 0.0088969000, 0.0106266000, 0.0164962000, 0.0359579000, 0.0960440000, 0.2808102000", \ - "0.0135050000, 0.0142798000, 0.0163028000, 0.0215814000, 0.0375856000, 0.0964357000, 0.2811006000", \ - "0.0228836000, 0.0239620000, 0.0269443000, 0.0344265000, 0.0523825000, 0.1004215000, 0.2813154000", \ - "0.0405219000, 0.0421616000, 0.0467646000, 0.0579773000, 0.0828988000, 0.1345194000, 0.2878474000", \ - "0.0732488000, 0.0755938000, 0.0829560000, 0.1001149000, 0.1381889000, 0.2121423000, 0.3615457000", \ - "0.1339508000, 0.1380252000, 0.1494766000, 0.1781520000, 0.2383416000, 0.3461895000, 0.5494210000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015360000, 0.0047185800, 0.0144955000, 0.0445300000, 0.1367960000, 0.4202370000"); - values("0.0459793000, 0.0495966000, 0.0609334000, 0.0947366000, 0.1977666000, 0.5123976000, 1.4720235000", \ - "0.0456084000, 0.0494247000, 0.0605234000, 0.0944463000, 0.1979495000, 0.5114467000, 1.4879349000", \ - "0.0448136000, 0.0485828000, 0.0598350000, 0.0944980000, 0.1976933000, 0.5152596000, 1.4849157000", \ - "0.0565272000, 0.0588024000, 0.0671153000, 0.0961228000, 0.1976181000, 0.5141764000, 1.4753984000", \ - "0.0793493000, 0.0835403000, 0.0955345000, 0.1259878000, 0.2067757000, 0.5108995000, 1.4754861000", \ - "0.1174643000, 0.1231805000, 0.1394131000, 0.1825537000, 0.2754375000, 0.5295281000, 1.4825822000", \ - "0.1802606000, 0.1882133000, 0.2105895000, 0.2718851000, 0.4088286000, 0.6826879000, 1.4997682000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_isobufsrckapwr_16") { - leakage_power () { - value : 0.0109574000; - when : "!A&SLEEP"; - } - leakage_power () { - value : 0.0145802000; - when : "!A&!SLEEP"; - } - leakage_power () { - value : 0.0220334000; - when : "A&SLEEP"; - } - leakage_power () { - value : 0.0270417000; - when : "A&!SLEEP"; - } - area : 38.787200000; - cell_footprint : "sky130_fd_sc_hd__isobufsrckapwr"; - cell_leakage_power : 0.0186531800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_isolation_cell : "true"; - pg_pin ("KAPWR") { - pg_type : "backup_power"; - voltage_name : "KAPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213133000, 0.0211815000, 0.0208777000, 0.0210733000, 0.0215240000, 0.0225628000, 0.0249574000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0069232000, 0.0068178000, 0.0065748000, 0.0067100000, 0.0070216000, 0.0077402000, 0.0093966000"); - } - } - isolation_cell_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024750000; - } - pin ("SLEEP") { - always_on : "true"; - capacitance : 0.0087260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0164540000, 0.0164474000, 0.0164323000, 0.0164286000, 0.0164201000, 0.0164008000, 0.0163561000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015046100, -0.015180500, -0.015490100, -0.015507400, -0.015547100, -0.015638500, -0.015849100"); - } - } - isolation_cell_enable_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - rise_capacitance : 0.0091650000; - } - pin ("X") { - always_on : "true"; - direction : "output"; - function : "(A&!SLEEP)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293203800, 0.1139120000, 0.4425572000, 1.7193700000"); - values("0.1011384000, 0.0990559000, 0.0912085000, 0.0604689000, -0.068732600, -0.597171500, -2.664788000", \ - "0.1012193000, 0.0991808000, 0.0912903000, 0.0604798000, -0.068693200, -0.596831400, -2.664667900", \ - "0.1012466000, 0.0991691000, 0.0912964000, 0.0605349000, -0.068669100, -0.596992200, -2.664117800", \ - "0.1004919000, 0.0984821000, 0.0904214000, 0.0597386000, -0.069322200, -0.597858000, -2.664962600", \ - "0.0996716000, 0.0976190000, 0.0895379000, 0.0588438000, -0.070204400, -0.598681500, -2.666089400", \ - "0.0982575000, 0.0962237000, 0.0883078000, 0.0576323000, -0.071461200, -0.599947000, -2.667048700", \ - "0.1018654000, 0.0997990000, 0.0916455000, 0.0594499000, -0.071915000, -0.600313500, -2.667437500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293203800, 0.1139120000, 0.4425572000, 1.7193700000"); - values("0.1257254000, 0.1279527000, 0.1375521000, 0.1741457000, 0.3126052000, 0.8386842000, 2.8826357000", \ - "0.1255808000, 0.1279845000, 0.1375934000, 0.1743367000, 0.3126351000, 0.8390004000, 2.8856212000", \ - "0.1257042000, 0.1279283000, 0.1375276000, 0.1741211000, 0.3125835000, 0.8386590000, 2.8827734000", \ - "0.1248480000, 0.1272889000, 0.1369274000, 0.1735260000, 0.3117895000, 0.8381754000, 2.8832796000", \ - "0.1240506000, 0.1264854000, 0.1361618000, 0.1729109000, 0.3111712000, 0.8375226000, 2.8852665000", \ - "0.1236209000, 0.1260569000, 0.1356828000, 0.1725718000, 0.3105099000, 0.8372841000, 2.8817598000", \ - "0.1271918000, 0.1296952000, 0.1387533000, 0.1749721000, 0.3132258000, 0.8390290000, 2.8750328000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293203800, 0.1139120000, 0.4425572000, 1.7193700000"); - values("0.1059488000, 0.1039492000, 0.0959491000, 0.0649844000, -0.064215800, -0.592303700, -2.658619500", \ - "0.1055710000, 0.1036460000, 0.0955531000, 0.0645937000, -0.064467200, -0.592583600, -2.659181900", \ - "0.1052840000, 0.1033609000, 0.0953278000, 0.0644359000, -0.064751100, -0.592860800, -2.659303300", \ - "0.1045163000, 0.1024896000, 0.0944089000, 0.0635076000, -0.065633000, -0.593702000, -2.660051300", \ - "0.1043748000, 0.1024382000, 0.0942678000, 0.0632477000, -0.065814900, -0.593693900, -2.660366700", \ - "0.1098879000, 0.1077676000, 0.0997580000, 0.0674049000, -0.064735800, -0.592752300, -2.659370500", \ - "0.1154555000, 0.1134387000, 0.1044315000, 0.0720080000, -0.059457700, -0.588187000, -2.654640300"); - } - related_pin : "SLEEP"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293203800, 0.1139120000, 0.4425572000, 1.7193700000"); - values("0.1282222000, 0.1307317000, 0.1403071000, 0.1771989000, 0.3152374000, 0.8418040000, 2.8883594000", \ - "0.1275568000, 0.1299837000, 0.1396319000, 0.1760172000, 0.3144842000, 0.8406470000, 2.8864826000", \ - "0.1265699000, 0.1290633000, 0.1386055000, 0.1756378000, 0.3137029000, 0.8400073000, 2.8769981000", \ - "0.1260055000, 0.1283776000, 0.1379120000, 0.1749129000, 0.3131194000, 0.8393288000, 2.8761733000", \ - "0.1251000000, 0.1275969000, 0.1371367000, 0.1740940000, 0.3119478000, 0.8383614000, 2.8844419000", \ - "0.1243992000, 0.1270101000, 0.1364398000, 0.1733888000, 0.3110222000, 0.8378347000, 2.8826542000", \ - "0.1281676000, 0.1305356000, 0.1400241000, 0.1759788000, 0.3131120000, 0.8412672000, 2.8808250000"); - } - } - max_capacitance : 1.7193700000; - max_transition : 1.5050850000; - power_down_function : "(!KAPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "KAPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.2354291000, 0.2371526000, 0.2431633000, 0.2609558000, 0.3091693000, 0.4592866000, 1.0225805000", \ - "0.2405476000, 0.2422794000, 0.2482412000, 0.2660603000, 0.3141824000, 0.4640167000, 1.0295634000", \ - "0.2534655000, 0.2551818000, 0.2611396000, 0.2789562000, 0.3270831000, 0.4769597000, 1.0452522000", \ - "0.2836212000, 0.2853466000, 0.2913095000, 0.3091166000, 0.3573197000, 0.5074453000, 1.0726506000", \ - "0.3523734000, 0.3540912000, 0.3600556000, 0.3778566000, 0.4260557000, 0.5761776000, 1.1430635000", \ - "0.4670750000, 0.4687995000, 0.4747673000, 0.4925779000, 0.5406878000, 0.6909368000, 1.2584098000", \ - "0.6363470000, 0.6381063000, 0.6440834000, 0.6618945000, 0.7101538000, 0.8600728000, 1.4229226000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.2692735000, 0.2711510000, 0.2779171000, 0.2981206000, 0.3560424000, 0.5530842000, 1.3112319000", \ - "0.2740005000, 0.2760021000, 0.2827971000, 0.3030001000, 0.3609237000, 0.5582187000, 1.3177404000", \ - "0.2854505000, 0.2873253000, 0.2940924000, 0.3142917000, 0.3722143000, 0.5692504000, 1.3272300000", \ - "0.3105980000, 0.3125561000, 0.3193147000, 0.3395570000, 0.3976021000, 0.5948289000, 1.3544416000", \ - "0.3564019000, 0.3583536000, 0.3652026000, 0.3854055000, 0.4433385000, 0.6409056000, 1.4009720000", \ - "0.4199084000, 0.4219158000, 0.4287143000, 0.4489251000, 0.5068665000, 0.7043112000, 1.4678162000", \ - "0.4987968000, 0.5007504000, 0.5074861000, 0.5277578000, 0.5857200000, 0.7828252000, 1.5397859000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.0235083000, 0.0247190000, 0.0289399000, 0.0432891000, 0.0938746000, 0.2957353000, 1.1019111000", \ - "0.0234409000, 0.0246362000, 0.0289935000, 0.0431645000, 0.0939648000, 0.2959377000, 1.1040863000", \ - "0.0235372000, 0.0247551000, 0.0290104000, 0.0432080000, 0.0939885000, 0.2957886000, 1.1043605000", \ - "0.0235571000, 0.0247075000, 0.0289261000, 0.0430600000, 0.0939146000, 0.2954678000, 1.1040292000", \ - "0.0235509000, 0.0247208000, 0.0289213000, 0.0430615000, 0.0939273000, 0.2954552000, 1.1029582000", \ - "0.0235932000, 0.0247648000, 0.0289660000, 0.0431039000, 0.0938841000, 0.2957377000, 1.1028477000", \ - "0.0237044000, 0.0248481000, 0.0289739000, 0.0434358000, 0.0940505000, 0.2958125000, 1.1020458000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.0272539000, 0.0287402000, 0.0339936000, 0.0523337000, 0.1212118000, 0.3997497000, 1.5036752000", \ - "0.0272279000, 0.0286754000, 0.0339892000, 0.0523860000, 0.1211861000, 0.4005061000, 1.5037984000", \ - "0.0272546000, 0.0287405000, 0.0339933000, 0.0523339000, 0.1212117000, 0.3997475000, 1.5038232000", \ - "0.0272284000, 0.0286140000, 0.0338648000, 0.0524051000, 0.1214199000, 0.4002200000, 1.5050310000", \ - "0.0272408000, 0.0286492000, 0.0339565000, 0.0524495000, 0.1211219000, 0.4000608000, 1.5041449000", \ - "0.0272756000, 0.0286954000, 0.0340062000, 0.0524588000, 0.1214270000, 0.4006356000, 1.5050852000", \ - "0.0274333000, 0.0289522000, 0.0341902000, 0.0524558000, 0.1212856000, 0.3999941000, 1.5009578000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.1462297000, 0.1479947000, 0.1539976000, 0.1718862000, 0.2203205000, 0.3707581000, 0.9351682000", \ - "0.1507265000, 0.1524648000, 0.1584486000, 0.1763533000, 0.2247949000, 0.3750765000, 0.9431333000", \ - "0.1616141000, 0.1634094000, 0.1694095000, 0.1873060000, 0.2357586000, 0.3861941000, 0.9503242000", \ - "0.1824712000, 0.1842081000, 0.1902176000, 0.2081202000, 0.2565687000, 0.4070130000, 0.9716492000", \ - "0.2093249000, 0.2110734000, 0.2170736000, 0.2347329000, 0.2832605000, 0.4337080000, 0.9972440000", \ - "0.2349805000, 0.2367116000, 0.2427164000, 0.2606249000, 0.3091432000, 0.4597927000, 1.0233417000", \ - "0.2398003000, 0.2415420000, 0.2475704000, 0.2653964000, 0.3138395000, 0.4644478000, 1.0317190000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.2463743000, 0.2483413000, 0.2551179000, 0.2753331000, 0.3332837000, 0.5309191000, 1.2885212000", \ - "0.2503474000, 0.2523044000, 0.2590629000, 0.2792750000, 0.3372070000, 0.5342418000, 1.2933982000", \ - "0.2620232000, 0.2639820000, 0.2707204000, 0.2910104000, 0.3490074000, 0.5467771000, 1.3030732000", \ - "0.2886285000, 0.2905785000, 0.2973226000, 0.3176192000, 0.3755167000, 0.5733045000, 1.3297130000", \ - "0.3453380000, 0.3472987000, 0.3540560000, 0.3743462000, 0.4323341000, 0.6301190000, 1.3881293000", \ - "0.4519988000, 0.4539990000, 0.4607839000, 0.4812125000, 0.5393765000, 0.7369880000, 1.4957861000", \ - "0.6325543000, 0.6346226000, 0.6416950000, 0.6625102000, 0.7211218000, 0.9186699000, 1.6758138000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.0237674000, 0.0249098000, 0.0291940000, 0.0436352000, 0.0944772000, 0.2962513000, 1.1053649000", \ - "0.0237506000, 0.0250428000, 0.0292071000, 0.0434714000, 0.0944655000, 0.2959215000, 1.1056078000", \ - "0.0236954000, 0.0249141000, 0.0291944000, 0.0436297000, 0.0944614000, 0.2962624000, 1.1050469000", \ - "0.0237666000, 0.0249145000, 0.0290910000, 0.0436648000, 0.0944955000, 0.2962060000, 1.1055481000", \ - "0.0240553000, 0.0251702000, 0.0293668000, 0.0435101000, 0.0943596000, 0.2960925000, 1.1023774000", \ - "0.0238698000, 0.0251221000, 0.0293678000, 0.0437691000, 0.0946248000, 0.2963825000, 1.1035090000", \ - "0.0242444000, 0.0253277000, 0.0295231000, 0.0439505000, 0.0948583000, 0.2960939000, 1.1019970000"); - } - related_pin : "SLEEP"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0019425400, 0.0075469200, 0.0293204000, 0.1139120000, 0.4425570000, 1.7193700000"); - values("0.0273812000, 0.0287360000, 0.0339475000, 0.0524513000, 0.1209923000, 0.3996536000, 1.5033835000", \ - "0.0272336000, 0.0286390000, 0.0338105000, 0.0523634000, 0.1212133000, 0.3993365000, 1.5043483000", \ - "0.0273192000, 0.0286454000, 0.0338994000, 0.0523168000, 0.1213771000, 0.4005540000, 1.5009307000", \ - "0.0272376000, 0.0286830000, 0.0339087000, 0.0523961000, 0.1211966000, 0.4000753000, 1.5006197000", \ - "0.0273904000, 0.0287229000, 0.0339707000, 0.0524284000, 0.1209531000, 0.4003867000, 1.5027982000", \ - "0.0281659000, 0.0295848000, 0.0348554000, 0.0531341000, 0.1213288000, 0.4004071000, 1.5027721000", \ - "0.0299233000, 0.0313573000, 0.0364479000, 0.0543595000, 0.1221768000, 0.4000740000, 1.4981214000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1") { - leakage_power () { - value : 0.0040109000; - when : "!A"; - } - leakage_power () { - value : 0.0128890000; - when : "A"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_hl_isowell_tap"; - cell_leakage_power : 0.0084499560; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "HL_LH"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pg_pin ("VPWRIN") { - pg_type : "primary_power"; - voltage_name : "VPWRIN"; - } - pin ("A") { - capacitance : 0.0060050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059730000; - input_signal_level : "VPWRIN"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWRIN"; - rise_capacitance : 0.0060360000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0666069000, 0.0658148000, 0.0635455000, 0.0562799000, 0.0366015000, -0.013118400, -0.138450400", \ - "0.0644716000, 0.0636973000, 0.0614099000, 0.0540933000, 0.0344460000, -0.015261900, -0.140563400", \ - "0.0629772000, 0.0621609000, 0.0598586000, 0.0525469000, 0.0328902000, -0.016807700, -0.142105900", \ - "0.0623686000, 0.0615903000, 0.0592437000, 0.0519340000, 0.0322833000, -0.017424800, -0.142722400", \ - "0.0630116000, 0.0622536000, 0.0599631000, 0.0526606000, 0.0329912000, -0.016751500, -0.142045600", \ - "0.0659842000, 0.0648258000, 0.0617777000, 0.0539078000, 0.0345618000, -0.015163500, -0.140488700", \ - "0.0707192000, 0.0695170000, 0.0664897000, 0.0586095000, 0.0387032000, -0.011172600, -0.136054300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0475195000, 0.0489009000, 0.0522202000, 0.0602185000, 0.0797879000, 0.1285391000, 0.2519763000", \ - "0.0477653000, 0.0491705000, 0.0524904000, 0.0604583000, 0.0800413000, 0.1287858000, 0.2520080000", \ - "0.0499663000, 0.0513810000, 0.0547010000, 0.0626715000, 0.0822366000, 0.1310915000, 0.2543952000", \ - "0.0572633000, 0.0586674000, 0.0619839000, 0.0699514000, 0.0895371000, 0.1382222000, 0.2626607000", \ - "0.0700089000, 0.0714157000, 0.0747290000, 0.0826844000, 0.1023757000, 0.1515468000, 0.2743529000", \ - "0.0906735000, 0.0919866000, 0.0951997000, 0.1029862000, 0.1225482000, 0.1718329000, 0.2946264000", \ - "0.1218675000, 0.1231849000, 0.1264206000, 0.1344631000, 0.1539236000, 0.2030844000, 0.3259181000"); - } - } - max_capacitance : 0.1281840000; - max_transition : 1.5082230000; - power_down_function : "(!VPWRIN+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1454589000, 0.1502713000, 0.1599459000, 0.1793152000, 0.2205457000, 0.3178710000, 0.5623551000", \ - "0.1498388000, 0.1545513000, 0.1643017000, 0.1836732000, 0.2248461000, 0.3222360000, 0.5663129000", \ - "0.1621660000, 0.1669062000, 0.1766199000, 0.1959760000, 0.2371555000, 0.3344875000, 0.5793021000", \ - "0.1917064000, 0.1964917000, 0.2062298000, 0.2255420000, 0.2666949000, 0.3641012000, 0.6083425000", \ - "0.2441024000, 0.2488724000, 0.2585523000, 0.2778781000, 0.3190047000, 0.4163649000, 0.6618909000", \ - "0.3210611000, 0.3258476000, 0.3355494000, 0.3548250000, 0.3958999000, 0.4932024000, 0.7371429000", \ - "0.4295365000, 0.4342948000, 0.4440188000, 0.4632701000, 0.5041697000, 0.6012432000, 0.8454257000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1803228000, 0.1873066000, 0.2039925000, 0.2443161000, 0.3420605000, 0.5862133000, 1.1999580000", \ - "0.1848014000, 0.1918927000, 0.2086041000, 0.2488692000, 0.3466879000, 0.5904272000, 1.2073024000", \ - "0.1960401000, 0.2031274000, 0.2197711000, 0.2600022000, 0.3579515000, 0.6013241000, 1.2177330000", \ - "0.2214663000, 0.2285563000, 0.2452456000, 0.2855267000, 0.3833223000, 0.6268763000, 1.2436443000", \ - "0.2615042000, 0.2685716000, 0.2852626000, 0.3253982000, 0.4232945000, 0.6668294000, 1.2849350000", \ - "0.3167741000, 0.3238735000, 0.3405689000, 0.3808241000, 0.4789721000, 0.7227210000, 1.3356405000", \ - "0.3896990000, 0.3967912000, 0.4136267000, 0.4539051000, 0.5518670000, 0.7965616000, 1.4079961000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0165354000, 0.0204344000, 0.0288723000, 0.0481636000, 0.0954784000, 0.2208997000, 0.5413865000", \ - "0.0164604000, 0.0202667000, 0.0288647000, 0.0478514000, 0.0953409000, 0.2215737000, 0.5402253000", \ - "0.0164763000, 0.0203886000, 0.0287737000, 0.0477475000, 0.0953260000, 0.2210787000, 0.5460719000", \ - "0.0164159000, 0.0200868000, 0.0288146000, 0.0479181000, 0.0952966000, 0.2223154000, 0.5487357000", \ - "0.0163365000, 0.0201780000, 0.0287830000, 0.0480278000, 0.0954165000, 0.2214114000, 0.5416482000", \ - "0.0163492000, 0.0202513000, 0.0286324000, 0.0478739000, 0.0954149000, 0.2200315000, 0.5437487000", \ - "0.0164077000, 0.0200794000, 0.0286627000, 0.0477562000, 0.0953725000, 0.2204612000, 0.5424337000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0230291000, 0.0314795000, 0.0531412000, 0.1084744000, 0.2486472000, 0.6037408000, 1.5029737000", \ - "0.0230160000, 0.0314681000, 0.0531305000, 0.1085167000, 0.2487134000, 0.6042548000, 1.5013907000", \ - "0.0230787000, 0.0314776000, 0.0530588000, 0.1085383000, 0.2488711000, 0.6046291000, 1.5043325000", \ - "0.0229944000, 0.0314444000, 0.0531264000, 0.1084937000, 0.2486378000, 0.6037729000, 1.5082229000", \ - "0.0230448000, 0.0314797000, 0.0530439000, 0.1085037000, 0.2486644000, 0.6062588000, 1.5061826000", \ - "0.0231216000, 0.0315806000, 0.0532456000, 0.1086202000, 0.2480199000, 0.6042309000, 1.5022911000", \ - "0.0231937000, 0.0316264000, 0.0532593000, 0.1086844000, 0.2486215000, 0.6051953000, 1.4924076000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2") { - leakage_power () { - value : 0.0072536000; - when : "!A"; - } - leakage_power () { - value : 0.0133877000; - when : "A"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_hl_isowell_tap"; - cell_leakage_power : 0.0103206600; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "HL_LH"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pg_pin ("VPWRIN") { - pg_type : "primary_power"; - voltage_name : "VPWRIN"; - } - pin ("A") { - capacitance : 0.0060240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059910000; - input_signal_level : "VPWRIN"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWRIN"; - rise_capacitance : 0.0060570000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0709261000, 0.0695932000, 0.0659052000, 0.0541762000, 0.0168543000, -0.093213000, -0.413325800", \ - "0.0687892000, 0.0674407000, 0.0638037000, 0.0520087000, 0.0147574000, -0.095327300, -0.415404700", \ - "0.0672449000, 0.0658994000, 0.0622559000, 0.0504748000, 0.0132152000, -0.096818700, -0.416921400", \ - "0.0666453000, 0.0653056000, 0.0615978000, 0.0498536000, 0.0126200000, -0.097437400, -0.417505900", \ - "0.0672731000, 0.0659804000, 0.0623102000, 0.0505975000, 0.0132844000, -0.096775600, -0.416872800", \ - "0.0704379000, 0.0690190000, 0.0647990000, 0.0520561000, 0.0148166000, -0.095281900, -0.415400200", \ - "0.0750739000, 0.0737196000, 0.0693941000, 0.0567304000, 0.0188979000, -0.091425300, -0.411139200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0527395000, 0.0544599000, 0.0592577000, 0.0727027000, 0.1105841000, 0.2194089000, 0.5356605000", \ - "0.0529580000, 0.0546712000, 0.0595148000, 0.0729735000, 0.1108162000, 0.2196662000, 0.5354008000", \ - "0.0551870000, 0.0569037000, 0.0617241000, 0.0751971000, 0.1130572000, 0.2216852000, 0.5374515000", \ - "0.0624335000, 0.0641606000, 0.0690205000, 0.0824430000, 0.1204068000, 0.2290167000, 0.5466849000", \ - "0.0752163000, 0.0769305000, 0.0817912000, 0.0952392000, 0.1330736000, 0.2414648000, 0.5577926000", \ - "0.0962047000, 0.0978557000, 0.1025069000, 0.1155647000, 0.1535493000, 0.2621025000, 0.5754471000", \ - "0.1281622000, 0.1298185000, 0.1344746000, 0.1479464000, 0.1861013000, 0.2953171000, 0.6083219000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5053220000; - power_down_function : "(!VPWRIN+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1657121000, 0.1700538000, 0.1798035000, 0.1999809000, 0.2432771000, 0.3511756000, 0.6583855000", \ - "0.1699223000, 0.1742237000, 0.1840568000, 0.2042310000, 0.2474442000, 0.3554499000, 0.6625536000", \ - "0.1821764000, 0.1864775000, 0.1962842000, 0.2165013000, 0.2596848000, 0.3676681000, 0.6750945000", \ - "0.2117323000, 0.2160443000, 0.2257846000, 0.2459690000, 0.2892232000, 0.3971893000, 0.7037250000", \ - "0.2640917000, 0.2684022000, 0.2781570000, 0.2983946000, 0.3416024000, 0.4495876000, 0.7569353000", \ - "0.3408588000, 0.3451303000, 0.3549347000, 0.3751852000, 0.4183329000, 0.5262104000, 0.8323846000", \ - "0.4489404000, 0.4532348000, 0.4630022000, 0.4832169000, 0.5264070000, 0.6343337000, 0.9409595000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1892277000, 0.1940791000, 0.2060907000, 0.2361613000, 0.3179241000, 0.5501658000, 1.2270968000", \ - "0.1937644000, 0.1986322000, 0.2106753000, 0.2407168000, 0.3224130000, 0.5544739000, 1.2313773000", \ - "0.2048866000, 0.2097316000, 0.2218110000, 0.2518492000, 0.3335277000, 0.5657280000, 1.2406125000", \ - "0.2303759000, 0.2352598000, 0.2472900000, 0.2773445000, 0.3588227000, 0.5920230000, 1.2672331000", \ - "0.2704673000, 0.2753112000, 0.2873591000, 0.3173877000, 0.3990312000, 0.6310975000, 1.3103196000", \ - "0.3258794000, 0.3307360000, 0.3427560000, 0.3727555000, 0.4543574000, 0.6872521000, 1.3609048000", \ - "0.3986987000, 0.4035745000, 0.4156182000, 0.4456447000, 0.5271785000, 0.7600349000, 1.4321960000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0181946000, 0.0210962000, 0.0280296000, 0.0450410000, 0.0899852000, 0.2244856000, 0.6306293000", \ - "0.0181754000, 0.0210696000, 0.0278117000, 0.0450095000, 0.0898436000, 0.2255422000, 0.6339346000", \ - "0.0181859000, 0.0210447000, 0.0278930000, 0.0448670000, 0.0896792000, 0.2248789000, 0.6326267000", \ - "0.0179694000, 0.0207966000, 0.0278589000, 0.0448273000, 0.0897090000, 0.2240395000, 0.6353567000", \ - "0.0181173000, 0.0207003000, 0.0276706000, 0.0448393000, 0.0897111000, 0.2250433000, 0.6334606000", \ - "0.0178809000, 0.0209969000, 0.0280966000, 0.0447861000, 0.0899282000, 0.2236052000, 0.6343585000", \ - "0.0179171000, 0.0209427000, 0.0279365000, 0.0447634000, 0.0900859000, 0.2247308000, 0.6294247000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0183449000, 0.0229002000, 0.0357856000, 0.0739294000, 0.1882545000, 0.5242115000, 1.5053224000", \ - "0.0184106000, 0.0229790000, 0.0358575000, 0.0738685000, 0.1882196000, 0.5240053000, 1.5013660000", \ - "0.0183474000, 0.0229170000, 0.0358951000, 0.0738560000, 0.1883492000, 0.5242318000, 1.5006851000", \ - "0.0183800000, 0.0229435000, 0.0358666000, 0.0739443000, 0.1882991000, 0.5242746000, 1.5029809000", \ - "0.0183520000, 0.0229346000, 0.0358496000, 0.0739007000, 0.1884321000, 0.5238092000, 1.5017807000", \ - "0.0184367000, 0.0230266000, 0.0360183000, 0.0740533000, 0.1878702000, 0.5233862000, 1.5000728000", \ - "0.0185393000, 0.0231211000, 0.0361132000, 0.0741418000, 0.1879982000, 0.5242095000, 1.4977014000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4") { - leakage_power () { - value : 0.0144944000; - when : "A"; - } - leakage_power () { - value : 0.0079841000; - when : "!A"; - } - area : 40.038400000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_hl_isowell_tap"; - cell_leakage_power : 0.0112392300; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "HL_LH"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pg_pin ("VPWRIN") { - pg_type : "primary_power"; - voltage_name : "VPWRIN"; - } - pin ("A") { - capacitance : 0.0060090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059820000; - input_signal_level : "VPWRIN"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWRIN"; - rise_capacitance : 0.0060360000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0797332000, 0.0779974000, 0.0727341000, 0.0564963000, -0.000150800, -0.189956100, -0.802660600", \ - "0.0774675000, 0.0757457000, 0.0704464000, 0.0542869000, -0.002359900, -0.192130400, -0.804823800", \ - "0.0758446000, 0.0741403000, 0.0688814000, 0.0526943000, -0.003907400, -0.193679100, -0.806317300", \ - "0.0752267000, 0.0735124000, 0.0682374000, 0.0520794000, -0.004529600, -0.194268300, -0.806964800", \ - "0.0757893000, 0.0740693000, 0.0687830000, 0.0526491000, -0.003933300, -0.193718100, -0.806377200", \ - "0.0791722000, 0.0774007000, 0.0718452000, 0.0538231000, -0.002343500, -0.192180500, -0.804885900", \ - "0.0855790000, 0.0838329000, 0.0782814000, 0.0606451000, 0.0016603000, -0.188803200, -0.801201100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0640623000, 0.0659751000, 0.0720920000, 0.0914153000, 0.1512683000, 0.3400952000, 0.9402325000", \ - "0.0643617000, 0.0662770000, 0.0724491000, 0.0915904000, 0.1516077000, 0.3405099000, 0.9453431000", \ - "0.0665088000, 0.0684518000, 0.0745352000, 0.0937734000, 0.1536506000, 0.3425817000, 0.9470333000", \ - "0.0736732000, 0.0755832000, 0.0817045000, 0.1010232000, 0.1609037000, 0.3496039000, 0.9502492000", \ - "0.0866237000, 0.0884421000, 0.0946184000, 0.1138386000, 0.1736934000, 0.3624997000, 0.9644226000", \ - "0.1075086000, 0.1093158000, 0.1152817000, 0.1340904000, 0.1941213000, 0.3825726000, 0.9870969000", \ - "0.1403614000, 0.1422527000, 0.1482499000, 0.1673138000, 0.2276658000, 0.4172479000, 1.0150512000"); - } - } - max_capacitance : 0.5493260000; - max_transition : 1.5084210000; - power_down_function : "(!VPWRIN+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2061720000, 0.2098357000, 0.2193025000, 0.2405003000, 0.2850765000, 0.3908754000, 0.7003834000", \ - "0.2100965000, 0.2137479000, 0.2232211000, 0.2444172000, 0.2889586000, 0.3947462000, 0.7039513000", \ - "0.2223106000, 0.2259537000, 0.2354366000, 0.2565999000, 0.3011223000, 0.4070039000, 0.7166928000", \ - "0.2518410000, 0.2554792000, 0.2649509000, 0.2861675000, 0.3306687000, 0.4364819000, 0.7456455000", \ - "0.3041731000, 0.3078092000, 0.3173108000, 0.3384986000, 0.3828264000, 0.4887117000, 0.7984123000", \ - "0.3808393000, 0.3844831000, 0.3939671000, 0.4152137000, 0.4597309000, 0.5655483000, 0.8753594000", \ - "0.4886296000, 0.4922623000, 0.5017286000, 0.5229782000, 0.5665625000, 0.6723901000, 0.9816292000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2144032000, 0.2181773000, 0.2284638000, 0.2548182000, 0.3272365000, 0.5505775000, 1.2618733000", \ - "0.2189395000, 0.2227078000, 0.2330033000, 0.2593291000, 0.3318149000, 0.5547526000, 1.2670693000", \ - "0.2300325000, 0.2338175000, 0.2440794000, 0.2704887000, 0.3429926000, 0.5661315000, 1.2796040000", \ - "0.2555697000, 0.2593417000, 0.2696302000, 0.2959755000, 0.3683406000, 0.5912647000, 1.3043564000", \ - "0.2958069000, 0.2995608000, 0.3098266000, 0.3361427000, 0.4086647000, 0.6319823000, 1.3431446000", \ - "0.3517203000, 0.3555070000, 0.3658068000, 0.3921237000, 0.4645894000, 0.6875640000, 1.3987540000", \ - "0.4256702000, 0.4294627000, 0.4398017000, 0.4661672000, 0.5387143000, 0.7618214000, 1.4718186000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0251400000, 0.0272557000, 0.0334269000, 0.0477824000, 0.0872649000, 0.2060923000, 0.6150900000", \ - "0.0251575000, 0.0272306000, 0.0334368000, 0.0477173000, 0.0868946000, 0.2062452000, 0.6151203000", \ - "0.0249080000, 0.0271406000, 0.0334401000, 0.0476822000, 0.0871476000, 0.2063884000, 0.6124199000", \ - "0.0248950000, 0.0271638000, 0.0333534000, 0.0478490000, 0.0869437000, 0.2061652000, 0.6113350000", \ - "0.0249199000, 0.0271912000, 0.0334644000, 0.0478097000, 0.0871778000, 0.2062128000, 0.6120599000", \ - "0.0249096000, 0.0271455000, 0.0336210000, 0.0477861000, 0.0871853000, 0.2062394000, 0.6141070000", \ - "0.0249635000, 0.0272349000, 0.0334859000, 0.0478683000, 0.0872373000, 0.2066939000, 0.6079689000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0216259000, 0.0247166000, 0.0341571000, 0.0631135000, 0.1590537000, 0.4780369000, 1.5040114000", \ - "0.0215438000, 0.0246175000, 0.0340273000, 0.0631261000, 0.1591707000, 0.4783848000, 1.5071387000", \ - "0.0214424000, 0.0245867000, 0.0341100000, 0.0630956000, 0.1594652000, 0.4784032000, 1.5061129000", \ - "0.0216282000, 0.0247338000, 0.0341601000, 0.0631250000, 0.1592263000, 0.4773896000, 1.5029049000", \ - "0.0215934000, 0.0247856000, 0.0341396000, 0.0630975000, 0.1595218000, 0.4783399000, 1.5014046000", \ - "0.0215534000, 0.0248901000, 0.0341803000, 0.0630738000, 0.1593588000, 0.4780304000, 1.5084213000", \ - "0.0218317000, 0.0249125000, 0.0342809000, 0.0633162000, 0.1594195000, 0.4785177000, 1.5008732000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4") { - leakage_power () { - value : 0.0144911000; - when : "A"; - } - leakage_power () { - value : 0.0079808000; - when : "!A"; - } - area : 40.038400000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_isowell_tap"; - cell_leakage_power : 0.0112359500; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "LH"; - pg_pin ("LOWLVPWR") { - pg_type : "primary_power"; - voltage_name : "LOWLVPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0060130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059900000; - input_signal_level : "LOWLVPWR"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "LOWLVPWR"; - rise_capacitance : 0.0060360000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0797907000, 0.0780729000, 0.0727833000, 0.0565846000, -6.6622494e-05, -0.189839100, -0.802570400", \ - "0.0775460000, 0.0758344000, 0.0705757000, 0.0544050000, -0.002268600, -0.192008200, -0.804713200", \ - "0.0759150000, 0.0741993000, 0.0689448000, 0.0527300000, -0.003813900, -0.193578700, -0.806245800", \ - "0.0753192000, 0.0736077000, 0.0683194000, 0.0521828000, -0.004466500, -0.194180100, -0.806870600", \ - "0.0758212000, 0.0741312000, 0.0688765000, 0.0527379000, -0.003905500, -0.193610400, -0.806318400", \ - "0.0792385000, 0.0774637000, 0.0719291000, 0.0538679000, -0.002278600, -0.192117700, -0.804825400", \ - "0.0856187000, 0.0838665000, 0.0782567000, 0.0605915000, 0.0022152000, -0.188246700, -0.800677600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0637062000, 0.0656174000, 0.0717484000, 0.0909899000, 0.1508506000, 0.3397356000, 0.9443895000", \ - "0.0640010000, 0.0658937000, 0.0720570000, 0.0912056000, 0.1510680000, 0.3399579000, 0.9445831000", \ - "0.0660818000, 0.0680264000, 0.0741479000, 0.0934032000, 0.1532711000, 0.3420547000, 0.9466033000", \ - "0.0733111000, 0.0752396000, 0.0813393000, 0.1006674000, 0.1605231000, 0.3492777000, 0.9499864000", \ - "0.0862568000, 0.0880885000, 0.0942590000, 0.1134937000, 0.1734379000, 0.3620027000, 0.9657601000", \ - "0.1070928000, 0.1089687000, 0.1149262000, 0.1337109000, 0.1937669000, 0.3824948000, 0.9870090000", \ - "0.1399498000, 0.1418385000, 0.1479349000, 0.1668034000, 0.2272313000, 0.4168397000, 1.0145459000"); - } - } - max_capacitance : 0.5493260000; - max_transition : 1.5061640000; - power_down_function : "(!LOWLVPWR+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2056602000, 0.2093221000, 0.2187873000, 0.2399378000, 0.2844308000, 0.3901554000, 0.6996272000", \ - "0.2095623000, 0.2132329000, 0.2226850000, 0.2438571000, 0.2883118000, 0.3940197000, 0.7032234000", \ - "0.2217868000, 0.2254240000, 0.2349052000, 0.2560541000, 0.3004752000, 0.4062823000, 0.7160011000", \ - "0.2512945000, 0.2549377000, 0.2643814000, 0.2855707000, 0.3300089000, 0.4357450000, 0.7449705000", \ - "0.3035091000, 0.3071598000, 0.3166646000, 0.3378089000, 0.3823400000, 0.4880693000, 0.7976107000", \ - "0.3801201000, 0.3837595000, 0.3932332000, 0.4144686000, 0.4588930000, 0.5646532000, 0.8745027000", \ - "0.4877790000, 0.4914061000, 0.5008643000, 0.5220874000, 0.5666081000, 0.6724314000, 0.9821877000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2141210000, 0.2178976000, 0.2281473000, 0.2545442000, 0.3270422000, 0.5501639000, 1.2637267000", \ - "0.2186971000, 0.2224596000, 0.2327240000, 0.2590798000, 0.3316042000, 0.5546977000, 1.2683612000", \ - "0.2297357000, 0.2335178000, 0.2437692000, 0.2701578000, 0.3426207000, 0.5655215000, 1.2767768000", \ - "0.2552924000, 0.2590954000, 0.2693555000, 0.2957076000, 0.3681113000, 0.5911229000, 1.3037688000", \ - "0.2954612000, 0.2992096000, 0.3094672000, 0.3357929000, 0.4082878000, 0.6312515000, 1.3425259000", \ - "0.3513397000, 0.3551086000, 0.3654016000, 0.3917128000, 0.4640533000, 0.6869756000, 1.3977325000", \ - "0.4252088000, 0.4289956000, 0.4393233000, 0.4656743000, 0.5382184000, 0.7612783000, 1.4712207000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0249629000, 0.0271210000, 0.0333135000, 0.0476612000, 0.0869852000, 0.2061336000, 0.6152011000", \ - "0.0249700000, 0.0270791000, 0.0333061000, 0.0476463000, 0.0867663000, 0.2060785000, 0.6114893000", \ - "0.0247693000, 0.0270005000, 0.0332742000, 0.0478098000, 0.0869741000, 0.2060104000, 0.6128791000", \ - "0.0247362000, 0.0270397000, 0.0330387000, 0.0476937000, 0.0868121000, 0.2060360000, 0.6115025000", \ - "0.0248369000, 0.0270931000, 0.0333518000, 0.0476373000, 0.0868433000, 0.2061105000, 0.6152510000", \ - "0.0247791000, 0.0270126000, 0.0329791000, 0.0476401000, 0.0870690000, 0.2063006000, 0.6145349000", \ - "0.0250000000, 0.0273264000, 0.0333416000, 0.0478832000, 0.0870241000, 0.2067757000, 0.6091743000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0213936000, 0.0244983000, 0.0340167000, 0.0630461000, 0.1593922000, 0.4783278000, 1.5060417000", \ - "0.0214505000, 0.0245501000, 0.0339977000, 0.0630133000, 0.1594617000, 0.4783002000, 1.5058340000", \ - "0.0213755000, 0.0245392000, 0.0340016000, 0.0630697000, 0.1593361000, 0.4777096000, 1.5050308000", \ - "0.0214362000, 0.0246310000, 0.0340885000, 0.0630857000, 0.1590612000, 0.4776475000, 1.5028626000", \ - "0.0214787000, 0.0247157000, 0.0340494000, 0.0630958000, 0.1591792000, 0.4772761000, 1.5061637000", \ - "0.0216541000, 0.0248029000, 0.0341466000, 0.0630789000, 0.1593816000, 0.4781848000, 1.5034956000", \ - "0.0217547000, 0.0248400000, 0.0342068000, 0.0632638000, 0.1593413000, 0.4784539000, 1.5006454000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1") { - leakage_power () { - value : 0.0128890000; - when : "A"; - } - leakage_power () { - value : 0.0040109000; - when : "!A"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_isowell_tap"; - cell_leakage_power : 0.0084499560; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "LH"; - pg_pin ("LOWLVPWR") { - pg_type : "primary_power"; - voltage_name : "LOWLVPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0060050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059730000; - input_signal_level : "LOWLVPWR"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "LOWLVPWR"; - rise_capacitance : 0.0060370000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0666049000, 0.0658134000, 0.0635457000, 0.0562780000, 0.0365992000, -0.013120600, -0.138452500", \ - "0.0644690000, 0.0636949000, 0.0614075000, 0.0540912000, 0.0344440000, -0.015263800, -0.140565600", \ - "0.0629751000, 0.0621587000, 0.0598564000, 0.0525450000, 0.0328883000, -0.016809600, -0.142106900", \ - "0.0623663000, 0.0615883000, 0.0592416000, 0.0519321000, 0.0322813000, -0.017426700, -0.142724500", \ - "0.0630096000, 0.0622510000, 0.0599619000, 0.0526587000, 0.0329894000, -0.016753200, -0.142047100", \ - "0.0659825000, 0.0648242000, 0.0617759000, 0.0539228000, 0.0345602000, -0.015164900, -0.140490000", \ - "0.0707248000, 0.0695242000, 0.0664983000, 0.0586130000, 0.0387076000, -0.011165600, -0.136073400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0475217000, 0.0489019000, 0.0522213000, 0.0602217000, 0.0797921000, 0.1285420000, 0.2519917000", \ - "0.0477674000, 0.0491724000, 0.0524922000, 0.0604602000, 0.0800443000, 0.1287908000, 0.2520179000", \ - "0.0499670000, 0.0513816000, 0.0547056000, 0.0626838000, 0.0822276000, 0.1310830000, 0.2544048000", \ - "0.0572645000, 0.0586698000, 0.0619863000, 0.0699540000, 0.0895391000, 0.1382215000, 0.2626492000", \ - "0.0700112000, 0.0714181000, 0.0747315000, 0.0826870000, 0.1023783000, 0.1515488000, 0.2743575000", \ - "0.0906732000, 0.0919862000, 0.0951994000, 0.1029862000, 0.1225479000, 0.1718330000, 0.2946165000", \ - "0.1218677000, 0.1231835000, 0.1264189000, 0.1344622000, 0.1539224000, 0.2030830000, 0.3259126000"); - } - } - max_capacitance : 0.1281840000; - max_transition : 1.5086440000; - power_down_function : "(!LOWLVPWR+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1454336000, 0.1502444000, 0.1599230000, 0.1792881000, 0.2205151000, 0.3178447000, 0.5623040000", \ - "0.1498165000, 0.1545282000, 0.1642779000, 0.1836485000, 0.2248212000, 0.3222098000, 0.5662897000", \ - "0.1621437000, 0.1668835000, 0.1765968000, 0.1959519000, 0.2371306000, 0.3344602000, 0.5792828000", \ - "0.1916849000, 0.1964699000, 0.2062080000, 0.2255188000, 0.2666709000, 0.3640764000, 0.6083111000", \ - "0.2440808000, 0.2488496000, 0.2585308000, 0.2778545000, 0.3189806000, 0.4163387000, 0.6618725000", \ - "0.3210390000, 0.3258251000, 0.3355264000, 0.3548237000, 0.3958754000, 0.4931787000, 0.7371178000", \ - "0.4295226000, 0.4342778000, 0.4440021000, 0.4632502000, 0.5041575000, 0.6012535000, 0.8454230000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1803053000, 0.1872859000, 0.2039683000, 0.2442935000, 0.3420346000, 0.5862037000, 1.1998861000", \ - "0.1847873000, 0.1918773000, 0.2085875000, 0.2488511000, 0.3466688000, 0.5904134000, 1.2072168000", \ - "0.1960195000, 0.2031061000, 0.2197317000, 0.2598910000, 0.3579575000, 0.6012293000, 1.2179566000", \ - "0.2214491000, 0.2285385000, 0.2452268000, 0.2855073000, 0.3833033000, 0.6268090000, 1.2428505000", \ - "0.2614868000, 0.2685537000, 0.2852445000, 0.3253764000, 0.4232783000, 0.6668365000, 1.2849287000", \ - "0.3167548000, 0.3238535000, 0.3405496000, 0.3808036000, 0.4789521000, 0.7227028000, 1.3356324000", \ - "0.3896770000, 0.3967746000, 0.4136145000, 0.4538913000, 0.5518532000, 0.7965181000, 1.4079680000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0165360000, 0.0204253000, 0.0288802000, 0.0481596000, 0.0954792000, 0.2208392000, 0.5415333000", \ - "0.0164592000, 0.0202663000, 0.0288613000, 0.0478472000, 0.0953405000, 0.2215659000, 0.5402247000", \ - "0.0164776000, 0.0203850000, 0.0287719000, 0.0477472000, 0.0953225000, 0.2210816000, 0.5462443000", \ - "0.0164127000, 0.0200844000, 0.0288120000, 0.0479140000, 0.0952972000, 0.2223169000, 0.5487549000", \ - "0.0163352000, 0.0201703000, 0.0287858000, 0.0480294000, 0.0954190000, 0.2214089000, 0.5416423000", \ - "0.0163487000, 0.0202478000, 0.0286302000, 0.0478362000, 0.0954115000, 0.2200299000, 0.5437479000", \ - "0.0163888000, 0.0200854000, 0.0286532000, 0.0477609000, 0.0953963000, 0.2204814000, 0.5447982000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0230219000, 0.0314853000, 0.0531354000, 0.1084587000, 0.2486104000, 0.6038449000, 1.5029152000", \ - "0.0230119000, 0.0314649000, 0.0531275000, 0.1085167000, 0.2486905000, 0.6042700000, 1.5015430000", \ - "0.0230765000, 0.0314751000, 0.0531056000, 0.1084942000, 0.2488590000, 0.6045440000, 1.5046245000", \ - "0.0229763000, 0.0314395000, 0.0531236000, 0.1084942000, 0.2486406000, 0.6036153000, 1.5086435000", \ - "0.0230431000, 0.0314752000, 0.0530456000, 0.1084945000, 0.2486489000, 0.6062422000, 1.5061571000", \ - "0.0231184000, 0.0315775000, 0.0532433000, 0.1086159000, 0.2480205000, 0.6042531000, 1.5023375000", \ - "0.0231851000, 0.0316166000, 0.0532465000, 0.1086816000, 0.2486097000, 0.6051730000, 1.4927197000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2") { - leakage_power () { - value : 0.0133872000; - when : "A"; - } - leakage_power () { - value : 0.0072536000; - when : "!A"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_isowell_tap"; - cell_leakage_power : 0.0103204400; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "LH"; - pg_pin ("LOWLVPWR") { - pg_type : "primary_power"; - voltage_name : "LOWLVPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0060240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059910000; - input_signal_level : "LOWLVPWR"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "LOWLVPWR"; - rise_capacitance : 0.0060580000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0708861000, 0.0695845000, 0.0659012000, 0.0541761000, 0.0168537000, -0.093218000, -0.413372300", \ - "0.0687871000, 0.0674391000, 0.0638035000, 0.0520076000, 0.0147554000, -0.095329200, -0.415406900", \ - "0.0672417000, 0.0658952000, 0.0622541000, 0.0504734000, 0.0132136000, -0.096820400, -0.416923000", \ - "0.0666430000, 0.0653034000, 0.0615957000, 0.0498517000, 0.0126179000, -0.097439500, -0.417508200", \ - "0.0672716000, 0.0659789000, 0.0623087000, 0.0505973000, 0.0132830000, -0.096776900, -0.416874300", \ - "0.0704367000, 0.0690177000, 0.0647978000, 0.0520554000, 0.0148154000, -0.095283300, -0.415401500", \ - "0.0750829000, 0.0737290000, 0.0694055000, 0.0567403000, 0.0189052000, -0.091416000, -0.411131200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0527431000, 0.0544615000, 0.0592581000, 0.0726866000, 0.1105840000, 0.2194137000, 0.5357092000", \ - "0.0529600000, 0.0546717000, 0.0595159000, 0.0729771000, 0.1108094000, 0.2196121000, 0.5353474000", \ - "0.0551834000, 0.0568737000, 0.0617250000, 0.0751985000, 0.1130607000, 0.2216780000, 0.5374449000", \ - "0.0624359000, 0.0641630000, 0.0690231000, 0.0824457000, 0.1204090000, 0.2290201000, 0.5466834000", \ - "0.0752190000, 0.0769403000, 0.0817941000, 0.0952423000, 0.1330772000, 0.2414650000, 0.5577894000", \ - "0.0962062000, 0.0978574000, 0.1025086000, 0.1155663000, 0.1535504000, 0.2621040000, 0.5801425000", \ - "0.1281662000, 0.1298227000, 0.1344786000, 0.1479504000, 0.1861056000, 0.2953219000, 0.6083393000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5064660000; - power_down_function : "(!LOWLVPWR+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1656818000, 0.1700267000, 0.1797674000, 0.1999426000, 0.2432370000, 0.3511430000, 0.6577444000", \ - "0.1698931000, 0.1741943000, 0.1840267000, 0.2041984000, 0.2474068000, 0.3554081000, 0.6625115000", \ - "0.1821468000, 0.1864475000, 0.1962534000, 0.2164694000, 0.2596479000, 0.3676265000, 0.6750542000", \ - "0.2117047000, 0.2160161000, 0.2257549000, 0.2459366000, 0.2891869000, 0.3971498000, 0.7036843000", \ - "0.2640635000, 0.2683729000, 0.2781266000, 0.2983645000, 0.3415653000, 0.4495477000, 0.7569016000", \ - "0.3408303000, 0.3451016000, 0.3549050000, 0.3751521000, 0.4182957000, 0.5261709000, 0.8323461000", \ - "0.4489303000, 0.4532225000, 0.4629923000, 0.4832019000, 0.5263849000, 0.6343130000, 0.9409301000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1892256000, 0.1940551000, 0.2060603000, 0.2361245000, 0.3178864000, 0.5501006000, 1.2269382000", \ - "0.1937418000, 0.1986070000, 0.2106460000, 0.2406850000, 0.3223779000, 0.5546151000, 1.2313593000", \ - "0.2048614000, 0.2097394000, 0.2217826000, 0.2518157000, 0.3334932000, 0.5656806000, 1.2406761000", \ - "0.2303526000, 0.2352342000, 0.2472616000, 0.2773120000, 0.3587893000, 0.5919903000, 1.2672075000", \ - "0.2704441000, 0.2752863000, 0.2873309000, 0.3173556000, 0.3989953000, 0.6310447000, 1.3102920000", \ - "0.3258553000, 0.3307103000, 0.3427267000, 0.3727220000, 0.4543216000, 0.6872147000, 1.3618640000", \ - "0.3986742000, 0.4035485000, 0.4155883000, 0.4456110000, 0.5271423000, 0.7599988000, 1.4321604000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0182093000, 0.0207846000, 0.0279936000, 0.0450364000, 0.0899370000, 0.2244875000, 0.6304245000", \ - "0.0181774000, 0.0210721000, 0.0278098000, 0.0450028000, 0.0898285000, 0.2255232000, 0.6339016000", \ - "0.0181833000, 0.0210428000, 0.0278925000, 0.0448532000, 0.0896800000, 0.2248550000, 0.6326102000", \ - "0.0179643000, 0.0207910000, 0.0278528000, 0.0448204000, 0.0897010000, 0.2240286000, 0.6353560000", \ - "0.0181142000, 0.0206963000, 0.0276699000, 0.0448511000, 0.0897030000, 0.2250565000, 0.6334347000", \ - "0.0178771000, 0.0209968000, 0.0281010000, 0.0447780000, 0.0899173000, 0.2236002000, 0.6343664000", \ - "0.0179145000, 0.0209401000, 0.0279239000, 0.0447619000, 0.0900414000, 0.2247066000, 0.6293384000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0183134000, 0.0228899000, 0.0357715000, 0.0739162000, 0.1882507000, 0.5241196000, 1.5055052000", \ - "0.0184067000, 0.0229658000, 0.0358560000, 0.0738517000, 0.1882439000, 0.5240270000, 1.5001145000", \ - "0.0183529000, 0.0229959000, 0.0358868000, 0.0738558000, 0.1883477000, 0.5242325000, 1.5008585000", \ - "0.0183724000, 0.0229336000, 0.0358572000, 0.0739361000, 0.1882924000, 0.5242553000, 1.5029662000", \ - "0.0183458000, 0.0229267000, 0.0358401000, 0.0738884000, 0.1884266000, 0.5237600000, 1.5019734000", \ - "0.0184293000, 0.0230186000, 0.0360090000, 0.0740451000, 0.1878661000, 0.5233766000, 1.5064661000", \ - "0.0185322000, 0.0231130000, 0.0361039000, 0.0741334000, 0.1879959000, 0.5242023000, 1.4976365000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4") { - leakage_power () { - value : 0.0144944000; - when : "A"; - } - leakage_power () { - value : 0.0079841000; - when : "!A"; - } - area : 40.038400000; - cell_footprint : "sky130_fd_sc_hd__lsbuf_lh_isowell_tap"; - cell_leakage_power : 0.0112392200; - input_voltage_range(1.2000000000, 2.1000000000); - output_voltage_range(1.2000000000, 2.1000000000); - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - is_level_shifter : "true"; - level_shifter_type : "LH"; - pg_pin ("LOWLVPWR") { - pg_type : "primary_power"; - voltage_name : "LOWLVPWR"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0060060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0059750000; - input_signal_level : "LOWLVPWR"; - level_shifter_data_pin : "true"; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "LOWLVPWR"; - rise_capacitance : 0.0060360000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0796881000, 0.0779843000, 0.0727276000, 0.0565279000, -0.000122500, -0.189958000, -0.802635100", \ - "0.0774666000, 0.0757218000, 0.0704447000, 0.0542858000, -0.002361700, -0.192132200, -0.804825600", \ - "0.0758433000, 0.0741392000, 0.0688807000, 0.0526924000, -0.003908300, -0.193679800, -0.806319600", \ - "0.0752218000, 0.0735076000, 0.0682325000, 0.0520748000, -0.004538000, -0.194273400, -0.806970100", \ - "0.0757976000, 0.0740749000, 0.0688185000, 0.0526614000, -0.003929600, -0.193714300, -0.806373300", \ - "0.0792818000, 0.0775298000, 0.0719787000, 0.0539671000, -0.002223500, -0.192049900, -0.804750700", \ - "0.0851062000, 0.0833545000, 0.0778328000, 0.0601133000, 0.0016586000, -0.188804600, -0.801202700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016061280, 0.0051592920, 0.0165729600, 0.0532365900, 0.1710095000, 0.5493262000"); - values("0.0640650000, 0.0659786000, 0.0720943000, 0.0914163000, 0.1512678000, 0.3400956000, 0.9446605000", \ - "0.0643656000, 0.0662805000, 0.0724543000, 0.0915922000, 0.1516103000, 0.3405103000, 0.9453438000", \ - "0.0665088000, 0.0684216000, 0.0745362000, 0.0937749000, 0.1536548000, 0.3425579000, 0.9469875000", \ - "0.0736745000, 0.0755846000, 0.0817057000, 0.1010241000, 0.1609038000, 0.3496024000, 0.9502577000", \ - "0.0866290000, 0.0884476000, 0.0946244000, 0.1138446000, 0.1738538000, 0.3625213000, 0.9644412000", \ - "0.1075105000, 0.1093174000, 0.1152838000, 0.1340922000, 0.1941229000, 0.3827096000, 0.9871180000", \ - "0.1403876000, 0.1422791000, 0.1482800000, 0.1673379000, 0.2276905000, 0.4172751000, 1.0158406000"); - } - } - max_capacitance : 0.5493260000; - max_transition : 1.5084650000; - power_down_function : "(!LOWLVPWR+!VPWR+VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2060755000, 0.2097138000, 0.2192707000, 0.2404364000, 0.2848684000, 0.3908324000, 0.7003626000", \ - "0.2100680000, 0.2137246000, 0.2231911000, 0.2443848000, 0.2889224000, 0.3947027000, 0.7039048000", \ - "0.2222824000, 0.2259253000, 0.2354072000, 0.2565715000, 0.3010879000, 0.4069608000, 0.7166536000", \ - "0.2518115000, 0.2554494000, 0.2649204000, 0.2861347000, 0.3306315000, 0.4364377000, 0.7455981000", \ - "0.3039795000, 0.3075438000, 0.3170732000, 0.3382676000, 0.3828015000, 0.4886750000, 0.7983650000", \ - "0.3807142000, 0.3843478000, 0.3938182000, 0.4150479000, 0.4595868000, 0.5654165000, 0.8752049000", \ - "0.4875910000, 0.4912336000, 0.5007104000, 0.5219870000, 0.5665324000, 0.6723514000, 0.9815881000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.2143807000, 0.2181544000, 0.2284351000, 0.2547869000, 0.3272089000, 0.5505417000, 1.2615095000", \ - "0.2189175000, 0.2226852000, 0.2329774000, 0.2592957000, 0.3317787000, 0.5547209000, 1.2669551000", \ - "0.2300095000, 0.2337936000, 0.2440511000, 0.2704539000, 0.3429495000, 0.5660716000, 1.2796063000", \ - "0.2555421000, 0.2593131000, 0.2695980000, 0.2959383000, 0.3682959000, 0.5912065000, 1.3042741000", \ - "0.2957888000, 0.2995412000, 0.3098041000, 0.3361137000, 0.4086185000, 0.6319388000, 1.3427295000", \ - "0.3516966000, 0.3554817000, 0.3657781000, 0.3920891000, 0.4645502000, 0.6871304000, 1.3986945000", \ - "0.4256513000, 0.4294426000, 0.4397780000, 0.4661379000, 0.5386768000, 0.7618045000, 1.4719331000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0251520000, 0.0273601000, 0.0334318000, 0.0480748000, 0.0871926000, 0.2060275000, 0.6142861000", \ - "0.0251554000, 0.0272109000, 0.0334334000, 0.0477115000, 0.0868813000, 0.2062336000, 0.6151150000", \ - "0.0249053000, 0.0271376000, 0.0334409000, 0.0476778000, 0.0871459000, 0.2064318000, 0.6122650000", \ - "0.0248914000, 0.0271601000, 0.0333486000, 0.0478424000, 0.0869317000, 0.2061548000, 0.6113295000", \ - "0.0249000000, 0.0273054000, 0.0333731000, 0.0477170000, 0.0871797000, 0.2061205000, 0.6122529000", \ - "0.0249207000, 0.0271850000, 0.0334056000, 0.0478693000, 0.0869977000, 0.2062697000, 0.6139360000", \ - "0.0249484000, 0.0271824000, 0.0336831000, 0.0477934000, 0.0872224000, 0.2066791000, 0.6079633000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016061300, 0.0051592900, 0.0165730000, 0.0532366000, 0.1710100000, 0.5493260000"); - values("0.0216205000, 0.0247035000, 0.0341482000, 0.0631069000, 0.1590907000, 0.4781065000, 1.5048343000", \ - "0.0215317000, 0.0246079000, 0.0340205000, 0.0631137000, 0.1591603000, 0.4784018000, 1.5071107000", \ - "0.0214304000, 0.0245769000, 0.0340945000, 0.0630940000, 0.1594510000, 0.4783522000, 1.5059572000", \ - "0.0216203000, 0.0247246000, 0.0341501000, 0.0631143000, 0.1592088000, 0.4773586000, 1.5028623000", \ - "0.0215886000, 0.0247775000, 0.0341300000, 0.0630833000, 0.1591309000, 0.4784069000, 1.5010205000", \ - "0.0215452000, 0.0248815000, 0.0341704000, 0.0630631000, 0.1593475000, 0.4777187000, 1.5084651000", \ - "0.0218224000, 0.0249030000, 0.0342719000, 0.0632990000, 0.1594367000, 0.4785171000, 1.5013608000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__macro_sparecell") { - area : 36.284800000; - cell_footprint : "sky130_fd_sc_hd__sparecell"; - cell_leakage_power : 0.0448711200; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("LO") { - direction : "output"; - function : "0"; - max_capacitance : 1.8948000000; - max_transition : 1.0000000000; - power_down_function : "!VPWR + VGND"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - } - - cell ("sky130_fd_sc_hd__maj3_1") { - leakage_power () { - value : 0.0035483000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0026247000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0013537000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0034460000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0008273000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0035232000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0004770000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0009219000; - when : "A&B&!C"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__maj3"; - cell_leakage_power : 0.0020902560; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0027450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0026690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040342000, 0.0040236000, 0.0039993000, 0.0039993000, 0.0039992000, 0.0039992000, 0.0039990000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003994600, -0.003988900, -0.003975700, -0.003975200, -0.003974200, -0.003971600, -0.003965800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0028210000; - } - pin ("B") { - capacitance : 0.0025380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0024160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045054000, 0.0045043000, 0.0045017000, 0.0045003000, 0.0044971000, 0.0044897000, 0.0044727000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003420300, -0.003424000, -0.003432300, -0.003424300, -0.003405800, -0.003363300, -0.003265300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026590000; - } - pin ("C") { - capacitance : 0.0030520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0055106000, 0.0055114000, 0.0055134000, 0.0055142000, 0.0055162000, 0.0055207000, 0.0055310000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004979200, -0.004979800, -0.004981100, -0.004977000, -0.004967500, -0.004945600, -0.004895200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0031450000; - } - pin ("X") { - direction : "output"; - function : "(A&B) | (A&C) | (B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0132926000, 0.0124572000, 0.0097667000, 0.0022166000, -0.019508200, -0.078659900, -0.233749100", \ - "0.0132411000, 0.0122223000, 0.0095767000, 0.0020093000, -0.019703400, -0.078719500, -0.233831100", \ - "0.0132378000, 0.0122086000, 0.0095302000, 0.0019741000, -0.019783300, -0.078865500, -0.233958100", \ - "0.0129799000, 0.0119809000, 0.0093184000, 0.0017898000, -0.019978000, -0.078997800, -0.234097400", \ - "0.0128628000, 0.0118505000, 0.0091969000, 0.0016302000, -0.020129300, -0.079210600, -0.234258200", \ - "0.0128869000, 0.0118583000, 0.0092018000, 0.0015735000, -0.020224500, -0.079324300, -0.234375700", \ - "0.0156791000, 0.0143120000, 0.0108533000, 0.0020184000, -0.020462500, -0.079329800, -0.234314000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0122429000, 0.0136382000, 0.0172128000, 0.0262045000, 0.0491443000, 0.1084087000, 0.2620052000", \ - "0.0121960000, 0.0135840000, 0.0171178000, 0.0260839000, 0.0490219000, 0.1087494000, 0.2629636000", \ - "0.0120611000, 0.0134553000, 0.0170051000, 0.0259813000, 0.0489545000, 0.1086384000, 0.2617958000", \ - "0.0119968000, 0.0133918000, 0.0169446000, 0.0258885000, 0.0487889000, 0.1084551000, 0.2628653000", \ - "0.0120107000, 0.0133936000, 0.0168064000, 0.0257296000, 0.0486299000, 0.1083665000, 0.2627013000", \ - "0.0120962000, 0.0134321000, 0.0168344000, 0.0254542000, 0.0484056000, 0.1073918000, 0.2612873000", \ - "0.0124372000, 0.0136879000, 0.0170016000, 0.0259162000, 0.0487427000, 0.1080301000, 0.2605413000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0102276000, 0.0092675000, 0.0067732000, -0.000641900, -0.022017500, -0.080943900, -0.236062900", \ - "0.0100277000, 0.0091611000, 0.0066159000, -0.000825800, -0.022245700, -0.081170400, -0.236286600", \ - "0.0096904000, 0.0087411000, 0.0062203000, -0.001176500, -0.022584900, -0.081545600, -0.236664400", \ - "0.0093549000, 0.0084047000, 0.0058346000, -0.001592400, -0.023026700, -0.081989300, -0.237076700", \ - "0.0090425000, 0.0080901000, 0.0055749000, -0.001838300, -0.023309700, -0.082257800, -0.237334200", \ - "0.0092108000, 0.0082265000, 0.0056124000, -0.001824000, -0.023379000, -0.082304000, -0.237329500", \ - "0.0124000000, 0.0109944000, 0.0075215000, -0.001118800, -0.023161900, -0.081989100, -0.237031400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0121218000, 0.0135357000, 0.0171231000, 0.0260964000, 0.0490272000, 0.1086280000, 0.2629398000", \ - "0.0121566000, 0.0135666000, 0.0171408000, 0.0261218000, 0.0490487000, 0.1082044000, 0.2618437000", \ - "0.0121013000, 0.0135110000, 0.0170855000, 0.0260630000, 0.0489427000, 0.1082194000, 0.2618927000", \ - "0.0119807000, 0.0133757000, 0.0168916000, 0.0258154000, 0.0487064000, 0.1083959000, 0.2628862000", \ - "0.0116899000, 0.0130593000, 0.0165246000, 0.0254687000, 0.0483320000, 0.1076824000, 0.2623024000", \ - "0.0117204000, 0.0130196000, 0.0163970000, 0.0249865000, 0.0479838000, 0.1068707000, 0.2623698000", \ - "0.0119625000, 0.0133019000, 0.0165254000, 0.0253164000, 0.0481568000, 0.1077992000, 0.2600461000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0130259000, 0.0120670000, 0.0095206000, 0.0019764000, -0.019870000, -0.078916200, -0.234041700", \ - "0.0128847000, 0.0120599000, 0.0093550000, 0.0017956000, -0.019927900, -0.079104200, -0.234243200", \ - "0.0126072000, 0.0115809000, 0.0089599000, 0.0013928000, -0.020339600, -0.079471400, -0.234575700", \ - "0.0121875000, 0.0112188000, 0.0085793000, 0.0011252000, -0.020682000, -0.079847800, -0.234968100", \ - "0.0119070000, 0.0109131000, 0.0082598000, 0.0006939000, -0.021073600, -0.080173300, -0.235289000", \ - "0.0119540000, 0.0108976000, 0.0082443000, 0.0005853000, -0.021209400, -0.080299900, -0.235328200", \ - "0.0152638000, 0.0138535000, 0.0103218000, 0.0013715000, -0.020864100, -0.079853100, -0.234901100"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0131669000, 0.0145365000, 0.0180819000, 0.0271184000, 0.0499737000, 0.1092417000, 0.2639394000", \ - "0.0131517000, 0.0145180000, 0.0180609000, 0.0270863000, 0.0499447000, 0.1091540000, 0.2638335000", \ - "0.0130928000, 0.0144641000, 0.0180102000, 0.0269903000, 0.0499120000, 0.1090543000, 0.2626432000", \ - "0.0129250000, 0.0143197000, 0.0178614000, 0.0267961000, 0.0497183000, 0.1088382000, 0.2624961000", \ - "0.0127852000, 0.0141117000, 0.0175671000, 0.0265077000, 0.0495535000, 0.1086993000, 0.2624042000", \ - "0.0128437000, 0.0141560000, 0.0175131000, 0.0260513000, 0.0489540000, 0.1085053000, 0.2631176000", \ - "0.0131605000, 0.0143994000, 0.0177607000, 0.0264983000, 0.0492521000, 0.1084079000, 0.2623914000"); - } - } - max_capacitance : 0.1556500000; - max_transition : 1.5002550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3016484000, 0.3118367000, 0.3321805000, 0.3701004000, 0.4394409000, 0.5785986000, 0.9008560000", \ - "0.3064639000, 0.3166472000, 0.3368945000, 0.3750846000, 0.4450725000, 0.5830179000, 0.9051398000", \ - "0.3179254000, 0.3279344000, 0.3484217000, 0.3866463000, 0.4563768000, 0.5953187000, 0.9174319000", \ - "0.3433009000, 0.3536937000, 0.3739846000, 0.4121163000, 0.4819057000, 0.6200050000, 0.9423099000", \ - "0.4042450000, 0.4144139000, 0.4347368000, 0.4728805000, 0.5425634000, 0.6814159000, 1.0039487000", \ - "0.5431949000, 0.5532890000, 0.5739760000, 0.6123387000, 0.6818495000, 0.8210365000, 1.1435305000", \ - "0.8018756000, 0.8138221000, 0.8380135000, 0.8819372000, 0.9585482000, 1.1039062000, 1.4290912000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1140358000, 0.1219552000, 0.1396795000, 0.1794093000, 0.2761132000, 0.5234967000, 1.1640600000", \ - "0.1183662000, 0.1262421000, 0.1439162000, 0.1836190000, 0.2803173000, 0.5277237000, 1.1710565000", \ - "0.1273191000, 0.1352260000, 0.1529435000, 0.1926942000, 0.2893596000, 0.5380013000, 1.1778644000", \ - "0.1480436000, 0.1559204000, 0.1735552000, 0.2132049000, 0.3097585000, 0.5580237000, 1.2007926000", \ - "0.1883430000, 0.1965482000, 0.2146927000, 0.2547398000, 0.3513798000, 0.5994569000, 1.2423738000", \ - "0.2465868000, 0.2558118000, 0.2755088000, 0.3169918000, 0.4140051000, 0.6617959000, 1.3022513000", \ - "0.3063012000, 0.3180469000, 0.3413621000, 0.3869289000, 0.4852956000, 0.7329634000, 1.3738887000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0473893000, 0.0545107000, 0.0662675000, 0.0929048000, 0.1531142000, 0.2994363000, 0.7060387000", \ - "0.0481168000, 0.0542661000, 0.0662764000, 0.0925447000, 0.1520157000, 0.2989284000, 0.7040363000", \ - "0.0474585000, 0.0536141000, 0.0661007000, 0.0931491000, 0.1517107000, 0.2983377000, 0.7047428000", \ - "0.0478157000, 0.0539966000, 0.0662539000, 0.0938077000, 0.1527351000, 0.2994347000, 0.7059666000", \ - "0.0480579000, 0.0542995000, 0.0662965000, 0.0923674000, 0.1524735000, 0.2993197000, 0.7065399000", \ - "0.0495089000, 0.0556039000, 0.0683762000, 0.0947409000, 0.1538579000, 0.2993190000, 0.7079706000", \ - "0.0616767000, 0.0684713000, 0.0821508000, 0.1086406000, 0.1682375000, 0.3085084000, 0.7088278000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0304174000, 0.0375743000, 0.0560166000, 0.1046287000, 0.2366029000, 0.5868928000, 1.4935750000", \ - "0.0302568000, 0.0376291000, 0.0560468000, 0.1045276000, 0.2360830000, 0.5875579000, 1.4961211000", \ - "0.0304203000, 0.0375383000, 0.0559598000, 0.1045018000, 0.2366541000, 0.5871410000, 1.4969651000", \ - "0.0302239000, 0.0374465000, 0.0559403000, 0.1044963000, 0.2359364000, 0.5865125000, 1.4975118000", \ - "0.0324699000, 0.0397847000, 0.0579542000, 0.1055106000, 0.2360090000, 0.5871599000, 1.4952566000", \ - "0.0380993000, 0.0457617000, 0.0630886000, 0.1089506000, 0.2376670000, 0.5857771000, 1.4933438000", \ - "0.0507889000, 0.0587030000, 0.0753971000, 0.1180719000, 0.2410689000, 0.5892566000, 1.4948777000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.2915934000, 0.3020980000, 0.3236215000, 0.3649302000, 0.4400746000, 0.5863943000, 0.9126191000", \ - "0.2927780000, 0.3030350000, 0.3246069000, 0.3656445000, 0.4414836000, 0.5876075000, 0.9138823000", \ - "0.2983772000, 0.3086987000, 0.3302571000, 0.3709253000, 0.4467679000, 0.5928917000, 0.9191000000", \ - "0.3209695000, 0.3313530000, 0.3526096000, 0.3925914000, 0.4681525000, 0.6143482000, 0.9406042000", \ - "0.3836559000, 0.3940449000, 0.4155878000, 0.4566594000, 0.5321609000, 0.6780311000, 1.0042684000", \ - "0.5442865000, 0.5547424000, 0.5763527000, 0.6173037000, 0.6929424000, 0.8389837000, 1.1654494000", \ - "0.8288428000, 0.8419407000, 0.8685349000, 0.9148146000, 0.9967855000, 1.1520546000, 1.4835366000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1064958000, 0.1147213000, 0.1330062000, 0.1734156000, 0.2702339000, 0.5182947000, 1.1608748000", \ - "0.1112446000, 0.1194055000, 0.1376562000, 0.1780369000, 0.2748616000, 0.5217753000, 1.1627583000", \ - "0.1216315000, 0.1297880000, 0.1480338000, 0.1884164000, 0.2850499000, 0.5323545000, 1.1723985000", \ - "0.1453508000, 0.1535117000, 0.1721529000, 0.2122784000, 0.3090240000, 0.5570395000, 1.1968215000", \ - "0.1874911000, 0.1962901000, 0.2154787000, 0.2569870000, 0.3539097000, 0.6007913000, 1.2447692000", \ - "0.2386067000, 0.2483504000, 0.2691673000, 0.3123881000, 0.4109007000, 0.6598085000, 1.3015251000", \ - "0.2792728000, 0.2917578000, 0.3157065000, 0.3642893000, 0.4637969000, 0.7120299000, 1.3551673000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0486412000, 0.0554646000, 0.0703163000, 0.0998297000, 0.1637925000, 0.3108373000, 0.7082240000", \ - "0.0484575000, 0.0552114000, 0.0706864000, 0.1002094000, 0.1636239000, 0.3100284000, 0.7094452000", \ - "0.0484861000, 0.0550476000, 0.0703092000, 0.1007798000, 0.1634314000, 0.3100377000, 0.7093059000", \ - "0.0482902000, 0.0549729000, 0.0702170000, 0.0993775000, 0.1631472000, 0.3099645000, 0.7098749000", \ - "0.0485754000, 0.0549063000, 0.0707299000, 0.0994050000, 0.1615754000, 0.3105715000, 0.7087378000", \ - "0.0506151000, 0.0569518000, 0.0709248000, 0.1012425000, 0.1617908000, 0.3104842000, 0.7083136000", \ - "0.0711980000, 0.0774419000, 0.0915065000, 0.1219581000, 0.1813047000, 0.3262849000, 0.7167469000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0313804000, 0.0386515000, 0.0571045000, 0.1052510000, 0.2364645000, 0.5855851000, 1.4980382000", \ - "0.0314202000, 0.0386984000, 0.0570662000, 0.1052412000, 0.2365121000, 0.5870645000, 1.4956593000", \ - "0.0313785000, 0.0386423000, 0.0569964000, 0.1051516000, 0.2362793000, 0.5844297000, 1.4975747000", \ - "0.0312928000, 0.0386881000, 0.0570922000, 0.1051089000, 0.2356285000, 0.5864381000, 1.4981195000", \ - "0.0350787000, 0.0425791000, 0.0608960000, 0.1079561000, 0.2368091000, 0.5872896000, 1.4979155000", \ - "0.0415593000, 0.0490121000, 0.0670259000, 0.1125334000, 0.2401900000, 0.5861736000, 1.4974619000", \ - "0.0568465000, 0.0647021000, 0.0828974000, 0.1253747000, 0.2443692000, 0.5893093000, 1.4931276000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3137986000, 0.3241813000, 0.3445111000, 0.3820732000, 0.4528608000, 0.5907687000, 0.9130170000", \ - "0.3158657000, 0.3262165000, 0.3467733000, 0.3847815000, 0.4542925000, 0.5933260000, 0.9154968000", \ - "0.3224528000, 0.3327056000, 0.3532295000, 0.3912366000, 0.4612262000, 0.5999605000, 0.9221120000", \ - "0.3435370000, 0.3536416000, 0.3740845000, 0.4117799000, 0.4817146000, 0.6207013000, 0.9428028000", \ - "0.4052975000, 0.4152621000, 0.4355718000, 0.4736140000, 0.5432810000, 0.6822585000, 1.0045601000", \ - "0.5585589000, 0.5686565000, 0.5892698000, 0.6276445000, 0.6975596000, 0.8366789000, 1.1590174000", \ - "0.8351023000, 0.8480625000, 0.8740279000, 0.9195403000, 0.9964846000, 1.1414805000, 1.4668233000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1181419000, 0.1259728000, 0.1436783000, 0.1834850000, 0.2797703000, 0.5266769000, 1.1685297000", \ - "0.1226562000, 0.1304799000, 0.1481738000, 0.1879920000, 0.2842727000, 0.5309135000, 1.1733889000", \ - "0.1332816000, 0.1411186000, 0.1588212000, 0.1985944000, 0.2951217000, 0.5420845000, 1.1827619000", \ - "0.1579712000, 0.1658560000, 0.1834997000, 0.2230804000, 0.3196696000, 0.5666957000, 1.2076954000", \ - "0.2075671000, 0.2155544000, 0.2335177000, 0.2736583000, 0.3700809000, 0.6176450000, 1.2578824000", \ - "0.2731275000, 0.2826196000, 0.3020532000, 0.3436321000, 0.4406367000, 0.6882360000, 1.3326884000", \ - "0.3383276000, 0.3509612000, 0.3753976000, 0.4210922000, 0.5187639000, 0.7675484000, 1.4080992000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0476280000, 0.0537913000, 0.0665214000, 0.0931458000, 0.1521774000, 0.2996263000, 0.7044305000", \ - "0.0476199000, 0.0536399000, 0.0660867000, 0.0938049000, 0.1528754000, 0.2996628000, 0.7065006000", \ - "0.0481309000, 0.0533727000, 0.0665058000, 0.0924152000, 0.1519295000, 0.2986687000, 0.7049655000", \ - "0.0473500000, 0.0537423000, 0.0661779000, 0.0929077000, 0.1526360000, 0.2985583000, 0.7075135000", \ - "0.0477153000, 0.0536641000, 0.0663543000, 0.0936969000, 0.1518464000, 0.2987104000, 0.7047822000", \ - "0.0494480000, 0.0552110000, 0.0672676000, 0.0941042000, 0.1524399000, 0.2989211000, 0.7030059000", \ - "0.0694366000, 0.0764125000, 0.0893077000, 0.1140959000, 0.1704010000, 0.3100190000, 0.7089461000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0301994000, 0.0377104000, 0.0560296000, 0.1043429000, 0.2367284000, 0.5862979000, 1.5002262000", \ - "0.0302207000, 0.0376911000, 0.0560066000, 0.1043717000, 0.2366423000, 0.5870597000, 1.5002550000", \ - "0.0302449000, 0.0376328000, 0.0559264000, 0.1045693000, 0.2365172000, 0.5872851000, 1.4933720000", \ - "0.0302491000, 0.0374262000, 0.0558819000, 0.1044699000, 0.2366930000, 0.5873265000, 1.4953389000", \ - "0.0329078000, 0.0401927000, 0.0579513000, 0.1054849000, 0.2363589000, 0.5849224000, 1.4978737000", \ - "0.0402610000, 0.0472697000, 0.0643883000, 0.1092737000, 0.2383006000, 0.5852863000, 1.4991194000", \ - "0.0556595000, 0.0632511000, 0.0792187000, 0.1206129000, 0.2416385000, 0.5894769000, 1.4927970000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__maj3_2") { - leakage_power () { - value : 0.0050786000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0041376000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0023887000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0049819000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0013468000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0050482000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0008789000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0015400000; - when : "A&B&!C"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__maj3"; - cell_leakage_power : 0.0031750860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0032460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053724000, 0.0053775000, 0.0053892000, 0.0053895000, 0.0053900000, 0.0053913000, 0.0053943000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005371800, -0.005367900, -0.005358700, -0.005359800, -0.005362300, -0.005368200, -0.005381800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033650000; - } - pin ("B") { - capacitance : 0.0029880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0028190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0060047000, 0.0060027000, 0.0059981000, 0.0059980000, 0.0059980000, 0.0059977000, 0.0059973000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004918000, -0.004922300, -0.004932000, -0.004923100, -0.004902700, -0.004855600, -0.004746900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0031570000; - } - pin ("C") { - capacitance : 0.0037180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0070634000, 0.0070535000, 0.0070306000, 0.0070320000, 0.0070352000, 0.0070428000, 0.0070601000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006483800, -0.006484500, -0.006486200, -0.006483000, -0.006475700, -0.006458800, -0.006419800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0038630000; - } - pin ("X") { - direction : "output"; - function : "(A&B) | (A&C) | (B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0169070000, 0.0153135000, 0.0115981000, 0.0003027000, -0.035452200, -0.145446300, -0.469377200", \ - "0.0168828000, 0.0153249000, 0.0115090000, 0.0002582000, -0.035543100, -0.145519000, -0.469435600", \ - "0.0170174000, 0.0154799000, 0.0115644000, 0.0002740000, -0.035593500, -0.145683600, -0.469609700", \ - "0.0166729000, 0.0150870000, 0.0112894000, 0.0001043000, -0.035750300, -0.145868700, -0.469758400", \ - "0.0164692000, 0.0148887000, 0.0110905000, -0.000108300, -0.035971700, -0.145988800, -0.469902300", \ - "0.0165387000, 0.0149409000, 0.0110627000, -0.000274600, -0.036147600, -0.146204900, -0.470029600", \ - "0.0217588000, 0.0199968000, 0.0151712000, 0.0018063000, -0.035990200, -0.146261500, -0.469991900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0186725000, 0.0203508000, 0.0251498000, 0.0386059000, 0.0769693000, 0.1876841000, 0.5088402000", \ - "0.0185435000, 0.0201777000, 0.0249543000, 0.0383948000, 0.0768392000, 0.1875061000, 0.5082813000", \ - "0.0183821000, 0.0200387000, 0.0247186000, 0.0382739000, 0.0766468000, 0.1881953000, 0.5104341000", \ - "0.0182508000, 0.0198608000, 0.0246193000, 0.0381830000, 0.0765320000, 0.1870644000, 0.5075719000", \ - "0.0183631000, 0.0199540000, 0.0245934000, 0.0380821000, 0.0763907000, 0.1870922000, 0.5103144000", \ - "0.0188566000, 0.0203905000, 0.0249209000, 0.0378765000, 0.0760990000, 0.1864583000, 0.5094592000", \ - "0.0195670000, 0.0210248000, 0.0254530000, 0.0387059000, 0.0766677000, 0.1874550000, 0.5091214000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0128967000, 0.0114137000, 0.0077283000, -0.003249600, -0.038531200, -0.148280500, -0.472156500", \ - "0.0127767000, 0.0112653000, 0.0076123000, -0.003335900, -0.038698800, -0.148416100, -0.472308400", \ - "0.0125436000, 0.0109857000, 0.0072813000, -0.003651000, -0.038956600, -0.148704000, -0.472614300", \ - "0.0121450000, 0.0106163000, 0.0069138000, -0.004013400, -0.039370600, -0.149067800, -0.472964300", \ - "0.0118471000, 0.0103140000, 0.0066876000, -0.004389700, -0.039857000, -0.149531000, -0.473382000", \ - "0.0121384000, 0.0105538000, 0.0067246000, -0.004159000, -0.039812600, -0.149578700, -0.473349600", \ - "0.0185246000, 0.0166653000, 0.0116654000, -0.002179100, -0.039945000, -0.149163900, -0.472948500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0184718000, 0.0201242000, 0.0249444000, 0.0385030000, 0.0769218000, 0.1875091000, 0.5081586000", \ - "0.0184708000, 0.0201202000, 0.0249289000, 0.0385175000, 0.0769665000, 0.1874986000, 0.5086035000", \ - "0.0184392000, 0.0200452000, 0.0248777000, 0.0384830000, 0.0768530000, 0.1875516000, 0.5084360000", \ - "0.0182001000, 0.0198557000, 0.0246459000, 0.0383014000, 0.0766312000, 0.1873045000, 0.5080339000", \ - "0.0179974000, 0.0195807000, 0.0243068000, 0.0378382000, 0.0760423000, 0.1867648000, 0.5075030000", \ - "0.0184571000, 0.0199545000, 0.0244269000, 0.0371307000, 0.0752629000, 0.1858151000, 0.5071657000", \ - "0.0190848000, 0.0205315000, 0.0248534000, 0.0378648000, 0.0757888000, 0.1863242000, 0.5045472000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0160850000, 0.0144994000, 0.0109245000, -0.000414700, -0.036082600, -0.146354100, -0.470384600", \ - "0.0159481000, 0.0143689000, 0.0108358000, -0.000504900, -0.036136100, -0.146483200, -0.470502800", \ - "0.0156769000, 0.0141064000, 0.0103831000, -0.000655600, -0.036531100, -0.146802800, -0.470761900", \ - "0.0152787000, 0.0137233000, 0.0100601000, -0.001200700, -0.037058100, -0.147234100, -0.471212900", \ - "0.0149369000, 0.0133656000, 0.0095301000, -0.001610700, -0.037527600, -0.147653000, -0.471572700", \ - "0.0152811000, 0.0136524000, 0.0097038000, -0.001698300, -0.037789300, -0.147897900, -0.471688100", \ - "0.0213019000, 0.0194385000, 0.0144845000, 0.0009324000, -0.037521700, -0.147221000, -0.470939800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0205611000, 0.0222003000, 0.0268600000, 0.0404302000, 0.0788513000, 0.1894318000, 0.5124653000", \ - "0.0205313000, 0.0221581000, 0.0268302000, 0.0403784000, 0.0788387000, 0.1895188000, 0.5104035000", \ - "0.0204662000, 0.0220975000, 0.0268561000, 0.0402876000, 0.0787079000, 0.1894061000, 0.5102081000", \ - "0.0201985000, 0.0218327000, 0.0265186000, 0.0400591000, 0.0784174000, 0.1890455000, 0.5121375000", \ - "0.0200285000, 0.0216862000, 0.0263845000, 0.0397234000, 0.0779320000, 0.1886667000, 0.5118194000", \ - "0.0202664000, 0.0217930000, 0.0262430000, 0.0391477000, 0.0771339000, 0.1878062000, 0.5087693000", \ - "0.0210943000, 0.0225552000, 0.0269256000, 0.0400201000, 0.0776792000, 0.1882039000, 0.5069037000"); - } - } - max_capacitance : 0.3048800000; - max_transition : 1.5026130000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.2642092000, 0.2721371000, 0.2897725000, 0.3240865000, 0.3883928000, 0.5191151000, 0.8451752000", \ - "0.2698049000, 0.2777557000, 0.2952707000, 0.3295574000, 0.3939808000, 0.5245878000, 0.8505586000", \ - "0.2824599000, 0.2904163000, 0.3079401000, 0.3421811000, 0.4065654000, 0.5380646000, 0.8641244000", \ - "0.3095033000, 0.3174515000, 0.3349793000, 0.3694415000, 0.4336907000, 0.5650704000, 0.8911389000", \ - "0.3711287000, 0.3790672000, 0.3966306000, 0.4310160000, 0.4951516000, 0.6269011000, 0.9527834000", \ - "0.5089559000, 0.5171976000, 0.5353774000, 0.5703231000, 0.6349876000, 0.7668096000, 1.0928586000", \ - "0.7589934000, 0.7686762000, 0.7900189000, 0.8307750000, 0.9035088000, 1.0437796000, 1.3735261000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1410052000, 0.1481218000, 0.1645541000, 0.2004032000, 0.2858425000, 0.5210858000, 1.2010741000", \ - "0.1452791000, 0.1523956000, 0.1687208000, 0.2045197000, 0.2900099000, 0.5258864000, 1.2036719000", \ - "0.1545255000, 0.1616156000, 0.1779057000, 0.2138376000, 0.2993853000, 0.5348100000, 1.2152498000", \ - "0.1754539000, 0.1825557000, 0.1989006000, 0.2348343000, 0.3202033000, 0.5548876000, 1.2342509000", \ - "0.2205923000, 0.2279223000, 0.2443600000, 0.2804682000, 0.3658226000, 0.6006547000, 1.2796865000", \ - "0.2942253000, 0.3025151000, 0.3208403000, 0.3593223000, 0.4464418000, 0.6815269000, 1.3640039000", \ - "0.3845269000, 0.3951096000, 0.4178768000, 0.4617683000, 0.5526377000, 0.7878563000, 1.4664263000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0399146000, 0.0442814000, 0.0548612000, 0.0777420000, 0.1265066000, 0.2598839000, 0.6662684000", \ - "0.0397608000, 0.0444850000, 0.0548178000, 0.0767062000, 0.1263633000, 0.2604281000, 0.6660028000", \ - "0.0398257000, 0.0447186000, 0.0548304000, 0.0779414000, 0.1279491000, 0.2594723000, 0.6659534000", \ - "0.0396285000, 0.0446040000, 0.0547460000, 0.0774135000, 0.1274635000, 0.2593972000, 0.6663071000", \ - "0.0397264000, 0.0447081000, 0.0547954000, 0.0775183000, 0.1268320000, 0.2601840000, 0.6659634000", \ - "0.0430706000, 0.0474216000, 0.0577811000, 0.0789434000, 0.1296295000, 0.2603442000, 0.6665001000", \ - "0.0553375000, 0.0602379000, 0.0720228000, 0.0957505000, 0.1451597000, 0.2732076000, 0.6697429000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0277072000, 0.0334554000, 0.0471530000, 0.0838673000, 0.1923001000, 0.5248416000, 1.5015226000", \ - "0.0277555000, 0.0332953000, 0.0470135000, 0.0837232000, 0.1924994000, 0.5243357000, 1.4989006000", \ - "0.0278193000, 0.0333561000, 0.0473353000, 0.0836439000, 0.1924890000, 0.5248877000, 1.5024314000", \ - "0.0278465000, 0.0333542000, 0.0471263000, 0.0837578000, 0.1920953000, 0.5240959000, 1.4970353000", \ - "0.0289581000, 0.0341974000, 0.0479382000, 0.0843759000, 0.1926502000, 0.5246165000, 1.4996120000", \ - "0.0341140000, 0.0397565000, 0.0542594000, 0.0894098000, 0.1946992000, 0.5247236000, 1.4971266000", \ - "0.0458240000, 0.0523136000, 0.0675277000, 0.1016173000, 0.2017519000, 0.5265322000, 1.4984718000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.2575334000, 0.2657542000, 0.2841181000, 0.3210386000, 0.3910551000, 0.5316216000, 0.8636409000", \ - "0.2609318000, 0.2690896000, 0.2875018000, 0.3240162000, 0.3945025000, 0.5349549000, 0.8669643000", \ - "0.2693707000, 0.2775113000, 0.2959007000, 0.3327662000, 0.4027586000, 0.5432352000, 0.8753295000", \ - "0.2930916000, 0.3012297000, 0.3196615000, 0.3573252000, 0.4277529000, 0.5680908000, 0.8999898000", \ - "0.3587468000, 0.3668280000, 0.3851222000, 0.4216589000, 0.4920246000, 0.6320637000, 0.9640092000", \ - "0.5136361000, 0.5219105000, 0.5407637000, 0.5785561000, 0.6492053000, 0.7896760000, 1.1217238000", \ - "0.7859817000, 0.7965323000, 0.8197646000, 0.8641215000, 0.9407866000, 1.0906468000, 1.4300078000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1299857000, 0.1373411000, 0.1541534000, 0.1906266000, 0.2765735000, 0.5115350000, 1.1910616000", \ - "0.1348971000, 0.1422725000, 0.1590253000, 0.1955235000, 0.2816011000, 0.5171631000, 1.1954646000", \ - "0.1453502000, 0.1526206000, 0.1694140000, 0.2059183000, 0.2918479000, 0.5267521000, 1.2062227000", \ - "0.1688396000, 0.1762375000, 0.1930155000, 0.2294772000, 0.3152489000, 0.5502686000, 1.2297828000", \ - "0.2199469000, 0.2276834000, 0.2451071000, 0.2820636000, 0.3679363000, 0.6028946000, 1.2825661000", \ - "0.2904466000, 0.2992969000, 0.3189906000, 0.3591539000, 0.4481019000, 0.6841571000, 1.3635488000", \ - "0.3635695000, 0.3751509000, 0.3996358000, 0.4470333000, 0.5411722000, 0.7778440000, 1.4575992000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0409266000, 0.0460761000, 0.0576653000, 0.0833028000, 0.1379976000, 0.2732310000, 0.6721394000", \ - "0.0408962000, 0.0461016000, 0.0576188000, 0.0841726000, 0.1376706000, 0.2731835000, 0.6714042000", \ - "0.0411197000, 0.0460181000, 0.0577240000, 0.0832895000, 0.1377875000, 0.2732373000, 0.6717649000", \ - "0.0410241000, 0.0457453000, 0.0578346000, 0.0839598000, 0.1372460000, 0.2730292000, 0.6717961000", \ - "0.0406692000, 0.0459645000, 0.0581500000, 0.0831040000, 0.1371775000, 0.2731752000, 0.6718739000", \ - "0.0447031000, 0.0497707000, 0.0607007000, 0.0858155000, 0.1397804000, 0.2737922000, 0.6705540000", \ - "0.0642894000, 0.0699748000, 0.0829922000, 0.1069422000, 0.1606529000, 0.2919757000, 0.6800161000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0285720000, 0.0340740000, 0.0478112000, 0.0843761000, 0.1924922000, 0.5242242000, 1.4989101000", \ - "0.0283996000, 0.0339270000, 0.0477267000, 0.0843884000, 0.1923620000, 0.5235991000, 1.5011076000", \ - "0.0284171000, 0.0338698000, 0.0478921000, 0.0842026000, 0.1925772000, 0.5239514000, 1.5002907000", \ - "0.0282894000, 0.0339674000, 0.0478530000, 0.0844528000, 0.1925703000, 0.5240405000, 1.4998395000", \ - "0.0308498000, 0.0362534000, 0.0499065000, 0.0857703000, 0.1928171000, 0.5240296000, 1.4987874000", \ - "0.0380201000, 0.0439770000, 0.0582546000, 0.0935760000, 0.1979475000, 0.5239076000, 1.4999185000", \ - "0.0527715000, 0.0600475000, 0.0756954000, 0.1093384000, 0.2067021000, 0.5279411000, 1.4985386000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.2708986000, 0.2788828000, 0.2965045000, 0.3308530000, 0.3948020000, 0.5262851000, 0.8525378000", \ - "0.2741681000, 0.2821358000, 0.2997979000, 0.3340926000, 0.3979280000, 0.5295546000, 0.8557421000", \ - "0.2827407000, 0.2906908000, 0.3082967000, 0.3423506000, 0.4063254000, 0.5379758000, 0.8644067000", \ - "0.3055522000, 0.3134938000, 0.3310012000, 0.3653563000, 0.4296282000, 0.5611946000, 0.8872643000", \ - "0.3669538000, 0.3749057000, 0.3924659000, 0.4267850000, 0.4910476000, 0.6224445000, 0.9485579000", \ - "0.5160197000, 0.5242801000, 0.5425477000, 0.5773350000, 0.6421317000, 0.7742265000, 1.1001610000", \ - "0.7682389000, 0.7786968000, 0.8018642000, 0.8455847000, 0.9208870000, 1.0610473000, 1.3919701000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1464631000, 0.1535850000, 0.1698844000, 0.2057932000, 0.2913165000, 0.5269143000, 1.2073675000", \ - "0.1512101000, 0.1583251000, 0.1746262000, 0.2104653000, 0.2959558000, 0.5309113000, 1.2105413000", \ - "0.1617863000, 0.1689219000, 0.1852724000, 0.2210383000, 0.3065841000, 0.5414507000, 1.2210079000", \ - "0.1862108000, 0.1933649000, 0.2096042000, 0.2454398000, 0.3309634000, 0.5662096000, 1.2458257000", \ - "0.2416197000, 0.2487659000, 0.2652373000, 0.3016390000, 0.3869233000, 0.6218203000, 1.3015613000", \ - "0.3281212000, 0.3368490000, 0.3559087000, 0.3942499000, 0.4810821000, 0.7169230000, 1.3947318000", \ - "0.4281013000, 0.4393167000, 0.4636847000, 0.5099824000, 0.6010384000, 0.8363413000, 1.5158454000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0397150000, 0.0445817000, 0.0548911000, 0.0779452000, 0.1277615000, 0.2598306000, 0.6701901000", \ - "0.0398308000, 0.0447241000, 0.0548418000, 0.0779269000, 0.1279164000, 0.2597655000, 0.6696827000", \ - "0.0399000000, 0.0446937000, 0.0548904000, 0.0772812000, 0.1279713000, 0.2594200000, 0.6696116000", \ - "0.0396318000, 0.0446786000, 0.0549205000, 0.0779633000, 0.1268185000, 0.2595394000, 0.6659745000", \ - "0.0398065000, 0.0446045000, 0.0547501000, 0.0769010000, 0.1278803000, 0.2595948000, 0.6658747000", \ - "0.0438300000, 0.0482895000, 0.0583383000, 0.0794093000, 0.1282469000, 0.2600988000, 0.6665188000", \ - "0.0632284000, 0.0688768000, 0.0816666000, 0.1040340000, 0.1503718000, 0.2754762000, 0.6728194000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0278086000, 0.0333656000, 0.0474132000, 0.0837862000, 0.1926208000, 0.5249597000, 1.5026129000", \ - "0.0277673000, 0.0333435000, 0.0473435000, 0.0837569000, 0.1925423000, 0.5247353000, 1.5011322000", \ - "0.0277116000, 0.0331584000, 0.0471272000, 0.0836154000, 0.1922597000, 0.5246170000, 1.5010042000", \ - "0.0275985000, 0.0332496000, 0.0472381000, 0.0837073000, 0.1924358000, 0.5250944000, 1.5022826000", \ - "0.0288691000, 0.0341940000, 0.0478827000, 0.0842968000, 0.1925951000, 0.5250992000, 1.5017131000", \ - "0.0371054000, 0.0427768000, 0.0560075000, 0.0907940000, 0.1958217000, 0.5240138000, 1.4961643000", \ - "0.0512879000, 0.0585756000, 0.0735104000, 0.1066318000, 0.2032631000, 0.5274662000, 1.4988164000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__maj3_4") { - leakage_power () { - value : 0.0049017000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0040372000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0038141000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0048111000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0026805000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0048742000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0020872000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0029445000; - when : "A&B&!C"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__maj3"; - cell_leakage_power : 0.0037688080; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078682000, 0.0078564000, 0.0078293000, 0.0078302000, 0.0078323000, 0.0078372000, 0.0078485000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007778200, -0.007774600, -0.007766400, -0.007768300, -0.007772800, -0.007783200, -0.007807100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045630000; - } - pin ("B") { - capacitance : 0.0041370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0038700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088941000, 0.0088957000, 0.0088993000, 0.0088970000, 0.0088918000, 0.0088798000, 0.0088521000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007131200, -0.007138400, -0.007155000, -0.007143100, -0.007115600, -0.007052100, -0.006905900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044040000; - } - pin ("C") { - capacitance : 0.0049570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0047400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0098222000, 0.0098218000, 0.0098208000, 0.0098211000, 0.0098220000, 0.0098241000, 0.0098289000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008921100, -0.008918900, -0.008913900, -0.008908700, -0.008896700, -0.008869100, -0.008805400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051750000; - } - pin ("X") { - direction : "output"; - function : "(A&B) | (A&C) | (B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0304469000, 0.0284829000, 0.0227540000, 0.0069444000, -0.046467000, -0.229125300, -0.823335300", \ - "0.0302719000, 0.0283612000, 0.0226726000, 0.0072532000, -0.046530300, -0.229161300, -0.823589200", \ - "0.0302063000, 0.0282752000, 0.0226083000, 0.0068244000, -0.046715500, -0.229332000, -0.823804800", \ - "0.0299386000, 0.0280666000, 0.0224096000, 0.0068572000, -0.046667800, -0.229594500, -0.823882500", \ - "0.0297770000, 0.0278585000, 0.0222413000, 0.0064297000, -0.047214500, -0.230008400, -0.824073100", \ - "0.0298446000, 0.0278951000, 0.0221386000, 0.0063301000, -0.047352700, -0.230278000, -0.824388000", \ - "0.0374279000, 0.0354252000, 0.0292183000, 0.0099410000, -0.047150200, -0.229862200, -0.824206700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0329215000, 0.0348999000, 0.0408701000, 0.0599630000, 0.1185089000, 0.3041198000, 0.8934265000", \ - "0.0327952000, 0.0346740000, 0.0406768000, 0.0595111000, 0.1182956000, 0.3034912000, 0.8965168000", \ - "0.0326280000, 0.0344828000, 0.0404778000, 0.0593070000, 0.1181582000, 0.3035967000, 0.8966103000", \ - "0.0323104000, 0.0342281000, 0.0401714000, 0.0591116000, 0.1179219000, 0.3031625000, 0.8965783000", \ - "0.0323909000, 0.0342232000, 0.0400662000, 0.0590094000, 0.1175481000, 0.3030531000, 0.8922681000", \ - "0.0334468000, 0.0352169000, 0.0409681000, 0.0587109000, 0.1171522000, 0.3015664000, 0.8918417000", \ - "0.0346780000, 0.0363717000, 0.0419606000, 0.0598241000, 0.1180454000, 0.3030990000, 0.8900040000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0242148000, 0.0221503000, 0.0167538000, 0.0011300000, -0.051538000, -0.233514100, -0.827717900", \ - "0.0238556000, 0.0218510000, 0.0164931000, 0.0009098000, -0.051803600, -0.233682200, -0.827894900", \ - "0.0236101000, 0.0216841000, 0.0162251000, 0.0005900000, -0.052164700, -0.234213900, -0.828407500", \ - "0.0228752000, 0.0210651000, 0.0154421000, 3.390000e-05, -0.052900100, -0.234878600, -0.828979400", \ - "0.0223231000, 0.0205126000, 0.0150232000, -0.000528200, -0.053485000, -0.235418600, -0.829514300", \ - "0.0228109000, 0.0208552000, 0.0152433000, 0.0001465000, -0.053422000, -0.235614800, -0.829574300", \ - "0.0319854000, 0.0297521000, 0.0230576000, 0.0032605000, -0.053963900, -0.234935000, -0.828911500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0325225000, 0.0344612000, 0.0404458000, 0.0594863000, 0.1183778000, 0.3036518000, 0.8966179000", \ - "0.0325753000, 0.0344826000, 0.0404807000, 0.0595710000, 0.1184860000, 0.3038801000, 0.8930482000", \ - "0.0325601000, 0.0344824000, 0.0404790000, 0.0595223000, 0.1183926000, 0.3034930000, 0.8968843000", \ - "0.0322777000, 0.0341766000, 0.0401797000, 0.0591944000, 0.1179761000, 0.3033093000, 0.8922101000", \ - "0.0320515000, 0.0338407000, 0.0397678000, 0.0585273000, 0.1171419000, 0.3024866000, 0.8912732000", \ - "0.0332630000, 0.0350359000, 0.0406383000, 0.0581689000, 0.1164150000, 0.3009921000, 0.8950227000", \ - "0.0342398000, 0.0359513000, 0.0414199000, 0.0593727000, 0.1169659000, 0.3019103000, 0.8868485000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0291793000, 0.0272489000, 0.0215223000, 0.0060897000, -0.047713200, -0.230224000, -0.824802400", \ - "0.0290414000, 0.0270753000, 0.0213415000, 0.0056681000, -0.047824900, -0.230531700, -0.824879900", \ - "0.0286544000, 0.0267014000, 0.0216259000, 0.0056484000, -0.048245900, -0.230820500, -0.825382500", \ - "0.0280915000, 0.0261247000, 0.0205049000, 0.0049331000, -0.048586600, -0.231559300, -0.825901300", \ - "0.0276328000, 0.0256951000, 0.0200885000, 0.0041819000, -0.049451800, -0.232212500, -0.826441600", \ - "0.0278526000, 0.0259194000, 0.0201087000, 0.0040489000, -0.049710100, -0.232622700, -0.826505300", \ - "0.0369400000, 0.0347175000, 0.0280998000, 0.0092402000, -0.048866000, -0.231205000, -0.825395300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0349825000, 0.0368967000, 0.0428934000, 0.0618994000, 0.1205467000, 0.3059310000, 0.8947377000", \ - "0.0349846000, 0.0368935000, 0.0428889000, 0.0618636000, 0.1205067000, 0.3060801000, 0.8944916000", \ - "0.0350082000, 0.0368447000, 0.0428352000, 0.0616183000, 0.1205290000, 0.3054658000, 0.8990088000", \ - "0.0346088000, 0.0365335000, 0.0424708000, 0.0614077000, 0.1202299000, 0.3055668000, 0.8944006000", \ - "0.0344789000, 0.0362820000, 0.0421469000, 0.0609302000, 0.1192375000, 0.3048553000, 0.8939299000", \ - "0.0351280000, 0.0368744000, 0.0425692000, 0.0605723000, 0.1182988000, 0.3033406000, 0.8931492000", \ - "0.0364716000, 0.0381665000, 0.0436427000, 0.0613642000, 0.1193445000, 0.3031190000, 0.8891987000"); - } - } - max_capacitance : 0.5346780000; - max_transition : 1.5032330000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.2982816000, 0.3038199000, 0.3183651000, 0.3500691000, 0.4116955000, 0.5379803000, 0.8601237000", \ - "0.3036218000, 0.3092397000, 0.3237584000, 0.3553060000, 0.4172415000, 0.5439167000, 0.8662964000", \ - "0.3164869000, 0.3220988000, 0.3366049000, 0.3681684000, 0.4300878000, 0.5561732000, 0.8786673000", \ - "0.3441771000, 0.3497640000, 0.3642288000, 0.3958046000, 0.4575137000, 0.5847610000, 0.9068960000", \ - "0.4070506000, 0.4126400000, 0.4270200000, 0.4587264000, 0.5204237000, 0.6476450000, 0.9698764000", \ - "0.5511098000, 0.5567483000, 0.5712807000, 0.6031034000, 0.6649633000, 0.7919383000, 1.1142874000", \ - "0.8235441000, 0.8302030000, 0.8472846000, 0.8839005000, 0.9538168000, 1.0888640000, 1.4149789000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.1398386000, 0.1445007000, 0.1570160000, 0.1872354000, 0.2637887000, 0.4896716000, 1.2047683000", \ - "0.1441140000, 0.1488030000, 0.1612627000, 0.1914134000, 0.2679676000, 0.4934209000, 1.2107545000", \ - "0.1533695000, 0.1580704000, 0.1704684000, 0.2005923000, 0.2770975000, 0.5029120000, 1.2188845000", \ - "0.1741119000, 0.1789009000, 0.1913049000, 0.2214997000, 0.2978656000, 0.5244709000, 1.2388888000", \ - "0.2188061000, 0.2236003000, 0.2362071000, 0.2666591000, 0.3430808000, 0.5693165000, 1.2823322000", \ - "0.2889059000, 0.2943832000, 0.3086692000, 0.3412249000, 0.4198165000, 0.6457444000, 1.3605370000", \ - "0.3671877000, 0.3741259000, 0.3918458000, 0.4302185000, 0.5134677000, 0.7396819000, 1.4535677000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0480111000, 0.0509818000, 0.0595206000, 0.0785341000, 0.1221650000, 0.2413299000, 0.6334857000", \ - "0.0477449000, 0.0509996000, 0.0596175000, 0.0778612000, 0.1208118000, 0.2402907000, 0.6327570000", \ - "0.0479851000, 0.0508010000, 0.0592531000, 0.0777980000, 0.1214351000, 0.2413637000, 0.6336002000", \ - "0.0476480000, 0.0508353000, 0.0595187000, 0.0776009000, 0.1202595000, 0.2402589000, 0.6337115000", \ - "0.0477030000, 0.0508657000, 0.0601269000, 0.0779187000, 0.1212961000, 0.2405756000, 0.6337828000", \ - "0.0495468000, 0.0525794000, 0.0606908000, 0.0795231000, 0.1210692000, 0.2410406000, 0.6331572000", \ - "0.0634753000, 0.0666128000, 0.0767572000, 0.0954372000, 0.1388102000, 0.2540226000, 0.6373865000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0287704000, 0.0321581000, 0.0424226000, 0.0718302000, 0.1658724000, 0.4816411000, 1.5011330000", \ - "0.0284876000, 0.0321148000, 0.0424350000, 0.0719040000, 0.1654801000, 0.4805679000, 1.4988581000", \ - "0.0285921000, 0.0321809000, 0.0424605000, 0.0719365000, 0.1656723000, 0.4813145000, 1.5031678000", \ - "0.0285478000, 0.0322308000, 0.0425917000, 0.0717006000, 0.1656925000, 0.4810042000, 1.5032335000", \ - "0.0299553000, 0.0334685000, 0.0434345000, 0.0726633000, 0.1660931000, 0.4819535000, 1.4992214000", \ - "0.0358418000, 0.0395472000, 0.0498884000, 0.0784772000, 0.1694258000, 0.4806275000, 1.5015686000", \ - "0.0487849000, 0.0530483000, 0.0647658000, 0.0923333000, 0.1773317000, 0.4835313000, 1.4953867000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.2877142000, 0.2934366000, 0.3081617000, 0.3409706000, 0.4071832000, 0.5431713000, 0.8733425000", \ - "0.2910071000, 0.2966570000, 0.3114307000, 0.3442677000, 0.4104581000, 0.5465794000, 0.8763169000", \ - "0.2995703000, 0.3051264000, 0.3198884000, 0.3527472000, 0.4189185000, 0.5551288000, 0.8849495000", \ - "0.3233845000, 0.3291541000, 0.3437937000, 0.3768179000, 0.4422955000, 0.5785066000, 0.9085578000", \ - "0.3883378000, 0.3939508000, 0.4086007000, 0.4404434000, 0.5066394000, 0.6424957000, 0.9725106000", \ - "0.5470321000, 0.5525416000, 0.5670647000, 0.6003900000, 0.6663881000, 0.8014946000, 1.1315689000", \ - "0.8424644000, 0.8493740000, 0.8674465000, 0.9069773000, 0.9814156000, 1.1242713000, 1.4613210000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.1297877000, 0.1345960000, 0.1473329000, 0.1779793000, 0.2549511000, 0.4814232000, 1.1968435000", \ - "0.1345561000, 0.1393394000, 0.1521238000, 0.1827599000, 0.2597665000, 0.4856721000, 1.1986012000", \ - "0.1447835000, 0.1495479000, 0.1623415000, 0.1929211000, 0.2697833000, 0.4961421000, 1.2097893000", \ - "0.1676961000, 0.1724696000, 0.1851475000, 0.2163432000, 0.2931181000, 0.5193058000, 1.2322141000", \ - "0.2176686000, 0.2227414000, 0.2359541000, 0.2671321000, 0.3441025000, 0.5697062000, 1.2841769000", \ - "0.2828905000, 0.2888500000, 0.3039513000, 0.3380082000, 0.4179304000, 0.6449555000, 1.3616225000", \ - "0.3432694000, 0.3507512000, 0.3700811000, 0.4112315000, 0.4970735000, 0.7249957000, 1.4399461000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0484639000, 0.0518238000, 0.0610585000, 0.0823204000, 0.1297988000, 0.2539670000, 0.6401499000", \ - "0.0486333000, 0.0520112000, 0.0604514000, 0.0822760000, 0.1311517000, 0.2541330000, 0.6406758000", \ - "0.0485292000, 0.0516238000, 0.0607101000, 0.0825405000, 0.1295241000, 0.2533853000, 0.6403420000", \ - "0.0487689000, 0.0522724000, 0.0603748000, 0.0816960000, 0.1309123000, 0.2534630000, 0.6407675000", \ - "0.0485143000, 0.0518830000, 0.0606955000, 0.0816301000, 0.1308802000, 0.2532295000, 0.6403221000", \ - "0.0507835000, 0.0537791000, 0.0618894000, 0.0832036000, 0.1298640000, 0.2543800000, 0.6396625000", \ - "0.0739911000, 0.0774957000, 0.0863614000, 0.1071831000, 0.1515944000, 0.2709342000, 0.6486939000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0292437000, 0.0326685000, 0.0429853000, 0.0722472000, 0.1658714000, 0.4809044000, 1.5023637000", \ - "0.0289733000, 0.0327390000, 0.0429202000, 0.0722430000, 0.1655579000, 0.4812390000, 1.4970926000", \ - "0.0291525000, 0.0327428000, 0.0429517000, 0.0721124000, 0.1656409000, 0.4801092000, 1.5017317000", \ - "0.0292061000, 0.0328039000, 0.0429218000, 0.0722006000, 0.1654600000, 0.4810535000, 1.4998309000", \ - "0.0320381000, 0.0352523000, 0.0452254000, 0.0739968000, 0.1661038000, 0.4802760000, 1.4964123000", \ - "0.0399108000, 0.0439115000, 0.0544773000, 0.0829993000, 0.1717011000, 0.4816945000, 1.5024492000", \ - "0.0556058000, 0.0602480000, 0.0725833000, 0.0998141000, 0.1824563000, 0.4849436000, 1.4976420000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.2985072000, 0.3040906000, 0.3186193000, 0.3502803000, 0.4123806000, 0.5386815000, 0.8610593000", \ - "0.3020327000, 0.3076051000, 0.3221746000, 0.3539337000, 0.4156433000, 0.5419465000, 0.8643353000", \ - "0.3107286000, 0.3163523000, 0.3308849000, 0.3623379000, 0.4245259000, 0.5511364000, 0.8734288000", \ - "0.3345385000, 0.3401951000, 0.3546578000, 0.3859930000, 0.4477014000, 0.5749295000, 0.8971104000", \ - "0.3964496000, 0.4021354000, 0.4165879000, 0.4486004000, 0.5104397000, 0.6375481000, 0.9597509000", \ - "0.5506259000, 0.5562119000, 0.5706405000, 0.6024073000, 0.6642150000, 0.7914135000, 1.1117753000", \ - "0.8302644000, 0.8372660000, 0.8557218000, 0.8953884000, 0.9684018000, 1.1044423000, 1.4304717000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.1418551000, 0.1465319000, 0.1591201000, 0.1892981000, 0.2658280000, 0.4923492000, 1.2053136000", \ - "0.1466252000, 0.1512918000, 0.1637318000, 0.1940300000, 0.2705433000, 0.4966526000, 1.2105714000", \ - "0.1573004000, 0.1619715000, 0.1743621000, 0.2044940000, 0.2809554000, 0.5074353000, 1.2208233000", \ - "0.1811613000, 0.1859303000, 0.1983733000, 0.2285677000, 0.3050185000, 0.5308034000, 1.2446026000", \ - "0.2356828000, 0.2404131000, 0.2529024000, 0.2831438000, 0.3595520000, 0.5856668000, 1.2988719000", \ - "0.3166054000, 0.3223577000, 0.3369670000, 0.3699212000, 0.4480240000, 0.6737811000, 1.3884390000", \ - "0.4036068000, 0.4110927000, 0.4299524000, 0.4700259000, 0.5536899000, 0.7794438000, 1.4941500000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0476810000, 0.0509452000, 0.0595548000, 0.0775806000, 0.1211471000, 0.2407587000, 0.6324776000", \ - "0.0479557000, 0.0509566000, 0.0595756000, 0.0779945000, 0.1222316000, 0.2415875000, 0.6333063000", \ - "0.0476623000, 0.0508203000, 0.0597935000, 0.0782374000, 0.1210240000, 0.2406033000, 0.6321584000", \ - "0.0476678000, 0.0510824000, 0.0591607000, 0.0775890000, 0.1203506000, 0.2402678000, 0.6337506000", \ - "0.0481093000, 0.0510712000, 0.0590908000, 0.0778420000, 0.1209264000, 0.2407900000, 0.6332283000", \ - "0.0496579000, 0.0529609000, 0.0607367000, 0.0788802000, 0.1214366000, 0.2409838000, 0.6331706000", \ - "0.0724792000, 0.0760310000, 0.0858801000, 0.1057226000, 0.1450007000, 0.2566941000, 0.6380012000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0286559000, 0.0324264000, 0.0427532000, 0.0719770000, 0.1659752000, 0.4816744000, 1.5017391000", \ - "0.0287954000, 0.0322435000, 0.0423807000, 0.0719287000, 0.1659113000, 0.4817787000, 1.4971139000", \ - "0.0286095000, 0.0322140000, 0.0425100000, 0.0718116000, 0.1655216000, 0.4806009000, 1.5021897000", \ - "0.0285919000, 0.0322565000, 0.0425201000, 0.0717623000, 0.1657222000, 0.4812690000, 1.5013426000", \ - "0.0298372000, 0.0333971000, 0.0433940000, 0.0723488000, 0.1660408000, 0.4819959000, 1.4999494000", \ - "0.0388138000, 0.0423713000, 0.0521299000, 0.0797192000, 0.1698460000, 0.4813911000, 1.4997481000", \ - "0.0546339000, 0.0591185000, 0.0705593000, 0.0969209000, 0.1793306000, 0.4842854000, 1.4960891000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2_1") { - leakage_power () { - value : 0.0067577000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0065026000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0014513000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0068987000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0071740000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0011854000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0012616000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0009910000; - when : "A0&A1&!S"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__mux2"; - cell_leakage_power : 0.0040277890; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0015580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022554000, 0.0022535000, 0.0022491000, 0.0022498000, 0.0022515000, 0.0022553000, 0.0022640000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001485800, -0.001502000, -0.001539300, -0.001537100, -0.001532200, -0.001520900, -0.001494900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016110000; - } - pin ("A1") { - capacitance : 0.0018840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030295000, 0.0030252000, 0.0030155000, 0.0030152000, 0.0030145000, 0.0030128000, 0.0030090000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002301700, -0.002309600, -0.002327700, -0.002325300, -0.002319800, -0.002307100, -0.002278000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - } - pin ("S") { - capacitance : 0.0034020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0114305000, 0.0113157000, 0.0110510000, 0.0110959000, 0.0111992000, 0.0114375000, 0.0119866000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002432300, -0.002494400, -0.002637600, -0.002604600, -0.002528500, -0.002353000, -0.001948700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035200000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S) | (A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0093551000, 0.0082503000, 0.0055250000, -0.002828900, -0.026897600, -0.092454300, -0.266909000", \ - "0.0093649000, 0.0082594000, 0.0053646000, -0.002982600, -0.026994000, -0.092572400, -0.267007900", \ - "0.0091106000, 0.0080213000, 0.0051577000, -0.003187100, -0.027155100, -0.092693400, -0.267154200", \ - "0.0089792000, 0.0078942000, 0.0050110000, -0.003342900, -0.027361600, -0.092899600, -0.267309000", \ - "0.0088436000, 0.0077406000, 0.0048927000, -0.003433400, -0.027457300, -0.092991200, -0.267401500", \ - "0.0090206000, 0.0078839000, 0.0049818000, -0.003405900, -0.027448300, -0.092968600, -0.267351300", \ - "0.0121098000, 0.0106334000, 0.0069209000, -0.002584800, -0.027251400, -0.092684400, -0.267069200"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0091072000, 0.0105714000, 0.0143296000, 0.0239028000, 0.0486656000, 0.1139809000, 0.2880523000", \ - "0.0091188000, 0.0105856000, 0.0143607000, 0.0238970000, 0.0486432000, 0.1145506000, 0.2859671000", \ - "0.0091030000, 0.0105643000, 0.0143234000, 0.0238620000, 0.0486119000, 0.1140071000, 0.2872423000", \ - "0.0089889000, 0.0104274000, 0.0141482000, 0.0236318000, 0.0484102000, 0.1138430000, 0.2859676000", \ - "0.0088773000, 0.0102956000, 0.0139927000, 0.0233914000, 0.0481923000, 0.1142262000, 0.2848490000", \ - "0.0093037000, 0.0106364000, 0.0142574000, 0.0234986000, 0.0482495000, 0.1131210000, 0.2879116000", \ - "0.0099379000, 0.0112512000, 0.0146652000, 0.0241871000, 0.0487751000, 0.1143620000, 0.2860805000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0088424000, 0.0077704000, 0.0050151000, -0.003236100, -0.027182300, -0.092613100, -0.267026400", \ - "0.0087088000, 0.0076304000, 0.0047920000, -0.003496600, -0.027342700, -0.092748400, -0.267160100", \ - "0.0085088000, 0.0074187000, 0.0047113000, -0.003621800, -0.027527700, -0.092981100, -0.267377300", \ - "0.0082583000, 0.0071717000, 0.0043486000, -0.003929800, -0.027829300, -0.093266200, -0.267630100", \ - "0.0081754000, 0.0070789000, 0.0042452000, -0.004077500, -0.027955100, -0.093381900, -0.267737700", \ - "0.0086003000, 0.0074832000, 0.0045536000, -0.003878900, -0.027914500, -0.093401900, -0.267723400", \ - "0.0114470000, 0.0099581000, 0.0062241000, -0.002293100, -0.027228900, -0.092625600, -0.266948300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0100790000, 0.0115061000, 0.0151610000, 0.0245440000, 0.0490460000, 0.1144503000, 0.2861807000", \ - "0.0100629000, 0.0114816000, 0.0151514000, 0.0245287000, 0.0491052000, 0.1142423000, 0.2870238000", \ - "0.0100063000, 0.0114323000, 0.0150854000, 0.0244715000, 0.0490575000, 0.1142507000, 0.2869923000", \ - "0.0099062000, 0.0113136000, 0.0149518000, 0.0243375000, 0.0491078000, 0.1143065000, 0.2885168000", \ - "0.0097131000, 0.0111421000, 0.0148078000, 0.0241183000, 0.0487445000, 0.1145620000, 0.2873212000", \ - "0.0100838000, 0.0114079000, 0.0149533000, 0.0241846000, 0.0488712000, 0.1134624000, 0.2882056000", \ - "0.0107220000, 0.0120456000, 0.0155309000, 0.0249210000, 0.0494397000, 0.1146022000, 0.2870683000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0108124000, 0.0098040000, 0.0069566000, -0.001265100, -0.025258300, -0.090695200, -0.265051400", \ - "0.0107618000, 0.0097167000, 0.0068716000, -0.001428500, -0.025287200, -0.090682400, -0.265051000", \ - "0.0107532000, 0.0096868000, 0.0068412000, -0.001457700, -0.025308600, -0.090707300, -0.265066800", \ - "0.0104930000, 0.0094041000, 0.0065804000, -0.001713800, -0.025571800, -0.090965400, -0.265332500", \ - "0.0102878000, 0.0091844000, 0.0063764000, -0.001883900, -0.025764200, -0.091194900, -0.265547000", \ - "0.0119001000, 0.0105436000, 0.0069712000, -0.001918700, -0.025841000, -0.091272000, -0.265623000", \ - "0.0135000000, 0.0121218000, 0.0086430000, -0.000496300, -0.025126700, -0.090947800, -0.265389300"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("0.0096418000, 0.0110898000, 0.0148046000, 0.0243675000, 0.0491395000, 0.1144771000, 0.2873823000", \ - "0.0095990000, 0.0110389000, 0.0147776000, 0.0242939000, 0.0491199000, 0.1144405000, 0.2871896000", \ - "0.0097747000, 0.0112055000, 0.0149198000, 0.0244704000, 0.0494494000, 0.1146109000, 0.2872142000", \ - "0.0097501000, 0.0111788000, 0.0148914000, 0.0244423000, 0.0492453000, 0.1144706000, 0.2870901000", \ - "0.0096208000, 0.0110690000, 0.0148048000, 0.0243159000, 0.0491136000, 0.1148828000, 0.2871368000", \ - "0.0094669000, 0.0108219000, 0.0145690000, 0.0243916000, 0.0490141000, 0.1143407000, 0.2884834000", \ - "0.0097010000, 0.0110779000, 0.0147340000, 0.0242812000, 0.0491787000, 0.1146895000, 0.2865902000"); - } - } - max_capacitance : 0.1730450000; - max_transition : 1.5042320000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.2429637000, 0.2530684000, 0.2733664000, 0.3115355000, 0.3829204000, 0.5307446000, 0.8904517000", \ - "0.2459605000, 0.2560381000, 0.2765444000, 0.3147721000, 0.3862506000, 0.5340248000, 0.8932227000", \ - "0.2552336000, 0.2652079000, 0.2856106000, 0.3239027000, 0.3946961000, 0.5424531000, 0.9018619000", \ - "0.2811036000, 0.2911968000, 0.3116636000, 0.3498369000, 0.4212213000, 0.5691500000, 0.9289299000", \ - "0.3495411000, 0.3595188000, 0.3800386000, 0.4182914000, 0.4896301000, 0.6374772000, 0.9967642000", \ - "0.5081483000, 0.5187329000, 0.5401209000, 0.5787524000, 0.6506041000, 0.7989518000, 1.1585668000", \ - "0.7813678000, 0.7947139000, 0.8214726000, 0.8689188000, 0.9489407000, 1.1037615000, 1.4652617000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0825322000, 0.0905096000, 0.1081006000, 0.1467415000, 0.2403692000, 0.4848532000, 1.1303292000", \ - "0.0869777000, 0.0950013000, 0.1125939000, 0.1511205000, 0.2446311000, 0.4884149000, 1.1447283000", \ - "0.0973659000, 0.1054055000, 0.1229261000, 0.1615033000, 0.2550509000, 0.5005140000, 1.1499588000", \ - "0.1212526000, 0.1292920000, 0.1467602000, 0.1851815000, 0.2787920000, 0.5229629000, 1.1788722000", \ - "0.1585448000, 0.1675118000, 0.1863090000, 0.2258075000, 0.3200034000, 0.5651930000, 1.2121013000", \ - "0.1994847000, 0.2108551000, 0.2332579000, 0.2756458000, 0.3705170000, 0.6152473000, 1.2634637000", \ - "0.2220627000, 0.2373346000, 0.2669290000, 0.3186315000, 0.4167464000, 0.6615460000, 1.3071866000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0407074000, 0.0470764000, 0.0611734000, 0.0896904000, 0.1521490000, 0.3165794000, 0.7793373000", \ - "0.0408472000, 0.0471679000, 0.0603266000, 0.0882173000, 0.1521236000, 0.3156432000, 0.7807624000", \ - "0.0411419000, 0.0472315000, 0.0604128000, 0.0885547000, 0.1529887000, 0.3167556000, 0.7805706000", \ - "0.0408220000, 0.0470948000, 0.0603245000, 0.0881784000, 0.1521471000, 0.3165608000, 0.7808756000", \ - "0.0408970000, 0.0470661000, 0.0604125000, 0.0883253000, 0.1524739000, 0.3157782000, 0.7803505000", \ - "0.0453620000, 0.0515445000, 0.0639824000, 0.0904644000, 0.1534166000, 0.3167415000, 0.7832782000", \ - "0.0648145000, 0.0716121000, 0.0864201000, 0.1127907000, 0.1721740000, 0.3266874000, 0.7838654000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0263857000, 0.0331894000, 0.0502716000, 0.0963280000, 0.2245293000, 0.5730470000, 1.4950828000", \ - "0.0264893000, 0.0331400000, 0.0503843000, 0.0963208000, 0.2244743000, 0.5748342000, 1.5015991000", \ - "0.0264036000, 0.0331783000, 0.0503696000, 0.0962620000, 0.2245496000, 0.5760838000, 1.5014562000", \ - "0.0271211000, 0.0338730000, 0.0507083000, 0.0964803000, 0.2245014000, 0.5711713000, 1.4994118000", \ - "0.0327928000, 0.0388535000, 0.0548151000, 0.0988329000, 0.2250339000, 0.5735702000, 1.4948180000", \ - "0.0443843000, 0.0502671000, 0.0652065000, 0.1051424000, 0.2271266000, 0.5717274000, 1.5027594000", \ - "0.0622399000, 0.0701198000, 0.0866698000, 0.1231422000, 0.2330962000, 0.5750114000, 1.4878268000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.2550970000, 0.2653238000, 0.2858625000, 0.3240013000, 0.3959930000, 0.5442536000, 0.9037557000", \ - "0.2572662000, 0.2676734000, 0.2883946000, 0.3270787000, 0.3985071000, 0.5466409000, 0.9061793000", \ - "0.2656863000, 0.2757679000, 0.2962789000, 0.3351030000, 0.4068484000, 0.5555196000, 0.9152459000", \ - "0.2903129000, 0.3005664000, 0.3212427000, 0.3598035000, 0.4317873000, 0.5800733000, 0.9398294000", \ - "0.3580822000, 0.3683464000, 0.3888900000, 0.4275625000, 0.4994897000, 0.6478639000, 1.0080428000", \ - "0.5163710000, 0.5270306000, 0.5483307000, 0.5871936000, 0.6595961000, 0.8082315000, 1.1683670000", \ - "0.7893732000, 0.8028029000, 0.8293848000, 0.8775405000, 0.9584242000, 1.1130957000, 1.4756820000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0855012000, 0.0934913000, 0.1109298000, 0.1491568000, 0.2419970000, 0.4868842000, 1.1327013000", \ - "0.0899015000, 0.0978555000, 0.1153380000, 0.1535640000, 0.2465617000, 0.4901951000, 1.1345916000", \ - "0.1002214000, 0.1082531000, 0.1256432000, 0.1639216000, 0.2569989000, 0.5011533000, 1.1459663000", \ - "0.1237849000, 0.1317814000, 0.1492282000, 0.1874950000, 0.2806293000, 0.5254858000, 1.1740190000", \ - "0.1613350000, 0.1703942000, 0.1891752000, 0.2288238000, 0.3225407000, 0.5674183000, 1.2143468000", \ - "0.2028403000, 0.2143195000, 0.2369469000, 0.2792782000, 0.3741218000, 0.6186294000, 1.2661491000", \ - "0.2266353000, 0.2420066000, 0.2717693000, 0.3236110000, 0.4216473000, 0.6663710000, 1.3117153000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0410359000, 0.0475245000, 0.0610803000, 0.0892712000, 0.1533213000, 0.3173068000, 0.7805211000", \ - "0.0413282000, 0.0477416000, 0.0608164000, 0.0892820000, 0.1535699000, 0.3173119000, 0.7805463000", \ - "0.0413211000, 0.0475270000, 0.0611046000, 0.0892550000, 0.1528729000, 0.3168918000, 0.7826738000", \ - "0.0415761000, 0.0482220000, 0.0612231000, 0.0886383000, 0.1531698000, 0.3162049000, 0.7817108000", \ - "0.0419467000, 0.0483548000, 0.0610714000, 0.0892917000, 0.1526399000, 0.3171115000, 0.7860420000", \ - "0.0454874000, 0.0515788000, 0.0643456000, 0.0910349000, 0.1549193000, 0.3177679000, 0.7805814000", \ - "0.0640890000, 0.0715825000, 0.0863763000, 0.1136150000, 0.1729289000, 0.3275539000, 0.7824648000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0269556000, 0.0336961000, 0.0508901000, 0.0968071000, 0.2242755000, 0.5745073000, 1.4958901000", \ - "0.0269184000, 0.0337431000, 0.0509358000, 0.0968682000, 0.2245832000, 0.5735469000, 1.5000035000", \ - "0.0269750000, 0.0337983000, 0.0509057000, 0.0968237000, 0.2247484000, 0.5727038000, 1.4970497000", \ - "0.0274492000, 0.0341063000, 0.0512263000, 0.0967964000, 0.2242460000, 0.5729542000, 1.5042317000", \ - "0.0329951000, 0.0393354000, 0.0553044000, 0.0993442000, 0.2253272000, 0.5736578000, 1.4964180000", \ - "0.0449631000, 0.0511631000, 0.0653714000, 0.1056155000, 0.2282068000, 0.5716769000, 1.4983531000", \ - "0.0633604000, 0.0711532000, 0.0874665000, 0.1238996000, 0.2341370000, 0.5751989000, 1.4904125000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.2685503000, 0.2787834000, 0.2991572000, 0.3375414000, 0.4086368000, 0.5565593000, 0.9161238000", \ - "0.2722520000, 0.2823364000, 0.3028446000, 0.3411134000, 0.4126161000, 0.5603311000, 0.9198686000", \ - "0.2826785000, 0.2926761000, 0.3132342000, 0.3514932000, 0.4227594000, 0.5705799000, 0.9299987000", \ - "0.3076742000, 0.3177434000, 0.3382155000, 0.3764614000, 0.4479306000, 0.5956567000, 0.9553882000", \ - "0.3667593000, 0.3770137000, 0.3974770000, 0.4356828000, 0.5071106000, 0.6548729000, 1.0146389000", \ - "0.4994569000, 0.5101488000, 0.5316452000, 0.5707979000, 0.6429981000, 0.7913002000, 1.1509491000", \ - "0.7403561000, 0.7525980000, 0.7772031000, 0.8220282000, 0.9021132000, 1.0572322000, 1.4198059000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0933996000, 0.1007524000, 0.1171054000, 0.1540888000, 0.2463703000, 0.4896453000, 1.1346188000", \ - "0.0977335000, 0.1050850000, 0.1214468000, 0.1584181000, 0.2505084000, 0.4936326000, 1.1380707000", \ - "0.1071139000, 0.1144239000, 0.1307532000, 0.1676379000, 0.2599950000, 0.5040870000, 1.1506660000", \ - "0.1275497000, 0.1348577000, 0.1511896000, 0.1882718000, 0.2808188000, 0.5240042000, 1.1690470000", \ - "0.1641579000, 0.1720598000, 0.1892875000, 0.2273217000, 0.3204701000, 0.5650940000, 1.2120714000", \ - "0.2122483000, 0.2217009000, 0.2409599000, 0.2807462000, 0.3744892000, 0.6185787000, 1.2640692000", \ - "0.2517477000, 0.2638714000, 0.2886000000, 0.3335092000, 0.4290715000, 0.6744522000, 1.3185744000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0415780000, 0.0476721000, 0.0604463000, 0.0884563000, 0.1518739000, 0.3166994000, 0.7798743000", \ - "0.0407116000, 0.0472831000, 0.0604035000, 0.0881824000, 0.1523401000, 0.3163874000, 0.7804584000", \ - "0.0409501000, 0.0471274000, 0.0608702000, 0.0886905000, 0.1521641000, 0.3164743000, 0.7834485000", \ - "0.0406980000, 0.0472247000, 0.0603846000, 0.0880651000, 0.1519641000, 0.3166430000, 0.7854939000", \ - "0.0410933000, 0.0471934000, 0.0603086000, 0.0880867000, 0.1521176000, 0.3166051000, 0.7854339000", \ - "0.0452131000, 0.0515030000, 0.0641837000, 0.0914815000, 0.1536476000, 0.3170747000, 0.7804464000", \ - "0.0555547000, 0.0626160000, 0.0774533000, 0.1057799000, 0.1690937000, 0.3281878000, 0.7865377000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0243505000, 0.0312825000, 0.0485235000, 0.0951912000, 0.2246447000, 0.5717113000, 1.4914543000", \ - "0.0243776000, 0.0312191000, 0.0486223000, 0.0952134000, 0.2246631000, 0.5715695000, 1.4928877000", \ - "0.0244415000, 0.0312402000, 0.0485027000, 0.0953751000, 0.2239455000, 0.5734300000, 1.4961573000", \ - "0.0245140000, 0.0314075000, 0.0485939000, 0.0951846000, 0.2247074000, 0.5715171000, 1.4947154000", \ - "0.0275359000, 0.0343631000, 0.0512097000, 0.0967126000, 0.2250801000, 0.5726619000, 1.4923188000", \ - "0.0341250000, 0.0409431000, 0.0571476000, 0.1003665000, 0.2266626000, 0.5720363000, 1.4926803000", \ - "0.0473171000, 0.0552633000, 0.0718071000, 0.1109091000, 0.2290863000, 0.5750836000, 1.4918803000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.2706922000, 0.2807822000, 0.3014324000, 0.3397528000, 0.4113564000, 0.5601344000, 0.9199475000", \ - "0.2763302000, 0.2865606000, 0.3071896000, 0.3457494000, 0.4170657000, 0.5653717000, 0.9249204000", \ - "0.2874111000, 0.2976390000, 0.3182952000, 0.3568983000, 0.4282441000, 0.5765802000, 0.9361979000", \ - "0.3056422000, 0.3158760000, 0.3364822000, 0.3751396000, 0.4465650000, 0.5949238000, 0.9547301000", \ - "0.3287104000, 0.3388363000, 0.3594552000, 0.3982435000, 0.4702380000, 0.6186749000, 0.9782403000", \ - "0.3560644000, 0.3662071000, 0.3865085000, 0.4242749000, 0.4957123000, 0.6430502000, 1.0027186000", \ - "0.3665400000, 0.3766426000, 0.3976258000, 0.4359421000, 0.5076268000, 0.6554061000, 1.0141649000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.1560518000, 0.1635039000, 0.1800744000, 0.2176717000, 0.3109575000, 0.5555904000, 1.2008678000", \ - "0.1606906000, 0.1681346000, 0.1847180000, 0.2222891000, 0.3155556000, 0.5602607000, 1.2052399000", \ - "0.1738891000, 0.1812778000, 0.1978085000, 0.2354030000, 0.3289639000, 0.5734977000, 1.2198322000", \ - "0.2064490000, 0.2137925000, 0.2303375000, 0.2679331000, 0.3614830000, 0.6058338000, 1.2523518000", \ - "0.2731908000, 0.2805660000, 0.2971524000, 0.3346780000, 0.4278990000, 0.6735313000, 1.3186020000", \ - "0.3822668000, 0.3897196000, 0.4063465000, 0.4439345000, 0.5369901000, 0.7809999000, 1.4278128000", \ - "0.5576422000, 0.5653432000, 0.5822639000, 0.6200853000, 0.7134335000, 0.9573252000, 1.6022973000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0416267000, 0.0476412000, 0.0606879000, 0.0897755000, 0.1525484000, 0.3171451000, 0.7844282000", \ - "0.0410830000, 0.0476392000, 0.0608925000, 0.0893157000, 0.1535649000, 0.3173231000, 0.7805449000", \ - "0.0411093000, 0.0476761000, 0.0609063000, 0.0894780000, 0.1535698000, 0.3173425000, 0.7804146000", \ - "0.0416398000, 0.0482778000, 0.0608561000, 0.0892215000, 0.1536064000, 0.3173586000, 0.7807193000", \ - "0.0411343000, 0.0482040000, 0.0607784000, 0.0888827000, 0.1525793000, 0.3170863000, 0.7802509000", \ - "0.0409976000, 0.0473777000, 0.0601020000, 0.0893559000, 0.1501738000, 0.3152930000, 0.7813658000", \ - "0.0409176000, 0.0475737000, 0.0605521000, 0.0890451000, 0.1520794000, 0.3158510000, 0.7711207000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0244016000, 0.0312222000, 0.0482827000, 0.0948305000, 0.2246344000, 0.5709607000, 1.4908734000", \ - "0.0243201000, 0.0311325000, 0.0484555000, 0.0949781000, 0.2245967000, 0.5710962000, 1.4906445000", \ - "0.0243209000, 0.0311664000, 0.0484069000, 0.0951170000, 0.2241560000, 0.5728455000, 1.4937076000", \ - "0.0243035000, 0.0311179000, 0.0484211000, 0.0951055000, 0.2247066000, 0.5732541000, 1.4958539000", \ - "0.0244137000, 0.0312718000, 0.0485166000, 0.0952071000, 0.2244074000, 0.5725637000, 1.4922382000", \ - "0.0248769000, 0.0317555000, 0.0487721000, 0.0951989000, 0.2236638000, 0.5713228000, 1.4965360000", \ - "0.0260603000, 0.0328138000, 0.0496683000, 0.0956397000, 0.2243090000, 0.5703804000, 1.4935816000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2_2") { - leakage_power () { - value : 0.0059452000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0051965000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0025970000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0055820000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0063671000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0017988000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0023018000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0015697000; - when : "A0&A1&!S"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__mux2"; - cell_leakage_power : 0.0039197610; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0018780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030588000, 0.0030564000, 0.0030509000, 0.0030524000, 0.0030559000, 0.0030638000, 0.0030821000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002206000, -0.002237200, -0.002309100, -0.002308700, -0.002308000, -0.002306200, -0.002302100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019650000; - } - pin ("A1") { - capacitance : 0.0017040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016230000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030625000, 0.0030587000, 0.0030499000, 0.0030506000, 0.0030523000, 0.0030562000, 0.0030652000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002413500, -0.002423100, -0.002445300, -0.002442600, -0.002436300, -0.002421800, -0.002388400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017850000; - } - pin ("S") { - capacitance : 0.0032150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0030780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0106879000, 0.0105748000, 0.0103141000, 0.0103784000, 0.0105264000, 0.0108677000, 0.0116544000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0008183000, 0.0007172000, 0.0004840000, 0.0005377000, 0.0006615000, 0.0009469000, 0.0016047000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033520000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S) | (A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0128097000, 0.0112582000, 0.0073577000, -0.003875500, -0.039360100, -0.147283000, -0.462700100", \ - "0.0126108000, 0.0110461000, 0.0072710000, -0.003950500, -0.039488400, -0.147333300, -0.462875600", \ - "0.0124857000, 0.0109367000, 0.0070198000, -0.004217200, -0.039549300, -0.147451700, -0.463017400", \ - "0.0122391000, 0.0106723000, 0.0068287000, -0.004424500, -0.039794600, -0.147691300, -0.463204300", \ - "0.0121031000, 0.0105489000, 0.0066107000, -0.004651800, -0.040119700, -0.147964900, -0.463461600", \ - "0.0125358000, 0.0115149000, 0.0074242000, -0.004574500, -0.040145800, -0.147707600, -0.463278900", \ - "0.0177510000, 0.0158799000, 0.0109439000, -0.002338400, -0.039994100, -0.147721200, -0.463033400"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0149313000, 0.0165550000, 0.0212968000, 0.0346410000, 0.0719253000, 0.1794663000, 0.4925809000", \ - "0.0149918000, 0.0166271000, 0.0213592000, 0.0346575000, 0.0719947000, 0.1794801000, 0.4928364000", \ - "0.0149725000, 0.0166141000, 0.0213232000, 0.0346165000, 0.0720099000, 0.1796804000, 0.4898948000", \ - "0.0148966000, 0.0165276000, 0.0212508000, 0.0344837000, 0.0718565000, 0.1796177000, 0.4945540000", \ - "0.0148985000, 0.0164600000, 0.0211050000, 0.0342963000, 0.0715659000, 0.1795360000, 0.4924013000", \ - "0.0157811000, 0.0172764000, 0.0216792000, 0.0343750000, 0.0714847000, 0.1790627000, 0.4922798000", \ - "0.0168336000, 0.0182549000, 0.0224982000, 0.0353327000, 0.0726043000, 0.1802768000, 0.4907326000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0126664000, 0.0111595000, 0.0072204000, -0.004052100, -0.039725100, -0.147927000, -0.463561600", \ - "0.0125009000, 0.0109394000, 0.0070176000, -0.004219500, -0.039839800, -0.147868700, -0.463633300", \ - "0.0124128000, 0.0108429000, 0.0069260000, -0.004338800, -0.039982600, -0.148140800, -0.463744800", \ - "0.0121569000, 0.0106329000, 0.0067425000, -0.004547400, -0.040127500, -0.148284200, -0.463940900", \ - "0.0120528000, 0.0105092000, 0.0065915000, -0.004688300, -0.040315500, -0.148361800, -0.464056900", \ - "0.0124541000, 0.0107931000, 0.0067473000, -0.004609500, -0.040109500, -0.148227300, -0.463831900", \ - "0.0177976000, 0.0159727000, 0.0110113000, -0.002345500, -0.040103800, -0.147997500, -0.463605700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0148945000, 0.0165387000, 0.0212915000, 0.0346953000, 0.0723584000, 0.1804333000, 0.4912661000", \ - "0.0149200000, 0.0165627000, 0.0213131000, 0.0347096000, 0.0723744000, 0.1803903000, 0.4928918000", \ - "0.0148559000, 0.0165125000, 0.0212687000, 0.0346815000, 0.0723404000, 0.1803170000, 0.4906697000", \ - "0.0148256000, 0.0164709000, 0.0211873000, 0.0345166000, 0.0721234000, 0.1802821000, 0.4936813000", \ - "0.0147662000, 0.0163675000, 0.0209585000, 0.0342127000, 0.0716802000, 0.1799484000, 0.4925777000", \ - "0.0155580000, 0.0170570000, 0.0214638000, 0.0342108000, 0.0715906000, 0.1790817000, 0.4925816000", \ - "0.0165506000, 0.0179408000, 0.0221881000, 0.0349946000, 0.0724836000, 0.1802511000, 0.4913636000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0142459000, 0.0126869000, 0.0088099000, -0.002465000, -0.038089700, -0.146448300, -0.462392900", \ - "0.0142949000, 0.0127179000, 0.0087973000, -0.002424300, -0.038174200, -0.146574300, -0.462359900", \ - "0.0140900000, 0.0125436000, 0.0086304000, -0.002592900, -0.038206100, -0.146556200, -0.462479500", \ - "0.0137359000, 0.0121792000, 0.0083000000, -0.002996400, -0.038664100, -0.147006000, -0.462837300", \ - "0.0133592000, 0.0117972000, 0.0079187000, -0.003333900, -0.039033300, -0.147376900, -0.463186900", \ - "0.0143782000, 0.0128374000, 0.0082290000, -0.003412200, -0.039148700, -0.147477400, -0.463283600", \ - "0.0182608000, 0.0166244000, 0.0120300000, -0.000815100, -0.038140900, -0.147058700, -0.462980400"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014501170, 0.0042056820, 0.0121974600, 0.0353755100, 0.1025973000, 0.2975563000"); - values("0.0182970000, 0.0199389000, 0.0245776000, 0.0378050000, 0.0751074000, 0.1827530000, 0.4947044000", \ - "0.0181709000, 0.0198047000, 0.0244988000, 0.0377462000, 0.0750407000, 0.1828440000, 0.4952093000", \ - "0.0182351000, 0.0198548000, 0.0245474000, 0.0377950000, 0.0750938000, 0.1827404000, 0.4952955000", \ - "0.0180378000, 0.0196633000, 0.0243065000, 0.0375798000, 0.0748423000, 0.1825474000, 0.4945839000", \ - "0.0177146000, 0.0193728000, 0.0240652000, 0.0373103000, 0.0746055000, 0.1823910000, 0.4946982000", \ - "0.0175411000, 0.0190210000, 0.0238841000, 0.0374538000, 0.0745414000, 0.1821854000, 0.4938112000", \ - "0.0181807000, 0.0197955000, 0.0241929000, 0.0372452000, 0.0742853000, 0.1827697000, 0.4962899000"); - } - } - max_capacitance : 0.2975560000; - max_transition : 1.5066720000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2266660000, 0.2344140000, 0.2512571000, 0.2841361000, 0.3457040000, 0.4734192000, 0.7924621000", \ - "0.2304622000, 0.2381082000, 0.2548991000, 0.2877833000, 0.3494454000, 0.4770220000, 0.7955712000", \ - "0.2404853000, 0.2481464000, 0.2650678000, 0.2978039000, 0.3592634000, 0.4865769000, 0.8055120000", \ - "0.2677142000, 0.2753490000, 0.2922030000, 0.3250775000, 0.3864510000, 0.5138555000, 0.8329540000", \ - "0.3346227000, 0.3422716000, 0.3590370000, 0.3918400000, 0.4535713000, 0.5811001000, 0.9000095000", \ - "0.4881914000, 0.4961605000, 0.5139165000, 0.5480499000, 0.6106407000, 0.7370570000, 1.0561041000", \ - "0.7461818000, 0.7561841000, 0.7791648000, 0.8219742000, 0.8955376000, 1.0314473000, 1.3547290000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1050333000, 0.1122484000, 0.1286312000, 0.1643404000, 0.2489847000, 0.4828324000, 1.1647262000", \ - "0.1096510000, 0.1168499000, 0.1332986000, 0.1689454000, 0.2536436000, 0.4871061000, 1.1656470000", \ - "0.1201515000, 0.1273860000, 0.1438192000, 0.1794011000, 0.2643202000, 0.4988034000, 1.1756389000", \ - "0.1441348000, 0.1513029000, 0.1676184000, 0.2031787000, 0.2880543000, 0.5229254000, 1.2037449000", \ - "0.1907649000, 0.1985879000, 0.2159297000, 0.2522514000, 0.3373771000, 0.5717424000, 1.2498284000", \ - "0.2507905000, 0.2606417000, 0.2816330000, 0.3220653000, 0.4096064000, 0.6442112000, 1.3243433000", \ - "0.3058055000, 0.3184041000, 0.3457604000, 0.3970917000, 0.4910277000, 0.7254702000, 1.4013405000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0372907000, 0.0420529000, 0.0521418000, 0.0747246000, 0.1245541000, 0.2578816000, 0.6669384000", \ - "0.0373527000, 0.0420172000, 0.0522483000, 0.0745604000, 0.1240766000, 0.2578460000, 0.6663297000", \ - "0.0376137000, 0.0418960000, 0.0525535000, 0.0738797000, 0.1247241000, 0.2580659000, 0.6673616000", \ - "0.0374505000, 0.0421954000, 0.0522591000, 0.0745448000, 0.1248925000, 0.2580136000, 0.6663957000", \ - "0.0374832000, 0.0421017000, 0.0522024000, 0.0746345000, 0.1243935000, 0.2574878000, 0.6675880000", \ - "0.0429726000, 0.0481433000, 0.0577506000, 0.0780530000, 0.1267661000, 0.2596405000, 0.6667171000", \ - "0.0635160000, 0.0684442000, 0.0806234000, 0.1029216000, 0.1488126000, 0.2745806000, 0.6704828000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0276067000, 0.0329456000, 0.0464891000, 0.0832832000, 0.1925965000, 0.5254460000, 1.5019312000", \ - "0.0274933000, 0.0327520000, 0.0464662000, 0.0832891000, 0.1923605000, 0.5246484000, 1.5020880000", \ - "0.0274993000, 0.0327879000, 0.0466504000, 0.0832967000, 0.1927546000, 0.5262817000, 1.4977919000", \ - "0.0273244000, 0.0327755000, 0.0463673000, 0.0832565000, 0.1926780000, 0.5250734000, 1.5052536000", \ - "0.0321024000, 0.0368920000, 0.0499159000, 0.0853623000, 0.1933846000, 0.5258446000, 1.5042806000", \ - "0.0433655000, 0.0485631000, 0.0610798000, 0.0942919000, 0.1974177000, 0.5250853000, 1.5037244000", \ - "0.0602757000, 0.0678859000, 0.0832618000, 0.1161651000, 0.2082423000, 0.5286051000, 1.4965142000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2291980000, 0.2368686000, 0.2541432000, 0.2874066000, 0.3498573000, 0.4785123000, 0.7980512000", \ - "0.2330599000, 0.2408463000, 0.2579801000, 0.2912630000, 0.3539025000, 0.4815481000, 0.8008234000", \ - "0.2433838000, 0.2511864000, 0.2683498000, 0.3015558000, 0.3642893000, 0.4929673000, 0.8121752000", \ - "0.2696691000, 0.2775351000, 0.2953073000, 0.3278757000, 0.3910939000, 0.5196604000, 0.8389157000", \ - "0.3378715000, 0.3456503000, 0.3626694000, 0.3960409000, 0.4574208000, 0.5860326000, 0.9059405000", \ - "0.4925489000, 0.5007434000, 0.5189996000, 0.5530894000, 0.6156108000, 0.7448655000, 1.0642646000", \ - "0.7543471000, 0.7649469000, 0.7878853000, 0.8307715000, 0.9050199000, 1.0419544000, 1.3656820000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1060241000, 0.1132372000, 0.1296707000, 0.1654746000, 0.2508506000, 0.4853928000, 1.1725056000", \ - "0.1104670000, 0.1176958000, 0.1341164000, 0.1699543000, 0.2552954000, 0.4905556000, 1.1730489000", \ - "0.1205622000, 0.1278080000, 0.1442356000, 0.1800631000, 0.2654157000, 0.5004771000, 1.1782796000", \ - "0.1445573000, 0.1517801000, 0.1681204000, 0.2037809000, 0.2890654000, 0.5235484000, 1.2050317000", \ - "0.1920711000, 0.1998864000, 0.2172576000, 0.2536556000, 0.3390875000, 0.5738194000, 1.2574701000", \ - "0.2524753000, 0.2623450000, 0.2833638000, 0.3238650000, 0.4114669000, 0.6466572000, 1.3229234000", \ - "0.3082269000, 0.3208085000, 0.3482002000, 0.3989356000, 0.4934975000, 0.7286819000, 1.4049801000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0385255000, 0.0435914000, 0.0535649000, 0.0768260000, 0.1264217000, 0.2605620000, 0.6679432000", \ - "0.0386419000, 0.0432988000, 0.0535694000, 0.0765490000, 0.1264777000, 0.2603499000, 0.6680884000", \ - "0.0387433000, 0.0430981000, 0.0542522000, 0.0756945000, 0.1264327000, 0.2605078000, 0.6680772000", \ - "0.0389480000, 0.0433240000, 0.0535552000, 0.0765401000, 0.1267097000, 0.2597164000, 0.6674722000", \ - "0.0386723000, 0.0433401000, 0.0536170000, 0.0766306000, 0.1267352000, 0.2601387000, 0.6673060000", \ - "0.0441205000, 0.0486532000, 0.0584373000, 0.0796210000, 0.1285066000, 0.2616820000, 0.6680675000", \ - "0.0647569000, 0.0706048000, 0.0819447000, 0.1046523000, 0.1517145000, 0.2764296000, 0.6719225000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0272801000, 0.0326571000, 0.0461306000, 0.0829780000, 0.1921630000, 0.5259662000, 1.5008922000", \ - "0.0273805000, 0.0326348000, 0.0461103000, 0.0829001000, 0.1922381000, 0.5251670000, 1.5056167000", \ - "0.0272484000, 0.0326319000, 0.0461691000, 0.0829331000, 0.1925967000, 0.5262088000, 1.4980267000", \ - "0.0272137000, 0.0325863000, 0.0462681000, 0.0830536000, 0.1922926000, 0.5256103000, 1.5066720000", \ - "0.0316147000, 0.0369586000, 0.0496925000, 0.0850606000, 0.1931486000, 0.5255938000, 1.5053726000", \ - "0.0429034000, 0.0482531000, 0.0608390000, 0.0940453000, 0.1977195000, 0.5261409000, 1.5015221000", \ - "0.0598201000, 0.0670854000, 0.0828581000, 0.1150082000, 0.2082363000, 0.5286312000, 1.4943067000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2322584000, 0.2398856000, 0.2567114000, 0.2896509000, 0.3515533000, 0.4791529000, 0.7980492000", \ - "0.2375990000, 0.2452850000, 0.2620745000, 0.2950411000, 0.3569521000, 0.4845245000, 0.8034615000", \ - "0.2502997000, 0.2579369000, 0.2747797000, 0.3076533000, 0.3695943000, 0.4971608000, 0.8161092000", \ - "0.2773061000, 0.2849156000, 0.3017887000, 0.3346738000, 0.3966034000, 0.5242062000, 0.8431303000", \ - "0.3377408000, 0.3454186000, 0.3622237000, 0.3952593000, 0.4571660000, 0.5846537000, 0.9036172000", \ - "0.4687092000, 0.4768247000, 0.4945345000, 0.5288184000, 0.5918155000, 0.7203693000, 1.0394393000", \ - "0.7007833000, 0.7102671000, 0.7310833000, 0.7705199000, 0.8419581000, 0.9789425000, 1.3017390000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1135210000, 0.1203043000, 0.1357975000, 0.1704168000, 0.2549927000, 0.4896232000, 1.1665913000", \ - "0.1178334000, 0.1246170000, 0.1401090000, 0.1747740000, 0.2593028000, 0.4942225000, 1.1715122000", \ - "0.1271759000, 0.1339409000, 0.1494654000, 0.1840495000, 0.2686191000, 0.5043094000, 1.1796594000", \ - "0.1481737000, 0.1549515000, 0.1704587000, 0.2050298000, 0.2894962000, 0.5244895000, 1.2017972000", \ - "0.1907664000, 0.1978555000, 0.2139821000, 0.2489621000, 0.3335869000, 0.5687599000, 1.2457594000", \ - "0.2537553000, 0.2621386000, 0.2803526000, 0.3179052000, 0.4041472000, 0.6387659000, 1.3158107000", \ - "0.3215601000, 0.3322934000, 0.3557108000, 0.3998770000, 0.4900202000, 0.7251991000, 1.4012739000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0373774000, 0.0421491000, 0.0522028000, 0.0747130000, 0.1241769000, 0.2576467000, 0.6672146000", \ - "0.0373719000, 0.0421349000, 0.0521973000, 0.0749282000, 0.1241988000, 0.2576650000, 0.6671894000", \ - "0.0373698000, 0.0420324000, 0.0521033000, 0.0740290000, 0.1243384000, 0.2575276000, 0.6673880000", \ - "0.0376502000, 0.0421724000, 0.0522513000, 0.0746099000, 0.1242109000, 0.2576539000, 0.6671969000", \ - "0.0376453000, 0.0420920000, 0.0521755000, 0.0742150000, 0.1241044000, 0.2576886000, 0.6675919000", \ - "0.0417578000, 0.0467199000, 0.0567211000, 0.0779986000, 0.1269730000, 0.2587495000, 0.6676521000", \ - "0.0547708000, 0.0595769000, 0.0710187000, 0.0949396000, 0.1441320000, 0.2727310000, 0.6703454000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0250716000, 0.0305454000, 0.0441561000, 0.0810729000, 0.1916793000, 0.5258385000, 1.5007355000", \ - "0.0250952000, 0.0305362000, 0.0440997000, 0.0811223000, 0.1918375000, 0.5264102000, 1.5009861000", \ - "0.0250446000, 0.0305033000, 0.0441248000, 0.0811138000, 0.1919274000, 0.5254501000, 1.4979294000", \ - "0.0250796000, 0.0304592000, 0.0440750000, 0.0811601000, 0.1916660000, 0.5264761000, 1.5010794000", \ - "0.0273049000, 0.0328264000, 0.0460283000, 0.0823161000, 0.1922218000, 0.5261017000, 1.5000144000", \ - "0.0340184000, 0.0396821000, 0.0533156000, 0.0878521000, 0.1947304000, 0.5257016000, 1.4967336000", \ - "0.0468232000, 0.0537900000, 0.0686532000, 0.1024328000, 0.2015250000, 0.5273597000, 1.4956962000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.2899485000, 0.2977517000, 0.3149048000, 0.3481579000, 0.4100283000, 0.5381606000, 0.8573209000", \ - "0.2950588000, 0.3028696000, 0.3200057000, 0.3533574000, 0.4156793000, 0.5441079000, 0.8631392000", \ - "0.3054595000, 0.3132880000, 0.3304446000, 0.3637566000, 0.4259196000, 0.5538374000, 0.8736605000", \ - "0.3258045000, 0.3335832000, 0.3507819000, 0.3839432000, 0.4466079000, 0.5743283000, 0.8935738000", \ - "0.3539222000, 0.3617136000, 0.3788440000, 0.4121942000, 0.4746505000, 0.6031519000, 0.9220164000", \ - "0.3871556000, 0.3949853000, 0.4121197000, 0.4454498000, 0.5077556000, 0.6359973000, 0.9555170000", \ - "0.4139463000, 0.4217426000, 0.4388599000, 0.4719985000, 0.5345140000, 0.6630203000, 0.9826023000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.1843353000, 0.1910715000, 0.2065275000, 0.2410281000, 0.3249605000, 0.5587866000, 1.2352246000", \ - "0.1890048000, 0.1958210000, 0.2113813000, 0.2458284000, 0.3298622000, 0.5637413000, 1.2403031000", \ - "0.2016874000, 0.2084499000, 0.2240226000, 0.2584710000, 0.3424876000, 0.5771847000, 1.2528576000", \ - "0.2331775000, 0.2399386000, 0.2554095000, 0.2899029000, 0.3738539000, 0.6077613000, 1.2843776000", \ - "0.2946129000, 0.3014336000, 0.3169423000, 0.3514230000, 0.4353911000, 0.6694295000, 1.3463636000", \ - "0.3934688000, 0.4002686000, 0.4159352000, 0.4505656000, 0.5344948000, 0.7681787000, 1.4443219000", \ - "0.5515511000, 0.5585565000, 0.5744599000, 0.6093293000, 0.6935716000, 0.9275097000, 1.6044693000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0385192000, 0.0433245000, 0.0536063000, 0.0764285000, 0.1270985000, 0.2602140000, 0.6680930000", \ - "0.0385263000, 0.0432227000, 0.0534796000, 0.0756559000, 0.1264266000, 0.2606353000, 0.6679738000", \ - "0.0385915000, 0.0433128000, 0.0540445000, 0.0765740000, 0.1269620000, 0.2604621000, 0.6671147000", \ - "0.0385474000, 0.0433582000, 0.0539771000, 0.0755869000, 0.1263576000, 0.2608663000, 0.6679436000", \ - "0.0386492000, 0.0434426000, 0.0537612000, 0.0759627000, 0.1264560000, 0.2606791000, 0.6675742000", \ - "0.0386252000, 0.0433200000, 0.0536925000, 0.0767460000, 0.1257589000, 0.2602200000, 0.6684783000", \ - "0.0387726000, 0.0434168000, 0.0537037000, 0.0759754000, 0.1262168000, 0.2602693000, 0.6651665000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014501200, 0.0042056800, 0.0121975000, 0.0353755000, 0.1025970000, 0.2975560000"); - values("0.0256273000, 0.0310306000, 0.0447637000, 0.0816115000, 0.1921240000, 0.5261404000, 1.4995976000", \ - "0.0256355000, 0.0311683000, 0.0446982000, 0.0816224000, 0.1919110000, 0.5262204000, 1.5013500000", \ - "0.0255589000, 0.0310688000, 0.0446811000, 0.0817063000, 0.1918189000, 0.5258102000, 1.5012224000", \ - "0.0256616000, 0.0310570000, 0.0447679000, 0.0816377000, 0.1920861000, 0.5263128000, 1.5001985000", \ - "0.0255972000, 0.0310939000, 0.0447313000, 0.0816292000, 0.1920941000, 0.5263437000, 1.5012636000", \ - "0.0260849000, 0.0315784000, 0.0451367000, 0.0819214000, 0.1918482000, 0.5259350000, 1.4975690000", \ - "0.0267672000, 0.0323233000, 0.0462770000, 0.0826672000, 0.1923071000, 0.5259824000, 1.4995153000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2_4") { - leakage_power () { - value : 0.0094639000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0061145000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0103948000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0065188000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0098170000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0081835000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0089766000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0062184000; - when : "A0&A1&!S"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__mux2"; - cell_leakage_power : 0.0082109340; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0022690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045371000, 0.0045299000, 0.0045131000, 0.0045161000, 0.0045229000, 0.0045386000, 0.0045750000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002570100, -0.002604700, -0.002684400, -0.002680400, -0.002671000, -0.002649300, -0.002599300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024080000; - } - pin ("A1") { - capacitance : 0.0022800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045463000, 0.0045374000, 0.0045171000, 0.0045213000, 0.0045310000, 0.0045534000, 0.0046051000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002680000, -0.002697500, -0.002737700, -0.002729700, -0.002711200, -0.002668600, -0.002570600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024190000; - } - pin ("S") { - capacitance : 0.0051430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0049150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158524000, 0.0156876000, 0.0153077000, 0.0154604000, 0.0158125000, 0.0166238000, 0.0184943000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001837200, -0.002004500, -0.002390200, -0.002250300, -0.001927800, -0.001184500, 0.0005290000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0053720000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S) | (A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0235614000, 0.0215959000, 0.0159250000, -9.72000e-05, -0.054410200, -0.239014500, -0.836066300", \ - "0.0233265000, 0.0215110000, 0.0158218000, -0.000222600, -0.054754100, -0.239044800, -0.836150700", \ - "0.0232613000, 0.0213001000, 0.0156207000, -0.000394000, -0.054753000, -0.239347500, -0.836398400", \ - "0.0230860000, 0.0211448000, 0.0154231000, -0.000650300, -0.055185900, -0.239683600, -0.836668300", \ - "0.0227519000, 0.0207994000, 0.0151027000, -0.000878200, -0.055355400, -0.239709600, -0.836697000", \ - "0.0238352000, 0.0218331000, 0.0159411000, -0.000542500, -0.055081600, -0.239564000, -0.836019900", \ - "0.0340524000, 0.0317810000, 0.0250715000, 0.0057258000, -0.053257900, -0.237907500, -0.835032300"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0253535000, 0.0272446000, 0.0333299000, 0.0524784000, 0.1115670000, 0.2970805000, 0.8903869000", \ - "0.0254272000, 0.0273128000, 0.0333593000, 0.0525156000, 0.1116906000, 0.2971525000, 0.8855669000", \ - "0.0255015000, 0.0273695000, 0.0334023000, 0.0525123000, 0.1116121000, 0.2972278000, 0.8888108000", \ - "0.0252987000, 0.0271549000, 0.0331703000, 0.0522512000, 0.1111555000, 0.2967888000, 0.8846305000", \ - "0.0253836000, 0.0271805000, 0.0330137000, 0.0518103000, 0.1105078000, 0.2961894000, 0.8896572000", \ - "0.0272822000, 0.0289982000, 0.0345674000, 0.0527715000, 0.1107110000, 0.2954530000, 0.8919296000", \ - "0.0298364000, 0.0313595000, 0.0366959000, 0.0544540000, 0.1127119000, 0.2971669000, 0.8847782000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0238751000, 0.0220219000, 0.0164593000, 0.0004913000, -0.053592500, -0.237584000, -0.834418400", \ - "0.0236952000, 0.0218349000, 0.0161992000, 0.0003435000, -0.053647700, -0.237580200, -0.834431200", \ - "0.0235408000, 0.0215965000, 0.0159928000, 0.0002266000, -0.053679900, -0.237823100, -0.834694400", \ - "0.0234138000, 0.0214702000, 0.0158643000, -2.56000e-05, -0.054213100, -0.238223000, -0.834971300", \ - "0.0230392000, 0.0211519000, 0.0155231000, -0.000429600, -0.054458500, -0.238491000, -0.835111200", \ - "0.0241349000, 0.0220713000, 0.0162225000, -0.000154800, -0.054439200, -0.238473400, -0.834934100", \ - "0.0342251000, 0.0319834000, 0.0253059000, 0.0059748000, -0.052704900, -0.237073900, -0.833655800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0256248000, 0.0274686000, 0.0334444000, 0.0523542000, 0.1108078000, 0.2955838000, 0.8835579000", \ - "0.0256749000, 0.0275218000, 0.0335104000, 0.0524366000, 0.1107439000, 0.2957006000, 0.8869848000", \ - "0.0256238000, 0.0274685000, 0.0334393000, 0.0523558000, 0.1108426000, 0.2954312000, 0.8836645000", \ - "0.0254537000, 0.0272945000, 0.0332394000, 0.0520766000, 0.1104867000, 0.2953117000, 0.8880786000", \ - "0.0255376000, 0.0273151000, 0.0332089000, 0.0517447000, 0.1100611000, 0.2950963000, 0.8868418000", \ - "0.0273381000, 0.0290392000, 0.0345767000, 0.0525515000, 0.1104495000, 0.2947491000, 0.8863358000", \ - "0.0299940000, 0.0314584000, 0.0368267000, 0.0544667000, 0.1124975000, 0.2966064000, 0.8840131000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0265855000, 0.0246923000, 0.0190874000, 0.0031182000, -0.050958000, -0.234976500, -0.831664000", \ - "0.0264714000, 0.0245312000, 0.0189288000, 0.0031071000, -0.050896800, -0.234878500, -0.831640300", \ - "0.0265346000, 0.0246113000, 0.0189583000, 0.0032037000, -0.050866400, -0.234725100, -0.831431900", \ - "0.0261954000, 0.0242528000, 0.0186491000, 0.0028266000, -0.051079800, -0.235265200, -0.831824800", \ - "0.0258628000, 0.0239661000, 0.0183112000, 0.0024919000, -0.051609700, -0.235605100, -0.832070300", \ - "0.0292418000, 0.0272759000, 0.0213473000, 0.0031362000, -0.051669700, -0.235688800, -0.832292000", \ - "0.0338863000, 0.0319310000, 0.0260394000, 0.0080647000, -0.049381200, -0.234875500, -0.832033500"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188490, 0.0163784700, 0.0524052200, 0.1676779000, 0.5365088000"); - values("0.0288505000, 0.0306959000, 0.0366606000, 0.0557460000, 0.1148111000, 0.3005932000, 0.8927778000", \ - "0.0287147000, 0.0306323000, 0.0366113000, 0.0557352000, 0.1146432000, 0.3005667000, 0.8928133000", \ - "0.0289602000, 0.0307985000, 0.0368348000, 0.0559894000, 0.1148627000, 0.3008167000, 0.8930506000", \ - "0.0289249000, 0.0307511000, 0.0367548000, 0.0558074000, 0.1148348000, 0.3009095000, 0.8955482000", \ - "0.0287855000, 0.0306504000, 0.0366906000, 0.0557819000, 0.1148679000, 0.3005689000, 0.8905212000", \ - "0.0287030000, 0.0305362000, 0.0362932000, 0.0556433000, 0.1145998000, 0.3002060000, 0.8915131000", \ - "0.0296295000, 0.0314729000, 0.0372353000, 0.0559421000, 0.1151899000, 0.3013293000, 0.8908278000"); - } - } - max_capacitance : 0.5365090000; - max_transition : 1.5070850000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2396542000, 0.2449914000, 0.2585316000, 0.2882858000, 0.3470177000, 0.4713033000, 0.7937889000", \ - "0.2434491000, 0.2487879000, 0.2623209000, 0.2920213000, 0.3511551000, 0.4750150000, 0.7971759000", \ - "0.2531122000, 0.2584449000, 0.2719733000, 0.3017252000, 0.3604892000, 0.4850663000, 0.8069095000", \ - "0.2781665000, 0.2834288000, 0.2969545000, 0.3265528000, 0.3857107000, 0.5100676000, 0.8318106000", \ - "0.3421492000, 0.3474384000, 0.3609900000, 0.3906718000, 0.4494437000, 0.5741646000, 0.8962022000", \ - "0.4885490000, 0.4942979000, 0.5084284000, 0.5390788000, 0.5990672000, 0.7243008000, 1.0447034000", \ - "0.7321493000, 0.7390590000, 0.7566595000, 0.7954612000, 0.8659126000, 0.9989223000, 1.3254950000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1076029000, 0.1124912000, 0.1252908000, 0.1558777000, 0.2322754000, 0.4554024000, 1.1689735000", \ - "0.1119979000, 0.1168567000, 0.1296591000, 0.1602757000, 0.2366598000, 0.4603691000, 1.1744608000", \ - "0.1220379000, 0.1268845000, 0.1396772000, 0.1702854000, 0.2465310000, 0.4708942000, 1.1787220000", \ - "0.1458367000, 0.1506509000, 0.1634023000, 0.1939256000, 0.2701418000, 0.4935894000, 1.2052476000", \ - "0.1919754000, 0.1971696000, 0.2106148000, 0.2418219000, 0.3183696000, 0.5417120000, 1.2546740000", \ - "0.2491014000, 0.2555695000, 0.2718557000, 0.3073129000, 0.3864919000, 0.6103562000, 1.3225814000", \ - "0.3004427000, 0.3085365000, 0.3295776000, 0.3742343000, 0.4612761000, 0.6862948000, 1.3942409000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0419489000, 0.0450491000, 0.0533416000, 0.0713630000, 0.1164523000, 0.2389170000, 0.6418074000", \ - "0.0423577000, 0.0452159000, 0.0530100000, 0.0714519000, 0.1158716000, 0.2389787000, 0.6427172000", \ - "0.0419461000, 0.0450410000, 0.0533011000, 0.0713339000, 0.1162817000, 0.2388122000, 0.6429753000", \ - "0.0422067000, 0.0453474000, 0.0531627000, 0.0714769000, 0.1159642000, 0.2389695000, 0.6423823000", \ - "0.0420359000, 0.0450779000, 0.0533186000, 0.0715615000, 0.1158531000, 0.2389787000, 0.6418046000", \ - "0.0481649000, 0.0509478000, 0.0594731000, 0.0759228000, 0.1184935000, 0.2401972000, 0.6413028000", \ - "0.0701557000, 0.0732068000, 0.0835570000, 0.1027374000, 0.1436823000, 0.2571528000, 0.6475925000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0282299000, 0.0315873000, 0.0417286000, 0.0709484000, 0.1644598000, 0.4797374000, 1.5070850000", \ - "0.0281623000, 0.0317287000, 0.0416625000, 0.0710191000, 0.1643783000, 0.4799704000, 1.4998202000", \ - "0.0280865000, 0.0316833000, 0.0415918000, 0.0709382000, 0.1642797000, 0.4789051000, 1.5035738000", \ - "0.0281715000, 0.0316619000, 0.0417347000, 0.0710564000, 0.1645158000, 0.4797994000, 1.4976305000", \ - "0.0323733000, 0.0359319000, 0.0454799000, 0.0733782000, 0.1651289000, 0.4796687000, 1.5056257000", \ - "0.0435036000, 0.0469747000, 0.0568383000, 0.0833884000, 0.1707205000, 0.4803062000, 1.5041972000", \ - "0.0602040000, 0.0646286000, 0.0769406000, 0.1043237000, 0.1834515000, 0.4821042000, 1.4966556000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2293153000, 0.2344532000, 0.2475364000, 0.2764047000, 0.3340518000, 0.4558681000, 0.7762098000", \ - "0.2333582000, 0.2384475000, 0.2515573000, 0.2803510000, 0.3380849000, 0.4597673000, 0.7799992000", \ - "0.2432833000, 0.2483670000, 0.2614885000, 0.2903676000, 0.3475824000, 0.4698403000, 0.7904974000", \ - "0.2686313000, 0.2738474000, 0.2870163000, 0.3157725000, 0.3731340000, 0.4956465000, 0.8158034000", \ - "0.3335452000, 0.3386553000, 0.3517520000, 0.3805337000, 0.4376953000, 0.5602366000, 0.8806508000", \ - "0.4804405000, 0.4859148000, 0.4999232000, 0.5299616000, 0.5884312000, 0.7115687000, 1.0319559000", \ - "0.7226795000, 0.7294222000, 0.7468625000, 0.7847863000, 0.8544193000, 0.9850215000, 1.3098453000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1071501000, 0.1120359000, 0.1247598000, 0.1551275000, 0.2308216000, 0.4540089000, 1.1671663000", \ - "0.1115124000, 0.1164018000, 0.1290751000, 0.1594786000, 0.2352531000, 0.4579540000, 1.1752420000", \ - "0.1214234000, 0.1262974000, 0.1390442000, 0.1693840000, 0.2451695000, 0.4680717000, 1.1850583000", \ - "0.1452167000, 0.1500393000, 0.1627101000, 0.1930497000, 0.2688340000, 0.4916807000, 1.2025658000", \ - "0.1911788000, 0.1963700000, 0.2098402000, 0.2409639000, 0.3172179000, 0.5398411000, 1.2531034000", \ - "0.2477681000, 0.2542990000, 0.2707410000, 0.3060742000, 0.3851184000, 0.6088247000, 1.3197888000", \ - "0.2985973000, 0.3067560000, 0.3276782000, 0.3722873000, 0.4595256000, 0.6842397000, 1.3913007000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0400235000, 0.0427181000, 0.0509758000, 0.0686527000, 0.1124299000, 0.2344826000, 0.6401817000", \ - "0.0400915000, 0.0428632000, 0.0506132000, 0.0685193000, 0.1123560000, 0.2355849000, 0.6405299000", \ - "0.0397063000, 0.0426927000, 0.0506408000, 0.0685074000, 0.1130286000, 0.2353013000, 0.6393992000", \ - "0.0396452000, 0.0426673000, 0.0506195000, 0.0687445000, 0.1123494000, 0.2349922000, 0.6399907000", \ - "0.0399211000, 0.0426524000, 0.0506611000, 0.0684933000, 0.1120878000, 0.2351456000, 0.6399921000", \ - "0.0460054000, 0.0493302000, 0.0575608000, 0.0735980000, 0.1153375000, 0.2365222000, 0.6410413000", \ - "0.0674956000, 0.0709021000, 0.0805287000, 0.1000128000, 0.1404728000, 0.2533022000, 0.6448000000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0282581000, 0.0317752000, 0.0419201000, 0.0712000000, 0.1647226000, 0.4804305000, 1.4997558000", \ - "0.0282093000, 0.0317498000, 0.0418827000, 0.0712361000, 0.1646328000, 0.4796853000, 1.5054789000", \ - "0.0281982000, 0.0317518000, 0.0419039000, 0.0712345000, 0.1645607000, 0.4791212000, 1.5019149000", \ - "0.0283104000, 0.0318024000, 0.0419141000, 0.0712851000, 0.1646346000, 0.4786044000, 1.5050682000", \ - "0.0327145000, 0.0363219000, 0.0456317000, 0.0735617000, 0.1652280000, 0.4797605000, 1.5038795000", \ - "0.0441737000, 0.0476253000, 0.0570830000, 0.0838336000, 0.1705160000, 0.4790737000, 1.5037072000", \ - "0.0610779000, 0.0652239000, 0.0777101000, 0.1048619000, 0.1838104000, 0.4822488000, 1.4981568000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2647815000, 0.2700379000, 0.2835781000, 0.3131096000, 0.3720833000, 0.4965990000, 0.8183117000", \ - "0.2694579000, 0.2746968000, 0.2882472000, 0.3179215000, 0.3768215000, 0.5013708000, 0.8229767000", \ - "0.2813058000, 0.2865668000, 0.3000117000, 0.3297007000, 0.3887527000, 0.5132084000, 0.8349961000", \ - "0.3064977000, 0.3117793000, 0.3253166000, 0.3549584000, 0.4140378000, 0.5384728000, 0.8604151000", \ - "0.3624986000, 0.3677519000, 0.3812791000, 0.4108620000, 0.4698792000, 0.5944131000, 0.9163603000", \ - "0.4851006000, 0.4907071000, 0.5047538000, 0.5350485000, 0.5954102000, 0.7208018000, 1.0429865000", \ - "0.7052149000, 0.7114823000, 0.7276247000, 0.7626594000, 0.8303194000, 0.9644067000, 1.2920167000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1202902000, 0.1247851000, 0.1367324000, 0.1658167000, 0.2400991000, 0.4624854000, 1.1710730000", \ - "0.1246049000, 0.1290832000, 0.1410221000, 0.1701074000, 0.2444247000, 0.4665414000, 1.1757895000", \ - "0.1336449000, 0.1381383000, 0.1500913000, 0.1791789000, 0.2535006000, 0.4758134000, 1.1848149000", \ - "0.1537526000, 0.1583924000, 0.1702594000, 0.1992509000, 0.2736165000, 0.4958289000, 1.2052722000", \ - "0.1951597000, 0.1998729000, 0.2122260000, 0.2418515000, 0.3165506000, 0.5401098000, 1.2486165000", \ - "0.2545291000, 0.2600989000, 0.2741367000, 0.3062432000, 0.3832018000, 0.6064043000, 1.3151646000", \ - "0.3132854000, 0.3202728000, 0.3383790000, 0.3768537000, 0.4587906000, 0.6830290000, 1.3905722000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0423034000, 0.0454536000, 0.0529528000, 0.0717153000, 0.1164106000, 0.2387983000, 0.6414752000", \ - "0.0422515000, 0.0454460000, 0.0530082000, 0.0715049000, 0.1163866000, 0.2388101000, 0.6423133000", \ - "0.0423398000, 0.0454612000, 0.0535616000, 0.0716260000, 0.1165245000, 0.2387298000, 0.6412445000", \ - "0.0420588000, 0.0451243000, 0.0534310000, 0.0716154000, 0.1164637000, 0.2386028000, 0.6426701000", \ - "0.0421384000, 0.0453060000, 0.0534566000, 0.0715708000, 0.1161676000, 0.2389273000, 0.6414831000", \ - "0.0461317000, 0.0490427000, 0.0577674000, 0.0755052000, 0.1188151000, 0.2402132000, 0.6413706000", \ - "0.0585700000, 0.0619488000, 0.0708485000, 0.0904400000, 0.1346512000, 0.2542268000, 0.6479114000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0259369000, 0.0294375000, 0.0395616000, 0.0691416000, 0.1635998000, 0.4801837000, 1.5013901000", \ - "0.0259922000, 0.0295072000, 0.0395981000, 0.0691244000, 0.1637122000, 0.4801319000, 1.5017149000", \ - "0.0258255000, 0.0295490000, 0.0395529000, 0.0691539000, 0.1636710000, 0.4802042000, 1.5016003000", \ - "0.0258353000, 0.0294237000, 0.0395579000, 0.0690663000, 0.1637084000, 0.4793630000, 1.5018277000", \ - "0.0279282000, 0.0315179000, 0.0417701000, 0.0704023000, 0.1641009000, 0.4804810000, 1.5015535000", \ - "0.0345659000, 0.0381425000, 0.0484919000, 0.0765681000, 0.1674592000, 0.4802889000, 1.5010941000", \ - "0.0475344000, 0.0520490000, 0.0636653000, 0.0908110000, 0.1754573000, 0.4821050000, 1.4985817000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.2618348000, 0.2669170000, 0.2800371000, 0.3086607000, 0.3662061000, 0.4878843000, 0.8081245000", \ - "0.2671290000, 0.2722079000, 0.2853054000, 0.3140764000, 0.3712053000, 0.4933775000, 0.8140080000", \ - "0.2784553000, 0.2835991000, 0.2967153000, 0.3255679000, 0.3829634000, 0.5049713000, 0.8252728000", \ - "0.2961605000, 0.3012476000, 0.3143673000, 0.3431992000, 0.4004361000, 0.5229281000, 0.8434381000", \ - "0.3172549000, 0.3223930000, 0.3354390000, 0.3643176000, 0.4219616000, 0.5446315000, 0.8649041000", \ - "0.3388599000, 0.3439436000, 0.3569815000, 0.3856718000, 0.4430451000, 0.5644346000, 0.8847202000", \ - "0.3435545000, 0.3486607000, 0.3615666000, 0.3903403000, 0.4479884000, 0.5702880000, 0.8897774000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.1635571000, 0.1680837000, 0.1800659000, 0.2094579000, 0.2847063000, 0.5083410000, 1.2185063000", \ - "0.1685875000, 0.1731364000, 0.1851825000, 0.2145893000, 0.2898021000, 0.5132560000, 1.2233454000", \ - "0.1818221000, 0.1863743000, 0.1984454000, 0.2278506000, 0.3030614000, 0.5267161000, 1.2363415000", \ - "0.2124509000, 0.2170056000, 0.2290347000, 0.2583826000, 0.3335257000, 0.5575088000, 1.2686948000", \ - "0.2653401000, 0.2698602000, 0.2819521000, 0.3113139000, 0.3865016000, 0.6107175000, 1.3184036000", \ - "0.3482229000, 0.3527841000, 0.3648698000, 0.3942517000, 0.4693429000, 0.6929177000, 1.4025998000", \ - "0.4834953000, 0.4880993000, 0.5002559000, 0.5296625000, 0.6048361000, 0.8286065000, 1.5366515000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0399603000, 0.0429934000, 0.0507239000, 0.0685410000, 0.1121643000, 0.2349705000, 0.6391249000", \ - "0.0397001000, 0.0426983000, 0.0505940000, 0.0685361000, 0.1127420000, 0.2352543000, 0.6391663000", \ - "0.0397117000, 0.0427458000, 0.0508281000, 0.0693979000, 0.1126737000, 0.2349795000, 0.6398995000", \ - "0.0397079000, 0.0426886000, 0.0505884000, 0.0686814000, 0.1131056000, 0.2350135000, 0.6391133000", \ - "0.0399550000, 0.0426807000, 0.0505514000, 0.0692694000, 0.1118205000, 0.2347474000, 0.6402937000", \ - "0.0395662000, 0.0425448000, 0.0501752000, 0.0680633000, 0.1116922000, 0.2335254000, 0.6397117000", \ - "0.0397107000, 0.0427598000, 0.0509466000, 0.0685375000, 0.1127574000, 0.2346350000, 0.6381399000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015998200, 0.0051188500, 0.0163785000, 0.0524052000, 0.1676780000, 0.5365090000"); - values("0.0260028000, 0.0295519000, 0.0398411000, 0.0690283000, 0.1637371000, 0.4795176000, 1.5014437000", \ - "0.0260779000, 0.0296226000, 0.0396788000, 0.0691830000, 0.1637424000, 0.4800179000, 1.5009388000", \ - "0.0260022000, 0.0296353000, 0.0396534000, 0.0691849000, 0.1636989000, 0.4803045000, 1.5008818000", \ - "0.0258805000, 0.0294420000, 0.0397749000, 0.0689361000, 0.1633879000, 0.4796507000, 1.5030462000", \ - "0.0259818000, 0.0296219000, 0.0397379000, 0.0690883000, 0.1634348000, 0.4812536000, 1.4995432000", \ - "0.0261348000, 0.0296822000, 0.0398256000, 0.0692629000, 0.1633518000, 0.4791000000, 1.5015307000", \ - "0.0265820000, 0.0301104000, 0.0404191000, 0.0695683000, 0.1635548000, 0.4797906000, 1.4986957000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2_8") { - leakage_power () { - value : 0.0094897000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0078680000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0078450000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0094288000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0109275000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0062551000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0074153000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0511929000; - when : "A0&A1&!S"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__mux2"; - cell_leakage_power : 0.0138027900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0047680000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092736000, 0.0092463000, 0.0091835000, 0.0091952000, 0.0092219000, 0.0092835000, 0.0094257000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005318400, -0.005389900, -0.005554900, -0.005544100, -0.005519200, -0.005462000, -0.005329700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050450000; - } - pin ("A1") { - capacitance : 0.0051000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0048030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101062000, 0.0100851000, 0.0100365000, 0.0100465000, 0.0100693000, 0.0101223000, 0.0102443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006841800, -0.006879000, -0.006964500, -0.006952000, -0.006923100, -0.006856400, -0.006703000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0053980000; - } - pin ("S") { - capacitance : 0.0078480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0074980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0251372000, 0.0249240000, 0.0244328000, 0.0245301000, 0.0247545000, 0.0252715000, 0.0264635000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001849000, -0.001990100, -0.002315400, -0.002250300, -0.002100200, -0.001754000, -0.000956100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0081970000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S) | (A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0475176000, 0.0453009000, 0.0379034000, 0.0149690000, -0.064643500, -0.366159800, -1.443295300", \ - "0.0473448000, 0.0451423000, 0.0375754000, 0.0146387000, -0.064780200, -0.366384100, -1.443390000", \ - "0.0469749000, 0.0446813000, 0.0371668000, 0.0144120000, -0.064722700, -0.366569400, -1.443720800", \ - "0.0465858000, 0.0442983000, 0.0368192000, 0.0138584000, -0.065682300, -0.367165900, -1.444138200", \ - "0.0458674000, 0.0435781000, 0.0360949000, 0.0131473000, -0.066458100, -0.367874600, -1.444825700", \ - "0.0470182000, 0.0446792000, 0.0371166000, 0.0137892000, -0.066457900, -0.368037900, -1.444683900", \ - "0.0625961000, 0.0600190000, 0.0515056000, 0.0221716000, -0.063480700, -0.365581300, -1.443363200"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0493270000, 0.0514197000, 0.0589835000, 0.0854399000, 0.1748714000, 0.4806108000, 1.5411323000", \ - "0.0493855000, 0.0514522000, 0.0589327000, 0.0856069000, 0.1749464000, 0.4806236000, 1.5488793000", \ - "0.0495278000, 0.0516314000, 0.0591843000, 0.0857264000, 0.1749552000, 0.4806124000, 1.5512131000", \ - "0.0493023000, 0.0513734000, 0.0589409000, 0.0853676000, 0.1744357000, 0.4803662000, 1.5410443000", \ - "0.0492455000, 0.0512962000, 0.0585556000, 0.0844781000, 0.1730235000, 0.4791656000, 1.5409945000", \ - "0.0518309000, 0.0537632000, 0.0607775000, 0.0854035000, 0.1732278000, 0.4776567000, 1.5401588000", \ - "0.0552945000, 0.0570630000, 0.0637220000, 0.0878133000, 0.1750417000, 0.4785070000, 1.5423784000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0475733000, 0.0454269000, 0.0380766000, 0.0152547000, -0.063609000, -0.364260000, -1.440918000", \ - "0.0481097000, 0.0452765000, 0.0383350000, 0.0158627000, -0.063506700, -0.364386900, -1.441030200", \ - "0.0474139000, 0.0451964000, 0.0377434000, 0.0150268000, -0.064215000, -0.364882800, -1.441263100", \ - "0.0465109000, 0.0443015000, 0.0369679000, 0.0144749000, -0.064572500, -0.365437500, -1.441917100", \ - "0.0459792000, 0.0437025000, 0.0363012000, 0.0136078000, -0.065608300, -0.366303800, -1.442687000", \ - "0.0471115000, 0.0449474000, 0.0372593000, 0.0141872000, -0.065765800, -0.366590800, -1.442586500", \ - "0.0632563000, 0.0606822000, 0.0520997000, 0.0247762000, -0.065614800, -0.364235700, -1.441319800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0504801000, 0.0526082000, 0.0600386000, 0.0861954000, 0.1746111000, 0.4786556000, 1.5405875000", \ - "0.0505839000, 0.0527265000, 0.0601939000, 0.0862187000, 0.1745661000, 0.4788968000, 1.5463801000", \ - "0.0505000000, 0.0526577000, 0.0600921000, 0.0861733000, 0.1746698000, 0.4791070000, 1.5406477000", \ - "0.0504092000, 0.0525423000, 0.0599140000, 0.0858984000, 0.1741932000, 0.4788056000, 1.5484071000", \ - "0.0505969000, 0.0526386000, 0.0599037000, 0.0851555000, 0.1732398000, 0.4781945000, 1.5459603000", \ - "0.0527936000, 0.0547106000, 0.0616050000, 0.0860966000, 0.1735241000, 0.4769855000, 1.5447417000", \ - "0.0562838000, 0.0580209000, 0.0646174000, 0.0887676000, 0.1759324000, 0.4787685000, 1.5410863000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0529259000, 0.0507201000, 0.0432576000, 0.0205240000, -0.058181700, -0.358934700, -1.435494100", \ - "0.0530244000, 0.0507373000, 0.0432776000, 0.0209954000, -0.058116200, -0.359043900, -1.435531700", \ - "0.0529069000, 0.0506056000, 0.0431735000, 0.0206232000, -0.058338800, -0.359014700, -1.435476300", \ - "0.0526403000, 0.0504167000, 0.0429639000, 0.0201907000, -0.058830900, -0.359457100, -1.435909900", \ - "0.0522231000, 0.0500090000, 0.0425682000, 0.0198687000, -0.059001400, -0.359889800, -1.436063500", \ - "0.0523215000, 0.0500042000, 0.0426928000, 0.0198390000, -0.059200300, -0.359981900, -1.436416900", \ - "0.0676392000, 0.0653181000, 0.0576991000, 0.0325809000, -0.053789600, -0.359144000, -1.436084200"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017537770, 0.0061514700, 0.0215766200, 0.0756811700, 0.2654559000, 0.9311010000"); - values("0.0563025000, 0.0583454000, 0.0658691000, 0.0922570000, 0.1814077000, 0.4873764000, 1.5542316000", \ - "0.0562895000, 0.0584426000, 0.0657716000, 0.0920645000, 0.1813892000, 0.4873375000, 1.5534534000", \ - "0.0564259000, 0.0585054000, 0.0660527000, 0.0924284000, 0.1814667000, 0.4876514000, 1.5547367000", \ - "0.0561958000, 0.0582407000, 0.0657901000, 0.0921415000, 0.1813903000, 0.4872408000, 1.5544616000", \ - "0.0560173000, 0.0581660000, 0.0656465000, 0.0918088000, 0.1811317000, 0.4867848000, 1.5519087000", \ - "0.0560202000, 0.0581464000, 0.0656855000, 0.0919886000, 0.1808255000, 0.4866803000, 1.5543686000", \ - "0.0575480000, 0.0596329000, 0.0670517000, 0.0926509000, 0.1811864000, 0.4885081000, 1.5518852000"); - } - } - max_capacitance : 0.9311010000; - max_transition : 1.5062170000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.2661859000, 0.2699155000, 0.2807402000, 0.3076643000, 0.3648419000, 0.4879473000, 0.8157796000", \ - "0.2705366000, 0.2741920000, 0.2850326000, 0.3119505000, 0.3692922000, 0.4923759000, 0.8201120000", \ - "0.2806364000, 0.2843938000, 0.2952524000, 0.3222178000, 0.3790993000, 0.5021084000, 0.8305676000", \ - "0.3079630000, 0.3116083000, 0.3224489000, 0.3493457000, 0.4065618000, 0.5295319000, 0.8583768000", \ - "0.3753525000, 0.3789977000, 0.3898804000, 0.4166979000, 0.4739729000, 0.5970875000, 0.9258405000", \ - "0.5352327000, 0.5389462000, 0.5499249000, 0.5768716000, 0.6341437000, 0.7576003000, 1.0858371000", \ - "0.8244604000, 0.8291801000, 0.8429742000, 0.8770552000, 0.9457770000, 1.0782294000, 1.4111790000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.1161920000, 0.1195943000, 0.1298626000, 0.1568998000, 0.2269480000, 0.4397869000, 1.1732064000", \ - "0.1206813000, 0.1240631000, 0.1343168000, 0.1614125000, 0.2315015000, 0.4447272000, 1.1826268000", \ - "0.1311387000, 0.1345307000, 0.1447674000, 0.1718032000, 0.2419013000, 0.4551803000, 1.1919742000", \ - "0.1551402000, 0.1585277000, 0.1687758000, 0.1957328000, 0.2655980000, 0.4785335000, 1.2121532000", \ - "0.2040120000, 0.2075424000, 0.2181372000, 0.2456534000, 0.3159639000, 0.5292175000, 1.2629506000", \ - "0.2677202000, 0.2720469000, 0.2847238000, 0.3158293000, 0.3892963000, 0.6034375000, 1.3374215000", \ - "0.3288903000, 0.3342793000, 0.3502707000, 0.3895383000, 0.4721939000, 0.6883054000, 1.4224739000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0458587000, 0.0480045000, 0.0544814000, 0.0701214000, 0.1102367000, 0.2276364000, 0.6453954000", \ - "0.0458790000, 0.0480415000, 0.0545660000, 0.0699950000, 0.1104405000, 0.2278193000, 0.6451236000", \ - "0.0458937000, 0.0476641000, 0.0539565000, 0.0699013000, 0.1106630000, 0.2280542000, 0.6455441000", \ - "0.0458658000, 0.0480216000, 0.0545300000, 0.0699467000, 0.1101955000, 0.2278413000, 0.6455397000", \ - "0.0458878000, 0.0480194000, 0.0542145000, 0.0700450000, 0.1105611000, 0.2283459000, 0.6442006000", \ - "0.0484316000, 0.0503318000, 0.0566295000, 0.0720022000, 0.1108323000, 0.2286720000, 0.6452147000", \ - "0.0715063000, 0.0737708000, 0.0811810000, 0.0993855000, 0.1371403000, 0.2458135000, 0.6511141000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0304275000, 0.0329065000, 0.0404882000, 0.0645778000, 0.1447148000, 0.4407061000, 1.5008427000", \ - "0.0305052000, 0.0330078000, 0.0405464000, 0.0645625000, 0.1448305000, 0.4404128000, 1.5032666000", \ - "0.0304362000, 0.0328670000, 0.0405882000, 0.0646719000, 0.1449044000, 0.4404619000, 1.5054769000", \ - "0.0304178000, 0.0329147000, 0.0405401000, 0.0645838000, 0.1448766000, 0.4406863000, 1.5004854000", \ - "0.0338741000, 0.0361721000, 0.0433115000, 0.0666613000, 0.1459723000, 0.4405148000, 1.5006923000", \ - "0.0444339000, 0.0469986000, 0.0541196000, 0.0765056000, 0.1517951000, 0.4406835000, 1.5002241000", \ - "0.0621566000, 0.0647242000, 0.0738643000, 0.0972585000, 0.1666624000, 0.4450717000, 1.4941716000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.2628870000, 0.2665418000, 0.2773192000, 0.3039738000, 0.3610330000, 0.4839679000, 0.8119917000", \ - "0.2673770000, 0.2709411000, 0.2816145000, 0.3084472000, 0.3653919000, 0.4885021000, 0.8165317000", \ - "0.2775963000, 0.2812948000, 0.2920179000, 0.3187500000, 0.3754669000, 0.4985348000, 0.8269638000", \ - "0.3044427000, 0.3081381000, 0.3188314000, 0.3452744000, 0.4023080000, 0.5252774000, 0.8533036000", \ - "0.3713178000, 0.3749095000, 0.3856257000, 0.4122507000, 0.4692292000, 0.5921248000, 0.9206337000", \ - "0.5295870000, 0.5333302000, 0.5440422000, 0.5708597000, 0.6278737000, 0.7512398000, 1.0793185000", \ - "0.8124759000, 0.8170471000, 0.8307507000, 0.8646184000, 0.9329398000, 1.0652355000, 1.3985032000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.1167072000, 0.1201701000, 0.1303991000, 0.1573330000, 0.2268778000, 0.4392357000, 1.1779611000", \ - "0.1211339000, 0.1245999000, 0.1348049000, 0.1616998000, 0.2313425000, 0.4440303000, 1.1855272000", \ - "0.1314009000, 0.1348767000, 0.1450988000, 0.1720254000, 0.2415872000, 0.4537707000, 1.1919418000", \ - "0.1553240000, 0.1587957000, 0.1688886000, 0.1957158000, 0.2653157000, 0.4781234000, 1.2156574000", \ - "0.2040496000, 0.2076230000, 0.2182777000, 0.2456171000, 0.3156017000, 0.5286356000, 1.2663502000", \ - "0.2677001000, 0.2720640000, 0.2847865000, 0.3160283000, 0.3893239000, 0.6032032000, 1.3389828000", \ - "0.3287207000, 0.3341160000, 0.3503364000, 0.3898853000, 0.4727765000, 0.6882459000, 1.4228269000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0445396000, 0.0466263000, 0.0529913000, 0.0688600000, 0.1092130000, 0.2268121000, 0.6448448000", \ - "0.0448198000, 0.0469005000, 0.0529452000, 0.0690112000, 0.1100423000, 0.2273688000, 0.6448263000", \ - "0.0447748000, 0.0465278000, 0.0529821000, 0.0693942000, 0.1097389000, 0.2267779000, 0.6445910000", \ - "0.0445225000, 0.0465824000, 0.0529178000, 0.0693309000, 0.1100440000, 0.2275897000, 0.6446913000", \ - "0.0447782000, 0.0470062000, 0.0528325000, 0.0690572000, 0.1094124000, 0.2270689000, 0.6448163000", \ - "0.0477025000, 0.0496931000, 0.0560913000, 0.0709296000, 0.1108189000, 0.2279457000, 0.6446040000", \ - "0.0706640000, 0.0729251000, 0.0802232000, 0.0970675000, 0.1347691000, 0.2450713000, 0.6492801000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0307139000, 0.0332114000, 0.0408995000, 0.0648255000, 0.1452234000, 0.4399134000, 1.5023240000", \ - "0.0306755000, 0.0331328000, 0.0407578000, 0.0648587000, 0.1454172000, 0.4412761000, 1.5023356000", \ - "0.0307160000, 0.0331715000, 0.0408587000, 0.0647795000, 0.1452531000, 0.4400194000, 1.5020214000", \ - "0.0307793000, 0.0331070000, 0.0407572000, 0.0648449000, 0.1453297000, 0.4411593000, 1.5045750000", \ - "0.0343016000, 0.0366201000, 0.0437309000, 0.0669661000, 0.1458732000, 0.4411691000, 1.5053276000", \ - "0.0454407000, 0.0477911000, 0.0550675000, 0.0772214000, 0.1519277000, 0.4423270000, 1.5062169000", \ - "0.0626848000, 0.0657298000, 0.0751295000, 0.0985732000, 0.1672533000, 0.4461027000, 1.4954340000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.2855169000, 0.2892151000, 0.3001121000, 0.3270517000, 0.3841877000, 0.5073270000, 0.8358607000", \ - "0.2905766000, 0.2942251000, 0.3052336000, 0.3321965000, 0.3894881000, 0.5127183000, 0.8412079000", \ - "0.3037093000, 0.3074554000, 0.3183432000, 0.3453142000, 0.4024871000, 0.5258209000, 0.8539168000", \ - "0.3328380000, 0.3364883000, 0.3473364000, 0.3742207000, 0.4314766000, 0.5547852000, 0.8833361000", \ - "0.3967589000, 0.4004051000, 0.4112831000, 0.4381725000, 0.4954052000, 0.6184617000, 0.9472920000", \ - "0.5411485000, 0.5448421000, 0.5557819000, 0.5830054000, 0.6404767000, 0.7639148000, 1.0921823000", \ - "0.8128641000, 0.8171510000, 0.8295579000, 0.8611753000, 0.9260508000, 1.0587625000, 1.3917698000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.1281132000, 0.1312860000, 0.1408058000, 0.1661668000, 0.2334513000, 0.4451371000, 1.1803774000", \ - "0.1324899000, 0.1356765000, 0.1451968000, 0.1705349000, 0.2379016000, 0.4492293000, 1.1836551000", \ - "0.1419813000, 0.1450965000, 0.1545524000, 0.1799318000, 0.2473962000, 0.4594188000, 1.1939388000", \ - "0.1629911000, 0.1661185000, 0.1757050000, 0.2010113000, 0.2684638000, 0.4806327000, 1.2148078000", \ - "0.2071933000, 0.2104269000, 0.2202490000, 0.2459737000, 0.3138163000, 0.5261461000, 1.2610658000", \ - "0.2737717000, 0.2775155000, 0.2886926000, 0.3168539000, 0.3871651000, 0.5997802000, 1.3358700000", \ - "0.3451588000, 0.3499018000, 0.3640289000, 0.3980159000, 0.4743869000, 0.6883115000, 1.4225098000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0456796000, 0.0477141000, 0.0540420000, 0.0699443000, 0.1099423000, 0.2278427000, 0.6449706000", \ - "0.0458964000, 0.0480254000, 0.0541923000, 0.0699811000, 0.1107703000, 0.2280635000, 0.6451967000", \ - "0.0455823000, 0.0476779000, 0.0539272000, 0.0710217000, 0.1102293000, 0.2277543000, 0.6455290000", \ - "0.0458092000, 0.0480462000, 0.0541544000, 0.0700022000, 0.1107378000, 0.2280201000, 0.6452703000", \ - "0.0457864000, 0.0480110000, 0.0541589000, 0.0699774000, 0.1107541000, 0.2276249000, 0.6450527000", \ - "0.0481200000, 0.0501827000, 0.0563542000, 0.0717625000, 0.1103273000, 0.2284009000, 0.6452598000", \ - "0.0613970000, 0.0636673000, 0.0708183000, 0.0876707000, 0.1279268000, 0.2409295000, 0.6499888000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0276571000, 0.0300782000, 0.0379181000, 0.0620141000, 0.1432464000, 0.4403980000, 1.5007685000", \ - "0.0276558000, 0.0300872000, 0.0379323000, 0.0620588000, 0.1432890000, 0.4413663000, 1.5003782000", \ - "0.0277788000, 0.0301540000, 0.0378184000, 0.0619903000, 0.1433901000, 0.4417334000, 1.5023613000", \ - "0.0276947000, 0.0300923000, 0.0380405000, 0.0619410000, 0.1433566000, 0.4416613000, 1.5021830000", \ - "0.0293682000, 0.0317736000, 0.0394341000, 0.0631898000, 0.1436152000, 0.4418224000, 1.5023729000", \ - "0.0358511000, 0.0384387000, 0.0457809000, 0.0695885000, 0.1473292000, 0.4417743000, 1.4997064000", \ - "0.0491495000, 0.0523414000, 0.0608579000, 0.0839613000, 0.1569008000, 0.4433500000, 1.4991175000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.3155954000, 0.3192941000, 0.3300145000, 0.3566765000, 0.4134361000, 0.5360426000, 0.8642646000", \ - "0.3206011000, 0.3241970000, 0.3349515000, 0.3615269000, 0.4183291000, 0.5414222000, 0.8694626000", \ - "0.3318725000, 0.3354422000, 0.3462073000, 0.3729274000, 0.4298367000, 0.5522973000, 0.8806318000", \ - "0.3552268000, 0.3588966000, 0.3695858000, 0.3962460000, 0.4532957000, 0.5762052000, 0.9039403000", \ - "0.3871432000, 0.3908299000, 0.4015310000, 0.4282643000, 0.4850846000, 0.6082997000, 0.9365972000", \ - "0.4240514000, 0.4277250000, 0.4383685000, 0.4649442000, 0.5218439000, 0.6442904000, 0.9726040000", \ - "0.4515124000, 0.4551296000, 0.4658058000, 0.4924128000, 0.5493530000, 0.6724872000, 1.0005144000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.2120138000, 0.2152230000, 0.2248080000, 0.2505129000, 0.3187876000, 0.5319081000, 1.2665270000", \ - "0.2168186000, 0.2199792000, 0.2295494000, 0.2552192000, 0.3235228000, 0.5366325000, 1.2700592000", \ - "0.2294613000, 0.2326164000, 0.2422041000, 0.2679082000, 0.3361880000, 0.5493100000, 1.2838858000", \ - "0.2610393000, 0.2642205000, 0.2738004000, 0.2995396000, 0.3677423000, 0.5808682000, 1.3155548000", \ - "0.3300218000, 0.3332725000, 0.3428404000, 0.3684854000, 0.4367712000, 0.6497404000, 1.3837003000", \ - "0.4454059000, 0.4485900000, 0.4582296000, 0.4839926000, 0.5521088000, 0.7653025000, 1.5003797000", \ - "0.6302000000, 0.6334480000, 0.6432900000, 0.6693117000, 0.7378014000, 0.9510029000, 1.6846105000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0445257000, 0.0466006000, 0.0528379000, 0.0691546000, 0.1099031000, 0.2272730000, 0.6445325000", \ - "0.0448187000, 0.0468488000, 0.0528915000, 0.0697314000, 0.1100320000, 0.2273607000, 0.6447364000", \ - "0.0446161000, 0.0466725000, 0.0530452000, 0.0689099000, 0.1097092000, 0.2273880000, 0.6448308000", \ - "0.0448111000, 0.0469531000, 0.0529975000, 0.0688520000, 0.1092086000, 0.2267574000, 0.6448743000", \ - "0.0445458000, 0.0466225000, 0.0529267000, 0.0691449000, 0.1100708000, 0.2274293000, 0.6448213000", \ - "0.0445095000, 0.0465464000, 0.0526251000, 0.0684312000, 0.1086121000, 0.2269175000, 0.6449915000", \ - "0.0448714000, 0.0467509000, 0.0530673000, 0.0688832000, 0.1097532000, 0.2271500000, 0.6440176000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017537800, 0.0061514700, 0.0215766000, 0.0756812000, 0.2654560000, 0.9311010000"); - values("0.0278701000, 0.0305316000, 0.0381512000, 0.0622961000, 0.1432674000, 0.4412965000, 1.5007953000", \ - "0.0279952000, 0.0304675000, 0.0383064000, 0.0622693000, 0.1435524000, 0.4408009000, 1.4999070000", \ - "0.0280780000, 0.0305492000, 0.0381513000, 0.0622948000, 0.1436259000, 0.4412026000, 1.5007955000", \ - "0.0280783000, 0.0305226000, 0.0381663000, 0.0622776000, 0.1431466000, 0.4414114000, 1.5007730000", \ - "0.0279998000, 0.0304300000, 0.0383219000, 0.0623124000, 0.1431659000, 0.4398532000, 1.4971833000", \ - "0.0281776000, 0.0306672000, 0.0385306000, 0.0626093000, 0.1433145000, 0.4412382000, 1.5006498000", \ - "0.0291530000, 0.0315781000, 0.0392349000, 0.0632723000, 0.1437915000, 0.4409340000, 1.4964767000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2i_1") { - leakage_power () { - value : 0.0094009000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0005004000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0115162000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0006906000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0095910000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0028692000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0101436000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0024123000; - when : "A0&A1&!S"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__mux2i"; - cell_leakage_power : 0.0058905370; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0022070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046343000, 0.0046342000, 0.0046338000, 0.0046341000, 0.0046345000, 0.0046358000, 0.0046388000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002410900, -0.002444000, -0.002520200, -0.002520400, -0.002520900, -0.002521800, -0.002523800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023150000; - } - pin ("A1") { - capacitance : 0.0022600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049199000, 0.0049179000, 0.0049134000, 0.0049150000, 0.0049187000, 0.0049274000, 0.0049472000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003078300, -0.003102200, -0.003157300, -0.003150600, -0.003135200, -0.003099600, -0.003017700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023640000; - } - pin ("S") { - capacitance : 0.0046530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156620000, 0.0155050000, 0.0151430000, 0.0153198000, 0.0157272000, 0.0166666000, 0.0188320000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000761500, -0.000926400, -0.001306200, -0.001158800, -0.000818800, -3.5263879e-05, 0.0017709000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048290000; - } - pin ("Y") { - direction : "output"; - function : "(!A0&!S) | (!A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0030566000, 0.0020734000, -0.000187800, -0.005401300, -0.017372500, -0.044694800, -0.106914600", \ - "0.0030340000, 0.0020686000, -0.000179500, -0.005355700, -0.017300100, -0.044595200, -0.106802600", \ - "0.0029768000, 0.0020121000, -0.000212400, -0.005355200, -0.017244800, -0.044497600, -0.106667000", \ - "0.0027114000, 0.0017614000, -0.000401100, -0.005528600, -0.017364000, -0.044581900, -0.106659700", \ - "0.0026191000, 0.0016449000, -0.000614200, -0.005802300, -0.017588900, -0.044710200, -0.106746100", \ - "0.0031712000, 0.0021506000, -0.000211100, -0.005434100, -0.017739800, -0.044785200, -0.106805200", \ - "0.0045103000, 0.0033792000, 0.0008659000, -0.004683600, -0.016985900, -0.044583300, -0.106830300"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0079152000, 0.0090002000, 0.0114003000, 0.0167721000, 0.0287781000, 0.0559022000, 0.1173743000", \ - "0.0077048000, 0.0087962000, 0.0111862000, 0.0166203000, 0.0287422000, 0.0558726000, 0.1173770000", \ - "0.0074329000, 0.0084597000, 0.0108806000, 0.0163639000, 0.0285144000, 0.0557918000, 0.1173425000", \ - "0.0072170000, 0.0082836000, 0.0107050000, 0.0159865000, 0.0282241000, 0.0555974000, 0.1172501000", \ - "0.0072915000, 0.0082958000, 0.0106296000, 0.0159588000, 0.0279971000, 0.0552351000, 0.1170150000", \ - "0.0078603000, 0.0089020000, 0.0112908000, 0.0164502000, 0.0282762000, 0.0550762000, 0.1167353000", \ - "0.0089300000, 0.0098734000, 0.0120212000, 0.0173638000, 0.0290816000, 0.0557542000, 0.1171646000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0045431000, 0.0035518000, 0.0013017000, -0.003932500, -0.015866800, -0.043159800, -0.105333600", \ - "0.0045133000, 0.0035411000, 0.0013004000, -0.003886300, -0.015818100, -0.043079100, -0.105237700", \ - "0.0044230000, 0.0034750000, 0.0012161000, -0.003913600, -0.015790500, -0.043012400, -0.105138700", \ - "0.0041836000, 0.0032413000, 0.0010136000, -0.004092900, -0.015936400, -0.043109500, -0.105182700", \ - "0.0041295000, 0.0031507000, 0.0008728000, -0.004297000, -0.016156300, -0.043272500, -0.105250500", \ - "0.0044099000, 0.0032933000, 0.0010874000, -0.004179200, -0.016407400, -0.043406000, -0.105384000", \ - "0.0053454000, 0.0042389000, 0.0017873000, -0.003601200, -0.015912700, -0.043253300, -0.105545800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0078132000, 0.0089177000, 0.0113154000, 0.0166768000, 0.0287129000, 0.0558740000, 0.1173641000", \ - "0.0076023000, 0.0086504000, 0.0110949000, 0.0165345000, 0.0286690000, 0.0558191000, 0.1172977000", \ - "0.0073142000, 0.0083658000, 0.0108251000, 0.0163044000, 0.0284802000, 0.0557428000, 0.1171647000", \ - "0.0070629000, 0.0081149000, 0.0104737000, 0.0159610000, 0.0281707000, 0.0555610000, 0.1171599000", \ - "0.0071108000, 0.0081401000, 0.0104880000, 0.0158946000, 0.0278679000, 0.0552039000, 0.1168445000", \ - "0.0075469000, 0.0085501000, 0.0109351000, 0.0161311000, 0.0282180000, 0.0549268000, 0.1165302000", \ - "0.0083269000, 0.0092797000, 0.0114610000, 0.0168540000, 0.0286324000, 0.0554095000, 0.1166066000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0046769000, 0.0036669000, 0.0013538000, -0.003919200, -0.015938400, -0.043289000, -0.105513300", \ - "0.0045561000, 0.0035534000, 0.0012431000, -0.004028100, -0.016053500, -0.043406200, -0.105628300", \ - "0.0046300000, 0.0036255000, 0.0013210000, -0.003941800, -0.015948500, -0.043308900, -0.105495400", \ - "0.0043654000, 0.0033520000, 0.0009727000, -0.004266000, -0.016252900, -0.043583600, -0.105802200", \ - "0.0039014000, 0.0029717000, 0.0007214000, -0.004517300, -0.016481300, -0.043806200, -0.105996400", \ - "0.0032331000, 0.0022109000, -0.000102700, -0.005357100, -0.016715000, -0.044006100, -0.106185300", \ - "0.0035400000, 0.0025030000, 0.0002356000, -0.005011100, -0.017017600, -0.044369800, -0.105933600"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011357280, 0.0025797560, 0.0058598010, 0.0133102800, 0.0302337100, 0.0686745300"); - values("0.0107015000, 0.0117377000, 0.0140588000, 0.0193412000, 0.0312758000, 0.0583829000, 0.1198287000", \ - "0.0105364000, 0.0115835000, 0.0139058000, 0.0191965000, 0.0311520000, 0.0582032000, 0.1197373000", \ - "0.0105083000, 0.0115628000, 0.0138999000, 0.0192152000, 0.0311947000, 0.0583092000, 0.1197391000", \ - "0.0100228000, 0.0110704000, 0.0134438000, 0.0187591000, 0.0307661000, 0.0578097000, 0.1193133000", \ - "0.0096288000, 0.0106758000, 0.0130257000, 0.0183693000, 0.0303862000, 0.0575114000, 0.1189970000", \ - "0.0099033000, 0.0109292000, 0.0131618000, 0.0183363000, 0.0303819000, 0.0574951000, 0.1189521000", \ - "0.0106152000, 0.0116761000, 0.0140000000, 0.0193408000, 0.0311705000, 0.0582561000, 0.1195935000"); - } - } - max_capacitance : 0.0686750000; - max_transition : 1.4582830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0312540000, 0.0354293000, 0.0444537000, 0.0637578000, 0.1064207000, 0.2018555000, 0.4170745000", \ - "0.0355975000, 0.0397757000, 0.0488267000, 0.0683006000, 0.1110573000, 0.2066012000, 0.4220892000", \ - "0.0463639000, 0.0503919000, 0.0593405000, 0.0786007000, 0.1216003000, 0.2171404000, 0.4324571000", \ - "0.0650947000, 0.0707916000, 0.0823136000, 0.1034972000, 0.1459588000, 0.2413060000, 0.4568051000", \ - "0.0869112000, 0.0953640000, 0.1128412000, 0.1452529000, 0.2011350000, 0.2975037000, 0.5129380000", \ - "0.1056656000, 0.1188237000, 0.1443642000, 0.1930325000, 0.2803930000, 0.4186194000, 0.6461872000", \ - "0.1009637000, 0.1213978000, 0.1618904000, 0.2379360000, 0.3694990000, 0.5835253000, 0.9161787000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0731053000, 0.0829277000, 0.1043660000, 0.1518206000, 0.2574669000, 0.4955761000, 1.0343150000", \ - "0.0761859000, 0.0860303000, 0.1076386000, 0.1556051000, 0.2618165000, 0.5001287000, 1.0391482000", \ - "0.0861692000, 0.0957122000, 0.1170745000, 0.1653637000, 0.2725452000, 0.5112351000, 1.0506452000", \ - "0.1134405000, 0.1228393000, 0.1439098000, 0.1907961000, 0.2976629000, 0.5374158000, 1.0772255000", \ - "0.1701774000, 0.1825822000, 0.2087128000, 0.2565319000, 0.3608539000, 0.5997199000, 1.1405675000", \ - "0.2615474000, 0.2805582000, 0.3187662000, 0.3908574000, 0.5154678000, 0.7534552000, 1.2923610000", \ - "0.4050068000, 0.4313315000, 0.4899832000, 0.5981564000, 0.7900506000, 1.1025330000, 1.6427371000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0255447000, 0.0303681000, 0.0414016000, 0.0660436000, 0.1221804000, 0.2497466000, 0.5397114000", \ - "0.0253355000, 0.0302848000, 0.0412657000, 0.0660544000, 0.1222077000, 0.2502200000, 0.5393960000", \ - "0.0264604000, 0.0308511000, 0.0412470000, 0.0658285000, 0.1224161000, 0.2496285000, 0.5398054000", \ - "0.0375062000, 0.0423164000, 0.0523197000, 0.0718858000, 0.1231587000, 0.2503661000, 0.5395660000", \ - "0.0593180000, 0.0659802000, 0.0791964000, 0.1033346000, 0.1477328000, 0.2572731000, 0.5390483000", \ - "0.0982199000, 0.1086938000, 0.1292443000, 0.1652795000, 0.2244748000, 0.3276118000, 0.5652356000", \ - "0.1666714000, 0.1830210000, 0.2145359000, 0.2696086000, 0.3571941000, 0.5014091000, 0.7366260000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0674947000, 0.0800995000, 0.1080731000, 0.1718746000, 0.3153849000, 0.6401916000, 1.3787577000", \ - "0.0675241000, 0.0799277000, 0.1079560000, 0.1716351000, 0.3154488000, 0.6411834000, 1.3790487000", \ - "0.0672686000, 0.0798308000, 0.1079834000, 0.1715094000, 0.3156187000, 0.6413035000, 1.3798930000", \ - "0.0701203000, 0.0815757000, 0.1081277000, 0.1714738000, 0.3153366000, 0.6403337000, 1.3799860000", \ - "0.0973915000, 0.1091484000, 0.1314961000, 0.1838596000, 0.3164317000, 0.6409508000, 1.3840136000", \ - "0.1474797000, 0.1629826000, 0.1954848000, 0.2544749000, 0.3669851000, 0.6502201000, 1.3787987000", \ - "0.2276335000, 0.2527979000, 0.3004909000, 0.3859232000, 0.5317088000, 0.7793907000, 1.4118082000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0336551000, 0.0380669000, 0.0475758000, 0.0678440000, 0.1118654000, 0.2095805000, 0.4291769000", \ - "0.0380094000, 0.0424542000, 0.0520439000, 0.0723690000, 0.1165346000, 0.2142736000, 0.4341145000", \ - "0.0485458000, 0.0530227000, 0.0621444000, 0.0826708000, 0.1269420000, 0.2247911000, 0.4451386000", \ - "0.0692551000, 0.0748503000, 0.0863754000, 0.1074437000, 0.1512621000, 0.2492519000, 0.4693489000", \ - "0.0937112000, 0.1022183000, 0.1191020000, 0.1504562000, 0.2071196000, 0.3059759000, 0.5261085000", \ - "0.1166041000, 0.1292664000, 0.1550192000, 0.2024585000, 0.2890005000, 0.4255292000, 0.6548702000", \ - "0.1149764000, 0.1341611000, 0.1734245000, 0.2485959000, 0.3815681000, 0.5938569000, 0.9296408000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0779257000, 0.0883975000, 0.1107528000, 0.1607213000, 0.2714526000, 0.5211638000, 1.0867609000", \ - "0.0814745000, 0.0914129000, 0.1141173000, 0.1644065000, 0.2759012000, 0.5259977000, 1.0915334000", \ - "0.0912640000, 0.1013195000, 0.1239584000, 0.1745134000, 0.2866190000, 0.5372855000, 1.1037072000", \ - "0.1188048000, 0.1284454000, 0.1504840000, 0.2004643000, 0.3128238000, 0.5643190000, 1.1313213000", \ - "0.1789581000, 0.1922749000, 0.2176803000, 0.2673947000, 0.3765364000, 0.6274415000, 1.1948316000", \ - "0.2785877000, 0.2965389000, 0.3368097000, 0.4093859000, 0.5364857000, 0.7850622000, 1.3506122000", \ - "0.4370510000, 0.4648165000, 0.5250016000, 0.6357704000, 0.8301823000, 1.1466031000, 1.7090069000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0292036000, 0.0342834000, 0.0454640000, 0.0708531000, 0.1282279000, 0.2583821000, 0.5532623000", \ - "0.0289717000, 0.0340741000, 0.0453587000, 0.0707155000, 0.1282362000, 0.2579966000, 0.5538932000", \ - "0.0293931000, 0.0341019000, 0.0449583000, 0.0705631000, 0.1281787000, 0.2582030000, 0.5538934000", \ - "0.0400502000, 0.0447337000, 0.0544996000, 0.0755127000, 0.1286878000, 0.2586814000, 0.5531673000", \ - "0.0624901000, 0.0689697000, 0.0833244000, 0.1076672000, 0.1512661000, 0.2643656000, 0.5535735000", \ - "0.1027142000, 0.1122992000, 0.1330799000, 0.1691527000, 0.2285323000, 0.3340555000, 0.5781068000", \ - "0.1733690000, 0.1896464000, 0.2202461000, 0.2754848000, 0.3643507000, 0.5125706000, 0.7475827000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0689382000, 0.0818604000, 0.1111127000, 0.1777123000, 0.3265715000, 0.6665583000, 1.4369067000", \ - "0.0689756000, 0.0819525000, 0.1110665000, 0.1771365000, 0.3266258000, 0.6667267000, 1.4373757000", \ - "0.0688950000, 0.0818625000, 0.1111129000, 0.1772471000, 0.3266845000, 0.6655303000, 1.4389544000", \ - "0.0712042000, 0.0830635000, 0.1111239000, 0.1772352000, 0.3269684000, 0.6657906000, 1.4330148000", \ - "0.0979502000, 0.1101037000, 0.1325338000, 0.1871880000, 0.3272432000, 0.6659582000, 1.4397797000", \ - "0.1497473000, 0.1646098000, 0.1964091000, 0.2555878000, 0.3721904000, 0.6720054000, 1.4341970000", \ - "0.2335543000, 0.2585937000, 0.3068640000, 0.3919439000, 0.5370990000, 0.7889808000, 1.4582833000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0383825000, 0.0425846000, 0.0517593000, 0.0717388000, 0.1155579000, 0.2131659000, 0.4330963000", \ - "0.0427494000, 0.0469549000, 0.0561528000, 0.0761708000, 0.1200338000, 0.2175634000, 0.4376610000", \ - "0.0521696000, 0.0562946000, 0.0653957000, 0.0853921000, 0.1292904000, 0.2269270000, 0.4469289000", \ - "0.0695386000, 0.0743920000, 0.0846294000, 0.1056669000, 0.1497095000, 0.2475772000, 0.4675191000", \ - "0.0944896000, 0.1014322000, 0.1154865000, 0.1430771000, 0.1947122000, 0.2950151000, 0.5154119000", \ - "0.1204218000, 0.1312426000, 0.1528353000, 0.1948161000, 0.2690242000, 0.3945262000, 0.6258122000", \ - "0.1282089000, 0.1444416000, 0.1791884000, 0.2450584000, 0.3616316000, 0.5491296000, 0.8482095000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0884979000, 0.0977783000, 0.1186399000, 0.1655102000, 0.2707417000, 0.5084919000, 1.0471248000", \ - "0.0934496000, 0.1028177000, 0.1237943000, 0.1708023000, 0.2761840000, 0.5140232000, 1.0525911000", \ - "0.1060936000, 0.1155314000, 0.1367060000, 0.1837971000, 0.2895705000, 0.5275818000, 1.0661310000", \ - "0.1339171000, 0.1432449000, 0.1642175000, 0.2113665000, 0.3171919000, 0.5557014000, 1.0945156000", \ - "0.1863656000, 0.1974484000, 0.2211239000, 0.2697184000, 0.3754715000, 0.6140680000, 1.1535634000", \ - "0.2726170000, 0.2881273000, 0.3202802000, 0.3845097000, 0.5060261000, 0.7473787000, 1.2871694000", \ - "0.4047286000, 0.4291904000, 0.4794515000, 0.5755850000, 0.7454017000, 1.0419750000, 1.5966902000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0275079000, 0.0326507000, 0.0441275000, 0.0698843000, 0.1277826000, 0.2588332000, 0.5529650000", \ - "0.0274232000, 0.0325637000, 0.0440219000, 0.0699185000, 0.1280111000, 0.2579389000, 0.5539684000", \ - "0.0278035000, 0.0327475000, 0.0439965000, 0.0696270000, 0.1277555000, 0.2587356000, 0.5531559000", \ - "0.0345982000, 0.0391678000, 0.0494069000, 0.0727914000, 0.1284809000, 0.2582831000, 0.5549131000", \ - "0.0525191000, 0.0577969000, 0.0692773000, 0.0930000000, 0.1427417000, 0.2629826000, 0.5536723000", \ - "0.0877393000, 0.0948459000, 0.1104699000, 0.1409851000, 0.1968746000, 0.3055252000, 0.5681651000", \ - "0.1524315000, 0.1635069000, 0.1857629000, 0.2301887000, 0.3058519000, 0.4327525000, 0.6801119000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0660661000, 0.0787031000, 0.1071836000, 0.1712967000, 0.3149165000, 0.6413010000, 1.3797804000", \ - "0.0660188000, 0.0786007000, 0.1072689000, 0.1711813000, 0.3154167000, 0.6407005000, 1.3797761000", \ - "0.0661024000, 0.0787105000, 0.1071327000, 0.1712181000, 0.3153500000, 0.6408332000, 1.3795040000", \ - "0.0670568000, 0.0792236000, 0.1073273000, 0.1712241000, 0.3153025000, 0.6408316000, 1.3790825000", \ - "0.0824796000, 0.0942047000, 0.1192739000, 0.1781393000, 0.3158889000, 0.6415265000, 1.3803300000", \ - "0.1210711000, 0.1349399000, 0.1640680000, 0.2231486000, 0.3458512000, 0.6483817000, 1.3799070000", \ - "0.2027606000, 0.2216720000, 0.2589169000, 0.3308417000, 0.4631684000, 0.7340553000, 1.4117084000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0834943000, 0.0876220000, 0.0966794000, 0.1160962000, 0.1586738000, 0.2539950000, 0.4695465000", \ - "0.0883532000, 0.0925138000, 0.1015370000, 0.1209690000, 0.1635996000, 0.2588298000, 0.4741669000", \ - "0.1009018000, 0.1051449000, 0.1142280000, 0.1336503000, 0.1762257000, 0.2715773000, 0.4871387000", \ - "0.1297717000, 0.1340504000, 0.1432710000, 0.1627906000, 0.2054690000, 0.3008198000, 0.5162644000", \ - "0.1773706000, 0.1819074000, 0.1914178000, 0.2114136000, 0.2545578000, 0.3500691000, 0.5654806000", \ - "0.2485340000, 0.2531324000, 0.2633990000, 0.2840882000, 0.3279338000, 0.4238775000, 0.6395972000", \ - "0.3562225000, 0.3621625000, 0.3733556000, 0.3965377000, 0.4421787000, 0.5387886000, 0.7549721000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.1195052000, 0.1295136000, 0.1512747000, 0.2003877000, 0.3104474000, 0.5594668000, 1.1241926000", \ - "0.1239039000, 0.1340509000, 0.1557307000, 0.2049866000, 0.3150407000, 0.5642093000, 1.1287042000", \ - "0.1345484000, 0.1447424000, 0.1665540000, 0.2159888000, 0.3262571000, 0.5754991000, 1.1401279000", \ - "0.1546640000, 0.1645059000, 0.1865765000, 0.2360274000, 0.3468130000, 0.5963103000, 1.1612616000", \ - "0.1816197000, 0.1913809000, 0.2134734000, 0.2634030000, 0.3740781000, 0.6237745000, 1.1888911000", \ - "0.2142130000, 0.2242629000, 0.2462489000, 0.2960422000, 0.4069854000, 0.6569082000, 1.2235239000", \ - "0.2457745000, 0.2558591000, 0.2783200000, 0.3280551000, 0.4390841000, 0.6891949000, 1.2549400000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0268310000, 0.0316451000, 0.0423194000, 0.0666179000, 0.1223388000, 0.2496350000, 0.5389155000", \ - "0.0268487000, 0.0316393000, 0.0423348000, 0.0666580000, 0.1225729000, 0.2493516000, 0.5392007000", \ - "0.0268513000, 0.0316171000, 0.0423174000, 0.0667279000, 0.1223525000, 0.2498978000, 0.5396701000", \ - "0.0269915000, 0.0317640000, 0.0424662000, 0.0667264000, 0.1223796000, 0.2493508000, 0.5393126000", \ - "0.0285242000, 0.0333041000, 0.0438337000, 0.0678503000, 0.1229183000, 0.2499950000, 0.5389727000", \ - "0.0322737000, 0.0367731000, 0.0470895000, 0.0701798000, 0.1244620000, 0.2502718000, 0.5393056000", \ - "0.0406206000, 0.0449184000, 0.0547101000, 0.0768431000, 0.1281344000, 0.2519773000, 0.5399743000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011357300, 0.0025797600, 0.0058598000, 0.0133103000, 0.0302337000, 0.0686745000"); - values("0.0691199000, 0.0819031000, 0.1109873000, 0.1772930000, 0.3271440000, 0.6663284000, 1.4346515000", \ - "0.0691228000, 0.0819999000, 0.1110136000, 0.1772488000, 0.3268149000, 0.6659377000, 1.4338728000", \ - "0.0691125000, 0.0819993000, 0.1110203000, 0.1770491000, 0.3268155000, 0.6672493000, 1.4342338000", \ - "0.0691104000, 0.0820039000, 0.1112018000, 0.1771886000, 0.3269048000, 0.6664900000, 1.4339224000", \ - "0.0695168000, 0.0823657000, 0.1118943000, 0.1774444000, 0.3271536000, 0.6680174000, 1.4362560000", \ - "0.0700946000, 0.0828999000, 0.1118294000, 0.1776612000, 0.3272389000, 0.6665173000, 1.4359341000", \ - "0.0737176000, 0.0859576000, 0.1139654000, 0.1786800000, 0.3276585000, 0.6664785000, 1.4338826000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2i_2") { - leakage_power () { - value : 0.0033675000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0011944000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0058200000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0018432000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0039098000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0088905000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0047783000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0040437000; - when : "A0&A1&!S"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__mux2i"; - cell_leakage_power : 0.0042309330; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0043320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089642000, 0.0089596000, 0.0089492000, 0.0089490000, 0.0089484000, 0.0089472000, 0.0089443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006273200, -0.006353800, -0.006539600, -0.006544000, -0.006554100, -0.006577500, -0.006631300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045670000; - } - pin ("A1") { - capacitance : 0.0041860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093874000, 0.0093828000, 0.0093722000, 0.0093713000, 0.0093695000, 0.0093651000, 0.0093551000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006311200, -0.006353800, -0.006452000, -0.006441900, -0.006418700, -0.006365000, -0.006241400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044350000; - } - pin ("S") { - capacitance : 0.0064110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0061070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0218201000, 0.0216464000, 0.0212459000, 0.0213467000, 0.0215790000, 0.0221146000, 0.0233490000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000222600, -0.000348700, -0.000639300, -0.000558100, -0.000371100, 5.9954033e-05, 0.0010536000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0067160000; - } - pin ("Y") { - direction : "output"; - function : "(!A0&!S) | (!A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0106771000, 0.0095500000, 0.0067924000, -0.000106400, -0.017176000, -0.059291200, -0.162678900", \ - "0.0106885000, 0.0095747000, 0.0068187000, -1.59000e-05, -0.017011400, -0.059067300, -0.162417800", \ - "0.0106097000, 0.0095011000, 0.0067782000, 1.330000e-05, -0.016913000, -0.058875200, -0.162190300", \ - "0.0101994000, 0.0091054000, 0.0063989000, -0.000337200, -0.017161400, -0.059005700, -0.162270000", \ - "0.0100403000, 0.0089212000, 0.0061619000, -0.000678100, -0.017492900, -0.059205200, -0.162310900", \ - "0.0106931000, 0.0095182000, 0.0066943000, -0.000228700, -0.017479200, -0.059311500, -0.162432600", \ - "0.0130997000, 0.0118720000, 0.0088201000, 0.0014552000, -0.016028200, -0.058750700, -0.162105600"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0170511000, 0.0182786000, 0.0212365000, 0.0283983000, 0.0455790000, 0.0874538000, 0.1896840000", \ - "0.0165789000, 0.0178143000, 0.0208093000, 0.0280334000, 0.0454167000, 0.0873751000, 0.1896102000", \ - "0.0158834000, 0.0171385000, 0.0201558000, 0.0274124000, 0.0449682000, 0.0871728000, 0.1895302000", \ - "0.0154262000, 0.0166569000, 0.0195004000, 0.0267670000, 0.0443109000, 0.0866992000, 0.1892629000", \ - "0.0152710000, 0.0164573000, 0.0193812000, 0.0265044000, 0.0437440000, 0.0860435000, 0.1887854000", \ - "0.0167966000, 0.0180067000, 0.0209861000, 0.0272307000, 0.0447521000, 0.0857268000, 0.1883594000", \ - "0.0203688000, 0.0216089000, 0.0241199000, 0.0297301000, 0.0462168000, 0.0878029000, 0.1885534000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0111121000, 0.0099816000, 0.0072103000, 0.0002958000, -0.016794400, -0.058927600, -0.162363300", \ - "0.0110768000, 0.0099591000, 0.0071998000, 0.0003377000, -0.016698700, -0.058766700, -0.162177000", \ - "0.0109335000, 0.0098220000, 0.0070892000, 0.0002860000, -0.016661200, -0.058649300, -0.162046600", \ - "0.0104700000, 0.0093898000, 0.0066777000, -0.000100000, -0.016951100, -0.058827900, -0.162063800", \ - "0.0102547000, 0.0091127000, 0.0062907000, -0.000532300, -0.017294600, -0.059081000, -0.162217800", \ - "0.0106885000, 0.0093730000, 0.0066707000, -0.000283400, -0.017632700, -0.059496100, -0.162538300", \ - "0.0126778000, 0.0114781000, 0.0084207000, 0.0011279000, -0.016297600, -0.058177500, -0.162402300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0159827000, 0.0172133000, 0.0201943000, 0.0273480000, 0.0445740000, 0.0864590000, 0.1887104000", \ - "0.0154181000, 0.0166701000, 0.0196918000, 0.0269932000, 0.0443871000, 0.0863991000, 0.1886911000", \ - "0.0147387000, 0.0159879000, 0.0190267000, 0.0263464000, 0.0439796000, 0.0862528000, 0.1885991000", \ - "0.0144042000, 0.0155455000, 0.0184091000, 0.0255714000, 0.0431662000, 0.0857351000, 0.1882475000", \ - "0.0141507000, 0.0153499000, 0.0182625000, 0.0253630000, 0.0425930000, 0.0849085000, 0.1878233000", \ - "0.0151359000, 0.0162714000, 0.0190790000, 0.0259587000, 0.0430118000, 0.0842784000, 0.1872286000", \ - "0.0184760000, 0.0196033000, 0.0223409000, 0.0284429000, 0.0449614000, 0.0863752000, 0.1874462000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0116832000, 0.0105570000, 0.0077496000, 0.0008096000, -0.016327300, -0.058489000, -0.161905200", \ - "0.0115903000, 0.0104546000, 0.0076460000, 0.0007114000, -0.016413800, -0.058590300, -0.162014500", \ - "0.0116742000, 0.0105533000, 0.0077413000, 0.0008037000, -0.016325100, -0.058464700, -0.161897100", \ - "0.0113413000, 0.0102093000, 0.0074197000, 0.0005090000, -0.016586000, -0.058738200, -0.162151000", \ - "0.0107650000, 0.0096468000, 0.0068715000, -6.80000e-06, -0.017047900, -0.059134800, -0.162523900", \ - "0.0100059000, 0.0088751000, 0.0060276000, -0.000681900, -0.017014500, -0.059060100, -0.162474500", \ - "0.0107998000, 0.0096366000, 0.0068720000, -0.000167100, -0.017283900, -0.059450400, -0.161877100"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012248250, 0.0030003910, 0.0073499050, 0.0180046900, 0.0441051700, 0.1080422000"); - values("0.0214879000, 0.0226572000, 0.0255582000, 0.0325690000, 0.0496855000, 0.0913561000, 0.1935654000", \ - "0.0213337000, 0.0225109000, 0.0253819000, 0.0324191000, 0.0495404000, 0.0912673000, 0.1934683000", \ - "0.0211525000, 0.0223541000, 0.0252539000, 0.0323083000, 0.0494737000, 0.0912272000, 0.1935342000", \ - "0.0205752000, 0.0217557000, 0.0246701000, 0.0317378000, 0.0488810000, 0.0907087000, 0.1929191000", \ - "0.0202287000, 0.0214328000, 0.0243281000, 0.0314271000, 0.0486524000, 0.0904451000, 0.1926772000", \ - "0.0202634000, 0.0212863000, 0.0239946000, 0.0311030000, 0.0482658000, 0.0901636000, 0.1924772000", \ - "0.0211970000, 0.0224023000, 0.0252718000, 0.0323212000, 0.0492138000, 0.0911415000, 0.1931759000"); - } - } - max_capacitance : 0.1080420000; - max_transition : 1.4709000000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0367435000, 0.0392785000, 0.0452477000, 0.0592712000, 0.0924237000, 0.1718476000, 0.3645260000", \ - "0.0411876000, 0.0436701000, 0.0497028000, 0.0638543000, 0.0970493000, 0.1765869000, 0.3693746000", \ - "0.0514547000, 0.0539500000, 0.0598966000, 0.0740524000, 0.1075190000, 0.1871860000, 0.3803537000", \ - "0.0718869000, 0.0752130000, 0.0827309000, 0.0984566000, 0.1317775000, 0.2114657000, 0.4046001000", \ - "0.0950952000, 0.0998810000, 0.1109579000, 0.1347925000, 0.1824868000, 0.2675107000, 0.4597345000", \ - "0.1137605000, 0.1211691000, 0.1386788000, 0.1748576000, 0.2467898000, 0.3737014000, 0.5887089000", \ - "0.1050287000, 0.1163619000, 0.1429167000, 0.2002128000, 0.3094634000, 0.5066603000, 0.8324781000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.1006992000, 0.1077898000, 0.1246389000, 0.1654709000, 0.2631524000, 0.5000471000, 1.0787345000", \ - "0.1028027000, 0.1098264000, 0.1272811000, 0.1684193000, 0.2667901000, 0.5050532000, 1.0847682000", \ - "0.1108691000, 0.1182523000, 0.1354687000, 0.1770510000, 0.2763047000, 0.5149121000, 1.0945695000", \ - "0.1369350000, 0.1440863000, 0.1599949000, 0.2015743000, 0.3006383000, 0.5401598000, 1.1208118000", \ - "0.1995899000, 0.2076977000, 0.2260576000, 0.2665141000, 0.3637577000, 0.6024854000, 1.1840808000", \ - "0.3031947000, 0.3151803000, 0.3417532000, 0.4013758000, 0.5164140000, 0.7528129000, 1.3323446000", \ - "0.4681813000, 0.4864218000, 0.5286999000, 0.6149148000, 0.7886995000, 1.1011390000, 1.6845830000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0318561000, 0.0348281000, 0.0422119000, 0.0600365000, 0.1043707000, 0.2125931000, 0.4783918000", \ - "0.0317458000, 0.0347761000, 0.0421560000, 0.0601449000, 0.1042170000, 0.2127209000, 0.4784212000", \ - "0.0322970000, 0.0351277000, 0.0420747000, 0.0598361000, 0.1042074000, 0.2130884000, 0.4785096000", \ - "0.0436273000, 0.0465714000, 0.0528931000, 0.0669031000, 0.1061661000, 0.2128898000, 0.4790166000", \ - "0.0666167000, 0.0706081000, 0.0798483000, 0.0982086000, 0.1365391000, 0.2237642000, 0.4783212000", \ - "0.1088730000, 0.1149982000, 0.1282829000, 0.1566940000, 0.2094465000, 0.3031288000, 0.5141992000", \ - "0.1837531000, 0.1957190000, 0.2153848000, 0.2531741000, 0.3330482000, 0.4649187000, 0.6995762000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0955617000, 0.1046406000, 0.1268375000, 0.1820405000, 0.3162769000, 0.6418094000, 1.4405883000", \ - "0.0952649000, 0.1044548000, 0.1267267000, 0.1816930000, 0.3149774000, 0.6446649000, 1.4415251000", \ - "0.0953726000, 0.1046295000, 0.1267479000, 0.1815770000, 0.3162394000, 0.6424636000, 1.4407688000", \ - "0.0959295000, 0.1046967000, 0.1265081000, 0.1816522000, 0.3150012000, 0.6438465000, 1.4407797000", \ - "0.1216920000, 0.1287820000, 0.1459406000, 0.1919767000, 0.3159031000, 0.6418553000, 1.4404320000", \ - "0.1763118000, 0.1875794000, 0.2100568000, 0.2607484000, 0.3645380000, 0.6512482000, 1.4416730000", \ - "0.2645083000, 0.2805159000, 0.3163362000, 0.3874906000, 0.5250296000, 0.7789190000, 1.4664171000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0361737000, 0.0385997000, 0.0443005000, 0.0576247000, 0.0890511000, 0.1641690000, 0.3467383000", \ - "0.0404586000, 0.0428644000, 0.0485858000, 0.0620448000, 0.0936436000, 0.1687434000, 0.3513053000", \ - "0.0508619000, 0.0532167000, 0.0589249000, 0.0722656000, 0.1039062000, 0.1790637000, 0.3615413000", \ - "0.0705933000, 0.0733960000, 0.0806984000, 0.0963037000, 0.1279789000, 0.2033213000, 0.3860390000", \ - "0.0927670000, 0.0976174000, 0.1085822000, 0.1320302000, 0.1777363000, 0.2592944000, 0.4416891000", \ - "0.1092355000, 0.1160550000, 0.1330879000, 0.1683133000, 0.2389818000, 0.3633800000, 0.5716417000", \ - "0.0941040000, 0.1055969000, 0.1316856000, 0.1864668000, 0.2938607000, 0.4834476000, 0.8035093000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.1001276000, 0.1072520000, 0.1242201000, 0.1656137000, 0.2643970000, 0.5040272000, 1.0880092000", \ - "0.1020168000, 0.1092707000, 0.1265786000, 0.1683873000, 0.2680303000, 0.5080636000, 1.0928610000", \ - "0.1105895000, 0.1174347000, 0.1352803000, 0.1773442000, 0.2776144000, 0.5187875000, 1.1045308000", \ - "0.1374410000, 0.1440158000, 0.1608061000, 0.2019952000, 0.3021767000, 0.5441841000, 1.1313627000", \ - "0.2012061000, 0.2091874000, 0.2274822000, 0.2684834000, 0.3663520000, 0.6074857000, 1.1945431000", \ - "0.3072055000, 0.3194297000, 0.3468636000, 0.4067844000, 0.5228107000, 0.7593487000, 1.3465787000", \ - "0.4817986000, 0.4996913000, 0.5406966000, 0.6282003000, 0.8038266000, 1.1162068000, 1.7028980000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0307966000, 0.0335834000, 0.0405203000, 0.0572737000, 0.0986715000, 0.2001899000, 0.4491958000", \ - "0.0307033000, 0.0334806000, 0.0403777000, 0.0572275000, 0.0987137000, 0.2003907000, 0.4493658000", \ - "0.0312209000, 0.0338481000, 0.0403534000, 0.0568573000, 0.0986078000, 0.2002104000, 0.4499734000", \ - "0.0426489000, 0.0457548000, 0.0519207000, 0.0646410000, 0.1009408000, 0.2004089000, 0.4494381000", \ - "0.0660577000, 0.0697953000, 0.0777193000, 0.0961246000, 0.1325143000, 0.2131683000, 0.4493716000", \ - "0.1087224000, 0.1140303000, 0.1262739000, 0.1527881000, 0.2016709000, 0.2940548000, 0.4886168000", \ - "0.1830518000, 0.1918535000, 0.2114216000, 0.2523268000, 0.3266282000, 0.4605281000, 0.6785463000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0935433000, 0.1025381000, 0.1249932000, 0.1799783000, 0.3142673000, 0.6423077000, 1.4444210000", \ - "0.0934886000, 0.1024697000, 0.1252376000, 0.1800119000, 0.3143973000, 0.6436402000, 1.4462400000", \ - "0.0930792000, 0.1025343000, 0.1249763000, 0.1801139000, 0.3144118000, 0.6424346000, 1.4507320000", \ - "0.0940936000, 0.1028420000, 0.1246789000, 0.1798851000, 0.3142507000, 0.6424818000, 1.4470324000", \ - "0.1195445000, 0.1267244000, 0.1440753000, 0.1904252000, 0.3151345000, 0.6429776000, 1.4452518000", \ - "0.1747643000, 0.1848706000, 0.2088558000, 0.2588031000, 0.3615982000, 0.6513519000, 1.4512374000", \ - "0.2656341000, 0.2797533000, 0.3142477000, 0.3858805000, 0.5226940000, 0.7766116000, 1.4708995000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0407157000, 0.0431225000, 0.0489227000, 0.0624055000, 0.0938466000, 0.1688603000, 0.3512614000", \ - "0.0447135000, 0.0471392000, 0.0529412000, 0.0664290000, 0.0978886000, 0.1729872000, 0.3551249000", \ - "0.0528990000, 0.0553090000, 0.0611084000, 0.0747137000, 0.1062727000, 0.1813891000, 0.3635602000", \ - "0.0681215000, 0.0709518000, 0.0775459000, 0.0924796000, 0.1247416000, 0.2000133000, 0.3823108000", \ - "0.0892360000, 0.0933037000, 0.1024612000, 0.1223747000, 0.1619246000, 0.2423602000, 0.4254616000", \ - "0.1063924000, 0.1128122000, 0.1272642000, 0.1580147000, 0.2162792000, 0.3214151000, 0.5227994000", \ - "0.0935519000, 0.1036370000, 0.1265550000, 0.1757834000, 0.2683574000, 0.4290549000, 0.7002710000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.1180070000, 0.1251365000, 0.1420039000, 0.1823434000, 0.2795701000, 0.5165286000, 1.0946971000", \ - "0.1227462000, 0.1297013000, 0.1467626000, 0.1874086000, 0.2848253000, 0.5217114000, 1.1003242000", \ - "0.1348537000, 0.1421358000, 0.1591555000, 0.1998115000, 0.2976276000, 0.5349917000, 1.1135871000", \ - "0.1613095000, 0.1681087000, 0.1851602000, 0.2259641000, 0.3238777000, 0.5615906000, 1.1408005000", \ - "0.2153341000, 0.2230020000, 0.2413998000, 0.2824433000, 0.3802904000, 0.6184632000, 1.1975390000", \ - "0.3125007000, 0.3222349000, 0.3455462000, 0.3972465000, 0.5073992000, 0.7473880000, 1.3289605000", \ - "0.4806995000, 0.4953388000, 0.5295577000, 0.6028887000, 0.7484713000, 1.0343244000, 1.6269909000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0317634000, 0.0344881000, 0.0413633000, 0.0580629000, 0.0989882000, 0.2002803000, 0.4493320000", \ - "0.0316639000, 0.0345131000, 0.0413299000, 0.0580406000, 0.0990389000, 0.2003598000, 0.4499974000", \ - "0.0321924000, 0.0349635000, 0.0416451000, 0.0581341000, 0.0990309000, 0.2003849000, 0.4499978000", \ - "0.0385201000, 0.0411509000, 0.0474626000, 0.0623379000, 0.1010270000, 0.2002914000, 0.4502368000", \ - "0.0562386000, 0.0591455000, 0.0663647000, 0.0819916000, 0.1178127000, 0.2075385000, 0.4500837000", \ - "0.0926604000, 0.0967757000, 0.1062405000, 0.1261613000, 0.1664154000, 0.2540008000, 0.4707391000", \ - "0.1602132000, 0.1668069000, 0.1804140000, 0.2092138000, 0.2645165000, 0.3685847000, 0.5856551000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0979320000, 0.1069469000, 0.1290442000, 0.1831073000, 0.3155388000, 0.6424585000, 1.4407288000", \ - "0.0979507000, 0.1070527000, 0.1289490000, 0.1829428000, 0.3158201000, 0.6414688000, 1.4412841000", \ - "0.0979499000, 0.1068772000, 0.1290255000, 0.1830988000, 0.3156768000, 0.6415501000, 1.4409317000", \ - "0.0982707000, 0.1073076000, 0.1292425000, 0.1831400000, 0.3158850000, 0.6416906000, 1.4412890000", \ - "0.1103967000, 0.1185151000, 0.1385757000, 0.1890676000, 0.3167548000, 0.6428520000, 1.4410887000", \ - "0.1484944000, 0.1572967000, 0.1782681000, 0.2266309000, 0.3421110000, 0.6481097000, 1.4463140000", \ - "0.2315848000, 0.2424509000, 0.2665197000, 0.3201273000, 0.4413284000, 0.7213899000, 1.4582270000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.1162440000, 0.1189142000, 0.1253287000, 0.1398952000, 0.1736628000, 0.2533444000, 0.4461744000", \ - "0.1208268000, 0.1235059000, 0.1299154000, 0.1444896000, 0.1782362000, 0.2579452000, 0.4507813000", \ - "0.1334529000, 0.1362020000, 0.1425153000, 0.1570729000, 0.1908657000, 0.2705499000, 0.4633311000", \ - "0.1644389000, 0.1670370000, 0.1734747000, 0.1881111000, 0.2218908000, 0.3016397000, 0.4945639000", \ - "0.2294222000, 0.2321576000, 0.2386966000, 0.2536810000, 0.2877705000, 0.3676495000, 0.5604395000", \ - "0.3338085000, 0.3369049000, 0.3440647000, 0.3599291000, 0.3948873000, 0.4756839000, 0.6689352000", \ - "0.4994273000, 0.5030248000, 0.5114723000, 0.5292580000, 0.5671041000, 0.6500159000, 0.8440702000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.1468832000, 0.1540877000, 0.1708611000, 0.2112522000, 0.3091207000, 0.5476563000, 1.1313688000", \ - "0.1518438000, 0.1585210000, 0.1754460000, 0.2160566000, 0.3140073000, 0.5527925000, 1.1362470000", \ - "0.1624775000, 0.1694787000, 0.1862007000, 0.2267643000, 0.3249307000, 0.5639846000, 1.1477257000", \ - "0.1838889000, 0.1910980000, 0.2079032000, 0.2486779000, 0.3469796000, 0.5860479000, 1.1700333000", \ - "0.2135002000, 0.2206853000, 0.2375920000, 0.2782613000, 0.3768022000, 0.6160804000, 1.2002003000", \ - "0.2468683000, 0.2536219000, 0.2704987000, 0.3113794000, 0.4099961000, 0.6496099000, 1.2340697000", \ - "0.2684698000, 0.2757768000, 0.2926676000, 0.3337951000, 0.4322846000, 0.6717946000, 1.2567380000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0353675000, 0.0384423000, 0.0454822000, 0.0629508000, 0.1060235000, 0.2134647000, 0.4783064000", \ - "0.0353505000, 0.0384357000, 0.0454956000, 0.0629714000, 0.1060969000, 0.2133653000, 0.4786930000", \ - "0.0354367000, 0.0383331000, 0.0455009000, 0.0630080000, 0.1059754000, 0.2132442000, 0.4780385000", \ - "0.0354259000, 0.0384834000, 0.0455747000, 0.0630369000, 0.1060999000, 0.2133955000, 0.4788058000", \ - "0.0368357000, 0.0396182000, 0.0466371000, 0.0638853000, 0.1066171000, 0.2133144000, 0.4782141000", \ - "0.0419260000, 0.0446661000, 0.0513067000, 0.0678814000, 0.1095087000, 0.2151525000, 0.4788059000", \ - "0.0529640000, 0.0558265000, 0.0624816000, 0.0777262000, 0.1166658000, 0.2183734000, 0.4798463000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012248200, 0.0030003900, 0.0073499000, 0.0180047000, 0.0441052000, 0.1080420000"); - values("0.0933337000, 0.1025714000, 0.1248160000, 0.1796670000, 0.3140725000, 0.6416375000, 1.4492910000", \ - "0.0934919000, 0.1026615000, 0.1251978000, 0.1800859000, 0.3140533000, 0.6425702000, 1.4468882000", \ - "0.0936135000, 0.1028133000, 0.1250349000, 0.1800226000, 0.3143969000, 0.6448608000, 1.4502731000", \ - "0.0935349000, 0.1027775000, 0.1251498000, 0.1800227000, 0.3142435000, 0.6419517000, 1.4444629000", \ - "0.0942098000, 0.1033066000, 0.1254375000, 0.1802308000, 0.3146863000, 0.6422927000, 1.4456490000", \ - "0.0949966000, 0.1039857000, 0.1260816000, 0.1807013000, 0.3144759000, 0.6447634000, 1.4488689000", \ - "0.0993629000, 0.1081536000, 0.1293901000, 0.1825031000, 0.3150397000, 0.6432463000, 1.4480278000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux2i_4") { - leakage_power () { - value : 0.0042041000; - when : "!A0&!A1&S"; - } - leakage_power () { - value : 0.0024342000; - when : "!A0&!A1&!S"; - } - leakage_power () { - value : 0.0088269000; - when : "!A0&A1&S"; - } - leakage_power () { - value : 0.0037733000; - when : "!A0&A1&!S"; - } - leakage_power () { - value : 0.0057088000; - when : "A0&!A1&S"; - } - leakage_power () { - value : 0.0060484000; - when : "A0&!A1&!S"; - } - leakage_power () { - value : 0.0065226000; - when : "A0&A1&S"; - } - leakage_power () { - value : 0.0049325000; - when : "A0&A1&!S"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__mux2i"; - cell_leakage_power : 0.0053063500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0081010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0188478000, 0.0188385000, 0.0188173000, 0.0188121000, 0.0188001000, 0.0187726000, 0.0187091000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.011318500, -0.011468200, -0.011813200, -0.011817800, -0.011828400, -0.011852900, -0.011909400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085850000; - } - pin ("A1") { - capacitance : 0.0082660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0177537000, 0.0177423000, 0.0177161000, 0.0177148000, 0.0177117000, 0.0177046000, 0.0176883000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012904800, -0.012996000, -0.013206400, -0.013193900, -0.013165300, -0.013099300, -0.012947100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087230000; - } - pin ("S") { - capacitance : 0.0111250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0106520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0371004000, 0.0369125000, 0.0364795000, 0.0365683000, 0.0367729000, 0.0372446000, 0.0383318000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001494400, -0.001611300, -0.001880700, -0.001841600, -0.001751300, -0.001543400, -0.001064100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0115980000; - } - pin ("Y") { - direction : "output"; - function : "(!A0&!S) | (!A1&S)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0187792000, 0.0174957000, 0.0139610000, 0.0043742000, -0.021902400, -0.093466200, -0.287113800", \ - "0.0187875000, 0.0175035000, 0.0140137000, 0.0045129000, -0.021614700, -0.093078500, -0.286566800", \ - "0.0187719000, 0.0174899000, 0.0140114000, 0.0045612000, -0.021429900, -0.092700900, -0.286028100", \ - "0.0179763000, 0.0167192000, 0.0132872000, 0.0039084000, -0.021953400, -0.092927700, -0.286129500", \ - "0.0178536000, 0.0165430000, 0.0129517000, 0.0033138000, -0.022662400, -0.093498500, -0.286286500", \ - "0.0189026000, 0.0175356000, 0.0138796000, 0.0040321000, -0.022603900, -0.094124100, -0.286779400", \ - "0.0233156000, 0.0218348000, 0.0178839000, 0.0074402000, -0.019922400, -0.091559300, -0.286185800"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0279325000, 0.0294078000, 0.0332955000, 0.0435309000, 0.0704636000, 0.1418621000, 0.3333275000", \ - "0.0269835000, 0.0284617000, 0.0324114000, 0.0427810000, 0.0700970000, 0.1416929000, 0.3333172000", \ - "0.0256977000, 0.0271800000, 0.0309796000, 0.0414254000, 0.0689514000, 0.1411437000, 0.3331771000", \ - "0.0249071000, 0.0263363000, 0.0300516000, 0.0401190000, 0.0675057000, 0.1402674000, 0.3326510000", \ - "0.0245402000, 0.0259201000, 0.0296300000, 0.0396346000, 0.0665321000, 0.1386114000, 0.3315547000", \ - "0.0263746000, 0.0277259000, 0.0312722000, 0.0410165000, 0.0670965000, 0.1382388000, 0.3306519000", \ - "0.0320541000, 0.0333368000, 0.0367142000, 0.0458090000, 0.0711371000, 0.1412868000, 0.3307278000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0199213000, 0.0186152000, 0.0150619000, 0.0053631000, -0.021043900, -0.092748700, -0.286438200", \ - "0.0198595000, 0.0185589000, 0.0150676000, 0.0054539000, -0.020802700, -0.092374100, -0.285995300", \ - "0.0196147000, 0.0183293000, 0.0148439000, 0.0053407000, -0.020784000, -0.092157100, -0.285646000", \ - "0.0187060000, 0.0174299000, 0.0140616000, 0.0046189000, -0.021372000, -0.092447500, -0.285714300", \ - "0.0183698000, 0.0171144000, 0.0135941000, 0.0037046000, -0.021888000, -0.093021300, -0.285888500", \ - "0.0192267000, 0.0178494000, 0.0141896000, 0.0043476000, -0.022823700, -0.093917500, -0.286389800", \ - "0.0233582000, 0.0218777000, 0.0179283000, 0.0074582000, -0.019706600, -0.090931600, -0.286279800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0300106000, 0.0314531000, 0.0352762000, 0.0454583000, 0.0723184000, 0.1437748000, 0.3352698000", \ - "0.0291091000, 0.0305734000, 0.0344833000, 0.0448059000, 0.0720094000, 0.1435471000, 0.3351355000", \ - "0.0278997000, 0.0293844000, 0.0332816000, 0.0435741000, 0.0709727000, 0.1430817000, 0.3352085000", \ - "0.0268543000, 0.0283052000, 0.0320937000, 0.0423255000, 0.0697958000, 0.1422123000, 0.3345509000", \ - "0.0265734000, 0.0279369000, 0.0316395000, 0.0417604000, 0.0686950000, 0.1409189000, 0.3338679000", \ - "0.0287903000, 0.0301525000, 0.0332059000, 0.0434762000, 0.0697880000, 0.1403298000, 0.3325860000", \ - "0.0345284000, 0.0358545000, 0.0387106000, 0.0476068000, 0.0731143000, 0.1435092000, 0.3328612000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0218739000, 0.0205677000, 0.0170238000, 0.0074156000, -0.018973300, -0.090706400, -0.284336600", \ - "0.0218631000, 0.0205348000, 0.0169938000, 0.0073923000, -0.018980900, -0.090724300, -0.284370900", \ - "0.0219291000, 0.0206236000, 0.0171351000, 0.0075125000, -0.018866500, -0.090606700, -0.284258900", \ - "0.0214923000, 0.0201954000, 0.0166537000, 0.0070853000, -0.019260000, -0.090972700, -0.284619500", \ - "0.0207456000, 0.0194260000, 0.0159270000, 0.0064070000, -0.019849600, -0.091493700, -0.285156400", \ - "0.0193025000, 0.0180696000, 0.0149334000, 0.0061266000, -0.019871100, -0.091421700, -0.284995600", \ - "0.0208093000, 0.0194446000, 0.0158617000, 0.0060210000, -0.020633500, -0.092125300, -0.284537600"); - } - related_pin : "S"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013461740, 0.0036243690, 0.0097580630, 0.0262721100, 0.0707336500, 0.1904396000"); - values("0.0396886000, 0.0410714000, 0.0447364000, 0.0545718000, 0.0808615000, 0.1517473000, 0.3428176000", \ - "0.0395605000, 0.0409087000, 0.0445863000, 0.0544623000, 0.0808385000, 0.1516937000, 0.3429116000", \ - "0.0392762000, 0.0406218000, 0.0443150000, 0.0542274000, 0.0806859000, 0.1519348000, 0.3428407000", \ - "0.0385708000, 0.0399611000, 0.0436247000, 0.0535631000, 0.0802050000, 0.1513261000, 0.3424661000", \ - "0.0381861000, 0.0395730000, 0.0432555000, 0.0532285000, 0.0799660000, 0.1512838000, 0.3424249000", \ - "0.0375539000, 0.0389420000, 0.0426431000, 0.0526655000, 0.0792498000, 0.1506397000, 0.3419635000", \ - "0.0394044000, 0.0407841000, 0.0444063000, 0.0543366000, 0.0805434000, 0.1515644000, 0.3426099000"); - } - } - max_capacitance : 0.1904400000; - max_transition : 1.4686160000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0333925000, 0.0350213000, 0.0391215000, 0.0497507000, 0.0766623000, 0.1464078000, 0.3316810000", \ - "0.0377216000, 0.0392818000, 0.0434750000, 0.0541577000, 0.0811079000, 0.1509291000, 0.3363459000", \ - "0.0483136000, 0.0498368000, 0.0538682000, 0.0644144000, 0.0912435000, 0.1612747000, 0.3468296000", \ - "0.0672244000, 0.0692651000, 0.0747315000, 0.0877060000, 0.1153968000, 0.1847384000, 0.3704292000", \ - "0.0874012000, 0.0906375000, 0.0988846000, 0.1185150000, 0.1601022000, 0.2408883000, 0.4261417000", \ - "0.0992545000, 0.1041561000, 0.1167582000, 0.1467196000, 0.2115195000, 0.3348576000, 0.5551082000", \ - "0.0766168000, 0.0841121000, 0.1032633000, 0.1488824000, 0.2483259000, 0.4375335000, 0.7754174000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0987302000, 0.1033645000, 0.1164523000, 0.1496578000, 0.2365148000, 0.4666548000, 1.0836479000", \ - "0.1008442000, 0.1057114000, 0.1184311000, 0.1523068000, 0.2399122000, 0.4709286000, 1.0875433000", \ - "0.1089933000, 0.1136261000, 0.1262277000, 0.1600718000, 0.2487758000, 0.4809746000, 1.0989321000", \ - "0.1348995000, 0.1393099000, 0.1514608000, 0.1846679000, 0.2728066000, 0.5058116000, 1.1251201000", \ - "0.1981237000, 0.2035668000, 0.2173982000, 0.2507774000, 0.3372073000, 0.5681822000, 1.1908595000", \ - "0.3028139000, 0.3107526000, 0.3313790000, 0.3818011000, 0.4893415000, 0.7199926000, 1.3379545000", \ - "0.4764614000, 0.4881899000, 0.5182728000, 0.5927245000, 0.7538111000, 1.0704575000, 1.6850982000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0296152000, 0.0313744000, 0.0360278000, 0.0487999000, 0.0836598000, 0.1780080000, 0.4335491000", \ - "0.0294030000, 0.0311953000, 0.0359179000, 0.0487694000, 0.0836703000, 0.1783343000, 0.4333121000", \ - "0.0300808000, 0.0316913000, 0.0360808000, 0.0484106000, 0.0834025000, 0.1782950000, 0.4332182000", \ - "0.0407530000, 0.0426843000, 0.0473285000, 0.0581235000, 0.0873852000, 0.1778890000, 0.4336381000", \ - "0.0624797000, 0.0650322000, 0.0713544000, 0.0863329000, 0.1192163000, 0.1942369000, 0.4333054000", \ - "0.1020489000, 0.1059603000, 0.1155392000, 0.1378711000, 0.1842371000, 0.2737749000, 0.4751796000", \ - "0.1730274000, 0.1790708000, 0.1939710000, 0.2283633000, 0.2988000000, 0.4293631000, 0.6686905000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0911408000, 0.0972255000, 0.1137003000, 0.1572432000, 0.2748790000, 0.5911564000, 1.4432117000", \ - "0.0913122000, 0.0971569000, 0.1134475000, 0.1574597000, 0.2747287000, 0.5921991000, 1.4385390000", \ - "0.0911012000, 0.0972165000, 0.1134664000, 0.1575737000, 0.2748696000, 0.5922406000, 1.4429462000", \ - "0.0916935000, 0.0975149000, 0.1133782000, 0.1572629000, 0.2746599000, 0.5904586000, 1.4424028000", \ - "0.1176377000, 0.1221272000, 0.1344626000, 0.1700881000, 0.2780372000, 0.5925976000, 1.4439508000", \ - "0.1678329000, 0.1751604000, 0.1937080000, 0.2365647000, 0.3303230000, 0.6027024000, 1.4442747000", \ - "0.2514178000, 0.2620363000, 0.2882634000, 0.3507953000, 0.4819424000, 0.7374936000, 1.4686159000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0369343000, 0.0386696000, 0.0430950000, 0.0545891000, 0.0840958000, 0.1606243000, 0.3637617000", \ - "0.0410662000, 0.0428251000, 0.0473444000, 0.0590116000, 0.0885247000, 0.1652048000, 0.3685822000", \ - "0.0512551000, 0.0529444000, 0.0574334000, 0.0689383000, 0.0985657000, 0.1753499000, 0.3786848000", \ - "0.0707696000, 0.0730221000, 0.0788527000, 0.0921666000, 0.1221968000, 0.1990475000, 0.4030810000", \ - "0.0916799000, 0.0949560000, 0.1035262000, 0.1246326000, 0.1681920000, 0.2532930000, 0.4566916000", \ - "0.1062959000, 0.1114433000, 0.1243630000, 0.1553637000, 0.2234002000, 0.3527811000, 0.5820618000", \ - "0.0863275000, 0.0943212000, 0.1141826000, 0.1618372000, 0.2645651000, 0.4617345000, 0.8165951000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0965714000, 0.1010384000, 0.1130030000, 0.1451127000, 0.2283535000, 0.4493214000, 1.0410453000", \ - "0.0986240000, 0.1036082000, 0.1159759000, 0.1482077000, 0.2322894000, 0.4537924000, 1.0457415000", \ - "0.1074289000, 0.1121548000, 0.1243049000, 0.1566589000, 0.2415327000, 0.4644650000, 1.0572121000", \ - "0.1331240000, 0.1377775000, 0.1496062000, 0.1813907000, 0.2661517000, 0.4897531000, 1.0844019000", \ - "0.1964862000, 0.2018619000, 0.2150109000, 0.2476825000, 0.3300094000, 0.5527452000, 1.1482572000", \ - "0.3010692000, 0.3090282000, 0.3290220000, 0.3775054000, 0.4820134000, 0.7025914000, 1.2992560000", \ - "0.4738336000, 0.4853271000, 0.5139615000, 0.5858039000, 0.7431071000, 1.0506647000, 1.6539025000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0327358000, 0.0347043000, 0.0400606000, 0.0545124000, 0.0937610000, 0.1998649000, 0.4877864000", \ - "0.0326523000, 0.0346599000, 0.0399526000, 0.0544503000, 0.0935806000, 0.2000685000, 0.4876743000", \ - "0.0328563000, 0.0347597000, 0.0399268000, 0.0541158000, 0.0935308000, 0.2000833000, 0.4872001000", \ - "0.0431971000, 0.0452545000, 0.0508318000, 0.0624362000, 0.0965741000, 0.1998336000, 0.4873144000", \ - "0.0649883000, 0.0677778000, 0.0747877000, 0.0900548000, 0.1281421000, 0.2142953000, 0.4875347000", \ - "0.1049473000, 0.1089562000, 0.1193320000, 0.1432542000, 0.1925867000, 0.2918365000, 0.5243947000", \ - "0.1769989000, 0.1833104000, 0.1990534000, 0.2348009000, 0.3090840000, 0.4509594000, 0.7081691000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0891081000, 0.0949913000, 0.1110246000, 0.1534428000, 0.2672506000, 0.5723468000, 1.3974015000", \ - "0.0891818000, 0.0951697000, 0.1106839000, 0.1534498000, 0.2678553000, 0.5726911000, 1.3926972000", \ - "0.0889793000, 0.0950468000, 0.1108021000, 0.1535435000, 0.2671500000, 0.5749882000, 1.3974910000", \ - "0.0895296000, 0.0950304000, 0.1104689000, 0.1531924000, 0.2670164000, 0.5726991000, 1.3979043000", \ - "0.1153904000, 0.1197112000, 0.1319107000, 0.1668358000, 0.2696862000, 0.5726511000, 1.3951020000", \ - "0.1656404000, 0.1726760000, 0.1906402000, 0.2321874000, 0.3233798000, 0.5851232000, 1.3986324000", \ - "0.2510734000, 0.2614399000, 0.2859354000, 0.3463372000, 0.4740356000, 0.7254301000, 1.4190408000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0405641000, 0.0422880000, 0.0465922000, 0.0579565000, 0.0872328000, 0.1636022000, 0.3666515000", \ - "0.0444559000, 0.0460738000, 0.0505002000, 0.0618229000, 0.0911222000, 0.1675238000, 0.3706223000", \ - "0.0522402000, 0.0538928000, 0.0582722000, 0.0696486000, 0.0990101000, 0.1754517000, 0.3785739000", \ - "0.0666552000, 0.0686208000, 0.0735622000, 0.0861200000, 0.1166163000, 0.1932526000, 0.3966658000", \ - "0.0864586000, 0.0892468000, 0.0962420000, 0.1128819000, 0.1500507000, 0.2332908000, 0.4376299000", \ - "0.1007684000, 0.1050830000, 0.1158734000, 0.1413948000, 0.1972328000, 0.3063736000, 0.5301422000", \ - "0.0830222000, 0.0897520000, 0.1068923000, 0.1472222000, 0.2348684000, 0.4023477000, 0.7006488000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.1138836000, 0.1185428000, 0.1305812000, 0.1629833000, 0.2489144000, 0.4783327000, 1.0940355000", \ - "0.1182673000, 0.1228740000, 0.1350862000, 0.1677105000, 0.2540029000, 0.4836606000, 1.1009625000", \ - "0.1300382000, 0.1346695000, 0.1469343000, 0.1797794000, 0.2664955000, 0.4966295000, 1.1147603000", \ - "0.1556842000, 0.1602803000, 0.1724868000, 0.2052464000, 0.2921522000, 0.5227929000, 1.1391813000", \ - "0.2076579000, 0.2127373000, 0.2263232000, 0.2603379000, 0.3468315000, 0.5774773000, 1.1948853000", \ - "0.2994480000, 0.3061600000, 0.3232745000, 0.3659790000, 0.4665232000, 0.7022841000, 1.3197601000", \ - "0.4585791000, 0.4684254000, 0.4935453000, 0.5544349000, 0.6890651000, 0.9747180000, 1.6100166000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0325563000, 0.0345649000, 0.0399104000, 0.0543620000, 0.0935826000, 0.1998992000, 0.4872282000", \ - "0.0324686000, 0.0345124000, 0.0398210000, 0.0543606000, 0.0934546000, 0.1999758000, 0.4872123000", \ - "0.0330464000, 0.0349732000, 0.0401207000, 0.0542898000, 0.0935143000, 0.1998187000, 0.4872088000", \ - "0.0391504000, 0.0409699000, 0.0460045000, 0.0593605000, 0.0958436000, 0.1997773000, 0.4873097000", \ - "0.0557868000, 0.0579400000, 0.0634122000, 0.0772699000, 0.1129611000, 0.2084915000, 0.4879291000", \ - "0.0907985000, 0.0935624000, 0.1006021000, 0.1183560000, 0.1594805000, 0.2538765000, 0.5064303000", \ - "0.1555608000, 0.1599418000, 0.1709830000, 0.1964680000, 0.2531820000, 0.3642216000, 0.6164397000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0910509000, 0.0970755000, 0.1134974000, 0.1572071000, 0.2748843000, 0.5906417000, 1.4402024000", \ - "0.0910296000, 0.0970999000, 0.1135587000, 0.1574135000, 0.2748168000, 0.5922674000, 1.4445023000", \ - "0.0910262000, 0.0970732000, 0.1135609000, 0.1574153000, 0.2747942000, 0.5922673000, 1.4441564000", \ - "0.0912957000, 0.0972842000, 0.1135307000, 0.1572421000, 0.2745888000, 0.5907386000, 1.4384589000", \ - "0.1046801000, 0.1098741000, 0.1241077000, 0.1647581000, 0.2764549000, 0.5908014000, 1.4435624000", \ - "0.1395404000, 0.1454743000, 0.1607895000, 0.2020756000, 0.3058779000, 0.6010499000, 1.4389390000", \ - "0.2186948000, 0.2264848000, 0.2447394000, 0.2903764000, 0.4024518000, 0.6766617000, 1.4590681000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.1533500000, 0.1552026000, 0.1600312000, 0.1717874000, 0.2007008000, 0.2721142000, 0.4576767000", \ - "0.1583920000, 0.1602627000, 0.1650748000, 0.1768759000, 0.2056609000, 0.2771512000, 0.4626476000", \ - "0.1708371000, 0.1727031000, 0.1775828000, 0.1893945000, 0.2182197000, 0.2896922000, 0.4752644000", \ - "0.2016707000, 0.2035373000, 0.2083835000, 0.2201690000, 0.2490961000, 0.3206009000, 0.5062041000", \ - "0.2743642000, 0.2763344000, 0.2810107000, 0.2930533000, 0.3220811000, 0.3937007000, 0.5792678000", \ - "0.4075236000, 0.4093179000, 0.4148743000, 0.4281482000, 0.4585053000, 0.5315298000, 0.7176004000", \ - "0.6146513000, 0.6173168000, 0.6244043000, 0.6405175000, 0.6753688000, 0.7527020000, 0.9412265000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.1670885000, 0.1715183000, 0.1828509000, 0.2138491000, 0.2959850000, 0.5153880000, 1.1047174000", \ - "0.1720794000, 0.1767492000, 0.1881169000, 0.2193599000, 0.3016095000, 0.5210279000, 1.1112834000", \ - "0.1832232000, 0.1878024000, 0.1992810000, 0.2306145000, 0.3130702000, 0.5328443000, 1.1242339000", \ - "0.2086906000, 0.2130362000, 0.2245652000, 0.2559391000, 0.3385916000, 0.5586397000, 1.1492470000", \ - "0.2507136000, 0.2551902000, 0.2668922000, 0.2981539000, 0.3810644000, 0.6014747000, 1.1931637000", \ - "0.3038313000, 0.3084891000, 0.3200799000, 0.3517962000, 0.4347442000, 0.6553412000, 1.2480081000", \ - "0.3556077000, 0.3602345000, 0.3724748000, 0.4045311000, 0.4880522000, 0.7088237000, 1.3004454000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0372635000, 0.0389725000, 0.0434234000, 0.0558479000, 0.0894485000, 0.1807749000, 0.4333669000", \ - "0.0371886000, 0.0388412000, 0.0434356000, 0.0558663000, 0.0892240000, 0.1807322000, 0.4338500000", \ - "0.0371918000, 0.0388991000, 0.0435209000, 0.0558535000, 0.0892588000, 0.1807750000, 0.4335043000", \ - "0.0372554000, 0.0389650000, 0.0434190000, 0.0558548000, 0.0892489000, 0.1807990000, 0.4333938000", \ - "0.0376803000, 0.0393108000, 0.0439011000, 0.0560249000, 0.0892390000, 0.1808317000, 0.4338127000", \ - "0.0444793000, 0.0460484000, 0.0505452000, 0.0619961000, 0.0937815000, 0.1830346000, 0.4344755000", \ - "0.0594136000, 0.0609685000, 0.0656929000, 0.0769608000, 0.1062627000, 0.1908771000, 0.4365470000"); - } - related_pin : "S"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013461700, 0.0036243700, 0.0097580600, 0.0262721000, 0.0707337000, 0.1904400000"); - values("0.0896298000, 0.0955108000, 0.1108778000, 0.1529856000, 0.2663815000, 0.5733126000, 1.3904674000", \ - "0.0899187000, 0.0958258000, 0.1113841000, 0.1535743000, 0.2676476000, 0.5715571000, 1.3945576000", \ - "0.0900602000, 0.0959265000, 0.1115420000, 0.1537896000, 0.2676264000, 0.5726504000, 1.3947307000", \ - "0.0902217000, 0.0960232000, 0.1116434000, 0.1538669000, 0.2671492000, 0.5727722000, 1.3924976000", \ - "0.0905185000, 0.0963519000, 0.1120307000, 0.1541942000, 0.2678496000, 0.5728801000, 1.3979267000", \ - "0.0925867000, 0.0983641000, 0.1135375000, 0.1551595000, 0.2678988000, 0.5736566000, 1.3983675000", \ - "0.0988664000, 0.1042897000, 0.1190894000, 0.1591058000, 0.2695477000, 0.5735505000, 1.3932283000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux4_1") { - leakage_power () { - value : 0.0137458000; - when : "!A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0116037000; - when : "!A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0158573000; - when : "!A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0137152000; - when : "!A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0140316000; - when : "!A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0118895000; - when : "!A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0087038000; - when : "!A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0161449000; - when : "!A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0065285000; - when : "!A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0139696000; - when : "!A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0161416000; - when : "!A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0139995000; - when : "!A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0058742000; - when : "!A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0133153000; - when : "!A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0078557000; - when : "!A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0152968000; - when : "!A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0140134000; - when : "!A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0118712000; - when : "!A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0193198000; - when : "!A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0062357000; - when : "!A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0142992000; - when : "!A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0121571000; - when : "!A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0085645000; - when : "!A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0064224000; - when : "!A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0067961000; - when : "!A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0142372000; - when : "!A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0196041000; - when : "!A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0065201000; - when : "!A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0061418000; - when : "!A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0135829000; - when : "!A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0077164000; - when : "!A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0055743000; - when : "!A0&A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0171159000; - when : "A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0040318000; - when : "A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0162469000; - when : "A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0141048000; - when : "A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0174018000; - when : "A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0043177000; - when : "A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0090934000; - when : "A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0165345000; - when : "A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0062968000; - when : "A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0041546000; - when : "A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0165312000; - when : "A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0143891000; - when : "A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0056425000; - when : "A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0035004000; - when : "A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0082453000; - when : "A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0156864000; - when : "A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0161641000; - when : "A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0030800000; - when : "A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0183565000; - when : "A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0052725000; - when : "A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0164499000; - when : "A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0033659000; - when : "A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0076012000; - when : "A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0054591000; - when : "A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0053449000; - when : "A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0032028000; - when : "A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0186409000; - when : "A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0055568000; - when : "A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0046907000; - when : "A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0025486000; - when : "A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0067531000; - when : "A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0046110000; - when : "A0&A1&A2&A3&S0&!S1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__mux4"; - cell_leakage_power : 0.0105018800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0015250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0108004000, 0.0107252000, 0.0105520000, 0.0105549000, 0.0105614000, 0.0105768000, 0.0106121000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050509000, 0.0050113000, 0.0049199000, 0.0049420000, 0.0049929000, 0.0051104000, 0.0053813000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015740000; - } - pin ("A1") { - capacitance : 0.0014380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020590000, 0.0020531000, 0.0020396000, 0.0020395000, 0.0020390000, 0.0020380000, 0.0020358000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001912400, -0.001922600, -0.001946200, -0.001948400, -0.001953700, -0.001965700, -0.001993400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014800000; - } - pin ("A2") { - capacitance : 0.0014640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086365000, 0.0085740000, 0.0084300000, 0.0084297000, 0.0084288000, 0.0084270000, 0.0084228000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0065099000, 0.0064677000, 0.0063705000, 0.0063839000, 0.0064146000, 0.0064857000, 0.0066496000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015100000; - } - pin ("A3") { - capacitance : 0.0014780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023059000, 0.0023023000, 0.0022941000, 0.0022945000, 0.0022952000, 0.0022971000, 0.0023015000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002222200, -0.002231400, -0.002252600, -0.002253300, -0.002255100, -0.002259100, -0.002268200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015180000; - } - pin ("S0") { - capacitance : 0.0038950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0037000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0153468000, 0.0151944000, 0.0148432000, 0.0148869000, 0.0149876000, 0.0152199000, 0.0157554000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0034915000, 0.0033720000, 0.0030965000, 0.0031518000, 0.0032792000, 0.0035729000, 0.0042501000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0040890000; - } - pin ("S1") { - capacitance : 0.0026750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0026070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084846000, 0.0083717000, 0.0081114000, 0.0081627000, 0.0082808000, 0.0085532000, 0.0091811000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0008260000, 0.0007332000, 0.0005193000, 0.0005749000, 0.0007030000, 0.0009983000, 0.0016792000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0027440000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S0&!S1) | (A1&S0&!S1) | (A2&!S0&S1) | (A3&S0&S1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0059481000, 0.0046562000, 0.0017191000, -0.006269400, -0.028379200, -0.089151500, -0.250279900", \ - "0.0059135000, 0.0046558000, 0.0017100000, -0.006244100, -0.028404700, -0.089176200, -0.250264000", \ - "0.0060027000, 0.0047619000, 0.0018243000, -0.006139700, -0.028268100, -0.089047600, -0.250162700", \ - "0.0059120000, 0.0046895000, 0.0016624000, -0.006229600, -0.028401900, -0.089164900, -0.250253600", \ - "0.0058404000, 0.0045742000, 0.0015987000, -0.006339000, -0.028484400, -0.089279900, -0.250345400", \ - "0.0058221000, 0.0045534000, 0.0015485000, -0.006388200, -0.028573000, -0.089381300, -0.250439500", \ - "0.0076036000, 0.0060750000, 0.0023208000, -0.006461800, -0.028578700, -0.089365900, -0.250424100"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0115631000, 0.0130373000, 0.0168632000, 0.0261743000, 0.0497513000, 0.1108908000, 0.2702471000", \ - "0.0115721000, 0.0130360000, 0.0168683000, 0.0262047000, 0.0497071000, 0.1108800000, 0.2713143000", \ - "0.0115967000, 0.0130835000, 0.0169196000, 0.0262209000, 0.0498049000, 0.1108958000, 0.2706444000", \ - "0.0115100000, 0.0129840000, 0.0168321000, 0.0261211000, 0.0496983000, 0.1108079000, 0.2700842000", \ - "0.0114423000, 0.0129114000, 0.0167349000, 0.0260124000, 0.0495332000, 0.1106592000, 0.2705351000", \ - "0.0119513000, 0.0132718000, 0.0166298000, 0.0258164000, 0.0492199000, 0.1104153000, 0.2702854000", \ - "0.0123690000, 0.0136700000, 0.0171279000, 0.0261011000, 0.0492696000, 0.1106086000, 0.2695234000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0172384000, 0.0159773000, 0.0130468000, 0.0052229000, -0.016772400, -0.077443500, -0.238511300", \ - "0.0171604000, 0.0159323000, 0.0130573000, 0.0051751000, -0.016811700, -0.077486100, -0.238520300", \ - "0.0171225000, 0.0158650000, 0.0129531000, 0.0050917000, -0.016909500, -0.077564600, -0.238602200", \ - "0.0170423000, 0.0157633000, 0.0128504000, 0.0050349000, -0.016957000, -0.077663300, -0.238686000", \ - "0.0169421000, 0.0157122000, 0.0128135000, 0.0049607000, -0.017065000, -0.077745200, -0.238776600", \ - "0.0169397000, 0.0156909000, 0.0127776000, 0.0048928000, -0.017173100, -0.077830800, -0.238849100", \ - "0.0187262000, 0.0171925000, 0.0134374000, 0.0048701000, -0.017103200, -0.077814400, -0.238827200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0153355000, 0.0167542000, 0.0204871000, 0.0297900000, 0.0532563000, 0.1144039000, 0.2751977000", \ - "0.0152772000, 0.0167085000, 0.0204666000, 0.0297083000, 0.0532176000, 0.1144098000, 0.2748566000", \ - "0.0152516000, 0.0166828000, 0.0204402000, 0.0296810000, 0.0531904000, 0.1143827000, 0.2748279000", \ - "0.0152068000, 0.0166394000, 0.0203698000, 0.0296651000, 0.0531262000, 0.1142833000, 0.2751001000", \ - "0.0151854000, 0.0166108000, 0.0203369000, 0.0295661000, 0.0530930000, 0.1141985000, 0.2737158000", \ - "0.0155469000, 0.0168487000, 0.0202850000, 0.0295174000, 0.0528762000, 0.1143241000, 0.2736481000", \ - "0.0162053000, 0.0175074000, 0.0209919000, 0.0299420000, 0.0530929000, 0.1142682000, 0.2734860000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0090409000, 0.0077541000, 0.0048381000, -0.003062700, -0.025184800, -0.085995600, -0.247086600", \ - "0.0089691000, 0.0077224000, 0.0048000000, -0.003107100, -0.025264100, -0.086019500, -0.247087300", \ - "0.0090467000, 0.0077938000, 0.0048703000, -0.003067100, -0.025198400, -0.085966200, -0.247020100", \ - "0.0089496000, 0.0077026000, 0.0047801000, -0.003110700, -0.025259300, -0.085977700, -0.247109200", \ - "0.0088597000, 0.0076334000, 0.0046782000, -0.003194300, -0.025364200, -0.086126200, -0.247201500", \ - "0.0088944000, 0.0076363000, 0.0046516000, -0.003253100, -0.025424100, -0.086228500, -0.247278900", \ - "0.0107171000, 0.0091853000, 0.0054411000, -0.003326700, -0.025414400, -0.086191700, -0.247236800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0080953000, 0.0095270000, 0.0133018000, 0.0226059000, 0.0460494000, 0.1070979000, 0.2667809000", \ - "0.0080588000, 0.0095158000, 0.0132942000, 0.0225602000, 0.0460580000, 0.1071847000, 0.2680293000", \ - "0.0081219000, 0.0095646000, 0.0133155000, 0.0226421000, 0.0460860000, 0.1072032000, 0.2680302000", \ - "0.0080384000, 0.0094960000, 0.0132635000, 0.0225243000, 0.0460366000, 0.1070961000, 0.2676599000", \ - "0.0079836000, 0.0094208000, 0.0131696000, 0.0224456000, 0.0458889000, 0.1068850000, 0.2669445000", \ - "0.0083412000, 0.0096637000, 0.0130210000, 0.0222659000, 0.0456265000, 0.1067135000, 0.2667172000", \ - "0.0087931000, 0.0100996000, 0.0134705000, 0.0225202000, 0.0456737000, 0.1068439000, 0.2668362000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0164479000, 0.0152232000, 0.0123019000, 0.0044886000, -0.017580100, -0.078360200, -0.239443000", \ - "0.0164000000, 0.0151604000, 0.0122687000, 0.0044056000, -0.017672400, -0.078424300, -0.239490400", \ - "0.0163373000, 0.0150946000, 0.0121652000, 0.0043412000, -0.017739100, -0.078491100, -0.239557500", \ - "0.0162442000, 0.0150052000, 0.0121176000, 0.0042683000, -0.017769500, -0.078561300, -0.239632700", \ - "0.0161488000, 0.0149243000, 0.0120150000, 0.0041712000, -0.017917500, -0.078713500, -0.239738500", \ - "0.0161544000, 0.0149407000, 0.0120371000, 0.0041260000, -0.017996600, -0.078780100, -0.239824800", \ - "0.0181283000, 0.0165939000, 0.0128508000, 0.0040557000, -0.017981200, -0.078764600, -0.239792800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0140796000, 0.0154714000, 0.0191615000, 0.0283693000, 0.0518207000, 0.1127334000, 0.2726772000", \ - "0.0140475000, 0.0154527000, 0.0191220000, 0.0283073000, 0.0518219000, 0.1128476000, 0.2725675000", \ - "0.0140200000, 0.0154131000, 0.0191030000, 0.0283156000, 0.0517531000, 0.1127138000, 0.2724332000", \ - "0.0139525000, 0.0153622000, 0.0190271000, 0.0282680000, 0.0516779000, 0.1127668000, 0.2731441000", \ - "0.0139223000, 0.0153181000, 0.0189956000, 0.0281771000, 0.0516159000, 0.1125346000, 0.2725380000", \ - "0.0142442000, 0.0155303000, 0.0189348000, 0.0280941000, 0.0514009000, 0.1125480000, 0.2723184000", \ - "0.0147418000, 0.0160107000, 0.0194431000, 0.0285072000, 0.0516226000, 0.1126678000, 0.2718328000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0184749000, 0.0172705000, 0.0143327000, 0.0064797000, -0.015510500, -0.076178300, -0.237221200", \ - "0.0184748000, 0.0172436000, 0.0143497000, 0.0064770000, -0.015516300, -0.076182000, -0.237237400", \ - "0.0184653000, 0.0172410000, 0.0143127000, 0.0064990000, -0.015531900, -0.076205900, -0.237245400", \ - "0.0177666000, 0.0165267000, 0.0135854000, 0.0057959000, -0.016219800, -0.076897700, -0.237920200", \ - "0.0171542000, 0.0159076000, 0.0130376000, 0.0051569000, -0.016823700, -0.077475100, -0.238531200", \ - "0.0165819000, 0.0153845000, 0.0124336000, 0.0046130000, -0.017337100, -0.077997600, -0.239014900", \ - "0.0208433000, 0.0193635000, 0.0157447000, 0.0066510000, -0.016878200, -0.077656400, -0.238638400"); - } - related_pin : "S0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0234401000, 0.0249210000, 0.0287619000, 0.0380620000, 0.0616178000, 0.1226766000, 0.2828010000", \ - "0.0233995000, 0.0248659000, 0.0286625000, 0.0379733000, 0.0615207000, 0.1227276000, 0.2831125000", \ - "0.0235246000, 0.0249939000, 0.0287879000, 0.0380979000, 0.0616108000, 0.1228600000, 0.2832466000", \ - "0.0232735000, 0.0247381000, 0.0285652000, 0.0378623000, 0.0614386000, 0.1225865000, 0.2821293000", \ - "0.0229430000, 0.0244103000, 0.0282251000, 0.0375095000, 0.0610814000, 0.1223159000, 0.2828045000", \ - "0.0225571000, 0.0240328000, 0.0278814000, 0.0372331000, 0.0607479000, 0.1218186000, 0.2824158000", \ - "0.0227936000, 0.0241312000, 0.0276333000, 0.0366581000, 0.0606013000, 0.1217088000, 0.2810817000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0076263000, 0.0064341000, 0.0035829000, -0.004175000, -0.026266100, -0.087118400, -0.248286000", \ - "0.0076801000, 0.0064863000, 0.0036353000, -0.004161200, -0.026236300, -0.087062700, -0.248229400", \ - "0.0078325000, 0.0066337000, 0.0038120000, -0.003965600, -0.026052800, -0.086900900, -0.248066900", \ - "0.0077769000, 0.0066052000, 0.0037377000, -0.004008900, -0.026069600, -0.086898900, -0.248061800", \ - "0.0077268000, 0.0065937000, 0.0037779000, -0.003958000, -0.026024000, -0.086796100, -0.247931400", \ - "0.0093264000, 0.0079336000, 0.0044627000, -0.003436100, -0.025576400, -0.086375800, -0.247479000", \ - "0.0134992000, 0.0121364000, 0.0086940000, -0.000184400, -0.023544600, -0.085069100, -0.246236700"); - } - related_pin : "S1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0121377000, 0.0135760000, 0.0173405000, 0.0265911000, 0.0500171000, 0.1111099000, 0.2719908000", \ - "0.0120013000, 0.0134626000, 0.0172394000, 0.0264880000, 0.0499362000, 0.1108458000, 0.2710566000", \ - "0.0121146000, 0.0135562000, 0.0173107000, 0.0265623000, 0.0500643000, 0.1110967000, 0.2718774000", \ - "0.0120975000, 0.0135384000, 0.0172907000, 0.0265515000, 0.0500508000, 0.1110944000, 0.2719406000", \ - "0.0122339000, 0.0136986000, 0.0174522000, 0.0267385000, 0.0501590000, 0.1109793000, 0.2713749000", \ - "0.0127289000, 0.0140209000, 0.0179575000, 0.0272933000, 0.0506745000, 0.1116608000, 0.2717367000", \ - "0.0138255000, 0.0151744000, 0.0186562000, 0.0277587000, 0.0511335000, 0.1124942000, 0.2713970000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5063560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.4305261000, 0.4433747000, 0.4707105000, 0.5203642000, 0.6094312000, 0.7784000000, 1.1448035000", \ - "0.4349955000, 0.4484747000, 0.4757554000, 0.5255227000, 0.6142764000, 0.7834726000, 1.1496277000", \ - "0.4473923000, 0.4611971000, 0.4884600000, 0.5379664000, 0.6271010000, 0.7960110000, 1.1624196000", \ - "0.4744450000, 0.4881490000, 0.5153927000, 0.5650636000, 0.6538657000, 0.8230113000, 1.1892562000", \ - "0.5319831000, 0.5455890000, 0.5726986000, 0.6222999000, 0.7112191000, 0.8800917000, 1.2464832000", \ - "0.6616791000, 0.6753029000, 0.7026374000, 0.7519140000, 0.8412075000, 1.0101172000, 1.3765592000", \ - "0.9145905000, 0.9297085000, 0.9587965000, 1.0121265000, 1.1052587000, 1.2786883000, 1.6469760000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1717983000, 0.1813912000, 0.2020530000, 0.2453318000, 0.3429268000, 0.5866390000, 1.2188831000", \ - "0.1763315000, 0.1858235000, 0.2064409000, 0.2498500000, 0.3472704000, 0.5901197000, 1.2224211000", \ - "0.1851639000, 0.1948254000, 0.2154342000, 0.2587976000, 0.3562944000, 0.5999626000, 1.2328480000", \ - "0.2048376000, 0.2144553000, 0.2350892000, 0.2783584000, 0.3759355000, 0.6196473000, 1.2514763000", \ - "0.2467429000, 0.2564435000, 0.2771971000, 0.3206292000, 0.4179758000, 0.6616040000, 1.2946253000", \ - "0.3164575000, 0.3269614000, 0.3490047000, 0.3940969000, 0.4927541000, 0.7368272000, 1.3697127000", \ - "0.4071747000, 0.4195484000, 0.4450411000, 0.4944751000, 0.5963810000, 0.8408385000, 1.4724846000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0686527000, 0.0758281000, 0.0905232000, 0.1219073000, 0.1914591000, 0.3565445000, 0.7866747000", \ - "0.0676483000, 0.0759727000, 0.0905919000, 0.1209970000, 0.1891139000, 0.3552455000, 0.7885047000", \ - "0.0691611000, 0.0759160000, 0.0907322000, 0.1218594000, 0.1913357000, 0.3565800000, 0.7868282000", \ - "0.0689290000, 0.0759682000, 0.0904001000, 0.1209942000, 0.1895553000, 0.3555945000, 0.7884906000", \ - "0.0684204000, 0.0750862000, 0.0908299000, 0.1217172000, 0.1911000000, 0.3564938000, 0.7868560000", \ - "0.0683062000, 0.0748076000, 0.0897114000, 0.1227171000, 0.1912118000, 0.3565469000, 0.7871152000", \ - "0.0797135000, 0.0860904000, 0.1015315000, 0.1331974000, 0.2000329000, 0.3627101000, 0.7905140000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0333627000, 0.0415996000, 0.0611515000, 0.1093269000, 0.2368543000, 0.5827621000, 1.5014476000", \ - "0.0333041000, 0.0417158000, 0.0612216000, 0.1093494000, 0.2367016000, 0.5829626000, 1.4980898000", \ - "0.0332479000, 0.0414889000, 0.0612421000, 0.1095098000, 0.2368806000, 0.5834287000, 1.5015308000", \ - "0.0334680000, 0.0415266000, 0.0612093000, 0.1092771000, 0.2368796000, 0.5824927000, 1.5010080000", \ - "0.0338649000, 0.0420552000, 0.0616427000, 0.1099685000, 0.2366199000, 0.5837477000, 1.5002004000", \ - "0.0373041000, 0.0459607000, 0.0657140000, 0.1132670000, 0.2387181000, 0.5839980000, 1.4995973000", \ - "0.0459192000, 0.0550010000, 0.0765411000, 0.1225740000, 0.2441715000, 0.5851983000, 1.4943221000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.4441279000, 0.4577177000, 0.4847449000, 0.5346096000, 0.6237669000, 0.7930026000, 1.1596397000", \ - "0.4484306000, 0.4622151000, 0.4895741000, 0.5393376000, 0.6284803000, 0.7977683000, 1.1644072000", \ - "0.4618141000, 0.4754250000, 0.5024666000, 0.5523481000, 0.6414521000, 0.8107691000, 1.1771730000", \ - "0.4885655000, 0.5019040000, 0.5292891000, 0.5793896000, 0.6682208000, 0.8376821000, 1.2041564000", \ - "0.5449684000, 0.5588440000, 0.5859488000, 0.6358227000, 0.7248915000, 0.8943954000, 1.2606740000", \ - "0.6745370000, 0.6880530000, 0.7153234000, 0.7651172000, 0.8540105000, 1.0233504000, 1.3903850000", \ - "0.9284050000, 0.9433000000, 0.9719904000, 1.0252198000, 1.1183483000, 1.2916838000, 1.6599315000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1807053000, 0.1905545000, 0.2118679000, 0.2564059000, 0.3547463000, 0.5979023000, 1.2309885000", \ - "0.1854525000, 0.1953950000, 0.2167591000, 0.2611690000, 0.3597520000, 0.6029172000, 1.2346402000", \ - "0.1952207000, 0.2051606000, 0.2265251000, 0.2709329000, 0.3695173000, 0.6126866000, 1.2442665000", \ - "0.2157056000, 0.2256286000, 0.2469325000, 0.2914495000, 0.3897856000, 0.6329385000, 1.2660728000", \ - "0.2595558000, 0.2695308000, 0.2909115000, 0.3354103000, 0.4339718000, 0.6778857000, 1.3110454000", \ - "0.3342261000, 0.3449455000, 0.3676130000, 0.4137743000, 0.5134028000, 0.7578024000, 1.3929506000", \ - "0.4356476000, 0.4483710000, 0.4744677000, 0.5249338000, 0.6282792000, 0.8730068000, 1.5043868000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0683000000, 0.0753742000, 0.0902898000, 0.1213173000, 0.1917310000, 0.3568467000, 0.7869299000", \ - "0.0698022000, 0.0764355000, 0.0910260000, 0.1228445000, 0.1912922000, 0.3570257000, 0.7884525000", \ - "0.0685880000, 0.0753679000, 0.0906310000, 0.1215586000, 0.1907502000, 0.3563775000, 0.7902193000", \ - "0.0686185000, 0.0758598000, 0.0910067000, 0.1221308000, 0.1899191000, 0.3562769000, 0.7889351000", \ - "0.0691618000, 0.0761955000, 0.0914916000, 0.1218013000, 0.1897701000, 0.3553661000, 0.7885597000", \ - "0.0682056000, 0.0751728000, 0.0902034000, 0.1218765000, 0.1907967000, 0.3562084000, 0.7884367000", \ - "0.0790607000, 0.0860688000, 0.1033034000, 0.1326945000, 0.2026071000, 0.3623398000, 0.7922393000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0345376000, 0.0431686000, 0.0631602000, 0.1114520000, 0.2384579000, 0.5831274000, 1.5012145000", \ - "0.0346409000, 0.0430684000, 0.0630910000, 0.1116274000, 0.2380471000, 0.5819913000, 1.4983518000", \ - "0.0346268000, 0.0430826000, 0.0630922000, 0.1116282000, 0.2380496000, 0.5819793000, 1.4986539000", \ - "0.0346351000, 0.0431680000, 0.0631700000, 0.1114892000, 0.2384701000, 0.5831723000, 1.5018320000", \ - "0.0349520000, 0.0436290000, 0.0635214000, 0.1115611000, 0.2384915000, 0.5836806000, 1.5021601000", \ - "0.0382260000, 0.0472277000, 0.0674240000, 0.1153490000, 0.2404825000, 0.5828560000, 1.5026057000", \ - "0.0469614000, 0.0566771000, 0.0778820000, 0.1247582000, 0.2463703000, 0.5857106000, 1.4984626000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.4315596000, 0.4442849000, 0.4712651000, 0.5201995000, 0.6080528000, 0.7758702000, 1.1408459000", \ - "0.4362156000, 0.4495936000, 0.4764460000, 0.5254579000, 0.6131946000, 0.7810060000, 1.1456394000", \ - "0.4496539000, 0.4625058000, 0.4893282000, 0.5381794000, 0.6260027000, 0.7938501000, 1.1584684000", \ - "0.4766469000, 0.4900708000, 0.5168944000, 0.5659196000, 0.6537303000, 0.8213926000, 1.1865233000", \ - "0.5343626000, 0.5479032000, 0.5745044000, 0.6235825000, 0.7113698000, 0.8790338000, 1.2440712000", \ - "0.6649902000, 0.6782878000, 0.7050741000, 0.7537496000, 0.8414812000, 1.0093524000, 1.3743543000", \ - "0.9188307000, 0.9329801000, 0.9621701000, 1.0142163000, 1.1061811000, 1.2780577000, 1.6449081000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1758945000, 0.1858125000, 0.2071320000, 0.2514927000, 0.3493573000, 0.5920405000, 1.2284394000", \ - "0.1806884000, 0.1906743000, 0.2120599000, 0.2562686000, 0.3544131000, 0.5972955000, 1.2309050000", \ - "0.1903733000, 0.2003084000, 0.2216123000, 0.2659484000, 0.3638719000, 0.6067382000, 1.2418001000", \ - "0.2103527000, 0.2203896000, 0.2416987000, 0.2858887000, 0.3840649000, 0.6275623000, 1.2592369000", \ - "0.2538819000, 0.2640388000, 0.2854577000, 0.3297626000, 0.4276097000, 0.6706322000, 1.3043715000", \ - "0.3292198000, 0.3401116000, 0.3627717000, 0.4088560000, 0.5081598000, 0.7524021000, 1.3851444000", \ - "0.4318023000, 0.4446970000, 0.4709208000, 0.5215545000, 0.6246172000, 0.8687389000, 1.5013003000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0664589000, 0.0746101000, 0.0891018000, 0.1198992000, 0.1897462000, 0.3527141000, 0.7876010000", \ - "0.0667053000, 0.0734567000, 0.0880328000, 0.1201542000, 0.1883916000, 0.3532286000, 0.7874136000", \ - "0.0666622000, 0.0732489000, 0.0878593000, 0.1211913000, 0.1883020000, 0.3528933000, 0.7861682000", \ - "0.0668303000, 0.0736016000, 0.0880574000, 0.1202914000, 0.1878006000, 0.3542549000, 0.7865759000", \ - "0.0666249000, 0.0742768000, 0.0883695000, 0.1206483000, 0.1901270000, 0.3533022000, 0.7883879000", \ - "0.0663560000, 0.0733032000, 0.0880401000, 0.1213686000, 0.1896201000, 0.3528174000, 0.7873456000", \ - "0.0779261000, 0.0849636000, 0.0994551000, 0.1305360000, 0.1996427000, 0.3593060000, 0.7909534000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0347354000, 0.0433435000, 0.0630671000, 0.1109276000, 0.2379892000, 0.5838274000, 1.5040769000", \ - "0.0348356000, 0.0430809000, 0.0629923000, 0.1111530000, 0.2374490000, 0.5824596000, 1.5047310000", \ - "0.0348291000, 0.0433477000, 0.0631190000, 0.1110833000, 0.2380197000, 0.5832977000, 1.5049728000", \ - "0.0346212000, 0.0431807000, 0.0629839000, 0.1110856000, 0.2377177000, 0.5822470000, 1.5026596000", \ - "0.0352159000, 0.0436964000, 0.0636460000, 0.1112727000, 0.2381087000, 0.5839047000, 1.5010617000", \ - "0.0385060000, 0.0475582000, 0.0675126000, 0.1151018000, 0.2400507000, 0.5841683000, 1.4998357000", \ - "0.0475587000, 0.0573515000, 0.0778753000, 0.1246584000, 0.2457695000, 0.5840483000, 1.4997625000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.4196395000, 0.4326556000, 0.4593695000, 0.5076592000, 0.5943556000, 0.7605500000, 1.1240534000", \ - "0.4249230000, 0.4377723000, 0.4643257000, 0.5127286000, 0.5995044000, 0.7656636000, 1.1292587000", \ - "0.4372444000, 0.4500643000, 0.4766107000, 0.5250479000, 0.6118127000, 0.7779705000, 1.1413597000", \ - "0.4630592000, 0.4759551000, 0.5025281000, 0.5508147000, 0.6375099000, 0.8038402000, 1.1671797000", \ - "0.5209315000, 0.5341198000, 0.5603182000, 0.6086565000, 0.6956707000, 0.8617386000, 1.2253643000", \ - "0.6557294000, 0.6690531000, 0.6951908000, 0.7435050000, 0.8302771000, 0.9965663000, 1.3602738000", \ - "0.9177614000, 0.9317430000, 0.9605947000, 1.0122592000, 1.1032798000, 1.2737557000, 1.6390288000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1689931000, 0.1788766000, 0.2000838000, 0.2443059000, 0.3421240000, 0.5851397000, 1.2177844000", \ - "0.1738278000, 0.1837813000, 0.2049828000, 0.2491105000, 0.3471149000, 0.5905265000, 1.2235724000", \ - "0.1838195000, 0.1936652000, 0.2148898000, 0.2591201000, 0.3568762000, 0.5996608000, 1.2327174000", \ - "0.2048264000, 0.2146996000, 0.2359048000, 0.2800903000, 0.3778830000, 0.6206688000, 1.2536739000", \ - "0.2494966000, 0.2595124000, 0.2808485000, 0.3251329000, 0.4230140000, 0.6660962000, 1.2984210000", \ - "0.3245688000, 0.3353944000, 0.3581133000, 0.4041353000, 0.5033234000, 0.7476605000, 1.3799850000", \ - "0.4252081000, 0.4379898000, 0.4645038000, 0.5152614000, 0.6183417000, 0.8620185000, 1.4943613000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0647652000, 0.0720417000, 0.0865763000, 0.1181937000, 0.1879459000, 0.3503676000, 0.7865933000", \ - "0.0652340000, 0.0719769000, 0.0865186000, 0.1183718000, 0.1878212000, 0.3508377000, 0.7856744000", \ - "0.0652397000, 0.0719847000, 0.0865129000, 0.1182916000, 0.1877971000, 0.3508637000, 0.7862883000", \ - "0.0651628000, 0.0719768000, 0.0865314000, 0.1176277000, 0.1873352000, 0.3497805000, 0.7850314000", \ - "0.0650765000, 0.0719932000, 0.0875627000, 0.1179531000, 0.1868192000, 0.3510106000, 0.7851105000", \ - "0.0648110000, 0.0721182000, 0.0873382000, 0.1182173000, 0.1882311000, 0.3511564000, 0.7844724000", \ - "0.0767310000, 0.0853742000, 0.0993372000, 0.1298631000, 0.1981587000, 0.3565939000, 0.7887275000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0343914000, 0.0429472000, 0.0626487000, 0.1108631000, 0.2372544000, 0.5825633000, 1.5013099000", \ - "0.0342969000, 0.0429686000, 0.0627612000, 0.1105194000, 0.2377648000, 0.5840094000, 1.5015210000", \ - "0.0344068000, 0.0429884000, 0.0626391000, 0.1107932000, 0.2373799000, 0.5836706000, 1.5035042000", \ - "0.0345251000, 0.0430282000, 0.0628025000, 0.1108079000, 0.2377270000, 0.5831789000, 1.5003453000", \ - "0.0349385000, 0.0433605000, 0.0632847000, 0.1111824000, 0.2375996000, 0.5828576000, 1.4988415000", \ - "0.0384681000, 0.0476592000, 0.0675429000, 0.1150664000, 0.2394695000, 0.5842169000, 1.4988883000", \ - "0.0480141000, 0.0576628000, 0.0781082000, 0.1250077000, 0.2454117000, 0.5844775000, 1.4996366000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.3958371000, 0.4094101000, 0.4360752000, 0.4849924000, 0.5728234000, 0.7406895000, 1.1055863000", \ - "0.3995951000, 0.4131626000, 0.4396093000, 0.4886365000, 0.5765531000, 0.7441705000, 1.1093588000", \ - "0.4089652000, 0.4224062000, 0.4490457000, 0.4981015000, 0.5859456000, 0.7535997000, 1.1187380000", \ - "0.4346916000, 0.4481718000, 0.4747230000, 0.5237860000, 0.6116366000, 0.7793026000, 1.1444585000", \ - "0.4987379000, 0.5121135000, 0.5389833000, 0.5879665000, 0.6756317000, 0.8433876000, 1.2084224000", \ - "0.6531096000, 0.6664118000, 0.6932774000, 0.7419226000, 0.8296859000, 0.9976664000, 1.3624566000", \ - "0.9501938000, 0.9648938000, 0.9941219000, 1.0472606000, 1.1403357000, 1.3125817000, 1.6796489000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1604632000, 0.1706095000, 0.1923996000, 0.2377651000, 0.3378545000, 0.5816930000, 1.2159075000", \ - "0.1649863000, 0.1751325000, 0.1969219000, 0.2422794000, 0.3423774000, 0.5862259000, 1.2201937000", \ - "0.1756993000, 0.1858478000, 0.2076385000, 0.2529936000, 0.3530966000, 0.5969555000, 1.2315912000", \ - "0.2000939000, 0.2101868000, 0.2320019000, 0.2773038000, 0.3773232000, 0.6211081000, 1.2540593000", \ - "0.2520272000, 0.2623116000, 0.2842562000, 0.3296612000, 0.4293397000, 0.6731952000, 1.3086149000", \ - "0.3344233000, 0.3461865000, 0.3705027000, 0.4185086000, 0.5194348000, 0.7636817000, 1.3988060000", \ - "0.4359068000, 0.4514475000, 0.4816067000, 0.5366694000, 0.6422838000, 0.8865993000, 1.5191374000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0657789000, 0.0737810000, 0.0879502000, 0.1210674000, 0.1875223000, 0.3523858000, 0.7872534000", \ - "0.0658392000, 0.0729490000, 0.0882036000, 0.1194633000, 0.1890221000, 0.3542916000, 0.7857905000", \ - "0.0657492000, 0.0730285000, 0.0887254000, 0.1195152000, 0.1899429000, 0.3537014000, 0.7881627000", \ - "0.0658256000, 0.0730052000, 0.0886133000, 0.1195331000, 0.1899140000, 0.3537492000, 0.7880364000", \ - "0.0659801000, 0.0729300000, 0.0878941000, 0.1195566000, 0.1886496000, 0.3532508000, 0.7889424000", \ - "0.0664246000, 0.0733058000, 0.0880516000, 0.1215955000, 0.1903486000, 0.3533133000, 0.7867186000", \ - "0.0824733000, 0.0892340000, 0.1049879000, 0.1347232000, 0.2010680000, 0.3613805000, 0.7895334000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0353984000, 0.0438906000, 0.0642482000, 0.1133057000, 0.2400030000, 0.5828268000, 1.5025756000", \ - "0.0353979000, 0.0438920000, 0.0642452000, 0.1133223000, 0.2401008000, 0.5831021000, 1.5023890000", \ - "0.0354640000, 0.0438567000, 0.0641820000, 0.1133315000, 0.2400296000, 0.5824499000, 1.5026195000", \ - "0.0354233000, 0.0440604000, 0.0643828000, 0.1133390000, 0.2403675000, 0.5839590000, 1.4968337000", \ - "0.0365055000, 0.0450044000, 0.0651434000, 0.1136547000, 0.2400913000, 0.5831506000, 1.5023750000", \ - "0.0439228000, 0.0527258000, 0.0725669000, 0.1193216000, 0.2425783000, 0.5844917000, 1.4999829000", \ - "0.0588665000, 0.0693244000, 0.0899239000, 0.1346046000, 0.2504323000, 0.5866183000, 1.4977554000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.4865461000, 0.5001505000, 0.5271107000, 0.5769263000, 0.6660651000, 0.8352037000, 1.2018134000", \ - "0.4916957000, 0.5053744000, 0.5324506000, 0.5822351000, 0.6711166000, 0.8403466000, 1.2069237000", \ - "0.5020636000, 0.5156164000, 0.5422985000, 0.5924278000, 0.6813676000, 0.8505720000, 1.2172048000", \ - "0.5218871000, 0.5356396000, 0.5627938000, 0.6125105000, 0.7015346000, 0.8709979000, 1.2370857000", \ - "0.5538349000, 0.5673498000, 0.5946816000, 0.6443141000, 0.7335351000, 0.9026855000, 1.2692852000", \ - "0.5960044000, 0.6099439000, 0.6374491000, 0.6874187000, 0.7767204000, 0.9461960000, 1.3128328000", \ - "0.6408872000, 0.6546449000, 0.6816718000, 0.7314915000, 0.8207247000, 0.9906438000, 1.3587301000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2823122000, 0.2919767000, 0.3127105000, 0.3561656000, 0.4534755000, 0.6968278000, 1.3294064000", \ - "0.2863027000, 0.2959239000, 0.3166281000, 0.3600597000, 0.4575035000, 0.7003334000, 1.3325931000", \ - "0.2979529000, 0.3075912000, 0.3282945000, 0.3717386000, 0.4691381000, 0.7119557000, 1.3436120000", \ - "0.3283357000, 0.3380144000, 0.3587315000, 0.4021147000, 0.4995962000, 0.7432046000, 1.3756273000", \ - "0.3979761000, 0.4076001000, 0.4283600000, 0.4716926000, 0.5692087000, 0.8120242000, 1.4444698000", \ - "0.5235851000, 0.5333481000, 0.5541350000, 0.5978993000, 0.6953891000, 0.9382792000, 1.5720993000", \ - "0.7182879000, 0.7282474000, 0.7495004000, 0.7934983000, 0.8914630000, 1.1351206000, 1.7662728000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0684248000, 0.0752609000, 0.0919906000, 0.1225727000, 0.1918732000, 0.3570325000, 0.7872833000", \ - "0.0685202000, 0.0754894000, 0.0903164000, 0.1221514000, 0.1917282000, 0.3567474000, 0.7885984000", \ - "0.0688945000, 0.0757329000, 0.0923129000, 0.1227386000, 0.1914405000, 0.3569594000, 0.7879193000", \ - "0.0692059000, 0.0754944000, 0.0903043000, 0.1238188000, 0.1924893000, 0.3558438000, 0.7883343000", \ - "0.0687361000, 0.0755810000, 0.0906857000, 0.1218973000, 0.1914763000, 0.3569834000, 0.7872140000", \ - "0.0690950000, 0.0768894000, 0.0906607000, 0.1221956000, 0.1904572000, 0.3571835000, 0.7885546000", \ - "0.0681626000, 0.0747368000, 0.0903517000, 0.1217682000, 0.1926409000, 0.3575544000, 0.7913152000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0338507000, 0.0419169000, 0.0615890000, 0.1096440000, 0.2366608000, 0.5838581000, 1.4985930000", \ - "0.0337838000, 0.0420453000, 0.0616540000, 0.1097216000, 0.2364070000, 0.5818960000, 1.5005983000", \ - "0.0337435000, 0.0420422000, 0.0616395000, 0.1096927000, 0.2365874000, 0.5824417000, 1.4997218000", \ - "0.0338340000, 0.0418752000, 0.0615789000, 0.1094973000, 0.2369961000, 0.5829487000, 1.5015997000", \ - "0.0337824000, 0.0420525000, 0.0615465000, 0.1096893000, 0.2368395000, 0.5821465000, 1.5008852000", \ - "0.0342809000, 0.0422428000, 0.0619548000, 0.1101863000, 0.2374625000, 0.5835710000, 1.4998959000", \ - "0.0355430000, 0.0437193000, 0.0632813000, 0.1111189000, 0.2374714000, 0.5826256000, 1.4990676000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1791548000, 0.1909618000, 0.2154324000, 0.2618498000, 0.3473030000, 0.5138311000, 0.8787119000", \ - "0.1830618000, 0.1950304000, 0.2194349000, 0.2658654000, 0.3512945000, 0.5177974000, 0.8827449000", \ - "0.1933579000, 0.2051038000, 0.2294113000, 0.2755884000, 0.3610884000, 0.5276312000, 0.8923312000", \ - "0.2194800000, 0.2310547000, 0.2550583000, 0.3008654000, 0.3861172000, 0.5525163000, 0.9171134000", \ - "0.2848818000, 0.2961472000, 0.3193166000, 0.3642200000, 0.4484859000, 0.6147270000, 0.9796387000", \ - "0.4175857000, 0.4300036000, 0.4549809000, 0.5009245000, 0.5850605000, 0.7509058000, 1.1158474000", \ - "0.6147556000, 0.6301250000, 0.6622588000, 0.7182940000, 0.8113105000, 0.9808802000, 1.3496907000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0959095000, 0.1058636000, 0.1271737000, 0.1714488000, 0.2691191000, 0.5122254000, 1.1427131000", \ - "0.1002359000, 0.1101911000, 0.1314906000, 0.1757831000, 0.2734101000, 0.5163909000, 1.1517717000", \ - "0.1106549000, 0.1205669000, 0.1418596000, 0.1859483000, 0.2838275000, 0.5262674000, 1.1592233000", \ - "0.1351932000, 0.1449786000, 0.1658974000, 0.2099008000, 0.3077820000, 0.5503760000, 1.1822634000", \ - "0.1787855000, 0.1886428000, 0.2098948000, 0.2543655000, 0.3526982000, 0.5955232000, 1.2298028000", \ - "0.2323743000, 0.2442763000, 0.2681494000, 0.3138242000, 0.4129453000, 0.6572748000, 1.2963437000", \ - "0.2775380000, 0.2931521000, 0.3237733000, 0.3773182000, 0.4789941000, 0.7233038000, 1.3557792000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0489436000, 0.0570949000, 0.0740037000, 0.1089349000, 0.1840244000, 0.3510135000, 0.7881422000", \ - "0.0483578000, 0.0565210000, 0.0737664000, 0.1088214000, 0.1840289000, 0.3511878000, 0.7881884000", \ - "0.0483899000, 0.0562038000, 0.0731487000, 0.1094829000, 0.1815178000, 0.3515370000, 0.7862632000", \ - "0.0473538000, 0.0551802000, 0.0721690000, 0.1087279000, 0.1809863000, 0.3515039000, 0.7858219000", \ - "0.0448117000, 0.0526722000, 0.0708943000, 0.1057795000, 0.1810003000, 0.3505786000, 0.7855215000", \ - "0.0567828000, 0.0648005000, 0.0793768000, 0.1105508000, 0.1823280000, 0.3511979000, 0.7861807000", \ - "0.0797720000, 0.0888252000, 0.1068042000, 0.1372979000, 0.2013993000, 0.3612232000, 0.7915851000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0337208000, 0.0419950000, 0.0619058000, 0.1101947000, 0.2370988000, 0.5838012000, 1.4981792000", \ - "0.0336513000, 0.0420073000, 0.0618775000, 0.1101597000, 0.2368426000, 0.5833266000, 1.5035581000", \ - "0.0334577000, 0.0419661000, 0.0618149000, 0.1102604000, 0.2370076000, 0.5816216000, 1.5054208000", \ - "0.0331794000, 0.0417040000, 0.0616713000, 0.1101501000, 0.2372490000, 0.5815270000, 1.5053511000", \ - "0.0363796000, 0.0443906000, 0.0638070000, 0.1116608000, 0.2374916000, 0.5816427000, 1.5053139000", \ - "0.0471861000, 0.0545160000, 0.0718582000, 0.1163636000, 0.2409998000, 0.5843618000, 1.4987116000", \ - "0.0637612000, 0.0737855000, 0.0926755000, 0.1327621000, 0.2467317000, 0.5860097000, 1.4962299000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2125450000, 0.2259471000, 0.2523761000, 0.3006133000, 0.3874697000, 0.5540086000, 0.9180112000", \ - "0.2187354000, 0.2317623000, 0.2581070000, 0.3065567000, 0.3933205000, 0.5598673000, 0.9237683000", \ - "0.2300898000, 0.2435827000, 0.2701180000, 0.3184057000, 0.4051548000, 0.5718002000, 0.9357590000", \ - "0.2519512000, 0.2650370000, 0.2912780000, 0.3395553000, 0.4262097000, 0.5926850000, 0.9568287000", \ - "0.3003957000, 0.3129343000, 0.3381451000, 0.3853390000, 0.4714269000, 0.6374814000, 1.0014122000", \ - "0.3599424000, 0.3715493000, 0.3956178000, 0.4413145000, 0.5251689000, 0.6897186000, 1.0531432000", \ - "0.4016203000, 0.4130937000, 0.4375394000, 0.4835415000, 0.5682634000, 0.7333210000, 1.0950053000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1594995000, 0.1693261000, 0.1903884000, 0.2346316000, 0.3326049000, 0.5753956000, 1.2099327000", \ - "0.1640958000, 0.1738946000, 0.1950135000, 0.2392958000, 0.3373897000, 0.5805421000, 1.2141810000", \ - "0.1769023000, 0.1866645000, 0.2077704000, 0.2520024000, 0.3503081000, 0.5939091000, 1.2283039000", \ - "0.2084224000, 0.2181985000, 0.2393121000, 0.2835626000, 0.3818597000, 0.6254353000, 1.2599868000", \ - "0.2737858000, 0.2835610000, 0.3046240000, 0.3489291000, 0.4469695000, 0.6900184000, 1.3266864000", \ - "0.3759724000, 0.3856556000, 0.4065897000, 0.4508063000, 0.5483403000, 0.7909034000, 1.4254189000", \ - "0.5282612000, 0.5380268000, 0.5590030000, 0.6033649000, 0.7019227000, 0.9449159000, 1.5750500000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0626184000, 0.0695871000, 0.0845249000, 0.1179546000, 0.1851410000, 0.3508027000, 0.7860194000", \ - "0.0623004000, 0.0693777000, 0.0850373000, 0.1164985000, 0.1860783000, 0.3513930000, 0.7874647000", \ - "0.0624822000, 0.0695107000, 0.0858674000, 0.1173017000, 0.1849718000, 0.3506375000, 0.7859945000", \ - "0.0609288000, 0.0684303000, 0.0838398000, 0.1157573000, 0.1868647000, 0.3520924000, 0.7847774000", \ - "0.0543830000, 0.0622942000, 0.0788797000, 0.1124649000, 0.1832280000, 0.3512525000, 0.7853139000", \ - "0.0509183000, 0.0588722000, 0.0747845000, 0.1093883000, 0.1794555000, 0.3493246000, 0.7845466000", \ - "0.0509563000, 0.0584370000, 0.0750795000, 0.1099631000, 0.1819381000, 0.3470438000, 0.7786902000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0337437000, 0.0425192000, 0.0625667000, 0.1110131000, 0.2380644000, 0.5831794000, 1.5046555000", \ - "0.0340228000, 0.0424317000, 0.0625414000, 0.1111769000, 0.2375639000, 0.5826065000, 1.5022611000", \ - "0.0339614000, 0.0424060000, 0.0624543000, 0.1110130000, 0.2380006000, 0.5835809000, 1.5001740000", \ - "0.0339408000, 0.0423895000, 0.0624127000, 0.1109859000, 0.2379730000, 0.5835219000, 1.5020198000", \ - "0.0338170000, 0.0423904000, 0.0624641000, 0.1109290000, 0.2375184000, 0.5830311000, 1.5063562000", \ - "0.0337646000, 0.0423243000, 0.0623708000, 0.1111456000, 0.2369799000, 0.5835197000, 1.5000368000", \ - "0.0350091000, 0.0430972000, 0.0630584000, 0.1119757000, 0.2385319000, 0.5814808000, 1.4945579000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux4_2") { - leakage_power () { - value : 0.0065112000; - when : "!A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0052504000; - when : "!A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0075643000; - when : "!A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0063036000; - when : "!A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0069087000; - when : "!A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0056480000; - when : "!A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0065752000; - when : "!A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0081139000; - when : "!A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0054602000; - when : "!A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0069988000; - when : "!A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0079600000; - when : "!A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0066992000; - when : "!A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0052203000; - when : "!A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0067590000; - when : "!A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0063420000; - when : "!A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0078806000; - when : "!A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0068980000; - when : "!A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0056373000; - when : "!A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0101045000; - when : "!A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0060444000; - when : "!A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0072956000; - when : "!A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0060349000; - when : "!A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0065866000; - when : "!A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0053259000; - when : "!A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0058470000; - when : "!A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0073857000; - when : "!A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0105002000; - when : "!A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0064400000; - when : "!A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0056072000; - when : "!A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0071458000; - when : "!A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0063534000; - when : "!A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0050926000; - when : "!A0&A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0080367000; - when : "A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0039766000; - when : "A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0079628000; - when : "A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0067021000; - when : "A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0084343000; - when : "A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0043741000; - when : "A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0069737000; - when : "A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0085124000; - when : "A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0044569000; - when : "A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0031962000; - when : "A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0083585000; - when : "A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0070977000; - when : "A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0042171000; - when : "A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0029563000; - when : "A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0067404000; - when : "A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0082791000; - when : "A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0078633000; - when : "A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0038032000; - when : "A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0098838000; - when : "A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0058237000; - when : "A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0082609000; - when : "A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0042008000; - when : "A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0063659000; - when : "A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0051052000; - when : "A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0042836000; - when : "A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0030228000; - when : "A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0102795000; - when : "A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0062193000; - when : "A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0040437000; - when : "A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0027830000; - when : "A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0061327000; - when : "A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0048719000; - when : "A0&A1&A2&A3&S0&!S1"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__mux4"; - cell_leakage_power : 0.0063705090; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0018020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0096454000, 0.0095878000, 0.0094552000, 0.0094643000, 0.0094852000, 0.0095333000, 0.0096443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027816000, 0.0027271000, 0.0026014000, 0.0026198000, 0.0026623000, 0.0027601000, 0.0029855000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018880000; - } - pin ("A1") { - capacitance : 0.0017890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033125000, 0.0033090000, 0.0033009000, 0.0033039000, 0.0033109000, 0.0033270000, 0.0033641000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003205600, -0.003220300, -0.003254200, -0.003256600, -0.003262100, -0.003274900, -0.003304300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018750000; - } - pin ("A2") { - capacitance : 0.0017380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087109000, 0.0086571000, 0.0085333000, 0.0085442000, 0.0085692000, 0.0086270000, 0.0087602000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047573000, 0.0047038000, 0.0045806000, 0.0046008000, 0.0046472000, 0.0047541000, 0.0050007000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018090000; - } - pin ("A3") { - capacitance : 0.0017510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029117000, 0.0029114000, 0.0029107000, 0.0029086000, 0.0029038000, 0.0028926000, 0.0028669000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002823000, -0.002837300, -0.002870200, -0.002871100, -0.002873200, -0.002877900, -0.002888700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018280000; - } - pin ("S0") { - capacitance : 0.0054550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0195877000, 0.0192944000, 0.0186182000, 0.0186790000, 0.0188192000, 0.0191424000, 0.0198872000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0018888000, 0.0016645000, 0.0011477000, 0.0011759000, 0.0012409000, 0.0013907000, 0.0017360000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0057660000; - } - pin ("S1") { - capacitance : 0.0031740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0030690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103230000, 0.0101985000, 0.0099114000, 0.0099829000, 0.0101477000, 0.0105277000, 0.0114035000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000848900, -0.000978700, -0.001277900, -0.001207600, -0.001045700, -0.000672500, 0.0001878000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0032790000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S0&!S1) | (A1&S0&!S1) | (A2&!S0&S1) | (A3&S0&S1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0102547000, 0.0084013000, 0.0039720000, -0.007980900, -0.043969600, -0.152627500, -0.472419300", \ - "0.0102007000, 0.0083934000, 0.0040170000, -0.008135100, -0.043973000, -0.152635400, -0.472417100", \ - "0.0103454000, 0.0085608000, 0.0040790000, -0.007937800, -0.043951600, -0.152602600, -0.472370900", \ - "0.0101550000, 0.0083590000, 0.0039101000, -0.008130700, -0.044084700, -0.152739100, -0.472497400", \ - "0.0099267000, 0.0081297000, 0.0037179000, -0.008402400, -0.044305700, -0.152908100, -0.472690600", \ - "0.0099611000, 0.0081735000, 0.0036951000, -0.008388700, -0.044440200, -0.153037300, -0.472754600", \ - "0.0129805000, 0.0110466000, 0.0058655000, -0.007889600, -0.044447700, -0.153018900, -0.472679800"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0167303000, 0.0183573000, 0.0230609000, 0.0367353000, 0.0745168000, 0.1828451000, 0.4994583000", \ - "0.0167223000, 0.0183517000, 0.0231160000, 0.0367809000, 0.0745069000, 0.1828177000, 0.5014930000", \ - "0.0167257000, 0.0182821000, 0.0231512000, 0.0368232000, 0.0745410000, 0.1828401000, 0.5015070000", \ - "0.0165952000, 0.0181756000, 0.0230230000, 0.0367029000, 0.0744330000, 0.1828074000, 0.5014843000", \ - "0.0165248000, 0.0180772000, 0.0228687000, 0.0365745000, 0.0743086000, 0.1827991000, 0.4993726000", \ - "0.0169607000, 0.0184357000, 0.0227554000, 0.0363282000, 0.0740170000, 0.1826067000, 0.4986980000", \ - "0.0180980000, 0.0196442000, 0.0240431000, 0.0370944000, 0.0747195000, 0.1833356000, 0.4979273000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0184020000, 0.0166174000, 0.0122281000, 0.0003965000, -0.035205800, -0.143362600, -0.462794700", \ - "0.0183219000, 0.0165413000, 0.0121479000, 0.0003256000, -0.035284600, -0.143441800, -0.462860900", \ - "0.0182898000, 0.0164957000, 0.0121405000, 0.0002640000, -0.035357300, -0.143533000, -0.462998100", \ - "0.0181265000, 0.0163450000, 0.0118854000, 6.970000e-05, -0.035529600, -0.143654800, -0.463092800", \ - "0.0179252000, 0.0161451000, 0.0117606000, -0.000121600, -0.035728700, -0.143835100, -0.463294800", \ - "0.0180475000, 0.0162582000, 0.0117695000, -0.000135400, -0.035827100, -0.143995600, -0.463399600", \ - "0.0221398000, 0.0201913000, 0.0151008000, 0.0013949000, -0.035817700, -0.143915100, -0.463298400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0203918000, 0.0220188000, 0.0266936000, 0.0404025000, 0.0785325000, 0.1876773000, 0.5047704000", \ - "0.0202979000, 0.0219241000, 0.0266181000, 0.0403254000, 0.0784479000, 0.1875308000, 0.5069006000", \ - "0.0202275000, 0.0218539000, 0.0265301000, 0.0402500000, 0.0783689000, 0.1875105000, 0.5047512000", \ - "0.0201488000, 0.0217547000, 0.0264387000, 0.0401564000, 0.0782502000, 0.1873770000, 0.5045855000", \ - "0.0200478000, 0.0216814000, 0.0264431000, 0.0401726000, 0.0781868000, 0.1872255000, 0.5065099000", \ - "0.0203266000, 0.0218296000, 0.0263003000, 0.0400357000, 0.0779461000, 0.1870290000, 0.5042901000", \ - "0.0219788000, 0.0234677000, 0.0279298000, 0.0410085000, 0.0786736000, 0.1874148000, 0.5035530000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0122333000, 0.0104157000, 0.0059519000, -0.005943100, -0.041573600, -0.149701000, -0.469141400", \ - "0.0121968000, 0.0104579000, 0.0060104000, -0.005927000, -0.041635200, -0.149724500, -0.469109800", \ - "0.0122688000, 0.0104701000, 0.0060120000, -0.005863600, -0.041516900, -0.149635800, -0.469043200", \ - "0.0122226000, 0.0104312000, 0.0060110000, -0.005990600, -0.041580100, -0.149722000, -0.469127500", \ - "0.0120858000, 0.0102868000, 0.0058289000, -0.006067900, -0.041774800, -0.149884800, -0.469258900", \ - "0.0121716000, 0.0103830000, 0.0058212000, -0.006114600, -0.041864600, -0.150011500, -0.469400200", \ - "0.0154517000, 0.0134945000, 0.0083261000, -0.005411300, -0.041852000, -0.150064900, -0.469418600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0141652000, 0.0157477000, 0.0206017000, 0.0343759000, 0.0724995000, 0.1816456000, 0.5008750000", \ - "0.0141452000, 0.0157269000, 0.0205149000, 0.0342602000, 0.0725057000, 0.1816770000, 0.4980771000", \ - "0.0142170000, 0.0158029000, 0.0205966000, 0.0343719000, 0.0724311000, 0.1817709000, 0.5008477000", \ - "0.0141326000, 0.0157670000, 0.0204613000, 0.0342135000, 0.0723641000, 0.1816341000, 0.4988989000", \ - "0.0140522000, 0.0156527000, 0.0204278000, 0.0342440000, 0.0723021000, 0.1815086000, 0.5005833000", \ - "0.0144820000, 0.0159714000, 0.0203088000, 0.0339532000, 0.0719514000, 0.1811297000, 0.4982949000", \ - "0.0156522000, 0.0171210000, 0.0215425000, 0.0347541000, 0.0723716000, 0.1815490000, 0.4958081000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0201106000, 0.0183211000, 0.0138945000, 0.0020698000, -0.033412500, -0.141441300, -0.460790900", \ - "0.0200569000, 0.0182702000, 0.0138234000, 0.0018893000, -0.033458700, -0.141483100, -0.460877400", \ - "0.0199721000, 0.0181847000, 0.0137449000, 0.0019722000, -0.033579600, -0.141558500, -0.460948700", \ - "0.0198953000, 0.0180989000, 0.0136681000, 0.0018839000, -0.033639600, -0.141640900, -0.461037100", \ - "0.0197517000, 0.0179581000, 0.0135542000, 0.0015569000, -0.033822500, -0.141802700, -0.461144300", \ - "0.0198611000, 0.0180645000, 0.0135456000, 0.0017375000, -0.033861000, -0.141879400, -0.461231200", \ - "0.0233739000, 0.0214194000, 0.0162281000, 0.0025601000, -0.033738100, -0.141779900, -0.461096200"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0193172000, 0.0209571000, 0.0256351000, 0.0393152000, 0.0774128000, 0.1865980000, 0.5039019000", \ - "0.0192500000, 0.0208451000, 0.0255752000, 0.0392658000, 0.0773737000, 0.1865079000, 0.5034614000", \ - "0.0192178000, 0.0208251000, 0.0254901000, 0.0391232000, 0.0772349000, 0.1864393000, 0.5036511000", \ - "0.0191072000, 0.0206972000, 0.0254289000, 0.0391212000, 0.0771351000, 0.1863815000, 0.5054869000", \ - "0.0191038000, 0.0206628000, 0.0254442000, 0.0390163000, 0.0770621000, 0.1862279000, 0.5030185000", \ - "0.0194789000, 0.0210074000, 0.0253765000, 0.0389066000, 0.0768190000, 0.1859553000, 0.5052111000", \ - "0.0207455000, 0.0222639000, 0.0266932000, 0.0398874000, 0.0774915000, 0.1867093000, 0.5047505000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0199940000, 0.0182060000, 0.0137425000, 0.0019307000, -0.033629300, -0.141816200, -0.461011700", \ - "0.0199390000, 0.0181591000, 0.0137406000, 0.0019023000, -0.033646900, -0.141766000, -0.461169300", \ - "0.0199773000, 0.0181834000, 0.0137926000, 0.0019662000, -0.033590000, -0.141729600, -0.461096300", \ - "0.0191589000, 0.0174063000, 0.0129660000, 0.0011452000, -0.034409900, -0.142538600, -0.461918000", \ - "0.0185734000, 0.0167933000, 0.0123800000, 0.0005754000, -0.035048300, -0.143141400, -0.462519400", \ - "0.0181609000, 0.0163871000, 0.0119757000, 0.0001862000, -0.035363100, -0.143438900, -0.462841200", \ - "0.0247401000, 0.0228669000, 0.0179727000, 0.0045974000, -0.033221600, -0.142497600, -0.461856200"); - } - related_pin : "S0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0281051000, 0.0297595000, 0.0345108000, 0.0481437000, 0.0858414000, 0.1946317000, 0.5132366000", \ - "0.0279772000, 0.0295608000, 0.0343495000, 0.0479738000, 0.0857791000, 0.1944678000, 0.5106128000", \ - "0.0282019000, 0.0297811000, 0.0346178000, 0.0482831000, 0.0859969000, 0.1944783000, 0.5132573000", \ - "0.0277580000, 0.0293372000, 0.0341037000, 0.0477851000, 0.0855035000, 0.1941360000, 0.5125878000", \ - "0.0271241000, 0.0286696000, 0.0334442000, 0.0470753000, 0.0848664000, 0.1935053000, 0.5100634000", \ - "0.0267141000, 0.0282737000, 0.0330464000, 0.0466630000, 0.0845349000, 0.1931637000, 0.5095133000", \ - "0.0277820000, 0.0293402000, 0.0338254000, 0.0469798000, 0.0848774000, 0.1932815000, 0.5113675000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0118414000, 0.0100605000, 0.0056639000, -0.006170700, -0.041576100, -0.149714900, -0.469211500", \ - "0.0118171000, 0.0100332000, 0.0056348000, -0.006129600, -0.041610200, -0.149747500, -0.469256200", \ - "0.0119755000, 0.0101875000, 0.0058109000, -0.005974400, -0.041426700, -0.149547300, -0.469061200", \ - "0.0118762000, 0.0100906000, 0.0056955000, -0.006003000, -0.041488500, -0.149651900, -0.469159600", \ - "0.0116637000, 0.0099300000, 0.0056427000, -0.006105200, -0.041529100, -0.149619800, -0.469087100", \ - "0.0124671000, 0.0106921000, 0.0060587000, -0.005747000, -0.041296100, -0.149397000, -0.468812900", \ - "0.0190292000, 0.0172406000, 0.0124113000, -0.000692000, -0.038377400, -0.148196400, -0.467691700"); - } - related_pin : "S1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0161761000, 0.0177861000, 0.0225699000, 0.0362673000, 0.0742928000, 0.1834596000, 0.5008831000", \ - "0.0160944000, 0.0177117000, 0.0224713000, 0.0361992000, 0.0741943000, 0.1833802000, 0.5002813000", \ - "0.0162151000, 0.0178176000, 0.0225971000, 0.0363139000, 0.0743408000, 0.1835158000, 0.5009714000", \ - "0.0161547000, 0.0177892000, 0.0225695000, 0.0362994000, 0.0742848000, 0.1834738000, 0.5025204000", \ - "0.0162864000, 0.0179269000, 0.0227379000, 0.0363816000, 0.0744407000, 0.1835410000, 0.5010431000", \ - "0.0164742000, 0.0181021000, 0.0229997000, 0.0369606000, 0.0747693000, 0.1840388000, 0.5013780000", \ - "0.0187676000, 0.0203344000, 0.0248595000, 0.0380396000, 0.0756026000, 0.1854059000, 0.5007813000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5034400000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4064566000, 0.4168633000, 0.4403922000, 0.4858796000, 0.5686201000, 0.7259255000, 1.0727361000", \ - "0.4118063000, 0.4219450000, 0.4455451000, 0.4910618000, 0.5741012000, 0.7317501000, 1.0781452000", \ - "0.4236314000, 0.4342437000, 0.4572681000, 0.5028883000, 0.5858555000, 0.7434631000, 1.0899835000", \ - "0.4483160000, 0.4588196000, 0.4821618000, 0.5273632000, 0.6102494000, 0.7679807000, 1.1144942000", \ - "0.5016001000, 0.5120019000, 0.5354281000, 0.5809204000, 0.6638914000, 0.8216512000, 1.1681631000", \ - "0.6249725000, 0.6356153000, 0.6585354000, 0.7041711000, 0.7874986000, 0.9454714000, 1.2918501000", \ - "0.8629336000, 0.8744643000, 0.8995458000, 0.9485662000, 1.0362531000, 1.1994075000, 1.5489627000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1870773000, 0.1955082000, 0.2145116000, 0.2552492000, 0.3455625000, 0.5803257000, 1.2546754000", \ - "0.1913064000, 0.1996716000, 0.2188745000, 0.2595693000, 0.3499168000, 0.5844882000, 1.2570756000", \ - "0.1999485000, 0.2083165000, 0.2275607000, 0.2682575000, 0.3585919000, 0.5932493000, 1.2668571000", \ - "0.2193661000, 0.2277431000, 0.2469899000, 0.2876666000, 0.3780295000, 0.6125994000, 1.2862429000", \ - "0.2609037000, 0.2692591000, 0.2885256000, 0.3292611000, 0.4195694000, 0.6540291000, 1.3296448000", \ - "0.3305168000, 0.3396436000, 0.3601690000, 0.4028857000, 0.4953818000, 0.7313605000, 1.4059340000", \ - "0.4243418000, 0.4348883000, 0.4584445000, 0.5056741000, 0.6027651000, 0.8405358000, 1.5149113000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0673857000, 0.0734419000, 0.0860516000, 0.1131727000, 0.1708523000, 0.3094284000, 0.7002091000", \ - "0.0669130000, 0.0729047000, 0.0866374000, 0.1114177000, 0.1696362000, 0.3090778000, 0.6991259000", \ - "0.0673918000, 0.0732574000, 0.0874357000, 0.1131121000, 0.1689011000, 0.3088177000, 0.6989153000", \ - "0.0676294000, 0.0733021000, 0.0860590000, 0.1118305000, 0.1685779000, 0.3092599000, 0.6990285000", \ - "0.0676598000, 0.0733180000, 0.0851652000, 0.1114941000, 0.1688832000, 0.3097209000, 0.6970994000", \ - "0.0683931000, 0.0734745000, 0.0859111000, 0.1126296000, 0.1701475000, 0.3090621000, 0.7003946000", \ - "0.0802775000, 0.0847451000, 0.0980832000, 0.1231802000, 0.1795013000, 0.3149734000, 0.7022090000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0345745000, 0.0412417000, 0.0569984000, 0.0951282000, 0.2017510000, 0.5279353000, 1.5009304000", \ - "0.0347468000, 0.0411526000, 0.0567440000, 0.0951374000, 0.2019472000, 0.5268416000, 1.5024441000", \ - "0.0347217000, 0.0410139000, 0.0565963000, 0.0951424000, 0.2019899000, 0.5263620000, 1.5032691000", \ - "0.0346267000, 0.0410402000, 0.0567181000, 0.0950673000, 0.2018379000, 0.5272252000, 1.5008349000", \ - "0.0351189000, 0.0414677000, 0.0570341000, 0.0951831000, 0.2017801000, 0.5275275000, 1.5007783000", \ - "0.0384538000, 0.0452063000, 0.0614645000, 0.0993485000, 0.2047885000, 0.5273783000, 1.4978527000", \ - "0.0474543000, 0.0552711000, 0.0709930000, 0.1097210000, 0.2124420000, 0.5301319000, 1.4972487000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4048666000, 0.4151327000, 0.4383294000, 0.4834255000, 0.5661637000, 0.7236334000, 1.0695631000", \ - "0.4096184000, 0.4199760000, 0.4430824000, 0.4882255000, 0.5709480000, 0.7284225000, 1.0743515000", \ - "0.4205606000, 0.4309696000, 0.4539405000, 0.4992921000, 0.5819066000, 0.7390317000, 1.0852284000", \ - "0.4433916000, 0.4537967000, 0.4769851000, 0.5221563000, 0.6049163000, 0.7620741000, 1.1081088000", \ - "0.4915708000, 0.5016479000, 0.5250516000, 0.5703535000, 0.6529923000, 0.8106074000, 1.1567239000", \ - "0.6024209000, 0.6128730000, 0.6365859000, 0.6816055000, 0.7642653000, 0.9218014000, 1.2680563000", \ - "0.8078631000, 0.8188128000, 0.8441265000, 0.8930514000, 0.9807534000, 1.1452546000, 1.4949773000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1908322000, 0.1994451000, 0.2187772000, 0.2601863000, 0.3517930000, 0.5874131000, 1.2642551000", \ - "0.1951242000, 0.2037103000, 0.2230301000, 0.2644354000, 0.3559819000, 0.5924414000, 1.2710922000", \ - "0.2043849000, 0.2129729000, 0.2323090000, 0.2737075000, 0.3653057000, 0.6014851000, 1.2768583000", \ - "0.2253508000, 0.2338535000, 0.2532508000, 0.2946546000, 0.3862306000, 0.6219988000, 1.2984279000", \ - "0.2704026000, 0.2789426000, 0.2985162000, 0.3397907000, 0.4313556000, 0.6676067000, 1.3426181000", \ - "0.3487486000, 0.3579530000, 0.3787074000, 0.4219713000, 0.5153305000, 0.7522098000, 1.4274285000", \ - "0.4605424000, 0.4712962000, 0.4950271000, 0.5428362000, 0.6407501000, 0.8794750000, 1.5548604000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0661384000, 0.0717818000, 0.0841070000, 0.1112770000, 0.1687611000, 0.3075573000, 0.6991785000", \ - "0.0661279000, 0.0717430000, 0.0841057000, 0.1113547000, 0.1687802000, 0.3075505000, 0.6992094000", \ - "0.0661068000, 0.0714185000, 0.0860722000, 0.1118944000, 0.1698331000, 0.3080459000, 0.6988303000", \ - "0.0663695000, 0.0719457000, 0.0839660000, 0.1102826000, 0.1674990000, 0.3077402000, 0.6978609000", \ - "0.0658282000, 0.0717676000, 0.0850409000, 0.1101936000, 0.1670442000, 0.3083992000, 0.6963370000", \ - "0.0673664000, 0.0725645000, 0.0848575000, 0.1107897000, 0.1684130000, 0.3081919000, 0.6981050000", \ - "0.0786880000, 0.0850077000, 0.0977811000, 0.1229350000, 0.1789359000, 0.3144744000, 0.7027945000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0350009000, 0.0416731000, 0.0574604000, 0.0957816000, 0.2026136000, 0.5279920000, 1.5011814000", \ - "0.0350182000, 0.0417747000, 0.0576393000, 0.0958242000, 0.2024957000, 0.5283055000, 1.4999185000", \ - "0.0349965000, 0.0417329000, 0.0575705000, 0.0957347000, 0.2026587000, 0.5270391000, 1.5014544000", \ - "0.0351876000, 0.0416792000, 0.0574681000, 0.0957868000, 0.2026173000, 0.5279269000, 1.5012781000", \ - "0.0355253000, 0.0419972000, 0.0575304000, 0.0958897000, 0.2027325000, 0.5274616000, 1.4999070000", \ - "0.0387322000, 0.0458427000, 0.0619879000, 0.0999627000, 0.2050230000, 0.5285859000, 1.5004767000", \ - "0.0475663000, 0.0549534000, 0.0715984000, 0.1106606000, 0.2131032000, 0.5310886000, 1.4947537000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4108521000, 0.4214223000, 0.4448030000, 0.4904499000, 0.5740558000, 0.7325646000, 1.0798916000", \ - "0.4165570000, 0.4271264000, 0.4503947000, 0.4961371000, 0.5794007000, 0.7378938000, 1.0853828000", \ - "0.4286272000, 0.4392300000, 0.4626277000, 0.5082388000, 0.5915827000, 0.7504171000, 1.0974903000", \ - "0.4534585000, 0.4639447000, 0.4874751000, 0.5328381000, 0.6162751000, 0.7747770000, 1.1223011000", \ - "0.5065477000, 0.5171889000, 0.5403768000, 0.5862167000, 0.6694470000, 0.8279192000, 1.1753770000", \ - "0.6272096000, 0.6377737000, 0.6612639000, 0.7068994000, 0.7904299000, 0.9490067000, 1.2965354000", \ - "0.8605056000, 0.8712143000, 0.8967442000, 0.9458555000, 1.0339652000, 1.1974426000, 1.5475243000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1874012000, 0.1957921000, 0.2151716000, 0.2562920000, 0.3476015000, 0.5839998000, 1.2595469000", \ - "0.1917907000, 0.2001660000, 0.2195423000, 0.2605745000, 0.3520039000, 0.5881924000, 1.2642059000", \ - "0.2008756000, 0.2091980000, 0.2285047000, 0.2696415000, 0.3608442000, 0.5974824000, 1.2744392000", \ - "0.2206766000, 0.2291034000, 0.2483486000, 0.2894040000, 0.3808175000, 0.6165858000, 1.2929454000", \ - "0.2631791000, 0.2715782000, 0.2909227000, 0.3320897000, 0.4232027000, 0.6598361000, 1.3371712000", \ - "0.3370782000, 0.3461462000, 0.3667615000, 0.4097530000, 0.5024657000, 0.7387069000, 1.4142865000", \ - "0.4376047000, 0.4481407000, 0.4720658000, 0.5196030000, 0.6170879000, 0.8555386000, 1.5304873000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0677703000, 0.0734504000, 0.0856324000, 0.1123504000, 0.1697636000, 0.3094975000, 0.7010410000", \ - "0.0672312000, 0.0733538000, 0.0867322000, 0.1132923000, 0.1690547000, 0.3104334000, 0.6994636000", \ - "0.0677971000, 0.0734475000, 0.0856504000, 0.1128226000, 0.1706587000, 0.3099232000, 0.7009781000", \ - "0.0680027000, 0.0735222000, 0.0865548000, 0.1121257000, 0.1691895000, 0.3105085000, 0.6979333000", \ - "0.0675650000, 0.0734013000, 0.0870502000, 0.1133988000, 0.1694607000, 0.3090881000, 0.6994778000", \ - "0.0683800000, 0.0736567000, 0.0859426000, 0.1123721000, 0.1695244000, 0.3102608000, 0.7004272000", \ - "0.0797729000, 0.0850662000, 0.0996605000, 0.1245309000, 0.1806279000, 0.3154244000, 0.7038267000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0347505000, 0.0412728000, 0.0565828000, 0.0951888000, 0.2021762000, 0.5263370000, 1.5015171000", \ - "0.0347776000, 0.0410116000, 0.0568391000, 0.0951370000, 0.2018483000, 0.5274442000, 1.4957434000", \ - "0.0348247000, 0.0413370000, 0.0568805000, 0.0951063000, 0.2021369000, 0.5275113000, 1.5024073000", \ - "0.0348073000, 0.0411273000, 0.0568418000, 0.0951251000, 0.2024581000, 0.5277035000, 1.5008065000", \ - "0.0350580000, 0.0415511000, 0.0571928000, 0.0953368000, 0.2021075000, 0.5280358000, 1.5020389000", \ - "0.0383466000, 0.0450074000, 0.0612713000, 0.0994306000, 0.2045082000, 0.5279853000, 1.4983158000", \ - "0.0475189000, 0.0543053000, 0.0709980000, 0.1097451000, 0.2120344000, 0.5300835000, 1.4959642000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4199485000, 0.4304875000, 0.4537044000, 0.5000557000, 0.5833068000, 0.7423897000, 1.0904371000", \ - "0.4244852000, 0.4353911000, 0.4588300000, 0.5046196000, 0.5882964000, 0.7470658000, 1.0952657000", \ - "0.4369370000, 0.4478469000, 0.4711759000, 0.5170018000, 0.6006562000, 0.7594494000, 1.1076268000", \ - "0.4617436000, 0.4723794000, 0.4956049000, 0.5416582000, 0.6252091000, 0.7839178000, 1.1321426000", \ - "0.5138322000, 0.5244719000, 0.5478288000, 0.5940506000, 0.6777013000, 0.8367338000, 1.1847578000", \ - "0.6327406000, 0.6434728000, 0.6670072000, 0.7131987000, 0.7971087000, 0.9559552000, 1.3040999000", \ - "0.8617722000, 0.8733027000, 0.8985790000, 0.9471491000, 1.0353101000, 1.1994481000, 1.5501955000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1879124000, 0.1963856000, 0.2155988000, 0.2567989000, 0.3481683000, 0.5844110000, 1.2599395000", \ - "0.1919989000, 0.2003221000, 0.2198621000, 0.2609526000, 0.3524225000, 0.5885616000, 1.2647799000", \ - "0.2010209000, 0.2095102000, 0.2287059000, 0.2698273000, 0.3613400000, 0.5969683000, 1.2741849000", \ - "0.2212175000, 0.2296506000, 0.2489490000, 0.2901451000, 0.3814057000, 0.6180001000, 1.2954416000", \ - "0.2647074000, 0.2731179000, 0.2924890000, 0.3335950000, 0.4250471000, 0.6610005000, 1.3381143000", \ - "0.3389920000, 0.3482296000, 0.3687219000, 0.4118196000, 0.5048371000, 0.7416454000, 1.4181581000", \ - "0.4398074000, 0.4504707000, 0.4743512000, 0.5220602000, 0.6195643000, 0.8580515000, 1.5341407000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0678972000, 0.0743674000, 0.0870613000, 0.1135037000, 0.1696537000, 0.3111103000, 0.7005789000", \ - "0.0679389000, 0.0734865000, 0.0871416000, 0.1145670000, 0.1721896000, 0.3109570000, 0.7009309000", \ - "0.0684360000, 0.0741528000, 0.0871325000, 0.1144792000, 0.1697438000, 0.3109129000, 0.7007546000", \ - "0.0684256000, 0.0742391000, 0.0868095000, 0.1140508000, 0.1717636000, 0.3109470000, 0.7011550000", \ - "0.0682188000, 0.0739169000, 0.0877219000, 0.1141549000, 0.1695424000, 0.3108125000, 0.7007690000", \ - "0.0690789000, 0.0740401000, 0.0863162000, 0.1130784000, 0.1702230000, 0.3113352000, 0.6992576000", \ - "0.0807309000, 0.0854596000, 0.0983853000, 0.1245331000, 0.1806034000, 0.3161780000, 0.7041243000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0347110000, 0.0411684000, 0.0570247000, 0.0951446000, 0.2021537000, 0.5268851000, 1.5010885000", \ - "0.0348485000, 0.0412563000, 0.0569113000, 0.0952944000, 0.2020200000, 0.5275266000, 1.4960451000", \ - "0.0347556000, 0.0411624000, 0.0568863000, 0.0953026000, 0.2025604000, 0.5277938000, 1.5008530000", \ - "0.0345153000, 0.0413373000, 0.0570343000, 0.0952632000, 0.2022014000, 0.5278276000, 1.5018891000", \ - "0.0350716000, 0.0412761000, 0.0568588000, 0.0955375000, 0.2024513000, 0.5279567000, 1.4984450000", \ - "0.0383367000, 0.0450792000, 0.0613752000, 0.0996941000, 0.2044588000, 0.5287344000, 1.5020756000", \ - "0.0477061000, 0.0542766000, 0.0710805000, 0.1099921000, 0.2120950000, 0.5305726000, 1.4978200000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.3746346000, 0.3851202000, 0.4086974000, 0.4544212000, 0.5376989000, 0.6960131000, 1.0435255000", \ - "0.3785701000, 0.3890412000, 0.4125132000, 0.4585053000, 0.5416176000, 0.6998749000, 1.0474598000", \ - "0.3893547000, 0.3998320000, 0.4233669000, 0.4692158000, 0.5524462000, 0.7107778000, 1.0583078000", \ - "0.4171118000, 0.4276967000, 0.4513324000, 0.4968734000, 0.5801831000, 0.7387581000, 1.0861617000", \ - "0.4855453000, 0.4963695000, 0.5198382000, 0.5654853000, 0.6487464000, 0.8073499000, 1.1548493000", \ - "0.6499271000, 0.6607497000, 0.6842180000, 0.7298687000, 0.8132464000, 0.9718122000, 1.3194497000", \ - "0.9776112000, 0.9898866000, 1.0158220000, 1.0666659000, 1.1562329000, 1.3201732000, 1.6704156000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1712913000, 0.1800936000, 0.1997857000, 0.2416991000, 0.3340826000, 0.5707342000, 1.2453413000", \ - "0.1754861000, 0.1840935000, 0.2039224000, 0.2457874000, 0.3381020000, 0.5744420000, 1.2521791000", \ - "0.1850418000, 0.1938252000, 0.2135381000, 0.2554401000, 0.3478413000, 0.5845112000, 1.2603141000", \ - "0.2069703000, 0.2156401000, 0.2354993000, 0.2772330000, 0.3695964000, 0.6061331000, 1.2812905000", \ - "0.2510811000, 0.2598785000, 0.2797464000, 0.3215850000, 0.4138484000, 0.6500419000, 1.3254887000", \ - "0.3178596000, 0.3279458000, 0.3498185000, 0.3943867000, 0.4886279000, 0.7262271000, 1.4032239000", \ - "0.3853014000, 0.3974774000, 0.4249344000, 0.4769763000, 0.5771562000, 0.8165358000, 1.4916309000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0671728000, 0.0730860000, 0.0853254000, 0.1131348000, 0.1682715000, 0.3094661000, 0.6993983000", \ - "0.0672723000, 0.0727283000, 0.0849540000, 0.1127435000, 0.1685403000, 0.3096978000, 0.6995479000", \ - "0.0671804000, 0.0729829000, 0.0851176000, 0.1131337000, 0.1683675000, 0.3094490000, 0.6993254000", \ - "0.0673063000, 0.0730520000, 0.0858491000, 0.1131844000, 0.1682818000, 0.3099695000, 0.6999782000", \ - "0.0672115000, 0.0724079000, 0.0863379000, 0.1110881000, 0.1686189000, 0.3103414000, 0.6996488000", \ - "0.0675573000, 0.0728637000, 0.0865780000, 0.1119684000, 0.1693475000, 0.3103800000, 0.6999292000", \ - "0.0917081000, 0.0956447000, 0.1071052000, 0.1306650000, 0.1849958000, 0.3187231000, 0.7029701000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0359135000, 0.0423578000, 0.0584666000, 0.0969634000, 0.2036654000, 0.5273908000, 1.4957405000", \ - "0.0357280000, 0.0421527000, 0.0580387000, 0.0969718000, 0.2037137000, 0.5272676000, 1.5011159000", \ - "0.0359383000, 0.0423793000, 0.0584830000, 0.0969656000, 0.2036185000, 0.5274343000, 1.4990300000", \ - "0.0358910000, 0.0422456000, 0.0583142000, 0.0967222000, 0.2035674000, 0.5284012000, 1.5003742000", \ - "0.0366040000, 0.0431214000, 0.0587758000, 0.0971951000, 0.2034748000, 0.5282272000, 1.4999558000", \ - "0.0429829000, 0.0495511000, 0.0661171000, 0.1033166000, 0.2072035000, 0.5288217000, 1.4998882000", \ - "0.0589471000, 0.0670229000, 0.0837529000, 0.1203278000, 0.2174828000, 0.5315084000, 1.4950011000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4437304000, 0.4540818000, 0.4772144000, 0.5224792000, 0.6051443000, 0.7625415000, 1.1086428000", \ - "0.4484687000, 0.4588832000, 0.4820884000, 0.5271265000, 0.6098007000, 0.7672666000, 1.1132819000", \ - "0.4587409000, 0.4691064000, 0.4922426000, 0.5375214000, 0.6202069000, 0.7776073000, 1.1237126000", \ - "0.4796816000, 0.4900325000, 0.5131568000, 0.5584398000, 0.6411610000, 0.7985685000, 1.1446820000", \ - "0.5134259000, 0.5238703000, 0.5468756000, 0.5923388000, 0.6748984000, 0.8322674000, 1.1782513000", \ - "0.5560891000, 0.5664421000, 0.5895905000, 0.6351743000, 0.7182538000, 0.8757710000, 1.2218860000", \ - "0.6029630000, 0.6129450000, 0.6361363000, 0.6813344000, 0.7639115000, 0.9210869000, 1.2669942000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2880656000, 0.2965204000, 0.3157156000, 0.3564978000, 0.4468052000, 0.6819528000, 1.3573795000", \ - "0.2916572000, 0.3000356000, 0.3192891000, 0.3599568000, 0.4504878000, 0.6848965000, 1.3609244000", \ - "0.3031164000, 0.3114828000, 0.3307538000, 0.3715161000, 0.4619057000, 0.6968942000, 1.3717615000", \ - "0.3336632000, 0.3419920000, 0.3611702000, 0.4019551000, 0.4922309000, 0.7274409000, 1.4050381000", \ - "0.4037823000, 0.4121267000, 0.4313563000, 0.4720405000, 0.5625810000, 0.7968623000, 1.4731382000", \ - "0.5264448000, 0.5348421000, 0.5539471000, 0.5948785000, 0.6857677000, 0.9205971000, 1.5959537000", \ - "0.7221028000, 0.7307158000, 0.7502414000, 0.7914692000, 0.8822676000, 1.1176423000, 1.7915487000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0665016000, 0.0719812000, 0.0844454000, 0.1105071000, 0.1673986000, 0.3084131000, 0.6978272000", \ - "0.0662292000, 0.0718351000, 0.0839182000, 0.1105019000, 0.1673629000, 0.3071033000, 0.6975986000", \ - "0.0664699000, 0.0715549000, 0.0845396000, 0.1105182000, 0.1674383000, 0.3084647000, 0.6975319000", \ - "0.0664930000, 0.0719171000, 0.0843755000, 0.1104811000, 0.1674225000, 0.3084487000, 0.6976907000", \ - "0.0658977000, 0.0714635000, 0.0853462000, 0.1115824000, 0.1679239000, 0.3070796000, 0.6976613000", \ - "0.0655861000, 0.0711015000, 0.0847959000, 0.1116872000, 0.1680214000, 0.3084098000, 0.6990581000", \ - "0.0648983000, 0.0711240000, 0.0833115000, 0.1098816000, 0.1690775000, 0.3073714000, 0.6967820000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0352507000, 0.0415274000, 0.0570868000, 0.0952214000, 0.2022213000, 0.5274490000, 1.5028485000", \ - "0.0349682000, 0.0412258000, 0.0569939000, 0.0952663000, 0.2023364000, 0.5278052000, 1.4989827000", \ - "0.0351806000, 0.0414114000, 0.0568898000, 0.0952741000, 0.2020930000, 0.5265100000, 1.5024666000", \ - "0.0349627000, 0.0415372000, 0.0571266000, 0.0952146000, 0.2021099000, 0.5276896000, 1.4998974000", \ - "0.0349748000, 0.0413077000, 0.0569500000, 0.0952718000, 0.2024888000, 0.5276669000, 1.5001452000", \ - "0.0351890000, 0.0414927000, 0.0571027000, 0.0958003000, 0.2025369000, 0.5279009000, 1.4989302000", \ - "0.0360274000, 0.0427978000, 0.0584962000, 0.0963187000, 0.2023767000, 0.5269666000, 1.4966494000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2399966000, 0.2503268000, 0.2733793000, 0.3186075000, 0.4005219000, 0.5570880000, 0.9025925000", \ - "0.2445389000, 0.2548767000, 0.2779867000, 0.3229822000, 0.4050726000, 0.5615625000, 0.9069273000", \ - "0.2552276000, 0.2652833000, 0.2885937000, 0.3336468000, 0.4157611000, 0.5718659000, 0.9177075000", \ - "0.2803892000, 0.2908853000, 0.3140631000, 0.3588910000, 0.4409203000, 0.5975715000, 0.9428963000", \ - "0.3346550000, 0.3448351000, 0.3678013000, 0.4124613000, 0.4944320000, 0.6506262000, 0.9961457000", \ - "0.4496420000, 0.4606429000, 0.4848759000, 0.5302747000, 0.6116109000, 0.7682352000, 1.1136412000", \ - "0.6266296000, 0.6403134000, 0.6705750000, 0.7298243000, 0.8276633000, 0.9943839000, 1.3463424000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1322831000, 0.1408095000, 0.1600963000, 0.2012452000, 0.2927387000, 0.5285664000, 1.2029036000", \ - "0.1368509000, 0.1452931000, 0.1647178000, 0.2058171000, 0.2971871000, 0.5333748000, 1.2091346000", \ - "0.1473973000, 0.1558408000, 0.1752547000, 0.2163811000, 0.3076303000, 0.5440144000, 1.2216780000", \ - "0.1710600000, 0.1796467000, 0.1989253000, 0.2399810000, 0.3313522000, 0.5669896000, 1.2457860000", \ - "0.2234960000, 0.2319524000, 0.2512232000, 0.2924014000, 0.3839754000, 0.6201305000, 1.2948019000", \ - "0.2989836000, 0.3091579000, 0.3309068000, 0.3745527000, 0.4678716000, 0.7056801000, 1.3866028000", \ - "0.3838321000, 0.3966189000, 0.4247709000, 0.4778013000, 0.5769113000, 0.8140315000, 1.4898834000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0626069000, 0.0682792000, 0.0808967000, 0.1094050000, 0.1649142000, 0.3070448000, 0.6963403000", \ - "0.0626388000, 0.0681527000, 0.0807071000, 0.1077359000, 0.1659214000, 0.3059509000, 0.6966401000", \ - "0.0629189000, 0.0684975000, 0.0818837000, 0.1072631000, 0.1669751000, 0.3064795000, 0.6986307000", \ - "0.0624360000, 0.0683819000, 0.0810578000, 0.1089774000, 0.1653405000, 0.3061746000, 0.6982288000", \ - "0.0607779000, 0.0664495000, 0.0804267000, 0.1068497000, 0.1662431000, 0.3058560000, 0.6967559000", \ - "0.0697762000, 0.0753989000, 0.0875875000, 0.1105964000, 0.1671692000, 0.3067329000, 0.6986156000", \ - "0.0965640000, 0.1039961000, 0.1189536000, 0.1475783000, 0.1992812000, 0.3268877000, 0.7076281000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0345150000, 0.0410730000, 0.0566528000, 0.0950125000, 0.2016666000, 0.5273895000, 1.4992093000", \ - "0.0345841000, 0.0409562000, 0.0566304000, 0.0949363000, 0.2019494000, 0.5266313000, 1.5034397000", \ - "0.0345454000, 0.0411043000, 0.0566165000, 0.0949702000, 0.2018698000, 0.5274964000, 1.4995032000", \ - "0.0344747000, 0.0409050000, 0.0567480000, 0.0948070000, 0.2022094000, 0.5273581000, 1.4996653000", \ - "0.0360272000, 0.0421469000, 0.0574140000, 0.0958328000, 0.2021065000, 0.5265896000, 1.4977948000", \ - "0.0467752000, 0.0530751000, 0.0672036000, 0.1032977000, 0.2069272000, 0.5286570000, 1.5004632000", \ - "0.0653179000, 0.0734143000, 0.0902873000, 0.1237969000, 0.2176448000, 0.5331111000, 1.4968254000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2397436000, 0.2501770000, 0.2737584000, 0.3192583000, 0.4024751000, 0.5606232000, 0.9078667000", \ - "0.2447549000, 0.2551818000, 0.2785674000, 0.3244841000, 0.4073097000, 0.5655754000, 0.9127951000", \ - "0.2549087000, 0.2653276000, 0.2890941000, 0.3347319000, 0.4179835000, 0.5756277000, 0.9231053000", \ - "0.2769386000, 0.2869381000, 0.3106320000, 0.3559853000, 0.4386144000, 0.5962710000, 0.9430415000", \ - "0.3195882000, 0.3298418000, 0.3528905000, 0.3978563000, 0.4803394000, 0.6376597000, 0.9846093000", \ - "0.3799708000, 0.3890918000, 0.4103932000, 0.4531915000, 0.5334750000, 0.6889589000, 1.0356994000", \ - "0.4073024000, 0.4167987000, 0.4381835000, 0.4810748000, 0.5621792000, 0.7182406000, 1.0641850000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1714219000, 0.1799362000, 0.1994855000, 0.2406242000, 0.3321426000, 0.5679861000, 1.2468965000", \ - "0.1763147000, 0.1849562000, 0.2043034000, 0.2455904000, 0.3369217000, 0.5733695000, 1.2530355000", \ - "0.1897090000, 0.1982359000, 0.2176665000, 0.2588833000, 0.3504233000, 0.5861732000, 1.2649292000", \ - "0.2216017000, 0.2301071000, 0.2494985000, 0.2908148000, 0.3821059000, 0.6185853000, 1.2969438000", \ - "0.2835074000, 0.2920193000, 0.3114243000, 0.3526373000, 0.4441457000, 0.6798342000, 1.3544654000", \ - "0.3771835000, 0.3856238000, 0.4049445000, 0.4461257000, 0.5372480000, 0.7733256000, 1.4495967000", \ - "0.5212845000, 0.5295273000, 0.5492359000, 0.5903778000, 0.6819056000, 0.9172322000, 1.5911799000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0661858000, 0.0720272000, 0.0848308000, 0.1104189000, 0.1683147000, 0.3096720000, 0.6990545000", \ - "0.0662644000, 0.0719195000, 0.0842115000, 0.1120911000, 0.1680473000, 0.3098275000, 0.6998496000", \ - "0.0664477000, 0.0713238000, 0.0852037000, 0.1105869000, 0.1689421000, 0.3094876000, 0.7005377000", \ - "0.0650464000, 0.0705097000, 0.0830309000, 0.1100632000, 0.1673199000, 0.3085474000, 0.6990624000", \ - "0.0610631000, 0.0668318000, 0.0805926000, 0.1075630000, 0.1669842000, 0.3075692000, 0.6970921000", \ - "0.0562516000, 0.0620074000, 0.0753310000, 0.1046984000, 0.1629321000, 0.3061247000, 0.6978975000", \ - "0.0568474000, 0.0622445000, 0.0761393000, 0.1040527000, 0.1639866000, 0.3057838000, 0.6929799000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0350362000, 0.0413011000, 0.0572016000, 0.0955664000, 0.2026188000, 0.5278529000, 1.5022368000", \ - "0.0350511000, 0.0414867000, 0.0572927000, 0.0955445000, 0.2022588000, 0.5279768000, 1.5005966000", \ - "0.0350508000, 0.0413419000, 0.0571883000, 0.0956224000, 0.2027259000, 0.5278568000, 1.4981101000", \ - "0.0353345000, 0.0415993000, 0.0571845000, 0.0955565000, 0.2023939000, 0.5277186000, 1.5000015000", \ - "0.0351819000, 0.0415129000, 0.0569289000, 0.0956174000, 0.2025684000, 0.5278682000, 1.5007570000", \ - "0.0346473000, 0.0414318000, 0.0572338000, 0.0954415000, 0.2018945000, 0.5269952000, 1.5017557000", \ - "0.0354604000, 0.0421925000, 0.0576998000, 0.0959517000, 0.2029101000, 0.5264325000, 1.4955419000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__mux4_4") { - leakage_power () { - value : 0.0072464000; - when : "!A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0059859000; - when : "!A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0082752000; - when : "!A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0070148000; - when : "!A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0076441000; - when : "!A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0063836000; - when : "!A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0076514000; - when : "!A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0088244000; - when : "!A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0065558000; - when : "!A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0077288000; - when : "!A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0086710000; - when : "!A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0074106000; - when : "!A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0063162000; - when : "!A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0074892000; - when : "!A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0074181000; - when : "!A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0085911000; - when : "!A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0076421000; - when : "!A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0063817000; - when : "!A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0107468000; - when : "!A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0070530000; - when : "!A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0080398000; - when : "!A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0067794000; - when : "!A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0075942000; - when : "!A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0063338000; - when : "!A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0069516000; - when : "!A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0081245000; - when : "!A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0111426000; - when : "!A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0074488000; - when : "!A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0067119000; - when : "!A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0078849000; - when : "!A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0073609000; - when : "!A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0061005000; - when : "!A0&A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0086616000; - when : "A0&!A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0049678000; - when : "A0&!A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0086866000; - when : "A0&!A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0074261000; - when : "A0&!A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0090593000; - when : "A0&!A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0053655000; - when : "A0&!A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0080627000; - when : "A0&!A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0092357000; - when : "A0&!A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0054423000; - when : "A0&!A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0041818000; - when : "A0&!A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0090823000; - when : "A0&!A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0078219000; - when : "A0&!A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0052026000; - when : "A0&!A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0039422000; - when : "A0&!A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0078294000; - when : "A0&!A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0090024000; - when : "A0&!A1&A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0085003000; - when : "A0&A1&!A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0048065000; - when : "A0&A1&!A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0105408000; - when : "A0&A1&!A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0068471000; - when : "A0&A1&!A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0088979000; - when : "A0&A1&!A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0052042000; - when : "A0&A1&!A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0073883000; - when : "A0&A1&!A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0061278000; - when : "A0&A1&!A2&A3&S0&!S1"; - } - leakage_power () { - value : 0.0052809000; - when : "A0&A1&A2&!A3&!S0&S1"; - } - leakage_power () { - value : 0.0040205000; - when : "A0&A1&A2&!A3&!S0&!S1"; - } - leakage_power () { - value : 0.0109366000; - when : "A0&A1&A2&!A3&S0&S1"; - } - leakage_power () { - value : 0.0072428000; - when : "A0&A1&A2&!A3&S0&!S1"; - } - leakage_power () { - value : 0.0050413000; - when : "A0&A1&A2&A3&!S0&S1"; - } - leakage_power () { - value : 0.0037809000; - when : "A0&A1&A2&A3&!S0&!S1"; - } - leakage_power () { - value : 0.0071550000; - when : "A0&A1&A2&A3&S0&S1"; - } - leakage_power () { - value : 0.0058945000; - when : "A0&A1&A2&A3&S0&!S1"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__mux4"; - cell_leakage_power : 0.0072365410; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A0") { - capacitance : 0.0017890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0096456000, 0.0095878000, 0.0094547000, 0.0094624000, 0.0094802000, 0.0095212000, 0.0096157000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027827000, 0.0027294000, 0.0026068000, 0.0026239000, 0.0026634000, 0.0027545000, 0.0029643000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018750000; - } - pin ("A1") { - capacitance : 0.0017780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032909000, 0.0032862000, 0.0032753000, 0.0032757000, 0.0032766000, 0.0032786000, 0.0032830000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003179500, -0.003194500, -0.003229000, -0.003232500, -0.003240500, -0.003259000, -0.003301700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018670000; - } - pin ("A2") { - capacitance : 0.0017420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087646000, 0.0087121000, 0.0085912000, 0.0086002000, 0.0086209000, 0.0086687000, 0.0087787000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047275000, 0.0046741000, 0.0045512000, 0.0045727000, 0.0046222000, 0.0047362000, 0.0049990000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018140000; - } - pin ("A3") { - capacitance : 0.0017450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029108000, 0.0029110000, 0.0029114000, 0.0029092000, 0.0029043000, 0.0028929000, 0.0028666000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002818700, -0.002836400, -0.002877200, -0.002877700, -0.002879000, -0.002882000, -0.002889000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018230000; - } - pin ("S0") { - capacitance : 0.0054620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0197016000, 0.0194089000, 0.0187343000, 0.0187925000, 0.0189267000, 0.0192361000, 0.0199491000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017680000, 0.0015591000, 0.0010776000, 0.0011124000, 0.0011928000, 0.0013781000, 0.0018052000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0057740000; - } - pin ("S1") { - capacitance : 0.0031760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0030690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0103286000, 0.0102071000, 0.0099269000, 0.0099983000, 0.0101629000, 0.0105424000, 0.0114171000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000896900, -0.001021400, -0.001308300, -0.001236800, -0.001072000, -0.000692200, 0.0001834000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0032830000; - } - pin ("X") { - direction : "output"; - function : "(A0&!S0&!S1) | (A1&S0&!S1) | (A2&!S0&S1) | (A3&S0&S1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0231181000, 0.0206851000, 0.0136419000, -0.005651100, -0.063220900, -0.250235500, -0.860632800", \ - "0.0231363000, 0.0207809000, 0.0136695000, -0.005940400, -0.063231000, -0.250383300, -0.860679000", \ - "0.0229921000, 0.0206038000, 0.0136128000, -0.005637700, -0.063168200, -0.250294100, -0.860605900", \ - "0.0228919000, 0.0204525000, 0.0133667000, -0.005991000, -0.063304700, -0.250446000, -0.860703000", \ - "0.0229146000, 0.0204307000, 0.0133656000, -0.005853200, -0.063379500, -0.250596100, -0.860830300", \ - "0.0225390000, 0.0201351000, 0.0130641000, -0.006214500, -0.063758100, -0.250845100, -0.861015700", \ - "0.0238363000, 0.0213825000, 0.0141351000, -0.005352700, -0.063463500, -0.250781200, -0.860966800"); - } - related_pin : "A0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0273708000, 0.0291008000, 0.0347800000, 0.0542825000, 0.1144003000, 0.3024492000, 0.9108463000", \ - "0.0274069000, 0.0291101000, 0.0349296000, 0.0541686000, 0.1144264000, 0.3023391000, 0.9066067000", \ - "0.0274426000, 0.0292064000, 0.0351108000, 0.0542635000, 0.1143557000, 0.3026556000, 0.9072322000", \ - "0.0273494000, 0.0291023000, 0.0349976000, 0.0541599000, 0.1142365000, 0.3025557000, 0.9028412000", \ - "0.0271989000, 0.0288932000, 0.0347376000, 0.0541790000, 0.1143420000, 0.3021639000, 0.9073292000", \ - "0.0272628000, 0.0290389000, 0.0347643000, 0.0539709000, 0.1138887000, 0.3020810000, 0.9071789000", \ - "0.0306881000, 0.0323366000, 0.0378163000, 0.0560130000, 0.1145662000, 0.3024728000, 0.9065507000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0313299000, 0.0289443000, 0.0216958000, 0.0025781000, -0.054570900, -0.241055100, -0.850823200", \ - "0.0309557000, 0.0285960000, 0.0214983000, 0.0025312000, -0.054784400, -0.241149900, -0.850907400", \ - "0.0308809000, 0.0284771000, 0.0214181000, 0.0023583000, -0.054784900, -0.241252800, -0.850962900", \ - "0.0309745000, 0.0286096000, 0.0215466000, 0.0024667000, -0.054940200, -0.241304500, -0.851054500", \ - "0.0307237000, 0.0283352000, 0.0213144000, 0.0022875000, -0.055048400, -0.241430400, -0.851180700", \ - "0.0305830000, 0.0282014000, 0.0211211000, 0.0020434000, -0.055168300, -0.241701600, -0.851360400", \ - "0.0319983000, 0.0296117000, 0.0223128000, 0.0029023000, -0.054542500, -0.241485700, -0.851231700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0310926000, 0.0327988000, 0.0386400000, 0.0578938000, 0.1183263000, 0.3071145000, 0.9130792000", \ - "0.0309797000, 0.0327268000, 0.0385748000, 0.0579884000, 0.1182134000, 0.3069961000, 0.9130007000", \ - "0.0309380000, 0.0326323000, 0.0383976000, 0.0577139000, 0.1181810000, 0.3070545000, 0.9123385000", \ - "0.0308424000, 0.0325794000, 0.0381949000, 0.0576781000, 0.1179764000, 0.3069807000, 0.9166099000", \ - "0.0306978000, 0.0325497000, 0.0382510000, 0.0576860000, 0.1181857000, 0.3070417000, 0.9129093000", \ - "0.0309524000, 0.0327397000, 0.0385081000, 0.0574174000, 0.1178606000, 0.3065746000, 0.9127487000", \ - "0.0345385000, 0.0361554000, 0.0416321000, 0.0599334000, 0.1184755000, 0.3069568000, 0.9158800000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0249347000, 0.0225404000, 0.0154887000, -0.003651200, -0.061015300, -0.247300400, -0.856912500", \ - "0.0249460000, 0.0225428000, 0.0155219000, -0.003618100, -0.060949100, -0.247301300, -0.856913500", \ - "0.0251092000, 0.0226295000, 0.0156182000, -0.003577800, -0.060813800, -0.247219900, -0.856802500", \ - "0.0249404000, 0.0225254000, 0.0154597000, -0.003817700, -0.061011900, -0.247310300, -0.856895800", \ - "0.0248818000, 0.0225352000, 0.0154414000, -0.003769600, -0.060970400, -0.247346600, -0.856995300", \ - "0.0247898000, 0.0223669000, 0.0153335000, -0.003877800, -0.061211800, -0.247636100, -0.857189200", \ - "0.0260326000, 0.0236375000, 0.0163755000, -0.003072600, -0.060864800, -0.247705400, -0.857277600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0248790000, 0.0267658000, 0.0323830000, 0.0519131000, 0.1124017000, 0.3019509000, 0.9039900000", \ - "0.0249031000, 0.0266348000, 0.0325002000, 0.0518112000, 0.1124646000, 0.3016817000, 0.9081917000", \ - "0.0249044000, 0.0267070000, 0.0326587000, 0.0519625000, 0.1124784000, 0.3019164000, 0.9087594000", \ - "0.0248937000, 0.0266234000, 0.0323640000, 0.0518493000, 0.1124529000, 0.3015446000, 0.9115056000", \ - "0.0247873000, 0.0264961000, 0.0323536000, 0.0518525000, 0.1124137000, 0.3012736000, 0.9072840000", \ - "0.0248091000, 0.0265649000, 0.0324378000, 0.0516690000, 0.1119540000, 0.3012366000, 0.9076471000", \ - "0.0282743000, 0.0299070000, 0.0354011000, 0.0536187000, 0.1124495000, 0.3008203000, 0.9059780000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0330694000, 0.0307302000, 0.0236196000, 0.0045304000, -0.052538100, -0.238966000, -0.848635000", \ - "0.0328523000, 0.0304581000, 0.0234134000, 0.0040596000, -0.053054500, -0.239199500, -0.848755300", \ - "0.0328762000, 0.0304056000, 0.0232916000, 0.0039985000, -0.052952500, -0.239232500, -0.848812100", \ - "0.0326572000, 0.0302792000, 0.0233086000, 0.0043926000, -0.052846800, -0.239322500, -0.848881800", \ - "0.0326724000, 0.0302968000, 0.0232116000, 0.0041175000, -0.053070200, -0.239353000, -0.848972000", \ - "0.0325190000, 0.0300782000, 0.0229753000, 0.0039723000, -0.053411500, -0.239634900, -0.849112700", \ - "0.0340377000, 0.0315958000, 0.0242704000, 0.0049868000, -0.052877200, -0.239425100, -0.849013900"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0300261000, 0.0318129000, 0.0374832000, 0.0569420000, 0.1172896000, 0.3065212000, 0.9165801000", \ - "0.0299683000, 0.0317357000, 0.0374885000, 0.0567912000, 0.1172872000, 0.3063996000, 0.9120160000", \ - "0.0299133000, 0.0316802000, 0.0374131000, 0.0567836000, 0.1172318000, 0.3062233000, 0.9161029000", \ - "0.0298825000, 0.0316066000, 0.0373558000, 0.0567383000, 0.1171034000, 0.3062734000, 0.9163177000", \ - "0.0298486000, 0.0315182000, 0.0373332000, 0.0567402000, 0.1170789000, 0.3060643000, 0.9123362000", \ - "0.0299791000, 0.0317231000, 0.0374375000, 0.0565584000, 0.1167865000, 0.3057031000, 0.9120445000", \ - "0.0334711000, 0.0350440000, 0.0406353000, 0.0589232000, 0.1172716000, 0.3068990000, 0.9108025000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0327787000, 0.0303671000, 0.0231610000, 0.0041753000, -0.053038400, -0.239384800, -0.849191500", \ - "0.0327673000, 0.0303439000, 0.0233310000, 0.0042183000, -0.052925800, -0.239375200, -0.849161600", \ - "0.0327162000, 0.0303352000, 0.0233056000, 0.0040892000, -0.053118800, -0.239372400, -0.849116500", \ - "0.0319249000, 0.0295518000, 0.0225303000, 0.0034728000, -0.053672900, -0.240121100, -0.849869300", \ - "0.0313982000, 0.0289287000, 0.0218944000, 0.0027923000, -0.054407800, -0.240722100, -0.850397100", \ - "0.0309615000, 0.0285983000, 0.0216571000, 0.0025356000, -0.054665900, -0.241032500, -0.850711000", \ - "0.0368542000, 0.0344248000, 0.0271942000, 0.0066451000, -0.053617100, -0.240073300, -0.849707100"); - } - related_pin : "S0"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0386872000, 0.0404184000, 0.0462055000, 0.0656404000, 0.1258064000, 0.3137640000, 0.9191459000", \ - "0.0386126000, 0.0403727000, 0.0460612000, 0.0654537000, 0.1258037000, 0.3140023000, 0.9187922000", \ - "0.0387595000, 0.0404831000, 0.0462373000, 0.0656012000, 0.1258554000, 0.3137937000, 0.9185023000", \ - "0.0383534000, 0.0400696000, 0.0458811000, 0.0651456000, 0.1253680000, 0.3134867000, 0.9186961000", \ - "0.0376617000, 0.0394147000, 0.0451388000, 0.0645544000, 0.1247468000, 0.3127053000, 0.9174776000", \ - "0.0373633000, 0.0391312000, 0.0448388000, 0.0642151000, 0.1244768000, 0.3127159000, 0.9217790000", \ - "0.0395133000, 0.0412170000, 0.0467507000, 0.0651232000, 0.1248710000, 0.3126474000, 0.9168711000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0246172000, 0.0221653000, 0.0151037000, -0.004018100, -0.061085500, -0.247334000, -0.857009800", \ - "0.0245632000, 0.0221618000, 0.0150414000, -0.004074300, -0.061057800, -0.247359100, -0.857055900", \ - "0.0247313000, 0.0223347000, 0.0152543000, -0.004037900, -0.060940100, -0.247164900, -0.856880400", \ - "0.0245343000, 0.0221250000, 0.0150146000, -0.004073000, -0.061002700, -0.247335400, -0.857016300", \ - "0.0242783000, 0.0218230000, 0.0148072000, -0.004170300, -0.061135400, -0.247229100, -0.856927500", \ - "0.0238264000, 0.0215094000, 0.0145550000, -0.004260300, -0.061024500, -0.247190200, -0.856777200", \ - "0.0326548000, 0.0302096000, 0.0230503000, 0.0028510000, -0.057392900, -0.245997300, -0.855623600"); - } - related_pin : "S1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016056810, 0.0051564240, 0.0165591500, 0.0531774200, 0.1707720000, 0.5484107000"); - values("0.0267332000, 0.0284574000, 0.0342556000, 0.0536177000, 0.1142203000, 0.3032269000, 0.9093049000", \ - "0.0265187000, 0.0283246000, 0.0340805000, 0.0535226000, 0.1138839000, 0.3029751000, 0.9129470000", \ - "0.0267372000, 0.0284534000, 0.0342341000, 0.0536333000, 0.1142523000, 0.3030441000, 0.9089739000", \ - "0.0266075000, 0.0284702000, 0.0341600000, 0.0535608000, 0.1139664000, 0.3031110000, 0.9131580000", \ - "0.0266445000, 0.0284585000, 0.0342218000, 0.0536676000, 0.1141029000, 0.3031357000, 0.9131185000", \ - "0.0272205000, 0.0289188000, 0.0347400000, 0.0539508000, 0.1145428000, 0.3034456000, 0.9099104000", \ - "0.0306143000, 0.0323708000, 0.0381022000, 0.0564953000, 0.1154273000, 0.3048316000, 0.9082048000"); - } - } - max_capacitance : 0.5484110000; - max_transition : 1.5049570000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5511351000, 0.5593666000, 0.5809816000, 0.6296572000, 0.7247308000, 0.9040786000, 1.2844931000", \ - "0.5562673000, 0.5642555000, 0.5862656000, 0.6344965000, 0.7295515000, 0.9095681000, 1.2899085000", \ - "0.5683765000, 0.5765898000, 0.5985503000, 0.6475360000, 0.7421561000, 0.9218291000, 1.3025890000", \ - "0.5933126000, 0.6013228000, 0.6232084000, 0.6718185000, 0.7671058000, 0.9468483000, 1.3273107000", \ - "0.6477588000, 0.6559274000, 0.6777904000, 0.7263123000, 0.8211340000, 1.0011202000, 1.3817083000", \ - "0.7734248000, 0.7815513000, 0.8031601000, 0.8520157000, 0.9467473000, 1.1268635000, 1.5074080000", \ - "1.0414859000, 1.0497447000, 1.0721611000, 1.1222130000, 1.2198434000, 1.4006099000, 1.7840489000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2497307000, 0.2566626000, 0.2748399000, 0.3166637000, 0.4084322000, 0.6406042000, 1.3504052000", \ - "0.2540533000, 0.2610078000, 0.2792779000, 0.3207157000, 0.4126439000, 0.6447075000, 1.3551006000", \ - "0.2626244000, 0.2695751000, 0.2878427000, 0.3294537000, 0.4213951000, 0.6536290000, 1.3606468000", \ - "0.2819044000, 0.2888523000, 0.3071247000, 0.3487402000, 0.4406880000, 0.6729425000, 1.3800885000", \ - "0.3238097000, 0.3308098000, 0.3492671000, 0.3909036000, 0.4827377000, 0.7148409000, 1.4229128000", \ - "0.4024919000, 0.4097284000, 0.4287529000, 0.4717561000, 0.5649196000, 0.7979647000, 1.5068173000", \ - "0.5181710000, 0.5261363000, 0.5471008000, 0.5942831000, 0.6928232000, 0.9300516000, 1.6380233000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0989808000, 0.1034866000, 0.1145933000, 0.1419831000, 0.1995022000, 0.3355318000, 0.7187358000", \ - "0.0995136000, 0.1033841000, 0.1144439000, 0.1410601000, 0.2008961000, 0.3353965000, 0.7186505000", \ - "0.0995512000, 0.1032058000, 0.1146344000, 0.1417018000, 0.1987394000, 0.3337453000, 0.7192758000", \ - "0.0995441000, 0.1034948000, 0.1142851000, 0.1410874000, 0.2005320000, 0.3359727000, 0.7184470000", \ - "0.0994216000, 0.1038037000, 0.1150644000, 0.1417292000, 0.1991746000, 0.3360403000, 0.7188353000", \ - "0.0992606000, 0.1033392000, 0.1147305000, 0.1414609000, 0.1987398000, 0.3352800000, 0.7184398000", \ - "0.1080008000, 0.1118663000, 0.1244273000, 0.1507662000, 0.2057070000, 0.3394742000, 0.7210442000"); - } - related_pin : "A0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0469551000, 0.0519594000, 0.0652969000, 0.0994962000, 0.1916715000, 0.4906091000, 1.4993743000", \ - "0.0470113000, 0.0519833000, 0.0655467000, 0.0998979000, 0.1914660000, 0.4903976000, 1.4992240000", \ - "0.0472155000, 0.0521812000, 0.0657318000, 0.0995334000, 0.1917506000, 0.4903704000, 1.4988711000", \ - "0.0472526000, 0.0522105000, 0.0657343000, 0.0995292000, 0.1917427000, 0.4902867000, 1.4986310000", \ - "0.0471073000, 0.0519847000, 0.0655843000, 0.0994820000, 0.1911188000, 0.4908888000, 1.5004276000", \ - "0.0503737000, 0.0554980000, 0.0687499000, 0.1030809000, 0.1933486000, 0.4908319000, 1.5004361000", \ - "0.0583347000, 0.0641627000, 0.0784276000, 0.1134466000, 0.2037941000, 0.4970880000, 1.4990237000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5428973000, 0.5508738000, 0.5725146000, 0.6207093000, 0.7151554000, 0.8937675000, 1.2732141000", \ - "0.5474949000, 0.5557050000, 0.5772357000, 0.6253060000, 0.7198838000, 0.8981565000, 1.2776514000", \ - "0.5590380000, 0.5669504000, 0.5885963000, 0.6368642000, 0.7314728000, 0.9099135000, 1.2891772000", \ - "0.5822063000, 0.5902077000, 0.6118564000, 0.6595287000, 0.7541966000, 0.9328983000, 1.3123180000", \ - "0.6305278000, 0.6386015000, 0.6600478000, 0.7082787000, 0.8025898000, 0.9815903000, 1.3607293000", \ - "0.7427013000, 0.7507021000, 0.7723688000, 0.8208352000, 0.9155459000, 1.0941631000, 1.4733841000", \ - "0.9744372000, 0.9827562000, 1.0051369000, 1.0549202000, 1.1526804000, 1.3337258000, 1.7156742000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2554338000, 0.2623564000, 0.2810574000, 0.3231693000, 0.4162795000, 0.6500099000, 1.3595665000", \ - "0.2595898000, 0.2666062000, 0.2852082000, 0.3275401000, 0.4204785000, 0.6542294000, 1.3637419000", \ - "0.2689638000, 0.2760147000, 0.2944528000, 0.3367024000, 0.4298241000, 0.6634305000, 1.3760927000", \ - "0.2897577000, 0.2968700000, 0.3149507000, 0.3577412000, 0.4507734000, 0.6846246000, 1.3954479000", \ - "0.3353829000, 0.3424255000, 0.3610042000, 0.4033631000, 0.4965389000, 0.7304570000, 1.4384275000", \ - "0.4233376000, 0.4306432000, 0.4498588000, 0.4933379000, 0.5873325000, 0.8219387000, 1.5304100000", \ - "0.5590672000, 0.5670750000, 0.5882984000, 0.6358423000, 0.7357892000, 0.9740031000, 1.6856035000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0977586000, 0.1016509000, 0.1126937000, 0.1389133000, 0.1964490000, 0.3318056000, 0.7171592000", \ - "0.0970098000, 0.1010492000, 0.1121661000, 0.1405547000, 0.1975329000, 0.3331771000, 0.7147479000", \ - "0.0975956000, 0.1010350000, 0.1119585000, 0.1404865000, 0.1976751000, 0.3337060000, 0.7147625000", \ - "0.0970658000, 0.1010228000, 0.1122727000, 0.1409137000, 0.1989623000, 0.3319715000, 0.7155654000", \ - "0.0972049000, 0.1012110000, 0.1128933000, 0.1392625000, 0.1994351000, 0.3335263000, 0.7160186000", \ - "0.0969506000, 0.1008754000, 0.1124578000, 0.1405012000, 0.1978075000, 0.3334774000, 0.7158682000", \ - "0.1067427000, 0.1106503000, 0.1224766000, 0.1495116000, 0.2063890000, 0.3388899000, 0.7186013000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0475638000, 0.0527234000, 0.0665765000, 0.1010246000, 0.1927574000, 0.4910136000, 1.5006220000", \ - "0.0476591000, 0.0526626000, 0.0667664000, 0.1007149000, 0.1930144000, 0.4906829000, 1.5005889000", \ - "0.0477833000, 0.0527329000, 0.0663226000, 0.1007498000, 0.1925572000, 0.4911735000, 1.5002575000", \ - "0.0476373000, 0.0526429000, 0.0661894000, 0.1008391000, 0.1929629000, 0.4915956000, 1.5013834000", \ - "0.0483471000, 0.0534559000, 0.0662490000, 0.1007102000, 0.1931016000, 0.4916867000, 1.5010494000", \ - "0.0505355000, 0.0559557000, 0.0700912000, 0.1033093000, 0.1949741000, 0.4924196000, 1.5001997000", \ - "0.0589543000, 0.0645584000, 0.0798678000, 0.1149379000, 0.2049782000, 0.4968996000, 1.5010783000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5485432000, 0.5565149000, 0.5783009000, 0.6268399000, 0.7217823000, 0.9016538000, 1.2823326000", \ - "0.5539315000, 0.5619391000, 0.5836745000, 0.6322532000, 0.7271113000, 0.9069490000, 1.2876842000", \ - "0.5666013000, 0.5744030000, 0.5962917000, 0.6452491000, 0.7397506000, 0.9193593000, 1.3002280000", \ - "0.5910437000, 0.5990358000, 0.6208506000, 0.6693758000, 0.7644050000, 0.9443044000, 1.3249012000", \ - "0.6446087000, 0.6527432000, 0.6742615000, 0.7227596000, 0.8177954000, 0.9977414000, 1.3783266000", \ - "0.7678914000, 0.7759601000, 0.7975431000, 0.8461647000, 0.9409398000, 1.1204320000, 1.5013986000", \ - "1.0244756000, 1.0330625000, 1.0551147000, 1.1052139000, 1.2025760000, 1.3835211000, 1.7664951000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2505740000, 0.2575839000, 0.2757541000, 0.3177299000, 0.4102466000, 0.6439384000, 1.3536222000", \ - "0.2549987000, 0.2618639000, 0.2803054000, 0.3219599000, 0.4144703000, 0.6478728000, 1.3578565000", \ - "0.2639687000, 0.2709443000, 0.2892465000, 0.3312167000, 0.4236026000, 0.6572852000, 1.3655086000", \ - "0.2839054000, 0.2908134000, 0.3089880000, 0.3509335000, 0.4433533000, 0.6768906000, 1.3888503000", \ - "0.3269109000, 0.3338920000, 0.3524062000, 0.3942205000, 0.4866726000, 0.7200303000, 1.4323357000", \ - "0.4100704000, 0.4172731000, 0.4362988000, 0.4794147000, 0.5726820000, 0.8068836000, 1.5167803000", \ - "0.5344710000, 0.5424101000, 0.5634765000, 0.6104126000, 0.7095744000, 0.9470971000, 1.6587842000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0990262000, 0.1031829000, 0.1141751000, 0.1402213000, 0.2008007000, 0.3348032000, 0.7180400000", \ - "0.0984871000, 0.1027018000, 0.1141811000, 0.1403136000, 0.1975898000, 0.3351709000, 0.7179983000", \ - "0.0986890000, 0.1028050000, 0.1139871000, 0.1409416000, 0.1978784000, 0.3331804000, 0.7169176000", \ - "0.0984597000, 0.1029736000, 0.1138309000, 0.1402262000, 0.2003030000, 0.3342279000, 0.7181661000", \ - "0.0984857000, 0.1023804000, 0.1147935000, 0.1405240000, 0.2006229000, 0.3343901000, 0.7183014000", \ - "0.0985979000, 0.1027967000, 0.1141421000, 0.1414536000, 0.1981381000, 0.3327953000, 0.7186963000", \ - "0.1077428000, 0.1110916000, 0.1231668000, 0.1497083000, 0.2047235000, 0.3390741000, 0.7188954000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0473224000, 0.0524061000, 0.0651372000, 0.0993811000, 0.1915290000, 0.4898540000, 1.4975972000", \ - "0.0466698000, 0.0517255000, 0.0654326000, 0.0997361000, 0.1911196000, 0.4897707000, 1.5004009000", \ - "0.0474203000, 0.0517253000, 0.0656599000, 0.0994497000, 0.1914597000, 0.4900421000, 1.5046079000", \ - "0.0468260000, 0.0516672000, 0.0657222000, 0.0990894000, 0.1912815000, 0.4909314000, 1.4991518000", \ - "0.0469191000, 0.0517940000, 0.0654025000, 0.0991787000, 0.1909429000, 0.4909693000, 1.4990499000", \ - "0.0494596000, 0.0544212000, 0.0678397000, 0.1025037000, 0.1928901000, 0.4902329000, 1.5040785000", \ - "0.0575734000, 0.0629993000, 0.0780151000, 0.1124390000, 0.2036215000, 0.4965687000, 1.4983740000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5573597000, 0.5654886000, 0.5874113000, 0.6357712000, 0.7309938000, 0.9115900000, 1.2932240000", \ - "0.5623915000, 0.5705902000, 0.5923388000, 0.6409193000, 0.7362236000, 0.9168338000, 1.2980357000", \ - "0.5748436000, 0.5829650000, 0.6046650000, 0.6533674000, 0.7489377000, 0.9293398000, 1.3105336000", \ - "0.5997535000, 0.6078032000, 0.6295693000, 0.6781374000, 0.7735474000, 0.9538896000, 1.3354049000", \ - "0.6522932000, 0.6603584000, 0.6816943000, 0.7304686000, 0.8256784000, 1.0062082000, 1.3877940000", \ - "0.7719122000, 0.7797381000, 0.8017769000, 0.8504589000, 0.9455512000, 1.1257106000, 1.5074717000", \ - "1.0241471000, 1.0325233000, 1.0561564000, 1.1065977000, 1.2041450000, 1.3843912000, 1.7686359000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2515601000, 0.2585706000, 0.2768004000, 0.3190225000, 0.4116030000, 0.6453398000, 1.3556201000", \ - "0.2557357000, 0.2628216000, 0.2810775000, 0.3229994000, 0.4156875000, 0.6490753000, 1.3616978000", \ - "0.2647048000, 0.2716448000, 0.2899092000, 0.3320278000, 0.4246108000, 0.6583004000, 1.3696418000", \ - "0.2849865000, 0.2919192000, 0.3102252000, 0.3523164000, 0.4448885000, 0.6786396000, 1.3892459000", \ - "0.3287904000, 0.3357387000, 0.3543026000, 0.3962963000, 0.4889769000, 0.7223158000, 1.4319945000", \ - "0.4125204000, 0.4197661000, 0.4386356000, 0.4818808000, 0.5755352000, 0.8096108000, 1.5198441000", \ - "0.5371828000, 0.5451249000, 0.5661226000, 0.6132568000, 0.7123904000, 0.9503999000, 1.6593404000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0992834000, 0.1032710000, 0.1144458000, 0.1434821000, 0.2011154000, 0.3370172000, 0.7190256000", \ - "0.0992078000, 0.1032051000, 0.1149868000, 0.1409148000, 0.2013284000, 0.3355572000, 0.7193779000", \ - "0.0996637000, 0.1029081000, 0.1145298000, 0.1409313000, 0.2004030000, 0.3357639000, 0.7193915000", \ - "0.0990876000, 0.1033603000, 0.1155268000, 0.1436456000, 0.2002433000, 0.3361278000, 0.7190846000", \ - "0.0999311000, 0.1036206000, 0.1153993000, 0.1415178000, 0.1986420000, 0.3364885000, 0.7191500000", \ - "0.0993143000, 0.1031455000, 0.1140970000, 0.1427899000, 0.2017309000, 0.3344065000, 0.7178080000", \ - "0.1083316000, 0.1121399000, 0.1237216000, 0.1515321000, 0.2053572000, 0.3401121000, 0.7223800000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0476104000, 0.0519601000, 0.0654048000, 0.0998380000, 0.1919203000, 0.4905004000, 1.5030495000", \ - "0.0469315000, 0.0519870000, 0.0654058000, 0.0997569000, 0.1914997000, 0.4911819000, 1.4999613000", \ - "0.0469520000, 0.0518231000, 0.0652386000, 0.0993248000, 0.1919089000, 0.4911620000, 1.5003885000", \ - "0.0470131000, 0.0518871000, 0.0654565000, 0.0997752000, 0.1919921000, 0.4907146000, 1.5022807000", \ - "0.0471652000, 0.0521575000, 0.0655642000, 0.0998023000, 0.1918240000, 0.4904230000, 1.5002335000", \ - "0.0497500000, 0.0548559000, 0.0692212000, 0.1032016000, 0.1934511000, 0.4906433000, 1.5006104000", \ - "0.0587023000, 0.0632265000, 0.0775384000, 0.1138971000, 0.2037235000, 0.4959212000, 1.4993180000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5121706000, 0.5201456000, 0.5420202000, 0.5906303000, 0.6854906000, 0.8652397000, 1.2461058000", \ - "0.5161833000, 0.5244037000, 0.5461788000, 0.5946413000, 0.6898958000, 0.8692166000, 1.2500865000", \ - "0.5275998000, 0.5355978000, 0.5575171000, 0.6060903000, 0.7011410000, 0.8811805000, 1.2615338000", \ - "0.5558211000, 0.5639941000, 0.5857861000, 0.6342440000, 0.7294703000, 0.9087816000, 1.2896971000", \ - "0.6242994000, 0.6323159000, 0.6541964000, 0.7027128000, 0.7976392000, 0.9774082000, 1.3582757000", \ - "0.7882584000, 0.7963067000, 0.8180716000, 0.8666673000, 0.9614508000, 1.1412998000, 1.5221199000", \ - "1.1536195000, 1.1618597000, 1.1842217000, 1.2342982000, 1.3308822000, 1.5120283000, 1.8939266000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2379060000, 0.2449986000, 0.2635590000, 0.3062159000, 0.3995884000, 0.6337639000, 1.3438068000", \ - "0.2420492000, 0.2490355000, 0.2676342000, 0.3102909000, 0.4035980000, 0.6375671000, 1.3498428000", \ - "0.2516542000, 0.2586485000, 0.2772703000, 0.3199239000, 0.4132514000, 0.6472433000, 1.3600503000", \ - "0.2734779000, 0.2805861000, 0.2992180000, 0.3419789000, 0.4351437000, 0.6695121000, 1.3788412000", \ - "0.3200286000, 0.3271289000, 0.3458435000, 0.3885113000, 0.4815457000, 0.7155750000, 1.4271626000", \ - "0.4034784000, 0.4110078000, 0.4305132000, 0.4746656000, 0.5693622000, 0.8042235000, 1.5125746000", \ - "0.5101153000, 0.5187124000, 0.5413368000, 0.5914922000, 0.6933069000, 0.9319467000, 1.6413890000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0984830000, 0.1023337000, 0.1132889000, 0.1418145000, 0.1977302000, 0.3336920000, 0.7174669000", \ - "0.0984066000, 0.1023550000, 0.1135778000, 0.1417658000, 0.1989325000, 0.3341327000, 0.7169450000", \ - "0.0985103000, 0.1023927000, 0.1133647000, 0.1420813000, 0.1996848000, 0.3345448000, 0.7182264000", \ - "0.0984249000, 0.1023209000, 0.1136024000, 0.1416653000, 0.1988512000, 0.3345944000, 0.7162470000", \ - "0.0988662000, 0.1026823000, 0.1137436000, 0.1402421000, 0.1976997000, 0.3356329000, 0.7176458000", \ - "0.0984897000, 0.1022963000, 0.1134288000, 0.1402413000, 0.1975929000, 0.3350070000, 0.7180846000", \ - "0.1118158000, 0.1146486000, 0.1261592000, 0.1510180000, 0.2055067000, 0.3375440000, 0.7180009000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0483420000, 0.0532956000, 0.0668493000, 0.1014615000, 0.1936424000, 0.4919009000, 1.5007967000", \ - "0.0485060000, 0.0537219000, 0.0668685000, 0.1012875000, 0.1932437000, 0.4921705000, 1.4997229000", \ - "0.0483729000, 0.0538755000, 0.0668881000, 0.1013273000, 0.1931205000, 0.4917372000, 1.5003205000", \ - "0.0490991000, 0.0542059000, 0.0671286000, 0.1012499000, 0.1934002000, 0.4909883000, 1.5049573000", \ - "0.0482958000, 0.0532512000, 0.0670356000, 0.1010479000, 0.1933714000, 0.4921922000, 1.5004646000", \ - "0.0525279000, 0.0578023000, 0.0712270000, 0.1058941000, 0.1956963000, 0.4919554000, 1.5003844000", \ - "0.0680371000, 0.0726095000, 0.0875027000, 0.1216774000, 0.2092825000, 0.4991863000, 1.4970905000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.5805124000, 0.5887047000, 0.6099876000, 0.6581308000, 0.7526157000, 0.9309686000, 1.3104148000", \ - "0.5851276000, 0.5932020000, 0.6146840000, 0.6630533000, 0.7571532000, 0.9357112000, 1.3151955000", \ - "0.5958687000, 0.6038625000, 0.6252134000, 0.6733009000, 0.7678424000, 0.9462388000, 1.3256128000", \ - "0.6174997000, 0.6255823000, 0.6469600000, 0.6952536000, 0.7895010000, 0.9683446000, 1.3475295000", \ - "0.6527852000, 0.6604666000, 0.6819999000, 0.7302020000, 0.8247181000, 1.0031260000, 1.3826094000", \ - "0.6980547000, 0.7058461000, 0.7275592000, 0.7758782000, 0.8700487000, 1.0488721000, 1.4279917000", \ - "0.7437503000, 0.7517127000, 0.7734029000, 0.8215776000, 0.9157951000, 1.0949091000, 1.4737264000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.3513580000, 0.3583886000, 0.3765095000, 0.4182641000, 0.5101035000, 0.7423015000, 1.4530138000", \ - "0.3548574000, 0.3618115000, 0.3799623000, 0.4217084000, 0.5136843000, 0.7460260000, 1.4532390000", \ - "0.3662779000, 0.3731943000, 0.3914481000, 0.4331181000, 0.5250261000, 0.7571502000, 1.4683180000", \ - "0.3967879000, 0.4037522000, 0.4220055000, 0.4635239000, 0.5554211000, 0.7873728000, 1.4959578000", \ - "0.4668939000, 0.4739642000, 0.4920727000, 0.5338242000, 0.6256726000, 0.8578237000, 1.5689336000", \ - "0.5907985000, 0.5977948000, 0.6159740000, 0.6578396000, 0.7499263000, 0.9823650000, 1.6914922000", \ - "0.7885052000, 0.7955018000, 0.8138561000, 0.8558544000, 0.9479749000, 1.1804466000, 1.8880477000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0973668000, 0.1010683000, 0.1121474000, 0.1402325000, 0.1973108000, 0.3327193000, 0.7140500000", \ - "0.0972516000, 0.1014378000, 0.1133132000, 0.1396784000, 0.1968433000, 0.3319808000, 0.7171340000", \ - "0.0972646000, 0.1013330000, 0.1134348000, 0.1400774000, 0.1974211000, 0.3336180000, 0.7139791000", \ - "0.0972729000, 0.1013724000, 0.1133385000, 0.1396519000, 0.1964611000, 0.3331392000, 0.7156041000", \ - "0.0973321000, 0.1009392000, 0.1128541000, 0.1400788000, 0.1972145000, 0.3330000000, 0.7149964000", \ - "0.0967812000, 0.1011234000, 0.1124967000, 0.1398277000, 0.1969314000, 0.3315646000, 0.7155690000", \ - "0.0970228000, 0.1007721000, 0.1123227000, 0.1386591000, 0.1959538000, 0.3320772000, 0.7162096000"); - } - related_pin : "S0"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0469688000, 0.0520825000, 0.0658963000, 0.0992585000, 0.1913915000, 0.4907778000, 1.4992044000", \ - "0.0471620000, 0.0521362000, 0.0654074000, 0.0995629000, 0.1918583000, 0.4906146000, 1.5036581000", \ - "0.0469966000, 0.0519992000, 0.0658777000, 0.0994450000, 0.1913365000, 0.4908839000, 1.4993952000", \ - "0.0470551000, 0.0520218000, 0.0656066000, 0.0998412000, 0.1912286000, 0.4905348000, 1.5003194000", \ - "0.0470699000, 0.0520334000, 0.0659311000, 0.0993041000, 0.1913800000, 0.4908840000, 1.4995719000", \ - "0.0474789000, 0.0524546000, 0.0664788000, 0.0997582000, 0.1917778000, 0.4897115000, 1.5027576000", \ - "0.0475758000, 0.0524572000, 0.0660360000, 0.1000754000, 0.1919969000, 0.4896913000, 1.4983227000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.3684631000, 0.3764960000, 0.3979629000, 0.4463234000, 0.5410458000, 0.7190574000, 1.0982670000", \ - "0.3732305000, 0.3812288000, 0.4027030000, 0.4515127000, 0.5456452000, 0.7241150000, 1.1033550000", \ - "0.3846229000, 0.3926513000, 0.4142892000, 0.4625904000, 0.5570647000, 0.7355476000, 1.1147356000", \ - "0.4099107000, 0.4182103000, 0.4390656000, 0.4878451000, 0.5823684000, 0.7606208000, 1.1397695000", \ - "0.4604675000, 0.4684543000, 0.4900820000, 0.5380756000, 0.6318703000, 0.8099232000, 1.1887795000", \ - "0.5586677000, 0.5663335000, 0.5869422000, 0.6343909000, 0.7282115000, 0.9063691000, 1.2847322000", \ - "0.7407149000, 0.7503569000, 0.7770291000, 0.8365106000, 0.9476453000, 1.1385177000, 1.5231886000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.1972775000, 0.2042434000, 0.2224734000, 0.2644189000, 0.3571481000, 0.5908089000, 1.2987882000", \ - "0.2018193000, 0.2087730000, 0.2270716000, 0.2691273000, 0.3617407000, 0.5954073000, 1.3053346000", \ - "0.2125655000, 0.2195158000, 0.2378255000, 0.2798421000, 0.3724955000, 0.6061655000, 1.3159970000", \ - "0.2358631000, 0.2428487000, 0.2611078000, 0.3031836000, 0.3956848000, 0.6293636000, 1.3399245000", \ - "0.2885309000, 0.2954319000, 0.3138122000, 0.3557144000, 0.4481374000, 0.6816830000, 1.3907584000", \ - "0.3881289000, 0.3957237000, 0.4155427000, 0.4593206000, 0.5536476000, 0.7877020000, 1.4970167000", \ - "0.5117517000, 0.5208267000, 0.5444580000, 0.5988899000, 0.7018885000, 0.9406557000, 1.6512788000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0970360000, 0.1011398000, 0.1125044000, 0.1398213000, 0.1973053000, 0.3322315000, 0.7144795000", \ - "0.0967904000, 0.1006115000, 0.1121173000, 0.1391459000, 0.1959684000, 0.3312021000, 0.7160231000", \ - "0.0965214000, 0.1005839000, 0.1119965000, 0.1386211000, 0.1959026000, 0.3315931000, 0.7159767000", \ - "0.0966297000, 0.1007823000, 0.1116687000, 0.1395448000, 0.1974868000, 0.3317107000, 0.7139035000", \ - "0.0958132000, 0.0995276000, 0.1110401000, 0.1390009000, 0.1951253000, 0.3330721000, 0.7169447000", \ - "0.0943492000, 0.0980138000, 0.1094639000, 0.1375203000, 0.1958520000, 0.3314085000, 0.7153285000", \ - "0.1362910000, 0.1406157000, 0.1532968000, 0.1814084000, 0.2348895000, 0.3532021000, 0.7260781000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0467619000, 0.0517799000, 0.0653682000, 0.0996888000, 0.1918664000, 0.4904899000, 1.5041840000", \ - "0.0467602000, 0.0516693000, 0.0651784000, 0.0994778000, 0.1916894000, 0.4899377000, 1.5028581000", \ - "0.0467695000, 0.0516312000, 0.0651451000, 0.0995040000, 0.1916374000, 0.4898018000, 1.5030897000", \ - "0.0474663000, 0.0517502000, 0.0652679000, 0.0994730000, 0.1916752000, 0.4905542000, 1.5013997000", \ - "0.0469262000, 0.0522847000, 0.0654615000, 0.0991332000, 0.1918414000, 0.4902024000, 1.4981347000", \ - "0.0565530000, 0.0612615000, 0.0743080000, 0.1077864000, 0.1962574000, 0.4912092000, 1.4979072000", \ - "0.0802014000, 0.0856863000, 0.1007347000, 0.1329693000, 0.2158331000, 0.4999316000, 1.4987472000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.3727901000, 0.3807739000, 0.4021517000, 0.4511168000, 0.5460207000, 0.7254419000, 1.1061942000", \ - "0.3775511000, 0.3856703000, 0.4073599000, 0.4557785000, 0.5510659000, 0.7304555000, 1.1109171000", \ - "0.3873420000, 0.3953704000, 0.4172272000, 0.4656600000, 0.5606260000, 0.7402546000, 1.1209490000", \ - "0.4029560000, 0.4109791000, 0.4328304000, 0.4807748000, 0.5765028000, 0.7557155000, 1.1363591000", \ - "0.4414118000, 0.4496717000, 0.4708109000, 0.5196873000, 0.6140474000, 0.7929790000, 1.1731929000", \ - "0.5318567000, 0.5393509000, 0.5593836000, 0.6059261000, 0.6977529000, 0.8760790000, 1.2560144000", \ - "0.5733803000, 0.5808036000, 0.6007658000, 0.6463844000, 0.7381908000, 0.9147809000, 1.2928626000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.2321873000, 0.2392265000, 0.2576233000, 0.2999153000, 0.3930219000, 0.6269718000, 1.3357022000", \ - "0.2371776000, 0.2442259000, 0.2626840000, 0.3051053000, 0.3980512000, 0.6319433000, 1.3426267000", \ - "0.2506571000, 0.2575477000, 0.2761578000, 0.3184019000, 0.4114966000, 0.6453003000, 1.3553616000", \ - "0.2824263000, 0.2894502000, 0.3079109000, 0.3501938000, 0.4433352000, 0.6772250000, 1.3874688000", \ - "0.3448780000, 0.3518921000, 0.3704197000, 0.4128421000, 0.5058229000, 0.7397106000, 1.4501099000", \ - "0.4411733000, 0.4480209000, 0.4666840000, 0.5087811000, 0.6013815000, 0.8354777000, 1.5436507000", \ - "0.5865157000, 0.5935230000, 0.6119890000, 0.6542079000, 0.7471972000, 0.9808065000, 1.6893158000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0987711000, 0.1026943000, 0.1140286000, 0.1403304000, 0.1976599000, 0.3332440000, 0.7163408000", \ - "0.0984409000, 0.1021570000, 0.1134987000, 0.1416539000, 0.1990793000, 0.3350208000, 0.7179595000", \ - "0.0986598000, 0.1023688000, 0.1139129000, 0.1401704000, 0.1974618000, 0.3354041000, 0.7175558000", \ - "0.0983322000, 0.1020763000, 0.1134494000, 0.1412994000, 0.1991155000, 0.3336067000, 0.7171518000", \ - "0.0968571000, 0.1012290000, 0.1124194000, 0.1400077000, 0.1996522000, 0.3326226000, 0.7163340000", \ - "0.0890235000, 0.0928914000, 0.1055123000, 0.1338914000, 0.1945209000, 0.3319612000, 0.7172392000", \ - "0.0920165000, 0.0957552000, 0.1066869000, 0.1356184000, 0.1956591000, 0.3306008000, 0.7134526000"); - } - related_pin : "S1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016056800, 0.0051564200, 0.0165591000, 0.0531774000, 0.1707720000, 0.5484110000"); - values("0.0475522000, 0.0526313000, 0.0668002000, 0.1008121000, 0.1929071000, 0.4912891000, 1.4990647000", \ - "0.0481717000, 0.0526717000, 0.0661154000, 0.1004905000, 0.1927340000, 0.4911678000, 1.5019113000", \ - "0.0474764000, 0.0526596000, 0.0665279000, 0.1003893000, 0.1928620000, 0.4915859000, 1.5003681000", \ - "0.0480121000, 0.0529271000, 0.0661927000, 0.1005322000, 0.1925249000, 0.4904394000, 1.5027490000", \ - "0.0481086000, 0.0524583000, 0.0661331000, 0.1004494000, 0.1926961000, 0.4908286000, 1.5023349000", \ - "0.0473045000, 0.0527858000, 0.0662114000, 0.0992050000, 0.1922173000, 0.4916154000, 1.5037137000", \ - "0.0482327000, 0.0532602000, 0.0666075000, 0.1005823000, 0.1928837000, 0.4898353000, 1.4933181000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2_1") { - leakage_power () { - value : 0.0002796000; - when : "!A&B"; - } - leakage_power () { - value : 3.005879e-05; - when : "!A&!B"; - } - leakage_power () { - value : 0.0079423000; - when : "A&B"; - } - leakage_power () { - value : 0.0002199000; - when : "A&!B"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__nand2"; - cell_leakage_power : 0.0021179600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047914000, 0.0048016000, 0.0048250000, 0.0048257000, 0.0048275000, 0.0048316000, 0.0048409000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003895500, -0.003894100, -0.003890900, -0.003884500, -0.003869900, -0.003836300, -0.003758800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023750000; - } - pin ("B") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041316000, 0.0041310000, 0.0041296000, 0.0041311000, 0.0041345000, 0.0041424000, 0.0041606000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004132500, -0.004132200, -0.004131700, -0.004131700, -0.004131700, -0.004131700, -0.004131700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024280000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0021930000, 0.0009877000, -0.002368500, -0.011438400, -0.035540500, -0.099111900, -0.266552000", \ - "0.0019150000, 0.0007341000, -0.002546500, -0.011530000, -0.035576100, -0.099127900, -0.266536000", \ - "0.0016812000, 0.0004745000, -0.002798000, -0.011703200, -0.035666500, -0.099159300, -0.266586400", \ - "0.0015598000, 0.0003119000, -0.003061200, -0.011898200, -0.035827100, -0.099232400, -0.266584100", \ - "0.0017783000, 0.0004552000, -0.003119600, -0.012139600, -0.036038600, -0.099390900, -0.266687900", \ - "0.0027861000, 0.0013388000, -0.002282800, -0.011885500, -0.035881700, -0.099359200, -0.266693000", \ - "0.0048177000, 0.0033845000, -0.000672800, -0.010464500, -0.034922800, -0.099271800, -0.266154600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0037314000, 0.0052286000, 0.0089009000, 0.0181829000, 0.0422231000, 0.1054610000, 0.2726763000", \ - "0.0034187000, 0.0049127000, 0.0086510000, 0.0180038000, 0.0420756000, 0.1055726000, 0.2714830000", \ - "0.0032277000, 0.0046497000, 0.0082120000, 0.0177886000, 0.0417785000, 0.1040326000, 0.2704122000", \ - "0.0032360000, 0.0045693000, 0.0081208000, 0.0173876000, 0.0416048000, 0.1050550000, 0.2705313000", \ - "0.0034249000, 0.0046908000, 0.0081153000, 0.0172295000, 0.0413235000, 0.1040842000, 0.2697601000", \ - "0.0045563000, 0.0054145000, 0.0088138000, 0.0176135000, 0.0414409000, 0.1039098000, 0.2701764000", \ - "0.0064050000, 0.0076344000, 0.0107086000, 0.0190730000, 0.0427296000, 0.1054309000, 0.2720940000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0025427000, 0.0012996000, -0.002084300, -0.011195900, -0.035311000, -0.098872400, -0.266309200", \ - "0.0023156000, 0.0011047000, -0.002234800, -0.011266700, -0.035342900, -0.098887700, -0.266309300", \ - "0.0020560000, 0.0008378000, -0.002451900, -0.011410700, -0.035404100, -0.098922900, -0.266317900", \ - "0.0018599000, 0.0006250000, -0.002710600, -0.011640800, -0.035542500, -0.098979300, -0.266340400", \ - "0.0019574000, 0.0006497000, -0.002753200, -0.011862900, -0.035739500, -0.099096800, -0.266445600", \ - "0.0023066000, 0.0009468000, -0.002586700, -0.011744600, -0.035877200, -0.099238000, -0.266451100", \ - "0.0040502000, 0.0025270000, -0.001336900, -0.010911200, -0.035353400, -0.099135500, -0.266482500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013165470, 0.0034665930, 0.0091278680, 0.0240345400, 0.0632852100, 0.1666359000"); - values("0.0069497000, 0.0083090000, 0.0118392000, 0.0209668000, 0.0448440000, 0.1075803000, 0.2723604000", \ - "0.0067527000, 0.0081352000, 0.0116717000, 0.0208073000, 0.0447328000, 0.1075189000, 0.2726214000", \ - "0.0064834000, 0.0079083000, 0.0114938000, 0.0207418000, 0.0446096000, 0.1072483000, 0.2725577000", \ - "0.0064612000, 0.0078038000, 0.0113248000, 0.0204341000, 0.0444926000, 0.1074404000, 0.2721664000", \ - "0.0066367000, 0.0079137000, 0.0113830000, 0.0204016000, 0.0444885000, 0.1066676000, 0.2712178000", \ - "0.0071356000, 0.0083861000, 0.0116437000, 0.0209430000, 0.0444210000, 0.1060977000, 0.2708233000", \ - "0.0095357000, 0.0113323000, 0.0147721000, 0.0224804000, 0.0464461000, 0.1074965000, 0.2734130000"); - } - } - max_capacitance : 0.1666360000; - max_transition : 1.4963760000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0206305000, 0.0250594000, 0.0363371000, 0.0651531000, 0.1403625000, 0.3379392000, 0.8628026000", \ - "0.0243797000, 0.0289316000, 0.0403352000, 0.0696727000, 0.1447142000, 0.3426395000, 0.8633784000", \ - "0.0327052000, 0.0384095000, 0.0504824000, 0.0797753000, 0.1551681000, 0.3529022000, 0.8773479000", \ - "0.0428315000, 0.0514229000, 0.0698132000, 0.1038626000, 0.1794323000, 0.3766826000, 0.8969099000", \ - "0.0525334000, 0.0659547000, 0.0937839000, 0.1461446000, 0.2370110000, 0.4342275000, 0.9573758000", \ - "0.0550564000, 0.0754976000, 0.1173683000, 0.1976946000, 0.3328764000, 0.5653441000, 1.0820946000", \ - "0.0332144000, 0.0632894000, 0.1271843000, 0.2473768000, 0.4578195000, 0.8093176000, 1.3854335000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0240063000, 0.0297255000, 0.0438504000, 0.0795463000, 0.1715528000, 0.4137325000, 1.0495054000", \ - "0.0289988000, 0.0346509000, 0.0487512000, 0.0844679000, 0.1772878000, 0.4204850000, 1.0572072000", \ - "0.0420366000, 0.0477456000, 0.0612167000, 0.0970882000, 0.1885427000, 0.4287654000, 1.0789833000", \ - "0.0629112000, 0.0724855000, 0.0913957000, 0.1279769000, 0.2206074000, 0.4624459000, 1.0904021000", \ - "0.0945378000, 0.1099490000, 0.1410190000, 0.1966647000, 0.2916911000, 0.5313731000, 1.1659407000", \ - "0.1452155000, 0.1690215000, 0.2179952000, 0.3063044000, 0.4550610000, 0.7010251000, 1.3242337000", \ - "0.2320864000, 0.2668832000, 0.3375273000, 0.4781309000, 0.7110746000, 1.0824839000, 1.7181800000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0143751000, 0.0198544000, 0.0342729000, 0.0724393000, 0.1726079000, 0.4374054000, 1.1358902000", \ - "0.0145368000, 0.0198407000, 0.0345439000, 0.0723585000, 0.1723529000, 0.4350408000, 1.1268473000", \ - "0.0201271000, 0.0243951000, 0.0360804000, 0.0721914000, 0.1724084000, 0.4396732000, 1.1359822000", \ - "0.0312488000, 0.0374144000, 0.0503344000, 0.0798062000, 0.1744425000, 0.4360109000, 1.1384014000", \ - "0.0516999000, 0.0605678000, 0.0793523000, 0.1147933000, 0.1905170000, 0.4379490000, 1.1324792000", \ - "0.0872036000, 0.1004496000, 0.1294284000, 0.1812328000, 0.2757691000, 0.4747423000, 1.1319222000", \ - "0.1511015000, 0.1709510000, 0.2164908000, 0.2924142000, 0.4307443000, 0.6664593000, 1.2073347000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0177745000, 0.0249474000, 0.0439057000, 0.0938566000, 0.2253318000, 0.5702676000, 1.4819062000", \ - "0.0177772000, 0.0249766000, 0.0438372000, 0.0936947000, 0.2257364000, 0.5698652000, 1.4800936000", \ - "0.0222987000, 0.0275231000, 0.0441973000, 0.0935905000, 0.2250331000, 0.5661273000, 1.4720122000", \ - "0.0371093000, 0.0432567000, 0.0558207000, 0.0963630000, 0.2242809000, 0.5701420000, 1.4678687000", \ - "0.0621296000, 0.0713724000, 0.0906731000, 0.1273404000, 0.2318113000, 0.5676693000, 1.4793876000", \ - "0.1010294000, 0.1167905000, 0.1495524000, 0.2053604000, 0.3035009000, 0.5787597000, 1.4755684000", \ - "0.1675207000, 0.1948717000, 0.2425694000, 0.3349839000, 0.4854143000, 0.7358355000, 1.4963760000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0249171000, 0.0293153000, 0.0405828000, 0.0698819000, 0.1449331000, 0.3421441000, 0.8628038000", \ - "0.0289195000, 0.0334123000, 0.0447040000, 0.0736592000, 0.1489819000, 0.3498721000, 0.8727723000", \ - "0.0371437000, 0.0422262000, 0.0539688000, 0.0833453000, 0.1595860000, 0.3563234000, 0.8763164000", \ - "0.0489818000, 0.0563682000, 0.0720499000, 0.1048230000, 0.1812728000, 0.3791143000, 0.9050736000", \ - "0.0618681000, 0.0734889000, 0.0976455000, 0.1439502000, 0.2319962000, 0.4309580000, 0.9541561000", \ - "0.0681193000, 0.0868404000, 0.1254586000, 0.1972257000, 0.3221010000, 0.5490411000, 1.0729806000", \ - "0.0516367000, 0.0794927000, 0.1402303000, 0.2530506000, 0.4456706000, 0.7654773000, 1.3452001000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0314335000, 0.0367492000, 0.0504271000, 0.0855896000, 0.1771391000, 0.4171834000, 1.0486217000", \ - "0.0366510000, 0.0420007000, 0.0555974000, 0.0906578000, 0.1822921000, 0.4226315000, 1.0537489000", \ - "0.0496344000, 0.0552493000, 0.0689263000, 0.1041672000, 0.1948095000, 0.4349560000, 1.0664511000", \ - "0.0764485000, 0.0839915000, 0.1002800000, 0.1354751000, 0.2270771000, 0.4675205000, 1.0956603000", \ - "0.1179990000, 0.1300048000, 0.1559456000, 0.2058038000, 0.2993580000, 0.5374151000, 1.1674532000", \ - "0.1820919000, 0.2009641000, 0.2425259000, 0.3235598000, 0.4618716000, 0.7024087000, 1.3293885000", \ - "0.2872291000, 0.3144594000, 0.3778534000, 0.5040435000, 0.7292905000, 1.0858007000, 1.7218809000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0143837000, 0.0198933000, 0.0343693000, 0.0728649000, 0.1721484000, 0.4353723000, 1.1278795000", \ - "0.0144473000, 0.0199313000, 0.0343100000, 0.0724451000, 0.1721519000, 0.4389184000, 1.1310675000", \ - "0.0174452000, 0.0219472000, 0.0352071000, 0.0731724000, 0.1748237000, 0.4359115000, 1.1295511000", \ - "0.0264352000, 0.0316231000, 0.0440914000, 0.0764118000, 0.1747762000, 0.4364655000, 1.1456923000", \ - "0.0447879000, 0.0516863000, 0.0670188000, 0.1004151000, 0.1848698000, 0.4368550000, 1.1325847000", \ - "0.0791932000, 0.0891027000, 0.1107220000, 0.1538412000, 0.2429680000, 0.4620836000, 1.1412313000", \ - "0.1436275000, 0.1568697000, 0.1875469000, 0.2503348000, 0.3659521000, 0.5934254000, 1.1799060000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013165500, 0.0034665900, 0.0091278700, 0.0240345000, 0.0632852000, 0.1666360000"); - values("0.0241903000, 0.0313734000, 0.0500101000, 0.0993460000, 0.2291821000, 0.5699834000, 1.4686290000", \ - "0.0241965000, 0.0313595000, 0.0501164000, 0.0992997000, 0.2290979000, 0.5700846000, 1.4677114000", \ - "0.0261318000, 0.0322598000, 0.0500219000, 0.0994030000, 0.2291394000, 0.5705483000, 1.4705132000", \ - "0.0397762000, 0.0454874000, 0.0590114000, 0.1013268000, 0.2291905000, 0.5706875000, 1.4728638000", \ - "0.0654496000, 0.0745571000, 0.0933218000, 0.1284161000, 0.2362834000, 0.5703250000, 1.4725746000", \ - "0.1078965000, 0.1228889000, 0.1530385000, 0.2070083000, 0.3018776000, 0.5851778000, 1.4702581000", \ - "0.1734774000, 0.1969473000, 0.2479368000, 0.3391057000, 0.4880620000, 0.7299975000, 1.4910937000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2_2") { - leakage_power () { - value : 0.0007598000; - when : "!A&B"; - } - leakage_power () { - value : 0.0010743000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0074091000; - when : "A&B"; - } - leakage_power () { - value : 0.0005953000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nand2"; - cell_leakage_power : 0.0024596230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0044310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092837000, 0.0092804000, 0.0092728000, 0.0092766000, 0.0092853000, 0.0093054000, 0.0093516000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006470300, -0.006486800, -0.006524800, -0.006507100, -0.006466400, -0.006372600, -0.006156300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045570000; - } - pin ("B") { - capacitance : 0.0044180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079109000, 0.0079053000, 0.0078925000, 0.0078915000, 0.0078893000, 0.0078841000, 0.0078723000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007885100, -0.007879200, -0.007865700, -0.007865000, -0.007863500, -0.007860200, -0.007852300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046210000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0043000000, 0.0029365000, -0.001242600, -0.013895200, -0.051140000, -0.159390100, -0.473114400", \ - "0.0037984000, 0.0024775000, -0.001598600, -0.014100500, -0.051210800, -0.159402100, -0.473102800", \ - "0.0033323000, 0.0019714000, -0.002102400, -0.014436500, -0.051372100, -0.159429300, -0.473063200", \ - "0.0031747000, 0.0016346000, -0.002561700, -0.014931500, -0.051730800, -0.159599100, -0.473090800", \ - "0.0033215000, 0.0017641000, -0.002661700, -0.015264300, -0.052092400, -0.159851400, -0.473266200", \ - "0.0049827000, 0.0033121000, -0.001412900, -0.014471500, -0.052114500, -0.160174200, -0.473494700", \ - "0.0089544000, 0.0069929000, 0.0020048000, -0.012238700, -0.050480200, -0.159363900, -0.473459900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0051695000, 0.0069984000, 0.0119347000, 0.0250587000, 0.0627718000, 0.1685942000, 0.4799906000", \ - "0.0046728000, 0.0064591000, 0.0114415000, 0.0248384000, 0.0624139000, 0.1699517000, 0.4772817000", \ - "0.0043712000, 0.0060143000, 0.0108481000, 0.0241225000, 0.0618879000, 0.1700678000, 0.4772038000", \ - "0.0043965000, 0.0059780000, 0.0105570000, 0.0234968000, 0.0612702000, 0.1700221000, 0.4829393000", \ - "0.0047997000, 0.0062809000, 0.0106162000, 0.0234145000, 0.0607981000, 0.1671371000, 0.4784243000", \ - "0.0062127000, 0.0074318000, 0.0116096000, 0.0247757000, 0.0616678000, 0.1680576000, 0.4811337000", \ - "0.0105457000, 0.0112672000, 0.0154959000, 0.0269047000, 0.0629195000, 0.1701047000, 0.4813517000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0058741000, 0.0044654000, 0.0001872000, -0.012570400, -0.049857400, -0.158106400, -0.471821800", \ - "0.0054251000, 0.0040485000, -0.000127400, -0.012740600, -0.049939700, -0.158144600, -0.471836600", \ - "0.0049507000, 0.0035509000, -0.000587100, -0.013050400, -0.050094300, -0.158215100, -0.471859200", \ - "0.0045877000, 0.0031407000, -0.001064400, -0.013498800, -0.050362000, -0.158335000, -0.471850300", \ - "0.0048410000, 0.0033569000, -0.000985000, -0.013809200, -0.050682700, -0.158482300, -0.471938700", \ - "0.0052693000, 0.0036834000, -0.000826400, -0.013709700, -0.051069100, -0.158850000, -0.472175300", \ - "0.0081106000, 0.0063356000, 0.0013643000, -0.012220600, -0.050128400, -0.158734000, -0.472253000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014486260, 0.0041970370, 0.0121598800, 0.0352302400, 0.1020709000, 0.2957252000"); - values("0.0131740000, 0.0147706000, 0.0193188000, 0.0322856000, 0.0692454000, 0.1761525000, 0.4850417000", \ - "0.0126719000, 0.0143115000, 0.0188792000, 0.0319361000, 0.0691396000, 0.1762759000, 0.4854702000", \ - "0.0122513000, 0.0138694000, 0.0183436000, 0.0315773000, 0.0688111000, 0.1762427000, 0.4850414000", \ - "0.0121634000, 0.0136488000, 0.0180699000, 0.0312011000, 0.0682199000, 0.1757919000, 0.4856277000", \ - "0.0122867000, 0.0138020000, 0.0182162000, 0.0310540000, 0.0681211000, 0.1750580000, 0.4836663000", \ - "0.0138289000, 0.0153922000, 0.0196239000, 0.0326541000, 0.0691547000, 0.1757100000, 0.4841492000", \ - "0.0173075000, 0.0186911000, 0.0229938000, 0.0348008000, 0.0715592000, 0.1778563000, 0.4857931000"); - } - } - max_capacitance : 0.2957250000; - max_transition : 1.4947070000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0196405000, 0.0225313000, 0.0306073000, 0.0530876000, 0.1170498000, 0.3002479000, 0.8311263000", \ - "0.0232580000, 0.0262031000, 0.0343710000, 0.0569615000, 0.1207237000, 0.3041890000, 0.8371382000", \ - "0.0306083000, 0.0345953000, 0.0441969000, 0.0668423000, 0.1306313000, 0.3147617000, 0.8456565000", \ - "0.0386521000, 0.0448781000, 0.0594110000, 0.0890522000, 0.1547668000, 0.3392265000, 0.8753171000", \ - "0.0443111000, 0.0537228000, 0.0760942000, 0.1222494000, 0.2090958000, 0.3938025000, 0.9279358000", \ - "0.0379220000, 0.0521680000, 0.0861455000, 0.1566489000, 0.2886878000, 0.5227326000, 1.0532761000", \ - "-0.002888300, 0.0177590000, 0.0683835000, 0.1751257000, 0.3776648000, 0.7334811000, 1.3508487000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0234042000, 0.0272961000, 0.0378902000, 0.0662710000, 0.1468296000, 0.3766720000, 1.0430288000", \ - "0.0285029000, 0.0323242000, 0.0428804000, 0.0715777000, 0.1526758000, 0.3841040000, 1.0501123000", \ - "0.0415735000, 0.0456471000, 0.0558024000, 0.0841595000, 0.1648275000, 0.3982397000, 1.0630141000", \ - "0.0625212000, 0.0693067000, 0.0848274000, 0.1156314000, 0.1961560000, 0.4278370000, 1.0972452000", \ - "0.0954805000, 0.1063290000, 0.1310645000, 0.1805098000, 0.2699957000, 0.4987042000, 1.1642018000", \ - "0.1500733000, 0.1667145000, 0.2058185000, 0.2846440000, 0.4270209000, 0.6712687000, 1.3360445000", \ - "0.2493886000, 0.2726850000, 0.3303575000, 0.4510220000, 0.6755325000, 1.0523511000, 1.7335490000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0133514000, 0.0169215000, 0.0272753000, 0.0571250000, 0.1432498000, 0.3932893000, 1.1146614000", \ - "0.0135047000, 0.0169035000, 0.0272243000, 0.0570915000, 0.1431917000, 0.3934648000, 1.1143239000", \ - "0.0189651000, 0.0223409000, 0.0300608000, 0.0575397000, 0.1435002000, 0.3926613000, 1.1151650000", \ - "0.0291933000, 0.0333672000, 0.0438684000, 0.0685226000, 0.1446107000, 0.3939905000, 1.1197315000", \ - "0.0481151000, 0.0545263000, 0.0693009000, 0.1011888000, 0.1690530000, 0.3962433000, 1.1235318000", \ - "0.0823343000, 0.0910101000, 0.1157910000, 0.1606186000, 0.2497840000, 0.4423278000, 1.1198590000", \ - "0.1424869000, 0.1578238000, 0.1906454000, 0.2624215000, 0.3945884000, 0.6341604000, 1.2002073000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0162349000, 0.0209719000, 0.0344655000, 0.0738505000, 0.1890225000, 0.5165977000, 1.4734944000", \ - "0.0162659000, 0.0209354000, 0.0345138000, 0.0740792000, 0.1888583000, 0.5220078000, 1.4719527000", \ - "0.0209573000, 0.0241506000, 0.0354277000, 0.0742037000, 0.1882903000, 0.5190770000, 1.4700853000", \ - "0.0349278000, 0.0392107000, 0.0495496000, 0.0785863000, 0.1883307000, 0.5208434000, 1.4828988000", \ - "0.0579283000, 0.0648078000, 0.0806066000, 0.1126596000, 0.1985025000, 0.5204151000, 1.4727725000", \ - "0.0948433000, 0.1057711000, 0.1324597000, 0.1838822000, 0.2765839000, 0.5346962000, 1.4794285000", \ - "0.1578225000, 0.1749729000, 0.2149484000, 0.2979191000, 0.4434074000, 0.6930639000, 1.4947069000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0258854000, 0.0287373000, 0.0366466000, 0.0587570000, 0.1226356000, 0.3080318000, 0.8395692000", \ - "0.0299134000, 0.0328028000, 0.0409529000, 0.0632304000, 0.1268022000, 0.3142586000, 0.8414771000", \ - "0.0377397000, 0.0411122000, 0.0497526000, 0.0723792000, 0.1362899000, 0.3199820000, 0.8553105000", \ - "0.0485581000, 0.0532613000, 0.0653250000, 0.0925028000, 0.1575871000, 0.3441385000, 0.8781460000", \ - "0.0585524000, 0.0662130000, 0.0848243000, 0.1244623000, 0.2048766000, 0.3931037000, 0.9231521000", \ - "0.0568926000, 0.0694083000, 0.0996281000, 0.1623507000, 0.2795128000, 0.5042519000, 1.0413539000", \ - "0.0186719000, 0.0389093000, 0.0869898000, 0.1869998000, 0.3715080000, 0.6908207000, 1.2956061000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0335011000, 0.0370433000, 0.0470833000, 0.0749227000, 0.1540908000, 0.3817728000, 1.0409879000", \ - "0.0385394000, 0.0421363000, 0.0520825000, 0.0802044000, 0.1595571000, 0.3870675000, 1.0442850000", \ - "0.0517572000, 0.0553038000, 0.0650654000, 0.0935463000, 0.1727755000, 0.4007794000, 1.0587002000", \ - "0.0796275000, 0.0844973000, 0.0966274000, 0.1252340000, 0.2042371000, 0.4318303000, 1.0891379000", \ - "0.1252061000, 0.1329483000, 0.1523629000, 0.1943629000, 0.2787976000, 0.5053701000, 1.1601994000", \ - "0.1972206000, 0.2090814000, 0.2396525000, 0.3081440000, 0.4375670000, 0.6776678000, 1.3334276000", \ - "0.3201439000, 0.3376978000, 0.3831760000, 0.4891667000, 0.6986259000, 1.0566379000, 1.7296361000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0134140000, 0.0169738000, 0.0272946000, 0.0571261000, 0.1431280000, 0.3941987000, 1.1152559000", \ - "0.0135070000, 0.0169832000, 0.0273614000, 0.0571311000, 0.1430896000, 0.3969800000, 1.1147236000", \ - "0.0163336000, 0.0192690000, 0.0284941000, 0.0573182000, 0.1433677000, 0.3932045000, 1.1201525000", \ - "0.0246764000, 0.0281617000, 0.0376337000, 0.0628800000, 0.1444065000, 0.3941566000, 1.1195170000", \ - "0.0422421000, 0.0468894000, 0.0589070000, 0.0867815000, 0.1598832000, 0.3954339000, 1.1198584000", \ - "0.0756723000, 0.0822930000, 0.0989951000, 0.1363624000, 0.2170712000, 0.4260189000, 1.1205752000", \ - "0.1417335000, 0.1504941000, 0.1730674000, 0.2265761000, 0.3351082000, 0.5600993000, 1.1691822000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014486300, 0.0041970400, 0.0121599000, 0.0352302000, 0.1020710000, 0.2957250000"); - values("0.0249890000, 0.0296424000, 0.0429328000, 0.0816157000, 0.1940235000, 0.5203246000, 1.4690655000", \ - "0.0249228000, 0.0296308000, 0.0430159000, 0.0817695000, 0.1945153000, 0.5192103000, 1.4630871000", \ - "0.0260850000, 0.0302875000, 0.0429290000, 0.0818567000, 0.1945699000, 0.5198304000, 1.4680340000", \ - "0.0388287000, 0.0428265000, 0.0522368000, 0.0847626000, 0.1942694000, 0.5197135000, 1.4632040000", \ - "0.0635308000, 0.0692776000, 0.0837312000, 0.1145030000, 0.2033784000, 0.5211009000, 1.4684114000", \ - "0.1041696000, 0.1139577000, 0.1375801000, 0.1863291000, 0.2751538000, 0.5386456000, 1.4682930000", \ - "0.1691102000, 0.1853677000, 0.2235712000, 0.3036737000, 0.4455700000, 0.6903160000, 1.4855411000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2_4") { - leakage_power () { - value : 0.0019122000; - when : "!A&B"; - } - leakage_power () { - value : 0.0168098000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0082791000; - when : "A&B"; - } - leakage_power () { - value : 0.0014905000; - when : "A&!B"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__nand2"; - cell_leakage_power : 0.0071228910; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0085370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181423000, 0.0181690000, 0.0182305000, 0.0182212000, 0.0181998000, 0.0181504000, 0.0180365000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012965000, -0.012981700, -0.013020300, -0.012986000, -0.012906800, -0.012724100, -0.012303100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087960000; - } - pin ("B") { - capacitance : 0.0088300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158302000, 0.0158272000, 0.0158201000, 0.0158218000, 0.0158258000, 0.0158349000, 0.0158559000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015780500, -0.015776400, -0.015766800, -0.015765400, -0.015761800, -0.015753500, -0.015734500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092720000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0092709000, 0.0077009000, 0.0025027000, -0.015025000, -0.072574000, -0.257171200, -0.847001100", \ - "0.0082969000, 0.0067735000, 0.0016752000, -0.015512900, -0.072721600, -0.257184300, -0.846950300", \ - "0.0074126000, 0.0057640000, 0.0006926000, -0.016316200, -0.073149300, -0.257310100, -0.846966500", \ - "0.0068373000, 0.0053001000, -0.000165400, -0.017304700, -0.073918100, -0.257701000, -0.847107100", \ - "0.0074511000, 0.0053845000, -0.000227900, -0.018013700, -0.074543500, -0.258244900, -0.847347200", \ - "0.0100396000, 0.0088558000, 0.0026606000, -0.016283000, -0.074757700, -0.258933800, -0.847823400", \ - "0.0173091000, 0.0151494000, 0.0083075000, -0.011870700, -0.071891100, -0.258441100, -0.848122700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0091146000, 0.0112783000, 0.0178392000, 0.0369367000, 0.0950041000, 0.2763970000, 0.8621528000", \ - "0.0081918000, 0.0102920000, 0.0166638000, 0.0360023000, 0.0947208000, 0.2788672000, 0.8564815000", \ - "0.0074836000, 0.0094487000, 0.0154921000, 0.0348579000, 0.0936324000, 0.2760390000, 0.8564804000", \ - "0.0075544000, 0.0093879000, 0.0151739000, 0.0334676000, 0.0924796000, 0.2767033000, 0.8606083000", \ - "0.0082828000, 0.0100198000, 0.0155066000, 0.0342195000, 0.0906974000, 0.2755006000, 0.8596083000", \ - "0.0100462000, 0.0115774000, 0.0168437000, 0.0348121000, 0.0918673000, 0.2721794000, 0.8578122000", \ - "0.0211584000, 0.0192862000, 0.0241122000, 0.0402916000, 0.0954585000, 0.2754714000, 0.8561925000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0124667000, 0.0108860000, 0.0055330000, -0.012192100, -0.069814400, -0.254450100, -0.844262700", \ - "0.0115513000, 0.0099962000, 0.0048302000, -0.012614800, -0.070006000, -0.254502500, -0.844283200", \ - "0.0105588000, 0.0089911000, 0.0038382000, -0.013366100, -0.070359800, -0.254624800, -0.844307900", \ - "0.0098371000, 0.0082435000, 0.0028662000, -0.014336500, -0.071013900, -0.254935600, -0.844440300", \ - "0.0103310000, 0.0086112000, 0.0031815000, -0.014982500, -0.071688200, -0.255262900, -0.844565600", \ - "0.0110791000, 0.0092420000, 0.0035066000, -0.014649000, -0.072463200, -0.256062100, -0.844943400", \ - "0.0162366000, 0.0142006000, 0.0078286000, -0.011624200, -0.070533000, -0.255904100, -0.845158800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0246982000, 0.0265806000, 0.0324368000, 0.0507196000, 0.1082635000, 0.2906759000, 0.8724890000", \ - "0.0236517000, 0.0255482000, 0.0315826000, 0.0501034000, 0.1077713000, 0.2905790000, 0.8720048000", \ - "0.0226210000, 0.0245063000, 0.0306335000, 0.0491354000, 0.1071174000, 0.2901346000, 0.8721392000", \ - "0.0222230000, 0.0240774000, 0.0298671000, 0.0482436000, 0.1062879000, 0.2891320000, 0.8720190000", \ - "0.0233464000, 0.0251660000, 0.0310043000, 0.0490305000, 0.1064789000, 0.2890935000, 0.8712707000", \ - "0.0248859000, 0.0265116000, 0.0319589000, 0.0509890000, 0.1085646000, 0.2896306000, 0.8713115000", \ - "0.0315546000, 0.0333030000, 0.0386418000, 0.0553548000, 0.1107202000, 0.2930465000, 0.8722406000"); - } - } - max_capacitance : 0.5301000000; - max_transition : 1.4986590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0196846000, 0.0214894000, 0.0270948000, 0.0441384000, 0.0963893000, 0.2626743000, 0.7983328000", \ - "0.0232463000, 0.0250872000, 0.0307584000, 0.0478779000, 0.1014861000, 0.2674229000, 0.7975810000", \ - "0.0301511000, 0.0327263000, 0.0399473000, 0.0575092000, 0.1106251000, 0.2770611000, 0.8073930000", \ - "0.0372339000, 0.0410862000, 0.0521713000, 0.0781962000, 0.1340250000, 0.3011591000, 0.8350764000", \ - "0.0401552000, 0.0463746000, 0.0631236000, 0.1029376000, 0.1836212000, 0.3545091000, 0.8851356000", \ - "0.0282955000, 0.0379621000, 0.0634936000, 0.1240876000, 0.2477358000, 0.4819245000, 1.0147604000", \ - "-0.025064200, -0.011335100, 0.0263611000, 0.1176377000, 0.3079844000, 0.6639810000, 1.3116122000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0242340000, 0.0269078000, 0.0348598000, 0.0579881000, 0.1288697000, 0.3500559000, 1.0564722000", \ - "0.0293365000, 0.0318920000, 0.0395086000, 0.0629239000, 0.1342490000, 0.3580886000, 1.0637792000", \ - "0.0424911000, 0.0452213000, 0.0526283000, 0.0759010000, 0.1465874000, 0.3692190000, 1.0762998000", \ - "0.0641670000, 0.0686250000, 0.0805502000, 0.1072780000, 0.1773256000, 0.3990797000, 1.1052306000", \ - "0.0987517000, 0.1059299000, 0.1248592000, 0.1683010000, 0.2522434000, 0.4750554000, 1.1799575000", \ - "0.1581990000, 0.1687093000, 0.1984489000, 0.2672093000, 0.4015263000, 0.6471254000, 1.3525815000", \ - "0.2686611000, 0.2839625000, 0.3268878000, 0.4302959000, 0.6430589000, 1.0218250000, 1.7544647000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0130327000, 0.0151905000, 0.0223079000, 0.0450649000, 0.1167571000, 0.3458200000, 1.0805018000", \ - "0.0131986000, 0.0152698000, 0.0223447000, 0.0449553000, 0.1176859000, 0.3468408000, 1.0782312000", \ - "0.0184825000, 0.0208300000, 0.0262382000, 0.0458781000, 0.1173606000, 0.3456738000, 1.0795913000", \ - "0.0283107000, 0.0312156000, 0.0391559000, 0.0595476000, 0.1196149000, 0.3465407000, 1.0788846000", \ - "0.0473497000, 0.0512064000, 0.0625856000, 0.0893939000, 0.1500424000, 0.3495459000, 1.0761634000", \ - "0.0797161000, 0.0861683000, 0.1031389000, 0.1433381000, 0.2262718000, 0.4096607000, 1.0780071000", \ - "0.1394519000, 0.1490594000, 0.1757089000, 0.2373024000, 0.3605228000, 0.5942562000, 1.1732155000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0163728000, 0.0193365000, 0.0291154000, 0.0602568000, 0.1598662000, 0.4740094000, 1.4826818000", \ - "0.0163340000, 0.0193897000, 0.0290425000, 0.0600941000, 0.1596554000, 0.4764955000, 1.4817469000", \ - "0.0207267000, 0.0227527000, 0.0305370000, 0.0600965000, 0.1596094000, 0.4769091000, 1.4796694000", \ - "0.0344062000, 0.0372092000, 0.0452310000, 0.0666464000, 0.1593882000, 0.4757272000, 1.4806347000", \ - "0.0570896000, 0.0618423000, 0.0737096000, 0.1015869000, 0.1730242000, 0.4760021000, 1.4867120000", \ - "0.0930665000, 0.1007368000, 0.1208184000, 0.1653146000, 0.2510803000, 0.4943750000, 1.4874799000", \ - "0.1562131000, 0.1687451000, 0.1971350000, 0.2695675000, 0.4079915000, 0.6520386000, 1.4986586000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0253961000, 0.0272441000, 0.0327091000, 0.0495859000, 0.1016656000, 0.2691097000, 0.7995458000", \ - "0.0292059000, 0.0310275000, 0.0367110000, 0.0535885000, 0.1069765000, 0.2727188000, 0.8032400000", \ - "0.0360932000, 0.0383465000, 0.0446087000, 0.0620557000, 0.1152077000, 0.2825578000, 0.8124311000", \ - "0.0452887000, 0.0484803000, 0.0569603000, 0.0789576000, 0.1344180000, 0.3014440000, 0.8323233000", \ - "0.0523876000, 0.0572227000, 0.0711605000, 0.1033989000, 0.1756529000, 0.3473160000, 0.8786184000", \ - "0.0445039000, 0.0524351000, 0.0752641000, 0.1267944000, 0.2336107000, 0.4488819000, 0.9877016000", \ - "-0.007831800, 0.0051118000, 0.0406924000, 0.1246323000, 0.2935974000, 0.6075307000, 1.2241136000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0350992000, 0.0375969000, 0.0449204000, 0.0672063000, 0.1365061000, 0.3554612000, 1.0523779000", \ - "0.0401893000, 0.0425308000, 0.0500041000, 0.0725969000, 0.1418545000, 0.3608226000, 1.0587001000", \ - "0.0533601000, 0.0556450000, 0.0631076000, 0.0852729000, 0.1554152000, 0.3748254000, 1.0715463000", \ - "0.0825839000, 0.0855946000, 0.0945014000, 0.1176278000, 0.1873090000, 0.4060128000, 1.1023487000", \ - "0.1305368000, 0.1354267000, 0.1493281000, 0.1848286000, 0.2619334000, 0.4802199000, 1.1769874000", \ - "0.2086142000, 0.2163482000, 0.2385785000, 0.2956733000, 0.4165240000, 0.6538708000, 1.3473886000", \ - "0.3422315000, 0.3554846000, 0.3890883000, 0.4763761000, 0.6703939000, 1.0324812000, 1.7501620000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0130486000, 0.0153045000, 0.0223979000, 0.0449948000, 0.1170474000, 0.3462942000, 1.0776381000", \ - "0.0131341000, 0.0153396000, 0.0224098000, 0.0450121000, 0.1170983000, 0.3457965000, 1.0763236000", \ - "0.0160618000, 0.0179452000, 0.0240640000, 0.0454251000, 0.1169452000, 0.3460591000, 1.0776199000", \ - "0.0239101000, 0.0261751000, 0.0328030000, 0.0527195000, 0.1186293000, 0.3455221000, 1.0775539000", \ - "0.0408777000, 0.0438993000, 0.0524337000, 0.0746259000, 0.1377432000, 0.3488929000, 1.0765813000", \ - "0.0737383000, 0.0778088000, 0.0899509000, 0.1204960000, 0.1915944000, 0.3861498000, 1.0824506000", \ - "0.1393429000, 0.1447637000, 0.1602991000, 0.2029102000, 0.2995143000, 0.5164569000, 1.1353274000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0262074000, 0.0290839000, 0.0385814000, 0.0688890000, 0.1665689000, 0.4785676000, 1.4708065000", \ - "0.0260423000, 0.0290809000, 0.0385178000, 0.0691440000, 0.1666881000, 0.4777270000, 1.4763981000", \ - "0.0268695000, 0.0294992000, 0.0384833000, 0.0690093000, 0.1665566000, 0.4775256000, 1.4712840000", \ - "0.0392180000, 0.0418221000, 0.0484628000, 0.0729160000, 0.1667060000, 0.4799063000, 1.4715091000", \ - "0.0636660000, 0.0676837000, 0.0785134000, 0.1047819000, 0.1790759000, 0.4781919000, 1.4725076000", \ - "0.1038778000, 0.1105205000, 0.1281283000, 0.1701179000, 0.2544870000, 0.4989449000, 1.4719324000", \ - "0.1682099000, 0.1790331000, 0.2076618000, 0.2767220000, 0.4093141000, 0.6541236000, 1.4922104000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2_8") { - leakage_power () { - value : 0.0045597000; - when : "!A&B"; - } - leakage_power () { - value : 0.0004022000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0097833000; - when : "A&B"; - } - leakage_power () { - value : 0.0034683000; - when : "A&!B"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__nand2"; - cell_leakage_power : 0.0045533830; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0169330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0164390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0363587000, 0.0363664000, 0.0363840000, 0.0363832000, 0.0363812000, 0.0363766000, 0.0363659000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.026356800, -0.026400100, -0.026500100, -0.026438400, -0.026296000, -0.025967800, -0.025211400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0174280000; - } - pin ("B") { - capacitance : 0.0172050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0163140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0313291000, 0.0313225000, 0.0313075000, 0.0312961000, 0.0312700000, 0.0312097000, 0.0310707000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.031259000, -0.031245900, -0.031215800, -0.031212700, -0.031205400, -0.031188700, -0.031150100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0180960000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017546390, 0.0061575130, 0.0216084200, 0.0758299300, 0.2661083000, 0.9338476000"); - values("0.0205508000, 0.0188009000, 0.0124390000, -0.011414600, -0.098430800, -0.406381200, -1.488124000", \ - "0.0185952000, 0.0168989000, 0.0107097000, -0.012504100, -0.098884100, -0.406553400, -1.488042700", \ - "0.0166970000, 0.0148576000, 0.0086170000, -0.014414700, -0.099743800, -0.406757100, -1.488114100", \ - "0.0157569000, 0.0138915000, 0.0069896000, -0.016399700, -0.101640900, -0.407554600, -1.488302300", \ - "0.0164532000, 0.0138633000, 0.0073967000, -0.017665500, -0.103095100, -0.408774500, -1.488831300", \ - "0.0207503000, 0.0184439000, 0.0108731000, -0.014541600, -0.103444500, -0.410268200, -1.489782600", \ - "0.0333020000, 0.0308041000, 0.0223208000, -0.005964200, -0.097507600, -0.409411000, -1.490448300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017546390, 0.0061575130, 0.0216084200, 0.0758299300, 0.2661083000, 0.9338476000"); - values("0.0184146000, 0.0210472000, 0.0296986000, 0.0569996000, 0.1454304000, 0.4489157000, 1.5171134000", \ - "0.0166210000, 0.0189581000, 0.0273034000, 0.0550721000, 0.1448347000, 0.4520620000, 1.5135194000", \ - "0.0150424000, 0.0172704000, 0.0251191000, 0.0526776000, 0.1421168000, 0.4485339000, 1.5174999000", \ - "0.0147223000, 0.0168517000, 0.0243489000, 0.0502502000, 0.1407197000, 0.4502171000, 1.5135958000", \ - "0.0160566000, 0.0180353000, 0.0250976000, 0.0499872000, 0.1371661000, 0.4437872000, 1.5130565000", \ - "0.0206582000, 0.0224965000, 0.0290742000, 0.0530189000, 0.1391848000, 0.4432059000, 1.5104705000", \ - "0.0327240000, 0.0343552000, 0.0396617000, 0.0649382000, 0.1436804000, 0.4455923000, 1.5122625000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017546390, 0.0061575130, 0.0216084200, 0.0758299300, 0.2661083000, 0.9338476000"); - values("0.0264887000, 0.0246092000, 0.0179861000, -0.006251500, -0.093636600, -0.401703700, -1.483293500", \ - "0.0246305000, 0.0228776000, 0.0164715000, -0.007219700, -0.094029800, -0.401857400, -1.483327700", \ - "0.0226646000, 0.0208773000, 0.0144559000, -0.008898900, -0.094846300, -0.402116000, -1.483513600", \ - "0.0211754000, 0.0193045000, 0.0125936000, -0.010985700, -0.096363200, -0.402738200, -1.483717200", \ - "0.0219283000, 0.0200251000, 0.0131308000, -0.011994700, -0.097773800, -0.403542100, -1.483750100", \ - "0.0230724000, 0.0210642000, 0.0138143000, -0.011206600, -0.098931300, -0.405297900, -1.484731100", \ - "0.0324301000, 0.0300654000, 0.0217968000, -0.005074400, -0.095148100, -0.404945600, -1.485336500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017546390, 0.0061575130, 0.0216084200, 0.0758299300, 0.2661083000, 0.9338476000"); - values("0.0488452000, 0.0509326000, 0.0583063000, 0.0837468000, 0.1711816000, 0.4758318000, 1.5436059000", \ - "0.0468624000, 0.0490846000, 0.0565711000, 0.0824552000, 0.1705423000, 0.4756971000, 1.5423772000", \ - "0.0450527000, 0.0472793000, 0.0545243000, 0.0807461000, 0.1690376000, 0.4749533000, 1.5418241000", \ - "0.0438718000, 0.0459505000, 0.0533183000, 0.0788456000, 0.1674054000, 0.4735745000, 1.5420861000", \ - "0.0448575000, 0.0469049000, 0.0538923000, 0.0790352000, 0.1664499000, 0.4719770000, 1.5418975000", \ - "0.0490883000, 0.0510718000, 0.0578024000, 0.0816818000, 0.1681400000, 0.4717201000, 1.5347605000", \ - "0.0602685000, 0.0620399000, 0.0684007000, 0.0909495000, 0.1735191000, 0.4756184000, 1.5391567000"); - } - } - max_capacitance : 0.9338480000; - max_transition : 1.4961180000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0224117000, 0.0236913000, 0.0280666000, 0.0423203000, 0.0903754000, 0.2588930000, 0.8410206000", \ - "0.0257246000, 0.0270420000, 0.0314871000, 0.0460865000, 0.0943061000, 0.2626327000, 0.8464651000", \ - "0.0331355000, 0.0348437000, 0.0403686000, 0.0551771000, 0.1038348000, 0.2709631000, 0.8615312000", \ - "0.0408780000, 0.0433810000, 0.0517113000, 0.0740146000, 0.1269494000, 0.2944963000, 0.8780461000", \ - "0.0439788000, 0.0479524000, 0.0605036000, 0.0948883000, 0.1729469000, 0.3492918000, 0.9383808000", \ - "0.0307661000, 0.0367069000, 0.0554403000, 0.1082930000, 0.2285799000, 0.4707799000, 1.0610661000", \ - "-0.028072700, -0.018929800, 0.0093322000, 0.0869713000, 0.2700820000, 0.6412523000, 1.3512288000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0264431000, 0.0282106000, 0.0340901000, 0.0526758000, 0.1134019000, 0.3213201000, 1.0532489000", \ - "0.0314573000, 0.0330337000, 0.0387074000, 0.0576204000, 0.1186226000, 0.3297862000, 1.0565987000", \ - "0.0448864000, 0.0464786000, 0.0518004000, 0.0701208000, 0.1314871000, 0.3403342000, 1.0724535000", \ - "0.0679208000, 0.0707478000, 0.0793896000, 0.1017512000, 0.1626818000, 0.3722355000, 1.0990397000", \ - "0.1055412000, 0.1099643000, 0.1237297000, 0.1595495000, 0.2374898000, 0.4468821000, 1.1738386000", \ - "0.1700382000, 0.1767170000, 0.1976753000, 0.2545144000, 0.3792140000, 0.6202291000, 1.3482485000", \ - "0.2910064000, 0.3005842000, 0.3311068000, 0.4166284000, 0.6108516000, 0.9875615000, 1.7493069000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0161049000, 0.0176591000, 0.0231072000, 0.0420753000, 0.1087631000, 0.3443780000, 1.1593273000", \ - "0.0160172000, 0.0175571000, 0.0230757000, 0.0421819000, 0.1085911000, 0.3428719000, 1.1595260000", \ - "0.0216718000, 0.0228243000, 0.0270165000, 0.0433478000, 0.1088337000, 0.3419069000, 1.1647437000", \ - "0.0308782000, 0.0328123000, 0.0390341000, 0.0571887000, 0.1119642000, 0.3425072000, 1.1599337000", \ - "0.0502674000, 0.0532643000, 0.0620706000, 0.0854881000, 0.1450423000, 0.3461157000, 1.1668896000", \ - "0.0842350000, 0.0883137000, 0.1016648000, 0.1379871000, 0.2181692000, 0.4092773000, 1.1613154000", \ - "0.1455370000, 0.1514515000, 0.1709396000, 0.2250627000, 0.3473864000, 0.5935612000, 1.2440662000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0180334000, 0.0199122000, 0.0267879000, 0.0508646000, 0.1350507000, 0.4292810000, 1.4669440000", \ - "0.0179886000, 0.0199674000, 0.0267932000, 0.0509626000, 0.1354678000, 0.4350233000, 1.4641154000", \ - "0.0214298000, 0.0227952000, 0.0281915000, 0.0508145000, 0.1352446000, 0.4290920000, 1.4660406000", \ - "0.0354160000, 0.0372444000, 0.0428243000, 0.0590735000, 0.1353016000, 0.4330590000, 1.4618393000", \ - "0.0582357000, 0.0610972000, 0.0696132000, 0.0927805000, 0.1526168000, 0.4304789000, 1.4661564000", \ - "0.0957267000, 0.1002051000, 0.1146139000, 0.1526402000, 0.2308653000, 0.4540299000, 1.4706362000", \ - "0.1603378000, 0.1670111000, 0.1877338000, 0.2472398000, 0.3761665000, 0.6170633000, 1.4784669000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0289452000, 0.0301681000, 0.0343323000, 0.0485501000, 0.0961600000, 0.2630340000, 0.8464043000", \ - "0.0322972000, 0.0336257000, 0.0379330000, 0.0523958000, 0.1002924000, 0.2687019000, 0.8525156000", \ - "0.0386135000, 0.0400687000, 0.0448181000, 0.0596188000, 0.1088806000, 0.2749924000, 0.8596091000", \ - "0.0471507000, 0.0490638000, 0.0551071000, 0.0732435000, 0.1248505000, 0.2924853000, 0.8767654000", \ - "0.0532898000, 0.0562810000, 0.0658502000, 0.0924738000, 0.1583344000, 0.3319826000, 0.9175613000", \ - "0.0429012000, 0.0478118000, 0.0634277000, 0.1061592000, 0.2040668000, 0.4165796000, 1.0091663000", \ - "-0.015941300, -0.008017600, 0.0168739000, 0.0852448000, 0.2404768000, 0.5486946000, 1.2174135000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0394806000, 0.0409352000, 0.0462588000, 0.0639553000, 0.1237404000, 0.3308363000, 1.0547064000", \ - "0.0441710000, 0.0457039000, 0.0511316000, 0.0690070000, 0.1291672000, 0.3363283000, 1.0607962000", \ - "0.0572794000, 0.0588592000, 0.0638967000, 0.0817498000, 0.1425250000, 0.3495408000, 1.0747906000", \ - "0.0874759000, 0.0894198000, 0.0957082000, 0.1140368000, 0.1742327000, 0.3817158000, 1.1045490000", \ - "0.1381147000, 0.1411141000, 0.1509334000, 0.1797678000, 0.2492755000, 0.4554379000, 1.1821506000", \ - "0.2212021000, 0.2258948000, 0.2412849000, 0.2868407000, 0.3973467000, 0.6300300000, 1.3485423000", \ - "0.3677006000, 0.3742824000, 0.3963834000, 0.4660898000, 0.6411204000, 1.0004062000, 1.7536783000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0161749000, 0.0176969000, 0.0230839000, 0.0422533000, 0.1086732000, 0.3424355000, 1.1592646000", \ - "0.0162444000, 0.0177565000, 0.0231413000, 0.0422662000, 0.1086846000, 0.3429780000, 1.1637161000", \ - "0.0187044000, 0.0200780000, 0.0247997000, 0.0428880000, 0.1091377000, 0.3416637000, 1.1591201000", \ - "0.0259421000, 0.0274268000, 0.0325246000, 0.0500344000, 0.1107406000, 0.3412993000, 1.1591048000", \ - "0.0428752000, 0.0447565000, 0.0507818000, 0.0696037000, 0.1294861000, 0.3449796000, 1.1611854000", \ - "0.0765463000, 0.0790865000, 0.0870578000, 0.1119808000, 0.1773981000, 0.3791053000, 1.1615073000", \ - "0.1427901000, 0.1462824000, 0.1573155000, 0.1905947000, 0.2780893000, 0.4981724000, 1.2110781000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017546400, 0.0061575100, 0.0216084000, 0.0758299000, 0.2661080000, 0.9338480000"); - values("0.0293910000, 0.0313095000, 0.0381604000, 0.0620688000, 0.1463961000, 0.4420224000, 1.4781832000", \ - "0.0294329000, 0.0313841000, 0.0380884000, 0.0621966000, 0.1462411000, 0.4429453000, 1.4844204000", \ - "0.0296646000, 0.0314866000, 0.0380430000, 0.0620277000, 0.1462656000, 0.4418284000, 1.4847428000", \ - "0.0416091000, 0.0427913000, 0.0477545000, 0.0668010000, 0.1464050000, 0.4423252000, 1.4810816000", \ - "0.0663627000, 0.0688524000, 0.0760029000, 0.0976313000, 0.1614487000, 0.4421318000, 1.4840437000", \ - "0.1082542000, 0.1122554000, 0.1241131000, 0.1585154000, 0.2365880000, 0.4654858000, 1.4852369000", \ - "0.1739390000, 0.1803012000, 0.2001274000, 0.2580160000, 0.3817304000, 0.6266708000, 1.4961177000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2b_1") { - leakage_power () { - value : 0.0062841000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0006300000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0011852000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0009204000; - when : "A_N&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nand2b"; - cell_leakage_power : 0.0022549180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0013950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0068080000, 0.0067224000, 0.0065251000, 0.0065712000, 0.0066775000, 0.0069226000, 0.0074874000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045957000, 0.0045294000, 0.0043766000, 0.0044173000, 0.0045113000, 0.0047278000, 0.0052269000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014450000; - } - pin ("B") { - capacitance : 0.0023990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038582000, 0.0038598000, 0.0038635000, 0.0038652000, 0.0038692000, 0.0038782000, 0.0038991000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003875500, -0.003871300, -0.003861600, -0.003861200, -0.003860200, -0.003857900, -0.003852600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025070000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0043144000, 0.0032094000, 0.0002598000, -0.007949100, -0.029996600, -0.087588600, -0.236789300", \ - "0.0042672000, 0.0031684000, 0.0001953000, -0.007984000, -0.030040500, -0.087628000, -0.236842500", \ - "0.0042965000, 0.0031883000, 0.0002410000, -0.007975900, -0.030024500, -0.087591400, -0.236773200", \ - "0.0041326000, 0.0030020000, 3.300000e-06, -0.008227700, -0.030239400, -0.087771800, -0.236956200", \ - "0.0040481000, 0.0028793000, -0.000195700, -0.008525800, -0.030473300, -0.087956300, -0.237103900", \ - "0.0040663000, 0.0027405000, -0.000556100, -0.008782300, -0.030376000, -0.087792000, -0.236902300", \ - "0.0045330000, 0.0033453000, -1.38000e-05, -0.008732000, -0.030782200, -0.087957400, -0.237012600"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0035660000, 0.0049830000, 0.0084844000, 0.0171655000, 0.0395290000, 0.0963918000, 0.2426410000", \ - "0.0035532000, 0.0049679000, 0.0084780000, 0.0171847000, 0.0395279000, 0.0963840000, 0.2435471000", \ - "0.0035425000, 0.0049422000, 0.0084404000, 0.0171852000, 0.0394369000, 0.0964263000, 0.2426633000", \ - "0.0032758000, 0.0046406000, 0.0081144000, 0.0168039000, 0.0391483000, 0.0966012000, 0.2434622000", \ - "0.0031896000, 0.0044783000, 0.0078820000, 0.0165190000, 0.0387261000, 0.0960651000, 0.2436779000", \ - "0.0031247000, 0.0044470000, 0.0078600000, 0.0163582000, 0.0387285000, 0.0953900000, 0.2446636000", \ - "0.0035078000, 0.0047461000, 0.0081116000, 0.0168005000, 0.0389005000, 0.0964179000, 0.2425233000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0043991000, 0.0032356000, 0.0001044000, -0.008356000, -0.030579500, -0.088235100, -0.237421400", \ - "0.0041891000, 0.0030569000, -2.40000e-05, -0.008427600, -0.030613200, -0.088240500, -0.237495000", \ - "0.0039264000, 0.0028084000, -0.000237800, -0.008561700, -0.030681600, -0.088288100, -0.237506900", \ - "0.0038233000, 0.0026329000, -0.000458200, -0.008770600, -0.030808800, -0.088335300, -0.237528800", \ - "0.0041593000, 0.0028931000, -0.000414800, -0.008979500, -0.031000000, -0.088455900, -0.237536800", \ - "0.0044811000, 0.0031647000, -0.000191400, -0.008796100, -0.031135600, -0.088570700, -0.237659200", \ - "0.0060336000, 0.0045764000, 0.0009544000, -0.008028600, -0.030578700, -0.088491800, -0.237672800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0055239000, 0.0068052000, 0.0101348000, 0.0186852000, 0.0406941000, 0.0975507000, 0.2447029000", \ - "0.0053074000, 0.0066152000, 0.0099812000, 0.0185411000, 0.0406184000, 0.0974835000, 0.2446953000", \ - "0.0051308000, 0.0064208000, 0.0097540000, 0.0184371000, 0.0403409000, 0.0974400000, 0.2444970000", \ - "0.0051312000, 0.0063883000, 0.0096980000, 0.0182857000, 0.0402739000, 0.0969598000, 0.2445785000", \ - "0.0051226000, 0.0063892000, 0.0097013000, 0.0181443000, 0.0399399000, 0.0967400000, 0.2435841000", \ - "0.0055271000, 0.0067262000, 0.0099085000, 0.0186076000, 0.0408861000, 0.0974294000, 0.2443477000", \ - "0.0076709000, 0.0088454000, 0.0119045000, 0.0198827000, 0.0416219000, 0.0974522000, 0.2441025000"); - } - } - max_capacitance : 0.1501560000; - max_transition : 1.5061160000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.1034257000, 0.1102257000, 0.1249078000, 0.1563750000, 0.2288244000, 0.4102221000, 0.8789943000", \ - "0.1084989000, 0.1152293000, 0.1298916000, 0.1614971000, 0.2338686000, 0.4156431000, 0.8869536000", \ - "0.1212644000, 0.1279946000, 0.1426910000, 0.1742850000, 0.2465777000, 0.4281527000, 0.8988822000", \ - "0.1530543000, 0.1597305000, 0.1743983000, 0.2059884000, 0.2784428000, 0.4608543000, 0.9301817000", \ - "0.2221842000, 0.2291834000, 0.2442925000, 0.2762841000, 0.3489685000, 0.5310249000, 1.0004002000", \ - "0.3360641000, 0.3446534000, 0.3625003000, 0.3973517000, 0.4720840000, 0.6536036000, 1.1241699000", \ - "0.5145535000, 0.5259607000, 0.5480861000, 0.5908290000, 0.6702471000, 0.8492763000, 1.3178396000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0605303000, 0.0670824000, 0.0826768000, 0.1206063000, 0.2162324000, 0.4628263000, 1.1028164000", \ - "0.0654275000, 0.0719787000, 0.0876053000, 0.1254715000, 0.2212389000, 0.4678206000, 1.1062667000", \ - "0.0767061000, 0.0831713000, 0.0987144000, 0.1367134000, 0.2334229000, 0.4829739000, 1.1180429000", \ - "0.0987401000, 0.1052528000, 0.1208196000, 0.1587230000, 0.2552865000, 0.5041368000, 1.1562628000", \ - "0.1292653000, 0.1361918000, 0.1520633000, 0.1899516000, 0.2864792000, 0.5339157000, 1.1715503000", \ - "0.1644226000, 0.1728888000, 0.1902066000, 0.2286065000, 0.3246046000, 0.5717181000, 1.2150905000", \ - "0.1874866000, 0.1984877000, 0.2214584000, 0.2634795000, 0.3582978000, 0.6061131000, 1.2434134000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0275151000, 0.0328390000, 0.0466267000, 0.0805707000, 0.1711005000, 0.4144822000, 1.0451888000", \ - "0.0272889000, 0.0328210000, 0.0466733000, 0.0806842000, 0.1710451000, 0.4152159000, 1.0395693000", \ - "0.0273460000, 0.0331142000, 0.0465749000, 0.0806680000, 0.1711784000, 0.4149591000, 1.0420763000", \ - "0.0273031000, 0.0331804000, 0.0464809000, 0.0807093000, 0.1707910000, 0.4121302000, 1.0401091000", \ - "0.0310456000, 0.0361773000, 0.0491714000, 0.0819604000, 0.1716193000, 0.4144305000, 1.0441310000", \ - "0.0423008000, 0.0476506000, 0.0603239000, 0.0909597000, 0.1759425000, 0.4140424000, 1.0446720000", \ - "0.0607227000, 0.0670333000, 0.0813269000, 0.1111452000, 0.1885510000, 0.4185799000, 1.0402724000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0246217000, 0.0321220000, 0.0518914000, 0.1041771000, 0.2413349000, 0.5917821000, 1.5031738000", \ - "0.0246229000, 0.0321220000, 0.0519001000, 0.1041025000, 0.2411708000, 0.5922978000, 1.5039167000", \ - "0.0246859000, 0.0321107000, 0.0518829000, 0.1040678000, 0.2403528000, 0.5960624000, 1.4996218000", \ - "0.0260085000, 0.0332048000, 0.0523876000, 0.1041506000, 0.2407683000, 0.5938305000, 1.5059931000", \ - "0.0300365000, 0.0366079000, 0.0545561000, 0.1050833000, 0.2396286000, 0.5935822000, 1.5000184000", \ - "0.0393846000, 0.0454694000, 0.0610626000, 0.1080121000, 0.2420009000, 0.5910092000, 1.5061162000", \ - "0.0567332000, 0.0631355000, 0.0781340000, 0.1180524000, 0.2432712000, 0.5928993000, 1.4975257000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0265986000, 0.0312340000, 0.0426886000, 0.0710069000, 0.1419970000, 0.3238535000, 0.7991605000", \ - "0.0306401000, 0.0354059000, 0.0470443000, 0.0755216000, 0.1469049000, 0.3295301000, 0.7972004000", \ - "0.0385113000, 0.0437812000, 0.0556581000, 0.0844652000, 0.1560552000, 0.3380200000, 0.8066621000", \ - "0.0500308000, 0.0572249000, 0.0725389000, 0.1045150000, 0.1769145000, 0.3599066000, 0.8303950000", \ - "0.0625008000, 0.0735116000, 0.0966401000, 0.1410401000, 0.2242080000, 0.4085952000, 0.8811460000", \ - "0.0664890000, 0.0842593000, 0.1211157000, 0.1895887000, 0.3078951000, 0.5221482000, 0.9975816000", \ - "0.0406147000, 0.0691904000, 0.1269989000, 0.2350845000, 0.4185850000, 0.7205022000, 1.2560001000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0334802000, 0.0391453000, 0.0533759000, 0.0892029000, 0.1806853000, 0.4162381000, 1.0255479000", \ - "0.0386575000, 0.0443590000, 0.0586087000, 0.0943790000, 0.1858823000, 0.4215481000, 1.0305918000", \ - "0.0519186000, 0.0574364000, 0.0717745000, 0.1078967000, 0.1987445000, 0.4347811000, 1.0432735000", \ - "0.0799719000, 0.0875358000, 0.1035741000, 0.1390684000, 0.2300442000, 0.4653150000, 1.0753834000", \ - "0.1251441000, 0.1369222000, 0.1625290000, 0.2111903000, 0.3024008000, 0.5372745000, 1.1454254000", \ - "0.1959850000, 0.2146057000, 0.2551795000, 0.3335713000, 0.4676015000, 0.7087391000, 1.3141092000", \ - "0.3145050000, 0.3421277000, 0.4037206000, 0.5270250000, 0.7439301000, 1.0923609000, 1.7102002000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0172297000, 0.0233179000, 0.0380330000, 0.0751638000, 0.1709340000, 0.4118769000, 1.0443507000", \ - "0.0173650000, 0.0233415000, 0.0381112000, 0.0752513000, 0.1694367000, 0.4120308000, 1.0393283000", \ - "0.0196861000, 0.0248385000, 0.0387965000, 0.0751808000, 0.1691487000, 0.4132565000, 1.0391416000", \ - "0.0277346000, 0.0335313000, 0.0468477000, 0.0786546000, 0.1695772000, 0.4124622000, 1.0400523000", \ - "0.0456308000, 0.0526057000, 0.0680431000, 0.1017375000, 0.1807685000, 0.4161220000, 1.0413954000", \ - "0.0801625000, 0.0900277000, 0.1112064000, 0.1543959000, 0.2372528000, 0.4415558000, 1.0482802000", \ - "0.1455418000, 0.1595947000, 0.1892687000, 0.2498985000, 0.3604388000, 0.5750083000, 1.0966820000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0278096000, 0.0352489000, 0.0545574000, 0.1044193000, 0.2337335000, 0.5684989000, 1.4364185000", \ - "0.0278103000, 0.0352934000, 0.0545786000, 0.1043617000, 0.2336175000, 0.5689595000, 1.4357147000", \ - "0.0293467000, 0.0360615000, 0.0544768000, 0.1044947000, 0.2340951000, 0.5694938000, 1.4336570000", \ - "0.0433856000, 0.0484166000, 0.0624729000, 0.1063958000, 0.2337211000, 0.5691969000, 1.4361969000", \ - "0.0699781000, 0.0785379000, 0.0962144000, 0.1316407000, 0.2402452000, 0.5692368000, 1.4359905000", \ - "0.1146256000, 0.1287394000, 0.1575635000, 0.2106785000, 0.3053729000, 0.5815866000, 1.4355471000", \ - "0.1827105000, 0.2058559000, 0.2538142000, 0.3409513000, 0.4860778000, 0.7247740000, 1.4566661000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2b_2") { - leakage_power () { - value : 0.0056295000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0008422000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0014932000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0021284000; - when : "A_N&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__nand2b"; - cell_leakage_power : 0.0025233180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0013780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0097497000, 0.0096540000, 0.0094335000, 0.0094675000, 0.0095460000, 0.0097268000, 0.0101435000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088058000, 0.0087556000, 0.0086401000, 0.0086618000, 0.0087118000, 0.0088272000, 0.0090930000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014380000; - } - pin ("B") { - capacitance : 0.0045610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081022000, 0.0081011000, 0.0080986000, 0.0080958000, 0.0080893000, 0.0080745000, 0.0080402000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008090300, -0.008087800, -0.008082000, -0.008080800, -0.008077900, -0.008071300, -0.008056200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047760000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0067237000, 0.0053247000, 0.0013147000, -0.010461600, -0.046314300, -0.150994700, -0.452984900", \ - "0.0067196000, 0.0053222000, 0.0012892000, -0.010525200, -0.046335000, -0.151008000, -0.452995300", \ - "0.0067777000, 0.0053853000, 0.0013921000, -0.010445100, -0.046276100, -0.150948700, -0.452989300", \ - "0.0065930000, 0.0051868000, 0.0011140000, -0.010700000, -0.046483000, -0.151127500, -0.453104700", \ - "0.0066129000, 0.0051397000, 0.0010050000, -0.011006400, -0.046833200, -0.151337100, -0.453314700", \ - "0.0063889000, 0.0048168000, 0.0005784000, -0.011371100, -0.047110600, -0.151474100, -0.453373800", \ - "0.0080966000, 0.0064455000, 0.0026522000, -0.009974800, -0.047177300, -0.151482600, -0.453308100"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0042823000, 0.0060074000, 0.0107714000, 0.0240456000, 0.0606166000, 0.1647465000, 0.4641019000", \ - "0.0042783000, 0.0059801000, 0.0107827000, 0.0240666000, 0.0606451000, 0.1648295000, 0.4639540000", \ - "0.0042703000, 0.0059750000, 0.0107750000, 0.0239582000, 0.0606132000, 0.1638275000, 0.4612781000", \ - "0.0040869000, 0.0057546000, 0.0104431000, 0.0234884000, 0.0602252000, 0.1645949000, 0.4634520000", \ - "0.0039039000, 0.0055504000, 0.0101668000, 0.0230282000, 0.0594922000, 0.1633280000, 0.4612674000", \ - "0.0041638000, 0.0056750000, 0.0102042000, 0.0227485000, 0.0590912000, 0.1632001000, 0.4633057000", \ - "0.0047347000, 0.0062352000, 0.0105483000, 0.0233987000, 0.0592385000, 0.1640441000, 0.4616750000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0101142000, 0.0087538000, 0.0047468000, -0.007374800, -0.043494000, -0.148308800, -0.450403500", \ - "0.0096401000, 0.0083271000, 0.0044235000, -0.007542700, -0.043566500, -0.148336000, -0.450404900", \ - "0.0091607000, 0.0078368000, 0.0039683000, -0.007873400, -0.043727000, -0.148398600, -0.450421000", \ - "0.0088775000, 0.0074680000, 0.0034919000, -0.008334200, -0.044026800, -0.148531000, -0.450480400", \ - "0.0097316000, 0.0082132000, 0.0037947000, -0.008639700, -0.044359200, -0.148683800, -0.450499300", \ - "0.0102166000, 0.0086474000, 0.0042245000, -0.008352800, -0.044759900, -0.149096200, -0.450739900", \ - "0.0127991000, 0.0111230000, 0.0061789000, -0.007039100, -0.043880100, -0.149033000, -0.450897900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0095861000, 0.0110972000, 0.0154344000, 0.0278450000, 0.0638292000, 0.1671520000, 0.4649060000", \ - "0.0090235000, 0.0105668000, 0.0150106000, 0.0274522000, 0.0636706000, 0.1671866000, 0.4651777000", \ - "0.0085227000, 0.0100074000, 0.0144921000, 0.0271933000, 0.0633760000, 0.1669599000, 0.4651712000", \ - "0.0083518000, 0.0098626000, 0.0142664000, 0.0266451000, 0.0629464000, 0.1665274000, 0.4645184000", \ - "0.0082842000, 0.0098133000, 0.0142015000, 0.0266256000, 0.0626688000, 0.1662971000, 0.4640644000", \ - "0.0089665000, 0.0104215000, 0.0145266000, 0.0274680000, 0.0630885000, 0.1661931000, 0.4638812000", \ - "0.0125867000, 0.0140796000, 0.0180651000, 0.0297299000, 0.0653530000, 0.1678596000, 0.4630959000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.5067580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1373126000, 0.1429783000, 0.1563463000, 0.1863783000, 0.2542455000, 0.4320516000, 0.9420347000", \ - "0.1422674000, 0.1479022000, 0.1615112000, 0.1911778000, 0.2592242000, 0.4370352000, 0.9458713000", \ - "0.1552723000, 0.1609423000, 0.1745254000, 0.2043164000, 0.2720689000, 0.4500777000, 0.9587892000", \ - "0.1866248000, 0.1922585000, 0.2057917000, 0.2355866000, 0.3039166000, 0.4820819000, 0.9896645000", \ - "0.2612448000, 0.2668755000, 0.2803530000, 0.3098964000, 0.3784654000, 0.5567131000, 1.0653392000", \ - "0.3999245000, 0.4068790000, 0.4227897000, 0.4565396000, 0.5274697000, 0.7043331000, 1.2111377000", \ - "0.6171301000, 0.6256751000, 0.6474767000, 0.6897521000, 0.7694350000, 0.9516922000, 1.4590699000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0742828000, 0.0790802000, 0.0913851000, 0.1222470000, 0.2049739000, 0.4398334000, 1.1137955000", \ - "0.0793286000, 0.0841452000, 0.0964487000, 0.1273667000, 0.2100575000, 0.4456132000, 1.1217540000", \ - "0.0909718000, 0.0957755000, 0.1080515000, 0.1388064000, 0.2219125000, 0.4555341000, 1.1284177000", \ - "0.1173957000, 0.1221273000, 0.1342121000, 0.1649850000, 0.2476958000, 0.4816557000, 1.1554520000", \ - "0.1605983000, 0.1658478000, 0.1787991000, 0.2100501000, 0.2926335000, 0.5284226000, 1.2022908000", \ - "0.2173709000, 0.2238623000, 0.2392085000, 0.2722955000, 0.3556635000, 0.5894430000, 1.2670287000", \ - "0.2754416000, 0.2845947000, 0.3049890000, 0.3457147000, 0.4299675000, 0.6641422000, 1.3359904000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0313626000, 0.0354135000, 0.0464054000, 0.0738996000, 0.1514853000, 0.3857029000, 1.0799234000", \ - "0.0313773000, 0.0356292000, 0.0461408000, 0.0739724000, 0.1515227000, 0.3857573000, 1.0796094000", \ - "0.0316428000, 0.0353342000, 0.0464283000, 0.0740156000, 0.1514124000, 0.3850317000, 1.0753756000", \ - "0.0313758000, 0.0355132000, 0.0464762000, 0.0739842000, 0.1516091000, 0.3861997000, 1.0765643000", \ - "0.0322031000, 0.0363811000, 0.0471278000, 0.0748038000, 0.1517538000, 0.3853490000, 1.0745335000", \ - "0.0443205000, 0.0484563000, 0.0586732000, 0.0840634000, 0.1569439000, 0.3863687000, 1.0775162000", \ - "0.0657206000, 0.0709492000, 0.0829666000, 0.1094393000, 0.1760098000, 0.3935490000, 1.0742609000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0234589000, 0.0279362000, 0.0410221000, 0.0796068000, 0.1956748000, 0.5325196000, 1.5043968000", \ - "0.0234454000, 0.0279152000, 0.0409685000, 0.0797893000, 0.1959075000, 0.5323654000, 1.5067576000", \ - "0.0234210000, 0.0279114000, 0.0409405000, 0.0796650000, 0.1952838000, 0.5319070000, 1.4984466000", \ - "0.0240371000, 0.0285162000, 0.0413232000, 0.0799927000, 0.1957972000, 0.5329125000, 1.4996520000", \ - "0.0294239000, 0.0332802000, 0.0453100000, 0.0821875000, 0.1955177000, 0.5329331000, 1.4995443000", \ - "0.0399926000, 0.0439947000, 0.0548138000, 0.0880722000, 0.1977709000, 0.5304515000, 1.5060112000", \ - "0.0578036000, 0.0628792000, 0.0744751000, 0.1049138000, 0.2035837000, 0.5341464000, 1.4962049000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0292365000, 0.0327301000, 0.0420746000, 0.0665055000, 0.1309393000, 0.3085886000, 0.8157918000", \ - "0.0331872000, 0.0367239000, 0.0462518000, 0.0709772000, 0.1354181000, 0.3131318000, 0.8201257000", \ - "0.0406382000, 0.0444975000, 0.0541644000, 0.0789593000, 0.1436159000, 0.3210649000, 0.8295814000", \ - "0.0509996000, 0.0558706000, 0.0679704000, 0.0963052000, 0.1624049000, 0.3407101000, 0.8485478000", \ - "0.0614810000, 0.0690037000, 0.0872854000, 0.1264758000, 0.2058392000, 0.3876838000, 0.8962124000", \ - "0.0601100000, 0.0723878000, 0.1019374000, 0.1635658000, 0.2793129000, 0.4973911000, 1.0123441000", \ - "0.0202667000, 0.0412280000, 0.0881763000, 0.1867455000, 0.3681552000, 0.6830734000, 1.2691088000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0331157000, 0.0367888000, 0.0469238000, 0.0750840000, 0.1536334000, 0.3771613000, 1.0192793000", \ - "0.0380864000, 0.0418093000, 0.0521162000, 0.0800968000, 0.1587924000, 0.3824703000, 1.0239666000", \ - "0.0514530000, 0.0550605000, 0.0653309000, 0.0934245000, 0.1717069000, 0.3958057000, 1.0370704000", \ - "0.0802686000, 0.0851886000, 0.0971540000, 0.1254757000, 0.2043599000, 0.4270536000, 1.0686434000", \ - "0.1265680000, 0.1343658000, 0.1536895000, 0.1958626000, 0.2789213000, 0.5010987000, 1.1468703000", \ - "0.2013978000, 0.2135198000, 0.2438307000, 0.3115241000, 0.4391961000, 0.6753007000, 1.3151973000", \ - "0.3290966000, 0.3469995000, 0.3917429000, 0.4970683000, 0.7023057000, 1.0583511000, 1.7133267000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0159279000, 0.0201609000, 0.0318187000, 0.0628929000, 0.1470061000, 0.3838427000, 1.0754756000", \ - "0.0159613000, 0.0201859000, 0.0319140000, 0.0635629000, 0.1469999000, 0.3838250000, 1.0763402000", \ - "0.0177218000, 0.0215114000, 0.0324087000, 0.0626527000, 0.1463796000, 0.3849668000, 1.0754139000", \ - "0.0236717000, 0.0281149000, 0.0391718000, 0.0664541000, 0.1472746000, 0.3838546000, 1.0738461000", \ - "0.0389920000, 0.0442813000, 0.0572403000, 0.0871081000, 0.1600392000, 0.3870322000, 1.0755529000", \ - "0.0713536000, 0.0786613000, 0.0962532000, 0.1348607000, 0.2157459000, 0.4172020000, 1.0715859000", \ - "0.1372444000, 0.1466572000, 0.1703960000, 0.2241442000, 0.3321217000, 0.5516077000, 1.1265455000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0277425000, 0.0323791000, 0.0456776000, 0.0835871000, 0.1936377000, 0.5118364000, 1.4329896000", \ - "0.0277352000, 0.0323394000, 0.0457235000, 0.0835119000, 0.1940014000, 0.5110675000, 1.4284985000", \ - "0.0289601000, 0.0330114000, 0.0455232000, 0.0836698000, 0.1936343000, 0.5116298000, 1.4270706000", \ - "0.0424626000, 0.0457227000, 0.0551106000, 0.0865336000, 0.1936983000, 0.5119767000, 1.4284578000", \ - "0.0679248000, 0.0734987000, 0.0868352000, 0.1158648000, 0.2027583000, 0.5115336000, 1.4338412000", \ - "0.1103514000, 0.1197515000, 0.1424574000, 0.1876723000, 0.2718171000, 0.5288760000, 1.4307099000", \ - "0.1775857000, 0.1923572000, 0.2308233000, 0.3062476000, 0.4419571000, 0.6791008000, 1.4477058000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand2b_4") { - leakage_power () { - value : 0.0074245000; - when : "!A_N&B"; - } - leakage_power () { - value : 0.0017623000; - when : "!A_N&!B"; - } - leakage_power () { - value : 0.0123756000; - when : "A_N&B"; - } - leakage_power () { - value : 0.0106382000; - when : "A_N&!B"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__nand2b"; - cell_leakage_power : 0.0080501840; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0023730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0176582000, 0.0175297000, 0.0172334000, 0.0173690000, 0.0176813000, 0.0184015000, 0.0200615000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0176654000, 0.0175429000, 0.0172606000, 0.0173750000, 0.0176386000, 0.0182463000, 0.0196470000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024790000; - } - pin ("B") { - capacitance : 0.0088640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0084170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158752000, 0.0158640000, 0.0158382000, 0.0158380000, 0.0158373000, 0.0158360000, 0.0158329000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015794700, -0.015793200, -0.015789900, -0.015787200, -0.015781200, -0.015767000, -0.015734400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0093110000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0156624000, 0.0140941000, 0.0090908000, -0.007477500, -0.063115700, -0.244622800, -0.824375400", \ - "0.0157033000, 0.0140331000, 0.0089831000, -0.007415700, -0.063211600, -0.244661400, -0.824539900", \ - "0.0156573000, 0.0142001000, 0.0091093000, -0.007535900, -0.063138000, -0.244579700, -0.824309200", \ - "0.0153140000, 0.0137157000, 0.0085425000, -0.008130600, -0.063824300, -0.245067500, -0.824730400", \ - "0.0147123000, 0.0130673000, 0.0078441000, -0.009036100, -0.064487500, -0.245594600, -0.825140800", \ - "0.0148539000, 0.0130876000, 0.0074989000, -0.009906700, -0.065402500, -0.246258200, -0.825515300", \ - "0.0171217000, 0.0154010000, 0.0096854000, -0.009047800, -0.064558400, -0.245494900, -0.824604100"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0076721000, 0.0095913000, 0.0158126000, 0.0350094000, 0.0932393000, 0.2743382000, 0.8437075000", \ - "0.0076663000, 0.0095824000, 0.0158543000, 0.0350309000, 0.0933620000, 0.2757028000, 0.8528079000", \ - "0.0077015000, 0.0096769000, 0.0158983000, 0.0350825000, 0.0932909000, 0.2744842000, 0.8431699000", \ - "0.0073175000, 0.0092290000, 0.0151565000, 0.0341297000, 0.0923967000, 0.2721696000, 0.8433740000", \ - "0.0068305000, 0.0087094000, 0.0147492000, 0.0332674000, 0.0907833000, 0.2738332000, 0.8455731000", \ - "0.0075739000, 0.0093764000, 0.0150936000, 0.0334669000, 0.0908854000, 0.2702991000, 0.8469875000", \ - "0.0085631000, 0.0102334000, 0.0157836000, 0.0338046000, 0.0904490000, 0.2719623000, 0.8415233000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0216865000, 0.0200904000, 0.0149363000, -0.002228100, -0.058887000, -0.240861500, -0.820772000", \ - "0.0207127000, 0.0192330000, 0.0142317000, -0.002638400, -0.059069500, -0.240907500, -0.820826100", \ - "0.0197897000, 0.0182525000, 0.0132671000, -0.003389600, -0.059428900, -0.241057900, -0.820858500", \ - "0.0191401000, 0.0175050000, 0.0123369000, -0.004431400, -0.060070500, -0.241305800, -0.820963400", \ - "0.0204023000, 0.0186675000, 0.0131350000, -0.004842000, -0.060812600, -0.241672200, -0.821006500", \ - "0.0210956000, 0.0193253000, 0.0136022000, -0.004331400, -0.061591300, -0.242506600, -0.821477200", \ - "0.0258804000, 0.0238534000, 0.0175373000, -0.001507100, -0.059733900, -0.242479000, -0.821861300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015924560, 0.0050718310, 0.0161533300, 0.0514469400, 0.1638540000, 0.5218604000"); - values("0.0169458000, 0.0187579000, 0.0243654000, 0.0421865000, 0.0988931000, 0.2783822000, 0.8506821000", \ - "0.0158744000, 0.0177000000, 0.0234797000, 0.0415565000, 0.0984001000, 0.2781501000, 0.8504522000", \ - "0.0149634000, 0.0167086000, 0.0225634000, 0.0408304000, 0.0977040000, 0.2782409000, 0.8500685000", \ - "0.0146278000, 0.0163613000, 0.0220604000, 0.0395543000, 0.0968931000, 0.2773301000, 0.8499750000", \ - "0.0148263000, 0.0165840000, 0.0223552000, 0.0401770000, 0.0968119000, 0.2765905000, 0.8491048000", \ - "0.0160928000, 0.0174319000, 0.0230810000, 0.0414308000, 0.0976613000, 0.2770913000, 0.8462801000", \ - "0.0221717000, 0.0238915000, 0.0288770000, 0.0461137000, 0.1013310000, 0.2794271000, 0.8500683000"); - } - } - max_capacitance : 0.5218600000; - max_transition : 1.4991030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.1083051000, 0.1116210000, 0.1205516000, 0.1431613000, 0.2004808000, 0.3667021000, 0.8903043000", \ - "0.1133032000, 0.1165068000, 0.1254381000, 0.1481624000, 0.2053856000, 0.3714277000, 0.8975435000", \ - "0.1260659000, 0.1292988000, 0.1383576000, 0.1609064000, 0.2182024000, 0.3844591000, 0.9082937000", \ - "0.1563434000, 0.1595551000, 0.1679989000, 0.1906056000, 0.2484255000, 0.4148123000, 0.9457169000", \ - "0.2225588000, 0.2259719000, 0.2352498000, 0.2582786000, 0.3152509000, 0.4815864000, 1.0113127000", \ - "0.3275312000, 0.3318706000, 0.3437149000, 0.3709735000, 0.4323844000, 0.5998828000, 1.1234357000", \ - "0.4806609000, 0.4862441000, 0.5016901000, 0.5355982000, 0.6078615000, 0.7776553000, 1.3015262000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0843545000, 0.0875884000, 0.0968363000, 0.1221187000, 0.1937091000, 0.4135258000, 1.1119030000", \ - "0.0889025000, 0.0921256000, 0.1014453000, 0.1267207000, 0.1983615000, 0.4190093000, 1.1147979000", \ - "0.1005804000, 0.1037727000, 0.1130484000, 0.1382630000, 0.2097647000, 0.4293877000, 1.1261838000", \ - "0.1271068000, 0.1302729000, 0.1392963000, 0.1643246000, 0.2358269000, 0.4557442000, 1.1543309000", \ - "0.1744893000, 0.1780108000, 0.1878822000, 0.2134632000, 0.2847226000, 0.5061147000, 1.2096035000", \ - "0.2370352000, 0.2416065000, 0.2535691000, 0.2819176000, 0.3542948000, 0.5734820000, 1.2721123000", \ - "0.3101174000, 0.3160898000, 0.3319615000, 0.3677693000, 0.4439785000, 0.6636187000, 1.3587810000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0261534000, 0.0287628000, 0.0361036000, 0.0576963000, 0.1246321000, 0.3477024000, 1.0630231000", \ - "0.0263722000, 0.0285670000, 0.0362249000, 0.0576510000, 0.1244952000, 0.3461888000, 1.0646345000", \ - "0.0261695000, 0.0285594000, 0.0362085000, 0.0576357000, 0.1246967000, 0.3478410000, 1.0664295000", \ - "0.0261464000, 0.0285730000, 0.0361397000, 0.0576704000, 0.1246442000, 0.3468898000, 1.0705132000", \ - "0.0297006000, 0.0319888000, 0.0389472000, 0.0596884000, 0.1255141000, 0.3463984000, 1.0717541000", \ - "0.0424422000, 0.0450511000, 0.0520792000, 0.0720590000, 0.1331703000, 0.3484215000, 1.0666544000", \ - "0.0618406000, 0.0652095000, 0.0742498000, 0.0953354000, 0.1520275000, 0.3546235000, 1.0642442000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0249635000, 0.0277742000, 0.0367075000, 0.0655451000, 0.1611982000, 0.4738257000, 1.4641484000", \ - "0.0249960000, 0.0278687000, 0.0366649000, 0.0652589000, 0.1614707000, 0.4730165000, 1.4725989000", \ - "0.0249974000, 0.0277571000, 0.0367524000, 0.0655438000, 0.1615061000, 0.4719533000, 1.4601752000", \ - "0.0252391000, 0.0280790000, 0.0370724000, 0.0656001000, 0.1614429000, 0.4718380000, 1.4609636000", \ - "0.0307025000, 0.0333919000, 0.0413620000, 0.0683797000, 0.1618569000, 0.4743814000, 1.4687180000", \ - "0.0419960000, 0.0445657000, 0.0521381000, 0.0763472000, 0.1650198000, 0.4716559000, 1.4666497000", \ - "0.0594822000, 0.0631011000, 0.0717917000, 0.0963949000, 0.1740728000, 0.4753735000, 1.4601892000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0286923000, 0.0308930000, 0.0373652000, 0.0563122000, 0.1102508000, 0.2758156000, 0.8002875000", \ - "0.0323494000, 0.0345715000, 0.0412029000, 0.0601376000, 0.1145817000, 0.2805311000, 0.8039358000", \ - "0.0387506000, 0.0412936000, 0.0483027000, 0.0674315000, 0.1221922000, 0.2880777000, 0.8117448000", \ - "0.0473206000, 0.0505264000, 0.0593173000, 0.0820514000, 0.1390078000, 0.3058912000, 0.8297006000", \ - "0.0547559000, 0.0595077000, 0.0728500000, 0.1051542000, 0.1766774000, 0.3491105000, 0.8819062000", \ - "0.0466456000, 0.0551237000, 0.0761572000, 0.1276923000, 0.2336545000, 0.4467642000, 0.9820028000", \ - "-0.007934700, 0.0047214000, 0.0402004000, 0.1230616000, 0.2912324000, 0.6003157000, 1.2160286000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0350341000, 0.0374855000, 0.0450599000, 0.0681269000, 0.1386658000, 0.3594898000, 1.0599726000", \ - "0.0400257000, 0.0424585000, 0.0501422000, 0.0734224000, 0.1441108000, 0.3647773000, 1.0665605000", \ - "0.0533817000, 0.0557986000, 0.0634206000, 0.0865814000, 0.1576222000, 0.3786100000, 1.0803024000", \ - "0.0834451000, 0.0865234000, 0.0955144000, 0.1179894000, 0.1893222000, 0.4107555000, 1.1104686000", \ - "0.1326079000, 0.1375556000, 0.1514039000, 0.1872180000, 0.2647520000, 0.4849166000, 1.1892285000", \ - "0.2138364000, 0.2213407000, 0.2438813000, 0.3008411000, 0.4219737000, 0.6602098000, 1.3575203000", \ - "0.3550716000, 0.3667530000, 0.3997349000, 0.4875213000, 0.6795591000, 1.0423203000, 1.7606682000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0156844000, 0.0182276000, 0.0263284000, 0.0502427000, 0.1217419000, 0.3470888000, 1.0673852000", \ - "0.0155962000, 0.0183300000, 0.0264748000, 0.0502231000, 0.1214846000, 0.3471204000, 1.0631419000", \ - "0.0175817000, 0.0199064000, 0.0272949000, 0.0502230000, 0.1218415000, 0.3463827000, 1.0629750000", \ - "0.0232440000, 0.0259208000, 0.0338132000, 0.0556245000, 0.1228135000, 0.3467251000, 1.0646988000", \ - "0.0385178000, 0.0417609000, 0.0511802000, 0.0751355000, 0.1391426000, 0.3489632000, 1.0710223000", \ - "0.0707754000, 0.0753247000, 0.0880898000, 0.1191874000, 0.1907804000, 0.3841566000, 1.0679386000", \ - "0.1365430000, 0.1419335000, 0.1583173000, 0.2023194000, 0.2990361000, 0.5122320000, 1.1250710000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015924600, 0.0050718300, 0.0161533000, 0.0514469000, 0.1638540000, 0.5218600000"); - values("0.0294602000, 0.0324531000, 0.0419503000, 0.0724992000, 0.1703067000, 0.4830026000, 1.4796768000", \ - "0.0294566000, 0.0324519000, 0.0419934000, 0.0726573000, 0.1705701000, 0.4837141000, 1.4815613000", \ - "0.0301745000, 0.0329119000, 0.0419244000, 0.0725406000, 0.1704209000, 0.4824743000, 1.4839647000", \ - "0.0428537000, 0.0449885000, 0.0515621000, 0.0766640000, 0.1704797000, 0.4835279000, 1.4817015000", \ - "0.0680631000, 0.0716728000, 0.0819767000, 0.1067139000, 0.1823108000, 0.4832638000, 1.4821409000", \ - "0.1100001000, 0.1168482000, 0.1327108000, 0.1730013000, 0.2546311000, 0.5018374000, 1.4794389000", \ - "0.1774334000, 0.1864103000, 0.2149986000, 0.2803801000, 0.4121637000, 0.6554611000, 1.4991034000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3_1") { - leakage_power () { - value : 3.9563455e-05; - when : "!A&!B&C"; - } - leakage_power () { - value : 2.2629071e-05; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0003124000; - when : "!A&B&C"; - } - leakage_power () { - value : 3.3721618e-05; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0003155000; - when : "A&!B&C"; - } - leakage_power () { - value : 3.9362278e-05; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0072118000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0002441000; - when : "A&B&!C"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__nand3"; - cell_leakage_power : 0.0010273980; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047191000, 0.0047175000, 0.0047138000, 0.0047132000, 0.0047118000, 0.0047086000, 0.0047012000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003710200, -0.003710900, -0.003712400, -0.003705900, -0.003691100, -0.003656800, -0.003577900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023500000; - } - pin ("B") { - capacitance : 0.0023950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046823000, 0.0046797000, 0.0046735000, 0.0046881000, 0.0047217000, 0.0047992000, 0.0049777000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004277300, -0.004276300, -0.004274200, -0.004273500, -0.004271800, -0.004268000, -0.004259200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024800000; - } - pin ("C") { - capacitance : 0.0023550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042441000, 0.0042416000, 0.0042358000, 0.0042366000, 0.0042385000, 0.0042429000, 0.0042530000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004235400, -0.004234300, -0.004231800, -0.004231800, -0.004231700, -0.004231600, -0.004231400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024630000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0040389000, 0.0028229000, -0.000390000, -0.008812500, -0.030638400, -0.086973800, -0.232192500", \ - "0.0037998000, 0.0026083000, -0.000540500, -0.008888700, -0.030675500, -0.086981700, -0.232207700", \ - "0.0034980000, 0.0023198000, -0.000777400, -0.009054800, -0.030757200, -0.087030400, -0.232187800", \ - "0.0033268000, 0.0020921000, -0.001035800, -0.009307500, -0.030924200, -0.087115100, -0.232255300", \ - "0.0033132000, 0.0020324000, -0.001190300, -0.009505700, -0.031146400, -0.087245800, -0.232309400", \ - "0.0041714000, 0.0028462000, -0.000768100, -0.009460000, -0.031078800, -0.087335900, -0.232401000", \ - "0.0061083000, 0.0045898000, 0.0007152000, -0.008121400, -0.030221100, -0.086967700, -0.232341000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0049724000, 0.0063580000, 0.0097794000, 0.0182321000, 0.0400204000, 0.0961776000, 0.2402407000", \ - "0.0047243000, 0.0061326000, 0.0096109000, 0.0182296000, 0.0401171000, 0.0962396000, 0.2389282000", \ - "0.0044325000, 0.0058099000, 0.0093270000, 0.0179401000, 0.0398274000, 0.0958919000, 0.2398397000", \ - "0.0043419000, 0.0056543000, 0.0090018000, 0.0176053000, 0.0395900000, 0.0957571000, 0.2393707000", \ - "0.0045716000, 0.0058094000, 0.0090809000, 0.0174908000, 0.0393667000, 0.0949975000, 0.2398112000", \ - "0.0049867000, 0.0062006000, 0.0094066000, 0.0179938000, 0.0393021000, 0.0952260000, 0.2379558000", \ - "0.0069489000, 0.0079768000, 0.0109760000, 0.0189444000, 0.0400244000, 0.0957222000, 0.2393712000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0047156000, 0.0034948000, 0.0002617000, -0.008181500, -0.030017900, -0.086350700, -0.231583200", \ - "0.0045162000, 0.0033187000, 0.0001344000, -0.008255200, -0.030043700, -0.086374900, -0.231600700", \ - "0.0042355000, 0.0030533000, -8.79000e-05, -0.008390400, -0.030120400, -0.086398100, -0.231610500", \ - "0.0039665000, 0.0027590000, -0.000376000, -0.008624800, -0.030255800, -0.086471800, -0.231637400", \ - "0.0038275000, 0.0025722000, -0.000614300, -0.008899600, -0.030491600, -0.086590700, -0.231705000", \ - "0.0040735000, 0.0027739000, -0.000461400, -0.008971400, -0.030669500, -0.086781400, -0.231812000", \ - "0.0051577000, 0.0037573000, 0.0003044000, -0.008384600, -0.030363100, -0.086817000, -0.231884900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0079217000, 0.0092369000, 0.0125723000, 0.0210293000, 0.0426649000, 0.0982602000, 0.2411447000", \ - "0.0076619000, 0.0089990000, 0.0123841000, 0.0208331000, 0.0425676000, 0.0981759000, 0.2411432000", \ - "0.0073810000, 0.0087327000, 0.0121427000, 0.0207145000, 0.0423961000, 0.0980883000, 0.2414673000", \ - "0.0071009000, 0.0083961000, 0.0117657000, 0.0203730000, 0.0419375000, 0.0978958000, 0.2412653000", \ - "0.0070978000, 0.0083632000, 0.0117758000, 0.0200926000, 0.0415334000, 0.0972219000, 0.2404522000", \ - "0.0074863000, 0.0087309000, 0.0121500000, 0.0206197000, 0.0419502000, 0.0972990000, 0.2410325000", \ - "0.0088803000, 0.0100294000, 0.0130650000, 0.0212011000, 0.0425639000, 0.0983098000, 0.2408576000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0045376000, 0.0032910000, 5.580000e-05, -0.008376100, -0.030214400, -0.086541600, -0.231788700", \ - "0.0043376000, 0.0031299000, -6.91000e-05, -0.008446900, -0.030239600, -0.086560000, -0.231785800", \ - "0.0040566000, 0.0028649000, -0.000279600, -0.008585200, -0.030314100, -0.086590400, -0.231797100", \ - "0.0038048000, 0.0026030000, -0.000568100, -0.008824700, -0.030460800, -0.086665500, -0.231821700", \ - "0.0037686000, 0.0024859000, -0.000789900, -0.009068100, -0.030691400, -0.086803400, -0.231888200", \ - "0.0038700000, 0.0026041000, -0.000673000, -0.009109000, -0.030859900, -0.086982700, -0.231990200", \ - "0.0049139000, 0.0035317000, 7.050000e-05, -0.008579900, -0.030579400, -0.087001400, -0.232071500"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0106438000, 0.0119397000, 0.0152510000, 0.0237657000, 0.0453681000, 0.1011930000, 0.2442714000", \ - "0.0104526000, 0.0117513000, 0.0150900000, 0.0235846000, 0.0453301000, 0.1009850000, 0.2441920000", \ - "0.0102309000, 0.0115460000, 0.0149140000, 0.0235002000, 0.0451530000, 0.1009137000, 0.2441936000", \ - "0.0100419000, 0.0113680000, 0.0147026000, 0.0232759000, 0.0451218000, 0.1008181000, 0.2438005000", \ - "0.0101062000, 0.0113911000, 0.0147070000, 0.0231845000, 0.0450552000, 0.1002854000, 0.2429748000", \ - "0.0104859000, 0.0117178000, 0.0150360000, 0.0234764000, 0.0449209000, 0.0996018000, 0.2427886000", \ - "0.0126352000, 0.0137597000, 0.0168558000, 0.0248819000, 0.0468975000, 0.1009216000, 0.2449268000"); - } - } - max_capacitance : 0.1464940000; - max_transition : 1.4958090000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0319453000, 0.0377438000, 0.0522698000, 0.0886064000, 0.1842952000, 0.4248309000, 1.0446726000", \ - "0.0352240000, 0.0410559000, 0.0556452000, 0.0923954000, 0.1882067000, 0.4272266000, 1.0450919000", \ - "0.0443876000, 0.0499941000, 0.0648342000, 0.1021642000, 0.1958182000, 0.4363752000, 1.0617024000", \ - "0.0596980000, 0.0682277000, 0.0868967000, 0.1237350000, 0.2182345000, 0.4592172000, 1.0871873000", \ - "0.0769958000, 0.0894973000, 0.1171790000, 0.1711709000, 0.2714910000, 0.5119409000, 1.1308345000", \ - "0.0896703000, 0.1080718000, 0.1494097000, 0.2309335000, 0.3749126000, 0.6360509000, 1.2567627000", \ - "0.0804976000, 0.1082180000, 0.1694053000, 0.2912025000, 0.5144584000, 0.8864768000, 1.5416515000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0316862000, 0.0372976000, 0.0513602000, 0.0861792000, 0.1769890000, 0.4052028000, 0.9968641000", \ - "0.0366843000, 0.0423816000, 0.0563464000, 0.0914559000, 0.1816574000, 0.4114003000, 1.0061821000", \ - "0.0496193000, 0.0551823000, 0.0692896000, 0.1045346000, 0.1943795000, 0.4214344000, 1.0126181000", \ - "0.0754047000, 0.0833148000, 0.1000646000, 0.1351976000, 0.2248985000, 0.4556733000, 1.0387884000", \ - "0.1148888000, 0.1277284000, 0.1545216000, 0.2051712000, 0.2963212000, 0.5239917000, 1.1105296000", \ - "0.1772345000, 0.1965221000, 0.2403520000, 0.3212103000, 0.4603758000, 0.6939099000, 1.2724205000", \ - "0.2801860000, 0.3096663000, 0.3751834000, 0.5021358000, 0.7225039000, 1.0689728000, 1.6669134000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0294798000, 0.0368112000, 0.0558995000, 0.1042707000, 0.2298789000, 0.5526462000, 1.3863796000", \ - "0.0292983000, 0.0367031000, 0.0556156000, 0.1042574000, 0.2299837000, 0.5535623000, 1.3811413000", \ - "0.0315650000, 0.0379121000, 0.0556148000, 0.1041806000, 0.2292336000, 0.5500126000, 1.3856789000", \ - "0.0438998000, 0.0505898000, 0.0662104000, 0.1075041000, 0.2292271000, 0.5502286000, 1.3847780000", \ - "0.0679901000, 0.0770903000, 0.0969420000, 0.1379645000, 0.2398893000, 0.5511912000, 1.3800473000", \ - "0.1098868000, 0.1233710000, 0.1519781000, 0.2079397000, 0.3170524000, 0.5779455000, 1.3818504000", \ - "0.1841412000, 0.2029371000, 0.2468173000, 0.3276150000, 0.4799489000, 0.7481190000, 1.4292552000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0271069000, 0.0345000000, 0.0535741000, 0.1026657000, 0.2302502000, 0.5568992000, 1.3990794000", \ - "0.0270927000, 0.0345104000, 0.0536561000, 0.1028342000, 0.2297713000, 0.5574791000, 1.3971591000", \ - "0.0292043000, 0.0354167000, 0.0535334000, 0.1026310000, 0.2298375000, 0.5562986000, 1.3984249000", \ - "0.0448543000, 0.0496264000, 0.0627416000, 0.1043419000, 0.2291050000, 0.5594820000, 1.3890313000", \ - "0.0736110000, 0.0816978000, 0.0991204000, 0.1335046000, 0.2357154000, 0.5540491000, 1.4017806000", \ - "0.1210566000, 0.1342113000, 0.1619678000, 0.2125574000, 0.3056531000, 0.5684269000, 1.3957574000", \ - "0.1997629000, 0.2189788000, 0.2639110000, 0.3466731000, 0.4876043000, 0.7213956000, 1.4222230000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0406289000, 0.0464391000, 0.0609391000, 0.0971056000, 0.1904577000, 0.4335319000, 1.0562137000", \ - "0.0443396000, 0.0501485000, 0.0647947000, 0.1012509000, 0.1960863000, 0.4349576000, 1.0542816000", \ - "0.0524670000, 0.0583860000, 0.0731066000, 0.1103002000, 0.2039276000, 0.4442704000, 1.0634125000", \ - "0.0671095000, 0.0745960000, 0.0921406000, 0.1303156000, 0.2262235000, 0.4658775000, 1.0850284000", \ - "0.0854939000, 0.0967018000, 0.1213991000, 0.1711788000, 0.2733060000, 0.5161515000, 1.1381928000", \ - "0.0975568000, 0.1152910000, 0.1539255000, 0.2292099000, 0.3671241000, 0.6268299000, 1.2537316000", \ - "0.0804313000, 0.1081579000, 0.1683698000, 0.2858672000, 0.4932023000, 0.8444722000, 1.5061851000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0436773000, 0.0494889000, 0.0642132000, 0.1014763000, 0.1961162000, 0.4390322000, 1.0658833000", \ - "0.0486088000, 0.0546200000, 0.0695334000, 0.1067081000, 0.2015716000, 0.4447564000, 1.0697195000", \ - "0.0616315000, 0.0674714000, 0.0823017000, 0.1192830000, 0.2140980000, 0.4570315000, 1.0829955000", \ - "0.0923331000, 0.0989848000, 0.1140178000, 0.1513446000, 0.2453205000, 0.4887300000, 1.1151920000", \ - "0.1447818000, 0.1552644000, 0.1785545000, 0.2252695000, 0.3183359000, 0.5607720000, 1.1858149000", \ - "0.2293291000, 0.2464214000, 0.2843002000, 0.3587377000, 0.4888099000, 0.7322811000, 1.3544313000", \ - "0.3678712000, 0.3950409000, 0.4535604000, 0.5724827000, 0.7857862000, 1.1289595000, 1.7593582000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0295293000, 0.0368797000, 0.0559390000, 0.1042661000, 0.2290997000, 0.5531403000, 1.3850104000", \ - "0.0295273000, 0.0369445000, 0.0559180000, 0.1043097000, 0.2327733000, 0.5497748000, 1.3782170000", \ - "0.0306801000, 0.0376189000, 0.0557835000, 0.1042330000, 0.2291727000, 0.5505186000, 1.3783978000", \ - "0.0399390000, 0.0465156000, 0.0624095000, 0.1065132000, 0.2305275000, 0.5512835000, 1.3780520000", \ - "0.0611155000, 0.0685222000, 0.0863874000, 0.1278048000, 0.2366355000, 0.5509610000, 1.3861642000", \ - "0.1017842000, 0.1123605000, 0.1357116000, 0.1857420000, 0.2927402000, 0.5689484000, 1.3882619000", \ - "0.1749947000, 0.1902006000, 0.2230991000, 0.2916362000, 0.4238009000, 0.6918330000, 1.4168340000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0362275000, 0.0441682000, 0.0641851000, 0.1161362000, 0.2496292000, 0.5931590000, 1.4834178000", \ - "0.0362464000, 0.0440387000, 0.0644423000, 0.1161077000, 0.2493075000, 0.5920883000, 1.4795231000", \ - "0.0363228000, 0.0440343000, 0.0641587000, 0.1161813000, 0.2496435000, 0.5934598000, 1.4794068000", \ - "0.0470988000, 0.0526728000, 0.0689484000, 0.1166232000, 0.2496101000, 0.5935882000, 1.4818977000", \ - "0.0778809000, 0.0851201000, 0.1021936000, 0.1378838000, 0.2538530000, 0.5948581000, 1.4831407000", \ - "0.1286363000, 0.1412767000, 0.1678772000, 0.2179476000, 0.3116088000, 0.6029978000, 1.4778241000", \ - "0.2096402000, 0.2305904000, 0.2746629000, 0.3554504000, 0.4947842000, 0.7370753000, 1.4958088000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0443021000, 0.0498949000, 0.0643063000, 0.1007762000, 0.1943447000, 0.4358107000, 1.0648027000", \ - "0.0480888000, 0.0538980000, 0.0683839000, 0.1050091000, 0.1992241000, 0.4399845000, 1.0573629000", \ - "0.0559065000, 0.0617110000, 0.0765190000, 0.1133255000, 0.2081532000, 0.4498804000, 1.0664905000", \ - "0.0700531000, 0.0768174000, 0.0930448000, 0.1307730000, 0.2264347000, 0.4667815000, 1.0857097000", \ - "0.0898380000, 0.0995133000, 0.1203484000, 0.1663712000, 0.2650241000, 0.5086155000, 1.1265072000", \ - "0.1069104000, 0.1222715000, 0.1547885000, 0.2195711000, 0.3470688000, 0.6001952000, 1.2227903000", \ - "0.0995032000, 0.1231001000, 0.1760309000, 0.2785397000, 0.4600246000, 0.7835908000, 1.4370188000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0449216000, 0.0502660000, 0.0638893000, 0.0978680000, 0.1842738000, 0.4037659000, 0.9686695000", \ - "0.0500441000, 0.0555216000, 0.0691254000, 0.1032822000, 0.1893045000, 0.4090991000, 0.9749198000", \ - "0.0632304000, 0.0688075000, 0.0825403000, 0.1167161000, 0.2024716000, 0.4222031000, 0.9861345000", \ - "0.0944604000, 0.1002378000, 0.1140172000, 0.1480533000, 0.2343110000, 0.4541642000, 1.0179684000", \ - "0.1485719000, 0.1577883000, 0.1786031000, 0.2201581000, 0.3069904000, 0.5244339000, 1.0877236000", \ - "0.2331197000, 0.2478347000, 0.2812257000, 0.3489563000, 0.4721509000, 0.6912877000, 1.2520153000", \ - "0.3679455000, 0.3905762000, 0.4425076000, 0.5509016000, 0.7501617000, 1.0750988000, 1.6502485000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0295615000, 0.0368470000, 0.0556697000, 0.1041762000, 0.2290151000, 0.5533252000, 1.3905794000", \ - "0.0295171000, 0.0368519000, 0.0556693000, 0.1042929000, 0.2300540000, 0.5536268000, 1.3821309000", \ - "0.0299954000, 0.0370850000, 0.0558700000, 0.1044956000, 0.2298897000, 0.5526362000, 1.3802101000", \ - "0.0362173000, 0.0430356000, 0.0596944000, 0.1058187000, 0.2305774000, 0.5528308000, 1.3824087000", \ - "0.0530973000, 0.0602746000, 0.0775768000, 0.1214125000, 0.2343288000, 0.5514536000, 1.3823170000", \ - "0.0899138000, 0.0993004000, 0.1194378000, 0.1657398000, 0.2792014000, 0.5635171000, 1.3821018000", \ - "0.1631292000, 0.1745675000, 0.2024353000, 0.2607207000, 0.3825281000, 0.6640135000, 1.4076199000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0395250000, 0.0465698000, 0.0649283000, 0.1119676000, 0.2330105000, 0.5443764000, 1.3497121000", \ - "0.0393854000, 0.0465392000, 0.0647444000, 0.1118328000, 0.2327951000, 0.5451549000, 1.3532557000", \ - "0.0392031000, 0.0463100000, 0.0647777000, 0.1119099000, 0.2327637000, 0.5446375000, 1.3475066000", \ - "0.0484293000, 0.0541659000, 0.0693499000, 0.1123638000, 0.2330199000, 0.5449270000, 1.3516811000", \ - "0.0790231000, 0.0861224000, 0.1013202000, 0.1357917000, 0.2380194000, 0.5447787000, 1.3495897000", \ - "0.1297362000, 0.1418949000, 0.1664909000, 0.2139158000, 0.3003946000, 0.5605428000, 1.3484101000", \ - "0.2113828000, 0.2301851000, 0.2724642000, 0.3514508000, 0.4854391000, 0.7054011000, 1.3779615000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3_2") { - leakage_power () { - value : 7.3749221e-05; - when : "!A&!B&C"; - } - leakage_power () { - value : 4.0589155e-05; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0007599000; - when : "!A&B&C"; - } - leakage_power () { - value : 6.3265392e-05; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0005963000; - when : "A&!B&C"; - } - leakage_power () { - value : 7.346556e-05; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0143381000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0004622000; - when : "A&B&!C"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__nand3"; - cell_leakage_power : 0.0020509380; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091506000, 0.0091481000, 0.0091423000, 0.0091413000, 0.0091390000, 0.0091337000, 0.0091214000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006448600, -0.006436400, -0.006408200, -0.006390300, -0.006349000, -0.006253700, -0.006034100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044250000; - } - pin ("B") { - capacitance : 0.0044680000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088433000, 0.0088373000, 0.0088234000, 0.0088570000, 0.0089344000, 0.0091128000, 0.0095241000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008138600, -0.008132700, -0.008119300, -0.008115900, -0.008108100, -0.008090100, -0.008048600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045990000; - } - pin ("C") { - capacitance : 0.0045040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080990000, 0.0080989000, 0.0080987000, 0.0081015000, 0.0081080000, 0.0081230000, 0.0081577000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008100000, -0.008095900, -0.008086200, -0.008085400, -0.008083600, -0.008079400, -0.008069700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047260000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0064606000, 0.0050607000, 0.0010403000, -0.010726400, -0.044523500, -0.140626000, -0.413315200", \ - "0.0059735000, 0.0046191000, 0.0006722000, -0.010939000, -0.044624600, -0.140703900, -0.413322600", \ - "0.0054157000, 0.0040405000, 0.0001745000, -0.011347900, -0.044823800, -0.140773200, -0.413405000", \ - "0.0050841000, 0.0036925000, -0.000280100, -0.011846300, -0.045165900, -0.140954200, -0.413479300", \ - "0.0051916000, 0.0036973000, -0.000488200, -0.012167100, -0.045593600, -0.141244100, -0.413634200", \ - "0.0065457000, 0.0049628000, 0.0005852000, -0.011401500, -0.045576500, -0.141513300, -0.413835100", \ - "0.0099423000, 0.0082840000, 0.0034990000, -0.009476900, -0.044228200, -0.141272100, -0.413972800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0063344000, 0.0080346000, 0.0126016000, 0.0248150000, 0.0586394000, 0.1547690000, 0.4235775000", \ - "0.0058696000, 0.0076006000, 0.0122269000, 0.0245681000, 0.0583052000, 0.1546885000, 0.4224418000", \ - "0.0055172000, 0.0071464000, 0.0117259000, 0.0241093000, 0.0582964000, 0.1543834000, 0.4211328000", \ - "0.0054060000, 0.0069265000, 0.0111559000, 0.0236133000, 0.0577305000, 0.1534508000, 0.4244446000", \ - "0.0059226000, 0.0073570000, 0.0114915000, 0.0233474000, 0.0569715000, 0.1533815000, 0.4246675000", \ - "0.0064383000, 0.0078221000, 0.0118648000, 0.0241727000, 0.0573406000, 0.1528684000, 0.4244126000", \ - "0.0105631000, 0.0116701000, 0.0152743000, 0.0264289000, 0.0590227000, 0.1541548000, 0.4242567000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0084771000, 0.0070583000, 0.0029780000, -0.008847300, -0.042666900, -0.138766100, -0.411447700", \ - "0.0080288000, 0.0066434000, 0.0026615000, -0.009018600, -0.042739600, -0.138805200, -0.411436100", \ - "0.0074915000, 0.0061271000, 0.0021895000, -0.009365700, -0.042922200, -0.138897700, -0.411512800", \ - "0.0070393000, 0.0056471000, 0.0016480000, -0.009877800, -0.043241600, -0.139031000, -0.411535100", \ - "0.0069451000, 0.0055058000, 0.0014387000, -0.010220400, -0.043626400, -0.139264500, -0.411671000", \ - "0.0073783000, 0.0059263000, 0.0016369000, -0.010308900, -0.044091800, -0.139711200, -0.411856300", \ - "0.0097141000, 0.0080858000, 0.0034385000, -0.009043600, -0.043300500, -0.139658500, -0.412083200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0135868000, 0.0151238000, 0.0194369000, 0.0314452000, 0.0650552000, 0.1601493000, 0.4289869000", \ - "0.0130175000, 0.0145906000, 0.0189874000, 0.0311266000, 0.0649298000, 0.1599856000, 0.4290183000", \ - "0.0124727000, 0.0140665000, 0.0185262000, 0.0307860000, 0.0644467000, 0.1598658000, 0.4289702000", \ - "0.0120350000, 0.0136727000, 0.0179815000, 0.0300533000, 0.0641865000, 0.1593618000, 0.4288347000", \ - "0.0119933000, 0.0134635000, 0.0176998000, 0.0296625000, 0.0634898000, 0.1587231000, 0.4278881000", \ - "0.0126703000, 0.0140953000, 0.0182212000, 0.0306393000, 0.0643287000, 0.1589621000, 0.4278751000", \ - "0.0158887000, 0.0171080000, 0.0208176000, 0.0321802000, 0.0650250000, 0.1595125000, 0.4274275000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0081929000, 0.0068003000, 0.0027026000, -0.009123400, -0.042949300, -0.139065100, -0.411720700", \ - "0.0077607000, 0.0063951000, 0.0023973000, -0.009294400, -0.043021100, -0.139113600, -0.411767200", \ - "0.0072580000, 0.0058905000, 0.0019253000, -0.009639900, -0.043201200, -0.139183200, -0.411785100", \ - "0.0068448000, 0.0054474000, 0.0014226000, -0.010139400, -0.043538800, -0.139340500, -0.411850800", \ - "0.0069390000, 0.0054142000, 0.0011699000, -0.010489600, -0.043900800, -0.139549600, -0.411941800", \ - "0.0070778000, 0.0055989000, 0.0013837000, -0.010469900, -0.044311000, -0.139986900, -0.412167700", \ - "0.0093248000, 0.0077050000, 0.0031671000, -0.009260000, -0.043505100, -0.139895900, -0.412302700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014178910, 0.0040208270, 0.0114021900, 0.0323341000, 0.0916924300, 0.2600197000"); - values("0.0189976000, 0.0204890000, 0.0247374000, 0.0367757000, 0.0704795000, 0.1655898000, 0.4346895000", \ - "0.0186619000, 0.0201895000, 0.0244506000, 0.0365640000, 0.0704406000, 0.1655576000, 0.4345745000", \ - "0.0182357000, 0.0197703000, 0.0241060000, 0.0362645000, 0.0702160000, 0.1653722000, 0.4343081000", \ - "0.0179846000, 0.0195119000, 0.0238096000, 0.0359752000, 0.0696060000, 0.1649808000, 0.4343532000", \ - "0.0183932000, 0.0199064000, 0.0241151000, 0.0360780000, 0.0697985000, 0.1648816000, 0.4337778000", \ - "0.0195374000, 0.0209600000, 0.0251492000, 0.0370917000, 0.0705148000, 0.1651108000, 0.4337895000", \ - "0.0232760000, 0.0246558000, 0.0285378000, 0.0396482000, 0.0727913000, 0.1671411000, 0.4343570000"); - } - } - max_capacitance : 0.2600200000; - max_transition : 1.4982790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0281846000, 0.0321108000, 0.0432435000, 0.0734159000, 0.1576495000, 0.3974761000, 1.0802266000", \ - "0.0312080000, 0.0352777000, 0.0464389000, 0.0769226000, 0.1614840000, 0.4001530000, 1.0786011000", \ - "0.0402546000, 0.0442177000, 0.0551726000, 0.0857299000, 0.1707746000, 0.4098741000, 1.0859074000", \ - "0.0530225000, 0.0592642000, 0.0746801000, 0.1073304000, 0.1931987000, 0.4313850000, 1.1083545000", \ - "0.0655059000, 0.0750306000, 0.0980919000, 0.1479191000, 0.2450859000, 0.4856840000, 1.1593683000", \ - "0.0691311000, 0.0833706000, 0.1181531000, 0.1935344000, 0.3384907000, 0.6058807000, 1.2850970000", \ - "0.0437660000, 0.0655553000, 0.1161278000, 0.2274716000, 0.4463900000, 0.8399806000, 1.5629819000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0264594000, 0.0300331000, 0.0396513000, 0.0655686000, 0.1372150000, 0.3384666000, 0.9081564000", \ - "0.0315925000, 0.0351807000, 0.0448656000, 0.0708944000, 0.1427610000, 0.3443894000, 0.9236852000", \ - "0.0449870000, 0.0484661000, 0.0579500000, 0.0841154000, 0.1564192000, 0.3589409000, 0.9282719000", \ - "0.0682376000, 0.0736508000, 0.0873388000, 0.1153280000, 0.1875208000, 0.3886096000, 0.9624539000", \ - "0.1041436000, 0.1136596000, 0.1352927000, 0.1797167000, 0.2611926000, 0.4599049000, 1.0316243000", \ - "0.1623226000, 0.1766919000, 0.2115730000, 0.2843784000, 0.4132447000, 0.6346002000, 1.2034626000", \ - "0.2643360000, 0.2853405000, 0.3366795000, 0.4482199000, 0.6560504000, 1.0050545000, 1.6014239000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0265294000, 0.0316461000, 0.0462452000, 0.0868510000, 0.2013820000, 0.5281851000, 1.4531225000", \ - "0.0260318000, 0.0313075000, 0.0460623000, 0.0867767000, 0.2018350000, 0.5270823000, 1.4547641000", \ - "0.0289008000, 0.0332020000, 0.0465869000, 0.0866764000, 0.2012627000, 0.5263236000, 1.4495528000", \ - "0.0395444000, 0.0448643000, 0.0587612000, 0.0920967000, 0.2021292000, 0.5265803000, 1.4474633000", \ - "0.0614485000, 0.0682320000, 0.0851380000, 0.1236951000, 0.2169391000, 0.5289712000, 1.4491003000", \ - "0.1004660000, 0.1106208000, 0.1355775000, 0.1876031000, 0.2935295000, 0.5556714000, 1.4553968000", \ - "0.1690733000, 0.1826653000, 0.2194117000, 0.2969258000, 0.4444384000, 0.7337019000, 1.4982791000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0201902000, 0.0246378000, 0.0372427000, 0.0732269000, 0.1753958000, 0.4668183000, 1.2782282000", \ - "0.0201139000, 0.0246623000, 0.0372665000, 0.0729225000, 0.1744478000, 0.4638935000, 1.2856849000", \ - "0.0235536000, 0.0269753000, 0.0378934000, 0.0731659000, 0.1752412000, 0.4639713000, 1.2776145000", \ - "0.0388492000, 0.0423929000, 0.0506356000, 0.0777185000, 0.1750137000, 0.4664236000, 1.2846999000", \ - "0.0642500000, 0.0704218000, 0.0834914000, 0.1124891000, 0.1864262000, 0.4648895000, 1.2859892000", \ - "0.1059081000, 0.1158928000, 0.1382211000, 0.1835737000, 0.2638663000, 0.4845285000, 1.2837417000", \ - "0.1773206000, 0.1910742000, 0.2272898000, 0.3016048000, 0.4332465000, 0.6564346000, 1.3155547000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0401754000, 0.0440285000, 0.0550419000, 0.0849718000, 0.1692608000, 0.4075651000, 1.0871116000", \ - "0.0437131000, 0.0476553000, 0.0587577000, 0.0891196000, 0.1735763000, 0.4119423000, 1.0904784000", \ - "0.0519038000, 0.0559865000, 0.0672990000, 0.0981367000, 0.1828707000, 0.4215982000, 1.0970578000", \ - "0.0659764000, 0.0713207000, 0.0851055000, 0.1181312000, 0.2043639000, 0.4429258000, 1.1188316000", \ - "0.0827623000, 0.0909048000, 0.1115677000, 0.1559957000, 0.2517257000, 0.4924137000, 1.1694972000", \ - "0.0911093000, 0.1055179000, 0.1360828000, 0.2050361000, 0.3383216000, 0.6048345000, 1.2840815000", \ - "0.0691769000, 0.0899577000, 0.1388356000, 0.2459383000, 0.4505144000, 0.8234879000, 1.5442042000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0382361000, 0.0417605000, 0.0514296000, 0.0777776000, 0.1512164000, 0.3575475000, 0.9417249000", \ - "0.0430405000, 0.0466747000, 0.0564134000, 0.0830996000, 0.1566767000, 0.3633019000, 0.9472214000", \ - "0.0560225000, 0.0595538000, 0.0693810000, 0.0961148000, 0.1695373000, 0.3763650000, 0.9605446000", \ - "0.0852850000, 0.0897666000, 0.1007005000, 0.1273007000, 0.2013006000, 0.4059257000, 0.9905804000", \ - "0.1325205000, 0.1396136000, 0.1573067000, 0.1964494000, 0.2747224000, 0.4810660000, 1.0613865000", \ - "0.2089718000, 0.2200885000, 0.2479014000, 0.3108984000, 0.4312614000, 0.6526404000, 1.2332562000", \ - "0.3347696000, 0.3511183000, 0.3934249000, 0.4921748000, 0.6870134000, 1.0239551000, 1.6319573000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0268742000, 0.0318426000, 0.0462466000, 0.0867692000, 0.2012746000, 0.5266475000, 1.4537894000", \ - "0.0267743000, 0.0318261000, 0.0461569000, 0.0873186000, 0.2013849000, 0.5266692000, 1.4520102000", \ - "0.0279672000, 0.0326515000, 0.0464546000, 0.0868701000, 0.2014870000, 0.5264025000, 1.4482009000", \ - "0.0370550000, 0.0416978000, 0.0540521000, 0.0899192000, 0.2017861000, 0.5273828000, 1.4488487000", \ - "0.0571716000, 0.0626326000, 0.0773383000, 0.1130770000, 0.2112163000, 0.5259280000, 1.4482409000", \ - "0.0965290000, 0.1047716000, 0.1231007000, 0.1671180000, 0.2677060000, 0.5488666000, 1.4501840000", \ - "0.1696997000, 0.1797543000, 0.2060586000, 0.2684644000, 0.3987442000, 0.6833719000, 1.4788012000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0297232000, 0.0342374000, 0.0470944000, 0.0835505000, 0.1872250000, 0.4812626000, 1.3135555000", \ - "0.0297021000, 0.0342120000, 0.0471567000, 0.0836135000, 0.1875049000, 0.4813964000, 1.3149601000", \ - "0.0301203000, 0.0344368000, 0.0470196000, 0.0837741000, 0.1875724000, 0.4811680000, 1.3167720000", \ - "0.0425635000, 0.0462001000, 0.0551236000, 0.0863364000, 0.1878931000, 0.4819825000, 1.3141158000", \ - "0.0698307000, 0.0751510000, 0.0876943000, 0.1154278000, 0.1972885000, 0.4826521000, 1.3164513000", \ - "0.1151662000, 0.1238882000, 0.1448582000, 0.1883676000, 0.2708877000, 0.5023280000, 1.3166637000", \ - "0.1883775000, 0.2016657000, 0.2376721000, 0.3084310000, 0.4386028000, 0.6627714000, 1.3482091000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0436772000, 0.0477376000, 0.0584451000, 0.0889810000, 0.1728156000, 0.4111875000, 1.0871355000", \ - "0.0471658000, 0.0511565000, 0.0622572000, 0.0929520000, 0.1789402000, 0.4178356000, 1.0913930000", \ - "0.0542682000, 0.0583311000, 0.0695862000, 0.1001899000, 0.1850854000, 0.4254184000, 1.0992337000", \ - "0.0668227000, 0.0714014000, 0.0837618000, 0.1156630000, 0.2008910000, 0.4403620000, 1.1162437000", \ - "0.0837284000, 0.0899513000, 0.1058622000, 0.1441255000, 0.2358148000, 0.4755192000, 1.1526466000", \ - "0.0956644000, 0.1057504000, 0.1308672000, 0.1862979000, 0.3012991000, 0.5570527000, 1.2355663000", \ - "0.0790348000, 0.0958696000, 0.1366355000, 0.2244664000, 0.3924287000, 0.7131945000, 1.4229671000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0401411000, 0.0435032000, 0.0526611000, 0.0775780000, 0.1459592000, 0.3362477000, 0.8739639000", \ - "0.0453831000, 0.0487699000, 0.0579138000, 0.0829443000, 0.1511002000, 0.3415402000, 0.8796502000", \ - "0.0584980000, 0.0619453000, 0.0712530000, 0.0962379000, 0.1645521000, 0.3541913000, 0.8912537000", \ - "0.0889860000, 0.0929514000, 0.1028123000, 0.1275646000, 0.1952958000, 0.3861419000, 0.9229752000", \ - "0.1392675000, 0.1452821000, 0.1604983000, 0.1963302000, 0.2687972000, 0.4583532000, 0.9949741000", \ - "0.2187489000, 0.2282156000, 0.2522766000, 0.3080721000, 0.4202348000, 0.6277717000, 1.1610669000", \ - "0.3445075000, 0.3566849000, 0.3939402000, 0.4827758000, 0.6623980000, 0.9833817000, 1.5527669000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0267828000, 0.0319079000, 0.0464673000, 0.0869733000, 0.2012683000, 0.5271402000, 1.4465060000", \ - "0.0268047000, 0.0318630000, 0.0462147000, 0.0870777000, 0.2034285000, 0.5280181000, 1.4499421000", \ - "0.0272915000, 0.0321804000, 0.0463737000, 0.0866917000, 0.2016353000, 0.5282862000, 1.4549321000", \ - "0.0327316000, 0.0373533000, 0.0507077000, 0.0887008000, 0.2025185000, 0.5278807000, 1.4470888000", \ - "0.0470963000, 0.0520389000, 0.0653352000, 0.1027978000, 0.2078855000, 0.5264401000, 1.4484356000", \ - "0.0804860000, 0.0865744000, 0.1022917000, 0.1412585000, 0.2469920000, 0.5406053000, 1.4496097000", \ - "0.1507825000, 0.1581079000, 0.1780733000, 0.2264234000, 0.3397053000, 0.6306199000, 1.4722763000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014178900, 0.0040208300, 0.0114022000, 0.0323341000, 0.0916924000, 0.2600200000"); - values("0.0350920000, 0.0394028000, 0.0513173000, 0.0852313000, 0.1815069000, 0.4543474000, 1.2303593000", \ - "0.0349726000, 0.0393290000, 0.0512812000, 0.0851687000, 0.1817322000, 0.4542755000, 1.2288836000", \ - "0.0348419000, 0.0389510000, 0.0509923000, 0.0850928000, 0.1816366000, 0.4544638000, 1.2301550000", \ - "0.0453679000, 0.0484619000, 0.0580242000, 0.0876028000, 0.1815820000, 0.4554539000, 1.2302093000", \ - "0.0726106000, 0.0774866000, 0.0891939000, 0.1166704000, 0.1926398000, 0.4547524000, 1.2329167000", \ - "0.1193813000, 0.1272162000, 0.1463704000, 0.1883283000, 0.2669084000, 0.4807677000, 1.2305001000", \ - "0.1930905000, 0.2063468000, 0.2374174000, 0.3066956000, 0.4324639000, 0.6479056000, 1.2723501000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3_4") { - leakage_power () { - value : 0.0001713000; - when : "!A&!B&C"; - } - leakage_power () { - value : 9.9474228e-05; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0015251000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0001757000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0014820000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0001986000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0155295000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0014760000; - when : "A&B&!C"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__nand3"; - cell_leakage_power : 0.0025822140; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0084820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0186038000, 0.0186415000, 0.0187282000, 0.0187153000, 0.0186854000, 0.0186164000, 0.0184575000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013647500, -0.013592800, -0.013466800, -0.013441300, -0.013382400, -0.013246700, -0.012933900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088430000; - } - pin ("B") { - capacitance : 0.0085870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171354000, 0.0171216000, 0.0170895000, 0.0171503000, 0.0172903000, 0.0176130000, 0.0183568000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015922200, -0.015897700, -0.015841300, -0.015836700, -0.015826200, -0.015802000, -0.015746300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088890000; - } - pin ("C") { - capacitance : 0.0087760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157436000, 0.0157321000, 0.0157057000, 0.0157098000, 0.0157192000, 0.0157409000, 0.0157910000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015691500, -0.015690900, -0.015689700, -0.015690600, -0.015692700, -0.015697700, -0.015709000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092250000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0148238000, 0.0132860000, 0.0082393000, -0.008183700, -0.060750800, -0.226094800, -0.743746200", \ - "0.0138061000, 0.0122942000, 0.0073528000, -0.008774400, -0.061012000, -0.226236100, -0.743880400", \ - "0.0125288000, 0.0109903000, 0.0060999000, -0.009828900, -0.061658300, -0.226563600, -0.744066700", \ - "0.0119390000, 0.0102876000, 0.0050808000, -0.010900500, -0.062536400, -0.226944100, -0.744244600", \ - "0.0118880000, 0.0101811000, 0.0048744000, -0.011581300, -0.063419000, -0.227617300, -0.744549000", \ - "0.0141030000, 0.0123688000, 0.0068597000, -0.010015400, -0.062998100, -0.228236400, -0.745082400", \ - "0.0212559000, 0.0196006000, 0.0135686000, -0.005512500, -0.060148100, -0.226065800, -0.744652200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0123830000, 0.0144335000, 0.0204769000, 0.0380743000, 0.0910411000, 0.2553705000, 0.7636961000", \ - "0.0114321000, 0.0134404000, 0.0195086000, 0.0374665000, 0.0908859000, 0.2550968000, 0.7633567000", \ - "0.0105647000, 0.0124402000, 0.0183613000, 0.0362378000, 0.0896426000, 0.2563069000, 0.7686824000", \ - "0.0101080000, 0.0119612000, 0.0175856000, 0.0350887000, 0.0887259000, 0.2552921000, 0.7722336000", \ - "0.0111988000, 0.0128972000, 0.0180674000, 0.0346287000, 0.0869915000, 0.2538234000, 0.7661253000", \ - "0.0124349000, 0.0140626000, 0.0192018000, 0.0365230000, 0.0890295000, 0.2517047000, 0.7659576000", \ - "0.0205954000, 0.0213936000, 0.0260153000, 0.0412429000, 0.0911729000, 0.2562551000, 0.7657882000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0177715000, 0.0161247000, 0.0108678000, -0.005797000, -0.058521300, -0.223936400, -0.741606900", \ - "0.0169147000, 0.0153343000, 0.0102336000, -0.006199000, -0.058716800, -0.223995800, -0.741633900", \ - "0.0157981000, 0.0142461000, 0.0092353000, -0.006948100, -0.059119600, -0.224190200, -0.741785400", \ - "0.0148902000, 0.0132826000, 0.0082118000, -0.007933100, -0.059765500, -0.224464700, -0.741899100", \ - "0.0146943000, 0.0130180000, 0.0077961000, -0.008573000, -0.060486000, -0.224947500, -0.742052700", \ - "0.0154620000, 0.0137562000, 0.0082897000, -0.008485400, -0.061302400, -0.225651500, -0.742607700", \ - "0.0196160000, 0.0176976000, 0.0117613000, -0.005998100, -0.059636600, -0.225641500, -0.742782400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0261560000, 0.0279487000, 0.0334644000, 0.0504479000, 0.1029416000, 0.2663360000, 0.7774018000", \ - "0.0252622000, 0.0270793000, 0.0326903000, 0.0499507000, 0.1027871000, 0.2662114000, 0.7770667000", \ - "0.0241001000, 0.0259593000, 0.0317359000, 0.0491697000, 0.1022096000, 0.2662915000, 0.7774053000", \ - "0.0233544000, 0.0252897000, 0.0308375000, 0.0480021000, 0.1011163000, 0.2652256000, 0.7762032000", \ - "0.0232486000, 0.0249626000, 0.0303128000, 0.0471554000, 0.0998599000, 0.2642862000, 0.7756777000", \ - "0.0249198000, 0.0264727000, 0.0320165000, 0.0485873000, 0.1013283000, 0.2645859000, 0.7747176000", \ - "0.0297222000, 0.0311918000, 0.0361543000, 0.0519407000, 0.1030897000, 0.2652951000, 0.7737678000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0172616000, 0.0156488000, 0.0103614000, -0.006312100, -0.059099300, -0.224514100, -0.742150900", \ - "0.0164811000, 0.0148750000, 0.0097771000, -0.006712200, -0.059248200, -0.224574200, -0.742268800", \ - "0.0155140000, 0.0139388000, 0.0089018000, -0.007351100, -0.059571400, -0.224705500, -0.742320500", \ - "0.0146571000, 0.0130339000, 0.0079425000, -0.008291900, -0.060179900, -0.224957000, -0.742394500", \ - "0.0146066000, 0.0127506000, 0.0074676000, -0.008939300, -0.060870000, -0.225245300, -0.742517000", \ - "0.0147590000, 0.0131024000, 0.0077270000, -0.008992100, -0.061685800, -0.226126000, -0.743031600", \ - "0.0179792000, 0.0160696000, 0.0103607000, -0.007113100, -0.060446700, -0.226088900, -0.743204600"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0385330000, 0.0402708000, 0.0457332000, 0.0627508000, 0.1156065000, 0.2791567000, 0.7904297000", \ - "0.0377395000, 0.0395026000, 0.0449968000, 0.0621528000, 0.1151536000, 0.2789635000, 0.7896619000", \ - "0.0368356000, 0.0386319000, 0.0441755000, 0.0614560000, 0.1146391000, 0.2788045000, 0.7897168000", \ - "0.0360106000, 0.0377415000, 0.0433576000, 0.0606083000, 0.1139195000, 0.2778599000, 0.7891288000", \ - "0.0358799000, 0.0376210000, 0.0431625000, 0.0599462000, 0.1132483000, 0.2771696000, 0.7896121000", \ - "0.0397742000, 0.0415249000, 0.0468238000, 0.0612678000, 0.1136505000, 0.2773930000, 0.7889463000", \ - "0.0441251000, 0.0454404000, 0.0504740000, 0.0665281000, 0.1181064000, 0.2806854000, 0.7891014000"); - } - } - max_capacitance : 0.4696750000; - max_transition : 1.5000220000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0302676000, 0.0329060000, 0.0406888000, 0.0645687000, 0.1361186000, 0.3590482000, 1.0648394000", \ - "0.0331539000, 0.0358655000, 0.0438181000, 0.0677186000, 0.1406878000, 0.3630337000, 1.0602202000", \ - "0.0421428000, 0.0447874000, 0.0524350000, 0.0765361000, 0.1491480000, 0.3731184000, 1.0701783000", \ - "0.0555814000, 0.0595294000, 0.0703919000, 0.0987270000, 0.1712134000, 0.3956915000, 1.0931490000", \ - "0.0685256000, 0.0747302000, 0.0915916000, 0.1342628000, 0.2242455000, 0.4477924000, 1.1509889000", \ - "0.0735063000, 0.0824164000, 0.1078502000, 0.1712698000, 0.3066237000, 0.5700685000, 1.2707281000", \ - "0.0506534000, 0.0640933000, 0.1009098000, 0.1936399000, 0.3981120000, 0.7923255000, 1.5549986000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0277117000, 0.0300593000, 0.0371650000, 0.0576961000, 0.1188868000, 0.3099523000, 0.9046163000", \ - "0.0327574000, 0.0350679000, 0.0420725000, 0.0628037000, 0.1248805000, 0.3176835000, 0.9079208000", \ - "0.0459637000, 0.0481965000, 0.0550020000, 0.0757706000, 0.1377625000, 0.3288765000, 0.9247297000", \ - "0.0692441000, 0.0728561000, 0.0828008000, 0.1065208000, 0.1685722000, 0.3593920000, 0.9526359000", \ - "0.1052746000, 0.1112052000, 0.1270643000, 0.1652565000, 0.2414686000, 0.4322622000, 1.0224208000", \ - "0.1632590000, 0.1725183000, 0.1978565000, 0.2580154000, 0.3798337000, 0.6000623000, 1.1929892000", \ - "0.2647666000, 0.2775693000, 0.3151261000, 0.4065552000, 0.5990414000, 0.9541149000, 1.5856080000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0285984000, 0.0319071000, 0.0420519000, 0.0740418000, 0.1729742000, 0.4821433000, 1.4601245000", \ - "0.0282909000, 0.0316011000, 0.0418894000, 0.0736938000, 0.1729777000, 0.4813023000, 1.4474754000", \ - "0.0305539000, 0.0333223000, 0.0424051000, 0.0733760000, 0.1727166000, 0.4813105000, 1.4491495000", \ - "0.0417622000, 0.0456030000, 0.0555326000, 0.0808436000, 0.1729255000, 0.4829409000, 1.4512634000", \ - "0.0635358000, 0.0678036000, 0.0803162000, 0.1129683000, 0.1935836000, 0.4844428000, 1.4500522000", \ - "0.1023974000, 0.1095058000, 0.1265735000, 0.1717025000, 0.2714832000, 0.5192799000, 1.4531373000", \ - "0.1703103000, 0.1806344000, 0.2053011000, 0.2720454000, 0.4114367000, 0.7010760000, 1.5000218000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0213387000, 0.0241156000, 0.0329913000, 0.0606726000, 0.1476590000, 0.4216956000, 1.2751485000", \ - "0.0212796000, 0.0241537000, 0.0329463000, 0.0605811000, 0.1478673000, 0.4221709000, 1.2675441000", \ - "0.0242274000, 0.0263747000, 0.0338502000, 0.0606846000, 0.1475153000, 0.4226350000, 1.2765687000", \ - "0.0394323000, 0.0414751000, 0.0480517000, 0.0675341000, 0.1478872000, 0.4210181000, 1.2754989000", \ - "0.0650113000, 0.0687163000, 0.0788491000, 0.1029325000, 0.1648665000, 0.4203217000, 1.2739746000", \ - "0.1072404000, 0.1129065000, 0.1293168000, 0.1693689000, 0.2466275000, 0.4499186000, 1.2714556000", \ - "0.1777549000, 0.1893831000, 0.2125928000, 0.2748110000, 0.4005875000, 0.6352814000, 1.3081766000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0406368000, 0.0431720000, 0.0506949000, 0.0741405000, 0.1454709000, 0.3709738000, 1.0666669000", \ - "0.0439725000, 0.0465655000, 0.0543576000, 0.0779216000, 0.1496468000, 0.3745434000, 1.0723233000", \ - "0.0511655000, 0.0538625000, 0.0618621000, 0.0859823000, 0.1579888000, 0.3812181000, 1.0785375000", \ - "0.0632241000, 0.0665652000, 0.0763222000, 0.1031718000, 0.1763061000, 0.4002172000, 1.0983492000", \ - "0.0774984000, 0.0825068000, 0.0967978000, 0.1330572000, 0.2182724000, 0.4449335000, 1.1430519000", \ - "0.0807745000, 0.0898954000, 0.1112197000, 0.1669533000, 0.2868765000, 0.5446084000, 1.2481962000", \ - "0.0468086000, 0.0601038000, 0.0938935000, 0.1805796000, 0.3657763000, 0.7207090000, 1.4780133000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0422749000, 0.0446074000, 0.0518243000, 0.0739549000, 0.1410707000, 0.3489302000, 0.9978199000", \ - "0.0472646000, 0.0496986000, 0.0569113000, 0.0792699000, 0.1466850000, 0.3546542000, 1.0039474000", \ - "0.0599214000, 0.0623179000, 0.0698152000, 0.0922496000, 0.1600875000, 0.3680974000, 1.0183124000", \ - "0.0904054000, 0.0931291000, 0.1013718000, 0.1236222000, 0.1915141000, 0.3998429000, 1.0505085000", \ - "0.1409214000, 0.1454535000, 0.1583781000, 0.1916118000, 0.2653373000, 0.4735076000, 1.1226788000", \ - "0.2242766000, 0.2312963000, 0.2514369000, 0.3046199000, 0.4190462000, 0.6453268000, 1.2916576000", \ - "0.3651656000, 0.3753554000, 0.4060830000, 0.4875207000, 0.6706186000, 1.0182574000, 1.6909090000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0288416000, 0.0320583000, 0.0420794000, 0.0737625000, 0.1727410000, 0.4838017000, 1.4491321000", \ - "0.0288789000, 0.0320855000, 0.0421504000, 0.0737191000, 0.1725986000, 0.4828791000, 1.4525401000", \ - "0.0302127000, 0.0331529000, 0.0426858000, 0.0739383000, 0.1727034000, 0.4815253000, 1.4484696000", \ - "0.0383599000, 0.0413884000, 0.0507352000, 0.0782470000, 0.1731502000, 0.4817615000, 1.4483872000", \ - "0.0574879000, 0.0608620000, 0.0710450000, 0.1002170000, 0.1856801000, 0.4835302000, 1.4514718000", \ - "0.0961440000, 0.1007437000, 0.1135630000, 0.1495910000, 0.2395392000, 0.5065027000, 1.4539727000", \ - "0.1683338000, 0.1748161000, 0.1930253000, 0.2419098000, 0.3571268000, 0.6298424000, 1.4838255000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0332386000, 0.0364586000, 0.0461934000, 0.0767189000, 0.1723928000, 0.4718840000, 1.4075198000", \ - "0.0332320000, 0.0363533000, 0.0461717000, 0.0766876000, 0.1724896000, 0.4714933000, 1.4072856000", \ - "0.0333722000, 0.0363228000, 0.0460782000, 0.0767273000, 0.1724071000, 0.4716995000, 1.4144720000", \ - "0.0443688000, 0.0468638000, 0.0539828000, 0.0797556000, 0.1725886000, 0.4716662000, 1.4135408000", \ - "0.0723089000, 0.0756689000, 0.0849731000, 0.1099021000, 0.1839327000, 0.4723677000, 1.4092869000", \ - "0.1184961000, 0.1240928000, 0.1395747000, 0.1766017000, 0.2582480000, 0.4934469000, 1.4093442000", \ - "0.1930836000, 0.2023822000, 0.2282166000, 0.2899719000, 0.4150365000, 0.6521169000, 1.4317170000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0456467000, 0.0482875000, 0.0557768000, 0.0793095000, 0.1504686000, 0.3768995000, 1.0715164000", \ - "0.0491742000, 0.0517222000, 0.0595632000, 0.0830003000, 0.1550859000, 0.3779358000, 1.0754178000", \ - "0.0561914000, 0.0587681000, 0.0668162000, 0.0904905000, 0.1640248000, 0.3863628000, 1.0832191000", \ - "0.0676077000, 0.0705731000, 0.0792880000, 0.1046303000, 0.1772709000, 0.4019325000, 1.0986809000", \ - "0.0816723000, 0.0858016000, 0.0969860000, 0.1278579000, 0.2079219000, 0.4336209000, 1.1320377000", \ - "0.0861761000, 0.0930543000, 0.1105985000, 0.1562593000, 0.2606250000, 0.5056250000, 1.2075890000", \ - "0.0490743000, 0.0594548000, 0.0894226000, 0.1629416000, 0.3195011000, 0.6354369000, 1.3741289000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0485061000, 0.0509094000, 0.0582133000, 0.0801880000, 0.1462676000, 0.3476912000, 0.9748141000", \ - "0.0535530000, 0.0560682000, 0.0634748000, 0.0855859000, 0.1514781000, 0.3530546000, 0.9801169000", \ - "0.0664559000, 0.0689102000, 0.0762979000, 0.0986043000, 0.1647680000, 0.3664512000, 0.9931819000", \ - "0.0983284000, 0.1007228000, 0.1087613000, 0.1305863000, 0.1967528000, 0.3985919000, 1.0261660000", \ - "0.1575121000, 0.1613745000, 0.1724018000, 0.2017820000, 0.2712915000, 0.4733411000, 1.0998743000", \ - "0.2533974000, 0.2592144000, 0.2765941000, 0.3219479000, 0.4292643000, 0.6438756000, 1.2687630000", \ - "0.4125420000, 0.4211259000, 0.4478486000, 0.5200061000, 0.6877767000, 1.0171779000, 1.6710165000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0287981000, 0.0321048000, 0.0420776000, 0.0739446000, 0.1734321000, 0.4838959000, 1.4490191000", \ - "0.0288680000, 0.0320621000, 0.0421544000, 0.0737938000, 0.1727225000, 0.4818771000, 1.4481408000", \ - "0.0293318000, 0.0324409000, 0.0423117000, 0.0737508000, 0.1735110000, 0.4816545000, 1.4492808000", \ - "0.0345681000, 0.0375915000, 0.0471108000, 0.0762035000, 0.1729069000, 0.4822058000, 1.4488956000", \ - "0.0486582000, 0.0515914000, 0.0609690000, 0.0905885000, 0.1808126000, 0.4817513000, 1.4471573000", \ - "0.0825321000, 0.0862074000, 0.0971497000, 0.1286256000, 0.2207680000, 0.4984441000, 1.4581208000", \ - "0.1533309000, 0.1577750000, 0.1721941000, 0.2121399000, 0.3121181000, 0.5905266000, 1.4756406000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0426683000, 0.0458258000, 0.0552861000, 0.0849477000, 0.1786247000, 0.4712017000, 1.3888447000", \ - "0.0425819000, 0.0456585000, 0.0552628000, 0.0850394000, 0.1786357000, 0.4719144000, 1.3900809000", \ - "0.0418626000, 0.0450100000, 0.0548506000, 0.0849683000, 0.1783886000, 0.4715334000, 1.3899726000", \ - "0.0491979000, 0.0520409000, 0.0597491000, 0.0864532000, 0.1784078000, 0.4715643000, 1.3899165000", \ - "0.0767094000, 0.0799735000, 0.0894328000, 0.1127320000, 0.1877672000, 0.4717598000, 1.3938735000", \ - "0.1253093000, 0.1300486000, 0.1444019000, 0.1797871000, 0.2590445000, 0.4929216000, 1.3900300000", \ - "0.2031041000, 0.2120537000, 0.2351861000, 0.2920672000, 0.4152522000, 0.6466940000, 1.4127383000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3b_1") { - leakage_power () { - value : 0.0007172000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0004175000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0057612000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0006812000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0008339000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0008166000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0011269000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0008316000; - when : "A_N&B&!C"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__nand3b"; - cell_leakage_power : 0.0013982570; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0013770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0070248000, 0.0069369000, 0.0067344000, 0.0067798000, 0.0068845000, 0.0071259000, 0.0076822000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045334000, 0.0044735000, 0.0043354000, 0.0043743000, 0.0044640000, 0.0046709000, 0.0051476000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014270000; - } - pin ("B") { - capacitance : 0.0023250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045660000, 0.0045652000, 0.0045635000, 0.0045678000, 0.0045776000, 0.0046003000, 0.0046526000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004248600, -0.004247400, -0.004244700, -0.004238400, -0.004223800, -0.004190200, -0.004112700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024070000; - } - pin ("C") { - capacitance : 0.0023300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022230000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040017000, 0.0040013000, 0.0040003000, 0.0039979000, 0.0039921000, 0.0039790000, 0.0039486000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003997900, -0.003994600, -0.003987100, -0.003986600, -0.003985600, -0.003983300, -0.003977900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024380000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0061081000, 0.0050057000, 0.0019619000, -0.006145100, -0.027507100, -0.082803700, -0.224955500", \ - "0.0060537000, 0.0049067000, 0.0018844000, -0.006195500, -0.027559200, -0.082856500, -0.225056100", \ - "0.0061141000, 0.0049777000, 0.0019043000, -0.006187600, -0.027532800, -0.082790300, -0.224948000", \ - "0.0059102000, 0.0047547000, 0.0017011000, -0.006431100, -0.027742200, -0.082969100, -0.225138200", \ - "0.0057900000, 0.0046142000, 0.0015512000, -0.006708000, -0.027964100, -0.083151900, -0.225269200", \ - "0.0054780000, 0.0042053000, 0.0011569000, -0.006571500, -0.027894900, -0.082990400, -0.225066600", \ - "0.0060395000, 0.0047509000, 0.0015528000, -0.006950400, -0.028243500, -0.083251500, -0.225256600"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0041031000, 0.0054929000, 0.0089166000, 0.0173909000, 0.0388133000, 0.0938726000, 0.2343645000", \ - "0.0040970000, 0.0054892000, 0.0089205000, 0.0173903000, 0.0390102000, 0.0940347000, 0.2337952000", \ - "0.0040563000, 0.0054360000, 0.0088713000, 0.0173796000, 0.0388741000, 0.0942499000, 0.2344780000", \ - "0.0037645000, 0.0050812000, 0.0084906000, 0.0170309000, 0.0386857000, 0.0939296000, 0.2342792000", \ - "0.0035886000, 0.0048808000, 0.0081787000, 0.0167006000, 0.0384333000, 0.0938121000, 0.2351271000", \ - "0.0035363000, 0.0048665000, 0.0082213000, 0.0165428000, 0.0382316000, 0.0932517000, 0.2349909000", \ - "0.0038997000, 0.0051846000, 0.0084440000, 0.0167991000, 0.0383545000, 0.0934413000, 0.2322033000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0070621000, 0.0058428000, 0.0026745000, -0.005623000, -0.027135000, -0.082485400, -0.224706000", \ - "0.0068628000, 0.0056903000, 0.0025663000, -0.005676400, -0.027162000, -0.082489400, -0.224705700", \ - "0.0066096000, 0.0054598000, 0.0023706000, -0.005816700, -0.027226200, -0.082521700, -0.224711600", \ - "0.0063877000, 0.0052238000, 0.0021199000, -0.006024200, -0.027367700, -0.082595600, -0.224750100", \ - "0.0063467000, 0.0051009000, 0.0019204000, -0.006273600, -0.027568700, -0.082702000, -0.224814400", \ - "0.0066239000, 0.0053474000, 0.0020867000, -0.006341800, -0.027788800, -0.082882800, -0.224908200", \ - "0.0076518000, 0.0062700000, 0.0027881000, -0.005804000, -0.027496700, -0.082967800, -0.225054600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0053550000, 0.0066319000, 0.0098964000, 0.0182429000, 0.0394902000, 0.0940064000, 0.2343329000", \ - "0.0051062000, 0.0064044000, 0.0096750000, 0.0180564000, 0.0394513000, 0.0940751000, 0.2343335000", \ - "0.0048598000, 0.0061702000, 0.0095215000, 0.0179096000, 0.0393423000, 0.0939540000, 0.2342078000", \ - "0.0046473000, 0.0059228000, 0.0092016000, 0.0176247000, 0.0388541000, 0.0938573000, 0.2342698000", \ - "0.0046497000, 0.0059162000, 0.0091467000, 0.0174601000, 0.0385795000, 0.0932053000, 0.2334029000", \ - "0.0050341000, 0.0062968000, 0.0097212000, 0.0179757000, 0.0391496000, 0.0937238000, 0.2330707000", \ - "0.0065836000, 0.0077027000, 0.0106760000, 0.0186609000, 0.0397060000, 0.0936027000, 0.2336747000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0070432000, 0.0058409000, 0.0026739000, -0.005635700, -0.027137100, -0.082484400, -0.224705500", \ - "0.0068644000, 0.0057027000, 0.0025661000, -0.005689100, -0.027168600, -0.082496500, -0.224706800", \ - "0.0066162000, 0.0054616000, 0.0023633000, -0.005826600, -0.027235800, -0.082534000, -0.224734000", \ - "0.0063964000, 0.0052274000, 0.0021075000, -0.006030800, -0.027363400, -0.082592200, -0.224736600", \ - "0.0064388000, 0.0051304000, 0.0019172000, -0.006265300, -0.027571100, -0.082710500, -0.224804600", \ - "0.0065946000, 0.0053281000, 0.0020814000, -0.006267100, -0.027732900, -0.082878400, -0.224913300", \ - "0.0075343000, 0.0061748000, 0.0027585000, -0.005797500, -0.027409300, -0.082855200, -0.224977700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012845230, 0.0032999980, 0.0084778460, 0.0217799700, 0.0559537500, 0.1437477000"); - values("0.0079779000, 0.0092423000, 0.0124957000, 0.0208165000, 0.0421052000, 0.0967433000, 0.2370399000", \ - "0.0077978000, 0.0090688000, 0.0123409000, 0.0207037000, 0.0421410000, 0.0967060000, 0.2369151000", \ - "0.0075999000, 0.0088821000, 0.0121737000, 0.0205613000, 0.0419561000, 0.0965198000, 0.2364881000", \ - "0.0074697000, 0.0087305000, 0.0119914000, 0.0203833000, 0.0417820000, 0.0964118000, 0.2361701000", \ - "0.0075015000, 0.0087623000, 0.0120045000, 0.0202983000, 0.0413411000, 0.0960092000, 0.2357121000", \ - "0.0078231000, 0.0089937000, 0.0123892000, 0.0206373000, 0.0417182000, 0.0961630000, 0.2355270000", \ - "0.0098665000, 0.0111705000, 0.0140584000, 0.0220737000, 0.0434921000, 0.0980180000, 0.2369050000"); - } - } - max_capacitance : 0.1437480000; - max_transition : 1.4954820000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.1142771000, 0.1214741000, 0.1379894000, 0.1761503000, 0.2680882000, 0.5018255000, 1.0987802000", \ - "0.1192477000, 0.1263560000, 0.1429227000, 0.1811261000, 0.2730279000, 0.5060523000, 1.1063289000", \ - "0.1320518000, 0.1391876000, 0.1558455000, 0.1939666000, 0.2857802000, 0.5189892000, 1.1168306000", \ - "0.1639708000, 0.1710741000, 0.1875811000, 0.2257784000, 0.3178465000, 0.5525935000, 1.1488565000", \ - "0.2332767000, 0.2404919000, 0.2572912000, 0.2960522000, 0.3885320000, 0.6228182000, 1.2197797000", \ - "0.3505271000, 0.3590135000, 0.3778176000, 0.4177488000, 0.5111255000, 0.7444973000, 1.3452153000", \ - "0.5348711000, 0.5453028000, 0.5679859000, 0.6142348000, 0.7099205000, 0.9436750000, 1.5407339000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0647092000, 0.0707027000, 0.0852548000, 0.1205420000, 0.2097361000, 0.4383320000, 1.0187214000", \ - "0.0695917000, 0.0755775000, 0.0901545000, 0.1256468000, 0.2145641000, 0.4416008000, 1.0260912000", \ - "0.0807341000, 0.0867157000, 0.1012223000, 0.1366916000, 0.2260474000, 0.4559557000, 1.0350939000", \ - "0.1026996000, 0.1086827000, 0.1231660000, 0.1587128000, 0.2487366000, 0.4756232000, 1.0576691000", \ - "0.1333291000, 0.1396334000, 0.1542382000, 0.1903289000, 0.2794900000, 0.5076382000, 1.0918351000", \ - "0.1693588000, 0.1763567000, 0.1922611000, 0.2281011000, 0.3173279000, 0.5449171000, 1.1333769000", \ - "0.1927670000, 0.2020937000, 0.2225117000, 0.2611276000, 0.3496780000, 0.5772716000, 1.1630725000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0372160000, 0.0443882000, 0.0620655000, 0.1077617000, 0.2279992000, 0.5403612000, 1.3416214000", \ - "0.0372964000, 0.0442489000, 0.0620726000, 0.1077661000, 0.2277332000, 0.5410063000, 1.3502058000", \ - "0.0374618000, 0.0444686000, 0.0621909000, 0.1076917000, 0.2277546000, 0.5388898000, 1.3434039000", \ - "0.0374144000, 0.0445705000, 0.0621028000, 0.1077431000, 0.2279530000, 0.5421056000, 1.3440586000", \ - "0.0402575000, 0.0471896000, 0.0642037000, 0.1085775000, 0.2279388000, 0.5395830000, 1.3442623000", \ - "0.0505911000, 0.0572418000, 0.0737015000, 0.1157859000, 0.2299449000, 0.5415198000, 1.3447378000", \ - "0.0695070000, 0.0770888000, 0.0927885000, 0.1319059000, 0.2382369000, 0.5428497000, 1.3454254000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0293368000, 0.0364019000, 0.0550061000, 0.1032940000, 0.2288622000, 0.5555658000, 1.3775108000", \ - "0.0293525000, 0.0363370000, 0.0549420000, 0.1035367000, 0.2295617000, 0.5521226000, 1.3775742000", \ - "0.0294028000, 0.0364459000, 0.0549971000, 0.1034057000, 0.2291902000, 0.5557473000, 1.3856238000", \ - "0.0305270000, 0.0373402000, 0.0554168000, 0.1035638000, 0.2296703000, 0.5528466000, 1.3776881000", \ - "0.0340624000, 0.0403726000, 0.0575769000, 0.1044620000, 0.2287951000, 0.5550253000, 1.3826111000", \ - "0.0432058000, 0.0490273000, 0.0633674000, 0.1073538000, 0.2308657000, 0.5500136000, 1.3838755000", \ - "0.0607123000, 0.0664873000, 0.0801764000, 0.1176471000, 0.2326782000, 0.5552328000, 1.3764138000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0408225000, 0.0467179000, 0.0613358000, 0.0974798000, 0.1889452000, 0.4214383000, 1.0291686000", \ - "0.0445082000, 0.0505611000, 0.0653385000, 0.1018559000, 0.1932578000, 0.4265706000, 1.0232799000", \ - "0.0522079000, 0.0582701000, 0.0733010000, 0.1099285000, 0.2018557000, 0.4352958000, 1.0320655000", \ - "0.0657892000, 0.0736463000, 0.0908523000, 0.1290914000, 0.2217546000, 0.4565501000, 1.0528176000", \ - "0.0831378000, 0.0943314000, 0.1188301000, 0.1683253000, 0.2676401000, 0.5044221000, 1.1075785000", \ - "0.0930698000, 0.1107839000, 0.1491351000, 0.2235937000, 0.3573336000, 0.6140227000, 1.2175040000", \ - "0.0715203000, 0.0987435000, 0.1586095000, 0.2749082000, 0.4785889000, 0.8239022000, 1.4703780000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0419908000, 0.0480118000, 0.0630691000, 0.1008779000, 0.1963755000, 0.4413083000, 1.0677271000", \ - "0.0471001000, 0.0531662000, 0.0681619000, 0.1062313000, 0.2018662000, 0.4460943000, 1.0723763000", \ - "0.0603023000, 0.0663617000, 0.0815009000, 0.1190864000, 0.2149817000, 0.4591344000, 1.0863800000", \ - "0.0912976000, 0.0981278000, 0.1135119000, 0.1513450000, 0.2461631000, 0.4907382000, 1.1168931000", \ - "0.1449530000, 0.1558730000, 0.1795342000, 0.2259700000, 0.3196743000, 0.5628417000, 1.1889731000", \ - "0.2315742000, 0.2488746000, 0.2871432000, 0.3619295000, 0.4927099000, 0.7389653000, 1.3610661000", \ - "0.3750157000, 0.4016112000, 0.4612651000, 0.5802048000, 0.7920871000, 1.1359491000, 1.7654818000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0301822000, 0.0376989000, 0.0567771000, 0.1059858000, 0.2265956000, 0.5396784000, 1.3490705000", \ - "0.0301770000, 0.0378078000, 0.0569903000, 0.1051639000, 0.2276339000, 0.5406101000, 1.3412270000", \ - "0.0312069000, 0.0384943000, 0.0571407000, 0.1050830000, 0.2278318000, 0.5404966000, 1.3410814000", \ - "0.0391425000, 0.0466160000, 0.0625696000, 0.1068929000, 0.2269260000, 0.5398546000, 1.3449969000", \ - "0.0589930000, 0.0668574000, 0.0852510000, 0.1271749000, 0.2344269000, 0.5428735000, 1.3505140000", \ - "0.0986438000, 0.1096063000, 0.1332053000, 0.1827436000, 0.2872616000, 0.5585203000, 1.3501513000", \ - "0.1718455000, 0.1866906000, 0.2200291000, 0.2892801000, 0.4199594000, 0.6860912000, 1.3852532000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0378344000, 0.0456509000, 0.0660840000, 0.1180410000, 0.2521826000, 0.5975709000, 1.4834618000", \ - "0.0379084000, 0.0457914000, 0.0659480000, 0.1180532000, 0.2518439000, 0.5961836000, 1.4817684000", \ - "0.0379814000, 0.0455677000, 0.0660050000, 0.1182210000, 0.2523118000, 0.5968865000, 1.4860334000", \ - "0.0488587000, 0.0544772000, 0.0706980000, 0.1184407000, 0.2522661000, 0.5962036000, 1.4818080000", \ - "0.0796577000, 0.0870351000, 0.1032059000, 0.1393178000, 0.2559584000, 0.5970223000, 1.4861736000", \ - "0.1302668000, 0.1429481000, 0.1691850000, 0.2184737000, 0.3126309000, 0.6049203000, 1.4829150000", \ - "0.2114015000, 0.2323368000, 0.2760988000, 0.3590557000, 0.4957013000, 0.7351724000, 1.4954823000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0453610000, 0.0511701000, 0.0658244000, 0.1023316000, 0.1935272000, 0.4267970000, 1.0236295000", \ - "0.0490779000, 0.0551312000, 0.0698864000, 0.1063508000, 0.1978430000, 0.4317445000, 1.0287901000", \ - "0.0565407000, 0.0626264000, 0.0776389000, 0.1146453000, 0.2058743000, 0.4388834000, 1.0365974000", \ - "0.0694792000, 0.0763183000, 0.0926565000, 0.1301493000, 0.2224885000, 0.4555542000, 1.0566673000", \ - "0.0869359000, 0.0962428000, 0.1171798000, 0.1624285000, 0.2593784000, 0.4942747000, 1.0984914000", \ - "0.0994297000, 0.1142217000, 0.1466099000, 0.2107172000, 0.3331618000, 0.5822389000, 1.1832036000", \ - "0.0804094000, 0.1045473000, 0.1570455000, 0.2587102000, 0.4408922000, 0.7580790000, 1.3905126000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0456624000, 0.0513181000, 0.0653838000, 0.1007001000, 0.1898138000, 0.4167439000, 0.9986783000", \ - "0.0509339000, 0.0565597000, 0.0707283000, 0.1060873000, 0.1952349000, 0.4227777000, 1.0045355000", \ - "0.0643613000, 0.0700946000, 0.0843016000, 0.1198138000, 0.2091145000, 0.4355787000, 1.0172237000", \ - "0.0960159000, 0.1022909000, 0.1161960000, 0.1514890000, 0.2405794000, 0.4661839000, 1.0458588000", \ - "0.1528447000, 0.1622426000, 0.1833970000, 0.2256388000, 0.3128516000, 0.5388323000, 1.1203320000", \ - "0.2435049000, 0.2586946000, 0.2924414000, 0.3603844000, 0.4833349000, 0.7136565000, 1.2837138000", \ - "0.3904050000, 0.4151172000, 0.4660171000, 0.5745157000, 0.7748887000, 1.1012695000, 1.6910768000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0304474000, 0.0380726000, 0.0572501000, 0.1051497000, 0.2276590000, 0.5406643000, 1.3428820000", \ - "0.0304475000, 0.0381972000, 0.0572770000, 0.1056033000, 0.2276036000, 0.5398851000, 1.3442376000", \ - "0.0308790000, 0.0383196000, 0.0573232000, 0.1055586000, 0.2275202000, 0.5394175000, 1.3409829000", \ - "0.0360437000, 0.0433126000, 0.0604914000, 0.1063163000, 0.2268433000, 0.5392783000, 1.3454768000", \ - "0.0511931000, 0.0586354000, 0.0767278000, 0.1209859000, 0.2329409000, 0.5405184000, 1.3464104000", \ - "0.0868455000, 0.0960659000, 0.1172630000, 0.1635355000, 0.2734769000, 0.5541132000, 1.3454859000", \ - "0.1594292000, 0.1712827000, 0.1994563000, 0.2581013000, 0.3822839000, 0.6585036000, 1.3731760000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012845200, 0.0033000000, 0.0084778500, 0.0217800000, 0.0559537000, 0.1437480000"); - values("0.0426280000, 0.0497729000, 0.0683281000, 0.1166795000, 0.2408686000, 0.5616895000, 1.3861358000", \ - "0.0424221000, 0.0497083000, 0.0682729000, 0.1164620000, 0.2411480000, 0.5622711000, 1.3849258000", \ - "0.0422485000, 0.0494304000, 0.0681940000, 0.1165913000, 0.2409275000, 0.5622887000, 1.3876899000", \ - "0.0508631000, 0.0564584000, 0.0721865000, 0.1165821000, 0.2408798000, 0.5612546000, 1.3887986000", \ - "0.0810100000, 0.0881459000, 0.1034501000, 0.1372877000, 0.2458606000, 0.5615869000, 1.3880691000", \ - "0.1331114000, 0.1436049000, 0.1681493000, 0.2152939000, 0.3038626000, 0.5721686000, 1.3867119000", \ - "0.2148717000, 0.2333972000, 0.2738983000, 0.3536449000, 0.4872081000, 0.7172089000, 1.4091459000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3b_2") { - leakage_power () { - value : 0.0009503000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0028061000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0140887000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0008771000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0139842000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0139802000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0015194000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0008294000; - when : "A_N&B&!C"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__nand3b"; - cell_leakage_power : 0.0061294120; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0014470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101873000, 0.0100983000, 0.0098931000, 0.0099328000, 0.0100241000, 0.0102347000, 0.0107202000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0097468000, 0.0097062000, 0.0096127000, 0.0096390000, 0.0096996000, 0.0098392000, 0.0101610000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015040000; - } - pin ("B") { - capacitance : 0.0045160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087414000, 0.0087372000, 0.0087276000, 0.0087388000, 0.0087648000, 0.0088246000, 0.0089624000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008138500, -0.008132000, -0.008116800, -0.008107700, -0.008086700, -0.008038100, -0.007926100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046650000; - } - pin ("C") { - capacitance : 0.0044480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078712000, 0.0078701000, 0.0078677000, 0.0078696000, 0.0078741000, 0.0078845000, 0.0079084000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007859900, -0.007858100, -0.007854000, -0.007854300, -0.007855200, -0.007857200, -0.007861700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046830000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0103534000, 0.0089175000, 0.0050377000, -0.006287900, -0.039820600, -0.136799200, -0.413603600", \ - "0.0103000000, 0.0089587000, 0.0050117000, -0.006345100, -0.039810300, -0.136837300, -0.413496100", \ - "0.0103562000, 0.0089931000, 0.0050718000, -0.006269000, -0.039752900, -0.136809200, -0.413492900", \ - "0.0101779000, 0.0087961000, 0.0048641000, -0.006493400, -0.040028700, -0.137019300, -0.413714300", \ - "0.0099665000, 0.0085646000, 0.0045611000, -0.006889700, -0.040448200, -0.137257900, -0.413865600", \ - "0.0099409000, 0.0085022000, 0.0044170000, -0.007211200, -0.040842800, -0.137622700, -0.414139100", \ - "0.0113284000, 0.0096980000, 0.0062460000, -0.006153000, -0.040241200, -0.137661100, -0.414032500"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0054652000, 0.0071508000, 0.0118106000, 0.0243928000, 0.0588325000, 0.1555910000, 0.4274955000", \ - "0.0054724000, 0.0071484000, 0.0118128000, 0.0243916000, 0.0587860000, 0.1553979000, 0.4319158000", \ - "0.0054262000, 0.0070944000, 0.0117466000, 0.0243611000, 0.0588121000, 0.1552416000, 0.4303658000", \ - "0.0052035000, 0.0068540000, 0.0113982000, 0.0238774000, 0.0584652000, 0.1545736000, 0.4304881000", \ - "0.0050341000, 0.0066114000, 0.0110859000, 0.0232545000, 0.0577710000, 0.1549710000, 0.4269397000", \ - "0.0051574000, 0.0066763000, 0.0110132000, 0.0232206000, 0.0575182000, 0.1537023000, 0.4307853000", \ - "0.0059753000, 0.0073507000, 0.0116050000, 0.0238339000, 0.0576310000, 0.1546397000, 0.4270247000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0130023000, 0.0116261000, 0.0075866000, -0.004177800, -0.038291500, -0.135669100, -0.412468600", \ - "0.0125731000, 0.0112283000, 0.0073023000, -0.004319800, -0.038368800, -0.135672100, -0.412512300", \ - "0.0120961000, 0.0107532000, 0.0068522000, -0.004648300, -0.038513700, -0.135762300, -0.412582300", \ - "0.0116608000, 0.0102973000, 0.0063691000, -0.005113800, -0.038817200, -0.135906300, -0.412642700", \ - "0.0118320000, 0.0103593000, 0.0061670000, -0.005465500, -0.039160100, -0.136104900, -0.412754200", \ - "0.0124420000, 0.0109247000, 0.0066545000, -0.005494100, -0.039598000, -0.136504500, -0.412885000", \ - "0.0146092000, 0.0128898000, 0.0083042000, -0.004196800, -0.038898900, -0.136582100, -0.413173000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0096128000, 0.0110961000, 0.0152843000, 0.0271292000, 0.0609614000, 0.1570709000, 0.4301393000", \ - "0.0090852000, 0.0105763000, 0.0148467000, 0.0268702000, 0.0609005000, 0.1569310000, 0.4300623000", \ - "0.0084720000, 0.0100079000, 0.0143766000, 0.0263648000, 0.0604511000, 0.1568914000, 0.4300012000", \ - "0.0081042000, 0.0096534000, 0.0139296000, 0.0257612000, 0.0601059000, 0.1565042000, 0.4300936000", \ - "0.0082161000, 0.0097161000, 0.0139369000, 0.0259275000, 0.0599138000, 0.1563093000, 0.4283065000", \ - "0.0083591000, 0.0097777000, 0.0139375000, 0.0262368000, 0.0597890000, 0.1560421000, 0.4290542000", \ - "0.0116023000, 0.0129393000, 0.0167655000, 0.0280415000, 0.0612797000, 0.1561923000, 0.4282197000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0130708000, 0.0116749000, 0.0076317000, -0.004150000, -0.038264100, -0.135658300, -0.412499600", \ - "0.0126915000, 0.0113413000, 0.0073924000, -0.004294700, -0.038326100, -0.135678700, -0.412523000", \ - "0.0122130000, 0.0108661000, 0.0069757000, -0.004570900, -0.038476800, -0.135719500, -0.412550400", \ - "0.0118044000, 0.0104202000, 0.0065003000, -0.005005600, -0.038724100, -0.135829400, -0.412593700", \ - "0.0118604000, 0.0103922000, 0.0062993000, -0.005325500, -0.039039700, -0.135997400, -0.412659300", \ - "0.0123137000, 0.0108190000, 0.0066201000, -0.005363900, -0.039466200, -0.136412500, -0.412917600", \ - "0.0137263000, 0.0121344000, 0.0076956000, -0.004610700, -0.038964100, -0.136455100, -0.413003900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014211990, 0.0040396160, 0.0114822000, 0.0326369900, 0.0927673400, 0.2636818000"); - values("0.0149132000, 0.0163877000, 0.0205408000, 0.0324424000, 0.0663811000, 0.1625163000, 0.4362489000", \ - "0.0146053000, 0.0160727000, 0.0202634000, 0.0322434000, 0.0662262000, 0.1623813000, 0.4354150000", \ - "0.0141826000, 0.0156794000, 0.0199373000, 0.0319258000, 0.0659170000, 0.1622465000, 0.4353004000", \ - "0.0138581000, 0.0153747000, 0.0195796000, 0.0315295000, 0.0656934000, 0.1621131000, 0.4353843000", \ - "0.0138808000, 0.0153637000, 0.0196181000, 0.0316233000, 0.0652350000, 0.1615721000, 0.4351306000", \ - "0.0141422000, 0.0155660000, 0.0200498000, 0.0320881000, 0.0658237000, 0.1617801000, 0.4342546000", \ - "0.0173040000, 0.0186661000, 0.0224707000, 0.0338443000, 0.0677671000, 0.1627111000, 0.4345510000"); - } - } - max_capacitance : 0.2636820000; - max_transition : 1.4919890000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.1605845000, 0.1668771000, 0.1824820000, 0.2191928000, 0.3076967000, 0.5462789000, 1.2212301000", \ - "0.1656500000, 0.1718461000, 0.1873207000, 0.2239353000, 0.3128172000, 0.5515035000, 1.2243012000", \ - "0.1781502000, 0.1843684000, 0.1999397000, 0.2373146000, 0.3259269000, 0.5648023000, 1.2451679000", \ - "0.2101034000, 0.2163066000, 0.2318279000, 0.2684281000, 0.3572774000, 0.5965929000, 1.2696342000", \ - "0.2850147000, 0.2911676000, 0.3064726000, 0.3429990000, 0.4316656000, 0.6700214000, 1.3431694000", \ - "0.4308325000, 0.4378378000, 0.4550617000, 0.4938073000, 0.5837746000, 0.8226086000, 1.4954811000", \ - "0.6627579000, 0.6717154000, 0.6936079000, 0.7399055000, 0.8353850000, 1.0740188000, 1.7474224000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0794193000, 0.0838406000, 0.0952136000, 0.1234945000, 0.1981366000, 0.4065701000, 0.9947739000", \ - "0.0843049000, 0.0887164000, 0.1001001000, 0.1283913000, 0.2032066000, 0.4123718000, 1.0014042000", \ - "0.0957989000, 0.1001832000, 0.1115382000, 0.1399110000, 0.2145972000, 0.4228468000, 1.0173556000", \ - "0.1216655000, 0.1259666000, 0.1371899000, 0.1656274000, 0.2404086000, 0.4504884000, 1.0457653000", \ - "0.1641661000, 0.1688567000, 0.1805900000, 0.2092754000, 0.2846672000, 0.4939832000, 1.0818754000", \ - "0.2179733000, 0.2238191000, 0.2377826000, 0.2682117000, 0.3431476000, 0.5512784000, 1.1405793000", \ - "0.2701171000, 0.2779215000, 0.2961555000, 0.3336272000, 0.4103692000, 0.6183516000, 1.2083146000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0442448000, 0.0494965000, 0.0636942000, 0.1020544000, 0.2109371000, 0.5312817000, 1.4515767000", \ - "0.0441952000, 0.0495205000, 0.0640487000, 0.1019415000, 0.2111374000, 0.5321040000, 1.4515735000", \ - "0.0444404000, 0.0500651000, 0.0640123000, 0.1021964000, 0.2109766000, 0.5320011000, 1.4563635000", \ - "0.0442272000, 0.0497175000, 0.0640069000, 0.1019337000, 0.2109558000, 0.5323769000, 1.4508169000", \ - "0.0447398000, 0.0503524000, 0.0638131000, 0.1025440000, 0.2113004000, 0.5322577000, 1.4540666000", \ - "0.0567560000, 0.0617301000, 0.0753341000, 0.1101427000, 0.2147003000, 0.5320398000, 1.4513168000", \ - "0.0796518000, 0.0853559000, 0.0993529000, 0.1336967000, 0.2306232000, 0.5361588000, 1.4554155000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0281791000, 0.0324372000, 0.0445991000, 0.0801608000, 0.1843182000, 0.4847129000, 1.3375460000", \ - "0.0282005000, 0.0324457000, 0.0445928000, 0.0802712000, 0.1849543000, 0.4855521000, 1.3424165000", \ - "0.0281990000, 0.0324699000, 0.0446393000, 0.0802144000, 0.1846714000, 0.4854236000, 1.3432372000", \ - "0.0288477000, 0.0329815000, 0.0451343000, 0.0804829000, 0.1848180000, 0.4845710000, 1.3444429000", \ - "0.0342104000, 0.0380553000, 0.0490158000, 0.0829606000, 0.1848191000, 0.4856701000, 1.3383241000", \ - "0.0458754000, 0.0495697000, 0.0594274000, 0.0891133000, 0.1875043000, 0.4830401000, 1.3414421000", \ - "0.0663666000, 0.0704418000, 0.0816070000, 0.1081710000, 0.1955013000, 0.4857607000, 1.3345847000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0419466000, 0.0463176000, 0.0580734000, 0.0896013000, 0.1749830000, 0.4126562000, 1.0970403000", \ - "0.0456981000, 0.0501679000, 0.0622156000, 0.0940691000, 0.1795395000, 0.4180998000, 1.1006346000", \ - "0.0536692000, 0.0581894000, 0.0703122000, 0.1026429000, 0.1887727000, 0.4275277000, 1.1007419000", \ - "0.0667134000, 0.0722692000, 0.0866107000, 0.1206770000, 0.2075038000, 0.4470758000, 1.1221272000", \ - "0.0835866000, 0.0916276000, 0.1112013000, 0.1561662000, 0.2527356000, 0.4932775000, 1.1678341000", \ - "0.0923782000, 0.1048840000, 0.1363209000, 0.2046733000, 0.3392061000, 0.6035559000, 1.2820868000", \ - "0.0694306000, 0.0894782000, 0.1384516000, 0.2451134000, 0.4484720000, 0.8184149000, 1.5418331000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0393675000, 0.0432741000, 0.0539956000, 0.0833979000, 0.1648898000, 0.3936637000, 1.0426991000", \ - "0.0441655000, 0.0480147000, 0.0589230000, 0.0887206000, 0.1704764000, 0.3999333000, 1.0481096000", \ - "0.0568564000, 0.0607735000, 0.0716327000, 0.1012825000, 0.1831060000, 0.4124573000, 1.0611944000", \ - "0.0865081000, 0.0913398000, 0.1032978000, 0.1317919000, 0.2144356000, 0.4447675000, 1.0930312000", \ - "0.1348203000, 0.1422178000, 0.1610120000, 0.2026890000, 0.2874514000, 0.5159891000, 1.1625928000", \ - "0.2131426000, 0.2246363000, 0.2535299000, 0.3199426000, 0.4466762000, 0.6869370000, 1.3353154000", \ - "0.3426026000, 0.3593975000, 0.4033345000, 0.5056950000, 0.7079970000, 1.0614756000, 1.7271098000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0286663000, 0.0342603000, 0.0497370000, 0.0919110000, 0.2078816000, 0.5323655000, 1.4617784000", \ - "0.0286436000, 0.0342216000, 0.0497835000, 0.0919950000, 0.2077909000, 0.5317539000, 1.4612902000", \ - "0.0295573000, 0.0349267000, 0.0499272000, 0.0922503000, 0.2078519000, 0.5332811000, 1.4523535000", \ - "0.0367977000, 0.0421879000, 0.0559355000, 0.0943127000, 0.2066241000, 0.5309221000, 1.4539179000", \ - "0.0541747000, 0.0603782000, 0.0759626000, 0.1140442000, 0.2152640000, 0.5303868000, 1.4539032000", \ - "0.0920749000, 0.1000331000, 0.1200278000, 0.1663846000, 0.2704140000, 0.5508221000, 1.4532301000", \ - "0.1644246000, 0.1747814000, 0.2026248000, 0.2666066000, 0.3973595000, 0.6843714000, 1.4855177000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0351797000, 0.0402501000, 0.0544686000, 0.0947152000, 0.2100824000, 0.5388781000, 1.4732445000", \ - "0.0352034000, 0.0402694000, 0.0545411000, 0.0949405000, 0.2101599000, 0.5390824000, 1.4735828000", \ - "0.0356205000, 0.0402934000, 0.0544268000, 0.0950333000, 0.2107280000, 0.5386057000, 1.4735640000", \ - "0.0479208000, 0.0516037000, 0.0622013000, 0.0970892000, 0.2107001000, 0.5384755000, 1.4735771000", \ - "0.0766045000, 0.0820518000, 0.0949103000, 0.1249793000, 0.2187712000, 0.5384150000, 1.4737764000", \ - "0.1237949000, 0.1323703000, 0.1533167000, 0.1977122000, 0.2853217000, 0.5554081000, 1.4747475000", \ - "0.1991227000, 0.2127354000, 0.2490509000, 0.3216535000, 0.4572105000, 0.7038929000, 1.4919807000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0471667000, 0.0514647000, 0.0632949000, 0.0951857000, 0.1808987000, 0.4187307000, 1.0919352000", \ - "0.0508127000, 0.0552297000, 0.0673096000, 0.0992603000, 0.1851926000, 0.4234117000, 1.0964353000", \ - "0.0579298000, 0.0624543000, 0.0746956000, 0.1072380000, 0.1931761000, 0.4307838000, 1.1040862000", \ - "0.0702185000, 0.0751805000, 0.0882293000, 0.1214110000, 0.2082027000, 0.4474257000, 1.1204841000", \ - "0.0865216000, 0.0927935000, 0.1089316000, 0.1477581000, 0.2399624000, 0.4796108000, 1.1537260000", \ - "0.0968568000, 0.1068625000, 0.1313111000, 0.1863027000, 0.3012917000, 0.5577911000, 1.2361827000", \ - "0.0714637000, 0.0881545000, 0.1289011000, 0.2177388000, 0.3875345000, 0.7128363000, 1.4202063000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0471912000, 0.0511379000, 0.0618837000, 0.0913834000, 0.1725410000, 0.4000229000, 1.0454706000", \ - "0.0524153000, 0.0563198000, 0.0671856000, 0.0967601000, 0.1780173000, 0.4054282000, 1.0499409000", \ - "0.0657194000, 0.0696939000, 0.0805968000, 0.1100472000, 0.1915865000, 0.4189931000, 1.0636830000", \ - "0.0975468000, 0.1019560000, 0.1125168000, 0.1416998000, 0.2228040000, 0.4502968000, 1.0955362000", \ - "0.1555215000, 0.1618633000, 0.1781587000, 0.2156134000, 0.2973458000, 0.5250886000, 1.1691846000", \ - "0.2481541000, 0.2580715000, 0.2838024000, 0.3433845000, 0.4638654000, 0.6976264000, 1.3380913000", \ - "0.4000821000, 0.4154052000, 0.4548934000, 0.5488129000, 0.7405309000, 1.0842369000, 1.7381203000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0289043000, 0.0347452000, 0.0501827000, 0.0926864000, 0.2077955000, 0.5304993000, 1.4515396000", \ - "0.0289575000, 0.0348014000, 0.0504312000, 0.0923493000, 0.2077615000, 0.5305980000, 1.4515364000", \ - "0.0292437000, 0.0347703000, 0.0504841000, 0.0923390000, 0.2081254000, 0.5321146000, 1.4509303000", \ - "0.0335532000, 0.0389729000, 0.0533392000, 0.0935441000, 0.2078217000, 0.5328047000, 1.4527365000", \ - "0.0449132000, 0.0504938000, 0.0656769000, 0.1055558000, 0.2125552000, 0.5307778000, 1.4532020000", \ - "0.0759798000, 0.0827595000, 0.0996110000, 0.1415710000, 0.2486331000, 0.5452215000, 1.4575734000", \ - "0.1449478000, 0.1536392000, 0.1755927000, 0.2267253000, 0.3418658000, 0.6353994000, 1.4770227000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014212000, 0.0040396200, 0.0114822000, 0.0326370000, 0.0927673000, 0.2636820000"); - values("0.0448074000, 0.0494654000, 0.0634457000, 0.1030936000, 0.2168144000, 0.5436304000, 1.4750522000", \ - "0.0445819000, 0.0495408000, 0.0633533000, 0.1029700000, 0.2168729000, 0.5436666000, 1.4742959000", \ - "0.0440903000, 0.0490330000, 0.0631198000, 0.1028004000, 0.2167335000, 0.5436301000, 1.4737709000", \ - "0.0518388000, 0.0558910000, 0.0674839000, 0.1036119000, 0.2167968000, 0.5438038000, 1.4752204000", \ - "0.0808992000, 0.0857747000, 0.0978252000, 0.1272216000, 0.2231863000, 0.5433591000, 1.4729988000", \ - "0.1302232000, 0.1378935000, 0.1571150000, 0.1989859000, 0.2866825000, 0.5571412000, 1.4750363000", \ - "0.2110670000, 0.2239737000, 0.2542752000, 0.3245779000, 0.4572659000, 0.7003671000, 1.4919892000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand3b_4") { - leakage_power () { - value : 0.0016853000; - when : "!A_N&!B&C"; - } - leakage_power () { - value : 0.0406824000; - when : "!A_N&!B&!C"; - } - leakage_power () { - value : 0.0147872000; - when : "!A_N&B&C"; - } - leakage_power () { - value : 0.0014284000; - when : "!A_N&B&!C"; - } - leakage_power () { - value : 0.0106302000; - when : "A_N&!B&C"; - } - leakage_power () { - value : 0.0304876000; - when : "A_N&!B&!C"; - } - leakage_power () { - value : 0.0123664000; - when : "A_N&B&C"; - } - leakage_power () { - value : 0.0106099000; - when : "A_N&B&!C"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__nand3b"; - cell_leakage_power : 0.0153347000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0023570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0174003000, 0.0172767000, 0.0169919000, 0.0171257000, 0.0174344000, 0.0181460000, 0.0197862000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0177306000, 0.0176176000, 0.0173572000, 0.0174806000, 0.0177651000, 0.0184210000, 0.0199330000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024570000; - } - pin ("B") { - capacitance : 0.0084720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0170075000, 0.0170228000, 0.0170580000, 0.0170768000, 0.0171201000, 0.0172199000, 0.0174502000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015615000, -0.015614700, -0.015614000, -0.015578700, -0.015497200, -0.015309400, -0.014876400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087780000; - } - pin ("C") { - capacitance : 0.0088630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0160060000, 0.0159939000, 0.0159659000, 0.0159707000, 0.0159818000, 0.0160073000, 0.0160663000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015963100, -0.015956300, -0.015940900, -0.015936000, -0.015924700, -0.015898800, -0.015838900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0093360000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0266510000, 0.0250244000, 0.0198749000, 0.0032153000, -0.050187500, -0.218799200, -0.748388800", \ - "0.0257413000, 0.0242108000, 0.0192150000, 0.0028392000, -0.050334900, -0.218787700, -0.748433800", \ - "0.0246982000, 0.0231658000, 0.0182499000, 0.0020986000, -0.050716100, -0.218938300, -0.748485500", \ - "0.0238481000, 0.0222537000, 0.0171579000, 0.0009900000, -0.051461300, -0.219276800, -0.748607300", \ - "0.0237294000, 0.0220582000, 0.0167759000, 0.0002114000, -0.052364800, -0.219835500, -0.748768100", \ - "0.0244620000, 0.0227318000, 0.0172665000, 0.0001963000, -0.053472000, -0.220851700, -0.749551600", \ - "0.0281929000, 0.0262978000, 0.0203509000, 0.0023069000, -0.052145100, -0.221157600, -0.750291900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0179628000, 0.0197003000, 0.0251863000, 0.0421871000, 0.0953592000, 0.2616700000, 0.7841056000", \ - "0.0169124000, 0.0187405000, 0.0242929000, 0.0415964000, 0.0951934000, 0.2619506000, 0.7842605000", \ - "0.0156523000, 0.0175341000, 0.0232279000, 0.0407541000, 0.0942446000, 0.2613913000, 0.7840640000", \ - "0.0149924000, 0.0168204000, 0.0223872000, 0.0394273000, 0.0934866000, 0.2608281000, 0.7846278000", \ - "0.0151299000, 0.0168440000, 0.0224133000, 0.0391933000, 0.0924784000, 0.2594812000, 0.7820618000", \ - "0.0157364000, 0.0174220000, 0.0228906000, 0.0399031000, 0.0928177000, 0.2579864000, 0.7814315000", \ - "0.0216191000, 0.0231116000, 0.0280478000, 0.0437986000, 0.0953670000, 0.2600684000, 0.7804887000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0268749000, 0.0252802000, 0.0200862000, 0.0034034000, -0.050051000, -0.218656800, -0.748306500", \ - "0.0260242000, 0.0244733000, 0.0194382000, 0.0030088000, -0.050245600, -0.218677100, -0.748316400", \ - "0.0250043000, 0.0234763000, 0.0184849000, 0.0022605000, -0.050612800, -0.218851800, -0.748432300", \ - "0.0241226000, 0.0225139000, 0.0174641000, 0.0012467000, -0.051304500, -0.219168900, -0.748553400", \ - "0.0239904000, 0.0223064000, 0.0170320000, 0.0005413000, -0.052145300, -0.219600500, -0.748697000", \ - "0.0247302000, 0.0229687000, 0.0175918000, 0.0006373000, -0.052965300, -0.220592700, -0.749161800", \ - "0.0283111000, 0.0264175000, 0.0205546000, 0.0027490000, -0.051561000, -0.220502600, -0.749555500"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0290896000, 0.0308315000, 0.0362425000, 0.0532609000, 0.1066170000, 0.2732143000, 0.7960479000", \ - "0.0283430000, 0.0301030000, 0.0355786000, 0.0527339000, 0.1060907000, 0.2727282000, 0.7955306000", \ - "0.0275097000, 0.0293136000, 0.0347162000, 0.0520712000, 0.1056178000, 0.2726434000, 0.7953638000", \ - "0.0269217000, 0.0285462000, 0.0340525000, 0.0513182000, 0.1050764000, 0.2720215000, 0.7951775000", \ - "0.0265505000, 0.0283504000, 0.0346645000, 0.0516250000, 0.1049876000, 0.2721296000, 0.7944279000", \ - "0.0296318000, 0.0312522000, 0.0361874000, 0.0533035000, 0.1061528000, 0.2722681000, 0.7947871000", \ - "0.0347915000, 0.0363888000, 0.0415053000, 0.0571303000, 0.1096756000, 0.2749691000, 0.7951327000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0211471000, 0.0195515000, 0.0146809000, -0.001368500, -0.053965200, -0.222244200, -0.751803500", \ - "0.0210703000, 0.0195457000, 0.0145782000, -0.001415300, -0.054017800, -0.222335300, -0.751645500", \ - "0.0211546000, 0.0195475000, 0.0146485000, -0.001466600, -0.054018200, -0.222083000, -0.751508400", \ - "0.0207063000, 0.0191381000, 0.0141002000, -0.002082600, -0.054680200, -0.222511600, -0.751971300", \ - "0.0199757000, 0.0183480000, 0.0132416000, -0.003027700, -0.055507700, -0.223208500, -0.752358800", \ - "0.0194001000, 0.0177594000, 0.0126277000, -0.003563700, -0.056207800, -0.223780600, -0.752750900", \ - "0.0212564000, 0.0197219000, 0.0145180000, -0.003327300, -0.056152200, -0.223572900, -0.752470200"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015702790, 0.0049315550, 0.0154878400, 0.0486404600, 0.1527582000, 0.4797462000"); - values("0.0104443000, 0.0124120000, 0.0185436000, 0.0368550000, 0.0912748000, 0.2578964000, 0.7819453000", \ - "0.0104369000, 0.0124022000, 0.0185458000, 0.0368669000, 0.0914161000, 0.2591642000, 0.7847402000", \ - "0.0104308000, 0.0123940000, 0.0185120000, 0.0368216000, 0.0914789000, 0.2593560000, 0.7846003000", \ - "0.0098187000, 0.0117915000, 0.0176513000, 0.0358767000, 0.0906376000, 0.2572733000, 0.7843387000", \ - "0.0092823000, 0.0111375000, 0.0170148000, 0.0345227000, 0.0891194000, 0.2571854000, 0.7847299000", \ - "0.0096181000, 0.0114284000, 0.0170757000, 0.0341332000, 0.0882604000, 0.2554784000, 0.7817247000", \ - "0.0104190000, 0.0120986000, 0.0176193000, 0.0348561000, 0.0885468000, 0.2567189000, 0.7771575000"); - } - } - max_capacitance : 0.4797460000; - max_transition : 1.5009230000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.1191366000, 0.1225463000, 0.1324881000, 0.1596446000, 0.2344029000, 0.4612593000, 1.1710496000", \ - "0.1242498000, 0.1276723000, 0.1374356000, 0.1646353000, 0.2394109000, 0.4662578000, 1.1720903000", \ - "0.1370431000, 0.1403790000, 0.1502913000, 0.1774546000, 0.2523594000, 0.4795073000, 1.1848534000", \ - "0.1668169000, 0.1701978000, 0.1800872000, 0.2071883000, 0.2821046000, 0.5092182000, 1.2159658000", \ - "0.2338588000, 0.2373481000, 0.2473148000, 0.2745353000, 0.3497840000, 0.5770510000, 1.2822898000", \ - "0.3415476000, 0.3457228000, 0.3574393000, 0.3873691000, 0.4645696000, 0.6912926000, 1.3983498000", \ - "0.4985237000, 0.5041054000, 0.5192374000, 0.5550596000, 0.6367605000, 0.8634617000, 1.5713328000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0901781000, 0.0932362000, 0.1020195000, 0.1263525000, 0.1949108000, 0.4034368000, 1.0559008000", \ - "0.0949992000, 0.0980713000, 0.1068514000, 0.1311583000, 0.1998666000, 0.4089337000, 1.0638773000", \ - "0.1063483000, 0.1093826000, 0.1181626000, 0.1424630000, 0.2109921000, 0.4205519000, 1.0764991000", \ - "0.1327446000, 0.1357944000, 0.1443750000, 0.1684904000, 0.2373386000, 0.4461441000, 1.1031629000", \ - "0.1809226000, 0.1841163000, 0.1931397000, 0.2175707000, 0.2864329000, 0.4972662000, 1.1525100000", \ - "0.2456404000, 0.2494550000, 0.2601549000, 0.2863511000, 0.3560377000, 0.5657267000, 1.2182594000", \ - "0.3212991000, 0.3264379000, 0.3402536000, 0.3732111000, 0.4463276000, 0.6536567000, 1.3056021000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0370566000, 0.0404037000, 0.0504450000, 0.0814434000, 0.1781783000, 0.4896409000, 1.4740111000", \ - "0.0366744000, 0.0400980000, 0.0504061000, 0.0814488000, 0.1781694000, 0.4897263000, 1.4671169000", \ - "0.0367575000, 0.0404353000, 0.0504578000, 0.0814799000, 0.1782405000, 0.4887182000, 1.4671516000", \ - "0.0369792000, 0.0403010000, 0.0504579000, 0.0815747000, 0.1781718000, 0.4896353000, 1.4665542000", \ - "0.0395277000, 0.0427183000, 0.0525929000, 0.0827433000, 0.1785347000, 0.4898094000, 1.4662251000", \ - "0.0517718000, 0.0546820000, 0.0638251000, 0.0922593000, 0.1834285000, 0.4891494000, 1.4680083000", \ - "0.0725058000, 0.0761927000, 0.0863937000, 0.1150721000, 0.1976105000, 0.4926223000, 1.4670185000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0303122000, 0.0331092000, 0.0418229000, 0.0701160000, 0.1625738000, 0.4589830000, 1.3881527000", \ - "0.0303058000, 0.0331076000, 0.0418177000, 0.0700661000, 0.1624584000, 0.4595631000, 1.3895768000", \ - "0.0303291000, 0.0330486000, 0.0417854000, 0.0700785000, 0.1626998000, 0.4601722000, 1.3956889000", \ - "0.0306382000, 0.0333751000, 0.0421203000, 0.0703099000, 0.1627663000, 0.4566465000, 1.3944816000", \ - "0.0354991000, 0.0380856000, 0.0461099000, 0.0728798000, 0.1632660000, 0.4596766000, 1.3910008000", \ - "0.0466516000, 0.0497789000, 0.0567847000, 0.0806731000, 0.1660768000, 0.4567615000, 1.3849251000", \ - "0.0666052000, 0.0691891000, 0.0766783000, 0.0992635000, 0.1750948000, 0.4602752000, 1.3813464000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0452141000, 0.0479948000, 0.0564128000, 0.0808373000, 0.1540812000, 0.3793234000, 1.0861633000", \ - "0.0485300000, 0.0513546000, 0.0597799000, 0.0846099000, 0.1579929000, 0.3854434000, 1.0897576000", \ - "0.0554329000, 0.0582887000, 0.0668618000, 0.0921684000, 0.1660252000, 0.3917497000, 1.1008232000", \ - "0.0669452000, 0.0704555000, 0.0806042000, 0.1084241000, 0.1833451000, 0.4111851000, 1.1164716000", \ - "0.0810743000, 0.0864233000, 0.1013012000, 0.1378741000, 0.2253461000, 0.4558594000, 1.1700396000", \ - "0.0853288000, 0.0932677000, 0.1161507000, 0.1734303000, 0.2967092000, 0.5590428000, 1.2712620000", \ - "0.0515527000, 0.0642328000, 0.0998928000, 0.1891329000, 0.3799577000, 0.7475728000, 1.5149852000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0416727000, 0.0441413000, 0.0517778000, 0.0746762000, 0.1441739000, 0.3590455000, 1.0352060000", \ - "0.0463273000, 0.0488675000, 0.0566062000, 0.0798713000, 0.1498222000, 0.3646365000, 1.0371090000", \ - "0.0590877000, 0.0616468000, 0.0693824000, 0.0926944000, 0.1625179000, 0.3783361000, 1.0499238000", \ - "0.0896552000, 0.0925839000, 0.1011022000, 0.1239763000, 0.1940486000, 0.4096385000, 1.0809302000", \ - "0.1403772000, 0.1451532000, 0.1581444000, 0.1921379000, 0.2679885000, 0.4828816000, 1.1512726000", \ - "0.2238986000, 0.2311728000, 0.2519057000, 0.3060613000, 0.4231338000, 0.6550357000, 1.3255022000", \ - "0.3651864000, 0.3758370000, 0.4071855000, 0.4891718000, 0.6759310000, 1.0278599000, 1.7191143000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0295873000, 0.0332058000, 0.0441318000, 0.0770256000, 0.1767560000, 0.4884355000, 1.4657395000", \ - "0.0296910000, 0.0332275000, 0.0441031000, 0.0768863000, 0.1770241000, 0.4902257000, 1.4684657000", \ - "0.0305040000, 0.0338291000, 0.0443698000, 0.0769882000, 0.1768413000, 0.4884221000, 1.4682907000", \ - "0.0378351000, 0.0412913000, 0.0513911000, 0.0804991000, 0.1769555000, 0.4893059000, 1.4649482000", \ - "0.0554176000, 0.0593318000, 0.0705581000, 0.1013412000, 0.1886414000, 0.4890368000, 1.4751959000", \ - "0.0939410000, 0.0988371000, 0.1135898000, 0.1512629000, 0.2437899000, 0.5126334000, 1.4658322000", \ - "0.1670342000, 0.1734356000, 0.1936866000, 0.2449577000, 0.3636277000, 0.6468471000, 1.5009232000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0361157000, 0.0391290000, 0.0487357000, 0.0790692000, 0.1750073000, 0.4778776000, 1.4293092000", \ - "0.0360914000, 0.0391730000, 0.0485402000, 0.0790899000, 0.1746407000, 0.4769956000, 1.4274328000", \ - "0.0361495000, 0.0390027000, 0.0485650000, 0.0787882000, 0.1747521000, 0.4777148000, 1.4278919000", \ - "0.0473005000, 0.0495730000, 0.0565069000, 0.0817346000, 0.1751132000, 0.4768739000, 1.4278503000", \ - "0.0756978000, 0.0788384000, 0.0884898000, 0.1122098000, 0.1848608000, 0.4772447000, 1.4276865000", \ - "0.1225051000, 0.1277710000, 0.1429407000, 0.1798319000, 0.2590796000, 0.4978818000, 1.4280922000", \ - "0.1975622000, 0.2065075000, 0.2307627000, 0.2937536000, 0.4179737000, 0.6537552000, 1.4488832000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0495813000, 0.0524053000, 0.0605956000, 0.0850201000, 0.1580065000, 0.3852440000, 1.0983405000", \ - "0.0529712000, 0.0557614000, 0.0642696000, 0.0892434000, 0.1624468000, 0.3884690000, 1.1035713000", \ - "0.0593628000, 0.0622963000, 0.0708821000, 0.0958900000, 0.1698721000, 0.3954811000, 1.1019715000", \ - "0.0701946000, 0.0733147000, 0.0826137000, 0.1089041000, 0.1832931000, 0.4095457000, 1.1164373000", \ - "0.0843389000, 0.0882365000, 0.0996174000, 0.1308266000, 0.2123320000, 0.4412708000, 1.1480645000", \ - "0.0912469000, 0.0971590000, 0.1148724000, 0.1601636000, 0.2643945000, 0.5129533000, 1.2228275000", \ - "0.0601253000, 0.0705612000, 0.0999646000, 0.1733013000, 0.3297325000, 0.6497379000, 1.3954526000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0458201000, 0.0481417000, 0.0551874000, 0.0765031000, 0.1405917000, 0.3371333000, 0.9514662000", \ - "0.0508765000, 0.0532214000, 0.0603474000, 0.0817416000, 0.1459154000, 0.3426489000, 0.9572896000", \ - "0.0636935000, 0.0660390000, 0.0731522000, 0.0946295000, 0.1588401000, 0.3555549000, 0.9703552000", \ - "0.0951444000, 0.0980850000, 0.1053638000, 0.1264556000, 0.1908129000, 0.3878374000, 1.0020387000", \ - "0.1512288000, 0.1551232000, 0.1660054000, 0.1959005000, 0.2644245000, 0.4607042000, 1.0744067000", \ - "0.2405833000, 0.2465133000, 0.2630214000, 0.3111004000, 0.4161453000, 0.6319439000, 1.2428280000", \ - "0.3879606000, 0.3968824000, 0.4223415000, 0.4949054000, 0.6623679000, 0.9949905000, 1.6394993000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0297953000, 0.0332626000, 0.0441690000, 0.0769902000, 0.1768356000, 0.4900680000, 1.4747601000", \ - "0.0297799000, 0.0333344000, 0.0442301000, 0.0772467000, 0.1767847000, 0.4886754000, 1.4755112000", \ - "0.0299933000, 0.0335347000, 0.0443602000, 0.0769381000, 0.1768299000, 0.4883828000, 1.4678333000", \ - "0.0344440000, 0.0378222000, 0.0481691000, 0.0789389000, 0.1769489000, 0.4884926000, 1.4679992000", \ - "0.0458358000, 0.0493483000, 0.0598338000, 0.0916160000, 0.1843568000, 0.4888395000, 1.4685624000", \ - "0.0780212000, 0.0820401000, 0.0939982000, 0.1272669000, 0.2209548000, 0.5057670000, 1.4672780000", \ - "0.1486700000, 0.1535095000, 0.1681426000, 0.2093067000, 0.3110284000, 0.5979331000, 1.4919393000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015702800, 0.0049315500, 0.0154878000, 0.0486405000, 0.1527580000, 0.4797460000"); - values("0.0442696000, 0.0468705000, 0.0557587000, 0.0833089000, 0.1719372000, 0.4531153000, 1.3407062000", \ - "0.0441601000, 0.0468462000, 0.0556609000, 0.0834196000, 0.1719495000, 0.4538317000, 1.3411589000", \ - "0.0432973000, 0.0461415000, 0.0549870000, 0.0831360000, 0.1719710000, 0.4534165000, 1.3412093000", \ - "0.0517730000, 0.0538207000, 0.0610331000, 0.0853704000, 0.1717983000, 0.4538463000, 1.3401331000", \ - "0.0799606000, 0.0829280000, 0.0919140000, 0.1134097000, 0.1833648000, 0.4534407000, 1.3410469000", \ - "0.1279850000, 0.1331737000, 0.1461356000, 0.1808538000, 0.2562194000, 0.4777423000, 1.3408981000", \ - "0.2049712000, 0.2129739000, 0.2353072000, 0.2923546000, 0.4120191000, 0.6400757000, 1.3710747000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4_1") { - leakage_power () { - value : 2.6603169e-05; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 1.9808313e-05; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 4.3621706e-05; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 2.4194187e-05; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 4.382749e-05; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 2.4799466e-05; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0003519000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 3.617058e-05; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 4.9541551e-05; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 3.0294963e-05; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0003530000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 4.1828364e-05; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0003428000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 4.7061493e-05; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0067214000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0002583000; - when : "A&B&C&!D"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nand4"; - cell_leakage_power : 0.0005259485; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048946000, 0.0048999000, 0.0049121000, 0.0049129000, 0.0049147000, 0.0049189000, 0.0049286000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003914800, -0.003907000, -0.003889100, -0.003882500, -0.003867400, -0.003832400, -0.003751700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023520000; - } - pin ("B") { - capacitance : 0.0023910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023230000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045984000, 0.0045952000, 0.0045878000, 0.0046022000, 0.0046355000, 0.0047122000, 0.0048890000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004193200, -0.004190100, -0.004183100, -0.004182300, -0.004180600, -0.004176600, -0.004167500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024590000; - } - pin ("C") { - capacitance : 0.0023490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039392000, 0.0039398000, 0.0039413000, 0.0039407000, 0.0039394000, 0.0039364000, 0.0039295000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003952300, -0.003944300, -0.003926000, -0.003925800, -0.003925200, -0.003923800, -0.003920700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024320000; - } - pin ("D") { - capacitance : 0.0022960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039969000, 0.0039955000, 0.0039921000, 0.0039934000, 0.0039965000, 0.0040036000, 0.0040198000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003991900, -0.003990900, -0.003988700, -0.003988700, -0.003988900, -0.003989300, -0.003990300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024050000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0044931000, 0.0033307000, 0.0003368000, -0.007284900, -0.026542600, -0.074869600, -0.196158400", \ - "0.0042524000, 0.0031278000, 0.0001873000, -0.007379500, -0.026592100, -0.074896000, -0.196173300", \ - "0.0039313000, 0.0028089000, -5.82000e-05, -0.007555800, -0.026696100, -0.074955600, -0.196169200", \ - "0.0037380000, 0.0025652000, -0.000341000, -0.007816600, -0.026852800, -0.075041000, -0.196244500", \ - "0.0036801000, 0.0024784000, -0.000512100, -0.008039600, -0.027103400, -0.075224600, -0.196375900", \ - "0.0044436000, 0.0032189000, -0.000127400, -0.007973200, -0.027065500, -0.075276400, -0.196436400", \ - "0.0061365000, 0.0047498000, 0.0011867000, -0.006786200, -0.026448300, -0.074419600, -0.196139600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0050914000, 0.0064189000, 0.0096166000, 0.0174334000, 0.0365496000, 0.0845929000, 0.2044707000", \ - "0.0048687000, 0.0062209000, 0.0094565000, 0.0172646000, 0.0365236000, 0.0847470000, 0.2044552000", \ - "0.0045714000, 0.0059181000, 0.0092092000, 0.0170198000, 0.0364446000, 0.0843759000, 0.2044911000", \ - "0.0044484000, 0.0057295000, 0.0088312000, 0.0166636000, 0.0361225000, 0.0844192000, 0.2030362000", \ - "0.0046098000, 0.0058325000, 0.0088549000, 0.0165468000, 0.0358141000, 0.0840601000, 0.2046447000", \ - "0.0049218000, 0.0060613000, 0.0090597000, 0.0168556000, 0.0356846000, 0.0837418000, 0.2040224000", \ - "0.0066547000, 0.0077023000, 0.0105464000, 0.0177055000, 0.0365959000, 0.0846656000, 0.2043267000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0050485000, 0.0038549000, 0.0008386000, -0.006802300, -0.026051000, -0.074397000, -0.195666600", \ - "0.0048740000, 0.0036990000, 0.0007346000, -0.006869400, -0.026094000, -0.074417400, -0.195701600", \ - "0.0045960000, 0.0034456000, 0.0005160000, -0.007007600, -0.026164200, -0.074447600, -0.195769900", \ - "0.0043173000, 0.0031599000, 0.0002390000, -0.007250200, -0.026305600, -0.074513000, -0.195748400", \ - "0.0041604000, 0.0029799000, 8.250000e-05, -0.007450800, -0.026484300, -0.074654800, -0.195806200", \ - "0.0043632000, 0.0031343000, 0.0001038000, -0.007632100, -0.026713700, -0.074842800, -0.195924900", \ - "0.0052782000, 0.0039857000, 0.0007600000, -0.007075700, -0.026533800, -0.074886400, -0.196019900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0081044000, 0.0093520000, 0.0124578000, 0.0201021000, 0.0392260000, 0.0869932000, 0.2062748000", \ - "0.0078956000, 0.0091677000, 0.0123154000, 0.0200203000, 0.0391672000, 0.0870221000, 0.2064994000", \ - "0.0075861000, 0.0088636000, 0.0119741000, 0.0198162000, 0.0389753000, 0.0866893000, 0.2065727000", \ - "0.0073548000, 0.0086412000, 0.0117409000, 0.0194902000, 0.0387250000, 0.0866097000, 0.2062140000", \ - "0.0074148000, 0.0086311000, 0.0117374000, 0.0192935000, 0.0385962000, 0.0866585000, 0.2054902000", \ - "0.0075090000, 0.0086500000, 0.0118409000, 0.0195726000, 0.0386675000, 0.0864862000, 0.2061132000", \ - "0.0087325000, 0.0098444000, 0.0127355000, 0.0199901000, 0.0390349000, 0.0865272000, 0.2052203000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0048227000, 0.0036439000, 0.0006186000, -0.007031000, -0.026296400, -0.074638900, -0.195938000", \ - "0.0046623000, 0.0035003000, 0.0005045000, -0.007105000, -0.026338100, -0.074662200, -0.195954100", \ - "0.0044043000, 0.0032439000, 0.0003043000, -0.007247800, -0.026407000, -0.074701700, -0.195955400", \ - "0.0041440000, 0.0029814000, 3.410000e-05, -0.007462100, -0.026555600, -0.074778800, -0.196039700", \ - "0.0039614000, 0.0027834000, -0.000135200, -0.007656800, -0.026706900, -0.074860200, -0.196049100", \ - "0.0040903000, 0.0028868000, -0.000144300, -0.007861000, -0.026967400, -0.075089200, -0.196174600", \ - "0.0048049000, 0.0035198000, 0.0003386000, -0.007438000, -0.026771200, -0.075149000, -0.196271200"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0110372000, 0.0122786000, 0.0153659000, 0.0230682000, 0.0421384000, 0.0899933000, 0.2095745000", \ - "0.0108177000, 0.0120572000, 0.0151667000, 0.0229017000, 0.0420479000, 0.0897690000, 0.2095444000", \ - "0.0105678000, 0.0118223000, 0.0149577000, 0.0226799000, 0.0418427000, 0.0897451000, 0.2092999000", \ - "0.0103761000, 0.0116129000, 0.0147212000, 0.0224770000, 0.0417048000, 0.0894831000, 0.2088775000", \ - "0.0103270000, 0.0115655000, 0.0146569000, 0.0222997000, 0.0411957000, 0.0890957000, 0.2085959000", \ - "0.0108968000, 0.0121396000, 0.0152379000, 0.0229020000, 0.0417348000, 0.0896547000, 0.2093423000", \ - "0.0121747000, 0.0133166000, 0.0162652000, 0.0235684000, 0.0424386000, 0.0899502000, 0.2084827000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0047066000, 0.0035046000, 0.0004830000, -0.007161800, -0.026409400, -0.074761600, -0.196062500", \ - "0.0045269000, 0.0033669000, 0.0003785000, -0.007228100, -0.026451400, -0.074782600, -0.196068100", \ - "0.0042924000, 0.0031355000, 0.0001720000, -0.007360000, -0.026522700, -0.074813700, -0.196083200", \ - "0.0040540000, 0.0028749000, -7.88000e-05, -0.007575100, -0.026655200, -0.074878300, -0.196095800", \ - "0.0038810000, 0.0026990000, -0.000224700, -0.007784100, -0.026837200, -0.074981200, -0.196185800", \ - "0.0040056000, 0.0027954000, -0.000229900, -0.007961600, -0.027064600, -0.075195600, -0.196299400", \ - "0.0047189000, 0.0034374000, 0.0002717000, -0.007519600, -0.026839400, -0.075239200, -0.196381000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0131846000, 0.0144174000, 0.0174988000, 0.0252033000, 0.0444784000, 0.0923580000, 0.2120264000", \ - "0.0130436000, 0.0142828000, 0.0173677000, 0.0251072000, 0.0444058000, 0.0921773000, 0.2119485000", \ - "0.0128815000, 0.0141155000, 0.0172245000, 0.0249813000, 0.0441903000, 0.0921006000, 0.2119081000", \ - "0.0126927000, 0.0139122000, 0.0170260000, 0.0248739000, 0.0441763000, 0.0921807000, 0.2118205000", \ - "0.0127113000, 0.0139749000, 0.0170439000, 0.0247843000, 0.0438500000, 0.0916433000, 0.2109098000", \ - "0.0132098000, 0.0144473000, 0.0175018000, 0.0250824000, 0.0440186000, 0.0916648000, 0.2105694000", \ - "0.0152802000, 0.0164377000, 0.0192977000, 0.0266187000, 0.0462404000, 0.0921753000, 0.2121036000"); - } - } - max_capacitance : 0.1245220000; - max_transition : 1.4955400000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0376158000, 0.0443032000, 0.0608772000, 0.1019825000, 0.2036166000, 0.4553360000, 1.0882606000", \ - "0.0405108000, 0.0474240000, 0.0640716000, 0.1048114000, 0.2078877000, 0.4603052000, 1.0922253000", \ - "0.0489402000, 0.0555174000, 0.0724115000, 0.1139417000, 0.2150740000, 0.4677938000, 1.1005228000", \ - "0.0661707000, 0.0750106000, 0.0940285000, 0.1341086000, 0.2356575000, 0.4888838000, 1.1216398000", \ - "0.0859427000, 0.0989831000, 0.1270206000, 0.1827956000, 0.2866150000, 0.5395698000, 1.1729341000", \ - "0.1011085000, 0.1201085000, 0.1619268000, 0.2443916000, 0.3895047000, 0.6553940000, 1.2885455000", \ - "0.0945083000, 0.1227385000, 0.1836422000, 0.3053895000, 0.5262458000, 0.8985496000, 1.5553173000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0333140000, 0.0387839000, 0.0520902000, 0.0843289000, 0.1640568000, 0.3662832000, 0.8627147000", \ - "0.0384392000, 0.0439535000, 0.0572193000, 0.0900474000, 0.1700749000, 0.3714378000, 0.8686598000", \ - "0.0515028000, 0.0569320000, 0.0702385000, 0.1028845000, 0.1831833000, 0.3827992000, 0.8814081000", \ - "0.0784353000, 0.0859189000, 0.1013946000, 0.1340957000, 0.2149728000, 0.4167127000, 0.9109572000", \ - "0.1205921000, 0.1324863000, 0.1576456000, 0.2047007000, 0.2872414000, 0.4866841000, 0.9849710000", \ - "0.1870239000, 0.2063293000, 0.2462639000, 0.3213755000, 0.4487207000, 0.6538889000, 1.1478276000", \ - "0.2968650000, 0.3256883000, 0.3874530000, 0.5054032000, 0.7102338000, 1.0340715000, 1.5469769000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0393056000, 0.0480962000, 0.0696740000, 0.1242628000, 0.2591227000, 0.5984760000, 1.4445395000", \ - "0.0388637000, 0.0478133000, 0.0696481000, 0.1234385000, 0.2595719000, 0.5976856000, 1.4448581000", \ - "0.0395252000, 0.0476852000, 0.0689772000, 0.1238772000, 0.2581751000, 0.5961422000, 1.4463429000", \ - "0.0510706000, 0.0589585000, 0.0767586000, 0.1251037000, 0.2594624000, 0.5963321000, 1.4446636000", \ - "0.0755253000, 0.0849430000, 0.1067977000, 0.1530195000, 0.2662068000, 0.5961008000, 1.4454326000", \ - "0.1199470000, 0.1338575000, 0.1631971000, 0.2222271000, 0.3380702000, 0.6190602000, 1.4444684000", \ - "0.1955844000, 0.2155240000, 0.2608865000, 0.3495551000, 0.4990950000, 0.7920194000, 1.4955402000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0288817000, 0.0361371000, 0.0539329000, 0.0995640000, 0.2131328000, 0.5019487000, 1.2094932000", \ - "0.0289285000, 0.0361677000, 0.0539604000, 0.0994459000, 0.2126731000, 0.5011725000, 1.2091524000", \ - "0.0303103000, 0.0367483000, 0.0541012000, 0.0994389000, 0.2122825000, 0.4977495000, 1.2053046000", \ - "0.0454420000, 0.0498768000, 0.0628528000, 0.1010196000, 0.2127708000, 0.5008317000, 1.2057988000", \ - "0.0758272000, 0.0827261000, 0.0985694000, 0.1306269000, 0.2205417000, 0.4966896000, 1.2146678000", \ - "0.1247311000, 0.1373566000, 0.1624555000, 0.2087877000, 0.2911202000, 0.5165225000, 1.2131496000", \ - "0.2057549000, 0.2253868000, 0.2664119000, 0.3446214000, 0.4710232000, 0.6823883000, 1.2537056000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0492486000, 0.0556947000, 0.0721029000, 0.1124600000, 0.2133689000, 0.4658435000, 1.0985823000", \ - "0.0525319000, 0.0592739000, 0.0759328000, 0.1169083000, 0.2194322000, 0.4696028000, 1.1022905000", \ - "0.0600724000, 0.0670542000, 0.0837898000, 0.1246836000, 0.2259222000, 0.4785761000, 1.1112681000", \ - "0.0756360000, 0.0837089000, 0.1024871000, 0.1441444000, 0.2463743000, 0.5016575000, 1.1343128000", \ - "0.0965616000, 0.1082665000, 0.1342288000, 0.1860034000, 0.2929004000, 0.5472066000, 1.1829406000", \ - "0.1116606000, 0.1299020000, 0.1692411000, 0.2460282000, 0.3873788000, 0.6555121000, 1.2912120000", \ - "0.0966787000, 0.1249287000, 0.1857919000, 0.3040858000, 0.5141874000, 0.8749002000, 1.5431553000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0459891000, 0.0518668000, 0.0659862000, 0.1008781000, 0.1873523000, 0.4033550000, 0.9442862000", \ - "0.0512036000, 0.0571382000, 0.0714784000, 0.1066306000, 0.1931022000, 0.4092852000, 0.9500808000", \ - "0.0641732000, 0.0700596000, 0.0841501000, 0.1194418000, 0.2064787000, 0.4224298000, 0.9632733000", \ - "0.0956015000, 0.1021066000, 0.1161071000, 0.1515309000, 0.2385687000, 0.4519742000, 0.9928998000", \ - "0.1505331000, 0.1606804000, 0.1824967000, 0.2253501000, 0.3125189000, 0.5280172000, 1.0685798000", \ - "0.2397997000, 0.2559083000, 0.2914941000, 0.3606570000, 0.4825333000, 0.7023909000, 1.2414967000", \ - "0.3871819000, 0.4121302000, 0.4680744000, 0.5787332000, 0.7754237000, 1.0948000000, 1.6454278000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0397169000, 0.0481506000, 0.0696721000, 0.1234327000, 0.2583977000, 0.5965825000, 1.4433171000", \ - "0.0397221000, 0.0482640000, 0.0698510000, 0.1236889000, 0.2597507000, 0.5983884000, 1.4495731000", \ - "0.0401739000, 0.0485112000, 0.0698188000, 0.1237364000, 0.2595404000, 0.5955462000, 1.4432427000", \ - "0.0488937000, 0.0559749000, 0.0746977000, 0.1251496000, 0.2586629000, 0.6018031000, 1.4497015000", \ - "0.0699887000, 0.0782854000, 0.0984257000, 0.1442579000, 0.2656053000, 0.5972184000, 1.4475923000", \ - "0.1137321000, 0.1246564000, 0.1497648000, 0.2023183000, 0.3175695000, 0.6118787000, 1.4453873000", \ - "0.1910932000, 0.2071285000, 0.2418882000, 0.3138542000, 0.4526244000, 0.7388448000, 1.4774649000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0389247000, 0.0466661000, 0.0659881000, 0.1144805000, 0.2360458000, 0.5404594000, 1.3069545000", \ - "0.0389056000, 0.0467079000, 0.0659264000, 0.1144309000, 0.2361649000, 0.5406595000, 1.3037768000", \ - "0.0388813000, 0.0466683000, 0.0660062000, 0.1146094000, 0.2369004000, 0.5422998000, 1.3050222000", \ - "0.0483564000, 0.0542518000, 0.0708068000, 0.1150402000, 0.2364180000, 0.5409098000, 1.3055701000", \ - "0.0800841000, 0.0872626000, 0.1029244000, 0.1372848000, 0.2402638000, 0.5413683000, 1.3104512000", \ - "0.1322598000, 0.1446138000, 0.1690449000, 0.2150913000, 0.3006310000, 0.5555174000, 1.3060715000", \ - "0.2187250000, 0.2382566000, 0.2778830000, 0.3551758000, 0.4816681000, 0.6929442000, 1.3334612000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0550275000, 0.0617658000, 0.0781572000, 0.1190589000, 0.2204551000, 0.4733738000, 1.1052764000", \ - "0.0586787000, 0.0654099000, 0.0820153000, 0.1223316000, 0.2252762000, 0.4761069000, 1.1081468000", \ - "0.0660437000, 0.0728834000, 0.0894846000, 0.1303443000, 0.2315510000, 0.4841769000, 1.1169592000", \ - "0.0802389000, 0.0877845000, 0.1056712000, 0.1470350000, 0.2487032000, 0.5015581000, 1.1453397000", \ - "0.1005832000, 0.1108030000, 0.1334339000, 0.1821437000, 0.2873042000, 0.5410644000, 1.1745228000", \ - "0.1169543000, 0.1327903000, 0.1672495000, 0.2351042000, 0.3641872000, 0.6319419000, 1.2664254000", \ - "0.1011846000, 0.1261893000, 0.1811456000, 0.2877029000, 0.4768112000, 0.8079625000, 1.4771147000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0524538000, 0.0583115000, 0.0725801000, 0.1078404000, 0.1946118000, 0.4101385000, 0.9495322000", \ - "0.0575020000, 0.0635243000, 0.0778849000, 0.1132422000, 0.2000141000, 0.4160076000, 0.9552010000", \ - "0.0705305000, 0.0764009000, 0.0909325000, 0.1262912000, 0.2133517000, 0.4287310000, 0.9686417000", \ - "0.1029369000, 0.1086119000, 0.1232411000, 0.1583575000, 0.2454497000, 0.4585791000, 0.9981589000", \ - "0.1638223000, 0.1728502000, 0.1930364000, 0.2335978000, 0.3179934000, 0.5330079000, 1.0716569000", \ - "0.2633456000, 0.2778212000, 0.3100832000, 0.3742420000, 0.4897060000, 0.7078755000, 1.2437928000", \ - "0.4255436000, 0.4481359000, 0.4976986000, 0.6016890000, 0.7913159000, 1.1017695000, 1.6492826000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0395984000, 0.0483459000, 0.0697578000, 0.1243540000, 0.2589861000, 0.5981931000, 1.4453220000", \ - "0.0397231000, 0.0483446000, 0.0699921000, 0.1234686000, 0.2596158000, 0.5967926000, 1.4486393000", \ - "0.0399238000, 0.0484537000, 0.0700384000, 0.1238071000, 0.2582911000, 0.5964511000, 1.4419568000", \ - "0.0460645000, 0.0537433000, 0.0731802000, 0.1247707000, 0.2585907000, 0.5959679000, 1.4507172000", \ - "0.0632175000, 0.0714103000, 0.0909735000, 0.1390684000, 0.2633314000, 0.5961899000, 1.4425272000", \ - "0.1034705000, 0.1132770000, 0.1355308000, 0.1855687000, 0.3027786000, 0.6097723000, 1.4437158000", \ - "0.1818065000, 0.1947429000, 0.2248745000, 0.2889468000, 0.4161527000, 0.7046699000, 1.4790486000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0463519000, 0.0541380000, 0.0734231000, 0.1218621000, 0.2439030000, 0.5474405000, 1.3089411000", \ - "0.0463596000, 0.0540515000, 0.0733770000, 0.1220056000, 0.2428325000, 0.5477644000, 1.3098427000", \ - "0.0461408000, 0.0538811000, 0.0734416000, 0.1217507000, 0.2433721000, 0.5475154000, 1.3116622000", \ - "0.0526094000, 0.0592524000, 0.0759375000, 0.1218479000, 0.2433594000, 0.5482865000, 1.3141029000", \ - "0.0829507000, 0.0902356000, 0.1051001000, 0.1400336000, 0.2471433000, 0.5475788000, 1.3109447000", \ - "0.1372848000, 0.1486620000, 0.1723741000, 0.2180959000, 0.3042809000, 0.5603280000, 1.3112733000", \ - "0.2253429000, 0.2436135000, 0.2823692000, 0.3571377000, 0.4832982000, 0.6955326000, 1.3376370000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0586162000, 0.0652303000, 0.0816343000, 0.1220263000, 0.2229160000, 0.4758324000, 1.1087713000", \ - "0.0622769000, 0.0690709000, 0.0856553000, 0.1260464000, 0.2269186000, 0.4798923000, 1.1137050000", \ - "0.0698582000, 0.0765723000, 0.0932197000, 0.1341453000, 0.2363503000, 0.4879500000, 1.1219942000", \ - "0.0841582000, 0.0914310000, 0.1086477000, 0.1499243000, 0.2531856000, 0.5044969000, 1.1377432000", \ - "0.1053215000, 0.1141715000, 0.1346551000, 0.1808117000, 0.2848373000, 0.5381752000, 1.1723217000", \ - "0.1267640000, 0.1404201000, 0.1695462000, 0.2294117000, 0.3515965000, 0.6144009000, 1.2515881000", \ - "0.1241974000, 0.1448544000, 0.1924863000, 0.2849458000, 0.4526263000, 0.7681035000, 1.4257986000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0505282000, 0.0560131000, 0.0693182000, 0.1011975000, 0.1791862000, 0.3710053000, 0.8496482000", \ - "0.0558933000, 0.0613653000, 0.0746765000, 0.1067251000, 0.1844575000, 0.3774465000, 0.8555400000", \ - "0.0693295000, 0.0748718000, 0.0881800000, 0.1199806000, 0.1978687000, 0.3899928000, 0.8674135000", \ - "0.1015580000, 0.1069126000, 0.1199653000, 0.1518307000, 0.2296206000, 0.4215322000, 0.8989517000", \ - "0.1615419000, 0.1699851000, 0.1883433000, 0.2247804000, 0.3016451000, 0.4927593000, 0.9701073000", \ - "0.2574858000, 0.2704071000, 0.2995370000, 0.3593382000, 0.4676873000, 0.6655385000, 1.1348902000", \ - "0.4102999000, 0.4301036000, 0.4753817000, 0.5694828000, 0.7453104000, 1.0392119000, 1.5334389000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0397234000, 0.0482797000, 0.0698100000, 0.1238679000, 0.2593124000, 0.5985906000, 1.4450195000", \ - "0.0396343000, 0.0483022000, 0.0698295000, 0.1236290000, 0.2580337000, 0.5969225000, 1.4459374000", \ - "0.0398084000, 0.0483490000, 0.0699097000, 0.1234663000, 0.2588924000, 0.5967773000, 1.4430033000", \ - "0.0435828000, 0.0513691000, 0.0715639000, 0.1244259000, 0.2601832000, 0.5973042000, 1.4438515000", \ - "0.0561428000, 0.0643137000, 0.0846759000, 0.1343543000, 0.2621714000, 0.5973164000, 1.4434682000", \ - "0.0897072000, 0.0987139000, 0.1195541000, 0.1696196000, 0.2930544000, 0.6076473000, 1.4466403000", \ - "0.1625361000, 0.1737476000, 0.1997691000, 0.2564819000, 0.3822337000, 0.6878326000, 1.4733832000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0479623000, 0.0550360000, 0.0722188000, 0.1152642000, 0.2236467000, 0.4943612000, 1.1741644000", \ - "0.0479350000, 0.0548859000, 0.0723047000, 0.1155621000, 0.2237779000, 0.4957095000, 1.1747043000", \ - "0.0472621000, 0.0543430000, 0.0719787000, 0.1153214000, 0.2236046000, 0.4952181000, 1.1741804000", \ - "0.0534581000, 0.0593867000, 0.0748940000, 0.1155690000, 0.2236775000, 0.4947780000, 1.1783978000", \ - "0.0837695000, 0.0900061000, 0.1040344000, 0.1370896000, 0.2296195000, 0.4953692000, 1.1760050000", \ - "0.1377132000, 0.1477985000, 0.1697714000, 0.2130449000, 0.2920052000, 0.5129832000, 1.1759866000", \ - "0.2259437000, 0.2430334000, 0.2799759000, 0.3508111000, 0.4711437000, 0.6676097000, 1.2192818000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4_2") { - leakage_power () { - value : 0.0010585000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0099957000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0010781000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0010614000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 7.7395257e-05; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0100941000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0008277000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 7.9341868e-05; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 8.7701913e-05; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0201798000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0006145000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0002807000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0006039000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0299277000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0068021000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0005982000; - when : "A&B&C&!D"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__nand4"; - cell_leakage_power : 0.0052104240; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0042940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091602000, 0.0091623000, 0.0091672000, 0.0091684000, 0.0091713000, 0.0091779000, 0.0091931000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006165000, -0.006165500, -0.006166600, -0.006147800, -0.006104600, -0.006005000, -0.005775300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043670000; - } - pin ("B") { - capacitance : 0.0043790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086550000, 0.0086519000, 0.0086447000, 0.0086788000, 0.0087574000, 0.0089385000, 0.0093559000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008059100, -0.008057200, -0.008052600, -0.008049200, -0.008041400, -0.008023400, -0.007981800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044840000; - } - pin ("C") { - capacitance : 0.0043170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078261000, 0.0078263000, 0.0078268000, 0.0078280000, 0.0078306000, 0.0078366000, 0.0078505000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007841800, -0.007833700, -0.007815000, -0.007812900, -0.007808200, -0.007797100, -0.007771500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044840000; - } - pin ("D") { - capacitance : 0.0044380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078787000, 0.0078745000, 0.0078648000, 0.0078662000, 0.0078694000, 0.0078768000, 0.0078937000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007863000, -0.007864400, -0.007867500, -0.007867400, -0.007867300, -0.007866800, -0.007865600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046590000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0085530000, 0.0072425000, 0.0035841000, -0.006520700, -0.034248300, -0.109764300, -0.314949800", \ - "0.0081480000, 0.0068601000, 0.0032717000, -0.006691500, -0.034342200, -0.109802600, -0.314968600", \ - "0.0076512000, 0.0064037000, 0.0028142000, -0.007040200, -0.034500200, -0.109900400, -0.314995600", \ - "0.0072239000, 0.0059242000, 0.0023610000, -0.007539900, -0.034874500, -0.110050300, -0.315084900", \ - "0.0071232000, 0.0057606000, 0.0020690000, -0.007907100, -0.035247600, -0.110340600, -0.315247900", \ - "0.0081849000, 0.0066920000, 0.0028111000, -0.007601000, -0.035467900, -0.110756400, -0.315538500", \ - "0.0106327000, 0.0091261000, 0.0049772000, -0.005921900, -0.034463500, -0.110611200, -0.315782500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0073373000, 0.0088769000, 0.0129110000, 0.0233442000, 0.0513245000, 0.1251966000, 0.3289749000", \ - "0.0069634000, 0.0085050000, 0.0125909000, 0.0231660000, 0.0513348000, 0.1253225000, 0.3308996000", \ - "0.0065828000, 0.0081163000, 0.0121305000, 0.0227785000, 0.0511266000, 0.1265899000, 0.3292714000", \ - "0.0062095000, 0.0076729000, 0.0117808000, 0.0222119000, 0.0504574000, 0.1258162000, 0.3302184000", \ - "0.0063315000, 0.0077057000, 0.0115019000, 0.0217597000, 0.0495795000, 0.1243904000, 0.3296111000", \ - "0.0067103000, 0.0080181000, 0.0116326000, 0.0222924000, 0.0496433000, 0.1241519000, 0.3273418000", \ - "0.0107555000, 0.0119833000, 0.0156987000, 0.0260185000, 0.0509267000, 0.1247612000, 0.3263663000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0108476000, 0.0094965000, 0.0058415000, -0.004313000, -0.032090700, -0.107627400, -0.312817200", \ - "0.0104853000, 0.0091765000, 0.0055641000, -0.004473800, -0.032158800, -0.107654700, -0.312823100", \ - "0.0100358000, 0.0087253000, 0.0051435000, -0.004789600, -0.032325300, -0.107728900, -0.312828200", \ - "0.0095329000, 0.0082274000, 0.0046318000, -0.005260100, -0.032652700, -0.107873200, -0.312907300", \ - "0.0093270000, 0.0079802000, 0.0043441000, -0.005656200, -0.033023000, -0.108099700, -0.312989200", \ - "0.0094293000, 0.0080282000, 0.0041399000, -0.006020100, -0.033536400, -0.108586900, -0.313271400", \ - "0.0105589000, 0.0090920000, 0.0051633000, -0.005264900, -0.033258700, -0.108819700, -0.313601000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0149977000, 0.0164023000, 0.0202602000, 0.0305507000, 0.0581091000, 0.1327664000, 0.3350718000", \ - "0.0145544000, 0.0160633000, 0.0199291000, 0.0303205000, 0.0580841000, 0.1327028000, 0.3356209000", \ - "0.0140393000, 0.0154950000, 0.0194693000, 0.0300315000, 0.0578712000, 0.1328885000, 0.3353403000", \ - "0.0134758000, 0.0149653000, 0.0187970000, 0.0292695000, 0.0572990000, 0.1323171000, 0.3347016000", \ - "0.0131879000, 0.0146167000, 0.0184973000, 0.0288818000, 0.0568072000, 0.1314886000, 0.3349408000", \ - "0.0131015000, 0.0145066000, 0.0184571000, 0.0288504000, 0.0565392000, 0.1313199000, 0.3342752000", \ - "0.0162516000, 0.0163812000, 0.0198972000, 0.0316875000, 0.0568924000, 0.1311195000, 0.3326460000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0106636000, 0.0093461000, 0.0056172000, -0.004532600, -0.032296200, -0.107840500, -0.313027600", \ - "0.0103300000, 0.0090389000, 0.0053801000, -0.004664900, -0.032338100, -0.107862200, -0.312980900", \ - "0.0098646000, 0.0085487000, 0.0049694000, -0.004993000, -0.032542200, -0.107944800, -0.313121200", \ - "0.0093876000, 0.0080607000, 0.0044443000, -0.005445900, -0.032845700, -0.108096000, -0.313170900", \ - "0.0091253000, 0.0078071000, 0.0041637000, -0.005806600, -0.033219900, -0.108301500, -0.313215200", \ - "0.0091747000, 0.0078009000, 0.0041013000, -0.006231400, -0.033732800, -0.108783900, -0.313538600", \ - "0.0099593000, 0.0086133000, 0.0047043000, -0.005627300, -0.033493400, -0.109019000, -0.313835900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0205977000, 0.0220174000, 0.0258136000, 0.0361523000, 0.0638073000, 0.1388472000, 0.3409526000", \ - "0.0202780000, 0.0217149000, 0.0255528000, 0.0359111000, 0.0636803000, 0.1383968000, 0.3411157000", \ - "0.0197807000, 0.0212213000, 0.0250588000, 0.0355439000, 0.0634257000, 0.1384102000, 0.3410154000", \ - "0.0193508000, 0.0207789000, 0.0246344000, 0.0351079000, 0.0630957000, 0.1380139000, 0.3412877000", \ - "0.0193098000, 0.0207225000, 0.0245504000, 0.0348922000, 0.0628882000, 0.1371439000, 0.3408287000", \ - "0.0199518000, 0.0213135000, 0.0250153000, 0.0351447000, 0.0627993000, 0.1372474000, 0.3404056000", \ - "0.0219198000, 0.0232204000, 0.0267600000, 0.0365226000, 0.0641555000, 0.1379914000, 0.3394645000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0105190000, 0.0091976000, 0.0054733000, -0.004677400, -0.032437300, -0.107971600, -0.313154600", \ - "0.0101768000, 0.0088569000, 0.0052180000, -0.004834900, -0.032498100, -0.108002400, -0.313197200", \ - "0.0097187000, 0.0083998000, 0.0048217000, -0.005129800, -0.032678200, -0.108075300, -0.313207600", \ - "0.0092545000, 0.0079216000, 0.0043175000, -0.005585200, -0.032987900, -0.108226200, -0.313264600", \ - "0.0090860000, 0.0077155000, 0.0040779000, -0.005953600, -0.033353900, -0.108466300, -0.313329100", \ - "0.0091162000, 0.0077291000, 0.0040037000, -0.006322900, -0.033839200, -0.108949500, -0.313690500", \ - "0.0100308000, 0.0085802000, 0.0047330000, -0.005636000, -0.033474300, -0.109066800, -0.313905100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0260840000, 0.0274754000, 0.0312623000, 0.0416018000, 0.0695573000, 0.1445181000, 0.3473231000", \ - "0.0257787000, 0.0271264000, 0.0309294000, 0.0412988000, 0.0693169000, 0.1442883000, 0.3469877000", \ - "0.0253378000, 0.0267551000, 0.0305855000, 0.0409854000, 0.0689407000, 0.1441473000, 0.3469367000", \ - "0.0248924000, 0.0262923000, 0.0300969000, 0.0406261000, 0.0687179000, 0.1439690000, 0.3467344000", \ - "0.0248058000, 0.0262156000, 0.0300852000, 0.0404023000, 0.0687030000, 0.1428729000, 0.3451199000", \ - "0.0268214000, 0.0278746000, 0.0307284000, 0.0407534000, 0.0689948000, 0.1440895000, 0.3465110000", \ - "0.0287527000, 0.0300636000, 0.0336789000, 0.0433596000, 0.0707276000, 0.1451940000, 0.3457913000"); - } - } - max_capacitance : 0.2005100000; - max_transition : 1.4964450000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0366782000, 0.0412760000, 0.0537110000, 0.0866774000, 0.1751574000, 0.4144290000, 1.0633583000", \ - "0.0394225000, 0.0440703000, 0.0566713000, 0.0903481000, 0.1786850000, 0.4182443000, 1.0672749000", \ - "0.0481018000, 0.0524234000, 0.0645812000, 0.0981597000, 0.1871719000, 0.4272707000, 1.0767099000", \ - "0.0651100000, 0.0710510000, 0.0856196000, 0.1181946000, 0.2077714000, 0.4481660000, 1.0975219000", \ - "0.0834543000, 0.0923982000, 0.1142344000, 0.1615262000, 0.2559058000, 0.4960755000, 1.1461130000", \ - "0.0946543000, 0.1072628000, 0.1400645000, 0.2112962000, 0.3515067000, 0.6132501000, 1.2619270000", \ - "0.0757197000, 0.0954567000, 0.1435045000, 0.2495453000, 0.4598073000, 0.8371093000, 1.5319632000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0317665000, 0.0352914000, 0.0443316000, 0.0679715000, 0.1306637000, 0.3005094000, 0.7583619000", \ - "0.0370821000, 0.0404796000, 0.0497513000, 0.0734966000, 0.1365867000, 0.3059243000, 0.7642629000", \ - "0.0505602000, 0.0539438000, 0.0629881000, 0.0871303000, 0.1506850000, 0.3192173000, 0.7799161000", \ - "0.0775400000, 0.0825512000, 0.0945140000, 0.1183177000, 0.1816342000, 0.3513182000, 0.8138189000", \ - "0.1206598000, 0.1286415000, 0.1473462000, 0.1861400000, 0.2573938000, 0.4267686000, 0.8904164000", \ - "0.1901118000, 0.2029517000, 0.2336055000, 0.2969490000, 0.4093730000, 0.6009269000, 1.0542153000", \ - "0.3106276000, 0.3295035000, 0.3759633000, 0.4743197000, 0.6587836000, 0.9619255000, 1.4618328000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0429532000, 0.0491339000, 0.0661347000, 0.1116034000, 0.2312898000, 0.5574955000, 1.4425207000", \ - "0.0421144000, 0.0485594000, 0.0657901000, 0.1111716000, 0.2314579000, 0.5575140000, 1.4429763000", \ - "0.0423072000, 0.0483011000, 0.0646034000, 0.1105475000, 0.2312808000, 0.5574329000, 1.4430580000", \ - "0.0525964000, 0.0591953000, 0.0733235000, 0.1127013000, 0.2311306000, 0.5586993000, 1.4427132000", \ - "0.0754324000, 0.0822206000, 0.0998436000, 0.1415057000, 0.2428968000, 0.5581361000, 1.4436654000", \ - "0.1194462000, 0.1293919000, 0.1531542000, 0.2048581000, 0.3149463000, 0.5845833000, 1.4460027000", \ - "0.1945502000, 0.2094012000, 0.2435261000, 0.3191345000, 0.4708536000, 0.7554387000, 1.4964449000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0264735000, 0.0308362000, 0.0428600000, 0.0755694000, 0.1649060000, 0.4056626000, 1.0579534000", \ - "0.0263815000, 0.0309248000, 0.0428734000, 0.0754666000, 0.1647457000, 0.4044073000, 1.0652674000", \ - "0.0280672000, 0.0318855000, 0.0430121000, 0.0756165000, 0.1644186000, 0.4063691000, 1.0661618000", \ - "0.0429617000, 0.0458032000, 0.0537479000, 0.0797303000, 0.1645735000, 0.4053602000, 1.0633415000", \ - "0.0713585000, 0.0762157000, 0.0875991000, 0.1117204000, 0.1769853000, 0.4053828000, 1.0700733000", \ - "0.1192296000, 0.1271753000, 0.1456069000, 0.1842449000, 0.2551086000, 0.4324135000, 1.0594516000", \ - "0.1981238000, 0.2111374000, 0.2414885000, 0.3048228000, 0.4191621000, 0.6046418000, 1.1093976000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0545066000, 0.0591063000, 0.0717409000, 0.1047622000, 0.1928175000, 0.4320058000, 1.0811904000", \ - "0.0580063000, 0.0625719000, 0.0750924000, 0.1083496000, 0.1968844000, 0.4363585000, 1.0856557000", \ - "0.0658536000, 0.0704613000, 0.0832910000, 0.1167834000, 0.2058056000, 0.4459836000, 1.0977153000", \ - "0.0825312000, 0.0881322000, 0.1021869000, 0.1365164000, 0.2269525000, 0.4663328000, 1.1239902000", \ - "0.1056027000, 0.1135280000, 0.1333025000, 0.1766502000, 0.2730952000, 0.5148746000, 1.1702678000", \ - "0.1229615000, 0.1353399000, 0.1658351000, 0.2322358000, 0.3629301000, 0.6256723000, 1.2772852000", \ - "0.1065158000, 0.1260839000, 0.1738807000, 0.2780488000, 0.4787604000, 0.8373974000, 1.5353158000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0471125000, 0.0508341000, 0.0603569000, 0.0859784000, 0.1540763000, 0.3376577000, 0.8345794000", \ - "0.0521955000, 0.0561523000, 0.0657105000, 0.0915552000, 0.1598947000, 0.3437778000, 0.8403441000", \ - "0.0654646000, 0.0692507000, 0.0790056000, 0.1050264000, 0.1737537000, 0.3575886000, 0.8536471000", \ - "0.0973504000, 0.1014175000, 0.1110720000, 0.1371466000, 0.2056487000, 0.3874762000, 0.8849786000", \ - "0.1545861000, 0.1609918000, 0.1767465000, 0.2106450000, 0.2815190000, 0.4646323000, 0.9612862000", \ - "0.2483148000, 0.2585433000, 0.2837075000, 0.3391795000, 0.4461037000, 0.6417473000, 1.1375305000", \ - "0.4047358000, 0.4204081000, 0.4606291000, 0.5478082000, 0.7226669000, 1.0237046000, 1.5464038000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0440647000, 0.0499771000, 0.0667575000, 0.1114571000, 0.2311749000, 0.5583321000, 1.4422498000", \ - "0.0439922000, 0.0499766000, 0.0665161000, 0.1111107000, 0.2313162000, 0.5578393000, 1.4428441000", \ - "0.0441116000, 0.0501030000, 0.0665764000, 0.1110851000, 0.2316004000, 0.5577574000, 1.4470092000", \ - "0.0516781000, 0.0568100000, 0.0712597000, 0.1128913000, 0.2319216000, 0.5580406000, 1.4520523000", \ - "0.0722231000, 0.0782318000, 0.0942466000, 0.1329936000, 0.2386749000, 0.5585463000, 1.4458093000", \ - "0.1169619000, 0.1244351000, 0.1436798000, 0.1887260000, 0.2950397000, 0.5778475000, 1.4457131000", \ - "0.1983582000, 0.2090303000, 0.2363356000, 0.2984658000, 0.4295628000, 0.7088766000, 1.4822380000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0389948000, 0.0437027000, 0.0566624000, 0.0916064000, 0.1870752000, 0.4474287000, 1.1511981000", \ - "0.0391445000, 0.0437519000, 0.0566361000, 0.0916398000, 0.1870713000, 0.4465830000, 1.1470412000", \ - "0.0389036000, 0.0436870000, 0.0565796000, 0.0918775000, 0.1870881000, 0.4458153000, 1.1481938000", \ - "0.0472474000, 0.0509771000, 0.0615253000, 0.0928961000, 0.1871349000, 0.4458823000, 1.1520388000", \ - "0.0773657000, 0.0819011000, 0.0929842000, 0.1176618000, 0.1952134000, 0.4460406000, 1.1490559000", \ - "0.1295746000, 0.1370136000, 0.1546280000, 0.1920977000, 0.2632345000, 0.4656062000, 1.1484634000", \ - "0.2151169000, 0.2295362000, 0.2581614000, 0.3190590000, 0.4311387000, 0.6239766000, 1.1869591000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0625068000, 0.0673535000, 0.0794025000, 0.1122183000, 0.2007157000, 0.4401163000, 1.0892236000", \ - "0.0658927000, 0.0707974000, 0.0830510000, 0.1166104000, 0.2049658000, 0.4451196000, 1.0951519000", \ - "0.0729875000, 0.0779188000, 0.0905579000, 0.1238334000, 0.2127580000, 0.4535194000, 1.1032036000", \ - "0.0866100000, 0.0917703000, 0.1053821000, 0.1394620000, 0.2287828000, 0.4718548000, 1.1213304000", \ - "0.1069113000, 0.1139132000, 0.1302378000, 0.1701967000, 0.2640204000, 0.5072129000, 1.1551322000", \ - "0.1244450000, 0.1346920000, 0.1598133000, 0.2158674000, 0.3316669000, 0.5876895000, 1.2406443000", \ - "0.1070780000, 0.1235931000, 0.1640461000, 0.2528981000, 0.4250229000, 0.7492872000, 1.4335810000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0543250000, 0.0579306000, 0.0678549000, 0.0935668000, 0.1618389000, 0.3444326000, 0.8378334000", \ - "0.0596924000, 0.0633345000, 0.0733358000, 0.0991498000, 0.1676296000, 0.3504845000, 0.8428565000", \ - "0.0727626000, 0.0765411000, 0.0864096000, 0.1124466000, 0.1809766000, 0.3635938000, 0.8572557000", \ - "0.1053567000, 0.1089521000, 0.1190149000, 0.1450249000, 0.2134818000, 0.3961781000, 0.8871262000", \ - "0.1690990000, 0.1747340000, 0.1888305000, 0.2206266000, 0.2895498000, 0.4713653000, 0.9640799000", \ - "0.2733681000, 0.2820401000, 0.3042880000, 0.3554797000, 0.4576577000, 0.6483575000, 1.1399778000", \ - "0.4477455000, 0.4616528000, 0.4965557000, 0.5764776000, 0.7409658000, 1.0325178000, 1.5477610000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0438913000, 0.0501664000, 0.0664038000, 0.1111375000, 0.2312125000, 0.5574914000, 1.4424363000", \ - "0.0438977000, 0.0502863000, 0.0664288000, 0.1114236000, 0.2318208000, 0.5590470000, 1.4471272000", \ - "0.0442206000, 0.0504381000, 0.0666957000, 0.1110178000, 0.2314578000, 0.5584543000, 1.4474727000", \ - "0.0493883000, 0.0545551000, 0.0697500000, 0.1126035000, 0.2314713000, 0.5595230000, 1.4456271000", \ - "0.0641837000, 0.0700697000, 0.0850520000, 0.1263195000, 0.2372839000, 0.5594025000, 1.4450524000", \ - "0.1025680000, 0.1092482000, 0.1260673000, 0.1678045000, 0.2760297000, 0.5708013000, 1.4444945000", \ - "0.1804095000, 0.1890407000, 0.2110638000, 0.2652236000, 0.3804597000, 0.6674796000, 1.4698333000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0477080000, 0.0526671000, 0.0652868000, 0.1001475000, 0.1945264000, 0.4522595000, 1.1518083000", \ - "0.0476381000, 0.0525402000, 0.0653339000, 0.1003518000, 0.1953738000, 0.4524423000, 1.1503543000", \ - "0.0473016000, 0.0521683000, 0.0650994000, 0.0999441000, 0.1951925000, 0.4528780000, 1.1499781000", \ - "0.0526971000, 0.0568746000, 0.0679702000, 0.1005133000, 0.1951801000, 0.4522064000, 1.1523740000", \ - "0.0818613000, 0.0861673000, 0.0964637000, 0.1219721000, 0.2015574000, 0.4531747000, 1.1514782000", \ - "0.1354280000, 0.1415347000, 0.1584889000, 0.1938920000, 0.2657315000, 0.4717239000, 1.1520697000", \ - "0.2247706000, 0.2361755000, 0.2640337000, 0.3233540000, 0.4326982000, 0.6239551000, 1.1930901000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0677319000, 0.0725549000, 0.0846400000, 0.1175427000, 0.2058110000, 0.4450028000, 1.0942857000", \ - "0.0713914000, 0.0761985000, 0.0885749000, 0.1217183000, 0.2107867000, 0.4509869000, 1.1003994000", \ - "0.0789329000, 0.0835925000, 0.0962844000, 0.1296138000, 0.2186189000, 0.4581734000, 1.1074044000", \ - "0.0925260000, 0.0976578000, 0.1105358000, 0.1443194000, 0.2337110000, 0.4738886000, 1.1233381000", \ - "0.1124282000, 0.1180973000, 0.1332906000, 0.1707610000, 0.2629291000, 0.5035450000, 1.1613500000", \ - "0.1316841000, 0.1400582000, 0.1608712000, 0.2089429000, 0.3165659000, 0.5686469000, 1.2204113000", \ - "0.1195598000, 0.1345224000, 0.1675050000, 0.2428085000, 0.3936891000, 0.6942958000, 1.3698656000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0538659000, 0.0574204000, 0.0669538000, 0.0910846000, 0.1539632000, 0.3194362000, 0.7643600000", \ - "0.0591924000, 0.0627918000, 0.0722833000, 0.0964694000, 0.1592660000, 0.3247327000, 0.7707776000", \ - "0.0725605000, 0.0761578000, 0.0857295000, 0.1096694000, 0.1724866000, 0.3379039000, 0.7829423000", \ - "0.1051539000, 0.1085510000, 0.1177597000, 0.1419749000, 0.2047956000, 0.3704029000, 0.8149882000", \ - "0.1693535000, 0.1740401000, 0.1866901000, 0.2163438000, 0.2787661000, 0.4425063000, 0.8859636000", \ - "0.2741531000, 0.2818386000, 0.3002063000, 0.3463768000, 0.4399685000, 0.6167616000, 1.0575747000", \ - "0.4433827000, 0.4554862000, 0.4842652000, 0.5570386000, 0.7075722000, 0.9825970000, 1.4613897000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0439051000, 0.0502622000, 0.0665362000, 0.1110282000, 0.2311544000, 0.5578156000, 1.4453064000", \ - "0.0439010000, 0.0500921000, 0.0664181000, 0.1110255000, 0.2317397000, 0.5590778000, 1.4444043000", \ - "0.0440255000, 0.0501839000, 0.0665197000, 0.1110061000, 0.2317344000, 0.5572462000, 1.4422731000", \ - "0.0469592000, 0.0525615000, 0.0682031000, 0.1117457000, 0.2313343000, 0.5573699000, 1.4426799000", \ - "0.0576042000, 0.0633993000, 0.0789588000, 0.1211828000, 0.2352818000, 0.5602021000, 1.4523192000", \ - "0.0878556000, 0.0938872000, 0.1095479000, 0.1514060000, 0.2636069000, 0.5692105000, 1.4463195000", \ - "0.1582841000, 0.1658709000, 0.1850316000, 0.2316429000, 0.3461606000, 0.6419663000, 1.4686848000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0524934000, 0.0568454000, 0.0685997000, 0.1001693000, 0.1860271000, 0.4195835000, 1.0524670000", \ - "0.0521330000, 0.0567152000, 0.0684781000, 0.1000899000, 0.1859883000, 0.4191110000, 1.0558344000", \ - "0.0511931000, 0.0558256000, 0.0680611000, 0.0999513000, 0.1860482000, 0.4203849000, 1.0528148000", \ - "0.0555736000, 0.0594691000, 0.0700527000, 0.1001010000, 0.1858474000, 0.4201668000, 1.0549365000", \ - "0.0840169000, 0.0882938000, 0.0979927000, 0.1220017000, 0.1938866000, 0.4190611000, 1.0540490000", \ - "0.1375057000, 0.1435853000, 0.1603460000, 0.1934745000, 0.2630137000, 0.4442398000, 1.0547636000", \ - "0.2261995000, 0.2368595000, 0.2613054000, 0.3172750000, 0.4254616000, 0.6129977000, 1.1091730000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4_4") { - leakage_power () { - value : 0.0167977000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0167972000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0001765000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0001012000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0001796000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0001051000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0019163000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0001843000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0001981000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0001091000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0014939000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0002020000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0014645000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0002237000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0105515000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0014670000; - when : "A&B&C&!D"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__nand4"; - cell_leakage_power : 0.0032479900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0084590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0182239000, 0.0182852000, 0.0184264000, 0.0184119000, 0.0183786000, 0.0183016000, 0.0181242000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.012986800, -0.012976000, -0.012951000, -0.012918800, -0.012844700, -0.012673700, -0.012279600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086040000; - } - pin ("B") { - capacitance : 0.0084720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173805000, 0.0173653000, 0.0173305000, 0.0173935000, 0.0175389000, 0.0178738000, 0.0186459000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015845200, -0.015836000, -0.015815000, -0.015810800, -0.015801200, -0.015778900, -0.015727600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086960000; - } - pin ("C") { - capacitance : 0.0085330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156250000, 0.0156266000, 0.0156301000, 0.0156303000, 0.0156307000, 0.0156316000, 0.0156337000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015610200, -0.015606800, -0.015598800, -0.015594500, -0.015584600, -0.015561900, -0.015509500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088780000; - } - pin ("D") { - capacitance : 0.0087390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157077000, 0.0156991000, 0.0156792000, 0.0156825000, 0.0156903000, 0.0157082000, 0.0157494000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015654100, -0.015659700, -0.015672500, -0.015670500, -0.015665900, -0.015655500, -0.015631300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092020000; - } - pin ("Y") { - direction : "output"; - function : "(!A) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0186030000, 0.0170370000, 0.0124358000, -0.001633200, -0.044553200, -0.173494900, -0.559542800", \ - "0.0177491000, 0.0162761000, 0.0117649000, -0.002091900, -0.044761300, -0.173593800, -0.559543000", \ - "0.0165783000, 0.0151106000, 0.0107011000, -0.002933900, -0.045243900, -0.173788700, -0.559582200", \ - "0.0156784000, 0.0141756000, 0.0097288000, -0.004058600, -0.046174400, -0.174300200, -0.559803200", \ - "0.0155492000, 0.0139650000, 0.0092610000, -0.004754400, -0.047018300, -0.175035600, -0.560206700", \ - "0.0171759000, 0.0154705000, 0.0106172000, -0.003960600, -0.047219800, -0.175686300, -0.560886300", \ - "0.0229424000, 0.0210998000, 0.0155070000, -9.55000e-05, -0.044499700, -0.174742500, -0.560929800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0140159000, 0.0158510000, 0.0211570000, 0.0362073000, 0.0792957000, 0.2076847000, 0.5882907000", \ - "0.0132190000, 0.0150592000, 0.0204067000, 0.0356714000, 0.0792600000, 0.2077523000, 0.5863967000", \ - "0.0123073000, 0.0141224000, 0.0193596000, 0.0346594000, 0.0786105000, 0.2062564000, 0.5889083000", \ - "0.0118642000, 0.0136303000, 0.0186093000, 0.0334509000, 0.0778607000, 0.2066729000, 0.5903794000", \ - "0.0119212000, 0.0135386000, 0.0183647000, 0.0330424000, 0.0761926000, 0.2066711000, 0.5851748000", \ - "0.0127122000, 0.0142293000, 0.0188276000, 0.0339861000, 0.0766944000, 0.2032347000, 0.5902992000", \ - "0.0219010000, 0.0206307000, 0.0248099000, 0.0402238000, 0.0817538000, 0.2065960000, 0.5862779000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0220777000, 0.0204876000, 0.0157842000, 0.0015510000, -0.041459600, -0.170487500, -0.556516600", \ - "0.0213333000, 0.0198920000, 0.0152493000, 0.0011976000, -0.041636400, -0.170541700, -0.556488100", \ - "0.0203947000, 0.0188965000, 0.0143745000, 0.0004848000, -0.041993100, -0.170656900, -0.556556300", \ - "0.0193535000, 0.0178673000, 0.0132940000, -0.000469500, -0.042687900, -0.171021200, -0.556673600", \ - "0.0189795000, 0.0173926000, 0.0127677000, -0.001221800, -0.043496700, -0.171489000, -0.556764300", \ - "0.0187839000, 0.0171246000, 0.0123499000, -0.001829600, -0.044503900, -0.172448200, -0.557404000", \ - "0.0215435000, 0.0197755000, 0.0147902000, -3.00000e-06, -0.043467700, -0.172771900, -0.558006500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0281140000, 0.0297558000, 0.0347118000, 0.0492496000, 0.0921554000, 0.2199161000, 0.6001347000", \ - "0.0274511000, 0.0291415000, 0.0341624000, 0.0489121000, 0.0921846000, 0.2199866000, 0.6003756000", \ - "0.0263587000, 0.0281735000, 0.0331630000, 0.0481618000, 0.0915770000, 0.2196078000, 0.6011851000", \ - "0.0252572000, 0.0270670000, 0.0319664000, 0.0469176000, 0.0904634000, 0.2183960000, 0.6010176000", \ - "0.0246571000, 0.0263426000, 0.0313667000, 0.0460568000, 0.0897376000, 0.2173856000, 0.6008098000", \ - "0.0254584000, 0.0270093000, 0.0316935000, 0.0458470000, 0.0893974000, 0.2168787000, 0.5987188000", \ - "0.0304787000, 0.0331522000, 0.0343500000, 0.0501817000, 0.0926933000, 0.2155185000, 0.5959053000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0218047000, 0.0202398000, 0.0155529000, 0.0012084000, -0.041831800, -0.170855600, -0.556788400", \ - "0.0211840000, 0.0196713000, 0.0149985000, 0.0008696000, -0.041999000, -0.170923000, -0.556909700", \ - "0.0201740000, 0.0186807000, 0.0141241000, 0.0002420000, -0.042361700, -0.171102200, -0.556985100", \ - "0.0192233000, 0.0176839000, 0.0130869000, -0.000716400, -0.043008400, -0.171382800, -0.557166400", \ - "0.0186758000, 0.0171753000, 0.0124886000, -0.001448100, -0.043778400, -0.171794500, -0.557230800", \ - "0.0187194000, 0.0171936000, 0.0124139000, -0.002236900, -0.044775500, -0.172748500, -0.557733000", \ - "0.0203069000, 0.0186431000, 0.0136697000, -0.000916300, -0.044122200, -0.173260100, -0.558327800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0403066000, 0.0419327000, 0.0468289000, 0.0613239000, 0.1044702000, 0.2322445000, 0.6138008000", \ - "0.0397094000, 0.0413489000, 0.0462730000, 0.0609067000, 0.1040309000, 0.2319618000, 0.6134357000", \ - "0.0387135000, 0.0403693000, 0.0453671000, 0.0601428000, 0.1035639000, 0.2315899000, 0.6129827000", \ - "0.0376617000, 0.0395313000, 0.0443535000, 0.0590728000, 0.1026803000, 0.2307591000, 0.6126902000", \ - "0.0376329000, 0.0392940000, 0.0442787000, 0.0588390000, 0.1023200000, 0.2307906000, 0.6122943000", \ - "0.0385033000, 0.0400442000, 0.0447379000, 0.0592341000, 0.1023321000, 0.2301129000, 0.6092007000", \ - "0.0420935000, 0.0437422000, 0.0482471000, 0.0617512000, 0.1038994000, 0.2306266000, 0.6105945000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0215637000, 0.0199817000, 0.0151932000, 0.0009185000, -0.042162100, -0.171155300, -0.557244900", \ - "0.0208993000, 0.0193653000, 0.0146752000, 0.0005654000, -0.042346800, -0.171279500, -0.557253000", \ - "0.0199021000, 0.0184326000, 0.0138601000, -7.71000e-05, -0.042658900, -0.171425600, -0.557322700", \ - "0.0189905000, 0.0174441000, 0.0128708000, -0.000981100, -0.043300400, -0.171716200, -0.557491100", \ - "0.0185800000, 0.0170227000, 0.0123749000, -0.001659700, -0.044011500, -0.172131500, -0.557625800", \ - "0.0186345000, 0.0170465000, 0.0122777000, -0.002104700, -0.044927100, -0.173096400, -0.558217600", \ - "0.0204040000, 0.0187338000, 0.0137973000, -0.000897300, -0.044114000, -0.173317200, -0.558573000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014954950, 0.0044730120, 0.0133787300, 0.0400156700, 0.1196865000, 0.3579811000"); - values("0.0505226000, 0.0521053000, 0.0569047000, 0.0713579000, 0.1148573000, 0.2429654000, 0.6249235000", \ - "0.0498700000, 0.0515053000, 0.0562804000, 0.0709126000, 0.1143761000, 0.2425654000, 0.6239257000", \ - "0.0491379000, 0.0507624000, 0.0556031000, 0.0701663000, 0.1138153000, 0.2423749000, 0.6237191000", \ - "0.0482390000, 0.0498540000, 0.0547318000, 0.0694301000, 0.1131392000, 0.2415523000, 0.6234690000", \ - "0.0486304000, 0.0502364000, 0.0550297000, 0.0696924000, 0.1124403000, 0.2412978000, 0.6230694000", \ - "0.0502503000, 0.0518118000, 0.0565862000, 0.0707688000, 0.1137540000, 0.2416436000, 0.6219960000", \ - "0.0547124000, 0.0562051000, 0.0606972000, 0.0742861000, 0.1165083000, 0.2442691000, 0.6236484000"); - } - } - max_capacitance : 0.3579810000; - max_transition : 1.4971000000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0383248000, 0.0412170000, 0.0502259000, 0.0763721000, 0.1521192000, 0.3783246000, 1.0518199000", \ - "0.0409280000, 0.0439713000, 0.0530262000, 0.0795689000, 0.1562497000, 0.3839961000, 1.0562029000", \ - "0.0491333000, 0.0519686000, 0.0608142000, 0.0871435000, 0.1640941000, 0.3909202000, 1.0647678000", \ - "0.0661648000, 0.0699966000, 0.0809398000, 0.1074941000, 0.1847658000, 0.4131731000, 1.0869045000", \ - "0.0846683000, 0.0904326000, 0.1063797000, 0.1465356000, 0.2344251000, 0.4609907000, 1.1395664000", \ - "0.0951928000, 0.1038334000, 0.1274654000, 0.1867923000, 0.3172921000, 0.5769888000, 1.2556032000", \ - "0.0751527000, 0.0874035000, 0.1220142000, 0.2096603000, 0.4040361000, 0.7831524000, 1.5182311000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0320231000, 0.0342172000, 0.0407722000, 0.0591831000, 0.1119233000, 0.2688587000, 0.7346339000", \ - "0.0372808000, 0.0395164000, 0.0460518000, 0.0646804000, 0.1177196000, 0.2744474000, 0.7397638000", \ - "0.0506795000, 0.0528485000, 0.0592148000, 0.0780178000, 0.1307937000, 0.2878198000, 0.7528559000", \ - "0.0778445000, 0.0810338000, 0.0894054000, 0.1095882000, 0.1629745000, 0.3209841000, 0.7890347000", \ - "0.1208821000, 0.1260411000, 0.1395053000, 0.1723104000, 0.2377375000, 0.3946107000, 0.8587291000", \ - "0.1908684000, 0.1989702000, 0.2205514000, 0.2729200000, 0.3786590000, 0.5678089000, 1.0323331000", \ - "0.3128083000, 0.3246755000, 0.3573060000, 0.4376828000, 0.6045421000, 0.9110664000, 1.4357773000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0465908000, 0.0506948000, 0.0627696000, 0.0980039000, 0.2022073000, 0.5150299000, 1.4446551000", \ - "0.0459403000, 0.0501147000, 0.0622082000, 0.0978410000, 0.2030880000, 0.5152956000, 1.4435187000", \ - "0.0456785000, 0.0494798000, 0.0610608000, 0.0971547000, 0.2022802000, 0.5142787000, 1.4446755000", \ - "0.0568068000, 0.0608516000, 0.0705341000, 0.1013083000, 0.2014810000, 0.5143643000, 1.4456937000", \ - "0.0779018000, 0.0823986000, 0.0953350000, 0.1304455000, 0.2177257000, 0.5145317000, 1.4513617000", \ - "0.1224332000, 0.1290262000, 0.1454763000, 0.1893772000, 0.2904866000, 0.5497775000, 1.4490301000", \ - "0.1992094000, 0.2078732000, 0.2329899000, 0.2954795000, 0.4333107000, 0.7241588000, 1.4971004000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0269890000, 0.0298184000, 0.0379982000, 0.0627903000, 0.1366193000, 0.3594950000, 1.0246688000", \ - "0.0270209000, 0.0297435000, 0.0380144000, 0.0626669000, 0.1371527000, 0.3604161000, 1.0210832000", \ - "0.0285000000, 0.0308154000, 0.0382813000, 0.0627584000, 0.1367493000, 0.3578145000, 1.0233289000", \ - "0.0430854000, 0.0450419000, 0.0501162000, 0.0683148000, 0.1371154000, 0.3615489000, 1.0326445000", \ - "0.0712801000, 0.0744411000, 0.0825470000, 0.1025241000, 0.1540045000, 0.3595024000, 1.0200362000", \ - "0.1191396000, 0.1240185000, 0.1372889000, 0.1691132000, 0.2346934000, 0.3939952000, 1.0271434000", \ - "0.1972724000, 0.2056550000, 0.2273586000, 0.2791839000, 0.3862603000, 0.5751788000, 1.0792415000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0564232000, 0.0592972000, 0.0679257000, 0.0936411000, 0.1695033000, 0.3950422000, 1.0733350000", \ - "0.0592226000, 0.0626147000, 0.0714253000, 0.0975395000, 0.1736428000, 0.3996748000, 1.0733352000", \ - "0.0667824000, 0.0698247000, 0.0789806000, 0.1053322000, 0.1832331000, 0.4086647000, 1.0828047000", \ - "0.0820233000, 0.0856965000, 0.0961493000, 0.1236358000, 0.2014552000, 0.4279437000, 1.1095331000", \ - "0.1040514000, 0.1089479000, 0.1230334000, 0.1589021000, 0.2456726000, 0.4741236000, 1.1590279000", \ - "0.1180670000, 0.1260621000, 0.1478439000, 0.2029441000, 0.3225964000, 0.5792105000, 1.2568759000", \ - "0.0943839000, 0.1068383000, 0.1412613000, 0.2268518000, 0.4119000000, 0.7686818000, 1.5029664000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0494571000, 0.0518314000, 0.0586071000, 0.0788354000, 0.1377354000, 0.3117282000, 0.8302024000", \ - "0.0545690000, 0.0571105000, 0.0640539000, 0.0845347000, 0.1435140000, 0.3176506000, 0.8364252000", \ - "0.0676315000, 0.0700706000, 0.0769611000, 0.0976507000, 0.1572765000, 0.3315875000, 0.8500119000", \ - "0.0994617000, 0.1021278000, 0.1090072000, 0.1290798000, 0.1892663000, 0.3622175000, 0.8810899000", \ - "0.1574275000, 0.1615592000, 0.1726635000, 0.2008218000, 0.2643418000, 0.4382104000, 0.9590705000", \ - "0.2526361000, 0.2590287000, 0.2769087000, 0.3226133000, 0.4221757000, 0.6146514000, 1.1324321000", \ - "0.4146563000, 0.4234545000, 0.4515470000, 0.5239902000, 0.6816458000, 0.9840294000, 1.5378615000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0475955000, 0.0516306000, 0.0632936000, 0.0980462000, 0.2022046000, 0.5136244000, 1.4484471000", \ - "0.0474994000, 0.0514681000, 0.0632948000, 0.0982687000, 0.2024012000, 0.5151591000, 1.4444035000", \ - "0.0479012000, 0.0515960000, 0.0631903000, 0.0981167000, 0.2031312000, 0.5145391000, 1.4455008000", \ - "0.0551396000, 0.0584668000, 0.0686356000, 0.1008030000, 0.2027597000, 0.5140930000, 1.4492454000", \ - "0.0753073000, 0.0792231000, 0.0906304000, 0.1223639000, 0.2134811000, 0.5137601000, 1.4541939000", \ - "0.1193523000, 0.1244552000, 0.1384168000, 0.1754402000, 0.2689590000, 0.5384117000, 1.4453108000", \ - "0.2014291000, 0.2082447000, 0.2274552000, 0.2781693000, 0.3969077000, 0.6706690000, 1.4817925000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0405677000, 0.0436433000, 0.0528979000, 0.0803751000, 0.1630906000, 0.4097949000, 1.1458070000", \ - "0.0405957000, 0.0436456000, 0.0529711000, 0.0803546000, 0.1627089000, 0.4085547000, 1.1455072000", \ - "0.0405017000, 0.0436525000, 0.0528305000, 0.0804912000, 0.1626279000, 0.4088739000, 1.1471558000", \ - "0.0482658000, 0.0507814000, 0.0580445000, 0.0822674000, 0.1627850000, 0.4090896000, 1.1473397000", \ - "0.0777250000, 0.0806908000, 0.0891086000, 0.1091726000, 0.1739770000, 0.4085788000, 1.1492137000", \ - "0.1305172000, 0.1351136000, 0.1476630000, 0.1791698000, 0.2468423000, 0.4343444000, 1.1456480000", \ - "0.2149340000, 0.2227109000, 0.2452325000, 0.2961059000, 0.4021536000, 0.5994781000, 1.1820025000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0652890000, 0.0681994000, 0.0772449000, 0.1028491000, 0.1783361000, 0.4080239000, 1.0798369000", \ - "0.0686755000, 0.0717234000, 0.0804349000, 0.1063814000, 0.1827352000, 0.4087265000, 1.0826818000", \ - "0.0752996000, 0.0784901000, 0.0873877000, 0.1140676000, 0.1903404000, 0.4162143000, 1.0993739000", \ - "0.0879464000, 0.0913843000, 0.1012223000, 0.1283717000, 0.2055718000, 0.4318974000, 1.1080041000", \ - "0.1065578000, 0.1113923000, 0.1230420000, 0.1549371000, 0.2378476000, 0.4671782000, 1.1407296000", \ - "0.1208487000, 0.1281018000, 0.1453682000, 0.1913714000, 0.2955071000, 0.5427521000, 1.2253755000", \ - "0.0949631000, 0.1053537000, 0.1352848000, 0.2077879000, 0.3666922000, 0.6823452000, 1.3972768000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0588805000, 0.0613960000, 0.0687566000, 0.0893115000, 0.1496031000, 0.3258106000, 0.8489254000", \ - "0.0644227000, 0.0668696000, 0.0740525000, 0.0948002000, 0.1552635000, 0.3314635000, 0.8554013000", \ - "0.0773820000, 0.0799932000, 0.0873357000, 0.1083606000, 0.1688762000, 0.3453456000, 0.8694455000", \ - "0.1093876000, 0.1119298000, 0.1189918000, 0.1402438000, 0.1994954000, 0.3761177000, 0.8997130000", \ - "0.1746809000, 0.1776163000, 0.1881863000, 0.2137537000, 0.2760516000, 0.4523831000, 0.9754229000", \ - "0.2830987000, 0.2887965000, 0.3047029000, 0.3454793000, 0.4382564000, 0.6284473000, 1.1483676000", \ - "0.4641965000, 0.4722497000, 0.4968665000, 0.5613176000, 0.7101667000, 1.0020798000, 1.5569466000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0477103000, 0.0516366000, 0.0631245000, 0.0981748000, 0.2022045000, 0.5158033000, 1.4480550000", \ - "0.0476622000, 0.0515453000, 0.0632446000, 0.0979800000, 0.2031891000, 0.5146217000, 1.4448752000", \ - "0.0478032000, 0.0516728000, 0.0634169000, 0.0983092000, 0.2022283000, 0.5135656000, 1.4494973000", \ - "0.0526658000, 0.0562183000, 0.0668323000, 0.1000082000, 0.2025289000, 0.5136342000, 1.4467236000", \ - "0.0674148000, 0.0712040000, 0.0821461000, 0.1143053000, 0.2097198000, 0.5153352000, 1.4454734000", \ - "0.1060815000, 0.1100126000, 0.1222642000, 0.1560352000, 0.2486376000, 0.5296001000, 1.4492019000", \ - "0.1849770000, 0.1908465000, 0.2059091000, 0.2488781000, 0.3535762000, 0.6260367000, 1.4754215000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0516851000, 0.0546727000, 0.0641072000, 0.0922306000, 0.1756981000, 0.4267575000, 1.1786517000", \ - "0.0515366000, 0.0547869000, 0.0640353000, 0.0921322000, 0.1762265000, 0.4278311000, 1.1795757000", \ - "0.0512628000, 0.0544465000, 0.0639008000, 0.0921495000, 0.1763074000, 0.4267857000, 1.1779488000", \ - "0.0555242000, 0.0582411000, 0.0665978000, 0.0926970000, 0.1761127000, 0.4277127000, 1.1796075000", \ - "0.0836743000, 0.0873643000, 0.0944414000, 0.1154349000, 0.1848166000, 0.4278768000, 1.1826061000", \ - "0.1375031000, 0.1420333000, 0.1541808000, 0.1858552000, 0.2527233000, 0.4503838000, 1.1789381000", \ - "0.2273271000, 0.2348182000, 0.2553369000, 0.3042236000, 0.4090115000, 0.6099796000, 1.2176564000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0699904000, 0.0729105000, 0.0814610000, 0.1075825000, 0.1829296000, 0.4083222000, 1.0889757000", \ - "0.0732969000, 0.0763512000, 0.0850481000, 0.1115129000, 0.1871218000, 0.4127720000, 1.0866029000", \ - "0.0796682000, 0.0829070000, 0.0918910000, 0.1180824000, 0.1958487000, 0.4231515000, 1.0952482000", \ - "0.0917260000, 0.0949946000, 0.1042593000, 0.1308856000, 0.2084355000, 0.4343566000, 1.1107135000", \ - "0.1081683000, 0.1118881000, 0.1225397000, 0.1518666000, 0.2327760000, 0.4614814000, 1.1380267000", \ - "0.1214042000, 0.1266018000, 0.1411784000, 0.1795803000, 0.2739188000, 0.5150339000, 1.1938822000", \ - "0.0978673000, 0.1066714000, 0.1304459000, 0.1904859000, 0.3246467000, 0.6125376000, 1.3180546000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0591857000, 0.0615771000, 0.0685171000, 0.0884810000, 0.1445956000, 0.3061654000, 0.7826487000", \ - "0.0643185000, 0.0667922000, 0.0738800000, 0.0937000000, 0.1499404000, 0.3123845000, 0.7888840000", \ - "0.0774459000, 0.0798603000, 0.0868999000, 0.1068108000, 0.1631279000, 0.3248235000, 0.8009272000", \ - "0.1100781000, 0.1123780000, 0.1191995000, 0.1391314000, 0.1954645000, 0.3574258000, 0.8358731000", \ - "0.1766741000, 0.1800810000, 0.1891874000, 0.2130239000, 0.2698201000, 0.4312131000, 0.9091851000", \ - "0.2865642000, 0.2915498000, 0.3058855000, 0.3417643000, 0.4289881000, 0.6055874000, 1.0792164000", \ - "0.4686883000, 0.4762776000, 0.4977991000, 0.5552884000, 0.6910016000, 0.9666764000, 1.4822619000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0476257000, 0.0514888000, 0.0633135000, 0.0983604000, 0.2020957000, 0.5132398000, 1.4489897000", \ - "0.0476120000, 0.0515083000, 0.0633064000, 0.0983355000, 0.2025261000, 0.5137091000, 1.4435493000", \ - "0.0477677000, 0.0515824000, 0.0633988000, 0.0982325000, 0.2032239000, 0.5153836000, 1.4453997000", \ - "0.0505571000, 0.0541632000, 0.0651085000, 0.0990137000, 0.2029405000, 0.5136631000, 1.4472985000", \ - "0.0602490000, 0.0640152000, 0.0751794000, 0.1086941000, 0.2073316000, 0.5147535000, 1.4461722000", \ - "0.0893699000, 0.0930717000, 0.1039494000, 0.1364164000, 0.2344835000, 0.5271774000, 1.4469789000", \ - "0.1594051000, 0.1639729000, 0.1770822000, 0.2134494000, 0.3110788000, 0.5946446000, 1.4693026000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014955000, 0.0044730100, 0.0133787000, 0.0400157000, 0.1196860000, 0.3579810000"); - values("0.0581279000, 0.0611742000, 0.0697912000, 0.0958916000, 0.1733021000, 0.4052824000, 1.1035320000", \ - "0.0579230000, 0.0608157000, 0.0698022000, 0.0957365000, 0.1733129000, 0.4059695000, 1.1025553000", \ - "0.0569226000, 0.0600051000, 0.0691459000, 0.0955081000, 0.1730569000, 0.4052540000, 1.1019998000", \ - "0.0601238000, 0.0628157000, 0.0709048000, 0.0956330000, 0.1728382000, 0.4058907000, 1.1046422000", \ - "0.0880659000, 0.0908521000, 0.0986434000, 0.1185795000, 0.1821149000, 0.4053787000, 1.1041379000", \ - "0.1409855000, 0.1450918000, 0.1565868000, 0.1855604000, 0.2515229000, 0.4331570000, 1.1024696000", \ - "0.2302440000, 0.2369736000, 0.2556582000, 0.3021644000, 0.4020892000, 0.5989952000, 1.1520200000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4b_1") { - leakage_power () { - value : 0.0004407000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0004210000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0007688000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0004375000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0007679000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0004429000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0058889000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0007284000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0007748000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0007683000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0007931000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0007739000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0007945000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0007750000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0011304000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0007914000; - when : "A_N&B&C&!D"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__nand4b"; - cell_leakage_power : 0.0010310960; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0013760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0074480000, 0.0073602000, 0.0071579000, 0.0072032000, 0.0073076000, 0.0075483000, 0.0081030000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044888000, 0.0044338000, 0.0043068000, 0.0043438000, 0.0044290000, 0.0046256000, 0.0050787000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014270000; - } - pin ("B") { - capacitance : 0.0023110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045902000, 0.0045897000, 0.0045885000, 0.0045930000, 0.0046034000, 0.0046274000, 0.0046827000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004192200, -0.004193100, -0.004195300, -0.004184200, -0.004158400, -0.004099000, -0.003962000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023780000; - } - pin ("C") { - capacitance : 0.0023280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041437000, 0.0041424000, 0.0041394000, 0.0041549000, 0.0041907000, 0.0042732000, 0.0044635000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004066000, -0.004060100, -0.004046400, -0.004045800, -0.004044400, -0.004041000, -0.004033400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024130000; - } - pin ("D") { - capacitance : 0.0023190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022100000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040193000, 0.0040175000, 0.0040132000, 0.0040148000, 0.0040186000, 0.0040274000, 0.0040476000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004013700, -0.004012000, -0.004008100, -0.004008100, -0.004008200, -0.004008300, -0.004008700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024290000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0066412000, 0.0055245000, 0.0026508000, -0.004809500, -0.023882900, -0.072186500, -0.193410100", \ - "0.0066074000, 0.0054654000, 0.0025887000, -0.004846700, -0.023954400, -0.072221100, -0.193480800", \ - "0.0066281000, 0.0054995000, 0.0026246000, -0.004836100, -0.023929600, -0.072180200, -0.193441400", \ - "0.0064369000, 0.0052992000, 0.0024093000, -0.005053400, -0.024135000, -0.072386200, -0.193627800", \ - "0.0063024000, 0.0051547000, 0.0022553000, -0.005344700, -0.024366200, -0.072554100, -0.193760300", \ - "0.0059327000, 0.0048182000, 0.0019434000, -0.005234400, -0.024325600, -0.072412600, -0.193544200", \ - "0.0064294000, 0.0051911000, 0.0019871000, -0.005601600, -0.024551100, -0.072668100, -0.193756600"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0046268000, 0.0059505000, 0.0091633000, 0.0169597000, 0.0361598000, 0.0840601000, 0.2040674000", \ - "0.0046093000, 0.0059544000, 0.0091754000, 0.0169733000, 0.0361824000, 0.0840752000, 0.2042197000", \ - "0.0045852000, 0.0059046000, 0.0091330000, 0.0169437000, 0.0361980000, 0.0842642000, 0.2039911000", \ - "0.0042798000, 0.0055558000, 0.0087559000, 0.0166193000, 0.0359600000, 0.0844600000, 0.2050132000", \ - "0.0040640000, 0.0053309000, 0.0084414000, 0.0162634000, 0.0356116000, 0.0841551000, 0.2025966000", \ - "0.0040259000, 0.0052908000, 0.0084748000, 0.0161092000, 0.0355472000, 0.0831718000, 0.2038271000", \ - "0.0043487000, 0.0055726000, 0.0086818000, 0.0163568000, 0.0356444000, 0.0839743000, 0.2028954000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0074995000, 0.0063372000, 0.0033226000, -0.004299400, -0.023547500, -0.071885100, -0.193184000", \ - "0.0073409000, 0.0061873000, 0.0032223000, -0.004363100, -0.023573400, -0.071911300, -0.193201800", \ - "0.0071153000, 0.0059772000, 0.0030535000, -0.004481700, -0.023627300, -0.071951100, -0.193205500", \ - "0.0068597000, 0.0057102000, 0.0027955000, -0.004695200, -0.023784400, -0.072022300, -0.193263700", \ - "0.0067092000, 0.0055422000, 0.0025596000, -0.004900300, -0.023939300, -0.072157200, -0.193295200", \ - "0.0069195000, 0.0057058000, 0.0026547000, -0.005129000, -0.024247400, -0.072363500, -0.193461600", \ - "0.0076733000, 0.0063899000, 0.0031945000, -0.004666800, -0.024146700, -0.072518900, -0.193672900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0058952000, 0.0071225000, 0.0101911000, 0.0178066000, 0.0368259000, 0.0845173000, 0.2042538000", \ - "0.0056978000, 0.0069599000, 0.0100660000, 0.0177411000, 0.0368358000, 0.0845160000, 0.2041632000", \ - "0.0054396000, 0.0066940000, 0.0098256000, 0.0175487000, 0.0366676000, 0.0845628000, 0.2042436000", \ - "0.0052361000, 0.0064306000, 0.0095247000, 0.0172708000, 0.0363144000, 0.0843305000, 0.2041537000", \ - "0.0052699000, 0.0064942000, 0.0095224000, 0.0171297000, 0.0362133000, 0.0837487000, 0.2033220000", \ - "0.0054325000, 0.0065924000, 0.0097941000, 0.0174426000, 0.0363317000, 0.0840773000, 0.2029446000", \ - "0.0067073000, 0.0078257000, 0.0106981000, 0.0179690000, 0.0369309000, 0.0840176000, 0.2032464000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0077242000, 0.0065330000, 0.0035280000, -0.004088600, -0.023361100, -0.071703200, -0.192983300", \ - "0.0075496000, 0.0064049000, 0.0034260000, -0.004155600, -0.023384800, -0.071715700, -0.193009700", \ - "0.0073070000, 0.0061702000, 0.0032359000, -0.004298700, -0.023462200, -0.071754200, -0.193046500", \ - "0.0070669000, 0.0059091000, 0.0029786000, -0.004504300, -0.023588900, -0.071816600, -0.193048300", \ - "0.0069047000, 0.0057185000, 0.0027673000, -0.004695400, -0.023793100, -0.071933800, -0.193102000", \ - "0.0070765000, 0.0058620000, 0.0028265000, -0.004914000, -0.023982800, -0.072116200, -0.193239500", \ - "0.0077088000, 0.0064318000, 0.0032663000, -0.004499000, -0.023851900, -0.072193300, -0.193326100"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0087485000, 0.0099726000, 0.0130316000, 0.0206796000, 0.0397160000, 0.0874691000, 0.2071652000", \ - "0.0085662000, 0.0097704000, 0.0128515000, 0.0205314000, 0.0396398000, 0.0874412000, 0.2071104000", \ - "0.0083531000, 0.0096021000, 0.0127119000, 0.0203312000, 0.0394457000, 0.0873592000, 0.2072210000", \ - "0.0080523000, 0.0092856000, 0.0123800000, 0.0201316000, 0.0391228000, 0.0870891000, 0.2069635000", \ - "0.0079720000, 0.0092075000, 0.0122487000, 0.0199153000, 0.0388235000, 0.0867064000, 0.2059639000", \ - "0.0083288000, 0.0096107000, 0.0127266000, 0.0205547000, 0.0392096000, 0.0871231000, 0.2066123000", \ - "0.0093751000, 0.0105123000, 0.0134038000, 0.0207234000, 0.0396401000, 0.0871485000, 0.2061693000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0076171000, 0.0064405000, 0.0034363000, -0.004185500, -0.023450000, -0.071789200, -0.193097600", \ - "0.0074689000, 0.0062963000, 0.0033425000, -0.004250800, -0.023475600, -0.071805900, -0.193087600", \ - "0.0072278000, 0.0060727000, 0.0031443000, -0.004374700, -0.023545400, -0.071836200, -0.193111600", \ - "0.0069787000, 0.0058317000, 0.0028994000, -0.004583900, -0.023661800, -0.071891900, -0.193152100", \ - "0.0068357000, 0.0056641000, 0.0027025000, -0.004833400, -0.023894600, -0.072017600, -0.193216800", \ - "0.0070153000, 0.0057978000, 0.0027663000, -0.004982600, -0.024067200, -0.072209100, -0.193307700", \ - "0.0076201000, 0.0063513000, 0.0031932000, -0.004538300, -0.023854000, -0.072264800, -0.193414400"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012541490, 0.0031457800, 0.0078905540, 0.0197918600, 0.0496438900, 0.1245217000"); - values("0.0109791000, 0.0122233000, 0.0152957000, 0.0229897000, 0.0421330000, 0.0899624000, 0.2097148000", \ - "0.0108381000, 0.0120624000, 0.0151510000, 0.0228659000, 0.0420583000, 0.0899004000, 0.2096094000", \ - "0.0106586000, 0.0119015000, 0.0149994000, 0.0227388000, 0.0419720000, 0.0897642000, 0.2095400000", \ - "0.0104887000, 0.0117153000, 0.0148174000, 0.0225872000, 0.0417626000, 0.0898448000, 0.2095700000", \ - "0.0104978000, 0.0117338000, 0.0147952000, 0.0224923000, 0.0413666000, 0.0892012000, 0.2086873000", \ - "0.0109336000, 0.0121691000, 0.0151786000, 0.0228199000, 0.0416810000, 0.0893413000, 0.2082375000", \ - "0.0126580000, 0.0138271000, 0.0166772000, 0.0240294000, 0.0433368000, 0.0904531000, 0.2092359000"); - } - } - max_capacitance : 0.1245220000; - max_transition : 1.4920960000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.1240825000, 0.1318752000, 0.1501627000, 0.1925199000, 0.2948201000, 0.5486759000, 1.1842732000", \ - "0.1291518000, 0.1368204000, 0.1551485000, 0.1975239000, 0.2997926000, 0.5534526000, 1.1893317000", \ - "0.1418629000, 0.1496519000, 0.1679225000, 0.2103246000, 0.3127004000, 0.5663613000, 1.2022504000", \ - "0.1737615000, 0.1814525000, 0.1996373000, 0.2421427000, 0.3446368000, 0.5983706000, 1.2346743000", \ - "0.2437547000, 0.2515219000, 0.2697189000, 0.3126661000, 0.4152453000, 0.6694326000, 1.3051231000", \ - "0.3642490000, 0.3731304000, 0.3926783000, 0.4360624000, 0.5388683000, 0.7930810000, 1.4286189000", \ - "0.5542242000, 0.5647362000, 0.5884412000, 0.6363362000, 0.7405009000, 0.9944406000, 1.6309106000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0681532000, 0.0739964000, 0.0877894000, 0.1206248000, 0.2008982000, 0.4016053000, 0.9040030000", \ - "0.0731245000, 0.0789013000, 0.0927062000, 0.1254645000, 0.2058900000, 0.4061623000, 0.9076859000", \ - "0.0842837000, 0.0900603000, 0.1037980000, 0.1366302000, 0.2177570000, 0.4188620000, 0.9184903000", \ - "0.1064923000, 0.1122658000, 0.1260005000, 0.1590184000, 0.2398026000, 0.4402586000, 0.9404415000", \ - "0.1376733000, 0.1436929000, 0.1575917000, 0.1910336000, 0.2716763000, 0.4725423000, 0.9741800000", \ - "0.1745144000, 0.1811783000, 0.1961802000, 0.2293978000, 0.3101729000, 0.5119514000, 1.0139263000", \ - "0.1990085000, 0.2078771000, 0.2269969000, 0.2628825000, 0.3429559000, 0.5432527000, 1.0468343000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0470699000, 0.0555757000, 0.0769165000, 0.1296769000, 0.2640740000, 0.6045477000, 1.4561121000", \ - "0.0469918000, 0.0555927000, 0.0767982000, 0.1295664000, 0.2645637000, 0.6033964000, 1.4561015000", \ - "0.0470461000, 0.0556215000, 0.0767806000, 0.1296645000, 0.2639274000, 0.6035825000, 1.4570846000", \ - "0.0470111000, 0.0556457000, 0.0769157000, 0.1295784000, 0.2648426000, 0.6039976000, 1.4560108000", \ - "0.0493060000, 0.0575748000, 0.0781065000, 0.1301027000, 0.2647133000, 0.6035878000, 1.4560815000", \ - "0.0584001000, 0.0662770000, 0.0860640000, 0.1356730000, 0.2657824000, 0.6048041000, 1.4579209000", \ - "0.0777159000, 0.0853108000, 0.1034092000, 0.1491955000, 0.2721575000, 0.6063822000, 1.4564016000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0319103000, 0.0389280000, 0.0565662000, 0.1013273000, 0.2149602000, 0.5031309000, 1.2240146000", \ - "0.0320246000, 0.0388625000, 0.0565864000, 0.1016121000, 0.2157002000, 0.5024577000, 1.2189530000", \ - "0.0319994000, 0.0390032000, 0.0565569000, 0.1014592000, 0.2165206000, 0.5020867000, 1.2129573000", \ - "0.0330468000, 0.0397380000, 0.0569935000, 0.1016562000, 0.2157719000, 0.5038139000, 1.2213032000", \ - "0.0364232000, 0.0426046000, 0.0590916000, 0.1025724000, 0.2147357000, 0.5018043000, 1.2169681000", \ - "0.0452271000, 0.0507895000, 0.0647846000, 0.1054675000, 0.2165089000, 0.4984389000, 1.2148705000", \ - "0.0629788000, 0.0682519000, 0.0809567000, 0.1161883000, 0.2189918000, 0.5041255000, 1.2135483000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0507679000, 0.0576291000, 0.0742226000, 0.1157749000, 0.2172597000, 0.4722754000, 1.1065278000", \ - "0.0542792000, 0.0610625000, 0.0780001000, 0.1191596000, 0.2214423000, 0.4742720000, 1.1120443000", \ - "0.0615549000, 0.0686173000, 0.0856845000, 0.1276398000, 0.2295730000, 0.4827821000, 1.1220674000", \ - "0.0764795000, 0.0847751000, 0.1035228000, 0.1458462000, 0.2485841000, 0.5053381000, 1.1387629000", \ - "0.0973075000, 0.1093707000, 0.1342871000, 0.1864427000, 0.2941225000, 0.5500163000, 1.1908858000", \ - "0.1122252000, 0.1304042000, 0.1695593000, 0.2465343000, 0.3858247000, 0.6563900000, 1.2963877000", \ - "0.0954034000, 0.1235547000, 0.1842822000, 0.3028753000, 0.5134276000, 0.8720615000, 1.5481402000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0455083000, 0.0514467000, 0.0659483000, 0.1014809000, 0.1894662000, 0.4088779000, 0.9583688000", \ - "0.0508379000, 0.0568249000, 0.0715312000, 0.1074274000, 0.1953855000, 0.4151820000, 0.9642457000", \ - "0.0640073000, 0.0699740000, 0.0845485000, 0.1202827000, 0.2085979000, 0.4281980000, 0.9775760000", \ - "0.0956195000, 0.1023943000, 0.1167002000, 0.1524944000, 0.2399869000, 0.4596275000, 1.0120251000", \ - "0.1520440000, 0.1622146000, 0.1840890000, 0.2271328000, 0.3151223000, 0.5331064000, 1.0821108000", \ - "0.2439151000, 0.2601831000, 0.2955821000, 0.3651086000, 0.4871997000, 0.7100462000, 1.2552440000", \ - "0.3966993000, 0.4216979000, 0.4766537000, 0.5880833000, 0.7856814000, 1.1045925000, 1.6627347000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0420021000, 0.0511136000, 0.0731998000, 0.1284833000, 0.2639856000, 0.6050891000, 1.4554258000", \ - "0.0420536000, 0.0510130000, 0.0731034000, 0.1279798000, 0.2642634000, 0.6032037000, 1.4613963000", \ - "0.0423661000, 0.0512499000, 0.0733550000, 0.1277998000, 0.2648597000, 0.6033392000, 1.4614809000", \ - "0.0501413000, 0.0579269000, 0.0772218000, 0.1289506000, 0.2637659000, 0.6048614000, 1.4549436000", \ - "0.0701936000, 0.0791386000, 0.0994967000, 0.1469214000, 0.2696249000, 0.6038013000, 1.4597967000", \ - "0.1135334000, 0.1247978000, 0.1502130000, 0.2047875000, 0.3186289000, 0.6189535000, 1.4580988000", \ - "0.1919801000, 0.2083531000, 0.2434533000, 0.3170545000, 0.4548932000, 0.7402377000, 1.4920961000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0415542000, 0.0494026000, 0.0689721000, 0.1182148000, 0.2416921000, 0.5516647000, 1.3294924000", \ - "0.0416398000, 0.0494959000, 0.0689703000, 0.1180341000, 0.2414375000, 0.5514263000, 1.3266294000", \ - "0.0415668000, 0.0493023000, 0.0690983000, 0.1183556000, 0.2411535000, 0.5511839000, 1.3273592000", \ - "0.0514427000, 0.0568038000, 0.0729367000, 0.1183530000, 0.2415712000, 0.5509120000, 1.3290788000", \ - "0.0829742000, 0.0900307000, 0.1055231000, 0.1397586000, 0.2454459000, 0.5508877000, 1.3316667000", \ - "0.1362698000, 0.1474584000, 0.1721114000, 0.2178951000, 0.3034960000, 0.5626856000, 1.3277969000", \ - "0.2231491000, 0.2418981000, 0.2822467000, 0.3577667000, 0.4823449000, 0.6991300000, 1.3532149000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0594497000, 0.0662586000, 0.0830392000, 0.1241487000, 0.2254797000, 0.4789906000, 1.1140711000", \ - "0.0629961000, 0.0699714000, 0.0869050000, 0.1281816000, 0.2299339000, 0.4838774000, 1.1186915000", \ - "0.0701691000, 0.0772014000, 0.0944153000, 0.1362810000, 0.2377654000, 0.4921892000, 1.1337680000", \ - "0.0838130000, 0.0914815000, 0.1096318000, 0.1515660000, 0.2541052000, 0.5080927000, 1.1436406000", \ - "0.1035033000, 0.1135166000, 0.1361078000, 0.1848908000, 0.2909106000, 0.5459594000, 1.1847182000", \ - "0.1194125000, 0.1349373000, 0.1688926000, 0.2365316000, 0.3684054000, 0.6337565000, 1.2715087000", \ - "0.1008467000, 0.1257101000, 0.1800892000, 0.2864814000, 0.4758500000, 0.8104284000, 1.4797938000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0545616000, 0.0606210000, 0.0753246000, 0.1112934000, 0.1998526000, 0.4200555000, 0.9709028000", \ - "0.0599620000, 0.0658817000, 0.0807440000, 0.1168162000, 0.2054311000, 0.4258760000, 0.9764070000", \ - "0.0730787000, 0.0791360000, 0.0939402000, 0.1299024000, 0.2187188000, 0.4390533000, 0.9894972000", \ - "0.1055097000, 0.1113992000, 0.1261186000, 0.1622157000, 0.2499585000, 0.4707356000, 1.0214490000", \ - "0.1683358000, 0.1772665000, 0.1972458000, 0.2380159000, 0.3237160000, 0.5431143000, 1.0943527000", \ - "0.2717318000, 0.2860612000, 0.3180265000, 0.3818556000, 0.4969213000, 0.7187145000, 1.2664048000", \ - "0.4416166000, 0.4640069000, 0.5126241000, 0.6168794000, 0.8055479000, 1.1189807000, 1.6756808000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0421744000, 0.0511617000, 0.0732532000, 0.1283618000, 0.2637906000, 0.6037303000, 1.4572611000", \ - "0.0422809000, 0.0513088000, 0.0732745000, 0.1283624000, 0.2638878000, 0.6044254000, 1.4583753000", \ - "0.0424436000, 0.0514025000, 0.0735526000, 0.1278972000, 0.2640621000, 0.6044451000, 1.4598581000", \ - "0.0475521000, 0.0553490000, 0.0761079000, 0.1289184000, 0.2636830000, 0.6043124000, 1.4551221000", \ - "0.0633472000, 0.0719569000, 0.0924693000, 0.1420704000, 0.2686759000, 0.6036405000, 1.4600250000", \ - "0.1032145000, 0.1129708000, 0.1360646000, 0.1872647000, 0.3083364000, 0.6164433000, 1.4556485000", \ - "0.1818025000, 0.1948491000, 0.2258078000, 0.2894077000, 0.4199048000, 0.7146708000, 1.4842712000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0509406000, 0.0587187000, 0.0780615000, 0.1270458000, 0.2505978000, 0.5616024000, 1.3409212000", \ - "0.0509791000, 0.0586288000, 0.0780526000, 0.1273826000, 0.2505791000, 0.5609089000, 1.3411324000", \ - "0.0506642000, 0.0583944000, 0.0779086000, 0.1270925000, 0.2505852000, 0.5609682000, 1.3414652000", \ - "0.0560796000, 0.0625673000, 0.0800810000, 0.1269865000, 0.2505861000, 0.5617677000, 1.3453157000", \ - "0.0870157000, 0.0937323000, 0.1077260000, 0.1440251000, 0.2536834000, 0.5612734000, 1.3433361000", \ - "0.1417194000, 0.1527197000, 0.1759331000, 0.2210835000, 0.3082484000, 0.5716596000, 1.3411281000", \ - "0.2314346000, 0.2494977000, 0.2868336000, 0.3617148000, 0.4874958000, 0.7060216000, 1.3674957000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0632274000, 0.0699450000, 0.0867299000, 0.1280241000, 0.2291987000, 0.4827174000, 1.1178289000", \ - "0.0667272000, 0.0738466000, 0.0908570000, 0.1318549000, 0.2337955000, 0.4876615000, 1.1280415000", \ - "0.0739524000, 0.0810741000, 0.0982668000, 0.1398581000, 0.2418506000, 0.4954972000, 1.1310305000", \ - "0.0875439000, 0.0949008000, 0.1125230000, 0.1544782000, 0.2572587000, 0.5119565000, 1.1472100000", \ - "0.1066945000, 0.1156093000, 0.1361643000, 0.1825876000, 0.2872166000, 0.5438775000, 1.1822839000", \ - "0.1251940000, 0.1377587000, 0.1666506000, 0.2262303000, 0.3489906000, 0.6131883000, 1.2532645000", \ - "0.1112211000, 0.1337523000, 0.1798794000, 0.2730582000, 0.4420030000, 0.7571331000, 1.4174604000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0547279000, 0.0606051000, 0.0742538000, 0.1079575000, 0.1896673000, 0.3918903000, 0.8968973000", \ - "0.0601857000, 0.0658955000, 0.0796990000, 0.1133646000, 0.1951400000, 0.3977911000, 0.9021996000", \ - "0.0736007000, 0.0794726000, 0.0934198000, 0.1270883000, 0.2080655000, 0.4101153000, 0.9148813000", \ - "0.1060084000, 0.1115379000, 0.1252585000, 0.1588338000, 0.2407089000, 0.4429125000, 0.9455592000", \ - "0.1699966000, 0.1780805000, 0.1963361000, 0.2341049000, 0.3131127000, 0.5145922000, 1.0179568000", \ - "0.2733817000, 0.2862374000, 0.3153345000, 0.3748185000, 0.4840710000, 0.6896453000, 1.1836502000", \ - "0.4409470000, 0.4587395000, 0.5043375000, 0.6007417000, 0.7787954000, 1.0746543000, 1.5922987000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0422652000, 0.0512247000, 0.0732226000, 0.1283628000, 0.2638167000, 0.6037099000, 1.4547338000", \ - "0.0423854000, 0.0512451000, 0.0736499000, 0.1283507000, 0.2638915000, 0.6043351000, 1.4603890000", \ - "0.0423394000, 0.0512951000, 0.0732736000, 0.1283693000, 0.2637623000, 0.6043213000, 1.4552787000", \ - "0.0454911000, 0.0537453000, 0.0749381000, 0.1284750000, 0.2643721000, 0.6047931000, 1.4563624000", \ - "0.0567806000, 0.0656325000, 0.0867020000, 0.1376413000, 0.2672405000, 0.6054957000, 1.4666502000", \ - "0.0891377000, 0.0984577000, 0.1203142000, 0.1720029000, 0.2973031000, 0.6139518000, 1.4583973000", \ - "0.1619079000, 0.1737912000, 0.2004742000, 0.2597243000, 0.3866814000, 0.6919406000, 1.4812342000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012541500, 0.0031457800, 0.0078905500, 0.0197919000, 0.0496439000, 0.1245220000"); - values("0.0535523000, 0.0604849000, 0.0785279000, 0.1232767000, 0.2361265000, 0.5214879000, 1.2392568000", \ - "0.0532857000, 0.0603637000, 0.0784378000, 0.1233618000, 0.2361541000, 0.5224906000, 1.2396978000", \ - "0.0528347000, 0.0600520000, 0.0781733000, 0.1232638000, 0.2365200000, 0.5217775000, 1.2392685000", \ - "0.0575109000, 0.0636541000, 0.0798196000, 0.1228705000, 0.2363880000, 0.5220949000, 1.2402156000", \ - "0.0874572000, 0.0937671000, 0.1070734000, 0.1406023000, 0.2407517000, 0.5218982000, 1.2389174000", \ - "0.1419635000, 0.1517327000, 0.1736740000, 0.2165307000, 0.2981844000, 0.5354218000, 1.2390589000", \ - "0.2317487000, 0.2485011000, 0.2833903000, 0.3549025000, 0.4767586000, 0.6834385000, 1.2736504000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4b_2") { - leakage_power () { - value : 0.0003079000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0236149000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0008188000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0027055000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0008209000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0333430000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0071410000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0008235000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0024095000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0155860000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0024389000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0155875000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0024412000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0156779000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0031248000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0024441000; - when : "A_N&B&C&!D"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__nand4b"; - cell_leakage_power : 0.0080803330; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102045000, 0.0101102000, 0.0098929000, 0.0099387000, 0.0100442000, 0.0102872000, 0.0108476000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087581000, 0.0087043000, 0.0085802000, 0.0086149000, 0.0086950000, 0.0088795000, 0.0093051000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015630000; - } - pin ("B") { - capacitance : 0.0044400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088964000, 0.0088961000, 0.0088955000, 0.0089026000, 0.0089189000, 0.0089566000, 0.0090435000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008089800, -0.008083300, -0.008068200, -0.008059000, -0.008037900, -0.007989200, -0.007876900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045600000; - } - pin ("C") { - capacitance : 0.0044460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081200000, 0.0081201000, 0.0081201000, 0.0081393000, 0.0081836000, 0.0082856000, 0.0085207000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008021700, -0.008009700, -0.007981900, -0.007980600, -0.007977400, -0.007970000, -0.007953000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046010000; - } - pin ("D") { - capacitance : 0.0044730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080114000, 0.0080069000, 0.0079967000, 0.0080000000, 0.0080077000, 0.0080252000, 0.0080658000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007999200, -0.007995800, -0.007988000, -0.007986200, -0.007982000, -0.007972100, -0.007949300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046950000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0116228000, 0.0103348000, 0.0067525000, -0.002994900, -0.030326200, -0.105606600, -0.310570900", \ - "0.0115238000, 0.0102324000, 0.0067791000, -0.003057800, -0.030354200, -0.105637700, -0.310590100", \ - "0.0115884000, 0.0102852000, 0.0067591000, -0.002964100, -0.030320500, -0.105547500, -0.310550700", \ - "0.0114040000, 0.0101256000, 0.0065476000, -0.003269800, -0.030682900, -0.105773100, -0.310864100", \ - "0.0110620000, 0.0097450000, 0.0061357000, -0.003753800, -0.031068800, -0.106173200, -0.311180700", \ - "0.0108752000, 0.0095410000, 0.0058860000, -0.004040200, -0.031434800, -0.106502300, -0.311371200", \ - "0.0115083000, 0.0101036000, 0.0065202000, -0.003672600, -0.031201900, -0.106263800, -0.310997300"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0067452000, 0.0082922000, 0.0124023000, 0.0231212000, 0.0511307000, 0.1260400000, 0.3271913000", \ - "0.0067548000, 0.0082988000, 0.0124138000, 0.0231423000, 0.0511486000, 0.1267610000, 0.3295385000", \ - "0.0067200000, 0.0082743000, 0.0123912000, 0.0231427000, 0.0511347000, 0.1262001000, 0.3298131000", \ - "0.0063814000, 0.0078996000, 0.0119196000, 0.0226241000, 0.0508174000, 0.1253534000, 0.3297560000", \ - "0.0060549000, 0.0075488000, 0.0115469000, 0.0221254000, 0.0500617000, 0.1254755000, 0.3302718000", \ - "0.0061743000, 0.0076250000, 0.0116094000, 0.0218617000, 0.0497940000, 0.1249389000, 0.3285566000", \ - "0.0065029000, 0.0079119000, 0.0117649000, 0.0221733000, 0.0500653000, 0.1245639000, 0.3267905000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0149982000, 0.0136297000, 0.0100137000, -8.44000e-05, -0.027820800, -0.103348200, -0.308538700", \ - "0.0145923000, 0.0133047000, 0.0097479000, -0.000250400, -0.027889300, -0.103384100, -0.308563300", \ - "0.0141315000, 0.0128617000, 0.0093194000, -0.000576700, -0.028076700, -0.103472400, -0.308594000", \ - "0.0136355000, 0.0123343000, 0.0087927000, -0.001049700, -0.028398600, -0.103635900, -0.308644700", \ - "0.0134728000, 0.0121425000, 0.0084962000, -0.001441900, -0.028773700, -0.103859400, -0.308757700", \ - "0.0134712000, 0.0120592000, 0.0083218000, -0.001826200, -0.029318800, -0.104358000, -0.309161800", \ - "0.0147333000, 0.0133059000, 0.0093681000, -0.001062900, -0.029111200, -0.104665400, -0.309456600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0109964000, 0.0123901000, 0.0161019000, 0.0262499000, 0.0538169000, 0.1284525000, 0.3307778000", \ - "0.0105832000, 0.0119989000, 0.0158235000, 0.0260044000, 0.0537491000, 0.1285251000, 0.3307777000", \ - "0.0100097000, 0.0114541000, 0.0153571000, 0.0256856000, 0.0534443000, 0.1283357000, 0.3307103000", \ - "0.0094393000, 0.0108680000, 0.0147453000, 0.0250324000, 0.0529399000, 0.1278424000, 0.3302183000", \ - "0.0090806000, 0.0104924000, 0.0143482000, 0.0246115000, 0.0524924000, 0.1270925000, 0.3297234000", \ - "0.0088695000, 0.0102380000, 0.0141343000, 0.0245815000, 0.0522712000, 0.1271108000, 0.3298983000", \ - "0.0114155000, 0.0127261000, 0.0165132000, 0.0274185000, 0.0529410000, 0.1265598000, 0.3286235000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0151201000, 0.0137955000, 0.0101342000, 1.610000e-05, -0.027720500, -0.103240100, -0.308446500", \ - "0.0147579000, 0.0134691000, 0.0098760000, -0.000136300, -0.027792400, -0.103258900, -0.308471400", \ - "0.0142794000, 0.0129828000, 0.0094499000, -0.000446100, -0.027964000, -0.103364800, -0.308492600", \ - "0.0137994000, 0.0124778000, 0.0089342000, -0.000897700, -0.028252800, -0.103524400, -0.308568300", \ - "0.0135881000, 0.0122306000, 0.0086718000, -0.001296700, -0.028648600, -0.103735000, -0.308665900", \ - "0.0137593000, 0.0124364000, 0.0086415000, -0.001706900, -0.029070500, -0.104157300, -0.308879200", \ - "0.0145468000, 0.0131391000, 0.0092700000, -0.001054400, -0.028918200, -0.104389300, -0.309250900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0163886000, 0.0177514000, 0.0214997000, 0.0316529000, 0.0591992000, 0.1339943000, 0.3364477000", \ - "0.0160631000, 0.0174480000, 0.0212157000, 0.0314412000, 0.0590622000, 0.1337414000, 0.3363414000", \ - "0.0155562000, 0.0169515000, 0.0207572000, 0.0311174000, 0.0588893000, 0.1335662000, 0.3361527000", \ - "0.0150466000, 0.0164369000, 0.0202381000, 0.0305638000, 0.0583842000, 0.1330881000, 0.3361725000", \ - "0.0150249000, 0.0164445000, 0.0202697000, 0.0304478000, 0.0582346000, 0.1331436000, 0.3357606000", \ - "0.0148591000, 0.0162447000, 0.0202743000, 0.0305641000, 0.0580613000, 0.1328420000, 0.3340571000", \ - "0.0185361000, 0.0199288000, 0.0216727000, 0.0313141000, 0.0590141000, 0.1328910000, 0.3341779000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0148233000, 0.0135158000, 0.0098212000, -0.000281500, -0.028011700, -0.103536900, -0.308779600", \ - "0.0144923000, 0.0132147000, 0.0095858000, -0.000447500, -0.028108400, -0.103612000, -0.308792400", \ - "0.0140278000, 0.0127699000, 0.0092136000, -0.000704900, -0.028259700, -0.103677600, -0.308823600", \ - "0.0135598000, 0.0122736000, 0.0087214000, -0.001137100, -0.028521500, -0.103802900, -0.308873600", \ - "0.0134014000, 0.0120986000, 0.0084477000, -0.001506700, -0.028895300, -0.104010500, -0.308958700", \ - "0.0135564000, 0.0121878000, 0.0084713000, -0.001902200, -0.029375600, -0.104469900, -0.309229300", \ - "0.0143258000, 0.0128326000, 0.0090277000, -0.001310300, -0.029105500, -0.104687200, -0.309529500"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0219672000, 0.0233859000, 0.0271885000, 0.0374634000, 0.0653006000, 0.1400641000, 0.3429497000", \ - "0.0216286000, 0.0230470000, 0.0268457000, 0.0372051000, 0.0650040000, 0.1400704000, 0.3426823000", \ - "0.0212288000, 0.0226429000, 0.0264531000, 0.0368177000, 0.0645753000, 0.1397775000, 0.3426355000", \ - "0.0208210000, 0.0222478000, 0.0260939000, 0.0364929000, 0.0644357000, 0.1393346000, 0.3425480000", \ - "0.0208551000, 0.0222375000, 0.0260273000, 0.0363779000, 0.0639291000, 0.1392699000, 0.3419383000", \ - "0.0216989000, 0.0230545000, 0.0267724000, 0.0369469000, 0.0643965000, 0.1393201000, 0.3408932000", \ - "0.0238965000, 0.0252314000, 0.0287558000, 0.0385230000, 0.0659966000, 0.1403955000, 0.3411441000"); - } - } - max_capacitance : 0.2005100000; - max_transition : 1.4944930000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.1553981000, 0.1612445000, 0.1758721000, 0.2124360000, 0.3037050000, 0.5463500000, 1.2048530000", \ - "0.1601095000, 0.1659157000, 0.1809194000, 0.2171033000, 0.3085045000, 0.5511919000, 1.2094540000", \ - "0.1722165000, 0.1784220000, 0.1932706000, 0.2297214000, 0.3211410000, 0.5646673000, 1.2211789000", \ - "0.2029481000, 0.2087026000, 0.2234911000, 0.2599014000, 0.3515456000, 0.5948331000, 1.2555447000", \ - "0.2740642000, 0.2798050000, 0.2944892000, 0.3305752000, 0.4221279000, 0.6653979000, 1.3225244000", \ - "0.4029048000, 0.4094581000, 0.4255926000, 0.4635141000, 0.5558844000, 0.7988298000, 1.4546810000", \ - "0.5982098000, 0.6065228000, 0.6267596000, 0.6701465000, 0.7651930000, 1.0072972000, 1.6636621000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0857938000, 0.0897580000, 0.0997894000, 0.1242560000, 0.1862642000, 0.3522299000, 0.7973858000", \ - "0.0906703000, 0.0946479000, 0.1046238000, 0.1290524000, 0.1910147000, 0.3569592000, 0.8041354000", \ - "0.1022729000, 0.1062115000, 0.1162335000, 0.1407443000, 0.2029319000, 0.3684333000, 0.8167508000", \ - "0.1287192000, 0.1326524000, 0.1425677000, 0.1669339000, 0.2293398000, 0.3943154000, 0.8438026000", \ - "0.1749224000, 0.1790900000, 0.1894470000, 0.2145015000, 0.2766011000, 0.4424596000, 0.8885223000", \ - "0.2368547000, 0.2421692000, 0.2537986000, 0.2800995000, 0.3432911000, 0.5085412000, 0.9561826000", \ - "0.3081934000, 0.3146448000, 0.3298101000, 0.3617733000, 0.4274645000, 0.5919413000, 1.0384678000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0518733000, 0.0582659000, 0.0748682000, 0.1189158000, 0.2381917000, 0.5655402000, 1.4666136000", \ - "0.0520879000, 0.0582106000, 0.0750018000, 0.1190182000, 0.2381853000, 0.5655698000, 1.4667891000", \ - "0.0520418000, 0.0582724000, 0.0749860000, 0.1189794000, 0.2380089000, 0.5681811000, 1.4606543000", \ - "0.0520012000, 0.0583725000, 0.0748792000, 0.1189413000, 0.2381756000, 0.5664041000, 1.4678155000", \ - "0.0525602000, 0.0591738000, 0.0758562000, 0.1193629000, 0.2383168000, 0.5660430000, 1.4613133000", \ - "0.0625228000, 0.0684354000, 0.0843447000, 0.1263083000, 0.2408096000, 0.5670837000, 1.4608165000", \ - "0.0842246000, 0.0897337000, 0.1052216000, 0.1440952000, 0.2514278000, 0.5700886000, 1.4612846000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0316715000, 0.0356467000, 0.0464302000, 0.0767322000, 0.1621598000, 0.3981576000, 1.0346985000", \ - "0.0316861000, 0.0356397000, 0.0463698000, 0.0767909000, 0.1619852000, 0.3976072000, 1.0384769000", \ - "0.0317170000, 0.0356164000, 0.0464568000, 0.0767773000, 0.1622010000, 0.3964686000, 1.0378364000", \ - "0.0322127000, 0.0360950000, 0.0469126000, 0.0769945000, 0.1622646000, 0.3972812000, 1.0391039000", \ - "0.0367604000, 0.0402856000, 0.0502601000, 0.0793245000, 0.1625401000, 0.3989861000, 1.0348895000", \ - "0.0471376000, 0.0505670000, 0.0595002000, 0.0855673000, 0.1652717000, 0.3959268000, 1.0338211000", \ - "0.0664757000, 0.0702205000, 0.0788991000, 0.1033994000, 0.1731856000, 0.3996527000, 1.0315138000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0593714000, 0.0643623000, 0.0774420000, 0.1118940000, 0.2010871000, 0.4428123000, 1.0983376000", \ - "0.0627730000, 0.0677556000, 0.0811286000, 0.1158122000, 0.2056359000, 0.4469510000, 1.1021917000", \ - "0.0701020000, 0.0752498000, 0.0887334000, 0.1235790000, 0.2137708000, 0.4560308000, 1.1116502000", \ - "0.0850232000, 0.0908323000, 0.1056386000, 0.1411138000, 0.2324727000, 0.4766942000, 1.1306321000", \ - "0.1073408000, 0.1152864000, 0.1348971000, 0.1794193000, 0.2772967000, 0.5227947000, 1.1824479000", \ - "0.1249263000, 0.1376016000, 0.1682336000, 0.2354884000, 0.3670423000, 0.6319102000, 1.2915274000", \ - "0.1097908000, 0.1294603000, 0.1773258000, 0.2820229000, 0.4836172000, 0.8437220000, 1.5474819000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0446262000, 0.0482320000, 0.0577737000, 0.0831087000, 0.1500595000, 0.3298751000, 0.8144558000", \ - "0.0498189000, 0.0534944000, 0.0632217000, 0.0886949000, 0.1559153000, 0.3352028000, 0.8205586000", \ - "0.0630559000, 0.0667752000, 0.0764572000, 0.1021945000, 0.1696095000, 0.3498723000, 0.8350278000", \ - "0.0950714000, 0.0992030000, 0.1087697000, 0.1338568000, 0.2014245000, 0.3792080000, 0.8650367000", \ - "0.1510700000, 0.1575402000, 0.1730761000, 0.2074961000, 0.2775415000, 0.4568916000, 0.9441325000", \ - "0.2427896000, 0.2530868000, 0.2782678000, 0.3340601000, 0.4408130000, 0.6334860000, 1.1178501000", \ - "0.3967637000, 0.4125467000, 0.4518360000, 0.5403951000, 0.7132351000, 1.0115789000, 1.5262519000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0447626000, 0.0513225000, 0.0687414000, 0.1149485000, 0.2369009000, 0.5659414000, 1.4597612000", \ - "0.0448130000, 0.0512997000, 0.0688170000, 0.1150329000, 0.2372341000, 0.5660412000, 1.4604872000", \ - "0.0449667000, 0.0514579000, 0.0687910000, 0.1146885000, 0.2372846000, 0.5657912000, 1.4590450000", \ - "0.0514108000, 0.0570278000, 0.0726034000, 0.1160413000, 0.2368471000, 0.5673390000, 1.4624101000", \ - "0.0695948000, 0.0762428000, 0.0929952000, 0.1343769000, 0.2435384000, 0.5672591000, 1.4610223000", \ - "0.1124426000, 0.1207306000, 0.1414070000, 0.1890819000, 0.2965935000, 0.5853243000, 1.4607490000", \ - "0.1926787000, 0.2038079000, 0.2327659000, 0.2967858000, 0.4280296000, 0.7106910000, 1.4944931000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0395720000, 0.0443391000, 0.0566879000, 0.0908790000, 0.1838096000, 0.4373991000, 1.1252220000", \ - "0.0397237000, 0.0443159000, 0.0569370000, 0.0909342000, 0.1839105000, 0.4367506000, 1.1249736000", \ - "0.0395325000, 0.0441808000, 0.0568523000, 0.0909395000, 0.1840476000, 0.4372515000, 1.1292968000", \ - "0.0489142000, 0.0523293000, 0.0621891000, 0.0922472000, 0.1840836000, 0.4367581000, 1.1285901000", \ - "0.0793460000, 0.0836370000, 0.0939603000, 0.1173789000, 0.1924492000, 0.4371671000, 1.1288593000", \ - "0.1320204000, 0.1392265000, 0.1559316000, 0.1921253000, 0.2621166000, 0.4590708000, 1.1258130000", \ - "0.2166582000, 0.2289876000, 0.2577678000, 0.3180959000, 0.4288385000, 0.6180643000, 1.1679472000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0674150000, 0.0722635000, 0.0853935000, 0.1192886000, 0.2093923000, 0.4527355000, 1.1055075000", \ - "0.0707587000, 0.0757015000, 0.0889874000, 0.1233195000, 0.2134930000, 0.4562206000, 1.1101765000", \ - "0.0775201000, 0.0825764000, 0.0960553000, 0.1305455000, 0.2212517000, 0.4654066000, 1.1184205000", \ - "0.0903326000, 0.0957976000, 0.1098180000, 0.1447593000, 0.2362948000, 0.4781741000, 1.1344183000", \ - "0.1094312000, 0.1158276000, 0.1327754000, 0.1729008000, 0.2687066000, 0.5136738000, 1.1716386000", \ - "0.1260997000, 0.1372534000, 0.1612818000, 0.2170229000, 0.3352053000, 0.5925884000, 1.2552078000", \ - "0.1076093000, 0.1259321000, 0.1650045000, 0.2539511000, 0.4267637000, 0.7584764000, 1.4418211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0529825000, 0.0565944000, 0.0663759000, 0.0919584000, 0.1595305000, 0.3399597000, 0.8285833000", \ - "0.0584499000, 0.0620936000, 0.0718952000, 0.0976084000, 0.1652582000, 0.3463048000, 0.8340994000", \ - "0.0717647000, 0.0754658000, 0.0853509000, 0.1112350000, 0.1791476000, 0.3598074000, 0.8477277000", \ - "0.1045834000, 0.1081194000, 0.1177728000, 0.1435578000, 0.2114729000, 0.3911690000, 0.8789982000", \ - "0.1678302000, 0.1734117000, 0.1872987000, 0.2183925000, 0.2872725000, 0.4675292000, 0.9555128000", \ - "0.2719695000, 0.2809436000, 0.3032660000, 0.3540309000, 0.4547751000, 0.6450463000, 1.1292518000", \ - "0.4465446000, 0.4604113000, 0.4941473000, 0.5751197000, 0.7390422000, 1.0296229000, 1.5407540000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0449066000, 0.0512517000, 0.0688374000, 0.1146348000, 0.2371962000, 0.5682315000, 1.4584408000", \ - "0.0449098000, 0.0513481000, 0.0688936000, 0.1147779000, 0.2373270000, 0.5682546000, 1.4615270000", \ - "0.0450612000, 0.0515668000, 0.0688650000, 0.1145503000, 0.2372307000, 0.5685536000, 1.4619436000", \ - "0.0494035000, 0.0550585000, 0.0714256000, 0.1156235000, 0.2375544000, 0.5660581000, 1.4592865000", \ - "0.0619685000, 0.0681398000, 0.0848634000, 0.1280859000, 0.2418740000, 0.5670437000, 1.4607952000", \ - "0.0983008000, 0.1055254000, 0.1235929000, 0.1673794000, 0.2787428000, 0.5794987000, 1.4625349000", \ - "0.1754334000, 0.1850881000, 0.2079730000, 0.2621720000, 0.3807157000, 0.6797743000, 1.4860233000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0500273000, 0.0546240000, 0.0669874000, 0.1009572000, 0.1944938000, 0.4492437000, 1.1451742000", \ - "0.0499000000, 0.0546300000, 0.0670795000, 0.1009339000, 0.1944949000, 0.4497133000, 1.1449710000", \ - "0.0495287000, 0.0543603000, 0.0669128000, 0.1009970000, 0.1942469000, 0.4498905000, 1.1443732000", \ - "0.0550633000, 0.0589057000, 0.0698114000, 0.1014056000, 0.1944335000, 0.4498359000, 1.1449973000", \ - "0.0845465000, 0.0892497000, 0.0993377000, 0.1227542000, 0.2012242000, 0.4498148000, 1.1450190000", \ - "0.1396324000, 0.1458021000, 0.1604116000, 0.1957317000, 0.2656788000, 0.4695333000, 1.1449102000", \ - "0.2273971000, 0.2384789000, 0.2667603000, 0.3242693000, 0.4318679000, 0.6226891000, 1.1846801000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0727472000, 0.0777779000, 0.0905804000, 0.1249621000, 0.2143018000, 0.4566198000, 1.1108084000", \ - "0.0765030000, 0.0815585000, 0.0948099000, 0.1289756000, 0.2191750000, 0.4604634000, 1.1163481000", \ - "0.0838752000, 0.0889586000, 0.1023495000, 0.1371964000, 0.2274917000, 0.4691346000, 1.1247210000", \ - "0.0974197000, 0.1026249000, 0.1162906000, 0.1513188000, 0.2424721000, 0.4868098000, 1.1400469000", \ - "0.1166342000, 0.1226314000, 0.1378201000, 0.1758438000, 0.2695726000, 0.5133984000, 1.1695341000", \ - "0.1352019000, 0.1434696000, 0.1646315000, 0.2126940000, 0.3210271000, 0.5753477000, 1.2329344000", \ - "0.1228733000, 0.1358856000, 0.1692664000, 0.2445196000, 0.3954637000, 0.6957550000, 1.3802891000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0570105000, 0.0607612000, 0.0704273000, 0.0956264000, 0.1608086000, 0.3329435000, 0.7963425000", \ - "0.0623120000, 0.0660607000, 0.0757323000, 0.1009287000, 0.1661822000, 0.3387914000, 0.8023990000", \ - "0.0754077000, 0.0791770000, 0.0888597000, 0.1141234000, 0.1794410000, 0.3519969000, 0.8154011000", \ - "0.1082357000, 0.1117821000, 0.1213590000, 0.1465808000, 0.2119619000, 0.3844007000, 0.8478226000", \ - "0.1749474000, 0.1800219000, 0.1927653000, 0.2218092000, 0.2866871000, 0.4587286000, 0.9217432000", \ - "0.2836224000, 0.2906584000, 0.3100280000, 0.3569815000, 0.4524331000, 0.6338023000, 1.0950881000", \ - "0.4608872000, 0.4735293000, 0.5044785000, 0.5769711000, 0.7280523000, 1.0085107000, 1.4985256000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0447649000, 0.0514815000, 0.0687466000, 0.1148315000, 0.2370370000, 0.5662428000, 1.4580983000", \ - "0.0448213000, 0.0513644000, 0.0688646000, 0.1148419000, 0.2372272000, 0.5660413000, 1.4582789000", \ - "0.0449498000, 0.0515462000, 0.0688107000, 0.1148720000, 0.2366047000, 0.5660366000, 1.4599982000", \ - "0.0472080000, 0.0533891000, 0.0701968000, 0.1151760000, 0.2374275000, 0.5684851000, 1.4583794000", \ - "0.0560342000, 0.0624673000, 0.0794495000, 0.1235154000, 0.2401005000, 0.5661586000, 1.4614965000", \ - "0.0833502000, 0.0898217000, 0.1072495000, 0.1517741000, 0.2668133000, 0.5772752000, 1.4606902000", \ - "0.1524309000, 0.1602096000, 0.1810598000, 0.2295035000, 0.3467029000, 0.6471383000, 1.4831922000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0588457000, 0.0630493000, 0.0750380000, 0.1074130000, 0.1964548000, 0.4417913000, 1.1112180000", \ - "0.0586736000, 0.0628331000, 0.0749301000, 0.1074896000, 0.1965809000, 0.4420038000, 1.1111666000", \ - "0.0572897000, 0.0620276000, 0.0743525000, 0.1070602000, 0.1967440000, 0.4413018000, 1.1127838000", \ - "0.0609331000, 0.0648197000, 0.0758996000, 0.1069476000, 0.1962516000, 0.4416833000, 1.1098168000", \ - "0.0890096000, 0.0931301000, 0.1027477000, 0.1269393000, 0.2025311000, 0.4414211000, 1.1106912000", \ - "0.1429660000, 0.1487483000, 0.1641043000, 0.1982234000, 0.2675420000, 0.4631224000, 1.1122521000", \ - "0.2328472000, 0.2434986000, 0.2690576000, 0.3237035000, 0.4307499000, 0.6229042000, 1.1551666000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4b_4") { - leakage_power () { - value : 0.0003959000; - when : "!A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0406719000; - when : "!A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0016850000; - when : "!A_N&!B&C&D"; - } - leakage_power () { - value : 0.0003949000; - when : "!A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0016604000; - when : "!A_N&B&!C&D"; - } - leakage_power () { - value : 0.0602537000; - when : "!A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0107621000; - when : "!A_N&B&C&D"; - } - leakage_power () { - value : 0.0016603000; - when : "!A_N&B&C&!D"; - } - leakage_power () { - value : 0.0105546000; - when : "A_N&!B&!C&D"; - } - leakage_power () { - value : 0.0304875000; - when : "A_N&!B&!C&!D"; - } - leakage_power () { - value : 0.0106304000; - when : "A_N&!B&C&D"; - } - leakage_power () { - value : 0.0105558000; - when : "A_N&!B&C&!D"; - } - leakage_power () { - value : 0.0106336000; - when : "A_N&B&!C&D"; - } - leakage_power () { - value : 0.0307067000; - when : "A_N&B&!C&!D"; - } - leakage_power () { - value : 0.0123665000; - when : "A_N&B&C&D"; - } - leakage_power () { - value : 0.0106382000; - when : "A_N&B&C&!D"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__nand4b"; - cell_leakage_power : 0.0152536100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173525000, 0.0172317000, 0.0169534000, 0.0170858000, 0.0173912000, 0.0180952000, 0.0197179000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0175856000, 0.0174760000, 0.0172232000, 0.0173328000, 0.0175856000, 0.0181683000, 0.0195115000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024800000; - } - pin ("B") { - capacitance : 0.0085040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0169471000, 0.0169429000, 0.0169329000, 0.0169528000, 0.0169986000, 0.0171042000, 0.0173475000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015540200, -0.015544600, -0.015554700, -0.015523200, -0.015450300, -0.015282400, -0.014895200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087360000; - } - pin ("C") { - capacitance : 0.0086320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161104000, 0.0161101000, 0.0161094000, 0.0161715000, 0.0163147000, 0.0166448000, 0.0174056000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015802500, -0.015782200, -0.015735300, -0.015729200, -0.015715200, -0.015683000, -0.015608500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089830000; - } - pin ("D") { - capacitance : 0.0087340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157072000, 0.0157041000, 0.0156969000, 0.0156999000, 0.0157068000, 0.0157228000, 0.0157595000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015708700, -0.015698200, -0.015674200, -0.015674700, -0.015675900, -0.015678700, -0.015685000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091920000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (!B) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0253315000, 0.0237651000, 0.0192805000, 0.0054584000, -0.037290200, -0.167896300, -0.561146800", \ - "0.0252654000, 0.0237808000, 0.0191843000, 0.0055234000, -0.037264200, -0.167871700, -0.561049800", \ - "0.0253755000, 0.0236989000, 0.0192566000, 0.0054719000, -0.037314500, -0.167863200, -0.561117600", \ - "0.0248129000, 0.0233383000, 0.0188077000, 0.0048193000, -0.037952500, -0.168327600, -0.561542100", \ - "0.0240029000, 0.0224530000, 0.0178788000, 0.0038712000, -0.038837300, -0.169055400, -0.562017300", \ - "0.0235685000, 0.0220220000, 0.0173769000, 0.0033669000, -0.039580000, -0.169683000, -0.562398300", \ - "0.0249469000, 0.0238064000, 0.0177374000, 0.0034470000, -0.039477900, -0.168681900, -0.561434100"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0125918000, 0.0144238000, 0.0198429000, 0.0354397000, 0.0800787000, 0.2104518000, 0.6038223000", \ - "0.0126096000, 0.0144274000, 0.0198370000, 0.0354237000, 0.0798975000, 0.2106991000, 0.6006288000", \ - "0.0125262000, 0.0143919000, 0.0197775000, 0.0353854000, 0.0800175000, 0.2104455000, 0.6040728000", \ - "0.0118891000, 0.0136907000, 0.0190195000, 0.0346089000, 0.0793276000, 0.2104037000, 0.6019046000", \ - "0.0112396000, 0.0129826000, 0.0182404000, 0.0334539000, 0.0779118000, 0.2089305000, 0.5958062000", \ - "0.0116074000, 0.0132907000, 0.0179589000, 0.0328724000, 0.0768417000, 0.2074592000, 0.5989113000", \ - "0.0120581000, 0.0139964000, 0.0188025000, 0.0332451000, 0.0773113000, 0.2076910000, 0.5952115000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0307837000, 0.0293025000, 0.0245768000, 0.0102556000, -0.033284200, -0.164389800, -0.557846200", \ - "0.0301097000, 0.0286158000, 0.0241000000, 0.0099198000, -0.033427900, -0.164439200, -0.557900500", \ - "0.0292218000, 0.0277151000, 0.0232068000, 0.0092436000, -0.033809900, -0.164558000, -0.557909900", \ - "0.0281785000, 0.0266293000, 0.0220776000, 0.0082017000, -0.034526300, -0.164924300, -0.558072400", \ - "0.0276679000, 0.0261029000, 0.0214822000, 0.0073380000, -0.035447500, -0.165516000, -0.558346200", \ - "0.0276683000, 0.0261180000, 0.0212785000, 0.0068173000, -0.036581600, -0.166670900, -0.558931100", \ - "0.0301191000, 0.0283213000, 0.0232166000, 0.0081944000, -0.035855200, -0.167004300, -0.559924700"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0198977000, 0.0215257000, 0.0264110000, 0.0409180000, 0.0842580000, 0.2136485000, 0.6023022000", \ - "0.0191726000, 0.0208183000, 0.0258211000, 0.0405709000, 0.0842370000, 0.2140650000, 0.6020894000", \ - "0.0181017000, 0.0197978000, 0.0249487000, 0.0398110000, 0.0837291000, 0.2135677000, 0.6027380000", \ - "0.0170006000, 0.0186716000, 0.0237382000, 0.0387657000, 0.0826188000, 0.2123321000, 0.6021721000", \ - "0.0168491000, 0.0183397000, 0.0233050000, 0.0375039000, 0.0810869000, 0.2121617000, 0.6015690000", \ - "0.0174021000, 0.0189929000, 0.0237027000, 0.0381097000, 0.0817217000, 0.2122965000, 0.5985972000", \ - "0.0207590000, 0.0256807000, 0.0299666000, 0.0404487000, 0.0827583000, 0.2120782000, 0.5984618000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0312842000, 0.0297402000, 0.0250612000, 0.0106428000, -0.032951200, -0.164064000, -0.557694000", \ - "0.0305877000, 0.0290616000, 0.0245014000, 0.0102708000, -0.033122100, -0.164165800, -0.557622100", \ - "0.0295663000, 0.0280892000, 0.0235446000, 0.0095937000, -0.033546200, -0.164338200, -0.557736400", \ - "0.0285733000, 0.0270251000, 0.0224865000, 0.0086052000, -0.034194000, -0.164666200, -0.557791800", \ - "0.0281051000, 0.0265725000, 0.0219068000, 0.0078374000, -0.034981300, -0.165093800, -0.557995100", \ - "0.0285085000, 0.0269072000, 0.0221288000, 0.0072923000, -0.035755300, -0.166016700, -0.558550900", \ - "0.0299018000, 0.0281222000, 0.0231985000, 0.0084235000, -0.035387200, -0.166458100, -0.559191900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0313106000, 0.0329328000, 0.0377955000, 0.0523240000, 0.0956892000, 0.2254624000, 0.6138771000", \ - "0.0306790000, 0.0323014000, 0.0371878000, 0.0518394000, 0.0955062000, 0.2251936000, 0.6136282000", \ - "0.0296349000, 0.0312984000, 0.0362773000, 0.0510629000, 0.0949247000, 0.2250232000, 0.6133794000", \ - "0.0287258000, 0.0304039000, 0.0354195000, 0.0499360000, 0.0939500000, 0.2238550000, 0.6132370000", \ - "0.0278815000, 0.0295226000, 0.0344086000, 0.0490120000, 0.0929084000, 0.2234747000, 0.6116581000", \ - "0.0287864000, 0.0303775000, 0.0351331000, 0.0496689000, 0.0931476000, 0.2231552000, 0.6095522000", \ - "0.0313059000, 0.0328213000, 0.0374301000, 0.0512220000, 0.0939352000, 0.2228235000, 0.6096827000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0308279000, 0.0292583000, 0.0245661000, 0.0101716000, -0.033430600, -0.164670000, -0.558077900", \ - "0.0301812000, 0.0286337000, 0.0240259000, 0.0098066000, -0.033611900, -0.164663100, -0.558140900", \ - "0.0291794000, 0.0277439000, 0.0231378000, 0.0091593000, -0.034005800, -0.164809800, -0.558251300", \ - "0.0282566000, 0.0267326000, 0.0221771000, 0.0082386000, -0.034618600, -0.165135600, -0.558303100", \ - "0.0278442000, 0.0263436000, 0.0216385000, 0.0074866000, -0.035398700, -0.165550600, -0.558423600", \ - "0.0283369000, 0.0267302000, 0.0219460000, 0.0072742000, -0.036090600, -0.166336600, -0.559086800", \ - "0.0298756000, 0.0281520000, 0.0231728000, 0.0084208000, -0.035407800, -0.166679400, -0.559433300"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014999240, 0.0044995460, 0.0134979600, 0.0404918300, 0.1214694000, 0.3643898000"); - values("0.0416487000, 0.0432393000, 0.0481428000, 0.0628640000, 0.1066911000, 0.2368774000, 0.6258627000", \ - "0.0409820000, 0.0426341000, 0.0474741000, 0.0622383000, 0.1061699000, 0.2363021000, 0.6248989000", \ - "0.0401822000, 0.0418130000, 0.0467883000, 0.0615606000, 0.1056134000, 0.2361308000, 0.6247535000", \ - "0.0393422000, 0.0410035000, 0.0459371000, 0.0608182000, 0.1049592000, 0.2352186000, 0.6248913000", \ - "0.0389707000, 0.0407129000, 0.0456589000, 0.0601004000, 0.1044327000, 0.2346231000, 0.6243789000", \ - "0.0418927000, 0.0434365000, 0.0469355000, 0.0611128000, 0.1056513000, 0.2356826000, 0.6236888000", \ - "0.0457137000, 0.0472265000, 0.0520024000, 0.0658216000, 0.1090715000, 0.2383330000, 0.6248739000"); - } - } - max_capacitance : 0.3643900000; - max_transition : 1.4977150000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.1316373000, 0.1350986000, 0.1451933000, 0.1731124000, 0.2518179000, 0.4820106000, 1.1651677000", \ - "0.1366805000, 0.1401592000, 0.1502372000, 0.1782948000, 0.2564738000, 0.4863834000, 1.1705059000", \ - "0.1493562000, 0.1528317000, 0.1628811000, 0.1909168000, 0.2694741000, 0.4992331000, 1.1827481000", \ - "0.1790705000, 0.1825694000, 0.1925295000, 0.2205046000, 0.2990532000, 0.5294034000, 1.2129313000", \ - "0.2459768000, 0.2494701000, 0.2594796000, 0.2873196000, 0.3657808000, 0.5958352000, 1.2847121000", \ - "0.3559739000, 0.3599414000, 0.3712801000, 0.4005351000, 0.4798187000, 0.7090736000, 1.3957845000", \ - "0.5174426000, 0.5224827000, 0.5352067000, 0.5697405000, 0.6512270000, 0.8815329000, 1.5650513000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0944386000, 0.0971363000, 0.1047374000, 0.1255054000, 0.1819055000, 0.3447631000, 0.8310987000", \ - "0.0990464000, 0.1017473000, 0.1094233000, 0.1300911000, 0.1863250000, 0.3492347000, 0.8367187000", \ - "0.1105630000, 0.1132616000, 0.1208612000, 0.1416149000, 0.1980652000, 0.3615560000, 0.8464643000", \ - "0.1368516000, 0.1395315000, 0.1470582000, 0.1676242000, 0.2240601000, 0.3879866000, 0.8748853000", \ - "0.1851386000, 0.1879190000, 0.1957417000, 0.2167183000, 0.2732243000, 0.4372989000, 0.9225876000", \ - "0.2504926000, 0.2537021000, 0.2625276000, 0.2851366000, 0.3424980000, 0.5065949000, 0.9910995000", \ - "0.3278555000, 0.3324565000, 0.3437863000, 0.3710356000, 0.4320897000, 0.5950507000, 1.0818699000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0508424000, 0.0549135000, 0.0671208000, 0.1021094000, 0.2060961000, 0.5205003000, 1.4617714000", \ - "0.0509239000, 0.0550104000, 0.0672066000, 0.1021005000, 0.2059238000, 0.5214187000, 1.4636898000", \ - "0.0509363000, 0.0550733000, 0.0672390000, 0.1021340000, 0.2059705000, 0.5210942000, 1.4613686000", \ - "0.0511002000, 0.0551525000, 0.0672328000, 0.1021450000, 0.2061179000, 0.5205544000, 1.4602346000", \ - "0.0527733000, 0.0566924000, 0.0685994000, 0.1029133000, 0.2060157000, 0.5208193000, 1.4646557000", \ - "0.0625104000, 0.0663076000, 0.0776422000, 0.1104603000, 0.2098906000, 0.5203952000, 1.4617888000", \ - "0.0835338000, 0.0870385000, 0.0976413000, 0.1280651000, 0.2202912000, 0.5232884000, 1.4627279000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0346482000, 0.0371246000, 0.0449921000, 0.0691488000, 0.1443484000, 0.3744123000, 1.0691648000", \ - "0.0346444000, 0.0372347000, 0.0450578000, 0.0690963000, 0.1441751000, 0.3751819000, 1.0698274000", \ - "0.0347120000, 0.0371962000, 0.0450095000, 0.0691385000, 0.1442711000, 0.3739711000, 1.0691592000", \ - "0.0350050000, 0.0375150000, 0.0452121000, 0.0692320000, 0.1442984000, 0.3742308000, 1.0680457000", \ - "0.0394556000, 0.0417469000, 0.0489058000, 0.0720124000, 0.1447789000, 0.3735811000, 1.0605499000", \ - "0.0504003000, 0.0525648000, 0.0600044000, 0.0796904000, 0.1483532000, 0.3732164000, 1.0684000000", \ - "0.0701560000, 0.0731961000, 0.0788633000, 0.0984077000, 0.1585870000, 0.3771045000, 1.0600042000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0600948000, 0.0633855000, 0.0725272000, 0.0988444000, 0.1762017000, 0.4039716000, 1.0879418000", \ - "0.0631673000, 0.0663711000, 0.0759434000, 0.1024641000, 0.1801673000, 0.4082897000, 1.0992316000", \ - "0.0700404000, 0.0732222000, 0.0827966000, 0.1101039000, 0.1878796000, 0.4192643000, 1.1004821000", \ - "0.0835400000, 0.0872918000, 0.0979312000, 0.1262306000, 0.2058959000, 0.4350542000, 1.1194852000", \ - "0.1035333000, 0.1085898000, 0.1230748000, 0.1593655000, 0.2474959000, 0.4802385000, 1.1656830000", \ - "0.1173365000, 0.1253753000, 0.1473637000, 0.2024528000, 0.3238907000, 0.5828940000, 1.2726467000", \ - "0.0937562000, 0.1060841000, 0.1404411000, 0.2267663000, 0.4135040000, 0.7754244000, 1.5177499000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0477010000, 0.0500908000, 0.0573622000, 0.0782041000, 0.1389054000, 0.3178106000, 0.8523370000", \ - "0.0528399000, 0.0554124000, 0.0626917000, 0.0838930000, 0.1448376000, 0.3245026000, 0.8612197000", \ - "0.0659275000, 0.0683840000, 0.0757261000, 0.0969891000, 0.1584356000, 0.3382388000, 0.8718383000", \ - "0.0980164000, 0.1006640000, 0.1079229000, 0.1287494000, 0.1888261000, 0.3684856000, 0.9032645000", \ - "0.1555665000, 0.1596914000, 0.1710797000, 0.2003335000, 0.2653523000, 0.4447799000, 0.9778921000", \ - "0.2506663000, 0.2572975000, 0.2757122000, 0.3218585000, 0.4236470000, 0.6197149000, 1.1519183000", \ - "0.4121503000, 0.4220624000, 0.4506025000, 0.5223844000, 0.6854315000, 0.9933860000, 1.5614199000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0472734000, 0.0515457000, 0.0636621000, 0.0997342000, 0.2054593000, 0.5195624000, 1.4612026000", \ - "0.0472975000, 0.0514284000, 0.0638676000, 0.0996153000, 0.2056502000, 0.5203252000, 1.4654954000", \ - "0.0475387000, 0.0516639000, 0.0639301000, 0.0999549000, 0.2058761000, 0.5220380000, 1.4612046000", \ - "0.0542101000, 0.0579260000, 0.0685043000, 0.1021664000, 0.2059522000, 0.5200360000, 1.4623465000", \ - "0.0723386000, 0.0764899000, 0.0883944000, 0.1221186000, 0.2149478000, 0.5212399000, 1.4629031000", \ - "0.1155140000, 0.1205562000, 0.1350910000, 0.1738674000, 0.2697490000, 0.5432476000, 1.4601141000", \ - "0.1967374000, 0.2038838000, 0.2243376000, 0.2762731000, 0.3954499000, 0.6784527000, 1.4977153000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0428053000, 0.0458657000, 0.0553075000, 0.0826730000, 0.1664331000, 0.4180367000, 1.1735427000", \ - "0.0430643000, 0.0461307000, 0.0552961000, 0.0829064000, 0.1663018000, 0.4181328000, 1.1739173000", \ - "0.0427698000, 0.0459024000, 0.0552644000, 0.0828846000, 0.1664335000, 0.4174344000, 1.1718903000", \ - "0.0508797000, 0.0531843000, 0.0606103000, 0.0848991000, 0.1664483000, 0.4184067000, 1.1724401000", \ - "0.0816343000, 0.0845380000, 0.0925688000, 0.1115134000, 0.1771795000, 0.4173476000, 1.1739150000", \ - "0.1337967000, 0.1383055000, 0.1509399000, 0.1824041000, 0.2495762000, 0.4407866000, 1.1753984000", \ - "0.2188382000, 0.2257926000, 0.2475661000, 0.3003859000, 0.4051514000, 0.6054389000, 1.2104360000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0699235000, 0.0729505000, 0.0821198000, 0.1085678000, 0.1851953000, 0.4133089000, 1.1019632000", \ - "0.0730256000, 0.0761478000, 0.0856663000, 0.1122947000, 0.1892252000, 0.4176576000, 1.1023664000", \ - "0.0796376000, 0.0828017000, 0.0923114000, 0.1195257000, 0.1972395000, 0.4284842000, 1.1097659000", \ - "0.0917349000, 0.0952217000, 0.1051754000, 0.1327942000, 0.2109624000, 0.4407297000, 1.1244683000", \ - "0.1088344000, 0.1132518000, 0.1250551000, 0.1575040000, 0.2417171000, 0.4724587000, 1.1634811000", \ - "0.1222702000, 0.1286753000, 0.1470818000, 0.1927251000, 0.2986525000, 0.5480302000, 1.2351848000", \ - "0.0956967000, 0.1064965000, 0.1358451000, 0.2088434000, 0.3687109000, 0.6923108000, 1.4165994000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0590119000, 0.0613651000, 0.0687209000, 0.0897510000, 0.1508855000, 0.3304286000, 0.8661720000", \ - "0.0642260000, 0.0666972000, 0.0740399000, 0.0952192000, 0.1564714000, 0.3359973000, 0.8713516000", \ - "0.0772174000, 0.0797270000, 0.0871003000, 0.1085362000, 0.1700639000, 0.3503207000, 0.8853473000", \ - "0.1094229000, 0.1118268000, 0.1189895000, 0.1399189000, 0.2020989000, 0.3803762000, 0.9157540000", \ - "0.1744916000, 0.1780290000, 0.1881802000, 0.2143943000, 0.2772099000, 0.4571786000, 0.9892461000", \ - "0.2822765000, 0.2880615000, 0.3042217000, 0.3463515000, 0.4397905000, 0.6328782000, 1.1651745000", \ - "0.4636513000, 0.4723719000, 0.4970208000, 0.5625126000, 0.7131796000, 1.0094230000, 1.5733432000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0473161000, 0.0514047000, 0.0638784000, 0.0999989000, 0.2051367000, 0.5201918000, 1.4648115000", \ - "0.0473525000, 0.0514639000, 0.0639310000, 0.0997455000, 0.2058096000, 0.5206992000, 1.4653754000", \ - "0.0474766000, 0.0516239000, 0.0637518000, 0.0999827000, 0.2056092000, 0.5221641000, 1.4617554000", \ - "0.0517130000, 0.0555292000, 0.0668269000, 0.1011352000, 0.2055060000, 0.5200451000, 1.4610623000", \ - "0.0648631000, 0.0685211000, 0.0801584000, 0.1145826000, 0.2120238000, 0.5198469000, 1.4639195000", \ - "0.1017058000, 0.1060604000, 0.1190549000, 0.1541148000, 0.2512941000, 0.5354810000, 1.4617697000", \ - "0.1803107000, 0.1859639000, 0.2025545000, 0.2455342000, 0.3523539000, 0.6349059000, 1.4864174000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0547018000, 0.0579649000, 0.0669455000, 0.0946384000, 0.1788545000, 0.4327056000, 1.1995912000", \ - "0.0548917000, 0.0579041000, 0.0670156000, 0.0946579000, 0.1787740000, 0.4329205000, 1.1997180000", \ - "0.0545033000, 0.0576258000, 0.0668948000, 0.0945555000, 0.1784822000, 0.4339159000, 1.2015782000", \ - "0.0586244000, 0.0613086000, 0.0695091000, 0.0953706000, 0.1787878000, 0.4329717000, 1.1993375000", \ - "0.0869997000, 0.0896886000, 0.0974809000, 0.1171448000, 0.1864546000, 0.4340832000, 1.1986019000", \ - "0.1406310000, 0.1449011000, 0.1566974000, 0.1872472000, 0.2536410000, 0.4558660000, 1.1996731000", \ - "0.2309388000, 0.2380660000, 0.2577326000, 0.3059605000, 0.4101372000, 0.6114426000, 1.2340053000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0743834000, 0.0774103000, 0.0865444000, 0.1127059000, 0.1898494000, 0.4192246000, 1.1028254000", \ - "0.0777406000, 0.0808119000, 0.0900429000, 0.1166026000, 0.1941264000, 0.4219917000, 1.1060427000", \ - "0.0841820000, 0.0875332000, 0.0969109000, 0.1240858000, 0.2014787000, 0.4310553000, 1.1137984000", \ - "0.0959934000, 0.0993352000, 0.1089738000, 0.1363576000, 0.2148944000, 0.4437118000, 1.1277491000", \ - "0.1118708000, 0.1156287000, 0.1265048000, 0.1562626000, 0.2382637000, 0.4692442000, 1.1540905000", \ - "0.1248102000, 0.1299409000, 0.1447836000, 0.1827783000, 0.2779972000, 0.5224484000, 1.2108572000", \ - "0.1009186000, 0.1094493000, 0.1336176000, 0.1940125000, 0.3301029000, 0.6202087000, 1.3366821000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0598642000, 0.0621142000, 0.0690628000, 0.0890310000, 0.1456702000, 0.3097725000, 0.7942006000", \ - "0.0650806000, 0.0674916000, 0.0743415000, 0.0943069000, 0.1509636000, 0.3149792000, 0.8005923000", \ - "0.0780809000, 0.0803957000, 0.0873450000, 0.1073649000, 0.1641675000, 0.3284570000, 0.8129910000", \ - "0.1105084000, 0.1127849000, 0.1195976000, 0.1395103000, 0.1963932000, 0.3604685000, 0.8463659000", \ - "0.1773335000, 0.1805262000, 0.1896460000, 0.2128639000, 0.2711265000, 0.4350657000, 0.9216156000", \ - "0.2875984000, 0.2924795000, 0.3044587000, 0.3424941000, 0.4292654000, 0.6075406000, 1.0909976000", \ - "0.4684481000, 0.4759643000, 0.4966491000, 0.5532220000, 0.6930420000, 0.9697536000, 1.4938660000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0473442000, 0.0514611000, 0.0636660000, 0.0996604000, 0.2058805000, 0.5215563000, 1.4626897000", \ - "0.0473324000, 0.0514995000, 0.0637453000, 0.0996316000, 0.2055435000, 0.5196759000, 1.4628206000", \ - "0.0474734000, 0.0516869000, 0.0637358000, 0.0999923000, 0.2059371000, 0.5216715000, 1.4616660000", \ - "0.0498075000, 0.0537091000, 0.0654633000, 0.1004369000, 0.2056958000, 0.5202182000, 1.4613324000", \ - "0.0583966000, 0.0625128000, 0.0744006000, 0.1093237000, 0.2096927000, 0.5215356000, 1.4616768000", \ - "0.0856118000, 0.0894757000, 0.1016292000, 0.1355290000, 0.2361264000, 0.5326798000, 1.4634932000", \ - "0.1553269000, 0.1600331000, 0.1737283000, 0.2115843000, 0.3129938000, 0.5999666000, 1.4853687000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014999200, 0.0044995500, 0.0134980000, 0.0404918000, 0.1214690000, 0.3643900000"); - values("0.0618360000, 0.0646155000, 0.0730282000, 0.0982797000, 0.1752953000, 0.4095033000, 1.1166397000", \ - "0.0614405000, 0.0643516000, 0.0727947000, 0.0981301000, 0.1752962000, 0.4097994000, 1.1170652000", \ - "0.0604222000, 0.0634200000, 0.0720720000, 0.0977075000, 0.1750792000, 0.4095007000, 1.1167398000", \ - "0.0635751000, 0.0660265000, 0.0738323000, 0.0978404000, 0.1748568000, 0.4099589000, 1.1194179000", \ - "0.0909299000, 0.0937816000, 0.1010750000, 0.1196249000, 0.1834974000, 0.4092122000, 1.1176270000", \ - "0.1443408000, 0.1483411000, 0.1609267000, 0.1874481000, 0.2537322000, 0.4361940000, 1.1163366000", \ - "0.2341960000, 0.2406907000, 0.2577422000, 0.3041306000, 0.4055563000, 0.5994975000, 1.1634018000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4bb_1") { - leakage_power () { - value : 0.0010409000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0007156000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0060269000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0010006000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0010715000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0010520000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0013883000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0010685000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0019236000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0019047000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0022168000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0019207000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0022628000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0022564000; - when : "A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0022798000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0022619000; - when : "A_N&B_N&C&!D"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__nand4bb"; - cell_leakage_power : 0.0018994410; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014800000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087580000, 0.0086485000, 0.0083960000, 0.0084467000, 0.0085635000, 0.0088328000, 0.0094536000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053563000, 0.0052833000, 0.0051150000, 0.0051527000, 0.0052396000, 0.0054398000, 0.0059014000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016080000; - } - pin ("B_N") { - capacitance : 0.0014960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0074101000, 0.0073143000, 0.0070934000, 0.0071394000, 0.0072455000, 0.0074900000, 0.0080535000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042918000, 0.0042319000, 0.0040941000, 0.0041343000, 0.0042270000, 0.0044406000, 0.0049330000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015560000; - } - pin ("C") { - capacitance : 0.0022900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045349000, 0.0045349000, 0.0045349000, 0.0045372000, 0.0045424000, 0.0045544000, 0.0045821000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004207700, -0.004207600, -0.004207400, -0.004203400, -0.004194100, -0.004172900, -0.004123800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023750000; - } - pin ("D") { - capacitance : 0.0023130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040487000, 0.0040484000, 0.0040476000, 0.0040493000, 0.0040533000, 0.0040624000, 0.0040834000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004044300, -0.004042900, -0.004039800, -0.004040400, -0.004041700, -0.004044800, -0.004051900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (B_N) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0059668000, 0.0048483000, 0.0019983000, -0.005413400, -0.024411000, -0.072349700, -0.192639000", \ - "0.0059163000, 0.0047864000, 0.0019482000, -0.005465000, -0.024450000, -0.072377600, -0.192727800", \ - "0.0059571000, 0.0048389000, 0.0019789000, -0.005440800, -0.024414300, -0.072348200, -0.192644800", \ - "0.0057517000, 0.0046089000, 0.0017028000, -0.005696000, -0.024659200, -0.072524900, -0.192793600", \ - "0.0054173000, 0.0042826000, 0.0013795000, -0.006025400, -0.024945400, -0.072787200, -0.193009100", \ - "0.0051177000, 0.0040265000, 0.0011834000, -0.006278500, -0.025188000, -0.072958500, -0.193126100", \ - "0.0057280000, 0.0045776000, 0.0012955000, -0.006204700, -0.024974400, -0.072685000, -0.192832000"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0039845000, 0.0053144000, 0.0085491000, 0.0163271000, 0.0354305000, 0.0834184000, 0.2030039000", \ - "0.0039722000, 0.0053060000, 0.0085461000, 0.0163275000, 0.0354368000, 0.0830809000, 0.2024313000", \ - "0.0039413000, 0.0052726000, 0.0085038000, 0.0163096000, 0.0354260000, 0.0830515000, 0.2019326000", \ - "0.0036036000, 0.0049114000, 0.0081184000, 0.0159669000, 0.0351833000, 0.0826208000, 0.2020915000", \ - "0.0032389000, 0.0045258000, 0.0076802000, 0.0154770000, 0.0349241000, 0.0826353000, 0.2016494000", \ - "0.0032961000, 0.0045398000, 0.0076970000, 0.0152458000, 0.0345828000, 0.0820561000, 0.2015830000", \ - "0.0036287000, 0.0048410000, 0.0078597000, 0.0156506000, 0.0348652000, 0.0827221000, 0.2003165000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0094208000, 0.0083045000, 0.0054246000, -0.002016000, -0.021033100, -0.068980800, -0.189261800", \ - "0.0093597000, 0.0082341000, 0.0053523000, -0.002080400, -0.021084300, -0.069044700, -0.189326000", \ - "0.0094172000, 0.0082945000, 0.0054080000, -0.002029900, -0.021037900, -0.068983700, -0.189261100", \ - "0.0092247000, 0.0080851000, 0.0051982000, -0.002251500, -0.021213800, -0.069161200, -0.189388600", \ - "0.0089378000, 0.0077986000, 0.0048891000, -0.002551400, -0.021497000, -0.069354200, -0.189577800", \ - "0.0086729000, 0.0075587000, 0.0046806000, -0.002777200, -0.021715200, -0.069493700, -0.189707300", \ - "0.0088289000, 0.0076718000, 0.0047614000, -0.002778700, -0.021624400, -0.069318300, -0.189441100"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0055085000, 0.0067614000, 0.0098676000, 0.0174732000, 0.0364972000, 0.0837546000, 0.2023781000", \ - "0.0055133000, 0.0067626000, 0.0098658000, 0.0175248000, 0.0364651000, 0.0837334000, 0.2023525000", \ - "0.0054789000, 0.0067321000, 0.0098377000, 0.0175088000, 0.0364560000, 0.0836882000, 0.2024381000", \ - "0.0051240000, 0.0063633000, 0.0094896000, 0.0171839000, 0.0362349000, 0.0836918000, 0.2021390000", \ - "0.0048088000, 0.0060818000, 0.0092023000, 0.0168516000, 0.0359247000, 0.0834233000, 0.2021444000", \ - "0.0048212000, 0.0060730000, 0.0091083000, 0.0166578000, 0.0358000000, 0.0833007000, 0.2018744000", \ - "0.0050322000, 0.0062807000, 0.0092341000, 0.0168890000, 0.0359781000, 0.0834922000, 0.2019145000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0098400000, 0.0086910000, 0.0056913000, -0.001891200, -0.021028100, -0.069037700, -0.189322300", \ - "0.0097007000, 0.0085378000, 0.0055942000, -0.001948200, -0.021060800, -0.069051200, -0.189345000", \ - "0.0094616000, 0.0083323000, 0.0054167000, -0.002068600, -0.021108200, -0.069074500, -0.189355400", \ - "0.0092129000, 0.0080629000, 0.0051622000, -0.002271400, -0.021246600, -0.069144200, -0.189389800", \ - "0.0090654000, 0.0078812000, 0.0049925000, -0.002471900, -0.021413400, -0.069227100, -0.189451100", \ - "0.0092698000, 0.0080653000, 0.0050289000, -0.002711500, -0.021673700, -0.069449600, -0.189599700", \ - "0.0098443000, 0.0085633000, 0.0054392000, -0.002306600, -0.021540000, -0.069580000, -0.189712800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0064101000, 0.0076205000, 0.0106524000, 0.0182406000, 0.0372601000, 0.0845910000, 0.2032388000", \ - "0.0062012000, 0.0074322000, 0.0104952000, 0.0181458000, 0.0371117000, 0.0844899000, 0.2031295000", \ - "0.0060160000, 0.0072563000, 0.0103471000, 0.0180253000, 0.0370267000, 0.0842333000, 0.2031018000", \ - "0.0058228000, 0.0070547000, 0.0101500000, 0.0178380000, 0.0366828000, 0.0841184000, 0.2025343000", \ - "0.0057203000, 0.0069367000, 0.0099567000, 0.0175657000, 0.0366209000, 0.0839117000, 0.2022515000", \ - "0.0064283000, 0.0076929000, 0.0106924000, 0.0182731000, 0.0370169000, 0.0843627000, 0.2031106000", \ - "0.0073376000, 0.0084223000, 0.0113166000, 0.0186063000, 0.0375021000, 0.0843491000, 0.2025823000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0099821000, 0.0087928000, 0.0058182000, -0.001767300, -0.020911800, -0.068933900, -0.189219400", \ - "0.0098036000, 0.0086750000, 0.0057149000, -0.001834500, -0.020926800, -0.068927800, -0.189220400", \ - "0.0095735000, 0.0084480000, 0.0055258000, -0.001959100, -0.020989900, -0.068966900, -0.189220000", \ - "0.0093281000, 0.0081735000, 0.0052815000, -0.002162700, -0.021119000, -0.069022600, -0.189277600", \ - "0.0092330000, 0.0080204000, 0.0051267000, -0.002363600, -0.021316800, -0.069099900, -0.189345100", \ - "0.0093855000, 0.0081756000, 0.0051518000, -0.002579200, -0.021532200, -0.069352400, -0.189434800", \ - "0.0099595000, 0.0086637000, 0.0055613000, -0.002166400, -0.021372100, -0.069384900, -0.189553600"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012526080, 0.0031380510, 0.0078614930, 0.0196947300, 0.0493395400, 0.1236061000"); - values("0.0090010000, 0.0102279000, 0.0132728000, 0.0209066000, 0.0398787000, 0.0873785000, 0.2060541000", \ - "0.0088513000, 0.0100682000, 0.0131196000, 0.0207811000, 0.0397957000, 0.0874383000, 0.2059784000", \ - "0.0086683000, 0.0099010000, 0.0129671000, 0.0206440000, 0.0396629000, 0.0873017000, 0.2059071000", \ - "0.0085016000, 0.0097198000, 0.0128102000, 0.0204757000, 0.0395206000, 0.0870499000, 0.2056639000", \ - "0.0084797000, 0.0096945000, 0.0127637000, 0.0203754000, 0.0391544000, 0.0865979000, 0.2050166000", \ - "0.0089265000, 0.0101114000, 0.0130985000, 0.0206928000, 0.0394458000, 0.0867799000, 0.2048318000", \ - "0.0104358000, 0.0116022000, 0.0144834000, 0.0216812000, 0.0409918000, 0.0874203000, 0.2053153000"); - } - } - max_capacitance : 0.1236060000; - max_transition : 1.4914760000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.1283473000, 0.1361495000, 0.1544717000, 0.1971018000, 0.2996026000, 0.5543778000, 1.1910574000", \ - "0.1330462000, 0.1408147000, 0.1592294000, 0.2017758000, 0.3042369000, 0.5593109000, 1.1955916000", \ - "0.1451874000, 0.1530724000, 0.1714066000, 0.2140013000, 0.3167075000, 0.5711659000, 1.2082446000", \ - "0.1761459000, 0.1839478000, 0.2022600000, 0.2448250000, 0.3476871000, 0.6044265000, 1.2393475000", \ - "0.2443949000, 0.2523106000, 0.2707153000, 0.3134535000, 0.4160709000, 0.6712433000, 1.3115518000", \ - "0.3582740000, 0.3671195000, 0.3870795000, 0.4312228000, 0.5350216000, 0.7904730000, 1.4297005000", \ - "0.5331178000, 0.5440172000, 0.5680007000, 0.6167802000, 0.7217631000, 0.9757233000, 1.6134812000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0740475000, 0.0802151000, 0.0948988000, 0.1295855000, 0.2148874000, 0.4260788000, 0.9543887000", \ - "0.0788227000, 0.0849691000, 0.0996820000, 0.1344111000, 0.2196832000, 0.4313744000, 0.9629022000", \ - "0.0901317000, 0.0962717000, 0.1109590000, 0.1458338000, 0.2310127000, 0.4435689000, 0.9704573000", \ - "0.1136485000, 0.1197732000, 0.1343885000, 0.1692758000, 0.2549460000, 0.4668524000, 0.9960066000", \ - "0.1482070000, 0.1546197000, 0.1695123000, 0.2049267000, 0.2901775000, 0.5030266000, 1.0310183000", \ - "0.1922752000, 0.1993686000, 0.2151019000, 0.2499746000, 0.3360365000, 0.5479594000, 1.0784929000", \ - "0.2321275000, 0.2413456000, 0.2603248000, 0.2986039000, 0.3830559000, 0.5952944000, 1.1251602000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0466805000, 0.0556658000, 0.0769448000, 0.1301270000, 0.2659960000, 0.6067719000, 1.4622875000", \ - "0.0466697000, 0.0555128000, 0.0770001000, 0.1303570000, 0.2657364000, 0.6066120000, 1.4589867000", \ - "0.0469369000, 0.0555868000, 0.0769056000, 0.1303854000, 0.2661655000, 0.6059976000, 1.4602093000", \ - "0.0469259000, 0.0557769000, 0.0769762000, 0.1300942000, 0.2662704000, 0.6091032000, 1.4606512000", \ - "0.0489415000, 0.0575928000, 0.0783633000, 0.1306478000, 0.2658250000, 0.6072725000, 1.4636088000", \ - "0.0585150000, 0.0671550000, 0.0866816000, 0.1364256000, 0.2677280000, 0.6060457000, 1.4631623000", \ - "0.0771436000, 0.0859813000, 0.1036432000, 0.1505099000, 0.2738187000, 0.6081271000, 1.4626457000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0341025000, 0.0413809000, 0.0599785000, 0.1072630000, 0.2275955000, 0.5275353000, 1.2809650000", \ - "0.0341347000, 0.0413564000, 0.0600314000, 0.1073229000, 0.2269098000, 0.5260538000, 1.2825873000", \ - "0.0342021000, 0.0414312000, 0.0598491000, 0.1069952000, 0.2276573000, 0.5300311000, 1.2728073000", \ - "0.0350382000, 0.0420380000, 0.0603113000, 0.1073490000, 0.2271087000, 0.5255543000, 1.2821454000", \ - "0.0386499000, 0.0451926000, 0.0625421000, 0.1083752000, 0.2268255000, 0.5262586000, 1.2727468000", \ - "0.0470944000, 0.0528478000, 0.0679232000, 0.1109268000, 0.2277054000, 0.5238644000, 1.2768212000", \ - "0.0644054000, 0.0698955000, 0.0854193000, 0.1208130000, 0.2305546000, 0.5291677000, 1.2728094000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.1396916000, 0.1475760000, 0.1662847000, 0.2095962000, 0.3127540000, 0.5673906000, 1.2046547000", \ - "0.1442084000, 0.1523426000, 0.1710520000, 0.2142885000, 0.3174301000, 0.5730040000, 1.2088924000", \ - "0.1572900000, 0.1651804000, 0.1838856000, 0.2271918000, 0.3305401000, 0.5862791000, 1.2218577000", \ - "0.1889125000, 0.1968550000, 0.2153992000, 0.2586835000, 0.3621103000, 0.6180231000, 1.2534991000", \ - "0.2595714000, 0.2676177000, 0.2863493000, 0.3297797000, 0.4334058000, 0.6886354000, 1.3334573000", \ - "0.3811191000, 0.3896073000, 0.4095482000, 0.4543068000, 0.5587592000, 0.8144354000, 1.4515673000", \ - "0.5741809000, 0.5850788000, 0.6081687000, 0.6556600000, 0.7622232000, 1.0189102000, 1.6569358000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0821883000, 0.0882349000, 0.1029384000, 0.1384720000, 0.2262436000, 0.4435764000, 0.9893761000", \ - "0.0869667000, 0.0929955000, 0.1076953000, 0.1433660000, 0.2307052000, 0.4481722000, 0.9931175000", \ - "0.0981915000, 0.1042504000, 0.1190162000, 0.1548129000, 0.2423889000, 0.4602300000, 1.0035422000", \ - "0.1209156000, 0.1268508000, 0.1416580000, 0.1776087000, 0.2653442000, 0.4829645000, 1.0265608000", \ - "0.1534170000, 0.1595769000, 0.1745530000, 0.2105984000, 0.2989964000, 0.5166035000, 1.0603391000", \ - "0.1930827000, 0.1995255000, 0.2144770000, 0.2504156000, 0.3387333000, 0.5564954000, 1.1001449000", \ - "0.2249802000, 0.2326879000, 0.2493457000, 0.2863467000, 0.3735541000, 0.5914277000, 1.1399079000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0472847000, 0.0559891000, 0.0776172000, 0.1311103000, 0.2663447000, 0.6064383000, 1.4582129000", \ - "0.0473243000, 0.0559905000, 0.0776837000, 0.1311488000, 0.2660022000, 0.6063146000, 1.4594003000", \ - "0.0472600000, 0.0561050000, 0.0776341000, 0.1312345000, 0.2661100000, 0.6070616000, 1.4584652000", \ - "0.0473018000, 0.0561919000, 0.0776571000, 0.1312898000, 0.2666616000, 0.6070847000, 1.4584228000", \ - "0.0483548000, 0.0570237000, 0.0784061000, 0.1314565000, 0.2665191000, 0.6071895000, 1.4624933000", \ - "0.0545419000, 0.0626381000, 0.0831956000, 0.1347825000, 0.2671122000, 0.6076760000, 1.4577828000", \ - "0.0692885000, 0.0773168000, 0.0966262000, 0.1439229000, 0.2716095000, 0.6073612000, 1.4628208000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0431788000, 0.0510306000, 0.0699690000, 0.1182632000, 0.2406737000, 0.5457935000, 1.3136502000", \ - "0.0431617000, 0.0508905000, 0.0700008000, 0.1184065000, 0.2404366000, 0.5468255000, 1.3164125000", \ - "0.0431898000, 0.0507857000, 0.0698948000, 0.1184518000, 0.2401823000, 0.5466332000, 1.3132521000", \ - "0.0438500000, 0.0512470000, 0.0702151000, 0.1183446000, 0.2406582000, 0.5458017000, 1.3128125000", \ - "0.0460202000, 0.0531704000, 0.0717925000, 0.1193247000, 0.2406086000, 0.5458540000, 1.3123600000", \ - "0.0521341000, 0.0585501000, 0.0757019000, 0.1211439000, 0.2418557000, 0.5470697000, 1.3126229000", \ - "0.0671184000, 0.0729898000, 0.0883748000, 0.1286193000, 0.2434166000, 0.5479768000, 1.3131106000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0603608000, 0.0675677000, 0.0848571000, 0.1264042000, 0.2287415000, 0.4836335000, 1.1191439000", \ - "0.0639769000, 0.0711105000, 0.0885948000, 0.1304655000, 0.2326073000, 0.4872942000, 1.1235441000", \ - "0.0708470000, 0.0780380000, 0.0956715000, 0.1380198000, 0.2402859000, 0.4949061000, 1.1344955000", \ - "0.0838354000, 0.0916887000, 0.1101177000, 0.1526547000, 0.2556970000, 0.5116728000, 1.1481458000", \ - "0.1033509000, 0.1133389000, 0.1361534000, 0.1853479000, 0.2919870000, 0.5486644000, 1.1852644000", \ - "0.1190220000, 0.1346345000, 0.1687243000, 0.2367437000, 0.3687461000, 0.6350737000, 1.2738268000", \ - "0.1000704000, 0.1251944000, 0.1797823000, 0.2862512000, 0.4756550000, 0.8195396000, 1.4820518000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0530824000, 0.0590919000, 0.0740594000, 0.1102462000, 0.1991717000, 0.4194931000, 0.9691896000", \ - "0.0582892000, 0.0644834000, 0.0794520000, 0.1157923000, 0.2047202000, 0.4255129000, 0.9746639000", \ - "0.0716846000, 0.0777538000, 0.0928750000, 0.1292415000, 0.2185177000, 0.4382212000, 0.9877961000", \ - "0.1044780000, 0.1103242000, 0.1249642000, 0.1610349000, 0.2491576000, 0.4692589000, 1.0193687000", \ - "0.1676825000, 0.1766710000, 0.1969403000, 0.2376355000, 0.3260451000, 0.5425529000, 1.0921205000", \ - "0.2704848000, 0.2850653000, 0.3174107000, 0.3820860000, 0.4982704000, 0.7187343000, 1.2649309000", \ - "0.4420564000, 0.4634152000, 0.5140031000, 0.6175658000, 0.8085967000, 1.1197718000, 1.6754299000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0433957000, 0.0525548000, 0.0750655000, 0.1298484000, 0.2662679000, 0.6072201000, 1.4579529000", \ - "0.0433897000, 0.0524949000, 0.0747884000, 0.1298462000, 0.2657130000, 0.6067027000, 1.4589008000", \ - "0.0435972000, 0.0526287000, 0.0750640000, 0.1298860000, 0.2664207000, 0.6062209000, 1.4647523000", \ - "0.0484173000, 0.0565856000, 0.0771985000, 0.1305323000, 0.2668170000, 0.6071619000, 1.4598812000", \ - "0.0635450000, 0.0723702000, 0.0932916000, 0.1431016000, 0.2703741000, 0.6066479000, 1.4584016000", \ - "0.1024008000, 0.1126462000, 0.1359637000, 0.1874846000, 0.3096442000, 0.6192283000, 1.4590938000", \ - "0.1806135000, 0.1938466000, 0.2245812000, 0.2897588000, 0.4207371000, 0.7249136000, 1.4869176000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0503403000, 0.0582942000, 0.0778383000, 0.1270704000, 0.2505360000, 0.5599394000, 1.3351497000", \ - "0.0504048000, 0.0581795000, 0.0778171000, 0.1270793000, 0.2500979000, 0.5603528000, 1.3359107000", \ - "0.0499823000, 0.0581858000, 0.0777392000, 0.1270750000, 0.2503559000, 0.5600675000, 1.3359761000", \ - "0.0561755000, 0.0627073000, 0.0800617000, 0.1269262000, 0.2503804000, 0.5598418000, 1.3342824000", \ - "0.0866639000, 0.0933284000, 0.1077309000, 0.1442428000, 0.2528390000, 0.5602249000, 1.3392960000", \ - "0.1429339000, 0.1533726000, 0.1757072000, 0.2214939000, 0.3082253000, 0.5722939000, 1.3359163000", \ - "0.2325713000, 0.2501127000, 0.2873434000, 0.3615309000, 0.4867104000, 0.7040027000, 1.3551952000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0652119000, 0.0723206000, 0.0896689000, 0.1313004000, 0.2331923000, 0.4874067000, 1.1246359000", \ - "0.0688837000, 0.0761737000, 0.0936219000, 0.1354493000, 0.2379319000, 0.4919817000, 1.1284557000", \ - "0.0760304000, 0.0832521000, 0.1008648000, 0.1432616000, 0.2459234000, 0.5022616000, 1.1450406000", \ - "0.0890418000, 0.0967224000, 0.1146132000, 0.1572566000, 0.2604982000, 0.5151067000, 1.1620175000", \ - "0.1078501000, 0.1167071000, 0.1373770000, 0.1842754000, 0.2897430000, 0.5466196000, 1.1830752000", \ - "0.1254577000, 0.1390975000, 0.1675715000, 0.2274143000, 0.3504869000, 0.6154710000, 1.2554956000", \ - "0.1118516000, 0.1336939000, 0.1808387000, 0.2727886000, 0.4404056000, 0.7576010000, 1.4194493000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0565218000, 0.0625639000, 0.0768623000, 0.1119959000, 0.1970528000, 0.4066807000, 0.9295599000", \ - "0.0618324000, 0.0678460000, 0.0822306000, 0.1173008000, 0.2024643000, 0.4122056000, 0.9348012000", \ - "0.0752727000, 0.0814281000, 0.0959328000, 0.1306873000, 0.2153129000, 0.4255986000, 0.9477017000", \ - "0.1076865000, 0.1134909000, 0.1278513000, 0.1628523000, 0.2479879000, 0.4563893000, 0.9777573000", \ - "0.1727860000, 0.1810396000, 0.1999200000, 0.2383916000, 0.3203377000, 0.5293433000, 1.0511626000", \ - "0.2791015000, 0.2922002000, 0.3217894000, 0.3823580000, 0.4936111000, 0.7047432000, 1.2181592000", \ - "0.4511215000, 0.4709129000, 0.5166542000, 0.6129363000, 0.7941517000, 1.0942154000, 1.6258654000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0436489000, 0.0526651000, 0.0749720000, 0.1298617000, 0.2666831000, 0.6088686000, 1.4582466000", \ - "0.0436692000, 0.0528174000, 0.0752700000, 0.1300019000, 0.2660617000, 0.6060443000, 1.4604908000", \ - "0.0436315000, 0.0528859000, 0.0750319000, 0.1301448000, 0.2659989000, 0.6074851000, 1.4690762000", \ - "0.0465201000, 0.0549527000, 0.0762733000, 0.1299983000, 0.2658520000, 0.6061766000, 1.4724596000", \ - "0.0571041000, 0.0660361000, 0.0875606000, 0.1390416000, 0.2691129000, 0.6071431000, 1.4601709000", \ - "0.0880816000, 0.0977437000, 0.1199999000, 0.1722649000, 0.2981264000, 0.6191987000, 1.4593554000", \ - "0.1599704000, 0.1717455000, 0.2000045000, 0.2578898000, 0.3854371000, 0.6937609000, 1.4914762000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012526100, 0.0031380500, 0.0078614900, 0.0196947000, 0.0493395000, 0.1236060000"); - values("0.0561386000, 0.0634829000, 0.0821608000, 0.1285478000, 0.2451834000, 0.5396877000, 1.2789741000", \ - "0.0561806000, 0.0633101000, 0.0820852000, 0.1287314000, 0.2452097000, 0.5396741000, 1.2781796000", \ - "0.0555163000, 0.0630177000, 0.0818801000, 0.1284020000, 0.2454416000, 0.5398509000, 1.2782415000", \ - "0.0596194000, 0.0661812000, 0.0833614000, 0.1279934000, 0.2452497000, 0.5397043000, 1.2809234000", \ - "0.0893582000, 0.0956755000, 0.1092985000, 0.1443358000, 0.2487744000, 0.5398010000, 1.2812936000", \ - "0.1447516000, 0.1547249000, 0.1768411000, 0.2198844000, 0.3033323000, 0.5532425000, 1.2820215000", \ - "0.2360884000, 0.2522225000, 0.2894220000, 0.3587806000, 0.4836934000, 0.6920213000, 1.3080154000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4bb_2") { - leakage_power () { - value : 0.0013298000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0008363000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0087330000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0013309000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0014701000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0014427000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0019814000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0014755000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0010759000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0010472000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0017604000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0010789000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0016926000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0181058000; - when : "A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0017219000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0016932000; - when : "A_N&B_N&C&!D"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__nand4bb"; - cell_leakage_power : 0.0029234700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0015000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0119788000, 0.0118940000, 0.0116985000, 0.0117663000, 0.0119226000, 0.0122829000, 0.0131135000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0100219000, 0.0099853000, 0.0099008000, 0.0099309000, 0.0100005000, 0.0101608000, 0.0105304000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015450000; - } - pin ("B_N") { - capacitance : 0.0014890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089561000, 0.0088790000, 0.0087012000, 0.0087382000, 0.0088235000, 0.0090201000, 0.0094733000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093452000, 0.0092985000, 0.0091907000, 0.0092318000, 0.0093263000, 0.0095444000, 0.0100469000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015440000; - } - pin ("C") { - capacitance : 0.0044620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085633000, 0.0085778000, 0.0086113000, 0.0086154000, 0.0086249000, 0.0086467000, 0.0086971000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007653000, -0.007653300, -0.007653900, -0.007641800, -0.007614000, -0.007549700, -0.007401600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046410000; - } - pin ("D") { - capacitance : 0.0044700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079348000, 0.0079351000, 0.0079358000, 0.0079369000, 0.0079396000, 0.0079457000, 0.0079598000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007916300, -0.007915100, -0.007912300, -0.007911300, -0.007909000, -0.007903700, -0.007891400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046960000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (B_N) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0102354000, 0.0090002000, 0.0054376000, -0.004374100, -0.031646800, -0.106865200, -0.311981300", \ - "0.0102798000, 0.0089415000, 0.0053888000, -0.004387000, -0.031666700, -0.106865900, -0.311934600", \ - "0.0102668000, 0.0089922000, 0.0054684000, -0.004293200, -0.031633400, -0.106825200, -0.311833300", \ - "0.0100622000, 0.0087801000, 0.0052485000, -0.004555400, -0.031890200, -0.107099600, -0.312063400", \ - "0.0097874000, 0.0084776000, 0.0050713000, -0.004835000, -0.032192300, -0.107416700, -0.312316600", \ - "0.0095198000, 0.0081857000, 0.0048196000, -0.005169200, -0.032497100, -0.107596000, -0.312709100", \ - "0.0097843000, 0.0083789000, 0.0045927000, -0.005692200, -0.033095700, -0.108247700, -0.312957700"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0057837000, 0.0073240000, 0.0114125000, 0.0220225000, 0.0499968000, 0.1249911000, 0.3281905000", \ - "0.0057819000, 0.0073225000, 0.0114070000, 0.0220338000, 0.0500128000, 0.1248290000, 0.3282035000", \ - "0.0057212000, 0.0072637000, 0.0113444000, 0.0219851000, 0.0499845000, 0.1250085000, 0.3298239000", \ - "0.0053927000, 0.0068892000, 0.0109186000, 0.0215594000, 0.0496291000, 0.1247231000, 0.3298362000", \ - "0.0051918000, 0.0066713000, 0.0106617000, 0.0210101000, 0.0491907000, 0.1246736000, 0.3281877000", \ - "0.0050581000, 0.0065183000, 0.0104400000, 0.0209768000, 0.0487502000, 0.1233844000, 0.3275040000", \ - "0.0053373000, 0.0067976000, 0.0108001000, 0.0212994000, 0.0490027000, 0.1235258000, 0.3261182000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0179275000, 0.0166615000, 0.0131472000, 0.0033908000, -0.023973100, -0.099187300, -0.304250600", \ - "0.0179140000, 0.0166315000, 0.0131231000, 0.0033428000, -0.024008200, -0.099182400, -0.304289900", \ - "0.0179329000, 0.0166411000, 0.0131281000, 0.0033700000, -0.023974700, -0.099218600, -0.304287800", \ - "0.0177765000, 0.0164893000, 0.0129452000, 0.0031363000, -0.024210700, -0.099376100, -0.304426100", \ - "0.0175002000, 0.0162261000, 0.0126301000, 0.0027999000, -0.024525000, -0.099621200, -0.304639100", \ - "0.0172354000, 0.0159273000, 0.0123304000, 0.0024204000, -0.024894800, -0.099980600, -0.304850100", \ - "0.0174258000, 0.0160794000, 0.0123606000, 0.0022495000, -0.025032000, -0.100104100, -0.304902100"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0102330000, 0.0116774000, 0.0155804000, 0.0259603000, 0.0536818000, 0.1283497000, 0.3309013000", \ - "0.0102479000, 0.0116924000, 0.0155831000, 0.0259500000, 0.0537634000, 0.1284208000, 0.3304947000", \ - "0.0101923000, 0.0116469000, 0.0155301000, 0.0259371000, 0.0536921000, 0.1286392000, 0.3306523000", \ - "0.0097491000, 0.0112006000, 0.0150201000, 0.0254741000, 0.0533675000, 0.1282014000, 0.3309763000", \ - "0.0093499000, 0.0107864000, 0.0146332000, 0.0249027000, 0.0528083000, 0.1280070000, 0.3301416000", \ - "0.0089751000, 0.0103932000, 0.0142595000, 0.0246281000, 0.0524510000, 0.1272618000, 0.3301913000", \ - "0.0090987000, 0.0105021000, 0.0143531000, 0.0245247000, 0.0525169000, 0.1271066000, 0.3298927000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0192860000, 0.0179784000, 0.0143538000, 0.0042941000, -0.023395600, -0.098915500, -0.304102300", \ - "0.0189343000, 0.0176523000, 0.0140974000, 0.0041558000, -0.023460400, -0.098935700, -0.304114100", \ - "0.0184537000, 0.0172176000, 0.0137003000, 0.0038533000, -0.023635600, -0.099046800, -0.304139000", \ - "0.0179507000, 0.0166855000, 0.0131655000, 0.0033518000, -0.023948600, -0.099237600, -0.304150400", \ - "0.0177581000, 0.0164548000, 0.0128887000, 0.0029661000, -0.024341200, -0.099414400, -0.304292800", \ - "0.0179941000, 0.0166071000, 0.0128533000, 0.0025015000, -0.024903100, -0.099984000, -0.304667700", \ - "0.0187363000, 0.0172903000, 0.0134388000, 0.0031095000, -0.024814100, -0.100348400, -0.305121400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0120811000, 0.0134431000, 0.0171127000, 0.0271871000, 0.0547192000, 0.1293271000, 0.3316766000", \ - "0.0117144000, 0.0130646000, 0.0167926000, 0.0269540000, 0.0544839000, 0.1290988000, 0.3315570000", \ - "0.0112132000, 0.0126002000, 0.0163723000, 0.0266054000, 0.0543246000, 0.1289906000, 0.3311792000", \ - "0.0107977000, 0.0121902000, 0.0158802000, 0.0260684000, 0.0537830000, 0.1284615000, 0.3314270000", \ - "0.0105727000, 0.0119653000, 0.0156907000, 0.0256317000, 0.0537398000, 0.1286116000, 0.3310094000", \ - "0.0105850000, 0.0120831000, 0.0159257000, 0.0263178000, 0.0537639000, 0.1285382000, 0.3295127000", \ - "0.0141424000, 0.0151796000, 0.0173471000, 0.0271734000, 0.0547415000, 0.1285526000, 0.3297229000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0194624000, 0.0181565000, 0.0145245000, 0.0044694000, -0.023217100, -0.098736600, -0.303924300", \ - "0.0191242000, 0.0178615000, 0.0142679000, 0.0043096000, -0.023305500, -0.098761800, -0.303944300", \ - "0.0186861000, 0.0174095000, 0.0138710000, 0.0040022000, -0.023449200, -0.098823900, -0.303965600", \ - "0.0181683000, 0.0168933000, 0.0133690000, 0.0035461000, -0.023762200, -0.098996200, -0.304050800", \ - "0.0180157000, 0.0166766000, 0.0130751000, 0.0031416000, -0.024171500, -0.099230300, -0.304109600", \ - "0.0183307000, 0.0169509000, 0.0131771000, 0.0028120000, -0.024622600, -0.099718800, -0.304424900", \ - "0.0192934000, 0.0178304000, 0.0139656000, 0.0036156000, -0.024257900, -0.099845900, -0.304697900"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013577850, 0.0036871630, 0.0100127500, 0.0271903400, 0.0738373000, 0.2005104000"); - values("0.0181549000, 0.0195119000, 0.0232314000, 0.0333880000, 0.0609270000, 0.1357293000, 0.3382050000", \ - "0.0177960000, 0.0191581000, 0.0228801000, 0.0330379000, 0.0606483000, 0.1353793000, 0.3380126000", \ - "0.0174237000, 0.0188185000, 0.0225697000, 0.0327689000, 0.0604737000, 0.1351414000, 0.3378413000", \ - "0.0169761000, 0.0183582000, 0.0220746000, 0.0323819000, 0.0601067000, 0.1348636000, 0.3372614000", \ - "0.0169485000, 0.0183152000, 0.0220494000, 0.0322744000, 0.0598951000, 0.1346824000, 0.3373415000", \ - "0.0175026000, 0.0189475000, 0.0226479000, 0.0327044000, 0.0602160000, 0.1347495000, 0.3368013000", \ - "0.0199594000, 0.0212869000, 0.0248277000, 0.0345576000, 0.0615924000, 0.1359701000, 0.3375494000"); - } - } - max_capacitance : 0.2005100000; - max_transition : 1.4991700000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.1729595000, 0.1790768000, 0.1943536000, 0.2316289000, 0.3236871000, 0.5674556000, 1.2238046000", \ - "0.1778843000, 0.1839689000, 0.1992357000, 0.2365954000, 0.3289586000, 0.5728191000, 1.2289718000", \ - "0.1904723000, 0.1973455000, 0.2127726000, 0.2499577000, 0.3419699000, 0.5851565000, 1.2496718000", \ - "0.2224110000, 0.2285091000, 0.2440941000, 0.2814435000, 0.3735326000, 0.6167126000, 1.2730536000", \ - "0.2973074000, 0.3033604000, 0.3183908000, 0.3553840000, 0.4472459000, 0.6907949000, 1.3480563000", \ - "0.4456431000, 0.4524204000, 0.4686511000, 0.5071543000, 0.5998593000, 0.8434817000, 1.5068302000", \ - "0.6832838000, 0.6918816000, 0.7123575000, 0.7569410000, 0.8539576000, 1.0963127000, 1.7556917000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0837018000, 0.0876816000, 0.0978583000, 0.1227700000, 0.1860467000, 0.3549986000, 0.8114216000", \ - "0.0885540000, 0.0926310000, 0.1027337000, 0.1276291000, 0.1909790000, 0.3595529000, 0.8178342000", \ - "0.0999739000, 0.1040336000, 0.1141272000, 0.1391211000, 0.2026888000, 0.3716465000, 0.8279478000", \ - "0.1256124000, 0.1296057000, 0.1396504000, 0.1646692000, 0.2284891000, 0.3983277000, 0.8573668000", \ - "0.1680773000, 0.1722552000, 0.1827803000, 0.2080712000, 0.2721899000, 0.4411124000, 0.8994470000", \ - "0.2219465000, 0.2272747000, 0.2389830000, 0.2659257000, 0.3302809000, 0.4995943000, 0.9563526000", \ - "0.2724467000, 0.2794178000, 0.2951689000, 0.3274441000, 0.3943497000, 0.5629211000, 1.0191374000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0548506000, 0.0611934000, 0.0778788000, 0.1221039000, 0.2415635000, 0.5731725000, 1.4758106000", \ - "0.0551393000, 0.0615765000, 0.0778248000, 0.1220552000, 0.2416714000, 0.5729680000, 1.4734235000", \ - "0.0548179000, 0.0612423000, 0.0777645000, 0.1220609000, 0.2418258000, 0.5724483000, 1.4814511000", \ - "0.0547280000, 0.0615142000, 0.0777170000, 0.1219545000, 0.2414814000, 0.5758777000, 1.4723922000", \ - "0.0552216000, 0.0616656000, 0.0782077000, 0.1222553000, 0.2419246000, 0.5738203000, 1.4763658000", \ - "0.0644126000, 0.0707128000, 0.0863520000, 0.1283496000, 0.2443042000, 0.5734085000, 1.4792774000", \ - "0.0870675000, 0.0931644000, 0.1080434000, 0.1469415000, 0.2555601000, 0.5789091000, 1.4740674000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0321898000, 0.0362340000, 0.0475858000, 0.0791792000, 0.1674591000, 0.4108205000, 1.0708656000", \ - "0.0321487000, 0.0363228000, 0.0474540000, 0.0791596000, 0.1675887000, 0.4098533000, 1.0717693000", \ - "0.0321672000, 0.0363273000, 0.0474741000, 0.0791683000, 0.1674403000, 0.4106413000, 1.0751277000", \ - "0.0328443000, 0.0368830000, 0.0479899000, 0.0793416000, 0.1675954000, 0.4112240000, 1.0748031000", \ - "0.0372606000, 0.0409922000, 0.0512993000, 0.0815938000, 0.1679637000, 0.4105807000, 1.0726388000", \ - "0.0476271000, 0.0512549000, 0.0605777000, 0.0874032000, 0.1704725000, 0.4100092000, 1.0678640000", \ - "0.0677868000, 0.0712413000, 0.0806626000, 0.1045132000, 0.1784568000, 0.4118923000, 1.0671528000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.1931726000, 0.1994319000, 0.2149549000, 0.2536709000, 0.3480024000, 0.5924718000, 1.2489112000", \ - "0.1982242000, 0.2043877000, 0.2200883000, 0.2587587000, 0.3530087000, 0.5974458000, 1.2539310000", \ - "0.2109248000, 0.2169656000, 0.2326670000, 0.2713461000, 0.3655045000, 0.6098791000, 1.2672016000", \ - "0.2419905000, 0.2482664000, 0.2638209000, 0.3024677000, 0.3967188000, 0.6411693000, 1.2976789000", \ - "0.3158660000, 0.3218619000, 0.3374574000, 0.3758046000, 0.4701000000, 0.7149822000, 1.3719107000", \ - "0.4619649000, 0.4685328000, 0.4851017000, 0.5244328000, 0.6200195000, 0.8648441000, 1.5224073000", \ - "0.6937998000, 0.7018248000, 0.7213382000, 0.7658035000, 0.8653234000, 1.1117873000, 1.7714528000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.1027618000, 0.1067228000, 0.1169998000, 0.1432111000, 0.2111038000, 0.3915936000, 0.8785095000", \ - "0.1076211000, 0.1115610000, 0.1218360000, 0.1480776000, 0.2160137000, 0.3961203000, 0.8855841000", \ - "0.1191326000, 0.1230850000, 0.1333839000, 0.1596561000, 0.2274849000, 0.4084912000, 0.8959284000", \ - "0.1451800000, 0.1491246000, 0.1594015000, 0.1857247000, 0.2537323000, 0.4343532000, 0.9215420000", \ - "0.1908673000, 0.1948773000, 0.2053097000, 0.2318475000, 0.2998703000, 0.4811800000, 0.9682476000", \ - "0.2526959000, 0.2570223000, 0.2679454000, 0.2951359000, 0.3628438000, 0.5438782000, 1.0321923000", \ - "0.3206981000, 0.3259848000, 0.3390150000, 0.3688624000, 0.4384131000, 0.6187333000, 1.1078621000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0544289000, 0.0612111000, 0.0782204000, 0.1233921000, 0.2436204000, 0.5738320000, 1.4729638000", \ - "0.0546388000, 0.0611340000, 0.0784215000, 0.1234141000, 0.2436810000, 0.5736258000, 1.4727176000", \ - "0.0546410000, 0.0611551000, 0.0783081000, 0.1233477000, 0.2435007000, 0.5732774000, 1.4752962000", \ - "0.0546738000, 0.0612304000, 0.0783087000, 0.1234850000, 0.2437630000, 0.5738244000, 1.4729375000", \ - "0.0548814000, 0.0612790000, 0.0786056000, 0.1235396000, 0.2434776000, 0.5736543000, 1.4738359000", \ - "0.0608230000, 0.0670370000, 0.0836047000, 0.1267806000, 0.2454643000, 0.5747119000, 1.4728598000", \ - "0.0793317000, 0.0847007000, 0.0995722000, 0.1399610000, 0.2529182000, 0.5768709000, 1.4751967000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0446333000, 0.0489903000, 0.0611393000, 0.0943629000, 0.1868933000, 0.4406622000, 1.1304022000", \ - "0.0446389000, 0.0490525000, 0.0611187000, 0.0944555000, 0.1868086000, 0.4403878000, 1.1330137000", \ - "0.0445908000, 0.0491189000, 0.0612348000, 0.0945004000, 0.1867714000, 0.4409179000, 1.1336144000", \ - "0.0450337000, 0.0493652000, 0.0613938000, 0.0946059000, 0.1872354000, 0.4407560000, 1.1299492000", \ - "0.0480805000, 0.0521332000, 0.0636038000, 0.0959601000, 0.1871896000, 0.4408219000, 1.1324275000", \ - "0.0562808000, 0.0600732000, 0.0704132000, 0.1005815000, 0.1896956000, 0.4409693000, 1.1314640000", \ - "0.0743513000, 0.0779454000, 0.0874122000, 0.1152676000, 0.1955662000, 0.4429165000, 1.1316880000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0710201000, 0.0763060000, 0.0901275000, 0.1258912000, 0.2174903000, 0.4602400000, 1.1164584000", \ - "0.0742162000, 0.0796288000, 0.0937278000, 0.1301540000, 0.2213882000, 0.4649566000, 1.1206506000", \ - "0.0804513000, 0.0859983000, 0.1003623000, 0.1369553000, 0.2285204000, 0.4724561000, 1.1282761000", \ - "0.0921065000, 0.0979496000, 0.1126855000, 0.1491158000, 0.2422527000, 0.4864327000, 1.1431036000", \ - "0.1097196000, 0.1168460000, 0.1341022000, 0.1754401000, 0.2723836000, 0.5182187000, 1.1750301000", \ - "0.1268743000, 0.1373107000, 0.1622020000, 0.2183850000, 0.3369191000, 0.5961155000, 1.2620199000", \ - "0.1094066000, 0.1262476000, 0.1671062000, 0.2559178000, 0.4286384000, 0.7527821000, 1.4462795000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0505999000, 0.0543137000, 0.0641644000, 0.0899170000, 0.1576432000, 0.3377772000, 0.8228400000", \ - "0.0560627000, 0.0596784000, 0.0695876000, 0.0954492000, 0.1632206000, 0.3434034000, 0.8290831000", \ - "0.0692975000, 0.0730552000, 0.0830023000, 0.1091201000, 0.1771404000, 0.3565588000, 0.8418568000", \ - "0.1024820000, 0.1059695000, 0.1154339000, 0.1414764000, 0.2094299000, 0.3875779000, 0.8726453000", \ - "0.1650592000, 0.1707431000, 0.1847613000, 0.2165935000, 0.2848402000, 0.4645331000, 0.9497655000", \ - "0.2668200000, 0.2759607000, 0.2995411000, 0.3510549000, 0.4523528000, 0.6419940000, 1.1232757000", \ - "0.4407673000, 0.4544524000, 0.4885776000, 0.5704637000, 0.7345344000, 1.0251701000, 1.5344117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0477080000, 0.0544816000, 0.0723296000, 0.1195832000, 0.2421570000, 0.5730258000, 1.4733172000", \ - "0.0476999000, 0.0544312000, 0.0723663000, 0.1193499000, 0.2417563000, 0.5751041000, 1.4731993000", \ - "0.0477342000, 0.0545933000, 0.0725679000, 0.1195076000, 0.2420711000, 0.5768666000, 1.4724085000", \ - "0.0517009000, 0.0577551000, 0.0747353000, 0.1197055000, 0.2420142000, 0.5743916000, 1.4740713000", \ - "0.0626591000, 0.0696929000, 0.0872034000, 0.1311576000, 0.2464447000, 0.5746023000, 1.4726812000", \ - "0.0972253000, 0.1046488000, 0.1231440000, 0.1685264000, 0.2823080000, 0.5862427000, 1.4787379000", \ - "0.1728860000, 0.1822270000, 0.2062498000, 0.2618571000, 0.3822106000, 0.6762786000, 1.4991705000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0498554000, 0.0546172000, 0.0672045000, 0.1009280000, 0.1934384000, 0.4458407000, 1.1339389000", \ - "0.0500047000, 0.0545366000, 0.0671672000, 0.1009667000, 0.1938818000, 0.4461822000, 1.1337603000", \ - "0.0493864000, 0.0542363000, 0.0669261000, 0.1009937000, 0.1934975000, 0.4456421000, 1.1352989000", \ - "0.0558767000, 0.0595336000, 0.0700815000, 0.1016572000, 0.1937565000, 0.4462351000, 1.1343456000", \ - "0.0863735000, 0.0903689000, 0.1005684000, 0.1230886000, 0.2005064000, 0.4457258000, 1.1341167000", \ - "0.1405253000, 0.1471701000, 0.1634173000, 0.1977272000, 0.2660589000, 0.4664876000, 1.1341488000", \ - "0.2303261000, 0.2412101000, 0.2688834000, 0.3253588000, 0.4323007000, 0.6204660000, 1.1750204000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0762011000, 0.0814487000, 0.0954553000, 0.1310058000, 0.2224805000, 0.4654243000, 1.1215689000", \ - "0.0797228000, 0.0852922000, 0.0992379000, 0.1351810000, 0.2271493000, 0.4700085000, 1.1262314000", \ - "0.0868151000, 0.0924597000, 0.1067842000, 0.1430472000, 0.2350482000, 0.4795557000, 1.1346070000", \ - "0.0997294000, 0.1052632000, 0.1195407000, 0.1561979000, 0.2488544000, 0.4922526000, 1.1494183000", \ - "0.1174278000, 0.1236749000, 0.1395545000, 0.1787686000, 0.2739292000, 0.5187298000, 1.1761410000", \ - "0.1356193000, 0.1439435000, 0.1647282000, 0.2139647000, 0.3233268000, 0.5787745000, 1.2380460000", \ - "0.1236265000, 0.1369317000, 0.1706156000, 0.2459170000, 0.3977033000, 0.6986519000, 1.3847421000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0528092000, 0.0563901000, 0.0658782000, 0.0902461000, 0.1531824000, 0.3187683000, 0.7638238000", \ - "0.0580458000, 0.0616332000, 0.0710864000, 0.0955157000, 0.1584972000, 0.3239971000, 0.7680164000", \ - "0.0712573000, 0.0748733000, 0.0844313000, 0.1089382000, 0.1720431000, 0.3372575000, 0.7816557000", \ - "0.1041638000, 0.1074729000, 0.1166175000, 0.1409521000, 0.2039727000, 0.3694489000, 0.8143851000", \ - "0.1684316000, 0.1735119000, 0.1862617000, 0.2153688000, 0.2788743000, 0.4432279000, 0.8874271000", \ - "0.2703943000, 0.2783260000, 0.2982561000, 0.3448206000, 0.4410225000, 0.6176685000, 1.0613840000", \ - "0.4406854000, 0.4527320000, 0.4837097000, 0.5557463000, 0.7051822000, 0.9828623000, 1.4627336000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0477393000, 0.0544330000, 0.0726215000, 0.1193621000, 0.2418104000, 0.5729812000, 1.4733188000", \ - "0.0476940000, 0.0545849000, 0.0724712000, 0.1193966000, 0.2419166000, 0.5729615000, 1.4732799000", \ - "0.0477870000, 0.0547904000, 0.0726256000, 0.1192373000, 0.2421597000, 0.5747313000, 1.4737488000", \ - "0.0496499000, 0.0561770000, 0.0734934000, 0.1195012000, 0.2421262000, 0.5736562000, 1.4749835000", \ - "0.0576678000, 0.0643853000, 0.0820332000, 0.1271155000, 0.2448683000, 0.5731150000, 1.4750112000", \ - "0.0827308000, 0.0894355000, 0.1072907000, 0.1539281000, 0.2710745000, 0.5835383000, 1.4746023000", \ - "0.1505545000, 0.1587720000, 0.1799557000, 0.2304234000, 0.3490539000, 0.6539365000, 1.4972187000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013577900, 0.0036871600, 0.0100128000, 0.0271903000, 0.0738373000, 0.2005100000"); - values("0.0575174000, 0.0617822000, 0.0729666000, 0.1037043000, 0.1878220000, 0.4201330000, 1.0548481000", \ - "0.0572453000, 0.0615423000, 0.0728602000, 0.1035075000, 0.1887154000, 0.4204180000, 1.0545359000", \ - "0.0559188000, 0.0601566000, 0.0721396000, 0.1035789000, 0.1880403000, 0.4203183000, 1.0550396000", \ - "0.0607398000, 0.0645090000, 0.0748431000, 0.1035752000, 0.1878933000, 0.4203727000, 1.0539468000", \ - "0.0902649000, 0.0941639000, 0.1031822000, 0.1257932000, 0.1953610000, 0.4205851000, 1.0549269000", \ - "0.1454971000, 0.1515121000, 0.1651417000, 0.1975894000, 0.2633641000, 0.4464884000, 1.0559427000", \ - "0.2335328000, 0.2436234000, 0.2682097000, 0.3226677000, 0.4258979000, 0.6127255000, 1.1088117000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nand4bb_4") { - leakage_power () { - value : 0.0021446000; - when : "!A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0008800000; - when : "!A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0110036000; - when : "!A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0021369000; - when : "!A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0023886000; - when : "!A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0023167000; - when : "!A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0036834000; - when : "!A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0023927000; - when : "!A_N&B_N&C&!D"; - } - leakage_power () { - value : 0.0038340000; - when : "A_N&!B_N&!C&D"; - } - leakage_power () { - value : 0.0037578000; - when : "A_N&!B_N&!C&!D"; - } - leakage_power () { - value : 0.0055639000; - when : "A_N&!B_N&C&D"; - } - leakage_power () { - value : 0.0038371000; - when : "A_N&!B_N&C&!D"; - } - leakage_power () { - value : 0.0052867000; - when : "A_N&B_N&!C&D"; - } - leakage_power () { - value : 0.0284557000; - when : "A_N&B_N&!C&!D"; - } - leakage_power () { - value : 0.0053618000; - when : "A_N&B_N&C&D"; - } - leakage_power () { - value : 0.0052875000; - when : "A_N&B_N&C&!D"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__nand4bb"; - cell_leakage_power : 0.0055206760; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A_N") { - capacitance : 0.0023840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0218176000, 0.0217040000, 0.0214422000, 0.0215769000, 0.0218874000, 0.0226030000, 0.0242527000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0193043000, 0.0192187000, 0.0190213000, 0.0190986000, 0.0192770000, 0.0196881000, 0.0206357000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025000000; - } - pin ("B_N") { - capacitance : 0.0023850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156780000, 0.0155711000, 0.0153248000, 0.0154240000, 0.0156526000, 0.0161796000, 0.0173942000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181510000, 0.0180644000, 0.0178646000, 0.0179548000, 0.0181626000, 0.0186416000, 0.0197458000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024990000; - } - pin ("C") { - capacitance : 0.0085950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0165704000, 0.0166114000, 0.0167057000, 0.0166959000, 0.0166733000, 0.0166212000, 0.0165011000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015126200, -0.015130000, -0.015138600, -0.015123700, -0.015089400, -0.015010400, -0.014828300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089330000; - } - pin ("D") { - capacitance : 0.0087430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157040000, 0.0157019000, 0.0156971000, 0.0156996000, 0.0157052000, 0.0157181000, 0.0157479000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015682300, -0.015677500, -0.015666300, -0.015664000, -0.015658800, -0.015646800, -0.015619200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092010000; - } - pin ("Y") { - direction : "output"; - function : "(A_N) | (B_N) | (!C) | (!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0221397000, 0.0206874000, 0.0162441000, 0.0027047000, -0.039226600, -0.166930500, -0.550374800", \ - "0.0221083000, 0.0206331000, 0.0163271000, 0.0026859000, -0.039189900, -0.166916200, -0.550404700", \ - "0.0221753000, 0.0206881000, 0.0162050000, 0.0026652000, -0.039162200, -0.166822700, -0.550453300", \ - "0.0217697000, 0.0202910000, 0.0157901000, 0.0022015000, -0.039699100, -0.167256300, -0.550711100", \ - "0.0211700000, 0.0196405000, 0.0150784000, 0.0012501000, -0.040571400, -0.167975300, -0.551163700", \ - "0.0206103000, 0.0190510000, 0.0144713000, 0.0005778000, -0.041468500, -0.168729600, -0.551824400", \ - "0.0210715000, 0.0194597000, 0.0146713000, 0.0008356000, -0.041527600, -0.168929400, -0.552238300"); - } - related_pin : "A_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0104989000, 0.0123208000, 0.0176578000, 0.0330056000, 0.0767196000, 0.2047415000, 0.5819098000", \ - "0.0104762000, 0.0122904000, 0.0176064000, 0.0330070000, 0.0768519000, 0.2048132000, 0.5852412000", \ - "0.0104421000, 0.0122554000, 0.0175769000, 0.0329407000, 0.0768161000, 0.2047918000, 0.5851992000", \ - "0.0098336000, 0.0116210000, 0.0168993000, 0.0321812000, 0.0761459000, 0.2043266000, 0.5849690000", \ - "0.0092916000, 0.0110295000, 0.0161761000, 0.0310102000, 0.0749826000, 0.2035392000, 0.5845771000", \ - "0.0093579000, 0.0110283000, 0.0160816000, 0.0305019000, 0.0738088000, 0.2018364000, 0.5839186000", \ - "0.0101032000, 0.0116468000, 0.0166373000, 0.0311862000, 0.0743178000, 0.2019650000, 0.5812801000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0371745000, 0.0356867000, 0.0312335000, 0.0176570000, -0.024290600, -0.152143100, -0.535708400", \ - "0.0371504000, 0.0356100000, 0.0312239000, 0.0176458000, -0.024305700, -0.152137800, -0.535710000", \ - "0.0371665000, 0.0356520000, 0.0312464000, 0.0176487000, -0.024299500, -0.152073300, -0.535689000", \ - "0.0368576000, 0.0353711000, 0.0308898000, 0.0172386000, -0.024715800, -0.152420600, -0.535896400", \ - "0.0362949000, 0.0347817000, 0.0302111000, 0.0165001000, -0.025428500, -0.152984400, -0.536327700", \ - "0.0355775000, 0.0341452000, 0.0295631000, 0.0156993000, -0.026299500, -0.153731100, -0.536817400", \ - "0.0358960000, 0.0342149000, 0.0295141000, 0.0155353000, -0.026647800, -0.154009800, -0.536938300"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0186495000, 0.0203472000, 0.0253952000, 0.0400938000, 0.0832327000, 0.2104603000, 0.5887537000", \ - "0.0186816000, 0.0203768000, 0.0253940000, 0.0401730000, 0.0833155000, 0.2104353000, 0.5891327000", \ - "0.0185885000, 0.0203054000, 0.0253407000, 0.0400889000, 0.0832559000, 0.2103617000, 0.5897785000", \ - "0.0178395000, 0.0195297000, 0.0245524000, 0.0394019000, 0.0826180000, 0.2100109000, 0.5890551000", \ - "0.0169451000, 0.0186204000, 0.0235752000, 0.0383143000, 0.0814473000, 0.2092331000, 0.5884591000", \ - "0.0163357000, 0.0179824000, 0.0230960000, 0.0372624000, 0.0805192000, 0.2086517000, 0.5877551000", \ - "0.0163556000, 0.0180398000, 0.0229432000, 0.0373820000, 0.0806435000, 0.2074517000, 0.5872903000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0400806000, 0.0385412000, 0.0338268000, 0.0197126000, -0.023031800, -0.151402500, -0.535268200", \ - "0.0393243000, 0.0379090000, 0.0333197000, 0.0193787000, -0.023170000, -0.151548200, -0.535212800", \ - "0.0383884000, 0.0369015000, 0.0324251000, 0.0187214000, -0.023544300, -0.151591200, -0.535345900", \ - "0.0373594000, 0.0358507000, 0.0313797000, 0.0177549000, -0.024223900, -0.151958500, -0.535450700", \ - "0.0368911000, 0.0353974000, 0.0307954000, 0.0170290000, -0.025016000, -0.152422300, -0.535539500", \ - "0.0374382000, 0.0359037000, 0.0310400000, 0.0164613000, -0.026037300, -0.153465700, -0.536302300", \ - "0.0388234000, 0.0371006000, 0.0321845000, 0.0176533000, -0.025476600, -0.153975500, -0.537005000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0227515000, 0.0243081000, 0.0290003000, 0.0431884000, 0.0855925000, 0.2126583000, 0.5911958000", \ - "0.0220718000, 0.0236497000, 0.0284193000, 0.0426966000, 0.0852815000, 0.2122179000, 0.5909421000", \ - "0.0209961000, 0.0226085000, 0.0274243000, 0.0418339000, 0.0847239000, 0.2117391000, 0.5912352000", \ - "0.0201828000, 0.0217986000, 0.0266686000, 0.0408656000, 0.0838654000, 0.2111411000, 0.5906211000", \ - "0.0195805000, 0.0211563000, 0.0259037000, 0.0402089000, 0.0830809000, 0.2108161000, 0.5900437000", \ - "0.0206264000, 0.0221831000, 0.0268940000, 0.0411445000, 0.0837508000, 0.2108594000, 0.5875913000", \ - "0.0241042000, 0.0253780000, 0.0299724000, 0.0435496000, 0.0855510000, 0.2113186000, 0.5885470000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0402242000, 0.0386815000, 0.0340679000, 0.0199412000, -0.022795400, -0.151287200, -0.535033300", \ - "0.0395817000, 0.0381590000, 0.0335455000, 0.0195792000, -0.023003200, -0.151338200, -0.535089700", \ - "0.0386206000, 0.0371516000, 0.0326822000, 0.0189374000, -0.023355400, -0.151503600, -0.535151600", \ - "0.0376824000, 0.0361858000, 0.0316980000, 0.0180277000, -0.023985800, -0.151812500, -0.535260400", \ - "0.0372876000, 0.0357776000, 0.0311421000, 0.0172958000, -0.024779800, -0.152228000, -0.535463200", \ - "0.0379417000, 0.0363693000, 0.0316084000, 0.0169052000, -0.025505700, -0.152991400, -0.535873500", \ - "0.0395494000, 0.0378701000, 0.0329131000, 0.0183267000, -0.024691100, -0.153400800, -0.536494000"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014942180, 0.0044653720, 0.0133444700, 0.0398791000, 0.1191761000, 0.3561500000"); - values("0.0342876000, 0.0358583000, 0.0406068000, 0.0548193000, 0.0974979000, 0.2247226000, 0.6040780000", \ - "0.0336445000, 0.0352536000, 0.0399430000, 0.0541989000, 0.0969033000, 0.2240804000, 0.6029840000", \ - "0.0328422000, 0.0344267000, 0.0392181000, 0.0535442000, 0.0963629000, 0.2237941000, 0.6033541000", \ - "0.0320347000, 0.0336412000, 0.0384433000, 0.0528206000, 0.0957763000, 0.2231373000, 0.6025175000", \ - "0.0316631000, 0.0332803000, 0.0380592000, 0.0521096000, 0.0952391000, 0.2224993000, 0.6027529000", \ - "0.0339609000, 0.0355083000, 0.0389607000, 0.0529531000, 0.0964913000, 0.2235480000, 0.6017278000", \ - "0.0374075000, 0.0389158000, 0.0433775000, 0.0571339000, 0.0995090000, 0.2263008000, 0.6030352000"); - } - } - max_capacitance : 0.3561500000; - max_transition : 1.4966030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.1537746000, 0.1575625000, 0.1684753000, 0.1978556000, 0.2780254000, 0.5084203000, 1.1942745000", \ - "0.1588737000, 0.1626870000, 0.1735001000, 0.2030413000, 0.2831334000, 0.5134909000, 1.1994424000", \ - "0.1716907000, 0.1754724000, 0.1862845000, 0.2158836000, 0.2959757000, 0.5273847000, 1.2099058000", \ - "0.2020906000, 0.2058521000, 0.2166302000, 0.2459490000, 0.3259548000, 0.5578584000, 1.2402894000", \ - "0.2731690000, 0.2768774000, 0.2875007000, 0.3167906000, 0.3967951000, 0.6277053000, 1.3157020000", \ - "0.4013293000, 0.4055013000, 0.4171811000, 0.4477847000, 0.5289661000, 0.7595889000, 1.4444392000", \ - "0.5991769000, 0.6044388000, 0.6189047000, 0.6547442000, 0.7397054000, 0.9701830000, 1.6544834000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0964563000, 0.0993018000, 0.1074176000, 0.1289327000, 0.1869881000, 0.3546990000, 0.8509086000", \ - "0.1011542000, 0.1039998000, 0.1120155000, 0.1336555000, 0.1919163000, 0.3587897000, 0.8558620000", \ - "0.1124033000, 0.1152407000, 0.1232849000, 0.1448895000, 0.2031924000, 0.3702715000, 0.8674710000", \ - "0.1379480000, 0.1407397000, 0.1487302000, 0.1702426000, 0.2285491000, 0.3959884000, 0.8930069000", \ - "0.1827268000, 0.1856720000, 0.1938830000, 0.2157712000, 0.2746176000, 0.4422483000, 0.9401993000", \ - "0.2413722000, 0.2447614000, 0.2539386000, 0.2768617000, 0.3363904000, 0.5048118000, 1.0000327000", \ - "0.3012455000, 0.3056475000, 0.3173298000, 0.3455112000, 0.4082155000, 0.5754057000, 1.0728043000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0554860000, 0.0597176000, 0.0718923000, 0.1074823000, 0.2120498000, 0.5279622000, 1.4714878000", \ - "0.0555161000, 0.0597947000, 0.0720530000, 0.1075089000, 0.2121716000, 0.5280114000, 1.4713308000", \ - "0.0555693000, 0.0596619000, 0.0719015000, 0.1075726000, 0.2122251000, 0.5286621000, 1.4717588000", \ - "0.0554524000, 0.0596089000, 0.0716840000, 0.1074686000, 0.2120444000, 0.5283611000, 1.4718612000", \ - "0.0561743000, 0.0603471000, 0.0725495000, 0.1081580000, 0.2120928000, 0.5275615000, 1.4728881000", \ - "0.0657996000, 0.0696872000, 0.0814687000, 0.1147944000, 0.2154191000, 0.5293183000, 1.4734922000", \ - "0.0876984000, 0.0914831000, 0.1018461000, 0.1336990000, 0.2274843000, 0.5314845000, 1.4723268000"); - } - related_pin : "A_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0371197000, 0.0397930000, 0.0481366000, 0.0731359000, 0.1506383000, 0.3872577000, 1.0940210000", \ - "0.0370986000, 0.0398245000, 0.0480459000, 0.0731913000, 0.1504514000, 0.3877701000, 1.0972407000", \ - "0.0370470000, 0.0398583000, 0.0481344000, 0.0731338000, 0.1503208000, 0.3874096000, 1.0974629000", \ - "0.0375616000, 0.0402113000, 0.0484185000, 0.0734480000, 0.1507335000, 0.3876130000, 1.0971202000", \ - "0.0415350000, 0.0440321000, 0.0517811000, 0.0760552000, 0.1515677000, 0.3867634000, 1.0960055000", \ - "0.0523036000, 0.0544391000, 0.0612247000, 0.0831051000, 0.1546439000, 0.3864394000, 1.0992356000", \ - "0.0714954000, 0.0735870000, 0.0804180000, 0.1004663000, 0.1646150000, 0.3902154000, 1.0920838000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.1822447000, 0.1862472000, 0.1976440000, 0.2288095000, 0.3111811000, 0.5425922000, 1.2268951000", \ - "0.1872193000, 0.1914124000, 0.2027272000, 0.2337979000, 0.3163278000, 0.5482355000, 1.2311978000", \ - "0.2005053000, 0.2044543000, 0.2157388000, 0.2469289000, 0.3293613000, 0.5611841000, 1.2450772000", \ - "0.2311008000, 0.2351606000, 0.2464189000, 0.2773455000, 0.3598173000, 0.5915467000, 1.2795357000", \ - "0.3039753000, 0.3080123000, 0.3191598000, 0.3499971000, 0.4325339000, 0.6649565000, 1.3488760000", \ - "0.4419446000, 0.4463158000, 0.4579585000, 0.4899988000, 0.5738215000, 0.8068365000, 1.4915680000", \ - "0.6613317000, 0.6659839000, 0.6803531000, 0.7164859000, 0.8036358000, 1.0387798000, 1.7253292000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.1125902000, 0.1152899000, 0.1230861000, 0.1451340000, 0.2068048000, 0.3856388000, 0.9186888000", \ - "0.1172100000, 0.1198937000, 0.1277383000, 0.1496690000, 0.2114380000, 0.3904663000, 0.9202823000", \ - "0.1283716000, 0.1310775000, 0.1388724000, 0.1609468000, 0.2226816000, 0.4016108000, 0.9317096000", \ - "0.1535352000, 0.1562277000, 0.1640044000, 0.1860206000, 0.2479658000, 0.4270579000, 0.9571761000", \ - "0.1990005000, 0.2017184000, 0.2095839000, 0.2317366000, 0.2938345000, 0.4737520000, 1.0036463000", \ - "0.2588087000, 0.2616952000, 0.2700448000, 0.2925428000, 0.3550245000, 0.5338985000, 1.0644050000", \ - "0.3196829000, 0.3231065000, 0.3328820000, 0.3581932000, 0.4222011000, 0.6007422000, 1.1329325000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0574704000, 0.0616854000, 0.0743820000, 0.1105031000, 0.2150001000, 0.5303818000, 1.4737696000", \ - "0.0574918000, 0.0616808000, 0.0742213000, 0.1105688000, 0.2150336000, 0.5291698000, 1.4721169000", \ - "0.0575005000, 0.0616549000, 0.0743066000, 0.1104695000, 0.2150154000, 0.5295762000, 1.4739343000", \ - "0.0573756000, 0.0617878000, 0.0743416000, 0.1104944000, 0.2150179000, 0.5287166000, 1.4731469000", \ - "0.0578370000, 0.0621215000, 0.0747910000, 0.1107586000, 0.2150224000, 0.5289592000, 1.4707088000", \ - "0.0634270000, 0.0677287000, 0.0795624000, 0.1146104000, 0.2172858000, 0.5301495000, 1.4731727000", \ - "0.0810491000, 0.0841741000, 0.0950748000, 0.1274713000, 0.2249715000, 0.5324848000, 1.4736267000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0495974000, 0.0526547000, 0.0616221000, 0.0883820000, 0.1708184000, 0.4194460000, 1.1702745000", \ - "0.0496689000, 0.0525335000, 0.0614923000, 0.0885440000, 0.1707785000, 0.4197223000, 1.1672454000", \ - "0.0496424000, 0.0526411000, 0.0616375000, 0.0883589000, 0.1707375000, 0.4203358000, 1.1667475000", \ - "0.0498956000, 0.0528192000, 0.0616641000, 0.0885004000, 0.1706683000, 0.4202780000, 1.1662543000", \ - "0.0526384000, 0.0554397000, 0.0639268000, 0.0899550000, 0.1710921000, 0.4200844000, 1.1655235000", \ - "0.0605069000, 0.0631518000, 0.0711356000, 0.0954901000, 0.1733916000, 0.4199942000, 1.1680286000", \ - "0.0792148000, 0.0815496000, 0.0886861000, 0.1105135000, 0.1810145000, 0.4227985000, 1.1675296000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0752285000, 0.0787905000, 0.0885354000, 0.1167996000, 0.1960963000, 0.4263179000, 1.1090491000", \ - "0.0781367000, 0.0818163000, 0.0920793000, 0.1205503000, 0.1998881000, 0.4309328000, 1.1132798000", \ - "0.0837970000, 0.0875520000, 0.0976881000, 0.1265638000, 0.2070705000, 0.4370134000, 1.1202880000", \ - "0.0942201000, 0.0979723000, 0.1087401000, 0.1379419000, 0.2189939000, 0.4508304000, 1.1340048000", \ - "0.1091507000, 0.1136550000, 0.1263134000, 0.1593888000, 0.2455135000, 0.4784297000, 1.1631299000", \ - "0.1227941000, 0.1288667000, 0.1466068000, 0.1929116000, 0.2986947000, 0.5490425000, 1.2363460000", \ - "0.0969279000, 0.1076442000, 0.1356837000, 0.2078937000, 0.3656893000, 0.6830863000, 1.4095601000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0563355000, 0.0588553000, 0.0661509000, 0.0873370000, 0.1482518000, 0.3260749000, 0.8498481000", \ - "0.0615670000, 0.0641074000, 0.0715177000, 0.0928150000, 0.1539237000, 0.3312368000, 0.8558788000", \ - "0.0746823000, 0.0771972000, 0.0846843000, 0.1061484000, 0.1675929000, 0.3452671000, 0.8696150000", \ - "0.1073942000, 0.1097640000, 0.1168863000, 0.1376992000, 0.1982417000, 0.3763053000, 0.9008402000", \ - "0.1722833000, 0.1759727000, 0.1862328000, 0.2127822000, 0.2750418000, 0.4528732000, 0.9779011000", \ - "0.2800765000, 0.2856922000, 0.3015671000, 0.3443351000, 0.4374942000, 0.6283056000, 1.1498190000", \ - "0.4626069000, 0.4707231000, 0.4948442000, 0.5602255000, 0.7104183000, 1.0036453000, 1.5588748000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0518914000, 0.0563679000, 0.0690152000, 0.1063415000, 0.2131262000, 0.5296853000, 1.4721759000", \ - "0.0518507000, 0.0562957000, 0.0693128000, 0.1063422000, 0.2132157000, 0.5290278000, 1.4714634000", \ - "0.0519186000, 0.0564003000, 0.0691588000, 0.1061959000, 0.2129621000, 0.5281846000, 1.4720349000", \ - "0.0554520000, 0.0594960000, 0.0716696000, 0.1073048000, 0.2132472000, 0.5292450000, 1.4740588000", \ - "0.0662890000, 0.0707464000, 0.0831817000, 0.1188672000, 0.2191652000, 0.5313559000, 1.4710861000", \ - "0.1006199000, 0.1053131000, 0.1183030000, 0.1551929000, 0.2546061000, 0.5439786000, 1.4734541000", \ - "0.1776992000, 0.1835891000, 0.2005097000, 0.2448608000, 0.3527376000, 0.6359255000, 1.4966027000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0560571000, 0.0592206000, 0.0684871000, 0.0962039000, 0.1788659000, 0.4292932000, 1.1790201000", \ - "0.0560620000, 0.0592001000, 0.0685503000, 0.0962563000, 0.1797458000, 0.4285765000, 1.1802964000", \ - "0.0556139000, 0.0587826000, 0.0681438000, 0.0962068000, 0.1791926000, 0.4292256000, 1.1786654000", \ - "0.0605619000, 0.0631125000, 0.0711586000, 0.0966753000, 0.1795089000, 0.4292149000, 1.1792285000", \ - "0.0899013000, 0.0925148000, 0.1000667000, 0.1197594000, 0.1870583000, 0.4291287000, 1.1813421000", \ - "0.1451907000, 0.1493139000, 0.1607030000, 0.1899441000, 0.2547479000, 0.4519084000, 1.1789666000", \ - "0.2349645000, 0.2423885000, 0.2632557000, 0.3103498000, 0.4108085000, 0.6078145000, 1.2175695000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0798999000, 0.0832495000, 0.0933242000, 0.1213912000, 0.2004263000, 0.4311964000, 1.1134357000", \ - "0.0829390000, 0.0865980000, 0.0967155000, 0.1253566000, 0.2046047000, 0.4356233000, 1.1180152000", \ - "0.0891352000, 0.0927080000, 0.1030749000, 0.1321834000, 0.2119062000, 0.4432254000, 1.1256276000", \ - "0.1002129000, 0.1038346000, 0.1142334000, 0.1433098000, 0.2237746000, 0.4554855000, 1.1383449000", \ - "0.1145179000, 0.1184833000, 0.1297135000, 0.1611253000, 0.2447672000, 0.4771581000, 1.1616244000", \ - "0.1265554000, 0.1315714000, 0.1460899000, 0.1845160000, 0.2804763000, 0.5258552000, 1.2142648000", \ - "0.1021362000, 0.1110435000, 0.1343840000, 0.1945654000, 0.3298972000, 0.6162684000, 1.3329740000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0584689000, 0.0608304000, 0.0677967000, 0.0877165000, 0.1440105000, 0.3057224000, 0.7819270000", \ - "0.0637750000, 0.0661722000, 0.0730146000, 0.0930042000, 0.1493806000, 0.3111501000, 0.7862892000", \ - "0.0766836000, 0.0790793000, 0.0860827000, 0.1061142000, 0.1626312000, 0.3242726000, 0.8006209000", \ - "0.1094479000, 0.1117103000, 0.1184892000, 0.1383515000, 0.1948444000, 0.3565733000, 0.8318937000", \ - "0.1764568000, 0.1796795000, 0.1888038000, 0.2120499000, 0.2697906000, 0.4314618000, 0.9061112000", \ - "0.2871699000, 0.2920611000, 0.3046607000, 0.3421476000, 0.4279200000, 0.6040908000, 1.0776281000", \ - "0.4695195000, 0.4771336000, 0.4988466000, 0.5550660000, 0.6918994000, 0.9654348000, 1.4814058000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0519309000, 0.0563303000, 0.0693041000, 0.1063565000, 0.2132269000, 0.5289784000, 1.4718987000", \ - "0.0519069000, 0.0563770000, 0.0693181000, 0.1064963000, 0.2132219000, 0.5290836000, 1.4708815000", \ - "0.0519751000, 0.0563702000, 0.0693330000, 0.1065285000, 0.2132453000, 0.5290531000, 1.4715772000", \ - "0.0536977000, 0.0579262000, 0.0704167000, 0.1065753000, 0.2132161000, 0.5289649000, 1.4716970000", \ - "0.0610923000, 0.0653855000, 0.0780649000, 0.1145186000, 0.2170970000, 0.5313168000, 1.4733976000", \ - "0.0845032000, 0.0885240000, 0.1011049000, 0.1375192000, 0.2408506000, 0.5408614000, 1.4766794000", \ - "0.1516657000, 0.1565636000, 0.1708774000, 0.2102028000, 0.3154788000, 0.6049368000, 1.4947379000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014942200, 0.0044653700, 0.0133445000, 0.0398791000, 0.1191760000, 0.3561500000"); - values("0.0643988000, 0.0671786000, 0.0755820000, 0.1006816000, 0.1760519000, 0.4066854000, 1.1002933000", \ - "0.0640369000, 0.0669435000, 0.0753799000, 0.1005291000, 0.1761830000, 0.4063167000, 1.0972115000", \ - "0.0628723000, 0.0658603000, 0.0744507000, 0.1001175000, 0.1759988000, 0.4063460000, 1.0979467000", \ - "0.0664748000, 0.0689370000, 0.0765853000, 0.1001573000, 0.1760706000, 0.4062581000, 1.0979747000", \ - "0.0945829000, 0.0971442000, 0.1041004000, 0.1222592000, 0.1847176000, 0.4070207000, 1.0979428000", \ - "0.1488095000, 0.1526727000, 0.1640613000, 0.1905898000, 0.2548909000, 0.4334452000, 1.0979301000", \ - "0.2391375000, 0.2450527000, 0.2628552000, 0.3068589000, 0.4064248000, 0.5969951000, 1.1472702000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2_1") { - leakage_power () { - value : 0.0042527000; - when : "!A&B"; - } - leakage_power () { - value : 0.0005535000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0003034000; - when : "A&B"; - } - leakage_power () { - value : 0.0027691000; - when : "A&!B"; - } - area : 3.7536000000; - cell_footprint : "sky130_fd_sc_hd__nor2"; - cell_leakage_power : 0.0019697000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040287000, 0.0040304000, 0.0040343000, 0.0040313000, 0.0040243000, 0.0040084000, 0.0039716000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003655800, -0.003724700, -0.003883500, -0.003886400, -0.003893300, -0.003909000, -0.003945400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024670000; - } - pin ("B") { - capacitance : 0.0023530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024958000, 0.0024923000, 0.0024842000, 0.0024914000, 0.0025080000, 0.0025464000, 0.0026348000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001703600, -0.001700200, -0.001692300, -0.001693300, -0.001695500, -0.001700800, -0.001712900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025010000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011792790, 0.0027813980, 0.0065600890, 0.0154723500, 0.0364924400, 0.0860695400"); - values("0.0033831000, 0.0023087000, -0.000245100, -0.006313400, -0.020688500, -0.054711300, -0.134953900", \ - "0.0032959000, 0.0022221000, -0.000312600, -0.006351000, -0.020726200, -0.054729100, -0.134959000", \ - "0.0032503000, 0.0021761000, -0.000331200, -0.006314900, -0.020650300, -0.054603000, -0.134870500", \ - "0.0030726000, 0.0020069000, -0.000507400, -0.006441700, -0.020731600, -0.054663600, -0.134880700", \ - "0.0032625000, 0.0021845000, -0.000354800, -0.006474000, -0.020854800, -0.054700800, -0.134913600", \ - "0.0041084000, 0.0029247000, 6.490000e-05, -0.005936600, -0.020424100, -0.054593100, -0.134844300", \ - "0.0058008000, 0.0046885000, 0.0018346000, -0.004658800, -0.019427000, -0.053837100, -0.134544700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011792790, 0.0027813980, 0.0065600890, 0.0154723500, 0.0364924400, 0.0860695400"); - values("0.0072133000, 0.0083823000, 0.0110600000, 0.0172660000, 0.0316026000, 0.0656529000, 0.1442872000", \ - "0.0070087000, 0.0081744000, 0.0108689000, 0.0171299000, 0.0314262000, 0.0651136000, 0.1442832000", \ - "0.0068800000, 0.0080154000, 0.0106724000, 0.0168250000, 0.0314744000, 0.0649365000, 0.1441691000", \ - "0.0067844000, 0.0079038000, 0.0105160000, 0.0166964000, 0.0310259000, 0.0647920000, 0.1440820000", \ - "0.0067126000, 0.0078404000, 0.0104623000, 0.0165733000, 0.0310240000, 0.0646135000, 0.1440148000", \ - "0.0065377000, 0.0076235000, 0.0104706000, 0.0166179000, 0.0310122000, 0.0648914000, 0.1440435000", \ - "0.0079056000, 0.0089073000, 0.0112540000, 0.0170768000, 0.0313416000, 0.0653377000, 0.1446737000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011792790, 0.0027813980, 0.0065600890, 0.0154723500, 0.0364924400, 0.0860695400"); - values("0.0001161000, -0.000884300, -0.003365600, -0.009388200, -0.023771700, -0.057797000, -0.138083900", \ - "-8.87000e-05, -0.001058900, -0.003479700, -0.009427700, -0.023753300, -0.057745400, -0.138026200", \ - "-0.000355700, -0.001342700, -0.003716400, -0.009594300, -0.023832200, -0.057775100, -0.138016100", \ - "-0.000425500, -0.001518700, -0.004020500, -0.009856300, -0.023974100, -0.057841600, -0.138049000", \ - "-0.000432100, -0.001497100, -0.004034400, -0.009923000, -0.024221000, -0.057956300, -0.138099100", \ - "0.0004539000, -0.000660000, -0.003442700, -0.009560000, -0.023989300, -0.058016800, -0.138155800", \ - "0.0026121000, 0.0012756000, -0.001701100, -0.008298900, -0.023249600, -0.057449100, -0.138009500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011792790, 0.0027813980, 0.0065600890, 0.0154723500, 0.0364924400, 0.0860695400"); - values("0.0062893000, 0.0075031000, 0.0101938000, 0.0163798000, 0.0307311000, 0.0646927000, 0.1447920000", \ - "0.0060386000, 0.0072036000, 0.0099546000, 0.0161864000, 0.0306119000, 0.0642636000, 0.1445428000", \ - "0.0059374000, 0.0070815000, 0.0096878000, 0.0158973000, 0.0304077000, 0.0641823000, 0.1434526000", \ - "0.0058546000, 0.0069660000, 0.0096178000, 0.0156518000, 0.0301002000, 0.0639702000, 0.1433623000", \ - "0.0060840000, 0.0071573000, 0.0096762000, 0.0157862000, 0.0301081000, 0.0640169000, 0.1440335000", \ - "0.0067959000, 0.0078057000, 0.0102727000, 0.0162380000, 0.0303135000, 0.0636023000, 0.1429686000", \ - "0.0087301000, 0.0096610000, 0.0120748000, 0.0184535000, 0.0319003000, 0.0648031000, 0.1440411000"); - } - } - max_capacitance : 0.0860700000; - max_transition : 1.4944790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0190360000, 0.0215947000, 0.0272198000, 0.0399461000, 0.0688945000, 0.1361845000, 0.2943552000", \ - "0.0238153000, 0.0263031000, 0.0319310000, 0.0446257000, 0.0735838000, 0.1409075000, 0.2990341000", \ - "0.0341733000, 0.0370188000, 0.0432750000, 0.0560966000, 0.0848920000, 0.1520304000, 0.3101353000", \ - "0.0477991000, 0.0526141000, 0.0623161000, 0.0802289000, 0.1116031000, 0.1786463000, 0.3368668000", \ - "0.0635656000, 0.0709430000, 0.0860044000, 0.1142329000, 0.1621650000, 0.2393694000, 0.3966667000", \ - "0.0750275000, 0.0862809000, 0.1098119000, 0.1529907000, 0.2291519000, 0.3512564000, 0.5416234000", \ - "0.0630542000, 0.0808831000, 0.1170295000, 0.1859119000, 0.3042667000, 0.4954561000, 0.7911051000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0535309000, 0.0624521000, 0.0827583000, 0.1296748000, 0.2403223000, 0.4964094000, 1.0910149000", \ - "0.0584658000, 0.0672655000, 0.0876976000, 0.1348434000, 0.2428248000, 0.5027195000, 1.0975248000", \ - "0.0704606000, 0.0790985000, 0.0992865000, 0.1457621000, 0.2562149000, 0.5105412000, 1.1113832000", \ - "0.0949138000, 0.1045912000, 0.1248307000, 0.1714398000, 0.2804020000, 0.5354027000, 1.1368554000", \ - "0.1338386000, 0.1471503000, 0.1748801000, 0.2287121000, 0.3391497000, 0.5938540000, 1.1942373000", \ - "0.1923603000, 0.2135827000, 0.2551632000, 0.3315146000, 0.4695703000, 0.7293924000, 1.3343304000", \ - "0.2908056000, 0.3221162000, 0.3846763000, 0.4995299000, 0.6933965000, 1.0300584000, 1.6428976000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0133173000, 0.0162387000, 0.0230975000, 0.0390614000, 0.0769627000, 0.1659429000, 0.3741285000", \ - "0.0132612000, 0.0160771000, 0.0229152000, 0.0390843000, 0.0769860000, 0.1659096000, 0.3747086000", \ - "0.0183004000, 0.0207453000, 0.0259583000, 0.0400061000, 0.0766724000, 0.1655208000, 0.3751109000", \ - "0.0296812000, 0.0331107000, 0.0402443000, 0.0528114000, 0.0824942000, 0.1650518000, 0.3746599000", \ - "0.0495575000, 0.0550513000, 0.0657323000, 0.0848695000, 0.1176947000, 0.1840762000, 0.3745960000", \ - "0.0846432000, 0.0934187000, 0.1097656000, 0.1411326000, 0.1905301000, 0.2697150000, 0.4213641000", \ - "0.1471779000, 0.1623777000, 0.1894495000, 0.2357859000, 0.3114916000, 0.4319934000, 0.6206120000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0397691000, 0.0511740000, 0.0780082000, 0.1417654000, 0.2909386000, 0.6475466000, 1.4665317000", \ - "0.0398254000, 0.0511983000, 0.0780980000, 0.1418391000, 0.2897509000, 0.6444150000, 1.4694822000", \ - "0.0398298000, 0.0512603000, 0.0781290000, 0.1409021000, 0.2915635000, 0.6396143000, 1.4640775000", \ - "0.0462081000, 0.0559536000, 0.0804090000, 0.1411384000, 0.2889892000, 0.6407167000, 1.4624811000", \ - "0.0668605000, 0.0775374000, 0.1017904000, 0.1540026000, 0.2925267000, 0.6394485000, 1.4691923000", \ - "0.1105513000, 0.1228485000, 0.1499894000, 0.2083700000, 0.3313576000, 0.6479490000, 1.4656883000", \ - "0.1863145000, 0.2034043000, 0.2404033000, 0.3140700000, 0.4557996000, 0.7493287000, 1.4878785000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0156296000, 0.0180104000, 0.0233638000, 0.0356609000, 0.0641406000, 0.1316836000, 0.2900434000", \ - "0.0203053000, 0.0227182000, 0.0281792000, 0.0404438000, 0.0691446000, 0.1361500000, 0.2948875000", \ - "0.0277223000, 0.0315402000, 0.0388281000, 0.0518945000, 0.0805566000, 0.1475413000, 0.3090947000", \ - "0.0359846000, 0.0422275000, 0.0539056000, 0.0741758000, 0.1070441000, 0.1739432000, 0.3341677000", \ - "0.0431602000, 0.0525956000, 0.0712007000, 0.1028897000, 0.1550372000, 0.2346605000, 0.3925809000", \ - "0.0404120000, 0.0560548000, 0.0842626000, 0.1340692000, 0.2156434000, 0.3426192000, 0.5366415000", \ - "0.0075956000, 0.0298035000, 0.0746855000, 0.1536548000, 0.2819046000, 0.4820727000, 0.7827049000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0409774000, 0.0500758000, 0.0706680000, 0.1172771000, 0.2268389000, 0.4830076000, 1.0878999000", \ - "0.0440666000, 0.0529172000, 0.0737508000, 0.1208034000, 0.2300006000, 0.4855337000, 1.0955047000", \ - "0.0553825000, 0.0640778000, 0.0837551000, 0.1309525000, 0.2402728000, 0.4961174000, 1.0969213000", \ - "0.0801953000, 0.0908979000, 0.1113433000, 0.1569330000, 0.2671649000, 0.5223477000, 1.1227607000", \ - "0.1184158000, 0.1348123000, 0.1659439000, 0.2226178000, 0.3299288000, 0.5862180000, 1.1893532000", \ - "0.1779249000, 0.2019334000, 0.2500242000, 0.3374095000, 0.4811848000, 0.7302756000, 1.3320954000", \ - "0.2813761000, 0.3149384000, 0.3830530000, 0.5107562000, 0.7322720000, 1.0770871000, 1.6773825000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0088665000, 0.0117921000, 0.0186609000, 0.0347135000, 0.0731656000, 0.1612023000, 0.3708196000", \ - "0.0096863000, 0.0122191000, 0.0186360000, 0.0344515000, 0.0726028000, 0.1622722000, 0.3730477000", \ - "0.0155484000, 0.0180238000, 0.0229369000, 0.0362456000, 0.0724510000, 0.1619080000, 0.3712491000", \ - "0.0266471000, 0.0300579000, 0.0372801000, 0.0514777000, 0.0790242000, 0.1632742000, 0.3706679000", \ - "0.0458007000, 0.0522172000, 0.0626350000, 0.0826596000, 0.1155174000, 0.1811881000, 0.3739281000", \ - "0.0806957000, 0.0910282000, 0.1072080000, 0.1383468000, 0.1888244000, 0.2668552000, 0.4209027000", \ - "0.1464894000, 0.1613612000, 0.1881425000, 0.2345852000, 0.3118086000, 0.4312395000, 0.6195141000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011792800, 0.0027814000, 0.0065600900, 0.0154724000, 0.0364924000, 0.0860695000"); - values("0.0397519000, 0.0512007000, 0.0779957000, 0.1409291000, 0.2896431000, 0.6418243000, 1.4797075000", \ - "0.0394845000, 0.0510389000, 0.0780166000, 0.1408854000, 0.2898597000, 0.6389512000, 1.4823202000", \ - "0.0400411000, 0.0509512000, 0.0778922000, 0.1410948000, 0.2898015000, 0.6397169000, 1.4658119000", \ - "0.0540333000, 0.0623788000, 0.0840599000, 0.1418888000, 0.2898861000, 0.6394330000, 1.4697440000", \ - "0.0787265000, 0.0913860000, 0.1159434000, 0.1637902000, 0.2942867000, 0.6427856000, 1.4728250000", \ - "0.1203677000, 0.1386865000, 0.1737311000, 0.2398944000, 0.3522298000, 0.6517846000, 1.4655828000", \ - "0.1892298000, 0.2147965000, 0.2652500000, 0.3617796000, 0.5241573000, 0.7896050000, 1.4944792000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2_2") { - leakage_power () { - value : 0.0036845000; - when : "!A&B"; - } - leakage_power () { - value : 0.0015349000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0002441000; - when : "A&B"; - } - leakage_power () { - value : 0.0022266000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nor2"; - cell_leakage_power : 0.0019225140; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0044010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083596000, 0.0083601000, 0.0083614000, 0.0083582000, 0.0083510000, 0.0083343000, 0.0082960000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007230700, -0.007335600, -0.007577500, -0.007590200, -0.007619600, -0.007687400, -0.007843500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046110000; - } - pin ("B") { - capacitance : 0.0044380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042515000, 0.0042461000, 0.0042335000, 0.0042552000, 0.0043054000, 0.0044212000, 0.0046879000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003435100, -0.003434600, -0.003433400, -0.003431600, -0.003427500, -0.003417900, -0.003395900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047400000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0073745000, 0.0061358000, 0.0029227000, -0.005283900, -0.026426800, -0.080952600, -0.220968900", \ - "0.0071484000, 0.0059227000, 0.0027561000, -0.005426000, -0.026525600, -0.080995400, -0.221066300", \ - "0.0069652000, 0.0057606000, 0.0026709000, -0.005482000, -0.026516900, -0.080944700, -0.220989400", \ - "0.0066225000, 0.0054307000, 0.0022739000, -0.005784300, -0.026727600, -0.081110600, -0.221070700", \ - "0.0068860000, 0.0056776000, 0.0025148000, -0.005681200, -0.026949600, -0.081233700, -0.221170300", \ - "0.0081474000, 0.0068761000, 0.0036039000, -0.004755800, -0.026103200, -0.081095500, -0.221037300", \ - "0.0113450000, 0.0099364000, 0.0065013000, -0.002350900, -0.024201900, -0.079607500, -0.220424300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0128950000, 0.0142341000, 0.0176613000, 0.0260292000, 0.0472620000, 0.1013471000, 0.2397798000", \ - "0.0125529000, 0.0138972000, 0.0172895000, 0.0257286000, 0.0471062000, 0.1014395000, 0.2397332000", \ - "0.0123128000, 0.0136308000, 0.0169836000, 0.0253620000, 0.0470654000, 0.1010472000, 0.2405892000", \ - "0.0121624000, 0.0134507000, 0.0167624000, 0.0251620000, 0.0466846000, 0.1011173000, 0.2394514000", \ - "0.0120071000, 0.0133236000, 0.0165791000, 0.0248679000, 0.0461908000, 0.1003002000, 0.2390999000", \ - "0.0120678000, 0.0133443000, 0.0165953000, 0.0249152000, 0.0460655000, 0.1006008000, 0.2386959000", \ - "0.0131879000, 0.0142743000, 0.0173908000, 0.0252415000, 0.0465944000, 0.1012898000, 0.2402129000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("-0.000488800, -0.001610300, -0.004610500, -0.012699500, -0.033897600, -0.088527100, -0.228713000", \ - "-0.000860600, -0.001954500, -0.004867700, -0.012771300, -0.033849200, -0.088390900, -0.228544400", \ - "-0.001308000, -0.002404100, -0.005255500, -0.013066500, -0.033966500, -0.088371900, -0.228471900", \ - "-0.001682500, -0.002856900, -0.005747100, -0.013543600, -0.034294800, -0.088527400, -0.228496400", \ - "-0.001181600, -0.002629000, -0.005764800, -0.013812100, -0.034742900, -0.088823800, -0.228644100", \ - "4.680000e-05, -0.001317200, -0.004744900, -0.013213300, -0.034350400, -0.088936900, -0.228750400", \ - "0.0039358000, 0.0023853000, -0.001389300, -0.010687400, -0.032925900, -0.087914100, -0.228633000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012817810, 0.0032859260, 0.0084236780, 0.0215946300, 0.0553591700, 0.1419167000"); - values("0.0120659000, 0.0135219000, 0.0170708000, 0.0256150000, 0.0471589000, 0.1013624000, 0.2405368000", \ - "0.0116343000, 0.0130064000, 0.0164398000, 0.0251373000, 0.0466608000, 0.1009385000, 0.2394738000", \ - "0.0114624000, 0.0127780000, 0.0161374000, 0.0245983000, 0.0461837000, 0.1014518000, 0.2399905000", \ - "0.0113236000, 0.0126046000, 0.0159888000, 0.0243982000, 0.0455761000, 0.1003875000, 0.2398083000", \ - "0.0119148000, 0.0131421000, 0.0162965000, 0.0243881000, 0.0456010000, 0.0996798000, 0.2386542000", \ - "0.0131292000, 0.0142935000, 0.0174108000, 0.0254979000, 0.0460363000, 0.0994893000, 0.2381229000", \ - "0.0159512000, 0.0169725000, 0.0197795000, 0.0275421000, 0.0484078000, 0.1013567000, 0.2383341000"); - } - } - max_capacitance : 0.1419170000; - max_transition : 1.4983880000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0169765000, 0.0186137000, 0.0225047000, 0.0317480000, 0.0538005000, 0.1082873000, 0.2463683000", \ - "0.0218970000, 0.0234217000, 0.0272035000, 0.0363347000, 0.0583460000, 0.1129020000, 0.2511329000", \ - "0.0315818000, 0.0336417000, 0.0382211000, 0.0476932000, 0.0692584000, 0.1237162000, 0.2619326000", \ - "0.0436403000, 0.0466044000, 0.0537263000, 0.0682395000, 0.0954174000, 0.1499542000, 0.2880661000", \ - "0.0557866000, 0.0604313000, 0.0712855000, 0.0937865000, 0.1360242000, 0.2087881000, 0.3476518000", \ - "0.0592939000, 0.0665427000, 0.0832647000, 0.1176225000, 0.1842997000, 0.2985803000, 0.4848358000", \ - "0.0289450000, 0.0404634000, 0.0666192000, 0.1215940000, 0.2253026000, 0.4052740000, 0.6964460000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0598512000, 0.0661608000, 0.0818005000, 0.1204893000, 0.2178144000, 0.4658339000, 1.1001068000", \ - "0.0645408000, 0.0707845000, 0.0864186000, 0.1252582000, 0.2230472000, 0.4756194000, 1.1065003000", \ - "0.0774803000, 0.0835427000, 0.0989149000, 0.1377132000, 0.2369799000, 0.4852300000, 1.1255878000", \ - "0.1046485000, 0.1111289000, 0.1266699000, 0.1651232000, 0.2640097000, 0.5126880000, 1.1476432000", \ - "0.1485323000, 0.1574588000, 0.1780745000, 0.2236462000, 0.3228659000, 0.5733475000, 1.2074964000", \ - "0.2165370000, 0.2308327000, 0.2627495000, 0.3270954000, 0.4536868000, 0.7105454000, 1.3508183000", \ - "0.3247446000, 0.3481303000, 0.3973368000, 0.4979204000, 0.6811013000, 1.0181618000, 1.6702481000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0121913000, 0.0139872000, 0.0184149000, 0.0295312000, 0.0577435000, 0.1302407000, 0.3149928000", \ - "0.0122711000, 0.0139194000, 0.0181640000, 0.0292849000, 0.0576226000, 0.1303335000, 0.3149339000", \ - "0.0174991000, 0.0189791000, 0.0224710000, 0.0313296000, 0.0576492000, 0.1302361000, 0.3154841000", \ - "0.0278304000, 0.0301365000, 0.0351356000, 0.0458227000, 0.0667332000, 0.1312678000, 0.3150509000", \ - "0.0462946000, 0.0497118000, 0.0579389000, 0.0734008000, 0.1022856000, 0.1564527000, 0.3181727000", \ - "0.0787279000, 0.0845512000, 0.0973526000, 0.1221569000, 0.1662236000, 0.2417725000, 0.3770034000", \ - "0.1377398000, 0.1473311000, 0.1670777000, 0.2068850000, 0.2752654000, 0.3887180000, 0.5769948000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0387164000, 0.0465397000, 0.0671545000, 0.1191083000, 0.2519610000, 0.5924332000, 1.4660573000", \ - "0.0387927000, 0.0467894000, 0.0671140000, 0.1193467000, 0.2531905000, 0.5963443000, 1.4642677000", \ - "0.0388228000, 0.0468128000, 0.0671166000, 0.1193101000, 0.2541284000, 0.5942123000, 1.4723758000", \ - "0.0428648000, 0.0500679000, 0.0690108000, 0.1196403000, 0.2542018000, 0.5942771000, 1.4705871000", \ - "0.0609025000, 0.0684849000, 0.0876629000, 0.1321587000, 0.2555057000, 0.5936081000, 1.4707048000", \ - "0.0995867000, 0.1085114000, 0.1304543000, 0.1799390000, 0.2948676000, 0.6014265000, 1.4671513000", \ - "0.1783026000, 0.1896907000, 0.2178831000, 0.2801153000, 0.4119040000, 0.7022209000, 1.4890928000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0141760000, 0.0156199000, 0.0191598000, 0.0278052000, 0.0492845000, 0.1040127000, 0.2438898000", \ - "0.0186334000, 0.0202421000, 0.0238568000, 0.0324836000, 0.0541217000, 0.1089733000, 0.2497110000", \ - "0.0246079000, 0.0272212000, 0.0327980000, 0.0435904000, 0.0654035000, 0.1199132000, 0.2625150000", \ - "0.0304144000, 0.0345370000, 0.0434582000, 0.0606458000, 0.0907239000, 0.1459215000, 0.2876185000", \ - "0.0320202000, 0.0386238000, 0.0528719000, 0.0800952000, 0.1274019000, 0.2048295000, 0.3456997000", \ - "0.0190370000, 0.0289388000, 0.0516526000, 0.0945865000, 0.1686562000, 0.2903307000, 0.4836087000", \ - "-0.037415200, -0.022069200, 0.0132257000, 0.0813341000, 0.1994799000, 0.3909838000, 0.6922216000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0395814000, 0.0463244000, 0.0626076000, 0.1021031000, 0.2018021000, 0.4509545000, 1.0874180000", \ - "0.0428289000, 0.0490655000, 0.0650582000, 0.1051309000, 0.2032878000, 0.4522231000, 1.0868446000", \ - "0.0543258000, 0.0604069000, 0.0758686000, 0.1145287000, 0.2132721000, 0.4656956000, 1.1023106000", \ - "0.0798983000, 0.0876051000, 0.1039779000, 0.1416236000, 0.2412836000, 0.4923889000, 1.1289197000", \ - "0.1193988000, 0.1314784000, 0.1568444000, 0.2073465000, 0.3057597000, 0.5536542000, 1.1896503000", \ - "0.1842142000, 0.2015711000, 0.2396233000, 0.3170890000, 0.4540920000, 0.7055990000, 1.3411834000", \ - "0.3025458000, 0.3261292000, 0.3795286000, 0.4912014000, 0.6986479000, 1.0530292000, 1.6922767000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0070459000, 0.0087223000, 0.0131490000, 0.0243219000, 0.0531277000, 0.1275299000, 0.3138667000", \ - "0.0082968000, 0.0096261000, 0.0134577000, 0.0243722000, 0.0530534000, 0.1277071000, 0.3147392000", \ - "0.0137204000, 0.0154245000, 0.0192885000, 0.0275155000, 0.0535135000, 0.1268677000, 0.3165656000", \ - "0.0235946000, 0.0260140000, 0.0315956000, 0.0427767000, 0.0643198000, 0.1286790000, 0.3161398000", \ - "0.0416952000, 0.0453546000, 0.0544462000, 0.0705738000, 0.1002252000, 0.1543953000, 0.3188899000", \ - "0.0737656000, 0.0801945000, 0.0942736000, 0.1194076000, 0.1649284000, 0.2402973000, 0.3775331000", \ - "0.1354639000, 0.1452008000, 0.1697280000, 0.2075639000, 0.2767224000, 0.3894367000, 0.5774533000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012817800, 0.0032859300, 0.0084236800, 0.0215946000, 0.0553592000, 0.1419170000"); - values("0.0383727000, 0.0464427000, 0.0670202000, 0.1193254000, 0.2544325000, 0.5955795000, 1.4724479000", \ - "0.0381824000, 0.0460213000, 0.0669146000, 0.1192609000, 0.2525813000, 0.5925727000, 1.4656973000", \ - "0.0381865000, 0.0458870000, 0.0664339000, 0.1192298000, 0.2523023000, 0.5972254000, 1.4709203000", \ - "0.0518557000, 0.0576092000, 0.0733776000, 0.1196992000, 0.2540167000, 0.5957025000, 1.4724416000", \ - "0.0736324000, 0.0839464000, 0.1035009000, 0.1448334000, 0.2575590000, 0.5951247000, 1.4645798000", \ - "0.1118042000, 0.1259139000, 0.1547507000, 0.2130005000, 0.3210224000, 0.6068745000, 1.4703324000", \ - "0.1760784000, 0.1950611000, 0.2384363000, 0.3231547000, 0.4775236000, 0.7496009000, 1.4983882000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2_4") { - leakage_power () { - value : 0.0040121000; - when : "!A&B"; - } - leakage_power () { - value : 0.0038425000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0004326000; - when : "A&B"; - } - leakage_power () { - value : 0.0025266000; - when : "A&!B"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__nor2"; - cell_leakage_power : 0.0027034450; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0087330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0166262000, 0.0166196000, 0.0166045000, 0.0166015000, 0.0165948000, 0.0165793000, 0.0165435000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014203000, -0.014451100, -0.015023100, -0.015052500, -0.015120400, -0.015276800, -0.015637300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091620000; - } - pin ("B") { - capacitance : 0.0086870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081436000, 0.0081226000, 0.0080741000, 0.0081109000, 0.0081958000, 0.0083914000, 0.0088424000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006803300, -0.006799600, -0.006791000, -0.006789500, -0.006786200, -0.006778400, -0.006760500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092890000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0145888000, 0.0131288000, 0.0090218000, -0.002561700, -0.035331800, -0.128296000, -0.391244100", \ - "0.0142153000, 0.0127769000, 0.0086766000, -0.002845900, -0.035513400, -0.128443600, -0.391371600", \ - "0.0138944000, 0.0125050000, 0.0084683000, -0.002870700, -0.035438400, -0.128239700, -0.391195500", \ - "0.0130502000, 0.0116242000, 0.0076562000, -0.003648700, -0.035904100, -0.128573600, -0.391304800", \ - "0.0136694000, 0.0122110000, 0.0081994000, -0.003201600, -0.036291200, -0.128826400, -0.391466700", \ - "0.0160415000, 0.0146191000, 0.0104409000, -0.002234800, -0.035401700, -0.128272600, -0.391073900", \ - "0.0215214000, 0.0200398000, 0.0154086000, 0.0030774000, -0.031095100, -0.125725300, -0.390139800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0249433000, 0.0265426000, 0.0309809000, 0.0430860000, 0.0763783000, 0.1683058000, 0.4283017000", \ - "0.0242285000, 0.0258172000, 0.0302205000, 0.0424180000, 0.0757326000, 0.1680930000, 0.4281469000", \ - "0.0237443000, 0.0252968000, 0.0295957000, 0.0415580000, 0.0753023000, 0.1681136000, 0.4278681000", \ - "0.0234331000, 0.0249690000, 0.0291991000, 0.0410534000, 0.0741796000, 0.1671085000, 0.4310648000", \ - "0.0231148000, 0.0246845000, 0.0288640000, 0.0405805000, 0.0736300000, 0.1667428000, 0.4301930000", \ - "0.0232302000, 0.0247032000, 0.0288746000, 0.0406072000, 0.0737207000, 0.1665469000, 0.4262356000", \ - "0.0249650000, 0.0262105000, 0.0300107000, 0.0411471000, 0.0743474000, 0.1672062000, 0.4281072000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("-5.18000e-05, -0.001346100, -0.005112600, -0.016321000, -0.049065600, -0.142248100, -0.405451700", \ - "-0.000782300, -0.002019900, -0.005667100, -0.016589700, -0.049012800, -0.142011800, -0.405117700", \ - "-0.001647300, -0.002906000, -0.006470400, -0.017263100, -0.049292900, -0.142004900, -0.404946800", \ - "-0.002350500, -0.003672800, -0.007446400, -0.018167700, -0.050101100, -0.142319400, -0.404969500", \ - "-0.001778100, -0.003062700, -0.007073500, -0.018577100, -0.050980400, -0.142884000, -0.405222200", \ - "0.0003238000, -0.001299400, -0.005673300, -0.017701800, -0.050703300, -0.143048500, -0.405359200", \ - "0.0081546000, 0.0065841000, 0.0007174000, -0.012229700, -0.047334100, -0.141374600, -0.405403900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014103010, 0.0039778980, 0.0112200700, 0.0316473500, 0.0892646000, 0.2517799000"); - values("0.0234499000, 0.0252083000, 0.0298260000, 0.0424246000, 0.0757155000, 0.1681166000, 0.4281616000", \ - "0.0225901000, 0.0242770000, 0.0287232000, 0.0410645000, 0.0751239000, 0.1682812000, 0.4278748000", \ - "0.0220176000, 0.0236259000, 0.0279958000, 0.0403448000, 0.0738392000, 0.1684640000, 0.4277499000", \ - "0.0224831000, 0.0239328000, 0.0280787000, 0.0397846000, 0.0728287000, 0.1662264000, 0.4279252000", \ - "0.0234005000, 0.0248091000, 0.0286947000, 0.0400777000, 0.0728604000, 0.1654970000, 0.4262714000", \ - "0.0253165000, 0.0268912000, 0.0307984000, 0.0422785000, 0.0742481000, 0.1664044000, 0.4285354000", \ - "0.0315872000, 0.0323786000, 0.0359486000, 0.0468016000, 0.0779553000, 0.1683928000, 0.4261670000"); - } - } - max_capacitance : 0.2517800000; - max_transition : 1.4964490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0169715000, 0.0179898000, 0.0207708000, 0.0278877000, 0.0464088000, 0.0962407000, 0.2342976000", \ - "0.0218200000, 0.0227798000, 0.0254185000, 0.0324638000, 0.0509264000, 0.1007439000, 0.2387181000", \ - "0.0311648000, 0.0324597000, 0.0357109000, 0.0435209000, 0.0617677000, 0.1114110000, 0.2496350000", \ - "0.0424904000, 0.0444516000, 0.0494231000, 0.0614109000, 0.0862029000, 0.1371073000, 0.2749299000", \ - "0.0523674000, 0.0554190000, 0.0631869000, 0.0816469000, 0.1203738000, 0.1924431000, 0.3342928000", \ - "0.0511493000, 0.0557858000, 0.0678160000, 0.0966514000, 0.1572204000, 0.2690975000, 0.4647971000", \ - "0.0095339000, 0.0168776000, 0.0358525000, 0.0808120000, 0.1756667000, 0.3539680000, 0.6596342000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0622744000, 0.0664765000, 0.0779111000, 0.1094290000, 0.1954166000, 0.4332344000, 1.1041421000", \ - "0.0667856000, 0.0709660000, 0.0823530000, 0.1140250000, 0.2003005000, 0.4389736000, 1.1103100000", \ - "0.0798638000, 0.0838861000, 0.0952087000, 0.1260894000, 0.2131699000, 0.4561659000, 1.1249001000", \ - "0.1076138000, 0.1118374000, 0.1228784000, 0.1538689000, 0.2394934000, 0.4796278000, 1.1576793000", \ - "0.1527445000, 0.1587778000, 0.1737594000, 0.2112743000, 0.2997347000, 0.5399549000, 1.2174648000", \ - "0.2263442000, 0.2352630000, 0.2582115000, 0.3114440000, 0.4269287000, 0.6780203000, 1.3543581000", \ - "0.3456880000, 0.3598186000, 0.3963414000, 0.4799576000, 0.6491258000, 0.9774964000, 1.6728150000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0124766000, 0.0136194000, 0.0167281000, 0.0253355000, 0.0492240000, 0.1167727000, 0.3080123000", \ - "0.0125080000, 0.0135257000, 0.0164962000, 0.0249712000, 0.0490925000, 0.1167750000, 0.3080687000", \ - "0.0176730000, 0.0187179000, 0.0212990000, 0.0279611000, 0.0495384000, 0.1167363000, 0.3085307000", \ - "0.0277003000, 0.0291974000, 0.0329441000, 0.0415591000, 0.0609881000, 0.1191021000, 0.3082691000", \ - "0.0453959000, 0.0477238000, 0.0535742000, 0.0665357000, 0.0940910000, 0.1479985000, 0.3128849000", \ - "0.0771960000, 0.0809411000, 0.0904556000, 0.1114286000, 0.1515543000, 0.2297037000, 0.3762480000", \ - "0.1353600000, 0.1415310000, 0.1563482000, 0.1899870000, 0.2544940000, 0.3675451000, 0.5692316000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0402232000, 0.0454527000, 0.0599119000, 0.1017079000, 0.2190281000, 0.5447648000, 1.4649204000", \ - "0.0402643000, 0.0454902000, 0.0599241000, 0.1014302000, 0.2177543000, 0.5452596000, 1.4655323000", \ - "0.0403483000, 0.0455417000, 0.0602361000, 0.1015483000, 0.2189719000, 0.5471781000, 1.4664657000", \ - "0.0438942000, 0.0485808000, 0.0622658000, 0.1016263000, 0.2180911000, 0.5448665000, 1.4783624000", \ - "0.0609245000, 0.0662622000, 0.0800483000, 0.1158114000, 0.2220661000, 0.5454546000, 1.4779042000", \ - "0.0980405000, 0.1042219000, 0.1197569000, 0.1601521000, 0.2630935000, 0.5558799000, 1.4675843000", \ - "0.1757244000, 0.1831104000, 0.2033222000, 0.2535891000, 0.3716539000, 0.6541388000, 1.4863820000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0138624000, 0.0147903000, 0.0172767000, 0.0237678000, 0.0414504000, 0.0905806000, 0.2287096000", \ - "0.0182299000, 0.0193012000, 0.0218561000, 0.0283958000, 0.0462271000, 0.0953179000, 0.2356907000", \ - "0.0237826000, 0.0254619000, 0.0296104000, 0.0387528000, 0.0571306000, 0.1064740000, 0.2446131000", \ - "0.0285800000, 0.0312624000, 0.0379018000, 0.0522514000, 0.0802141000, 0.1320774000, 0.2707602000", \ - "0.0280358000, 0.0322023000, 0.0425710000, 0.0657560000, 0.1098734000, 0.1865268000, 0.3294210000", \ - "0.0095458000, 0.0162749000, 0.0325911000, 0.0691303000, 0.1390075000, 0.2584541000, 0.4607315000", \ - "-0.059366700, -0.048490700, -0.023510800, 0.0340899000, 0.1441704000, 0.3356903000, 0.6527048000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0419300000, 0.0465356000, 0.0584431000, 0.0910134000, 0.1781699000, 0.4159947000, 1.0871927000", \ - "0.0450207000, 0.0493287000, 0.0609082000, 0.0928722000, 0.1826169000, 0.4218549000, 1.0933071000", \ - "0.0562287000, 0.0602519000, 0.0715604000, 0.1031770000, 0.1898992000, 0.4331795000, 1.1038219000", \ - "0.0833635000, 0.0884081000, 0.1007163000, 0.1308756000, 0.2159345000, 0.4562961000, 1.1357739000", \ - "0.1253656000, 0.1329178000, 0.1526407000, 0.1948177000, 0.2835507000, 0.5216512000, 1.1936074000", \ - "0.1955487000, 0.2069636000, 0.2353216000, 0.3007529000, 0.4295797000, 0.6782531000, 1.3499469000", \ - "0.3272712000, 0.3421144000, 0.3818280000, 0.4756208000, 0.6683371000, 1.0252291000, 1.7070267000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0068857000, 0.0079172000, 0.0108661000, 0.0193111000, 0.0428918000, 0.1091994000, 0.2961055000", \ - "0.0081798000, 0.0089718000, 0.0114750000, 0.0193212000, 0.0429388000, 0.1092325000, 0.2976890000", \ - "0.0134535000, 0.0145305000, 0.0174647000, 0.0238283000, 0.0439932000, 0.1091723000, 0.2962383000", \ - "0.0230443000, 0.0246661000, 0.0286775000, 0.0381474000, 0.0569112000, 0.1120622000, 0.2984915000", \ - "0.0408158000, 0.0432319000, 0.0497885000, 0.0638828000, 0.0916016000, 0.1426618000, 0.3020172000", \ - "0.0731927000, 0.0775736000, 0.0871061000, 0.1086018000, 0.1501374000, 0.2266512000, 0.3695773000", \ - "0.1334633000, 0.1400780000, 0.1583683000, 0.1922647000, 0.2549426000, 0.3658019000, 0.5634401000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014103000, 0.0039779000, 0.0112201000, 0.0316474000, 0.0892646000, 0.2517800000"); - values("0.0398289000, 0.0452207000, 0.0597080000, 0.1014653000, 0.2181662000, 0.5454607000, 1.4650987000", \ - "0.0395948000, 0.0450032000, 0.0598076000, 0.1013858000, 0.2193156000, 0.5467820000, 1.4662073000", \ - "0.0394401000, 0.0444469000, 0.0593656000, 0.1013186000, 0.2176547000, 0.5498381000, 1.4670208000", \ - "0.0524386000, 0.0563191000, 0.0668484000, 0.1029512000, 0.2178261000, 0.5451701000, 1.4725396000", \ - "0.0749895000, 0.0802406000, 0.0969379000, 0.1303689000, 0.2258270000, 0.5478105000, 1.4688503000", \ - "0.1122800000, 0.1208849000, 0.1430223000, 0.1934740000, 0.2917642000, 0.5620057000, 1.4755858000", \ - "0.1741214000, 0.1877213000, 0.2188592000, 0.2915491000, 0.4369753000, 0.7131835000, 1.4964487000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2_8") { - leakage_power () { - value : 0.0052252000; - when : "!A&B"; - } - leakage_power () { - value : 0.0089170000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0304538000; - when : "A&B"; - } - leakage_power () { - value : 0.0033195000; - when : "A&!B"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__nor2"; - cell_leakage_power : 0.0119788500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0169770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0160990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0328015000, 0.0327925000, 0.0327720000, 0.0327651000, 0.0327492000, 0.0327128000, 0.0326289000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.027975000, -0.028472500, -0.029619200, -0.029651700, -0.029726700, -0.029899600, -0.030298100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0178550000; - } - pin ("B") { - capacitance : 0.0168590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0156850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155097000, 0.0154846000, 0.0154270000, 0.0154879000, 0.0156284000, 0.0159524000, 0.0166992000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013536600, -0.013546200, -0.013568400, -0.013561100, -0.013544500, -0.013506200, -0.013417900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0180320000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015437090, 0.0047660740, 0.0147148600, 0.0454309200, 0.1402642000, 0.4330543000"); - values("0.0287614000, 0.0270941000, 0.0219603000, 0.0059743000, -0.043253300, -0.196066300, -0.669809100", \ - "0.0281109000, 0.0264513000, 0.0213520000, 0.0055176000, -0.043629700, -0.196498400, -0.670061900", \ - "0.0276275000, 0.0260196000, 0.0210079000, 0.0053459000, -0.043439100, -0.196046000, -0.669560100", \ - "0.0259752000, 0.0243554000, 0.0193939000, 0.0039083000, -0.044347600, -0.196750900, -0.670088800", \ - "0.0264983000, 0.0248785000, 0.0199472000, 0.0037660000, -0.045685100, -0.197367300, -0.670335300", \ - "0.0299247000, 0.0281978000, 0.0229075000, 0.0072699000, -0.043729000, -0.196523500, -0.669801300", \ - "0.0405168000, 0.0386630000, 0.0329572000, 0.0159012000, -0.036029700, -0.192117600, -0.668230600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015437090, 0.0047660740, 0.0147148600, 0.0454309200, 0.1402642000, 0.4330543000"); - values("0.0485691000, 0.0504218000, 0.0560263000, 0.0727050000, 0.1220704000, 0.2740585000, 0.7422944000", \ - "0.0471913000, 0.0489983000, 0.0544773000, 0.0712350000, 0.1213667000, 0.2739965000, 0.7421079000", \ - "0.0461688000, 0.0479250000, 0.0534082000, 0.0701652000, 0.1202508000, 0.2750931000, 0.7479051000", \ - "0.0455308000, 0.0472694000, 0.0525746000, 0.0690197000, 0.1188887000, 0.2720387000, 0.7435090000", \ - "0.0448136000, 0.0465441000, 0.0518959000, 0.0680106000, 0.1177731000, 0.2705709000, 0.7422387000", \ - "0.0449695000, 0.0466591000, 0.0519315000, 0.0681252000, 0.1181533000, 0.2707345000, 0.7427643000", \ - "0.0476205000, 0.0491070000, 0.0537981000, 0.0690460000, 0.1194539000, 0.2737545000, 0.7412837000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015437090, 0.0047660740, 0.0147148600, 0.0454309200, 0.1402642000, 0.4330543000"); - values("0.0007795000, -0.000678300, -0.005322800, -0.020459200, -0.069333400, -0.222539500, -0.696716200", \ - "-0.000478100, -0.001882300, -0.006410000, -0.021119300, -0.069318100, -0.222131800, -0.696083900", \ - "-0.002137900, -0.003553800, -0.008058500, -0.022585400, -0.070042600, -0.222072400, -0.695667300", \ - "-0.003772600, -0.005207200, -0.009839200, -0.024467600, -0.071644000, -0.222766200, -0.695801800", \ - "-0.002548000, -0.004151900, -0.009763100, -0.025155600, -0.073038200, -0.224068500, -0.696349100", \ - "0.0008337000, -0.000971300, -0.006518600, -0.023116200, -0.072095300, -0.224076400, -0.696643600", \ - "0.0143394000, 0.0124367000, 0.0072470000, -0.013173800, -0.065824400, -0.222052100, -0.696855100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015437090, 0.0047660740, 0.0147148600, 0.0454309200, 0.1402642000, 0.4330543000"); - values("0.0463488000, 0.0483530000, 0.0545126000, 0.0719742000, 0.1227204000, 0.2752506000, 0.7462117000", \ - "0.0444147000, 0.0463534000, 0.0520742000, 0.0695950000, 0.1211187000, 0.2756151000, 0.7436033000", \ - "0.0435556000, 0.0453259000, 0.0506918000, 0.0674969000, 0.1186648000, 0.2731151000, 0.7431602000", \ - "0.0436569000, 0.0454137000, 0.0506665000, 0.0670226000, 0.1166619000, 0.2709268000, 0.7418378000", \ - "0.0441636000, 0.0458296000, 0.0509624000, 0.0668216000, 0.1161251000, 0.2699872000, 0.7418663000", \ - "0.0485371000, 0.0501102000, 0.0549468000, 0.0700585000, 0.1207402000, 0.2712104000, 0.7366308000", \ - "0.0595213000, 0.0608326000, 0.0652265000, 0.0795306000, 0.1257943000, 0.2745302000, 0.7436020000"); - } - } - max_capacitance : 0.4330540000; - max_transition : 1.5005290000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0197774000, 0.0204758000, 0.0225789000, 0.0285550000, 0.0452383000, 0.0936334000, 0.2390254000", \ - "0.0243005000, 0.0249771000, 0.0270058000, 0.0329009000, 0.0495266000, 0.0978096000, 0.2436393000", \ - "0.0336286000, 0.0344923000, 0.0370112000, 0.0435521000, 0.0600810000, 0.1081399000, 0.2537492000", \ - "0.0449409000, 0.0462075000, 0.0498801000, 0.0595694000, 0.0825186000, 0.1328829000, 0.2783699000", \ - "0.0545276000, 0.0564866000, 0.0618402000, 0.0769283000, 0.1122493000, 0.1841828000, 0.3357790000", \ - "0.0506918000, 0.0536284000, 0.0621847000, 0.0852320000, 0.1399801000, 0.2508781000, 0.4605185000", \ - "0.0032813000, 0.0077170000, 0.0209127000, 0.0568531000, 0.1416175000, 0.3168178000, 0.6408177000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0687306000, 0.0715801000, 0.0802060000, 0.1054978000, 0.1803611000, 0.4089183000, 1.1125542000", \ - "0.0730061000, 0.0758128000, 0.0842936000, 0.1097438000, 0.1850888000, 0.4184216000, 1.1192198000", \ - "0.0857158000, 0.0884081000, 0.0967772000, 0.1221056000, 0.1977227000, 0.4299323000, 1.1402169000", \ - "0.1133531000, 0.1161430000, 0.1245646000, 0.1495367000, 0.2253747000, 0.4549209000, 1.1724933000", \ - "0.1594456000, 0.1631723000, 0.1743075000, 0.2045814000, 0.2837072000, 0.5136362000, 1.2238578000", \ - "0.2357745000, 0.2414359000, 0.2577646000, 0.3006094000, 0.4040986000, 0.6484052000, 1.3545438000", \ - "0.3637627000, 0.3726655000, 0.3984071000, 0.4654535000, 0.6168954000, 0.9368591000, 1.6680478000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0158439000, 0.0166219000, 0.0190921000, 0.0267082000, 0.0502291000, 0.1240099000, 0.3545708000", \ - "0.0154748000, 0.0162672000, 0.0186701000, 0.0262501000, 0.0500650000, 0.1241418000, 0.3544244000", \ - "0.0196745000, 0.0205146000, 0.0227867000, 0.0291055000, 0.0506472000, 0.1240789000, 0.3546221000", \ - "0.0290299000, 0.0300918000, 0.0329127000, 0.0413497000, 0.0622279000, 0.1271352000, 0.3544787000", \ - "0.0464337000, 0.0483598000, 0.0534009000, 0.0643186000, 0.0906441000, 0.1559740000, 0.3588972000", \ - "0.0790082000, 0.0813495000, 0.0880000000, 0.1053273000, 0.1440244000, 0.2277055000, 0.4211807000", \ - "0.1378229000, 0.1416394000, 0.1525105000, 0.1793503000, 0.2395067000, 0.3563106000, 0.5903218000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0452421000, 0.0486069000, 0.0593287000, 0.0923898000, 0.1940042000, 0.5082929000, 1.4714202000", \ - "0.0450887000, 0.0484647000, 0.0592052000, 0.0923456000, 0.1943445000, 0.5100345000, 1.4763820000", \ - "0.0452822000, 0.0487334000, 0.0593622000, 0.0924290000, 0.1940613000, 0.5109930000, 1.4901040000", \ - "0.0482495000, 0.0514302000, 0.0610977000, 0.0928649000, 0.1942859000, 0.5079019000, 1.4844482000", \ - "0.0646949000, 0.0679782000, 0.0783681000, 0.1076980000, 0.1998871000, 0.5093160000, 1.4769374000", \ - "0.1003077000, 0.1041185000, 0.1153314000, 0.1480234000, 0.2412771000, 0.5202619000, 1.4813695000", \ - "0.1771377000, 0.1818284000, 0.1956129000, 0.2354224000, 0.3402287000, 0.6185717000, 1.4929483000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0150784000, 0.0157153000, 0.0175184000, 0.0226916000, 0.0374287000, 0.0819137000, 0.2181240000", \ - "0.0193918000, 0.0200514000, 0.0219379000, 0.0271700000, 0.0421241000, 0.0864426000, 0.2227483000", \ - "0.0250808000, 0.0261405000, 0.0291474000, 0.0366447000, 0.0528500000, 0.0973343000, 0.2335750000", \ - "0.0296527000, 0.0313417000, 0.0360942000, 0.0479739000, 0.0733676000, 0.1226988000, 0.2594080000", \ - "0.0278524000, 0.0304945000, 0.0381239000, 0.0570227000, 0.0972732000, 0.1728238000, 0.3172400000", \ - "0.0061384000, 0.0104043000, 0.0224089000, 0.0522493000, 0.1157816000, 0.2341154000, 0.4445879000", \ - "-0.071036600, -0.064388500, -0.045444100, 0.0001765000, 0.1022099000, 0.2914796000, 0.6203900000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0471657000, 0.0501632000, 0.0594878000, 0.0860986000, 0.1624637000, 0.3917942000, 1.1025658000", \ - "0.0494162000, 0.0523813000, 0.0611073000, 0.0877580000, 0.1650027000, 0.3984238000, 1.1015601000", \ - "0.0604727000, 0.0632295000, 0.0714539000, 0.0968115000, 0.1748347000, 0.4056060000, 1.1123898000", \ - "0.0885102000, 0.0918695000, 0.1010090000, 0.1252865000, 0.2002996000, 0.4315593000, 1.1398196000", \ - "0.1332741000, 0.1381707000, 0.1521794000, 0.1882895000, 0.2681473000, 0.4984124000, 1.2075080000", \ - "0.2090579000, 0.2162937000, 0.2370784000, 0.2901058000, 0.4104640000, 0.6546906000, 1.3585501000", \ - "0.3511713000, 0.3607008000, 0.3894551000, 0.4656350000, 0.6416651000, 0.9977307000, 1.7166861000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0073398000, 0.0079919000, 0.0100282000, 0.0163893000, 0.0362007000, 0.0974516000, 0.2859552000", \ - "0.0084012000, 0.0089060000, 0.0106398000, 0.0165183000, 0.0362222000, 0.0973674000, 0.2860255000", \ - "0.0135331000, 0.0142641000, 0.0162065000, 0.0215728000, 0.0378543000, 0.0973951000, 0.2861389000", \ - "0.0230536000, 0.0240481000, 0.0269957000, 0.0344133000, 0.0521442000, 0.1014274000, 0.2866271000", \ - "0.0408479000, 0.0423801000, 0.0465306000, 0.0581317000, 0.0833450000, 0.1355983000, 0.2922917000", \ - "0.0729770000, 0.0755865000, 0.0829970000, 0.1002705000, 0.1386377000, 0.2133092000, 0.3653646000", \ - "0.1344481000, 0.1377043000, 0.1496298000, 0.1800755000, 0.2370084000, 0.3471598000, 0.5553930000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015437100, 0.0047660700, 0.0147149000, 0.0454309000, 0.1402640000, 0.4330540000"); - values("0.0448253000, 0.0483573000, 0.0592249000, 0.0922946000, 0.1938111000, 0.5068124000, 1.4812471000", \ - "0.0445498000, 0.0481733000, 0.0588824000, 0.0922444000, 0.1941897000, 0.5100114000, 1.4766717000", \ - "0.0438438000, 0.0473525000, 0.0583716000, 0.0920292000, 0.1943211000, 0.5067857000, 1.4758267000", \ - "0.0553540000, 0.0578717000, 0.0658475000, 0.0943102000, 0.1944571000, 0.5080103000, 1.4760185000", \ - "0.0783161000, 0.0823331000, 0.0942990000, 0.1246646000, 0.2040040000, 0.5104560000, 1.4789406000", \ - "0.1164724000, 0.1221573000, 0.1383999000, 0.1796805000, 0.2742779000, 0.5283255000, 1.4761402000", \ - "0.1805894000, 0.1868739000, 0.2114946000, 0.2703431000, 0.4069935000, 0.6812171000, 1.5005294000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2b_1") { - leakage_power () { - value : 0.0015386000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0039870000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0026465000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0005469000; - when : "A&!B_N"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nor2b"; - cell_leakage_power : 0.0021797420; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044630000, 0.0044628000, 0.0044622000, 0.0044611000, 0.0044586000, 0.0044529000, 0.0044396000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004251300, -0.004299700, -0.004411300, -0.004412800, -0.004416300, -0.004424300, -0.004442800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024610000; - } - pin ("B_N") { - capacitance : 0.0014900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084048000, 0.0083113000, 0.0080958000, 0.0081437000, 0.0082541000, 0.0085086000, 0.0090953000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021945000, 0.0021386000, 0.0020097000, 0.0020521000, 0.0021497000, 0.0023748000, 0.0028936000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015460000; - } - pin ("Y") { - direction : "output"; - function : "(!A&B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0019959000, 0.0011170000, -0.000964600, -0.006432700, -0.020072500, -0.052620600, -0.129005000", \ - "0.0019420000, 0.0010652000, -0.001015900, -0.006480800, -0.020112100, -0.052657700, -0.129129300", \ - "0.0019951000, 0.0011313000, -0.000983700, -0.006429700, -0.020051800, -0.052584200, -0.129022700", \ - "0.0017984000, 0.0009013000, -0.001231800, -0.006668500, -0.020270200, -0.052736300, -0.129201300", \ - "0.0015340000, 0.0005998000, -0.001549700, -0.006885200, -0.020452900, -0.052901700, -0.129325000", \ - "0.0020690000, 0.0013346000, -0.001238400, -0.007006800, -0.020474000, -0.052843600, -0.129192800", \ - "0.0024784000, 0.0013661000, -0.001154700, -0.006988800, -0.020591500, -0.053028500, -0.128991900"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0062081000, 0.0073988000, 0.0100980000, 0.0162584000, 0.0303019000, 0.0626561000, 0.1378758000", \ - "0.0061984000, 0.0073811000, 0.0100785000, 0.0161573000, 0.0302827000, 0.0626418000, 0.1386795000", \ - "0.0061770000, 0.0073431000, 0.0100121000, 0.0160940000, 0.0300661000, 0.0623932000, 0.1389808000", \ - "0.0059003000, 0.0069845000, 0.0096216000, 0.0157726000, 0.0298549000, 0.0621252000, 0.1376413000", \ - "0.0057059000, 0.0068304000, 0.0094326000, 0.0153845000, 0.0294059000, 0.0622426000, 0.1382316000", \ - "0.0057366000, 0.0068690000, 0.0094302000, 0.0152896000, 0.0291720000, 0.0616410000, 0.1372246000", \ - "0.0060673000, 0.0071511000, 0.0097353000, 0.0156278000, 0.0294027000, 0.0622476000, 0.1372378000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0043467000, 0.0032616000, 0.0007570000, -0.005155400, -0.019060100, -0.051674600, -0.128102900", \ - "0.0042298000, 0.0031698000, 0.0006738000, -0.005222400, -0.019080500, -0.051711300, -0.128122600", \ - "0.0041597000, 0.0031213000, 0.0006207000, -0.005225500, -0.019070700, -0.051654000, -0.128072100", \ - "0.0040279000, 0.0029579000, 0.0004872000, -0.005365000, -0.019160400, -0.051691600, -0.128092700", \ - "0.0041591000, 0.0030989000, 0.0006581000, -0.005295200, -0.019209700, -0.051750000, -0.128136900", \ - "0.0048380000, 0.0037489000, 0.0009825000, -0.005040200, -0.019010900, -0.051578800, -0.128010300", \ - "0.0065513000, 0.0053689000, 0.0026485000, -0.003573200, -0.017716500, -0.050744800, -0.127681400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0066008000, 0.0077505000, 0.0103407000, 0.0164114000, 0.0301479000, 0.0624061000, 0.1388924000", \ - "0.0064208000, 0.0075552000, 0.0101613000, 0.0161884000, 0.0301438000, 0.0623883000, 0.1378779000", \ - "0.0063009000, 0.0074306000, 0.0100108000, 0.0160060000, 0.0299740000, 0.0623264000, 0.1388762000", \ - "0.0062060000, 0.0073141000, 0.0098810000, 0.0158368000, 0.0297455000, 0.0626333000, 0.1384202000", \ - "0.0061486000, 0.0072566000, 0.0098213000, 0.0157594000, 0.0297279000, 0.0623760000, 0.1382774000", \ - "0.0059390000, 0.0070961000, 0.0098079000, 0.0157696000, 0.0297042000, 0.0622015000, 0.1375294000", \ - "0.0071454000, 0.0081128000, 0.0104537000, 0.0161582000, 0.0299921000, 0.0623358000, 0.1380558000"); - } - } - max_capacitance : 0.0824070000; - max_transition : 1.4969190000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0183489000, 0.0207866000, 0.0262815000, 0.0385245000, 0.0660583000, 0.1295483000, 0.2774052000", \ - "0.0231083000, 0.0255211000, 0.0309801000, 0.0431542000, 0.0707510000, 0.1342357000, 0.2820796000", \ - "0.0331671000, 0.0362230000, 0.0421659000, 0.0543237000, 0.0817818000, 0.1452322000, 0.2932948000", \ - "0.0461717000, 0.0509465000, 0.0604657000, 0.0780251000, 0.1083926000, 0.1717014000, 0.3195342000", \ - "0.0604451000, 0.0671588000, 0.0821356000, 0.1097163000, 0.1567125000, 0.2325757000, 0.3795523000", \ - "0.0680601000, 0.0791785000, 0.1018504000, 0.1447535000, 0.2186241000, 0.3350328000, 0.5197788000", \ - "0.0465838000, 0.0639966000, 0.0993808000, 0.1664107000, 0.2814258000, 0.4674255000, 0.7530149000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0585989000, 0.0678814000, 0.0885699000, 0.1367331000, 0.2464649000, 0.5022917000, 1.1080010000", \ - "0.0634510000, 0.0725376000, 0.0935227000, 0.1412510000, 0.2535409000, 0.5082342000, 1.1080564000", \ - "0.0754452000, 0.0844244000, 0.1052602000, 0.1528361000, 0.2633951000, 0.5203508000, 1.1302007000", \ - "0.1004400000, 0.1100178000, 0.1308328000, 0.1785383000, 0.2889456000, 0.5488303000, 1.1496514000", \ - "0.1424253000, 0.1557518000, 0.1835740000, 0.2374200000, 0.3482676000, 0.6076660000, 1.2075241000", \ - "0.2079334000, 0.2288835000, 0.2704523000, 0.3456357000, 0.4844529000, 0.7447173000, 1.3459400000", \ - "0.3192730000, 0.3507592000, 0.4131745000, 0.5271756000, 0.7205905000, 1.0537584000, 1.6667543000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0134957000, 0.0163520000, 0.0229247000, 0.0380548000, 0.0737932000, 0.1573593000, 0.3520182000", \ - "0.0135807000, 0.0163069000, 0.0226884000, 0.0379357000, 0.0736306000, 0.1572279000, 0.3521806000", \ - "0.0190673000, 0.0212445000, 0.0261168000, 0.0392940000, 0.0735478000, 0.1571358000, 0.3520781000", \ - "0.0311575000, 0.0339252000, 0.0410443000, 0.0529005000, 0.0800221000, 0.1572172000, 0.3524833000", \ - "0.0504336000, 0.0558982000, 0.0669238000, 0.0843911000, 0.1166909000, 0.1772618000, 0.3544365000", \ - "0.0855817000, 0.0940684000, 0.1103094000, 0.1390548000, 0.1865902000, 0.2669858000, 0.4050399000", \ - "0.1489061000, 0.1623999000, 0.1897607000, 0.2345995000, 0.3089887000, 0.4266958000, 0.6085345000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0439501000, 0.0558995000, 0.0836571000, 0.1488991000, 0.2984583000, 0.6524895000, 1.4865060000", \ - "0.0440366000, 0.0559742000, 0.0835085000, 0.1479901000, 0.2999269000, 0.6506792000, 1.4751167000", \ - "0.0442104000, 0.0559832000, 0.0837208000, 0.1479644000, 0.2996045000, 0.6523395000, 1.4889139000", \ - "0.0491786000, 0.0598096000, 0.0853109000, 0.1483279000, 0.2989474000, 0.6557169000, 1.4807034000", \ - "0.0696060000, 0.0806421000, 0.1053322000, 0.1591477000, 0.3010932000, 0.6547448000, 1.4788468000", \ - "0.1129302000, 0.1258505000, 0.1541389000, 0.2119272000, 0.3378151000, 0.6581760000, 1.4835150000", \ - "0.1903240000, 0.2085342000, 0.2462656000, 0.3197626000, 0.4621437000, 0.7558062000, 1.4969191000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0964098000, 0.1010860000, 0.1102523000, 0.1273195000, 0.1600110000, 0.2280251000, 0.3827862000", \ - "0.1012241000, 0.1058767000, 0.1152085000, 0.1322784000, 0.1650034000, 0.2330573000, 0.3878352000", \ - "0.1142060000, 0.1188111000, 0.1279525000, 0.1451122000, 0.1778948000, 0.2459654000, 0.4008484000", \ - "0.1460100000, 0.1506360000, 0.1597965000, 0.1770128000, 0.2097790000, 0.2780579000, 0.4326710000", \ - "0.2146767000, 0.2196822000, 0.2294603000, 0.2469999000, 0.2804278000, 0.3492035000, 0.5036980000", \ - "0.3266986000, 0.3331350000, 0.3453720000, 0.3666815000, 0.4035157000, 0.4744856000, 0.6297366000", \ - "0.5031695000, 0.5116762000, 0.5271391000, 0.5547521000, 0.5997640000, 0.6754318000, 0.8304952000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0739826000, 0.0835647000, 0.1051338000, 0.1539338000, 0.2665917000, 0.5243608000, 1.1219606000", \ - "0.0788807000, 0.0883915000, 0.1099354000, 0.1587790000, 0.2706097000, 0.5276034000, 1.1328408000", \ - "0.0899662000, 0.0993038000, 0.1205752000, 0.1688996000, 0.2799708000, 0.5374332000, 1.1435738000", \ - "0.1110085000, 0.1198304000, 0.1409138000, 0.1895600000, 0.3036836000, 0.5581809000, 1.1587908000", \ - "0.1402031000, 0.1492857000, 0.1701274000, 0.2181786000, 0.3293248000, 0.5890536000, 1.1930470000", \ - "0.1748854000, 0.1844042000, 0.2052351000, 0.2524772000, 0.3625855000, 0.6200887000, 1.2236121000", \ - "0.1987370000, 0.2104141000, 0.2338083000, 0.2808738000, 0.3899273000, 0.6477113000, 1.2476300000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0228015000, 0.0257814000, 0.0330566000, 0.0485313000, 0.0830718000, 0.1671984000, 0.3719465000", \ - "0.0225309000, 0.0257804000, 0.0331338000, 0.0485782000, 0.0834598000, 0.1667683000, 0.3712204000", \ - "0.0225978000, 0.0258449000, 0.0330889000, 0.0485857000, 0.0833986000, 0.1671392000, 0.3725490000", \ - "0.0226441000, 0.0262253000, 0.0330380000, 0.0487171000, 0.0832926000, 0.1672811000, 0.3748068000", \ - "0.0269756000, 0.0299821000, 0.0365149000, 0.0514093000, 0.0847900000, 0.1677483000, 0.3732379000", \ - "0.0384616000, 0.0416982000, 0.0488214000, 0.0624021000, 0.0944999000, 0.1725085000, 0.3726053000", \ - "0.0557503000, 0.0608906000, 0.0693901000, 0.0842106000, 0.1141633000, 0.1857527000, 0.3789422000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0439679000, 0.0559289000, 0.0835110000, 0.1485700000, 0.3012280000, 0.6534101000, 1.4775490000", \ - "0.0439710000, 0.0557057000, 0.0835164000, 0.1481422000, 0.3014541000, 0.6529548000, 1.4901750000", \ - "0.0440178000, 0.0559424000, 0.0836399000, 0.1483531000, 0.2986190000, 0.6515350000, 1.4881395000", \ - "0.0445554000, 0.0562340000, 0.0836712000, 0.1485765000, 0.3010883000, 0.6526127000, 1.4787215000", \ - "0.0463223000, 0.0575298000, 0.0845476000, 0.1484604000, 0.2992479000, 0.6551769000, 1.4857059000", \ - "0.0527390000, 0.0625363000, 0.0872049000, 0.1496528000, 0.3006978000, 0.6504319000, 1.4771152000", \ - "0.0674572000, 0.0768115000, 0.0985232000, 0.1542040000, 0.3015296000, 0.6537398000, 1.4738359000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2b_2") { - leakage_power () { - value : 0.0038944000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0039075000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0045917000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0004672000; - when : "A&!B_N"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__nor2b"; - cell_leakage_power : 0.0032152190; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082382000, 0.0082360000, 0.0082309000, 0.0082275000, 0.0082195000, 0.0082011000, 0.0081586000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007666700, -0.007719800, -0.007842100, -0.007845700, -0.007853900, -0.007873100, -0.007917100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045380000; - } - pin ("B_N") { - capacitance : 0.0014500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0113285000, 0.0112417000, 0.0110417000, 0.0111014000, 0.0112392000, 0.0115568000, 0.0122889000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0036756000, 0.0036283000, 0.0035192000, 0.0035750000, 0.0037036000, 0.0040001000, 0.0046834000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014970000; - } - pin ("Y") { - direction : "output"; - function : "(!A&B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0079985000, 0.0067413000, 0.0035105000, -0.004818600, -0.026161600, -0.081013200, -0.222111600", \ - "0.0076934000, 0.0064538000, 0.0032741000, -0.005016300, -0.026298700, -0.081160800, -0.222173900", \ - "0.0074126000, 0.0061968000, 0.0030406000, -0.005207400, -0.026411200, -0.081198900, -0.222252100", \ - "0.0068614000, 0.0056505000, 0.0025710000, -0.005512100, -0.026628800, -0.081341900, -0.222334600", \ - "0.0071687000, 0.0058998000, 0.0027311000, -0.005388100, -0.026913900, -0.081473900, -0.222399200", \ - "0.0082961000, 0.0070587000, 0.0037754000, -0.004638900, -0.026120400, -0.081463100, -0.222407000", \ - "0.0115054000, 0.0100427000, 0.0065630000, -0.002314800, -0.024369600, -0.080159600, -0.221917600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0125455000, 0.0139188000, 0.0173570000, 0.0258740000, 0.0472657000, 0.1014935000, 0.2410094000", \ - "0.0122328000, 0.0135635000, 0.0169968000, 0.0255700000, 0.0471809000, 0.1014729000, 0.2410170000", \ - "0.0120039000, 0.0133211000, 0.0166682000, 0.0251773000, 0.0466823000, 0.1016083000, 0.2428790000", \ - "0.0118657000, 0.0131603000, 0.0164843000, 0.0249059000, 0.0464883000, 0.1013532000, 0.2406952000", \ - "0.0116983000, 0.0130076000, 0.0163057000, 0.0246352000, 0.0460323000, 0.1006365000, 0.2403281000", \ - "0.0117932000, 0.0130768000, 0.0163116000, 0.0247032000, 0.0460415000, 0.1008541000, 0.2400256000", \ - "0.0128788000, 0.0139963000, 0.0170529000, 0.0250314000, 0.0464631000, 0.1008673000, 0.2415720000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0019774000, 0.0008895000, -0.001835800, -0.008938800, -0.029202800, -0.083576400, -0.224554700", \ - "0.0019624000, 0.0008847000, -0.001777000, -0.008930000, -0.029187300, -0.083564500, -0.224570900", \ - "0.0020111000, 0.0008919000, -0.001767200, -0.008899600, -0.029163700, -0.083538000, -0.224508500", \ - "0.0017734000, 0.0006720000, -0.002021200, -0.009227300, -0.029444500, -0.083781400, -0.224757200", \ - "0.0015652000, 0.0004042000, -0.002363300, -0.009645800, -0.029876600, -0.084131400, -0.224998300", \ - "0.0023957000, 0.0011162000, -0.002091500, -0.010279400, -0.030468900, -0.084525700, -0.225249200", \ - "0.0041358000, 0.0027719000, -9.86000e-05, -0.008704900, -0.030324300, -0.084775000, -0.225317200"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0110047000, 0.0123598000, 0.0158202000, 0.0244993000, 0.0461387000, 0.1015427000, 0.2404454000", \ - "0.0110199000, 0.0123639000, 0.0158282000, 0.0244937000, 0.0461430000, 0.1008110000, 0.2407682000", \ - "0.0110383000, 0.0123733000, 0.0158046000, 0.0244559000, 0.0462560000, 0.1014970000, 0.2406209000", \ - "0.0108948000, 0.0122061000, 0.0155791000, 0.0240453000, 0.0459114000, 0.1005815000, 0.2401687000", \ - "0.0105477000, 0.0118392000, 0.0151950000, 0.0235755000, 0.0452509000, 0.0999360000, 0.2398213000", \ - "0.0108543000, 0.0121172000, 0.0153525000, 0.0235553000, 0.0448561000, 0.0996035000, 0.2393984000", \ - "0.0110891000, 0.0123294000, 0.0155321000, 0.0238938000, 0.0448434000, 0.0999790000, 0.2392051000"); - } - } - max_capacitance : 0.1428320000; - max_transition : 1.4932400000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0159532000, 0.0176173000, 0.0216005000, 0.0309414000, 0.0531194000, 0.1078442000, 0.2462899000", \ - "0.0210041000, 0.0225194000, 0.0263262000, 0.0355495000, 0.0577057000, 0.1124223000, 0.2509850000", \ - "0.0305058000, 0.0325879000, 0.0373189000, 0.0469902000, 0.0686917000, 0.1233813000, 0.2619028000", \ - "0.0425369000, 0.0457016000, 0.0525812000, 0.0675312000, 0.0948940000, 0.1492459000, 0.2875701000", \ - "0.0548513000, 0.0594791000, 0.0700069000, 0.0929645000, 0.1356883000, 0.2081435000, 0.3476981000", \ - "0.0581121000, 0.0655313000, 0.0820781000, 0.1167581000, 0.1838952000, 0.2983156000, 0.4853830000", \ - "0.0276354000, 0.0389158000, 0.0654221000, 0.1208359000, 0.2254197000, 0.4044260000, 0.6965175000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0628951000, 0.0693736000, 0.0853091000, 0.1246943000, 0.2232756000, 0.4745561000, 1.1094881000", \ - "0.0674506000, 0.0739218000, 0.0897503000, 0.1292249000, 0.2286495000, 0.4773693000, 1.1145255000", \ - "0.0799971000, 0.0863048000, 0.1020295000, 0.1409156000, 0.2393778000, 0.4951272000, 1.1348853000", \ - "0.1061764000, 0.1126816000, 0.1285202000, 0.1673335000, 0.2658927000, 0.5164832000, 1.1546877000", \ - "0.1482087000, 0.1573537000, 0.1785602000, 0.2249016000, 0.3247476000, 0.5747048000, 1.2141246000", \ - "0.2147283000, 0.2300877000, 0.2617774000, 0.3272390000, 0.4548365000, 0.7127364000, 1.3518157000", \ - "0.3211828000, 0.3438194000, 0.3946946000, 0.4967464000, 0.6827007000, 1.0133437000, 1.6753906000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0121092000, 0.0140031000, 0.0185590000, 0.0296002000, 0.0572151000, 0.1284871000, 0.3130052000", \ - "0.0125308000, 0.0141061000, 0.0183185000, 0.0293277000, 0.0572436000, 0.1284171000, 0.3119147000", \ - "0.0183850000, 0.0198361000, 0.0229534000, 0.0316193000, 0.0572586000, 0.1283941000, 0.3122562000", \ - "0.0290410000, 0.0312239000, 0.0363334000, 0.0468043000, 0.0664812000, 0.1297147000, 0.3119242000", \ - "0.0478155000, 0.0515389000, 0.0586214000, 0.0749412000, 0.1026737000, 0.1555103000, 0.3153853000", \ - "0.0800461000, 0.0857045000, 0.0979205000, 0.1227889000, 0.1666031000, 0.2408371000, 0.3738677000", \ - "0.1388318000, 0.1477538000, 0.1676557000, 0.2070200000, 0.2755252000, 0.3879010000, 0.5762861000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0375735000, 0.0457924000, 0.0664655000, 0.1192451000, 0.2543901000, 0.5982274000, 1.4768614000", \ - "0.0377760000, 0.0457250000, 0.0663354000, 0.1192723000, 0.2540555000, 0.5960673000, 1.4718242000", \ - "0.0379286000, 0.0458753000, 0.0666592000, 0.1191234000, 0.2533607000, 0.5994678000, 1.4897832000", \ - "0.0412922000, 0.0488462000, 0.0679910000, 0.1196369000, 0.2540298000, 0.5974073000, 1.4804914000", \ - "0.0580544000, 0.0662801000, 0.0864110000, 0.1316856000, 0.2566202000, 0.5976389000, 1.4757714000", \ - "0.0951874000, 0.1050135000, 0.1280845000, 0.1795486000, 0.2949324000, 0.6059835000, 1.4805269000", \ - "0.1737621000, 0.1856034000, 0.2145132000, 0.2789017000, 0.4124240000, 0.6981005000, 1.4932403000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1191507000, 0.1230982000, 0.1316109000, 0.1481851000, 0.1787895000, 0.2404221000, 0.3824831000", \ - "0.1241789000, 0.1280997000, 0.1365535000, 0.1529632000, 0.1837590000, 0.2456539000, 0.3876908000", \ - "0.1366735000, 0.1405968000, 0.1490155000, 0.1654451000, 0.1959146000, 0.2579473000, 0.3997786000", \ - "0.1672347000, 0.1711899000, 0.1796397000, 0.1961668000, 0.2272139000, 0.2889988000, 0.4307835000", \ - "0.2383217000, 0.2422754000, 0.2507481000, 0.2674242000, 0.2986537000, 0.3605578000, 0.5020364000", \ - "0.3603219000, 0.3652304000, 0.3761966000, 0.3962687000, 0.4318967000, 0.4976035000, 0.6402731000", \ - "0.5448403000, 0.5513525000, 0.5652900000, 0.5914524000, 0.6362414000, 0.7113335000, 0.8591082000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0850827000, 0.0915806000, 0.1077065000, 0.1477067000, 0.2471145000, 0.4983962000, 1.1352976000", \ - "0.0900440000, 0.0965464000, 0.1126415000, 0.1525025000, 0.2520509000, 0.5025037000, 1.1440479000", \ - "0.1017131000, 0.1082521000, 0.1241953000, 0.1639636000, 0.2639431000, 0.5156037000, 1.1547951000", \ - "0.1279568000, 0.1342575000, 0.1500619000, 0.1891261000, 0.2889944000, 0.5417804000, 1.1783942000", \ - "0.1717177000, 0.1782563000, 0.1941255000, 0.2332152000, 0.3318474000, 0.5829571000, 1.2209209000", \ - "0.2310062000, 0.2382372000, 0.2549623000, 0.2940025000, 0.3913674000, 0.6406796000, 1.2824904000", \ - "0.2973325000, 0.3069641000, 0.3274714000, 0.3695982000, 0.4649781000, 0.7149331000, 1.3520109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0254083000, 0.0276955000, 0.0333064000, 0.0450796000, 0.0720788000, 0.1388267000, 0.3183009000", \ - "0.0254099000, 0.0280855000, 0.0332918000, 0.0453896000, 0.0723231000, 0.1389905000, 0.3192530000", \ - "0.0256039000, 0.0276651000, 0.0330740000, 0.0456818000, 0.0720882000, 0.1390372000, 0.3184676000", \ - "0.0254888000, 0.0278462000, 0.0333572000, 0.0453043000, 0.0719558000, 0.1390676000, 0.3184578000", \ - "0.0273382000, 0.0294373000, 0.0346769000, 0.0460064000, 0.0730632000, 0.1388552000, 0.3186862000", \ - "0.0394351000, 0.0427221000, 0.0478363000, 0.0592400000, 0.0846910000, 0.1455955000, 0.3208909000", \ - "0.0586966000, 0.0621029000, 0.0694690000, 0.0840776000, 0.1085623000, 0.1665664000, 0.3295225000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0381011000, 0.0460886000, 0.0664559000, 0.1192002000, 0.2536772000, 0.6001803000, 1.4758188000", \ - "0.0380606000, 0.0460790000, 0.0663492000, 0.1190981000, 0.2537064000, 0.5975983000, 1.4793547000", \ - "0.0381432000, 0.0459972000, 0.0665279000, 0.1191819000, 0.2537545000, 0.5994495000, 1.4808624000", \ - "0.0383746000, 0.0464138000, 0.0666500000, 0.1190637000, 0.2545955000, 0.5979719000, 1.4765567000", \ - "0.0414338000, 0.0490315000, 0.0684923000, 0.1197716000, 0.2534887000, 0.5975594000, 1.4768212000", \ - "0.0494856000, 0.0566454000, 0.0740001000, 0.1223709000, 0.2546289000, 0.5966870000, 1.4775206000", \ - "0.0646317000, 0.0718417000, 0.0892738000, 0.1323175000, 0.2569990000, 0.6002753000, 1.4740861000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor2b_4") { - leakage_power () { - value : 0.0128888000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0041047000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0115579000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0004820000; - when : "A&!B_N"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__nor2b"; - cell_leakage_power : 0.0072583460; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163411000, 0.0163396000, 0.0163361000, 0.0163320000, 0.0163224000, 0.0163003000, 0.0162493000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015076600, -0.015208700, -0.015513300, -0.015529200, -0.015565800, -0.015650100, -0.015844500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091070000; - } - pin ("B_N") { - capacitance : 0.0023750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213266000, 0.0211919000, 0.0208815000, 0.0210785000, 0.0215325000, 0.0225791000, 0.0249918000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072082000, 0.0071060000, 0.0068704000, 0.0070089000, 0.0073282000, 0.0080641000, 0.0097604000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("Y") { - direction : "output"; - function : "(!A&B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0156603000, 0.0141994000, 0.0100369000, -0.001723400, -0.034930800, -0.128921500, -0.394981000", \ - "0.0150968000, 0.0136758000, 0.0095519000, -0.002137600, -0.035224200, -0.129173400, -0.395237300", \ - "0.0145217000, 0.0131042000, 0.0091203000, -0.002464400, -0.035416800, -0.129164200, -0.395250200", \ - "0.0136036000, 0.0121971000, 0.0081973000, -0.003204400, -0.035828400, -0.129507500, -0.395382200", \ - "0.0140303000, 0.0125554000, 0.0085893000, -0.002827200, -0.036304200, -0.129805800, -0.395641900", \ - "0.0160356000, 0.0145337000, 0.0106329000, -0.001923400, -0.035522100, -0.129290700, -0.395321400", \ - "0.0218320000, 0.0201055000, 0.0156098000, 0.0031652000, -0.031426600, -0.126857100, -0.394530900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0247326000, 0.0263657000, 0.0308587000, 0.0430420000, 0.0764064000, 0.1701780000, 0.4328061000", \ - "0.0240680000, 0.0256324000, 0.0300775000, 0.0423163000, 0.0759481000, 0.1698034000, 0.4325939000", \ - "0.0235715000, 0.0251267000, 0.0294658000, 0.0415924000, 0.0754972000, 0.1690189000, 0.4325200000", \ - "0.0233170000, 0.0248277000, 0.0290898000, 0.0410541000, 0.0747304000, 0.1683390000, 0.4354687000", \ - "0.0230181000, 0.0245464000, 0.0287608000, 0.0405465000, 0.0738985000, 0.1675412000, 0.4313828000", \ - "0.0231349000, 0.0245862000, 0.0287762000, 0.0406785000, 0.0741701000, 0.1676452000, 0.4306002000", \ - "0.0248234000, 0.0260770000, 0.0299101000, 0.0411294000, 0.0747708000, 0.1686073000, 0.4324480000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0065992000, 0.0053411000, 0.0018174000, -0.008193900, -0.039279600, -0.132432400, -0.398443500", \ - "0.0064991000, 0.0052404000, 0.0018214000, -0.008170000, -0.039457300, -0.132463500, -0.398514500", \ - "0.0066055000, 0.0053591000, 0.0018310000, -0.008153400, -0.039342100, -0.132357200, -0.398414100", \ - "0.0060972000, 0.0048372000, 0.0012090000, -0.008906300, -0.040037200, -0.132942700, -0.398828500", \ - "0.0053456000, 0.0039680000, 0.0002217000, -0.009732400, -0.040815300, -0.133640500, -0.399373500", \ - "0.0065270000, 0.0050584000, 0.0011124000, -0.010326200, -0.042804900, -0.134755100, -0.399956500", \ - "0.0081062000, 0.0064969000, 0.0026281000, -0.009649200, -0.042647600, -0.135711800, -0.400351100"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014128540, 0.0039923110, 0.0112811000, 0.0318770900, 0.0900753300, 0.2545265000"); - values("0.0217529000, 0.0233573000, 0.0276966000, 0.0402582000, 0.0742913000, 0.1683187000, 0.4325166000", \ - "0.0217986000, 0.0232972000, 0.0277789000, 0.0402427000, 0.0742300000, 0.1683183000, 0.4352205000", \ - "0.0217274000, 0.0232999000, 0.0277585000, 0.0401276000, 0.0741001000, 0.1687842000, 0.4329226000", \ - "0.0213503000, 0.0227112000, 0.0270785000, 0.0394302000, 0.0732445000, 0.1674657000, 0.4325612000", \ - "0.0210015000, 0.0225164000, 0.0268145000, 0.0387879000, 0.0724291000, 0.1665589000, 0.4319569000", \ - "0.0212032000, 0.0226972000, 0.0268484000, 0.0383998000, 0.0715490000, 0.1657788000, 0.4296247000", \ - "0.0216327000, 0.0230409000, 0.0273182000, 0.0389346000, 0.0720717000, 0.1661579000, 0.4293406000"); - } - } - max_capacitance : 0.2545270000; - max_transition : 1.4968260000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0160142000, 0.0170734000, 0.0198829000, 0.0271018000, 0.0457914000, 0.0958116000, 0.2345839000", \ - "0.0209866000, 0.0219348000, 0.0245740000, 0.0316841000, 0.0503207000, 0.1003642000, 0.2391566000", \ - "0.0299907000, 0.0313558000, 0.0347635000, 0.0428326000, 0.0612158000, 0.1111690000, 0.2499775000", \ - "0.0412602000, 0.0432970000, 0.0485171000, 0.0606468000, 0.0858001000, 0.1368519000, 0.2754638000", \ - "0.0515882000, 0.0546736000, 0.0622945000, 0.0810431000, 0.1201033000, 0.1925900000, 0.3346948000", \ - "0.0502625000, 0.0544404000, 0.0668979000, 0.0957900000, 0.1570456000, 0.2696325000, 0.4662067000", \ - "0.0087570000, 0.0159149000, 0.0348840000, 0.0803524000, 0.1759627000, 0.3551769000, 0.6623609000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0662234000, 0.0705175000, 0.0824665000, 0.1142435000, 0.2004081000, 0.4451087000, 1.1203524000", \ - "0.0706156000, 0.0749206000, 0.0867009000, 0.1184648000, 0.2053521000, 0.4494732000, 1.1264520000", \ - "0.0832884000, 0.0875117000, 0.0989541000, 0.1304279000, 0.2186052000, 0.4599232000, 1.1387934000", \ - "0.1095305000, 0.1138895000, 0.1255137000, 0.1571903000, 0.2438829000, 0.4859941000, 1.1722423000", \ - "0.1533812000, 0.1594385000, 0.1747372000, 0.2127831000, 0.3023926000, 0.5442859000, 1.2249710000", \ - "0.2256816000, 0.2348750000, 0.2580792000, 0.3130704000, 0.4290217000, 0.6817658000, 1.3626513000", \ - "0.3433906000, 0.3580092000, 0.3950220000, 0.4795077000, 0.6500027000, 0.9837876000, 1.6847267000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0123489000, 0.0135213000, 0.0166915000, 0.0253564000, 0.0486799000, 0.1150753000, 0.3039048000", \ - "0.0127588000, 0.0137470000, 0.0166011000, 0.0249156000, 0.0486199000, 0.1146939000, 0.3035438000", \ - "0.0185441000, 0.0194579000, 0.0220905000, 0.0282152000, 0.0491085000, 0.1147665000, 0.3031523000", \ - "0.0293116000, 0.0307264000, 0.0343030000, 0.0425244000, 0.0607997000, 0.1171382000, 0.3027833000", \ - "0.0474978000, 0.0496781000, 0.0551350000, 0.0682077000, 0.0943894000, 0.1467603000, 0.3071406000", \ - "0.0790182000, 0.0829210000, 0.0916790000, 0.1126393000, 0.1530106000, 0.2291786000, 0.3717098000", \ - "0.1367200000, 0.1423041000, 0.1572647000, 0.1905674000, 0.2545001000, 0.3674498000, 0.5672125000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0398133000, 0.0450908000, 0.0601126000, 0.1017120000, 0.2191019000, 0.5513106000, 1.4809782000", \ - "0.0399206000, 0.0451020000, 0.0601242000, 0.1017813000, 0.2195742000, 0.5508926000, 1.4813188000", \ - "0.0399256000, 0.0453416000, 0.0601783000, 0.1017390000, 0.2198217000, 0.5492316000, 1.4773528000", \ - "0.0431177000, 0.0480061000, 0.0619649000, 0.1022666000, 0.2199265000, 0.5492986000, 1.4906608000", \ - "0.0588889000, 0.0643543000, 0.0789254000, 0.1159390000, 0.2236760000, 0.5507796000, 1.4812067000", \ - "0.0942571000, 0.1003694000, 0.1170020000, 0.1600984000, 0.2638552000, 0.5587937000, 1.4859194000", \ - "0.1712942000, 0.1784486000, 0.1994296000, 0.2516667000, 0.3731673000, 0.6576292000, 1.4968262000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0977795000, 0.1000745000, 0.1057360000, 0.1182200000, 0.1435915000, 0.1995470000, 0.3430505000", \ - "0.1029064000, 0.1051694000, 0.1107779000, 0.1232238000, 0.1487210000, 0.2046316000, 0.3481125000", \ - "0.1157972000, 0.1180654000, 0.1236615000, 0.1362148000, 0.1617443000, 0.2175607000, 0.3609215000", \ - "0.1460184000, 0.1483136000, 0.1539129000, 0.1667514000, 0.1923309000, 0.2483578000, 0.3919397000", \ - "0.2128946000, 0.2153297000, 0.2213365000, 0.2340903000, 0.2603124000, 0.3169101000, 0.4605892000", \ - "0.3175447000, 0.3206632000, 0.3284230000, 0.3448764000, 0.3763039000, 0.4371102000, 0.5801596000", \ - "0.4716567000, 0.4757089000, 0.4859146000, 0.5076093000, 0.5481544000, 0.6193909000, 0.7668251000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0928147000, 0.0971228000, 0.1088444000, 0.1413558000, 0.2293673000, 0.4721448000, 1.1573766000", \ - "0.0976597000, 0.1019375000, 0.1137729000, 0.1461654000, 0.2341311000, 0.4770579000, 1.1617509000", \ - "0.1089983000, 0.1133625000, 0.1252057000, 0.1574394000, 0.2453100000, 0.4886567000, 1.1716412000", \ - "0.1352985000, 0.1391838000, 0.1508148000, 0.1827285000, 0.2705369000, 0.5132372000, 1.2069526000", \ - "0.1804233000, 0.1847746000, 0.1965307000, 0.2280231000, 0.3147629000, 0.5573966000, 1.2497489000", \ - "0.2421779000, 0.2471262000, 0.2597159000, 0.2914139000, 0.3774774000, 0.6194486000, 1.3003699000", \ - "0.3121997000, 0.3183856000, 0.3343887000, 0.3694187000, 0.4550140000, 0.6956424000, 1.3740475000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0217630000, 0.0232819000, 0.0267479000, 0.0357588000, 0.0586312000, 0.1217876000, 0.3098992000", \ - "0.0218615000, 0.0231300000, 0.0268550000, 0.0357496000, 0.0586032000, 0.1214610000, 0.3095133000", \ - "0.0217502000, 0.0230926000, 0.0266367000, 0.0357710000, 0.0585876000, 0.1217580000, 0.3098468000", \ - "0.0217920000, 0.0231543000, 0.0266908000, 0.0357824000, 0.0586753000, 0.1217619000, 0.3100117000", \ - "0.0258091000, 0.0271669000, 0.0306292000, 0.0389277000, 0.0607739000, 0.1225645000, 0.3092109000", \ - "0.0382268000, 0.0398160000, 0.0441935000, 0.0530597000, 0.0735146000, 0.1310640000, 0.3120447000", \ - "0.0578787000, 0.0600356000, 0.0652876000, 0.0763967000, 0.0978210000, 0.1513619000, 0.3204470000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014128500, 0.0039923100, 0.0112811000, 0.0318771000, 0.0900753000, 0.2545270000"); - values("0.0402938000, 0.0455372000, 0.0601489000, 0.1019518000, 0.2194860000, 0.5491805000, 1.4829701000", \ - "0.0404023000, 0.0455187000, 0.0603164000, 0.1019973000, 0.2189524000, 0.5492034000, 1.4915129000", \ - "0.0404294000, 0.0454191000, 0.0600965000, 0.1019582000, 0.2189981000, 0.5497766000, 1.4835964000", \ - "0.0405595000, 0.0457808000, 0.0604103000, 0.1019422000, 0.2195089000, 0.5481779000, 1.4865011000", \ - "0.0436174000, 0.0485572000, 0.0624350000, 0.1026194000, 0.2193180000, 0.5492477000, 1.4870921000", \ - "0.0517941000, 0.0564574000, 0.0690430000, 0.1063531000, 0.2205822000, 0.5498084000, 1.4836515000", \ - "0.0678176000, 0.0723064000, 0.0851565000, 0.1187569000, 0.2242531000, 0.5530017000, 1.4771380000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3_1") { - leakage_power () { - value : 0.0029956000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0010077000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0001104000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0009729000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0002132000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0018331000; - when : "A&!B&!C"; - } - leakage_power () { - value : 7.6149604e-05; - when : "A&B&C"; - } - leakage_power () { - value : 0.0001922000; - when : "A&B&!C"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__nor3"; - cell_leakage_power : 0.0009251654; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040753000, 0.0040736000, 0.0040699000, 0.0040711000, 0.0040740000, 0.0040806000, 0.0040959000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003501000, -0.003540400, -0.003631100, -0.003645400, -0.003678500, -0.003754500, -0.003929900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025510000; - } - pin ("B") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038040000, 0.0038034000, 0.0038021000, 0.0038012000, 0.0037991000, 0.0037943000, 0.0037831000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003295200, -0.003393500, -0.003620000, -0.003625200, -0.003637000, -0.003664400, -0.003727500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025300000; - } - pin ("C") { - capacitance : 0.0023250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025804000, 0.0025747000, 0.0025616000, 0.0025690000, 0.0025862000, 0.0026256000, 0.0027166000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001713400, -0.001713400, -0.001713300, -0.001713600, -0.001714300, -0.001715800, -0.001719200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024950000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0049567000, 0.0040170000, 0.0019687000, -0.002453500, -0.012030800, -0.032914900, -0.078364300", \ - "0.0048605000, 0.0039236000, 0.0018714000, -0.002547000, -0.012114200, -0.032979200, -0.078440400", \ - "0.0047772000, 0.0038370000, 0.0018077000, -0.002595700, -0.012161400, -0.033020500, -0.078467000", \ - "0.0045857000, 0.0036690000, 0.0016656000, -0.002734800, -0.012238300, -0.033096600, -0.078515400", \ - "0.0047352000, 0.0037963000, 0.0017431000, -0.002767600, -0.012305200, -0.033109300, -0.078579600", \ - "0.0052369000, 0.0042912000, 0.0022071000, -0.002273400, -0.011980300, -0.032859700, -0.078359300", \ - "0.0069291000, 0.0059805000, 0.0037494000, -0.000861500, -0.010561100, -0.031910600, -0.077880000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0115260000, 0.0125078000, 0.0146466000, 0.0190944000, 0.0287251000, 0.0494983000, 0.0947177000", \ - "0.0113135000, 0.0123277000, 0.0144086000, 0.0189265000, 0.0286103000, 0.0495400000, 0.0944870000", \ - "0.0111185000, 0.0121072000, 0.0141913000, 0.0187202000, 0.0284260000, 0.0494620000, 0.0945068000", \ - "0.0110106000, 0.0119801000, 0.0140427000, 0.0185547000, 0.0282142000, 0.0490890000, 0.0942705000", \ - "0.0109338000, 0.0118665000, 0.0139346000, 0.0183966000, 0.0280662000, 0.0491679000, 0.0942862000", \ - "0.0108809000, 0.0118390000, 0.0139334000, 0.0183734000, 0.0279332000, 0.0488871000, 0.0941751000", \ - "0.0108732000, 0.0117901000, 0.0137952000, 0.0183728000, 0.0281909000, 0.0488549000, 0.0939727000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0037824000, 0.0028465000, 0.0008207000, -0.003590100, -0.013233800, -0.034176400, -0.079729600", \ - "0.0038012000, 0.0028783000, 0.0008706000, -0.003528100, -0.013144100, -0.034103900, -0.079639000", \ - "0.0038626000, 0.0029542000, 0.0009643000, -0.003408800, -0.012970000, -0.033894700, -0.079411200", \ - "0.0036411000, 0.0027332000, 0.0007624000, -0.003551800, -0.013092800, -0.033964000, -0.079426200", \ - "0.0036610000, 0.0027452000, 0.0007697000, -0.003602500, -0.013236000, -0.034054200, -0.079485900", \ - "0.0040697000, 0.0031109000, 0.0010829000, -0.003518100, -0.013121200, -0.034107200, -0.079513500", \ - "0.0053354000, 0.0043308000, 0.0021701000, -0.002488400, -0.012340000, -0.033465400, -0.079217900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0093849000, 0.0103807000, 0.0124896000, 0.0169441000, 0.0265758000, 0.0473420000, 0.0924071000", \ - "0.0091423000, 0.0101584000, 0.0122532000, 0.0167799000, 0.0264494000, 0.0473524000, 0.0924395000", \ - "0.0089777000, 0.0099347000, 0.0120588000, 0.0165485000, 0.0262675000, 0.0471823000, 0.0926326000", \ - "0.0088491000, 0.0098228000, 0.0119100000, 0.0163591000, 0.0260528000, 0.0473180000, 0.0920529000", \ - "0.0087747000, 0.0097380000, 0.0117876000, 0.0162533000, 0.0259508000, 0.0470182000, 0.0921995000", \ - "0.0087400000, 0.0096930000, 0.0117804000, 0.0161939000, 0.0258984000, 0.0468316000, 0.0920098000", \ - "0.0091348000, 0.0099876000, 0.0120261000, 0.0165743000, 0.0261305000, 0.0466752000, 0.0921999000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0005491000, -0.000366900, -0.002364000, -0.006767700, -0.016402700, -0.037397000, -0.082953900", \ - "0.0004233000, -0.000469400, -0.002426300, -0.006778900, -0.016360600, -0.037296000, -0.082850500", \ - "0.0002389000, -0.000637700, -0.002570500, -0.006854800, -0.016384800, -0.037267400, -0.082788300", \ - "-2.25000e-05, -0.000868900, -0.002785100, -0.007026900, -0.016504200, -0.037314500, -0.082794200", \ - "-3.50000e-06, -0.000905800, -0.002870300, -0.007161800, -0.016712000, -0.037464600, -0.082861200", \ - "0.0005263000, -0.000451500, -0.002505700, -0.007117900, -0.016711000, -0.037587700, -0.082840000", \ - "0.0021888000, 0.0011038000, -0.001174000, -0.005933500, -0.015888000, -0.036839900, -0.082637700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010849590, 0.0023542710, 0.0051085730, 0.0110851800, 0.0240539300, 0.0521950400"); - values("0.0083143000, 0.0093049000, 0.0114222000, 0.0159171000, 0.0255639000, 0.0463590000, 0.0913444000", \ - "0.0080377000, 0.0090128000, 0.0112009000, 0.0157282000, 0.0254451000, 0.0462978000, 0.0913635000", \ - "0.0078781000, 0.0088649000, 0.0109446000, 0.0155191000, 0.0253028000, 0.0463134000, 0.0916228000", \ - "0.0078639000, 0.0088126000, 0.0108694000, 0.0153055000, 0.0249743000, 0.0459102000, 0.0911193000", \ - "0.0078763000, 0.0089062000, 0.0109171000, 0.0154184000, 0.0248993000, 0.0459814000, 0.0909286000", \ - "0.0087964000, 0.0097255000, 0.0117056000, 0.0156374000, 0.0250920000, 0.0458588000, 0.0907415000", \ - "0.0101611000, 0.0110137000, 0.0129941000, 0.0174953000, 0.0263271000, 0.0466554000, 0.0913534000"); - } - } - max_capacitance : 0.0521950000; - max_transition : 1.4885470000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0223779000, 0.0248573000, 0.0299914000, 0.0404833000, 0.0618348000, 0.1060171000, 0.1994343000", \ - "0.0274590000, 0.0298325000, 0.0348444000, 0.0451921000, 0.0664637000, 0.1106190000, 0.2041279000", \ - "0.0393958000, 0.0419140000, 0.0467351000, 0.0566220000, 0.0775815000, 0.1216309000, 0.2150073000", \ - "0.0578836000, 0.0616330000, 0.0686824000, 0.0819609000, 0.1046338000, 0.1480674000, 0.2404814000", \ - "0.0807421000, 0.0862941000, 0.0971576000, 0.1174887000, 0.1522369000, 0.2081267000, 0.3020888000", \ - "0.1029177000, 0.1112546000, 0.1281341000, 0.1584279000, 0.2131086000, 0.2987582000, 0.4327963000", \ - "0.1038004000, 0.1170745000, 0.1429224000, 0.1914963000, 0.2750107000, 0.4123095000, 0.6225844000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.1166974000, 0.1286098000, 0.1548863000, 0.2095078000, 0.3276015000, 0.5829396000, 1.1402208000", \ - "0.1200316000, 0.1324596000, 0.1582201000, 0.2142080000, 0.3347363000, 0.5908646000, 1.1397037000", \ - "0.1312744000, 0.1431035000, 0.1689481000, 0.2244508000, 0.3437401000, 0.6014493000, 1.1522986000", \ - "0.1559344000, 0.1677316000, 0.1934151000, 0.2491660000, 0.3671410000, 0.6235835000, 1.1767773000", \ - "0.2036687000, 0.2168362000, 0.2441977000, 0.2993804000, 0.4190064000, 0.6778352000, 1.2316493000", \ - "0.2797045000, 0.2964545000, 0.3304351000, 0.3978348000, 0.5276790000, 0.7844748000, 1.3429498000", \ - "0.3957481000, 0.4212154000, 0.4713954000, 0.5626083000, 0.7292523000, 1.0275748000, 1.5922126000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0198579000, 0.0227868000, 0.0289072000, 0.0416703000, 0.0682569000, 0.1254282000, 0.2478291000", \ - "0.0193091000, 0.0221149000, 0.0283740000, 0.0413227000, 0.0679454000, 0.1253828000, 0.2481216000", \ - "0.0233866000, 0.0254727000, 0.0303755000, 0.0417022000, 0.0677279000, 0.1249419000, 0.2477779000", \ - "0.0364752000, 0.0400397000, 0.0454260000, 0.0539389000, 0.0744490000, 0.1261939000, 0.2484911000", \ - "0.0594451000, 0.0633881000, 0.0711475000, 0.0858454000, 0.1092237000, 0.1503268000, 0.2555879000", \ - "0.0996707000, 0.1059827000, 0.1172480000, 0.1389884000, 0.1756151000, 0.2363399000, 0.3265884000", \ - "0.1715744000, 0.1814325000, 0.2024426000, 0.2353033000, 0.2907062000, 0.3776335000, 0.5141596000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0881264000, 0.1032275000, 0.1375830000, 0.2107693000, 0.3691070000, 0.7120426000, 1.4597853000", \ - "0.0880203000, 0.1036530000, 0.1370808000, 0.2106304000, 0.3696751000, 0.7145087000, 1.4586999000", \ - "0.0881068000, 0.1036259000, 0.1371008000, 0.2106986000, 0.3684462000, 0.7133800000, 1.4556183000", \ - "0.0880133000, 0.1039069000, 0.1372563000, 0.2110711000, 0.3693518000, 0.7118288000, 1.4571735000", \ - "0.1006545000, 0.1143089000, 0.1451950000, 0.2145348000, 0.3693177000, 0.7177247000, 1.4578582000", \ - "0.1339562000, 0.1491921000, 0.1816144000, 0.2498142000, 0.3902446000, 0.7183638000, 1.4637038000", \ - "0.2121132000, 0.2290739000, 0.2635516000, 0.3358471000, 0.4858989000, 0.7895865000, 1.4803729000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0222037000, 0.0243573000, 0.0287961000, 0.0381772000, 0.0578872000, 0.0998164000, 0.1902821000", \ - "0.0269927000, 0.0291385000, 0.0335863000, 0.0428861000, 0.0626090000, 0.1045893000, 0.1951109000", \ - "0.0377824000, 0.0401766000, 0.0449506000, 0.0540224000, 0.0736993000, 0.1156839000, 0.2060217000", \ - "0.0525181000, 0.0563875000, 0.0637277000, 0.0771295000, 0.0993809000, 0.1413379000, 0.2316343000", \ - "0.0683222000, 0.0742064000, 0.0857931000, 0.1068450000, 0.1426342000, 0.1992556000, 0.2924334000", \ - "0.0770364000, 0.0861866000, 0.1036352000, 0.1376908000, 0.1935789000, 0.2831463000, 0.4189156000", \ - "0.0533973000, 0.0678730000, 0.0965666000, 0.1487775000, 0.2380128000, 0.3793064000, 0.5924434000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.1036205000, 0.1158502000, 0.1419130000, 0.1964600000, 0.3145612000, 0.5698142000, 1.1221449000", \ - "0.1064722000, 0.1185495000, 0.1443432000, 0.1999376000, 0.3187571000, 0.5781570000, 1.1260682000", \ - "0.1168151000, 0.1289084000, 0.1550693000, 0.2104873000, 0.3314946000, 0.5853068000, 1.1396241000", \ - "0.1428397000, 0.1544910000, 0.1802332000, 0.2352870000, 0.3539675000, 0.6138920000, 1.1725276000", \ - "0.1956481000, 0.2103857000, 0.2388781000, 0.2945761000, 0.4136486000, 0.6725693000, 1.2244086000", \ - "0.2830730000, 0.3034621000, 0.3438562000, 0.4171101000, 0.5514313000, 0.8085256000, 1.3632125000", \ - "0.4270884000, 0.4579581000, 0.5177886000, 0.6261613000, 0.8094654000, 1.1184271000, 1.6856744000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0165060000, 0.0190662000, 0.0245338000, 0.0363127000, 0.0619617000, 0.1174168000, 0.2386035000", \ - "0.0162023000, 0.0187501000, 0.0243415000, 0.0362204000, 0.0619240000, 0.1176792000, 0.2379625000", \ - "0.0203982000, 0.0222675000, 0.0267745000, 0.0373686000, 0.0618601000, 0.1171162000, 0.2371792000", \ - "0.0325467000, 0.0353194000, 0.0408662000, 0.0508973000, 0.0702751000, 0.1193677000, 0.2384764000", \ - "0.0545386000, 0.0585787000, 0.0678998000, 0.0817801000, 0.1060637000, 0.1465084000, 0.2466019000", \ - "0.0934596000, 0.1005363000, 0.1132776000, 0.1350039000, 0.1729007000, 0.2306009000, 0.3214849000", \ - "0.1637797000, 0.1747560000, 0.1951613000, 0.2304731000, 0.2862526000, 0.3755009000, 0.5084855000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0881116000, 0.1038072000, 0.1375114000, 0.2108149000, 0.3694675000, 0.7117603000, 1.4561437000", \ - "0.0880579000, 0.1036672000, 0.1370318000, 0.2104735000, 0.3684923000, 0.7144547000, 1.4585432000", \ - "0.0880083000, 0.1037146000, 0.1373921000, 0.2106245000, 0.3697528000, 0.7118736000, 1.4612811000", \ - "0.0893007000, 0.1040989000, 0.1376467000, 0.2105051000, 0.3692673000, 0.7168882000, 1.4604788000", \ - "0.1083803000, 0.1210635000, 0.1503650000, 0.2160926000, 0.3697309000, 0.7172291000, 1.4596752000", \ - "0.1557234000, 0.1710602000, 0.2017641000, 0.2647474000, 0.3974377000, 0.7185642000, 1.4627409000", \ - "0.2492607000, 0.2664994000, 0.3052597000, 0.3815225000, 0.5218503000, 0.7969438000, 1.4762105000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0183757000, 0.0204267000, 0.0248041000, 0.0341129000, 0.0540484000, 0.0967946000, 0.1898217000", \ - "0.0231186000, 0.0252282000, 0.0295758000, 0.0389844000, 0.0589146000, 0.1019543000, 0.1949964000", \ - "0.0321185000, 0.0350785000, 0.0406026000, 0.0503947000, 0.0703835000, 0.1132756000, 0.2062601000", \ - "0.0430320000, 0.0476979000, 0.0564396000, 0.0717774000, 0.0965654000, 0.1397285000, 0.2329502000", \ - "0.0530495000, 0.0604321000, 0.0743021000, 0.0985037000, 0.1377451000, 0.1981696000, 0.2937999000", \ - "0.0532513000, 0.0649054000, 0.0867136000, 0.1252709000, 0.1873312000, 0.2822663000, 0.4211877000", \ - "0.0193679000, 0.0376434000, 0.0727450000, 0.1330798000, 0.2312389000, 0.3814362000, 0.6029462000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0706407000, 0.0829719000, 0.1088799000, 0.1642288000, 0.2824118000, 0.5375335000, 1.0904911000", \ - "0.0720551000, 0.0843427000, 0.1114113000, 0.1666759000, 0.2855345000, 0.5411118000, 1.0939745000", \ - "0.0813392000, 0.0933133000, 0.1187876000, 0.1752096000, 0.2944012000, 0.5510316000, 1.1041823000", \ - "0.1078150000, 0.1188825000, 0.1439304000, 0.1983063000, 0.3165614000, 0.5731693000, 1.1268316000", \ - "0.1602081000, 0.1753421000, 0.2048158000, 0.2592737000, 0.3756721000, 0.6330114000, 1.1880874000", \ - "0.2419052000, 0.2640507000, 0.3071615000, 0.3855792000, 0.5212678000, 0.7727854000, 1.3231904000", \ - "0.3766652000, 0.4082859000, 0.4708227000, 0.5844570000, 0.7794746000, 1.1008784000, 1.6488680000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0122766000, 0.0149800000, 0.0206814000, 0.0328027000, 0.0595685000, 0.1175230000, 0.2424265000", \ - "0.0126863000, 0.0150781000, 0.0206744000, 0.0326668000, 0.0596368000, 0.1175904000, 0.2416489000", \ - "0.0183933000, 0.0203751000, 0.0244191000, 0.0345951000, 0.0599336000, 0.1177284000, 0.2415494000", \ - "0.0305955000, 0.0332681000, 0.0390209000, 0.0493668000, 0.0687000000, 0.1197948000, 0.2417397000", \ - "0.0526681000, 0.0562287000, 0.0648682000, 0.0806100000, 0.1050496000, 0.1469168000, 0.2509004000", \ - "0.0912088000, 0.0987438000, 0.1109737000, 0.1336316000, 0.1710175000, 0.2298633000, 0.3258146000", \ - "0.1646047000, 0.1747045000, 0.1953845000, 0.2311229000, 0.2872640000, 0.3768373000, 0.5127607000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010849600, 0.0023542700, 0.0051085700, 0.0110852000, 0.0240539000, 0.0521950000"); - values("0.0871604000, 0.1028754000, 0.1369202000, 0.2105918000, 0.3693316000, 0.7114782000, 1.4569882000", \ - "0.0867689000, 0.1024512000, 0.1370282000, 0.2103691000, 0.3691589000, 0.7117442000, 1.4568372000", \ - "0.0853038000, 0.1016379000, 0.1365589000, 0.2109107000, 0.3696691000, 0.7139908000, 1.4607628000", \ - "0.0891034000, 0.1033504000, 0.1356894000, 0.2096808000, 0.3691653000, 0.7123674000, 1.4586465000", \ - "0.1177742000, 0.1316064000, 0.1581999000, 0.2191809000, 0.3688420000, 0.7165707000, 1.4586491000", \ - "0.1640260000, 0.1822141000, 0.2184952000, 0.2873332000, 0.4113341000, 0.7193959000, 1.4573195000", \ - "0.2448390000, 0.2715110000, 0.3197312000, 0.4106201000, 0.5665758000, 0.8402844000, 1.4885466000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3_2") { - leakage_power () { - value : 0.0079423000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0020798000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0002563000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0022883000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0002589000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0021588000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0001310000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0002484000; - when : "A&B&!C"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__nor3"; - cell_leakage_power : 0.0019204830; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076233000, 0.0076199000, 0.0076121000, 0.0076081000, 0.0075988000, 0.0075775000, 0.0075282000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006782900, -0.006856700, -0.007026700, -0.007054100, -0.007117200, -0.007262600, -0.007597900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046010000; - } - pin ("B") { - capacitance : 0.0043790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083130000, 0.0083128000, 0.0083122000, 0.0083120000, 0.0083116000, 0.0083107000, 0.0083086000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007173500, -0.007298000, -0.007585000, -0.007597200, -0.007625400, -0.007690300, -0.007839900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046750000; - } - pin ("C") { - capacitance : 0.0043460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043182000, 0.0043109000, 0.0042942000, 0.0043144000, 0.0043609000, 0.0044683000, 0.0047158000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003498600, -0.003499900, -0.003503100, -0.003501800, -0.003498700, -0.003491700, -0.003475600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046900000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("0.0106688000, 0.0095273000, 0.0068632000, 0.0005111000, -0.014657600, -0.050738800, -0.137351000", \ - "0.0104799000, 0.0093597000, 0.0066955000, 0.0003271000, -0.014811100, -0.050876500, -0.137515500", \ - "0.0103154000, 0.0092127000, 0.0065453000, 0.0002241000, -0.014944900, -0.050997500, -0.137615000", \ - "0.0099610000, 0.0088683000, 0.0061823000, -9.83000e-05, -0.015146700, -0.051210800, -0.137798900", \ - "0.0101146000, 0.0089805000, 0.0062708000, -0.000122300, -0.015216800, -0.051224600, -0.137930100", \ - "0.0114859000, 0.0103664000, 0.0076071000, 0.0011966000, -0.014185600, -0.050896200, -0.137563700", \ - "0.0143078000, 0.0131627000, 0.0103313000, 0.0036246000, -0.011876900, -0.048846500, -0.136537800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("0.0215073000, 0.0226951000, 0.0254730000, 0.0320173000, 0.0471108000, 0.0834076000, 0.1690139000", \ - "0.0211745000, 0.0223188000, 0.0251103000, 0.0316979000, 0.0470893000, 0.0834720000, 0.1691784000", \ - "0.0209143000, 0.0220779000, 0.0247942000, 0.0313495000, 0.0466681000, 0.0829366000, 0.1688959000", \ - "0.0207303000, 0.0218373000, 0.0245715000, 0.0309781000, 0.0462775000, 0.0826002000, 0.1688579000", \ - "0.0205403000, 0.0216643000, 0.0243344000, 0.0307348000, 0.0460814000, 0.0821601000, 0.1683314000", \ - "0.0205354000, 0.0217303000, 0.0244301000, 0.0308109000, 0.0458751000, 0.0821075000, 0.1688380000", \ - "0.0203514000, 0.0213801000, 0.0240413000, 0.0306535000, 0.0462390000, 0.0821522000, 0.1682115000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("0.0075075000, 0.0063962000, 0.0037418000, -0.002557300, -0.017689900, -0.053936100, -0.140878400", \ - "0.0075224000, 0.0064195000, 0.0037903000, -0.002495700, -0.017594300, -0.053839500, -0.140726600", \ - "0.0075341000, 0.0064552000, 0.0038706000, -0.002370200, -0.017386200, -0.053599500, -0.140456000", \ - "0.0071591000, 0.0060651000, 0.0034939000, -0.002640000, -0.017573800, -0.053756600, -0.140528500", \ - "0.0073042000, 0.0062084000, 0.0035538000, -0.002644500, -0.017911400, -0.053876200, -0.140591000", \ - "0.0080502000, 0.0070128000, 0.0042220000, -0.002084200, -0.017226600, -0.053708900, -0.140563100", \ - "0.0108419000, 0.0096171000, 0.0075609000, 3.300000e-05, -0.015713400, -0.052457700, -0.139784600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("0.0162315000, 0.0174025000, 0.0202206000, 0.0266846000, 0.0419560000, 0.0780828000, 0.1640609000", \ - "0.0158405000, 0.0169965000, 0.0198283000, 0.0264305000, 0.0418735000, 0.0781526000, 0.1643689000", \ - "0.0155444000, 0.0166997000, 0.0194662000, 0.0259669000, 0.0413343000, 0.0776388000, 0.1636447000", \ - "0.0153687000, 0.0165128000, 0.0192278000, 0.0256227000, 0.0409102000, 0.0775249000, 0.1636469000", \ - "0.0151264000, 0.0162847000, 0.0189579000, 0.0253797000, 0.0406601000, 0.0768339000, 0.1630344000", \ - "0.0151603000, 0.0162725000, 0.0189663000, 0.0253969000, 0.0406468000, 0.0768506000, 0.1633577000", \ - "0.0158262000, 0.0168831000, 0.0196415000, 0.0260324000, 0.0410306000, 0.0768941000, 0.1635405000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("6.600000e-05, -0.001018300, -0.003647600, -0.009982200, -0.025169800, -0.061565300, -0.148583700", \ - "-0.000274000, -0.001305200, -0.003852100, -0.010033700, -0.025107900, -0.061397300, -0.148364000", \ - "-0.000702100, -0.001725700, -0.004185800, -0.010259500, -0.025148300, -0.061305300, -0.148202200", \ - "-0.001137400, -0.002151400, -0.004504500, -0.010690200, -0.025378600, -0.061394900, -0.148163300", \ - "-0.001034600, -0.002133600, -0.004683200, -0.010720400, -0.025749100, -0.061660400, -0.148271800", \ - "1.310000e-05, -0.001143600, -0.003846800, -0.010221100, -0.025465700, -0.061567600, -0.148386700", \ - "0.0035963000, 0.0023047000, -0.000650000, -0.007696300, -0.023788700, -0.060602800, -0.147801900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011934790, 0.0028487860, 0.0067999350, 0.0162311600, 0.0387431200, 0.0924782300"); - values("0.0153646000, 0.0165746000, 0.0194064000, 0.0260877000, 0.0413307000, 0.0776651000, 0.1639553000", \ - "0.0148434000, 0.0160269000, 0.0189673000, 0.0255642000, 0.0410453000, 0.0773291000, 0.1632525000", \ - "0.0146049000, 0.0157495000, 0.0185388000, 0.0250320000, 0.0406465000, 0.0772111000, 0.1632344000", \ - "0.0144237000, 0.0155293000, 0.0182248000, 0.0247624000, 0.0401209000, 0.0769387000, 0.1629746000", \ - "0.0147220000, 0.0158232000, 0.0184241000, 0.0247479000, 0.0399357000, 0.0763057000, 0.1625118000", \ - "0.0162958000, 0.0173854000, 0.0199805000, 0.0262514000, 0.0410162000, 0.0762962000, 0.1621742000", \ - "0.0193720000, 0.0203672000, 0.0227595000, 0.0289704000, 0.0436227000, 0.0782466000, 0.1625150000"); - } - } - max_capacitance : 0.0924780000; - max_transition : 1.4918710000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0180192000, 0.0195338000, 0.0230281000, 0.0309241000, 0.0483616000, 0.0870205000, 0.1750691000", \ - "0.0234068000, 0.0248133000, 0.0281364000, 0.0357885000, 0.0530349000, 0.0915985000, 0.1796590000", \ - "0.0349668000, 0.0366474000, 0.0403144000, 0.0478425000, 0.0644515000, 0.1024366000, 0.1903702000", \ - "0.0513954000, 0.0538681000, 0.0593954000, 0.0703487000, 0.0907384000, 0.1288562000, 0.2161445000", \ - "0.0713610000, 0.0749838000, 0.0829686000, 0.0995072000, 0.1307642000, 0.1847252000, 0.2765064000", \ - "0.0872436000, 0.0926790000, 0.1049424000, 0.1289908000, 0.1780098000, 0.2620352000, 0.3995271000", \ - "0.0770244000, 0.0855287000, 0.1044339000, 0.1430147000, 0.2177024000, 0.3490510000, 0.5634211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.1192571000, 0.1272480000, 0.1466794000, 0.1915880000, 0.2961619000, 0.5442469000, 1.1335854000", \ - "0.1229934000, 0.1313087000, 0.1504393000, 0.1957595000, 0.3014201000, 0.5551559000, 1.1430371000", \ - "0.1351002000, 0.1431834000, 0.1619349000, 0.2073084000, 0.3123998000, 0.5607695000, 1.1519985000", \ - "0.1622162000, 0.1702912000, 0.1892310000, 0.2331391000, 0.3380395000, 0.5870323000, 1.1782173000", \ - "0.2136839000, 0.2227770000, 0.2427168000, 0.2878574000, 0.3925044000, 0.6408644000, 1.2318684000", \ - "0.2971453000, 0.3089482000, 0.3341699000, 0.3889666000, 0.5061874000, 0.7568577000, 1.3509794000", \ - "0.4248159000, 0.4419626000, 0.4795074000, 0.5571802000, 0.7085982000, 1.0039702000, 1.6080015000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0163760000, 0.0183232000, 0.0226945000, 0.0325105000, 0.0542124000, 0.1032848000, 0.2189168000", \ - "0.0166067000, 0.0182126000, 0.0221812000, 0.0318461000, 0.0537251000, 0.1032591000, 0.2193072000", \ - "0.0222770000, 0.0234979000, 0.0261960000, 0.0338651000, 0.0535508000, 0.1026708000, 0.2194888000", \ - "0.0348866000, 0.0366657000, 0.0402123000, 0.0487104000, 0.0633621000, 0.1055577000, 0.2193219000", \ - "0.0567760000, 0.0594052000, 0.0649372000, 0.0763893000, 0.0984294000, 0.1359585000, 0.2305395000", \ - "0.0947525000, 0.0990936000, 0.1081722000, 0.1261121000, 0.1583965000, 0.2132191000, 0.3083944000", \ - "0.1626390000, 0.1694147000, 0.1840777000, 0.2123723000, 0.2642556000, 0.3469187000, 0.4854929000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0808628000, 0.0911982000, 0.1163235000, 0.1760010000, 0.3172489000, 0.6560630000, 1.4569698000", \ - "0.0808818000, 0.0916592000, 0.1164129000, 0.1761280000, 0.3182998000, 0.6602326000, 1.4614724000", \ - "0.0809526000, 0.0913853000, 0.1163159000, 0.1761192000, 0.3174864000, 0.6532811000, 1.4576663000", \ - "0.0811579000, 0.0918420000, 0.1170058000, 0.1752404000, 0.3172034000, 0.6534515000, 1.4571113000", \ - "0.0910396000, 0.1003787000, 0.1231012000, 0.1802778000, 0.3186054000, 0.6552806000, 1.4589951000", \ - "0.1205687000, 0.1309373000, 0.1554205000, 0.2114025000, 0.3384175000, 0.6606767000, 1.4658142000", \ - "0.1943985000, 0.2056952000, 0.2316013000, 0.2911888000, 0.4279911000, 0.7268851000, 1.4782252000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0198151000, 0.0212261000, 0.0244935000, 0.0317904000, 0.0482294000, 0.0860520000, 0.1749170000", \ - "0.0247875000, 0.0261705000, 0.0293654000, 0.0366452000, 0.0528972000, 0.0907138000, 0.1795660000", \ - "0.0354105000, 0.0370800000, 0.0406849000, 0.0480194000, 0.0641751000, 0.1017904000, 0.1906813000", \ - "0.0494997000, 0.0518379000, 0.0575107000, 0.0687060000, 0.0895665000, 0.1275448000, 0.2162426000", \ - "0.0638559000, 0.0678133000, 0.0764543000, 0.0940316000, 0.1266664000, 0.1829667000, 0.2771487000", \ - "0.0703330000, 0.0755142000, 0.0901389000, 0.1172032000, 0.1686594000, 0.2572352000, 0.3986421000", \ - "0.0439507000, 0.0534383000, 0.0747050000, 0.1175037000, 0.1990237000, 0.3388039000, 0.5615635000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.1012423000, 0.1096086000, 0.1290649000, 0.1738078000, 0.2783084000, 0.5259239000, 1.1153276000", \ - "0.1039090000, 0.1123512000, 0.1315497000, 0.1771361000, 0.2831775000, 0.5307318000, 1.1321487000", \ - "0.1143604000, 0.1226106000, 0.1415945000, 0.1868766000, 0.2920779000, 0.5412688000, 1.1320497000", \ - "0.1405215000, 0.1486174000, 0.1676892000, 0.2115472000, 0.3178989000, 0.5663139000, 1.1571590000", \ - "0.1901418000, 0.1999731000, 0.2216716000, 0.2687543000, 0.3742652000, 0.6225143000, 1.2142110000", \ - "0.2718747000, 0.2848611000, 0.3155482000, 0.3786029000, 0.5045304000, 0.7569499000, 1.3527888000", \ - "0.3981871000, 0.4197158000, 0.4672402000, 0.5626876000, 0.7361053000, 1.0519007000, 1.6609263000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0151347000, 0.0167081000, 0.0204223000, 0.0291919000, 0.0498491000, 0.0997281000, 0.2183485000", \ - "0.0148251000, 0.0163595000, 0.0200060000, 0.0289229000, 0.0498103000, 0.0996122000, 0.2181476000", \ - "0.0194746000, 0.0207652000, 0.0234023000, 0.0307002000, 0.0499539000, 0.0994422000, 0.2181565000", \ - "0.0305350000, 0.0324912000, 0.0366260000, 0.0444761000, 0.0603594000, 0.1028326000, 0.2191174000", \ - "0.0517070000, 0.0536054000, 0.0594791000, 0.0724514000, 0.0943070000, 0.1344293000, 0.2294022000", \ - "0.0868273000, 0.0919970000, 0.1021012000, 0.1204622000, 0.1554876000, 0.2131731000, 0.3082992000", \ - "0.1540477000, 0.1611533000, 0.1756686000, 0.2069314000, 0.2595353000, 0.3468892000, 0.4865705000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0809650000, 0.0911240000, 0.1157996000, 0.1755128000, 0.3170816000, 0.6533102000, 1.4555621000", \ - "0.0807924000, 0.0916262000, 0.1161253000, 0.1760597000, 0.3182103000, 0.6560292000, 1.4669059000", \ - "0.0810379000, 0.0912713000, 0.1161852000, 0.1759218000, 0.3171315000, 0.6555727000, 1.4579670000", \ - "0.0817986000, 0.0919843000, 0.1172938000, 0.1753804000, 0.3175639000, 0.6558323000, 1.4550605000", \ - "0.1002017000, 0.1091660000, 0.1301696000, 0.1840914000, 0.3184149000, 0.6541153000, 1.4603386000", \ - "0.1431423000, 0.1533258000, 0.1773887000, 0.2316761000, 0.3514919000, 0.6621160000, 1.4638540000", \ - "0.2328844000, 0.2455174000, 0.2746600000, 0.3402824000, 0.4699021000, 0.7531019000, 1.4786899000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0161211000, 0.0174194000, 0.0204020000, 0.0272388000, 0.0431558000, 0.0806425000, 0.1699278000", \ - "0.0208723000, 0.0221912000, 0.0252123000, 0.0320494000, 0.0481183000, 0.0856841000, 0.1750862000", \ - "0.0287282000, 0.0307799000, 0.0351099000, 0.0434321000, 0.0596523000, 0.0971493000, 0.1866508000", \ - "0.0376929000, 0.0409557000, 0.0476166000, 0.0611653000, 0.0845026000, 0.1238829000, 0.2131900000", \ - "0.0447543000, 0.0499651000, 0.0610246000, 0.0819721000, 0.1187796000, 0.1783979000, 0.2747998000", \ - "0.0405076000, 0.0483211000, 0.0663567000, 0.1000032000, 0.1575507000, 0.2520605000, 0.3989261000", \ - "-0.000384900, 0.0129002000, 0.0405654000, 0.0936333000, 0.1867645000, 0.3363437000, 0.5672157000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0585200000, 0.0669250000, 0.0865564000, 0.1321268000, 0.2380119000, 0.4859397000, 1.0782684000", \ - "0.0598769000, 0.0679902000, 0.0879869000, 0.1333030000, 0.2396777000, 0.4885050000, 1.0790221000", \ - "0.0697737000, 0.0773960000, 0.0962618000, 0.1409856000, 0.2492429000, 0.4975050000, 1.0885192000", \ - "0.0976371000, 0.1045972000, 0.1210865000, 0.1647992000, 0.2694617000, 0.5218974000, 1.1182378000", \ - "0.1443771000, 0.1556504000, 0.1792153000, 0.2272388000, 0.3286384000, 0.5789452000, 1.1678267000", \ - "0.2173730000, 0.2334118000, 0.2683050000, 0.3394845000, 0.4710013000, 0.7143550000, 1.3043402000", \ - "0.3404023000, 0.3623796000, 0.4110018000, 0.5112239000, 0.7004188000, 1.0347295000, 1.6241501000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0093026000, 0.0108646000, 0.0145066000, 0.0233681000, 0.0445808000, 0.0945522000, 0.2144443000", \ - "0.0099994000, 0.0113351000, 0.0146784000, 0.0234219000, 0.0442455000, 0.0949233000, 0.2158235000", \ - "0.0156944000, 0.0171827000, 0.0200155000, 0.0264418000, 0.0453795000, 0.0942715000, 0.2140308000", \ - "0.0262844000, 0.0283598000, 0.0328030000, 0.0410608000, 0.0572251000, 0.0983651000, 0.2146495000", \ - "0.0455990000, 0.0487671000, 0.0551348000, 0.0684368000, 0.0908972000, 0.1305008000, 0.2254242000", \ - "0.0810313000, 0.0859251000, 0.0973571000, 0.1163791000, 0.1514452000, 0.2091552000, 0.3043911000", \ - "0.1486753000, 0.1565375000, 0.1764466000, 0.2055809000, 0.2580053000, 0.3462731000, 0.4843387000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011934800, 0.0028487900, 0.0067999300, 0.0162312000, 0.0387431000, 0.0924782000"); - values("0.0775928000, 0.0889734000, 0.1146629000, 0.1756337000, 0.3172677000, 0.6556532000, 1.4628008000", \ - "0.0765637000, 0.0875773000, 0.1142167000, 0.1745212000, 0.3176377000, 0.6550397000, 1.4579350000", \ - "0.0740722000, 0.0855381000, 0.1125233000, 0.1740847000, 0.3182877000, 0.6553801000, 1.4592141000", \ - "0.0808659000, 0.0903725000, 0.1132441000, 0.1723522000, 0.3174746000, 0.6582961000, 1.4617477000", \ - "0.1063631000, 0.1180089000, 0.1410405000, 0.1892946000, 0.3187434000, 0.6568711000, 1.4580702000", \ - "0.1472233000, 0.1607485000, 0.1902894000, 0.2550368000, 0.3724421000, 0.6653958000, 1.4571947000", \ - "0.2190149000, 0.2376913000, 0.2766278000, 0.3636842000, 0.5158967000, 0.8065590000, 1.4918707000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3_4") { - leakage_power () { - value : 0.0022547000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0063490000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0002338000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0021546000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0002616000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0022324000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0168094000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0040347000; - when : "A&B&!C"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__nor3"; - cell_leakage_power : 0.0042912730; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0142969000, 0.0143097000, 0.0143392000, 0.0143519000, 0.0143812000, 0.0144486000, 0.0146039000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013326700, -0.013483800, -0.013845900, -0.013901100, -0.014028400, -0.014321800, -0.014998200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091280000; - } - pin ("B") { - capacitance : 0.0090040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0163574000, 0.0163542000, 0.0163467000, 0.0163500000, 0.0163575000, 0.0163747000, 0.0164143000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013661800, -0.013966800, -0.014670000, -0.014698300, -0.014763700, -0.014914300, -0.015261500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0096290000; - } - pin ("C") { - capacitance : 0.0083840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075804000, 0.0075711000, 0.0075497000, 0.0075769000, 0.0076396000, 0.0077840000, 0.0081169000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006788000, -0.006791100, -0.006798300, -0.006793500, -0.006782500, -0.006757000, -0.006698300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090080000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0199379000, 0.0186626000, 0.0153205000, 0.0065976000, -0.015967400, -0.074374600, -0.226809300", \ - "0.0196014000, 0.0183152000, 0.0149740000, 0.0062845000, -0.016262000, -0.074648500, -0.227148300", \ - "0.0193230000, 0.0180300000, 0.0146901000, 0.0061114000, -0.016482700, -0.074859800, -0.227308100", \ - "0.0184938000, 0.0172186000, 0.0139127000, 0.0055356000, -0.017009400, -0.075289800, -0.227694300", \ - "0.0183470000, 0.0171017000, 0.0137670000, 0.0052763000, -0.017156400, -0.075386800, -0.227853100", \ - "0.0208707000, 0.0195771000, 0.0156983000, 0.0069001000, -0.015753500, -0.074644600, -0.227468100", \ - "0.0258766000, 0.0245120000, 0.0210551000, 0.0119967000, -0.011104100, -0.071097600, -0.225411300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0419332000, 0.0433019000, 0.0467233000, 0.0557576000, 0.0782246000, 0.1365093000, 0.2880104000", \ - "0.0411786000, 0.0425389000, 0.0459865000, 0.0549509000, 0.0778164000, 0.1364060000, 0.2879243000", \ - "0.0405733000, 0.0418956000, 0.0453065000, 0.0543634000, 0.0773700000, 0.1361863000, 0.2874550000", \ - "0.0401619000, 0.0414900000, 0.0448884000, 0.0536514000, 0.0767059000, 0.1356105000, 0.2870848000", \ - "0.0398210000, 0.0410637000, 0.0444403000, 0.0532134000, 0.0759599000, 0.1347622000, 0.2882585000", \ - "0.0397544000, 0.0410743000, 0.0444992000, 0.0532753000, 0.0755772000, 0.1343866000, 0.2858779000", \ - "0.0388516000, 0.0401609000, 0.0434223000, 0.0526392000, 0.0760440000, 0.1345737000, 0.2859439000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0142556000, 0.0129849000, 0.0096522000, 0.0010167000, -0.021434700, -0.080125200, -0.233151200", \ - "0.0143063000, 0.0130362000, 0.0097349000, 0.0011696000, -0.021232500, -0.079899600, -0.232886800", \ - "0.0145259000, 0.0131917000, 0.0099707000, 0.0015336000, -0.020778700, -0.079330800, -0.232229900", \ - "0.0135534000, 0.0123194000, 0.0091125000, 0.0007452000, -0.021302600, -0.079635200, -0.232389100", \ - "0.0135697000, 0.0123205000, 0.0091050000, 0.0006158000, -0.021710700, -0.080089300, -0.232568100", \ - "0.0147046000, 0.0134104000, 0.0101398000, 0.0014837000, -0.021296100, -0.079635500, -0.232641900", \ - "0.0194847000, 0.0180977000, 0.0145660000, 0.0053740000, -0.017976400, -0.077378900, -0.231021600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0314095000, 0.0328272000, 0.0364328000, 0.0455414000, 0.0682135000, 0.1269929000, 0.2780706000", \ - "0.0304710000, 0.0319002000, 0.0354974000, 0.0445383000, 0.0676230000, 0.1264213000, 0.2779885000", \ - "0.0297923000, 0.0311795000, 0.0346926000, 0.0436078000, 0.0669969000, 0.1260448000, 0.2775422000", \ - "0.0294258000, 0.0307273000, 0.0341787000, 0.0430974000, 0.0658411000, 0.1248810000, 0.2771386000", \ - "0.0289657000, 0.0302752000, 0.0336642000, 0.0424145000, 0.0652545000, 0.1239028000, 0.2761691000", \ - "0.0289157000, 0.0302567000, 0.0336725000, 0.0424800000, 0.0650870000, 0.1239872000, 0.2751327000", \ - "0.0306071000, 0.0318181000, 0.0350267000, 0.0434365000, 0.0657157000, 0.1235841000, 0.2764350000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0014765000, 0.0002150000, -0.003129700, -0.011829600, -0.034445400, -0.093324700, -0.246539700", \ - "0.0009819000, -0.000250400, -0.003471400, -0.011956900, -0.034359900, -0.093065100, -0.246197300", \ - "0.0001864000, -0.001003200, -0.004127800, -0.012373200, -0.034429500, -0.092879200, -0.245878400", \ - "-0.000619800, -0.001741000, -0.004796000, -0.012946800, -0.034882500, -0.092997000, -0.245715400", \ - "-0.000643700, -0.001880200, -0.005061700, -0.013256300, -0.035327200, -0.093434500, -0.245911400", \ - "0.0006571000, -0.000665300, -0.004055000, -0.012693300, -0.034746500, -0.092958100, -0.245984400", \ - "0.0058112000, 0.0043291000, 0.0005567000, -0.008775600, -0.032707200, -0.092377500, -0.245518400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0300088000, 0.0314758000, 0.0351346000, 0.0443569000, 0.0673434000, 0.1257530000, 0.2773657000", \ - "0.0288508000, 0.0303594000, 0.0340765000, 0.0431939000, 0.0664739000, 0.1260338000, 0.2782887000", \ - "0.0282233000, 0.0295622000, 0.0330668000, 0.0420783000, 0.0655194000, 0.1246652000, 0.2767622000", \ - "0.0281496000, 0.0294557000, 0.0328368000, 0.0416365000, 0.0644769000, 0.1237586000, 0.2761190000", \ - "0.0281677000, 0.0294708000, 0.0327529000, 0.0414062000, 0.0639806000, 0.1226242000, 0.2748800000", \ - "0.0298666000, 0.0311652000, 0.0344254000, 0.0428357000, 0.0649640000, 0.1228135000, 0.2754221000", \ - "0.0349379000, 0.0357968000, 0.0388321000, 0.0469724000, 0.0683805000, 0.1253775000, 0.2758469000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.4951450000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0174855000, 0.0184340000, 0.0208644000, 0.0268790000, 0.0413733000, 0.0759522000, 0.1607760000", \ - "0.0228412000, 0.0237286000, 0.0260120000, 0.0317810000, 0.0460489000, 0.0804793000, 0.1652044000", \ - "0.0338757000, 0.0350339000, 0.0376741000, 0.0436949000, 0.0572489000, 0.0912593000, 0.1757439000", \ - "0.0488273000, 0.0504366000, 0.0543635000, 0.0634235000, 0.0817694000, 0.1171124000, 0.2004549000", \ - "0.0659919000, 0.0682947000, 0.0740620000, 0.0873439000, 0.1152536000, 0.1675864000, 0.2599356000", \ - "0.0757500000, 0.0792676000, 0.0881226000, 0.1083624000, 0.1509201000, 0.2309555000, 0.3720089000", \ - "0.0510694000, 0.0561829000, 0.0692785000, 0.1004629000, 0.1667459000, 0.2929524000, 0.5115211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1298159000, 0.1355968000, 0.1501819000, 0.1872919000, 0.2819722000, 0.5220789000, 1.1467399000", \ - "0.1331755000, 0.1390662000, 0.1533607000, 0.1906723000, 0.2849966000, 0.5268181000, 1.1521017000", \ - "0.1451605000, 0.1509002000, 0.1650792000, 0.2025948000, 0.2982548000, 0.5447562000, 1.1666669000", \ - "0.1723862000, 0.1781808000, 0.1921589000, 0.2289811000, 0.3240281000, 0.5672227000, 1.1943477000", \ - "0.2262289000, 0.2321218000, 0.2472209000, 0.2847693000, 0.3784654000, 0.6209191000, 1.2532270000", \ - "0.3142628000, 0.3215296000, 0.3400843000, 0.3849722000, 0.4910379000, 0.7364828000, 1.3637210000", \ - "0.4568851000, 0.4693879000, 0.4948969000, 0.5562682000, 0.6914393000, 0.9795311000, 1.6215130000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0177636000, 0.0189838000, 0.0221398000, 0.0299893000, 0.0488784000, 0.0953409000, 0.2141622000", \ - "0.0180974000, 0.0191670000, 0.0219415000, 0.0292275000, 0.0484198000, 0.0951764000, 0.2139516000", \ - "0.0239326000, 0.0246984000, 0.0268349000, 0.0325979000, 0.0489265000, 0.0946129000, 0.2138524000", \ - "0.0362100000, 0.0373315000, 0.0400577000, 0.0468523000, 0.0611602000, 0.0993074000, 0.2135024000", \ - "0.0582597000, 0.0599486000, 0.0640821000, 0.0726279000, 0.0931257000, 0.1320733000, 0.2281107000", \ - "0.0947308000, 0.0974467000, 0.1044113000, 0.1177873000, 0.1462023000, 0.2026841000, 0.3063559000", \ - "0.1616153000, 0.1667246000, 0.1790753000, 0.2018979000, 0.2457702000, 0.3244041000, 0.4720148000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0878985000, 0.0951547000, 0.1140563000, 0.1634166000, 0.2900222000, 0.6166931000, 1.4705920000", \ - "0.0880411000, 0.0952453000, 0.1141172000, 0.1626418000, 0.2898620000, 0.6180101000, 1.4702175000", \ - "0.0881856000, 0.0953229000, 0.1141622000, 0.1634007000, 0.2904801000, 0.6214129000, 1.4663758000", \ - "0.0883323000, 0.0955404000, 0.1143988000, 0.1625666000, 0.2906717000, 0.6193145000, 1.4676541000", \ - "0.0965134000, 0.1029909000, 0.1205704000, 0.1668808000, 0.2902321000, 0.6186347000, 1.4799252000", \ - "0.1236126000, 0.1308136000, 0.1490097000, 0.1964444000, 0.3118961000, 0.6253068000, 1.4698887000", \ - "0.1882582000, 0.1963475000, 0.2163412000, 0.2653510000, 0.3898074000, 0.6904268000, 1.4880702000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0195721000, 0.0204865000, 0.0227717000, 0.0283697000, 0.0417606000, 0.0746293000, 0.1578625000", \ - "0.0244824000, 0.0253698000, 0.0275988000, 0.0330007000, 0.0463590000, 0.0791664000, 0.1624030000", \ - "0.0347018000, 0.0357575000, 0.0383862000, 0.0443344000, 0.0574041000, 0.0901648000, 0.1733458000", \ - "0.0475746000, 0.0491778000, 0.0531290000, 0.0620804000, 0.0805916000, 0.1153359000, 0.1984920000", \ - "0.0591916000, 0.0617303000, 0.0675750000, 0.0816729000, 0.1100720000, 0.1639329000, 0.2577930000", \ - "0.0582438000, 0.0621531000, 0.0715283000, 0.0939686000, 0.1395103000, 0.2241317000, 0.3678348000", \ - "0.0146769000, 0.0208107000, 0.0358447000, 0.0701333000, 0.1420067000, 0.2768593000, 0.5038059000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1142725000, 0.1202723000, 0.1354291000, 0.1730752000, 0.2683934000, 0.5105107000, 1.1349477000", \ - "0.1157988000, 0.1218348000, 0.1367999000, 0.1742820000, 0.2696984000, 0.5125184000, 1.1383716000", \ - "0.1262602000, 0.1317984000, 0.1466168000, 0.1841995000, 0.2801167000, 0.5246776000, 1.1507342000", \ - "0.1525392000, 0.1581648000, 0.1727031000, 0.2095677000, 0.3040389000, 0.5477452000, 1.1756628000", \ - "0.2048156000, 0.2116040000, 0.2281908000, 0.2672846000, 0.3620047000, 0.6047445000, 1.2323484000", \ - "0.2927722000, 0.3019903000, 0.3251388000, 0.3769600000, 0.4912363000, 0.7390542000, 1.3666539000", \ - "0.4408492000, 0.4550161000, 0.4885838000, 0.5659982000, 0.7243198000, 1.0342206000, 1.6829288000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0156992000, 0.0166459000, 0.0190882000, 0.0255265000, 0.0419842000, 0.0853736000, 0.1989443000", \ - "0.0153676000, 0.0162562000, 0.0186041000, 0.0250300000, 0.0418266000, 0.0853272000, 0.1993425000", \ - "0.0204189000, 0.0209392000, 0.0227567000, 0.0276932000, 0.0425135000, 0.0850439000, 0.1990770000", \ - "0.0309497000, 0.0320449000, 0.0349263000, 0.0414388000, 0.0549837000, 0.0903609000, 0.1990117000", \ - "0.0509184000, 0.0526848000, 0.0567675000, 0.0660789000, 0.0865589000, 0.1247088000, 0.2135362000", \ - "0.0861778000, 0.0890312000, 0.0961018000, 0.1110217000, 0.1413703000, 0.1965280000, 0.2977827000", \ - "0.1523646000, 0.1570169000, 0.1680824000, 0.1918130000, 0.2389067000, 0.3234140000, 0.4659654000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0878828000, 0.0950797000, 0.1141156000, 0.1633197000, 0.2900672000, 0.6191880000, 1.4675007000", \ - "0.0879162000, 0.0951389000, 0.1142852000, 0.1628861000, 0.2897843000, 0.6175445000, 1.4675549000", \ - "0.0883621000, 0.0953542000, 0.1143070000, 0.1628883000, 0.2906612000, 0.6192415000, 1.4668564000", \ - "0.0886925000, 0.0958294000, 0.1141918000, 0.1634327000, 0.2896006000, 0.6173739000, 1.4705618000", \ - "0.1058244000, 0.1120284000, 0.1275556000, 0.1718821000, 0.2914304000, 0.6183120000, 1.4674681000", \ - "0.1457064000, 0.1530166000, 0.1717830000, 0.2175987000, 0.3257934000, 0.6258756000, 1.4674465000", \ - "0.2336381000, 0.2417454000, 0.2635151000, 0.3158614000, 0.4377489000, 0.7156046000, 1.4900667000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0166630000, 0.0175123000, 0.0196659000, 0.0248849000, 0.0380139000, 0.0714376000, 0.1578602000", \ - "0.0211700000, 0.0220372000, 0.0242017000, 0.0295231000, 0.0427048000, 0.0761763000, 0.1626047000", \ - "0.0284252000, 0.0297743000, 0.0329602000, 0.0398711000, 0.0536753000, 0.0872085000, 0.1739171000", \ - "0.0355065000, 0.0376028000, 0.0425859000, 0.0536003000, 0.0749217000, 0.1126652000, 0.1985515000", \ - "0.0375934000, 0.0409943000, 0.0490976000, 0.0665096000, 0.1003095000, 0.1588000000, 0.2579170000", \ - "0.0209890000, 0.0264177000, 0.0390681000, 0.0667888000, 0.1202230000, 0.2140151000, 0.3645091000", \ - "-0.050968400, -0.042378700, -0.021936900, 0.0225795000, 0.1080176000, 0.2571367000, 0.4986430000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0693758000, 0.0754909000, 0.0905052000, 0.1288806000, 0.2237668000, 0.4655428000, 1.0908835000", \ - "0.0700857000, 0.0760378000, 0.0912834000, 0.1296351000, 0.2253014000, 0.4738527000, 1.0958655000", \ - "0.0792077000, 0.0847351000, 0.0989169000, 0.1367923000, 0.2336180000, 0.4771583000, 1.1044766000", \ - "0.1084151000, 0.1132198000, 0.1264000000, 0.1620965000, 0.2567785000, 0.5011897000, 1.1289453000", \ - "0.1650485000, 0.1721184000, 0.1895115000, 0.2288432000, 0.3199367000, 0.5620018000, 1.1960951000", \ - "0.2580751000, 0.2690016000, 0.2942368000, 0.3524377000, 0.4726861000, 0.7108291000, 1.3397407000", \ - "0.4224762000, 0.4373680000, 0.4731002000, 0.5571136000, 0.7286381000, 1.0571489000, 1.6824081000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0099043000, 0.0108621000, 0.0134194000, 0.0202097000, 0.0377014000, 0.0834049000, 0.2023953000", \ - "0.0106335000, 0.0114928000, 0.0137850000, 0.0202230000, 0.0377256000, 0.0835781000, 0.2020942000", \ - "0.0163442000, 0.0172148000, 0.0194349000, 0.0245176000, 0.0392715000, 0.0833790000, 0.2019923000", \ - "0.0267918000, 0.0281645000, 0.0313672000, 0.0387342000, 0.0532375000, 0.0892817000, 0.2029456000", \ - "0.0465941000, 0.0486352000, 0.0537363000, 0.0636149000, 0.0848939000, 0.1263257000, 0.2165589000", \ - "0.0830219000, 0.0853947000, 0.0931576000, 0.1097660000, 0.1420419000, 0.2004886000, 0.3014893000", \ - "0.1508091000, 0.1559392000, 0.1679303000, 0.1970926000, 0.2415479000, 0.3278302000, 0.4744952000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0856598000, 0.0931410000, 0.1128413000, 0.1627234000, 0.2900939000, 0.6192534000, 1.4673779000", \ - "0.0849465000, 0.0924107000, 0.1121060000, 0.1620091000, 0.2896744000, 0.6224912000, 1.4742988000", \ - "0.0826841000, 0.0905084000, 0.1107553000, 0.1614921000, 0.2899253000, 0.6175083000, 1.4683749000", \ - "0.0861134000, 0.0929247000, 0.1106008000, 0.1594168000, 0.2897711000, 0.6186904000, 1.4664878000", \ - "0.1132848000, 0.1212698000, 0.1357074000, 0.1750334000, 0.2905699000, 0.6179647000, 1.4708655000", \ - "0.1542560000, 0.1646399000, 0.1855475000, 0.2364153000, 0.3448199000, 0.6276140000, 1.4774657000", \ - "0.2299706000, 0.2397104000, 0.2713543000, 0.3402219000, 0.4781893000, 0.7599425000, 1.4951451000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3b_1") { - leakage_power () { - value : 0.0019918000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0025105000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0015972000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0004610000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0019535000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0005050000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0009283000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0004280000; - when : "A&B&!C_N"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__nor3b"; - cell_leakage_power : 0.0012968970; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040064000, 0.0040014000, 0.0039901000, 0.0039880000, 0.0039832000, 0.0039720000, 0.0039464000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003455800, -0.003495300, -0.003586300, -0.003599600, -0.003630100, -0.003700500, -0.003862800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024980000; - } - pin ("B") { - capacitance : 0.0023770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043529000, 0.0043522000, 0.0043507000, 0.0043515000, 0.0043535000, 0.0043581000, 0.0043686000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004067000, -0.004132000, -0.004281800, -0.004281900, -0.004282300, -0.004283000, -0.004284600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025160000; - } - pin ("C_N") { - capacitance : 0.0014530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085264000, 0.0084351000, 0.0082245000, 0.0082693000, 0.0083726000, 0.0086106000, 0.0091594000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025261000, 0.0024736000, 0.0023524000, 0.0023929000, 0.0024863000, 0.0027014000, 0.0031972000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015120000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0051551000, 0.0042163000, 0.0022277000, -0.002038500, -0.011220300, -0.031006300, -0.073732900", \ - "0.0050675000, 0.0041361000, 0.0021387000, -0.002128900, -0.011297400, -0.031094000, -0.073821000", \ - "0.0050047000, 0.0040848000, 0.0021279000, -0.002161800, -0.011332400, -0.031113900, -0.073836800", \ - "0.0048625000, 0.0039666000, 0.0019968000, -0.002277200, -0.011410400, -0.031205500, -0.073901500", \ - "0.0050165000, 0.0040902000, 0.0020796000, -0.002189700, -0.011431500, -0.031180300, -0.073931600", \ - "0.0056626000, 0.0047445000, 0.0027832000, -0.001775300, -0.011040400, -0.031107900, -0.073753900", \ - "0.0071398000, 0.0061578000, 0.0040358000, -0.000400000, -0.009738000, -0.030041700, -0.073146800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0111228000, 0.0120673000, 0.0141242000, 0.0184213000, 0.0276189000, 0.0473065000, 0.0896469000", \ - "0.0109420000, 0.0119231000, 0.0139360000, 0.0182876000, 0.0275941000, 0.0473096000, 0.0897103000", \ - "0.0108095000, 0.0117433000, 0.0138197000, 0.0181218000, 0.0273885000, 0.0471994000, 0.0895460000", \ - "0.0107201000, 0.0116551000, 0.0136616000, 0.0179686000, 0.0273355000, 0.0471389000, 0.0894502000", \ - "0.0106468000, 0.0115697000, 0.0135845000, 0.0178778000, 0.0270828000, 0.0468691000, 0.0893652000", \ - "0.0106316000, 0.0115595000, 0.0136101000, 0.0178505000, 0.0270056000, 0.0467903000, 0.0891365000", \ - "0.0105966000, 0.0115195000, 0.0134753000, 0.0179764000, 0.0273447000, 0.0468863000, 0.0893223000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0045602000, 0.0036397000, 0.0016574000, -0.002609700, -0.011844200, -0.031731700, -0.074524300", \ - "0.0045728000, 0.0036574000, 0.0016712000, -0.002578300, -0.011777200, -0.031644600, -0.074460100", \ - "0.0045915000, 0.0036860000, 0.0017377000, -0.002503800, -0.011668400, -0.031500400, -0.074278000", \ - "0.0043773000, 0.0034939000, 0.0015515000, -0.002636400, -0.011756200, -0.031562300, -0.074330300", \ - "0.0044287000, 0.0035280000, 0.0016000000, -0.002657500, -0.011924900, -0.031652400, -0.074375900", \ - "0.0047527000, 0.0038422000, 0.0019007000, -0.002620500, -0.011624500, -0.031572600, -0.074374000", \ - "0.0059307000, 0.0049453000, 0.0028266000, -0.001652600, -0.011109700, -0.031157700, -0.074120400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0086274000, 0.0095777000, 0.0116731000, 0.0159577000, 0.0251504000, 0.0448529000, 0.0872731000", \ - "0.0084101000, 0.0094129000, 0.0114365000, 0.0158016000, 0.0250601000, 0.0448136000, 0.0874795000", \ - "0.0082754000, 0.0092428000, 0.0112590000, 0.0155984000, 0.0249615000, 0.0447399000, 0.0871714000", \ - "0.0081626000, 0.0091139000, 0.0111600000, 0.0154298000, 0.0247328000, 0.0446247000, 0.0871579000", \ - "0.0080997000, 0.0090253000, 0.0110315000, 0.0153365000, 0.0246498000, 0.0445782000, 0.0871003000", \ - "0.0080656000, 0.0090009000, 0.0110100000, 0.0152878000, 0.0245466000, 0.0442907000, 0.0870540000", \ - "0.0083487000, 0.0092239000, 0.0113082000, 0.0155865000, 0.0247596000, 0.0445737000, 0.0870062000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0023112000, 0.0015468000, -0.000121900, -0.004023400, -0.012943500, -0.032691500, -0.075440200", \ - "0.0022559000, 0.0015015000, -0.000178900, -0.004048200, -0.012969800, -0.032721500, -0.075486600", \ - "0.0022969000, 0.0015457000, -0.000130700, -0.004029900, -0.012926100, -0.032669100, -0.075426400", \ - "0.0021105000, 0.0013459000, -0.000340100, -0.004220000, -0.013133200, -0.032831600, -0.075572900", \ - "0.0019704000, 0.0011989000, -0.000512100, -0.004410800, -0.013335800, -0.032997300, -0.075707600", \ - "0.0022760000, 0.0013661000, -0.000557000, -0.004743800, -0.013318200, -0.033171500, -0.075842600", \ - "0.0027418000, 0.0018376000, -0.000134000, -0.004138800, -0.013528600, -0.033199400, -0.075857700"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010752280, 0.0023122290, 0.0049723460, 0.0106928100, 0.0229944100, 0.0494484600"); - values("0.0081902000, 0.0091722000, 0.0112973000, 0.0157014000, 0.0250116000, 0.0451254000, 0.0874120000", \ - "0.0081649000, 0.0091736000, 0.0112523000, 0.0157155000, 0.0251144000, 0.0448015000, 0.0872022000", \ - "0.0081284000, 0.0091034000, 0.0111897000, 0.0156535000, 0.0249473000, 0.0450832000, 0.0871680000", \ - "0.0078582000, 0.0088236000, 0.0108574000, 0.0152872000, 0.0246033000, 0.0445321000, 0.0868931000", \ - "0.0075674000, 0.0085247000, 0.0105533000, 0.0149201000, 0.0242808000, 0.0441455000, 0.0866008000", \ - "0.0076000000, 0.0085043000, 0.0105222000, 0.0148102000, 0.0240940000, 0.0440052000, 0.0867608000", \ - "0.0079152000, 0.0088510000, 0.0108457000, 0.0150594000, 0.0240871000, 0.0439972000, 0.0865431000"); - } - } - max_capacitance : 0.0494480000; - max_transition : 1.4967630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0201224000, 0.0224065000, 0.0271684000, 0.0367779000, 0.0562002000, 0.0959399000, 0.1792086000", \ - "0.0252664000, 0.0274617000, 0.0320533000, 0.0415243000, 0.0608177000, 0.1004980000, 0.1836982000", \ - "0.0370479000, 0.0394366000, 0.0441150000, 0.0529515000, 0.0718907000, 0.1114449000, 0.1946323000", \ - "0.0537997000, 0.0574923000, 0.0644031000, 0.0770733000, 0.0985570000, 0.1369546000, 0.2199583000", \ - "0.0746953000, 0.0800968000, 0.0906210000, 0.1094863000, 0.1425028000, 0.1954487000, 0.2808705000", \ - "0.0910400000, 0.0991189000, 0.1145727000, 0.1449082000, 0.1968068000, 0.2792613000, 0.4035087000", \ - "0.0819214000, 0.0945774000, 0.1195526000, 0.1656209000, 0.2452482000, 0.3754730000, 0.5735640000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.1233536000, 0.1359640000, 0.1630733000, 0.2191053000, 0.3395996000, 0.5972500000, 1.1507771000", \ - "0.1271663000, 0.1400526000, 0.1666012000, 0.2236379000, 0.3454917000, 0.6085397000, 1.1565883000", \ - "0.1390288000, 0.1514666000, 0.1784684000, 0.2348789000, 0.3562366000, 0.6151734000, 1.1698206000", \ - "0.1647270000, 0.1772564000, 0.2036949000, 0.2599285000, 0.3853496000, 0.6429225000, 1.2021832000", \ - "0.2149977000, 0.2286347000, 0.2562710000, 0.3128322000, 0.4334014000, 0.6922303000, 1.2472654000", \ - "0.2979482000, 0.3150995000, 0.3496113000, 0.4175952000, 0.5479686000, 0.8084229000, 1.3616064000", \ - "0.4299732000, 0.4546957000, 0.5044188000, 0.5972151000, 0.7636810000, 1.0616408000, 1.6263374000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0188828000, 0.0215447000, 0.0272004000, 0.0387132000, 0.0626389000, 0.1134835000, 0.2219731000", \ - "0.0186307000, 0.0211401000, 0.0265774000, 0.0382393000, 0.0624844000, 0.1131999000, 0.2224115000", \ - "0.0234069000, 0.0250992000, 0.0293283000, 0.0392741000, 0.0620323000, 0.1132265000, 0.2218917000", \ - "0.0367741000, 0.0392543000, 0.0440760000, 0.0530750000, 0.0701435000, 0.1149839000, 0.2220349000", \ - "0.0588981000, 0.0628183000, 0.0700100000, 0.0840150000, 0.1057796000, 0.1425454000, 0.2326944000", \ - "0.0987060000, 0.1048779000, 0.1167365000, 0.1355734000, 0.1715889000, 0.2240535000, 0.3114798000", \ - "0.1703011000, 0.1800227000, 0.1980877000, 0.2309827000, 0.2823701000, 0.3650451000, 0.4935419000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0944222000, 0.1106435000, 0.1460053000, 0.2218430000, 0.3833621000, 0.7311074000, 1.4787132000", \ - "0.0942916000, 0.1108252000, 0.1457097000, 0.2214804000, 0.3840627000, 0.7334590000, 1.4769638000", \ - "0.0944553000, 0.1105488000, 0.1462686000, 0.2217871000, 0.3833606000, 0.7303380000, 1.4744012000", \ - "0.0946895000, 0.1110768000, 0.1461941000, 0.2216568000, 0.3863308000, 0.7326029000, 1.4787044000", \ - "0.1052159000, 0.1195697000, 0.1525746000, 0.2245178000, 0.3832943000, 0.7295967000, 1.4771181000", \ - "0.1382806000, 0.1538840000, 0.1875708000, 0.2570373000, 0.4022198000, 0.7355604000, 1.4792408000", \ - "0.2175129000, 0.2340277000, 0.2700377000, 0.3443837000, 0.4955109000, 0.7975910000, 1.4959696000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0210286000, 0.0231584000, 0.0275486000, 0.0365832000, 0.0554018000, 0.0949617000, 0.1793860000", \ - "0.0258985000, 0.0279855000, 0.0322678000, 0.0413390000, 0.0601538000, 0.0997691000, 0.1840973000", \ - "0.0365900000, 0.0390049000, 0.0437149000, 0.0524915000, 0.0712008000, 0.1108314000, 0.1952663000", \ - "0.0511343000, 0.0548634000, 0.0621566000, 0.0750194000, 0.0972954000, 0.1368099000, 0.2209641000", \ - "0.0657911000, 0.0719522000, 0.0832957000, 0.1037809000, 0.1382351000, 0.1922022000, 0.2800002000", \ - "0.0731455000, 0.0821840000, 0.0991636000, 0.1321174000, 0.1856199000, 0.2725657000, 0.4034864000", \ - "0.0454279000, 0.0597746000, 0.0879312000, 0.1388164000, 0.2250413000, 0.3612277000, 0.5659628000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.1096101000, 0.1220293000, 0.1491551000, 0.2067473000, 0.3260444000, 0.5841350000, 1.1379190000", \ - "0.1121614000, 0.1251089000, 0.1517632000, 0.2088597000, 0.3300787000, 0.5890414000, 1.1447465000", \ - "0.1228155000, 0.1353394000, 0.1622530000, 0.2200269000, 0.3440103000, 0.5996139000, 1.1543468000", \ - "0.1484477000, 0.1610899000, 0.1876089000, 0.2446796000, 0.3663149000, 0.6263850000, 1.1852558000", \ - "0.2020485000, 0.2170115000, 0.2461228000, 0.3031843000, 0.4248584000, 0.6858575000, 1.2386281000", \ - "0.2926099000, 0.3133344000, 0.3541158000, 0.4281659000, 0.5627825000, 0.8227253000, 1.3856188000", \ - "0.4430030000, 0.4742545000, 0.5343008000, 0.6424213000, 0.8253253000, 1.1432399000, 1.7019122000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0168559000, 0.0193129000, 0.0246190000, 0.0357858000, 0.0599648000, 0.1121479000, 0.2236199000", \ - "0.0166403000, 0.0190183000, 0.0242904000, 0.0357198000, 0.0598766000, 0.1117103000, 0.2241610000", \ - "0.0213267000, 0.0229445000, 0.0271114000, 0.0370695000, 0.0597701000, 0.1117940000, 0.2239768000", \ - "0.0336114000, 0.0368035000, 0.0413787000, 0.0507674000, 0.0686529000, 0.1140934000, 0.2235141000", \ - "0.0557973000, 0.0596945000, 0.0681523000, 0.0815656000, 0.1045662000, 0.1439184000, 0.2344467000", \ - "0.0946591000, 0.1011267000, 0.1139911000, 0.1341444000, 0.1711751000, 0.2263170000, 0.3130438000", \ - "0.1647028000, 0.1753020000, 0.1950407000, 0.2287502000, 0.2835396000, 0.3690432000, 0.4984266000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0944003000, 0.1104369000, 0.1463148000, 0.2218535000, 0.3837208000, 0.7300238000, 1.4742131000", \ - "0.0942127000, 0.1108378000, 0.1455763000, 0.2214235000, 0.3835396000, 0.7301357000, 1.4787938000", \ - "0.0940723000, 0.1108670000, 0.1461854000, 0.2218054000, 0.3856453000, 0.7315752000, 1.4750824000", \ - "0.0952639000, 0.1113436000, 0.1463161000, 0.2217400000, 0.3838563000, 0.7312788000, 1.4777809000", \ - "0.1128279000, 0.1261770000, 0.1569277000, 0.2268480000, 0.3851188000, 0.7345888000, 1.4806878000", \ - "0.1594441000, 0.1752715000, 0.2076292000, 0.2729004000, 0.4093734000, 0.7333292000, 1.4857413000", \ - "0.2524597000, 0.2731071000, 0.3109158000, 0.3873711000, 0.5294026000, 0.8205849000, 1.4967634000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.1049400000, 0.1086010000, 0.1157049000, 0.1287366000, 0.1517693000, 0.1949430000, 0.2816807000", \ - "0.1099618000, 0.1136556000, 0.1207801000, 0.1337063000, 0.1567649000, 0.1999119000, 0.2865106000", \ - "0.1225243000, 0.1262875000, 0.1334463000, 0.1464383000, 0.1695171000, 0.2126436000, 0.2992513000", \ - "0.1542648000, 0.1580969000, 0.1652407000, 0.1782094000, 0.2012789000, 0.2444890000, 0.3313111000", \ - "0.2243720000, 0.2283376000, 0.2358079000, 0.2491652000, 0.2729637000, 0.3164929000, 0.4033025000", \ - "0.3405834000, 0.3456083000, 0.3551183000, 0.3711309000, 0.3976857000, 0.4440372000, 0.5321764000", \ - "0.5243336000, 0.5308660000, 0.5426786000, 0.5633771000, 0.5964688000, 0.6488755000, 0.7402265000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.1046562000, 0.1179900000, 0.1458289000, 0.2035317000, 0.3253962000, 0.5872496000, 1.1399136000", \ - "0.1095578000, 0.1224714000, 0.1500447000, 0.2086278000, 0.3309595000, 0.5893082000, 1.1473925000", \ - "0.1200331000, 0.1330866000, 0.1603494000, 0.2188912000, 0.3422764000, 0.6070581000, 1.1539282000", \ - "0.1400120000, 0.1528475000, 0.1794729000, 0.2377921000, 0.3609195000, 0.6233822000, 1.1817225000", \ - "0.1684873000, 0.1809913000, 0.2079457000, 0.2650770000, 0.3883332000, 0.6469948000, 1.2026523000", \ - "0.2036617000, 0.2155551000, 0.2413925000, 0.2976870000, 0.4198009000, 0.6781411000, 1.2422402000", \ - "0.2312159000, 0.2429651000, 0.2683872000, 0.3220858000, 0.4436716000, 0.7020302000, 1.2563248000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0267340000, 0.0293355000, 0.0350343000, 0.0459943000, 0.0689356000, 0.1181318000, 0.2284928000", \ - "0.0268579000, 0.0292621000, 0.0348096000, 0.0462327000, 0.0689544000, 0.1181618000, 0.2284416000", \ - "0.0267697000, 0.0294714000, 0.0349946000, 0.0460835000, 0.0687714000, 0.1181917000, 0.2283969000", \ - "0.0267869000, 0.0294866000, 0.0349692000, 0.0457891000, 0.0689551000, 0.1176335000, 0.2276813000", \ - "0.0303503000, 0.0328129000, 0.0378979000, 0.0482481000, 0.0703991000, 0.1186136000, 0.2283465000", \ - "0.0423879000, 0.0450150000, 0.0500154000, 0.0602523000, 0.0811982000, 0.1269422000, 0.2316553000", \ - "0.0627294000, 0.0661105000, 0.0725152000, 0.0829351000, 0.1021870000, 0.1443833000, 0.2421607000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010752300, 0.0023122300, 0.0049723500, 0.0106928000, 0.0229944000, 0.0494485000"); - values("0.0926988000, 0.1096847000, 0.1456341000, 0.2213401000, 0.3836514000, 0.7351700000, 1.4796802000", \ - "0.0926337000, 0.1097014000, 0.1451234000, 0.2216554000, 0.3848152000, 0.7316008000, 1.4774619000", \ - "0.0925810000, 0.1093648000, 0.1451516000, 0.2215642000, 0.3833383000, 0.7368203000, 1.4787099000", \ - "0.0921808000, 0.1088787000, 0.1451647000, 0.2216563000, 0.3836904000, 0.7320115000, 1.4789162000", \ - "0.0918261000, 0.1091095000, 0.1451189000, 0.2215155000, 0.3837113000, 0.7319699000, 1.4756265000", \ - "0.0933701000, 0.1095639000, 0.1452435000, 0.2213238000, 0.3868308000, 0.7303518000, 1.4850930000", \ - "0.1026232000, 0.1170962000, 0.1488300000, 0.2222510000, 0.3853950000, 0.7324820000, 1.4744607000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3b_2") { - leakage_power () { - value : 0.0044615000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0072634000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0046415000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0004774000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0045214000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0004804000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0026135000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0003540000; - when : "A&B&!C_N"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__nor3b"; - cell_leakage_power : 0.0031016480; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075918000, 0.0075932000, 0.0075965000, 0.0075996000, 0.0076069000, 0.0076236000, 0.0076623000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006883100, -0.006951500, -0.007109000, -0.007134000, -0.007191500, -0.007324100, -0.007629700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046090000; - } - pin ("B") { - capacitance : 0.0044790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082823000, 0.0082804000, 0.0082761000, 0.0082754000, 0.0082736000, 0.0082695000, 0.0082602000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007675200, -0.007753400, -0.007933600, -0.007938300, -0.007949200, -0.007974400, -0.008032300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047840000; - } - pin ("C_N") { - capacitance : 0.0012770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0107861000, 0.0107096000, 0.0105331000, 0.0106023000, 0.0107618000, 0.0111295000, 0.0119771000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039553000, 0.0039133000, 0.0038164000, 0.0038793000, 0.0040243000, 0.0043584000, 0.0051287000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0013180000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0107893000, 0.0096694000, 0.0069844000, 0.0005851000, -0.014664500, -0.051092900, -0.138719200", \ - "0.0105982000, 0.0094919000, 0.0068103000, 0.0003965000, -0.014813000, -0.051221300, -0.138824800", \ - "0.0104374000, 0.0093726000, 0.0066936000, 0.0002979000, -0.014949000, -0.051369400, -0.138967500", \ - "0.0100202000, 0.0089192000, 0.0063010000, -2.10000e-06, -0.015168900, -0.051573000, -0.139145500", \ - "0.0103001000, 0.0091885000, 0.0064796000, 4.500000e-05, -0.015246400, -0.051597300, -0.139271700", \ - "0.0116435000, 0.0104817000, 0.0077404000, 0.0012278000, -0.014232900, -0.051275000, -0.139033400", \ - "0.0144693000, 0.0132807000, 0.0103912000, 0.0036545000, -0.011978800, -0.049259500, -0.137923000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0213880000, 0.0225970000, 0.0253390000, 0.0319624000, 0.0472258000, 0.0836420000, 0.1704598000", \ - "0.0210558000, 0.0222113000, 0.0249786000, 0.0316447000, 0.0471485000, 0.0838080000, 0.1704754000", \ - "0.0207804000, 0.0219268000, 0.0246925000, 0.0312087000, 0.0467952000, 0.0832667000, 0.1710101000", \ - "0.0205934000, 0.0217232000, 0.0244284000, 0.0309779000, 0.0463179000, 0.0829989000, 0.1705428000", \ - "0.0204035000, 0.0215481000, 0.0242238000, 0.0306734000, 0.0461361000, 0.0825455000, 0.1700490000", \ - "0.0203550000, 0.0215388000, 0.0242470000, 0.0307089000, 0.0458415000, 0.0825209000, 0.1694393000", \ - "0.0200165000, 0.0211351000, 0.0238200000, 0.0304510000, 0.0461480000, 0.0824068000, 0.1694417000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0082209000, 0.0070972000, 0.0044125000, -0.002001200, -0.017330900, -0.053966900, -0.141840200", \ - "0.0081600000, 0.0070532000, 0.0043903000, -0.001993600, -0.017280600, -0.053910200, -0.141784000", \ - "0.0080594000, 0.0069653000, 0.0043198000, -0.001989900, -0.017197300, -0.053764800, -0.141618400", \ - "0.0075029000, 0.0065096000, 0.0039215000, -0.002290000, -0.017387600, -0.053906700, -0.141642000", \ - "0.0075876000, 0.0064671000, 0.0038461000, -0.002404800, -0.017667400, -0.054056600, -0.141742900", \ - "0.0083601000, 0.0071911000, 0.0045759000, -0.001882000, -0.017282100, -0.053966800, -0.141746500", \ - "0.0109470000, 0.0097368000, 0.0069027000, 9.850000e-05, -0.015687100, -0.052877400, -0.141166500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0163497000, 0.0175179000, 0.0203668000, 0.0270038000, 0.0423005000, 0.0787906000, 0.1658441000", \ - "0.0159531000, 0.0171337000, 0.0199084000, 0.0265460000, 0.0421391000, 0.0787681000, 0.1660968000", \ - "0.0156296000, 0.0168122000, 0.0195335000, 0.0262104000, 0.0416620000, 0.0783874000, 0.1655513000", \ - "0.0154559000, 0.0165818000, 0.0193104000, 0.0258712000, 0.0412491000, 0.0779584000, 0.1650595000", \ - "0.0152455000, 0.0163897000, 0.0190599000, 0.0255388000, 0.0409663000, 0.0774495000, 0.1646754000", \ - "0.0152134000, 0.0163480000, 0.0190819000, 0.0255286000, 0.0408873000, 0.0774978000, 0.1643801000", \ - "0.0162497000, 0.0173117000, 0.0198349000, 0.0260628000, 0.0413404000, 0.0773527000, 0.1650521000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0028831000, 0.0018979000, -0.000332500, -0.005851800, -0.020263300, -0.056389600, -0.144125800", \ - "0.0028257000, 0.0018421000, -0.000354500, -0.005904000, -0.020278100, -0.056414900, -0.144121100", \ - "0.0028831000, 0.0019193000, -0.000316300, -0.005843900, -0.020243200, -0.056383300, -0.144061700", \ - "0.0025799000, 0.0016108000, -0.000641200, -0.006208200, -0.020508300, -0.056595600, -0.144256600", \ - "0.0023162000, 0.0013403000, -0.000697800, -0.006392400, -0.020840800, -0.056919200, -0.144510300", \ - "0.0028259000, 0.0017329000, -0.000894900, -0.007147400, -0.021607100, -0.057397400, -0.144828400", \ - "0.0038442000, 0.0026835000, -1.63000e-05, -0.006413200, -0.021245000, -0.057520000, -0.144989100"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011954410, 0.0028581560, 0.0068335120, 0.0163381100, 0.0390624900, 0.0933937600"); - values("0.0143227000, 0.0155176000, 0.0183713000, 0.0251057000, 0.0406053000, 0.0776378000, 0.1643626000", \ - "0.0143073000, 0.0154798000, 0.0183519000, 0.0250838000, 0.0406998000, 0.0773535000, 0.1644024000", \ - "0.0143327000, 0.0155281000, 0.0183415000, 0.0250330000, 0.0406636000, 0.0777352000, 0.1645991000", \ - "0.0140944000, 0.0152684000, 0.0180395000, 0.0245907000, 0.0402068000, 0.0771009000, 0.1640245000", \ - "0.0138436000, 0.0149875000, 0.0177141000, 0.0241925000, 0.0396883000, 0.0767278000, 0.1636592000", \ - "0.0137399000, 0.0148477000, 0.0175464000, 0.0240513000, 0.0394364000, 0.0760998000, 0.1633900000", \ - "0.0141434000, 0.0152499000, 0.0179270000, 0.0242891000, 0.0391858000, 0.0758750000, 0.1631458000"); - } - } - max_capacitance : 0.0933940000; - max_transition : 1.4934560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0174638000, 0.0190365000, 0.0226516000, 0.0307326000, 0.0484098000, 0.0873477000, 0.1759946000", \ - "0.0229612000, 0.0243895000, 0.0277855000, 0.0355942000, 0.0530597000, 0.0919029000, 0.1806034000", \ - "0.0347826000, 0.0362820000, 0.0400741000, 0.0476890000, 0.0643720000, 0.1027379000, 0.1913351000", \ - "0.0515127000, 0.0539243000, 0.0592660000, 0.0702706000, 0.0907974000, 0.1291494000, 0.2171356000", \ - "0.0713027000, 0.0748824000, 0.0828645000, 0.0995355000, 0.1308267000, 0.1850730000, 0.2774496000", \ - "0.0873729000, 0.0927860000, 0.1049497000, 0.1300376000, 0.1780211000, 0.2626681000, 0.4005083000", \ - "0.0767385000, 0.0857307000, 0.1037695000, 0.1431844000, 0.2174440000, 0.3500095000, 0.5657276000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.1221256000, 0.1305824000, 0.1496599000, 0.1951484000, 0.3013165000, 0.5503449000, 1.1463153000", \ - "0.1261864000, 0.1341117000, 0.1535959000, 0.1991702000, 0.3063147000, 0.5557218000, 1.1528917000", \ - "0.1382274000, 0.1461819000, 0.1654061000, 0.2101782000, 0.3184524000, 0.5681136000, 1.1662157000", \ - "0.1651756000, 0.1729542000, 0.1923044000, 0.2369834000, 0.3428942000, 0.5937029000, 1.1959380000", \ - "0.2166414000, 0.2255109000, 0.2454650000, 0.2906873000, 0.3967636000, 0.6468667000, 1.2549816000", \ - "0.2994350000, 0.3112549000, 0.3361585000, 0.3917172000, 0.5093352000, 0.7624090000, 1.3618406000", \ - "0.4263933000, 0.4436008000, 0.4834204000, 0.5611777000, 0.7120740000, 1.0099822000, 1.6202764000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0172284000, 0.0191740000, 0.0235873000, 0.0333404000, 0.0547994000, 0.1037425000, 0.2199378000", \ - "0.0176181000, 0.0192377000, 0.0231761000, 0.0326919000, 0.0543472000, 0.1034575000, 0.2196236000", \ - "0.0235267000, 0.0246029000, 0.0272053000, 0.0347465000, 0.0540419000, 0.1029674000, 0.2194068000", \ - "0.0365299000, 0.0381868000, 0.0415610000, 0.0496586000, 0.0639097000, 0.1055603000, 0.2190303000", \ - "0.0584059000, 0.0609165000, 0.0664010000, 0.0773706000, 0.0990046000, 0.1360936000, 0.2301962000", \ - "0.0967209000, 0.1002059000, 0.1086585000, 0.1264877000, 0.1590051000, 0.2136456000, 0.3087806000", \ - "0.1640530000, 0.1705147000, 0.1849614000, 0.2130939000, 0.2629026000, 0.3475678000, 0.4856627000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0786376000, 0.0892441000, 0.1148131000, 0.1756683000, 0.3191343000, 0.6589938000, 1.4731059000", \ - "0.0787230000, 0.0894936000, 0.1148597000, 0.1756153000, 0.3200090000, 0.6607309000, 1.4710367000", \ - "0.0788195000, 0.0894819000, 0.1147593000, 0.1752546000, 0.3198784000, 0.6588909000, 1.4767021000", \ - "0.0791052000, 0.0897574000, 0.1148076000, 0.1757246000, 0.3187656000, 0.6583921000, 1.4756928000", \ - "0.0883152000, 0.0980765000, 0.1213959000, 0.1789737000, 0.3193649000, 0.6604566000, 1.4789494000", \ - "0.1171455000, 0.1277981000, 0.1528003000, 0.2104329000, 0.3399669000, 0.6661525000, 1.4718832000", \ - "0.1893233000, 0.2010237000, 0.2285320000, 0.2899236000, 0.4277675000, 0.7314248000, 1.4932042000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0193489000, 0.0208098000, 0.0241565000, 0.0316382000, 0.0484369000, 0.0868964000, 0.1771617000", \ - "0.0243250000, 0.0257413000, 0.0290197000, 0.0364772000, 0.0531105000, 0.0915847000, 0.1818195000", \ - "0.0349650000, 0.0366756000, 0.0404055000, 0.0479119000, 0.0642362000, 0.1026870000, 0.1929294000", \ - "0.0490542000, 0.0513882000, 0.0572468000, 0.0686824000, 0.0895352000, 0.1284876000, 0.2186378000", \ - "0.0634656000, 0.0674605000, 0.0762889000, 0.0941523000, 0.1268942000, 0.1840380000, 0.2794813000", \ - "0.0702492000, 0.0763105000, 0.0900865000, 0.1175766000, 0.1705429000, 0.2590498000, 0.4018602000", \ - "0.0443753000, 0.0538836000, 0.0751365000, 0.1183230000, 0.1998545000, 0.3415671000, 0.5659854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.1056506000, 0.1139644000, 0.1336405000, 0.1791973000, 0.2844225000, 0.5343299000, 1.1304507000", \ - "0.1081371000, 0.1164411000, 0.1359120000, 0.1812544000, 0.2909029000, 0.5400763000, 1.1384299000", \ - "0.1183909000, 0.1267085000, 0.1456014000, 0.1911606000, 0.2975707000, 0.5492276000, 1.1468408000", \ - "0.1441105000, 0.1521110000, 0.1709755000, 0.2160206000, 0.3219423000, 0.5735655000, 1.1720467000", \ - "0.1925439000, 0.2021914000, 0.2246456000, 0.2718669000, 0.3776812000, 0.6293186000, 1.2275156000", \ - "0.2729188000, 0.2873184000, 0.3177166000, 0.3814496000, 0.5076187000, 0.7628067000, 1.3611797000", \ - "0.3989712000, 0.4204742000, 0.4678765000, 0.5634965000, 0.7414186000, 1.0547635000, 1.6725850000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0157023000, 0.0173505000, 0.0211329000, 0.0300204000, 0.0507297000, 0.1004767000, 0.2201481000", \ - "0.0155179000, 0.0170636000, 0.0207184000, 0.0297086000, 0.0506304000, 0.1004902000, 0.2208906000", \ - "0.0207970000, 0.0217448000, 0.0242887000, 0.0315733000, 0.0507937000, 0.1005409000, 0.2210722000", \ - "0.0320793000, 0.0341693000, 0.0377584000, 0.0454598000, 0.0617161000, 0.1034529000, 0.2206680000", \ - "0.0529091000, 0.0558368000, 0.0619539000, 0.0739197000, 0.0955794000, 0.1350220000, 0.2307881000", \ - "0.0886423000, 0.0933428000, 0.1032525000, 0.1217018000, 0.1547436000, 0.2134803000, 0.3087702000", \ - "0.1549495000, 0.1623990000, 0.1782059000, 0.2080359000, 0.2597224000, 0.3481906000, 0.4895594000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0785831000, 0.0892690000, 0.1150037000, 0.1757348000, 0.3185399000, 0.6580178000, 1.4705089000", \ - "0.0786203000, 0.0891370000, 0.1148251000, 0.1751672000, 0.3192756000, 0.6605552000, 1.4763089000", \ - "0.0787095000, 0.0893925000, 0.1148128000, 0.1755939000, 0.3186210000, 0.6582317000, 1.4710358000", \ - "0.0797236000, 0.0900736000, 0.1153799000, 0.1756952000, 0.3188347000, 0.6593442000, 1.4729100000", \ - "0.0976543000, 0.1068154000, 0.1283792000, 0.1833857000, 0.3196129000, 0.6590216000, 1.4720406000", \ - "0.1385849000, 0.1496131000, 0.1744369000, 0.2303910000, 0.3510951000, 0.6659436000, 1.4702989000", \ - "0.2273998000, 0.2404269000, 0.2707507000, 0.3379102000, 0.4730307000, 0.7577503000, 1.4934559000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.1233045000, 0.1265290000, 0.1332351000, 0.1462338000, 0.1701202000, 0.2151784000, 0.3091362000", \ - "0.1282925000, 0.1314595000, 0.1381607000, 0.1510252000, 0.1750510000, 0.2201314000, 0.3139676000", \ - "0.1410908000, 0.1442519000, 0.1509404000, 0.1640650000, 0.1878945000, 0.2329762000, 0.3267936000", \ - "0.1713641000, 0.1745782000, 0.1812683000, 0.1943339000, 0.2185243000, 0.2637316000, 0.3575383000", \ - "0.2426369000, 0.2458537000, 0.2524868000, 0.2657254000, 0.2900578000, 0.3353928000, 0.4293949000", \ - "0.3670427000, 0.3709447000, 0.3791542000, 0.3949755000, 0.4224959000, 0.4712806000, 0.5669943000", \ - "0.5537659000, 0.5586502000, 0.5696646000, 0.5898181000, 0.6253303000, 0.6826723000, 0.7839706000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.1002572000, 0.1081896000, 0.1272421000, 0.1731871000, 0.2807507000, 0.5358910000, 1.1294202000", \ - "0.1052427000, 0.1131347000, 0.1320911000, 0.1778576000, 0.2857005000, 0.5373373000, 1.1393352000", \ - "0.1168936000, 0.1246580000, 0.1436795000, 0.1893183000, 0.2975079000, 0.5500173000, 1.1458181000", \ - "0.1426948000, 0.1503438000, 0.1690048000, 0.2138366000, 0.3214061000, 0.5732320000, 1.1712398000", \ - "0.1854434000, 0.1928193000, 0.2107946000, 0.2550296000, 0.3614146000, 0.6164616000, 1.2125616000", \ - "0.2440382000, 0.2515884000, 0.2691244000, 0.3120119000, 0.4178967000, 0.6685718000, 1.2673139000", \ - "0.3135723000, 0.3221469000, 0.3412599000, 0.3839925000, 0.4866147000, 0.7372059000, 1.3333868000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0287448000, 0.0306575000, 0.0350394000, 0.0450198000, 0.0651326000, 0.1109909000, 0.2255628000", \ - "0.0287221000, 0.0307057000, 0.0350281000, 0.0448600000, 0.0652021000, 0.1111103000, 0.2251626000", \ - "0.0287366000, 0.0306987000, 0.0350151000, 0.0447987000, 0.0651373000, 0.1108852000, 0.2252246000", \ - "0.0288938000, 0.0307854000, 0.0351056000, 0.0443648000, 0.0650648000, 0.1110938000, 0.2252963000", \ - "0.0304094000, 0.0325447000, 0.0366400000, 0.0460652000, 0.0659195000, 0.1113224000, 0.2250357000", \ - "0.0429485000, 0.0456606000, 0.0494942000, 0.0584037000, 0.0769245000, 0.1205395000, 0.2290940000", \ - "0.0637393000, 0.0662105000, 0.0718893000, 0.0828614000, 0.1015704000, 0.1425181000, 0.2426514000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011954400, 0.0028581600, 0.0068335100, 0.0163381000, 0.0390625000, 0.0933938000"); - values("0.0734222000, 0.0847731000, 0.1115934000, 0.1744354000, 0.3186205000, 0.6607144000, 1.4717295000", \ - "0.0735121000, 0.0846716000, 0.1115487000, 0.1738498000, 0.3188737000, 0.6604176000, 1.4743652000", \ - "0.0735841000, 0.0847153000, 0.1113493000, 0.1743161000, 0.3192989000, 0.6606415000, 1.4718693000", \ - "0.0733090000, 0.0844364000, 0.1112093000, 0.1738484000, 0.3192622000, 0.6594578000, 1.4721421000", \ - "0.0739970000, 0.0852509000, 0.1112869000, 0.1733261000, 0.3186068000, 0.6617412000, 1.4708805000", \ - "0.0791018000, 0.0890866000, 0.1132724000, 0.1734408000, 0.3198989000, 0.6603864000, 1.4718283000", \ - "0.0913414000, 0.1010330000, 0.1237505000, 0.1781506000, 0.3193945000, 0.6599492000, 1.4705360000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor3b_4") { - leakage_power () { - value : 0.0088421000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0045084000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0048605000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0006619000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0053392000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0007225000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0025465000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0205818000; - when : "A&B&!C_N"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__nor3b"; - cell_leakage_power : 0.0060078780; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0087190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150865000, 0.0150942000, 0.0151119000, 0.0151050000, 0.0150893000, 0.0150531000, 0.0149697000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013957700, -0.014081200, -0.014365800, -0.014413200, -0.014522500, -0.014774400, -0.015354900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091970000; - } - pin ("B") { - capacitance : 0.0084420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0164894000, 0.0164827000, 0.0164672000, 0.0164751000, 0.0164931000, 0.0165347000, 0.0166307000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014960000, -0.015147100, -0.015578400, -0.015593000, -0.015626800, -0.015704700, -0.015884200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090510000; - } - pin ("C_N") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0227238000, 0.0225835000, 0.0222600000, 0.0223986000, 0.0227180000, 0.0234544000, 0.0251518000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075975000, 0.0075120000, 0.0073150000, 0.0074166000, 0.0076509000, 0.0081910000, 0.0094358000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024850000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0205265000, 0.0192576000, 0.0159771000, 0.0075359000, -0.014213000, -0.070073300, -0.214661100", \ - "0.0201400000, 0.0188808000, 0.0156026000, 0.0071787000, -0.014523300, -0.070338100, -0.214921800", \ - "0.0198247000, 0.0185787000, 0.0154371000, 0.0069936000, -0.014764500, -0.070511400, -0.215117300", \ - "0.0192788000, 0.0180658000, 0.0148446000, 0.0065607000, -0.015205600, -0.070898200, -0.215375700", \ - "0.0191975000, 0.0179308000, 0.0146926000, 0.0063417000, -0.015299300, -0.070972400, -0.215521200", \ - "0.0218487000, 0.0205568000, 0.0172278000, 0.0086943000, -0.013237700, -0.070193400, -0.215000600", \ - "0.0273727000, 0.0261270000, 0.0225925000, 0.0137004000, -0.008641400, -0.066216200, -0.212700400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0410249000, 0.0422934000, 0.0457054000, 0.0542916000, 0.0764289000, 0.1318351000, 0.2754306000", \ - "0.0401734000, 0.0415701000, 0.0450416000, 0.0537622000, 0.0757115000, 0.1317289000, 0.2757093000", \ - "0.0395783000, 0.0409921000, 0.0443066000, 0.0529793000, 0.0750311000, 0.1313828000, 0.2761525000", \ - "0.0392858000, 0.0405775000, 0.0439536000, 0.0525188000, 0.0743789000, 0.1306416000, 0.2747238000", \ - "0.0388860000, 0.0401832000, 0.0434668000, 0.0520280000, 0.0740310000, 0.1298750000, 0.2746090000", \ - "0.0388747000, 0.0401450000, 0.0435032000, 0.0519931000, 0.0735029000, 0.1296196000, 0.2732577000", \ - "0.0385929000, 0.0398507000, 0.0430450000, 0.0522207000, 0.0746217000, 0.1301515000, 0.2737958000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0170515000, 0.0157864000, 0.0124912000, 0.0039824000, -0.017826100, -0.073958500, -0.218937200", \ - "0.0169781000, 0.0157247000, 0.0124642000, 0.0040254000, -0.017738200, -0.073778800, -0.218672000", \ - "0.0169168000, 0.0156576000, 0.0124554000, 0.0040733000, -0.017494300, -0.073401800, -0.218288600", \ - "0.0159538000, 0.0147269000, 0.0116219000, 0.0033481000, -0.017960800, -0.073702500, -0.218397400", \ - "0.0157713000, 0.0145258000, 0.0112883000, 0.0031822000, -0.018702800, -0.074148600, -0.218581700", \ - "0.0170710000, 0.0157939000, 0.0124926000, 0.0040716000, -0.017428900, -0.073572300, -0.218598800", \ - "0.0219701000, 0.0205908000, 0.0171117000, 0.0081900000, -0.014487400, -0.071318600, -0.217148800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0306559000, 0.0320596000, 0.0354317000, 0.0441545000, 0.0660787000, 0.1219934000, 0.2651940000", \ - "0.0297777000, 0.0312406000, 0.0346643000, 0.0433761000, 0.0658171000, 0.1219756000, 0.2650885000", \ - "0.0292275000, 0.0305470000, 0.0339427000, 0.0425998000, 0.0650827000, 0.1213983000, 0.2650111000", \ - "0.0288246000, 0.0301290000, 0.0334467000, 0.0420950000, 0.0642290000, 0.1206317000, 0.2643764000", \ - "0.0284373000, 0.0297272000, 0.0329744000, 0.0415448000, 0.0634976000, 0.1193746000, 0.2634282000", \ - "0.0284368000, 0.0297053000, 0.0330267000, 0.0414675000, 0.0632604000, 0.1193483000, 0.2628844000", \ - "0.0301673000, 0.0313126000, 0.0344563000, 0.0426252000, 0.0642929000, 0.1192656000, 0.2638014000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0077723000, 0.0066569000, 0.0038859000, -0.003386200, -0.023104400, -0.077905500, -0.222399300", \ - "0.0077942000, 0.0066535000, 0.0038301000, -0.003386900, -0.023164200, -0.077865600, -0.222411200", \ - "0.0078465000, 0.0067685000, 0.0039899000, -0.003264400, -0.023025700, -0.077773700, -0.222303600", \ - "0.0072985000, 0.0061877000, 0.0033143000, -0.003815100, -0.023590700, -0.078241700, -0.222642900", \ - "0.0065307000, 0.0053670000, 0.0025472000, -0.004788000, -0.024158100, -0.078816000, -0.223181500", \ - "0.0066735000, 0.0054311000, 0.0022246000, -0.005867400, -0.025855100, -0.079681900, -0.223745500", \ - "0.0101043000, 0.0090607000, 0.0057433000, -0.002630300, -0.024307300, -0.079868700, -0.223965800"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012885810, 0.0033208830, 0.0085584560, 0.0220565300, 0.0568432600, 0.1464943000"); - values("0.0291150000, 0.0305081000, 0.0340275000, 0.0428900000, 0.0654537000, 0.1218777000, 0.2665862000", \ - "0.0291044000, 0.0305078000, 0.0339470000, 0.0428969000, 0.0653870000, 0.1218086000, 0.2658963000", \ - "0.0291373000, 0.0305074000, 0.0340070000, 0.0429077000, 0.0652458000, 0.1217964000, 0.2658010000", \ - "0.0286161000, 0.0299732000, 0.0334298000, 0.0422579000, 0.0645038000, 0.1216804000, 0.2664545000", \ - "0.0282182000, 0.0295141000, 0.0329095000, 0.0412928000, 0.0634525000, 0.1204693000, 0.2655062000", \ - "0.0280671000, 0.0293545000, 0.0326159000, 0.0412388000, 0.0627328000, 0.1192954000, 0.2646329000", \ - "0.0287413000, 0.0299935000, 0.0330009000, 0.0414953000, 0.0627559000, 0.1192294000, 0.2631032000"); - } - } - max_capacitance : 0.1464940000; - max_transition : 1.4983920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0180535000, 0.0190306000, 0.0215461000, 0.0275991000, 0.0419278000, 0.0755601000, 0.1572186000", \ - "0.0233343000, 0.0242562000, 0.0265865000, 0.0324312000, 0.0464996000, 0.0799560000, 0.1614892000", \ - "0.0344013000, 0.0355037000, 0.0381037000, 0.0442771000, 0.0575425000, 0.0905679000, 0.1720237000", \ - "0.0496089000, 0.0511965000, 0.0550261000, 0.0637961000, 0.0816099000, 0.1160966000, 0.1964858000", \ - "0.0663308000, 0.0686086000, 0.0741816000, 0.0870521000, 0.1139484000, 0.1653060000, 0.2551916000", \ - "0.0747514000, 0.0781687000, 0.0865193000, 0.1058519000, 0.1472085000, 0.2258293000, 0.3626393000", \ - "0.0481251000, 0.0534651000, 0.0666529000, 0.0965894000, 0.1597645000, 0.2820445000, 0.4958208000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.1408186000, 0.1468816000, 0.1616228000, 0.1994349000, 0.2963655000, 0.5382451000, 1.1630007000", \ - "0.1437985000, 0.1496285000, 0.1650153000, 0.2033649000, 0.2991607000, 0.5428913000, 1.1743569000", \ - "0.1550015000, 0.1608562000, 0.1758124000, 0.2137805000, 0.3100277000, 0.5566993000, 1.1820869000", \ - "0.1799516000, 0.1856588000, 0.2004465000, 0.2381695000, 0.3339337000, 0.5789116000, 1.2159365000", \ - "0.2287550000, 0.2350445000, 0.2504359000, 0.2886105000, 0.3846719000, 0.6283352000, 1.2573574000", \ - "0.3086462000, 0.3160597000, 0.3344226000, 0.3800529000, 0.4865475000, 0.7348393000, 1.3612360000", \ - "0.4403033000, 0.4504767000, 0.4764006000, 0.5385576000, 0.6719524000, 0.9588654000, 1.6000756000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0189896000, 0.0202792000, 0.0233527000, 0.0309562000, 0.0493729000, 0.0947246000, 0.2109767000", \ - "0.0192050000, 0.0202645000, 0.0230848000, 0.0303121000, 0.0488392000, 0.0943826000, 0.2108743000", \ - "0.0248482000, 0.0256238000, 0.0277852000, 0.0333557000, 0.0492863000, 0.0938864000, 0.2105699000", \ - "0.0371174000, 0.0382770000, 0.0410656000, 0.0475828000, 0.0613222000, 0.0984779000, 0.2102863000", \ - "0.0582847000, 0.0599372000, 0.0638621000, 0.0730019000, 0.0925009000, 0.1312064000, 0.2254523000", \ - "0.0952870000, 0.0977261000, 0.1040076000, 0.1179937000, 0.1471434000, 0.2005569000, 0.3055344000", \ - "0.1630292000, 0.1671848000, 0.1772461000, 0.1988286000, 0.2431492000, 0.3215379000, 0.4679664000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0950738000, 0.1029152000, 0.1224635000, 0.1728771000, 0.3027454000, 0.6305259000, 1.4767154000", \ - "0.0955273000, 0.1030645000, 0.1226770000, 0.1731659000, 0.3017269000, 0.6311294000, 1.4795670000", \ - "0.0956322000, 0.1028962000, 0.1226437000, 0.1726269000, 0.3011289000, 0.6324990000, 1.4835865000", \ - "0.0956937000, 0.1033398000, 0.1229748000, 0.1733177000, 0.3017502000, 0.6309880000, 1.4808362000", \ - "0.1032361000, 0.1104927000, 0.1288875000, 0.1767701000, 0.3026409000, 0.6330331000, 1.4810247000", \ - "0.1297242000, 0.1372354000, 0.1567176000, 0.2053239000, 0.3236045000, 0.6380401000, 1.4780270000", \ - "0.1945596000, 0.2023014000, 0.2220948000, 0.2731890000, 0.3985198000, 0.7005056000, 1.4983920000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0196048000, 0.0205431000, 0.0228560000, 0.0284385000, 0.0417655000, 0.0741559000, 0.1554527000", \ - "0.0244357000, 0.0253297000, 0.0275815000, 0.0331140000, 0.0463956000, 0.0787738000, 0.1600187000", \ - "0.0345966000, 0.0356806000, 0.0381773000, 0.0441600000, 0.0571899000, 0.0895565000, 0.1707030000", \ - "0.0472281000, 0.0488480000, 0.0528226000, 0.0619533000, 0.0798711000, 0.1146033000, 0.1955783000", \ - "0.0590410000, 0.0615348000, 0.0674530000, 0.0812953000, 0.1097456000, 0.1619932000, 0.2542272000", \ - "0.0570921000, 0.0608698000, 0.0701627000, 0.0920702000, 0.1360611000, 0.2191647000, 0.3604516000", \ - "0.0122192000, 0.0182868000, 0.0328057000, 0.0663179000, 0.1354746000, 0.2669200000, 0.4880889000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.1242780000, 0.1305093000, 0.1460816000, 0.1844423000, 0.2796582000, 0.5259000000, 1.1487461000", \ - "0.1260200000, 0.1321965000, 0.1472952000, 0.1858265000, 0.2841344000, 0.5272467000, 1.1537064000", \ - "0.1360613000, 0.1420306000, 0.1568532000, 0.1950854000, 0.2933782000, 0.5377302000, 1.1641605000", \ - "0.1615900000, 0.1673524000, 0.1824098000, 0.2202732000, 0.3167724000, 0.5619148000, 1.1898783000", \ - "0.2126431000, 0.2196928000, 0.2366512000, 0.2761368000, 0.3721956000, 0.6186449000, 1.2448513000", \ - "0.2998622000, 0.3092387000, 0.3327338000, 0.3843003000, 0.4996342000, 0.7498871000, 1.3765812000", \ - "0.4463893000, 0.4610183000, 0.4946087000, 0.5719067000, 0.7311226000, 1.0406895000, 1.6890384000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0162089000, 0.0172588000, 0.0198495000, 0.0264885000, 0.0433868000, 0.0867963000, 0.1997371000", \ - "0.0161201000, 0.0170715000, 0.0195436000, 0.0262263000, 0.0432864000, 0.0868401000, 0.1998009000", \ - "0.0213030000, 0.0220149000, 0.0239451000, 0.0290526000, 0.0440094000, 0.0867227000, 0.1998797000", \ - "0.0326680000, 0.0338161000, 0.0365457000, 0.0426833000, 0.0567919000, 0.0918545000, 0.1999260000", \ - "0.0525430000, 0.0542633000, 0.0586016000, 0.0684457000, 0.0873786000, 0.1261002000, 0.2153077000", \ - "0.0886756000, 0.0914303000, 0.0981360000, 0.1126159000, 0.1426165000, 0.1967042000, 0.2984145000", \ - "0.1549547000, 0.1594875000, 0.1701660000, 0.1929726000, 0.2392072000, 0.3214980000, 0.4654595000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0953922000, 0.1030106000, 0.1225488000, 0.1730303000, 0.3018410000, 0.6323029000, 1.4763892000", \ - "0.0954791000, 0.1028664000, 0.1227349000, 0.1729386000, 0.3026973000, 0.6330446000, 1.4759819000", \ - "0.0952478000, 0.1029248000, 0.1228110000, 0.1726218000, 0.3026821000, 0.6329698000, 1.4766638000", \ - "0.0960570000, 0.1036865000, 0.1228511000, 0.1735074000, 0.3019045000, 0.6329706000, 1.4762763000", \ - "0.1116729000, 0.1177470000, 0.1350309000, 0.1811062000, 0.3036060000, 0.6321261000, 1.4771747000", \ - "0.1515120000, 0.1592445000, 0.1792248000, 0.2256245000, 0.3352074000, 0.6408961000, 1.4789051000", \ - "0.2399402000, 0.2489281000, 0.2719121000, 0.3256387000, 0.4501176000, 0.7292137000, 1.4968985000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.1217676000, 0.1236951000, 0.1283057000, 0.1383292000, 0.1580312000, 0.1968260000, 0.2800710000", \ - "0.1269149000, 0.1288598000, 0.1334889000, 0.1434775000, 0.1632674000, 0.2019990000, 0.2850465000", \ - "0.1401212000, 0.1421027000, 0.1466328000, 0.1566469000, 0.1765370000, 0.2154420000, 0.2984876000", \ - "0.1712354000, 0.1731794000, 0.1777596000, 0.1877963000, 0.2075607000, 0.2463654000, 0.3296623000", \ - "0.2443563000, 0.2462991000, 0.2508435000, 0.2609122000, 0.2808098000, 0.3198728000, 0.4032749000", \ - "0.3734126000, 0.3758364000, 0.3815577000, 0.3938881000, 0.4176470000, 0.4607292000, 0.5465864000", \ - "0.5755263000, 0.5787444000, 0.5860340000, 0.6019332000, 0.6324106000, 0.6852950000, 0.7787739000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.1240417000, 0.1298163000, 0.1449060000, 0.1836880000, 0.2818158000, 0.5284103000, 1.1570214000", \ - "0.1287793000, 0.1345236000, 0.1492848000, 0.1881340000, 0.2865634000, 0.5349404000, 1.1600875000", \ - "0.1396347000, 0.1455061000, 0.1604344000, 0.1990630000, 0.2969223000, 0.5437150000, 1.1764046000", \ - "0.1638765000, 0.1694684000, 0.1841512000, 0.2225209000, 0.3202998000, 0.5708960000, 1.1954854000", \ - "0.2067496000, 0.2121599000, 0.2265204000, 0.2629961000, 0.3599908000, 0.6096508000, 1.2353972000", \ - "0.2618571000, 0.2673492000, 0.2812557000, 0.3176624000, 0.4120826000, 0.6570098000, 1.2893641000", \ - "0.3179259000, 0.3237059000, 0.3368645000, 0.3730262000, 0.4663253000, 0.7110044000, 1.3365260000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0291893000, 0.0303341000, 0.0337264000, 0.0399628000, 0.0562205000, 0.0944228000, 0.1949947000", \ - "0.0293983000, 0.0306398000, 0.0336639000, 0.0401218000, 0.0561894000, 0.0943856000, 0.1950335000", \ - "0.0294955000, 0.0305560000, 0.0334966000, 0.0402924000, 0.0558031000, 0.0945647000, 0.1951346000", \ - "0.0292258000, 0.0303700000, 0.0331670000, 0.0401446000, 0.0560176000, 0.0944079000, 0.1948954000", \ - "0.0312065000, 0.0323110000, 0.0350164000, 0.0413892000, 0.0571945000, 0.0950048000, 0.1950770000", \ - "0.0453014000, 0.0466683000, 0.0488441000, 0.0556588000, 0.0696305000, 0.1050867000, 0.2000214000", \ - "0.0679940000, 0.0697095000, 0.0726788000, 0.0804793000, 0.0963640000, 0.1308921000, 0.2177179000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012885800, 0.0033208800, 0.0085584600, 0.0220565000, 0.0568433000, 0.1464940000"); - values("0.0907781000, 0.0986370000, 0.1193003000, 0.1713047000, 0.3026186000, 0.6309996000, 1.4803733000", \ - "0.0908448000, 0.0986015000, 0.1189951000, 0.1715032000, 0.3020749000, 0.6321674000, 1.4787579000", \ - "0.0907744000, 0.0987428000, 0.1190272000, 0.1714875000, 0.3019106000, 0.6310896000, 1.4802358000", \ - "0.0904554000, 0.0984922000, 0.1187707000, 0.1707458000, 0.3018448000, 0.6348124000, 1.4831802000", \ - "0.0917778000, 0.0990126000, 0.1191050000, 0.1707175000, 0.3016631000, 0.6339339000, 1.4828816000", \ - "0.0945655000, 0.1019518000, 0.1209435000, 0.1712839000, 0.3015750000, 0.6325379000, 1.4859218000", \ - "0.1074184000, 0.1136480000, 0.1319202000, 0.1773732000, 0.3025064000, 0.6351541000, 1.4761002000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4_1") { - leakage_power () { - value : 0.0025606000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0015417000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 8.2139272e-05; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0007090000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 8.2465766e-05; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0006652000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 4.4465012e-05; - when : "!A&B&C&D"; - } - leakage_power () { - value : 8.1062381e-05; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0001830000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0015228000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 5.9868919e-05; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0001608000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 6.0456712e-05; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0001640000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 3.8163977e-05; - when : "A&B&C&D"; - } - leakage_power () { - value : 6.2324413e-05; - when : "A&B&C&!D"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__nor4"; - cell_leakage_power : 0.0005011251; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040778000, 0.0040756000, 0.0040704000, 0.0040712000, 0.0040730000, 0.0040770000, 0.0040863000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003430000, -0.003465700, -0.003547900, -0.003562700, -0.003596900, -0.003675700, -0.003857300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024310000; - } - pin ("B") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039600000, 0.0039546000, 0.0039422000, 0.0039434000, 0.0039462000, 0.0039525000, 0.0039671000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003301900, -0.003334200, -0.003408700, -0.003426500, -0.003467600, -0.003562300, -0.003780600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024850000; - } - pin ("C") { - capacitance : 0.0024120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039761000, 0.0039754000, 0.0039737000, 0.0039718000, 0.0039674000, 0.0039574000, 0.0039342000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003477300, -0.003567800, -0.003776400, -0.003784700, -0.003803700, -0.003847500, -0.003948400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025860000; - } - pin ("D") { - capacitance : 0.0023470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025717000, 0.0025675000, 0.0025578000, 0.0025654000, 0.0025828000, 0.0026230000, 0.0027156000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001720900, -0.001720400, -0.001719400, -0.001719600, -0.001720100, -0.001721100, -0.001723600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025370000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0060654000, 0.0052332000, 0.0035108000, -2.13000e-05, -0.007220600, -0.021887900, -0.051965000", \ - "0.0059871000, 0.0051474000, 0.0034220000, -0.000114800, -0.007326300, -0.021974100, -0.052052100", \ - "0.0059196000, 0.0050720000, 0.0033881000, -0.000150400, -0.007365100, -0.022023600, -0.052086300", \ - "0.0058000000, 0.0049591000, 0.0032555000, -0.000283200, -0.007446200, -0.022111200, -0.052204000", \ - "0.0057391000, 0.0048932000, 0.0031939000, -0.000320200, -0.007463200, -0.022083200, -0.052220900", \ - "0.0064913000, 0.0056394000, 0.0038823000, 0.0003151000, -0.006987800, -0.021737700, -0.051952300", \ - "0.0081163000, 0.0072458000, 0.0054579000, 0.0019091000, -0.005489500, -0.020580100, -0.051140400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0142613000, 0.0151427000, 0.0168861000, 0.0204365000, 0.0276530000, 0.0424198000, 0.0723222000", \ - "0.0140787000, 0.0149642000, 0.0167152000, 0.0203466000, 0.0275613000, 0.0422439000, 0.0721875000", \ - "0.0139397000, 0.0147946000, 0.0165406000, 0.0201524000, 0.0273895000, 0.0422600000, 0.0721865000", \ - "0.0138250000, 0.0146774000, 0.0164049000, 0.0199645000, 0.0271885000, 0.0419782000, 0.0720524000", \ - "0.0137477000, 0.0145890000, 0.0163334000, 0.0198769000, 0.0271297000, 0.0418042000, 0.0718651000", \ - "0.0137166000, 0.0145645000, 0.0162627000, 0.0198217000, 0.0269783000, 0.0416839000, 0.0718843000", \ - "0.0134399000, 0.0143007000, 0.0162468000, 0.0198522000, 0.0271237000, 0.0416147000, 0.0716850000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0049490000, 0.0041101000, 0.0023805000, -0.001141600, -0.008315100, -0.022996200, -0.053200800", \ - "0.0049325000, 0.0040985000, 0.0023758000, -0.001152400, -0.008323200, -0.023012400, -0.053215400", \ - "0.0048999000, 0.0040582000, 0.0023641000, -0.001181200, -0.008329500, -0.023001500, -0.053195800", \ - "0.0047109000, 0.0038860000, 0.0021900000, -0.001294900, -0.008421300, -0.023083300, -0.053253700", \ - "0.0048159000, 0.0039808000, 0.0022771000, -0.001312500, -0.008509500, -0.023116600, -0.053278400", \ - "0.0052945000, 0.0044547000, 0.0027770000, -0.000936500, -0.007965800, -0.022816000, -0.053192400", \ - "0.0065045000, 0.0056240000, 0.0038156000, 0.0001433000, -0.007096800, -0.021948700, -0.052514800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0121848000, 0.0130485000, 0.0148254000, 0.0183818000, 0.0255868000, 0.0403321000, 0.0706061000", \ - "0.0119988000, 0.0128787000, 0.0146283000, 0.0182325000, 0.0254878000, 0.0402561000, 0.0703504000", \ - "0.0118459000, 0.0127146000, 0.0144410000, 0.0180946000, 0.0253310000, 0.0400786000, 0.0700751000", \ - "0.0117233000, 0.0125918000, 0.0143351000, 0.0178689000, 0.0251208000, 0.0399944000, 0.0701364000", \ - "0.0116471000, 0.0125035000, 0.0142421000, 0.0177568000, 0.0249851000, 0.0397038000, 0.0697252000", \ - "0.0116144000, 0.0124521000, 0.0141899000, 0.0176802000, 0.0248877000, 0.0396788000, 0.0695979000", \ - "0.0116168000, 0.0124588000, 0.0141781000, 0.0177481000, 0.0250403000, 0.0396278000, 0.0697780000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0035405000, 0.0026999000, 0.0009887000, -0.002521000, -0.009734700, -0.024520500, -0.054791800", \ - "0.0035960000, 0.0027660000, 0.0010664000, -0.002441000, -0.009630300, -0.024392700, -0.054681800", \ - "0.0037231000, 0.0028992000, 0.0012163000, -0.002252400, -0.009427400, -0.024157900, -0.054433100", \ - "0.0035517000, 0.0027418000, 0.0010676000, -0.002342400, -0.009474500, -0.024172800, -0.054403700", \ - "0.0035890000, 0.0027734000, 0.0010764000, -0.002396200, -0.009642400, -0.024254200, -0.054413200", \ - "0.0039189000, 0.0030894000, 0.0013649000, -0.002328400, -0.009461600, -0.024044800, -0.054349500", \ - "0.0049160000, 0.0040348000, 0.0022218000, -0.001453400, -0.008765600, -0.023496800, -0.053882300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0102488000, 0.0111227000, 0.0128905000, 0.0164945000, 0.0236898000, 0.0383993000, 0.0683816000", \ - "0.0099952000, 0.0109143000, 0.0126782000, 0.0162778000, 0.0235811000, 0.0383314000, 0.0683017000", \ - "0.0098367000, 0.0106707000, 0.0124505000, 0.0160489000, 0.0233965000, 0.0381883000, 0.0681653000", \ - "0.0096899000, 0.0105463000, 0.0122993000, 0.0158550000, 0.0232022000, 0.0379239000, 0.0680330000", \ - "0.0096005000, 0.0104579000, 0.0121987000, 0.0157381000, 0.0230215000, 0.0378006000, 0.0678023000", \ - "0.0095872000, 0.0104146000, 0.0121582000, 0.0157008000, 0.0229368000, 0.0377579000, 0.0676959000", \ - "0.0100459000, 0.0108626000, 0.0125344000, 0.0160008000, 0.0232046000, 0.0378746000, 0.0679499000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0005212000, -0.000326600, -0.002064300, -0.005617400, -0.012870800, -0.027685300, -0.057986200", \ - "0.0003854000, -0.000438600, -0.002136000, -0.005648800, -0.012842700, -0.027604800, -0.057904100", \ - "0.0001836000, -0.000626300, -0.002284500, -0.005722100, -0.012868400, -0.027572600, -0.057809600", \ - "-9.93000e-05, -0.000870200, -0.002476500, -0.005873200, -0.012953800, -0.027598200, -0.057813000", \ - "-8.21000e-05, -0.000880500, -0.002554200, -0.005953000, -0.013108700, -0.027716100, -0.057851900", \ - "0.0003288000, -0.000512500, -0.002404200, -0.005954600, -0.013108100, -0.027750800, -0.057815600", \ - "0.0016551000, 0.0007570000, -0.001120700, -0.004935500, -0.012344000, -0.027077400, -0.057325200"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0092451000, 0.0101334000, 0.0119257000, 0.0155187000, 0.0227648000, 0.0374684000, 0.0673783000", \ - "0.0089509000, 0.0098345000, 0.0117285000, 0.0152949000, 0.0226748000, 0.0373767000, 0.0674132000", \ - "0.0087862000, 0.0096499000, 0.0113983000, 0.0150541000, 0.0224174000, 0.0372814000, 0.0672215000", \ - "0.0087552000, 0.0095827000, 0.0112793000, 0.0148597000, 0.0221415000, 0.0369441000, 0.0671033000", \ - "0.0088461000, 0.0097336000, 0.0114453000, 0.0148936000, 0.0220631000, 0.0367687000, 0.0671404000", \ - "0.0096227000, 0.0100854000, 0.0117091000, 0.0151192000, 0.0221987000, 0.0367944000, 0.0667377000", \ - "0.0106716000, 0.0114485000, 0.0130661000, 0.0164207000, 0.0233136000, 0.0375978000, 0.0671126000"); - } - } - max_capacitance : 0.0366310000; - max_transition : 1.4862940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0212823000, 0.0234843000, 0.0278732000, 0.0365224000, 0.0533369000, 0.0859637000, 0.1497100000", \ - "0.0266493000, 0.0287580000, 0.0330124000, 0.0414868000, 0.0581550000, 0.0906175000, 0.1543478000", \ - "0.0390429000, 0.0412777000, 0.0454619000, 0.0534434000, 0.0696001000, 0.1017558000, 0.1653256000", \ - "0.0588975000, 0.0622019000, 0.0684135000, 0.0790917000, 0.0972438000, 0.1286306000, 0.1907604000", \ - "0.0851976000, 0.0900610000, 0.0985518000, 0.1153622000, 0.1427213000, 0.1862105000, 0.2531666000", \ - "0.1130083000, 0.1202760000, 0.1341262000, 0.1588652000, 0.2000950000, 0.2661626000, 0.3689386000", \ - "0.1226007000, 0.1336800000, 0.1547933000, 0.1924077000, 0.2568945000, 0.3621637000, 0.5214107000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1847200000, 0.1996022000, 0.2302879000, 0.2904752000, 0.4136790000, 0.6645016000, 1.1819372000", \ - "0.1878879000, 0.2030379000, 0.2339732000, 0.2954140000, 0.4180537000, 0.6691792000, 1.1812927000", \ - "0.1989508000, 0.2137425000, 0.2436191000, 0.3058041000, 0.4288770000, 0.6808631000, 1.2029691000", \ - "0.2235211000, 0.2383010000, 0.2682171000, 0.3290901000, 0.4539197000, 0.7040352000, 1.2174048000", \ - "0.2737899000, 0.2884173000, 0.3184587000, 0.3787085000, 0.5033303000, 0.7528986000, 1.2657013000", \ - "0.3589292000, 0.3758901000, 0.4107200000, 0.4771417000, 0.6033332000, 0.8546575000, 1.3722028000", \ - "0.4900051000, 0.5124120000, 0.5570517000, 0.6382261000, 0.7888656000, 1.0673695000, 1.5850897000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0207630000, 0.0235664000, 0.0291292000, 0.0402871000, 0.0613882000, 0.1028828000, 0.1840492000", \ - "0.0206008000, 0.0232644000, 0.0286594000, 0.0396696000, 0.0609522000, 0.1024281000, 0.1841818000", \ - "0.0252504000, 0.0272025000, 0.0314851000, 0.0406667000, 0.0606235000, 0.1018597000, 0.1844156000", \ - "0.0396411000, 0.0419485000, 0.0462475000, 0.0540672000, 0.0689655000, 0.1046904000, 0.1839909000", \ - "0.0647039000, 0.0681180000, 0.0747133000, 0.0856562000, 0.1055685000, 0.1347053000, 0.1978310000", \ - "0.1065801000, 0.1124303000, 0.1218484000, 0.1389722000, 0.1668071000, 0.2149118000, 0.2812705000", \ - "0.1832069000, 0.1911439000, 0.2060488000, 0.2337147000, 0.2765342000, 0.3449524000, 0.4455827000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1359170000, 0.1552237000, 0.1946831000, 0.2738837000, 0.4376941000, 0.7733209000, 1.4557837000", \ - "0.1359987000, 0.1553788000, 0.1947506000, 0.2751287000, 0.4383902000, 0.7727586000, 1.4525354000", \ - "0.1368614000, 0.1555785000, 0.1941481000, 0.2744453000, 0.4376826000, 0.7736397000, 1.4579907000", \ - "0.1369654000, 0.1556995000, 0.1941420000, 0.2746756000, 0.4385214000, 0.7703161000, 1.4514481000", \ - "0.1401409000, 0.1581084000, 0.1957535000, 0.2747009000, 0.4386802000, 0.7702323000, 1.4522956000", \ - "0.1660192000, 0.1838254000, 0.2212660000, 0.2951204000, 0.4481477000, 0.7738601000, 1.4576154000", \ - "0.2250565000, 0.2439809000, 0.2837575000, 0.3630928000, 0.5182175000, 0.8249998000, 1.4700795000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0219756000, 0.0241162000, 0.0282910000, 0.0364848000, 0.0522544000, 0.0829617000, 0.1438243000", \ - "0.0271751000, 0.0292312000, 0.0333311000, 0.0413375000, 0.0569317000, 0.0875474000, 0.1482678000", \ - "0.0391178000, 0.0412760000, 0.0453048000, 0.0527453000, 0.0680817000, 0.0985681000, 0.1592889000", \ - "0.0568738000, 0.0599541000, 0.0660293000, 0.0761284000, 0.0941247000, 0.1243690000, 0.1850269000", \ - "0.0776754000, 0.0825250000, 0.0916758000, 0.1080345000, 0.1353112000, 0.1789275000, 0.2442368000", \ - "0.0937662000, 0.1010725000, 0.1148336000, 0.1402461000, 0.1819362000, 0.2503735000, 0.3537707000", \ - "0.0802927000, 0.0919389000, 0.1140292000, 0.1529297000, 0.2207724000, 0.3268159000, 0.4894080000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1730702000, 0.1878031000, 0.2187547000, 0.2790272000, 0.4023048000, 0.6544730000, 1.1744684000", \ - "0.1749528000, 0.1905021000, 0.2204503000, 0.2825207000, 0.4067050000, 0.6588492000, 1.1705699000", \ - "0.1852613000, 0.2003009000, 0.2301761000, 0.2924643000, 0.4157092000, 0.6676407000, 1.1811239000", \ - "0.2107242000, 0.2258753000, 0.2557310000, 0.3166380000, 0.4403007000, 0.6924853000, 1.2090526000", \ - "0.2663138000, 0.2811116000, 0.3110725000, 0.3722297000, 0.4948983000, 0.7464220000, 1.2599082000", \ - "0.3633048000, 0.3815877000, 0.4179208000, 0.4870964000, 0.6154315000, 0.8674876000, 1.3787953000", \ - "0.5225874000, 0.5496246000, 0.6003883000, 0.6931884000, 0.8548106000, 1.1372531000, 1.6552956000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0201536000, 0.0227255000, 0.0277097000, 0.0376435000, 0.0570899000, 0.0960721000, 0.1758050000", \ - "0.0196702000, 0.0221198000, 0.0271489000, 0.0372012000, 0.0568365000, 0.0959606000, 0.1755532000", \ - "0.0236320000, 0.0254214000, 0.0294163000, 0.0380446000, 0.0565366000, 0.0957121000, 0.1752176000", \ - "0.0367760000, 0.0391241000, 0.0434045000, 0.0519419000, 0.0655839000, 0.0990892000, 0.1752644000", \ - "0.0598535000, 0.0631734000, 0.0698094000, 0.0817449000, 0.0997580000, 0.1311222000, 0.1919303000", \ - "0.1012209000, 0.1067407000, 0.1167907000, 0.1329488000, 0.1654638000, 0.2075611000, 0.2766635000", \ - "0.1749777000, 0.1835525000, 0.1992999000, 0.2277764000, 0.2702707000, 0.3416153000, 0.4406554000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1359203000, 0.1549453000, 0.1946697000, 0.2740058000, 0.4376358000, 0.7732493000, 1.4666257000", \ - "0.1361696000, 0.1554146000, 0.1942436000, 0.2746763000, 0.4382373000, 0.7730988000, 1.4562885000", \ - "0.1362172000, 0.1561478000, 0.1956037000, 0.2751581000, 0.4384815000, 0.7722958000, 1.4512166000", \ - "0.1364125000, 0.1555701000, 0.1947248000, 0.2743235000, 0.4376735000, 0.7734419000, 1.4567212000", \ - "0.1426283000, 0.1603590000, 0.1980671000, 0.2755797000, 0.4387952000, 0.7714703000, 1.4519383000", \ - "0.1778651000, 0.1957145000, 0.2325984000, 0.3020062000, 0.4530511000, 0.7743556000, 1.4525313000", \ - "0.2639897000, 0.2822733000, 0.3197553000, 0.3961242000, 0.5455561000, 0.8331036000, 1.4742604000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0224397000, 0.0243324000, 0.0280258000, 0.0354120000, 0.0500532000, 0.0794116000, 0.1389092000", \ - "0.0272887000, 0.0291664000, 0.0328565000, 0.0401676000, 0.0548114000, 0.0842154000, 0.1436600000", \ - "0.0381903000, 0.0403324000, 0.0442959000, 0.0515839000, 0.0659254000, 0.0953372000, 0.1547511000", \ - "0.0530838000, 0.0564647000, 0.0626311000, 0.0734947000, 0.0910741000, 0.1210523000, 0.1803969000", \ - "0.0687386000, 0.0739253000, 0.0836562000, 0.1008451000, 0.1292508000, 0.1736066000, 0.2411073000", \ - "0.0747862000, 0.0828898000, 0.0980596000, 0.1262407000, 0.1715829000, 0.2397811000, 0.3453614000", \ - "0.0459568000, 0.0590248000, 0.0834173000, 0.1265507000, 0.1985104000, 0.3091157000, 0.4749944000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1433813000, 0.1585324000, 0.1884837000, 0.2501398000, 0.3740720000, 0.6236380000, 1.1350662000", \ - "0.1443134000, 0.1599851000, 0.1900199000, 0.2519273000, 0.3763733000, 0.6324293000, 1.1393744000", \ - "0.1535532000, 0.1680074000, 0.1983770000, 0.2599530000, 0.3847517000, 0.6405465000, 1.1497204000", \ - "0.1779417000, 0.1923761000, 0.2228940000, 0.2844233000, 0.4102364000, 0.6600023000, 1.1740220000", \ - "0.2343332000, 0.2499545000, 0.2804208000, 0.3415210000, 0.4661353000, 0.7165806000, 1.2291163000", \ - "0.3338594000, 0.3549855000, 0.3951234000, 0.4693723000, 0.6007331000, 0.8520349000, 1.3667651000", \ - "0.5005567000, 0.5321879000, 0.5914930000, 0.6952653000, 0.8710038000, 1.1676040000, 1.6840942000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0169824000, 0.0192405000, 0.0237494000, 0.0329892000, 0.0519012000, 0.0902017000, 0.1694073000", \ - "0.0166974000, 0.0189479000, 0.0235484000, 0.0328492000, 0.0517856000, 0.0901972000, 0.1691870000", \ - "0.0207838000, 0.0224628000, 0.0260790000, 0.0343354000, 0.0520386000, 0.0901936000, 0.1691981000", \ - "0.0330604000, 0.0354796000, 0.0399349000, 0.0482197000, 0.0621188000, 0.0943873000, 0.1687799000", \ - "0.0548224000, 0.0585900000, 0.0657081000, 0.0772059000, 0.0963999000, 0.1285713000, 0.1869701000", \ - "0.0958434000, 0.1015715000, 0.1120935000, 0.1293489000, 0.1590652000, 0.2055605000, 0.2739545000", \ - "0.1679885000, 0.1772578000, 0.1937140000, 0.2224413000, 0.2667224000, 0.3382686000, 0.4399514000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1360922000, 0.1551485000, 0.1941492000, 0.2747421000, 0.4383641000, 0.7719844000, 1.4510000000", \ - "0.1356780000, 0.1554770000, 0.1942201000, 0.2742369000, 0.4382031000, 0.7729953000, 1.4550843000", \ - "0.1362572000, 0.1547840000, 0.1942124000, 0.2741087000, 0.4382508000, 0.7728392000, 1.4559206000", \ - "0.1357204000, 0.1547927000, 0.1940851000, 0.2746516000, 0.4407319000, 0.7703586000, 1.4518986000", \ - "0.1470584000, 0.1645234000, 0.2007092000, 0.2777870000, 0.4393268000, 0.7721175000, 1.4538620000", \ - "0.1958232000, 0.2133624000, 0.2491863000, 0.3161797000, 0.4583426000, 0.7767802000, 1.4528329000", \ - "0.2933375000, 0.3148246000, 0.3568567000, 0.4332570000, 0.5791093000, 0.8556169000, 1.4750566000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0188271000, 0.0206541000, 0.0243014000, 0.0316186000, 0.0463311000, 0.0763285000, 0.1373366000", \ - "0.0236101000, 0.0254682000, 0.0290591000, 0.0364206000, 0.0512959000, 0.0812439000, 0.1422077000", \ - "0.0328943000, 0.0354679000, 0.0400778000, 0.0479081000, 0.0627537000, 0.0925465000, 0.1537874000", \ - "0.0443728000, 0.0483836000, 0.0556682000, 0.0681012000, 0.0881235000, 0.1191564000, 0.1802909000", \ - "0.0551252000, 0.0613511000, 0.0730135000, 0.0926691000, 0.1242690000, 0.1716214000, 0.2414118000", \ - "0.0551735000, 0.0651094000, 0.0840851000, 0.1153661000, 0.1655855000, 0.2406581000, 0.3476230000", \ - "0.0175201000, 0.0340024000, 0.0638317000, 0.1144138000, 0.1943232000, 0.3141229000, 0.4858466000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0903391000, 0.1056903000, 0.1362071000, 0.1974330000, 0.3211541000, 0.5720612000, 1.0844540000", \ - "0.0901059000, 0.1050222000, 0.1370071000, 0.1984101000, 0.3247785000, 0.5747719000, 1.0867576000", \ - "0.0983467000, 0.1130281000, 0.1431094000, 0.2046621000, 0.3297016000, 0.5827376000, 1.0968489000", \ - "0.1238673000, 0.1373701000, 0.1657784000, 0.2261639000, 0.3509734000, 0.6027804000, 1.1166690000", \ - "0.1847425000, 0.1998574000, 0.2285653000, 0.2838802000, 0.4065415000, 0.6569106000, 1.1744924000", \ - "0.2795951000, 0.3011321000, 0.3424288000, 0.4175821000, 0.5453300000, 0.7918366000, 1.3017210000", \ - "0.4347989000, 0.4657564000, 0.5258790000, 0.6333455000, 0.8142279000, 1.1118314000, 1.6121059000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0129235000, 0.0151465000, 0.0199610000, 0.0293294000, 0.0491618000, 0.0893417000, 0.1706883000", \ - "0.0131855000, 0.0153364000, 0.0199276000, 0.0296028000, 0.0486574000, 0.0889930000, 0.1713389000", \ - "0.0188729000, 0.0206013000, 0.0238309000, 0.0316394000, 0.0494134000, 0.0884582000, 0.1712729000", \ - "0.0308751000, 0.0333286000, 0.0381233000, 0.0463886000, 0.0606838000, 0.0934619000, 0.1699213000", \ - "0.0523688000, 0.0565030000, 0.0635170000, 0.0763649000, 0.0956798000, 0.1272604000, 0.1878242000", \ - "0.0931540000, 0.0987046000, 0.1109001000, 0.1273295000, 0.1572639000, 0.2036202000, 0.2767707000", \ - "0.1689100000, 0.1797050000, 0.1945839000, 0.2226183000, 0.2672972000, 0.3369947000, 0.4423309000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1311981000, 0.1515316000, 0.1921048000, 0.2733487000, 0.4376697000, 0.7726835000, 1.4512873000", \ - "0.1297504000, 0.1504814000, 0.1922167000, 0.2730611000, 0.4388007000, 0.7707638000, 1.4517202000", \ - "0.1270757000, 0.1483907000, 0.1901530000, 0.2732212000, 0.4383436000, 0.7725835000, 1.4505380000", \ - "0.1264069000, 0.1455190000, 0.1860642000, 0.2710657000, 0.4381435000, 0.7699137000, 1.4508219000", \ - "0.1490536000, 0.1651557000, 0.1997201000, 0.2727860000, 0.4341423000, 0.7707072000, 1.4625751000", \ - "0.1963986000, 0.2166108000, 0.2573342000, 0.3285849000, 0.4654751000, 0.7745740000, 1.4522370000", \ - "0.2792530000, 0.3078553000, 0.3568472000, 0.4506795000, 0.6066595000, 0.8840420000, 1.4862936000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4_2") { - leakage_power () { - value : 9.0724479e-05; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0001408000; - when : "A&B&C&!D"; - } - leakage_power () { - value : 0.0036845000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0030832000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0002442000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0022266000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0002444000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0021358000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0001313000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0002461000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0003365000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0021041000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0001299000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0002487000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0001265000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0002583000; - when : "A&B&!C&!D"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__nor4"; - cell_leakage_power : 0.0009644675; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0074710000, 0.0074665000, 0.0074563000, 0.0074596000, 0.0074672000, 0.0074847000, 0.0075251000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006628400, -0.006705100, -0.006881800, -0.006916400, -0.006996200, -0.007180000, -0.007603800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045830000; - } - pin ("B") { - capacitance : 0.0043070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091253000, 0.0091242000, 0.0091217000, 0.0091198000, 0.0091154000, 0.0091052000, 0.0090817000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006762800, -0.006810900, -0.006921600, -0.006954900, -0.007031600, -0.007208600, -0.007616500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046080000; - } - pin ("C") { - capacitance : 0.0043000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082417000, 0.0082398000, 0.0082354000, 0.0082401000, 0.0082509000, 0.0082758000, 0.0083332000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006909900, -0.007055400, -0.007390800, -0.007408100, -0.007447900, -0.007539800, -0.007751500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046380000; - } - pin ("D") { - capacitance : 0.0042970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044731000, 0.0044659000, 0.0044493000, 0.0044699000, 0.0045173000, 0.0046267000, 0.0048787000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003418300, -0.003418300, -0.003418300, -0.003416900, -0.003413600, -0.003406000, -0.003388400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046680000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0130284000, 0.0120197000, 0.0097689000, 0.0047162000, -0.006651100, -0.032129900, -0.089100700", \ - "0.0128438000, 0.0118516000, 0.0095977000, 0.0045344000, -0.006823500, -0.032264500, -0.089255300", \ - "0.0127313000, 0.0117024000, 0.0094803000, 0.0044354000, -0.006966000, -0.032382400, -0.089363200", \ - "0.0124401000, 0.0114312000, 0.0091964000, 0.0041980000, -0.007210900, -0.032632400, -0.089601900", \ - "0.0121480000, 0.0111551000, 0.0089241000, 0.0039681000, -0.007296700, -0.032704600, -0.089605500", \ - "0.0137727000, 0.0127434000, 0.0104460000, 0.0052922000, -0.006110300, -0.032021800, -0.089372000", \ - "0.0166367000, 0.0155872000, 0.0132526000, 0.0081951000, -0.003491200, -0.029575700, -0.087639900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0287875000, 0.0298175000, 0.0321801000, 0.0372424000, 0.0486435000, 0.0740613000, 0.1307851000", \ - "0.0284711000, 0.0294753000, 0.0318289000, 0.0369529000, 0.0484236000, 0.0739263000, 0.1309251000", \ - "0.0281256000, 0.0291841000, 0.0314566000, 0.0366394000, 0.0481049000, 0.0738271000, 0.1311391000", \ - "0.0279422000, 0.0289971000, 0.0312730000, 0.0363411000, 0.0477663000, 0.0733794000, 0.1304999000", \ - "0.0277532000, 0.0287609000, 0.0310206000, 0.0361411000, 0.0475595000, 0.0729280000, 0.1301431000", \ - "0.0277163000, 0.0287145000, 0.0309642000, 0.0359990000, 0.0473639000, 0.0729720000, 0.1298406000", \ - "0.0273679000, 0.0285756000, 0.0308981000, 0.0359837000, 0.0475017000, 0.0725922000, 0.1298778000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0100157000, 0.0090120000, 0.0067623000, 0.0017005000, -0.009642100, -0.034994000, -0.092241800", \ - "0.0100179000, 0.0089974000, 0.0067469000, 0.0016838000, -0.009640200, -0.035004000, -0.092255300", \ - "0.0099416000, 0.0089481000, 0.0067072000, 0.0016771000, -0.009654100, -0.035013800, -0.092224500", \ - "0.0096152000, 0.0086280000, 0.0064091000, 0.0014305000, -0.009815700, -0.035097000, -0.092317100", \ - "0.0096692000, 0.0086541000, 0.0063838000, 0.0012875000, -0.009992500, -0.035220400, -0.092354100", \ - "0.0106974000, 0.0097364000, 0.0074863000, 0.0024766000, -0.008984500, -0.034708800, -0.092177800", \ - "0.0133206000, 0.0122639000, 0.0098848000, 0.0045972000, -0.006938000, -0.032910600, -0.090760800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0225975000, 0.0236289000, 0.0259982000, 0.0310818000, 0.0425042000, 0.0679458000, 0.1255043000", \ - "0.0222309000, 0.0232462000, 0.0256109000, 0.0307767000, 0.0422472000, 0.0677990000, 0.1247980000", \ - "0.0218476000, 0.0228957000, 0.0252143000, 0.0304014000, 0.0419548000, 0.0675139000, 0.1245685000", \ - "0.0216468000, 0.0227051000, 0.0249418000, 0.0300889000, 0.0415880000, 0.0671324000, 0.1242576000", \ - "0.0214618000, 0.0224808000, 0.0247184000, 0.0298311000, 0.0413122000, 0.0666748000, 0.1241631000", \ - "0.0213697000, 0.0223914000, 0.0246852000, 0.0297651000, 0.0410355000, 0.0666059000, 0.1235866000", \ - "0.0215558000, 0.0225502000, 0.0248001000, 0.0298838000, 0.0415381000, 0.0666328000, 0.1238652000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0076335000, 0.0066295000, 0.0043907000, -0.000642900, -0.011968600, -0.037469700, -0.094917300", \ - "0.0076962000, 0.0067027000, 0.0044743000, -0.000529300, -0.011802300, -0.037296100, -0.094746400", \ - "0.0078558000, 0.0068779000, 0.0046771000, -0.000297300, -0.011508600, -0.036949500, -0.094312000", \ - "0.0075835000, 0.0065956000, 0.0044278000, -0.000492800, -0.011607500, -0.036976800, -0.094312900", \ - "0.0076475000, 0.0066783000, 0.0044629000, -0.000505900, -0.011917600, -0.037148100, -0.094338700", \ - "0.0082141000, 0.0072108000, 0.0049761000, 2.320000e-05, -0.011423300, -0.036887200, -0.094332600", \ - "0.0104270000, 0.0093551000, 0.0070069000, 0.0017269000, -0.010031900, -0.035761600, -0.093437300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0191213000, 0.0201547000, 0.0224737000, 0.0276574000, 0.0391815000, 0.0645562000, 0.1218996000", \ - "0.0187518000, 0.0197560000, 0.0221517000, 0.0272985000, 0.0388998000, 0.0643722000, 0.1216919000", \ - "0.0184150000, 0.0194114000, 0.0217778000, 0.0269027000, 0.0384162000, 0.0640884000, 0.1211389000", \ - "0.0181649000, 0.0191547000, 0.0215042000, 0.0266030000, 0.0380941000, 0.0636854000, 0.1208614000", \ - "0.0179073000, 0.0189464000, 0.0211997000, 0.0263199000, 0.0376820000, 0.0632214000, 0.1203851000", \ - "0.0179127000, 0.0188916000, 0.0211581000, 0.0261939000, 0.0376541000, 0.0632177000, 0.1204888000", \ - "0.0184885000, 0.0194785000, 0.0216711000, 0.0266334000, 0.0379242000, 0.0631364000, 0.1205011000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0006149000, -0.000395700, -0.002676900, -0.007831600, -0.019354800, -0.045065300, -0.102640000", \ - "0.0003663000, -0.000628500, -0.002856700, -0.007898900, -0.019319200, -0.044916200, -0.102440000", \ - "-2.33000e-05, -0.000974600, -0.003155200, -0.008103100, -0.019365600, -0.044817000, -0.102252300", \ - "-0.000520400, -0.001401200, -0.003675800, -0.008466000, -0.019523400, -0.044841300, -0.102153600", \ - "-0.000576100, -0.001515600, -0.003656900, -0.008527500, -0.019618400, -0.045002400, -0.102195300", \ - "0.0001152000, -0.000874000, -0.003106700, -0.008411900, -0.019409000, -0.044749600, -0.102202300", \ - "0.0031988000, 0.0021786000, -0.000953500, -0.006409500, -0.018246400, -0.043900900, -0.101580900"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011227450, 0.0025211130, 0.0056611350, 0.0127120200, 0.0285447200, 0.0640968900"); - values("0.0178812000, 0.0189363000, 0.0213264000, 0.0266082000, 0.0380634000, 0.0637161000, 0.1208378000", \ - "0.0173390000, 0.0184400000, 0.0208636000, 0.0261402000, 0.0377266000, 0.0633700000, 0.1203746000", \ - "0.0170459000, 0.0181134000, 0.0204686000, 0.0256198000, 0.0373986000, 0.0630041000, 0.1202045000", \ - "0.0167815000, 0.0178156000, 0.0200932000, 0.0252549000, 0.0367066000, 0.0624425000, 0.1201492000", \ - "0.0169691000, 0.0179690000, 0.0201852000, 0.0252186000, 0.0365658000, 0.0620517000, 0.1195766000", \ - "0.0181963000, 0.0191985000, 0.0213997000, 0.0263195000, 0.0373943000, 0.0620773000, 0.1191686000", \ - "0.0205777000, 0.0215047000, 0.0235862000, 0.0283932000, 0.0392594000, 0.0640179000, 0.1198470000"); - } - } - max_capacitance : 0.0640970000; - max_transition : 1.4876160000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0187713000, 0.0200900000, 0.0229711000, 0.0292571000, 0.0427578000, 0.0713906000, 0.1322000000", \ - "0.0242278000, 0.0254706000, 0.0282438000, 0.0343376000, 0.0476410000, 0.0760561000, 0.1367284000", \ - "0.0363310000, 0.0377925000, 0.0408142000, 0.0468365000, 0.0595051000, 0.0871717000, 0.1475017000", \ - "0.0542579000, 0.0564017000, 0.0609028000, 0.0697844000, 0.0857490000, 0.1143040000, 0.1737668000", \ - "0.0779258000, 0.0810440000, 0.0875971000, 0.1004099000, 0.1249966000, 0.1668213000, 0.2351737000", \ - "0.1005380000, 0.1052627000, 0.1152750000, 0.1350978000, 0.1713770000, 0.2362926000, 0.3406248000", \ - "0.1014119000, 0.1084063000, 0.1232528000, 0.1537416000, 0.2097768000, 0.3108372000, 0.4734844000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.2021592000, 0.2121610000, 0.2351810000, 0.2845141000, 0.3947034000, 0.6401782000, 1.1896456000", \ - "0.2050959000, 0.2153341000, 0.2379860000, 0.2879163000, 0.3988190000, 0.6451023000, 1.1950138000", \ - "0.2157930000, 0.2262210000, 0.2487763000, 0.2991486000, 0.4106315000, 0.6570174000, 1.2086372000", \ - "0.2420663000, 0.2525829000, 0.2748867000, 0.3246607000, 0.4346401000, 0.6815490000, 1.2336163000", \ - "0.2957066000, 0.3060008000, 0.3284738000, 0.3779119000, 0.4887682000, 0.7336964000, 1.2851961000", \ - "0.3877532000, 0.4000050000, 0.4246726000, 0.4793793000, 0.5930212000, 0.8400822000, 1.3896378000", \ - "0.5328565000, 0.5489976000, 0.5797829000, 0.6458979000, 0.7802328000, 1.0533104000, 1.6110900000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0182040000, 0.0199483000, 0.0238064000, 0.0320937000, 0.0495666000, 0.0867199000, 0.1658401000", \ - "0.0186333000, 0.0201621000, 0.0236441000, 0.0316034000, 0.0492148000, 0.0861039000, 0.1651121000", \ - "0.0245480000, 0.0255077000, 0.0279948000, 0.0343272000, 0.0496870000, 0.0855214000, 0.1650973000", \ - "0.0385216000, 0.0400451000, 0.0431988000, 0.0495000000, 0.0613917000, 0.0903246000, 0.1645469000", \ - "0.0631187000, 0.0652830000, 0.0697092000, 0.0788308000, 0.0956127000, 0.1242121000, 0.1829912000", \ - "0.1047386000, 0.1079451000, 0.1150845000, 0.1290019000, 0.1540257000, 0.1964730000, 0.2669154000", \ - "0.1787154000, 0.1842280000, 0.1957056000, 0.2174704000, 0.2566652000, 0.3201756000, 0.4228498000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1377540000, 0.1511649000, 0.1801583000, 0.2454214000, 0.3921349000, 0.7213515000, 1.4663045000", \ - "0.1377585000, 0.1511589000, 0.1802224000, 0.2454536000, 0.3922334000, 0.7210312000, 1.4586964000", \ - "0.1383394000, 0.1507140000, 0.1799706000, 0.2460100000, 0.3929798000, 0.7224180000, 1.4637810000", \ - "0.1379630000, 0.1509495000, 0.1802046000, 0.2454580000, 0.3920489000, 0.7218117000, 1.4621455000", \ - "0.1398204000, 0.1527884000, 0.1812334000, 0.2456763000, 0.3927944000, 0.7253197000, 1.4576160000", \ - "0.1628577000, 0.1754280000, 0.2034959000, 0.2652080000, 0.4030000000, 0.7252889000, 1.4585184000", \ - "0.2149677000, 0.2288669000, 0.2576873000, 0.3230915000, 0.4660621000, 0.7710041000, 1.4758222000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0205020000, 0.0218853000, 0.0249181000, 0.0313845000, 0.0449763000, 0.0734497000, 0.1342683000", \ - "0.0259000000, 0.0272146000, 0.0301221000, 0.0364345000, 0.0497432000, 0.0781231000, 0.1389796000", \ - "0.0379640000, 0.0394073000, 0.0424105000, 0.0484528000, 0.0613532000, 0.0891981000, 0.1499283000", \ - "0.0557492000, 0.0578314000, 0.0622166000, 0.0710625000, 0.0872769000, 0.1156249000, 0.1755679000", \ - "0.0769549000, 0.0800970000, 0.0867486000, 0.1001722000, 0.1246736000, 0.1674124000, 0.2366232000", \ - "0.0940972000, 0.0988874000, 0.1089853000, 0.1286616000, 0.1679591000, 0.2343822000, 0.3413634000", \ - "0.0837898000, 0.0912886000, 0.1071710000, 0.1388587000, 0.1986557000, 0.3032246000, 0.4711492000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1856914000, 0.1956623000, 0.2188012000, 0.2682820000, 0.3786415000, 0.6242029000, 1.1805115000", \ - "0.1872077000, 0.1974765000, 0.2203062000, 0.2705217000, 0.3816650000, 0.6280952000, 1.1785686000", \ - "0.1961708000, 0.2070160000, 0.2291097000, 0.2801662000, 0.3910944000, 0.6383251000, 1.1900632000", \ - "0.2206270000, 0.2310880000, 0.2532929000, 0.3035385000, 0.4137592000, 0.6610622000, 1.2139987000", \ - "0.2724156000, 0.2828647000, 0.3055573000, 0.3553229000, 0.4658849000, 0.7142763000, 1.2637343000", \ - "0.3610418000, 0.3731640000, 0.4004991000, 0.4574758000, 0.5758299000, 0.8222859000, 1.3731029000", \ - "0.5063613000, 0.5229732000, 0.5596443000, 0.6372055000, 0.7840609000, 1.0646799000, 1.6258637000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0193990000, 0.0211193000, 0.0247596000, 0.0325912000, 0.0492847000, 0.0852555000, 0.1650886000", \ - "0.0191599000, 0.0207267000, 0.0241798000, 0.0319687000, 0.0488397000, 0.0849134000, 0.1647702000", \ - "0.0237732000, 0.0247912000, 0.0273543000, 0.0336639000, 0.0487530000, 0.0845155000, 0.1646243000", \ - "0.0367554000, 0.0383124000, 0.0415527000, 0.0475787000, 0.0594834000, 0.0889983000, 0.1642646000", \ - "0.0591660000, 0.0614879000, 0.0661688000, 0.0762613000, 0.0921304000, 0.1230434000, 0.1821868000", \ - "0.0991136000, 0.1023327000, 0.1096919000, 0.1243890000, 0.1503944000, 0.1933836000, 0.2670345000", \ - "0.1711792000, 0.1768957000, 0.1884156000, 0.2117673000, 0.2516994000, 0.3179647000, 0.4275300000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1377950000, 0.1511312000, 0.1801559000, 0.2454065000, 0.3920954000, 0.7216397000, 1.4705931000", \ - "0.1377130000, 0.1511071000, 0.1801956000, 0.2453330000, 0.3919896000, 0.7222701000, 1.4617636000", \ - "0.1382779000, 0.1513673000, 0.1798752000, 0.2459108000, 0.3930725000, 0.7216129000, 1.4591206000", \ - "0.1380029000, 0.1509413000, 0.1800626000, 0.2459331000, 0.3932014000, 0.7216006000, 1.4588118000", \ - "0.1439691000, 0.1565999000, 0.1836523000, 0.2483049000, 0.3936408000, 0.7231271000, 1.4612626000", \ - "0.1762492000, 0.1892497000, 0.2174323000, 0.2770474000, 0.4104662000, 0.7261110000, 1.4612552000", \ - "0.2529504000, 0.2657997000, 0.2944827000, 0.3596138000, 0.4964409000, 0.7882297000, 1.4812508000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0216120000, 0.0228902000, 0.0255837000, 0.0314185000, 0.0438818000, 0.0707258000, 0.1296757000", \ - "0.0265603000, 0.0277878000, 0.0304701000, 0.0362375000, 0.0485719000, 0.0753766000, 0.1344037000", \ - "0.0375941000, 0.0390060000, 0.0419489000, 0.0477379000, 0.0599892000, 0.0865145000, 0.1455928000", \ - "0.0527664000, 0.0548507000, 0.0593239000, 0.0683520000, 0.0847373000, 0.1129640000, 0.1712950000", \ - "0.0688405000, 0.0722905000, 0.0794599000, 0.0933890000, 0.1188772000, 0.1624653000, 0.2322647000", \ - "0.0772723000, 0.0825109000, 0.0936068000, 0.1146846000, 0.1560001000, 0.2248066000, 0.3342603000", \ - "0.0512867000, 0.0596190000, 0.0771141000, 0.1117583000, 0.1762825000, 0.2857898000, 0.4588651000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1514140000, 0.1617506000, 0.1841764000, 0.2351577000, 0.3455518000, 0.5911918000, 1.1415748000", \ - "0.1527708000, 0.1629572000, 0.1860523000, 0.2360069000, 0.3476505000, 0.5943790000, 1.1465996000", \ - "0.1615051000, 0.1717103000, 0.1944209000, 0.2442186000, 0.3556051000, 0.6029989000, 1.1555557000", \ - "0.1862479000, 0.1965148000, 0.2189169000, 0.2688501000, 0.3795274000, 0.6260668000, 1.1784441000", \ - "0.2402174000, 0.2508022000, 0.2735293000, 0.3233146000, 0.4343078000, 0.6803584000, 1.2319756000", \ - "0.3344003000, 0.3485386000, 0.3786665000, 0.4402838000, 0.5633601000, 0.8108374000, 1.3668833000", \ - "0.4856856000, 0.5065109000, 0.5517989000, 0.6402815000, 0.8063080000, 1.1029881000, 1.6666297000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0169181000, 0.0183546000, 0.0214442000, 0.0283262000, 0.0438264000, 0.0786185000, 0.1570244000", \ - "0.0165705000, 0.0179177000, 0.0210230000, 0.0280774000, 0.0436480000, 0.0784455000, 0.1570508000", \ - "0.0206743000, 0.0216923000, 0.0240572000, 0.0298291000, 0.0440414000, 0.0784080000, 0.1566564000", \ - "0.0326995000, 0.0340038000, 0.0370449000, 0.0435538000, 0.0553304000, 0.0834811000, 0.1569914000", \ - "0.0533300000, 0.0555703000, 0.0603298000, 0.0703329000, 0.0873846000, 0.1188899000, 0.1764350000", \ - "0.0912437000, 0.0951218000, 0.1030981000, 0.1182261000, 0.1442502000, 0.1886292000, 0.2621644000", \ - "0.1622568000, 0.1682467000, 0.1805942000, 0.2041181000, 0.2468874000, 0.3134864000, 0.4211128000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1374286000, 0.1511236000, 0.1796196000, 0.2451614000, 0.3931216000, 0.7215971000, 1.4639783000", \ - "0.1375069000, 0.1510421000, 0.1801442000, 0.2453879000, 0.3932103000, 0.7215713000, 1.4641449000", \ - "0.1374815000, 0.1511065000, 0.1801194000, 0.2452506000, 0.3919482000, 0.7221174000, 1.4591633000", \ - "0.1373100000, 0.1509710000, 0.1800423000, 0.2460734000, 0.3930876000, 0.7218736000, 1.4611710000", \ - "0.1471619000, 0.1598649000, 0.1868355000, 0.2491729000, 0.3929941000, 0.7212250000, 1.4603294000", \ - "0.1911271000, 0.2042599000, 0.2322105000, 0.2898376000, 0.4188097000, 0.7279390000, 1.4661065000", \ - "0.2869661000, 0.3017702000, 0.3329722000, 0.4009302000, 0.5366951000, 0.8121874000, 1.4830173000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0169959000, 0.0181058000, 0.0205276000, 0.0257937000, 0.0373433000, 0.0630078000, 0.1203365000", \ - "0.0217372000, 0.0228528000, 0.0253060000, 0.0305594000, 0.0422276000, 0.0679012000, 0.1252925000", \ - "0.0300306000, 0.0317050000, 0.0351282000, 0.0416667000, 0.0535804000, 0.0793001000, 0.1364757000", \ - "0.0396244000, 0.0422153000, 0.0479001000, 0.0582509000, 0.0761745000, 0.1057016000, 0.1630036000", \ - "0.0472996000, 0.0515440000, 0.0601235000, 0.0766317000, 0.1053158000, 0.1516068000, 0.2235958000", \ - "0.0407721000, 0.0475951000, 0.0616035000, 0.0880176000, 0.1330436000, 0.2076655000, 0.3200743000", \ - "-0.009724200, 0.0008977000, 0.0228811000, 0.0659229000, 0.1400355000, 0.2590225000, 0.4370896000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0804117000, 0.0904259000, 0.1132455000, 0.1638580000, 0.2760722000, 0.5216027000, 1.0728735000", \ - "0.0806463000, 0.0904732000, 0.1138423000, 0.1641829000, 0.2763835000, 0.5238729000, 1.0759535000", \ - "0.0898037000, 0.0991102000, 0.1208590000, 0.1705456000, 0.2838461000, 0.5314615000, 1.0838892000", \ - "0.1169143000, 0.1252247000, 0.1453078000, 0.1934513000, 0.3040330000, 0.5540701000, 1.1056482000", \ - "0.1792698000, 0.1890038000, 0.2110261000, 0.2552701000, 0.3620110000, 0.6088967000, 1.1719743000", \ - "0.2767812000, 0.2923296000, 0.3247462000, 0.3883180000, 0.5075718000, 0.7424387000, 1.2969893000", \ - "0.4403280000, 0.4620364000, 0.5073551000, 0.5990093000, 0.7709046000, 1.0725857000, 1.6123999000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.0109336000, 0.0122294000, 0.0152554000, 0.0220382000, 0.0373313000, 0.0716860000, 0.1493370000", \ - "0.0115174000, 0.0127082000, 0.0154696000, 0.0220214000, 0.0370662000, 0.0710881000, 0.1476030000", \ - "0.0174120000, 0.0186324000, 0.0208857000, 0.0256597000, 0.0387168000, 0.0711522000, 0.1477194000", \ - "0.0286262000, 0.0307237000, 0.0335920000, 0.0401526000, 0.0532302000, 0.0784603000, 0.1496304000", \ - "0.0492103000, 0.0510806000, 0.0563373000, 0.0664338000, 0.0850067000, 0.1146736000, 0.1697201000", \ - "0.0865155000, 0.0905923000, 0.0995723000, 0.1156436000, 0.1414324000, 0.1860490000, 0.2580700000", \ - "0.1581574000, 0.1660289000, 0.1798481000, 0.2021549000, 0.2429249000, 0.3107040000, 0.4144504000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011227500, 0.0025211100, 0.0056611300, 0.0127120000, 0.0285447000, 0.0640969000"); - values("0.1280252000, 0.1418451000, 0.1737747000, 0.2431621000, 0.3923805000, 0.7227355000, 1.4632247000", \ - "0.1259774000, 0.1401429000, 0.1724934000, 0.2422378000, 0.3923987000, 0.7216677000, 1.4588630000", \ - "0.1227664000, 0.1376401000, 0.1696940000, 0.2406568000, 0.3926013000, 0.7211817000, 1.4614154000", \ - "0.1219119000, 0.1349427000, 0.1654521000, 0.2359255000, 0.3902280000, 0.7221867000, 1.4617676000", \ - "0.1454235000, 0.1568292000, 0.1827375000, 0.2423129000, 0.3876195000, 0.7203104000, 1.4687728000", \ - "0.1874968000, 0.2026039000, 0.2343778000, 0.3018862000, 0.4231266000, 0.7254627000, 1.4648500000", \ - "0.2683465000, 0.2865665000, 0.3270896000, 0.4068787000, 0.5633975000, 0.8439540000, 1.4876161000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4_4") { - leakage_power () { - value : 0.0041413000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0089600000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0002945000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0026775000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0002967000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0025928000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0001617000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0003091000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0002871000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0024317000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0001565000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0002989000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0001561000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0003195000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0169857000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0001781000; - when : "A&B&C&!D"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__nor4"; - cell_leakage_power : 0.0025154460; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081520000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0139736000, 0.0139653000, 0.0139464000, 0.0139425000, 0.0139336000, 0.0139130000, 0.0138654000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013126100, -0.013268400, -0.013596500, -0.013663900, -0.013819400, -0.014177600, -0.015003400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091060000; - } - pin ("B") { - capacitance : 0.0085660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0205394000, 0.0205346000, 0.0205236000, 0.0205256000, 0.0205301000, 0.0205404000, 0.0205641000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013206000, -0.013288200, -0.013477800, -0.013550800, -0.013719100, -0.014107000, -0.015001200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091700000; - } - pin ("C") { - capacitance : 0.0083640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0165717000, 0.0165649000, 0.0165492000, 0.0165512000, 0.0165559000, 0.0165667000, 0.0165917000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013817000, -0.014080300, -0.014687200, -0.014716200, -0.014782900, -0.014936700, -0.015291100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090310000; - } - pin ("D") { - capacitance : 0.0085430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0071704000, 0.0071577000, 0.0071283000, 0.0071537000, 0.0072123000, 0.0073472000, 0.0076583000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006809800, -0.006818000, -0.006836900, -0.006834000, -0.006827200, -0.006811600, -0.006775700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092980000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&!D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0258536000, 0.0246675000, 0.0217951000, 0.0145956000, -0.003172300, -0.046845800, -0.154350300", \ - "0.0255606000, 0.0243752000, 0.0214335000, 0.0142787000, -0.003480400, -0.047186700, -0.154671200", \ - "0.0253191000, 0.0241583000, 0.0213516000, 0.0140476000, -0.003739200, -0.047392000, -0.154894000", \ - "0.0246075000, 0.0234827000, 0.0206176000, 0.0135902000, -0.004173900, -0.047836700, -0.155355600", \ - "0.0242454000, 0.0230725000, 0.0201942000, 0.0130485000, -0.004343300, -0.048061600, -0.155483400", \ - "0.0258922000, 0.0246844000, 0.0217390000, 0.0144945000, -0.003275400, -0.047504900, -0.154733300", \ - "0.0316230000, 0.0303862000, 0.0273510000, 0.0200466000, 0.0021243000, -0.042851700, -0.152236800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0568994000, 0.0581136000, 0.0610980000, 0.0683895000, 0.0861611000, 0.1297799000, 0.2364492000", \ - "0.0561970000, 0.0574093000, 0.0604668000, 0.0677914000, 0.0856868000, 0.1295917000, 0.2364734000", \ - "0.0556635000, 0.0567906000, 0.0598544000, 0.0672150000, 0.0851368000, 0.1289659000, 0.2369291000", \ - "0.0552329000, 0.0564561000, 0.0593433000, 0.0666809000, 0.0846081000, 0.1287856000, 0.2359779000", \ - "0.0548319000, 0.0560244000, 0.0589427000, 0.0662090000, 0.0839013000, 0.1276851000, 0.2353038000", \ - "0.0546776000, 0.0558880000, 0.0587411000, 0.0659636000, 0.0836877000, 0.1276639000, 0.2347430000", \ - "0.0547155000, 0.0559366000, 0.0588459000, 0.0660513000, 0.0841257000, 0.1271616000, 0.2347138000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0201957000, 0.0190150000, 0.0161015000, 0.0088895000, -0.008836400, -0.052396900, -0.160228400", \ - "0.0201400000, 0.0189480000, 0.0160408000, 0.0088509000, -0.008871200, -0.052406800, -0.160160000", \ - "0.0200465000, 0.0188703000, 0.0159483000, 0.0087606000, -0.008963600, -0.052492400, -0.160263600", \ - "0.0193000000, 0.0181201000, 0.0153573000, 0.0082912000, -0.009390900, -0.052747400, -0.160502300", \ - "0.0188840000, 0.0177187000, 0.0148436000, 0.0076942000, -0.009857300, -0.052986900, -0.160555000", \ - "0.0208977000, 0.0196907000, 0.0168061000, 0.0097550000, -0.008386900, -0.051843500, -0.160062000", \ - "0.0257932000, 0.0244995000, 0.0214592000, 0.0141110000, -0.004139400, -0.048523000, -0.157560600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0418712000, 0.0431004000, 0.0461302000, 0.0534739000, 0.0712791000, 0.1149089000, 0.2221098000", \ - "0.0410878000, 0.0423052000, 0.0453518000, 0.0529086000, 0.0710503000, 0.1150721000, 0.2219309000", \ - "0.0403595000, 0.0416194000, 0.0445829000, 0.0519048000, 0.0700102000, 0.1140205000, 0.2217857000", \ - "0.0398668000, 0.0411129000, 0.0440833000, 0.0513871000, 0.0692065000, 0.1132726000, 0.2210306000", \ - "0.0394266000, 0.0406540000, 0.0435935000, 0.0507979000, 0.0688461000, 0.1123686000, 0.2201341000", \ - "0.0393214000, 0.0405284000, 0.0435511000, 0.0506692000, 0.0683765000, 0.1122321000, 0.2195484000", \ - "0.0394760000, 0.0406609000, 0.0435315000, 0.0508074000, 0.0687894000, 0.1121211000, 0.2193161000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0151695000, 0.0139835000, 0.0110700000, 0.0038854000, -0.013791000, -0.057472300, -0.165693800", \ - "0.0153108000, 0.0141387000, 0.0112399000, 0.0040888000, -0.013503500, -0.057156000, -0.165345600", \ - "0.0156310000, 0.0144686000, 0.0116086000, 0.0045541000, -0.012963000, -0.056504200, -0.164545000", \ - "0.0150195000, 0.0139297000, 0.0111226000, 0.0041533000, -0.013153700, -0.056518100, -0.164483300", \ - "0.0153607000, 0.0142155000, 0.0113771000, 0.0042743000, -0.013485400, -0.056781400, -0.164544000", \ - "0.0164597000, 0.0152759000, 0.0123571000, 0.0053862000, -0.012897800, -0.055857900, -0.164305900", \ - "0.0204215000, 0.0191836000, 0.0160917000, 0.0085952000, -0.009594900, -0.053851300, -0.162710700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0364060000, 0.0376655000, 0.0407342000, 0.0481260000, 0.0660603000, 0.1097205000, 0.2168759000", \ - "0.0355367000, 0.0367814000, 0.0398679000, 0.0473158000, 0.0654474000, 0.1093261000, 0.2167118000", \ - "0.0348295000, 0.0360504000, 0.0391555000, 0.0464541000, 0.0645920000, 0.1086825000, 0.2164088000", \ - "0.0344173000, 0.0356609000, 0.0385694000, 0.0458242000, 0.0637399000, 0.1079265000, 0.2158656000", \ - "0.0339125000, 0.0351212000, 0.0381331000, 0.0453186000, 0.0633486000, 0.1069773000, 0.2148989000", \ - "0.0339676000, 0.0350744000, 0.0380269000, 0.0452673000, 0.0630572000, 0.1067641000, 0.2148413000", \ - "0.0352447000, 0.0363975000, 0.0392781000, 0.0462103000, 0.0639357000, 0.1068490000, 0.2147592000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0020474000, 0.0008672000, -0.002068500, -0.009367400, -0.027435800, -0.071628900, -0.180092500", \ - "0.0015703000, 0.0004395000, -0.002438400, -0.009592900, -0.027414900, -0.071374100, -0.179722000", \ - "0.0007928000, -0.000329300, -0.003133800, -0.010131100, -0.027610300, -0.071204900, -0.179324100", \ - "-0.000324800, -0.001421200, -0.004120600, -0.010896900, -0.028061800, -0.071341400, -0.179173800", \ - "-0.000270800, -0.001399500, -0.004199400, -0.010879400, -0.028057000, -0.071574700, -0.179231400", \ - "0.0009318000, -0.000168100, -0.002994400, -0.010832800, -0.028448600, -0.071758400, -0.179181100", \ - "0.0063932000, 0.0039648000, 0.0008123000, -0.007008900, -0.025627700, -0.069590000, -0.177931800"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012333250, 0.0030421800, 0.0075039940, 0.0185097200, 0.0456570000, 0.1126198000"); - values("0.0363275000, 0.0376833000, 0.0408159000, 0.0484411000, 0.0665670000, 0.1104309000, 0.2181026000", \ - "0.0353127000, 0.0365789000, 0.0397452000, 0.0473135000, 0.0658773000, 0.1098842000, 0.2176014000", \ - "0.0345309000, 0.0357975000, 0.0388462000, 0.0464790000, 0.0647453000, 0.1090096000, 0.2180210000", \ - "0.0343549000, 0.0355494000, 0.0385228000, 0.0458748000, 0.0638758000, 0.1081298000, 0.2158983000", \ - "0.0345560000, 0.0356289000, 0.0384902000, 0.0459951000, 0.0633223000, 0.1071781000, 0.2150072000", \ - "0.0373415000, 0.0385124000, 0.0413760000, 0.0476575000, 0.0650933000, 0.1077903000, 0.2150446000", \ - "0.0409639000, 0.0420970000, 0.0448032000, 0.0514045000, 0.0683057000, 0.1103649000, 0.2158137000"); - } - } - max_capacitance : 0.1126200000; - max_transition : 1.4888180000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0193964000, 0.0202370000, 0.0223514000, 0.0274228000, 0.0392381000, 0.0667027000, 0.1301931000", \ - "0.0247133000, 0.0255499000, 0.0275593000, 0.0324276000, 0.0440852000, 0.0712996000, 0.1345911000", \ - "0.0364115000, 0.0374181000, 0.0397948000, 0.0446742000, 0.0556589000, 0.0823060000, 0.1451904000", \ - "0.0534250000, 0.0548221000, 0.0582012000, 0.0655158000, 0.0805144000, 0.1087747000, 0.1707596000", \ - "0.0747592000, 0.0767650000, 0.0814943000, 0.0923522000, 0.1146586000, 0.1563677000, 0.2298305000", \ - "0.0935944000, 0.0965953000, 0.1036819000, 0.1196564000, 0.1530284000, 0.2158915000, 0.3271649000", \ - "0.0828202000, 0.0873171000, 0.0979523000, 0.1220692000, 0.1718244000, 0.2709675000, 0.4434555000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.2157051000, 0.2223377000, 0.2387324000, 0.2797581000, 0.3770114000, 0.6151051000, 1.2015151000", \ - "0.2181038000, 0.2248109000, 0.2418281000, 0.2828819000, 0.3817732000, 0.6210371000, 1.2076589000", \ - "0.2290101000, 0.2355684000, 0.2524831000, 0.2931838000, 0.3916164000, 0.6350207000, 1.2220954000", \ - "0.2549880000, 0.2620093000, 0.2788463000, 0.3189234000, 0.4177814000, 0.6575551000, 1.2473347000", \ - "0.3099524000, 0.3166008000, 0.3324913000, 0.3727015000, 0.4708845000, 0.7103442000, 1.2991488000", \ - "0.4066977000, 0.4137463000, 0.4321690000, 0.4768357000, 0.5783118000, 0.8183057000, 1.4111032000", \ - "0.5637575000, 0.5730733000, 0.5953374000, 0.6484591000, 0.7682323000, 1.0355933000, 1.6304902000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0204699000, 0.0216928000, 0.0247275000, 0.0318782000, 0.0488783000, 0.0879051000, 0.1778832000", \ - "0.0206207000, 0.0218017000, 0.0245538000, 0.0314307000, 0.0483457000, 0.0873167000, 0.1779467000", \ - "0.0262347000, 0.0271475000, 0.0294873000, 0.0348189000, 0.0492424000, 0.0864460000, 0.1775064000", \ - "0.0398617000, 0.0409330000, 0.0434214000, 0.0496515000, 0.0617239000, 0.0925948000, 0.1772074000", \ - "0.0640157000, 0.0655679000, 0.0691402000, 0.0767606000, 0.0932471000, 0.1252015000, 0.1965112000", \ - "0.1058031000, 0.1081279000, 0.1135441000, 0.1241585000, 0.1468419000, 0.1911147000, 0.2757500000", \ - "0.1784763000, 0.1819669000, 0.1903398000, 0.2086242000, 0.2441687000, 0.3096373000, 0.4254224000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.1471014000, 0.1557794000, 0.1760432000, 0.2293268000, 0.3595388000, 0.6792555000, 1.4712923000", \ - "0.1472028000, 0.1559224000, 0.1772182000, 0.2293676000, 0.3595126000, 0.6793623000, 1.4629895000", \ - "0.1468696000, 0.1560581000, 0.1766923000, 0.2296580000, 0.3590153000, 0.6801698000, 1.4687057000", \ - "0.1470615000, 0.1556080000, 0.1775881000, 0.2297089000, 0.3600041000, 0.6793510000, 1.4642157000", \ - "0.1483388000, 0.1569298000, 0.1777967000, 0.2301762000, 0.3592500000, 0.6785599000, 1.4652298000", \ - "0.1703348000, 0.1787398000, 0.1990188000, 0.2486714000, 0.3701452000, 0.6820695000, 1.4680837000", \ - "0.2190299000, 0.2276419000, 0.2478266000, 0.3005848000, 0.4281617000, 0.7278557000, 1.4819532000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0212197000, 0.0221721000, 0.0243960000, 0.0296707000, 0.0417172000, 0.0692400000, 0.1328612000", \ - "0.0264733000, 0.0273474000, 0.0295051000, 0.0346107000, 0.0465360000, 0.0738662000, 0.1373183000", \ - "0.0382906000, 0.0392549000, 0.0414879000, 0.0464551000, 0.0577554000, 0.0846028000, 0.1480137000", \ - "0.0548283000, 0.0562301000, 0.0594764000, 0.0668769000, 0.0819777000, 0.1101630000, 0.1725815000", \ - "0.0731851000, 0.0752699000, 0.0801991000, 0.0913982000, 0.1135221000, 0.1565475000, 0.2312242000", \ - "0.0831566000, 0.0862820000, 0.0936078000, 0.1096746000, 0.1454118000, 0.2107256000, 0.3255069000", \ - "0.0561493000, 0.0606212000, 0.0720514000, 0.0979217000, 0.1522031000, 0.2552490000, 0.4348051000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.2007191000, 0.2074685000, 0.2240368000, 0.2654947000, 0.3633754000, 0.6015873000, 1.1882382000", \ - "0.2014680000, 0.2085743000, 0.2251251000, 0.2667724000, 0.3665485000, 0.6078115000, 1.1919701000", \ - "0.2105524000, 0.2171880000, 0.2339913000, 0.2746164000, 0.3737511000, 0.6145652000, 1.2082482000", \ - "0.2352427000, 0.2421349000, 0.2587085000, 0.2992333000, 0.3981374000, 0.6383643000, 1.2278650000", \ - "0.2887728000, 0.2957519000, 0.3124322000, 0.3527074000, 0.4514963000, 0.6907956000, 1.2801494000", \ - "0.3835336000, 0.3915073000, 0.4112180000, 0.4583033000, 0.5644271000, 0.8048086000, 1.3932882000", \ - "0.5409192000, 0.5520773000, 0.5788349000, 0.6419716000, 0.7730525000, 1.0507950000, 1.6502183000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0214002000, 0.0225405000, 0.0252722000, 0.0319387000, 0.0473617000, 0.0835541000, 0.1716677000", \ - "0.0209750000, 0.0220265000, 0.0246250000, 0.0311299000, 0.0467703000, 0.0832944000, 0.1714104000", \ - "0.0254215000, 0.0262074000, 0.0280637000, 0.0333234000, 0.0471840000, 0.0826224000, 0.1712895000", \ - "0.0376065000, 0.0386838000, 0.0414738000, 0.0469998000, 0.0589988000, 0.0884555000, 0.1708772000", \ - "0.0599613000, 0.0612903000, 0.0660632000, 0.0728643000, 0.0891194000, 0.1211973000, 0.1908433000", \ - "0.0994359000, 0.1015590000, 0.1070380000, 0.1190263000, 0.1431604000, 0.1888305000, 0.2715039000", \ - "0.1703333000, 0.1750433000, 0.1835578000, 0.2020261000, 0.2391993000, 0.3061655000, 0.4259288000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.1470063000, 0.1557003000, 0.1760016000, 0.2292738000, 0.3594780000, 0.6787073000, 1.4625005000", \ - "0.1466805000, 0.1557131000, 0.1771308000, 0.2299596000, 0.3600965000, 0.6822220000, 1.4648662000", \ - "0.1468064000, 0.1554268000, 0.1765428000, 0.2294096000, 0.3590177000, 0.6782149000, 1.4682039000", \ - "0.1470143000, 0.1556046000, 0.1768987000, 0.2297196000, 0.3594739000, 0.6786770000, 1.4640581000", \ - "0.1514297000, 0.1594034000, 0.1798394000, 0.2311494000, 0.3600773000, 0.6783745000, 1.4641387000", \ - "0.1835499000, 0.1921497000, 0.2125530000, 0.2597398000, 0.3777193000, 0.6835392000, 1.4641912000", \ - "0.2568987000, 0.2657791000, 0.2866783000, 0.3385827000, 0.4605740000, 0.7464262000, 1.4870626000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0216729000, 0.0225063000, 0.0244658000, 0.0291382000, 0.0399077000, 0.0651272000, 0.1256967000", \ - "0.0264791000, 0.0272791000, 0.0292420000, 0.0338567000, 0.0445712000, 0.0697247000, 0.1303019000", \ - "0.0370599000, 0.0380074000, 0.0402478000, 0.0450609000, 0.0555991000, 0.0805266000, 0.1411087000", \ - "0.0510705000, 0.0525640000, 0.0559145000, 0.0632026000, 0.0780945000, 0.1061548000, 0.1660976000", \ - "0.0642806000, 0.0664421000, 0.0715440000, 0.0830597000, 0.1063718000, 0.1498335000, 0.2243730000", \ - "0.0649452000, 0.0683427000, 0.0761926000, 0.0930474000, 0.1311225000, 0.1987648000, 0.3155671000", \ - "0.0214212000, 0.0267248000, 0.0394508000, 0.0673107000, 0.1257935000, 0.2345920000, 0.4183102000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.1606854000, 0.1674417000, 0.1841279000, 0.2257041000, 0.3243719000, 0.5628746000, 1.1496002000", \ - "0.1607507000, 0.1674475000, 0.1845295000, 0.2258134000, 0.3251469000, 0.5655953000, 1.1537217000", \ - "0.1687135000, 0.1753466000, 0.1925603000, 0.2332726000, 0.3324687000, 0.5739989000, 1.1632834000", \ - "0.1935081000, 0.2002329000, 0.2164628000, 0.2573327000, 0.3571456000, 0.5963337000, 1.1863973000", \ - "0.2484653000, 0.2554921000, 0.2722799000, 0.3128889000, 0.4118929000, 0.6506989000, 1.2401521000", \ - "0.3469006000, 0.3561340000, 0.3779904000, 0.4289335000, 0.5402631000, 0.7832817000, 1.3783603000", \ - "0.5134955000, 0.5273993000, 0.5592642000, 0.6312767000, 0.7802052000, 1.0730298000, 1.6782256000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0174449000, 0.0183922000, 0.0206117000, 0.0261409000, 0.0395629000, 0.0728496000, 0.1556640000", \ - "0.0171149000, 0.0179869000, 0.0201753000, 0.0257964000, 0.0393944000, 0.0728523000, 0.1557998000", \ - "0.0212648000, 0.0219881000, 0.0236047000, 0.0281575000, 0.0402865000, 0.0726890000, 0.1554258000", \ - "0.0326310000, 0.0335113000, 0.0358816000, 0.0413183000, 0.0531065000, 0.0796627000, 0.1560818000", \ - "0.0530578000, 0.0546040000, 0.0582501000, 0.0666165000, 0.0826685000, 0.1148760000, 0.1777592000", \ - "0.0906204000, 0.0931699000, 0.0990344000, 0.1117756000, 0.1360147000, 0.1820826000, 0.2615011000", \ - "0.1603888000, 0.1643540000, 0.1733663000, 0.1927346000, 0.2323397000, 0.3002042000, 0.4172471000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.1468896000, 0.1555396000, 0.1759198000, 0.2292294000, 0.3595376000, 0.6786939000, 1.4673825000", \ - "0.1468821000, 0.1553313000, 0.1770245000, 0.2288603000, 0.3589142000, 0.6778590000, 1.4659506000", \ - "0.1468382000, 0.1553025000, 0.1766459000, 0.2292690000, 0.3585940000, 0.6778250000, 1.4624771000", \ - "0.1463126000, 0.1549603000, 0.1768179000, 0.2292344000, 0.3595745000, 0.6794166000, 1.4629861000", \ - "0.1560615000, 0.1643192000, 0.1839754000, 0.2333342000, 0.3606122000, 0.6779409000, 1.4631959000", \ - "0.1979907000, 0.2062877000, 0.2276539000, 0.2752711000, 0.3864913000, 0.6871141000, 1.4698061000", \ - "0.2918360000, 0.3011892000, 0.3235449000, 0.3778484000, 0.4986511000, 0.7686763000, 1.4848925000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0164159000, 0.0171596000, 0.0188569000, 0.0229135000, 0.0326080000, 0.0558092000, 0.1123402000", \ - "0.0210773000, 0.0218084000, 0.0235560000, 0.0276065000, 0.0373197000, 0.0605084000, 0.1175268000", \ - "0.0289974000, 0.0301058000, 0.0326460000, 0.0380456000, 0.0485006000, 0.0715594000, 0.1284588000", \ - "0.0376951000, 0.0394226000, 0.0433678000, 0.0518780000, 0.0684435000, 0.0974589000, 0.1543048000", \ - "0.0429256000, 0.0455104000, 0.0518244000, 0.0651084000, 0.0913644000, 0.1371303000, 0.2129550000", \ - "0.0308211000, 0.0351600000, 0.0450799000, 0.0670899000, 0.1089847000, 0.1824462000, 0.2995009000", \ - "-0.032950500, -0.026249000, -0.010231100, 0.0249926000, 0.0926665000, 0.2101262000, 0.3988873000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0869582000, 0.0936298000, 0.1108970000, 0.1522951000, 0.2524986000, 0.4921450000, 1.0837348000", \ - "0.0866143000, 0.0933467000, 0.1099740000, 0.1510310000, 0.2525602000, 0.4943553000, 1.0828911000", \ - "0.0948040000, 0.1011967000, 0.1173059000, 0.1579510000, 0.2576952000, 0.5004837000, 1.0980566000", \ - "0.1227608000, 0.1282550000, 0.1427657000, 0.1813988000, 0.2794211000, 0.5239660000, 1.1120217000", \ - "0.1881298000, 0.1950101000, 0.2102194000, 0.2459316000, 0.3373394000, 0.5763717000, 1.1675954000", \ - "0.2933446000, 0.3034437000, 0.3272358000, 0.3789323000, 0.4876655000, 0.7161398000, 1.3117915000", \ - "0.4714776000, 0.4862213000, 0.5195100000, 0.5942608000, 0.7505704000, 1.0471086000, 1.6296657000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.0107609000, 0.0115777000, 0.0136564000, 0.0187260000, 0.0311013000, 0.0620105000, 0.1391110000", \ - "0.0113974000, 0.0120853000, 0.0139551000, 0.0187453000, 0.0311910000, 0.0624330000, 0.1380273000", \ - "0.0172111000, 0.0179458000, 0.0196500000, 0.0232600000, 0.0333000000, 0.0625213000, 0.1393195000", \ - "0.0283588000, 0.0294997000, 0.0316299000, 0.0370721000, 0.0484861000, 0.0709437000, 0.1396297000", \ - "0.0483265000, 0.0495506000, 0.0531997000, 0.0615611000, 0.0779724000, 0.1077036000, 0.1633238000", \ - "0.0854376000, 0.0881445000, 0.0941730000, 0.1070071000, 0.1321546000, 0.1740435000, 0.2517621000", \ - "0.1572322000, 0.1608975000, 0.1717755000, 0.1919131000, 0.2270973000, 0.2934396000, 0.4047209000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012333200, 0.0030421800, 0.0075039900, 0.0185097000, 0.0456570000, 0.1126200000"); - values("0.1369178000, 0.1460602000, 0.1696259000, 0.2252919000, 0.3581626000, 0.6784678000, 1.4686953000", \ - "0.1345313000, 0.1443000000, 0.1675846000, 0.2243238000, 0.3587755000, 0.6783206000, 1.4641419000", \ - "0.1310881000, 0.1409326000, 0.1644384000, 0.2220676000, 0.3578731000, 0.6782066000, 1.4767428000", \ - "0.1289892000, 0.1380813000, 0.1609174000, 0.2169620000, 0.3562587000, 0.6807450000, 1.4711325000", \ - "0.1516510000, 0.1586596000, 0.1781801000, 0.2257350000, 0.3515012000, 0.6788178000, 1.4637934000", \ - "0.1933094000, 0.2037902000, 0.2275826000, 0.2841264000, 0.3920864000, 0.6827688000, 1.4695545000", \ - "0.2750249000, 0.2872869000, 0.3156812000, 0.3820756000, 0.5217672000, 0.8019726000, 1.4888180000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4b_1") { - leakage_power () { - value : 0.0024302000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0015074000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0012771000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0004415000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0012813000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0004447000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0008103000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0004150000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0016839000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0004891000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0008486000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0004229000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0008541000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0004246000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0007921000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0004092000; - when : "A&B&C&!D_N"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__nor4b"; - cell_leakage_power : 0.0009082530; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039721000, 0.0039702000, 0.0039658000, 0.0039667000, 0.0039688000, 0.0039737000, 0.0039851000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003371000, -0.003404800, -0.003482800, -0.003496800, -0.003529000, -0.003603200, -0.003774200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024990000; - } - pin ("B") { - capacitance : 0.0023770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038993000, 0.0038983000, 0.0038960000, 0.0038953000, 0.0038936000, 0.0038896000, 0.0038806000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003324500, -0.003348700, -0.003404400, -0.003421400, -0.003460500, -0.003550800, -0.003758900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025200000; - } - pin ("C") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043366000, 0.0043355000, 0.0043329000, 0.0043310000, 0.0043266000, 0.0043163000, 0.0042928000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004070300, -0.004125900, -0.004253900, -0.004258000, -0.004267600, -0.004289800, -0.004340800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - } - pin ("D_N") { - capacitance : 0.0014580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086550000, 0.0085641000, 0.0083546000, 0.0084020000, 0.0085111000, 0.0087628000, 0.0093429000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026292000, 0.0025761000, 0.0024538000, 0.0024937000, 0.0025857000, 0.0027978000, 0.0032865000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015170000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0066619000, 0.0058464000, 0.0041968000, 0.0008442000, -0.005912100, -0.019502000, -0.046959600", \ - "0.0065843000, 0.0057590000, 0.0040993000, 0.0007614000, -0.006006400, -0.019588700, -0.047039400", \ - "0.0065370000, 0.0056933000, 0.0040536000, 0.0007174000, -0.006060200, -0.019640800, -0.047086700", \ - "0.0063880000, 0.0055633000, 0.0039323000, 0.0005812000, -0.006166200, -0.019720800, -0.047211800", \ - "0.0063741000, 0.0055452000, 0.0038789000, 0.0005555000, -0.006154100, -0.019683900, -0.047208300", \ - "0.0070636000, 0.0062307000, 0.0045424000, 0.0011586000, -0.005678500, -0.019304800, -0.046932800", \ - "0.0085904000, 0.0077375000, 0.0060428000, 0.0026570000, -0.004250000, -0.018202800, -0.046200100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0139558000, 0.0147981000, 0.0164643000, 0.0198381000, 0.0265990000, 0.0401932000, 0.0675465000", \ - "0.0137748000, 0.0146306000, 0.0163036000, 0.0197600000, 0.0266204000, 0.0401276000, 0.0675392000", \ - "0.0136338000, 0.0144440000, 0.0161904000, 0.0195343000, 0.0263557000, 0.0399694000, 0.0676070000", \ - "0.0135035000, 0.0143353000, 0.0160788000, 0.0194217000, 0.0261817000, 0.0397891000, 0.0674402000", \ - "0.0134215000, 0.0142293000, 0.0159189000, 0.0192551000, 0.0260343000, 0.0396993000, 0.0672647000", \ - "0.0134052000, 0.0142336000, 0.0158733000, 0.0192038000, 0.0259641000, 0.0395592000, 0.0669660000", \ - "0.0132146000, 0.0142102000, 0.0158637000, 0.0192731000, 0.0260502000, 0.0394460000, 0.0669871000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0055998000, 0.0047761000, 0.0031072000, -0.000220400, -0.006940100, -0.020546500, -0.048107200", \ - "0.0055921000, 0.0047665000, 0.0031063000, -0.000234100, -0.006956400, -0.020553300, -0.048141500", \ - "0.0055444000, 0.0047457000, 0.0030967000, -0.000253300, -0.006981000, -0.020552700, -0.048144200", \ - "0.0053699000, 0.0045597000, 0.0029610000, -0.000379200, -0.007068900, -0.020628000, -0.048207400", \ - "0.0054888000, 0.0046671000, 0.0030157000, -0.000381700, -0.007148200, -0.020662700, -0.048216300", \ - "0.0059208000, 0.0051186000, 0.0034833000, -5.78000e-05, -0.006811900, -0.020316000, -0.048060500", \ - "0.0070257000, 0.0061921000, 0.0044323000, 0.0010428000, -0.005799300, -0.019549600, -0.047360400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0119572000, 0.0127774000, 0.0145189000, 0.0178593000, 0.0246272000, 0.0382280000, 0.0655879000", \ - "0.0117513000, 0.0125798000, 0.0143533000, 0.0177035000, 0.0245245000, 0.0380898000, 0.0656605000", \ - "0.0115740000, 0.0123960000, 0.0141585000, 0.0175373000, 0.0243440000, 0.0379729000, 0.0656679000", \ - "0.0114398000, 0.0123013000, 0.0140211000, 0.0173299000, 0.0241415000, 0.0377847000, 0.0652561000", \ - "0.0113838000, 0.0122056000, 0.0138874000, 0.0172733000, 0.0240663000, 0.0376157000, 0.0652372000", \ - "0.0113469000, 0.0121800000, 0.0138474000, 0.0171477000, 0.0239413000, 0.0375880000, 0.0649536000", \ - "0.0113870000, 0.0122174000, 0.0138476000, 0.0172284000, 0.0240564000, 0.0375880000, 0.0650191000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0049440000, 0.0041222000, 0.0024557000, -0.000894200, -0.007647300, -0.021330300, -0.048984100", \ - "0.0049745000, 0.0041574000, 0.0024939000, -0.000828700, -0.007580200, -0.021245200, -0.048896400", \ - "0.0050362000, 0.0042317000, 0.0025989000, -0.000711800, -0.007451800, -0.021088000, -0.048718100", \ - "0.0048858000, 0.0040811000, 0.0024852000, -0.000773000, -0.007498000, -0.021094600, -0.048708800", \ - "0.0049134000, 0.0041093000, 0.0024829000, -0.000842200, -0.007620800, -0.021154200, -0.048714500", \ - "0.0051786000, 0.0043928000, 0.0025595000, -0.000775500, -0.007495700, -0.021106000, -0.048716200", \ - "0.0060478000, 0.0051892000, 0.0034487000, -9.40000e-06, -0.006861500, -0.020563800, -0.048399000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0093518000, 0.0101752000, 0.0119371000, 0.0152769000, 0.0220147000, 0.0356681000, 0.0629693000", \ - "0.0091496000, 0.0099868000, 0.0117387000, 0.0151081000, 0.0219204000, 0.0356340000, 0.0629855000", \ - "0.0089598000, 0.0098016000, 0.0115018000, 0.0149680000, 0.0218541000, 0.0354127000, 0.0628900000", \ - "0.0088893000, 0.0097025000, 0.0113817000, 0.0147455000, 0.0215430000, 0.0352425000, 0.0627171000", \ - "0.0087496000, 0.0095889000, 0.0112538000, 0.0146389000, 0.0214368000, 0.0350228000, 0.0625065000", \ - "0.0087633000, 0.0095717000, 0.0112523000, 0.0146324000, 0.0213907000, 0.0350156000, 0.0623420000", \ - "0.0091216000, 0.0099315000, 0.0115457000, 0.0148538000, 0.0215492000, 0.0351606000, 0.0626561000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0028894000, 0.0022196000, 0.0007961000, -0.002231200, -0.008696900, -0.022208200, -0.049770000", \ - "0.0028651000, 0.0021830000, 0.0007522000, -0.002251500, -0.008727000, -0.022223400, -0.049814500", \ - "0.0029140000, 0.0022120000, 0.0008026000, -0.002198600, -0.008668300, -0.022177700, -0.049762500", \ - "0.0027133000, 0.0020419000, 0.0006094000, -0.002400600, -0.008838100, -0.022320800, -0.049905500", \ - "0.0025033000, 0.0018048000, 0.0003885000, -0.002640100, -0.009026300, -0.022484100, -0.050006600", \ - "0.0027002000, 0.0019135000, 0.0003068000, -0.002951100, -0.009480400, -0.022695800, -0.050203200", \ - "0.0032233000, 0.0023452000, 0.0007287000, -0.002340100, -0.009025800, -0.022773800, -0.050283600"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0089724000, 0.0098597000, 0.0115894000, 0.0150736000, 0.0219270000, 0.0357000000, 0.0631494000", \ - "0.0089665000, 0.0098190000, 0.0115899000, 0.0150690000, 0.0219337000, 0.0355796000, 0.0630025000", \ - "0.0089168000, 0.0097727000, 0.0115140000, 0.0150155000, 0.0218357000, 0.0355713000, 0.0631216000", \ - "0.0086079000, 0.0094731000, 0.0112124000, 0.0146128000, 0.0215013000, 0.0352998000, 0.0627418000", \ - "0.0083443000, 0.0091823000, 0.0108774000, 0.0143566000, 0.0211833000, 0.0350869000, 0.0627617000", \ - "0.0082584000, 0.0090984000, 0.0108056000, 0.0141363000, 0.0209061000, 0.0346880000, 0.0622047000", \ - "0.0085703000, 0.0094150000, 0.0110692000, 0.0142639000, 0.0210500000, 0.0349139000, 0.0622962000"); - } - } - max_capacitance : 0.0338840000; - max_transition : 1.4791600000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0202338000, 0.0222449000, 0.0262332000, 0.0339961000, 0.0489276000, 0.0776554000, 0.1331733000", \ - "0.0255936000, 0.0275353000, 0.0313815000, 0.0389696000, 0.0537386000, 0.0823214000, 0.1378008000", \ - "0.0378430000, 0.0397720000, 0.0437403000, 0.0508897000, 0.0651843000, 0.0933933000, 0.1486432000", \ - "0.0564512000, 0.0595777000, 0.0652307000, 0.0752066000, 0.0922927000, 0.1200981000, 0.1739916000", \ - "0.0803840000, 0.0849646000, 0.0935798000, 0.1082716000, 0.1340392000, 0.1746486000, 0.2358817000", \ - "0.1034364000, 0.1104487000, 0.1229221000, 0.1459253000, 0.1850252000, 0.2460792000, 0.3409733000", \ - "0.1025667000, 0.1132093000, 0.1333851000, 0.1684450000, 0.2288889000, 0.3266928000, 0.4734578000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.2030005000, 0.2188656000, 0.2495229000, 0.3126740000, 0.4384671000, 0.6852889000, 1.1883846000", \ - "0.2059491000, 0.2218591000, 0.2531218000, 0.3161517000, 0.4424782000, 0.6905281000, 1.1946450000", \ - "0.2171232000, 0.2323210000, 0.2640004000, 0.3258097000, 0.4510542000, 0.7022979000, 1.2096020000", \ - "0.2422358000, 0.2576419000, 0.2888449000, 0.3514784000, 0.4751653000, 0.7264858000, 1.2368632000", \ - "0.2947524000, 0.3100667000, 0.3412079000, 0.4030266000, 0.5271110000, 0.7787312000, 1.2832418000", \ - "0.3876111000, 0.4052616000, 0.4395433000, 0.5066580000, 0.6331043000, 0.8827701000, 1.3910459000", \ - "0.5346422000, 0.5584256000, 0.6011535000, 0.6825226000, 0.8319833000, 1.1050952000, 1.6148776000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0202574000, 0.0227689000, 0.0278020000, 0.0376776000, 0.0562781000, 0.0926301000, 0.1638602000", \ - "0.0203067000, 0.0226498000, 0.0274166000, 0.0370161000, 0.0559203000, 0.0924720000, 0.1636200000", \ - "0.0253494000, 0.0270457000, 0.0307667000, 0.0386415000, 0.0558353000, 0.0919802000, 0.1634024000", \ - "0.0397738000, 0.0419831000, 0.0460131000, 0.0533913000, 0.0653316000, 0.0955917000, 0.1632167000", \ - "0.0651325000, 0.0683655000, 0.0738889000, 0.0842789000, 0.1011898000, 0.1292209000, 0.1807419000", \ - "0.1065190000, 0.1111981000, 0.1203213000, 0.1361597000, 0.1619291000, 0.2070070000, 0.2667849000", \ - "0.1825803000, 0.1906436000, 0.2045970000, 0.2294882000, 0.2699974000, 0.3326708000, 0.4264321000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1509433000, 0.1711600000, 0.2108937000, 0.2935228000, 0.4582356000, 0.7884571000, 1.4577365000", \ - "0.1509520000, 0.1712342000, 0.2115164000, 0.2940188000, 0.4607523000, 0.7895429000, 1.4581956000", \ - "0.1505351000, 0.1708215000, 0.2118687000, 0.2928325000, 0.4584877000, 0.7889869000, 1.4609910000", \ - "0.1508692000, 0.1708598000, 0.2119629000, 0.2938211000, 0.4586412000, 0.7887941000, 1.4610324000", \ - "0.1529150000, 0.1728235000, 0.2128568000, 0.2938767000, 0.4581575000, 0.7915021000, 1.4619870000", \ - "0.1783097000, 0.1973232000, 0.2358045000, 0.3103808000, 0.4671804000, 0.7930286000, 1.4607245000", \ - "0.2356808000, 0.2567632000, 0.2964243000, 0.3775571000, 0.5350412000, 0.8379318000, 1.4743311000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0220998000, 0.0241864000, 0.0282226000, 0.0360450000, 0.0508788000, 0.0793765000, 0.1350127000", \ - "0.0273036000, 0.0293120000, 0.0332693000, 0.0409052000, 0.0555830000, 0.0840143000, 0.1396444000", \ - "0.0392225000, 0.0412628000, 0.0452365000, 0.0524917000, 0.0666777000, 0.0949458000, 0.1504998000", \ - "0.0571310000, 0.0600872000, 0.0658490000, 0.0754648000, 0.0925368000, 0.1207270000, 0.1758967000", \ - "0.0775508000, 0.0824478000, 0.0912442000, 0.1067507000, 0.1326566000, 0.1739108000, 0.2364279000", \ - "0.0929613000, 0.0999894000, 0.1127935000, 0.1376734000, 0.1781607000, 0.2415098000, 0.3387289000", \ - "0.0774074000, 0.0878869000, 0.1099319000, 0.1470338000, 0.2107887000, 0.3123851000, 0.4646373000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1904601000, 0.2058929000, 0.2374801000, 0.2991183000, 0.4235469000, 0.6730420000, 1.1757270000", \ - "0.1920427000, 0.2079132000, 0.2395938000, 0.3016967000, 0.4268861000, 0.6775583000, 1.1873573000", \ - "0.2014701000, 0.2172253000, 0.2489576000, 0.3122486000, 0.4364804000, 0.6880327000, 1.1932138000", \ - "0.2272986000, 0.2427260000, 0.2740266000, 0.3370269000, 0.4607589000, 0.7119118000, 1.2174324000", \ - "0.2824918000, 0.2980314000, 0.3292937000, 0.3911634000, 0.5168664000, 0.7684089000, 1.2723503000", \ - "0.3831833000, 0.4021843000, 0.4383270000, 0.5081154000, 0.6358883000, 0.8880474000, 1.3902204000", \ - "0.5509614000, 0.5775087000, 0.6272473000, 0.7179081000, 0.8773769000, 1.1571286000, 1.6674536000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0214270000, 0.0239037000, 0.0287403000, 0.0379626000, 0.0561977000, 0.0921292000, 0.1642898000", \ - "0.0210304000, 0.0233768000, 0.0280865000, 0.0375557000, 0.0557676000, 0.0918648000, 0.1642669000", \ - "0.0248126000, 0.0266767000, 0.0303947000, 0.0384310000, 0.0553456000, 0.0915823000, 0.1641704000", \ - "0.0382803000, 0.0403798000, 0.0446658000, 0.0524907000, 0.0651156000, 0.0953251000, 0.1639287000", \ - "0.0616586000, 0.0649765000, 0.0709543000, 0.0825462000, 0.0990193000, 0.1282970000, 0.1818151000", \ - "0.1031155000, 0.1081461000, 0.1178387000, 0.1329853000, 0.1600032000, 0.2043566000, 0.2696773000", \ - "0.1770852000, 0.1877723000, 0.2001075000, 0.2272613000, 0.2686021000, 0.3332499000, 0.4290246000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1506800000, 0.1706265000, 0.2117023000, 0.2931155000, 0.4578444000, 0.7900471000, 1.4602175000", \ - "0.1509549000, 0.1706701000, 0.2117829000, 0.2929292000, 0.4583807000, 0.7887347000, 1.4616076000", \ - "0.1508419000, 0.1708432000, 0.2117905000, 0.2940062000, 0.4586527000, 0.7891969000, 1.4629921000", \ - "0.1508918000, 0.1711534000, 0.2119164000, 0.2935684000, 0.4573548000, 0.7909627000, 1.4569748000", \ - "0.1563841000, 0.1754224000, 0.2136057000, 0.2945532000, 0.4595220000, 0.7909939000, 1.4617879000", \ - "0.1908528000, 0.2096220000, 0.2464650000, 0.3186935000, 0.4717581000, 0.7938649000, 1.4598118000", \ - "0.2730217000, 0.2928159000, 0.3319875000, 0.4085007000, 0.5601503000, 0.8476769000, 1.4777255000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0220864000, 0.0239252000, 0.0276083000, 0.0346941000, 0.0485779000, 0.0760192000, 0.1307491000", \ - "0.0269572000, 0.0288166000, 0.0323531000, 0.0394466000, 0.0533639000, 0.0808115000, 0.1355539000", \ - "0.0379669000, 0.0400258000, 0.0439081000, 0.0509047000, 0.0644807000, 0.0919124000, 0.1466255000", \ - "0.0533919000, 0.0564551000, 0.0623849000, 0.0728916000, 0.0895483000, 0.1176774000, 0.1725370000", \ - "0.0691643000, 0.0743028000, 0.0838595000, 0.1000934000, 0.1271262000, 0.1691885000, 0.2314775000", \ - "0.0762127000, 0.0836879000, 0.0996611000, 0.1253428000, 0.1683395000, 0.2349536000, 0.3333893000", \ - "0.0471179000, 0.0598434000, 0.0831333000, 0.1244845000, 0.1925821000, 0.2984970000, 0.4547514000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1553433000, 0.1706388000, 0.2026244000, 0.2641407000, 0.3890780000, 0.6426124000, 1.1521720000", \ - "0.1567886000, 0.1727133000, 0.2044531000, 0.2664560000, 0.3917185000, 0.6434692000, 1.1451585000", \ - "0.1655637000, 0.1809772000, 0.2129721000, 0.2761465000, 0.4032740000, 0.6517856000, 1.1570378000", \ - "0.1905436000, 0.2061433000, 0.2364778000, 0.2992464000, 0.4261934000, 0.6799877000, 1.1876653000", \ - "0.2468445000, 0.2627430000, 0.2940249000, 0.3563103000, 0.4817745000, 0.7310000000, 1.2359509000", \ - "0.3514307000, 0.3723185000, 0.4129506000, 0.4871368000, 0.6165335000, 0.8675891000, 1.3757677000", \ - "0.5287023000, 0.5598129000, 0.6175209000, 0.7191216000, 0.8909191000, 1.1826737000, 1.6908860000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0181395000, 0.0203808000, 0.0247340000, 0.0334242000, 0.0510260000, 0.0868344000, 0.1588187000", \ - "0.0179716000, 0.0200631000, 0.0244744000, 0.0332973000, 0.0509034000, 0.0866638000, 0.1587030000", \ - "0.0220684000, 0.0236553000, 0.0272005000, 0.0348920000, 0.0512105000, 0.0866384000, 0.1589036000", \ - "0.0345765000, 0.0368335000, 0.0417735000, 0.0489193000, 0.0618259000, 0.0912925000, 0.1592504000", \ - "0.0569223000, 0.0604440000, 0.0670211000, 0.0779368000, 0.0958037000, 0.1262558000, 0.1797496000", \ - "0.0980808000, 0.1038214000, 0.1128397000, 0.1296994000, 0.1579596000, 0.2003574000, 0.2664205000", \ - "0.1712852000, 0.1800559000, 0.1957654000, 0.2223792000, 0.2648465000, 0.3309427000, 0.4287418000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1506641000, 0.1703828000, 0.2117683000, 0.2932300000, 0.4578525000, 0.7911933000, 1.4649979000", \ - "0.1508214000, 0.1705069000, 0.2116317000, 0.2931822000, 0.4578704000, 0.7915284000, 1.4577874000", \ - "0.1502728000, 0.1705830000, 0.2116459000, 0.2935217000, 0.4610695000, 0.7894170000, 1.4581907000", \ - "0.1507823000, 0.1704326000, 0.2113128000, 0.2930769000, 0.4583723000, 0.7921741000, 1.4616460000", \ - "0.1598029000, 0.1784733000, 0.2168259000, 0.2955295000, 0.4584650000, 0.7895214000, 1.4577816000", \ - "0.2061752000, 0.2243647000, 0.2615998000, 0.3301828000, 0.4765338000, 0.7928858000, 1.4604806000", \ - "0.3065214000, 0.3271039000, 0.3684703000, 0.4462734000, 0.5905869000, 0.8664516000, 1.4791597000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1095944000, 0.1129144000, 0.1188885000, 0.1290702000, 0.1468742000, 0.1781014000, 0.2355173000", \ - "0.1146355000, 0.1177600000, 0.1237244000, 0.1340303000, 0.1518699000, 0.1831461000, 0.2406444000", \ - "0.1271807000, 0.1304286000, 0.1363713000, 0.1468391000, 0.1645902000, 0.1958047000, 0.2532938000", \ - "0.1589640000, 0.1622125000, 0.1681082000, 0.1784790000, 0.1963722000, 0.2276307000, 0.2850990000", \ - "0.2297876000, 0.2331856000, 0.2393848000, 0.2500947000, 0.2683175000, 0.2999157000, 0.3577900000", \ - "0.3487377000, 0.3530423000, 0.3606691000, 0.3735290000, 0.3945994000, 0.4288465000, 0.4885450000", \ - "0.5367655000, 0.5422278000, 0.5519982000, 0.5685544000, 0.5937229000, 0.6351508000, 0.6990706000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1309237000, 0.1472732000, 0.1796033000, 0.2435223000, 0.3690866000, 0.6224199000, 1.1248359000", \ - "0.1356913000, 0.1515893000, 0.1836748000, 0.2477984000, 0.3751862000, 0.6247684000, 1.1320950000", \ - "0.1460868000, 0.1619981000, 0.1938134000, 0.2578426000, 0.3845587000, 0.6378221000, 1.1429938000", \ - "0.1657898000, 0.1811161000, 0.2127133000, 0.2766245000, 0.4027229000, 0.6554979000, 1.1663372000", \ - "0.1934199000, 0.2088188000, 0.2397502000, 0.3026477000, 0.4304765000, 0.6836924000, 1.1944548000", \ - "0.2277068000, 0.2424012000, 0.2726984000, 0.3343124000, 0.4601008000, 0.7119415000, 1.2172401000", \ - "0.2561513000, 0.2698803000, 0.2981629000, 0.3577418000, 0.4820703000, 0.7349515000, 1.2377535000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0284351000, 0.0311193000, 0.0355469000, 0.0446390000, 0.0615996000, 0.0954880000, 0.1661232000", \ - "0.0285695000, 0.0312914000, 0.0356040000, 0.0446635000, 0.0617588000, 0.0955941000, 0.1660298000", \ - "0.0288023000, 0.0311618000, 0.0357902000, 0.0446599000, 0.0616466000, 0.0955661000, 0.1661347000", \ - "0.0286441000, 0.0313046000, 0.0356501000, 0.0445915000, 0.0616225000, 0.0954154000, 0.1665683000", \ - "0.0318714000, 0.0340542000, 0.0384306000, 0.0466717000, 0.0632633000, 0.0963358000, 0.1667730000", \ - "0.0440320000, 0.0462475000, 0.0506510000, 0.0587379000, 0.0748020000, 0.1058233000, 0.1715344000", \ - "0.0643239000, 0.0671528000, 0.0732423000, 0.0820701000, 0.0963057000, 0.1253624000, 0.1869750000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1448795000, 0.1662235000, 0.2090490000, 0.2927804000, 0.4580973000, 0.7941331000, 1.4612344000", \ - "0.1446911000, 0.1663303000, 0.2091052000, 0.2931055000, 0.4590316000, 0.7897819000, 1.4606223000", \ - "0.1447393000, 0.1662121000, 0.2089008000, 0.2930963000, 0.4583125000, 0.7912220000, 1.4610887000", \ - "0.1433628000, 0.1653399000, 0.2082560000, 0.2923370000, 0.4579215000, 0.7917670000, 1.4606037000", \ - "0.1423510000, 0.1634986000, 0.2070443000, 0.2924067000, 0.4581648000, 0.7948446000, 1.4693232000", \ - "0.1411214000, 0.1627397000, 0.2059460000, 0.2915634000, 0.4578554000, 0.7914995000, 1.4587205000", \ - "0.1457890000, 0.1648814000, 0.2055034000, 0.2897073000, 0.4597119000, 0.7933698000, 1.4573576000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4b_2") { - leakage_power () { - value : 0.0053971000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0039293000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0047642000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0004851000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0046828000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0004865000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0026311000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0003625000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0046485000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0004887000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0026336000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0003626000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0026434000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0003611000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0025145000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0003203000; - when : "A&B&C&!D_N"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__nor4b"; - cell_leakage_power : 0.0022944600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0044560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0070700000, 0.0070712000, 0.0070740000, 0.0070705000, 0.0070623000, 0.0070433000, 0.0069997000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006759200, -0.006835600, -0.007011800, -0.007045300, -0.007122600, -0.007300600, -0.007711000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046810000; - } - pin ("B") { - capacitance : 0.0044220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0095209000, 0.0095328000, 0.0095602000, 0.0095624000, 0.0095676000, 0.0095795000, 0.0096068000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006959000, -0.006994900, -0.007077600, -0.007108700, -0.007180300, -0.007345400, -0.007726000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047260000; - } - pin ("C") { - capacitance : 0.0043030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083312000, 0.0083290000, 0.0083240000, 0.0083282000, 0.0083379000, 0.0083604000, 0.0084121000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007520100, -0.007620400, -0.007851600, -0.007859600, -0.007878200, -0.007920900, -0.008019500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046400000; - } - pin ("D_N") { - capacitance : 0.0014290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0115543000, 0.0114646000, 0.0112579000, 0.0113173000, 0.0114543000, 0.0117699000, 0.0124976000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039983000, 0.0039533000, 0.0038497000, 0.0039064000, 0.0040372000, 0.0043387000, 0.0050336000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014770000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0101539000, 0.0091370000, 0.0068696000, 0.0017710000, -0.009677700, -0.035392600, -0.093545200", \ - "0.0101132000, 0.0091008000, 0.0068488000, 0.0017393000, -0.009700500, -0.035421700, -0.093582900", \ - "0.0100193000, 0.0090245000, 0.0068188000, 0.0017016000, -0.009737300, -0.035447300, -0.093591000", \ - "0.0097257000, 0.0087417000, 0.0065222000, 0.0014515000, -0.009902600, -0.035598700, -0.093734400", \ - "0.0097382000, 0.0087123000, 0.0064295000, 0.0013162000, -0.010098500, -0.035692500, -0.093780200", \ - "0.0107128000, 0.0096994000, 0.0074728000, 0.0024062000, -0.009155000, -0.035244400, -0.093621000", \ - "0.0133136000, 0.0122514000, 0.0098820000, 0.0045454000, -0.007155900, -0.033444400, -0.092250500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0223660000, 0.0234470000, 0.0258083000, 0.0310941000, 0.0426993000, 0.0687509000, 0.1268420000", \ - "0.0219821000, 0.0230573000, 0.0253735000, 0.0307228000, 0.0422459000, 0.0681704000, 0.1261166000", \ - "0.0216218000, 0.0226292000, 0.0249916000, 0.0301968000, 0.0418462000, 0.0678404000, 0.1258896000", \ - "0.0213613000, 0.0223921000, 0.0247511000, 0.0298720000, 0.0414496000, 0.0674467000, 0.1255713000", \ - "0.0211579000, 0.0221772000, 0.0244865000, 0.0296317000, 0.0412138000, 0.0672025000, 0.1252691000", \ - "0.0211703000, 0.0221361000, 0.0244426000, 0.0295666000, 0.0410061000, 0.0669455000, 0.1246099000", \ - "0.0211682000, 0.0221773000, 0.0244431000, 0.0295679000, 0.0413514000, 0.0668512000, 0.1249871000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0083801000, 0.0073580000, 0.0050730000, -6.86000e-05, -0.011582100, -0.037458600, -0.095855500", \ - "0.0083742000, 0.0073672000, 0.0050989000, 3.700000e-06, -0.011461100, -0.037354500, -0.095726600", \ - "0.0084254000, 0.0074328000, 0.0051783000, 0.0001430000, -0.011257500, -0.037038100, -0.095393700", \ - "0.0079792000, 0.0070214000, 0.0048402000, -9.44000e-05, -0.011370600, -0.037142200, -0.095375000", \ - "0.0079541000, 0.0069719000, 0.0047537000, -0.000223500, -0.011730500, -0.037313500, -0.095432900", \ - "0.0085317000, 0.0075309000, 0.0052820000, 0.0003130000, -0.011257800, -0.037040800, -0.095483900", \ - "0.0106491000, 0.0095916000, 0.0071796000, 0.0018274000, -0.009978800, -0.036036400, -0.094731600"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0190065000, 0.0200683000, 0.0225172000, 0.0276582000, 0.0392380000, 0.0650940000, 0.1229486000", \ - "0.0186142000, 0.0196753000, 0.0221253000, 0.0273449000, 0.0391477000, 0.0649105000, 0.1230086000", \ - "0.0182868000, 0.0193682000, 0.0216889000, 0.0270008000, 0.0386579000, 0.0645944000, 0.1226875000", \ - "0.0180528000, 0.0191301000, 0.0213669000, 0.0265685000, 0.0381535000, 0.0641541000, 0.1223623000", \ - "0.0178451000, 0.0188635000, 0.0211610000, 0.0263144000, 0.0379705000, 0.0636632000, 0.1221725000", \ - "0.0178223000, 0.0188541000, 0.0210761000, 0.0262444000, 0.0377610000, 0.0637191000, 0.1214337000", \ - "0.0183968000, 0.0193725000, 0.0215800000, 0.0265997000, 0.0380040000, 0.0638506000, 0.1217914000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0032646000, 0.0024167000, 0.0004756000, -0.003986300, -0.014760000, -0.040095800, -0.098215000", \ - "0.0032705000, 0.0024026000, 0.0004760000, -0.003964200, -0.014729000, -0.040067300, -0.098242400", \ - "0.0033060000, 0.0024766000, 0.0005285000, -0.003942900, -0.014668600, -0.040026500, -0.098166000", \ - "0.0030666000, 0.0021612000, 0.0002337000, -0.004233300, -0.014930900, -0.040241400, -0.098365700", \ - "0.0027266000, 0.0018004000, -0.000148700, -0.004585300, -0.015280400, -0.040515500, -0.098576800", \ - "0.0030046000, 0.0020154000, -0.000219800, -0.005197900, -0.015963200, -0.040903800, -0.098832000", \ - "0.0046298000, 0.0032330000, 0.0009364000, -0.003698900, -0.014987200, -0.040405200, -0.098365300"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0169790000, 0.0180756000, 0.0203952000, 0.0257384000, 0.0376666000, 0.0636749000, 0.1221616000", \ - "0.0169747000, 0.0180378000, 0.0203924000, 0.0257360000, 0.0376161000, 0.0634414000, 0.1215938000", \ - "0.0169755000, 0.0180117000, 0.0204128000, 0.0257325000, 0.0375432000, 0.0635749000, 0.1220149000", \ - "0.0167509000, 0.0177742000, 0.0200685000, 0.0253405000, 0.0371589000, 0.0631217000, 0.1214424000", \ - "0.0163423000, 0.0174157000, 0.0196568000, 0.0248914000, 0.0365380000, 0.0625399000, 0.1209229000", \ - "0.0163611000, 0.0173804000, 0.0196915000, 0.0248221000, 0.0362475000, 0.0621666000, 0.1204382000", \ - "0.0166692000, 0.0176520000, 0.0199070000, 0.0248126000, 0.0360071000, 0.0620952000, 0.1201769000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0130550000, 0.0120672000, 0.0097934000, 0.0046899000, -0.006793600, -0.032586100, -0.090492300", \ - "0.0128628000, 0.0118840000, 0.0096060000, 0.0045015000, -0.006973400, -0.032748600, -0.090675700", \ - "0.0128136000, 0.0118013000, 0.0095360000, 0.0044046000, -0.007110600, -0.032887200, -0.090795700", \ - "0.0124565000, 0.0114759000, 0.0091434000, 0.0040899000, -0.007402000, -0.033146200, -0.091036400", \ - "0.0121441000, 0.0111504000, 0.0089051000, 0.0039119000, -0.007591500, -0.033201500, -0.091055900", \ - "0.0137676000, 0.0127496000, 0.0104242000, 0.0052269000, -0.006315400, -0.032605400, -0.090847100", \ - "0.0166500000, 0.0155983000, 0.0133816000, 0.0081300000, -0.003722600, -0.030173600, -0.089154500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011254020, 0.0025330600, 0.0057014220, 0.0128327800, 0.0288840800, 0.0650124200"); - values("0.0294802000, 0.0305464000, 0.0328810000, 0.0380203000, 0.0495689000, 0.0753424000, 0.1331858000", \ - "0.0291500000, 0.0301464000, 0.0325264000, 0.0377122000, 0.0493253000, 0.0751945000, 0.1331376000", \ - "0.0287862000, 0.0298197000, 0.0321729000, 0.0373326000, 0.0489751000, 0.0749211000, 0.1330279000", \ - "0.0285896000, 0.0296208000, 0.0319817000, 0.0370803000, 0.0486418000, 0.0746317000, 0.1327023000", \ - "0.0284351000, 0.0294247000, 0.0317269000, 0.0368936000, 0.0483363000, 0.0742095000, 0.1323028000", \ - "0.0284209000, 0.0294325000, 0.0317344000, 0.0368074000, 0.0482709000, 0.0741828000, 0.1320196000", \ - "0.0282191000, 0.0294202000, 0.0317162000, 0.0369095000, 0.0485005000, 0.0738742000, 0.1320172000"); - } - } - max_capacitance : 0.0650120000; - max_transition : 1.4960870000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0186632000, 0.0200093000, 0.0230175000, 0.0295165000, 0.0433553000, 0.0724971000, 0.1343142000", \ - "0.0241686000, 0.0254482000, 0.0283126000, 0.0345879000, 0.0482243000, 0.0771602000, 0.1388345000", \ - "0.0363659000, 0.0378396000, 0.0409386000, 0.0471382000, 0.0600623000, 0.0882639000, 0.1496362000", \ - "0.0548664000, 0.0569780000, 0.0615629000, 0.0704305000, 0.0864111000, 0.1153562000, 0.1759212000", \ - "0.0791046000, 0.0822351000, 0.0886675000, 0.1017108000, 0.1263915000, 0.1682919000, 0.2372860000", \ - "0.1024775000, 0.1071016000, 0.1169468000, 0.1368959000, 0.1733908000, 0.2387484000, 0.3440505000", \ - "0.1040552000, 0.1110414000, 0.1262622000, 0.1567602000, 0.2130425000, 0.3150693000, 0.4793251000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.2044698000, 0.2150123000, 0.2379063000, 0.2873981000, 0.3985451000, 0.6467558000, 1.2035593000", \ - "0.2075834000, 0.2174245000, 0.2407182000, 0.2906650000, 0.4025024000, 0.6515601000, 1.2086064000", \ - "0.2184307000, 0.2283987000, 0.2514977000, 0.3012868000, 0.4133621000, 0.6631710000, 1.2211741000", \ - "0.2448003000, 0.2547065000, 0.2774685000, 0.3269904000, 0.4384668000, 0.6880117000, 1.2470907000", \ - "0.2983497000, 0.3079816000, 0.3307246000, 0.3803403000, 0.4909887000, 0.7399380000, 1.2989201000", \ - "0.3895819000, 0.4010304000, 0.4257880000, 0.4806190000, 0.5955501000, 0.8459356000, 1.4025668000", \ - "0.5317544000, 0.5476550000, 0.5785156000, 0.6451421000, 0.7804011000, 1.0573605000, 1.6219858000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0193294000, 0.0211320000, 0.0249699000, 0.0333889000, 0.0509253000, 0.0879315000, 0.1675779000", \ - "0.0197887000, 0.0213057000, 0.0248294000, 0.0328435000, 0.0503555000, 0.0875695000, 0.1674917000", \ - "0.0255862000, 0.0265734000, 0.0290781000, 0.0354170000, 0.0507377000, 0.0866931000, 0.1672746000", \ - "0.0400517000, 0.0414601000, 0.0444251000, 0.0505661000, 0.0622364000, 0.0914182000, 0.1666211000", \ - "0.0646028000, 0.0666796000, 0.0709472000, 0.0800199000, 0.0964764000, 0.1254911000, 0.1847661000", \ - "0.1060829000, 0.1094396000, 0.1161821000, 0.1300536000, 0.1550127000, 0.1973516000, 0.2684455000", \ - "0.1796793000, 0.1851522000, 0.1972129000, 0.2185409000, 0.2558172000, 0.3211440000, 0.4250779000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1346611000, 0.1477962000, 0.1775751000, 0.2439496000, 0.3923314000, 0.7247855000, 1.4698620000", \ - "0.1349133000, 0.1486691000, 0.1777256000, 0.2439828000, 0.3928024000, 0.7246754000, 1.4710442000", \ - "0.1355674000, 0.1480802000, 0.1777316000, 0.2439933000, 0.3927631000, 0.7247907000, 1.4710251000", \ - "0.1356868000, 0.1488784000, 0.1779475000, 0.2439246000, 0.3922228000, 0.7263226000, 1.4743609000", \ - "0.1370771000, 0.1498271000, 0.1790513000, 0.2441924000, 0.3927572000, 0.7247341000, 1.4710081000", \ - "0.1598321000, 0.1727376000, 0.2012967000, 0.2623354000, 0.4029828000, 0.7286488000, 1.4721835000", \ - "0.2110598000, 0.2244483000, 0.2542704000, 0.3204335000, 0.4656634000, 0.7755355000, 1.4896895000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0205609000, 0.0220011000, 0.0251504000, 0.0318250000, 0.0457406000, 0.0747882000, 0.1369096000", \ - "0.0259750000, 0.0273382000, 0.0303496000, 0.0368618000, 0.0504921000, 0.0794342000, 0.1415619000", \ - "0.0382221000, 0.0396658000, 0.0426511000, 0.0488644000, 0.0620788000, 0.0904998000, 0.1525076000", \ - "0.0561807000, 0.0584331000, 0.0625519000, 0.0717866000, 0.0880976000, 0.1166034000, 0.1781720000", \ - "0.0781625000, 0.0813675000, 0.0879655000, 0.1010050000, 0.1260267000, 0.1691300000, 0.2391912000", \ - "0.0954638000, 0.1002375000, 0.1105526000, 0.1305765000, 0.1700815000, 0.2371827000, 0.3455121000", \ - "0.0870374000, 0.0945040000, 0.1103736000, 0.1421162000, 0.2021197000, 0.3078219000, 0.4781038000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1883819000, 0.1990663000, 0.2221696000, 0.2728884000, 0.3854290000, 0.6357088000, 1.1992197000", \ - "0.1900130000, 0.2005001000, 0.2233290000, 0.2747317000, 0.3859237000, 0.6350693000, 1.1927174000", \ - "0.1994630000, 0.2092868000, 0.2324787000, 0.2826735000, 0.3949536000, 0.6452169000, 1.2033318000", \ - "0.2234791000, 0.2336274000, 0.2562580000, 0.3058560000, 0.4175510000, 0.6675872000, 1.2270398000", \ - "0.2746326000, 0.2849031000, 0.3078028000, 0.3577370000, 0.4694718000, 0.7219383000, 1.2788994000", \ - "0.3620431000, 0.3742144000, 0.4011605000, 0.4594173000, 0.5782834000, 0.8277563000, 1.3874671000", \ - "0.5037235000, 0.5204619000, 0.5575105000, 0.6348791000, 0.7837282000, 1.0684310000, 1.6360638000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0206591000, 0.0223392000, 0.0260616000, 0.0338650000, 0.0505189000, 0.0867543000, 0.1677497000", \ - "0.0203258000, 0.0219700000, 0.0254252000, 0.0332988000, 0.0500422000, 0.0864975000, 0.1673992000", \ - "0.0247595000, 0.0258339000, 0.0284229000, 0.0348656000, 0.0500558000, 0.0860434000, 0.1674799000", \ - "0.0381762000, 0.0395195000, 0.0431067000, 0.0487096000, 0.0603990000, 0.0904958000, 0.1669218000", \ - "0.0607905000, 0.0630754000, 0.0679324000, 0.0770682000, 0.0931722000, 0.1241905000, 0.1846609000", \ - "0.1004926000, 0.1041117000, 0.1108009000, 0.1256006000, 0.1514247000, 0.1947261000, 0.2691527000", \ - "0.1717646000, 0.1774063000, 0.1891725000, 0.2123772000, 0.2529436000, 0.3198454000, 0.4268057000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1351325000, 0.1479205000, 0.1775194000, 0.2446625000, 0.3933714000, 0.7312775000, 1.4853341000", \ - "0.1346411000, 0.1480721000, 0.1776622000, 0.2446394000, 0.3931734000, 0.7252523000, 1.4706846000", \ - "0.1349781000, 0.1487104000, 0.1777099000, 0.2440660000, 0.3924397000, 0.7258343000, 1.4739479000", \ - "0.1357326000, 0.1488293000, 0.1780014000, 0.2440674000, 0.3922700000, 0.7260786000, 1.4748249000", \ - "0.1408358000, 0.1531482000, 0.1812337000, 0.2456200000, 0.3936097000, 0.7283086000, 1.4755832000", \ - "0.1726623000, 0.1859145000, 0.2146309000, 0.2745536000, 0.4109048000, 0.7314293000, 1.4721280000", \ - "0.2482008000, 0.2616680000, 0.2911150000, 0.3560611000, 0.4960983000, 0.7945213000, 1.4960874000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0213084000, 0.0226165000, 0.0254227000, 0.0314599000, 0.0443287000, 0.0721051000, 0.1332677000", \ - "0.0262541000, 0.0275277000, 0.0303069000, 0.0363200000, 0.0490416000, 0.0768230000, 0.1379876000", \ - "0.0373641000, 0.0388122000, 0.0418245000, 0.0478448000, 0.0604261000, 0.0880231000, 0.1492016000", \ - "0.0528684000, 0.0550580000, 0.0596618000, 0.0686706000, 0.0853237000, 0.1140207000, 0.1749713000", \ - "0.0693454000, 0.0727689000, 0.0799387000, 0.0941759000, 0.1202374000, 0.1647150000, 0.2361298000", \ - "0.0784278000, 0.0837212000, 0.0948385000, 0.1162068000, 0.1582377000, 0.2286636000, 0.3399715000", \ - "0.0538684000, 0.0622104000, 0.0798852000, 0.1149555000, 0.1805603000, 0.2923057000, 0.4680962000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1534486000, 0.1634719000, 0.1870709000, 0.2368531000, 0.3485028000, 0.5970834000, 1.1538002000", \ - "0.1547759000, 0.1647612000, 0.1882500000, 0.2393573000, 0.3529239000, 0.6001366000, 1.1625025000", \ - "0.1630633000, 0.1736804000, 0.1964781000, 0.2471950000, 0.3617400000, 0.6089137000, 1.1681295000", \ - "0.1879292000, 0.1980341000, 0.2204339000, 0.2702449000, 0.3814452000, 0.6317225000, 1.1912361000", \ - "0.2406019000, 0.2512478000, 0.2742915000, 0.3244753000, 0.4365384000, 0.6876513000, 1.2446151000", \ - "0.3330090000, 0.3472325000, 0.3774679000, 0.4412578000, 0.5639560000, 0.8139463000, 1.3750072000", \ - "0.4807727000, 0.5022943000, 0.5475877000, 0.6371307000, 0.8045063000, 1.1077440000, 1.6756587000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0176438000, 0.0190423000, 0.0223352000, 0.0295169000, 0.0453271000, 0.0807466000, 0.1611890000", \ - "0.0173254000, 0.0187231000, 0.0219172000, 0.0291847000, 0.0451575000, 0.0808490000, 0.1613074000", \ - "0.0216528000, 0.0226589000, 0.0250337000, 0.0309988000, 0.0454504000, 0.0806728000, 0.1612360000", \ - "0.0336408000, 0.0351560000, 0.0383311000, 0.0446774000, 0.0567015000, 0.0856956000, 0.1616740000", \ - "0.0555598000, 0.0579007000, 0.0629299000, 0.0721216000, 0.0890142000, 0.1210927000, 0.1799491000", \ - "0.0935062000, 0.0973593000, 0.1046275000, 0.1201056000, 0.1477075000, 0.1920192000, 0.2650272000", \ - "0.1639848000, 0.1700495000, 0.1823719000, 0.2059424000, 0.2485743000, 0.3165052000, 0.4257110000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1350756000, 0.1483303000, 0.1777981000, 0.2441055000, 0.3926069000, 0.7271221000, 1.4714392000", \ - "0.1351070000, 0.1483616000, 0.1777268000, 0.2443659000, 0.3934198000, 0.7246193000, 1.4766478000", \ - "0.1349543000, 0.1475606000, 0.1773390000, 0.2448209000, 0.3940861000, 0.7245420000, 1.4710390000", \ - "0.1350328000, 0.1477279000, 0.1775061000, 0.2438129000, 0.3928720000, 0.7245784000, 1.4707604000", \ - "0.1447494000, 0.1570743000, 0.1845587000, 0.2479319000, 0.3941810000, 0.7271745000, 1.4751175000", \ - "0.1875926000, 0.2006290000, 0.2293206000, 0.2889854000, 0.4164276000, 0.7308317000, 1.4739823000", \ - "0.2826013000, 0.2978769000, 0.3302300000, 0.3982731000, 0.5332956000, 0.8134192000, 1.4941024000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1285085000, 0.1311598000, 0.1365980000, 0.1468955000, 0.1656855000, 0.1992686000, 0.2633491000", \ - "0.1335115000, 0.1361451000, 0.1415540000, 0.1519137000, 0.1706665000, 0.2042004000, 0.2683475000", \ - "0.1458616000, 0.1485193000, 0.1539478000, 0.1641979000, 0.1830591000, 0.2165648000, 0.2808027000", \ - "0.1765748000, 0.1793395000, 0.1847440000, 0.1950829000, 0.2137162000, 0.2474426000, 0.3116019000", \ - "0.2479218000, 0.2505886000, 0.2560213000, 0.2664503000, 0.2854228000, 0.3191881000, 0.3834588000", \ - "0.3733421000, 0.3764130000, 0.3829861000, 0.3956506000, 0.4176283000, 0.4546363000, 0.5216240000", \ - "0.5625814000, 0.5666642000, 0.5748724000, 0.5912938000, 0.6192729000, 0.6635473000, 0.7375509000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1226002000, 0.1318954000, 0.1536378000, 0.2049801000, 0.3187704000, 0.5685971000, 1.1320782000", \ - "0.1273497000, 0.1368930000, 0.1584790000, 0.2095396000, 0.3238496000, 0.5734062000, 1.1326861000", \ - "0.1388483000, 0.1483402000, 0.1702129000, 0.2208839000, 0.3344622000, 0.5846403000, 1.1482364000", \ - "0.1642013000, 0.1734835000, 0.1946140000, 0.2447459000, 0.3579998000, 0.6090619000, 1.1720931000", \ - "0.2075289000, 0.2165645000, 0.2371663000, 0.2865233000, 0.3987325000, 0.6494928000, 1.2111742000", \ - "0.2689307000, 0.2770957000, 0.2967649000, 0.3441664000, 0.4545544000, 0.7037120000, 1.2635821000", \ - "0.3438277000, 0.3520854000, 0.3714370000, 0.4158896000, 0.5235335000, 0.7724171000, 1.3306106000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.0313346000, 0.0330040000, 0.0365877000, 0.0444268000, 0.0593231000, 0.0918138000, 0.1649737000", \ - "0.0313619000, 0.0329763000, 0.0364718000, 0.0445680000, 0.0596979000, 0.0921617000, 0.1648310000", \ - "0.0317169000, 0.0332396000, 0.0368288000, 0.0443078000, 0.0597627000, 0.0918380000, 0.1652081000", \ - "0.0314594000, 0.0330900000, 0.0366542000, 0.0442975000, 0.0596994000, 0.0919163000, 0.1650873000", \ - "0.0330140000, 0.0344718000, 0.0377572000, 0.0449381000, 0.0603490000, 0.0923687000, 0.1651922000", \ - "0.0462064000, 0.0478950000, 0.0514967000, 0.0580369000, 0.0723905000, 0.1023287000, 0.1706055000", \ - "0.0682369000, 0.0705548000, 0.0740512000, 0.0827097000, 0.0974663000, 0.1268578000, 0.1902008000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011254000, 0.0025330600, 0.0057014200, 0.0128328000, 0.0288841000, 0.0650124000"); - values("0.1210227000, 0.1354697000, 0.1680676000, 0.2393318000, 0.3930802000, 0.7269750000, 1.4813419000", \ - "0.1210790000, 0.1350836000, 0.1680505000, 0.2391247000, 0.3928001000, 0.7294864000, 1.4729304000", \ - "0.1209224000, 0.1358090000, 0.1678827000, 0.2397445000, 0.3930313000, 0.7271404000, 1.4813475000", \ - "0.1202398000, 0.1351923000, 0.1670446000, 0.2390963000, 0.3929236000, 0.7256535000, 1.4772134000", \ - "0.1196381000, 0.1336565000, 0.1656986000, 0.2374712000, 0.3917259000, 0.7262092000, 1.4756379000", \ - "0.1203981000, 0.1344698000, 0.1659312000, 0.2360576000, 0.3909487000, 0.7272080000, 1.4719349000", \ - "0.1290126000, 0.1413871000, 0.1706134000, 0.2362896000, 0.3887010000, 0.7290926000, 1.4707981000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4b_4") { - leakage_power () { - value : 0.0184481000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0043410000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0121737000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0004944000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0120930000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0004974000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0098057000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0003598000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0120646000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0004999000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0098089000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0005285000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0098296000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0003652000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0100500000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0204222000; - when : "A&B&C&!D_N"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__nor4b"; - cell_leakage_power : 0.0076113790; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0085850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0140888000, 0.0140839000, 0.0140727000, 0.0140679000, 0.0140566000, 0.0140308000, 0.0139710000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013191200, -0.013329000, -0.013646500, -0.013706100, -0.013843600, -0.014160500, -0.014891000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090510000; - } - pin ("B") { - capacitance : 0.0084790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0214155000, 0.0214021000, 0.0213713000, 0.0213688000, 0.0213629000, 0.0213495000, 0.0213183000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013343800, -0.013418200, -0.013589800, -0.013656800, -0.013811300, -0.014167300, -0.014988100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090690000; - } - pin ("C") { - capacitance : 0.0083790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0162977000, 0.0162931000, 0.0162824000, 0.0162908000, 0.0163101000, 0.0163547000, 0.0164572000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014821200, -0.015005600, -0.015430600, -0.015443200, -0.015472200, -0.015539200, -0.015693500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090320000; - } - pin ("D_N") { - capacitance : 0.0024210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213841000, 0.0212423000, 0.0209156000, 0.0211059000, 0.0215444000, 0.0225555000, 0.0248861000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0066424000, 0.0065307000, 0.0062730000, 0.0064048000, 0.0067086000, 0.0074090000, 0.0090233000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025260000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&!C&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0257232000, 0.0245343000, 0.0216000000, 0.0143801000, -0.003439200, -0.047482500, -0.155893500", \ - "0.0254330000, 0.0242402000, 0.0213062000, 0.0140567000, -0.003805700, -0.047801900, -0.156226700", \ - "0.0252551000, 0.0240921000, 0.0211945000, 0.0139196000, -0.004057000, -0.048038600, -0.156389700", \ - "0.0244680000, 0.0233089000, 0.0204341000, 0.0133095000, -0.004501500, -0.048475100, -0.156904000", \ - "0.0241985000, 0.0230025000, 0.0201746000, 0.0132356000, -0.004371600, -0.048684400, -0.156813900", \ - "0.0259097000, 0.0247019000, 0.0217657000, 0.0144606000, -0.003397200, -0.047978900, -0.156278500", \ - "0.0321938000, 0.0309709000, 0.0279488000, 0.0205547000, 0.0014235000, -0.043432400, -0.153099800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0564816000, 0.0577213000, 0.0606919000, 0.0680693000, 0.0860170000, 0.1299101000, 0.2381069000", \ - "0.0558108000, 0.0570674000, 0.0600592000, 0.0676037000, 0.0854853000, 0.1295944000, 0.2378415000", \ - "0.0552264000, 0.0564675000, 0.0594082000, 0.0668749000, 0.0849120000, 0.1291958000, 0.2375805000", \ - "0.0547262000, 0.0559257000, 0.0588734000, 0.0663522000, 0.0846075000, 0.1286702000, 0.2370907000", \ - "0.0543675000, 0.0555627000, 0.0585624000, 0.0658486000, 0.0836725000, 0.1280006000, 0.2366473000", \ - "0.0542453000, 0.0553694000, 0.0583239000, 0.0655935000, 0.0834692000, 0.1278093000, 0.2364151000", \ - "0.0543306000, 0.0555162000, 0.0585303000, 0.0658423000, 0.0836543000, 0.1272830000, 0.2357103000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0202089000, 0.0190304000, 0.0161044000, 0.0088742000, -0.008938000, -0.052798600, -0.161583400", \ - "0.0201459000, 0.0189567000, 0.0160281000, 0.0088001000, -0.008994300, -0.052852500, -0.161629600", \ - "0.0200806000, 0.0187789000, 0.0159497000, 0.0086463000, -0.009079900, -0.052925800, -0.161656600", \ - "0.0194549000, 0.0182816000, 0.0154017000, 0.0081715000, -0.009482800, -0.053170700, -0.161892700", \ - "0.0192086000, 0.0180445000, 0.0151448000, 0.0080449000, -0.009508600, -0.053471000, -0.161795700", \ - "0.0209358000, 0.0198717000, 0.0169054000, 0.0098235000, -0.008541000, -0.052308200, -0.161544500", \ - "0.0260012000, 0.0247641000, 0.0217372000, 0.0145423000, -0.003867600, -0.049032400, -0.158555500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0406750000, 0.0418467000, 0.0449291000, 0.0524219000, 0.0702068000, 0.1145793000, 0.2223907000", \ - "0.0398017000, 0.0409927000, 0.0440562000, 0.0517093000, 0.0697151000, 0.1137891000, 0.2222674000", \ - "0.0390965000, 0.0402719000, 0.0433467000, 0.0508888000, 0.0692972000, 0.1138424000, 0.2222444000", \ - "0.0386504000, 0.0398816000, 0.0427665000, 0.0500701000, 0.0681402000, 0.1126009000, 0.2213858000", \ - "0.0382371000, 0.0394337000, 0.0423881000, 0.0496235000, 0.0678398000, 0.1116653000, 0.2204343000", \ - "0.0380215000, 0.0392308000, 0.0422586000, 0.0494254000, 0.0671987000, 0.1114423000, 0.2197300000", \ - "0.0383654000, 0.0395644000, 0.0424515000, 0.0497109000, 0.0678282000, 0.1114585000, 0.2195871000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0163545000, 0.0151351000, 0.0121803000, 0.0048871000, -0.013019000, -0.057175500, -0.166337100", \ - "0.0163452000, 0.0151638000, 0.0122534000, 0.0049953000, -0.012844300, -0.056886900, -0.166074300", \ - "0.0164911000, 0.0153197000, 0.0124118000, 0.0052321000, -0.012468400, -0.056385600, -0.165461800", \ - "0.0157979000, 0.0146637000, 0.0118353000, 0.0048749000, -0.012724700, -0.056434100, -0.165381000", \ - "0.0159478000, 0.0148004000, 0.0119772000, 0.0048403000, -0.012788200, -0.056663800, -0.165318800", \ - "0.0167506000, 0.0154403000, 0.0124985000, 0.0053363000, -0.012641000, -0.055783600, -0.165323300", \ - "0.0208523000, 0.0195630000, 0.0163011000, 0.0090601000, -0.009277400, -0.054286700, -0.163276400"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0366084000, 0.0378584000, 0.0410811000, 0.0484186000, 0.0665173000, 0.1105769000, 0.2187962000", \ - "0.0356844000, 0.0369372000, 0.0401628000, 0.0475692000, 0.0658783000, 0.1101439000, 0.2186712000", \ - "0.0350549000, 0.0363092000, 0.0393303000, 0.0468518000, 0.0649886000, 0.1102637000, 0.2180457000", \ - "0.0344468000, 0.0356742000, 0.0387752000, 0.0459887000, 0.0641212000, 0.1084889000, 0.2175037000", \ - "0.0339981000, 0.0352393000, 0.0382144000, 0.0455060000, 0.0636779000, 0.1078420000, 0.2163901000", \ - "0.0340018000, 0.0351638000, 0.0380815000, 0.0453678000, 0.0633404000, 0.1075580000, 0.2156777000", \ - "0.0352285000, 0.0363529000, 0.0392439000, 0.0462479000, 0.0639143000, 0.1073548000, 0.2166201000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0092062000, 0.0081750000, 0.0056279000, -0.000806200, -0.017496000, -0.060742600, -0.169596700", \ - "0.0092000000, 0.0081644000, 0.0055558000, -0.000816100, -0.017478300, -0.060768200, -0.169606300", \ - "0.0093173000, 0.0082749000, 0.0056680000, -0.000787800, -0.017494700, -0.060702100, -0.169507600", \ - "0.0087908000, 0.0077361000, 0.0051017000, -0.001341800, -0.018013400, -0.061155800, -0.169925400", \ - "0.0078767000, 0.0068459000, 0.0042145000, -0.002238800, -0.018811900, -0.061827700, -0.170288700", \ - "0.0080788000, 0.0069428000, 0.0041166000, -0.002736100, -0.020094800, -0.062722000, -0.170992200", \ - "0.0084863000, 0.0072203000, 0.0043313000, -0.002709700, -0.020172200, -0.063522000, -0.171894800"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504020, 0.0075344330, 0.0186099000, 0.0459660900, 0.1135353000"); - values("0.0341430000, 0.0354103000, 0.0385247000, 0.0460506000, 0.0648989000, 0.1091314000, 0.2180621000", \ - "0.0341404000, 0.0353976000, 0.0384918000, 0.0460953000, 0.0645202000, 0.1092432000, 0.2188019000", \ - "0.0341235000, 0.0353784000, 0.0385049000, 0.0460932000, 0.0644550000, 0.1092774000, 0.2189131000", \ - "0.0335249000, 0.0347343000, 0.0378860000, 0.0453248000, 0.0636197000, 0.1086994000, 0.2179155000", \ - "0.0330880000, 0.0343020000, 0.0373164000, 0.0445386000, 0.0629087000, 0.1075501000, 0.2164799000", \ - "0.0326890000, 0.0338645000, 0.0368853000, 0.0442233000, 0.0619804000, 0.1063979000, 0.2153029000", \ - "0.0336042000, 0.0348294000, 0.0377555000, 0.0446361000, 0.0622101000, 0.1062494000, 0.2152501000"); - } - } - max_capacitance : 0.1135350000; - max_transition : 1.4936780000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0190220000, 0.0198998000, 0.0220757000, 0.0272302000, 0.0392796000, 0.0668758000, 0.1305074000", \ - "0.0244504000, 0.0252791000, 0.0273296000, 0.0323348000, 0.0440878000, 0.0715002000, 0.1349674000", \ - "0.0364463000, 0.0373925000, 0.0396126000, 0.0447100000, 0.0556925000, 0.0824421000, 0.1454633000", \ - "0.0539770000, 0.0553564000, 0.0585656000, 0.0656551000, 0.0807897000, 0.1089785000, 0.1709623000", \ - "0.0759961000, 0.0779775000, 0.0824882000, 0.0922438000, 0.1150999000, 0.1568789000, 0.2303104000", \ - "0.0947094000, 0.0976684000, 0.1046752000, 0.1205142000, 0.1538406000, 0.2168715000, 0.3285837000", \ - "0.0842810000, 0.0887441000, 0.0993147000, 0.1233217000, 0.1724988000, 0.2723542000, 0.4447409000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.2177670000, 0.2244380000, 0.2409266000, 0.2820803000, 0.3804499000, 0.6197703000, 1.2111756000", \ - "0.2200170000, 0.2271414000, 0.2440406000, 0.2850929000, 0.3833915000, 0.6244334000, 1.2166800000", \ - "0.2309873000, 0.2378531000, 0.2545820000, 0.2955319000, 0.3941812000, 0.6362645000, 1.2292695000", \ - "0.2571894000, 0.2636880000, 0.2800163000, 0.3209638000, 0.4211970000, 0.6628620000, 1.2564807000", \ - "0.3112007000, 0.3175821000, 0.3345902000, 0.3746350000, 0.4727276000, 0.7208608000, 1.3126626000", \ - "0.4069903000, 0.4143689000, 0.4328286000, 0.4771079000, 0.5795015000, 0.8215504000, 1.4241772000", \ - "0.5619865000, 0.5713987000, 0.5949027000, 0.6475080000, 0.7676566000, 1.0369414000, 1.6373666000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0217038000, 0.0229255000, 0.0258310000, 0.0328212000, 0.0491690000, 0.0868988000, 0.1754608000", \ - "0.0220346000, 0.0230180000, 0.0256844000, 0.0323352000, 0.0485650000, 0.0864710000, 0.1751917000", \ - "0.0275042000, 0.0283244000, 0.0302947000, 0.0355363000, 0.0494824000, 0.0855314000, 0.1745595000", \ - "0.0412139000, 0.0421976000, 0.0448350000, 0.0499224000, 0.0619803000, 0.0915803000, 0.1745379000", \ - "0.0649435000, 0.0663885000, 0.0698573000, 0.0783694000, 0.0938753000, 0.1244407000, 0.1937385000", \ - "0.1064850000, 0.1086674000, 0.1135568000, 0.1247379000, 0.1474602000, 0.1908074000, 0.2743818000", \ - "0.1793015000, 0.1827597000, 0.1907817000, 0.2091357000, 0.2453509000, 0.3096548000, 0.4253260000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1444006000, 0.1531266000, 0.1739067000, 0.2275191000, 0.3593074000, 0.6812474000, 1.4708169000", \ - "0.1437618000, 0.1526514000, 0.1743053000, 0.2282072000, 0.3587163000, 0.6817812000, 1.4708800000", \ - "0.1440752000, 0.1528300000, 0.1744574000, 0.2280504000, 0.3590217000, 0.6819843000, 1.4718458000", \ - "0.1447721000, 0.1535200000, 0.1741733000, 0.2281439000, 0.3599823000, 0.6820396000, 1.4724514000", \ - "0.1459070000, 0.1541044000, 0.1756087000, 0.2286138000, 0.3590204000, 0.6852168000, 1.4762309000", \ - "0.1673582000, 0.1765024000, 0.1966032000, 0.2459767000, 0.3697301000, 0.6851854000, 1.4819230000", \ - "0.2148652000, 0.2239204000, 0.2453118000, 0.2988337000, 0.4271922000, 0.7308202000, 1.4850724000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0209873000, 0.0219406000, 0.0242269000, 0.0296338000, 0.0419805000, 0.0697622000, 0.1339411000", \ - "0.0262663000, 0.0271002000, 0.0292955000, 0.0345391000, 0.0466393000, 0.0743312000, 0.1382758000", \ - "0.0382489000, 0.0392508000, 0.0413917000, 0.0463650000, 0.0579552000, 0.0851138000, 0.1489716000", \ - "0.0551100000, 0.0564991000, 0.0597674000, 0.0671271000, 0.0820572000, 0.1103033000, 0.1737389000", \ - "0.0738956000, 0.0759325000, 0.0807486000, 0.0915591000, 0.1140576000, 0.1573278000, 0.2321416000", \ - "0.0843680000, 0.0872307000, 0.0940621000, 0.1102351000, 0.1463042000, 0.2121263000, 0.3276684000", \ - "0.0564777000, 0.0612357000, 0.0725211000, 0.0979798000, 0.1517364000, 0.2571939000, 0.4360594000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.2027566000, 0.2095227000, 0.2260106000, 0.2672034000, 0.3668265000, 0.6063223000, 1.1979407000", \ - "0.2033071000, 0.2100819000, 0.2267004000, 0.2686949000, 0.3674362000, 0.6139557000, 1.2015124000", \ - "0.2122932000, 0.2189309000, 0.2356707000, 0.2770221000, 0.3777225000, 0.6248969000, 1.2160665000", \ - "0.2370358000, 0.2438942000, 0.2599997000, 0.3005561000, 0.3995163000, 0.6420993000, 1.2372690000", \ - "0.2900934000, 0.2973583000, 0.3136922000, 0.3541615000, 0.4529855000, 0.6943742000, 1.2888616000", \ - "0.3832514000, 0.3916927000, 0.4117673000, 0.4586463000, 0.5653760000, 0.8075079000, 1.4011338000", \ - "0.5401576000, 0.5514932000, 0.5782723000, 0.6403656000, 0.7735780000, 1.0517081000, 1.6587496000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0226563000, 0.0237033000, 0.0264522000, 0.0328505000, 0.0478991000, 0.0836001000, 0.1707711000", \ - "0.0223188000, 0.0232551000, 0.0258391000, 0.0321029000, 0.0474329000, 0.0833481000, 0.1707668000", \ - "0.0266161000, 0.0272429000, 0.0292273000, 0.0343229000, 0.0477499000, 0.0825304000, 0.1704846000", \ - "0.0394308000, 0.0404020000, 0.0428087000, 0.0479051000, 0.0593953000, 0.0883187000, 0.1703515000", \ - "0.0612904000, 0.0627725000, 0.0662097000, 0.0750832000, 0.0906474000, 0.1213875000, 0.1899574000", \ - "0.1005186000, 0.1030599000, 0.1081553000, 0.1205767000, 0.1436995000, 0.1892258000, 0.2712336000", \ - "0.1708268000, 0.1745195000, 0.1830867000, 0.2024053000, 0.2399731000, 0.3074695000, 0.4264730000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1438758000, 0.1530392000, 0.1747091000, 0.2281514000, 0.3590769000, 0.6822428000, 1.4734780000", \ - "0.1439798000, 0.1531921000, 0.1740389000, 0.2282153000, 0.3590163000, 0.6819689000, 1.4720555000", \ - "0.1440825000, 0.1533100000, 0.1745157000, 0.2280853000, 0.3594655000, 0.6852767000, 1.4767236000", \ - "0.1442375000, 0.1529907000, 0.1751367000, 0.2276527000, 0.3582316000, 0.6816556000, 1.4705623000", \ - "0.1486434000, 0.1568505000, 0.1776655000, 0.2295551000, 0.3598359000, 0.6805698000, 1.4721333000", \ - "0.1803408000, 0.1890756000, 0.2099914000, 0.2578419000, 0.3776837000, 0.6863323000, 1.4723455000", \ - "0.2525249000, 0.2614149000, 0.2817807000, 0.3341342000, 0.4594993000, 0.7486147000, 1.4904202000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0214138000, 0.0222679000, 0.0243254000, 0.0291454000, 0.0402933000, 0.0664479000, 0.1289664000", \ - "0.0261415000, 0.0269709000, 0.0289831000, 0.0337579000, 0.0449115000, 0.0710282000, 0.1336209000", \ - "0.0368430000, 0.0378006000, 0.0400244000, 0.0450160000, 0.0558631000, 0.0818939000, 0.1445156000", \ - "0.0511898000, 0.0526289000, 0.0560012000, 0.0634908000, 0.0787151000, 0.1071193000, 0.1695057000", \ - "0.0649713000, 0.0671791000, 0.0723577000, 0.0838706000, 0.1070692000, 0.1520238000, 0.2279326000", \ - "0.0655620000, 0.0690389000, 0.0771678000, 0.0955974000, 0.1332160000, 0.2018171000, 0.3210063000", \ - "0.0227291000, 0.0281146000, 0.0408591000, 0.0695993000, 0.1286255000, 0.2397215000, 0.4258357000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1632324000, 0.1702423000, 0.1879373000, 0.2285589000, 0.3277938000, 0.5687936000, 1.1609305000", \ - "0.1636029000, 0.1703350000, 0.1879744000, 0.2289315000, 0.3290833000, 0.5716098000, 1.1647855000", \ - "0.1716817000, 0.1784989000, 0.1954075000, 0.2367998000, 0.3358767000, 0.5840121000, 1.1738349000", \ - "0.1957279000, 0.2022661000, 0.2191189000, 0.2590271000, 0.3581463000, 0.6015255000, 1.1968662000", \ - "0.2495613000, 0.2566507000, 0.2736460000, 0.3145064000, 0.4134826000, 0.6547093000, 1.2496016000", \ - "0.3465021000, 0.3557833000, 0.3778335000, 0.4287121000, 0.5416179000, 0.7852683000, 1.3797189000", \ - "0.5117060000, 0.5257477000, 0.5578912000, 0.6306755000, 0.7808232000, 1.0754870000, 1.6873406000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0183264000, 0.0192151000, 0.0215312000, 0.0271167000, 0.0409655000, 0.0746984000, 0.1587006000", \ - "0.0180136000, 0.0189079000, 0.0211387000, 0.0268398000, 0.0407539000, 0.0746231000, 0.1586995000", \ - "0.0225357000, 0.0232587000, 0.0248041000, 0.0292984000, 0.0416084000, 0.0743642000, 0.1585906000", \ - "0.0343242000, 0.0354005000, 0.0378377000, 0.0431829000, 0.0541334000, 0.0811263000, 0.1589914000", \ - "0.0556035000, 0.0571254000, 0.0606428000, 0.0682526000, 0.0847406000, 0.1164339000, 0.1800305000", \ - "0.0934567000, 0.0955722000, 0.1012437000, 0.1134045000, 0.1379439000, 0.1848619000, 0.2652123000", \ - "0.1640681000, 0.1678347000, 0.1764742000, 0.1960744000, 0.2336615000, 0.3032662000, 0.4227903000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1438764000, 0.1520371000, 0.1738949000, 0.2273639000, 0.3583166000, 0.6822101000, 1.4711260000", \ - "0.1441368000, 0.1528984000, 0.1738812000, 0.2274138000, 0.3585917000, 0.6794215000, 1.4711758000", \ - "0.1435348000, 0.1524048000, 0.1738761000, 0.2282091000, 0.3593029000, 0.6860024000, 1.4789852000", \ - "0.1440656000, 0.1528227000, 0.1737970000, 0.2273784000, 0.3586845000, 0.6804701000, 1.4726228000", \ - "0.1536609000, 0.1614546000, 0.1817067000, 0.2321277000, 0.3601242000, 0.6816869000, 1.4750487000", \ - "0.1948519000, 0.2034916000, 0.2245872000, 0.2727853000, 0.3862046000, 0.6869759000, 1.4723261000", \ - "0.2870231000, 0.2970338000, 0.3194756000, 0.3747212000, 0.4971162000, 0.7739629000, 1.4936781000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1049657000, 0.1065145000, 0.1100418000, 0.1177060000, 0.1330479000, 0.1633508000, 0.2271826000", \ - "0.1100521000, 0.1115926000, 0.1151920000, 0.1228230000, 0.1380920000, 0.1684473000, 0.2322706000", \ - "0.1228726000, 0.1243920000, 0.1280027000, 0.1356623000, 0.1510533000, 0.1812499000, 0.2450712000", \ - "0.1531460000, 0.1546722000, 0.1582001000, 0.1659225000, 0.1812460000, 0.2115765000, 0.2755224000", \ - "0.2203262000, 0.2219181000, 0.2256788000, 0.2336193000, 0.2494984000, 0.2803399000, 0.3444867000", \ - "0.3269016000, 0.3289091000, 0.3335327000, 0.3434321000, 0.3626226000, 0.3974659000, 0.4644969000", \ - "0.4830484000, 0.4856231000, 0.4912105000, 0.5044078000, 0.5291084000, 0.5717861000, 0.6464083000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1330785000, 0.1396044000, 0.1553466000, 0.1964676000, 0.2982562000, 0.5434181000, 1.1425277000", \ - "0.1379589000, 0.1441182000, 0.1601667000, 0.2014656000, 0.3027504000, 0.5482253000, 1.1466111000", \ - "0.1492758000, 0.1555509000, 0.1716672000, 0.2122791000, 0.3134087000, 0.5586207000, 1.1585899000", \ - "0.1741412000, 0.1803387000, 0.1961888000, 0.2363731000, 0.3367977000, 0.5842420000, 1.1775885000", \ - "0.2189419000, 0.2247489000, 0.2399257000, 0.2784408000, 0.3777277000, 0.6218357000, 1.2183552000", \ - "0.2817486000, 0.2872219000, 0.3016553000, 0.3394598000, 0.4372541000, 0.6790353000, 1.2764940000", \ - "0.3597995000, 0.3654492000, 0.3794903000, 0.4148921000, 0.5085112000, 0.7500673000, 1.3431389000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.0273159000, 0.0284459000, 0.0304919000, 0.0363460000, 0.0493806000, 0.0796781000, 0.1571535000", \ - "0.0274905000, 0.0284795000, 0.0308185000, 0.0364705000, 0.0492872000, 0.0796627000, 0.1571453000", \ - "0.0272184000, 0.0281950000, 0.0305298000, 0.0362083000, 0.0491551000, 0.0796145000, 0.1570055000", \ - "0.0273206000, 0.0282970000, 0.0306476000, 0.0360623000, 0.0491047000, 0.0797489000, 0.1570192000", \ - "0.0312980000, 0.0321217000, 0.0341953000, 0.0393339000, 0.0515400000, 0.0810649000, 0.1573812000", \ - "0.0443833000, 0.0453788000, 0.0477097000, 0.0534006000, 0.0646552000, 0.0923436000, 0.1633314000", \ - "0.0664640000, 0.0669446000, 0.0699678000, 0.0769884000, 0.0892868000, 0.1155583000, 0.1810952000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012349900, 0.0030504000, 0.0075344300, 0.0186099000, 0.0459661000, 0.1135350000"); - values("0.1293662000, 0.1393586000, 0.1627660000, 0.2207978000, 0.3581302000, 0.6808074000, 1.4759219000", \ - "0.1295572000, 0.1390453000, 0.1627540000, 0.2208739000, 0.3569395000, 0.6808262000, 1.4818010000", \ - "0.1295976000, 0.1394853000, 0.1629574000, 0.2210934000, 0.3569845000, 0.6809475000, 1.4836593000", \ - "0.1288513000, 0.1386870000, 0.1622022000, 0.2201575000, 0.3566594000, 0.6829589000, 1.4778199000", \ - "0.1278568000, 0.1376917000, 0.1613368000, 0.2181915000, 0.3568303000, 0.6817079000, 1.4740067000", \ - "0.1289926000, 0.1380491000, 0.1610442000, 0.2173623000, 0.3553941000, 0.6813205000, 1.4729913000", \ - "0.1365343000, 0.1450520000, 0.1663287000, 0.2187215000, 0.3539017000, 0.6816844000, 1.4725725000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4bb_1") { - leakage_power () { - value : 0.0034182000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0007199000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0062738000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0053254000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0027817000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0006817000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0054229000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0027673000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0028618000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0006972000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0062841000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0028685000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0027625000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0006752000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0049120000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0027447000; - when : "A&B&C_N&!D_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__nor4bb"; - cell_leakage_power : 0.0031998050; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040277000, 0.0040226000, 0.0040110000, 0.0040129000, 0.0040172000, 0.0040273000, 0.0040504000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003522800, -0.003562200, -0.003653000, -0.003665200, -0.003693400, -0.003758400, -0.003908200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024260000; - } - pin ("B") { - capacitance : 0.0023560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043084000, 0.0043049000, 0.0042967000, 0.0042956000, 0.0042931000, 0.0042873000, 0.0042739000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004132100, -0.004157700, -0.004216700, -0.004218600, -0.004222800, -0.004232600, -0.004255200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024950000; - } - pin ("C_N") { - capacitance : 0.0015020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082800000, 0.0081899000, 0.0079824000, 0.0080372000, 0.0081636000, 0.0084549000, 0.0091265000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045812000, 0.0045266000, 0.0044009000, 0.0044475000, 0.0045551000, 0.0048030000, 0.0053744000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015560000; - } - pin ("D_N") { - capacitance : 0.0013900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076430000, 0.0075598000, 0.0073683000, 0.0074332000, 0.0075830000, 0.0079282000, 0.0087239000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027673000, 0.0027079000, 0.0025712000, 0.0026338000, 0.0027780000, 0.0031106000, 0.0038773000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014400000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0058334000, 0.0049802000, 0.0032598000, -0.000251200, -0.007464400, -0.022112500, -0.052183800", \ - "0.0057584000, 0.0049119000, 0.0031826000, -0.000338200, -0.007552500, -0.022218900, -0.052273000", \ - "0.0057597000, 0.0048992000, 0.0031732000, -0.000365400, -0.007592700, -0.022238800, -0.052306000", \ - "0.0055733000, 0.0047322000, 0.0030737000, -0.000439100, -0.007697600, -0.022324500, -0.052392300", \ - "0.0055613000, 0.0047086000, 0.0029740000, -0.000577400, -0.007678700, -0.022361800, -0.052421400", \ - "0.0063230000, 0.0054616000, 0.0038750000, 0.0002775000, -0.007159000, -0.021979000, -0.052270600", \ - "0.0078741000, 0.0070416000, 0.0052394000, 0.0015878000, -0.005705800, -0.020847300, -0.051361600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0141630000, 0.0150381000, 0.0167812000, 0.0203386000, 0.0276320000, 0.0422494000, 0.0722439000", \ - "0.0139910000, 0.0148697000, 0.0166200000, 0.0202078000, 0.0274600000, 0.0423658000, 0.0725176000", \ - "0.0138440000, 0.0147111000, 0.0164573000, 0.0200956000, 0.0273817000, 0.0420803000, 0.0720481000", \ - "0.0137448000, 0.0146011000, 0.0163516000, 0.0198761000, 0.0270956000, 0.0418935000, 0.0719800000", \ - "0.0136716000, 0.0145133000, 0.0162611000, 0.0198111000, 0.0270523000, 0.0417207000, 0.0720922000", \ - "0.0136357000, 0.0144953000, 0.0161938000, 0.0196915000, 0.0268976000, 0.0416760000, 0.0719246000", \ - "0.0133512000, 0.0142055000, 0.0161563000, 0.0197462000, 0.0270246000, 0.0415107000, 0.0715105000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0054980000, 0.0046543000, 0.0029216000, -0.000587700, -0.007759000, -0.022455700, -0.052658600", \ - "0.0054768000, 0.0046313000, 0.0029164000, -0.000617200, -0.007786000, -0.022481500, -0.052667100", \ - "0.0054514000, 0.0046155000, 0.0028972000, -0.000644000, -0.007795500, -0.022482300, -0.052687100", \ - "0.0052635000, 0.0044352000, 0.0027367000, -0.000764800, -0.007866100, -0.022578100, -0.052766100", \ - "0.0053540000, 0.0045133000, 0.0027899000, -0.000762700, -0.007975500, -0.022624600, -0.052797200", \ - "0.0057483000, 0.0049234000, 0.0030161000, -0.000501000, -0.007656600, -0.022393300, -0.052713600", \ - "0.0067235000, 0.0058384000, 0.0040563000, 0.0004390000, -0.006981500, -0.021890800, -0.052380300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0117095000, 0.0126059000, 0.0143852000, 0.0179433000, 0.0251610000, 0.0398835000, 0.0697671000", \ - "0.0115135000, 0.0124013000, 0.0141712000, 0.0177706000, 0.0250505000, 0.0399559000, 0.0698298000", \ - "0.0113739000, 0.0122432000, 0.0139843000, 0.0175796000, 0.0248794000, 0.0398474000, 0.0697458000", \ - "0.0112568000, 0.0121195000, 0.0138484000, 0.0173998000, 0.0246431000, 0.0394518000, 0.0695375000", \ - "0.0111764000, 0.0120261000, 0.0137718000, 0.0173170000, 0.0245691000, 0.0392526000, 0.0693595000", \ - "0.0111657000, 0.0120122000, 0.0137314000, 0.0172405000, 0.0244272000, 0.0391849000, 0.0691633000", \ - "0.0112025000, 0.0120485000, 0.0137663000, 0.0173180000, 0.0246213000, 0.0391926000, 0.0693569000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0047226000, 0.0039689000, 0.0023530000, -0.000966400, -0.008008400, -0.022702100, -0.052932300", \ - "0.0046632000, 0.0038827000, 0.0022873000, -0.001026000, -0.008061500, -0.022742200, -0.052979700", \ - "0.0047145000, 0.0039503000, 0.0023305000, -0.000981700, -0.008020500, -0.022697100, -0.052926300", \ - "0.0044883000, 0.0037152000, 0.0021245000, -0.001178900, -0.008218300, -0.022873500, -0.053098700", \ - "0.0041857000, 0.0034284000, 0.0018245000, -0.001462400, -0.008423500, -0.023033800, -0.053232100", \ - "0.0043285000, 0.0035102000, 0.0021693000, -0.001640400, -0.008787600, -0.023179700, -0.053305500", \ - "0.0049850000, 0.0041489000, 0.0024359000, -0.000969800, -0.008002600, -0.022851400, -0.053078200"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0096367000, 0.0105079000, 0.0123564000, 0.0159339000, 0.0232381000, 0.0379386000, 0.0681524000", \ - "0.0096068000, 0.0104858000, 0.0122854000, 0.0159736000, 0.0232045000, 0.0379658000, 0.0679268000", \ - "0.0095695000, 0.0104625000, 0.0122291000, 0.0158534000, 0.0231356000, 0.0379409000, 0.0679777000", \ - "0.0093034000, 0.0101474000, 0.0119190000, 0.0155192000, 0.0228665000, 0.0376693000, 0.0676951000", \ - "0.0090412000, 0.0098983000, 0.0116768000, 0.0152998000, 0.0225996000, 0.0372984000, 0.0675700000", \ - "0.0089603000, 0.0098190000, 0.0115545000, 0.0151475000, 0.0223450000, 0.0372023000, 0.0672094000", \ - "0.0094035000, 0.0102644000, 0.0120286000, 0.0154633000, 0.0227791000, 0.0374377000, 0.0674891000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0028661000, 0.0021648000, 0.0006227000, -0.002645600, -0.009651500, -0.024302000, -0.054555400", \ - "0.0028071000, 0.0020945000, 0.0005688000, -0.002687600, -0.009689600, -0.024355100, -0.054596600", \ - "0.0028169000, 0.0021033000, 0.0006004000, -0.002662200, -0.009666600, -0.024313500, -0.054558800", \ - "0.0026354000, 0.0019045000, 0.0003779000, -0.002870900, -0.009849300, -0.024500200, -0.054707800", \ - "0.0023173000, 0.0016031000, 0.0001249000, -0.003108000, -0.010031000, -0.024621100, -0.054813600", \ - "0.0025031000, 0.0017005000, 5.540000e-05, -0.003360900, -0.010431400, -0.024841300, -0.054950100", \ - "0.0028758000, 0.0021445000, 0.0003917000, -0.002924200, -0.010279400, -0.024501400, -0.054687000"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010227830, 0.0020921680, 0.0042796660, 0.0087543350, 0.0179075600, 0.0366310800"); - values("0.0084352000, 0.0093250000, 0.0111507000, 0.0147801000, 0.0220909000, 0.0367499000, 0.0668105000", \ - "0.0083893000, 0.0092910000, 0.0111234000, 0.0147993000, 0.0220531000, 0.0369490000, 0.0666871000", \ - "0.0083457000, 0.0092450000, 0.0110238000, 0.0146636000, 0.0219767000, 0.0368114000, 0.0669733000", \ - "0.0079936000, 0.0088824000, 0.0106530000, 0.0142822000, 0.0216858000, 0.0364402000, 0.0665429000", \ - "0.0077858000, 0.0086305000, 0.0103986000, 0.0139951000, 0.0213289000, 0.0360831000, 0.0662323000", \ - "0.0076650000, 0.0085322000, 0.0102902000, 0.0138198000, 0.0210520000, 0.0358891000, 0.0660543000", \ - "0.0080646000, 0.0089123000, 0.0106256000, 0.0141237000, 0.0212492000, 0.0360572000, 0.0661004000"); - } - } - max_capacitance : 0.0366310000; - max_transition : 1.4798240000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0190938000, 0.0212482000, 0.0255232000, 0.0339030000, 0.0501340000, 0.0815503000, 0.1428610000", \ - "0.0245840000, 0.0266164000, 0.0307243000, 0.0389156000, 0.0549770000, 0.0862286000, 0.1474670000", \ - "0.0370947000, 0.0393612000, 0.0435076000, 0.0511962000, 0.0665180000, 0.0973329000, 0.1584251000", \ - "0.0561749000, 0.0593966000, 0.0652261000, 0.0762218000, 0.0939051000, 0.1243462000, 0.1847677000", \ - "0.0817834000, 0.0866008000, 0.0956778000, 0.1113606000, 0.1384793000, 0.1811619000, 0.2453600000", \ - "0.1084912000, 0.1155588000, 0.1280969000, 0.1530382000, 0.1943077000, 0.2606456000, 0.3607868000", \ - "0.1155268000, 0.1265074000, 0.1481144000, 0.1857526000, 0.2490479000, 0.3526046000, 0.5095128000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1834300000, 0.1985314000, 0.2285446000, 0.2904139000, 0.4151522000, 0.6624642000, 1.1731844000", \ - "0.1867246000, 0.2018965000, 0.2318836000, 0.2936832000, 0.4175414000, 0.6743148000, 1.1864507000", \ - "0.1973787000, 0.2124869000, 0.2423160000, 0.3045095000, 0.4294965000, 0.6789815000, 1.1910980000", \ - "0.2220190000, 0.2369547000, 0.2672437000, 0.3281544000, 0.4523540000, 0.7020601000, 1.2144813000", \ - "0.2717197000, 0.2864790000, 0.3166548000, 0.3769645000, 0.5014277000, 0.7505425000, 1.2683428000", \ - "0.3550210000, 0.3724460000, 0.4071799000, 0.4742622000, 0.6004467000, 0.8518168000, 1.3662425000", \ - "0.4841714000, 0.5067636000, 0.5514952000, 0.6336341000, 0.7845579000, 1.0627154000, 1.5793437000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0199718000, 0.0227068000, 0.0281127000, 0.0385168000, 0.0587854000, 0.0978846000, 0.1756329000", \ - "0.0202172000, 0.0226936000, 0.0276889000, 0.0379894000, 0.0582848000, 0.0975296000, 0.1753167000", \ - "0.0257017000, 0.0273244000, 0.0311271000, 0.0397282000, 0.0578899000, 0.0969483000, 0.1752699000", \ - "0.0406576000, 0.0427452000, 0.0470807000, 0.0545603000, 0.0674562000, 0.1003017000, 0.1747166000", \ - "0.0654525000, 0.0687867000, 0.0748659000, 0.0851930000, 0.1043099000, 0.1312971000, 0.1910883000", \ - "0.1078861000, 0.1131112000, 0.1232113000, 0.1388945000, 0.1652311000, 0.2082978000, 0.2734123000", \ - "0.1839601000, 0.1928064000, 0.2073483000, 0.2330561000, 0.2749203000, 0.3402426000, 0.4382752000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1337570000, 0.1531806000, 0.1925829000, 0.2737222000, 0.4392521000, 0.7724744000, 1.4561922000", \ - "0.1338077000, 0.1531039000, 0.1926673000, 0.2736785000, 0.4380653000, 0.7798873000, 1.4704166000", \ - "0.1337550000, 0.1534372000, 0.1927643000, 0.2742421000, 0.4395030000, 0.7742970000, 1.4582687000", \ - "0.1339183000, 0.1535150000, 0.1931110000, 0.2737245000, 0.4385083000, 0.7731220000, 1.4552842000", \ - "0.1375532000, 0.1562420000, 0.1943244000, 0.2737834000, 0.4391402000, 0.7730446000, 1.4674952000", \ - "0.1629494000, 0.1821420000, 0.2204230000, 0.2943987000, 0.4486406000, 0.7781403000, 1.4634360000", \ - "0.2223332000, 0.2411003000, 0.2815372000, 0.3615663000, 0.5190706000, 0.8324915000, 1.4798243000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0206824000, 0.0228566000, 0.0271009000, 0.0353852000, 0.0512843000, 0.0821012000, 0.1430565000", \ - "0.0259255000, 0.0280045000, 0.0321210000, 0.0401774000, 0.0560008000, 0.0867664000, 0.1476883000", \ - "0.0378836000, 0.0401270000, 0.0442960000, 0.0517589000, 0.0671762000, 0.0977731000, 0.1586066000", \ - "0.0553420000, 0.0587454000, 0.0647988000, 0.0751467000, 0.0936457000, 0.1236524000, 0.1840842000", \ - "0.0757181000, 0.0808768000, 0.0903214000, 0.1067655000, 0.1344677000, 0.1781652000, 0.2449553000", \ - "0.0915086000, 0.0988397000, 0.1141035000, 0.1396561000, 0.1819895000, 0.2492087000, 0.3527493000", \ - "0.0781026000, 0.0898413000, 0.1122262000, 0.1512120000, 0.2196637000, 0.3270003000, 0.4884217000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1721425000, 0.1877357000, 0.2185932000, 0.2788188000, 0.4021502000, 0.6527378000, 1.1639557000", \ - "0.1744353000, 0.1897306000, 0.2200845000, 0.2823404000, 0.4063843000, 0.6645193000, 1.1674187000", \ - "0.1845469000, 0.1995826000, 0.2294586000, 0.2912919000, 0.4153992000, 0.6731900000, 1.1874808000", \ - "0.2094386000, 0.2244903000, 0.2540931000, 0.3156871000, 0.4398689000, 0.6948209000, 1.2104540000", \ - "0.2637373000, 0.2790551000, 0.3092220000, 0.3695890000, 0.4944515000, 0.7436840000, 1.2631518000", \ - "0.3586022000, 0.3776470000, 0.4145787000, 0.4838694000, 0.6123557000, 0.8652938000, 1.3749946000", \ - "0.5152776000, 0.5428056000, 0.5939160000, 0.6868245000, 0.8494073000, 1.1333745000, 1.6509583000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0204166000, 0.0229644000, 0.0279120000, 0.0377633000, 0.0569872000, 0.0955670000, 0.1740166000", \ - "0.0201913000, 0.0225446000, 0.0273202000, 0.0372749000, 0.0567896000, 0.0954662000, 0.1736715000", \ - "0.0247160000, 0.0263597000, 0.0301783000, 0.0384894000, 0.0564709000, 0.0950741000, 0.1737164000", \ - "0.0384855000, 0.0406367000, 0.0447069000, 0.0524382000, 0.0656570000, 0.0982739000, 0.1736619000", \ - "0.0619752000, 0.0651844000, 0.0712742000, 0.0833754000, 0.1016402000, 0.1308579000, 0.1904928000", \ - "0.1031106000, 0.1087508000, 0.1173200000, 0.1343911000, 0.1632661000, 0.2098279000, 0.2774492000", \ - "0.1769137000, 0.1853979000, 0.2002880000, 0.2289480000, 0.2724227000, 0.3394907000, 0.4415289000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1334762000, 0.1533391000, 0.1931932000, 0.2733530000, 0.4376653000, 0.7734128000, 1.4576470000", \ - "0.1336861000, 0.1533490000, 0.1925851000, 0.2737367000, 0.4380201000, 0.7804086000, 1.4559022000", \ - "0.1338140000, 0.1530203000, 0.1927784000, 0.2736603000, 0.4384259000, 0.7801474000, 1.4615716000", \ - "0.1340606000, 0.1529672000, 0.1928654000, 0.2736917000, 0.4381424000, 0.7755012000, 1.4620132000", \ - "0.1406833000, 0.1588825000, 0.1963900000, 0.2748755000, 0.4393438000, 0.7730847000, 1.4620789000", \ - "0.1757303000, 0.1947348000, 0.2312193000, 0.3023932000, 0.4529286000, 0.7777019000, 1.4573194000", \ - "0.2602868000, 0.2794778000, 0.3182811000, 0.3945062000, 0.5461737000, 0.8362004000, 1.4774346000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1104536000, 0.1132795000, 0.1186746000, 0.1285477000, 0.1463414000, 0.1785509000, 0.2399215000", \ - "0.1153433000, 0.1181695000, 0.1235656000, 0.1334203000, 0.1511544000, 0.1835342000, 0.2448145000", \ - "0.1277123000, 0.1305495000, 0.1358440000, 0.1459112000, 0.1635872000, 0.1959203000, 0.2572978000", \ - "0.1585329000, 0.1614651000, 0.1667986000, 0.1767418000, 0.1944709000, 0.2269104000, 0.2882956000", \ - "0.2253273000, 0.2283752000, 0.2341131000, 0.2445422000, 0.2626200000, 0.2953243000, 0.3567731000", \ - "0.3328236000, 0.3365367000, 0.3434595000, 0.3556068000, 0.3762067000, 0.4111206000, 0.4747493000", \ - "0.4958923000, 0.5001469000, 0.5098836000, 0.5240900000, 0.5504304000, 0.5912530000, 0.6577812000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1754939000, 0.1905689000, 0.2220003000, 0.2831841000, 0.4076578000, 0.6591224000, 1.1705297000", \ - "0.1796989000, 0.1947525000, 0.2263169000, 0.2889315000, 0.4119090000, 0.6632261000, 1.1744979000", \ - "0.1903606000, 0.2060514000, 0.2361842000, 0.2983972000, 0.4233827000, 0.6775748000, 1.1953363000", \ - "0.2119428000, 0.2270197000, 0.2568450000, 0.3185203000, 0.4430444000, 0.6964029000, 1.2141915000", \ - "0.2424516000, 0.2575160000, 0.2881417000, 0.3497158000, 0.4752173000, 0.7267397000, 1.2388217000", \ - "0.2819293000, 0.2969596000, 0.3268344000, 0.3891296000, 0.5129224000, 0.7640910000, 1.2778268000", \ - "0.3196120000, 0.3344345000, 0.3650386000, 0.4259767000, 0.5505715000, 0.8027749000, 1.3140732000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0305653000, 0.0326936000, 0.0371685000, 0.0463759000, 0.0639723000, 0.1001317000, 0.1757181000", \ - "0.0304150000, 0.0328006000, 0.0372011000, 0.0463266000, 0.0639204000, 0.1000495000, 0.1758448000", \ - "0.0305884000, 0.0327423000, 0.0372485000, 0.0462063000, 0.0640201000, 0.1001193000, 0.1756128000", \ - "0.0302798000, 0.0329870000, 0.0374569000, 0.0464014000, 0.0640241000, 0.1000540000, 0.1756954000", \ - "0.0334556000, 0.0356238000, 0.0399191000, 0.0487622000, 0.0656969000, 0.1009369000, 0.1762953000", \ - "0.0441771000, 0.0464792000, 0.0514838000, 0.0595416000, 0.0760647000, 0.1096851000, 0.1815709000", \ - "0.0615287000, 0.0645096000, 0.0697121000, 0.0802533000, 0.0959842000, 0.1274293000, 0.1944205000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1332793000, 0.1529208000, 0.1930761000, 0.2728272000, 0.4377456000, 0.7730506000, 1.4618894000", \ - "0.1333498000, 0.1527639000, 0.1924043000, 0.2741938000, 0.4377979000, 0.7724161000, 1.4592838000", \ - "0.1333411000, 0.1533052000, 0.1922936000, 0.2738131000, 0.4384168000, 0.7753500000, 1.4618226000", \ - "0.1336286000, 0.1529481000, 0.1925496000, 0.2731373000, 0.4383090000, 0.7751399000, 1.4624116000", \ - "0.1337283000, 0.1531808000, 0.1925953000, 0.2742835000, 0.4398660000, 0.7738496000, 1.4589259000", \ - "0.1344414000, 0.1539988000, 0.1932045000, 0.2746461000, 0.4379419000, 0.7746707000, 1.4582905000", \ - "0.1376809000, 0.1562386000, 0.1947193000, 0.2746166000, 0.4400372000, 0.7745913000, 1.4565485000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0949603000, 0.0981555000, 0.1041297000, 0.1145257000, 0.1328629000, 0.1657691000, 0.2288375000", \ - "0.0996921000, 0.1030078000, 0.1088849000, 0.1193967000, 0.1377287000, 0.1707072000, 0.2337314000", \ - "0.1121037000, 0.1154567000, 0.1213763000, 0.1318959000, 0.1501593000, 0.1830757000, 0.2461406000", \ - "0.1430012000, 0.1462435000, 0.1521998000, 0.1627940000, 0.1812045000, 0.2141839000, 0.2772035000", \ - "0.2071325000, 0.2106408000, 0.2171188000, 0.2282513000, 0.2473076000, 0.2808881000, 0.3439588000", \ - "0.3076863000, 0.3120610000, 0.3198699000, 0.3332138000, 0.3549760000, 0.3908832000, 0.4560313000", \ - "0.4617172000, 0.4670582000, 0.4770232000, 0.4937035000, 0.5206108000, 0.5610995000, 0.6284128000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1150250000, 0.1302205000, 0.1612056000, 0.2235977000, 0.3478808000, 0.6001528000, 1.1097147000", \ - "0.1195969000, 0.1348632000, 0.1658715000, 0.2285010000, 0.3530242000, 0.6057018000, 1.1152289000", \ - "0.1298162000, 0.1449145000, 0.1759264000, 0.2376500000, 0.3631464000, 0.6151623000, 1.1277348000", \ - "0.1486553000, 0.1632492000, 0.1939060000, 0.2556518000, 0.3822096000, 0.6328136000, 1.1452347000", \ - "0.1768051000, 0.1908979000, 0.2209440000, 0.2821952000, 0.4082838000, 0.6594468000, 1.1718905000", \ - "0.2125449000, 0.2261141000, 0.2548841000, 0.3150917000, 0.4389779000, 0.6910022000, 1.2059070000", \ - "0.2467153000, 0.2597958000, 0.2865765000, 0.3447827000, 0.4685607000, 0.7191499000, 1.2306555000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.0254375000, 0.0275702000, 0.0326004000, 0.0417334000, 0.0602398000, 0.0979067000, 0.1778330000", \ - "0.0254427000, 0.0278090000, 0.0326735000, 0.0418311000, 0.0600895000, 0.0977767000, 0.1776616000", \ - "0.0255431000, 0.0278676000, 0.0327436000, 0.0418399000, 0.0602345000, 0.0979914000, 0.1778304000", \ - "0.0256433000, 0.0279896000, 0.0327395000, 0.0420848000, 0.0602293000, 0.0979847000, 0.1780373000", \ - "0.0300132000, 0.0321992000, 0.0368115000, 0.0451181000, 0.0628477000, 0.0994057000, 0.1780152000", \ - "0.0422484000, 0.0441973000, 0.0485349000, 0.0563042000, 0.0732353000, 0.1078899000, 0.1825046000", \ - "0.0600340000, 0.0623061000, 0.0681868000, 0.0766295000, 0.0929869000, 0.1251099000, 0.1943306000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010227800, 0.0020921700, 0.0042796700, 0.0087543400, 0.0179076000, 0.0366311000"); - values("0.1267210000, 0.1477136000, 0.1898150000, 0.2721951000, 0.4371843000, 0.7728129000, 1.4562677000", \ - "0.1265860000, 0.1477458000, 0.1893839000, 0.2729006000, 0.4383036000, 0.7755973000, 1.4607411000", \ - "0.1263309000, 0.1474909000, 0.1890760000, 0.2721373000, 0.4381478000, 0.7745098000, 1.4625497000", \ - "0.1249802000, 0.1461947000, 0.1881129000, 0.2716380000, 0.4385285000, 0.7724221000, 1.4564697000", \ - "0.1241826000, 0.1451697000, 0.1874594000, 0.2711603000, 0.4385605000, 0.7739430000, 1.4573253000", \ - "0.1232848000, 0.1438521000, 0.1860441000, 0.2709331000, 0.4381586000, 0.7738076000, 1.4601259000", \ - "0.1288712000, 0.1473722000, 0.1869099000, 0.2687756000, 0.4385943000, 0.7751567000, 1.4579371000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4bb_2") { - leakage_power () { - value : 0.0050802000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0008941000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0078535000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0063874000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0029295000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0007652000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0068738000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0029257000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0029356000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0007679000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0068746000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0029323000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0030712000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0007259000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0049925000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0028149000; - when : "A&B&C_N&!D_N"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__nor4bb"; - cell_leakage_power : 0.0036765220; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101327000, 0.0101318000, 0.0101298000, 0.0101278000, 0.0101233000, 0.0101128000, 0.0100886000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006812500, -0.006890400, -0.007069800, -0.007088300, -0.007131000, -0.007229500, -0.007456500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045930000; - } - pin ("B") { - capacitance : 0.0043280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082907000, 0.0082925000, 0.0082965000, 0.0083005000, 0.0083097000, 0.0083310000, 0.0083799000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007482000, -0.007523800, -0.007620300, -0.007624200, -0.007633300, -0.007654100, -0.007702300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046270000; - } - pin ("C_N") { - capacitance : 0.0013610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0101479000, 0.0100740000, 0.0099036000, 0.0099457000, 0.0100426000, 0.0102659000, 0.0107808000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083149000, 0.0082730000, 0.0081765000, 0.0082194000, 0.0083182000, 0.0085462000, 0.0090716000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014090000; - } - pin ("D_N") { - capacitance : 0.0014870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0115589000, 0.0114650000, 0.0112486000, 0.0113128000, 0.0114607000, 0.0118016000, 0.0125873000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0057305000, 0.0056822000, 0.0055708000, 0.0056344000, 0.0057810000, 0.0061189000, 0.0068976000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015430000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0046469000, 0.0037914000, 0.0019045000, -0.002381300, -0.012395900, -0.035885400, -0.089373000", \ - "0.0045924000, 0.0037383000, 0.0018357000, -0.002415500, -0.012434100, -0.035917400, -0.089375200", \ - "0.0046648000, 0.0038147000, 0.0019270000, -0.002329900, -0.012369500, -0.035893300, -0.089318900", \ - "0.0043580000, 0.0035633000, 0.0016433000, -0.002637000, -0.012655400, -0.036131600, -0.089530100", \ - "0.0040531000, 0.0031842000, 0.0012814000, -0.002988200, -0.012990500, -0.036389100, -0.089761800", \ - "0.0038222000, 0.0028591000, 0.0007198000, -0.003854100, -0.013612000, -0.036777700, -0.090026100", \ - "0.0060792000, 0.0050299000, 0.0028440000, -0.001994700, -0.012614800, -0.036368500, -0.089789500"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0161465000, 0.0171996000, 0.0194364000, 0.0246722000, 0.0357832000, 0.0599847000, 0.1133350000", \ - "0.0161358000, 0.0171993000, 0.0195241000, 0.0246487000, 0.0356993000, 0.0600137000, 0.1135150000", \ - "0.0161519000, 0.0171984000, 0.0195317000, 0.0245823000, 0.0357283000, 0.0600296000, 0.1133989000", \ - "0.0158119000, 0.0168488000, 0.0191189000, 0.0241998000, 0.0353576000, 0.0595221000, 0.1131197000", \ - "0.0155818000, 0.0165678000, 0.0188191000, 0.0237489000, 0.0348705000, 0.0590358000, 0.1125801000", \ - "0.0153978000, 0.0164052000, 0.0185962000, 0.0234840000, 0.0342837000, 0.0584939000, 0.1121637000", \ - "0.0156748000, 0.0167326000, 0.0188881000, 0.0234889000, 0.0343283000, 0.0584904000, 0.1117673000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0130554000, 0.0121013000, 0.0099012000, 0.0050235000, -0.005794100, -0.029831500, -0.083095100", \ - "0.0128753000, 0.0119110000, 0.0097063000, 0.0048291000, -0.005974300, -0.030001800, -0.083270600", \ - "0.0128316000, 0.0118587000, 0.0096556000, 0.0047544000, -0.006105600, -0.030161300, -0.083384700", \ - "0.0124119000, 0.0114416000, 0.0092559000, 0.0044620000, -0.006404200, -0.030375300, -0.083632700", \ - "0.0121580000, 0.0111833000, 0.0090163000, 0.0042068000, -0.006545100, -0.030500900, -0.083812600", \ - "0.0138350000, 0.0128314000, 0.0105785000, 0.0056272000, -0.005364400, -0.029780000, -0.083501800", \ - "0.0165045000, 0.0154797000, 0.0132048000, 0.0082177000, -0.003073000, -0.027663200, -0.081847800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0260961000, 0.0271266000, 0.0293708000, 0.0343979000, 0.0454376000, 0.0691722000, 0.1226689000", \ - "0.0256985000, 0.0267741000, 0.0290143000, 0.0340812000, 0.0451458000, 0.0690596000, 0.1223484000", \ - "0.0254211000, 0.0264512000, 0.0287017000, 0.0336877000, 0.0448086000, 0.0691258000, 0.1221948000", \ - "0.0252430000, 0.0262428000, 0.0284370000, 0.0333333000, 0.0443324000, 0.0684496000, 0.1219797000", \ - "0.0250453000, 0.0260364000, 0.0282734000, 0.0331745000, 0.0439757000, 0.0680895000, 0.1215237000", \ - "0.0250513000, 0.0260163000, 0.0282395000, 0.0330966000, 0.0439008000, 0.0681397000, 0.1213001000", \ - "0.0250850000, 0.0261151000, 0.0282757000, 0.0332293000, 0.0441445000, 0.0678140000, 0.1213523000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0106470000, 0.0096720000, 0.0074868000, 0.0026134000, -0.008197700, -0.032151400, -0.085680900", \ - "0.0106107000, 0.0096314000, 0.0074445000, 0.0025603000, -0.008226500, -0.032185900, -0.085678000", \ - "0.0105992000, 0.0096111000, 0.0073875000, 0.0025580000, -0.008239200, -0.032190200, -0.085752000", \ - "0.0102550000, 0.0093072000, 0.0071537000, 0.0023370000, -0.008405400, -0.032338400, -0.085850800", \ - "0.0103078000, 0.0093096000, 0.0070939000, 0.0022089000, -0.008628100, -0.032468300, -0.085931200", \ - "0.0111139000, 0.0101005000, 0.0079644000, 0.0031186000, -0.007815600, -0.032102100, -0.085924700", \ - "0.0132851000, 0.0122438000, 0.0099560000, 0.0048718000, -0.006185800, -0.030776800, -0.084793800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0234900000, 0.0245371000, 0.0267987000, 0.0318546000, 0.0429426000, 0.0667390000, 0.1199859000", \ - "0.0230334000, 0.0241156000, 0.0264152000, 0.0314670000, 0.0426293000, 0.0668970000, 0.1198844000", \ - "0.0227397000, 0.0237613000, 0.0260306000, 0.0309561000, 0.0419923000, 0.0663655000, 0.1196992000", \ - "0.0224659000, 0.0234944000, 0.0257416000, 0.0306997000, 0.0417910000, 0.0658100000, 0.1193432000", \ - "0.0222909000, 0.0232994000, 0.0255151000, 0.0304068000, 0.0414127000, 0.0654312000, 0.1188592000", \ - "0.0223477000, 0.0232960000, 0.0255213000, 0.0303773000, 0.0411354000, 0.0653172000, 0.1184543000", \ - "0.0223588000, 0.0233406000, 0.0255343000, 0.0304389000, 0.0415183000, 0.0652034000, 0.1186201000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0098810000, 0.0089794000, 0.0069608000, 0.0024042000, -0.007959800, -0.031743100, -0.085301400", \ - "0.0098579000, 0.0089359000, 0.0068927000, 0.0023419000, -0.008013600, -0.031789400, -0.085343500", \ - "0.0098815000, 0.0089700000, 0.0069365000, 0.0023932000, -0.007988900, -0.031732800, -0.085298700", \ - "0.0096387000, 0.0087271000, 0.0066694000, 0.0021306000, -0.008187900, -0.031928800, -0.085483500", \ - "0.0094541000, 0.0085326000, 0.0064888000, 0.0020155000, -0.008353200, -0.031987500, -0.085541000", \ - "0.0089783000, 0.0080100000, 0.0058541000, 0.0012041000, -0.008864600, -0.032359700, -0.085769700", \ - "0.0104701000, 0.0095210000, 0.0073549000, 0.0025269000, -0.008087300, -0.032098500, -0.085773300"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721550, 0.0054970350, 0.0122231000, 0.0271790400, 0.0604347800"); - values("0.0176914000, 0.0187285000, 0.0210530000, 0.0259861000, 0.0370059000, 0.0614634000, 0.1143692000", \ - "0.0177175000, 0.0187536000, 0.0209894000, 0.0260024000, 0.0369515000, 0.0611414000, 0.1144848000", \ - "0.0176915000, 0.0187436000, 0.0209730000, 0.0259657000, 0.0369619000, 0.0611669000, 0.1147819000", \ - "0.0174320000, 0.0184750000, 0.0206901000, 0.0256608000, 0.0366633000, 0.0609524000, 0.1141884000", \ - "0.0171640000, 0.0181988000, 0.0204327000, 0.0253876000, 0.0364350000, 0.0604071000, 0.1140405000", \ - "0.0170736000, 0.0180829000, 0.0202652000, 0.0251908000, 0.0360706000, 0.0603318000, 0.1137832000", \ - "0.0174424000, 0.0184161000, 0.0205930000, 0.0253983000, 0.0362956000, 0.0603114000, 0.1137185000"); - } - } - max_capacitance : 0.0604350000; - max_transition : 1.4787620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0176752000, 0.0189566000, 0.0217865000, 0.0278480000, 0.0407542000, 0.0678194000, 0.1246771000", \ - "0.0231949000, 0.0243930000, 0.0270729000, 0.0329599000, 0.0456573000, 0.0725329000, 0.1292538000", \ - "0.0351900000, 0.0366346000, 0.0396186000, 0.0456075000, 0.0576053000, 0.0837103000, 0.1400938000", \ - "0.0533536000, 0.0555007000, 0.0597855000, 0.0683217000, 0.0837346000, 0.1110465000, 0.1664622000", \ - "0.0771003000, 0.0801686000, 0.0864105000, 0.0986098000, 0.1226300000, 0.1629390000, 0.2267250000", \ - "0.1000696000, 0.1045912000, 0.1141265000, 0.1324138000, 0.1690816000, 0.2305773000, 0.3303425000", \ - "0.1007273000, 0.1075733000, 0.1219381000, 0.1512738000, 0.2067536000, 0.3027596000, 0.4574700000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.2147116000, 0.2254782000, 0.2480830000, 0.2991541000, 0.4103698000, 0.6542170000, 1.1915806000", \ - "0.2168683000, 0.2278805000, 0.2509350000, 0.3020992000, 0.4150020000, 0.6601271000, 1.1997137000", \ - "0.2278952000, 0.2386838000, 0.2618177000, 0.3126457000, 0.4245837000, 0.6719831000, 1.2134018000", \ - "0.2542134000, 0.2648162000, 0.2868882000, 0.3372126000, 0.4475545000, 0.6920494000, 1.2324353000", \ - "0.3065249000, 0.3172422000, 0.3394917000, 0.3894763000, 0.4990909000, 0.7425418000, 1.2819467000", \ - "0.3973165000, 0.4087179000, 0.4344674000, 0.4883762000, 0.6017478000, 0.8457612000, 1.3835924000", \ - "0.5404337000, 0.5562378000, 0.5864045000, 0.6514106000, 0.7836766000, 1.0524241000, 1.5986078000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0185520000, 0.0202838000, 0.0240279000, 0.0319445000, 0.0483731000, 0.0827008000, 0.1551451000", \ - "0.0193525000, 0.0208540000, 0.0240905000, 0.0315834000, 0.0478782000, 0.0823166000, 0.1546720000", \ - "0.0259642000, 0.0268629000, 0.0291950000, 0.0348113000, 0.0488036000, 0.0815563000, 0.1545564000", \ - "0.0411375000, 0.0424939000, 0.0452409000, 0.0510847000, 0.0613218000, 0.0872438000, 0.1541346000", \ - "0.0665903000, 0.0685522000, 0.0725427000, 0.0812667000, 0.0960769000, 0.1227990000, 0.1749730000", \ - "0.1098566000, 0.1130181000, 0.1193898000, 0.1324122000, 0.1544603000, 0.1948670000, 0.2597102000", \ - "0.1854790000, 0.1907075000, 0.2012250000, 0.2210518000, 0.2571032000, 0.3186075000, 0.4137807000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1452965000, 0.1589922000, 0.1891828000, 0.2571378000, 0.4063865000, 0.7339233000, 1.4616487000", \ - "0.1450341000, 0.1588939000, 0.1892112000, 0.2571171000, 0.4063709000, 0.7348443000, 1.4629983000", \ - "0.1453917000, 0.1590196000, 0.1894696000, 0.2570975000, 0.4062731000, 0.7373867000, 1.4632946000", \ - "0.1456235000, 0.1592487000, 0.1894890000, 0.2565957000, 0.4052065000, 0.7320088000, 1.4586523000", \ - "0.1473834000, 0.1607583000, 0.1905695000, 0.2569266000, 0.4048894000, 0.7326972000, 1.4599235000", \ - "0.1691808000, 0.1822312000, 0.2111729000, 0.2740574000, 0.4142482000, 0.7364914000, 1.4575305000", \ - "0.2175705000, 0.2315314000, 0.2618019000, 0.3287966000, 0.4732146000, 0.7798474000, 1.4745021000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0194549000, 0.0208378000, 0.0238064000, 0.0301019000, 0.0431968000, 0.0703471000, 0.1275783000", \ - "0.0248740000, 0.0261741000, 0.0290192000, 0.0350369000, 0.0479744000, 0.0750248000, 0.1322532000", \ - "0.0368530000, 0.0382977000, 0.0413926000, 0.0473108000, 0.0595901000, 0.0861522000, 0.1431934000", \ - "0.0547447000, 0.0568051000, 0.0611193000, 0.0696953000, 0.0851292000, 0.1125535000, 0.1689226000", \ - "0.0762667000, 0.0793533000, 0.0858318000, 0.0984187000, 0.1224486000, 0.1636132000, 0.2298536000", \ - "0.0931203000, 0.0978211000, 0.1075837000, 0.1273123000, 0.1650997000, 0.2290921000, 0.3318119000", \ - "0.0836429000, 0.0910084000, 0.1064226000, 0.1370859000, 0.1943227000, 0.2949863000, 0.4558104000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1987626000, 0.2096060000, 0.2324196000, 0.2837694000, 0.3953582000, 0.6410917000, 1.1797515000", \ - "0.1994153000, 0.2105081000, 0.2339240000, 0.2855083000, 0.3976471000, 0.6445757000, 1.1846105000", \ - "0.2089389000, 0.2196683000, 0.2426591000, 0.2928179000, 0.4060929000, 0.6497156000, 1.1966591000", \ - "0.2323279000, 0.2428088000, 0.2659059000, 0.3163440000, 0.4278796000, 0.6712976000, 1.2127013000", \ - "0.2824361000, 0.2927489000, 0.3158318000, 0.3657030000, 0.4765343000, 0.7201219000, 1.2603036000", \ - "0.3689063000, 0.3819048000, 0.4092406000, 0.4667620000, 0.5837240000, 0.8276225000, 1.3685409000", \ - "0.5122324000, 0.5292894000, 0.5657231000, 0.6423578000, 0.7864104000, 1.0622855000, 1.6123514000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0198325000, 0.0214633000, 0.0250822000, 0.0326733000, 0.0484301000, 0.0819377000, 0.1551567000", \ - "0.0198846000, 0.0213146000, 0.0246855000, 0.0320620000, 0.0480843000, 0.0815530000, 0.1547108000", \ - "0.0251609000, 0.0261465000, 0.0284393000, 0.0343017000, 0.0482893000, 0.0811089000, 0.1548627000", \ - "0.0391023000, 0.0404270000, 0.0433095000, 0.0488990000, 0.0599084000, 0.0862439000, 0.1549234000", \ - "0.0630138000, 0.0650687000, 0.0692767000, 0.0779394000, 0.0926561000, 0.1211408000, 0.1746895000", \ - "0.1031743000, 0.1066605000, 0.1136469000, 0.1267254000, 0.1505695000, 0.1910411000, 0.2582199000", \ - "0.1762618000, 0.1816586000, 0.1926208000, 0.2140042000, 0.2517687000, 0.3146839000, 0.4178901000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1452365000, 0.1589302000, 0.1891239000, 0.2571119000, 0.4064096000, 0.7349427000, 1.4629516000", \ - "0.1449513000, 0.1588333000, 0.1891736000, 0.2568280000, 0.4063371000, 0.7369494000, 1.4628083000", \ - "0.1454311000, 0.1591058000, 0.1893589000, 0.2561186000, 0.4053063000, 0.7334258000, 1.4634807000", \ - "0.1462959000, 0.1590554000, 0.1895817000, 0.2569168000, 0.4062723000, 0.7321100000, 1.4589258000", \ - "0.1505993000, 0.1637559000, 0.1926461000, 0.2581849000, 0.4057920000, 0.7332882000, 1.4586663000", \ - "0.1819005000, 0.1957987000, 0.2247630000, 0.2854759000, 0.4217635000, 0.7385427000, 1.4595356000", \ - "0.2543290000, 0.2683023000, 0.2974077000, 0.3646694000, 0.5038984000, 0.7993101000, 1.4787620000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1428356000, 0.1448874000, 0.1492108000, 0.1579535000, 0.1746564000, 0.2058274000, 0.2663680000", \ - "0.1475708000, 0.1496479000, 0.1539974000, 0.1627279000, 0.1795162000, 0.2106715000, 0.2711610000", \ - "0.1602439000, 0.1623194000, 0.1666617000, 0.1754012000, 0.1919865000, 0.2233946000, 0.2838799000", \ - "0.1905208000, 0.1926075000, 0.1968658000, 0.2056129000, 0.2224269000, 0.2537684000, 0.3142870000", \ - "0.2618425000, 0.2638716000, 0.2682206000, 0.2771198000, 0.2938502000, 0.3253065000, 0.3857480000", \ - "0.3915111000, 0.3939933000, 0.3991694000, 0.4094240000, 0.4284565000, 0.4623205000, 0.5248691000", \ - "0.5885104000, 0.5916374000, 0.5982456000, 0.6106736000, 0.6346614000, 0.6750705000, 0.7433330000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.2019255000, 0.2124187000, 0.2361443000, 0.2862388000, 0.3976548000, 0.6454236000, 1.1802543000", \ - "0.2069772000, 0.2176977000, 0.2403881000, 0.2915778000, 0.4026316000, 0.6471761000, 1.1864514000", \ - "0.2179008000, 0.2289648000, 0.2517304000, 0.3029803000, 0.4142659000, 0.6587347000, 1.1974138000", \ - "0.2424266000, 0.2533977000, 0.2759981000, 0.3268553000, 0.4377471000, 0.6820215000, 1.2221321000", \ - "0.2818926000, 0.2926031000, 0.3155978000, 0.3664016000, 0.4784604000, 0.7245452000, 1.2617118000", \ - "0.3344487000, 0.3447777000, 0.3673536000, 0.4175014000, 0.5283474000, 0.7744859000, 1.3127668000", \ - "0.3921380000, 0.4026153000, 0.4257068000, 0.4765299000, 0.5878271000, 0.8303189000, 1.3695972000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0381488000, 0.0396004000, 0.0425590000, 0.0494433000, 0.0641083000, 0.0951074000, 0.1646918000", \ - "0.0377411000, 0.0392757000, 0.0424894000, 0.0497445000, 0.0640401000, 0.0951562000, 0.1650064000", \ - "0.0382191000, 0.0396377000, 0.0427194000, 0.0496748000, 0.0640969000, 0.0950856000, 0.1650014000", \ - "0.0377094000, 0.0396415000, 0.0425346000, 0.0497800000, 0.0640647000, 0.0950616000, 0.1648913000", \ - "0.0386092000, 0.0406125000, 0.0434238000, 0.0505287000, 0.0651055000, 0.0956278000, 0.1649443000", \ - "0.0506920000, 0.0522613000, 0.0555606000, 0.0620269000, 0.0758324000, 0.1046651000, 0.1708779000", \ - "0.0696724000, 0.0718883000, 0.0755535000, 0.0837027000, 0.0996344000, 0.1262693000, 0.1884907000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1455325000, 0.1592230000, 0.1893948000, 0.2561817000, 0.4046511000, 0.7366653000, 1.4664787000", \ - "0.1447890000, 0.1586768000, 0.1889807000, 0.2563730000, 0.4042136000, 0.7323038000, 1.4586988000", \ - "0.1448308000, 0.1584561000, 0.1889778000, 0.2563272000, 0.4053617000, 0.7332383000, 1.4613301000", \ - "0.1448435000, 0.1584799000, 0.1889845000, 0.2563606000, 0.4053734000, 0.7339030000, 1.4586803000", \ - "0.1451589000, 0.1587199000, 0.1892569000, 0.2565297000, 0.4061340000, 0.7347490000, 1.4599060000", \ - "0.1466509000, 0.1595202000, 0.1899053000, 0.2571213000, 0.4046534000, 0.7339426000, 1.4603811000", \ - "0.1494633000, 0.1629997000, 0.1920547000, 0.2586191000, 0.4065290000, 0.7324154000, 1.4590765000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1382985000, 0.1409798000, 0.1464573000, 0.1568530000, 0.1756099000, 0.2088867000, 0.2707981000", \ - "0.1432512000, 0.1459403000, 0.1514234000, 0.1619015000, 0.1807634000, 0.2137864000, 0.2756742000", \ - "0.1555876000, 0.1582637000, 0.1637850000, 0.1743213000, 0.1930889000, 0.2261689000, 0.2879396000", \ - "0.1861237000, 0.1888034000, 0.1942846000, 0.2047178000, 0.2235483000, 0.2568254000, 0.3185961000", \ - "0.2580362000, 0.2607399000, 0.2661527000, 0.2766226000, 0.2954886000, 0.3289036000, 0.3908896000", \ - "0.3885676000, 0.3917782000, 0.3983010000, 0.4106874000, 0.4321704000, 0.4687009000, 0.5333812000", \ - "0.5878392000, 0.5919797000, 0.6003722000, 0.6163217000, 0.6438549000, 0.6880076000, 0.7590660000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1324294000, 0.1420811000, 0.1642478000, 0.2161408000, 0.3287222000, 0.5736663000, 1.1144060000", \ - "0.1373876000, 0.1470416000, 0.1696422000, 0.2210804000, 0.3329917000, 0.5803314000, 1.1193511000", \ - "0.1486709000, 0.1586475000, 0.1810866000, 0.2314403000, 0.3441106000, 0.5903104000, 1.1294057000", \ - "0.1731610000, 0.1827125000, 0.2046969000, 0.2552152000, 0.3675517000, 0.6146185000, 1.1544202000", \ - "0.2160665000, 0.2250908000, 0.2464423000, 0.2960229000, 0.4077834000, 0.6518924000, 1.1970814000", \ - "0.2747631000, 0.2833004000, 0.3035463000, 0.3514312000, 0.4609947000, 0.7049211000, 1.2458674000", \ - "0.3439927000, 0.3527471000, 0.3721886000, 0.4167289000, 0.5246831000, 0.7687639000, 1.3068794000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.0343779000, 0.0360940000, 0.0396919000, 0.0469728000, 0.0623746000, 0.0934824000, 0.1629978000", \ - "0.0341565000, 0.0357932000, 0.0392933000, 0.0466632000, 0.0621169000, 0.0935520000, 0.1628095000", \ - "0.0344467000, 0.0361759000, 0.0395116000, 0.0465888000, 0.0620955000, 0.0935993000, 0.1627339000", \ - "0.0341961000, 0.0358934000, 0.0394245000, 0.0468192000, 0.0620671000, 0.0935335000, 0.1625357000", \ - "0.0356675000, 0.0370001000, 0.0403739000, 0.0480567000, 0.0630416000, 0.0938911000, 0.1627759000", \ - "0.0486820000, 0.0503768000, 0.0539101000, 0.0609861000, 0.0748165000, 0.1039523000, 0.1686711000", \ - "0.0725654000, 0.0737822000, 0.0791750000, 0.0858142000, 0.1003715000, 0.1281036000, 0.1885893000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011117900, 0.0024721500, 0.0054970400, 0.0122231000, 0.0271790000, 0.0604348000"); - values("0.1308353000, 0.1460328000, 0.1790104000, 0.2514397000, 0.4046619000, 0.7325839000, 1.4602776000", \ - "0.1313148000, 0.1460454000, 0.1793808000, 0.2515627000, 0.4036064000, 0.7330344000, 1.4586881000", \ - "0.1311450000, 0.1464976000, 0.1793580000, 0.2514144000, 0.4044770000, 0.7332348000, 1.4592773000", \ - "0.1303538000, 0.1450360000, 0.1782704000, 0.2506405000, 0.4041312000, 0.7329738000, 1.4589495000", \ - "0.1294508000, 0.1448858000, 0.1770128000, 0.2493026000, 0.4041959000, 0.7326632000, 1.4603424000", \ - "0.1304832000, 0.1448330000, 0.1764144000, 0.2474788000, 0.4022508000, 0.7330663000, 1.4566738000", \ - "0.1387817000, 0.1520135000, 0.1814622000, 0.2475506000, 0.4011234000, 0.7353543000, 1.4573845000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__nor4bb_4") { - leakage_power () { - value : 0.0064806000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0008563000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0160276000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0079382000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0041123000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0007194000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0096319000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0040918000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0041026000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0030763000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0094708000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0040826000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0043587000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0240213000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0705719000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0275975000; - when : "A&B&C_N&!D_N"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__nor4bb"; - cell_leakage_power : 0.0123212400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0180145000, 0.0180200000, 0.0180324000, 0.0180249000, 0.0180075000, 0.0179676000, 0.0178756000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013499500, -0.013645800, -0.013983000, -0.014028500, -0.014133300, -0.014375000, -0.014932000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091020000; - } - pin ("B") { - capacitance : 0.0085340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0164138000, 0.0164108000, 0.0164037000, 0.0164099000, 0.0164243000, 0.0164574000, 0.0165338000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014983700, -0.015078900, -0.015298300, -0.015311200, -0.015340900, -0.015409400, -0.015567300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091220000; - } - pin ("C_N") { - capacitance : 0.0023790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0202468000, 0.0201320000, 0.0198674000, 0.0200102000, 0.0203392000, 0.0210977000, 0.0228461000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161162000, 0.0160346000, 0.0158465000, 0.0159151000, 0.0160733000, 0.0164378000, 0.0172782000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025030000; - } - pin ("D_N") { - capacitance : 0.0023990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0211021000, 0.0209580000, 0.0206258000, 0.0207583000, 0.0210640000, 0.0217687000, 0.0233929000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0125330000, 0.0124316000, 0.0121978000, 0.0123131000, 0.0125789000, 0.0131914000, 0.0146036000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025190000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B&C_N&D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0261679000, 0.0250024000, 0.0220948000, 0.0149223000, -0.002717400, -0.046085400, -0.152557200", \ - "0.0258397000, 0.0246402000, 0.0217401000, 0.0145954000, -0.003015100, -0.046412200, -0.152875600", \ - "0.0257137000, 0.0245035000, 0.0215588000, 0.0144132000, -0.003311700, -0.046627500, -0.153090500", \ - "0.0248968000, 0.0237243000, 0.0210457000, 0.0138277000, -0.003761900, -0.047076200, -0.153614500", \ - "0.0246038000, 0.0234193000, 0.0207173000, 0.0137366000, -0.003858700, -0.047089200, -0.153574400", \ - "0.0261879000, 0.0249925000, 0.0219811000, 0.0147275000, -0.003114000, -0.046657000, -0.153198500", \ - "0.0322499000, 0.0310570000, 0.0280373000, 0.0207550000, 0.0017578000, -0.041477000, -0.150172000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0534110000, 0.0546923000, 0.0576785000, 0.0648636000, 0.0825285000, 0.1257510000, 0.2320316000", \ - "0.0527235000, 0.0539763000, 0.0569537000, 0.0643451000, 0.0823640000, 0.1253644000, 0.2317544000", \ - "0.0520301000, 0.0532133000, 0.0562717000, 0.0636901000, 0.0814571000, 0.1250755000, 0.2314988000", \ - "0.0516156000, 0.0528892000, 0.0558583000, 0.0631309000, 0.0810942000, 0.1245538000, 0.2310087000", \ - "0.0512835000, 0.0524282000, 0.0554257000, 0.0625873000, 0.0804880000, 0.1236463000, 0.2303736000", \ - "0.0511220000, 0.0523338000, 0.0552533000, 0.0624708000, 0.0799908000, 0.1237299000, 0.2304662000", \ - "0.0513220000, 0.0525063000, 0.0554073000, 0.0626977000, 0.0804382000, 0.1232429000, 0.2302954000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0218480000, 0.0206727000, 0.0177677000, 0.0106091000, -0.007001100, -0.050254000, -0.157074300", \ - "0.0217722000, 0.0205839000, 0.0176845000, 0.0105275000, -0.007083700, -0.050316500, -0.157135900", \ - "0.0217595000, 0.0205700000, 0.0176557000, 0.0104680000, -0.007109500, -0.050334100, -0.157097900", \ - "0.0211102000, 0.0199581000, 0.0171279000, 0.0099796000, -0.007548200, -0.050592900, -0.157396500", \ - "0.0206259000, 0.0194547000, 0.0165901000, 0.0095802000, -0.007644500, -0.050641700, -0.157370600", \ - "0.0223129000, 0.0211267000, 0.0182243000, 0.0112374000, -0.006653800, -0.050341400, -0.157520800", \ - "0.0266076000, 0.0253548000, 0.0224697000, 0.0151410000, -0.003019300, -0.047555300, -0.155664600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0465409000, 0.0477125000, 0.0507351000, 0.0580684000, 0.0758054000, 0.1190535000, 0.2253513000", \ - "0.0456093000, 0.0468452000, 0.0499532000, 0.0572995000, 0.0752404000, 0.1187728000, 0.2264469000", \ - "0.0448928000, 0.0461073000, 0.0491139000, 0.0564837000, 0.0744696000, 0.1181535000, 0.2248308000", \ - "0.0444748000, 0.0456831000, 0.0486635000, 0.0558218000, 0.0737406000, 0.1173707000, 0.2248700000", \ - "0.0440403000, 0.0452195000, 0.0481356000, 0.0553489000, 0.0732214000, 0.1164868000, 0.2235607000", \ - "0.0438194000, 0.0450381000, 0.0479274000, 0.0551583000, 0.0727041000, 0.1163733000, 0.2223363000", \ - "0.0439871000, 0.0451738000, 0.0480537000, 0.0552810000, 0.0730318000, 0.1161129000, 0.2225080000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0195589000, 0.0184459000, 0.0157179000, 0.0089547000, -0.007888400, -0.050490000, -0.157401400", \ - "0.0194900000, 0.0183854000, 0.0156681000, 0.0089149000, -0.007888100, -0.050542300, -0.157427700", \ - "0.0195177000, 0.0183844000, 0.0156792000, 0.0089567000, -0.007865900, -0.050477800, -0.157353300", \ - "0.0190319000, 0.0179285000, 0.0152006000, 0.0084671000, -0.008276700, -0.050891400, -0.157690100", \ - "0.0181765000, 0.0171577000, 0.0144355000, 0.0077148000, -0.009036900, -0.051461300, -0.158165600", \ - "0.0164977000, 0.0154349000, 0.0126764000, 0.0059202000, -0.010170900, -0.052212900, -0.158720000", \ - "0.0190230000, 0.0178530000, 0.0149901000, 0.0078374000, -0.009486000, -0.052434300, -0.159412100"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0362399000, 0.0374740000, 0.0406211000, 0.0479483000, 0.0660662000, 0.1097450000, 0.2169569000", \ - "0.0362335000, 0.0374602000, 0.0405980000, 0.0479196000, 0.0663429000, 0.1099798000, 0.2164253000", \ - "0.0362844000, 0.0375254000, 0.0404831000, 0.0479865000, 0.0659587000, 0.1096050000, 0.2163765000", \ - "0.0357389000, 0.0369485000, 0.0400459000, 0.0474173000, 0.0655446000, 0.1093947000, 0.2159267000", \ - "0.0351878000, 0.0364889000, 0.0394553000, 0.0467605000, 0.0644885000, 0.1086132000, 0.2151738000", \ - "0.0347115000, 0.0359574000, 0.0388297000, 0.0460475000, 0.0638305000, 0.1074673000, 0.2142191000", \ - "0.0354971000, 0.0366985000, 0.0395613000, 0.0465756000, 0.0642266000, 0.1076947000, 0.2145201000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0093471000, 0.0083043000, 0.0058231000, -0.000578400, -0.016936700, -0.059252400, -0.165990300", \ - "0.0093417000, 0.0082825000, 0.0057503000, -0.000603300, -0.016904500, -0.059256100, -0.166070400", \ - "0.0093411000, 0.0083003000, 0.0057671000, -0.000538000, -0.016843500, -0.059160200, -0.165967900", \ - "0.0088862000, 0.0078558000, 0.0053040000, -0.001053200, -0.017420100, -0.059605000, -0.166291500", \ - "0.0081705000, 0.0071123000, 0.0045069000, -0.001869300, -0.018119900, -0.060196600, -0.166764500", \ - "0.0079082000, 0.0067658000, 0.0039487000, -0.002898200, -0.019455800, -0.060961200, -0.167218600", \ - "0.0097787000, 0.0086025000, 0.0056479000, -0.001320100, -0.018630300, -0.061325700, -0.167798400"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012316480, 0.0030339140, 0.0074734290, 0.0184092700, 0.0453474900, 0.1117043000"); - values("0.0287490000, 0.0300330000, 0.0329841000, 0.0406089000, 0.0589589000, 0.1026691000, 0.2096025000", \ - "0.0286431000, 0.0298961000, 0.0329920000, 0.0405561000, 0.0587851000, 0.1027750000, 0.2106404000", \ - "0.0287618000, 0.0299764000, 0.0331221000, 0.0405564000, 0.0588297000, 0.1028085000, 0.2094121000", \ - "0.0280538000, 0.0293160000, 0.0324022000, 0.0398925000, 0.0580351000, 0.1021391000, 0.2087720000", \ - "0.0277042000, 0.0289314000, 0.0319079000, 0.0390746000, 0.0571769000, 0.1008285000, 0.2086883000", \ - "0.0273099000, 0.0284859000, 0.0314317000, 0.0386660000, 0.0562420000, 0.0998883000, 0.2069987000", \ - "0.0279883000, 0.0291622000, 0.0319748000, 0.0388397000, 0.0561379000, 0.0998090000, 0.2065034000"); - } - } - max_capacitance : 0.1117040000; - max_transition : 1.4977500000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0184547000, 0.0193525000, 0.0214495000, 0.0265288000, 0.0383737000, 0.0656831000, 0.1285700000", \ - "0.0238937000, 0.0247033000, 0.0267149000, 0.0315619000, 0.0431893000, 0.0702940000, 0.1330378000", \ - "0.0355958000, 0.0365624000, 0.0388478000, 0.0439119000, 0.0548316000, 0.0812620000, 0.1435396000", \ - "0.0529441000, 0.0543569000, 0.0571905000, 0.0648571000, 0.0798394000, 0.1079226000, 0.1691643000", \ - "0.0749583000, 0.0769440000, 0.0815199000, 0.0912329000, 0.1140006000, 0.1554430000, 0.2283298000", \ - "0.0936779000, 0.0966313000, 0.1034180000, 0.1192083000, 0.1529333000, 0.2151383000, 0.3256075000", \ - "0.0835856000, 0.0880136000, 0.0986038000, 0.1222146000, 0.1710587000, 0.2687032000, 0.4407061000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.2256218000, 0.2329843000, 0.2502770000, 0.2901171000, 0.3882226000, 0.6294515000, 1.2148484000", \ - "0.2283594000, 0.2353955000, 0.2523705000, 0.2941388000, 0.3937782000, 0.6350260000, 1.2202764000", \ - "0.2389644000, 0.2457694000, 0.2629999000, 0.3043217000, 0.4031484000, 0.6455798000, 1.2329336000", \ - "0.2647561000, 0.2718177000, 0.2890294000, 0.3295807000, 0.4293915000, 0.6698837000, 1.2592665000", \ - "0.3185872000, 0.3251584000, 0.3423632000, 0.3824857000, 0.4816801000, 0.7213172000, 1.3104065000", \ - "0.4139171000, 0.4212542000, 0.4404831000, 0.4844645000, 0.5865903000, 0.8278053000, 1.4250241000", \ - "0.5708014000, 0.5799626000, 0.6021708000, 0.6557005000, 0.7746663000, 1.0417400000, 1.6381834000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0217909000, 0.0229684000, 0.0258597000, 0.0328726000, 0.0493271000, 0.0871695000, 0.1745460000", \ - "0.0222206000, 0.0233731000, 0.0260131000, 0.0326124000, 0.0488550000, 0.0867425000, 0.1742300000", \ - "0.0282124000, 0.0289944000, 0.0309758000, 0.0362629000, 0.0500315000, 0.0857761000, 0.1737944000", \ - "0.0428039000, 0.0437935000, 0.0466004000, 0.0510515000, 0.0629951000, 0.0922437000, 0.1737018000", \ - "0.0669909000, 0.0688737000, 0.0721992000, 0.0803523000, 0.0949520000, 0.1256818000, 0.1932632000", \ - "0.1098938000, 0.1120065000, 0.1169593000, 0.1276202000, 0.1498154000, 0.1937617000, 0.2740315000", \ - "0.1844097000, 0.1879475000, 0.1955946000, 0.2141893000, 0.2486453000, 0.3120978000, 0.4248909000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1495676000, 0.1583462000, 0.1803900000, 0.2339718000, 0.3660098000, 0.6885191000, 1.4779047000", \ - "0.1498579000, 0.1587616000, 0.1808248000, 0.2344202000, 0.3666465000, 0.6892563000, 1.4776750000", \ - "0.1506326000, 0.1594747000, 0.1806076000, 0.2347085000, 0.3657427000, 0.6883629000, 1.4779945000", \ - "0.1497946000, 0.1587753000, 0.1806974000, 0.2346482000, 0.3668505000, 0.6884196000, 1.4778316000", \ - "0.1515807000, 0.1602357000, 0.1817111000, 0.2348451000, 0.3665008000, 0.6871645000, 1.4796631000", \ - "0.1732313000, 0.1816650000, 0.2016793000, 0.2511524000, 0.3757037000, 0.6920851000, 1.4841677000", \ - "0.2190536000, 0.2277447000, 0.2504828000, 0.3035239000, 0.4329916000, 0.7369411000, 1.4944760000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0204359000, 0.0213706000, 0.0236499000, 0.0289585000, 0.0411123000, 0.0688303000, 0.1326077000", \ - "0.0256465000, 0.0265463000, 0.0286831000, 0.0337717000, 0.0457590000, 0.0733952000, 0.1370919000", \ - "0.0373573000, 0.0383156000, 0.0407231000, 0.0458060000, 0.0571460000, 0.0841990000, 0.1476463000", \ - "0.0540458000, 0.0554443000, 0.0587482000, 0.0662181000, 0.0811998000, 0.1096229000, 0.1725611000", \ - "0.0731142000, 0.0752060000, 0.0800899000, 0.0907891000, 0.1132390000, 0.1561425000, 0.2310250000", \ - "0.0836411000, 0.0867944000, 0.0934156000, 0.1096756000, 0.1454562000, 0.2116353000, 0.3269398000", \ - "0.0572767000, 0.0614265000, 0.0720858000, 0.0982888000, 0.1515317000, 0.2556568000, 0.4346900000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.2112975000, 0.2181605000, 0.2348600000, 0.2766070000, 0.3753152000, 0.6139565000, 1.2006127000", \ - "0.2115915000, 0.2184591000, 0.2361095000, 0.2775089000, 0.3772114000, 0.6171512000, 1.2130872000", \ - "0.2201595000, 0.2268940000, 0.2439320000, 0.2858883000, 0.3851272000, 0.6268720000, 1.2158131000", \ - "0.2443144000, 0.2514553000, 0.2684635000, 0.3084566000, 0.4075039000, 0.6514520000, 1.2404482000", \ - "0.2962635000, 0.3033287000, 0.3197506000, 0.3604549000, 0.4600144000, 0.7014335000, 1.2945964000", \ - "0.3889258000, 0.3970314000, 0.4168410000, 0.4643156000, 0.5706027000, 0.8119110000, 1.4026936000", \ - "0.5450878000, 0.5563887000, 0.5830235000, 0.6448836000, 0.7763231000, 1.0544442000, 1.6561306000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0223661000, 0.0234538000, 0.0262372000, 0.0327377000, 0.0480283000, 0.0839765000, 0.1708084000", \ - "0.0222914000, 0.0232912000, 0.0258529000, 0.0321138000, 0.0476157000, 0.0837900000, 0.1706818000", \ - "0.0271328000, 0.0279898000, 0.0297411000, 0.0347489000, 0.0481887000, 0.0830143000, 0.1703890000", \ - "0.0405986000, 0.0415975000, 0.0440347000, 0.0490527000, 0.0605313000, 0.0891794000, 0.1702518000", \ - "0.0634968000, 0.0647864000, 0.0685969000, 0.0766760000, 0.0920999000, 0.1228224000, 0.1900133000", \ - "0.1041017000, 0.1062785000, 0.1112690000, 0.1233531000, 0.1457893000, 0.1904523000, 0.2731878000", \ - "0.1753990000, 0.1790020000, 0.1881875000, 0.2063116000, 0.2430046000, 0.3082280000, 0.4254296000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1497030000, 0.1591168000, 0.1798898000, 0.2341157000, 0.3659286000, 0.6874428000, 1.4783930000", \ - "0.1504274000, 0.1592532000, 0.1805147000, 0.2341859000, 0.3658190000, 0.6880985000, 1.4904297000", \ - "0.1505825000, 0.1586088000, 0.1802494000, 0.2342274000, 0.3651879000, 0.6875158000, 1.4773677000", \ - "0.1501547000, 0.1590093000, 0.1807274000, 0.2342092000, 0.3660205000, 0.6886984000, 1.4818559000", \ - "0.1540306000, 0.1625985000, 0.1833961000, 0.2359611000, 0.3671201000, 0.6879679000, 1.4826075000", \ - "0.1859165000, 0.1946765000, 0.2149971000, 0.2637039000, 0.3843253000, 0.6926062000, 1.4778059000", \ - "0.2563101000, 0.2651906000, 0.2858020000, 0.3389760000, 0.4631068000, 0.7561076000, 1.4977503000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1401381000, 0.1414878000, 0.1448587000, 0.1520351000, 0.1673426000, 0.1990187000, 0.2654301000", \ - "0.1451632000, 0.1465375000, 0.1496824000, 0.1568858000, 0.1723179000, 0.2039213000, 0.2704423000", \ - "0.1576090000, 0.1589095000, 0.1627117000, 0.1699260000, 0.1852450000, 0.2168673000, 0.2834143000", \ - "0.1883414000, 0.1897285000, 0.1930489000, 0.2002023000, 0.2156469000, 0.2471989000, 0.3137299000", \ - "0.2598475000, 0.2612521000, 0.2643888000, 0.2718218000, 0.2873993000, 0.3190476000, 0.3857399000", \ - "0.3885102000, 0.3900249000, 0.3938026000, 0.4019827000, 0.4200456000, 0.4545770000, 0.5233406000", \ - "0.5846490000, 0.5867308000, 0.5915697000, 0.6019007000, 0.6247266000, 0.6663464000, 0.7414088000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.2211398000, 0.2281523000, 0.2458371000, 0.2869246000, 0.3874079000, 0.6334631000, 1.2188829000", \ - "0.2257204000, 0.2326667000, 0.2504726000, 0.2914333000, 0.3935276000, 0.6350211000, 1.2234121000", \ - "0.2373048000, 0.2443621000, 0.2612440000, 0.3033497000, 0.4028267000, 0.6447941000, 1.2338999000", \ - "0.2611368000, 0.2680589000, 0.2858626000, 0.3272721000, 0.4280596000, 0.6684849000, 1.2581147000", \ - "0.3033536000, 0.3107804000, 0.3276351000, 0.3690228000, 0.4684251000, 0.7096119000, 1.3001134000", \ - "0.3593786000, 0.3666627000, 0.3834242000, 0.4243808000, 0.5235083000, 0.7650542000, 1.3566552000", \ - "0.4202025000, 0.4270942000, 0.4445335000, 0.4855861000, 0.5848566000, 0.8260125000, 1.4152353000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0382306000, 0.0391958000, 0.0415772000, 0.0472909000, 0.0607907000, 0.0922642000, 0.1705557000", \ - "0.0381939000, 0.0388802000, 0.0418259000, 0.0474460000, 0.0605827000, 0.0920733000, 0.1706137000", \ - "0.0380298000, 0.0389922000, 0.0413397000, 0.0474039000, 0.0605726000, 0.0920526000, 0.1705195000", \ - "0.0381524000, 0.0392333000, 0.0416052000, 0.0474034000, 0.0605691000, 0.0921614000, 0.1706576000", \ - "0.0390675000, 0.0400085000, 0.0425801000, 0.0481282000, 0.0616453000, 0.0925890000, 0.1708563000", \ - "0.0513608000, 0.0522413000, 0.0546642000, 0.0605745000, 0.0733247000, 0.1022304000, 0.1764911000", \ - "0.0727002000, 0.0740364000, 0.0771133000, 0.0838703000, 0.0979513000, 0.1254886000, 0.1944803000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1500476000, 0.1589108000, 0.1800660000, 0.2338469000, 0.3657137000, 0.6897055000, 1.4806325000", \ - "0.1499006000, 0.1581106000, 0.1800377000, 0.2339098000, 0.3669434000, 0.6884635000, 1.4784801000", \ - "0.1494023000, 0.1583861000, 0.1804962000, 0.2342352000, 0.3659354000, 0.6875405000, 1.4769737000", \ - "0.1498418000, 0.1581042000, 0.1802114000, 0.2346219000, 0.3667674000, 0.6886916000, 1.4789828000", \ - "0.1495644000, 0.1585130000, 0.1804532000, 0.2341272000, 0.3658678000, 0.6889606000, 1.4787930000", \ - "0.1505459000, 0.1598041000, 0.1813885000, 0.2350476000, 0.3660272000, 0.6872584000, 1.4786758000", \ - "0.1557870000, 0.1636737000, 0.1849905000, 0.2375466000, 0.3672524000, 0.6893528000, 1.4774358000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1244922000, 0.1261745000, 0.1301586000, 0.1385870000, 0.1552590000, 0.1876230000, 0.2538911000", \ - "0.1295375000, 0.1312268000, 0.1351157000, 0.1435250000, 0.1602527000, 0.1926344000, 0.2589330000", \ - "0.1418287000, 0.1435147000, 0.1478242000, 0.1562728000, 0.1730777000, 0.2053116000, 0.2716185000", \ - "0.1726941000, 0.1743717000, 0.1782361000, 0.1866947000, 0.2035198000, 0.2357843000, 0.3022431000", \ - "0.2436251000, 0.2452985000, 0.2491935000, 0.2576725000, 0.2746074000, 0.3073323000, 0.3737946000", \ - "0.3664153000, 0.3684866000, 0.3732626000, 0.3834477000, 0.4033424000, 0.4394975000, 0.5085817000", \ - "0.5537072000, 0.5563836000, 0.5625133000, 0.5756252000, 0.6010866000, 0.6455363000, 0.7219353000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1364133000, 0.1429283000, 0.1588434000, 0.2000729000, 0.3010673000, 0.5440488000, 1.1343732000", \ - "0.1409222000, 0.1472032000, 0.1634815000, 0.2041952000, 0.3062746000, 0.5497469000, 1.1431130000", \ - "0.1522658000, 0.1587691000, 0.1747222000, 0.2155317000, 0.3164184000, 0.5592686000, 1.1560277000", \ - "0.1763142000, 0.1824587000, 0.1982170000, 0.2387160000, 0.3393198000, 0.5852516000, 1.1801153000", \ - "0.2192888000, 0.2251727000, 0.2404285000, 0.2790285000, 0.3780330000, 0.6209443000, 1.2240640000", \ - "0.2767775000, 0.2824688000, 0.2968691000, 0.3346768000, 0.4321971000, 0.6728242000, 1.2637241000", \ - "0.3414642000, 0.3471373000, 0.3610092000, 0.3964259000, 0.4897218000, 0.7310689000, 1.3187020000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.0319202000, 0.0329316000, 0.0353933000, 0.0411898000, 0.0548094000, 0.0861160000, 0.1631932000", \ - "0.0320186000, 0.0330508000, 0.0356648000, 0.0414741000, 0.0552116000, 0.0860110000, 0.1635663000", \ - "0.0319106000, 0.0329624000, 0.0354559000, 0.0415256000, 0.0550525000, 0.0860217000, 0.1635672000", \ - "0.0321712000, 0.0332389000, 0.0357775000, 0.0417097000, 0.0548957000, 0.0862037000, 0.1630439000", \ - "0.0341530000, 0.0352434000, 0.0373064000, 0.0431498000, 0.0562022000, 0.0870452000, 0.1633890000", \ - "0.0481383000, 0.0492346000, 0.0518591000, 0.0568084000, 0.0686108000, 0.0973318000, 0.1693360000", \ - "0.0714635000, 0.0726940000, 0.0747622000, 0.0819745000, 0.0951484000, 0.1216769000, 0.1881631000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012316500, 0.0030339100, 0.0074734300, 0.0184093000, 0.0453475000, 0.1117040000"); - values("0.1339201000, 0.1437977000, 0.1675943000, 0.2260081000, 0.3638645000, 0.6867193000, 1.4788464000", \ - "0.1339566000, 0.1433783000, 0.1675716000, 0.2261569000, 0.3633775000, 0.6883519000, 1.4855742000", \ - "0.1340148000, 0.1439435000, 0.1676839000, 0.2259236000, 0.3632602000, 0.6889129000, 1.4819557000", \ - "0.1325770000, 0.1425466000, 0.1664284000, 0.2253180000, 0.3639018000, 0.6903358000, 1.4830598000", \ - "0.1322634000, 0.1421705000, 0.1660664000, 0.2235734000, 0.3629207000, 0.6867512000, 1.4881528000", \ - "0.1330410000, 0.1420465000, 0.1657445000, 0.2221719000, 0.3613668000, 0.6881017000, 1.4795958000", \ - "0.1407513000, 0.1493637000, 0.1715605000, 0.2237320000, 0.3596633000, 0.6899271000, 1.4780280000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111a_1") { - leakage_power () { - value : 0.0170728000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0119733000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0022061000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0120179000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0022003000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0119748000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0027321000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0031950000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0021797000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0021531000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0025234000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0021737000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0025089000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0021710000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0027416000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0024917000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0021797000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0021531000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0025234000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0021737000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0025089000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0021710000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0031922000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0024917000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0021797000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0021531000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0025234000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0021737000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0025089000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0021710000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0020359000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0024917000; - when : "A1&A2&B1&C1&!D1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o2111a"; - cell_leakage_power : 0.0037483290; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039708000, 0.0039673000, 0.0039595000, 0.0039601000, 0.0039617000, 0.0039651000, 0.0039731000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003964400, -0.003963500, -0.003961300, -0.003957900, -0.003950200, -0.003932400, -0.003891300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024740000; - } - pin ("A2") { - capacitance : 0.0023410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038764000, 0.0038703000, 0.0038563000, 0.0038569000, 0.0038583000, 0.0038616000, 0.0038691000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003865100, -0.003864200, -0.003862000, -0.003859700, -0.003854400, -0.003842300, -0.003814200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025000000; - } - pin ("B1") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022840000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039332000, 0.0039345000, 0.0039376000, 0.0039379000, 0.0039386000, 0.0039404000, 0.0039443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003935300, -0.003934400, -0.003932200, -0.003931100, -0.003928700, -0.003923200, -0.003910500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024350000; - } - pin ("C1") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023170000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042736000, 0.0042701000, 0.0042621000, 0.0042766000, 0.0043099000, 0.0043868000, 0.0045641000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003928900, -0.003927100, -0.003922800, -0.003922200, -0.003920800, -0.003917600, -0.003910400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024430000; - } - pin ("D1") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046323000, 0.0046320000, 0.0046314000, 0.0046307000, 0.0046291000, 0.0046254000, 0.0046168000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003586900, -0.003586800, -0.003586800, -0.003580200, -0.003565100, -0.003530400, -0.003450300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024110000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1&D1) | (A2&B1&C1&D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0190038000, 0.0181251000, 0.0157185000, 0.0080645000, -0.014427900, -0.075462800, -0.236436500", \ - "0.0189466000, 0.0180510000, 0.0156329000, 0.0079792000, -0.014541200, -0.075576400, -0.236604900", \ - "0.0188219000, 0.0179359000, 0.0155270000, 0.0078622000, -0.014655900, -0.075692200, -0.236705600", \ - "0.0186653000, 0.0178008000, 0.0153912000, 0.0077248000, -0.014803000, -0.075838100, -0.236794000", \ - "0.0185091000, 0.0176387000, 0.0152204000, 0.0075483000, -0.015003100, -0.076005100, -0.236962500", \ - "0.0183784000, 0.0171177000, 0.0148310000, 0.0073339000, -0.015113600, -0.076105100, -0.237022500", \ - "0.0218750000, 0.0205491000, 0.0171392000, 0.0082520000, -0.015076600, -0.075909600, -0.236734100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0153475000, 0.0168271000, 0.0205300000, 0.0297444000, 0.0532082000, 0.1148600000, 0.2739139000", \ - "0.0152424000, 0.0167041000, 0.0203892000, 0.0296004000, 0.0531464000, 0.1142712000, 0.2751454000", \ - "0.0150818000, 0.0165624000, 0.0202782000, 0.0294780000, 0.0529884000, 0.1146595000, 0.2738301000", \ - "0.0149228000, 0.0163894000, 0.0200708000, 0.0292949000, 0.0527801000, 0.1139708000, 0.2749190000", \ - "0.0147709000, 0.0161983000, 0.0199017000, 0.0291024000, 0.0526014000, 0.1138846000, 0.2746157000", \ - "0.0151059000, 0.0164434000, 0.0199986000, 0.0288527000, 0.0524243000, 0.1133045000, 0.2732993000", \ - "0.0154542000, 0.0168045000, 0.0202776000, 0.0292413000, 0.0527650000, 0.1138671000, 0.2725939000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0168892000, 0.0159960000, 0.0135913000, 0.0059413000, -0.016600600, -0.077615100, -0.238570000", \ - "0.0167427000, 0.0159000000, 0.0134664000, 0.0058189000, -0.016728400, -0.077743000, -0.238695800", \ - "0.0166813000, 0.0157852000, 0.0133218000, 0.0056668000, -0.016869100, -0.077897600, -0.238918000", \ - "0.0163696000, 0.0154900000, 0.0131102000, 0.0054473000, -0.017091100, -0.078112500, -0.239071300", \ - "0.0162769000, 0.0153905000, 0.0129701000, 0.0052673000, -0.017273400, -0.078258900, -0.239185600", \ - "0.0167399000, 0.0157754000, 0.0134053000, 0.0057812000, -0.016791800, -0.077752200, -0.238611700", \ - "0.0206523000, 0.0193056000, 0.0158539000, 0.0068969000, -0.016478900, -0.077236800, -0.238034800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0141324000, 0.0155825000, 0.0192675000, 0.0284792000, 0.0519271000, 0.1135673000, 0.2730472000", \ - "0.0140912000, 0.0155466000, 0.0192217000, 0.0284273000, 0.0518877000, 0.1128787000, 0.2735066000", \ - "0.0139177000, 0.0153723000, 0.0190748000, 0.0282728000, 0.0517031000, 0.1133740000, 0.2726513000", \ - "0.0136114000, 0.0150782000, 0.0187638000, 0.0279530000, 0.0513996000, 0.1131058000, 0.2718431000", \ - "0.0133350000, 0.0148036000, 0.0184249000, 0.0276061000, 0.0510742000, 0.1122723000, 0.2734908000", \ - "0.0135735000, 0.0149380000, 0.0184373000, 0.0273196000, 0.0508405000, 0.1115822000, 0.2720146000", \ - "0.0137752000, 0.0151302000, 0.0185622000, 0.0276808000, 0.0511576000, 0.1124474000, 0.2721788000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0157213000, 0.0149937000, 0.0126265000, 0.0047082000, -0.018297700, -0.079668700, -0.240839900", \ - "0.0155840000, 0.0148294000, 0.0125332000, 0.0046111000, -0.018411900, -0.079766000, -0.240944800", \ - "0.0153793000, 0.0146375000, 0.0123180000, 0.0043807000, -0.018621000, -0.079974700, -0.241160500", \ - "0.0151130000, 0.0143507000, 0.0119943000, 0.0040838000, -0.018891500, -0.080225600, -0.241414600", \ - "0.0148161000, 0.0140547000, 0.0116746000, 0.0037176000, -0.019217600, -0.080487300, -0.241631800", \ - "0.0169685000, 0.0156844000, 0.0122692000, 0.0038134000, -0.018899400, -0.080124900, -0.241236500", \ - "0.0186007000, 0.0172684000, 0.0138359000, 0.0049523000, -0.018364400, -0.079368200, -0.240379800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0155498000, 0.0170033000, 0.0207092000, 0.0299498000, 0.0534422000, 0.1146045000, 0.2742037000", \ - "0.0154922000, 0.0169721000, 0.0206731000, 0.0298909000, 0.0533785000, 0.1150407000, 0.2755427000", \ - "0.0153250000, 0.0168172000, 0.0205270000, 0.0297427000, 0.0532307000, 0.1149021000, 0.2753979000", \ - "0.0150948000, 0.0165498000, 0.0202778000, 0.0294848000, 0.0530003000, 0.1146900000, 0.2749979000", \ - "0.0149351000, 0.0163880000, 0.0200699000, 0.0292447000, 0.0527286000, 0.1139278000, 0.2747864000", \ - "0.0153014000, 0.0166237000, 0.0201112000, 0.0289549000, 0.0524266000, 0.1134104000, 0.2734365000", \ - "0.0157921000, 0.0171340000, 0.0204844000, 0.0295366000, 0.0529601000, 0.1141702000, 0.2732682000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0128021000, 0.0121055000, 0.0097207000, 0.0017783000, -0.021354700, -0.082817100, -0.244095400", \ - "0.0127284000, 0.0120056000, 0.0096687000, 0.0016781000, -0.021444300, -0.082905300, -0.244183900", \ - "0.0124735000, 0.0117601000, 0.0093990000, 0.0014098000, -0.021696700, -0.083157100, -0.244430900", \ - "0.0122097000, 0.0114470000, 0.0090475000, 0.0010825000, -0.021986500, -0.083420000, -0.244675000", \ - "0.0119617000, 0.0111862000, 0.0087589000, 0.0008104000, -0.022216700, -0.083574900, -0.244794900", \ - "0.0136722000, 0.0123973000, 0.0090508000, 0.0004254000, -0.022162600, -0.083459500, -0.244627600", \ - "0.0151983000, 0.0138428000, 0.0104474000, 0.0015417000, -0.021631500, -0.082720400, -0.243858300"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0155473000, 0.0170169000, 0.0206806000, 0.0299120000, 0.0534645000, 0.1146452000, 0.2746761000", \ - "0.0154838000, 0.0169578000, 0.0206303000, 0.0298421000, 0.0533627000, 0.1149768000, 0.2740737000", \ - "0.0153072000, 0.0167570000, 0.0204834000, 0.0297232000, 0.0532284000, 0.1148860000, 0.2754149000", \ - "0.0150791000, 0.0165561000, 0.0202562000, 0.0294588000, 0.0529579000, 0.1140449000, 0.2737992000", \ - "0.0149909000, 0.0164617000, 0.0200955000, 0.0292332000, 0.0526761000, 0.1138928000, 0.2737317000", \ - "0.0153900000, 0.0167163000, 0.0201492000, 0.0289719000, 0.0525183000, 0.1139410000, 0.2734574000", \ - "0.0159543000, 0.0173104000, 0.0206719000, 0.0297577000, 0.0531702000, 0.1145568000, 0.2739656000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0098896000, 0.0091531000, 0.0066587000, -0.001482300, -0.024805200, -0.086397300, -0.247735700", \ - "0.0097301000, 0.0089906000, 0.0065609000, -0.001614200, -0.024921800, -0.086518900, -0.247877500", \ - "0.0094658000, 0.0087132000, 0.0062235000, -0.001907400, -0.025181700, -0.086774300, -0.248121700", \ - "0.0091901000, 0.0084138000, 0.0059500000, -0.002195300, -0.025430000, -0.086989400, -0.248333000", \ - "0.0090174000, 0.0082001000, 0.0056939000, -0.002397700, -0.025582900, -0.087089700, -0.248417800", \ - "0.0107663000, 0.0094871000, 0.0061450000, -0.002773200, -0.025493000, -0.086957700, -0.248250400", \ - "0.0122412000, 0.0109082000, 0.0074915000, -0.001416800, -0.024751400, -0.085876500, -0.247131800"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013092120, 0.0034280750, 0.0089761560, 0.0235033900, 0.0615418700, 0.1611428000"); - values("0.0151381000, 0.0165984000, 0.0203180000, 0.0295435000, 0.0530288000, 0.1141902000, 0.2740008000", \ - "0.0150348000, 0.0165258000, 0.0202165000, 0.0294375000, 0.0529410000, 0.1145415000, 0.2737951000", \ - "0.0148649000, 0.0163260000, 0.0200477000, 0.0292756000, 0.0527433000, 0.1145125000, 0.2735537000", \ - "0.0146170000, 0.0160880000, 0.0197891000, 0.0289831000, 0.0524658000, 0.1136605000, 0.2745667000", \ - "0.0144355000, 0.0158661000, 0.0194908000, 0.0286903000, 0.0521564000, 0.1138959000, 0.2744172000", \ - "0.0149947000, 0.0163215000, 0.0197726000, 0.0285661000, 0.0520552000, 0.1130544000, 0.2731052000", \ - "0.0159169000, 0.0173627000, 0.0207343000, 0.0296498000, 0.0530132000, 0.1141712000, 0.2738313000"); - } - } - max_capacitance : 0.1611430000; - max_transition : 1.5041860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.2036876000, 0.2118373000, 0.2284263000, 0.2602881000, 0.3219063000, 0.4600775000, 0.8077132000", \ - "0.2090474000, 0.2171617000, 0.2337849000, 0.2655198000, 0.3272821000, 0.4654427000, 0.8127332000", \ - "0.2215096000, 0.2296257000, 0.2462367000, 0.2779797000, 0.3397729000, 0.4779116000, 0.8253569000", \ - "0.2476633000, 0.2557759000, 0.2723584000, 0.3041215000, 0.3661403000, 0.5043142000, 0.8520172000", \ - "0.3064907000, 0.3146372000, 0.3312278000, 0.3629032000, 0.4253294000, 0.5636120000, 0.9109091000", \ - "0.4277441000, 0.4364856000, 0.4541735000, 0.4875294000, 0.5512343000, 0.6901173000, 1.0378012000", \ - "0.6371542000, 0.6475289000, 0.6683977000, 0.7061690000, 0.7758318000, 0.9189319000, 1.2670551000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1499049000, 0.1593606000, 0.1795253000, 0.2222874000, 0.3195502000, 0.5662066000, 1.2065446000", \ - "0.1542583000, 0.1636220000, 0.1837911000, 0.2265924000, 0.3240654000, 0.5696337000, 1.2133545000", \ - "0.1631139000, 0.1725671000, 0.1927637000, 0.2355234000, 0.3329399000, 0.5796795000, 1.2200617000", \ - "0.1798430000, 0.1892302000, 0.2094238000, 0.2521032000, 0.3497086000, 0.5955825000, 1.2363973000", \ - "0.2100601000, 0.2197651000, 0.2402522000, 0.2832737000, 0.3809772000, 0.6264052000, 1.2691974000", \ - "0.2571272000, 0.2676812000, 0.2898580000, 0.3347270000, 0.4336254000, 0.6798372000, 1.3203360000", \ - "0.3072066000, 0.3203328000, 0.3464805000, 0.3959210000, 0.4979855000, 0.7451912000, 1.3854371000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0296776000, 0.0349255000, 0.0465417000, 0.0725299000, 0.1350196000, 0.3018611000, 0.7601458000", \ - "0.0297115000, 0.0348475000, 0.0467886000, 0.0727299000, 0.1349400000, 0.3011389000, 0.7605875000", \ - "0.0296963000, 0.0348740000, 0.0467618000, 0.0726777000, 0.1349332000, 0.3010467000, 0.7594144000", \ - "0.0296265000, 0.0348847000, 0.0466555000, 0.0727137000, 0.1349096000, 0.3018725000, 0.7598491000", \ - "0.0295854000, 0.0347823000, 0.0467109000, 0.0726848000, 0.1343598000, 0.3013699000, 0.7634837000", \ - "0.0338319000, 0.0390033000, 0.0505127000, 0.0766026000, 0.1376611000, 0.3027139000, 0.7610921000", \ - "0.0426318000, 0.0487804000, 0.0612048000, 0.0873939000, 0.1486105000, 0.3086396000, 0.7588336000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0318163000, 0.0395975000, 0.0585704000, 0.1059220000, 0.2330478000, 0.5809126000, 1.4974897000", \ - "0.0316929000, 0.0397392000, 0.0586852000, 0.1057336000, 0.2335127000, 0.5810690000, 1.4937082000", \ - "0.0318647000, 0.0396050000, 0.0586609000, 0.1059229000, 0.2334375000, 0.5804324000, 1.4955904000", \ - "0.0317013000, 0.0396719000, 0.0586040000, 0.1058901000, 0.2330572000, 0.5801607000, 1.4981528000", \ - "0.0329841000, 0.0406470000, 0.0593414000, 0.1066284000, 0.2336224000, 0.5797346000, 1.4982992000", \ - "0.0367286000, 0.0452112000, 0.0640824000, 0.1103940000, 0.2352897000, 0.5801037000, 1.4936450000", \ - "0.0472920000, 0.0562602000, 0.0755263000, 0.1208472000, 0.2402658000, 0.5820506000, 1.4925868000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1911456000, 0.1991717000, 0.2157215000, 0.2476528000, 0.3098457000, 0.4481365000, 0.7956036000", \ - "0.1950676000, 0.2032344000, 0.2197506000, 0.2515709000, 0.3138114000, 0.4520694000, 0.7991690000", \ - "0.2057519000, 0.2138249000, 0.2303877000, 0.2621907000, 0.3241932000, 0.4623641000, 0.8098108000", \ - "0.2342671000, 0.2424010000, 0.2588346000, 0.2905962000, 0.3527441000, 0.4909311000, 0.8381545000", \ - "0.3025601000, 0.3105949000, 0.3271036000, 0.3588631000, 0.4213322000, 0.5595067000, 0.9069503000", \ - "0.4507758000, 0.4597803000, 0.4774360000, 0.5105366000, 0.5737624000, 0.7124209000, 1.0602278000", \ - "0.6954023000, 0.7070483000, 0.7295584000, 0.7686279000, 0.8369099000, 0.9792298000, 1.3281277000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1275007000, 0.1364398000, 0.1557567000, 0.1973211000, 0.2935182000, 0.5396293000, 1.1820824000", \ - "0.1321767000, 0.1410807000, 0.1604045000, 0.2020026000, 0.2980717000, 0.5443765000, 1.1885770000", \ - "0.1407655000, 0.1497106000, 0.1691069000, 0.2106160000, 0.3067984000, 0.5529803000, 1.1954182000", \ - "0.1565247000, 0.1655450000, 0.1848693000, 0.2263600000, 0.3225933000, 0.5686784000, 1.2197157000", \ - "0.1835185000, 0.1929065000, 0.2128676000, 0.2549085000, 0.3515598000, 0.5967051000, 1.2413677000", \ - "0.2207408000, 0.2311805000, 0.2530373000, 0.2972140000, 0.3952778000, 0.6407668000, 1.2844169000", \ - "0.2442996000, 0.2580055000, 0.2850323000, 0.3354115000, 0.4366982000, 0.6834567000, 1.3230510000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0301635000, 0.0349416000, 0.0470993000, 0.0725256000, 0.1350254000, 0.3015074000, 0.7590819000", \ - "0.0296657000, 0.0349333000, 0.0465726000, 0.0724599000, 0.1350426000, 0.3015005000, 0.7573229000", \ - "0.0298652000, 0.0350313000, 0.0468686000, 0.0724721000, 0.1352940000, 0.3010417000, 0.7580856000", \ - "0.0295992000, 0.0347971000, 0.0468130000, 0.0724708000, 0.1352779000, 0.3012419000, 0.7572487000", \ - "0.0299547000, 0.0349078000, 0.0470374000, 0.0723912000, 0.1349652000, 0.3016618000, 0.7594022000", \ - "0.0354281000, 0.0403050000, 0.0513105000, 0.0759401000, 0.1371177000, 0.3019459000, 0.7584424000", \ - "0.0497112000, 0.0555483000, 0.0672469000, 0.0906303000, 0.1480223000, 0.3080991000, 0.7573852000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0295748000, 0.0373715000, 0.0560245000, 0.1030061000, 0.2316159000, 0.5808187000, 1.4993079000", \ - "0.0295658000, 0.0373587000, 0.0560269000, 0.1031854000, 0.2313198000, 0.5806133000, 1.4997528000", \ - "0.0295982000, 0.0374189000, 0.0559898000, 0.1031405000, 0.2314786000, 0.5804559000, 1.5008215000", \ - "0.0294868000, 0.0373143000, 0.0559077000, 0.1029734000, 0.2316227000, 0.5808643000, 1.4975676000", \ - "0.0312362000, 0.0392599000, 0.0575836000, 0.1045323000, 0.2318349000, 0.5800829000, 1.5041859000", \ - "0.0362708000, 0.0448244000, 0.0633579000, 0.1090876000, 0.2340850000, 0.5784210000, 1.5004614000", \ - "0.0493631000, 0.0585533000, 0.0774906000, 0.1210882000, 0.2396526000, 0.5810281000, 1.4888003000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1014433000, 0.1078503000, 0.1217490000, 0.1498937000, 0.2070849000, 0.3409978000, 0.6858520000", \ - "0.1071619000, 0.1136446000, 0.1274664000, 0.1555897000, 0.2127760000, 0.3466926000, 0.6917059000", \ - "0.1202997000, 0.1267890000, 0.1406128000, 0.1687777000, 0.2259603000, 0.3596917000, 0.7062941000", \ - "0.1529053000, 0.1593504000, 0.1732538000, 0.2013592000, 0.2586385000, 0.3925939000, 0.7376546000", \ - "0.2266116000, 0.2333438000, 0.2476251000, 0.2761628000, 0.3337668000, 0.4678265000, 0.8142335000", \ - "0.3533839000, 0.3619073000, 0.3795830000, 0.4134303000, 0.4756244000, 0.6114447000, 0.9576440000", \ - "0.5595139000, 0.5708615000, 0.5942217000, 0.6380322000, 0.7109604000, 0.8524881000, 1.1984806000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1425556000, 0.1519794000, 0.1722570000, 0.2148975000, 0.3125203000, 0.5583511000, 1.1985948000", \ - "0.1464865000, 0.1559517000, 0.1761015000, 0.2188671000, 0.3161358000, 0.5626788000, 1.2029019000", \ - "0.1543412000, 0.1637969000, 0.1839594000, 0.2267256000, 0.3240021000, 0.5705242000, 1.2106984000", \ - "0.1707368000, 0.1801439000, 0.2003233000, 0.2430658000, 0.3404604000, 0.5866503000, 1.2301981000", \ - "0.2040998000, 0.2138564000, 0.2346266000, 0.2777697000, 0.3755257000, 0.6212043000, 1.2637507000", \ - "0.2537661000, 0.2640575000, 0.2863773000, 0.3316465000, 0.4307950000, 0.6775194000, 1.3177787000", \ - "0.2950628000, 0.3087032000, 0.3357189000, 0.3854424000, 0.4869902000, 0.7338532000, 1.3752449000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0209008000, 0.0259657000, 0.0379246000, 0.0633550000, 0.1250383000, 0.2965054000, 0.7527304000", \ - "0.0207319000, 0.0258378000, 0.0378103000, 0.0636339000, 0.1249899000, 0.2953879000, 0.7521789000", \ - "0.0208412000, 0.0257963000, 0.0378595000, 0.0634723000, 0.1249007000, 0.2949411000, 0.7577158000", \ - "0.0207325000, 0.0258963000, 0.0378139000, 0.0636284000, 0.1251415000, 0.2965632000, 0.7536436000", \ - "0.0228057000, 0.0278957000, 0.0393607000, 0.0643256000, 0.1254943000, 0.2947637000, 0.7555592000", \ - "0.0321849000, 0.0379995000, 0.0505288000, 0.0758184000, 0.1328752000, 0.2965476000, 0.7572048000", \ - "0.0466465000, 0.0533474000, 0.0691178000, 0.0979411000, 0.1529641000, 0.3050583000, 0.7513195000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0315954000, 0.0398564000, 0.0586904000, 0.1058007000, 0.2330648000, 0.5804457000, 1.4977340000", \ - "0.0317812000, 0.0396219000, 0.0585429000, 0.1058465000, 0.2333049000, 0.5814237000, 1.4976355000", \ - "0.0318098000, 0.0396485000, 0.0585563000, 0.1058951000, 0.2333206000, 0.5814698000, 1.4974890000", \ - "0.0316527000, 0.0396778000, 0.0585831000, 0.1056775000, 0.2335319000, 0.5814164000, 1.4945343000", \ - "0.0335077000, 0.0414636000, 0.0600334000, 0.1070435000, 0.2335621000, 0.5787348000, 1.4985632000", \ - "0.0386482000, 0.0469720000, 0.0653626000, 0.1111845000, 0.2361428000, 0.5806559000, 1.4980086000", \ - "0.0513426000, 0.0595063000, 0.0782741000, 0.1211105000, 0.2404157000, 0.5813163000, 1.4932109000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0918274000, 0.0980811000, 0.1116632000, 0.1395174000, 0.1965925000, 0.3302322000, 0.6764849000", \ - "0.0975602000, 0.1037392000, 0.1173486000, 0.1452324000, 0.2023059000, 0.3359200000, 0.6823143000", \ - "0.1111748000, 0.1173283000, 0.1309827000, 0.1587919000, 0.2158896000, 0.3495228000, 0.6959174000", \ - "0.1435898000, 0.1498184000, 0.1633802000, 0.1912449000, 0.2484311000, 0.3820751000, 0.7285983000", \ - "0.2141036000, 0.2209246000, 0.2351792000, 0.2640023000, 0.3217289000, 0.4555719000, 0.8015862000", \ - "0.3334098000, 0.3421656000, 0.3601759000, 0.3944106000, 0.4574891000, 0.5935734000, 0.9389858000", \ - "0.5263582000, 0.5378898000, 0.5616756000, 0.6064389000, 0.6802897000, 0.8232512000, 1.1690738000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1337003000, 0.1431203000, 0.1632828000, 0.2060351000, 0.3035789000, 0.5490888000, 1.1921742000", \ - "0.1374671000, 0.1469413000, 0.1670789000, 0.2098610000, 0.3072082000, 0.5539965000, 1.1940634000", \ - "0.1456463000, 0.1550474000, 0.1753160000, 0.2180623000, 0.3153745000, 0.5619138000, 1.2017592000", \ - "0.1648547000, 0.1743032000, 0.1945318000, 0.2372416000, 0.3346375000, 0.5816229000, 1.2217302000", \ - "0.2040837000, 0.2137108000, 0.2343921000, 0.2777207000, 0.3754155000, 0.6213999000, 1.2609660000", \ - "0.2590591000, 0.2698247000, 0.2916282000, 0.3362556000, 0.4350194000, 0.6821477000, 1.3244360000", \ - "0.3052713000, 0.3188906000, 0.3450044000, 0.3939356000, 0.4945615000, 0.7422233000, 1.3835106000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0196105000, 0.0248409000, 0.0366966000, 0.0629942000, 0.1247675000, 0.2937489000, 0.7551811000", \ - "0.0198161000, 0.0248388000, 0.0368411000, 0.0628748000, 0.1247366000, 0.2940946000, 0.7556850000", \ - "0.0196009000, 0.0248100000, 0.0367586000, 0.0628772000, 0.1247851000, 0.2939633000, 0.7554986000", \ - "0.0197786000, 0.0247651000, 0.0367520000, 0.0629647000, 0.1244686000, 0.2944895000, 0.7548372000", \ - "0.0230030000, 0.0278747000, 0.0395422000, 0.0648231000, 0.1255662000, 0.2944570000, 0.7581641000", \ - "0.0324096000, 0.0380906000, 0.0510284000, 0.0769574000, 0.1344363000, 0.2971383000, 0.7548974000", \ - "0.0476671000, 0.0543684000, 0.0706161000, 0.1009213000, 0.1575930000, 0.3068458000, 0.7513591000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0317375000, 0.0396383000, 0.0587517000, 0.1059736000, 0.2335146000, 0.5805006000, 1.4968048000", \ - "0.0315000000, 0.0396727000, 0.0587010000, 0.1060181000, 0.2330576000, 0.5809022000, 1.4978808000", \ - "0.0316735000, 0.0398898000, 0.0585925000, 0.1058882000, 0.2333229000, 0.5813832000, 1.4970273000", \ - "0.0317094000, 0.0394161000, 0.0585933000, 0.1059079000, 0.2334108000, 0.5814171000, 1.4913228000", \ - "0.0336128000, 0.0415762000, 0.0601785000, 0.1072980000, 0.2336318000, 0.5809038000, 1.4961014000", \ - "0.0385021000, 0.0464231000, 0.0651541000, 0.1107416000, 0.2361223000, 0.5797343000, 1.4961440000", \ - "0.0513920000, 0.0598524000, 0.0774787000, 0.1199290000, 0.2398189000, 0.5837373000, 1.4934266000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0796547000, 0.0857163000, 0.0989329000, 0.1261784000, 0.1825851000, 0.3156506000, 0.6619105000", \ - "0.0851571000, 0.0912241000, 0.1045312000, 0.1317356000, 0.1881765000, 0.3213285000, 0.6677310000", \ - "0.0986787000, 0.1046814000, 0.1179749000, 0.1452796000, 0.2017538000, 0.3348932000, 0.6813381000", \ - "0.1310713000, 0.1371033000, 0.1503349000, 0.1777148000, 0.2343529000, 0.3676883000, 0.7127591000", \ - "0.1965685000, 0.2035165000, 0.2181159000, 0.2472400000, 0.3048965000, 0.4384451000, 0.7836146000", \ - "0.3026201000, 0.3117266000, 0.3304958000, 0.3658189000, 0.4296684000, 0.5660749000, 0.9112335000", \ - "0.4731713000, 0.4850783000, 0.5097114000, 0.5567187000, 0.6348430000, 0.7780052000, 1.1242864000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.1216391000, 0.1310362000, 0.1512738000, 0.1940123000, 0.2915431000, 0.5374224000, 1.1769208000", \ - "0.1250960000, 0.1345403000, 0.1547441000, 0.1975094000, 0.2948254000, 0.5416161000, 1.1820372000", \ - "0.1336018000, 0.1430520000, 0.1632550000, 0.2060414000, 0.3033029000, 0.5499886000, 1.1907383000", \ - "0.1549574000, 0.1643666000, 0.1845887000, 0.2271938000, 0.3247552000, 0.5705413000, 1.2121528000", \ - "0.1976129000, 0.2070714000, 0.2276022000, 0.2706396000, 0.3680816000, 0.6144008000, 1.2547614000", \ - "0.2532399000, 0.2633797000, 0.2846630000, 0.3284340000, 0.4269032000, 0.6746678000, 1.3168672000", \ - "0.2998037000, 0.3129875000, 0.3388017000, 0.3857132000, 0.4845552000, 0.7321818000, 1.3742429000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0188039000, 0.0239886000, 0.0359924000, 0.0621731000, 0.1239371000, 0.2940910000, 0.7501401000", \ - "0.0188375000, 0.0239880000, 0.0359672000, 0.0621495000, 0.1242686000, 0.2937072000, 0.7549124000", \ - "0.0189864000, 0.0240566000, 0.0359961000, 0.0620608000, 0.1239637000, 0.2941089000, 0.7484754000", \ - "0.0191536000, 0.0241199000, 0.0361266000, 0.0623722000, 0.1242616000, 0.2948577000, 0.7510665000", \ - "0.0237385000, 0.0289499000, 0.0404838000, 0.0658187000, 0.1257716000, 0.2940669000, 0.7532299000", \ - "0.0339108000, 0.0399130000, 0.0531239000, 0.0796963000, 0.1366511000, 0.2969566000, 0.7593006000", \ - "0.0489195000, 0.0565292000, 0.0737493000, 0.1061352000, 0.1610947000, 0.3085977000, 0.7513655000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013092100, 0.0034280700, 0.0089761600, 0.0235034000, 0.0615419000, 0.1611430000"); - values("0.0315478000, 0.0396691000, 0.0585907000, 0.1057190000, 0.2333294000, 0.5808556000, 1.4962600000", \ - "0.0318193000, 0.0396782000, 0.0586660000, 0.1059482000, 0.2329570000, 0.5799349000, 1.4962946000", \ - "0.0316972000, 0.0396716000, 0.0585599000, 0.1058092000, 0.2331129000, 0.5810025000, 1.4963718000", \ - "0.0316247000, 0.0395440000, 0.0585352000, 0.1058812000, 0.2328381000, 0.5794499000, 1.4985527000", \ - "0.0327015000, 0.0409560000, 0.0599145000, 0.1072582000, 0.2338954000, 0.5817284000, 1.4969396000", \ - "0.0384593000, 0.0457076000, 0.0636109000, 0.1097003000, 0.2363888000, 0.5813736000, 1.4926961000", \ - "0.0517028000, 0.0597941000, 0.0761612000, 0.1183410000, 0.2384080000, 0.5844388000, 1.4939628000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111a_2") { - leakage_power () { - value : 0.0028564000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0029481000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0028974000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0028507000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0028911000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0028484000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0034259000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0029938000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0028705000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0028443000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0032034000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0028646000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0031752000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0028606000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0028710000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0031580000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0028705000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0028443000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0032034000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0028646000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0031752000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0028606000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0034392000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0031579000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0028705000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0028443000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0032034000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0028646000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0031752000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0028606000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0022976000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0031579000; - when : "A1&A2&B1&C1&!D1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__o2111a"; - cell_leakage_power : 0.0029765370; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044615000, 0.0044414000, 0.0043949000, 0.0043929000, 0.0043884000, 0.0043781000, 0.0043543000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004347900, -0.004361400, -0.004392700, -0.004392000, -0.004390500, -0.004386900, -0.004378800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025810000; - } - pin ("A2") { - capacitance : 0.0023830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040626000, 0.0040702000, 0.0040876000, 0.0040878000, 0.0040882000, 0.0040890000, 0.0040910000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004074100, -0.004075900, -0.004079900, -0.004079300, -0.004077700, -0.004074000, -0.004065600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025430000; - } - pin ("B1") { - capacitance : 0.0023230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039164000, 0.0039147000, 0.0039108000, 0.0039105000, 0.0039098000, 0.0039082000, 0.0039045000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003913800, -0.003915800, -0.003920400, -0.003919300, -0.003916800, -0.003911100, -0.003897800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("C1") { - capacitance : 0.0024500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044592000, 0.0044539000, 0.0044419000, 0.0044554000, 0.0044866000, 0.0045587000, 0.0047246000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004028700, -0.004030100, -0.004033200, -0.004032000, -0.004029300, -0.004023200, -0.004008900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025320000; - } - pin ("D1") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047484000, 0.0047462000, 0.0047411000, 0.0047428000, 0.0047465000, 0.0047552000, 0.0047751000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003897700, -0.003899200, -0.003902800, -0.003895900, -0.003880100, -0.003843700, -0.003759800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1&D1) | (A2&B1&C1&D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0220624000, 0.0206054000, 0.0169284000, 0.0060178000, -0.029307000, -0.137652500, -0.454819900", \ - "0.0220005000, 0.0205413000, 0.0168123000, 0.0059605000, -0.029432800, -0.137744900, -0.455130300", \ - "0.0219177000, 0.0204813000, 0.0167925000, 0.0058761000, -0.029502500, -0.137824700, -0.455198200", \ - "0.0217413000, 0.0202894000, 0.0166554000, 0.0057896000, -0.029692500, -0.137950000, -0.455310000", \ - "0.0216091000, 0.0201919000, 0.0164870000, 0.0055348000, -0.029895000, -0.138140200, -0.455478200", \ - "0.0214545000, 0.0200756000, 0.0163478000, 0.0054487000, -0.030090400, -0.138331500, -0.455597100", \ - "0.0272895000, 0.0254098000, 0.0207484000, 0.0077125000, -0.029755600, -0.138237300, -0.455400700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0195618000, 0.0211917000, 0.0259767000, 0.0394433000, 0.0773743000, 0.1862403000, 0.5030952000", \ - "0.0194343000, 0.0210533000, 0.0257989000, 0.0394378000, 0.0773187000, 0.1860985000, 0.5031096000", \ - "0.0193454000, 0.0209595000, 0.0257148000, 0.0393580000, 0.0771993000, 0.1867386000, 0.5031018000", \ - "0.0192008000, 0.0208304000, 0.0255538000, 0.0391632000, 0.0770969000, 0.1858749000, 0.5029796000", \ - "0.0191278000, 0.0207383000, 0.0254881000, 0.0389613000, 0.0768749000, 0.1855566000, 0.5003785000", \ - "0.0197718000, 0.0213203000, 0.0258224000, 0.0387119000, 0.0766321000, 0.1850617000, 0.4998216000", \ - "0.0203411000, 0.0218997000, 0.0263281000, 0.0394898000, 0.0773125000, 0.1859845000, 0.5017724000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0199315000, 0.0184711000, 0.0149538000, 0.0038945000, -0.031544200, -0.139755800, -0.457121600", \ - "0.0198457000, 0.0183795000, 0.0146856000, 0.0038063000, -0.031686100, -0.139873300, -0.457190100", \ - "0.0196322000, 0.0181927000, 0.0145535000, 0.0036061000, -0.031826900, -0.140021000, -0.457439300", \ - "0.0194934000, 0.0180192000, 0.0143329000, 0.0034716000, -0.032061500, -0.140288100, -0.457642200", \ - "0.0193358000, 0.0178692000, 0.0142083000, 0.0032680000, -0.032273000, -0.140462500, -0.457789500", \ - "0.0196599000, 0.0181754000, 0.0146837000, 0.0037173000, -0.031882600, -0.140118500, -0.457323600", \ - "0.0256067000, 0.0238696000, 0.0192443000, 0.0060017000, -0.031528300, -0.139743600, -0.456868400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0180415000, 0.0196481000, 0.0244675000, 0.0381140000, 0.0759380000, 0.1845238000, 0.5018827000", \ - "0.0180674000, 0.0197350000, 0.0245325000, 0.0380755000, 0.0759178000, 0.1845126000, 0.5018630000", \ - "0.0179217000, 0.0195841000, 0.0244187000, 0.0379227000, 0.0757902000, 0.1843700000, 0.5019428000", \ - "0.0176497000, 0.0193072000, 0.0241383000, 0.0376955000, 0.0755494000, 0.1842467000, 0.4989859000", \ - "0.0174504000, 0.0190973000, 0.0238706000, 0.0373076000, 0.0751154000, 0.1837192000, 0.4988330000", \ - "0.0179887000, 0.0196076000, 0.0241378000, 0.0370444000, 0.0749295000, 0.1833656000, 0.4955406000", \ - "0.0186398000, 0.0201281000, 0.0245838000, 0.0378736000, 0.0753758000, 0.1843321000, 0.4966838000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0180649000, 0.0169134000, 0.0139094000, 0.0033046000, -0.032547300, -0.141420100, -0.459087100", \ - "0.0179551000, 0.0168732000, 0.0138132000, 0.0032339000, -0.032661500, -0.141524100, -0.459194100", \ - "0.0177558000, 0.0165860000, 0.0135585000, 0.0030175000, -0.032824000, -0.141673300, -0.459350400", \ - "0.0175562000, 0.0164066000, 0.0133399000, 0.0027555000, -0.033110400, -0.141917700, -0.459560200", \ - "0.0173598000, 0.0161645000, 0.0129945000, 0.0025601000, -0.033565800, -0.142271500, -0.459852200", \ - "0.0196598000, 0.0181372000, 0.0136364000, 0.0019426000, -0.033325300, -0.142037100, -0.459551000", \ - "0.0239535000, 0.0222944000, 0.0176925000, 0.0044720000, -0.032901500, -0.141548000, -0.458865700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0198891000, 0.0215337000, 0.0262424000, 0.0398842000, 0.0777337000, 0.1865574000, 0.5035658000", \ - "0.0198504000, 0.0215181000, 0.0262773000, 0.0397494000, 0.0776752000, 0.1865078000, 0.5032918000", \ - "0.0197163000, 0.0213591000, 0.0260658000, 0.0396491000, 0.0775707000, 0.1864079000, 0.5034314000", \ - "0.0194264000, 0.0210486000, 0.0258886000, 0.0394275000, 0.0773184000, 0.1870202000, 0.5031990000", \ - "0.0193376000, 0.0209426000, 0.0256171000, 0.0390797000, 0.0769511000, 0.1856917000, 0.5009318000", \ - "0.0199834000, 0.0215210000, 0.0260791000, 0.0388610000, 0.0767507000, 0.1852015000, 0.5001945000", \ - "0.0208024000, 0.0222597000, 0.0266221000, 0.0397231000, 0.0774058000, 0.1860734000, 0.4983143000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0151891000, 0.0139626000, 0.0108907000, 0.0003681000, -0.035614800, -0.144627300, -0.462407500", \ - "0.0150331000, 0.0138451000, 0.0108912000, 0.0003174000, -0.035689700, -0.144683900, -0.462460600", \ - "0.0148735000, 0.0136360000, 0.0106368000, 8.640000e-05, -0.035843100, -0.144851100, -0.462629300", \ - "0.0145520000, 0.0134281000, 0.0102945000, -0.000296300, -0.036226500, -0.145165100, -0.462926900", \ - "0.0143572000, 0.0131250000, 0.0099422000, -0.000752300, -0.036673600, -0.145474400, -0.463147100", \ - "0.0165162000, 0.0149607000, 0.0105229000, -0.001570600, -0.036904200, -0.145583800, -0.463134600", \ - "0.0202315000, 0.0185579000, 0.0138909000, 0.0009298000, -0.036478500, -0.145177300, -0.462571800"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0200299000, 0.0216814000, 0.0264602000, 0.0399057000, 0.0779004000, 0.1864354000, 0.5037416000", \ - "0.0199044000, 0.0215238000, 0.0262796000, 0.0399142000, 0.0778047000, 0.1866624000, 0.5012533000", \ - "0.0198071000, 0.0214535000, 0.0262382000, 0.0397163000, 0.0776589000, 0.1865121000, 0.5033195000", \ - "0.0195564000, 0.0211905000, 0.0259358000, 0.0395414000, 0.0774436000, 0.1862386000, 0.5028032000", \ - "0.0194382000, 0.0210379000, 0.0257049000, 0.0391870000, 0.0770257000, 0.1858228000, 0.5006686000", \ - "0.0201132000, 0.0216379000, 0.0261832000, 0.0389146000, 0.0765593000, 0.1850582000, 0.5004053000", \ - "0.0210872000, 0.0225810000, 0.0269482000, 0.0399423000, 0.0776194000, 0.1861028000, 0.4985405000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0127127000, 0.0116304000, 0.0085105000, -0.002373400, -0.038805700, -0.148088300, -0.465999000", \ - "0.0126593000, 0.0114654000, 0.0084191000, -0.002475000, -0.038887300, -0.148158200, -0.466085200", \ - "0.0123535000, 0.0111916000, 0.0081622000, -0.002676400, -0.039065300, -0.148331100, -0.466264000", \ - "0.0120520000, 0.0109268000, 0.0077790000, -0.003104100, -0.039445300, -0.148633100, -0.466521600", \ - "0.0121788000, 0.0108870000, 0.0076000000, -0.003406200, -0.039708200, -0.148812900, -0.466652200", \ - "0.0146614000, 0.0130931000, 0.0087599000, -0.004134200, -0.039861100, -0.148845200, -0.466596600", \ - "0.0174233000, 0.0157368000, 0.0111044000, -0.001865200, -0.039344100, -0.148259900, -0.465809400"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0197758000, 0.0213979000, 0.0261391000, 0.0397511000, 0.0777185000, 0.1864263000, 0.5033765000", \ - "0.0196510000, 0.0213078000, 0.0260563000, 0.0396927000, 0.0775800000, 0.1862770000, 0.5013628000", \ - "0.0194882000, 0.0211398000, 0.0259809000, 0.0394797000, 0.0774984000, 0.1860909000, 0.5007012000", \ - "0.0192463000, 0.0208838000, 0.0256719000, 0.0392604000, 0.0771104000, 0.1858005000, 0.5008313000", \ - "0.0190901000, 0.0206993000, 0.0253937000, 0.0388961000, 0.0766898000, 0.1854372000, 0.5003331000", \ - "0.0199535000, 0.0214856000, 0.0259229000, 0.0387106000, 0.0762675000, 0.1849232000, 0.4999833000", \ - "0.0212529000, 0.0227266000, 0.0270609000, 0.0398892000, 0.0774800000, 0.1860316000, 0.4984620000"); - } - } - max_capacitance : 0.2993870000; - max_transition : 1.5057730000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2254194000, 0.2322189000, 0.2471249000, 0.2763244000, 0.3325414000, 0.4558522000, 0.7797867000", \ - "0.2307645000, 0.2375415000, 0.2524876000, 0.2816171000, 0.3375636000, 0.4609105000, 0.7842897000", \ - "0.2434245000, 0.2502105000, 0.2651809000, 0.2942911000, 0.3502772000, 0.4736301000, 0.7970135000", \ - "0.2698684000, 0.2766919000, 0.2916203000, 0.3203159000, 0.3771316000, 0.5004319000, 0.8243858000", \ - "0.3284476000, 0.3354106000, 0.3502245000, 0.3794535000, 0.4360388000, 0.5595355000, 0.8829671000", \ - "0.4538886000, 0.4618358000, 0.4776664000, 0.5082066000, 0.5658971000, 0.6897086000, 1.0136735000", \ - "0.6723973000, 0.6810692000, 0.6996923000, 0.7348258000, 0.7993888000, 0.9297884000, 1.2555994000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1646369000, 0.1725484000, 0.1905947000, 0.2294332000, 0.3187046000, 0.5567753000, 1.2405263000", \ - "0.1689794000, 0.1768669000, 0.1948856000, 0.2338443000, 0.3230735000, 0.5611820000, 1.2442698000", \ - "0.1779051000, 0.1857937000, 0.2038192000, 0.2427796000, 0.3318795000, 0.5700996000, 1.2517858000", \ - "0.1947459000, 0.2026595000, 0.2206483000, 0.2595897000, 0.3488498000, 0.5866527000, 1.2690722000", \ - "0.2267714000, 0.2347570000, 0.2529036000, 0.2919925000, 0.3812570000, 0.6193333000, 1.3019813000", \ - "0.2780930000, 0.2868782000, 0.3065927000, 0.3477055000, 0.4388817000, 0.6769253000, 1.3601411000", \ - "0.3399695000, 0.3507713000, 0.3740091000, 0.4203386000, 0.5160262000, 0.7556133000, 1.4375975000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0315370000, 0.0354466000, 0.0443826000, 0.0645808000, 0.1129884000, 0.2476493000, 0.6666731000", \ - "0.0314833000, 0.0353929000, 0.0444009000, 0.0641381000, 0.1133548000, 0.2479923000, 0.6650277000", \ - "0.0315141000, 0.0359937000, 0.0452239000, 0.0641292000, 0.1133761000, 0.2477725000, 0.6647816000", \ - "0.0316480000, 0.0354194000, 0.0443617000, 0.0645887000, 0.1129032000, 0.2477243000, 0.6676824000", \ - "0.0315469000, 0.0357244000, 0.0444040000, 0.0644476000, 0.1128146000, 0.2480549000, 0.6644746000", \ - "0.0352335000, 0.0391824000, 0.0479881000, 0.0679601000, 0.1148233000, 0.2486552000, 0.6656584000", \ - "0.0455687000, 0.0499364000, 0.0597215000, 0.0808303000, 0.1293036000, 0.2580479000, 0.6646423000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0301403000, 0.0361729000, 0.0513045000, 0.0891168000, 0.1972985000, 0.5274175000, 1.5039389000", \ - "0.0302001000, 0.0364008000, 0.0514958000, 0.0890569000, 0.1968919000, 0.5269923000, 1.5043606000", \ - "0.0302540000, 0.0361001000, 0.0514766000, 0.0890435000, 0.1973740000, 0.5267400000, 1.5006648000", \ - "0.0301818000, 0.0362688000, 0.0514915000, 0.0889862000, 0.1966199000, 0.5261998000, 1.5033124000", \ - "0.0306909000, 0.0366265000, 0.0517102000, 0.0897640000, 0.1972667000, 0.5275773000, 1.5030961000", \ - "0.0344013000, 0.0408743000, 0.0564693000, 0.0939745000, 0.1996430000, 0.5275398000, 1.5027471000", \ - "0.0443124000, 0.0514371000, 0.0677370000, 0.1050294000, 0.2068988000, 0.5295724000, 1.4995670000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2111182000, 0.2179423000, 0.2328294000, 0.2621067000, 0.3187131000, 0.4416582000, 0.7653337000", \ - "0.2151521000, 0.2219633000, 0.2368122000, 0.2660104000, 0.3227374000, 0.4454289000, 0.7690017000", \ - "0.2262040000, 0.2330354000, 0.2480517000, 0.2772191000, 0.3339129000, 0.4562418000, 0.7796614000", \ - "0.2551325000, 0.2619365000, 0.2766365000, 0.3057788000, 0.3624749000, 0.4851546000, 0.8087246000", \ - "0.3236837000, 0.3304870000, 0.3452832000, 0.3743914000, 0.4311316000, 0.5545478000, 0.8780865000", \ - "0.4788206000, 0.4864045000, 0.5021438000, 0.5319910000, 0.5892060000, 0.7128560000, 1.0366873000", \ - "0.7406829000, 0.7505196000, 0.7715359000, 0.8091833000, 0.8747832000, 1.0042074000, 1.3299118000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1414645000, 0.1489740000, 0.1664053000, 0.2041040000, 0.2920023000, 0.5285088000, 1.2090909000", \ - "0.1463194000, 0.1539032000, 0.1711649000, 0.2088281000, 0.2967783000, 0.5333666000, 1.2142392000", \ - "0.1549689000, 0.1625123000, 0.1798803000, 0.2176053000, 0.3055052000, 0.5422032000, 1.2247150000", \ - "0.1707052000, 0.1782376000, 0.1956610000, 0.2333410000, 0.3210779000, 0.5576881000, 1.2405394000", \ - "0.1990898000, 0.2068876000, 0.2247664000, 0.2627570000, 0.3507218000, 0.5882382000, 1.2692100000", \ - "0.2405107000, 0.2491694000, 0.2685909000, 0.3091897000, 0.3993872000, 0.6366139000, 1.3212941000", \ - "0.2758923000, 0.2868238000, 0.3109799000, 0.3577985000, 0.4527563000, 0.6913554000, 1.3722923000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0317660000, 0.0354255000, 0.0443924000, 0.0644714000, 0.1132413000, 0.2474762000, 0.6649921000", \ - "0.0316758000, 0.0356740000, 0.0443982000, 0.0649139000, 0.1131805000, 0.2478404000, 0.6654619000", \ - "0.0317553000, 0.0359292000, 0.0446417000, 0.0640003000, 0.1131048000, 0.2482719000, 0.6659107000", \ - "0.0315211000, 0.0358649000, 0.0446001000, 0.0650037000, 0.1131917000, 0.2475230000, 0.6656107000", \ - "0.0315313000, 0.0357453000, 0.0446384000, 0.0649595000, 0.1126693000, 0.2478367000, 0.6641578000", \ - "0.0369156000, 0.0412785000, 0.0491152000, 0.0677975000, 0.1147127000, 0.2486979000, 0.6645916000", \ - "0.0544886000, 0.0587903000, 0.0686758000, 0.0882177000, 0.1310979000, 0.2580309000, 0.6679076000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0283892000, 0.0342655000, 0.0489390000, 0.0864779000, 0.1947288000, 0.5247459000, 1.5053647000", \ - "0.0284276000, 0.0342583000, 0.0489083000, 0.0863276000, 0.1947411000, 0.5244029000, 1.5057733000", \ - "0.0283786000, 0.0343273000, 0.0487168000, 0.0864486000, 0.1946370000, 0.5241091000, 1.5036165000", \ - "0.0283882000, 0.0343677000, 0.0488698000, 0.0864575000, 0.1946385000, 0.5260427000, 1.5000918000", \ - "0.0297968000, 0.0355634000, 0.0501283000, 0.0872624000, 0.1953706000, 0.5263418000, 1.5023787000", \ - "0.0341588000, 0.0406835000, 0.0558256000, 0.0926366000, 0.1982863000, 0.5254051000, 1.4990675000", \ - "0.0461103000, 0.0532856000, 0.0694928000, 0.1058282000, 0.2063756000, 0.5287485000, 1.4971294000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1216515000, 0.1269630000, 0.1390729000, 0.1643708000, 0.2167393000, 0.3345840000, 0.6557234000", \ - "0.1270734000, 0.1324292000, 0.1444920000, 0.1698806000, 0.2222082000, 0.3400434000, 0.6607756000", \ - "0.1402548000, 0.1455662000, 0.1577047000, 0.1830069000, 0.2353132000, 0.3531393000, 0.6739987000", \ - "0.1721552000, 0.1774684000, 0.1894775000, 0.2148774000, 0.2672438000, 0.3851187000, 0.7061535000", \ - "0.2476494000, 0.2529695000, 0.2649871000, 0.2896573000, 0.3429322000, 0.4609572000, 0.7817092000", \ - "0.3868934000, 0.3936855000, 0.4086339000, 0.4390530000, 0.4960866000, 0.6167160000, 0.9381089000", \ - "0.6122733000, 0.6213062000, 0.6414941000, 0.6805074000, 0.7524110000, 0.8840780000, 1.2072889000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1581799000, 0.1660651000, 0.1840712000, 0.2230132000, 0.3122822000, 0.5503871000, 1.2335771000", \ - "0.1622208000, 0.1701507000, 0.1881322000, 0.2269413000, 0.3162002000, 0.5543834000, 1.2386075000", \ - "0.1700766000, 0.1780530000, 0.1959888000, 0.2349249000, 0.3242043000, 0.5622379000, 1.2452780000", \ - "0.1864501000, 0.1943690000, 0.2124472000, 0.2512738000, 0.3403839000, 0.5786443000, 1.2601997000", \ - "0.2215598000, 0.2296722000, 0.2478656000, 0.2871632000, 0.3764629000, 0.6138782000, 1.2964820000", \ - "0.2772950000, 0.2862677000, 0.3063043000, 0.3474664000, 0.4385725000, 0.6771871000, 1.3603326000", \ - "0.3335419000, 0.3447284000, 0.3690534000, 0.4158648000, 0.5112468000, 0.7507711000, 1.4331825000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0211573000, 0.0246930000, 0.0337516000, 0.0549102000, 0.1031692000, 0.2385084000, 0.6608254000", \ - "0.0211590000, 0.0248721000, 0.0337723000, 0.0545504000, 0.1030001000, 0.2390817000, 0.6598558000", \ - "0.0210622000, 0.0246627000, 0.0335087000, 0.0547198000, 0.1033031000, 0.2391874000, 0.6588640000", \ - "0.0210687000, 0.0246223000, 0.0337077000, 0.0546854000, 0.1030496000, 0.2387155000, 0.6604800000", \ - "0.0219977000, 0.0254132000, 0.0342100000, 0.0554711000, 0.1035488000, 0.2392025000, 0.6596076000", \ - "0.0318628000, 0.0362696000, 0.0451127000, 0.0659914000, 0.1117812000, 0.2420184000, 0.6615055000", \ - "0.0485430000, 0.0536012000, 0.0646554000, 0.0897939000, 0.1377365000, 0.2570504000, 0.6600527000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0303242000, 0.0363822000, 0.0515020000, 0.0890854000, 0.1972454000, 0.5270286000, 1.5042981000", \ - "0.0301424000, 0.0361729000, 0.0512876000, 0.0890557000, 0.1973765000, 0.5275436000, 1.5031738000", \ - "0.0302059000, 0.0363825000, 0.0514961000, 0.0890633000, 0.1971343000, 0.5268830000, 1.5041934000", \ - "0.0301104000, 0.0361236000, 0.0512348000, 0.0889037000, 0.1973348000, 0.5271621000, 1.5021341000", \ - "0.0311423000, 0.0371826000, 0.0521917000, 0.0898961000, 0.1974372000, 0.5261989000, 1.4985153000", \ - "0.0358165000, 0.0421363000, 0.0573309000, 0.0946872000, 0.2002964000, 0.5280246000, 1.5040176000", \ - "0.0482595000, 0.0553386000, 0.0706178000, 0.1072716000, 0.2071777000, 0.5305529000, 1.4964346000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1115644000, 0.1167317000, 0.1284885000, 0.1535189000, 0.2053578000, 0.3231161000, 0.6441827000", \ - "0.1172322000, 0.1223692000, 0.1341333000, 0.1591052000, 0.2111043000, 0.3288791000, 0.6497402000", \ - "0.1303321000, 0.1353030000, 0.1472303000, 0.1719564000, 0.2240930000, 0.3418587000, 0.6627471000", \ - "0.1621439000, 0.1673156000, 0.1790803000, 0.2039960000, 0.2561105000, 0.3738008000, 0.6946413000", \ - "0.2358364000, 0.2410765000, 0.2529263000, 0.2781522000, 0.3305733000, 0.4485698000, 0.7693174000", \ - "0.3680136000, 0.3749957000, 0.3902066000, 0.4203894000, 0.4788710000, 0.6001850000, 0.9210029000", \ - "0.5806149000, 0.5898509000, 0.6099951000, 0.6496584000, 0.7231127000, 0.8562229000, 1.1796943000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1502279000, 0.1581275000, 0.1762519000, 0.2149726000, 0.3041173000, 0.5423640000, 1.2240011000", \ - "0.1539860000, 0.1618847000, 0.1799246000, 0.2188825000, 0.3081204000, 0.5458315000, 1.2278412000", \ - "0.1623319000, 0.1702551000, 0.1882942000, 0.2271165000, 0.3164033000, 0.5545526000, 1.2386743000", \ - "0.1817691000, 0.1897008000, 0.2076778000, 0.2465911000, 0.3358040000, 0.5739091000, 1.2588108000", \ - "0.2239890000, 0.2320044000, 0.2502630000, 0.2895400000, 0.3787469000, 0.6162231000, 1.2997908000", \ - "0.2885858000, 0.2975732000, 0.3174688000, 0.3583487000, 0.4493392000, 0.6885176000, 1.3721702000", \ - "0.3533798000, 0.3645220000, 0.3890770000, 0.4355442000, 0.5297323000, 0.7689153000, 1.4519905000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0200540000, 0.0237768000, 0.0324743000, 0.0534770000, 0.1027768000, 0.2384699000, 0.6617598000", \ - "0.0201162000, 0.0236065000, 0.0325359000, 0.0537783000, 0.1024572000, 0.2381644000, 0.6603797000", \ - "0.0200288000, 0.0239058000, 0.0323755000, 0.0537613000, 0.1026928000, 0.2382106000, 0.6604538000", \ - "0.0200800000, 0.0238091000, 0.0324167000, 0.0535425000, 0.1028309000, 0.2387247000, 0.6642227000", \ - "0.0218334000, 0.0253358000, 0.0337320000, 0.0544530000, 0.1032145000, 0.2389676000, 0.6579393000", \ - "0.0321574000, 0.0362399000, 0.0455008000, 0.0667051000, 0.1131940000, 0.2426926000, 0.6591164000", \ - "0.0490479000, 0.0543058000, 0.0656286000, 0.0913722000, 0.1405603000, 0.2593945000, 0.6596406000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0300662000, 0.0360743000, 0.0512165000, 0.0890057000, 0.1972856000, 0.5271146000, 1.5009531000", \ - "0.0300052000, 0.0361287000, 0.0514954000, 0.0890909000, 0.1969272000, 0.5266216000, 1.5026591000", \ - "0.0301702000, 0.0362021000, 0.0513019000, 0.0890641000, 0.1973034000, 0.5276092000, 1.5035438000", \ - "0.0302075000, 0.0363707000, 0.0514322000, 0.0889758000, 0.1969272000, 0.5276650000, 1.5004267000", \ - "0.0313986000, 0.0373812000, 0.0525233000, 0.0900315000, 0.1975725000, 0.5273848000, 1.5009327000", \ - "0.0370212000, 0.0431203000, 0.0580483000, 0.0945564000, 0.2007868000, 0.5274834000, 1.4998793000", \ - "0.0500880000, 0.0570709000, 0.0719650000, 0.1075225000, 0.2065170000, 0.5298565000, 1.4975321000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0937965000, 0.0986844000, 0.1099028000, 0.1336907000, 0.1839837000, 0.3002107000, 0.6204981000", \ - "0.0993590000, 0.1042004000, 0.1154263000, 0.1390179000, 0.1893504000, 0.3055316000, 0.6256492000", \ - "0.1128552000, 0.1177305000, 0.1289082000, 0.1526346000, 0.2029636000, 0.3191732000, 0.6391964000", \ - "0.1449948000, 0.1498979000, 0.1610241000, 0.1848892000, 0.2352823000, 0.3515906000, 0.6721270000", \ - "0.2166164000, 0.2218579000, 0.2336399000, 0.2582395000, 0.3092839000, 0.4259026000, 0.7465165000", \ - "0.3368225000, 0.3437785000, 0.3591286000, 0.3898036000, 0.4484747000, 0.5693453000, 0.8899146000", \ - "0.5304169000, 0.5396200000, 0.5598376000, 0.5998901000, 0.6749278000, 0.8082277000, 1.1298015000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.1392899000, 0.1471836000, 0.1652129000, 0.2041533000, 0.2934038000, 0.5316614000, 1.2154122000", \ - "0.1428769000, 0.1507966000, 0.1688231000, 0.2077746000, 0.2970150000, 0.5345302000, 1.2162640000", \ - "0.1515849000, 0.1594906000, 0.1775939000, 0.2164265000, 0.3055607000, 0.5436557000, 1.2260891000", \ - "0.1728260000, 0.1806974000, 0.1987891000, 0.2377196000, 0.3269437000, 0.5645651000, 1.2460430000", \ - "0.2203110000, 0.2282497000, 0.2464047000, 0.2855831000, 0.3745105000, 0.6117840000, 1.2955094000", \ - "0.2881172000, 0.2973281000, 0.3164125000, 0.3568124000, 0.4476403000, 0.6862092000, 1.3689627000", \ - "0.3538413000, 0.3653273000, 0.3899794000, 0.4361545000, 0.5292550000, 0.7671277000, 1.4512473000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0185178000, 0.0219267000, 0.0304821000, 0.0514189000, 0.0999143000, 0.2362299000, 0.6589642000", \ - "0.0184807000, 0.0219149000, 0.0304090000, 0.0514855000, 0.1000703000, 0.2370731000, 0.6564860000", \ - "0.0184703000, 0.0219054000, 0.0304847000, 0.0513190000, 0.0998615000, 0.2369771000, 0.6571101000", \ - "0.0183998000, 0.0219020000, 0.0304084000, 0.0513457000, 0.0999077000, 0.2361421000, 0.6594978000", \ - "0.0221991000, 0.0254468000, 0.0334512000, 0.0535030000, 0.1009707000, 0.2363922000, 0.6598115000", \ - "0.0323253000, 0.0365580000, 0.0463348000, 0.0676937000, 0.1136994000, 0.2423034000, 0.6604336000", \ - "0.0490510000, 0.0543364000, 0.0668554000, 0.0931695000, 0.1422612000, 0.2604950000, 0.6587521000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0302122000, 0.0364038000, 0.0515090000, 0.0891206000, 0.1966653000, 0.5272927000, 1.5031965000", \ - "0.0301662000, 0.0363612000, 0.0513460000, 0.0889993000, 0.1970590000, 0.5255403000, 1.4992003000", \ - "0.0301202000, 0.0364798000, 0.0512591000, 0.0891337000, 0.1968586000, 0.5274927000, 1.5034437000", \ - "0.0303057000, 0.0363851000, 0.0512400000, 0.0889653000, 0.1969650000, 0.5254610000, 1.5011384000", \ - "0.0310058000, 0.0369858000, 0.0520440000, 0.0898380000, 0.1975507000, 0.5270809000, 1.4989009000", \ - "0.0381053000, 0.0438956000, 0.0583276000, 0.0942733000, 0.2011488000, 0.5285099000, 1.5044103000", \ - "0.0531348000, 0.0596148000, 0.0740805000, 0.1073808000, 0.2059513000, 0.5310352000, 1.4979399000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111a_4") { - leakage_power () { - value : 0.0074436000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0304454000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0406505000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0303491000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0088315000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0077691000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0075078000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0074553000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0081425000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0074963000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0080641000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0074860000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0093144000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0082135000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0075078000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0074553000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0081425000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0074963000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0080642000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0074860000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0075948000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0082134000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0075078000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0074553000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0081425000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0074963000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0080641000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0074860000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0068680000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0082135000; - when : "A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0405379000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0303464000; - when : "!A1&!A2&!B1&!C1&!D1"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__o2111a"; - cell_leakage_power : 0.0119764800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076095000, 0.0076056000, 0.0075966000, 0.0075941000, 0.0075883000, 0.0075750000, 0.0075443000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007607900, -0.007607300, -0.007605900, -0.007603400, -0.007597400, -0.007583700, -0.007552000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046150000; - } - pin ("A2") { - capacitance : 0.0046810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043270000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081752000, 0.0081835000, 0.0082028000, 0.0082042000, 0.0082075000, 0.0082152000, 0.0082328000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008226200, -0.008221400, -0.008210100, -0.008211000, -0.008212700, -0.008216800, -0.008226200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050340000; - } - pin ("B1") { - capacitance : 0.0043640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075614000, 0.0075627000, 0.0075659000, 0.0075662000, 0.0075668000, 0.0075685000, 0.0075724000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007573100, -0.007569200, -0.007560400, -0.007561200, -0.007562900, -0.007566800, -0.007575700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045280000; - } - pin ("C1") { - capacitance : 0.0047180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086781000, 0.0086731000, 0.0086618000, 0.0086915000, 0.0087598000, 0.0089175000, 0.0092809000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008064500, -0.008061300, -0.008053800, -0.008051900, -0.008047400, -0.008036900, -0.008012700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048590000; - } - pin ("D1") { - capacitance : 0.0043290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092212000, 0.0092207000, 0.0092195000, 0.0092177000, 0.0092137000, 0.0092046000, 0.0091836000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006132500, -0.006140500, -0.006159000, -0.006141400, -0.006100600, -0.006006500, -0.005789600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044520000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1&D1) | (A2&B1&C1&D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0441783000, 0.0423312000, 0.0368404000, 0.0219727000, -0.032644500, -0.221098800, -0.835070300", \ - "0.0439196000, 0.0420672000, 0.0365789000, 0.0216268000, -0.032866000, -0.221348700, -0.835252400", \ - "0.0437311000, 0.0419283000, 0.0364526000, 0.0211689000, -0.033198100, -0.221611500, -0.835295800", \ - "0.0434379000, 0.0418341000, 0.0360671000, 0.0210860000, -0.033464200, -0.221829500, -0.835772300", \ - "0.0431806000, 0.0412812000, 0.0358773000, 0.0205783000, -0.033851700, -0.222188500, -0.835980200", \ - "0.0432206000, 0.0413624000, 0.0358314000, 0.0203278000, -0.034125600, -0.222516300, -0.836228300", \ - "0.0538204000, 0.0517399000, 0.0454634000, 0.0265783000, -0.033153300, -0.222116200, -0.835947000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0401073000, 0.0419431000, 0.0480572000, 0.0674365000, 0.1276588000, 0.3169253000, 0.9278031000", \ - "0.0399501000, 0.0417902000, 0.0478449000, 0.0673304000, 0.1273674000, 0.3168929000, 0.9255981000", \ - "0.0397238000, 0.0416235000, 0.0476411000, 0.0670765000, 0.1272241000, 0.3164714000, 0.9235293000", \ - "0.0392998000, 0.0411089000, 0.0471468000, 0.0667367000, 0.1269228000, 0.3161890000, 0.9283335000", \ - "0.0390084000, 0.0408490000, 0.0467952000, 0.0663383000, 0.1263404000, 0.3160366000, 0.9250655000", \ - "0.0401578000, 0.0419167000, 0.0475526000, 0.0660016000, 0.1260606000, 0.3151828000, 0.9230707000", \ - "0.0415114000, 0.0432185000, 0.0488961000, 0.0675401000, 0.1272383000, 0.3163414000, 0.9210078000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0400325000, 0.0380623000, 0.0326307000, 0.0176223000, -0.036888000, -0.225365800, -0.839374700", \ - "0.0395855000, 0.0377455000, 0.0322777000, 0.0170068000, -0.037351800, -0.225736100, -0.839486000", \ - "0.0392409000, 0.0377309000, 0.0322803000, 0.0168785000, -0.037621300, -0.226025000, -0.839808200", \ - "0.0388424000, 0.0369467000, 0.0315701000, 0.0162804000, -0.038086900, -0.226449000, -0.840024600", \ - "0.0386020000, 0.0367262000, 0.0312499000, 0.0160692000, -0.038390100, -0.226772600, -0.840389500", \ - "0.0394603000, 0.0376588000, 0.0319804000, 0.0175169000, -0.037524300, -0.226380800, -0.840069300", \ - "0.0511154000, 0.0489289000, 0.0424276000, 0.0231701000, -0.036647100, -0.225452700, -0.838904900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0374524000, 0.0392533000, 0.0453066000, 0.0648466000, 0.1246752000, 0.3130562000, 0.9217195000", \ - "0.0374387000, 0.0393142000, 0.0453817000, 0.0646340000, 0.1245410000, 0.3130850000, 0.9209969000", \ - "0.0373020000, 0.0390093000, 0.0451003000, 0.0646445000, 0.1244497000, 0.3130885000, 0.9215681000", \ - "0.0366623000, 0.0384396000, 0.0445449000, 0.0639424000, 0.1239457000, 0.3124492000, 0.9211862000", \ - "0.0360303000, 0.0378705000, 0.0439059000, 0.0632692000, 0.1229789000, 0.3118499000, 0.9210535000", \ - "0.0372267000, 0.0389945000, 0.0447376000, 0.0630050000, 0.1228420000, 0.3112282000, 0.9193957000", \ - "0.0389586000, 0.0406142000, 0.0462949000, 0.0647147000, 0.1236666000, 0.3127486000, 0.9171360000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0368966000, 0.0354680000, 0.0313584000, 0.0174107000, -0.037479300, -0.227073000, -0.841453900", \ - "0.0366596000, 0.0352378000, 0.0311423000, 0.0171783000, -0.037729400, -0.227264600, -0.841648200", \ - "0.0364813000, 0.0350407000, 0.0308956000, 0.0168165000, -0.038050100, -0.227582900, -0.841982500", \ - "0.0358290000, 0.0343847000, 0.0302759000, 0.0161300000, -0.038710700, -0.228172000, -0.842536700", \ - "0.0355085000, 0.0340289000, 0.0297900000, 0.0156112000, -0.039310100, -0.228556000, -0.842722700", \ - "0.0380899000, 0.0361935000, 0.0312629000, 0.0152534000, -0.039317300, -0.228609300, -0.842662000", \ - "0.0485055000, 0.0464353000, 0.0401718000, 0.0212559000, -0.038055900, -0.227748700, -0.841371600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0399451000, 0.0417728000, 0.0478068000, 0.0673825000, 0.1274831000, 0.3171974000, 0.9293730000", \ - "0.0398570000, 0.0416655000, 0.0476854000, 0.0672793000, 0.1273654000, 0.3170930000, 0.9292738000", \ - "0.0396069000, 0.0414740000, 0.0474414000, 0.0669336000, 0.1271887000, 0.3169004000, 0.9255274000", \ - "0.0392621000, 0.0410849000, 0.0470949000, 0.0666371000, 0.1269409000, 0.3163438000, 0.9286092000", \ - "0.0390649000, 0.0408461000, 0.0469362000, 0.0663473000, 0.1263922000, 0.3161739000, 0.9254726000", \ - "0.0401562000, 0.0419006000, 0.0476333000, 0.0661043000, 0.1258352000, 0.3153924000, 0.9237969000", \ - "0.0423284000, 0.0439997000, 0.0496205000, 0.0677953000, 0.1275105000, 0.3166045000, 0.9212894000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0325246000, 0.0311721000, 0.0269005000, 0.0125881000, -0.042857900, -0.232883900, -0.847494600", \ - "0.0323361000, 0.0310230000, 0.0266804000, 0.0124524000, -0.042964400, -0.232991100, -0.847633600", \ - "0.0320342000, 0.0306569000, 0.0265000000, 0.0121164000, -0.043264400, -0.233286200, -0.847917000", \ - "0.0315353000, 0.0302160000, 0.0259110000, 0.0115133000, -0.043890700, -0.233811200, -0.848388700", \ - "0.0310756000, 0.0296626000, 0.0251960000, 0.0105198000, -0.044867400, -0.234542400, -0.848948100", \ - "0.0341848000, 0.0323499000, 0.0264994000, 0.0088055000, -0.045602300, -0.235086000, -0.849231900", \ - "0.0419983000, 0.0399359000, 0.0336344000, 0.0147374000, -0.044488600, -0.234282900, -0.848133400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0406602000, 0.0424492000, 0.0485227000, 0.0679710000, 0.1280500000, 0.3175056000, 0.9261202000", \ - "0.0405330000, 0.0422979000, 0.0483902000, 0.0678463000, 0.1279106000, 0.3174566000, 0.9264191000", \ - "0.0401224000, 0.0419887000, 0.0479577000, 0.0674478000, 0.1276723000, 0.3175467000, 0.9255134000", \ - "0.0396639000, 0.0414611000, 0.0475620000, 0.0671733000, 0.1274046000, 0.3169300000, 0.9280656000", \ - "0.0394639000, 0.0412665000, 0.0472349000, 0.0665172000, 0.1267968000, 0.3163810000, 0.9288188000", \ - "0.0403794000, 0.0421213000, 0.0477097000, 0.0660910000, 0.1261708000, 0.3153532000, 0.9254748000", \ - "0.0430264000, 0.0446790000, 0.0502479000, 0.0685309000, 0.1275100000, 0.3170297000, 0.9214530000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0249207000, 0.0237062000, 0.0196495000, 0.0053262000, -0.050041500, -0.240254000, -0.855085700", \ - "0.0248493000, 0.0235377000, 0.0193929000, 0.0053413000, -0.050126800, -0.240348900, -0.855186000", \ - "0.0245858000, 0.0232793000, 0.0191660000, 0.0049470000, -0.050486300, -0.240683500, -0.855522600", \ - "0.0240092000, 0.0226792000, 0.0185993000, 0.0042362000, -0.051137300, -0.241187700, -0.855945900", \ - "0.0238896000, 0.0224045000, 0.0180196000, 0.0033827000, -0.052133700, -0.241867400, -0.856223600", \ - "0.0291711000, 0.0272813000, 0.0214035000, 0.0030911000, -0.052363800, -0.241744400, -0.856104700", \ - "0.0363236000, 0.0342365000, 0.0279619000, 0.0090390000, -0.049426900, -0.239081600, -0.853840200"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016070190, 0.0051650180, 0.0166005600, 0.0533548200, 0.1714844000, 0.5511573000"); - values("0.0386657000, 0.0404757000, 0.0466355000, 0.0660187000, 0.1262190000, 0.3158923000, 0.9239549000", \ - "0.0384151000, 0.0402917000, 0.0463364000, 0.0657421000, 0.1261072000, 0.3160090000, 0.9248860000", \ - "0.0381134000, 0.0399122000, 0.0460337000, 0.0655829000, 0.1258048000, 0.3157250000, 0.9282169000", \ - "0.0376273000, 0.0393949000, 0.0455156000, 0.0651434000, 0.1252406000, 0.3149108000, 0.9231662000", \ - "0.0376440000, 0.0394706000, 0.0454046000, 0.0645595000, 0.1246346000, 0.3144336000, 0.9270766000", \ - "0.0391320000, 0.0408681000, 0.0464763000, 0.0644902000, 0.1244804000, 0.3134627000, 0.9238238000", \ - "0.0426738000, 0.0442880000, 0.0497616000, 0.0680749000, 0.1268561000, 0.3157442000, 0.9215466000"); - } - } - max_capacitance : 0.5511570000; - max_transition : 1.5038940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.2600758000, 0.2648713000, 0.2772687000, 0.3043159000, 0.3598264000, 0.4810825000, 0.8100508000", \ - "0.2650182000, 0.2698231000, 0.2822260000, 0.3094296000, 0.3648625000, 0.4859994000, 0.8146566000", \ - "0.2779044000, 0.2827388000, 0.2950699000, 0.3223393000, 0.3778992000, 0.4987580000, 0.8283942000", \ - "0.3061385000, 0.3109706000, 0.3232873000, 0.3503926000, 0.4058213000, 0.5268018000, 0.8560520000", \ - "0.3690795000, 0.3739436000, 0.3861925000, 0.4134377000, 0.4689025000, 0.5903240000, 0.9196255000", \ - "0.5107875000, 0.5157632000, 0.5286565000, 0.5563661000, 0.6121743000, 0.7334398000, 1.0628854000", \ - "0.7715302000, 0.7774075000, 0.7924433000, 0.8248662000, 0.8875569000, 1.0168242000, 1.3494149000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1830092000, 0.1885146000, 0.2031867000, 0.2377567000, 0.3198103000, 0.5449343000, 1.2522269000", \ - "0.1870629000, 0.1925903000, 0.2073191000, 0.2418648000, 0.3238095000, 0.5492934000, 1.2573618000", \ - "0.1951789000, 0.2006789000, 0.2153429000, 0.2498819000, 0.3319252000, 0.5573025000, 1.2653466000", \ - "0.2097039000, 0.2150895000, 0.2297776000, 0.2644948000, 0.3464835000, 0.5714950000, 1.2812775000", \ - "0.2368089000, 0.2424146000, 0.2571729000, 0.2920033000, 0.3740696000, 0.5997199000, 1.3076058000", \ - "0.2797568000, 0.2857617000, 0.3014788000, 0.3382440000, 0.4223780000, 0.6489594000, 1.3598693000", \ - "0.3265177000, 0.3335000000, 0.3517753000, 0.3927279000, 0.4823120000, 0.7113816000, 1.4191953000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0359789000, 0.0389614000, 0.0456967000, 0.0631749000, 0.1054377000, 0.2319956000, 0.6562741000", \ - "0.0359700000, 0.0389284000, 0.0455560000, 0.0630060000, 0.1061089000, 0.2318342000, 0.6554182000", \ - "0.0357409000, 0.0385259000, 0.0458337000, 0.0629129000, 0.1060325000, 0.2320165000, 0.6547803000", \ - "0.0358009000, 0.0385149000, 0.0456455000, 0.0630163000, 0.1052437000, 0.2317773000, 0.6559253000", \ - "0.0359460000, 0.0388269000, 0.0460507000, 0.0629994000, 0.1061465000, 0.2315676000, 0.6561190000", \ - "0.0383700000, 0.0411142000, 0.0481017000, 0.0646310000, 0.1068361000, 0.2324090000, 0.6565896000", \ - "0.0497523000, 0.0524390000, 0.0603802000, 0.0786219000, 0.1214499000, 0.2431776000, 0.6586279000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0325949000, 0.0371662000, 0.0488968000, 0.0801516000, 0.1722926000, 0.4803030000, 1.4980002000", \ - "0.0326157000, 0.0371006000, 0.0489051000, 0.0801975000, 0.1725151000, 0.4805744000, 1.4999246000", \ - "0.0329951000, 0.0371766000, 0.0487437000, 0.0801902000, 0.1726507000, 0.4809988000, 1.5000567000", \ - "0.0329048000, 0.0369969000, 0.0490606000, 0.0800941000, 0.1725102000, 0.4805559000, 1.5035541000", \ - "0.0334208000, 0.0377114000, 0.0495286000, 0.0808483000, 0.1727613000, 0.4809510000, 1.4996735000", \ - "0.0365236000, 0.0409789000, 0.0533265000, 0.0846674000, 0.1761202000, 0.4820694000, 1.5027664000", \ - "0.0450517000, 0.0500967000, 0.0632803000, 0.0958234000, 0.1837377000, 0.4837178000, 1.4991788000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.2416986000, 0.2465075000, 0.2589034000, 0.2860307000, 0.3413458000, 0.4625981000, 0.7916664000", \ - "0.2450555000, 0.2498540000, 0.2622564000, 0.2896452000, 0.3450120000, 0.4663486000, 0.7958327000", \ - "0.2554710000, 0.2602525000, 0.2726276000, 0.2999349000, 0.3553917000, 0.4768388000, 0.8062944000", \ - "0.2811763000, 0.2859745000, 0.2984335000, 0.3256602000, 0.3811274000, 0.5026439000, 0.8316006000", \ - "0.3464939000, 0.3512926000, 0.3637380000, 0.3910535000, 0.4464938000, 0.5678258000, 0.8974329000", \ - "0.4977654000, 0.5028099000, 0.5157421000, 0.5437792000, 0.5990355000, 0.7211132000, 1.0506951000", \ - "0.7574630000, 0.7637870000, 0.7801149000, 0.8156049000, 0.8806124000, 1.0085205000, 1.3412962000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1595379000, 0.1648804000, 0.1790559000, 0.2128464000, 0.2932755000, 0.5161404000, 1.2239039000", \ - "0.1643021000, 0.1696299000, 0.1837976000, 0.2174247000, 0.2978245000, 0.5213908000, 1.2306339000", \ - "0.1724549000, 0.1776871000, 0.1918807000, 0.2256221000, 0.3060609000, 0.5290662000, 1.2363800000", \ - "0.1865313000, 0.1918663000, 0.2060766000, 0.2398279000, 0.3202265000, 0.5432466000, 1.2514185000", \ - "0.2123494000, 0.2178638000, 0.2323293000, 0.2664081000, 0.3472066000, 0.5705683000, 1.2791064000", \ - "0.2513070000, 0.2572270000, 0.2728528000, 0.3091558000, 0.3925932000, 0.6177195000, 1.3280740000", \ - "0.2891046000, 0.2963009000, 0.3148430000, 0.3567162000, 0.4453992000, 0.6731490000, 1.3805239000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0359026000, 0.0388235000, 0.0456067000, 0.0629610000, 0.1065362000, 0.2317891000, 0.6554544000", \ - "0.0357602000, 0.0389293000, 0.0455949000, 0.0629758000, 0.1061759000, 0.2317056000, 0.6547772000", \ - "0.0357421000, 0.0387604000, 0.0458229000, 0.0629657000, 0.1061609000, 0.2316911000, 0.6545449000", \ - "0.0362265000, 0.0385955000, 0.0461672000, 0.0628312000, 0.1061898000, 0.2317684000, 0.6552551000", \ - "0.0361842000, 0.0390283000, 0.0456740000, 0.0628321000, 0.1062124000, 0.2318132000, 0.6544300000", \ - "0.0397538000, 0.0424307000, 0.0494805000, 0.0659171000, 0.1080009000, 0.2327799000, 0.6555006000", \ - "0.0572859000, 0.0605428000, 0.0692263000, 0.0872677000, 0.1258827000, 0.2440948000, 0.6583054000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0314902000, 0.0355061000, 0.0471129000, 0.0781078000, 0.1703365000, 0.4790045000, 1.5002094000", \ - "0.0313036000, 0.0356929000, 0.0472873000, 0.0783000000, 0.1702252000, 0.4783920000, 1.4992946000", \ - "0.0314692000, 0.0354388000, 0.0469862000, 0.0781071000, 0.1703166000, 0.4792073000, 1.5012666000", \ - "0.0316583000, 0.0354666000, 0.0469965000, 0.0780602000, 0.1702174000, 0.4786749000, 1.5005920000", \ - "0.0325892000, 0.0366665000, 0.0479263000, 0.0791107000, 0.1712350000, 0.4790540000, 1.5029910000", \ - "0.0362683000, 0.0404855000, 0.0528866000, 0.0839315000, 0.1747142000, 0.4806874000, 1.5008672000", \ - "0.0464472000, 0.0515245000, 0.0647803000, 0.0961066000, 0.1840317000, 0.4835699000, 1.4974951000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1265083000, 0.1300285000, 0.1393501000, 0.1613223000, 0.2103666000, 0.3239552000, 0.6487543000", \ - "0.1319075000, 0.1354243000, 0.1447653000, 0.1668033000, 0.2158120000, 0.3294144000, 0.6541658000", \ - "0.1449895000, 0.1484972000, 0.1577567000, 0.1798159000, 0.2289424000, 0.3425834000, 0.6676151000", \ - "0.1770172000, 0.1805288000, 0.1898412000, 0.2117687000, 0.2610130000, 0.3747012000, 0.6994024000", \ - "0.2517979000, 0.2552586000, 0.2645635000, 0.2857818000, 0.3351406000, 0.4488228000, 0.7737133000", \ - "0.3924484000, 0.3968623000, 0.4082844000, 0.4337422000, 0.4879239000, 0.6049334000, 0.9301586000", \ - "0.6203140000, 0.6260933000, 0.6410597000, 0.6744612000, 0.7420221000, 0.8718415000, 1.2001035000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1755473000, 0.1811152000, 0.1957812000, 0.2305338000, 0.3124238000, 0.5378470000, 1.2478848000", \ - "0.1795886000, 0.1850705000, 0.1997424000, 0.2345258000, 0.3163764000, 0.5418415000, 1.2521987000", \ - "0.1877870000, 0.1933000000, 0.2079884000, 0.2426318000, 0.3246045000, 0.5501236000, 1.2586245000", \ - "0.2046628000, 0.2101800000, 0.2248382000, 0.2596098000, 0.3415926000, 0.5667460000, 1.2773843000", \ - "0.2410533000, 0.2466437000, 0.2615156000, 0.2964596000, 0.3783626000, 0.6040391000, 1.3123037000", \ - "0.3010741000, 0.3072150000, 0.3231971000, 0.3602133000, 0.4445640000, 0.6714015000, 1.3812174000", \ - "0.3659504000, 0.3733130000, 0.3926781000, 0.4349766000, 0.5243923000, 0.7530433000, 1.4623541000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0216186000, 0.0239678000, 0.0305892000, 0.0484225000, 0.0931386000, 0.2196729000, 0.6488732000", \ - "0.0216142000, 0.0239239000, 0.0304852000, 0.0482961000, 0.0930967000, 0.2195584000, 0.6499278000", \ - "0.0216042000, 0.0239771000, 0.0305132000, 0.0484026000, 0.0930807000, 0.2193363000, 0.6489235000", \ - "0.0216093000, 0.0239559000, 0.0304680000, 0.0483926000, 0.0930162000, 0.2191810000, 0.6502928000", \ - "0.0222338000, 0.0244938000, 0.0310883000, 0.0487266000, 0.0932591000, 0.2198127000, 0.6488874000", \ - "0.0320039000, 0.0342094000, 0.0415937000, 0.0589797000, 0.1018983000, 0.2231466000, 0.6505829000", \ - "0.0480686000, 0.0514541000, 0.0610273000, 0.0802630000, 0.1264135000, 0.2403762000, 0.6521355000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0328254000, 0.0369638000, 0.0490784000, 0.0803165000, 0.1727243000, 0.4808902000, 1.5038938000", \ - "0.0327813000, 0.0372981000, 0.0490313000, 0.0803552000, 0.1727082000, 0.4808995000, 1.5038307000", \ - "0.0327071000, 0.0372025000, 0.0489878000, 0.0803543000, 0.1726963000, 0.4809086000, 1.5021823000", \ - "0.0326292000, 0.0369426000, 0.0490830000, 0.0802402000, 0.1724637000, 0.4804808000, 1.5036071000", \ - "0.0338232000, 0.0379582000, 0.0495744000, 0.0811912000, 0.1728870000, 0.4809564000, 1.4996430000", \ - "0.0377078000, 0.0423272000, 0.0547528000, 0.0857029000, 0.1765764000, 0.4812765000, 1.5014376000", \ - "0.0492140000, 0.0540794000, 0.0671096000, 0.0981145000, 0.1849427000, 0.4845740000, 1.4996819000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1138815000, 0.1172265000, 0.1261056000, 0.1470974000, 0.1937218000, 0.3038481000, 0.6274958000", \ - "0.1195590000, 0.1229042000, 0.1318068000, 0.1528279000, 0.1994192000, 0.3095228000, 0.6333150000", \ - "0.1329297000, 0.1362623000, 0.1451903000, 0.1661715000, 0.2127868000, 0.3230340000, 0.6465958000", \ - "0.1644375000, 0.1678074000, 0.1766586000, 0.1974861000, 0.2441681000, 0.3543641000, 0.6781338000", \ - "0.2382274000, 0.2416307000, 0.2506109000, 0.2716941000, 0.3187575000, 0.4292931000, 0.7527826000", \ - "0.3710255000, 0.3755459000, 0.3870194000, 0.4128290000, 0.4663195000, 0.5812423000, 0.9049958000", \ - "0.5837362000, 0.5895769000, 0.6046037000, 0.6385093000, 0.7070712000, 0.8363661000, 1.1639856000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1679198000, 0.1734560000, 0.1881323000, 0.2226595000, 0.3046911000, 0.5304591000, 1.2397174000", \ - "0.1718558000, 0.1773871000, 0.1920520000, 0.2265749000, 0.3085946000, 0.5344112000, 1.2438023000", \ - "0.1801861000, 0.1856947000, 0.2003896000, 0.2350289000, 0.3170167000, 0.5426666000, 1.2537205000", \ - "0.1994108000, 0.2049020000, 0.2196039000, 0.2542920000, 0.3363481000, 0.5618913000, 1.2695955000", \ - "0.2425797000, 0.2482100000, 0.2628655000, 0.2978335000, 0.3799522000, 0.6051423000, 1.3151668000", \ - "0.3119874000, 0.3182107000, 0.3342616000, 0.3708055000, 0.4551225000, 0.6826680000, 1.3915428000", \ - "0.3866725000, 0.3941542000, 0.4135874000, 0.4558582000, 0.5443014000, 0.7725315000, 1.4819089000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0200129000, 0.0222805000, 0.0286158000, 0.0455760000, 0.0888133000, 0.2153340000, 0.6471387000", \ - "0.0202052000, 0.0222291000, 0.0284757000, 0.0455754000, 0.0888313000, 0.2153479000, 0.6475410000", \ - "0.0201276000, 0.0224192000, 0.0286169000, 0.0455902000, 0.0887831000, 0.2153131000, 0.6504023000", \ - "0.0201641000, 0.0223041000, 0.0288687000, 0.0456320000, 0.0886650000, 0.2152575000, 0.6474703000", \ - "0.0217148000, 0.0236945000, 0.0301677000, 0.0465159000, 0.0892467000, 0.2150529000, 0.6480917000", \ - "0.0318767000, 0.0343064000, 0.0414223000, 0.0587089000, 0.1001429000, 0.2201356000, 0.6472439000", \ - "0.0483405000, 0.0516983000, 0.0606258000, 0.0822123000, 0.1276244000, 0.2391105000, 0.6505579000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0331136000, 0.0368946000, 0.0487770000, 0.0802926000, 0.1727331000, 0.4808932000, 1.5019413000", \ - "0.0328171000, 0.0370512000, 0.0488220000, 0.0803301000, 0.1726977000, 0.4804198000, 1.5020009000", \ - "0.0327048000, 0.0372112000, 0.0489881000, 0.0803527000, 0.1726869000, 0.4808993000, 1.5031227000", \ - "0.0329171000, 0.0369194000, 0.0486273000, 0.0801643000, 0.1723102000, 0.4805630000, 1.4984389000", \ - "0.0338371000, 0.0377672000, 0.0496003000, 0.0810653000, 0.1725157000, 0.4801348000, 1.5023699000", \ - "0.0385426000, 0.0428178000, 0.0543125000, 0.0858593000, 0.1766628000, 0.4818523000, 1.5003864000", \ - "0.0512897000, 0.0558128000, 0.0682653000, 0.0985224000, 0.1842411000, 0.4847729000, 1.5003929000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1020834000, 0.1053953000, 0.1142888000, 0.1353379000, 0.1826739000, 0.2938784000, 0.6177888000", \ - "0.1076027000, 0.1109234000, 0.1198054000, 0.1409041000, 0.1882216000, 0.2993955000, 0.6232161000", \ - "0.1200810000, 0.1233325000, 0.1326449000, 0.1537097000, 0.2010648000, 0.3123005000, 0.6357309000", \ - "0.1511767000, 0.1545301000, 0.1633483000, 0.1843548000, 0.2318144000, 0.3430708000, 0.6669178000", \ - "0.2192904000, 0.2228493000, 0.2322232000, 0.2539100000, 0.3021367000, 0.4138391000, 0.7374724000", \ - "0.3320571000, 0.3366195000, 0.3484414000, 0.3753503000, 0.4309087000, 0.5483127000, 0.8730697000", \ - "0.5088629000, 0.5146043000, 0.5299477000, 0.5643506000, 0.6362760000, 0.7684415000, 1.0965517000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.1513510000, 0.1568565000, 0.1715056000, 0.2060409000, 0.2881457000, 0.5138882000, 1.2220599000", \ - "0.1547050000, 0.1602175000, 0.1748528000, 0.2095304000, 0.2915171000, 0.5173821000, 1.2261684000", \ - "0.1631298000, 0.1686589000, 0.1833586000, 0.2180438000, 0.3001400000, 0.5257772000, 1.2364688000", \ - "0.1836412000, 0.1891711000, 0.2038856000, 0.2386116000, 0.3206730000, 0.5466375000, 1.2553842000", \ - "0.2309932000, 0.2364837000, 0.2511455000, 0.2860601000, 0.3678906000, 0.5932186000, 1.3039373000", \ - "0.3008376000, 0.3068608000, 0.3223780000, 0.3577389000, 0.4413547000, 0.6695536000, 1.3789817000", \ - "0.3723588000, 0.3797615000, 0.3986820000, 0.4403839000, 0.5261147000, 0.7534480000, 1.4635182000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0195950000, 0.0219444000, 0.0283536000, 0.0457191000, 0.0897679000, 0.2165277000, 0.6503775000", \ - "0.0193650000, 0.0217046000, 0.0280546000, 0.0455991000, 0.0897432000, 0.2166131000, 0.6476383000", \ - "0.0195362000, 0.0216971000, 0.0284479000, 0.0456833000, 0.0897317000, 0.2163823000, 0.6497334000", \ - "0.0194883000, 0.0217223000, 0.0281984000, 0.0458085000, 0.0896996000, 0.2165330000, 0.6476311000", \ - "0.0227205000, 0.0250085000, 0.0311879000, 0.0480090000, 0.0908381000, 0.2167996000, 0.6503669000", \ - "0.0329345000, 0.0357156000, 0.0432636000, 0.0615166000, 0.1039657000, 0.2234429000, 0.6502628000", \ - "0.0490813000, 0.0529286000, 0.0624429000, 0.0842471000, 0.1328182000, 0.2448012000, 0.6514646000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016070200, 0.0051650200, 0.0166006000, 0.0533548000, 0.1714840000, 0.5511570000"); - values("0.0329011000, 0.0369870000, 0.0487159000, 0.0801989000, 0.1725626000, 0.4808356000, 1.4991418000", \ - "0.0327238000, 0.0370870000, 0.0490777000, 0.0803339000, 0.1726390000, 0.4808822000, 1.5026579000", \ - "0.0329488000, 0.0370170000, 0.0487159000, 0.0801207000, 0.1726187000, 0.4808249000, 1.5038851000", \ - "0.0327354000, 0.0370019000, 0.0487296000, 0.0801524000, 0.1726559000, 0.4808428000, 1.5008652000", \ - "0.0330968000, 0.0372794000, 0.0493481000, 0.0809911000, 0.1732246000, 0.4802471000, 1.5033557000", \ - "0.0387425000, 0.0425938000, 0.0539733000, 0.0846298000, 0.1765580000, 0.4821578000, 1.5019056000", \ - "0.0520332000, 0.0567801000, 0.0694210000, 0.0980595000, 0.1833958000, 0.4854671000, 1.5003265000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111ai_1") { - leakage_power () { - value : 3.9556262e-05; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 2.3462865e-05; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 8.0724625e-05; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 3.3923642e-05; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 7.4281185e-05; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 3.1586394e-05; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0006096000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 6.8105169e-05; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 5.3715601e-05; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 2.7532454e-05; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0003872000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 4.7826079e-05; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0003586000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 4.3744827e-05; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0046087000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0003415000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 5.3715601e-05; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 2.7532454e-05; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0003872000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 4.7826079e-05; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0003586000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 4.3744827e-05; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0051966000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0003418000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 5.3715601e-05; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 2.7532454e-05; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0003872000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 4.7826079e-05; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0003586000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 4.3744827e-05; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0039472000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0003413000; - when : "A1&A2&B1&C1&!D1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o2111ai"; - cell_leakage_power : 0.0005779411; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039873000, 0.0039870000, 0.0039862000, 0.0039837000, 0.0039780000, 0.0039648000, 0.0039343000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003981800, -0.003981400, -0.003980500, -0.003979700, -0.003977900, -0.003973900, -0.003964500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024370000; - } - pin ("A2") { - capacitance : 0.0023850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039413000, 0.0039404000, 0.0039382000, 0.0039384000, 0.0039387000, 0.0039394000, 0.0039412000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003939800, -0.003938000, -0.003934100, -0.003934600, -0.003935600, -0.003938200, -0.003943900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025440000; - } - pin ("B1") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038694000, 0.0038703000, 0.0038724000, 0.0038727000, 0.0038734000, 0.0038751000, 0.0038790000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003886800, -0.003880300, -0.003865500, -0.003867100, -0.003870700, -0.003878900, -0.003898100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024090000; - } - pin ("C1") { - capacitance : 0.0024040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044113000, 0.0044069000, 0.0043969000, 0.0044099000, 0.0044397000, 0.0045084000, 0.0046669000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004016200, -0.004010800, -0.003998300, -0.003996800, -0.003993200, -0.003985100, -0.003966300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024730000; - } - pin ("D1") { - capacitance : 0.0023090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047335000, 0.0047355000, 0.0047402000, 0.0047400000, 0.0047394000, 0.0047380000, 0.0047347000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003903400, -0.003903800, -0.003904600, -0.003897800, -0.003881900, -0.003845300, -0.003761000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023530000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1) | (!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0069581000, 0.0059201000, 0.0035568000, -0.001866900, -0.014291700, -0.042725100, -0.107764100", \ - "0.0068378000, 0.0058070000, 0.0034537000, -0.001972800, -0.014376500, -0.042820500, -0.107839700", \ - "0.0066845000, 0.0056667000, 0.0033245000, -0.002078300, -0.014463600, -0.042863100, -0.107901600", \ - "0.0064879000, 0.0054792000, 0.0031567000, -0.002209600, -0.014559200, -0.042931600, -0.107942200", \ - "0.0063812000, 0.0053799000, 0.0030431000, -0.002323000, -0.014645700, -0.042969300, -0.107942100", \ - "0.0063611000, 0.0053638000, 0.0029920000, -0.002546800, -0.014843000, -0.043156300, -0.108139000", \ - "0.0067881000, 0.0057225000, 0.0032897000, -0.002165500, -0.014642100, -0.043166900, -0.108114100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0170243000, 0.0180757000, 0.0204675000, 0.0259606000, 0.0384016000, 0.0666709000, 0.1312176000", \ - "0.0168941000, 0.0179711000, 0.0203686000, 0.0258408000, 0.0383131000, 0.0665706000, 0.1309287000", \ - "0.0167667000, 0.0178362000, 0.0202418000, 0.0257253000, 0.0382273000, 0.0664708000, 0.1308147000", \ - "0.0166115000, 0.0176803000, 0.0200963000, 0.0256309000, 0.0380855000, 0.0665043000, 0.1308267000", \ - "0.0165158000, 0.0175732000, 0.0199906000, 0.0255320000, 0.0380290000, 0.0663159000, 0.1307327000", \ - "0.0164643000, 0.0175541000, 0.0200003000, 0.0254699000, 0.0380708000, 0.0664717000, 0.1308758000", \ - "0.0167955000, 0.0178077000, 0.0200948000, 0.0256939000, 0.0382184000, 0.0666195000, 0.1310603000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0053715000, 0.0043414000, 0.0019962000, -0.003423200, -0.015870600, -0.044323500, -0.109405600", \ - "0.0052732000, 0.0042726000, 0.0019578000, -0.003425900, -0.015825300, -0.044270600, -0.109340200", \ - "0.0050726000, 0.0040988000, 0.0018209000, -0.003514700, -0.015860600, -0.044257600, -0.109309900", \ - "0.0047634000, 0.0037835000, 0.0015331000, -0.003723500, -0.015989200, -0.044321400, -0.109329400", \ - "0.0045356000, 0.0035477000, 0.0012683000, -0.004007200, -0.016223100, -0.044443600, -0.109365200", \ - "0.0045224000, 0.0034997000, 0.0011692000, -0.004190100, -0.016535000, -0.044734400, -0.109568400", \ - "0.0048489000, 0.0037863000, 0.0013915000, -0.004065800, -0.016475700, -0.044877100, -0.109759500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0148528000, 0.0159100000, 0.0183206000, 0.0238020000, 0.0362691000, 0.0645838000, 0.1288832000", \ - "0.0147266000, 0.0157691000, 0.0181649000, 0.0236927000, 0.0361389000, 0.0644551000, 0.1287010000", \ - "0.0144632000, 0.0155583000, 0.0179805000, 0.0234930000, 0.0360561000, 0.0643128000, 0.1286889000", \ - "0.0142853000, 0.0153618000, 0.0177933000, 0.0233255000, 0.0358796000, 0.0641957000, 0.1286095000", \ - "0.0142297000, 0.0152704000, 0.0176670000, 0.0231039000, 0.0356844000, 0.0639932000, 0.1287437000", \ - "0.0144921000, 0.0155419000, 0.0179120000, 0.0232958000, 0.0357446000, 0.0636858000, 0.1282268000", \ - "0.0159207000, 0.0169364000, 0.0192064000, 0.0243810000, 0.0367710000, 0.0648995000, 0.1282134000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0071934000, 0.0061727000, 0.0038312000, -0.001582400, -0.013976700, -0.042422800, -0.107420900", \ - "0.0070905000, 0.0060826000, 0.0037489000, -0.001631800, -0.014022500, -0.042424400, -0.107436400", \ - "0.0069050000, 0.0059157000, 0.0035941000, -0.001759100, -0.014087400, -0.042454300, -0.107475200", \ - "0.0066709000, 0.0056673000, 0.0033608000, -0.001950800, -0.014233200, -0.042536200, -0.107506400", \ - "0.0064431000, 0.0054568000, 0.0031525000, -0.002171600, -0.014434900, -0.042696800, -0.107590500", \ - "0.0065663000, 0.0055440000, 0.0031454000, -0.002350400, -0.014621700, -0.042901400, -0.107727800", \ - "0.0070243000, 0.0060329000, 0.0035872000, -0.001913300, -0.014396700, -0.042924300, -0.107801400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0131241000, 0.0141749000, 0.0165692000, 0.0220044000, 0.0343701000, 0.0625596000, 0.1267787000", \ - "0.0129663000, 0.0140390000, 0.0164192000, 0.0218759000, 0.0343268000, 0.0625044000, 0.1266574000", \ - "0.0126762000, 0.0137468000, 0.0162237000, 0.0217303000, 0.0341343000, 0.0624331000, 0.1266801000", \ - "0.0124825000, 0.0135455000, 0.0158813000, 0.0214832000, 0.0339557000, 0.0622010000, 0.1264511000", \ - "0.0124933000, 0.0135275000, 0.0158191000, 0.0212973000, 0.0337448000, 0.0618485000, 0.1259228000", \ - "0.0129417000, 0.0139396000, 0.0162820000, 0.0217657000, 0.0340443000, 0.0623583000, 0.1265795000", \ - "0.0139173000, 0.0148652000, 0.0171476000, 0.0222385000, 0.0345380000, 0.0626214000, 0.1265752000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0072948000, 0.0062718000, 0.0039336000, -0.001464900, -0.013867000, -0.042256500, -0.107288700", \ - "0.0071717000, 0.0061693000, 0.0038433000, -0.001525200, -0.013893200, -0.042283000, -0.107307900", \ - "0.0069902000, 0.0059899000, 0.0036871000, -0.001662700, -0.013983000, -0.042331900, -0.107338600", \ - "0.0067565000, 0.0057628000, 0.0034575000, -0.001843500, -0.014120100, -0.042428600, -0.107432200", \ - "0.0066178000, 0.0055416000, 0.0032360000, -0.002103500, -0.014357600, -0.042572700, -0.107464300", \ - "0.0066661000, 0.0056464000, 0.0032469000, -0.002214600, -0.014553300, -0.042786600, -0.107617400", \ - "0.0074058000, 0.0063350000, 0.0038642000, -0.001664400, -0.014223200, -0.042764500, -0.107710600"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0099544000, 0.0110250000, 0.0134315000, 0.0188965000, 0.0312319000, 0.0593274000, 0.1235845000", \ - "0.0097997000, 0.0108581000, 0.0133050000, 0.0188010000, 0.0311889000, 0.0594020000, 0.1236105000", \ - "0.0094762000, 0.0105598000, 0.0130133000, 0.0185591000, 0.0310718000, 0.0592435000, 0.1236712000", \ - "0.0092946000, 0.0103955000, 0.0128060000, 0.0183268000, 0.0308197000, 0.0591236000, 0.1233172000", \ - "0.0091473000, 0.0101987000, 0.0125889000, 0.0181790000, 0.0305374000, 0.0586147000, 0.1228438000", \ - "0.0098337000, 0.0108234000, 0.0130545000, 0.0183680000, 0.0307783000, 0.0589646000, 0.1232782000", \ - "0.0105521000, 0.0115120000, 0.0137110000, 0.0188319000, 0.0310198000, 0.0590163000, 0.1231321000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0070696000, 0.0060630000, 0.0037333000, -0.001633600, -0.014005300, -0.042394400, -0.107445900", \ - "0.0069444000, 0.0059442000, 0.0036462000, -0.001708400, -0.014055900, -0.042455200, -0.107464700", \ - "0.0067077000, 0.0057328000, 0.0034473000, -0.001853600, -0.014162000, -0.042515400, -0.107472800", \ - "0.0064648000, 0.0054646000, 0.0031892000, -0.002094500, -0.014359200, -0.042611300, -0.107585600", \ - "0.0063236000, 0.0053173000, 0.0029942000, -0.002314100, -0.014560800, -0.042842100, -0.107690900", \ - "0.0069373000, 0.0058099000, 0.0031380000, -0.002320400, -0.014714100, -0.042919200, -0.107768000", \ - "0.0080715000, 0.0069868000, 0.0044468000, -0.001144200, -0.013891400, -0.042420700, -0.107298200"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011431750, 0.0026136990, 0.0059758310, 0.0136628400, 0.0312380400, 0.0714211100"); - values("0.0070387000, 0.0081545000, 0.0106546000, 0.0161972000, 0.0285743000, 0.0567503000, 0.1208735000", \ - "0.0068009000, 0.0079533000, 0.0104876000, 0.0160788000, 0.0285469000, 0.0567799000, 0.1209574000", \ - "0.0065352000, 0.0076562000, 0.0102299000, 0.0158783000, 0.0284089000, 0.0566771000, 0.1209522000", \ - "0.0064094000, 0.0074768000, 0.0099277000, 0.0155059000, 0.0280745000, 0.0564689000, 0.1207111000", \ - "0.0065474000, 0.0075467000, 0.0099308000, 0.0153816000, 0.0277640000, 0.0560252000, 0.1202286000", \ - "0.0069535000, 0.0080542000, 0.0104269000, 0.0157911000, 0.0280625000, 0.0559332000, 0.1201543000", \ - "0.0085141000, 0.0094232000, 0.0116241000, 0.0166945000, 0.0286743000, 0.0569550000, 0.1204962000"); - } - } - max_capacitance : 0.0714210000; - max_transition : 1.4984840000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0811939000, 0.0871770000, 0.1010433000, 0.1320306000, 0.2016777000, 0.3593918000, 0.7189032000", \ - "0.0854237000, 0.0914689000, 0.1054935000, 0.1363451000, 0.2060285000, 0.3638628000, 0.7232603000", \ - "0.0941468000, 0.1002998000, 0.1142911000, 0.1453159000, 0.2151495000, 0.3732470000, 0.7335418000", \ - "0.1106691000, 0.1169818000, 0.1309128000, 0.1622188000, 0.2321707000, 0.3903224000, 0.7506925000", \ - "0.1373741000, 0.1446137000, 0.1601820000, 0.1940003000, 0.2656914000, 0.4240675000, 0.7843432000", \ - "0.1718744000, 0.1820152000, 0.2027057000, 0.2440149000, 0.3276745000, 0.4969959000, 0.8584839000", \ - "0.1921914000, 0.2090698000, 0.2408906000, 0.3033012000, 0.4177434000, 0.6244681000, 1.0240422000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1342675000, 0.1441828000, 0.1659952000, 0.2161689000, 0.3265979000, 0.5760197000, 1.1410706000", \ - "0.1389262000, 0.1489751000, 0.1718156000, 0.2210164000, 0.3321437000, 0.5816261000, 1.1465697000", \ - "0.1514492000, 0.1614646000, 0.1843562000, 0.2339300000, 0.3448491000, 0.5946651000, 1.1597159000", \ - "0.1779104000, 0.1882311000, 0.2106172000, 0.2605193000, 0.3714705000, 0.6206373000, 1.1861907000", \ - "0.2368095000, 0.2470067000, 0.2693273000, 0.3190562000, 0.4299808000, 0.6797772000, 1.2454603000", \ - "0.3439364000, 0.3593603000, 0.3873600000, 0.4461970000, 0.5654112000, 0.8151907000, 1.3819079000", \ - "0.5281124000, 0.5467098000, 0.5882771000, 0.6696680000, 0.8251095000, 1.1209046000, 1.6951789000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0559792000, 0.0637143000, 0.0814349000, 0.1218376000, 0.2139646000, 0.4249570000, 0.9060365000", \ - "0.0559188000, 0.0637668000, 0.0814973000, 0.1218548000, 0.2140644000, 0.4249677000, 0.9049341000", \ - "0.0559135000, 0.0637841000, 0.0813696000, 0.1218536000, 0.2143081000, 0.4245464000, 0.9072470000", \ - "0.0572842000, 0.0648595000, 0.0821715000, 0.1219803000, 0.2139854000, 0.4249966000, 0.9085613000", \ - "0.0673034000, 0.0750639000, 0.0917878000, 0.1297380000, 0.2176387000, 0.4248195000, 0.9055600000", \ - "0.0962744000, 0.1043622000, 0.1219670000, 0.1602859000, 0.2466374000, 0.4404407000, 0.9097621000", \ - "0.1663410000, 0.1753726000, 0.1969374000, 0.2402261000, 0.3296248000, 0.5203947000, 0.9548687000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1145698000, 0.1270342000, 0.1560320000, 0.2215240000, 0.3695563000, 0.7066469000, 1.4759763000", \ - "0.1147939000, 0.1271281000, 0.1559258000, 0.2212792000, 0.3688392000, 0.7087151000, 1.4763413000", \ - "0.1143862000, 0.1270430000, 0.1560081000, 0.2211375000, 0.3688511000, 0.7083621000, 1.4762555000", \ - "0.1139830000, 0.1269095000, 0.1558434000, 0.2212528000, 0.3697046000, 0.7061670000, 1.4769972000", \ - "0.1224072000, 0.1342844000, 0.1612976000, 0.2232200000, 0.3689712000, 0.7064694000, 1.4767032000", \ - "0.1631223000, 0.1767822000, 0.2032759000, 0.2597408000, 0.3902952000, 0.7103799000, 1.4772695000", \ - "0.2492404000, 0.2639460000, 0.2970305000, 0.3647371000, 0.4998685000, 0.7870907000, 1.4954757000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0639317000, 0.0696028000, 0.0823222000, 0.1114470000, 0.1775916000, 0.3254824000, 0.6663096000", \ - "0.0682436000, 0.0739593000, 0.0869282000, 0.1160089000, 0.1813437000, 0.3307117000, 0.6747702000", \ - "0.0765338000, 0.0824909000, 0.0957131000, 0.1247584000, 0.1906287000, 0.3400126000, 0.6811908000", \ - "0.0911922000, 0.0974160000, 0.1109484000, 0.1406917000, 0.2070760000, 0.3588137000, 0.7046553000", \ - "0.1119602000, 0.1193392000, 0.1351626000, 0.1687509000, 0.2383490000, 0.3893193000, 0.7304475000", \ - "0.1315733000, 0.1419450000, 0.1648824000, 0.2084405000, 0.2928298000, 0.4572727000, 0.8016137000", \ - "0.1157616000, 0.1347433000, 0.1709669000, 0.2410675000, 0.3620957000, 0.5748022000, 0.9567933000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1199504000, 0.1297685000, 0.1522025000, 0.2020606000, 0.3128529000, 0.5620091000, 1.1270904000", \ - "0.1240382000, 0.1339855000, 0.1561182000, 0.2059322000, 0.3166974000, 0.5658045000, 1.1310751000", \ - "0.1347314000, 0.1448756000, 0.1670608000, 0.2169807000, 0.3281249000, 0.5773656000, 1.1427308000", \ - "0.1629363000, 0.1728824000, 0.1956826000, 0.2453854000, 0.3561127000, 0.6057249000, 1.1713647000", \ - "0.2311110000, 0.2420314000, 0.2642150000, 0.3114056000, 0.4218496000, 0.6712649000, 1.2368143000", \ - "0.3643734000, 0.3787524000, 0.4086296000, 0.4690934000, 0.5847139000, 0.8256318000, 1.3893511000", \ - "0.5792485000, 0.6016815000, 0.6472013000, 0.7382823000, 0.9091902000, 1.2028966000, 1.7614005000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0409519000, 0.0483162000, 0.0651593000, 0.1036910000, 0.1913792000, 0.3900108000, 0.8454043000", \ - "0.0408350000, 0.0481375000, 0.0650599000, 0.1034973000, 0.1906467000, 0.3909756000, 0.8500498000", \ - "0.0409033000, 0.0483346000, 0.0651843000, 0.1032539000, 0.1907702000, 0.3899523000, 0.8469974000", \ - "0.0439459000, 0.0505688000, 0.0668729000, 0.1040928000, 0.1907966000, 0.3914462000, 0.8516280000", \ - "0.0555263000, 0.0624907000, 0.0782694000, 0.1144260000, 0.1958807000, 0.3917705000, 0.8479608000", \ - "0.0875658000, 0.0951389000, 0.1116954000, 0.1475682000, 0.2293649000, 0.4104269000, 0.8550374000", \ - "0.1584078000, 0.1684605000, 0.1891858000, 0.2319823000, 0.3159256000, 0.5036379000, 0.9084351000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.1142259000, 0.1268603000, 0.1554881000, 0.2212890000, 0.3694486000, 0.7074356000, 1.4752751000", \ - "0.1146416000, 0.1272724000, 0.1554979000, 0.2209917000, 0.3686208000, 0.7063474000, 1.4766782000", \ - "0.1143421000, 0.1268916000, 0.1556805000, 0.2204312000, 0.3688262000, 0.7072303000, 1.4757086000", \ - "0.1137649000, 0.1267272000, 0.1558882000, 0.2209457000, 0.3689542000, 0.7071639000, 1.4758975000", \ - "0.1274816000, 0.1381531000, 0.1637593000, 0.2242004000, 0.3689747000, 0.7066312000, 1.4771451000", \ - "0.1878041000, 0.2005713000, 0.2264654000, 0.2781669000, 0.3979534000, 0.7093314000, 1.4799636000", \ - "0.2909574000, 0.3103144000, 0.3488672000, 0.4226652000, 0.5550561000, 0.8119759000, 1.4984838000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0741397000, 0.0802403000, 0.0943679000, 0.1253158000, 0.1949828000, 0.3527975000, 0.7123729000", \ - "0.0779269000, 0.0842679000, 0.0982052000, 0.1292489000, 0.1992323000, 0.3570177000, 0.7171660000", \ - "0.0855877000, 0.0919213000, 0.1059608000, 0.1373031000, 0.2073106000, 0.3657144000, 0.7251024000", \ - "0.1015280000, 0.1080783000, 0.1223285000, 0.1538119000, 0.2241698000, 0.3826862000, 0.7430685000", \ - "0.1278667000, 0.1361709000, 0.1533827000, 0.1886832000, 0.2619134000, 0.4211295000, 0.7812321000", \ - "0.1596840000, 0.1715523000, 0.1950123000, 0.2433045000, 0.3337264000, 0.5078310000, 0.8716892000", \ - "0.1655453000, 0.1835792000, 0.2225674000, 0.2962679000, 0.4308597000, 0.6584700000, 1.0725856000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0593388000, 0.0649686000, 0.0773359000, 0.1053096000, 0.1676991000, 0.3090685000, 0.6310953000", \ - "0.0647710000, 0.0703180000, 0.0826440000, 0.1107967000, 0.1734742000, 0.3148246000, 0.6369745000", \ - "0.0775289000, 0.0830656000, 0.0956617000, 0.1238147000, 0.1868951000, 0.3281617000, 0.6503598000", \ - "0.1095119000, 0.1149429000, 0.1267636000, 0.1556960000, 0.2186287000, 0.3578759000, 0.6807120000", \ - "0.1743008000, 0.1821943000, 0.1987308000, 0.2307735000, 0.2923765000, 0.4322606000, 0.7538776000", \ - "0.2813994000, 0.2940364000, 0.3203351000, 0.3707774000, 0.4586333000, 0.6081348000, 0.9287718000", \ - "0.4572949000, 0.4769923000, 0.5175262000, 0.5985609000, 0.7427224000, 0.9751513000, 1.3372822000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0559261000, 0.0637440000, 0.0815036000, 0.1218946000, 0.2140738000, 0.4249173000, 0.9059125000", \ - "0.0560177000, 0.0636606000, 0.0813988000, 0.1216510000, 0.2140200000, 0.4247245000, 0.9074737000", \ - "0.0560315000, 0.0637144000, 0.0815049000, 0.1218595000, 0.2138605000, 0.4245534000, 0.9068040000", \ - "0.0590616000, 0.0662188000, 0.0832415000, 0.1222222000, 0.2140326000, 0.4248743000, 0.9081733000", \ - "0.0748798000, 0.0820802000, 0.0985381000, 0.1347246000, 0.2196991000, 0.4256788000, 0.9064511000", \ - "0.1144170000, 0.1230479000, 0.1407600000, 0.1786224000, 0.2617879000, 0.4462645000, 0.9095985000", \ - "0.1915681000, 0.2039724000, 0.2288882000, 0.2777531000, 0.3714650000, 0.5563234000, 0.9743982000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0675369000, 0.0753246000, 0.0930247000, 0.1324272000, 0.2199845000, 0.4181966000, 0.8728267000", \ - "0.0675250000, 0.0753215000, 0.0929896000, 0.1324302000, 0.2201873000, 0.4190739000, 0.8756140000", \ - "0.0674205000, 0.0752715000, 0.0929652000, 0.1324031000, 0.2201355000, 0.4189594000, 0.8750029000", \ - "0.0725043000, 0.0794735000, 0.0952418000, 0.1325541000, 0.2202092000, 0.4189799000, 0.8736772000", \ - "0.1058561000, 0.1113123000, 0.1222325000, 0.1513402000, 0.2272959000, 0.4189734000, 0.8748038000", \ - "0.1747981000, 0.1826282000, 0.1990278000, 0.2309365000, 0.2912577000, 0.4474899000, 0.8755822000", \ - "0.2886398000, 0.3011009000, 0.3263766000, 0.3776870000, 0.4657575000, 0.6116228000, 0.9552275000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0661539000, 0.0723553000, 0.0862636000, 0.1172069000, 0.1870790000, 0.3448553000, 0.7045658000", \ - "0.0695957000, 0.0758942000, 0.0899979000, 0.1211157000, 0.1911145000, 0.3490000000, 0.7085447000", \ - "0.0777776000, 0.0841444000, 0.0982819000, 0.1295952000, 0.1997094000, 0.3580903000, 0.7177544000", \ - "0.0963176000, 0.1031876000, 0.1175320000, 0.1492763000, 0.2197080000, 0.3781385000, 0.7381055000", \ - "0.1266585000, 0.1360316000, 0.1546415000, 0.1913805000, 0.2657491000, 0.4257974000, 0.7862518000", \ - "0.1605985000, 0.1742565000, 0.2016869000, 0.2551617000, 0.3532240000, 0.5310765000, 0.8961802000", \ - "0.1738270000, 0.1943660000, 0.2358682000, 0.3187081000, 0.4666687000, 0.7165070000, 1.1410715000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0495629000, 0.0548616000, 0.0668510000, 0.0937941000, 0.1544340000, 0.2926144000, 0.6085422000", \ - "0.0547500000, 0.0599959000, 0.0721359000, 0.0993147000, 0.1602283000, 0.2984396000, 0.6141390000", \ - "0.0674009000, 0.0727691000, 0.0848964000, 0.1121043000, 0.1733899000, 0.3120108000, 0.6283912000", \ - "0.0992625000, 0.1048410000, 0.1166296000, 0.1440240000, 0.2053947000, 0.3442530000, 0.6568806000", \ - "0.1557443000, 0.1646468000, 0.1829856000, 0.2170878000, 0.2785561000, 0.4152554000, 0.7301987000", \ - "0.2479268000, 0.2624211000, 0.2918019000, 0.3456647000, 0.4400106000, 0.5899894000, 0.9039701000", \ - "0.4012433000, 0.4231578000, 0.4688154000, 0.5554754000, 0.7063388000, 0.9471465000, 1.3100176000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0560547000, 0.0635940000, 0.0813856000, 0.1218186000, 0.2141039000, 0.4247472000, 0.9049138000", \ - "0.0560285000, 0.0637389000, 0.0815082000, 0.1216375000, 0.2141446000, 0.4248011000, 0.9064736000", \ - "0.0558805000, 0.0636285000, 0.0814481000, 0.1218180000, 0.2141141000, 0.4245612000, 0.9051430000", \ - "0.0603424000, 0.0674069000, 0.0838092000, 0.1226229000, 0.2137998000, 0.4251400000, 0.9063852000", \ - "0.0812042000, 0.0880443000, 0.1047086000, 0.1394500000, 0.2222195000, 0.4248721000, 0.9061134000", \ - "0.1233303000, 0.1331010000, 0.1535220000, 0.1942013000, 0.2753818000, 0.4521412000, 0.9075481000", \ - "0.2019089000, 0.2163927000, 0.2451233000, 0.3006960000, 0.4017322000, 0.5912110000, 0.9881195000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0553950000, 0.0633726000, 0.0810527000, 0.1204517000, 0.2068779000, 0.4013472000, 0.8471536000", \ - "0.0554196000, 0.0632714000, 0.0810598000, 0.1203985000, 0.2068170000, 0.4016412000, 0.8470372000", \ - "0.0554078000, 0.0632918000, 0.0810308000, 0.1204257000, 0.2068420000, 0.4011953000, 0.8444427000", \ - "0.0639774000, 0.0703362000, 0.0853853000, 0.1213716000, 0.2069605000, 0.4014507000, 0.8468137000", \ - "0.1019768000, 0.1073369000, 0.1184298000, 0.1461719000, 0.2167820000, 0.4012533000, 0.8455272000", \ - "0.1704121000, 0.1783391000, 0.1954450000, 0.2274590000, 0.2864564000, 0.4344708000, 0.8461917000", \ - "0.2827790000, 0.2954141000, 0.3215384000, 0.3722445000, 0.4602417000, 0.6083585000, 0.9324727000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0553969000, 0.0617102000, 0.0757238000, 0.1068999000, 0.1766555000, 0.3346013000, 0.6943058000", \ - "0.0586661000, 0.0649027000, 0.0792769000, 0.1103610000, 0.1804860000, 0.3385573000, 0.6982935000", \ - "0.0668331000, 0.0733049000, 0.0876842000, 0.1191197000, 0.1895635000, 0.3478249000, 0.7077486000", \ - "0.0885534000, 0.0948746000, 0.1086650000, 0.1400508000, 0.2105349000, 0.3691001000, 0.7290850000", \ - "0.1204730000, 0.1299030000, 0.1496093000, 0.1883034000, 0.2605914000, 0.4190386000, 0.7790916000", \ - "0.1539063000, 0.1676542000, 0.1967410000, 0.2539451000, 0.3585368000, 0.5340109000, 0.8931502000", \ - "0.1737477000, 0.1944230000, 0.2371577000, 0.3221879000, 0.4754256000, 0.7376029000, 1.1597839000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0363125000, 0.0413036000, 0.0524373000, 0.0771370000, 0.1329145000, 0.2586737000, 0.5465668000", \ - "0.0412296000, 0.0463812000, 0.0574060000, 0.0826224000, 0.1381974000, 0.2643081000, 0.5512144000", \ - "0.0540841000, 0.0590714000, 0.0703152000, 0.0949619000, 0.1514100000, 0.2774891000, 0.5637287000", \ - "0.0817855000, 0.0883039000, 0.1010402000, 0.1260919000, 0.1818974000, 0.3091447000, 0.5945840000", \ - "0.1251943000, 0.1356156000, 0.1560736000, 0.1927494000, 0.2544647000, 0.3789927000, 0.6654620000", \ - "0.1935316000, 0.2096762000, 0.2424399000, 0.3019653000, 0.3982673000, 0.5499263000, 0.8354153000", \ - "0.3049587000, 0.3296216000, 0.3797742000, 0.4718947000, 0.6274615000, 0.8705346000, 1.2297059000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0559561000, 0.0636145000, 0.0813537000, 0.1219354000, 0.2139924000, 0.4240991000, 0.9066092000", \ - "0.0558193000, 0.0636667000, 0.0815121000, 0.1218598000, 0.2143168000, 0.4250694000, 0.9057398000", \ - "0.0548035000, 0.0626333000, 0.0810521000, 0.1217777000, 0.2142458000, 0.4252148000, 0.9069783000", \ - "0.0614819000, 0.0679616000, 0.0839413000, 0.1218712000, 0.2139998000, 0.4248953000, 0.9067974000", \ - "0.0846667000, 0.0929025000, 0.1103856000, 0.1457800000, 0.2236001000, 0.4257144000, 0.9070706000", \ - "0.1319694000, 0.1432442000, 0.1658860000, 0.2109099000, 0.2929729000, 0.4641672000, 0.9099344000", \ - "0.2105826000, 0.2275828000, 0.2630327000, 0.3265072000, 0.4424617000, 0.6366521000, 1.0233423000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011431800, 0.0026137000, 0.0059758300, 0.0136628000, 0.0312380000, 0.0714211000"); - values("0.0420278000, 0.0493623000, 0.0657333000, 0.1020683000, 0.1817454000, 0.3598904000, 0.7668763000", \ - "0.0421222000, 0.0493850000, 0.0657895000, 0.1021785000, 0.1816930000, 0.3599216000, 0.7655955000", \ - "0.0432647000, 0.0497537000, 0.0657748000, 0.1021632000, 0.1816691000, 0.3599308000, 0.7669819000", \ - "0.0579794000, 0.0626516000, 0.0749881000, 0.1053204000, 0.1817053000, 0.3597073000, 0.7669135000", \ - "0.0990719000, 0.1040790000, 0.1149961000, 0.1368997000, 0.1957811000, 0.3602903000, 0.7669887000", \ - "0.1660906000, 0.1735844000, 0.1888836000, 0.2204292000, 0.2792777000, 0.4037247000, 0.7702795000", \ - "0.2742855000, 0.2857686000, 0.3102750000, 0.3604403000, 0.4490244000, 0.5929906000, 0.8809040000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111ai_2") { - leakage_power () { - value : 7.3309997e-05; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 4.1239117e-05; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0001679000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 6.1341069e-05; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0001559000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 5.8938965e-05; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0013858000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0001513000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 9.3501778e-05; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 4.6789114e-05; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0006377000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 8.1139881e-05; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0006258000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 7.7595685e-05; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0107021000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0008243000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 9.3515311e-05; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 4.6789114e-05; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0006377000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 8.115691e-05; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0006258000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 7.7595685e-05; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0094054000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0008254000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 9.3501778e-05; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 4.6789114e-05; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0006377000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 8.0836447e-05; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0006258000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 7.7595685e-05; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0077470000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0008246000; - when : "A1&A2&B1&C1&!D1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__o2111ai"; - cell_leakage_power : 0.0011597490; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078961000, 0.0078977000, 0.0079014000, 0.0079047000, 0.0079122000, 0.0079296000, 0.0079697000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007907900, -0.007903500, -0.007893400, -0.007895100, -0.007898900, -0.007907900, -0.007928500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045640000; - } - pin ("A2") { - capacitance : 0.0043280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040230000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078947000, 0.0078934000, 0.0078906000, 0.0078897000, 0.0078877000, 0.0078830000, 0.0078723000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007893700, -0.007892000, -0.007888000, -0.007886200, -0.007881800, -0.007871800, -0.007848800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046330000; - } - pin ("B1") { - capacitance : 0.0044470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079695000, 0.0079709000, 0.0079740000, 0.0079744000, 0.0079755000, 0.0079779000, 0.0079835000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008000600, -0.007993700, -0.007977700, -0.007972400, -0.007960200, -0.007932300, -0.007867700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046050000; - } - pin ("C1") { - capacitance : 0.0043070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085067000, 0.0084964000, 0.0084726000, 0.0085056000, 0.0085818000, 0.0087574000, 0.0091623000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007916200, -0.007908000, -0.007889000, -0.007886000, -0.007879300, -0.007863800, -0.007828100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044200000; - } - pin ("D1") { - capacitance : 0.0042940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091642000, 0.0091626000, 0.0091588000, 0.0091580000, 0.0091563000, 0.0091523000, 0.0091430000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006232700, -0.006228900, -0.006220300, -0.006201700, -0.006159000, -0.006060400, -0.005833300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043590000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1) | (!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0146891000, 0.0134622000, 0.0103556000, 0.0025690000, -0.017163000, -0.067097400, -0.193183400", \ - "0.0144002000, 0.0132038000, 0.0101222000, 0.0023293000, -0.017391400, -0.067297900, -0.193389300", \ - "0.0140908000, 0.0128783000, 0.0098019000, 0.0020605000, -0.017620800, -0.067529100, -0.193605200", \ - "0.0136261000, 0.0124322000, 0.0094205000, 0.0017331000, -0.017867900, -0.067676000, -0.193732500", \ - "0.0133470000, 0.0121413000, 0.0091065000, 0.0014050000, -0.018099500, -0.067777600, -0.193793800", \ - "0.0132560000, 0.0120273000, 0.0089457000, 0.0010016000, -0.018454400, -0.068170200, -0.194058100", \ - "0.0139772000, 0.0127267000, 0.0096280000, 0.0017106000, -0.018128000, -0.068180800, -0.194049900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0325767000, 0.0337617000, 0.0369118000, 0.0448543000, 0.0647558000, 0.1145779000, 0.2395004000", \ - "0.0323133000, 0.0335345000, 0.0367079000, 0.0446183000, 0.0644681000, 0.1142220000, 0.2391202000", \ - "0.0320257000, 0.0332922000, 0.0364006000, 0.0443602000, 0.0643024000, 0.1141322000, 0.2389571000", \ - "0.0317297000, 0.0329728000, 0.0361545000, 0.0440869000, 0.0640935000, 0.1138699000, 0.2388339000", \ - "0.0314081000, 0.0326474000, 0.0357957000, 0.0437439000, 0.0637788000, 0.1135967000, 0.2386491000", \ - "0.0313599000, 0.0326149000, 0.0358332000, 0.0437784000, 0.0638163000, 0.1137444000, 0.2387310000", \ - "0.0314776000, 0.0326730000, 0.0356805000, 0.0440051000, 0.0639811000, 0.1137301000, 0.2389751000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0103847000, 0.0091984000, 0.0061172000, -0.001675300, -0.021449200, -0.071461900, -0.197707300", \ - "0.0102313000, 0.0090538000, 0.0060628000, -0.001673200, -0.021367900, -0.071295400, -0.197561900", \ - "0.0098061000, 0.0086446000, 0.0057461000, -0.001837100, -0.021409100, -0.071270700, -0.197454800", \ - "0.0091890000, 0.0080412000, 0.0051428000, -0.002318700, -0.021699600, -0.071393700, -0.197466700", \ - "0.0087711000, 0.0075806000, 0.0046512000, -0.002905800, -0.022199600, -0.071675100, -0.197565600", \ - "0.0087481000, 0.0075266000, 0.0045131000, -0.003213200, -0.022841800, -0.072268100, -0.197890900", \ - "0.0097688000, 0.0084584000, 0.0052679000, -0.002675500, -0.022529100, -0.072474400, -0.198286400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0279170000, 0.0291766000, 0.0323098000, 0.0402285000, 0.0601907000, 0.1100537000, 0.2346626000", \ - "0.0275828000, 0.0289307000, 0.0319816000, 0.0399576000, 0.0599360000, 0.1097784000, 0.2345756000", \ - "0.0271684000, 0.0284335000, 0.0316704000, 0.0396110000, 0.0596421000, 0.1095847000, 0.2343851000", \ - "0.0267647000, 0.0280386000, 0.0312093000, 0.0391974000, 0.0593210000, 0.1092111000, 0.2344288000", \ - "0.0266298000, 0.0278528000, 0.0310107000, 0.0389349000, 0.0590160000, 0.1090867000, 0.2340452000", \ - "0.0274251000, 0.0286898000, 0.0317987000, 0.0396063000, 0.0593262000, 0.1086885000, 0.2336632000", \ - "0.0303960000, 0.0315466000, 0.0344288000, 0.0418455000, 0.0613397000, 0.1104058000, 0.2342734000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0146827000, 0.0135042000, 0.0104965000, 0.0027418000, -0.016935300, -0.066804600, -0.192907700", \ - "0.0144494000, 0.0132733000, 0.0102988000, 0.0025896000, -0.017019200, -0.066860400, -0.192939200", \ - "0.0141299000, 0.0129407000, 0.0099635000, 0.0023150000, -0.017220800, -0.066973200, -0.192981400", \ - "0.0136559000, 0.0124795000, 0.0094964000, 0.0019088000, -0.017534200, -0.067151900, -0.193082200", \ - "0.0134417000, 0.0122325000, 0.0091915000, 0.0015792000, -0.017908700, -0.067414900, -0.193212000", \ - "0.0134250000, 0.0122612000, 0.0090559000, 0.0011564000, -0.018380700, -0.067934400, -0.193644500", \ - "0.0145182000, 0.0132559000, 0.0101005000, 0.0021223000, -0.017825000, -0.068012800, -0.193835900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0252743000, 0.0265147000, 0.0296614000, 0.0375682000, 0.0573827000, 0.1069270000, 0.2316611000", \ - "0.0249858000, 0.0262415000, 0.0294061000, 0.0373811000, 0.0572526000, 0.1068091000, 0.2315609000", \ - "0.0245449000, 0.0258092000, 0.0290226000, 0.0370023000, 0.0570084000, 0.1066965000, 0.2316061000", \ - "0.0241045000, 0.0253509000, 0.0284859000, 0.0365361000, 0.0565610000, 0.1061802000, 0.2312296000", \ - "0.0237946000, 0.0250416000, 0.0282297000, 0.0363059000, 0.0562622000, 0.1055426000, 0.2308572000", \ - "0.0249686000, 0.0261814000, 0.0292409000, 0.0369452000, 0.0566146000, 0.1061530000, 0.2307892000", \ - "0.0275646000, 0.0287109000, 0.0315592000, 0.0389923000, 0.0583614000, 0.1089105000, 0.2320804000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0146576000, 0.0134604000, 0.0104319000, 0.0027081000, -0.016963300, -0.066871400, -0.192951300", \ - "0.0144275000, 0.0132368000, 0.0102654000, 0.0025693000, -0.017053000, -0.066901500, -0.192982400", \ - "0.0141133000, 0.0129240000, 0.0099412000, 0.0023020000, -0.017232100, -0.066989200, -0.193026300", \ - "0.0136971000, 0.0125161000, 0.0095312000, 0.0019005000, -0.017525600, -0.067163200, -0.193093900", \ - "0.0134285000, 0.0122242000, 0.0092862000, 0.0016339000, -0.017823000, -0.067394400, -0.193201500", \ - "0.0133102000, 0.0120920000, 0.0090455000, 0.0012465000, -0.018312400, -0.067877600, -0.193521700", \ - "0.0146238000, 0.0133426000, 0.0101794000, 0.0021882000, -0.017791900, -0.067927900, -0.193817500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0195151000, 0.0207779000, 0.0239710000, 0.0318720000, 0.0516544000, 0.1011323000, 0.2256591000", \ - "0.0191422000, 0.0204271000, 0.0236642000, 0.0316673000, 0.0516039000, 0.1011411000, 0.2258158000", \ - "0.0185885000, 0.0198854000, 0.0231619000, 0.0312727000, 0.0513345000, 0.1010746000, 0.2257662000", \ - "0.0180457000, 0.0193654000, 0.0225211000, 0.0306406000, 0.0508077000, 0.1006095000, 0.2254738000", \ - "0.0175978000, 0.0188510000, 0.0220100000, 0.0300309000, 0.0501478000, 0.1000120000, 0.2249608000", \ - "0.0183197000, 0.0194912000, 0.0225339000, 0.0304363000, 0.0501297000, 0.0999149000, 0.2245652000", \ - "0.0199223000, 0.0210353000, 0.0239194000, 0.0314143000, 0.0507512000, 0.1006066000, 0.2247185000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0126077000, 0.0114345000, 0.0084650000, 0.0007953000, -0.018856400, -0.068739400, -0.194776300", \ - "0.0123194000, 0.0111500000, 0.0081988000, 0.0005597000, -0.018966300, -0.068807000, -0.194827700", \ - "0.0120082000, 0.0108379000, 0.0078802000, 0.0002584000, -0.019168100, -0.068889200, -0.194874800", \ - "0.0116707000, 0.0104717000, 0.0074846000, -0.000151300, -0.019530100, -0.069125700, -0.195018400", \ - "0.0114441000, 0.0102172000, 0.0072239000, -0.000339800, -0.019941900, -0.069465700, -0.195193700", \ - "0.0120946000, 0.0108070000, 0.0076428000, -3.18000e-05, -0.019885800, -0.069672600, -0.195534900", \ - "0.0146590000, 0.0133247000, 0.0100079000, 0.0017985000, -0.018568700, -0.069212600, -0.195568600"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012617180, 0.0031838650, 0.0080342800, 0.0202739900, 0.0511601300, 0.1290993000"); - values("0.0115986000, 0.0129661000, 0.0163517000, 0.0244707000, 0.0443675000, 0.0938555000, 0.2185337000", \ - "0.0112462000, 0.0126539000, 0.0160348000, 0.0242138000, 0.0443096000, 0.0939525000, 0.2187449000", \ - "0.0109438000, 0.0122980000, 0.0156320000, 0.0238462000, 0.0440724000, 0.0938362000, 0.2184801000", \ - "0.0106226000, 0.0118984000, 0.0152402000, 0.0233942000, 0.0435246000, 0.0936460000, 0.2185111000", \ - "0.0107022000, 0.0119368000, 0.0150595000, 0.0229782000, 0.0428841000, 0.0928838000, 0.2176272000", \ - "0.0115400000, 0.0128624000, 0.0160746000, 0.0236772000, 0.0432807000, 0.0924943000, 0.2174507000", \ - "0.0149758000, 0.0159221000, 0.0187031000, 0.0258677000, 0.0446931000, 0.0949227000, 0.2193357000"); - } - } - max_capacitance : 0.1290990000; - max_transition : 1.5017350000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0907011000, 0.0950418000, 0.1063241000, 0.1336657000, 0.2008871000, 0.3675017000, 0.7853508000", \ - "0.0944024000, 0.0990825000, 0.1101616000, 0.1374943000, 0.2046886000, 0.3713685000, 0.7895536000", \ - "0.1024404000, 0.1069622000, 0.1182087000, 0.1457115000, 0.2131106000, 0.3801196000, 0.7977046000", \ - "0.1166564000, 0.1212942000, 0.1325563000, 0.1603572000, 0.2279097000, 0.3952011000, 0.8127281000", \ - "0.1389904000, 0.1441208000, 0.1562561000, 0.1860678000, 0.2557055000, 0.4231319000, 0.8418969000", \ - "0.1671471000, 0.1736667000, 0.1892478000, 0.2245327000, 0.3039074000, 0.4818728000, 0.9021657000", \ - "0.1765508000, 0.1863374000, 0.2105244000, 0.2629829000, 0.3692497000, 0.5811777000, 1.0360408000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1390183000, 0.1454867000, 0.1611564000, 0.2011699000, 0.2972489000, 0.5336737000, 1.1245666000", \ - "0.1435077000, 0.1498887000, 0.1667450000, 0.2056965000, 0.3021660000, 0.5389532000, 1.1294533000", \ - "0.1568221000, 0.1633659000, 0.1790973000, 0.2191636000, 0.3153515000, 0.5518534000, 1.1427438000", \ - "0.1841759000, 0.1905579000, 0.2071902000, 0.2464640000, 0.3430368000, 0.5801477000, 1.1710068000", \ - "0.2447848000, 0.2513926000, 0.2672935000, 0.3068208000, 0.4034962000, 0.6410928000, 1.2320159000", \ - "0.3601850000, 0.3686985000, 0.3891119000, 0.4359596000, 0.5422839000, 0.7798940000, 1.3720436000", \ - "0.5537795000, 0.5657160000, 0.5958720000, 0.6612367000, 0.8042501000, 1.0891000000, 1.6930483000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0644754000, 0.0697959000, 0.0839055000, 0.1188373000, 0.2080717000, 0.4335743000, 1.0021369000", \ - "0.0643925000, 0.0700306000, 0.0836677000, 0.1188111000, 0.2079130000, 0.4328262000, 1.0027357000", \ - "0.0644620000, 0.0697996000, 0.0838238000, 0.1188000000, 0.2080694000, 0.4337978000, 1.0021398000", \ - "0.0655397000, 0.0706847000, 0.0844084000, 0.1189829000, 0.2078729000, 0.4336004000, 1.0027180000", \ - "0.0736910000, 0.0788492000, 0.0922889000, 0.1259681000, 0.2114613000, 0.4335909000, 1.0018768000", \ - "0.0985077000, 0.1039010000, 0.1174587000, 0.1511986000, 0.2361709000, 0.4480614000, 1.0048673000", \ - "0.1645240000, 0.1711944000, 0.1875234000, 0.2239587000, 0.3090101000, 0.5151851000, 1.0432412000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1166269000, 0.1248883000, 0.1456908000, 0.1978496000, 0.3281357000, 0.6550347000, 1.4821795000", \ - "0.1168157000, 0.1249641000, 0.1456110000, 0.1976890000, 0.3272683000, 0.6545057000, 1.4790165000", \ - "0.1165104000, 0.1250581000, 0.1456246000, 0.1977877000, 0.3280373000, 0.6543753000, 1.4789516000", \ - "0.1163876000, 0.1246788000, 0.1455420000, 0.1973552000, 0.3274915000, 0.6541983000, 1.4810771000", \ - "0.1230643000, 0.1306409000, 0.1505053000, 0.1999175000, 0.3273702000, 0.6555050000, 1.4795951000", \ - "0.1618368000, 0.1702054000, 0.1904469000, 0.2362290000, 0.3509492000, 0.6588268000, 1.4796471000", \ - "0.2472150000, 0.2563486000, 0.2805619000, 0.3354476000, 0.4592984000, 0.7389143000, 1.4922407000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0691867000, 0.0735538000, 0.0835555000, 0.1089848000, 0.1739218000, 0.3347716000, 0.7395983000", \ - "0.0736159000, 0.0779073000, 0.0882862000, 0.1137164000, 0.1788837000, 0.3375340000, 0.7412342000", \ - "0.0811330000, 0.0853179000, 0.0962481000, 0.1225274000, 0.1870223000, 0.3474178000, 0.7488718000", \ - "0.0942023000, 0.0988166000, 0.1098588000, 0.1365576000, 0.2011956000, 0.3616928000, 0.7655393000", \ - "0.1120183000, 0.1171633000, 0.1300315000, 0.1596118000, 0.2280673000, 0.3908435000, 0.7931250000", \ - "0.1270646000, 0.1346205000, 0.1529472000, 0.1908591000, 0.2722049000, 0.4473706000, 0.8547568000", \ - "0.1064594000, 0.1180145000, 0.1464308000, 0.2070409000, 0.3235744000, 0.5452491000, 0.9863030000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1191663000, 0.1255621000, 0.1418499000, 0.1819075000, 0.2778043000, 0.5142319000, 1.1045641000", \ - "0.1223152000, 0.1295477000, 0.1459787000, 0.1849141000, 0.2811552000, 0.5179817000, 1.1092512000", \ - "0.1329741000, 0.1398093000, 0.1562313000, 0.1955756000, 0.2918169000, 0.5287123000, 1.1200548000", \ - "0.1601438000, 0.1668461000, 0.1830124000, 0.2227106000, 0.3187882000, 0.5557307000, 1.1464256000", \ - "0.2261798000, 0.2329251000, 0.2488261000, 0.2878872000, 0.3835831000, 0.6208814000, 1.2120650000", \ - "0.3508718000, 0.3604518000, 0.3825954000, 0.4337553000, 0.5399274000, 0.7730666000, 1.3631619000", \ - "0.5534752000, 0.5673156000, 0.5998010000, 0.6747367000, 0.8302393000, 1.1290128000, 1.7192838000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0431311000, 0.0486577000, 0.0621979000, 0.0964713000, 0.1839937000, 0.4027184000, 0.9544090000", \ - "0.0431260000, 0.0488031000, 0.0624782000, 0.0965715000, 0.1840049000, 0.4014726000, 0.9517532000", \ - "0.0432761000, 0.0485718000, 0.0624928000, 0.0968581000, 0.1831677000, 0.4013506000, 0.9501859000", \ - "0.0457683000, 0.0508281000, 0.0637306000, 0.0976130000, 0.1830707000, 0.4011001000, 0.9500589000", \ - "0.0560450000, 0.0612989000, 0.0741771000, 0.1069183000, 0.1881738000, 0.4030775000, 0.9506339000", \ - "0.0857880000, 0.0908623000, 0.1040389000, 0.1362516000, 0.2172570000, 0.4188203000, 0.9529650000", \ - "0.1556343000, 0.1622746000, 0.1779291000, 0.2145730000, 0.2962877000, 0.4992174000, 1.0000648000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.1164632000, 0.1246762000, 0.1454116000, 0.1974080000, 0.3279880000, 0.6540944000, 1.4779590000", \ - "0.1165467000, 0.1250946000, 0.1454724000, 0.1973052000, 0.3275621000, 0.6544189000, 1.4782868000", \ - "0.1167412000, 0.1247148000, 0.1459243000, 0.1972731000, 0.3273538000, 0.6540931000, 1.4812187000", \ - "0.1156659000, 0.1239897000, 0.1453956000, 0.1972363000, 0.3275905000, 0.6542309000, 1.4789241000", \ - "0.1299773000, 0.1372330000, 0.1553176000, 0.2021620000, 0.3275824000, 0.6547001000, 1.4789900000", \ - "0.1846325000, 0.1935241000, 0.2175702000, 0.2622746000, 0.3657956000, 0.6607635000, 1.4792729000", \ - "0.2809073000, 0.2939628000, 0.3250180000, 0.3904392000, 0.5221085000, 0.7814988000, 1.5017352000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0830480000, 0.0878417000, 0.0991480000, 0.1266552000, 0.1939326000, 0.3610893000, 0.7785810000", \ - "0.0867756000, 0.0913790000, 0.1030543000, 0.1307077000, 0.1981778000, 0.3654149000, 0.7829100000", \ - "0.0943314000, 0.0987611000, 0.1105880000, 0.1383556000, 0.2059986000, 0.3731596000, 0.7916428000", \ - "0.1097743000, 0.1144445000, 0.1259078000, 0.1538339000, 0.2219342000, 0.3897174000, 0.8077481000", \ - "0.1365483000, 0.1420223000, 0.1548189000, 0.1862619000, 0.2570142000, 0.4252305000, 0.8440710000", \ - "0.1703406000, 0.1780909000, 0.1974683000, 0.2371138000, 0.3229129000, 0.5056385000, 0.9271798000", \ - "0.1859480000, 0.1978545000, 0.2269623000, 0.2883691000, 0.4139868000, 0.6483840000, 1.1167376000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0505421000, 0.0536709000, 0.0612098000, 0.0799903000, 0.1258654000, 0.2385742000, 0.5213558000", \ - "0.0558921000, 0.0590556000, 0.0666597000, 0.0855136000, 0.1314508000, 0.2441322000, 0.5274782000", \ - "0.0688099000, 0.0720520000, 0.0798423000, 0.0987233000, 0.1447745000, 0.2578033000, 0.5407069000", \ - "0.1002887000, 0.1035557000, 0.1113762000, 0.1300434000, 0.1760600000, 0.2879227000, 0.5713223000", \ - "0.1592497000, 0.1642225000, 0.1756432000, 0.2007854000, 0.2504928000, 0.3629451000, 0.6452827000", \ - "0.2524571000, 0.2602888000, 0.2786348000, 0.3191659000, 0.3968418000, 0.5357416000, 0.8171525000", \ - "0.4053173000, 0.4178160000, 0.4457784000, 0.5080761000, 0.6321838000, 0.8533942000, 1.2163315000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0644627000, 0.0700719000, 0.0835497000, 0.1187296000, 0.2080111000, 0.4337232000, 1.0025374000", \ - "0.0645621000, 0.0698387000, 0.0836714000, 0.1189907000, 0.2077511000, 0.4334462000, 1.0024150000", \ - "0.0643154000, 0.0698503000, 0.0835377000, 0.1187357000, 0.2079865000, 0.4328292000, 1.0024686000", \ - "0.0664911000, 0.0716745000, 0.0850786000, 0.1191605000, 0.2078615000, 0.4334895000, 1.0026765000", \ - "0.0798117000, 0.0849888000, 0.0980261000, 0.1306215000, 0.2135868000, 0.4336063000, 1.0026765000", \ - "0.1157626000, 0.1220679000, 0.1357771000, 0.1693372000, 0.2497798000, 0.4544597000, 1.0053343000", \ - "0.1913358000, 0.1991293000, 0.2194179000, 0.2602786000, 0.3505328000, 0.5503982000, 1.0563908000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0558202000, 0.0602026000, 0.0713124000, 0.0989208000, 0.1663969000, 0.3292171000, 0.7349216000", \ - "0.0557906000, 0.0601969000, 0.0712712000, 0.0989085000, 0.1663836000, 0.3291466000, 0.7370892000", \ - "0.0553005000, 0.0598944000, 0.0711129000, 0.0987979000, 0.1663847000, 0.3290652000, 0.7365059000", \ - "0.0624798000, 0.0660622000, 0.0754957000, 0.1005594000, 0.1662769000, 0.3291758000, 0.7372731000", \ - "0.0973465000, 0.1007130000, 0.1088869000, 0.1277566000, 0.1810417000, 0.3303150000, 0.7358897000", \ - "0.1655688000, 0.1703366000, 0.1815940000, 0.2068854000, 0.2576778000, 0.3761529000, 0.7394499000", \ - "0.2761954000, 0.2838251000, 0.3010739000, 0.3410749000, 0.4181723000, 0.5613306000, 0.8517277000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0742282000, 0.0788130000, 0.0903550000, 0.1179416000, 0.1853321000, 0.3519501000, 0.7700317000", \ - "0.0779482000, 0.0825394000, 0.0940162000, 0.1218550000, 0.1893739000, 0.3560510000, 0.7742409000", \ - "0.0865871000, 0.0910451000, 0.1024960000, 0.1305852000, 0.1983238000, 0.3656577000, 0.7832114000", \ - "0.1060685000, 0.1107700000, 0.1224368000, 0.1502759000, 0.2185161000, 0.3862201000, 0.8050622000", \ - "0.1402560000, 0.1463104000, 0.1614152000, 0.1943197000, 0.2657067000, 0.4341581000, 0.8529835000", \ - "0.1798499000, 0.1888193000, 0.2103415000, 0.2576037000, 0.3534466000, 0.5418190000, 0.9654795000", \ - "0.1998284000, 0.2137631000, 0.2469891000, 0.3199759000, 0.4665787000, 0.7327893000, 1.2136719000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0457874000, 0.0489174000, 0.0567829000, 0.0760007000, 0.1235474000, 0.2416939000, 0.5394520000", \ - "0.0509487000, 0.0542045000, 0.0621134000, 0.0815444000, 0.1294286000, 0.2481085000, 0.5471001000", \ - "0.0641463000, 0.0673788000, 0.0754122000, 0.0950867000, 0.1430521000, 0.2611713000, 0.5591128000", \ - "0.0952405000, 0.0988205000, 0.1072987000, 0.1267291000, 0.1748973000, 0.2940551000, 0.5927521000", \ - "0.1507337000, 0.1563910000, 0.1694497000, 0.1972136000, 0.2500082000, 0.3686184000, 0.6671589000", \ - "0.2406611000, 0.2493928000, 0.2703263000, 0.3152672000, 0.3994892000, 0.5450425000, 0.8409234000", \ - "0.3906235000, 0.4040322000, 0.4365661000, 0.5075824000, 0.6422577000, 0.8760787000, 1.2491483000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0643790000, 0.0699251000, 0.0838844000, 0.1188452000, 0.2080675000, 0.4328964000, 1.0015142000", \ - "0.0643848000, 0.0699212000, 0.0835743000, 0.1188761000, 0.2079825000, 0.4328100000, 1.0033274000", \ - "0.0642965000, 0.0698315000, 0.0835937000, 0.1188358000, 0.2078096000, 0.4334560000, 1.0027000000", \ - "0.0670409000, 0.0723536000, 0.0853067000, 0.1193288000, 0.2078326000, 0.4331264000, 1.0026602000", \ - "0.0859882000, 0.0912739000, 0.1049485000, 0.1362553000, 0.2155213000, 0.4334103000, 1.0027590000", \ - "0.1293962000, 0.1360378000, 0.1519806000, 0.1887398000, 0.2690047000, 0.4591459000, 1.0040397000", \ - "0.2097705000, 0.2193437000, 0.2421116000, 0.2924085000, 0.3950938000, 0.5973396000, 1.0725999000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0474941000, 0.0519940000, 0.0641410000, 0.0936365000, 0.1648542000, 0.3351844000, 0.7606423000", \ - "0.0474895000, 0.0520777000, 0.0640087000, 0.0935626000, 0.1648443000, 0.3353163000, 0.7611444000", \ - "0.0474364000, 0.0519999000, 0.0639911000, 0.0934003000, 0.1648733000, 0.3352572000, 0.7600283000", \ - "0.0565700000, 0.0605487000, 0.0700122000, 0.0957818000, 0.1647802000, 0.3352137000, 0.7615055000", \ - "0.0943986000, 0.0978628000, 0.1060174000, 0.1248011000, 0.1788678000, 0.3359551000, 0.7618409000", \ - "0.1650284000, 0.1698623000, 0.1808330000, 0.2064811000, 0.2579977000, 0.3795939000, 0.7636893000", \ - "0.2795832000, 0.2874575000, 0.3053543000, 0.3441836000, 0.4212370000, 0.5625221000, 0.8646679000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0553888000, 0.0601340000, 0.0717097000, 0.0994842000, 0.1667338000, 0.3336309000, 0.7526770000", \ - "0.0585486000, 0.0632071000, 0.0749123000, 0.1025481000, 0.1703892000, 0.3375303000, 0.7552651000", \ - "0.0668188000, 0.0714738000, 0.0829734000, 0.1109060000, 0.1789307000, 0.3461158000, 0.7643627000", \ - "0.0889680000, 0.0934864000, 0.1041815000, 0.1312067000, 0.1997292000, 0.3672880000, 0.7857514000", \ - "0.1219726000, 0.1286768000, 0.1442984000, 0.1781178000, 0.2477971000, 0.4149131000, 0.8347446000", \ - "0.1558004000, 0.1650333000, 0.1885842000, 0.2376970000, 0.3410771000, 0.5318045000, 0.9491026000", \ - "0.1719792000, 0.1861888000, 0.2203748000, 0.2948378000, 0.4471023000, 0.7261931000, 1.2167964000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0302071000, 0.0332512000, 0.0407766000, 0.0585620000, 0.1022749000, 0.2111899000, 0.4867224000", \ - "0.0354398000, 0.0384867000, 0.0460005000, 0.0639625000, 0.1080606000, 0.2170685000, 0.4929798000", \ - "0.0489119000, 0.0518627000, 0.0592094000, 0.0773074000, 0.1216938000, 0.2302595000, 0.5045913000", \ - "0.0748127000, 0.0793401000, 0.0892577000, 0.1086167000, 0.1533102000, 0.2624705000, 0.5381888000", \ - "0.1153934000, 0.1225934000, 0.1384146000, 0.1703759000, 0.2269801000, 0.3367581000, 0.6096149000", \ - "0.1802453000, 0.1916273000, 0.2169014000, 0.2675706000, 0.3595446000, 0.5081540000, 0.7826111000", \ - "0.2917548000, 0.3080179000, 0.3456621000, 0.4244288000, 0.5689585000, 0.8085798000, 1.1761110000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0646015000, 0.0702364000, 0.0838006000, 0.1188083000, 0.2076059000, 0.4333174000, 1.0027392000", \ - "0.0646194000, 0.0698606000, 0.0836938000, 0.1189290000, 0.2078386000, 0.4334525000, 1.0028435000", \ - "0.0619020000, 0.0676776000, 0.0822439000, 0.1185981000, 0.2078955000, 0.4329454000, 1.0025055000", \ - "0.0678190000, 0.0726141000, 0.0852017000, 0.1181870000, 0.2073723000, 0.4331049000, 1.0026880000", \ - "0.0879091000, 0.0940148000, 0.1089331000, 0.1430982000, 0.2182667000, 0.4329320000, 1.0032709000", \ - "0.1314507000, 0.1398581000, 0.1596193000, 0.2013400000, 0.2872505000, 0.4722592000, 1.0038264000", \ - "0.2099235000, 0.2222721000, 0.2501776000, 0.3112175000, 0.4274199000, 0.6461852000, 1.1021205000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012617200, 0.0031838600, 0.0080342800, 0.0202740000, 0.0511601000, 0.1290990000"); - values("0.0325904000, 0.0368022000, 0.0478567000, 0.0754419000, 0.1416361000, 0.2996484000, 0.6929137000", \ - "0.0325064000, 0.0368983000, 0.0476589000, 0.0754299000, 0.1417262000, 0.2998033000, 0.6932494000", \ - "0.0348070000, 0.0384184000, 0.0486466000, 0.0751671000, 0.1417129000, 0.2997585000, 0.6922760000", \ - "0.0522957000, 0.0539628000, 0.0606890000, 0.0818813000, 0.1423057000, 0.2998713000, 0.6929851000", \ - "0.0916570000, 0.0944715000, 0.1017389000, 0.1189674000, 0.1638284000, 0.3020283000, 0.6923753000", \ - "0.1612590000, 0.1651983000, 0.1750782000, 0.1992639000, 0.2490582000, 0.3561035000, 0.6974833000", \ - "0.2729485000, 0.2787249000, 0.2949947000, 0.3323077000, 0.4095786000, 0.5471864000, 0.8209010000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2111ai_4") { - leakage_power () { - value : 0.0001554000; - when : "!A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 8.7651755e-05; - when : "!A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0003827000; - when : "!A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001354000; - when : "!A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0003493000; - when : "!A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001296000; - when : "!A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0031880000; - when : "!A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0003407000; - when : "!A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0002086000; - when : "!A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0001018000; - when : "!A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0015177000; - when : "!A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001846000; - when : "!A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0014926000; - when : "!A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001760000; - when : "!A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0107099000; - when : "!A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0019084000; - when : "!A1&A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0002086000; - when : "A1&!A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0001018000; - when : "A1&!A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0015177000; - when : "A1&!A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001846000; - when : "A1&!A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0014926000; - when : "A1&!A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001760000; - when : "A1&!A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0116937000; - when : "A1&!A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0019140000; - when : "A1&!A2&B1&C1&!D1"; - } - leakage_power () { - value : 0.0002086000; - when : "A1&A2&!B1&!C1&D1"; - } - leakage_power () { - value : 0.0001018000; - when : "A1&A2&!B1&!C1&!D1"; - } - leakage_power () { - value : 0.0015177000; - when : "A1&A2&!B1&C1&D1"; - } - leakage_power () { - value : 0.0001847000; - when : "A1&A2&!B1&C1&!D1"; - } - leakage_power () { - value : 0.0014926000; - when : "A1&A2&B1&!C1&D1"; - } - leakage_power () { - value : 0.0001760000; - when : "A1&A2&B1&!C1&!D1"; - } - leakage_power () { - value : 0.0074550000; - when : "A1&A2&B1&C1&D1"; - } - leakage_power () { - value : 0.0019123000; - when : "A1&A2&B1&C1&!D1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__o2111ai"; - cell_leakage_power : 0.0016064340; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0086720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157913000, 0.0157868000, 0.0157763000, 0.0157820000, 0.0157949000, 0.0158248000, 0.0158938000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015767000, -0.015763000, -0.015753900, -0.015749700, -0.015740200, -0.015718200, -0.015667600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091090000; - } - pin ("A2") { - capacitance : 0.0084330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156436000, 0.0156443000, 0.0156460000, 0.0156436000, 0.0156381000, 0.0156254000, 0.0155961000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015630000, -0.015626200, -0.015617500, -0.015618900, -0.015622100, -0.015629400, -0.015646300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090530000; - } - pin ("B1") { - capacitance : 0.0084830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155884000, 0.0155809000, 0.0155634000, 0.0155662000, 0.0155726000, 0.0155872000, 0.0156210000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015641100, -0.015618500, -0.015566500, -0.015568400, -0.015572600, -0.015582300, -0.015604800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088150000; - } - pin ("C1") { - capacitance : 0.0083670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0172187000, 0.0172000000, 0.0171569000, 0.0172217000, 0.0173712000, 0.0177158000, 0.0185101000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015669800, -0.015653900, -0.015617200, -0.015612200, -0.015600600, -0.015574100, -0.015512800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086130000; - } - pin ("D1") { - capacitance : 0.0083610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181415000, 0.0181372000, 0.0181273000, 0.0181319000, 0.0181426000, 0.0181673000, 0.0182242000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013200900, -0.013192400, -0.013172600, -0.013138400, -0.013059600, -0.012877800, -0.012458900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0084880000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1) | (!D1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0293599000, 0.0279618000, 0.0241086000, 0.0134875000, -0.015752800, -0.096220400, -0.317678100", \ - "0.0288857000, 0.0274958000, 0.0236354000, 0.0130168000, -0.016200600, -0.096662600, -0.318086500", \ - "0.0283480000, 0.0269455000, 0.0230985000, 0.0125360000, -0.016626400, -0.097047800, -0.318484700", \ - "0.0275663000, 0.0261984000, 0.0224233000, 0.0119393000, -0.017072300, -0.097384700, -0.318784000", \ - "0.0270614000, 0.0256755000, 0.0218897000, 0.0114137000, -0.017488000, -0.097582000, -0.318771900", \ - "0.0271324000, 0.0257253000, 0.0219557000, 0.0108749000, -0.018193100, -0.098073400, -0.319109300", \ - "0.0285013000, 0.0270623000, 0.0231505000, 0.0123822000, -0.017114700, -0.098144600, -0.319298900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0627156000, 0.0641428000, 0.0680539000, 0.0789226000, 0.1084044000, 0.1887059000, 0.4084574000", \ - "0.0621957000, 0.0636102000, 0.0676441000, 0.0784631000, 0.1079312000, 0.1885161000, 0.4076963000", \ - "0.0617554000, 0.0632225000, 0.0671715000, 0.0778205000, 0.1073967000, 0.1879968000, 0.4073141000", \ - "0.0611965000, 0.0626319000, 0.0666038000, 0.0774428000, 0.1070465000, 0.1874808000, 0.4068492000", \ - "0.0605595000, 0.0619223000, 0.0658368000, 0.0766932000, 0.1064624000, 0.1871028000, 0.4068529000", \ - "0.0605196000, 0.0618667000, 0.0658120000, 0.0767553000, 0.1064494000, 0.1866863000, 0.4066561000", \ - "0.0612353000, 0.0625989000, 0.0665092000, 0.0777664000, 0.1071570000, 0.1880082000, 0.4071944000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0237637000, 0.0223278000, 0.0184909000, 0.0078835000, -0.021370500, -0.102048200, -0.323679300", \ - "0.0234533000, 0.0220870000, 0.0183065000, 0.0078249000, -0.021293100, -0.101868200, -0.323531200", \ - "0.0225110000, 0.0212182000, 0.0175882000, 0.0074140000, -0.021497500, -0.101830100, -0.323402200", \ - "0.0212434000, 0.0199388000, 0.0163758000, 0.0063380000, -0.022131100, -0.102111800, -0.323416200", \ - "0.0203242000, 0.0190180000, 0.0152957000, 0.0051344000, -0.023239000, -0.102728800, -0.323611400", \ - "0.0203124000, 0.0189276000, 0.0151702000, 0.0046905000, -0.024351600, -0.103767600, -0.324255000", \ - "0.0216964000, 0.0202483000, 0.0162569000, 0.0055070000, -0.023844800, -0.104382900, -0.325040400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0540709000, 0.0554951000, 0.0594145000, 0.0701521000, 0.0997897000, 0.1803881000, 0.3994325000", \ - "0.0533807000, 0.0547759000, 0.0589468000, 0.0695594000, 0.0991941000, 0.1796296000, 0.3992679000", \ - "0.0525721000, 0.0540039000, 0.0579809000, 0.0690113000, 0.0985685000, 0.1792605000, 0.3983983000", \ - "0.0516806000, 0.0531223000, 0.0570568000, 0.0681105000, 0.0977944000, 0.1787185000, 0.3981380000", \ - "0.0510980000, 0.0525407000, 0.0564879000, 0.0672821000, 0.0971271000, 0.1779685000, 0.3977742000", \ - "0.0532048000, 0.0546019000, 0.0586343000, 0.0689002000, 0.0982488000, 0.1788694000, 0.3969841000", \ - "0.0570959000, 0.0584128000, 0.0620680000, 0.0722889000, 0.1010952000, 0.1807988000, 0.3985185000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0302835000, 0.0288812000, 0.0250811000, 0.0145084000, -0.014663200, -0.095104300, -0.316553800", \ - "0.0298594000, 0.0284935000, 0.0247441000, 0.0142301000, -0.014838100, -0.095229500, -0.316645900", \ - "0.0291473000, 0.0277984000, 0.0240291000, 0.0136565000, -0.015263600, -0.095474700, -0.316801900", \ - "0.0281520000, 0.0268281000, 0.0231365000, 0.0128128000, -0.015908000, -0.095857500, -0.316977200", \ - "0.0275585000, 0.0261802000, 0.0223649000, 0.0120009000, -0.016690700, -0.096413100, -0.317218100", \ - "0.0272003000, 0.0257765000, 0.0219254000, 0.0113967000, -0.017502600, -0.097207300, -0.317814900", \ - "0.0287836000, 0.0273395000, 0.0234080000, 0.0126725000, -0.016829200, -0.097653700, -0.318309600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0485962000, 0.0500262000, 0.0539626000, 0.0647042000, 0.0940175000, 0.1740641000, 0.3930927000", \ - "0.0481110000, 0.0495550000, 0.0535393000, 0.0643612000, 0.0937979000, 0.1738627000, 0.3927983000", \ - "0.0472025000, 0.0486660000, 0.0526659000, 0.0636487000, 0.0932662000, 0.1735187000, 0.3927410000", \ - "0.0460750000, 0.0475491000, 0.0516065000, 0.0625599000, 0.0922723000, 0.1729004000, 0.3926693000", \ - "0.0452585000, 0.0466936000, 0.0507831000, 0.0616950000, 0.0913832000, 0.1719597000, 0.3912006000", \ - "0.0466784000, 0.0480953000, 0.0519699000, 0.0627801000, 0.0919398000, 0.1721272000, 0.3897555000", \ - "0.0500457000, 0.0513682000, 0.0550152000, 0.0651407000, 0.0943503000, 0.1743362000, 0.3914808000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0302733000, 0.0288302000, 0.0250294000, 0.0145276000, -0.014624800, -0.095044300, -0.316496700", \ - "0.0298159000, 0.0284094000, 0.0246616000, 0.0142400000, -0.014790600, -0.095143400, -0.316521300", \ - "0.0290477000, 0.0277161000, 0.0240003000, 0.0136390000, -0.015204800, -0.095372200, -0.316665700", \ - "0.0281828000, 0.0268145000, 0.0231114000, 0.0128159000, -0.015877600, -0.095769200, -0.316837400", \ - "0.0275722000, 0.0262333000, 0.0224872000, 0.0120323000, -0.016640600, -0.096352100, -0.317130400", \ - "0.0273511000, 0.0260201000, 0.0221165000, 0.0115425000, -0.017494800, -0.097353500, -0.317826900", \ - "0.0294383000, 0.0279982000, 0.0240279000, 0.0131505000, -0.016444700, -0.097379500, -0.318199400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0364276000, 0.0378726000, 0.0418588000, 0.0526452000, 0.0820126000, 0.1618470000, 0.3804085000", \ - "0.0358185000, 0.0373039000, 0.0413738000, 0.0523486000, 0.0819467000, 0.1619298000, 0.3809844000", \ - "0.0348127000, 0.0363112000, 0.0404822000, 0.0515670000, 0.0813868000, 0.1618274000, 0.3810843000", \ - "0.0337501000, 0.0352941000, 0.0393913000, 0.0506588000, 0.0803992000, 0.1611680000, 0.3803382000", \ - "0.0327154000, 0.0341630000, 0.0381264000, 0.0490754000, 0.0789462000, 0.1590363000, 0.3793920000", \ - "0.0336493000, 0.0350508000, 0.0388672000, 0.0495188000, 0.0790628000, 0.1596913000, 0.3770027000", \ - "0.0363057000, 0.0376019000, 0.0411963000, 0.0513652000, 0.0800385000, 0.1605926000, 0.3781336000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0272400000, 0.0259039000, 0.0221821000, 0.0118326000, -0.017186900, -0.097511300, -0.318971400", \ - "0.0266919000, 0.0253683000, 0.0216929000, 0.0113543000, -0.017421600, -0.097634300, -0.318982500", \ - "0.0259480000, 0.0246268000, 0.0209838000, 0.0107284000, -0.017960100, -0.097914100, -0.319086200", \ - "0.0250758000, 0.0237931000, 0.0200363000, 0.0098301000, -0.018732500, -0.098481900, -0.319366900", \ - "0.0250213000, 0.0236537000, 0.0198589000, 0.0091601000, -0.019453900, -0.099112400, -0.319795700", \ - "0.0260831000, 0.0247346000, 0.0205124000, 0.0098197000, -0.019998800, -0.100124900, -0.320760300", \ - "0.0301817000, 0.0286602000, 0.0244245000, 0.0132647000, -0.016536500, -0.097617000, -0.320684100"); - } - related_pin : "D1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0223177000, 0.0239674000, 0.0283127000, 0.0395483000, 0.0692876000, 0.1493142000, 0.3678410000", \ - "0.0216396000, 0.0232453000, 0.0276617000, 0.0390821000, 0.0690413000, 0.1493720000, 0.3682449000", \ - "0.0209610000, 0.0225342000, 0.0268117000, 0.0381864000, 0.0685223000, 0.1488837000, 0.3685210000", \ - "0.0204153000, 0.0219237000, 0.0260788000, 0.0373304000, 0.0673895000, 0.1483576000, 0.3676264000", \ - "0.0202662000, 0.0217194000, 0.0256432000, 0.0365707000, 0.0665466000, 0.1474383000, 0.3671629000", \ - "0.0222389000, 0.0235884000, 0.0273633000, 0.0379982000, 0.0675904000, 0.1467535000, 0.3660350000", \ - "0.0270011000, 0.0282117000, 0.0316494000, 0.0417159000, 0.0695425000, 0.1499453000, 0.3656871000"); - } - } - max_capacitance : 0.2151590000; - max_transition : 1.4993560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0941140000, 0.0971742000, 0.1051024000, 0.1263719000, 0.1827369000, 0.3343156000, 0.7464022000", \ - "0.0978351000, 0.1007795000, 0.1089318000, 0.1301303000, 0.1865516000, 0.3378409000, 0.7499820000", \ - "0.1054103000, 0.1082900000, 0.1161228000, 0.1373599000, 0.1940448000, 0.3458023000, 0.7578397000", \ - "0.1184979000, 0.1214506000, 0.1295139000, 0.1508152000, 0.2076543000, 0.3592291000, 0.7719902000", \ - "0.1380046000, 0.1412574000, 0.1500367000, 0.1728719000, 0.2316938000, 0.3842929000, 0.7981483000", \ - "0.1613026000, 0.1651645000, 0.1764360000, 0.2027806000, 0.2696545000, 0.4326089000, 0.8489896000", \ - "0.1630797000, 0.1692171000, 0.1856343000, 0.2255834000, 0.3155349000, 0.5094819000, 0.9603388000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1534684000, 0.1576660000, 0.1695477000, 0.2013185000, 0.2849416000, 0.5094677000, 1.1164690000", \ - "0.1577345000, 0.1625299000, 0.1736757000, 0.2061510000, 0.2902120000, 0.5140974000, 1.1213244000", \ - "0.1694235000, 0.1741220000, 0.1866113000, 0.2176698000, 0.3026329000, 0.5272990000, 1.1335998000", \ - "0.1948486000, 0.1991849000, 0.2110167000, 0.2431896000, 0.3272292000, 0.5521982000, 1.1592673000", \ - "0.2495590000, 0.2538817000, 0.2656240000, 0.2975657000, 0.3815246000, 0.6068342000, 1.2142019000", \ - "0.3541757000, 0.3591999000, 0.3725810000, 0.4111055000, 0.5036497000, 0.7311124000, 1.3404725000", \ - "0.5363499000, 0.5436003000, 0.5628917000, 0.6114267000, 0.7313721000, 1.0058717000, 1.6291671000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0724996000, 0.0762502000, 0.0856673000, 0.1125423000, 0.1871444000, 0.3941778000, 0.9632862000", \ - "0.0727635000, 0.0763118000, 0.0857342000, 0.1125435000, 0.1871213000, 0.3939626000, 0.9625576000", \ - "0.0726455000, 0.0761801000, 0.0859569000, 0.1125758000, 0.1870699000, 0.3942226000, 0.9628887000", \ - "0.0736208000, 0.0770953000, 0.0863308000, 0.1130836000, 0.1870974000, 0.3940775000, 0.9655641000", \ - "0.0811597000, 0.0845674000, 0.0940251000, 0.1197714000, 0.1913534000, 0.3947749000, 0.9643601000", \ - "0.1041061000, 0.1075451000, 0.1170020000, 0.1428628000, 0.2140393000, 0.4107110000, 0.9666725000", \ - "0.1695776000, 0.1737673000, 0.1835468000, 0.2117524000, 0.2828891000, 0.4723587000, 1.0089753000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1341151000, 0.1397363000, 0.1546077000, 0.1966087000, 0.3100704000, 0.6212041000, 1.4754494000", \ - "0.1342076000, 0.1393886000, 0.1550907000, 0.1970649000, 0.3108153000, 0.6216280000, 1.4752867000", \ - "0.1342099000, 0.1397978000, 0.1549803000, 0.1962974000, 0.3098499000, 0.6220033000, 1.4757725000", \ - "0.1338665000, 0.1394828000, 0.1546653000, 0.1966115000, 0.3103667000, 0.6210570000, 1.4746945000", \ - "0.1403998000, 0.1452780000, 0.1602580000, 0.2001905000, 0.3106480000, 0.6221431000, 1.4769923000", \ - "0.1762582000, 0.1811887000, 0.1956005000, 0.2339035000, 0.3357570000, 0.6311361000, 1.4798937000", \ - "0.2531555000, 0.2595251000, 0.2758582000, 0.3187715000, 0.4292053000, 0.7060559000, 1.4985411000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0760160000, 0.0786072000, 0.0859069000, 0.1057907000, 0.1602798000, 0.3069585000, 0.7096973000", \ - "0.0800928000, 0.0829275000, 0.0901699000, 0.1102573000, 0.1650643000, 0.3115701000, 0.7144820000", \ - "0.0870801000, 0.0899543000, 0.0975827000, 0.1184237000, 0.1725405000, 0.3209079000, 0.7224112000", \ - "0.0990497000, 0.1020810000, 0.1100926000, 0.1312047000, 0.1865866000, 0.3341088000, 0.7399523000", \ - "0.1151578000, 0.1183927000, 0.1271825000, 0.1509808000, 0.2099352000, 0.3591558000, 0.7628376000", \ - "0.1276721000, 0.1323852000, 0.1448537000, 0.1745471000, 0.2446169000, 0.4079311000, 0.8163544000", \ - "0.1006937000, 0.1083167000, 0.1280052000, 0.1754038000, 0.2765408000, 0.4846594000, 0.9290038000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1397753000, 0.1441482000, 0.1557864000, 0.1872005000, 0.2711803000, 0.4954558000, 1.1031719000", \ - "0.1424562000, 0.1463764000, 0.1591707000, 0.1912353000, 0.2751503000, 0.4992758000, 1.1062510000", \ - "0.1527138000, 0.1575942000, 0.1691882000, 0.2013555000, 0.2852295000, 0.5096087000, 1.1174096000", \ - "0.1794854000, 0.1843144000, 0.1956890000, 0.2271689000, 0.3120451000, 0.5368989000, 1.1448654000", \ - "0.2472000000, 0.2514821000, 0.2632334000, 0.2945424000, 0.3787239000, 0.6043404000, 1.2118873000", \ - "0.3839896000, 0.3899255000, 0.4054121000, 0.4453770000, 0.5361619000, 0.7578445000, 1.3627706000", \ - "0.6068266000, 0.6154857000, 0.6385362000, 0.6971986000, 0.8348348000, 1.1225303000, 1.7299455000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0513772000, 0.0549110000, 0.0646019000, 0.0915668000, 0.1657456000, 0.3696824000, 0.9264256000", \ - "0.0512721000, 0.0548003000, 0.0646946000, 0.0915665000, 0.1657472000, 0.3681329000, 0.9273901000", \ - "0.0514116000, 0.0549755000, 0.0644617000, 0.0913109000, 0.1651590000, 0.3695107000, 0.9245654000", \ - "0.0534847000, 0.0569198000, 0.0664507000, 0.0923178000, 0.1654128000, 0.3677423000, 0.9270412000", \ - "0.0634008000, 0.0667034000, 0.0759648000, 0.1015116000, 0.1710870000, 0.3696808000, 0.9248851000", \ - "0.0921178000, 0.0955514000, 0.1045843000, 0.1292330000, 0.1984963000, 0.3884146000, 0.9293246000", \ - "0.1632193000, 0.1670047000, 0.1774102000, 0.2054089000, 0.2760334000, 0.4629114000, 0.9734270000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1339347000, 0.1395181000, 0.1548045000, 0.1963728000, 0.3100705000, 0.6208255000, 1.4754538000", \ - "0.1339210000, 0.1395396000, 0.1553216000, 0.1964909000, 0.3109591000, 0.6217405000, 1.4750341000", \ - "0.1342321000, 0.1393978000, 0.1546724000, 0.1968870000, 0.3104930000, 0.6210383000, 1.4738415000", \ - "0.1335123000, 0.1393088000, 0.1548100000, 0.1966955000, 0.3100170000, 0.6214972000, 1.4771574000", \ - "0.1432459000, 0.1482150000, 0.1618465000, 0.2005517000, 0.3100640000, 0.6221548000, 1.4768257000", \ - "0.2010815000, 0.2067360000, 0.2220654000, 0.2597758000, 0.3503526000, 0.6278539000, 1.4775622000", \ - "0.3028257000, 0.3109770000, 0.3322061000, 0.3846877000, 0.5008961000, 0.7529418000, 1.4993560000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0886280000, 0.0916511000, 0.0997693000, 0.1211666000, 0.1775659000, 0.3288372000, 0.7415755000", \ - "0.0923864000, 0.0954768000, 0.1035443000, 0.1250165000, 0.1815129000, 0.3331050000, 0.7458810000", \ - "0.0993144000, 0.1026521000, 0.1107357000, 0.1324091000, 0.1892672000, 0.3414233000, 0.7561367000", \ - "0.1139438000, 0.1170153000, 0.1252042000, 0.1469373000, 0.2041111000, 0.3563968000, 0.7692990000", \ - "0.1387530000, 0.1422928000, 0.1510816000, 0.1753362000, 0.2363396000, 0.3894008000, 0.8032124000", \ - "0.1695511000, 0.1744337000, 0.1876542000, 0.2194043000, 0.2931171000, 0.4639133000, 0.8820225000", \ - "0.1751403000, 0.1833677000, 0.2032453000, 0.2530279000, 0.3629043000, 0.5855808000, 1.0556034000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0647950000, 0.0671382000, 0.0734468000, 0.0901813000, 0.1348611000, 0.2545822000, 0.5807281000", \ - "0.0701705000, 0.0725373000, 0.0787427000, 0.0956855000, 0.1405810000, 0.2604318000, 0.5863885000", \ - "0.0828799000, 0.0852590000, 0.0917638000, 0.1087664000, 0.1537852000, 0.2739058000, 0.5997784000", \ - "0.1143356000, 0.1166651000, 0.1229851000, 0.1399853000, 0.1852371000, 0.3055572000, 0.6325518000", \ - "0.1806258000, 0.1838794000, 0.1924161000, 0.2135744000, 0.2601070000, 0.3802245000, 0.7055854000", \ - "0.2905612000, 0.2956319000, 0.3089647000, 0.3423474000, 0.4134764000, 0.5550003000, 0.8781912000", \ - "0.4757837000, 0.4834886000, 0.5037908000, 0.5546832000, 0.6683799000, 0.8919132000, 1.2835325000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0728218000, 0.0759812000, 0.0856751000, 0.1127046000, 0.1872187000, 0.3939862000, 0.9635447000", \ - "0.0727671000, 0.0761650000, 0.0858354000, 0.1125629000, 0.1872129000, 0.3939543000, 0.9633966000", \ - "0.0727739000, 0.0761637000, 0.0859014000, 0.1125765000, 0.1870880000, 0.3941938000, 0.9680803000", \ - "0.0745392000, 0.0780023000, 0.0872661000, 0.1132145000, 0.1869744000, 0.3940203000, 0.9644734000", \ - "0.0874501000, 0.0906586000, 0.0997918000, 0.1250720000, 0.1938761000, 0.3949596000, 0.9633122000", \ - "0.1232031000, 0.1266938000, 0.1363375000, 0.1620146000, 0.2301386000, 0.4172347000, 0.9687739000", \ - "0.2021078000, 0.2074223000, 0.2200710000, 0.2520133000, 0.3295995000, 0.5170425000, 1.0210267000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0722812000, 0.0755569000, 0.0845451000, 0.1088400000, 0.1731284000, 0.3449092000, 0.8171291000", \ - "0.0722910000, 0.0755739000, 0.0844720000, 0.1088554000, 0.1731568000, 0.3445318000, 0.8142285000", \ - "0.0721658000, 0.0754335000, 0.0843572000, 0.1088356000, 0.1731427000, 0.3448620000, 0.8136640000", \ - "0.0755544000, 0.0785685000, 0.0866399000, 0.1095785000, 0.1730703000, 0.3450017000, 0.8164152000", \ - "0.1068881000, 0.1092078000, 0.1148695000, 0.1324788000, 0.1849574000, 0.3451482000, 0.8145668000", \ - "0.1753579000, 0.1785747000, 0.1871794000, 0.2088220000, 0.2569335000, 0.3848008000, 0.8173088000", \ - "0.2909557000, 0.2959413000, 0.3091115000, 0.3415519000, 0.4143104000, 0.5583520000, 0.9041002000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0785515000, 0.0814092000, 0.0894685000, 0.1107255000, 0.1672262000, 0.3187917000, 0.7338403000", \ - "0.0819922000, 0.0849072000, 0.0930903000, 0.1146204000, 0.1713923000, 0.3233540000, 0.7354525000", \ - "0.0898344000, 0.0929462000, 0.1011813000, 0.1229230000, 0.1798992000, 0.3319546000, 0.7444821000", \ - "0.1083781000, 0.1114168000, 0.1196049000, 0.1413272000, 0.1986573000, 0.3512451000, 0.7644003000", \ - "0.1413384000, 0.1452935000, 0.1554847000, 0.1806008000, 0.2431682000, 0.3964395000, 0.8105194000", \ - "0.1776976000, 0.1837991000, 0.1988105000, 0.2361308000, 0.3203174000, 0.4973082000, 0.9175152000", \ - "0.1914504000, 0.2000898000, 0.2232195000, 0.2812325000, 0.4091784000, 0.6646414000, 1.1607619000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0525856000, 0.0548283000, 0.0607541000, 0.0767183000, 0.1194630000, 0.2347836000, 0.5501399000", \ - "0.0578490000, 0.0601109000, 0.0662282000, 0.0823475000, 0.1254481000, 0.2410898000, 0.5570508000", \ - "0.0706086000, 0.0728760000, 0.0789685000, 0.0953500000, 0.1388416000, 0.2553548000, 0.5715177000", \ - "0.1025593000, 0.1047912000, 0.1106967000, 0.1266031000, 0.1698469000, 0.2864718000, 0.6023499000", \ - "0.1611025000, 0.1647284000, 0.1741139000, 0.1967338000, 0.2451042000, 0.3605480000, 0.6762483000", \ - "0.2579934000, 0.2637292000, 0.2786341000, 0.3146514000, 0.3911134000, 0.5364073000, 0.8491541000", \ - "0.4208505000, 0.4295975000, 0.4525125000, 0.5088596000, 0.6309899000, 0.8624558000, 1.2582216000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0726057000, 0.0761776000, 0.0856180000, 0.1124856000, 0.1869913000, 0.3939631000, 0.9681821000", \ - "0.0726396000, 0.0762495000, 0.0857780000, 0.1124350000, 0.1872280000, 0.3942393000, 0.9648627000", \ - "0.0723877000, 0.0760702000, 0.0855653000, 0.1126741000, 0.1872207000, 0.3937432000, 0.9635697000", \ - "0.0750521000, 0.0785633000, 0.0877885000, 0.1138815000, 0.1868933000, 0.3940092000, 0.9638932000", \ - "0.0935546000, 0.0972152000, 0.1065843000, 0.1303779000, 0.1967514000, 0.3952858000, 0.9633023000", \ - "0.1364528000, 0.1413256000, 0.1518903000, 0.1802830000, 0.2506095000, 0.4255159000, 0.9659874000", \ - "0.2185490000, 0.2248429000, 0.2404999000, 0.2806714000, 0.3701394000, 0.5623589000, 1.0459513000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0548211000, 0.0580456000, 0.0668686000, 0.0910436000, 0.1546159000, 0.3202937000, 0.7707204000", \ - "0.0548282000, 0.0580887000, 0.0669537000, 0.0911196000, 0.1546113000, 0.3203340000, 0.7712103000", \ - "0.0547628000, 0.0579846000, 0.0669019000, 0.0911548000, 0.1545978000, 0.3201978000, 0.7714306000", \ - "0.0618653000, 0.0646237000, 0.0720596000, 0.0936534000, 0.1545902000, 0.3202623000, 0.7698250000", \ - "0.0982808000, 0.1006105000, 0.1068747000, 0.1222649000, 0.1703022000, 0.3211689000, 0.7716175000", \ - "0.1682671000, 0.1714341000, 0.1798011000, 0.2009177000, 0.2487122000, 0.3660685000, 0.7746038000", \ - "0.2833010000, 0.2882238000, 0.3011755000, 0.3333082000, 0.4052226000, 0.5463668000, 0.8709081000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0602019000, 0.0632141000, 0.0714034000, 0.0929501000, 0.1499309000, 0.3017916000, 0.7141247000", \ - "0.0630937000, 0.0662154000, 0.0743828000, 0.0961304000, 0.1534448000, 0.3053968000, 0.7179388000", \ - "0.0709888000, 0.0741094000, 0.0824268000, 0.1044320000, 0.1620261000, 0.3140375000, 0.7269005000", \ - "0.0927640000, 0.0957623000, 0.1035068000, 0.1244735000, 0.1820423000, 0.3345665000, 0.7494479000", \ - "0.1261513000, 0.1303935000, 0.1414455000, 0.1683121000, 0.2312433000, 0.3832352000, 0.7967388000", \ - "0.1599389000, 0.1664446000, 0.1827681000, 0.2228619000, 0.3132334000, 0.4972570000, 0.9116297000", \ - "0.1725433000, 0.1817129000, 0.2059492000, 0.2653051000, 0.3991029000, 0.6698010000, 1.1771796000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0334581000, 0.0355775000, 0.0412950000, 0.0558542000, 0.0940118000, 0.1965460000, 0.4781147000", \ - "0.0386511000, 0.0407454000, 0.0463935000, 0.0612287000, 0.0996988000, 0.2033822000, 0.4857110000", \ - "0.0520141000, 0.0540824000, 0.0595392000, 0.0743651000, 0.1132032000, 0.2166052000, 0.4971525000", \ - "0.0799953000, 0.0827223000, 0.0898567000, 0.1059192000, 0.1447695000, 0.2485343000, 0.5282410000", \ - "0.1242326000, 0.1287398000, 0.1400914000, 0.1658750000, 0.2174084000, 0.3218464000, 0.6026981000", \ - "0.1961354000, 0.2031711000, 0.2210601000, 0.2621010000, 0.3446363000, 0.4932130000, 0.7713217000", \ - "0.3218961000, 0.3305490000, 0.3572452000, 0.4206069000, 0.5519124000, 0.7857145000, 1.1726715000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0731234000, 0.0765758000, 0.0858617000, 0.1126220000, 0.1872518000, 0.3942733000, 0.9636598000", \ - "0.0728070000, 0.0762459000, 0.0861322000, 0.1129590000, 0.1871716000, 0.3938089000, 0.9644716000", \ - "0.0702424000, 0.0739780000, 0.0840711000, 0.1121006000, 0.1871341000, 0.3947898000, 0.9627156000", \ - "0.0750645000, 0.0782486000, 0.0866521000, 0.1123147000, 0.1861310000, 0.3939927000, 0.9640923000", \ - "0.0960381000, 0.1000957000, 0.1109924000, 0.1376426000, 0.2009216000, 0.3953388000, 0.9643283000", \ - "0.1410183000, 0.1462591000, 0.1599506000, 0.1945169000, 0.2688623000, 0.4407490000, 0.9659028000", \ - "0.2194027000, 0.2269846000, 0.2465415000, 0.2942794000, 0.4010527000, 0.6169533000, 1.0768456000"); - } - related_pin : "D1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0362883000, 0.0392157000, 0.0471847000, 0.0681305000, 0.1252954000, 0.2730591000, 0.6717015000", \ - "0.0363335000, 0.0390590000, 0.0469335000, 0.0682687000, 0.1253207000, 0.2731349000, 0.6712884000", \ - "0.0375793000, 0.0402140000, 0.0473608000, 0.0683300000, 0.1253701000, 0.2731650000, 0.6714541000", \ - "0.0525144000, 0.0541264000, 0.0589023000, 0.0751666000, 0.1262081000, 0.2732443000, 0.6713114000", \ - "0.0916611000, 0.0935817000, 0.0989376000, 0.1128703000, 0.1500460000, 0.2768074000, 0.6711742000", \ - "0.1605230000, 0.1631735000, 0.1702008000, 0.1902293000, 0.2351738000, 0.3341262000, 0.6772689000", \ - "0.2719483000, 0.2763956000, 0.2877932000, 0.3171503000, 0.3863656000, 0.5211892000, 0.7957215000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211a_1") { - leakage_power () { - value : 0.0104688000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0203015000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0110478000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0203640000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0108196000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0104991000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0040491000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0108088000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0108196000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0104991000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0046375000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0108088000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0108196000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0104991000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0032714000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0108088000; - when : "A1&A2&B1&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o211a"; - cell_leakage_power : 0.0106576600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041078000, 0.0041011000, 0.0040857000, 0.0040869000, 0.0040897000, 0.0040961000, 0.0041112000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004087400, -0.004089800, -0.004095500, -0.004094500, -0.004092400, -0.004087100, -0.004075100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024720000; - } - pin ("A2") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039684000, 0.0039646000, 0.0039556000, 0.0039560000, 0.0039569000, 0.0039589000, 0.0039638000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003955800, -0.003954100, -0.003950300, -0.003949700, -0.003948200, -0.003944600, -0.003936300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - } - pin ("B1") { - capacitance : 0.0023110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041155000, 0.0041031000, 0.0040745000, 0.0040816000, 0.0040980000, 0.0041360000, 0.0042235000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004010900, -0.004008100, -0.004001800, -0.004001600, -0.004001300, -0.004000400, -0.003998200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023940000; - } - pin ("C1") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047467000, 0.0047473000, 0.0047484000, 0.0047491000, 0.0047506000, 0.0047542000, 0.0047626000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003706500, -0.003707200, -0.003708800, -0.003702800, -0.003688800, -0.003656600, -0.003582200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024050000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0168119000, 0.0157553000, 0.0132132000, 0.0046567000, -0.020482900, -0.089526100, -0.274947100", \ - "0.0166670000, 0.0157275000, 0.0130656000, 0.0045296000, -0.020626000, -0.089622400, -0.275172200", \ - "0.0164964000, 0.0155521000, 0.0128959000, 0.0043735000, -0.020773300, -0.089805100, -0.275303400", \ - "0.0162785000, 0.0153549000, 0.0127121000, 0.0041614000, -0.020982600, -0.089998900, -0.275482100", \ - "0.0161322000, 0.0152031000, 0.0124952000, 0.0039779000, -0.021203300, -0.090166900, -0.275618300", \ - "0.0168537000, 0.0154894000, 0.0118612000, 0.0037095000, -0.021371600, -0.090313300, -0.275726000", \ - "0.0191931000, 0.0177972000, 0.0141423000, 0.0044947000, -0.021279600, -0.090043300, -0.275357200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0149390000, 0.0164256000, 0.0202966000, 0.0301740000, 0.0560084000, 0.1249253000, 0.3099603000", \ - "0.0148354000, 0.0163053000, 0.0201558000, 0.0300491000, 0.0559444000, 0.1253147000, 0.3088587000", \ - "0.0147025000, 0.0161919000, 0.0200040000, 0.0299214000, 0.0557789000, 0.1250723000, 0.3096579000", \ - "0.0144788000, 0.0159672000, 0.0198279000, 0.0296810000, 0.0555407000, 0.1243887000, 0.3081252000", \ - "0.0143225000, 0.0157861000, 0.0196235000, 0.0294599000, 0.0553034000, 0.1241576000, 0.3077309000", \ - "0.0146852000, 0.0160614000, 0.0197045000, 0.0292954000, 0.0552699000, 0.1244379000, 0.3091345000", \ - "0.0152356000, 0.0166097000, 0.0202066000, 0.0298628000, 0.0557455000, 0.1248092000, 0.3068276000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0145716000, 0.0136496000, 0.0109977000, 0.0025284000, -0.022608400, -0.091586300, -0.277187400", \ - "0.0143703000, 0.0135738000, 0.0108718000, 0.0023942000, -0.022781700, -0.091821700, -0.277215600", \ - "0.0142065000, 0.0132597000, 0.0105844000, 0.0021135000, -0.023018700, -0.092021100, -0.277501000", \ - "0.0139923000, 0.0130785000, 0.0103990000, 0.0019147000, -0.023215700, -0.092208200, -0.277673000", \ - "0.0142388000, 0.0133054000, 0.0105514000, 0.0019757000, -0.023224800, -0.092220000, -0.277670100", \ - "0.0149236000, 0.0135316000, 0.0104858000, 0.0022296000, -0.022921300, -0.091851500, -0.277234100", \ - "0.0181978000, 0.0167603000, 0.0130553000, 0.0033704000, -0.022484400, -0.091212100, -0.276524400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0134621000, 0.0149466000, 0.0188155000, 0.0286427000, 0.0544534000, 0.1232694000, 0.3068095000", \ - "0.0134150000, 0.0148980000, 0.0187185000, 0.0285929000, 0.0544011000, 0.1238064000, 0.3070757000", \ - "0.0132442000, 0.0147255000, 0.0185266000, 0.0283999000, 0.0544238000, 0.1230313000, 0.3072296000", \ - "0.0129103000, 0.0143876000, 0.0182115000, 0.0280621000, 0.0540833000, 0.1229105000, 0.3078735000", \ - "0.0126812000, 0.0140931000, 0.0179153000, 0.0276469000, 0.0534826000, 0.1225237000, 0.3079018000", \ - "0.0128963000, 0.0142773000, 0.0179782000, 0.0276052000, 0.0534235000, 0.1224013000, 0.3059627000", \ - "0.0132783000, 0.0146510000, 0.0183953000, 0.0282170000, 0.0540383000, 0.1229167000, 0.3058121000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0129824000, 0.0122440000, 0.0097501000, 0.0010888000, -0.024445200, -0.093738000, -0.279392900", \ - "0.0128306000, 0.0121085000, 0.0096083000, 0.0009511000, -0.024584700, -0.093869400, -0.279526200", \ - "0.0126313000, 0.0119057000, 0.0093941000, 0.0007300000, -0.024797800, -0.094068800, -0.279722500", \ - "0.0123306000, 0.0115762000, 0.0090343000, 0.0003621000, -0.025130700, -0.094362500, -0.280006700", \ - "0.0122387000, 0.0114235000, 0.0088484000, 0.0001971000, -0.025257800, -0.094438200, -0.280026400", \ - "0.0143173000, 0.0129943000, 0.0094442000, -0.000175100, -0.025059400, -0.094167700, -0.279694400", \ - "0.0161368000, 0.0147839000, 0.0119969000, 0.0022639000, -0.023545100, -0.092399200, -0.277878100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0150401000, 0.0165014000, 0.0203360000, 0.0302451000, 0.0561529000, 0.1254893000, 0.3096662000", \ - "0.0149600000, 0.0164444000, 0.0202575000, 0.0301641000, 0.0560200000, 0.1247181000, 0.3084218000", \ - "0.0147682000, 0.0162432000, 0.0201234000, 0.0299933000, 0.0558488000, 0.1247400000, 0.3097913000", \ - "0.0145616000, 0.0160408000, 0.0198784000, 0.0297507000, 0.0555952000, 0.1244570000, 0.3080033000", \ - "0.0143965000, 0.0158812000, 0.0196840000, 0.0294220000, 0.0552561000, 0.1247696000, 0.3093222000", \ - "0.0148198000, 0.0161666000, 0.0198287000, 0.0293780000, 0.0553163000, 0.1243906000, 0.3093847000", \ - "0.0157021000, 0.0171013000, 0.0205700000, 0.0302797000, 0.0561319000, 0.1252490000, 0.3086489000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0099617000, 0.0092590000, 0.0067253000, -0.002045300, -0.027720300, -0.097094300, -0.282822200", \ - "0.0097737000, 0.0090976000, 0.0065607000, -0.002208000, -0.027879900, -0.097246600, -0.282961200", \ - "0.0094730000, 0.0087620000, 0.0061907000, -0.002565600, -0.028190800, -0.097537900, -0.283259600", \ - "0.0091634000, 0.0084445000, 0.0058429000, -0.002917900, -0.028496400, -0.097813200, -0.283519100", \ - "0.0086752000, 0.0080300000, 0.0056373000, -0.003014700, -0.028542600, -0.097796400, -0.283461500", \ - "0.0114592000, 0.0101156000, 0.0065877000, -0.002849100, -0.028156800, -0.097358300, -0.282996100", \ - "0.0133380000, 0.0120348000, 0.0083525000, -0.001292700, -0.026921000, -0.095883700, -0.281450700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0145789000, 0.0160742000, 0.0198828000, 0.0298098000, 0.0556739000, 0.1250760000, 0.3096286000", \ - "0.0144545000, 0.0159600000, 0.0198019000, 0.0296747000, 0.0555706000, 0.1244199000, 0.3079228000", \ - "0.0142529000, 0.0157396000, 0.0195775000, 0.0294810000, 0.0553490000, 0.1241807000, 0.3092311000", \ - "0.0140253000, 0.0155050000, 0.0193683000, 0.0291798000, 0.0550395000, 0.1239401000, 0.3076368000", \ - "0.0138410000, 0.0153356000, 0.0191035000, 0.0288761000, 0.0547463000, 0.1237088000, 0.3074280000", \ - "0.0148210000, 0.0161557000, 0.0197949000, 0.0293305000, 0.0552161000, 0.1235892000, 0.3090799000", \ - "0.0161107000, 0.0175137000, 0.0210140000, 0.0306489000, 0.0563750000, 0.1254382000, 0.3088523000"); - } - } - max_capacitance : 0.1831150000; - max_transition : 1.5032510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1834713000, 0.1911791000, 0.2069496000, 0.2385668000, 0.3022844000, 0.4500007000, 0.8339674000", \ - "0.1886115000, 0.1962125000, 0.2122543000, 0.2437984000, 0.3074493000, 0.4551767000, 0.8398802000", \ - "0.2007182000, 0.2084008000, 0.2244567000, 0.2559996000, 0.3194324000, 0.4671062000, 0.8512598000", \ - "0.2264016000, 0.2340457000, 0.2501116000, 0.2815914000, 0.3453655000, 0.4930377000, 0.8772410000", \ - "0.2844687000, 0.2920758000, 0.3080828000, 0.3395491000, 0.4034409000, 0.5511172000, 0.9351577000", \ - "0.3980783000, 0.4065251000, 0.4241044000, 0.4576698000, 0.5239225000, 0.6728994000, 1.0569819000", \ - "0.5902466000, 0.6003312000, 0.6211468000, 0.6597587000, 0.7320264000, 0.8848763000, 1.2700859000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1141335000, 0.1220220000, 0.1394294000, 0.1776934000, 0.2703985000, 0.5133813000, 1.1617853000", \ - "0.1185723000, 0.1264295000, 0.1438439000, 0.1821854000, 0.2749900000, 0.5183234000, 1.1687278000", \ - "0.1277426000, 0.1355608000, 0.1528920000, 0.1913025000, 0.2840629000, 0.5282355000, 1.1750733000", \ - "0.1453754000, 0.1532688000, 0.1706346000, 0.2088632000, 0.3015653000, 0.5450937000, 1.1920278000", \ - "0.1781119000, 0.1863567000, 0.2043074000, 0.2432460000, 0.3362589000, 0.5797940000, 1.2283039000", \ - "0.2254597000, 0.2349918000, 0.2543979000, 0.2956394000, 0.3895703000, 0.6329105000, 1.2825202000", \ - "0.2684523000, 0.2807693000, 0.3055314000, 0.3519763000, 0.4489545000, 0.6924266000, 1.3406863000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0269979000, 0.0319695000, 0.0444786000, 0.0707953000, 0.1358124000, 0.3171103000, 0.8207786000", \ - "0.0270426000, 0.0321968000, 0.0438507000, 0.0705437000, 0.1359349000, 0.3168930000, 0.8195211000", \ - "0.0273643000, 0.0320106000, 0.0438212000, 0.0701832000, 0.1355281000, 0.3170187000, 0.8163031000", \ - "0.0269530000, 0.0325756000, 0.0437880000, 0.0704511000, 0.1355926000, 0.3171627000, 0.8176643000", \ - "0.0269255000, 0.0320504000, 0.0437822000, 0.0704729000, 0.1355015000, 0.3172107000, 0.8204726000", \ - "0.0314610000, 0.0369057000, 0.0494710000, 0.0758758000, 0.1390240000, 0.3185037000, 0.8175664000", \ - "0.0406328000, 0.0470162000, 0.0598143000, 0.0870221000, 0.1507480000, 0.3247034000, 0.8209590000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0257089000, 0.0325334000, 0.0496639000, 0.0947914000, 0.2209148000, 0.5660918000, 1.4964250000", \ - "0.0254762000, 0.0325277000, 0.0497158000, 0.0950203000, 0.2207031000, 0.5684856000, 1.4954047000", \ - "0.0255992000, 0.0324969000, 0.0497210000, 0.0949104000, 0.2210415000, 0.5669848000, 1.4956558000", \ - "0.0255637000, 0.0324157000, 0.0497182000, 0.0948224000, 0.2210058000, 0.5668031000, 1.4912840000", \ - "0.0274696000, 0.0345805000, 0.0516042000, 0.0960714000, 0.2212077000, 0.5679029000, 1.4953901000", \ - "0.0325457000, 0.0396223000, 0.0570042000, 0.1001449000, 0.2230074000, 0.5659307000, 1.4950192000", \ - "0.0441869000, 0.0522020000, 0.0710067000, 0.1107832000, 0.2271646000, 0.5676657000, 1.4925137000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1689593000, 0.1766582000, 0.1927077000, 0.2240431000, 0.2876695000, 0.4354436000, 0.8201860000", \ - "0.1725742000, 0.1801192000, 0.1961950000, 0.2274050000, 0.2912615000, 0.4390419000, 0.8231462000", \ - "0.1832347000, 0.1908850000, 0.2068515000, 0.2384436000, 0.3020699000, 0.4497461000, 0.8342747000", \ - "0.2110605000, 0.2187249000, 0.2347313000, 0.2662622000, 0.3299036000, 0.4774485000, 0.8618921000", \ - "0.2789832000, 0.2866186000, 0.3024994000, 0.3338866000, 0.3978388000, 0.5455834000, 0.9303665000", \ - "0.4196353000, 0.4283084000, 0.4459363000, 0.4793242000, 0.5448643000, 0.6936104000, 1.0782150000", \ - "0.6451211000, 0.6564015000, 0.6782272000, 0.7179730000, 0.7886490000, 0.9404726000, 1.3265675000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0965892000, 0.1041330000, 0.1208733000, 0.1582695000, 0.2501216000, 0.4935592000, 1.1429052000", \ - "0.1012635000, 0.1087583000, 0.1255277000, 0.1629798000, 0.2549579000, 0.4979487000, 1.1486905000", \ - "0.1101221000, 0.1176018000, 0.1342823000, 0.1718025000, 0.2638311000, 0.5072245000, 1.1592595000", \ - "0.1267578000, 0.1342422000, 0.1509411000, 0.1884164000, 0.2805242000, 0.5242637000, 1.1808182000", \ - "0.1545882000, 0.1626652000, 0.1803005000, 0.2187195000, 0.3112947000, 0.5536825000, 1.2059884000", \ - "0.1888246000, 0.1985669000, 0.2185391000, 0.2591569000, 0.3527540000, 0.5956638000, 1.2465350000", \ - "0.2014209000, 0.2144482000, 0.2404468000, 0.2881080000, 0.3848843000, 0.6291460000, 1.2759868000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0269117000, 0.0326822000, 0.0438051000, 0.0707699000, 0.1355994000, 0.3168771000, 0.8197142000", \ - "0.0268095000, 0.0322041000, 0.0438365000, 0.0708900000, 0.1359359000, 0.3156481000, 0.8254766000", \ - "0.0272859000, 0.0322827000, 0.0436272000, 0.0703425000, 0.1356677000, 0.3176705000, 0.8259989000", \ - "0.0268969000, 0.0320485000, 0.0442360000, 0.0696750000, 0.1356789000, 0.3176480000, 0.8264349000", \ - "0.0272601000, 0.0328548000, 0.0440886000, 0.0707922000, 0.1359642000, 0.3161625000, 0.8243909000", \ - "0.0336397000, 0.0389077000, 0.0500880000, 0.0758778000, 0.1391660000, 0.3182649000, 0.8272402000", \ - "0.0476779000, 0.0538878000, 0.0663769000, 0.0906868000, 0.1501483000, 0.3248781000, 0.8232683000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0239138000, 0.0307623000, 0.0477249000, 0.0931097000, 0.2198106000, 0.5691929000, 1.4953758000", \ - "0.0238559000, 0.0307069000, 0.0476811000, 0.0930101000, 0.2193166000, 0.5673510000, 1.5007723000", \ - "0.0239712000, 0.0306614000, 0.0477225000, 0.0928555000, 0.2197476000, 0.5667966000, 1.4999190000", \ - "0.0241572000, 0.0308953000, 0.0478591000, 0.0931061000, 0.2197789000, 0.5660594000, 1.5032507000", \ - "0.0268985000, 0.0336456000, 0.0504802000, 0.0947326000, 0.2199635000, 0.5672678000, 1.5025938000", \ - "0.0335043000, 0.0406942000, 0.0571590000, 0.0993581000, 0.2223455000, 0.5658140000, 1.4934677000", \ - "0.0467325000, 0.0554697000, 0.0737525000, 0.1131560000, 0.2269858000, 0.5679773000, 1.4906922000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0888085000, 0.0950328000, 0.1088347000, 0.1374643000, 0.1972286000, 0.3417186000, 0.7258898000", \ - "0.0942517000, 0.1004806000, 0.1143151000, 0.1429452000, 0.2026923000, 0.3471850000, 0.7313010000", \ - "0.1074639000, 0.1137292000, 0.1275035000, 0.1560738000, 0.2158657000, 0.3603879000, 0.7446571000", \ - "0.1394995000, 0.1457143000, 0.1594932000, 0.1881271000, 0.2479763000, 0.3927062000, 0.7757077000", \ - "0.2078832000, 0.2147273000, 0.2294195000, 0.2591719000, 0.3196934000, 0.4646165000, 0.8471737000", \ - "0.3201356000, 0.3290081000, 0.3474765000, 0.3831429000, 0.4492589000, 0.5962155000, 0.9794340000", \ - "0.5008423000, 0.5120818000, 0.5372144000, 0.5835987000, 0.6619225000, 0.8147837000, 1.1990589000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1059578000, 0.1137941000, 0.1312019000, 0.1695842000, 0.2624223000, 0.5062993000, 1.1565733000", \ - "0.1100413000, 0.1178595000, 0.1352044000, 0.1735813000, 0.2662425000, 0.5111290000, 1.1582152000", \ - "0.1185960000, 0.1264329000, 0.1438533000, 0.1821273000, 0.2749382000, 0.5176414000, 1.1670377000", \ - "0.1383926000, 0.1461610000, 0.1634849000, 0.2017764000, 0.2944106000, 0.5379208000, 1.1864120000", \ - "0.1747488000, 0.1830046000, 0.2009973000, 0.2401024000, 0.3331052000, 0.5778369000, 1.2251182000", \ - "0.2222942000, 0.2317031000, 0.2515175000, 0.2921712000, 0.3860597000, 0.6299583000, 1.2791046000", \ - "0.2566902000, 0.2691471000, 0.2935429000, 0.3393731000, 0.4351043000, 0.6793223000, 1.3275142000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0190550000, 0.0242182000, 0.0363758000, 0.0629468000, 0.1280066000, 0.3117447000, 0.8231794000", \ - "0.0190708000, 0.0242896000, 0.0363800000, 0.0629484000, 0.1280382000, 0.3118595000, 0.8233123000", \ - "0.0190621000, 0.0241333000, 0.0363386000, 0.0628838000, 0.1277892000, 0.3128299000, 0.8225003000", \ - "0.0192194000, 0.0242161000, 0.0362569000, 0.0630833000, 0.1280168000, 0.3114095000, 0.8148541000", \ - "0.0226441000, 0.0277772000, 0.0394150000, 0.0653499000, 0.1288763000, 0.3146801000, 0.8148467000", \ - "0.0320934000, 0.0379346000, 0.0511647000, 0.0775272000, 0.1378765000, 0.3149090000, 0.8255712000", \ - "0.0460089000, 0.0530599000, 0.0698595000, 0.1012810000, 0.1584959000, 0.3226024000, 0.8179816000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0256001000, 0.0325961000, 0.0497561000, 0.0949973000, 0.2209615000, 0.5678911000, 1.4929464000", \ - "0.0255639000, 0.0325415000, 0.0497160000, 0.0949407000, 0.2204426000, 0.5680217000, 1.4960352000", \ - "0.0257013000, 0.0325195000, 0.0497685000, 0.0947321000, 0.2208292000, 0.5670212000, 1.4972749000", \ - "0.0254831000, 0.0324837000, 0.0496761000, 0.0948912000, 0.2206280000, 0.5680375000, 1.4950399000", \ - "0.0281473000, 0.0351088000, 0.0519924000, 0.0965343000, 0.2213947000, 0.5680084000, 1.4967472000", \ - "0.0342075000, 0.0408108000, 0.0573896000, 0.0999481000, 0.2232646000, 0.5667704000, 1.4981058000", \ - "0.0462141000, 0.0542268000, 0.0709916000, 0.1099566000, 0.2263019000, 0.5702230000, 1.4919967000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0742470000, 0.0802683000, 0.0936618000, 0.1215044000, 0.1805454000, 0.3246143000, 0.7082862000", \ - "0.0795443000, 0.0855682000, 0.0988942000, 0.1267439000, 0.1857934000, 0.3298586000, 0.7149746000", \ - "0.0924636000, 0.0984422000, 0.1117542000, 0.1396203000, 0.1987493000, 0.3429516000, 0.7262252000", \ - "0.1235539000, 0.1293231000, 0.1426197000, 0.1706332000, 0.2298686000, 0.3742219000, 0.7586827000", \ - "0.1821905000, 0.1892419000, 0.2041460000, 0.2342281000, 0.2949226000, 0.4395466000, 0.8241735000", \ - "0.2735686000, 0.2825815000, 0.3015908000, 0.3378570000, 0.4049527000, 0.5522070000, 0.9349432000", \ - "0.4168980000, 0.4292691000, 0.4536985000, 0.5014740000, 0.5812563000, 0.7350711000, 1.1185678000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0976449000, 0.1054930000, 0.1228207000, 0.1612373000, 0.2540615000, 0.4985007000, 1.1456061000", \ - "0.1012633000, 0.1091571000, 0.1265332000, 0.1648030000, 0.2574836000, 0.5011135000, 1.1487434000", \ - "0.1104023000, 0.1182176000, 0.1356039000, 0.1739851000, 0.2668151000, 0.5096090000, 1.1598114000", \ - "0.1328281000, 0.1406393000, 0.1579324000, 0.1960821000, 0.2887989000, 0.5324319000, 1.1794785000", \ - "0.1727079000, 0.1807469000, 0.1985624000, 0.2373912000, 0.3306180000, 0.5744514000, 1.2213788000", \ - "0.2208417000, 0.2301930000, 0.2495042000, 0.2894918000, 0.3829570000, 0.6271966000, 1.2787293000", \ - "0.2608172000, 0.2733521000, 0.2973406000, 0.3416127000, 0.4355610000, 0.6797343000, 1.3288491000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0176365000, 0.0226805000, 0.0347304000, 0.0613253000, 0.1267779000, 0.3116399000, 0.8144895000", \ - "0.0176525000, 0.0226940000, 0.0347219000, 0.0614252000, 0.1268537000, 0.3121316000, 0.8152470000", \ - "0.0176699000, 0.0226963000, 0.0347546000, 0.0614520000, 0.1271580000, 0.3131018000, 0.8296473000", \ - "0.0181207000, 0.0230721000, 0.0351258000, 0.0619154000, 0.1271949000, 0.3124269000, 0.8180421000", \ - "0.0232931000, 0.0283403000, 0.0402364000, 0.0661310000, 0.1291983000, 0.3141767000, 0.8157275000", \ - "0.0328210000, 0.0390400000, 0.0526568000, 0.0799140000, 0.1392932000, 0.3147728000, 0.8256829000", \ - "0.0460285000, 0.0538169000, 0.0716424000, 0.1052021000, 0.1624690000, 0.3242590000, 0.8151433000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0256426000, 0.0324781000, 0.0497493000, 0.0948929000, 0.2210238000, 0.5672914000, 1.4965493000", \ - "0.0255817000, 0.0325123000, 0.0497853000, 0.0948346000, 0.2209861000, 0.5673014000, 1.4915869000", \ - "0.0255941000, 0.0325005000, 0.0496924000, 0.0948141000, 0.2204974000, 0.5677738000, 1.4975244000", \ - "0.0257271000, 0.0326132000, 0.0498646000, 0.0949056000, 0.2210091000, 0.5666799000, 1.4931318000", \ - "0.0278103000, 0.0345572000, 0.0517923000, 0.0964843000, 0.2214578000, 0.5670993000, 1.4927535000", \ - "0.0344560000, 0.0409646000, 0.0571855000, 0.0994738000, 0.2235649000, 0.5671505000, 1.4980799000", \ - "0.0472187000, 0.0550050000, 0.0700543000, 0.1091059000, 0.2255518000, 0.5691194000, 1.4913433000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211a_2") { - leakage_power () { - value : 0.0038162000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0032149000; - when : "A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0030042000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0029646000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0035052000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0030019000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0031535000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0029699000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0043709000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0032149000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0031535000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0029699000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0041706000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0032149000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0031535000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0029699000; - when : "A1&A2&!B1&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o211a"; - cell_leakage_power : 0.0033030240; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0024100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042431000, 0.0042451000, 0.0042496000, 0.0042507000, 0.0042532000, 0.0042592000, 0.0042728000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004248600, -0.004247500, -0.004245000, -0.004245900, -0.004248100, -0.004253000, -0.004264500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025400000; - } - pin ("A2") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039540000, 0.0039392000, 0.0039052000, 0.0039057000, 0.0039070000, 0.0039099000, 0.0039166000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003914500, -0.003913000, -0.003909400, -0.003910000, -0.003911300, -0.003914200, -0.003920900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024870000; - } - pin ("B1") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042840000, 0.0042693000, 0.0042352000, 0.0042445000, 0.0042659000, 0.0043151000, 0.0044287000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004082300, -0.004080900, -0.004077700, -0.004077000, -0.004075200, -0.004071000, -0.004061400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("C1") { - capacitance : 0.0023710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048311000, 0.0048315000, 0.0048326000, 0.0048339000, 0.0048369000, 0.0048437000, 0.0048595000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003999900, -0.004005000, -0.004016600, -0.004009800, -0.003993900, -0.003957500, -0.003873400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0194563000, 0.0181173000, 0.0144544000, 0.0041945000, -0.028668500, -0.126923400, -0.408840200", \ - "0.0192967000, 0.0178653000, 0.0144263000, 0.0040016000, -0.028797100, -0.127033100, -0.408938800", \ - "0.0193017000, 0.0177663000, 0.0141608000, 0.0039393000, -0.028969000, -0.127202300, -0.409090400", \ - "0.0189398000, 0.0175147000, 0.0139025000, 0.0036213000, -0.029189500, -0.127384800, -0.409270000", \ - "0.0187675000, 0.0173223000, 0.0137334000, 0.0034046000, -0.029441400, -0.127571000, -0.409428400", \ - "0.0186811000, 0.0171837000, 0.0135394000, 0.0031493000, -0.029594200, -0.127667200, -0.409466200", \ - "0.0237617000, 0.0218993000, 0.0177098000, 0.0053340000, -0.029345200, -0.127573500, -0.409294500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0207355000, 0.0223530000, 0.0268324000, 0.0393099000, 0.0736744000, 0.1709998000, 0.4492098000", \ - "0.0206683000, 0.0222924000, 0.0267740000, 0.0392092000, 0.0735871000, 0.1709515000, 0.4492447000", \ - "0.0205596000, 0.0221623000, 0.0266910000, 0.0390488000, 0.0734421000, 0.1711325000, 0.4497113000", \ - "0.0203044000, 0.0218955000, 0.0264463000, 0.0388838000, 0.0732301000, 0.1708798000, 0.4495743000", \ - "0.0202430000, 0.0218116000, 0.0262457000, 0.0386874000, 0.0730983000, 0.1707506000, 0.4490447000", \ - "0.0207193000, 0.0221874000, 0.0264965000, 0.0385018000, 0.0730618000, 0.1703231000, 0.4490826000", \ - "0.0212892000, 0.0227488000, 0.0269758000, 0.0390473000, 0.0736576000, 0.1715142000, 0.4487095000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0174939000, 0.0159484000, 0.0123660000, 0.0021552000, -0.030737200, -0.128846700, -0.410682000", \ - "0.0172955000, 0.0158487000, 0.0121818000, 0.0018931000, -0.030879100, -0.128955000, -0.410784300", \ - "0.0171184000, 0.0158665000, 0.0122774000, 0.0019145000, -0.030939700, -0.129078800, -0.410894500", \ - "0.0169831000, 0.0155345000, 0.0118895000, 0.0015807000, -0.031208300, -0.129284400, -0.411088900", \ - "0.0167590000, 0.0153158000, 0.0117179000, 0.0013492000, -0.031432800, -0.129469500, -0.411247900", \ - "0.0170450000, 0.0155307000, 0.0122791000, 0.0017749000, -0.031027400, -0.129077200, -0.410805000", \ - "0.0228994000, 0.0211677000, 0.0165400000, 0.0041461000, -0.030568100, -0.128650600, -0.410381100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0192442000, 0.0208551000, 0.0253817000, 0.0379894000, 0.0728654000, 0.1712124000, 0.4490083000", \ - "0.0191756000, 0.0208031000, 0.0253446000, 0.0380087000, 0.0728739000, 0.1709435000, 0.4506852000", \ - "0.0190800000, 0.0206860000, 0.0252613000, 0.0378106000, 0.0727148000, 0.1708609000, 0.4502301000", \ - "0.0188032000, 0.0204012000, 0.0249929000, 0.0376051000, 0.0724427000, 0.1707357000, 0.4499446000", \ - "0.0186088000, 0.0201788000, 0.0247562000, 0.0372113000, 0.0720209000, 0.1703284000, 0.4498761000", \ - "0.0191479000, 0.0206485000, 0.0250575000, 0.0370384000, 0.0715929000, 0.1695797000, 0.4490430000", \ - "0.0194128000, 0.0208818000, 0.0251043000, 0.0373727000, 0.0719450000, 0.1701237000, 0.4480394000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0161945000, 0.0150737000, 0.0121250000, 0.0020583000, -0.031179400, -0.129745000, -0.411729200", \ - "0.0160548000, 0.0150232000, 0.0119981000, 0.0019545000, -0.031271500, -0.129854100, -0.411840400", \ - "0.0159307000, 0.0147863000, 0.0118435000, 0.0017817000, -0.031439200, -0.129992500, -0.411969500", \ - "0.0155966000, 0.0144889000, 0.0114874000, 0.0013993000, -0.031792200, -0.130303000, -0.412256300", \ - "0.0154120000, 0.0142793000, 0.0111034000, 0.0009264000, -0.032243600, -0.130657400, -0.412550600", \ - "0.0181567000, 0.0166300000, 0.0123977000, 0.0003686000, -0.032254100, -0.130361200, -0.412233500", \ - "0.0209164000, 0.0192923000, 0.0148283000, 0.0026048000, -0.031854500, -0.130234800, -0.411753200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0207273000, 0.0222930000, 0.0267854000, 0.0393149000, 0.0736874000, 0.1711900000, 0.4512097000", \ - "0.0206489000, 0.0222139000, 0.0267051000, 0.0392360000, 0.0736174000, 0.1711512000, 0.4511617000", \ - "0.0205282000, 0.0221456000, 0.0265936000, 0.0390307000, 0.0734566000, 0.1712707000, 0.4501237000", \ - "0.0202393000, 0.0218214000, 0.0263538000, 0.0388121000, 0.0732673000, 0.1710413000, 0.4495122000", \ - "0.0200539000, 0.0216084000, 0.0262553000, 0.0385157000, 0.0729386000, 0.1707919000, 0.4492128000", \ - "0.0208031000, 0.0222874000, 0.0265459000, 0.0384895000, 0.0729014000, 0.1704492000, 0.4498753000", \ - "0.0215444000, 0.0229907000, 0.0272086000, 0.0393890000, 0.0736910000, 0.1715602000, 0.4488451000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0135709000, 0.0125178000, 0.0095631000, -0.000550300, -0.033974000, -0.132661000, -0.414719800", \ - "0.0134168000, 0.0123913000, 0.0094771000, -0.000635600, -0.034082400, -0.132773600, -0.414834300", \ - "0.0132071000, 0.0121021000, 0.0091988000, -0.000952800, -0.034363500, -0.133037300, -0.415102600", \ - "0.0128871000, 0.0118164000, 0.0087940000, -0.001389100, -0.034750100, -0.133345900, -0.415383000", \ - "0.0125781000, 0.0113979000, 0.0081700000, -0.001816000, -0.035091600, -0.133618100, -0.415619600", \ - "0.0160182000, 0.0145028000, 0.0102819000, -0.001339800, -0.034915100, -0.133310800, -0.415233700", \ - "0.0184634000, 0.0168132000, 0.0123874000, 0.0002190000, -0.034163200, -0.132731600, -0.414113500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014252820, 0.0040628580, 0.0115814400, 0.0330136300, 0.0941074800, 0.2682594000"); - values("0.0205911000, 0.0221754000, 0.0266967000, 0.0390866000, 0.0735621000, 0.1713328000, 0.4499288000", \ - "0.0204752000, 0.0220730000, 0.0265567000, 0.0389789000, 0.0734881000, 0.1712516000, 0.4498835000", \ - "0.0203101000, 0.0219114000, 0.0263910000, 0.0388195000, 0.0733354000, 0.1714167000, 0.4503846000", \ - "0.0199864000, 0.0216047000, 0.0261248000, 0.0385786000, 0.0730883000, 0.1711884000, 0.4501616000", \ - "0.0198649000, 0.0214391000, 0.0259300000, 0.0382303000, 0.0727396000, 0.1708397000, 0.4493742000", \ - "0.0209021000, 0.0223680000, 0.0265677000, 0.0385309000, 0.0727861000, 0.1706617000, 0.4494409000", \ - "0.0222928000, 0.0237169000, 0.0278835000, 0.0398780000, 0.0742369000, 0.1720758000, 0.4486706000"); - } - } - max_capacitance : 0.2682590000; - max_transition : 1.5034830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.2217476000, 0.2282682000, 0.2424470000, 0.2699399000, 0.3229881000, 0.4343484000, 0.7163563000", \ - "0.2269902000, 0.2335282000, 0.2476158000, 0.2754842000, 0.3279919000, 0.4396631000, 0.7217086000", \ - "0.2398739000, 0.2463467000, 0.2606099000, 0.2883573000, 0.3413636000, 0.4524823000, 0.7348405000", \ - "0.2674625000, 0.2739511000, 0.2881649000, 0.3159080000, 0.3685674000, 0.4803163000, 0.7624015000", \ - "0.3304078000, 0.3368981000, 0.3510892000, 0.3788085000, 0.4319533000, 0.5438224000, 0.8260381000", \ - "0.4665963000, 0.4735384000, 0.4885820000, 0.5176678000, 0.5720827000, 0.6843122000, 0.9669453000", \ - "0.7086574000, 0.7164581000, 0.7351398000, 0.7689860000, 0.8305676000, 0.9502863000, 1.2360846000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.1400998000, 0.1471940000, 0.1633919000, 0.1991827000, 0.2838346000, 0.5126372000, 1.1648074000", \ - "0.1444461000, 0.1514705000, 0.1677211000, 0.2034326000, 0.2881635000, 0.5169596000, 1.1692172000", \ - "0.1526532000, 0.1597118000, 0.1759016000, 0.2116820000, 0.2963549000, 0.5257041000, 1.1765691000", \ - "0.1684004000, 0.1754920000, 0.1916555000, 0.2275152000, 0.3120928000, 0.5415146000, 1.1924559000", \ - "0.1994343000, 0.2068327000, 0.2233519000, 0.2595235000, 0.3446945000, 0.5741557000, 1.2263733000", \ - "0.2469966000, 0.2550327000, 0.2731658000, 0.3115552000, 0.3983138000, 0.6285029000, 1.2821727000", \ - "0.2941601000, 0.3042007000, 0.3263464000, 0.3694535000, 0.4603749000, 0.6912191000, 1.3422178000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0326750000, 0.0365375000, 0.0448780000, 0.0642812000, 0.1083526000, 0.2272046000, 0.5876584000", \ - "0.0328144000, 0.0365571000, 0.0457328000, 0.0638011000, 0.1087130000, 0.2271620000, 0.5872309000", \ - "0.0327128000, 0.0365076000, 0.0454638000, 0.0637982000, 0.1084777000, 0.2276064000, 0.5887358000", \ - "0.0327384000, 0.0366309000, 0.0454824000, 0.0641079000, 0.1083288000, 0.2272802000, 0.5875107000", \ - "0.0327159000, 0.0365473000, 0.0449322000, 0.0642802000, 0.1081373000, 0.2270107000, 0.5889051000", \ - "0.0367934000, 0.0408468000, 0.0490427000, 0.0672237000, 0.1106889000, 0.2283918000, 0.5889331000", \ - "0.0481034000, 0.0528104000, 0.0619106000, 0.0817882000, 0.1256527000, 0.2408541000, 0.5905810000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0286341000, 0.0345938000, 0.0494951000, 0.0885087000, 0.2012489000, 0.5357352000, 1.4983127000", \ - "0.0290166000, 0.0347850000, 0.0496076000, 0.0884744000, 0.2010516000, 0.5360072000, 1.4962147000", \ - "0.0288330000, 0.0346525000, 0.0493419000, 0.0886661000, 0.2013173000, 0.5361016000, 1.5008013000", \ - "0.0286267000, 0.0344805000, 0.0494782000, 0.0886053000, 0.2007953000, 0.5357091000, 1.5008089000", \ - "0.0302409000, 0.0359324000, 0.0508634000, 0.0894237000, 0.2014520000, 0.5359609000, 1.4960613000", \ - "0.0347287000, 0.0406867000, 0.0559143000, 0.0938969000, 0.2043413000, 0.5366571000, 1.4977568000", \ - "0.0453319000, 0.0523643000, 0.0686436000, 0.1050942000, 0.2100780000, 0.5383199000, 1.4983301000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.2047710000, 0.2112231000, 0.2255051000, 0.2532043000, 0.3057636000, 0.4175967000, 0.6997858000", \ - "0.2086536000, 0.2150848000, 0.2293222000, 0.2570684000, 0.3101867000, 0.4211556000, 0.7037737000", \ - "0.2195150000, 0.2260256000, 0.2402213000, 0.2680728000, 0.3211435000, 0.4324662000, 0.7148968000", \ - "0.2475761000, 0.2540477000, 0.2686607000, 0.2964139000, 0.3492241000, 0.4610873000, 0.7432378000", \ - "0.3161310000, 0.3225546000, 0.3369391000, 0.3646137000, 0.4177983000, 0.5297824000, 0.8117020000", \ - "0.4678048000, 0.4749286000, 0.4899670000, 0.5193615000, 0.5735862000, 0.6862558000, 0.9688991000", \ - "0.7192373000, 0.7287616000, 0.7489752000, 0.7866334000, 0.8504745000, 0.9699667000, 1.2551555000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.1283099000, 0.1353827000, 0.1515413000, 0.1877149000, 0.2731868000, 0.5039706000, 1.1549183000", \ - "0.1330931000, 0.1401428000, 0.1564359000, 0.1924536000, 0.2779429000, 0.5081268000, 1.1589808000", \ - "0.1417956000, 0.1488411000, 0.1651206000, 0.2011890000, 0.2866083000, 0.5168303000, 1.1699237000", \ - "0.1582292000, 0.1652648000, 0.1815703000, 0.2175699000, 0.3031197000, 0.5332215000, 1.1904698000", \ - "0.1900733000, 0.1974263000, 0.2143236000, 0.2507381000, 0.3365604000, 0.5677869000, 1.2204860000", \ - "0.2381084000, 0.2463841000, 0.2647448000, 0.3035762000, 0.3911491000, 0.6218137000, 1.2771063000", \ - "0.2840032000, 0.2945200000, 0.3175496000, 0.3628781000, 0.4538195000, 0.6857303000, 1.3366943000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0327751000, 0.0368597000, 0.0455501000, 0.0638042000, 0.1084341000, 0.2271194000, 0.5862724000", \ - "0.0326509000, 0.0363962000, 0.0452578000, 0.0635898000, 0.1081503000, 0.2278029000, 0.5906549000", \ - "0.0325842000, 0.0364959000, 0.0455848000, 0.0637790000, 0.1084382000, 0.2274885000, 0.5885482000", \ - "0.0327315000, 0.0364988000, 0.0453445000, 0.0638819000, 0.1081682000, 0.2271428000, 0.5876461000", \ - "0.0326435000, 0.0365181000, 0.0454432000, 0.0642437000, 0.1078443000, 0.2271647000, 0.5884222000", \ - "0.0393119000, 0.0435317000, 0.0510754000, 0.0686845000, 0.1113283000, 0.2288125000, 0.5877444000", \ - "0.0575945000, 0.0621486000, 0.0723830000, 0.0912865000, 0.1301372000, 0.2410399000, 0.5914109000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0283995000, 0.0341726000, 0.0490542000, 0.0880083000, 0.2007330000, 0.5355719000, 1.4962263000", \ - "0.0283751000, 0.0341990000, 0.0490508000, 0.0878667000, 0.2006730000, 0.5349440000, 1.5009549000", \ - "0.0284884000, 0.0341677000, 0.0489308000, 0.0880004000, 0.2005008000, 0.5359593000, 1.5009518000", \ - "0.0285203000, 0.0342108000, 0.0489581000, 0.0878484000, 0.2008384000, 0.5358980000, 1.5034833000", \ - "0.0300340000, 0.0356884000, 0.0509481000, 0.0891015000, 0.2013367000, 0.5358712000, 1.5028719000", \ - "0.0351919000, 0.0412458000, 0.0568005000, 0.0944211000, 0.2042304000, 0.5360489000, 1.5029440000", \ - "0.0481918000, 0.0550393000, 0.0705626000, 0.1076180000, 0.2117427000, 0.5383716000, 1.4978135000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.1018380000, 0.1064813000, 0.1169600000, 0.1390845000, 0.1848172000, 0.2883742000, 0.5677137000", \ - "0.1072182000, 0.1118595000, 0.1224514000, 0.1447173000, 0.1902511000, 0.2938110000, 0.5731395000", \ - "0.1206461000, 0.1252397000, 0.1358345000, 0.1578638000, 0.2036646000, 0.3072131000, 0.5859488000", \ - "0.1526712000, 0.1573390000, 0.1678402000, 0.1900446000, 0.2358495000, 0.3394732000, 0.6188298000", \ - "0.2255315000, 0.2304533000, 0.2413411000, 0.2639690000, 0.3102210000, 0.4140797000, 0.6933434000", \ - "0.3495460000, 0.3559730000, 0.3703792000, 0.3983700000, 0.4511528000, 0.5575816000, 0.8366148000", \ - "0.5464369000, 0.5550985000, 0.5739510000, 0.6104870000, 0.6781312000, 0.7981211000, 1.0800107000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.1336350000, 0.1406906000, 0.1569114000, 0.1927144000, 0.2773658000, 0.5066566000, 1.1588263000", \ - "0.1379074000, 0.1449604000, 0.1611802000, 0.1969841000, 0.2816794000, 0.5110127000, 1.1632442000", \ - "0.1472223000, 0.1542890000, 0.1703885000, 0.2062718000, 0.2909932000, 0.5204940000, 1.1739897000", \ - "0.1682960000, 0.1753364000, 0.1915920000, 0.2274473000, 0.3122896000, 0.5417605000, 1.1944045000", \ - "0.2130837000, 0.2203938000, 0.2373576000, 0.2735578000, 0.3585054000, 0.5883862000, 1.2411271000", \ - "0.2820121000, 0.2903776000, 0.3085222000, 0.3468468000, 0.4337379000, 0.6639153000, 1.3167881000", \ - "0.3575689000, 0.3680369000, 0.3911945000, 0.4350424000, 0.5251287000, 0.7563881000, 1.4076866000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0192992000, 0.0222942000, 0.0303062000, 0.0489508000, 0.0926170000, 0.2139845000, 0.5807095000", \ - "0.0192346000, 0.0224173000, 0.0301736000, 0.0488924000, 0.0928653000, 0.2139938000, 0.5815756000", \ - "0.0193728000, 0.0223642000, 0.0301930000, 0.0489083000, 0.0926789000, 0.2136624000, 0.5817538000", \ - "0.0191020000, 0.0224341000, 0.0300987000, 0.0488674000, 0.0926406000, 0.2139285000, 0.5812275000", \ - "0.0217743000, 0.0248215000, 0.0322764000, 0.0502958000, 0.0933339000, 0.2140723000, 0.5818855000", \ - "0.0324971000, 0.0358568000, 0.0446357000, 0.0633242000, 0.1049811000, 0.2191938000, 0.5819891000", \ - "0.0490807000, 0.0536113000, 0.0642418000, 0.0877835000, 0.1325093000, 0.2368596000, 0.5821083000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0289077000, 0.0345871000, 0.0495546000, 0.0886339000, 0.2014164000, 0.5344811000, 1.5003573000", \ - "0.0289106000, 0.0345737000, 0.0495413000, 0.0886281000, 0.2013907000, 0.5347979000, 1.4996951000", \ - "0.0288464000, 0.0346594000, 0.0495000000, 0.0886476000, 0.2007733000, 0.5358870000, 1.4987462000", \ - "0.0289146000, 0.0345832000, 0.0494882000, 0.0885735000, 0.2013060000, 0.5362940000, 1.4952666000", \ - "0.0306632000, 0.0362139000, 0.0508095000, 0.0897861000, 0.2016051000, 0.5358067000, 1.4980946000", \ - "0.0365945000, 0.0424423000, 0.0571305000, 0.0943707000, 0.2045297000, 0.5369843000, 1.5011113000", \ - "0.0493807000, 0.0562151000, 0.0716167000, 0.1067434000, 0.2101021000, 0.5390901000, 1.4985840000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0864407000, 0.0907945000, 0.1009777000, 0.1223327000, 0.1671408000, 0.2701023000, 0.5489301000", \ - "0.0917735000, 0.0961599000, 0.1061954000, 0.1277221000, 0.1725123000, 0.2754678000, 0.5545227000", \ - "0.1048617000, 0.1092824000, 0.1192857000, 0.1408011000, 0.1856340000, 0.2885778000, 0.5675936000", \ - "0.1360201000, 0.1404135000, 0.1504279000, 0.1718947000, 0.2168177000, 0.3197873000, 0.5990013000", \ - "0.2016259000, 0.2065503000, 0.2176123000, 0.2399355000, 0.2858927000, 0.3892723000, 0.6684676000", \ - "0.3055327000, 0.3119691000, 0.3262439000, 0.3540270000, 0.4077712000, 0.5161476000, 0.7952930000", \ - "0.4653364000, 0.4736513000, 0.4923533000, 0.5288897000, 0.5971977000, 0.7179796000, 0.9988081000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.1260133000, 0.1330289000, 0.1493477000, 0.1849972000, 0.2699598000, 0.4996091000, 1.1527510000", \ - "0.1297205000, 0.1367617000, 0.1530081000, 0.1887601000, 0.2737258000, 0.5033899000, 1.1565549000", \ - "0.1389294000, 0.1459889000, 0.1622868000, 0.1979868000, 0.2828375000, 0.5129622000, 1.1648315000", \ - "0.1616331000, 0.1687317000, 0.1849237000, 0.2208255000, 0.3057914000, 0.5359861000, 1.1876921000", \ - "0.2101333000, 0.2173605000, 0.2339720000, 0.2703713000, 0.3556736000, 0.5862202000, 1.2364700000", \ - "0.2778947000, 0.2862875000, 0.3045887000, 0.3422957000, 0.4282929000, 0.6592480000, 1.3103649000", \ - "0.3490747000, 0.3598343000, 0.3830646000, 0.4270235000, 0.5164142000, 0.7460905000, 1.3984027000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0175261000, 0.0206987000, 0.0282417000, 0.0470680000, 0.0913475000, 0.2132049000, 0.5815160000", \ - "0.0174898000, 0.0207100000, 0.0283131000, 0.0470569000, 0.0911489000, 0.2127944000, 0.5815184000", \ - "0.0176164000, 0.0205505000, 0.0283560000, 0.0471513000, 0.0913183000, 0.2130705000, 0.5816056000", \ - "0.0176106000, 0.0206395000, 0.0284679000, 0.0471301000, 0.0912602000, 0.2131569000, 0.5816115000", \ - "0.0218662000, 0.0249668000, 0.0326300000, 0.0506079000, 0.0932472000, 0.2134719000, 0.5848043000", \ - "0.0322604000, 0.0362308000, 0.0447786000, 0.0648415000, 0.1064241000, 0.2193815000, 0.5837164000", \ - "0.0482516000, 0.0533701000, 0.0646008000, 0.0881289000, 0.1339900000, 0.2379103000, 0.5835695000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014252800, 0.0040628600, 0.0115814000, 0.0330136000, 0.0941075000, 0.2682590000"); - values("0.0287197000, 0.0345456000, 0.0496032000, 0.0884584000, 0.2010468000, 0.5352642000, 1.4965684000", \ - "0.0287203000, 0.0345584000, 0.0496067000, 0.0885375000, 0.2011408000, 0.5357648000, 1.4969268000", \ - "0.0288329000, 0.0346620000, 0.0494311000, 0.0886138000, 0.2008527000, 0.5361152000, 1.5006720000", \ - "0.0288207000, 0.0346987000, 0.0494345000, 0.0885632000, 0.2012933000, 0.5358691000, 1.5007401000", \ - "0.0307930000, 0.0363594000, 0.0508836000, 0.0898984000, 0.2017858000, 0.5359651000, 1.5005064000", \ - "0.0382608000, 0.0438495000, 0.0575533000, 0.0945196000, 0.2048224000, 0.5370154000, 1.5009521000", \ - "0.0525581000, 0.0589951000, 0.0735061000, 0.1085262000, 0.2100615000, 0.5384179000, 1.4995759000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211a_4") { - leakage_power () { - value : 0.0038445000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0266621000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0051182000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0040349000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0043986000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0037725000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0045757000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0047141000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0043986000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0037725000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0048331000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0047140000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0043986000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0037725000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0034708000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0047141000; - when : "A1&A2&B1&!C1"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__o211a"; - cell_leakage_power : 0.0056996750; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0048630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081188000, 0.0081014000, 0.0080613000, 0.0080617000, 0.0080626000, 0.0080648000, 0.0080698000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008052100, -0.008049700, -0.008044100, -0.008042500, -0.008038600, -0.008029800, -0.008009400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051060000; - } - pin ("A2") { - capacitance : 0.0044610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076146000, 0.0076106000, 0.0076014000, 0.0076020000, 0.0076034000, 0.0076068000, 0.0076144000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007570300, -0.007568800, -0.007565500, -0.007567100, -0.007571000, -0.007580000, -0.007600800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047840000; - } - pin ("B1") { - capacitance : 0.0049490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0047410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089587000, 0.0089267000, 0.0088528000, 0.0088677000, 0.0089022000, 0.0089816000, 0.0091648000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008602600, -0.008607300, -0.008618200, -0.008618300, -0.008618700, -0.008619700, -0.008621700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051560000; - } - pin ("C1") { - capacitance : 0.0044470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087786000, 0.0087868000, 0.0088055000, 0.0088074000, 0.0088118000, 0.0088220000, 0.0088455000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006996100, -0.006999800, -0.007008200, -0.006997100, -0.006971700, -0.006913100, -0.006777900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046150000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0403545000, 0.0386221000, 0.0337810000, 0.0192240000, -0.032360400, -0.208086800, -0.771826800", \ - "0.0400661000, 0.0383702000, 0.0332899000, 0.0187459000, -0.032514000, -0.208323600, -0.772028900", \ - "0.0397890000, 0.0381225000, 0.0329580000, 0.0184530000, -0.032999800, -0.208560500, -0.772336000", \ - "0.0394584000, 0.0377937000, 0.0326977000, 0.0182690000, -0.033325900, -0.208928600, -0.772656000", \ - "0.0391687000, 0.0374884000, 0.0323733000, 0.0177919000, -0.033805600, -0.209324900, -0.772953700", \ - "0.0388882000, 0.0370956000, 0.0319230000, 0.0174408000, -0.034265200, -0.209722900, -0.773215000", \ - "0.0483455000, 0.0463830000, 0.0404291000, 0.0224941000, -0.033337700, -0.209545900, -0.772782300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0370410000, 0.0389005000, 0.0448476000, 0.0634282000, 0.1203252000, 0.2971230000, 0.8559693000", \ - "0.0367825000, 0.0386808000, 0.0447107000, 0.0632256000, 0.1200007000, 0.2970512000, 0.8551811000", \ - "0.0365718000, 0.0384374000, 0.0444474000, 0.0629830000, 0.1199384000, 0.2966531000, 0.8559409000", \ - "0.0360864000, 0.0379990000, 0.0439839000, 0.0626132000, 0.1193668000, 0.2965920000, 0.8584498000", \ - "0.0359287000, 0.0377789000, 0.0437988000, 0.0622034000, 0.1188157000, 0.2961554000, 0.8568808000", \ - "0.0371435000, 0.0389250000, 0.0446221000, 0.0623160000, 0.1184258000, 0.2947947000, 0.8563670000", \ - "0.0380410000, 0.0397432000, 0.0452927000, 0.0629016000, 0.1193955000, 0.2957617000, 0.8530323000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0359939000, 0.0342495000, 0.0291707000, 0.0145876000, -0.036788900, -0.212426100, -0.776119900", \ - "0.0356515000, 0.0339514000, 0.0288755000, 0.0145026000, -0.037128300, -0.212660300, -0.776332200", \ - "0.0353694000, 0.0336778000, 0.0285521000, 0.0140022000, -0.037468300, -0.213031600, -0.776739800", \ - "0.0350960000, 0.0333892000, 0.0282740000, 0.0138055000, -0.037770400, -0.213428800, -0.777070700", \ - "0.0348643000, 0.0331528000, 0.0279677000, 0.0135280000, -0.038066400, -0.213685300, -0.777290100", \ - "0.0352705000, 0.0334793000, 0.0292965000, 0.0138360000, -0.037981400, -0.213015600, -0.776649900", \ - "0.0457215000, 0.0437068000, 0.0376496000, 0.0197922000, -0.036275000, -0.212350600, -0.775403800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0338291000, 0.0357015000, 0.0416601000, 0.0603330000, 0.1171679000, 0.2942909000, 0.8526292000", \ - "0.0337862000, 0.0356723000, 0.0417248000, 0.0602549000, 0.1172064000, 0.2939488000, 0.8539640000", \ - "0.0335731000, 0.0354598000, 0.0415059000, 0.0600638000, 0.1170135000, 0.2940109000, 0.8538713000", \ - "0.0331011000, 0.0349765000, 0.0410266000, 0.0596686000, 0.1163619000, 0.2935333000, 0.8487609000", \ - "0.0326406000, 0.0345182000, 0.0405183000, 0.0588553000, 0.1157334000, 0.2925353000, 0.8492046000", \ - "0.0333469000, 0.0351349000, 0.0409040000, 0.0587935000, 0.1148817000, 0.2907815000, 0.8517842000", \ - "0.0344392000, 0.0361476000, 0.0417217000, 0.0600541000, 0.1159707000, 0.2922944000, 0.8486613000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0312223000, 0.0299077000, 0.0259624000, 0.0121427000, -0.040438600, -0.217581100, -0.782014000", \ - "0.0310057000, 0.0296984000, 0.0256957000, 0.0118885000, -0.040678600, -0.217801400, -0.782243200", \ - "0.0305765000, 0.0292916000, 0.0253310000, 0.0115813000, -0.040995800, -0.218119100, -0.782539200", \ - "0.0299512000, 0.0286042000, 0.0246124000, 0.0107572000, -0.041737900, -0.218715500, -0.783069900", \ - "0.0297256000, 0.0282533000, 0.0241362000, 0.0105253000, -0.042072800, -0.218922400, -0.783217900", \ - "0.0336053000, 0.0318169000, 0.0260396000, 0.0086997000, -0.042428700, -0.218924100, -0.783015800", \ - "0.0403913000, 0.0384099000, 0.0325173000, 0.0146618000, -0.041123800, -0.217976300, -0.781664300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0379152000, 0.0398029000, 0.0458036000, 0.0643951000, 0.1211690000, 0.2982370000, 0.8556372000", \ - "0.0378216000, 0.0397032000, 0.0457293000, 0.0642273000, 0.1211595000, 0.2981242000, 0.8576962000", \ - "0.0374362000, 0.0393383000, 0.0453729000, 0.0639731000, 0.1208270000, 0.2980359000, 0.8588988000", \ - "0.0370040000, 0.0388498000, 0.0448968000, 0.0635120000, 0.1202070000, 0.2975978000, 0.8563385000", \ - "0.0367901000, 0.0386101000, 0.0445570000, 0.0627523000, 0.1193672000, 0.2964493000, 0.8559105000", \ - "0.0376589000, 0.0394494000, 0.0450969000, 0.0626817000, 0.1190063000, 0.2953828000, 0.8542286000", \ - "0.0391872000, 0.0408724000, 0.0463049000, 0.0638915000, 0.1202447000, 0.2970800000, 0.8523415000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0249713000, 0.0236042000, 0.0198581000, 0.0064441000, -0.045576400, -0.222452900, -0.786896800", \ - "0.0247918000, 0.0234043000, 0.0196145000, 0.0062196000, -0.045779500, -0.222657500, -0.787107800", \ - "0.0243416000, 0.0229562000, 0.0191641000, 0.0056582000, -0.046288600, -0.223137600, -0.787581500", \ - "0.0236930000, 0.0222610000, 0.0184253000, 0.0048707000, -0.047090100, -0.223791700, -0.788159200", \ - "0.0235394000, 0.0220436000, 0.0183422000, 0.0041780000, -0.047715000, -0.223965700, -0.788270300", \ - "0.0278592000, 0.0260478000, 0.0203875000, 0.0032239000, -0.047846400, -0.223980600, -0.787969300", \ - "0.0351631000, 0.0331786000, 0.0272856000, 0.0094311000, -0.046157800, -0.222761000, -0.786260400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015858690, 0.0050299640, 0.0159537300, 0.0506010700, 0.1604934000, 0.5090431000"); - values("0.0365837000, 0.0384314000, 0.0444590000, 0.0629609000, 0.1198988000, 0.2967689000, 0.8565507000", \ - "0.0364539000, 0.0383204000, 0.0443393000, 0.0628291000, 0.1196708000, 0.2969240000, 0.8561108000", \ - "0.0360861000, 0.0379732000, 0.0439255000, 0.0626250000, 0.1193965000, 0.2965680000, 0.8585553000", \ - "0.0356603000, 0.0375578000, 0.0435635000, 0.0621549000, 0.1188436000, 0.2961493000, 0.8554442000", \ - "0.0357740000, 0.0374352000, 0.0432341000, 0.0612232000, 0.1178458000, 0.2953191000, 0.8564819000", \ - "0.0366481000, 0.0384019000, 0.0440495000, 0.0616383000, 0.1174631000, 0.2937713000, 0.8537200000", \ - "0.0389917000, 0.0406929000, 0.0462083000, 0.0636019000, 0.1195778000, 0.2959787000, 0.8527548000"); - } - } - max_capacitance : 0.5090430000; - max_transition : 1.5050520000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.2127835000, 0.2170772000, 0.2279269000, 0.2518614000, 0.3010265000, 0.4111745000, 0.7165624000", \ - "0.2178994000, 0.2221897000, 0.2331205000, 0.2571673000, 0.3058178000, 0.4163616000, 0.7217793000", \ - "0.2305002000, 0.2347938000, 0.2457309000, 0.2697542000, 0.3190568000, 0.4290036000, 0.7343355000", \ - "0.2576417000, 0.2619693000, 0.2729174000, 0.2967578000, 0.3458853000, 0.4562179000, 0.7616271000", \ - "0.3184256000, 0.3227338000, 0.3336883000, 0.3575954000, 0.4069580000, 0.5172888000, 0.8226964000", \ - "0.4473981000, 0.4520390000, 0.4637776000, 0.4891834000, 0.5402385000, 0.6519204000, 0.9572518000", \ - "0.6728384000, 0.6784291000, 0.6926074000, 0.7226290000, 0.7806354000, 0.8997627000, 1.2086433000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1257112000, 0.1302431000, 0.1422445000, 0.1718437000, 0.2480020000, 0.4728346000, 1.1794451000", \ - "0.1299950000, 0.1345384000, 0.1465840000, 0.1762516000, 0.2521764000, 0.4777512000, 1.1859159000", \ - "0.1388509000, 0.1433954000, 0.1554314000, 0.1849914000, 0.2611460000, 0.4856439000, 1.1928725000", \ - "0.1559841000, 0.1605086000, 0.1725707000, 0.2022388000, 0.2783036000, 0.5039332000, 1.2107123000", \ - "0.1889314000, 0.1936326000, 0.2060900000, 0.2362466000, 0.3126871000, 0.5381121000, 1.2435530000", \ - "0.2377828000, 0.2431090000, 0.2567529000, 0.2888497000, 0.3669232000, 0.5920344000, 1.2998861000", \ - "0.2818327000, 0.2886784000, 0.3060623000, 0.3432155000, 0.4260119000, 0.6521261000, 1.3578854000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0308254000, 0.0333251000, 0.0400450000, 0.0555127000, 0.0955248000, 0.2149574000, 0.6141182000", \ - "0.0308827000, 0.0334292000, 0.0400886000, 0.0557874000, 0.0962980000, 0.2148122000, 0.6133549000", \ - "0.0309172000, 0.0334545000, 0.0395824000, 0.0556430000, 0.0955523000, 0.2147633000, 0.6139337000", \ - "0.0309373000, 0.0333968000, 0.0399685000, 0.0555195000, 0.0960888000, 0.2155196000, 0.6126441000", \ - "0.0308715000, 0.0333394000, 0.0399334000, 0.0552637000, 0.0957617000, 0.2149654000, 0.6147712000", \ - "0.0351997000, 0.0379437000, 0.0441658000, 0.0597680000, 0.0987484000, 0.2165792000, 0.6127236000", \ - "0.0471704000, 0.0494986000, 0.0567373000, 0.0732942000, 0.1136800000, 0.2283399000, 0.6157219000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0258615000, 0.0295180000, 0.0401823000, 0.0703907000, 0.1661379000, 0.4834680000, 1.5013885000", \ - "0.0260334000, 0.0296890000, 0.0399249000, 0.0704866000, 0.1664281000, 0.4833764000, 1.5030428000", \ - "0.0259343000, 0.0295698000, 0.0400982000, 0.0703726000, 0.1664507000, 0.4840660000, 1.5018345000", \ - "0.0259406000, 0.0295163000, 0.0400738000, 0.0702120000, 0.1665220000, 0.4842485000, 1.5021990000", \ - "0.0276287000, 0.0313835000, 0.0416944000, 0.0715710000, 0.1668616000, 0.4852433000, 1.4972248000", \ - "0.0322227000, 0.0359205000, 0.0470240000, 0.0764582000, 0.1696003000, 0.4839585000, 1.4990992000", \ - "0.0443072000, 0.0481261000, 0.0597901000, 0.0891782000, 0.1765972000, 0.4856144000, 1.4982044000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1960775000, 0.2003949000, 0.2113038000, 0.2352598000, 0.2846157000, 0.3943906000, 0.6997021000", \ - "0.1999004000, 0.2042136000, 0.2151410000, 0.2389393000, 0.2882940000, 0.3982427000, 0.7036733000", \ - "0.2109037000, 0.2151925000, 0.2261663000, 0.2500851000, 0.2993739000, 0.4094045000, 0.7148155000", \ - "0.2386236000, 0.2429228000, 0.2538592000, 0.2773647000, 0.3264553000, 0.4367380000, 0.7418264000", \ - "0.3075390000, 0.3117969000, 0.3227375000, 0.3467906000, 0.3960529000, 0.5064545000, 0.8117619000", \ - "0.4570181000, 0.4618290000, 0.4739962000, 0.4997376000, 0.5504772000, 0.6605255000, 0.9661528000", \ - "0.7051297000, 0.7114333000, 0.7272878000, 0.7606995000, 0.8204600000, 0.9384917000, 1.2473471000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1160347000, 0.1206003000, 0.1327159000, 0.1627151000, 0.2390165000, 0.4640734000, 1.1682955000", \ - "0.1206859000, 0.1252639000, 0.1374677000, 0.1673959000, 0.2437931000, 0.4683173000, 1.1767322000", \ - "0.1291156000, 0.1336905000, 0.1458885000, 0.1758308000, 0.2522006000, 0.4770079000, 1.1872188000", \ - "0.1447989000, 0.1493542000, 0.1615655000, 0.1914758000, 0.2676053000, 0.4922047000, 1.1991912000", \ - "0.1729701000, 0.1777736000, 0.1904509000, 0.2211401000, 0.2980405000, 0.5224303000, 1.2362832000", \ - "0.2115015000, 0.2169655000, 0.2311383000, 0.2640457000, 0.3428061000, 0.5679976000, 1.2783367000", \ - "0.2355663000, 0.2426343000, 0.2606738000, 0.2999790000, 0.3837570000, 0.6099440000, 1.3157231000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0309152000, 0.0333297000, 0.0398072000, 0.0551718000, 0.0958352000, 0.2154041000, 0.6124632000", \ - "0.0308558000, 0.0333859000, 0.0399925000, 0.0555327000, 0.0955361000, 0.2149668000, 0.6130446000", \ - "0.0308869000, 0.0334215000, 0.0400127000, 0.0556066000, 0.0956197000, 0.2148059000, 0.6143188000", \ - "0.0309429000, 0.0334784000, 0.0401575000, 0.0556861000, 0.0962040000, 0.2151990000, 0.6122905000", \ - "0.0311472000, 0.0333115000, 0.0399815000, 0.0555306000, 0.0961271000, 0.2148602000, 0.6143033000", \ - "0.0378776000, 0.0399819000, 0.0464903000, 0.0609804000, 0.0992566000, 0.2169779000, 0.6141138000", \ - "0.0553973000, 0.0587189000, 0.0662982000, 0.0821370000, 0.1187608000, 0.2286460000, 0.6162427000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0260244000, 0.0297029000, 0.0402790000, 0.0705339000, 0.1665887000, 0.4838147000, 1.5007506000", \ - "0.0259430000, 0.0295999000, 0.0400882000, 0.0706783000, 0.1662239000, 0.4841884000, 1.5050521000", \ - "0.0259302000, 0.0295937000, 0.0400899000, 0.0707393000, 0.1663202000, 0.4849453000, 1.5022732000", \ - "0.0260312000, 0.0297282000, 0.0401469000, 0.0706903000, 0.1662256000, 0.4835808000, 1.4996491000", \ - "0.0280105000, 0.0318398000, 0.0423816000, 0.0722943000, 0.1670050000, 0.4835492000, 1.5010517000", \ - "0.0334566000, 0.0373518000, 0.0485127000, 0.0778252000, 0.1705750000, 0.4828487000, 1.5010259000", \ - "0.0464091000, 0.0511091000, 0.0624177000, 0.0920719000, 0.1786106000, 0.4862376000, 1.4972166000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1077575000, 0.1109628000, 0.1193560000, 0.1390643000, 0.1832240000, 0.2877767000, 0.5895326000", \ - "0.1129685000, 0.1161664000, 0.1244883000, 0.1442921000, 0.1884842000, 0.2930837000, 0.5954834000", \ - "0.1262440000, 0.1294453000, 0.1377705000, 0.1574510000, 0.2018199000, 0.3064313000, 0.6082357000", \ - "0.1581160000, 0.1613418000, 0.1697044000, 0.1893163000, 0.2337554000, 0.3384245000, 0.6402978000", \ - "0.2317303000, 0.2350859000, 0.2440750000, 0.2635669000, 0.3083039000, 0.4132764000, 0.7154198000", \ - "0.3614565000, 0.3658740000, 0.3772701000, 0.4019036000, 0.4529674000, 0.5625356000, 0.8653102000", \ - "0.5716171000, 0.5774727000, 0.5921631000, 0.6249219000, 0.6900595000, 0.8133763000, 1.1190853000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1198430000, 0.1243628000, 0.1364522000, 0.1660392000, 0.2421403000, 0.4673922000, 1.1720130000", \ - "0.1239242000, 0.1284613000, 0.1405105000, 0.1701198000, 0.2462681000, 0.4706613000, 1.1777216000", \ - "0.1327500000, 0.1372627000, 0.1493811000, 0.1789869000, 0.2551284000, 0.4804828000, 1.1868749000", \ - "0.1531546000, 0.1576441000, 0.1696761000, 0.1993464000, 0.2752184000, 0.5003579000, 1.2063552000", \ - "0.1935249000, 0.1982780000, 0.2107160000, 0.2410764000, 0.3174246000, 0.5419802000, 1.2496589000", \ - "0.2490874000, 0.2545678000, 0.2684721000, 0.3002585000, 0.3781337000, 0.6040009000, 1.3112685000", \ - "0.2976234000, 0.3045710000, 0.3219320000, 0.3596216000, 0.4411113000, 0.6668358000, 1.3739230000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0194788000, 0.0216078000, 0.0276816000, 0.0440361000, 0.0862116000, 0.2058476000, 0.6084135000", \ - "0.0195772000, 0.0216691000, 0.0279614000, 0.0439529000, 0.0860718000, 0.2059048000, 0.6104481000", \ - "0.0196989000, 0.0216005000, 0.0276377000, 0.0441740000, 0.0860304000, 0.2059957000, 0.6080347000", \ - "0.0196221000, 0.0218057000, 0.0276806000, 0.0439832000, 0.0861203000, 0.2060275000, 0.6080190000", \ - "0.0218460000, 0.0237858000, 0.0295236000, 0.0454706000, 0.0869180000, 0.2061900000, 0.6088096000", \ - "0.0324863000, 0.0351136000, 0.0413010000, 0.0574657000, 0.0978745000, 0.2114955000, 0.6093842000", \ - "0.0493809000, 0.0528117000, 0.0607471000, 0.0802166000, 0.1246517000, 0.2306024000, 0.6118449000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0258601000, 0.0295149000, 0.0401899000, 0.0703032000, 0.1665345000, 0.4850577000, 1.4986771000", \ - "0.0259068000, 0.0295533000, 0.0399735000, 0.0703315000, 0.1664690000, 0.4842694000, 1.5018460000", \ - "0.0259852000, 0.0295624000, 0.0401773000, 0.0703106000, 0.1664456000, 0.4849738000, 1.5001391000", \ - "0.0259544000, 0.0295053000, 0.0399872000, 0.0704247000, 0.1662943000, 0.4841825000, 1.5013142000", \ - "0.0277782000, 0.0316594000, 0.0421932000, 0.0720855000, 0.1671525000, 0.4842147000, 1.5017465000", \ - "0.0338240000, 0.0375287000, 0.0475274000, 0.0768484000, 0.1701504000, 0.4849304000, 1.4999538000", \ - "0.0463618000, 0.0507206000, 0.0617270000, 0.0891185000, 0.1759793000, 0.4862371000, 1.4984232000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1055886000, 0.1089676000, 0.1177464000, 0.1382948000, 0.1843797000, 0.2909691000, 0.5937917000", \ - "0.1108617000, 0.1142001000, 0.1230012000, 0.1435706000, 0.1896689000, 0.2962615000, 0.5990874000", \ - "0.1235968000, 0.1269186000, 0.1357066000, 0.1561264000, 0.2022432000, 0.3089010000, 0.6116936000", \ - "0.1549366000, 0.1582428000, 0.1669827000, 0.1875067000, 0.2336513000, 0.3403613000, 0.6427672000", \ - "0.2266898000, 0.2302187000, 0.2394379000, 0.2602054000, 0.3067953000, 0.4130500000, 0.7158622000", \ - "0.3506486000, 0.3551796000, 0.3669176000, 0.3928486000, 0.4465850000, 0.5587482000, 0.8619659000", \ - "0.5525678000, 0.5583263000, 0.5732799000, 0.6068919000, 0.6751981000, 0.8027914000, 1.1100652000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.1105377000, 0.1150514000, 0.1271036000, 0.1566764000, 0.2328673000, 0.4574831000, 1.1639729000", \ - "0.1143064000, 0.1188591000, 0.1308437000, 0.1604515000, 0.2365292000, 0.4613690000, 1.1672402000", \ - "0.1230777000, 0.1276208000, 0.1396807000, 0.1693672000, 0.2454550000, 0.4710738000, 1.1780397000", \ - "0.1452756000, 0.1498721000, 0.1618442000, 0.1914432000, 0.2672991000, 0.4924087000, 1.1985474000", \ - "0.1869516000, 0.1915845000, 0.2038095000, 0.2338497000, 0.3103814000, 0.5356312000, 1.2412859000", \ - "0.2380171000, 0.2434443000, 0.2571535000, 0.2883928000, 0.3655966000, 0.5915233000, 1.3014881000", \ - "0.2741641000, 0.2812389000, 0.2988069000, 0.3361699000, 0.4160994000, 0.6405972000, 1.3480529000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0203402000, 0.0226476000, 0.0288216000, 0.0458513000, 0.0886716000, 0.2083072000, 0.6107899000", \ - "0.0201841000, 0.0224808000, 0.0288055000, 0.0458489000, 0.0886854000, 0.2082791000, 0.6108108000", \ - "0.0204566000, 0.0226109000, 0.0287794000, 0.0459037000, 0.0886589000, 0.2082752000, 0.6100634000", \ - "0.0201974000, 0.0226306000, 0.0289825000, 0.0457962000, 0.0887488000, 0.2084227000, 0.6080976000", \ - "0.0230698000, 0.0252297000, 0.0311893000, 0.0473469000, 0.0896107000, 0.2087765000, 0.6097878000", \ - "0.0338558000, 0.0366770000, 0.0440286000, 0.0608004000, 0.1022975000, 0.2151209000, 0.6110019000", \ - "0.0509873000, 0.0544625000, 0.0635245000, 0.0846204000, 0.1310825000, 0.2368594000, 0.6133961000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015858700, 0.0050299600, 0.0159537000, 0.0506011000, 0.1604930000, 0.5090430000"); - values("0.0259350000, 0.0296271000, 0.0399939000, 0.0703697000, 0.1663318000, 0.4841771000, 1.5016919000", \ - "0.0259302000, 0.0295801000, 0.0399726000, 0.0703176000, 0.1663806000, 0.4838279000, 1.4991246000", \ - "0.0258877000, 0.0295133000, 0.0400251000, 0.0702997000, 0.1665173000, 0.4844901000, 1.5023199000", \ - "0.0258720000, 0.0295655000, 0.0399447000, 0.0704319000, 0.1662095000, 0.4843828000, 1.4996422000", \ - "0.0277761000, 0.0314069000, 0.0418012000, 0.0720644000, 0.1671423000, 0.4854874000, 1.4980476000", \ - "0.0349739000, 0.0382258000, 0.0482231000, 0.0765758000, 0.1700954000, 0.4849907000, 1.5038295000", \ - "0.0486782000, 0.0530496000, 0.0636629000, 0.0903155000, 0.1760718000, 0.4870440000, 1.4994752000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211ai_1") { - leakage_power () { - value : 7.4987779e-05; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 8.8724194e-05; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0006068000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 7.0753089e-05; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0003833000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 4.8189554e-05; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0027003000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0004553000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0003833000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 4.8189554e-05; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0031689000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0004553000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0003833000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 4.8189554e-05; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0018754000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0004553000; - when : "A1&A2&B1&!C1"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__o211ai"; - cell_leakage_power : 0.0007028808; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039649000, 0.0039654000, 0.0039664000, 0.0039663000, 0.0039658000, 0.0039648000, 0.0039624000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003960700, -0.003960300, -0.003959400, -0.003958400, -0.003956100, -0.003950900, -0.003938800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024500000; - } - pin ("A2") { - capacitance : 0.0023310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038776000, 0.0038692000, 0.0038497000, 0.0038502000, 0.0038515000, 0.0038544000, 0.0038611000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003858500, -0.003855200, -0.003847600, -0.003847000, -0.003845600, -0.003842500, -0.003835100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024860000; - } - pin ("B1") { - capacitance : 0.0023400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041206000, 0.0041055000, 0.0040705000, 0.0040777000, 0.0040943000, 0.0041325000, 0.0042205000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003948600, -0.003946900, -0.003942800, -0.003940000, -0.003933500, -0.003918500, -0.003884000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024210000; - } - pin ("C1") { - capacitance : 0.0023590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048043000, 0.0048026000, 0.0047987000, 0.0048001000, 0.0048032000, 0.0048103000, 0.0048268000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003963000, -0.003965200, -0.003970200, -0.003964400, -0.003951200, -0.003920700, -0.003850300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0072172000, 0.0061723000, 0.0037672000, -0.001792600, -0.014594700, -0.044066400, -0.111953100", \ - "0.0071045000, 0.0060667000, 0.0036642000, -0.001879600, -0.014671100, -0.044152300, -0.112022700", \ - "0.0069730000, 0.0059414000, 0.0035466000, -0.001986000, -0.014756800, -0.044220800, -0.112102700", \ - "0.0067949000, 0.0057612000, 0.0033818000, -0.002115500, -0.014853500, -0.044287100, -0.112144100", \ - "0.0066629000, 0.0056265000, 0.0032511000, -0.002230500, -0.014929900, -0.044325700, -0.112145600", \ - "0.0067321000, 0.0056652000, 0.0032607000, -0.002272500, -0.015119000, -0.044454900, -0.112255900", \ - "0.0072383000, 0.0061758000, 0.0037249000, -0.001896200, -0.014777900, -0.044410500, -0.112224400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0147845000, 0.0158461000, 0.0182722000, 0.0238550000, 0.0366242000, 0.0658389000, 0.1328937000", \ - "0.0146570000, 0.0157277000, 0.0181738000, 0.0237610000, 0.0365366000, 0.0658431000, 0.1330247000", \ - "0.0145057000, 0.0155763000, 0.0180206000, 0.0236353000, 0.0364406000, 0.0656862000, 0.1328242000", \ - "0.0143415000, 0.0154164000, 0.0178776000, 0.0235045000, 0.0363187000, 0.0656103000, 0.1327391000", \ - "0.0142732000, 0.0153353000, 0.0177999000, 0.0233978000, 0.0361792000, 0.0655020000, 0.1327899000", \ - "0.0142141000, 0.0152546000, 0.0177500000, 0.0233597000, 0.0362610000, 0.0655696000, 0.1326601000", \ - "0.0146058000, 0.0156289000, 0.0179596000, 0.0235017000, 0.0364811000, 0.0657581000, 0.1328563000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0059053000, 0.0048617000, 0.0024816000, -0.003068600, -0.015890900, -0.045403300, -0.113323900", \ - "0.0058224000, 0.0048068000, 0.0024275000, -0.003084600, -0.015861300, -0.045353600, -0.113250700", \ - "0.0056082000, 0.0046088000, 0.0022847000, -0.003180100, -0.015902400, -0.045355400, -0.113242800", \ - "0.0053019000, 0.0043162000, 0.0020003000, -0.003398700, -0.016042600, -0.045421300, -0.113266500", \ - "0.0051801000, 0.0040904000, 0.0017298000, -0.003655500, -0.016272400, -0.045556700, -0.113316400", \ - "0.0050802000, 0.0040540000, 0.0016677000, -0.003840800, -0.016582300, -0.045822000, -0.113505600", \ - "0.0056518000, 0.0045436000, 0.0020667000, -0.003554100, -0.016418200, -0.045937000, -0.113633800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0126180000, 0.0136515000, 0.0160885000, 0.0216788000, 0.0344594000, 0.0637723000, 0.1306976000", \ - "0.0124016000, 0.0134763000, 0.0159407000, 0.0215729000, 0.0343233000, 0.0636813000, 0.1306807000", \ - "0.0122437000, 0.0132936000, 0.0157741000, 0.0214210000, 0.0342774000, 0.0635289000, 0.1307568000", \ - "0.0119871000, 0.0130372000, 0.0154975000, 0.0212069000, 0.0340704000, 0.0634601000, 0.1305400000", \ - "0.0121765000, 0.0132501000, 0.0156746000, 0.0212712000, 0.0338457000, 0.0632087000, 0.1304983000", \ - "0.0128561000, 0.0139230000, 0.0161886000, 0.0212924000, 0.0342411000, 0.0634505000, 0.1300971000", \ - "0.0135811000, 0.0145267000, 0.0168748000, 0.0224780000, 0.0351553000, 0.0644531000, 0.1307485000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0075118000, 0.0064697000, 0.0040813000, -0.001453200, -0.014240400, -0.043725200, -0.111617000", \ - "0.0074056000, 0.0063869000, 0.0040038000, -0.001506500, -0.014264100, -0.043730800, -0.111604000", \ - "0.0072387000, 0.0062223000, 0.0038649000, -0.001619800, -0.014338500, -0.043764300, -0.111595100", \ - "0.0069983000, 0.0059908000, 0.0036393000, -0.001814200, -0.014477100, -0.043854300, -0.111675200", \ - "0.0068525000, 0.0058228000, 0.0034437000, -0.002005400, -0.014643200, -0.044017300, -0.111751900", \ - "0.0069456000, 0.0058851000, 0.0034772000, -0.002090100, -0.014882800, -0.044196100, -0.111848900", \ - "0.0076763000, 0.0065837000, 0.0040750000, -0.001608600, -0.014530900, -0.044186700, -0.111966600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0105648000, 0.0116354000, 0.0140808000, 0.0196630000, 0.0323575000, 0.0615357000, 0.1285424000", \ - "0.0103919000, 0.0114785000, 0.0139590000, 0.0195732000, 0.0323384000, 0.0615393000, 0.1285768000", \ - "0.0101790000, 0.0112780000, 0.0136774000, 0.0193847000, 0.0322109000, 0.0614593000, 0.1285960000", \ - "0.0098858000, 0.0109703000, 0.0135314000, 0.0192150000, 0.0320696000, 0.0611281000, 0.1282186000", \ - "0.0098539000, 0.0108990000, 0.0133342000, 0.0188928000, 0.0316969000, 0.0609808000, 0.1278927000", \ - "0.0104720000, 0.0115165000, 0.0136033000, 0.0194744000, 0.0316850000, 0.0608025000, 0.1278386000", \ - "0.0113892000, 0.0123699000, 0.0146675000, 0.0199623000, 0.0325639000, 0.0616643000, 0.1287244000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0074320000, 0.0064133000, 0.0040471000, -0.001473900, -0.014237700, -0.043710300, -0.111591500", \ - "0.0072986000, 0.0062906000, 0.0039594000, -0.001534100, -0.014268900, -0.043713500, -0.111581700", \ - "0.0070834000, 0.0061113000, 0.0037710000, -0.001669000, -0.014347300, -0.043761200, -0.111591500", \ - "0.0068504000, 0.0058424000, 0.0035008000, -0.001937100, -0.014543100, -0.043861900, -0.111627400", \ - "0.0066698000, 0.0056441000, 0.0032905000, -0.002143500, -0.014773000, -0.044046700, -0.111781500", \ - "0.0072690000, 0.0059649000, 0.0035135000, -0.002147200, -0.014762800, -0.044209900, -0.111842100", \ - "0.0082805000, 0.0071620000, 0.0045895000, -0.001114200, -0.014145000, -0.043559300, -0.111321400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011503870, 0.0026467830, 0.0060896510, 0.0140109200, 0.0322359600, 0.0741676900"); - values("0.0074389000, 0.0085562000, 0.0110901000, 0.0167319000, 0.0295084000, 0.0587218000, 0.1255661000", \ - "0.0071686000, 0.0083159000, 0.0109213000, 0.0165884000, 0.0294261000, 0.0586772000, 0.1255376000", \ - "0.0068361000, 0.0079902000, 0.0105945000, 0.0163641000, 0.0292607000, 0.0586083000, 0.1256489000", \ - "0.0066770000, 0.0077783000, 0.0103048000, 0.0159762000, 0.0288847000, 0.0582555000, 0.1253313000", \ - "0.0067713000, 0.0078298000, 0.0101333000, 0.0157225000, 0.0285476000, 0.0579186000, 0.1248218000", \ - "0.0072696000, 0.0083166000, 0.0108877000, 0.0164356000, 0.0285202000, 0.0576553000, 0.1235530000", \ - "0.0084791000, 0.0093972000, 0.0116482000, 0.0169041000, 0.0294867000, 0.0586092000, 0.1246745000"); - } - } - max_capacitance : 0.0741680000; - max_transition : 1.4934270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0610228000, 0.0657417000, 0.0766812000, 0.1013980000, 0.1573026000, 0.2846874000, 0.5771610000", \ - "0.0654483000, 0.0702702000, 0.0811512000, 0.1058069000, 0.1617110000, 0.2893973000, 0.5815572000", \ - "0.0744520000, 0.0793001000, 0.0902885000, 0.1150677000, 0.1711031000, 0.2985716000, 0.5910539000", \ - "0.0917570000, 0.0968928000, 0.1082316000, 0.1331717000, 0.1891901000, 0.3168976000, 0.6093022000", \ - "0.1191971000, 0.1256738000, 0.1392788000, 0.1683906000, 0.2284554000, 0.3568424000, 0.6501527000", \ - "0.1520206000, 0.1616048000, 0.1818113000, 0.2225806000, 0.2984516000, 0.4447419000, 0.7420055000", \ - "0.1677513000, 0.1834365000, 0.2156007000, 0.2795535000, 0.3943539000, 0.5907804000, 0.9401153000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.1190023000, 0.1281138000, 0.1497984000, 0.1978959000, 0.3067559000, 0.5553476000, 1.1251248000", \ - "0.1241694000, 0.1338712000, 0.1550573000, 0.2030611000, 0.3125169000, 0.5609530000, 1.1307525000", \ - "0.1365339000, 0.1457781000, 0.1673729000, 0.2158644000, 0.3249786000, 0.5737978000, 1.1432665000", \ - "0.1626281000, 0.1719436000, 0.1934173000, 0.2418134000, 0.3511986000, 0.6002832000, 1.1704678000", \ - "0.2196579000, 0.2302579000, 0.2524155000, 0.3004605000, 0.4100605000, 0.6593647000, 1.2294359000", \ - "0.3229761000, 0.3359077000, 0.3649346000, 0.4251430000, 0.5459908000, 0.7958701000, 1.3664326000", \ - "0.4951994000, 0.5149079000, 0.5568747000, 0.6415689000, 0.8012035000, 1.1015248000, 1.6818154000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0442562000, 0.0503759000, 0.0643050000, 0.0964463000, 0.1702826000, 0.3391227000, 0.7307380000", \ - "0.0442435000, 0.0502622000, 0.0642843000, 0.0964054000, 0.1703216000, 0.3396364000, 0.7300660000", \ - "0.0443193000, 0.0502831000, 0.0642390000, 0.0963018000, 0.1704401000, 0.3398298000, 0.7300144000", \ - "0.0476763000, 0.0530887000, 0.0661441000, 0.0973344000, 0.1702246000, 0.3396780000, 0.7307432000", \ - "0.0622408000, 0.0682749000, 0.0808974000, 0.1102677000, 0.1773518000, 0.3417912000, 0.7329191000", \ - "0.0983870000, 0.1052077000, 0.1200513000, 0.1513156000, 0.2181565000, 0.3684389000, 0.7364778000", \ - "0.1711673000, 0.1803597000, 0.2012842000, 0.2414110000, 0.3190465000, 0.4711341000, 0.8117252000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.1023585000, 0.1146740000, 0.1426552000, 0.2066463000, 0.3546423000, 0.6925264000, 1.4707139000", \ - "0.1021680000, 0.1144612000, 0.1429424000, 0.2073017000, 0.3542514000, 0.6931609000, 1.4701278000", \ - "0.1022466000, 0.1146513000, 0.1426628000, 0.2066846000, 0.3545516000, 0.6926246000, 1.4704767000", \ - "0.1019774000, 0.1142508000, 0.1425620000, 0.2071221000, 0.3542067000, 0.6926953000, 1.4694337000", \ - "0.1141828000, 0.1251913000, 0.1506580000, 0.2106849000, 0.3546847000, 0.6935676000, 1.4710219000", \ - "0.1583432000, 0.1695126000, 0.1964384000, 0.2523345000, 0.3796456000, 0.6988018000, 1.4702827000", \ - "0.2453202000, 0.2599762000, 0.2912404000, 0.3583369000, 0.4926783000, 0.7783362000, 1.4867988000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0486528000, 0.0529760000, 0.0630062000, 0.0859158000, 0.1375850000, 0.2570877000, 0.5317882000", \ - "0.0531142000, 0.0575802000, 0.0675765000, 0.0905178000, 0.1426884000, 0.2621150000, 0.5384533000", \ - "0.0616059000, 0.0661680000, 0.0764164000, 0.0994582000, 0.1518412000, 0.2714714000, 0.5466034000", \ - "0.0765419000, 0.0816958000, 0.0929418000, 0.1167910000, 0.1695057000, 0.2895097000, 0.5643238000", \ - "0.0967351000, 0.1037028000, 0.1187455000, 0.1484576000, 0.2068238000, 0.3283159000, 0.6055076000", \ - "0.1124623000, 0.1235873000, 0.1465517000, 0.1903186000, 0.2684296000, 0.4118294000, 0.6930637000", \ - "0.0936909000, 0.1121755000, 0.1496255000, 0.2206176000, 0.3419759000, 0.5426338000, 0.8828474000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.1066426000, 0.1161629000, 0.1371263000, 0.1855845000, 0.2944390000, 0.5430930000, 1.1129404000", \ - "0.1099777000, 0.1193713000, 0.1410197000, 0.1893097000, 0.2988838000, 0.5473325000, 1.1171233000", \ - "0.1208019000, 0.1304019000, 0.1520832000, 0.2004276000, 0.3101172000, 0.5590068000, 1.1285131000", \ - "0.1486841000, 0.1577564000, 0.1790647000, 0.2286621000, 0.3386517000, 0.5878696000, 1.1583488000", \ - "0.2172577000, 0.2267568000, 0.2488603000, 0.2966757000, 0.4039868000, 0.6528379000, 1.2226287000", \ - "0.3394711000, 0.3530441000, 0.3842344000, 0.4479413000, 0.5634949000, 0.8090024000, 1.3756781000", \ - "0.5370351000, 0.5578426000, 0.6056571000, 0.7030212000, 0.8801938000, 1.1817328000, 1.7453932000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0326616000, 0.0383205000, 0.0515571000, 0.0818822000, 0.1511673000, 0.3099868000, 0.6763636000", \ - "0.0326126000, 0.0383743000, 0.0513303000, 0.0815185000, 0.1508412000, 0.3098886000, 0.6806099000", \ - "0.0328179000, 0.0384885000, 0.0515217000, 0.0815116000, 0.1510790000, 0.3098129000, 0.6782119000", \ - "0.0381106000, 0.0432535000, 0.0549608000, 0.0832585000, 0.1507647000, 0.3107200000, 0.6761381000", \ - "0.0546503000, 0.0599243000, 0.0721270000, 0.0997064000, 0.1606087000, 0.3138046000, 0.6799097000", \ - "0.0919189000, 0.0988141000, 0.1131111000, 0.1437758000, 0.2058668000, 0.3450272000, 0.6865402000", \ - "0.1663927000, 0.1756313000, 0.1960308000, 0.2349575000, 0.3101948000, 0.4550482000, 0.7697284000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.1022379000, 0.1142443000, 0.1422385000, 0.2071532000, 0.3547780000, 0.6932059000, 1.4740273000", \ - "0.1019215000, 0.1141872000, 0.1424675000, 0.2068104000, 0.3546285000, 0.6930954000, 1.4686674000", \ - "0.1021252000, 0.1141161000, 0.1425092000, 0.2066989000, 0.3544212000, 0.6930997000, 1.4711981000", \ - "0.1023176000, 0.1141406000, 0.1423999000, 0.2066785000, 0.3542865000, 0.6939930000, 1.4738014000", \ - "0.1224196000, 0.1323710000, 0.1556149000, 0.2124037000, 0.3544664000, 0.6934219000, 1.4701724000", \ - "0.1816384000, 0.1942706000, 0.2211619000, 0.2733376000, 0.3927119000, 0.6991725000, 1.4743223000", \ - "0.2826584000, 0.3020774000, 0.3416788000, 0.4177747000, 0.5514206000, 0.8092117000, 1.4934273000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0539922000, 0.0588550000, 0.0698942000, 0.0946182000, 0.1506136000, 0.2781775000, 0.5704718000", \ - "0.0580179000, 0.0628814000, 0.0739500000, 0.0986946000, 0.1547524000, 0.2824195000, 0.5747031000", \ - "0.0665400000, 0.0714891000, 0.0826511000, 0.1076085000, 0.1638035000, 0.2917109000, 0.5840201000", \ - "0.0851258000, 0.0907486000, 0.1027005000, 0.1280314000, 0.1846314000, 0.3129386000, 0.6055925000", \ - "0.1134976000, 0.1211571000, 0.1367781000, 0.1690450000, 0.2321097000, 0.3620974000, 0.6556976000", \ - "0.1418426000, 0.1526653000, 0.1773741000, 0.2254699000, 0.3133013000, 0.4673846000, 0.7684565000", \ - "0.1453870000, 0.1636950000, 0.2021218000, 0.2772385000, 0.4114553000, 0.6360686000, 1.0102731000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0520409000, 0.0574072000, 0.0696604000, 0.0972434000, 0.1606863000, 0.3047767000, 0.6366758000", \ - "0.0572742000, 0.0627011000, 0.0750648000, 0.1029038000, 0.1664501000, 0.3105329000, 0.6425848000", \ - "0.0701560000, 0.0756127000, 0.0876584000, 0.1156057000, 0.1789774000, 0.3235979000, 0.6554829000", \ - "0.1022102000, 0.1076492000, 0.1197078000, 0.1471356000, 0.2105097000, 0.3543944000, 0.6867108000", \ - "0.1612119000, 0.1699255000, 0.1879671000, 0.2219241000, 0.2859607000, 0.4297705000, 0.7585099000", \ - "0.2582424000, 0.2718490000, 0.3001799000, 0.3545285000, 0.4496785000, 0.6042452000, 0.9345804000", \ - "0.4194376000, 0.4408991000, 0.4850914000, 0.5716582000, 0.7235291000, 0.9669169000, 1.3365108000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0443735000, 0.0503800000, 0.0643606000, 0.0964300000, 0.1704520000, 0.3396464000, 0.7304567000", \ - "0.0442473000, 0.0503988000, 0.0641637000, 0.0963990000, 0.1702337000, 0.3402194000, 0.7303582000", \ - "0.0442748000, 0.0503184000, 0.0642353000, 0.0963387000, 0.1702116000, 0.3401243000, 0.7301534000", \ - "0.0511559000, 0.0560462000, 0.0683345000, 0.0982396000, 0.1702669000, 0.3397301000, 0.7307368000", \ - "0.0720465000, 0.0779729000, 0.0913632000, 0.1189390000, 0.1819811000, 0.3424619000, 0.7303109000", \ - "0.1150069000, 0.1226905000, 0.1398456000, 0.1736426000, 0.2407425000, 0.3784888000, 0.7363669000", \ - "0.1909533000, 0.2029980000, 0.2272256000, 0.2758632000, 0.3649209000, 0.5216160000, 0.8414367000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0596593000, 0.0675639000, 0.0853075000, 0.1249293000, 0.2139759000, 0.4167298000, 0.8883104000", \ - "0.0596223000, 0.0675024000, 0.0853277000, 0.1249408000, 0.2141011000, 0.4173650000, 0.8849182000", \ - "0.0596692000, 0.0675436000, 0.0853325000, 0.1249958000, 0.2140294000, 0.4173756000, 0.8882697000", \ - "0.0673690000, 0.0738401000, 0.0891733000, 0.1258064000, 0.2140365000, 0.4174804000, 0.8842309000", \ - "0.1042434000, 0.1095018000, 0.1205753000, 0.1480752000, 0.2219840000, 0.4169144000, 0.8858806000", \ - "0.1724777000, 0.1799132000, 0.1969980000, 0.2295616000, 0.2891669000, 0.4458567000, 0.8888485000", \ - "0.2829771000, 0.2958046000, 0.3219598000, 0.3739604000, 0.4648067000, 0.6165932000, 0.9699762000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0471693000, 0.0520841000, 0.0633381000, 0.0880234000, 0.1440994000, 0.2718026000, 0.5640279000", \ - "0.0507396000, 0.0556648000, 0.0669861000, 0.0916976000, 0.1478912000, 0.2756513000, 0.5690729000", \ - "0.0594727000, 0.0646008000, 0.0759812000, 0.1010056000, 0.1572936000, 0.2852665000, 0.5778095000", \ - "0.0805010000, 0.0859789000, 0.0977249000, 0.1222742000, 0.1786615000, 0.3067628000, 0.5994397000", \ - "0.1070930000, 0.1155124000, 0.1331542000, 0.1677574000, 0.2309594000, 0.3586750000, 0.6515649000", \ - "0.1306138000, 0.1439315000, 0.1697739000, 0.2218456000, 0.3138123000, 0.4743164000, 0.7691646000", \ - "0.1304209000, 0.1495540000, 0.1892496000, 0.2679296000, 0.4096700000, 0.6495547000, 1.0325858000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0418186000, 0.0473257000, 0.0595980000, 0.0870895000, 0.1489548000, 0.2912853000, 0.6154053000", \ - "0.0467372000, 0.0522307000, 0.0646025000, 0.0920062000, 0.1542324000, 0.2960422000, 0.6217277000", \ - "0.0593370000, 0.0649312000, 0.0774309000, 0.1052270000, 0.1675573000, 0.3102409000, 0.6339322000", \ - "0.0897235000, 0.0961200000, 0.1087649000, 0.1359691000, 0.1990992000, 0.3387684000, 0.6643185000", \ - "0.1401026000, 0.1502658000, 0.1706972000, 0.2079161000, 0.2727293000, 0.4139023000, 0.7361384000", \ - "0.2212233000, 0.2374104000, 0.2703432000, 0.3302567000, 0.4301733000, 0.5872413000, 0.9025166000", \ - "0.3588506000, 0.3833356000, 0.4345613000, 0.5280514000, 0.6890494000, 0.9379327000, 1.3123891000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0443908000, 0.0504016000, 0.0644042000, 0.0962822000, 0.1704503000, 0.3399166000, 0.7306125000", \ - "0.0441497000, 0.0502892000, 0.0643146000, 0.0964177000, 0.1703407000, 0.3398833000, 0.7305087000", \ - "0.0439330000, 0.0499316000, 0.0638895000, 0.0963626000, 0.1701904000, 0.3393662000, 0.7296328000", \ - "0.0541440000, 0.0589523000, 0.0705195000, 0.0991066000, 0.1703986000, 0.3406758000, 0.7300279000", \ - "0.0783603000, 0.0852123000, 0.0993954000, 0.1288069000, 0.1876179000, 0.3419801000, 0.7300804000", \ - "0.1251158000, 0.1344882000, 0.1549336000, 0.1940747000, 0.2672617000, 0.3982289000, 0.7412851000", \ - "0.2047432000, 0.2196771000, 0.2508080000, 0.3071115000, 0.4093288000, 0.5815924000, 0.8887929000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011503900, 0.0026467800, 0.0060896500, 0.0140109000, 0.0322360000, 0.0741677000"); - values("0.0492216000, 0.0570390000, 0.0745591000, 0.1136751000, 0.2009389000, 0.3992948000, 0.8561933000", \ - "0.0491486000, 0.0570114000, 0.0745876000, 0.1136743000, 0.2009192000, 0.3995038000, 0.8582060000", \ - "0.0496166000, 0.0570164000, 0.0745915000, 0.1137203000, 0.2009239000, 0.3993680000, 0.8566171000", \ - "0.0618933000, 0.0673498000, 0.0809096000, 0.1153434000, 0.2009498000, 0.3994796000, 0.8583603000", \ - "0.1024475000, 0.1073478000, 0.1182149000, 0.1423602000, 0.2112774000, 0.3994680000, 0.8592612000", \ - "0.1700617000, 0.1774228000, 0.1930376000, 0.2256110000, 0.2842052000, 0.4323714000, 0.8593415000", \ - "0.2785389000, 0.2909148000, 0.3169569000, 0.3678088000, 0.4579494000, 0.6122696000, 0.9411655000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211ai_2") { - leakage_power () { - value : 0.0001345000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0099902000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0011590000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0001281000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0006140000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0010767000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0107590000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0007845000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0006140000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0010767000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0094929000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0007834000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0006140000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0099988000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0074242000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0007829000; - when : "A1&A2&B1&!C1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__o211ai"; - cell_leakage_power : 0.0034645460; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079226000, 0.0079212000, 0.0079182000, 0.0079202000, 0.0079247000, 0.0079353000, 0.0079596000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007898200, -0.007899900, -0.007903800, -0.007905700, -0.007909900, -0.007919800, -0.007942400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046090000; - } - pin ("A2") { - capacitance : 0.0043690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079478000, 0.0079448000, 0.0079380000, 0.0079389000, 0.0079411000, 0.0079462000, 0.0079578000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007941700, -0.007934100, -0.007916600, -0.007912000, -0.007901500, -0.007877100, -0.007821000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046870000; - } - pin ("B1") { - capacitance : 0.0043810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0083323000, 0.0083109000, 0.0082616000, 0.0082814000, 0.0083270000, 0.0084320000, 0.0086741000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008066000, -0.008055000, -0.008029700, -0.008024800, -0.008013400, -0.007987100, -0.007926500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045180000; - } - pin ("C1") { - capacitance : 0.0043510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092862000, 0.0092898000, 0.0092981000, 0.0092987000, 0.0093001000, 0.0093032000, 0.0093106000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006405000, -0.006401700, -0.006394000, -0.006373800, -0.006327400, -0.006220500, -0.005973900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044480000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0124568000, 0.0112152000, 0.0080976000, 0.0001313000, -0.020130400, -0.071711000, -0.202882700", \ - "0.0121981000, 0.0109606000, 0.0078617000, -8.09000e-05, -0.020336300, -0.071892400, -0.203039000", \ - "0.0118575000, 0.0106503000, 0.0075600000, -0.000336900, -0.020563200, -0.072100100, -0.203186600", \ - "0.0114022000, 0.0102014000, 0.0071487000, -0.000681900, -0.020784200, -0.072247000, -0.203260700", \ - "0.0111225000, 0.0099230000, 0.0068720000, -0.000936800, -0.021010800, -0.072378600, -0.203277700", \ - "0.0113066000, 0.0100694000, 0.0069134000, -0.001055600, -0.021321000, -0.072668400, -0.203565000", \ - "0.0124916000, 0.0112016000, 0.0079643000, -0.000128900, -0.020610600, -0.072534600, -0.203447100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0254998000, 0.0267398000, 0.0299126000, 0.0379728000, 0.0583049000, 0.1095301000, 0.2392151000", \ - "0.0252721000, 0.0265069000, 0.0297181000, 0.0377683000, 0.0581200000, 0.1093878000, 0.2390376000", \ - "0.0250246000, 0.0262810000, 0.0294817000, 0.0376153000, 0.0579924000, 0.1093602000, 0.2389875000", \ - "0.0247427000, 0.0259821000, 0.0292367000, 0.0373510000, 0.0578018000, 0.1091281000, 0.2387596000", \ - "0.0245642000, 0.0258147000, 0.0289807000, 0.0370900000, 0.0574951000, 0.1088805000, 0.2386789000", \ - "0.0244758000, 0.0257098000, 0.0289102000, 0.0370917000, 0.0576855000, 0.1088715000, 0.2384869000", \ - "0.0249944000, 0.0262142000, 0.0292347000, 0.0369332000, 0.0578173000, 0.1094311000, 0.2393284000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0084517000, 0.0072928000, 0.0042152000, -0.003707600, -0.024023300, -0.075687400, -0.206875300", \ - "0.0081743000, 0.0070624000, 0.0040674000, -0.003739000, -0.023936200, -0.075554900, -0.206753300", \ - "0.0076765000, 0.0065625000, 0.0036672000, -0.003993500, -0.024021800, -0.075522100, -0.206657800", \ - "0.0070702000, 0.0059386000, 0.0030339000, -0.004538400, -0.024358200, -0.075667000, -0.206669100", \ - "0.0069139000, 0.0056203000, 0.0024999000, -0.005132800, -0.024897900, -0.075957000, -0.206773300", \ - "0.0068843000, 0.0056243000, 0.0025418000, -0.005314000, -0.025547800, -0.076587100, -0.207214600", \ - "0.0083755000, 0.0070480000, 0.0037179000, -0.004516600, -0.025013800, -0.076767000, -0.207509000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0209710000, 0.0221817000, 0.0254176000, 0.0334772000, 0.0537985000, 0.1050354000, 0.2349062000", \ - "0.0206660000, 0.0218339000, 0.0250864000, 0.0332265000, 0.0536281000, 0.1049622000, 0.2345506000", \ - "0.0201985000, 0.0215168000, 0.0247110000, 0.0328803000, 0.0533661000, 0.1047251000, 0.2342487000", \ - "0.0197906000, 0.0210501000, 0.0243342000, 0.0324192000, 0.0530772000, 0.1045513000, 0.2343398000", \ - "0.0197081000, 0.0209628000, 0.0241409000, 0.0322912000, 0.0527659000, 0.1041724000, 0.2341619000", \ - "0.0205760000, 0.0218104000, 0.0249298000, 0.0329224000, 0.0529741000, 0.1039153000, 0.2336681000", \ - "0.0245436000, 0.0253348000, 0.0280675000, 0.0356142000, 0.0555278000, 0.1075637000, 0.2360920000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0125468000, 0.0113565000, 0.0082760000, 0.0003970000, -0.019815100, -0.071367500, -0.202390000", \ - "0.0122856000, 0.0110920000, 0.0080523000, 0.0002215000, -0.019898500, -0.071386600, -0.202458200", \ - "0.0119000000, 0.0107087000, 0.0077020000, -7.51000e-05, -0.020113300, -0.071526800, -0.202590200", \ - "0.0114715000, 0.0103193000, 0.0072745000, -0.000491300, -0.020434300, -0.071721600, -0.202662900", \ - "0.0113063000, 0.0101007000, 0.0070150000, -0.000765400, -0.020709100, -0.071974600, -0.202687500", \ - "0.0115892000, 0.0103529000, 0.0072030000, -0.000831900, -0.021192100, -0.072408100, -0.203088800", \ - "0.0133887000, 0.0120814000, 0.0088008000, 0.0004906000, -0.020153500, -0.072177500, -0.203135100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0188283000, 0.0201040000, 0.0233433000, 0.0314464000, 0.0517710000, 0.1029391000, 0.2323981000", \ - "0.0183768000, 0.0196719000, 0.0229819000, 0.0311863000, 0.0516392000, 0.1028110000, 0.2323991000", \ - "0.0177479000, 0.0190356000, 0.0224172000, 0.0307259000, 0.0513007000, 0.1027362000, 0.2323677000", \ - "0.0172986000, 0.0185991000, 0.0218398000, 0.0300924000, 0.0507288000, 0.1021949000, 0.2321566000", \ - "0.0173041000, 0.0185736000, 0.0217548000, 0.0298824000, 0.0504323000, 0.1013869000, 0.2316000000", \ - "0.0182447000, 0.0195441000, 0.0226186000, 0.0304165000, 0.0508328000, 0.1022720000, 0.2307267000", \ - "0.0227117000, 0.0223852000, 0.0259750000, 0.0327902000, 0.0521321000, 0.1047407000, 0.2310041000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0105616000, 0.0093761000, 0.0063489000, -0.001474500, -0.021633400, -0.073146500, -0.204190700", \ - "0.0102603000, 0.0091010000, 0.0060836000, -0.001680500, -0.021756700, -0.073229600, -0.204263800", \ - "0.0099191000, 0.0087418000, 0.0057588000, -0.002000100, -0.021960500, -0.073317000, -0.204312600", \ - "0.0095151000, 0.0083524000, 0.0053245000, -0.002450900, -0.022308400, -0.073549400, -0.204394900", \ - "0.0093823000, 0.0081551000, 0.0050769000, -0.002717800, -0.022626600, -0.073895900, -0.204630600", \ - "0.0102520000, 0.0089470000, 0.0059723000, -0.002191400, -0.022645200, -0.074102300, -0.204907100", \ - "0.0131773000, 0.0117970000, 0.0083652000, -0.000105500, -0.021094800, -0.073578700, -0.204920100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012690670, 0.0032210600, 0.0081754800, 0.0207504600, 0.0526674300, 0.1336770000"); - values("0.0107393000, 0.0121651000, 0.0156592000, 0.0240026000, 0.0444524000, 0.0956213000, 0.2250277000", \ - "0.0103133000, 0.0117287000, 0.0152542000, 0.0236638000, 0.0443164000, 0.0956445000, 0.2251409000", \ - "0.0099352000, 0.0113180000, 0.0147638000, 0.0230913000, 0.0439533000, 0.0954490000, 0.2251323000", \ - "0.0098194000, 0.0110864000, 0.0142961000, 0.0227331000, 0.0436713000, 0.0951296000, 0.2247604000", \ - "0.0099751000, 0.0111773000, 0.0143276000, 0.0223653000, 0.0427130000, 0.0943023000, 0.2240712000", \ - "0.0107565000, 0.0120792000, 0.0153626000, 0.0231316000, 0.0430559000, 0.0942605000, 0.2234984000", \ - "0.0148534000, 0.0163623000, 0.0187316000, 0.0257327000, 0.0450077000, 0.0964586000, 0.2257735000"); - } - } - max_capacitance : 0.1336770000; - max_transition : 1.4955910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0591538000, 0.0625918000, 0.0715450000, 0.0929008000, 0.1453798000, 0.2765507000, 0.6064041000", \ - "0.0630490000, 0.0665328000, 0.0755514000, 0.0968595000, 0.1493932000, 0.2804381000, 0.6104964000", \ - "0.0706901000, 0.0742452000, 0.0832514000, 0.1046430000, 0.1575058000, 0.2886864000, 0.6184204000", \ - "0.0846570000, 0.0885706000, 0.0978862000, 0.1199596000, 0.1727481000, 0.3041186000, 0.6342395000", \ - "0.1066370000, 0.1112923000, 0.1223206000, 0.1472528000, 0.2044683000, 0.3371565000, 0.6682506000", \ - "0.1308115000, 0.1375080000, 0.1525440000, 0.1871562000, 0.2595635000, 0.4083189000, 0.7445340000", \ - "0.1295184000, 0.1398686000, 0.1651760000, 0.2194601000, 0.3264332000, 0.5233244000, 0.9088610000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.1122025000, 0.1184912000, 0.1339225000, 0.1729845000, 0.2696360000, 0.5104730000, 1.1189119000", \ - "0.1171609000, 0.1232150000, 0.1395558000, 0.1779018000, 0.2749022000, 0.5160751000, 1.1244704000", \ - "0.1301940000, 0.1364910000, 0.1520077000, 0.1914921000, 0.2881788000, 0.5291595000, 1.1376733000", \ - "0.1573818000, 0.1636364000, 0.1797378000, 0.2187534000, 0.3157214000, 0.5571493000, 1.1651384000", \ - "0.2151456000, 0.2220716000, 0.2392275000, 0.2784562000, 0.3753458000, 0.6169900000, 1.2258197000", \ - "0.3167061000, 0.3255946000, 0.3472022000, 0.3985631000, 0.5102541000, 0.7539574000, 1.3634464000", \ - "0.4838703000, 0.4981316000, 0.5309531000, 0.6036818000, 0.7566682000, 1.0578118000, 1.6800592000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0411738000, 0.0454361000, 0.0561279000, 0.0835308000, 0.1530697000, 0.3300381000, 0.7803145000", \ - "0.0411620000, 0.0454175000, 0.0560597000, 0.0835710000, 0.1529154000, 0.3303518000, 0.7800532000", \ - "0.0410526000, 0.0453027000, 0.0560004000, 0.0834465000, 0.1530495000, 0.3301973000, 0.7789271000", \ - "0.0442762000, 0.0484176000, 0.0583659000, 0.0846570000, 0.1532165000, 0.3300113000, 0.7793041000", \ - "0.0558505000, 0.0599457000, 0.0704833000, 0.0963465000, 0.1610417000, 0.3320417000, 0.7798452000", \ - "0.0871903000, 0.0919517000, 0.1034515000, 0.1305868000, 0.1961117000, 0.3558180000, 0.7847196000", \ - "0.1535152000, 0.1599546000, 0.1754578000, 0.2105070000, 0.2841689000, 0.4453579000, 0.8477399000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0875822000, 0.0957427000, 0.1164546000, 0.1684883000, 0.2999753000, 0.6296774000, 1.4697485000", \ - "0.0877486000, 0.0958544000, 0.1162066000, 0.1684010000, 0.2990885000, 0.6308344000, 1.4760305000", \ - "0.0875547000, 0.0958422000, 0.1163512000, 0.1683879000, 0.3000238000, 0.6303387000, 1.4728749000", \ - "0.0875306000, 0.0955739000, 0.1162233000, 0.1680828000, 0.2997172000, 0.6302996000, 1.4712204000", \ - "0.0996315000, 0.1066220000, 0.1249811000, 0.1734739000, 0.2997254000, 0.6300362000, 1.4708988000", \ - "0.1383592000, 0.1464534000, 0.1665283000, 0.2146531000, 0.3285833000, 0.6368190000, 1.4745585000", \ - "0.2208197000, 0.2310070000, 0.2572026000, 0.3138015000, 0.4404961000, 0.7216794000, 1.4876540000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0460402000, 0.0494933000, 0.0578243000, 0.0783485000, 0.1293154000, 0.2586932000, 0.5865309000", \ - "0.0500556000, 0.0536291000, 0.0619673000, 0.0827697000, 0.1343395000, 0.2635941000, 0.5916895000", \ - "0.0574397000, 0.0609351000, 0.0697559000, 0.0906974000, 0.1425085000, 0.2728441000, 0.6013300000", \ - "0.0695208000, 0.0734451000, 0.0832147000, 0.1055834000, 0.1582748000, 0.2883483000, 0.6201849000", \ - "0.0852926000, 0.0906049000, 0.1027161000, 0.1303432000, 0.1892511000, 0.3219955000, 0.6508290000", \ - "0.0938226000, 0.1023119000, 0.1217657000, 0.1629620000, 0.2390515000, 0.3932332000, 0.7286826000", \ - "0.0649761000, 0.0792861000, 0.1112594000, 0.1766756000, 0.2965187000, 0.5058910000, 0.8943322000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0936761000, 0.0996471000, 0.1160509000, 0.1546725000, 0.2514154000, 0.4925772000, 1.1006109000", \ - "0.0970545000, 0.1035624000, 0.1195437000, 0.1586762000, 0.2550164000, 0.4962870000, 1.1047864000", \ - "0.1070859000, 0.1137992000, 0.1300806000, 0.1690263000, 0.2661723000, 0.5075787000, 1.1165260000", \ - "0.1343003000, 0.1407124000, 0.1572783000, 0.1955099000, 0.2924426000, 0.5344571000, 1.1430904000", \ - "0.1991368000, 0.2064051000, 0.2226604000, 0.2623280000, 0.3585317000, 0.6001780000, 1.2094102000", \ - "0.3071352000, 0.3178513000, 0.3429629000, 0.3988175000, 0.5122773000, 0.7490762000, 1.3556817000", \ - "0.4822864000, 0.4966600000, 0.5325377000, 0.6161736000, 0.7876279000, 1.1036864000, 1.7105555000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0270021000, 0.0313343000, 0.0422616000, 0.0698610000, 0.1392352000, 0.3152991000, 0.7629499000", \ - "0.0270071000, 0.0313417000, 0.0423555000, 0.0697382000, 0.1395873000, 0.3154675000, 0.7628434000", \ - "0.0273106000, 0.0315515000, 0.0422636000, 0.0695314000, 0.1392054000, 0.3165901000, 0.7630887000", \ - "0.0322298000, 0.0362792000, 0.0462879000, 0.0718425000, 0.1399423000, 0.3157395000, 0.7703313000", \ - "0.0460011000, 0.0501304000, 0.0601473000, 0.0858804000, 0.1498085000, 0.3184263000, 0.7636648000", \ - "0.0792882000, 0.0842213000, 0.0962860000, 0.1240631000, 0.1870798000, 0.3458546000, 0.7704195000", \ - "0.1488909000, 0.1552691000, 0.1711769000, 0.2062507000, 0.2803063000, 0.4397206000, 0.8365448000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0877192000, 0.0955633000, 0.1162350000, 0.1680558000, 0.2990737000, 0.6303025000, 1.4714414000", \ - "0.0876719000, 0.0954840000, 0.1164987000, 0.1683389000, 0.2993639000, 0.6302245000, 1.4743347000", \ - "0.0874388000, 0.0955987000, 0.1160864000, 0.1680343000, 0.2990935000, 0.6298723000, 1.4759984000", \ - "0.0878007000, 0.0956394000, 0.1158765000, 0.1680942000, 0.2992991000, 0.6304020000, 1.4706856000", \ - "0.1105781000, 0.1171638000, 0.1336713000, 0.1775469000, 0.3003171000, 0.6302619000, 1.4749908000", \ - "0.1617906000, 0.1716875000, 0.1942957000, 0.2433739000, 0.3462310000, 0.6399993000, 1.4731305000", \ - "0.2479590000, 0.2624911000, 0.2963342000, 0.3652099000, 0.5054389000, 0.7717100000, 1.4955905000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0536654000, 0.0573716000, 0.0661741000, 0.0877486000, 0.1406000000, 0.2717330000, 0.6017866000", \ - "0.0577067000, 0.0613083000, 0.0703794000, 0.0921534000, 0.1449603000, 0.2762416000, 0.6060900000", \ - "0.0665030000, 0.0701378000, 0.0791654000, 0.1011110000, 0.1541440000, 0.2856625000, 0.6156908000", \ - "0.0850698000, 0.0894135000, 0.0990757000, 0.1214982000, 0.1750023000, 0.3067931000, 0.6371227000", \ - "0.1137439000, 0.1194440000, 0.1318780000, 0.1614372000, 0.2221914000, 0.3560114000, 0.6875207000", \ - "0.1423473000, 0.1511182000, 0.1710693000, 0.2140758000, 0.2998132000, 0.4607805000, 0.8004238000", \ - "0.1510303000, 0.1641184000, 0.1946918000, 0.2609436000, 0.3930529000, 0.6298935000, 1.0445855000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0389677000, 0.0419800000, 0.0493312000, 0.0676168000, 0.1126327000, 0.2254563000, 0.5120920000", \ - "0.0439721000, 0.0470047000, 0.0545771000, 0.0729837000, 0.1182037000, 0.2311682000, 0.5171468000", \ - "0.0565800000, 0.0595963000, 0.0670722000, 0.0855212000, 0.1312622000, 0.2443457000, 0.5298421000", \ - "0.0861812000, 0.0898858000, 0.0984803000, 0.1170874000, 0.1627051000, 0.2761034000, 0.5606793000", \ - "0.1347480000, 0.1406708000, 0.1542480000, 0.1826526000, 0.2368267000, 0.3488080000, 0.6345376000", \ - "0.2119424000, 0.2206874000, 0.2422785000, 0.2880676000, 0.3741016000, 0.5191522000, 0.8036253000", \ - "0.3396441000, 0.3541029000, 0.3869293000, 0.4571975000, 0.5933633000, 0.8279135000, 1.2009478000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0411657000, 0.0453573000, 0.0561570000, 0.0833859000, 0.1532174000, 0.3301862000, 0.7787471000", \ - "0.0411368000, 0.0454070000, 0.0561023000, 0.0835236000, 0.1531397000, 0.3298512000, 0.7789881000", \ - "0.0408975000, 0.0452068000, 0.0559965000, 0.0834421000, 0.1531490000, 0.3300605000, 0.7794773000", \ - "0.0472593000, 0.0510678000, 0.0601887000, 0.0853405000, 0.1529522000, 0.3300267000, 0.7792840000", \ - "0.0661748000, 0.0706829000, 0.0817616000, 0.1066041000, 0.1658757000, 0.3323828000, 0.7793771000", \ - "0.1051164000, 0.1110556000, 0.1263148000, 0.1569836000, 0.2221228000, 0.3701302000, 0.7857308000", \ - "0.1766510000, 0.1854474000, 0.2057480000, 0.2502741000, 0.3396205000, 0.5100708000, 0.8800320000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0408161000, 0.0452156000, 0.0564076000, 0.0844003000, 0.1519250000, 0.3151692000, 0.7283172000", \ - "0.0407479000, 0.0452353000, 0.0564289000, 0.0844416000, 0.1518997000, 0.3151995000, 0.7278348000", \ - "0.0413347000, 0.0454557000, 0.0563867000, 0.0844373000, 0.1519485000, 0.3151526000, 0.7272660000", \ - "0.0535179000, 0.0565490000, 0.0650223000, 0.0886153000, 0.1519820000, 0.3151960000, 0.7271989000", \ - "0.0916700000, 0.0949782000, 0.1031435000, 0.1212400000, 0.1714283000, 0.3168170000, 0.7271547000", \ - "0.1570412000, 0.1620950000, 0.1741951000, 0.2000827000, 0.2527998000, 0.3676325000, 0.7319070000", \ - "0.2596247000, 0.2679000000, 0.2867601000, 0.3280945000, 0.4096979000, 0.5556297000, 0.8429479000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0419311000, 0.0455392000, 0.0546331000, 0.0763683000, 0.1290586000, 0.2601199000, 0.5903144000", \ - "0.0452768000, 0.0490532000, 0.0581061000, 0.0799848000, 0.1329985000, 0.2640569000, 0.5944085000", \ - "0.0543521000, 0.0580085000, 0.0670443000, 0.0888486000, 0.1421146000, 0.2734538000, 0.6037356000", \ - "0.0751731000, 0.0794189000, 0.0891432000, 0.1106530000, 0.1636145000, 0.2953711000, 0.6268466000", \ - "0.1011206000, 0.1073678000, 0.1217633000, 0.1533564000, 0.2152925000, 0.3465832000, 0.6768326000", \ - "0.1246171000, 0.1339292000, 0.1550948000, 0.2015864000, 0.2956800000, 0.4655846000, 0.7990978000", \ - "0.1266108000, 0.1402001000, 0.1725323000, 0.2432022000, 0.3834560000, 0.6372424000, 1.0736434000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0279085000, 0.0311276000, 0.0390137000, 0.0577338000, 0.1036695000, 0.2189183000, 0.5109412000", \ - "0.0329736000, 0.0361740000, 0.0440280000, 0.0629087000, 0.1091458000, 0.2245482000, 0.5159757000", \ - "0.0463027000, 0.0493931000, 0.0569713000, 0.0755208000, 0.1224802000, 0.2383956000, 0.5283519000", \ - "0.0701320000, 0.0749955000, 0.0860152000, 0.1071573000, 0.1529687000, 0.2690823000, 0.5599808000", \ - "0.1073431000, 0.1152880000, 0.1326644000, 0.1668133000, 0.2266979000, 0.3423854000, 0.6322572000", \ - "0.1678496000, 0.1793123000, 0.2065580000, 0.2610032000, 0.3568876000, 0.5132224000, 0.8027497000", \ - "0.2726939000, 0.2902647000, 0.3304889000, 0.4133762000, 0.5647837000, 0.8133668000, 1.1957966000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0413478000, 0.0455470000, 0.0561966000, 0.0835545000, 0.1530880000, 0.3299019000, 0.7792126000", \ - "0.0411474000, 0.0454063000, 0.0560901000, 0.0835840000, 0.1532437000, 0.3299900000, 0.7789762000", \ - "0.0403586000, 0.0444194000, 0.0552781000, 0.0832758000, 0.1530820000, 0.3304670000, 0.7792235000", \ - "0.0495403000, 0.0539095000, 0.0629579000, 0.0867686000, 0.1529508000, 0.3301925000, 0.7798842000", \ - "0.0703106000, 0.0755811000, 0.0884730000, 0.1157411000, 0.1726701000, 0.3328950000, 0.7799415000", \ - "0.1099673000, 0.1177756000, 0.1368669000, 0.1733180000, 0.2449667000, 0.3903730000, 0.7864452000", \ - "0.1807875000, 0.1927398000, 0.2188732000, 0.2746733000, 0.3791000000, 0.5683107000, 0.9223469000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012690700, 0.0032210600, 0.0081754800, 0.0207505000, 0.0526674000, 0.1336770000"); - values("0.0306503000, 0.0352029000, 0.0468700000, 0.0754916000, 0.1444859000, 0.3103605000, 0.7271777000", \ - "0.0306699000, 0.0349929000, 0.0467837000, 0.0755686000, 0.1444709000, 0.3102305000, 0.7276290000", \ - "0.0337603000, 0.0374657000, 0.0475487000, 0.0754821000, 0.1444446000, 0.3101813000, 0.7280885000", \ - "0.0535771000, 0.0552994000, 0.0613247000, 0.0825375000, 0.1450929000, 0.3102758000, 0.7271099000", \ - "0.0928494000, 0.0956132000, 0.1027922000, 0.1207958000, 0.1670939000, 0.3122316000, 0.7274403000", \ - "0.1584977000, 0.1627837000, 0.1737765000, 0.1994755000, 0.2519140000, 0.3652917000, 0.7311299000", \ - "0.2635086000, 0.2695938000, 0.2867552000, 0.3269043000, 0.4089890000, 0.5555826000, 0.8503025000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o211ai_4") { - leakage_power () { - value : 0.0003630000; - when : "!A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0001428000; - when : "!A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0033077000; - when : "!A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0003565000; - when : "!A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0017760000; - when : "!A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0002065000; - when : "!A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0054324000; - when : "!A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0022967000; - when : "!A1&A2&B1&!C1"; - } - leakage_power () { - value : 0.0017760000; - when : "A1&!A2&!B1&C1"; - } - leakage_power () { - value : 0.0002065000; - when : "A1&!A2&!B1&!C1"; - } - leakage_power () { - value : 0.0059303000; - when : "A1&!A2&B1&C1"; - } - leakage_power () { - value : 0.0023150000; - when : "A1&!A2&B1&!C1"; - } - leakage_power () { - value : 0.0384252000; - when : "A1&A2&!B1&C1"; - } - leakage_power () { - value : 0.0004460000; - when : "A1&A2&!B1&!C1"; - } - leakage_power () { - value : 0.0039680000; - when : "A1&A2&B1&C1"; - } - leakage_power () { - value : 0.0023148000; - when : "A1&A2&B1&!C1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__o211ai"; - cell_leakage_power : 0.0043289680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0090560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0085870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158396000, 0.0158298000, 0.0158073000, 0.0158052000, 0.0158005000, 0.0157897000, 0.0157645000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015753900, -0.015745700, -0.015726800, -0.015730100, -0.015737700, -0.015755400, -0.015796100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0095250000; - } - pin ("A2") { - capacitance : 0.0085000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0151545000, 0.0151449000, 0.0151227000, 0.0151228000, 0.0151231000, 0.0151238000, 0.0151252000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015101100, -0.015084200, -0.015045400, -0.015044600, -0.015042700, -0.015038400, -0.015028600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091060000; - } - pin ("B1") { - capacitance : 0.0090450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0170414000, 0.0169638000, 0.0167847000, 0.0168208000, 0.0169041000, 0.0170960000, 0.0175383000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016275100, -0.016262500, -0.016233400, -0.016237100, -0.016245500, -0.016264900, -0.016309700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0094230000; - } - pin ("C1") { - capacitance : 0.0084390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0173801000, 0.0173819000, 0.0173861000, 0.0173877000, 0.0173915000, 0.0174000000, 0.0174200000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013280600, -0.013278500, -0.013273600, -0.013250300, -0.013196400, -0.013072300, -0.012786300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087080000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0240838000, 0.0226844000, 0.0188426000, 0.0082419000, -0.020943900, -0.101377800, -0.322897100", \ - "0.0235919000, 0.0222194000, 0.0183588000, 0.0077934000, -0.021365600, -0.101824800, -0.323257400", \ - "0.0229151000, 0.0215451000, 0.0177580000, 0.0072550000, -0.021834000, -0.102198000, -0.323628300", \ - "0.0221517000, 0.0207607000, 0.0170134000, 0.0065777000, -0.022346900, -0.102590800, -0.323909200", \ - "0.0215916000, 0.0202248000, 0.0164810000, 0.0061138000, -0.022712200, -0.102768300, -0.324002300", \ - "0.0218767000, 0.0204468000, 0.0166344000, 0.0059554000, -0.023527000, -0.103361600, -0.324402900", \ - "0.0237297000, 0.0221625000, 0.0182107000, 0.0073970000, -0.022108400, -0.102822900, -0.324367500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0510168000, 0.0524593000, 0.0562353000, 0.0671046000, 0.0964604000, 0.1765977000, 0.3957580000", \ - "0.0504190000, 0.0518554000, 0.0556689000, 0.0665335000, 0.0960400000, 0.1762100000, 0.3956141000", \ - "0.0495818000, 0.0511162000, 0.0551317000, 0.0659177000, 0.0954509000, 0.1757528000, 0.3948161000", \ - "0.0489888000, 0.0504602000, 0.0544150000, 0.0653327000, 0.0950217000, 0.1754568000, 0.3946718000", \ - "0.0484223000, 0.0498504000, 0.0537940000, 0.0646328000, 0.0943181000, 0.1747923000, 0.3943403000", \ - "0.0484200000, 0.0498654000, 0.0538778000, 0.0647109000, 0.0943654000, 0.1748612000, 0.3940103000", \ - "0.0488274000, 0.0502238000, 0.0539450000, 0.0646605000, 0.0946985000, 0.1753306000, 0.3947753000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0175122000, 0.0161577000, 0.0123669000, 0.0017959000, -0.027482200, -0.108118200, -0.329810000", \ - "0.0170912000, 0.0157839000, 0.0121204000, 0.0017277000, -0.027374800, -0.107912600, -0.329548400", \ - "0.0162109000, 0.0149652000, 0.0113898000, 0.0012471000, -0.027532700, -0.107895400, -0.329404500", \ - "0.0150955000, 0.0138296000, 0.0102862000, 0.0002921000, -0.028135300, -0.108093200, -0.329404900", \ - "0.0148095000, 0.0132806000, 0.0093887000, -0.000739400, -0.029066800, -0.108658000, -0.329460100", \ - "0.0145349000, 0.0131497000, 0.0093434000, -0.001070100, -0.030139800, -0.109672600, -0.330272000", \ - "0.0165176000, 0.0150365000, 0.0110027000, 0.0001216000, -0.029385000, -0.109670100, -0.330823900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0422243000, 0.0436605000, 0.0475829000, 0.0583764000, 0.0878478000, 0.1679816000, 0.3872399000", \ - "0.0415361000, 0.0429981000, 0.0469407000, 0.0578205000, 0.0873650000, 0.1677112000, 0.3866726000", \ - "0.0408132000, 0.0422894000, 0.0461729000, 0.0569691000, 0.0867709000, 0.1672201000, 0.3863267000", \ - "0.0400178000, 0.0414711000, 0.0455299000, 0.0562381000, 0.0859850000, 0.1668731000, 0.3861258000", \ - "0.0395582000, 0.0409951000, 0.0449544000, 0.0557622000, 0.0853409000, 0.1660719000, 0.3861659000", \ - "0.0406637000, 0.0420580000, 0.0459463000, 0.0565943000, 0.0856495000, 0.1657972000, 0.3852624000", \ - "0.0459332000, 0.0471858000, 0.0507188000, 0.0607686000, 0.0892574000, 0.1691341000, 0.3850542000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0246326000, 0.0233016000, 0.0195319000, 0.0090803000, -0.019991200, -0.100379600, -0.321794400", \ - "0.0241250000, 0.0227885000, 0.0191070000, 0.0087588000, -0.020176500, -0.100467300, -0.321835200", \ - "0.0234035000, 0.0220847000, 0.0184083000, 0.0081447000, -0.020603300, -0.100694400, -0.321939900", \ - "0.0226063000, 0.0212759000, 0.0175987000, 0.0073169000, -0.021277400, -0.101119500, -0.322157100", \ - "0.0220920000, 0.0207103000, 0.0170371000, 0.0066928000, -0.021901300, -0.101534000, -0.322392600", \ - "0.0226461000, 0.0212105000, 0.0173459000, 0.0067924000, -0.022741300, -0.102520300, -0.322965800", \ - "0.0255813000, 0.0240712000, 0.0200372000, 0.0090168000, -0.020762500, -0.102038600, -0.323259200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0343818000, 0.0358508000, 0.0398526000, 0.0507250000, 0.0800924000, 0.1599070000, 0.3785905000", \ - "0.0334895000, 0.0349984000, 0.0390997000, 0.0501480000, 0.0798175000, 0.1597923000, 0.3787772000", \ - "0.0324348000, 0.0339535000, 0.0380706000, 0.0492351000, 0.0791885000, 0.1595797000, 0.3790105000", \ - "0.0315233000, 0.0329735000, 0.0369201000, 0.0481397000, 0.0780095000, 0.1586801000, 0.3782294000", \ - "0.0311915000, 0.0326072000, 0.0364960000, 0.0472457000, 0.0770292000, 0.1575077000, 0.3771349000", \ - "0.0328205000, 0.0341793000, 0.0379508000, 0.0484528000, 0.0776810000, 0.1568930000, 0.3762500000", \ - "0.0373984000, 0.0394133000, 0.0438239000, 0.0518766000, 0.0801466000, 0.1602825000, 0.3792036000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0216793000, 0.0203516000, 0.0166480000, 0.0062356000, -0.022796700, -0.103136700, -0.324465600", \ - "0.0211308000, 0.0198262000, 0.0161894000, 0.0058585000, -0.022974800, -0.103227600, -0.324601600", \ - "0.0205229000, 0.0191263000, 0.0154613000, 0.0052845000, -0.023394400, -0.103448000, -0.324664500", \ - "0.0196981000, 0.0183588000, 0.0146601000, 0.0045047000, -0.024075000, -0.103880200, -0.324912000", \ - "0.0193773000, 0.0179940000, 0.0142054000, 0.0039530000, -0.024881300, -0.104546000, -0.325229100", \ - "0.0212361000, 0.0197876000, 0.0158178000, 0.0050082000, -0.024616200, -0.104853200, -0.325800300", \ - "0.0251822000, 0.0236294000, 0.0194656000, 0.0080719000, -0.021995500, -0.103438900, -0.325092200"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013738360, 0.0037748500, 0.0103720500, 0.0284989900, 0.0783058700, 0.2151589000"); - values("0.0206364000, 0.0222702000, 0.0266420000, 0.0379126000, 0.0675146000, 0.1473698000, 0.3661292000", \ - "0.0197136000, 0.0213684000, 0.0257320000, 0.0371789000, 0.0672506000, 0.1475164000, 0.3662003000", \ - "0.0188696000, 0.0204632000, 0.0247966000, 0.0362800000, 0.0663743000, 0.1471708000, 0.3661926000", \ - "0.0184389000, 0.0199553000, 0.0240279000, 0.0353249000, 0.0651631000, 0.1460992000, 0.3657744000", \ - "0.0187313000, 0.0201066000, 0.0239606000, 0.0345409000, 0.0643810000, 0.1443688000, 0.3646020000", \ - "0.0209790000, 0.0223109000, 0.0260136000, 0.0361475000, 0.0649602000, 0.1452851000, 0.3624555000", \ - "0.0262052000, 0.0273900000, 0.0315049000, 0.0401652000, 0.0683411000, 0.1483196000, 0.3641188000"); - } - } - max_capacitance : 0.2151590000; - max_transition : 1.4928460000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0545961000, 0.0566207000, 0.0620174000, 0.0762722000, 0.1138111000, 0.2135186000, 0.4843529000", \ - "0.0587434000, 0.0608442000, 0.0661999000, 0.0805231000, 0.1179502000, 0.2175840000, 0.4885105000", \ - "0.0669352000, 0.0690040000, 0.0744390000, 0.0888835000, 0.1262841000, 0.2262276000, 0.4971147000", \ - "0.0813899000, 0.0836363000, 0.0895707000, 0.1045101000, 0.1422106000, 0.2423024000, 0.5129423000", \ - "0.1021179000, 0.1048667000, 0.1120774000, 0.1297666000, 0.1727038000, 0.2759414000, 0.5473808000", \ - "0.1205969000, 0.1242913000, 0.1356097000, 0.1612092000, 0.2186398000, 0.3424244000, 0.6247804000", \ - "0.1064234000, 0.1119858000, 0.1295568000, 0.1707177000, 0.2607450000, 0.4361727000, 0.7779457000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1326331000, 0.1370274000, 0.1491096000, 0.1803668000, 0.2660390000, 0.4958744000, 1.1221988000", \ - "0.1372679000, 0.1416299000, 0.1538742000, 0.1853879000, 0.2708508000, 0.5008884000, 1.1258757000", \ - "0.1489765000, 0.1530669000, 0.1659111000, 0.1981291000, 0.2840558000, 0.5141035000, 1.1396774000", \ - "0.1758217000, 0.1800951000, 0.1919317000, 0.2243437000, 0.3103004000, 0.5410046000, 1.1665486000", \ - "0.2346069000, 0.2392960000, 0.2514795000, 0.2833578000, 0.3689880000, 0.6000778000, 1.2260908000", \ - "0.3428211000, 0.3488558000, 0.3649177000, 0.4037342000, 0.5018061000, 0.7351169000, 1.3625984000", \ - "0.5295929000, 0.5385034000, 0.5618518000, 0.6178729000, 0.7467814000, 1.0336241000, 1.6753937000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0395774000, 0.0418727000, 0.0482390000, 0.0658909000, 0.1154009000, 0.2526623000, 0.6314368000", \ - "0.0395322000, 0.0417970000, 0.0482266000, 0.0659491000, 0.1153685000, 0.2526019000, 0.6310296000", \ - "0.0393637000, 0.0416984000, 0.0480929000, 0.0658915000, 0.1152021000, 0.2526704000, 0.6311550000", \ - "0.0431856000, 0.0453125000, 0.0513154000, 0.0679250000, 0.1159913000, 0.2523955000, 0.6311258000", \ - "0.0554671000, 0.0577678000, 0.0639228000, 0.0809572000, 0.1271801000, 0.2562876000, 0.6310791000", \ - "0.0878253000, 0.0908120000, 0.0976903000, 0.1164348000, 0.1640172000, 0.2894820000, 0.6419295000", \ - "0.1545513000, 0.1580920000, 0.1681190000, 0.1934496000, 0.2520753000, 0.3839631000, 0.7206437000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1065052000, 0.1120644000, 0.1273010000, 0.1701833000, 0.2857996000, 0.6046454000, 1.4793862000", \ - "0.1063543000, 0.1120409000, 0.1273124000, 0.1701351000, 0.2858816000, 0.6039136000, 1.4751601000", \ - "0.1060878000, 0.1120387000, 0.1275814000, 0.1696541000, 0.2855921000, 0.6035941000, 1.4760301000", \ - "0.1061337000, 0.1118991000, 0.1273770000, 0.1699001000, 0.2858743000, 0.6039982000, 1.4760163000", \ - "0.1152284000, 0.1204533000, 0.1351618000, 0.1745793000, 0.2865919000, 0.6043085000, 1.4764753000", \ - "0.1523029000, 0.1581690000, 0.1740351000, 0.2130105000, 0.3148120000, 0.6106157000, 1.4753883000", \ - "0.2313598000, 0.2381653000, 0.2556066000, 0.3030711000, 0.4140832000, 0.6939467000, 1.4928460000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0457458000, 0.0476212000, 0.0530154000, 0.0672387000, 0.1052225000, 0.2092501000, 0.4965252000", \ - "0.0498160000, 0.0518352000, 0.0574565000, 0.0716308000, 0.1099154000, 0.2150535000, 0.5006000000", \ - "0.0573952000, 0.0594602000, 0.0651172000, 0.0798595000, 0.1183428000, 0.2228797000, 0.5108176000", \ - "0.0686936000, 0.0712506000, 0.0776731000, 0.0937852000, 0.1333590000, 0.2384018000, 0.5250006000", \ - "0.0824217000, 0.0856530000, 0.0936869000, 0.1141620000, 0.1603699000, 0.2698766000, 0.5581494000", \ - "0.0835853000, 0.0887097000, 0.1019288000, 0.1330436000, 0.1980787000, 0.3312670000, 0.6296928000", \ - "0.0364603000, 0.0450957000, 0.0667953000, 0.1185106000, 0.2215061000, 0.4131743000, 0.7739708000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1135202000, 0.1178214000, 0.1300675000, 0.1616791000, 0.2472987000, 0.4770818000, 1.1022314000", \ - "0.1172521000, 0.1215664000, 0.1332684000, 0.1653204000, 0.2511283000, 0.4806041000, 1.1067700000", \ - "0.1272965000, 0.1317630000, 0.1440492000, 0.1753740000, 0.2615484000, 0.4917748000, 1.1176720000", \ - "0.1545172000, 0.1588205000, 0.1708890000, 0.2028171000, 0.2888477000, 0.5194072000, 1.1456015000", \ - "0.2228493000, 0.2270266000, 0.2401034000, 0.2716848000, 0.3568106000, 0.5878299000, 1.2141699000", \ - "0.3509804000, 0.3576906000, 0.3741800000, 0.4179985000, 0.5165247000, 0.7464413000, 1.3712127000", \ - "0.5637972000, 0.5733547000, 0.5982966000, 0.6614490000, 0.8094998000, 1.1123171000, 1.7362227000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0278596000, 0.0304107000, 0.0375028000, 0.0570106000, 0.1103246000, 0.2564399000, 0.6591549000", \ - "0.0278554000, 0.0303922000, 0.0374996000, 0.0568274000, 0.1101466000, 0.2567542000, 0.6589223000", \ - "0.0281870000, 0.0306760000, 0.0376142000, 0.0570026000, 0.1102334000, 0.2563846000, 0.6583303000", \ - "0.0331126000, 0.0355836000, 0.0421828000, 0.0599878000, 0.1111378000, 0.2565971000, 0.6579402000", \ - "0.0471535000, 0.0495894000, 0.0560923000, 0.0743043000, 0.1235505000, 0.2604615000, 0.6583971000", \ - "0.0813759000, 0.0842878000, 0.0921143000, 0.1122609000, 0.1617930000, 0.2945763000, 0.6682891000", \ - "0.1513950000, 0.1553948000, 0.1660120000, 0.1925990000, 0.2527418000, 0.3912452000, 0.7468592000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.1060569000, 0.1118111000, 0.1272341000, 0.1697368000, 0.2856946000, 0.6040330000, 1.4767886000", \ - "0.1059785000, 0.1116956000, 0.1273344000, 0.1697386000, 0.2857012000, 0.6034077000, 1.4818179000", \ - "0.1066465000, 0.1120015000, 0.1272673000, 0.1696989000, 0.2857889000, 0.6035893000, 1.4765820000", \ - "0.1057308000, 0.1113165000, 0.1271494000, 0.1698643000, 0.2857545000, 0.6038298000, 1.4783562000", \ - "0.1216866000, 0.1262938000, 0.1400068000, 0.1773617000, 0.2866368000, 0.6045058000, 1.4765272000", \ - "0.1757320000, 0.1820861000, 0.1981760000, 0.2375252000, 0.3296432000, 0.6112905000, 1.4770262000", \ - "0.2666350000, 0.2756927000, 0.2996921000, 0.3556592000, 0.4817222000, 0.7321014000, 1.4928431000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0475751000, 0.0497378000, 0.0551749000, 0.0696296000, 0.1072362000, 0.2068853000, 0.4785683000", \ - "0.0513862000, 0.0534315000, 0.0590367000, 0.0735785000, 0.1112366000, 0.2112980000, 0.4821066000", \ - "0.0595334000, 0.0616570000, 0.0672266000, 0.0819542000, 0.1199095000, 0.2200741000, 0.4911448000", \ - "0.0762039000, 0.0786692000, 0.0851058000, 0.1008267000, 0.1392136000, 0.2398142000, 0.5116196000", \ - "0.0989771000, 0.1023492000, 0.1112867000, 0.1325544000, 0.1798654000, 0.2854398000, 0.5577006000", \ - "0.1168398000, 0.1217508000, 0.1349178000, 0.1673020000, 0.2365708000, 0.3747136000, 0.6643843000", \ - "0.1007052000, 0.1086361000, 0.1291594000, 0.1788284000, 0.2869243000, 0.4955707000, 0.8746054000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0473856000, 0.0496510000, 0.0557312000, 0.0718208000, 0.1148860000, 0.2313237000, 0.5495802000", \ - "0.0521254000, 0.0544413000, 0.0606413000, 0.0770154000, 0.1204223000, 0.2374009000, 0.5561031000", \ - "0.0647059000, 0.0669607000, 0.0731492000, 0.0896378000, 0.1334193000, 0.2502444000, 0.5692416000", \ - "0.0958999000, 0.0984713000, 0.1048157000, 0.1209220000, 0.1646247000, 0.2821696000, 0.5990005000", \ - "0.1510221000, 0.1549445000, 0.1649466000, 0.1890164000, 0.2394972000, 0.3564709000, 0.6742520000", \ - "0.2425634000, 0.2487256000, 0.2647057000, 0.3025400000, 0.3827260000, 0.5300164000, 0.8471237000", \ - "0.3996002000, 0.4101479000, 0.4336818000, 0.4908773000, 0.6162797000, 0.8527849000, 1.2529300000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0396353000, 0.0419095000, 0.0482836000, 0.0659659000, 0.1153062000, 0.2525867000, 0.6313955000", \ - "0.0395337000, 0.0418659000, 0.0482076000, 0.0658232000, 0.1153007000, 0.2523875000, 0.6309650000", \ - "0.0394555000, 0.0417170000, 0.0478692000, 0.0656171000, 0.1152803000, 0.2525289000, 0.6312290000", \ - "0.0465032000, 0.0487168000, 0.0542683000, 0.0698788000, 0.1164506000, 0.2525865000, 0.6315696000", \ - "0.0643354000, 0.0668691000, 0.0735179000, 0.0910153000, 0.1351366000, 0.2584694000, 0.6310494000", \ - "0.1018701000, 0.1051980000, 0.1143245000, 0.1370266000, 0.1885607000, 0.3086927000, 0.6458485000", \ - "0.1704803000, 0.1756510000, 0.1883293000, 0.2209636000, 0.2915082000, 0.4365245000, 0.7585071000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0480995000, 0.0513576000, 0.0602972000, 0.0846427000, 0.1494804000, 0.3175924000, 0.7750696000", \ - "0.0481014000, 0.0513474000, 0.0602962000, 0.0845880000, 0.1494776000, 0.3174548000, 0.7741950000", \ - "0.0480232000, 0.0512478000, 0.0602557000, 0.0846356000, 0.1495656000, 0.3175788000, 0.7751292000", \ - "0.0572670000, 0.0597256000, 0.0670696000, 0.0881244000, 0.1494820000, 0.3178377000, 0.7746906000", \ - "0.0934391000, 0.0960033000, 0.1028455000, 0.1191995000, 0.1672553000, 0.3191281000, 0.7753068000", \ - "0.1590769000, 0.1625002000, 0.1716453000, 0.1945629000, 0.2456267000, 0.3646362000, 0.7763754000", \ - "0.2629946000, 0.2687857000, 0.2829912000, 0.3181222000, 0.3951323000, 0.5435047000, 0.8769757000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0372129000, 0.0392769000, 0.0449346000, 0.0594258000, 0.0971087000, 0.1967592000, 0.4681517000", \ - "0.0405789000, 0.0427162000, 0.0483789000, 0.0630774000, 0.1007619000, 0.2006925000, 0.4715629000", \ - "0.0497350000, 0.0516839000, 0.0572026000, 0.0717919000, 0.1100225000, 0.2101596000, 0.4810207000", \ - "0.0686931000, 0.0712745000, 0.0779794000, 0.0941542000, 0.1314405000, 0.2318317000, 0.5031447000", \ - "0.0895007000, 0.0932933000, 0.1030922000, 0.1263544000, 0.1773513000, 0.2816507000, 0.5532540000", \ - "0.1014828000, 0.1071493000, 0.1217958000, 0.1573118000, 0.2331705000, 0.3838394000, 0.6707865000", \ - "0.0784628000, 0.0868805000, 0.1086714000, 0.1616636000, 0.2786440000, 0.5056786000, 0.9139134000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0340956000, 0.0366732000, 0.0434915000, 0.0610089000, 0.1068729000, 0.2327572000, 0.5691091000", \ - "0.0388386000, 0.0413820000, 0.0481746000, 0.0659124000, 0.1123526000, 0.2372450000, 0.5773794000", \ - "0.0518530000, 0.0544060000, 0.0609712000, 0.0784770000, 0.1249682000, 0.2502350000, 0.5888673000", \ - "0.0792940000, 0.0827573000, 0.0912791000, 0.1098946000, 0.1564120000, 0.2813275000, 0.6206221000", \ - "0.1236499000, 0.1290517000, 0.1422927000, 0.1719466000, 0.2301859000, 0.3541588000, 0.6949413000", \ - "0.1980873000, 0.2063836000, 0.2275624000, 0.2736284000, 0.3661960000, 0.5277469000, 0.8639179000", \ - "0.3339720000, 0.3458213000, 0.3759638000, 0.4458363000, 0.5889326000, 0.8455730000, 1.2676624000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0397840000, 0.0420542000, 0.0483585000, 0.0659496000, 0.1154214000, 0.2524443000, 0.6309198000", \ - "0.0392205000, 0.0416366000, 0.0481243000, 0.0659204000, 0.1152891000, 0.2524560000, 0.6310529000", \ - "0.0387586000, 0.0410022000, 0.0472491000, 0.0649087000, 0.1153041000, 0.2524257000, 0.6310543000", \ - "0.0480224000, 0.0505157000, 0.0568539000, 0.0721249000, 0.1168078000, 0.2522760000, 0.6315657000", \ - "0.0684240000, 0.0715577000, 0.0795966000, 0.0989371000, 0.1442888000, 0.2614234000, 0.6314190000", \ - "0.1079402000, 0.1125576000, 0.1237165000, 0.1526083000, 0.2118751000, 0.3330546000, 0.6514554000", \ - "0.1760871000, 0.1831959000, 0.2011313000, 0.2427495000, 0.3290027000, 0.4903800000, 0.8156661000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013738400, 0.0037748500, 0.0103721000, 0.0284990000, 0.0783059000, 0.2151590000"); - values("0.0383459000, 0.0416444000, 0.0515491000, 0.0776050000, 0.1465384000, 0.3250101000, 0.8068481000", \ - "0.0382623000, 0.0419311000, 0.0513976000, 0.0776550000, 0.1465212000, 0.3248218000, 0.8066165000", \ - "0.0399477000, 0.0428938000, 0.0515586000, 0.0776884000, 0.1465022000, 0.3246615000, 0.8070269000", \ - "0.0555741000, 0.0575802000, 0.0635143000, 0.0839132000, 0.1467418000, 0.3245769000, 0.8075267000", \ - "0.0949042000, 0.0971328000, 0.1035633000, 0.1207724000, 0.1672700000, 0.3259334000, 0.8079076000", \ - "0.1605735000, 0.1637957000, 0.1727351000, 0.1961822000, 0.2488699000, 0.3737163000, 0.8090458000", \ - "0.2662080000, 0.2705497000, 0.2834981000, 0.3182356000, 0.3977162000, 0.5541602000, 0.9034182000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21a_1") { - leakage_power () { - value : 0.0011118000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0024572000; - when : "A1&A2&!B1"; - } - leakage_power () { - value : 0.0026866000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0022050000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0018589000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0024572000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0024355000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0024572000; - when : "A1&!A2&!B1"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__o21a"; - cell_leakage_power : 0.0022086780; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039908000, 0.0039920000, 0.0039948000, 0.0039926000, 0.0039875000, 0.0039759000, 0.0039490000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003988500, -0.003985800, -0.003979600, -0.003980700, -0.003983100, -0.003988900, -0.004002100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024670000; - } - pin ("A2") { - capacitance : 0.0024150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040718000, 0.0040689000, 0.0040621000, 0.0040611000, 0.0040587000, 0.0040533000, 0.0040407000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004064100, -0.004062400, -0.004058300, -0.004056800, -0.004053100, -0.004044800, -0.004025500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025650000; - } - pin ("B1") { - capacitance : 0.0023690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047437000, 0.0047453000, 0.0047489000, 0.0047507000, 0.0047549000, 0.0047645000, 0.0047867000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002440500, -0.002444500, -0.002453700, -0.002441300, -0.002412700, -0.002346700, -0.002194600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024460000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0139344000, 0.0129491000, 0.0103342000, 0.0022350000, -0.020942400, -0.082965900, -0.246215800", \ - "0.0137831000, 0.0128176000, 0.0101662000, 0.0020987000, -0.021072400, -0.083096600, -0.246296200", \ - "0.0136238000, 0.0126549000, 0.0100056000, 0.0019239000, -0.021244400, -0.083255500, -0.246304600", \ - "0.0134472000, 0.0124801000, 0.0098291000, 0.0017328000, -0.021428900, -0.083437600, -0.246646500", \ - "0.0133259000, 0.0123322000, 0.0096730000, 0.0015791000, -0.021592400, -0.083555800, -0.246744000", \ - "0.0144221000, 0.0131403000, 0.0097523000, 0.0010859000, -0.021769600, -0.083661100, -0.246819100", \ - "0.0155806000, 0.0142340000, 0.0108339000, 0.0019295000, -0.021632800, -0.083269800, -0.246305800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0128871000, 0.0143059000, 0.0179755000, 0.0272192000, 0.0509378000, 0.1131951000, 0.2742285000", \ - "0.0127675000, 0.0142162000, 0.0178791000, 0.0270957000, 0.0508335000, 0.1130712000, 0.2755015000", \ - "0.0125982000, 0.0140478000, 0.0177001000, 0.0269274000, 0.0506834000, 0.1129290000, 0.2743215000", \ - "0.0123991000, 0.0138218000, 0.0174617000, 0.0266842000, 0.0504429000, 0.1120429000, 0.2749143000", \ - "0.0123321000, 0.0136533000, 0.0172957000, 0.0264502000, 0.0501743000, 0.1125065000, 0.2749489000", \ - "0.0124727000, 0.0138461000, 0.0173330000, 0.0263621000, 0.0500380000, 0.1115334000, 0.2737477000", \ - "0.0133025000, 0.0145921000, 0.0181620000, 0.0272466000, 0.0509732000, 0.1131902000, 0.2733124000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0116799000, 0.0107196000, 0.0081380000, 1.450000e-05, -0.023160800, -0.085190100, -0.248335200", \ - "0.0114999000, 0.0105617000, 0.0079340000, -0.000184800, -0.023352700, -0.085356800, -0.248519100", \ - "0.0113006000, 0.0103234000, 0.0076777000, -0.000412800, -0.023583100, -0.085588500, -0.248798900", \ - "0.0111311000, 0.0101617000, 0.0075012000, -0.000609600, -0.023767000, -0.085759000, -0.248967100", \ - "0.0112130000, 0.0102193000, 0.0075493000, -0.000602300, -0.023925800, -0.085873800, -0.249058000", \ - "0.0126142000, 0.0113122000, 0.0078913000, -0.000505400, -0.023460100, -0.085332500, -0.248454500", \ - "0.0145993000, 0.0132499000, 0.0097776000, 0.0008179000, -0.022746400, -0.084370500, -0.247417400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0115154000, 0.0129665000, 0.0166318000, 0.0258335000, 0.0494548000, 0.1117392000, 0.2736718000", \ - "0.0114388000, 0.0128897000, 0.0165506000, 0.0257602000, 0.0493660000, 0.1111292000, 0.2741424000", \ - "0.0112175000, 0.0126621000, 0.0163154000, 0.0255162000, 0.0494018000, 0.1115738000, 0.2710968000", \ - "0.0108783000, 0.0122923000, 0.0158772000, 0.0250794000, 0.0490387000, 0.1106433000, 0.2736389000", \ - "0.0107661000, 0.0121055000, 0.0155492000, 0.0247154000, 0.0483589000, 0.1109109000, 0.2714711000", \ - "0.0107919000, 0.0121378000, 0.0155669000, 0.0247033000, 0.0483796000, 0.1096235000, 0.2720086000", \ - "0.0114200000, 0.0127350000, 0.0162873000, 0.0253967000, 0.0491476000, 0.1111427000, 0.2722825000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0096099000, 0.0087971000, 0.0062130000, -0.002245100, -0.025851600, -0.088108000, -0.251495000", \ - "0.0093394000, 0.0085346000, 0.0059517000, -0.002487600, -0.026090900, -0.088344400, -0.251734400", \ - "0.0090346000, 0.0081906000, 0.0055713000, -0.002797500, -0.026378100, -0.088628600, -0.252017400", \ - "0.0087075000, 0.0078830000, 0.0052442000, -0.003104800, -0.026600100, -0.088809000, -0.252178000", \ - "0.0083438000, 0.0075327000, 0.0051179000, -0.003183100, -0.026622300, -0.088791300, -0.252110300", \ - "0.0102210000, 0.0089741000, 0.0055924000, -0.003285200, -0.026391300, -0.088501400, -0.251808000", \ - "0.0117108000, 0.0103525000, 0.0069255000, -0.001933100, -0.025475600, -0.087307700, -0.250568800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0115158000, 0.0129603000, 0.0166187000, 0.0258721000, 0.0498220000, 0.1113104000, 0.2729463000", \ - "0.0113874000, 0.0128101000, 0.0164780000, 0.0257375000, 0.0494652000, 0.1112373000, 0.2727372000", \ - "0.0111614000, 0.0126159000, 0.0162732000, 0.0255093000, 0.0494607000, 0.1109384000, 0.2726095000", \ - "0.0109037000, 0.0123151000, 0.0159437000, 0.0251424000, 0.0488989000, 0.1110514000, 0.2736060000", \ - "0.0107816000, 0.0120457000, 0.0156115000, 0.0247791000, 0.0484554000, 0.1108567000, 0.2728566000", \ - "0.0112386000, 0.0125824000, 0.0161117000, 0.0250940000, 0.0488053000, 0.1101642000, 0.2721219000", \ - "0.0121279000, 0.0134021000, 0.0168457000, 0.0258820000, 0.0497615000, 0.1116321000, 0.2730166000"); - } - } - max_capacitance : 0.1629740000; - max_transition : 1.5111880000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.1477577000, 0.1544530000, 0.1684099000, 0.1963403000, 0.2543213000, 0.3902269000, 0.7414725000", \ - "0.1530534000, 0.1597328000, 0.1737795000, 0.2014257000, 0.2593218000, 0.3952065000, 0.7458255000", \ - "0.1652123000, 0.1718864000, 0.1859222000, 0.2135744000, 0.2715133000, 0.4074560000, 0.7576965000", \ - "0.1912420000, 0.1979551000, 0.2118466000, 0.2398071000, 0.2977383000, 0.4337569000, 0.7853017000", \ - "0.2483332000, 0.2551250000, 0.2692534000, 0.2969074000, 0.3549867000, 0.4909548000, 0.8426357000", \ - "0.3509823000, 0.3586983000, 0.3746858000, 0.4053957000, 0.4664536000, 0.6041832000, 0.9554283000", \ - "0.5213165000, 0.5309558000, 0.5503206000, 0.5862809000, 0.6529611000, 0.7942232000, 1.1466048000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0832170000, 0.0902228000, 0.1063823000, 0.1443331000, 0.2396075000, 0.4865265000, 1.1331883000", \ - "0.0877685000, 0.0948001000, 0.1109280000, 0.1489006000, 0.2441172000, 0.4909715000, 1.1376146000", \ - "0.0972194000, 0.1042529000, 0.1203575000, 0.1583036000, 0.2535691000, 0.5004603000, 1.1470014000", \ - "0.1171748000, 0.1242094000, 0.1403087000, 0.1781364000, 0.2733395000, 0.5208338000, 1.1685559000", \ - "0.1511535000, 0.1586405000, 0.1754114000, 0.2136692000, 0.3094198000, 0.5574733000, 1.2059714000", \ - "0.1945102000, 0.2033150000, 0.2211998000, 0.2606687000, 0.3563801000, 0.6037292000, 1.2499606000", \ - "0.2281220000, 0.2392491000, 0.2621871000, 0.3054926000, 0.4018018000, 0.6502241000, 1.2958321000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0238366000, 0.0284674000, 0.0391444000, 0.0645764000, 0.1272941000, 0.2993502000, 0.7664654000", \ - "0.0235963000, 0.0282183000, 0.0395658000, 0.0647661000, 0.1273701000, 0.2991852000, 0.7680915000", \ - "0.0236347000, 0.0282318000, 0.0395173000, 0.0647432000, 0.1273366000, 0.2989895000, 0.7627117000", \ - "0.0238497000, 0.0285766000, 0.0392755000, 0.0645037000, 0.1275615000, 0.3002402000, 0.7654695000", \ - "0.0244293000, 0.0294055000, 0.0400604000, 0.0653077000, 0.1275566000, 0.2993930000, 0.7667272000", \ - "0.0294666000, 0.0346387000, 0.0458737000, 0.0716848000, 0.1322331000, 0.3011494000, 0.7672256000", \ - "0.0401671000, 0.0458142000, 0.0577883000, 0.0834809000, 0.1440418000, 0.3064055000, 0.7610916000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0226704000, 0.0297095000, 0.0480072000, 0.0972019000, 0.2306620000, 0.5815826000, 1.5024484000", \ - "0.0226495000, 0.0296810000, 0.0479741000, 0.0972685000, 0.2307699000, 0.5811815000, 1.5035692000", \ - "0.0226900000, 0.0297092000, 0.0478973000, 0.0972792000, 0.2307460000, 0.5816808000, 1.4979921000", \ - "0.0230168000, 0.0299708000, 0.0480864000, 0.0972185000, 0.2297182000, 0.5822016000, 1.5041375000", \ - "0.0256805000, 0.0324973000, 0.0501869000, 0.0980621000, 0.2305648000, 0.5807641000, 1.5026534000", \ - "0.0312738000, 0.0382265000, 0.0551203000, 0.1008654000, 0.2306063000, 0.5786832000, 1.4973237000", \ - "0.0435728000, 0.0508176000, 0.0678410000, 0.1086202000, 0.2331357000, 0.5817464000, 1.4938971000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.1341642000, 0.1408618000, 0.1548972000, 0.1825851000, 0.2405215000, 0.3764684000, 0.7273569000", \ - "0.1378827000, 0.1444076000, 0.1583589000, 0.1865298000, 0.2443405000, 0.3803879000, 0.7306740000", \ - "0.1485233000, 0.1551916000, 0.1692236000, 0.1971931000, 0.2549605000, 0.3909775000, 0.7420266000", \ - "0.1768767000, 0.1835825000, 0.1974741000, 0.2253965000, 0.2833482000, 0.4194047000, 0.7705619000", \ - "0.2447379000, 0.2514314000, 0.2654704000, 0.2934116000, 0.3518552000, 0.4879105000, 0.8393985000", \ - "0.3687335000, 0.3769053000, 0.3929903000, 0.4231245000, 0.4834386000, 0.6215168000, 0.9719415000", \ - "0.5664182000, 0.5770213000, 0.5978437000, 0.6340978000, 0.6986453000, 0.8381847000, 1.1911833000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0700623000, 0.0768511000, 0.0924971000, 0.1298607000, 0.2243573000, 0.4732589000, 1.1208975000", \ - "0.0747302000, 0.0815140000, 0.0971393000, 0.1345383000, 0.2294824000, 0.4763491000, 1.1242384000", \ - "0.0841225000, 0.0908593000, 0.1064764000, 0.1438758000, 0.2386759000, 0.4848892000, 1.1334824000", \ - "0.1027444000, 0.1095430000, 0.1252189000, 0.1625659000, 0.2573335000, 0.5102375000, 1.1506704000", \ - "0.1299730000, 0.1374504000, 0.1539666000, 0.1918307000, 0.2870130000, 0.5341897000, 1.1829193000", \ - "0.1583218000, 0.1674637000, 0.1858941000, 0.2253078000, 0.3205793000, 0.5675438000, 1.2154293000", \ - "0.1619228000, 0.1742749000, 0.1984858000, 0.2431922000, 0.3393073000, 0.5868222000, 1.2333410000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0238469000, 0.0282077000, 0.0395536000, 0.0645990000, 0.1274328000, 0.2982561000, 0.7646014000", \ - "0.0235098000, 0.0286420000, 0.0393584000, 0.0645269000, 0.1276741000, 0.3007122000, 0.7638137000", \ - "0.0236000000, 0.0282163000, 0.0395523000, 0.0647158000, 0.1273749000, 0.3009039000, 0.7639660000", \ - "0.0238437000, 0.0285957000, 0.0392853000, 0.0645569000, 0.1276404000, 0.3009841000, 0.7640494000", \ - "0.0245076000, 0.0289770000, 0.0399879000, 0.0649343000, 0.1273167000, 0.2989547000, 0.7658319000", \ - "0.0330931000, 0.0376084000, 0.0472892000, 0.0709948000, 0.1325314000, 0.3014353000, 0.7625287000", \ - "0.0474967000, 0.0529311000, 0.0635619000, 0.0858167000, 0.1420109000, 0.3054658000, 0.7629151000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0210879000, 0.0280782000, 0.0463601000, 0.0958105000, 0.2303679000, 0.5846222000, 1.5066316000", \ - "0.0210863000, 0.0280816000, 0.0463531000, 0.0958186000, 0.2298840000, 0.5833981000, 1.5111877000", \ - "0.0210775000, 0.0280449000, 0.0464712000, 0.0959660000, 0.2298915000, 0.5827930000, 1.5000987000", \ - "0.0219468000, 0.0288261000, 0.0469197000, 0.0962096000, 0.2304785000, 0.5821956000, 1.5037660000", \ - "0.0255706000, 0.0321610000, 0.0494454000, 0.0973574000, 0.2294254000, 0.5835148000, 1.5009718000", \ - "0.0329276000, 0.0401255000, 0.0560684000, 0.1003351000, 0.2309074000, 0.5789080000, 1.5068465000", \ - "0.0476337000, 0.0551838000, 0.0712219000, 0.1113291000, 0.2332627000, 0.5829616000, 1.4955468000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0685490000, 0.0742137000, 0.0867080000, 0.1125660000, 0.1675788000, 0.3014103000, 0.6508575000", \ - "0.0737954000, 0.0794779000, 0.0919953000, 0.1178934000, 0.1729280000, 0.3067684000, 0.6562381000", \ - "0.0870530000, 0.0927027000, 0.1051879000, 0.1311428000, 0.1862420000, 0.3201652000, 0.6713857000", \ - "0.1190508000, 0.1246718000, 0.1372042000, 0.1633667000, 0.2185506000, 0.3525890000, 0.7038866000", \ - "0.1784492000, 0.1852167000, 0.1995241000, 0.2282076000, 0.2850477000, 0.4194415000, 0.7705360000", \ - "0.2723685000, 0.2811985000, 0.2995326000, 0.3350057000, 0.3975891000, 0.5344014000, 0.8843958000", \ - "0.4248753000, 0.4362689000, 0.4602387000, 0.5069692000, 0.5830837000, 0.7261055000, 1.0766150000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0764844000, 0.0835369000, 0.0996105000, 0.1375692000, 0.2330883000, 0.4799789000, 1.1265125000", \ - "0.0805802000, 0.0875791000, 0.1037439000, 0.1416649000, 0.2368795000, 0.4835669000, 1.1304759000", \ - "0.0905182000, 0.0976492000, 0.1137088000, 0.1516303000, 0.2470780000, 0.4941308000, 1.1408193000", \ - "0.1138152000, 0.1208939000, 0.1368309000, 0.1745818000, 0.2697220000, 0.5180357000, 1.1664490000", \ - "0.1478701000, 0.1550136000, 0.1717535000, 0.2098478000, 0.3056675000, 0.5536525000, 1.2022916000", \ - "0.1864060000, 0.1949792000, 0.2125493000, 0.2513926000, 0.3466307000, 0.5950436000, 1.2424273000", \ - "0.2103868000, 0.2213588000, 0.2428289000, 0.2845867000, 0.3792381000, 0.6281234000, 1.2745989000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0174001000, 0.0222879000, 0.0340359000, 0.0595557000, 0.1221369000, 0.2961008000, 0.7616917000", \ - "0.0174546000, 0.0222887000, 0.0340232000, 0.0595148000, 0.1221462000, 0.2960818000, 0.7614686000", \ - "0.0173877000, 0.0223440000, 0.0339734000, 0.0596557000, 0.1221941000, 0.2962517000, 0.7719224000", \ - "0.0179830000, 0.0226642000, 0.0342935000, 0.0598345000, 0.1223331000, 0.2962401000, 0.7719654000", \ - "0.0236833000, 0.0285296000, 0.0400780000, 0.0644269000, 0.1243932000, 0.2977396000, 0.7593144000", \ - "0.0335225000, 0.0397620000, 0.0532982000, 0.0792417000, 0.1352586000, 0.2984797000, 0.7629099000", \ - "0.0474720000, 0.0551223000, 0.0730523000, 0.1053918000, 0.1590112000, 0.3084304000, 0.7582080000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0226158000, 0.0297196000, 0.0478724000, 0.0971947000, 0.2306479000, 0.5813389000, 1.4988157000", \ - "0.0227040000, 0.0297304000, 0.0478731000, 0.0972007000, 0.2303270000, 0.5813829000, 1.5041218000", \ - "0.0226573000, 0.0297213000, 0.0478518000, 0.0972504000, 0.2302218000, 0.5816878000, 1.5002182000", \ - "0.0231154000, 0.0300786000, 0.0482780000, 0.0970529000, 0.2306415000, 0.5808750000, 1.5023125000", \ - "0.0254544000, 0.0325167000, 0.0501746000, 0.0989318000, 0.2303448000, 0.5824649000, 1.4996584000", \ - "0.0321218000, 0.0382438000, 0.0543654000, 0.1002441000, 0.2318721000, 0.5803988000, 1.5059011000", \ - "0.0444615000, 0.0510866000, 0.0661070000, 0.1071253000, 0.2329321000, 0.5841049000, 1.4955747000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21a_2") { - leakage_power () { - value : 0.0036491000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0031636000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0020413000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0034189000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0025891000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0034189000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0013631000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0034189000; - when : "A1&A2&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o21a"; - cell_leakage_power : 0.0028828480; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040105000, 0.0040083000, 0.0040034000, 0.0040047000, 0.0040078000, 0.0040149000, 0.0040313000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004002500, -0.004000800, -0.003996800, -0.003994600, -0.003989600, -0.003977900, -0.003951100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024380000; - } - pin ("A2") { - capacitance : 0.0024040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040067000, 0.0040088000, 0.0040138000, 0.0040144000, 0.0040159000, 0.0040192000, 0.0040269000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004023600, -0.004019800, -0.004011100, -0.004011700, -0.004013000, -0.004016200, -0.004023500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025640000; - } - pin ("B1") { - capacitance : 0.0024110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048738000, 0.0048725000, 0.0048695000, 0.0048676000, 0.0048631000, 0.0048528000, 0.0048291000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002698500, -0.002703800, -0.002716100, -0.002704700, -0.002678400, -0.002617800, -0.002478000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024930000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0168101000, 0.0153723000, 0.0118168000, 0.0008346000, -0.034776300, -0.142026000, -0.454390400", \ - "0.0167020000, 0.0154138000, 0.0117477000, 0.0007846000, -0.034797000, -0.142108300, -0.454492800", \ - "0.0167058000, 0.0152345000, 0.0115920000, 0.0006900000, -0.034954100, -0.142248900, -0.454660100", \ - "0.0164334000, 0.0149996000, 0.0113694000, 0.0004227000, -0.035177700, -0.142443500, -0.454795000", \ - "0.0163291000, 0.0150417000, 0.0113261000, 0.0003245000, -0.035356400, -0.142563100, -0.454958200", \ - "0.0172207000, 0.0156387000, 0.0112719000, -0.000193600, -0.035681200, -0.142794200, -0.455063000", \ - "0.0203357000, 0.0186685000, 0.0141610000, 0.0013286000, -0.035550100, -0.142367300, -0.454638100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0174420000, 0.0191158000, 0.0238296000, 0.0371509000, 0.0745411000, 0.1818402000, 0.4910827000", \ - "0.0173327000, 0.0190350000, 0.0238036000, 0.0370655000, 0.0744608000, 0.1813691000, 0.4903391000", \ - "0.0172021000, 0.0188861000, 0.0235936000, 0.0369054000, 0.0743441000, 0.1815666000, 0.4908356000", \ - "0.0170579000, 0.0187403000, 0.0234863000, 0.0367409000, 0.0741196000, 0.1814118000, 0.4923397000", \ - "0.0168959000, 0.0185409000, 0.0232335000, 0.0363646000, 0.0738074000, 0.1811334000, 0.4899322000", \ - "0.0173771000, 0.0189535000, 0.0234623000, 0.0363902000, 0.0736220000, 0.1804211000, 0.4914381000", \ - "0.0182128000, 0.0197146000, 0.0240915000, 0.0371161000, 0.0743247000, 0.1818735000, 0.4907081000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0146963000, 0.0132874000, 0.0096593000, -0.001277400, -0.036846800, -0.144158100, -0.456493700", \ - "0.0147140000, 0.0131319000, 0.0095168000, -0.001339300, -0.036991200, -0.144289600, -0.456703700", \ - "0.0144057000, 0.0129330000, 0.0092800000, -0.001663800, -0.037234200, -0.144527000, -0.456897200", \ - "0.0141928000, 0.0127541000, 0.0091160000, -0.001852000, -0.037449000, -0.144726700, -0.457083500", \ - "0.0140342000, 0.0126089000, 0.0089516000, -0.001880600, -0.037575100, -0.144867900, -0.457208100", \ - "0.0144190000, 0.0128135000, 0.0086907000, -0.002160400, -0.037713300, -0.144841600, -0.457057900", \ - "0.0196588000, 0.0179462000, 0.0133089000, 0.0003196000, -0.036680600, -0.143747400, -0.455845900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0160912000, 0.0177829000, 0.0225792000, 0.0358584000, 0.0732052000, 0.1804141000, 0.4880280000", \ - "0.0160613000, 0.0177528000, 0.0225492000, 0.0358325000, 0.0731771000, 0.1804411000, 0.4878954000", \ - "0.0158813000, 0.0175825000, 0.0223609000, 0.0356889000, 0.0730054000, 0.1800409000, 0.4896942000", \ - "0.0156482000, 0.0172735000, 0.0220420000, 0.0352414000, 0.0726302000, 0.1797300000, 0.4896084000", \ - "0.0154893000, 0.0170289000, 0.0216705000, 0.0348305000, 0.0720562000, 0.1794007000, 0.4894511000", \ - "0.0156562000, 0.0172239000, 0.0217613000, 0.0348119000, 0.0718631000, 0.1782397000, 0.4886908000", \ - "0.0164792000, 0.0179769000, 0.0224231000, 0.0353595000, 0.0726912000, 0.1798291000, 0.4887237000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0123664000, 0.0113149000, 0.0081681000, -0.002806600, -0.039222900, -0.147051300, -0.459712700", \ - "0.0122099000, 0.0111213000, 0.0080029000, -0.002981100, -0.039385000, -0.147218900, -0.459864800", \ - "0.0119248000, 0.0108372000, 0.0076339000, -0.003337000, -0.039688000, -0.147500300, -0.460148000", \ - "0.0116171000, 0.0104614000, 0.0072232000, -0.003772400, -0.040056800, -0.147797300, -0.460410500", \ - "0.0117763000, 0.0105674000, 0.0071710000, -0.003881800, -0.040135800, -0.147796100, -0.460365100", \ - "0.0144531000, 0.0129033000, 0.0085075000, -0.004158100, -0.040084000, -0.147596900, -0.460091900", \ - "0.0165779000, 0.0149016000, 0.0103404000, -0.002519800, -0.039532400, -0.146847200, -0.459183400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0163736000, 0.0180666000, 0.0227915000, 0.0361015000, 0.0735261000, 0.1813586000, 0.4919254000", \ - "0.0162420000, 0.0179413000, 0.0226634000, 0.0360018000, 0.0734139000, 0.1807086000, 0.4892909000", \ - "0.0160412000, 0.0177505000, 0.0225286000, 0.0358555000, 0.0732184000, 0.1811144000, 0.4916274000", \ - "0.0158751000, 0.0175303000, 0.0222663000, 0.0355058000, 0.0728385000, 0.1799340000, 0.4889954000", \ - "0.0155878000, 0.0171925000, 0.0218559000, 0.0349229000, 0.0722087000, 0.1794700000, 0.4908967000", \ - "0.0164314000, 0.0179426000, 0.0224556000, 0.0350434000, 0.0720682000, 0.1787225000, 0.4891847000", \ - "0.0173784000, 0.0188666000, 0.0232054000, 0.0360309000, 0.0731894000, 0.1801841000, 0.4882626000"); - } - } - max_capacitance : 0.2948100000; - max_transition : 1.5084580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1744457000, 0.1804836000, 0.1937485000, 0.2201087000, 0.2721059000, 0.3906667000, 0.7111945000", \ - "0.1798609000, 0.1858372000, 0.1991136000, 0.2251884000, 0.2774777000, 0.3959953000, 0.7163860000", \ - "0.1922811000, 0.1983463000, 0.2116002000, 0.2377741000, 0.2898908000, 0.4083869000, 0.7284953000", \ - "0.2184337000, 0.2244736000, 0.2377630000, 0.2640818000, 0.3162101000, 0.4346827000, 0.7546875000", \ - "0.2768208000, 0.2828273000, 0.2960206000, 0.3222458000, 0.3746954000, 0.4933767000, 0.8132362000", \ - "0.3898240000, 0.3965508000, 0.4113580000, 0.4400403000, 0.4949236000, 0.6154233000, 0.9360424000", \ - "0.5793228000, 0.5876851000, 0.6056869000, 0.6396975000, 0.7021899000, 0.8274632000, 1.1497053000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0945007000, 0.1004484000, 0.1143493000, 0.1468219000, 0.2301383000, 0.4653071000, 1.1432526000", \ - "0.0989768000, 0.1049839000, 0.1189377000, 0.1514032000, 0.2348749000, 0.4700437000, 1.1468920000", \ - "0.1083891000, 0.1143333000, 0.1282392000, 0.1607260000, 0.2440972000, 0.4795812000, 1.1576168000", \ - "0.1286817000, 0.1346167000, 0.1485147000, 0.1808556000, 0.2641783000, 0.4994049000, 1.1800891000", \ - "0.1662875000, 0.1726127000, 0.1871917000, 0.2202927000, 0.3039480000, 0.5394587000, 1.2203347000", \ - "0.2178417000, 0.2254217000, 0.2420311000, 0.2771118000, 0.3617484000, 0.5969895000, 1.2760591000", \ - "0.2657810000, 0.2757719000, 0.2968217000, 0.3378103000, 0.4249582000, 0.6614773000, 1.3381526000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0263242000, 0.0300036000, 0.0384297000, 0.0575915000, 0.1065028000, 0.2453596000, 0.6729253000", \ - "0.0259674000, 0.0298620000, 0.0385241000, 0.0577972000, 0.1066765000, 0.2457028000, 0.6738875000", \ - "0.0260499000, 0.0296657000, 0.0385883000, 0.0573734000, 0.1067828000, 0.2458674000, 0.6734296000", \ - "0.0261900000, 0.0299245000, 0.0384316000, 0.0573455000, 0.1066366000, 0.2457370000, 0.6709452000", \ - "0.0261709000, 0.0299404000, 0.0382784000, 0.0574185000, 0.1064885000, 0.2454268000, 0.6709232000", \ - "0.0317992000, 0.0354811000, 0.0442737000, 0.0638769000, 0.1111452000, 0.2482144000, 0.6720470000", \ - "0.0434440000, 0.0475667000, 0.0572267000, 0.0778910000, 0.1257717000, 0.2583986000, 0.6725523000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0207358000, 0.0257741000, 0.0392753000, 0.0768973000, 0.1903662000, 0.5274070000, 1.5045422000", \ - "0.0207688000, 0.0259100000, 0.0392184000, 0.0769498000, 0.1903297000, 0.5274435000, 1.5003530000", \ - "0.0208571000, 0.0258460000, 0.0392922000, 0.0770587000, 0.1906008000, 0.5277249000, 1.5044914000", \ - "0.0208051000, 0.0258925000, 0.0392814000, 0.0770890000, 0.1904754000, 0.5276892000, 1.5040263000", \ - "0.0232633000, 0.0283171000, 0.0416314000, 0.0784755000, 0.1910671000, 0.5276801000, 1.5020813000", \ - "0.0292761000, 0.0346116000, 0.0477940000, 0.0829097000, 0.1926710000, 0.5266429000, 1.5003724000", \ - "0.0413324000, 0.0474961000, 0.0614101000, 0.0946424000, 0.1969692000, 0.5279212000, 1.4967686000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1614281000, 0.1675108000, 0.1807779000, 0.2070580000, 0.2594222000, 0.3776882000, 0.6979448000", \ - "0.1650372000, 0.1714156000, 0.1843260000, 0.2105773000, 0.2626599000, 0.3811482000, 0.7012865000", \ - "0.1760117000, 0.1820570000, 0.1953081000, 0.2214614000, 0.2738265000, 0.3918795000, 0.7121188000", \ - "0.2041621000, 0.2102348000, 0.2235330000, 0.2498258000, 0.3020639000, 0.4205480000, 0.7409629000", \ - "0.2731201000, 0.2791548000, 0.2923296000, 0.3182776000, 0.3705357000, 0.4891601000, 0.8096943000", \ - "0.4109877000, 0.4181272000, 0.4336648000, 0.4624492000, 0.5173306000, 0.6379464000, 0.9581375000", \ - "0.6322566000, 0.6418842000, 0.6621357000, 0.6991219000, 0.7629442000, 0.8881992000, 1.2110026000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0794585000, 0.0850353000, 0.0983340000, 0.1297839000, 0.2124493000, 0.4474866000, 1.1320150000", \ - "0.0842235000, 0.0897862000, 0.1030915000, 0.1345467000, 0.2172421000, 0.4522092000, 1.1351043000", \ - "0.0938019000, 0.0993637000, 0.1126557000, 0.1441207000, 0.2268153000, 0.4624790000, 1.1383877000", \ - "0.1138691000, 0.1193859000, 0.1326796000, 0.1639947000, 0.2466178000, 0.4826196000, 1.1617864000", \ - "0.1466602000, 0.1527038000, 0.1670355000, 0.1995640000, 0.2825382000, 0.5183597000, 1.1975313000", \ - "0.1851487000, 0.1929401000, 0.2095186000, 0.2445784000, 0.3282419000, 0.5632468000, 1.2427289000", \ - "0.2063377000, 0.2167496000, 0.2393835000, 0.2814969000, 0.3687870000, 0.6038652000, 1.2809367000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0259917000, 0.0297038000, 0.0380346000, 0.0576007000, 0.1063049000, 0.2457193000, 0.6705808000", \ - "0.0261276000, 0.0297094000, 0.0380946000, 0.0573520000, 0.1068153000, 0.2459708000, 0.6735105000", \ - "0.0263069000, 0.0296881000, 0.0384919000, 0.0575707000, 0.1062848000, 0.2458000000, 0.6706925000", \ - "0.0262255000, 0.0299541000, 0.0383721000, 0.0575754000, 0.1064390000, 0.2456657000, 0.6686058000", \ - "0.0260631000, 0.0297180000, 0.0382154000, 0.0582902000, 0.1069013000, 0.2454833000, 0.6738573000", \ - "0.0353928000, 0.0391251000, 0.0471996000, 0.0651627000, 0.1114468000, 0.2486373000, 0.6721361000", \ - "0.0524836000, 0.0569009000, 0.0670202000, 0.0863618000, 0.1283700000, 0.2574584000, 0.6739119000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0191061000, 0.0238782000, 0.0370420000, 0.0748446000, 0.1889927000, 0.5275296000, 1.5040951000", \ - "0.0190910000, 0.0238870000, 0.0370238000, 0.0748786000, 0.1891845000, 0.5279069000, 1.5043509000", \ - "0.0190544000, 0.0239577000, 0.0370137000, 0.0749812000, 0.1894830000, 0.5264183000, 1.5046248000", \ - "0.0194592000, 0.0244175000, 0.0375025000, 0.0751159000, 0.1893397000, 0.5273703000, 1.5084585000", \ - "0.0229446000, 0.0279020000, 0.0406156000, 0.0772312000, 0.1898613000, 0.5268199000, 1.5061217000", \ - "0.0305347000, 0.0355664000, 0.0481474000, 0.0826237000, 0.1916246000, 0.5257481000, 1.5053415000", \ - "0.0439978000, 0.0504179000, 0.0647528000, 0.0966815000, 0.1968761000, 0.5281535000, 1.4978270000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0840701000, 0.0887784000, 0.0994740000, 0.1223708000, 0.1702098000, 0.2841776000, 0.6031456000", \ - "0.0893311000, 0.0940393000, 0.1047191000, 0.1276628000, 0.1755217000, 0.2894864000, 0.6085444000", \ - "0.1025574000, 0.1071982000, 0.1178247000, 0.1406748000, 0.1885907000, 0.3024828000, 0.6221291000", \ - "0.1347469000, 0.1394145000, 0.1500172000, 0.1728944000, 0.2209640000, 0.3349252000, 0.6546297000", \ - "0.2030357000, 0.2082327000, 0.2198513000, 0.2440285000, 0.2931413000, 0.4075083000, 0.7264267000", \ - "0.3145453000, 0.3214297000, 0.3365483000, 0.3668389000, 0.4238277000, 0.5421912000, 0.8611492000", \ - "0.4939416000, 0.5029024000, 0.5226354000, 0.5621585000, 0.6354073000, 0.7651917000, 1.0846872000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0888665000, 0.0947658000, 0.1087394000, 0.1412499000, 0.2247041000, 0.4607264000, 1.1381507000", \ - "0.0928799000, 0.0988163000, 0.1127650000, 0.1452501000, 0.2285490000, 0.4637928000, 1.1446238000", \ - "0.1031337000, 0.1088382000, 0.1227987000, 0.1552780000, 0.2389992000, 0.4748270000, 1.1529525000", \ - "0.1273316000, 0.1332449000, 0.1470939000, 0.1793981000, 0.2627664000, 0.4977183000, 1.1760436000", \ - "0.1693400000, 0.1755434000, 0.1901689000, 0.2233677000, 0.3070686000, 0.5432856000, 1.2224711000", \ - "0.2196127000, 0.2271647000, 0.2440318000, 0.2791655000, 0.3633673000, 0.5993903000, 1.2786595000", \ - "0.2608649000, 0.2711688000, 0.2931045000, 0.3340457000, 0.4199974000, 0.6549012000, 1.3331137000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0167413000, 0.0202744000, 0.0285913000, 0.0490153000, 0.0974964000, 0.2384732000, 0.6673015000", \ - "0.0168137000, 0.0202802000, 0.0285541000, 0.0490916000, 0.0976134000, 0.2385064000, 0.6671055000", \ - "0.0167429000, 0.0202814000, 0.0285773000, 0.0490665000, 0.0974609000, 0.2387273000, 0.6653524000", \ - "0.0168060000, 0.0201775000, 0.0286869000, 0.0491727000, 0.0976677000, 0.2386680000, 0.6651415000", \ - "0.0214894000, 0.0246427000, 0.0330224000, 0.0524830000, 0.0994082000, 0.2385851000, 0.6674756000", \ - "0.0314192000, 0.0356810000, 0.0452974000, 0.0669545000, 0.1123012000, 0.2438986000, 0.6713156000", \ - "0.0474547000, 0.0528244000, 0.0646317000, 0.0918418000, 0.1405697000, 0.2596747000, 0.6694597000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0207732000, 0.0258164000, 0.0392707000, 0.0771698000, 0.1906160000, 0.5281555000, 1.5041468000", \ - "0.0207536000, 0.0258289000, 0.0393004000, 0.0771157000, 0.1903608000, 0.5277634000, 1.5027571000", \ - "0.0208029000, 0.0259079000, 0.0392689000, 0.0769020000, 0.1906616000, 0.5282924000, 1.5045573000", \ - "0.0208941000, 0.0258626000, 0.0393047000, 0.0769701000, 0.1901457000, 0.5260588000, 1.5030088000", \ - "0.0241444000, 0.0291418000, 0.0421016000, 0.0792362000, 0.1911485000, 0.5279922000, 1.5056468000", \ - "0.0321192000, 0.0370380000, 0.0489310000, 0.0832506000, 0.1931373000, 0.5275334000, 1.5055777000", \ - "0.0459399000, 0.0518251000, 0.0646975000, 0.0966106000, 0.1969958000, 0.5298628000, 1.4983514000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21a_4") { - leakage_power () { - value : 0.0051880000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0039272000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0037499000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0046044000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0039146000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0046044000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0026220000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0046044000; - when : "A1&A2&!B1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__o21a"; - cell_leakage_power : 0.0041518770; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0048480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081779000, 0.0081694000, 0.0081499000, 0.0081509000, 0.0081531000, 0.0081583000, 0.0081702000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008139400, -0.008136500, -0.008129700, -0.008131200, -0.008134600, -0.008142400, -0.008160400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050770000; - } - pin ("A2") { - capacitance : 0.0044330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075832000, 0.0075840000, 0.0075857000, 0.0075877000, 0.0075922000, 0.0076026000, 0.0076266000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007574500, -0.007573700, -0.007571700, -0.007573300, -0.007577100, -0.007585900, -0.007606200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047490000; - } - pin ("B1") { - capacitance : 0.0045100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093113000, 0.0093097000, 0.0093062000, 0.0093028000, 0.0092949000, 0.0092768000, 0.0092351000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004740500, -0.004749600, -0.004770600, -0.004747300, -0.004693700, -0.004570200, -0.004285500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046890000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0349028000, 0.0331402000, 0.0279697000, 0.0133849000, -0.038846400, -0.215411900, -0.780559600", \ - "0.0343731000, 0.0328957000, 0.0278629000, 0.0131828000, -0.039086500, -0.215625100, -0.780835900", \ - "0.0343512000, 0.0325940000, 0.0274996000, 0.0128293000, -0.039413500, -0.215928400, -0.781125400", \ - "0.0338105000, 0.0321305000, 0.0271300000, 0.0122806000, -0.039942800, -0.216308200, -0.781469200", \ - "0.0336993000, 0.0319363000, 0.0268497000, 0.0119352000, -0.040334100, -0.216731800, -0.781724400", \ - "0.0328575000, 0.0310351000, 0.0254072000, 0.0108969000, -0.040757900, -0.216987400, -0.781936400", \ - "0.0405978000, 0.0386626000, 0.0328660000, 0.0151461000, -0.040474700, -0.217009500, -0.781222000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0344488000, 0.0363426000, 0.0424278000, 0.0610558000, 0.1178451000, 0.2949718000, 0.8542011000", \ - "0.0341556000, 0.0361253000, 0.0422117000, 0.0608381000, 0.1176249000, 0.2948226000, 0.8540360000", \ - "0.0338866000, 0.0358399000, 0.0419299000, 0.0605367000, 0.1173418000, 0.2944585000, 0.8539235000", \ - "0.0336399000, 0.0355600000, 0.0415777000, 0.0601399000, 0.1168501000, 0.2940188000, 0.8535667000", \ - "0.0332854000, 0.0352010000, 0.0411113000, 0.0595469000, 0.1162195000, 0.2935417000, 0.8529137000", \ - "0.0340778000, 0.0358745000, 0.0415579000, 0.0595313000, 0.1155557000, 0.2921790000, 0.8515688000", \ - "0.0356085000, 0.0373480000, 0.0428863000, 0.0606354000, 0.1171346000, 0.2940427000, 0.8513857000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0305294000, 0.0287249000, 0.0236549000, 0.0087595000, -0.043442400, -0.219717000, -0.784948000", \ - "0.0299549000, 0.0283017000, 0.0231859000, 0.0084876000, -0.043691600, -0.220044300, -0.785196600", \ - "0.0297775000, 0.0279660000, 0.0228584000, 0.0081665000, -0.044066300, -0.220469500, -0.785549800", \ - "0.0293841000, 0.0276790000, 0.0225608000, 0.0078522000, -0.044409000, -0.220781500, -0.785836000", \ - "0.0291426000, 0.0273972000, 0.0222902000, 0.0073664000, -0.044507000, -0.221106900, -0.786117800", \ - "0.0292481000, 0.0275666000, 0.0221533000, 0.0071859000, -0.044924500, -0.221091700, -0.785780000", \ - "0.0393491000, 0.0373496000, 0.0311361000, 0.0131061000, -0.042714600, -0.218760900, -0.783506900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0312794000, 0.0331467000, 0.0392206000, 0.0579581000, 0.1148050000, 0.2915096000, 0.8511920000", \ - "0.0311978000, 0.0331274000, 0.0391970000, 0.0579636000, 0.1147774000, 0.2915987000, 0.8478284000", \ - "0.0309205000, 0.0328365000, 0.0389439000, 0.0576620000, 0.1145166000, 0.2918043000, 0.8483428000", \ - "0.0304083000, 0.0323401000, 0.0383697000, 0.0569140000, 0.1137636000, 0.2910374000, 0.8469606000", \ - "0.0300034000, 0.0318251000, 0.0378375000, 0.0562372000, 0.1126580000, 0.2902981000, 0.8516763000", \ - "0.0305780000, 0.0323726000, 0.0380586000, 0.0560480000, 0.1121007000, 0.2887010000, 0.8500587000", \ - "0.0323767000, 0.0341036000, 0.0396439000, 0.0573750000, 0.1134528000, 0.2903706000, 0.8473345000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0247369000, 0.0235843000, 0.0195587000, 0.0055707000, -0.047762100, -0.225504900, -0.791192600", \ - "0.0243170000, 0.0231739000, 0.0192000000, 0.0051222000, -0.048084200, -0.225828100, -0.791494100", \ - "0.0238650000, 0.0226560000, 0.0186428000, 0.0045288000, -0.048637200, -0.226316800, -0.792003500", \ - "0.0232073000, 0.0219989000, 0.0179122000, 0.0036897000, -0.049367400, -0.226890300, -0.792496900", \ - "0.0231594000, 0.0217689000, 0.0174918000, 0.0031894000, -0.049670300, -0.226773300, -0.792312900", \ - "0.0284098000, 0.0265827000, 0.0210866000, 0.0036738000, -0.049671400, -0.226627100, -0.791915200", \ - "0.0333419000, 0.0314218000, 0.0255302000, 0.0076895000, -0.048017900, -0.225374300, -0.790040200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015863440, 0.0050329770, 0.0159680700, 0.0506617200, 0.1607339000, 0.5099586000"); - values("0.0314506000, 0.0333302000, 0.0394235000, 0.0580362000, 0.1149053000, 0.2921032000, 0.8513946000", \ - "0.0312377000, 0.0332098000, 0.0391923000, 0.0578483000, 0.1147157000, 0.2918835000, 0.8519878000", \ - "0.0309177000, 0.0328472000, 0.0389526000, 0.0575845000, 0.1143825000, 0.2916041000, 0.8509636000", \ - "0.0306130000, 0.0324885000, 0.0384521000, 0.0568931000, 0.1136168000, 0.2907188000, 0.8510610000", \ - "0.0303449000, 0.0322732000, 0.0381762000, 0.0560965000, 0.1124882000, 0.2901295000, 0.8503830000", \ - "0.0311608000, 0.0329620000, 0.0386072000, 0.0563998000, 0.1120234000, 0.2888569000, 0.8520636000", \ - "0.0333226000, 0.0350483000, 0.0405597000, 0.0580158000, 0.1141196000, 0.2907186000, 0.8485613000"); - } - } - max_capacitance : 0.5099590000; - max_transition : 1.5044210000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.1794242000, 0.1833074000, 0.1932474000, 0.2152595000, 0.2612872000, 0.3675630000, 0.6715705000", \ - "0.1845851000, 0.1884811000, 0.1984325000, 0.2203748000, 0.2662723000, 0.3727826000, 0.6763995000", \ - "0.1971462000, 0.2010235000, 0.2110096000, 0.2330001000, 0.2790358000, 0.3853597000, 0.6888844000", \ - "0.2242279000, 0.2281207000, 0.2380838000, 0.2600631000, 0.3061917000, 0.4127133000, 0.7165839000", \ - "0.2855375000, 0.2894339000, 0.2993225000, 0.3212597000, 0.3672074000, 0.4740194000, 0.7775355000", \ - "0.4067305000, 0.4110992000, 0.4221781000, 0.4461673000, 0.4956328000, 0.6044996000, 0.9090384000", \ - "0.6166190000, 0.6219832000, 0.6356252000, 0.6643857000, 0.7202821000, 0.8368277000, 1.1410498000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0918284000, 0.0956384000, 0.1060552000, 0.1326806000, 0.2057754000, 0.4299661000, 1.1327927000", \ - "0.0962322000, 0.1000703000, 0.1104946000, 0.1371346000, 0.2102197000, 0.4344053000, 1.1371009000", \ - "0.1055927000, 0.1094960000, 0.1198841000, 0.1465217000, 0.2195638000, 0.4436351000, 1.1467938000", \ - "0.1256645000, 0.1294807000, 0.1398490000, 0.1664581000, 0.2394696000, 0.4634778000, 1.1668773000", \ - "0.1614973000, 0.1656273000, 0.1765301000, 0.2039067000, 0.2773710000, 0.5018066000, 1.2047752000", \ - "0.2073992000, 0.2122812000, 0.2246534000, 0.2539609000, 0.3286876000, 0.5519538000, 1.2585022000", \ - "0.2420341000, 0.2485088000, 0.2644797000, 0.2996433000, 0.3777444000, 0.6013403000, 1.3048087000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0270151000, 0.0292594000, 0.0352753000, 0.0502974000, 0.0903679000, 0.2103345000, 0.6138639000", \ - "0.0273606000, 0.0293203000, 0.0358181000, 0.0502917000, 0.0904944000, 0.2104127000, 0.6114365000", \ - "0.0270136000, 0.0292738000, 0.0354196000, 0.0504199000, 0.0903610000, 0.2103981000, 0.6112896000", \ - "0.0272046000, 0.0294401000, 0.0355469000, 0.0504219000, 0.0903436000, 0.2103777000, 0.6118739000", \ - "0.0271586000, 0.0293896000, 0.0353721000, 0.0508849000, 0.0904274000, 0.2104373000, 0.6106762000", \ - "0.0327694000, 0.0352907000, 0.0410132000, 0.0568550000, 0.0956348000, 0.2131264000, 0.6138424000", \ - "0.0453802000, 0.0476535000, 0.0548346000, 0.0708017000, 0.1101975000, 0.2243486000, 0.6139343000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0210057000, 0.0244143000, 0.0342651000, 0.0643234000, 0.1626311000, 0.4838848000, 1.5011893000", \ - "0.0210205000, 0.0244197000, 0.0342405000, 0.0642629000, 0.1626285000, 0.4838946000, 1.5010634000", \ - "0.0210512000, 0.0244120000, 0.0342425000, 0.0643404000, 0.1625084000, 0.4838784000, 1.5011247000", \ - "0.0211060000, 0.0244514000, 0.0342654000, 0.0644369000, 0.1625435000, 0.4838359000, 1.5011641000", \ - "0.0236412000, 0.0269859000, 0.0367336000, 0.0662502000, 0.1635368000, 0.4837685000, 1.5011568000", \ - "0.0296821000, 0.0330465000, 0.0432511000, 0.0709208000, 0.1653566000, 0.4819817000, 1.5003772000", \ - "0.0419511000, 0.0458914000, 0.0565707000, 0.0835526000, 0.1702403000, 0.4835568000, 1.4945181000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.1629001000, 0.1667835000, 0.1767070000, 0.1988171000, 0.2447848000, 0.3509430000, 0.6547117000", \ - "0.1669428000, 0.1708396000, 0.1807852000, 0.2028017000, 0.2488832000, 0.3551968000, 0.6587268000", \ - "0.1777025000, 0.1815534000, 0.1914972000, 0.2135167000, 0.2596185000, 0.3659711000, 0.6697596000", \ - "0.2061578000, 0.2100685000, 0.2200166000, 0.2420078000, 0.2879404000, 0.3945712000, 0.6987067000", \ - "0.2751042000, 0.2790180000, 0.2889020000, 0.3107205000, 0.3564044000, 0.4633104000, 0.7669959000", \ - "0.4145607000, 0.4192351000, 0.4309026000, 0.4552873000, 0.5038420000, 0.6126850000, 0.9161629000", \ - "0.6408246000, 0.6468981000, 0.6622714000, 0.6944760000, 0.7523265000, 0.8662150000, 1.1725843000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0856212000, 0.0895050000, 0.1001278000, 0.1272672000, 0.2004477000, 0.4236371000, 1.1304541000", \ - "0.0901740000, 0.0941451000, 0.1047548000, 0.1318821000, 0.2052042000, 0.4282820000, 1.1327043000", \ - "0.0988489000, 0.1027721000, 0.1134161000, 0.1405163000, 0.2137782000, 0.4367532000, 1.1409593000", \ - "0.1165524000, 0.1204852000, 0.1311069000, 0.1581384000, 0.2314838000, 0.4553698000, 1.1569835000", \ - "0.1457895000, 0.1500709000, 0.1613796000, 0.1893901000, 0.2632160000, 0.4868777000, 1.1932122000", \ - "0.1798477000, 0.1849600000, 0.1978663000, 0.2281626000, 0.3035026000, 0.5274052000, 1.2312900000", \ - "0.1928019000, 0.1996217000, 0.2167523000, 0.2536663000, 0.3330297000, 0.5567531000, 1.2600262000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0270509000, 0.0292771000, 0.0354355000, 0.0504688000, 0.0904032000, 0.2100605000, 0.6132257000", \ - "0.0272395000, 0.0294727000, 0.0354614000, 0.0503279000, 0.0903970000, 0.2103326000, 0.6132346000", \ - "0.0273040000, 0.0294473000, 0.0354679000, 0.0502804000, 0.0903407000, 0.2104927000, 0.6113732000", \ - "0.0270869000, 0.0293886000, 0.0355313000, 0.0502944000, 0.0904686000, 0.2105812000, 0.6127315000", \ - "0.0270877000, 0.0293902000, 0.0354704000, 0.0502345000, 0.0907141000, 0.2106436000, 0.6118317000", \ - "0.0366343000, 0.0391440000, 0.0455119000, 0.0588236000, 0.0956770000, 0.2133078000, 0.6119781000", \ - "0.0538691000, 0.0569584000, 0.0646356000, 0.0803821000, 0.1146534000, 0.2242430000, 0.6151942000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0212409000, 0.0246061000, 0.0346018000, 0.0648250000, 0.1626774000, 0.4837908000, 1.5018164000", \ - "0.0213390000, 0.0247041000, 0.0346230000, 0.0647600000, 0.1629866000, 0.4830731000, 1.4990253000", \ - "0.0213363000, 0.0247184000, 0.0346251000, 0.0647693000, 0.1628629000, 0.4827345000, 1.4998432000", \ - "0.0217105000, 0.0250423000, 0.0350719000, 0.0649471000, 0.1630079000, 0.4837510000, 1.4995671000", \ - "0.0245645000, 0.0279725000, 0.0376876000, 0.0672699000, 0.1636668000, 0.4827794000, 1.5044208000", \ - "0.0313618000, 0.0347590000, 0.0447659000, 0.0728697000, 0.1662895000, 0.4820174000, 1.4990331000", \ - "0.0447700000, 0.0489775000, 0.0598782000, 0.0867364000, 0.1728573000, 0.4842042000, 1.4982131000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0855756000, 0.0886027000, 0.0964216000, 0.1149069000, 0.1572844000, 0.2597968000, 0.5614166000", \ - "0.0908521000, 0.0937988000, 0.1016540000, 0.1201948000, 0.1626319000, 0.2651681000, 0.5668795000", \ - "0.1040908000, 0.1069987000, 0.1148100000, 0.1333453000, 0.1758474000, 0.2783760000, 0.5807209000", \ - "0.1363760000, 0.1393249000, 0.1471042000, 0.1655543000, 0.2081372000, 0.3108306000, 0.6130395000", \ - "0.2052914000, 0.2086408000, 0.2172657000, 0.2370345000, 0.2807059000, 0.3829769000, 0.6852152000", \ - "0.3201192000, 0.3244230000, 0.3356884000, 0.3603286000, 0.4115334000, 0.5202398000, 0.8219033000", \ - "0.5077440000, 0.5133734000, 0.5273012000, 0.5596177000, 0.6254853000, 0.7485467000, 1.0535538000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0848856000, 0.0886865000, 0.0991085000, 0.1257663000, 0.1989082000, 0.4231330000, 1.1259795000", \ - "0.0889653000, 0.0928212000, 0.1031696000, 0.1299097000, 0.2032000000, 0.4264813000, 1.1300901000", \ - "0.0987954000, 0.1026995000, 0.1131106000, 0.1397295000, 0.2128038000, 0.4370223000, 1.1400469000", \ - "0.1228097000, 0.1265942000, 0.1369288000, 0.1633827000, 0.2365166000, 0.4596065000, 1.1643687000", \ - "0.1609926000, 0.1650354000, 0.1758623000, 0.2030252000, 0.2763443000, 0.4998935000, 1.2046936000", \ - "0.2049994000, 0.2099421000, 0.2224707000, 0.2510384000, 0.3249547000, 0.5493651000, 1.2530784000", \ - "0.2327299000, 0.2393742000, 0.2556191000, 0.2904473000, 0.3664199000, 0.5894520000, 1.2936808000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0172841000, 0.0191860000, 0.0251101000, 0.0411605000, 0.0828023000, 0.2033193000, 0.6088952000", \ - "0.0172002000, 0.0193430000, 0.0251820000, 0.0411585000, 0.0827912000, 0.2032008000, 0.6081589000", \ - "0.0171893000, 0.0193170000, 0.0249370000, 0.0411120000, 0.0826956000, 0.2032227000, 0.6080784000", \ - "0.0171680000, 0.0194030000, 0.0250454000, 0.0411802000, 0.0826515000, 0.2029703000, 0.6078531000", \ - "0.0216619000, 0.0237078000, 0.0293331000, 0.0443694000, 0.0844567000, 0.2041599000, 0.6075128000", \ - "0.0323305000, 0.0345872000, 0.0415477000, 0.0577726000, 0.0979837000, 0.2102534000, 0.6082649000", \ - "0.0487041000, 0.0518258000, 0.0605436000, 0.0806460000, 0.1264223000, 0.2298852000, 0.6118550000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015863400, 0.0050329800, 0.0159681000, 0.0506617000, 0.1607340000, 0.5099590000"); - values("0.0210194000, 0.0244297000, 0.0342620000, 0.0643472000, 0.1626461000, 0.4838970000, 1.5011384000", \ - "0.0209664000, 0.0242673000, 0.0342460000, 0.0643709000, 0.1628384000, 0.4833194000, 1.4978221000", \ - "0.0210599000, 0.0243856000, 0.0342183000, 0.0643046000, 0.1625693000, 0.4839160000, 1.5011040000", \ - "0.0212124000, 0.0245385000, 0.0343286000, 0.0644579000, 0.1627965000, 0.4822261000, 1.4999936000", \ - "0.0241496000, 0.0272303000, 0.0369356000, 0.0666993000, 0.1634964000, 0.4828467000, 1.5006046000", \ - "0.0316699000, 0.0349237000, 0.0435945000, 0.0710406000, 0.1655318000, 0.4821830000, 1.4992791000", \ - "0.0449280000, 0.0489921000, 0.0589535000, 0.0842841000, 0.1706999000, 0.4841962000, 1.4951113000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ai_0") { - leakage_power () { - value : 0.0006167000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 6.4139476e-05; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0023595000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0003568000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0025649000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0003567000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0016325000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0003568000; - when : "A1&A2&!B1"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__o21ai"; - cell_leakage_power : 0.0010385090; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0017470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029027000, 0.0029025000, 0.0029019000, 0.0029015000, 0.0029004000, 0.0028981000, 0.0028927000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002911200, -0.002903600, -0.002886200, -0.002886900, -0.002888600, -0.002892500, -0.002901600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018180000; - } - pin ("A2") { - capacitance : 0.0017060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028299000, 0.0028267000, 0.0028194000, 0.0028194000, 0.0028196000, 0.0028199000, 0.0028207000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002819000, -0.002817400, -0.002814000, -0.002813900, -0.002813800, -0.002813600, -0.002813000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018090000; - } - pin ("B1") { - capacitance : 0.0016580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0035057000, 0.0035047000, 0.0035023000, 0.0035017000, 0.0035003000, 0.0034970000, 0.0034894000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001929900, -0.001936400, -0.001951200, -0.001942600, -0.001922600, -0.001876700, -0.001770900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016950000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0026146000, 0.0016789000, -0.000330600, -0.004660200, -0.014028800, -0.034312000, -0.078047800", \ - "0.0025198000, 0.0015986000, -0.000398000, -0.004731600, -0.014105200, -0.034358500, -0.078100000", \ - "0.0023930000, 0.0014842000, -0.000499200, -0.004812400, -0.014173900, -0.034425300, -0.078150300", \ - "0.0022777000, 0.0013741000, -0.000605000, -0.004889000, -0.014228400, -0.034448700, -0.078172800", \ - "0.0022947000, 0.0013138000, -0.000681300, -0.004972600, -0.014273800, -0.034487100, -0.078185200", \ - "0.0023559000, 0.0014340000, -0.000575200, -0.004931600, -0.014380200, -0.034567500, -0.078225900", \ - "0.0028140000, 0.0018620000, -0.000226600, -0.004641500, -0.014091000, -0.034477200, -0.078193300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0077185000, 0.0086568000, 0.0106860000, 0.0150267000, 0.0243651000, 0.0444061000, 0.0875928000", \ - "0.0076128000, 0.0085715000, 0.0106072000, 0.0149635000, 0.0243171000, 0.0443591000, 0.0875636000", \ - "0.0075006000, 0.0084525000, 0.0105091000, 0.0148850000, 0.0242394000, 0.0443211000, 0.0875315000", \ - "0.0074061000, 0.0083555000, 0.0104032000, 0.0147995000, 0.0241906000, 0.0442995000, 0.0874675000", \ - "0.0073371000, 0.0083019000, 0.0103457000, 0.0147453000, 0.0240810000, 0.0442047000, 0.0874182000", \ - "0.0073024000, 0.0082441000, 0.0103006000, 0.0146609000, 0.0241117000, 0.0442004000, 0.0873998000", \ - "0.0075752000, 0.0084700000, 0.0104180000, 0.0146652000, 0.0242036000, 0.0442780000, 0.0874934000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0018067000, 0.0009012000, -0.001078300, -0.005405400, -0.014792600, -0.035071400, -0.078835200", \ - "0.0017004000, 0.0008338000, -0.001115300, -0.005409300, -0.014772300, -0.035035800, -0.078790700", \ - "0.0015119000, 0.0006700000, -0.001234200, -0.005478900, -0.014794700, -0.035039700, -0.078774600", \ - "0.0013004000, 0.0004463000, -0.001447300, -0.005637200, -0.014896700, -0.035088700, -0.078790100", \ - "0.0012804000, 0.0003747000, -0.001609700, -0.005832200, -0.015051000, -0.035177200, -0.078836400", \ - "0.0012942000, 0.0003884000, -0.001606400, -0.005902800, -0.015258800, -0.035359200, -0.078937100", \ - "0.0018352000, 0.0008582000, -0.001270100, -0.005684100, -0.015124800, -0.035422900, -0.079043000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0062043000, 0.0071586000, 0.0091984000, 0.0135690000, 0.0228985000, 0.0429268000, 0.0861631000", \ - "0.0060657000, 0.0070356000, 0.0090938000, 0.0134502000, 0.0228208000, 0.0428952000, 0.0860804000", \ - "0.0058806000, 0.0068580000, 0.0089192000, 0.0133295000, 0.0227732000, 0.0428377000, 0.0860095000", \ - "0.0057585000, 0.0067167000, 0.0087815000, 0.0131890000, 0.0226036000, 0.0427525000, 0.0860264000", \ - "0.0057701000, 0.0066999000, 0.0087415000, 0.0130879000, 0.0224661000, 0.0426260000, 0.0858456000", \ - "0.0060328000, 0.0069463000, 0.0089344000, 0.0132107000, 0.0224968000, 0.0425051000, 0.0857443000", \ - "0.0069006000, 0.0078588000, 0.0096533000, 0.0139472000, 0.0232119000, 0.0432572000, 0.0858050000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0016815000, 0.0007904000, -0.001178100, -0.005477300, -0.014837900, -0.035097900, -0.078813900", \ - "0.0015852000, 0.0006811000, -0.001258300, -0.005525000, -0.014857100, -0.035094900, -0.078817600", \ - "0.0014345000, 0.0005579000, -0.001392800, -0.005619600, -0.014917100, -0.035123600, -0.078821500", \ - "0.0012576000, 0.0003767000, -0.001565600, -0.005786100, -0.015068800, -0.035205200, -0.078867400", \ - "0.0012054000, 0.0002893000, -0.001689400, -0.005967400, -0.015215100, -0.035347100, -0.078964300", \ - "0.0015187000, 0.0005534000, -0.001500600, -0.005896800, -0.015314900, -0.035475400, -0.079098400", \ - "0.0024392000, 0.0013871000, -0.000754800, -0.005305800, -0.014764600, -0.035385500, -0.079164000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264120, 0.0050181660, 0.0108243900, 0.0233486500, 0.0503639900"); - values("0.0045366000, 0.0055672000, 0.0076883000, 0.0120792000, 0.0214398000, 0.0414467000, 0.0845862000", \ - "0.0043706000, 0.0054141000, 0.0075763000, 0.0119874000, 0.0213539000, 0.0414703000, 0.0846191000", \ - "0.0042052000, 0.0052224000, 0.0073128000, 0.0118169000, 0.0212644000, 0.0413851000, 0.0846303000", \ - "0.0041052000, 0.0050708000, 0.0071598000, 0.0116003000, 0.0210554000, 0.0412098000, 0.0843918000", \ - "0.0041898000, 0.0051149000, 0.0071863000, 0.0115062000, 0.0208244000, 0.0411288000, 0.0838843000", \ - "0.0044015000, 0.0053859000, 0.0075625000, 0.0118208000, 0.0210233000, 0.0408800000, 0.0842573000", \ - "0.0057047000, 0.0064496000, 0.0082059000, 0.0125009000, 0.0214387000, 0.0414769000, 0.0849115000"); - } - } - max_capacitance : 0.0503640000; - max_transition : 1.4843140000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0436490000, 0.0495469000, 0.0616037000, 0.0871112000, 0.1412386000, 0.2569616000, 0.5057608000", \ - "0.0482914000, 0.0540965000, 0.0662570000, 0.0918149000, 0.1458842000, 0.2617472000, 0.5102848000", \ - "0.0580325000, 0.0639239000, 0.0761485000, 0.1017791000, 0.1560266000, 0.2718948000, 0.5212040000", \ - "0.0766947000, 0.0835814000, 0.0967656000, 0.1229501000, 0.1773701000, 0.2933616000, 0.5423204000", \ - "0.1052199000, 0.1145394000, 0.1327040000, 0.1653298000, 0.2254060000, 0.3423264000, 0.5917594000", \ - "0.1377645000, 0.1530298000, 0.1807592000, 0.2299330000, 0.3115596000, 0.4491964000, 0.7056271000", \ - "0.1600048000, 0.1832382000, 0.2279469000, 0.3053224000, 0.4325055000, 0.6297551000, 0.9460914000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0901964000, 0.1023199000, 0.1286690000, 0.1842828000, 0.3033011000, 0.5587113000, 1.1080346000", \ - "0.0951948000, 0.1074794000, 0.1340034000, 0.1897490000, 0.3089096000, 0.5645181000, 1.1136404000", \ - "0.1070936000, 0.1193924000, 0.1458601000, 0.2022283000, 0.3213622000, 0.5769431000, 1.1263223000", \ - "0.1327502000, 0.1450721000, 0.1714326000, 0.2275834000, 0.3471835000, 0.6030398000, 1.1534889000", \ - "0.1842171000, 0.1991228000, 0.2283995000, 0.2854895000, 0.4050127000, 0.6609737000, 1.2115867000", \ - "0.2693001000, 0.2907251000, 0.3302361000, 0.4035000000, 0.5382927000, 0.7952084000, 1.3463551000", \ - "0.4056318000, 0.4366866000, 0.4967218000, 0.6031790000, 0.7851442000, 1.0944748000, 1.6543490000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0301504000, 0.0374475000, 0.0529754000, 0.0864064000, 0.1585125000, 0.3126197000, 0.6466603000", \ - "0.0300923000, 0.0373355000, 0.0528810000, 0.0863711000, 0.1584118000, 0.3132538000, 0.6468118000", \ - "0.0302498000, 0.0373164000, 0.0528391000, 0.0862933000, 0.1585150000, 0.3131846000, 0.6478661000", \ - "0.0365011000, 0.0428306000, 0.0564693000, 0.0878992000, 0.1581149000, 0.3129277000, 0.6475223000", \ - "0.0539438000, 0.0611936000, 0.0764527000, 0.1055058000, 0.1677334000, 0.3151845000, 0.6483672000", \ - "0.0901895000, 0.0999559000, 0.1192483000, 0.1546331000, 0.2186766000, 0.3481432000, 0.6542841000", \ - "0.1573385000, 0.1727827000, 0.2000500000, 0.2490070000, 0.3300538000, 0.4739658000, 0.7520092000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0713990000, 0.0876398000, 0.1227914000, 0.1976577000, 0.3596843000, 0.7090999000, 1.4617978000", \ - "0.0713589000, 0.0876369000, 0.1228039000, 0.1977088000, 0.3597438000, 0.7088605000, 1.4619128000", \ - "0.0713544000, 0.0875971000, 0.1225973000, 0.1983581000, 0.3592818000, 0.7087852000, 1.4604564000", \ - "0.0724413000, 0.0879195000, 0.1225641000, 0.1978812000, 0.3599478000, 0.7091610000, 1.4594815000", \ - "0.0897458000, 0.1043552000, 0.1345012000, 0.2037099000, 0.3603660000, 0.7087931000, 1.4614225000", \ - "0.1314061000, 0.1484393000, 0.1822533000, 0.2481951000, 0.3871730000, 0.7125303000, 1.4613132000", \ - "0.2149693000, 0.2370327000, 0.2801162000, 0.3584362000, 0.5053753000, 0.7951551000, 1.4798190000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0343842000, 0.0396189000, 0.0506527000, 0.0737989000, 0.1242194000, 0.2343878000, 0.4636627000", \ - "0.0389537000, 0.0442939000, 0.0554245000, 0.0787548000, 0.1287721000, 0.2371769000, 0.4679994000", \ - "0.0481582000, 0.0536923000, 0.0650562000, 0.0889139000, 0.1397719000, 0.2477161000, 0.4782937000", \ - "0.0631867000, 0.0703485000, 0.0842924000, 0.1096610000, 0.1605467000, 0.2699155000, 0.5005524000", \ - "0.0817333000, 0.0929690000, 0.1138623000, 0.1481063000, 0.2080056000, 0.3181691000, 0.5517035000", \ - "0.0964391000, 0.1144305000, 0.1474654000, 0.2009939000, 0.2872920000, 0.4230604000, 0.6661839000", \ - "0.0834065000, 0.1143334000, 0.1664923000, 0.2538834000, 0.3889402000, 0.5905442000, 0.9013650000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0784626000, 0.0909055000, 0.1174909000, 0.1732014000, 0.2922046000, 0.5478493000, 1.0971752000", \ - "0.0819515000, 0.0945067000, 0.1211656000, 0.1772520000, 0.2962913000, 0.5518794000, 1.1016664000", \ - "0.0921697000, 0.1047104000, 0.1311261000, 0.1877541000, 0.3073894000, 0.5632830000, 1.1134342000", \ - "0.1204817000, 0.1328172000, 0.1591975000, 0.2156296000, 0.3357049000, 0.5919783000, 1.1419398000", \ - "0.1813785000, 0.1970938000, 0.2264538000, 0.2822367000, 0.4014453000, 0.6576322000, 1.2084965000", \ - "0.2777073000, 0.3018108000, 0.3470572000, 0.4267618000, 0.5588200000, 0.8119693000, 1.3609422000", \ - "0.4326880000, 0.4697477000, 0.5381379000, 0.6585262000, 0.8611430000, 1.1743526000, 1.7185852000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0202737000, 0.0268759000, 0.0413774000, 0.0721997000, 0.1390982000, 0.2854241000, 0.5942348000", \ - "0.0202355000, 0.0270123000, 0.0413673000, 0.0722146000, 0.1391846000, 0.2830597000, 0.5928624000", \ - "0.0212453000, 0.0275243000, 0.0415492000, 0.0724819000, 0.1397417000, 0.2847607000, 0.5978730000", \ - "0.0293519000, 0.0352466000, 0.0478510000, 0.0753855000, 0.1394663000, 0.2838008000, 0.5941679000", \ - "0.0481230000, 0.0554316000, 0.0700430000, 0.0966884000, 0.1524987000, 0.2861138000, 0.6004303000", \ - "0.0843080000, 0.0944089000, 0.1141817000, 0.1480717000, 0.2075343000, 0.3272329000, 0.6083431000", \ - "0.1544036000, 0.1685860000, 0.1959194000, 0.2433064000, 0.3221091000, 0.4565990000, 0.7136159000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0712012000, 0.0874553000, 0.1223644000, 0.1979550000, 0.3595213000, 0.7082481000, 1.4606076000", \ - "0.0712047000, 0.0874609000, 0.1224929000, 0.1984626000, 0.3593482000, 0.7084312000, 1.4609612000", \ - "0.0712444000, 0.0875782000, 0.1223909000, 0.1979139000, 0.3598161000, 0.7087659000, 1.4608733000", \ - "0.0741651000, 0.0888802000, 0.1225220000, 0.1977227000, 0.3599120000, 0.7086544000, 1.4616099000", \ - "0.1012434000, 0.1144389000, 0.1414968000, 0.2060893000, 0.3595809000, 0.7090534000, 1.4656372000", \ - "0.1539361000, 0.1737543000, 0.2099259000, 0.2729428000, 0.3978294000, 0.7133099000, 1.4611383000", \ - "0.2392376000, 0.2685213000, 0.3266396000, 0.4179388000, 0.5659103000, 0.8276886000, 1.4843142000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0370172000, 0.0429432000, 0.0553835000, 0.0809910000, 0.1352077000, 0.2509869000, 0.4998730000", \ - "0.0409376000, 0.0469908000, 0.0594156000, 0.0851784000, 0.1396266000, 0.2554770000, 0.5042483000", \ - "0.0512235000, 0.0571671000, 0.0693900000, 0.0952874000, 0.1498122000, 0.2659399000, 0.5148138000", \ - "0.0717807000, 0.0793671000, 0.0936955000, 0.1199572000, 0.1739486000, 0.2907130000, 0.5397469000", \ - "0.0984989000, 0.1099933000, 0.1316271000, 0.1696546000, 0.2324511000, 0.3480737000, 0.5972538000", \ - "0.1265547000, 0.1437625000, 0.1767736000, 0.2347326000, 0.3309359000, 0.4796246000, 0.7303014000", \ - "0.1434929000, 0.1697120000, 0.2191828000, 0.3075885000, 0.4525756000, 0.6793692000, 1.0249919000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0293638000, 0.0356612000, 0.0485600000, 0.0756354000, 0.1327393000, 0.2553406000, 0.5201094000", \ - "0.0345536000, 0.0408496000, 0.0537833000, 0.0810133000, 0.1395615000, 0.2620857000, 0.5251943000", \ - "0.0478290000, 0.0539083000, 0.0665873000, 0.0938997000, 0.1515278000, 0.2740701000, 0.5384653000", \ - "0.0729704000, 0.0820910000, 0.0979339000, 0.1252241000, 0.1826197000, 0.3052347000, 0.5687221000", \ - "0.1115117000, 0.1263564000, 0.1517048000, 0.1926359000, 0.2551768000, 0.3774305000, 0.6402085000", \ - "0.1712993000, 0.1949414000, 0.2365501000, 0.3035071000, 0.4030221000, 0.5502460000, 0.8097813000", \ - "0.2681894000, 0.3045884000, 0.3675332000, 0.4732022000, 0.6388763000, 0.8751698000, 1.2051345000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0301383000, 0.0373865000, 0.0530168000, 0.0863600000, 0.1583972000, 0.3144443000, 0.6466855000", \ - "0.0301128000, 0.0374270000, 0.0529161000, 0.0862745000, 0.1585355000, 0.3127465000, 0.6465596000", \ - "0.0306421000, 0.0375522000, 0.0526194000, 0.0861244000, 0.1584546000, 0.3131684000, 0.6461301000", \ - "0.0422715000, 0.0492361000, 0.0608785000, 0.0900985000, 0.1580298000, 0.3132735000, 0.6472217000", \ - "0.0659815000, 0.0749904000, 0.0913718000, 0.1215078000, 0.1769250000, 0.3163814000, 0.6473820000", \ - "0.1075074000, 0.1210394000, 0.1461672000, 0.1875948000, 0.2558271000, 0.3728904000, 0.6609624000", \ - "0.1787290000, 0.2012159000, 0.2374143000, 0.2999501000, 0.4029098000, 0.5577397000, 0.8143225000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010785200, 0.0023264100, 0.0050181700, 0.0108244000, 0.0233486000, 0.0503640000"); - values("0.0325444000, 0.0416005000, 0.0605810000, 0.0997379000, 0.1811897000, 0.3553317000, 0.7314158000", \ - "0.0325500000, 0.0415310000, 0.0605735000, 0.0997502000, 0.1815036000, 0.3553188000, 0.7301158000", \ - "0.0350243000, 0.0428541000, 0.0605584000, 0.0997559000, 0.1811466000, 0.3552158000, 0.7331827000", \ - "0.0531846000, 0.0574072000, 0.0704203000, 0.1030229000, 0.1811758000, 0.3554500000, 0.7317689000", \ - "0.0908905000, 0.0972897000, 0.1102120000, 0.1342412000, 0.1962020000, 0.3559003000, 0.7317399000", \ - "0.1525316000, 0.1626079000, 0.1820162000, 0.2171189000, 0.2757479000, 0.3989175000, 0.7360952000", \ - "0.2510516000, 0.2681264000, 0.3006811000, 0.3587374000, 0.4482859000, 0.5880856000, 0.8527456000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ai_1") { - leakage_power () { - value : 0.0005413000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 5.8967899e-05; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0028398000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0003116000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0029319000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0003116000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0010667000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0003116000; - when : "A1&A2&!B1"; - } - area : 5.0048000000; - cell_footprint : "sky130_fd_sc_hd__o21ai"; - cell_leakage_power : 0.0010466900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040070000, 0.0040018000, 0.0039898000, 0.0039883000, 0.0039850000, 0.0039774000, 0.0039599000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003977900, -0.003976300, -0.003972500, -0.003971700, -0.003969800, -0.003965400, -0.003955400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024370000; - } - pin ("A2") { - capacitance : 0.0024590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042431000, 0.0042424000, 0.0042410000, 0.0042402000, 0.0042385000, 0.0042344000, 0.0042252000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004245300, -0.004242900, -0.004237600, -0.004237400, -0.004237100, -0.004236300, -0.004234500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026170000; - } - pin ("B1") { - capacitance : 0.0019960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0019750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038374000, 0.0038377000, 0.0038383000, 0.0038382000, 0.0038380000, 0.0038376000, 0.0038366000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001632200, -0.001642000, -0.001664700, -0.001652400, -0.001624200, -0.001559300, -0.001409500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020180000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0041742000, 0.0031045000, 0.0006145000, -0.005235300, -0.018883300, -0.050807800, -0.125329800", \ - "0.0040490000, 0.0029875000, 0.0004995000, -0.005321300, -0.018974100, -0.050884900, -0.125413300", \ - "0.0038734000, 0.0028238000, 0.0003615000, -0.005437200, -0.019058000, -0.050958600, -0.125464500", \ - "0.0036734000, 0.0026251000, 0.0002004000, -0.005575200, -0.019160100, -0.051019400, -0.125517400", \ - "0.0037412000, 0.0026704000, 0.0001093000, -0.005684700, -0.019219300, -0.051048800, -0.125522600", \ - "0.0038101000, 0.0027455000, 0.0002417000, -0.005634300, -0.019379400, -0.051184500, -0.125623600", \ - "0.0047928000, 0.0036442000, 0.0010479000, -0.004986700, -0.018820000, -0.050990500, -0.125549500"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0105737000, 0.0116650000, 0.0141870000, 0.0200376000, 0.0336439000, 0.0652198000, 0.1388122000", \ - "0.0104286000, 0.0115306000, 0.0140737000, 0.0199546000, 0.0335682000, 0.0651672000, 0.1388836000", \ - "0.0102732000, 0.0113797000, 0.0139503000, 0.0198681000, 0.0335277000, 0.0651690000, 0.1387822000", \ - "0.0101376000, 0.0112444000, 0.0137869000, 0.0197119000, 0.0333786000, 0.0650459000, 0.1386714000", \ - "0.0100592000, 0.0111596000, 0.0137232000, 0.0196202000, 0.0332661000, 0.0649341000, 0.1386406000", \ - "0.0099730000, 0.0111503000, 0.0136646000, 0.0196127000, 0.0332958000, 0.0650119000, 0.1387668000", \ - "0.0108476000, 0.0118335000, 0.0142051000, 0.0198259000, 0.0335850000, 0.0652605000, 0.1387566000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0030592000, 0.0020548000, -0.000383000, -0.006184100, -0.019849700, -0.051798100, -0.126350800", \ - "0.0028585000, 0.0018912000, -0.000474400, -0.006213000, -0.019828400, -0.051750000, -0.126306300", \ - "0.0025445000, 0.0015989000, -0.000706900, -0.006354600, -0.019885900, -0.051756900, -0.126283700", \ - "0.0022458000, 0.0012597000, -0.001053600, -0.006639200, -0.020054300, -0.051842000, -0.126313900", \ - "0.0022665000, 0.0012278000, -0.001164300, -0.006937800, -0.020315900, -0.051985800, -0.126383700", \ - "0.0023920000, 0.0013046000, -0.001192100, -0.006985200, -0.020599200, -0.052277000, -0.126566300", \ - "0.0036038000, 0.0024509000, -0.000279700, -0.006358800, -0.020220900, -0.052174800, -0.126657600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0083108000, 0.0094322000, 0.0119889000, 0.0178763000, 0.0314875000, 0.0630843000, 0.1366988000", \ - "0.0080103000, 0.0091897000, 0.0117522000, 0.0176993000, 0.0313793000, 0.0630116000, 0.1366128000", \ - "0.0077679000, 0.0088989000, 0.0114494000, 0.0174678000, 0.0311964000, 0.0629294000, 0.1365791000", \ - "0.0076866000, 0.0087928000, 0.0113640000, 0.0171489000, 0.0309745000, 0.0627595000, 0.1364802000", \ - "0.0076969000, 0.0087702000, 0.0112796000, 0.0172148000, 0.0308329000, 0.0625518000, 0.1364008000", \ - "0.0088200000, 0.0098301000, 0.0123522000, 0.0175346000, 0.0309358000, 0.0624772000, 0.1361942000", \ - "0.0099047000, 0.0110756000, 0.0133506000, 0.0188019000, 0.0323040000, 0.0636314000, 0.1368036000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0024482000, 0.0013994000, -0.001062500, -0.006861900, -0.020505900, -0.052428600, -0.126949300", \ - "0.0023489000, 0.0013096000, -0.001126200, -0.006896400, -0.020507500, -0.052428100, -0.126934700", \ - "0.0022355000, 0.0011900000, -0.001214300, -0.006985200, -0.020559600, -0.052410700, -0.126926500", \ - "0.0020394000, 0.0010072000, -0.001382600, -0.007119600, -0.020660800, -0.052510600, -0.126973200", \ - "0.0020371000, 0.0009287000, -0.001551400, -0.007317600, -0.020843200, -0.052620000, -0.127054300", \ - "0.0024562000, 0.0015744000, -0.001222400, -0.007145300, -0.020903600, -0.052750700, -0.127167100", \ - "0.0038565000, 0.0026641000, -5.88000e-05, -0.006240400, -0.020021300, -0.052558300, -0.127169400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0059098000, 0.0071299000, 0.0097941000, 0.0157466000, 0.0293947000, 0.0609754000, 0.1344587000", \ - "0.0056725000, 0.0068901000, 0.0095881000, 0.0155957000, 0.0292874000, 0.0609329000, 0.1343946000", \ - "0.0054665000, 0.0066321000, 0.0093004000, 0.0152260000, 0.0291188000, 0.0608795000, 0.1344460000", \ - "0.0053731000, 0.0064747000, 0.0090565000, 0.0150406000, 0.0288506000, 0.0606266000, 0.1343335000", \ - "0.0056785000, 0.0067462000, 0.0092408000, 0.0150666000, 0.0286842000, 0.0604109000, 0.1340285000", \ - "0.0060268000, 0.0071691000, 0.0096650000, 0.0154879000, 0.0289452000, 0.0604245000, 0.1338848000", \ - "0.0077968000, 0.0087581000, 0.0109548000, 0.0164045000, 0.0296959000, 0.0609048000, 0.1340662000"); - } - } - max_capacitance : 0.0805760000; - max_transition : 1.4900030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0370636000, 0.0412873000, 0.0506141000, 0.0715936000, 0.1194165000, 0.2297097000, 0.4859544000", \ - "0.0414390000, 0.0457069000, 0.0551016000, 0.0760250000, 0.1238668000, 0.2343411000, 0.4904901000", \ - "0.0507754000, 0.0549840000, 0.0644013000, 0.0855200000, 0.1334047000, 0.2438759000, 0.5003855000", \ - "0.0674541000, 0.0724410000, 0.0834167000, 0.1059427000, 0.1542239000, 0.2647956000, 0.5211881000", \ - "0.0905636000, 0.0979049000, 0.1133094000, 0.1427762000, 0.1995540000, 0.3124499000, 0.5696443000", \ - "0.1122398000, 0.1230168000, 0.1480696000, 0.1935147000, 0.2739245000, 0.4133023000, 0.6808413000", \ - "0.1125790000, 0.1306803000, 0.1696704000, 0.2423054000, 0.3676839000, 0.5735863000, 0.9080673000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0788648000, 0.0881769000, 0.1087636000, 0.1562166000, 0.2651128000, 0.5183348000, 1.1067735000", \ - "0.0839519000, 0.0933296000, 0.1140600000, 0.1616633000, 0.2707473000, 0.5240300000, 1.1127727000", \ - "0.0959788000, 0.1052645000, 0.1261411000, 0.1737407000, 0.2833550000, 0.5367003000, 1.1259559000", \ - "0.1220365000, 0.1310179000, 0.1517663000, 0.1995652000, 0.3093385000, 0.5630207000, 1.1526382000", \ - "0.1711518000, 0.1826015000, 0.2073496000, 0.2578961000, 0.3676099000, 0.6215585000, 1.2112662000", \ - "0.2521902000, 0.2694477000, 0.3028633000, 0.3702550000, 0.4997929000, 0.7569285000, 1.3469030000", \ - "0.3850411000, 0.4096736000, 0.4603835000, 0.5596212000, 0.7373318000, 1.0574543000, 1.6602494000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0246122000, 0.0296045000, 0.0412687000, 0.0687779000, 0.1324641000, 0.2808725000, 0.6262984000", \ - "0.0245325000, 0.0295712000, 0.0414232000, 0.0686443000, 0.1324659000, 0.2812753000, 0.6264031000", \ - "0.0251105000, 0.0299709000, 0.0414220000, 0.0685641000, 0.1324968000, 0.2812956000, 0.6278245000", \ - "0.0320295000, 0.0366870000, 0.0472606000, 0.0718245000, 0.1330188000, 0.2811357000, 0.6266595000", \ - "0.0496786000, 0.0551756000, 0.0671176000, 0.0919608000, 0.1465362000, 0.2837396000, 0.6275712000", \ - "0.0839944000, 0.0926070000, 0.1087342000, 0.1397492000, 0.1991061000, 0.3230347000, 0.6378035000", \ - "0.1482261000, 0.1596394000, 0.1838877000, 0.2292554000, 0.3083795000, 0.4501478000, 0.7378819000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0598001000, 0.0715216000, 0.0990498000, 0.1631785000, 0.3118225000, 0.6586327000, 1.4657388000", \ - "0.0597938000, 0.0715237000, 0.0990491000, 0.1636335000, 0.3121486000, 0.6582490000, 1.4655099000", \ - "0.0596861000, 0.0716221000, 0.0991982000, 0.1630940000, 0.3120387000, 0.6592762000, 1.4689308000", \ - "0.0619422000, 0.0730387000, 0.0993957000, 0.1631379000, 0.3118359000, 0.6587375000, 1.4669014000", \ - "0.0799433000, 0.0908414000, 0.1149651000, 0.1715986000, 0.3128151000, 0.6588478000, 1.4668129000", \ - "0.1210248000, 0.1338833000, 0.1614961000, 0.2195516000, 0.3460722000, 0.6650873000, 1.4661601000", \ - "0.1989316000, 0.2167767000, 0.2528961000, 0.3247837000, 0.4646368000, 0.7559973000, 1.4870509000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0286549000, 0.0322400000, 0.0403679000, 0.0588812000, 0.1012872000, 0.2000522000, 0.4327201000", \ - "0.0329223000, 0.0366450000, 0.0449265000, 0.0635481000, 0.1061724000, 0.2049605000, 0.4357273000", \ - "0.0414456000, 0.0455907000, 0.0541944000, 0.0730924000, 0.1168571000, 0.2149827000, 0.4463117000", \ - "0.0534220000, 0.0592280000, 0.0709167000, 0.0933616000, 0.1372774000, 0.2373989000, 0.4676398000", \ - "0.0654217000, 0.0748413000, 0.0927893000, 0.1253132000, 0.1828203000, 0.2866733000, 0.5189855000", \ - "0.0678293000, 0.0831909000, 0.1116537000, 0.1628992000, 0.2479538000, 0.3853760000, 0.6314070000", \ - "0.0328679000, 0.0570385000, 0.1039620000, 0.1869215000, 0.3213259000, 0.5313464000, 0.8582015000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0687322000, 0.0777870000, 0.0989039000, 0.1463683000, 0.2556576000, 0.5089072000, 1.0974167000", \ - "0.0716533000, 0.0812164000, 0.1021112000, 0.1501785000, 0.2597118000, 0.5131903000, 1.1022622000", \ - "0.0821309000, 0.0911881000, 0.1122888000, 0.1605647000, 0.2709664000, 0.5243596000, 1.1135983000", \ - "0.1105686000, 0.1193925000, 0.1399413000, 0.1867056000, 0.2981018000, 0.5524100000, 1.1421368000", \ - "0.1666512000, 0.1790915000, 0.2047300000, 0.2540213000, 0.3619604000, 0.6153863000, 1.2054513000", \ - "0.2558693000, 0.2742312000, 0.3130368000, 0.3879548000, 0.5187656000, 0.7715645000, 1.3578947000", \ - "0.4038574000, 0.4297838000, 0.4878854000, 0.5990365000, 0.7996798000, 1.1281747000, 1.7086634000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0148218000, 0.0193466000, 0.0298051000, 0.0545611000, 0.1112896000, 0.2444759000, 0.5569009000", \ - "0.0148933000, 0.0193648000, 0.0298271000, 0.0542104000, 0.1111139000, 0.2439348000, 0.5528142000", \ - "0.0169132000, 0.0208149000, 0.0305347000, 0.0545257000, 0.1125193000, 0.2445099000, 0.5538380000", \ - "0.0255213000, 0.0297427000, 0.0390814000, 0.0596823000, 0.1126428000, 0.2472576000, 0.5542133000", \ - "0.0439434000, 0.0493740000, 0.0606591000, 0.0834354000, 0.1321267000, 0.2491407000, 0.5535692000", \ - "0.0782981000, 0.0862490000, 0.1022259000, 0.1331335000, 0.1883392000, 0.2980363000, 0.5713417000", \ - "0.1467505000, 0.1572692000, 0.1800936000, 0.2232653000, 0.2995096000, 0.4329449000, 0.6898222000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0596130000, 0.0714418000, 0.0991686000, 0.1630103000, 0.3120512000, 0.6580704000, 1.4658921000", \ - "0.0596550000, 0.0714956000, 0.0990585000, 0.1630685000, 0.3119548000, 0.6574677000, 1.4649419000", \ - "0.0596726000, 0.0715238000, 0.0990232000, 0.1634614000, 0.3130357000, 0.6591654000, 1.4667603000", \ - "0.0641311000, 0.0747279000, 0.1001188000, 0.1631798000, 0.3118989000, 0.6600511000, 1.4667366000", \ - "0.0917279000, 0.1029792000, 0.1245032000, 0.1771713000, 0.3134391000, 0.6582521000, 1.4680159000", \ - "0.1390708000, 0.1548285000, 0.1872738000, 0.2475334000, 0.3598213000, 0.6665355000, 1.4656457000", \ - "0.2146771000, 0.2386394000, 0.2881752000, 0.3782155000, 0.5265396000, 0.7889506000, 1.4900032000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0295749000, 0.0338112000, 0.0433308000, 0.0642938000, 0.1121818000, 0.2227433000, 0.4788427000", \ - "0.0336923000, 0.0380028000, 0.0475113000, 0.0686081000, 0.1165729000, 0.2271196000, 0.4832746000", \ - "0.0444673000, 0.0484685000, 0.0577671000, 0.0788168000, 0.1268864000, 0.2375032000, 0.4937253000", \ - "0.0620698000, 0.0681340000, 0.0803599000, 0.1035332000, 0.1512720000, 0.2619615000, 0.5191162000", \ - "0.0819859000, 0.0914978000, 0.1103940000, 0.1454322000, 0.2068868000, 0.3184486000, 0.5750939000", \ - "0.0982313000, 0.1119918000, 0.1411843000, 0.1948365000, 0.2899392000, 0.4432621000, 0.7055173000", \ - "0.0883130000, 0.1106387000, 0.1546781000, 0.2376537000, 0.3812269000, 0.6186990000, 0.9899610000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0320036000, 0.0387219000, 0.0535930000, 0.0868658000, 0.1635826000, 0.3396926000, 0.7492292000", \ - "0.0369083000, 0.0435733000, 0.0584978000, 0.0919064000, 0.1687120000, 0.3448666000, 0.7563767000", \ - "0.0500332000, 0.0564618000, 0.0709983000, 0.1042030000, 0.1812813000, 0.3586525000, 0.7687621000", \ - "0.0767142000, 0.0857051000, 0.1026262000, 0.1354676000, 0.2126104000, 0.3887283000, 0.7993047000", \ - "0.1185493000, 0.1330530000, 0.1603457000, 0.2068341000, 0.2852268000, 0.4615718000, 0.8713751000", \ - "0.1854465000, 0.2080547000, 0.2512964000, 0.3270072000, 0.4456487000, 0.6328310000, 1.0419651000", \ - "0.2997657000, 0.3340259000, 0.4000503000, 0.5167499000, 0.7098193000, 0.9988422000, 1.4391660000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0245882000, 0.0296431000, 0.0414710000, 0.0686283000, 0.1325775000, 0.2810359000, 0.6264213000", \ - "0.0243320000, 0.0295117000, 0.0413348000, 0.0686364000, 0.1323962000, 0.2809416000, 0.6263818000", \ - "0.0262753000, 0.0307634000, 0.0416615000, 0.0684523000, 0.1323878000, 0.2809687000, 0.6268323000", \ - "0.0377461000, 0.0428441000, 0.0532950000, 0.0749526000, 0.1331961000, 0.2815666000, 0.6277885000", \ - "0.0596889000, 0.0673082000, 0.0809638000, 0.1083513000, 0.1577707000, 0.2863826000, 0.6268193000", \ - "0.0982237000, 0.1094621000, 0.1305186000, 0.1707493000, 0.2362019000, 0.3521267000, 0.6452133000", \ - "0.1686675000, 0.1870369000, 0.2183621000, 0.2760411000, 0.3782005000, 0.5363878000, 0.8054248000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0425642000, 0.0520069000, 0.0732459000, 0.1208692000, 0.2296398000, 0.4821196000, 1.0717737000", \ - "0.0426050000, 0.0520112000, 0.0732493000, 0.1209157000, 0.2297144000, 0.4829468000, 1.0715261000", \ - "0.0446002000, 0.0528839000, 0.0732716000, 0.1209271000, 0.2296492000, 0.4828703000, 1.0722954000", \ - "0.0610114000, 0.0665050000, 0.0818336000, 0.1226820000, 0.2296050000, 0.4829248000, 1.0727368000", \ - "0.1015437000, 0.1074551000, 0.1209341000, 0.1505043000, 0.2379900000, 0.4826070000, 1.0733872000", \ - "0.1660825000, 0.1758556000, 0.1964754000, 0.2360427000, 0.3085415000, 0.5057243000, 1.0755760000", \ - "0.2680992000, 0.2835028000, 0.3161611000, 0.3830912000, 0.4935821000, 0.6704779000, 1.1307169000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ai_2") { - leakage_power () { - value : 0.0014004000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0001450000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0045644000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0008215000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0048488000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0008205000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0032314000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0008215000; - when : "A1&A2&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o21ai"; - cell_leakage_power : 0.0020816910; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0048320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081785000, 0.0081845000, 0.0081982000, 0.0081990000, 0.0082008000, 0.0082049000, 0.0082146000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008210000, -0.008200600, -0.008178700, -0.008174500, -0.008164800, -0.008142500, -0.008091000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050700000; - } - pin ("A2") { - capacitance : 0.0044220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075833000, 0.0075822000, 0.0075798000, 0.0075811000, 0.0075840000, 0.0075909000, 0.0076067000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007594700, -0.007588000, -0.007572400, -0.007571800, -0.007570300, -0.007567100, -0.007559500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047200000; - } - pin ("B1") { - capacitance : 0.0043790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090705000, 0.0090711000, 0.0090726000, 0.0090718000, 0.0090700000, 0.0090657000, 0.0090558000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004437400, -0.004446800, -0.004468500, -0.004444100, -0.004387900, -0.004258500, -0.003960000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045220000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0096090000, 0.0083648000, 0.0051832000, -0.002951800, -0.023860300, -0.077420800, -0.214556200", \ - "0.0093091000, 0.0080735000, 0.0049370000, -0.003190100, -0.024064500, -0.077646600, -0.214734700", \ - "0.0089141000, 0.0076966000, 0.0045718000, -0.003480000, -0.024318100, -0.077829200, -0.214909000", \ - "0.0084508000, 0.0072655000, 0.0041735000, -0.003804200, -0.024547500, -0.078025500, -0.215030400", \ - "0.0085419000, 0.0073141000, 0.0041598000, -0.004113700, -0.024693600, -0.078077200, -0.215024800", \ - "0.0086223000, 0.0073806000, 0.0041518000, -0.004030100, -0.024887700, -0.078439800, -0.215251800", \ - "0.0101452000, 0.0088024000, 0.0054890000, -0.002945000, -0.024142700, -0.077971300, -0.215242000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0195203000, 0.0208075000, 0.0240541000, 0.0323440000, 0.0532157000, 0.1063415000, 0.2417976000", \ - "0.0190958000, 0.0203908000, 0.0237020000, 0.0320414000, 0.0530481000, 0.1062313000, 0.2416918000", \ - "0.0186675000, 0.0199882000, 0.0232915000, 0.0316508000, 0.0527239000, 0.1060260000, 0.2415488000", \ - "0.0183765000, 0.0196597000, 0.0229422000, 0.0312839000, 0.0524314000, 0.1057152000, 0.2415459000", \ - "0.0181364000, 0.0194787000, 0.0227603000, 0.0310293000, 0.0520484000, 0.1054043000, 0.2411913000", \ - "0.0181837000, 0.0194027000, 0.0226532000, 0.0310030000, 0.0520588000, 0.1053034000, 0.2409582000", \ - "0.0189004000, 0.0200953000, 0.0231211000, 0.0310860000, 0.0523650000, 0.1053257000, 0.2413104000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0059808000, 0.0048014000, 0.0017042000, -0.006405300, -0.027363100, -0.081035600, -0.218242400", \ - "0.0056600000, 0.0045444000, 0.0015517000, -0.006433300, -0.027305900, -0.080928900, -0.218113600", \ - "0.0051706000, 0.0040667000, 0.0011496000, -0.006684000, -0.027380900, -0.080902600, -0.218037100", \ - "0.0046641000, 0.0035461000, 0.0005864000, -0.007160600, -0.027676500, -0.081025500, -0.218059200", \ - "0.0047062000, 0.0035021000, 0.0004213000, -0.007642500, -0.028111600, -0.081254000, -0.218145100", \ - "0.0049194000, 0.0036423000, 0.0004205000, -0.007691400, -0.028407100, -0.081749700, -0.218416000", \ - "0.0068154000, 0.0054435000, 0.0020280000, -0.006609700, -0.027907500, -0.081559200, -0.218613300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0149653000, 0.0162507000, 0.0195640000, 0.0278155000, 0.0487599000, 0.1019036000, 0.2372119000", \ - "0.0145135000, 0.0158352000, 0.0191756000, 0.0275370000, 0.0484802000, 0.1017208000, 0.2371581000", \ - "0.0140383000, 0.0153739000, 0.0186897000, 0.0271038000, 0.0482262000, 0.1015521000, 0.2368660000", \ - "0.0138865000, 0.0151430000, 0.0184557000, 0.0267344000, 0.0478775000, 0.1013181000, 0.2369697000", \ - "0.0142151000, 0.0154731000, 0.0186913000, 0.0264871000, 0.0475530000, 0.1008465000, 0.2367240000", \ - "0.0154824000, 0.0166867000, 0.0198604000, 0.0272537000, 0.0477937000, 0.1007605000, 0.2364134000", \ - "0.0175176000, 0.0187209000, 0.0219506000, 0.0300094000, 0.0504941000, 0.1037169000, 0.2365616000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0056042000, 0.0044332000, 0.0013840000, -0.006587900, -0.027376700, -0.080908100, -0.217966300", \ - "0.0053694000, 0.0041768000, 0.0011607000, -0.006802100, -0.027476000, -0.080933100, -0.217986300", \ - "0.0050256000, 0.0038464000, 0.0008262000, -0.007050100, -0.027680800, -0.080991300, -0.217983600", \ - "0.0047008000, 0.0034797000, 0.0004322000, -0.007428400, -0.028036300, -0.081287000, -0.218133900", \ - "0.0047575000, 0.0035166000, 0.0003363000, -0.007736300, -0.028336300, -0.081496700, -0.218294500", \ - "0.0059487000, 0.0046552000, 0.0016062000, -0.006820700, -0.028038400, -0.081768900, -0.218596600", \ - "0.0091023000, 0.0076653000, 0.0040759000, -0.004758400, -0.026506400, -0.080907200, -0.218614800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012776130, 0.0032645900, 0.0083417660, 0.0213151000, 0.0544649000, 0.1391701000"); - values("0.0091897000, 0.0107001000, 0.0142540000, 0.0228288000, 0.0438763000, 0.0971493000, 0.2322570000", \ - "0.0087839000, 0.0101723000, 0.0137366000, 0.0224347000, 0.0437348000, 0.0970745000, 0.2322813000", \ - "0.0084383000, 0.0097894000, 0.0132585000, 0.0219438000, 0.0432783000, 0.0966477000, 0.2323252000", \ - "0.0085402000, 0.0098045000, 0.0131571000, 0.0213818000, 0.0427744000, 0.0961464000, 0.2322939000", \ - "0.0088236000, 0.0100511000, 0.0132142000, 0.0213417000, 0.0421868000, 0.0955670000, 0.2309699000", \ - "0.0099106000, 0.0110367000, 0.0141806000, 0.0223610000, 0.0428594000, 0.0953063000, 0.2308780000", \ - "0.0141507000, 0.0151318000, 0.0179053000, 0.0259604000, 0.0450396000, 0.0984368000, 0.2334779000"); - } - } - max_capacitance : 0.1391700000; - max_transition : 1.4997990000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0327163000, 0.0352249000, 0.0411928000, 0.0554968000, 0.0903964000, 0.1772799000, 0.3974127000", \ - "0.0371420000, 0.0396592000, 0.0456505000, 0.0599938000, 0.0948263000, 0.1817927000, 0.4020554000", \ - "0.0465958000, 0.0490918000, 0.0550793000, 0.0694419000, 0.1044217000, 0.1914105000, 0.4117068000", \ - "0.0620934000, 0.0653591000, 0.0726752000, 0.0892139000, 0.1251280000, 0.2125900000, 0.4332479000", \ - "0.0810604000, 0.0860202000, 0.0970044000, 0.1206635000, 0.1671460000, 0.2603823000, 0.4818040000", \ - "0.0946743000, 0.1023623000, 0.1197487000, 0.1561945000, 0.2265839000, 0.3521729000, 0.5933586000", \ - "0.0772965000, 0.0884390000, 0.1158853000, 0.1746933000, 0.2869965000, 0.4803138000, 0.8046043000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0872319000, 0.0934144000, 0.1086711000, 0.1477364000, 0.2444592000, 0.4895642000, 1.1134332000", \ - "0.0916253000, 0.0977106000, 0.1136712000, 0.1525719000, 0.2497153000, 0.4948578000, 1.1186622000", \ - "0.1035710000, 0.1101828000, 0.1256522000, 0.1650741000, 0.2626259000, 0.5080882000, 1.1321626000", \ - "0.1310149000, 0.1374957000, 0.1530491000, 0.1918550000, 0.2895239000, 0.5357907000, 1.1601381000", \ - "0.1843666000, 0.1925246000, 0.2105067000, 0.2525167000, 0.3497242000, 0.5959315000, 1.2213049000", \ - "0.2762365000, 0.2863773000, 0.3116626000, 0.3675358000, 0.4858857000, 0.7362709000, 1.3619723000", \ - "0.4271304000, 0.4436669000, 0.4811090000, 0.5650051000, 0.7288347000, 1.0435182000, 1.6862376000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0208671000, 0.0235749000, 0.0304603000, 0.0482722000, 0.0938806000, 0.2110170000, 0.5105090000", \ - "0.0207531000, 0.0234798000, 0.0304235000, 0.0482353000, 0.0937778000, 0.2112065000, 0.5093913000", \ - "0.0215086000, 0.0241148000, 0.0307587000, 0.0480843000, 0.0936989000, 0.2106989000, 0.5094976000", \ - "0.0290207000, 0.0315563000, 0.0379849000, 0.0535287000, 0.0955900000, 0.2111432000, 0.5100534000", \ - "0.0460138000, 0.0494502000, 0.0568558000, 0.0745312000, 0.1151385000, 0.2175320000, 0.5098389000", \ - "0.0784240000, 0.0832153000, 0.0943979000, 0.1181598000, 0.1670837000, 0.2684870000, 0.5284798000", \ - "0.1402601000, 0.1473172000, 0.1642593000, 0.1998516000, 0.2682959000, 0.3944998000, 0.6511275000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0606703000, 0.0688258000, 0.0892487000, 0.1416761000, 0.2748253000, 0.6132291000, 1.4800445000", \ - "0.0607580000, 0.0688475000, 0.0893118000, 0.1416141000, 0.2745425000, 0.6128029000, 1.4759232000", \ - "0.0607608000, 0.0688148000, 0.0893825000, 0.1415178000, 0.2748196000, 0.6139685000, 1.4768192000", \ - "0.0617463000, 0.0694630000, 0.0895076000, 0.1417475000, 0.2746941000, 0.6138510000, 1.4801511000", \ - "0.0783071000, 0.0862058000, 0.1041884000, 0.1503079000, 0.2765169000, 0.6130666000, 1.4761415000", \ - "0.1164884000, 0.1254839000, 0.1463839000, 0.1959572000, 0.3105751000, 0.6205124000, 1.4773045000", \ - "0.1943285000, 0.2059431000, 0.2335702000, 0.2939060000, 0.4229691000, 0.7093212000, 1.4926287000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0265077000, 0.0288213000, 0.0345491000, 0.0486509000, 0.0842160000, 0.1743439000, 0.4047038000", \ - "0.0307364000, 0.0331595000, 0.0390226000, 0.0533644000, 0.0890238000, 0.1800213000, 0.4096588000", \ - "0.0384361000, 0.0412034000, 0.0475876000, 0.0622350000, 0.0981586000, 0.1892589000, 0.4218000000", \ - "0.0486376000, 0.0525004000, 0.0610922000, 0.0793644000, 0.1173792000, 0.2087524000, 0.4390110000", \ - "0.0570955000, 0.0630028000, 0.0764947000, 0.1036315000, 0.1543098000, 0.2532664000, 0.4851687000", \ - "0.0517068000, 0.0615812000, 0.0829417000, 0.1262954000, 0.2038635000, 0.3363467000, 0.5885836000", \ - "-0.003033500, 0.0123871000, 0.0506626000, 0.1206166000, 0.2453454000, 0.4496049000, 0.7857009000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0692346000, 0.0752968000, 0.0912167000, 0.1297058000, 0.2265175000, 0.4715007000, 1.0968653000", \ - "0.0727151000, 0.0785957000, 0.0947052000, 0.1336707000, 0.2307643000, 0.4758384000, 1.0996448000", \ - "0.0831033000, 0.0892831000, 0.1050494000, 0.1441881000, 0.2419213000, 0.4872948000, 1.1123237000", \ - "0.1121357000, 0.1180193000, 0.1333876000, 0.1714702000, 0.2687101000, 0.5148293000, 1.1390561000", \ - "0.1721598000, 0.1804395000, 0.1997463000, 0.2410143000, 0.3373440000, 0.5827427000, 1.2075920000", \ - "0.2682456000, 0.2821414000, 0.3112903000, 0.3732678000, 0.4944254000, 0.7409051000, 1.3615593000", \ - "0.4344807000, 0.4524052000, 0.4958020000, 0.5897274000, 0.7745559000, 1.1033349000, 1.7293927000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0130757000, 0.0160091000, 0.0234747000, 0.0425208000, 0.0910773000, 0.2145869000, 0.5315825000", \ - "0.0131382000, 0.0160541000, 0.0234687000, 0.0426481000, 0.0910411000, 0.2155576000, 0.5320018000", \ - "0.0154048000, 0.0178594000, 0.0245786000, 0.0428264000, 0.0913626000, 0.2159771000, 0.5367545000", \ - "0.0230887000, 0.0258214000, 0.0326282000, 0.0495278000, 0.0931643000, 0.2152391000, 0.5319621000", \ - "0.0399815000, 0.0436364000, 0.0520606000, 0.0706498000, 0.1131910000, 0.2223924000, 0.5324507000", \ - "0.0725127000, 0.0777890000, 0.0897842000, 0.1149400000, 0.1653381000, 0.2708878000, 0.5486959000", \ - "0.1391735000, 0.1468825000, 0.1624407000, 0.1978910000, 0.2668292000, 0.3951339000, 0.6658937000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0605853000, 0.0686980000, 0.0895049000, 0.1416199000, 0.2747341000, 0.6127513000, 1.4814294000", \ - "0.0606206000, 0.0686669000, 0.0892742000, 0.1416240000, 0.2748639000, 0.6139774000, 1.4767131000", \ - "0.0605685000, 0.0687534000, 0.0893630000, 0.1416945000, 0.2746998000, 0.6133496000, 1.4820006000", \ - "0.0641290000, 0.0715406000, 0.0905699000, 0.1415333000, 0.2747482000, 0.6129168000, 1.4774255000", \ - "0.0896062000, 0.0976331000, 0.1151626000, 0.1569066000, 0.2767370000, 0.6150065000, 1.4773029000", \ - "0.1346292000, 0.1464959000, 0.1707918000, 0.2237614000, 0.3278346000, 0.6224066000, 1.4791698000", \ - "0.2083926000, 0.2253310000, 0.2626478000, 0.3429215000, 0.4859333000, 0.7526176000, 1.4997993000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0244773000, 0.0270529000, 0.0332348000, 0.0477698000, 0.0828070000, 0.1697937000, 0.3900734000", \ - "0.0285322000, 0.0310706000, 0.0372910000, 0.0518480000, 0.0869593000, 0.1741123000, 0.3944407000", \ - "0.0390837000, 0.0416902000, 0.0476318000, 0.0618960000, 0.0968752000, 0.1841282000, 0.4049558000", \ - "0.0538951000, 0.0576018000, 0.0665358000, 0.0847227000, 0.1202791000, 0.2082802000, 0.4288031000", \ - "0.0694217000, 0.0751858000, 0.0884943000, 0.1160166000, 0.1688633000, 0.2637577000, 0.4837612000", \ - "0.0775868000, 0.0863619000, 0.1061242000, 0.1476442000, 0.2287442000, 0.3710038000, 0.6133274000", \ - "0.0547334000, 0.0680204000, 0.0982061000, 0.1626650000, 0.2861750000, 0.5036284000, 0.8645007000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0238300000, 0.0272273000, 0.0354022000, 0.0549364000, 0.1028777000, 0.2249688000, 0.5340851000", \ - "0.0290095000, 0.0321792000, 0.0402854000, 0.0599592000, 0.1084964000, 0.2298994000, 0.5370117000", \ - "0.0420580000, 0.0456295000, 0.0533900000, 0.0728267000, 0.1206247000, 0.2418772000, 0.5515662000", \ - "0.0637527000, 0.0693796000, 0.0815162000, 0.1044131000, 0.1521038000, 0.2733078000, 0.5830287000", \ - "0.0979999000, 0.1071491000, 0.1267294000, 0.1634527000, 0.2262621000, 0.3469603000, 0.6522197000", \ - "0.1555198000, 0.1693893000, 0.1993532000, 0.2575704000, 0.3587102000, 0.5190643000, 0.8256142000", \ - "0.2611981000, 0.2810955000, 0.3244245000, 0.4125381000, 0.5705856000, 0.8282737000, 1.2246161000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0207771000, 0.0235018000, 0.0304539000, 0.0482200000, 0.0938198000, 0.2111963000, 0.5102564000", \ - "0.0199761000, 0.0228733000, 0.0301812000, 0.0481778000, 0.0936593000, 0.2108035000, 0.5094186000", \ - "0.0230772000, 0.0253888000, 0.0314231000, 0.0481060000, 0.0936917000, 0.2105350000, 0.5094993000", \ - "0.0333320000, 0.0362733000, 0.0435570000, 0.0589592000, 0.0974000000, 0.2107345000, 0.5094660000", \ - "0.0521542000, 0.0569867000, 0.0673177000, 0.0877188000, 0.1290194000, 0.2237707000, 0.5097616000", \ - "0.0854041000, 0.0923652000, 0.1093612000, 0.1413252000, 0.1974040000, 0.3016530000, 0.5406680000", \ - "0.1455845000, 0.1571590000, 0.1819099000, 0.2308408000, 0.3174581000, 0.4652093000, 0.7213521000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012776100, 0.0032645900, 0.0083417700, 0.0213151000, 0.0544649000, 0.1391700000"); - values("0.0232553000, 0.0279276000, 0.0396594000, 0.0689026000, 0.1403636000, 0.3144672000, 0.7542662000", \ - "0.0233664000, 0.0278877000, 0.0396296000, 0.0689107000, 0.1405241000, 0.3143392000, 0.7532511000", \ - "0.0279990000, 0.0312861000, 0.0411368000, 0.0689755000, 0.1405314000, 0.3140097000, 0.7547921000", \ - "0.0477284000, 0.0502636000, 0.0559660000, 0.0768757000, 0.1411680000, 0.3140709000, 0.7543756000", \ - "0.0833441000, 0.0864345000, 0.0950100000, 0.1149987000, 0.1634455000, 0.3160485000, 0.7542653000", \ - "0.1432471000, 0.1480855000, 0.1605753000, 0.1896079000, 0.2465701000, 0.3661950000, 0.7570390000", \ - "0.2387945000, 0.2457773000, 0.2648549000, 0.3103134000, 0.4010784000, 0.5551312000, 0.8692939000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ai_4") { - leakage_power () { - value : 0.0033032000; - when : "!A1&!A2&B1"; - } - leakage_power () { - value : 0.0003379000; - when : "!A1&!A2&!B1"; - } - leakage_power () { - value : 0.0055610000; - when : "!A1&A2&B1"; - } - leakage_power () { - value : 0.0020090000; - when : "!A1&A2&!B1"; - } - leakage_power () { - value : 0.0060341000; - when : "A1&!A2&B1"; - } - leakage_power () { - value : 0.0019958000; - when : "A1&!A2&!B1"; - } - leakage_power () { - value : 0.0039633000; - when : "A1&A2&B1"; - } - leakage_power () { - value : 0.0020126000; - when : "A1&A2&!B1"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__o21ai"; - cell_leakage_power : 0.0031521180; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0091440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0159853000, 0.0159759000, 0.0159543000, 0.0159531000, 0.0159504000, 0.0159442000, 0.0159297000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015936800, -0.015925700, -0.015900200, -0.015894200, -0.015880200, -0.015848000, -0.015773900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0096110000; - } - pin ("A2") { - capacitance : 0.0084740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0151335000, 0.0151232000, 0.0150996000, 0.0150990000, 0.0150977000, 0.0150948000, 0.0150879000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015094100, -0.015094700, -0.015096200, -0.015095400, -0.015093800, -0.015090000, -0.015081200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090640000; - } - pin ("B1") { - capacitance : 0.0086920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0183625000, 0.0183591000, 0.0183515000, 0.0183575000, 0.0183713000, 0.0184031000, 0.0184764000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.009988700, -0.010021200, -0.010096200, -0.010048000, -0.009936600, -0.009680100, -0.009088600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089930000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0198567000, 0.0184379000, 0.0145406000, 0.0036896000, -0.026417700, -0.110016700, -0.341819100", \ - "0.0193277000, 0.0179346000, 0.0140290000, 0.0032380000, -0.026839000, -0.110465500, -0.342231200", \ - "0.0186186000, 0.0172210000, 0.0133816000, 0.0026657000, -0.027302200, -0.110840900, -0.342521900", \ - "0.0177382000, 0.0163835000, 0.0126388000, 0.0020367000, -0.027807300, -0.111236500, -0.342747600", \ - "0.0178248000, 0.0164199000, 0.0125143000, 0.0014983000, -0.028204700, -0.111380300, -0.342859300", \ - "0.0180236000, 0.0166111000, 0.0125930000, 0.0017153000, -0.028383300, -0.111994000, -0.343325000", \ - "0.0207343000, 0.0193630000, 0.0152204000, 0.0039568000, -0.026816500, -0.110951600, -0.343149300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0375294000, 0.0389800000, 0.0429471000, 0.0540202000, 0.0842378000, 0.1673311000, 0.3964341000", \ - "0.0368062000, 0.0382830000, 0.0423065000, 0.0534856000, 0.0839196000, 0.1669254000, 0.3962280000", \ - "0.0360370000, 0.0375554000, 0.0416340000, 0.0528213000, 0.0833851000, 0.1666621000, 0.3960475000", \ - "0.0355080000, 0.0369404000, 0.0409951000, 0.0521038000, 0.0827333000, 0.1660710000, 0.3957360000", \ - "0.0350694000, 0.0365372000, 0.0405848000, 0.0516003000, 0.0819388000, 0.1654224000, 0.3952675000", \ - "0.0349743000, 0.0364155000, 0.0403696000, 0.0515763000, 0.0819511000, 0.1652728000, 0.3947931000", \ - "0.0359171000, 0.0373066000, 0.0410647000, 0.0516545000, 0.0825219000, 0.1663649000, 0.3951909000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0130528000, 0.0117167000, 0.0079095000, -0.002826200, -0.033009800, -0.116827400, -0.348823200", \ - "0.0124754000, 0.0112210000, 0.0075921000, -0.002924400, -0.032876000, -0.116583800, -0.348546000", \ - "0.0115637000, 0.0103112000, 0.0067716000, -0.003419900, -0.033037100, -0.116493700, -0.348339200", \ - "0.0104974000, 0.0092569000, 0.0056897000, -0.004461700, -0.033686600, -0.116730100, -0.348356200", \ - "0.0105889000, 0.0092430000, 0.0054671000, -0.005108600, -0.034617800, -0.117288100, -0.348512800", \ - "0.0108225000, 0.0093814000, 0.0054624000, -0.005347800, -0.035111700, -0.118232300, -0.349117400", \ - "0.0143662000, 0.0127120000, 0.0084355000, -0.003074600, -0.033952600, -0.117821100, -0.349499500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0285894000, 0.0300678000, 0.0340754000, 0.0451522000, 0.0753900000, 0.1584686000, 0.3874950000", \ - "0.0277337000, 0.0292123000, 0.0333278000, 0.0445479000, 0.0749813000, 0.1581746000, 0.3873588000", \ - "0.0268622000, 0.0283082000, 0.0324520000, 0.0437338000, 0.0743148000, 0.1577178000, 0.3870611000", \ - "0.0262646000, 0.0277460000, 0.0318726000, 0.0429547000, 0.0735726000, 0.1573816000, 0.3868761000", \ - "0.0262932000, 0.0277355000, 0.0316658000, 0.0427235000, 0.0730024000, 0.1564933000, 0.3863418000", \ - "0.0286772000, 0.0300672000, 0.0339801000, 0.0447559000, 0.0746524000, 0.1568866000, 0.3846276000", \ - "0.0334104000, 0.0350448000, 0.0388090000, 0.0488631000, 0.0777342000, 0.1595000000, 0.3864958000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0136968000, 0.0123635000, 0.0086711000, -0.001806700, -0.031658500, -0.115108100, -0.346844800", \ - "0.0131097000, 0.0118073000, 0.0081701000, -0.002242800, -0.031864800, -0.115141800, -0.346754100", \ - "0.0124934000, 0.0111805000, 0.0074595000, -0.002876400, -0.032294900, -0.115355000, -0.346929700", \ - "0.0117042000, 0.0103759000, 0.0067285000, -0.003712400, -0.033130000, -0.115908300, -0.347092600", \ - "0.0116757000, 0.0102637000, 0.0063666000, -0.004325800, -0.033881600, -0.116782600, -0.347502500", \ - "0.0139444000, 0.0125770000, 0.0087520000, -0.002509100, -0.033672700, -0.117010300, -0.348111200", \ - "0.0190410000, 0.0174023000, 0.0129922000, 0.0011417000, -0.030255200, -0.115330700, -0.348173900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013834110, 0.0038276500, 0.0105904200, 0.0293018100, 0.0810728600, 0.2243141000"); - values("0.0181989000, 0.0200062000, 0.0246691000, 0.0365772000, 0.0674511000, 0.1505339000, 0.3795280000", \ - "0.0172663000, 0.0189542000, 0.0234684000, 0.0356349000, 0.0667807000, 0.1504597000, 0.3796086000", \ - "0.0165928000, 0.0181578000, 0.0225441000, 0.0344036000, 0.0655030000, 0.1499659000, 0.3798025000", \ - "0.0168151000, 0.0182569000, 0.0219413000, 0.0334912000, 0.0646330000, 0.1485199000, 0.3783599000", \ - "0.0174958000, 0.0187294000, 0.0225190000, 0.0333222000, 0.0638333000, 0.1477859000, 0.3775810000", \ - "0.0198439000, 0.0211351000, 0.0248243000, 0.0354356000, 0.0658961000, 0.1474220000, 0.3739525000", \ - "0.0264546000, 0.0275616000, 0.0307605000, 0.0428123000, 0.0687302000, 0.1518231000, 0.3774925000"); - } - } - max_capacitance : 0.2243140000; - max_transition : 1.4943390000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0341694000, 0.0357726000, 0.0401979000, 0.0514408000, 0.0808595000, 0.1590864000, 0.3728817000", \ - "0.0383389000, 0.0400060000, 0.0443702000, 0.0557198000, 0.0850638000, 0.1633668000, 0.3768873000", \ - "0.0469476000, 0.0486026000, 0.0529413000, 0.0642507000, 0.0936581000, 0.1719120000, 0.3856913000", \ - "0.0608769000, 0.0628951000, 0.0683591000, 0.0814181000, 0.1122911000, 0.1908625000, 0.4048147000", \ - "0.0783892000, 0.0813325000, 0.0891538000, 0.1071802000, 0.1468141000, 0.2333676000, 0.4484930000", \ - "0.0889602000, 0.0934999000, 0.1053196000, 0.1327943000, 0.1929517000, 0.3092364000, 0.5470426000", \ - "0.0619597000, 0.0692746000, 0.0881530000, 0.1328153000, 0.2284248000, 0.4078190000, 0.7277438000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.1003323000, 0.1045961000, 0.1163993000, 0.1479843000, 0.2335145000, 0.4678911000, 1.1167905000", \ - "0.1045577000, 0.1090350000, 0.1207176000, 0.1527927000, 0.2386732000, 0.4737271000, 1.1194455000", \ - "0.1163351000, 0.1210212000, 0.1327891000, 0.1650161000, 0.2516572000, 0.4868996000, 1.1329389000", \ - "0.1435823000, 0.1477670000, 0.1596073000, 0.1916122000, 0.2779779000, 0.5136339000, 1.1600039000", \ - "0.1974026000, 0.2022735000, 0.2159943000, 0.2502936000, 0.3364303000, 0.5720435000, 1.2193372000", \ - "0.2916447000, 0.2982642000, 0.3156072000, 0.3604048000, 0.4647673000, 0.7066279000, 1.3550692000", \ - "0.4518075000, 0.4620334000, 0.4888832000, 0.5539021000, 0.6975475000, 1.0023979000, 1.6678967000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0248376000, 0.0265352000, 0.0312712000, 0.0447122000, 0.0825021000, 0.1881129000, 0.4816426000", \ - "0.0246349000, 0.0263442000, 0.0312032000, 0.0446635000, 0.0824659000, 0.1881151000, 0.4817008000", \ - "0.0254089000, 0.0269940000, 0.0316061000, 0.0447636000, 0.0823877000, 0.1881472000, 0.4811362000", \ - "0.0319613000, 0.0335619000, 0.0381648000, 0.0503605000, 0.0848552000, 0.1882185000, 0.4811554000", \ - "0.0482819000, 0.0501802000, 0.0554483000, 0.0690068000, 0.1037211000, 0.1972017000, 0.4818376000", \ - "0.0809816000, 0.0839376000, 0.0910628000, 0.1091840000, 0.1507977000, 0.2462794000, 0.5021340000", \ - "0.1424125000, 0.1467481000, 0.1578898000, 0.1855008000, 0.2438027000, 0.3603943000, 0.6180320000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0712219000, 0.0768922000, 0.0923835000, 0.1357977000, 0.2535419000, 0.5781401000, 1.4785918000", \ - "0.0711968000, 0.0768112000, 0.0925288000, 0.1357988000, 0.2534997000, 0.5794961000, 1.4805310000", \ - "0.0712527000, 0.0769249000, 0.0926642000, 0.1357819000, 0.2549503000, 0.5796232000, 1.4805505000", \ - "0.0715915000, 0.0771026000, 0.0925965000, 0.1355664000, 0.2533746000, 0.5790159000, 1.4769895000", \ - "0.0870297000, 0.0920774000, 0.1056263000, 0.1439173000, 0.2559129000, 0.5784745000, 1.4788840000", \ - "0.1222318000, 0.1286375000, 0.1440239000, 0.1855596000, 0.2898668000, 0.5878960000, 1.4809189000", \ - "0.1994151000, 0.2069881000, 0.2263395000, 0.2748045000, 0.3910973000, 0.6767196000, 1.4932955000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0280072000, 0.0295461000, 0.0335594000, 0.0444858000, 0.0739375000, 0.1554548000, 0.3780100000", \ - "0.0320494000, 0.0336314000, 0.0378587000, 0.0488544000, 0.0785241000, 0.1592009000, 0.3821911000", \ - "0.0390645000, 0.0409414000, 0.0455713000, 0.0571004000, 0.0872889000, 0.1683377000, 0.3914664000", \ - "0.0483930000, 0.0508283000, 0.0569545000, 0.0714429000, 0.1044099000, 0.1860021000, 0.4096711000", \ - "0.0550642000, 0.0588121000, 0.0683213000, 0.0901613000, 0.1344108000, 0.2261607000, 0.4518472000", \ - "0.0458952000, 0.0514218000, 0.0666574000, 0.1020145000, 0.1708357000, 0.2961164000, 0.5457395000", \ - "-0.018259800, -0.007830900, 0.0181535000, 0.0757855000, 0.1868152000, 0.3816133000, 0.7152793000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0809942000, 0.0851180000, 0.0968628000, 0.1286109000, 0.2144106000, 0.4487218000, 1.0941149000", \ - "0.0839757000, 0.0882662000, 0.1000463000, 0.1322937000, 0.2184165000, 0.4530866000, 1.0988620000", \ - "0.0938002000, 0.0980872000, 0.1102753000, 0.1425253000, 0.2287812000, 0.4641668000, 1.1102106000", \ - "0.1221292000, 0.1264555000, 0.1382112000, 0.1694495000, 0.2559851000, 0.4918345000, 1.1381432000", \ - "0.1857744000, 0.1911097000, 0.2048040000, 0.2390225000, 0.3239434000, 0.5589635000, 1.2087839000", \ - "0.2918167000, 0.2999071000, 0.3209723000, 0.3714707000, 0.4815919000, 0.7172781000, 1.3584690000", \ - "0.4712327000, 0.4837261000, 0.5142463000, 0.5885430000, 0.7546582000, 1.0789938000, 1.7284796000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0151399000, 0.0170417000, 0.0222124000, 0.0369683000, 0.0773120000, 0.1894418000, 0.5004201000", \ - "0.0151697000, 0.0170653000, 0.0223144000, 0.0369674000, 0.0774802000, 0.1891781000, 0.4985138000", \ - "0.0172727000, 0.0188491000, 0.0235780000, 0.0373395000, 0.0774886000, 0.1894945000, 0.5003991000", \ - "0.0246024000, 0.0263318000, 0.0310976000, 0.0444883000, 0.0804673000, 0.1891732000, 0.4983581000", \ - "0.0417217000, 0.0439134000, 0.0497962000, 0.0642389000, 0.1002596000, 0.1987887000, 0.4985591000", \ - "0.0749543000, 0.0785231000, 0.0866960000, 0.1058591000, 0.1488864000, 0.2474977000, 0.5176258000", \ - "0.1422240000, 0.1462398000, 0.1574384000, 0.1849700000, 0.2442120000, 0.3641032000, 0.6320210000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0710834000, 0.0768147000, 0.0925858000, 0.1354576000, 0.2536767000, 0.5782630000, 1.4763843000", \ - "0.0713316000, 0.0769620000, 0.0924520000, 0.1354318000, 0.2536487000, 0.5782950000, 1.4777517000", \ - "0.0712379000, 0.0767689000, 0.0925094000, 0.1353815000, 0.2535794000, 0.5783640000, 1.4764886000", \ - "0.0730897000, 0.0782811000, 0.0931792000, 0.1351159000, 0.2534334000, 0.5790052000, 1.4758105000", \ - "0.0984298000, 0.1040615000, 0.1162663000, 0.1506047000, 0.2569069000, 0.5784232000, 1.4791952000", \ - "0.1446964000, 0.1521369000, 0.1714505000, 0.2147365000, 0.3102775000, 0.5900521000, 1.4761424000", \ - "0.2196438000, 0.2319243000, 0.2601366000, 0.3241244000, 0.4587456000, 0.7199569000, 1.4943392000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0268924000, 0.0285883000, 0.0331602000, 0.0447837000, 0.0744197000, 0.1526743000, 0.3667182000", \ - "0.0307669000, 0.0325205000, 0.0370520000, 0.0487408000, 0.0784958000, 0.1570224000, 0.3708949000", \ - "0.0412525000, 0.0429358000, 0.0471777000, 0.0584628000, 0.0883949000, 0.1670163000, 0.3809805000", \ - "0.0568080000, 0.0591756000, 0.0655417000, 0.0804963000, 0.1117964000, 0.1903845000, 0.4044485000", \ - "0.0727300000, 0.0762373000, 0.0858414000, 0.1080148000, 0.1550945000, 0.2454053000, 0.4595437000", \ - "0.0791271000, 0.0846019000, 0.0988493000, 0.1323774000, 0.2040172000, 0.3415962000, 0.5867895000", \ - "0.0509830000, 0.0591293000, 0.0803043000, 0.1315119000, 0.2410677000, 0.4512840000, 0.8214778000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0262463000, 0.0286122000, 0.0347495000, 0.0504813000, 0.0911037000, 0.2008829000, 0.5028712000", \ - "0.0311709000, 0.0334262000, 0.0394469000, 0.0552869000, 0.0963862000, 0.2070279000, 0.5105821000", \ - "0.0446820000, 0.0467849000, 0.0524819000, 0.0678634000, 0.1086067000, 0.2204906000, 0.5246265000", \ - "0.0676343000, 0.0712773000, 0.0800668000, 0.0992125000, 0.1397415000, 0.2513532000, 0.5527575000", \ - "0.1048718000, 0.1107573000, 0.1245562000, 0.1549045000, 0.2128023000, 0.3244017000, 0.6262394000", \ - "0.1676070000, 0.1762069000, 0.1976046000, 0.2456275000, 0.3368510000, 0.4952342000, 0.7930516000", \ - "0.2844502000, 0.2968476000, 0.3278376000, 0.3979799000, 0.5397457000, 0.7907355000, 1.1985344000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0248096000, 0.0265626000, 0.0312374000, 0.0446303000, 0.0824516000, 0.1881089000, 0.4816876000", \ - "0.0238526000, 0.0257068000, 0.0309175000, 0.0445300000, 0.0824011000, 0.1878784000, 0.4809093000", \ - "0.0262272000, 0.0276889000, 0.0318985000, 0.0445189000, 0.0822033000, 0.1879746000, 0.4824167000", \ - "0.0361592000, 0.0382037000, 0.0439570000, 0.0562034000, 0.0868976000, 0.1879226000, 0.4819619000", \ - "0.0554302000, 0.0584629000, 0.0659080000, 0.0831305000, 0.1199788000, 0.2032903000, 0.4813021000", \ - "0.0898670000, 0.0944214000, 0.1061864000, 0.1328061000, 0.1839803000, 0.2843639000, 0.5171772000", \ - "0.1511542000, 0.1583000000, 0.1760443000, 0.2154980000, 0.2945386000, 0.4392601000, 0.7041171000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013834100, 0.0038276500, 0.0105904000, 0.0293018000, 0.0810729000, 0.2243140000"); - values("0.0258049000, 0.0287961000, 0.0372633000, 0.0601138000, 0.1212455000, 0.2800027000, 0.7095466000", \ - "0.0257874000, 0.0289506000, 0.0370638000, 0.0600273000, 0.1212707000, 0.2802889000, 0.7105490000", \ - "0.0293723000, 0.0318699000, 0.0385561000, 0.0601383000, 0.1212897000, 0.2801169000, 0.7112838000", \ - "0.0490444000, 0.0506590000, 0.0542409000, 0.0694612000, 0.1227241000, 0.2800868000, 0.7111312000", \ - "0.0844502000, 0.0866605000, 0.0923319000, 0.1085408000, 0.1484248000, 0.2839644000, 0.7109633000", \ - "0.1464882000, 0.1493994000, 0.1578119000, 0.1806522000, 0.2316862000, 0.3408435000, 0.7146481000", \ - "0.2450864000, 0.2492935000, 0.2617000000, 0.2957463000, 0.3747755000, 0.5244851000, 0.8320422000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ba_1") { - leakage_power () { - value : 0.0194758000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0062981000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0066847000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0044071000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0066847000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0046948000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0066847000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0031934000; - when : "A1&A2&!B1_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o21ba"; - cell_leakage_power : 0.0072654050; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040034000, 0.0040015000, 0.0039972000, 0.0039994000, 0.0040044000, 0.0040161000, 0.0040429000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004003400, -0.004000800, -0.003994700, -0.003995900, -0.003998600, -0.004004700, -0.004018900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025030000; - } - pin ("A2") { - capacitance : 0.0024160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040083000, 0.0040092000, 0.0040113000, 0.0040124000, 0.0040149000, 0.0040207000, 0.0040339000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004008900, -0.004004600, -0.003994600, -0.003996200, -0.003999700, -0.004007700, -0.004026200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025760000; - } - pin ("B1_N") { - capacitance : 0.0013550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080696000, 0.0079741000, 0.0077539000, 0.0078117000, 0.0079449000, 0.0082521000, 0.0089602000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0044582000, 0.0043933000, 0.0042436000, 0.0042832000, 0.0043743000, 0.0045843000, 0.0050684000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0013970000; - } - pin ("X") { - direction : "output"; - function : "(A1&!B1_N) | (A2&!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0123744000, 0.0113586000, 0.0086891000, 0.0007367000, -0.021744800, -0.081481400, -0.237630600", \ - "0.0121798000, 0.0111725000, 0.0085277000, 0.0005592000, -0.021882000, -0.081602100, -0.237747900", \ - "0.0120576000, 0.0110325000, 0.0084023000, 0.0004441000, -0.022025100, -0.081758400, -0.237951600", \ - "0.0118568000, 0.0108574000, 0.0081838000, 0.0002393000, -0.022213200, -0.081913700, -0.238062300", \ - "0.0118072000, 0.0107470000, 0.0080546000, 7.570000e-05, -0.022392500, -0.082066100, -0.238138000", \ - "0.0125986000, 0.0113348000, 0.0079579000, -0.000503300, -0.022636600, -0.082197100, -0.238274200", \ - "0.0137278000, 0.0123843000, 0.0089952000, 0.0006076000, -0.022215100, -0.081667100, -0.237683900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0156352000, 0.0170869000, 0.0207235000, 0.0298096000, 0.0527869000, 0.1122577000, 0.2669766000", \ - "0.0155239000, 0.0169589000, 0.0206111000, 0.0296984000, 0.0526791000, 0.1121490000, 0.2668633000", \ - "0.0153682000, 0.0168065000, 0.0204542000, 0.0295286000, 0.0525101000, 0.1120460000, 0.2667187000", \ - "0.0151858000, 0.0166091000, 0.0202265000, 0.0292833000, 0.0523050000, 0.1118787000, 0.2664144000", \ - "0.0151121000, 0.0165091000, 0.0200938000, 0.0290474000, 0.0521079000, 0.1116255000, 0.2663684000", \ - "0.0154520000, 0.0167942000, 0.0202373000, 0.0290050000, 0.0520629000, 0.1111586000, 0.2661952000", \ - "0.0162845000, 0.0175946000, 0.0211392000, 0.0299069000, 0.0529510000, 0.1125713000, 0.2659060000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0102956000, 0.0092786000, 0.0065955000, -0.001336800, -0.023802600, -0.083544100, -0.239671800", \ - "0.0100561000, 0.0090558000, 0.0063935000, -0.001534300, -0.024005100, -0.083747000, -0.239926500", \ - "0.0098441000, 0.0088337000, 0.0061554000, -0.001786100, -0.024262300, -0.083986100, -0.240127800", \ - "0.0096144000, 0.0086353000, 0.0059370000, -0.002029800, -0.024480900, -0.084175000, -0.240317600", \ - "0.0096564000, 0.0086139000, 0.0058661000, -0.002140000, -0.024627400, -0.084283700, -0.240391600", \ - "0.0107348000, 0.0098831000, 0.0064760000, -0.001853800, -0.024042600, -0.083597700, -0.239629800", \ - "0.0131392000, 0.0118296000, 0.0083877000, -0.000472300, -0.022976000, -0.082348900, -0.238368900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0143306000, 0.0157794000, 0.0194553000, 0.0285381000, 0.0513829000, 0.1108788000, 0.2656847000", \ - "0.0142584000, 0.0157190000, 0.0193661000, 0.0283878000, 0.0513125000, 0.1108767000, 0.2657083000", \ - "0.0140022000, 0.0154581000, 0.0191092000, 0.0281747000, 0.0510755000, 0.1104880000, 0.2657746000", \ - "0.0136901000, 0.0150889000, 0.0187068000, 0.0277616000, 0.0506827000, 0.1101409000, 0.2639132000", \ - "0.0135673000, 0.0148623000, 0.0184473000, 0.0274216000, 0.0503641000, 0.1099864000, 0.2647310000", \ - "0.0138042000, 0.0151318000, 0.0185923000, 0.0273603000, 0.0503587000, 0.1094866000, 0.2646577000", \ - "0.0146249000, 0.0159197000, 0.0193729000, 0.0283517000, 0.0513243000, 0.1110184000, 0.2640954000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0103355000, 0.0093874000, 0.0068765000, -0.001107600, -0.023800700, -0.083676800, -0.239950100", \ - "0.0102977000, 0.0093682000, 0.0068552000, -0.001126900, -0.023825300, -0.083693600, -0.239952900", \ - "0.0102093000, 0.0092787000, 0.0067554000, -0.001216800, -0.023904700, -0.083770900, -0.240030300", \ - "0.0098180000, 0.0088491000, 0.0063329000, -0.001651900, -0.024328700, -0.084178400, -0.240410900", \ - "0.0096424000, 0.0086003000, 0.0059889000, -0.002022700, -0.024684700, -0.084524800, -0.240718800", \ - "0.0109085000, 0.0096803000, 0.0065232000, -0.002000100, -0.024898100, -0.084744800, -0.240972200", \ - "0.0111128000, 0.0099336000, 0.0066146000, -0.001848400, -0.024657100, -0.084519300, -0.240842300"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0139952000, 0.0154348000, 0.0190219000, 0.0280816000, 0.0511138000, 0.1107101000, 0.2655087000", \ - "0.0139353000, 0.0153806000, 0.0190120000, 0.0280661000, 0.0510766000, 0.1106303000, 0.2654143000", \ - "0.0139859000, 0.0154259000, 0.0190497000, 0.0281202000, 0.0511107000, 0.1106626000, 0.2654533000", \ - "0.0137665000, 0.0152043000, 0.0188038000, 0.0278355000, 0.0508794000, 0.1104608000, 0.2652768000", \ - "0.0134037000, 0.0148381000, 0.0184533000, 0.0275061000, 0.0504881000, 0.1101261000, 0.2646635000", \ - "0.0129548000, 0.0144259000, 0.0180845000, 0.0271466000, 0.0501043000, 0.1096500000, 0.2645582000", \ - "0.0134041000, 0.0147329000, 0.0182070000, 0.0271560000, 0.0500239000, 0.1094605000, 0.2645906000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.5055210000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1457191000, 0.1525492000, 0.1666010000, 0.1939910000, 0.2499436000, 0.3792698000, 0.7101252000", \ - "0.1508914000, 0.1577091000, 0.1718566000, 0.1992534000, 0.2552659000, 0.3846051000, 0.7150214000", \ - "0.1629105000, 0.1697358000, 0.1838023000, 0.2112003000, 0.2671734000, 0.3964822000, 0.7270161000", \ - "0.1888591000, 0.1956497000, 0.2097063000, 0.2372285000, 0.2932561000, 0.4226357000, 0.7540888000", \ - "0.2458480000, 0.2527273000, 0.2666848000, 0.2943493000, 0.3504628000, 0.4799388000, 0.8102889000", \ - "0.3479622000, 0.3558926000, 0.3717191000, 0.4022400000, 0.4613897000, 0.5925478000, 0.9229369000", \ - "0.5179330000, 0.5277971000, 0.5470108000, 0.5818933000, 0.6471300000, 0.7819841000, 1.1141885000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0912567000, 0.0985864000, 0.1152688000, 0.1541379000, 0.2501897000, 0.4974626000, 1.1397029000", \ - "0.0956611000, 0.1029938000, 0.1196798000, 0.1585581000, 0.2546288000, 0.5018743000, 1.1441356000", \ - "0.1045698000, 0.1119028000, 0.1286419000, 0.1674789000, 0.2637210000, 0.5105161000, 1.1548096000", \ - "0.1226641000, 0.1300196000, 0.1466648000, 0.1854200000, 0.2818763000, 0.5295767000, 1.1743861000", \ - "0.1553541000, 0.1630650000, 0.1804077000, 0.2194833000, 0.3158794000, 0.5635152000, 1.2048003000", \ - "0.1984078000, 0.2073589000, 0.2260366000, 0.2662958000, 0.3627637000, 0.6103259000, 1.2532680000", \ - "0.2325917000, 0.2441418000, 0.2672309000, 0.3111948000, 0.4086639000, 0.6560188000, 1.2984607000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0243826000, 0.0289235000, 0.0391636000, 0.0636294000, 0.1238244000, 0.2870916000, 0.7272859000", \ - "0.0241071000, 0.0286558000, 0.0391479000, 0.0637858000, 0.1232967000, 0.2869878000, 0.7269031000", \ - "0.0244801000, 0.0290447000, 0.0391907000, 0.0636248000, 0.1237054000, 0.2872549000, 0.7271081000", \ - "0.0241089000, 0.0286266000, 0.0394761000, 0.0637053000, 0.1236850000, 0.2872508000, 0.7271990000", \ - "0.0252655000, 0.0296178000, 0.0400590000, 0.0644262000, 0.1237604000, 0.2876455000, 0.7244230000", \ - "0.0304101000, 0.0352570000, 0.0461388000, 0.0705799000, 0.1291867000, 0.2886723000, 0.7271459000", \ - "0.0409467000, 0.0467856000, 0.0589639000, 0.0841078000, 0.1410763000, 0.2951734000, 0.7241165000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0243041000, 0.0316069000, 0.0502882000, 0.1000027000, 0.2333903000, 0.5824572000, 1.4985787000", \ - "0.0243069000, 0.0316003000, 0.0502820000, 0.0999878000, 0.2333782000, 0.5824378000, 1.4986662000", \ - "0.0242887000, 0.0315752000, 0.0503147000, 0.1002076000, 0.2328177000, 0.5843449000, 1.4999144000", \ - "0.0245548000, 0.0319336000, 0.0504572000, 0.1001923000, 0.2335095000, 0.5848072000, 1.4973859000", \ - "0.0266189000, 0.0339414000, 0.0523140000, 0.1009906000, 0.2337305000, 0.5841716000, 1.4953192000", \ - "0.0321889000, 0.0394512000, 0.0566981000, 0.1035424000, 0.2347163000, 0.5816835000, 1.4940708000", \ - "0.0439355000, 0.0515903000, 0.0692425000, 0.1113947000, 0.2362912000, 0.5836860000, 1.4935624000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1342271000, 0.1409050000, 0.1549761000, 0.1825657000, 0.2385014000, 0.3679025000, 0.6991757000", \ - "0.1376129000, 0.1444579000, 0.1585488000, 0.1861210000, 0.2420604000, 0.3713530000, 0.7017765000", \ - "0.1483545000, 0.1551384000, 0.1692168000, 0.1966727000, 0.2526526000, 0.3819059000, 0.7121443000", \ - "0.1763260000, 0.1831398000, 0.1971838000, 0.2246892000, 0.2807264000, 0.4101283000, 0.7416699000", \ - "0.2434630000, 0.2502651000, 0.2642502000, 0.2918172000, 0.3479684000, 0.4774357000, 0.8089872000", \ - "0.3627020000, 0.3714281000, 0.3877263000, 0.4177465000, 0.4764496000, 0.6081404000, 0.9381074000", \ - "0.5536160000, 0.5643809000, 0.5854554000, 0.6212961000, 0.6836834000, 0.8171646000, 1.1499111000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0784862000, 0.0856246000, 0.1020129000, 0.1404996000, 0.2362289000, 0.4826429000, 1.1248916000", \ - "0.0831675000, 0.0902943000, 0.1066744000, 0.1451426000, 0.2409128000, 0.4873871000, 1.1327906000", \ - "0.0917861000, 0.0989436000, 0.1152507000, 0.1537120000, 0.2496296000, 0.4966240000, 1.1437030000", \ - "0.1086504000, 0.1157565000, 0.1321189000, 0.1704640000, 0.2663242000, 0.5135511000, 1.1544121000", \ - "0.1349004000, 0.1424419000, 0.1595377000, 0.1984850000, 0.2945879000, 0.5417181000, 1.1904985000", \ - "0.1640263000, 0.1732772000, 0.1922698000, 0.2323230000, 0.3287781000, 0.5759593000, 1.2214481000", \ - "0.1702606000, 0.1826587000, 0.2071302000, 0.2523059000, 0.3496221000, 0.5979309000, 1.2399097000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0244118000, 0.0289503000, 0.0396417000, 0.0637242000, 0.1233675000, 0.2871831000, 0.7270799000", \ - "0.0243545000, 0.0289589000, 0.0395014000, 0.0636572000, 0.1235858000, 0.2871511000, 0.7270620000", \ - "0.0243156000, 0.0287637000, 0.0395937000, 0.0635644000, 0.1233739000, 0.2862292000, 0.7327431000", \ - "0.0241566000, 0.0287247000, 0.0392538000, 0.0635793000, 0.1237571000, 0.2872593000, 0.7272600000", \ - "0.0250373000, 0.0299848000, 0.0398586000, 0.0645505000, 0.1236813000, 0.2864141000, 0.7282082000", \ - "0.0340847000, 0.0385751000, 0.0482857000, 0.0709769000, 0.1287131000, 0.2885729000, 0.7335973000", \ - "0.0482943000, 0.0540997000, 0.0646036000, 0.0865733000, 0.1406015000, 0.2937471000, 0.7261397000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0230705000, 0.0303516000, 0.0490817000, 0.0992313000, 0.2324072000, 0.5834756000, 1.5030102000", \ - "0.0230337000, 0.0302731000, 0.0490810000, 0.0993038000, 0.2320858000, 0.5855249000, 1.5050207000", \ - "0.0230570000, 0.0303240000, 0.0490456000, 0.0992365000, 0.2326879000, 0.5837348000, 1.5042099000", \ - "0.0236256000, 0.0308226000, 0.0493787000, 0.0992869000, 0.2321120000, 0.5840728000, 1.4961087000", \ - "0.0264432000, 0.0336340000, 0.0516439000, 0.1004767000, 0.2329572000, 0.5854485000, 1.5055213000", \ - "0.0341805000, 0.0405426000, 0.0574906000, 0.1034378000, 0.2342823000, 0.5815747000, 1.5004714000", \ - "0.0475358000, 0.0555958000, 0.0722196000, 0.1140492000, 0.2369723000, 0.5851354000, 1.4910670000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1066121000, 0.1125583000, 0.1254554000, 0.1514630000, 0.2052875000, 0.3332147000, 0.6646694000", \ - "0.1115238000, 0.1174639000, 0.1303430000, 0.1563798000, 0.2102387000, 0.3380564000, 0.6676942000", \ - "0.1225793000, 0.1284933000, 0.1413946000, 0.1673843000, 0.2212277000, 0.3491734000, 0.6801442000", \ - "0.1443767000, 0.1502896000, 0.1631435000, 0.1891511000, 0.2430277000, 0.3709960000, 0.7020659000", \ - "0.1761225000, 0.1820290000, 0.1948701000, 0.2209689000, 0.2749028000, 0.4028573000, 0.7332067000", \ - "0.2156885000, 0.2216234000, 0.2346316000, 0.2609477000, 0.3151125000, 0.4429739000, 0.7730718000", \ - "0.2503976000, 0.2566364000, 0.2703002000, 0.2975815000, 0.3524971000, 0.4805263000, 0.8119508000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1705885000, 0.1779284000, 0.1945783000, 0.2333895000, 0.3299224000, 0.5777516000, 1.2195529000", \ - "0.1754466000, 0.1828478000, 0.1994885000, 0.2383616000, 0.3346201000, 0.5820825000, 1.2250317000", \ - "0.1880298000, 0.1953698000, 0.2120623000, 0.2509356000, 0.3470392000, 0.5948718000, 1.2360937000", \ - "0.2195842000, 0.2269429000, 0.2436485000, 0.2824132000, 0.3789056000, 0.6266793000, 1.2685965000", \ - "0.2891949000, 0.2965857000, 0.3132936000, 0.3521817000, 0.4485173000, 0.6968743000, 1.3387506000", \ - "0.4087677000, 0.4161817000, 0.4330615000, 0.4721339000, 0.5686749000, 0.8160890000, 1.4590363000", \ - "0.5989687000, 0.6066959000, 0.6238388000, 0.6630680000, 0.7605842000, 1.0078413000, 1.6505961000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0181013000, 0.0230548000, 0.0345153000, 0.0593729000, 0.1193972000, 0.2841939000, 0.7266509000", \ - "0.0181678000, 0.0231125000, 0.0345889000, 0.0594053000, 0.1194135000, 0.2840198000, 0.7289587000", \ - "0.0182029000, 0.0230659000, 0.0345525000, 0.0594662000, 0.1194170000, 0.2841137000, 0.7274083000", \ - "0.0181607000, 0.0231575000, 0.0346572000, 0.0595491000, 0.1194452000, 0.2840023000, 0.7235200000", \ - "0.0183909000, 0.0233941000, 0.0348857000, 0.0592040000, 0.1196278000, 0.2848808000, 0.7308522000", \ - "0.0190976000, 0.0238920000, 0.0353745000, 0.0601950000, 0.1197962000, 0.2824424000, 0.7295040000", \ - "0.0213412000, 0.0263369000, 0.0377989000, 0.0623536000, 0.1209786000, 0.2846874000, 0.7260429000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0244854000, 0.0318030000, 0.0506296000, 0.1003307000, 0.2334749000, 0.5848299000, 1.4974462000", \ - "0.0246152000, 0.0318644000, 0.0506216000, 0.1004104000, 0.2333612000, 0.5823715000, 1.4994547000", \ - "0.0245661000, 0.0318878000, 0.0505883000, 0.1001452000, 0.2333411000, 0.5839597000, 1.4958945000", \ - "0.0245115000, 0.0318581000, 0.0505997000, 0.1003495000, 0.2334810000, 0.5848755000, 1.4975179000", \ - "0.0246476000, 0.0319841000, 0.0506861000, 0.1004178000, 0.2333428000, 0.5838821000, 1.4991944000", \ - "0.0253696000, 0.0327070000, 0.0513531000, 0.1010670000, 0.2335233000, 0.5837603000, 1.4997427000", \ - "0.0273721000, 0.0343382000, 0.0527390000, 0.1023651000, 0.2346819000, 0.5815240000, 1.4990083000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ba_2") { - leakage_power () { - value : 0.0029671000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0030880000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0032197000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0025417000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0032197000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0029198000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0032197000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0017887000; - when : "A1&A2&!B1_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o21ba"; - cell_leakage_power : 0.0028705310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040632000, 0.0040547000, 0.0040349000, 0.0040336000, 0.0040305000, 0.0040234000, 0.0040069000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004039100, -0.004037100, -0.004032500, -0.004033400, -0.004035500, -0.004040300, -0.004051400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025040000; - } - pin ("A2") { - capacitance : 0.0023780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039735000, 0.0039731000, 0.0039722000, 0.0039733000, 0.0039759000, 0.0039818000, 0.0039954000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003977500, -0.003974500, -0.003967600, -0.003968400, -0.003970100, -0.003974100, -0.003983200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025470000; - } - pin ("B1_N") { - capacitance : 0.0013850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079652000, 0.0078723000, 0.0076584000, 0.0077175000, 0.0078537000, 0.0081678000, 0.0088916000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0051478000, 0.0050950000, 0.0049732000, 0.0050163000, 0.0051156000, 0.0053446000, 0.0058724000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014370000; - } - pin ("X") { - direction : "output"; - function : "(A1&!B1_N) | (A2&!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0151537000, 0.0137350000, 0.0101925000, -0.000176100, -0.032986100, -0.130106700, -0.407797900", \ - "0.0150183000, 0.0136230000, 0.0101053000, -0.000304500, -0.033098600, -0.130221700, -0.407884600", \ - "0.0149420000, 0.0135583000, 0.0099745000, -0.000363200, -0.033221800, -0.130318700, -0.408007200", \ - "0.0147225000, 0.0133313000, 0.0097491000, -0.000600900, -0.033384500, -0.130472600, -0.408171800", \ - "0.0147046000, 0.0132766000, 0.0096482000, -0.000777700, -0.033602600, -0.130666400, -0.408320900", \ - "0.0151151000, 0.0140825000, 0.0096591000, -0.001114600, -0.033758000, -0.130774900, -0.408377800", \ - "0.0181750000, 0.0165689000, 0.0122793000, 0.0007149000, -0.033451800, -0.130512500, -0.407979000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0202025000, 0.0218426000, 0.0264337000, 0.0389401000, 0.0734901000, 0.1703719000, 0.4450428000", \ - "0.0201029000, 0.0217363000, 0.0263466000, 0.0387855000, 0.0733924000, 0.1702192000, 0.4447464000", \ - "0.0199462000, 0.0216001000, 0.0261419000, 0.0387207000, 0.0732014000, 0.1703286000, 0.4450129000", \ - "0.0197968000, 0.0214538000, 0.0260508000, 0.0385294000, 0.0730489000, 0.1700817000, 0.4448349000", \ - "0.0197632000, 0.0213843000, 0.0259549000, 0.0382286000, 0.0727510000, 0.1698157000, 0.4444698000", \ - "0.0202702000, 0.0217916000, 0.0261389000, 0.0381219000, 0.0724908000, 0.1692562000, 0.4441543000", \ - "0.0210758000, 0.0225463000, 0.0268210000, 0.0389787000, 0.0732098000, 0.1700643000, 0.4437447000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0131533000, 0.0117567000, 0.0082029000, -0.002155700, -0.034997200, -0.132056400, -0.409781300", \ - "0.0129371000, 0.0115666000, 0.0079977000, -0.002373200, -0.035168700, -0.132251500, -0.409969400", \ - "0.0127500000, 0.0113561000, 0.0078208000, -0.002564600, -0.035368300, -0.132469700, -0.410147300", \ - "0.0125850000, 0.0111696000, 0.0076325000, -0.002770800, -0.035628900, -0.132677400, -0.410354700", \ - "0.0128279000, 0.0113905000, 0.0077276000, -0.002730800, -0.035618100, -0.132689000, -0.410332400", \ - "0.0126270000, 0.0110506000, 0.0072346000, -0.002775600, -0.035519600, -0.132412200, -0.409945000", \ - "0.0176784000, 0.0160802000, 0.0116892000, -0.000779100, -0.034861400, -0.131624200, -0.409125100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0188627000, 0.0205286000, 0.0251473000, 0.0377094000, 0.0721908000, 0.1690732000, 0.4440976000", \ - "0.0188359000, 0.0205010000, 0.0250362000, 0.0376595000, 0.0720955000, 0.1689503000, 0.4439225000", \ - "0.0186452000, 0.0203098000, 0.0249314000, 0.0375054000, 0.0719990000, 0.1688115000, 0.4440376000", \ - "0.0183961000, 0.0200347000, 0.0245739000, 0.0370777000, 0.0715984000, 0.1684174000, 0.4421616000", \ - "0.0181292000, 0.0197128000, 0.0242998000, 0.0366819000, 0.0710626000, 0.1681429000, 0.4418819000", \ - "0.0185434000, 0.0200776000, 0.0244548000, 0.0366910000, 0.0708474000, 0.1673331000, 0.4429764000", \ - "0.0193831000, 0.0208564000, 0.0250670000, 0.0372319000, 0.0712115000, 0.1679961000, 0.4419019000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0129103000, 0.0116714000, 0.0084454000, -0.001861600, -0.035215800, -0.132718600, -0.410595700", \ - "0.0129103000, 0.0116834000, 0.0084749000, -0.001891400, -0.035222100, -0.132724300, -0.410592300", \ - "0.0128524000, 0.0115899000, 0.0083871000, -0.001951000, -0.035303900, -0.132796700, -0.410670600", \ - "0.0124009000, 0.0112010000, 0.0079477000, -0.002382400, -0.035725200, -0.133207800, -0.411051300", \ - "0.0120619000, 0.0108672000, 0.0075862000, -0.002741200, -0.036071300, -0.133537700, -0.411388800", \ - "0.0149702000, 0.0135836000, 0.0096118000, -0.002129700, -0.036298200, -0.133844500, -0.411685700", \ - "0.0149724000, 0.0135282000, 0.0095379000, -0.002147000, -0.036212000, -0.133795500, -0.411737100"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014220210, 0.0040442850, 0.0115021200, 0.0327124900, 0.0930356800, 0.2645973000"); - values("0.0186950000, 0.0203368000, 0.0248623000, 0.0373863000, 0.0719120000, 0.1689468000, 0.4438713000", \ - "0.0186423000, 0.0203066000, 0.0248643000, 0.0373518000, 0.0718595000, 0.1688597000, 0.4440897000", \ - "0.0187197000, 0.0203426000, 0.0248675000, 0.0373877000, 0.0719121000, 0.1689119000, 0.4438845000", \ - "0.0185003000, 0.0201371000, 0.0246464000, 0.0371608000, 0.0716831000, 0.1686628000, 0.4431619000", \ - "0.0182078000, 0.0198340000, 0.0244350000, 0.0369208000, 0.0714136000, 0.1685849000, 0.4437331000", \ - "0.0177730000, 0.0194001000, 0.0239249000, 0.0364144000, 0.0708994000, 0.1679079000, 0.4430897000", \ - "0.0184472000, 0.0199809000, 0.0243377000, 0.0364972000, 0.0707338000, 0.1679540000, 0.4424655000"); - } - } - max_capacitance : 0.2645970000; - max_transition : 1.5029580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1759621000, 0.1819530000, 0.1950053000, 0.2205354000, 0.2698863000, 0.3799800000, 0.6686636000", \ - "0.1812555000, 0.1872894000, 0.2001190000, 0.2255683000, 0.2753545000, 0.3853120000, 0.6742462000", \ - "0.1935121000, 0.1995294000, 0.2125651000, 0.2380006000, 0.2877379000, 0.3973860000, 0.6862694000", \ - "0.2196711000, 0.2256028000, 0.2386482000, 0.2641980000, 0.3137102000, 0.4234974000, 0.7119756000", \ - "0.2784834000, 0.2844376000, 0.2974056000, 0.3228885000, 0.3726336000, 0.4825631000, 0.7711272000", \ - "0.3920725000, 0.3997397000, 0.4140787000, 0.4417102000, 0.4940552000, 0.6061936000, 0.8951497000", \ - "0.5854540000, 0.5935102000, 0.6113466000, 0.6441981000, 0.7037992000, 0.8223507000, 1.1137606000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1043124000, 0.1103974000, 0.1245980000, 0.1576354000, 0.2416418000, 0.4734050000, 1.1297459000", \ - "0.1088045000, 0.1148797000, 0.1291293000, 0.1621324000, 0.2461912000, 0.4778448000, 1.1342763000", \ - "0.1176541000, 0.1237357000, 0.1379282000, 0.1710288000, 0.2548500000, 0.4875700000, 1.1428858000", \ - "0.1362481000, 0.1423387000, 0.1565537000, 0.1894958000, 0.2733819000, 0.5051354000, 1.1612343000", \ - "0.1722687000, 0.1786429000, 0.1934582000, 0.2270050000, 0.3108551000, 0.5433246000, 1.2001786000", \ - "0.2239012000, 0.2313806000, 0.2478088000, 0.2832139000, 0.3682354000, 0.6000368000, 1.2566335000", \ - "0.2734165000, 0.2831717000, 0.3041428000, 0.3444768000, 0.4317038000, 0.6640916000, 1.3194432000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0272424000, 0.0308528000, 0.0388783000, 0.0566006000, 0.1024426000, 0.2274208000, 0.6081990000", \ - "0.0273231000, 0.0306939000, 0.0391357000, 0.0569941000, 0.1021114000, 0.2276469000, 0.6080954000", \ - "0.0274218000, 0.0309076000, 0.0390800000, 0.0570117000, 0.1021358000, 0.2278107000, 0.6080654000", \ - "0.0272035000, 0.0309654000, 0.0389652000, 0.0564938000, 0.1022340000, 0.2277471000, 0.6088535000", \ - "0.0272607000, 0.0307558000, 0.0385820000, 0.0568434000, 0.1021642000, 0.2274835000, 0.6055744000", \ - "0.0329661000, 0.0369491000, 0.0452198000, 0.0638340000, 0.1068000000, 0.2301753000, 0.6095633000", \ - "0.0444738000, 0.0487364000, 0.0579045000, 0.0771998000, 0.1218348000, 0.2412149000, 0.6075920000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0226253000, 0.0280069000, 0.0423286000, 0.0819058000, 0.1981990000, 0.5354753000, 1.5009504000", \ - "0.0227160000, 0.0280237000, 0.0422573000, 0.0818708000, 0.1983593000, 0.5359704000, 1.5005845000", \ - "0.0226234000, 0.0280040000, 0.0423229000, 0.0819955000, 0.1978344000, 0.5368693000, 1.4999578000", \ - "0.0226971000, 0.0280822000, 0.0422619000, 0.0817755000, 0.1982579000, 0.5367840000, 1.5006300000", \ - "0.0247574000, 0.0301571000, 0.0441744000, 0.0832461000, 0.1983641000, 0.5359673000, 1.4982038000", \ - "0.0303962000, 0.0355893000, 0.0497229000, 0.0872900000, 0.2006152000, 0.5355940000, 1.4997303000", \ - "0.0423077000, 0.0484335000, 0.0631863000, 0.0979782000, 0.2046938000, 0.5365157000, 1.4951385000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1637799000, 0.1698251000, 0.1827926000, 0.2084048000, 0.2579712000, 0.3677004000, 0.6566286000", \ - "0.1672194000, 0.1732428000, 0.1862970000, 0.2115529000, 0.2613949000, 0.3711375000, 0.6599356000", \ - "0.1781848000, 0.1841999000, 0.1971448000, 0.2225320000, 0.2721901000, 0.3820366000, 0.6709006000", \ - "0.2063092000, 0.2122783000, 0.2252013000, 0.2506710000, 0.3003665000, 0.4102450000, 0.6987849000", \ - "0.2749678000, 0.2808885000, 0.2937602000, 0.3183283000, 0.3681155000, 0.4780786000, 0.7668882000", \ - "0.4123633000, 0.4197730000, 0.4348601000, 0.4631117000, 0.5153769000, 0.6272724000, 0.9159826000", \ - "0.6334548000, 0.6426388000, 0.6626337000, 0.6985965000, 0.7595296000, 0.8765793000, 1.1676182000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0894020000, 0.0951940000, 0.1089733000, 0.1413521000, 0.2243730000, 0.4558014000, 1.1127167000", \ - "0.0942165000, 0.1000174000, 0.1136694000, 0.1460638000, 0.2292311000, 0.4607626000, 1.1169213000", \ - "0.1031706000, 0.1089763000, 0.1226727000, 0.1550430000, 0.2385198000, 0.4697284000, 1.1273334000", \ - "0.1213193000, 0.1270559000, 0.1406921000, 0.1728786000, 0.2564086000, 0.4877214000, 1.1506336000", \ - "0.1526771000, 0.1589736000, 0.1734417000, 0.2065024000, 0.2901199000, 0.5220455000, 1.1763882000", \ - "0.1920892000, 0.1997172000, 0.2160512000, 0.2513009000, 0.3357616000, 0.5672529000, 1.2252471000", \ - "0.2159098000, 0.2262401000, 0.2479614000, 0.2896931000, 0.3765418000, 0.6083257000, 1.2632841000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0271534000, 0.0307285000, 0.0385760000, 0.0564562000, 0.1022217000, 0.2275336000, 0.6080666000", \ - "0.0273486000, 0.0309116000, 0.0389227000, 0.0569896000, 0.1020268000, 0.2275334000, 0.6082524000", \ - "0.0272250000, 0.0306719000, 0.0388095000, 0.0570892000, 0.1022854000, 0.2278077000, 0.6088688000", \ - "0.0271929000, 0.0306403000, 0.0386919000, 0.0573515000, 0.1020368000, 0.2277111000, 0.6076901000", \ - "0.0272839000, 0.0308829000, 0.0388674000, 0.0571736000, 0.1021375000, 0.2282999000, 0.6090574000", \ - "0.0367120000, 0.0399080000, 0.0477401000, 0.0644879000, 0.1074309000, 0.2303869000, 0.6099425000", \ - "0.0531384000, 0.0578083000, 0.0676882000, 0.0857394000, 0.1250414000, 0.2409333000, 0.6090315000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0213066000, 0.0265213000, 0.0405867000, 0.0803178000, 0.1966712000, 0.5347648000, 1.4997117000", \ - "0.0212751000, 0.0265101000, 0.0405709000, 0.0801547000, 0.1968526000, 0.5355360000, 1.5005059000", \ - "0.0212698000, 0.0264069000, 0.0405439000, 0.0802093000, 0.1968294000, 0.5341472000, 1.5029159000", \ - "0.0214529000, 0.0266079000, 0.0407156000, 0.0801568000, 0.1968073000, 0.5348942000, 1.5029582000", \ - "0.0240613000, 0.0295123000, 0.0433914000, 0.0820957000, 0.1977297000, 0.5347350000, 1.5006067000", \ - "0.0314273000, 0.0370228000, 0.0505087000, 0.0869283000, 0.1996509000, 0.5356950000, 1.5012915000", \ - "0.0446841000, 0.0514087000, 0.0653429000, 0.1001698000, 0.2047224000, 0.5377282000, 1.4956658000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1229225000, 0.1275115000, 0.1379858000, 0.1601586000, 0.2058941000, 0.3115138000, 0.5993377000", \ - "0.1278053000, 0.1324179000, 0.1428659000, 0.1650590000, 0.2108043000, 0.3164981000, 0.6036622000", \ - "0.1388158000, 0.1434173000, 0.1538569000, 0.1761309000, 0.2218775000, 0.3275507000, 0.6153590000", \ - "0.1612667000, 0.1658373000, 0.1762856000, 0.1985263000, 0.2442953000, 0.3500183000, 0.6370845000", \ - "0.1941651000, 0.1987576000, 0.2091977000, 0.2313794000, 0.2771902000, 0.3828423000, 0.6707632000", \ - "0.2352998000, 0.2399434000, 0.2504250000, 0.2726311000, 0.3186079000, 0.4243647000, 0.7119585000", \ - "0.2728862000, 0.2776787000, 0.2885256000, 0.3113830000, 0.3578457000, 0.4639092000, 0.7516926000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.1918952000, 0.1979881000, 0.2122060000, 0.2452505000, 0.3291760000, 0.5620121000, 1.2175259000", \ - "0.1965844000, 0.2029095000, 0.2169790000, 0.2502666000, 0.3340734000, 0.5664779000, 1.2238661000", \ - "0.2095169000, 0.2156103000, 0.2298177000, 0.2628872000, 0.3468700000, 0.5786880000, 1.2357683000", \ - "0.2412157000, 0.2472700000, 0.2615749000, 0.2946672000, 0.3783785000, 0.6098907000, 1.2655668000", \ - "0.3122251000, 0.3183200000, 0.3326328000, 0.3656970000, 0.4494667000, 0.6821806000, 1.3379028000", \ - "0.4400996000, 0.4462535000, 0.4606145000, 0.4939204000, 0.5777688000, 0.8100460000, 1.4675686000", \ - "0.6450730000, 0.6514434000, 0.6662168000, 0.6998069000, 0.7838711000, 1.0163512000, 1.6719199000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0176349000, 0.0209954000, 0.0290670000, 0.0485268000, 0.0939872000, 0.2209829000, 0.6019817000", \ - "0.0176600000, 0.0208786000, 0.0289641000, 0.0487119000, 0.0939685000, 0.2213801000, 0.6071056000", \ - "0.0176584000, 0.0209288000, 0.0289628000, 0.0485285000, 0.0939878000, 0.2212003000, 0.6030501000", \ - "0.0176466000, 0.0209288000, 0.0290431000, 0.0485300000, 0.0939771000, 0.2211883000, 0.6075398000", \ - "0.0178144000, 0.0211235000, 0.0291874000, 0.0485379000, 0.0940005000, 0.2213417000, 0.6018560000", \ - "0.0183805000, 0.0216647000, 0.0296351000, 0.0489690000, 0.0942810000, 0.2204805000, 0.6064320000", \ - "0.0196774000, 0.0230000000, 0.0310762000, 0.0504234000, 0.0953155000, 0.2217982000, 0.6046568000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014220200, 0.0040442900, 0.0115021000, 0.0327125000, 0.0930357000, 0.2645970000"); - values("0.0229162000, 0.0282249000, 0.0426194000, 0.0820957000, 0.1979793000, 0.5368267000, 1.4999317000", \ - "0.0229574000, 0.0282453000, 0.0425565000, 0.0821788000, 0.1979004000, 0.5358604000, 1.4994360000", \ - "0.0230115000, 0.0282871000, 0.0426016000, 0.0820840000, 0.1982097000, 0.5363541000, 1.4975713000", \ - "0.0229306000, 0.0283639000, 0.0425399000, 0.0821982000, 0.1978221000, 0.5368794000, 1.5020036000", \ - "0.0231522000, 0.0283993000, 0.0425994000, 0.0822323000, 0.1978342000, 0.5365846000, 1.5026185000", \ - "0.0237544000, 0.0289966000, 0.0433794000, 0.0827934000, 0.1986089000, 0.5359822000, 1.5014309000", \ - "0.0259531000, 0.0309799000, 0.0449073000, 0.0840527000, 0.1994471000, 0.5352709000, 1.5005975000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21ba_4") { - leakage_power () { - value : 0.0041175000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0043530000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0047840000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0087956000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0047840000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0073377000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0047835000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0053552000; - when : "A1&A2&!B1_N"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__o21ba"; - cell_leakage_power : 0.0055388110; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079288000, 0.0079283000, 0.0079274000, 0.0079279000, 0.0079292000, 0.0079322000, 0.0079390000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007923000, -0.007919700, -0.007912000, -0.007908600, -0.007900800, -0.007882700, -0.007841200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046170000; - } - pin ("A2") { - capacitance : 0.0043840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079257000, 0.0079215000, 0.0079119000, 0.0079149000, 0.0079218000, 0.0079376000, 0.0079740000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007909000, -0.007904900, -0.007895300, -0.007896800, -0.007900200, -0.007908100, -0.007926400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047070000; - } - pin ("B1_N") { - capacitance : 0.0023920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0147969000, 0.0146597000, 0.0143436000, 0.0144893000, 0.0148252000, 0.0155995000, 0.0173842000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0094873000, 0.0093640000, 0.0090796000, 0.0091595000, 0.0093435000, 0.0097678000, 0.0107457000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025120000; - } - pin ("X") { - direction : "output"; - function : "(A1&!B1_N) | (A2&!B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0304762000, 0.0288187000, 0.0239638000, 0.0101763000, -0.037483800, -0.195425500, -0.691926100", \ - "0.0301900000, 0.0284700000, 0.0236224000, 0.0097784000, -0.037798900, -0.195629500, -0.692175000", \ - "0.0298331000, 0.0282524000, 0.0234023000, 0.0095797000, -0.038045400, -0.195982200, -0.692484100", \ - "0.0294591000, 0.0279212000, 0.0230334000, 0.0090792000, -0.038482100, -0.196304900, -0.692774400", \ - "0.0292828000, 0.0275721000, 0.0227131000, 0.0086940000, -0.038913400, -0.196779300, -0.693147800", \ - "0.0288276000, 0.0270343000, 0.0216744000, 0.0075652000, -0.039580300, -0.197025600, -0.693328300", \ - "0.0358945000, 0.0340272000, 0.0284409000, 0.0119317000, -0.038803800, -0.197410800, -0.692850100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0397647000, 0.0416476000, 0.0473767000, 0.0648559000, 0.1170254000, 0.2762178000, 0.7682191000", \ - "0.0395254000, 0.0414084000, 0.0471584000, 0.0646264000, 0.1168040000, 0.2760240000, 0.7679905000", \ - "0.0392316000, 0.0411166000, 0.0468364000, 0.0642645000, 0.1165063000, 0.2757713000, 0.7670203000", \ - "0.0388468000, 0.0407110000, 0.0465325000, 0.0639421000, 0.1160355000, 0.2752254000, 0.7672805000", \ - "0.0385870000, 0.0404561000, 0.0461100000, 0.0633301000, 0.1153772000, 0.2747940000, 0.7663932000", \ - "0.0395287000, 0.0412950000, 0.0467589000, 0.0634170000, 0.1147725000, 0.2734176000, 0.7657848000", \ - "0.0411861000, 0.0428661000, 0.0481916000, 0.0647268000, 0.1163761000, 0.2748467000, 0.7652079000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0259273000, 0.0242716000, 0.0193252000, 0.0055112000, -0.042012100, -0.199926200, -0.696382400", \ - "0.0255366000, 0.0238435000, 0.0191092000, 0.0051723000, -0.042373300, -0.200272600, -0.696806300", \ - "0.0250297000, 0.0234059000, 0.0186670000, 0.0046989000, -0.042808100, -0.200661400, -0.697208700", \ - "0.0247374000, 0.0230638000, 0.0182760000, 0.0043033000, -0.043201200, -0.201093900, -0.697543400", \ - "0.0252223000, 0.0235097000, 0.0185573000, 0.0043747000, -0.043484400, -0.201376300, -0.697727400", \ - "0.0255854000, 0.0237733000, 0.0183043000, 0.0040758000, -0.042687300, -0.200485500, -0.696726500", \ - "0.0348521000, 0.0328497000, 0.0271751000, 0.0105498000, -0.040520500, -0.199012300, -0.694443300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0357777000, 0.0376556000, 0.0434001000, 0.0608219000, 0.1128714000, 0.2714177000, 0.7635393000", \ - "0.0357550000, 0.0375901000, 0.0434019000, 0.0608286000, 0.1128371000, 0.2715402000, 0.7605400000", \ - "0.0354226000, 0.0372926000, 0.0430512000, 0.0605693000, 0.1125127000, 0.2711694000, 0.7603508000", \ - "0.0349296000, 0.0367820000, 0.0425069000, 0.0597851000, 0.1117641000, 0.2705213000, 0.7600991000", \ - "0.0345146000, 0.0363690000, 0.0420517000, 0.0590743000, 0.1108113000, 0.2699351000, 0.7624216000", \ - "0.0352367000, 0.0370292000, 0.0424660000, 0.0593710000, 0.1103848000, 0.2687198000, 0.7619309000", \ - "0.0373751000, 0.0390569000, 0.0443352000, 0.0608970000, 0.1121397000, 0.2706667000, 0.7600698000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0240577000, 0.0229105000, 0.0191156000, 0.0060420000, -0.042084100, -0.201075800, -0.698017400", \ - "0.0240215000, 0.0228056000, 0.0190584000, 0.0060449000, -0.042119300, -0.201101000, -0.698064000", \ - "0.0239362000, 0.0227790000, 0.0189999000, 0.0059182000, -0.042201700, -0.201172900, -0.698090200", \ - "0.0230278000, 0.0220057000, 0.0181926000, 0.0051739000, -0.042895800, -0.201834600, -0.698756500", \ - "0.0226789000, 0.0214269000, 0.0176791000, 0.0044624000, -0.043538700, -0.202451500, -0.699344700", \ - "0.0296923000, 0.0281452000, 0.0231790000, 0.0074502000, -0.043307800, -0.202815100, -0.699703900", \ - "0.0302350000, 0.0286244000, 0.0236341000, 0.0079068000, -0.042599400, -0.202065000, -0.699225500"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015549260, 0.0048355870, 0.0150379600, 0.0467658100, 0.1454347000, 0.4522804000"); - values("0.0360603000, 0.0379362000, 0.0437132000, 0.0610846000, 0.1132052000, 0.2726159000, 0.7639562000", \ - "0.0360257000, 0.0379058000, 0.0436823000, 0.0610375000, 0.1131614000, 0.2724718000, 0.7639685000", \ - "0.0360615000, 0.0379087000, 0.0436643000, 0.0610950000, 0.1132027000, 0.2726193000, 0.7639775000", \ - "0.0356604000, 0.0375201000, 0.0431747000, 0.0606445000, 0.1127791000, 0.2720601000, 0.7639805000", \ - "0.0348264000, 0.0366827000, 0.0424942000, 0.0599202000, 0.1119781000, 0.2713675000, 0.7627791000", \ - "0.0340653000, 0.0359264000, 0.0417358000, 0.0592288000, 0.1110503000, 0.2703392000, 0.7623387000", \ - "0.0350176000, 0.0366928000, 0.0422445000, 0.0592842000, 0.1104385000, 0.2707522000, 0.7613585000"); - } - } - max_capacitance : 0.4522800000; - max_transition : 1.5066050000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.1825060000, 0.1864565000, 0.1964071000, 0.2180379000, 0.2620164000, 0.3606793000, 0.6305391000", \ - "0.1875134000, 0.1914351000, 0.2013848000, 0.2230114000, 0.2670103000, 0.3659366000, 0.6358301000", \ - "0.2000880000, 0.2040187000, 0.2139495000, 0.2355968000, 0.2796120000, 0.3784507000, 0.6481603000", \ - "0.2271705000, 0.2310844000, 0.2409902000, 0.2625797000, 0.3068449000, 0.4054743000, 0.6753914000", \ - "0.2864826000, 0.2904280000, 0.3002966000, 0.3218436000, 0.3660265000, 0.4648585000, 0.7349262000", \ - "0.4029122000, 0.4073356000, 0.4183055000, 0.4418424000, 0.4888408000, 0.5898219000, 0.8602902000", \ - "0.6004276000, 0.6058419000, 0.6193714000, 0.6474844000, 0.7015437000, 0.8106776000, 1.0849569000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.1078331000, 0.1121078000, 0.1233602000, 0.1517093000, 0.2273670000, 0.4512017000, 1.1431617000", \ - "0.1121398000, 0.1164162000, 0.1276762000, 0.1560204000, 0.2316870000, 0.4555139000, 1.1475372000", \ - "0.1207307000, 0.1249773000, 0.1362374000, 0.1645345000, 0.2402076000, 0.4640344000, 1.1560025000", \ - "0.1386581000, 0.1429196000, 0.1542142000, 0.1825384000, 0.2580884000, 0.4822891000, 1.1721978000", \ - "0.1734917000, 0.1779659000, 0.1897006000, 0.2185681000, 0.2944301000, 0.5194020000, 1.2085636000", \ - "0.2221019000, 0.2272015000, 0.2402189000, 0.2705330000, 0.3472083000, 0.5714442000, 1.2620306000", \ - "0.2638480000, 0.2704300000, 0.2868483000, 0.3220441000, 0.4017832000, 0.6267132000, 1.3163496000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0272578000, 0.0295542000, 0.0354835000, 0.0497083000, 0.0867552000, 0.1926783000, 0.5391630000", \ - "0.0275228000, 0.0296746000, 0.0354035000, 0.0498015000, 0.0864542000, 0.1924187000, 0.5416665000", \ - "0.0275724000, 0.0296037000, 0.0355250000, 0.0496982000, 0.0867479000, 0.1927202000, 0.5390483000", \ - "0.0275409000, 0.0298311000, 0.0356679000, 0.0500682000, 0.0863544000, 0.1925348000, 0.5408916000", \ - "0.0276008000, 0.0295333000, 0.0355076000, 0.0496788000, 0.0868112000, 0.1929686000, 0.5416466000", \ - "0.0328120000, 0.0352786000, 0.0410686000, 0.0561598000, 0.0918960000, 0.1959989000, 0.5406230000", \ - "0.0445261000, 0.0473489000, 0.0552099000, 0.0696399000, 0.1063474000, 0.2081530000, 0.5414214000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0234974000, 0.0272022000, 0.0380380000, 0.0699846000, 0.1711506000, 0.4938556000, 1.4992514000", \ - "0.0234957000, 0.0271963000, 0.0380310000, 0.0699771000, 0.1711550000, 0.4938921000, 1.4989612000", \ - "0.0234776000, 0.0272046000, 0.0380087000, 0.0698225000, 0.1711542000, 0.4939365000, 1.4987286000", \ - "0.0233884000, 0.0272225000, 0.0379325000, 0.0698877000, 0.1708374000, 0.4928348000, 1.5009446000", \ - "0.0253519000, 0.0290731000, 0.0398377000, 0.0714266000, 0.1717632000, 0.4941891000, 1.5010341000", \ - "0.0310203000, 0.0347322000, 0.0448422000, 0.0755738000, 0.1736162000, 0.4925235000, 1.5006734000", \ - "0.0422890000, 0.0464508000, 0.0580411000, 0.0866777000, 0.1780701000, 0.4954238000, 1.4986223000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.1633791000, 0.1673263000, 0.1771172000, 0.1987110000, 0.2428963000, 0.3417815000, 0.6116564000", \ - "0.1665429000, 0.1705033000, 0.1804282000, 0.2021755000, 0.2460674000, 0.3450335000, 0.6144917000", \ - "0.1767918000, 0.1807352000, 0.1906046000, 0.2122278000, 0.2562277000, 0.3550240000, 0.6247974000", \ - "0.2036169000, 0.2075450000, 0.2174850000, 0.2389537000, 0.2828835000, 0.3817726000, 0.6516442000", \ - "0.2702172000, 0.2741088000, 0.2839252000, 0.3052699000, 0.3492529000, 0.4482913000, 0.7182350000", \ - "0.4013320000, 0.4060249000, 0.4176126000, 0.4415985000, 0.4879069000, 0.5891884000, 0.8594512000", \ - "0.6083453000, 0.6141379000, 0.6294371000, 0.6606062000, 0.7162250000, 0.8215038000, 1.0951698000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0932214000, 0.0973650000, 0.1082749000, 0.1361369000, 0.2109114000, 0.4335770000, 1.1251740000", \ - "0.0978004000, 0.1018617000, 0.1128954000, 0.1407033000, 0.2154480000, 0.4390854000, 1.1275958000", \ - "0.1064613000, 0.1105529000, 0.1215407000, 0.1493385000, 0.2242508000, 0.4473746000, 1.1362646000", \ - "0.1237333000, 0.1278446000, 0.1387814000, 0.1664514000, 0.2413235000, 0.4646793000, 1.1552038000", \ - "0.1534860000, 0.1579167000, 0.1694993000, 0.1980850000, 0.2735249000, 0.4979863000, 1.1881383000", \ - "0.1893180000, 0.1945945000, 0.2078043000, 0.2383711000, 0.3149662000, 0.5387825000, 1.2284183000", \ - "0.2071747000, 0.2141852000, 0.2317298000, 0.2684159000, 0.3483906000, 0.5722176000, 1.2621236000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0272532000, 0.0295525000, 0.0355498000, 0.0503093000, 0.0862279000, 0.1927444000, 0.5399846000", \ - "0.0272340000, 0.0294972000, 0.0353707000, 0.0499244000, 0.0867816000, 0.1925460000, 0.5408006000", \ - "0.0272647000, 0.0294890000, 0.0353811000, 0.0499889000, 0.0861994000, 0.1927876000, 0.5404973000", \ - "0.0276196000, 0.0297679000, 0.0356875000, 0.0499472000, 0.0868114000, 0.1927187000, 0.5393251000", \ - "0.0273745000, 0.0297079000, 0.0356848000, 0.0498412000, 0.0870453000, 0.1928632000, 0.5394474000", \ - "0.0369197000, 0.0396248000, 0.0449301000, 0.0582393000, 0.0934131000, 0.1964222000, 0.5400991000", \ - "0.0539571000, 0.0569963000, 0.0652728000, 0.0791567000, 0.1103625000, 0.2085548000, 0.5427903000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0222978000, 0.0259182000, 0.0367065000, 0.0685645000, 0.1699973000, 0.4933755000, 1.5018146000", \ - "0.0223745000, 0.0260177000, 0.0366941000, 0.0686010000, 0.1696847000, 0.4932376000, 1.4983428000", \ - "0.0224103000, 0.0260440000, 0.0366885000, 0.0686040000, 0.1699423000, 0.4919569000, 1.4989849000", \ - "0.0225460000, 0.0262020000, 0.0369118000, 0.0687082000, 0.1699225000, 0.4918599000, 1.5011926000", \ - "0.0252597000, 0.0288650000, 0.0395679000, 0.0707435000, 0.1708457000, 0.4932088000, 1.5066048000", \ - "0.0322583000, 0.0362672000, 0.0461494000, 0.0759141000, 0.1729943000, 0.4923271000, 1.4993091000", \ - "0.0454980000, 0.0499646000, 0.0614931000, 0.0894144000, 0.1794405000, 0.4941487000, 1.4976770000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.1211804000, 0.1241406000, 0.1318119000, 0.1498836000, 0.1908361000, 0.2860273000, 0.5538576000", \ - "0.1258700000, 0.1288022000, 0.1365168000, 0.1545652000, 0.1955345000, 0.2906927000, 0.5582170000", \ - "0.1366268000, 0.1395701000, 0.1472236000, 0.1652932000, 0.2062567000, 0.3014878000, 0.5692276000", \ - "0.1586710000, 0.1616329000, 0.1691699000, 0.1872196000, 0.2282524000, 0.3234535000, 0.5909785000", \ - "0.1899811000, 0.1929275000, 0.2005529000, 0.2186144000, 0.2596745000, 0.3549363000, 0.6224405000", \ - "0.2272564000, 0.2301796000, 0.2380116000, 0.2561291000, 0.2973823000, 0.3927987000, 0.6602793000", \ - "0.2548737000, 0.2579494000, 0.2658951000, 0.2844077000, 0.3264480000, 0.4223402000, 0.6902935000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.1812617000, 0.1855389000, 0.1968204000, 0.2251625000, 0.3007465000, 0.5245713000, 1.2160148000", \ - "0.1865314000, 0.1908509000, 0.2021473000, 0.2304771000, 0.3060820000, 0.5309963000, 1.2214677000", \ - "0.1992128000, 0.2034816000, 0.2147446000, 0.2430970000, 0.3186948000, 0.5425317000, 1.2338035000", \ - "0.2310428000, 0.2353215000, 0.2465790000, 0.2749305000, 0.3505095000, 0.5748245000, 1.2653706000", \ - "0.3002142000, 0.3044681000, 0.3157774000, 0.3441099000, 0.4196720000, 0.6435498000, 1.3357125000", \ - "0.4189224000, 0.4231424000, 0.4346624000, 0.4631361000, 0.5384745000, 0.7628613000, 1.4531502000", \ - "0.6117125000, 0.6158873000, 0.6274462000, 0.6561861000, 0.7325521000, 0.9559482000, 1.6477811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0169540000, 0.0189804000, 0.0246698000, 0.0404655000, 0.0797621000, 0.1863435000, 0.5371899000", \ - "0.0169532000, 0.0190066000, 0.0245963000, 0.0405032000, 0.0797519000, 0.1862426000, 0.5379889000", \ - "0.0169458000, 0.0190111000, 0.0246881000, 0.0404892000, 0.0797855000, 0.1857882000, 0.5377186000", \ - "0.0170190000, 0.0190861000, 0.0246101000, 0.0405309000, 0.0797755000, 0.1861810000, 0.5379899000", \ - "0.0171276000, 0.0191261000, 0.0248417000, 0.0405256000, 0.0799613000, 0.1861864000, 0.5379849000", \ - "0.0175370000, 0.0195751000, 0.0252189000, 0.0410375000, 0.0802941000, 0.1863184000, 0.5357855000", \ - "0.0191551000, 0.0212277000, 0.0269485000, 0.0423921000, 0.0815068000, 0.1870537000, 0.5369731000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015549300, 0.0048355900, 0.0150380000, 0.0467658000, 0.1454350000, 0.4522800000"); - values("0.0235974000, 0.0273164000, 0.0380878000, 0.0701265000, 0.1711905000, 0.4940415000, 1.4982608000", \ - "0.0236076000, 0.0273510000, 0.0380935000, 0.0700862000, 0.1711912000, 0.4940024000, 1.4982715000", \ - "0.0235342000, 0.0272351000, 0.0381511000, 0.0701313000, 0.1711920000, 0.4940491000, 1.4989452000", \ - "0.0235604000, 0.0272688000, 0.0381904000, 0.0700979000, 0.1708279000, 0.4929616000, 1.5000431000", \ - "0.0236423000, 0.0274384000, 0.0381884000, 0.0701187000, 0.1712062000, 0.4939859000, 1.4983196000", \ - "0.0241943000, 0.0280159000, 0.0388190000, 0.0706788000, 0.1713403000, 0.4935843000, 1.5014573000", \ - "0.0255456000, 0.0296320000, 0.0401803000, 0.0717787000, 0.1724142000, 0.4931965000, 1.4997841000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21bai_1") { - leakage_power () { - value : 0.0011052000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0019309000; - when : "A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0106602000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0007643000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0011065000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0029540000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0011042000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0033211000; - when : "A1&!A2&!B1_N"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__o21bai"; - cell_leakage_power : 0.0028682940; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039993000, 0.0040000000, 0.0040016000, 0.0040034000, 0.0040073000, 0.0040165000, 0.0040376000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003998100, -0.003997200, -0.003995300, -0.003994700, -0.003993400, -0.003990400, -0.003983400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024550000; - } - pin ("A2") { - capacitance : 0.0023380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039948000, 0.0039927000, 0.0039881000, 0.0039865000, 0.0039829000, 0.0039747000, 0.0039556000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003992000, -0.003989100, -0.003982400, -0.003980300, -0.003975600, -0.003964700, -0.003939500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024950000; - } - pin ("B1_N") { - capacitance : 0.0016960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088038000, 0.0086857000, 0.0084134000, 0.0084580000, 0.0085609000, 0.0087981000, 0.0093450000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039210000, 0.0038566000, 0.0037080000, 0.0037447000, 0.0038293000, 0.0040242000, 0.0044736000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017610000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0068158000, 0.0057642000, 0.0033343000, -0.002340000, -0.015596200, -0.046465400, -0.118149500", \ - "0.0066907000, 0.0056477000, 0.0032262000, -0.002444000, -0.015685400, -0.046544500, -0.118228800", \ - "0.0065241000, 0.0054904000, 0.0030967000, -0.002541600, -0.015774200, -0.046606200, -0.118308300", \ - "0.0063252000, 0.0052908000, 0.0029112000, -0.002676200, -0.015861200, -0.046677800, -0.118311600", \ - "0.0064255000, 0.0053443000, 0.0028406000, -0.002789800, -0.015929300, -0.046707500, -0.118330800", \ - "0.0065448000, 0.0054619000, 0.0029994000, -0.002712600, -0.016117200, -0.046853800, -0.118407600", \ - "0.0073650000, 0.0062489000, 0.0036957000, -0.002160900, -0.015586800, -0.046682500, -0.118384900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0084342000, 0.0094995000, 0.0119699000, 0.0176818000, 0.0308885000, 0.0614217000, 0.1322255000", \ - "0.0082690000, 0.0093486000, 0.0118549000, 0.0175846000, 0.0308077000, 0.0613128000, 0.1321469000", \ - "0.0080960000, 0.0091670000, 0.0116736000, 0.0174510000, 0.0307089000, 0.0612994000, 0.1320453000", \ - "0.0079559000, 0.0090341000, 0.0115271000, 0.0172952000, 0.0305971000, 0.0612065000, 0.1321187000", \ - "0.0078507000, 0.0089420000, 0.0114264000, 0.0171980000, 0.0304526000, 0.0610575000, 0.1320107000", \ - "0.0076809000, 0.0088582000, 0.0113342000, 0.0171673000, 0.0304915000, 0.0611653000, 0.1318819000", \ - "0.0083099000, 0.0093036000, 0.0116965000, 0.0172230000, 0.0306963000, 0.0612515000, 0.1320653000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0051591000, 0.0042136000, 0.0018958000, -0.003694300, -0.016944200, -0.047838400, -0.119548300", \ - "0.0050013000, 0.0040745000, 0.0018195000, -0.003711200, -0.016918900, -0.047790200, -0.119482900", \ - "0.0047104000, 0.0038229000, 0.0016140000, -0.003841100, -0.016975400, -0.047794200, -0.119463600", \ - "0.0044685000, 0.0035263000, 0.0012918000, -0.004098800, -0.017130900, -0.047870700, -0.119498500", \ - "0.0047137000, 0.0036914000, 0.0012919000, -0.004381200, -0.017382100, -0.048014300, -0.119558100", \ - "0.0047931000, 0.0037231000, 0.0012600000, -0.004415600, -0.017671000, -0.048292600, -0.119734800", \ - "0.0057251000, 0.0045620000, 0.0019487000, -0.003960900, -0.017389900, -0.048274100, -0.119893900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0063254000, 0.0074068000, 0.0099037000, 0.0156386000, 0.0288542000, 0.0593606000, 0.1301262000", \ - "0.0060284000, 0.0071396000, 0.0096751000, 0.0154591000, 0.0287264000, 0.0592971000, 0.1301465000", \ - "0.0058471000, 0.0069322000, 0.0094357000, 0.0152522000, 0.0285844000, 0.0592586000, 0.1300932000", \ - "0.0057357000, 0.0068136000, 0.0093268000, 0.0149721000, 0.0283590000, 0.0590849000, 0.1299530000", \ - "0.0059283000, 0.0069088000, 0.0093310000, 0.0151580000, 0.0282194000, 0.0588433000, 0.1298167000", \ - "0.0067074000, 0.0076970000, 0.0101266000, 0.0156485000, 0.0283218000, 0.0586232000, 0.1296007000", \ - "0.0075533000, 0.0085484000, 0.0109536000, 0.0164621000, 0.0294792000, 0.0597373000, 0.1300604000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0047632000, 0.0037555000, 0.0014201000, -0.004141800, -0.017348300, -0.048197400, -0.119857500", \ - "0.0047363000, 0.0037001000, 0.0013501000, -0.004202400, -0.017383600, -0.048225200, -0.119907800", \ - "0.0048015000, 0.0037971000, 0.0014331000, -0.004151300, -0.017313800, -0.048143500, -0.119783600", \ - "0.0045783000, 0.0035702000, 0.0012085000, -0.004353200, -0.017498300, -0.048295700, -0.119942600", \ - "0.0042900000, 0.0032760000, 0.0009158000, -0.004635400, -0.017723000, -0.048511100, -0.120084600", \ - "0.0039812000, 0.0029438000, 0.0004651000, -0.004855700, -0.017950600, -0.048647900, -0.120227200", \ - "0.0043548000, 0.0032985000, 0.0008071000, -0.004875200, -0.017976900, -0.048615700, -0.120164700"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011596650, 0.0026896470, 0.0062381810, 0.0144684000, 0.0335570100, 0.0778298000"); - values("0.0056282000, 0.0068747000, 0.0095490000, 0.0155485000, 0.0288930000, 0.0594728000, 0.1301419000", \ - "0.0056221000, 0.0068432000, 0.0095595000, 0.0155370000, 0.0288757000, 0.0594883000, 0.1303090000", \ - "0.0055978000, 0.0067830000, 0.0094592000, 0.0154334000, 0.0288256000, 0.0594278000, 0.1302588000", \ - "0.0052845000, 0.0064461000, 0.0090416000, 0.0150139000, 0.0284926000, 0.0592170000, 0.1299120000", \ - "0.0050201000, 0.0061446000, 0.0087361000, 0.0146424000, 0.0279899000, 0.0587080000, 0.1296935000", \ - "0.0051204000, 0.0062182000, 0.0087826000, 0.0146571000, 0.0278278000, 0.0586632000, 0.1294875000", \ - "0.0052914000, 0.0063487000, 0.0088302000, 0.0145623000, 0.0279728000, 0.0582303000, 0.1291978000"); - } - } - max_capacitance : 0.0778300000; - max_transition : 1.4969080000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0407904000, 0.0451637000, 0.0546892000, 0.0755073000, 0.1214207000, 0.2254883000, 0.4651585000", \ - "0.0451528000, 0.0495572000, 0.0590971000, 0.0799181000, 0.1258515000, 0.2299301000, 0.4694367000", \ - "0.0540490000, 0.0584159000, 0.0680751000, 0.0889543000, 0.1350671000, 0.2391330000, 0.4787400000", \ - "0.0700725000, 0.0749994000, 0.0858359000, 0.1081894000, 0.1547475000, 0.2591836000, 0.4992542000", \ - "0.0930679000, 0.1003288000, 0.1154814000, 0.1445671000, 0.1993608000, 0.3068870000, 0.5473758000", \ - "0.1158119000, 0.1268006000, 0.1502916000, 0.1951840000, 0.2731410000, 0.4075935000, 0.6603546000", \ - "0.1156381000, 0.1336606000, 0.1716436000, 0.2428706000, 0.3657184000, 0.5654717000, 0.8887619000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0834352000, 0.0931317000, 0.1144246000, 0.1631072000, 0.2740322000, 0.5295727000, 1.1207761000", \ - "0.0887228000, 0.0979409000, 0.1198235000, 0.1685654000, 0.2796801000, 0.5355342000, 1.1266603000", \ - "0.1007319000, 0.1099932000, 0.1316453000, 0.1807935000, 0.2923297000, 0.5482895000, 1.1398538000", \ - "0.1269771000, 0.1364028000, 0.1577688000, 0.2067211000, 0.3184329000, 0.5748870000, 1.1664504000", \ - "0.1779644000, 0.1900061000, 0.2145663000, 0.2655778000, 0.3771140000, 0.6336804000, 1.2258117000", \ - "0.2633760000, 0.2804655000, 0.3143379000, 0.3813833000, 0.5116859000, 0.7701583000, 1.3630018000", \ - "0.4040743000, 0.4287229000, 0.4799592000, 0.5778182000, 0.7551783000, 1.0735816000, 1.6772468000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0264788000, 0.0316238000, 0.0433665000, 0.0699915000, 0.1299318000, 0.2688480000, 0.5916304000", \ - "0.0264187000, 0.0315250000, 0.0433921000, 0.0700085000, 0.1301416000, 0.2688197000, 0.5916272000", \ - "0.0265799000, 0.0317497000, 0.0433693000, 0.0697072000, 0.1301583000, 0.2688670000, 0.5924196000", \ - "0.0320247000, 0.0370510000, 0.0478398000, 0.0723618000, 0.1304151000, 0.2686295000, 0.5908202000", \ - "0.0480550000, 0.0538217000, 0.0666708000, 0.0911342000, 0.1443507000, 0.2722915000, 0.5912989000", \ - "0.0821217000, 0.0898380000, 0.1062736000, 0.1377698000, 0.1965364000, 0.3139516000, 0.6045323000", \ - "0.1455809000, 0.1579125000, 0.1818811000, 0.2261597000, 0.3048155000, 0.4416315000, 0.7118055000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0666627000, 0.0784825000, 0.1060906000, 0.1706785000, 0.3201544000, 0.6677597000, 1.4750554000", \ - "0.0666022000, 0.0786059000, 0.1058503000, 0.1701171000, 0.3211423000, 0.6705547000, 1.4745821000", \ - "0.0664915000, 0.0785014000, 0.1061253000, 0.1705240000, 0.3211494000, 0.6690876000, 1.4740158000", \ - "0.0680601000, 0.0792407000, 0.1060764000, 0.1703552000, 0.3204753000, 0.6678650000, 1.4742991000", \ - "0.0854241000, 0.0965739000, 0.1198613000, 0.1776314000, 0.3217065000, 0.6699684000, 1.4754147000", \ - "0.1259157000, 0.1385096000, 0.1657986000, 0.2234124000, 0.3517653000, 0.6733398000, 1.4759737000", \ - "0.2053023000, 0.2223520000, 0.2580629000, 0.3282038000, 0.4679925000, 0.7602667000, 1.4934336000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0311564000, 0.0352091000, 0.0440007000, 0.0633288000, 0.1059085000, 0.2025941000, 0.4254845000", \ - "0.0355036000, 0.0396424000, 0.0486730000, 0.0682305000, 0.1107678000, 0.2074380000, 0.4320833000", \ - "0.0438822000, 0.0482547000, 0.0574754000, 0.0770867000, 0.1201902000, 0.2171509000, 0.4413158000", \ - "0.0559253000, 0.0616712000, 0.0733275000, 0.0957965000, 0.1399176000, 0.2374065000, 0.4605494000", \ - "0.0687265000, 0.0778211000, 0.0957411000, 0.1271633000, 0.1831647000, 0.2851382000, 0.5107136000", \ - "0.0719877000, 0.0863277000, 0.1145388000, 0.1653815000, 0.2481166000, 0.3843146000, 0.6233364000", \ - "0.0352610000, 0.0593391000, 0.1056235000, 0.1872144000, 0.3195909000, 0.5254862000, 0.8455984000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0714919000, 0.0807611000, 0.1026329000, 0.1513689000, 0.2624476000, 0.5182055000, 1.1097393000", \ - "0.0740869000, 0.0838296000, 0.1059690000, 0.1550736000, 0.2665392000, 0.5225246000, 1.1138416000", \ - "0.0852715000, 0.0947953000, 0.1163915000, 0.1656651000, 0.2776114000, 0.5339084000, 1.1256760000", \ - "0.1141102000, 0.1233873000, 0.1446253000, 0.1925092000, 0.3056264000, 0.5623700000, 1.1549267000", \ - "0.1740120000, 0.1863204000, 0.2114169000, 0.2611620000, 0.3707447000, 0.6267165000, 1.2190771000", \ - "0.2704183000, 0.2891652000, 0.3278923000, 0.4000698000, 0.5305475000, 0.7794164000, 1.3695897000", \ - "0.4291740000, 0.4568909000, 0.5135831000, 0.6255043000, 0.8246293000, 1.1508470000, 1.7388556000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0173244000, 0.0223844000, 0.0335605000, 0.0584037000, 0.1148009000, 0.2448760000, 0.5448860000", \ - "0.0175059000, 0.0225554000, 0.0336002000, 0.0591084000, 0.1147009000, 0.2444508000, 0.5436501000", \ - "0.0186528000, 0.0232424000, 0.0339670000, 0.0587735000, 0.1144099000, 0.2432027000, 0.5441639000", \ - "0.0254375000, 0.0302299000, 0.0408471000, 0.0623629000, 0.1152436000, 0.2428598000, 0.5431557000", \ - "0.0423352000, 0.0481427000, 0.0605661000, 0.0839342000, 0.1325691000, 0.2487285000, 0.5435704000", \ - "0.0761935000, 0.0844216000, 0.1016261000, 0.1333186000, 0.1875910000, 0.2981268000, 0.5605271000", \ - "0.1441463000, 0.1558099000, 0.1792270000, 0.2228671000, 0.2983130000, 0.4293438000, 0.6794257000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0662955000, 0.0784912000, 0.1058898000, 0.1701029000, 0.3208944000, 0.6704107000, 1.4737083000", \ - "0.0665206000, 0.0784275000, 0.1058204000, 0.1700591000, 0.3207564000, 0.6702555000, 1.4747845000", \ - "0.0662561000, 0.0781939000, 0.1060041000, 0.1706008000, 0.3203798000, 0.6682229000, 1.4753457000", \ - "0.0698110000, 0.0805088000, 0.1064984000, 0.1701628000, 0.3208334000, 0.6676395000, 1.4765976000", \ - "0.0975107000, 0.1083642000, 0.1294298000, 0.1823653000, 0.3213717000, 0.6683901000, 1.4779885000", \ - "0.1469461000, 0.1623152000, 0.1926271000, 0.2516269000, 0.3629775000, 0.6750577000, 1.4759738000", \ - "0.2256110000, 0.2506504000, 0.2986362000, 0.3854088000, 0.5305941000, 0.7893198000, 1.4969080000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.1163371000, 0.1214248000, 0.1322860000, 0.1543616000, 0.2011417000, 0.3053047000, 0.5449231000", \ - "0.1211567000, 0.1261338000, 0.1368526000, 0.1590944000, 0.2058622000, 0.3100466000, 0.5496684000", \ - "0.1336810000, 0.1387793000, 0.1494567000, 0.1715319000, 0.2182618000, 0.3224634000, 0.5621387000", \ - "0.1655771000, 0.1707290000, 0.1814532000, 0.2036503000, 0.2505218000, 0.3548375000, 0.5944741000", \ - "0.2354236000, 0.2406332000, 0.2515849000, 0.2741031000, 0.3206350000, 0.4256000000, 0.6652821000", \ - "0.3514207000, 0.3571198000, 0.3697025000, 0.3941739000, 0.4430273000, 0.5485083000, 0.7881049000", \ - "0.5319976000, 0.5394777000, 0.5547773000, 0.5836224000, 0.6369685000, 0.7432832000, 0.9829808000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0633780000, 0.0690351000, 0.0811013000, 0.1070700000, 0.1653622000, 0.2978276000, 0.6049617000", \ - "0.0682542000, 0.0738664000, 0.0859472000, 0.1120527000, 0.1698261000, 0.3026957000, 0.6095148000", \ - "0.0796257000, 0.0850971000, 0.0973276000, 0.1233089000, 0.1817221000, 0.3147832000, 0.6209078000", \ - "0.1028886000, 0.1084965000, 0.1204073000, 0.1463796000, 0.2048957000, 0.3374304000, 0.6442330000", \ - "0.1370417000, 0.1428030000, 0.1550837000, 0.1812942000, 0.2396897000, 0.3735725000, 0.6803600000", \ - "0.1789139000, 0.1857793000, 0.1993314000, 0.2262353000, 0.2843621000, 0.4172134000, 0.7243887000", \ - "0.2152307000, 0.2244954000, 0.2422381000, 0.2728003000, 0.3317004000, 0.4629472000, 0.7702117000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0323816000, 0.0374456000, 0.0483857000, 0.0734778000, 0.1317530000, 0.2694597000, 0.5916805000", \ - "0.0320768000, 0.0373244000, 0.0485357000, 0.0737283000, 0.1316002000, 0.2687926000, 0.5921533000", \ - "0.0319745000, 0.0373091000, 0.0485211000, 0.0737506000, 0.1316898000, 0.2694562000, 0.5909774000", \ - "0.0321597000, 0.0370816000, 0.0485315000, 0.0737427000, 0.1315033000, 0.2691725000, 0.5913052000", \ - "0.0344291000, 0.0395140000, 0.0505596000, 0.0749209000, 0.1324218000, 0.2694834000, 0.5914825000", \ - "0.0437124000, 0.0491693000, 0.0600546000, 0.0832356000, 0.1382151000, 0.2715774000, 0.5914098000", \ - "0.0608938000, 0.0669315000, 0.0786208000, 0.1011412000, 0.1516117000, 0.2784833000, 0.5947425000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011596700, 0.0026896500, 0.0062381800, 0.0144684000, 0.0335570000, 0.0778298000"); - values("0.0339975000, 0.0406246000, 0.0564080000, 0.0926153000, 0.1740445000, 0.3603135000, 0.7936177000", \ - "0.0340401000, 0.0406432000, 0.0564282000, 0.0926254000, 0.1740247000, 0.3603058000, 0.7933005000", \ - "0.0340090000, 0.0406783000, 0.0564165000, 0.0926522000, 0.1740297000, 0.3606820000, 0.7930660000", \ - "0.0354222000, 0.0418321000, 0.0571391000, 0.0928279000, 0.1740529000, 0.3604691000, 0.7935042000", \ - "0.0401062000, 0.0457063000, 0.0599469000, 0.0946494000, 0.1749199000, 0.3608802000, 0.7929758000", \ - "0.0516501000, 0.0558272000, 0.0675462000, 0.0984045000, 0.1762614000, 0.3621065000, 0.7952639000", \ - "0.0747160000, 0.0778026000, 0.0863160000, 0.1120826000, 0.1813360000, 0.3629797000, 0.7958475000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21bai_2") { - leakage_power () { - value : 0.0010301000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0016159000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0016964000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0099398000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0016965000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0084818000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0016950000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0064994000; - when : "A1&A2&!B1_N"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o21bai"; - cell_leakage_power : 0.0040818700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079290000, 0.0079306000, 0.0079345000, 0.0079364000, 0.0079407000, 0.0079508000, 0.0079741000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007921800, -0.007917100, -0.007906200, -0.007902900, -0.007895500, -0.007878300, -0.007838700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045950000; - } - pin ("A2") { - capacitance : 0.0044110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079950000, 0.0079944000, 0.0079928000, 0.0079932000, 0.0079943000, 0.0079969000, 0.0080027000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007991700, -0.007987000, -0.007976200, -0.007974700, -0.007971200, -0.007963000, -0.007944300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047150000; - } - pin ("B1_N") { - capacitance : 0.0013440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0110784000, 0.0109838000, 0.0107657000, 0.0108374000, 0.0110027000, 0.0113835000, 0.0122614000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088634000, 0.0088153000, 0.0087044000, 0.0087301000, 0.0087895000, 0.0089263000, 0.0092417000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0013940000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0150044000, 0.0137433000, 0.0105851000, 0.0024785000, -0.018409800, -0.072263900, -0.210311600", \ - "0.0147256000, 0.0135006000, 0.0103408000, 0.0022540000, -0.018620100, -0.072457100, -0.210487600", \ - "0.0143430000, 0.0131248000, 0.0099845000, 0.0019528000, -0.018840500, -0.072630000, -0.210668900", \ - "0.0138806000, 0.0126958000, 0.0095800000, 0.0016219000, -0.019093200, -0.072808200, -0.210782000", \ - "0.0137898000, 0.0125444000, 0.0093817000, 0.0012973000, -0.019264100, -0.072897300, -0.210831400", \ - "0.0142713000, 0.0130232000, 0.0098190000, 0.0015858000, -0.019599000, -0.073252700, -0.211051200", \ - "0.0158539000, 0.0145520000, 0.0112906000, 0.0028589000, -0.018529800, -0.072782900, -0.211009100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0155917000, 0.0168233000, 0.0200102000, 0.0281890000, 0.0490994000, 0.1025124000, 0.2388535000", \ - "0.0151801000, 0.0164489000, 0.0196803000, 0.0279247000, 0.0489532000, 0.1023663000, 0.2384348000", \ - "0.0148100000, 0.0160652000, 0.0193039000, 0.0275967000, 0.0486839000, 0.1022575000, 0.2388631000", \ - "0.0145321000, 0.0157970000, 0.0190047000, 0.0272585000, 0.0483619000, 0.1019966000, 0.2385253000", \ - "0.0142609000, 0.0155224000, 0.0187399000, 0.0269719000, 0.0479828000, 0.1017039000, 0.2381164000", \ - "0.0140872000, 0.0153501000, 0.0185667000, 0.0269034000, 0.0481565000, 0.1017454000, 0.2381371000", \ - "0.0146536000, 0.0158503000, 0.0189384000, 0.0269293000, 0.0482339000, 0.1021319000, 0.2388908000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0102257000, 0.0091171000, 0.0061707000, -0.001641400, -0.022433400, -0.076345900, -0.214550000", \ - "0.0098316000, 0.0088024000, 0.0059814000, -0.001682800, -0.022370600, -0.076205100, -0.214374100", \ - "0.0093198000, 0.0083004000, 0.0055506000, -0.001974100, -0.022463600, -0.076176900, -0.214288300", \ - "0.0088829000, 0.0077630000, 0.0049431000, -0.002541000, -0.022794100, -0.076314400, -0.214307000", \ - "0.0095474000, 0.0083253000, 0.0051222000, -0.002968800, -0.023321700, -0.076624000, -0.214400100", \ - "0.0099958000, 0.0087248000, 0.0055014000, -0.002675200, -0.023551500, -0.077142700, -0.214723300", \ - "0.0125345000, 0.0111136000, 0.0075852000, -0.001140000, -0.022684900, -0.076799000, -0.214908000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0109234000, 0.0122321000, 0.0154555000, 0.0236906000, 0.0446451000, 0.0980926000, 0.2344112000", \ - "0.0103093000, 0.0116709000, 0.0149356000, 0.0232790000, 0.0443833000, 0.0978660000, 0.2342494000", \ - "0.0098445000, 0.0111568000, 0.0144076000, 0.0228315000, 0.0440789000, 0.0977054000, 0.2342145000", \ - "0.0096775000, 0.0109234000, 0.0141795000, 0.0223548000, 0.0433916000, 0.0973867000, 0.2342088000", \ - "0.0096869000, 0.0110820000, 0.0142726000, 0.0222775000, 0.0432556000, 0.0969756000, 0.2336839000", \ - "0.0112417000, 0.0121661000, 0.0152282000, 0.0237404000, 0.0443795000, 0.0974520000, 0.2329288000", \ - "0.0137748000, 0.0148948000, 0.0177726000, 0.0262897000, 0.0463573000, 0.0992152000, 0.2344184000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0099353000, 0.0087505000, 0.0057089000, -0.002278800, -0.022799900, -0.076419500, -0.214393600", \ - "0.0099446000, 0.0087525000, 0.0056721000, -0.002243000, -0.022831900, -0.076440800, -0.214415400", \ - "0.0100645000, 0.0088468000, 0.0057623000, -0.002168400, -0.022759700, -0.076355800, -0.214414100", \ - "0.0097494000, 0.0085403000, 0.0054733000, -0.002430500, -0.023024400, -0.076642400, -0.214582500", \ - "0.0095435000, 0.0083335000, 0.0052262000, -0.002709800, -0.023428300, -0.076932600, -0.214743000", \ - "0.0091303000, 0.0078577000, 0.0047485000, -0.003252300, -0.023875200, -0.077389400, -0.215176600", \ - "0.0101631000, 0.0088338000, 0.0055917000, -0.001900000, -0.023208900, -0.077092100, -0.214975300"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717330, 0.0083691590, 0.0214084800, 0.0547633100, 0.1400856000"); - values("0.0089271000, 0.0103532000, 0.0139058000, 0.0226562000, 0.0441639000, 0.0979198000, 0.2341842000", \ - "0.0089343000, 0.0103468000, 0.0138983000, 0.0226492000, 0.0442577000, 0.0979276000, 0.2344864000", \ - "0.0089220000, 0.0103174000, 0.0138568000, 0.0226197000, 0.0441787000, 0.0978980000, 0.2342433000", \ - "0.0087705000, 0.0101051000, 0.0135461000, 0.0221607000, 0.0436831000, 0.0976142000, 0.2343354000", \ - "0.0086782000, 0.0100032000, 0.0133402000, 0.0216772000, 0.0431246000, 0.0971863000, 0.2339287000", \ - "0.0088905000, 0.0101299000, 0.0133705000, 0.0217333000, 0.0426203000, 0.0965082000, 0.2335775000", \ - "0.0094330000, 0.0109043000, 0.0140650000, 0.0222439000, 0.0433413000, 0.0962759000, 0.2334868000"); - } - } - max_capacitance : 0.1400860000; - max_transition : 1.4989860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0427542000, 0.0457160000, 0.0531164000, 0.0703058000, 0.1102919000, 0.2069311000, 0.4488194000", \ - "0.0469133000, 0.0499616000, 0.0573248000, 0.0745464000, 0.1145533000, 0.2111724000, 0.4531043000", \ - "0.0551544000, 0.0581980000, 0.0655622000, 0.0827545000, 0.1229378000, 0.2196278000, 0.4614056000", \ - "0.0691054000, 0.0726231000, 0.0809708000, 0.0995848000, 0.1403912000, 0.2374188000, 0.4797071000", \ - "0.0895918000, 0.0942524000, 0.1057659000, 0.1297034000, 0.1798004000, 0.2816417000, 0.5251122000", \ - "0.1062803000, 0.1141126000, 0.1317388000, 0.1684324000, 0.2408675000, 0.3727992000, 0.6324947000", \ - "0.0938283000, 0.1064001000, 0.1342604000, 0.1934441000, 0.3076052000, 0.5068038000, 0.8468071000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0877682000, 0.0940721000, 0.1097820000, 0.1488479000, 0.2463361000, 0.4926420000, 1.1197266000", \ - "0.0922745000, 0.0986133000, 0.1145170000, 0.1538776000, 0.2517238000, 0.4980044000, 1.1269062000", \ - "0.1046437000, 0.1109922000, 0.1268977000, 0.1664213000, 0.2645812000, 0.5112835000, 1.1388213000", \ - "0.1322963000, 0.1385628000, 0.1542506000, 0.1936249000, 0.2918922000, 0.5391299000, 1.1669591000", \ - "0.1859249000, 0.1934630000, 0.2117668000, 0.2538018000, 0.3517890000, 0.5990204000, 1.2281922000", \ - "0.2763974000, 0.2869755000, 0.3121901000, 0.3683407000, 0.4869481000, 0.7377615000, 1.3670531000", \ - "0.4217268000, 0.4382407000, 0.4763246000, 0.5608180000, 0.7256439000, 1.0437403000, 1.6890913000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0271057000, 0.0305236000, 0.0391569000, 0.0601965000, 0.1110693000, 0.2389119000, 0.5667182000", \ - "0.0269210000, 0.0305725000, 0.0391077000, 0.0601781000, 0.1110590000, 0.2389073000, 0.5668931000", \ - "0.0270386000, 0.0305000000, 0.0390025000, 0.0599771000, 0.1108880000, 0.2387342000, 0.5666516000", \ - "0.0316936000, 0.0350555000, 0.0434176000, 0.0626259000, 0.1116324000, 0.2391791000, 0.5667022000", \ - "0.0458661000, 0.0497475000, 0.0591373000, 0.0797857000, 0.1264064000, 0.2441317000, 0.5677115000", \ - "0.0783460000, 0.0838415000, 0.0961581000, 0.1227801000, 0.1763178000, 0.2892712000, 0.5820944000", \ - "0.1404451000, 0.1482554000, 0.1666210000, 0.2049834000, 0.2783630000, 0.4132381000, 0.6937765000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0673229000, 0.0751358000, 0.0944318000, 0.1453378000, 0.2773431000, 0.6138902000, 1.4768364000", \ - "0.0670781000, 0.0745803000, 0.0946321000, 0.1454329000, 0.2766218000, 0.6141539000, 1.4816773000", \ - "0.0671264000, 0.0748424000, 0.0946032000, 0.1453247000, 0.2773507000, 0.6136278000, 1.4755807000", \ - "0.0678724000, 0.0751526000, 0.0945624000, 0.1452553000, 0.2771984000, 0.6149301000, 1.4767177000", \ - "0.0842167000, 0.0912487000, 0.1080961000, 0.1534764000, 0.2785462000, 0.6136068000, 1.4819406000", \ - "0.1225360000, 0.1306274000, 0.1504761000, 0.1982641000, 0.3108815000, 0.6199849000, 1.4756683000", \ - "0.2022136000, 0.2133071000, 0.2399069000, 0.2974848000, 0.4253886000, 0.7107367000, 1.4924491000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0309811000, 0.0338998000, 0.0409053000, 0.0573788000, 0.0959043000, 0.1881715000, 0.4205632000", \ - "0.0351556000, 0.0381849000, 0.0453720000, 0.0620267000, 0.1006006000, 0.1929744000, 0.4258401000", \ - "0.0429138000, 0.0461208000, 0.0535493000, 0.0704030000, 0.1091862000, 0.2018680000, 0.4344433000", \ - "0.0530024000, 0.0570373000, 0.0664563000, 0.0861488000, 0.1265556000, 0.2198719000, 0.4523294000", \ - "0.0623778000, 0.0684681000, 0.0825278000, 0.1103847000, 0.1633726000, 0.2641551000, 0.4987679000", \ - "0.0581121000, 0.0681959000, 0.0904010000, 0.1346381000, 0.2144612000, 0.3516568000, 0.6061425000", \ - "0.0079024000, 0.0256897000, 0.0615128000, 0.1333240000, 0.2604810000, 0.4714510000, 0.8151968000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0682733000, 0.0747087000, 0.0906609000, 0.1299778000, 0.2277155000, 0.4739948000, 1.1011185000", \ - "0.0706212000, 0.0774232000, 0.0933369000, 0.1331327000, 0.2313340000, 0.4782490000, 1.1081628000", \ - "0.0808509000, 0.0872942000, 0.1031207000, 0.1430635000, 0.2418767000, 0.4889802000, 1.1167718000", \ - "0.1091455000, 0.1152596000, 0.1307847000, 0.1700068000, 0.2674840000, 0.5152121000, 1.1435277000", \ - "0.1661144000, 0.1748219000, 0.1944661000, 0.2366258000, 0.3334589000, 0.5804523000, 1.2098605000", \ - "0.2575548000, 0.2694271000, 0.2991232000, 0.3628308000, 0.4863006000, 0.7326268000, 1.3559852000", \ - "0.4102984000, 0.4281259000, 0.4701786000, 0.5644165000, 0.7473206000, 1.0836634000, 1.7119144000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0156134000, 0.0191914000, 0.0279295000, 0.0484945000, 0.0984265000, 0.2213188000, 0.5353480000", \ - "0.0156436000, 0.0192121000, 0.0279607000, 0.0485521000, 0.0982527000, 0.2211853000, 0.5344725000", \ - "0.0169047000, 0.0201098000, 0.0282698000, 0.0484282000, 0.0983835000, 0.2211309000, 0.5350961000", \ - "0.0225143000, 0.0261610000, 0.0344076000, 0.0530619000, 0.0992741000, 0.2208096000, 0.5379420000", \ - "0.0374502000, 0.0418869000, 0.0515880000, 0.0723934000, 0.1180361000, 0.2273960000, 0.5353400000", \ - "0.0695017000, 0.0754603000, 0.0888993000, 0.1164835000, 0.1701925000, 0.2784937000, 0.5529737000", \ - "0.1368444000, 0.1440988000, 0.1618251000, 0.2002917000, 0.2723204000, 0.4057055000, 0.6747336000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0666899000, 0.0746915000, 0.0943139000, 0.1451454000, 0.2769396000, 0.6137693000, 1.4769995000", \ - "0.0669890000, 0.0745925000, 0.0945459000, 0.1455379000, 0.2772337000, 0.6141432000, 1.4788204000", \ - "0.0662817000, 0.0743983000, 0.0942320000, 0.1454129000, 0.2767008000, 0.6132475000, 1.4767878000", \ - "0.0704593000, 0.0772090000, 0.0955177000, 0.1445818000, 0.2770036000, 0.6130683000, 1.4762406000", \ - "0.0963924000, 0.1038880000, 0.1209309000, 0.1615968000, 0.2788970000, 0.6133554000, 1.4815781000", \ - "0.1409967000, 0.1517794000, 0.1758681000, 0.2285395000, 0.3324279000, 0.6240568000, 1.4756495000", \ - "0.2112713000, 0.2281732000, 0.2658311000, 0.3441726000, 0.4893629000, 0.7540520000, 1.4989855000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.1524370000, 0.1562156000, 0.1652177000, 0.1847694000, 0.2274293000, 0.3248405000, 0.5668285000", \ - "0.1577551000, 0.1615398000, 0.1704206000, 0.1898380000, 0.2322060000, 0.3298834000, 0.5719084000", \ - "0.1705076000, 0.1742723000, 0.1830548000, 0.2028388000, 0.2454055000, 0.3429561000, 0.5849446000", \ - "0.2018352000, 0.2056278000, 0.2142900000, 0.2341507000, 0.2766742000, 0.3744368000, 0.6163803000", \ - "0.2760139000, 0.2797171000, 0.2885532000, 0.3083006000, 0.3503177000, 0.4480334000, 0.6901245000", \ - "0.4163470000, 0.4206158000, 0.4301804000, 0.4519967000, 0.4965685000, 0.5956702000, 0.8369021000", \ - "0.6354745000, 0.6410795000, 0.6535800000, 0.6799689000, 0.7309184000, 0.8332150000, 1.0757396000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0729571000, 0.0767831000, 0.0855610000, 0.1051180000, 0.1501250000, 0.2615640000, 0.5438555000", \ - "0.0780788000, 0.0819293000, 0.0906172000, 0.1101787000, 0.1550982000, 0.2664361000, 0.5483258000", \ - "0.0896735000, 0.0935824000, 0.1022420000, 0.1218199000, 0.1669563000, 0.2777042000, 0.5595591000", \ - "0.1162951000, 0.1201134000, 0.1287706000, 0.1481128000, 0.1929155000, 0.3044612000, 0.5872474000", \ - "0.1603451000, 0.1646941000, 0.1740214000, 0.1939232000, 0.2393116000, 0.3509389000, 0.6329469000", \ - "0.2177236000, 0.2229863000, 0.2344299000, 0.2572473000, 0.3030774000, 0.4141409000, 0.6961565000", \ - "0.2780553000, 0.2855184000, 0.3006747000, 0.3297755000, 0.3812476000, 0.4917982000, 0.7751212000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0367955000, 0.0404314000, 0.0489703000, 0.0685715000, 0.1162462000, 0.2407151000, 0.5669723000", \ - "0.0364982000, 0.0401138000, 0.0485532000, 0.0687108000, 0.1165884000, 0.2407120000, 0.5670399000", \ - "0.0370223000, 0.0405269000, 0.0492728000, 0.0686926000, 0.1162616000, 0.2407053000, 0.5677405000", \ - "0.0365469000, 0.0401644000, 0.0490309000, 0.0686147000, 0.1162862000, 0.2406243000, 0.5679020000", \ - "0.0372054000, 0.0406863000, 0.0490649000, 0.0690546000, 0.1169503000, 0.2408384000, 0.5667103000", \ - "0.0466726000, 0.0503808000, 0.0591779000, 0.0781604000, 0.1235224000, 0.2435371000, 0.5666794000", \ - "0.0653196000, 0.0701112000, 0.0798662000, 0.1002845000, 0.1438060000, 0.2557638000, 0.5734314000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012790100, 0.0032717300, 0.0083691600, 0.0214085000, 0.0547633000, 0.1400860000"); - values("0.0322127000, 0.0357872000, 0.0449343000, 0.0698594000, 0.1339761000, 0.2925500000, 0.6949157000", \ - "0.0323218000, 0.0355858000, 0.0449539000, 0.0698423000, 0.1339840000, 0.2925694000, 0.6950561000", \ - "0.0324859000, 0.0355868000, 0.0449655000, 0.0698628000, 0.1340489000, 0.2923772000, 0.6943917000", \ - "0.0331704000, 0.0365760000, 0.0455534000, 0.0702291000, 0.1340641000, 0.2925700000, 0.6961952000", \ - "0.0403864000, 0.0428107000, 0.0507881000, 0.0737356000, 0.1353691000, 0.2926742000, 0.6959094000", \ - "0.0565215000, 0.0578785000, 0.0636025000, 0.0827068000, 0.1399094000, 0.2941562000, 0.6957064000", \ - "0.0843154000, 0.0853468000, 0.0895920000, 0.1047764000, 0.1534234000, 0.2976010000, 0.6971332000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o21bai_4") { - leakage_power () { - value : 0.0025183000; - when : "!A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0034819000; - when : "!A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0041637000; - when : "!A1&A2&B1_N"; - } - leakage_power () { - value : 0.0094213000; - when : "!A1&A2&!B1_N"; - } - leakage_power () { - value : 0.0041636000; - when : "A1&!A2&B1_N"; - } - leakage_power () { - value : 0.0078186000; - when : "A1&!A2&!B1_N"; - } - leakage_power () { - value : 0.0041625000; - when : "A1&A2&B1_N"; - } - leakage_power () { - value : 0.0055663000; - when : "A1&A2&!B1_N"; - } - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__o21bai"; - cell_leakage_power : 0.0051620300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0088780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0084370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161869000, 0.0161949000, 0.0162132000, 0.0162119000, 0.0162089000, 0.0162018000, 0.0161856000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016180000, -0.016179400, -0.016178000, -0.016173800, -0.016164200, -0.016142000, -0.016090900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0093190000; - } - pin ("A2") { - capacitance : 0.0085010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156686000, 0.0156626000, 0.0156486000, 0.0156549000, 0.0156694000, 0.0157029000, 0.0157801000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015678700, -0.015668800, -0.015646000, -0.015641400, -0.015630900, -0.015606700, -0.015550800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090990000; - } - pin ("B1_N") { - capacitance : 0.0023560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0202902000, 0.0201568000, 0.0198494000, 0.0200072000, 0.0203709000, 0.0212093000, 0.0231419000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0176135000, 0.0175008000, 0.0172408000, 0.0172952000, 0.0174206000, 0.0177096000, 0.0183757000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024710000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2) | (B1_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0301752000, 0.0287382000, 0.0246497000, 0.0132412000, -0.018818900, -0.109720400, -0.365367100", \ - "0.0296519000, 0.0282188000, 0.0241599000, 0.0127893000, -0.019229100, -0.110113300, -0.365676400", \ - "0.0289305000, 0.0275052000, 0.0234936000, 0.0122541000, -0.019659500, -0.110445900, -0.365963000", \ - "0.0280375000, 0.0266536000, 0.0226946000, 0.0115283000, -0.020231100, -0.110765500, -0.366362800", \ - "0.0276614000, 0.0262177000, 0.0222253000, 0.0109562000, -0.020604400, -0.110937900, -0.366227900", \ - "0.0283697000, 0.0269752000, 0.0228207000, 0.0113387000, -0.021018200, -0.111646900, -0.366745300", \ - "0.0311360000, 0.0296140000, 0.0254483000, 0.0136500000, -0.019305100, -0.110733200, -0.366679900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0292583000, 0.0307296000, 0.0348337000, 0.0463490000, 0.0785110000, 0.1686279000, 0.4210518000", \ - "0.0285359000, 0.0300208000, 0.0341783000, 0.0457938000, 0.0780916000, 0.1683143000, 0.4209360000", \ - "0.0278196000, 0.0293099000, 0.0334766000, 0.0451230000, 0.0776324000, 0.1680077000, 0.4206470000", \ - "0.0272725000, 0.0287530000, 0.0328800000, 0.0445013000, 0.0770178000, 0.1675793000, 0.4208907000", \ - "0.0267908000, 0.0282609000, 0.0323890000, 0.0439317000, 0.0763217000, 0.1668630000, 0.4201090000", \ - "0.0265412000, 0.0280111000, 0.0321451000, 0.0439054000, 0.0764291000, 0.1669074000, 0.4197998000", \ - "0.0272327000, 0.0286438000, 0.0325760000, 0.0437671000, 0.0767057000, 0.1678752000, 0.4213354000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0219253000, 0.0206526000, 0.0169035000, 0.0060159000, -0.025843400, -0.116740000, -0.372617900", \ - "0.0212168000, 0.0200222000, 0.0164352000, 0.0058425000, -0.025736600, -0.116478200, -0.372290700", \ - "0.0202066000, 0.0189741000, 0.0155375000, 0.0051978000, -0.025985300, -0.116446500, -0.372095700", \ - "0.0191724000, 0.0179487000, 0.0143495000, 0.0040218000, -0.026780300, -0.116748900, -0.372143200", \ - "0.0200462000, 0.0185828000, 0.0144169000, 0.0032621000, -0.027836000, -0.117449700, -0.372471500", \ - "0.0206985000, 0.0191843000, 0.0150771000, 0.0036695000, -0.028278400, -0.118559600, -0.373126000", \ - "0.0249877000, 0.0234631000, 0.0189247000, 0.0066149000, -0.026679100, -0.117962400, -0.373537900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0198451000, 0.0213493000, 0.0255255000, 0.0371264000, 0.0694784000, 0.1595507000, 0.4125053000", \ - "0.0187007000, 0.0202413000, 0.0245153000, 0.0363203000, 0.0688539000, 0.1592135000, 0.4118450000", \ - "0.0176681000, 0.0191952000, 0.0234535000, 0.0351994000, 0.0679583000, 0.1588868000, 0.4116713000", \ - "0.0171518000, 0.0186489000, 0.0228706000, 0.0347021000, 0.0672342000, 0.1581691000, 0.4114634000", \ - "0.0172998000, 0.0187257000, 0.0232682000, 0.0349193000, 0.0666127000, 0.1572167000, 0.4103776000", \ - "0.0205664000, 0.0217265000, 0.0247710000, 0.0361485000, 0.0689615000, 0.1576993000, 0.4099934000", \ - "0.0252527000, 0.0265975000, 0.0303500000, 0.0409647000, 0.0720391000, 0.1607133000, 0.4116145000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0210202000, 0.0196206000, 0.0157736000, 0.0047465000, -0.026875900, -0.117127400, -0.372501300", \ - "0.0209795000, 0.0196556000, 0.0157228000, 0.0047044000, -0.026906000, -0.117225200, -0.372725200", \ - "0.0210634000, 0.0197205000, 0.0158094000, 0.0047727000, -0.026783000, -0.117103900, -0.372438900", \ - "0.0205640000, 0.0192031000, 0.0152930000, 0.0042452000, -0.027320800, -0.117512300, -0.372827800", \ - "0.0201991000, 0.0187976000, 0.0148548000, 0.0036752000, -0.028018500, -0.118228000, -0.373481800", \ - "0.0188428000, 0.0174097000, 0.0135211000, 0.0023780000, -0.029121000, -0.119220400, -0.374224600", \ - "0.0205977000, 0.0190895000, 0.0158975000, 0.0040107000, -0.028358000, -0.118902600, -0.374093600"); - } - related_pin : "B1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014042540, 0.0039438570, 0.0110763500, 0.0311080200, 0.0873671300, 0.2453712000"); - values("0.0170437000, 0.0187087000, 0.0233470000, 0.0359496000, 0.0696891000, 0.1605879000, 0.4134346000", \ - "0.0171289000, 0.0187417000, 0.0233532000, 0.0359545000, 0.0696465000, 0.1606886000, 0.4139154000", \ - "0.0171445000, 0.0187410000, 0.0232944000, 0.0358856000, 0.0696471000, 0.1606921000, 0.4135599000", \ - "0.0167737000, 0.0183837000, 0.0228355000, 0.0350378000, 0.0687650000, 0.1600168000, 0.4132261000", \ - "0.0166014000, 0.0181455000, 0.0224190000, 0.0344685000, 0.0673764000, 0.1587805000, 0.4126812000", \ - "0.0169301000, 0.0183592000, 0.0225094000, 0.0342350000, 0.0664206000, 0.1575348000, 0.4117358000", \ - "0.0181014000, 0.0195336000, 0.0235362000, 0.0350380000, 0.0679069000, 0.1571405000, 0.4115566000"); - } - } - max_capacitance : 0.2453710000; - max_transition : 1.4960120000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0440453000, 0.0459953000, 0.0513807000, 0.0651988000, 0.1004516000, 0.1938694000, 0.4503322000", \ - "0.0481159000, 0.0500545000, 0.0554030000, 0.0692412000, 0.1045258000, 0.1979164000, 0.4545971000", \ - "0.0555655000, 0.0575843000, 0.0629263000, 0.0767736000, 0.1121917000, 0.2056736000, 0.4623653000", \ - "0.0677128000, 0.0700456000, 0.0762329000, 0.0913887000, 0.1277891000, 0.2218260000, 0.4786559000", \ - "0.0855016000, 0.0885930000, 0.0967364000, 0.1158863000, 0.1608179000, 0.2607937000, 0.5191891000", \ - "0.0978176000, 0.1028365000, 0.1151904000, 0.1447563000, 0.2094737000, 0.3380592000, 0.6141163000", \ - "0.0748403000, 0.0825195000, 0.1022134000, 0.1497154000, 0.2519786000, 0.4464300000, 0.8010482000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0931795000, 0.0973606000, 0.1088489000, 0.1403276000, 0.2261182000, 0.4631295000, 1.1278295000", \ - "0.0976295000, 0.1018591000, 0.1135215000, 0.1451895000, 0.2313698000, 0.4684883000, 1.1308050000", \ - "0.1100299000, 0.1142680000, 0.1259065000, 0.1577690000, 0.2443810000, 0.4825165000, 1.1443871000", \ - "0.1378272000, 0.1419587000, 0.1536869000, 0.1854007000, 0.2719947000, 0.5100457000, 1.1729715000", \ - "0.1929523000, 0.1978844000, 0.2111858000, 0.2454740000, 0.3316984000, 0.5698768000, 1.2339464000", \ - "0.2878989000, 0.2947042000, 0.3127029000, 0.3576006000, 0.4643778000, 0.7083590000, 1.3739446000", \ - "0.4451382000, 0.4555652000, 0.4833176000, 0.5509301000, 0.6995142000, 1.0120649000, 1.6931977000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0284359000, 0.0307200000, 0.0370139000, 0.0540114000, 0.0997831000, 0.2258530000, 0.5806068000", \ - "0.0283521000, 0.0307179000, 0.0370066000, 0.0539889000, 0.0997660000, 0.2257716000, 0.5802084000", \ - "0.0285447000, 0.0307827000, 0.0369836000, 0.0538145000, 0.0996976000, 0.2258052000, 0.5802224000", \ - "0.0327943000, 0.0350730000, 0.0412540000, 0.0573086000, 0.1008883000, 0.2257620000, 0.5810464000", \ - "0.0461230000, 0.0485830000, 0.0554200000, 0.0724557000, 0.1157175000, 0.2317180000, 0.5806298000", \ - "0.0778833000, 0.0813958000, 0.0900416000, 0.1118160000, 0.1604574000, 0.2744256000, 0.5943423000", \ - "0.1390714000, 0.1441346000, 0.1572336000, 0.1885095000, 0.2538123000, 0.3869940000, 0.6967699000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0709392000, 0.0760789000, 0.0905430000, 0.1308214000, 0.2456418000, 0.5697400000, 1.4781273000", \ - "0.0710622000, 0.0761323000, 0.0903528000, 0.1309810000, 0.2457524000, 0.5680319000, 1.4754152000", \ - "0.0711935000, 0.0761628000, 0.0906620000, 0.1309059000, 0.2457557000, 0.5700304000, 1.4762487000", \ - "0.0714898000, 0.0762927000, 0.0903710000, 0.1306990000, 0.2451609000, 0.5688305000, 1.4772471000", \ - "0.0868584000, 0.0914103000, 0.1036546000, 0.1393530000, 0.2478735000, 0.5677602000, 1.4806208000", \ - "0.1228774000, 0.1282001000, 0.1427095000, 0.1814362000, 0.2829039000, 0.5760444000, 1.4754447000", \ - "0.2009880000, 0.2076182000, 0.2270391000, 0.2739862000, 0.3886100000, 0.6684663000, 1.4944899000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0314923000, 0.0334288000, 0.0385255000, 0.0515578000, 0.0849887000, 0.1728592000, 0.4164496000", \ - "0.0355146000, 0.0374941000, 0.0427482000, 0.0560524000, 0.0894503000, 0.1772844000, 0.4214329000", \ - "0.0426076000, 0.0448069000, 0.0502582000, 0.0637795000, 0.0976721000, 0.1856538000, 0.4298861000", \ - "0.0516531000, 0.0542920000, 0.0610660000, 0.0772545000, 0.1137243000, 0.2030771000, 0.4466677000", \ - "0.0588969000, 0.0628031000, 0.0732274000, 0.0965072000, 0.1448197000, 0.2436437000, 0.4884269000", \ - "0.0506014000, 0.0570693000, 0.0732008000, 0.1102031000, 0.1839917000, 0.3203172000, 0.5883199000", \ - "-0.009965900, 0.0025010000, 0.0285074000, 0.0889274000, 0.2071110000, 0.4158268000, 0.7774484000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0734087000, 0.0777050000, 0.0894738000, 0.1212430000, 0.2072806000, 0.4443719000, 1.1068635000", \ - "0.0756299000, 0.0799493000, 0.0919276000, 0.1241298000, 0.2107843000, 0.4482192000, 1.1105875000", \ - "0.0855062000, 0.0897945000, 0.1016568000, 0.1335181000, 0.2208851000, 0.4591610000, 1.1221144000", \ - "0.1138240000, 0.1179791000, 0.1294159000, 0.1610633000, 0.2472281000, 0.4861670000, 1.1498339000", \ - "0.1740860000, 0.1795008000, 0.1940635000, 0.2287592000, 0.3139382000, 0.5518981000, 1.2183610000", \ - "0.2719662000, 0.2801276000, 0.3014083000, 0.3535429000, 0.4665565000, 0.7039054000, 1.3644218000", \ - "0.4378227000, 0.4494367000, 0.4798419000, 0.5559559000, 0.7252861000, 1.0582485000, 1.7264847000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0161717000, 0.0184821000, 0.0247070000, 0.0414767000, 0.0852181000, 0.2043832000, 0.5394111000", \ - "0.0162642000, 0.0185839000, 0.0247047000, 0.0415625000, 0.0850736000, 0.2041400000, 0.5387730000", \ - "0.0176010000, 0.0197012000, 0.0255326000, 0.0415357000, 0.0852846000, 0.2042641000, 0.5387381000", \ - "0.0230699000, 0.0253679000, 0.0314581000, 0.0471475000, 0.0871741000, 0.2040969000, 0.5400020000", \ - "0.0382552000, 0.0409680000, 0.0480846000, 0.0650870000, 0.1062241000, 0.2120201000, 0.5385180000", \ - "0.0706159000, 0.0742921000, 0.0839691000, 0.1066658000, 0.1546736000, 0.2620604000, 0.5559566000", \ - "0.1387436000, 0.1427091000, 0.1554590000, 0.1862267000, 0.2526679000, 0.3845500000, 0.6718377000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0712513000, 0.0760694000, 0.0901493000, 0.1305703000, 0.2454267000, 0.5677683000, 1.4792910000", \ - "0.0709466000, 0.0762328000, 0.0901969000, 0.1307384000, 0.2455048000, 0.5679633000, 1.4758351000", \ - "0.0704939000, 0.0758293000, 0.0903119000, 0.1308132000, 0.2455908000, 0.5689680000, 1.4755471000", \ - "0.0736945000, 0.0782914000, 0.0911604000, 0.1302713000, 0.2455421000, 0.5698816000, 1.4791229000", \ - "0.0992799000, 0.1043367000, 0.1163209000, 0.1478590000, 0.2485665000, 0.5695119000, 1.4781257000", \ - "0.1430582000, 0.1506578000, 0.1685237000, 0.2115542000, 0.3069656000, 0.5810749000, 1.4806063000", \ - "0.2159351000, 0.2264851000, 0.2542067000, 0.3194503000, 0.4561690000, 0.7182601000, 1.4960116000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.1384206000, 0.1407730000, 0.1468124000, 0.1624989000, 0.1997695000, 0.2939443000, 0.5507340000", \ - "0.1435288000, 0.1456268000, 0.1519376000, 0.1677506000, 0.2049535000, 0.2992627000, 0.5559693000", \ - "0.1567238000, 0.1588052000, 0.1651810000, 0.1808874000, 0.2181032000, 0.3123524000, 0.5691086000", \ - "0.1878317000, 0.1899753000, 0.1963749000, 0.2119395000, 0.2494957000, 0.3438890000, 0.6005772000", \ - "0.2601733000, 0.2625975000, 0.2686233000, 0.2843900000, 0.3218285000, 0.4161936000, 0.6728440000", \ - "0.3901959000, 0.3929443000, 0.3996719000, 0.4174784000, 0.4573181000, 0.5531065000, 0.8098127000", \ - "0.5901216000, 0.5937189000, 0.6034919000, 0.6243935000, 0.6712713000, 0.7709208000, 1.0264382000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0802303000, 0.0828216000, 0.0897552000, 0.1065305000, 0.1479954000, 0.2580811000, 0.5634354000", \ - "0.0852210000, 0.0877926000, 0.0945456000, 0.1113894000, 0.1525534000, 0.2633655000, 0.5690813000", \ - "0.0965663000, 0.0991403000, 0.1059620000, 0.1227227000, 0.1642057000, 0.2747276000, 0.5793768000", \ - "0.1231249000, 0.1256697000, 0.1323551000, 0.1487037000, 0.1901341000, 0.3007211000, 0.6067685000", \ - "0.1687420000, 0.1716944000, 0.1789117000, 0.1959349000, 0.2373262000, 0.3479532000, 0.6534885000", \ - "0.2284829000, 0.2321100000, 0.2408890000, 0.2607420000, 0.3032444000, 0.4140650000, 0.7189541000", \ - "0.2910076000, 0.2959088000, 0.3075435000, 0.3331161000, 0.3826218000, 0.4924672000, 0.7975318000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0355166000, 0.0378925000, 0.0444812000, 0.0605370000, 0.1039755000, 0.2266987000, 0.5803031000", \ - "0.0355077000, 0.0380502000, 0.0441092000, 0.0603271000, 0.1038556000, 0.2270035000, 0.5811510000", \ - "0.0354042000, 0.0380364000, 0.0441734000, 0.0605566000, 0.1039545000, 0.2269260000, 0.5804460000", \ - "0.0353744000, 0.0381193000, 0.0442861000, 0.0604074000, 0.1040227000, 0.2269441000, 0.5808179000", \ - "0.0364226000, 0.0390387000, 0.0452961000, 0.0614819000, 0.1044424000, 0.2271321000, 0.5809930000", \ - "0.0464936000, 0.0489726000, 0.0555687000, 0.0710434000, 0.1122095000, 0.2301228000, 0.5806363000", \ - "0.0656170000, 0.0686592000, 0.0763573000, 0.0929557000, 0.1324033000, 0.2412654000, 0.5857642000"); - } - related_pin : "B1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014042500, 0.0039438600, 0.0110764000, 0.0311080000, 0.0873671000, 0.2453710000"); - values("0.0355269000, 0.0376697000, 0.0443425000, 0.0642107000, 0.1216572000, 0.2777886000, 0.7120294000", \ - "0.0355621000, 0.0377426000, 0.0441097000, 0.0641448000, 0.1216520000, 0.2777457000, 0.7120970000", \ - "0.0354919000, 0.0377202000, 0.0441257000, 0.0642392000, 0.1216620000, 0.2777835000, 0.7108356000", \ - "0.0359094000, 0.0381816000, 0.0446861000, 0.0645941000, 0.1217610000, 0.2777941000, 0.7112239000", \ - "0.0433061000, 0.0450502000, 0.0504815000, 0.0682134000, 0.1232730000, 0.2779852000, 0.7117710000", \ - "0.0598727000, 0.0607690000, 0.0643948000, 0.0788072000, 0.1289105000, 0.2794971000, 0.7112526000", \ - "0.0887909000, 0.0893937000, 0.0917727000, 0.1024066000, 0.1434644000, 0.2837685000, 0.7131604000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221a_1") { - leakage_power () { - value : 0.0038197000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0118394000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0024973000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0020294000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0025006000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0020294000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0025055000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0020294000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0025139000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0020287000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0031084000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0029542000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0025415000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0025139000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0020287000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029637000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0028095000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0023967000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0025139000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0020287000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0025328000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0023786000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0019659000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0023061000; - when : "A1&A2&B1&B2&!C1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o221a"; - cell_leakage_power : 0.0027276230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041904000, 0.0041900000, 0.0041890000, 0.0041901000, 0.0041926000, 0.0041984000, 0.0042117000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004185500, -0.004183100, -0.004177700, -0.004178000, -0.004178800, -0.004180600, -0.004184800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - } - pin ("A2") { - capacitance : 0.0024010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040361000, 0.0040363000, 0.0040366000, 0.0040370000, 0.0040380000, 0.0040401000, 0.0040452000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004022600, -0.004024400, -0.004028600, -0.004029300, -0.004031000, -0.004034800, -0.004043800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025700000; - } - pin ("B1") { - capacitance : 0.0023410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040072000, 0.0040117000, 0.0040221000, 0.0040224000, 0.0040232000, 0.0040251000, 0.0040293000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004009500, -0.004008200, -0.004005200, -0.004004200, -0.004001800, -0.003996400, -0.003983900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024270000; - } - pin ("B2") { - capacitance : 0.0023550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040170000, 0.0040170000, 0.0040172000, 0.0040209000, 0.0040295000, 0.0040491000, 0.0040944000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004008800, -0.004008600, -0.004008100, -0.004007200, -0.004005300, -0.004000900, -0.003990800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024840000; - } - pin ("C1") { - capacitance : 0.0023180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047379000, 0.0047374000, 0.0047364000, 0.0047365000, 0.0047366000, 0.0047371000, 0.0047380000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002526500, -0.002528600, -0.002533300, -0.002522400, -0.002497200, -0.002439200, -0.002305500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023770000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A1&B2&C1) | (A2&B2&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0191647000, 0.0182827000, 0.0158224000, 0.0083658000, -0.013545300, -0.071912400, -0.224072600", \ - "0.0189457000, 0.0181624000, 0.0157167000, 0.0082360000, -0.013671000, -0.072033400, -0.224200600", \ - "0.0188645000, 0.0179809000, 0.0155218000, 0.0080298000, -0.013851500, -0.072183500, -0.224306400", \ - "0.0185477000, 0.0177169000, 0.0152598000, 0.0077543000, -0.014015500, -0.072396700, -0.224561800", \ - "0.0183855000, 0.0175095000, 0.0150686000, 0.0075688000, -0.014213000, -0.072543200, -0.224614500", \ - "0.0180015000, 0.0171328000, 0.0148776000, 0.0074457000, -0.014265400, -0.072545100, -0.224620300", \ - "0.0218796000, 0.0205409000, 0.0170748000, 0.0086203000, -0.014030100, -0.072244100, -0.224328900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0180753000, 0.0194697000, 0.0229774000, 0.0316952000, 0.0538711000, 0.1115898000, 0.2629202000", \ - "0.0179957000, 0.0193909000, 0.0228714000, 0.0315827000, 0.0537866000, 0.1114510000, 0.2618563000", \ - "0.0178486000, 0.0192442000, 0.0227453000, 0.0314606000, 0.0536423000, 0.1112853000, 0.2616563000", \ - "0.0176681000, 0.0190698000, 0.0225670000, 0.0312848000, 0.0534676000, 0.1112694000, 0.2615619000", \ - "0.0175347000, 0.0188898000, 0.0223636000, 0.0311378000, 0.0534552000, 0.1117805000, 0.2628215000", \ - "0.0177591000, 0.0190535000, 0.0224325000, 0.0309075000, 0.0533392000, 0.1109950000, 0.2616235000", \ - "0.0180933000, 0.0193413000, 0.0226445000, 0.0313640000, 0.0537537000, 0.1119471000, 0.2610294000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0171141000, 0.0162207000, 0.0137555000, 0.0062897000, -0.015418200, -0.073700500, -0.225715300", \ - "0.0169723000, 0.0160903000, 0.0136236000, 0.0061553000, -0.015579900, -0.073831900, -0.225841500", \ - "0.0167341000, 0.0158252000, 0.0134141000, 0.0059505000, -0.015779200, -0.074042500, -0.226090200", \ - "0.0165192000, 0.0156807000, 0.0132334000, 0.0057390000, -0.015973800, -0.074229800, -0.226251800", \ - "0.0164515000, 0.0155909000, 0.0131600000, 0.0056691000, -0.016012000, -0.074275500, -0.226282900", \ - "0.0166526000, 0.0157322000, 0.0133992000, 0.0059482000, -0.015759400, -0.073999900, -0.226002100", \ - "0.0206805000, 0.0193236000, 0.0158917000, 0.0071218000, -0.015478700, -0.073542900, -0.225540300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0166610000, 0.0180812000, 0.0216595000, 0.0305127000, 0.0530691000, 0.1116605000, 0.2615949000", \ - "0.0166665000, 0.0180764000, 0.0216090000, 0.0305167000, 0.0530078000, 0.1111159000, 0.2620326000", \ - "0.0165892000, 0.0179995000, 0.0215430000, 0.0304236000, 0.0529316000, 0.1111650000, 0.2628335000", \ - "0.0163074000, 0.0177297000, 0.0212933000, 0.0301348000, 0.0526626000, 0.1108444000, 0.2614678000", \ - "0.0160475000, 0.0174447000, 0.0209505000, 0.0298273000, 0.0525127000, 0.1105583000, 0.2613778000", \ - "0.0161474000, 0.0174942000, 0.0209026000, 0.0294145000, 0.0520257000, 0.1105655000, 0.2608906000", \ - "0.0163722000, 0.0176248000, 0.0209596000, 0.0297923000, 0.0522357000, 0.1105047000, 0.2600497000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0148364000, 0.0142513000, 0.0121355000, 0.0053088000, -0.015919300, -0.074141800, -0.226238400", \ - "0.0147750000, 0.0140960000, 0.0121029000, 0.0051431000, -0.016047700, -0.074263700, -0.226364200", \ - "0.0144953000, 0.0138491000, 0.0118301000, 0.0049459000, -0.016295600, -0.074495500, -0.226587300", \ - "0.0142319000, 0.0135783000, 0.0115813000, 0.0046216000, -0.016580400, -0.074772500, -0.226863100", \ - "0.0140620000, 0.0133749000, 0.0112959000, 0.0043893000, -0.016841500, -0.075014600, -0.227078900", \ - "0.0144921000, 0.0132065000, 0.0108315000, 0.0041789000, -0.017010500, -0.075156500, -0.227202100", \ - "0.0186486000, 0.0173130000, 0.0139565000, 0.0053387000, -0.017087900, -0.075070100, -0.227008600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0179487000, 0.0193224000, 0.0228153000, 0.0315401000, 0.0538329000, 0.1117117000, 0.2622702000", \ - "0.0178296000, 0.0192277000, 0.0227306000, 0.0314509000, 0.0537345000, 0.1117056000, 0.2632156000", \ - "0.0177057000, 0.0191062000, 0.0226124000, 0.0313412000, 0.0536117000, 0.1120714000, 0.2629099000", \ - "0.0175363000, 0.0189423000, 0.0224539000, 0.0311789000, 0.0535195000, 0.1119742000, 0.2618205000", \ - "0.0174372000, 0.0188168000, 0.0223132000, 0.0310693000, 0.0534261000, 0.1114491000, 0.2630553000", \ - "0.0176723000, 0.0189977000, 0.0223488000, 0.0308543000, 0.0532977000, 0.1111257000, 0.2618241000", \ - "0.0182545000, 0.0195056000, 0.0228602000, 0.0314806000, 0.0538102000, 0.1121233000, 0.2627823000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0126815000, 0.0120351000, 0.0099754000, 0.0030855000, -0.018143900, -0.076345500, -0.228440400", \ - "0.0124908000, 0.0118719000, 0.0098000000, 0.0029575000, -0.018284900, -0.076486700, -0.228582300", \ - "0.0123449000, 0.0116794000, 0.0096705000, 0.0027277000, -0.018489100, -0.076691400, -0.228775900", \ - "0.0120273000, 0.0113613000, 0.0093409000, 0.0024084000, -0.018805600, -0.076991800, -0.229065000", \ - "0.0118630000, 0.0112315000, 0.0091401000, 0.0022388000, -0.019010000, -0.077161600, -0.229208600", \ - "0.0123171000, 0.0110142000, 0.0087893000, 0.0020651000, -0.019067600, -0.077159000, -0.229162800", \ - "0.0173053000, 0.0159624000, 0.0125673000, 0.0038799000, -0.018576300, -0.076530400, -0.228451900"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0166506000, 0.0180496000, 0.0215556000, 0.0302823000, 0.0525224000, 0.1109484000, 0.2617690000", \ - "0.0166466000, 0.0180434000, 0.0215491000, 0.0302787000, 0.0525232000, 0.1104353000, 0.2618419000", \ - "0.0165142000, 0.0179233000, 0.0214472000, 0.0301638000, 0.0524652000, 0.1108577000, 0.2606306000", \ - "0.0162676000, 0.0176729000, 0.0211877000, 0.0299102000, 0.0522415000, 0.1107003000, 0.2606054000", \ - "0.0160879000, 0.0174700000, 0.0208901000, 0.0296246000, 0.0520045000, 0.1105180000, 0.2604536000", \ - "0.0161801000, 0.0174752000, 0.0208106000, 0.0293205000, 0.0517714000, 0.1095464000, 0.2603041000", \ - "0.0166224000, 0.0178807000, 0.0212721000, 0.0298936000, 0.0522310000, 0.1106537000, 0.2606349000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0111360000, 0.0107314000, 0.0088018000, 0.0016518000, -0.020305400, -0.078843200, -0.231098400", \ - "0.0109401000, 0.0105962000, 0.0086889000, 0.0015245000, -0.020429500, -0.078979700, -0.231233800", \ - "0.0107020000, 0.0103047000, 0.0083471000, 0.0012094000, -0.020723500, -0.079253800, -0.231527200", \ - "0.0103966000, 0.0099339000, 0.0080477000, 0.0008517000, -0.021015700, -0.079509000, -0.231745700", \ - "0.0098704000, 0.0096110000, 0.0076783000, 0.0006382000, -0.021164700, -0.079600400, -0.231797000", \ - "0.0135093000, 0.0122563000, 0.0090099000, 0.0004505000, -0.020962000, -0.079317700, -0.231461200", \ - "0.0163869000, 0.0150384000, 0.0116154000, 0.0029896000, -0.019410900, -0.077644500, -0.229623800"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436550, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0164135000, 0.0178121000, 0.0213188000, 0.0300640000, 0.0524060000, 0.1110255000, 0.2619911000", \ - "0.0163356000, 0.0177337000, 0.0212194000, 0.0299926000, 0.0523425000, 0.1104552000, 0.2610195000", \ - "0.0161666000, 0.0175695000, 0.0210795000, 0.0298358000, 0.0522036000, 0.1108273000, 0.2617616000", \ - "0.0159314000, 0.0173383000, 0.0208382000, 0.0296348000, 0.0520220000, 0.1101406000, 0.2607556000", \ - "0.0158336000, 0.0172179000, 0.0206808000, 0.0294834000, 0.0518581000, 0.1099557000, 0.2604823000", \ - "0.0163697000, 0.0176524000, 0.0210403000, 0.0295197000, 0.0520167000, 0.1097846000, 0.2605831000", \ - "0.0173967000, 0.0185982000, 0.0219757000, 0.0305733000, 0.0529273000, 0.1112488000, 0.2605307000"); - } - } - max_capacitance : 0.1529030000; - max_transition : 1.5048690000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.2184170000, 0.2260216000, 0.2414480000, 0.2708170000, 0.3279189000, 0.4506244000, 0.7512872000", \ - "0.2236838000, 0.2312191000, 0.2465943000, 0.2760642000, 0.3331782000, 0.4559153000, 0.7565999000", \ - "0.2362266000, 0.2438414000, 0.2592729000, 0.2890192000, 0.3461500000, 0.4683764000, 0.7693897000", \ - "0.2635328000, 0.2712307000, 0.2867009000, 0.3164023000, 0.3730869000, 0.4956414000, 0.7968403000", \ - "0.3256488000, 0.3332537000, 0.3488629000, 0.3784454000, 0.4357193000, 0.5584391000, 0.8592252000", \ - "0.4588712000, 0.4670921000, 0.4836072000, 0.5146630000, 0.5732227000, 0.6960017000, 0.9974314000", \ - "0.6952943000, 0.7049389000, 0.7242946000, 0.7595742000, 0.8242990000, 0.9526547000, 1.2553335000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1424957000, 0.1509294000, 0.1693793000, 0.2099262000, 0.3060464000, 0.5514496000, 1.1925040000", \ - "0.1469332000, 0.1553354000, 0.1738220000, 0.2143718000, 0.3104678000, 0.5558839000, 1.1938462000", \ - "0.1559047000, 0.1642518000, 0.1827755000, 0.2233930000, 0.3194327000, 0.5667946000, 1.2041256000", \ - "0.1732266000, 0.1815813000, 0.2001148000, 0.2407090000, 0.3368399000, 0.5827930000, 1.2220801000", \ - "0.2070818000, 0.2157243000, 0.2345336000, 0.2755397000, 0.3722416000, 0.6189471000, 1.2576655000", \ - "0.2597334000, 0.2692746000, 0.2895816000, 0.3323771000, 0.4301215000, 0.6769069000, 1.3160686000", \ - "0.3150777000, 0.3268141000, 0.3507547000, 0.3976108000, 0.4976387000, 0.7457038000, 1.3837804000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0329104000, 0.0374810000, 0.0480814000, 0.0719288000, 0.1264784000, 0.2684532000, 0.6576961000", \ - "0.0325522000, 0.0377528000, 0.0483025000, 0.0719334000, 0.1265339000, 0.2684530000, 0.6579680000", \ - "0.0329130000, 0.0374972000, 0.0481025000, 0.0712048000, 0.1261685000, 0.2683187000, 0.6615012000", \ - "0.0326288000, 0.0376876000, 0.0477967000, 0.0714942000, 0.1263259000, 0.2683500000, 0.6641170000", \ - "0.0324698000, 0.0372950000, 0.0482822000, 0.0717137000, 0.1261591000, 0.2684590000, 0.6605635000", \ - "0.0362705000, 0.0410752000, 0.0520125000, 0.0744679000, 0.1283739000, 0.2694509000, 0.6613579000", \ - "0.0462722000, 0.0515268000, 0.0627615000, 0.0878338000, 0.1411680000, 0.2777835000, 0.6603801000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0320047000, 0.0398815000, 0.0587812000, 0.1075806000, 0.2389211000, 0.5907059000, 1.5036415000", \ - "0.0319406000, 0.0398346000, 0.0588216000, 0.1075906000, 0.2390023000, 0.5892050000, 1.5023498000", \ - "0.0321375000, 0.0398504000, 0.0588225000, 0.1076968000, 0.2390561000, 0.5906660000, 1.4977007000", \ - "0.0320341000, 0.0397414000, 0.0588193000, 0.1076651000, 0.2388837000, 0.5907109000, 1.4995379000", \ - "0.0334098000, 0.0412014000, 0.0598904000, 0.1083942000, 0.2392489000, 0.5908891000, 1.5034869000", \ - "0.0377582000, 0.0456132000, 0.0639959000, 0.1114591000, 0.2402322000, 0.5890622000, 1.5006980000", \ - "0.0478635000, 0.0564307000, 0.0748502000, 0.1200123000, 0.2440752000, 0.5912550000, 1.4987975000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.2040022000, 0.2115736000, 0.2271192000, 0.2568587000, 0.3139668000, 0.4368515000, 0.7378321000", \ - "0.2078095000, 0.2153818000, 0.2308791000, 0.2606093000, 0.3177401000, 0.4405656000, 0.7417258000", \ - "0.2181230000, 0.2257463000, 0.2413786000, 0.2709631000, 0.3283203000, 0.4512552000, 0.7521916000", \ - "0.2456453000, 0.2532972000, 0.2687877000, 0.2984532000, 0.3558110000, 0.4787482000, 0.7797284000", \ - "0.3135635000, 0.3212633000, 0.3368509000, 0.3665145000, 0.4239662000, 0.5468720000, 0.8482403000", \ - "0.4649461000, 0.4733829000, 0.4900407000, 0.5210376000, 0.5793174000, 0.7027911000, 1.0043181000", \ - "0.7142635000, 0.7251561000, 0.7468103000, 0.7843304000, 0.8488449000, 0.9764189000, 1.2797875000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1341236000, 0.1426406000, 0.1615200000, 0.2027406000, 0.3002661000, 0.5481597000, 1.1878423000", \ - "0.1390126000, 0.1475167000, 0.1663653000, 0.2076923000, 0.3049182000, 0.5540788000, 1.1919674000", \ - "0.1485607000, 0.1570428000, 0.1758155000, 0.2171354000, 0.3145379000, 0.5614145000, 1.2031738000", \ - "0.1662963000, 0.1748142000, 0.1936698000, 0.2349152000, 0.3323807000, 0.5796650000, 1.2202851000", \ - "0.2007937000, 0.2096688000, 0.2288546000, 0.2704942000, 0.3679567000, 0.6158123000, 1.2552441000", \ - "0.2534139000, 0.2631223000, 0.2839497000, 0.3274593000, 0.4261266000, 0.6740242000, 1.3151502000", \ - "0.3064640000, 0.3190319000, 0.3442204000, 0.3925213000, 0.4936606000, 0.7420302000, 1.3818979000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0328695000, 0.0374209000, 0.0477912000, 0.0712583000, 0.1263021000, 0.2684560000, 0.6609221000", \ - "0.0327571000, 0.0376090000, 0.0478380000, 0.0714099000, 0.1262034000, 0.2683759000, 0.6610524000", \ - "0.0325358000, 0.0373627000, 0.0483756000, 0.0718845000, 0.1258983000, 0.2684076000, 0.6627116000", \ - "0.0325616000, 0.0372972000, 0.0480691000, 0.0718279000, 0.1258516000, 0.2684153000, 0.6618370000", \ - "0.0324527000, 0.0372621000, 0.0484880000, 0.0717072000, 0.1262553000, 0.2684089000, 0.6604670000", \ - "0.0383165000, 0.0427377000, 0.0526387000, 0.0749433000, 0.1284005000, 0.2694887000, 0.6631515000", \ - "0.0544266000, 0.0598431000, 0.0708293000, 0.0917034000, 0.1414077000, 0.2775340000, 0.6608539000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0318396000, 0.0396609000, 0.0587715000, 0.1073113000, 0.2384767000, 0.5896869000, 1.5031884000", \ - "0.0317904000, 0.0397217000, 0.0587225000, 0.1073406000, 0.2383106000, 0.5901475000, 1.4988419000", \ - "0.0318963000, 0.0396645000, 0.0586555000, 0.1074345000, 0.2386012000, 0.5893417000, 1.5045144000", \ - "0.0319832000, 0.0395851000, 0.0587081000, 0.1074564000, 0.2387662000, 0.5905197000, 1.5002347000", \ - "0.0335273000, 0.0413275000, 0.0599076000, 0.1080340000, 0.2387646000, 0.5901568000, 1.4993865000", \ - "0.0385110000, 0.0467715000, 0.0652710000, 0.1121187000, 0.2404531000, 0.5893315000, 1.5037890000", \ - "0.0511318000, 0.0597126000, 0.0779680000, 0.1225372000, 0.2451956000, 0.5916025000, 1.4944849000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1833475000, 0.1912697000, 0.2080728000, 0.2412976000, 0.3047914000, 0.4326420000, 0.7343380000", \ - "0.1886668000, 0.1965708000, 0.2133261000, 0.2466847000, 0.3101672000, 0.4381155000, 0.7403245000", \ - "0.2008691000, 0.2088121000, 0.2255527000, 0.2594531000, 0.3221441000, 0.4501722000, 0.7518901000", \ - "0.2275993000, 0.2353682000, 0.2521976000, 0.2857979000, 0.3491751000, 0.4772089000, 0.7793859000", \ - "0.2894628000, 0.2973241000, 0.3139526000, 0.3478053000, 0.4113006000, 0.5392985000, 0.8412550000", \ - "0.4131110000, 0.4216706000, 0.4398305000, 0.4760072000, 0.5425592000, 0.6722608000, 0.9747564000", \ - "0.6262174000, 0.6368546000, 0.6584974000, 0.7007217000, 0.7764164000, 0.9149366000, 1.2210313000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1345264000, 0.1429021000, 0.1613535000, 0.2019970000, 0.2982612000, 0.5446897000, 1.1833851000", \ - "0.1386580000, 0.1470749000, 0.1655224000, 0.2061468000, 0.3025169000, 0.5484622000, 1.1900438000", \ - "0.1480561000, 0.1564871000, 0.1749395000, 0.2155126000, 0.3120660000, 0.5586011000, 1.2008136000", \ - "0.1688568000, 0.1772694000, 0.1957994000, 0.2364333000, 0.3331482000, 0.5806360000, 1.2197173000", \ - "0.2121278000, 0.2208657000, 0.2396963000, 0.2808107000, 0.3775754000, 0.6245880000, 1.2649801000", \ - "0.2755610000, 0.2852340000, 0.3055047000, 0.3480178000, 0.4458019000, 0.6935630000, 1.3330109000", \ - "0.3384643000, 0.3505148000, 0.3743005000, 0.4205249000, 0.5198518000, 0.7679204000, 1.4075490000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0315911000, 0.0370422000, 0.0503110000, 0.0787721000, 0.1354839000, 0.2738488000, 0.6602491000", \ - "0.0312860000, 0.0369724000, 0.0502116000, 0.0781410000, 0.1356584000, 0.2745144000, 0.6633646000", \ - "0.0315467000, 0.0371983000, 0.0502454000, 0.0779783000, 0.1355338000, 0.2740749000, 0.6602975000", \ - "0.0312302000, 0.0369307000, 0.0502323000, 0.0786418000, 0.1353329000, 0.2746450000, 0.6630428000", \ - "0.0316310000, 0.0370858000, 0.0502112000, 0.0781988000, 0.1349570000, 0.2742048000, 0.6604337000", \ - "0.0366976000, 0.0426291000, 0.0562343000, 0.0847025000, 0.1403156000, 0.2768169000, 0.6626033000", \ - "0.0483017000, 0.0546629000, 0.0698166000, 0.1007400000, 0.1590372000, 0.2907675000, 0.6629635000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0320325000, 0.0399713000, 0.0587622000, 0.1076698000, 0.2391887000, 0.5889061000, 1.5021628000", \ - "0.0319204000, 0.0398965000, 0.0587497000, 0.1076128000, 0.2390865000, 0.5902114000, 1.5046199000", \ - "0.0318801000, 0.0398745000, 0.0587435000, 0.1075422000, 0.2387281000, 0.5910756000, 1.5004215000", \ - "0.0321136000, 0.0397163000, 0.0588624000, 0.1074867000, 0.2390381000, 0.5895878000, 1.5032223000", \ - "0.0336163000, 0.0411291000, 0.0599112000, 0.1085053000, 0.2393772000, 0.5887429000, 1.5041209000", \ - "0.0387643000, 0.0463653000, 0.0643007000, 0.1114361000, 0.2407946000, 0.5887190000, 1.5007389000", \ - "0.0507003000, 0.0585287000, 0.0768648000, 0.1194068000, 0.2436460000, 0.5916775000, 1.4979735000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1683677000, 0.1761787000, 0.1927804000, 0.2268565000, 0.2899373000, 0.4179098000, 0.7200646000", \ - "0.1722216000, 0.1801281000, 0.1969398000, 0.2304039000, 0.2938367000, 0.4218158000, 0.7240263000", \ - "0.1829955000, 0.1908379000, 0.2076224000, 0.2410293000, 0.3045127000, 0.4324227000, 0.7341565000", \ - "0.2102958000, 0.2181737000, 0.2348875000, 0.2684894000, 0.3318789000, 0.4598963000, 0.7617872000", \ - "0.2780360000, 0.2857954000, 0.3025291000, 0.3360135000, 0.3995289000, 0.5276355000, 0.8297458000", \ - "0.4150367000, 0.4241111000, 0.4430519000, 0.4798039000, 0.5469675000, 0.6768941000, 0.9795172000", \ - "0.6326610000, 0.6444452000, 0.6687225000, 0.7143894000, 0.7937738000, 0.9331973000, 1.2396699000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1282896000, 0.1368898000, 0.1556394000, 0.1966336000, 0.2933022000, 0.5394579000, 1.1815670000", \ - "0.1328585000, 0.1414519000, 0.1602035000, 0.2012133000, 0.2978972000, 0.5437961000, 1.1857415000", \ - "0.1422392000, 0.1508812000, 0.1696811000, 0.2107078000, 0.3074350000, 0.5546039000, 1.1934866000", \ - "0.1623847000, 0.1709292000, 0.1897856000, 0.2308485000, 0.3277106000, 0.5749813000, 1.2141169000", \ - "0.2030397000, 0.2119862000, 0.2313195000, 0.2729978000, 0.3700875000, 0.6177372000, 1.2568592000", \ - "0.2614813000, 0.2713967000, 0.2920999000, 0.3355667000, 0.4339923000, 0.6816114000, 1.3208042000", \ - "0.3177422000, 0.3303675000, 0.3555253000, 0.4030495000, 0.5033045000, 0.7518137000, 1.3909408000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0312271000, 0.0370777000, 0.0504829000, 0.0779284000, 0.1354417000, 0.2745008000, 0.6640182000", \ - "0.0313225000, 0.0369300000, 0.0503203000, 0.0785350000, 0.1353472000, 0.2744705000, 0.6629157000", \ - "0.0316228000, 0.0369752000, 0.0502600000, 0.0781893000, 0.1354024000, 0.2740804000, 0.6601717000", \ - "0.0311616000, 0.0372585000, 0.0502628000, 0.0782850000, 0.1353053000, 0.2738605000, 0.6604596000", \ - "0.0313158000, 0.0374694000, 0.0504593000, 0.0785291000, 0.1354592000, 0.2743958000, 0.6604055000", \ - "0.0406157000, 0.0459744000, 0.0591189000, 0.0862969000, 0.1415481000, 0.2770325000, 0.6648383000", \ - "0.0569137000, 0.0649118000, 0.0797125000, 0.1111416000, 0.1657567000, 0.2929448000, 0.6656558000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0323414000, 0.0404194000, 0.0594131000, 0.1079217000, 0.2385815000, 0.5908446000, 1.5009675000", \ - "0.0323423000, 0.0404312000, 0.0593451000, 0.1080446000, 0.2388070000, 0.5903845000, 1.5025118000", \ - "0.0324787000, 0.0404210000, 0.0595672000, 0.1081284000, 0.2391448000, 0.5897674000, 1.5031758000", \ - "0.0325516000, 0.0402523000, 0.0595018000, 0.1080947000, 0.2392571000, 0.5894505000, 1.5018193000", \ - "0.0343856000, 0.0423799000, 0.0612182000, 0.1093259000, 0.2394901000, 0.5902315000, 1.5018539000", \ - "0.0402081000, 0.0475238000, 0.0661920000, 0.1128646000, 0.2411590000, 0.5895654000, 1.5041848000", \ - "0.0534923000, 0.0616032000, 0.0803225000, 0.1227066000, 0.2449933000, 0.5921952000, 1.4975711000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0808450000, 0.0868613000, 0.1002365000, 0.1280713000, 0.1826674000, 0.3023801000, 0.6019281000", \ - "0.0861717000, 0.0921955000, 0.1055750000, 0.1334015000, 0.1879946000, 0.3076975000, 0.6068056000", \ - "0.0992612000, 0.1052819000, 0.1186234000, 0.1465040000, 0.2011525000, 0.3208771000, 0.6203900000", \ - "0.1304551000, 0.1364183000, 0.1497733000, 0.1777985000, 0.2325868000, 0.3524085000, 0.6521370000", \ - "0.1925025000, 0.1993347000, 0.2140682000, 0.2441361000, 0.3005396000, 0.4207849000, 0.7205003000", \ - "0.2896456000, 0.2984060000, 0.3171516000, 0.3544861000, 0.4194076000, 0.5448857000, 0.8448128000", \ - "0.4425027000, 0.4537789000, 0.4779105000, 0.5255842000, 0.6092351000, 0.7474067000, 1.0497856000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.1222732000, 0.1307630000, 0.1492248000, 0.1898328000, 0.2867042000, 0.5337688000, 1.1766449000", \ - "0.1261690000, 0.1345077000, 0.1530314000, 0.1937620000, 0.2903377000, 0.5379178000, 1.1772816000", \ - "0.1356143000, 0.1440957000, 0.1625520000, 0.2032333000, 0.3001911000, 0.5472862000, 1.1901761000", \ - "0.1582681000, 0.1666709000, 0.1852254000, 0.2260571000, 0.3227212000, 0.5704187000, 1.2093611000", \ - "0.2039936000, 0.2125239000, 0.2314560000, 0.2726541000, 0.3696141000, 0.6168093000, 1.2568023000", \ - "0.2670677000, 0.2761896000, 0.2959090000, 0.3379629000, 0.4358444000, 0.6841176000, 1.3244461000", \ - "0.3290591000, 0.3402710000, 0.3637687000, 0.4078496000, 0.5065882000, 0.7548343000, 1.3950148000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0205949000, 0.0257864000, 0.0381808000, 0.0638264000, 0.1189226000, 0.2612772000, 0.6579451000", \ - "0.0207003000, 0.0257703000, 0.0381169000, 0.0638557000, 0.1185070000, 0.2618243000, 0.6540283000", \ - "0.0206981000, 0.0258386000, 0.0382489000, 0.0637704000, 0.1188817000, 0.2613930000, 0.6575860000", \ - "0.0209007000, 0.0261508000, 0.0385371000, 0.0641744000, 0.1190351000, 0.2616869000, 0.6581118000", \ - "0.0261949000, 0.0312472000, 0.0433911000, 0.0685132000, 0.1208346000, 0.2627913000, 0.6576962000", \ - "0.0361705000, 0.0427839000, 0.0570347000, 0.0850105000, 0.1369480000, 0.2691424000, 0.6573872000", \ - "0.0512425000, 0.0588868000, 0.0770606000, 0.1139213000, 0.1691397000, 0.2891138000, 0.6553650000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012978100, 0.0033686200, 0.0087436600, 0.0226952000, 0.0589081000, 0.1529030000"); - values("0.0319698000, 0.0398459000, 0.0588559000, 0.1074848000, 0.2386552000, 0.5911447000, 1.5002801000", \ - "0.0321747000, 0.0398800000, 0.0588841000, 0.1075075000, 0.2387812000, 0.5892398000, 1.5027211000", \ - "0.0319908000, 0.0398886000, 0.0587087000, 0.1075113000, 0.2386680000, 0.5911467000, 1.5000419000", \ - "0.0320413000, 0.0396807000, 0.0587710000, 0.1074778000, 0.2391453000, 0.5896060000, 1.5013932000", \ - "0.0330914000, 0.0408500000, 0.0597867000, 0.1083703000, 0.2392318000, 0.5907711000, 1.4974048000", \ - "0.0378876000, 0.0456318000, 0.0632402000, 0.1106569000, 0.2411442000, 0.5893179000, 1.5048692000", \ - "0.0501213000, 0.0574001000, 0.0740849000, 0.1174110000, 0.2427932000, 0.5909403000, 1.5001748000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221a_2") { - leakage_power () { - value : 0.0050991000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0160364000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0034899000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0029880000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0034935000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0029889000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0034983000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0029878000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0034718000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0029841000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0035029000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0033635000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029589000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0034718000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0029841000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0033321000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0032830000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0031928000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0027882000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0034718000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0029841000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0029904000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0028511000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0024465000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0032831000; - when : "A1&A2&B1&B2&!C1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o221a"; - cell_leakage_power : 0.0036538670; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041836000, 0.0041855000, 0.0041898000, 0.0041904000, 0.0041917000, 0.0041949000, 0.0042022000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004184900, -0.004184600, -0.004183700, -0.004184700, -0.004186800, -0.004191800, -0.004203200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025020000; - } - pin ("A2") { - capacitance : 0.0023810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040164000, 0.0040174000, 0.0040196000, 0.0040199000, 0.0040206000, 0.0040223000, 0.0040261000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004007700, -0.004008000, -0.004008700, -0.004009400, -0.004011200, -0.004015300, -0.004024800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025470000; - } - pin ("B1") { - capacitance : 0.0023330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040027000, 0.0040079000, 0.0040197000, 0.0040225000, 0.0040289000, 0.0040437000, 0.0040779000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004007500, -0.004006400, -0.004003900, -0.004002900, -0.004000600, -0.003995300, -0.003983200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("B2") { - capacitance : 0.0023400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040200000, 0.0040182000, 0.0040141000, 0.0040187000, 0.0040291000, 0.0040532000, 0.0041088000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004013700, -0.004013700, -0.004013800, -0.004014000, -0.004014400, -0.004015400, -0.004017700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024690000; - } - pin ("C1") { - capacitance : 0.0023120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022530000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047518000, 0.0047531000, 0.0047562000, 0.0047562000, 0.0047563000, 0.0047564000, 0.0047568000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002594000, -0.002598900, -0.002610300, -0.002599300, -0.002574100, -0.002515900, -0.002381900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023710000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A1&B2&C1) | (A2&B2&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0224227000, 0.0208523000, 0.0172393000, 0.0067191000, -0.027205100, -0.129642700, -0.426208500", \ - "0.0221860000, 0.0207078000, 0.0170980000, 0.0065879000, -0.027335100, -0.129749500, -0.426285300", \ - "0.0219638000, 0.0205212000, 0.0169444000, 0.0064101000, -0.027493800, -0.129904700, -0.426435300", \ - "0.0219337000, 0.0205083000, 0.0168470000, 0.0062830000, -0.027671200, -0.130103300, -0.426642500", \ - "0.0216218000, 0.0201362000, 0.0165652000, 0.0059842000, -0.027906700, -0.130297000, -0.426765400", \ - "0.0215730000, 0.0200924000, 0.0163985000, 0.0058225000, -0.027965500, -0.130297600, -0.426781800", \ - "0.0269669000, 0.0252892000, 0.0207354000, 0.0080823000, -0.027533600, -0.130234800, -0.426658200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0223715000, 0.0240051000, 0.0286296000, 0.0414067000, 0.0771814000, 0.1790750000, 0.4721855000", \ - "0.0222477000, 0.0238883000, 0.0284304000, 0.0413110000, 0.0770790000, 0.1791588000, 0.4719920000", \ - "0.0220928000, 0.0237081000, 0.0283465000, 0.0412467000, 0.0770476000, 0.1790035000, 0.4723565000", \ - "0.0219512000, 0.0236107000, 0.0281981000, 0.0410632000, 0.0768410000, 0.1788823000, 0.4742176000", \ - "0.0218468000, 0.0234220000, 0.0280212000, 0.0408893000, 0.0767394000, 0.1788360000, 0.4740708000", \ - "0.0224208000, 0.0239920000, 0.0283857000, 0.0407587000, 0.0765504000, 0.1782532000, 0.4720473000", \ - "0.0229654000, 0.0244463000, 0.0287857000, 0.0412590000, 0.0770319000, 0.1792344000, 0.4709146000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0202710000, 0.0188042000, 0.0152321000, 0.0046696000, -0.029198300, -0.131421200, -0.427845900", \ - "0.0201392000, 0.0186807000, 0.0150323000, 0.0045439000, -0.029278200, -0.131490600, -0.428042700", \ - "0.0199465000, 0.0184922000, 0.0149010000, 0.0043854000, -0.029518300, -0.131757500, -0.428193100", \ - "0.0198478000, 0.0183881000, 0.0147405000, 0.0042537000, -0.029658800, -0.131983900, -0.428421800", \ - "0.0195180000, 0.0180441000, 0.0143975000, 0.0040400000, -0.029798900, -0.132087100, -0.428501900", \ - "0.0198248000, 0.0183175000, 0.0145459000, 0.0042558000, -0.029677000, -0.131945000, -0.428295700", \ - "0.0258057000, 0.0240511000, 0.0194197000, 0.0068181000, -0.029314000, -0.131502300, -0.427846700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0209108000, 0.0225477000, 0.0271484000, 0.0401493000, 0.0762100000, 0.1788000000, 0.4721398000", \ - "0.0209291000, 0.0225799000, 0.0272407000, 0.0401381000, 0.0762546000, 0.1788206000, 0.4744314000", \ - "0.0208430000, 0.0224720000, 0.0270884000, 0.0401521000, 0.0761319000, 0.1788286000, 0.4722466000", \ - "0.0205887000, 0.0222281000, 0.0268652000, 0.0398721000, 0.0759636000, 0.1785063000, 0.4725240000", \ - "0.0204060000, 0.0219988000, 0.0265264000, 0.0394608000, 0.0755697000, 0.1781676000, 0.4718781000", \ - "0.0210074000, 0.0225320000, 0.0269691000, 0.0392249000, 0.0753260000, 0.1774253000, 0.4736567000", \ - "0.0212148000, 0.0227029000, 0.0270843000, 0.0397415000, 0.0754420000, 0.1780726000, 0.4705716000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0175277000, 0.0163575000, 0.0130928000, 0.0032350000, -0.029788800, -0.131888500, -0.428388700", \ - "0.0174251000, 0.0160948000, 0.0128831000, 0.0030433000, -0.029979900, -0.132000700, -0.428485800", \ - "0.0173776000, 0.0159574000, 0.0127354000, 0.0029328000, -0.030142700, -0.132196800, -0.428675500", \ - "0.0169661000, 0.0156375000, 0.0124757000, 0.0025970000, -0.030459600, -0.132467500, -0.428962100", \ - "0.0166911000, 0.0153517000, 0.0121889000, 0.0022576000, -0.030819900, -0.132777300, -0.429223900", \ - "0.0164551000, 0.0151267000, 0.0118604000, 0.0020051000, -0.031122000, -0.133042200, -0.429414500", \ - "0.0234716000, 0.0217989000, 0.0173183000, 0.0047154000, -0.030521100, -0.133114000, -0.429361700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0221660000, 0.0237878000, 0.0283730000, 0.0413090000, 0.0770670000, 0.1794176000, 0.4727709000", \ - "0.0221476000, 0.0237704000, 0.0283885000, 0.0411586000, 0.0770424000, 0.1791295000, 0.4746517000", \ - "0.0220123000, 0.0236452000, 0.0282758000, 0.0410616000, 0.0768715000, 0.1789833000, 0.4722501000", \ - "0.0218177000, 0.0234402000, 0.0280336000, 0.0409141000, 0.0767728000, 0.1789736000, 0.4725757000", \ - "0.0218119000, 0.0233771000, 0.0279916000, 0.0407876000, 0.0766191000, 0.1788935000, 0.4744921000", \ - "0.0223692000, 0.0238777000, 0.0282058000, 0.0404284000, 0.0763347000, 0.1785320000, 0.4725241000", \ - "0.0231549000, 0.0246517000, 0.0288838000, 0.0413772000, 0.0770788000, 0.1796668000, 0.4730840000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0155363000, 0.0140310000, 0.0107960000, 0.0010579000, -0.032089000, -0.134057000, -0.430577900", \ - "0.0152300000, 0.0139032000, 0.0107459000, 0.0008349000, -0.032210000, -0.134219600, -0.430694700", \ - "0.0150671000, 0.0137368000, 0.0105381000, 0.0006680000, -0.032374600, -0.134391500, -0.430876500", \ - "0.0147994000, 0.0135258000, 0.0103239000, 0.0004552000, -0.032653500, -0.134664300, -0.431124400", \ - "0.0147208000, 0.0133824000, 0.0101201000, 0.0001669000, -0.032943300, -0.134921500, -0.431327900", \ - "0.0148555000, 0.0134327000, 0.0100142000, 2.170000e-05, -0.033159800, -0.135086600, -0.431410700", \ - "0.0223444000, 0.0206247000, 0.0159749000, 0.0032733000, -0.032591300, -0.134658200, -0.430859700"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0208615000, 0.0224843000, 0.0270507000, 0.0400062000, 0.0757779000, 0.1779532000, 0.4708705000", \ - "0.0208337000, 0.0224600000, 0.0271026000, 0.0399614000, 0.0757455000, 0.1779748000, 0.4716455000", \ - "0.0208012000, 0.0224125000, 0.0270402000, 0.0398630000, 0.0757322000, 0.1779829000, 0.4716622000", \ - "0.0205251000, 0.0221508000, 0.0267849000, 0.0397011000, 0.0754680000, 0.1777866000, 0.4709738000", \ - "0.0203123000, 0.0218810000, 0.0264919000, 0.0393289000, 0.0751787000, 0.1772910000, 0.4731010000", \ - "0.0208344000, 0.0223426000, 0.0267467000, 0.0390488000, 0.0746654000, 0.1768774000, 0.4703000000", \ - "0.0215520000, 0.0229965000, 0.0272524000, 0.0397310000, 0.0755080000, 0.1776880000, 0.4710246000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0134561000, 0.0125814000, 0.0101300000, 0.0005059000, -0.033470400, -0.136338700, -0.433097200", \ - "0.0133725000, 0.0124176000, 0.0100231000, 0.0003706000, -0.033540000, -0.136424700, -0.433185500", \ - "0.0131164000, 0.0122159000, 0.0097702000, 0.0001033000, -0.033820200, -0.136690900, -0.433449300", \ - "0.0129175000, 0.0119803000, 0.0094375000, -0.000274600, -0.034196000, -0.136968300, -0.433696100", \ - "0.0127406000, 0.0116536000, 0.0089016000, -0.000728500, -0.034513100, -0.137155700, -0.433790300", \ - "0.0172167000, 0.0157019000, 0.0113972000, -0.000938100, -0.034513200, -0.136982300, -0.433518800", \ - "0.0208266000, 0.0191734000, 0.0146547000, 0.0021396000, -0.033495200, -0.136062400, -0.432393500"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014364120, 0.0041265620, 0.0118548900, 0.0340570200, 0.0978398700, 0.2810768000"); - values("0.0208553000, 0.0224679000, 0.0270715000, 0.0399470000, 0.0757780000, 0.1779977000, 0.4736305000", \ - "0.0207018000, 0.0223024000, 0.0269825000, 0.0398344000, 0.0757183000, 0.1779982000, 0.4715956000", \ - "0.0206048000, 0.0221765000, 0.0268102000, 0.0397456000, 0.0755232000, 0.1777270000, 0.4711962000", \ - "0.0203135000, 0.0219386000, 0.0265658000, 0.0394855000, 0.0753303000, 0.1776725000, 0.4733225000", \ - "0.0202441000, 0.0218035000, 0.0264025000, 0.0391370000, 0.0750101000, 0.1775035000, 0.4708548000", \ - "0.0209495000, 0.0224570000, 0.0268473000, 0.0390970000, 0.0748206000, 0.1771976000, 0.4713600000", \ - "0.0223783000, 0.0238381000, 0.0282807000, 0.0407053000, 0.0763331000, 0.1786383000, 0.4718650000"); - } - } - max_capacitance : 0.2810770000; - max_transition : 1.5027830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.2479300000, 0.2547791000, 0.2700935000, 0.2994344000, 0.3551064000, 0.4710395000, 0.7671129000", \ - "0.2531462000, 0.2601304000, 0.2752578000, 0.3047227000, 0.3605066000, 0.4763214000, 0.7724739000", \ - "0.2660491000, 0.2729861000, 0.2881859000, 0.3175637000, 0.3733831000, 0.4892325000, 0.7855002000", \ - "0.2934205000, 0.3004826000, 0.3156959000, 0.3451593000, 0.4007047000, 0.5171076000, 0.8133037000", \ - "0.3565371000, 0.3633734000, 0.3785470000, 0.4078742000, 0.4636594000, 0.5806586000, 0.8770653000", \ - "0.4961860000, 0.5034764000, 0.5192573000, 0.5493310000, 0.6054631000, 0.7243282000, 1.0207772000", \ - "0.7516818000, 0.7604062000, 0.7791304000, 0.8140523000, 0.8762931000, 1.0015428000, 1.3004340000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1529854000, 0.1601745000, 0.1766109000, 0.2131126000, 0.2995836000, 0.5344957000, 1.2069955000", \ - "0.1573230000, 0.1645534000, 0.1809575000, 0.2175139000, 0.3038980000, 0.5392758000, 1.2126999000", \ - "0.1661582000, 0.1732784000, 0.1898437000, 0.2262783000, 0.3129607000, 0.5488228000, 1.2211431000", \ - "0.1833611000, 0.1905189000, 0.2070107000, 0.2435430000, 0.3300815000, 0.5657069000, 1.2403831000", \ - "0.2176821000, 0.2249904000, 0.2417413000, 0.2784378000, 0.3653600000, 0.6015394000, 1.2771910000", \ - "0.2728678000, 0.2808950000, 0.2991431000, 0.3379019000, 0.4265204000, 0.6627884000, 1.3367722000", \ - "0.3345584000, 0.3445688000, 0.3666838000, 0.4101910000, 0.5026343000, 0.7393761000, 1.4130704000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0346998000, 0.0386219000, 0.0481356000, 0.0675337000, 0.1130086000, 0.2378128000, 0.6146246000", \ - "0.0348295000, 0.0389814000, 0.0475188000, 0.0667016000, 0.1127574000, 0.2375280000, 0.6142062000", \ - "0.0346037000, 0.0389152000, 0.0478430000, 0.0666635000, 0.1127601000, 0.2375698000, 0.6150903000", \ - "0.0348815000, 0.0386710000, 0.0474187000, 0.0672031000, 0.1127403000, 0.2376589000, 0.6143948000", \ - "0.0347510000, 0.0385973000, 0.0475592000, 0.0676591000, 0.1129146000, 0.2361213000, 0.6159505000", \ - "0.0379846000, 0.0414585000, 0.0503977000, 0.0690024000, 0.1148025000, 0.2382358000, 0.6177853000", \ - "0.0486465000, 0.0527088000, 0.0623334000, 0.0823118000, 0.1290557000, 0.2477476000, 0.6171309000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0282472000, 0.0342699000, 0.0487658000, 0.0873426000, 0.1981902000, 0.5318311000, 1.4975340000", \ - "0.0284568000, 0.0343521000, 0.0490726000, 0.0873405000, 0.1985641000, 0.5323296000, 1.4980704000", \ - "0.0283532000, 0.0343246000, 0.0488717000, 0.0872703000, 0.1984655000, 0.5323548000, 1.4984054000", \ - "0.0283266000, 0.0341037000, 0.0489251000, 0.0872747000, 0.1985029000, 0.5329818000, 1.5026907000", \ - "0.0292441000, 0.0351557000, 0.0496304000, 0.0878531000, 0.1987544000, 0.5327688000, 1.4996794000", \ - "0.0332646000, 0.0396226000, 0.0543322000, 0.0920302000, 0.2010005000, 0.5321764000, 1.5003037000", \ - "0.0433462000, 0.0502761000, 0.0658057000, 0.1026164000, 0.2071001000, 0.5338516000, 1.4976375000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.2329734000, 0.2399616000, 0.2550402000, 0.2844209000, 0.3402453000, 0.4566373000, 0.7531650000", \ - "0.2367818000, 0.2438109000, 0.2588935000, 0.2882649000, 0.3439599000, 0.4604288000, 0.7568104000", \ - "0.2473594000, 0.2543969000, 0.2694517000, 0.2988400000, 0.3546675000, 0.4713690000, 0.7678160000", \ - "0.2745865000, 0.2815230000, 0.2966628000, 0.3258394000, 0.3816473000, 0.4979509000, 0.7942232000", \ - "0.3432708000, 0.3502191000, 0.3653929000, 0.3939711000, 0.4495736000, 0.5668118000, 0.8633905000", \ - "0.5002107000, 0.5077463000, 0.5236716000, 0.5536444000, 0.6100758000, 0.7270546000, 1.0234771000", \ - "0.7706468000, 0.7798514000, 0.8010003000, 0.8396237000, 0.9049078000, 1.0284948000, 1.3275774000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1453370000, 0.1525692000, 0.1692858000, 0.2063098000, 0.2936511000, 0.5296992000, 1.2038960000", \ - "0.1503209000, 0.1575734000, 0.1743369000, 0.2112191000, 0.2986814000, 0.5350523000, 1.2103587000", \ - "0.1597705000, 0.1670069000, 0.1837369000, 0.2207631000, 0.3081162000, 0.5444135000, 1.2189132000", \ - "0.1776444000, 0.1848871000, 0.2016149000, 0.2386087000, 0.3260524000, 0.5630434000, 1.2366466000", \ - "0.2133488000, 0.2208462000, 0.2377574000, 0.2750420000, 0.3626295000, 0.5995950000, 1.2727884000", \ - "0.2700010000, 0.2783620000, 0.2970205000, 0.3365140000, 0.4257726000, 0.6626669000, 1.3367847000", \ - "0.3336809000, 0.3441861000, 0.3673116000, 0.4125917000, 0.5059135000, 0.7436846000, 1.4174378000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0348331000, 0.0389293000, 0.0475215000, 0.0665778000, 0.1128259000, 0.2367059000, 0.6155974000", \ - "0.0349836000, 0.0387827000, 0.0474244000, 0.0676007000, 0.1120839000, 0.2372740000, 0.6138935000", \ - "0.0347022000, 0.0389363000, 0.0475398000, 0.0675774000, 0.1129360000, 0.2369185000, 0.6144151000", \ - "0.0346998000, 0.0388976000, 0.0473980000, 0.0671125000, 0.1128957000, 0.2375936000, 0.6143396000", \ - "0.0349729000, 0.0385580000, 0.0473251000, 0.0666805000, 0.1132121000, 0.2366125000, 0.6166733000", \ - "0.0391102000, 0.0428720000, 0.0511433000, 0.0693256000, 0.1142117000, 0.2383129000, 0.6144988000", \ - "0.0569081000, 0.0617365000, 0.0725820000, 0.0909837000, 0.1316618000, 0.2484815000, 0.6188844000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0285754000, 0.0343850000, 0.0493123000, 0.0875351000, 0.1979788000, 0.5318953000, 1.4979925000", \ - "0.0285218000, 0.0343658000, 0.0491336000, 0.0874398000, 0.1984536000, 0.5326199000, 1.5016995000", \ - "0.0286905000, 0.0345247000, 0.0491011000, 0.0874900000, 0.1980897000, 0.5320371000, 1.4989509000", \ - "0.0284766000, 0.0343864000, 0.0490396000, 0.0872908000, 0.1982697000, 0.5310442000, 1.5011419000", \ - "0.0296185000, 0.0354929000, 0.0500765000, 0.0881029000, 0.1983175000, 0.5321759000, 1.4979877000", \ - "0.0341530000, 0.0402563000, 0.0555200000, 0.0931465000, 0.2013996000, 0.5316524000, 1.5000807000", \ - "0.0459148000, 0.0526539000, 0.0688321000, 0.1052995000, 0.2082730000, 0.5329411000, 1.4936531000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.2084661000, 0.2151866000, 0.2304115000, 0.2614403000, 0.3227759000, 0.4459808000, 0.7448824000", \ - "0.2140029000, 0.2207707000, 0.2359423000, 0.2669193000, 0.3286385000, 0.4512719000, 0.7502397000", \ - "0.2264602000, 0.2332580000, 0.2484179000, 0.2794293000, 0.3407978000, 0.4639889000, 0.7628110000", \ - "0.2532672000, 0.2600239000, 0.2752033000, 0.3062227000, 0.3675827000, 0.4911711000, 0.7899406000", \ - "0.3150037000, 0.3217947000, 0.3369895000, 0.3679572000, 0.4296009000, 0.5532269000, 0.8520666000", \ - "0.4465403000, 0.4538866000, 0.4700479000, 0.5028307000, 0.5664362000, 0.6905350000, 0.9895977000", \ - "0.6758758000, 0.6843318000, 0.7039763000, 0.7421321000, 0.8135548000, 0.9493951000, 1.2537459000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1449314000, 0.1520658000, 0.1686105000, 0.2051211000, 0.2917937000, 0.5275133000, 1.2017958000", \ - "0.1492484000, 0.1563960000, 0.1729445000, 0.2093500000, 0.2960447000, 0.5318285000, 1.2063843000", \ - "0.1586916000, 0.1658584000, 0.1823271000, 0.2188250000, 0.3053971000, 0.5407276000, 1.2138909000", \ - "0.1796305000, 0.1867930000, 0.2032962000, 0.2397707000, 0.3265872000, 0.5629778000, 1.2356119000", \ - "0.2249656000, 0.2322775000, 0.2489927000, 0.2857112000, 0.3725623000, 0.6084858000, 1.2828165000", \ - "0.2953630000, 0.3036199000, 0.3219521000, 0.3607026000, 0.4491455000, 0.6856603000, 1.3598916000", \ - "0.3708114000, 0.3812727000, 0.4040235000, 0.4478941000, 0.5396701000, 0.7763973000, 1.4504028000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0318680000, 0.0365598000, 0.0462985000, 0.0697248000, 0.1210914000, 0.2450541000, 0.6180946000", \ - "0.0319103000, 0.0361069000, 0.0462586000, 0.0700224000, 0.1210356000, 0.2444814000, 0.6182677000", \ - "0.0318892000, 0.0361175000, 0.0463153000, 0.0698320000, 0.1211922000, 0.2442016000, 0.6171220000", \ - "0.0319307000, 0.0361400000, 0.0465159000, 0.0697948000, 0.1211225000, 0.2445893000, 0.6165828000", \ - "0.0320529000, 0.0362246000, 0.0462322000, 0.0696919000, 0.1210183000, 0.2445068000, 0.6165719000", \ - "0.0366115000, 0.0412574000, 0.0514284000, 0.0746597000, 0.1247431000, 0.2461456000, 0.6167068000", \ - "0.0482737000, 0.0535655000, 0.0647274000, 0.0900089000, 0.1444768000, 0.2630052000, 0.6208921000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0283889000, 0.0342986000, 0.0489216000, 0.0871691000, 0.1983775000, 0.5323777000, 1.5006858000", \ - "0.0282951000, 0.0341333000, 0.0489606000, 0.0872432000, 0.1985712000, 0.5317946000, 1.5016236000", \ - "0.0284153000, 0.0342409000, 0.0488275000, 0.0872899000, 0.1981241000, 0.5319537000, 1.4968654000", \ - "0.0285828000, 0.0343699000, 0.0488450000, 0.0872401000, 0.1983808000, 0.5322731000, 1.4992920000", \ - "0.0296711000, 0.0351385000, 0.0497011000, 0.0877233000, 0.1986614000, 0.5322008000, 1.5015522000", \ - "0.0348562000, 0.0408068000, 0.0556897000, 0.0923436000, 0.2011529000, 0.5325336000, 1.5008484000", \ - "0.0471297000, 0.0537712000, 0.0682711000, 0.1042702000, 0.2060813000, 0.5344826000, 1.4978554000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1932596000, 0.2001035000, 0.2152379000, 0.2462481000, 0.3076160000, 0.4307938000, 0.7295438000", \ - "0.1973551000, 0.2041377000, 0.2193539000, 0.2502999000, 0.3119974000, 0.4351035000, 0.7341055000", \ - "0.2080450000, 0.2148260000, 0.2299705000, 0.2610060000, 0.3227560000, 0.4455126000, 0.7444597000", \ - "0.2355532000, 0.2423343000, 0.2574481000, 0.2886320000, 0.3497844000, 0.4732923000, 0.7722862000", \ - "0.3032053000, 0.3099180000, 0.3250842000, 0.3553899000, 0.4177029000, 0.5411884000, 0.8402122000", \ - "0.4506491000, 0.4582864000, 0.4750558000, 0.5080752000, 0.5722993000, 0.6971903000, 0.9961314000", \ - "0.6896877000, 0.6995016000, 0.7213480000, 0.7635937000, 0.8409413000, 0.9780675000, 1.2824630000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1396960000, 0.1470146000, 0.1638782000, 0.2011244000, 0.2883219000, 0.5237666000, 1.1971232000", \ - "0.1442710000, 0.1516372000, 0.1686148000, 0.2057218000, 0.2929676000, 0.5291854000, 1.2030447000", \ - "0.1538979000, 0.1611923000, 0.1782069000, 0.2152534000, 0.3026722000, 0.5389443000, 1.2121069000", \ - "0.1741828000, 0.1815443000, 0.1984746000, 0.2356856000, 0.3228891000, 0.5587630000, 1.2326802000", \ - "0.2172632000, 0.2248683000, 0.2421333000, 0.2797464000, 0.3673407000, 0.6031592000, 1.2769794000", \ - "0.2837754000, 0.2923822000, 0.3112433000, 0.3510303000, 0.4405843000, 0.6776347000, 1.3516842000", \ - "0.3542208000, 0.3651147000, 0.3888060000, 0.4343530000, 0.5277439000, 0.7652251000, 1.4387347000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0319943000, 0.0362227000, 0.0462178000, 0.0699130000, 0.1212501000, 0.2445826000, 0.6165717000", \ - "0.0319290000, 0.0362516000, 0.0464466000, 0.0700856000, 0.1208401000, 0.2440183000, 0.6178882000", \ - "0.0319102000, 0.0362066000, 0.0466096000, 0.0699886000, 0.1208672000, 0.2449602000, 0.6156665000", \ - "0.0318126000, 0.0362498000, 0.0462116000, 0.0697163000, 0.1209497000, 0.2441940000, 0.6182883000", \ - "0.0318057000, 0.0360420000, 0.0466082000, 0.0697910000, 0.1208008000, 0.2440917000, 0.6181475000", \ - "0.0394958000, 0.0444827000, 0.0537181000, 0.0764635000, 0.1256045000, 0.2468380000, 0.6163260000", \ - "0.0578782000, 0.0638609000, 0.0766227000, 0.1013070000, 0.1519399000, 0.2664060000, 0.6226696000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0292274000, 0.0351661000, 0.0500501000, 0.0885246000, 0.1989539000, 0.5322746000, 1.4973009000", \ - "0.0292648000, 0.0352171000, 0.0498792000, 0.0883275000, 0.1993770000, 0.5318646000, 1.5012344000", \ - "0.0290454000, 0.0348850000, 0.0499420000, 0.0884405000, 0.1992485000, 0.5319362000, 1.5014732000", \ - "0.0291089000, 0.0350610000, 0.0498336000, 0.0885174000, 0.1992728000, 0.5323618000, 1.4987900000", \ - "0.0306579000, 0.0363538000, 0.0509565000, 0.0892442000, 0.1995625000, 0.5309174000, 1.5011891000", \ - "0.0363713000, 0.0424996000, 0.0574217000, 0.0943039000, 0.2025998000, 0.5327642000, 1.4975380000", \ - "0.0494154000, 0.0562919000, 0.0712256000, 0.1077387000, 0.2090116000, 0.5334813000, 1.4937972000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0905421000, 0.0954068000, 0.1066056000, 0.1309260000, 0.1815962000, 0.2922805000, 0.5848953000", \ - "0.0958608000, 0.1006129000, 0.1117544000, 0.1362057000, 0.1868723000, 0.2975565000, 0.5903256000", \ - "0.1092139000, 0.1140435000, 0.1250772000, 0.1495471000, 0.2002422000, 0.3109571000, 0.6036346000", \ - "0.1405858000, 0.1453828000, 0.1564080000, 0.1808074000, 0.2316098000, 0.3423246000, 0.6349267000", \ - "0.2081652000, 0.2134539000, 0.2254555000, 0.2505631000, 0.3023407000, 0.4135600000, 0.7062984000", \ - "0.3174307000, 0.3242980000, 0.3396160000, 0.3711556000, 0.4321573000, 0.5491660000, 0.8426242000", \ - "0.4885850000, 0.4974665000, 0.5173101000, 0.5573998000, 0.6363111000, 0.7697025000, 1.0687080000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.1333823000, 0.1405056000, 0.1570338000, 0.1934664000, 0.2802688000, 0.5165507000, 1.1920074000", \ - "0.1370471000, 0.1441923000, 0.1607384000, 0.1971740000, 0.2840347000, 0.5206071000, 1.1937654000", \ - "0.1463495000, 0.1534499000, 0.1700090000, 0.2065799000, 0.2932712000, 0.5289504000, 1.2024268000", \ - "0.1688420000, 0.1760198000, 0.1926407000, 0.2291565000, 0.3159989000, 0.5522625000, 1.2278577000", \ - "0.2189263000, 0.2261972000, 0.2428399000, 0.2795916000, 0.3662906000, 0.6025720000, 1.2770975000", \ - "0.2899068000, 0.2980733000, 0.3160158000, 0.3542399000, 0.4421091000, 0.6793208000, 1.3534549000", \ - "0.3633621000, 0.3739352000, 0.3970826000, 0.4395457000, 0.5299582000, 0.7658872000, 1.4408097000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0183951000, 0.0220063000, 0.0309638000, 0.0528601000, 0.1001444000, 0.2250579000, 0.6116308000", \ - "0.0185417000, 0.0220645000, 0.0310230000, 0.0526580000, 0.1004084000, 0.2252904000, 0.6115853000", \ - "0.0185163000, 0.0220652000, 0.0309670000, 0.0528386000, 0.1003763000, 0.2248830000, 0.6115803000", \ - "0.0185223000, 0.0220710000, 0.0310136000, 0.0528065000, 0.1002613000, 0.2251576000, 0.6079141000", \ - "0.0225889000, 0.0261460000, 0.0344991000, 0.0554576000, 0.1021183000, 0.2256365000, 0.6116186000", \ - "0.0330621000, 0.0370436000, 0.0475924000, 0.0708158000, 0.1176479000, 0.2333631000, 0.6117267000", \ - "0.0487079000, 0.0540115000, 0.0666599000, 0.0957571000, 0.1509315000, 0.2590147000, 0.6130775000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014364100, 0.0041265600, 0.0118549000, 0.0340570000, 0.0978399000, 0.2810770000"); - values("0.0286152000, 0.0344308000, 0.0489635000, 0.0872391000, 0.1983688000, 0.5325537000, 1.5024346000", \ - "0.0286164000, 0.0343539000, 0.0488441000, 0.0872470000, 0.1984381000, 0.5322602000, 1.4983041000", \ - "0.0284231000, 0.0344437000, 0.0488975000, 0.0873012000, 0.1981592000, 0.5317305000, 1.4967806000", \ - "0.0283716000, 0.0341168000, 0.0489566000, 0.0871241000, 0.1985119000, 0.5331728000, 1.5027827000", \ - "0.0293429000, 0.0350291000, 0.0495629000, 0.0879991000, 0.1987486000, 0.5323489000, 1.4987528000", \ - "0.0358792000, 0.0412428000, 0.0554589000, 0.0918081000, 0.2012068000, 0.5316839000, 1.5017865000", \ - "0.0487254000, 0.0553252000, 0.0701620000, 0.1035436000, 0.2053860000, 0.5349822000, 1.4954920000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221a_4") { - leakage_power () { - value : 0.0420802000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0267047000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0051139000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0038426000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0051092000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0040363000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0050467000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0268305000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0050716000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0038347000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0063420000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0045016000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0060504000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0045017000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0055027000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0045016000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0050716000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0038347000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0060568000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0045015000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0057653000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0045018000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0056302000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0045016000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0050717000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0038148000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0055691000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0044817000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0052766000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0044817000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0047259000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0044697000; - when : "A1&A2&B1&B2&!C1"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__o221a"; - cell_leakage_power : 0.0074007920; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0048640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084025000, 0.0084029000, 0.0084039000, 0.0084054000, 0.0084087000, 0.0084165000, 0.0084343000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008416600, -0.008406100, -0.008381800, -0.008377200, -0.008366500, -0.008341700, -0.008284600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051400000; - } - pin ("A2") { - capacitance : 0.0043010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075374000, 0.0075337000, 0.0075253000, 0.0075260000, 0.0075276000, 0.0075313000, 0.0075399000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007512300, -0.007513000, -0.007514500, -0.007514300, -0.007513900, -0.007512900, -0.007510400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046000000; - } - pin ("B1") { - capacitance : 0.0047430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080839000, 0.0080918000, 0.0081100000, 0.0081117000, 0.0081156000, 0.0081245000, 0.0081451000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008124100, -0.008114500, -0.008092200, -0.008090200, -0.008085500, -0.008074800, -0.008049900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0049220000; - } - pin ("B2") { - capacitance : 0.0042740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075660000, 0.0075591000, 0.0075431000, 0.0075477000, 0.0075582000, 0.0075825000, 0.0076384000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007567800, -0.007566400, -0.007563200, -0.007560900, -0.007555500, -0.007543400, -0.007515100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045180000; - } - pin ("C1") { - capacitance : 0.0043050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089922000, 0.0089913000, 0.0089892000, 0.0089932000, 0.0090023000, 0.0090234000, 0.0090722000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004444000, -0.004452200, -0.004470900, -0.004446600, -0.004390600, -0.004261400, -0.003963400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044210000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A1&B2&C1) | (A2&B2&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0447872000, 0.0430985000, 0.0379007000, 0.0234003000, -0.026594600, -0.195708000, -0.734429100", \ - "0.0444340000, 0.0427536000, 0.0376217000, 0.0230899000, -0.026888400, -0.195954500, -0.734625000", \ - "0.0441151000, 0.0423394000, 0.0371654000, 0.0227295000, -0.026998300, -0.196163600, -0.735094500", \ - "0.0437424000, 0.0419835000, 0.0367940000, 0.0223150000, -0.027645000, -0.196738100, -0.735449000", \ - "0.0432487000, 0.0414405000, 0.0362765000, 0.0218229000, -0.028147100, -0.197183500, -0.735834800", \ - "0.0432350000, 0.0415391000, 0.0363027000, 0.0216364000, -0.028475100, -0.197260700, -0.735942800", \ - "0.0515092000, 0.0495618000, 0.0437295000, 0.0262359000, -0.028091700, -0.196886100, -0.735504200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0398328000, 0.0416796000, 0.0475192000, 0.0654147000, 0.1197149000, 0.2887943000, 0.8218226000", \ - "0.0396451000, 0.0414810000, 0.0471975000, 0.0651316000, 0.1194779000, 0.2885478000, 0.8223691000", \ - "0.0393601000, 0.0411335000, 0.0469222000, 0.0649407000, 0.1192262000, 0.2883678000, 0.8215471000", \ - "0.0389835000, 0.0408227000, 0.0466340000, 0.0645271000, 0.1188899000, 0.2880265000, 0.8214555000", \ - "0.0387649000, 0.0405388000, 0.0462745000, 0.0640821000, 0.1186477000, 0.2880490000, 0.8203150000", \ - "0.0394812000, 0.0412276000, 0.0468258000, 0.0637683000, 0.1183781000, 0.2871459000, 0.8211964000", \ - "0.0404994000, 0.0421950000, 0.0476513000, 0.0646337000, 0.1192595000, 0.2880250000, 0.8195723000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0405791000, 0.0393568000, 0.0336464000, 0.0191958000, -0.030772300, -0.199256000, -0.738038300", \ - "0.0404240000, 0.0387056000, 0.0336595000, 0.0190721000, -0.030822100, -0.199719400, -0.738194600", \ - "0.0399910000, 0.0381885000, 0.0331436000, 0.0185628000, -0.031346400, -0.199839600, -0.738380100", \ - "0.0396607000, 0.0378845000, 0.0327122000, 0.0182379000, -0.031666200, -0.200502600, -0.738979000", \ - "0.0391683000, 0.0373870000, 0.0322830000, 0.0177316000, -0.032133100, -0.200908100, -0.739301200", \ - "0.0409208000, 0.0391835000, 0.0337153000, 0.0188224000, -0.031537600, -0.200448300, -0.738962900", \ - "0.0507383000, 0.0486999000, 0.0426402000, 0.0247080000, -0.029656000, -0.199166900, -0.737704500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0359623000, 0.0377911000, 0.0435521000, 0.0616208000, 0.1163220000, 0.2856546000, 0.8194625000", \ - "0.0360420000, 0.0378830000, 0.0436394000, 0.0616455000, 0.1163825000, 0.2858155000, 0.8193831000", \ - "0.0359217000, 0.0377057000, 0.0434971000, 0.0616214000, 0.1161876000, 0.2856415000, 0.8194190000", \ - "0.0355278000, 0.0373102000, 0.0431669000, 0.0611837000, 0.1158668000, 0.2855275000, 0.8191388000", \ - "0.0351759000, 0.0370649000, 0.0427693000, 0.0606198000, 0.1153701000, 0.2850613000, 0.8187969000", \ - "0.0360174000, 0.0378133000, 0.0433657000, 0.0603531000, 0.1149406000, 0.2837669000, 0.8183669000", \ - "0.0367673000, 0.0384837000, 0.0439279000, 0.0609391000, 0.1156621000, 0.2848676000, 0.8160136000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0344520000, 0.0329294000, 0.0282836000, 0.0153997000, -0.032709900, -0.200706500, -0.739435800", \ - "0.0343359000, 0.0326858000, 0.0283007000, 0.0152771000, -0.032880600, -0.200909700, -0.739620100", \ - "0.0339264000, 0.0324843000, 0.0278789000, 0.0149826000, -0.033121100, -0.201317000, -0.740082800", \ - "0.0333957000, 0.0317662000, 0.0270645000, 0.0142179000, -0.033852000, -0.201847700, -0.740572100", \ - "0.0328441000, 0.0312040000, 0.0265666000, 0.0135405000, -0.034619400, -0.202548700, -0.741144500", \ - "0.0326131000, 0.0308244000, 0.0261095000, 0.0131382000, -0.035150900, -0.202955700, -0.741384300", \ - "0.0453405000, 0.0433990000, 0.0375526000, 0.0201277000, -0.034026100, -0.203125000, -0.741304200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0395566000, 0.0413533000, 0.0471093000, 0.0651245000, 0.1194461000, 0.2889725000, 0.8229751000", \ - "0.0394334000, 0.0412068000, 0.0470049000, 0.0649578000, 0.1194195000, 0.2887903000, 0.8218413000", \ - "0.0391534000, 0.0409320000, 0.0467296000, 0.0645704000, 0.1191522000, 0.2884167000, 0.8227426000", \ - "0.0387275000, 0.0405237000, 0.0462909000, 0.0642449000, 0.1186680000, 0.2882394000, 0.8222127000", \ - "0.0385661000, 0.0403680000, 0.0460662000, 0.0639599000, 0.1184425000, 0.2883124000, 0.8209640000", \ - "0.0395095000, 0.0412422000, 0.0465771000, 0.0636280000, 0.1181895000, 0.2874315000, 0.8216298000", \ - "0.0409110000, 0.0425899000, 0.0480386000, 0.0649335000, 0.1193541000, 0.2890004000, 0.8192970000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0301549000, 0.0284994000, 0.0240855000, 0.0109294000, -0.037150700, -0.205092300, -0.743738100", \ - "0.0299268000, 0.0282752000, 0.0238344000, 0.0107367000, -0.037309800, -0.205263600, -0.743982600", \ - "0.0296442000, 0.0280238000, 0.0235084000, 0.0104805000, -0.037651300, -0.205609200, -0.744305500", \ - "0.0291812000, 0.0274739000, 0.0229143000, 0.0098734000, -0.038272400, -0.206196300, -0.744848600", \ - "0.0289354000, 0.0272387000, 0.0225811000, 0.0093718000, -0.038891500, -0.206806100, -0.745312200", \ - "0.0291349000, 0.0273461000, 0.0224501000, 0.0093433000, -0.038274500, -0.206302300, -0.744868200", \ - "0.0432485000, 0.0412188000, 0.0351799000, 0.0174721000, -0.036750600, -0.205641600, -0.743734800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0360149000, 0.0378626000, 0.0436547000, 0.0615468000, 0.1161678000, 0.2854119000, 0.8196605000", \ - "0.0360904000, 0.0378812000, 0.0436874000, 0.0615165000, 0.1161010000, 0.2852345000, 0.8184085000", \ - "0.0358862000, 0.0377006000, 0.0434632000, 0.0614650000, 0.1159825000, 0.2854564000, 0.8193988000", \ - "0.0355257000, 0.0373095000, 0.0431461000, 0.0611004000, 0.1156402000, 0.2853729000, 0.8189805000", \ - "0.0354486000, 0.0372710000, 0.0429276000, 0.0605615000, 0.1151632000, 0.2847213000, 0.8178017000", \ - "0.0361588000, 0.0378981000, 0.0434048000, 0.0604716000, 0.1143614000, 0.2840342000, 0.8184888000", \ - "0.0372812000, 0.0389787000, 0.0443365000, 0.0616226000, 0.1159054000, 0.2858666000, 0.8152930000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0257862000, 0.0247535000, 0.0218052000, 0.0098406000, -0.039627100, -0.209654000, -0.748976700", \ - "0.0257574000, 0.0245656000, 0.0216653000, 0.0096952000, -0.039739700, -0.209774700, -0.749107700", \ - "0.0254013000, 0.0242666000, 0.0213042000, 0.0093689000, -0.040074300, -0.210185700, -0.749486600", \ - "0.0250901000, 0.0238395000, 0.0206366000, 0.0084446000, -0.040946900, -0.210767600, -0.749963400", \ - "0.0242694000, 0.0228819000, 0.0192861000, 0.0072228000, -0.041958000, -0.211368000, -0.750391500", \ - "0.0325007000, 0.0307211000, 0.0252753000, 0.0085144000, -0.042243400, -0.210980800, -0.749787000", \ - "0.0395491000, 0.0376008000, 0.0318320000, 0.0143619000, -0.039219600, -0.209262100, -0.747299400"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015747420, 0.0049596280, 0.0156202700, 0.0491958200, 0.1549415000, 0.4879859000"); - values("0.0359191000, 0.0376957000, 0.0434756000, 0.0614367000, 0.1160044000, 0.2856048000, 0.8204210000", \ - "0.0356782000, 0.0375408000, 0.0432474000, 0.0611825000, 0.1156848000, 0.2856362000, 0.8202623000", \ - "0.0354093000, 0.0372214000, 0.0430368000, 0.0610340000, 0.1154526000, 0.2855000000, 0.8201566000", \ - "0.0350004000, 0.0368042000, 0.0426100000, 0.0605860000, 0.1152230000, 0.2851892000, 0.8193577000", \ - "0.0354803000, 0.0372514000, 0.0428831000, 0.0602812000, 0.1148058000, 0.2847645000, 0.8191599000", \ - "0.0363362000, 0.0380704000, 0.0435809000, 0.0605344000, 0.1147531000, 0.2842005000, 0.8188460000", \ - "0.0389805000, 0.0406665000, 0.0460636000, 0.0629805000, 0.1171980000, 0.2869237000, 0.8172215000"); - } - } - max_capacitance : 0.4879860000; - max_transition : 1.5047510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.2454885000, 0.2500413000, 0.2615787000, 0.2862391000, 0.3363101000, 0.4451415000, 0.7402345000", \ - "0.2505230000, 0.2550710000, 0.2666380000, 0.2914001000, 0.3414420000, 0.4504010000, 0.7457940000", \ - "0.2632935000, 0.2678723000, 0.2793419000, 0.3041620000, 0.3537314000, 0.4633775000, 0.7585404000", \ - "0.2914405000, 0.2959464000, 0.3075007000, 0.3321666000, 0.3823195000, 0.4913169000, 0.7865198000", \ - "0.3546869000, 0.3592457000, 0.3707082000, 0.3954617000, 0.4454336000, 0.5550270000, 0.8503577000", \ - "0.4961475000, 0.5007340000, 0.5125118000, 0.5380690000, 0.5887192000, 0.6988066000, 0.9942374000", \ - "0.7540039000, 0.7596765000, 0.7737106000, 0.8036161000, 0.8608683000, 0.9765575000, 1.2748002000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1539274000, 0.1587919000, 0.1716918000, 0.2030056000, 0.2812817000, 0.5086606000, 1.2174207000", \ - "0.1580735000, 0.1629759000, 0.1759270000, 0.2073261000, 0.2857200000, 0.5124016000, 1.2225563000", \ - "0.1667795000, 0.1717698000, 0.1846924000, 0.2160850000, 0.2944686000, 0.5219820000, 1.2328181000", \ - "0.1837652000, 0.1886652000, 0.2016115000, 0.2329537000, 0.3113498000, 0.5380812000, 1.2488486000", \ - "0.2168782000, 0.2219241000, 0.2351699000, 0.2668195000, 0.3454904000, 0.5730545000, 1.2815087000", \ - "0.2695323000, 0.2749999000, 0.2892594000, 0.3227744000, 0.4032926000, 0.6315077000, 1.3424625000", \ - "0.3265113000, 0.3332080000, 0.3503843000, 0.3881655000, 0.4728767000, 0.7021742000, 1.4126537000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0343256000, 0.0368792000, 0.0436866000, 0.0589971000, 0.0987178000, 0.2137054000, 0.5922356000", \ - "0.0345293000, 0.0372091000, 0.0436017000, 0.0586842000, 0.0985387000, 0.2135793000, 0.5928059000", \ - "0.0345575000, 0.0371065000, 0.0431976000, 0.0586984000, 0.0993699000, 0.2132755000, 0.5938868000", \ - "0.0343472000, 0.0371072000, 0.0439456000, 0.0587203000, 0.0985949000, 0.2135264000, 0.5924509000", \ - "0.0347779000, 0.0368472000, 0.0433095000, 0.0586852000, 0.0986909000, 0.2132034000, 0.5929134000", \ - "0.0374898000, 0.0402990000, 0.0468820000, 0.0614601000, 0.1001801000, 0.2141134000, 0.5919415000", \ - "0.0485713000, 0.0515885000, 0.0588094000, 0.0743708000, 0.1142617000, 0.2254877000, 0.5957735000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0291285000, 0.0328364000, 0.0439884000, 0.0753087000, 0.1722307000, 0.4898785000, 1.5018630000", \ - "0.0290038000, 0.0328560000, 0.0443066000, 0.0754550000, 0.1722655000, 0.4896553000, 1.5038920000", \ - "0.0289021000, 0.0330026000, 0.0440780000, 0.0755996000, 0.1722444000, 0.4896689000, 1.5046686000", \ - "0.0290020000, 0.0329223000, 0.0439485000, 0.0755431000, 0.1722464000, 0.4896642000, 1.5026089000", \ - "0.0300053000, 0.0337643000, 0.0449596000, 0.0763416000, 0.1724264000, 0.4899763000, 1.4993479000", \ - "0.0334013000, 0.0376020000, 0.0492057000, 0.0801044000, 0.1750023000, 0.4885318000, 1.5028249000", \ - "0.0432023000, 0.0479210000, 0.0599568000, 0.0908236000, 0.1810203000, 0.4918722000, 1.4977924000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.2255689000, 0.2301443000, 0.2415421000, 0.2663449000, 0.3163912000, 0.4252969000, 0.7204513000", \ - "0.2295001000, 0.2340446000, 0.2455286000, 0.2703379000, 0.3203506000, 0.4299710000, 0.7254491000", \ - "0.2398344000, 0.2443908000, 0.2558778000, 0.2806902000, 0.3307589000, 0.4396454000, 0.7353533000", \ - "0.2676946000, 0.2722464000, 0.2837194000, 0.3084524000, 0.3586355000, 0.4680075000, 0.7637728000", \ - "0.3360694000, 0.3406578000, 0.3520756000, 0.3768311000, 0.4268745000, 0.5366190000, 0.8321784000", \ - "0.4933576000, 0.4981943000, 0.5102799000, 0.5358171000, 0.5861325000, 0.6963229000, 0.9916138000", \ - "0.7646079000, 0.7709082000, 0.7866347000, 0.8195143000, 0.8790981000, 0.9948388000, 1.2924483000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1447217000, 0.1496852000, 0.1629029000, 0.1946766000, 0.2736666000, 0.5009514000, 1.2113842000", \ - "0.1496510000, 0.1545926000, 0.1677553000, 0.1994978000, 0.2784927000, 0.5058607000, 1.2155202000", \ - "0.1585604000, 0.1635164000, 0.1766873000, 0.2085631000, 0.2875678000, 0.5148569000, 1.2253587000", \ - "0.1752033000, 0.1802464000, 0.1933968000, 0.2251531000, 0.3040695000, 0.5316657000, 1.2407207000", \ - "0.2068785000, 0.2120128000, 0.2254637000, 0.2575816000, 0.3369944000, 0.5637790000, 1.2733437000", \ - "0.2546887000, 0.2602645000, 0.2750608000, 0.3091895000, 0.3906047000, 0.6186033000, 1.3287295000", \ - "0.2978531000, 0.3049316000, 0.3229942000, 0.3623537000, 0.4487606000, 0.6781234000, 1.3865356000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0343178000, 0.0371993000, 0.0432393000, 0.0587227000, 0.0986686000, 0.2137286000, 0.5925264000", \ - "0.0344030000, 0.0370320000, 0.0433471000, 0.0589066000, 0.0987078000, 0.2131982000, 0.5928434000", \ - "0.0344031000, 0.0368882000, 0.0433812000, 0.0587253000, 0.0986208000, 0.2137698000, 0.5925344000", \ - "0.0342970000, 0.0368270000, 0.0433434000, 0.0587772000, 0.0986523000, 0.2139751000, 0.5924071000", \ - "0.0344894000, 0.0370968000, 0.0435166000, 0.0587569000, 0.0984318000, 0.2130392000, 0.5929249000", \ - "0.0391483000, 0.0412683000, 0.0475776000, 0.0621283000, 0.1002709000, 0.2139852000, 0.5943602000", \ - "0.0571876000, 0.0603280000, 0.0679536000, 0.0831097000, 0.1176201000, 0.2244848000, 0.5954401000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0291952000, 0.0333663000, 0.0444805000, 0.0759703000, 0.1721865000, 0.4878920000, 1.4977981000", \ - "0.0292114000, 0.0331264000, 0.0445818000, 0.0757979000, 0.1721056000, 0.4879051000, 1.5005694000", \ - "0.0292063000, 0.0332011000, 0.0444923000, 0.0760591000, 0.1722268000, 0.4879222000, 1.4976329000", \ - "0.0291949000, 0.0332446000, 0.0445589000, 0.0758851000, 0.1721294000, 0.4885791000, 1.5010744000", \ - "0.0303168000, 0.0345832000, 0.0454481000, 0.0769367000, 0.1723464000, 0.4881922000, 1.4984435000", \ - "0.0348474000, 0.0389260000, 0.0506183000, 0.0817279000, 0.1756569000, 0.4873053000, 1.4980360000", \ - "0.0462487000, 0.0508981000, 0.0632101000, 0.0944654000, 0.1829076000, 0.4907493000, 1.4931302000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.2029143000, 0.2072385000, 0.2183803000, 0.2436340000, 0.2988021000, 0.4169345000, 0.7160897000", \ - "0.2083491000, 0.2126664000, 0.2236897000, 0.2487985000, 0.3037650000, 0.4223432000, 0.7219009000", \ - "0.2209197000, 0.2252385000, 0.2363610000, 0.2614834000, 0.3167338000, 0.4349568000, 0.7345076000", \ - "0.2483613000, 0.2526625000, 0.2637421000, 0.2890385000, 0.3440739000, 0.4625378000, 0.7618015000", \ - "0.3111168000, 0.3153912000, 0.3264279000, 0.3517208000, 0.4069108000, 0.5255562000, 0.8248958000", \ - "0.4432088000, 0.4477708000, 0.4597366000, 0.4864434000, 0.5439682000, 0.6643265000, 0.9643951000", \ - "0.6753656000, 0.6810397000, 0.6954560000, 0.7267810000, 0.7918362000, 0.9235605000, 1.2297641000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1450189000, 0.1499144000, 0.1628987000, 0.1942935000, 0.2727309000, 0.5000762000, 1.2102533000", \ - "0.1493230000, 0.1542092000, 0.1671578000, 0.1983714000, 0.2768510000, 0.5044613000, 1.2148466000", \ - "0.1584949000, 0.1633345000, 0.1762337000, 0.2075289000, 0.2860654000, 0.5132701000, 1.2243097000", \ - "0.1789677000, 0.1838409000, 0.1967718000, 0.2281755000, 0.3066205000, 0.5348988000, 1.2474234000", \ - "0.2227101000, 0.2277239000, 0.2409344000, 0.2726213000, 0.3514230000, 0.5791002000, 1.2886118000", \ - "0.2898800000, 0.2954408000, 0.3095819000, 0.3429853000, 0.4234313000, 0.6523184000, 1.3652904000", \ - "0.3591908000, 0.3661544000, 0.3837218000, 0.4217383000, 0.5054782000, 0.7345831000, 1.4457672000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0308325000, 0.0333660000, 0.0403751000, 0.0592329000, 0.1066164000, 0.2238430000, 0.5953406000", \ - "0.0305501000, 0.0331719000, 0.0403865000, 0.0593565000, 0.1068855000, 0.2238959000, 0.5937193000", \ - "0.0308126000, 0.0332005000, 0.0403354000, 0.0592899000, 0.1065382000, 0.2236233000, 0.5939637000", \ - "0.0306041000, 0.0332931000, 0.0405216000, 0.0591762000, 0.1066944000, 0.2238631000, 0.5952181000", \ - "0.0305771000, 0.0333292000, 0.0403339000, 0.0592305000, 0.1064339000, 0.2237093000, 0.5951209000", \ - "0.0353538000, 0.0383730000, 0.0454844000, 0.0638702000, 0.1109035000, 0.2257476000, 0.5945862000", \ - "0.0478350000, 0.0511388000, 0.0587180000, 0.0781838000, 0.1278238000, 0.2415614000, 0.5995084000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0288515000, 0.0328157000, 0.0440793000, 0.0756024000, 0.1722346000, 0.4895419000, 1.5034217000", \ - "0.0288401000, 0.0327930000, 0.0440116000, 0.0755058000, 0.1722174000, 0.4897427000, 1.4996133000", \ - "0.0289416000, 0.0328181000, 0.0441411000, 0.0755271000, 0.1720196000, 0.4893951000, 1.5036704000", \ - "0.0288014000, 0.0327959000, 0.0439918000, 0.0753755000, 0.1719808000, 0.4892443000, 1.5010337000", \ - "0.0299730000, 0.0338912000, 0.0450106000, 0.0762602000, 0.1725113000, 0.4897333000, 1.4988820000", \ - "0.0347255000, 0.0386981000, 0.0498338000, 0.0804427000, 0.1751167000, 0.4903007000, 1.5032018000", \ - "0.0461119000, 0.0506706000, 0.0624536000, 0.0920624000, 0.1806987000, 0.4920830000, 1.5011773000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1835976000, 0.1879538000, 0.1989936000, 0.2242808000, 0.2795479000, 0.3977290000, 0.6967616000", \ - "0.1876519000, 0.1919755000, 0.2030518000, 0.2283419000, 0.2836119000, 0.4017758000, 0.7010041000", \ - "0.1983067000, 0.2026016000, 0.2136938000, 0.2389989000, 0.2942795000, 0.4125040000, 0.7117980000", \ - "0.2261089000, 0.2304223000, 0.2415129000, 0.2667466000, 0.3217913000, 0.4404551000, 0.7400353000", \ - "0.2941030000, 0.2983982000, 0.3094607000, 0.3345581000, 0.3897686000, 0.5084128000, 0.8080466000", \ - "0.4397446000, 0.4446658000, 0.4571538000, 0.4845068000, 0.5412467000, 0.6617992000, 0.9618302000", \ - "0.6781318000, 0.6845293000, 0.7005099000, 0.7354296000, 0.8041195000, 0.9373681000, 1.2438823000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1336015000, 0.1385286000, 0.1515982000, 0.1832342000, 0.2621109000, 0.4890939000, 1.1996483000", \ - "0.1381712000, 0.1431011000, 0.1561732000, 0.1876648000, 0.2665412000, 0.4942276000, 1.2037779000", \ - "0.1472160000, 0.1521493000, 0.1652847000, 0.1968829000, 0.2757056000, 0.5037168000, 1.2155569000", \ - "0.1663141000, 0.1712741000, 0.1843359000, 0.2159162000, 0.2947511000, 0.5228662000, 1.2333383000", \ - "0.2052881000, 0.2103848000, 0.2237399000, 0.2558194000, 0.3350611000, 0.5630418000, 1.2721719000", \ - "0.2606889000, 0.2663528000, 0.2809520000, 0.3148584000, 0.3959954000, 0.6249447000, 1.3359843000", \ - "0.3086142000, 0.3158003000, 0.3341208000, 0.3735954000, 0.4587622000, 0.6883344000, 1.3988928000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0304851000, 0.0331619000, 0.0403572000, 0.0592563000, 0.1065580000, 0.2237415000, 0.5952439000", \ - "0.0305772000, 0.0332003000, 0.0406686000, 0.0590177000, 0.1064980000, 0.2238879000, 0.5942839000", \ - "0.0308609000, 0.0332583000, 0.0406558000, 0.0591510000, 0.1064728000, 0.2238219000, 0.5939110000", \ - "0.0308197000, 0.0331257000, 0.0403664000, 0.0590632000, 0.1064798000, 0.2236463000, 0.5943341000", \ - "0.0307488000, 0.0332577000, 0.0403778000, 0.0592014000, 0.1065387000, 0.2236054000, 0.5947455000", \ - "0.0391297000, 0.0419877000, 0.0484613000, 0.0660322000, 0.1126329000, 0.2264481000, 0.5959259000", \ - "0.0571181000, 0.0604251000, 0.0692425000, 0.0892249000, 0.1363124000, 0.2456756000, 0.6022438000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0291398000, 0.0331266000, 0.0442237000, 0.0758132000, 0.1722789000, 0.4892622000, 1.5035541000", \ - "0.0290186000, 0.0330227000, 0.0443729000, 0.0758111000, 0.1725763000, 0.4886652000, 1.4983684000", \ - "0.0290340000, 0.0330666000, 0.0443283000, 0.0758009000, 0.1723298000, 0.4889815000, 1.5028641000", \ - "0.0290309000, 0.0330394000, 0.0443648000, 0.0757908000, 0.1725470000, 0.4899541000, 1.5040326000", \ - "0.0305720000, 0.0345319000, 0.0456991000, 0.0771044000, 0.1730085000, 0.4892535000, 1.4991912000", \ - "0.0359541000, 0.0398474000, 0.0513287000, 0.0816573000, 0.1761581000, 0.4891423000, 1.5047511000", \ - "0.0486958000, 0.0534783000, 0.0650885000, 0.0938517000, 0.1820665000, 0.4918636000, 1.4970872000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0835541000, 0.0865858000, 0.0946342000, 0.1140758000, 0.1594433000, 0.2635524000, 0.5545846000", \ - "0.0892002000, 0.0922404000, 0.1002715000, 0.1197111000, 0.1650991000, 0.2692093000, 0.5602443000", \ - "0.1023868000, 0.1054515000, 0.1134063000, 0.1327919000, 0.1781550000, 0.2825850000, 0.5735843000", \ - "0.1341725000, 0.1371663000, 0.1450757000, 0.1644058000, 0.2099454000, 0.3143112000, 0.6051773000", \ - "0.1995413000, 0.2029337000, 0.2117501000, 0.2324028000, 0.2792605000, 0.3844283000, 0.6755405000", \ - "0.3043178000, 0.3087054000, 0.3199886000, 0.3457563000, 0.4013516000, 0.5143803000, 0.8064692000", \ - "0.4713528000, 0.4769839000, 0.4915839000, 0.5241648000, 0.5947881000, 0.7276302000, 1.0269134000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.1308782000, 0.1357516000, 0.1486901000, 0.1799690000, 0.2585621000, 0.4863172000, 1.1973625000", \ - "0.1345452000, 0.1394458000, 0.1523298000, 0.1837163000, 0.2623251000, 0.4900447000, 1.2016713000", \ - "0.1438407000, 0.1487404000, 0.1616798000, 0.1930798000, 0.2716897000, 0.4996140000, 1.2108428000", \ - "0.1660305000, 0.1709908000, 0.1840092000, 0.2153709000, 0.2939624000, 0.5227322000, 1.2351656000", \ - "0.2140879000, 0.2189873000, 0.2318594000, 0.2635362000, 0.3423468000, 0.5707800000, 1.2806641000", \ - "0.2805107000, 0.2858865000, 0.2997161000, 0.3321252000, 0.4119402000, 0.6410595000, 1.3557174000", \ - "0.3464188000, 0.3531092000, 0.3702149000, 0.4068650000, 0.4885510000, 0.7171103000, 1.4286461000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0172214000, 0.0193524000, 0.0254565000, 0.0430756000, 0.0870141000, 0.2025316000, 0.5855721000", \ - "0.0170614000, 0.0193582000, 0.0254738000, 0.0430817000, 0.0869968000, 0.2025371000, 0.5856657000", \ - "0.0171330000, 0.0193948000, 0.0254171000, 0.0431453000, 0.0868959000, 0.2023141000, 0.5857256000", \ - "0.0173909000, 0.0195115000, 0.0256662000, 0.0432257000, 0.0871502000, 0.2022144000, 0.5837621000", \ - "0.0217551000, 0.0239335000, 0.0299312000, 0.0467716000, 0.0894084000, 0.2032463000, 0.5845342000", \ - "0.0323156000, 0.0348729000, 0.0422160000, 0.0606089000, 0.1051976000, 0.2123499000, 0.5863879000", \ - "0.0478253000, 0.0513285000, 0.0602196000, 0.0829074000, 0.1361120000, 0.2409024000, 0.5919961000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015747400, 0.0049596300, 0.0156203000, 0.0491958000, 0.1549410000, 0.4879860000"); - values("0.0288656000, 0.0328417000, 0.0441308000, 0.0754196000, 0.1719783000, 0.4892879000, 1.5043295000", \ - "0.0290336000, 0.0330129000, 0.0442995000, 0.0754425000, 0.1722158000, 0.4896711000, 1.5034649000", \ - "0.0289100000, 0.0328882000, 0.0439349000, 0.0755515000, 0.1722354000, 0.4896616000, 1.5041263000", \ - "0.0288756000, 0.0327937000, 0.0440775000, 0.0752782000, 0.1720883000, 0.4893751000, 1.5040326000", \ - "0.0297438000, 0.0336227000, 0.0448853000, 0.0763385000, 0.1724737000, 0.4896430000, 1.5030168000", \ - "0.0348216000, 0.0385187000, 0.0490515000, 0.0794739000, 0.1753103000, 0.4904464000, 1.5025943000", \ - "0.0473687000, 0.0517361000, 0.0619595000, 0.0898482000, 0.1790137000, 0.4920150000, 1.5010747000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221ai_1") { - leakage_power () { - value : 7.9602313e-05; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 3.6069692e-05; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0005749000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 5.7669933e-05; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0005743000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 5.7756026e-05; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0005783000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 5.7873167e-05; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0005686000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 5.5935877e-05; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0036178000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0001943000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0033839000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0001943000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0030007000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0001938000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0005686000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 5.5935877e-05; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0041112000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0001946000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0038773000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0001945000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0034940000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0001938000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0005686000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 5.5935877e-05; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0028494000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0001943000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0026155000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0001938000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0022322000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0001938000; - when : "A1&A2&B1&B2&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o221ai"; - cell_leakage_power : 0.0010880900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039643000, 0.0039640000, 0.0039631000, 0.0039630000, 0.0039629000, 0.0039627000, 0.0039620000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003960200, -0.003958400, -0.003954200, -0.003953700, -0.003952600, -0.003949900, -0.003943600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024330000; - } - pin ("A2") { - capacitance : 0.0023230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039594000, 0.0039562000, 0.0039489000, 0.0039491000, 0.0039494000, 0.0039502000, 0.0039521000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003936800, -0.003936200, -0.003934800, -0.003935100, -0.003935900, -0.003937700, -0.003941900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024740000; - } - pin ("B1") { - capacitance : 0.0023190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041081000, 0.0041047000, 0.0040970000, 0.0040982000, 0.0041008000, 0.0041069000, 0.0041208000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004098400, -0.004096100, -0.004090800, -0.004089800, -0.004087600, -0.004082400, -0.004070300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023910000; - } - pin ("B2") { - capacitance : 0.0023020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039938000, 0.0039929000, 0.0039910000, 0.0039918000, 0.0039937000, 0.0039981000, 0.0040083000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003999800, -0.003994400, -0.003982100, -0.003981600, -0.003980500, -0.003978000, -0.003972200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024180000; - } - pin ("C1") { - capacitance : 0.0022480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048446000, 0.0048429000, 0.0048389000, 0.0048402000, 0.0048432000, 0.0048501000, 0.0048660000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002720000, -0.002720600, -0.002721900, -0.002710600, -0.002684700, -0.002624800, -0.002486900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0022820000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0085850000, 0.0075661000, 0.0052261000, -0.000134300, -0.012416700, -0.040493500, -0.104440200", \ - "0.0084802000, 0.0074552000, 0.0051222000, -0.000222400, -0.012490600, -0.040524200, -0.104583500", \ - "0.0083466000, 0.0073296000, 0.0050139000, -0.000325100, -0.012581600, -0.040645900, -0.104684400", \ - "0.0081929000, 0.0071793000, 0.0048594000, -0.000449300, -0.012694200, -0.040653200, -0.104658300", \ - "0.0080597000, 0.0070498000, 0.0047662000, -0.000522300, -0.012717200, -0.040678200, -0.104685200", \ - "0.0080799000, 0.0070347000, 0.0046725000, -0.000751900, -0.012936700, -0.040865000, -0.104787500", \ - "0.0084482000, 0.0074229000, 0.0050337000, -0.000426300, -0.012749300, -0.040891500, -0.104846800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0135007000, 0.0145477000, 0.0169114000, 0.0223009000, 0.0344898000, 0.0622964000, 0.1255689000", \ - "0.0133660000, 0.0144258000, 0.0168233000, 0.0222319000, 0.0344576000, 0.0622645000, 0.1254775000", \ - "0.0131403000, 0.0142128000, 0.0166355000, 0.0220762000, 0.0343849000, 0.0622428000, 0.1255338000", \ - "0.0128906000, 0.0139573000, 0.0163791000, 0.0218472000, 0.0341994000, 0.0621393000, 0.1255811000", \ - "0.0127422000, 0.0137939000, 0.0161985000, 0.0216260000, 0.0339558000, 0.0619304000, 0.1254617000", \ - "0.0126209000, 0.0136699000, 0.0160612000, 0.0214792000, 0.0338870000, 0.0618020000, 0.1251590000", \ - "0.0126292000, 0.0136401000, 0.0159204000, 0.0215101000, 0.0338049000, 0.0618792000, 0.1253766000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0071816000, 0.0061699000, 0.0038338000, -0.001525000, -0.013801500, -0.041830600, -0.105918800", \ - "0.0071380000, 0.0061334000, 0.0038216000, -0.001517400, -0.013771200, -0.041810500, -0.105928400", \ - "0.0069992000, 0.0059979000, 0.0037074000, -0.001585000, -0.013801000, -0.041788300, -0.105875800", \ - "0.0067375000, 0.0057429000, 0.0034740000, -0.001768900, -0.013921100, -0.041888700, -0.105894100", \ - "0.0064597000, 0.0054697000, 0.0032198000, -0.002021800, -0.014113200, -0.042015800, -0.105915700", \ - "0.0064594000, 0.0054403000, 0.0031090000, -0.002327300, -0.014452900, -0.042283400, -0.106124600", \ - "0.0069293000, 0.0059045000, 0.0034986000, -0.001979400, -0.014288900, -0.042407600, -0.106287900"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0113319000, 0.0123801000, 0.0147607000, 0.0201408000, 0.0323567000, 0.0601502000, 0.1234050000", \ - "0.0111355000, 0.0122000000, 0.0146024000, 0.0200516000, 0.0323023000, 0.0600580000, 0.1234096000", \ - "0.0109066000, 0.0119582000, 0.0143935000, 0.0198639000, 0.0321779000, 0.0600485000, 0.1233754000", \ - "0.0106553000, 0.0117250000, 0.0141664000, 0.0195288000, 0.0319795000, 0.0599529000, 0.1232763000", \ - "0.0106337000, 0.0117381000, 0.0141311000, 0.0194516000, 0.0317201000, 0.0596047000, 0.1232150000", \ - "0.0110019000, 0.0120290000, 0.0143160000, 0.0196288000, 0.0319056000, 0.0597455000, 0.1225870000", \ - "0.0117101000, 0.0127026000, 0.0151671000, 0.0203641000, 0.0324303000, 0.0599574000, 0.1229413000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0071864000, 0.0061764000, 0.0038758000, -0.001432600, -0.013680000, -0.041759600, -0.105751200", \ - "0.0070747000, 0.0060731000, 0.0037812000, -0.001508800, -0.013702800, -0.041768500, -0.105731200", \ - "0.0069245000, 0.0059179000, 0.0036337000, -0.001631900, -0.013788100, -0.041838200, -0.105731400", \ - "0.0066842000, 0.0056427000, 0.0033854000, -0.001903100, -0.014039600, -0.041904500, -0.105914600", \ - "0.0064821000, 0.0054420000, 0.0031477000, -0.002125100, -0.014271500, -0.042147800, -0.106023700", \ - "0.0068137000, 0.0055626000, 0.0031765000, -0.002208500, -0.014439100, -0.042273700, -0.106096500", \ - "0.0076828000, 0.0066115000, 0.0041763000, -0.001302200, -0.013815300, -0.041880300, -0.105632100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0089157000, 0.0100441000, 0.0125202000, 0.0179761000, 0.0302099000, 0.0580069000, 0.1213387000", \ - "0.0087060000, 0.0098394000, 0.0123877000, 0.0178864000, 0.0301640000, 0.0580668000, 0.1213269000", \ - "0.0084240000, 0.0095538000, 0.0121098000, 0.0176828000, 0.0300763000, 0.0579386000, 0.1214401000", \ - "0.0082335000, 0.0093122000, 0.0117769000, 0.0173136000, 0.0297497000, 0.0574964000, 0.1210732000", \ - "0.0083943000, 0.0094538000, 0.0117419000, 0.0171228000, 0.0294543000, 0.0569787000, 0.1205325000", \ - "0.0088231000, 0.0098376000, 0.0121355000, 0.0174668000, 0.0296253000, 0.0572496000, 0.1204850000", \ - "0.0099529000, 0.0108807000, 0.0130613000, 0.0181159000, 0.0300405000, 0.0579146000, 0.1214750000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0083195000, 0.0073003000, 0.0049630000, -0.000415600, -0.012680500, -0.040751500, -0.104727900", \ - "0.0082213000, 0.0071991000, 0.0048619000, -0.000489900, -0.012766900, -0.040814300, -0.104879700", \ - "0.0080919000, 0.0070734000, 0.0047494000, -0.000589900, -0.012843200, -0.040858100, -0.104937000", \ - "0.0079306000, 0.0069214000, 0.0046087000, -0.000705200, -0.012954900, -0.040934000, -0.104955600", \ - "0.0078353000, 0.0068212000, 0.0045131000, -0.000797000, -0.013007500, -0.040983100, -0.105026700", \ - "0.0078412000, 0.0068747000, 0.0045076000, -0.001017600, -0.013137000, -0.041112000, -0.105093000", \ - "0.0082431000, 0.0072203000, 0.0048398000, -0.000544900, -0.012937500, -0.041134600, -0.105089700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0172718000, 0.0183504000, 0.0207621000, 0.0261558000, 0.0384888000, 0.0663942000, 0.1297659000", \ - "0.0171875000, 0.0182204000, 0.0206069000, 0.0260415000, 0.0383955000, 0.0663021000, 0.1296400000", \ - "0.0169854000, 0.0180809000, 0.0204755000, 0.0259040000, 0.0382612000, 0.0661955000, 0.1296333000", \ - "0.0168306000, 0.0178867000, 0.0203040000, 0.0257935000, 0.0381651000, 0.0661215000, 0.1297523000", \ - "0.0167471000, 0.0177904000, 0.0202070000, 0.0256565000, 0.0380619000, 0.0660221000, 0.1295200000", \ - "0.0166613000, 0.0177158000, 0.0201677000, 0.0255884000, 0.0380758000, 0.0660905000, 0.1294658000", \ - "0.0170568000, 0.0180474000, 0.0203269000, 0.0258494000, 0.0382093000, 0.0662413000, 0.1296895000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0070171000, 0.0060021000, 0.0036723000, -0.001687700, -0.013970100, -0.042011400, -0.106125200", \ - "0.0069910000, 0.0059761000, 0.0036628000, -0.001673900, -0.013929200, -0.041946900, -0.106058700", \ - "0.0068301000, 0.0058347000, 0.0035488000, -0.001758900, -0.013954400, -0.041970100, -0.106043800", \ - "0.0065625000, 0.0055719000, 0.0033054000, -0.001931700, -0.014083400, -0.041996700, -0.106062400", \ - "0.0063295000, 0.0053283000, 0.0030600000, -0.002197700, -0.014294800, -0.042158600, -0.106133100", \ - "0.0062892000, 0.0052588000, 0.0029356000, -0.002425500, -0.014586600, -0.042418200, -0.106308200", \ - "0.0066417000, 0.0055856000, 0.0032111000, -0.002222500, -0.014520100, -0.042628200, -0.106475200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024820, 0.0059374060, 0.0135458300, 0.0309039900, 0.0705055800"); - values("0.0150713000, 0.0161234000, 0.0185226000, 0.0239801000, 0.0362799000, 0.0641914000, 0.1276359000", \ - "0.0149068000, 0.0159555000, 0.0183685000, 0.0238309000, 0.0362232000, 0.0640958000, 0.1276080000", \ - "0.0146370000, 0.0157030000, 0.0181504000, 0.0236242000, 0.0360376000, 0.0640494000, 0.1274507000", \ - "0.0144624000, 0.0155355000, 0.0179460000, 0.0234625000, 0.0358366000, 0.0638930000, 0.1273617000", \ - "0.0145559000, 0.0155894000, 0.0179677000, 0.0234209000, 0.0355855000, 0.0635241000, 0.1273005000", \ - "0.0151230000, 0.0161448000, 0.0185522000, 0.0237395000, 0.0359840000, 0.0638331000, 0.1268131000", \ - "0.0161464000, 0.0171703000, 0.0194361000, 0.0245337000, 0.0368795000, 0.0646908000, 0.1280044000"); - } - } - max_capacitance : 0.0705060000; - max_transition : 1.5275130000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0844206000, 0.0903811000, 0.1029107000, 0.1313181000, 0.1938771000, 0.3354426000, 0.6563632000", \ - "0.0890843000, 0.0949299000, 0.1073502000, 0.1357052000, 0.1983748000, 0.3400257000, 0.6609251000", \ - "0.0986245000, 0.1043700000, 0.1170425000, 0.1451471000, 0.2080889000, 0.3497173000, 0.6707850000", \ - "0.1162045000, 0.1220909000, 0.1349859000, 0.1632536000, 0.2261744000, 0.3678993000, 0.6893808000", \ - "0.1461045000, 0.1530377000, 0.1672971000, 0.1978834000, 0.2622842000, 0.4042943000, 0.7256103000", \ - "0.1889399000, 0.1980624000, 0.2168414000, 0.2544422000, 0.3310906000, 0.4840220000, 0.8079612000", \ - "0.2242211000, 0.2385554000, 0.2667217000, 0.3236872000, 0.4310453000, 0.6229166000, 0.9876835000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1314851000, 0.1404840000, 0.1629570000, 0.2103698000, 0.3177177000, 0.5567623000, 1.0990615000", \ - "0.1368254000, 0.1464406000, 0.1677303000, 0.2161246000, 0.3230470000, 0.5622665000, 1.1047520000", \ - "0.1485807000, 0.1585453000, 0.1804183000, 0.2286115000, 0.3352927000, 0.5752719000, 1.1170397000", \ - "0.1744892000, 0.1846149000, 0.2063731000, 0.2547422000, 0.3618072000, 0.6013909000, 1.1436230000", \ - "0.2334238000, 0.2435863000, 0.2654048000, 0.3133864000, 0.4202817000, 0.6606716000, 1.2032035000", \ - "0.3420019000, 0.3551056000, 0.3833623000, 0.4404662000, 0.5567973000, 0.7971044000, 1.3400135000", \ - "0.5260506000, 0.5453304000, 0.5849641000, 0.6641545000, 0.8164286000, 1.1033372000, 1.6548943000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0577204000, 0.0649159000, 0.0813302000, 0.1183380000, 0.2020748000, 0.3935615000, 0.8276592000", \ - "0.0577290000, 0.0648780000, 0.0813096000, 0.1182884000, 0.2022933000, 0.3934847000, 0.8278517000", \ - "0.0577048000, 0.0650045000, 0.0812025000, 0.1183034000, 0.2021487000, 0.3933152000, 0.8273150000", \ - "0.0587208000, 0.0656979000, 0.0816862000, 0.1183108000, 0.2021723000, 0.3934059000, 0.8311964000", \ - "0.0691896000, 0.0761837000, 0.0918420000, 0.1263160000, 0.2060113000, 0.3935951000, 0.8295318000", \ - "0.0991632000, 0.1070494000, 0.1234109000, 0.1589449000, 0.2375712000, 0.4111491000, 0.8335799000", \ - "0.1679663000, 0.1776948000, 0.1992433000, 0.2403067000, 0.3246300000, 0.4981866000, 0.8880862000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1124814000, 0.1255013000, 0.1527538000, 0.2147606000, 0.3567575000, 0.6811829000, 1.4172135000", \ - "0.1127643000, 0.1250460000, 0.1526978000, 0.2158108000, 0.3579530000, 0.6799769000, 1.4187150000", \ - "0.1123811000, 0.1248762000, 0.1528530000, 0.2150460000, 0.3563714000, 0.6800430000, 1.4150103000", \ - "0.1122502000, 0.1244084000, 0.1525339000, 0.2153035000, 0.3576023000, 0.6801523000, 1.4171628000", \ - "0.1215258000, 0.1324023000, 0.1582173000, 0.2174517000, 0.3570392000, 0.6801785000, 1.4171216000", \ - "0.1626116000, 0.1741818000, 0.2002960000, 0.2545679000, 0.3789477000, 0.6834717000, 1.4208461000", \ - "0.2474654000, 0.2618290000, 0.2942756000, 0.3595555000, 0.4902751000, 0.7636144000, 1.4352037000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0716462000, 0.0770822000, 0.0895673000, 0.1173339000, 0.1794686000, 0.3196975000, 0.6389201000", \ - "0.0761591000, 0.0818876000, 0.0942858000, 0.1222206000, 0.1844895000, 0.3249022000, 0.6438693000", \ - "0.0851638000, 0.0908187000, 0.1034464000, 0.1314500000, 0.1938873000, 0.3346347000, 0.6538731000", \ - "0.1011490000, 0.1069872000, 0.1197755000, 0.1480120000, 0.2106991000, 0.3516244000, 0.6712399000", \ - "0.1256829000, 0.1323736000, 0.1472294000, 0.1785064000, 0.2439210000, 0.3854351000, 0.7055206000", \ - "0.1551205000, 0.1642246000, 0.1842551000, 0.2250417000, 0.3035875000, 0.4588139000, 0.7814168000", \ - "0.1615117000, 0.1771145000, 0.2078221000, 0.2703168000, 0.3835017000, 0.5789909000, 0.9455569000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1188196000, 0.1284959000, 0.1500044000, 0.1985693000, 0.3050721000, 0.5450501000, 1.0868373000", \ - "0.1227605000, 0.1320780000, 0.1539476000, 0.2026324000, 0.3090989000, 0.5486044000, 1.0903846000", \ - "0.1330573000, 0.1426139000, 0.1650871000, 0.2130740000, 0.3204899000, 0.5602503000, 1.1024591000", \ - "0.1616547000, 0.1711999000, 0.1929677000, 0.2417845000, 0.3487644000, 0.5893722000, 1.1315955000", \ - "0.2292804000, 0.2402588000, 0.2617445000, 0.3096064000, 0.4141517000, 0.6539475000, 1.1964388000", \ - "0.3626882000, 0.3766480000, 0.4058650000, 0.4625147000, 0.5755684000, 0.8114489000, 1.3495152000", \ - "0.5750850000, 0.5958102000, 0.6408932000, 0.7295103000, 0.8964255000, 1.1836275000, 1.7228713000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0476546000, 0.0547606000, 0.0708694000, 0.1075582000, 0.1910767000, 0.3809500000, 0.8139976000", \ - "0.0476405000, 0.0546615000, 0.0707578000, 0.1075744000, 0.1911317000, 0.3806321000, 0.8131287000", \ - "0.0476609000, 0.0546611000, 0.0708261000, 0.1074965000, 0.1909460000, 0.3810608000, 0.8136463000", \ - "0.0495326000, 0.0562775000, 0.0717704000, 0.1077831000, 0.1909337000, 0.3808235000, 0.8141127000", \ - "0.0607578000, 0.0674721000, 0.0828823000, 0.1172343000, 0.1953178000, 0.3819020000, 0.8156141000", \ - "0.0919962000, 0.0995737000, 0.1158173000, 0.1510119000, 0.2284756000, 0.4010641000, 0.8179715000", \ - "0.1613523000, 0.1710244000, 0.1921241000, 0.2343504000, 0.3166095000, 0.4888802000, 0.8784194000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1123904000, 0.1246412000, 0.1522903000, 0.2155994000, 0.3563536000, 0.6815563000, 1.4168240000", \ - "0.1125986000, 0.1249609000, 0.1522748000, 0.2151753000, 0.3572101000, 0.6810669000, 1.4178018000", \ - "0.1124277000, 0.1246937000, 0.1525495000, 0.2145471000, 0.3565037000, 0.6804525000, 1.4170748000", \ - "0.1119143000, 0.1243654000, 0.1521926000, 0.2153812000, 0.3578533000, 0.6808122000, 1.4174190000", \ - "0.1262013000, 0.1362424000, 0.1604316000, 0.2184789000, 0.3570522000, 0.6810495000, 1.4166828000", \ - "0.1849981000, 0.1976195000, 0.2238943000, 0.2733188000, 0.3915812000, 0.6839511000, 1.4160974000", \ - "0.2880632000, 0.3064023000, 0.3448919000, 0.4178708000, 0.5463461000, 0.7920433000, 1.4412505000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0764847000, 0.0823115000, 0.0946685000, 0.1230478000, 0.1857078000, 0.3273247000, 0.6483299000", \ - "0.0804372000, 0.0859915000, 0.0991154000, 0.1270950000, 0.1898667000, 0.3315926000, 0.6536350000", \ - "0.0899106000, 0.0953478000, 0.1083104000, 0.1365964000, 0.1993097000, 0.3409701000, 0.6618935000", \ - "0.1095896000, 0.1152772000, 0.1281770000, 0.1565267000, 0.2196493000, 0.3614453000, 0.6825630000", \ - "0.1452152000, 0.1524241000, 0.1685031000, 0.2003943000, 0.2661024000, 0.4083059000, 0.7302572000", \ - "0.1932003000, 0.2036644000, 0.2258159000, 0.2705342000, 0.3548804000, 0.5132197000, 0.8398098000", \ - "0.2285331000, 0.2452559000, 0.2811092000, 0.3499770000, 0.4784360000, 0.6971717000, 1.0803793000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1079666000, 0.1176887000, 0.1394951000, 0.1896339000, 0.3008420000, 0.5552270000, 1.1322001000", \ - "0.1132302000, 0.1230151000, 0.1451160000, 0.1954719000, 0.3069822000, 0.5617208000, 1.1388093000", \ - "0.1254163000, 0.1353647000, 0.1576229000, 0.2079708000, 0.3203475000, 0.5750193000, 1.1525335000", \ - "0.1524216000, 0.1622931000, 0.1846895000, 0.2349182000, 0.3479043000, 0.6030857000, 1.1824841000", \ - "0.2128227000, 0.2236600000, 0.2472503000, 0.2973195000, 0.4104267000, 0.6658327000, 1.2448844000", \ - "0.3200400000, 0.3349339000, 0.3666699000, 0.4314247000, 0.5558921000, 0.8116432000, 1.3916390000", \ - "0.5029857000, 0.5260671000, 0.5733718000, 0.6672548000, 0.8357421000, 1.1425577000, 1.7287753000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0577326000, 0.0648946000, 0.0813284000, 0.1182624000, 0.2022204000, 0.3940751000, 0.8276668000", \ - "0.0576449000, 0.0649349000, 0.0812278000, 0.1183226000, 0.2022749000, 0.3933852000, 0.8288314000", \ - "0.0577990000, 0.0649056000, 0.0811727000, 0.1182259000, 0.2021520000, 0.3939247000, 0.8282542000", \ - "0.0600748000, 0.0670545000, 0.0828528000, 0.1184763000, 0.2021828000, 0.3933349000, 0.8272605000", \ - "0.0772090000, 0.0838725000, 0.0996038000, 0.1325687000, 0.2085600000, 0.3936453000, 0.8284297000", \ - "0.1183537000, 0.1268948000, 0.1445780000, 0.1811935000, 0.2556664000, 0.4195629000, 0.8317860000", \ - "0.1959220000, 0.2078078000, 0.2334380000, 0.2823526000, 0.3749021000, 0.5459431000, 0.9135276000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1161392000, 0.1289631000, 0.1581507000, 0.2245766000, 0.3752622000, 0.7183044000, 1.5060783000", \ - "0.1161295000, 0.1289455000, 0.1580863000, 0.2245348000, 0.3752676000, 0.7192689000, 1.5093556000", \ - "0.1161317000, 0.1289579000, 0.1581012000, 0.2243927000, 0.3750307000, 0.7188034000, 1.5064517000", \ - "0.1162478000, 0.1289868000, 0.1581129000, 0.2243937000, 0.3750447000, 0.7184586000, 1.5038245000", \ - "0.1302205000, 0.1412665000, 0.1673165000, 0.2285737000, 0.3751505000, 0.7192655000, 1.5039930000", \ - "0.1803961000, 0.1913540000, 0.2160268000, 0.2706990000, 0.3996413000, 0.7231764000, 1.5088926000", \ - "0.2838973000, 0.2970471000, 0.3253156000, 0.3870099000, 0.5147053000, 0.7961093000, 1.5275131000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0621622000, 0.0675189000, 0.0797662000, 0.1070684000, 0.1681078000, 0.3059175000, 0.6191447000", \ - "0.0664983000, 0.0719324000, 0.0843136000, 0.1116128000, 0.1727753000, 0.3105691000, 0.6239044000", \ - "0.0751770000, 0.0806327000, 0.0930974000, 0.1206331000, 0.1819846000, 0.3200094000, 0.6344162000", \ - "0.0928741000, 0.0987268000, 0.1116693000, 0.1395239000, 0.2011652000, 0.3397179000, 0.6534140000", \ - "0.1209494000, 0.1288721000, 0.1454390000, 0.1786320000, 0.2452554000, 0.3847683000, 0.6991932000", \ - "0.1503118000, 0.1623431000, 0.1874384000, 0.2357832000, 0.3233865000, 0.4829147000, 0.8037500000", \ - "0.1550158000, 0.1745152000, 0.2134775000, 0.2894880000, 0.4242846000, 0.6477134000, 1.0301037000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0929605000, 0.1027208000, 0.1246112000, 0.1742288000, 0.2859965000, 0.5406877000, 1.1183943000", \ - "0.0963655000, 0.1062597000, 0.1286207000, 0.1789945000, 0.2906921000, 0.5450251000, 1.1224356000", \ - "0.1067392000, 0.1165853000, 0.1391418000, 0.1894735000, 0.3024330000, 0.5563975000, 1.1344669000", \ - "0.1345773000, 0.1444339000, 0.1665650000, 0.2160114000, 0.3293659000, 0.5840173000, 1.1627579000", \ - "0.2003487000, 0.2115993000, 0.2349842000, 0.2836014000, 0.3946279000, 0.6496318000, 1.2293123000", \ - "0.3123437000, 0.3295953000, 0.3650113000, 0.4334934000, 0.5552946000, 0.8063772000, 1.3813867000", \ - "0.4951755000, 0.5208712000, 0.5751626000, 0.6795499000, 0.8686295000, 1.1790644000, 1.7539352000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0468701000, 0.0538577000, 0.0696746000, 0.1056524000, 0.1874701000, 0.3739140000, 0.7990238000", \ - "0.0468502000, 0.0538855000, 0.0695981000, 0.1056681000, 0.1874535000, 0.3741194000, 0.8000829000", \ - "0.0469053000, 0.0537857000, 0.0696517000, 0.1056390000, 0.1878200000, 0.3738533000, 0.7998680000", \ - "0.0513373000, 0.0575972000, 0.0722947000, 0.1067781000, 0.1876319000, 0.3755017000, 0.7993780000", \ - "0.0698364000, 0.0765626000, 0.0913077000, 0.1235516000, 0.1960137000, 0.3754485000, 0.7989312000", \ - "0.1104173000, 0.1190063000, 0.1372618000, 0.1736667000, 0.2456492000, 0.4038698000, 0.8030944000", \ - "0.1868898000, 0.1995514000, 0.2243087000, 0.2744268000, 0.3637785000, 0.5327985000, 0.8914235000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.1161305000, 0.1289766000, 0.1581113000, 0.2244730000, 0.3750968000, 0.7186500000, 1.5060920000", \ - "0.1161277000, 0.1289531000, 0.1581551000, 0.2245678000, 0.3752700000, 0.7198850000, 1.5060803000", \ - "0.1161138000, 0.1289572000, 0.1581388000, 0.2244800000, 0.3751192000, 0.7199472000, 1.5082866000", \ - "0.1172490000, 0.1296093000, 0.1579892000, 0.2244437000, 0.3753868000, 0.7199308000, 1.5082833000", \ - "0.1427646000, 0.1524085000, 0.1756724000, 0.2329331000, 0.3754120000, 0.7203387000, 1.5019425000", \ - "0.2125526000, 0.2242389000, 0.2482795000, 0.2965331000, 0.4126795000, 0.7247009000, 1.5093738000", \ - "0.3303628000, 0.3472702000, 0.3830884000, 0.4534644000, 0.5815616000, 0.8343206000, 1.5267744000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0644692000, 0.0700470000, 0.0832091000, 0.1112297000, 0.1742626000, 0.3159913000, 0.6371448000", \ - "0.0684202000, 0.0741653000, 0.0870971000, 0.1154762000, 0.1785806000, 0.3203138000, 0.6414222000", \ - "0.0781775000, 0.0838552000, 0.0968037000, 0.1251050000, 0.1885397000, 0.3304437000, 0.6517054000", \ - "0.1017696000, 0.1071692000, 0.1197751000, 0.1478721000, 0.2113053000, 0.3534834000, 0.6746779000", \ - "0.1439311000, 0.1519430000, 0.1689021000, 0.2026047000, 0.2668758000, 0.4088579000, 0.7303770000", \ - "0.1945234000, 0.2077974000, 0.2334200000, 0.2834372000, 0.3765048000, 0.5347467000, 0.8551481000", \ - "0.2434219000, 0.2615880000, 0.2998207000, 0.3763728000, 0.5179955000, 0.7591011000, 1.1482050000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0333173000, 0.0378498000, 0.0479018000, 0.0698620000, 0.1192600000, 0.2312954000, 0.4890811000", \ - "0.0385818000, 0.0431603000, 0.0531709000, 0.0752140000, 0.1253033000, 0.2375787000, 0.4927220000", \ - "0.0517733000, 0.0563731000, 0.0662799000, 0.0886819000, 0.1386863000, 0.2503220000, 0.5075841000", \ - "0.0793064000, 0.0855018000, 0.0976195000, 0.1200746000, 0.1701417000, 0.2819616000, 0.5378591000", \ - "0.1223157000, 0.1322947000, 0.1513138000, 0.1859820000, 0.2439254000, 0.3533064000, 0.6086670000", \ - "0.1882270000, 0.2049961000, 0.2359918000, 0.2931398000, 0.3846130000, 0.5281713000, 0.7822023000", \ - "0.2939471000, 0.3184087000, 0.3680104000, 0.4588296000, 0.6096092000, 0.8407134000, 1.1759790000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0577309000, 0.0649000000, 0.0811968000, 0.1183283000, 0.2021750000, 0.3937339000, 0.8286325000", \ - "0.0576965000, 0.0649508000, 0.0811932000, 0.1182772000, 0.2018199000, 0.3936246000, 0.8272873000", \ - "0.0572657000, 0.0647228000, 0.0810599000, 0.1182610000, 0.2018102000, 0.3939508000, 0.8273843000", \ - "0.0615308000, 0.0679598000, 0.0827804000, 0.1179795000, 0.2023269000, 0.3939096000, 0.8291650000", \ - "0.0858604000, 0.0928515000, 0.1089965000, 0.1402150000, 0.2113782000, 0.3939461000, 0.8294236000", \ - "0.1344825000, 0.1436479000, 0.1654669000, 0.2068546000, 0.2816006000, 0.4356884000, 0.8318468000", \ - "0.2137215000, 0.2294274000, 0.2620517000, 0.3239200000, 0.4313074000, 0.6122711000, 0.9514598000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011407200, 0.0026024800, 0.0059374100, 0.0135458000, 0.0309040000, 0.0705056000"); - values("0.0521796000, 0.0585447000, 0.0728733000, 0.1048245000, 0.1756586000, 0.3347334000, 0.6976728000", \ - "0.0522254000, 0.0585653000, 0.0728836000, 0.1048260000, 0.1756917000, 0.3349314000, 0.6976842000", \ - "0.0538443000, 0.0594196000, 0.0729797000, 0.1048586000, 0.1756552000, 0.3348229000, 0.6984604000", \ - "0.0691865000, 0.0729841000, 0.0828535000, 0.1089189000, 0.1756759000, 0.3349810000, 0.6983393000", \ - "0.1144457000, 0.1175949000, 0.1249836000, 0.1425635000, 0.1927886000, 0.3361569000, 0.6974314000", \ - "0.1908599000, 0.1957235000, 0.2064836000, 0.2299615000, 0.2792245000, 0.3858037000, 0.7028442000", \ - "0.3182681000, 0.3261790000, 0.3438780000, 0.3825328000, 0.4550061000, 0.5784191000, 0.8284378000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221ai_2") { - leakage_power () { - value : 0.0001839000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 8.3183521e-05; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0014228000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0001406000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0014197000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0001405000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0013980000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 6.9222622e-05; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0014311000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0001373000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0049871000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0005536000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0046773000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0005538000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0041281000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0005390000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0014311000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0001373000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0051478000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0005542000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0048381000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0005560000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0042888000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0005376000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0014311000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0001373000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0038573000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0005574000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0035475000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0005545000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0030005000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0005277000; - when : "A1&A2&B1&B2&!C1"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__o221ai"; - cell_leakage_power : 0.0016552910; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0047770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045410000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079786000, 0.0079834000, 0.0079943000, 0.0079974000, 0.0080044000, 0.0080205000, 0.0080577000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008020100, -0.008010100, -0.007987100, -0.007988300, -0.007991100, -0.007997400, -0.008012100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050120000; - } - pin ("A2") { - capacitance : 0.0043180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075196000, 0.0075268000, 0.0075433000, 0.0075448000, 0.0075483000, 0.0075563000, 0.0075747000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007562800, -0.007556800, -0.007543000, -0.007544100, -0.007546700, -0.007552600, -0.007566400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046180000; - } - pin ("B1") { - capacitance : 0.0048790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082793000, 0.0082741000, 0.0082621000, 0.0082655000, 0.0082733000, 0.0082913000, 0.0083329000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008306800, -0.008291100, -0.008254800, -0.008250800, -0.008241800, -0.008220800, -0.008172500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050740000; - } - pin ("B2") { - capacitance : 0.0042780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075602000, 0.0075593000, 0.0075571000, 0.0075615000, 0.0075717000, 0.0075953000, 0.0076495000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007557200, -0.007553300, -0.007544300, -0.007540000, -0.007530100, -0.007507400, -0.007455000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045070000; - } - pin ("C1") { - capacitance : 0.0042400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090214000, 0.0090259000, 0.0090360000, 0.0090364000, 0.0090372000, 0.0090392000, 0.0090436000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004477200, -0.004484500, -0.004501300, -0.004477500, -0.004422500, -0.004295900, -0.004004000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0043320000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0149990000, 0.0138182000, 0.0107486000, 0.0030207000, -0.016576700, -0.066104800, -0.191085800", \ - "0.0147666000, 0.0135777000, 0.0105244000, 0.0028038000, -0.016788200, -0.066286900, -0.191316700", \ - "0.0144545000, 0.0132516000, 0.0102374000, 0.0025469000, -0.016988700, -0.066475000, -0.191477500", \ - "0.0141063000, 0.0129207000, 0.0098875000, 0.0022565000, -0.017209800, -0.066635100, -0.191608700", \ - "0.0138821000, 0.0126840000, 0.0097065000, 0.0020875000, -0.017396700, -0.066767200, -0.191609500", \ - "0.0139920000, 0.0127734000, 0.0096811000, 0.0019931000, -0.017795600, -0.066974600, -0.191836700", \ - "0.0147296000, 0.0135270000, 0.0103805000, 0.0025214000, -0.017204200, -0.067087900, -0.191829200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0323784000, 0.0335997000, 0.0366395000, 0.0446514000, 0.0643399000, 0.1138474000, 0.2376373000", \ - "0.0319702000, 0.0332116000, 0.0364578000, 0.0442716000, 0.0640706000, 0.1134906000, 0.2374833000", \ - "0.0316659000, 0.0329030000, 0.0359939000, 0.0440322000, 0.0638398000, 0.1132884000, 0.2372591000", \ - "0.0312145000, 0.0324774000, 0.0356641000, 0.0436046000, 0.0635198000, 0.1130546000, 0.2372112000", \ - "0.0309353000, 0.0321684000, 0.0353041000, 0.0432402000, 0.0631557000, 0.1126858000, 0.2369109000", \ - "0.0308229000, 0.0319777000, 0.0352289000, 0.0431239000, 0.0631359000, 0.1126638000, 0.2369071000", \ - "0.0311128000, 0.0322866000, 0.0352986000, 0.0434166000, 0.0633261000, 0.1131159000, 0.2370193000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0115908000, 0.0104176000, 0.0073751000, -0.000347600, -0.019939500, -0.069506900, -0.194639100", \ - "0.0115304000, 0.0103545000, 0.0073401000, -0.000325700, -0.019885500, -0.069412100, -0.194565000", \ - "0.0112941000, 0.0101147000, 0.0071443000, -0.000463400, -0.019910700, -0.069410200, -0.194468300", \ - "0.0108531000, 0.0096776000, 0.0067124000, -0.000819900, -0.020149400, -0.069466100, -0.194434800", \ - "0.0104513000, 0.0092786000, 0.0063115000, -0.001271500, -0.020521200, -0.069703900, -0.194609800", \ - "0.0103993000, 0.0092417000, 0.0062028000, -0.001493300, -0.021114800, -0.070150100, -0.194876900", \ - "0.0112264000, 0.0099623000, 0.0068412000, -0.000997200, -0.020787400, -0.070474000, -0.195120400"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0278152000, 0.0289856000, 0.0320725000, 0.0399638000, 0.0597880000, 0.1092770000, 0.2329941000", \ - "0.0274384000, 0.0286697000, 0.0318086000, 0.0397234000, 0.0596490000, 0.1090634000, 0.2327880000", \ - "0.0269537000, 0.0282042000, 0.0314419000, 0.0393412000, 0.0592399000, 0.1088629000, 0.2327638000", \ - "0.0265635000, 0.0279100000, 0.0311160000, 0.0390076000, 0.0589774000, 0.1085717000, 0.2325744000", \ - "0.0262813000, 0.0274921000, 0.0306018000, 0.0385048000, 0.0583819000, 0.1082351000, 0.2322447000", \ - "0.0270768000, 0.0282963000, 0.0315557000, 0.0390837000, 0.0589454000, 0.1079601000, 0.2321563000", \ - "0.0296209000, 0.0307691000, 0.0336735000, 0.0431149000, 0.0624295000, 0.1089347000, 0.2321108000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0154509000, 0.0142153000, 0.0111861000, 0.0034572000, -0.016104700, -0.065605600, -0.190720800", \ - "0.0151879000, 0.0140069000, 0.0109250000, 0.0032438000, -0.016347700, -0.065889500, -0.190863900", \ - "0.0148672000, 0.0136854000, 0.0106649000, 0.0029912000, -0.016547500, -0.066069800, -0.191217600", \ - "0.0145022000, 0.0133329000, 0.0103163000, 0.0026425000, -0.016830600, -0.066255500, -0.191186200", \ - "0.0142495000, 0.0130446000, 0.0100141000, 0.0023914000, -0.016898700, -0.066336700, -0.191248500", \ - "0.0143020000, 0.0130680000, 0.0099875000, 0.0021879000, -0.017436100, -0.066689300, -0.191431800", \ - "0.0151140000, 0.0138419000, 0.0107165000, 0.0028773000, -0.016864400, -0.066731000, -0.191589800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0250201000, 0.0262604000, 0.0293991000, 0.0372588000, 0.0568660000, 0.1060014000, 0.2295898000", \ - "0.0246550000, 0.0259253000, 0.0291049000, 0.0370390000, 0.0567203000, 0.1059764000, 0.2295317000", \ - "0.0241101000, 0.0253926000, 0.0286182000, 0.0366330000, 0.0564542000, 0.1058372000, 0.2294249000", \ - "0.0236009000, 0.0248848000, 0.0280834000, 0.0360799000, 0.0559888000, 0.1055016000, 0.2293381000", \ - "0.0232542000, 0.0245224000, 0.0276667000, 0.0355909000, 0.0554383000, 0.1049431000, 0.2289686000", \ - "0.0231209000, 0.0243524000, 0.0274998000, 0.0353070000, 0.0552762000, 0.1048475000, 0.2288174000", \ - "0.0230335000, 0.0242308000, 0.0272030000, 0.0354849000, 0.0553261000, 0.1044411000, 0.2287359000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0117246000, 0.0105450000, 0.0075020000, -0.000204500, -0.019798000, -0.069403900, -0.194469800", \ - "0.0116557000, 0.0104795000, 0.0074785000, -0.000180000, -0.019713100, -0.069278600, -0.194376100", \ - "0.0114583000, 0.0102790000, 0.0073050000, -0.000295600, -0.019760800, -0.069229200, -0.194367600", \ - "0.0110397000, 0.0098805000, 0.0069204000, -0.000643700, -0.019973800, -0.069344400, -0.194306900", \ - "0.0105866000, 0.0094432000, 0.0064783000, -0.001056500, -0.020317800, -0.069510300, -0.194471800", \ - "0.0106348000, 0.0094033000, 0.0063478000, -0.001321900, -0.020928400, -0.070030300, -0.194757100", \ - "0.0116244000, 0.0103409000, 0.0071226000, -0.000753400, -0.020545000, -0.070283700, -0.195047100"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0207514000, 0.0220150000, 0.0251317000, 0.0329797000, 0.0525614000, 0.1017068000, 0.2253362000", \ - "0.0203381000, 0.0216117000, 0.0248133000, 0.0327441000, 0.0524298000, 0.1016309000, 0.2252670000", \ - "0.0198008000, 0.0210289000, 0.0242711000, 0.0322933000, 0.0521084000, 0.1014939000, 0.2251524000", \ - "0.0192216000, 0.0204823000, 0.0237148000, 0.0316453000, 0.0516930000, 0.1012882000, 0.2250516000", \ - "0.0190265000, 0.0202578000, 0.0234192000, 0.0313519000, 0.0511301000, 0.1006054000, 0.2245595000", \ - "0.0198093000, 0.0210298000, 0.0241214000, 0.0317812000, 0.0511323000, 0.1004499000, 0.2242483000", \ - "0.0228059000, 0.0241607000, 0.0262828000, 0.0335234000, 0.0528093000, 0.1019522000, 0.2247203000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0113533000, 0.0101964000, 0.0072022000, -0.000407900, -0.019876000, -0.069401200, -0.194406100", \ - "0.0111617000, 0.0099878000, 0.0070041000, -0.000590600, -0.019978300, -0.069406800, -0.194535600", \ - "0.0109342000, 0.0097558000, 0.0067688000, -0.000843500, -0.020127200, -0.069569600, -0.194534700", \ - "0.0105567000, 0.0093610000, 0.0064025000, -0.001207000, -0.020462800, -0.069670900, -0.194659000", \ - "0.0103427000, 0.0091342000, 0.0060969000, -0.001458400, -0.020811300, -0.070099700, -0.194728600", \ - "0.0109710000, 0.0097170000, 0.0064924000, -0.001427600, -0.020829700, -0.070305900, -0.195056200", \ - "0.0130599000, 0.0117891000, 0.0084939000, 0.0003302000, -0.019730900, -0.069995500, -0.195161100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012602220, 0.0031763210, 0.0080057410, 0.0201780300, 0.0508576100, 0.1281838000"); - values("0.0148303000, 0.0162088000, 0.0195937000, 0.0276614000, 0.0474384000, 0.0965669000, 0.2199467000", \ - "0.0144258000, 0.0158054000, 0.0191747000, 0.0273942000, 0.0472900000, 0.0966360000, 0.2201954000", \ - "0.0140304000, 0.0153941000, 0.0187733000, 0.0268038000, 0.0468748000, 0.0964049000, 0.2203269000", \ - "0.0139241000, 0.0151759000, 0.0182833000, 0.0264606000, 0.0465668000, 0.0958737000, 0.2198503000", \ - "0.0139729000, 0.0151981000, 0.0182765000, 0.0261276000, 0.0457360000, 0.0953882000, 0.2191584000", \ - "0.0151196000, 0.0163520000, 0.0192663000, 0.0268765000, 0.0463172000, 0.0951289000, 0.2190364000", \ - "0.0183671000, 0.0194998000, 0.0225681000, 0.0290819000, 0.0477423000, 0.0973847000, 0.2191902000"); - } - } - max_capacitance : 0.1281840000; - max_transition : 1.5429350000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0721908000, 0.0756196000, 0.0839850000, 0.1039333000, 0.1516038000, 0.2698899000, 0.5654340000", \ - "0.0765108000, 0.0799455000, 0.0883476000, 0.1082872000, 0.1560052000, 0.2742842000, 0.5699921000", \ - "0.0855900000, 0.0889107000, 0.0975145000, 0.1175194000, 0.1653531000, 0.2836511000, 0.5793676000", \ - "0.1030012000, 0.1065131000, 0.1148212000, 0.1348836000, 0.1829766000, 0.3014812000, 0.5966331000", \ - "0.1304678000, 0.1343933000, 0.1442727000, 0.1668754000, 0.2182810000, 0.3376238000, 0.6329128000", \ - "0.1652837000, 0.1711619000, 0.1841208000, 0.2145165000, 0.2779708000, 0.4137266000, 0.7143691000", \ - "0.1804494000, 0.1902117000, 0.2109374000, 0.2567796000, 0.3534155000, 0.5339406000, 0.8867623000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1324391000, 0.1390614000, 0.1546737000, 0.1942027000, 0.2888937000, 0.5232902000, 1.1068512000", \ - "0.1370925000, 0.1434860000, 0.1602874000, 0.1990466000, 0.2945184000, 0.5289078000, 1.1124250000", \ - "0.1498362000, 0.1564588000, 0.1722611000, 0.2119086000, 0.3070933000, 0.5414961000, 1.1260050000", \ - "0.1766460000, 0.1831688000, 0.1994509000, 0.2392076000, 0.3347308000, 0.5701830000, 1.1535495000", \ - "0.2383380000, 0.2450296000, 0.2609650000, 0.2998846000, 0.3954171000, 0.6311185000, 1.2153821000", \ - "0.3539462000, 0.3609861000, 0.3838713000, 0.4300334000, 0.5365510000, 0.7721798000, 1.3575302000", \ - "0.5534511000, 0.5653765000, 0.5950985000, 0.6612368000, 0.8020571000, 1.0908424000, 1.6850581000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0470174000, 0.0510719000, 0.0611819000, 0.0861912000, 0.1494806000, 0.3097756000, 0.7133576000", \ - "0.0469976000, 0.0510640000, 0.0611847000, 0.0861855000, 0.1495298000, 0.3097263000, 0.7133276000", \ - "0.0470185000, 0.0510206000, 0.0611201000, 0.0861543000, 0.1495976000, 0.3096011000, 0.7133028000", \ - "0.0486905000, 0.0524809000, 0.0620789000, 0.0867000000, 0.1493751000, 0.3092191000, 0.7131788000", \ - "0.0593505000, 0.0633381000, 0.0735071000, 0.0973861000, 0.1562967000, 0.3112099000, 0.7131633000", \ - "0.0898720000, 0.0943893000, 0.1049244000, 0.1311577000, 0.1906295000, 0.3367998000, 0.7198924000", \ - "0.1556345000, 0.1618767000, 0.1761958000, 0.2095156000, 0.2792954000, 0.4303090000, 0.7897955000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1071949000, 0.1157104000, 0.1358400000, 0.1872526000, 0.3146478000, 0.6364855000, 1.4455835000", \ - "0.1068515000, 0.1150301000, 0.1359953000, 0.1864559000, 0.3144192000, 0.6367514000, 1.4442344000", \ - "0.1071575000, 0.1152217000, 0.1357811000, 0.1872217000, 0.3147080000, 0.6361126000, 1.4465422000", \ - "0.1067469000, 0.1148381000, 0.1355634000, 0.1871434000, 0.3154493000, 0.6382413000, 1.4450026000", \ - "0.1147630000, 0.1219875000, 0.1414709000, 0.1898938000, 0.3148057000, 0.6366063000, 1.4449870000", \ - "0.1540352000, 0.1610506000, 0.1812103000, 0.2285538000, 0.3396711000, 0.6407406000, 1.4462944000", \ - "0.2351961000, 0.2458658000, 0.2703250000, 0.3237021000, 0.4457379000, 0.7210613000, 1.4617676000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0610343000, 0.0646133000, 0.0729637000, 0.0933506000, 0.1428669000, 0.2651557000, 0.5720946000", \ - "0.0658017000, 0.0693033000, 0.0776974000, 0.0981232000, 0.1478435000, 0.2702703000, 0.5765181000", \ - "0.0744948000, 0.0779235000, 0.0866114000, 0.1070864000, 0.1568811000, 0.2795554000, 0.5869539000", \ - "0.0899101000, 0.0936434000, 0.1024661000, 0.1233076000, 0.1733842000, 0.2962776000, 0.6030574000", \ - "0.1118720000, 0.1163684000, 0.1270706000, 0.1509125000, 0.2052002000, 0.3295393000, 0.6368955000", \ - "0.1333371000, 0.1403222000, 0.1558535000, 0.1883573000, 0.2567532000, 0.3991766000, 0.7124423000", \ - "0.1260610000, 0.1365855000, 0.1605041000, 0.2129894000, 0.3154988000, 0.5048898000, 0.8691879000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1153291000, 0.1220119000, 0.1379745000, 0.1766323000, 0.2724076000, 0.5061131000, 1.0895288000", \ - "0.1191946000, 0.1254778000, 0.1415601000, 0.1806710000, 0.2767311000, 0.5105834000, 1.0943952000", \ - "0.1292220000, 0.1354896000, 0.1523211000, 0.1912764000, 0.2873510000, 0.5215741000, 1.1054393000", \ - "0.1574575000, 0.1641159000, 0.1798684000, 0.2196255000, 0.3152814000, 0.5491018000, 1.1332273000", \ - "0.2259886000, 0.2328958000, 0.2487306000, 0.2873121000, 0.3819471000, 0.6168377000, 1.2012951000", \ - "0.3568711000, 0.3664412000, 0.3887936000, 0.4390504000, 0.5435167000, 0.7745711000, 1.3577010000", \ - "0.5707951000, 0.5848470000, 0.6183741000, 0.6955346000, 0.8506351000, 1.1417566000, 1.7243870000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0390603000, 0.0430002000, 0.0533706000, 0.0794577000, 0.1455497000, 0.3125171000, 0.7345767000", \ - "0.0389875000, 0.0430344000, 0.0533838000, 0.0794331000, 0.1455433000, 0.3121903000, 0.7327869000", \ - "0.0389285000, 0.0429758000, 0.0532620000, 0.0794349000, 0.1455070000, 0.3127762000, 0.7335180000", \ - "0.0416356000, 0.0453038000, 0.0550278000, 0.0802666000, 0.1454162000, 0.3123265000, 0.7328463000", \ - "0.0527383000, 0.0568270000, 0.0666426000, 0.0916849000, 0.1529240000, 0.3142362000, 0.7341019000", \ - "0.0838246000, 0.0881805000, 0.0994430000, 0.1256558000, 0.1873018000, 0.3399243000, 0.7394234000", \ - "0.1495099000, 0.1559000000, 0.1710548000, 0.2049676000, 0.2758238000, 0.4313732000, 0.8098154000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1075446000, 0.1151649000, 0.1356026000, 0.1865601000, 0.3147199000, 0.6363002000, 1.4458932000", \ - "0.1068474000, 0.1149259000, 0.1353505000, 0.1865640000, 0.3147334000, 0.6362105000, 1.4472102000", \ - "0.1068019000, 0.1150218000, 0.1359223000, 0.1865292000, 0.3141988000, 0.6364554000, 1.4447274000", \ - "0.1061842000, 0.1144965000, 0.1354664000, 0.1864387000, 0.3154695000, 0.6363388000, 1.4450218000", \ - "0.1207075000, 0.1276148000, 0.1451718000, 0.1916791000, 0.3151339000, 0.6365770000, 1.4460513000", \ - "0.1734981000, 0.1824869000, 0.2034196000, 0.2520767000, 0.3516108000, 0.6417208000, 1.4467697000", \ - "0.2681624000, 0.2811711000, 0.3116539000, 0.3760552000, 0.5073996000, 0.7542900000, 1.4647712000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0646643000, 0.0677975000, 0.0761605000, 0.0959634000, 0.1441526000, 0.2623688000, 0.5570366000", \ - "0.0685452000, 0.0720418000, 0.0800227000, 0.1001041000, 0.1480913000, 0.2664177000, 0.5611592000", \ - "0.0773253000, 0.0807699000, 0.0891528000, 0.1091980000, 0.1572811000, 0.2755823000, 0.5703466000", \ - "0.0963308000, 0.0999240000, 0.1086720000, 0.1286119000, 0.1770861000, 0.2955988000, 0.5903774000", \ - "0.1277634000, 0.1324310000, 0.1430221000, 0.1670875000, 0.2214701000, 0.3411871000, 0.6366112000", \ - "0.1636897000, 0.1700933000, 0.1862739000, 0.2217987000, 0.2950464000, 0.4384920000, 0.7429783000", \ - "0.1776596000, 0.1878957000, 0.2129965000, 0.2699759000, 0.3830884000, 0.5921243000, 0.9645907000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1049989000, 0.1116489000, 0.1279318000, 0.1674290000, 0.2658086000, 0.5109873000, 1.1272200000", \ - "0.1096317000, 0.1163769000, 0.1329358000, 0.1727966000, 0.2716664000, 0.5170457000, 1.1334442000", \ - "0.1214957000, 0.1283328000, 0.1448602000, 0.1855320000, 0.2847920000, 0.5307174000, 1.1474172000", \ - "0.1491587000, 0.1558712000, 0.1720878000, 0.2127114000, 0.3122042000, 0.5592292000, 1.1774661000", \ - "0.2092100000, 0.2166932000, 0.2348235000, 0.2753693000, 0.3751074000, 0.6232034000, 1.2412802000", \ - "0.3162134000, 0.3261899000, 0.3496919000, 0.4039042000, 0.5192591000, 0.7692916000, 1.3889560000", \ - "0.4981680000, 0.5135341000, 0.5501110000, 0.6308983000, 0.7921860000, 1.0963213000, 1.7283872000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0471359000, 0.0510181000, 0.0610772000, 0.0861858000, 0.1492698000, 0.3096837000, 0.7134683000", \ - "0.0470277000, 0.0510656000, 0.0610161000, 0.0862453000, 0.1494413000, 0.3099518000, 0.7114277000", \ - "0.0469444000, 0.0509268000, 0.0609015000, 0.0862966000, 0.1493842000, 0.3096874000, 0.7138319000", \ - "0.0504060000, 0.0541206000, 0.0634174000, 0.0875235000, 0.1496131000, 0.3095758000, 0.7131891000", \ - "0.0668150000, 0.0707987000, 0.0805088000, 0.1041765000, 0.1602249000, 0.3120609000, 0.7136090000", \ - "0.1042473000, 0.1097614000, 0.1220461000, 0.1498755000, 0.2104884000, 0.3476658000, 0.7208970000", \ - "0.1742685000, 0.1824803000, 0.2003583000, 0.2406122000, 0.3196225000, 0.4750876000, 0.8147328000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1096392000, 0.1182001000, 0.1397958000, 0.1937068000, 0.3280664000, 0.6652328000, 1.5220012000", \ - "0.1096467000, 0.1182000000, 0.1398044000, 0.1937140000, 0.3280913000, 0.6647211000, 1.5216712000", \ - "0.1096383000, 0.1181950000, 0.1397874000, 0.1937349000, 0.3281053000, 0.6649546000, 1.5221046000", \ - "0.1097719000, 0.1182673000, 0.1397827000, 0.1937490000, 0.3281942000, 0.6646534000, 1.5237674000", \ - "0.1241765000, 0.1315867000, 0.1506342000, 0.1997556000, 0.3285489000, 0.6652719000, 1.5217253000", \ - "0.1731517000, 0.1808127000, 0.1991533000, 0.2443702000, 0.3580832000, 0.6691859000, 1.5156786000", \ - "0.2733289000, 0.2821397000, 0.3035937000, 0.3554883000, 0.4751086000, 0.7481627000, 1.5358457000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0536280000, 0.0572201000, 0.0656987000, 0.0863463000, 0.1365783000, 0.2608460000, 0.5713151000", \ - "0.0579811000, 0.0615866000, 0.0702744000, 0.0910428000, 0.1411865000, 0.2653703000, 0.5770158000", \ - "0.0669804000, 0.0704555000, 0.0792002000, 0.1001727000, 0.1506965000, 0.2752317000, 0.5857340000", \ - "0.0842933000, 0.0883910000, 0.0976255000, 0.1192825000, 0.1700982000, 0.2949591000, 0.6070047000", \ - "0.1094103000, 0.1150444000, 0.1276754000, 0.1550064000, 0.2130256000, 0.3400896000, 0.6521739000", \ - "0.1316180000, 0.1398386000, 0.1591235000, 0.2008178000, 0.2818210000, 0.4358951000, 0.7568753000", \ - "0.1220890000, 0.1344413000, 0.1643603000, 0.2291640000, 0.3564969000, 0.5823933000, 0.9762267000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0858707000, 0.0923052000, 0.1083638000, 0.1480625000, 0.2463924000, 0.4915511000, 1.1095510000", \ - "0.0888743000, 0.0957433000, 0.1120254000, 0.1520515000, 0.2509164000, 0.4962994000, 1.1127962000", \ - "0.0989553000, 0.1052258000, 0.1218172000, 0.1624136000, 0.2618052000, 0.5078641000, 1.1245020000", \ - "0.1263564000, 0.1327710000, 0.1496567000, 0.1891108000, 0.2882169000, 0.5354617000, 1.1534668000", \ - "0.1910864000, 0.1989782000, 0.2170568000, 0.2580350000, 0.3567036000, 0.6023652000, 1.2219272000", \ - "0.2993213000, 0.3113697000, 0.3391819000, 0.3987999000, 0.5159230000, 0.7612314000, 1.3769844000", \ - "0.4816387000, 0.4987964000, 0.5405662000, 0.6301369000, 0.8086280000, 1.1286142000, 1.7426216000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0402420000, 0.0442851000, 0.0547313000, 0.0811660000, 0.1481401000, 0.3175678000, 0.7438990000", \ - "0.0402720000, 0.0443516000, 0.0546648000, 0.0810245000, 0.1481187000, 0.3177103000, 0.7441051000", \ - "0.0400820000, 0.0442430000, 0.0546571000, 0.0810806000, 0.1480891000, 0.3175603000, 0.7438936000", \ - "0.0456685000, 0.0492543000, 0.0584482000, 0.0829868000, 0.1480272000, 0.3173809000, 0.7468085000", \ - "0.0630195000, 0.0671311000, 0.0774860000, 0.1020719000, 0.1602837000, 0.3195296000, 0.7439639000", \ - "0.1015869000, 0.1070042000, 0.1203482000, 0.1499506000, 0.2132164000, 0.3573092000, 0.7510818000", \ - "0.1731651000, 0.1810545000, 0.2006849000, 0.2430201000, 0.3265065000, 0.4900000000, 0.8461753000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.1095790000, 0.1181324000, 0.1397331000, 0.1936712000, 0.3278562000, 0.6651278000, 1.5149423000", \ - "0.1095874000, 0.1181420000, 0.1397075000, 0.1937640000, 0.3280751000, 0.6644712000, 1.5211654000", \ - "0.1095402000, 0.1181271000, 0.1397427000, 0.1937147000, 0.3281296000, 0.6647133000, 1.5222739000", \ - "0.1109875000, 0.1190886000, 0.1398999000, 0.1936532000, 0.3281812000, 0.6654798000, 1.5156250000", \ - "0.1369896000, 0.1435182000, 0.1602540000, 0.2051338000, 0.3289771000, 0.6652666000, 1.5203869000", \ - "0.2022155000, 0.2103445000, 0.2295276000, 0.2738971000, 0.3746996000, 0.6716165000, 1.5157797000", \ - "0.3120472000, 0.3235695000, 0.3525626000, 0.4136373000, 0.5379552000, 0.7922008000, 1.5429349000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0501570000, 0.0538015000, 0.0620742000, 0.0823850000, 0.1304828000, 0.2487767000, 0.5435534000", \ - "0.0540888000, 0.0576194000, 0.0658751000, 0.0861379000, 0.1345266000, 0.2529408000, 0.5478785000", \ - "0.0638298000, 0.0673098000, 0.0757092000, 0.0956390000, 0.1441190000, 0.2627181000, 0.5578013000", \ - "0.0873051000, 0.0908411000, 0.0987707000, 0.1182990000, 0.1665769000, 0.2852335000, 0.5804943000", \ - "0.1221422000, 0.1273517000, 0.1396209000, 0.1665763000, 0.2213759000, 0.3398960000, 0.6350895000", \ - "0.1603613000, 0.1681491000, 0.1862547000, 0.2271140000, 0.3090602000, 0.4620823000, 0.7607605000", \ - "0.1844776000, 0.1963264000, 0.2243324000, 0.2858285000, 0.4109559000, 0.6412097000, 1.0425150000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0272881000, 0.0304023000, 0.0377858000, 0.0553727000, 0.0984782000, 0.2060048000, 0.4766860000", \ - "0.0325482000, 0.0355655000, 0.0430467000, 0.0609261000, 0.1043046000, 0.2120370000, 0.4839544000", \ - "0.0461381000, 0.0490649000, 0.0563026000, 0.0737157000, 0.1177508000, 0.2250310000, 0.4957567000", \ - "0.0706167000, 0.0754523000, 0.0858691000, 0.1059988000, 0.1491788000, 0.2572738000, 0.5266053000", \ - "0.1093182000, 0.1170430000, 0.1337536000, 0.1664875000, 0.2236346000, 0.3317384000, 0.6024971000", \ - "0.1713287000, 0.1834276000, 0.2101296000, 0.2626173000, 0.3549838000, 0.5031080000, 0.7743297000", \ - "0.2791124000, 0.2961793000, 0.3357150000, 0.4173196000, 0.5639280000, 0.8042659000, 1.1720489000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0472908000, 0.0511739000, 0.0611898000, 0.0861964000, 0.1496181000, 0.3099153000, 0.7125556000", \ - "0.0472696000, 0.0511346000, 0.0612157000, 0.0861401000, 0.1492992000, 0.3094051000, 0.7140653000", \ - "0.0457943000, 0.0498739000, 0.0601214000, 0.0859903000, 0.1493622000, 0.3097054000, 0.7139646000", \ - "0.0527262000, 0.0561762000, 0.0650439000, 0.0877635000, 0.1488845000, 0.3095504000, 0.7133009000", \ - "0.0735237000, 0.0782385000, 0.0893011000, 0.1145508000, 0.1672677000, 0.3122874000, 0.7124070000", \ - "0.1141972000, 0.1213919000, 0.1373656000, 0.1711898000, 0.2369686000, 0.3687664000, 0.7236775000", \ - "0.1861953000, 0.1969622000, 0.2213967000, 0.2724679000, 0.3675011000, 0.5394201000, 0.8657746000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012602200, 0.0031763200, 0.0080057400, 0.0201780000, 0.0508576000, 0.1281840000"); - values("0.0416539000, 0.0460935000, 0.0572441000, 0.0844696000, 0.1486227000, 0.3030262000, 0.6869553000", \ - "0.0416636000, 0.0461417000, 0.0572570000, 0.0845045000, 0.1486471000, 0.3030743000, 0.6881272000", \ - "0.0447538000, 0.0484637000, 0.0582027000, 0.0845070000, 0.1486453000, 0.3030142000, 0.6880168000", \ - "0.0633606000, 0.0655141000, 0.0716344000, 0.0919015000, 0.1495324000, 0.3030536000, 0.6868561000", \ - "0.1110711000, 0.1127344000, 0.1174610000, 0.1303720000, 0.1718044000, 0.3055714000, 0.6877580000", \ - "0.1863639000, 0.1888592000, 0.1965227000, 0.2156142000, 0.2592841000, 0.3613847000, 0.6931638000", \ - "0.3099758000, 0.3144003000, 0.3258889000, 0.3567989000, 0.4262065000, 0.5548829000, 0.8176908000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o221ai_4") { - leakage_power () { - value : 0.0004130000; - when : "!A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0168845000; - when : "!A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0032993000; - when : "!A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0003314000; - when : "!A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0032880000; - when : "!A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0004925000; - when : "!A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0033356000; - when : "!A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0002716000; - when : "!A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0033389000; - when : "!A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0003256000; - when : "!A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0064977000; - when : "!A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0015247000; - when : "!A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0060087000; - when : "!A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0014954000; - when : "!A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0051254000; - when : "!A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0014736000; - when : "!A1&A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0033389000; - when : "A1&!A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0003256000; - when : "A1&!A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0068375000; - when : "A1&!A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0014995000; - when : "A1&!A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0063485000; - when : "A1&!A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0015336000; - when : "A1&!A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0054658000; - when : "A1&!A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0014761000; - when : "A1&!A2&B1&B2&!C1"; - } - leakage_power () { - value : 0.0080091000; - when : "A1&A2&!B1&!B2&C1"; - } - leakage_power () { - value : 0.0020177000; - when : "A1&A2&!B1&!B2&!C1"; - } - leakage_power () { - value : 0.0050589000; - when : "A1&A2&!B1&B2&C1"; - } - leakage_power () { - value : 0.0015334000; - when : "A1&A2&!B1&B2&!C1"; - } - leakage_power () { - value : 0.0045699000; - when : "A1&A2&B1&!B2&C1"; - } - leakage_power () { - value : 0.0015334000; - when : "A1&A2&B1&!B2&!C1"; - } - leakage_power () { - value : 0.0036882000; - when : "A1&A2&B1&B2&C1"; - } - leakage_power () { - value : 0.0015334000; - when : "A1&A2&B1&B2&!C1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__o221ai"; - cell_leakage_power : 0.0034023540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0091070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086310000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158788000, 0.0158727000, 0.0158587000, 0.0158644000, 0.0158775000, 0.0159078000, 0.0159777000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015892600, -0.015872700, -0.015826700, -0.015822500, -0.015812800, -0.015790500, -0.015739200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0095840000; - } - pin ("A2") { - capacitance : 0.0084800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150382000, 0.0150310000, 0.0150144000, 0.0150191000, 0.0150298000, 0.0150545000, 0.0151114000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015022500, -0.015024000, -0.015027400, -0.015032200, -0.015043000, -0.015068100, -0.015126000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090930000; - } - pin ("B1") { - capacitance : 0.0089150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0085920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161553000, 0.0161425000, 0.0161129000, 0.0161273000, 0.0161605000, 0.0162370000, 0.0164133000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016130100, -0.016123300, -0.016107600, -0.016100400, -0.016083900, -0.016045700, -0.015957800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092390000; - } - pin ("B2") { - capacitance : 0.0081250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0076720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0151883000, 0.0151853000, 0.0151783000, 0.0151909000, 0.0152200000, 0.0152871000, 0.0154416000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015183700, -0.015175400, -0.015156300, -0.015153100, -0.015145900, -0.015129100, -0.015090400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085780000; - } - pin ("C1") { - capacitance : 0.0084170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181816000, 0.0181792000, 0.0181735000, 0.0181731000, 0.0181724000, 0.0181706000, 0.0181665000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.009690000, -0.009698600, -0.009718500, -0.009673700, -0.009570300, -0.009332100, -0.008782900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0085760000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0308118000, 0.0293641000, 0.0255065000, 0.0150083000, -0.014161700, -0.094760700, -0.316913800", \ - "0.0303307000, 0.0288903000, 0.0250401000, 0.0145576000, -0.014579000, -0.095141000, -0.317442700", \ - "0.0297215000, 0.0283284000, 0.0244647000, 0.0140698000, -0.015045600, -0.095618400, -0.317790800", \ - "0.0290045000, 0.0276169000, 0.0238104000, 0.0133784000, -0.015561700, -0.095917100, -0.318020600", \ - "0.0284385000, 0.0270939000, 0.0233000000, 0.0130023000, -0.015966500, -0.096202000, -0.318116000", \ - "0.0286542000, 0.0272093000, 0.0233272000, 0.0126416000, -0.016885700, -0.096820500, -0.318661200", \ - "0.0297381000, 0.0282444000, 0.0243470000, 0.0136902000, -0.015866900, -0.097106500, -0.318739600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0627689000, 0.0641523000, 0.0680326000, 0.0789087000, 0.1084904000, 0.1892970000, 0.4099191000", \ - "0.0622598000, 0.0636943000, 0.0675495000, 0.0784410000, 0.1080415000, 0.1887738000, 0.4092136000", \ - "0.0614429000, 0.0628737000, 0.0670408000, 0.0777190000, 0.1075130000, 0.1884710000, 0.4090131000", \ - "0.0607837000, 0.0622474000, 0.0662259000, 0.0771667000, 0.1069296000, 0.1879895000, 0.4085586000", \ - "0.0600738000, 0.0615455000, 0.0654486000, 0.0762874000, 0.1061567000, 0.1871572000, 0.4083585000", \ - "0.0599445000, 0.0613652000, 0.0652318000, 0.0763228000, 0.1059201000, 0.1870730000, 0.4074641000", \ - "0.0601139000, 0.0616327000, 0.0655916000, 0.0768236000, 0.1064749000, 0.1874652000, 0.4086071000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0238279000, 0.0224647000, 0.0186882000, 0.0082241000, -0.020981800, -0.101671900, -0.324060600", \ - "0.0237587000, 0.0224107000, 0.0186454000, 0.0082458000, -0.020827800, -0.101405400, -0.323787000", \ - "0.0233170000, 0.0220187000, 0.0182918000, 0.0079759000, -0.020874600, -0.101309300, -0.323575500", \ - "0.0225195000, 0.0211563000, 0.0174688000, 0.0072427000, -0.021410500, -0.101537200, -0.323633000", \ - "0.0216188000, 0.0202168000, 0.0165523000, 0.0063325000, -0.022294800, -0.102114500, -0.323814100", \ - "0.0216861000, 0.0203087000, 0.0164849000, 0.0059877000, -0.023248100, -0.103114500, -0.324492500", \ - "0.0227216000, 0.0214093000, 0.0173173000, 0.0064952000, -0.022772900, -0.103774700, -0.325076900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0540372000, 0.0554860000, 0.0594094000, 0.0702050000, 0.0998178000, 0.1806332000, 0.4014361000", \ - "0.0535928000, 0.0550302000, 0.0588140000, 0.0696418000, 0.0993093000, 0.1800338000, 0.4006631000", \ - "0.0525308000, 0.0539575000, 0.0581289000, 0.0688806000, 0.0987104000, 0.1796031000, 0.4003307000", \ - "0.0518367000, 0.0531843000, 0.0573228000, 0.0679701000, 0.0979019000, 0.1791955000, 0.3998281000", \ - "0.0510101000, 0.0524345000, 0.0563825000, 0.0671785000, 0.0969777000, 0.1782785000, 0.3991643000", \ - "0.0519920000, 0.0533720000, 0.0572757000, 0.0679171000, 0.0973193000, 0.1781470000, 0.3987486000", \ - "0.0565482000, 0.0578122000, 0.0635848000, 0.0728890000, 0.1019912000, 0.1796064000, 0.3993596000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0313086000, 0.0298946000, 0.0261305000, 0.0155485000, -0.013636400, -0.094268600, -0.316513400", \ - "0.0308642000, 0.0294721000, 0.0256912000, 0.0151481000, -0.013980700, -0.094628200, -0.316791200", \ - "0.0303100000, 0.0289515000, 0.0251125000, 0.0146332000, -0.014431700, -0.094953300, -0.317132100", \ - "0.0296366000, 0.0282501000, 0.0244545000, 0.0140025000, -0.014979300, -0.095342400, -0.317408400", \ - "0.0289949000, 0.0276438000, 0.0238669000, 0.0134617000, -0.015242100, -0.095518100, -0.317472300", \ - "0.0288090000, 0.0274106000, 0.0235775000, 0.0127569000, -0.016187700, -0.096330200, -0.317963900", \ - "0.0304893000, 0.0290305000, 0.0251224000, 0.0144284000, -0.015107100, -0.096361500, -0.318160200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0486270000, 0.0500547000, 0.0540033000, 0.0647110000, 0.0939362000, 0.1741229000, 0.3939558000", \ - "0.0480106000, 0.0494718000, 0.0534686000, 0.0642648000, 0.0936654000, 0.1738842000, 0.3939337000", \ - "0.0469696000, 0.0484853000, 0.0525564000, 0.0634964000, 0.0931548000, 0.1736043000, 0.3935924000", \ - "0.0459301000, 0.0473975000, 0.0514317000, 0.0623844000, 0.0923325000, 0.1730633000, 0.3932871000", \ - "0.0451664000, 0.0466059000, 0.0505833000, 0.0614150000, 0.0910906000, 0.1720349000, 0.3927751000", \ - "0.0448341000, 0.0462647000, 0.0502533000, 0.0609396000, 0.0907444000, 0.1714481000, 0.3920045000", \ - "0.0444193000, 0.0458018000, 0.0500757000, 0.0612816000, 0.0907012000, 0.1715764000, 0.3924932000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0242969000, 0.0229570000, 0.0191458000, 0.0086125000, -0.020529900, -0.101303700, -0.323704100", \ - "0.0242232000, 0.0228718000, 0.0190868000, 0.0086677000, -0.020390800, -0.101033100, -0.323418600", \ - "0.0237880000, 0.0224582000, 0.0187818000, 0.0083959000, -0.020499600, -0.100964000, -0.323309800", \ - "0.0229835000, 0.0216960000, 0.0179919000, 0.0076855000, -0.020991000, -0.101144900, -0.323293000", \ - "0.0220258000, 0.0207369000, 0.0171296000, 0.0068694000, -0.021713700, -0.101612300, -0.323384900", \ - "0.0222155000, 0.0208172000, 0.0170138000, 0.0063001000, -0.022906300, -0.102672800, -0.323993600", \ - "0.0239851000, 0.0224975000, 0.0185280000, 0.0077144000, -0.021937600, -0.103023800, -0.324548100"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0401043000, 0.0415468000, 0.0454609000, 0.0561854000, 0.0855142000, 0.1655927000, 0.3854266000", \ - "0.0393880000, 0.0408516000, 0.0448385000, 0.0557062000, 0.0851374000, 0.1653539000, 0.3851068000", \ - "0.0382197000, 0.0397512000, 0.0438061000, 0.0547993000, 0.0845798000, 0.1650219000, 0.3851052000", \ - "0.0372198000, 0.0386871000, 0.0428326000, 0.0537023000, 0.0835002000, 0.1644386000, 0.3846954000", \ - "0.0370726000, 0.0385254000, 0.0423927000, 0.0532029000, 0.0826237000, 0.1633901000, 0.3841423000", \ - "0.0379346000, 0.0393368000, 0.0431674000, 0.0536682000, 0.0827443000, 0.1630157000, 0.3834245000", \ - "0.0426782000, 0.0439892000, 0.0476075000, 0.0576846000, 0.0860270000, 0.1650252000, 0.3818799000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0243095000, 0.0229616000, 0.0191876000, 0.0087637000, -0.020360000, -0.100843100, -0.323109000", \ - "0.0238471000, 0.0225129000, 0.0188160000, 0.0083832000, -0.020528000, -0.100986300, -0.323178600", \ - "0.0233858000, 0.0220334000, 0.0182911000, 0.0079485000, -0.020863500, -0.101238700, -0.323234200", \ - "0.0227484000, 0.0213385000, 0.0176059000, 0.0072625000, -0.021465400, -0.101536900, -0.323430700", \ - "0.0225031000, 0.0211044000, 0.0172982000, 0.0071480000, -0.021904500, -0.102006200, -0.323616300", \ - "0.0234028000, 0.0220419000, 0.0179435000, 0.0073046000, -0.022004600, -0.102252600, -0.324053500", \ - "0.0273393000, 0.0258246000, 0.0217339000, 0.0107500000, -0.018742000, -0.101759400, -0.324190200"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013748080, 0.0037801970, 0.0103940900, 0.0285797800, 0.0785834500, 0.2160744000"); - values("0.0290511000, 0.0306559000, 0.0349800000, 0.0461552000, 0.0757117000, 0.1558071000, 0.3757882000", \ - "0.0283173000, 0.0299266000, 0.0342656000, 0.0456135000, 0.0755649000, 0.1558722000, 0.3758302000", \ - "0.0275635000, 0.0291731000, 0.0335264000, 0.0449278000, 0.0749936000, 0.1558126000, 0.3760113000", \ - "0.0270137000, 0.0285399000, 0.0327518000, 0.0440560000, 0.0742610000, 0.1552079000, 0.3759987000", \ - "0.0272966000, 0.0287280000, 0.0324972000, 0.0433707000, 0.0733065000, 0.1537109000, 0.3746453000", \ - "0.0297139000, 0.0310789000, 0.0346701000, 0.0448797000, 0.0740734000, 0.1552954000, 0.3746415000", \ - "0.0354622000, 0.0366547000, 0.0392046000, 0.0487917000, 0.0771750000, 0.1578802000, 0.3778743000"); - } - } - max_capacitance : 0.2160740000; - max_transition : 1.5474020000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0832690000, 0.0853258000, 0.0916175000, 0.1087885000, 0.1524408000, 0.2691491000, 0.5848709000", \ - "0.0873068000, 0.0894162000, 0.0957651000, 0.1127866000, 0.1565514000, 0.2734311000, 0.5889364000", \ - "0.0956254000, 0.0978497000, 0.1040684000, 0.1213357000, 0.1652208000, 0.2816811000, 0.5976138000", \ - "0.1107007000, 0.1131252000, 0.1195346000, 0.1365670000, 0.1806070000, 0.2974472000, 0.6133099000", \ - "0.1348088000, 0.1375560000, 0.1443268000, 0.1634761000, 0.2101088000, 0.3282054000, 0.6448438000", \ - "0.1654506000, 0.1687263000, 0.1779723000, 0.2017026000, 0.2580334000, 0.3904305000, 0.7130845000", \ - "0.1747399000, 0.1801882000, 0.1947007000, 0.2306105000, 0.3131361000, 0.4855285000, 0.8561848000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1471695000, 0.1517173000, 0.1634059000, 0.1956383000, 0.2803825000, 0.5053360000, 1.1155112000", \ - "0.1521087000, 0.1565081000, 0.1683937000, 0.2005709000, 0.2853491000, 0.5103248000, 1.1209426000", \ - "0.1643060000, 0.1684594000, 0.1806325000, 0.2128775000, 0.2979965000, 0.5233735000, 1.1335863000", \ - "0.1902641000, 0.1947747000, 0.2076491000, 0.2393322000, 0.3243720000, 0.5509178000, 1.1615926000", \ - "0.2511128000, 0.2554515000, 0.2674380000, 0.2995367000, 0.3848112000, 0.6114443000, 1.2218810000", \ - "0.3686884000, 0.3744312000, 0.3891022000, 0.4273849000, 0.5208980000, 0.7492800000, 1.3612320000", \ - "0.5750557000, 0.5830916000, 0.6037563000, 0.6553511000, 0.7819060000, 1.0572242000, 1.6819786000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0554388000, 0.0582792000, 0.0663357000, 0.0886435000, 0.1490756000, 0.3154045000, 0.7743525000", \ - "0.0554466000, 0.0582568000, 0.0663198000, 0.0885970000, 0.1489056000, 0.3154219000, 0.7741903000", \ - "0.0553951000, 0.0582921000, 0.0662809000, 0.0884875000, 0.1490552000, 0.3155903000, 0.7742371000", \ - "0.0566025000, 0.0594071000, 0.0673204000, 0.0889767000, 0.1487144000, 0.3152996000, 0.7744313000", \ - "0.0658418000, 0.0687715000, 0.0765356000, 0.0982097000, 0.1557610000, 0.3172009000, 0.7737491000", \ - "0.0930282000, 0.0963267000, 0.1045988000, 0.1265704000, 0.1848850000, 0.3405776000, 0.7807912000", \ - "0.1577103000, 0.1621063000, 0.1730763000, 0.1999762000, 0.2643182000, 0.4210685000, 0.8400808000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1278002000, 0.1328323000, 0.1472755000, 0.1879330000, 0.2975186000, 0.6010338000, 1.4396353000", \ - "0.1276530000, 0.1329790000, 0.1472826000, 0.1879254000, 0.2976213000, 0.6003110000, 1.4379073000", \ - "0.1274308000, 0.1327083000, 0.1478557000, 0.1871813000, 0.2975157000, 0.6006386000, 1.4388577000", \ - "0.1272916000, 0.1326343000, 0.1473913000, 0.1873659000, 0.2976666000, 0.6008936000, 1.4371553000", \ - "0.1334240000, 0.1385545000, 0.1521461000, 0.1897301000, 0.2971168000, 0.6003167000, 1.4369806000", \ - "0.1688967000, 0.1743691000, 0.1885228000, 0.2259923000, 0.3214196000, 0.6066929000, 1.4379876000", \ - "0.2483223000, 0.2551591000, 0.2726109000, 0.3146851000, 0.4218978000, 0.6855170000, 1.4527483000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0689043000, 0.0713327000, 0.0777867000, 0.0949854000, 0.1396836000, 0.2589557000, 0.5837311000", \ - "0.0734634000, 0.0759167000, 0.0823791000, 0.0996944000, 0.1445650000, 0.2640527000, 0.5888466000", \ - "0.0816740000, 0.0842950000, 0.0907473000, 0.1080734000, 0.1533024000, 0.2731366000, 0.5982882000", \ - "0.0959800000, 0.0984513000, 0.1051553000, 0.1227636000, 0.1680704000, 0.2883979000, 0.6142907000", \ - "0.1160241000, 0.1185336000, 0.1267135000, 0.1465396000, 0.1954090000, 0.3172988000, 0.6436439000", \ - "0.1348433000, 0.1390640000, 0.1500705000, 0.1769363000, 0.2375566000, 0.3759764000, 0.7084545000", \ - "0.1190347000, 0.1275689000, 0.1429270000, 0.1849309000, 0.2769415000, 0.4610386000, 0.8442589000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1286565000, 0.1331320000, 0.1452431000, 0.1771480000, 0.2617661000, 0.4868697000, 1.0967923000", \ - "0.1313918000, 0.1358121000, 0.1479255000, 0.1802002000, 0.2652644000, 0.4906899000, 1.1004260000", \ - "0.1420470000, 0.1462511000, 0.1581851000, 0.1912579000, 0.2756345000, 0.5017268000, 1.1118750000", \ - "0.1691990000, 0.1733496000, 0.1851757000, 0.2179900000, 0.3029129000, 0.5290148000, 1.1397415000", \ - "0.2382456000, 0.2424909000, 0.2543681000, 0.2860411000, 0.3702158000, 0.5969756000, 1.2083198000", \ - "0.3771906000, 0.3832945000, 0.3994876000, 0.4389273000, 0.5318018000, 0.7563932000, 1.3663568000", \ - "0.6066940000, 0.6155257000, 0.6412609000, 0.7007968000, 0.8397441000, 1.1223157000, 1.7336961000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0458635000, 0.0487878000, 0.0568674000, 0.0792501000, 0.1412590000, 0.3126132000, 0.7851891000", \ - "0.0458348000, 0.0487933000, 0.0568441000, 0.0792840000, 0.1412377000, 0.3129715000, 0.7851592000", \ - "0.0457826000, 0.0487364000, 0.0568680000, 0.0792647000, 0.1412598000, 0.3126157000, 0.7855266000", \ - "0.0479867000, 0.0507186000, 0.0584443000, 0.0801972000, 0.1412038000, 0.3127569000, 0.7861995000", \ - "0.0581464000, 0.0609773000, 0.0687208000, 0.0903692000, 0.1495841000, 0.3147664000, 0.7852580000", \ - "0.0884183000, 0.0914729000, 0.0997908000, 0.1222463000, 0.1807401000, 0.3391998000, 0.7907270000", \ - "0.1548088000, 0.1592341000, 0.1699918000, 0.1980671000, 0.2638514000, 0.4220906000, 0.8512057000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1275445000, 0.1328892000, 0.1474167000, 0.1874869000, 0.2969010000, 0.6001846000, 1.4365076000", \ - "0.1283195000, 0.1337356000, 0.1473004000, 0.1871948000, 0.2969190000, 0.6001185000, 1.4358014000", \ - "0.1276968000, 0.1328439000, 0.1480045000, 0.1875904000, 0.2971038000, 0.6001705000, 1.4393466000", \ - "0.1264948000, 0.1316032000, 0.1471388000, 0.1871338000, 0.2969444000, 0.6009177000, 1.4408330000", \ - "0.1370604000, 0.1416493000, 0.1546120000, 0.1904426000, 0.2972444000, 0.6005227000, 1.4440467000", \ - "0.1910950000, 0.1966640000, 0.2109725000, 0.2470813000, 0.3348315000, 0.6063773000, 1.4414151000", \ - "0.2878849000, 0.2971680000, 0.3188103000, 0.3704790000, 0.4851681000, 0.7245459000, 1.4549272000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0747985000, 0.0771504000, 0.0837868000, 0.1003722000, 0.1444022000, 0.2610900000, 0.5767118000", \ - "0.0787306000, 0.0810691000, 0.0875418000, 0.1043709000, 0.1482616000, 0.2650872000, 0.5805690000", \ - "0.0872731000, 0.0898176000, 0.0960415000, 0.1130735000, 0.1570128000, 0.2737130000, 0.5895455000", \ - "0.1057178000, 0.1081550000, 0.1145927000, 0.1315358000, 0.1756626000, 0.2923329000, 0.6084648000", \ - "0.1372174000, 0.1402211000, 0.1481570000, 0.1678651000, 0.2173066000, 0.3356684000, 0.6528310000", \ - "0.1741508000, 0.1787834000, 0.1904656000, 0.2194682000, 0.2861947000, 0.4277862000, 0.7546750000", \ - "0.1887658000, 0.1950047000, 0.2140401000, 0.2586835000, 0.3607744000, 0.5674272000, 0.9660323000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1168802000, 0.1212523000, 0.1333214000, 0.1660720000, 0.2527863000, 0.4892650000, 1.1369914000", \ - "0.1211985000, 0.1257057000, 0.1380794000, 0.1708880000, 0.2583141000, 0.4948540000, 1.1412036000", \ - "0.1327742000, 0.1373093000, 0.1498329000, 0.1830785000, 0.2711774000, 0.5083061000, 1.1549502000", \ - "0.1597166000, 0.1643541000, 0.1765604000, 0.2097881000, 0.2984453000, 0.5363860000, 1.1836933000", \ - "0.2191447000, 0.2242148000, 0.2376191000, 0.2708736000, 0.3592666000, 0.5979983000, 1.2463061000", \ - "0.3265268000, 0.3330921000, 0.3504787000, 0.3941009000, 0.4972941000, 0.7396556000, 1.3893174000", \ - "0.5135932000, 0.5238058000, 0.5494574000, 0.6137485000, 0.7547756000, 1.0577462000, 1.7210414000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0553161000, 0.0582909000, 0.0663505000, 0.0885082000, 0.1490539000, 0.3156028000, 0.7738136000", \ - "0.0553143000, 0.0582489000, 0.0664660000, 0.0885687000, 0.1489456000, 0.3156248000, 0.7741381000", \ - "0.0552992000, 0.0582683000, 0.0664112000, 0.0885391000, 0.1490155000, 0.3154204000, 0.7743421000", \ - "0.0578958000, 0.0607161000, 0.0684714000, 0.0898559000, 0.1488886000, 0.3153497000, 0.7743352000", \ - "0.0732798000, 0.0762908000, 0.0843142000, 0.1055918000, 0.1604772000, 0.3176047000, 0.7745833000", \ - "0.1118823000, 0.1155161000, 0.1248907000, 0.1487755000, 0.2072215000, 0.3547926000, 0.7808543000", \ - "0.1852810000, 0.1904397000, 0.2038762000, 0.2372228000, 0.3119332000, 0.4756354000, 0.8721512000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1286397000, 0.1342879000, 0.1496658000, 0.1925580000, 0.3101339000, 0.6333475000, 1.5249567000", \ - "0.1286365000, 0.1342361000, 0.1497063000, 0.1924542000, 0.3102189000, 0.6336669000, 1.5213266000", \ - "0.1286462000, 0.1342208000, 0.1497031000, 0.1924490000, 0.3101990000, 0.6336919000, 1.5280168000", \ - "0.1286626000, 0.1342364000, 0.1497335000, 0.1924918000, 0.3103076000, 0.6334767000, 1.5273122000", \ - "0.1408765000, 0.1458647000, 0.1597188000, 0.1988563000, 0.3111781000, 0.6331305000, 1.5220640000", \ - "0.1874338000, 0.1923226000, 0.2058655000, 0.2420733000, 0.3412411000, 0.6402515000, 1.5281604000", \ - "0.2854148000, 0.2924208000, 0.3074430000, 0.3483293000, 0.4518626000, 0.7216961000, 1.5425601000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0609584000, 0.0635144000, 0.0698261000, 0.0868871000, 0.1317483000, 0.2515591000, 0.5771367000", \ - "0.0653449000, 0.0677839000, 0.0741621000, 0.0912926000, 0.1363886000, 0.2562127000, 0.5816439000", \ - "0.0736368000, 0.0760733000, 0.0828381000, 0.1000671000, 0.1451073000, 0.2647242000, 0.5902829000", \ - "0.0898258000, 0.0926760000, 0.0996523000, 0.1174356000, 0.1628283000, 0.2834575000, 0.6088660000", \ - "0.1140838000, 0.1175930000, 0.1268131000, 0.1490224000, 0.2012344000, 0.3245931000, 0.6520333000", \ - "0.1349681000, 0.1399780000, 0.1538905000, 0.1869780000, 0.2601397000, 0.4097407000, 0.7487167000", \ - "0.1201316000, 0.1282574000, 0.1494340000, 0.2015756000, 0.3143304000, 0.5351371000, 0.9484937000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0953339000, 0.0998545000, 0.1120816000, 0.1447843000, 0.2315983000, 0.4678248000, 1.1141555000", \ - "0.0984351000, 0.1029853000, 0.1154120000, 0.1483145000, 0.2355668000, 0.4722304000, 1.1201859000", \ - "0.1077357000, 0.1123397000, 0.1250141000, 0.1581202000, 0.2461939000, 0.4831820000, 1.1298706000", \ - "0.1348607000, 0.1392802000, 0.1515292000, 0.1842093000, 0.2726735000, 0.5109013000, 1.1583648000", \ - "0.2010180000, 0.2060473000, 0.2189949000, 0.2523438000, 0.3389031000, 0.5767258000, 1.2247361000", \ - "0.3147120000, 0.3223765000, 0.3424253000, 0.3912934000, 0.4980723000, 0.7360847000, 1.3848376000", \ - "0.5068777000, 0.5180605000, 0.5473405000, 0.6199216000, 0.7802311000, 1.0983798000, 1.7455328000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0463820000, 0.0493298000, 0.0575720000, 0.0802083000, 0.1426539000, 0.3150736000, 0.7906703000", \ - "0.0463723000, 0.0493603000, 0.0575436000, 0.0801710000, 0.1425358000, 0.3152284000, 0.7903548000", \ - "0.0462495000, 0.0492507000, 0.0574842000, 0.0801648000, 0.1425484000, 0.3151328000, 0.7898991000", \ - "0.0509823000, 0.0536858000, 0.0608376000, 0.0823482000, 0.1428431000, 0.3151398000, 0.7902103000", \ - "0.0668940000, 0.0700226000, 0.0783233000, 0.0999272000, 0.1558835000, 0.3182138000, 0.7903249000", \ - "0.1056522000, 0.1093897000, 0.1191302000, 0.1446264000, 0.2042316000, 0.3554294000, 0.7977949000", \ - "0.1776386000, 0.1833576000, 0.1978747000, 0.2319366000, 0.3088796000, 0.4765774000, 0.8873045000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.1285714000, 0.1341706000, 0.1496562000, 0.1925406000, 0.3102086000, 0.6335152000, 1.5273858000", \ - "0.1285594000, 0.1341655000, 0.1497070000, 0.1925324000, 0.3101247000, 0.6332704000, 1.5241439000", \ - "0.1285551000, 0.1341457000, 0.1496474000, 0.1924010000, 0.3102731000, 0.6333294000, 1.5274435000", \ - "0.1290104000, 0.1343118000, 0.1493705000, 0.1923300000, 0.3101591000, 0.6335005000, 1.5227676000", \ - "0.1532106000, 0.1574912000, 0.1695382000, 0.2041651000, 0.3123366000, 0.6338894000, 1.5234940000", \ - "0.2191355000, 0.2243402000, 0.2381891000, 0.2731789000, 0.3615453000, 0.6427548000, 1.5276557000", \ - "0.3317630000, 0.3392126000, 0.3589724000, 0.4083670000, 0.5204511000, 0.7684595000, 1.5474020000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0592321000, 0.0617435000, 0.0682600000, 0.0849221000, 0.1289229000, 0.2456763000, 0.5615964000", \ - "0.0628792000, 0.0653765000, 0.0719681000, 0.0887791000, 0.1329808000, 0.2497059000, 0.5656816000", \ - "0.0720809000, 0.0745609000, 0.0809460000, 0.0979635000, 0.1426047000, 0.2596312000, 0.5753969000", \ - "0.0956173000, 0.0976405000, 0.1039641000, 0.1205158000, 0.1647030000, 0.2822353000, 0.5983925000", \ - "0.1312353000, 0.1346920000, 0.1438418000, 0.1666531000, 0.2169830000, 0.3339629000, 0.6504808000", \ - "0.1701829000, 0.1753275000, 0.1882554000, 0.2215008000, 0.2969300000, 0.4500986000, 0.7716112000", \ - "0.1909435000, 0.1985666000, 0.2185577000, 0.2688584000, 0.3818728000, 0.6143710000, 1.0459906000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0295199000, 0.0315622000, 0.0370919000, 0.0512972000, 0.0882906000, 0.1889636000, 0.4640737000", \ - "0.0347738000, 0.0368416000, 0.0424075000, 0.0568460000, 0.0943505000, 0.1953017000, 0.4707119000", \ - "0.0483651000, 0.0503397000, 0.0557494000, 0.0700419000, 0.1078918000, 0.2092645000, 0.4848009000", \ - "0.0739755000, 0.0772045000, 0.0849276000, 0.1018170000, 0.1394268000, 0.2409986000, 0.5164905000", \ - "0.1150804000, 0.1200461000, 0.1322129000, 0.1595504000, 0.2121096000, 0.3153625000, 0.5925148000", \ - "0.1824137000, 0.1901590000, 0.2090194000, 0.2516945000, 0.3374893000, 0.4837119000, 0.7627322000", \ - "0.3015405000, 0.3125661000, 0.3398593000, 0.4050982000, 0.5390782000, 0.7761845000, 1.1646754000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0554404000, 0.0583677000, 0.0664903000, 0.0885160000, 0.1489584000, 0.3151775000, 0.7741017000", \ - "0.0554208000, 0.0583080000, 0.0664284000, 0.0885653000, 0.1490907000, 0.3154339000, 0.7741853000", \ - "0.0542125000, 0.0573573000, 0.0657906000, 0.0883167000, 0.1490558000, 0.3155952000, 0.7740035000", \ - "0.0589887000, 0.0614692000, 0.0689188000, 0.0896326000, 0.1484068000, 0.3154076000, 0.7744305000", \ - "0.0792098000, 0.0826836000, 0.0918542000, 0.1157761000, 0.1672067000, 0.3181168000, 0.7741024000", \ - "0.1208004000, 0.1258883000, 0.1382667000, 0.1687514000, 0.2343645000, 0.3790979000, 0.7843114000", \ - "0.1930578000, 0.2001639000, 0.2186176000, 0.2615827000, 0.3548604000, 0.5361518000, 0.9223379000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013748100, 0.0037802000, 0.0103941000, 0.0285798000, 0.0785834000, 0.2160740000"); - values("0.0552115000, 0.0578877000, 0.0654830000, 0.0862616000, 0.1424013000, 0.2914965000, 0.6975610000", \ - "0.0552125000, 0.0578628000, 0.0654412000, 0.0863602000, 0.1424554000, 0.2915988000, 0.6983953000", \ - "0.0576114000, 0.0598614000, 0.0664028000, 0.0863513000, 0.1424379000, 0.2916117000, 0.6982183000", \ - "0.0739956000, 0.0753704000, 0.0800713000, 0.0950172000, 0.1440060000, 0.2915920000, 0.6972652000", \ - "0.1186654000, 0.1197701000, 0.1233232000, 0.1335117000, 0.1690259000, 0.2957422000, 0.6972992000", \ - "0.1940449000, 0.1955961000, 0.2004544000, 0.2153526000, 0.2544318000, 0.3539451000, 0.7049775000", \ - "0.3199856000, 0.3223097000, 0.3293271000, 0.3522491000, 0.4103477000, 0.5406531000, 0.8285743000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22a_1") { - leakage_power () { - value : 0.0026328000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0152674000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0026430000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0026276000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0017675000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0028082000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0011522000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0015364000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0022609000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0028082000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0016456000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0020298000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0009991000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0028082000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0003838000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0007680000; - when : "A1&A2&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o22a"; - cell_leakage_power : 0.0027586670; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040057000, 0.0040013000, 0.0039913000, 0.0039899000, 0.0039865000, 0.0039788000, 0.0039611000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003985100, -0.003983800, -0.003980700, -0.003981700, -0.003984000, -0.003989200, -0.004001200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024540000; - } - pin ("A2") { - capacitance : 0.0024230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041013000, 0.0040977000, 0.0040891000, 0.0040893000, 0.0040897000, 0.0040906000, 0.0040928000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004076400, -0.004077100, -0.004078600, -0.004077600, -0.004075100, -0.004069400, -0.004056300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025770000; - } - pin ("B1") { - capacitance : 0.0024050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048797000, 0.0048715000, 0.0048528000, 0.0048539000, 0.0048566000, 0.0048628000, 0.0048771000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001463400, -0.001469300, -0.001482800, -0.001465500, -0.001425700, -0.001333900, -0.001122500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024900000; - } - pin ("B2") { - capacitance : 0.0023640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045773000, 0.0045760000, 0.0045730000, 0.0045725000, 0.0045714000, 0.0045688000, 0.0045628000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001177300, -0.001183500, -0.001197800, -0.001180100, -0.001139400, -0.001045500, -0.000829100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024920000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A1&B2) | (A2&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0171775000, 0.0162554000, 0.0137001000, 0.0057646000, -0.017223700, -0.078812700, -0.240967800", \ - "0.0171198000, 0.0162135000, 0.0136395000, 0.0056829000, -0.017304100, -0.078925500, -0.241176600", \ - "0.0168937000, 0.0159428000, 0.0133951000, 0.0054584000, -0.017513200, -0.079116300, -0.241233600", \ - "0.0167249000, 0.0157705000, 0.0132207000, 0.0052730000, -0.017669500, -0.079282700, -0.241462800", \ - "0.0166378000, 0.0156786000, 0.0131014000, 0.0051167000, -0.017875700, -0.079423900, -0.241574800", \ - "0.0175441000, 0.0162429000, 0.0128300000, 0.0048876000, -0.018016400, -0.079541400, -0.241643200", \ - "0.0193086000, 0.0179841000, 0.0145470000, 0.0056312000, -0.017821100, -0.079091300, -0.241178700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0145140000, 0.0159635000, 0.0196146000, 0.0288552000, 0.0525441000, 0.1144809000, 0.2760794000", \ - "0.0144202000, 0.0158690000, 0.0195356000, 0.0287550000, 0.0524464000, 0.1144155000, 0.2759690000", \ - "0.0142959000, 0.0157373000, 0.0194159000, 0.0286290000, 0.0523318000, 0.1142880000, 0.2758531000", \ - "0.0141725000, 0.0156074000, 0.0192396000, 0.0284455000, 0.0520961000, 0.1137627000, 0.2744654000", \ - "0.0140031000, 0.0154509000, 0.0190813000, 0.0282559000, 0.0520835000, 0.1140320000, 0.2755426000", \ - "0.0142622000, 0.0156353000, 0.0191520000, 0.0280803000, 0.0518317000, 0.1136155000, 0.2743036000", \ - "0.0149611000, 0.0162643000, 0.0197338000, 0.0288352000, 0.0524246000, 0.1141369000, 0.2751724000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0149741000, 0.0140445000, 0.0115118000, 0.0035781000, -0.019413800, -0.080995800, -0.243156400", \ - "0.0147937000, 0.0139787000, 0.0113877000, 0.0033984000, -0.019558500, -0.081173400, -0.243335100", \ - "0.0145590000, 0.0136188000, 0.0110655000, 0.0031261000, -0.019846200, -0.081453800, -0.243631400", \ - "0.0143820000, 0.0134560000, 0.0108949000, 0.0029149000, -0.020059100, -0.081658000, -0.243775000", \ - "0.0143815000, 0.0134431000, 0.0108831000, 0.0029126000, -0.020084400, -0.081647100, -0.243757300", \ - "0.0152484000, 0.0139257000, 0.0107929000, 0.0030495000, -0.019850400, -0.081370600, -0.243467300", \ - "0.0180882000, 0.0167237000, 0.0132960000, 0.0043020000, -0.019184400, -0.080461100, -0.242473800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0134520000, 0.0148961000, 0.0185371000, 0.0277545000, 0.0513639000, 0.1128266000, 0.2734096000", \ - "0.0134230000, 0.0148601000, 0.0185178000, 0.0277299000, 0.0513497000, 0.1125776000, 0.2743998000", \ - "0.0132737000, 0.0147136000, 0.0183730000, 0.0275805000, 0.0512038000, 0.1124727000, 0.2742680000", \ - "0.0129919000, 0.0144191000, 0.0180407000, 0.0272401000, 0.0508883000, 0.1123745000, 0.2727686000", \ - "0.0128210000, 0.0141411000, 0.0177411000, 0.0268272000, 0.0504802000, 0.1125677000, 0.2729131000", \ - "0.0128234000, 0.0141653000, 0.0176630000, 0.0266789000, 0.0502988000, 0.1112837000, 0.2727867000", \ - "0.0133898000, 0.0146800000, 0.0181672000, 0.0272177000, 0.0509015000, 0.1125361000, 0.2718012000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0105681000, 0.0100198000, 0.0078320000, 0.0003214000, -0.022596500, -0.084473700, -0.246863700", \ - "0.0103773000, 0.0098296000, 0.0076132000, 0.0001356000, -0.022759400, -0.084652000, -0.247032700", \ - "0.0101679000, 0.0095819000, 0.0073506000, -0.000142100, -0.023034500, -0.084906000, -0.247260500", \ - "0.0098601000, 0.0092877000, 0.0071006000, -0.000422700, -0.023293700, -0.085143800, -0.247527400", \ - "0.0096222000, 0.0090252000, 0.0068346000, -0.000661100, -0.023474600, -0.085286800, -0.247611400", \ - "0.0114223000, 0.0101634000, 0.0067757000, -0.001127800, -0.023646500, -0.085368900, -0.247680800", \ - "0.0134038000, 0.0121103000, 0.0086773000, -0.000176800, -0.023634400, -0.085117700, -0.247350000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0121344000, 0.0135663000, 0.0172108000, 0.0264764000, 0.0500794000, 0.1116405000, 0.2726663000", \ - "0.0120058000, 0.0134468000, 0.0171203000, 0.0263390000, 0.0500363000, 0.1120149000, 0.2735806000", \ - "0.0118700000, 0.0133124000, 0.0169836000, 0.0262116000, 0.0498893000, 0.1113262000, 0.2731783000", \ - "0.0116407000, 0.0130890000, 0.0167203000, 0.0259231000, 0.0496021000, 0.1110953000, 0.2718506000", \ - "0.0113712000, 0.0128062000, 0.0164294000, 0.0255792000, 0.0492574000, 0.1113315000, 0.2727982000", \ - "0.0117241000, 0.0130834000, 0.0165286000, 0.0254160000, 0.0491884000, 0.1102968000, 0.2711776000", \ - "0.0124391000, 0.0137305000, 0.0171936000, 0.0262134000, 0.0498780000, 0.1116210000, 0.2709195000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0085134000, 0.0078540000, 0.0057119000, -0.001781400, -0.024649200, -0.086444500, -0.248811500", \ - "0.0082399000, 0.0076524000, 0.0055284000, -0.002006400, -0.024853100, -0.086645600, -0.248989600", \ - "0.0079708000, 0.0073599000, 0.0051804000, -0.002307000, -0.025128900, -0.086935900, -0.249262300", \ - "0.0076730000, 0.0070402000, 0.0048800000, -0.002598900, -0.025424100, -0.087192900, -0.249521000", \ - "0.0076720000, 0.0070834000, 0.0048815000, -0.002628800, -0.025389100, -0.087124300, -0.249412000", \ - "0.0098961000, 0.0085776000, 0.0052170000, -0.002764300, -0.025189300, -0.086877000, -0.249141100", \ - "0.0129270000, 0.0115070000, 0.0081262000, -0.000748200, -0.024267200, -0.085703300, -0.247955200"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013104490, 0.0034345540, 0.0090016190, 0.0235923300, 0.0618331000, 0.1620583000"); - values("0.0106310000, 0.0120577000, 0.0157270000, 0.0249372000, 0.0485318000, 0.1104517000, 0.2715896000", \ - "0.0106117000, 0.0120577000, 0.0156985000, 0.0249111000, 0.0487468000, 0.1099628000, 0.2707903000", \ - "0.0104617000, 0.0119033000, 0.0155467000, 0.0247525000, 0.0483377000, 0.1099042000, 0.2705747000", \ - "0.0102507000, 0.0116141000, 0.0152027000, 0.0244067000, 0.0482754000, 0.1095495000, 0.2704013000", \ - "0.0100265000, 0.0113256000, 0.0148833000, 0.0238844000, 0.0475229000, 0.1092128000, 0.2709924000", \ - "0.0101656000, 0.0114937000, 0.0149206000, 0.0239425000, 0.0476369000, 0.1086159000, 0.2709355000", \ - "0.0111334000, 0.0125177000, 0.0159269000, 0.0249850000, 0.0485121000, 0.1103816000, 0.2694081000"); - } - } - max_capacitance : 0.1620580000; - max_transition : 1.5016480000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1718140000, 0.1789377000, 0.1936602000, 0.2227273000, 0.2816895000, 0.4183289000, 0.7677886000", \ - "0.1768923000, 0.1840757000, 0.1988471000, 0.2275215000, 0.2867001000, 0.4231153000, 0.7727605000", \ - "0.1889993000, 0.1961480000, 0.2109409000, 0.2399924000, 0.2990103000, 0.4353675000, 0.7856555000", \ - "0.2148247000, 0.2219684000, 0.2367410000, 0.2657633000, 0.3244612000, 0.4609246000, 0.8106030000", \ - "0.2731313000, 0.2802643000, 0.2949938000, 0.3239385000, 0.3830771000, 0.5196453000, 0.8706387000", \ - "0.3849189000, 0.3930515000, 0.4093134000, 0.4405834000, 0.5021409000, 0.6397746000, 0.9903228000", \ - "0.5726606000, 0.5827104000, 0.6023953000, 0.6385639000, 0.7056892000, 0.8470346000, 1.1978248000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0995235000, 0.1069236000, 0.1235772000, 0.1620172000, 0.2577060000, 0.5054884000, 1.1492134000", \ - "0.1041456000, 0.1115258000, 0.1282212000, 0.1667016000, 0.2621742000, 0.5099891000, 1.1533968000", \ - "0.1141708000, 0.1215571000, 0.1382771000, 0.1767525000, 0.2721914000, 0.5199688000, 1.1633057000", \ - "0.1348628000, 0.1422157000, 0.1587984000, 0.1971680000, 0.2929360000, 0.5396311000, 1.1831341000", \ - "0.1736404000, 0.1814297000, 0.1984970000, 0.2372254000, 0.3330924000, 0.5799238000, 1.2249729000", \ - "0.2274730000, 0.2363962000, 0.2550781000, 0.2950640000, 0.3909230000, 0.6380074000, 1.2856033000", \ - "0.2785359000, 0.2901495000, 0.3128726000, 0.3566321000, 0.4536248000, 0.7011422000, 1.3452124000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0256753000, 0.0303023000, 0.0411878000, 0.0667880000, 0.1293884000, 0.3014093000, 0.7705498000", \ - "0.0256604000, 0.0308337000, 0.0413195000, 0.0669227000, 0.1291729000, 0.3006569000, 0.7667471000", \ - "0.0255665000, 0.0302422000, 0.0415618000, 0.0669457000, 0.1293135000, 0.3009464000, 0.7707946000", \ - "0.0255760000, 0.0302541000, 0.0415812000, 0.0669678000, 0.1296859000, 0.3009726000, 0.7729363000", \ - "0.0258036000, 0.0304062000, 0.0412898000, 0.0668038000, 0.1293323000, 0.3004062000, 0.7677203000", \ - "0.0308400000, 0.0357280000, 0.0468619000, 0.0724012000, 0.1330750000, 0.3028173000, 0.7674719000", \ - "0.0411291000, 0.0468584000, 0.0583895000, 0.0847935000, 0.1445464000, 0.3072545000, 0.7655186000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0239694000, 0.0311656000, 0.0493158000, 0.0981488000, 0.2306137000, 0.5812311000, 1.4992400000", \ - "0.0239273000, 0.0311131000, 0.0494008000, 0.0981855000, 0.2303505000, 0.5800977000, 1.4988714000", \ - "0.0239186000, 0.0310667000, 0.0493963000, 0.0981665000, 0.2301888000, 0.5798197000, 1.4983046000", \ - "0.0239808000, 0.0310685000, 0.0493371000, 0.0981774000, 0.2307214000, 0.5794112000, 1.4979733000", \ - "0.0259032000, 0.0331057000, 0.0509471000, 0.0988119000, 0.2300965000, 0.5811928000, 1.4991633000", \ - "0.0311168000, 0.0383226000, 0.0553340000, 0.1013100000, 0.2311916000, 0.5792422000, 1.4969022000", \ - "0.0426254000, 0.0501396000, 0.0665084000, 0.1087328000, 0.2332184000, 0.5828216000, 1.4945937000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1604344000, 0.1675651000, 0.1824409000, 0.2114893000, 0.2704898000, 0.4068369000, 0.7568462000", \ - "0.1641298000, 0.1711819000, 0.1859721000, 0.2151609000, 0.2740265000, 0.4105571000, 0.7610387000", \ - "0.1742827000, 0.1814658000, 0.1961931000, 0.2252489000, 0.2840794000, 0.4205631000, 0.7699216000", \ - "0.2025886000, 0.2097734000, 0.2244494000, 0.2534312000, 0.3125530000, 0.4489807000, 0.7989266000", \ - "0.2710948000, 0.2782024000, 0.2929040000, 0.3216408000, 0.3805188000, 0.5170376000, 0.8677816000", \ - "0.4075067000, 0.4159531000, 0.4323265000, 0.4632042000, 0.5243696000, 0.6622333000, 1.0119720000", \ - "0.6250778000, 0.6363115000, 0.6577132000, 0.6945941000, 0.7600059000, 0.9004509000, 1.2521839000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0886362000, 0.0958673000, 0.1122253000, 0.1503009000, 0.2453709000, 0.4915079000, 1.1358200000", \ - "0.0934502000, 0.1006802000, 0.1170533000, 0.1551724000, 0.2501093000, 0.4968229000, 1.1424502000", \ - "0.1030359000, 0.1102622000, 0.1266796000, 0.1647816000, 0.2597493000, 0.5064894000, 1.1521367000", \ - "0.1224164000, 0.1296465000, 0.1459287000, 0.1839408000, 0.2791381000, 0.5251957000, 1.1702860000", \ - "0.1555221000, 0.1632406000, 0.1802698000, 0.2187995000, 0.3143003000, 0.5607051000, 1.2052614000", \ - "0.1960649000, 0.2050480000, 0.2237839000, 0.2637649000, 0.3596148000, 0.6063030000, 1.2523310000", \ - "0.2201034000, 0.2320660000, 0.2558089000, 0.3002475000, 0.3972252000, 0.6440017000, 1.2885013000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0254146000, 0.0302117000, 0.0412820000, 0.0668838000, 0.1293778000, 0.3007281000, 0.7697986000", \ - "0.0254168000, 0.0308394000, 0.0413363000, 0.0668501000, 0.1297023000, 0.3016725000, 0.7684737000", \ - "0.0255149000, 0.0304028000, 0.0411496000, 0.0669205000, 0.1296535000, 0.3012237000, 0.7737997000", \ - "0.0255642000, 0.0307451000, 0.0411322000, 0.0669285000, 0.1293994000, 0.3005018000, 0.7701291000", \ - "0.0255231000, 0.0303381000, 0.0418559000, 0.0672765000, 0.1295320000, 0.3011332000, 0.7663304000", \ - "0.0334408000, 0.0380860000, 0.0480728000, 0.0725193000, 0.1329123000, 0.3022577000, 0.7733205000", \ - "0.0488362000, 0.0538044000, 0.0649061000, 0.0865823000, 0.1438738000, 0.3076970000, 0.7664999000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0230633000, 0.0300624000, 0.0483160000, 0.0972986000, 0.2300379000, 0.5797890000, 1.4988466000", \ - "0.0231119000, 0.0301041000, 0.0483186000, 0.0970672000, 0.2292704000, 0.5810806000, 1.4995235000", \ - "0.0231187000, 0.0301228000, 0.0483442000, 0.0970957000, 0.2295243000, 0.5810374000, 1.4993677000", \ - "0.0233930000, 0.0303092000, 0.0484454000, 0.0973062000, 0.2300309000, 0.5802951000, 1.4999670000", \ - "0.0257780000, 0.0328833000, 0.0506689000, 0.0982624000, 0.2299444000, 0.5808382000, 1.4935406000", \ - "0.0322279000, 0.0388542000, 0.0558411000, 0.1013023000, 0.2311997000, 0.5785009000, 1.4940924000", \ - "0.0447347000, 0.0521139000, 0.0695665000, 0.1103786000, 0.2329383000, 0.5824543000, 1.4939198000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1368976000, 0.1447872000, 0.1619892000, 0.1961067000, 0.2615390000, 0.4019207000, 0.7516804000", \ - "0.1416826000, 0.1495785000, 0.1665696000, 0.2009314000, 0.2663249000, 0.4068388000, 0.7564141000", \ - "0.1534789000, 0.1614425000, 0.1784556000, 0.2127927000, 0.2781792000, 0.4186926000, 0.7685562000", \ - "0.1806773000, 0.1885420000, 0.2056517000, 0.2400047000, 0.3054015000, 0.4459326000, 0.7958454000", \ - "0.2409064000, 0.2487877000, 0.2662548000, 0.3010086000, 0.3668827000, 0.5075521000, 0.8573714000", \ - "0.3482013000, 0.3575691000, 0.3772791000, 0.4163999000, 0.4871710000, 0.6310063000, 0.9811201000", \ - "0.5291556000, 0.5407925000, 0.5651282000, 0.6125410000, 0.6946996000, 0.8469612000, 1.2001068000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0906589000, 0.0980567000, 0.1147310000, 0.1532040000, 0.2488121000, 0.4958039000, 1.1399942000", \ - "0.0947488000, 0.1021294000, 0.1188268000, 0.1573081000, 0.2528345000, 0.5006563000, 1.1441431000", \ - "0.1048394000, 0.1122362000, 0.1289218000, 0.1673915000, 0.2627604000, 0.5097290000, 1.1557212000", \ - "0.1291475000, 0.1365805000, 0.1531626000, 0.1914956000, 0.2871857000, 0.5340725000, 1.1790974000", \ - "0.1706274000, 0.1782235000, 0.1952945000, 0.2340210000, 0.3299410000, 0.5781357000, 1.2247289000", \ - "0.2210381000, 0.2295733000, 0.2473837000, 0.2866412000, 0.3827051000, 0.6306089000, 1.2768655000", \ - "0.2608735000, 0.2720324000, 0.2939721000, 0.3356912000, 0.4316913000, 0.6794629000, 1.3246005000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0264796000, 0.0327386000, 0.0472797000, 0.0771010000, 0.1403614000, 0.3053427000, 0.7664736000", \ - "0.0264268000, 0.0327444000, 0.0476217000, 0.0771392000, 0.1405728000, 0.3057271000, 0.7717936000", \ - "0.0263447000, 0.0327775000, 0.0475188000, 0.0771323000, 0.1406460000, 0.3063559000, 0.7673046000", \ - "0.0265506000, 0.0328033000, 0.0473756000, 0.0770723000, 0.1407070000, 0.3062993000, 0.7670434000", \ - "0.0278663000, 0.0345478000, 0.0488665000, 0.0780109000, 0.1409945000, 0.3063746000, 0.7685998000", \ - "0.0340995000, 0.0407882000, 0.0566558000, 0.0870528000, 0.1484362000, 0.3100125000, 0.7688637000", \ - "0.0464182000, 0.0547275000, 0.0728177000, 0.1070727000, 0.1697539000, 0.3232024000, 0.7676352000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0239133000, 0.0311130000, 0.0492938000, 0.0980996000, 0.2305981000, 0.5801178000, 1.4943445000", \ - "0.0239251000, 0.0311056000, 0.0493820000, 0.0982009000, 0.2303435000, 0.5803308000, 1.4990545000", \ - "0.0239996000, 0.0310736000, 0.0492987000, 0.0979338000, 0.2302448000, 0.5815340000, 1.5003833000", \ - "0.0241942000, 0.0311309000, 0.0492700000, 0.0982091000, 0.2307546000, 0.5812825000, 1.4964163000", \ - "0.0259853000, 0.0329500000, 0.0510496000, 0.0993559000, 0.2306866000, 0.5799672000, 1.4988629000", \ - "0.0312671000, 0.0379816000, 0.0546171000, 0.1008663000, 0.2320296000, 0.5787651000, 1.4995508000", \ - "0.0434541000, 0.0498529000, 0.0651469000, 0.1068941000, 0.2325151000, 0.5842344000, 1.4945104000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.1207362000, 0.1285985000, 0.1458758000, 0.1800065000, 0.2456139000, 0.3861313000, 0.7361118000", \ - "0.1241903000, 0.1320334000, 0.1491676000, 0.1835653000, 0.2491371000, 0.3896602000, 0.7397014000", \ - "0.1343681000, 0.1421092000, 0.1592561000, 0.1937036000, 0.2592268000, 0.3998638000, 0.7498249000", \ - "0.1623484000, 0.1701932000, 0.1872407000, 0.2216276000, 0.2872820000, 0.4278478000, 0.7779885000", \ - "0.2285608000, 0.2367833000, 0.2541388000, 0.2891051000, 0.3547952000, 0.4957881000, 0.8456691000", \ - "0.3412524000, 0.3514025000, 0.3724128000, 0.4128277000, 0.4840249000, 0.6286960000, 0.9787100000", \ - "0.5244412000, 0.5371912000, 0.5640067000, 0.6144696000, 0.6999037000, 0.8525550000, 1.2061656000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0777093000, 0.0849066000, 0.1013570000, 0.1394671000, 0.2343219000, 0.4811798000, 1.1270054000", \ - "0.0820331000, 0.0892573000, 0.1056008000, 0.1436427000, 0.2390935000, 0.4853659000, 1.1291956000", \ - "0.0921246000, 0.0993663000, 0.1157175000, 0.1537571000, 0.2491780000, 0.4953429000, 1.1386035000", \ - "0.1147011000, 0.1218575000, 0.1381254000, 0.1760477000, 0.2715050000, 0.5180638000, 1.1621927000", \ - "0.1475363000, 0.1550230000, 0.1718099000, 0.2101417000, 0.3058057000, 0.5526233000, 1.1979987000", \ - "0.1826777000, 0.1915185000, 0.2092910000, 0.2481736000, 0.3439055000, 0.5916046000, 1.2372019000", \ - "0.1958259000, 0.2078163000, 0.2299908000, 0.2724063000, 0.3676793000, 0.6155852000, 1.2601317000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0263479000, 0.0329504000, 0.0473048000, 0.0771975000, 0.1405204000, 0.3055646000, 0.7691074000", \ - "0.0262795000, 0.0327848000, 0.0473531000, 0.0771386000, 0.1404068000, 0.3062783000, 0.7679268000", \ - "0.0262892000, 0.0328482000, 0.0473530000, 0.0770574000, 0.1404366000, 0.3062993000, 0.7674631000", \ - "0.0263110000, 0.0328350000, 0.0474450000, 0.0771629000, 0.1404653000, 0.3059742000, 0.7690769000", \ - "0.0288673000, 0.0351147000, 0.0492394000, 0.0784847000, 0.1413471000, 0.3060142000, 0.7688340000", \ - "0.0388961000, 0.0463936000, 0.0614757000, 0.0914092000, 0.1509420000, 0.3110363000, 0.7690502000", \ - "0.0538849000, 0.0624567000, 0.0817140000, 0.1185749000, 0.1760376000, 0.3233616000, 0.7691777000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013104500, 0.0034345500, 0.0090016200, 0.0235923000, 0.0618331000, 0.1620580000"); - values("0.0230064000, 0.0301373000, 0.0483699000, 0.0970087000, 0.2295580000, 0.5810287000, 1.4988657000", \ - "0.0230013000, 0.0300766000, 0.0482506000, 0.0971238000, 0.2301964000, 0.5787086000, 1.4941378000", \ - "0.0229959000, 0.0300946000, 0.0483202000, 0.0972707000, 0.2300631000, 0.5790415000, 1.4974006000", \ - "0.0233787000, 0.0305750000, 0.0487037000, 0.0972778000, 0.2300819000, 0.5792868000, 1.4934639000", \ - "0.0258968000, 0.0327068000, 0.0504922000, 0.0987791000, 0.2301225000, 0.5801460000, 1.5001216000", \ - "0.0322807000, 0.0386180000, 0.0550979000, 0.1006904000, 0.2313966000, 0.5783547000, 1.5016483000", \ - "0.0452979000, 0.0522869000, 0.0674757000, 0.1080127000, 0.2321012000, 0.5829503000, 1.4939118000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22a_2") { - leakage_power () { - value : 0.0033643000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0027789000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0033722000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0033587000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0020102000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0035378000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0014442000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0017816000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0023893000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0035374000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0018233000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0021608000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0012855000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0035379000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0007196000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0010570000; - when : "A1&A2&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o22a"; - cell_leakage_power : 0.0023849210; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040175000, 0.0040093000, 0.0039905000, 0.0039917000, 0.0039945000, 0.0040009000, 0.0040156000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003976700, -0.003976000, -0.003974500, -0.003973200, -0.003970100, -0.003963000, -0.003946700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024570000; - } - pin ("A2") { - capacitance : 0.0023550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021970000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039455000, 0.0039481000, 0.0039539000, 0.0039547000, 0.0039564000, 0.0039603000, 0.0039692000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003943800, -0.003942400, -0.003939200, -0.003940000, -0.003941800, -0.003945900, -0.003955400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025130000; - } - pin ("B1") { - capacitance : 0.0023890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048515000, 0.0048468000, 0.0048359000, 0.0048375000, 0.0048410000, 0.0048491000, 0.0048678000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001438300, -0.001444600, -0.001459100, -0.001440800, -0.001398700, -0.001301600, -0.001077900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024770000; - } - pin ("B2") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045679000, 0.0045668000, 0.0045644000, 0.0045637000, 0.0045624000, 0.0045592000, 0.0045518000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001150300, -0.001157600, -0.001174500, -0.001157000, -0.001116600, -0.001023600, -0.000809000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A1&B2) | (A2&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0200288000, 0.0184603000, 0.0147810000, 0.0037515000, -0.032650000, -0.143180700, -0.467193000", \ - "0.0197434000, 0.0184104000, 0.0147171000, 0.0036797000, -0.032725000, -0.143333600, -0.467269200", \ - "0.0198227000, 0.0182390000, 0.0145771000, 0.0035034000, -0.032914400, -0.143499800, -0.467395700", \ - "0.0193773000, 0.0179479000, 0.0143325000, 0.0032725000, -0.033156100, -0.143719000, -0.467566300", \ - "0.0192715000, 0.0178194000, 0.0141544000, 0.0030125000, -0.033404800, -0.143874300, -0.467754400", \ - "0.0188868000, 0.0173104000, 0.0136703000, 0.0028360000, -0.033612200, -0.144085900, -0.467912100", \ - "0.0238218000, 0.0221526000, 0.0175237000, 0.0044622000, -0.033490100, -0.143945500, -0.467633900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0191170000, 0.0207949000, 0.0256576000, 0.0392422000, 0.0775154000, 0.1880488000, 0.5089308000", \ - "0.0190246000, 0.0207190000, 0.0254922000, 0.0390780000, 0.0774836000, 0.1880238000, 0.5089103000", \ - "0.0188862000, 0.0205862000, 0.0253820000, 0.0389705000, 0.0773209000, 0.1880409000, 0.5085032000", \ - "0.0186961000, 0.0203896000, 0.0252522000, 0.0388363000, 0.0771311000, 0.1877791000, 0.5082823000", \ - "0.0187022000, 0.0203852000, 0.0251993000, 0.0386254000, 0.0769017000, 0.1882135000, 0.5105046000", \ - "0.0191676000, 0.0207187000, 0.0253227000, 0.0384649000, 0.0767620000, 0.1866616000, 0.5078253000", \ - "0.0199361000, 0.0214186000, 0.0258547000, 0.0390314000, 0.0773859000, 0.1882271000, 0.5071810000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0179569000, 0.0164002000, 0.0126610000, 0.0016569000, -0.034728300, -0.145262400, -0.469239500", \ - "0.0175440000, 0.0161290000, 0.0124204000, 0.0013705000, -0.035040100, -0.145582300, -0.469495800", \ - "0.0173621000, 0.0158727000, 0.0122393000, 0.0011714000, -0.035254700, -0.145799900, -0.469686300", \ - "0.0171047000, 0.0156656000, 0.0120274000, 0.0010075000, -0.035447900, -0.146037400, -0.469875900", \ - "0.0170605000, 0.0156149000, 0.0119300000, 0.0007587000, -0.035576800, -0.146089200, -0.469998400", \ - "0.0171969000, 0.0156552000, 0.0118707000, 0.0007795000, -0.035389600, -0.145848600, -0.469606200", \ - "0.0230264000, 0.0213038000, 0.0165668000, 0.0033450000, -0.034832500, -0.145258700, -0.468919800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0178672000, 0.0195357000, 0.0244221000, 0.0379883000, 0.0763277000, 0.1866829000, 0.5093413000", \ - "0.0178684000, 0.0195296000, 0.0243771000, 0.0379738000, 0.0763046000, 0.1868050000, 0.5097234000", \ - "0.0177755000, 0.0194331000, 0.0242771000, 0.0378749000, 0.0761955000, 0.1864805000, 0.5093272000", \ - "0.0175829000, 0.0192954000, 0.0241242000, 0.0376357000, 0.0759312000, 0.1864693000, 0.5093169000", \ - "0.0173195000, 0.0190011000, 0.0237464000, 0.0371988000, 0.0754867000, 0.1860959000, 0.5091057000", \ - "0.0177379000, 0.0193080000, 0.0239666000, 0.0370950000, 0.0750752000, 0.1849424000, 0.5064698000", \ - "0.0183883000, 0.0198656000, 0.0243293000, 0.0375659000, 0.0758631000, 0.1864435000, 0.5047391000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0127020000, 0.0115348000, 0.0084228000, -0.002075000, -0.038030600, -0.148822500, -0.473059700", \ - "0.0125630000, 0.0113945000, 0.0082491000, -0.002194400, -0.038179900, -0.148948400, -0.473182900", \ - "0.0123817000, 0.0110673000, 0.0079961000, -0.002405700, -0.038415500, -0.149184200, -0.473427800", \ - "0.0120253000, 0.0107624000, 0.0076848000, -0.002831100, -0.038758400, -0.149490100, -0.473698600", \ - "0.0118891000, 0.0106382000, 0.0074756000, -0.003114800, -0.039047200, -0.149720400, -0.473889600", \ - "0.0130484000, 0.0114722000, 0.0069223000, -0.003593600, -0.039350000, -0.149874300, -0.473983200", \ - "0.0180006000, 0.0163224000, 0.0116891000, -0.001296600, -0.039120300, -0.149737100, -0.473789700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0166545000, 0.0183726000, 0.0232280000, 0.0368112000, 0.0750784000, 0.1856646000, 0.5065500000", \ - "0.0165834000, 0.0182730000, 0.0230665000, 0.0366919000, 0.0750114000, 0.1855803000, 0.5062372000", \ - "0.0164160000, 0.0180970000, 0.0228988000, 0.0365196000, 0.0748762000, 0.1863397000, 0.5071308000", \ - "0.0162266000, 0.0179161000, 0.0227775000, 0.0363332000, 0.0746661000, 0.1851311000, 0.5061692000", \ - "0.0160934000, 0.0177113000, 0.0224457000, 0.0358872000, 0.0741471000, 0.1848690000, 0.5075618000", \ - "0.0165732000, 0.0181486000, 0.0227394000, 0.0358001000, 0.0738087000, 0.1840656000, 0.5073415000", \ - "0.0175001000, 0.0190025000, 0.0233988000, 0.0365494000, 0.0746103000, 0.1855175000, 0.5043241000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0105941000, 0.0093122000, 0.0062373000, -0.004119600, -0.040091300, -0.150822400, -0.474996400", \ - "0.0103909000, 0.0091076000, 0.0060325000, -0.004450800, -0.040297900, -0.150994300, -0.475154700", \ - "0.0101865000, 0.0088732000, 0.0057717000, -0.004698300, -0.040580700, -0.151262700, -0.475421800", \ - "0.0098562000, 0.0085671000, 0.0054718000, -0.005020900, -0.040915000, -0.151542800, -0.475693200", \ - "0.0098495000, 0.0085480000, 0.0054174000, -0.005202000, -0.041073100, -0.151675300, -0.475733400", \ - "0.0114121000, 0.0097845000, 0.0052226000, -0.005268000, -0.040915900, -0.151474000, -0.475391300", \ - "0.0175547000, 0.0157799000, 0.0110931000, -0.002178400, -0.039931600, -0.149906400, -0.474591300"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014560060, 0.0042399090, 0.0123466700, 0.0359536600, 0.1046975000, 0.3048805000"); - values("0.0152199000, 0.0169128000, 0.0217041000, 0.0352921000, 0.0736295000, 0.1840712000, 0.5045661000", \ - "0.0151969000, 0.0168892000, 0.0216822000, 0.0352846000, 0.0735955000, 0.1841000000, 0.5072317000", \ - "0.0150638000, 0.0167783000, 0.0216319000, 0.0352179000, 0.0735494000, 0.1838131000, 0.5070412000", \ - "0.0149254000, 0.0166113000, 0.0214544000, 0.0349578000, 0.0732303000, 0.1835678000, 0.5045366000", \ - "0.0145505000, 0.0162265000, 0.0210149000, 0.0341921000, 0.0724384000, 0.1830591000, 0.5064254000", \ - "0.0152963000, 0.0168373000, 0.0214450000, 0.0344452000, 0.0722493000, 0.1821870000, 0.5048944000", \ - "0.0163227000, 0.0178023000, 0.0222356000, 0.0355661000, 0.0734834000, 0.1845028000, 0.5052935000"); - } - } - max_capacitance : 0.3048800000; - max_transition : 1.5045490000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1996883000, 0.2063336000, 0.2206666000, 0.2484706000, 0.3031800000, 0.4268831000, 0.7601779000", \ - "0.2050613000, 0.2116743000, 0.2259822000, 0.2538019000, 0.3085003000, 0.4320299000, 0.7659121000", \ - "0.2172341000, 0.2238681000, 0.2381493000, 0.2660353000, 0.3210693000, 0.4445129000, 0.7778425000", \ - "0.2432133000, 0.2498070000, 0.2640843000, 0.2920412000, 0.3470806000, 0.4702965000, 0.8035047000", \ - "0.3022087000, 0.3088559000, 0.3230894000, 0.3510318000, 0.4058454000, 0.5295862000, 0.8631013000", \ - "0.4225656000, 0.4302016000, 0.4456758000, 0.4758164000, 0.5329281000, 0.6576573000, 0.9916609000", \ - "0.6291411000, 0.6380700000, 0.6570481000, 0.6921587000, 0.7560935000, 0.8874526000, 1.2231257000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1095076000, 0.1156404000, 0.1300228000, 0.1630385000, 0.2467351000, 0.4830677000, 1.1661460000", \ - "0.1141897000, 0.1203685000, 0.1346596000, 0.1676828000, 0.2514735000, 0.4873445000, 1.1706590000", \ - "0.1242462000, 0.1303532000, 0.1447677000, 0.1778086000, 0.2616519000, 0.4977486000, 1.1819838000", \ - "0.1450289000, 0.1512054000, 0.1655728000, 0.1985738000, 0.2824091000, 0.5181576000, 1.2023095000", \ - "0.1864814000, 0.1928827000, 0.2078264000, 0.2411755000, 0.3250007000, 0.5627886000, 1.2476165000", \ - "0.2470417000, 0.2544897000, 0.2712367000, 0.3069611000, 0.3916893000, 0.6282132000, 1.3131116000", \ - "0.3103280000, 0.3202459000, 0.3413419000, 0.3825597000, 0.4706519000, 0.7077885000, 1.3911465000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0282382000, 0.0320730000, 0.0404723000, 0.0604390000, 0.1105898000, 0.2542398000, 0.6968090000", \ - "0.0281852000, 0.0320517000, 0.0403376000, 0.0603490000, 0.1106151000, 0.2541556000, 0.6991746000", \ - "0.0279632000, 0.0320436000, 0.0403376000, 0.0603965000, 0.1107581000, 0.2542633000, 0.6971932000", \ - "0.0279827000, 0.0317262000, 0.0403571000, 0.0602078000, 0.1104229000, 0.2537645000, 0.6962894000", \ - "0.0278825000, 0.0320364000, 0.0403092000, 0.0603819000, 0.1104476000, 0.2541704000, 0.6956192000", \ - "0.0326381000, 0.0364986000, 0.0454006000, 0.0650538000, 0.1134192000, 0.2550272000, 0.6993934000", \ - "0.0434947000, 0.0482614000, 0.0579350000, 0.0783350000, 0.1282780000, 0.2650914000, 0.6977166000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0211590000, 0.0262854000, 0.0396279000, 0.0767312000, 0.1884413000, 0.5245263000, 1.5005032000", \ - "0.0212436000, 0.0263131000, 0.0397423000, 0.0767465000, 0.1886286000, 0.5243414000, 1.5005128000", \ - "0.0212009000, 0.0262811000, 0.0397608000, 0.0767410000, 0.1886876000, 0.5231888000, 1.4984854000", \ - "0.0212300000, 0.0262896000, 0.0396426000, 0.0767038000, 0.1886621000, 0.5242487000, 1.4975516000", \ - "0.0230903000, 0.0281586000, 0.0414661000, 0.0776748000, 0.1888897000, 0.5237174000, 1.5045492000", \ - "0.0282948000, 0.0339601000, 0.0471205000, 0.0821123000, 0.1905381000, 0.5232182000, 1.5025010000", \ - "0.0392658000, 0.0454730000, 0.0600601000, 0.0931155000, 0.1953819000, 0.5254290000, 1.4984598000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1870406000, 0.1936342000, 0.2079671000, 0.2357595000, 0.2903012000, 0.4138106000, 0.7474529000", \ - "0.1907960000, 0.1974033000, 0.2116283000, 0.2396052000, 0.2946474000, 0.4178780000, 0.7517345000", \ - "0.2011957000, 0.2077838000, 0.2221123000, 0.2499745000, 0.3050167000, 0.4284184000, 0.7616129000", \ - "0.2292359000, 0.2358722000, 0.2502176000, 0.2777898000, 0.3325128000, 0.4561731000, 0.7899392000", \ - "0.2980042000, 0.3045825000, 0.3187891000, 0.3466966000, 0.4013693000, 0.5250378000, 0.8590907000", \ - "0.4441046000, 0.4517665000, 0.4679694000, 0.4977678000, 0.5548361000, 0.6791908000, 1.0133280000", \ - "0.6826510000, 0.6928119000, 0.7141664000, 0.7525206000, 0.8176144000, 0.9474458000, 1.2830966000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0977887000, 0.1037519000, 0.1178214000, 0.1503391000, 0.2334513000, 0.4692091000, 1.1557099000", \ - "0.1027061000, 0.1086514000, 0.1227184000, 0.1552484000, 0.2384279000, 0.4744448000, 1.1578374000", \ - "0.1124744000, 0.1184321000, 0.1325055000, 0.1650397000, 0.2482574000, 0.4855510000, 1.1708788000", \ - "0.1323537000, 0.1383810000, 0.1523537000, 0.1847301000, 0.2678604000, 0.5039407000, 1.1905181000", \ - "0.1688118000, 0.1752365000, 0.1899069000, 0.2231266000, 0.3067077000, 0.5428589000, 1.2266576000", \ - "0.2171911000, 0.2249367000, 0.2417930000, 0.2773200000, 0.3619444000, 0.5979944000, 1.2831216000", \ - "0.2549129000, 0.2652119000, 0.2872040000, 0.3292493000, 0.4175282000, 0.6538697000, 1.3372782000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0282929000, 0.0320989000, 0.0403627000, 0.0601636000, 0.1109341000, 0.2542628000, 0.6987671000", \ - "0.0280177000, 0.0319075000, 0.0402427000, 0.0605929000, 0.1104260000, 0.2539433000, 0.6964552000", \ - "0.0278930000, 0.0320011000, 0.0404796000, 0.0601607000, 0.1103636000, 0.2542175000, 0.6965225000", \ - "0.0280618000, 0.0316161000, 0.0402746000, 0.0607604000, 0.1107310000, 0.2541996000, 0.6987892000", \ - "0.0279218000, 0.0317432000, 0.0403592000, 0.0601689000, 0.1103686000, 0.2534939000, 0.7002059000", \ - "0.0352491000, 0.0389617000, 0.0473707000, 0.0657926000, 0.1136394000, 0.2551290000, 0.6991589000", \ - "0.0519142000, 0.0571734000, 0.0673853000, 0.0866849000, 0.1309880000, 0.2646948000, 0.6996584000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0205117000, 0.0254001000, 0.0386165000, 0.0756239000, 0.1878778000, 0.5240791000, 1.5021518000", \ - "0.0203758000, 0.0254034000, 0.0385889000, 0.0756288000, 0.1878710000, 0.5241000000, 1.5014611000", \ - "0.0203300000, 0.0253943000, 0.0386236000, 0.0756589000, 0.1877146000, 0.5240112000, 1.5027173000", \ - "0.0203771000, 0.0253878000, 0.0385039000, 0.0756577000, 0.1878804000, 0.5242365000, 1.5001973000", \ - "0.0228472000, 0.0278801000, 0.0409999000, 0.0769997000, 0.1881604000, 0.5241043000, 1.5030381000", \ - "0.0290822000, 0.0344343000, 0.0473819000, 0.0820115000, 0.1896983000, 0.5222778000, 1.4990273000", \ - "0.0410017000, 0.0474814000, 0.0620481000, 0.0947524000, 0.1951667000, 0.5248036000, 1.4979382000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1635411000, 0.1701347000, 0.1851158000, 0.2162322000, 0.2784285000, 0.4089931000, 0.7442415000", \ - "0.1687751000, 0.1754150000, 0.1903740000, 0.2216705000, 0.2837592000, 0.4142777000, 0.7494628000", \ - "0.1808859000, 0.1875062000, 0.2024421000, 0.2337220000, 0.2956998000, 0.4262397000, 0.7614309000", \ - "0.2077759000, 0.2143833000, 0.2293595000, 0.2604308000, 0.3227768000, 0.4533047000, 0.7885663000", \ - "0.2703136000, 0.2769081000, 0.2917256000, 0.3229796000, 0.3852729000, 0.5158846000, 0.8510567000", \ - "0.3909557000, 0.3984316000, 0.4150644000, 0.4493448000, 0.5151736000, 0.6484337000, 0.9840941000", \ - "0.5984643000, 0.6076258000, 0.6278629000, 0.6685372000, 0.7457356000, 0.8904551000, 1.2309532000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1003850000, 0.1065322000, 0.1208868000, 0.1538856000, 0.2376379000, 0.4739089000, 1.1571512000", \ - "0.1045483000, 0.1106898000, 0.1250556000, 0.1581013000, 0.2419523000, 0.4782860000, 1.1626470000", \ - "0.1145866000, 0.1207452000, 0.1351244000, 0.1681510000, 0.2518582000, 0.4894173000, 1.1748834000", \ - "0.1392044000, 0.1453422000, 0.1597325000, 0.1926682000, 0.2764414000, 0.5127140000, 1.1960296000", \ - "0.1865470000, 0.1929183000, 0.2076641000, 0.2412293000, 0.3250313000, 0.5614811000, 1.2485379000", \ - "0.2467628000, 0.2546560000, 0.2710511000, 0.3061312000, 0.3909992000, 0.6276242000, 1.3148227000", \ - "0.3009281000, 0.3111872000, 0.3327929000, 0.3733724000, 0.4598475000, 0.6962314000, 1.3805245000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0265964000, 0.0309537000, 0.0421864000, 0.0674398000, 0.1218920000, 0.2620430000, 0.6991659000", \ - "0.0265934000, 0.0311656000, 0.0420618000, 0.0673250000, 0.1216738000, 0.2626568000, 0.6994143000", \ - "0.0266072000, 0.0308816000, 0.0420321000, 0.0671962000, 0.1219442000, 0.2625990000, 0.6983302000", \ - "0.0264889000, 0.0309944000, 0.0417704000, 0.0673866000, 0.1214831000, 0.2618920000, 0.6987631000", \ - "0.0269554000, 0.0311658000, 0.0422163000, 0.0677006000, 0.1216904000, 0.2625030000, 0.6981762000", \ - "0.0326962000, 0.0375466000, 0.0489870000, 0.0749781000, 0.1280396000, 0.2662426000, 0.6992555000", \ - "0.0452696000, 0.0509971000, 0.0637369000, 0.0922433000, 0.1494798000, 0.2831531000, 0.7014486000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0212484000, 0.0262269000, 0.0396283000, 0.0767249000, 0.1884801000, 0.5239060000, 1.5002797000", \ - "0.0212201000, 0.0263428000, 0.0397527000, 0.0767279000, 0.1885239000, 0.5225710000, 1.5003480000", \ - "0.0211563000, 0.0262351000, 0.0397531000, 0.0767656000, 0.1885621000, 0.5243698000, 1.5031354000", \ - "0.0211768000, 0.0262974000, 0.0395783000, 0.0767462000, 0.1887454000, 0.5250024000, 1.5003327000", \ - "0.0234237000, 0.0284557000, 0.0416633000, 0.0781633000, 0.1889825000, 0.5249114000, 1.5002523000", \ - "0.0305625000, 0.0354083000, 0.0478159000, 0.0820811000, 0.1911801000, 0.5239867000, 1.5026591000", \ - "0.0429971000, 0.0490138000, 0.0618543000, 0.0940663000, 0.1942730000, 0.5264650000, 1.5006523000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.1475146000, 0.1541499000, 0.1691740000, 0.2004139000, 0.2624148000, 0.3929934000, 0.7281287000", \ - "0.1509952000, 0.1576179000, 0.1725680000, 0.2038637000, 0.2659440000, 0.3965239000, 0.7317672000", \ - "0.1614210000, 0.1679807000, 0.1829865000, 0.2139347000, 0.2764111000, 0.4069787000, 0.7422178000", \ - "0.1891051000, 0.1957195000, 0.2106053000, 0.2418829000, 0.3041641000, 0.4347787000, 0.7700288000", \ - "0.2575924000, 0.2641039000, 0.2789183000, 0.3101369000, 0.3723993000, 0.5033392000, 0.8383217000", \ - "0.3883080000, 0.3963471000, 0.4141220000, 0.4495146000, 0.5172103000, 0.6503730000, 0.9851874000", \ - "0.5981825000, 0.6081010000, 0.6308676000, 0.6756400000, 0.7577852000, 0.9040101000, 1.2445522000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0869378000, 0.0928657000, 0.1068979000, 0.1394506000, 0.2227389000, 0.4586637000, 1.1427841000", \ - "0.0912340000, 0.0972192000, 0.1112217000, 0.1437646000, 0.2269902000, 0.4628208000, 1.1461592000", \ - "0.1014445000, 0.1073719000, 0.1214849000, 0.1539926000, 0.2372767000, 0.4736073000, 1.1574904000", \ - "0.1249571000, 0.1308968000, 0.1448785000, 0.1772245000, 0.2604610000, 0.4964744000, 1.1792674000", \ - "0.1650685000, 0.1714314000, 0.1860428000, 0.2191657000, 0.3026324000, 0.5402435000, 1.2221261000", \ - "0.2106493000, 0.2185121000, 0.2354321000, 0.2702479000, 0.3544103000, 0.5909971000, 1.2782692000", \ - "0.2392803000, 0.2498893000, 0.2721927000, 0.3132610000, 0.3997435000, 0.6355496000, 1.3189642000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0265824000, 0.0309716000, 0.0418517000, 0.0673451000, 0.1219057000, 0.2625516000, 0.6967231000", \ - "0.0266022000, 0.0307947000, 0.0421778000, 0.0672020000, 0.1213341000, 0.2625879000, 0.6981558000", \ - "0.0266144000, 0.0309137000, 0.0416577000, 0.0674026000, 0.1216033000, 0.2625417000, 0.6983729000", \ - "0.0266396000, 0.0310488000, 0.0421812000, 0.0672933000, 0.1214487000, 0.2619968000, 0.6983529000", \ - "0.0268248000, 0.0315210000, 0.0424042000, 0.0673527000, 0.1218854000, 0.2625894000, 0.6985280000", \ - "0.0371691000, 0.0424385000, 0.0534451000, 0.0786834000, 0.1302174000, 0.2670980000, 0.6996993000", \ - "0.0545037000, 0.0602808000, 0.0737901000, 0.1042949000, 0.1597237000, 0.2866515000, 0.7041209000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014560100, 0.0042399100, 0.0123467000, 0.0359537000, 0.1046980000, 0.3048800000"); - values("0.0203860000, 0.0253005000, 0.0385585000, 0.0755532000, 0.1872131000, 0.5226188000, 1.5014001000", \ - "0.0202561000, 0.0252209000, 0.0386158000, 0.0756452000, 0.1877461000, 0.5241385000, 1.4999850000", \ - "0.0203300000, 0.0253124000, 0.0384920000, 0.0755914000, 0.1878049000, 0.5243698000, 1.5037346000", \ - "0.0204401000, 0.0254706000, 0.0386433000, 0.0755838000, 0.1878800000, 0.5242920000, 1.5003070000", \ - "0.0235449000, 0.0281356000, 0.0410664000, 0.0777060000, 0.1883682000, 0.5244688000, 1.5004912000", \ - "0.0314048000, 0.0361780000, 0.0482532000, 0.0824038000, 0.1904286000, 0.5230474000, 1.5038520000", \ - "0.0446654000, 0.0505627000, 0.0641562000, 0.0960625000, 0.1945040000, 0.5259630000, 1.4989517000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22a_4") { - leakage_power () { - value : 0.0050025000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0037075000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0050073000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0049961000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0036430000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0054476000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0028449000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0033494000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0038034000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0054365000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0030054000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0035098000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0025429000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0054417000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0017447000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0022492000; - when : "A1&A2&B1&!B2"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__o22a"; - cell_leakage_power : 0.0038582540; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0047950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080550000, 0.0080421000, 0.0080123000, 0.0080096000, 0.0080033000, 0.0079887000, 0.0079552000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007985000, -0.007981300, -0.007972600, -0.007974500, -0.007978800, -0.007988700, -0.008011600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050350000; - } - pin ("A2") { - capacitance : 0.0043350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040270000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0075522000, 0.0075517000, 0.0075505000, 0.0075518000, 0.0075549000, 0.0075621000, 0.0075785000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007529000, -0.007528000, -0.007525800, -0.007527400, -0.007531100, -0.007539600, -0.007559100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046440000; - } - pin ("B1") { - capacitance : 0.0048190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0095412000, 0.0095350000, 0.0095207000, 0.0095234000, 0.0095297000, 0.0095442000, 0.0095776000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003298400, -0.003309200, -0.003334100, -0.003301000, -0.003224800, -0.003049100, -0.002644100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050240000; - } - pin ("B2") { - capacitance : 0.0043130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0088068000, 0.0088065000, 0.0088061000, 0.0088034000, 0.0087973000, 0.0087833000, 0.0087508000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002505000, -0.002516800, -0.002544000, -0.002511900, -0.002437900, -0.002267300, -0.001874100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045610000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A1&B2) | (A2&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0369371000, 0.0351447000, 0.0299084000, 0.0148925000, -0.038303800, -0.220741100, -0.809786600", \ - "0.0364942000, 0.0348167000, 0.0295989000, 0.0147418000, -0.038739800, -0.220973600, -0.810070400", \ - "0.0364389000, 0.0346691000, 0.0293792000, 0.0143038000, -0.038985700, -0.221474400, -0.810414000", \ - "0.0358994000, 0.0341665000, 0.0289320000, 0.0137488000, -0.039530300, -0.221791000, -0.810942800", \ - "0.0355372000, 0.0337958000, 0.0285325000, 0.0134469000, -0.040053000, -0.222311400, -0.811188000", \ - "0.0362431000, 0.0344504000, 0.0291009000, 0.0141126000, -0.039630500, -0.221976900, -0.810745600", \ - "0.0462291000, 0.0441772000, 0.0380405000, 0.0196019000, -0.037941500, -0.220771900, -0.809163200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0344612000, 0.0363977000, 0.0425981000, 0.0615304000, 0.1201462000, 0.3050391000, 0.8864905000", \ - "0.0344759000, 0.0364213000, 0.0425108000, 0.0615671000, 0.1201862000, 0.3036672000, 0.8872135000", \ - "0.0343372000, 0.0362882000, 0.0423867000, 0.0614484000, 0.1200136000, 0.3034343000, 0.8874666000", \ - "0.0340779000, 0.0359885000, 0.0421467000, 0.0611299000, 0.1195629000, 0.3034907000, 0.8903197000", \ - "0.0337238000, 0.0356455000, 0.0416627000, 0.0602423000, 0.1186496000, 0.3027571000, 0.8859493000", \ - "0.0343746000, 0.0362035000, 0.0420911000, 0.0604944000, 0.1179095000, 0.3006603000, 0.8899084000", \ - "0.0356145000, 0.0373557000, 0.0430783000, 0.0609732000, 0.1192055000, 0.3027149000, 0.8841320000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0268516000, 0.0252333000, 0.0207557000, 0.0073273000, -0.044481700, -0.226819300, -0.816395200", \ - "0.0265584000, 0.0250744000, 0.0205046000, 0.0071573000, -0.044878900, -0.227113900, -0.816670700", \ - "0.0262112000, 0.0246107000, 0.0200107000, 0.0066869000, -0.045388300, -0.227596500, -0.817148800", \ - "0.0255209000, 0.0239339000, 0.0193788000, 0.0058746000, -0.046017300, -0.228202400, -0.817725100", \ - "0.0251633000, 0.0235286000, 0.0188956000, 0.0052476000, -0.046626500, -0.228707800, -0.818118600", \ - "0.0252668000, 0.0234020000, 0.0176291000, 0.0042334000, -0.047305900, -0.228955100, -0.818184700", \ - "0.0371943000, 0.0352302000, 0.0294160000, 0.0111422000, -0.045392400, -0.228486900, -0.817691000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0331761000, 0.0351847000, 0.0413112000, 0.0603631000, 0.1189868000, 0.3030172000, 0.8902141000", \ - "0.0330383000, 0.0349983000, 0.0411504000, 0.0600540000, 0.1187426000, 0.3024646000, 0.8865269000", \ - "0.0326672000, 0.0346442000, 0.0408159000, 0.0598503000, 0.1184439000, 0.3036287000, 0.8858063000", \ - "0.0324777000, 0.0344720000, 0.0405761000, 0.0595369000, 0.1179869000, 0.3021044000, 0.8894655000", \ - "0.0322807000, 0.0341673000, 0.0401477000, 0.0583862000, 0.1167183000, 0.3009164000, 0.8852024000", \ - "0.0329937000, 0.0347904000, 0.0405669000, 0.0589475000, 0.1163289000, 0.2992103000, 0.8877744000", \ - "0.0346544000, 0.0363816000, 0.0420467000, 0.0599841000, 0.1177207000, 0.3014606000, 0.8829927000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0227629000, 0.0211309000, 0.0166697000, 0.0032615000, -0.048596100, -0.230635200, -0.820039500", \ - "0.0224612000, 0.0208848000, 0.0164432000, 0.0029942000, -0.048818900, -0.230917000, -0.820336400", \ - "0.0219371000, 0.0202954000, 0.0157876000, 0.0023537000, -0.049436800, -0.231461400, -0.820854600", \ - "0.0213963000, 0.0197801000, 0.0152460000, 0.0017206000, -0.050105700, -0.232093700, -0.821446800", \ - "0.0210137000, 0.0194040000, 0.0148088000, 0.0009965000, -0.050760200, -0.232588000, -0.821807700", \ - "0.0234534000, 0.0214261000, 0.0154423000, 0.0012311000, -0.050188700, -0.231995000, -0.821201000", \ - "0.0367487000, 0.0346790000, 0.0287815000, 0.0099758000, -0.047678300, -0.230188200, -0.819266200"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0294303000, 0.0313940000, 0.0375623000, 0.0566547000, 0.1152695000, 0.2991847000, 0.8862554000", \ - "0.0294985000, 0.0314658000, 0.0375546000, 0.0566752000, 0.1151963000, 0.2991228000, 0.8859734000", \ - "0.0293261000, 0.0313245000, 0.0374796000, 0.0564969000, 0.1151583000, 0.2988207000, 0.8817462000", \ - "0.0292224000, 0.0311598000, 0.0372277000, 0.0561619000, 0.1144919000, 0.2984184000, 0.8851732000", \ - "0.0286709000, 0.0305388000, 0.0365649000, 0.0550475000, 0.1133536000, 0.2975362000, 0.8813778000", \ - "0.0300040000, 0.0317721000, 0.0374964000, 0.0558447000, 0.1128650000, 0.2961650000, 0.8814172000", \ - "0.0311869000, 0.0328782000, 0.0384781000, 0.0566277000, 0.1144346000, 0.2975070000, 0.8780664000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0414133000, 0.0396274000, 0.0344584000, 0.0193498000, -0.033874900, -0.216335800, -0.805344800", \ - "0.0413175000, 0.0396719000, 0.0342825000, 0.0192780000, -0.033881500, -0.216545000, -0.805569100", \ - "0.0407871000, 0.0389720000, 0.0338822000, 0.0187423000, -0.034439000, -0.216887000, -0.805924700", \ - "0.0403729000, 0.0386166000, 0.0334200000, 0.0183330000, -0.034973800, -0.217268800, -0.806203300", \ - "0.0400114000, 0.0382009000, 0.0330704000, 0.0178637000, -0.035428400, -0.217802500, -0.806707400", \ - "0.0395713000, 0.0377461000, 0.0324779000, 0.0174932000, -0.035670900, -0.218170000, -0.806932000", \ - "0.0480374000, 0.0460874000, 0.0401276000, 0.0219641000, -0.035301700, -0.218103000, -0.806351100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015966190, 0.0050983850, 0.0162803600, 0.0519870600, 0.1660071000, 0.5301002000"); - values("0.0377647000, 0.0396964000, 0.0457728000, 0.0648574000, 0.1233898000, 0.3071191000, 0.8906275000", \ - "0.0375306000, 0.0394895000, 0.0455554000, 0.0646409000, 0.1231736000, 0.3070670000, 0.8939375000", \ - "0.0372526000, 0.0392364000, 0.0453518000, 0.0643709000, 0.1230020000, 0.3069444000, 0.8941316000", \ - "0.0369299000, 0.0389032000, 0.0450205000, 0.0640090000, 0.1225929000, 0.3065167000, 0.8896844000", \ - "0.0370424000, 0.0389597000, 0.0450337000, 0.0634639000, 0.1220068000, 0.3058141000, 0.8898175000", \ - "0.0376638000, 0.0394281000, 0.0452774000, 0.0636670000, 0.1214548000, 0.3046629000, 0.8888077000", \ - "0.0391950000, 0.0409377000, 0.0466037000, 0.0645557000, 0.1228226000, 0.3064150000, 0.8870449000"); - } - } - max_capacitance : 0.5301000000; - max_transition : 1.5014620000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.2093929000, 0.2137404000, 0.2248173000, 0.2488763000, 0.2988721000, 0.4125689000, 0.7338822000", \ - "0.2145612000, 0.2189154000, 0.2299540000, 0.2541224000, 0.3034984000, 0.4176702000, 0.7397274000", \ - "0.2270176000, 0.2313635000, 0.2423806000, 0.2665031000, 0.3162714000, 0.4301897000, 0.7523147000", \ - "0.2540733000, 0.2584028000, 0.2694237000, 0.2935680000, 0.3433605000, 0.4569344000, 0.7784421000", \ - "0.3151698000, 0.3194976000, 0.3304731000, 0.3545826000, 0.4043248000, 0.5184190000, 0.8405291000", \ - "0.4431795000, 0.4478469000, 0.4596463000, 0.4848917000, 0.5365600000, 0.6524004000, 0.9743016000", \ - "0.6661068000, 0.6719179000, 0.6864280000, 0.7170421000, 0.7757245000, 0.8985466000, 1.2195877000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.1057784000, 0.1096749000, 0.1202656000, 0.1472490000, 0.2209285000, 0.4461737000, 1.1589165000", \ - "0.1103004000, 0.1142133000, 0.1247655000, 0.1517727000, 0.2254658000, 0.4507684000, 1.1665658000", \ - "0.1201044000, 0.1240316000, 0.1345962000, 0.1615717000, 0.2352146000, 0.4601628000, 1.1738093000", \ - "0.1408617000, 0.1447802000, 0.1553082000, 0.1822469000, 0.2558065000, 0.4809775000, 1.1937081000", \ - "0.1810772000, 0.1852018000, 0.1961945000, 0.2236995000, 0.2973241000, 0.5225455000, 1.2365038000", \ - "0.2369407000, 0.2416374000, 0.2541434000, 0.2835536000, 0.3584901000, 0.5836948000, 1.2974231000", \ - "0.2882988000, 0.2947109000, 0.3105690000, 0.3453560000, 0.4234553000, 0.6489100000, 1.3620668000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0304603000, 0.0330848000, 0.0392633000, 0.0548422000, 0.0965496000, 0.2212327000, 0.6427952000", \ - "0.0304523000, 0.0330339000, 0.0391815000, 0.0551707000, 0.0968004000, 0.2213730000, 0.6421518000", \ - "0.0305505000, 0.0330640000, 0.0395025000, 0.0553314000, 0.0969240000, 0.2211878000, 0.6426983000", \ - "0.0308235000, 0.0328867000, 0.0398184000, 0.0552330000, 0.0966467000, 0.2211493000, 0.6428325000", \ - "0.0304570000, 0.0330232000, 0.0392699000, 0.0551496000, 0.0967673000, 0.2211932000, 0.6426020000", \ - "0.0350499000, 0.0377338000, 0.0441451000, 0.0597365000, 0.1002876000, 0.2225213000, 0.6404342000", \ - "0.0466463000, 0.0496797000, 0.0570942000, 0.0734654000, 0.1140620000, 0.2336643000, 0.6436526000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0216665000, 0.0248922000, 0.0347423000, 0.0642662000, 0.1612612000, 0.4794264000, 1.4986217000", \ - "0.0216087000, 0.0248938000, 0.0346784000, 0.0643370000, 0.1611478000, 0.4798824000, 1.4987231000", \ - "0.0217111000, 0.0249680000, 0.0346050000, 0.0642603000, 0.1611394000, 0.4804044000, 1.4993213000", \ - "0.0216623000, 0.0249517000, 0.0345761000, 0.0642485000, 0.1611636000, 0.4800366000, 1.4970289000", \ - "0.0236069000, 0.0269232000, 0.0366083000, 0.0656069000, 0.1615305000, 0.4802459000, 1.4996491000", \ - "0.0290692000, 0.0327338000, 0.0423330000, 0.0700568000, 0.1633452000, 0.4788258000, 1.4984815000", \ - "0.0405737000, 0.0446660000, 0.0548550000, 0.0820366000, 0.1683581000, 0.4811870000, 1.4966253000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.1920340000, 0.1963445000, 0.2073777000, 0.2314677000, 0.2811950000, 0.3951749000, 0.7172739000", \ - "0.1960273000, 0.2003567000, 0.2114364000, 0.2354174000, 0.2853798000, 0.3987851000, 0.7208638000", \ - "0.2065200000, 0.2108674000, 0.2218423000, 0.2460093000, 0.2959055000, 0.4097450000, 0.7318102000", \ - "0.2345372000, 0.2388783000, 0.2499185000, 0.2739944000, 0.3239596000, 0.4376099000, 0.7592690000", \ - "0.3032123000, 0.3075610000, 0.3185786000, 0.3425789000, 0.3924510000, 0.5064739000, 0.8285181000", \ - "0.4511455000, 0.4560653000, 0.4687186000, 0.4946010000, 0.5459791000, 0.6613515000, 0.9836868000", \ - "0.6943732000, 0.7008210000, 0.7170893000, 0.7509479000, 0.8114657000, 0.9326636000, 1.2576459000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0987718000, 0.1027221000, 0.1135002000, 0.1407258000, 0.2144802000, 0.4397588000, 1.1519286000", \ - "0.1036435000, 0.1075690000, 0.1182925000, 0.1455481000, 0.2192468000, 0.4439252000, 1.1575240000", \ - "0.1130605000, 0.1169900000, 0.1277169000, 0.1549940000, 0.2287682000, 0.4535868000, 1.1668752000", \ - "0.1323001000, 0.1362406000, 0.1469292000, 0.1740325000, 0.2478021000, 0.4729083000, 1.1877636000", \ - "0.1673128000, 0.1715369000, 0.1827120000, 0.2106112000, 0.2847466000, 0.5102124000, 1.2225285000", \ - "0.2127535000, 0.2177177000, 0.2305582000, 0.2605774000, 0.3359287000, 0.5611321000, 1.2786635000", \ - "0.2444585000, 0.2510607000, 0.2679000000, 0.3038701000, 0.3833627000, 0.6087065000, 1.3215057000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0304273000, 0.0331289000, 0.0394669000, 0.0548376000, 0.0968177000, 0.2212661000, 0.6424578000", \ - "0.0306237000, 0.0331720000, 0.0396732000, 0.0551831000, 0.0966320000, 0.2212540000, 0.6415518000", \ - "0.0305183000, 0.0329273000, 0.0392362000, 0.0550738000, 0.0966455000, 0.2211534000, 0.6423163000", \ - "0.0304094000, 0.0328812000, 0.0399351000, 0.0548268000, 0.0966354000, 0.2212367000, 0.6409628000", \ - "0.0304886000, 0.0329688000, 0.0395922000, 0.0549244000, 0.0966529000, 0.2212447000, 0.6419448000", \ - "0.0378499000, 0.0403181000, 0.0465204000, 0.0612851000, 0.1001859000, 0.2227501000, 0.6429771000", \ - "0.0558580000, 0.0591843000, 0.0670548000, 0.0827920000, 0.1184294000, 0.2335157000, 0.6438121000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0218397000, 0.0251885000, 0.0349429000, 0.0645445000, 0.1611789000, 0.4806799000, 1.4970548000", \ - "0.0218400000, 0.0250943000, 0.0349466000, 0.0644674000, 0.1610907000, 0.4802534000, 1.4994435000", \ - "0.0218082000, 0.0251317000, 0.0349387000, 0.0644587000, 0.1611418000, 0.4788276000, 1.5009325000", \ - "0.0218698000, 0.0251759000, 0.0349365000, 0.0644277000, 0.1609022000, 0.4801960000, 1.5013237000", \ - "0.0241776000, 0.0275240000, 0.0372358000, 0.0664038000, 0.1618110000, 0.4799612000, 1.4983770000", \ - "0.0302489000, 0.0335865000, 0.0435846000, 0.0712545000, 0.1640588000, 0.4777278000, 1.5007726000", \ - "0.0426502000, 0.0466582000, 0.0574680000, 0.0840786000, 0.1697513000, 0.4813022000, 1.4933533000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.1721674000, 0.1763763000, 0.1874817000, 0.2131912000, 0.2701460000, 0.3946634000, 0.7209769000", \ - "0.1771224000, 0.1813217000, 0.1923661000, 0.2180662000, 0.2751591000, 0.3995614000, 0.7258814000", \ - "0.1891849000, 0.1933683000, 0.2043779000, 0.2300166000, 0.2871371000, 0.4115162000, 0.7378695000", \ - "0.2166495000, 0.2208183000, 0.2318684000, 0.2573614000, 0.3146513000, 0.4390650000, 0.7654534000", \ - "0.2797769000, 0.2839498000, 0.2949061000, 0.3205141000, 0.3778396000, 0.5024074000, 0.8287303000", \ - "0.4032484000, 0.4079363000, 0.4201576000, 0.4482276000, 0.5092115000, 0.6368326000, 0.9639790000", \ - "0.6192064000, 0.6248779000, 0.6396504000, 0.6726917000, 0.7420063000, 0.8822598000, 1.2163761000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0968901000, 0.1007574000, 0.1113371000, 0.1383468000, 0.2120576000, 0.4373285000, 1.1518552000", \ - "0.1009144000, 0.1048873000, 0.1154281000, 0.1423643000, 0.2159582000, 0.4410584000, 1.1551805000", \ - "0.1107984000, 0.1146963000, 0.1253053000, 0.1522544000, 0.2258521000, 0.4516548000, 1.1646903000", \ - "0.1349186000, 0.1388134000, 0.1493084000, 0.1761977000, 0.2496927000, 0.4748290000, 1.1887450000", \ - "0.1790161000, 0.1830691000, 0.1938798000, 0.2209087000, 0.2947473000, 0.5198604000, 1.2342107000", \ - "0.2326831000, 0.2375195000, 0.2498145000, 0.2785462000, 0.3527470000, 0.5787452000, 1.2955661000", \ - "0.2739361000, 0.2804067000, 0.2962604000, 0.3304713000, 0.4069727000, 0.6312123000, 1.3455812000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0283245000, 0.0310572000, 0.0389354000, 0.0586921000, 0.1090360000, 0.2342711000, 0.6449170000", \ - "0.0283408000, 0.0312781000, 0.0388299000, 0.0588600000, 0.1089282000, 0.2344302000, 0.6449146000", \ - "0.0284120000, 0.0312907000, 0.0388301000, 0.0588941000, 0.1089564000, 0.2343145000, 0.6449520000", \ - "0.0283103000, 0.0313018000, 0.0389763000, 0.0588358000, 0.1087803000, 0.2343064000, 0.6439930000", \ - "0.0286930000, 0.0313516000, 0.0391572000, 0.0587688000, 0.1089459000, 0.2340393000, 0.6448737000", \ - "0.0348110000, 0.0377092000, 0.0456124000, 0.0661651000, 0.1155296000, 0.2381973000, 0.6449993000", \ - "0.0483418000, 0.0516172000, 0.0599450000, 0.0820045000, 0.1356217000, 0.2572834000, 0.6507659000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0216270000, 0.0250628000, 0.0346872000, 0.0642370000, 0.1609093000, 0.4803836000, 1.5014622000", \ - "0.0216693000, 0.0250440000, 0.0346347000, 0.0642085000, 0.1611289000, 0.4802177000, 1.5003234000", \ - "0.0216793000, 0.0250076000, 0.0347330000, 0.0641239000, 0.1611187000, 0.4808680000, 1.4984654000", \ - "0.0215205000, 0.0248071000, 0.0346679000, 0.0641520000, 0.1610653000, 0.4805456000, 1.5002151000", \ - "0.0238705000, 0.0270769000, 0.0366262000, 0.0660914000, 0.1617612000, 0.4803832000, 1.5000311000", \ - "0.0305929000, 0.0335590000, 0.0425731000, 0.0698504000, 0.1634324000, 0.4784561000, 1.4996046000", \ - "0.0433540000, 0.0470412000, 0.0568450000, 0.0815963000, 0.1679801000, 0.4809712000, 1.4937941000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.1532577000, 0.1574764000, 0.1685609000, 0.1943561000, 0.2512436000, 0.3757085000, 0.7020176000", \ - "0.1568785000, 0.1610586000, 0.1720526000, 0.1976962000, 0.2548786000, 0.3794879000, 0.7057009000", \ - "0.1669148000, 0.1710972000, 0.1821429000, 0.2078019000, 0.2648960000, 0.3894965000, 0.7158347000", \ - "0.1941771000, 0.1983961000, 0.2092782000, 0.2346667000, 0.2918680000, 0.4163039000, 0.7427592000", \ - "0.2630154000, 0.2671723000, 0.2780700000, 0.3035941000, 0.3607014000, 0.4852557000, 0.8112860000", \ - "0.3970722000, 0.4020726000, 0.4149619000, 0.4438053000, 0.5052286000, 0.6334053000, 0.9605577000", \ - "0.6151275000, 0.6214599000, 0.6380013000, 0.6743121000, 0.7490785000, 0.8909181000, 1.2251584000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0910817000, 0.0950513000, 0.1058560000, 0.1332759000, 0.2072243000, 0.4318584000, 1.1449078000", \ - "0.0954199000, 0.0993799000, 0.1101716000, 0.1375806000, 0.2115239000, 0.4365628000, 1.1512413000", \ - "0.1056978000, 0.1096739000, 0.1204742000, 0.1478398000, 0.2217548000, 0.4477658000, 1.1588041000", \ - "0.1294809000, 0.1334236000, 0.1441143000, 0.1713270000, 0.2450009000, 0.4701868000, 1.1853889000", \ - "0.1696524000, 0.1738074000, 0.1849478000, 0.2128330000, 0.2868427000, 0.5123804000, 1.2247777000", \ - "0.2149076000, 0.2199523000, 0.2329249000, 0.2622985000, 0.3366593000, 0.5621806000, 1.2766408000", \ - "0.2416499000, 0.2484086000, 0.2651533000, 0.3009606000, 0.3787040000, 0.6028382000, 1.3155081000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0285543000, 0.0309944000, 0.0389186000, 0.0587149000, 0.1088505000, 0.2342501000, 0.6449822000", \ - "0.0284312000, 0.0312480000, 0.0386513000, 0.0588452000, 0.1091932000, 0.2344262000, 0.6449801000", \ - "0.0283151000, 0.0310223000, 0.0389199000, 0.0587852000, 0.1089013000, 0.2343694000, 0.6450179000", \ - "0.0285593000, 0.0313199000, 0.0389545000, 0.0589204000, 0.1085704000, 0.2343549000, 0.6449605000", \ - "0.0287921000, 0.0312924000, 0.0392255000, 0.0590531000, 0.1091777000, 0.2344197000, 0.6450845000", \ - "0.0394570000, 0.0423168000, 0.0500475000, 0.0697746000, 0.1175543000, 0.2394475000, 0.6453221000", \ - "0.0578941000, 0.0612897000, 0.0704420000, 0.0941046000, 0.1457911000, 0.2614662000, 0.6521572000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015966200, 0.0050983900, 0.0162804000, 0.0519871000, 0.1660070000, 0.5301000000"); - values("0.0220681000, 0.0253973000, 0.0352041000, 0.0647436000, 0.1609829000, 0.4801778000, 1.4990500000", \ - "0.0219959000, 0.0253597000, 0.0351672000, 0.0648012000, 0.1613494000, 0.4796840000, 1.4994103000", \ - "0.0221123000, 0.0254060000, 0.0352232000, 0.0647895000, 0.1612474000, 0.4798414000, 1.4971623000", \ - "0.0219887000, 0.0253646000, 0.0352338000, 0.0648978000, 0.1613825000, 0.4795478000, 1.4962090000", \ - "0.0249097000, 0.0281120000, 0.0376916000, 0.0669411000, 0.1621684000, 0.4796576000, 1.4990738000", \ - "0.0332104000, 0.0361791000, 0.0453592000, 0.0716375000, 0.1644540000, 0.4795321000, 1.5003191000", \ - "0.0471276000, 0.0507739000, 0.0608882000, 0.0872101000, 0.1703108000, 0.4817594000, 1.4948887000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22ai_1") { - leakage_power () { - value : 0.0005941000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 1.0595048e-05; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0006024000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0005872000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0021734000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0007704000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0012515000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0026854000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0026055000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0007704000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0016836000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0031176000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0012400000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0007704000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0003181000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0017520000; - when : "A1&A2&B1&!B2"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__o22ai"; - cell_leakage_power : 0.0013082870; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039520000, 0.0039595000, 0.0039767000, 0.0039762000, 0.0039751000, 0.0039726000, 0.0039668000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003962700, -0.003961400, -0.003958500, -0.003959300, -0.003961000, -0.003965000, -0.003974200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024310000; - } - pin ("A2") { - capacitance : 0.0023450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038999000, 0.0039019000, 0.0039063000, 0.0039070000, 0.0039085000, 0.0039122000, 0.0039205000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003903200, -0.003901400, -0.003897100, -0.003897000, -0.003896800, -0.003896400, -0.003895400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024910000; - } - pin ("B1") { - capacitance : 0.0024310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050106000, 0.0050062000, 0.0049962000, 0.0049956000, 0.0049942000, 0.0049909000, 0.0049833000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001658200, -0.001668200, -0.001691200, -0.001673300, -0.001631800, -0.001536400, -0.001316300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - } - pin ("B2") { - capacitance : 0.0023630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046824000, 0.0046865000, 0.0046962000, 0.0046962000, 0.0046962000, 0.0046962000, 0.0046962000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001272800, -0.001283700, -0.001308900, -0.001290600, -0.001248500, -0.001151300, -0.000927300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024800000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0062078000, 0.0051733000, 0.0028155000, -0.002678700, -0.015326100, -0.044422000, -0.111285700", \ - "0.0061054000, 0.0050787000, 0.0026991000, -0.002773900, -0.015431700, -0.044499500, -0.111389400", \ - "0.0059785000, 0.0049492000, 0.0025848000, -0.002866500, -0.015495500, -0.044539100, -0.111441900", \ - "0.0058261000, 0.0048158000, 0.0024556000, -0.003001000, -0.015588300, -0.044628200, -0.111486200", \ - "0.0057382000, 0.0047007000, 0.0023267000, -0.003051300, -0.015594700, -0.044641100, -0.111489800", \ - "0.0058957000, 0.0048427000, 0.0024370000, -0.003066000, -0.015795900, -0.044784800, -0.111583200", \ - "0.0065938000, 0.0055111000, 0.0030643000, -0.002549600, -0.015277500, -0.044618400, -0.111530800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0144491000, 0.0155193000, 0.0178887000, 0.0234259000, 0.0360580000, 0.0649416000, 0.1310680000", \ - "0.0142451000, 0.0153144000, 0.0177882000, 0.0233304000, 0.0359771000, 0.0648485000, 0.1309510000", \ - "0.0140368000, 0.0151264000, 0.0175715000, 0.0231470000, 0.0358490000, 0.0648155000, 0.1309089000", \ - "0.0138994000, 0.0149662000, 0.0173865000, 0.0229944000, 0.0357260000, 0.0646662000, 0.1308943000", \ - "0.0138063000, 0.0148814000, 0.0173046000, 0.0228858000, 0.0355184000, 0.0645156000, 0.1307758000", \ - "0.0137697000, 0.0147962000, 0.0172243000, 0.0228060000, 0.0356239000, 0.0644854000, 0.1307558000", \ - "0.0142712000, 0.0152589000, 0.0175809000, 0.0228975000, 0.0358921000, 0.0648010000, 0.1309855000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0048754000, 0.0038576000, 0.0014896000, -0.003978600, -0.016618200, -0.045743600, -0.112672400", \ - "0.0048260000, 0.0038189000, 0.0014714000, -0.003971000, -0.016585300, -0.045691900, -0.112605100", \ - "0.0046762000, 0.0036786000, 0.0013616000, -0.004045300, -0.016626900, -0.045685600, -0.112585000", \ - "0.0044019000, 0.0034237000, 0.0011234000, -0.004243400, -0.016754600, -0.045747800, -0.112607800", \ - "0.0043223000, 0.0033291000, 0.0008859000, -0.004501400, -0.016940400, -0.045869600, -0.112672100", \ - "0.0042600000, 0.0032562000, 0.0008550000, -0.004597200, -0.017227800, -0.046126400, -0.112826600", \ - "0.0049394000, 0.0038660000, 0.0013909000, -0.004203800, -0.016974200, -0.046098400, -0.112948000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0122465000, 0.0132695000, 0.0157020000, 0.0212692000, 0.0339226000, 0.0627575000, 0.1289092000", \ - "0.0119736000, 0.0131018000, 0.0155196000, 0.0210965000, 0.0338031000, 0.0626869000, 0.1288436000", \ - "0.0116582000, 0.0127374000, 0.0152188000, 0.0208842000, 0.0336164000, 0.0626158000, 0.1287870000", \ - "0.0115761000, 0.0125643000, 0.0149914000, 0.0206506000, 0.0333722000, 0.0624002000, 0.1286994000", \ - "0.0117055000, 0.0127416000, 0.0151784000, 0.0207004000, 0.0333407000, 0.0619998000, 0.1286488000", \ - "0.0124792000, 0.0134977000, 0.0158574000, 0.0213224000, 0.0338281000, 0.0624271000, 0.1278942000", \ - "0.0134426000, 0.0144148000, 0.0168155000, 0.0221554000, 0.0345894000, 0.0630497000, 0.1291431000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0038672000, 0.0028258000, 0.0004733000, -0.005019700, -0.017656000, -0.046744900, -0.113632800", \ - "0.0037310000, 0.0026989000, 0.0003393000, -0.005104700, -0.017753900, -0.046822500, -0.113693000", \ - "0.0035668000, 0.0025410000, 0.0001877000, -0.005238400, -0.017819100, -0.046883900, -0.113739000", \ - "0.0033526000, 0.0023587000, 1.590000e-05, -0.005403100, -0.017959800, -0.047018300, -0.113818600", \ - "0.0032249000, 0.0021890000, -0.000180100, -0.005588100, -0.018124200, -0.047100300, -0.113928700", \ - "0.0037673000, 0.0024914000, 5.460000e-05, -0.005516500, -0.018106200, -0.047167500, -0.113978300", \ - "0.0047467000, 0.0035812000, 0.0010554000, -0.004587700, -0.017403300, -0.047067300, -0.114068000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0091303000, 0.0102608000, 0.0127575000, 0.0183432000, 0.0309748000, 0.0597620000, 0.1257538000", \ - "0.0089010000, 0.0100285000, 0.0125681000, 0.0182149000, 0.0309124000, 0.0597762000, 0.1258397000", \ - "0.0086464000, 0.0097656000, 0.0122965000, 0.0179742000, 0.0307566000, 0.0597040000, 0.1258086000", \ - "0.0084791000, 0.0095584000, 0.0120307000, 0.0176578000, 0.0304707000, 0.0595061000, 0.1257288000", \ - "0.0083521000, 0.0094311000, 0.0118831000, 0.0174631000, 0.0301557000, 0.0591964000, 0.1255315000", \ - "0.0083747000, 0.0094247000, 0.0118504000, 0.0173906000, 0.0301385000, 0.0589933000, 0.1251121000", \ - "0.0090501000, 0.0100023000, 0.0122563000, 0.0176744000, 0.0302875000, 0.0592552000, 0.1255173000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0022699000, 0.0012578000, -0.001081500, -0.006533600, -0.019170900, -0.048276900, -0.115195000", \ - "0.0022245000, 0.0012227000, -0.001109900, -0.006521900, -0.019131000, -0.048197700, -0.115111000", \ - "0.0020819000, 0.0010929000, -0.001206200, -0.006589200, -0.019144200, -0.048171400, -0.115090100", \ - "0.0018249000, 0.0007956000, -0.001454400, -0.006795400, -0.019310000, -0.048275400, -0.115092300", \ - "0.0015970000, 0.0005890000, -0.001738700, -0.007106500, -0.019560000, -0.048465900, -0.115210200", \ - "0.0018986000, 0.0009505000, -0.001484700, -0.007134100, -0.019833500, -0.048609900, -0.115348200", \ - "0.0030144000, 0.0018703000, -0.000694600, -0.006445700, -0.019327000, -0.048394600, -0.115595600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011480080, 0.0026358470, 0.0060519480, 0.0138953800, 0.0319040200, 0.0732521600"); - values("0.0068577000, 0.0080095000, 0.0105473000, 0.0161548000, 0.0287981000, 0.0575979000, 0.1237274000", \ - "0.0065349000, 0.0077280000, 0.0103143000, 0.0159634000, 0.0287171000, 0.0575974000, 0.1235650000", \ - "0.0063172000, 0.0074457000, 0.0099394000, 0.0156696000, 0.0284969000, 0.0574902000, 0.1237053000", \ - "0.0061868000, 0.0072696000, 0.0097615000, 0.0153478000, 0.0281537000, 0.0572568000, 0.1235217000", \ - "0.0064220000, 0.0074714000, 0.0098791000, 0.0153738000, 0.0280434000, 0.0568317000, 0.1232843000", \ - "0.0068910000, 0.0079127000, 0.0102801000, 0.0157949000, 0.0283192000, 0.0570973000, 0.1228562000", \ - "0.0082064000, 0.0091052000, 0.0112384000, 0.0166933000, 0.0290010000, 0.0573392000, 0.1234268000"); - } - } - max_capacitance : 0.0732520000; - max_transition : 1.5223100000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0504874000, 0.0546806000, 0.0635824000, 0.0834937000, 0.1276147000, 0.2274340000, 0.4554528000", \ - "0.0551878000, 0.0593250000, 0.0682912000, 0.0881779000, 0.1323831000, 0.2321403000, 0.4595588000", \ - "0.0652200000, 0.0693135000, 0.0783714000, 0.0983662000, 0.1424686000, 0.2423834000, 0.4697928000", \ - "0.0849406000, 0.0894311000, 0.0989477000, 0.1192399000, 0.1636160000, 0.2635881000, 0.4912595000", \ - "0.1161761000, 0.1220205000, 0.1343960000, 0.1598684000, 0.2102895000, 0.3118894000, 0.5398532000", \ - "0.1523620000, 0.1611069000, 0.1800693000, 0.2187063000, 0.2886436000, 0.4127756000, 0.6506407000", \ - "0.1743823000, 0.1889626000, 0.2184217000, 0.2794359000, 0.3880102000, 0.5709986000, 0.8734407000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.1085020000, 0.1176562000, 0.1382813000, 0.1854169000, 0.2916364000, 0.5346210000, 1.0913020000", \ - "0.1137627000, 0.1223866000, 0.1436100000, 0.1906783000, 0.2976837000, 0.5403609000, 1.0962834000", \ - "0.1254909000, 0.1342543000, 0.1554710000, 0.2031846000, 0.3096771000, 0.5531074000, 1.1097683000", \ - "0.1510612000, 0.1606036000, 0.1809653000, 0.2285021000, 0.3357115000, 0.5792649000, 1.1356988000", \ - "0.2075099000, 0.2168561000, 0.2401595000, 0.2873166000, 0.3942449000, 0.6379405000, 1.1948109000", \ - "0.3047568000, 0.3185679000, 0.3474099000, 0.4083233000, 0.5296008000, 0.7741506000, 1.3315666000", \ - "0.4666862000, 0.4873128000, 0.5306370000, 0.6174505000, 0.7815454000, 1.0787824000, 1.6457853000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0342735000, 0.0391540000, 0.0503381000, 0.0757651000, 0.1340532000, 0.2675446000, 0.5745172000", \ - "0.0342136000, 0.0392397000, 0.0502542000, 0.0757170000, 0.1342069000, 0.2674048000, 0.5742474000", \ - "0.0341492000, 0.0390169000, 0.0501682000, 0.0756288000, 0.1338747000, 0.2675613000, 0.5728134000", \ - "0.0388862000, 0.0434876000, 0.0533709000, 0.0773465000, 0.1341572000, 0.2677425000, 0.5729931000", \ - "0.0561947000, 0.0610991000, 0.0718443000, 0.0956540000, 0.1457438000, 0.2707112000, 0.5741028000", \ - "0.0925312000, 0.0991580000, 0.1133755000, 0.1416646000, 0.1963848000, 0.3102928000, 0.5858794000", \ - "0.1598895000, 0.1709012000, 0.1912243000, 0.2308828000, 0.3042703000, 0.4365920000, 0.6913909000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0849875000, 0.0967776000, 0.1240854000, 0.1883862000, 0.3321987000, 0.6660677000, 1.4263073000", \ - "0.0841369000, 0.0963680000, 0.1243606000, 0.1875287000, 0.3330591000, 0.6637304000, 1.4267981000", \ - "0.0841078000, 0.0963115000, 0.1240364000, 0.1874860000, 0.3331095000, 0.6640369000, 1.4281767000", \ - "0.0844794000, 0.0965728000, 0.1240715000, 0.1875457000, 0.3324160000, 0.6641748000, 1.4242838000", \ - "0.0991348000, 0.1095982000, 0.1343505000, 0.1927692000, 0.3332554000, 0.6653475000, 1.4246713000", \ - "0.1411592000, 0.1532958000, 0.1791790000, 0.2364090000, 0.3602517000, 0.6692092000, 1.4266589000", \ - "0.2236765000, 0.2391608000, 0.2723010000, 0.3411121000, 0.4772238000, 0.7568519000, 1.4449023000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0414086000, 0.0453323000, 0.0538818000, 0.0728545000, 0.1153104000, 0.2116689000, 0.4317820000", \ - "0.0461635000, 0.0501331000, 0.0587367000, 0.0778183000, 0.1202550000, 0.2166604000, 0.4367789000", \ - "0.0557886000, 0.0596938000, 0.0684503000, 0.0876242000, 0.1303652000, 0.2269121000, 0.4469262000", \ - "0.0729999000, 0.0776134000, 0.0874520000, 0.1076935000, 0.1506849000, 0.2474995000, 0.4679084000", \ - "0.0956967000, 0.1027233000, 0.1165284000, 0.1431701000, 0.1944328000, 0.2939657000, 0.5150635000", \ - "0.1160231000, 0.1268541000, 0.1477749000, 0.1895421000, 0.2624779000, 0.3882425000, 0.6231656000", \ - "0.1063479000, 0.1237054000, 0.1586184000, 0.2247896000, 0.3401152000, 0.5293073000, 0.8316265000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0960422000, 0.1053869000, 0.1255798000, 0.1726883000, 0.2793731000, 0.5222287000, 1.0783604000", \ - "0.0993670000, 0.1087203000, 0.1298964000, 0.1765112000, 0.2838006000, 0.5266546000, 1.0826496000", \ - "0.1096916000, 0.1190103000, 0.1395840000, 0.1871013000, 0.2947491000, 0.5381439000, 1.0945317000", \ - "0.1375107000, 0.1465545000, 0.1669264000, 0.2155226000, 0.3229968000, 0.5668040000, 1.1237792000", \ - "0.2050471000, 0.2148518000, 0.2370290000, 0.2834359000, 0.3891077000, 0.6314418000, 1.1879391000", \ - "0.3185063000, 0.3338881000, 0.3661990000, 0.4307174000, 0.5492871000, 0.7880518000, 1.3419585000", \ - "0.5025568000, 0.5261661000, 0.5753597000, 0.6740586000, 0.8540796000, 1.1565613000, 1.7079794000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0263983000, 0.0311369000, 0.0418611000, 0.0663088000, 0.1227285000, 0.2517348000, 0.5495512000", \ - "0.0263686000, 0.0311228000, 0.0418575000, 0.0662391000, 0.1227791000, 0.2516826000, 0.5475693000", \ - "0.0266315000, 0.0310945000, 0.0417211000, 0.0662874000, 0.1228646000, 0.2518886000, 0.5483098000", \ - "0.0330699000, 0.0372035000, 0.0467199000, 0.0688906000, 0.1231095000, 0.2514808000, 0.5480184000", \ - "0.0509684000, 0.0558862000, 0.0664675000, 0.0886121000, 0.1375274000, 0.2558307000, 0.5485253000", \ - "0.0866786000, 0.0937071000, 0.1081278000, 0.1364090000, 0.1897701000, 0.2989174000, 0.5637008000", \ - "0.1544748000, 0.1646899000, 0.1864872000, 0.2264365000, 0.2984458000, 0.4252563000, 0.6734229000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0850871000, 0.0963154000, 0.1241752000, 0.1877903000, 0.3324603000, 0.6637887000, 1.4257888000", \ - "0.0840884000, 0.0966761000, 0.1242086000, 0.1873850000, 0.3324040000, 0.6642640000, 1.4228627000", \ - "0.0842115000, 0.0963304000, 0.1239988000, 0.1876305000, 0.3322907000, 0.6661277000, 1.4250834000", \ - "0.0849321000, 0.0968404000, 0.1242445000, 0.1874155000, 0.3326983000, 0.6642071000, 1.4289518000", \ - "0.1085701000, 0.1179589000, 0.1403594000, 0.1950998000, 0.3328065000, 0.6667745000, 1.4283497000", \ - "0.1632788000, 0.1770117000, 0.2046907000, 0.2598736000, 0.3756478000, 0.6707424000, 1.4305411000", \ - "0.2545388000, 0.2754730000, 0.3174977000, 0.3993749000, 0.5360090000, 0.7840624000, 1.4485394000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0416595000, 0.0455702000, 0.0547663000, 0.0747142000, 0.1186864000, 0.2185322000, 0.4459585000", \ - "0.0456349000, 0.0497819000, 0.0588251000, 0.0787176000, 0.1230150000, 0.2227882000, 0.4501982000", \ - "0.0557127000, 0.0597886000, 0.0688640000, 0.0889364000, 0.1331725000, 0.2329222000, 0.4604535000", \ - "0.0783084000, 0.0832210000, 0.0932869000, 0.1133300000, 0.1575293000, 0.2567982000, 0.4850627000", \ - "0.1077934000, 0.1150452000, 0.1304611000, 0.1599217000, 0.2133451000, 0.3126331000, 0.5411687000", \ - "0.1378586000, 0.1497360000, 0.1725241000, 0.2180317000, 0.2977733000, 0.4373923000, 0.6718213000", \ - "0.1528155000, 0.1686926000, 0.2044946000, 0.2735581000, 0.3986489000, 0.6109434000, 0.9478900000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0710261000, 0.0809884000, 0.1033492000, 0.1529859000, 0.2656499000, 0.5203478000, 1.1069112000", \ - "0.0751966000, 0.0852733000, 0.1077985000, 0.1578118000, 0.2703076000, 0.5268387000, 1.1121960000", \ - "0.0863801000, 0.0963353000, 0.1187873000, 0.1690584000, 0.2822984000, 0.5395664000, 1.1254355000", \ - "0.1118073000, 0.1215714000, 0.1438432000, 0.1935558000, 0.3069124000, 0.5656481000, 1.1514947000", \ - "0.1562175000, 0.1693107000, 0.1969828000, 0.2508061000, 0.3639481000, 0.6214989000, 1.2092795000", \ - "0.2260914000, 0.2463726000, 0.2854068000, 0.3602694000, 0.4959275000, 0.7546946000, 1.3437288000", \ - "0.3434772000, 0.3731046000, 0.4326861000, 0.5423036000, 0.7290357000, 1.0549743000, 1.6555750000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0343610000, 0.0391966000, 0.0505006000, 0.0759999000, 0.1338891000, 0.2680377000, 0.5733876000", \ - "0.0343049000, 0.0391730000, 0.0502830000, 0.0758629000, 0.1341507000, 0.2674000000, 0.5730839000", \ - "0.0341549000, 0.0389274000, 0.0498751000, 0.0757484000, 0.1336959000, 0.2681502000, 0.5729657000", \ - "0.0443577000, 0.0489100000, 0.0577272000, 0.0796296000, 0.1341239000, 0.2682060000, 0.5744836000", \ - "0.0668976000, 0.0736314000, 0.0859492000, 0.1104443000, 0.1562110000, 0.2733749000, 0.5737986000", \ - "0.1093422000, 0.1180475000, 0.1369255000, 0.1718405000, 0.2356359000, 0.3404101000, 0.5961170000", \ - "0.1802149000, 0.1952693000, 0.2245058000, 0.2782417000, 0.3689258000, 0.5152979000, 0.7641132000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0807676000, 0.0936212000, 0.1228860000, 0.1893998000, 0.3410481000, 0.6893825000, 1.4954543000", \ - "0.0807836000, 0.0935972000, 0.1228216000, 0.1892257000, 0.3407777000, 0.6888414000, 1.4882962000", \ - "0.0808495000, 0.0936326000, 0.1228350000, 0.1892662000, 0.3408581000, 0.6881014000, 1.4895750000", \ - "0.0849170000, 0.0965836000, 0.1237300000, 0.1893339000, 0.3407279000, 0.6893879000, 1.4890844000", \ - "0.1093527000, 0.1189879000, 0.1417630000, 0.1993812000, 0.3426465000, 0.6894739000, 1.4888221000", \ - "0.1622484000, 0.1730308000, 0.1974330000, 0.2534079000, 0.3774375000, 0.6952573000, 1.4980402000", \ - "0.2614433000, 0.2740700000, 0.3036816000, 0.3678873000, 0.4982679000, 0.7864900000, 1.5080668000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0312177000, 0.0351164000, 0.0435839000, 0.0623265000, 0.1040264000, 0.1986940000, 0.4146170000", \ - "0.0353827000, 0.0392752000, 0.0478235000, 0.0666498000, 0.1085761000, 0.2032794000, 0.4198874000", \ - "0.0457906000, 0.0495017000, 0.0579890000, 0.0766588000, 0.1186768000, 0.2134653000, 0.4296840000", \ - "0.0630566000, 0.0686891000, 0.0798051000, 0.1007159000, 0.1423329000, 0.2371744000, 0.4537497000", \ - "0.0823160000, 0.0904088000, 0.1070370000, 0.1393417000, 0.1951874000, 0.2924964000, 0.5087632000", \ - "0.0938060000, 0.1068926000, 0.1319352000, 0.1815136000, 0.2674176000, 0.4062521000, 0.6361838000", \ - "0.0742885000, 0.0937894000, 0.1335257000, 0.2092889000, 0.3411699000, 0.5545013000, 0.8934316000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0552210000, 0.0654594000, 0.0881193000, 0.1380456000, 0.2497194000, 0.5063146000, 1.0915400000", \ - "0.0577979000, 0.0682899000, 0.0912789000, 0.1417153000, 0.2540803000, 0.5112891000, 1.0967872000", \ - "0.0685517000, 0.0783762000, 0.1006129000, 0.1513798000, 0.2656420000, 0.5233348000, 1.1088458000", \ - "0.0972517000, 0.1069591000, 0.1284178000, 0.1778403000, 0.2908402000, 0.5485253000, 1.1360006000", \ - "0.1467391000, 0.1620336000, 0.1915842000, 0.2454015000, 0.3567498000, 0.6122278000, 1.1998765000", \ - "0.2268163000, 0.2493090000, 0.2947486000, 0.3769693000, 0.5155089000, 0.7662800000, 1.3502353000", \ - "0.3647594000, 0.3981339000, 0.4648981000, 0.5884675000, 0.7962984000, 1.1303823000, 1.7133610000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0262529000, 0.0308176000, 0.0413912000, 0.0654060000, 0.1206692000, 0.2480920000, 0.5375836000", \ - "0.0260683000, 0.0307110000, 0.0412892000, 0.0653608000, 0.1208258000, 0.2473953000, 0.5385840000", \ - "0.0273120000, 0.0314248000, 0.0412674000, 0.0650553000, 0.1206324000, 0.2470934000, 0.5391862000", \ - "0.0385342000, 0.0430393000, 0.0523217000, 0.0720055000, 0.1218603000, 0.2480853000, 0.5383157000", \ - "0.0607627000, 0.0672996000, 0.0798954000, 0.1045212000, 0.1481712000, 0.2556879000, 0.5380550000", \ - "0.1006487000, 0.1113268000, 0.1310374000, 0.1647787000, 0.2245703000, 0.3320959000, 0.5650223000", \ - "0.1726141000, 0.1871575000, 0.2171818000, 0.2703434000, 0.3584569000, 0.5046996000, 0.7472122000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011480100, 0.0026358500, 0.0060519500, 0.0138954000, 0.0319040000, 0.0732522000"); - values("0.0807326000, 0.0936058000, 0.1228588000, 0.1892997000, 0.3408478000, 0.6895272000, 1.4868280000", \ - "0.0807046000, 0.0935790000, 0.1228505000, 0.1893796000, 0.3407873000, 0.6896623000, 1.4972223000", \ - "0.0803253000, 0.0933860000, 0.1227762000, 0.1893709000, 0.3407301000, 0.6896249000, 1.4869929000", \ - "0.0896397000, 0.0998879000, 0.1250764000, 0.1891886000, 0.3407108000, 0.6887694000, 1.4882823000", \ - "0.1268256000, 0.1353491000, 0.1545262000, 0.2052031000, 0.3428413000, 0.6885540000, 1.4921540000", \ - "0.1904067000, 0.2023916000, 0.2291154000, 0.2819089000, 0.3931260000, 0.6979422000, 1.4865202000", \ - "0.2945616000, 0.3112636000, 0.3501533000, 0.4279863000, 0.5647673000, 0.8203886000, 1.5223104000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22ai_2") { - leakage_power () { - value : 0.0014957000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0168186000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0015170000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0014851000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0068183000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0019613000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0036488000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0056139000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0056139000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0019624000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0024445000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0044096000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0036488000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0019618000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0004794000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0024445000; - when : "A1&A2&B1&!B2"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__o22ai"; - cell_leakage_power : 0.0038952240; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079599000, 0.0079413000, 0.0078983000, 0.0078953000, 0.0078883000, 0.0078723000, 0.0078353000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007882500, -0.007879800, -0.007873300, -0.007874600, -0.007877500, -0.007884400, -0.007900100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045740000; - } - pin ("A2") { - capacitance : 0.0043120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079434000, 0.0079352000, 0.0079163000, 0.0079176000, 0.0079206000, 0.0079274000, 0.0079431000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007897200, -0.007892300, -0.007880900, -0.007882600, -0.007886300, -0.007894900, -0.007914700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046130000; - } - pin ("B1") { - capacitance : 0.0042990000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091324000, 0.0091294000, 0.0091224000, 0.0091179000, 0.0091074000, 0.0090832000, 0.0090275000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002170800, -0.002189000, -0.002230900, -0.002193900, -0.002108400, -0.001911500, -0.001457700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044230000; - } - pin ("B2") { - capacitance : 0.0043140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092880000, 0.0092841000, 0.0092750000, 0.0092734000, 0.0092696000, 0.0092609000, 0.0092408000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002221200, -0.002241300, -0.002287800, -0.002250200, -0.002163700, -0.001964100, -0.001504100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045470000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0144671000, 0.0132493000, 0.0100846000, 0.0020715000, -0.018580200, -0.071422000, -0.206395100", \ - "0.0142464000, 0.0130173000, 0.0098492000, 0.0018213000, -0.018802000, -0.071581700, -0.206477300", \ - "0.0139324000, 0.0127019000, 0.0095638000, 0.0015589000, -0.019007500, -0.071755500, -0.206657200", \ - "0.0136308000, 0.0124118000, 0.0092477000, 0.0012619000, -0.019252600, -0.071898600, -0.206753800", \ - "0.0133475000, 0.0121015000, 0.0089940000, 0.0011287000, -0.019282900, -0.072003000, -0.206726300", \ - "0.0136583000, 0.0124174000, 0.0092060000, 0.0012727000, -0.019746700, -0.072263600, -0.206970600", \ - "0.0150544000, 0.0137415000, 0.0105350000, 0.0022501000, -0.018656000, -0.071931100, -0.206880600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0279220000, 0.0291982000, 0.0323532000, 0.0405631000, 0.0613157000, 0.1138895000, 0.2473461000", \ - "0.0275470000, 0.0288152000, 0.0321680000, 0.0403276000, 0.0611280000, 0.1135717000, 0.2472960000", \ - "0.0271597000, 0.0284533000, 0.0317365000, 0.0400333000, 0.0609228000, 0.1135815000, 0.2472292000", \ - "0.0268140000, 0.0281328000, 0.0313763000, 0.0396624000, 0.0605758000, 0.1133729000, 0.2470990000", \ - "0.0266083000, 0.0278621000, 0.0310901000, 0.0393410000, 0.0601492000, 0.1129685000, 0.2466990000", \ - "0.0265208000, 0.0277733000, 0.0310254000, 0.0393791000, 0.0603096000, 0.1129629000, 0.2465729000", \ - "0.0271024000, 0.0283338000, 0.0313989000, 0.0392869000, 0.0604584000, 0.1134222000, 0.2472043000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0105748000, 0.0093695000, 0.0062650000, -0.001706500, -0.022359200, -0.075176000, -0.210232300", \ - "0.0105097000, 0.0093086000, 0.0062464000, -0.001692900, -0.022260200, -0.075036800, -0.210057500", \ - "0.0102364000, 0.0090699000, 0.0060153000, -0.001857100, -0.022294800, -0.074999000, -0.209959600", \ - "0.0097652000, 0.0086086000, 0.0055755000, -0.002221800, -0.022561900, -0.075115900, -0.209988900", \ - "0.0094265000, 0.0082316000, 0.0051768000, -0.002739100, -0.022984700, -0.075351200, -0.210087600", \ - "0.0096954000, 0.0083789000, 0.0053018000, -0.002784000, -0.023506200, -0.075855000, -0.210430600", \ - "0.0115889000, 0.0101753000, 0.0068243000, -0.001563700, -0.022519400, -0.075604400, -0.210551600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0232133000, 0.0245807000, 0.0277450000, 0.0359888000, 0.0567525000, 0.1092711000, 0.2428556000", \ - "0.0227382000, 0.0240580000, 0.0273499000, 0.0356140000, 0.0565301000, 0.1091140000, 0.2427158000", \ - "0.0221345000, 0.0234191000, 0.0267959000, 0.0351242000, 0.0561281000, 0.1089104000, 0.2426930000", \ - "0.0218207000, 0.0231315000, 0.0264383000, 0.0346461000, 0.0556365000, 0.1085481000, 0.2426206000", \ - "0.0217864000, 0.0231373000, 0.0263320000, 0.0346014000, 0.0553997000, 0.1076760000, 0.2418298000", \ - "0.0227579000, 0.0239710000, 0.0270952000, 0.0351806000, 0.0555659000, 0.1079652000, 0.2415908000", \ - "0.0271408000, 0.0288268000, 0.0300825000, 0.0379260000, 0.0606472000, 0.1094525000, 0.2422388000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0087497000, 0.0075187000, 0.0043472000, -0.003714100, -0.024327300, -0.077106800, -0.211987200", \ - "0.0084632000, 0.0072396000, 0.0040887000, -0.003920900, -0.024562300, -0.077273200, -0.212315800", \ - "0.0081708000, 0.0069456000, 0.0038159000, -0.004195000, -0.024694400, -0.077409700, -0.212315800", \ - "0.0077453000, 0.0065430000, 0.0034855000, -0.004497600, -0.024959800, -0.077683900, -0.212435000", \ - "0.0075824000, 0.0063396000, 0.0031689000, -0.004790000, -0.025289500, -0.077861500, -0.212643700", \ - "0.0081401000, 0.0068702000, 0.0036498000, -0.004494100, -0.025335800, -0.077931200, -0.212833900", \ - "0.0104028000, 0.0090983000, 0.0057306000, -0.002694400, -0.023950600, -0.077615600, -0.212888400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0178449000, 0.0191904000, 0.0225240000, 0.0308049000, 0.0515201000, 0.1038945000, 0.2371332000", \ - "0.0174470000, 0.0187982000, 0.0221925000, 0.0305963000, 0.0514243000, 0.1039067000, 0.2370742000", \ - "0.0170336000, 0.0183413000, 0.0217311000, 0.0301571000, 0.0511469000, 0.1038408000, 0.2372651000", \ - "0.0167481000, 0.0180444000, 0.0213089000, 0.0296421000, 0.0506467000, 0.1034806000, 0.2371510000", \ - "0.0165108000, 0.0177990000, 0.0210446000, 0.0292565000, 0.0500730000, 0.1028915000, 0.2366898000", \ - "0.0165545000, 0.0177998000, 0.0210309000, 0.0292071000, 0.0500770000, 0.1027397000, 0.2361497000", \ - "0.0174957000, 0.0186489000, 0.0216497000, 0.0295281000, 0.0503458000, 0.1025959000, 0.2368412000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0046984000, 0.0035155000, 0.0004624000, -0.007488800, -0.028080500, -0.080909300, -0.215975300", \ - "0.0046563000, 0.0034803000, 0.0004427000, -0.007463400, -0.028005500, -0.080762700, -0.215811200", \ - "0.0044325000, 0.0032800000, 0.0002609000, -0.007621500, -0.027993800, -0.080663300, -0.215595900", \ - "0.0040813000, 0.0028520000, -0.000155800, -0.008008900, -0.028284500, -0.080866400, -0.215670300", \ - "0.0037269000, 0.0025405000, -0.000534800, -0.008454900, -0.028760200, -0.081163100, -0.215892600", \ - "0.0045284000, 0.0034170000, 0.0002397000, -0.007926400, -0.029105000, -0.081378900, -0.216135800", \ - "0.0084331000, 0.0058879000, 0.0023767000, -0.006291500, -0.027644000, -0.081015100, -0.216463900"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012747960, 0.0032502100, 0.0082867080, 0.0211277200, 0.0538670700, 0.1373391000"); - values("0.0126997000, 0.0141183000, 0.0175922000, 0.0259886000, 0.0467852000, 0.0991631000, 0.2325661000", \ - "0.0121592000, 0.0135493000, 0.0170879000, 0.0256489000, 0.0466633000, 0.0991662000, 0.2326058000", \ - "0.0118000000, 0.0131979000, 0.0165870000, 0.0250011000, 0.0462445000, 0.0990112000, 0.2325982000", \ - "0.0116271000, 0.0128881000, 0.0162044000, 0.0246591000, 0.0456360000, 0.0986005000, 0.2323859000", \ - "0.0118861000, 0.0131211000, 0.0162694000, 0.0244617000, 0.0453646000, 0.0977959000, 0.2319430000", \ - "0.0134933000, 0.0146729000, 0.0179159000, 0.0257472000, 0.0459814000, 0.0987272000, 0.2312458000", \ - "0.0166315000, 0.0177435000, 0.0210392000, 0.0298266000, 0.0483066000, 0.1007114000, 0.2317134000"); - } - } - max_capacitance : 0.1373390000; - max_transition : 1.5034440000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0532076000, 0.0561019000, 0.0627821000, 0.0792617000, 0.1189167000, 0.2172614000, 0.4645483000", \ - "0.0576778000, 0.0605185000, 0.0673715000, 0.0838148000, 0.1232455000, 0.2216499000, 0.4691563000", \ - "0.0673197000, 0.0701721000, 0.0768783000, 0.0933896000, 0.1330819000, 0.2315147000, 0.4792935000", \ - "0.0864545000, 0.0894942000, 0.0966158000, 0.1133299000, 0.1532805000, 0.2517955000, 0.4996565000", \ - "0.1164629000, 0.1199806000, 0.1293059000, 0.1505666000, 0.1966978000, 0.2974955000, 0.5454363000", \ - "0.1497575000, 0.1559388000, 0.1695391000, 0.2014124000, 0.2653629000, 0.3909948000, 0.6513446000", \ - "0.1646495000, 0.1736219000, 0.1963300000, 0.2444421000, 0.3459598000, 0.5323844000, 0.8626216000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.1167801000, 0.1228610000, 0.1381414000, 0.1765499000, 0.2725181000, 0.5157135000, 1.1332220000", \ - "0.1218514000, 0.1275895000, 0.1432048000, 0.1812805000, 0.2781925000, 0.5215444000, 1.1393521000", \ - "0.1339393000, 0.1400197000, 0.1547943000, 0.1942712000, 0.2911194000, 0.5345328000, 1.1554138000", \ - "0.1611168000, 0.1664862000, 0.1822538000, 0.2211358000, 0.3181563000, 0.5620940000, 1.1802296000", \ - "0.2192868000, 0.2257358000, 0.2424177000, 0.2807790000, 0.3776179000, 0.6218218000, 1.2417003000", \ - "0.3214783000, 0.3299915000, 0.3516726000, 0.4034343000, 0.5139957000, 0.7600140000, 1.3790341000", \ - "0.4919781000, 0.5057506000, 0.5381460000, 0.6106189000, 0.7624097000, 1.0685742000, 1.7013744000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0367591000, 0.0399710000, 0.0482926000, 0.0690441000, 0.1213556000, 0.2551308000, 0.5963162000", \ - "0.0367189000, 0.0399894000, 0.0483131000, 0.0688923000, 0.1215845000, 0.2552410000, 0.5957176000", \ - "0.0365313000, 0.0397894000, 0.0480907000, 0.0688386000, 0.1215334000, 0.2553304000, 0.5962414000", \ - "0.0409789000, 0.0439485000, 0.0512174000, 0.0708849000, 0.1219379000, 0.2549853000, 0.5956821000", \ - "0.0571512000, 0.0604947000, 0.0685447000, 0.0885867000, 0.1352279000, 0.2592358000, 0.5953496000", \ - "0.0931687000, 0.0973542000, 0.1081546000, 0.1338970000, 0.1835373000, 0.2996131000, 0.6078809000", \ - "0.1600860000, 0.1673484000, 0.1832472000, 0.2169797000, 0.2860826000, 0.4195293000, 0.7138494000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0858961000, 0.0935890000, 0.1137423000, 0.1662721000, 0.2972962000, 0.6318627000, 1.4830165000", \ - "0.0850551000, 0.0932261000, 0.1142048000, 0.1656184000, 0.2969820000, 0.6316903000, 1.4849055000", \ - "0.0852574000, 0.0935013000, 0.1137908000, 0.1658018000, 0.2976045000, 0.6317247000, 1.4840627000", \ - "0.0853277000, 0.0934585000, 0.1140711000, 0.1660105000, 0.2972899000, 0.6325600000, 1.4794859000", \ - "0.0974840000, 0.1044104000, 0.1227751000, 0.1711861000, 0.2978069000, 0.6308660000, 1.4829267000", \ - "0.1370483000, 0.1453439000, 0.1654569000, 0.2135859000, 0.3269163000, 0.6377500000, 1.4819408000", \ - "0.2219508000, 0.2320136000, 0.2559401000, 0.3138363000, 0.4387238000, 0.7229954000, 1.4977044000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0418794000, 0.0445315000, 0.0510550000, 0.0667333000, 0.1050950000, 0.2002801000, 0.4414003000", \ - "0.0466158000, 0.0492624000, 0.0558737000, 0.0716673000, 0.1100365000, 0.2052955000, 0.4467826000", \ - "0.0560878000, 0.0588145000, 0.0653510000, 0.0813114000, 0.1199146000, 0.2153272000, 0.4562092000", \ - "0.0728472000, 0.0757279000, 0.0834754000, 0.1005977000, 0.1395495000, 0.2354238000, 0.4768046000", \ - "0.0946789000, 0.0992322000, 0.1097435000, 0.1326614000, 0.1798864000, 0.2801589000, 0.5220697000", \ - "0.1117773000, 0.1179735000, 0.1341072000, 0.1696056000, 0.2394434000, 0.3682019000, 0.6254009000", \ - "0.0966234000, 0.1074446000, 0.1333539000, 0.1889427000, 0.2987281000, 0.4928919000, 0.8271998000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0977618000, 0.1040414000, 0.1193745000, 0.1575780000, 0.2540131000, 0.4972395000, 1.1146952000", \ - "0.1010885000, 0.1071844000, 0.1224824000, 0.1613626000, 0.2576744000, 0.5013118000, 1.1204936000", \ - "0.1098720000, 0.1162403000, 0.1318848000, 0.1707600000, 0.2680892000, 0.5122303000, 1.1311510000", \ - "0.1372426000, 0.1433622000, 0.1586635000, 0.1969635000, 0.2938850000, 0.5383857000, 1.1570386000", \ - "0.2022181000, 0.2091323000, 0.2258213000, 0.2638965000, 0.3591014000, 0.6016875000, 1.2230483000", \ - "0.3112046000, 0.3214411000, 0.3460849000, 0.4011108000, 0.5139486000, 0.7523275000, 1.3679408000", \ - "0.4904098000, 0.5054784000, 0.5405493000, 0.6229209000, 0.7934720000, 1.1087851000, 1.7296347000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0276438000, 0.0306518000, 0.0385290000, 0.0585354000, 0.1094182000, 0.2393678000, 0.5708137000", \ - "0.0276046000, 0.0307266000, 0.0385808000, 0.0584812000, 0.1094446000, 0.2393218000, 0.5713389000", \ - "0.0277222000, 0.0306153000, 0.0384214000, 0.0584867000, 0.1094547000, 0.2394288000, 0.5709098000", \ - "0.0339689000, 0.0368720000, 0.0438307000, 0.0615670000, 0.1101554000, 0.2395857000, 0.5709656000", \ - "0.0514936000, 0.0547523000, 0.0625691000, 0.0815239000, 0.1263711000, 0.2447884000, 0.5708631000", \ - "0.0870910000, 0.0917156000, 0.1021694000, 0.1265771000, 0.1774004000, 0.2899022000, 0.5890764000", \ - "0.1535960000, 0.1603345000, 0.1759571000, 0.2113301000, 0.2794993000, 0.4141807000, 0.6941864000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0850680000, 0.0935484000, 0.1137756000, 0.1656850000, 0.2972342000, 0.6318879000, 1.4813023000", \ - "0.0849861000, 0.0934696000, 0.1137290000, 0.1659174000, 0.2974595000, 0.6317220000, 1.4828576000", \ - "0.0853335000, 0.0933569000, 0.1138238000, 0.1656668000, 0.2972776000, 0.6310977000, 1.4814947000", \ - "0.0857306000, 0.0936194000, 0.1138299000, 0.1658803000, 0.2972017000, 0.6308327000, 1.4822114000", \ - "0.1096273000, 0.1162434000, 0.1319528000, 0.1760263000, 0.2983071000, 0.6323738000, 1.4870358000", \ - "0.1597930000, 0.1695480000, 0.1923150000, 0.2414096000, 0.3439974000, 0.6407199000, 1.4854242000", \ - "0.2417272000, 0.2566416000, 0.2917119000, 0.3639692000, 0.4994660000, 0.7631890000, 1.5034444000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0423323000, 0.0451194000, 0.0519398000, 0.0684366000, 0.1078768000, 0.2063047000, 0.4537750000", \ - "0.0462999000, 0.0491322000, 0.0558248000, 0.0721982000, 0.1121010000, 0.2102724000, 0.4578433000", \ - "0.0561362000, 0.0588910000, 0.0656785000, 0.0821877000, 0.1218505000, 0.2203732000, 0.4682888000", \ - "0.0789304000, 0.0821285000, 0.0896250000, 0.1062657000, 0.1457845000, 0.2442906000, 0.4922707000", \ - "0.1085364000, 0.1132035000, 0.1242997000, 0.1492821000, 0.1992849000, 0.2995237000, 0.5468834000", \ - "0.1377346000, 0.1448293000, 0.1619279000, 0.1992407000, 0.2754699000, 0.4160555000, 0.6735180000", \ - "0.1456469000, 0.1566683000, 0.1822983000, 0.2393088000, 0.3556758000, 0.5726015000, 0.9441872000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0681784000, 0.0745459000, 0.0901469000, 0.1286504000, 0.2251210000, 0.4676381000, 1.0817185000", \ - "0.0727151000, 0.0790093000, 0.0949354000, 0.1339438000, 0.2303644000, 0.4729464000, 1.0892307000", \ - "0.0848749000, 0.0911018000, 0.1067716000, 0.1458453000, 0.2431245000, 0.4875619000, 1.1020459000", \ - "0.1119393000, 0.1181495000, 0.1337933000, 0.1720305000, 0.2697267000, 0.5131144000, 1.1302119000", \ - "0.1586210000, 0.1671064000, 0.1864993000, 0.2308820000, 0.3283203000, 0.5723206000, 1.1899904000", \ - "0.2327678000, 0.2454711000, 0.2745960000, 0.3359965000, 0.4590253000, 0.7090467000, 1.3273735000", \ - "0.3500069000, 0.3716251000, 0.4169038000, 0.5112143000, 0.6877828000, 1.0075620000, 1.6478570000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0368656000, 0.0401200000, 0.0483841000, 0.0689385000, 0.1215569000, 0.2553356000, 0.5962503000", \ - "0.0368335000, 0.0400723000, 0.0482724000, 0.0690578000, 0.1214846000, 0.2551394000, 0.5964706000", \ - "0.0362955000, 0.0394691000, 0.0477752000, 0.0686494000, 0.1214615000, 0.2553225000, 0.5962287000", \ - "0.0453617000, 0.0485879000, 0.0557651000, 0.0732937000, 0.1221928000, 0.2550662000, 0.5958677000", \ - "0.0670406000, 0.0712857000, 0.0815886000, 0.1026975000, 0.1469345000, 0.2619700000, 0.5958171000", \ - "0.1075578000, 0.1139247000, 0.1284947000, 0.1590843000, 0.2201693000, 0.3324169000, 0.6160975000", \ - "0.1790071000, 0.1890013000, 0.2114760000, 0.2574739000, 0.3435192000, 0.5014394000, 0.7861389000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0836583000, 0.0917231000, 0.1123796000, 0.1644187000, 0.2953456000, 0.6266850000, 1.4789543000", \ - "0.0837067000, 0.0918146000, 0.1124013000, 0.1644267000, 0.2950581000, 0.6275470000, 1.4807576000", \ - "0.0837886000, 0.0918436000, 0.1124083000, 0.1644209000, 0.2951714000, 0.6265163000, 1.4728291000", \ - "0.0870941000, 0.0945519000, 0.1136859000, 0.1645475000, 0.2951564000, 0.6265958000, 1.4708509000", \ - "0.1101286000, 0.1157799000, 0.1317763000, 0.1763507000, 0.2979437000, 0.6264139000, 1.4762234000", \ - "0.1629065000, 0.1695431000, 0.1866744000, 0.2291452000, 0.3348623000, 0.6347035000, 1.4799536000", \ - "0.2682751000, 0.2757422000, 0.2946916000, 0.3433290000, 0.4602274000, 0.7295257000, 1.4907136000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0298312000, 0.0324734000, 0.0389643000, 0.0543954000, 0.0917756000, 0.1846538000, 0.4194537000", \ - "0.0340807000, 0.0367337000, 0.0432389000, 0.0586563000, 0.0963089000, 0.1892371000, 0.4241008000", \ - "0.0446210000, 0.0470681000, 0.0532878000, 0.0685775000, 0.1062160000, 0.1995184000, 0.4349516000", \ - "0.0617199000, 0.0655444000, 0.0740333000, 0.0920034000, 0.1298155000, 0.2230665000, 0.4583600000", \ - "0.0803023000, 0.0856961000, 0.0984075000, 0.1256518000, 0.1789086000, 0.2772087000, 0.5122404000", \ - "0.0905170000, 0.0981844000, 0.1174117000, 0.1583032000, 0.2400238000, 0.3837742000, 0.6363461000", \ - "0.0680946000, 0.0796849000, 0.1088004000, 0.1717348000, 0.2961881000, 0.5161016000, 0.8908725000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0477768000, 0.0544350000, 0.0705874000, 0.1095790000, 0.2063848000, 0.4476512000, 1.0635083000", \ - "0.0506811000, 0.0570094000, 0.0735197000, 0.1131079000, 0.2104088000, 0.4523771000, 1.0686813000", \ - "0.0613044000, 0.0675587000, 0.0833012000, 0.1223388000, 0.2204598000, 0.4634690000, 1.0815470000", \ - "0.0886411000, 0.0957921000, 0.1108560000, 0.1491255000, 0.2450782000, 0.4913373000, 1.1072983000", \ - "0.1332828000, 0.1437510000, 0.1669034000, 0.2148129000, 0.3106773000, 0.5532836000, 1.1701932000", \ - "0.2072458000, 0.2226483000, 0.2562154000, 0.3278694000, 0.4596326000, 0.7056556000, 1.3181231000", \ - "0.3375012000, 0.3588344000, 0.4072769000, 0.5112847000, 0.7083292000, 1.0521213000, 1.6778390000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0271961000, 0.0301883000, 0.0376714000, 0.0570567000, 0.1063262000, 0.2325542000, 0.5534984000", \ - "0.0267733000, 0.0298254000, 0.0376173000, 0.0571229000, 0.1065265000, 0.2329114000, 0.5547001000", \ - "0.0277964000, 0.0304713000, 0.0376609000, 0.0567115000, 0.1062812000, 0.2326848000, 0.5541645000", \ - "0.0386607000, 0.0416014000, 0.0490583000, 0.0647315000, 0.1083803000, 0.2325962000, 0.5542974000", \ - "0.0591097000, 0.0636336000, 0.0737398000, 0.0946460000, 0.1377379000, 0.2421145000, 0.5545334000", \ - "0.0966063000, 0.1038384000, 0.1190324000, 0.1513952000, 0.2081550000, 0.3209626000, 0.5812468000", \ - "0.1646749000, 0.1762446000, 0.1990529000, 0.2464069000, 0.3338073000, 0.4861404000, 0.7563120000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012748000, 0.0032502100, 0.0082867100, 0.0211277000, 0.0538671000, 0.1373390000"); - values("0.0839845000, 0.0921439000, 0.1128737000, 0.1648974000, 0.2957192000, 0.6268925000, 1.4742474000", \ - "0.0837352000, 0.0919909000, 0.1128029000, 0.1649432000, 0.2957328000, 0.6266409000, 1.4795465000", \ - "0.0832450000, 0.0913429000, 0.1125182000, 0.1648715000, 0.2956942000, 0.6270001000, 1.4744633000", \ - "0.0945410000, 0.1007871000, 0.1177350000, 0.1653593000, 0.2956344000, 0.6275994000, 1.4758345000", \ - "0.1326073000, 0.1385830000, 0.1506723000, 0.1884439000, 0.3007981000, 0.6272625000, 1.4800310000", \ - "0.1943993000, 0.2021172000, 0.2208844000, 0.2658140000, 0.3596685000, 0.6410318000, 1.4746450000", \ - "0.2980908000, 0.3085416000, 0.3346187000, 0.3967794000, 0.5269726000, 0.7828534000, 1.5030591000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o22ai_4") { - leakage_power () { - value : 0.0034044000; - when : "!A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0004006000; - when : "!A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0105000000; - when : "!A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0033926000; - when : "!A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0038679000; - when : "!A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0044512000; - when : "!A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0019405000; - when : "!A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0037464000; - when : "!A1&A2&B1&!B2"; - } - leakage_power () { - value : 0.0042216000; - when : "A1&!A2&!B1&B2"; - } - leakage_power () { - value : 0.0044513000; - when : "A1&!A2&!B1&!B2"; - } - leakage_power () { - value : 0.0022942000; - when : "A1&!A2&B1&B2"; - } - leakage_power () { - value : 0.0041001000; - when : "A1&!A2&B1&!B2"; - } - leakage_power () { - value : 0.0023660000; - when : "A1&A2&!B1&B2"; - } - leakage_power () { - value : 0.0045049000; - when : "A1&A2&!B1&!B2"; - } - leakage_power () { - value : 0.0004384000; - when : "A1&A2&B1&B2"; - } - leakage_power () { - value : 0.0022443000; - when : "A1&A2&B1&!B2"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__o22ai"; - cell_leakage_power : 0.0035202790; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0091080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0160382000, 0.0160209000, 0.0159810000, 0.0159813000, 0.0159820000, 0.0159838000, 0.0159877000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015967400, -0.015957500, -0.015934500, -0.015927200, -0.015910400, -0.015871500, -0.015781900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0095820000; - } - pin ("A2") { - capacitance : 0.0084970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150935000, 0.0150894000, 0.0150801000, 0.0150814000, 0.0150845000, 0.0150917000, 0.0151081000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015048500, -0.015039700, -0.015019500, -0.015020400, -0.015022500, -0.015027400, -0.015038800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090970000; - } - pin ("B1") { - capacitance : 0.0089300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0086070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0186292000, 0.0186390000, 0.0186614000, 0.0186543000, 0.0186379000, 0.0186002000, 0.0185133000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006937800, -0.006936900, -0.006934900, -0.006873700, -0.006732600, -0.006407300, -0.005657600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092520000; - } - pin ("B2") { - capacitance : 0.0083220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0175385000, 0.0175378000, 0.0175363000, 0.0175324000, 0.0175232000, 0.0175022000, 0.0174538000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005686500, -0.005725800, -0.005816100, -0.005756400, -0.005618700, -0.005301400, -0.004570000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087580000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (!A1&!A2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0100875000, 0.0087272000, 0.0049463000, -0.005569600, -0.034839400, -0.115907700, -0.339403900", \ - "0.0099265000, 0.0085788000, 0.0048609000, -0.005575300, -0.034705500, -0.115668300, -0.339146300", \ - "0.0096699000, 0.0083246000, 0.0046076000, -0.005731300, -0.034718000, -0.115437900, -0.338797200", \ - "0.0089562000, 0.0076035000, 0.0039307000, -0.006316600, -0.035124800, -0.115648900, -0.338831600", \ - "0.0084651000, 0.0070974000, 0.0033441000, -0.007048300, -0.035726800, -0.116111700, -0.339058400", \ - "0.0094739000, 0.0080607000, 0.0041370000, -0.006458600, -0.036002600, -0.116441200, -0.339365600", \ - "0.0130302000, 0.0114834000, 0.0072615000, -0.004086200, -0.034339100, -0.116139600, -0.339851700"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0246389000, 0.0262205000, 0.0304756000, 0.0416263000, 0.0712184000, 0.1515190000, 0.3724207000", \ - "0.0235256000, 0.0251421000, 0.0294514000, 0.0408340000, 0.0708781000, 0.1515236000, 0.3723282000", \ - "0.0225498000, 0.0240730000, 0.0283785000, 0.0398165000, 0.0701120000, 0.1511684000, 0.3722022000", \ - "0.0220725000, 0.0235510000, 0.0276202000, 0.0387479000, 0.0688339000, 0.1506036000, 0.3720512000", \ - "0.0223633000, 0.0237436000, 0.0275827000, 0.0383089000, 0.0677035000, 0.1491846000, 0.3711654000", \ - "0.0243279000, 0.0257194000, 0.0295304000, 0.0399729000, 0.0690115000, 0.1496766000, 0.3701263000", \ - "0.0300372000, 0.0312538000, 0.0349460000, 0.0455533000, 0.0725867000, 0.1521483000, 0.3710191000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0266230000, 0.0252195000, 0.0213519000, 0.0107692000, -0.018454400, -0.099349800, -0.322567400", \ - "0.0261256000, 0.0247368000, 0.0209041000, 0.0103345000, -0.018911000, -0.099790400, -0.322924400", \ - "0.0255135000, 0.0241243000, 0.0203067000, 0.0097926000, -0.019335300, -0.100172100, -0.323324000", \ - "0.0249222000, 0.0233978000, 0.0197086000, 0.0092253000, -0.019831200, -0.100445600, -0.323543300", \ - "0.0243859000, 0.0229951000, 0.0191798000, 0.0087268000, -0.020210300, -0.100641600, -0.323586400", \ - "0.0249190000, 0.0235295000, 0.0196236000, 0.0089153000, -0.020471500, -0.101404500, -0.324079900", \ - "0.0271177000, 0.0256847000, 0.0217079000, 0.0107764000, -0.018940300, -0.100451800, -0.324122200"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0521503000, 0.0535943000, 0.0575441000, 0.0683142000, 0.0978840000, 0.1784445000, 0.3995588000", \ - "0.0515122000, 0.0529604000, 0.0569420000, 0.0678970000, 0.0974600000, 0.1782823000, 0.3992289000", \ - "0.0507351000, 0.0521961000, 0.0563644000, 0.0671719000, 0.0968996000, 0.1777826000, 0.3990699000", \ - "0.0501063000, 0.0514755000, 0.0554495000, 0.0664985000, 0.0963059000, 0.1773979000, 0.3987707000", \ - "0.0495246000, 0.0509679000, 0.0549471000, 0.0657528000, 0.0954250000, 0.1765282000, 0.3979055000", \ - "0.0492369000, 0.0506872000, 0.0547001000, 0.0657344000, 0.0954234000, 0.1762739000, 0.3972508000", \ - "0.0499283000, 0.0512694000, 0.0550466000, 0.0654258000, 0.0958083000, 0.1768732000, 0.3976791000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0196061000, 0.0182720000, 0.0145484000, 0.0041150000, -0.025087100, -0.106069200, -0.329549400", \ - "0.0194538000, 0.0181189000, 0.0144349000, 0.0040993000, -0.024962400, -0.105858800, -0.329306000", \ - "0.0190397000, 0.0177227000, 0.0140421000, 0.0037921000, -0.025082400, -0.105778600, -0.329148800", \ - "0.0182895000, 0.0169708000, 0.0133166000, 0.0031221000, -0.025607900, -0.106008800, -0.329104700", \ - "0.0178205000, 0.0164019000, 0.0126321000, 0.0023043000, -0.026336800, -0.106499100, -0.329336500", \ - "0.0179475000, 0.0165494000, 0.0126462000, 0.0021834000, -0.026974000, -0.107528200, -0.329983800", \ - "0.0202477000, 0.0187935000, 0.0147752000, 0.0036854000, -0.025980600, -0.107191700, -0.330440600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0434254000, 0.0448727000, 0.0488364000, 0.0596880000, 0.0892304000, 0.1698238000, 0.3907752000", \ - "0.0427651000, 0.0442274000, 0.0480813000, 0.0590211000, 0.0887057000, 0.1694644000, 0.3907544000", \ - "0.0415444000, 0.0430229000, 0.0470870000, 0.0580957000, 0.0879027000, 0.1690650000, 0.3906101000", \ - "0.0410070000, 0.0423950000, 0.0464962000, 0.0573526000, 0.0871383000, 0.1684878000, 0.3903079000", \ - "0.0408270000, 0.0422740000, 0.0461618000, 0.0570238000, 0.0866015000, 0.1675798000, 0.3893993000", \ - "0.0432532000, 0.0446789000, 0.0485994000, 0.0594804000, 0.0869145000, 0.1678891000, 0.3894737000", \ - "0.0491645000, 0.0513170000, 0.0517674000, 0.0618124000, 0.0929699000, 0.1735091000, 0.3892308000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0176703000, 0.0162736000, 0.0124411000, 0.0018689000, -0.027420400, -0.108222200, -0.331528000", \ - "0.0171300000, 0.0157281000, 0.0118869000, 0.0013324000, -0.027863900, -0.108654700, -0.332070200", \ - "0.0164373000, 0.0150538000, 0.0112909000, 0.0006949000, -0.028338700, -0.109193300, -0.332406100", \ - "0.0155574000, 0.0141769000, 0.0103821000, -6.79000e-05, -0.029037500, -0.109591000, -0.332827300", \ - "0.0151585000, 0.0137636000, 0.0099250000, -0.000582100, -0.029597000, -0.110099900, -0.333081100", \ - "0.0165275000, 0.0151168000, 0.0111858000, 0.0003304000, -0.029516200, -0.110392600, -0.333359700", \ - "0.0196231000, 0.0181443000, 0.0140689000, 0.0030747000, -0.027127800, -0.109283900, -0.333403900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013757780, 0.0037855280, 0.0104160900, 0.0286604500, 0.0788608200, 0.2169899000"); - values("0.0334409000, 0.0350243000, 0.0391920000, 0.0503580000, 0.0799615000, 0.1603831000, 0.3815305000", \ - "0.0324682000, 0.0340827000, 0.0382982000, 0.0496660000, 0.0796563000, 0.1602644000, 0.3811303000", \ - "0.0315366000, 0.0330942000, 0.0372335000, 0.0485545000, 0.0787665000, 0.1600927000, 0.3810581000", \ - "0.0309642000, 0.0324580000, 0.0364912000, 0.0475448000, 0.0776151000, 0.1590518000, 0.3804301000", \ - "0.0304677000, 0.0319452000, 0.0359721000, 0.0467902000, 0.0764241000, 0.1577767000, 0.3799333000", \ - "0.0305916000, 0.0319700000, 0.0359097000, 0.0466831000, 0.0763872000, 0.1572929000, 0.3785698000", \ - "0.0318392000, 0.0331531000, 0.0367904000, 0.0479508000, 0.0771749000, 0.1579102000, 0.3780772000"); - } - } - max_capacitance : 0.2169900000; - max_transition : 1.5396350000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0485013000, 0.0501742000, 0.0545300000, 0.0660051000, 0.0952530000, 0.1717184000, 0.3783210000", \ - "0.0528312000, 0.0544410000, 0.0588026000, 0.0702176000, 0.0995125000, 0.1761127000, 0.3823207000", \ - "0.0618247000, 0.0634827000, 0.0679024000, 0.0793483000, 0.1087149000, 0.1853006000, 0.3916577000", \ - "0.0793208000, 0.0809622000, 0.0859789000, 0.0980621000, 0.1276588000, 0.2044667000, 0.4109454000", \ - "0.1054218000, 0.1078424000, 0.1141698000, 0.1296499000, 0.1654839000, 0.2475766000, 0.4550508000", \ - "0.1317240000, 0.1355071000, 0.1446561000, 0.1675943000, 0.2196609000, 0.3271367000, 0.5546015000", \ - "0.1305469000, 0.1362179000, 0.1509412000, 0.1878175000, 0.2700035000, 0.4335654000, 0.7372302000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.1261880000, 0.1302933000, 0.1408564000, 0.1716706000, 0.2531024000, 0.4740195000, 1.0793927000", \ - "0.1306823000, 0.1348668000, 0.1455861000, 0.1763357000, 0.2580560000, 0.4794674000, 1.0882089000", \ - "0.1427862000, 0.1469234000, 0.1580129000, 0.1884422000, 0.2706521000, 0.4927064000, 1.0984651000", \ - "0.1694450000, 0.1736582000, 0.1851241000, 0.2155238000, 0.2973988000, 0.5201994000, 1.1262952000", \ - "0.2285244000, 0.2330549000, 0.2448677000, 0.2750967000, 0.3570720000, 0.5794186000, 1.1872117000", \ - "0.3345427000, 0.3401603000, 0.3565683000, 0.3960440000, 0.4919682000, 0.7172677000, 1.3252321000", \ - "0.5186022000, 0.5287465000, 0.5511970000, 0.6076069000, 0.7365052000, 1.0208033000, 1.6429701000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0345486000, 0.0363035000, 0.0412915000, 0.0546892000, 0.0920651000, 0.1962318000, 0.4846868000", \ - "0.0345391000, 0.0363540000, 0.0412603000, 0.0548444000, 0.0921829000, 0.1963403000, 0.4842859000", \ - "0.0342919000, 0.0360987000, 0.0409593000, 0.0546771000, 0.0920396000, 0.1963382000, 0.4843656000", \ - "0.0393776000, 0.0410542000, 0.0457129000, 0.0577987000, 0.0933186000, 0.1962047000, 0.4843544000", \ - "0.0551688000, 0.0570094000, 0.0621613000, 0.0755085000, 0.1096954000, 0.2032971000, 0.4847591000", \ - "0.0898628000, 0.0924627000, 0.0989364000, 0.1157502000, 0.1554939000, 0.2501950000, 0.5042290000", \ - "0.1544203000, 0.1582673000, 0.1683227000, 0.1936034000, 0.2490527000, 0.3637562000, 0.6177371000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0961312000, 0.1012799000, 0.1159504000, 0.1563564000, 0.2672020000, 0.5707088000, 1.4025706000", \ - "0.0960387000, 0.1015008000, 0.1159310000, 0.1569642000, 0.2667082000, 0.5717046000, 1.4074247000", \ - "0.0960840000, 0.1012883000, 0.1164660000, 0.1561383000, 0.2665326000, 0.5705539000, 1.4063856000", \ - "0.0961454000, 0.1014092000, 0.1158937000, 0.1564285000, 0.2669314000, 0.5703781000, 1.4046553000", \ - "0.1066835000, 0.1116326000, 0.1249551000, 0.1622266000, 0.2682096000, 0.5703018000, 1.4043333000", \ - "0.1441656000, 0.1498465000, 0.1643772000, 0.2028328000, 0.2979853000, 0.5777930000, 1.4080288000", \ - "0.2262661000, 0.2331511000, 0.2489098000, 0.2947703000, 0.4015316000, 0.6655588000, 1.4236894000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0391832000, 0.0409279000, 0.0456688000, 0.0575702000, 0.0875608000, 0.1664188000, 0.3800359000", \ - "0.0437852000, 0.0455618000, 0.0502799000, 0.0622671000, 0.0923158000, 0.1713511000, 0.3848771000", \ - "0.0528232000, 0.0546258000, 0.0592629000, 0.0712682000, 0.1015672000, 0.1805095000, 0.3943782000", \ - "0.0682185000, 0.0701805000, 0.0754628000, 0.0887437000, 0.1199209000, 0.1994180000, 0.4132700000", \ - "0.0872784000, 0.0901232000, 0.0979370000, 0.1152738000, 0.1547203000, 0.2409672000, 0.4561981000", \ - "0.0999715000, 0.1042499000, 0.1150112000, 0.1425805000, 0.2009149000, 0.3154949000, 0.5514246000", \ - "0.0724608000, 0.0795745000, 0.0973866000, 0.1401984000, 0.2333732000, 0.4101514000, 0.7271729000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.1071267000, 0.1114091000, 0.1223955000, 0.1524645000, 0.2343576000, 0.4558539000, 1.0611110000", \ - "0.1095757000, 0.1144011000, 0.1258132000, 0.1557656000, 0.2377540000, 0.4594921000, 1.0648562000", \ - "0.1199639000, 0.1241869000, 0.1356513000, 0.1661148000, 0.2486541000, 0.4705739000, 1.0765467000", \ - "0.1476451000, 0.1520779000, 0.1631869000, 0.1931548000, 0.2755405000, 0.4980272000, 1.1043891000", \ - "0.2166730000, 0.2210184000, 0.2330464000, 0.2627160000, 0.3433029000, 0.5650977000, 1.1721324000", \ - "0.3397712000, 0.3463517000, 0.3638511000, 0.4060310000, 0.5030003000, 0.7240130000, 1.3284684000", \ - "0.5449953000, 0.5549683000, 0.5791780000, 0.6439435000, 0.7920601000, 1.0866053000, 1.6994459000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0292410000, 0.0309878000, 0.0358783000, 0.0494852000, 0.0879394000, 0.1960885000, 0.4959209000", \ - "0.0291633000, 0.0309097000, 0.0357701000, 0.0494897000, 0.0879454000, 0.1963263000, 0.4962624000", \ - "0.0293771000, 0.0310600000, 0.0358001000, 0.0493008000, 0.0878175000, 0.1962867000, 0.4969845000", \ - "0.0355938000, 0.0373422000, 0.0417383000, 0.0539602000, 0.0896825000, 0.1962289000, 0.4959838000", \ - "0.0526937000, 0.0544238000, 0.0594480000, 0.0726244000, 0.1073618000, 0.2041649000, 0.4967392000", \ - "0.0874154000, 0.0900674000, 0.0970346000, 0.1142732000, 0.1545066000, 0.2515743000, 0.5168727000", \ - "0.1534328000, 0.1572889000, 0.1680879000, 0.1934309000, 0.2496443000, 0.3672237000, 0.6294102000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0963771000, 0.1013064000, 0.1160641000, 0.1561379000, 0.2668226000, 0.5712378000, 1.4080066000", \ - "0.0971420000, 0.1020641000, 0.1160129000, 0.1561157000, 0.2667218000, 0.5717397000, 1.4048775000", \ - "0.0961683000, 0.1013810000, 0.1161863000, 0.1561760000, 0.2666788000, 0.5699755000, 1.4059568000", \ - "0.0958883000, 0.1013156000, 0.1157112000, 0.1565684000, 0.2666205000, 0.5718252000, 1.4059638000", \ - "0.1156387000, 0.1197343000, 0.1317543000, 0.1658687000, 0.2680988000, 0.5703581000, 1.4045153000", \ - "0.1696734000, 0.1758152000, 0.1917235000, 0.2300956000, 0.3156837000, 0.5813123000, 1.4072168000", \ - "0.2564548000, 0.2692546000, 0.2905229000, 0.3464971000, 0.4671968000, 0.7095207000, 1.4270255000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0396090000, 0.0413209000, 0.0456965000, 0.0571372000, 0.0862843000, 0.1627523000, 0.3692700000", \ - "0.0434096000, 0.0451159000, 0.0495821000, 0.0609912000, 0.0901714000, 0.1667030000, 0.3733856000", \ - "0.0532201000, 0.0549196000, 0.0593582000, 0.0706029000, 0.0998078000, 0.1764344000, 0.3827757000", \ - "0.0742121000, 0.0762075000, 0.0814116000, 0.0940956000, 0.1230306000, 0.1995448000, 0.4062139000", \ - "0.1005945000, 0.1036192000, 0.1111780000, 0.1296011000, 0.1710909000, 0.2545968000, 0.4608569000", \ - "0.1214941000, 0.1258769000, 0.1375082000, 0.1657876000, 0.2284744000, 0.3547627000, 0.5875394000", \ - "0.1116713000, 0.1182393000, 0.1355384000, 0.1785874000, 0.2751047000, 0.4694298000, 0.8205344000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0786467000, 0.0832562000, 0.0956826000, 0.1281229000, 0.2146081000, 0.4466339000, 1.0837365000", \ - "0.0823914000, 0.0870580000, 0.0993849000, 0.1324050000, 0.2187401000, 0.4509866000, 1.0859382000", \ - "0.0941256000, 0.0986696000, 0.1107322000, 0.1435373000, 0.2313966000, 0.4670658000, 1.1006039000", \ - "0.1212817000, 0.1257038000, 0.1375040000, 0.1696158000, 0.2570479000, 0.4903280000, 1.1272629000", \ - "0.1701315000, 0.1758812000, 0.1907045000, 0.2274615000, 0.3149367000, 0.5488637000, 1.1866874000", \ - "0.2521159000, 0.2603956000, 0.2813967000, 0.3318887000, 0.4418861000, 0.6846299000, 1.3232223000", \ - "0.3891185000, 0.4032383000, 0.4361927000, 0.5127390000, 0.6695913000, 0.9819622000, 1.6403541000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0351327000, 0.0368989000, 0.0417111000, 0.0550449000, 0.0922930000, 0.1962628000, 0.4844313000", \ - "0.0349334000, 0.0367160000, 0.0416245000, 0.0549917000, 0.0923219000, 0.1962278000, 0.4841764000", \ - "0.0343753000, 0.0361823000, 0.0408952000, 0.0543211000, 0.0921483000, 0.1961523000, 0.4843552000", \ - "0.0440492000, 0.0458678000, 0.0506754000, 0.0619763000, 0.0948269000, 0.1961089000, 0.4843664000", \ - "0.0650752000, 0.0674349000, 0.0736111000, 0.0891545000, 0.1239494000, 0.2101368000, 0.4845412000", \ - "0.1038853000, 0.1076709000, 0.1174115000, 0.1404789000, 0.1884909000, 0.2866386000, 0.5188855000", \ - "0.1740770000, 0.1799095000, 0.1947331000, 0.2294604000, 0.3024973000, 0.4417359000, 0.7018847000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0977843000, 0.1035852000, 0.1195878000, 0.1635274000, 0.2835567000, 0.6103484000, 1.5140681000", \ - "0.0978230000, 0.1036284000, 0.1195905000, 0.1635349000, 0.2832461000, 0.6104105000, 1.5161865000", \ - "0.0978715000, 0.1036647000, 0.1196007000, 0.1635269000, 0.2833304000, 0.6114276000, 1.5119211000", \ - "0.1004510000, 0.1056958000, 0.1206951000, 0.1636578000, 0.2831086000, 0.6102011000, 1.5142640000", \ - "0.1209431000, 0.1253573000, 0.1382777000, 0.1761113000, 0.2871403000, 0.6113393000, 1.5117622000", \ - "0.1712804000, 0.1760531000, 0.1896052000, 0.2263589000, 0.3248835000, 0.6214785000, 1.5156729000", \ - "0.2716644000, 0.2767942000, 0.2913086000, 0.3317797000, 0.4378240000, 0.7116299000, 1.5377620000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0320097000, 0.0337914000, 0.0383387000, 0.0502473000, 0.0809857000, 0.1629608000, 0.3849698000", \ - "0.0361669000, 0.0379243000, 0.0425719000, 0.0545810000, 0.0854117000, 0.1673413000, 0.3896143000", \ - "0.0465287000, 0.0481582000, 0.0526103000, 0.0645855000, 0.0956121000, 0.1776457000, 0.4005289000", \ - "0.0645507000, 0.0669710000, 0.0724371000, 0.0869764000, 0.1188860000, 0.2010261000, 0.4240470000", \ - "0.0828937000, 0.0864887000, 0.0957360000, 0.1174964000, 0.1646516000, 0.2560152000, 0.4782154000", \ - "0.0911485000, 0.0966087000, 0.1106827000, 0.1440864000, 0.2153637000, 0.3543030000, 0.6050397000", \ - "0.0595058000, 0.0677334000, 0.0891014000, 0.1396373000, 0.2512110000, 0.4659564000, 0.8432305000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0572737000, 0.0618345000, 0.0744891000, 0.1070442000, 0.1919388000, 0.4242584000, 1.0588176000", \ - "0.0593129000, 0.0640508000, 0.0766516000, 0.1099280000, 0.1962227000, 0.4290147000, 1.0636703000", \ - "0.0691602000, 0.0736934000, 0.0861584000, 0.1190736000, 0.2068708000, 0.4410577000, 1.0779015000", \ - "0.0980545000, 0.1025940000, 0.1139059000, 0.1459290000, 0.2316849000, 0.4676892000, 1.1034360000", \ - "0.1486422000, 0.1552090000, 0.1727130000, 0.2121963000, 0.2980063000, 0.5312255000, 1.1702352000", \ - "0.2314629000, 0.2418138000, 0.2673428000, 0.3277213000, 0.4495577000, 0.6873617000, 1.3195592000", \ - "0.3809931000, 0.3952734000, 0.4330501000, 0.5234964000, 0.6999332000, 1.0386417000, 1.6873537000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0290024000, 0.0309856000, 0.0364984000, 0.0514875000, 0.0931238000, 0.2086543000, 0.5267784000", \ - "0.0287050000, 0.0307349000, 0.0362645000, 0.0515165000, 0.0930512000, 0.2084686000, 0.5268773000", \ - "0.0295623000, 0.0314208000, 0.0365434000, 0.0510389000, 0.0929296000, 0.2084748000, 0.5272387000", \ - "0.0397826000, 0.0419424000, 0.0479344000, 0.0611182000, 0.0965026000, 0.2084848000, 0.5272864000", \ - "0.0606056000, 0.0635027000, 0.0708340000, 0.0880658000, 0.1274326000, 0.2225307000, 0.5267379000", \ - "0.0987939000, 0.1032127000, 0.1143755000, 0.1399084000, 0.1924440000, 0.2997649000, 0.5580006000", \ - "0.1681321000, 0.1747267000, 0.1912515000, 0.2295074000, 0.3092683000, 0.4578769000, 0.7370197000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013757800, 0.0037855300, 0.0104161000, 0.0286605000, 0.0788608000, 0.2169900000"); - values("0.0977246000, 0.1035869000, 0.1196392000, 0.1636482000, 0.2832556000, 0.6110699000, 1.5128699000", \ - "0.0976466000, 0.1035053000, 0.1195796000, 0.1635614000, 0.2830833000, 0.6114327000, 1.5172938000", \ - "0.0969893000, 0.1029724000, 0.1193147000, 0.1635135000, 0.2832414000, 0.6106659000, 1.5181525000", \ - "0.1056574000, 0.1102348000, 0.1235511000, 0.1638322000, 0.2832816000, 0.6112895000, 1.5116975000", \ - "0.1416384000, 0.1449202000, 0.1552983000, 0.1874898000, 0.2894290000, 0.6104517000, 1.5189612000", \ - "0.2018482000, 0.2073203000, 0.2220324000, 0.2603753000, 0.3512148000, 0.6251949000, 1.5188468000", \ - "0.3061494000, 0.3134524000, 0.3333440000, 0.3858588000, 0.5057956000, 0.7639395000, 1.5396355000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2a_1") { - leakage_power () { - value : 0.0009469000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0061247000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0006840000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0011182000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0012680000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0064458000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0010052000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0014394000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0012611000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0064388000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0009982000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0014324000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0064277000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0061389000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0064277000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0064277000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o2bb2a"; - cell_leakage_power : 0.0034115550; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0013960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0021713000, 0.0021716000, 0.0021724000, 0.0021729000, 0.0021742000, 0.0021771000, 0.0021839000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002173300, -0.002171400, -0.002167100, -0.002167200, -0.002167300, -0.002167600, -0.002168300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014330000; - } - pin ("A2_N") { - capacitance : 0.0014870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024762000, 0.0024777000, 0.0024812000, 0.0024814000, 0.0024819000, 0.0024831000, 0.0024859000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001848700, -0.001849900, -0.001852700, -0.001848300, -0.001838300, -0.001815100, -0.001761600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015250000; - } - pin ("B1") { - capacitance : 0.0014810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014320000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019613000, 0.0019577000, 0.0019495000, 0.0019504000, 0.0019525000, 0.0019573000, 0.0019685000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001821000, -0.001843600, -0.001895600, -0.001896600, -0.001898800, -0.001903800, -0.001915600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015290000; - } - pin ("B2") { - capacitance : 0.0016130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0015759000, 0.0015725000, 0.0015645000, 0.0015674000, 0.0015742000, 0.0015898000, 0.0016258000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001199200, -0.001204100, -0.001215600, -0.001214800, -0.001212800, -0.001208100, -0.001197500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017040000; - } - pin ("X") { - direction : "output"; - function : "(!A1_N&B1) | (!A2_N&B1) | (!A1_N&B2) | (!A2_N&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0132979000, 0.0122889000, 0.0096751000, 0.0018116000, -0.020589700, -0.080360400, -0.236592700", \ - "0.0132631000, 0.0122492000, 0.0096409000, 0.0017872000, -0.020631700, -0.080395100, -0.236625100", \ - "0.0131271000, 0.0121037000, 0.0094653000, 0.0016684000, -0.020743100, -0.080515900, -0.236735800", \ - "0.0128810000, 0.0118683000, 0.0092517000, 0.0014164000, -0.020994500, -0.080753800, -0.236970600", \ - "0.0126249000, 0.0116086000, 0.0089894000, 0.0011171000, -0.021277900, -0.081036300, -0.237235000", \ - "0.0142742000, 0.0130540000, 0.0098473000, 0.0012673000, -0.021480700, -0.081238100, -0.237419700", \ - "0.0146559000, 0.0134600000, 0.0102200000, 0.0016439000, -0.021093200, -0.080919500, -0.237217200"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0182309000, 0.0196103000, 0.0232110000, 0.0322545000, 0.0552978000, 0.1149186000, 0.2692981000", \ - "0.0181444000, 0.0195222000, 0.0231243000, 0.0321863000, 0.0552018000, 0.1148387000, 0.2691862000", \ - "0.0180265000, 0.0194373000, 0.0230076000, 0.0320565000, 0.0551502000, 0.1146865000, 0.2690846000", \ - "0.0179001000, 0.0192834000, 0.0228779000, 0.0319248000, 0.0549696000, 0.1145761000, 0.2690827000", \ - "0.0177410000, 0.0191249000, 0.0227164000, 0.0317596000, 0.0548163000, 0.1144019000, 0.2688229000", \ - "0.0177055000, 0.0191106000, 0.0227146000, 0.0316638000, 0.0547575000, 0.1144054000, 0.2690377000", \ - "0.0185263000, 0.0198592000, 0.0232877000, 0.0322326000, 0.0551955000, 0.1144428000, 0.2689608000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0129988000, 0.0119675000, 0.0093307000, 0.0015261000, -0.020900900, -0.080704100, -0.236951300", \ - "0.0129222000, 0.0119035000, 0.0092381000, 0.0014234000, -0.020989600, -0.080795900, -0.237039000", \ - "0.0127316000, 0.0117108000, 0.0090700000, 0.0012675000, -0.021158400, -0.080961200, -0.237209400", \ - "0.0124816000, 0.0114747000, 0.0088454000, 0.0010026000, -0.021418300, -0.081214700, -0.237466000", \ - "0.0121957000, 0.0111810000, 0.0085544000, 0.0006968000, -0.021710300, -0.081501400, -0.237734100", \ - "0.0139634000, 0.0127071000, 0.0095579000, 0.0009737000, -0.021753800, -0.081522000, -0.237765700", \ - "0.0144765000, 0.0131930000, 0.0098888000, 0.0013617000, -0.021364500, -0.081183600, -0.237467600"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0161525000, 0.0175689000, 0.0211830000, 0.0301666000, 0.0532197000, 0.1127047000, 0.2685952000", \ - "0.0160213000, 0.0174147000, 0.0210124000, 0.0300268000, 0.0530146000, 0.1131132000, 0.2671805000", \ - "0.0157752000, 0.0172070000, 0.0207752000, 0.0297868000, 0.0527857000, 0.1122284000, 0.2669700000", \ - "0.0156004000, 0.0170166000, 0.0206305000, 0.0296181000, 0.0526765000, 0.1121727000, 0.2668351000", \ - "0.0154503000, 0.0168669000, 0.0204807000, 0.0294615000, 0.0525133000, 0.1120095000, 0.2665717000", \ - "0.0153957000, 0.0168238000, 0.0204845000, 0.0294850000, 0.0524706000, 0.1125376000, 0.2666304000", \ - "0.0161748000, 0.0174755000, 0.0209497000, 0.0298755000, 0.0527565000, 0.1122533000, 0.2682711000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0091362000, 0.0079835000, 0.0051329000, -0.002810800, -0.025039300, -0.084629400, -0.240742700", \ - "0.0090902000, 0.0079445000, 0.0050686000, -0.002866500, -0.025137200, -0.084688200, -0.240810900", \ - "0.0090059000, 0.0078522000, 0.0049801000, -0.002952100, -0.025189300, -0.084783300, -0.240898500", \ - "0.0088847000, 0.0077222000, 0.0048684000, -0.003080300, -0.025297400, -0.084898700, -0.241008400", \ - "0.0087414000, 0.0075837000, 0.0047402000, -0.003207900, -0.025453700, -0.085005900, -0.241095300", \ - "0.0086927000, 0.0075303000, 0.0046648000, -0.003354900, -0.025573400, -0.085117900, -0.241177600", \ - "0.0108324000, 0.0094506000, 0.0059998000, -0.002451700, -0.025397800, -0.084974600, -0.241042100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0120583000, 0.0134499000, 0.0170484000, 0.0260952000, 0.0491132000, 0.1086223000, 0.2629464000", \ - "0.0120395000, 0.0134315000, 0.0170262000, 0.0260738000, 0.0491251000, 0.1086314000, 0.2630842000", \ - "0.0120547000, 0.0134405000, 0.0170397000, 0.0260772000, 0.0490964000, 0.1086264000, 0.2630045000", \ - "0.0119926000, 0.0134049000, 0.0169916000, 0.0260020000, 0.0490445000, 0.1085428000, 0.2631586000", \ - "0.0119404000, 0.0133483000, 0.0169173000, 0.0258307000, 0.0488877000, 0.1084169000, 0.2631138000", \ - "0.0122653000, 0.0135492000, 0.0170003000, 0.0257080000, 0.0487265000, 0.1080324000, 0.2628993000", \ - "0.0126659000, 0.0139865000, 0.0173220000, 0.0260913000, 0.0491267000, 0.1086554000, 0.2622193000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0090508000, 0.0079057000, 0.0050216000, -0.002897900, -0.025159000, -0.084734800, -0.240855600", \ - "0.0089342000, 0.0077724000, 0.0048893000, -0.003024500, -0.025289800, -0.084861600, -0.240993100", \ - "0.0087704000, 0.0076074000, 0.0047549000, -0.003206600, -0.025437500, -0.084987300, -0.241093800", \ - "0.0086518000, 0.0075015000, 0.0046328000, -0.003325900, -0.025566700, -0.085159400, -0.241250500", \ - "0.0084766000, 0.0073473000, 0.0044728000, -0.003495300, -0.025718500, -0.085304500, -0.241405300", \ - "0.0086382000, 0.0074472000, 0.0045104000, -0.003539100, -0.025817000, -0.085355700, -0.241391000", \ - "0.0111800000, 0.0097104000, 0.0061832000, -0.002736000, -0.025612600, -0.085005900, -0.240983400"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013029390, 0.0033953010, 0.0088477440, 0.0230561400, 0.0600815100, 0.1565651000"); - values("0.0107440000, 0.0121711000, 0.0157286000, 0.0247626000, 0.0478216000, 0.1072496000, 0.2619823000", \ - "0.0107388000, 0.0121677000, 0.0157319000, 0.0247750000, 0.0478149000, 0.1073010000, 0.2621113000", \ - "0.0106702000, 0.0120895000, 0.0156861000, 0.0247472000, 0.0477635000, 0.1072657000, 0.2617708000", \ - "0.0105193000, 0.0119308000, 0.0155309000, 0.0245752000, 0.0475645000, 0.1070476000, 0.2609182000", \ - "0.0104379000, 0.0118329000, 0.0153949000, 0.0242603000, 0.0473057000, 0.1069211000, 0.2607610000", \ - "0.0107129000, 0.0120706000, 0.0154875000, 0.0240703000, 0.0471220000, 0.1062434000, 0.2613876000", \ - "0.0108840000, 0.0121709000, 0.0155460000, 0.0244839000, 0.0474873000, 0.1070670000, 0.2605014000"); - } - } - max_capacitance : 0.1565650000; - max_transition : 1.5068560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1747831000, 0.1822042000, 0.1976759000, 0.2281529000, 0.2872887000, 0.4170549000, 0.7433424000", \ - "0.1793046000, 0.1866450000, 0.2021666000, 0.2327316000, 0.2918354000, 0.4215826000, 0.7477512000", \ - "0.1881258000, 0.1954387000, 0.2109647000, 0.2415486000, 0.3006643000, 0.4304822000, 0.7562287000", \ - "0.2062392000, 0.2135540000, 0.2290667000, 0.2596215000, 0.3187653000, 0.4485328000, 0.7748918000", \ - "0.2365108000, 0.2437681000, 0.2593066000, 0.2898997000, 0.3490209000, 0.4787660000, 0.8043369000", \ - "0.2752109000, 0.2825912000, 0.2980507000, 0.3286287000, 0.3877365000, 0.5172437000, 0.8429198000", \ - "0.3060983000, 0.3135393000, 0.3290733000, 0.3597831000, 0.4191321000, 0.5490128000, 0.8745828000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1954100000, 0.2033054000, 0.2210151000, 0.2607194000, 0.3571787000, 0.6042001000, 1.2444783000", \ - "0.2004130000, 0.2083178000, 0.2260153000, 0.2657234000, 0.3621298000, 0.6092134000, 1.2493935000", \ - "0.2137760000, 0.2217851000, 0.2394886000, 0.2792140000, 0.3754442000, 0.6227099000, 1.2618707000", \ - "0.2461945000, 0.2541252000, 0.2718642000, 0.3114905000, 0.4080343000, 0.6548198000, 1.2957941000", \ - "0.3204366000, 0.3283715000, 0.3461184000, 0.3857320000, 0.4822401000, 0.7291921000, 1.3692176000", \ - "0.4565633000, 0.4646252000, 0.4824460000, 0.5222222000, 0.6187115000, 0.8659051000, 1.5064160000", \ - "0.6812990000, 0.6896325000, 0.7077652000, 0.7478507000, 0.8444265000, 1.0913519000, 1.7317399000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0266981000, 0.0319759000, 0.0443314000, 0.0700378000, 0.1290022000, 0.2863073000, 0.7174399000", \ - "0.0265188000, 0.0321056000, 0.0443339000, 0.0702939000, 0.1286604000, 0.2861806000, 0.7193169000", \ - "0.0266750000, 0.0320422000, 0.0442721000, 0.0703610000, 0.1293198000, 0.2856748000, 0.7212435000", \ - "0.0265438000, 0.0321160000, 0.0443228000, 0.0701704000, 0.1290687000, 0.2862816000, 0.7178351000", \ - "0.0264720000, 0.0320510000, 0.0443475000, 0.0703046000, 0.1290758000, 0.2856283000, 0.7159274000", \ - "0.0271037000, 0.0322427000, 0.0444733000, 0.0704118000, 0.1289423000, 0.2843390000, 0.7144650000", \ - "0.0275144000, 0.0331981000, 0.0454245000, 0.0713258000, 0.1296922000, 0.2856671000, 0.7112647000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0280574000, 0.0354989000, 0.0540217000, 0.1029975000, 0.2348206000, 0.5865520000, 1.4990541000", \ - "0.0280463000, 0.0354931000, 0.0540410000, 0.1029738000, 0.2348634000, 0.5865787000, 1.4986635000", \ - "0.0279578000, 0.0355426000, 0.0540028000, 0.1029103000, 0.2352110000, 0.5861635000, 1.4959423000", \ - "0.0280224000, 0.0355339000, 0.0540507000, 0.1029903000, 0.2352697000, 0.5866022000, 1.5003567000", \ - "0.0280527000, 0.0355791000, 0.0541021000, 0.1030117000, 0.2348308000, 0.5864753000, 1.4975823000", \ - "0.0286433000, 0.0360805000, 0.0546526000, 0.1030767000, 0.2353927000, 0.5871966000, 1.5014983000", \ - "0.0306765000, 0.0377719000, 0.0560988000, 0.1044244000, 0.2360944000, 0.5832305000, 1.4972356000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1718149000, 0.1791239000, 0.1946648000, 0.2252377000, 0.2843424000, 0.4140978000, 0.7397795000", \ - "0.1760200000, 0.1833469000, 0.1988478000, 0.2294494000, 0.2885383000, 0.4182934000, 0.7441568000", \ - "0.1857252000, 0.1933078000, 0.2088255000, 0.2393837000, 0.2984892000, 0.4282556000, 0.7539487000", \ - "0.2068073000, 0.2141793000, 0.2296303000, 0.2601697000, 0.3192824000, 0.4489373000, 0.7751674000", \ - "0.2382228000, 0.2455886000, 0.2612188000, 0.2917665000, 0.3508404000, 0.4806560000, 0.8064917000", \ - "0.2753466000, 0.2826991000, 0.2981407000, 0.3287678000, 0.3880169000, 0.5178768000, 0.8439305000", \ - "0.3050815000, 0.3125858000, 0.3281260000, 0.3588537000, 0.4182983000, 0.5483015000, 0.8738453000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1823399000, 0.1903193000, 0.2080309000, 0.2476420000, 0.3438561000, 0.5908672000, 1.2316983000", \ - "0.1871670000, 0.1950688000, 0.2127449000, 0.2524628000, 0.3486765000, 0.5966623000, 1.2367670000", \ - "0.1994035000, 0.2073928000, 0.2250182000, 0.2646956000, 0.3610250000, 0.6089813000, 1.2490313000", \ - "0.2315293000, 0.2395067000, 0.2572215000, 0.2968399000, 0.3930667000, 0.6401175000, 1.2795891000", \ - "0.3034008000, 0.3113514000, 0.3290689000, 0.3687430000, 0.4649729000, 0.7121254000, 1.3520109000", \ - "0.4287100000, 0.4366483000, 0.4545025000, 0.4940766000, 0.5903755000, 0.8376503000, 1.4784302000", \ - "0.6345541000, 0.6428478000, 0.6609933000, 0.7010966000, 0.7977978000, 1.0450530000, 1.6851659000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0267060000, 0.0320211000, 0.0442900000, 0.0701760000, 0.1292702000, 0.2857304000, 0.7214898000", \ - "0.0265656000, 0.0322422000, 0.0443073000, 0.0702769000, 0.1292036000, 0.2860728000, 0.7166823000", \ - "0.0267002000, 0.0320536000, 0.0442503000, 0.0701670000, 0.1292701000, 0.2857144000, 0.7213596000", \ - "0.0266073000, 0.0319854000, 0.0443221000, 0.0702762000, 0.1290083000, 0.2859004000, 0.7173418000", \ - "0.0268174000, 0.0324350000, 0.0446286000, 0.0705201000, 0.1294622000, 0.2849828000, 0.7179719000", \ - "0.0269733000, 0.0326381000, 0.0447369000, 0.0707516000, 0.1290818000, 0.2847169000, 0.7205607000", \ - "0.0277978000, 0.0332250000, 0.0454953000, 0.0714532000, 0.1298793000, 0.2860526000, 0.7121300000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0280044000, 0.0352228000, 0.0539162000, 0.1027914000, 0.2348414000, 0.5848544000, 1.5003457000", \ - "0.0278425000, 0.0353335000, 0.0537770000, 0.1024682000, 0.2345411000, 0.5858312000, 1.5014783000", \ - "0.0278181000, 0.0352757000, 0.0538098000, 0.1026501000, 0.2345710000, 0.5858788000, 1.5014826000", \ - "0.0280097000, 0.0352331000, 0.0539197000, 0.1027845000, 0.2349023000, 0.5857267000, 1.4963015000", \ - "0.0279582000, 0.0354495000, 0.0538251000, 0.1028084000, 0.2349235000, 0.5854844000, 1.4983420000", \ - "0.0287766000, 0.0362607000, 0.0545436000, 0.1031911000, 0.2346143000, 0.5861999000, 1.5018486000", \ - "0.0311017000, 0.0382011000, 0.0561222000, 0.1043576000, 0.2355106000, 0.5843179000, 1.4996204000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.2469520000, 0.2562652000, 0.2751664000, 0.3103695000, 0.3761889000, 0.5121898000, 0.8396872000", \ - "0.2516666000, 0.2609424000, 0.2797729000, 0.3151898000, 0.3807041000, 0.5166041000, 0.8447678000", \ - "0.2632605000, 0.2725966000, 0.2913931000, 0.3267544000, 0.3921929000, 0.5284463000, 0.8564276000", \ - "0.2884979000, 0.2978128000, 0.3167064000, 0.3518948000, 0.4178003000, 0.5537301000, 0.8812272000", \ - "0.3459383000, 0.3552574000, 0.3741865000, 0.4093498000, 0.4751767000, 0.6110867000, 0.9392049000", \ - "0.4706694000, 0.4805629000, 0.5000905000, 0.5365949000, 0.6030476000, 0.7400314000, 1.0679205000", \ - "0.6889367000, 0.7007448000, 0.7233037000, 0.7648226000, 0.8381817000, 0.9805624000, 1.3102491000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.1034677000, 0.1113654000, 0.1290944000, 0.1687223000, 0.2651357000, 0.5118769000, 1.1517377000", \ - "0.1082623000, 0.1161671000, 0.1339011000, 0.1735276000, 0.2699362000, 0.5164348000, 1.1573849000", \ - "0.1179533000, 0.1258503000, 0.1435679000, 0.1832031000, 0.2796636000, 0.5263702000, 1.1667548000", \ - "0.1375101000, 0.1454655000, 0.1630420000, 0.2026616000, 0.2987771000, 0.5453704000, 1.1866361000", \ - "0.1744831000, 0.1828666000, 0.2010855000, 0.2411911000, 0.3376393000, 0.5844222000, 1.2262152000", \ - "0.2287561000, 0.2381340000, 0.2580323000, 0.2997027000, 0.3966743000, 0.6434917000, 1.2848429000", \ - "0.2835341000, 0.2959726000, 0.3205094000, 0.3661919000, 0.4646923000, 0.7121100000, 1.3515394000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0396482000, 0.0453757000, 0.0576905000, 0.0831779000, 0.1434142000, 0.2963431000, 0.7214771000", \ - "0.0398636000, 0.0456800000, 0.0577463000, 0.0837104000, 0.1433870000, 0.2973128000, 0.7246211000", \ - "0.0398470000, 0.0455164000, 0.0575903000, 0.0836310000, 0.1433736000, 0.2961562000, 0.7207623000", \ - "0.0402482000, 0.0453798000, 0.0576838000, 0.0831880000, 0.1433573000, 0.2963509000, 0.7214362000", \ - "0.0397036000, 0.0453580000, 0.0585506000, 0.0845723000, 0.1430768000, 0.2966659000, 0.7218802000", \ - "0.0442515000, 0.0504317000, 0.0617267000, 0.0869812000, 0.1460841000, 0.2967996000, 0.7212907000", \ - "0.0554267000, 0.0623083000, 0.0752871000, 0.1021434000, 0.1604110000, 0.3072513000, 0.7237181000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0276809000, 0.0351451000, 0.0538298000, 0.1027803000, 0.2348849000, 0.5863917000, 1.4981898000", \ - "0.0276756000, 0.0351461000, 0.0538536000, 0.1028332000, 0.2354431000, 0.5867093000, 1.5009703000", \ - "0.0277175000, 0.0351476000, 0.0538025000, 0.1026464000, 0.2351918000, 0.5865755000, 1.5000717000", \ - "0.0276749000, 0.0351200000, 0.0537907000, 0.1027881000, 0.2352239000, 0.5847653000, 1.5014634000", \ - "0.0300046000, 0.0373537000, 0.0556492000, 0.1039133000, 0.2353286000, 0.5860576000, 1.5023897000", \ - "0.0361669000, 0.0436034000, 0.0612922000, 0.1073136000, 0.2365359000, 0.5840796000, 1.4985082000", \ - "0.0493618000, 0.0574102000, 0.0749436000, 0.1185063000, 0.2400540000, 0.5871469000, 1.4963999000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.2393855000, 0.2486258000, 0.2674478000, 0.3028360000, 0.3683360000, 0.5042560000, 0.8323212000", \ - "0.2418705000, 0.2512169000, 0.2700729000, 0.3054426000, 0.3709569000, 0.5068981000, 0.8349448000", \ - "0.2515813000, 0.2609240000, 0.2799271000, 0.3151299000, 0.3806510000, 0.5166705000, 0.8446570000", \ - "0.2791056000, 0.2884449000, 0.3073452000, 0.3425137000, 0.4081665000, 0.5441930000, 0.8718795000", \ - "0.3468811000, 0.3562576000, 0.3751049000, 0.4102952000, 0.4761337000, 0.6120935000, 0.9399915000", \ - "0.5027678000, 0.5124607000, 0.5321569000, 0.5680553000, 0.6343622000, 0.7709657000, 1.0992821000", \ - "0.7689061000, 0.7814785000, 0.8059790000, 0.8492445000, 0.9227006000, 1.0643003000, 1.3948794000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0933748000, 0.1010790000, 0.1182161000, 0.1573754000, 0.2533926000, 0.5007736000, 1.1406337000", \ - "0.0984477000, 0.1061547000, 0.1233036000, 0.1624755000, 0.2585459000, 0.5044825000, 1.1439807000", \ - "0.1081406000, 0.1158545000, 0.1331028000, 0.1722575000, 0.2681634000, 0.5148293000, 1.1567739000", \ - "0.1271941000, 0.1348381000, 0.1520202000, 0.1911113000, 0.2872388000, 0.5335183000, 1.1725980000", \ - "0.1606489000, 0.1688700000, 0.1867776000, 0.2265502000, 0.3225857000, 0.5697707000, 1.2090565000", \ - "0.2050553000, 0.2146565000, 0.2345513000, 0.2757956000, 0.3724934000, 0.6189491000, 1.2601588000", \ - "0.2392342000, 0.2520955000, 0.2773332000, 0.3237824000, 0.4218497000, 0.6682926000, 1.3087291000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0397213000, 0.0456557000, 0.0576840000, 0.0836476000, 0.1433893000, 0.2968059000, 0.7211844000", \ - "0.0399015000, 0.0456460000, 0.0575396000, 0.0835869000, 0.1434120000, 0.2967865000, 0.7259152000", \ - "0.0402423000, 0.0453919000, 0.0583514000, 0.0834510000, 0.1436296000, 0.2963730000, 0.7213016000", \ - "0.0401335000, 0.0461595000, 0.0577126000, 0.0832233000, 0.1435141000, 0.2956551000, 0.7236760000", \ - "0.0398077000, 0.0456912000, 0.0577769000, 0.0834982000, 0.1434464000, 0.2957518000, 0.7211122000", \ - "0.0443177000, 0.0510683000, 0.0618058000, 0.0873154000, 0.1455839000, 0.2972673000, 0.7215502000", \ - "0.0631224000, 0.0696097000, 0.0828170000, 0.1070287000, 0.1617173000, 0.3073542000, 0.7241814000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013029400, 0.0033953000, 0.0088477400, 0.0230561000, 0.0600815000, 0.1565650000"); - values("0.0263727000, 0.0336775000, 0.0523497000, 0.1013363000, 0.2345106000, 0.5859489000, 1.5040359000", \ - "0.0263817000, 0.0336862000, 0.0523422000, 0.1012727000, 0.2345654000, 0.5859087000, 1.5068560000", \ - "0.0264219000, 0.0337348000, 0.0523188000, 0.1015225000, 0.2338467000, 0.5867575000, 1.4994473000", \ - "0.0266510000, 0.0338887000, 0.0523753000, 0.1013893000, 0.2346306000, 0.5861374000, 1.5046449000", \ - "0.0294698000, 0.0366875000, 0.0548925000, 0.1028895000, 0.2345702000, 0.5849903000, 1.5036343000", \ - "0.0365511000, 0.0442597000, 0.0612943000, 0.1069703000, 0.2359311000, 0.5829909000, 1.5035132000", \ - "0.0512754000, 0.0596937000, 0.0768349000, 0.1192409000, 0.2400896000, 0.5857256000, 1.4978003000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2a_2") { - leakage_power () { - value : 0.0016547000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0043873000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0012479000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0019508000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0020059000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0047385000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0015991000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0023020000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0019812000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0047135000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0015741000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0022770000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0048489000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0045602000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0048489000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0048489000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o2bb2a"; - cell_leakage_power : 0.0030961860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0016650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030256000, 0.0030245000, 0.0030219000, 0.0030227000, 0.0030245000, 0.0030287000, 0.0030384000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003024600, -0.003023900, -0.003022200, -0.003022200, -0.003022300, -0.003022300, -0.003022500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017300000; - } - pin ("A2_N") { - capacitance : 0.0017540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033227000, 0.0033220000, 0.0033203000, 0.0033205000, 0.0033208000, 0.0033217000, 0.0033237000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002691200, -0.002692800, -0.002696600, -0.002692200, -0.002682200, -0.002659000, -0.002605700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018110000; - } - pin ("B1") { - capacitance : 0.0017220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028086000, 0.0028065000, 0.0028018000, 0.0028032000, 0.0028065000, 0.0028142000, 0.0028319000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002589100, -0.002627800, -0.002717100, -0.002718400, -0.002721400, -0.002728300, -0.002744300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017970000; - } - pin ("B2") { - capacitance : 0.0018810000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022241000, 0.0022166000, 0.0021992000, 0.0022041000, 0.0022155000, 0.0022416000, 0.0023020000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001647600, -0.001652300, -0.001663200, -0.001662800, -0.001661700, -0.001659300, -0.001653700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020050000; - } - pin ("X") { - direction : "output"; - function : "(!A1_N&B1) | (!A2_N&B1) | (!A1_N&B2) | (!A2_N&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0183625000, 0.0171574000, 0.0137313000, 0.0028769000, -0.032722500, -0.140147000, -0.452640900", \ - "0.0183067000, 0.0170055000, 0.0136278000, 0.0027821000, -0.032804600, -0.140224500, -0.452707300", \ - "0.0181233000, 0.0168539000, 0.0134574000, 0.0026401000, -0.032958500, -0.140368200, -0.452850300", \ - "0.0178549000, 0.0166251000, 0.0131416000, 0.0023928000, -0.033234900, -0.140644300, -0.453124300", \ - "0.0175702000, 0.0163133000, 0.0128517000, 0.0020391000, -0.033547400, -0.140969400, -0.453428600", \ - "0.0209832000, 0.0195286000, 0.0153338000, 0.0029361000, -0.033762600, -0.141164400, -0.453621100", \ - "0.0215397000, 0.0200943000, 0.0159874000, 0.0034525000, -0.033269400, -0.140839600, -0.453442800"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0242507000, 0.0259105000, 0.0306188000, 0.0439133000, 0.0814043000, 0.1887455000, 0.4983208000", \ - "0.0241713000, 0.0258340000, 0.0304787000, 0.0438218000, 0.0813480000, 0.1885729000, 0.4982400000", \ - "0.0240211000, 0.0256137000, 0.0303231000, 0.0436949000, 0.0811025000, 0.1884908000, 0.4979099000", \ - "0.0238916000, 0.0255307000, 0.0302285000, 0.0435357000, 0.0810256000, 0.1883051000, 0.4978451000", \ - "0.0237270000, 0.0253589000, 0.0300690000, 0.0433631000, 0.0808006000, 0.1881389000, 0.4977007000", \ - "0.0237353000, 0.0253571000, 0.0300734000, 0.0434013000, 0.0808246000, 0.1880735000, 0.4969452000", \ - "0.0250240000, 0.0266280000, 0.0311777000, 0.0441344000, 0.0813155000, 0.1886959000, 0.4970882000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0180586000, 0.0168167000, 0.0134294000, 0.0025693000, -0.033030500, -0.140497200, -0.453043900", \ - "0.0179523000, 0.0167194000, 0.0132587000, 0.0025022000, -0.033138600, -0.140615500, -0.453149300", \ - "0.0177230000, 0.0164575000, 0.0130521000, 0.0022546000, -0.033364800, -0.140833100, -0.453362000", \ - "0.0174448000, 0.0161671000, 0.0127207000, 0.0019520000, -0.033694100, -0.141151900, -0.453672500", \ - "0.0171513000, 0.0158949000, 0.0123767000, 0.0015555000, -0.034021800, -0.141471800, -0.453989900", \ - "0.0206912000, 0.0192637000, 0.0150109000, 0.0025799000, -0.034038500, -0.141447100, -0.453969000", \ - "0.0213875000, 0.0198720000, 0.0156955000, 0.0032664000, -0.033427300, -0.141011100, -0.453602000"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0220417000, 0.0236998000, 0.0283853000, 0.0417317000, 0.0791153000, 0.1864904000, 0.4979394000", \ - "0.0218792000, 0.0235455000, 0.0282890000, 0.0415568000, 0.0789924000, 0.1862130000, 0.4977007000", \ - "0.0216883000, 0.0233330000, 0.0280214000, 0.0414108000, 0.0787622000, 0.1859670000, 0.4946817000", \ - "0.0214956000, 0.0231585000, 0.0278349000, 0.0411859000, 0.0785591000, 0.1859449000, 0.4973912000", \ - "0.0213895000, 0.0230226000, 0.0277402000, 0.0410626000, 0.0784666000, 0.1856072000, 0.4972811000", \ - "0.0213155000, 0.0230011000, 0.0277774000, 0.0411981000, 0.0784454000, 0.1857947000, 0.4972033000", \ - "0.0226580000, 0.0242289000, 0.0288046000, 0.0417177000, 0.0788780000, 0.1862773000, 0.4950888000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0130980000, 0.0115828000, 0.0076397000, -0.003602000, -0.039171000, -0.146224800, -0.458559200", \ - "0.0129117000, 0.0113893000, 0.0074553000, -0.003737800, -0.039240800, -0.146295500, -0.458653000", \ - "0.0128561000, 0.0113182000, 0.0074886000, -0.003829300, -0.039322900, -0.146369800, -0.458716300", \ - "0.0128674000, 0.0113312000, 0.0073978000, -0.003903500, -0.039365100, -0.146474700, -0.458807200", \ - "0.0126460000, 0.0111132000, 0.0071619000, -0.004100900, -0.039577400, -0.146576200, -0.458947600", \ - "0.0125978000, 0.0110243000, 0.0070848000, -0.004300600, -0.039737200, -0.146773800, -0.459051300", \ - "0.0166726000, 0.0149261000, 0.0102533000, -0.002732300, -0.039244200, -0.146604200, -0.458893800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0178477000, 0.0194800000, 0.0241178000, 0.0374786000, 0.0749016000, 0.1822468000, 0.4913567000", \ - "0.0177732000, 0.0194126000, 0.0240924000, 0.0374817000, 0.0748369000, 0.1820538000, 0.4911447000", \ - "0.0178008000, 0.0194194000, 0.0242091000, 0.0374592000, 0.0749082000, 0.1822840000, 0.4917903000", \ - "0.0177010000, 0.0193326000, 0.0240469000, 0.0373912000, 0.0748087000, 0.1821043000, 0.4912349000", \ - "0.0177021000, 0.0193169000, 0.0239462000, 0.0372236000, 0.0745204000, 0.1818987000, 0.4911859000", \ - "0.0183396000, 0.0199097000, 0.0243820000, 0.0371003000, 0.0744221000, 0.1814752000, 0.4907994000", \ - "0.0191323000, 0.0206157000, 0.0249398000, 0.0378048000, 0.0749647000, 0.1820160000, 0.4905522000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0127682000, 0.0112646000, 0.0073524000, -0.003942400, -0.039412600, -0.146530800, -0.458799900", \ - "0.0126676000, 0.0111497000, 0.0072281000, -0.004076300, -0.039520300, -0.146601900, -0.458933900", \ - "0.0125650000, 0.0110440000, 0.0071164000, -0.004182000, -0.039629400, -0.146744300, -0.459073000", \ - "0.0123962000, 0.0108792000, 0.0069412000, -0.004396100, -0.039858700, -0.146904400, -0.459251400", \ - "0.0122129000, 0.0106638000, 0.0067118000, -0.004644300, -0.040140400, -0.147137400, -0.459432400", \ - "0.0124961000, 0.0109200000, 0.0068444000, -0.004667900, -0.040279300, -0.147253900, -0.459483500", \ - "0.0170778000, 0.0152897000, 0.0103987000, -0.002099900, -0.039732900, -0.146825400, -0.459015900"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014478780, 0.0041927010, 0.0121410400, 0.0351574900, 0.1018075000, 0.2948097000"); - values("0.0158132000, 0.0174619000, 0.0221170000, 0.0354733000, 0.0728493000, 0.1801299000, 0.4899672000", \ - "0.0157917000, 0.0174308000, 0.0221648000, 0.0355317000, 0.0727794000, 0.1801473000, 0.4898824000", \ - "0.0157023000, 0.0173036000, 0.0220787000, 0.0354241000, 0.0728896000, 0.1800872000, 0.4901093000", \ - "0.0155175000, 0.0171479000, 0.0218928000, 0.0351881000, 0.0726642000, 0.1798335000, 0.4898772000", \ - "0.0154306000, 0.0170873000, 0.0217689000, 0.0348594000, 0.0722285000, 0.1793629000, 0.4873709000", \ - "0.0159089000, 0.0174889000, 0.0221362000, 0.0348725000, 0.0719431000, 0.1789233000, 0.4891479000", \ - "0.0164315000, 0.0179178000, 0.0222789000, 0.0353049000, 0.0725714000, 0.1796358000, 0.4873407000"); - } - } - max_capacitance : 0.2948100000; - max_transition : 1.5046330000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1776424000, 0.1831631000, 0.1957142000, 0.2218509000, 0.2744086000, 0.3907286000, 0.7026206000", \ - "0.1819492000, 0.1874467000, 0.1999821000, 0.2261091000, 0.2787053000, 0.3950168000, 0.7069398000", \ - "0.1906723000, 0.1961994000, 0.2087083000, 0.2348702000, 0.2874403000, 0.4037399000, 0.7155166000", \ - "0.2093415000, 0.2148656000, 0.2273615000, 0.2535127000, 0.3061220000, 0.4223409000, 0.7336758000", \ - "0.2416656000, 0.2471439000, 0.2596723000, 0.2858435000, 0.3385395000, 0.4548402000, 0.7664458000", \ - "0.2838541000, 0.2893859000, 0.3019125000, 0.3280817000, 0.3807379000, 0.4969698000, 0.8090016000", \ - "0.3219487000, 0.3275163000, 0.3401681000, 0.3664392000, 0.4194067000, 0.5359126000, 0.8475138000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.2054943000, 0.2126665000, 0.2288023000, 0.2644344000, 0.3500621000, 0.5851203000, 1.2611668000", \ - "0.2110705000, 0.2180980000, 0.2342371000, 0.2699084000, 0.3556624000, 0.5914653000, 1.2655607000", \ - "0.2243867000, 0.2313782000, 0.2475811000, 0.2833097000, 0.3688661000, 0.6039007000, 1.2800628000", \ - "0.2569989000, 0.2640387000, 0.2801822000, 0.3158200000, 0.4015767000, 0.6373529000, 1.3113569000", \ - "0.3273067000, 0.3343624000, 0.3504589000, 0.3861186000, 0.4718408000, 0.7076667000, 1.3817210000", \ - "0.4496219000, 0.4566840000, 0.4730262000, 0.5088254000, 0.5944770000, 0.8291325000, 1.5044216000", \ - "0.6520542000, 0.6592484000, 0.6757115000, 0.7115720000, 0.7972606000, 1.0322652000, 1.7084630000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0230581000, 0.0269982000, 0.0359603000, 0.0569252000, 0.1052272000, 0.2380673000, 0.6495873000", \ - "0.0232604000, 0.0270314000, 0.0360647000, 0.0567616000, 0.1051715000, 0.2383601000, 0.6514193000", \ - "0.0230818000, 0.0267703000, 0.0361299000, 0.0569637000, 0.1051712000, 0.2377863000, 0.6510983000", \ - "0.0230956000, 0.0271337000, 0.0361193000, 0.0569458000, 0.1051690000, 0.2382437000, 0.6512146000", \ - "0.0232536000, 0.0269451000, 0.0362134000, 0.0570613000, 0.1052061000, 0.2384473000, 0.6474702000", \ - "0.0234223000, 0.0271275000, 0.0364291000, 0.0571792000, 0.1052689000, 0.2369201000, 0.6494382000", \ - "0.0240502000, 0.0280693000, 0.0370227000, 0.0580026000, 0.1059306000, 0.2384952000, 0.6466745000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0276113000, 0.0331873000, 0.0471718000, 0.0844264000, 0.1946680000, 0.5279293000, 1.5003881000", \ - "0.0275770000, 0.0330951000, 0.0473344000, 0.0844741000, 0.1945625000, 0.5269872000, 1.4980938000", \ - "0.0276440000, 0.0333273000, 0.0471992000, 0.0844218000, 0.1948090000, 0.5278751000, 1.4999103000", \ - "0.0276148000, 0.0331728000, 0.0472568000, 0.0844310000, 0.1947279000, 0.5270134000, 1.4987659000", \ - "0.0276946000, 0.0332151000, 0.0471873000, 0.0844356000, 0.1947902000, 0.5271056000, 1.4992863000", \ - "0.0282273000, 0.0337643000, 0.0475367000, 0.0848329000, 0.1948976000, 0.5276566000, 1.4974140000", \ - "0.0290273000, 0.0347408000, 0.0485331000, 0.0855672000, 0.1951991000, 0.5261643000, 1.4935081000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1747517000, 0.1802567000, 0.1928186000, 0.2189141000, 0.2715226000, 0.3877764000, 0.6993863000", \ - "0.1787135000, 0.1842261000, 0.1967315000, 0.2229052000, 0.2754683000, 0.3917687000, 0.7034346000", \ - "0.1886893000, 0.1942179000, 0.2067183000, 0.2328621000, 0.2854387000, 0.4016887000, 0.7133933000", \ - "0.2107338000, 0.2162552000, 0.2287567000, 0.2549235000, 0.3074791000, 0.4237493000, 0.7354667000", \ - "0.2460835000, 0.2516131000, 0.2641580000, 0.2904148000, 0.3430575000, 0.4594060000, 0.7711927000", \ - "0.2890069000, 0.2945766000, 0.3071302000, 0.3333469000, 0.3861157000, 0.5024955000, 0.8146679000", \ - "0.3297805000, 0.3353780000, 0.3479694000, 0.3742969000, 0.4273650000, 0.5439210000, 0.8554237000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1953842000, 0.2023337000, 0.2184077000, 0.2541527000, 0.3396590000, 0.5746805000, 1.2504253000", \ - "0.2002793000, 0.2073093000, 0.2233928000, 0.2590496000, 0.3446456000, 0.5800994000, 1.2568443000", \ - "0.2135027000, 0.2205166000, 0.2366092000, 0.2723377000, 0.3577906000, 0.5922340000, 1.2674292000", \ - "0.2455148000, 0.2524736000, 0.2685185000, 0.3042791000, 0.3897782000, 0.6247659000, 1.3003685000", \ - "0.3129622000, 0.3198849000, 0.3359786000, 0.3717089000, 0.4572619000, 0.6919471000, 1.3681996000", \ - "0.4257625000, 0.4328115000, 0.4491470000, 0.4849787000, 0.5703948000, 0.8057566000, 1.4827208000", \ - "0.6104224000, 0.6176424000, 0.6340953000, 0.6700621000, 0.7557396000, 0.9908320000, 1.6644143000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0231096000, 0.0268346000, 0.0358283000, 0.0568505000, 0.1050694000, 0.2380285000, 0.6518684000", \ - "0.0230694000, 0.0268464000, 0.0361161000, 0.0569384000, 0.1052611000, 0.2378223000, 0.6470400000", \ - "0.0230437000, 0.0267757000, 0.0361283000, 0.0569561000, 0.1052292000, 0.2376579000, 0.6513702000", \ - "0.0233067000, 0.0270092000, 0.0361249000, 0.0568471000, 0.1051566000, 0.2379601000, 0.6511904000", \ - "0.0235598000, 0.0272309000, 0.0364731000, 0.0569352000, 0.1053712000, 0.2380519000, 0.6463532000", \ - "0.0235423000, 0.0274211000, 0.0363738000, 0.0574089000, 0.1053588000, 0.2370978000, 0.6500274000", \ - "0.0241541000, 0.0278984000, 0.0371773000, 0.0581180000, 0.1058979000, 0.2387495000, 0.6491538000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0276478000, 0.0331760000, 0.0470904000, 0.0844346000, 0.1941991000, 0.5283982000, 1.5004143000", \ - "0.0275726000, 0.0330797000, 0.0469745000, 0.0843783000, 0.1945652000, 0.5282400000, 1.5016745000", \ - "0.0277114000, 0.0332012000, 0.0470931000, 0.0843762000, 0.1945131000, 0.5267236000, 1.4961866000", \ - "0.0276165000, 0.0331236000, 0.0470608000, 0.0844387000, 0.1942514000, 0.5282527000, 1.4995060000", \ - "0.0276522000, 0.0332362000, 0.0470674000, 0.0844525000, 0.1944081000, 0.5264577000, 1.5010680000", \ - "0.0281987000, 0.0337075000, 0.0475885000, 0.0848326000, 0.1946462000, 0.5286042000, 1.5018727000", \ - "0.0292371000, 0.0347840000, 0.0486845000, 0.0856733000, 0.1947927000, 0.5259565000, 1.4982743000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.2217109000, 0.2287768000, 0.2443183000, 0.2749310000, 0.3329346000, 0.4555214000, 0.7699170000", \ - "0.2271297000, 0.2342055000, 0.2498050000, 0.2799429000, 0.3382409000, 0.4610039000, 0.7751373000", \ - "0.2396381000, 0.2466932000, 0.2621591000, 0.2927261000, 0.3508905000, 0.4734514000, 0.7877883000", \ - "0.2655754000, 0.2726410000, 0.2882830000, 0.3189200000, 0.3770681000, 0.4994763000, 0.8138001000", \ - "0.3234928000, 0.3305471000, 0.3461055000, 0.3767892000, 0.4349865000, 0.5578426000, 0.8719508000", \ - "0.4457336000, 0.4529252000, 0.4691388000, 0.5017698000, 0.5607645000, 0.6845243000, 0.9990465000", \ - "0.6539018000, 0.6626450000, 0.6824218000, 0.7196750000, 0.7865020000, 0.9182545000, 1.2356689000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1318017000, 0.1387662000, 0.1548081000, 0.1906048000, 0.2761617000, 0.5112028000, 1.1880111000", \ - "0.1363770000, 0.1433513000, 0.1595991000, 0.1953282000, 0.2808557000, 0.5155728000, 1.1913971000", \ - "0.1460520000, 0.1530964000, 0.1692876000, 0.2049338000, 0.2906289000, 0.5252948000, 1.2009426000", \ - "0.1662027000, 0.1732372000, 0.1893467000, 0.2250675000, 0.3106553000, 0.5455676000, 1.2208748000", \ - "0.2090501000, 0.2162870000, 0.2327877000, 0.2687827000, 0.3543398000, 0.5895213000, 1.2653212000", \ - "0.2790791000, 0.2873030000, 0.3056532000, 0.3440100000, 0.4312161000, 0.6664941000, 1.3420433000", \ - "0.3665964000, 0.3770868000, 0.3997928000, 0.4437769000, 0.5350540000, 0.7708681000, 1.4450253000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0352993000, 0.0395076000, 0.0494317000, 0.0694060000, 0.1174701000, 0.2485815000, 0.6542604000", \ - "0.0353402000, 0.0395574000, 0.0486072000, 0.0694551000, 0.1179231000, 0.2490465000, 0.6545414000", \ - "0.0352342000, 0.0394644000, 0.0489317000, 0.0696462000, 0.1177755000, 0.2489462000, 0.6532752000", \ - "0.0352441000, 0.0394107000, 0.0490259000, 0.0696585000, 0.1176177000, 0.2492966000, 0.6546769000", \ - "0.0351995000, 0.0394407000, 0.0487382000, 0.0695044000, 0.1174167000, 0.2492069000, 0.6548241000", \ - "0.0397525000, 0.0442459000, 0.0536794000, 0.0740728000, 0.1211262000, 0.2502771000, 0.6551219000", \ - "0.0524324000, 0.0571049000, 0.0679758000, 0.0895008000, 0.1376097000, 0.2641447000, 0.6561621000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0276699000, 0.0331886000, 0.0472174000, 0.0845515000, 0.1942668000, 0.5289035000, 1.5018450000", \ - "0.0277241000, 0.0332037000, 0.0471236000, 0.0843704000, 0.1944656000, 0.5277093000, 1.4984501000", \ - "0.0276699000, 0.0332919000, 0.0470202000, 0.0843885000, 0.1947515000, 0.5274424000, 1.5006498000", \ - "0.0276460000, 0.0331501000, 0.0470777000, 0.0843199000, 0.1946634000, 0.5277783000, 1.4991021000", \ - "0.0290346000, 0.0347419000, 0.0481786000, 0.0854739000, 0.1950809000, 0.5279897000, 1.4996392000", \ - "0.0347492000, 0.0407567000, 0.0544088000, 0.0904384000, 0.1970923000, 0.5280276000, 1.4968489000", \ - "0.0469644000, 0.0536421000, 0.0685092000, 0.1037285000, 0.2043703000, 0.5285214000, 1.4983911000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.2126977000, 0.2197344000, 0.2353928000, 0.2660594000, 0.3242248000, 0.4466447000, 0.7612236000", \ - "0.2162502000, 0.2233216000, 0.2390022000, 0.2694911000, 0.3278869000, 0.4502146000, 0.7645855000", \ - "0.2270241000, 0.2340363000, 0.2496983000, 0.2802154000, 0.3385687000, 0.4608969000, 0.7751952000", \ - "0.2549458000, 0.2620049000, 0.2775736000, 0.3081059000, 0.3660456000, 0.4888340000, 0.8029862000", \ - "0.3228645000, 0.3299136000, 0.3454714000, 0.3759829000, 0.4341055000, 0.5570048000, 0.8715532000", \ - "0.4735897000, 0.4815303000, 0.4981753000, 0.5302557000, 0.5895460000, 0.7130332000, 1.0274472000", \ - "0.7223679000, 0.7321797000, 0.7536614000, 0.7947121000, 0.8644344000, 0.9951366000, 1.3127704000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.1163369000, 0.1230248000, 0.1383897000, 0.1730615000, 0.2578080000, 0.4923222000, 1.1684481000", \ - "0.1212673000, 0.1279599000, 0.1434581000, 0.1781330000, 0.2627132000, 0.4982735000, 1.1738648000", \ - "0.1310259000, 0.1376983000, 0.1531991000, 0.1878377000, 0.2725549000, 0.5070713000, 1.1842495000", \ - "0.1509400000, 0.1575781000, 0.1730667000, 0.2076687000, 0.2922123000, 0.5274367000, 1.2035608000", \ - "0.1907941000, 0.1978278000, 0.2139558000, 0.2491501000, 0.3337088000, 0.5682826000, 1.2419908000", \ - "0.2503733000, 0.2586742000, 0.2767486000, 0.3144079000, 0.4011645000, 0.6355982000, 1.3117714000", \ - "0.3150427000, 0.3258111000, 0.3492496000, 0.3941748000, 0.4844528000, 0.7192500000, 1.3934018000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0351946000, 0.0393077000, 0.0489937000, 0.0694683000, 0.1175742000, 0.2483686000, 0.6557797000", \ - "0.0354860000, 0.0393164000, 0.0493470000, 0.0690286000, 0.1173936000, 0.2490223000, 0.6542983000", \ - "0.0352666000, 0.0393104000, 0.0493704000, 0.0691146000, 0.1174430000, 0.2491853000, 0.6550414000", \ - "0.0353351000, 0.0394612000, 0.0487253000, 0.0696932000, 0.1178333000, 0.2491862000, 0.6545890000", \ - "0.0351570000, 0.0395770000, 0.0487538000, 0.0697132000, 0.1173558000, 0.2485218000, 0.6545322000", \ - "0.0419740000, 0.0463269000, 0.0553679000, 0.0743003000, 0.1208189000, 0.2505385000, 0.6549553000", \ - "0.0617486000, 0.0674527000, 0.0776800000, 0.0991885000, 0.1423061000, 0.2641195000, 0.6574230000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014478800, 0.0041927000, 0.0121410000, 0.0351575000, 0.1018080000, 0.2948100000"); - values("0.0259672000, 0.0312306000, 0.0449756000, 0.0819853000, 0.1924777000, 0.5270185000, 1.5020846000", \ - "0.0259975000, 0.0313797000, 0.0449664000, 0.0821632000, 0.1928690000, 0.5265953000, 1.5020283000", \ - "0.0258983000, 0.0314120000, 0.0450829000, 0.0820035000, 0.1925785000, 0.5271280000, 1.5034717000", \ - "0.0259700000, 0.0313668000, 0.0448416000, 0.0820632000, 0.1929775000, 0.5264360000, 1.5046334000", \ - "0.0283724000, 0.0338055000, 0.0471161000, 0.0836189000, 0.1934166000, 0.5258290000, 1.5017336000", \ - "0.0351438000, 0.0410365000, 0.0551187000, 0.0896312000, 0.1967911000, 0.5264396000, 1.5017342000", \ - "0.0493843000, 0.0559766000, 0.0707995000, 0.1044123000, 0.2036444000, 0.5288940000, 1.4949004000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2a_4") { - leakage_power () { - value : 0.0041073000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0051534000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0030143000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0043869000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0047227000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0057684000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0036298000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0050021000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0050435000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0060896000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0039508000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0053233000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0061870000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0055201000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0061808000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0061870000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__o2bb2a"; - cell_leakage_power : 0.0050166770; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0048940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0089309000, 0.0089176000, 0.0088868000, 0.0088844000, 0.0088788000, 0.0088659000, 0.0088362000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008836600, -0.008844100, -0.008861400, -0.008862400, -0.008864800, -0.008870100, -0.008882500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051100000; - } - pin ("A2_N") { - capacitance : 0.0044270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087526000, 0.0087465000, 0.0087325000, 0.0087348000, 0.0087401000, 0.0087523000, 0.0087805000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006645000, -0.006648800, -0.006657500, -0.006645600, -0.006618100, -0.006554900, -0.006409100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046250000; - } - pin ("B1") { - capacitance : 0.0048120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085233000, 0.0085169000, 0.0085023000, 0.0084971000, 0.0084850000, 0.0084571000, 0.0083928000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007351000, -0.007472100, -0.007751300, -0.007763000, -0.007790100, -0.007852500, -0.007996400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050640000; - } - pin ("B2") { - capacitance : 0.0043550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0035340000, 0.0035300000, 0.0035206000, 0.0035293000, 0.0035494000, 0.0035956000, 0.0037022000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003330800, -0.003344800, -0.003377300, -0.003376100, -0.003373400, -0.003367200, -0.003352800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046730000; - } - pin ("X") { - direction : "output"; - function : "(!A1_N&B1) | (!A2_N&B1) | (!A1_N&B2) | (!A2_N&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0418910000, 0.0406269000, 0.0365982000, 0.0230492000, -0.028492600, -0.201682500, -0.751902100", \ - "0.0415488000, 0.0404233000, 0.0362421000, 0.0226950000, -0.028773500, -0.201932200, -0.752100400", \ - "0.0410429000, 0.0396918000, 0.0357533000, 0.0221638000, -0.029367600, -0.202499700, -0.752644900", \ - "0.0401403000, 0.0388708000, 0.0349364000, 0.0213176000, -0.030239100, -0.203355700, -0.753467600", \ - "0.0396764000, 0.0383569000, 0.0343562000, 0.0205694000, -0.030919600, -0.203995000, -0.754088800", \ - "0.0462136000, 0.0446641000, 0.0396545000, 0.0232487000, -0.030722000, -0.204413900, -0.754505200", \ - "0.0473177000, 0.0457266000, 0.0405498000, 0.0239684000, -0.029703600, -0.203159900, -0.753533600"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0533234000, 0.0552145000, 0.0613001000, 0.0797641000, 0.1356722000, 0.3095931000, 0.8541200000", \ - "0.0530390000, 0.0549498000, 0.0609481000, 0.0793935000, 0.1353912000, 0.3091106000, 0.8540911000", \ - "0.0525846000, 0.0544430000, 0.0604612000, 0.0789276000, 0.1350056000, 0.3087139000, 0.8536911000", \ - "0.0521857000, 0.0540987000, 0.0600643000, 0.0785126000, 0.1345283000, 0.3081720000, 0.8531809000", \ - "0.0519114000, 0.0538413000, 0.0598593000, 0.0783179000, 0.1343248000, 0.3080087000, 0.8530249000", \ - "0.0521817000, 0.0539643000, 0.0599873000, 0.0787402000, 0.1344492000, 0.3083186000, 0.8534089000", \ - "0.0555007000, 0.0572706000, 0.0629325000, 0.0808831000, 0.1364420000, 0.3113916000, 0.8541391000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0400373000, 0.0387733000, 0.0348531000, 0.0212743000, -0.030320500, -0.203480800, -0.753711500", \ - "0.0397521000, 0.0385442000, 0.0344864000, 0.0209420000, -0.030619200, -0.203811600, -0.754037600", \ - "0.0390546000, 0.0379668000, 0.0338520000, 0.0202050000, -0.031287600, -0.204452000, -0.754671900", \ - "0.0381856000, 0.0370860000, 0.0330171000, 0.0192933000, -0.032182600, -0.205304900, -0.755495800", \ - "0.0380369000, 0.0369160000, 0.0326575000, 0.0188659000, -0.032592100, -0.205733000, -0.755916700", \ - "0.0450206000, 0.0434610000, 0.0384730000, 0.0220637000, -0.031916300, -0.205632700, -0.755751200", \ - "0.0478843000, 0.0463543000, 0.0408351000, 0.0248639000, -0.029347500, -0.202777400, -0.753174900"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0474498000, 0.0493172000, 0.0553123000, 0.0737304000, 0.1297095000, 0.3033177000, 0.8480327000", \ - "0.0469234000, 0.0488671000, 0.0549048000, 0.0732886000, 0.1291840000, 0.3027934000, 0.8473575000", \ - "0.0464858000, 0.0483940000, 0.0544582000, 0.0727339000, 0.1287110000, 0.3021953000, 0.8466416000", \ - "0.0459157000, 0.0478499000, 0.0538260000, 0.0722090000, 0.1281052000, 0.3016747000, 0.8461321000", \ - "0.0457023000, 0.0476454000, 0.0536349000, 0.0719824000, 0.1279189000, 0.3015612000, 0.8463913000", \ - "0.0460657000, 0.0478853000, 0.0534757000, 0.0723239000, 0.1280242000, 0.3014353000, 0.8469151000", \ - "0.0492852000, 0.0510430000, 0.0568782000, 0.0746170000, 0.1302315000, 0.3046087000, 0.8481188000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0309473000, 0.0292841000, 0.0241305000, 0.0093959000, -0.041717000, -0.213883300, -0.763918100", \ - "0.0308717000, 0.0291479000, 0.0240088000, 0.0092858000, -0.041897600, -0.214254700, -0.764049400", \ - "0.0303616000, 0.0287456000, 0.0236328000, 0.0087687000, -0.042277000, -0.214471100, -0.764489500", \ - "0.0300387000, 0.0284203000, 0.0232911000, 0.0083980000, -0.042639300, -0.214849900, -0.764856500", \ - "0.0296978000, 0.0281423000, 0.0228361000, 0.0080049000, -0.043203400, -0.215448400, -0.765089100", \ - "0.0288967000, 0.0270909000, 0.0218189000, 0.0071972000, -0.043821600, -0.215710400, -0.765227200", \ - "0.0367638000, 0.0348044000, 0.0290162000, 0.0114623000, -0.043132500, -0.215680800, -0.764736600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0382817000, 0.0401374000, 0.0461658000, 0.0646252000, 0.1205146000, 0.2939536000, 0.8376030000", \ - "0.0381327000, 0.0400279000, 0.0461155000, 0.0645465000, 0.1204362000, 0.2938527000, 0.8375863000", \ - "0.0381933000, 0.0401166000, 0.0460623000, 0.0645464000, 0.1204972000, 0.2939987000, 0.8385025000", \ - "0.0379011000, 0.0398025000, 0.0458213000, 0.0641296000, 0.1200200000, 0.2935894000, 0.8382595000", \ - "0.0376021000, 0.0395020000, 0.0453743000, 0.0635603000, 0.1192636000, 0.2928472000, 0.8379050000", \ - "0.0385336000, 0.0403512000, 0.0460733000, 0.0636228000, 0.1186800000, 0.2915486000, 0.8371778000", \ - "0.0402658000, 0.0419690000, 0.0475307000, 0.0648490000, 0.1203700000, 0.2935258000, 0.8361585000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0306268000, 0.0288623000, 0.0237295000, 0.0089983000, -0.042146400, -0.214190500, -0.764286700", \ - "0.0303183000, 0.0286032000, 0.0235572000, 0.0088238000, -0.042326300, -0.214552100, -0.764382500", \ - "0.0299708000, 0.0282544000, 0.0231548000, 0.0085537000, -0.042630100, -0.214924700, -0.764696800", \ - "0.0295991000, 0.0278683000, 0.0228795000, 0.0079879000, -0.043109100, -0.215354600, -0.765141700", \ - "0.0297334000, 0.0279685000, 0.0227812000, 0.0078142000, -0.043530300, -0.215711300, -0.765402800", \ - "0.0298575000, 0.0279942000, 0.0227339000, 0.0085401000, -0.042873100, -0.215262200, -0.764804200", \ - "0.0403717000, 0.0383662000, 0.0336326000, 0.0156426000, -0.039340800, -0.212116500, -0.761453800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015796280, 0.0049904520, 0.0157661200, 0.0498092300, 0.1573602000, 0.4971412000"); - values("0.0316933000, 0.0335781000, 0.0396653000, 0.0581461000, 0.1140256000, 0.2871950000, 0.8287935000", \ - "0.0316766000, 0.0335944000, 0.0396845000, 0.0580174000, 0.1141033000, 0.2870393000, 0.8328274000", \ - "0.0314598000, 0.0333336000, 0.0393917000, 0.0579082000, 0.1138752000, 0.2871919000, 0.8281645000", \ - "0.0309464000, 0.0328206000, 0.0388184000, 0.0572045000, 0.1131390000, 0.2867463000, 0.8284399000", \ - "0.0305436000, 0.0323924000, 0.0384351000, 0.0565391000, 0.1121083000, 0.2856790000, 0.8283666000", \ - "0.0312387000, 0.0330199000, 0.0387977000, 0.0566052000, 0.1113992000, 0.2841276000, 0.8306576000", \ - "0.0331040000, 0.0347917000, 0.0403211000, 0.0577122000, 0.1127234000, 0.2857433000, 0.8285218000"); - } - } - max_capacitance : 0.4971410000; - max_transition : 1.5041270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1330829000, 0.1360788000, 0.1439328000, 0.1624910000, 0.2050744000, 0.3070335000, 0.6029062000", \ - "0.1372400000, 0.1402636000, 0.1481313000, 0.1667224000, 0.2092863000, 0.3111781000, 0.6069900000", \ - "0.1459630000, 0.1489702000, 0.1568072000, 0.1753846000, 0.2179737000, 0.3199690000, 0.6159154000", \ - "0.1636159000, 0.1666343000, 0.1744887000, 0.1930194000, 0.2356001000, 0.3376286000, 0.6336115000", \ - "0.1894233000, 0.1923856000, 0.2002661000, 0.2188021000, 0.2614239000, 0.3634655000, 0.6593935000", \ - "0.2164919000, 0.2195358000, 0.2273691000, 0.2459388000, 0.2885198000, 0.3905957000, 0.6858519000", \ - "0.2230262000, 0.2260854000, 0.2341624000, 0.2529383000, 0.2959994000, 0.3984152000, 0.6942757000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1564660000, 0.1603755000, 0.1710045000, 0.1981750000, 0.2728274000, 0.5005629000, 1.2124486000", \ - "0.1618137000, 0.1657183000, 0.1763144000, 0.2035414000, 0.2782302000, 0.5053962000, 1.2183916000", \ - "0.1752598000, 0.1791738000, 0.1897839000, 0.2170142000, 0.2917445000, 0.5188205000, 1.2317853000", \ - "0.2079401000, 0.2119241000, 0.2224819000, 0.2497215000, 0.3244983000, 0.5518813000, 1.2644710000", \ - "0.2773775000, 0.2813265000, 0.2919320000, 0.3191918000, 0.3939730000, 0.6213340000, 1.3357879000", \ - "0.3960182000, 0.3999767000, 0.4106257000, 0.4378457000, 0.5124904000, 0.7396376000, 1.4537448000", \ - "0.5944810000, 0.5984751000, 0.6090689000, 0.6364330000, 0.7112547000, 0.9392157000, 1.6514348000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0176720000, 0.0196466000, 0.0252291000, 0.0411289000, 0.0826074000, 0.2003011000, 0.5946583000", \ - "0.0176039000, 0.0196647000, 0.0252992000, 0.0410031000, 0.0826230000, 0.2004031000, 0.5911780000", \ - "0.0176328000, 0.0197627000, 0.0252003000, 0.0411486000, 0.0826280000, 0.2001665000, 0.5949218000", \ - "0.0177128000, 0.0194763000, 0.0252292000, 0.0411332000, 0.0825593000, 0.2003028000, 0.5928698000", \ - "0.0177591000, 0.0196999000, 0.0255498000, 0.0409994000, 0.0827280000, 0.2004418000, 0.5946589000", \ - "0.0180430000, 0.0200995000, 0.0256590000, 0.0414229000, 0.0828710000, 0.2000703000, 0.5908075000", \ - "0.0189429000, 0.0209451000, 0.0267823000, 0.0423303000, 0.0836974000, 0.2008791000, 0.5942581000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0218271000, 0.0252320000, 0.0352562000, 0.0655655000, 0.1645570000, 0.4862576000, 1.4975730000", \ - "0.0217936000, 0.0252311000, 0.0352574000, 0.0656862000, 0.1644838000, 0.4858892000, 1.4995173000", \ - "0.0217367000, 0.0252364000, 0.0352214000, 0.0657251000, 0.1646137000, 0.4857093000, 1.5004609000", \ - "0.0218354000, 0.0252372000, 0.0352612000, 0.0656890000, 0.1645012000, 0.4860812000, 1.4995770000", \ - "0.0219388000, 0.0252435000, 0.0352709000, 0.0656815000, 0.1642454000, 0.4854819000, 1.5006874000", \ - "0.0221781000, 0.0255800000, 0.0355548000, 0.0659597000, 0.1648988000, 0.4849784000, 1.5020702000", \ - "0.0231128000, 0.0263557000, 0.0366113000, 0.0666972000, 0.1649586000, 0.4853650000, 1.4958532000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1281520000, 0.1311241000, 0.1390269000, 0.1576022000, 0.2001593000, 0.3020254000, 0.5979555000", \ - "0.1319691000, 0.1349929000, 0.1428347000, 0.1613869000, 0.2039770000, 0.3058994000, 0.6018480000", \ - "0.1413615000, 0.1443817000, 0.1522226000, 0.1707878000, 0.2133500000, 0.3152762000, 0.6110406000", \ - "0.1588859000, 0.1619028000, 0.1697357000, 0.1882564000, 0.2308488000, 0.3328298000, 0.6280921000", \ - "0.1803164000, 0.1833483000, 0.1912184000, 0.2098324000, 0.2526269000, 0.3546713000, 0.6503745000", \ - "0.1987024000, 0.2017336000, 0.2095769000, 0.2281514000, 0.2709538000, 0.3730414000, 0.6685754000", \ - "0.1922946000, 0.1953773000, 0.2033645000, 0.2219997000, 0.2649209000, 0.3672568000, 0.6632871000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1568007000, 0.1607264000, 0.1713418000, 0.1985901000, 0.2734230000, 0.5018118000, 1.2135802000", \ - "0.1612221000, 0.1651920000, 0.1757735000, 0.2029957000, 0.2777504000, 0.5055352000, 1.2185881000", \ - "0.1742442000, 0.1781889000, 0.1888213000, 0.2160151000, 0.2908081000, 0.5187386000, 1.2315047000", \ - "0.2059037000, 0.2098600000, 0.2204495000, 0.2476560000, 0.3224069000, 0.5504212000, 1.2630619000", \ - "0.2717595000, 0.2757051000, 0.2863054000, 0.3135667000, 0.3883809000, 0.6156388000, 1.3296064000", \ - "0.3812083000, 0.3851346000, 0.3958037000, 0.4232187000, 0.4980801000, 0.7251977000, 1.4392677000", \ - "0.5678191000, 0.5718439000, 0.5826312000, 0.6100370000, 0.6850536000, 0.9121198000, 1.6253371000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0174512000, 0.0195022000, 0.0253781000, 0.0410975000, 0.0826105000, 0.2004224000, 0.5946053000", \ - "0.0175544000, 0.0194401000, 0.0252461000, 0.0411285000, 0.0826202000, 0.2003466000, 0.5944437000", \ - "0.0174574000, 0.0196690000, 0.0253449000, 0.0410034000, 0.0826066000, 0.2002426000, 0.5944227000", \ - "0.0174634000, 0.0196727000, 0.0254048000, 0.0410229000, 0.0826142000, 0.2003494000, 0.5927418000", \ - "0.0178530000, 0.0199183000, 0.0255930000, 0.0413026000, 0.0828430000, 0.2004631000, 0.5943485000", \ - "0.0178645000, 0.0199347000, 0.0257648000, 0.0414333000, 0.0828748000, 0.2006098000, 0.5930829000", \ - "0.0188963000, 0.0208575000, 0.0267332000, 0.0422708000, 0.0835213000, 0.2008577000, 0.5900257000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0218466000, 0.0253076000, 0.0352778000, 0.0658125000, 0.1647512000, 0.4855094000, 1.4997192000", \ - "0.0219234000, 0.0251900000, 0.0353123000, 0.0656774000, 0.1646946000, 0.4865113000, 1.4996384000", \ - "0.0217996000, 0.0252749000, 0.0351974000, 0.0657055000, 0.1646340000, 0.4865656000, 1.4993109000", \ - "0.0218491000, 0.0251900000, 0.0353298000, 0.0656522000, 0.1647078000, 0.4865592000, 1.4990786000", \ - "0.0219546000, 0.0253289000, 0.0353608000, 0.0658623000, 0.1647257000, 0.4862781000, 1.5025883000", \ - "0.0223696000, 0.0257607000, 0.0358059000, 0.0661969000, 0.1651172000, 0.4850237000, 1.5023053000", \ - "0.0233985000, 0.0268137000, 0.0367402000, 0.0670633000, 0.1653750000, 0.4847703000, 1.4978785000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1838074000, 0.1878017000, 0.1979804000, 0.2204451000, 0.2667142000, 0.3730767000, 0.6710282000", \ - "0.1888323000, 0.1928297000, 0.2030405000, 0.2255365000, 0.2720310000, 0.3782836000, 0.6766515000", \ - "0.2013516000, 0.2053420000, 0.2155147000, 0.2379550000, 0.2844434000, 0.3906272000, 0.6886115000", \ - "0.2284516000, 0.2324362000, 0.2426043000, 0.2650273000, 0.3114552000, 0.4176592000, 0.7156556000", \ - "0.2893792000, 0.2933485000, 0.3035573000, 0.3260104000, 0.3723208000, 0.4788357000, 0.7773084000", \ - "0.4106145000, 0.4150485000, 0.4263883000, 0.4506455000, 0.5000704000, 0.6084381000, 0.9068138000", \ - "0.6195032000, 0.6249188000, 0.6385723000, 0.6677533000, 0.7239927000, 0.8400683000, 1.1421541000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0962196000, 0.1001466000, 0.1107513000, 0.1380056000, 0.2126750000, 0.4406822000, 1.1509542000", \ - "0.1006193000, 0.1045248000, 0.1151384000, 0.1423727000, 0.2170281000, 0.4449481000, 1.1550850000", \ - "0.1095958000, 0.1135285000, 0.1240956000, 0.1513664000, 0.2261352000, 0.4532124000, 1.1666771000", \ - "0.1288881000, 0.1327669000, 0.1433400000, 0.1704875000, 0.2451229000, 0.4721536000, 1.1851542000", \ - "0.1642353000, 0.1684092000, 0.1795078000, 0.2073773000, 0.2822559000, 0.5096281000, 1.2225191000", \ - "0.2107978000, 0.2157885000, 0.2283364000, 0.2579174000, 0.3338682000, 0.5611923000, 1.2760477000", \ - "0.2468843000, 0.2533941000, 0.2697801000, 0.3046623000, 0.3838350000, 0.6115894000, 1.3230426000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0280681000, 0.0304312000, 0.0366316000, 0.0515050000, 0.0911364000, 0.2080811000, 0.5976137000", \ - "0.0278424000, 0.0301848000, 0.0368565000, 0.0513965000, 0.0910853000, 0.2078947000, 0.5991032000", \ - "0.0279326000, 0.0302608000, 0.0362269000, 0.0516518000, 0.0907755000, 0.2080687000, 0.5974246000", \ - "0.0279275000, 0.0302499000, 0.0362290000, 0.0517278000, 0.0909914000, 0.2081258000, 0.5974797000", \ - "0.0280451000, 0.0304802000, 0.0364320000, 0.0516345000, 0.0910138000, 0.2080365000, 0.5988147000", \ - "0.0333946000, 0.0360945000, 0.0426844000, 0.0572070000, 0.0954982000, 0.2109263000, 0.5968788000", \ - "0.0458329000, 0.0482483000, 0.0555332000, 0.0714200000, 0.1104856000, 0.2221938000, 0.5997740000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0217826000, 0.0250793000, 0.0351748000, 0.0656641000, 0.1645757000, 0.4847902000, 1.4966254000", \ - "0.0217192000, 0.0251657000, 0.0351709000, 0.0655520000, 0.1645461000, 0.4856233000, 1.4954016000", \ - "0.0216438000, 0.0249921000, 0.0351689000, 0.0655882000, 0.1644174000, 0.4857930000, 1.5020180000", \ - "0.0217707000, 0.0251459000, 0.0351911000, 0.0656662000, 0.1645659000, 0.4859767000, 1.5014339000", \ - "0.0241946000, 0.0275911000, 0.0374944000, 0.0672968000, 0.1651024000, 0.4853690000, 1.5002748000", \ - "0.0300189000, 0.0334956000, 0.0434068000, 0.0717597000, 0.1672402000, 0.4846292000, 1.5009577000", \ - "0.0419524000, 0.0460396000, 0.0568670000, 0.0842984000, 0.1717422000, 0.4867660000, 1.4943005000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.1659593000, 0.1699580000, 0.1801087000, 0.2025717000, 0.2488245000, 0.3550502000, 0.6531742000", \ - "0.1697471000, 0.1737589000, 0.1839673000, 0.2062994000, 0.2527352000, 0.3590615000, 0.6575951000", \ - "0.1806133000, 0.1846076000, 0.1947719000, 0.2172186000, 0.2637283000, 0.3698745000, 0.6684038000", \ - "0.2089576000, 0.2129474000, 0.2232156000, 0.2456628000, 0.2918670000, 0.3982139000, 0.6961389000", \ - "0.2778588000, 0.2818144000, 0.2919300000, 0.3141714000, 0.3606794000, 0.4670780000, 0.7653905000", \ - "0.4178961000, 0.4225921000, 0.4344198000, 0.4592391000, 0.5078183000, 0.6162700000, 0.9144167000", \ - "0.6450177000, 0.6510916000, 0.6668961000, 0.6992435000, 0.7571170000, 0.8714034000, 1.1730685000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0889071000, 0.0928482000, 0.1035918000, 0.1311070000, 0.2059296000, 0.4326687000, 1.1431170000", \ - "0.0934831000, 0.0974630000, 0.1081929000, 0.1356506000, 0.2103252000, 0.4370899000, 1.1489993000", \ - "0.1018474000, 0.1058310000, 0.1165278000, 0.1440424000, 0.2189357000, 0.4458589000, 1.1562686000", \ - "0.1190214000, 0.1229690000, 0.1336979000, 0.1611006000, 0.2359574000, 0.4635208000, 1.1732735000", \ - "0.1482972000, 0.1526232000, 0.1639605000, 0.1923174000, 0.2674435000, 0.4949934000, 1.2056275000", \ - "0.1829577000, 0.1880628000, 0.2011152000, 0.2315486000, 0.3079807000, 0.5352908000, 1.2468302000", \ - "0.1971986000, 0.2040263000, 0.2211204000, 0.2580851000, 0.3382580000, 0.5657033000, 1.2767882000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0279075000, 0.0303049000, 0.0367028000, 0.0514452000, 0.0912200000, 0.2080728000, 0.5978668000", \ - "0.0278123000, 0.0301716000, 0.0364073000, 0.0513425000, 0.0911325000, 0.2080020000, 0.5990250000", \ - "0.0279543000, 0.0303580000, 0.0366102000, 0.0514723000, 0.0910987000, 0.2080174000, 0.5991243000", \ - "0.0279229000, 0.0302788000, 0.0365821000, 0.0516627000, 0.0911794000, 0.2079790000, 0.5966967000", \ - "0.0280296000, 0.0303921000, 0.0364812000, 0.0513703000, 0.0911654000, 0.2081098000, 0.5991347000", \ - "0.0374374000, 0.0394381000, 0.0459791000, 0.0597929000, 0.0965985000, 0.2109099000, 0.5971756000", \ - "0.0550295000, 0.0583218000, 0.0655288000, 0.0812743000, 0.1154600000, 0.2221475000, 0.6002011000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015796300, 0.0049904500, 0.0157661000, 0.0498092000, 0.1573600000, 0.4971410000"); - values("0.0217698000, 0.0252174000, 0.0352109000, 0.0656008000, 0.1644934000, 0.4849320000, 1.5000345000", \ - "0.0217357000, 0.0251009000, 0.0351796000, 0.0657151000, 0.1644027000, 0.4855874000, 1.5032762000", \ - "0.0218107000, 0.0252288000, 0.0352618000, 0.0657574000, 0.1640145000, 0.4854719000, 1.4939184000", \ - "0.0221317000, 0.0255778000, 0.0356904000, 0.0658903000, 0.1642635000, 0.4858366000, 1.4990499000", \ - "0.0248205000, 0.0284022000, 0.0380915000, 0.0680693000, 0.1652635000, 0.4845991000, 1.5041272000", \ - "0.0317110000, 0.0353218000, 0.0449028000, 0.0735641000, 0.1676112000, 0.4843718000, 1.5032625000", \ - "0.0448086000, 0.0490774000, 0.0601870000, 0.0870298000, 0.1740576000, 0.4863152000, 1.4958714000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2ai_1") { - leakage_power () { - value : 0.0015506000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0005608000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0008393000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0020079000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0017496000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0007606000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0010383000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0022068000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0018404000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0008514000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0011291000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0022976000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0032398000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0029891000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0032397000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0032408000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o2bb2ai"; - cell_leakage_power : 0.0018463660; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0023580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039617000, 0.0039622000, 0.0039634000, 0.0039655000, 0.0039703000, 0.0039814000, 0.0040070000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003960900, -0.003959400, -0.003956000, -0.003956400, -0.003957300, -0.003959300, -0.003963900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024610000; - } - pin ("A2_N") { - capacitance : 0.0025040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0024140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048431000, 0.0048449000, 0.0048490000, 0.0048503000, 0.0048535000, 0.0048607000, 0.0048773000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004020400, -0.004022300, -0.004026600, -0.004020800, -0.004007400, -0.003976600, -0.003905400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025930000; - } - pin ("B1") { - capacitance : 0.0023240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039670000, 0.0039673000, 0.0039681000, 0.0039700000, 0.0039744000, 0.0039845000, 0.0040079000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003650000, -0.003705800, -0.003834300, -0.003837900, -0.003846200, -0.003865200, -0.003909000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024290000; - } - pin ("B2") { - capacitance : 0.0023790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028120000, 0.0028085000, 0.0028006000, 0.0028083000, 0.0028262000, 0.0028673000, 0.0029621000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002020200, -0.002011100, -0.001990300, -0.001991600, -0.001994500, -0.002001300, -0.002017000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025360000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (A1_N&A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0149196000, 0.0139432000, 0.0116370000, 0.0061802000, -0.006720300, -0.036781500, -0.106485400", \ - "0.0147644000, 0.0137811000, 0.0115007000, 0.0060285000, -0.006867600, -0.036933600, -0.106651900", \ - "0.0145315000, 0.0135459000, 0.0112457000, 0.0057805000, -0.007097100, -0.037132800, -0.106878300", \ - "0.0143525000, 0.0133817000, 0.0110659000, 0.0056201000, -0.007230300, -0.037249200, -0.106919000", \ - "0.0141670000, 0.0131794000, 0.0108663000, 0.0054317000, -0.007374300, -0.037339700, -0.106999300", \ - "0.0143865000, 0.0133677000, 0.0109792000, 0.0054027000, -0.007024100, -0.036970300, -0.106548600", \ - "0.0161793000, 0.0150719000, 0.0127924000, 0.0072526000, -0.005595600, -0.035425400, -0.104684500"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0136865000, 0.0148979000, 0.0175987000, 0.0235058000, 0.0366043000, 0.0665354000, 0.1353599000", \ - "0.0135244000, 0.0147509000, 0.0174427000, 0.0233440000, 0.0364629000, 0.0663137000, 0.1352676000", \ - "0.0132733000, 0.0144798000, 0.0171626000, 0.0230733000, 0.0362146000, 0.0660650000, 0.1349248000", \ - "0.0129696000, 0.0141403000, 0.0167929000, 0.0226938000, 0.0358760000, 0.0658313000, 0.1347795000", \ - "0.0128073000, 0.0139308000, 0.0165064000, 0.0223840000, 0.0355738000, 0.0656526000, 0.1346289000", \ - "0.0130675000, 0.0142009000, 0.0166943000, 0.0225016000, 0.0355506000, 0.0656356000, 0.1346802000", \ - "0.0141797000, 0.0152618000, 0.0177696000, 0.0236084000, 0.0368610000, 0.0666005000, 0.1358723000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0117936000, 0.0108182000, 0.0084667000, 0.0028909000, -0.010101400, -0.040269100, -0.110045400", \ - "0.0114654000, 0.0104877000, 0.0081280000, 0.0025950000, -0.010402100, -0.040558600, -0.110369300", \ - "0.0111501000, 0.0101546000, 0.0078195000, 0.0022820000, -0.010689000, -0.040846200, -0.110612600", \ - "0.0108156000, 0.0098176000, 0.0074693000, 0.0019501000, -0.010951700, -0.041056800, -0.110776100", \ - "0.0107252000, 0.0097226000, 0.0073837000, 0.0018836000, -0.011021100, -0.041071700, -0.110790200", \ - "0.0108300000, 0.0098121000, 0.0074773000, 0.0018564000, -0.010682900, -0.040708500, -0.110368600", \ - "0.0122704000, 0.0113514000, 0.0088335000, 0.0033821000, -0.009578900, -0.039416100, -0.109014500"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0138106000, 0.0150259000, 0.0176880000, 0.0236180000, 0.0367296000, 0.0666275000, 0.1355024000", \ - "0.0136084000, 0.0148254000, 0.0175236000, 0.0233916000, 0.0365265000, 0.0663705000, 0.1351704000", \ - "0.0132937000, 0.0144877000, 0.0171584000, 0.0230677000, 0.0362235000, 0.0661266000, 0.1349376000", \ - "0.0129658000, 0.0141080000, 0.0167334000, 0.0226231000, 0.0358168000, 0.0658464000, 0.1346410000", \ - "0.0127454000, 0.0138353000, 0.0164345000, 0.0222745000, 0.0355026000, 0.0656017000, 0.1344964000", \ - "0.0132857000, 0.0143869000, 0.0169281000, 0.0226065000, 0.0355537000, 0.0657292000, 0.1347539000", \ - "0.0145251000, 0.0156487000, 0.0181430000, 0.0238754000, 0.0369302000, 0.0665874000, 0.1360664000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0063486000, 0.0053151000, 0.0028913000, -0.002716700, -0.015746600, -0.045919100, -0.115678700", \ - "0.0062780000, 0.0052533000, 0.0028409000, -0.002758000, -0.015779100, -0.045952700, -0.115720300", \ - "0.0062540000, 0.0052196000, 0.0028376000, -0.002748000, -0.015736900, -0.045879900, -0.115680900", \ - "0.0060519000, 0.0050410000, 0.0026588000, -0.002867900, -0.015829200, -0.045938900, -0.115683300", \ - "0.0061282000, 0.0051020000, 0.0025873000, -0.002963500, -0.015899700, -0.045957900, -0.115684400", \ - "0.0062889000, 0.0052315000, 0.0027764000, -0.002903100, -0.016037700, -0.046101800, -0.115756700", \ - "0.0070895000, 0.0059794000, 0.0034900000, -0.002301900, -0.015473100, -0.045877300, -0.115668100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0082153000, 0.0093007000, 0.0117467000, 0.0173944000, 0.0303274000, 0.0601918000, 0.1291677000", \ - "0.0080576000, 0.0091597000, 0.0116181000, 0.0172969000, 0.0302764000, 0.0601317000, 0.1291376000", \ - "0.0078891000, 0.0089742000, 0.0114563000, 0.0171576000, 0.0301799000, 0.0600722000, 0.1290244000", \ - "0.0077609000, 0.0088417000, 0.0113092000, 0.0169983000, 0.0300515000, 0.0600557000, 0.1289762000", \ - "0.0076663000, 0.0087297000, 0.0112140000, 0.0169095000, 0.0299236000, 0.0598423000, 0.1288299000", \ - "0.0076314000, 0.0086765000, 0.0111284000, 0.0168494000, 0.0299292000, 0.0598961000, 0.1288040000", \ - "0.0080297000, 0.0090433000, 0.0114160000, 0.0168482000, 0.0300964000, 0.0600037000, 0.1289575000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0029843000, 0.0020234000, -0.000289400, -0.005855000, -0.018883400, -0.049077400, -0.118909100", \ - "0.0028095000, 0.0018875000, -0.000373500, -0.005873700, -0.018865700, -0.049047800, -0.118847900", \ - "0.0025199000, 0.0016238000, -0.000593800, -0.006011300, -0.018926300, -0.049057600, -0.118835100", \ - "0.0022864000, 0.0013325000, -0.000894500, -0.006255800, -0.019080800, -0.049131400, -0.118857300", \ - "0.0024180000, 0.0013981000, -0.000963100, -0.006536900, -0.019317600, -0.049255700, -0.118914700", \ - "0.0025143000, 0.0014465000, -0.000956400, -0.006547200, -0.019549800, -0.049507000, -0.119086800", \ - "0.0033756000, 0.0022076000, -0.000362300, -0.006169200, -0.019325300, -0.049451900, -0.119203900"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011550730, 0.0026683870, 0.0061643630, 0.0142405800, 0.0328978100, 0.0759987400"); - values("0.0074806000, 0.0085495000, 0.0110398000, 0.0166951000, 0.0296809000, 0.0595667000, 0.1284435000", \ - "0.0071883000, 0.0082875000, 0.0108106000, 0.0165365000, 0.0295699000, 0.0594164000, 0.1284054000", \ - "0.0069853000, 0.0080978000, 0.0105805000, 0.0163443000, 0.0294560000, 0.0593718000, 0.1283638000", \ - "0.0068735000, 0.0079510000, 0.0104608000, 0.0161051000, 0.0291782000, 0.0592358000, 0.1282671000", \ - "0.0068371000, 0.0078909000, 0.0103304000, 0.0160060000, 0.0289882000, 0.0590200000, 0.1280383000", \ - "0.0072042000, 0.0082278000, 0.0106159000, 0.0161807000, 0.0290049000, 0.0588669000, 0.1278501000", \ - "0.0083280000, 0.0093709000, 0.0118400000, 0.0174994000, 0.0302362000, 0.0598894000, 0.1278997000"); - } - } - max_capacitance : 0.0759990000; - max_transition : 1.5018510000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0886377000, 0.0933117000, 0.1031988000, 0.1241191000, 0.1697734000, 0.2727433000, 0.5092450000", \ - "0.0941267000, 0.0987639000, 0.1086780000, 0.1296730000, 0.1752997000, 0.2783226000, 0.5147238000", \ - "0.1073727000, 0.1120874000, 0.1219865000, 0.1429619000, 0.1883052000, 0.2915999000, 0.5281482000", \ - "0.1385968000, 0.1431652000, 0.1531020000, 0.1740892000, 0.2198588000, 0.3229085000, 0.5595056000", \ - "0.2003243000, 0.2050491000, 0.2154580000, 0.2368050000, 0.2826997000, 0.3859233000, 0.6223663000", \ - "0.2976533000, 0.3031597000, 0.3144441000, 0.3369260000, 0.3835216000, 0.4872773000, 0.7240551000", \ - "0.4512422000, 0.4579811000, 0.4708792000, 0.4966719000, 0.5469427000, 0.6510041000, 0.8880748000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0721761000, 0.0781991000, 0.0909083000, 0.1178117000, 0.1772353000, 0.3115050000, 0.6213721000", \ - "0.0763561000, 0.0824163000, 0.0952146000, 0.1220125000, 0.1815006000, 0.3157688000, 0.6268236000", \ - "0.0854875000, 0.0915160000, 0.1040888000, 0.1311216000, 0.1902489000, 0.3249548000, 0.6349392000", \ - "0.1043419000, 0.1103439000, 0.1230787000, 0.1499969000, 0.2092602000, 0.3442051000, 0.6545536000", \ - "0.1329283000, 0.1390778000, 0.1522884000, 0.1795188000, 0.2392671000, 0.3744320000, 0.6861522000", \ - "0.1658794000, 0.1731938000, 0.1870998000, 0.2154271000, 0.2749639000, 0.4106339000, 0.7213219000", \ - "0.1861348000, 0.1955657000, 0.2130560000, 0.2450688000, 0.3063320000, 0.4417150000, 0.7527874000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0271250000, 0.0319601000, 0.0431390000, 0.0683184000, 0.1273394000, 0.2647069000, 0.5833755000", \ - "0.0271370000, 0.0319672000, 0.0431527000, 0.0683967000, 0.1275779000, 0.2650245000, 0.5828832000", \ - "0.0270906000, 0.0319555000, 0.0430731000, 0.0684128000, 0.1275125000, 0.2646083000, 0.5833948000", \ - "0.0272095000, 0.0322424000, 0.0432510000, 0.0683927000, 0.1275700000, 0.2646595000, 0.5833742000", \ - "0.0293832000, 0.0345835000, 0.0453426000, 0.0699184000, 0.1280560000, 0.2643940000, 0.5839992000", \ - "0.0357643000, 0.0405459000, 0.0512016000, 0.0748086000, 0.1309811000, 0.2660151000, 0.5834171000", \ - "0.0482573000, 0.0535216000, 0.0648653000, 0.0872236000, 0.1385464000, 0.2693355000, 0.5846822000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0346426000, 0.0413370000, 0.0573307000, 0.0940954000, 0.1769889000, 0.3659794000, 0.8036689000", \ - "0.0345476000, 0.0413866000, 0.0573022000, 0.0941306000, 0.1769525000, 0.3662299000, 0.8034823000", \ - "0.0346535000, 0.0413294000, 0.0573915000, 0.0941371000, 0.1769732000, 0.3661522000, 0.8035627000", \ - "0.0356489000, 0.0422296000, 0.0578485000, 0.0943438000, 0.1769884000, 0.3662411000, 0.8035693000", \ - "0.0394525000, 0.0453806000, 0.0603883000, 0.0958573000, 0.1776444000, 0.3662816000, 0.8031206000", \ - "0.0481013000, 0.0533346000, 0.0665408000, 0.0992322000, 0.1789034000, 0.3672607000, 0.8026633000", \ - "0.0672409000, 0.0710275000, 0.0812713000, 0.1096514000, 0.1832692000, 0.3679640000, 0.8052328000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0846219000, 0.0891427000, 0.0989050000, 0.1196661000, 0.1650367000, 0.2677447000, 0.5037122000", \ - "0.0894113000, 0.0939786000, 0.1038560000, 0.1246459000, 0.1700196000, 0.2726782000, 0.5087535000", \ - "0.1027365000, 0.1074249000, 0.1172413000, 0.1381067000, 0.1835679000, 0.2863491000, 0.5223422000", \ - "0.1346078000, 0.1391965000, 0.1490711000, 0.1697251000, 0.2153677000, 0.3183274000, 0.5545878000", \ - "0.1948234000, 0.1997237000, 0.2101911000, 0.2318411000, 0.2776653000, 0.3806084000, 0.6167410000", \ - "0.2924149000, 0.2976970000, 0.3096233000, 0.3327327000, 0.3795375000, 0.4833169000, 0.7199387000", \ - "0.4499826000, 0.4570657000, 0.4715544000, 0.4990856000, 0.5489311000, 0.6520604000, 0.8876393000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0690644000, 0.0751180000, 0.0878608000, 0.1146378000, 0.1740391000, 0.3084328000, 0.6185518000", \ - "0.0729557000, 0.0790004000, 0.0916780000, 0.1185270000, 0.1780553000, 0.3126248000, 0.6223632000", \ - "0.0828222000, 0.0887986000, 0.1013629000, 0.1283893000, 0.1874779000, 0.3222998000, 0.6322357000", \ - "0.1026078000, 0.1086986000, 0.1213245000, 0.1482920000, 0.2079906000, 0.3431864000, 0.6532918000", \ - "0.1288853000, 0.1348200000, 0.1477525000, 0.1751616000, 0.2351691000, 0.3705477000, 0.6812840000", \ - "0.1559234000, 0.1629201000, 0.1768224000, 0.2044105000, 0.2641583000, 0.4005785000, 0.7111511000", \ - "0.1620403000, 0.1711494000, 0.1885031000, 0.2197667000, 0.2789094000, 0.4145193000, 0.7253356000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0269479000, 0.0321067000, 0.0431296000, 0.0683784000, 0.1272141000, 0.2643361000, 0.5829527000", \ - "0.0269813000, 0.0321117000, 0.0431129000, 0.0683390000, 0.1273718000, 0.2645070000, 0.5837351000", \ - "0.0271104000, 0.0319560000, 0.0431409000, 0.0683038000, 0.1271693000, 0.2643495000, 0.5829741000", \ - "0.0272180000, 0.0324021000, 0.0432898000, 0.0684381000, 0.1272367000, 0.2648231000, 0.5834444000", \ - "0.0302740000, 0.0353538000, 0.0463393000, 0.0706393000, 0.1283174000, 0.2642935000, 0.5832189000", \ - "0.0377403000, 0.0428080000, 0.0534222000, 0.0764364000, 0.1320303000, 0.2663483000, 0.5844675000", \ - "0.0513884000, 0.0571842000, 0.0681470000, 0.0908760000, 0.1420048000, 0.2705590000, 0.5848022000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0345347000, 0.0412884000, 0.0573131000, 0.0941494000, 0.1769841000, 0.3662256000, 0.8036233000", \ - "0.0345523000, 0.0412989000, 0.0573125000, 0.0941480000, 0.1768837000, 0.3662012000, 0.8044987000", \ - "0.0346688000, 0.0413469000, 0.0573661000, 0.0941459000, 0.1769718000, 0.3662465000, 0.8036306000", \ - "0.0362455000, 0.0427581000, 0.0583788000, 0.0944786000, 0.1769660000, 0.3662163000, 0.8051769000", \ - "0.0397069000, 0.0459472000, 0.0608396000, 0.0966502000, 0.1784425000, 0.3665047000, 0.8038836000", \ - "0.0493006000, 0.0538702000, 0.0663979000, 0.0994287000, 0.1794016000, 0.3685211000, 0.8049735000", \ - "0.0697581000, 0.0729953000, 0.0826110000, 0.1096954000, 0.1831709000, 0.3685983000, 0.8061428000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0384419000, 0.0426381000, 0.0519095000, 0.0720787000, 0.1172783000, 0.2199361000, 0.4564029000", \ - "0.0428841000, 0.0470935000, 0.0563648000, 0.0765903000, 0.1217774000, 0.2244348000, 0.4608595000", \ - "0.0517650000, 0.0560058000, 0.0653078000, 0.0857261000, 0.1310429000, 0.2338691000, 0.4698215000", \ - "0.0681277000, 0.0733754000, 0.0837568000, 0.1057522000, 0.1512933000, 0.2545578000, 0.4910932000", \ - "0.0907771000, 0.0982683000, 0.1136143000, 0.1422195000, 0.1962659000, 0.3025720000, 0.5396767000", \ - "0.1121301000, 0.1236085000, 0.1474928000, 0.1921054000, 0.2702696000, 0.4028408000, 0.6516715000", \ - "0.1104710000, 0.1291257000, 0.1674697000, 0.2387501000, 0.3615495000, 0.5588040000, 0.8779302000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0847105000, 0.0944867000, 0.1161902000, 0.1653364000, 0.2773384000, 0.5344660000, 1.1270707000", \ - "0.0897641000, 0.0996770000, 0.1213285000, 0.1708112000, 0.2829300000, 0.5402795000, 1.1330169000", \ - "0.1021076000, 0.1115544000, 0.1337999000, 0.1833443000, 0.2957743000, 0.5533957000, 1.1462920000", \ - "0.1285344000, 0.1381413000, 0.1597398000, 0.2093051000, 0.3219985000, 0.5799470000, 1.1731862000", \ - "0.1800580000, 0.1917432000, 0.2168905000, 0.2683902000, 0.3810008000, 0.6393165000, 1.2328448000", \ - "0.2672747000, 0.2834744000, 0.3171921000, 0.3850432000, 0.5156783000, 0.7758550000, 1.3696124000", \ - "0.4090142000, 0.4339665000, 0.4860771000, 0.5846693000, 0.7642056000, 1.0807066000, 1.6855077000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0246027000, 0.0297556000, 0.0412209000, 0.0671398000, 0.1268103000, 0.2642782000, 0.5824464000", \ - "0.0245793000, 0.0296757000, 0.0411067000, 0.0671921000, 0.1267360000, 0.2644141000, 0.5827423000", \ - "0.0249978000, 0.0299014000, 0.0411346000, 0.0672129000, 0.1269850000, 0.2647722000, 0.5837136000", \ - "0.0311939000, 0.0359609000, 0.0464305000, 0.0701612000, 0.1276537000, 0.2645712000, 0.5832653000", \ - "0.0480102000, 0.0537454000, 0.0658329000, 0.0899537000, 0.1412737000, 0.2685033000, 0.5828045000", \ - "0.0821596000, 0.0905524000, 0.1058377000, 0.1366416000, 0.1938095000, 0.3107651000, 0.5962096000", \ - "0.1462043000, 0.1581116000, 0.1814113000, 0.2260376000, 0.3017208000, 0.4378966000, 0.7051804000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0640169000, 0.0764214000, 0.1046478000, 0.1703648000, 0.3223755000, 0.6712829000, 1.4790740000", \ - "0.0640085000, 0.0763922000, 0.1046259000, 0.1703728000, 0.3221236000, 0.6713642000, 1.4793797000", \ - "0.0640540000, 0.0763930000, 0.1045742000, 0.1703895000, 0.3225026000, 0.6723253000, 1.4778657000", \ - "0.0653856000, 0.0771220000, 0.1048102000, 0.1703996000, 0.3221197000, 0.6718485000, 1.4785475000", \ - "0.0822346000, 0.0937006000, 0.1182398000, 0.1775317000, 0.3229506000, 0.6721465000, 1.4809400000", \ - "0.1226894000, 0.1352352000, 0.1632266000, 0.2230545000, 0.3523702000, 0.6777190000, 1.4804733000", \ - "0.2008486000, 0.2184785000, 0.2557179000, 0.3260119000, 0.4694377000, 0.7610427000, 1.4969086000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0295420000, 0.0333741000, 0.0416465000, 0.0600494000, 0.1010984000, 0.1953335000, 0.4129031000", \ - "0.0339155000, 0.0378330000, 0.0462782000, 0.0647155000, 0.1058483000, 0.2003377000, 0.4172748000", \ - "0.0422930000, 0.0465321000, 0.0552178000, 0.0740122000, 0.1155906000, 0.2098911000, 0.4269616000", \ - "0.0542903000, 0.0600636000, 0.0716149000, 0.0935408000, 0.1361369000, 0.2313905000, 0.4490744000", \ - "0.0666194000, 0.0756390000, 0.0931355000, 0.1250085000, 0.1805755000, 0.2800140000, 0.4986791000", \ - "0.0686040000, 0.0830906000, 0.1116104000, 0.1617684000, 0.2450024000, 0.3800341000, 0.6118460000", \ - "0.0288541000, 0.0532522000, 0.1007116000, 0.1828636000, 0.3151668000, 0.5183333000, 0.8349410000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0728056000, 0.0825677000, 0.1043992000, 0.1536968000, 0.2658787000, 0.5231505000, 1.1170800000", \ - "0.0753964000, 0.0856101000, 0.1074989000, 0.1573155000, 0.2699438000, 0.5276617000, 1.1216366000", \ - "0.0867471000, 0.0963050000, 0.1178285000, 0.1679936000, 0.2810450000, 0.5390977000, 1.1330729000", \ - "0.1155822000, 0.1250246000, 0.1467211000, 0.1954324000, 0.3086132000, 0.5669313000, 1.1605947000", \ - "0.1765048000, 0.1891403000, 0.2151104000, 0.2653257000, 0.3766986000, 0.6348362000, 1.2288405000", \ - "0.2752061000, 0.2943358000, 0.3336195000, 0.4080483000, 0.5373891000, 0.7936778000, 1.3839930000", \ - "0.4395635000, 0.4675950000, 0.5253882000, 0.6386565000, 0.8385737000, 1.1626594000, 1.7488976000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0156466000, 0.0203732000, 0.0309809000, 0.0549654000, 0.1101928000, 0.2381700000, 0.5275662000", \ - "0.0157000000, 0.0203846000, 0.0310522000, 0.0548614000, 0.1100945000, 0.2377401000, 0.5278678000", \ - "0.0172648000, 0.0214779000, 0.0315423000, 0.0548964000, 0.1096344000, 0.2356447000, 0.5267606000", \ - "0.0249598000, 0.0294181000, 0.0392352000, 0.0598457000, 0.1112195000, 0.2360817000, 0.5273847000", \ - "0.0425666000, 0.0482650000, 0.0600081000, 0.0825715000, 0.1298360000, 0.2420542000, 0.5308812000", \ - "0.0769711000, 0.0851474000, 0.1014417000, 0.1316535000, 0.1855766000, 0.2954378000, 0.5456898000", \ - "0.1450805000, 0.1567443000, 0.1793221000, 0.2228774000, 0.2966207000, 0.4264221000, 0.6697894000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011550700, 0.0026683900, 0.0061643600, 0.0142406000, 0.0328978000, 0.0759987000"); - values("0.0646504000, 0.0768055000, 0.1053515000, 0.1710884000, 0.3222218000, 0.6724806000, 1.4816433000", \ - "0.0647561000, 0.0768130000, 0.1054073000, 0.1711357000, 0.3223569000, 0.6746001000, 1.4819025000", \ - "0.0644487000, 0.0768058000, 0.1052112000, 0.1707169000, 0.3226443000, 0.6714982000, 1.4812548000", \ - "0.0677837000, 0.0788956000, 0.1057489000, 0.1708639000, 0.3221219000, 0.6723755000, 1.4794264000", \ - "0.0945958000, 0.1057825000, 0.1269448000, 0.1818070000, 0.3228569000, 0.6722947000, 1.4789983000", \ - "0.1441728000, 0.1600325000, 0.1917605000, 0.2501022000, 0.3652807000, 0.6776079000, 1.4814793000", \ - "0.2245456000, 0.2489061000, 0.2972317000, 0.3847518000, 0.5351324000, 0.7939341000, 1.5018514000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2ai_2") { - leakage_power () { - value : 0.0044389000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0037635000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0044452000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0044382000; - when : "A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0045657000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0046256000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0034679000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0057336000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0027306000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0019005000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0015994000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0028908000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0030930000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0022633000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0019625000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0032537000; - when : "A1_N&!A2_N&B1&!B2"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__o2bb2ai"; - cell_leakage_power : 0.0034482750; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0049000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0046740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085035000, 0.0084950000, 0.0084754000, 0.0084786000, 0.0084860000, 0.0085032000, 0.0085427000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008453100, -0.008454300, -0.008457200, -0.008458700, -0.008462100, -0.008470100, -0.008488500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051250000; - } - pin ("A2_N") { - capacitance : 0.0044510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087885000, 0.0087798000, 0.0087599000, 0.0087564000, 0.0087483000, 0.0087297000, 0.0086867000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006684200, -0.006681900, -0.006676800, -0.006665300, -0.006638800, -0.006577700, -0.006437000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046450000; - } - pin ("B1") { - capacitance : 0.0048090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0045670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084928000, 0.0084986000, 0.0085120000, 0.0085134000, 0.0085166000, 0.0085239000, 0.0085409000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007407200, -0.007515800, -0.007766300, -0.007778500, -0.007806800, -0.007871900, -0.008022100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0050500000; - } - pin ("B2") { - capacitance : 0.0043440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0035472000, 0.0035387000, 0.0035193000, 0.0035309000, 0.0035577000, 0.0036193000, 0.0037615000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003400900, -0.003396700, -0.003387200, -0.003386200, -0.003383800, -0.003378300, -0.003365700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046410000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (A1_N&A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0280865000, 0.0269116000, 0.0239232000, 0.0161958000, -0.003880100, -0.055627200, -0.187611400", \ - "0.0276907000, 0.0265252000, 0.0235420000, 0.0158180000, -0.004260800, -0.056022800, -0.187971000", \ - "0.0272289000, 0.0260495000, 0.0230659000, 0.0153526000, -0.004699400, -0.056399000, -0.188402500", \ - "0.0267807000, 0.0256140000, 0.0226207000, 0.0149480000, -0.005103800, -0.056725800, -0.188630100", \ - "0.0264435000, 0.0252870000, 0.0222926000, 0.0146062000, -0.005164300, -0.056704100, -0.188545600", \ - "0.0272355000, 0.0260335000, 0.0229276000, 0.0150159000, -0.004532800, -0.055962400, -0.187772400", \ - "0.0303780000, 0.0291740000, 0.0260181000, 0.0180436000, -0.002415500, -0.054183500, -0.185175100"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0252773000, 0.0267124000, 0.0303050000, 0.0388763000, 0.0596090000, 0.1111388000, 0.2414576000", \ - "0.0249305000, 0.0263719000, 0.0299490000, 0.0385423000, 0.0593280000, 0.1109019000, 0.2410973000", \ - "0.0244000000, 0.0258280000, 0.0293803000, 0.0379554000, 0.0587678000, 0.1103181000, 0.2408033000", \ - "0.0237674000, 0.0251574000, 0.0286420000, 0.0371669000, 0.0580258000, 0.1097393000, 0.2403956000", \ - "0.0234805000, 0.0248467000, 0.0282062000, 0.0366576000, 0.0574701000, 0.1093429000, 0.2399541000", \ - "0.0238030000, 0.0250983000, 0.0284397000, 0.0367768000, 0.0571265000, 0.1091474000, 0.2399667000", \ - "0.0257377000, 0.0269948000, 0.0302210000, 0.0385039000, 0.0593139000, 0.1107256000, 0.2413817000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0218522000, 0.0207098000, 0.0177446000, 0.0100662000, -0.010039100, -0.061837300, -0.193788600", \ - "0.0213698000, 0.0202116000, 0.0173095000, 0.0096236000, -0.010481100, -0.062233300, -0.194346200", \ - "0.0208399000, 0.0196797000, 0.0167120000, 0.0090492000, -0.011011800, -0.062761900, -0.194784800", \ - "0.0202646000, 0.0191150000, 0.0161386000, 0.0084429000, -0.011530200, -0.063188300, -0.195175700", \ - "0.0201087000, 0.0189409000, 0.0159650000, 0.0082714000, -0.011697300, -0.063284300, -0.195131100", \ - "0.0206306000, 0.0194056000, 0.0163917000, 0.0084720000, -0.011021900, -0.062492400, -0.194284300", \ - "0.0237689000, 0.0225870000, 0.0193868000, 0.0114814000, -0.008559000, -0.060285200, -0.191442700"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0239572000, 0.0254064000, 0.0289898000, 0.0375969000, 0.0583343000, 0.1097960000, 0.2403094000", \ - "0.0236347000, 0.0250677000, 0.0286432000, 0.0372137000, 0.0580144000, 0.1095485000, 0.2398456000", \ - "0.0230533000, 0.0244666000, 0.0279863000, 0.0365583000, 0.0573529000, 0.1089912000, 0.2395037000", \ - "0.0224410000, 0.0238369000, 0.0272669000, 0.0357493000, 0.0565351000, 0.1083405000, 0.2389124000", \ - "0.0222700000, 0.0235824000, 0.0269555000, 0.0353211000, 0.0560608000, 0.1079925000, 0.2388342000", \ - "0.0231508000, 0.0244483000, 0.0277444000, 0.0358532000, 0.0561546000, 0.1081043000, 0.2391096000", \ - "0.0263528000, 0.0276091000, 0.0309179000, 0.0384606000, 0.0592090000, 0.1102299000, 0.2410461000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0131584000, 0.0119279000, 0.0088100000, 0.0008804000, -0.019459900, -0.071347800, -0.203466900", \ - "0.0130105000, 0.0117884000, 0.0086851000, 0.0007778000, -0.019551300, -0.071432800, -0.203538600", \ - "0.0128617000, 0.0116667000, 0.0086091000, 0.0007621000, -0.019513600, -0.071351000, -0.203464500", \ - "0.0124299000, 0.0112368000, 0.0082414000, 0.0004611000, -0.019709800, -0.071530700, -0.203586500", \ - "0.0126743000, 0.0114484000, 0.0082923000, 0.0001917000, -0.019900800, -0.071531100, -0.203525100", \ - "0.0128207000, 0.0115814000, 0.0084330000, 0.0004047000, -0.019942800, -0.071832600, -0.203649500", \ - "0.0143496000, 0.0130733000, 0.0098432000, 0.0016104000, -0.019070400, -0.071212500, -0.203460100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0149129000, 0.0161791000, 0.0194103000, 0.0274822000, 0.0478823000, 0.0993131000, 0.2298639000", \ - "0.0144745000, 0.0157732000, 0.0190308000, 0.0272117000, 0.0476144000, 0.0991366000, 0.2295823000", \ - "0.0140887000, 0.0153800000, 0.0186258000, 0.0268258000, 0.0473604000, 0.0989516000, 0.2296525000", \ - "0.0137949000, 0.0150674000, 0.0182893000, 0.0264462000, 0.0470331000, 0.0986511000, 0.2292829000", \ - "0.0135707000, 0.0148350000, 0.0180363000, 0.0261802000, 0.0466107000, 0.0983702000, 0.2291457000", \ - "0.0135237000, 0.0147689000, 0.0179532000, 0.0260940000, 0.0465192000, 0.0984225000, 0.2289262000", \ - "0.0140526000, 0.0152365000, 0.0183078000, 0.0260753000, 0.0468835000, 0.0983351000, 0.2296518000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0061910000, 0.0050875000, 0.0021495000, -0.005672700, -0.026015400, -0.078012600, -0.210218300", \ - "0.0059020000, 0.0048430000, 0.0020021000, -0.005697100, -0.025957500, -0.077905100, -0.210096300", \ - "0.0054267000, 0.0043831000, 0.0016270000, -0.005918800, -0.026023700, -0.077877100, -0.210013700", \ - "0.0050516000, 0.0039379000, 0.0011022000, -0.006407600, -0.026291600, -0.077985500, -0.210027600", \ - "0.0054099000, 0.0042296000, 0.0011559000, -0.006844600, -0.026726300, -0.078219700, -0.210109400", \ - "0.0055321000, 0.0042526000, 0.0011266000, -0.006822200, -0.027018300, -0.078678900, -0.210402500", \ - "0.0073722000, 0.0059600000, 0.0025841000, -0.005848800, -0.026524200, -0.078530900, -0.210527800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012705110, 0.0032283970, 0.0082034290, 0.0208450900, 0.0529678500, 0.1345925000"); - values("0.0144607000, 0.0157390000, 0.0189695000, 0.0270747000, 0.0473653000, 0.0988986000, 0.2293106000", \ - "0.0140597000, 0.0153597000, 0.0186369000, 0.0267788000, 0.0471968000, 0.0986833000, 0.2292999000", \ - "0.0136490000, 0.0149489000, 0.0182349000, 0.0263933000, 0.0469891000, 0.0985409000, 0.2292959000", \ - "0.0133304000, 0.0146033000, 0.0178414000, 0.0260610000, 0.0465023000, 0.0982473000, 0.2289951000", \ - "0.0134293000, 0.0146835000, 0.0178310000, 0.0258702000, 0.0460079000, 0.0978494000, 0.2285008000", \ - "0.0145787000, 0.0158336000, 0.0186404000, 0.0265554000, 0.0465843000, 0.0978789000, 0.2281512000", \ - "0.0168195000, 0.0182300000, 0.0216236000, 0.0281389000, 0.0481808000, 0.0986729000, 0.2285031000"); - } - } - max_capacitance : 0.1345920000; - max_transition : 1.4911730000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0865868000, 0.0894919000, 0.0961374000, 0.1112314000, 0.1463111000, 0.2313916000, 0.4452218000", \ - "0.0919131000, 0.0947541000, 0.1013303000, 0.1165770000, 0.1515984000, 0.2367936000, 0.4506375000", \ - "0.1050692000, 0.1079926000, 0.1146878000, 0.1299083000, 0.1649718000, 0.2501855000, 0.4641792000", \ - "0.1369265000, 0.1397116000, 0.1464990000, 0.1616350000, 0.1970710000, 0.2823917000, 0.4961661000", \ - "0.2010460000, 0.2041213000, 0.2111330000, 0.2269278000, 0.2625304000, 0.3480060000, 0.5622092000", \ - "0.3048113000, 0.3081475000, 0.3159582000, 0.3329123000, 0.3693744000, 0.4555522000, 0.6700310000", \ - "0.4715441000, 0.4758761000, 0.4855961000, 0.5055956000, 0.5457938000, 0.6329866000, 0.8475504000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0687866000, 0.0730653000, 0.0829573000, 0.1054368000, 0.1586286000, 0.2902072000, 0.6240842000", \ - "0.0730133000, 0.0772624000, 0.0871570000, 0.1096509000, 0.1629159000, 0.2946556000, 0.6283687000", \ - "0.0821031000, 0.0863680000, 0.0960731000, 0.1185790000, 0.1719042000, 0.3036850000, 0.6364498000", \ - "0.1003242000, 0.1045761000, 0.1144801000, 0.1369361000, 0.1901876000, 0.3229530000, 0.6566913000", \ - "0.1265796000, 0.1310356000, 0.1411983000, 0.1641660000, 0.2181178000, 0.3506449000, 0.6841725000", \ - "0.1544812000, 0.1597729000, 0.1711602000, 0.1951021000, 0.2492138000, 0.3820741000, 0.7168436000", \ - "0.1626287000, 0.1696524000, 0.1841463000, 0.2123654000, 0.2683652000, 0.4009517000, 0.7366973000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0245313000, 0.0273432000, 0.0343043000, 0.0514478000, 0.0949813000, 0.2079858000, 0.4966860000", \ - "0.0245301000, 0.0273285000, 0.0343781000, 0.0514311000, 0.0949691000, 0.2082645000, 0.4971916000", \ - "0.0245461000, 0.0273873000, 0.0343161000, 0.0514243000, 0.0948419000, 0.2079184000, 0.4975670000", \ - "0.0248158000, 0.0275990000, 0.0344006000, 0.0514940000, 0.0949502000, 0.2080452000, 0.4973323000", \ - "0.0267270000, 0.0295868000, 0.0364957000, 0.0533459000, 0.0961175000, 0.2081793000, 0.4977140000", \ - "0.0327180000, 0.0358011000, 0.0423521000, 0.0585918000, 0.0998450000, 0.2103320000, 0.4985155000", \ - "0.0449858000, 0.0481035000, 0.0555428000, 0.0715040000, 0.1092359000, 0.2138442000, 0.4996297000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0313251000, 0.0356027000, 0.0474884000, 0.0777853000, 0.1540273000, 0.3401504000, 0.8100584000", \ - "0.0311318000, 0.0354233000, 0.0473572000, 0.0778398000, 0.1540200000, 0.3400664000, 0.8101180000", \ - "0.0312597000, 0.0355670000, 0.0474582000, 0.0778836000, 0.1540238000, 0.3401745000, 0.8097035000", \ - "0.0324601000, 0.0369332000, 0.0481253000, 0.0782540000, 0.1540474000, 0.3401245000, 0.8101548000", \ - "0.0360500000, 0.0402548000, 0.0509086000, 0.0800848000, 0.1551109000, 0.3404127000, 0.8106223000", \ - "0.0445640000, 0.0477555000, 0.0574481000, 0.0840063000, 0.1564076000, 0.3413878000, 0.8106180000", \ - "0.0640450000, 0.0664070000, 0.0738291000, 0.0963074000, 0.1617718000, 0.3421956000, 0.8120943000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0884103000, 0.0913835000, 0.0983467000, 0.1139411000, 0.1494132000, 0.2347142000, 0.4485831000", \ - "0.0928719000, 0.0959515000, 0.1031575000, 0.1188186000, 0.1542921000, 0.2395918000, 0.4534776000", \ - "0.1058212000, 0.1087914000, 0.1157126000, 0.1314692000, 0.1670381000, 0.2522901000, 0.4661753000", \ - "0.1370359000, 0.1400293000, 0.1470022000, 0.1626990000, 0.1982512000, 0.2836892000, 0.4976960000", \ - "0.1984922000, 0.2015034000, 0.2089419000, 0.2253669000, 0.2617319000, 0.3473307000, 0.5613575000", \ - "0.2986647000, 0.3022898000, 0.3103124000, 0.3285166000, 0.3663029000, 0.4517036000, 0.6661576000", \ - "0.4634497000, 0.4680973000, 0.4785943000, 0.5003770000, 0.5416974000, 0.6298841000, 0.8445236000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0636859000, 0.0678641000, 0.0777747000, 0.1001612000, 0.1531370000, 0.2854167000, 0.6177801000", \ - "0.0674845000, 0.0717419000, 0.0816205000, 0.1040993000, 0.1573556000, 0.2890636000, 0.6229501000", \ - "0.0771864000, 0.0813545000, 0.0911015000, 0.1133762000, 0.1666174000, 0.2989655000, 0.6349122000", \ - "0.0944812000, 0.0987150000, 0.1085493000, 0.1309956000, 0.1845586000, 0.3166785000, 0.6500558000", \ - "0.1161810000, 0.1205919000, 0.1305620000, 0.1533407000, 0.2076595000, 0.3400849000, 0.6750200000", \ - "0.1347934000, 0.1398396000, 0.1507287000, 0.1738649000, 0.2273226000, 0.3615797000, 0.6949831000", \ - "0.1245493000, 0.1312321000, 0.1452360000, 0.1720922000, 0.2266599000, 0.3582202000, 0.6923421000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0255460000, 0.0284040000, 0.0354128000, 0.0526490000, 0.0957331000, 0.2084537000, 0.4971433000", \ - "0.0255215000, 0.0284353000, 0.0354226000, 0.0527131000, 0.0958436000, 0.2084681000, 0.4979598000", \ - "0.0255607000, 0.0284472000, 0.0355496000, 0.0526202000, 0.0958123000, 0.2082512000, 0.4974037000", \ - "0.0256643000, 0.0286975000, 0.0355449000, 0.0527421000, 0.0959011000, 0.2080909000, 0.4972975000", \ - "0.0284345000, 0.0315136000, 0.0385638000, 0.0553538000, 0.0977623000, 0.2087785000, 0.4972449000", \ - "0.0356359000, 0.0385696000, 0.0456916000, 0.0618422000, 0.1024968000, 0.2119601000, 0.4985970000", \ - "0.0481995000, 0.0518542000, 0.0598461000, 0.0766672000, 0.1147963000, 0.2169108000, 0.5009422000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0310225000, 0.0353677000, 0.0473722000, 0.0779606000, 0.1539959000, 0.3401751000, 0.8086676000", \ - "0.0311606000, 0.0354526000, 0.0474875000, 0.0779628000, 0.1540252000, 0.3401870000, 0.8101003000", \ - "0.0311732000, 0.0357254000, 0.0474322000, 0.0780298000, 0.1540602000, 0.3401143000, 0.8109051000", \ - "0.0331647000, 0.0373368000, 0.0487030000, 0.0786304000, 0.1541471000, 0.3400272000, 0.8093429000", \ - "0.0361680000, 0.0399368000, 0.0509049000, 0.0804343000, 0.1557249000, 0.3407981000, 0.8103835000", \ - "0.0447131000, 0.0478234000, 0.0569182000, 0.0838442000, 0.1566188000, 0.3420707000, 0.8103078000", \ - "0.0641174000, 0.0662539000, 0.0730238000, 0.0950934000, 0.1608248000, 0.3425593000, 0.8113956000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0349202000, 0.0374584000, 0.0436529000, 0.0580933000, 0.0927199000, 0.1776511000, 0.3914001000", \ - "0.0391849000, 0.0417987000, 0.0479814000, 0.0624481000, 0.0971139000, 0.1820912000, 0.3957663000", \ - "0.0481652000, 0.0507384000, 0.0569088000, 0.0715256000, 0.1062266000, 0.1911314000, 0.4049366000", \ - "0.0629435000, 0.0661443000, 0.0738562000, 0.0904853000, 0.1261904000, 0.2116327000, 0.4257880000", \ - "0.0822745000, 0.0869589000, 0.0978832000, 0.1208368000, 0.1668347000, 0.2589813000, 0.4739590000", \ - "0.0955835000, 0.1029775000, 0.1207880000, 0.1562901000, 0.2257197000, 0.3496214000, 0.5853005000", \ - "0.0764286000, 0.0883885000, 0.1160179000, 0.1745493000, 0.2846888000, 0.4755829000, 0.7940600000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0892662000, 0.0956564000, 0.1109107000, 0.1501952000, 0.2471028000, 0.4909304000, 1.1086484000", \ - "0.0937441000, 0.1001276000, 0.1161358000, 0.1553198000, 0.2526572000, 0.4966445000, 1.1140378000", \ - "0.1056349000, 0.1123771000, 0.1281616000, 0.1676057000, 0.2653164000, 0.5099512000, 1.1276625000", \ - "0.1332702000, 0.1396256000, 0.1554054000, 0.1946564000, 0.2925447000, 0.5377859000, 1.1558349000", \ - "0.1885778000, 0.1960330000, 0.2141019000, 0.2559641000, 0.3534671000, 0.5986547000, 1.2179610000", \ - "0.2823414000, 0.2932463000, 0.3177009000, 0.3734206000, 0.4913537000, 0.7410086000, 1.3604186000", \ - "0.4391509000, 0.4557195000, 0.4939673000, 0.5773433000, 0.7403382000, 1.0525523000, 1.6890397000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0222622000, 0.0251178000, 0.0321473000, 0.0498432000, 0.0944079000, 0.2080959000, 0.4969177000", \ - "0.0221385000, 0.0249970000, 0.0320709000, 0.0498821000, 0.0944984000, 0.2079874000, 0.4972087000", \ - "0.0226480000, 0.0253977000, 0.0322862000, 0.0497304000, 0.0943847000, 0.2081134000, 0.4969399000", \ - "0.0291693000, 0.0318521000, 0.0385398000, 0.0545846000, 0.0961074000, 0.2085873000, 0.4978100000", \ - "0.0453473000, 0.0487077000, 0.0567039000, 0.0746232000, 0.1147409000, 0.2154772000, 0.4980102000", \ - "0.0777405000, 0.0828126000, 0.0939608000, 0.1179646000, 0.1662381000, 0.2663735000, 0.5170996000", \ - "0.1391197000, 0.1468773000, 0.1634104000, 0.1994904000, 0.2678341000, 0.3925016000, 0.6386733000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0634482000, 0.0715749000, 0.0923288000, 0.1445890000, 0.2777512000, 0.6150015000, 1.4743513000", \ - "0.0634408000, 0.0714456000, 0.0922737000, 0.1449531000, 0.2787975000, 0.6142778000, 1.4703482000", \ - "0.0634972000, 0.0714475000, 0.0921300000, 0.1445984000, 0.2774466000, 0.6142972000, 1.4700983000", \ - "0.0641754000, 0.0719430000, 0.0923229000, 0.1447764000, 0.2777560000, 0.6153582000, 1.4715050000", \ - "0.0808882000, 0.0885028000, 0.1061239000, 0.1529569000, 0.2787733000, 0.6148309000, 1.4697991000", \ - "0.1189133000, 0.1273980000, 0.1482866000, 0.1974421000, 0.3139143000, 0.6206926000, 1.4722396000", \ - "0.1973821000, 0.2091121000, 0.2362817000, 0.2969863000, 0.4238720000, 0.7096121000, 1.4877619000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0282814000, 0.0307798000, 0.0368624000, 0.0515150000, 0.0869126000, 0.1750911000, 0.3981785000", \ - "0.0324471000, 0.0350843000, 0.0412992000, 0.0560431000, 0.0916475000, 0.1800361000, 0.4028709000", \ - "0.0398598000, 0.0427618000, 0.0494235000, 0.0644873000, 0.1003487000, 0.1888592000, 0.4118063000", \ - "0.0499309000, 0.0536933000, 0.0623605000, 0.0805775000, 0.1186635000, 0.2076476000, 0.4312369000", \ - "0.0586080000, 0.0644671000, 0.0779890000, 0.1045859000, 0.1550285000, 0.2515159000, 0.4773700000", \ - "0.0524866000, 0.0626084000, 0.0842601000, 0.1271853000, 0.2036499000, 0.3348703000, 0.5800744000", \ - "-0.002320800, 0.0139874000, 0.0508419000, 0.1209288000, 0.2441576000, 0.4457916000, 0.7796754000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0711312000, 0.0775278000, 0.0932596000, 0.1321634000, 0.2292779000, 0.4729513000, 1.0922837000", \ - "0.0743973000, 0.0809877000, 0.0969285000, 0.1359944000, 0.2333587000, 0.4776812000, 1.0953186000", \ - "0.0851240000, 0.0913411000, 0.1075321000, 0.1467222000, 0.2443860000, 0.4888018000, 1.1066440000", \ - "0.1138766000, 0.1201089000, 0.1358817000, 0.1748643000, 0.2722167000, 0.5161415000, 1.1347271000", \ - "0.1746225000, 0.1831082000, 0.2025694000, 0.2441152000, 0.3395513000, 0.5841296000, 1.2046864000", \ - "0.2746160000, 0.2871065000, 0.3159187000, 0.3781867000, 0.4986598000, 0.7433267000, 1.3585719000", \ - "0.4426597000, 0.4594307000, 0.5023585000, 0.5966322000, 0.7799801000, 1.1055635000, 1.7253099000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0141836000, 0.0173022000, 0.0250914000, 0.0442079000, 0.0921777000, 0.2130510000, 0.5174328000", \ - "0.0142044000, 0.0173248000, 0.0250442000, 0.0441920000, 0.0921895000, 0.2115233000, 0.5166185000", \ - "0.0159565000, 0.0186996000, 0.0259099000, 0.0444099000, 0.0922529000, 0.2115354000, 0.5166444000", \ - "0.0226311000, 0.0256433000, 0.0330451000, 0.0503745000, 0.0939153000, 0.2118423000, 0.5168581000", \ - "0.0390409000, 0.0428402000, 0.0515429000, 0.0705459000, 0.1135934000, 0.2193494000, 0.5189427000", \ - "0.0716192000, 0.0768905000, 0.0891200000, 0.1144262000, 0.1644549000, 0.2699536000, 0.5352017000", \ - "0.1383118000, 0.1458616000, 0.1618736000, 0.1972450000, 0.2643932000, 0.3913041000, 0.6574840000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012705100, 0.0032284000, 0.0082034300, 0.0208451000, 0.0529678000, 0.1345920000"); - values("0.0640060000, 0.0721305000, 0.0927377000, 0.1451984000, 0.2784372000, 0.6149657000, 1.4748512000", \ - "0.0640687000, 0.0720851000, 0.0925642000, 0.1452620000, 0.2777979000, 0.6172649000, 1.4740587000", \ - "0.0637545000, 0.0721574000, 0.0926296000, 0.1449995000, 0.2778069000, 0.6151858000, 1.4698982000", \ - "0.0670894000, 0.0743791000, 0.0934397000, 0.1446038000, 0.2784513000, 0.6146140000, 1.4708699000", \ - "0.0933850000, 0.1003327000, 0.1174450000, 0.1589314000, 0.2797785000, 0.6148888000, 1.4730555000", \ - "0.1386929000, 0.1498634000, 0.1732829000, 0.2250478000, 0.3290154000, 0.6246636000, 1.4756598000", \ - "0.2126287000, 0.2288108000, 0.2667750000, 0.3449304000, 0.4876246000, 0.7480769000, 1.4911731000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o2bb2ai_4") { - leakage_power () { - value : 0.0080652000; - when : "!A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0034842000; - when : "!A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0042097000; - when : "!A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0064620000; - when : "!A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0093820000; - when : "!A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0048002000; - when : "!A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0055262000; - when : "!A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0077785000; - when : "!A1_N&A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0098197000; - when : "A1_N&!A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0052387000; - when : "A1_N&!A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0059647000; - when : "A1_N&!A2_N&B1&B2"; - } - leakage_power () { - value : 0.0082170000; - when : "A1_N&!A2_N&B1&!B2"; - } - leakage_power () { - value : 0.0072939000; - when : "A1_N&A2_N&!B1&B2"; - } - leakage_power () { - value : 0.0056414000; - when : "A1_N&A2_N&!B1&!B2"; - } - leakage_power () { - value : 0.0072965000; - when : "A1_N&A2_N&B1&B2"; - } - leakage_power () { - value : 0.0072939000; - when : "A1_N&A2_N&B1&!B2"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__o2bb2ai"; - cell_leakage_power : 0.0066546030; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1_N") { - capacitance : 0.0087480000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156546000, 0.0156322000, 0.0155805000, 0.0155744000, 0.0155604000, 0.0155282000, 0.0154537000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015564200, -0.015556400, -0.015538500, -0.015536300, -0.015531200, -0.015519600, -0.015492700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091920000; - } - pin ("A2_N") { - capacitance : 0.0088120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0085190000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0182696000, 0.0182705000, 0.0182726000, 0.0182723000, 0.0182718000, 0.0182704000, 0.0182674000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013044900, -0.013048200, -0.013055600, -0.013026400, -0.012959200, -0.012804100, -0.012446800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091050000; - } - pin ("B1") { - capacitance : 0.0086730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0166930000, 0.0166750000, 0.0166337000, 0.0166359000, 0.0166409000, 0.0166524000, 0.0166789000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.014220300, -0.014459400, -0.015010700, -0.015031500, -0.015079300, -0.015189600, -0.015443700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091180000; - } - pin ("B2") { - capacitance : 0.0084840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078329000, 0.0078247000, 0.0078059000, 0.0078386000, 0.0079140000, 0.0080878000, 0.0084885000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006813900, -0.006812000, -0.006807800, -0.006808500, -0.006810100, -0.006813700, -0.006822200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090790000; - } - pin ("Y") { - direction : "output"; - function : "(!B1&!B2) | (A1_N&A2_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0589504000, 0.0575695000, 0.0536743000, 0.0425133000, 0.0107369000, -0.080138800, -0.336562300", \ - "0.0581908000, 0.0568019000, 0.0529004000, 0.0417678000, 0.0099968000, -0.080854900, -0.337310300", \ - "0.0573026000, 0.0559310000, 0.0520060000, 0.0409335000, 0.0091514000, -0.081554200, -0.337897800", \ - "0.0563944000, 0.0550135000, 0.0511303000, 0.0399861000, 0.0082566000, -0.082395500, -0.338646800", \ - "0.0558562000, 0.0544611000, 0.0504999000, 0.0393919000, 0.0076466000, -0.082658000, -0.338884300", \ - "0.0567193000, 0.0552582000, 0.0512147000, 0.0402419000, 0.0095059000, -0.080926300, -0.337018100", \ - "0.0617152000, 0.0602899000, 0.0561350000, 0.0448070000, 0.0145380000, -0.077366600, -0.333032200"); - } - related_pin : "A1_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0499080000, 0.0516123000, 0.0563518000, 0.0690523000, 0.1023754000, 0.1930448000, 0.4465540000", \ - "0.0492876000, 0.0509975000, 0.0557271000, 0.0684197000, 0.1018394000, 0.1924787000, 0.4460108000", \ - "0.0483101000, 0.0499939000, 0.0547047000, 0.0673913000, 0.1007410000, 0.1915881000, 0.4453795000", \ - "0.0472066000, 0.0488262000, 0.0533985000, 0.0659414000, 0.0994880000, 0.1904542000, 0.4441750000", \ - "0.0465767000, 0.0481526000, 0.0525871000, 0.0649261000, 0.0984485000, 0.1896597000, 0.4435560000", \ - "0.0472592000, 0.0487785000, 0.0530638000, 0.0651426000, 0.0977636000, 0.1894278000, 0.4436436000", \ - "0.0497946000, 0.0513233000, 0.0555253000, 0.0673704000, 0.1007077000, 0.1915231000, 0.4462125000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0455444000, 0.0441641000, 0.0402686000, 0.0291489000, -0.002761900, -0.093792900, -0.350324700", \ - "0.0447309000, 0.0433706000, 0.0395456000, 0.0284343000, -0.003466800, -0.094560000, -0.351206900", \ - "0.0436152000, 0.0422469000, 0.0383982000, 0.0272968000, -0.004523400, -0.095394600, -0.352192300", \ - "0.0425573000, 0.0410425000, 0.0371763000, 0.0261170000, -0.005536500, -0.096440900, -0.352835400", \ - "0.0427959000, 0.0413852000, 0.0374465000, 0.0262817000, -0.006206900, -0.096049300, -0.352487100", \ - "0.0426322000, 0.0412777000, 0.0378058000, 0.0264333000, -0.004250700, -0.094685000, -0.350847700", \ - "0.0489916000, 0.0476728000, 0.0435249000, 0.0324776000, 0.0009242000, -0.089872800, -0.345074200"); - } - related_pin : "A2_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0468429000, 0.0485520000, 0.0532983000, 0.0659474000, 0.0994058000, 0.1900617000, 0.4437297000", \ - "0.0461583000, 0.0478730000, 0.0526049000, 0.0653163000, 0.0986999000, 0.1894565000, 0.4429589000", \ - "0.0451046000, 0.0467834000, 0.0514825000, 0.0641420000, 0.0975538000, 0.1884213000, 0.4421137000", \ - "0.0441347000, 0.0457413000, 0.0502747000, 0.0627577000, 0.0963043000, 0.1873384000, 0.4413320000", \ - "0.0440077000, 0.0456018000, 0.0500215000, 0.0622129000, 0.0954130000, 0.1867875000, 0.4410911000", \ - "0.0457703000, 0.0472972000, 0.0515980000, 0.0634347000, 0.0960744000, 0.1874342000, 0.4419009000", \ - "0.0525055000, 0.0539866000, 0.0581428000, 0.0704578000, 0.1033568000, 0.1924712000, 0.4470382000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0288414000, 0.0273970000, 0.0233319000, 0.0118975000, -0.020405600, -0.111563300, -0.368286800", \ - "0.0285616000, 0.0271476000, 0.0230968000, 0.0116882000, -0.020546500, -0.111654200, -0.368434700", \ - "0.0284140000, 0.0270189000, 0.0230207000, 0.0116930000, -0.020452100, -0.111444900, -0.368194500", \ - "0.0275928000, 0.0261694000, 0.0222363000, 0.0110486000, -0.020926800, -0.111772500, -0.368383000", \ - "0.0271852000, 0.0257825000, 0.0217665000, 0.0104583000, -0.021192000, -0.111947800, -0.368379900", \ - "0.0281637000, 0.0267370000, 0.0226191000, 0.0110985000, -0.021601500, -0.112357900, -0.368572600", \ - "0.0309624000, 0.0296472000, 0.0252347000, 0.0133827000, -0.019530000, -0.111344100, -0.368178400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0287817000, 0.0302726000, 0.0344072000, 0.0459619000, 0.0783284000, 0.1688462000, 0.4224280000", \ - "0.0280949000, 0.0296160000, 0.0338092000, 0.0455259000, 0.0780416000, 0.1685463000, 0.4223398000", \ - "0.0274864000, 0.0289652000, 0.0331779000, 0.0449534000, 0.0775563000, 0.1682982000, 0.4220652000", \ - "0.0268604000, 0.0283795000, 0.0325619000, 0.0443034000, 0.0770871000, 0.1678658000, 0.4217725000", \ - "0.0264093000, 0.0278835000, 0.0320622000, 0.0437036000, 0.0762737000, 0.1671581000, 0.4213654000", \ - "0.0262324000, 0.0276762000, 0.0317808000, 0.0435008000, 0.0760942000, 0.1669070000, 0.4209789000", \ - "0.0270493000, 0.0284741000, 0.0324158000, 0.0436109000, 0.0765931000, 0.1669870000, 0.4223974000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0137695000, 0.0125026000, 0.0087806000, -0.002290900, -0.034511200, -0.125849400, -0.382793100", \ - "0.0130871000, 0.0118623000, 0.0083105000, -0.002468400, -0.034416700, -0.125565000, -0.382422400", \ - "0.0120575000, 0.0108661000, 0.0073982000, -0.003112800, -0.034645500, -0.125515500, -0.382304000", \ - "0.0111285000, 0.0098424000, 0.0062146000, -0.004297700, -0.035451900, -0.125867600, -0.382295700", \ - "0.0114767000, 0.0100897000, 0.0061283000, -0.005262000, -0.036516900, -0.126502800, -0.382472200", \ - "0.0122242000, 0.0106430000, 0.0065921000, -0.004842800, -0.037040300, -0.127555600, -0.383202000", \ - "0.0162883000, 0.0147471000, 0.0101887000, -0.002076800, -0.035415900, -0.127013200, -0.383538700"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014051260, 0.0039487570, 0.0110970000, 0.0311853600, 0.0876387000, 0.2462868000"); - values("0.0285473000, 0.0300707000, 0.0342677000, 0.0459685000, 0.0784371000, 0.1688187000, 0.4224739000", \ - "0.0274751000, 0.0290013000, 0.0333269000, 0.0451646000, 0.0778145000, 0.1685746000, 0.4223577000", \ - "0.0262895000, 0.0278311000, 0.0321551000, 0.0439863000, 0.0770823000, 0.1679575000, 0.4219751000", \ - "0.0256125000, 0.0271106000, 0.0314661000, 0.0434033000, 0.0761681000, 0.1675652000, 0.4215603000", \ - "0.0257166000, 0.0271707000, 0.0312592000, 0.0429394000, 0.0755870000, 0.1663306000, 0.4207025000", \ - "0.0289214000, 0.0301326000, 0.0341073000, 0.0459620000, 0.0770850000, 0.1660850000, 0.4201670000", \ - "0.0340251000, 0.0354058000, 0.0393830000, 0.0503774000, 0.0820838000, 0.1728246000, 0.4205182000"); - } - } - max_capacitance : 0.2462870000; - max_transition : 1.4976470000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.1035425000, 0.1057014000, 0.1114482000, 0.1254291000, 0.1610821000, 0.2558854000, 0.5181809000", \ - "0.1087730000, 0.1108377000, 0.1163203000, 0.1305358000, 0.1662159000, 0.2610287000, 0.5233294000", \ - "0.1219517000, 0.1240989000, 0.1296382000, 0.1438975000, 0.1797019000, 0.2744906000, 0.5363601000", \ - "0.1540183000, 0.1561807000, 0.1619429000, 0.1760860000, 0.2120331000, 0.3070121000, 0.5693769000", \ - "0.2229587000, 0.2251803000, 0.2308342000, 0.2455654000, 0.2819242000, 0.3769346000, 0.6390071000", \ - "0.3390347000, 0.3414432000, 0.3476301000, 0.3630897000, 0.4006265000, 0.4966366000, 0.7591037000", \ - "0.5313049000, 0.5343014000, 0.5420510000, 0.5600125000, 0.6014004000, 0.6975872000, 0.9605940000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0816007000, 0.0845987000, 0.0923503000, 0.1109525000, 0.1564826000, 0.2775428000, 0.6166185000", \ - "0.0856757000, 0.0887009000, 0.0963690000, 0.1151907000, 0.1608281000, 0.2822113000, 0.6197386000", \ - "0.0938238000, 0.0968234000, 0.1045097000, 0.1231182000, 0.1687978000, 0.2899696000, 0.6291900000", \ - "0.1105811000, 0.1135172000, 0.1211838000, 0.1400862000, 0.1859541000, 0.3072992000, 0.6455313000", \ - "0.1349035000, 0.1379571000, 0.1459413000, 0.1651199000, 0.2120673000, 0.3343805000, 0.6729745000", \ - "0.1586951000, 0.1621510000, 0.1710355000, 0.1917078000, 0.2391597000, 0.3626432000, 0.7016234000", \ - "0.1543999000, 0.1589671000, 0.1705059000, 0.1956146000, 0.2468056000, 0.3702265000, 0.7097800000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0296605000, 0.0318793000, 0.0380326000, 0.0547347000, 0.1007519000, 0.2321176000, 0.6048143000", \ - "0.0296492000, 0.0318680000, 0.0381414000, 0.0547564000, 0.1007520000, 0.2321801000, 0.6045058000", \ - "0.0296314000, 0.0319171000, 0.0381068000, 0.0548463000, 0.1007123000, 0.2320046000, 0.6042229000", \ - "0.0296970000, 0.0318869000, 0.0381007000, 0.0547690000, 0.1006269000, 0.2322557000, 0.6048368000", \ - "0.0311411000, 0.0335506000, 0.0397177000, 0.0561550000, 0.1015494000, 0.2321220000, 0.6044063000", \ - "0.0365973000, 0.0388718000, 0.0452761000, 0.0613670000, 0.1054302000, 0.2342450000, 0.6055072000", \ - "0.0484547000, 0.0509239000, 0.0572430000, 0.0739916000, 0.1146038000, 0.2378592000, 0.6067541000"); - } - related_pin : "A1_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0407764000, 0.0433149000, 0.0509416000, 0.0737049000, 0.1369787000, 0.3101594000, 0.7966623000", \ - "0.0409196000, 0.0434943000, 0.0509207000, 0.0735616000, 0.1369856000, 0.3100478000, 0.7961333000", \ - "0.0408516000, 0.0433577000, 0.0509791000, 0.0737352000, 0.1369502000, 0.3101673000, 0.7965614000", \ - "0.0420116000, 0.0444748000, 0.0518909000, 0.0741013000, 0.1371490000, 0.3100554000, 0.7960659000", \ - "0.0457439000, 0.0480222000, 0.0550624000, 0.0767634000, 0.1388777000, 0.3106367000, 0.7961343000", \ - "0.0548402000, 0.0565277000, 0.0628137000, 0.0819345000, 0.1410953000, 0.3119521000, 0.7973156000", \ - "0.0758077000, 0.0768513000, 0.0811537000, 0.0970306000, 0.1489269000, 0.3135128000, 0.7975875000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0865732000, 0.0887329000, 0.0942693000, 0.1082456000, 0.1438315000, 0.2384201000, 0.5004502000", \ - "0.0918176000, 0.0939403000, 0.0994471000, 0.1134892000, 0.1490721000, 0.2437560000, 0.5055781000", \ - "0.1048301000, 0.1069444000, 0.1126017000, 0.1266035000, 0.1622214000, 0.2568371000, 0.5185838000", \ - "0.1358929000, 0.1379171000, 0.1435243000, 0.1575276000, 0.1931961000, 0.2882896000, 0.5503143000", \ - "0.1943747000, 0.1963818000, 0.2023482000, 0.2170337000, 0.2539198000, 0.3482040000, 0.6106504000", \ - "0.2900274000, 0.2925153000, 0.2988123000, 0.3147616000, 0.3520200000, 0.4481772000, 0.7110884000", \ - "0.4481519000, 0.4513087000, 0.4592246000, 0.4779937000, 0.5196525000, 0.6167121000, 0.8797156000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0749157000, 0.0779012000, 0.0856347000, 0.1042957000, 0.1498558000, 0.2717100000, 0.6090498000", \ - "0.0785597000, 0.0815721000, 0.0893265000, 0.1079232000, 0.1535477000, 0.2746979000, 0.6140100000", \ - "0.0878975000, 0.0908285000, 0.0985276000, 0.1171021000, 0.1628689000, 0.2840795000, 0.6220154000", \ - "0.1063765000, 0.1093717000, 0.1170419000, 0.1357728000, 0.1816915000, 0.3041812000, 0.6420606000", \ - "0.1297404000, 0.1327737000, 0.1404430000, 0.1595344000, 0.2067872000, 0.3297764000, 0.6682140000", \ - "0.1512249000, 0.1545686000, 0.1631127000, 0.1829908000, 0.2301059000, 0.3527775000, 0.6936882000", \ - "0.1469970000, 0.1514292000, 0.1621024000, 0.1857103000, 0.2348530000, 0.3580778000, 0.6968552000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0286617000, 0.0309184000, 0.0369789000, 0.0537739000, 0.0998783000, 0.2319004000, 0.6046492000", \ - "0.0286673000, 0.0309101000, 0.0370887000, 0.0537470000, 0.1000253000, 0.2318472000, 0.6044696000", \ - "0.0287946000, 0.0309349000, 0.0370920000, 0.0537558000, 0.0998618000, 0.2316707000, 0.6041984000", \ - "0.0288904000, 0.0311718000, 0.0372862000, 0.0540561000, 0.1000309000, 0.2318792000, 0.6046417000", \ - "0.0312326000, 0.0337263000, 0.0398019000, 0.0565451000, 0.1016219000, 0.2320627000, 0.6044221000", \ - "0.0368500000, 0.0395889000, 0.0457829000, 0.0616434000, 0.1058161000, 0.2346834000, 0.6053794000", \ - "0.0489643000, 0.0517673000, 0.0585343000, 0.0748010000, 0.1160722000, 0.2380930000, 0.6070737000"); - } - related_pin : "A2_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0407857000, 0.0433679000, 0.0509531000, 0.0735073000, 0.1369863000, 0.3100327000, 0.7961473000", \ - "0.0408073000, 0.0433046000, 0.0509215000, 0.0737009000, 0.1369607000, 0.3101537000, 0.7964708000", \ - "0.0408624000, 0.0433662000, 0.0509920000, 0.0736985000, 0.1370075000, 0.3100553000, 0.7965206000", \ - "0.0425751000, 0.0450053000, 0.0524249000, 0.0745912000, 0.1372950000, 0.3100727000, 0.7964272000", \ - "0.0456010000, 0.0479720000, 0.0551332000, 0.0771327000, 0.1397697000, 0.3113409000, 0.7965927000", \ - "0.0548037000, 0.0564317000, 0.0621710000, 0.0816160000, 0.1411673000, 0.3128779000, 0.7979462000", \ - "0.0758090000, 0.0767865000, 0.0803344000, 0.0947104000, 0.1475902000, 0.3136436000, 0.7998107000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0418340000, 0.0437820000, 0.0488309000, 0.0621726000, 0.0971860000, 0.1914170000, 0.4534076000", \ - "0.0460308000, 0.0478813000, 0.0530631000, 0.0664027000, 0.1012689000, 0.1956917000, 0.4575130000", \ - "0.0538168000, 0.0557593000, 0.0608877000, 0.0743026000, 0.1094620000, 0.2037608000, 0.4656625000", \ - "0.0674307000, 0.0695186000, 0.0754466000, 0.0902955000, 0.1263168000, 0.2210897000, 0.4831427000", \ - "0.0858081000, 0.0889251000, 0.0968566000, 0.1162088000, 0.1607267000, 0.2612165000, 0.5244166000", \ - "0.0981283000, 0.1028242000, 0.1152013000, 0.1451570000, 0.2100818000, 0.3394718000, 0.6186845000", \ - "0.0760301000, 0.0833044000, 0.1029868000, 0.1508268000, 0.2526148000, 0.4473633000, 0.8042423000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0954038000, 0.0998102000, 0.1114390000, 0.1426794000, 0.2281813000, 0.4653282000, 1.1285338000", \ - "0.1004263000, 0.1041528000, 0.1159554000, 0.1474441000, 0.2332776000, 0.4705755000, 1.1339186000", \ - "0.1123822000, 0.1165319000, 0.1284926000, 0.1601767000, 0.2463497000, 0.4840477000, 1.1480829000", \ - "0.1400730000, 0.1443912000, 0.1558650000, 0.1871100000, 0.2736909000, 0.5120399000, 1.1758390000", \ - "0.1955853000, 0.2003245000, 0.2133603000, 0.2476274000, 0.3337300000, 0.5721653000, 1.2363559000", \ - "0.2914100000, 0.2980343000, 0.3153480000, 0.3597551000, 0.4657178000, 0.7105843000, 1.3760855000", \ - "0.4505435000, 0.4610645000, 0.4882826000, 0.5544674000, 0.7026534000, 1.0110823000, 1.6963317000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0268701000, 0.0290765000, 0.0352380000, 0.0522070000, 0.0992964000, 0.2317063000, 0.6046657000", \ - "0.0267649000, 0.0290469000, 0.0352048000, 0.0522450000, 0.0993733000, 0.2317536000, 0.6047081000", \ - "0.0271307000, 0.0293210000, 0.0353495000, 0.0521338000, 0.0993105000, 0.2314846000, 0.6041647000", \ - "0.0321943000, 0.0343223000, 0.0403195000, 0.0562272000, 0.1008828000, 0.2316339000, 0.6044500000", \ - "0.0472562000, 0.0496729000, 0.0558932000, 0.0728898000, 0.1167409000, 0.2380499000, 0.6039778000", \ - "0.0796895000, 0.0830352000, 0.0915881000, 0.1131830000, 0.1617485000, 0.2799837000, 0.6170073000", \ - "0.1416841000, 0.1463503000, 0.1590888000, 0.1899025000, 0.2560934000, 0.3937055000, 0.7151181000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0694483000, 0.0744725000, 0.0887411000, 0.1296663000, 0.2444576000, 0.5683002000, 1.4763658000", \ - "0.0690684000, 0.0746034000, 0.0888317000, 0.1295155000, 0.2445742000, 0.5680293000, 1.4764426000", \ - "0.0694234000, 0.0745116000, 0.0889495000, 0.1298308000, 0.2446020000, 0.5690210000, 1.4811312000", \ - "0.0695144000, 0.0745829000, 0.0888898000, 0.1296393000, 0.2446739000, 0.5679864000, 1.4766404000", \ - "0.0847546000, 0.0893966000, 0.1018017000, 0.1381207000, 0.2466857000, 0.5693205000, 1.4762146000", \ - "0.1208637000, 0.1259165000, 0.1409522000, 0.1800627000, 0.2803681000, 0.5758780000, 1.4765110000", \ - "0.1987110000, 0.2062941000, 0.2256862000, 0.2734605000, 0.3876303000, 0.6639322000, 1.4932584000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0314864000, 0.0332801000, 0.0380847000, 0.0506118000, 0.0835803000, 0.1738860000, 0.4260002000", \ - "0.0355151000, 0.0373640000, 0.0423474000, 0.0548915000, 0.0882288000, 0.1788002000, 0.4335120000", \ - "0.0428965000, 0.0449494000, 0.0501630000, 0.0632579000, 0.0967022000, 0.1872124000, 0.4396440000", \ - "0.0525893000, 0.0552279000, 0.0619148000, 0.0780244000, 0.1142790000, 0.2057568000, 0.4584198000", \ - "0.0603846000, 0.0643547000, 0.0747415000, 0.0985084000, 0.1465570000, 0.2478958000, 0.5032688000", \ - "0.0530049000, 0.0591993000, 0.0755505000, 0.1132954000, 0.1876981000, 0.3250719000, 0.6007730000", \ - "-0.007212400, 0.0044066000, 0.0319101000, 0.0934002000, 0.2120465000, 0.4241283000, 0.7935125000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0762067000, 0.0804618000, 0.0923888000, 0.1238936000, 0.2095998000, 0.4470071000, 1.1113056000", \ - "0.0787543000, 0.0832567000, 0.0951600000, 0.1271415000, 0.2133692000, 0.4509899000, 1.1142842000", \ - "0.0880737000, 0.0927048000, 0.1045509000, 0.1364191000, 0.2232891000, 0.4617200000, 1.1259725000", \ - "0.1160428000, 0.1201554000, 0.1318605000, 0.1635326000, 0.2496490000, 0.4886258000, 1.1530356000", \ - "0.1770545000, 0.1824745000, 0.1966513000, 0.2313225000, 0.3165226000, 0.5541918000, 1.2199391000", \ - "0.2762799000, 0.2842807000, 0.3054157000, 0.3568534000, 0.4696151000, 0.7065389000, 1.3683716000", \ - "0.4443951000, 0.4553642000, 0.4859542000, 0.5613393000, 0.7309706000, 1.0613942000, 1.7337400000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0157060000, 0.0179044000, 0.0240275000, 0.0407686000, 0.0865506000, 0.2145343000, 0.5734797000", \ - "0.0157525000, 0.0179234000, 0.0240132000, 0.0407100000, 0.0865615000, 0.2145738000, 0.5754678000", \ - "0.0172652000, 0.0192238000, 0.0248831000, 0.0409399000, 0.0863485000, 0.2139689000, 0.5729066000", \ - "0.0240760000, 0.0261930000, 0.0318928000, 0.0474555000, 0.0888438000, 0.2147503000, 0.5727649000", \ - "0.0407659000, 0.0435051000, 0.0503794000, 0.0673020000, 0.1085902000, 0.2220793000, 0.5736686000", \ - "0.0743449000, 0.0779870000, 0.0874863000, 0.1102222000, 0.1586221000, 0.2717696000, 0.5898927000", \ - "0.1435612000, 0.1473932000, 0.1595765000, 0.1907152000, 0.2572209000, 0.3928072000, 0.7052717000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014051300, 0.0039487600, 0.0110970000, 0.0311854000, 0.0876387000, 0.2462870000"); - values("0.0703410000, 0.0752966000, 0.0894896000, 0.1299972000, 0.2449275000, 0.5680906000, 1.4792038000", \ - "0.0701911000, 0.0751392000, 0.0893792000, 0.1301414000, 0.2448019000, 0.5693997000, 1.4765222000", \ - "0.0699545000, 0.0749748000, 0.0894026000, 0.1298345000, 0.2448054000, 0.5683369000, 1.4798613000", \ - "0.0723609000, 0.0770328000, 0.0901374000, 0.1296235000, 0.2448622000, 0.5695763000, 1.4770085000", \ - "0.0975726000, 0.1026335000, 0.1151342000, 0.1467603000, 0.2486331000, 0.5686228000, 1.4821075000", \ - "0.1423159000, 0.1492630000, 0.1682669000, 0.2113231000, 0.3073917000, 0.5821174000, 1.4822439000", \ - "0.2158428000, 0.2265408000, 0.2543672000, 0.3194137000, 0.4568700000, 0.7216925000, 1.4976469000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311a_1") { - leakage_power () { - value : 0.0171749000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0120266000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033318000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0121072000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0039434000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0036972000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033588000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0037234000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033632000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033668000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0025488000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0022253000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033409000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0025262000; - when : "A1&A2&A3&B1&!C1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o311a"; - cell_leakage_power : 0.0037667360; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041950000, 0.0041928000, 0.0041878000, 0.0041879000, 0.0041881000, 0.0041886000, 0.0041897000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004187700, -0.004186900, -0.004184800, -0.004184800, -0.004184800, -0.004184900, -0.004185000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024810000; - } - pin ("A2") { - capacitance : 0.0023620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038752000, 0.0038748000, 0.0038738000, 0.0038745000, 0.0038761000, 0.0038797000, 0.0038881000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003867100, -0.003868100, -0.003870600, -0.003870700, -0.003871000, -0.003871700, -0.003873300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025200000; - } - pin ("A3") { - capacitance : 0.0023490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039477000, 0.0039476000, 0.0039474000, 0.0039478000, 0.0039488000, 0.0039511000, 0.0039562000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003957600, -0.003954800, -0.003948400, -0.003948700, -0.003949500, -0.003951400, -0.003955800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025290000; - } - pin ("B1") { - capacitance : 0.0023720000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042007000, 0.0041861000, 0.0041523000, 0.0041568000, 0.0041672000, 0.0041911000, 0.0042461000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004088700, -0.004084200, -0.004073700, -0.004072400, -0.004069600, -0.004062900, -0.004047700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024570000; - } - pin ("C1") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047708000, 0.0047768000, 0.0047905000, 0.0047907000, 0.0047912000, 0.0047925000, 0.0047952000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003948100, -0.003949600, -0.003953000, -0.003947500, -0.003934900, -0.003905800, -0.003838800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024230000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A3&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0174410000, 0.0165317000, 0.0142267000, 0.0069369000, -0.014786700, -0.074104200, -0.229389400", \ - "0.0173511000, 0.0164636000, 0.0140217000, 0.0067910000, -0.014903800, -0.074179600, -0.229445800", \ - "0.0172566000, 0.0163506000, 0.0139000000, 0.0065444000, -0.015125600, -0.074427100, -0.229670200", \ - "0.0169884000, 0.0161023000, 0.0136819000, 0.0063912000, -0.015317000, -0.074546000, -0.229836600", \ - "0.0168476000, 0.0159722000, 0.0135612000, 0.0062119000, -0.015442800, -0.074686000, -0.229902500", \ - "0.0168591000, 0.0159526000, 0.0134481000, 0.0061816000, -0.015480000, -0.074719800, -0.229940200", \ - "0.0209842000, 0.0196170000, 0.0161703000, 0.0072798000, -0.015681500, -0.074600200, -0.229785700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0166427000, 0.0180814000, 0.0216971000, 0.0306518000, 0.0534316000, 0.1125106000, 0.2659567000", \ - "0.0164948000, 0.0179466000, 0.0215874000, 0.0305533000, 0.0533528000, 0.1127797000, 0.2669766000", \ - "0.0163923000, 0.0178428000, 0.0214193000, 0.0304344000, 0.0531814000, 0.1127328000, 0.2669011000", \ - "0.0162057000, 0.0176533000, 0.0212581000, 0.0302471000, 0.0532146000, 0.1125582000, 0.2668144000", \ - "0.0161530000, 0.0175721000, 0.0211625000, 0.0301277000, 0.0529495000, 0.1124845000, 0.2666939000", \ - "0.0164333000, 0.0177716000, 0.0211993000, 0.0298846000, 0.0527805000, 0.1122358000, 0.2653416000", \ - "0.0168808000, 0.0181728000, 0.0215503000, 0.0303424000, 0.0532151000, 0.1124829000, 0.2662807000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0156406000, 0.0147114000, 0.0122911000, 0.0049450000, -0.016694500, -0.075909700, -0.231039000", \ - "0.0153929000, 0.0145252000, 0.0120648000, 0.0047696000, -0.016793800, -0.075992800, -0.231163900", \ - "0.0152280000, 0.0143699000, 0.0119502000, 0.0046285000, -0.016971800, -0.076136900, -0.231291600", \ - "0.0150671000, 0.0142079000, 0.0117758000, 0.0045198000, -0.017100100, -0.076256100, -0.231441700", \ - "0.0149386000, 0.0140696000, 0.0116528000, 0.0043176000, -0.017286800, -0.076398600, -0.231567700", \ - "0.0148595000, 0.0139225000, 0.0114968000, 0.0042342000, -0.017296300, -0.076440500, -0.231566000", \ - "0.0191529000, 0.0177890000, 0.0142570000, 0.0054501000, -0.017564100, -0.076257400, -0.231361000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0151894000, 0.0166063000, 0.0201738000, 0.0291714000, 0.0519866000, 0.1112467000, 0.2649902000", \ - "0.0151325000, 0.0165515000, 0.0201567000, 0.0291137000, 0.0519937000, 0.1116311000, 0.2660009000", \ - "0.0150762000, 0.0164750000, 0.0200522000, 0.0290285000, 0.0519500000, 0.1116396000, 0.2660429000", \ - "0.0148667000, 0.0162788000, 0.0198643000, 0.0288355000, 0.0516960000, 0.1110294000, 0.2656728000", \ - "0.0146220000, 0.0160590000, 0.0196242000, 0.0285633000, 0.0515837000, 0.1107131000, 0.2645907000", \ - "0.0147902000, 0.0161306000, 0.0195418000, 0.0282549000, 0.0511688000, 0.1100362000, 0.2642384000", \ - "0.0150653000, 0.0164178000, 0.0198038000, 0.0285612000, 0.0514437000, 0.1107640000, 0.2632408000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0133459000, 0.0124871000, 0.0100720000, 0.0027491000, -0.018721800, -0.077737300, -0.232807400", \ - "0.0132252000, 0.0123719000, 0.0099321000, 0.0026018000, -0.018938400, -0.077981300, -0.233001300", \ - "0.0130863000, 0.0121761000, 0.0097498000, 0.0024140000, -0.019112900, -0.078160500, -0.233200300", \ - "0.0128307000, 0.0119413000, 0.0094872000, 0.0022040000, -0.019324800, -0.078360300, -0.233392100", \ - "0.0127934000, 0.0119088000, 0.0095235000, 0.0021994000, -0.019308700, -0.078358500, -0.233392000", \ - "0.0133092000, 0.0123935000, 0.0098805000, 0.0025695000, -0.018964200, -0.078008400, -0.233037800", \ - "0.0180006000, 0.0166152000, 0.0131307000, 0.0042562000, -0.018722800, -0.077317400, -0.232390300"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0135631000, 0.0149616000, 0.0185135000, 0.0274954000, 0.0504939000, 0.1094735000, 0.2618689000", \ - "0.0135506000, 0.0149539000, 0.0185312000, 0.0274859000, 0.0505069000, 0.1095348000, 0.2637750000", \ - "0.0134352000, 0.0148288000, 0.0183882000, 0.0273683000, 0.0501315000, 0.1094155000, 0.2633369000", \ - "0.0131732000, 0.0145801000, 0.0181461000, 0.0270732000, 0.0499459000, 0.1093394000, 0.2643447000", \ - "0.0128809000, 0.0142741000, 0.0178343000, 0.0266960000, 0.0495214000, 0.1089745000, 0.2625084000", \ - "0.0129115000, 0.0142454000, 0.0176843000, 0.0264645000, 0.0493143000, 0.1080574000, 0.2622355000", \ - "0.0134230000, 0.0147633000, 0.0180401000, 0.0269202000, 0.0497715000, 0.1090249000, 0.2625772000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0128422000, 0.0122637000, 0.0102128000, 0.0035635000, -0.018112300, -0.077542600, -0.232755800", \ - "0.0127027000, 0.0121177000, 0.0100583000, 0.0033981000, -0.018277700, -0.077694200, -0.232910000", \ - "0.0125210000, 0.0118780000, 0.0098241000, 0.0031822000, -0.018486300, -0.077895000, -0.233111600", \ - "0.0122140000, 0.0115396000, 0.0094498000, 0.0028243000, -0.018825100, -0.078198800, -0.233387900", \ - "0.0118248000, 0.0112341000, 0.0090785000, 0.0024700000, -0.019069800, -0.078385300, -0.233536100", \ - "0.0156785000, 0.0144030000, 0.0110867000, 0.0024537000, -0.018559400, -0.077763300, -0.232864900", \ - "0.0182078000, 0.0168809000, 0.0134900000, 0.0047729000, -0.017938200, -0.077080500, -0.232038100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0166347000, 0.0180911000, 0.0216658000, 0.0306991000, 0.0535199000, 0.1130325000, 0.2672650000", \ - "0.0165664000, 0.0180014000, 0.0216413000, 0.0306144000, 0.0534969000, 0.1125296000, 0.2663484000", \ - "0.0164138000, 0.0178630000, 0.0214425000, 0.0304661000, 0.0532589000, 0.1129356000, 0.2672213000", \ - "0.0162014000, 0.0176391000, 0.0212600000, 0.0302507000, 0.0531000000, 0.1123357000, 0.2660962000", \ - "0.0160897000, 0.0175426000, 0.0211001000, 0.0300969000, 0.0529147000, 0.1121968000, 0.2659724000", \ - "0.0165483000, 0.0178506000, 0.0212433000, 0.0298706000, 0.0528817000, 0.1122716000, 0.2669984000", \ - "0.0173747000, 0.0187114000, 0.0220419000, 0.0307319000, 0.0535391000, 0.1127738000, 0.2652338000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0101340000, 0.0095648000, 0.0074697000, 0.0006849000, -0.021113200, -0.080610300, -0.235882600", \ - "0.0099944000, 0.0093930000, 0.0072882000, 0.0005271000, -0.021280200, -0.080780700, -0.236052700", \ - "0.0096317000, 0.0090656000, 0.0069250000, 0.0001604000, -0.021621800, -0.081121800, -0.236391800", \ - "0.0092881000, 0.0086453000, 0.0064945000, -0.000248500, -0.021935800, -0.081382700, -0.236638000", \ - "0.0085387000, 0.0081070000, 0.0062922000, -0.000331100, -0.021966800, -0.081355700, -0.236575900", \ - "0.0132196000, 0.0119604000, 0.0086895000, 6.720000e-05, -0.021656100, -0.080903300, -0.236071600", \ - "0.0156999000, 0.0143727000, 0.0110326000, 0.0023086000, -0.020371800, -0.079671000, -0.234583100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013016660, 0.0033886710, 0.0088218360, 0.0229661800, 0.0597885900, 0.1556496000"); - values("0.0163824000, 0.0178202000, 0.0214398000, 0.0304023000, 0.0533079000, 0.1125050000, 0.2661485000", \ - "0.0162524000, 0.0176853000, 0.0213065000, 0.0303227000, 0.0532441000, 0.1128618000, 0.2672062000", \ - "0.0160923000, 0.0175435000, 0.0211211000, 0.0301487000, 0.0532095000, 0.1127031000, 0.2669868000", \ - "0.0159213000, 0.0173692000, 0.0209820000, 0.0299521000, 0.0528583000, 0.1124611000, 0.2667998000", \ - "0.0158049000, 0.0172399000, 0.0207755000, 0.0296842000, 0.0525800000, 0.1118507000, 0.2654433000", \ - "0.0167260000, 0.0180029000, 0.0214096000, 0.0300099000, 0.0528446000, 0.1118594000, 0.2659329000", \ - "0.0180157000, 0.0193100000, 0.0226598000, 0.0313442000, 0.0540220000, 0.1135555000, 0.2657846000"); - } - } - max_capacitance : 0.1556500000; - max_transition : 1.5115730000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.3033668000, 0.3126665000, 0.3310535000, 0.3656666000, 0.4297587000, 0.5586359000, 0.8581811000", \ - "0.3080605000, 0.3172799000, 0.3358851000, 0.3698862000, 0.4341433000, 0.5635460000, 0.8632332000", \ - "0.3200409000, 0.3293228000, 0.3478788000, 0.3825171000, 0.4468048000, 0.5760556000, 0.8757533000", \ - "0.3464831000, 0.3558512000, 0.3744629000, 0.4090631000, 0.4731930000, 0.6016491000, 0.9013736000", \ - "0.4035725000, 0.4127948000, 0.4315295000, 0.4660203000, 0.5299749000, 0.6591722000, 0.9589477000", \ - "0.5237309000, 0.5333345000, 0.5521618000, 0.5871476000, 0.6522016000, 0.7809519000, 1.0804863000", \ - "0.7418197000, 0.7526328000, 0.7742203000, 0.8130432000, 0.8833815000, 1.0192228000, 1.3218171000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1248290000, 0.1333937000, 0.1520701000, 0.1930714000, 0.2905228000, 0.5384908000, 1.1819393000", \ - "0.1290144000, 0.1376329000, 0.1564206000, 0.1974049000, 0.2948542000, 0.5438190000, 1.1886713000", \ - "0.1376253000, 0.1461955000, 0.1648853000, 0.2059534000, 0.3031673000, 0.5516201000, 1.1979705000", \ - "0.1540801000, 0.1626027000, 0.1812993000, 0.2223086000, 0.3196982000, 0.5690312000, 1.2145434000", \ - "0.1850378000, 0.1938441000, 0.2129393000, 0.2542002000, 0.3518581000, 0.6010998000, 1.2461771000", \ - "0.2302090000, 0.2397625000, 0.2601306000, 0.3028888000, 0.4011943000, 0.6499326000, 1.2952556000", \ - "0.2688115000, 0.2809211000, 0.3045523000, 0.3511408000, 0.4510803000, 0.7010687000, 1.3440418000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0384895000, 0.0441822000, 0.0565671000, 0.0826804000, 0.1388119000, 0.2761447000, 0.6509936000", \ - "0.0389933000, 0.0443527000, 0.0560793000, 0.0830628000, 0.1385787000, 0.2772553000, 0.6520279000", \ - "0.0385406000, 0.0441881000, 0.0560088000, 0.0815569000, 0.1388524000, 0.2763496000, 0.6533811000", \ - "0.0384930000, 0.0441256000, 0.0563276000, 0.0825552000, 0.1391298000, 0.2771871000, 0.6533357000", \ - "0.0383627000, 0.0441043000, 0.0566626000, 0.0813658000, 0.1392221000, 0.2766287000, 0.6500150000", \ - "0.0407873000, 0.0462402000, 0.0579911000, 0.0835285000, 0.1398973000, 0.2765249000, 0.6521010000", \ - "0.0480897000, 0.0541332000, 0.0666196000, 0.0932020000, 0.1518174000, 0.2869070000, 0.6564320000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0295483000, 0.0373351000, 0.0561140000, 0.1050040000, 0.2361855000, 0.5864564000, 1.4975642000", \ - "0.0297567000, 0.0373206000, 0.0561875000, 0.1052030000, 0.2369023000, 0.5875531000, 1.5035752000", \ - "0.0296214000, 0.0372107000, 0.0561790000, 0.1050905000, 0.2368659000, 0.5873904000, 1.5026866000", \ - "0.0294116000, 0.0371236000, 0.0561203000, 0.1048572000, 0.2365628000, 0.5873658000, 1.5006760000", \ - "0.0310454000, 0.0385495000, 0.0573748000, 0.1055584000, 0.2368851000, 0.5877605000, 1.5035693000", \ - "0.0352189000, 0.0432391000, 0.0614312000, 0.1084861000, 0.2376347000, 0.5863942000, 1.5029764000", \ - "0.0455336000, 0.0538048000, 0.0725256000, 0.1164496000, 0.2407737000, 0.5882985000, 1.4988876000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.2860614000, 0.2952884000, 0.3137965000, 0.3485406000, 0.4126991000, 0.5416028000, 0.8413690000", \ - "0.2897128000, 0.2991150000, 0.3176211000, 0.3522696000, 0.4156434000, 0.5455634000, 0.8455628000", \ - "0.3005086000, 0.3099055000, 0.3284747000, 0.3631853000, 0.4275952000, 0.5560480000, 0.8559428000", \ - "0.3270768000, 0.3364674000, 0.3550932000, 0.3893789000, 0.4540039000, 0.5830503000, 0.8830062000", \ - "0.3878888000, 0.3971186000, 0.4158117000, 0.4503821000, 0.5145944000, 0.6440301000, 0.9440061000", \ - "0.5238441000, 0.5335001000, 0.5525431000, 0.5876893000, 0.6521992000, 0.7821167000, 1.0821005000", \ - "0.7743877000, 0.7857422000, 0.8081824000, 0.8480571000, 0.9190991000, 1.0548350000, 1.3580735000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1199171000, 0.1282736000, 0.1466046000, 0.1872323000, 0.2842167000, 0.5328156000, 1.1761783000", \ - "0.1245095000, 0.1329182000, 0.1513571000, 0.1918342000, 0.2890911000, 0.5382097000, 1.1844735000", \ - "0.1333797000, 0.1417257000, 0.1601569000, 0.2007173000, 0.2979945000, 0.5474813000, 1.1909009000", \ - "0.1496442000, 0.1580100000, 0.1764125000, 0.2169746000, 0.3140176000, 0.5622716000, 1.2082619000", \ - "0.1790399000, 0.1878199000, 0.2067364000, 0.2476907000, 0.3449978000, 0.5939033000, 1.2376168000", \ - "0.2199352000, 0.2297584000, 0.2500732000, 0.2926935000, 0.3908540000, 0.6395116000, 1.2836493000", \ - "0.2473127000, 0.2599244000, 0.2847760000, 0.3315264000, 0.4315328000, 0.6803865000, 1.3243109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0389040000, 0.0445141000, 0.0563192000, 0.0816872000, 0.1387004000, 0.2765994000, 0.6509225000", \ - "0.0385062000, 0.0441134000, 0.0560640000, 0.0824942000, 0.1394451000, 0.2762712000, 0.6554808000", \ - "0.0385507000, 0.0440524000, 0.0561790000, 0.0812356000, 0.1387730000, 0.2766408000, 0.6548040000", \ - "0.0385437000, 0.0443246000, 0.0560471000, 0.0828368000, 0.1387585000, 0.2761642000, 0.6520389000", \ - "0.0383671000, 0.0441031000, 0.0565098000, 0.0813470000, 0.1390491000, 0.2763166000, 0.6512978000", \ - "0.0412831000, 0.0467163000, 0.0586608000, 0.0839467000, 0.1399729000, 0.2768038000, 0.6546373000", \ - "0.0520589000, 0.0575257000, 0.0700922000, 0.0960917000, 0.1505401000, 0.2860622000, 0.6552399000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0283792000, 0.0360365000, 0.0547816000, 0.1031916000, 0.2351978000, 0.5850859000, 1.5028422000", \ - "0.0285338000, 0.0360066000, 0.0548258000, 0.1032955000, 0.2346258000, 0.5871074000, 1.5026209000", \ - "0.0284201000, 0.0360711000, 0.0547646000, 0.1034855000, 0.2352455000, 0.5867694000, 1.5024673000", \ - "0.0282767000, 0.0360596000, 0.0547070000, 0.1033982000, 0.2351966000, 0.5867418000, 1.5042152000", \ - "0.0301852000, 0.0378016000, 0.0563645000, 0.1041123000, 0.2351334000, 0.5862426000, 1.4987639000", \ - "0.0349562000, 0.0427936000, 0.0611636000, 0.1076555000, 0.2367299000, 0.5854266000, 1.4980627000", \ - "0.0465551000, 0.0551923000, 0.0735927000, 0.1176051000, 0.2396746000, 0.5872722000, 1.4973665000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.2492122000, 0.2585054000, 0.2771511000, 0.3118603000, 0.3757068000, 0.5056902000, 0.8057820000", \ - "0.2516818000, 0.2610108000, 0.2796005000, 0.3142289000, 0.3789001000, 0.5086666000, 0.8087863000", \ - "0.2604466000, 0.2697802000, 0.2882884000, 0.3230538000, 0.3875241000, 0.5172520000, 0.8173793000", \ - "0.2849156000, 0.2941665000, 0.3126994000, 0.3470302000, 0.4118101000, 0.5416520000, 0.8415007000", \ - "0.3480846000, 0.3574050000, 0.3760502000, 0.4107114000, 0.4753314000, 0.6050681000, 0.9049692000", \ - "0.4979355000, 0.5075252000, 0.5266734000, 0.5614986000, 0.6260640000, 0.7561109000, 1.0562253000", \ - "0.7579953000, 0.7703355000, 0.7940965000, 0.8351793000, 0.9043210000, 1.0350585000, 1.3381669000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1019757000, 0.1098905000, 0.1276287000, 0.1674505000, 0.2639227000, 0.5112427000, 1.1583345000", \ - "0.1067858000, 0.1147407000, 0.1325050000, 0.1722211000, 0.2687658000, 0.5160737000, 1.1646683000", \ - "0.1157893000, 0.1237018000, 0.1414453000, 0.1812425000, 0.2777762000, 0.5258621000, 1.1705287000", \ - "0.1326364000, 0.1406306000, 0.1583972000, 0.1979854000, 0.2946036000, 0.5437187000, 1.1930774000", \ - "0.1608033000, 0.1692965000, 0.1878330000, 0.2282578000, 0.3251505000, 0.5743349000, 1.2169978000", \ - "0.1948492000, 0.2047983000, 0.2252117000, 0.2677494000, 0.3653176000, 0.6134031000, 1.2592162000", \ - "0.2073821000, 0.2207384000, 0.2466191000, 0.2948736000, 0.3948997000, 0.6442091000, 1.2871022000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0384465000, 0.0441434000, 0.0560462000, 0.0815453000, 0.1385329000, 0.2771599000, 0.6508450000", \ - "0.0383865000, 0.0441626000, 0.0559873000, 0.0814381000, 0.1386251000, 0.2761675000, 0.6525369000", \ - "0.0387236000, 0.0442235000, 0.0561075000, 0.0816088000, 0.1385561000, 0.2758727000, 0.6528377000", \ - "0.0392536000, 0.0445518000, 0.0561540000, 0.0828028000, 0.1388920000, 0.2757902000, 0.6524294000", \ - "0.0384509000, 0.0440249000, 0.0569287000, 0.0813895000, 0.1380825000, 0.2762930000, 0.6520466000", \ - "0.0417703000, 0.0468875000, 0.0584248000, 0.0826482000, 0.1395330000, 0.2766055000, 0.6540292000", \ - "0.0580108000, 0.0643547000, 0.0765471000, 0.0986658000, 0.1503563000, 0.2865885000, 0.6569015000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0266341000, 0.0341392000, 0.0526994000, 0.1013543000, 0.2337325000, 0.5862436000, 1.5008638000", \ - "0.0266328000, 0.0339603000, 0.0525823000, 0.1015277000, 0.2341251000, 0.5854398000, 1.5055076000", \ - "0.0266265000, 0.0341038000, 0.0527105000, 0.1013235000, 0.2338866000, 0.5863699000, 1.5008460000", \ - "0.0267592000, 0.0342706000, 0.0528350000, 0.1016053000, 0.2340505000, 0.5867588000, 1.5115731000", \ - "0.0294684000, 0.0367828000, 0.0551059000, 0.1028150000, 0.2344808000, 0.5865284000, 1.4974607000", \ - "0.0356902000, 0.0432262000, 0.0615427000, 0.1071639000, 0.2357279000, 0.5841623000, 1.5002386000", \ - "0.0495838000, 0.0586792000, 0.0764588000, 0.1191820000, 0.2397693000, 0.5883110000, 1.4967758000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0875346000, 0.0932319000, 0.1053274000, 0.1308936000, 0.1860170000, 0.3069027000, 0.6021049000", \ - "0.0928611000, 0.0986061000, 0.1106657000, 0.1363284000, 0.1914601000, 0.3123508000, 0.6074959000", \ - "0.1061081000, 0.1117382000, 0.1238879000, 0.1495814000, 0.2047224000, 0.3256163000, 0.6207854000", \ - "0.1381929000, 0.1438004000, 0.1559786000, 0.1816360000, 0.2368867000, 0.3578087000, 0.6528081000", \ - "0.2064908000, 0.2127813000, 0.2258491000, 0.2525562000, 0.3085238000, 0.4300146000, 0.7252509000", \ - "0.3186920000, 0.3268471000, 0.3434330000, 0.3756095000, 0.4381508000, 0.5643984000, 0.8598197000", \ - "0.4993533000, 0.5100207000, 0.5317488000, 0.5728224000, 0.6497667000, 0.7899607000, 1.0897735000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1170088000, 0.1256133000, 0.1443092000, 0.1854260000, 0.2829341000, 0.5326698000, 1.1781484000", \ - "0.1210720000, 0.1296837000, 0.1483706000, 0.1893710000, 0.2871199000, 0.5359830000, 1.1798945000", \ - "0.1298359000, 0.1383936000, 0.1570820000, 0.1981800000, 0.2956342000, 0.5444848000, 1.1912533000", \ - "0.1502896000, 0.1588089000, 0.1774710000, 0.2183602000, 0.3161326000, 0.5646789000, 1.2082588000", \ - "0.1904325000, 0.1992560000, 0.2183469000, 0.2596786000, 0.3573478000, 0.6057668000, 1.2496089000", \ - "0.2465017000, 0.2561578000, 0.2763307000, 0.3187370000, 0.4170966000, 0.6661425000, 1.3114441000", \ - "0.2972891000, 0.3094338000, 0.3335260000, 0.3782265000, 0.4775279000, 0.7267733000, 1.3717024000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0182503000, 0.0228491000, 0.0336349000, 0.0591221000, 0.1184874000, 0.2595863000, 0.6443912000", \ - "0.0183447000, 0.0228810000, 0.0337148000, 0.0590899000, 0.1184220000, 0.2596417000, 0.6442802000", \ - "0.0184065000, 0.0228291000, 0.0336341000, 0.0590757000, 0.1184383000, 0.2596345000, 0.6444170000", \ - "0.0184607000, 0.0229082000, 0.0337374000, 0.0592137000, 0.1183787000, 0.2592998000, 0.6425085000", \ - "0.0222568000, 0.0265662000, 0.0369146000, 0.0614551000, 0.1195957000, 0.2599958000, 0.6444305000", \ - "0.0314206000, 0.0365088000, 0.0483397000, 0.0741565000, 0.1316208000, 0.2659258000, 0.6444110000", \ - "0.0456223000, 0.0530035000, 0.0665638000, 0.0974059000, 0.1590297000, 0.2867378000, 0.6451873000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0296398000, 0.0372066000, 0.0562845000, 0.1049847000, 0.2363656000, 0.5862829000, 1.5012155000", \ - "0.0295191000, 0.0373300000, 0.0562642000, 0.1048914000, 0.2366189000, 0.5875849000, 1.5011365000", \ - "0.0295642000, 0.0371592000, 0.0561627000, 0.1050317000, 0.2367303000, 0.5871133000, 1.5017229000", \ - "0.0292391000, 0.0369738000, 0.0559725000, 0.1047627000, 0.2360063000, 0.5866638000, 1.4989772000", \ - "0.0311679000, 0.0386421000, 0.0573632000, 0.1054284000, 0.2363801000, 0.5866345000, 1.4997430000", \ - "0.0361084000, 0.0432175000, 0.0612433000, 0.1079644000, 0.2377432000, 0.5870247000, 1.5039979000", \ - "0.0470471000, 0.0547387000, 0.0718209000, 0.1158944000, 0.2401022000, 0.5901120000, 1.4971403000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0730925000, 0.0784688000, 0.0902475000, 0.1151463000, 0.1695220000, 0.2900577000, 0.5851339000", \ - "0.0783463000, 0.0837343000, 0.0954866000, 0.1203541000, 0.1747382000, 0.2952447000, 0.5903529000", \ - "0.0910073000, 0.0963828000, 0.1080731000, 0.1330033000, 0.1876016000, 0.3081408000, 0.6032586000", \ - "0.1220841000, 0.1274156000, 0.1391447000, 0.1641340000, 0.2184328000, 0.3391930000, 0.6343354000", \ - "0.1799570000, 0.1863467000, 0.1991933000, 0.2262611000, 0.2824457000, 0.4039757000, 0.6991041000", \ - "0.2695306000, 0.2778430000, 0.2948581000, 0.3275818000, 0.3908783000, 0.5181036000, 0.8136585000", \ - "0.4103265000, 0.4211408000, 0.4429127000, 0.4848775000, 0.5631188000, 0.7040146000, 1.0043273000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.1098970000, 0.1184532000, 0.1371473000, 0.1782432000, 0.2760287000, 0.5244052000, 1.1691147000", \ - "0.1135001000, 0.1220788000, 0.1408675000, 0.1819738000, 0.2797615000, 0.5293979000, 1.1747305000", \ - "0.1229329000, 0.1315166000, 0.1502108000, 0.1913651000, 0.2890330000, 0.5391007000, 1.1849542000", \ - "0.1463734000, 0.1548712000, 0.1735020000, 0.2144002000, 0.3121959000, 0.5618342000, 1.2072162000", \ - "0.1915912000, 0.2002430000, 0.2191368000, 0.2602665000, 0.3578312000, 0.6069177000, 1.2516586000", \ - "0.2501844000, 0.2592205000, 0.2790824000, 0.3211118000, 0.4191947000, 0.6688921000, 1.3134865000", \ - "0.3075609000, 0.3197078000, 0.3428018000, 0.3877597000, 0.4857558000, 0.7358587000, 1.3809728000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0168342000, 0.0214210000, 0.0320399000, 0.0576326000, 0.1173624000, 0.2590226000, 0.6440675000", \ - "0.0169631000, 0.0213573000, 0.0320886000, 0.0576807000, 0.1173512000, 0.2591961000, 0.6440753000", \ - "0.0169240000, 0.0214007000, 0.0320302000, 0.0576692000, 0.1173340000, 0.2589390000, 0.6440664000", \ - "0.0172043000, 0.0217152000, 0.0323670000, 0.0578088000, 0.1175245000, 0.2590547000, 0.6440006000", \ - "0.0225718000, 0.0270803000, 0.0378776000, 0.0624290000, 0.1202028000, 0.2600977000, 0.6471083000", \ - "0.0317432000, 0.0371920000, 0.0494955000, 0.0756071000, 0.1338423000, 0.2676109000, 0.6443787000", \ - "0.0456161000, 0.0525012000, 0.0678612000, 0.0989769000, 0.1621339000, 0.2904285000, 0.6458698000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013016700, 0.0033886700, 0.0088218400, 0.0229662000, 0.0597886000, 0.1556500000"); - values("0.0295130000, 0.0372842000, 0.0561299000, 0.1050550000, 0.2364847000, 0.5856056000, 1.4982576000", \ - "0.0294264000, 0.0373335000, 0.0561926000, 0.1048303000, 0.2368231000, 0.5878590000, 1.5035992000", \ - "0.0296124000, 0.0371765000, 0.0561954000, 0.1049796000, 0.2365487000, 0.5868158000, 1.5005591000", \ - "0.0292653000, 0.0369158000, 0.0558943000, 0.1049501000, 0.2368543000, 0.5875471000, 1.5036123000", \ - "0.0306010000, 0.0382733000, 0.0571426000, 0.1055913000, 0.2367201000, 0.5869419000, 1.5016048000", \ - "0.0362398000, 0.0435824000, 0.0608586000, 0.1076722000, 0.2380949000, 0.5870097000, 1.5038280000", \ - "0.0482646000, 0.0554498000, 0.0731865000, 0.1143766000, 0.2396604000, 0.5895425000, 1.5003566000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311a_2") { - leakage_power () { - value : 0.0023719000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0154414000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0035489000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0155231000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0043656000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0041188000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0038079000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0041156000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0038091000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0038130000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0027303000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0024030000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0037908000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0027066000; - when : "A1&A2&A3&B1&!C1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o311a"; - cell_leakage_power : 0.0037370320; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041943000, 0.0041903000, 0.0041813000, 0.0041780000, 0.0041703000, 0.0041525000, 0.0041116000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004182800, -0.004182700, -0.004182500, -0.004181500, -0.004179400, -0.004174300, -0.004162700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024780000; - } - pin ("A2") { - capacitance : 0.0023580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038651000, 0.0038664000, 0.0038693000, 0.0038698000, 0.0038710000, 0.0038737000, 0.0038800000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003865400, -0.003866300, -0.003868200, -0.003868700, -0.003870000, -0.003872900, -0.003879500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025160000; - } - pin ("A3") { - capacitance : 0.0023420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039508000, 0.0039496000, 0.0039469000, 0.0039451000, 0.0039410000, 0.0039316000, 0.0039099000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003941200, -0.003942200, -0.003944200, -0.003942800, -0.003939300, -0.003931500, -0.003913300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025230000; - } - pin ("B1") { - capacitance : 0.0023600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042021000, 0.0041869000, 0.0041518000, 0.0041573000, 0.0041699000, 0.0041989000, 0.0042660000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004082900, -0.004079100, -0.004070200, -0.004069800, -0.004068900, -0.004066700, -0.004061600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024510000; - } - pin ("C1") { - capacitance : 0.0023440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047923000, 0.0047891000, 0.0047820000, 0.0047825000, 0.0047839000, 0.0047869000, 0.0047938000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003944500, -0.003946600, -0.003951600, -0.003946200, -0.003933600, -0.003904600, -0.003837800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024020000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A3&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0211705000, 0.0196300000, 0.0158763000, 0.0048644000, -0.029798900, -0.136149100, -0.447524300", \ - "0.0209992000, 0.0194864000, 0.0157424000, 0.0047214000, -0.029917200, -0.136273600, -0.447640300", \ - "0.0207465000, 0.0191835000, 0.0154778000, 0.0045284000, -0.030121800, -0.136339600, -0.447765200", \ - "0.0205637000, 0.0190375000, 0.0153179000, 0.0044225000, -0.030228200, -0.136554000, -0.447931400", \ - "0.0204662000, 0.0189294000, 0.0151382000, 0.0042483000, -0.030437000, -0.136736800, -0.448030900", \ - "0.0204947000, 0.0189472000, 0.0151620000, 0.0042481000, -0.030470200, -0.136775900, -0.448080500", \ - "0.0255196000, 0.0238013000, 0.0190599000, 0.0063508000, -0.030858200, -0.136714400, -0.447934000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0215378000, 0.0231684000, 0.0279373000, 0.0412126000, 0.0784585000, 0.1857299000, 0.4953611000", \ - "0.0214693000, 0.0230863000, 0.0278716000, 0.0411025000, 0.0782985000, 0.1848480000, 0.4950789000", \ - "0.0213462000, 0.0229735000, 0.0277399000, 0.0409669000, 0.0781454000, 0.1849208000, 0.4927831000", \ - "0.0211214000, 0.0227757000, 0.0275352000, 0.0408485000, 0.0780025000, 0.1848299000, 0.4926942000", \ - "0.0210639000, 0.0227039000, 0.0273514000, 0.0406515000, 0.0778546000, 0.1852924000, 0.4949798000", \ - "0.0219366000, 0.0234796000, 0.0279812000, 0.0405233000, 0.0777574000, 0.1848872000, 0.4924999000", \ - "0.0222760000, 0.0237516000, 0.0281873000, 0.0410165000, 0.0781353000, 0.1852134000, 0.4914944000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0190359000, 0.0175020000, 0.0138078000, 0.0028490000, -0.031609300, -0.137908400, -0.449120900", \ - "0.0189436000, 0.0174178000, 0.0137021000, 0.0029454000, -0.031738700, -0.138071400, -0.449252300", \ - "0.0188465000, 0.0173391000, 0.0135856000, 0.0025888000, -0.031889800, -0.138158300, -0.449374100", \ - "0.0186734000, 0.0171607000, 0.0134062000, 0.0024199000, -0.032180400, -0.138328300, -0.449537600", \ - "0.0185698000, 0.0170463000, 0.0133008000, 0.0023656000, -0.032295300, -0.138510700, -0.449708900", \ - "0.0189157000, 0.0173746000, 0.0132051000, 0.0025436000, -0.032269500, -0.138509300, -0.449732700", \ - "0.0235693000, 0.0218178000, 0.0178097000, 0.0039983000, -0.032670600, -0.138528700, -0.449621900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0200343000, 0.0216644000, 0.0263917000, 0.0397176000, 0.0769791000, 0.1836231000, 0.4944480000", \ - "0.0200521000, 0.0216902000, 0.0264404000, 0.0396804000, 0.0769704000, 0.1839908000, 0.4922547000", \ - "0.0199844000, 0.0216236000, 0.0263717000, 0.0396128000, 0.0768969000, 0.1839114000, 0.4918204000", \ - "0.0197626000, 0.0213918000, 0.0261626000, 0.0394871000, 0.0767605000, 0.1836138000, 0.4918074000", \ - "0.0196431000, 0.0212278000, 0.0259056000, 0.0392384000, 0.0764307000, 0.1843244000, 0.4938256000", \ - "0.0201922000, 0.0217328000, 0.0263357000, 0.0389733000, 0.0761375000, 0.1826317000, 0.4935458000", \ - "0.0205972000, 0.0220367000, 0.0265026000, 0.0393160000, 0.0765602000, 0.1833085000, 0.4893304000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0169589000, 0.0154399000, 0.0116864000, 0.0007559000, -0.033866300, -0.139966800, -0.451073400", \ - "0.0167836000, 0.0152510000, 0.0115033000, 0.0005546000, -0.034046000, -0.140115500, -0.451219000", \ - "0.0166319000, 0.0150885000, 0.0113306000, 0.0003672000, -0.034206700, -0.140274000, -0.451375200", \ - "0.0164631000, 0.0149372000, 0.0112150000, 0.0001968000, -0.034377000, -0.140441100, -0.451506300", \ - "0.0162522000, 0.0147602000, 0.0110110000, 0.0001810000, -0.034427900, -0.140481700, -0.451591800", \ - "0.0165454000, 0.0149393000, 0.0111576000, 0.0005708000, -0.034154600, -0.140223600, -0.451288100", \ - "0.0226988000, 0.0209458000, 0.0161264000, 0.0029314000, -0.033909400, -0.139719000, -0.450803700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0184025000, 0.0200262000, 0.0247664000, 0.0381055000, 0.0753638000, 0.1820083000, 0.4904333000", \ - "0.0184355000, 0.0201083000, 0.0248735000, 0.0381756000, 0.0752230000, 0.1822884000, 0.4906395000", \ - "0.0183789000, 0.0200545000, 0.0248130000, 0.0380182000, 0.0752820000, 0.1822180000, 0.4910718000", \ - "0.0181686000, 0.0198068000, 0.0245603000, 0.0378818000, 0.0751210000, 0.1820971000, 0.4903638000", \ - "0.0179560000, 0.0195706000, 0.0242485000, 0.0373874000, 0.0746399000, 0.1815038000, 0.4905074000", \ - "0.0183828000, 0.0199291000, 0.0244579000, 0.0372505000, 0.0742853000, 0.1805388000, 0.4902193000", \ - "0.0189017000, 0.0203919000, 0.0248031000, 0.0378095000, 0.0744904000, 0.1815961000, 0.4904712000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0160191000, 0.0149862000, 0.0120856000, 0.0019903000, -0.032360300, -0.139356300, -0.450789900", \ - "0.0159007000, 0.0148253000, 0.0119315000, 0.0018695000, -0.032492700, -0.139469000, -0.450898100", \ - "0.0158207000, 0.0147070000, 0.0117515000, 0.0017419000, -0.032658500, -0.139617600, -0.451053200", \ - "0.0155049000, 0.0144074000, 0.0114153000, 0.0013616000, -0.033027400, -0.139931000, -0.451332600", \ - "0.0153871000, 0.0142035000, 0.0110670000, 0.0011067000, -0.033296500, -0.140103400, -0.451438700", \ - "0.0188770000, 0.0173311000, 0.0129223000, 1.780000e-05, -0.033364500, -0.140067000, -0.451317800", \ - "0.0235658000, 0.0218939000, 0.0172588000, 0.0043946000, -0.032497000, -0.139424300, -0.450417000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0215908000, 0.0232154000, 0.0279808000, 0.0412017000, 0.0784300000, 0.1853142000, 0.4932561000", \ - "0.0214786000, 0.0230919000, 0.0278450000, 0.0411773000, 0.0784301000, 0.1859512000, 0.4955326000", \ - "0.0213498000, 0.0229682000, 0.0277178000, 0.0410492000, 0.0783067000, 0.1858493000, 0.4954390000", \ - "0.0211414000, 0.0227621000, 0.0275450000, 0.0408440000, 0.0780498000, 0.1848383000, 0.4950113000", \ - "0.0212517000, 0.0228536000, 0.0275568000, 0.0405849000, 0.0776709000, 0.1846298000, 0.4946923000", \ - "0.0218960000, 0.0234252000, 0.0279210000, 0.0404162000, 0.0775288000, 0.1841136000, 0.4926867000", \ - "0.0228288000, 0.0243392000, 0.0286468000, 0.0415940000, 0.0786206000, 0.1854663000, 0.4919028000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0133993000, 0.0123301000, 0.0094661000, -0.000651200, -0.035262400, -0.142353100, -0.453870300", \ - "0.0132470000, 0.0122496000, 0.0093417000, -0.000806500, -0.035348400, -0.142467800, -0.453982100", \ - "0.0130113000, 0.0119323000, 0.0090149000, -0.001087100, -0.035667900, -0.142749000, -0.454265000", \ - "0.0127369000, 0.0116754000, 0.0086295000, -0.001468500, -0.036025600, -0.143037700, -0.454516100", \ - "0.0125629000, 0.0113619000, 0.0082460000, -0.001867300, -0.036336300, -0.143222000, -0.454625300", \ - "0.0171179000, 0.0156059000, 0.0112481000, -0.001504400, -0.036524400, -0.143129700, -0.454415500", \ - "0.0208955000, 0.0192446000, 0.0146583000, 0.0017830000, -0.035037600, -0.142051000, -0.453032900"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014471280, 0.0041883570, 0.0121221700, 0.0350846600, 0.1015440000, 0.2938942000"); - values("0.0212832000, 0.0229225000, 0.0276808000, 0.0409732000, 0.0782818000, 0.1857798000, 0.4955888000", \ - "0.0212472000, 0.0228628000, 0.0276365000, 0.0408628000, 0.0781003000, 0.1849131000, 0.4929739000", \ - "0.0210542000, 0.0226686000, 0.0274080000, 0.0407499000, 0.0780627000, 0.1855882000, 0.4953749000", \ - "0.0208314000, 0.0224642000, 0.0272299000, 0.0405589000, 0.0778151000, 0.1853675000, 0.4951552000", \ - "0.0208555000, 0.0224246000, 0.0271296000, 0.0401974000, 0.0774934000, 0.1841952000, 0.4946183000", \ - "0.0217088000, 0.0232306000, 0.0279325000, 0.0404396000, 0.0773671000, 0.1839062000, 0.4925746000", \ - "0.0235386000, 0.0250152000, 0.0293663000, 0.0422574000, 0.0788524000, 0.1856892000, 0.4921615000"); - } - } - max_capacitance : 0.2938940000; - max_transition : 1.5041320000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.3507666000, 0.3589440000, 0.3768486000, 0.4117410000, 0.4765811000, 0.6059159000, 0.9107580000", \ - "0.3554188000, 0.3635658000, 0.3816082000, 0.4164840000, 0.4813213000, 0.6106422000, 0.9154947000", \ - "0.3676614000, 0.3756109000, 0.3938945000, 0.4286889000, 0.4937628000, 0.6222899000, 0.9280636000", \ - "0.3944277000, 0.4026194000, 0.4206377000, 0.4556742000, 0.5205230000, 0.6489773000, 0.9548191000", \ - "0.4519926000, 0.4602171000, 0.4781811000, 0.5129258000, 0.5777578000, 0.7068484000, 1.0125850000", \ - "0.5761066000, 0.5842863000, 0.6024589000, 0.6369459000, 0.7019469000, 0.8316788000, 1.1374113000", \ - "0.8100519000, 0.8192295000, 0.8394460000, 0.8791374000, 0.9494490000, 1.0850059000, 1.3941583000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1402646000, 0.1472110000, 0.1633762000, 0.1995038000, 0.2861142000, 0.5237932000, 1.2048706000", \ - "0.1446660000, 0.1515999000, 0.1677481000, 0.2038443000, 0.2903530000, 0.5270414000, 1.2085027000", \ - "0.1530979000, 0.1600586000, 0.1762103000, 0.2122660000, 0.2988621000, 0.5358257000, 1.2168713000", \ - "0.1691518000, 0.1762055000, 0.1923292000, 0.2284619000, 0.3149387000, 0.5518537000, 1.2331154000", \ - "0.2014710000, 0.2085768000, 0.2251102000, 0.2613764000, 0.3482139000, 0.5861472000, 1.2674288000", \ - "0.2508861000, 0.2588127000, 0.2765219000, 0.3146995000, 0.4026809000, 0.6401491000, 1.3218474000", \ - "0.2995136000, 0.3092342000, 0.3307636000, 0.3727172000, 0.4646483000, 0.7031212000, 1.3832995000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0455245000, 0.0496282000, 0.0600786000, 0.0814309000, 0.1307443000, 0.2570120000, 0.6245868000", \ - "0.0452889000, 0.0498061000, 0.0599393000, 0.0814308000, 0.1317276000, 0.2570298000, 0.6248311000", \ - "0.0454646000, 0.0499848000, 0.0603585000, 0.0815198000, 0.1302432000, 0.2559762000, 0.6257099000", \ - "0.0454102000, 0.0503531000, 0.0602474000, 0.0814586000, 0.1317137000, 0.2573212000, 0.6250461000", \ - "0.0450930000, 0.0497917000, 0.0599995000, 0.0820937000, 0.1317238000, 0.2566534000, 0.6253721000", \ - "0.0460603000, 0.0506387000, 0.0603727000, 0.0820669000, 0.1310583000, 0.2565449000, 0.6250014000", \ - "0.0549296000, 0.0600386000, 0.0706582000, 0.0932512000, 0.1423786000, 0.2661542000, 0.6297833000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0285207000, 0.0340011000, 0.0479892000, 0.0854756000, 0.1955616000, 0.5283837000, 1.5002766000", \ - "0.0282884000, 0.0338830000, 0.0478471000, 0.0856291000, 0.1955709000, 0.5282503000, 1.5000687000", \ - "0.0282748000, 0.0338168000, 0.0479550000, 0.0855392000, 0.1959270000, 0.5280928000, 1.4987922000", \ - "0.0281283000, 0.0337827000, 0.0478497000, 0.0854722000, 0.1956854000, 0.5282437000, 1.4992988000", \ - "0.0294647000, 0.0350182000, 0.0488381000, 0.0861930000, 0.1957046000, 0.5284665000, 1.5004266000", \ - "0.0330400000, 0.0388320000, 0.0534681000, 0.0902826000, 0.1980864000, 0.5279034000, 1.4991457000", \ - "0.0432654000, 0.0500631000, 0.0643906000, 0.1004850000, 0.2029875000, 0.5302795000, 1.4965857000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.3327988000, 0.3408821000, 0.3591296000, 0.3939956000, 0.4584882000, 0.5876932000, 0.8934485000", \ - "0.3366531000, 0.3448455000, 0.3628652000, 0.3974252000, 0.4623442000, 0.5914310000, 0.8972484000", \ - "0.3478826000, 0.3560653000, 0.3740591000, 0.4088324000, 0.4733696000, 0.6025764000, 0.9083510000", \ - "0.3744450000, 0.3826008000, 0.4007262000, 0.4356330000, 0.5005412000, 0.6293904000, 0.9353455000", \ - "0.4354209000, 0.4434481000, 0.4615530000, 0.4965865000, 0.5613889000, 0.6907569000, 0.9962187000", \ - "0.5759657000, 0.5841694000, 0.6029997000, 0.6377270000, 0.7027093000, 0.8325967000, 1.1384628000", \ - "0.8443365000, 0.8539551000, 0.8755719000, 0.9148783000, 0.9858723000, 1.1219621000, 1.4316918000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1351151000, 0.1419392000, 0.1579461000, 0.1937365000, 0.2800199000, 0.5173179000, 1.1974364000", \ - "0.1399444000, 0.1467685000, 0.1627259000, 0.1984828000, 0.2846085000, 0.5210049000, 1.2012725000", \ - "0.1487841000, 0.1556098000, 0.1715791000, 0.2073260000, 0.2935031000, 0.5301657000, 1.2112638000", \ - "0.1650814000, 0.1719518000, 0.1878724000, 0.2236961000, 0.3098250000, 0.5466426000, 1.2273548000", \ - "0.1963137000, 0.2032874000, 0.2197557000, 0.2558849000, 0.3423931000, 0.5798192000, 1.2616027000", \ - "0.2426827000, 0.2505689000, 0.2683366000, 0.3066112000, 0.3944688000, 0.6314593000, 1.3140141000", \ - "0.2829091000, 0.2927781000, 0.3150328000, 0.3584409000, 0.4503092000, 0.6882347000, 1.3685444000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0453277000, 0.0497890000, 0.0601006000, 0.0814435000, 0.1316260000, 0.2569451000, 0.6260745000", \ - "0.0454156000, 0.0503501000, 0.0602590000, 0.0821913000, 0.1313038000, 0.2566664000, 0.6263977000", \ - "0.0453211000, 0.0502332000, 0.0598108000, 0.0814446000, 0.1315785000, 0.2569879000, 0.6261172000", \ - "0.0451535000, 0.0501545000, 0.0600809000, 0.0819925000, 0.1316118000, 0.2572582000, 0.6252978000", \ - "0.0453621000, 0.0496389000, 0.0598039000, 0.0824419000, 0.1315275000, 0.2565459000, 0.6251449000", \ - "0.0475209000, 0.0517579000, 0.0609944000, 0.0826628000, 0.1311840000, 0.2567206000, 0.6252492000", \ - "0.0580630000, 0.0627119000, 0.0746008000, 0.0952934000, 0.1461001000, 0.2658936000, 0.6280166000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0275358000, 0.0328364000, 0.0470741000, 0.0843416000, 0.1946201000, 0.5268591000, 1.5012618000", \ - "0.0274840000, 0.0329673000, 0.0470255000, 0.0845202000, 0.1943194000, 0.5273426000, 1.4985578000", \ - "0.0274823000, 0.0329653000, 0.0470658000, 0.0844993000, 0.1945771000, 0.5286850000, 1.5005963000", \ - "0.0274199000, 0.0330182000, 0.0469559000, 0.0845955000, 0.1947749000, 0.5266345000, 1.4959300000", \ - "0.0289639000, 0.0346001000, 0.0483916000, 0.0854656000, 0.1947908000, 0.5283380000, 1.5017858000", \ - "0.0333026000, 0.0388730000, 0.0536822000, 0.0900879000, 0.1974226000, 0.5277222000, 1.5007152000", \ - "0.0444907000, 0.0509918000, 0.0661755000, 0.1015301000, 0.2030608000, 0.5299358000, 1.4934823000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.2957902000, 0.3039596000, 0.3219280000, 0.3570003000, 0.4217986000, 0.5513401000, 0.8572160000", \ - "0.2984132000, 0.3066237000, 0.3245494000, 0.3594915000, 0.4244410000, 0.5538741000, 0.8598077000", \ - "0.3075083000, 0.3157390000, 0.3336500000, 0.3686033000, 0.4336083000, 0.5630630000, 0.8689724000", \ - "0.3318900000, 0.3400836000, 0.3580667000, 0.3927115000, 0.4572878000, 0.5870290000, 0.8930781000", \ - "0.3952510000, 0.4034585000, 0.4215523000, 0.4551458000, 0.5202156000, 0.6499647000, 0.9560392000", \ - "0.5463437000, 0.5544456000, 0.5723642000, 0.6073461000, 0.6722793000, 0.8020099000, 1.1080388000", \ - "0.8296088000, 0.8401736000, 0.8627771000, 0.9045152000, 0.9760285000, 1.1104689000, 1.4195685000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1161592000, 0.1226139000, 0.1379643000, 0.1726525000, 0.2578524000, 0.4943679000, 1.1751540000", \ - "0.1210801000, 0.1276242000, 0.1429171000, 0.1776466000, 0.2627416000, 0.4985481000, 1.1787880000", \ - "0.1303476000, 0.1368561000, 0.1521480000, 0.1868311000, 0.2719122000, 0.5078471000, 1.1872946000", \ - "0.1474212000, 0.1539497000, 0.1692714000, 0.2039377000, 0.2889960000, 0.5252086000, 1.2050972000", \ - "0.1784858000, 0.1853707000, 0.2012127000, 0.2366314000, 0.3221858000, 0.5583914000, 1.2417538000", \ - "0.2204266000, 0.2283714000, 0.2463675000, 0.2840477000, 0.3711470000, 0.6077049000, 1.2909418000", \ - "0.2485229000, 0.2589158000, 0.2817825000, 0.3264363000, 0.4178546000, 0.6544957000, 1.3343970000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0451791000, 0.0502311000, 0.0598659000, 0.0824151000, 0.1318181000, 0.2569043000, 0.6257183000", \ - "0.0450839000, 0.0497155000, 0.0600339000, 0.0820450000, 0.1319485000, 0.2568884000, 0.6256961000", \ - "0.0450536000, 0.0497648000, 0.0600610000, 0.0819177000, 0.1319076000, 0.2568842000, 0.6256758000", \ - "0.0451386000, 0.0498602000, 0.0610259000, 0.0814320000, 0.1315790000, 0.2562130000, 0.6263906000", \ - "0.0454245000, 0.0502749000, 0.0606093000, 0.0817427000, 0.1304039000, 0.2562710000, 0.6251096000", \ - "0.0457937000, 0.0505333000, 0.0605173000, 0.0823534000, 0.1303090000, 0.2562628000, 0.6250635000", \ - "0.0651051000, 0.0711206000, 0.0818451000, 0.1017932000, 0.1459599000, 0.2655672000, 0.6299683000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0257582000, 0.0310399000, 0.0449595000, 0.0820200000, 0.1926751000, 0.5267259000, 1.4998783000", \ - "0.0257772000, 0.0311481000, 0.0448165000, 0.0821648000, 0.1929571000, 0.5277054000, 1.4941198000", \ - "0.0258058000, 0.0311710000, 0.0448045000, 0.0822177000, 0.1928573000, 0.5285961000, 1.5030061000", \ - "0.0257030000, 0.0310596000, 0.0449039000, 0.0821498000, 0.1929962000, 0.5261840000, 1.4943150000", \ - "0.0276962000, 0.0333220000, 0.0472525000, 0.0836084000, 0.1928985000, 0.5276389000, 1.5041323000", \ - "0.0335979000, 0.0392978000, 0.0533580000, 0.0892816000, 0.1963920000, 0.5262802000, 1.4985905000", \ - "0.0471236000, 0.0538217000, 0.0684541000, 0.1034414000, 0.2029458000, 0.5275689000, 1.4908785000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1010767000, 0.1056326000, 0.1161592000, 0.1384995000, 0.1879238000, 0.3021733000, 0.5973197000", \ - "0.1063916000, 0.1109962000, 0.1215203000, 0.1438353000, 0.1932838000, 0.3075169000, 0.6027248000", \ - "0.1197886000, 0.1243180000, 0.1349181000, 0.1572957000, 0.2067164000, 0.3209729000, 0.6159914000", \ - "0.1519515000, 0.1565153000, 0.1670165000, 0.1894292000, 0.2388602000, 0.3531467000, 0.6481861000", \ - "0.2248133000, 0.2296468000, 0.2405289000, 0.2631801000, 0.3129964000, 0.4276361000, 0.7228457000", \ - "0.3492100000, 0.3555914000, 0.3697157000, 0.3981582000, 0.4540976000, 0.5739605000, 0.8697942000", \ - "0.5492904000, 0.5580001000, 0.5767311000, 0.6138059000, 0.6843182000, 0.8205480000, 1.1226441000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1326958000, 0.1396559000, 0.1558214000, 0.1918548000, 0.2785679000, 0.5159650000, 1.1963748000", \ - "0.1366765000, 0.1436168000, 0.1598116000, 0.1959380000, 0.2826401000, 0.5206132000, 1.2023513000", \ - "0.1454804000, 0.1524215000, 0.1686044000, 0.2047306000, 0.2914337000, 0.5294258000, 1.2110624000", \ - "0.1660563000, 0.1729686000, 0.1891230000, 0.2251794000, 0.3118469000, 0.5491724000, 1.2324477000", \ - "0.2092886000, 0.2163540000, 0.2328228000, 0.2691020000, 0.3556669000, 0.5929982000, 1.2765998000", \ - "0.2735715000, 0.2813610000, 0.2992964000, 0.3360880000, 0.4247023000, 0.6624830000, 1.3436711000", \ - "0.3389567000, 0.3490639000, 0.3710283000, 0.4138380000, 0.5039084000, 0.7422550000, 1.4232922000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0187194000, 0.0219561000, 0.0298988000, 0.0494516000, 0.0998738000, 0.2280583000, 0.6115193000", \ - "0.0187055000, 0.0218421000, 0.0298316000, 0.0494362000, 0.0999192000, 0.2282736000, 0.6095639000", \ - "0.0189004000, 0.0219615000, 0.0298671000, 0.0495431000, 0.0998559000, 0.2281580000, 0.6110275000", \ - "0.0189145000, 0.0220381000, 0.0299322000, 0.0495339000, 0.0998232000, 0.2281521000, 0.6108076000", \ - "0.0214648000, 0.0244403000, 0.0320160000, 0.0509700000, 0.1005187000, 0.2285275000, 0.6115303000", \ - "0.0318337000, 0.0355937000, 0.0437884000, 0.0639998000, 0.1122920000, 0.2347543000, 0.6092798000", \ - "0.0480634000, 0.0523356000, 0.0632315000, 0.0869278000, 0.1398782000, 0.2591009000, 0.6135323000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0282708000, 0.0338153000, 0.0479666000, 0.0855754000, 0.1959753000, 0.5291132000, 1.4968987000", \ - "0.0283256000, 0.0339994000, 0.0479580000, 0.0854215000, 0.1957742000, 0.5288888000, 1.5009248000", \ - "0.0282662000, 0.0340150000, 0.0479544000, 0.0854203000, 0.1957316000, 0.5287794000, 1.5008256000", \ - "0.0281999000, 0.0337922000, 0.0477864000, 0.0854096000, 0.1959227000, 0.5292503000, 1.5006005000", \ - "0.0296707000, 0.0351060000, 0.0487337000, 0.0864299000, 0.1960999000, 0.5291276000, 1.4991299000", \ - "0.0347530000, 0.0402146000, 0.0539951000, 0.0907274000, 0.1981825000, 0.5271940000, 1.4954736000", \ - "0.0462411000, 0.0530679000, 0.0665446000, 0.1004322000, 0.2025291000, 0.5312192000, 1.4972212000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0854720000, 0.0898553000, 0.0999396000, 0.1215277000, 0.1698766000, 0.2834691000, 0.5782345000", \ - "0.0907192000, 0.0950645000, 0.1051425000, 0.1267251000, 0.1751191000, 0.2887054000, 0.5835658000", \ - "0.1038084000, 0.1081113000, 0.1181060000, 0.1398555000, 0.1881624000, 0.3017776000, 0.5968042000", \ - "0.1349851000, 0.1393233000, 0.1492464000, 0.1709155000, 0.2193323000, 0.3330177000, 0.6278077000", \ - "0.1998292000, 0.2047122000, 0.2157493000, 0.2389656000, 0.2883630000, 0.4027285000, 0.6978835000", \ - "0.3033304000, 0.3097718000, 0.3240012000, 0.3524811000, 0.4092911000, 0.5299402000, 0.8253649000", \ - "0.4638125000, 0.4722566000, 0.4904585000, 0.5275222000, 0.5986904000, 0.7351545000, 1.0380738000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.1254863000, 0.1324402000, 0.1487097000, 0.1847219000, 0.2714807000, 0.5095543000, 1.1909488000", \ - "0.1294383000, 0.1364138000, 0.1525244000, 0.1886256000, 0.2753035000, 0.5124410000, 1.1942830000", \ - "0.1385587000, 0.1455018000, 0.1617828000, 0.1977968000, 0.2845801000, 0.5226593000, 1.2040744000", \ - "0.1617425000, 0.1687014000, 0.1848932000, 0.2209149000, 0.3076914000, 0.5457349000, 1.2273994000", \ - "0.2117061000, 0.2187646000, 0.2350518000, 0.2711880000, 0.3576534000, 0.5958689000, 1.2784306000", \ - "0.2811529000, 0.2890646000, 0.3063615000, 0.3438108000, 0.4320356000, 0.6698245000, 1.3517543000", \ - "0.3537411000, 0.3641379000, 0.3861935000, 0.4289624000, 0.5175439000, 0.7550482000, 1.4372548000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0170494000, 0.0202164000, 0.0278969000, 0.0475584000, 0.0981472000, 0.2272118000, 0.6084199000", \ - "0.0171609000, 0.0200656000, 0.0278478000, 0.0474315000, 0.0981886000, 0.2272994000, 0.6112476000", \ - "0.0171398000, 0.0200987000, 0.0278889000, 0.0474461000, 0.0981745000, 0.2272746000, 0.6111937000", \ - "0.0170492000, 0.0201259000, 0.0279884000, 0.0476374000, 0.0981885000, 0.2273146000, 0.6086747000", \ - "0.0217201000, 0.0249194000, 0.0324947000, 0.0508796000, 0.0998098000, 0.2278679000, 0.6113150000", \ - "0.0316041000, 0.0355326000, 0.0441147000, 0.0642342000, 0.1130716000, 0.2360468000, 0.6111286000", \ - "0.0471177000, 0.0519751000, 0.0638423000, 0.0877560000, 0.1414430000, 0.2622373000, 0.6144709000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014471300, 0.0041883600, 0.0121222000, 0.0350847000, 0.1015440000, 0.2938940000"); - values("0.0285196000, 0.0340067000, 0.0479892000, 0.0854679000, 0.1955242000, 0.5282364000, 1.5001750000", \ - "0.0282655000, 0.0338009000, 0.0479084000, 0.0855053000, 0.1957601000, 0.5272124000, 1.5003414000", \ - "0.0284901000, 0.0340238000, 0.0480239000, 0.0855167000, 0.1954606000, 0.5280330000, 1.5001472000", \ - "0.0281677000, 0.0336147000, 0.0478630000, 0.0854098000, 0.1955731000, 0.5281568000, 1.5005871000", \ - "0.0293570000, 0.0347051000, 0.0486466000, 0.0861914000, 0.1957010000, 0.5293593000, 1.5007701000", \ - "0.0361163000, 0.0412806000, 0.0554428000, 0.0903434000, 0.1981805000, 0.5288883000, 1.5013575000", \ - "0.0489379000, 0.0550817000, 0.0688859000, 0.1017178000, 0.2025965000, 0.5309536000, 1.4945905000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311a_4") { - leakage_power () { - value : 0.0042305000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0063875000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0060049000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0042296000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0046335000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0063961000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0134942000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047987000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0046336000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0063961000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0080309000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047987000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0046335000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0269774000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0058288000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047985000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0046336000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0063961000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0078960000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047974000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0046335000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0063961000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0058324000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047982000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0046336000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0063961000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0058204000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0047974000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0046335000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0269848000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0056983000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0047982000; - when : "A1&A2&A3&B1&!C1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__o311a"; - cell_leakage_power : 0.0070443310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079954000, 0.0079915000, 0.0079826000, 0.0079860000, 0.0079937000, 0.0080114000, 0.0080521000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007975700, -0.007974500, -0.007971800, -0.007971200, -0.007969600, -0.007965900, -0.007957700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046420000; - } - pin ("A2") { - capacitance : 0.0043240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079370000, 0.0079372000, 0.0079376000, 0.0079381000, 0.0079391000, 0.0079414000, 0.0079469000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007944900, -0.007942900, -0.007938200, -0.007933200, -0.007921700, -0.007895100, -0.007833800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046190000; - } - pin ("A3") { - capacitance : 0.0044440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040630000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080856000, 0.0080840000, 0.0080804000, 0.0080816000, 0.0080845000, 0.0080911000, 0.0081066000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008078900, -0.008079100, -0.008079600, -0.008080700, -0.008083100, -0.008088700, -0.008101700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0048250000; - } - pin ("B1") { - capacitance : 0.0044550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082214000, 0.0081960000, 0.0081375000, 0.0081501000, 0.0081793000, 0.0082465000, 0.0084014000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008086400, -0.008083300, -0.008076000, -0.008078300, -0.008083700, -0.008095900, -0.008124000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046090000; - } - pin ("C1") { - capacitance : 0.0044320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093921000, 0.0093928000, 0.0093945000, 0.0093958000, 0.0093987000, 0.0094053000, 0.0094205000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006480800, -0.006489300, -0.006509000, -0.006490400, -0.006447500, -0.006348400, -0.006119900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045480000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1&C1) | (A2&B1&C1) | (A3&B1&C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0431901000, 0.0413906000, 0.0361618000, 0.0211278000, -0.031797700, -0.215102700, -0.814753100", \ - "0.0430990000, 0.0412901000, 0.0360665000, 0.0210422000, -0.031912900, -0.215556600, -0.815016800", \ - "0.0426335000, 0.0408190000, 0.0355825000, 0.0209339000, -0.032148700, -0.215727100, -0.815282100", \ - "0.0424093000, 0.0406067000, 0.0354197000, 0.0206426000, -0.032470000, -0.216058500, -0.815521700", \ - "0.0420836000, 0.0402837000, 0.0350582000, 0.0200431000, -0.032920000, -0.216391100, -0.815932300", \ - "0.0423443000, 0.0405231000, 0.0351784000, 0.0198660000, -0.033045700, -0.216744000, -0.816029200", \ - "0.0522606000, 0.0502256000, 0.0440763000, 0.0254492000, -0.033021200, -0.217155900, -0.816225000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0397439000, 0.0415889000, 0.0477405000, 0.0670243000, 0.1266607000, 0.3136850000, 0.9069807000", \ - "0.0395018000, 0.0413453000, 0.0474969000, 0.0668760000, 0.1265242000, 0.3134248000, 0.9063530000", \ - "0.0390661000, 0.0410094000, 0.0470492000, 0.0666657000, 0.1262020000, 0.3128788000, 0.9083615000", \ - "0.0388560000, 0.0407023000, 0.0467805000, 0.0662078000, 0.1259892000, 0.3127130000, 0.9098810000", \ - "0.0387578000, 0.0406172000, 0.0466936000, 0.0658440000, 0.1254386000, 0.3122724000, 0.9076989000", \ - "0.0400072000, 0.0418216000, 0.0476321000, 0.0655606000, 0.1249187000, 0.3116148000, 0.9070425000", \ - "0.0418477000, 0.0435878000, 0.0492851000, 0.0675022000, 0.1258189000, 0.3126928000, 0.9054875000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0384254000, 0.0365900000, 0.0313704000, 0.0164319000, -0.036158500, -0.219876900, -0.819493600", \ - "0.0381788000, 0.0363205000, 0.0311055000, 0.0161819000, -0.036526600, -0.220105800, -0.819749500", \ - "0.0380223000, 0.0362161000, 0.0310026000, 0.0160190000, -0.036961900, -0.220613900, -0.819988800", \ - "0.0376206000, 0.0357900000, 0.0305686000, 0.0155068000, -0.037299400, -0.220791000, -0.820319400", \ - "0.0373018000, 0.0354334000, 0.0302977000, 0.0153034000, -0.037692100, -0.221243100, -0.820695500", \ - "0.0372698000, 0.0354788000, 0.0301877000, 0.0150620000, -0.037579000, -0.221437300, -0.820767100", \ - "0.0474909000, 0.0453993000, 0.0392201000, 0.0205199000, -0.036652300, -0.220726800, -0.820271700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0366026000, 0.0384487000, 0.0445853000, 0.0636903000, 0.1231114000, 0.3095986000, 0.9064174000", \ - "0.0364555000, 0.0383540000, 0.0444877000, 0.0636532000, 0.1229543000, 0.3093045000, 0.9049127000", \ - "0.0363171000, 0.0382188000, 0.0443393000, 0.0635161000, 0.1228165000, 0.3091892000, 0.9048300000", \ - "0.0359493000, 0.0378219000, 0.0439178000, 0.0632283000, 0.1225422000, 0.3091364000, 0.9071912000", \ - "0.0355786000, 0.0375215000, 0.0435166000, 0.0626770000, 0.1217983000, 0.3085517000, 0.9067309000", \ - "0.0365096000, 0.0385275000, 0.0443165000, 0.0626977000, 0.1214650000, 0.3073151000, 0.9021891000", \ - "0.0382344000, 0.0399647000, 0.0456678000, 0.0639031000, 0.1223553000, 0.3082018000, 0.9025229000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0337390000, 0.0319330000, 0.0267816000, 0.0118229000, -0.041135400, -0.224772900, -0.824160400", \ - "0.0334217000, 0.0315951000, 0.0264774000, 0.0114132000, -0.041505900, -0.224829400, -0.824427400", \ - "0.0330969000, 0.0313307000, 0.0260901000, 0.0111401000, -0.041798900, -0.225166200, -0.824730800", \ - "0.0327924000, 0.0309631000, 0.0256911000, 0.0106746000, -0.042241100, -0.225815400, -0.825187500", \ - "0.0325155000, 0.0307175000, 0.0255083000, 0.0104642000, -0.042568500, -0.226068900, -0.825446500", \ - "0.0333810000, 0.0321833000, 0.0269146000, 0.0116346000, -0.040724300, -0.224856600, -0.824265900", \ - "0.0467215000, 0.0445311000, 0.0381337000, 0.0192495000, -0.039508900, -0.223182100, -0.822394800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0323477000, 0.0342710000, 0.0404289000, 0.0595681000, 0.1187930000, 0.3047761000, 0.9003512000", \ - "0.0323464000, 0.0342588000, 0.0404500000, 0.0597123000, 0.1189121000, 0.3049205000, 0.9000887000", \ - "0.0322363000, 0.0341395000, 0.0403334000, 0.0595932000, 0.1187307000, 0.3049559000, 0.8994342000", \ - "0.0317677000, 0.0337135000, 0.0398622000, 0.0591096000, 0.1183013000, 0.3043680000, 0.9002960000", \ - "0.0312824000, 0.0331896000, 0.0392857000, 0.0583829000, 0.1175154000, 0.3038415000, 0.8990285000", \ - "0.0323280000, 0.0341350000, 0.0399417000, 0.0583721000, 0.1169081000, 0.3024096000, 0.8982570000", \ - "0.0337080000, 0.0354154000, 0.0413449000, 0.0595961000, 0.1183100000, 0.3039846000, 0.8981092000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0315436000, 0.0303977000, 0.0265665000, 0.0130426000, -0.038707100, -0.224158500, -0.824560000", \ - "0.0313355000, 0.0301912000, 0.0263164000, 0.0127853000, -0.038832800, -0.224359400, -0.824762500", \ - "0.0311587000, 0.0298259000, 0.0259951000, 0.0123966000, -0.039269000, -0.224686500, -0.825084500", \ - "0.0305846000, 0.0292544000, 0.0253162000, 0.0117032000, -0.039950200, -0.225245400, -0.825573100", \ - "0.0299398000, 0.0285012000, 0.0243549000, 0.0105230000, -0.040986900, -0.225989100, -0.826170200", \ - "0.0367379000, 0.0349175000, 0.0292391000, 0.0113855000, -0.040600200, -0.225331800, -0.825458100", \ - "0.0465622000, 0.0445699000, 0.0385770000, 0.0201677000, -0.037906200, -0.224127100, -0.823630600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0399189000, 0.0418082000, 0.0478870000, 0.0673608000, 0.1270599000, 0.3139298000, 0.9088461000", \ - "0.0398719000, 0.0417198000, 0.0478731000, 0.0672607000, 0.1268882000, 0.3138765000, 0.9070005000", \ - "0.0396120000, 0.0414170000, 0.0476343000, 0.0669254000, 0.1265887000, 0.3136146000, 0.9083555000", \ - "0.0392106000, 0.0409962000, 0.0471083000, 0.0667150000, 0.1262870000, 0.3127011000, 0.9085472000", \ - "0.0393586000, 0.0412245000, 0.0473002000, 0.0666082000, 0.1255457000, 0.3125659000, 0.9068798000", \ - "0.0406511000, 0.0424213000, 0.0480911000, 0.0660330000, 0.1253670000, 0.3117098000, 0.9060354000", \ - "0.0428278000, 0.0445952000, 0.0504813000, 0.0689476000, 0.1269924000, 0.3134595000, 0.9062884000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0247030000, 0.0233506000, 0.0196143000, 0.0058955000, -0.046270400, -0.232093500, -0.832768200", \ - "0.0244646000, 0.0231124000, 0.0193465000, 0.0056599000, -0.046455300, -0.232295600, -0.832956800", \ - "0.0240205000, 0.0227546000, 0.0189862000, 0.0052291000, -0.046857800, -0.232669200, -0.833321100", \ - "0.0234988000, 0.0221702000, 0.0182104000, 0.0043545000, -0.047640200, -0.233257000, -0.833859000", \ - "0.0227492000, 0.0212422000, 0.0170779000, 0.0030831000, -0.048682500, -0.233992100, -0.834428400", \ - "0.0294656000, 0.0276285000, 0.0220045000, 0.0040910000, -0.048957400, -0.233778100, -0.834016500", \ - "0.0383808000, 0.0363799000, 0.0303893000, 0.0119117000, -0.046045800, -0.232344200, -0.832095900"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0382196000, 0.0401009000, 0.0461746000, 0.0657839000, 0.1253642000, 0.3121871000, 0.9074256000", \ - "0.0380358000, 0.0399793000, 0.0460134000, 0.0656410000, 0.1251517000, 0.3116585000, 0.9075179000", \ - "0.0377844000, 0.0396795000, 0.0458456000, 0.0652341000, 0.1249423000, 0.3117742000, 0.9068942000", \ - "0.0373379000, 0.0392747000, 0.0453934000, 0.0648506000, 0.1245291000, 0.3112424000, 0.9067197000", \ - "0.0374835000, 0.0393212000, 0.0453228000, 0.0643596000, 0.1238665000, 0.3106239000, 0.9090547000", \ - "0.0389567000, 0.0407480000, 0.0464468000, 0.0644504000, 0.1235683000, 0.3098368000, 0.9090590000", \ - "0.0415138000, 0.0432223000, 0.0487070000, 0.0671150000, 0.1251937000, 0.3116418000, 0.9062106000"); - } - } - max_capacitance : 0.5392550000; - max_transition : 1.5056430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.3333404000, 0.3388826000, 0.3529105000, 0.3836678000, 0.4456875000, 0.5763929000, 0.9109404000", \ - "0.3378158000, 0.3433509000, 0.3574535000, 0.3882563000, 0.4502037000, 0.5811913000, 0.9149993000", \ - "0.3499312000, 0.3554509000, 0.3695599000, 0.4001579000, 0.4621879000, 0.5933273000, 0.9272613000", \ - "0.3761318000, 0.3816767000, 0.3957416000, 0.4264668000, 0.4884742000, 0.6195282000, 0.9534556000", \ - "0.4296857000, 0.4352471000, 0.4492659000, 0.4800145000, 0.5417405000, 0.6730602000, 1.0073272000", \ - "0.5410503000, 0.5466760000, 0.5609787000, 0.5919724000, 0.6535457000, 0.7852876000, 1.1197604000", \ - "0.7419269000, 0.7481887000, 0.7641472000, 0.7985300000, 0.8660611000, 1.0043858000, 1.3429639000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1579149000, 0.1631929000, 0.1770062000, 0.2097093000, 0.2895874000, 0.5163012000, 1.2262622000", \ - "0.1621002000, 0.1673727000, 0.1812023000, 0.2138896000, 0.2937740000, 0.5204489000, 1.2306943000", \ - "0.1706391000, 0.1759037000, 0.1897435000, 0.2225573000, 0.3023506000, 0.5294076000, 1.2401404000", \ - "0.1872673000, 0.1925400000, 0.2063318000, 0.2390271000, 0.3188884000, 0.5453162000, 1.2568381000", \ - "0.2200451000, 0.2253907000, 0.2392461000, 0.2720441000, 0.3518438000, 0.5788683000, 1.2897348000", \ - "0.2736991000, 0.2794470000, 0.2943323000, 0.3288148000, 0.4100741000, 0.6369589000, 1.3485112000", \ - "0.3370099000, 0.3438914000, 0.3615669000, 0.4004571000, 0.4851742000, 0.7134177000, 1.4239296000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0411982000, 0.0443738000, 0.0523379000, 0.0714538000, 0.1187059000, 0.2476355000, 0.6584212000", \ - "0.0410248000, 0.0442026000, 0.0527158000, 0.0727733000, 0.1184760000, 0.2474324000, 0.6597869000", \ - "0.0410563000, 0.0442978000, 0.0521332000, 0.0727907000, 0.1184566000, 0.2468071000, 0.6598790000", \ - "0.0409434000, 0.0441169000, 0.0530755000, 0.0725112000, 0.1183052000, 0.2471634000, 0.6597243000", \ - "0.0412148000, 0.0444018000, 0.0523400000, 0.0715332000, 0.1190002000, 0.2472751000, 0.6594748000", \ - "0.0424165000, 0.0457823000, 0.0535195000, 0.0735441000, 0.1200213000, 0.2477698000, 0.6584706000", \ - "0.0504089000, 0.0533985000, 0.0621527000, 0.0822013000, 0.1304867000, 0.2577800000, 0.6640047000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0295548000, 0.0335350000, 0.0446239000, 0.0753412000, 0.1693133000, 0.4817174000, 1.5011071000", \ - "0.0295428000, 0.0335286000, 0.0446091000, 0.0753428000, 0.1692829000, 0.4817835000, 1.5005336000", \ - "0.0297039000, 0.0335386000, 0.0448245000, 0.0752877000, 0.1689967000, 0.4823765000, 1.5032781000", \ - "0.0294326000, 0.0334359000, 0.0446671000, 0.0752607000, 0.1691428000, 0.4820661000, 1.5005102000", \ - "0.0300214000, 0.0338522000, 0.0448196000, 0.0755702000, 0.1692233000, 0.4825915000, 1.5033844000", \ - "0.0332390000, 0.0374263000, 0.0489462000, 0.0793897000, 0.1717860000, 0.4826708000, 1.5033336000", \ - "0.0423702000, 0.0470146000, 0.0585380000, 0.0890413000, 0.1776412000, 0.4832996000, 1.4976328000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.3154652000, 0.3209791000, 0.3350739000, 0.3659220000, 0.4274757000, 0.5585294000, 0.8928815000", \ - "0.3188599000, 0.3243822000, 0.3384918000, 0.3692761000, 0.4308960000, 0.5619930000, 0.8962909000", \ - "0.3296821000, 0.3352057000, 0.3493008000, 0.3802172000, 0.4420791000, 0.5729892000, 0.9068158000", \ - "0.3549392000, 0.3604005000, 0.3747364000, 0.4052202000, 0.4673751000, 0.5982693000, 0.9326647000", \ - "0.4114183000, 0.4166941000, 0.4309545000, 0.4614935000, 0.5235001000, 0.6548623000, 0.9890735000", \ - "0.5400040000, 0.5456824000, 0.5600918000, 0.5911893000, 0.6526971000, 0.7846506000, 1.1191211000", \ - "0.7759816000, 0.7822963000, 0.7991668000, 0.8343622000, 0.9025913000, 1.0411748000, 1.3802589000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1450375000, 0.1499725000, 0.1630233000, 0.1942539000, 0.2718601000, 0.4968403000, 1.2052011000", \ - "0.1496321000, 0.1545699000, 0.1676348000, 0.1989590000, 0.2766329000, 0.5008903000, 1.2101369000", \ - "0.1584763000, 0.1634146000, 0.1764755000, 0.2077945000, 0.2854625000, 0.5098802000, 1.2195833000", \ - "0.1743338000, 0.1792648000, 0.1924019000, 0.2236710000, 0.3012876000, 0.5263207000, 1.2361803000", \ - "0.2040388000, 0.2091248000, 0.2224978000, 0.2541497000, 0.3319807000, 0.5571247000, 1.2684015000", \ - "0.2494058000, 0.2550432000, 0.2695510000, 0.3031385000, 0.3828534000, 0.6080625000, 1.3182279000", \ - "0.2925586000, 0.2994811000, 0.3171817000, 0.3560985000, 0.4402023000, 0.6666004000, 1.3758856000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0411840000, 0.0444376000, 0.0522725000, 0.0724634000, 0.1199904000, 0.2476456000, 0.6598929000", \ - "0.0412603000, 0.0444896000, 0.0522544000, 0.0715372000, 0.1192962000, 0.2476588000, 0.6598726000", \ - "0.0409909000, 0.0441656000, 0.0527874000, 0.0722666000, 0.1185614000, 0.2472863000, 0.6595652000", \ - "0.0410238000, 0.0444510000, 0.0525209000, 0.0715690000, 0.1187890000, 0.2473269000, 0.6586803000", \ - "0.0412249000, 0.0442267000, 0.0523233000, 0.0718687000, 0.1192561000, 0.2472083000, 0.6595018000", \ - "0.0433812000, 0.0465185000, 0.0543365000, 0.0730366000, 0.1207699000, 0.2478676000, 0.6587230000", \ - "0.0541549000, 0.0577437000, 0.0671508000, 0.0865782000, 0.1336298000, 0.2588151000, 0.6650255000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0272555000, 0.0310827000, 0.0419120000, 0.0721233000, 0.1657896000, 0.4806568000, 1.4987419000", \ - "0.0273990000, 0.0312410000, 0.0417426000, 0.0722030000, 0.1660239000, 0.4800551000, 1.5011847000", \ - "0.0273776000, 0.0312321000, 0.0418728000, 0.0722002000, 0.1660578000, 0.4799635000, 1.5023075000", \ - "0.0271799000, 0.0310274000, 0.0418851000, 0.0720804000, 0.1659130000, 0.4796665000, 1.5030103000", \ - "0.0282783000, 0.0323150000, 0.0429495000, 0.0729497000, 0.1662582000, 0.4796023000, 1.5043985000", \ - "0.0321226000, 0.0363802000, 0.0476106000, 0.0775339000, 0.1694003000, 0.4803748000, 1.5021141000", \ - "0.0428647000, 0.0472674000, 0.0589366000, 0.0890572000, 0.1761234000, 0.4823074000, 1.4981564000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.2728193000, 0.2783402000, 0.2924083000, 0.3233285000, 0.3852243000, 0.5164946000, 0.8511265000", \ - "0.2753438000, 0.2808699000, 0.2950201000, 0.3258136000, 0.3879140000, 0.5185177000, 0.8530975000", \ - "0.2838928000, 0.2894583000, 0.3035404000, 0.3342547000, 0.3962802000, 0.5271358000, 0.8616793000", \ - "0.3065303000, 0.3125820000, 0.3266687000, 0.3572970000, 0.4195124000, 0.5504991000, 0.8848665000", \ - "0.3654976000, 0.3710670000, 0.3850488000, 0.4157602000, 0.4777798000, 0.6091491000, 0.9438049000", \ - "0.5054536000, 0.5111586000, 0.5256842000, 0.5563454000, 0.6172983000, 0.7490535000, 1.0832544000", \ - "0.7472610000, 0.7538200000, 0.7714475000, 0.8091406000, 0.8766688000, 1.0099548000, 1.3487956000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1222132000, 0.1269422000, 0.1394962000, 0.1698257000, 0.2460432000, 0.4697426000, 1.1796436000", \ - "0.1272204000, 0.1319271000, 0.1445096000, 0.1748815000, 0.2512000000, 0.4747170000, 1.1854180000", \ - "0.1364029000, 0.1411075000, 0.1536790000, 0.1840542000, 0.2604013000, 0.4834329000, 1.1956698000", \ - "0.1527765000, 0.1574904000, 0.1700029000, 0.2003994000, 0.2766503000, 0.5001714000, 1.2119521000", \ - "0.1818716000, 0.1868083000, 0.1998507000, 0.2309405000, 0.3077675000, 0.5318641000, 1.2391095000", \ - "0.2234866000, 0.2291073000, 0.2436886000, 0.2769609000, 0.3562399000, 0.5804595000, 1.2931215000", \ - "0.2573907000, 0.2646049000, 0.2830207000, 0.3230801000, 0.4081520000, 0.6340679000, 1.3424366000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0410057000, 0.0441219000, 0.0530943000, 0.0721121000, 0.1185300000, 0.2468052000, 0.6582221000", \ - "0.0411559000, 0.0444200000, 0.0522990000, 0.0714216000, 0.1183796000, 0.2477092000, 0.6582966000", \ - "0.0410703000, 0.0445244000, 0.0526430000, 0.0715700000, 0.1186109000, 0.2476118000, 0.6588252000", \ - "0.0409765000, 0.0441867000, 0.0527315000, 0.0714978000, 0.1186852000, 0.2474055000, 0.6585272000", \ - "0.0413313000, 0.0442433000, 0.0531839000, 0.0715990000, 0.1183408000, 0.2470847000, 0.6575848000", \ - "0.0440510000, 0.0469117000, 0.0545498000, 0.0728639000, 0.1208191000, 0.2482498000, 0.6597914000", \ - "0.0614671000, 0.0654917000, 0.0741635000, 0.0918134000, 0.1327805000, 0.2576520000, 0.6640770000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0255436000, 0.0292523000, 0.0397282000, 0.0699105000, 0.1638183000, 0.4793191000, 1.5048988000", \ - "0.0256596000, 0.0291894000, 0.0399474000, 0.0696683000, 0.1638586000, 0.4783065000, 1.5037145000", \ - "0.0256219000, 0.0292106000, 0.0399383000, 0.0696682000, 0.1638638000, 0.4784794000, 1.5015296000", \ - "0.0256603000, 0.0293520000, 0.0397655000, 0.0696744000, 0.1639100000, 0.4788814000, 1.5056434000", \ - "0.0273373000, 0.0312847000, 0.0417115000, 0.0712956000, 0.1645143000, 0.4779686000, 1.5047322000", \ - "0.0322735000, 0.0362427000, 0.0468838000, 0.0769743000, 0.1680491000, 0.4787871000, 1.5002762000", \ - "0.0447644000, 0.0497041000, 0.0619562000, 0.0910095000, 0.1769083000, 0.4819436000, 1.4958321000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0981407000, 0.1012999000, 0.1096916000, 0.1295366000, 0.1762534000, 0.2942829000, 0.6181171000", \ - "0.1034805000, 0.1066439000, 0.1150334000, 0.1349059000, 0.1816780000, 0.2997280000, 0.6237986000", \ - "0.1161663000, 0.1193114000, 0.1276970000, 0.1474600000, 0.1943514000, 0.3124178000, 0.6361089000", \ - "0.1474628000, 0.1506083000, 0.1589561000, 0.1787003000, 0.2256701000, 0.3438045000, 0.6678486000", \ - "0.2171993000, 0.2206018000, 0.2294260000, 0.2498546000, 0.2973230000, 0.4159077000, 0.7400165000", \ - "0.3329597000, 0.3374507000, 0.3489198000, 0.3743597000, 0.4279661000, 0.5522919000, 0.8776287000", \ - "0.5148496000, 0.5208157000, 0.5360487000, 0.5697234000, 0.6392974000, 0.7810108000, 1.1142112000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1492825000, 0.1545350000, 0.1683459000, 0.2012092000, 0.2810475000, 0.5080801000, 1.2184440000", \ - "0.1535441000, 0.1588220000, 0.1726390000, 0.2053335000, 0.2852462000, 0.5119893000, 1.2220964000", \ - "0.1625719000, 0.1677841000, 0.1815452000, 0.2143620000, 0.2942413000, 0.5212651000, 1.2314402000", \ - "0.1832000000, 0.1883000000, 0.2020664000, 0.2348789000, 0.3145222000, 0.5415542000, 1.2524367000", \ - "0.2290260000, 0.2343344000, 0.2481691000, 0.2808767000, 0.3604528000, 0.5867299000, 1.3005269000", \ - "0.3021105000, 0.3079790000, 0.3227808000, 0.3569359000, 0.4378033000, 0.6649675000, 1.3752508000", \ - "0.3859490000, 0.3930809000, 0.4112494000, 0.4500975000, 0.5338325000, 0.7608441000, 1.4725184000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0176547000, 0.0198481000, 0.0260325000, 0.0431122000, 0.0912878000, 0.2245115000, 0.6434713000", \ - "0.0176573000, 0.0198460000, 0.0258985000, 0.0431024000, 0.0912236000, 0.2246613000, 0.6425248000", \ - "0.0177380000, 0.0200195000, 0.0260377000, 0.0432149000, 0.0912898000, 0.2242667000, 0.6440560000", \ - "0.0175416000, 0.0196766000, 0.0258643000, 0.0431558000, 0.0912313000, 0.2246435000, 0.6431264000", \ - "0.0206809000, 0.0228511000, 0.0285388000, 0.0449898000, 0.0921181000, 0.2250556000, 0.6443533000", \ - "0.0305218000, 0.0332550000, 0.0398251000, 0.0576836000, 0.1045070000, 0.2320227000, 0.6449422000", \ - "0.0461521000, 0.0496456000, 0.0591760000, 0.0808624000, 0.1314094000, 0.2559141000, 0.6502668000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0294171000, 0.0336621000, 0.0448859000, 0.0752187000, 0.1690187000, 0.4822972000, 1.5035203000", \ - "0.0295461000, 0.0335211000, 0.0446042000, 0.0753281000, 0.1692763000, 0.4817309000, 1.5008811000", \ - "0.0295108000, 0.0334664000, 0.0445712000, 0.0753377000, 0.1693802000, 0.4820442000, 1.5033542000", \ - "0.0293876000, 0.0333077000, 0.0443714000, 0.0751215000, 0.1687256000, 0.4818257000, 1.5031245000", \ - "0.0300645000, 0.0339127000, 0.0449594000, 0.0754252000, 0.1690168000, 0.4820984000, 1.5039817000", \ - "0.0345347000, 0.0384951000, 0.0493571000, 0.0796725000, 0.1712734000, 0.4820891000, 1.5016595000", \ - "0.0457583000, 0.0504420000, 0.0617211000, 0.0901606000, 0.1766961000, 0.4845008000, 1.4989295000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0860490000, 0.0891330000, 0.0973836000, 0.1167949000, 0.1630424000, 0.2803559000, 0.6037745000", \ - "0.0915007000, 0.0945819000, 0.1027361000, 0.1222429000, 0.1684995000, 0.2859047000, 0.6091968000", \ - "0.1050075000, 0.1080525000, 0.1162200000, 0.1356708000, 0.1818999000, 0.2992390000, 0.6224432000", \ - "0.1371056000, 0.1401865000, 0.1482676000, 0.1676541000, 0.2139813000, 0.3314532000, 0.6548909000", \ - "0.2060314000, 0.2094755000, 0.2184787000, 0.2390977000, 0.2863972000, 0.4041359000, 0.7277694000", \ - "0.3191828000, 0.3237167000, 0.3354497000, 0.3616440000, 0.4173071000, 0.5425377000, 0.8667232000", \ - "0.5018266000, 0.5076694000, 0.5230971000, 0.5574353000, 0.6297552000, 0.7747565000, 1.1075717000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.1371391000, 0.1424007000, 0.1562340000, 0.1890599000, 0.2689206000, 0.4959878000, 1.2066015000", \ - "0.1408261000, 0.1461081000, 0.1599281000, 0.1927523000, 0.2725077000, 0.4995914000, 1.2103599000", \ - "0.1498186000, 0.1550841000, 0.1689156000, 0.2017351000, 0.2815411000, 0.5086265000, 1.2191472000", \ - "0.1722668000, 0.1775118000, 0.1913145000, 0.2241070000, 0.3037455000, 0.5308073000, 1.2416616000", \ - "0.2228655000, 0.2280884000, 0.2417810000, 0.2744014000, 0.3536767000, 0.5796667000, 1.2933472000", \ - "0.2958122000, 0.3015508000, 0.3158176000, 0.3490117000, 0.4290685000, 0.6568104000, 1.3698755000", \ - "0.3696992000, 0.3769925000, 0.3944934000, 0.4328670000, 0.5145332000, 0.7418016000, 1.4538029000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0167064000, 0.0189527000, 0.0250631000, 0.0422397000, 0.0903270000, 0.2238158000, 0.6434627000", \ - "0.0166559000, 0.0189517000, 0.0250588000, 0.0422486000, 0.0903522000, 0.2235326000, 0.6432676000", \ - "0.0167476000, 0.0189389000, 0.0249788000, 0.0421664000, 0.0903281000, 0.2234219000, 0.6436010000", \ - "0.0167010000, 0.0188512000, 0.0249740000, 0.0422745000, 0.0903557000, 0.2237725000, 0.6434555000", \ - "0.0207444000, 0.0229317000, 0.0289268000, 0.0452179000, 0.0917646000, 0.2243281000, 0.6428020000", \ - "0.0312381000, 0.0336103000, 0.0414706000, 0.0593143000, 0.1058068000, 0.2325588000, 0.6436645000", \ - "0.0470362000, 0.0507277000, 0.0599756000, 0.0839648000, 0.1369074000, 0.2606451000, 0.6510824000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0294350000, 0.0334189000, 0.0448337000, 0.0752800000, 0.1690218000, 0.4824715000, 1.5034666000", \ - "0.0295610000, 0.0336788000, 0.0447142000, 0.0752637000, 0.1687289000, 0.4816908000, 1.5027315000", \ - "0.0295992000, 0.0335781000, 0.0447944000, 0.0751901000, 0.1689923000, 0.4825108000, 1.5035473000", \ - "0.0295396000, 0.0334434000, 0.0443299000, 0.0750376000, 0.1687832000, 0.4824401000, 1.5033428000", \ - "0.0294859000, 0.0335055000, 0.0446122000, 0.0753497000, 0.1686503000, 0.4821779000, 1.5045358000", \ - "0.0351496000, 0.0386916000, 0.0493967000, 0.0787215000, 0.1713848000, 0.4831945000, 1.5051032000", \ - "0.0474298000, 0.0518338000, 0.0628907000, 0.0900473000, 0.1757284000, 0.4851209000, 1.5025339000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311ai_0") { - leakage_power () { - value : 0.0001085000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 3.7228392e-05; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0010956000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0001021000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0020640000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0019715000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0016459000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0023676000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0016930000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0016943000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0004090000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.7689107e-05; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0016309000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003979000; - when : "A1&A2&A3&B1&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o311ai"; - cell_leakage_power : 0.0006372847; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0017820000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029297000, 0.0029295000, 0.0029290000, 0.0029287000, 0.0029281000, 0.0029267000, 0.0029234000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002936800, -0.002933300, -0.002925000, -0.002924500, -0.002923400, -0.002920900, -0.002915000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018450000; - } - pin ("A2") { - capacitance : 0.0018750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030534000, 0.0030503000, 0.0030431000, 0.0030433000, 0.0030438000, 0.0030451000, 0.0030479000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003064700, -0.003056800, -0.003038700, -0.003039200, -0.003040300, -0.003043000, -0.003049100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019810000; - } - pin ("A3") { - capacitance : 0.0016940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027462000, 0.0027453000, 0.0027432000, 0.0027435000, 0.0027442000, 0.0027460000, 0.0027500000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002744400, -0.002744000, -0.002742900, -0.002743000, -0.002743200, -0.002743700, -0.002744900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018140000; - } - pin ("B1") { - capacitance : 0.0017280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029245000, 0.0029144000, 0.0028912000, 0.0028939000, 0.0029002000, 0.0029146000, 0.0029477000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002848400, -0.002847800, -0.002846200, -0.002846000, -0.002845500, -0.002844400, -0.002841900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017750000; - } - pin ("C1") { - capacitance : 0.0017240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0034926000, 0.0034931000, 0.0034942000, 0.0034951000, 0.0034969000, 0.0035013000, 0.0035114000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002944600, -0.002947200, -0.002953300, -0.002948700, -0.002938200, -0.002913900, -0.002857900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017510000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0055750000, 0.0047979000, 0.0032714000, 0.0002445000, -0.005729800, -0.017538700, -0.040883400", \ - "0.0054991000, 0.0047218000, 0.0031929000, 0.0001665000, -0.005805500, -0.017628700, -0.040948100", \ - "0.0054118000, 0.0046335000, 0.0031113000, 8.720000e-05, -0.005888100, -0.017703800, -0.041025800", \ - "0.0053149000, 0.0045412000, 0.0030233000, 8.500000e-06, -0.005953900, -0.017756000, -0.041078900", \ - "0.0052625000, 0.0045011000, 0.0029797000, -3.16000e-05, -0.005994400, -0.017780300, -0.041093900", \ - "0.0052932000, 0.0045088000, 0.0029678000, -0.000138900, -0.006075600, -0.017853400, -0.041160500", \ - "0.0055612000, 0.0047906000, 0.0032136000, 0.0001528000, -0.005893300, -0.017844000, -0.041119700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0122865000, 0.0130916000, 0.0146603000, 0.0176952000, 0.0236999000, 0.0354856000, 0.0586578000", \ - "0.0122117000, 0.0130168000, 0.0145744000, 0.0176431000, 0.0236264000, 0.0354214000, 0.0585351000", \ - "0.0121457000, 0.0129416000, 0.0144961000, 0.0175715000, 0.0235784000, 0.0353738000, 0.0585012000", \ - "0.0120514000, 0.0128501000, 0.0144092000, 0.0174915000, 0.0235130000, 0.0352871000, 0.0584879000", \ - "0.0119754000, 0.0127687000, 0.0143428000, 0.0174141000, 0.0234442000, 0.0352384000, 0.0584260000", \ - "0.0119615000, 0.0127517000, 0.0142924000, 0.0173605000, 0.0233767000, 0.0351905000, 0.0583699000", \ - "0.0118422000, 0.0127050000, 0.0142992000, 0.0174140000, 0.0234998000, 0.0352267000, 0.0583883000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0050180000, 0.0042240000, 0.0026840000, -0.000351800, -0.006352800, -0.018190700, -0.041520000", \ - "0.0049668000, 0.0041931000, 0.0026567000, -0.000376300, -0.006373000, -0.018214300, -0.041568700", \ - "0.0048711000, 0.0041018000, 0.0025823000, -0.000444700, -0.006428400, -0.018259800, -0.041605300", \ - "0.0047058000, 0.0039496000, 0.0024485000, -0.000546400, -0.006498500, -0.018297000, -0.041635100", \ - "0.0045406000, 0.0037935000, 0.0022951000, -0.000687500, -0.006610600, -0.018375600, -0.041671300", \ - "0.0045094000, 0.0037315000, 0.0022196000, -0.000884400, -0.006807000, -0.018527900, -0.041783400", \ - "0.0046608000, 0.0038685000, 0.0023112000, -0.000729500, -0.006726700, -0.018605100, -0.041868800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0109768000, 0.0117582000, 0.0133330000, 0.0163935000, 0.0223711000, 0.0341857000, 0.0572924000", \ - "0.0108640000, 0.0116584000, 0.0132391000, 0.0162859000, 0.0223078000, 0.0340793000, 0.0572063000", \ - "0.0107634000, 0.0115725000, 0.0131220000, 0.0162183000, 0.0222263000, 0.0340571000, 0.0572260000", \ - "0.0106214000, 0.0114288000, 0.0130081000, 0.0160934000, 0.0221252000, 0.0339766000, 0.0571163000", \ - "0.0105192000, 0.0113057000, 0.0128804000, 0.0159669000, 0.0220214000, 0.0338666000, 0.0570911000", \ - "0.0104656000, 0.0112432000, 0.0128090000, 0.0159326000, 0.0219613000, 0.0337692000, 0.0570022000", \ - "0.0105753000, 0.0113408000, 0.0128813000, 0.0159839000, 0.0219539000, 0.0337767000, 0.0570176000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0038439000, 0.0030785000, 0.0015353000, -0.001500300, -0.007506700, -0.019354100, -0.042744500", \ - "0.0038165000, 0.0030548000, 0.0015521000, -0.001469400, -0.007459100, -0.019311300, -0.042683600", \ - "0.0037295000, 0.0029820000, 0.0014828000, -0.001493700, -0.007453600, -0.019271200, -0.042639500", \ - "0.0035335000, 0.0027990000, 0.0013304000, -0.001617300, -0.007535800, -0.019312100, -0.042642000", \ - "0.0033380000, 0.0025936000, 0.0011323000, -0.001808400, -0.007699200, -0.019415700, -0.042690800", \ - "0.0032971000, 0.0025282000, 0.0010272000, -0.001946200, -0.007918200, -0.019607300, -0.042834900", \ - "0.0034535000, 0.0026531000, 0.0010947000, -0.001930400, -0.007907000, -0.019714700, -0.042972600"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0095814000, 0.0103759000, 0.0119407000, 0.0150063000, 0.0210086000, 0.0327711000, 0.0559209000", \ - "0.0094692000, 0.0102750000, 0.0118174000, 0.0149086000, 0.0209086000, 0.0327158000, 0.0557891000", \ - "0.0092983000, 0.0101070000, 0.0117054000, 0.0147842000, 0.0208046000, 0.0326306000, 0.0557857000", \ - "0.0091328000, 0.0099520000, 0.0115248000, 0.0146250000, 0.0206661000, 0.0325370000, 0.0556900000", \ - "0.0090519000, 0.0098575000, 0.0114305000, 0.0145224000, 0.0205434000, 0.0323969000, 0.0556167000", \ - "0.0091738000, 0.0099515000, 0.0115118000, 0.0145462000, 0.0205501000, 0.0323262000, 0.0555640000", \ - "0.0098125000, 0.0105820000, 0.0121157000, 0.0150745000, 0.0209638000, 0.0327396000, 0.0558536000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0059109000, 0.0051536000, 0.0036396000, 0.0006155000, -0.005352500, -0.017145400, -0.040486200", \ - "0.0058478000, 0.0050805000, 0.0035781000, 0.0005750000, -0.005375000, -0.017168100, -0.040483300", \ - "0.0057486000, 0.0049890000, 0.0034791000, 0.0004975000, -0.005429600, -0.017202700, -0.040505000", \ - "0.0056135000, 0.0048588000, 0.0033635000, 0.0003795000, -0.005522700, -0.017280900, -0.040564200", \ - "0.0054799000, 0.0047231000, 0.0032284000, 0.0002590000, -0.005652000, -0.017383900, -0.040626700", \ - "0.0055005000, 0.0047124000, 0.0031684000, 0.0001504000, -0.005778400, -0.017535300, -0.040729500", \ - "0.0059869000, 0.0051876000, 0.0036046000, 0.0005260000, -0.005545700, -0.017495200, -0.040797600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0089928000, 0.0097963000, 0.0113546000, 0.0144121000, 0.0204119000, 0.0321974000, 0.0552882000", \ - "0.0089020000, 0.0097060000, 0.0112865000, 0.0143316000, 0.0203566000, 0.0321973000, 0.0553136000", \ - "0.0087597000, 0.0095785000, 0.0111732000, 0.0142766000, 0.0202752000, 0.0320795000, 0.0552111000", \ - "0.0085468000, 0.0093480000, 0.0109347000, 0.0140486000, 0.0201255000, 0.0318397000, 0.0551339000", \ - "0.0084673000, 0.0092601000, 0.0108103000, 0.0138820000, 0.0199442000, 0.0318138000, 0.0549667000", \ - "0.0087238000, 0.0094720000, 0.0110109000, 0.0140674000, 0.0201580000, 0.0316660000, 0.0548192000", \ - "0.0092705000, 0.0100154000, 0.0114653000, 0.0143673000, 0.0203419000, 0.0320271000, 0.0551674000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0058991000, 0.0051379000, 0.0036337000, 0.0006329000, -0.005333600, -0.017110000, -0.040443200", \ - "0.0057960000, 0.0050461000, 0.0035522000, 0.0005837000, -0.005351900, -0.017144700, -0.040454700", \ - "0.0056938000, 0.0049357000, 0.0034363000, 0.0004801000, -0.005418900, -0.017183900, -0.040475700", \ - "0.0055322000, 0.0047771000, 0.0032809000, 0.0003212000, -0.005566000, -0.017284200, -0.040540900", \ - "0.0054058000, 0.0046484000, 0.0031485000, 0.0001611000, -0.005741300, -0.017434400, -0.040659800", \ - "0.0056228000, 0.0048357000, 0.0032918000, 0.0001204000, -0.005833600, -0.017576600, -0.040785600", \ - "0.0063133000, 0.0054834000, 0.0039000000, 0.0007635000, -0.005335800, -0.017265800, -0.040381100"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0009854544, 0.0019422410, 0.0038279800, 0.0075446000, 0.0148697200, 0.0293068700"); - values("0.0069641000, 0.0078033000, 0.0094003000, 0.0125064000, 0.0185305000, 0.0303653000, 0.0534097000", \ - "0.0068063000, 0.0076608000, 0.0092919000, 0.0124176000, 0.0184772000, 0.0303130000, 0.0534345000", \ - "0.0065847000, 0.0074252000, 0.0091050000, 0.0122890000, 0.0183184000, 0.0302444000, 0.0534039000", \ - "0.0064002000, 0.0072182000, 0.0088283000, 0.0120147000, 0.0180127000, 0.0299648000, 0.0531493000", \ - "0.0064767000, 0.0072354000, 0.0087664000, 0.0118115000, 0.0178266000, 0.0298058000, 0.0530095000", \ - "0.0067464000, 0.0074402000, 0.0089611000, 0.0121622000, 0.0178544000, 0.0297055000, 0.0526642000", \ - "0.0074192000, 0.0081370000, 0.0095958000, 0.0125122000, 0.0184339000, 0.0301978000, 0.0535383000"); - } - } - max_capacitance : 0.0293070000; - max_transition : 1.4812000000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0831662000, 0.0899731000, 0.1034506000, 0.1287437000, 0.1772558000, 0.2705285000, 0.4523192000", \ - "0.0875566000, 0.0945339000, 0.1078377000, 0.1331229000, 0.1816399000, 0.2751664000, 0.4569844000", \ - "0.0971093000, 0.1042452000, 0.1174942000, 0.1429106000, 0.1914301000, 0.2849295000, 0.4666082000", \ - "0.1158690000, 0.1227889000, 0.1360795000, 0.1614252000, 0.2099563000, 0.3035957000, 0.4853478000", \ - "0.1494129000, 0.1574065000, 0.1718374000, 0.1991696000, 0.2487637000, 0.3424609000, 0.5244084000", \ - "0.2003030000, 0.2100491000, 0.2286615000, 0.2630458000, 0.3218667000, 0.4258147000, 0.6123361000", \ - "0.2507438000, 0.2675169000, 0.2963184000, 0.3471085000, 0.4304500000, 0.5659992000, 0.7888524000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.2223490000, 0.2390723000, 0.2725376000, 0.3361447000, 0.4604954000, 0.7031196000, 1.1796046000", \ - "0.2272915000, 0.2437520000, 0.2772778000, 0.3412196000, 0.4654935000, 0.7082439000, 1.1843577000", \ - "0.2395024000, 0.2563862000, 0.2890516000, 0.3532512000, 0.4777216000, 0.7205898000, 1.1970243000", \ - "0.2641576000, 0.2812181000, 0.3141146000, 0.3782608000, 0.5029369000, 0.7461386000, 1.2227265000", \ - "0.3154502000, 0.3325671000, 0.3651464000, 0.4288109000, 0.5539342000, 0.7978915000, 1.2747774000", \ - "0.4168603000, 0.4354661000, 0.4715650000, 0.5390364000, 0.6641098000, 0.9073836000, 1.3844252000", \ - "0.5875631000, 0.6102274000, 0.6552493000, 0.7390685000, 0.8891985000, 1.1534893000, 1.6336973000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0683429000, 0.0768657000, 0.0931753000, 0.1248458000, 0.1870540000, 0.3097394000, 0.5513521000", \ - "0.0684753000, 0.0767221000, 0.0930564000, 0.1248097000, 0.1870887000, 0.3097128000, 0.5511874000", \ - "0.0684054000, 0.0767302000, 0.0930693000, 0.1249002000, 0.1870087000, 0.3097897000, 0.5519457000", \ - "0.0690927000, 0.0773230000, 0.0932227000, 0.1246655000, 0.1869293000, 0.3098615000, 0.5520577000", \ - "0.0804592000, 0.0881306000, 0.1033540000, 0.1328072000, 0.1914370000, 0.3110381000, 0.5518380000", \ - "0.1130034000, 0.1215507000, 0.1374000000, 0.1673369000, 0.2244016000, 0.3350172000, 0.5624056000", \ - "0.1873366000, 0.1978371000, 0.2161230000, 0.2514689000, 0.3139135000, 0.4274014000, 0.6425225000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.1873640000, 0.2095607000, 0.2526425000, 0.3360046000, 0.5011302000, 0.8249859000, 1.4627460000", \ - "0.1873665000, 0.2096301000, 0.2519667000, 0.3363238000, 0.5012739000, 0.8257360000, 1.4634429000", \ - "0.1877138000, 0.2097078000, 0.2519305000, 0.3369366000, 0.5011113000, 0.8254225000, 1.4629760000", \ - "0.1875840000, 0.2096192000, 0.2519523000, 0.3368196000, 0.5011007000, 0.8251602000, 1.4630799000", \ - "0.1893178000, 0.2106540000, 0.2523417000, 0.3361082000, 0.5011287000, 0.8252306000, 1.4622669000", \ - "0.2178193000, 0.2378601000, 0.2771978000, 0.3543565000, 0.5108060000, 0.8270963000, 1.4634025000", \ - "0.2900788000, 0.3126946000, 0.3550440000, 0.4364973000, 0.5896219000, 0.8781492000, 1.4812003000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0783559000, 0.0845487000, 0.0968268000, 0.1208105000, 0.1672923000, 0.2583789000, 0.4370093000", \ - "0.0831034000, 0.0894298000, 0.1017288000, 0.1257354000, 0.1722739000, 0.2634750000, 0.4420796000", \ - "0.0924072000, 0.0988568000, 0.1112723000, 0.1351580000, 0.1819016000, 0.2732034000, 0.4518864000", \ - "0.1096176000, 0.1160847000, 0.1285936000, 0.1528617000, 0.1996953000, 0.2909126000, 0.4701926000", \ - "0.1377666000, 0.1454786000, 0.1597980000, 0.1866282000, 0.2358962000, 0.3277522000, 0.5071318000", \ - "0.1756558000, 0.1862667000, 0.2060481000, 0.2406197000, 0.2999811000, 0.4046351000, 0.5902706000", \ - "0.2038302000, 0.2206933000, 0.2505607000, 0.3039619000, 0.3908155000, 0.5282429000, 0.7523197000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.2157001000, 0.2333328000, 0.2663218000, 0.3296881000, 0.4544088000, 0.6971070000, 1.1736031000", \ - "0.2200275000, 0.2364789000, 0.2698430000, 0.3340781000, 0.4579750000, 0.7014920000, 1.1772707000", \ - "0.2304100000, 0.2476830000, 0.2808348000, 0.3445136000, 0.4699257000, 0.7125203000, 1.1895402000", \ - "0.2549559000, 0.2726369000, 0.3057777000, 0.3697598000, 0.4955611000, 0.7385663000, 1.2156195000", \ - "0.3137034000, 0.3307583000, 0.3635061000, 0.4281297000, 0.5527828000, 0.7969265000, 1.2744821000", \ - "0.4394292000, 0.4572235000, 0.4942457000, 0.5641947000, 0.6887750000, 0.9329369000, 1.4105737000", \ - "0.6561098000, 0.6817092000, 0.7308523000, 0.8208190000, 0.9772321000, 1.2483152000, 1.7283412000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0570079000, 0.0651221000, 0.0810276000, 0.1124764000, 0.1741110000, 0.2958700000, 0.5346892000", \ - "0.0570416000, 0.0651124000, 0.0810484000, 0.1123807000, 0.1741212000, 0.2956188000, 0.5352072000", \ - "0.0569783000, 0.0650978000, 0.0810468000, 0.1124272000, 0.1741915000, 0.2959977000, 0.5355455000", \ - "0.0585327000, 0.0664023000, 0.0818569000, 0.1127514000, 0.1741036000, 0.2955693000, 0.5348460000", \ - "0.0704213000, 0.0783405000, 0.0933077000, 0.1224985000, 0.1798199000, 0.2978779000, 0.5353570000", \ - "0.1037013000, 0.1118734000, 0.1277553000, 0.1570439000, 0.2139425000, 0.3238574000, 0.5479320000", \ - "0.1773583000, 0.1884484000, 0.2082157000, 0.2435927000, 0.3048805000, 0.4159577000, 0.6302678000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.1877848000, 0.2094108000, 0.2527406000, 0.3361929000, 0.5023590000, 0.8247378000, 1.4620456000", \ - "0.1874247000, 0.2091623000, 0.2525261000, 0.3359398000, 0.5013909000, 0.8252323000, 1.4634995000", \ - "0.1876638000, 0.2097424000, 0.2517932000, 0.3363611000, 0.5009383000, 0.8248281000, 1.4630767000", \ - "0.1874347000, 0.2096326000, 0.2523063000, 0.3362564000, 0.5012598000, 0.8249241000, 1.4631756000", \ - "0.1905397000, 0.2114264000, 0.2526048000, 0.3360306000, 0.5014125000, 0.8249584000, 1.4626289000", \ - "0.2316655000, 0.2485299000, 0.2845203000, 0.3596451000, 0.5116028000, 0.8249380000, 1.4635378000", \ - "0.3307508000, 0.3504886000, 0.3926495000, 0.4694877000, 0.6095753000, 0.8848566000, 1.4799399000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0619858000, 0.0679810000, 0.0792732000, 0.1016770000, 0.1452734000, 0.2319842000, 0.4004685000", \ - "0.0670232000, 0.0729252000, 0.0843362000, 0.1067036000, 0.1507326000, 0.2373238000, 0.4078879000", \ - "0.0763941000, 0.0823302000, 0.0940801000, 0.1169143000, 0.1610354000, 0.2473085000, 0.4163673000", \ - "0.0929986000, 0.0994526000, 0.1115598000, 0.1345535000, 0.1788359000, 0.2659567000, 0.4359823000", \ - "0.1179757000, 0.1258393000, 0.1406487000, 0.1675187000, 0.2154525000, 0.3031789000, 0.4746377000", \ - "0.1454378000, 0.1574127000, 0.1790038000, 0.2158043000, 0.2785204000, 0.3809993000, 0.5592013000", \ - "0.1505060000, 0.1706044000, 0.2055057000, 0.2644399000, 0.3584394000, 0.4991641000, 0.7239814000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.1836466000, 0.2001214000, 0.2324444000, 0.2963793000, 0.4209395000, 0.6644515000, 1.1401082000", \ - "0.1854671000, 0.2027507000, 0.2355259000, 0.2992946000, 0.4243276000, 0.6670010000, 1.1436555000", \ - "0.1940882000, 0.2108099000, 0.2447310000, 0.3086553000, 0.4338735000, 0.6769835000, 1.1537348000", \ - "0.2188234000, 0.2359346000, 0.2694192000, 0.3332755000, 0.4589758000, 0.7028518000, 1.1806474000", \ - "0.2817566000, 0.2988774000, 0.3314793000, 0.3953979000, 0.5208763000, 0.7651541000, 1.2425414000", \ - "0.4221437000, 0.4420535000, 0.4790860000, 0.5457673000, 0.6696656000, 0.9100307000, 1.3885552000", \ - "0.6545519000, 0.6838820000, 0.7386164000, 0.8338998000, 0.9969746000, 1.2609668000, 1.7286257000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0435780000, 0.0514085000, 0.0662925000, 0.0960383000, 0.1543356000, 0.2712432000, 0.4968332000", \ - "0.0435712000, 0.0512382000, 0.0665679000, 0.0967426000, 0.1551624000, 0.2698767000, 0.4980034000", \ - "0.0436484000, 0.0513369000, 0.0663303000, 0.0964716000, 0.1552157000, 0.2715675000, 0.4974702000", \ - "0.0467482000, 0.0537976000, 0.0680519000, 0.0969332000, 0.1545685000, 0.2700148000, 0.4982169000", \ - "0.0608986000, 0.0679785000, 0.0822434000, 0.1094798000, 0.1622327000, 0.2731980000, 0.4990619000", \ - "0.0974089000, 0.1051993000, 0.1201628000, 0.1481275000, 0.2044086000, 0.3044255000, 0.5110984000", \ - "0.1723384000, 0.1831974000, 0.2035767000, 0.2379671000, 0.2984816000, 0.4025356000, 0.6081566000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.1871436000, 0.2091553000, 0.2520865000, 0.3369351000, 0.5012143000, 0.8252308000, 1.4634653000", \ - "0.1876392000, 0.2094982000, 0.2519573000, 0.3363533000, 0.5009606000, 0.8255009000, 1.4628416000", \ - "0.1873317000, 0.2091598000, 0.2523251000, 0.3362005000, 0.5014599000, 0.8250852000, 1.4632170000", \ - "0.1872056000, 0.2092015000, 0.2518021000, 0.3362742000, 0.5012125000, 0.8251309000, 1.4633720000", \ - "0.1912343000, 0.2112523000, 0.2525365000, 0.3357879000, 0.5012642000, 0.8258399000, 1.4614837000", \ - "0.2463189000, 0.2650232000, 0.2981608000, 0.3681981000, 0.5148734000, 0.8259039000, 1.4635951000", \ - "0.3591963000, 0.3846766000, 0.4298432000, 0.5138188000, 0.6516412000, 0.9098853000, 1.4786724000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0757190000, 0.0827512000, 0.0960601000, 0.1214212000, 0.1700404000, 0.2635843000, 0.4456636000", \ - "0.0797200000, 0.0866579000, 0.1001236000, 0.1257533000, 0.1744642000, 0.2680173000, 0.4498254000", \ - "0.0882976000, 0.0953704000, 0.1089600000, 0.1344235000, 0.1832685000, 0.2770342000, 0.4590311000", \ - "0.1092355000, 0.1161540000, 0.1294717000, 0.1550313000, 0.2041392000, 0.2984182000, 0.4806632000", \ - "0.1482045000, 0.1566131000, 0.1721964000, 0.2014788000, 0.2526336000, 0.3472413000, 0.5301882000", \ - "0.2005788000, 0.2130943000, 0.2360326000, 0.2752785000, 0.3419705000, 0.4519944000, 0.6428886000", \ - "0.2492286000, 0.2681706000, 0.3041308000, 0.3645858000, 0.4652672000, 0.6230508000, 0.8647844000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0517929000, 0.0572737000, 0.0679645000, 0.0890798000, 0.1299901000, 0.2100645000, 0.3676574000", \ - "0.0572593000, 0.0628262000, 0.0737505000, 0.0945763000, 0.1357630000, 0.2158137000, 0.3743744000", \ - "0.0704248000, 0.0760189000, 0.0868355000, 0.1080457000, 0.1488102000, 0.2299689000, 0.3872772000", \ - "0.1026797000, 0.1081952000, 0.1190348000, 0.1402279000, 0.1813790000, 0.2608413000, 0.4185613000", \ - "0.1618670000, 0.1709003000, 0.1870238000, 0.2137189000, 0.2567583000, 0.3370353000, 0.4942052000", \ - "0.2584646000, 0.2728674000, 0.2989693000, 0.3422844000, 0.4097155000, 0.5107083000, 0.6701247000", \ - "0.4145380000, 0.4377840000, 0.4789618000, 0.5489743000, 0.6602082000, 0.8252530000, 1.0561592000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0684299000, 0.0768850000, 0.0930334000, 0.1248142000, 0.1870929000, 0.3097560000, 0.5515106000", \ - "0.0684837000, 0.0768036000, 0.0931933000, 0.1249138000, 0.1870343000, 0.3098166000, 0.5517776000", \ - "0.0680484000, 0.0764284000, 0.0926227000, 0.1247230000, 0.1870541000, 0.3094957000, 0.5517979000", \ - "0.0704233000, 0.0782167000, 0.0939442000, 0.1247423000, 0.1867868000, 0.3096540000, 0.5510504000", \ - "0.0901377000, 0.0979953000, 0.1126968000, 0.1399627000, 0.1950591000, 0.3116804000, 0.5518083000", \ - "0.1330503000, 0.1423509000, 0.1596080000, 0.1908013000, 0.2470216000, 0.3493531000, 0.5666746000", \ - "0.2138368000, 0.2269857000, 0.2523173000, 0.2946740000, 0.3643658000, 0.4811370000, 0.6820964000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0592715000, 0.0677370000, 0.0840120000, 0.1154698000, 0.1766120000, 0.2952898000, 0.5224854000", \ - "0.0593764000, 0.0677189000, 0.0839981000, 0.1155217000, 0.1766370000, 0.2953892000, 0.5225362000", \ - "0.0593170000, 0.0676686000, 0.0839992000, 0.1155442000, 0.1766729000, 0.2956183000, 0.5227512000", \ - "0.0667414000, 0.0736139000, 0.0876518000, 0.1165529000, 0.1766265000, 0.2956028000, 0.5228210000", \ - "0.1044037000, 0.1097623000, 0.1193954000, 0.1409127000, 0.1896117000, 0.2972292000, 0.5228725000", \ - "0.1797959000, 0.1877618000, 0.2016072000, 0.2259589000, 0.2680479000, 0.3485530000, 0.5393027000", \ - "0.3168141000, 0.3275794000, 0.3483447000, 0.3852625000, 0.4455420000, 0.5393506000, 0.6887629000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0682209000, 0.0753269000, 0.0888166000, 0.1143304000, 0.1629822000, 0.2565438000, 0.4386596000", \ - "0.0719086000, 0.0790659000, 0.0926850000, 0.1182954000, 0.1671176000, 0.2607962000, 0.4428495000", \ - "0.0810541000, 0.0883283000, 0.1016782000, 0.1274512000, 0.1763455000, 0.2703494000, 0.4525187000", \ - "0.1047961000, 0.1115456000, 0.1245347000, 0.1501167000, 0.1992035000, 0.2931710000, 0.4756652000", \ - "0.1482467000, 0.1574597000, 0.1741904000, 0.2037385000, 0.2530678000, 0.3466426000, 0.5290618000", \ - "0.2009514000, 0.2142751000, 0.2383050000, 0.2823974000, 0.3549952000, 0.4695810000, 0.6548809000", \ - "0.2528492000, 0.2726770000, 0.3099093000, 0.3757376000, 0.4824854000, 0.6527435000, 0.9054628000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0409891000, 0.0463092000, 0.0564172000, 0.0760289000, 0.1141369000, 0.1895535000, 0.3358567000", \ - "0.0461594000, 0.0515180000, 0.0615629000, 0.0812701000, 0.1198056000, 0.1950210000, 0.3414709000", \ - "0.0590730000, 0.0643839000, 0.0746845000, 0.0945803000, 0.1330367000, 0.2085064000, 0.3548173000", \ - "0.0888982000, 0.0952544000, 0.1061676000, 0.1257020000, 0.1629821000, 0.2382636000, 0.3847562000", \ - "0.1375461000, 0.1476996000, 0.1647377000, 0.1943520000, 0.2381313000, 0.3127656000, 0.4600287000", \ - "0.2130596000, 0.2298634000, 0.2588562000, 0.3054518000, 0.3769409000, 0.4806559000, 0.6315476000", \ - "0.3328298000, 0.3587003000, 0.4048209000, 0.4794606000, 0.5960620000, 0.7638981000, 0.9955616000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0686690000, 0.0768320000, 0.0931358000, 0.1248073000, 0.1871032000, 0.3095509000, 0.5515090000", \ - "0.0685307000, 0.0767850000, 0.0931508000, 0.1248362000, 0.1871443000, 0.3097311000, 0.5516543000", \ - "0.0676673000, 0.0763615000, 0.0926807000, 0.1248319000, 0.1870924000, 0.3101681000, 0.5520542000", \ - "0.0710204000, 0.0785485000, 0.0935766000, 0.1241958000, 0.1868286000, 0.3094089000, 0.5522757000", \ - "0.0964830000, 0.1044521000, 0.1191005000, 0.1457784000, 0.1979943000, 0.3116835000, 0.5519258000", \ - "0.1484102000, 0.1595402000, 0.1794608000, 0.2120477000, 0.2691389000, 0.3651311000, 0.5722026000", \ - "0.2352677000, 0.2517098000, 0.2854744000, 0.3296218000, 0.4088571000, 0.5354372000, 0.7416083000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0009854540, 0.0019422400, 0.0038279800, 0.0075446000, 0.0148697000, 0.0293069000"); - values("0.0473421000, 0.0551542000, 0.0703418000, 0.0998087000, 0.1567945000, 0.2675586000, 0.4802361000", \ - "0.0473366000, 0.0551091000, 0.0703666000, 0.0998079000, 0.1567162000, 0.2674170000, 0.4802255000", \ - "0.0477285000, 0.0552292000, 0.0703663000, 0.0998071000, 0.1567684000, 0.2673564000, 0.4802834000", \ - "0.0600981000, 0.0655828000, 0.0773437000, 0.1028164000, 0.1567684000, 0.2673149000, 0.4804921000", \ - "0.1020910000, 0.1072370000, 0.1168095000, 0.1327931000, 0.1747566000, 0.2715730000, 0.4805327000", \ - "0.1775648000, 0.1844598000, 0.1973327000, 0.2209889000, 0.2601803000, 0.3323032000, 0.5041540000", \ - "0.3139914000, 0.3235256000, 0.3418003000, 0.3760761000, 0.4359909000, 0.5293387000, 0.6719448000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311ai_1") { - leakage_power () { - value : 9.9776937e-05; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0066099000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0009604000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 9.340170e-05; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0033522000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003514000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0031897000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003519000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0026940000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003503000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0038850000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003527000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0027613000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003503000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0027617000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0003503000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0003608000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 4.4096471e-05; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0026779000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0003503000; - when : "A1&A2&A3&B1&!C1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o311ai"; - cell_leakage_power : 0.0010742710; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041125000, 0.0041117000, 0.0041099000, 0.0041077000, 0.0041026000, 0.0040909000, 0.0040640000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004102200, -0.004099500, -0.004093200, -0.004092300, -0.004090200, -0.004085500, -0.004074600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024680000; - } - pin ("A2") { - capacitance : 0.0024650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041766000, 0.0041768000, 0.0041774000, 0.0041779000, 0.0041791000, 0.0041817000, 0.0041877000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004184800, -0.004181800, -0.004174800, -0.004173700, -0.004171000, -0.004164800, -0.004150500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026210000; - } - pin ("A3") { - capacitance : 0.0023330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039584000, 0.0039580000, 0.0039569000, 0.0039554000, 0.0039521000, 0.0039443000, 0.0039265000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003964100, -0.003961600, -0.003955900, -0.003956600, -0.003958200, -0.003961800, -0.003970300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025080000; - } - pin ("B1") { - capacitance : 0.0023410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041219000, 0.0041029000, 0.0040593000, 0.0040639000, 0.0040745000, 0.0040989000, 0.0041553000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003987200, -0.003985400, -0.003981300, -0.003982200, -0.003984200, -0.003989000, -0.003999800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024150000; - } - pin ("C1") { - capacitance : 0.0023320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048158000, 0.0048173000, 0.0048210000, 0.0048221000, 0.0048246000, 0.0048303000, 0.0048434000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004005500, -0.004000900, -0.003990400, -0.003984100, -0.003969600, -0.003936200, -0.003859200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023800000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0081101000, 0.0072107000, 0.0053080000, 0.0012522000, -0.007393400, -0.025781900, -0.064902100", \ - "0.0079946000, 0.0070984000, 0.0051861000, 0.0011396000, -0.007500900, -0.025893900, -0.065023300", \ - "0.0078777000, 0.0069656000, 0.0050598000, 0.0010042000, -0.007625100, -0.026002900, -0.065137300", \ - "0.0077270000, 0.0068317000, 0.0049159000, 0.0008781000, -0.007727900, -0.026097500, -0.065224400", \ - "0.0076184000, 0.0067197000, 0.0048400000, 0.0008293000, -0.007770900, -0.026114400, -0.065233100", \ - "0.0077067000, 0.0068057000, 0.0048919000, 0.0008170000, -0.007922700, -0.026232900, -0.065331500", \ - "0.0082309000, 0.0072749000, 0.0053342000, 0.0012606000, -0.007507300, -0.026046900, -0.065285900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0171668000, 0.0180738000, 0.0200341000, 0.0241303000, 0.0328036000, 0.0512021000, 0.0900269000", \ - "0.0170538000, 0.0179740000, 0.0199023000, 0.0240399000, 0.0327086000, 0.0510458000, 0.0899819000", \ - "0.0169216000, 0.0178560000, 0.0197856000, 0.0239332000, 0.0326298000, 0.0509692000, 0.0899112000", \ - "0.0167940000, 0.0177234000, 0.0197007000, 0.0237967000, 0.0325038000, 0.0509652000, 0.0898829000", \ - "0.0166956000, 0.0176187000, 0.0195728000, 0.0236926000, 0.0324242000, 0.0508136000, 0.0896618000", \ - "0.0166954000, 0.0176278000, 0.0195668000, 0.0236449000, 0.0323799000, 0.0507006000, 0.0897265000", \ - "0.0165105000, 0.0174250000, 0.0195417000, 0.0237338000, 0.0325636000, 0.0509402000, 0.0896890000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0071169000, 0.0062157000, 0.0043021000, 0.0002142000, -0.008456200, -0.026897500, -0.066084800", \ - "0.0070573000, 0.0061688000, 0.0042632000, 0.0001893000, -0.008468900, -0.026904500, -0.066087100", \ - "0.0069368000, 0.0060426000, 0.0041619000, 0.0001114000, -0.008525100, -0.026942300, -0.066129000", \ - "0.0066875000, 0.0058092000, 0.0039279000, -6.29000e-05, -0.008652300, -0.027043800, -0.066142400", \ - "0.0064192000, 0.0055474000, 0.0036955000, -0.000288900, -0.008832500, -0.027141500, -0.066237200", \ - "0.0063743000, 0.0054676000, 0.0035802000, -0.000440100, -0.009153600, -0.027393500, -0.066388800", \ - "0.0066766000, 0.0057764000, 0.0038568000, -0.000281300, -0.008954300, -0.027356900, -0.066526200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0151407000, 0.0160609000, 0.0180421000, 0.0221301000, 0.0308088000, 0.0491867000, 0.0879471000", \ - "0.0150202000, 0.0159239000, 0.0178802000, 0.0220153000, 0.0307109000, 0.0490669000, 0.0879788000", \ - "0.0148494000, 0.0157753000, 0.0177062000, 0.0218587000, 0.0305833000, 0.0490108000, 0.0878217000", \ - "0.0146477000, 0.0155680000, 0.0175400000, 0.0217113000, 0.0304287000, 0.0488967000, 0.0878172000", \ - "0.0145083000, 0.0154417000, 0.0173720000, 0.0215221000, 0.0302827000, 0.0487345000, 0.0877049000", \ - "0.0144507000, 0.0153785000, 0.0173035000, 0.0214515000, 0.0302151000, 0.0486000000, 0.0876499000", \ - "0.0147225000, 0.0156114000, 0.0174986000, 0.0216195000, 0.0302911000, 0.0488752000, 0.0877251000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0054238000, 0.0045421000, 0.0026271000, -0.001427100, -0.010115300, -0.028565800, -0.067795600", \ - "0.0053595000, 0.0044917000, 0.0026094000, -0.001421400, -0.010065600, -0.028491600, -0.067714600", \ - "0.0051786000, 0.0043337000, 0.0025052000, -0.001472300, -0.010059300, -0.028467100, -0.067648400", \ - "0.0048905000, 0.0040617000, 0.0022407000, -0.001683800, -0.010189300, -0.028515200, -0.067645600", \ - "0.0047173000, 0.0038208000, 0.0019189000, -0.001982100, -0.010446200, -0.028675900, -0.067722100", \ - "0.0045625000, 0.0037069000, 0.0018305000, -0.002166700, -0.010769100, -0.028939000, -0.067917300", \ - "0.0050105000, 0.0040826000, 0.0021236000, -0.002006500, -0.010670800, -0.029019900, -0.068118500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0130445000, 0.0139642000, 0.0158939000, 0.0200253000, 0.0287066000, 0.0470414000, 0.0858388000", \ - "0.0128132000, 0.0137487000, 0.0157402000, 0.0198625000, 0.0285618000, 0.0469776000, 0.0858637000", \ - "0.0125728000, 0.0135439000, 0.0155284000, 0.0196668000, 0.0284118000, 0.0468256000, 0.0856558000", \ - "0.0123938000, 0.0133222000, 0.0152910000, 0.0194590000, 0.0282478000, 0.0466944000, 0.0855669000", \ - "0.0124686000, 0.0133759000, 0.0152377000, 0.0193611000, 0.0280563000, 0.0464592000, 0.0855635000", \ - "0.0129913000, 0.0139028000, 0.0158401000, 0.0199873000, 0.0281465000, 0.0464900000, 0.0854242000", \ - "0.0138827000, 0.0147058000, 0.0165188000, 0.0205423000, 0.0290075000, 0.0471806000, 0.0859636000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0084130000, 0.0075431000, 0.0056368000, 0.0016211000, -0.007010500, -0.025371200, -0.064512500", \ - "0.0083166000, 0.0074294000, 0.0055488000, 0.0015367000, -0.007043600, -0.025399700, -0.064520500", \ - "0.0081779000, 0.0072866000, 0.0054153000, 0.0014358000, -0.007129100, -0.025459600, -0.064539300", \ - "0.0079858000, 0.0071026000, 0.0052383000, 0.0012491000, -0.007285800, -0.025566500, -0.064606100", \ - "0.0078274000, 0.0069440000, 0.0051159000, 0.0011335000, -0.007395500, -0.025665200, -0.064711200", \ - "0.0080208000, 0.0070946000, 0.0051754000, 0.0010128000, -0.007608500, -0.025908800, -0.064881200", \ - "0.0087731000, 0.0078409000, 0.0058515000, 0.0016914000, -0.007104400, -0.025709500, -0.064886300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0123882000, 0.0133166000, 0.0152760000, 0.0193892000, 0.0280722000, 0.0464246000, 0.0851104000", \ - "0.0122010000, 0.0131397000, 0.0151335000, 0.0192317000, 0.0279664000, 0.0464282000, 0.0851450000", \ - "0.0119899000, 0.0129430000, 0.0149452000, 0.0191456000, 0.0279440000, 0.0462958000, 0.0850447000", \ - "0.0116931000, 0.0126244000, 0.0146016000, 0.0187858000, 0.0274337000, 0.0459201000, 0.0848927000", \ - "0.0118254000, 0.0127059000, 0.0146341000, 0.0187019000, 0.0273517000, 0.0457870000, 0.0844074000", \ - "0.0122198000, 0.0132086000, 0.0150650000, 0.0190587000, 0.0277137000, 0.0459487000, 0.0849163000", \ - "0.0132766000, 0.0141088000, 0.0159210000, 0.0197989000, 0.0283248000, 0.0464746000, 0.0850368000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0083128000, 0.0074223000, 0.0055434000, 0.0015436000, -0.007049100, -0.025413700, -0.064528000", \ - "0.0081452000, 0.0072623000, 0.0054230000, 0.0014402000, -0.007116100, -0.025449000, -0.064558000", \ - "0.0079712000, 0.0070834000, 0.0052231000, 0.0012926000, -0.007239800, -0.025540800, -0.064609700", \ - "0.0077654000, 0.0068913000, 0.0050053000, 0.0010763000, -0.007446800, -0.025676100, -0.064681900", \ - "0.0076346000, 0.0067139000, 0.0048564000, 0.0008834000, -0.007683000, -0.025881200, -0.064849800", \ - "0.0081535000, 0.0071408000, 0.0052924000, 0.0011663000, -0.007540200, -0.025904800, -0.064963200", \ - "0.0093873000, 0.0083912000, 0.0063832000, 0.0021735000, -0.006724300, -0.025349700, -0.064247600"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010615270, 0.0022536790, 0.0047846820, 0.0101581400, 0.0215662700, 0.0457863500"); - values("0.0091713000, 0.0101442000, 0.0121822000, 0.0163882000, 0.0251437000, 0.0435239000, 0.0822810000", \ - "0.0089068000, 0.0099243000, 0.0119887000, 0.0161795000, 0.0250358000, 0.0435021000, 0.0822990000", \ - "0.0086192000, 0.0095888000, 0.0116808000, 0.0160081000, 0.0247623000, 0.0432516000, 0.0822639000", \ - "0.0084770000, 0.0094262000, 0.0114485000, 0.0155597000, 0.0244569000, 0.0430166000, 0.0819349000", \ - "0.0086292000, 0.0095364000, 0.0114811000, 0.0155987000, 0.0243992000, 0.0427006000, 0.0816719000", \ - "0.0092175000, 0.0101129000, 0.0119892000, 0.0159806000, 0.0245781000, 0.0425812000, 0.0813602000", \ - "0.0106211000, 0.0114152000, 0.0131482000, 0.0170010000, 0.0252612000, 0.0436543000, 0.0825153000"); - } - } - max_capacitance : 0.0457860000; - max_transition : 1.4766590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0658180000, 0.0705788000, 0.0806288000, 0.1006889000, 0.1416765000, 0.2260354000, 0.4020906000", \ - "0.0702334000, 0.0750400000, 0.0849146000, 0.1050902000, 0.1460873000, 0.2304067000, 0.4063448000", \ - "0.0792297000, 0.0841256000, 0.0939931000, 0.1141875000, 0.1551392000, 0.2394214000, 0.4156172000", \ - "0.0968767000, 0.1016938000, 0.1116457000, 0.1317191000, 0.1726977000, 0.2571587000, 0.4333038000", \ - "0.1260062000, 0.1314793000, 0.1432546000, 0.1656608000, 0.2093009000, 0.2946862000, 0.4709025000", \ - "0.1643292000, 0.1719505000, 0.1884445000, 0.2182370000, 0.2730885000, 0.3713276000, 0.5563227000", \ - "0.1899136000, 0.2024299000, 0.2262429000, 0.2728622000, 0.3550528000, 0.4901717000, 0.7168853000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1998522000, 0.2130931000, 0.2400884000, 0.2953663000, 0.4119737000, 0.6562646000, 1.1730796000", \ - "0.2057416000, 0.2184292000, 0.2451573000, 0.3002243000, 0.4171551000, 0.6621436000, 1.1782683000", \ - "0.2173236000, 0.2303875000, 0.2571570000, 0.3128495000, 0.4293858000, 0.6744033000, 1.1911460000", \ - "0.2423707000, 0.2545879000, 0.2822080000, 0.3378350000, 0.4548630000, 0.6998072000, 1.2170636000", \ - "0.2948792000, 0.3074018000, 0.3341960000, 0.3895053000, 0.5065718000, 0.7523270000, 1.2696104000", \ - "0.3948314000, 0.4096227000, 0.4392372000, 0.4995561000, 0.6185409000, 0.8636741000, 1.3810598000", \ - "0.5625593000, 0.5837063000, 0.6213319000, 0.6950707000, 0.8401105000, 1.1129917000, 1.6352476000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0520810000, 0.0577648000, 0.0696171000, 0.0943928000, 0.1462857000, 0.2561014000, 0.4898987000", \ - "0.0520523000, 0.0576719000, 0.0694627000, 0.0941452000, 0.1462511000, 0.2564577000, 0.4892518000", \ - "0.0518595000, 0.0574406000, 0.0693025000, 0.0938655000, 0.1461596000, 0.2561137000, 0.4897527000", \ - "0.0537428000, 0.0590043000, 0.0704555000, 0.0946733000, 0.1458770000, 0.2564546000, 0.4903078000", \ - "0.0666862000, 0.0717014000, 0.0829883000, 0.1058475000, 0.1533616000, 0.2586734000, 0.4891441000", \ - "0.1003900000, 0.1061659000, 0.1180620000, 0.1425573000, 0.1907567000, 0.2898403000, 0.5029633000", \ - "0.1704671000, 0.1778028000, 0.1945614000, 0.2257756000, 0.2810513000, 0.3843768000, 0.5924843000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1606849000, 0.1770929000, 0.2117838000, 0.2843769000, 0.4406698000, 0.7652963000, 1.4547327000", \ - "0.1605487000, 0.1770352000, 0.2111534000, 0.2846493000, 0.4386370000, 0.7646798000, 1.4549753000", \ - "0.1606657000, 0.1769546000, 0.2111801000, 0.2847378000, 0.4387493000, 0.7652087000, 1.4558456000", \ - "0.1605706000, 0.1769299000, 0.2116453000, 0.2843709000, 0.4403602000, 0.7647551000, 1.4551322000", \ - "0.1632146000, 0.1790541000, 0.2124959000, 0.2847378000, 0.4384803000, 0.7644890000, 1.4557524000", \ - "0.1924387000, 0.2076340000, 0.2399682000, 0.3065351000, 0.4514601000, 0.7670760000, 1.4560865000", \ - "0.2615732000, 0.2797339000, 0.3142983000, 0.3870938000, 0.5319389000, 0.8229231000, 1.4739790000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0638465000, 0.0683108000, 0.0775028000, 0.0965570000, 0.1364752000, 0.2202711000, 0.3974128000", \ - "0.0685389000, 0.0729147000, 0.0821578000, 0.1012921000, 0.1411594000, 0.2249839000, 0.4019567000", \ - "0.0772078000, 0.0817616000, 0.0909678000, 0.1101636000, 0.1501959000, 0.2340766000, 0.4111607000", \ - "0.0929858000, 0.0976820000, 0.1072781000, 0.1267231000, 0.1669325000, 0.2511018000, 0.4282453000", \ - "0.1166051000, 0.1225716000, 0.1341990000, 0.1565865000, 0.2006831000, 0.2865178000, 0.4641838000", \ - "0.1427185000, 0.1511922000, 0.1678911000, 0.2000331000, 0.2555932000, 0.3566575000, 0.5450750000", \ - "0.1429524000, 0.1568369000, 0.1843589000, 0.2336710000, 0.3197017000, 0.4605580000, 0.6919222000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1924658000, 0.2046050000, 0.2321733000, 0.2874985000, 0.4041305000, 0.6486133000, 1.1656555000", \ - "0.1964285000, 0.2095515000, 0.2353064000, 0.2913315000, 0.4078929000, 0.6531101000, 1.1695060000", \ - "0.2062866000, 0.2199186000, 0.2467671000, 0.3021786000, 0.4199639000, 0.6644111000, 1.1816331000", \ - "0.2329107000, 0.2454696000, 0.2718842000, 0.3285717000, 0.4455875000, 0.6910991000, 1.2086375000", \ - "0.2924185000, 0.3052927000, 0.3321745000, 0.3881148000, 0.5046311000, 0.7507209000, 1.2686560000", \ - "0.4169188000, 0.4323739000, 0.4624356000, 0.5248736000, 0.6443712000, 0.8899602000, 1.4080578000", \ - "0.6329131000, 0.6537856000, 0.6969972000, 0.7778961000, 0.9307458000, 1.2127990000, 1.7332142000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0436100000, 0.0490158000, 0.0608500000, 0.0856641000, 0.1384312000, 0.2504391000, 0.4866345000", \ - "0.0435424000, 0.0491540000, 0.0607323000, 0.0855090000, 0.1383290000, 0.2499824000, 0.4866057000", \ - "0.0435189000, 0.0490197000, 0.0606967000, 0.0855762000, 0.1383023000, 0.2500757000, 0.4861983000", \ - "0.0463578000, 0.0514924000, 0.0627086000, 0.0866173000, 0.1382805000, 0.2500542000, 0.4866748000", \ - "0.0592281000, 0.0646290000, 0.0758753000, 0.0989730000, 0.1470226000, 0.2538999000, 0.4874281000", \ - "0.0933232000, 0.0994395000, 0.1118845000, 0.1367092000, 0.1851362000, 0.2852781000, 0.5025574000", \ - "0.1642813000, 0.1727325000, 0.1900293000, 0.2207979000, 0.2782533000, 0.3835693000, 0.5925742000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1603386000, 0.1770287000, 0.2116477000, 0.2843644000, 0.4407670000, 0.7652005000, 1.4589195000", \ - "0.1606280000, 0.1766180000, 0.2113212000, 0.2852455000, 0.4389768000, 0.7664624000, 1.4552521000", \ - "0.1607368000, 0.1768887000, 0.2115832000, 0.2842419000, 0.4384806000, 0.7649391000, 1.4545977000", \ - "0.1606788000, 0.1769185000, 0.2116446000, 0.2851032000, 0.4386130000, 0.7650747000, 1.4560532000", \ - "0.1650403000, 0.1803660000, 0.2136457000, 0.2845735000, 0.4391378000, 0.7653050000, 1.4554340000", \ - "0.2068025000, 0.2221133000, 0.2507605000, 0.3133127000, 0.4522934000, 0.7662408000, 1.4566428000", \ - "0.3013705000, 0.3176854000, 0.3520899000, 0.4218635000, 0.5549816000, 0.8359172000, 1.4715248000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0491054000, 0.0530881000, 0.0611720000, 0.0784458000, 0.1148542000, 0.1916887000, 0.3549431000", \ - "0.0537909000, 0.0577554000, 0.0659626000, 0.0833325000, 0.1200355000, 0.1968806000, 0.3617152000", \ - "0.0626347000, 0.0666387000, 0.0751103000, 0.0926848000, 0.1294359000, 0.2065754000, 0.3690367000", \ - "0.0774486000, 0.0821072000, 0.0914297000, 0.1098763000, 0.1468421000, 0.2243725000, 0.3870682000", \ - "0.0969450000, 0.1035828000, 0.1154643000, 0.1388066000, 0.1812486000, 0.2617914000, 0.4254933000", \ - "0.1107672000, 0.1214804000, 0.1398092000, 0.1747440000, 0.2333228000, 0.3357939000, 0.5120152000", \ - "0.0874568000, 0.1039344000, 0.1352510000, 0.1912928000, 0.2850297000, 0.4313435000, 0.6595501000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1606375000, 0.1732215000, 0.1996727000, 0.2550737000, 0.3716412000, 0.6169103000, 1.1338602000", \ - "0.1622841000, 0.1750157000, 0.2025424000, 0.2579580000, 0.3754138000, 0.6196810000, 1.1367431000", \ - "0.1705234000, 0.1845075000, 0.2115236000, 0.2676797000, 0.3847753000, 0.6306338000, 1.1475687000", \ - "0.1963831000, 0.2087057000, 0.2358329000, 0.2916843000, 0.4089939000, 0.6555420000, 1.1729615000", \ - "0.2609183000, 0.2732031000, 0.2991063000, 0.3544872000, 0.4710211000, 0.7164779000, 1.2339832000", \ - "0.4002108000, 0.4139671000, 0.4452661000, 0.5064260000, 0.6230266000, 0.8661197000, 1.3828269000", \ - "0.6268855000, 0.6480356000, 0.6939423000, 0.7836030000, 0.9434287000, 1.2177268000, 1.7265188000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0308873000, 0.0358777000, 0.0466313000, 0.0697787000, 0.1177546000, 0.2211945000, 0.4387017000", \ - "0.0308402000, 0.0359774000, 0.0466577000, 0.0694203000, 0.1179199000, 0.2211650000, 0.4393445000", \ - "0.0310223000, 0.0360542000, 0.0467813000, 0.0696909000, 0.1184597000, 0.2204442000, 0.4384330000", \ - "0.0359359000, 0.0406232000, 0.0503939000, 0.0715393000, 0.1184450000, 0.2207407000, 0.4384473000", \ - "0.0514455000, 0.0563889000, 0.0662549000, 0.0874613000, 0.1305333000, 0.2252409000, 0.4379208000", \ - "0.0878919000, 0.0939680000, 0.1058249000, 0.1295370000, 0.1737494000, 0.2676584000, 0.4570383000", \ - "0.1607027000, 0.1689448000, 0.1854403000, 0.2171854000, 0.2724167000, 0.3697743000, 0.5630615000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.1604071000, 0.1771170000, 0.2112513000, 0.2846502000, 0.4389726000, 0.7648430000, 1.4591607000", \ - "0.1602890000, 0.1766227000, 0.2118071000, 0.2844207000, 0.4388021000, 0.7645707000, 1.4548552000", \ - "0.1602031000, 0.1767948000, 0.2116369000, 0.2843010000, 0.4400120000, 0.7676740000, 1.4582374000", \ - "0.1601119000, 0.1765505000, 0.2110704000, 0.2843508000, 0.4391820000, 0.7652239000, 1.4590074000", \ - "0.1662847000, 0.1814467000, 0.2141255000, 0.2847350000, 0.4387004000, 0.7650575000, 1.4553648000", \ - "0.2225377000, 0.2363130000, 0.2664902000, 0.3289795000, 0.4590890000, 0.7668320000, 1.4553149000", \ - "0.3271969000, 0.3474123000, 0.3872704000, 0.4627961000, 0.6030497000, 0.8585039000, 1.4766585000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0585894000, 0.0635711000, 0.0735105000, 0.0937540000, 0.1348982000, 0.2192439000, 0.3954055000", \ - "0.0625604000, 0.0674493000, 0.0775445000, 0.0978044000, 0.1390319000, 0.2235286000, 0.3996430000", \ - "0.0713982000, 0.0763014000, 0.0863100000, 0.1067478000, 0.1480760000, 0.2326385000, 0.4087403000", \ - "0.0918355000, 0.0969773000, 0.1071599000, 0.1273949000, 0.1686384000, 0.2536220000, 0.4302456000", \ - "0.1250322000, 0.1316551000, 0.1450347000, 0.1696409000, 0.2161746000, 0.3024254000, 0.4794260000", \ - "0.1635650000, 0.1731083000, 0.1928876000, 0.2288488000, 0.2926408000, 0.4009913000, 0.5884977000", \ - "0.1851141000, 0.2002120000, 0.2299653000, 0.2855663000, 0.3831330000, 0.5435142000, 0.7986129000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0465890000, 0.0509992000, 0.0600663000, 0.0792052000, 0.1191585000, 0.2035576000, 0.3814660000", \ - "0.0518602000, 0.0563313000, 0.0655414000, 0.0845933000, 0.1247665000, 0.2090563000, 0.3873685000", \ - "0.0650232000, 0.0693710000, 0.0785876000, 0.0977612000, 0.1380603000, 0.2220522000, 0.4008411000", \ - "0.0968405000, 0.1016544000, 0.1108144000, 0.1299879000, 0.1691190000, 0.2538843000, 0.4323876000", \ - "0.1532351000, 0.1605722000, 0.1753437000, 0.2012626000, 0.2457044000, 0.3285661000, 0.5052073000", \ - "0.2455881000, 0.2583181000, 0.2817656000, 0.3240287000, 0.3943489000, 0.5025039000, 0.6807583000", \ - "0.4004866000, 0.4191633000, 0.4559393000, 0.5228930000, 0.6365753000, 0.8148827000, 1.0734189000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0520529000, 0.0576922000, 0.0694074000, 0.0942718000, 0.1462336000, 0.2559115000, 0.4898545000", \ - "0.0520176000, 0.0575667000, 0.0694951000, 0.0941437000, 0.1460939000, 0.2562228000, 0.4905593000", \ - "0.0514392000, 0.0571339000, 0.0689393000, 0.0938554000, 0.1460167000, 0.2564132000, 0.4891952000", \ - "0.0562732000, 0.0608851000, 0.0717802000, 0.0951370000, 0.1457229000, 0.2558510000, 0.4891947000", \ - "0.0757451000, 0.0811244000, 0.0934266000, 0.1155117000, 0.1588756000, 0.2601913000, 0.4898577000", \ - "0.1178405000, 0.1256285000, 0.1389019000, 0.1651532000, 0.2157351000, 0.3065646000, 0.5094229000", \ - "0.1910540000, 0.2019647000, 0.2233187000, 0.2622430000, 0.3292149000, 0.4400093000, 0.6400124000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0515101000, 0.0579382000, 0.0717705000, 0.1004654000, 0.1600833000, 0.2844007000, 0.5410588000", \ - "0.0514817000, 0.0579432000, 0.0717730000, 0.1004565000, 0.1600828000, 0.2844640000, 0.5405570000", \ - "0.0514570000, 0.0580228000, 0.0717520000, 0.1004636000, 0.1601308000, 0.2845200000, 0.5408355000", \ - "0.0607179000, 0.0658683000, 0.0771774000, 0.1026033000, 0.1600318000, 0.2846974000, 0.5409344000", \ - "0.0996154000, 0.1040775000, 0.1132516000, 0.1312375000, 0.1758453000, 0.2873304000, 0.5409562000", \ - "0.1728158000, 0.1788388000, 0.1913671000, 0.2152053000, 0.2577114000, 0.3423945000, 0.5574093000", \ - "0.3045979000, 0.3133887000, 0.3313469000, 0.3669781000, 0.4301978000, 0.5327614000, 0.7028431000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0513325000, 0.0563278000, 0.0663597000, 0.0866941000, 0.1279005000, 0.2123971000, 0.3885595000", \ - "0.0549199000, 0.0599087000, 0.0701244000, 0.0905815000, 0.1318023000, 0.2163570000, 0.3925853000", \ - "0.0642046000, 0.0691001000, 0.0791213000, 0.0998120000, 0.1413096000, 0.2260889000, 0.4023389000", \ - "0.0881373000, 0.0931456000, 0.1027429000, 0.1223500000, 0.1630014000, 0.2477731000, 0.4243366000", \ - "0.1229883000, 0.1300746000, 0.1442116000, 0.1704030000, 0.2164221000, 0.3010479000, 0.4773295000", \ - "0.1602274000, 0.1718208000, 0.1908123000, 0.2295744000, 0.2979368000, 0.4127075000, 0.5983364000", \ - "0.1856900000, 0.2020013000, 0.2321072000, 0.2913217000, 0.3936052000, 0.5645898000, 0.8299006000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0350590000, 0.0391817000, 0.0478585000, 0.0656652000, 0.1026834000, 0.1805441000, 0.3459807000", \ - "0.0400780000, 0.0443370000, 0.0530261000, 0.0707313000, 0.1081684000, 0.1864176000, 0.3510364000", \ - "0.0530884000, 0.0572566000, 0.0659721000, 0.0838550000, 0.1213324000, 0.1994950000, 0.3650350000", \ - "0.0810027000, 0.0865166000, 0.0968047000, 0.1145965000, 0.1525207000, 0.2309254000, 0.3938178000", \ - "0.1250946000, 0.1340097000, 0.1507218000, 0.1794477000, 0.2257687000, 0.3042718000, 0.4687963000", \ - "0.1948242000, 0.2088766000, 0.2357311000, 0.2825266000, 0.3568778000, 0.4689244000, 0.6402579000", \ - "0.3112301000, 0.3321281000, 0.3726590000, 0.4456812000, 0.5643824000, 0.7463629000, 1.0076809000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0522355000, 0.0577181000, 0.0694336000, 0.0941251000, 0.1460851000, 0.2565339000, 0.4894927000", \ - "0.0520176000, 0.0575946000, 0.0694225000, 0.0940175000, 0.1459927000, 0.2560434000, 0.4906026000", \ - "0.0506409000, 0.0563373000, 0.0685061000, 0.0938096000, 0.1462268000, 0.2561160000, 0.4905888000", \ - "0.0580005000, 0.0628537000, 0.0729542000, 0.0951062000, 0.1454603000, 0.2557454000, 0.4896389000", \ - "0.0819960000, 0.0884185000, 0.0996602000, 0.1218851000, 0.1643700000, 0.2613704000, 0.4898122000", \ - "0.1278146000, 0.1363358000, 0.1534645000, 0.1852614000, 0.2394057000, 0.3287369000, 0.5196172000", \ - "0.2056331000, 0.2199178000, 0.2437269000, 0.2896049000, 0.3657884000, 0.4932632000, 0.6975969000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010615300, 0.0022536800, 0.0047846800, 0.0101581000, 0.0215663000, 0.0457864000"); - values("0.0394183000, 0.0454016000, 0.0581907000, 0.0847595000, 0.1400787000, 0.2549374000, 0.4934914000", \ - "0.0393191000, 0.0453521000, 0.0581844000, 0.0847744000, 0.1399836000, 0.2550766000, 0.4938476000", \ - "0.0406804000, 0.0461228000, 0.0581501000, 0.0847609000, 0.1399900000, 0.2549975000, 0.4938329000", \ - "0.0561659000, 0.0593185000, 0.0684273000, 0.0901421000, 0.1405829000, 0.2551311000, 0.4939322000", \ - "0.0973377000, 0.1012225000, 0.1095783000, 0.1254009000, 0.1634919000, 0.2605845000, 0.4937722000", \ - "0.1699013000, 0.1751436000, 0.1866481000, 0.2094904000, 0.2507986000, 0.3242394000, 0.5164973000", \ - "0.3009759000, 0.3084970000, 0.3243791000, 0.3571918000, 0.4197071000, 0.5212538000, 0.6824825000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311ai_2") { - leakage_power () { - value : 0.0002108000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 6.4908487e-05; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0021916000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0001901000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0073302000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005675000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0066767000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005665000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0045561000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005704000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0066091000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005676000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0045581000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005664000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0045654000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0005671000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0006617000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 7.7712407e-05; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0044394000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0005701000; - when : "A1&A2&A3&B1&!C1"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__o311ai"; - cell_leakage_power : 0.0015795030; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080142000, 0.0080126000, 0.0080089000, 0.0080060000, 0.0079992000, 0.0079834000, 0.0079472000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007993000, -0.007992900, -0.007992800, -0.007993100, -0.007993800, -0.007995400, -0.007999200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046590000; - } - pin ("A2") { - capacitance : 0.0043630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079681000, 0.0079654000, 0.0079591000, 0.0079606000, 0.0079640000, 0.0079719000, 0.0079901000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007943700, -0.007944700, -0.007947100, -0.007941900, -0.007929800, -0.007902100, -0.007838100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046560000; - } - pin ("A3") { - capacitance : 0.0044110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079357000, 0.0079325000, 0.0079250000, 0.0079217000, 0.0079141000, 0.0078964000, 0.0078558000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007935500, -0.007930300, -0.007918400, -0.007920000, -0.007923700, -0.007932300, -0.007952100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047730000; - } - pin ("B1") { - capacitance : 0.0044880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043370000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082524000, 0.0082336000, 0.0081904000, 0.0082013000, 0.0082266000, 0.0082849000, 0.0084194000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008126500, -0.008116200, -0.008092400, -0.008090700, -0.008086600, -0.008077300, -0.008055700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046400000; - } - pin ("C1") { - capacitance : 0.0043780000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0094700000, 0.0094680000, 0.0094636000, 0.0094604000, 0.0094533000, 0.0094367000, 0.0093985000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007227400, -0.007222000, -0.007209500, -0.007196900, -0.007168000, -0.007101200, -0.006947300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044700000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0174359000, 0.0163583000, 0.0138349000, 0.0079477000, -0.005849700, -0.038276300, -0.114486400", \ - "0.0171855000, 0.0161095000, 0.0135782000, 0.0077008000, -0.006099800, -0.038521000, -0.114775300", \ - "0.0168729000, 0.0157981000, 0.0132814000, 0.0073925000, -0.006380500, -0.038810200, -0.115029500", \ - "0.0165226000, 0.0154435000, 0.0129371000, 0.0070832000, -0.006657800, -0.039040200, -0.115267400", \ - "0.0162386000, 0.0151902000, 0.0127187000, 0.0069431000, -0.006799000, -0.039152600, -0.115281000", \ - "0.0163514000, 0.0152764000, 0.0127603000, 0.0066431000, -0.007137800, -0.039399100, -0.115549500", \ - "0.0172650000, 0.0162607000, 0.0136837000, 0.0076217000, -0.006343200, -0.039164100, -0.115431300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0339463000, 0.0350558000, 0.0376151000, 0.0435584000, 0.0574949000, 0.0899691000, 0.1658105000", \ - "0.0336813000, 0.0347896000, 0.0373078000, 0.0433078000, 0.0573039000, 0.0898204000, 0.1654038000", \ - "0.0333671000, 0.0344718000, 0.0370529000, 0.0430445000, 0.0570608000, 0.0895442000, 0.1654279000", \ - "0.0330502000, 0.0341186000, 0.0366874000, 0.0427319000, 0.0568237000, 0.0894652000, 0.1651477000", \ - "0.0327180000, 0.0338135000, 0.0363858000, 0.0424287000, 0.0564457000, 0.0890681000, 0.1649113000", \ - "0.0327550000, 0.0338460000, 0.0363836000, 0.0423914000, 0.0563511000, 0.0889763000, 0.1648005000", \ - "0.0325932000, 0.0337631000, 0.0364767000, 0.0424375000, 0.0567276000, 0.0891329000, 0.1647701000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0138599000, 0.0127770000, 0.0102667000, 0.0043489000, -0.009543700, -0.042137800, -0.118529700", \ - "0.0138075000, 0.0127282000, 0.0102176000, 0.0043225000, -0.009542500, -0.042121700, -0.118470000", \ - "0.0136097000, 0.0125476000, 0.0100692000, 0.0042060000, -0.009626100, -0.042134400, -0.118558500", \ - "0.0131633000, 0.0121117000, 0.0096594000, 0.0038744000, -0.009856500, -0.042292600, -0.118536800", \ - "0.0127051000, 0.0116623000, 0.0092070000, 0.0034503000, -0.010202700, -0.042480900, -0.118632800", \ - "0.0127174000, 0.0116544000, 0.0091344000, 0.0033269000, -0.010760200, -0.042926900, -0.118975100", \ - "0.0135296000, 0.0124564000, 0.0098597000, 0.0039220000, -0.010093700, -0.042731600, -0.119083800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0291421000, 0.0302729000, 0.0328479000, 0.0387904000, 0.0527387000, 0.0851630000, 0.1610611000", \ - "0.0288300000, 0.0299643000, 0.0325544000, 0.0385134000, 0.0524800000, 0.0849907000, 0.1607645000", \ - "0.0285079000, 0.0296231000, 0.0322409000, 0.0382329000, 0.0522865000, 0.0848717000, 0.1605791000", \ - "0.0282077000, 0.0292716000, 0.0319105000, 0.0379088000, 0.0519369000, 0.0845802000, 0.1603389000", \ - "0.0278481000, 0.0289822000, 0.0315368000, 0.0375935000, 0.0516292000, 0.0842871000, 0.1601005000", \ - "0.0277945000, 0.0289224000, 0.0315571000, 0.0377169000, 0.0516325000, 0.0842129000, 0.1600497000", \ - "0.0286486000, 0.0297073000, 0.0321816000, 0.0380774000, 0.0521000000, 0.0844426000, 0.1605142000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0107576000, 0.0096795000, 0.0072296000, 0.0013530000, -0.012535100, -0.045149400, -0.121621200", \ - "0.0105764000, 0.0095626000, 0.0071151000, 0.0013283000, -0.012430100, -0.044988700, -0.121429500", \ - "0.0101849000, 0.0091840000, 0.0068332000, 0.0011425000, -0.012481700, -0.044921900, -0.121300100", \ - "0.0095832000, 0.0086173000, 0.0062661000, 0.0006734000, -0.012787400, -0.045047900, -0.121269500", \ - "0.0091801000, 0.0080863000, 0.0056757000, 7.240000e-05, -0.013350800, -0.045413300, -0.121409500", \ - "0.0091549000, 0.0081378000, 0.0056466000, -0.000139500, -0.013867600, -0.045999300, -0.121857000", \ - "0.0103327000, 0.0093553000, 0.0065458000, 0.0005347000, -0.013506700, -0.045867600, -0.122125400"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0246706000, 0.0257243000, 0.0282982000, 0.0342748000, 0.0483145000, 0.0808224000, 0.1565534000", \ - "0.0242566000, 0.0253279000, 0.0279185000, 0.0339662000, 0.0479918000, 0.0805522000, 0.1562354000", \ - "0.0237991000, 0.0248717000, 0.0275045000, 0.0335396000, 0.0476506000, 0.0802185000, 0.1560219000", \ - "0.0233393000, 0.0244407000, 0.0271150000, 0.0331794000, 0.0473121000, 0.0799936000, 0.1559936000", \ - "0.0234479000, 0.0245607000, 0.0268687000, 0.0328898000, 0.0469607000, 0.0796304000, 0.1556563000", \ - "0.0243119000, 0.0253210000, 0.0283195000, 0.0334439000, 0.0472522000, 0.0796463000, 0.1553411000", \ - "0.0266015000, 0.0276117000, 0.0302216000, 0.0358419000, 0.0493764000, 0.0816561000, 0.1568866000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0177065000, 0.0166440000, 0.0141611000, 0.0083315000, -0.005405300, -0.037774200, -0.114009900", \ - "0.0174733000, 0.0164255000, 0.0139961000, 0.0081616000, -0.005521200, -0.037856600, -0.114012800", \ - "0.0171616000, 0.0161031000, 0.0136514000, 0.0078880000, -0.005731600, -0.037996200, -0.114127200", \ - "0.0167881000, 0.0157374000, 0.0132835000, 0.0074881000, -0.006063300, -0.038220700, -0.114224600", \ - "0.0165173000, 0.0154581000, 0.0129995000, 0.0072797000, -0.006315400, -0.038458900, -0.114384700", \ - "0.0165159000, 0.0154303000, 0.0128926000, 0.0069582000, -0.006756500, -0.038983700, -0.114780200", \ - "0.0180424000, 0.0169345000, 0.0143451000, 0.0082865000, -0.005796000, -0.038726000, -0.114978000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0241403000, 0.0252597000, 0.0278254000, 0.0338353000, 0.0477409000, 0.0802486000, 0.1560351000", \ - "0.0238090000, 0.0248905000, 0.0275011000, 0.0335778000, 0.0476156000, 0.0802366000, 0.1561685000", \ - "0.0233643000, 0.0245155000, 0.0271757000, 0.0333164000, 0.0474089000, 0.0800404000, 0.1560633000", \ - "0.0229086000, 0.0240265000, 0.0266938000, 0.0327334000, 0.0468148000, 0.0795698000, 0.1554987000", \ - "0.0226677000, 0.0237545000, 0.0263131000, 0.0323681000, 0.0463836000, 0.0791544000, 0.1553193000", \ - "0.0236640000, 0.0247414000, 0.0272640000, 0.0330759000, 0.0468495000, 0.0792621000, 0.1551450000", \ - "0.0265517000, 0.0269908000, 0.0290789000, 0.0345663000, 0.0481536000, 0.0807322000, 0.1570991000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0166703000, 0.0156234000, 0.0131736000, 0.0073927000, -0.006311300, -0.038667100, -0.114820800", \ - "0.0163855000, 0.0153533000, 0.0129211000, 0.0071923000, -0.006445600, -0.038750300, -0.114865800", \ - "0.0159810000, 0.0149465000, 0.0125236000, 0.0067995000, -0.006715200, -0.038908000, -0.114972700", \ - "0.0156305000, 0.0145790000, 0.0121487000, 0.0064042000, -0.007111600, -0.039223200, -0.115164300", \ - "0.0153786000, 0.0142871000, 0.0118748000, 0.0061033000, -0.007601400, -0.039628400, -0.115491200", \ - "0.0160079000, 0.0149136000, 0.0123569000, 0.0063393000, -0.007565800, -0.039970500, -0.115805200", \ - "0.0180849000, 0.0169628000, 0.0143463000, 0.0081624000, -0.006156600, -0.039206800, -0.115669800"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011707640, 0.0027413770, 0.0064190120, 0.0150303000, 0.0351938700, 0.0824074400"); - values("0.0172613000, 0.0184662000, 0.0212325000, 0.0274634000, 0.0415534000, 0.0740849000, 0.1498876000", \ - "0.0167194000, 0.0179547000, 0.0207957000, 0.0271277000, 0.0413859000, 0.0740236000, 0.1499000000", \ - "0.0162723000, 0.0174726000, 0.0202678000, 0.0265227000, 0.0409198000, 0.0737419000, 0.1496817000", \ - "0.0159333000, 0.0170842000, 0.0198142000, 0.0259226000, 0.0402525000, 0.0732897000, 0.1496777000", \ - "0.0159189000, 0.0170134000, 0.0195597000, 0.0256356000, 0.0397781000, 0.0726041000, 0.1489193000", \ - "0.0170945000, 0.0181585000, 0.0206552000, 0.0265931000, 0.0403616000, 0.0727861000, 0.1488589000", \ - "0.0202437000, 0.0211120000, 0.0229212000, 0.0284189000, 0.0418089000, 0.0743023000, 0.1486601000"); - } - } - max_capacitance : 0.0824070000; - max_transition : 1.4975910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0755979000, 0.0793291000, 0.0877336000, 0.1065603000, 0.1474960000, 0.2394180000, 0.4492291000", \ - "0.0798306000, 0.0835592000, 0.0920270000, 0.1107677000, 0.1517246000, 0.2436765000, 0.4535547000", \ - "0.0886426000, 0.0922343000, 0.1006163000, 0.1193490000, 0.1604268000, 0.2525295000, 0.4619508000", \ - "0.1050116000, 0.1087277000, 0.1170276000, 0.1356460000, 0.1768702000, 0.2687215000, 0.4785808000", \ - "0.1315816000, 0.1358972000, 0.1451351000, 0.1657961000, 0.2090988000, 0.3019090000, 0.5117087000", \ - "0.1677062000, 0.1729134000, 0.1855539000, 0.2109026000, 0.2630947000, 0.3679929000, 0.5858369000", \ - "0.1903092000, 0.1978016000, 0.2164179000, 0.2546512000, 0.3309405000, 0.4696760000, 0.7278135000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.2162915000, 0.2255374000, 0.2452820000, 0.2900322000, 0.3949067000, 0.6347398000, 1.1917151000", \ - "0.2210860000, 0.2299081000, 0.2495980000, 0.2943291000, 0.3989396000, 0.6389021000, 1.1964301000", \ - "0.2322539000, 0.2413525000, 0.2613535000, 0.3062952000, 0.4113211000, 0.6519851000, 1.2089830000", \ - "0.2585966000, 0.2666287000, 0.2868219000, 0.3327782000, 0.4376413000, 0.6779259000, 1.2362616000", \ - "0.3118688000, 0.3205625000, 0.3405610000, 0.3862249000, 0.4900015000, 0.7317675000, 1.2899517000", \ - "0.4142065000, 0.4236906000, 0.4457345000, 0.4951595000, 0.6024627000, 0.8429379000, 1.4013100000", \ - "0.5883796000, 0.6005823000, 0.6267198000, 0.6869481000, 0.8165768000, 1.0856912000, 1.6506171000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0616031000, 0.0657207000, 0.0753069000, 0.0979298000, 0.1493780000, 0.2689962000, 0.5502057000", \ - "0.0614379000, 0.0656023000, 0.0751310000, 0.0977711000, 0.1493086000, 0.2692946000, 0.5509723000", \ - "0.0610514000, 0.0653605000, 0.0750111000, 0.0974592000, 0.1492211000, 0.2695527000, 0.5513838000", \ - "0.0624126000, 0.0664770000, 0.0759093000, 0.0980316000, 0.1491829000, 0.2689651000, 0.5510870000", \ - "0.0729671000, 0.0768099000, 0.0858393000, 0.1073952000, 0.1551934000, 0.2716858000, 0.5505700000", \ - "0.1033191000, 0.1075634000, 0.1172020000, 0.1386171000, 0.1871527000, 0.2976926000, 0.5617028000", \ - "0.1725668000, 0.1783083000, 0.1904286000, 0.2160909000, 0.2715928000, 0.3835385000, 0.6367987000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.1661563000, 0.1768441000, 0.2027920000, 0.2615131000, 0.3994478000, 0.7224272000, 1.4746138000", \ - "0.1660326000, 0.1769773000, 0.2024864000, 0.2615935000, 0.3998395000, 0.7220891000, 1.4745968000", \ - "0.1660489000, 0.1768705000, 0.2027618000, 0.2615418000, 0.3998289000, 0.7219909000, 1.4745857000", \ - "0.1662552000, 0.1767965000, 0.2022754000, 0.2614723000, 0.4010302000, 0.7219401000, 1.4740821000", \ - "0.1676597000, 0.1782106000, 0.2028927000, 0.2618875000, 0.4003211000, 0.7217535000, 1.4748472000", \ - "0.1938297000, 0.2041761000, 0.2282053000, 0.2828625000, 0.4125285000, 0.7246867000, 1.4750953000", \ - "0.2580742000, 0.2693632000, 0.2955916000, 0.3550208000, 0.4880538000, 0.7796857000, 1.4914909000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0688901000, 0.0720182000, 0.0795237000, 0.0961837000, 0.1344733000, 0.2227728000, 0.4276840000", \ - "0.0737082000, 0.0767901000, 0.0841451000, 0.1007865000, 0.1391379000, 0.2274287000, 0.4326222000", \ - "0.0822595000, 0.0854522000, 0.0930215000, 0.1095796000, 0.1479793000, 0.2363995000, 0.4416425000", \ - "0.0970329000, 0.1004597000, 0.1082016000, 0.1253283000, 0.1639953000, 0.2526827000, 0.4580977000", \ - "0.1191150000, 0.1231130000, 0.1317408000, 0.1512380000, 0.1932716000, 0.2839433000, 0.4899158000", \ - "0.1426169000, 0.1476722000, 0.1599043000, 0.1872057000, 0.2396615000, 0.3444815000, 0.5601822000", \ - "0.1378059000, 0.1469102000, 0.1662841000, 0.2082497000, 0.2878088000, 0.4313273000, 0.6900055000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.1980034000, 0.2072835000, 0.2272945000, 0.2719606000, 0.3768413000, 0.6165133000, 1.1736971000", \ - "0.2009121000, 0.2101261000, 0.2303748000, 0.2751472000, 0.3800643000, 0.6198702000, 1.1771378000", \ - "0.2109306000, 0.2195603000, 0.2404708000, 0.2863076000, 0.3905565000, 0.6304413000, 1.1884626000", \ - "0.2356973000, 0.2441588000, 0.2650305000, 0.3105245000, 0.4156478000, 0.6564222000, 1.2145491000", \ - "0.2912898000, 0.3001106000, 0.3196319000, 0.3655413000, 0.4693194000, 0.7109308000, 1.2694472000", \ - "0.4025458000, 0.4130274000, 0.4376969000, 0.4904834000, 0.5990824000, 0.8397167000, 1.3987810000", \ - "0.6014412000, 0.6150252000, 0.6462521000, 0.7144151000, 0.8570119000, 1.1329365000, 1.7007438000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0473262000, 0.0513200000, 0.0605571000, 0.0823202000, 0.1333812000, 0.2527120000, 0.5317041000", \ - "0.0472755000, 0.0512034000, 0.0606027000, 0.0822553000, 0.1331642000, 0.2527255000, 0.5315082000", \ - "0.0472658000, 0.0513084000, 0.0604681000, 0.0824033000, 0.1333089000, 0.2523442000, 0.5321711000", \ - "0.0495553000, 0.0532690000, 0.0621757000, 0.0832418000, 0.1334861000, 0.2523353000, 0.5318516000", \ - "0.0605997000, 0.0644113000, 0.0731690000, 0.0940219000, 0.1419269000, 0.2559289000, 0.5314049000", \ - "0.0922902000, 0.0964620000, 0.1059202000, 0.1276567000, 0.1749285000, 0.2845913000, 0.5442323000", \ - "0.1619996000, 0.1677396000, 0.1797966000, 0.2071707000, 0.2616908000, 0.3721087000, 0.6208933000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.1662182000, 0.1769852000, 0.2027986000, 0.2615501000, 0.3997566000, 0.7223063000, 1.4746029000", \ - "0.1662172000, 0.1770091000, 0.2027898000, 0.2615340000, 0.3998137000, 0.7223274000, 1.4745651000", \ - "0.1662139000, 0.1771353000, 0.2023817000, 0.2615636000, 0.4010922000, 0.7218004000, 1.4736991000", \ - "0.1661202000, 0.1768567000, 0.2027109000, 0.2614447000, 0.3996834000, 0.7228101000, 1.4759617000", \ - "0.1715075000, 0.1817125000, 0.2061480000, 0.2625731000, 0.3998095000, 0.7217195000, 1.4748243000", \ - "0.2087003000, 0.2187316000, 0.2438207000, 0.2946339000, 0.4189423000, 0.7264866000, 1.4750203000", \ - "0.2971915000, 0.3088960000, 0.3357331000, 0.3931964000, 0.5243261000, 0.7947853000, 1.4909370000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0521832000, 0.0549080000, 0.0615127000, 0.0766088000, 0.1113430000, 0.1923424000, 0.3828936000", \ - "0.0565193000, 0.0594997000, 0.0660468000, 0.0811937000, 0.1163836000, 0.1976158000, 0.3867495000", \ - "0.0649644000, 0.0678946000, 0.0746768000, 0.0901731000, 0.1256126000, 0.2071241000, 0.3963203000", \ - "0.0785149000, 0.0818101000, 0.0892613000, 0.1056433000, 0.1415313000, 0.2235349000, 0.4133622000", \ - "0.0955277000, 0.0998766000, 0.1091898000, 0.1292668000, 0.1700638000, 0.2555219000, 0.4461687000", \ - "0.1052549000, 0.1119889000, 0.1266910000, 0.1556092000, 0.2112244000, 0.3152833000, 0.5190398000", \ - "0.0750250000, 0.0879584000, 0.1101132000, 0.1573510000, 0.2447668000, 0.3981506000, 0.6516205000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.1630202000, 0.1715450000, 0.1913503000, 0.2359751000, 0.3400364000, 0.5804466000, 1.1382594000", \ - "0.1648855000, 0.1734349000, 0.1932927000, 0.2387690000, 0.3427565000, 0.5829383000, 1.1408079000", \ - "0.1727386000, 0.1815295000, 0.2016393000, 0.2471942000, 0.3523302000, 0.5931722000, 1.1509291000", \ - "0.1965807000, 0.2048657000, 0.2252535000, 0.2704175000, 0.3760260000, 0.6168751000, 1.1754161000", \ - "0.2596108000, 0.2681785000, 0.2873560000, 0.3328336000, 0.4370837000, 0.6783764000, 1.2371286000", \ - "0.3944407000, 0.4040303000, 0.4294748000, 0.4792665000, 0.5850319000, 0.8227900000, 1.3799890000", \ - "0.6123905000, 0.6273722000, 0.6634298000, 0.7347695000, 0.8836855000, 1.1670492000, 1.7146966000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0316781000, 0.0352782000, 0.0439344000, 0.0642332000, 0.1112604000, 0.2212632000, 0.4797668000", \ - "0.0315899000, 0.0353298000, 0.0438113000, 0.0639598000, 0.1116279000, 0.2218913000, 0.4788949000", \ - "0.0318028000, 0.0354172000, 0.0440245000, 0.0641121000, 0.1116103000, 0.2220865000, 0.4782087000", \ - "0.0360438000, 0.0394225000, 0.0473860000, 0.0660906000, 0.1118190000, 0.2214827000, 0.4800624000", \ - "0.0490642000, 0.0526621000, 0.0604965000, 0.0794262000, 0.1228967000, 0.2260792000, 0.4794957000", \ - "0.0828665000, 0.0870759000, 0.0961666000, 0.1166851000, 0.1594722000, 0.2609567000, 0.4943607000", \ - "0.1527544000, 0.1591282000, 0.1712008000, 0.1971505000, 0.2496454000, 0.3590292000, 0.5880040000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.1662995000, 0.1770170000, 0.2021397000, 0.2613230000, 0.4001202000, 0.7218336000, 1.4760231000", \ - "0.1662218000, 0.1769320000, 0.2021720000, 0.2621652000, 0.3997374000, 0.7217187000, 1.4737507000", \ - "0.1661280000, 0.1766334000, 0.2025861000, 0.2614649000, 0.3997932000, 0.7215595000, 1.4797606000", \ - "0.1653175000, 0.1761830000, 0.2021118000, 0.2618608000, 0.4006079000, 0.7221900000, 1.4747028000", \ - "0.1713334000, 0.1813895000, 0.2045536000, 0.2621353000, 0.3993604000, 0.7225670000, 1.4739764000", \ - "0.2236873000, 0.2345876000, 0.2610943000, 0.3093751000, 0.4258189000, 0.7238841000, 1.4759227000", \ - "0.3213642000, 0.3362721000, 0.3700948000, 0.4377270000, 0.5714159000, 0.8296243000, 1.4975913000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0665245000, 0.0702528000, 0.0787747000, 0.0976125000, 0.1388440000, 0.2308513000, 0.4407100000", \ - "0.0704223000, 0.0741041000, 0.0826562000, 0.1015128000, 0.1430984000, 0.2350813000, 0.4447531000", \ - "0.0785000000, 0.0821824000, 0.0908170000, 0.1097256000, 0.1513383000, 0.2435520000, 0.4535892000", \ - "0.0975312000, 0.1015033000, 0.1099321000, 0.1284334000, 0.1698145000, 0.2623745000, 0.4726494000", \ - "0.1308140000, 0.1350719000, 0.1450138000, 0.1676344000, 0.2126314000, 0.3068737000, 0.5174790000", \ - "0.1721767000, 0.1785407000, 0.1931023000, 0.2230164000, 0.2835969000, 0.3967555000, 0.6193634000", \ - "0.1981748000, 0.2078669000, 0.2299495000, 0.2763161000, 0.3683205000, 0.5325500000, 0.8152191000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0453814000, 0.0481331000, 0.0545763000, 0.0692175000, 0.1030668000, 0.1815915000, 0.3647212000", \ - "0.0507545000, 0.0533764000, 0.0599218000, 0.0747026000, 0.1089295000, 0.1870979000, 0.3703314000", \ - "0.0639466000, 0.0667417000, 0.0732933000, 0.0881922000, 0.1224436000, 0.2015913000, 0.3839482000", \ - "0.0956234000, 0.0987592000, 0.1054640000, 0.1199876000, 0.1544390000, 0.2326535000, 0.4147431000", \ - "0.1515609000, 0.1565611000, 0.1674212000, 0.1894803000, 0.2297456000, 0.3087161000, 0.4915098000", \ - "0.2426157000, 0.2506101000, 0.2681921000, 0.3036069000, 0.3688717000, 0.4792012000, 0.6666975000", \ - "0.3967623000, 0.4087815000, 0.4354149000, 0.4908858000, 0.5956520000, 0.7748465000, 1.0515816000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0610494000, 0.0654163000, 0.0750337000, 0.0975799000, 0.1491463000, 0.2692706000, 0.5506878000", \ - "0.0610993000, 0.0652159000, 0.0751209000, 0.0975195000, 0.1492863000, 0.2689727000, 0.5510444000", \ - "0.0603354000, 0.0647511000, 0.0744193000, 0.0972789000, 0.1490686000, 0.2688359000, 0.5505532000", \ - "0.0636757000, 0.0675774000, 0.0766586000, 0.0981560000, 0.1486655000, 0.2690990000, 0.5507482000", \ - "0.0806536000, 0.0847966000, 0.0942010000, 0.1146737000, 0.1596415000, 0.2725340000, 0.5505427000", \ - "0.1213463000, 0.1249244000, 0.1361252000, 0.1600368000, 0.2091683000, 0.3119424000, 0.5661406000", \ - "0.1954157000, 0.2020705000, 0.2179514000, 0.2489786000, 0.3150188000, 0.4329964000, 0.6750286000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0494870000, 0.0536271000, 0.0633528000, 0.0856894000, 0.1366447000, 0.2533316000, 0.5195462000", \ - "0.0494623000, 0.0536235000, 0.0633637000, 0.0857004000, 0.1366826000, 0.2532162000, 0.5200085000", \ - "0.0494044000, 0.0535962000, 0.0632889000, 0.0857028000, 0.1367144000, 0.2535114000, 0.5197298000", \ - "0.0589034000, 0.0622092000, 0.0701204000, 0.0892447000, 0.1368327000, 0.2534409000, 0.5199132000", \ - "0.0978510000, 0.1005939000, 0.1068788000, 0.1204571000, 0.1567518000, 0.2582735000, 0.5199859000", \ - "0.1717177000, 0.1755647000, 0.1843724000, 0.2033762000, 0.2408917000, 0.3181504000, 0.5370723000", \ - "0.3074477000, 0.3127213000, 0.3243873000, 0.3508326000, 0.4084366000, 0.5108555000, 0.6903783000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0572728000, 0.0610824000, 0.0697618000, 0.0886538000, 0.1300532000, 0.2222040000, 0.4320255000", \ - "0.0608162000, 0.0646575000, 0.0732741000, 0.0924901000, 0.1339791000, 0.2263404000, 0.4360881000", \ - "0.0701053000, 0.0739469000, 0.0824571000, 0.1015845000, 0.1435667000, 0.2359169000, 0.4461385000", \ - "0.0955120000, 0.0988472000, 0.1065754000, 0.1247066000, 0.1655764000, 0.2589481000, 0.4694143000", \ - "0.1358417000, 0.1409066000, 0.1519454000, 0.1755800000, 0.2203560000, 0.3124154000, 0.5226048000", \ - "0.1825842000, 0.1900243000, 0.2064873000, 0.2409443000, 0.3084202000, 0.4305765000, 0.6485180000", \ - "0.2210049000, 0.2320041000, 0.2565609000, 0.3059380000, 0.4084285000, 0.5911315000, 0.9021344000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0346184000, 0.0375440000, 0.0440704000, 0.0588417000, 0.0923472000, 0.1701361000, 0.3495990000", \ - "0.0394092000, 0.0423561000, 0.0490006000, 0.0640204000, 0.0978560000, 0.1759001000, 0.3559299000", \ - "0.0524225000, 0.0552823000, 0.0617198000, 0.0766673000, 0.1107983000, 0.1883156000, 0.3681524000", \ - "0.0794924000, 0.0834477000, 0.0917365000, 0.1074643000, 0.1415058000, 0.2194914000, 0.4009744000", \ - "0.1218624000, 0.1281588000, 0.1414826000, 0.1675003000, 0.2135165000, 0.2928545000, 0.4737150000", \ - "0.1890721000, 0.1995165000, 0.2202493000, 0.2618454000, 0.3350853000, 0.4532974000, 0.6433906000", \ - "0.3014050000, 0.3167235000, 0.3477980000, 0.4124747000, 0.5280859000, 0.7195241000, 1.0091002000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0613147000, 0.0654948000, 0.0750163000, 0.0974474000, 0.1492015000, 0.2694160000, 0.5507336000", \ - "0.0612905000, 0.0653468000, 0.0750398000, 0.0976751000, 0.1491658000, 0.2694955000, 0.5506086000", \ - "0.0590638000, 0.0634544000, 0.0739128000, 0.0969776000, 0.1491540000, 0.2690035000, 0.5501105000", \ - "0.0642259000, 0.0679348000, 0.0765630000, 0.0974581000, 0.1479444000, 0.2688432000, 0.5501630000", \ - "0.0883722000, 0.0928450000, 0.1032907000, 0.1240927000, 0.1657551000, 0.2726904000, 0.5504227000", \ - "0.1347848000, 0.1409436000, 0.1542796000, 0.1817973000, 0.2350307000, 0.3364422000, 0.5728702000", \ - "0.2151940000, 0.2248139000, 0.2454947000, 0.2863809000, 0.3628893000, 0.4982786000, 0.7434969000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011707600, 0.0027413800, 0.0064190100, 0.0150303000, 0.0351939000, 0.0824074000"); - values("0.0393027000, 0.0433981000, 0.0530054000, 0.0752842000, 0.1256260000, 0.2406197000, 0.5038658000", \ - "0.0392116000, 0.0434275000, 0.0530632000, 0.0753115000, 0.1255956000, 0.2406230000, 0.5036123000", \ - "0.0406946000, 0.0443340000, 0.0532224000, 0.0752736000, 0.1255911000, 0.2406104000, 0.5037931000", \ - "0.0564631000, 0.0586151000, 0.0648942000, 0.0823808000, 0.1267835000, 0.2405597000, 0.5039273000", \ - "0.0994369000, 0.1017534000, 0.1077336000, 0.1206782000, 0.1526307000, 0.2475348000, 0.5038380000", \ - "0.1751118000, 0.1784455000, 0.1863121000, 0.2041008000, 0.2418998000, 0.3158415000, 0.5257771000", \ - "0.3164989000, 0.3202624000, 0.3301164000, 0.3535723000, 0.4079175000, 0.5118534000, 0.6884538000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o311ai_4") { - leakage_power () { - value : 0.0004445000; - when : "!A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0001411000; - when : "!A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0046112000; - when : "!A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0004457000; - when : "!A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0015094000; - when : "!A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "!A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0094520000; - when : "!A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0019318000; - when : "!A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0015094000; - when : "!A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "!A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0083034000; - when : "!A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0019249000; - when : "!A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0015094000; - when : "!A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "!A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0059320000; - when : "!A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0019323000; - when : "!A1&A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0015095000; - when : "A1&!A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "A1&!A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0080947000; - when : "A1&!A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0019325000; - when : "A1&!A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0015094000; - when : "A1&!A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "A1&!A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0059213000; - when : "A1&!A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0019296000; - when : "A1&!A2&A3&B1&!C1"; - } - leakage_power () { - value : 0.0015094000; - when : "A1&A2&!A3&!B1&C1"; - } - leakage_power () { - value : 0.0001779000; - when : "A1&A2&!A3&!B1&!C1"; - } - leakage_power () { - value : 0.0064565000; - when : "A1&A2&!A3&B1&C1"; - } - leakage_power () { - value : 0.0019209000; - when : "A1&A2&!A3&B1&!C1"; - } - leakage_power () { - value : 0.0015221000; - when : "A1&A2&A3&!B1&C1"; - } - leakage_power () { - value : 0.0001875000; - when : "A1&A2&A3&!B1&!C1"; - } - leakage_power () { - value : 0.0484985000; - when : "A1&A2&A3&B1&C1"; - } - leakage_power () { - value : 0.0019247000; - when : "A1&A2&A3&B1&!C1"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__o311ai"; - cell_leakage_power : 0.0038634690; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0086430000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157519000, 0.0157540000, 0.0157589000, 0.0157457000, 0.0157153000, 0.0156453000, 0.0154838000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015748900, -0.015744900, -0.015735600, -0.015733400, -0.015728400, -0.015716900, -0.015690300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090850000; - } - pin ("A2") { - capacitance : 0.0084510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157425000, 0.0157414000, 0.0157388000, 0.0157425000, 0.0157508000, 0.0157700000, 0.0158143000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015746800, -0.015742700, -0.015733100, -0.015735500, -0.015741000, -0.015753700, -0.015782800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090570000; - } - pin ("A3") { - capacitance : 0.0085460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158197000, 0.0158180000, 0.0158139000, 0.0158086000, 0.0157964000, 0.0157682000, 0.0157032000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015833100, -0.015824500, -0.015804500, -0.015807000, -0.015812900, -0.015826400, -0.015857600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0092510000; - } - pin ("B1") { - capacitance : 0.0084630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161095000, 0.0160418000, 0.0158856000, 0.0159158000, 0.0159853000, 0.0161455000, 0.0165149000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015685200, -0.015658900, -0.015598300, -0.015594600, -0.015586200, -0.015566700, -0.015521700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087460000; - } - pin ("C1") { - capacitance : 0.0084520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0182668000, 0.0182662000, 0.0182648000, 0.0182653000, 0.0182667000, 0.0182697000, 0.0182768000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.013007800, -0.013026000, -0.013068000, -0.013032300, -0.012950000, -0.012760300, -0.012323200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086220000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1) | (!C1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0259144000, 0.0246699000, 0.0214833000, 0.0131553000, -0.008143700, -0.062959100, -0.204026400", \ - "0.0258092000, 0.0245850000, 0.0213428000, 0.0130749000, -0.008215600, -0.063030700, -0.204012300", \ - "0.0254154000, 0.0241633000, 0.0209905000, 0.0127951000, -0.008398700, -0.063140500, -0.204093400", \ - "0.0244836000, 0.0232809000, 0.0201541000, 0.0120805000, -0.008900200, -0.063431100, -0.204220300", \ - "0.0234882000, 0.0222805000, 0.0192047000, 0.0112164000, -0.009674200, -0.063887200, -0.204399800", \ - "0.0236371000, 0.0222865000, 0.0191288000, 0.0109222000, -0.010602800, -0.064734100, -0.204977100", \ - "0.0249949000, 0.0236909000, 0.0204192000, 0.0120355000, -0.009408300, -0.064291300, -0.205236600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0539609000, 0.0552516000, 0.0584239000, 0.0668365000, 0.0883244000, 0.1430177000, 0.2829275000", \ - "0.0532932000, 0.0545654000, 0.0579221000, 0.0663187000, 0.0879335000, 0.1428341000, 0.2827072000", \ - "0.0527199000, 0.0540019000, 0.0573326000, 0.0659151000, 0.0874041000, 0.1423404000, 0.2821693000", \ - "0.0521622000, 0.0534751000, 0.0567310000, 0.0652213000, 0.0868992000, 0.1419454000, 0.2820064000", \ - "0.0514611000, 0.0527972000, 0.0560650000, 0.0645112000, 0.0861859000, 0.1412188000, 0.2813866000", \ - "0.0511769000, 0.0525521000, 0.0558053000, 0.0643902000, 0.0860960000, 0.1408905000, 0.2809660000", \ - "0.0523865000, 0.0536427000, 0.0568887000, 0.0651290000, 0.0866349000, 0.1411920000, 0.2818962000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0193992000, 0.0181894000, 0.0149875000, 0.0067812000, -0.014525900, -0.069452800, -0.210662000", \ - "0.0189880000, 0.0178234000, 0.0148095000, 0.0067285000, -0.014344800, -0.069186400, -0.210304800", \ - "0.0182108000, 0.0170854000, 0.0141506000, 0.0063278000, -0.014475000, -0.069009900, -0.209973100", \ - "0.0171005000, 0.0159590000, 0.0130647000, 0.0053748000, -0.015071600, -0.069188800, -0.209861600", \ - "0.0161605000, 0.0149893000, 0.0119457000, 0.0041880000, -0.016152400, -0.069868800, -0.210072200", \ - "0.0162760000, 0.0150295000, 0.0119269000, 0.0038384000, -0.017094900, -0.071061600, -0.210913200", \ - "0.0180847000, 0.0168115000, 0.0134103000, 0.0048911000, -0.016516300, -0.071115300, -0.211546800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0454022000, 0.0466959000, 0.0498587000, 0.0583014000, 0.0797965000, 0.1346684000, 0.2743759000", \ - "0.0445674000, 0.0458551000, 0.0492312000, 0.0577973000, 0.0792375000, 0.1341103000, 0.2737774000", \ - "0.0437462000, 0.0450389000, 0.0483180000, 0.0569090000, 0.0785614000, 0.1337175000, 0.2736591000", \ - "0.0426473000, 0.0440199000, 0.0474310000, 0.0559776000, 0.0776939000, 0.1330202000, 0.2735346000", \ - "0.0421602000, 0.0434355000, 0.0467827000, 0.0552757000, 0.0769923000, 0.1319448000, 0.2725526000", \ - "0.0441523000, 0.0454359000, 0.0487162000, 0.0572141000, 0.0774881000, 0.1326394000, 0.2723474000", \ - "0.0483157000, 0.0514975000, 0.0533843000, 0.0607306000, 0.0818514000, 0.1364915000, 0.2735825000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0326593000, 0.0314531000, 0.0282905000, 0.0201088000, -0.000990300, -0.055492200, -0.196179700", \ - "0.0322197000, 0.0310090000, 0.0278865000, 0.0197832000, -0.001217600, -0.055627100, -0.196147900", \ - "0.0315727000, 0.0304016000, 0.0272523000, 0.0191995000, -0.001672400, -0.055881500, -0.196402600", \ - "0.0309124000, 0.0296604000, 0.0265379000, 0.0184302000, -0.002346800, -0.056400600, -0.196581600", \ - "0.0303235000, 0.0291047000, 0.0260023000, 0.0179616000, -0.002850300, -0.056861100, -0.196991600", \ - "0.0304319000, 0.0291658000, 0.0259449000, 0.0175882000, -0.003795600, -0.057860300, -0.197705100", \ - "0.0329523000, 0.0316668000, 0.0283822000, 0.0197964000, -0.001927600, -0.057447100, -0.198136200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0454258000, 0.0467328000, 0.0500386000, 0.0585245000, 0.0800150000, 0.1347229000, 0.2747592000", \ - "0.0446580000, 0.0460092000, 0.0494242000, 0.0580121000, 0.0797650000, 0.1347690000, 0.2748537000", \ - "0.0435400000, 0.0449148000, 0.0483608000, 0.0571022000, 0.0791166000, 0.1344013000, 0.2747915000", \ - "0.0425452000, 0.0439198000, 0.0473042000, 0.0561027000, 0.0781733000, 0.1338296000, 0.2742179000", \ - "0.0421422000, 0.0434165000, 0.0466942000, 0.0551154000, 0.0766225000, 0.1321667000, 0.2729844000", \ - "0.0435506000, 0.0447417000, 0.0479210000, 0.0561751000, 0.0777894000, 0.1327852000, 0.2732465000", \ - "0.0475208000, 0.0485346000, 0.0513560000, 0.0590536000, 0.0803429000, 0.1346913000, 0.2755295000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0294350000, 0.0282345000, 0.0251869000, 0.0171347000, -0.003831800, -0.058246900, -0.198794800", \ - "0.0289387000, 0.0277518000, 0.0246665000, 0.0167054000, -0.004112800, -0.058386100, -0.198835300", \ - "0.0283236000, 0.0271502000, 0.0240422000, 0.0160723000, -0.004600100, -0.058658500, -0.198961800", \ - "0.0276439000, 0.0264370000, 0.0234201000, 0.0153203000, -0.005372400, -0.059319600, -0.199349400", \ - "0.0275898000, 0.0263425000, 0.0231706000, 0.0150307000, -0.006075100, -0.060002500, -0.199849500", \ - "0.0287470000, 0.0274371000, 0.0241268000, 0.0158104000, -0.005757400, -0.060369000, -0.200640200", \ - "0.0331367000, 0.0318118000, 0.0282887000, 0.0195936000, -0.002341000, -0.057307800, -0.200541700"); - } - related_pin : "C1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0296620000, 0.0311543000, 0.0348923000, 0.0439034000, 0.0658449000, 0.1208769000, 0.2610498000", \ - "0.0288112000, 0.0302780000, 0.0340111000, 0.0432649000, 0.0655110000, 0.1208201000, 0.2614442000", \ - "0.0280518000, 0.0294661000, 0.0331281000, 0.0421667000, 0.0648344000, 0.1204438000, 0.2609844000", \ - "0.0275500000, 0.0288891000, 0.0324058000, 0.0412953000, 0.0633090000, 0.1192353000, 0.2603212000", \ - "0.0278005000, 0.0290466000, 0.0323147000, 0.0407000000, 0.0622681000, 0.1179604000, 0.2592147000", \ - "0.0302867000, 0.0314892000, 0.0346614000, 0.0427258000, 0.0634416000, 0.1190671000, 0.2592667000", \ - "0.0365005000, 0.0372048000, 0.0398409000, 0.0470354000, 0.0669571000, 0.1209372000, 0.2618687000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0322443000, 0.0309936000, 0.0277653000, 0.0194648000, -0.001758200, -0.056329500, -0.196963900", \ - "0.0317545000, 0.0304964000, 0.0272823000, 0.0189620000, -0.002247300, -0.056814100, -0.197467400", \ - "0.0311953000, 0.0299153000, 0.0266879000, 0.0184313000, -0.002777800, -0.057346100, -0.197965800", \ - "0.0305324000, 0.0292707000, 0.0260652000, 0.0178351000, -0.003314900, -0.057812300, -0.198451600", \ - "0.0301175000, 0.0288682000, 0.0255760000, 0.0175089000, -0.003570200, -0.058060600, -0.198587900", \ - "0.0301821000, 0.0288928000, 0.0256263000, 0.0172333000, -0.004253600, -0.058567200, -0.199044600", \ - "0.0317049000, 0.0304852000, 0.0272132000, 0.0188521000, -0.002805400, -0.057941100, -0.198880700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012831560, 0.0032929770, 0.0084508050, 0.0216874000, 0.0556566200, 0.1428322000"); - values("0.0627872000, 0.0640822000, 0.0672200000, 0.0756744000, 0.0971196000, 0.1519473000, 0.2917186000", \ - "0.0623287000, 0.0636293000, 0.0669368000, 0.0752494000, 0.0967308000, 0.1515424000, 0.2913489000", \ - "0.0618498000, 0.0630032000, 0.0663109000, 0.0748079000, 0.0963495000, 0.1511605000, 0.2912731000", \ - "0.0611987000, 0.0626096000, 0.0659485000, 0.0743460000, 0.0959665000, 0.1508379000, 0.2908259000", \ - "0.0608323000, 0.0620821000, 0.0654316000, 0.0738729000, 0.0953849000, 0.1504479000, 0.2908699000", \ - "0.0607315000, 0.0619716000, 0.0651405000, 0.0736874000, 0.0951486000, 0.1501884000, 0.2902448000", \ - "0.0609382000, 0.0623226000, 0.0656570000, 0.0740289000, 0.0957696000, 0.1504576000, 0.2903907000"); - } - } - max_capacitance : 0.1428320000; - max_transition : 1.4964440000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0714431000, 0.0738831000, 0.0800329000, 0.0950003000, 0.1306553000, 0.2164406000, 0.4277320000", \ - "0.0753654000, 0.0778341000, 0.0840307000, 0.0989762000, 0.1345758000, 0.2203222000, 0.4310250000", \ - "0.0828426000, 0.0852433000, 0.0914503000, 0.1064040000, 0.1421239000, 0.2277553000, 0.4388578000", \ - "0.0967851000, 0.0992309000, 0.1054971000, 0.1204415000, 0.1561033000, 0.2416796000, 0.4525794000", \ - "0.1191743000, 0.1216425000, 0.1280405000, 0.1445327000, 0.1822982000, 0.2693604000, 0.4806406000", \ - "0.1472885000, 0.1504563000, 0.1584493000, 0.1788275000, 0.2247612000, 0.3224531000, 0.5431101000", \ - "0.1531250000, 0.1589426000, 0.1726780000, 0.2018241000, 0.2679416000, 0.3984773000, 0.6591189000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2247590000, 0.2307046000, 0.2453776000, 0.2810655000, 0.3731866000, 0.6033561000, 1.1888303000", \ - "0.2284216000, 0.2347347000, 0.2496615000, 0.2858892000, 0.3779143000, 0.6077256000, 1.1936032000", \ - "0.2416559000, 0.2475460000, 0.2621170000, 0.2978671000, 0.3905076000, 0.6211597000, 1.2061259000", \ - "0.2672291000, 0.2726407000, 0.2882328000, 0.3244467000, 0.4172283000, 0.6482208000, 1.2343357000", \ - "0.3218733000, 0.3281648000, 0.3423715000, 0.3793057000, 0.4708222000, 0.7024996000, 1.2884522000", \ - "0.4272494000, 0.4342458000, 0.4504142000, 0.4885748000, 0.5847919000, 0.8152136000, 1.4019679000", \ - "0.6095695000, 0.6172712000, 0.6393712000, 0.6874247000, 0.8014373000, 1.0587943000, 1.6543447000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0644718000, 0.0670847000, 0.0737450000, 0.0907128000, 0.1340677000, 0.2446946000, 0.5300174000", \ - "0.0643350000, 0.0668025000, 0.0734672000, 0.0907106000, 0.1339114000, 0.2445871000, 0.5296853000", \ - "0.0637562000, 0.0663989000, 0.0731921000, 0.0903375000, 0.1337341000, 0.2445149000, 0.5300004000", \ - "0.0652557000, 0.0678239000, 0.0742977000, 0.0909428000, 0.1338672000, 0.2444795000, 0.5298733000", \ - "0.0753864000, 0.0777888000, 0.0835378000, 0.0999061000, 0.1409542000, 0.2474076000, 0.5300478000", \ - "0.1030908000, 0.1052507000, 0.1117655000, 0.1279594000, 0.1692446000, 0.2724504000, 0.5414460000", \ - "0.1690816000, 0.1729520000, 0.1805002000, 0.2005511000, 0.2456979000, 0.3502029000, 0.6102931000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1693065000, 0.1765300000, 0.1957141000, 0.2432236000, 0.3651109000, 0.6775807000, 1.4777902000", \ - "0.1694245000, 0.1767143000, 0.1957167000, 0.2432537000, 0.3652122000, 0.6780811000, 1.4774617000", \ - "0.1692740000, 0.1768500000, 0.1950750000, 0.2431758000, 0.3652928000, 0.6765635000, 1.4729421000", \ - "0.1691342000, 0.1767172000, 0.1956768000, 0.2431786000, 0.3654806000, 0.6766553000, 1.4765236000", \ - "0.1704615000, 0.1778640000, 0.1960508000, 0.2438625000, 0.3660677000, 0.6771150000, 1.4737531000", \ - "0.1948535000, 0.2015502000, 0.2189741000, 0.2638847000, 0.3781895000, 0.6809546000, 1.4776425000", \ - "0.2543996000, 0.2618726000, 0.2812892000, 0.3297764000, 0.4472625000, 0.7374840000, 1.4923438000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0673671000, 0.0695466000, 0.0749923000, 0.0881002000, 0.1207897000, 0.2022555000, 0.4086848000", \ - "0.0719381000, 0.0741523000, 0.0793347000, 0.0926037000, 0.1252242000, 0.2066801000, 0.4137678000", \ - "0.0799134000, 0.0819113000, 0.0873387000, 0.1006532000, 0.1334948000, 0.2149735000, 0.4219443000", \ - "0.0928838000, 0.0951632000, 0.1007939000, 0.1145624000, 0.1475818000, 0.2295819000, 0.4364219000", \ - "0.1117483000, 0.1143845000, 0.1209345000, 0.1365445000, 0.1730226000, 0.2578849000, 0.4653444000", \ - "0.1310190000, 0.1338846000, 0.1431684000, 0.1638500000, 0.2103646000, 0.3095793000, 0.5290216000", \ - "0.1149604000, 0.1212298000, 0.1356670000, 0.1687579000, 0.2403055000, 0.3790597000, 0.6428443000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.2089689000, 0.2147434000, 0.2293339000, 0.2647178000, 0.3571211000, 0.5875959000, 1.1727964000", \ - "0.2118815000, 0.2171981000, 0.2310796000, 0.2689707000, 0.3600985000, 0.5902291000, 1.1758644000", \ - "0.2224327000, 0.2278635000, 0.2423527000, 0.2790755000, 0.3704740000, 0.6017250000, 1.1878207000", \ - "0.2470194000, 0.2529596000, 0.2673866000, 0.3034831000, 0.3960103000, 0.6276228000, 1.2137605000", \ - "0.3039538000, 0.3094928000, 0.3238267000, 0.3604908000, 0.4523392000, 0.6845997000, 1.2712625000", \ - "0.4202611000, 0.4263883000, 0.4439292000, 0.4875692000, 0.5849822000, 0.8163242000, 1.4032221000", \ - "0.6313899000, 0.6401712000, 0.6630310000, 0.7187759000, 0.8423117000, 1.1126861000, 1.7128767000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0485267000, 0.0511630000, 0.0574494000, 0.0738496000, 0.1168746000, 0.2271796000, 0.5114059000", \ - "0.0486069000, 0.0510354000, 0.0573391000, 0.0739082000, 0.1165809000, 0.2271749000, 0.5119998000", \ - "0.0484391000, 0.0509141000, 0.0574994000, 0.0739031000, 0.1165998000, 0.2271677000, 0.5118332000", \ - "0.0510925000, 0.0531843000, 0.0591682000, 0.0751513000, 0.1170582000, 0.2271717000, 0.5117686000", \ - "0.0609206000, 0.0633408000, 0.0695248000, 0.0852905000, 0.1260630000, 0.2310317000, 0.5115823000", \ - "0.0917164000, 0.0941558000, 0.1005912000, 0.1168988000, 0.1571081000, 0.2596766000, 0.5253201000", \ - "0.1594352000, 0.1627224000, 0.1716873000, 0.1924773000, 0.2404898000, 0.3452725000, 0.5988002000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1693373000, 0.1764320000, 0.1951689000, 0.2432371000, 0.3655254000, 0.6767429000, 1.4791099000", \ - "0.1689846000, 0.1764074000, 0.1957231000, 0.2431101000, 0.3664025000, 0.6769266000, 1.4725720000", \ - "0.1696862000, 0.1768526000, 0.1952727000, 0.2435789000, 0.3655274000, 0.6773072000, 1.4787718000", \ - "0.1694479000, 0.1768016000, 0.1955094000, 0.2434701000, 0.3654176000, 0.6772271000, 1.4763301000", \ - "0.1734808000, 0.1804060000, 0.1983211000, 0.2444915000, 0.3659669000, 0.6778013000, 1.4790247000", \ - "0.2093952000, 0.2167326000, 0.2347861000, 0.2757699000, 0.3858788000, 0.6816560000, 1.4770077000", \ - "0.2962276000, 0.3044110000, 0.3257562000, 0.3751312000, 0.4857831000, 0.7540783000, 1.4921581000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0533363000, 0.0552677000, 0.0600754000, 0.0723553000, 0.1035212000, 0.1824418000, 0.3845558000", \ - "0.0574272000, 0.0593840000, 0.0646208000, 0.0769360000, 0.1086065000, 0.1874706000, 0.3882991000", \ - "0.0654741000, 0.0676143000, 0.0726313000, 0.0855171000, 0.1172659000, 0.1970573000, 0.3996081000", \ - "0.0780661000, 0.0804658000, 0.0860673000, 0.0999798000, 0.1325225000, 0.2125068000, 0.4141034000", \ - "0.0935631000, 0.0965542000, 0.1040366000, 0.1209257000, 0.1588000000, 0.2433046000, 0.4462474000", \ - "0.1019909000, 0.1063982000, 0.1174107000, 0.1423995000, 0.1946324000, 0.2997136000, 0.5168286000", \ - "0.0661834000, 0.0737008000, 0.0922115000, 0.1340169000, 0.2168824000, 0.3692862000, 0.6474663000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1695104000, 0.1754506000, 0.1900112000, 0.2266989000, 0.3172071000, 0.5477190000, 1.1339228000", \ - "0.1717704000, 0.1773226000, 0.1912771000, 0.2287446000, 0.3196447000, 0.5504917000, 1.1360981000", \ - "0.1787187000, 0.1851188000, 0.2001749000, 0.2369202000, 0.3281496000, 0.5596710000, 1.1457331000", \ - "0.2020781000, 0.2077143000, 0.2227215000, 0.2593998000, 0.3523824000, 0.5845763000, 1.1708613000", \ - "0.2644319000, 0.2699969000, 0.2843465000, 0.3206153000, 0.4127977000, 0.6430885000, 1.2308917000", \ - "0.4030547000, 0.4100736000, 0.4270399000, 0.4694896000, 0.5624832000, 0.7874535000, 1.3716901000", \ - "0.6301131000, 0.6400029000, 0.6645799000, 0.7213666000, 0.8589762000, 1.1332387000, 1.7160715000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0322004000, 0.0347040000, 0.0410833000, 0.0576556000, 0.1000788000, 0.2091324000, 0.4874806000", \ - "0.0321488000, 0.0346673000, 0.0412068000, 0.0575709000, 0.1003158000, 0.2086806000, 0.4874411000", \ - "0.0324037000, 0.0348862000, 0.0412383000, 0.0576624000, 0.1000200000, 0.2091988000, 0.4888660000", \ - "0.0368888000, 0.0391974000, 0.0449978000, 0.0601488000, 0.1009815000, 0.2085419000, 0.4870198000", \ - "0.0499885000, 0.0521374000, 0.0580943000, 0.0732486000, 0.1126591000, 0.2141997000, 0.4874758000", \ - "0.0838335000, 0.0868184000, 0.0934688000, 0.1097321000, 0.1490237000, 0.2484400000, 0.5014941000", \ - "0.1555212000, 0.1590220000, 0.1675523000, 0.1895390000, 0.2373528000, 0.3407909000, 0.5931575000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.1693705000, 0.1765894000, 0.1955942000, 0.2431670000, 0.3655394000, 0.6769905000, 1.4761889000", \ - "0.1688253000, 0.1762484000, 0.1951548000, 0.2439609000, 0.3652920000, 0.6769907000, 1.4739882000", \ - "0.1691602000, 0.1765327000, 0.1954425000, 0.2432059000, 0.3655334000, 0.6766809000, 1.4736657000", \ - "0.1686750000, 0.1760722000, 0.1952794000, 0.2434657000, 0.3659225000, 0.6771423000, 1.4738176000", \ - "0.1733537000, 0.1801254000, 0.1980913000, 0.2433524000, 0.3643682000, 0.6772283000, 1.4724038000", \ - "0.2240159000, 0.2315083000, 0.2501121000, 0.2914831000, 0.3937198000, 0.6838564000, 1.4732808000", \ - "0.3207896000, 0.3287480000, 0.3526775000, 0.4085304000, 0.5341450000, 0.7885994000, 1.4964444000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0640882000, 0.0666140000, 0.0729001000, 0.0880255000, 0.1238232000, 0.2095057000, 0.4206715000", \ - "0.0679493000, 0.0704587000, 0.0768167000, 0.0919985000, 0.1280358000, 0.2138601000, 0.4248460000", \ - "0.0766349000, 0.0791720000, 0.0854455000, 0.1006668000, 0.1366797000, 0.2227146000, 0.4342035000", \ - "0.0971735000, 0.0996551000, 0.1059203000, 0.1206446000, 0.1563580000, 0.2426682000, 0.4544416000", \ - "0.1311897000, 0.1343771000, 0.1422552000, 0.1606292000, 0.2003868000, 0.2888748000, 0.5008672000", \ - "0.1722681000, 0.1766909000, 0.1876710000, 0.2138791000, 0.2688383000, 0.3804181000, 0.6084886000", \ - "0.1936894000, 0.2004463000, 0.2178312000, 0.2560265000, 0.3408574000, 0.5080853000, 0.8102438000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0483191000, 0.0502994000, 0.0553043000, 0.0676909000, 0.0987880000, 0.1771481000, 0.3760944000", \ - "0.0533696000, 0.0553584000, 0.0604281000, 0.0730926000, 0.1043870000, 0.1827179000, 0.3821624000", \ - "0.0659450000, 0.0679434000, 0.0730346000, 0.0857757000, 0.1173570000, 0.1968598000, 0.3959064000", \ - "0.0972868000, 0.0995384000, 0.1048662000, 0.1173027000, 0.1482353000, 0.2271230000, 0.4272519000", \ - "0.1531055000, 0.1567181000, 0.1649973000, 0.1837233000, 0.2226853000, 0.3022078000, 0.5025992000", \ - "0.2458505000, 0.2512871000, 0.2643886000, 0.2944099000, 0.3564157000, 0.4694008000, 0.6746901000", \ - "0.4035483000, 0.4112914000, 0.4309247000, 0.4777094000, 0.5750291000, 0.7571110000, 1.0600352000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0639604000, 0.0665503000, 0.0731910000, 0.0902770000, 0.1334122000, 0.2442673000, 0.5302136000", \ - "0.0638304000, 0.0664704000, 0.0732376000, 0.0901326000, 0.1335468000, 0.2443851000, 0.5296350000", \ - "0.0629362000, 0.0656105000, 0.0724950000, 0.0898333000, 0.1334467000, 0.2443712000, 0.5299362000", \ - "0.0664415000, 0.0687198000, 0.0748370000, 0.0909496000, 0.1331907000, 0.2439223000, 0.5300387000", \ - "0.0838545000, 0.0865419000, 0.0933249000, 0.1090041000, 0.1475729000, 0.2486362000, 0.5296776000", \ - "0.1248602000, 0.1279391000, 0.1360901000, 0.1547074000, 0.1982747000, 0.2954161000, 0.5481055000", \ - "0.2006305000, 0.2055564000, 0.2172066000, 0.2437348000, 0.3025657000, 0.4214699000, 0.6695370000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0506474000, 0.0534787000, 0.0610001000, 0.0802544000, 0.1279194000, 0.2465627000, 0.5408178000", \ - "0.0505356000, 0.0535737000, 0.0609996000, 0.0800807000, 0.1280080000, 0.2466850000, 0.5413821000", \ - "0.0505337000, 0.0533790000, 0.0609018000, 0.0802846000, 0.1279883000, 0.2467679000, 0.5411481000", \ - "0.0593070000, 0.0617042000, 0.0676466000, 0.0842247000, 0.1286833000, 0.2466777000, 0.5412283000", \ - "0.0975006000, 0.0995377000, 0.1047163000, 0.1169023000, 0.1503227000, 0.2520444000, 0.5414930000", \ - "0.1697108000, 0.1726377000, 0.1794973000, 0.1957611000, 0.2340618000, 0.3140377000, 0.5571021000", \ - "0.3027282000, 0.3059477000, 0.3144833000, 0.3382303000, 0.3905541000, 0.5001233000, 0.7055858000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0508554000, 0.0534318000, 0.0598668000, 0.0751200000, 0.1113131000, 0.1969771000, 0.4081964000", \ - "0.0542147000, 0.0567570000, 0.0631364000, 0.0786593000, 0.1148630000, 0.2009836000, 0.4121944000", \ - "0.0631863000, 0.0657579000, 0.0719974000, 0.0874188000, 0.1237899000, 0.2101528000, 0.4217629000", \ - "0.0875545000, 0.0900656000, 0.0962172000, 0.1101959000, 0.1455264000, 0.2313668000, 0.4432572000", \ - "0.1237458000, 0.1271650000, 0.1355329000, 0.1548875000, 0.1959026000, 0.2823807000, 0.4939507000", \ - "0.1612572000, 0.1662022000, 0.1782885000, 0.2067797000, 0.2678406000, 0.3878758000, 0.6125395000", \ - "0.1803615000, 0.1875261000, 0.2049631000, 0.2461013000, 0.3361751000, 0.5149676000, 0.8458301000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0304369000, 0.0324071000, 0.0372670000, 0.0488391000, 0.0769896000, 0.1477127000, 0.3288244000", \ - "0.0355393000, 0.0374510000, 0.0422447000, 0.0540216000, 0.0825853000, 0.1531887000, 0.3330955000", \ - "0.0488752000, 0.0506823000, 0.0553605000, 0.0669032000, 0.0953227000, 0.1667033000, 0.3462158000", \ - "0.0747721000, 0.0775694000, 0.0840946000, 0.0980866000, 0.1268076000, 0.1979643000, 0.3777028000", \ - "0.1156813000, 0.1201301000, 0.1304558000, 0.1529150000, 0.1956682000, 0.2718351000, 0.4522873000", \ - "0.1831954000, 0.1903149000, 0.2061932000, 0.2419826000, 0.3104648000, 0.4277277000, 0.6229980000", \ - "0.3040779000, 0.3130648000, 0.3368289000, 0.3892118000, 0.4963380000, 0.6839236000, 0.9856679000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0639169000, 0.0666048000, 0.0732724000, 0.0901184000, 0.1334800000, 0.2440571000, 0.5300514000", \ - "0.0638054000, 0.0664186000, 0.0731684000, 0.0903610000, 0.1335181000, 0.2444784000, 0.5300882000", \ - "0.0610805000, 0.0637679000, 0.0707073000, 0.0888659000, 0.1334180000, 0.2440629000, 0.5296284000", \ - "0.0672270000, 0.0694330000, 0.0751244000, 0.0904602000, 0.1320786000, 0.2438351000, 0.5297901000", \ - "0.0875736000, 0.0906723000, 0.0985517000, 0.1161080000, 0.1542811000, 0.2504831000, 0.5296170000", \ - "0.1310670000, 0.1352803000, 0.1455045000, 0.1687381000, 0.2194565000, 0.3193042000, 0.5568463000", \ - "0.2041254000, 0.2104990000, 0.2262118000, 0.2611567000, 0.3326980000, 0.4756107000, 0.7270187000"); - } - related_pin : "C1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012831600, 0.0032929800, 0.0084508100, 0.0216874000, 0.0556566000, 0.1428320000"); - values("0.0323665000, 0.0349215000, 0.0415739000, 0.0584701000, 0.1013214000, 0.2072067000, 0.4723770000", \ - "0.0321575000, 0.0347351000, 0.0415470000, 0.0585785000, 0.1013714000, 0.2071869000, 0.4719990000", \ - "0.0344220000, 0.0366115000, 0.0422146000, 0.0584225000, 0.1013434000, 0.2072271000, 0.4718154000", \ - "0.0520640000, 0.0529607000, 0.0564757000, 0.0679617000, 0.1041400000, 0.2071074000, 0.4719519000", \ - "0.0917787000, 0.0932828000, 0.0976337000, 0.1085650000, 0.1339217000, 0.2177550000, 0.4719121000", \ - "0.1646379000, 0.1667739000, 0.1720511000, 0.1864084000, 0.2204899000, 0.2919962000, 0.4959509000", \ - "0.3003277000, 0.3026898000, 0.3079679000, 0.3257067000, 0.3737190000, 0.4774844000, 0.6655797000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31a_1") { - leakage_power () { - value : 0.0026204000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0016139000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0027125000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0024132000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0020260000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0024420000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0020308000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0020340000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0020053000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0018799000; - when : "A1&A2&A3&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o31a"; - cell_leakage_power : 0.0020660990; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041862000, 0.0041879000, 0.0041917000, 0.0041928000, 0.0041953000, 0.0042011000, 0.0042144000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004192400, -0.004191500, -0.004189500, -0.004188900, -0.004187600, -0.004184600, -0.004177600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025090000; - } - pin ("A2") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038747000, 0.0038755000, 0.0038776000, 0.0038783000, 0.0038800000, 0.0038838000, 0.0038927000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003875700, -0.003873500, -0.003868400, -0.003869200, -0.003871100, -0.003875400, -0.003885500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025190000; - } - pin ("A3") { - capacitance : 0.0023360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021580000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038893000, 0.0038893000, 0.0038894000, 0.0038879000, 0.0038843000, 0.0038761000, 0.0038572000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003891400, -0.003890100, -0.003887200, -0.003887600, -0.003888600, -0.003891000, -0.003896400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025130000; - } - pin ("B1") { - capacitance : 0.0023630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022890000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047422000, 0.0047424000, 0.0047431000, 0.0047449000, 0.0047493000, 0.0047592000, 0.0047822000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002023100, -0.002029200, -0.002043300, -0.002029200, -0.001996700, -0.001922000, -0.001749600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024360000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0152005000, 0.0143554000, 0.0119317000, 0.0046199000, -0.016522900, -0.073727200, -0.222009700", \ - "0.0150584000, 0.0141773000, 0.0117438000, 0.0044951000, -0.016715800, -0.073877000, -0.222118000", \ - "0.0148620000, 0.0139906000, 0.0115351000, 0.0043019000, -0.016909200, -0.074060400, -0.222295100", \ - "0.0146576000, 0.0137822000, 0.0113943000, 0.0041137000, -0.017061400, -0.074225800, -0.222466600", \ - "0.0145113000, 0.0136745000, 0.0112225000, 0.0039334000, -0.017237100, -0.074329200, -0.222538600", \ - "0.0141359000, 0.0133357000, 0.0110259000, 0.0038060000, -0.017265900, -0.074284900, -0.222503000", \ - "0.0180745000, 0.0167382000, 0.0133987000, 0.0048213000, -0.017354000, -0.074221900, -0.222371800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0152923000, 0.0166720000, 0.0201739000, 0.0288253000, 0.0507415000, 0.1078074000, 0.2549800000", \ - "0.0151781000, 0.0165939000, 0.0200651000, 0.0287295000, 0.0506733000, 0.1072276000, 0.2535030000", \ - "0.0150420000, 0.0164560000, 0.0199399000, 0.0285985000, 0.0505846000, 0.1075911000, 0.2547646000", \ - "0.0148885000, 0.0162865000, 0.0197391000, 0.0284223000, 0.0504616000, 0.1075519000, 0.2547712000", \ - "0.0147375000, 0.0161018000, 0.0196233000, 0.0282293000, 0.0503299000, 0.1070475000, 0.2535690000", \ - "0.0151448000, 0.0164530000, 0.0197882000, 0.0281206000, 0.0502038000, 0.1066290000, 0.2534140000", \ - "0.0155933000, 0.0168692000, 0.0202194000, 0.0288142000, 0.0508950000, 0.1078125000, 0.2528772000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0132324000, 0.0123412000, 0.0099029000, 0.0026709000, -0.018453300, -0.075503700, -0.223652800", \ - "0.0130741000, 0.0121862000, 0.0097899000, 0.0025622000, -0.018596000, -0.075622400, -0.223780900", \ - "0.0129301000, 0.0120533000, 0.0096216000, 0.0023193000, -0.018731200, -0.075755200, -0.223939800", \ - "0.0127809000, 0.0119268000, 0.0094929000, 0.0021658000, -0.018936600, -0.075931500, -0.224095700", \ - "0.0125984000, 0.0117603000, 0.0093246000, 0.0020172000, -0.019049400, -0.076040700, -0.224171900", \ - "0.0122936000, 0.0114421000, 0.0093854000, 0.0020817000, -0.019003300, -0.076005600, -0.224144700", \ - "0.0164832000, 0.0150269000, 0.0116142000, 0.0030325000, -0.019064600, -0.075819800, -0.223923800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0139932000, 0.0153814000, 0.0188727000, 0.0276260000, 0.0498033000, 0.1065896000, 0.2543397000", \ - "0.0139843000, 0.0153515000, 0.0188474000, 0.0275995000, 0.0500113000, 0.1066337000, 0.2534127000", \ - "0.0138664000, 0.0152530000, 0.0187480000, 0.0274820000, 0.0496644000, 0.1065082000, 0.2531501000", \ - "0.0136618000, 0.0150337000, 0.0184975000, 0.0272171000, 0.0493957000, 0.1063925000, 0.2529419000", \ - "0.0134660000, 0.0147594000, 0.0182418000, 0.0269015000, 0.0490765000, 0.1064172000, 0.2537633000", \ - "0.0135251000, 0.0148552000, 0.0182012000, 0.0266602000, 0.0488181000, 0.1054151000, 0.2525525000", \ - "0.0140023000, 0.0152417000, 0.0185770000, 0.0272253000, 0.0493883000, 0.1065953000, 0.2533053000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0110958000, 0.0102141000, 0.0078162000, 0.0005883000, -0.020473200, -0.077382900, -0.225460900", \ - "0.0109302000, 0.0100242000, 0.0075906000, 0.0003817000, -0.020666600, -0.077568600, -0.225637800", \ - "0.0107187000, 0.0098171000, 0.0074117000, 0.0001659000, -0.020883800, -0.077783500, -0.225860100", \ - "0.0105251000, 0.0096499000, 0.0072373000, 6.000000e-07, -0.021022900, -0.077930700, -0.226052100", \ - "0.0106609000, 0.0097506000, 0.0073287000, 4.480000e-05, -0.020968000, -0.077893300, -0.225934100", \ - "0.0107849000, 0.0098976000, 0.0074701000, 0.0003337000, -0.020668500, -0.077544000, -0.225596300", \ - "0.0155903000, 0.0142439000, 0.0108492000, 0.0021953000, -0.019625100, -0.076561200, -0.224650000"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0124115000, 0.0138059000, 0.0173108000, 0.0260054000, 0.0481264000, 0.1051219000, 0.2504632000", \ - "0.0123868000, 0.0137751000, 0.0172710000, 0.0260143000, 0.0481150000, 0.1050458000, 0.2517410000", \ - "0.0122452000, 0.0136327000, 0.0171165000, 0.0258406000, 0.0480044000, 0.1049553000, 0.2515841000", \ - "0.0119495000, 0.0133242000, 0.0167795000, 0.0254742000, 0.0476536000, 0.1048174000, 0.2525495000", \ - "0.0118124000, 0.0130680000, 0.0164328000, 0.0250748000, 0.0472130000, 0.1043120000, 0.2508468000", \ - "0.0117600000, 0.0130638000, 0.0164133000, 0.0249915000, 0.0472096000, 0.1036092000, 0.2509909000", \ - "0.0123087000, 0.0135774000, 0.0168616000, 0.0255969000, 0.0477186000, 0.1048293000, 0.2499042000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0103530000, 0.0096763000, 0.0076320000, 0.0008386000, -0.020458300, -0.077681100, -0.225924500", \ - "0.0101191000, 0.0094378000, 0.0073851000, 0.0006171000, -0.020675800, -0.077897500, -0.226138600", \ - "0.0098136000, 0.0091152000, 0.0070484000, 0.0002846000, -0.020989600, -0.078206500, -0.226440900", \ - "0.0095854000, 0.0088237000, 0.0067074000, -3.71000e-05, -0.021232100, -0.078398800, -0.226615100", \ - "0.0088258000, 0.0082234000, 0.0063710000, -0.000203900, -0.021292300, -0.078378800, -0.226575800", \ - "0.0130601000, 0.0117882000, 0.0085668000, 0.0002921000, -0.020963900, -0.077956900, -0.226098100", \ - "0.0152838000, 0.0139916000, 0.0107034000, 0.0022284000, -0.019742800, -0.076867200, -0.224624300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012925770, 0.0033415090, 0.0086383130, 0.0223313600, 0.0577300000, 0.1492409000"); - values("0.0130799000, 0.0144907000, 0.0180053000, 0.0267035000, 0.0488012000, 0.1060258000, 0.2520884000", \ - "0.0129921000, 0.0144055000, 0.0178804000, 0.0265927000, 0.0487100000, 0.1053806000, 0.2532420000", \ - "0.0128229000, 0.0142386000, 0.0177365000, 0.0264593000, 0.0485701000, 0.1052893000, 0.2519020000", \ - "0.0126785000, 0.0140566000, 0.0175254000, 0.0262466000, 0.0483540000, 0.1051128000, 0.2517004000", \ - "0.0124676000, 0.0138800000, 0.0173036000, 0.0259709000, 0.0480483000, 0.1049392000, 0.2516451000", \ - "0.0133035000, 0.0146060000, 0.0179341000, 0.0261116000, 0.0484547000, 0.1054425000, 0.2518881000", \ - "0.0144333000, 0.0156747000, 0.0189954000, 0.0274730000, 0.0495105000, 0.1067565000, 0.2528088000"); - } - } - max_capacitance : 0.1492410000; - max_transition : 1.5053010000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.2539146000, 0.2619229000, 0.2782627000, 0.3095071000, 0.3681254000, 0.4898481000, 0.7761450000", \ - "0.2582156000, 0.2662422000, 0.2826852000, 0.3137462000, 0.3727852000, 0.4944891000, 0.7809403000", \ - "0.2697781000, 0.2777963000, 0.2941196000, 0.3252932000, 0.3843665000, 0.5060817000, 0.7925460000", \ - "0.2959527000, 0.3039389000, 0.3202689000, 0.3510458000, 0.4102077000, 0.5320299000, 0.8183597000", \ - "0.3523786000, 0.3603397000, 0.3766769000, 0.4077693000, 0.4670720000, 0.5887116000, 0.8752261000", \ - "0.4659378000, 0.4744225000, 0.4916370000, 0.5241202000, 0.5843908000, 0.7072708000, 0.9938088000", \ - "0.6660084000, 0.6756344000, 0.6951585000, 0.7316522000, 0.7984148000, 0.9274999000, 1.2175386000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0937478000, 0.1011271000, 0.1180812000, 0.1571199000, 0.2536308000, 0.5004793000, 1.1377842000", \ - "0.0981102000, 0.1055598000, 0.1224532000, 0.1615938000, 0.2576131000, 0.5039749000, 1.1424223000", \ - "0.1071638000, 0.1145955000, 0.1314585000, 0.1705533000, 0.2667646000, 0.5139407000, 1.1521283000", \ - "0.1265103000, 0.1338577000, 0.1506686000, 0.1897282000, 0.2863414000, 0.5334148000, 1.1702951000", \ - "0.1605927000, 0.1683319000, 0.1856265000, 0.2250093000, 0.3216362000, 0.5681177000, 1.2048892000", \ - "0.2046360000, 0.2131197000, 0.2316093000, 0.2720772000, 0.3692371000, 0.6157736000, 1.2522086000", \ - "0.2351753000, 0.2456655000, 0.2680949000, 0.3114303000, 0.4088957000, 0.6579410000, 1.2929086000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0347126000, 0.0397255000, 0.0514522000, 0.0747985000, 0.1298622000, 0.2635841000, 0.6265168000", \ - "0.0346293000, 0.0397352000, 0.0511612000, 0.0758769000, 0.1300357000, 0.2636154000, 0.6299361000", \ - "0.0346207000, 0.0396880000, 0.0509490000, 0.0759012000, 0.1299765000, 0.2636410000, 0.6298936000", \ - "0.0346687000, 0.0397170000, 0.0514576000, 0.0753349000, 0.1300834000, 0.2633248000, 0.6254307000", \ - "0.0347972000, 0.0400262000, 0.0509172000, 0.0751679000, 0.1302495000, 0.2638164000, 0.6299666000", \ - "0.0378848000, 0.0430997000, 0.0545657000, 0.0781987000, 0.1330003000, 0.2648625000, 0.6267060000", \ - "0.0458912000, 0.0521896000, 0.0637623000, 0.0894493000, 0.1447273000, 0.2759592000, 0.6286714000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0274167000, 0.0350665000, 0.0542518000, 0.1048815000, 0.2392733000, 0.5895360000, 1.4976481000", \ - "0.0274210000, 0.0350307000, 0.0543945000, 0.1049872000, 0.2390065000, 0.5894901000, 1.4975059000", \ - "0.0273593000, 0.0349584000, 0.0542939000, 0.1050427000, 0.2394715000, 0.5889131000, 1.4937612000", \ - "0.0273284000, 0.0349382000, 0.0542710000, 0.1049598000, 0.2395744000, 0.5898362000, 1.4976004000", \ - "0.0295615000, 0.0368425000, 0.0557263000, 0.1054827000, 0.2392971000, 0.5884138000, 1.4944591000", \ - "0.0344439000, 0.0419763000, 0.0594672000, 0.1076472000, 0.2399987000, 0.5883002000, 1.4942741000", \ - "0.0458114000, 0.0537719000, 0.0704428000, 0.1142152000, 0.2416266000, 0.5915691000, 1.4910365000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.2372271000, 0.2452478000, 0.2616332000, 0.2927176000, 0.3513493000, 0.4735646000, 0.7604973000", \ - "0.2407929000, 0.2487934000, 0.2651334000, 0.2960403000, 0.3549852000, 0.4771250000, 0.7637244000", \ - "0.2515014000, 0.2594459000, 0.2757991000, 0.3070527000, 0.3658081000, 0.4878345000, 0.7743189000", \ - "0.2775418000, 0.2855563000, 0.3018941000, 0.3330493000, 0.3919245000, 0.5139257000, 0.8003680000", \ - "0.3381400000, 0.3461298000, 0.3624190000, 0.3936357000, 0.4529835000, 0.5751754000, 0.8616570000", \ - "0.4660423000, 0.4745852000, 0.4930724000, 0.5256544000, 0.5866840000, 0.7096799000, 0.9964178000", \ - "0.6921420000, 0.7030186000, 0.7235920000, 0.7614039000, 0.8284496000, 0.9578652000, 1.2481297000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0901573000, 0.0974336000, 0.1140722000, 0.1530106000, 0.2495166000, 0.4964619000, 1.1346108000", \ - "0.0948620000, 0.1020704000, 0.1187568000, 0.1577459000, 0.2545307000, 0.5013994000, 1.1370482000", \ - "0.1039697000, 0.1111967000, 0.1278697000, 0.1668273000, 0.2635646000, 0.5104455000, 1.1474055000", \ - "0.1225875000, 0.1298336000, 0.1464204000, 0.1852959000, 0.2822946000, 0.5289095000, 1.1655055000", \ - "0.1540064000, 0.1616068000, 0.1787377000, 0.2180504000, 0.3149940000, 0.5629397000, 1.2018425000", \ - "0.1912596000, 0.1999148000, 0.2184826000, 0.2589444000, 0.3557087000, 0.6031108000, 1.2400474000", \ - "0.2095414000, 0.2208417000, 0.2436092000, 0.2877155000, 0.3853572000, 0.6327037000, 1.2692786000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0346890000, 0.0397426000, 0.0511008000, 0.0758600000, 0.1306056000, 0.2638534000, 0.6299507000", \ - "0.0346284000, 0.0396600000, 0.0514626000, 0.0751565000, 0.1306581000, 0.2632121000, 0.6251929000", \ - "0.0349571000, 0.0397208000, 0.0514057000, 0.0751996000, 0.1295515000, 0.2634566000, 0.6263478000", \ - "0.0346549000, 0.0397544000, 0.0512632000, 0.0748246000, 0.1303627000, 0.2628807000, 0.6260856000", \ - "0.0347457000, 0.0398342000, 0.0515811000, 0.0749563000, 0.1302035000, 0.2635440000, 0.6271644000", \ - "0.0394920000, 0.0443893000, 0.0559066000, 0.0796636000, 0.1335072000, 0.2642924000, 0.6275950000", \ - "0.0515269000, 0.0563007000, 0.0681182000, 0.0931158000, 0.1470831000, 0.2757632000, 0.6298880000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0261553000, 0.0335421000, 0.0526726000, 0.1032896000, 0.2381227000, 0.5897037000, 1.4981656000", \ - "0.0261030000, 0.0335726000, 0.0526429000, 0.1033076000, 0.2383437000, 0.5882356000, 1.4931070000", \ - "0.0260389000, 0.0335494000, 0.0526724000, 0.1033372000, 0.2384337000, 0.5896459000, 1.4938426000", \ - "0.0264146000, 0.0338709000, 0.0527651000, 0.1033985000, 0.2384166000, 0.5878332000, 1.4971711000", \ - "0.0286969000, 0.0360912000, 0.0546287000, 0.1041592000, 0.2383351000, 0.5890496000, 1.4960149000", \ - "0.0350782000, 0.0420825000, 0.0594042000, 0.1068314000, 0.2390450000, 0.5867187000, 1.4929230000", \ - "0.0469488000, 0.0543069000, 0.0712206000, 0.1147625000, 0.2408996000, 0.5895224000, 1.4881001000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.2022090000, 0.2102081000, 0.2265408000, 0.2575664000, 0.3167788000, 0.4392249000, 0.7258720000", \ - "0.2043636000, 0.2124117000, 0.2287261000, 0.2599557000, 0.3193778000, 0.4415723000, 0.7284198000", \ - "0.2129599000, 0.2209635000, 0.2374109000, 0.2686175000, 0.3281513000, 0.4503865000, 0.7372140000", \ - "0.2384827000, 0.2464651000, 0.2628906000, 0.2940859000, 0.3533842000, 0.4756692000, 0.7624936000", \ - "0.3018966000, 0.3099300000, 0.3260905000, 0.3573329000, 0.4169101000, 0.5390126000, 0.8258246000", \ - "0.4422255000, 0.4512060000, 0.4684843000, 0.5005719000, 0.5613367000, 0.6840913000, 0.9711479000", \ - "0.6722499000, 0.6835876000, 0.7060598000, 0.7440615000, 0.8089688000, 0.9350470000, 1.2254449000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0764046000, 0.0833968000, 0.0995398000, 0.1379749000, 0.2345420000, 0.4818987000, 1.1195459000", \ - "0.0811851000, 0.0881374000, 0.1043172000, 0.1427945000, 0.2388263000, 0.4861307000, 1.1223780000", \ - "0.0907775000, 0.0977350000, 0.1138342000, 0.1521933000, 0.2483778000, 0.4963784000, 1.1307423000", \ - "0.1097341000, 0.1167373000, 0.1329121000, 0.1713030000, 0.2675127000, 0.5160565000, 1.1600174000", \ - "0.1381124000, 0.1455980000, 0.1624733000, 0.2013646000, 0.2979375000, 0.5459790000, 1.1815446000", \ - "0.1672676000, 0.1762278000, 0.1948941000, 0.2349948000, 0.3316019000, 0.5784550000, 1.2175220000", \ - "0.1704024000, 0.1823278000, 0.2063904000, 0.2517549000, 0.3493009000, 0.5971655000, 1.2331246000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0346584000, 0.0396862000, 0.0515068000, 0.0754884000, 0.1303406000, 0.2629644000, 0.6235894000", \ - "0.0352676000, 0.0402488000, 0.0509316000, 0.0757457000, 0.1298084000, 0.2634876000, 0.6295577000", \ - "0.0347515000, 0.0395880000, 0.0513220000, 0.0757551000, 0.1300038000, 0.2635118000, 0.6293888000", \ - "0.0345496000, 0.0396516000, 0.0511945000, 0.0756978000, 0.1297611000, 0.2633997000, 0.6288509000", \ - "0.0349513000, 0.0400179000, 0.0507178000, 0.0746981000, 0.1300585000, 0.2631423000, 0.6283650000", \ - "0.0409445000, 0.0455720000, 0.0556108000, 0.0792040000, 0.1322602000, 0.2651518000, 0.6241651000", \ - "0.0577670000, 0.0634934000, 0.0740133000, 0.0943928000, 0.1434772000, 0.2731753000, 0.6310302000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0243959000, 0.0318039000, 0.0509126000, 0.1020633000, 0.2379105000, 0.5903153000, 1.4958722000", \ - "0.0244412000, 0.0317616000, 0.0509162000, 0.1017930000, 0.2378149000, 0.5896418000, 1.4958387000", \ - "0.0243971000, 0.0317687000, 0.0509740000, 0.1020449000, 0.2376979000, 0.5910208000, 1.4987168000", \ - "0.0252153000, 0.0324506000, 0.0513806000, 0.1021953000, 0.2378627000, 0.5911370000, 1.5053007000", \ - "0.0284599000, 0.0354288000, 0.0537087000, 0.1034049000, 0.2367338000, 0.5879925000, 1.4920001000", \ - "0.0358961000, 0.0427147000, 0.0599559000, 0.1063580000, 0.2387055000, 0.5871997000, 1.4985696000", \ - "0.0505698000, 0.0584394000, 0.0747351000, 0.1167347000, 0.2407928000, 0.5882736000, 1.4905395000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0699376000, 0.0750394000, 0.0861598000, 0.1098236000, 0.1617207000, 0.2769904000, 0.5602486000", \ - "0.0750867000, 0.0801784000, 0.0912724000, 0.1149887000, 0.1668981000, 0.2821672000, 0.5655411000", \ - "0.0880116000, 0.0930655000, 0.1041662000, 0.1278932000, 0.1798487000, 0.2950760000, 0.5784822000", \ - "0.1190349000, 0.1240474000, 0.1352010000, 0.1589514000, 0.2111045000, 0.3265192000, 0.6098422000", \ - "0.1762577000, 0.1822791000, 0.1950355000, 0.2211911000, 0.2751475000, 0.3910184000, 0.6749823000", \ - "0.2653351000, 0.2731375000, 0.2893863000, 0.3214698000, 0.3825067000, 0.5045731000, 0.7888366000", \ - "0.4078732000, 0.4180507000, 0.4388662000, 0.4795076000, 0.5560229000, 0.6917691000, 0.9797861000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0860726000, 0.0935354000, 0.1105347000, 0.1498126000, 0.2467214000, 0.4941293000, 1.1311541000", \ - "0.0902807000, 0.0977287000, 0.1146236000, 0.1539434000, 0.2506271000, 0.4977010000, 1.1366205000", \ - "0.1005041000, 0.1079460000, 0.1248701000, 0.1641654000, 0.2609808000, 0.5078113000, 1.1441261000", \ - "0.1252277000, 0.1325488000, 0.1492215000, 0.1880613000, 0.2847176000, 0.5316968000, 1.1687202000", \ - "0.1650556000, 0.1726680000, 0.1897067000, 0.2290927000, 0.3260321000, 0.5730523000, 1.2094281000", \ - "0.2130483000, 0.2212979000, 0.2392265000, 0.2787408000, 0.3758208000, 0.6236138000, 1.2613475000", \ - "0.2527765000, 0.2634085000, 0.2844223000, 0.3264355000, 0.4227155000, 0.6717706000, 1.3080884000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0173247000, 0.0215200000, 0.0319118000, 0.0564742000, 0.1135411000, 0.2496670000, 0.6181984000", \ - "0.0173228000, 0.0215717000, 0.0319310000, 0.0564755000, 0.1134892000, 0.2496768000, 0.6165335000", \ - "0.0171646000, 0.0215661000, 0.0319615000, 0.0564492000, 0.1134482000, 0.2506485000, 0.6173926000", \ - "0.0179401000, 0.0220192000, 0.0322493000, 0.0567491000, 0.1136820000, 0.2500886000, 0.6181491000", \ - "0.0235630000, 0.0277254000, 0.0379365000, 0.0616681000, 0.1165667000, 0.2516792000, 0.6210939000", \ - "0.0327422000, 0.0378754000, 0.0500331000, 0.0754915000, 0.1310938000, 0.2591846000, 0.6218844000", \ - "0.0465999000, 0.0530275000, 0.0681452000, 0.0992993000, 0.1598733000, 0.2815963000, 0.6230777000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012925800, 0.0033415100, 0.0086383100, 0.0223314000, 0.0577300000, 0.1492410000"); - values("0.0275228000, 0.0350513000, 0.0543708000, 0.1050959000, 0.2391031000, 0.5897453000, 1.4964282000", \ - "0.0273607000, 0.0349791000, 0.0543229000, 0.1050428000, 0.2393125000, 0.5895585000, 1.4974130000", \ - "0.0273321000, 0.0349472000, 0.0542591000, 0.1048865000, 0.2393606000, 0.5875980000, 1.4925851000", \ - "0.0274723000, 0.0349674000, 0.0541178000, 0.1046227000, 0.2392862000, 0.5888605000, 1.4947857000", \ - "0.0290297000, 0.0364230000, 0.0553767000, 0.1055813000, 0.2390720000, 0.5891444000, 1.4941087000", \ - "0.0345122000, 0.0412513000, 0.0588160000, 0.1074553000, 0.2404879000, 0.5885352000, 1.4952578000", \ - "0.0459629000, 0.0526698000, 0.0694408000, 0.1124915000, 0.2414338000, 0.5909881000, 1.4921884000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31a_2") { - leakage_power () { - value : 0.0031203000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0020626000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0031529000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0028548000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0025119000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0028423000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0025123000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0025159000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0024926000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0023309000; - when : "A1&A2&A3&!B1"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o31a"; - cell_leakage_power : 0.0025238810; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023680000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041872000, 0.0041881000, 0.0041901000, 0.0041880000, 0.0041831000, 0.0041720000, 0.0041462000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004187800, -0.004185600, -0.004180500, -0.004180100, -0.004179300, -0.004177300, -0.004172800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024980000; - } - pin ("A2") { - capacitance : 0.0023560000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038677000, 0.0038682000, 0.0038692000, 0.0038697000, 0.0038708000, 0.0038735000, 0.0038797000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003868700, -0.003866500, -0.003861600, -0.003862800, -0.003865700, -0.003872300, -0.003887400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025100000; - } - pin ("A3") { - capacitance : 0.0023230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038831000, 0.0038840000, 0.0038861000, 0.0038865000, 0.0038875000, 0.0038898000, 0.0038950000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003883000, -0.003882500, -0.003881200, -0.003882100, -0.003884200, -0.003889000, -0.003900100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025020000; - } - pin ("B1") { - capacitance : 0.0023400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047394000, 0.0047395000, 0.0047397000, 0.0047407000, 0.0047431000, 0.0047484000, 0.0047608000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002023900, -0.002033200, -0.002054600, -0.002039200, -0.002003500, -0.001921300, -0.001731900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024150000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0186742000, 0.0172466000, 0.0135480000, 0.0026507000, -0.031460400, -0.135164000, -0.437121900", \ - "0.0185469000, 0.0170728000, 0.0133975000, 0.0025104000, -0.031580300, -0.135297200, -0.437254800", \ - "0.0183789000, 0.0169227000, 0.0132551000, 0.0023418000, -0.031796400, -0.135467900, -0.437413900", \ - "0.0180311000, 0.0165793000, 0.0129110000, 0.0020585000, -0.032000000, -0.135640200, -0.437562800", \ - "0.0179014000, 0.0164516000, 0.0127547000, 0.0019814000, -0.032127700, -0.135803900, -0.437687200", \ - "0.0180253000, 0.0165610000, 0.0127565000, 0.0018431000, -0.032212400, -0.135863200, -0.437704600", \ - "0.0231177000, 0.0214240000, 0.0174199000, 0.0041704000, -0.031852900, -0.135776800, -0.437537600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0205070000, 0.0221557000, 0.0268753000, 0.0397797000, 0.0761036000, 0.1805212000, 0.4777624000", \ - "0.0204122000, 0.0220582000, 0.0267183000, 0.0396776000, 0.0759769000, 0.1795522000, 0.4776151000", \ - "0.0202483000, 0.0219159000, 0.0266079000, 0.0395415000, 0.0758796000, 0.1794648000, 0.4780662000", \ - "0.0201492000, 0.0218036000, 0.0264705000, 0.0394444000, 0.0757464000, 0.1802525000, 0.4776486000", \ - "0.0201178000, 0.0217464000, 0.0264194000, 0.0391437000, 0.0755322000, 0.1793060000, 0.4779132000", \ - "0.0205952000, 0.0221412000, 0.0266054000, 0.0390724000, 0.0754096000, 0.1789578000, 0.4776536000", \ - "0.0214915000, 0.0229935000, 0.0273276000, 0.0400339000, 0.0758810000, 0.1802242000, 0.4764932000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0165116000, 0.0150625000, 0.0115742000, 0.0007201000, -0.033367800, -0.137004600, -0.438836000", \ - "0.0163952000, 0.0149558000, 0.0113087000, 0.0004494000, -0.033553900, -0.137107100, -0.438962800", \ - "0.0162512000, 0.0147958000, 0.0111801000, 0.0002330000, -0.033632000, -0.137161300, -0.439075500", \ - "0.0161765000, 0.0147139000, 0.0110320000, 0.0002468000, -0.033818200, -0.137428300, -0.439260800", \ - "0.0159784000, 0.0145170000, 0.0108774000, -3.44000e-05, -0.034025800, -0.137616300, -0.439344600", \ - "0.0159757000, 0.0144693000, 0.0107364000, 2.380000e-05, -0.034068000, -0.137632500, -0.439393000", \ - "0.0213303000, 0.0206584000, 0.0156466000, 0.0026198000, -0.033982900, -0.137415000, -0.439158600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0191829000, 0.0208473000, 0.0254706000, 0.0385310000, 0.0750582000, 0.1790665000, 0.4777607000", \ - "0.0191674000, 0.0208193000, 0.0254433000, 0.0385143000, 0.0750916000, 0.1799194000, 0.4799494000", \ - "0.0190744000, 0.0207290000, 0.0253771000, 0.0384268000, 0.0749986000, 0.1788953000, 0.4798195000", \ - "0.0189146000, 0.0205605000, 0.0252460000, 0.0382292000, 0.0747700000, 0.1789185000, 0.4777964000", \ - "0.0187052000, 0.0203409000, 0.0250138000, 0.0377937000, 0.0743220000, 0.1786739000, 0.4792745000", \ - "0.0189962000, 0.0205538000, 0.0250198000, 0.0377421000, 0.0740357000, 0.1775641000, 0.4771084000", \ - "0.0195369000, 0.0210746000, 0.0254481000, 0.0381981000, 0.0745910000, 0.1787292000, 0.4768631000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0143988000, 0.0129637000, 0.0092859000, -0.001523600, -0.035490100, -0.138963900, -0.440664400", \ - "0.0143768000, 0.0129151000, 0.0092365000, -0.001545500, -0.035607700, -0.139091800, -0.440825500", \ - "0.0140975000, 0.0126079000, 0.0089776000, -0.001883800, -0.035819100, -0.139309100, -0.441010100", \ - "0.0138562000, 0.0124118000, 0.0087921000, -0.002069900, -0.036036500, -0.139438300, -0.441184100", \ - "0.0137083000, 0.0122648000, 0.0087406000, -0.002061500, -0.036078400, -0.139536500, -0.441172200", \ - "0.0141356000, 0.0126843000, 0.0092352000, -0.001708000, -0.035730400, -0.139164800, -0.440812000", \ - "0.0208283000, 0.0190780000, 0.0143082000, 0.0015223000, -0.035131300, -0.138615600, -0.440216100"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0176164000, 0.0192762000, 0.0239818000, 0.0369274000, 0.0734874000, 0.1773622000, 0.4767273000", \ - "0.0176359000, 0.0192780000, 0.0239631000, 0.0370001000, 0.0735857000, 0.1777297000, 0.4775456000", \ - "0.0175255000, 0.0191898000, 0.0238810000, 0.0368922000, 0.0734607000, 0.1783911000, 0.4770751000", \ - "0.0173199000, 0.0190043000, 0.0236060000, 0.0366000000, 0.0730872000, 0.1774205000, 0.4738839000", \ - "0.0171696000, 0.0187179000, 0.0232539000, 0.0360982000, 0.0725764000, 0.1767650000, 0.4764656000", \ - "0.0174625000, 0.0190135000, 0.0235042000, 0.0360272000, 0.0722972000, 0.1760254000, 0.4752648000", \ - "0.0181784000, 0.0196872000, 0.0240489000, 0.0367154000, 0.0728178000, 0.1771377000, 0.4758561000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0135706000, 0.0125089000, 0.0095633000, -0.000417400, -0.034488900, -0.138849600, -0.440888800", \ - "0.0134209000, 0.0123772000, 0.0093602000, -0.000613400, -0.034642300, -0.139002900, -0.441028400", \ - "0.0131372000, 0.0120958000, 0.0090653000, -0.000906300, -0.034957400, -0.139289000, -0.441318100", \ - "0.0128628000, 0.0117650000, 0.0086606000, -0.001346500, -0.035336200, -0.139615000, -0.441599400", \ - "0.0126795000, 0.0115514000, 0.0082606000, -0.001595400, -0.035500100, -0.139667100, -0.441589400", \ - "0.0173795000, 0.0158487000, 0.0115546000, -0.001042500, -0.035558500, -0.139414600, -0.441232100", \ - "0.0205556000, 0.0189207000, 0.0148418000, 0.0018122000, -0.034240000, -0.138595100, -0.440011300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0183250000, 0.0199918000, 0.0246875000, 0.0376330000, 0.0740580000, 0.1778716000, 0.4767592000", \ - "0.0182687000, 0.0199096000, 0.0245809000, 0.0375754000, 0.0739624000, 0.1777244000, 0.4759722000", \ - "0.0180863000, 0.0197373000, 0.0244281000, 0.0374406000, 0.0738390000, 0.1776128000, 0.4758183000", \ - "0.0179267000, 0.0195848000, 0.0242513000, 0.0372250000, 0.0735825000, 0.1774139000, 0.4778018000", \ - "0.0181126000, 0.0196854000, 0.0242794000, 0.0368423000, 0.0731948000, 0.1774445000, 0.4779415000", \ - "0.0185051000, 0.0200486000, 0.0245353000, 0.0369772000, 0.0731238000, 0.1768309000, 0.4762775000", \ - "0.0199923000, 0.0215257000, 0.0257593000, 0.0383356000, 0.0744512000, 0.1786416000, 0.4751672000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.5046800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3036469000, 0.3109825000, 0.3272416000, 0.3591873000, 0.4197389000, 0.5425341000, 0.8372256000", \ - "0.3082213000, 0.3155272000, 0.3317725000, 0.3636964000, 0.4242988000, 0.5471095000, 0.8418001000", \ - "0.3201706000, 0.3274384000, 0.3437072000, 0.3756157000, 0.4364955000, 0.5585295000, 0.8530585000", \ - "0.3465254000, 0.3538056000, 0.3703232000, 0.4023283000, 0.4630416000, 0.5851930000, 0.8796797000", \ - "0.4034243000, 0.4108763000, 0.4271148000, 0.4592508000, 0.5195264000, 0.6424534000, 0.9367647000", \ - "0.5245401000, 0.5321097000, 0.5487166000, 0.5811514000, 0.6423587000, 0.7648612000, 1.0595292000", \ - "0.7444334000, 0.7528863000, 0.7731009000, 0.8085691000, 0.8760896000, 1.0068860000, 1.3058643000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1053413000, 0.1112580000, 0.1253911000, 0.1584566000, 0.2424860000, 0.4785437000, 1.1510831000", \ - "0.1096715000, 0.1155787000, 0.1296671000, 0.1627512000, 0.2469402000, 0.4830130000, 1.1558831000", \ - "0.1185980000, 0.1245175000, 0.1386526000, 0.1717389000, 0.2558398000, 0.4915780000, 1.1652536000", \ - "0.1380017000, 0.1438703000, 0.1578663000, 0.1908368000, 0.2748543000, 0.5110303000, 1.1834245000", \ - "0.1747892000, 0.1809438000, 0.1954533000, 0.2290179000, 0.3132529000, 0.5491618000, 1.2227860000", \ - "0.2251782000, 0.2322735000, 0.2482782000, 0.2834717000, 0.3686151000, 0.6041835000, 1.2789759000", \ - "0.2669245000, 0.2760663000, 0.2959073000, 0.3359445000, 0.4228630000, 0.6591585000, 1.3322375000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0419663000, 0.0457436000, 0.0552117000, 0.0764407000, 0.1240837000, 0.2439653000, 0.6015159000", \ - "0.0419274000, 0.0457657000, 0.0552861000, 0.0765355000, 0.1225287000, 0.2439754000, 0.6015470000", \ - "0.0419988000, 0.0457887000, 0.0552560000, 0.0764848000, 0.1231203000, 0.2447028000, 0.5996393000", \ - "0.0415203000, 0.0461238000, 0.0561196000, 0.0758028000, 0.1231175000, 0.2449331000, 0.6008790000", \ - "0.0418095000, 0.0456532000, 0.0550678000, 0.0761454000, 0.1235949000, 0.2449315000, 0.6012708000", \ - "0.0439039000, 0.0480762000, 0.0572000000, 0.0772920000, 0.1249002000, 0.2442936000, 0.6014135000", \ - "0.0530668000, 0.0575982000, 0.0678208000, 0.0893147000, 0.1391303000, 0.2559877000, 0.6065418000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0246735000, 0.0299137000, 0.0435088000, 0.0818246000, 0.1953244000, 0.5307592000, 1.4951532000", \ - "0.0247026000, 0.0298172000, 0.0436054000, 0.0817000000, 0.1953658000, 0.5302991000, 1.4940420000", \ - "0.0247175000, 0.0298753000, 0.0434870000, 0.0817599000, 0.1949436000, 0.5304738000, 1.4983026000", \ - "0.0245326000, 0.0297637000, 0.0433660000, 0.0816814000, 0.1952097000, 0.5308579000, 1.4961925000", \ - "0.0265114000, 0.0316136000, 0.0451177000, 0.0827088000, 0.1951021000, 0.5307814000, 1.4979326000", \ - "0.0320329000, 0.0370250000, 0.0504148000, 0.0867604000, 0.1967699000, 0.5296138000, 1.4941801000", \ - "0.0436267000, 0.0495861000, 0.0626184000, 0.0964941000, 0.2011411000, 0.5314733000, 1.4955531000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2864743000, 0.2937947000, 0.3099744000, 0.3418862000, 0.4023693000, 0.5256144000, 0.8202918000", \ - "0.2901950000, 0.2975396000, 0.3138941000, 0.3458968000, 0.4066694000, 0.5288087000, 0.8234323000", \ - "0.3011179000, 0.3084505000, 0.3247317000, 0.3566990000, 0.4169609000, 0.5396544000, 0.8344052000", \ - "0.3276641000, 0.3349843000, 0.3512675000, 0.3833387000, 0.4438745000, 0.5660433000, 0.8612221000", \ - "0.3882045000, 0.3955151000, 0.4118728000, 0.4437885000, 0.5044285000, 0.6275264000, 0.9220242000", \ - "0.5242036000, 0.5318592000, 0.5486550000, 0.5813536000, 0.6421322000, 0.7657130000, 1.0603791000", \ - "0.7749499000, 0.7846548000, 0.8039845000, 0.8414244000, 0.9094835000, 1.0402499000, 1.3396102000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1014826000, 0.1072505000, 0.1210863000, 0.1539018000, 0.2380020000, 0.4729357000, 1.1470265000", \ - "0.1061088000, 0.1119400000, 0.1257529000, 0.1585661000, 0.2426636000, 0.4787749000, 1.1539332000", \ - "0.1152480000, 0.1210716000, 0.1348989000, 0.1677153000, 0.2518059000, 0.4881615000, 1.1634788000", \ - "0.1343499000, 0.1400923000, 0.1539291000, 0.1865855000, 0.2705474000, 0.5062703000, 1.1809606000", \ - "0.1693119000, 0.1754196000, 0.1898756000, 0.2232900000, 0.3073949000, 0.5429218000, 1.2203583000", \ - "0.2149329000, 0.2217770000, 0.2380024000, 0.2734544000, 0.3586068000, 0.5939970000, 1.2694504000", \ - "0.2471026000, 0.2564111000, 0.2768469000, 0.3176197000, 0.4056875000, 0.6411428000, 1.3153785000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0416743000, 0.0460603000, 0.0555157000, 0.0769778000, 0.1241722000, 0.2439123000, 0.6019487000", \ - "0.0417393000, 0.0461302000, 0.0561854000, 0.0755774000, 0.1230792000, 0.2446632000, 0.5996858000", \ - "0.0418220000, 0.0463009000, 0.0552508000, 0.0767618000, 0.1227729000, 0.2452456000, 0.6019094000", \ - "0.0415903000, 0.0458671000, 0.0550411000, 0.0764775000, 0.1231652000, 0.2443783000, 0.5999761000", \ - "0.0419636000, 0.0461314000, 0.0561966000, 0.0757157000, 0.1224889000, 0.2446681000, 0.6021092000", \ - "0.0446280000, 0.0487485000, 0.0578431000, 0.0778605000, 0.1263519000, 0.2452486000, 0.6019992000", \ - "0.0575704000, 0.0620975000, 0.0726369000, 0.0938059000, 0.1388358000, 0.2577728000, 0.6062695000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0237751000, 0.0288403000, 0.0424324000, 0.0803007000, 0.1939411000, 0.5298332000, 1.4969163000", \ - "0.0237059000, 0.0288471000, 0.0424479000, 0.0802125000, 0.1941820000, 0.5304948000, 1.5003991000", \ - "0.0237181000, 0.0288576000, 0.0424022000, 0.0802359000, 0.1941315000, 0.5298440000, 1.5001107000", \ - "0.0238080000, 0.0288865000, 0.0423731000, 0.0804208000, 0.1940543000, 0.5296814000, 1.4986827000", \ - "0.0259398000, 0.0311081000, 0.0444260000, 0.0817431000, 0.1945501000, 0.5302456000, 1.4980343000", \ - "0.0320526000, 0.0380427000, 0.0507500000, 0.0863392000, 0.1961078000, 0.5277822000, 1.4984917000", \ - "0.0447122000, 0.0506073000, 0.0639349000, 0.0973682000, 0.2006808000, 0.5307562000, 1.4918076000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2509878000, 0.2583450000, 0.2747729000, 0.3066609000, 0.3674833000, 0.4901655000, 0.7849682000", \ - "0.2535532000, 0.2608178000, 0.2771290000, 0.3091596000, 0.3697962000, 0.4928686000, 0.7877837000", \ - "0.2623226000, 0.2696839000, 0.2860152000, 0.3180042000, 0.3787340000, 0.5017565000, 0.7964925000", \ - "0.2866925000, 0.2941460000, 0.3103768000, 0.3421277000, 0.4028136000, 0.5258016000, 0.8209760000", \ - "0.3504708000, 0.3578092000, 0.3732623000, 0.4053117000, 0.4661233000, 0.5893805000, 0.8841466000", \ - "0.4986965000, 0.5065980000, 0.5237345000, 0.5560428000, 0.6171434000, 0.7404054000, 1.0351333000", \ - "0.7575601000, 0.7671451000, 0.7883853000, 0.8289887000, 0.8975551000, 1.0223657000, 1.3213949000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0865690000, 0.0920463000, 0.1052914000, 0.1371347000, 0.2205199000, 0.4547999000, 1.1327657000", \ - "0.0914423000, 0.0968918000, 0.1101509000, 0.1420585000, 0.2255096000, 0.4607549000, 1.1395572000", \ - "0.1011886000, 0.1066486000, 0.1198994000, 0.1517368000, 0.2350969000, 0.4698676000, 1.1469387000", \ - "0.1213265000, 0.1268502000, 0.1400577000, 0.1718307000, 0.2551993000, 0.4908758000, 1.1662630000", \ - "0.1550561000, 0.1609727000, 0.1749775000, 0.2077478000, 0.2913997000, 0.5272424000, 1.2033506000", \ - "0.1944407000, 0.2017119000, 0.2181790000, 0.2529364000, 0.3372022000, 0.5722296000, 1.2525374000", \ - "0.2150243000, 0.2247754000, 0.2460561000, 0.2880589000, 0.3755060000, 0.6109381000, 1.2843223000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0417746000, 0.0461012000, 0.0555019000, 0.0755562000, 0.1230396000, 0.2441433000, 0.6012154000", \ - "0.0419420000, 0.0458050000, 0.0551380000, 0.0763114000, 0.1237029000, 0.2438054000, 0.6012008000", \ - "0.0414913000, 0.0456948000, 0.0560682000, 0.0756953000, 0.1230505000, 0.2440550000, 0.6007391000", \ - "0.0419667000, 0.0457320000, 0.0552120000, 0.0759646000, 0.1226224000, 0.2447081000, 0.6025991000", \ - "0.0416867000, 0.0460500000, 0.0552203000, 0.0756035000, 0.1222569000, 0.2441487000, 0.6031277000", \ - "0.0457568000, 0.0502305000, 0.0583920000, 0.0780097000, 0.1238104000, 0.2452510000, 0.6018192000", \ - "0.0653922000, 0.0704200000, 0.0809069000, 0.1003508000, 0.1410395000, 0.2584877000, 0.6079630000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0219911000, 0.0268560000, 0.0402856000, 0.0784699000, 0.1923523000, 0.5302688000, 1.5001205000", \ - "0.0220910000, 0.0269880000, 0.0402463000, 0.0785034000, 0.1928130000, 0.5296827000, 1.5011018000", \ - "0.0220574000, 0.0269010000, 0.0403256000, 0.0783077000, 0.1926174000, 0.5309989000, 1.5046798000", \ - "0.0224601000, 0.0272202000, 0.0406065000, 0.0786039000, 0.1928457000, 0.5295431000, 1.4973320000", \ - "0.0256374000, 0.0305413000, 0.0435593000, 0.0806724000, 0.1934344000, 0.5294623000, 1.5045505000", \ - "0.0334644000, 0.0379884000, 0.0510411000, 0.0860079000, 0.1952688000, 0.5278015000, 1.5006270000", \ - "0.0475647000, 0.0536214000, 0.0668372000, 0.1000935000, 0.2007499000, 0.5300436000, 1.4929020000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0833609000, 0.0875813000, 0.0971353000, 0.1181849000, 0.1647836000, 0.2740363000, 0.5599711000", \ - "0.0887001000, 0.0928743000, 0.1024832000, 0.1234464000, 0.1700771000, 0.2793166000, 0.5650044000", \ - "0.1015925000, 0.1057262000, 0.1153689000, 0.1363623000, 0.1829955000, 0.2922602000, 0.5780730000", \ - "0.1332377000, 0.1373674000, 0.1469518000, 0.1679232000, 0.2146983000, 0.3240803000, 0.6100594000", \ - "0.1985878000, 0.2033004000, 0.2140069000, 0.2362386000, 0.2840280000, 0.3940790000, 0.6800012000", \ - "0.3031650000, 0.3092684000, 0.3230747000, 0.3509608000, 0.4064823000, 0.5225805000, 0.8096766000", \ - "0.4680522000, 0.4759564000, 0.4941709000, 0.5297129000, 0.5996225000, 0.7319162000, 1.0251212000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0978494000, 0.1037700000, 0.1179012000, 0.1510406000, 0.2354270000, 0.4709430000, 1.1457340000", \ - "0.1020209000, 0.1078599000, 0.1220178000, 0.1551125000, 0.2395221000, 0.4760322000, 1.1490345000", \ - "0.1123948000, 0.1179966000, 0.1321230000, 0.1655182000, 0.2498814000, 0.4864320000, 1.1595366000", \ - "0.1372162000, 0.1430460000, 0.1570099000, 0.1898848000, 0.2740661000, 0.5107152000, 1.1844568000", \ - "0.1835188000, 0.1895186000, 0.2038565000, 0.2373452000, 0.3216613000, 0.5571947000, 1.2340530000", \ - "0.2418953000, 0.2492659000, 0.2652348000, 0.3000640000, 0.3851599000, 0.6205753000, 1.2958855000", \ - "0.2969176000, 0.3062839000, 0.3263895000, 0.3659448000, 0.4516814000, 0.6875672000, 1.3622113000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0172986000, 0.0203407000, 0.0277961000, 0.0467436000, 0.0949803000, 0.2194637000, 0.5882620000", \ - "0.0173154000, 0.0203474000, 0.0278241000, 0.0467378000, 0.0951717000, 0.2194664000, 0.5877993000", \ - "0.0173779000, 0.0203355000, 0.0277808000, 0.0465743000, 0.0951806000, 0.2192648000, 0.5903561000", \ - "0.0174667000, 0.0204436000, 0.0279189000, 0.0467875000, 0.0951352000, 0.2192032000, 0.5879547000", \ - "0.0222910000, 0.0252747000, 0.0323843000, 0.0503619000, 0.0971485000, 0.2200019000, 0.5900147000", \ - "0.0322213000, 0.0360385000, 0.0446591000, 0.0642683000, 0.1107632000, 0.2282651000, 0.5888172000", \ - "0.0478465000, 0.0528034000, 0.0635272000, 0.0877622000, 0.1401743000, 0.2538632000, 0.5933160000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0247235000, 0.0298908000, 0.0434847000, 0.0816233000, 0.1953449000, 0.5290658000, 1.4995761000", \ - "0.0246789000, 0.0297955000, 0.0435552000, 0.0816901000, 0.1953469000, 0.5303776000, 1.4944398000", \ - "0.0246559000, 0.0299081000, 0.0435142000, 0.0817197000, 0.1953325000, 0.5302473000, 1.4940789000", \ - "0.0243817000, 0.0294949000, 0.0431308000, 0.0814774000, 0.1952113000, 0.5299650000, 1.4963437000", \ - "0.0269826000, 0.0320526000, 0.0453543000, 0.0829484000, 0.1952341000, 0.5307668000, 1.4989369000", \ - "0.0340281000, 0.0386272000, 0.0513259000, 0.0865537000, 0.1973467000, 0.5302211000, 1.5003345000", \ - "0.0470179000, 0.0528076000, 0.0650736000, 0.0981009000, 0.2001970000, 0.5327427000, 1.4954018000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31a_4") { - leakage_power () { - value : 0.0067624000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0047345000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0073472000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0053760000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0063516000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0053760000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0046285000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0053745000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0054377000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0053762000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0045377000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0053752000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0442887000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0053785000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0340162000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0053785000; - when : "A1&A2&A3&!B1"; - } - area : 17.516800000; - cell_footprint : "sky130_fd_sc_hd__o31a"; - cell_leakage_power : 0.0097337110; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076170000, 0.0076140000, 0.0076071000, 0.0076099000, 0.0076165000, 0.0076318000, 0.0076670000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007594300, -0.007591200, -0.007584000, -0.007580200, -0.007571300, -0.007551000, -0.007504100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046200000; - } - pin ("A2") { - capacitance : 0.0047900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082011000, 0.0081953000, 0.0081819000, 0.0081829000, 0.0081855000, 0.0081916000, 0.0082054000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008170100, -0.008167700, -0.008162200, -0.008161300, -0.008159400, -0.008154900, -0.008144600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0051160000; - } - pin ("A3") { - capacitance : 0.0042530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078247000, 0.0078202000, 0.0078098000, 0.0078092000, 0.0078077000, 0.0078042000, 0.0077964000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007801600, -0.007800700, -0.007798500, -0.007794900, -0.007786700, -0.007767700, -0.007723800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045870000; - } - pin ("B1") { - capacitance : 0.0045730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0095335000, 0.0095340000, 0.0095352000, 0.0095335000, 0.0095295000, 0.0095204000, 0.0094993000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003309700, -0.003325000, -0.003360300, -0.003322900, -0.003236800, -0.003038100, -0.002580300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047340000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0374524000, 0.0356899000, 0.0303813000, 0.0149562000, -0.038613100, -0.224369100, -0.830753400", \ - "0.0370281000, 0.0351867000, 0.0299298000, 0.0145786000, -0.039054200, -0.224441500, -0.830748900", \ - "0.0369419000, 0.0350868000, 0.0297432000, 0.0144595000, -0.039154700, -0.224874600, -0.831231700", \ - "0.0364613000, 0.0346420000, 0.0294821000, 0.0140240000, -0.039518400, -0.225012900, -0.831618000", \ - "0.0362306000, 0.0344048000, 0.0290799000, 0.0137445000, -0.039930700, -0.225429000, -0.831732500", \ - "0.0364090000, 0.0344546000, 0.0290618000, 0.0136147000, -0.040102600, -0.225741900, -0.831907300", \ - "0.0453627000, 0.0433515000, 0.0372346000, 0.0186143000, -0.039430700, -0.225779600, -0.831994000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0377012000, 0.0397069000, 0.0459615000, 0.0655531000, 0.1254482000, 0.3139736000, 0.9132829000", \ - "0.0375919000, 0.0395313000, 0.0457541000, 0.0653270000, 0.1253099000, 0.3137889000, 0.9135322000", \ - "0.0372411000, 0.0392503000, 0.0454474000, 0.0650129000, 0.1250965000, 0.3131305000, 0.9180829000", \ - "0.0370199000, 0.0389971000, 0.0452834000, 0.0648253000, 0.1246649000, 0.3133659000, 0.9135695000", \ - "0.0370627000, 0.0390032000, 0.0451783000, 0.0642236000, 0.1239827000, 0.3128478000, 0.9129339000", \ - "0.0386496000, 0.0404529000, 0.0463182000, 0.0648973000, 0.1235221000, 0.3108067000, 0.9158160000", \ - "0.0394364000, 0.0411827000, 0.0469120000, 0.0655083000, 0.1244858000, 0.3124955000, 0.9111242000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0329813000, 0.0311497000, 0.0259310000, 0.0105404000, -0.042927900, -0.228432300, -0.834728600", \ - "0.0327945000, 0.0309614000, 0.0256392000, 0.0102804000, -0.043288000, -0.228773900, -0.834966700", \ - "0.0324919000, 0.0306535000, 0.0253180000, 0.0101515000, -0.043334900, -0.228987500, -0.835602000", \ - "0.0322510000, 0.0305162000, 0.0251227000, 0.0097486000, -0.043747900, -0.229459900, -0.835796800", \ - "0.0318365000, 0.0299931000, 0.0246605000, 0.0093397000, -0.044215700, -0.229865100, -0.836133900", \ - "0.0320181000, 0.0300820000, 0.0246380000, 0.0094191000, -0.044330300, -0.230075400, -0.836267500", \ - "0.0423516000, 0.0402881000, 0.0339818000, 0.0151019000, -0.043971200, -0.230180000, -0.836090600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0357494000, 0.0377230000, 0.0438779000, 0.0632606000, 0.1230314000, 0.3112284000, 0.9105112000", \ - "0.0356242000, 0.0375875000, 0.0438399000, 0.0632530000, 0.1230162000, 0.3114445000, 0.9112369000", \ - "0.0355432000, 0.0375146000, 0.0436765000, 0.0630391000, 0.1228214000, 0.3106784000, 0.9122531000", \ - "0.0352446000, 0.0371623000, 0.0434337000, 0.0627337000, 0.1223330000, 0.3107812000, 0.9150747000", \ - "0.0348236000, 0.0367423000, 0.0427668000, 0.0619680000, 0.1214870000, 0.3099923000, 0.9145275000", \ - "0.0354692000, 0.0373152000, 0.0431703000, 0.0617310000, 0.1205381000, 0.3077276000, 0.9097649000", \ - "0.0367525000, 0.0384899000, 0.0442970000, 0.0627736000, 0.1219070000, 0.3100926000, 0.9108028000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0280704000, 0.0263389000, 0.0209795000, 0.0056870000, -0.047887200, -0.233423300, -0.839752300", \ - "0.0279140000, 0.0261206000, 0.0207458000, 0.0055042000, -0.048092200, -0.233780000, -0.840074600", \ - "0.0275025000, 0.0257365000, 0.0204539000, 0.0050780000, -0.048586500, -0.234157700, -0.840456500", \ - "0.0269491000, 0.0251009000, 0.0197905000, 0.0045880000, -0.049002500, -0.234665800, -0.841072700", \ - "0.0267634000, 0.0249493000, 0.0196742000, 0.0043251000, -0.049382200, -0.234976800, -0.841166800", \ - "0.0291132000, 0.0272238000, 0.0215993000, 0.0057492000, -0.048437000, -0.234367800, -0.840472300", \ - "0.0404297000, 0.0382875000, 0.0318219000, 0.0128034000, -0.045524600, -0.232395300, -0.838410800"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0314355000, 0.0334119000, 0.0395496000, 0.0589322000, 0.1184495000, 0.3074006000, 0.9117000000", \ - "0.0314285000, 0.0333879000, 0.0396490000, 0.0590261000, 0.1184522000, 0.3061987000, 0.9118752000", \ - "0.0312813000, 0.0332524000, 0.0394688000, 0.0588296000, 0.1183129000, 0.3059434000, 0.9064943000", \ - "0.0309259000, 0.0328858000, 0.0389840000, 0.0581322000, 0.1177478000, 0.3058981000, 0.9074364000", \ - "0.0305267000, 0.0323775000, 0.0385122000, 0.0574629000, 0.1166943000, 0.3048861000, 0.9069161000", \ - "0.0311588000, 0.0329676000, 0.0388832000, 0.0574165000, 0.1158123000, 0.3033541000, 0.9053837000", \ - "0.0331619000, 0.0349132000, 0.0405343000, 0.0590134000, 0.1176931000, 0.3051097000, 0.9028880000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0242816000, 0.0230799000, 0.0192554000, 0.0055890000, -0.047395500, -0.235224100, -0.842485100", \ - "0.0240316000, 0.0227810000, 0.0189839000, 0.0052602000, -0.047693100, -0.235512400, -0.842755100", \ - "0.0234349000, 0.0222018000, 0.0183651000, 0.0046558000, -0.048185600, -0.235988500, -0.843216200", \ - "0.0232798000, 0.0219648000, 0.0178496000, 0.0037371000, -0.048933400, -0.236568800, -0.843771100", \ - "0.0225054000, 0.0210294000, 0.0167039000, 0.0027087000, -0.049711500, -0.236990700, -0.843987900", \ - "0.0309065000, 0.0290685000, 0.0233813000, 0.0053522000, -0.049733300, -0.236328300, -0.843093300", \ - "0.0391718000, 0.0371878000, 0.0311963000, 0.0126422000, -0.045744600, -0.234017200, -0.840122700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0332226000, 0.0351750000, 0.0413735000, 0.0609860000, 0.1210337000, 0.3096889000, 0.9097556000", \ - "0.0330501000, 0.0349930000, 0.0412150000, 0.0608260000, 0.1208642000, 0.3094619000, 0.9093472000", \ - "0.0327594000, 0.0346770000, 0.0409336000, 0.0605377000, 0.1205440000, 0.3089402000, 0.9102590000", \ - "0.0324730000, 0.0344025000, 0.0407309000, 0.0602309000, 0.1199651000, 0.3087121000, 0.9095331000", \ - "0.0323382000, 0.0342350000, 0.0403726000, 0.0594417000, 0.1189021000, 0.3079864000, 0.9088418000", \ - "0.0344034000, 0.0361870000, 0.0419051000, 0.0602915000, 0.1191071000, 0.3071315000, 0.9090807000", \ - "0.0368218000, 0.0385159000, 0.0442171000, 0.0623508000, 0.1209653000, 0.3091845000, 0.9112658000"); - } - } - max_capacitance : 0.5447490000; - max_transition : 1.5087930000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.3098366000, 0.3149095000, 0.3282722000, 0.3573435000, 0.4167022000, 0.5442508000, 0.8778323000", \ - "0.3144502000, 0.3196314000, 0.3328791000, 0.3619645000, 0.4214095000, 0.5490598000, 0.8822322000", \ - "0.3267244000, 0.3318753000, 0.3451140000, 0.3743139000, 0.4336020000, 0.5611536000, 0.8941994000", \ - "0.3537288000, 0.3588706000, 0.3721742000, 0.4011925000, 0.4600251000, 0.5882868000, 0.9214063000", \ - "0.4113106000, 0.4165048000, 0.4297243000, 0.4587613000, 0.5178980000, 0.6461797000, 0.9794903000", \ - "0.5316192000, 0.5368441000, 0.5503683000, 0.5798881000, 0.6396647000, 0.7677780000, 1.1009769000", \ - "0.7490685000, 0.7550132000, 0.7704142000, 0.8034996000, 0.8693501000, 1.0056374000, 1.3432497000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.1061680000, 0.1103781000, 0.1216891000, 0.1501281000, 0.2251818000, 0.4502835000, 1.1638117000", \ - "0.1105060000, 0.1147222000, 0.1260334000, 0.1544700000, 0.2294590000, 0.4546136000, 1.1677004000", \ - "0.1194225000, 0.1236374000, 0.1349658000, 0.1634148000, 0.2384980000, 0.4637100000, 1.1793527000", \ - "0.1381470000, 0.1423253000, 0.1536229000, 0.1819136000, 0.2566563000, 0.4821276000, 1.1949378000", \ - "0.1743243000, 0.1786612000, 0.1902547000, 0.2189614000, 0.2937650000, 0.5191933000, 1.2318101000", \ - "0.2246563000, 0.2296220000, 0.2423674000, 0.2725619000, 0.3485295000, 0.5735455000, 1.2887217000", \ - "0.2665586000, 0.2729276000, 0.2891369000, 0.3246141000, 0.4033996000, 0.6293627000, 1.3423401000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0396218000, 0.0428114000, 0.0501740000, 0.0694002000, 0.1148395000, 0.2419307000, 0.6523981000", \ - "0.0397799000, 0.0427855000, 0.0501462000, 0.0692900000, 0.1146448000, 0.2414597000, 0.6530337000", \ - "0.0395364000, 0.0424642000, 0.0504457000, 0.0689650000, 0.1146392000, 0.2416762000, 0.6533025000", \ - "0.0396957000, 0.0427089000, 0.0504132000, 0.0693867000, 0.1153139000, 0.2413008000, 0.6525219000", \ - "0.0395467000, 0.0426652000, 0.0502510000, 0.0693113000, 0.1148425000, 0.2409024000, 0.6527078000", \ - "0.0416565000, 0.0446247000, 0.0523944000, 0.0700540000, 0.1156697000, 0.2424450000, 0.6526908000", \ - "0.0506937000, 0.0535326000, 0.0618791000, 0.0811322000, 0.1285813000, 0.2541483000, 0.6581578000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0232955000, 0.0266591000, 0.0369109000, 0.0665248000, 0.1623383000, 0.4792554000, 1.4974914000", \ - "0.0232689000, 0.0267237000, 0.0368442000, 0.0664596000, 0.1623090000, 0.4792741000, 1.4991900000", \ - "0.0232397000, 0.0266186000, 0.0367780000, 0.0664397000, 0.1622037000, 0.4778929000, 1.5025644000", \ - "0.0230359000, 0.0264312000, 0.0365957000, 0.0662763000, 0.1619651000, 0.4793768000, 1.5004075000", \ - "0.0246807000, 0.0281915000, 0.0381112000, 0.0674506000, 0.1624380000, 0.4793385000, 1.4997338000", \ - "0.0296799000, 0.0331918000, 0.0433046000, 0.0712902000, 0.1642267000, 0.4778785000, 1.4992011000", \ - "0.0406619000, 0.0446235000, 0.0548786000, 0.0822403000, 0.1689197000, 0.4810374000, 1.4983571000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.2936887000, 0.2988413000, 0.3121157000, 0.3411857000, 0.3998724000, 0.5282644000, 0.8614625000", \ - "0.2971012000, 0.3022546000, 0.3156042000, 0.3446280000, 0.4041413000, 0.5319232000, 0.8647835000", \ - "0.3073750000, 0.3125012000, 0.3257292000, 0.3549906000, 0.4138010000, 0.5419440000, 0.8750712000", \ - "0.3329927000, 0.3382150000, 0.3514523000, 0.3804553000, 0.4398882000, 0.5674714000, 0.9005380000", \ - "0.3903897000, 0.3955337000, 0.4087636000, 0.4377922000, 0.4970983000, 0.6253913000, 0.9581660000", \ - "0.5170940000, 0.5224727000, 0.5362161000, 0.5665640000, 0.6261758000, 0.7550507000, 1.0881651000", \ - "0.7457677000, 0.7520299000, 0.7680465000, 0.8025304000, 0.8692365000, 1.0059650000, 1.3443910000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0980642000, 0.1019978000, 0.1125943000, 0.1396522000, 0.2128793000, 0.4379080000, 1.1484121000", \ - "0.1028823000, 0.1067883000, 0.1174122000, 0.1444890000, 0.2177182000, 0.4413541000, 1.1536868000", \ - "0.1124562000, 0.1163524000, 0.1269905000, 0.1539740000, 0.2270902000, 0.4509219000, 1.1641232000", \ - "0.1318475000, 0.1357760000, 0.1464291000, 0.1733180000, 0.2464733000, 0.4706806000, 1.1858141000", \ - "0.1676250000, 0.1717758000, 0.1828384000, 0.2105267000, 0.2839163000, 0.5083016000, 1.2237066000", \ - "0.2147527000, 0.2197464000, 0.2324229000, 0.2619979000, 0.3367516000, 0.5610202000, 1.2775623000", \ - "0.2515718000, 0.2580280000, 0.2743793000, 0.3102120000, 0.3887158000, 0.6126740000, 1.3260769000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0400265000, 0.0429835000, 0.0501359000, 0.0694139000, 0.1152263000, 0.2415171000, 0.6530699000", \ - "0.0396087000, 0.0427081000, 0.0505642000, 0.0683332000, 0.1140860000, 0.2418137000, 0.6530517000", \ - "0.0398185000, 0.0426469000, 0.0507383000, 0.0688724000, 0.1153152000, 0.2413318000, 0.6527351000", \ - "0.0398488000, 0.0424430000, 0.0503840000, 0.0685247000, 0.1146807000, 0.2417310000, 0.6530876000", \ - "0.0399137000, 0.0429058000, 0.0502047000, 0.0685946000, 0.1154146000, 0.2415304000, 0.6528321000", \ - "0.0428394000, 0.0456723000, 0.0533627000, 0.0713758000, 0.1175673000, 0.2422658000, 0.6533863000", \ - "0.0547251000, 0.0583519000, 0.0660752000, 0.0850524000, 0.1306946000, 0.2543654000, 0.6589305000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0212369000, 0.0245197000, 0.0342994000, 0.0635491000, 0.1594544000, 0.4779119000, 1.4968796000", \ - "0.0212933000, 0.0245435000, 0.0342366000, 0.0636314000, 0.1594900000, 0.4780822000, 1.4969684000", \ - "0.0212480000, 0.0245094000, 0.0342247000, 0.0635167000, 0.1594387000, 0.4767445000, 1.5014190000", \ - "0.0212758000, 0.0245879000, 0.0341687000, 0.0635903000, 0.1598525000, 0.4779948000, 1.5017826000", \ - "0.0235058000, 0.0268024000, 0.0365682000, 0.0653296000, 0.1600396000, 0.4778548000, 1.5020120000", \ - "0.0293286000, 0.0327192000, 0.0421036000, 0.0698555000, 0.1623616000, 0.4764188000, 1.4991860000", \ - "0.0410798000, 0.0453386000, 0.0556117000, 0.0827800000, 0.1680348000, 0.4792420000, 1.4939195000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.2441892000, 0.2494469000, 0.2626931000, 0.2917021000, 0.3512305000, 0.4789947000, 0.8117884000", \ - "0.2466544000, 0.2518231000, 0.2651143000, 0.2942677000, 0.3536099000, 0.4816275000, 0.8148027000", \ - "0.2547841000, 0.2599586000, 0.2731786000, 0.3022429000, 0.3615039000, 0.4898023000, 0.8228986000", \ - "0.2787329000, 0.2838799000, 0.2971256000, 0.3263731000, 0.3856439000, 0.5126709000, 0.8457588000", \ - "0.3399647000, 0.3451553000, 0.3583547000, 0.3874826000, 0.4467514000, 0.5751787000, 0.9078957000", \ - "0.4846930000, 0.4900632000, 0.5037229000, 0.5330200000, 0.5920422000, 0.7207819000, 1.0541054000", \ - "0.7310584000, 0.7378089000, 0.7549064000, 0.7916003000, 0.8574300000, 0.9893072000, 1.3268734000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0866673000, 0.0905128000, 0.1009060000, 0.1275473000, 0.1999803000, 0.4233893000, 1.1356193000", \ - "0.0915057000, 0.0953823000, 0.1058001000, 0.1325026000, 0.2049496000, 0.4282598000, 1.1415201000", \ - "0.1011920000, 0.1050339000, 0.1154558000, 0.1420813000, 0.2145458000, 0.4382922000, 1.1495370000", \ - "0.1207381000, 0.1245845000, 0.1349214000, 0.1615178000, 0.2340829000, 0.4577631000, 1.1688627000", \ - "0.1524456000, 0.1566595000, 0.1679231000, 0.1955243000, 0.2687890000, 0.4938290000, 1.2041902000", \ - "0.1887492000, 0.1939866000, 0.2072192000, 0.2374963000, 0.3121625000, 0.5360393000, 1.2514974000", \ - "0.2034066000, 0.2105050000, 0.2280702000, 0.2661621000, 0.3457882000, 0.5699277000, 1.2817777000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0399806000, 0.0427200000, 0.0504312000, 0.0684081000, 0.1144953000, 0.2421328000, 0.6522090000", \ - "0.0395760000, 0.0425319000, 0.0504151000, 0.0688243000, 0.1146276000, 0.2415167000, 0.6522690000", \ - "0.0396942000, 0.0426200000, 0.0505371000, 0.0693230000, 0.1142815000, 0.2411986000, 0.6524000000", \ - "0.0399146000, 0.0429467000, 0.0502348000, 0.0690828000, 0.1150077000, 0.2412140000, 0.6519402000", \ - "0.0396916000, 0.0426612000, 0.0501143000, 0.0685699000, 0.1136026000, 0.2414071000, 0.6528459000", \ - "0.0435656000, 0.0466428000, 0.0535853000, 0.0710429000, 0.1163444000, 0.2426332000, 0.6525437000", \ - "0.0621611000, 0.0656916000, 0.0754962000, 0.0916492000, 0.1324340000, 0.2512421000, 0.6582294000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0204080000, 0.0236532000, 0.0334286000, 0.0624840000, 0.1587753000, 0.4780585000, 1.5087931000", \ - "0.0204689000, 0.0237569000, 0.0333818000, 0.0626491000, 0.1588523000, 0.4770270000, 1.5076793000", \ - "0.0205211000, 0.0237076000, 0.0334043000, 0.0625177000, 0.1587757000, 0.4774737000, 1.5008288000", \ - "0.0207751000, 0.0239756000, 0.0337027000, 0.0628462000, 0.1588079000, 0.4775516000, 1.4991733000", \ - "0.0238795000, 0.0270425000, 0.0367179000, 0.0652069000, 0.1598496000, 0.4773426000, 1.4993511000", \ - "0.0314131000, 0.0348852000, 0.0443470000, 0.0713908000, 0.1626545000, 0.4765089000, 1.4999387000", \ - "0.0451881000, 0.0496617000, 0.0606950000, 0.0872732000, 0.1699232000, 0.4786349000, 1.4967663000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0809040000, 0.0838174000, 0.0915737000, 0.1103097000, 0.1557923000, 0.2717870000, 0.5954626000", \ - "0.0861187000, 0.0890201000, 0.0967556000, 0.1154935000, 0.1610088000, 0.2770206000, 0.6006366000", \ - "0.0990241000, 0.1019068000, 0.1096176000, 0.1283618000, 0.1738776000, 0.2899269000, 0.6139819000", \ - "0.1302855000, 0.1331331000, 0.1406797000, 0.1596961000, 0.2051501000, 0.3213608000, 0.6453364000", \ - "0.1946491000, 0.1979628000, 0.2066668000, 0.2268922000, 0.2738177000, 0.3905830000, 0.7148589000", \ - "0.2970398000, 0.3013455000, 0.3125358000, 0.3378693000, 0.3927270000, 0.5170189000, 0.8420455000", \ - "0.4608535000, 0.4664574000, 0.4809455000, 0.5134987000, 0.5832576000, 0.7255156000, 1.0592047000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0978136000, 0.1020376000, 0.1133196000, 0.1417992000, 0.2167933000, 0.4421977000, 1.1548702000", \ - "0.1018858000, 0.1061017000, 0.1173966000, 0.1458666000, 0.2208983000, 0.4462050000, 1.1591513000", \ - "0.1120852000, 0.1162438000, 0.1275762000, 0.1560200000, 0.2310571000, 0.4572419000, 1.1704220000", \ - "0.1366850000, 0.1408562000, 0.1520552000, 0.1801839000, 0.2548368000, 0.4802286000, 1.1939285000", \ - "0.1826664000, 0.1869415000, 0.1983152000, 0.2267654000, 0.3014491000, 0.5268491000, 1.2403307000", \ - "0.2398982000, 0.2449264000, 0.2576386000, 0.2867797000, 0.3622448000, 0.5879664000, 1.3028135000", \ - "0.2917714000, 0.2982986000, 0.3145345000, 0.3492385000, 0.4261384000, 0.6508758000, 1.3648640000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0161201000, 0.0180404000, 0.0239189000, 0.0409052000, 0.0889642000, 0.2201313000, 0.6403456000", \ - "0.0159878000, 0.0182501000, 0.0240149000, 0.0408264000, 0.0889084000, 0.2200879000, 0.6405007000", \ - "0.0161192000, 0.0181826000, 0.0240255000, 0.0408889000, 0.0889281000, 0.2199462000, 0.6399541000", \ - "0.0161514000, 0.0183871000, 0.0241796000, 0.0409959000, 0.0890404000, 0.2203370000, 0.6394403000", \ - "0.0210273000, 0.0231833000, 0.0287760000, 0.0449028000, 0.0911154000, 0.2209513000, 0.6401494000", \ - "0.0310027000, 0.0335959000, 0.0404460000, 0.0582679000, 0.1050338000, 0.2299304000, 0.6412355000", \ - "0.0464880000, 0.0497236000, 0.0583906000, 0.0808758000, 0.1338744000, 0.2574046000, 0.6460463000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0232670000, 0.0267044000, 0.0368030000, 0.0665504000, 0.1622061000, 0.4793307000, 1.5000113000", \ - "0.0232527000, 0.0267140000, 0.0367880000, 0.0665247000, 0.1622691000, 0.4793014000, 1.4994870000", \ - "0.0232549000, 0.0266794000, 0.0367315000, 0.0665373000, 0.1623960000, 0.4785748000, 1.5021320000", \ - "0.0228638000, 0.0263047000, 0.0363305000, 0.0662053000, 0.1621585000, 0.4788377000, 1.5015204000", \ - "0.0247263000, 0.0281799000, 0.0379738000, 0.0673599000, 0.1622730000, 0.4793355000, 1.5012673000", \ - "0.0316054000, 0.0348363000, 0.0435715000, 0.0711589000, 0.1643710000, 0.4783868000, 1.5013393000", \ - "0.0435095000, 0.0475295000, 0.0572618000, 0.0825910000, 0.1682882000, 0.4806842000, 1.4989773000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31ai_1") { - leakage_power () { - value : 0.0009437000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0066736000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0027392000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0003753000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0025576000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0003745000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0020324000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0003754000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0033837000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0003749000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0021118000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0003754000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0021108000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0003754000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0020161000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0003754000; - when : "A1&A2&A3&!B1"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__o31ai"; - cell_leakage_power : 0.0016997230; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040123000, 0.0040145000, 0.0040194000, 0.0040163000, 0.0040092000, 0.0039929000, 0.0039552000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004009600, -0.004006400, -0.003998900, -0.004000000, -0.004002400, -0.004007900, -0.004020600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024000000; - } - pin ("A2") { - capacitance : 0.0025250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042044000, 0.0042134000, 0.0042343000, 0.0042350000, 0.0042365000, 0.0042402000, 0.0042486000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004228800, -0.004229400, -0.004230600, -0.004230200, -0.004229200, -0.004227000, -0.004221700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026720000; - } - pin ("A3") { - capacitance : 0.0024790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042679000, 0.0042693000, 0.0042725000, 0.0042731000, 0.0042746000, 0.0042779000, 0.0042856000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004276500, -0.004274600, -0.004270200, -0.004270800, -0.004272200, -0.004275400, -0.004282700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026650000; - } - pin ("B1") { - capacitance : 0.0023300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048665000, 0.0048751000, 0.0048951000, 0.0048911000, 0.0048819000, 0.0048605000, 0.0048114000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001667000, -0.001667000, -0.001667100, -0.001650600, -0.001612600, -0.001525000, -0.001323200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023940000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0067200000, 0.0058072000, 0.0038430000, -0.000315100, -0.009226200, -0.028310600, -0.069232600", \ - "0.0065928000, 0.0056856000, 0.0037257000, -0.000434500, -0.009340500, -0.028423600, -0.069367800", \ - "0.0064740000, 0.0055534000, 0.0035988000, -0.000570300, -0.009454900, -0.028541600, -0.069466800", \ - "0.0063193000, 0.0054169000, 0.0034785000, -0.000683600, -0.009549400, -0.028647800, -0.069568900", \ - "0.0062218000, 0.0053139000, 0.0033886000, -0.000728900, -0.009580600, -0.028630200, -0.069551500", \ - "0.0064688000, 0.0055525000, 0.0035911000, -0.000588900, -0.009613400, -0.028767300, -0.069635700", \ - "0.0071682000, 0.0062198000, 0.0042332000, -3.75000e-05, -0.009038900, -0.028326300, -0.069546100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0144083000, 0.0153296000, 0.0172955000, 0.0215159000, 0.0304400000, 0.0494865000, 0.0900665000", \ - "0.0142654000, 0.0151765000, 0.0171879000, 0.0214020000, 0.0303583000, 0.0494315000, 0.0900404000", \ - "0.0140965000, 0.0150341000, 0.0170278000, 0.0212605000, 0.0302768000, 0.0493369000, 0.0899692000", \ - "0.0139674000, 0.0148937000, 0.0168828000, 0.0211339000, 0.0301371000, 0.0492358000, 0.0898990000", \ - "0.0138828000, 0.0148150000, 0.0167981000, 0.0210346000, 0.0299869000, 0.0490873000, 0.0897022000", \ - "0.0138592000, 0.0148101000, 0.0168066000, 0.0209646000, 0.0299212000, 0.0489596000, 0.0896457000", \ - "0.0138066000, 0.0147293000, 0.0166385000, 0.0210872000, 0.0301907000, 0.0491072000, 0.0897897000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0054979000, 0.0045931000, 0.0026413000, -0.001534300, -0.010488200, -0.029653600, -0.070646100", \ - "0.0054622000, 0.0045539000, 0.0026082000, -0.001558600, -0.010505700, -0.029653400, -0.070653700", \ - "0.0053413000, 0.0044406000, 0.0025126000, -0.001626500, -0.010545700, -0.029682200, -0.070663500", \ - "0.0051112000, 0.0042305000, 0.0023297000, -0.001773700, -0.010659900, -0.029755200, -0.070710600", \ - "0.0050288000, 0.0041550000, 0.0021553000, -0.001993000, -0.010810500, -0.029825100, -0.070733400", \ - "0.0049589000, 0.0040507000, 0.0021158000, -0.002033900, -0.010921400, -0.030058000, -0.070874800", \ - "0.0054936000, 0.0045452000, 0.0025446000, -0.001670000, -0.010697800, -0.029884100, -0.070945600"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0124631000, 0.0133825000, 0.0153460000, 0.0195683000, 0.0285333000, 0.0475118000, 0.0881180000", \ - "0.0122672000, 0.0132254000, 0.0152230000, 0.0194385000, 0.0283990000, 0.0474543000, 0.0880197000", \ - "0.0120749000, 0.0130181000, 0.0150162000, 0.0192562000, 0.0282535000, 0.0473580000, 0.0879310000", \ - "0.0119185000, 0.0128583000, 0.0148472000, 0.0191080000, 0.0281033000, 0.0472374000, 0.0879322000", \ - "0.0118151000, 0.0127473000, 0.0147329000, 0.0189518000, 0.0279215000, 0.0470661000, 0.0877293000", \ - "0.0117459000, 0.0126799000, 0.0146916000, 0.0189148000, 0.0279426000, 0.0469837000, 0.0876600000", \ - "0.0119441000, 0.0129318000, 0.0149294000, 0.0190997000, 0.0280526000, 0.0469638000, 0.0877902000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0042313000, 0.0033517000, 0.0014210000, -0.002739500, -0.011692400, -0.030888300, -0.071915600", \ - "0.0041240000, 0.0032697000, 0.0013800000, -0.002735100, -0.011643100, -0.030804600, -0.071821200", \ - "0.0039077000, 0.0030783000, 0.0012434000, -0.002811000, -0.011664000, -0.030769600, -0.071753900", \ - "0.0036042000, 0.0027681000, 0.0009677000, -0.003035400, -0.011796000, -0.030817400, -0.071754000", \ - "0.0034858000, 0.0026267000, 0.0007748000, -0.003340600, -0.012041300, -0.030975200, -0.071813200", \ - "0.0034439000, 0.0025077000, 0.0005960000, -0.003471700, -0.012252600, -0.031290400, -0.072045800", \ - "0.0041171000, 0.0031434000, 0.0011384000, -0.003160000, -0.012165800, -0.031264700, -0.072198100"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0101993000, 0.0111285000, 0.0131527000, 0.0173736000, 0.0263289000, 0.0453729000, 0.0858713000", \ - "0.0099185000, 0.0108687000, 0.0129011000, 0.0171691000, 0.0261792000, 0.0452888000, 0.0858318000", \ - "0.0096319000, 0.0105748000, 0.0126040000, 0.0168975000, 0.0259758000, 0.0450845000, 0.0857262000", \ - "0.0094642000, 0.0103367000, 0.0123717000, 0.0166699000, 0.0257337000, 0.0449105000, 0.0856115000", \ - "0.0095872000, 0.0105094000, 0.0124787000, 0.0166421000, 0.0255726000, 0.0446859000, 0.0855298000", \ - "0.0100574000, 0.0109908000, 0.0129814000, 0.0172026000, 0.0256080000, 0.0446232000, 0.0853600000", \ - "0.0110812000, 0.0120488000, 0.0138964000, 0.0178564000, 0.0265068000, 0.0453498000, 0.0855254000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0043664000, 0.0034808000, 0.0015621000, -0.002553800, -0.011403100, -0.030470600, -0.071382400", \ - "0.0042221000, 0.0033387000, 0.0014255000, -0.002640400, -0.011462500, -0.030512800, -0.071403600", \ - "0.0040241000, 0.0031437000, 0.0012556000, -0.002784600, -0.011572700, -0.030572800, -0.071437800", \ - "0.0038603000, 0.0029670000, 0.0010608000, -0.003018400, -0.011739700, -0.030732900, -0.071536500", \ - "0.0037836000, 0.0028686000, 0.0009262000, -0.003129300, -0.012005500, -0.030954300, -0.071707700", \ - "0.0042824000, 0.0033486000, 0.0013370000, -0.002713500, -0.012006800, -0.030954400, -0.071765200", \ - "0.0057394000, 0.0047417000, 0.0026701000, -0.001733600, -0.010826500, -0.030320100, -0.071813100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010684870, 0.0022833300, 0.0048794160, 0.0104271900, 0.0222826300, 0.0476174100"); - values("0.0064682000, 0.0074805000, 0.0095774000, 0.0139008000, 0.0228998000, 0.0419307000, 0.0824886000", \ - "0.0061852000, 0.0072117000, 0.0093517000, 0.0137157000, 0.0227850000, 0.0418579000, 0.0824149000", \ - "0.0059543000, 0.0068956000, 0.0089862000, 0.0134096000, 0.0224709000, 0.0416268000, 0.0823529000", \ - "0.0058501000, 0.0068168000, 0.0088387000, 0.0131031000, 0.0221591000, 0.0413808000, 0.0820340000", \ - "0.0061678000, 0.0070805000, 0.0090108000, 0.0131444000, 0.0220429000, 0.0412240000, 0.0819379000", \ - "0.0064847000, 0.0073593000, 0.0094884000, 0.0139495000, 0.0227209000, 0.0410503000, 0.0815536000", \ - "0.0086782000, 0.0094752000, 0.0111486000, 0.0149587000, 0.0233968000, 0.0421716000, 0.0825084000"); - } - } - max_capacitance : 0.0476170000; - max_transition : 1.4872860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0407562000, 0.0445357000, 0.0521180000, 0.0675238000, 0.0984540000, 0.1618186000, 0.2942168000", \ - "0.0453768000, 0.0490984000, 0.0566869000, 0.0720629000, 0.1029952000, 0.1663131000, 0.2988803000", \ - "0.0556682000, 0.0592887000, 0.0667916000, 0.0820918000, 0.1129499000, 0.1763109000, 0.3088212000", \ - "0.0756528000, 0.0796200000, 0.0878568000, 0.1035591000, 0.1343362000, 0.1977654000, 0.3304072000", \ - "0.1052417000, 0.1106766000, 0.1217861000, 0.1423498000, 0.1793242000, 0.2462420000, 0.3791941000", \ - "0.1386596000, 0.1467539000, 0.1636288000, 0.1951563000, 0.2485039000, 0.3376373000, 0.4888700000", \ - "0.1558361000, 0.1686289000, 0.1959656000, 0.2440476000, 0.3281667000, 0.4654813000, 0.6772587000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1656764000, 0.1784766000, 0.2049495000, 0.2609478000, 0.3791051000, 0.6306757000, 1.1659577000", \ - "0.1701895000, 0.1828407000, 0.2096752000, 0.2658105000, 0.3847984000, 0.6359177000, 1.1715610000", \ - "0.1818779000, 0.1943790000, 0.2208815000, 0.2777704000, 0.3968679000, 0.6484781000, 1.1845043000", \ - "0.2061366000, 0.2191430000, 0.2457372000, 0.3024596000, 0.4212364000, 0.6736705000, 1.2096868000", \ - "0.2583928000, 0.2710783000, 0.2974581000, 0.3533755000, 0.4726573000, 0.7250085000, 1.2616364000", \ - "0.3495980000, 0.3639511000, 0.3964070000, 0.4588483000, 0.5831629000, 0.8350573000, 1.3712872000", \ - "0.5001728000, 0.5205623000, 0.5624345000, 0.6422753000, 0.7950265000, 1.0795065000, 1.6233104000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0321004000, 0.0363439000, 0.0452294000, 0.0637451000, 0.1024045000, 0.1843394000, 0.3580770000", \ - "0.0317876000, 0.0361344000, 0.0450354000, 0.0635840000, 0.1023492000, 0.1837207000, 0.3595440000", \ - "0.0318352000, 0.0360229000, 0.0447337000, 0.0631239000, 0.1020559000, 0.1842539000, 0.3581153000", \ - "0.0383237000, 0.0419762000, 0.0495944000, 0.0658794000, 0.1028132000, 0.1841867000, 0.3593506000", \ - "0.0570606000, 0.0613233000, 0.0695302000, 0.0861814000, 0.1188951000, 0.1908870000, 0.3594069000", \ - "0.0940595000, 0.0995077000, 0.1110381000, 0.1320973000, 0.1706544000, 0.2416868000, 0.3870015000", \ - "0.1612938000, 0.1703290000, 0.1868983000, 0.2167115000, 0.2724705000, 0.3626514000, 0.5167807000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1247821000, 0.1415965000, 0.1763943000, 0.2514533000, 0.4095277000, 0.7487528000, 1.4692667000", \ - "0.1250534000, 0.1412886000, 0.1766277000, 0.2509858000, 0.4097865000, 0.7464308000, 1.4643761000", \ - "0.1250239000, 0.1415274000, 0.1764582000, 0.2509406000, 0.4097481000, 0.7461909000, 1.4667779000", \ - "0.1249348000, 0.1414862000, 0.1763539000, 0.2515523000, 0.4098168000, 0.7466419000, 1.4648209000", \ - "0.1303413000, 0.1459917000, 0.1797329000, 0.2521622000, 0.4094908000, 0.7470662000, 1.4661516000", \ - "0.1603713000, 0.1770223000, 0.2104535000, 0.2790856000, 0.4248139000, 0.7500429000, 1.4656025000", \ - "0.2302297000, 0.2477656000, 0.2852496000, 0.3592630000, 0.5086345000, 0.8097953000, 1.4872856000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0407228000, 0.0440943000, 0.0509767000, 0.0652707000, 0.0950194000, 0.1576978000, 0.2906301000", \ - "0.0454486000, 0.0488438000, 0.0557504000, 0.0700705000, 0.0998314000, 0.1625308000, 0.2954798000", \ - "0.0550696000, 0.0584095000, 0.0653763000, 0.0797531000, 0.1095977000, 0.1723422000, 0.3055978000", \ - "0.0723199000, 0.0764362000, 0.0842534000, 0.0998523000, 0.1300651000, 0.1929488000, 0.3263042000", \ - "0.0956301000, 0.1014386000, 0.1127259000, 0.1334389000, 0.1713435000, 0.2395953000, 0.3734163000", \ - "0.1150029000, 0.1242009000, 0.1422136000, 0.1748198000, 0.2312627000, 0.3231782000, 0.4789180000", \ - "0.1041956000, 0.1194739000, 0.1483092000, 0.2012480000, 0.2913371000, 0.4340363000, 0.6528791000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1553010000, 0.1681444000, 0.1944834000, 0.2509004000, 0.3688727000, 0.6203902000, 1.1558805000", \ - "0.1588102000, 0.1710164000, 0.1984198000, 0.2542732000, 0.3733859000, 0.6247491000, 1.1606259000", \ - "0.1694544000, 0.1823395000, 0.2088999000, 0.2659433000, 0.3849167000, 0.6366372000, 1.1724671000", \ - "0.1955656000, 0.2078743000, 0.2351174000, 0.2912770000, 0.4106727000, 0.6631844000, 1.1994941000", \ - "0.2554400000, 0.2679568000, 0.2947407000, 0.3507658000, 0.4701059000, 0.7226390000, 1.2591568000", \ - "0.3666642000, 0.3831776000, 0.4190593000, 0.4849446000, 0.6090510000, 0.8614136000, 1.3980569000", \ - "0.5591634000, 0.5840115000, 0.6320955000, 0.7241150000, 0.8863730000, 1.1764483000, 1.7218977000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0267577000, 0.0308425000, 0.0392077000, 0.0574503000, 0.0964356000, 0.1798047000, 0.3562779000", \ - "0.0267934000, 0.0308204000, 0.0391954000, 0.0574235000, 0.0964079000, 0.1795458000, 0.3562603000", \ - "0.0270355000, 0.0309618000, 0.0392574000, 0.0573574000, 0.0961574000, 0.1791454000, 0.3567258000", \ - "0.0335262000, 0.0372048000, 0.0447910000, 0.0608503000, 0.0975797000, 0.1789546000, 0.3563997000", \ - "0.0516072000, 0.0558773000, 0.0644355000, 0.0812160000, 0.1152358000, 0.1882581000, 0.3576642000", \ - "0.0875225000, 0.0938330000, 0.1054451000, 0.1269810000, 0.1670678000, 0.2398929000, 0.3892939000", \ - "0.1551116000, 0.1649376000, 0.1823735000, 0.2135627000, 0.2680197000, 0.3607874000, 0.5204081000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1248402000, 0.1416273000, 0.1763922000, 0.2512117000, 0.4093492000, 0.7456115000, 1.4688512000", \ - "0.1248338000, 0.1414808000, 0.1768143000, 0.2510775000, 0.4094196000, 0.7464536000, 1.4684961000", \ - "0.1247717000, 0.1416170000, 0.1763965000, 0.2510072000, 0.4097641000, 0.7461779000, 1.4634297000", \ - "0.1251281000, 0.1414038000, 0.1765851000, 0.2512271000, 0.4095124000, 0.7468004000, 1.4647704000", \ - "0.1338200000, 0.1489031000, 0.1817022000, 0.2525806000, 0.4096319000, 0.7473218000, 1.4650009000", \ - "0.1765916000, 0.1912448000, 0.2255611000, 0.2887275000, 0.4281423000, 0.7493958000, 1.4656812000", \ - "0.2690470000, 0.2872096000, 0.3266604000, 0.3992918000, 0.5358988000, 0.8184552000, 1.4823528000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0333256000, 0.0362895000, 0.0424902000, 0.0556172000, 0.0833322000, 0.1422083000, 0.2690873000", \ - "0.0379227000, 0.0409366000, 0.0472736000, 0.0604816000, 0.0883406000, 0.1474215000, 0.2738409000", \ - "0.0472794000, 0.0504877000, 0.0570466000, 0.0704955000, 0.0983448000, 0.1578108000, 0.2841308000", \ - "0.0614163000, 0.0657882000, 0.0745873000, 0.0904196000, 0.1195250000, 0.1792199000, 0.3058286000", \ - "0.0765422000, 0.0834874000, 0.0966809000, 0.1205029000, 0.1598099000, 0.2270945000, 0.3542882000", \ - "0.0825107000, 0.0932511000, 0.1143607000, 0.1520735000, 0.2127862000, 0.3081012000, 0.4607054000", \ - "0.0456502000, 0.0644747000, 0.0998049000, 0.1604994000, 0.2591264000, 0.4090112000, 0.6356742000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1277465000, 0.1400227000, 0.1672578000, 0.2232927000, 0.3420499000, 0.5937116000, 1.1294818000", \ - "0.1290859000, 0.1419117000, 0.1688478000, 0.2260932000, 0.3455005000, 0.5970644000, 1.1330101000", \ - "0.1371250000, 0.1500623000, 0.1771013000, 0.2344206000, 0.3540860000, 0.6071996000, 1.1438144000", \ - "0.1628671000, 0.1747842000, 0.2017599000, 0.2581674000, 0.3780339000, 0.6316141000, 1.1686945000", \ - "0.2271220000, 0.2402469000, 0.2658229000, 0.3207188000, 0.4392464000, 0.6916882000, 1.2285852000", \ - "0.3509540000, 0.3689277000, 0.4029937000, 0.4698960000, 0.5916497000, 0.8414595000, 1.3774090000", \ - "0.5499002000, 0.5776352000, 0.6296000000, 0.7275340000, 0.8998350000, 1.1946849000, 1.7200997000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0183005000, 0.0220543000, 0.0302422000, 0.0476473000, 0.0845397000, 0.1622030000, 0.3308099000", \ - "0.0183378000, 0.0220549000, 0.0302089000, 0.0472721000, 0.0845072000, 0.1623224000, 0.3351467000", \ - "0.0194415000, 0.0228710000, 0.0305210000, 0.0473412000, 0.0839575000, 0.1625150000, 0.3350797000", \ - "0.0278085000, 0.0311864000, 0.0385852000, 0.0529967000, 0.0863357000, 0.1640845000, 0.3303602000", \ - "0.0467285000, 0.0508223000, 0.0593979000, 0.0756639000, 0.1074826000, 0.1736571000, 0.3340448000", \ - "0.0829295000, 0.0892108000, 0.1012239000, 0.1232352000, 0.1621395000, 0.2304933000, 0.3673261000", \ - "0.1533352000, 0.1622453000, 0.1792006000, 0.2112743000, 0.2654817000, 0.3557308000, 0.5112881000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.1246158000, 0.1412695000, 0.1767638000, 0.2509638000, 0.4093990000, 0.7481383000, 1.4671120000", \ - "0.1249823000, 0.1413490000, 0.1763751000, 0.2508631000, 0.4115079000, 0.7461167000, 1.4655833000", \ - "0.1246831000, 0.1411982000, 0.1763099000, 0.2510247000, 0.4092990000, 0.7471567000, 1.4650247000", \ - "0.1229883000, 0.1401855000, 0.1760958000, 0.2508567000, 0.4095509000, 0.7468494000, 1.4696316000", \ - "0.1387724000, 0.1529700000, 0.1835529000, 0.2530193000, 0.4091377000, 0.7486800000, 1.4646737000", \ - "0.1927053000, 0.2099049000, 0.2424289000, 0.3035341000, 0.4356249000, 0.7478892000, 1.4655904000", \ - "0.2868490000, 0.3094111000, 0.3574834000, 0.4385948000, 0.5857552000, 0.8504021000, 1.4846834000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0324259000, 0.0362662000, 0.0440235000, 0.0594846000, 0.0904980000, 0.1539705000, 0.2865308000", \ - "0.0365699000, 0.0403352000, 0.0480366000, 0.0635678000, 0.0946812000, 0.1582166000, 0.2907909000", \ - "0.0475830000, 0.0510735000, 0.0584377000, 0.0739401000, 0.1050013000, 0.1686047000, 0.3012412000", \ - "0.0692739000, 0.0739429000, 0.0829441000, 0.0990161000, 0.1290351000, 0.1927304000, 0.3247584000", \ - "0.0963297000, 0.1030886000, 0.1161283000, 0.1391820000, 0.1815276000, 0.2481333000, 0.3813808000", \ - "0.1232879000, 0.1334050000, 0.1530440000, 0.1888623000, 0.2505509000, 0.3524055000, 0.5102505000", \ - "0.1306770000, 0.1454807000, 0.1736627000, 0.2293071000, 0.3240139000, 0.4798702000, 0.7209959000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0295613000, 0.0337539000, 0.0423237000, 0.0600183000, 0.0969086000, 0.1745592000, 0.3411762000", \ - "0.0346584000, 0.0388293000, 0.0474619000, 0.0650087000, 0.1021980000, 0.1805674000, 0.3470406000", \ - "0.0479968000, 0.0518904000, 0.0603634000, 0.0782075000, 0.1151780000, 0.1935540000, 0.3597527000", \ - "0.0736000000, 0.0798180000, 0.0908260000, 0.1095489000, 0.1465914000, 0.2249823000, 0.3913073000", \ - "0.1134198000, 0.1232388000, 0.1411697000, 0.1716691000, 0.2198486000, 0.2981356000, 0.4631562000", \ - "0.1777774000, 0.1930992000, 0.2219106000, 0.2709024000, 0.3481700000, 0.4628945000, 0.6329191000", \ - "0.2887309000, 0.3120369000, 0.3546535000, 0.4291238000, 0.5513777000, 0.7380571000, 1.0024606000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0317682000, 0.0360371000, 0.0448539000, 0.0635246000, 0.1019197000, 0.1837676000, 0.3589648000", \ - "0.0312866000, 0.0357227000, 0.0447446000, 0.0633446000, 0.1020621000, 0.1842886000, 0.3580882000", \ - "0.0319112000, 0.0358629000, 0.0444502000, 0.0626398000, 0.1019657000, 0.1842282000, 0.3581800000", \ - "0.0440452000, 0.0479120000, 0.0550369000, 0.0691179000, 0.1037952000, 0.1837656000, 0.3581617000", \ - "0.0667216000, 0.0720806000, 0.0821231000, 0.1019912000, 0.1320011000, 0.1981761000, 0.3601150000", \ - "0.1069542000, 0.1150373000, 0.1301897000, 0.1576951000, 0.2030520000, 0.2755851000, 0.4084243000", \ - "0.1757976000, 0.1884181000, 0.2136671000, 0.2571268000, 0.3261540000, 0.4352718000, 0.5999529000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010684900, 0.0022833300, 0.0048794200, 0.0104272000, 0.0222826000, 0.0476174000"); - values("0.0315183000, 0.0376303000, 0.0501520000, 0.0762439000, 0.1297895000, 0.2405490000, 0.4758290000", \ - "0.0316390000, 0.0375700000, 0.0501491000, 0.0763108000, 0.1297794000, 0.2407483000, 0.4761858000", \ - "0.0342023000, 0.0393520000, 0.0505867000, 0.0763470000, 0.1297595000, 0.2406779000, 0.4761060000", \ - "0.0522753000, 0.0550759000, 0.0626705000, 0.0831395000, 0.1306965000, 0.2406209000, 0.4760384000", \ - "0.0899749000, 0.0942929000, 0.1032326000, 0.1203389000, 0.1557260000, 0.2474365000, 0.4759296000", \ - "0.1514371000, 0.1581650000, 0.1719760000, 0.1968244000, 0.2401739000, 0.3126664000, 0.5013505000", \ - "0.2503656000, 0.2605824000, 0.2821245000, 0.3234399000, 0.3923252000, 0.4997072000, 0.6700263000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31ai_2") { - leakage_power () { - value : 0.0022951000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 1.0930683e-05; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0068213000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0008629000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0058747000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0008634000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0037591000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0008625000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0056503000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0008681000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0037455000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0008629000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0037510000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0008662000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0036359000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0008643000; - when : "A1&A2&A3&!B1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__o31ai"; - cell_leakage_power : 0.0025996280; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044550000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080408000, 0.0080351000, 0.0080222000, 0.0080259000, 0.0080345000, 0.0080542000, 0.0080998000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008016700, -0.008016100, -0.008014500, -0.008016200, -0.008020100, -0.008029000, -0.008049700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046640000; - } - pin ("A2") { - capacitance : 0.0043700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079339000, 0.0079345000, 0.0079360000, 0.0079377000, 0.0079416000, 0.0079506000, 0.0079713000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007924200, -0.007923700, -0.007922500, -0.007923700, -0.007926500, -0.007932900, -0.007947600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046620000; - } - pin ("A3") { - capacitance : 0.0043160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039600000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079544000, 0.0079534000, 0.0079511000, 0.0079528000, 0.0079565000, 0.0079652000, 0.0079853000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007954600, -0.007950200, -0.007940200, -0.007941600, -0.007945000, -0.007952600, -0.007970300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046710000; - } - pin ("B1") { - capacitance : 0.0044040000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092119000, 0.0092082000, 0.0091999000, 0.0091971000, 0.0091907000, 0.0091760000, 0.0091421000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002688800, -0.002702100, -0.002733000, -0.002694800, -0.002606800, -0.002403900, -0.001936100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045400000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0148542000, 0.0137882000, 0.0112841000, 0.0054389000, -0.008112100, -0.039815500, -0.114065900", \ - "0.0146010000, 0.0135134000, 0.0110200000, 0.0051999000, -0.008374300, -0.040079800, -0.114333000", \ - "0.0142622000, 0.0132147000, 0.0107193000, 0.0048663000, -0.008679300, -0.040361400, -0.114620600", \ - "0.0139298000, 0.0128721000, 0.0104342000, 0.0046027000, -0.008958400, -0.040618700, -0.114860400", \ - "0.0136181000, 0.0125825000, 0.0101301000, 0.0043591000, -0.009070400, -0.040675700, -0.114876400", \ - "0.0139400000, 0.0129214000, 0.0103874000, 0.0045426000, -0.009149900, -0.040907900, -0.115111900", \ - "0.0152842000, 0.0141768000, 0.0116734000, 0.0057633000, -0.008139300, -0.040137200, -0.114942600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0271261000, 0.0281945000, 0.0307507000, 0.0366161000, 0.0503094000, 0.0820568000, 0.1556599000", \ - "0.0267813000, 0.0278715000, 0.0304004000, 0.0363551000, 0.0501113000, 0.0818551000, 0.1556866000", \ - "0.0263580000, 0.0274904000, 0.0300364000, 0.0360208000, 0.0497950000, 0.0816314000, 0.1553949000", \ - "0.0260827000, 0.0271416000, 0.0297263000, 0.0356596000, 0.0494980000, 0.0813976000, 0.1553515000", \ - "0.0257608000, 0.0268426000, 0.0293973000, 0.0353104000, 0.0490697000, 0.0809819000, 0.1549592000", \ - "0.0257790000, 0.0268944000, 0.0293748000, 0.0352656000, 0.0489355000, 0.0808051000, 0.1546631000", \ - "0.0252651000, 0.0263133000, 0.0290267000, 0.0352465000, 0.0491764000, 0.0808378000, 0.1545096000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0110698000, 0.0100068000, 0.0075279000, 0.0017086000, -0.011909400, -0.043770700, -0.118273900", \ - "0.0109946000, 0.0099373000, 0.0074648000, 0.0016607000, -0.011931100, -0.043799700, -0.118222400", \ - "0.0108151000, 0.0097619000, 0.0073231000, 0.0015669000, -0.011998300, -0.043815700, -0.118246100", \ - "0.0104062000, 0.0093533000, 0.0069674000, 0.0012829000, -0.012181600, -0.043948800, -0.118312100", \ - "0.0102982000, 0.0092434000, 0.0068066000, 0.0009021000, -0.012481100, -0.044025700, -0.118331700", \ - "0.0103600000, 0.0092624000, 0.0067807000, 0.0009325000, -0.012566900, -0.044431700, -0.118567100", \ - "0.0119185000, 0.0107535000, 0.0082162000, 0.0023272000, -0.011656200, -0.043727700, -0.118441700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0221811000, 0.0232344000, 0.0257803000, 0.0316807000, 0.0453378000, 0.0770266000, 0.1507891000", \ - "0.0218031000, 0.0229076000, 0.0254664000, 0.0313817000, 0.0451365000, 0.0768656000, 0.1506670000", \ - "0.0214433000, 0.0225447000, 0.0251035000, 0.0310691000, 0.0448914000, 0.0767374000, 0.1505008000", \ - "0.0211696000, 0.0222205000, 0.0248038000, 0.0307262000, 0.0445035000, 0.0764072000, 0.1503777000", \ - "0.0208654000, 0.0219583000, 0.0244972000, 0.0304267000, 0.0442110000, 0.0760481000, 0.1500090000", \ - "0.0208485000, 0.0219462000, 0.0245316000, 0.0304601000, 0.0442635000, 0.0761353000, 0.1499187000", \ - "0.0220060000, 0.0230394000, 0.0254443000, 0.0311765000, 0.0447674000, 0.0764227000, 0.1503934000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0083360000, 0.0073201000, 0.0048918000, -0.000835900, -0.014442500, -0.046332800, -0.120885200", \ - "0.0080342000, 0.0070628000, 0.0047377000, -0.000900000, -0.014361100, -0.046188500, -0.120694900", \ - "0.0075093000, 0.0065891000, 0.0043487000, -0.001136400, -0.014471800, -0.046149100, -0.120580800", \ - "0.0069307000, 0.0060165000, 0.0037617000, -0.001633900, -0.014823800, -0.046310800, -0.120600600", \ - "0.0067810000, 0.0057997000, 0.0034499000, -0.002227200, -0.015307800, -0.046659100, -0.120752000", \ - "0.0068929000, 0.0058075000, 0.0033325000, -0.002386000, -0.015726000, -0.047240700, -0.121151300", \ - "0.0088005000, 0.0076348000, 0.0049726000, -0.001194600, -0.015057300, -0.046930400, -0.121341500"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0177644000, 0.0188529000, 0.0214082000, 0.0273189000, 0.0410820000, 0.0728369000, 0.1464671000", \ - "0.0171589000, 0.0182966000, 0.0208906000, 0.0269139000, 0.0407352000, 0.0725354000, 0.1463505000", \ - "0.0166093000, 0.0177959000, 0.0203801000, 0.0263935000, 0.0403575000, 0.0723413000, 0.1460058000", \ - "0.0161926000, 0.0172986000, 0.0199225000, 0.0259593000, 0.0398650000, 0.0719708000, 0.1459098000", \ - "0.0162598000, 0.0173631000, 0.0198774000, 0.0258972000, 0.0394883000, 0.0714206000, 0.1456209000", \ - "0.0180025000, 0.0190233000, 0.0214916000, 0.0267854000, 0.0399592000, 0.0715281000, 0.1452063000", \ - "0.0203356000, 0.0214553000, 0.0244483000, 0.0289567000, 0.0423118000, 0.0731709000, 0.1471797000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0093936000, 0.0083855000, 0.0059577000, 0.0002515000, -0.013200100, -0.044813800, -0.119070400", \ - "0.0091166000, 0.0081160000, 0.0057044000, 2.690000e-05, -0.013336200, -0.044875000, -0.119057700", \ - "0.0088377000, 0.0078061000, 0.0054212000, -0.000257800, -0.013561600, -0.044986400, -0.119102000", \ - "0.0084522000, 0.0074257000, 0.0050023000, -0.000656800, -0.014007400, -0.045343800, -0.119325000", \ - "0.0082677000, 0.0072047000, 0.0047361000, -0.000980700, -0.014269800, -0.045659800, -0.119694800", \ - "0.0093941000, 0.0082802000, 0.0056712000, 4.200000e-06, -0.014061800, -0.045908800, -0.119937500", \ - "0.0120901000, 0.0108825000, 0.0081670000, 0.0019588000, -0.012136400, -0.044691100, -0.119939700"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011663880, 0.0027209210, 0.0063472980, 0.0148068200, 0.0345409900, 0.0805763800"); - values("0.0098942000, 0.0111335000, 0.0139415000, 0.0201610000, 0.0339919000, 0.0656948000, 0.1392929000", \ - "0.0093892000, 0.0105930000, 0.0134182000, 0.0197126000, 0.0336789000, 0.0656949000, 0.1393865000", \ - "0.0090127000, 0.0101839000, 0.0129153000, 0.0191611000, 0.0332172000, 0.0652239000, 0.1390611000", \ - "0.0090437000, 0.0101743000, 0.0126844000, 0.0186399000, 0.0327658000, 0.0646285000, 0.1386561000", \ - "0.0093141000, 0.0103697000, 0.0128504000, 0.0186667000, 0.0323195000, 0.0640880000, 0.1379692000", \ - "0.0103621000, 0.0114035000, 0.0139834000, 0.0198135000, 0.0331553000, 0.0644862000, 0.1374540000", \ - "0.0146265000, 0.0155108000, 0.0177277000, 0.0236763000, 0.0358745000, 0.0669817000, 0.1409597000"); - } - } - max_capacitance : 0.0805760000; - max_transition : 1.4910310000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0411329000, 0.0437262000, 0.0496954000, 0.0626763000, 0.0906369000, 0.1517795000, 0.2885301000", \ - "0.0457082000, 0.0483290000, 0.0542058000, 0.0671637000, 0.0950751000, 0.1561639000, 0.2928666000", \ - "0.0556527000, 0.0582124000, 0.0639874000, 0.0767360000, 0.1046073000, 0.1656101000, 0.3023532000", \ - "0.0743788000, 0.0773615000, 0.0835781000, 0.0968249000, 0.1247902000, 0.1856759000, 0.3226448000", \ - "0.1018578000, 0.1058972000, 0.1145024000, 0.1318997000, 0.1654055000, 0.2307538000, 0.3686321000", \ - "0.1310780000, 0.1369953000, 0.1493771000, 0.1752242000, 0.2247003000, 0.3123222000, 0.4698814000", \ - "0.1382187000, 0.1472164000, 0.1664733000, 0.2062610000, 0.2835383000, 0.4178138000, 0.6400265000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1803961000, 0.1894507000, 0.2100321000, 0.2553745000, 0.3610889000, 0.6047641000, 1.1701876000", \ - "0.1846996000, 0.1938767000, 0.2142169000, 0.2602154000, 0.3656147000, 0.6097089000, 1.1754528000", \ - "0.1961329000, 0.2048819000, 0.2249643000, 0.2718585000, 0.3781375000, 0.6226472000, 1.1884026000", \ - "0.2214292000, 0.2302647000, 0.2509775000, 0.2973795000, 0.4035462000, 0.6486722000, 1.2154585000", \ - "0.2758026000, 0.2843611000, 0.3044714000, 0.3502752000, 0.4566240000, 0.7015730000, 1.2686939000", \ - "0.3703781000, 0.3806677000, 0.4038235000, 0.4554302000, 0.5669358000, 0.8111233000, 1.3783547000", \ - "0.5269526000, 0.5403540000, 0.5710487000, 0.6351442000, 0.7707998000, 1.0477375000, 1.6236164000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0321801000, 0.0354978000, 0.0423517000, 0.0579162000, 0.0927194000, 0.1715429000, 0.3535191000", \ - "0.0319298000, 0.0348832000, 0.0420222000, 0.0576914000, 0.0924999000, 0.1711705000, 0.3541340000", \ - "0.0319867000, 0.0349032000, 0.0416847000, 0.0571635000, 0.0922357000, 0.1710789000, 0.3536955000", \ - "0.0385617000, 0.0411842000, 0.0472949000, 0.0605737000, 0.0932570000, 0.1708606000, 0.3538168000", \ - "0.0569950000, 0.0598270000, 0.0660756000, 0.0799566000, 0.1103354000, 0.1791249000, 0.3542864000", \ - "0.0936712000, 0.0974783000, 0.1058263000, 0.1236053000, 0.1590111000, 0.2293524000, 0.3838703000", \ - "0.1606460000, 0.1663998000, 0.1792109000, 0.2044213000, 0.2528775000, 0.3437028000, 0.5098638000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1274050000, 0.1386658000, 0.1650927000, 0.2261452000, 0.3675260000, 0.6964845000, 1.4625288000", \ - "0.1273991000, 0.1387903000, 0.1646628000, 0.2263932000, 0.3676066000, 0.6967602000, 1.4621948000", \ - "0.1274434000, 0.1388496000, 0.1647596000, 0.2257345000, 0.3676778000, 0.6978205000, 1.4612167000", \ - "0.1272788000, 0.1386909000, 0.1651852000, 0.2263494000, 0.3676956000, 0.6969127000, 1.4628475000", \ - "0.1311578000, 0.1421218000, 0.1675168000, 0.2267743000, 0.3681627000, 0.6978055000, 1.4628265000", \ - "0.1574881000, 0.1687054000, 0.1936055000, 0.2517033000, 0.3824830000, 0.7015031000, 1.4633056000", \ - "0.2206532000, 0.2332699000, 0.2606698000, 0.3209719000, 0.4574797000, 0.7568428000, 1.4795848000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0379139000, 0.0400358000, 0.0447815000, 0.0553309000, 0.0791622000, 0.1332296000, 0.2581963000", \ - "0.0425972000, 0.0446828000, 0.0494931000, 0.0600369000, 0.0838130000, 0.1380238000, 0.2630377000", \ - "0.0520928000, 0.0542098000, 0.0589644000, 0.0696758000, 0.0934931000, 0.1477494000, 0.2726602000", \ - "0.0678950000, 0.0705033000, 0.0761340000, 0.0882988000, 0.1130874000, 0.1675443000, 0.2928827000", \ - "0.0876126000, 0.0912960000, 0.0996562000, 0.1166927000, 0.1490485000, 0.2111298000, 0.3376766000", \ - "0.1012540000, 0.1069637000, 0.1202564000, 0.1464719000, 0.1961933000, 0.2827608000, 0.4346567000", \ - "0.0807691000, 0.0894252000, 0.1105927000, 0.1522225000, 0.2315623000, 0.3676637000, 0.5870427000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1618411000, 0.1706577000, 0.1899506000, 0.2365208000, 0.3419710000, 0.5854398000, 1.1511496000", \ - "0.1643018000, 0.1730084000, 0.1929518000, 0.2392932000, 0.3452062000, 0.5892156000, 1.1557867000", \ - "0.1735295000, 0.1827963000, 0.2027601000, 0.2494616000, 0.3553654000, 0.6000182000, 1.1661964000", \ - "0.1976153000, 0.2060501000, 0.2267598000, 0.2730343000, 0.3795909000, 0.6243694000, 1.1911455000", \ - "0.2512908000, 0.2599607000, 0.2798875000, 0.3263498000, 0.4319898000, 0.6771620000, 1.2442199000", \ - "0.3472404000, 0.3582388000, 0.3856739000, 0.4412930000, 0.5571575000, 0.8020386000, 1.3702421000", \ - "0.5209652000, 0.5371849000, 0.5717665000, 0.6459114000, 0.7919909000, 1.0832770000, 1.6610486000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0231734000, 0.0256750000, 0.0315078000, 0.0449177000, 0.0760887000, 0.1488284000, 0.3195120000", \ - "0.0231137000, 0.0256556000, 0.0314470000, 0.0448816000, 0.0760842000, 0.1489996000, 0.3179338000", \ - "0.0236273000, 0.0259889000, 0.0316314000, 0.0448908000, 0.0760075000, 0.1485954000, 0.3186214000", \ - "0.0301066000, 0.0323309000, 0.0376254000, 0.0496935000, 0.0783575000, 0.1489612000, 0.3188517000", \ - "0.0472132000, 0.0500175000, 0.0560448000, 0.0693525000, 0.0974686000, 0.1606475000, 0.3209449000", \ - "0.0811806000, 0.0850440000, 0.0934136000, 0.1111313000, 0.1458389000, 0.2122939000, 0.3557922000", \ - "0.1462181000, 0.1516878000, 0.1644045000, 0.1909305000, 0.2381737000, 0.3254583000, 0.4837046000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1274785000, 0.1383375000, 0.1648417000, 0.2258717000, 0.3676272000, 0.6969960000, 1.4670821000", \ - "0.1272102000, 0.1383623000, 0.1650033000, 0.2257271000, 0.3676243000, 0.6982656000, 1.4634051000", \ - "0.1274083000, 0.1388073000, 0.1647435000, 0.2263694000, 0.3675434000, 0.6966242000, 1.4609653000", \ - "0.1273788000, 0.1387257000, 0.1651630000, 0.2259320000, 0.3678836000, 0.6980752000, 1.4666316000", \ - "0.1370561000, 0.1473857000, 0.1723835000, 0.2296742000, 0.3679159000, 0.6994457000, 1.4629737000", \ - "0.1749328000, 0.1858652000, 0.2110832000, 0.2666746000, 0.3914525000, 0.7020035000, 1.4669576000", \ - "0.2583144000, 0.2712852000, 0.2991241000, 0.3632937000, 0.4912202000, 0.7778569000, 1.4814199000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0319705000, 0.0339943000, 0.0384443000, 0.0486274000, 0.0719711000, 0.1255336000, 0.2500292000", \ - "0.0363331000, 0.0383979000, 0.0429935000, 0.0533423000, 0.0768325000, 0.1307076000, 0.2562254000", \ - "0.0452537000, 0.0474816000, 0.0523970000, 0.0629999000, 0.0866722000, 0.1406765000, 0.2657565000", \ - "0.0575673000, 0.0608615000, 0.0673761000, 0.0808710000, 0.1067384000, 0.1613483000, 0.2871862000", \ - "0.0693333000, 0.0741095000, 0.0844976000, 0.1046647000, 0.1412612000, 0.2065303000, 0.3341445000", \ - "0.0676212000, 0.0753916000, 0.0925058000, 0.1246906000, 0.1820674000, 0.2795749000, 0.4370485000", \ - "0.0201248000, 0.0332959000, 0.0609084000, 0.1132675000, 0.2060847000, 0.3556291000, 0.5894853000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1279058000, 0.1368129000, 0.1566632000, 0.2029732000, 0.3085566000, 0.5524093000, 1.1180252000", \ - "0.1284409000, 0.1374213000, 0.1575223000, 0.2046336000, 0.3109075000, 0.5552626000, 1.1215006000", \ - "0.1356841000, 0.1444685000, 0.1654740000, 0.2122317000, 0.3195454000, 0.5645285000, 1.1328668000", \ - "0.1595082000, 0.1682502000, 0.1886743000, 0.2353162000, 0.3422691000, 0.5880255000, 1.1563425000", \ - "0.2238416000, 0.2327281000, 0.2524347000, 0.2969070000, 0.4035033000, 0.6482725000, 1.2162821000", \ - "0.3433399000, 0.3558427000, 0.3835267000, 0.4391684000, 0.5527847000, 0.7922465000, 1.3583152000", \ - "0.5366930000, 0.5531562000, 0.5942135000, 0.6741440000, 0.8397120000, 1.1340631000, 1.6948498000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0155254000, 0.0180492000, 0.0238547000, 0.0373522000, 0.0684966000, 0.1420417000, 0.3108546000", \ - "0.0156476000, 0.0180872000, 0.0238191000, 0.0372702000, 0.0687256000, 0.1419260000, 0.3127147000", \ - "0.0170019000, 0.0191458000, 0.0245241000, 0.0375125000, 0.0685151000, 0.1419022000, 0.3127407000", \ - "0.0250075000, 0.0274110000, 0.0326331000, 0.0445808000, 0.0718936000, 0.1418939000, 0.3109985000", \ - "0.0431104000, 0.0461029000, 0.0523021000, 0.0657604000, 0.0938712000, 0.1556770000, 0.3135630000", \ - "0.0779697000, 0.0820950000, 0.0910113000, 0.1096854000, 0.1450076000, 0.2154955000, 0.3549482000", \ - "0.1464719000, 0.1522751000, 0.1650136000, 0.1915271000, 0.2416618000, 0.3295336000, 0.4878963000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.1268421000, 0.1381311000, 0.1649296000, 0.2257109000, 0.3677256000, 0.6964880000, 1.4615852000", \ - "0.1270128000, 0.1381602000, 0.1645995000, 0.2257772000, 0.3675686000, 0.6982689000, 1.4658196000", \ - "0.1267441000, 0.1380875000, 0.1643978000, 0.2261412000, 0.3684157000, 0.6965031000, 1.4639938000", \ - "0.1244923000, 0.1359517000, 0.1633601000, 0.2256239000, 0.3674506000, 0.6967688000, 1.4675671000", \ - "0.1405503000, 0.1505252000, 0.1731089000, 0.2291403000, 0.3666971000, 0.6979448000, 1.4654350000", \ - "0.1911988000, 0.2041817000, 0.2307051000, 0.2855920000, 0.4025793000, 0.7028870000, 1.4666344000", \ - "0.2731295000, 0.2913980000, 0.3291024000, 0.4042426000, 0.5496569000, 0.8158729000, 1.4910306000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0310633000, 0.0337844000, 0.0397759000, 0.0527793000, 0.0807933000, 0.1418290000, 0.2788214000", \ - "0.0350491000, 0.0377303000, 0.0436838000, 0.0567821000, 0.0849578000, 0.1460361000, 0.2830210000", \ - "0.0464613000, 0.0488132000, 0.0543654000, 0.0669396000, 0.0947551000, 0.1560196000, 0.2931483000", \ - "0.0679200000, 0.0712538000, 0.0781532000, 0.0921330000, 0.1185639000, 0.1800157000, 0.3171466000", \ - "0.0947350000, 0.0993310000, 0.1094847000, 0.1299697000, 0.1682691000, 0.2358478000, 0.3707684000", \ - "0.1200162000, 0.1268730000, 0.1417380000, 0.1722057000, 0.2289482000, 0.3313834000, 0.5006165000", \ - "0.1249717000, 0.1349319000, 0.1567600000, 0.2021229000, 0.2880072000, 0.4425126000, 0.6986624000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0278281000, 0.0307392000, 0.0373593000, 0.0519001000, 0.0843406000, 0.1610592000, 0.3333418000", \ - "0.0326834000, 0.0355188000, 0.0420420000, 0.0567879000, 0.0895129000, 0.1647666000, 0.3377518000", \ - "0.0459536000, 0.0486887000, 0.0550325000, 0.0694495000, 0.1020239000, 0.1766593000, 0.3504290000", \ - "0.0693786000, 0.0739631000, 0.0832426000, 0.1006153000, 0.1332334000, 0.2079370000, 0.3820745000", \ - "0.1062644000, 0.1135392000, 0.1284883000, 0.1563129000, 0.2034601000, 0.2812646000, 0.4537811000", \ - "0.1672215000, 0.1781949000, 0.2011708000, 0.2458099000, 0.3200956000, 0.4401302000, 0.6251846000", \ - "0.2768350000, 0.2927073000, 0.3265275000, 0.3914251000, 0.5076813000, 0.6978367000, 0.9846884000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0309409000, 0.0341655000, 0.0411662000, 0.0568629000, 0.0917456000, 0.1708338000, 0.3538334000", \ - "0.0305037000, 0.0338380000, 0.0409867000, 0.0568473000, 0.0919449000, 0.1707708000, 0.3536036000", \ - "0.0315803000, 0.0343312000, 0.0408446000, 0.0559821000, 0.0913974000, 0.1708428000, 0.3537963000", \ - "0.0432216000, 0.0458994000, 0.0522768000, 0.0643791000, 0.0944531000, 0.1700516000, 0.3535377000", \ - "0.0646313000, 0.0687315000, 0.0769376000, 0.0931635000, 0.1243270000, 0.1870310000, 0.3547776000", \ - "0.1038758000, 0.1096482000, 0.1217262000, 0.1460898000, 0.1888259000, 0.2638703000, 0.4069289000", \ - "0.1718800000, 0.1807480000, 0.1995137000, 0.2356297000, 0.3035480000, 0.4110799000, 0.5951279000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011663900, 0.0027209200, 0.0063473000, 0.0148068000, 0.0345410000, 0.0805764000"); - values("0.0309160000, 0.0349417000, 0.0443531000, 0.0656269000, 0.1128569000, 0.2186960000, 0.4625549000", \ - "0.0309070000, 0.0349589000, 0.0443463000, 0.0655678000, 0.1128458000, 0.2185093000, 0.4617620000", \ - "0.0343062000, 0.0374609000, 0.0455415000, 0.0656171000, 0.1128700000, 0.2184090000, 0.4621566000", \ - "0.0543556000, 0.0555534000, 0.0604392000, 0.0750090000, 0.1151117000, 0.2185338000, 0.4623522000", \ - "0.0917660000, 0.0944078000, 0.1005607000, 0.1142874000, 0.1430944000, 0.2279588000, 0.4620241000", \ - "0.1520922000, 0.1562460000, 0.1658767000, 0.1866083000, 0.2267932000, 0.2990037000, 0.4868367000", \ - "0.2494613000, 0.2555993000, 0.2703956000, 0.3034950000, 0.3689197000, 0.4791305000, 0.6581972000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o31ai_4") { - leakage_power () { - value : 0.0051575000; - when : "!A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0004785000; - when : "!A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0082504000; - when : "!A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0020161000; - when : "!A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0068101000; - when : "!A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0020147000; - when : "!A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0044318000; - when : "!A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0020134000; - when : "!A1&A2&A3&!B1"; - } - leakage_power () { - value : 0.0065957000; - when : "A1&!A2&!A3&B1"; - } - leakage_power () { - value : 0.0020161000; - when : "A1&!A2&!A3&!B1"; - } - leakage_power () { - value : 0.0044218000; - when : "A1&!A2&A3&B1"; - } - leakage_power () { - value : 0.0020160000; - when : "A1&!A2&A3&!B1"; - } - leakage_power () { - value : 0.0044344000; - when : "A1&A2&!A3&B1"; - } - leakage_power () { - value : 0.0020272000; - when : "A1&A2&!A3&!B1"; - } - leakage_power () { - value : 0.0042579000; - when : "A1&A2&A3&B1"; - } - leakage_power () { - value : 0.0020741000; - when : "A1&A2&A3&!B1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__o31ai"; - cell_leakage_power : 0.0036884860; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0086170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0081550000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157321000, 0.0157359000, 0.0157447000, 0.0157359000, 0.0157156000, 0.0156689000, 0.0155611000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015736900, -0.015732600, -0.015722800, -0.015723400, -0.015724900, -0.015728200, -0.015736000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090780000; - } - pin ("A2") { - capacitance : 0.0084620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157351000, 0.0157276000, 0.0157103000, 0.0157053000, 0.0156936000, 0.0156667000, 0.0156047000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015722300, -0.015711600, -0.015687100, -0.015688100, -0.015690500, -0.015695900, -0.015708400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090330000; - } - pin ("A3") { - capacitance : 0.0086850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0160344000, 0.0160302000, 0.0160204000, 0.0160228000, 0.0160283000, 0.0160409000, 0.0160701000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.016022300, -0.016012900, -0.015991000, -0.015992300, -0.015995500, -0.016002600, -0.016019100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0094000000; - } - pin ("B1") { - capacitance : 0.0085620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181833000, 0.0181754000, 0.0181573000, 0.0181516000, 0.0181387000, 0.0181087000, 0.0180397000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.006098700, -0.006107800, -0.006128800, -0.006065000, -0.005917900, -0.005578900, -0.004797400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087890000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0282822000, 0.0270169000, 0.0237910000, 0.0153679000, -0.006095500, -0.061247400, -0.203844600", \ - "0.0277731000, 0.0265115000, 0.0232855000, 0.0149098000, -0.006572600, -0.061771200, -0.204356400", \ - "0.0271914000, 0.0259132000, 0.0226748000, 0.0143022000, -0.007143800, -0.062265100, -0.204935800", \ - "0.0264820000, 0.0253088000, 0.0220157000, 0.0137499000, -0.007711900, -0.062843600, -0.205321500", \ - "0.0258324000, 0.0246144000, 0.0214630000, 0.0131963000, -0.007930600, -0.063026100, -0.205493800", \ - "0.0262399000, 0.0249789000, 0.0217177000, 0.0133449000, -0.008303900, -0.063550600, -0.205914500", \ - "0.0286192000, 0.0273417000, 0.0240102000, 0.0155208000, -0.006490500, -0.062078200, -0.205719700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0512469000, 0.0526024000, 0.0557835000, 0.0642265000, 0.0858589000, 0.1412249000, 0.2826573000", \ - "0.0506362000, 0.0519138000, 0.0553197000, 0.0637133000, 0.0854559000, 0.1408585000, 0.2822226000", \ - "0.0499943000, 0.0512975000, 0.0545413000, 0.0631013000, 0.0849292000, 0.1404474000, 0.2821972000", \ - "0.0493709000, 0.0506638000, 0.0540008000, 0.0624861000, 0.0844012000, 0.1399182000, 0.2818537000", \ - "0.0488929000, 0.0501423000, 0.0534500000, 0.0618875000, 0.0836557000, 0.1393729000, 0.2812604000", \ - "0.0488034000, 0.0501069000, 0.0534028000, 0.0618774000, 0.0835499000, 0.1391173000, 0.2809171000", \ - "0.0480110000, 0.0494695000, 0.0531515000, 0.0619355000, 0.0839333000, 0.1392512000, 0.2806670000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0213988000, 0.0201510000, 0.0169362000, 0.0085822000, -0.012889100, -0.068358700, -0.211407600", \ - "0.0212643000, 0.0200145000, 0.0168039000, 0.0085384000, -0.012953100, -0.068405900, -0.211375000", \ - "0.0208245000, 0.0196092000, 0.0164475000, 0.0082253000, -0.013120500, -0.068460500, -0.211399900", \ - "0.0200062000, 0.0188165000, 0.0156975000, 0.0076050000, -0.013587100, -0.068696600, -0.211529700", \ - "0.0191475000, 0.0179339000, 0.0147982000, 0.0067275000, -0.014239000, -0.069033700, -0.211758700", \ - "0.0193787000, 0.0181315000, 0.0149189000, 0.0066216000, -0.014695500, -0.070001900, -0.212088500", \ - "0.0219379000, 0.0206180000, 0.0171942000, 0.0084790000, -0.013241000, -0.069005500, -0.212142900"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0423353000, 0.0437044000, 0.0469001000, 0.0553663000, 0.0769920000, 0.1322739000, 0.2739586000", \ - "0.0416806000, 0.0428843000, 0.0462452000, 0.0547948000, 0.0765888000, 0.1319011000, 0.2735773000", \ - "0.0408554000, 0.0422298000, 0.0454691000, 0.0540916000, 0.0759314000, 0.1314633000, 0.2733092000", \ - "0.0402280000, 0.0415450000, 0.0447963000, 0.0533419000, 0.0752378000, 0.1309457000, 0.2728136000", \ - "0.0395804000, 0.0409064000, 0.0442028000, 0.0526925000, 0.0744881000, 0.1301376000, 0.2721912000", \ - "0.0395869000, 0.0409038000, 0.0441952000, 0.0527302000, 0.0746313000, 0.1302757000, 0.2720300000", \ - "0.0411504000, 0.0423784000, 0.0455612000, 0.0537902000, 0.0753161000, 0.1302646000, 0.2724577000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0155592000, 0.0143636000, 0.0112677000, 0.0030547000, -0.018333700, -0.073887300, -0.217074100", \ - "0.0149511000, 0.0138140000, 0.0108501000, 0.0028987000, -0.018233500, -0.073604800, -0.216688300", \ - "0.0139486000, 0.0128252000, 0.0100151000, 0.0023574000, -0.018439500, -0.073472400, -0.216384800", \ - "0.0128575000, 0.0117582000, 0.0089009000, 0.0013035000, -0.019171700, -0.073753900, -0.216335400", \ - "0.0126663000, 0.0115052000, 0.0084742000, 0.0004841000, -0.020238800, -0.074457900, -0.216547400", \ - "0.0127601000, 0.0115492000, 0.0083609000, 0.0001655000, -0.020797500, -0.075643300, -0.217361500", \ - "0.0162822000, 0.0148986000, 0.0113960000, 0.0026939000, -0.019457400, -0.075067100, -0.217822700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0331412000, 0.0345367000, 0.0378685000, 0.0463422000, 0.0680406000, 0.1234458000, 0.2650640000", \ - "0.0320736000, 0.0333107000, 0.0368194000, 0.0454029000, 0.0673370000, 0.1229388000, 0.2646314000", \ - "0.0309218000, 0.0322138000, 0.0358221000, 0.0442866000, 0.0664634000, 0.1223980000, 0.2644453000", \ - "0.0301114000, 0.0314000000, 0.0348698000, 0.0433903000, 0.0653968000, 0.1215656000, 0.2639047000", \ - "0.0300907000, 0.0318320000, 0.0352226000, 0.0433620000, 0.0650411000, 0.1207283000, 0.2632516000", \ - "0.0325864000, 0.0333321000, 0.0365326000, 0.0448034000, 0.0664681000, 0.1207928000, 0.2622138000", \ - "0.0372061000, 0.0381289000, 0.0411498000, 0.0490553000, 0.0697501000, 0.1235400000, 0.2627075000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0181570000, 0.0169775000, 0.0139252000, 0.0057601000, -0.015424900, -0.070346200, -0.212919600", \ - "0.0176680000, 0.0164529000, 0.0133437000, 0.0052648000, -0.015740500, -0.070564900, -0.212972600", \ - "0.0170571000, 0.0158282000, 0.0127584000, 0.0045988000, -0.016273000, -0.070822600, -0.213104700", \ - "0.0162495000, 0.0150236000, 0.0120581000, 0.0039505000, -0.017046500, -0.071540200, -0.213424900", \ - "0.0160313000, 0.0147595000, 0.0114933000, 0.0034050000, -0.017750100, -0.072379700, -0.214246800", \ - "0.0177518000, 0.0164669000, 0.0130920000, 0.0045566000, -0.017340100, -0.072844500, -0.214964200", \ - "0.0222867000, 0.0208964000, 0.0173828000, 0.0085326000, -0.013799900, -0.070555200, -0.214362200"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012858830, 0.0033069890, 0.0085048000, 0.0218723500, 0.0562505700, 0.1446633000"); - values("0.0186349000, 0.0201889000, 0.0240360000, 0.0333180000, 0.0556571000, 0.1110961000, 0.2524752000", \ - "0.0177449000, 0.0192344000, 0.0229989000, 0.0323896000, 0.0550634000, 0.1107921000, 0.2526772000", \ - "0.0170237000, 0.0184235000, 0.0220398000, 0.0312966000, 0.0540986000, 0.1103498000, 0.2523656000", \ - "0.0168413000, 0.0181058000, 0.0215050000, 0.0303408000, 0.0526383000, 0.1089046000, 0.2512052000", \ - "0.0174467000, 0.0187030000, 0.0218994000, 0.0302131000, 0.0520375000, 0.1077097000, 0.2500950000", \ - "0.0195224000, 0.0207453000, 0.0240702000, 0.0324716000, 0.0534982000, 0.1085201000, 0.2498395000", \ - "0.0270143000, 0.0279838000, 0.0307426000, 0.0395007000, 0.0579461000, 0.1122324000, 0.2544924000"); - } - } - max_capacitance : 0.1446630000; - max_transition : 1.5045030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0438757000, 0.0458291000, 0.0506471000, 0.0622204000, 0.0894597000, 0.1538221000, 0.3115347000", \ - "0.0482041000, 0.0501419000, 0.0549484000, 0.0665133000, 0.0936320000, 0.1580882000, 0.3158976000", \ - "0.0570351000, 0.0588704000, 0.0635797000, 0.0749650000, 0.1020452000, 0.1663587000, 0.3242076000", \ - "0.0728026000, 0.0749737000, 0.0802183000, 0.0918023000, 0.1191032000, 0.1833532000, 0.3410767000", \ - "0.0973129000, 0.0999419000, 0.1063893000, 0.1207731000, 0.1524294000, 0.2207896000, 0.3795429000", \ - "0.1216918000, 0.1255662000, 0.1349291000, 0.1549386000, 0.2003046000, 0.2881613000, 0.4651203000", \ - "0.1177360000, 0.1235228000, 0.1379259000, 0.1711047000, 0.2390693000, 0.3722130000, 0.6095247000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1904498000, 0.1961273000, 0.2108201000, 0.2478810000, 0.3412551000, 0.5795922000, 1.1891429000", \ - "0.1930770000, 0.1993096000, 0.2147090000, 0.2515401000, 0.3458666000, 0.5845246000, 1.1938857000", \ - "0.2052990000, 0.2111883000, 0.2261864000, 0.2631363000, 0.3578243000, 0.5970274000, 1.2074328000", \ - "0.2308355000, 0.2365091000, 0.2522470000, 0.2893402000, 0.3846324000, 0.6241305000, 1.2345095000", \ - "0.2863693000, 0.2924525000, 0.3070699000, 0.3438883000, 0.4389346000, 0.6784073000, 1.2907272000", \ - "0.3870538000, 0.3938116000, 0.4104503000, 0.4527242000, 0.5533844000, 0.7926401000, 1.4037317000", \ - "0.5562693000, 0.5651446000, 0.5869722000, 0.6404638000, 0.7633903000, 1.0360683000, 1.6586574000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0384394000, 0.0405188000, 0.0459369000, 0.0592970000, 0.0925142000, 0.1754554000, 0.3884745000", \ - "0.0380142000, 0.0400691000, 0.0454850000, 0.0590269000, 0.0920340000, 0.1753573000, 0.3880791000", \ - "0.0378032000, 0.0398021000, 0.0451442000, 0.0584777000, 0.0917583000, 0.1750510000, 0.3887102000", \ - "0.0427737000, 0.0448222000, 0.0495838000, 0.0614471000, 0.0929424000, 0.1751330000, 0.3883694000", \ - "0.0583161000, 0.0603818000, 0.0650194000, 0.0769430000, 0.1073818000, 0.1820650000, 0.3893769000", \ - "0.0929565000, 0.0954766000, 0.1013450000, 0.1155890000, 0.1490311000, 0.2243917000, 0.4120537000", \ - "0.1582983000, 0.1619126000, 0.1706251000, 0.1921271000, 0.2344421000, 0.3275687000, 0.5196056000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1301083000, 0.1376927000, 0.1564340000, 0.2063420000, 0.3318645000, 0.6535384000, 1.4809229000", \ - "0.1299756000, 0.1375804000, 0.1569558000, 0.2059413000, 0.3316988000, 0.6530708000, 1.4756885000", \ - "0.1300526000, 0.1377086000, 0.1563935000, 0.2062383000, 0.3317024000, 0.6533514000, 1.4772994000", \ - "0.1299372000, 0.1373190000, 0.1569497000, 0.2059561000, 0.3326305000, 0.6533995000, 1.4774286000", \ - "0.1335516000, 0.1406891000, 0.1589319000, 0.2069271000, 0.3322477000, 0.6542327000, 1.4789813000", \ - "0.1590123000, 0.1662480000, 0.1850158000, 0.2320337000, 0.3479674000, 0.6574289000, 1.4779346000", \ - "0.2222442000, 0.2298515000, 0.2500655000, 0.2991915000, 0.4225146000, 0.7154002000, 1.4940819000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0426176000, 0.0442396000, 0.0482691000, 0.0579610000, 0.0817825000, 0.1412441000, 0.2920812000", \ - "0.0472180000, 0.0487726000, 0.0527429000, 0.0625908000, 0.0865689000, 0.1458859000, 0.2966819000", \ - "0.0560282000, 0.0576565000, 0.0616282000, 0.0714661000, 0.0954803000, 0.1549226000, 0.3059162000", \ - "0.0705534000, 0.0724675000, 0.0768796000, 0.0878518000, 0.1129205000, 0.1725455000, 0.3236079000", \ - "0.0892144000, 0.0920181000, 0.0982621000, 0.1129324000, 0.1442062000, 0.2111192000, 0.3636530000", \ - "0.1005220000, 0.1042153000, 0.1145304000, 0.1365597000, 0.1839615000, 0.2750778000, 0.4515603000", \ - "0.0735279000, 0.0799419000, 0.0943590000, 0.1301406000, 0.2057382000, 0.3472832000, 0.5934455000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1705992000, 0.1764698000, 0.1912558000, 0.2282343000, 0.3215916000, 0.5600537000, 1.1693407000", \ - "0.1729046000, 0.1788258000, 0.1935370000, 0.2309953000, 0.3253024000, 0.5640466000, 1.1740647000", \ - "0.1821262000, 0.1878754000, 0.2027437000, 0.2407633000, 0.3356046000, 0.5749259000, 1.1853682000", \ - "0.2067716000, 0.2124754000, 0.2265768000, 0.2651115000, 0.3601436000, 0.6000445000, 1.2107891000", \ - "0.2626737000, 0.2686860000, 0.2835047000, 0.3207456000, 0.4154504000, 0.6551945000, 1.2680283000", \ - "0.3672421000, 0.3743698000, 0.3930713000, 0.4403403000, 0.5459313000, 0.7862944000, 1.3976417000", \ - "0.5537194000, 0.5643825000, 0.5907677000, 0.6522679000, 0.7891978000, 1.0759587000, 1.7024498000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0281182000, 0.0298951000, 0.0345583000, 0.0465930000, 0.0777544000, 0.1581126000, 0.3658480000", \ - "0.0280477000, 0.0298668000, 0.0345471000, 0.0466174000, 0.0778557000, 0.1583420000, 0.3655243000", \ - "0.0283306000, 0.0300662000, 0.0346238000, 0.0465398000, 0.0778155000, 0.1583056000, 0.3657699000", \ - "0.0336971000, 0.0354190000, 0.0397395000, 0.0509228000, 0.0799192000, 0.1584557000, 0.3657196000", \ - "0.0494704000, 0.0514180000, 0.0560833000, 0.0678853000, 0.0968277000, 0.1683619000, 0.3677082000", \ - "0.0834604000, 0.0861353000, 0.0924218000, 0.1077888000, 0.1414127000, 0.2151782000, 0.3952738000", \ - "0.1483343000, 0.1521974000, 0.1617890000, 0.1839335000, 0.2306297000, 0.3227231000, 0.5122162000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1299275000, 0.1376474000, 0.1563934000, 0.2063344000, 0.3319150000, 0.6543948000, 1.4775222000", \ - "0.1300984000, 0.1374918000, 0.1564444000, 0.2063303000, 0.3327095000, 0.6541415000, 1.4785824000", \ - "0.1301649000, 0.1377637000, 0.1565600000, 0.2059789000, 0.3318707000, 0.6529479000, 1.4783451000", \ - "0.1303139000, 0.1378887000, 0.1568237000, 0.2059372000, 0.3316547000, 0.6548191000, 1.4763556000", \ - "0.1384253000, 0.1454487000, 0.1636425000, 0.2101708000, 0.3322370000, 0.6532180000, 1.4789446000", \ - "0.1763056000, 0.1834225000, 0.2019134000, 0.2480242000, 0.3569859000, 0.6595804000, 1.4795415000", \ - "0.2609257000, 0.2694156000, 0.2910257000, 0.3426988000, 0.4601925000, 0.7379320000, 1.4953401000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0315163000, 0.0328312000, 0.0361721000, 0.0443438000, 0.0650612000, 0.1173228000, 0.2507623000", \ - "0.0356751000, 0.0370719000, 0.0405397000, 0.0489552000, 0.0698060000, 0.1223650000, 0.2560183000", \ - "0.0439746000, 0.0454978000, 0.0492247000, 0.0579997000, 0.0789368000, 0.1318014000, 0.2660079000", \ - "0.0549548000, 0.0570619000, 0.0619715000, 0.0734260000, 0.0974039000, 0.1510000000, 0.2852633000", \ - "0.0641293000, 0.0674303000, 0.0752895000, 0.0923389000, 0.1259739000, 0.1915311000, 0.3290319000", \ - "0.0576214000, 0.0632180000, 0.0761874000, 0.1028496000, 0.1565296000, 0.2526076000, 0.4236610000", \ - "-0.000154600, 0.0085682000, 0.0291468000, 0.0746016000, 0.1605103000, 0.3117029000, 0.5606861000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1294042000, 0.1343993000, 0.1501404000, 0.1876924000, 0.2817599000, 0.5202351000, 1.1296065000", \ - "0.1293644000, 0.1351939000, 0.1498687000, 0.1888626000, 0.2835102000, 0.5228129000, 1.1330894000", \ - "0.1361454000, 0.1418831000, 0.1577504000, 0.1954744000, 0.2912862000, 0.5316366000, 1.1423668000", \ - "0.1604342000, 0.1660638000, 0.1811951000, 0.2183305000, 0.3142483000, 0.5551116000, 1.1677371000", \ - "0.2244655000, 0.2310543000, 0.2456935000, 0.2801489000, 0.3736514000, 0.6135161000, 1.2255450000", \ - "0.3476025000, 0.3551057000, 0.3749027000, 0.4227531000, 0.5257843000, 0.7570882000, 1.3658281000", \ - "0.5472922000, 0.5593191000, 0.5857708000, 0.6564452000, 0.8050058000, 1.1003604000, 1.7052578000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0153293000, 0.0169582000, 0.0212223000, 0.0320535000, 0.0601133000, 0.1317598000, 0.3153489000", \ - "0.0154293000, 0.0170660000, 0.0212733000, 0.0320891000, 0.0599429000, 0.1317533000, 0.3165041000", \ - "0.0169223000, 0.0183318000, 0.0222085000, 0.0324615000, 0.0601452000, 0.1318718000, 0.3160155000", \ - "0.0243782000, 0.0258989000, 0.0297828000, 0.0397057000, 0.0639603000, 0.1323109000, 0.3146395000", \ - "0.0419361000, 0.0437159000, 0.0482365000, 0.0594313000, 0.0849103000, 0.1468188000, 0.3181784000", \ - "0.0760085000, 0.0782015000, 0.0848789000, 0.1001701000, 0.1320616000, 0.2003930000, 0.3578539000", \ - "0.1435854000, 0.1470927000, 0.1564811000, 0.1779112000, 0.2241855000, 0.3105253000, 0.4823079000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.1292386000, 0.1368995000, 0.1565918000, 0.2055365000, 0.3315897000, 0.6532068000, 1.4776472000", \ - "0.1295135000, 0.1368029000, 0.1560959000, 0.2056619000, 0.3316318000, 0.6534387000, 1.4819098000", \ - "0.1286781000, 0.1362990000, 0.1562063000, 0.2055989000, 0.3316541000, 0.6529640000, 1.4766309000", \ - "0.1258839000, 0.1336328000, 0.1540965000, 0.2046940000, 0.3313911000, 0.6533473000, 1.4774167000", \ - "0.1409134000, 0.1470279000, 0.1641434000, 0.2092529000, 0.3304312000, 0.6535021000, 1.4806082000", \ - "0.1881177000, 0.1980557000, 0.2199064000, 0.2665207000, 0.3698322000, 0.6617522000, 1.4776677000", \ - "0.2681928000, 0.2806287000, 0.3086189000, 0.3725261000, 0.5073393000, 0.7769210000, 1.5045026000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0340388000, 0.0360423000, 0.0410015000, 0.0527215000, 0.0800868000, 0.1445648000, 0.3025375000", \ - "0.0379668000, 0.0399074000, 0.0448282000, 0.0565779000, 0.0841111000, 0.1488137000, 0.3067837000", \ - "0.0490582000, 0.0508101000, 0.0553006000, 0.0665719000, 0.0937700000, 0.1586182000, 0.3167711000", \ - "0.0714101000, 0.0736614000, 0.0795507000, 0.0917905000, 0.1179131000, 0.1816282000, 0.3396620000", \ - "0.0999341000, 0.1032268000, 0.1111494000, 0.1286653000, 0.1661430000, 0.2377534000, 0.3950238000", \ - "0.1255140000, 0.1302608000, 0.1417791000, 0.1682891000, 0.2242207000, 0.3322443000, 0.5232424000", \ - "0.1270705000, 0.1339452000, 0.1508598000, 0.1900604000, 0.2729125000, 0.4357341000, 0.7276981000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0262976000, 0.0282993000, 0.0331286000, 0.0447396000, 0.0727875000, 0.1427998000, 0.3219403000", \ - "0.0313333000, 0.0332187000, 0.0379178000, 0.0496122000, 0.0781319000, 0.1482970000, 0.3278684000", \ - "0.0448066000, 0.0465884000, 0.0510731000, 0.0625134000, 0.0905510000, 0.1614472000, 0.3414271000", \ - "0.0678574000, 0.0709593000, 0.0781047000, 0.0930531000, 0.1218301000, 0.1924514000, 0.3709051000", \ - "0.1051177000, 0.1099286000, 0.1212628000, 0.1452055000, 0.1900031000, 0.2664911000, 0.4456054000", \ - "0.1675150000, 0.1748519000, 0.1920945000, 0.2295582000, 0.3019328000, 0.4211941000, 0.6174469000", \ - "0.2823296000, 0.2931393000, 0.3182556000, 0.3732362000, 0.4820840000, 0.6740248000, 0.9797905000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0371356000, 0.0392047000, 0.0445497000, 0.0580853000, 0.0913713000, 0.1747175000, 0.3883639000", \ - "0.0366578000, 0.0388425000, 0.0443645000, 0.0580199000, 0.0914892000, 0.1749819000, 0.3881377000", \ - "0.0365313000, 0.0384969000, 0.0436303000, 0.0569188000, 0.0909870000, 0.1746480000, 0.3880812000", \ - "0.0473056000, 0.0494072000, 0.0545698000, 0.0648286000, 0.0934891000, 0.1740112000, 0.3882219000", \ - "0.0680711000, 0.0708672000, 0.0774679000, 0.0925969000, 0.1238838000, 0.1900531000, 0.3892788000", \ - "0.1071210000, 0.1112365000, 0.1209197000, 0.1426123000, 0.1848333000, 0.2691516000, 0.4354614000", \ - "0.1740954000, 0.1803226000, 0.1952672000, 0.2281845000, 0.2975901000, 0.4124752000, 0.6273446000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012858800, 0.0033069900, 0.0085048000, 0.0218724000, 0.0562506000, 0.1446630000"); - values("0.0272660000, 0.0298318000, 0.0361862000, 0.0529775000, 0.0944644000, 0.1947628000, 0.4456914000", \ - "0.0271749000, 0.0296959000, 0.0363689000, 0.0528948000, 0.0943958000, 0.1947303000, 0.4453921000", \ - "0.0308321000, 0.0327233000, 0.0380473000, 0.0531420000, 0.0944765000, 0.1947605000, 0.4457028000", \ - "0.0508100000, 0.0522333000, 0.0543619000, 0.0643418000, 0.0979914000, 0.1947104000, 0.4458762000", \ - "0.0880555000, 0.0895988000, 0.0937683000, 0.1047170000, 0.1297812000, 0.2058909000, 0.4458970000", \ - "0.1496594000, 0.1521351000, 0.1588760000, 0.1750106000, 0.2112780000, 0.2814993000, 0.4718774000", \ - "0.2490639000, 0.2526470000, 0.2622881000, 0.2871688000, 0.3444391000, 0.4542340000, 0.6418917000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32a_1") { - leakage_power () { - value : 0.0027452000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0015927000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0027603000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0027324000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0016656000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0010652000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0021209000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0014607000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0008603000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019161000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0011056000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0005052000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0015610000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0015378000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0009374000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019932000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0011150000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0005146000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0015704000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0011186000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0005181000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0015739000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0010881000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0024476000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0004876000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0015434000; - when : "A1&A2&A3&B1&!B2"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__o32a"; - cell_leakage_power : 0.0016632030; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0042088000, 0.0042045000, 0.0041945000, 0.0041938000, 0.0041920000, 0.0041879000, 0.0041786000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004196100, -0.004193900, -0.004188700, -0.004188300, -0.004187300, -0.004185000, -0.004179600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024400000; - } - pin ("A2") { - capacitance : 0.0024080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040853000, 0.0040840000, 0.0040811000, 0.0040797000, 0.0040764000, 0.0040687000, 0.0040511000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004083300, -0.004081500, -0.004077200, -0.004077100, -0.004076700, -0.004075800, -0.004073600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025700000; - } - pin ("A3") { - capacitance : 0.0023210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038273000, 0.0038249000, 0.0038193000, 0.0038199000, 0.0038213000, 0.0038247000, 0.0038323000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003816900, -0.003815100, -0.003810900, -0.003812000, -0.003814600, -0.003820600, -0.003834400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024930000; - } - pin ("B1") { - capacitance : 0.0023180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047502000, 0.0047415000, 0.0047213000, 0.0047207000, 0.0047195000, 0.0047165000, 0.0047098000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000741900, -0.000751700, -0.000774100, -0.000750300, -0.000695400, -0.000568800, -0.000277000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023880000; - } - pin ("B2") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046427000, 0.0046432000, 0.0046442000, 0.0046443000, 0.0046447000, 0.0046454000, 0.0046471000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000536000, -0.000545200, -0.000566300, -0.000544000, -0.000492400, -0.000373500, -9.9435673e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025050000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A1&B2) | (A2&B1) | (A3&B1) | (A2&B2) | (A3&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0190593000, 0.0181854000, 0.0158954000, 0.0087087000, -0.012514100, -0.069969400, -0.219247400", \ - "0.0189262000, 0.0180354000, 0.0156583000, 0.0085181000, -0.012705900, -0.070151900, -0.219387100", \ - "0.0187020000, 0.0178485000, 0.0154779000, 0.0082952000, -0.012899600, -0.070332700, -0.219586700", \ - "0.0185662000, 0.0177103000, 0.0152762000, 0.0080535000, -0.013132400, -0.070554700, -0.219778700", \ - "0.0183522000, 0.0174426000, 0.0150747000, 0.0079122000, -0.013279200, -0.070688000, -0.219921100", \ - "0.0182427000, 0.0173479000, 0.0149520000, 0.0077649000, -0.013326200, -0.070636900, -0.219866600", \ - "0.0221686000, 0.0208399000, 0.0174614000, 0.0088136000, -0.013533400, -0.070551900, -0.219701100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0166589000, 0.0180594000, 0.0215345000, 0.0300620000, 0.0518381000, 0.1083929000, 0.2558871000", \ - "0.0165205000, 0.0179184000, 0.0213827000, 0.0299640000, 0.0517134000, 0.1082794000, 0.2568328000", \ - "0.0164054000, 0.0177825000, 0.0212470000, 0.0298343000, 0.0516259000, 0.1082668000, 0.2567705000", \ - "0.0162739000, 0.0176695000, 0.0211314000, 0.0297210000, 0.0516040000, 0.1082671000, 0.2555355000", \ - "0.0161639000, 0.0175422000, 0.0210143000, 0.0296686000, 0.0516357000, 0.1084129000, 0.2555676000", \ - "0.0165628000, 0.0178534000, 0.0211864000, 0.0294707000, 0.0516684000, 0.1082414000, 0.2556884000", \ - "0.0170764000, 0.0183564000, 0.0216835000, 0.0302178000, 0.0522556000, 0.1094413000, 0.2554324000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0171986000, 0.0162958000, 0.0139020000, 0.0066794000, -0.014470600, -0.071780200, -0.220934500", \ - "0.0169242000, 0.0160458000, 0.0136842000, 0.0065714000, -0.014571200, -0.071904500, -0.221054100", \ - "0.0167229000, 0.0158561000, 0.0135352000, 0.0063309000, -0.014807500, -0.072124400, -0.221277200", \ - "0.0165462000, 0.0156418000, 0.0133201000, 0.0061187000, -0.015016900, -0.072325400, -0.221470300", \ - "0.0163598000, 0.0154939000, 0.0131153000, 0.0058954000, -0.015204900, -0.072470400, -0.221587900", \ - "0.0162823000, 0.0153889000, 0.0130048000, 0.0058193000, -0.015253600, -0.072498100, -0.221594100", \ - "0.0201342000, 0.0188188000, 0.0154532000, 0.0071389000, -0.015544000, -0.072113300, -0.221273700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0155753000, 0.0169901000, 0.0205113000, 0.0293363000, 0.0518541000, 0.1089525000, 0.2565731000", \ - "0.0155528000, 0.0169582000, 0.0204823000, 0.0293106000, 0.0516582000, 0.1088063000, 0.2576145000", \ - "0.0154668000, 0.0168761000, 0.0204080000, 0.0292382000, 0.0515631000, 0.1092694000, 0.2576368000", \ - "0.0153008000, 0.0167043000, 0.0202270000, 0.0290399000, 0.0513735000, 0.1091136000, 0.2574652000", \ - "0.0150440000, 0.0164458000, 0.0199484000, 0.0287190000, 0.0510589000, 0.1088448000, 0.2560304000", \ - "0.0151167000, 0.0164728000, 0.0198621000, 0.0283578000, 0.0507805000, 0.1077345000, 0.2569510000", \ - "0.0155534000, 0.0168539000, 0.0202486000, 0.0288384000, 0.0511029000, 0.1085092000, 0.2550161000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0149772000, 0.0140767000, 0.0116981000, 0.0044938000, -0.016512000, -0.073683300, -0.222736100", \ - "0.0147754000, 0.0139057000, 0.0115438000, 0.0043458000, -0.016709200, -0.073872300, -0.222904600", \ - "0.0145093000, 0.0136500000, 0.0112594000, 0.0041354000, -0.016963900, -0.074095600, -0.223130500", \ - "0.0143621000, 0.0134941000, 0.0110680000, 0.0039040000, -0.017096500, -0.074217100, -0.223283300", \ - "0.0143434000, 0.0134763000, 0.0110985000, 0.0039919000, -0.017088800, -0.074265300, -0.223354100", \ - "0.0148219000, 0.0139427000, 0.0114895000, 0.0043228000, -0.016727100, -0.073888400, -0.222916800", \ - "0.0193278000, 0.0179721000, 0.0145667000, 0.0062616000, -0.016392900, -0.073139200, -0.222219900"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0136706000, 0.0150512000, 0.0185813000, 0.0273864000, 0.0496523000, 0.1068547000, 0.2546580000", \ - "0.0136641000, 0.0150646000, 0.0185949000, 0.0274071000, 0.0497084000, 0.1067728000, 0.2544794000", \ - "0.0136272000, 0.0150315000, 0.0185483000, 0.0273495000, 0.0498574000, 0.1068526000, 0.2555953000", \ - "0.0134259000, 0.0148203000, 0.0183247000, 0.0271306000, 0.0494230000, 0.1070459000, 0.2554949000", \ - "0.0131838000, 0.0145476000, 0.0180486000, 0.0267448000, 0.0490486000, 0.1063787000, 0.2550951000", \ - "0.0132169000, 0.0145605000, 0.0179222000, 0.0264633000, 0.0488102000, 0.1062646000, 0.2550471000", \ - "0.0136486000, 0.0149259000, 0.0182648000, 0.0269228000, 0.0491737000, 0.1066430000, 0.2541365000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0115600000, 0.0109575000, 0.0088939000, 0.0026823000, -0.017599400, -0.074759600, -0.223948200", \ - "0.0114643000, 0.0108359000, 0.0087313000, 0.0025194000, -0.017763200, -0.074908800, -0.224098900", \ - "0.0112328000, 0.0105862000, 0.0084909000, 0.0022781000, -0.017992300, -0.075145600, -0.224330400", \ - "0.0108995000, 0.0103129000, 0.0082270000, 0.0019665000, -0.018261400, -0.075398500, -0.224572300", \ - "0.0106639000, 0.0100535000, 0.0079427000, 0.0017147000, -0.018503900, -0.075585700, -0.224741300", \ - "0.0132688000, 0.0120191000, 0.0088011000, 0.0009452000, -0.018739200, -0.075696300, -0.224805700", \ - "0.0170092000, 0.0156939000, 0.0123909000, 0.0039087000, -0.018028700, -0.075174800, -0.224228900"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0129898000, 0.0143836000, 0.0178721000, 0.0264933000, 0.0485165000, 0.1059964000, 0.2542706000", \ - "0.0128845000, 0.0142880000, 0.0177623000, 0.0264172000, 0.0484648000, 0.1054856000, 0.2530619000", \ - "0.0127717000, 0.0141760000, 0.0176588000, 0.0263274000, 0.0483967000, 0.1053893000, 0.2528905000", \ - "0.0126626000, 0.0140553000, 0.0175264000, 0.0261974000, 0.0482658000, 0.1051898000, 0.2539680000", \ - "0.0124795000, 0.0138639000, 0.0173306000, 0.0260000000, 0.0481003000, 0.1051085000, 0.2523851000", \ - "0.0132041000, 0.0145032000, 0.0178211000, 0.0261435000, 0.0483478000, 0.1056812000, 0.2536831000", \ - "0.0141058000, 0.0153496000, 0.0187110000, 0.0271647000, 0.0492198000, 0.1065031000, 0.2536451000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0093617000, 0.0087402000, 0.0066696000, 0.0004354000, -0.019831700, -0.076988500, -0.226188700", \ - "0.0091133000, 0.0085497000, 0.0064571000, 0.0002277000, -0.020033800, -0.077190100, -0.226369500", \ - "0.0088762000, 0.0082381000, 0.0061418000, -7.30000e-05, -0.020341400, -0.077493000, -0.226674000", \ - "0.0085542000, 0.0079463000, 0.0058370000, -0.000428200, -0.020657400, -0.077773600, -0.226936100", \ - "0.0085690000, 0.0079528000, 0.0057967000, -0.000532200, -0.020743300, -0.077785900, -0.226912600", \ - "0.0109889000, 0.0096931000, 0.0064256000, -0.000859900, -0.020565100, -0.077450000, -0.226549400", \ - "0.0159944000, 0.0146967000, 0.0113670000, 0.0026979000, -0.019391600, -0.076420100, -0.225409600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012938950, 0.0033483280, 0.0086647680, 0.0224226000, 0.0580249800, 0.1501564000"); - values("0.0114530000, 0.0128489000, 0.0163203000, 0.0249623000, 0.0470251000, 0.1038668000, 0.2526692000", \ - "0.0114379000, 0.0128362000, 0.0162953000, 0.0249818000, 0.0470551000, 0.1039925000, 0.2527800000", \ - "0.0113471000, 0.0127442000, 0.0162307000, 0.0248872000, 0.0469943000, 0.1039189000, 0.2516662000", \ - "0.0111821000, 0.0125744000, 0.0160188000, 0.0247035000, 0.0467836000, 0.1037837000, 0.2512737000", \ - "0.0109400000, 0.0123240000, 0.0158046000, 0.0243580000, 0.0464919000, 0.1039055000, 0.2518712000", \ - "0.0114106000, 0.0127343000, 0.0160447000, 0.0244141000, 0.0465976000, 0.1037853000, 0.2510919000", \ - "0.0122245000, 0.0134595000, 0.0167760000, 0.0253709000, 0.0474125000, 0.1047349000, 0.2507221000"); - } - } - max_capacitance : 0.1501560000; - max_transition : 1.4979900000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.3019107000, 0.3107978000, 0.3284572000, 0.3619581000, 0.4250448000, 0.5541298000, 0.8576613000", \ - "0.3061647000, 0.3151303000, 0.3330069000, 0.3666310000, 0.4296139000, 0.5585840000, 0.8621905000", \ - "0.3173478000, 0.3262638000, 0.3441920000, 0.3777435000, 0.4407161000, 0.5698423000, 0.8732235000", \ - "0.3431056000, 0.3519841000, 0.3698555000, 0.4034115000, 0.4663602000, 0.5955841000, 0.8991948000", \ - "0.3991096000, 0.4080965000, 0.4258452000, 0.4590713000, 0.5221945000, 0.6516597000, 0.9551731000", \ - "0.5163359000, 0.5257096000, 0.5440635000, 0.5781631000, 0.6414060000, 0.7712077000, 1.0748820000", \ - "0.7282580000, 0.7390286000, 0.7596436000, 0.7977587000, 0.8672661000, 1.0025184000, 1.3088048000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.1113291000, 0.1189738000, 0.1361470000, 0.1749737000, 0.2700993000, 0.5152467000, 1.1505680000", \ - "0.1157877000, 0.1234350000, 0.1405993000, 0.1795341000, 0.2746192000, 0.5194682000, 1.1553222000", \ - "0.1256747000, 0.1332595000, 0.1504098000, 0.1893806000, 0.2843837000, 0.5290633000, 1.1653556000", \ - "0.1457845000, 0.1533980000, 0.1704611000, 0.2094509000, 0.3046762000, 0.5498822000, 1.1857734000", \ - "0.1848789000, 0.1927463000, 0.2103067000, 0.2497799000, 0.3455823000, 0.5910416000, 1.2267497000", \ - "0.2400834000, 0.2488186000, 0.2678100000, 0.3084632000, 0.4051172000, 0.6510497000, 1.2866268000", \ - "0.2911089000, 0.3021920000, 0.3244919000, 0.3684290000, 0.4660670000, 0.7129105000, 1.3474316000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0395764000, 0.0447463000, 0.0565417000, 0.0820221000, 0.1391240000, 0.2797941000, 0.6685458000", \ - "0.0395671000, 0.0446568000, 0.0562000000, 0.0819881000, 0.1388398000, 0.2798123000, 0.6624510000", \ - "0.0396210000, 0.0446884000, 0.0558893000, 0.0810258000, 0.1389603000, 0.2798943000, 0.6650290000", \ - "0.0399107000, 0.0451225000, 0.0559983000, 0.0810816000, 0.1390476000, 0.2791771000, 0.6675985000", \ - "0.0395830000, 0.0446515000, 0.0560280000, 0.0822665000, 0.1389613000, 0.2796113000, 0.6647368000", \ - "0.0419448000, 0.0471709000, 0.0579140000, 0.0824708000, 0.1402618000, 0.2805635000, 0.6677747000", \ - "0.0498953000, 0.0555928000, 0.0680812000, 0.0942002000, 0.1511044000, 0.2887856000, 0.6686660000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0286059000, 0.0362567000, 0.0556492000, 0.1059949000, 0.2395043000, 0.5890483000, 1.4943132000", \ - "0.0286315000, 0.0363318000, 0.0555846000, 0.1058789000, 0.2395405000, 0.5892129000, 1.4956779000", \ - "0.0285034000, 0.0363076000, 0.0555596000, 0.1058154000, 0.2393262000, 0.5878343000, 1.4966010000", \ - "0.0284214000, 0.0360826000, 0.0554273000, 0.1056846000, 0.2393838000, 0.5889305000, 1.4958491000", \ - "0.0298907000, 0.0376278000, 0.0564950000, 0.1060179000, 0.2393852000, 0.5889019000, 1.4967647000", \ - "0.0350695000, 0.0425234000, 0.0604699000, 0.1084385000, 0.2396071000, 0.5885607000, 1.4955220000", \ - "0.0454025000, 0.0533084000, 0.0707816000, 0.1147242000, 0.2418896000, 0.5895001000, 1.4924281000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.2875606000, 0.2963575000, 0.3142109000, 0.3477918000, 0.4108334000, 0.5403140000, 0.8437678000", \ - "0.2907581000, 0.2996617000, 0.3175843000, 0.3507397000, 0.4141145000, 0.5433274000, 0.8470055000", \ - "0.3010268000, 0.3098691000, 0.3276335000, 0.3612581000, 0.4243486000, 0.5537524000, 0.8573452000", \ - "0.3266253000, 0.3354399000, 0.3530741000, 0.3867490000, 0.4499109000, 0.5793367000, 0.8830193000", \ - "0.3867872000, 0.3955421000, 0.4133543000, 0.4470857000, 0.5101514000, 0.6396924000, 0.9435296000", \ - "0.5214963000, 0.5309465000, 0.5503119000, 0.5847191000, 0.6487545000, 0.7786790000, 1.0821319000", \ - "0.7675671000, 0.7788699000, 0.8008667000, 0.8397407000, 0.9098406000, 1.0441894000, 1.3511088000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.1065102000, 0.1140301000, 0.1310776000, 0.1704123000, 0.2675611000, 0.5145668000, 1.1509339000", \ - "0.1112988000, 0.1188486000, 0.1358962000, 0.1753229000, 0.2720341000, 0.5192985000, 1.1580445000", \ - "0.1211360000, 0.1286956000, 0.1457788000, 0.1851940000, 0.2818958000, 0.5298375000, 1.1688833000", \ - "0.1408082000, 0.1483344000, 0.1653565000, 0.2047156000, 0.3013425000, 0.5493362000, 1.1883058000", \ - "0.1772504000, 0.1850175000, 0.2025385000, 0.2421361000, 0.3393300000, 0.5876911000, 1.2239983000", \ - "0.2256239000, 0.2345059000, 0.2533713000, 0.2941117000, 0.3912928000, 0.6388501000, 1.2775004000", \ - "0.2624272000, 0.2736528000, 0.2963668000, 0.3405413000, 0.4386374000, 0.6864455000, 1.3230738000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0398684000, 0.0447499000, 0.0559933000, 0.0809521000, 0.1388103000, 0.2796989000, 0.6651448000", \ - "0.0395898000, 0.0447507000, 0.0560096000, 0.0818551000, 0.1390268000, 0.2798956000, 0.6655927000", \ - "0.0393586000, 0.0446037000, 0.0560107000, 0.0810406000, 0.1388926000, 0.2798020000, 0.6649480000", \ - "0.0395562000, 0.0446166000, 0.0562003000, 0.0810674000, 0.1389168000, 0.2798347000, 0.6649858000", \ - "0.0396813000, 0.0451894000, 0.0564126000, 0.0812148000, 0.1387523000, 0.2800134000, 0.6648893000", \ - "0.0428583000, 0.0479163000, 0.0584582000, 0.0828004000, 0.1401994000, 0.2794305000, 0.6651877000", \ - "0.0539998000, 0.0597519000, 0.0709872000, 0.0966880000, 0.1523168000, 0.2907413000, 0.6670759000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0269804000, 0.0344878000, 0.0534725000, 0.1035931000, 0.2377415000, 0.5883244000, 1.4912704000", \ - "0.0270089000, 0.0344874000, 0.0535547000, 0.1037750000, 0.2378854000, 0.5894524000, 1.4969790000", \ - "0.0270867000, 0.0345336000, 0.0535095000, 0.1035483000, 0.2372231000, 0.5890770000, 1.4944808000", \ - "0.0270453000, 0.0344607000, 0.0535080000, 0.1036643000, 0.2374724000, 0.5893926000, 1.4939745000", \ - "0.0288893000, 0.0363047000, 0.0550484000, 0.1046252000, 0.2379996000, 0.5887511000, 1.4964349000", \ - "0.0344080000, 0.0413145000, 0.0592817000, 0.1068188000, 0.2394097000, 0.5858833000, 1.4962465000", \ - "0.0455306000, 0.0535342000, 0.0708535000, 0.1142904000, 0.2409828000, 0.5895667000, 1.4916234000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.2476653000, 0.2564600000, 0.2742842000, 0.3079908000, 0.3707249000, 0.5003647000, 0.8044219000", \ - "0.2500164000, 0.2589244000, 0.2768724000, 0.3104405000, 0.3738137000, 0.5036108000, 0.8076085000", \ - "0.2580538000, 0.2670095000, 0.2849061000, 0.3184402000, 0.3818264000, 0.5114877000, 0.8155097000", \ - "0.2837274000, 0.2927379000, 0.3104446000, 0.3441614000, 0.4071363000, 0.5370972000, 0.8410275000", \ - "0.3464362000, 0.3553792000, 0.3732526000, 0.4069032000, 0.4703243000, 0.5999525000, 0.9040289000", \ - "0.4967352000, 0.5059948000, 0.5244131000, 0.5584159000, 0.6220169000, 0.7520907000, 1.0561093000", \ - "0.7548652000, 0.7669606000, 0.7903135000, 0.8304532000, 0.8979314000, 1.0307497000, 1.3378840000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0945245000, 0.1018699000, 0.1187515000, 0.1577990000, 0.2546015000, 0.5010586000, 1.1366612000", \ - "0.0994359000, 0.1068321000, 0.1237278000, 0.1628457000, 0.2593896000, 0.5059106000, 1.1429194000", \ - "0.1093862000, 0.1167629000, 0.1335926000, 0.1726208000, 0.2694711000, 0.5160699000, 1.1532647000", \ - "0.1290319000, 0.1364169000, 0.1531966000, 0.1922278000, 0.2885877000, 0.5365089000, 1.1720663000", \ - "0.1626390000, 0.1704588000, 0.1877752000, 0.2272618000, 0.3239903000, 0.5704997000, 1.2092456000", \ - "0.2033720000, 0.2122559000, 0.2313489000, 0.2720040000, 0.3691649000, 0.6161356000, 1.2536850000", \ - "0.2251075000, 0.2371239000, 0.2605831000, 0.3058231000, 0.4039210000, 0.6525254000, 1.2878040000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0395508000, 0.0446137000, 0.0560516000, 0.0811931000, 0.1391744000, 0.2795292000, 0.6639020000", \ - "0.0394815000, 0.0446650000, 0.0567435000, 0.0807789000, 0.1387023000, 0.2797569000, 0.6671911000", \ - "0.0396843000, 0.0446728000, 0.0559418000, 0.0811098000, 0.1388823000, 0.2796012000, 0.6675812000", \ - "0.0396035000, 0.0446016000, 0.0560224000, 0.0812950000, 0.1388305000, 0.2793939000, 0.6651352000", \ - "0.0395814000, 0.0446837000, 0.0558514000, 0.0818363000, 0.1382947000, 0.2795298000, 0.6669588000", \ - "0.0428156000, 0.0477842000, 0.0585460000, 0.0824787000, 0.1396535000, 0.2798254000, 0.6666633000", \ - "0.0607157000, 0.0663263000, 0.0775154000, 0.0982242000, 0.1502179000, 0.2872468000, 0.6686277000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0260911000, 0.0336687000, 0.0526591000, 0.1029219000, 0.2376691000, 0.5869134000, 1.4919462000", \ - "0.0262392000, 0.0336737000, 0.0527225000, 0.1030101000, 0.2376450000, 0.5885806000, 1.4942699000", \ - "0.0261848000, 0.0336699000, 0.0525563000, 0.1027656000, 0.2375825000, 0.5872215000, 1.4974316000", \ - "0.0263953000, 0.0338350000, 0.0527361000, 0.1029601000, 0.2368606000, 0.5878938000, 1.4958375000", \ - "0.0288209000, 0.0362492000, 0.0547196000, 0.1036755000, 0.2376281000, 0.5883242000, 1.4972666000", \ - "0.0351556000, 0.0425729000, 0.0599409000, 0.1066402000, 0.2386761000, 0.5868753000, 1.4979900000", \ - "0.0482857000, 0.0563010000, 0.0731357000, 0.1161791000, 0.2409498000, 0.5898982000, 1.4870921000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.1338548000, 0.1408313000, 0.1562161000, 0.1882515000, 0.2544789000, 0.3894068000, 0.6943321000", \ - "0.1387913000, 0.1459070000, 0.1613329000, 0.1933341000, 0.2594051000, 0.3944045000, 0.6993247000", \ - "0.1504660000, 0.1575962000, 0.1728275000, 0.2049522000, 0.2710670000, 0.4059941000, 0.7109487000", \ - "0.1761959000, 0.1832777000, 0.1986153000, 0.2305975000, 0.2968655000, 0.4318417000, 0.7368492000", \ - "0.2316077000, 0.2387788000, 0.2545776000, 0.2869094000, 0.3535572000, 0.4889759000, 0.7939811000", \ - "0.3271559000, 0.3355053000, 0.3532646000, 0.3895192000, 0.4611807000, 0.6011801000, 0.9072982000", \ - "0.4858586000, 0.4961445000, 0.5177480000, 0.5603585000, 0.6406619000, 0.7939434000, 1.1067889000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0993625000, 0.1070048000, 0.1241897000, 0.1632981000, 0.2597579000, 0.5068330000, 1.1445299000", \ - "0.1035224000, 0.1111701000, 0.1283244000, 0.1675588000, 0.2635807000, 0.5099955000, 1.1470300000", \ - "0.1136387000, 0.1213030000, 0.1384759000, 0.1777632000, 0.2738265000, 0.5203627000, 1.1574396000", \ - "0.1387232000, 0.1462803000, 0.1633590000, 0.2025821000, 0.2989620000, 0.5452396000, 1.1819936000", \ - "0.1847418000, 0.1925171000, 0.2099745000, 0.2495065000, 0.3459578000, 0.5923337000, 1.2288005000", \ - "0.2430585000, 0.2515402000, 0.2696801000, 0.3097137000, 0.4068542000, 0.6530501000, 1.2921721000", \ - "0.2992621000, 0.3097084000, 0.3309228000, 0.3724415000, 0.4696781000, 0.7166773000, 1.3524852000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0261035000, 0.0319720000, 0.0451280000, 0.0752878000, 0.1412657000, 0.2846801000, 0.6663662000", \ - "0.0263044000, 0.0319031000, 0.0449575000, 0.0754936000, 0.1416512000, 0.2850365000, 0.6626407000", \ - "0.0262705000, 0.0319136000, 0.0451303000, 0.0755421000, 0.1413271000, 0.2846431000, 0.6651082000", \ - "0.0262439000, 0.0319803000, 0.0450856000, 0.0753748000, 0.1414765000, 0.2847115000, 0.6653118000", \ - "0.0280043000, 0.0336557000, 0.0467139000, 0.0766065000, 0.1423862000, 0.2854053000, 0.6631987000", \ - "0.0339461000, 0.0399410000, 0.0541281000, 0.0853340000, 0.1516954000, 0.2915644000, 0.6644848000", \ - "0.0458456000, 0.0528352000, 0.0687975000, 0.1035071000, 0.1747219000, 0.3123815000, 0.6697831000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0284998000, 0.0362321000, 0.0555063000, 0.1056723000, 0.2393920000, 0.5893075000, 1.4972732000", \ - "0.0284930000, 0.0361868000, 0.0555081000, 0.1056437000, 0.2393460000, 0.5883200000, 1.4945507000", \ - "0.0284369000, 0.0361271000, 0.0554273000, 0.1055728000, 0.2393494000, 0.5888265000, 1.4962374000", \ - "0.0281837000, 0.0359393000, 0.0552033000, 0.1056098000, 0.2394492000, 0.5893407000, 1.4963987000", \ - "0.0295712000, 0.0370424000, 0.0561001000, 0.1060594000, 0.2391866000, 0.5894630000, 1.4967531000", \ - "0.0342199000, 0.0412223000, 0.0589371000, 0.1074019000, 0.2398952000, 0.5889731000, 1.4934574000", \ - "0.0449195000, 0.0514285000, 0.0685423000, 0.1119010000, 0.2411496000, 0.5918867000, 1.4948072000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.1195387000, 0.1266897000, 0.1420823000, 0.1738623000, 0.2400874000, 0.3750399000, 0.6800599000", \ - "0.1231716000, 0.1303176000, 0.1457339000, 0.1775590000, 0.2436955000, 0.3786673000, 0.6835952000", \ - "0.1335391000, 0.1406595000, 0.1558671000, 0.1878793000, 0.2541427000, 0.3890482000, 0.6939823000", \ - "0.1616821000, 0.1687492000, 0.1840401000, 0.2160270000, 0.2823546000, 0.4173525000, 0.7223935000", \ - "0.2279065000, 0.2353523000, 0.2509171000, 0.2831347000, 0.3498461000, 0.4854259000, 0.7906020000", \ - "0.3405787000, 0.3496270000, 0.3685615000, 0.4057111000, 0.4785983000, 0.6182131000, 0.9244090000", \ - "0.5235785000, 0.5354451000, 0.5591410000, 0.6045809000, 0.6920922000, 0.8472520000, 1.1610325000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0856402000, 0.0931770000, 0.1101132000, 0.1492143000, 0.2452250000, 0.4924125000, 1.1308632000", \ - "0.0899578000, 0.0974745000, 0.1144489000, 0.1535525000, 0.2495159000, 0.4960520000, 1.1328783000", \ - "0.1003320000, 0.1078305000, 0.1248491000, 0.1638799000, 0.2603688000, 0.5068959000, 1.1431156000", \ - "0.1242418000, 0.1316721000, 0.1484823000, 0.1874604000, 0.2833720000, 0.5294910000, 1.1662125000", \ - "0.1622063000, 0.1698893000, 0.1871486000, 0.2263814000, 0.3228313000, 0.5700624000, 1.2076947000", \ - "0.2051057000, 0.2135945000, 0.2317512000, 0.2710466000, 0.3681326000, 0.6149226000, 1.2521240000", \ - "0.2311606000, 0.2419425000, 0.2639673000, 0.3059508000, 0.4017837000, 0.6489811000, 1.2849237000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0262662000, 0.0316401000, 0.0449758000, 0.0756154000, 0.1412982000, 0.2847967000, 0.6653602000", \ - "0.0260750000, 0.0317586000, 0.0448622000, 0.0754223000, 0.1415178000, 0.2846259000, 0.6663674000", \ - "0.0262569000, 0.0318101000, 0.0449806000, 0.0753212000, 0.1413834000, 0.2845811000, 0.6663837000", \ - "0.0262075000, 0.0319793000, 0.0451077000, 0.0753912000, 0.1412081000, 0.2846417000, 0.6615449000", \ - "0.0287736000, 0.0341992000, 0.0469990000, 0.0767372000, 0.1426042000, 0.2855448000, 0.6647661000", \ - "0.0388530000, 0.0448975000, 0.0588603000, 0.0890306000, 0.1539302000, 0.2933679000, 0.6664190000", \ - "0.0538517000, 0.0613512000, 0.0782989000, 0.1142206000, 0.1840084000, 0.3181793000, 0.6726315000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012938900, 0.0033483300, 0.0086647700, 0.0224226000, 0.0580250000, 0.1501560000"); - values("0.0276424000, 0.0353184000, 0.0546223000, 0.1048076000, 0.2387206000, 0.5881299000, 1.4934537000", \ - "0.0276605000, 0.0353264000, 0.0546369000, 0.1047998000, 0.2386106000, 0.5884673000, 1.4956585000", \ - "0.0275822000, 0.0352675000, 0.0545883000, 0.1049052000, 0.2388497000, 0.5882547000, 1.4932779000", \ - "0.0277482000, 0.0352148000, 0.0543682000, 0.1045255000, 0.2383714000, 0.5873507000, 1.4938969000", \ - "0.0291994000, 0.0365708000, 0.0555683000, 0.1052525000, 0.2387322000, 0.5877347000, 1.4920721000", \ - "0.0348654000, 0.0418634000, 0.0590530000, 0.1070312000, 0.2400364000, 0.5875003000, 1.4951915000", \ - "0.0468608000, 0.0535968000, 0.0700301000, 0.1124713000, 0.2409081000, 0.5903036000, 1.4902077000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32a_2") { - leakage_power () { - value : 0.0041560000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0030443000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041734000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0041430000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0020884000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0038116000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0015077000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0023784000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0018642000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0038121000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0012838000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0021545000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015550000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0038115000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0009746000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0018453000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0018661000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0038115000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0012857000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0021564000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015566000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0038115000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0009763000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0018469000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0015605000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0038115000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0009802000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0018509000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015381000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0038115000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0009578000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0018284000; - when : "A1&A2&A3&B1&!B2"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o32a"; - cell_leakage_power : 0.0023829350; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041816000, 0.0041790000, 0.0041731000, 0.0041746000, 0.0041781000, 0.0041862000, 0.0042048000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004170400, -0.004167300, -0.004160100, -0.004158700, -0.004155500, -0.004148100, -0.004131000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024760000; - } - pin ("A2") { - capacitance : 0.0022960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038423000, 0.0038381000, 0.0038282000, 0.0038288000, 0.0038302000, 0.0038333000, 0.0038405000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003829300, -0.003829400, -0.003829600, -0.003830500, -0.003832800, -0.003838000, -0.003849900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024440000; - } - pin ("A3") { - capacitance : 0.0022950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039005000, 0.0038965000, 0.0038873000, 0.0038876000, 0.0038882000, 0.0038896000, 0.0038928000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003885500, -0.003882900, -0.003876800, -0.003877900, -0.003880500, -0.003886400, -0.003900100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024690000; - } - pin ("B1") { - capacitance : 0.0022760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045915000, 0.0045910000, 0.0045897000, 0.0045885000, 0.0045857000, 0.0045792000, 0.0045644000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000721800, -0.000738500, -0.000777200, -0.000752300, -0.000694800, -0.000562300, -0.000256800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023460000; - } - pin ("B2") { - capacitance : 0.0023010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045735000, 0.0045725000, 0.0045701000, 0.0045703000, 0.0045706000, 0.0045714000, 0.0045731000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000547200, -0.000559000, -0.000586200, -0.000563100, -0.000509700, -0.000386800, -0.000103500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024320000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A1&B2) | (A2&B1) | (A3&B1) | (A2&B2) | (A3&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0134146000, 0.0121150000, 0.0090340000, -0.001281600, -0.035180800, -0.143353700, -0.462106400", \ - "0.0134036000, 0.0120840000, 0.0088850000, -0.001344500, -0.035307900, -0.143465200, -0.462205500", \ - "0.0130666000, 0.0118537000, 0.0086560000, -0.001561500, -0.035534400, -0.143697300, -0.462443900", \ - "0.0128115000, 0.0115358000, 0.0083653000, -0.001938000, -0.035841000, -0.143974700, -0.462704400", \ - "0.0127551000, 0.0114556000, 0.0081462000, -0.002209800, -0.036123700, -0.144208900, -0.462900300", \ - "0.0148336000, 0.0132489000, 0.0087644000, -0.003001300, -0.036563000, -0.144429600, -0.463026400", \ - "0.0214228000, 0.0196801000, 0.0150924000, 0.0022180000, -0.035297600, -0.144205500, -0.462649000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0174859000, 0.0191698000, 0.0239861000, 0.0373206000, 0.0751609000, 0.1839254000, 0.5012694000", \ - "0.0174058000, 0.0190840000, 0.0238953000, 0.0373154000, 0.0750393000, 0.1837287000, 0.4992097000", \ - "0.0172899000, 0.0189525000, 0.0236952000, 0.0371446000, 0.0749267000, 0.1845769000, 0.4990330000", \ - "0.0172060000, 0.0188697000, 0.0236726000, 0.0370847000, 0.0748261000, 0.1844746000, 0.4989124000", \ - "0.0171026000, 0.0187229000, 0.0234200000, 0.0366503000, 0.0745536000, 0.1833697000, 0.4988134000", \ - "0.0180793000, 0.0196227000, 0.0241271000, 0.0370201000, 0.0747032000, 0.1831764000, 0.5009219000", \ - "0.0191732000, 0.0206770000, 0.0249895000, 0.0380215000, 0.0754808000, 0.1848446000, 0.4996918000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0112515000, 0.0099774000, 0.0067582000, -0.003507800, -0.037431800, -0.145595100, -0.464350000", \ - "0.0110216000, 0.0097250000, 0.0065622000, -0.003695100, -0.037581600, -0.145767000, -0.464518800", \ - "0.0107698000, 0.0094626000, 0.0063192000, -0.003940200, -0.037868900, -0.146016400, -0.464773200", \ - "0.0105078000, 0.0091966000, 0.0060244000, -0.004279300, -0.038210300, -0.146335400, -0.465044100", \ - "0.0105210000, 0.0091995000, 0.0059536000, -0.004525200, -0.038437700, -0.146413600, -0.465100000", \ - "0.0126097000, 0.0110852000, 0.0064994000, -0.004774200, -0.038433800, -0.146102400, -0.464793900", \ - "0.0204099000, 0.0186405000, 0.0138731000, 0.0007222000, -0.035706100, -0.145337100, -0.462954000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0160141000, 0.0176917000, 0.0224266000, 0.0358826000, 0.0736724000, 0.1824439000, 0.5003652000", \ - "0.0160073000, 0.0176842000, 0.0225079000, 0.0358845000, 0.0737096000, 0.1824235000, 0.4977656000", \ - "0.0159389000, 0.0176057000, 0.0224563000, 0.0358628000, 0.0736505000, 0.1823932000, 0.4977018000", \ - "0.0160105000, 0.0176769000, 0.0224337000, 0.0357790000, 0.0735152000, 0.1821970000, 0.4975459000", \ - "0.0156155000, 0.0172209000, 0.0219707000, 0.0351510000, 0.0729781000, 0.1817574000, 0.4972035000", \ - "0.0163546000, 0.0178934000, 0.0224252000, 0.0352576000, 0.0728177000, 0.1811408000, 0.4972878000", \ - "0.0172636000, 0.0187241000, 0.0230873000, 0.0362114000, 0.0736766000, 0.1830818000, 0.4983941000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0216089000, 0.0200341000, 0.0162113000, 0.0050558000, -0.030212800, -0.138842300, -0.457633600", \ - "0.0215583000, 0.0199937000, 0.0162165000, 0.0050155000, -0.030307200, -0.138982700, -0.457738100", \ - "0.0212804000, 0.0197221000, 0.0159082000, 0.0047980000, -0.030544200, -0.139144000, -0.457918400", \ - "0.0209990000, 0.0194117000, 0.0155815000, 0.0044702000, -0.030871800, -0.139273100, -0.458099100", \ - "0.0208725000, 0.0193314000, 0.0154768000, 0.0043659000, -0.031028800, -0.139577200, -0.458275000", \ - "0.0207701000, 0.0191752000, 0.0152720000, 0.0041947000, -0.031134300, -0.139621300, -0.458309300", \ - "0.0259628000, 0.0242441000, 0.0194599000, 0.0066452000, -0.031395400, -0.139553500, -0.458203900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0211368000, 0.0228127000, 0.0276229000, 0.0409203000, 0.0786213000, 0.1870056000, 0.5022701000", \ - "0.0209968000, 0.0226932000, 0.0274175000, 0.0408323000, 0.0784916000, 0.1870692000, 0.5042925000", \ - "0.0208243000, 0.0225053000, 0.0272830000, 0.0407088000, 0.0783758000, 0.1877073000, 0.5024261000", \ - "0.0206902000, 0.0223813000, 0.0271891000, 0.0406085000, 0.0782551000, 0.1868949000, 0.5039400000", \ - "0.0207721000, 0.0224026000, 0.0271164000, 0.0404226000, 0.0781530000, 0.1877222000, 0.5019937000", \ - "0.0213057000, 0.0228686000, 0.0273681000, 0.0403167000, 0.0780677000, 0.1863912000, 0.5042119000", \ - "0.0219455000, 0.0234471000, 0.0278582000, 0.0409994000, 0.0787092000, 0.1874718000, 0.5009091000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0195401000, 0.0179673000, 0.0141318000, 0.0030659000, -0.032248500, -0.140701000, -0.459372300", \ - "0.0194657000, 0.0178890000, 0.0140466000, 0.0029138000, -0.032305400, -0.140811200, -0.459468200", \ - "0.0192177000, 0.0176565000, 0.0138316000, 0.0027441000, -0.032398900, -0.140881300, -0.459584700", \ - "0.0190832000, 0.0174976000, 0.0136629000, 0.0025586000, -0.032768200, -0.141057600, -0.459762500", \ - "0.0188966000, 0.0173174000, 0.0135294000, 0.0024119000, -0.032867500, -0.141299900, -0.459919400", \ - "0.0190130000, 0.0174678000, 0.0135049000, 0.0025448000, -0.032791600, -0.141321700, -0.459960800", \ - "0.0240253000, 0.0222582000, 0.0174671000, 0.0051025000, -0.032553700, -0.140922600, -0.459667100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0197922000, 0.0214660000, 0.0262119000, 0.0396841000, 0.0776379000, 0.1867469000, 0.5022323000", \ - "0.0197863000, 0.0214595000, 0.0262769000, 0.0397407000, 0.0777005000, 0.1867016000, 0.5020312000", \ - "0.0197045000, 0.0213891000, 0.0262065000, 0.0396793000, 0.0775756000, 0.1874600000, 0.5044983000", \ - "0.0195170000, 0.0212005000, 0.0259912000, 0.0394384000, 0.0773854000, 0.1865515000, 0.5043787000", \ - "0.0194734000, 0.0211266000, 0.0257933000, 0.0391144000, 0.0770537000, 0.1861536000, 0.5040803000", \ - "0.0198249000, 0.0213877000, 0.0259943000, 0.0390280000, 0.0768779000, 0.1854333000, 0.5032941000", \ - "0.0205134000, 0.0219906000, 0.0264396000, 0.0394947000, 0.0772996000, 0.1863921000, 0.4995149000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0174983000, 0.0159829000, 0.0121513000, 0.0009995000, -0.034246800, -0.142645600, -0.461187300", \ - "0.0172780000, 0.0156826000, 0.0118846000, 0.0006885000, -0.034501500, -0.142701800, -0.461282000", \ - "0.0170550000, 0.0154543000, 0.0116079000, 0.0005161000, -0.034709200, -0.143030600, -0.461572500", \ - "0.0168794000, 0.0152769000, 0.0114252000, 0.0003220000, -0.034885700, -0.143231100, -0.461763600", \ - "0.0166424000, 0.0150627000, 0.0112297000, 0.0001520000, -0.034960800, -0.143163200, -0.461771100", \ - "0.0170030000, 0.0154045000, 0.0114363000, 0.0002952000, -0.034578400, -0.142910800, -0.461396700", \ - "0.0235227000, 0.0217127000, 0.0167780000, 0.0033412000, -0.034310100, -0.142438800, -0.460917100"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185820, 0.0122536300, 0.0355928700, 0.1033859000, 0.3003029000"); - values("0.0181202000, 0.0197625000, 0.0245620000, 0.0380577000, 0.0759922000, 0.1857648000, 0.5026606000", \ - "0.0181634000, 0.0198360000, 0.0245910000, 0.0380830000, 0.0760230000, 0.1849869000, 0.5026426000", \ - "0.0181259000, 0.0197660000, 0.0245674000, 0.0380427000, 0.0760007000, 0.1858792000, 0.5025074000", \ - "0.0180083000, 0.0196564000, 0.0244635000, 0.0379190000, 0.0758416000, 0.1856455000, 0.5026507000", \ - "0.0178358000, 0.0194791000, 0.0241238000, 0.0373920000, 0.0753242000, 0.1852350000, 0.5021386000", \ - "0.0182413000, 0.0198199000, 0.0243989000, 0.0373508000, 0.0749701000, 0.1834031000, 0.4997531000", \ - "0.0186819000, 0.0201456000, 0.0246301000, 0.0378728000, 0.0753482000, 0.1847464000, 0.4975760000"); - } - } - max_capacitance : 0.3003030000; - max_transition : 1.5016900000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.3420412000, 0.3502315000, 0.3688111000, 0.4034506000, 0.4675461000, 0.5973812000, 0.9113382000", \ - "0.3465642000, 0.3550378000, 0.3732199000, 0.4078476000, 0.4718215000, 0.6016685000, 0.9158024000", \ - "0.3581649000, 0.3663575000, 0.3848785000, 0.4195199000, 0.4836936000, 0.6133272000, 0.9273972000", \ - "0.3842929000, 0.3928173000, 0.4111595000, 0.4455566000, 0.5098544000, 0.6390208000, 0.9527329000", \ - "0.4413557000, 0.4498088000, 0.4681214000, 0.5021394000, 0.5663355000, 0.6962184000, 1.0105787000", \ - "0.5647022000, 0.5732335000, 0.5916777000, 0.6263557000, 0.6902196000, 0.8197653000, 1.1339338000", \ - "0.7947334000, 0.8051203000, 0.8258920000, 0.8657001000, 0.9345736000, 1.0713544000, 1.3885846000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1136444000, 0.1198049000, 0.1342007000, 0.1673828000, 0.2512990000, 0.4879385000, 1.1688654000", \ - "0.1180576000, 0.1242258000, 0.1386183000, 0.1719058000, 0.2559661000, 0.4914884000, 1.1759012000", \ - "0.1277271000, 0.1338475000, 0.1483018000, 0.1815687000, 0.2656099000, 0.5024255000, 1.1827852000", \ - "0.1477561000, 0.1539730000, 0.1683761000, 0.2015755000, 0.2856897000, 0.5212223000, 1.2060928000", \ - "0.1879482000, 0.1943221000, 0.2091842000, 0.2426614000, 0.3267518000, 0.5636586000, 1.2440204000", \ - "0.2455386000, 0.2528978000, 0.2690540000, 0.3044170000, 0.3894541000, 0.6257733000, 1.3099646000", \ - "0.2991986000, 0.3088990000, 0.3293302000, 0.3698143000, 0.4574301000, 0.6951998000, 1.3757374000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0439656000, 0.0484743000, 0.0585961000, 0.0797429000, 0.1286526000, 0.2556886000, 0.6373315000", \ - "0.0440853000, 0.0484454000, 0.0589758000, 0.0793534000, 0.1296460000, 0.2558976000, 0.6379939000", \ - "0.0439531000, 0.0484677000, 0.0587514000, 0.0792323000, 0.1293445000, 0.2555393000, 0.6392518000", \ - "0.0440568000, 0.0489455000, 0.0592659000, 0.0795210000, 0.1275904000, 0.2566405000, 0.6379689000", \ - "0.0438597000, 0.0485862000, 0.0586467000, 0.0802934000, 0.1281402000, 0.2560578000, 0.6372148000", \ - "0.0452485000, 0.0496182000, 0.0596515000, 0.0799347000, 0.1280366000, 0.2559881000, 0.6397988000", \ - "0.0543012000, 0.0588218000, 0.0697193000, 0.0916291000, 0.1412803000, 0.2656502000, 0.6424053000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0227991000, 0.0279243000, 0.0415240000, 0.0790105000, 0.1913075000, 0.5260026000, 1.4977437000", \ - "0.0227645000, 0.0280503000, 0.0415881000, 0.0790544000, 0.1912362000, 0.5246720000, 1.4980815000", \ - "0.0228816000, 0.0280549000, 0.0416309000, 0.0790880000, 0.1911633000, 0.5249873000, 1.4954121000", \ - "0.0226749000, 0.0279181000, 0.0413641000, 0.0789148000, 0.1912695000, 0.5242705000, 1.4974526000", \ - "0.0241628000, 0.0292304000, 0.0429753000, 0.0796254000, 0.1912761000, 0.5260394000, 1.4959644000", \ - "0.0295616000, 0.0348673000, 0.0483630000, 0.0835773000, 0.1925172000, 0.5248962000, 1.5010428000", \ - "0.0401329000, 0.0462192000, 0.0597360000, 0.0932741000, 0.1968441000, 0.5273209000, 1.4966053000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.3245244000, 0.3329726000, 0.3512151000, 0.3859824000, 0.4500250000, 0.5799782000, 0.8940049000", \ - "0.3282126000, 0.3366886000, 0.3550062000, 0.3897023000, 0.4538181000, 0.5837826000, 0.8978833000", \ - "0.3389494000, 0.3472054000, 0.3657689000, 0.4003977000, 0.4638449000, 0.5937730000, 0.9076596000", \ - "0.3650222000, 0.3735594000, 0.3918619000, 0.4263665000, 0.4906855000, 0.6199793000, 0.9338658000", \ - "0.4258793000, 0.4343654000, 0.4523877000, 0.4870225000, 0.5511753000, 0.6811705000, 0.9956819000", \ - "0.5655835000, 0.5741914000, 0.5928331000, 0.6272723000, 0.6920417000, 0.8219986000, 1.1361511000", \ - "0.8310368000, 0.8407177000, 0.8624834000, 0.9028891000, 0.9730833000, 1.1091127000, 1.4264412000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1099033000, 0.1158685000, 0.1301273000, 0.1631171000, 0.2471557000, 0.4835138000, 1.1658486000", \ - "0.1147418000, 0.1207676000, 0.1349654000, 0.1679125000, 0.2519376000, 0.4883045000, 1.1703424000", \ - "0.1245886000, 0.1306202000, 0.1448261000, 0.1777853000, 0.2617183000, 0.4989067000, 1.1815776000", \ - "0.1444784000, 0.1505120000, 0.1647400000, 0.1976571000, 0.2815670000, 0.5181163000, 1.2000018000", \ - "0.1831801000, 0.1894885000, 0.2041764000, 0.2375601000, 0.3217135000, 0.5583191000, 1.2432960000", \ - "0.2364613000, 0.2439335000, 0.2603810000, 0.2959285000, 0.3808230000, 0.6172904000, 1.3028104000", \ - "0.2810755000, 0.2909094000, 0.3117112000, 0.3526069000, 0.4405832000, 0.6780274000, 1.3590317000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0438527000, 0.0487157000, 0.0585485000, 0.0803522000, 0.1290731000, 0.2556887000, 0.6384884000", \ - "0.0439434000, 0.0489625000, 0.0584830000, 0.0805350000, 0.1286289000, 0.2556335000, 0.6373660000", \ - "0.0440051000, 0.0488241000, 0.0592935000, 0.0793808000, 0.1281680000, 0.2562305000, 0.6382893000", \ - "0.0440644000, 0.0489458000, 0.0591955000, 0.0794978000, 0.1275588000, 0.2566406000, 0.6383465000", \ - "0.0441925000, 0.0484351000, 0.0592217000, 0.0800348000, 0.1297342000, 0.2555306000, 0.6371439000", \ - "0.0458141000, 0.0498192000, 0.0595502000, 0.0808634000, 0.1294709000, 0.2559712000, 0.6377572000", \ - "0.0570266000, 0.0630938000, 0.0736513000, 0.0958214000, 0.1425282000, 0.2663209000, 0.6426327000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0219821000, 0.0271004000, 0.0406260000, 0.0777996000, 0.1899821000, 0.5236174000, 1.4970989000", \ - "0.0219814000, 0.0270690000, 0.0405148000, 0.0777330000, 0.1901292000, 0.5259480000, 1.5000710000", \ - "0.0219882000, 0.0270968000, 0.0405073000, 0.0777787000, 0.1897651000, 0.5251678000, 1.5016904000", \ - "0.0220833000, 0.0270995000, 0.0405340000, 0.0778720000, 0.1900711000, 0.5256720000, 1.4991413000", \ - "0.0238696000, 0.0290007000, 0.0424307000, 0.0789238000, 0.1901869000, 0.5259627000, 1.4982062000", \ - "0.0295846000, 0.0345959000, 0.0478879000, 0.0831304000, 0.1921122000, 0.5240710000, 1.4970206000", \ - "0.0406853000, 0.0470511000, 0.0605477000, 0.0944310000, 0.1967475000, 0.5266312000, 1.4941718000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.2875946000, 0.2958483000, 0.3143788000, 0.3490319000, 0.4131724000, 0.5430605000, 0.8573695000", \ - "0.2901930000, 0.2987115000, 0.3171560000, 0.3516040000, 0.4160584000, 0.5449671000, 0.8592045000", \ - "0.2984346000, 0.3069749000, 0.3251680000, 0.3598987000, 0.4240817000, 0.5541667000, 0.8683863000", \ - "0.3228530000, 0.3313749000, 0.3495850000, 0.3842470000, 0.4486100000, 0.5785171000, 0.8923759000", \ - "0.3865244000, 0.3950042000, 0.4132377000, 0.4479325000, 0.5115516000, 0.6414497000, 0.9557384000", \ - "0.5382637000, 0.5467732000, 0.5649873000, 0.5995127000, 0.6642678000, 0.7944068000, 1.1085938000", \ - "0.8183031000, 0.8290662000, 0.8522643000, 0.8949326000, 0.9663677000, 1.1001512000, 1.4181093000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0989474000, 0.1048523000, 0.1188521000, 0.1514416000, 0.2349692000, 0.4717682000, 1.1542127000", \ - "0.1039656000, 0.1098760000, 0.1238404000, 0.1564701000, 0.2399787000, 0.4757974000, 1.1606879000", \ - "0.1140255000, 0.1199112000, 0.1339136000, 0.1665054000, 0.2499753000, 0.4872079000, 1.1699952000", \ - "0.1341860000, 0.1400424000, 0.1540176000, 0.1865396000, 0.2701328000, 0.5067480000, 1.1884899000", \ - "0.1708467000, 0.1771878000, 0.1918073000, 0.2251221000, 0.3087051000, 0.5457240000, 1.2287629000", \ - "0.2176185000, 0.2251968000, 0.2421226000, 0.2776065000, 0.3623739000, 0.5983635000, 1.2821190000", \ - "0.2498258000, 0.2599294000, 0.2819928000, 0.3240803000, 0.4121199000, 0.6483381000, 1.3298047000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0439018000, 0.0484701000, 0.0586280000, 0.0795257000, 0.1287690000, 0.2550878000, 0.6391973000", \ - "0.0440507000, 0.0488742000, 0.0595929000, 0.0794573000, 0.1283736000, 0.2565555000, 0.6379116000", \ - "0.0437676000, 0.0485512000, 0.0587135000, 0.0799730000, 0.1289015000, 0.2555837000, 0.6372479000", \ - "0.0436976000, 0.0484639000, 0.0586426000, 0.0796688000, 0.1283448000, 0.2556273000, 0.6375452000", \ - "0.0442833000, 0.0484664000, 0.0588378000, 0.0806133000, 0.1281066000, 0.2564661000, 0.6392179000", \ - "0.0450891000, 0.0493399000, 0.0592322000, 0.0797638000, 0.1279614000, 0.2562378000, 0.6385386000", \ - "0.0643299000, 0.0704945000, 0.0814076000, 0.1012142000, 0.1440367000, 0.2657577000, 0.6431793000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0213047000, 0.0263778000, 0.0396423000, 0.0768682000, 0.1889490000, 0.5244937000, 1.5007262000", \ - "0.0212786000, 0.0262798000, 0.0397225000, 0.0769559000, 0.1893152000, 0.5252123000, 1.4964865000", \ - "0.0212693000, 0.0263739000, 0.0396278000, 0.0769000000, 0.1891985000, 0.5243460000, 1.5000760000", \ - "0.0212229000, 0.0264508000, 0.0395850000, 0.0769600000, 0.1893818000, 0.5251373000, 1.5002992000", \ - "0.0237314000, 0.0288387000, 0.0422100000, 0.0784315000, 0.1893783000, 0.5244237000, 1.5009862000", \ - "0.0303048000, 0.0355481000, 0.0486208000, 0.0834968000, 0.1911682000, 0.5235588000, 1.4968289000", \ - "0.0428197000, 0.0492297000, 0.0636880000, 0.0964469000, 0.1969224000, 0.5259327000, 1.4939948000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1562724000, 0.1623448000, 0.1762082000, 0.2052161000, 0.2667162000, 0.4000134000, 0.7146830000", \ - "0.1616113000, 0.1676842000, 0.1815231000, 0.2105589000, 0.2719100000, 0.4053937000, 0.7201738000", \ - "0.1736231000, 0.1796691000, 0.1934381000, 0.2224675000, 0.2839239000, 0.4173898000, 0.7320675000", \ - "0.1995780000, 0.2056368000, 0.2194511000, 0.2483420000, 0.3099413000, 0.4434006000, 0.7580834000", \ - "0.2582368000, 0.2642723000, 0.2780004000, 0.3068077000, 0.3685558000, 0.5022061000, 0.8169588000", \ - "0.3668720000, 0.3737925000, 0.3892819000, 0.4212000000, 0.4870834000, 0.6242953000, 0.9401169000", \ - "0.5510584000, 0.5592456000, 0.5781358000, 0.6158832000, 0.6911237000, 0.8424444000, 1.1668364000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1024617000, 0.1085810000, 0.1230198000, 0.1562485000, 0.2405219000, 0.4764311000, 1.1617869000", \ - "0.1065902000, 0.1127489000, 0.1271337000, 0.1603783000, 0.2445176000, 0.4817267000, 1.1632773000", \ - "0.1166314000, 0.1227727000, 0.1371800000, 0.1704746000, 0.2547478000, 0.4920909000, 1.1726476000", \ - "0.1413732000, 0.1474807000, 0.1618747000, 0.1950232000, 0.2791476000, 0.5164932000, 1.1970273000", \ - "0.1910038000, 0.1972886000, 0.2118508000, 0.2453263000, 0.3295258000, 0.5660092000, 1.2484056000", \ - "0.2546811000, 0.2620843000, 0.2780831000, 0.3129845000, 0.3974106000, 0.6342100000, 1.3193550000", \ - "0.3174993000, 0.3271473000, 0.3472579000, 0.3868643000, 0.4730467000, 0.7085809000, 1.3908966000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0262733000, 0.0303289000, 0.0401999000, 0.0639980000, 0.1220843000, 0.2563006000, 0.6363604000", \ - "0.0261264000, 0.0302850000, 0.0403304000, 0.0639582000, 0.1221653000, 0.2566476000, 0.6354814000", \ - "0.0263461000, 0.0302181000, 0.0400021000, 0.0640339000, 0.1221514000, 0.2558468000, 0.6363903000", \ - "0.0264024000, 0.0303543000, 0.0401358000, 0.0642112000, 0.1219925000, 0.2559970000, 0.6363748000", \ - "0.0268807000, 0.0307746000, 0.0409027000, 0.0646152000, 0.1224189000, 0.2563983000, 0.6363962000", \ - "0.0330097000, 0.0373600000, 0.0475180000, 0.0719109000, 0.1296498000, 0.2609439000, 0.6357008000", \ - "0.0458872000, 0.0504592000, 0.0618011000, 0.0881142000, 0.1503412000, 0.2820773000, 0.6425323000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0227788000, 0.0280021000, 0.0414848000, 0.0790646000, 0.1913106000, 0.5241756000, 1.4965713000", \ - "0.0227760000, 0.0279048000, 0.0414731000, 0.0790300000, 0.1912777000, 0.5259998000, 1.4983267000", \ - "0.0226982000, 0.0278296000, 0.0415970000, 0.0790584000, 0.1911659000, 0.5255314000, 1.4947424000", \ - "0.0225410000, 0.0276354000, 0.0413049000, 0.0789027000, 0.1911814000, 0.5256720000, 1.4948623000", \ - "0.0242615000, 0.0293252000, 0.0426652000, 0.0797068000, 0.1911931000, 0.5255720000, 1.4991983000", \ - "0.0309283000, 0.0358966000, 0.0483896000, 0.0831355000, 0.1928445000, 0.5252572000, 1.4982895000", \ - "0.0426799000, 0.0486140000, 0.0615155000, 0.0931397000, 0.1957512000, 0.5277528000, 1.4973466000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.1425609000, 0.1486585000, 0.1624262000, 0.1915262000, 0.2528242000, 0.3863105000, 0.7011182000", \ - "0.1465332000, 0.1525916000, 0.1661463000, 0.1951638000, 0.2564693000, 0.3899474000, 0.7047810000", \ - "0.1569439000, 0.1630112000, 0.1766348000, 0.2057791000, 0.2671935000, 0.4006618000, 0.7153890000", \ - "0.1849039000, 0.1909219000, 0.2047474000, 0.2337015000, 0.2952288000, 0.4287337000, 0.7433197000", \ - "0.2534356000, 0.2594576000, 0.2731783000, 0.3023131000, 0.3638582000, 0.4966682000, 0.8120078000", \ - "0.3830327000, 0.3905305000, 0.4070793000, 0.4399454000, 0.5064357000, 0.6445378000, 0.9584951000", \ - "0.5910012000, 0.6002355000, 0.6210595000, 0.6622360000, 0.7437590000, 0.8977432000, 1.2227780000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0903946000, 0.0964510000, 0.1106541000, 0.1437215000, 0.2278079000, 0.4638773000, 1.1465112000", \ - "0.0947608000, 0.1008159000, 0.1150891000, 0.1480721000, 0.2320466000, 0.4688780000, 1.1503570000", \ - "0.1051360000, 0.1112174000, 0.1254384000, 0.1583832000, 0.2423742000, 0.4792065000, 1.1606702000", \ - "0.1295152000, 0.1354162000, 0.1494345000, 0.1821244000, 0.2657885000, 0.5025788000, 1.1840241000", \ - "0.1725663000, 0.1786954000, 0.1931960000, 0.2269139000, 0.3103255000, 0.5471199000, 1.2282593000", \ - "0.2229577000, 0.2303714000, 0.2470540000, 0.2816036000, 0.3658906000, 0.6023350000, 1.2854787000", \ - "0.2594788000, 0.2694833000, 0.2905187000, 0.3307444000, 0.4167819000, 0.6527438000, 1.3345205000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0263480000, 0.0301221000, 0.0400163000, 0.0638578000, 0.1222688000, 0.2559447000, 0.6344675000", \ - "0.0261906000, 0.0303381000, 0.0400727000, 0.0638206000, 0.1222726000, 0.2561337000, 0.6344182000", \ - "0.0261545000, 0.0301185000, 0.0404155000, 0.0639748000, 0.1219840000, 0.2563390000, 0.6348511000", \ - "0.0261565000, 0.0302491000, 0.0401235000, 0.0640284000, 0.1220306000, 0.2567155000, 0.6360303000", \ - "0.0267854000, 0.0307410000, 0.0404582000, 0.0643469000, 0.1224252000, 0.2568077000, 0.6352710000", \ - "0.0375363000, 0.0423357000, 0.0519826000, 0.0756341000, 0.1318962000, 0.2620993000, 0.6359159000", \ - "0.0552592000, 0.0605724000, 0.0728354000, 0.1001363000, 0.1614372000, 0.2904066000, 0.6460847000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014523400, 0.0042185800, 0.0122536000, 0.0355929000, 0.1033860000, 0.3003030000"); - values("0.0221619000, 0.0272036000, 0.0408886000, 0.0782808000, 0.1901675000, 0.5247331000, 1.4989148000", \ - "0.0221046000, 0.0273552000, 0.0408432000, 0.0783435000, 0.1906258000, 0.5253140000, 1.4987547000", \ - "0.0220699000, 0.0272968000, 0.0407812000, 0.0781585000, 0.1905907000, 0.5253274000, 1.4987883000", \ - "0.0218924000, 0.0269274000, 0.0404739000, 0.0781814000, 0.1904436000, 0.5252963000, 1.4982794000", \ - "0.0245777000, 0.0296855000, 0.0425966000, 0.0792874000, 0.1903466000, 0.5255038000, 1.4962362000", \ - "0.0318478000, 0.0366807000, 0.0484845000, 0.0832253000, 0.1925036000, 0.5246251000, 1.5003210000", \ - "0.0443901000, 0.0503640000, 0.0634760000, 0.0947475000, 0.1955609000, 0.5283721000, 1.4964548000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32a_4") { - leakage_power () { - value : 0.0093865000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0076254000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0094194000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0093876000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0131066000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0089315000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0097119000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0118297000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0076435000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0089322000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0042486000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0063664000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0054414000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0089321000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0020465000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0041643000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0075086000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0089331000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0041137000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0062315000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0054449000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0089322000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0020496000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0041674000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0054330000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0089341000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0020380000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0041558000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0053047000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0089319000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0019098000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0040277000; - when : "A1&A2&A3&B1&!B2"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__o32a"; - cell_leakage_power : 0.0067278040; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0043510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079952000, 0.0079865000, 0.0079664000, 0.0079692000, 0.0079757000, 0.0079907000, 0.0080251000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007876900, -0.007874100, -0.007867600, -0.007870800, -0.007878200, -0.007895300, -0.007934800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045570000; - } - pin ("A2") { - capacitance : 0.0042450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079386000, 0.0079291000, 0.0079070000, 0.0079097000, 0.0079160000, 0.0079303000, 0.0079635000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007857200, -0.007856300, -0.007854300, -0.007851200, -0.007844200, -0.007828100, -0.007790900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045270000; - } - pin ("A3") { - capacitance : 0.0042940000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0082388000, 0.0082310000, 0.0082130000, 0.0082112000, 0.0082068000, 0.0081969000, 0.0081739000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008189200, -0.008184200, -0.008172500, -0.008169400, -0.008162100, -0.008145300, -0.008106600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046510000; - } - pin ("B1") { - capacitance : 0.0042390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091941000, 0.0091903000, 0.0091814000, 0.0091843000, 0.0091909000, 0.0092062000, 0.0092415000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001430600, -0.001472900, -0.001570300, -0.001516400, -0.001392100, -0.001105600, -0.000445400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044050000; - } - pin ("B2") { - capacitance : 0.0042170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092649000, 0.0092642000, 0.0092625000, 0.0092649000, 0.0092702000, 0.0092825000, 0.0093109000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001418900, -0.001448700, -0.001517400, -0.001469900, -0.001360400, -0.001108100, -0.000526400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044600000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A1&B2) | (A2&B1) | (A3&B1) | (A2&B2) | (A3&B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0457043000, 0.0437829000, 0.0383290000, 0.0228184000, -0.031390600, -0.220139800, -0.840718700", \ - "0.0455581000, 0.0436117000, 0.0382151000, 0.0227530000, -0.031443700, -0.220549600, -0.840979900", \ - "0.0451734000, 0.0432983000, 0.0377997000, 0.0223906000, -0.031857500, -0.220628100, -0.841197700", \ - "0.0451173000, 0.0432260000, 0.0376090000, 0.0221566000, -0.032030100, -0.221173800, -0.841613400", \ - "0.0444085000, 0.0425881000, 0.0370578000, 0.0217008000, -0.032543000, -0.221515400, -0.841871200", \ - "0.0447732000, 0.0429314000, 0.0373133000, 0.0218052000, -0.032720300, -0.221877400, -0.842115400", \ - "0.0545601000, 0.0523635000, 0.0461041000, 0.0271263000, -0.032011600, -0.221837800, -0.842127800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0429197000, 0.0447870000, 0.0509854000, 0.0708763000, 0.1319595000, 0.3246019000, 0.9400425000", \ - "0.0425347000, 0.0445133000, 0.0507383000, 0.0706265000, 0.1316929000, 0.3241994000, 0.9401735000", \ - "0.0423565000, 0.0442514000, 0.0505158000, 0.0702281000, 0.1313851000, 0.3242199000, 0.9386433000", \ - "0.0419108000, 0.0438219000, 0.0501038000, 0.0699286000, 0.1309796000, 0.3234774000, 0.9390490000", \ - "0.0418846000, 0.0440303000, 0.0501184000, 0.0696816000, 0.1306588000, 0.3233008000, 0.9423967000", \ - "0.0438381000, 0.0457128000, 0.0514949000, 0.0701667000, 0.1300364000, 0.3220577000, 0.9420025000", \ - "0.0452001000, 0.0469321000, 0.0527784000, 0.0715651000, 0.1314235000, 0.3240090000, 0.9368697000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0409297000, 0.0390522000, 0.0335384000, 0.0181844000, -0.035828200, -0.224988100, -0.845331700", \ - "0.0407685000, 0.0388473000, 0.0333872000, 0.0179295000, -0.036235400, -0.225180500, -0.845421600", \ - "0.0405229000, 0.0385752000, 0.0331596000, 0.0177079000, -0.036497100, -0.225594100, -0.845969100", \ - "0.0400729000, 0.0381882000, 0.0327353000, 0.0172431000, -0.036984200, -0.225729200, -0.846293000", \ - "0.0397067000, 0.0378519000, 0.0323258000, 0.0169244000, -0.037277600, -0.226350600, -0.846747800", \ - "0.0401084000, 0.0380745000, 0.0324493000, 0.0169242000, -0.037364100, -0.226619200, -0.846807000", \ - "0.0502909000, 0.0481688000, 0.0417167000, 0.0224864000, -0.037641800, -0.226684600, -0.846623100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0395613000, 0.0415751000, 0.0477936000, 0.0672979000, 0.1280675000, 0.3205658000, 0.9349088000", \ - "0.0396479000, 0.0415302000, 0.0476371000, 0.0672571000, 0.1281309000, 0.3201915000, 0.9342857000", \ - "0.0395153000, 0.0414037000, 0.0476438000, 0.0671509000, 0.1279228000, 0.3204590000, 0.9348257000", \ - "0.0391068000, 0.0410134000, 0.0472676000, 0.0668522000, 0.1276982000, 0.3200455000, 0.9351994000", \ - "0.0390553000, 0.0409748000, 0.0471969000, 0.0665343000, 0.1271950000, 0.3192372000, 0.9355423000", \ - "0.0398778000, 0.0416927000, 0.0476057000, 0.0663883000, 0.1265581000, 0.3181038000, 0.9334557000", \ - "0.0416282000, 0.0434252000, 0.0491869000, 0.0674288000, 0.1276963000, 0.3192591000, 0.9327795000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0362418000, 0.0343806000, 0.0289794000, 0.0134635000, -0.040812400, -0.229896300, -0.850265700", \ - "0.0358080000, 0.0339242000, 0.0284324000, 0.0129968000, -0.041208000, -0.230159200, -0.850552200", \ - "0.0354411000, 0.0335238000, 0.0280614000, 0.0126045000, -0.041617000, -0.230400800, -0.850932000", \ - "0.0349191000, 0.0330562000, 0.0275643000, 0.0122281000, -0.041958300, -0.231023000, -0.851347400", \ - "0.0347406000, 0.0328281000, 0.0273896000, 0.0118894000, -0.042338800, -0.231426600, -0.851742900", \ - "0.0358484000, 0.0338972000, 0.0282465000, 0.0125436000, -0.041937100, -0.231069300, -0.851126500", \ - "0.0506431000, 0.0484517000, 0.0418505000, 0.0223977000, -0.036971600, -0.227118600, -0.847431300"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0359283000, 0.0378282000, 0.0440853000, 0.0636111000, 0.1244188000, 0.3160895000, 0.9299288000", \ - "0.0360349000, 0.0379312000, 0.0441767000, 0.0637181000, 0.1244008000, 0.3166103000, 0.9306387000", \ - "0.0359663000, 0.0379126000, 0.0440536000, 0.0636657000, 0.1245127000, 0.3164734000, 0.9314713000", \ - "0.0356441000, 0.0375328000, 0.0438203000, 0.0634009000, 0.1241192000, 0.3160873000, 0.9304755000", \ - "0.0354905000, 0.0374160000, 0.0435212000, 0.0626111000, 0.1231999000, 0.3156737000, 0.9342956000", \ - "0.0361116000, 0.0379285000, 0.0437941000, 0.0627099000, 0.1225578000, 0.3138935000, 0.9298413000", \ - "0.0379849000, 0.0397639000, 0.0455313000, 0.0638384000, 0.1241133000, 0.3159176000, 0.9270070000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0278589000, 0.0263467000, 0.0219733000, 0.0080621000, -0.043384400, -0.231043200, -0.852024700", \ - "0.0276590000, 0.0260941000, 0.0216974000, 0.0077267000, -0.043592600, -0.231256400, -0.852232800", \ - "0.0274330000, 0.0257901000, 0.0214789000, 0.0074665000, -0.044013300, -0.231684700, -0.852642300", \ - "0.0267282000, 0.0252244000, 0.0207782000, 0.0068774000, -0.044632200, -0.232274100, -0.853176800", \ - "0.0263487000, 0.0248079000, 0.0203911000, 0.0060983000, -0.045424200, -0.232861900, -0.853665000", \ - "0.0275805000, 0.0256809000, 0.0198554000, 0.0050089000, -0.046034000, -0.233183400, -0.853773000", \ - "0.0436586000, 0.0416433000, 0.0354669000, 0.0165787000, -0.042631200, -0.232947800, -0.853243100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0366708000, 0.0385962000, 0.0448635000, 0.0645450000, 0.1257367000, 0.3185193000, 0.9320236000", \ - "0.0365077000, 0.0384045000, 0.0445746000, 0.0643913000, 0.1255210000, 0.3181312000, 0.9337654000", \ - "0.0361695000, 0.0380667000, 0.0443517000, 0.0642335000, 0.1252918000, 0.3179270000, 0.9331048000", \ - "0.0357545000, 0.0377131000, 0.0439389000, 0.0637006000, 0.1248928000, 0.3174280000, 0.9324048000", \ - "0.0359368000, 0.0378343000, 0.0439429000, 0.0634860000, 0.1236328000, 0.3164707000, 0.9328664000", \ - "0.0372811000, 0.0390876000, 0.0450124000, 0.0632649000, 0.1238305000, 0.3156721000, 0.9316596000", \ - "0.0402745000, 0.0419672000, 0.0477163000, 0.0663875000, 0.1257456000, 0.3175765000, 0.9309257000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0231539000, 0.0215249000, 0.0170558000, 0.0032606000, -0.048117600, -0.235562700, -0.856450200", \ - "0.0228792000, 0.0214161000, 0.0169640000, 0.0030321000, -0.048312500, -0.235841900, -0.856717500", \ - "0.0223473000, 0.0208159000, 0.0163494000, 0.0024457000, -0.048825600, -0.236352200, -0.857184300", \ - "0.0217210000, 0.0201595000, 0.0158205000, 0.0017925000, -0.049562400, -0.237061100, -0.857858400", \ - "0.0214075000, 0.0198167000, 0.0152800000, 0.0010485000, -0.050382300, -0.237589100, -0.858233500", \ - "0.0246294000, 0.0226291000, 0.0165657000, 0.0009267000, -0.049950900, -0.236954500, -0.857518800", \ - "0.0424356000, 0.0402689000, 0.0338257000, 0.0145207000, -0.044712700, -0.234914400, -0.855270600"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016096770, 0.0051821200, 0.0166830800, 0.0537087500, 0.1729075000, 0.5566504000"); - values("0.0325260000, 0.0345066000, 0.0407062000, 0.0604844000, 0.1217914000, 0.3139711000, 0.9285386000", \ - "0.0325844000, 0.0344574000, 0.0407607000, 0.0606841000, 0.1217277000, 0.3139776000, 0.9293349000", \ - "0.0326142000, 0.0345176000, 0.0407081000, 0.0605783000, 0.1217242000, 0.3141654000, 0.9293893000", \ - "0.0322859000, 0.0342293000, 0.0405124000, 0.0602799000, 0.1213277000, 0.3136986000, 0.9328106000", \ - "0.0324342000, 0.0343929000, 0.0401279000, 0.0599424000, 0.1199661000, 0.3129087000, 0.9283573000", \ - "0.0336791000, 0.0354730000, 0.0412382000, 0.0597827000, 0.1198403000, 0.3112314000, 0.9285972000", \ - "0.0359831000, 0.0376815000, 0.0434298000, 0.0617937000, 0.1214178000, 0.3132171000, 0.9262779000"); - } - } - max_capacitance : 0.5566500000; - max_transition : 1.5033630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.3374238000, 0.3428658000, 0.3570133000, 0.3880938000, 0.4517398000, 0.5867798000, 0.9378868000", \ - "0.3420642000, 0.3475130000, 0.3615453000, 0.3928944000, 0.4562940000, 0.5920468000, 0.9429860000", \ - "0.3539506000, 0.3593208000, 0.3734780000, 0.4046737000, 0.4683490000, 0.6034151000, 0.9544638000", \ - "0.3797618000, 0.3850454000, 0.3994484000, 0.4307207000, 0.4941276000, 0.6298845000, 0.9810073000", \ - "0.4335429000, 0.4389742000, 0.4530707000, 0.4840254000, 0.5474997000, 0.6832127000, 1.0346962000", \ - "0.5455875000, 0.5510737000, 0.5653810000, 0.5968788000, 0.6604858000, 0.7958005000, 1.1468563000", \ - "0.7457549000, 0.7517569000, 0.7680133000, 0.8027854000, 0.8725596000, 1.0155393000, 1.3706132000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1339664000, 0.1383595000, 0.1502299000, 0.1797273000, 0.2557103000, 0.4823635000, 1.1973705000", \ - "0.1382342000, 0.1426572000, 0.1546236000, 0.1841018000, 0.2600593000, 0.4867325000, 1.2022336000", \ - "0.1479599000, 0.1523643000, 0.1642214000, 0.1936406000, 0.2697735000, 0.4957367000, 1.2107753000", \ - "0.1671702000, 0.1715728000, 0.1834578000, 0.2128964000, 0.2889281000, 0.5153538000, 1.2333328000", \ - "0.2078375000, 0.2123729000, 0.2243302000, 0.2539014000, 0.3298582000, 0.5558492000, 1.2743534000", \ - "0.2728726000, 0.2778618000, 0.2909908000, 0.3220975000, 0.3988670000, 0.6245442000, 1.3434680000", \ - "0.3463795000, 0.3526182000, 0.3689148000, 0.4044361000, 0.4846256000, 0.7111969000, 1.4263811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0427416000, 0.0461229000, 0.0544953000, 0.0735815000, 0.1209224000, 0.2546715000, 0.6858198000", \ - "0.0426790000, 0.0457757000, 0.0549672000, 0.0741827000, 0.1225941000, 0.2542200000, 0.6870736000", \ - "0.0428332000, 0.0462222000, 0.0548912000, 0.0735872000, 0.1217855000, 0.2543784000, 0.6862417000", \ - "0.0428623000, 0.0462503000, 0.0549384000, 0.0747263000, 0.1225272000, 0.2539292000, 0.6857357000", \ - "0.0429356000, 0.0461523000, 0.0540487000, 0.0741470000, 0.1223739000, 0.2548940000, 0.6860744000", \ - "0.0445207000, 0.0473970000, 0.0556573000, 0.0753475000, 0.1219967000, 0.2549539000, 0.6868994000", \ - "0.0529111000, 0.0560639000, 0.0651716000, 0.0854348000, 0.1344779000, 0.2658163000, 0.6913922000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0256959000, 0.0292613000, 0.0394948000, 0.0690069000, 0.1633822000, 0.4784313000, 1.5027217000", \ - "0.0258626000, 0.0292779000, 0.0393795000, 0.0690924000, 0.1635075000, 0.4788874000, 1.5030456000", \ - "0.0255769000, 0.0290827000, 0.0393281000, 0.0690117000, 0.1634756000, 0.4788092000, 1.5010977000", \ - "0.0256756000, 0.0291940000, 0.0392303000, 0.0689749000, 0.1635637000, 0.4794485000, 1.5026074000", \ - "0.0263550000, 0.0301670000, 0.0400725000, 0.0694416000, 0.1634271000, 0.4786597000, 1.5018601000", \ - "0.0307179000, 0.0345627000, 0.0445329000, 0.0730720000, 0.1651770000, 0.4776780000, 1.5033631000", \ - "0.0405955000, 0.0445930000, 0.0557744000, 0.0831907000, 0.1698283000, 0.4801947000, 1.5010774000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.3183661000, 0.3237971000, 0.3378986000, 0.3691115000, 0.4322769000, 0.5680018000, 0.9192411000", \ - "0.3220856000, 0.3273768000, 0.3416451000, 0.3727365000, 0.4362056000, 0.5716361000, 0.9227775000", \ - "0.3324488000, 0.3379017000, 0.3519418000, 0.3832314000, 0.4466967000, 0.5824448000, 0.9333617000", \ - "0.3571660000, 0.3626117000, 0.3768160000, 0.4079182000, 0.4715260000, 0.6066248000, 0.9577322000", \ - "0.4132117000, 0.4185360000, 0.4326273000, 0.4638146000, 0.5272028000, 0.6628985000, 1.0141087000", \ - "0.5403712000, 0.5459728000, 0.5602422000, 0.5922895000, 0.6554853000, 0.7916747000, 1.1427179000", \ - "0.7737040000, 0.7800448000, 0.7970892000, 0.8329969000, 0.9032699000, 1.0464302000, 1.4023775000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1234323000, 0.1276451000, 0.1388782000, 0.1671259000, 0.2413519000, 0.4659013000, 1.1817889000", \ - "0.1282702000, 0.1324166000, 0.1436412000, 0.1719099000, 0.2462965000, 0.4709902000, 1.1845077000", \ - "0.1378971000, 0.1420649000, 0.1533673000, 0.1815577000, 0.2558067000, 0.4803765000, 1.1964174000", \ - "0.1567299000, 0.1609433000, 0.1721916000, 0.2003875000, 0.2747726000, 0.4990674000, 1.2147833000", \ - "0.1945604000, 0.1988391000, 0.2103682000, 0.2389335000, 0.3134756000, 0.5379799000, 1.2536427000", \ - "0.2503916000, 0.2552684000, 0.2681369000, 0.2986444000, 0.3745037000, 0.5991342000, 1.3142215000", \ - "0.3034725000, 0.3097957000, 0.3260977000, 0.3617076000, 0.4412667000, 0.6664227000, 1.3811023000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0429938000, 0.0462168000, 0.0540798000, 0.0736395000, 0.1222221000, 0.2546751000, 0.6866215000", \ - "0.0428160000, 0.0461840000, 0.0544970000, 0.0735851000, 0.1211185000, 0.2552474000, 0.6863130000", \ - "0.0426376000, 0.0458086000, 0.0549568000, 0.0740209000, 0.1226275000, 0.2542165000, 0.6868658000", \ - "0.0429655000, 0.0462480000, 0.0544612000, 0.0735675000, 0.1210600000, 0.2551038000, 0.6854565000", \ - "0.0428341000, 0.0460941000, 0.0541903000, 0.0737531000, 0.1216580000, 0.2550197000, 0.6864096000", \ - "0.0450817000, 0.0481145000, 0.0563018000, 0.0761587000, 0.1240651000, 0.2550036000, 0.6865623000", \ - "0.0564374000, 0.0594934000, 0.0681679000, 0.0887337000, 0.1360408000, 0.2664476000, 0.6918377000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0239128000, 0.0271534000, 0.0370699000, 0.0663926000, 0.1610106000, 0.4770273000, 1.5025268000", \ - "0.0238435000, 0.0272504000, 0.0372421000, 0.0665200000, 0.1608374000, 0.4781932000, 1.4985306000", \ - "0.0237399000, 0.0271589000, 0.0372292000, 0.0664106000, 0.1610395000, 0.4770642000, 1.5031868000", \ - "0.0238023000, 0.0272425000, 0.0370813000, 0.0662854000, 0.1610316000, 0.4780263000, 1.5017524000", \ - "0.0253283000, 0.0287259000, 0.0384883000, 0.0672638000, 0.1613656000, 0.4770109000, 1.5028326000", \ - "0.0299458000, 0.0337452000, 0.0434875000, 0.0716147000, 0.1635923000, 0.4762973000, 1.5007138000", \ - "0.0407747000, 0.0446348000, 0.0556323000, 0.0830951000, 0.1692307000, 0.4782402000, 1.4959580000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.2773952000, 0.2828373000, 0.2969399000, 0.3281382000, 0.3915401000, 0.5273045000, 0.8785163000", \ - "0.2799952000, 0.2854280000, 0.2995680000, 0.3306826000, 0.3942691000, 0.5301882000, 0.8804502000", \ - "0.2878505000, 0.2932872000, 0.3074740000, 0.3385169000, 0.4021811000, 0.5375013000, 0.8884460000", \ - "0.3099519000, 0.3153711000, 0.3295237000, 0.3604971000, 0.4239220000, 0.5596689000, 0.9111476000", \ - "0.3693253000, 0.3747245000, 0.3889580000, 0.4200360000, 0.4834543000, 0.6192335000, 0.9704134000", \ - "0.5098268000, 0.5153938000, 0.5295176000, 0.5607911000, 0.6239672000, 0.7603168000, 1.1117149000", \ - "0.7529789000, 0.7599040000, 0.7773030000, 0.8153439000, 0.8841055000, 1.0242200000, 1.3800142000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1110479000, 0.1151638000, 0.1262837000, 0.1543039000, 0.2282925000, 0.4524888000, 1.1652799000", \ - "0.1160951000, 0.1201941000, 0.1313545000, 0.1593354000, 0.2332095000, 0.4570912000, 1.1728721000", \ - "0.1262949000, 0.1304098000, 0.1415213000, 0.1695305000, 0.2435278000, 0.4669676000, 1.1822991000", \ - "0.1460656000, 0.1501523000, 0.1613155000, 0.1892686000, 0.2632102000, 0.4872155000, 1.2013244000", \ - "0.1836185000, 0.1879610000, 0.1994961000, 0.2280943000, 0.3021857000, 0.5264020000, 1.2438087000", \ - "0.2365001000, 0.2415490000, 0.2545920000, 0.2853955000, 0.3614726000, 0.5856539000, 1.3021361000", \ - "0.2854872000, 0.2920827000, 0.3090902000, 0.3461616000, 0.4267094000, 0.6513443000, 1.3658724000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0427516000, 0.0459540000, 0.0540473000, 0.0748921000, 0.1215321000, 0.2547279000, 0.6868898000", \ - "0.0427922000, 0.0459956000, 0.0547697000, 0.0736522000, 0.1217978000, 0.2549178000, 0.6863154000", \ - "0.0427830000, 0.0459485000, 0.0546447000, 0.0736137000, 0.1218787000, 0.2549397000, 0.6854326000", \ - "0.0428576000, 0.0461286000, 0.0539916000, 0.0741412000, 0.1215688000, 0.2549921000, 0.6870848000", \ - "0.0430956000, 0.0463428000, 0.0547220000, 0.0735574000, 0.1215049000, 0.2545957000, 0.6866476000", \ - "0.0454232000, 0.0485037000, 0.0565395000, 0.0748300000, 0.1222023000, 0.2554178000, 0.6869203000", \ - "0.0641246000, 0.0678637000, 0.0780255000, 0.0946842000, 0.1386974000, 0.2648934000, 0.6924227000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0231624000, 0.0265384000, 0.0364289000, 0.0657385000, 0.1599573000, 0.4775295000, 1.4982469000", \ - "0.0232164000, 0.0266241000, 0.0365010000, 0.0656866000, 0.1603002000, 0.4765651000, 1.5030409000", \ - "0.0232900000, 0.0266516000, 0.0365303000, 0.0655934000, 0.1602909000, 0.4769416000, 1.5015771000", \ - "0.0231642000, 0.0266019000, 0.0364050000, 0.0655667000, 0.1602243000, 0.4780247000, 1.4998736000", \ - "0.0251638000, 0.0285734000, 0.0384667000, 0.0671093000, 0.1607044000, 0.4768108000, 1.5019355000", \ - "0.0310325000, 0.0343431000, 0.0449412000, 0.0723698000, 0.1634560000, 0.4760773000, 1.5010372000", \ - "0.0428709000, 0.0471168000, 0.0585563000, 0.0855852000, 0.1704072000, 0.4785917000, 1.4977196000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1798884000, 0.1842811000, 0.1958874000, 0.2235323000, 0.2875499000, 0.4363642000, 0.7980317000", \ - "0.1847473000, 0.1891439000, 0.2007564000, 0.2286807000, 0.2924379000, 0.4411611000, 0.8030360000", \ - "0.1965174000, 0.2008173000, 0.2124604000, 0.2402093000, 0.3041265000, 0.4528170000, 0.8145651000", \ - "0.2225968000, 0.2269761000, 0.2385611000, 0.2662559000, 0.3301646000, 0.4789126000, 0.8406479000", \ - "0.2811233000, 0.2854791000, 0.2970047000, 0.3246641000, 0.3885965000, 0.5375727000, 0.8994000000", \ - "0.3927419000, 0.3975580000, 0.4105565000, 0.4407682000, 0.5086535000, 0.6609721000, 1.0239646000", \ - "0.5804688000, 0.5861794000, 0.6015243000, 0.6370933000, 0.7150790000, 0.8824114000, 1.2560522000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1228419000, 0.1272559000, 0.1390930000, 0.1685002000, 0.2446634000, 0.4704938000, 1.1866442000", \ - "0.1268247000, 0.1312255000, 0.1430589000, 0.1725172000, 0.2485434000, 0.4752195000, 1.1904326000", \ - "0.1366578000, 0.1410508000, 0.1529261000, 0.1823712000, 0.2584787000, 0.4847660000, 1.2031407000", \ - "0.1610592000, 0.1654460000, 0.1773060000, 0.2066955000, 0.2827238000, 0.5088786000, 1.2273812000", \ - "0.2145764000, 0.2190063000, 0.2308226000, 0.2600239000, 0.3355853000, 0.5619346000, 1.2779251000", \ - "0.2894196000, 0.2944544000, 0.3072686000, 0.3375853000, 0.4139136000, 0.6397413000, 1.3594158000", \ - "0.3682289000, 0.3746690000, 0.3912481000, 0.4260677000, 0.5038518000, 0.7291139000, 1.4452093000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0295786000, 0.0325736000, 0.0405721000, 0.0637195000, 0.1229063000, 0.2704127000, 0.6930111000", \ - "0.0293428000, 0.0323095000, 0.0406151000, 0.0632609000, 0.1229018000, 0.2702811000, 0.6926913000", \ - "0.0295602000, 0.0325387000, 0.0410767000, 0.0636086000, 0.1229147000, 0.2701370000, 0.6928036000", \ - "0.0296441000, 0.0323526000, 0.0410456000, 0.0636636000, 0.1228861000, 0.2702635000, 0.6929461000", \ - "0.0296198000, 0.0325670000, 0.0413529000, 0.0635578000, 0.1230838000, 0.2704930000, 0.6929465000", \ - "0.0358784000, 0.0390061000, 0.0476344000, 0.0710666000, 0.1302490000, 0.2750111000, 0.6934493000", \ - "0.0495209000, 0.0530483000, 0.0624386000, 0.0880169000, 0.1505446000, 0.2969490000, 0.7026522000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0254994000, 0.0290467000, 0.0392715000, 0.0689834000, 0.1634745000, 0.4789511000, 1.4984879000", \ - "0.0256075000, 0.0290736000, 0.0394356000, 0.0688962000, 0.1632227000, 0.4782173000, 1.5028874000", \ - "0.0256901000, 0.0291805000, 0.0392800000, 0.0689555000, 0.1635447000, 0.4791726000, 1.5003232000", \ - "0.0253880000, 0.0290047000, 0.0391418000, 0.0687133000, 0.1632940000, 0.4788765000, 1.5002158000", \ - "0.0263353000, 0.0296940000, 0.0396035000, 0.0690251000, 0.1634426000, 0.4792951000, 1.5030384000", \ - "0.0323501000, 0.0356116000, 0.0448838000, 0.0727960000, 0.1652831000, 0.4787433000, 1.5007050000", \ - "0.0440457000, 0.0481102000, 0.0582553000, 0.0837788000, 0.1693355000, 0.4808101000, 1.4985173000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1563498000, 0.1607132000, 0.1723696000, 0.2002537000, 0.2641203000, 0.4131478000, 0.7752374000", \ - "0.1597902000, 0.1641771000, 0.1758182000, 0.2036868000, 0.2677792000, 0.4167975000, 0.7787206000", \ - "0.1691352000, 0.1733856000, 0.1849535000, 0.2129602000, 0.2769606000, 0.4260820000, 0.7880583000", \ - "0.1943542000, 0.1986614000, 0.2107449000, 0.2385334000, 0.3027572000, 0.4520086000, 0.8138941000", \ - "0.2595313000, 0.2638225000, 0.2752859000, 0.3029345000, 0.3668527000, 0.5160483000, 0.8779824000", \ - "0.3823531000, 0.3874468000, 0.4008861000, 0.4321576000, 0.4997004000, 0.6533893000, 1.0170251000", \ - "0.5750908000, 0.5813734000, 0.5982075000, 0.6365936000, 0.7182769000, 0.8893892000, 1.2645140000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.1096369000, 0.1140901000, 0.1260426000, 0.1554752000, 0.2317209000, 0.4569075000, 1.1735680000", \ - "0.1140660000, 0.1184828000, 0.1303928000, 0.1599480000, 0.2360141000, 0.4621647000, 1.1795187000", \ - "0.1247170000, 0.1291329000, 0.1409516000, 0.1704706000, 0.2465801000, 0.4728312000, 1.1874501000", \ - "0.1493424000, 0.1537138000, 0.1656153000, 0.1948892000, 0.2707764000, 0.4964736000, 1.2140217000", \ - "0.2002453000, 0.2046982000, 0.2165936000, 0.2458956000, 0.3209036000, 0.5470814000, 1.2619231000", \ - "0.2668666000, 0.2720933000, 0.2852117000, 0.3157513000, 0.3917823000, 0.6176832000, 1.3341687000", \ - "0.3312898000, 0.3380530000, 0.3549651000, 0.3914100000, 0.4697485000, 0.6948718000, 1.4109246000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0295097000, 0.0323250000, 0.0407369000, 0.0634212000, 0.1231931000, 0.2707848000, 0.6923234000", \ - "0.0294355000, 0.0325973000, 0.0410636000, 0.0636316000, 0.1232522000, 0.2708736000, 0.6931063000", \ - "0.0295571000, 0.0324043000, 0.0410426000, 0.0634039000, 0.1230552000, 0.2706134000, 0.6930100000", \ - "0.0294336000, 0.0323898000, 0.0410711000, 0.0634420000, 0.1232523000, 0.2706007000, 0.6920777000", \ - "0.0298633000, 0.0325331000, 0.0408954000, 0.0638586000, 0.1236296000, 0.2710591000, 0.6932042000", \ - "0.0404869000, 0.0436052000, 0.0524097000, 0.0744115000, 0.1326549000, 0.2769748000, 0.6942268000", \ - "0.0584583000, 0.0620433000, 0.0726980000, 0.0995353000, 0.1620075000, 0.3038573000, 0.7057341000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016096800, 0.0051821200, 0.0166831000, 0.0537087000, 0.1729070000, 0.5566500000"); - values("0.0254277000, 0.0289086000, 0.0392810000, 0.0687403000, 0.1630203000, 0.4779973000, 1.4994486000", \ - "0.0254514000, 0.0291269000, 0.0392080000, 0.0688759000, 0.1632396000, 0.4788459000, 1.5018214000", \ - "0.0254658000, 0.0289534000, 0.0392746000, 0.0687725000, 0.1630841000, 0.4777256000, 1.5021767000", \ - "0.0250591000, 0.0285975000, 0.0388727000, 0.0683385000, 0.1628134000, 0.4780131000, 1.5029122000", \ - "0.0265874000, 0.0301617000, 0.0402774000, 0.0693071000, 0.1629754000, 0.4775571000, 1.5021843000", \ - "0.0337357000, 0.0369968000, 0.0460878000, 0.0737215000, 0.1651911000, 0.4773439000, 1.5027919000", \ - "0.0463831000, 0.0504869000, 0.0607555000, 0.0858109000, 0.1705038000, 0.4802090000, 1.5010300000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32ai_1") { - leakage_power () { - value : 0.0010565000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0001174000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0010700000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0010448000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0015935000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0008169000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0020881000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0014623000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0006858000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0019570000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0009801000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0002036000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0014748000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0021497000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0008249000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0013732000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0026444000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0010457000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0002691000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0015403000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0010471000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0002706000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0015418000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0009647000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0008244000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0001881000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0014593000; - when : "A1&A2&A3&B1&!B2"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o32ai"; - cell_leakage_power : 0.0010880000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040336000, 0.0040379000, 0.0040478000, 0.0040465000, 0.0040436000, 0.0040369000, 0.0040215000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004040000, -0.004038200, -0.004034200, -0.004033400, -0.004031600, -0.004027400, -0.004017700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024080000; - } - pin ("A2") { - capacitance : 0.0024000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041536000, 0.0041500000, 0.0041417000, 0.0041409000, 0.0041391000, 0.0041349000, 0.0041252000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004142500, -0.004141300, -0.004138400, -0.004139300, -0.004141500, -0.004146400, -0.004157900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025480000; - } - pin ("A3") { - capacitance : 0.0022880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038631000, 0.0038633000, 0.0038639000, 0.0038633000, 0.0038620000, 0.0038590000, 0.0038519000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003860400, -0.003859600, -0.003857700, -0.003858500, -0.003860400, -0.003864700, -0.003874600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024590000; - } - pin ("B1") { - capacitance : 0.0023490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047217000, 0.0047195000, 0.0047145000, 0.0047155000, 0.0047180000, 0.0047236000, 0.0047366000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000900800, -0.000911500, -0.000936400, -0.000915000, -0.000865800, -0.000752500, -0.000491200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024070000; - } - pin ("B2") { - capacitance : 0.0023840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046525000, 0.0046562000, 0.0046647000, 0.0046631000, 0.0046594000, 0.0046508000, 0.0046310000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000782500, -0.000795400, -0.000825200, -0.000803700, -0.000754200, -0.000640200, -0.000377400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024980000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0084505000, 0.0075356000, 0.0056117000, 0.0014946000, -0.007247800, -0.025960900, -0.065944900", \ - "0.0083346000, 0.0074423000, 0.0054965000, 0.0013719000, -0.007390600, -0.026076500, -0.066071500", \ - "0.0082135000, 0.0073087000, 0.0053724000, 0.0012469000, -0.007489000, -0.026185400, -0.066182100", \ - "0.0080953000, 0.0072047000, 0.0052606000, 0.0011534000, -0.007581400, -0.026281600, -0.066209100", \ - "0.0079965000, 0.0070938000, 0.0051636000, 0.0011280000, -0.007593600, -0.026283200, -0.066241600", \ - "0.0081989000, 0.0072784000, 0.0053402000, 0.0011740000, -0.007697900, -0.026400300, -0.066285000", \ - "0.0088520000, 0.0079102000, 0.0059838000, 0.0017816000, -0.007151800, -0.025949600, -0.066255700"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0169744000, 0.0178952000, 0.0198698000, 0.0240255000, 0.0328440000, 0.0515009000, 0.0911492000", \ - "0.0168437000, 0.0177682000, 0.0197584000, 0.0239148000, 0.0327520000, 0.0514729000, 0.0911433000", \ - "0.0166702000, 0.0175989000, 0.0195902000, 0.0237769000, 0.0326374000, 0.0514037000, 0.0910853000", \ - "0.0165289000, 0.0174597000, 0.0194366000, 0.0236245000, 0.0324919000, 0.0512222000, 0.0910126000", \ - "0.0164520000, 0.0173781000, 0.0193545000, 0.0235294000, 0.0323480000, 0.0510735000, 0.0908145000", \ - "0.0164222000, 0.0173437000, 0.0193270000, 0.0234211000, 0.0322650000, 0.0509824000, 0.0907977000", \ - "0.0163092000, 0.0171730000, 0.0191886000, 0.0235312000, 0.0324882000, 0.0511474000, 0.0909078000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0073036000, 0.0063960000, 0.0044998000, 0.0003681000, -0.008419300, -0.027168700, -0.067207300", \ - "0.0072706000, 0.0063660000, 0.0044654000, 0.0003397000, -0.008437100, -0.027205600, -0.067242000", \ - "0.0071811000, 0.0062887000, 0.0043653000, 0.0002790000, -0.008493100, -0.027233600, -0.067257300", \ - "0.0069962000, 0.0061038000, 0.0042177000, 0.0001478000, -0.008583800, -0.027287500, -0.067308700", \ - "0.0067951000, 0.0059052000, 0.0040097000, 4.400000e-06, -0.008672000, -0.027336600, -0.067309900", \ - "0.0068453000, 0.0059485000, 0.0040290000, -4.89000e-05, -0.008872600, -0.027562700, -0.067400600", \ - "0.0073328000, 0.0064228000, 0.0044391000, 0.0002640000, -0.008602500, -0.027400700, -0.067511700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0149354000, 0.0158544000, 0.0178340000, 0.0219918000, 0.0307804000, 0.0494932000, 0.0891640000", \ - "0.0148074000, 0.0157249000, 0.0176979000, 0.0218830000, 0.0307069000, 0.0494553000, 0.0890618000", \ - "0.0146568000, 0.0155410000, 0.0175313000, 0.0217344000, 0.0305979000, 0.0493718000, 0.0889726000", \ - "0.0144488000, 0.0153787000, 0.0173624000, 0.0215553000, 0.0304342000, 0.0492390000, 0.0889499000", \ - "0.0143587000, 0.0152726000, 0.0172455000, 0.0214121000, 0.0302870000, 0.0490702000, 0.0888478000", \ - "0.0143296000, 0.0152463000, 0.0171661000, 0.0213630000, 0.0302601000, 0.0489942000, 0.0886576000", \ - "0.0145951000, 0.0154614000, 0.0173645000, 0.0214878000, 0.0302988000, 0.0490705000, 0.0890133000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0053616000, 0.0044624000, 0.0025598000, -0.001541000, -0.010334200, -0.029111100, -0.069196100", \ - "0.0053466000, 0.0044673000, 0.0025713000, -0.001509800, -0.010276300, -0.029041500, -0.069118800", \ - "0.0052563000, 0.0043844000, 0.0025263000, -0.001516000, -0.010252600, -0.028995100, -0.069049800", \ - "0.0050772000, 0.0042070000, 0.0023495000, -0.001664800, -0.010343000, -0.029025800, -0.069040100", \ - "0.0049490000, 0.0040849000, 0.0021343000, -0.001904300, -0.010538400, -0.029119000, -0.069079300", \ - "0.0048284000, 0.0039590000, 0.0020620000, -0.002055700, -0.010730300, -0.029422600, -0.069256000", \ - "0.0053361000, 0.0043713000, 0.0024268000, -0.001759300, -0.010620400, -0.029371700, -0.069409600"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0128332000, 0.0137270000, 0.0157013000, 0.0198767000, 0.0287018000, 0.0473687000, 0.0870564000", \ - "0.0125885000, 0.0135693000, 0.0155133000, 0.0197372000, 0.0285972000, 0.0473475000, 0.0870827000", \ - "0.0123019000, 0.0132323000, 0.0152367000, 0.0194966000, 0.0284003000, 0.0471707000, 0.0868694000", \ - "0.0121805000, 0.0130937000, 0.0150996000, 0.0192769000, 0.0281942000, 0.0470184000, 0.0867944000", \ - "0.0121846000, 0.0130986000, 0.0150102000, 0.0192430000, 0.0280587000, 0.0468155000, 0.0866758000", \ - "0.0124177000, 0.0133351000, 0.0152307000, 0.0193591000, 0.0281273000, 0.0467924000, 0.0863174000", \ - "0.0139318000, 0.0148060000, 0.0167579000, 0.0205309000, 0.0290971000, 0.0476493000, 0.0870039000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0053638000, 0.0044605000, 0.0025212000, -0.001578400, -0.010337800, -0.029036600, -0.069008400", \ - "0.0052344000, 0.0043373000, 0.0024152000, -0.001679800, -0.010420800, -0.029113600, -0.069086500", \ - "0.0051117000, 0.0042071000, 0.0022923000, -0.001799100, -0.010489700, -0.029150800, -0.069111300", \ - "0.0049897000, 0.0040989000, 0.0021698000, -0.001913800, -0.010605300, -0.029267200, -0.069178000", \ - "0.0048128000, 0.0039145000, 0.0019946000, -0.002059200, -0.010786700, -0.029424700, -0.069309000", \ - "0.0051782000, 0.0042459000, 0.0022720000, -0.001912700, -0.010680400, -0.029407300, -0.069373500", \ - "0.0063038000, 0.0053694000, 0.0033604000, -0.000818500, -0.009969400, -0.028866000, -0.069332100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0092591000, 0.0102292000, 0.0122349000, 0.0164523000, 0.0252434000, 0.0438819000, 0.0833590000", \ - "0.0090353000, 0.0100097000, 0.0120555000, 0.0163062000, 0.0252005000, 0.0438567000, 0.0834674000", \ - "0.0087895000, 0.0097619000, 0.0117894000, 0.0160642000, 0.0250086000, 0.0437626000, 0.0834635000", \ - "0.0086218000, 0.0095605000, 0.0115681000, 0.0157891000, 0.0247165000, 0.0435283000, 0.0832051000", \ - "0.0085034000, 0.0094375000, 0.0114108000, 0.0155988000, 0.0244770000, 0.0432290000, 0.0829535000", \ - "0.0085160000, 0.0094308000, 0.0113808000, 0.0155696000, 0.0244688000, 0.0431635000, 0.0829149000", \ - "0.0091595000, 0.0099998000, 0.0118195000, 0.0157545000, 0.0246286000, 0.0432370000, 0.0830261000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0039626000, 0.0030755000, 0.0011775000, -0.002894900, -0.011605500, -0.030301700, -0.070274500", \ - "0.0039223000, 0.0030460000, 0.0011563000, -0.002885700, -0.011578600, -0.030239200, -0.070239700", \ - "0.0038586000, 0.0029788000, 0.0010930000, -0.002955600, -0.011595800, -0.030222100, -0.070183300", \ - "0.0036260000, 0.0027521000, 0.0008592000, -0.003103200, -0.011750100, -0.030355400, -0.070272300", \ - "0.0034494000, 0.0025482000, 0.0006576000, -0.003411300, -0.012019600, -0.030555700, -0.070404500", \ - "0.0038152000, 0.0028908000, 0.0009761000, -0.003183400, -0.012222400, -0.030855500, -0.070632000", \ - "0.0046821000, 0.0037168000, 0.0016617000, -0.002613200, -0.011587400, -0.030361600, -0.070603800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010650350, 0.0022686010, 0.0048322810, 0.0102931000, 0.0219250400, 0.0467018800"); - values("0.0069346000, 0.0079385000, 0.0100013000, 0.0142260000, 0.0230641000, 0.0417195000, 0.0812153000", \ - "0.0066224000, 0.0076115000, 0.0097110000, 0.0140205000, 0.0229713000, 0.0416857000, 0.0813538000", \ - "0.0063977000, 0.0073732000, 0.0093859000, 0.0136661000, 0.0226882000, 0.0415631000, 0.0812689000", \ - "0.0062469000, 0.0071916000, 0.0092109000, 0.0134721000, 0.0222631000, 0.0412134000, 0.0810438000", \ - "0.0065361000, 0.0074660000, 0.0093951000, 0.0134945000, 0.0223259000, 0.0408654000, 0.0806014000", \ - "0.0069641000, 0.0078589000, 0.0097922000, 0.0140069000, 0.0226027000, 0.0409754000, 0.0803789000", \ - "0.0083229000, 0.0091343000, 0.0109274000, 0.0148698000, 0.0233991000, 0.0415580000, 0.0809769000"); - } - } - max_capacitance : 0.0467020000; - max_transition : 1.4953670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0538109000, 0.0576053000, 0.0653024000, 0.0810840000, 0.1126344000, 0.1770830000, 0.3116990000", \ - "0.0583823000, 0.0621402000, 0.0698918000, 0.0855500000, 0.1171029000, 0.1816594000, 0.3162323000", \ - "0.0682308000, 0.0720569000, 0.0797590000, 0.0954614000, 0.1271055000, 0.1915832000, 0.3260724000", \ - "0.0884653000, 0.0922636000, 0.1001788000, 0.1157430000, 0.1472645000, 0.2119728000, 0.3465448000", \ - "0.1216454000, 0.1266948000, 0.1363459000, 0.1555051000, 0.1909282000, 0.2576373000, 0.3925764000", \ - "0.1624402000, 0.1699913000, 0.1847187000, 0.2123873000, 0.2615770000, 0.3462331000, 0.4971355000", \ - "0.1907046000, 0.2021781000, 0.2248869000, 0.2683492000, 0.3446144000, 0.4729305000, 0.6770763000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1972416000, 0.2096483000, 0.2356759000, 0.2923043000, 0.4098045000, 0.6601927000, 1.1910628000", \ - "0.2019882000, 0.2138734000, 0.2411363000, 0.2971040000, 0.4157067000, 0.6656225000, 1.1967581000", \ - "0.2130040000, 0.2252161000, 0.2528381000, 0.3088017000, 0.4272094000, 0.6779989000, 1.2096175000", \ - "0.2382785000, 0.2508334000, 0.2768954000, 0.3333758000, 0.4528401000, 0.7039640000, 1.2352159000", \ - "0.2901737000, 0.3032068000, 0.3291843000, 0.3852666000, 0.5041222000, 0.7555893000, 1.2879194000", \ - "0.3899679000, 0.4038339000, 0.4339893000, 0.4947869000, 0.6162316000, 0.8670129000, 1.3989955000", \ - "0.5560324000, 0.5749519000, 0.6124687000, 0.6900009000, 0.8380663000, 1.1161817000, 1.6530274000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0403907000, 0.0448204000, 0.0541180000, 0.0734485000, 0.1130485000, 0.1973208000, 0.3758228000", \ - "0.0402497000, 0.0447659000, 0.0539055000, 0.0730389000, 0.1131746000, 0.1970695000, 0.3771305000", \ - "0.0398497000, 0.0442789000, 0.0536046000, 0.0729094000, 0.1130184000, 0.1969194000, 0.3771408000", \ - "0.0436019000, 0.0477365000, 0.0559859000, 0.0741354000, 0.1131557000, 0.1968140000, 0.3760735000", \ - "0.0603743000, 0.0647145000, 0.0731888000, 0.0906355000, 0.1258509000, 0.2026668000, 0.3763891000", \ - "0.0968739000, 0.1022712000, 0.1130148000, 0.1338932000, 0.1738053000, 0.2475359000, 0.4019818000", \ - "0.1658123000, 0.1738356000, 0.1894608000, 0.2184402000, 0.2710646000, 0.3628520000, 0.5219934000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1466796000, 0.1633888000, 0.1987422000, 0.2733142000, 0.4312903000, 0.7652372000, 1.4792199000", \ - "0.1468112000, 0.1635241000, 0.1990465000, 0.2732478000, 0.4313201000, 0.7656195000, 1.4753609000", \ - "0.1468311000, 0.1634965000, 0.1990168000, 0.2732713000, 0.4313275000, 0.7658119000, 1.4756499000", \ - "0.1471518000, 0.1634408000, 0.1987653000, 0.2731367000, 0.4312193000, 0.7674066000, 1.4759463000", \ - "0.1500814000, 0.1663698000, 0.2006531000, 0.2739014000, 0.4317805000, 0.7659793000, 1.4769083000", \ - "0.1786760000, 0.1946168000, 0.2286013000, 0.2957587000, 0.4441111000, 0.7682570000, 1.4802926000", \ - "0.2478659000, 0.2648734000, 0.3005739000, 0.3752888000, 0.5245928000, 0.8226186000, 1.4953674000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0516973000, 0.0552033000, 0.0621879000, 0.0769335000, 0.1069121000, 0.1698477000, 0.3023958000", \ - "0.0563944000, 0.0599037000, 0.0670130000, 0.0818184000, 0.1117864000, 0.1747469000, 0.3071822000", \ - "0.0660649000, 0.0695988000, 0.0768121000, 0.0914847000, 0.1216357000, 0.1845838000, 0.3170711000", \ - "0.0846826000, 0.0883204000, 0.0959413000, 0.1109813000, 0.1413334000, 0.2042838000, 0.3371161000", \ - "0.1128249000, 0.1179561000, 0.1276397000, 0.1466457000, 0.1825205000, 0.2488186000, 0.3819536000", \ - "0.1430407000, 0.1506581000, 0.1652532000, 0.1940565000, 0.2449431000, 0.3311894000, 0.4830256000", \ - "0.1489490000, 0.1613379000, 0.1858364000, 0.2315740000, 0.3111588000, 0.4426401000, 0.6506600000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1874816000, 0.1992541000, 0.2264144000, 0.2822782000, 0.4007314000, 0.6504023000, 1.1814510000", \ - "0.1908816000, 0.2032532000, 0.2304157000, 0.2862248000, 0.4044114000, 0.6550428000, 1.1869883000", \ - "0.2004933000, 0.2142569000, 0.2409390000, 0.2970945000, 0.4163769000, 0.6668779000, 1.1995341000", \ - "0.2280714000, 0.2393673000, 0.2674009000, 0.3236254000, 0.4426687000, 0.6935855000, 1.2258482000", \ - "0.2877323000, 0.3000775000, 0.3266871000, 0.3827855000, 0.5016565000, 0.7531145000, 1.2854928000", \ - "0.4101270000, 0.4251943000, 0.4561261000, 0.5187469000, 0.6408560000, 0.8919959000, 1.4246739000", \ - "0.6206513000, 0.6427830000, 0.6868859000, 0.7719650000, 0.9267994000, 1.2119046000, 1.7490075000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0340895000, 0.0382365000, 0.0471218000, 0.0659649000, 0.1052312000, 0.1886529000, 0.3660441000", \ - "0.0341214000, 0.0382274000, 0.0471681000, 0.0659393000, 0.1053488000, 0.1892158000, 0.3669085000", \ - "0.0339650000, 0.0382388000, 0.0469718000, 0.0657874000, 0.1051641000, 0.1892494000, 0.3673678000", \ - "0.0382911000, 0.0422307000, 0.0501613000, 0.0675236000, 0.1059497000, 0.1889019000, 0.3678426000", \ - "0.0546018000, 0.0588986000, 0.0673935000, 0.0854009000, 0.1202354000, 0.1956297000, 0.3678528000", \ - "0.0906221000, 0.0961918000, 0.1074623000, 0.1285369000, 0.1675235000, 0.2418338000, 0.3958574000", \ - "0.1592055000, 0.1672412000, 0.1840283000, 0.2131141000, 0.2667812000, 0.3580654000, 0.5167683000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1468242000, 0.1635195000, 0.1990355000, 0.2732429000, 0.4312059000, 0.7656724000, 1.4749378000", \ - "0.1468541000, 0.1635154000, 0.1987564000, 0.2732786000, 0.4311517000, 0.7656671000, 1.4793374000", \ - "0.1477751000, 0.1637274000, 0.1986278000, 0.2730994000, 0.4310806000, 0.7658744000, 1.4767386000", \ - "0.1466698000, 0.1634225000, 0.1989804000, 0.2732351000, 0.4307661000, 0.7659355000, 1.4747961000", \ - "0.1521587000, 0.1682257000, 0.2018275000, 0.2735607000, 0.4310813000, 0.7681442000, 1.4765789000", \ - "0.1926501000, 0.2083062000, 0.2386122000, 0.3030482000, 0.4464000000, 0.7683175000, 1.4769687000", \ - "0.2873352000, 0.3036861000, 0.3391478000, 0.4110740000, 0.5481087000, 0.8307390000, 1.4909177000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0414762000, 0.0447294000, 0.0514278000, 0.0652017000, 0.0938448000, 0.1539170000, 0.2810837000", \ - "0.0463950000, 0.0496171000, 0.0563712000, 0.0702430000, 0.0989404000, 0.1590094000, 0.2861909000", \ - "0.0561693000, 0.0594180000, 0.0662259000, 0.0802082000, 0.1090396000, 0.1692997000, 0.2964023000", \ - "0.0733510000, 0.0773542000, 0.0849391000, 0.0999434000, 0.1291735000, 0.1896539000, 0.3170701000", \ - "0.0958582000, 0.1014303000, 0.1125890000, 0.1327972000, 0.1693633000, 0.2352046000, 0.3631861000", \ - "0.1141572000, 0.1226313000, 0.1403848000, 0.1718634000, 0.2261881000, 0.3148938000, 0.4645409000", \ - "0.0993982000, 0.1134017000, 0.1415842000, 0.1929734000, 0.2798097000, 0.4174044000, 0.6289993000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1512079000, 0.1641465000, 0.1905577000, 0.2459152000, 0.3648797000, 0.6153415000, 1.1473881000", \ - "0.1533082000, 0.1660261000, 0.1934253000, 0.2492810000, 0.3682589000, 0.6187411000, 1.1501823000", \ - "0.1617942000, 0.1742261000, 0.2016051000, 0.2578868000, 0.3774282000, 0.6290679000, 1.1612296000", \ - "0.1870891000, 0.2000238000, 0.2263571000, 0.2828452000, 0.4017257000, 0.6538750000, 1.1863918000", \ - "0.2520611000, 0.2640748000, 0.2900720000, 0.3449202000, 0.4638558000, 0.7144905000, 1.2466679000", \ - "0.3885757000, 0.4049485000, 0.4374330000, 0.4984732000, 0.6170560000, 0.8659994000, 1.3981528000", \ - "0.6117539000, 0.6358692000, 0.6847606000, 0.7753008000, 0.9394420000, 1.2213117000, 1.7419314000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0260411000, 0.0299142000, 0.0383069000, 0.0560135000, 0.0936054000, 0.1738212000, 0.3443511000", \ - "0.0259986000, 0.0299554000, 0.0382678000, 0.0560730000, 0.0938371000, 0.1737570000, 0.3442829000", \ - "0.0262185000, 0.0299707000, 0.0382759000, 0.0559929000, 0.0936892000, 0.1744132000, 0.3445203000", \ - "0.0325296000, 0.0359339000, 0.0434622000, 0.0592038000, 0.0949626000, 0.1740133000, 0.3454461000", \ - "0.0500503000, 0.0542616000, 0.0625156000, 0.0793322000, 0.1121242000, 0.1827288000, 0.3460488000", \ - "0.0859658000, 0.0919693000, 0.1029657000, 0.1242979000, 0.1627896000, 0.2340096000, 0.3769582000", \ - "0.1546712000, 0.1628623000, 0.1799564000, 0.2100152000, 0.2625221000, 0.3515733000, 0.5047988000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.1472939000, 0.1637350000, 0.1985821000, 0.2731971000, 0.4311095000, 0.7660078000, 1.4803831000", \ - "0.1467491000, 0.1639087000, 0.1986858000, 0.2733030000, 0.4308303000, 0.7656862000, 1.4778877000", \ - "0.1469442000, 0.1633849000, 0.1989392000, 0.2733086000, 0.4308443000, 0.7655554000, 1.4769365000", \ - "0.1460724000, 0.1628990000, 0.1987513000, 0.2731753000, 0.4312823000, 0.7652844000, 1.4798445000", \ - "0.1550737000, 0.1701640000, 0.2026594000, 0.2731603000, 0.4314250000, 0.7672991000, 1.4755538000", \ - "0.2095283000, 0.2258365000, 0.2574614000, 0.3161848000, 0.4513519000, 0.7688647000, 1.4818906000", \ - "0.3103705000, 0.3328575000, 0.3772841000, 0.4539692000, 0.5940025000, 0.8617571000, 1.4913855000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0442872000, 0.0480575000, 0.0558134000, 0.0714008000, 0.1030495000, 0.1675757000, 0.3021060000", \ - "0.0484178000, 0.0522342000, 0.0599690000, 0.0755880000, 0.1071075000, 0.1718908000, 0.3064394000", \ - "0.0587696000, 0.0625081000, 0.0702099000, 0.0858719000, 0.1174351000, 0.1820496000, 0.3167544000", \ - "0.0838553000, 0.0879281000, 0.0958214000, 0.1110005000, 0.1418575000, 0.2065025000, 0.3406365000", \ - "0.1195662000, 0.1254878000, 0.1371429000, 0.1590771000, 0.1972271000, 0.2637835000, 0.3965862000", \ - "0.1593606000, 0.1681873000, 0.1856312000, 0.2193222000, 0.2772135000, 0.3734314000, 0.5301776000", \ - "0.1871083000, 0.2002678000, 0.2264771000, 0.2773252000, 0.3667753000, 0.5161541000, 0.7536715000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0686993000, 0.0769148000, 0.0942763000, 0.1300568000, 0.2047140000, 0.3642871000, 0.7002273000", \ - "0.0730582000, 0.0814986000, 0.0989361000, 0.1351254000, 0.2119405000, 0.3694003000, 0.7075689000", \ - "0.0846161000, 0.0928454000, 0.1102181000, 0.1466070000, 0.2230101000, 0.3822705000, 0.7218282000", \ - "0.1102529000, 0.1184048000, 0.1354817000, 0.1715199000, 0.2473676000, 0.4088113000, 0.7457089000", \ - "0.1556831000, 0.1664972000, 0.1883110000, 0.2286705000, 0.3052101000, 0.4655426000, 0.8059902000", \ - "0.2281159000, 0.2449605000, 0.2758054000, 0.3333141000, 0.4329116000, 0.5998647000, 0.9387587000", \ - "0.3482098000, 0.3742315000, 0.4213882000, 0.5061294000, 0.6452499000, 0.8712081000, 1.2520818000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0400026000, 0.0445084000, 0.0537568000, 0.0729829000, 0.1127941000, 0.1970600000, 0.3754672000", \ - "0.0399083000, 0.0443614000, 0.0536579000, 0.0729701000, 0.1129296000, 0.1967974000, 0.3760629000", \ - "0.0391716000, 0.0435078000, 0.0528132000, 0.0724534000, 0.1128312000, 0.1971369000, 0.3754662000", \ - "0.0483178000, 0.0521387000, 0.0592666000, 0.0758993000, 0.1133907000, 0.1969258000, 0.3754940000", \ - "0.0714955000, 0.0766931000, 0.0868687000, 0.1053701000, 0.1379134000, 0.2084120000, 0.3761424000", \ - "0.1145309000, 0.1223594000, 0.1373651000, 0.1635764000, 0.2089206000, 0.2867786000, 0.4220497000", \ - "0.1869834000, 0.1988963000, 0.2217037000, 0.2635580000, 0.3301356000, 0.4405234000, 0.6108868000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0820968000, 0.0930240000, 0.1160441000, 0.1644009000, 0.2657688000, 0.4809725000, 0.9404265000", \ - "0.0820709000, 0.0930309000, 0.1160485000, 0.1643763000, 0.2660529000, 0.4806679000, 0.9407830000", \ - "0.0821441000, 0.0930185000, 0.1160572000, 0.1643872000, 0.2659949000, 0.4813291000, 0.9381858000", \ - "0.0861944000, 0.0961525000, 0.1175139000, 0.1644922000, 0.2659703000, 0.4813412000, 0.9415468000", \ - "0.1105887000, 0.1186292000, 0.1362028000, 0.1773795000, 0.2703250000, 0.4812163000, 0.9420047000", \ - "0.1648094000, 0.1736015000, 0.1921684000, 0.2325917000, 0.3142465000, 0.5007036000, 0.9399550000", \ - "0.2653663000, 0.2754410000, 0.2982514000, 0.3440913000, 0.4361282000, 0.6140372000, 1.0027759000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0327650000, 0.0365210000, 0.0440447000, 0.0591500000, 0.0891780000, 0.1504503000, 0.2777571000", \ - "0.0370896000, 0.0408226000, 0.0483638000, 0.0634790000, 0.0936662000, 0.1549066000, 0.2824058000", \ - "0.0482794000, 0.0517258000, 0.0589904000, 0.0736283000, 0.1037641000, 0.1651182000, 0.2926766000", \ - "0.0697290000, 0.0742103000, 0.0830500000, 0.0984711000, 0.1280276000, 0.1890414000, 0.3165869000", \ - "0.0954307000, 0.1020500000, 0.1148509000, 0.1382651000, 0.1788771000, 0.2448415000, 0.3718613000", \ - "0.1177991000, 0.1277512000, 0.1471696000, 0.1828799000, 0.2437713000, 0.3440481000, 0.4965859000", \ - "0.1131635000, 0.1282005000, 0.1576691000, 0.2111832000, 0.3063628000, 0.4580747000, 0.6962309000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0555502000, 0.0641155000, 0.0816066000, 0.1180157000, 0.1927641000, 0.3524766000, 0.6884416000", \ - "0.0582424000, 0.0666907000, 0.0845114000, 0.1210455000, 0.1979584000, 0.3563199000, 0.6943864000", \ - "0.0692404000, 0.0774002000, 0.0946598000, 0.1310368000, 0.2080993000, 0.3688500000, 0.7085060000", \ - "0.0981090000, 0.1063896000, 0.1231092000, 0.1590726000, 0.2338663000, 0.3958376000, 0.7355109000", \ - "0.1488020000, 0.1617575000, 0.1854276000, 0.2271003000, 0.3011050000, 0.4597937000, 0.7975913000", \ - "0.2313171000, 0.2514875000, 0.2873733000, 0.3512613000, 0.4545420000, 0.6171752000, 0.9561725000", \ - "0.3751176000, 0.4029364000, 0.4561913000, 0.5518139000, 0.7089003000, 0.9556627000, 1.3268219000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0320921000, 0.0363063000, 0.0450715000, 0.0629790000, 0.1008749000, 0.1809603000, 0.3495221000", \ - "0.0317083000, 0.0360246000, 0.0449556000, 0.0631407000, 0.1011194000, 0.1807937000, 0.3505629000", \ - "0.0321019000, 0.0360729000, 0.0443809000, 0.0622776000, 0.1004718000, 0.1802463000, 0.3496344000", \ - "0.0432168000, 0.0470688000, 0.0547695000, 0.0688053000, 0.1025043000, 0.1805984000, 0.3502459000", \ - "0.0660644000, 0.0713014000, 0.0812659000, 0.1002268000, 0.1310036000, 0.1952920000, 0.3516376000", \ - "0.1075472000, 0.1154722000, 0.1305289000, 0.1567261000, 0.2011357000, 0.2727367000, 0.4049756000", \ - "0.1805364000, 0.1925878000, 0.2156077000, 0.2558641000, 0.3224783000, 0.4328216000, 0.5931330000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010650400, 0.0022686000, 0.0048322800, 0.0102931000, 0.0219250000, 0.0467019000"); - values("0.0820941000, 0.0930124000, 0.1160262000, 0.1644383000, 0.2659122000, 0.4809900000, 0.9406065000", \ - "0.0820307000, 0.0930039000, 0.1160514000, 0.1643447000, 0.2659636000, 0.4812088000, 0.9405722000", \ - "0.0817914000, 0.0928619000, 0.1160209000, 0.1643999000, 0.2659419000, 0.4813894000, 0.9404949000", \ - "0.0906468000, 0.0995211000, 0.1189714000, 0.1644854000, 0.2659010000, 0.4814907000, 0.9399922000", \ - "0.1287834000, 0.1355663000, 0.1499217000, 0.1856137000, 0.2720979000, 0.4812865000, 0.9412476000", \ - "0.1950066000, 0.2052107000, 0.2250202000, 0.2636567000, 0.3352499000, 0.5100148000, 0.9410714000", \ - "0.3039070000, 0.3181693000, 0.3475824000, 0.4050134000, 0.5024801000, 0.6698463000, 1.0188280000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32ai_2") { - leakage_power () { - value : 0.0024581000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0002720000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0025117000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0024794000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0071137000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0019872000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0036694000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0058065000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0059094000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0019872000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0024651000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0046021000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0039442000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0019870000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0004999000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0026370000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0082322000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0019879000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0047879000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0069249000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0041888000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0019869000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0007441000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0028811000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0041693000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0019873000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0007250000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0028621000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0038728000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0019873000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0004292000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0025663000; - when : "A1&A2&A3&B1&!B2"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__o32ai"; - cell_leakage_power : 0.0031457140; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080710000, 0.0080747000, 0.0080833000, 0.0080870000, 0.0080954000, 0.0081148000, 0.0081594000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008062700, -0.008060000, -0.008053900, -0.008048700, -0.008036700, -0.008009100, -0.007945500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046440000; - } - pin ("A2") { - capacitance : 0.0043190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040290000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080025000, 0.0079950000, 0.0079777000, 0.0079804000, 0.0079868000, 0.0080015000, 0.0080354000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007961200, -0.007959400, -0.007955200, -0.007952000, -0.007944600, -0.007927500, -0.007888100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046100000; - } - pin ("A3") { - capacitance : 0.0043800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080373000, 0.0080324000, 0.0080211000, 0.0080221000, 0.0080246000, 0.0080303000, 0.0080434000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008008400, -0.008003400, -0.007991900, -0.007993200, -0.007996100, -0.008002800, -0.008018300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047130000; - } - pin ("B1") { - capacitance : 0.0043800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042140000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093221000, 0.0093239000, 0.0093282000, 0.0093247000, 0.0093167000, 0.0092983000, 0.0092560000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-9.0112541e-05, -0.000125900, -0.000208500, -0.000154400, -2.9819422e-05, 0.0002575000, 0.0009198000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045460000; - } - pin ("B2") { - capacitance : 0.0042410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090935000, 0.0090990000, 0.0091118000, 0.0091079000, 0.0090990000, 0.0090783000, 0.0090308000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("1.9146015e-05, 7.8563398e-06, -1.8161713e-05, 2.7915349e-05, 0.0001341000, 0.0003790000, 0.0009434000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044620000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0175556000, 0.0164652000, 0.0138249000, 0.0076540000, -0.006961300, -0.041778000, -0.124556600", \ - "0.0173055000, 0.0162287000, 0.0135962000, 0.0073997000, -0.007243800, -0.042009400, -0.124790500", \ - "0.0170672000, 0.0159480000, 0.0133573000, 0.0071613000, -0.007461200, -0.042236900, -0.125059000", \ - "0.0168232000, 0.0156769000, 0.0130779000, 0.0068887000, -0.007724300, -0.042401200, -0.125187900", \ - "0.0166202000, 0.0155231000, 0.0129111000, 0.0068195000, -0.007710600, -0.042413100, -0.125179400", \ - "0.0168776000, 0.0157764000, 0.0131375000, 0.0068611000, -0.008039200, -0.042569700, -0.125299000", \ - "0.0185448000, 0.0174066000, 0.0146820000, 0.0083756000, -0.006523800, -0.041817000, -0.124931400"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0353707000, 0.0364877000, 0.0391734000, 0.0454181000, 0.0602466000, 0.0950800000, 0.1773594000", \ - "0.0350492000, 0.0361794000, 0.0388783000, 0.0451609000, 0.0600381000, 0.0949119000, 0.1772284000", \ - "0.0346577000, 0.0357573000, 0.0384725000, 0.0448051000, 0.0597287000, 0.0946977000, 0.1771261000", \ - "0.0342725000, 0.0354453000, 0.0380699000, 0.0444059000, 0.0593388000, 0.0944184000, 0.1766787000", \ - "0.0339793000, 0.0351202000, 0.0377416000, 0.0440441000, 0.0589739000, 0.0940018000, 0.1763440000", \ - "0.0338955000, 0.0350350000, 0.0376594000, 0.0439547000, 0.0587275000, 0.0937417000, 0.1762570000", \ - "0.0336607000, 0.0347467000, 0.0373547000, 0.0441797000, 0.0591506000, 0.0939536000, 0.1760160000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0149282000, 0.0138724000, 0.0112594000, 0.0051149000, -0.009511700, -0.044387800, -0.127300000", \ - "0.0148860000, 0.0137994000, 0.0111948000, 0.0050670000, -0.009565500, -0.044490400, -0.127330200", \ - "0.0146834000, 0.0135996000, 0.0110169000, 0.0049140000, -0.009676900, -0.044497900, -0.127429400", \ - "0.0143172000, 0.0132553000, 0.0106763000, 0.0045810000, -0.009958400, -0.044722400, -0.127494700", \ - "0.0138575000, 0.0128266000, 0.0102497000, 0.0041678000, -0.010178600, -0.044801900, -0.127559100", \ - "0.0140281000, 0.0129512000, 0.0103525000, 0.0041179000, -0.010523000, -0.045263400, -0.127905100", \ - "0.0151972000, 0.0141486000, 0.0113930000, 0.0051649000, -0.009685500, -0.044814800, -0.127978100"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0306805000, 0.0318172000, 0.0345840000, 0.0407619000, 0.0555517000, 0.0904611000, 0.1726422000", \ - "0.0303802000, 0.0315632000, 0.0342053000, 0.0405129000, 0.0553849000, 0.0902169000, 0.1725003000", \ - "0.0298902000, 0.0310450000, 0.0338305000, 0.0401115000, 0.0550331000, 0.0900375000, 0.1723727000", \ - "0.0295431000, 0.0306509000, 0.0333353000, 0.0396916000, 0.0546197000, 0.0897171000, 0.1722763000", \ - "0.0292589000, 0.0303627000, 0.0330192000, 0.0393196000, 0.0541736000, 0.0892577000, 0.1717835000", \ - "0.0291531000, 0.0302608000, 0.0329638000, 0.0392861000, 0.0542041000, 0.0890906000, 0.1715070000", \ - "0.0299552000, 0.0309947000, 0.0335675000, 0.0397636000, 0.0544513000, 0.0892751000, 0.1719202000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0107905000, 0.0097229000, 0.0071680000, 0.0010810000, -0.013543900, -0.048452300, -0.131477200", \ - "0.0107445000, 0.0097007000, 0.0071635000, 0.0011255000, -0.013443100, -0.048281400, -0.131278800", \ - "0.0106197000, 0.0095799000, 0.0070758000, 0.0010804000, -0.013385200, -0.048158600, -0.131131900", \ - "0.0102391000, 0.0092200000, 0.0067580000, 0.0008186000, -0.013567700, -0.048237600, -0.131057300", \ - "0.0099021000, 0.0088473000, 0.0063069000, 0.0003451000, -0.013972200, -0.048440800, -0.131094600", \ - "0.0100372000, 0.0089236000, 0.0063201000, 0.0001880000, -0.014330900, -0.049036400, -0.131492900", \ - "0.0114896000, 0.0103224000, 0.0075902000, 0.0012590000, -0.013687200, -0.048675100, -0.131677700"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0261873000, 0.0272398000, 0.0299319000, 0.0363362000, 0.0510740000, 0.0859209000, 0.1682567000", \ - "0.0256059000, 0.0268420000, 0.0294174000, 0.0358195000, 0.0507620000, 0.0857339000, 0.1681603000", \ - "0.0250470000, 0.0261556000, 0.0289782000, 0.0353403000, 0.0503634000, 0.0854672000, 0.1678893000", \ - "0.0245635000, 0.0256618000, 0.0282678000, 0.0346592000, 0.0497173000, 0.0850106000, 0.1675389000", \ - "0.0244135000, 0.0255507000, 0.0281880000, 0.0344938000, 0.0493378000, 0.0844489000, 0.1671472000", \ - "0.0253456000, 0.0264966000, 0.0290469000, 0.0351430000, 0.0498122000, 0.0845554000, 0.1668986000", \ - "0.0289201000, 0.0299704000, 0.0324765000, 0.0384541000, 0.0533043000, 0.0872556000, 0.1675651000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0101647000, 0.0090929000, 0.0064631000, 0.0002802000, -0.014343100, -0.049143600, -0.131939900", \ - "0.0099520000, 0.0088442000, 0.0062370000, 0.0001009000, -0.014520800, -0.049250200, -0.132061700", \ - "0.0096867000, 0.0086160000, 0.0059649000, -0.000148500, -0.014703500, -0.049363300, -0.132127700", \ - "0.0093064000, 0.0082743000, 0.0056897000, -0.000480100, -0.015065200, -0.049640100, -0.132344100", \ - "0.0089545000, 0.0078604000, 0.0052802000, -0.000850200, -0.015296000, -0.049940400, -0.132621800", \ - "0.0096956000, 0.0085514000, 0.0058718000, -0.000479900, -0.015414000, -0.049999500, -0.132675500", \ - "0.0116525000, 0.0105093000, 0.0077828000, 0.0013185000, -0.013894000, -0.049387500, -0.132988000"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0176272000, 0.0188335000, 0.0216127000, 0.0280402000, 0.0428861000, 0.0776291000, 0.1596897000", \ - "0.0171928000, 0.0184074000, 0.0212231000, 0.0277481000, 0.0427734000, 0.0776519000, 0.1597299000", \ - "0.0167521000, 0.0179232000, 0.0207034000, 0.0272209000, 0.0423810000, 0.0774004000, 0.1597470000", \ - "0.0164714000, 0.0176235000, 0.0203466000, 0.0267289000, 0.0417434000, 0.0769060000, 0.1593820000", \ - "0.0162425000, 0.0173516000, 0.0200185000, 0.0263235000, 0.0411980000, 0.0762654000, 0.1588414000", \ - "0.0163042000, 0.0174255000, 0.0200599000, 0.0263102000, 0.0412714000, 0.0760642000, 0.1582830000", \ - "0.0174624000, 0.0184669000, 0.0209009000, 0.0270052000, 0.0417807000, 0.0764279000, 0.1588331000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0058057000, 0.0047498000, 0.0022041000, -0.003880100, -0.018436700, -0.053193000, -0.136072700", \ - "0.0057789000, 0.0047168000, 0.0021757000, -0.003879200, -0.018331600, -0.053033500, -0.135901200", \ - "0.0056711000, 0.0045982000, 0.0021058000, -0.003941300, -0.018371900, -0.052970000, -0.135756400", \ - "0.0053537000, 0.0043114000, 0.0017936000, -0.004229600, -0.018627200, -0.053151100, -0.135844800", \ - "0.0049723000, 0.0038932000, 0.0013384000, -0.004587100, -0.019063100, -0.053518600, -0.136087400", \ - "0.0057215000, 0.0046263000, 0.0019783000, -0.004162900, -0.019178100, -0.053853700, -0.136398400", \ - "0.0077095000, 0.0065161000, 0.0037007000, -0.002748300, -0.017975600, -0.053303800, -0.136810800"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011854690, 0.0028106750, 0.0066639370, 0.0157997900, 0.0374603200, 0.0888161200"); - values("0.0128974000, 0.0141082000, 0.0169733000, 0.0233893000, 0.0382486000, 0.0730029000, 0.1550816000", \ - "0.0124200000, 0.0136839000, 0.0165416000, 0.0230607000, 0.0380746000, 0.0730005000, 0.1551771000", \ - "0.0119662000, 0.0131884000, 0.0160236000, 0.0225273000, 0.0377133000, 0.0727887000, 0.1550110000", \ - "0.0117968000, 0.0129341000, 0.0156899000, 0.0220016000, 0.0368663000, 0.0722207000, 0.1548085000", \ - "0.0120271000, 0.0131170000, 0.0156877000, 0.0218907000, 0.0367649000, 0.0716865000, 0.1543265000", \ - "0.0132848000, 0.0144289000, 0.0169898000, 0.0231385000, 0.0376631000, 0.0723071000, 0.1534760000", \ - "0.0163585000, 0.0175186000, 0.0206395000, 0.0272360000, 0.0398606000, 0.0738832000, 0.1554470000"); - } - } - max_capacitance : 0.0888160000; - max_transition : 1.5036780000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0579209000, 0.0605207000, 0.0663983000, 0.0796808000, 0.1090406000, 0.1742093000, 0.3245043000", \ - "0.0624201000, 0.0650245000, 0.0707955000, 0.0840452000, 0.1133130000, 0.1787593000, 0.3290118000", \ - "0.0724721000, 0.0749726000, 0.0809908000, 0.0941939000, 0.1233430000, 0.1887263000, 0.3389052000", \ - "0.0930924000, 0.0956821000, 0.1014706000, 0.1146570000, 0.1437337000, 0.2092742000, 0.3593822000", \ - "0.1269291000, 0.1302023000, 0.1372454000, 0.1536077000, 0.1864613000, 0.2547885000, 0.4054192000", \ - "0.1689030000, 0.1736451000, 0.1843192000, 0.2072597000, 0.2540339000, 0.3423246000, 0.5090893000", \ - "0.1967965000, 0.2041611000, 0.2208250000, 0.2571114000, 0.3281702000, 0.4616165000, 0.6917411000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.2058191000, 0.2138787000, 0.2324187000, 0.2766084000, 0.3794044000, 0.6214661000, 1.1926288000", \ - "0.2098449000, 0.2179033000, 0.2357504000, 0.2810420000, 0.3841150000, 0.6264941000, 1.1978628000", \ - "0.2201870000, 0.2282875000, 0.2467037000, 0.2917296000, 0.3949313000, 0.6384186000, 1.2107322000", \ - "0.2431054000, 0.2507242000, 0.2689666000, 0.3139662000, 0.4181753000, 0.6621344000, 1.2352626000", \ - "0.2904506000, 0.2989582000, 0.3172028000, 0.3612957000, 0.4649275000, 0.7087130000, 1.2827183000", \ - "0.3797740000, 0.3892671000, 0.4101400000, 0.4590228000, 0.5676623000, 0.8099899000, 1.3830657000", \ - "0.5271749000, 0.5385070000, 0.5645679000, 0.6269955000, 0.7572855000, 1.0312291000, 1.6128802000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0441957000, 0.0470816000, 0.0538724000, 0.0696362000, 0.1062325000, 0.1914866000, 0.3936851000", \ - "0.0439635000, 0.0468356000, 0.0537553000, 0.0696082000, 0.1061320000, 0.1913364000, 0.3934149000", \ - "0.0435783000, 0.0465157000, 0.0532994000, 0.0692794000, 0.1060132000, 0.1914652000, 0.3939852000", \ - "0.0469699000, 0.0492182000, 0.0556867000, 0.0705397000, 0.1062075000, 0.1910025000, 0.3930854000", \ - "0.0634911000, 0.0662613000, 0.0725375000, 0.0873488000, 0.1199593000, 0.1973209000, 0.3938388000", \ - "0.1005663000, 0.1041596000, 0.1123105000, 0.1298603000, 0.1662317000, 0.2440841000, 0.4179415000", \ - "0.1708718000, 0.1763039000, 0.1881110000, 0.2125137000, 0.2619301000, 0.3568485000, 0.5413164000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1451592000, 0.1558459000, 0.1811461000, 0.2406907000, 0.3794608000, 0.7074148000, 1.4841014000", \ - "0.1451427000, 0.1558354000, 0.1811939000, 0.2406764000, 0.3794929000, 0.7074277000, 1.4806799000", \ - "0.1455285000, 0.1557554000, 0.1811587000, 0.2407285000, 0.3797618000, 0.7086285000, 1.4850299000", \ - "0.1456801000, 0.1563209000, 0.1811967000, 0.2404004000, 0.3795927000, 0.7079847000, 1.4822422000", \ - "0.1488353000, 0.1590382000, 0.1831668000, 0.2410997000, 0.3801774000, 0.7071415000, 1.4825832000", \ - "0.1753953000, 0.1853839000, 0.2102599000, 0.2665113000, 0.3952903000, 0.7122836000, 1.4812336000", \ - "0.2382596000, 0.2499913000, 0.2758603000, 0.3368805000, 0.4720150000, 0.7701202000, 1.5015952000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0550462000, 0.0575101000, 0.0629061000, 0.0751693000, 0.1027987000, 0.1656682000, 0.3129107000", \ - "0.0599136000, 0.0622178000, 0.0675532000, 0.0797482000, 0.1074282000, 0.1706120000, 0.3179322000", \ - "0.0696677000, 0.0721126000, 0.0774552000, 0.0897460000, 0.1175050000, 0.1805666000, 0.3277990000", \ - "0.0889880000, 0.0915671000, 0.0970465000, 0.1098133000, 0.1375925000, 0.2009915000, 0.3482615000", \ - "0.1180717000, 0.1215400000, 0.1291192000, 0.1446131000, 0.1781632000, 0.2459430000, 0.3938147000", \ - "0.1481543000, 0.1539068000, 0.1651009000, 0.1888670000, 0.2375830000, 0.3275968000, 0.4949619000", \ - "0.1534058000, 0.1620623000, 0.1801234000, 0.2181489000, 0.2938577000, 0.4316277000, 0.6667967000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1935449000, 0.2010887000, 0.2195426000, 0.2641996000, 0.3674640000, 0.6089758000, 1.1827611000", \ - "0.1963701000, 0.2044163000, 0.2228590000, 0.2678485000, 0.3706538000, 0.6133603000, 1.1846345000", \ - "0.2060088000, 0.2134735000, 0.2331072000, 0.2772234000, 0.3818593000, 0.6243270000, 1.1964219000", \ - "0.2312830000, 0.2391492000, 0.2583176000, 0.3019937000, 0.4063438000, 0.6504325000, 1.2228737000", \ - "0.2887635000, 0.2963680000, 0.3156881000, 0.3600126000, 0.4637819000, 0.7071314000, 1.2802044000", \ - "0.4044587000, 0.4131027000, 0.4388628000, 0.4888697000, 0.5985336000, 0.8415341000, 1.4143083000", \ - "0.6036485000, 0.6181229000, 0.6483858000, 0.7191132000, 0.8620733000, 1.1455970000, 1.7288518000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0364411000, 0.0391314000, 0.0456842000, 0.0606795000, 0.0964486000, 0.1809716000, 0.3812323000", \ - "0.0364003000, 0.0391632000, 0.0455858000, 0.0608035000, 0.0964300000, 0.1809641000, 0.3809133000", \ - "0.0362616000, 0.0389845000, 0.0454889000, 0.0606862000, 0.0963597000, 0.1809541000, 0.3815364000", \ - "0.0404091000, 0.0428603000, 0.0485622000, 0.0626833000, 0.0972440000, 0.1809323000, 0.3811146000", \ - "0.0570822000, 0.0601221000, 0.0661570000, 0.0803940000, 0.1127517000, 0.1881949000, 0.3814092000", \ - "0.0939219000, 0.0975764000, 0.1059970000, 0.1238814000, 0.1612679000, 0.2371829000, 0.4084393000", \ - "0.1629307000, 0.1689002000, 0.1811413000, 0.2078444000, 0.2586388000, 0.3547824000, 0.5357882000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1452180000, 0.1558759000, 0.1817354000, 0.2403480000, 0.3797925000, 0.7071651000, 1.4844087000", \ - "0.1451900000, 0.1559586000, 0.1811187000, 0.2405220000, 0.3796442000, 0.7072711000, 1.4795658000", \ - "0.1452473000, 0.1559147000, 0.1817372000, 0.2404029000, 0.3797261000, 0.7080542000, 1.4794967000", \ - "0.1457046000, 0.1559084000, 0.1808827000, 0.2404533000, 0.3794703000, 0.7094721000, 1.4803225000", \ - "0.1507360000, 0.1610701000, 0.1852912000, 0.2417217000, 0.3794663000, 0.7092893000, 1.4808307000", \ - "0.1901554000, 0.2000985000, 0.2247899000, 0.2758044000, 0.3998603000, 0.7102966000, 1.4820203000", \ - "0.2843141000, 0.2949490000, 0.3248709000, 0.3832450000, 0.5065246000, 0.7816788000, 1.4984647000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0438180000, 0.0460024000, 0.0511334000, 0.0626763000, 0.0886912000, 0.1486091000, 0.2887418000", \ - "0.0485392000, 0.0508564000, 0.0558946000, 0.0674951000, 0.0936854000, 0.1535862000, 0.2938416000", \ - "0.0588480000, 0.0611040000, 0.0662653000, 0.0779352000, 0.1041707000, 0.1643777000, 0.3048267000", \ - "0.0769857000, 0.0797384000, 0.0858398000, 0.0983433000, 0.1251426000, 0.1856147000, 0.3262003000", \ - "0.1005768000, 0.1045004000, 0.1125492000, 0.1307082000, 0.1655531000, 0.2325896000, 0.3742096000", \ - "0.1185250000, 0.1245778000, 0.1382419000, 0.1651141000, 0.2185565000, 0.3123456000, 0.4788583000", \ - "0.1034541000, 0.1128798000, 0.1335173000, 0.1781010000, 0.2617938000, 0.4087581000, 0.6505937000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1521016000, 0.1602907000, 0.1792868000, 0.2234256000, 0.3261343000, 0.5687013000, 1.1400431000", \ - "0.1537296000, 0.1606596000, 0.1795575000, 0.2254667000, 0.3290726000, 0.5720296000, 1.1437672000", \ - "0.1608949000, 0.1683352000, 0.1874974000, 0.2334589000, 0.3381083000, 0.5816562000, 1.1539176000", \ - "0.1843427000, 0.1921174000, 0.2105943000, 0.2549501000, 0.3601061000, 0.6045097000, 1.1791776000", \ - "0.2476499000, 0.2554728000, 0.2735221000, 0.3176119000, 0.4210572000, 0.6646513000, 1.2381073000", \ - "0.3776540000, 0.3866410000, 0.4110565000, 0.4622962000, 0.5679508000, 0.8075962000, 1.3792036000", \ - "0.5875612000, 0.6026465000, 0.6368900000, 0.7105381000, 0.8638342000, 1.1475838000, 1.7055957000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0269788000, 0.0295920000, 0.0355803000, 0.0498481000, 0.0835229000, 0.1638516000, 0.3540893000", \ - "0.0270682000, 0.0295846000, 0.0355455000, 0.0498256000, 0.0836619000, 0.1637902000, 0.3540691000", \ - "0.0270251000, 0.0295578000, 0.0355273000, 0.0497879000, 0.0834464000, 0.1639107000, 0.3541517000", \ - "0.0335221000, 0.0358223000, 0.0410969000, 0.0534947000, 0.0849475000, 0.1638924000, 0.3548562000", \ - "0.0517370000, 0.0543934000, 0.0606241000, 0.0743537000, 0.1044627000, 0.1737521000, 0.3550784000", \ - "0.0884663000, 0.0923827000, 0.1007334000, 0.1186692000, 0.1557887000, 0.2278510000, 0.3870701000", \ - "0.1572124000, 0.1630075000, 0.1754540000, 0.2027103000, 0.2547819000, 0.3496113000, 0.5246309000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.1454660000, 0.1562471000, 0.1809786000, 0.2408396000, 0.3797182000, 0.7077706000, 1.4805196000", \ - "0.1451071000, 0.1563614000, 0.1811084000, 0.2405605000, 0.3796196000, 0.7088173000, 1.4832683000", \ - "0.1452479000, 0.1556618000, 0.1813780000, 0.2403142000, 0.3794405000, 0.7092761000, 1.4810801000", \ - "0.1438340000, 0.1546228000, 0.1803112000, 0.2403203000, 0.3796026000, 0.7070618000, 1.4819231000", \ - "0.1528373000, 0.1624349000, 0.1851441000, 0.2412708000, 0.3784310000, 0.7074369000, 1.4805950000", \ - "0.2037771000, 0.2183409000, 0.2399712000, 0.2922609000, 0.4075966000, 0.7103655000, 1.4861244000", \ - "0.2944882000, 0.3097232000, 0.3440939000, 0.4136132000, 0.5532216000, 0.8157308000, 1.5036784000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0453293000, 0.0479322000, 0.0537147000, 0.0668852000, 0.0962596000, 0.1616285000, 0.3117425000", \ - "0.0491240000, 0.0516667000, 0.0576174000, 0.0708709000, 0.1000620000, 0.1654284000, 0.3157442000", \ - "0.0590303000, 0.0615732000, 0.0673004000, 0.0804908000, 0.1097973000, 0.1752178000, 0.3255419000", \ - "0.0834229000, 0.0862212000, 0.0922480000, 0.1049202000, 0.1329886000, 0.1987975000, 0.3490183000", \ - "0.1174223000, 0.1213411000, 0.1300795000, 0.1486943000, 0.1844485000, 0.2537384000, 0.4033844000", \ - "0.1517909000, 0.1575972000, 0.1699657000, 0.1975323000, 0.2542600000, 0.3550005000, 0.5301172000", \ - "0.1667605000, 0.1756634000, 0.1953002000, 0.2369974000, 0.3204468000, 0.4748781000, 0.7387715000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0754303000, 0.0814634000, 0.0955142000, 0.1275236000, 0.2015210000, 0.3729951000, 0.7799897000", \ - "0.0793565000, 0.0855017000, 0.0996579000, 0.1321224000, 0.2069267000, 0.3791362000, 0.7878108000", \ - "0.0911242000, 0.0971869000, 0.1111107000, 0.1434589000, 0.2189609000, 0.3933260000, 0.7996260000", \ - "0.1180667000, 0.1240050000, 0.1376558000, 0.1693986000, 0.2436060000, 0.4181922000, 0.8270596000", \ - "0.1649757000, 0.1728614000, 0.1904205000, 0.2269759000, 0.3017659000, 0.4764404000, 0.8859826000", \ - "0.2407006000, 0.2522531000, 0.2772269000, 0.3281857000, 0.4292222000, 0.6120743000, 1.0215955000", \ - "0.3628194000, 0.3823525000, 0.4211390000, 0.4982444000, 0.6425357000, 0.8916654000, 1.3386419000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0437784000, 0.0466341000, 0.0534349000, 0.0691995000, 0.1058900000, 0.1913808000, 0.3936162000", \ - "0.0438143000, 0.0467496000, 0.0535281000, 0.0692421000, 0.1058280000, 0.1912376000, 0.3934891000", \ - "0.0423760000, 0.0452579000, 0.0521855000, 0.0683628000, 0.1056177000, 0.1913345000, 0.3933183000", \ - "0.0502954000, 0.0533728000, 0.0589546000, 0.0723747000, 0.1064775000, 0.1907030000, 0.3935689000", \ - "0.0723854000, 0.0758369000, 0.0836708000, 0.0999381000, 0.1341258000, 0.2032800000, 0.3939639000", \ - "0.1147246000, 0.1200886000, 0.1317230000, 0.1551908000, 0.1995790000, 0.2800153000, 0.4393692000", \ - "0.1876607000, 0.1959219000, 0.2135258000, 0.2490270000, 0.3146302000, 0.4270793000, 0.6253535000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0925819000, 0.1001849000, 0.1183088000, 0.1609473000, 0.2609151000, 0.4963606000, 1.0549088000", \ - "0.0925946000, 0.1002175000, 0.1183288000, 0.1609856000, 0.2609735000, 0.4966659000, 1.0567663000", \ - "0.0926624000, 0.1003019000, 0.1183515000, 0.1609966000, 0.2610695000, 0.4963354000, 1.0546739000", \ - "0.0955323000, 0.1025079000, 0.1194485000, 0.1611523000, 0.2609884000, 0.4965824000, 1.0571486000", \ - "0.1179635000, 0.1235367000, 0.1377780000, 0.1740526000, 0.2653630000, 0.4965290000, 1.0570875000", \ - "0.1721600000, 0.1786010000, 0.1935438000, 0.2283227000, 0.3097481000, 0.5140493000, 1.0570109000", \ - "0.2773993000, 0.2847970000, 0.3011797000, 0.3425735000, 0.4321498000, 0.6299201000, 1.1069605000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0332206000, 0.0360503000, 0.0423974000, 0.0563259000, 0.0866316000, 0.1539169000, 0.3081989000", \ - "0.0376898000, 0.0404760000, 0.0468231000, 0.0606866000, 0.0910454000, 0.1584759000, 0.3129016000", \ - "0.0489667000, 0.0514843000, 0.0574511000, 0.0711406000, 0.1015173000, 0.1688044000, 0.3233408000", \ - "0.0720754000, 0.0752714000, 0.0823793000, 0.0961419000, 0.1256009000, 0.1927846000, 0.3473911000", \ - "0.1007362000, 0.1053775000, 0.1155789000, 0.1363715000, 0.1768124000, 0.2487338000, 0.4027487000", \ - "0.1274574000, 0.1342775000, 0.1493498000, 0.1809443000, 0.2406118000, 0.3501489000, 0.5320194000", \ - "0.1322115000, 0.1423585000, 0.1649538000, 0.2117543000, 0.3050630000, 0.4704196000, 0.7466409000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0508852000, 0.0570185000, 0.0710903000, 0.1030745000, 0.1767741000, 0.3500294000, 0.7560852000", \ - "0.0535951000, 0.0597919000, 0.0741288000, 0.1065444000, 0.1811993000, 0.3559939000, 0.7608573000", \ - "0.0638174000, 0.0696944000, 0.0836954000, 0.1158633000, 0.1910984000, 0.3643249000, 0.7722695000", \ - "0.0914070000, 0.0975767000, 0.1107806000, 0.1419364000, 0.2151989000, 0.3904893000, 0.7997726000", \ - "0.1367376000, 0.1462279000, 0.1662300000, 0.2063287000, 0.2805205000, 0.4524809000, 0.8619941000", \ - "0.2095171000, 0.2239631000, 0.2543041000, 0.3131138000, 0.4204043000, 0.6047722000, 1.0071453000", \ - "0.3385024000, 0.3580298000, 0.3997955000, 0.4860075000, 0.6456924000, 0.9173621000, 1.3583525000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0367070000, 0.0398345000, 0.0467496000, 0.0631933000, 0.1008728000, 0.1888977000, 0.3975161000", \ - "0.0361746000, 0.0394276000, 0.0466853000, 0.0631554000, 0.1007679000, 0.1890081000, 0.3974673000", \ - "0.0360861000, 0.0389995000, 0.0458430000, 0.0620124000, 0.1004984000, 0.1889683000, 0.3976158000", \ - "0.0459615000, 0.0490402000, 0.0551984000, 0.0685649000, 0.1020535000, 0.1884491000, 0.3973036000", \ - "0.0676197000, 0.0717438000, 0.0799991000, 0.0972111000, 0.1294715000, 0.2021752000, 0.3978650000", \ - "0.1086791000, 0.1141433000, 0.1262105000, 0.1506207000, 0.1974051000, 0.2778348000, 0.4432707000", \ - "0.1793995000, 0.1884168000, 0.2072328000, 0.2447772000, 0.3133550000, 0.4297001000, 0.6291334000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011854700, 0.0028106700, 0.0066639400, 0.0157998000, 0.0374603000, 0.0888161000"); - values("0.0929993000, 0.1007717000, 0.1189741000, 0.1617095000, 0.2617188000, 0.4975446000, 1.0552721000", \ - "0.0927266000, 0.1005671000, 0.1189652000, 0.1617395000, 0.2617073000, 0.4976041000, 1.0572276000", \ - "0.0918250000, 0.0996985000, 0.1184910000, 0.1616488000, 0.2617386000, 0.4971409000, 1.0573699000", \ - "0.1022518000, 0.1080036000, 0.1232207000, 0.1620836000, 0.2614692000, 0.4973832000, 1.0550812000", \ - "0.1400700000, 0.1450401000, 0.1559786000, 0.1869691000, 0.2698300000, 0.4970634000, 1.0575887000", \ - "0.2023972000, 0.2098936000, 0.2263550000, 0.2633809000, 0.3375057000, 0.5238013000, 1.0567163000", \ - "0.3093251000, 0.3191740000, 0.3414363000, 0.3921653000, 0.4953092000, 0.6869272000, 1.1314276000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o32ai_4") { - leakage_power () { - value : 0.0053448000; - when : "!A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0005871000; - when : "!A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0054625000; - when : "!A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0053790000; - when : "!A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0082742000; - when : "!A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0045240000; - when : "!A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0044326000; - when : "!A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0068122000; - when : "!A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0068104000; - when : "!A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0045239000; - when : "!A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0029688000; - when : "!A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0053484000; - when : "!A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0044275000; - when : "!A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0045203000; - when : "!A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0005860000; - when : "!A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0029656000; - when : "!A1&A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0085026000; - when : "A1&!A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0045231000; - when : "A1&!A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0046609000; - when : "A1&!A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0070405000; - when : "A1&!A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0046113000; - when : "A1&!A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0045279000; - when : "A1&!A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0007686000; - when : "A1&!A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0031482000; - when : "A1&!A2&A3&B1&!B2"; - } - leakage_power () { - value : 0.0046084000; - when : "A1&A2&!A3&!B1&B2"; - } - leakage_power () { - value : 0.0045240000; - when : "A1&A2&!A3&!B1&!B2"; - } - leakage_power () { - value : 0.0007668000; - when : "A1&A2&!A3&B1&B2"; - } - leakage_power () { - value : 0.0031464000; - when : "A1&A2&!A3&B1&!B2"; - } - leakage_power () { - value : 0.0043299000; - when : "A1&A2&A3&!B1&B2"; - } - leakage_power () { - value : 0.0045187000; - when : "A1&A2&A3&!B1&!B2"; - } - leakage_power () { - value : 0.0004894000; - when : "A1&A2&A3&B1&B2"; - } - leakage_power () { - value : 0.0028679000; - when : "A1&A2&A3&B1&!B2"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__o32ai"; - cell_leakage_power : 0.0042500690; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0086590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158764000, 0.0158631000, 0.0158324000, 0.0158273000, 0.0158156000, 0.0157886000, 0.0157264000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015758400, -0.015753400, -0.015741800, -0.015736900, -0.015725600, -0.015699700, -0.015640000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090620000; - } - pin ("A2") { - capacitance : 0.0082520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155843000, 0.0155750000, 0.0155536000, 0.0155555000, 0.0155599000, 0.0155700000, 0.0155933000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015522600, -0.015518000, -0.015507400, -0.015510500, -0.015517800, -0.015534500, -0.015573000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088020000; - } - pin ("A3") { - capacitance : 0.0084670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157120000, 0.0157042000, 0.0156863000, 0.0156806000, 0.0156676000, 0.0156376000, 0.0155684000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015658300, -0.015656200, -0.015651300, -0.015654200, -0.015660900, -0.015676300, -0.015711700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0091230000; - } - pin ("B1") { - capacitance : 0.0083800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0181881000, 0.0181904000, 0.0181956000, 0.0181893000, 0.0181746000, 0.0181409000, 0.0180631000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001575200, -0.001649800, -0.001821800, -0.001726700, -0.001507400, -0.001002000, 0.0001629000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0086670000; - } - pin ("B2") { - capacitance : 0.0083060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0079060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0182531000, 0.0182485000, 0.0182380000, 0.0182401000, 0.0182452000, 0.0182567000, 0.0182834000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001745800, -0.001800500, -0.001926700, -0.001833700, -0.001619500, -0.001125600, 1.2835066e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0087070000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3) | (!B1&!B2)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0345127000, 0.0332180000, 0.0299230000, 0.0211787000, -0.001287300, -0.059728500, -0.212273800", \ - "0.0340475000, 0.0327624000, 0.0294331000, 0.0207095000, -0.001762300, -0.060183600, -0.212601100", \ - "0.0334474000, 0.0321824000, 0.0288096000, 0.0202009000, -0.002172200, -0.060694500, -0.213201400", \ - "0.0329806000, 0.0317009000, 0.0283812000, 0.0196568000, -0.002789900, -0.061107100, -0.213449500", \ - "0.0326278000, 0.0313450000, 0.0280667000, 0.0195451000, -0.002800400, -0.061151700, -0.213671500", \ - "0.0327239000, 0.0314313000, 0.0281450000, 0.0192910000, -0.003297500, -0.061707500, -0.213980200", \ - "0.0355252000, 0.0342167000, 0.0307949000, 0.0219711000, -0.000976700, -0.060247400, -0.213221300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0669955000, 0.0683560000, 0.0716935000, 0.0804267000, 0.1031608000, 0.1617628000, 0.3133855000", \ - "0.0664714000, 0.0677558000, 0.0711613000, 0.0800131000, 0.1027167000, 0.1614102000, 0.3130823000", \ - "0.0657432000, 0.0672523000, 0.0705277000, 0.0794216000, 0.1022995000, 0.1610793000, 0.3129967000", \ - "0.0652044000, 0.0664741000, 0.0699337000, 0.0789070000, 0.1017333000, 0.1606642000, 0.3127250000", \ - "0.0646385000, 0.0659424000, 0.0693394000, 0.0781185000, 0.1009948000, 0.1598506000, 0.3120094000", \ - "0.0643939000, 0.0657493000, 0.0690244000, 0.0779672000, 0.1005400000, 0.1595654000, 0.3114826000", \ - "0.0637495000, 0.0651534000, 0.0689613000, 0.0783318000, 0.1012411000, 0.1598400000, 0.3117722000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0287912000, 0.0275086000, 0.0242443000, 0.0155855000, -0.006792800, -0.065476400, -0.218131100", \ - "0.0286727000, 0.0273901000, 0.0241349000, 0.0155068000, -0.006892200, -0.065504300, -0.218183400", \ - "0.0283357000, 0.0270633000, 0.0237784000, 0.0151978000, -0.007149200, -0.065612500, -0.218365900", \ - "0.0276879000, 0.0263862000, 0.0231783000, 0.0146488000, -0.007625900, -0.065917600, -0.218548400", \ - "0.0268126000, 0.0255293000, 0.0222788000, 0.0139828000, -0.008177000, -0.066164800, -0.218806600", \ - "0.0269441000, 0.0256660000, 0.0223917000, 0.0137456000, -0.008831300, -0.067128700, -0.219056000", \ - "0.0289944000, 0.0277122000, 0.0242878000, 0.0155648000, -0.007211000, -0.066249600, -0.219259800"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0582765000, 0.0595533000, 0.0629435000, 0.0717570000, 0.0944415000, 0.1530367000, 0.3048388000", \ - "0.0576401000, 0.0590264000, 0.0624278000, 0.0712133000, 0.0940197000, 0.1526860000, 0.3042664000", \ - "0.0567585000, 0.0582696000, 0.0615724000, 0.0704792000, 0.0933686000, 0.1524677000, 0.3040001000", \ - "0.0561413000, 0.0574805000, 0.0607305000, 0.0696624000, 0.0926494000, 0.1516626000, 0.3038533000", \ - "0.0554207000, 0.0567217000, 0.0600729000, 0.0689485000, 0.0918638000, 0.1509370000, 0.3033154000", \ - "0.0554005000, 0.0566524000, 0.0599861000, 0.0690711000, 0.0917371000, 0.1504866000, 0.3026250000", \ - "0.0564215000, 0.0577032000, 0.0609004000, 0.0695175000, 0.0924083000, 0.1506142000, 0.3031254000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0211797000, 0.0199340000, 0.0166707000, 0.0081186000, -0.014277100, -0.072965600, -0.226026700", \ - "0.0211159000, 0.0198925000, 0.0167007000, 0.0082120000, -0.014066800, -0.072638500, -0.225554400", \ - "0.0208599000, 0.0196451000, 0.0165419000, 0.0081136000, -0.014006300, -0.072430200, -0.225264000", \ - "0.0201889000, 0.0189881000, 0.0158913000, 0.0076028000, -0.014356200, -0.072431900, -0.225059200", \ - "0.0193992000, 0.0181967000, 0.0150703000, 0.0066859000, -0.015099100, -0.072877300, -0.225249200", \ - "0.0196325000, 0.0182784000, 0.0149665000, 0.0065702000, -0.015759100, -0.073999800, -0.225778100", \ - "0.0220273000, 0.0207077000, 0.0170610000, 0.0084416000, -0.014564500, -0.073412600, -0.226185900"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0497270000, 0.0510053000, 0.0544311000, 0.0632882000, 0.0860527000, 0.1447346000, 0.2965584000", \ - "0.0487642000, 0.0502832000, 0.0534980000, 0.0624965000, 0.0854266000, 0.1443306000, 0.2958851000", \ - "0.0474610000, 0.0489171000, 0.0523407000, 0.0613211000, 0.0844777000, 0.1437470000, 0.2955945000", \ - "0.0464239000, 0.0478462000, 0.0512086000, 0.0603111000, 0.0834214000, 0.1428023000, 0.2950125000", \ - "0.0462426000, 0.0475865000, 0.0509483000, 0.0597831000, 0.0822104000, 0.1412933000, 0.2943264000", \ - "0.0484784000, 0.0497347000, 0.0531144000, 0.0618488000, 0.0847541000, 0.1415251000, 0.2931228000", \ - "0.0555177000, 0.0566994000, 0.0575593000, 0.0655306000, 0.0887282000, 0.1464065000, 0.2954459000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0211092000, 0.0198347000, 0.0165468000, 0.0078357000, -0.014531800, -0.072964900, -0.225374300", \ - "0.0206560000, 0.0193800000, 0.0161150000, 0.0074390000, -0.014851100, -0.073310700, -0.225806400", \ - "0.0201813000, 0.0189155000, 0.0156170000, 0.0070277000, -0.015290500, -0.073537000, -0.225785300", \ - "0.0193617000, 0.0181131000, 0.0148676000, 0.0062727000, -0.016007300, -0.073962300, -0.226249800", \ - "0.0191386000, 0.0178138000, 0.0145117000, 0.0059267000, -0.016294100, -0.074462400, -0.226464800", \ - "0.0195343000, 0.0182555000, 0.0149117000, 0.0061696000, -0.017090500, -0.075255300, -0.227103400", \ - "0.0232009000, 0.0218666000, 0.0184166000, 0.0096408000, -0.012765000, -0.073041800, -0.227086300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0338398000, 0.0352719000, 0.0389025000, 0.0480205000, 0.0708695000, 0.1293188000, 0.2805288000", \ - "0.0330024000, 0.0344561000, 0.0381976000, 0.0474325000, 0.0705962000, 0.1293385000, 0.2807274000", \ - "0.0321223000, 0.0335228000, 0.0371309000, 0.0464148000, 0.0697904000, 0.1289245000, 0.2806819000", \ - "0.0315209000, 0.0328141000, 0.0363395000, 0.0453770000, 0.0686000000, 0.1280875000, 0.2801807000", \ - "0.0309993000, 0.0322921000, 0.0357728000, 0.0446467000, 0.0674833000, 0.1266598000, 0.2791466000", \ - "0.0310422000, 0.0323306000, 0.0356698000, 0.0444801000, 0.0673438000, 0.1262063000, 0.2779546000", \ - "0.0327379000, 0.0339212000, 0.0370094000, 0.0456964000, 0.0684069000, 0.1264110000, 0.2791932000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0138108000, 0.0126137000, 0.0093994000, 0.0009592000, -0.021275000, -0.079549100, -0.232181700", \ - "0.0137279000, 0.0125367000, 0.0093447000, 0.0009344000, -0.021107200, -0.079233000, -0.231711600", \ - "0.0136163000, 0.0123802000, 0.0092261000, 0.0008310000, -0.021168400, -0.079086800, -0.231401500", \ - "0.0131038000, 0.0118807000, 0.0086542000, 0.0002614000, -0.021700300, -0.079481300, -0.231576400", \ - "0.0126518000, 0.0113822000, 0.0081042000, -0.000453400, -0.022231800, -0.080295200, -0.232144100", \ - "0.0126887000, 0.0114097000, 0.0080678000, -0.000485500, -0.023000700, -0.081051600, -0.233131600", \ - "0.0160245000, 0.0147179000, 0.0111707000, 0.0023248000, -0.020950800, -0.079379600, -0.233327000"); - } - related_pin : "B2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0245711000, 0.0260838000, 0.0298386000, 0.0390683000, 0.0621262000, 0.1205688000, 0.2718514000", \ - "0.0235387000, 0.0250230000, 0.0287955000, 0.0382725000, 0.0616512000, 0.1205787000, 0.2720410000", \ - "0.0226046000, 0.0240320000, 0.0277634000, 0.0370238000, 0.0606010000, 0.1202232000, 0.2719009000", \ - "0.0221033000, 0.0234601000, 0.0269762000, 0.0361319000, 0.0594441000, 0.1189266000, 0.2714005000", \ - "0.0223061000, 0.0236307000, 0.0269500000, 0.0356090000, 0.0586531000, 0.1176695000, 0.2702767000", \ - "0.0245330000, 0.0257698000, 0.0290019000, 0.0376949000, 0.0597971000, 0.1187747000, 0.2688978000", \ - "0.0307565000, 0.0322582000, 0.0356743000, 0.0425767000, 0.0636384000, 0.1206441000, 0.2738738000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.5101650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0634559000, 0.0653257000, 0.0700737000, 0.0814931000, 0.1092210000, 0.1765194000, 0.3435645000", \ - "0.0678179000, 0.0696024000, 0.0743106000, 0.0858012000, 0.1134854000, 0.1807836000, 0.3478599000", \ - "0.0769281000, 0.0788078000, 0.0834429000, 0.0949166000, 0.1227964000, 0.1898089000, 0.3570086000", \ - "0.0948407000, 0.0966748000, 0.1011260000, 0.1126693000, 0.1401080000, 0.2073085000, 0.3745437000", \ - "0.1250314000, 0.1272429000, 0.1320560000, 0.1460141000, 0.1764944000, 0.2463092000, 0.4136265000", \ - "0.1626124000, 0.1657212000, 0.1738022000, 0.1914417000, 0.2333184000, 0.3185578000, 0.5014621000", \ - "0.1828071000, 0.1875033000, 0.1992948000, 0.2272980000, 0.2899480000, 0.4174018000, 0.6581006000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2198283000, 0.2248810000, 0.2383767000, 0.2740121000, 0.3640344000, 0.5968951000, 1.1972150000", \ - "0.2237695000, 0.2291937000, 0.2431259000, 0.2785376000, 0.3693755000, 0.6014671000, 1.2029181000", \ - "0.2346847000, 0.2390264000, 0.2541418000, 0.2900045000, 0.3808314000, 0.6143990000, 1.2159037000", \ - "0.2591881000, 0.2644198000, 0.2779360000, 0.3132827000, 0.4047160000, 0.6390204000, 1.2405967000", \ - "0.3095353000, 0.3144977000, 0.3280957000, 0.3634582000, 0.4550162000, 0.6890651000, 1.2936050000", \ - "0.4062264000, 0.4122019000, 0.4277752000, 0.4657046000, 0.5620601000, 0.7949891000, 1.3972660000", \ - "0.5705038000, 0.5775878000, 0.5953855000, 0.6456517000, 0.7601581000, 1.0236374000, 1.6359581000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0526568000, 0.0546747000, 0.0599266000, 0.0736434000, 0.1082335000, 0.1968394000, 0.4273771000", \ - "0.0524067000, 0.0544726000, 0.0597538000, 0.0734431000, 0.1080978000, 0.1966541000, 0.4276282000", \ - "0.0518484000, 0.0539271000, 0.0592958000, 0.0730021000, 0.1077174000, 0.1966370000, 0.4273623000", \ - "0.0540352000, 0.0560228000, 0.0610607000, 0.0741103000, 0.1081550000, 0.1963484000, 0.4271926000", \ - "0.0676596000, 0.0695809000, 0.0749001000, 0.0876360000, 0.1193970000, 0.2018121000, 0.4275903000", \ - "0.1025832000, 0.1048789000, 0.1112142000, 0.1250901000, 0.1602129000, 0.2400776000, 0.4474226000", \ - "0.1717172000, 0.1751251000, 0.1835107000, 0.2027989000, 0.2472318000, 0.3423278000, 0.5526390000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1570056000, 0.1642768000, 0.1823515000, 0.2302506000, 0.3526545000, 0.6696890000, 1.4902223000", \ - "0.1567360000, 0.1638958000, 0.1820015000, 0.2298328000, 0.3526091000, 0.6686884000, 1.4915970000", \ - "0.1566349000, 0.1648002000, 0.1824968000, 0.2298362000, 0.3526142000, 0.6691201000, 1.4877912000", \ - "0.1570419000, 0.1636996000, 0.1822997000, 0.2306843000, 0.3527008000, 0.6696984000, 1.4894804000", \ - "0.1594688000, 0.1665435000, 0.1839920000, 0.2305556000, 0.3533758000, 0.6705136000, 1.4891360000", \ - "0.1840823000, 0.1911377000, 0.2083335000, 0.2547940000, 0.3679031000, 0.6731636000, 1.4870671000", \ - "0.2444722000, 0.2521253000, 0.2712983000, 0.3197688000, 0.4393245000, 0.7312903000, 1.5034490000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0598996000, 0.0615359000, 0.0658675000, 0.0761600000, 0.1016371000, 0.1652302000, 0.3268520000", \ - "0.0645591000, 0.0661788000, 0.0705280000, 0.0807398000, 0.1062795000, 0.1699381000, 0.3315876000", \ - "0.0740976000, 0.0756163000, 0.0797866000, 0.0901792000, 0.1158812000, 0.1793477000, 0.3409175000", \ - "0.0918103000, 0.0933814000, 0.0978272000, 0.1086300000, 0.1342642000, 0.1978993000, 0.3597883000", \ - "0.1191609000, 0.1213417000, 0.1269325000, 0.1404504000, 0.1705686000, 0.2385698000, 0.4009462000", \ - "0.1478484000, 0.1511010000, 0.1592288000, 0.1793142000, 0.2220431000, 0.3109116000, 0.4942142000", \ - "0.1478173000, 0.1533791000, 0.1664121000, 0.1965742000, 0.2645361000, 0.4001763000, 0.6494170000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2060386000, 0.2113910000, 0.2253440000, 0.2603997000, 0.3511886000, 0.5838098000, 1.1841556000", \ - "0.2088612000, 0.2144671000, 0.2283427000, 0.2629296000, 0.3542369000, 0.5874065000, 1.1880903000", \ - "0.2183804000, 0.2226237000, 0.2378544000, 0.2733415000, 0.3652486000, 0.5980642000, 1.1994494000", \ - "0.2429254000, 0.2491211000, 0.2631975000, 0.2985512000, 0.3901780000, 0.6245234000, 1.2267469000", \ - "0.3010002000, 0.3068200000, 0.3199939000, 0.3555556000, 0.4466766000, 0.6811719000, 1.2842593000", \ - "0.4215279000, 0.4281659000, 0.4438248000, 0.4853479000, 0.5820750000, 0.8160305000, 1.4187937000", \ - "0.6311591000, 0.6401612000, 0.6627107000, 0.7178666000, 0.8462167000, 1.1190462000, 1.7351607000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0416919000, 0.0436366000, 0.0486437000, 0.0614970000, 0.0947322000, 0.1814062000, 0.4068555000", \ - "0.0416969000, 0.0436159000, 0.0486317000, 0.0615173000, 0.0948434000, 0.1813864000, 0.4069075000", \ - "0.0415932000, 0.0435299000, 0.0485317000, 0.0614529000, 0.0946641000, 0.1811890000, 0.4070174000", \ - "0.0448133000, 0.0467081000, 0.0511152000, 0.0633430000, 0.0954962000, 0.1813513000, 0.4065814000", \ - "0.0599517000, 0.0618388000, 0.0667616000, 0.0793501000, 0.1097351000, 0.1883419000, 0.4075401000", \ - "0.0962995000, 0.0987672000, 0.1048439000, 0.1198558000, 0.1539510000, 0.2333925000, 0.4324732000", \ - "0.1656964000, 0.1689564000, 0.1784920000, 0.2005709000, 0.2462021000, 0.3435820000, 0.5470427000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1567602000, 0.1639096000, 0.1819757000, 0.2298642000, 0.3525033000, 0.6692148000, 1.4915819000", \ - "0.1567655000, 0.1639877000, 0.1821962000, 0.2299755000, 0.3526098000, 0.6709591000, 1.4873838000", \ - "0.1566157000, 0.1648403000, 0.1825320000, 0.2299705000, 0.3526985000, 0.6689391000, 1.4848284000", \ - "0.1573045000, 0.1640928000, 0.1820554000, 0.2298357000, 0.3526330000, 0.6709037000, 1.4915337000", \ - "0.1618326000, 0.1688797000, 0.1857155000, 0.2311088000, 0.3532922000, 0.6685512000, 1.4863508000", \ - "0.1996020000, 0.2067576000, 0.2235016000, 0.2654152000, 0.3738293000, 0.6733404000, 1.4892765000", \ - "0.2900615000, 0.2973877000, 0.3162180000, 0.3634872000, 0.4827837000, 0.7465049000, 1.5033821000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0458665000, 0.0474218000, 0.0512970000, 0.0607423000, 0.0839245000, 0.1422340000, 0.2913739000", \ - "0.0507340000, 0.0521896000, 0.0561530000, 0.0655117000, 0.0888533000, 0.1472680000, 0.2962445000", \ - "0.0605617000, 0.0621186000, 0.0660622000, 0.0755574000, 0.0991891000, 0.1577763000, 0.3068745000", \ - "0.0779344000, 0.0796842000, 0.0843266000, 0.0947308000, 0.1190141000, 0.1778749000, 0.3274388000", \ - "0.1005320000, 0.1030143000, 0.1095016000, 0.1235135000, 0.1551888000, 0.2215607000, 0.3725398000", \ - "0.1167183000, 0.1209041000, 0.1305330000, 0.1524252000, 0.2003993000, 0.2933072000, 0.4721626000", \ - "0.0952932000, 0.1014104000, 0.1164547000, 0.1538644000, 0.2285788000, 0.3740253000, 0.6297182000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1647324000, 0.1703224000, 0.1832449000, 0.2196188000, 0.3099044000, 0.5428016000, 1.1432353000", \ - "0.1659165000, 0.1707974000, 0.1853043000, 0.2214799000, 0.3126162000, 0.5457569000, 1.1465651000", \ - "0.1725368000, 0.1781564000, 0.1919072000, 0.2286517000, 0.3205957000, 0.5546860000, 1.1570772000", \ - "0.1954652000, 0.2009037000, 0.2152845000, 0.2503835000, 0.3432795000, 0.5782637000, 1.1811140000", \ - "0.2593066000, 0.2643418000, 0.2776627000, 0.3128824000, 0.4017976000, 0.6366405000, 1.2401778000", \ - "0.3952213000, 0.4019998000, 0.4191159000, 0.4604287000, 0.5540794000, 0.7796800000, 1.3811158000", \ - "0.6171946000, 0.6277217000, 0.6520804000, 0.7103356000, 0.8457113000, 1.1273439000, 1.7245027000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0296031000, 0.0313444000, 0.0357935000, 0.0476216000, 0.0782985000, 0.1580673000, 0.3660032000", \ - "0.0295309000, 0.0312678000, 0.0357772000, 0.0476371000, 0.0782991000, 0.1580126000, 0.3657256000", \ - "0.0295022000, 0.0312804000, 0.0357522000, 0.0475746000, 0.0783229000, 0.1581364000, 0.3659608000", \ - "0.0354624000, 0.0370795000, 0.0412579000, 0.0514992000, 0.0800763000, 0.1581108000, 0.3657758000", \ - "0.0528915000, 0.0547112000, 0.0593158000, 0.0709468000, 0.0989027000, 0.1685820000, 0.3669045000", \ - "0.0897749000, 0.0922227000, 0.0983631000, 0.1136274000, 0.1470062000, 0.2217774000, 0.3987694000", \ - "0.1590398000, 0.1626734000, 0.1717102000, 0.1946208000, 0.2414539000, 0.3366144000, 0.5280526000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1568235000, 0.1636200000, 0.1822121000, 0.2302752000, 0.3526028000, 0.6687254000, 1.4861015000", \ - "0.1565243000, 0.1642830000, 0.1822509000, 0.2303084000, 0.3524857000, 0.6684617000, 1.4849265000", \ - "0.1567935000, 0.1641793000, 0.1824399000, 0.2294858000, 0.3527821000, 0.6683067000, 1.4915715000", \ - "0.1554622000, 0.1629198000, 0.1813062000, 0.2295506000, 0.3528471000, 0.6706558000, 1.4864945000", \ - "0.1621227000, 0.1687968000, 0.1859036000, 0.2306829000, 0.3512898000, 0.6685068000, 1.4907353000", \ - "0.2132370000, 0.2205459000, 0.2388699000, 0.2805025000, 0.3819971000, 0.6741649000, 1.4920574000", \ - "0.3042253000, 0.3142086000, 0.3394526000, 0.3967982000, 0.5190539000, 0.7858444000, 1.5101654000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0513215000, 0.0531678000, 0.0579121000, 0.0692654000, 0.0971513000, 0.1640971000, 0.3313117000", \ - "0.0550856000, 0.0569626000, 0.0616862000, 0.0730860000, 0.1010326000, 0.1680844000, 0.3352175000", \ - "0.0647423000, 0.0666198000, 0.0712442000, 0.0827935000, 0.1104631000, 0.1778053000, 0.3450521000", \ - "0.0893068000, 0.0911897000, 0.0955587000, 0.1064096000, 0.1334020000, 0.2004430000, 0.3677239000", \ - "0.1259152000, 0.1285069000, 0.1352122000, 0.1509234000, 0.1850745000, 0.2550060000, 0.4217377000", \ - "0.1635055000, 0.1674175000, 0.1765458000, 0.1995909000, 0.2530406000, 0.3541399000, 0.5471835000", \ - "0.1788392000, 0.1846342000, 0.1991058000, 0.2336794000, 0.3109369000, 0.4695788000, 0.7621294000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0792204000, 0.0834163000, 0.0939052000, 0.1199934000, 0.1859499000, 0.3524727000, 0.7822319000", \ - "0.0831628000, 0.0873329000, 0.0979320000, 0.1244350000, 0.1908667000, 0.3576772000, 0.7891137000", \ - "0.0947185000, 0.0987072000, 0.1090248000, 0.1356374000, 0.2027744000, 0.3713541000, 0.8052640000", \ - "0.1217184000, 0.1255421000, 0.1357804000, 0.1617414000, 0.2281990000, 0.3981131000, 0.8301085000", \ - "0.1698880000, 0.1751796000, 0.1881236000, 0.2184820000, 0.2858575000, 0.4544796000, 0.8884484000", \ - "0.2502680000, 0.2581948000, 0.2762763000, 0.3180836000, 0.4093902000, 0.5906166000, 1.0245110000", \ - "0.3842713000, 0.3961251000, 0.4246823000, 0.4880846000, 0.6185492000, 0.8623986000, 1.3428663000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0516550000, 0.0536827000, 0.0589770000, 0.0726792000, 0.1073196000, 0.1965140000, 0.4272577000", \ - "0.0517493000, 0.0537786000, 0.0591125000, 0.0727891000, 0.1073759000, 0.1966382000, 0.4273292000", \ - "0.0502483000, 0.0523155000, 0.0578549000, 0.0720081000, 0.1073861000, 0.1963085000, 0.4270915000", \ - "0.0567047000, 0.0584129000, 0.0631861000, 0.0751971000, 0.1077845000, 0.1960623000, 0.4271190000", \ - "0.0784322000, 0.0809395000, 0.0871288000, 0.1016173000, 0.1334942000, 0.2082171000, 0.4272521000", \ - "0.1214887000, 0.1251885000, 0.1342296000, 0.1547802000, 0.1958149000, 0.2838720000, 0.4693759000", \ - "0.1949400000, 0.2003322000, 0.2135885000, 0.2441496000, 0.3087761000, 0.4294281000, 0.6503731000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0967887000, 0.1019099000, 0.1151702000, 0.1495030000, 0.2376917000, 0.4639955000, 1.0527158000", \ - "0.0968391000, 0.1019198000, 0.1151739000, 0.1495078000, 0.2376349000, 0.4638414000, 1.0515320000", \ - "0.0969174000, 0.1019885000, 0.1152463000, 0.1495194000, 0.2376658000, 0.4638747000, 1.0532438000", \ - "0.0993821000, 0.1040104000, 0.1163640000, 0.1497975000, 0.2376218000, 0.4642853000, 1.0525668000", \ - "0.1202482000, 0.1239684000, 0.1344283000, 0.1635489000, 0.2436354000, 0.4640641000, 1.0520377000", \ - "0.1728244000, 0.1769312000, 0.1879715000, 0.2161414000, 0.2880447000, 0.4838429000, 1.0521723000", \ - "0.2770544000, 0.2818396000, 0.2932750000, 0.3252684000, 0.4035652000, 0.5930438000, 1.0968682000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0398049000, 0.0419475000, 0.0472208000, 0.0599396000, 0.0900344000, 0.1617752000, 0.3403261000", \ - "0.0440104000, 0.0462057000, 0.0513729000, 0.0642556000, 0.0944078000, 0.1664387000, 0.3451251000", \ - "0.0547086000, 0.0567092000, 0.0619766000, 0.0743065000, 0.1045272000, 0.1766478000, 0.3554658000", \ - "0.0797085000, 0.0819111000, 0.0873939000, 0.0997102000, 0.1285689000, 0.2004095000, 0.3794376000", \ - "0.1108533000, 0.1140804000, 0.1219742000, 0.1400626000, 0.1794418000, 0.2548627000, 0.4333636000", \ - "0.1407719000, 0.1455024000, 0.1570480000, 0.1838468000, 0.2424166000, 0.3558498000, 0.5599824000", \ - "0.1441490000, 0.1511124000, 0.1683414000, 0.2084562000, 0.2968317000, 0.4689596000, 0.7824718000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0558125000, 0.0600677000, 0.0707630000, 0.0975658000, 0.1635061000, 0.3322808000, 0.7619566000", \ - "0.0579974000, 0.0621648000, 0.0729793000, 0.0999973000, 0.1671560000, 0.3342411000, 0.7657153000", \ - "0.0677964000, 0.0717915000, 0.0824206000, 0.1087485000, 0.1761958000, 0.3464983000, 0.7770790000", \ - "0.0958815000, 0.1000091000, 0.1095686000, 0.1352561000, 0.2006917000, 0.3703770000, 0.8036033000", \ - "0.1441102000, 0.1504186000, 0.1655108000, 0.1981660000, 0.2663888000, 0.4331353000, 0.8674768000", \ - "0.2225903000, 0.2318431000, 0.2542661000, 0.3053086000, 0.4039866000, 0.5873463000, 1.0143826000", \ - "0.3625560000, 0.3751406000, 0.4066645000, 0.4785030000, 0.6261088000, 0.8996188000, 1.3742841000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0470078000, 0.0491327000, 0.0546222000, 0.0690100000, 0.1056936000, 0.2004551000, 0.4473643000", \ - "0.0466672000, 0.0489236000, 0.0545125000, 0.0691108000, 0.1057072000, 0.2004564000, 0.4473489000", \ - "0.0453892000, 0.0474414000, 0.0531182000, 0.0676620000, 0.1053384000, 0.2004825000, 0.4472024000", \ - "0.0544414000, 0.0561023000, 0.0609553000, 0.0726371000, 0.1061115000, 0.1997632000, 0.4472468000", \ - "0.0756354000, 0.0783049000, 0.0849273000, 0.1003153000, 0.1345478000, 0.2121296000, 0.4467409000", \ - "0.1171367000, 0.1209469000, 0.1303795000, 0.1524906000, 0.1984094000, 0.2868873000, 0.4863498000", \ - "0.1910377000, 0.1964955000, 0.2109367000, 0.2441011000, 0.3109850000, 0.4416512000, 0.6687170000"); - } - related_pin : "B2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0970667000, 0.1021988000, 0.1155891000, 0.1499743000, 0.2381218000, 0.4647097000, 1.0535203000", \ - "0.0969241000, 0.1020286000, 0.1154806000, 0.1499480000, 0.2381197000, 0.4644866000, 1.0531522000", \ - "0.0960438000, 0.1014145000, 0.1150225000, 0.1498218000, 0.2381010000, 0.4644991000, 1.0531443000", \ - "0.1045844000, 0.1086751000, 0.1198898000, 0.1506244000, 0.2378198000, 0.4646515000, 1.0537832000", \ - "0.1429665000, 0.1451605000, 0.1529327000, 0.1769429000, 0.2482767000, 0.4642505000, 1.0523895000", \ - "0.2052948000, 0.2099460000, 0.2221750000, 0.2520701000, 0.3174375000, 0.4949549000, 1.0521913000", \ - "0.3140391000, 0.3207013000, 0.3368382000, 0.3770839000, 0.4705830000, 0.6600374000, 1.1234288000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41a_1") { - leakage_power () { - value : 0.0025373000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0013058000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0014988000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0013053000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009728000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0013738000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009814000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0009850000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009564000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0020666000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0010464000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0010419000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009644000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0010520000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009696000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0009740000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0009535000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015311000; - when : "A1&A2&A3&A4&!B1"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__o41a"; - cell_leakage_power : 0.0013734680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039982000, 0.0039995000, 0.0040026000, 0.0040025000, 0.0040025000, 0.0040023000, 0.0040018000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003998800, -0.003997100, -0.003993200, -0.003993700, -0.003994700, -0.003997200, -0.004002800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024210000; - } - pin ("A2") { - capacitance : 0.0023980000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040458000, 0.0040401000, 0.0040271000, 0.0040251000, 0.0040205000, 0.0040101000, 0.0039859000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004014600, -0.004017600, -0.004024300, -0.004023000, -0.004020100, -0.004013300, -0.003997600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025410000; - } - pin ("A3") { - capacitance : 0.0023890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038607000, 0.0038599000, 0.0038580000, 0.0038588000, 0.0038607000, 0.0038651000, 0.0038751000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003860600, -0.003860300, -0.003859700, -0.003858900, -0.003857000, -0.003852800, -0.003842900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025470000; - } - pin ("A4") { - capacitance : 0.0024250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041085000, 0.0041066000, 0.0041022000, 0.0041029000, 0.0041046000, 0.0041084000, 0.0041171000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004098700, -0.004098700, -0.004098800, -0.004099700, -0.004101700, -0.004106400, -0.004117100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026130000; - } - pin ("B1") { - capacitance : 0.0023950000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048262000, 0.0048284000, 0.0048335000, 0.0048369000, 0.0048448000, 0.0048629000, 0.0049046000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000678400, -0.000694600, -0.000732100, -0.000707200, -0.000649600, -0.000516800, -0.000210900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024720000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1) | (A4&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0186547000, 0.0177510000, 0.0153472000, 0.0084125000, -0.011899200, -0.067671900, -0.213556900", \ - "0.0185174000, 0.0176141000, 0.0152120000, 0.0082751000, -0.012031700, -0.067886900, -0.213775400", \ - "0.0183360000, 0.0174284000, 0.0150142000, 0.0080360000, -0.012220300, -0.068052400, -0.213958700", \ - "0.0181785000, 0.0172753000, 0.0148621000, 0.0079246000, -0.012381700, -0.068232900, -0.214132000", \ - "0.0180989000, 0.0171935000, 0.0147931000, 0.0077617000, -0.012559200, -0.068356500, -0.214237800", \ - "0.0179672000, 0.0170436000, 0.0145937000, 0.0077135000, -0.012636800, -0.068474000, -0.214332900", \ - "0.0216955000, 0.0203894000, 0.0170676000, 0.0086372000, -0.013222600, -0.068595500, -0.214417600"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0159511000, 0.0174610000, 0.0212181000, 0.0302739000, 0.0527080000, 0.1094458000, 0.2537800000", \ - "0.0158269000, 0.0173728000, 0.0211337000, 0.0301842000, 0.0524271000, 0.1089082000, 0.2547578000", \ - "0.0157034000, 0.0172358000, 0.0209926000, 0.0300381000, 0.0523565000, 0.1085492000, 0.2546185000", \ - "0.0156377000, 0.0171451000, 0.0208665000, 0.0298710000, 0.0521598000, 0.1085607000, 0.2545045000", \ - "0.0156367000, 0.0171282000, 0.0207632000, 0.0296973000, 0.0519853000, 0.1085401000, 0.2543912000", \ - "0.0162763000, 0.0175763000, 0.0209461000, 0.0294418000, 0.0517586000, 0.1080193000, 0.2542449000", \ - "0.0170568000, 0.0183559000, 0.0216211000, 0.0302432000, 0.0522181000, 0.1089749000, 0.2540051000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0164956000, 0.0155919000, 0.0131850000, 0.0061781000, -0.014096700, -0.069849900, -0.215768500", \ - "0.0164471000, 0.0155188000, 0.0131421000, 0.0060904000, -0.014214300, -0.070050700, -0.215941100", \ - "0.0161953000, 0.0152925000, 0.0128577000, 0.0058830000, -0.014378100, -0.070137300, -0.216011800", \ - "0.0160289000, 0.0151181000, 0.0127097000, 0.0057342000, -0.014536000, -0.070369100, -0.216270200", \ - "0.0159240000, 0.0150456000, 0.0126602000, 0.0056171000, -0.014700700, -0.070498100, -0.216375800", \ - "0.0158127000, 0.0150074000, 0.0125569000, 0.0055322000, -0.014798100, -0.070614600, -0.216479200", \ - "0.0191937000, 0.0181671000, 0.0147300000, 0.0062468000, -0.015305500, -0.070733400, -0.216535000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0152296000, 0.0166745000, 0.0202524000, 0.0291000000, 0.0511944000, 0.1079390000, 0.2533040000", \ - "0.0151955000, 0.0166391000, 0.0202185000, 0.0290596000, 0.0511795000, 0.1078800000, 0.2533740000", \ - "0.0150969000, 0.0165495000, 0.0201312000, 0.0289744000, 0.0510961000, 0.1074731000, 0.2524120000", \ - "0.0149567000, 0.0163865000, 0.0199564000, 0.0287644000, 0.0509254000, 0.1072177000, 0.2520232000", \ - "0.0147443000, 0.0161758000, 0.0197215000, 0.0284471000, 0.0507630000, 0.1073531000, 0.2527626000", \ - "0.0150776000, 0.0164052000, 0.0197278000, 0.0281247000, 0.0503359000, 0.1063679000, 0.2514856000", \ - "0.0154548000, 0.0167187000, 0.0201419000, 0.0286697000, 0.0506434000, 0.1071207000, 0.2508090000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0144276000, 0.0135304000, 0.0110730000, 0.0041052000, -0.016200900, -0.072033100, -0.217906700", \ - "0.0142062000, 0.0133558000, 0.0110100000, 0.0040373000, -0.016298100, -0.072162700, -0.218020100", \ - "0.0140780000, 0.0131748000, 0.0107473000, 0.0037639000, -0.016494900, -0.072312000, -0.218123300", \ - "0.0139222000, 0.0130203000, 0.0105904000, 0.0036086000, -0.016650300, -0.072408500, -0.218265500", \ - "0.0137907000, 0.0129094000, 0.0105224000, 0.0034853000, -0.016846100, -0.072641000, -0.218513400", \ - "0.0136598000, 0.0127720000, 0.0104650000, 0.0034273000, -0.016975300, -0.072774500, -0.218628800", \ - "0.0172679000, 0.0159302000, 0.0125197000, 0.0041475000, -0.017352300, -0.072828500, -0.218595600"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0139008000, 0.0152986000, 0.0187997000, 0.0275067000, 0.0497028000, 0.1057276000, 0.2505673000", \ - "0.0139072000, 0.0153004000, 0.0188023000, 0.0275125000, 0.0497149000, 0.1057385000, 0.2505624000", \ - "0.0138542000, 0.0152495000, 0.0187505000, 0.0274538000, 0.0494414000, 0.1057585000, 0.2502033000", \ - "0.0136784000, 0.0150655000, 0.0185504000, 0.0272320000, 0.0494676000, 0.1055485000, 0.2504196000", \ - "0.0133859000, 0.0147482000, 0.0182317000, 0.0268474000, 0.0488645000, 0.1052656000, 0.2498089000", \ - "0.0134040000, 0.0147480000, 0.0181081000, 0.0265486000, 0.0485902000, 0.1045626000, 0.2495909000", \ - "0.0137101000, 0.0149438000, 0.0183320000, 0.0269372000, 0.0489555000, 0.1053435000, 0.2502674000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0122337000, 0.0113426000, 0.0089693000, 0.0019418000, -0.018353900, -0.074177900, -0.220078600", \ - "0.0119793000, 0.0111338000, 0.0087526000, 0.0017420000, -0.018559700, -0.074380800, -0.220267900", \ - "0.0117775000, 0.0108723000, 0.0084830000, 0.0014677000, -0.018810300, -0.074636500, -0.220518100", \ - "0.0115699000, 0.0106626000, 0.0082461000, 0.0012678000, -0.019021800, -0.074841200, -0.220713300", \ - "0.0115684000, 0.0106799000, 0.0082126000, 0.0012682000, -0.019044000, -0.074859800, -0.220726300", \ - "0.0121396000, 0.0111956000, 0.0087374000, 0.0016310000, -0.018790700, -0.074656300, -0.220526400", \ - "0.0165384000, 0.0151895000, 0.0118304000, 0.0032520000, -0.018508400, -0.074029500, -0.219821700"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0124068000, 0.0137863000, 0.0172908000, 0.0259709000, 0.0478899000, 0.1038197000, 0.2482064000", \ - "0.0123791000, 0.0137670000, 0.0172342000, 0.0259355000, 0.0478624000, 0.1041867000, 0.2476713000", \ - "0.0122411000, 0.0136325000, 0.0171173000, 0.0257916000, 0.0477844000, 0.1040207000, 0.2469942000", \ - "0.0119599000, 0.0133274000, 0.0167759000, 0.0254464000, 0.0474679000, 0.1036367000, 0.2469764000", \ - "0.0117488000, 0.0129966000, 0.0164220000, 0.0250099000, 0.0469678000, 0.1033847000, 0.2479780000", \ - "0.0115611000, 0.0129025000, 0.0162910000, 0.0247994000, 0.0467831000, 0.1030442000, 0.2490849000", \ - "0.0120560000, 0.0132596000, 0.0166615000, 0.0252852000, 0.0473102000, 0.1039202000, 0.2481184000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0106238000, 0.0098353000, 0.0076724000, 0.0007545000, -0.020516100, -0.077155800, -0.223403800", \ - "0.0103379000, 0.0095739000, 0.0074437000, 0.0005524000, -0.020729200, -0.077355400, -0.223616300", \ - "0.0100378000, 0.0092564000, 0.0071101000, 0.0002551000, -0.021000400, -0.077624100, -0.223868900", \ - "0.0096915000, 0.0089050000, 0.0067533000, -3.64000e-05, -0.021217800, -0.077832600, -0.224060000", \ - "0.0092841000, 0.0086515000, 0.0065286000, -0.000142700, -0.021212600, -0.077753500, -0.223962300", \ - "0.0125603000, 0.0113103000, 0.0081591000, -0.000220700, -0.020955700, -0.077443400, -0.223625100", \ - "0.0146848000, 0.0134178000, 0.0101600000, 0.0016996000, -0.020075900, -0.076380400, -0.222487500"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277870, 0.0085851570, 0.0221483300, 0.0571391500, 0.1474098000"); - values("0.0128562000, 0.0143859000, 0.0181466000, 0.0272274000, 0.0494979000, 0.1059924000, 0.2518082000", \ - "0.0127445000, 0.0142710000, 0.0180538000, 0.0270947000, 0.0494168000, 0.1062195000, 0.2507908000", \ - "0.0126350000, 0.0141675000, 0.0179204000, 0.0269715000, 0.0492678000, 0.1056738000, 0.2513352000", \ - "0.0125432000, 0.0140254000, 0.0177082000, 0.0266881000, 0.0491398000, 0.1052797000, 0.2502951000", \ - "0.0123838000, 0.0138281000, 0.0173879000, 0.0263052000, 0.0485684000, 0.1050932000, 0.2510925000", \ - "0.0132813000, 0.0145814000, 0.0179472000, 0.0262521000, 0.0485382000, 0.1048347000, 0.2500130000", \ - "0.0140784000, 0.0152944000, 0.0185768000, 0.0271552000, 0.0491740000, 0.1057848000, 0.2506503000"); - } - } - max_capacitance : 0.1474100000; - max_transition : 1.5065940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.3729366000, 0.3821557000, 0.4013810000, 0.4377928000, 0.5084914000, 0.6490888000, 0.9658950000", \ - "0.3768464000, 0.3860690000, 0.4053729000, 0.4418240000, 0.5125003000, 0.6530022000, 0.9698210000", \ - "0.3875077000, 0.3967272000, 0.4159075000, 0.4530707000, 0.5226497000, 0.6630783000, 0.9798322000", \ - "0.4115558000, 0.4208409000, 0.4400976000, 0.4769275000, 0.5473397000, 0.6875466000, 1.0043157000", \ - "0.4624751000, 0.4718320000, 0.4910420000, 0.5280857000, 0.5977129000, 0.7382974000, 1.0546872000", \ - "0.5641656000, 0.5735905000, 0.5929809000, 0.6294796000, 0.7003153000, 0.8409120000, 1.1575730000", \ - "0.7372223000, 0.7475319000, 0.7686288000, 0.8088406000, 0.8838671000, 1.0296443000, 1.3493444000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.1023519000, 0.1102870000, 0.1287031000, 0.1706594000, 0.2713120000, 0.5224383000, 1.1620999000", \ - "0.1069119000, 0.1149737000, 0.1333330000, 0.1752477000, 0.2759274000, 0.5268395000, 1.1681058000", \ - "0.1173068000, 0.1253029000, 0.1435921000, 0.1855453000, 0.2860223000, 0.5362895000, 1.1793629000", \ - "0.1386726000, 0.1465114000, 0.1645608000, 0.2061503000, 0.3066413000, 0.5573046000, 1.1999546000", \ - "0.1793417000, 0.1874377000, 0.2055852000, 0.2469766000, 0.3470883000, 0.5979893000, 1.2400051000", \ - "0.2370976000, 0.2459096000, 0.2651577000, 0.3072054000, 0.4071068000, 0.6578204000, 1.2992936000", \ - "0.2944898000, 0.3057193000, 0.3282030000, 0.3729220000, 0.4728504000, 0.7241294000, 1.3644992000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0462622000, 0.0516658000, 0.0651845000, 0.0933032000, 0.1556757000, 0.3036177000, 0.6944876000", \ - "0.0462861000, 0.0516814000, 0.0650903000, 0.0930729000, 0.1556496000, 0.3036708000, 0.6939535000", \ - "0.0465178000, 0.0517652000, 0.0642370000, 0.0929260000, 0.1560406000, 0.3029030000, 0.6921411000", \ - "0.0462213000, 0.0516565000, 0.0651947000, 0.0925636000, 0.1556253000, 0.3035167000, 0.6926474000", \ - "0.0459646000, 0.0515149000, 0.0649461000, 0.0922115000, 0.1557010000, 0.3027497000, 0.6928716000", \ - "0.0476859000, 0.0525966000, 0.0654232000, 0.0951295000, 0.1562221000, 0.3027150000, 0.6939678000", \ - "0.0538341000, 0.0595147000, 0.0725701000, 0.1015638000, 0.1654730000, 0.3117858000, 0.6993515000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0313112000, 0.0392910000, 0.0593672000, 0.1111807000, 0.2458413000, 0.5961913000, 1.4993506000", \ - "0.0312908000, 0.0392505000, 0.0593761000, 0.1109756000, 0.2456813000, 0.5954146000, 1.5025124000", \ - "0.0311665000, 0.0391325000, 0.0591886000, 0.1110489000, 0.2460104000, 0.5957453000, 1.5033795000", \ - "0.0308152000, 0.0387559000, 0.0587697000, 0.1106938000, 0.2460626000, 0.5944968000, 1.4999755000", \ - "0.0326053000, 0.0402866000, 0.0596982000, 0.1103803000, 0.2454851000, 0.5946449000, 1.5026222000", \ - "0.0379966000, 0.0453675000, 0.0634942000, 0.1122804000, 0.2451966000, 0.5950754000, 1.5026969000", \ - "0.0497361000, 0.0575558000, 0.0749292000, 0.1185825000, 0.2470849000, 0.5975212000, 1.4993115000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.3591482000, 0.3683663000, 0.3875903000, 0.4248068000, 0.4946187000, 0.6352893000, 0.9520988000", \ - "0.3620912000, 0.3712567000, 0.3904287000, 0.4276006000, 0.4980572000, 0.6384122000, 0.9548978000", \ - "0.3720576000, 0.3812829000, 0.4005208000, 0.4376913000, 0.5074283000, 0.6482219000, 0.9650246000", \ - "0.3973664000, 0.4066892000, 0.4258116000, 0.4629639000, 0.5325326000, 0.6729700000, 0.9897365000", \ - "0.4532787000, 0.4625382000, 0.4817772000, 0.5188392000, 0.5885985000, 0.7292012000, 1.0456011000", \ - "0.5729447000, 0.5823113000, 0.6013763000, 0.6387008000, 0.7094001000, 0.8500219000, 1.1668555000", \ - "0.7927912000, 0.8040477000, 0.8257208000, 0.8667113000, 0.9419016000, 1.0880982000, 1.4085511000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0987282000, 0.1062873000, 0.1236618000, 0.1640546000, 0.2625690000, 0.5126808000, 1.1544072000", \ - "0.1035071000, 0.1110823000, 0.1284343000, 0.1688772000, 0.2673298000, 0.5173315000, 1.1591572000", \ - "0.1134170000, 0.1210030000, 0.1383816000, 0.1788155000, 0.2774428000, 0.5267882000, 1.1658524000", \ - "0.1334873000, 0.1409444000, 0.1582070000, 0.1984493000, 0.2969401000, 0.5463185000, 1.1861659000", \ - "0.1697203000, 0.1774665000, 0.1950480000, 0.2352818000, 0.3340816000, 0.5843702000, 1.2260308000", \ - "0.2170207000, 0.2257200000, 0.2442718000, 0.2851790000, 0.3838943000, 0.6334224000, 1.2736987000", \ - "0.2520174000, 0.2629220000, 0.2853025000, 0.3292826000, 0.4284002000, 0.6780184000, 1.3182575000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0462806000, 0.0516591000, 0.0651758000, 0.0922354000, 0.1557282000, 0.3035710000, 0.6950175000", \ - "0.0464510000, 0.0518386000, 0.0652842000, 0.0922534000, 0.1559431000, 0.3025352000, 0.6932280000", \ - "0.0462192000, 0.0516264000, 0.0642668000, 0.0923981000, 0.1557345000, 0.3035105000, 0.6954133000", \ - "0.0466840000, 0.0518846000, 0.0642118000, 0.0931034000, 0.1560648000, 0.3031212000, 0.6917862000", \ - "0.0458515000, 0.0515220000, 0.0649078000, 0.0921095000, 0.1557116000, 0.3026690000, 0.6927729000", \ - "0.0475793000, 0.0539182000, 0.0670089000, 0.0939181000, 0.1563650000, 0.3037985000, 0.6942413000", \ - "0.0560330000, 0.0622019000, 0.0752324000, 0.1047855000, 0.1657210000, 0.3121362000, 0.6979363000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0293588000, 0.0370538000, 0.0565545000, 0.1079065000, 0.2430451000, 0.5937910000, 1.5009279000", \ - "0.0293436000, 0.0370540000, 0.0567080000, 0.1078476000, 0.2428384000, 0.5941741000, 1.5027469000", \ - "0.0293484000, 0.0370631000, 0.0566802000, 0.1075774000, 0.2431230000, 0.5932976000, 1.4984445000", \ - "0.0292595000, 0.0368797000, 0.0564422000, 0.1075690000, 0.2427543000, 0.5927390000, 1.4973588000", \ - "0.0312356000, 0.0387584000, 0.0576254000, 0.1079598000, 0.2427636000, 0.5939600000, 1.5026769000", \ - "0.0369825000, 0.0439465000, 0.0619069000, 0.1103662000, 0.2428843000, 0.5923751000, 1.4970357000", \ - "0.0490944000, 0.0565073000, 0.0734405000, 0.1168889000, 0.2450314000, 0.5969598000, 1.4983189000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.3255883000, 0.3349449000, 0.3541560000, 0.3912054000, 0.4613575000, 0.6021538000, 0.9188746000", \ - "0.3282509000, 0.3375698000, 0.3565147000, 0.3937460000, 0.4641106000, 0.6046129000, 0.9209887000", \ - "0.3376736000, 0.3468918000, 0.3661084000, 0.4032636000, 0.4725583000, 0.6138175000, 0.9305834000", \ - "0.3622227000, 0.3714496000, 0.3906807000, 0.4278165000, 0.4975640000, 0.6383415000, 0.9551447000", \ - "0.4209843000, 0.4302944000, 0.4495594000, 0.4865739000, 0.5563909000, 0.6970212000, 1.0136491000", \ - "0.5541481000, 0.5637464000, 0.5835333000, 0.6208391000, 0.6907942000, 0.8314966000, 1.1482832000", \ - "0.8047636000, 0.8155884000, 0.8377516000, 0.8792957000, 0.9548451000, 1.1006810000, 1.4214213000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0934118000, 0.1005747000, 0.1173291000, 0.1566938000, 0.2544603000, 0.5028314000, 1.1413303000", \ - "0.0983073000, 0.1054755000, 0.1222337000, 0.1616161000, 0.2594023000, 0.5077631000, 1.1461059000", \ - "0.1082715000, 0.1155056000, 0.1322136000, 0.1715495000, 0.2694423000, 0.5173182000, 1.1581079000", \ - "0.1278449000, 0.1350094000, 0.1516922000, 0.1910389000, 0.2889270000, 0.5375127000, 1.1760568000", \ - "0.1608797000, 0.1684517000, 0.1856350000, 0.2252890000, 0.3231275000, 0.5718047000, 1.2125597000", \ - "0.2005311000, 0.2091068000, 0.2276938000, 0.2682360000, 0.3662126000, 0.6152270000, 1.2556656000", \ - "0.2211237000, 0.2322671000, 0.2552073000, 0.2996278000, 0.3982470000, 0.6479317000, 1.2872243000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0459919000, 0.0515093000, 0.0651651000, 0.0921680000, 0.1556732000, 0.3033598000, 0.6934518000", \ - "0.0459098000, 0.0516784000, 0.0647100000, 0.0925129000, 0.1556476000, 0.3029679000, 0.6921949000", \ - "0.0462970000, 0.0516395000, 0.0642749000, 0.0925002000, 0.1556968000, 0.3031200000, 0.6954262000", \ - "0.0462664000, 0.0516526000, 0.0642878000, 0.0924536000, 0.1557679000, 0.3034394000, 0.6955173000", \ - "0.0458668000, 0.0514935000, 0.0648080000, 0.0920020000, 0.1557535000, 0.3028634000, 0.6942072000", \ - "0.0481022000, 0.0535006000, 0.0660703000, 0.0950240000, 0.1568598000, 0.3035035000, 0.6946996000", \ - "0.0592285000, 0.0650719000, 0.0779199000, 0.1054137000, 0.1676869000, 0.3111573000, 0.6982546000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0276773000, 0.0352764000, 0.0546568000, 0.1059490000, 0.2420995000, 0.5918941000, 1.5010183000", \ - "0.0277361000, 0.0352764000, 0.0546527000, 0.1059493000, 0.2420918000, 0.5919539000, 1.5014010000", \ - "0.0277393000, 0.0352865000, 0.0547269000, 0.1056496000, 0.2418513000, 0.5936139000, 1.5040245000", \ - "0.0279646000, 0.0354738000, 0.0546753000, 0.1059722000, 0.2419934000, 0.5918978000, 1.5015035000", \ - "0.0304149000, 0.0377773000, 0.0564730000, 0.1064892000, 0.2418369000, 0.5937150000, 1.5040303000", \ - "0.0367155000, 0.0438286000, 0.0616436000, 0.1094791000, 0.2422678000, 0.5924957000, 1.4986899000", \ - "0.0497845000, 0.0571937000, 0.0740790000, 0.1175419000, 0.2440519000, 0.5962924000, 1.4946111000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.2721943000, 0.2815503000, 0.3007850000, 0.3378320000, 0.4083161000, 0.5486053000, 0.8652429000", \ - "0.2732566000, 0.2825831000, 0.3016397000, 0.3388999000, 0.4090006000, 0.5496476000, 0.8663328000", \ - "0.2802064000, 0.2894802000, 0.3086790000, 0.3454192000, 0.4158748000, 0.5565555000, 0.8730456000", \ - "0.3039568000, 0.3131864000, 0.3323676000, 0.3691831000, 0.4395704000, 0.5803117000, 0.8966680000", \ - "0.3645429000, 0.3737939000, 0.3929917000, 0.4300625000, 0.5002772000, 0.6410065000, 0.9576883000", \ - "0.5126741000, 0.5217635000, 0.5406495000, 0.5770727000, 0.6471069000, 0.7877732000, 1.1045979000", \ - "0.7769148000, 0.7886077000, 0.8114890000, 0.8518478000, 0.9227773000, 1.0650756000, 1.3858518000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0808251000, 0.0877537000, 0.1041670000, 0.1431527000, 0.2400292000, 0.4883311000, 1.1343781000", \ - "0.0856984000, 0.0926453000, 0.1089847000, 0.1478419000, 0.2450163000, 0.4935903000, 1.1321366000", \ - "0.0958302000, 0.1027946000, 0.1191376000, 0.1580770000, 0.2552578000, 0.5047091000, 1.1420977000", \ - "0.1154781000, 0.1224650000, 0.1387179000, 0.1776053000, 0.2749636000, 0.5247873000, 1.1639748000", \ - "0.1456115000, 0.1530323000, 0.1699998000, 0.2093752000, 0.3071025000, 0.5561192000, 1.1940745000", \ - "0.1772480000, 0.1860789000, 0.2050417000, 0.2455849000, 0.3435433000, 0.5921409000, 1.2328405000", \ - "0.1827647000, 0.1947704000, 0.2191095000, 0.2649753000, 0.3637474000, 0.6132871000, 1.2527022000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0456949000, 0.0514927000, 0.0648667000, 0.0921257000, 0.1558719000, 0.3025740000, 0.6926851000", \ - "0.0458955000, 0.0516562000, 0.0654249000, 0.0923888000, 0.1555600000, 0.3029804000, 0.6935389000", \ - "0.0462231000, 0.0515957000, 0.0651651000, 0.0933090000, 0.1550937000, 0.3024228000, 0.6936043000", \ - "0.0465378000, 0.0517579000, 0.0642222000, 0.0933263000, 0.1552273000, 0.3025704000, 0.6925250000", \ - "0.0464518000, 0.0525074000, 0.0643129000, 0.0929088000, 0.1552332000, 0.3028739000, 0.6927816000", \ - "0.0476777000, 0.0530907000, 0.0649033000, 0.0923244000, 0.1558318000, 0.3035531000, 0.6918454000", \ - "0.0655112000, 0.0707321000, 0.0823098000, 0.1053590000, 0.1631312000, 0.3091879000, 0.6990625000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0261977000, 0.0336831000, 0.0531209000, 0.1047474000, 0.2410918000, 0.5913443000, 1.5056845000", \ - "0.0261498000, 0.0336390000, 0.0531722000, 0.1047216000, 0.2403260000, 0.5930879000, 1.5065937000", \ - "0.0261871000, 0.0336285000, 0.0531722000, 0.1045503000, 0.2412059000, 0.5967719000, 1.4979781000", \ - "0.0269182000, 0.0342502000, 0.0534404000, 0.1047596000, 0.2411754000, 0.5972871000, 1.4961505000", \ - "0.0302330000, 0.0373618000, 0.0558918000, 0.1060234000, 0.2405222000, 0.5929580000, 1.4987160000", \ - "0.0379984000, 0.0449417000, 0.0621246000, 0.1091219000, 0.2419626000, 0.5915692000, 1.5028911000", \ - "0.0540977000, 0.0614809000, 0.0783757000, 0.1202823000, 0.2446769000, 0.5974454000, 1.4947338000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0740075000, 0.0792274000, 0.0909705000, 0.1165028000, 0.1731161000, 0.2984721000, 0.6062300000", \ - "0.0791023000, 0.0844038000, 0.0961843000, 0.1217695000, 0.1784090000, 0.3037279000, 0.6115148000", \ - "0.0923020000, 0.0975331000, 0.1093242000, 0.1350013000, 0.1917083000, 0.3171263000, 0.6247357000", \ - "0.1243116000, 0.1295505000, 0.1413523000, 0.1671563000, 0.2240245000, 0.3496803000, 0.6569880000", \ - "0.1857171000, 0.1918730000, 0.2051242000, 0.2329782000, 0.2912954000, 0.4175321000, 0.7254015000", \ - "0.2832767000, 0.2912606000, 0.3081755000, 0.3419628000, 0.4080387000, 0.5397234000, 0.8479941000", \ - "0.4418337000, 0.4520790000, 0.4738656000, 0.5171774000, 0.5981074000, 0.7448204000, 1.0568804000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0920687000, 0.1000955000, 0.1184304000, 0.1604204000, 0.2611152000, 0.5119034000, 1.1536382000", \ - "0.0962283000, 0.1042204000, 0.1225442000, 0.1645806000, 0.2649002000, 0.5162597000, 1.1575436000", \ - "0.1066818000, 0.1146813000, 0.1329716000, 0.1747702000, 0.2754336000, 0.5260591000, 1.1687248000", \ - "0.1321556000, 0.1398986000, 0.1576795000, 0.1989346000, 0.2993042000, 0.5504343000, 1.1903080000", \ - "0.1767227000, 0.1845365000, 0.2024190000, 0.2435138000, 0.3432428000, 0.5939579000, 1.2367124000", \ - "0.2328389000, 0.2410555000, 0.2592933000, 0.2999683000, 0.3999241000, 0.6510445000, 1.2922303000", \ - "0.2851220000, 0.2951100000, 0.3160598000, 0.3581969000, 0.4565395000, 0.7077471000, 1.3493807000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0196790000, 0.0245272000, 0.0360389000, 0.0633226000, 0.1259510000, 0.2749556000, 0.6755873000", \ - "0.0198568000, 0.0245766000, 0.0361205000, 0.0634885000, 0.1259012000, 0.2754441000, 0.6757852000", \ - "0.0198244000, 0.0244593000, 0.0361412000, 0.0634547000, 0.1259715000, 0.2748089000, 0.6770146000", \ - "0.0202870000, 0.0249051000, 0.0364338000, 0.0636290000, 0.1260645000, 0.2753733000, 0.6793247000", \ - "0.0260004000, 0.0304920000, 0.0415820000, 0.0678722000, 0.1284463000, 0.2760750000, 0.6794516000", \ - "0.0359988000, 0.0420442000, 0.0546443000, 0.0824632000, 0.1430306000, 0.2837786000, 0.6774997000", \ - "0.0515437000, 0.0583279000, 0.0744617000, 0.1089008000, 0.1753562000, 0.3068321000, 0.6802316000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012899200, 0.0033277900, 0.0085851600, 0.0221483000, 0.0571391000, 0.1474100000"); - values("0.0311426000, 0.0391483000, 0.0591648000, 0.1109267000, 0.2458231000, 0.5949856000, 1.5020735000", \ - "0.0311645000, 0.0391570000, 0.0591564000, 0.1108927000, 0.2458864000, 0.5955109000, 1.5015010000", \ - "0.0310128000, 0.0389379000, 0.0590955000, 0.1107626000, 0.2460027000, 0.5944630000, 1.4986251000", \ - "0.0305222000, 0.0384682000, 0.0583269000, 0.1100896000, 0.2451400000, 0.5960578000, 1.4977747000", \ - "0.0318782000, 0.0396062000, 0.0593102000, 0.1103042000, 0.2444748000, 0.5936868000, 1.5026769000", \ - "0.0366983000, 0.0436350000, 0.0616807000, 0.1113668000, 0.2462141000, 0.5954709000, 1.4993157000", \ - "0.0479418000, 0.0546755000, 0.0712797000, 0.1152963000, 0.2462165000, 0.5988419000, 1.4999257000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41a_2") { - leakage_power () { - value : 0.0011195000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0011242000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011074000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0042737000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0160239000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0015955000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0014342000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0032301000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011264000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0014884000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011333000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0011373000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011111000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0018005000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0032295000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011643000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0011654000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0011159000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0011728000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0032300000; - when : "A1&A2&!A3&!A4&!B1"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__o41a"; - cell_leakage_power : 0.0027357500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022570000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040494000, 0.0040523000, 0.0040590000, 0.0040591000, 0.0040594000, 0.0040601000, 0.0040616000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004058500, -0.004057000, -0.004053400, -0.004054600, -0.004057100, -0.004063100, -0.004076700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024830000; - } - pin ("A2") { - capacitance : 0.0023900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039781000, 0.0039758000, 0.0039707000, 0.0039691000, 0.0039654000, 0.0039570000, 0.0039376000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003969200, -0.003969400, -0.003969900, -0.003968700, -0.003966100, -0.003960000, -0.003945900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025340000; - } - pin ("A3") { - capacitance : 0.0023900000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038434000, 0.0038408000, 0.0038348000, 0.0038355000, 0.0038370000, 0.0038406000, 0.0038487000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003838500, -0.003838500, -0.003838700, -0.003837600, -0.003835100, -0.003829500, -0.003816400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025500000; - } - pin ("A4") { - capacitance : 0.0023050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038838000, 0.0038830000, 0.0038814000, 0.0038820000, 0.0038836000, 0.0038871000, 0.0038953000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003882500, -0.003881700, -0.003879900, -0.003879200, -0.003877500, -0.003873600, -0.003864700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024840000; - } - pin ("B1") { - capacitance : 0.0023190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022420000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0046838000, 0.0046817000, 0.0046771000, 0.0046773000, 0.0046779000, 0.0046792000, 0.0046823000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000264300, -0.000290200, -0.000349900, -0.000320000, -0.000250900, -9.1451365e-05, 0.0002760000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023950000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1) | (A4&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0211599000, 0.0195225000, 0.0156186000, 0.0041884000, -0.031111400, -0.140655200, -0.465342100", \ - "0.0210212000, 0.0193919000, 0.0154791000, 0.0040606000, -0.031466400, -0.140757300, -0.465473600", \ - "0.0208627000, 0.0192469000, 0.0152508000, 0.0039534000, -0.031550200, -0.141035800, -0.465663400", \ - "0.0207382000, 0.0192486000, 0.0152227000, 0.0037849000, -0.031700500, -0.141258100, -0.465859600", \ - "0.0205517000, 0.0190806000, 0.0151358000, 0.0037865000, -0.031897400, -0.141397700, -0.466004900", \ - "0.0205914000, 0.0189191000, 0.0149128000, 0.0034447000, -0.032042400, -0.141592300, -0.466113000", \ - "0.0248585000, 0.0230484000, 0.0182641000, 0.0048892000, -0.032425000, -0.141678200, -0.466202300"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0201444000, 0.0218865000, 0.0268556000, 0.0408876000, 0.0796947000, 0.1906119000, 0.5124125000", \ - "0.0200326000, 0.0217886000, 0.0268464000, 0.0407103000, 0.0796032000, 0.1905121000, 0.5146615000", \ - "0.0198832000, 0.0215956000, 0.0266082000, 0.0406195000, 0.0793956000, 0.1911840000, 0.5117274000", \ - "0.0198093000, 0.0215397000, 0.0265466000, 0.0405047000, 0.0792973000, 0.1902025000, 0.5141002000", \ - "0.0199923000, 0.0216733000, 0.0266490000, 0.0402228000, 0.0788966000, 0.1900345000, 0.5139810000", \ - "0.0209807000, 0.0225514000, 0.0271817000, 0.0401313000, 0.0788281000, 0.1893354000, 0.5140596000", \ - "0.0218848000, 0.0234135000, 0.0278285000, 0.0409789000, 0.0791656000, 0.1905117000, 0.5131212000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0189674000, 0.0173400000, 0.0134206000, 0.0020317000, -0.033469900, -0.142919700, -0.467452300", \ - "0.0188384000, 0.0172246000, 0.0132087000, 0.0019220000, -0.033583500, -0.143059700, -0.467615000", \ - "0.0186776000, 0.0170727000, 0.0131443000, 0.0017494000, -0.033753400, -0.143206900, -0.467764000", \ - "0.0185848000, 0.0169921000, 0.0129127000, 0.0017001000, -0.033901700, -0.143406600, -0.468027100", \ - "0.0184656000, 0.0168628000, 0.0129393000, 0.0015417000, -0.034046500, -0.143563200, -0.468160900", \ - "0.0183682000, 0.0167569000, 0.0128441000, 0.0013886000, -0.034169000, -0.143715700, -0.468267900", \ - "0.0224371000, 0.0206312000, 0.0153548000, 0.0018989000, -0.034532400, -0.143667500, -0.468275700"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0195246000, 0.0212325000, 0.0261187000, 0.0398125000, 0.0784220000, 0.1901247000, 0.5109629000", \ - "0.0194757000, 0.0211858000, 0.0260767000, 0.0397680000, 0.0783813000, 0.1900782000, 0.5109366000", \ - "0.0193728000, 0.0210554000, 0.0260143000, 0.0397088000, 0.0783279000, 0.1890428000, 0.5108984000", \ - "0.0192805000, 0.0210035000, 0.0259258000, 0.0396182000, 0.0781349000, 0.1890342000, 0.5132684000", \ - "0.0192522000, 0.0209442000, 0.0257918000, 0.0392405000, 0.0778104000, 0.1887375000, 0.5125034000", \ - "0.0198825000, 0.0214725000, 0.0261208000, 0.0391562000, 0.0775472000, 0.1876921000, 0.5123460000", \ - "0.0204247000, 0.0219352000, 0.0263333000, 0.0397506000, 0.0776173000, 0.1888012000, 0.5090554000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0168716000, 0.0152477000, 0.0116135000, 9.790000e-05, -0.035374200, -0.145059300, -0.469641400", \ - "0.0167630000, 0.0151446000, 0.0111295000, -0.000150400, -0.035664100, -0.145140900, -0.469775500", \ - "0.0167232000, 0.0150974000, 0.0111395000, -0.000291000, -0.035801800, -0.145312800, -0.469949800", \ - "0.0165841000, 0.0149692000, 0.0110009000, -0.000593000, -0.035983800, -0.145513200, -0.470094200", \ - "0.0163600000, 0.0147590000, 0.0108290000, -0.000589300, -0.036059500, -0.145623000, -0.470265200", \ - "0.0164822000, 0.0148450000, 0.0107740000, -0.000556500, -0.036178100, -0.145810200, -0.470423800", \ - "0.0196859000, 0.0178860000, 0.0130021000, 0.0005481000, -0.036433900, -0.145920300, -0.470399900"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0182069000, 0.0199276000, 0.0247794000, 0.0383647000, 0.0768370000, 0.1873695000, 0.5093959000", \ - "0.0182169000, 0.0198736000, 0.0247250000, 0.0383504000, 0.0767943000, 0.1873866000, 0.5101729000", \ - "0.0182178000, 0.0199101000, 0.0247197000, 0.0383393000, 0.0767779000, 0.1875015000, 0.5112123000", \ - "0.0181245000, 0.0198145000, 0.0246853000, 0.0382162000, 0.0766114000, 0.1874855000, 0.5088409000", \ - "0.0178522000, 0.0195295000, 0.0244029000, 0.0378339000, 0.0762051000, 0.1869561000, 0.5098707000", \ - "0.0181764000, 0.0197740000, 0.0243490000, 0.0376639000, 0.0758129000, 0.1859625000, 0.5083931000", \ - "0.0186955000, 0.0201841000, 0.0246392000, 0.0378803000, 0.0762784000, 0.1872944000, 0.5097515000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0147287000, 0.0131523000, 0.0092510000, -0.002096600, -0.037645200, -0.147213000, -0.471822300", \ - "0.0145882000, 0.0129927000, 0.0089946000, -0.002281200, -0.037832200, -0.147376800, -0.471982600", \ - "0.0144200000, 0.0128582000, 0.0088565000, -0.002612400, -0.038040000, -0.147584800, -0.472193100", \ - "0.0142105000, 0.0126272000, 0.0086283000, -0.002867100, -0.038244700, -0.147778200, -0.472392500", \ - "0.0139922000, 0.0123701000, 0.0084604000, -0.002914900, -0.038437400, -0.147884500, -0.472497300", \ - "0.0146375000, 0.0129633000, 0.0090400000, -0.002398700, -0.037694200, -0.147411200, -0.472044400", \ - "0.0199941000, 0.0181307000, 0.0131699000, -0.000360900, -0.037610400, -0.147178600, -0.471724500"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0166805000, 0.0183905000, 0.0232545000, 0.0367607000, 0.0751464000, 0.1866575000, 0.5101072000", \ - "0.0166952000, 0.0184018000, 0.0232684000, 0.0367367000, 0.0751749000, 0.1858639000, 0.5103188000", \ - "0.0166215000, 0.0183180000, 0.0232082000, 0.0368135000, 0.0752206000, 0.1867416000, 0.5102483000", \ - "0.0164822000, 0.0181262000, 0.0229411000, 0.0365009000, 0.0748848000, 0.1847194000, 0.5070803000", \ - "0.0162490000, 0.0178345000, 0.0225980000, 0.0360099000, 0.0744208000, 0.1862972000, 0.5064492000", \ - "0.0163968000, 0.0179769000, 0.0225388000, 0.0359180000, 0.0740848000, 0.1843042000, 0.5068936000", \ - "0.0170617000, 0.0185497000, 0.0228892000, 0.0360764000, 0.0745507000, 0.1855737000, 0.5063344000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0121950000, 0.0110899000, 0.0079976000, -0.002521100, -0.038582500, -0.149828100, -0.475133900", \ - "0.0120397000, 0.0109313000, 0.0078723000, -0.002624800, -0.038708600, -0.149959800, -0.475265400", \ - "0.0117186000, 0.0106702000, 0.0075187000, -0.002957200, -0.039029600, -0.150260600, -0.475559800", \ - "0.0114604000, 0.0103187000, 0.0071061000, -0.003404400, -0.039372800, -0.150525500, -0.475796000", \ - "0.0116827000, 0.0104134000, 0.0070415000, -0.003594200, -0.039514200, -0.150569500, -0.475780500", \ - "0.0151133000, 0.0135460000, 0.0090864000, -0.003805900, -0.039561700, -0.150405700, -0.475516800", \ - "0.0186991000, 0.0170035000, 0.0123798000, -0.000734900, -0.038747400, -0.149698000, -0.474666600"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014567340, 0.0042441490, 0.0123651900, 0.0360256000, 0.1049594000, 0.3057960000"); - values("0.0166768000, 0.0184192000, 0.0234092000, 0.0373998000, 0.0762662000, 0.1872798000, 0.5114883000", \ - "0.0166320000, 0.0183734000, 0.0233798000, 0.0373311000, 0.0762124000, 0.1879533000, 0.5083431000", \ - "0.0165244000, 0.0182446000, 0.0233219000, 0.0372731000, 0.0761084000, 0.1878957000, 0.5110260000", \ - "0.0164523000, 0.0181907000, 0.0231961000, 0.0370558000, 0.0758097000, 0.1876176000, 0.5106893000", \ - "0.0164657000, 0.0181293000, 0.0230351000, 0.0366784000, 0.0752726000, 0.1863299000, 0.5102632000", \ - "0.0177000000, 0.0192243000, 0.0237612000, 0.0367146000, 0.0751444000, 0.1859299000, 0.5079356000", \ - "0.0186175000, 0.0200984000, 0.0245309000, 0.0378899000, 0.0756202000, 0.1869417000, 0.5087437000"); - } - } - max_capacitance : 0.3057960000; - max_transition : 1.5043120000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.4394259000, 0.4488441000, 0.4699933000, 0.5098894000, 0.5834014000, 0.7305930000, 1.0728689000", \ - "0.4434470000, 0.4528603000, 0.4740640000, 0.5138125000, 0.5882501000, 0.7348451000, 1.0773537000", \ - "0.4545036000, 0.4641113000, 0.4849142000, 0.5250109000, 0.5992418000, 0.7456683000, 1.0876221000", \ - "0.4792619000, 0.4888827000, 0.5098318000, 0.5496720000, 0.6238425000, 0.7711345000, 1.1135611000", \ - "0.5318896000, 0.5415756000, 0.5623434000, 0.6022677000, 0.6764862000, 0.8235106000, 1.1664233000", \ - "0.6397756000, 0.6495837000, 0.6704376000, 0.7104997000, 0.7847893000, 0.9323683000, 1.2745089000", \ - "0.8375309000, 0.8481983000, 0.8706363000, 0.9133441000, 0.9913920000, 1.1426683000, 1.4879742000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.1064165000, 0.1128835000, 0.1279495000, 0.1625999000, 0.2485134000, 0.4864429000, 1.1714136000", \ - "0.1111270000, 0.1176291000, 0.1327352000, 0.1672219000, 0.2533201000, 0.4915885000, 1.1770189000", \ - "0.1214221000, 0.1278273000, 0.1429311000, 0.1775336000, 0.2637256000, 0.5020609000, 1.1868212000", \ - "0.1428396000, 0.1492351000, 0.1642246000, 0.1985447000, 0.2844685000, 0.5228316000, 1.2083539000", \ - "0.1853158000, 0.1919780000, 0.2074340000, 0.2418450000, 0.3274037000, 0.5656212000, 1.2513737000", \ - "0.2476011000, 0.2553895000, 0.2726011000, 0.3088024000, 0.3945384000, 0.6320827000, 1.3185207000", \ - "0.3104294000, 0.3205972000, 0.3422717000, 0.3837454000, 0.4729557000, 0.7111379000, 1.3940059000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0514058000, 0.0566369000, 0.0684591000, 0.0922024000, 0.1480696000, 0.2869196000, 0.6866433000", \ - "0.0513256000, 0.0566129000, 0.0684586000, 0.0923160000, 0.1476008000, 0.2876885000, 0.6881165000", \ - "0.0509659000, 0.0562524000, 0.0678456000, 0.0932381000, 0.1484947000, 0.2873590000, 0.6872922000", \ - "0.0509335000, 0.0562635000, 0.0677535000, 0.0921638000, 0.1488891000, 0.2873211000, 0.6876817000", \ - "0.0509199000, 0.0562153000, 0.0680118000, 0.0936247000, 0.1469055000, 0.2871365000, 0.6876876000", \ - "0.0513815000, 0.0562453000, 0.0679105000, 0.0935264000, 0.1478185000, 0.2869135000, 0.6880498000", \ - "0.0581325000, 0.0632751000, 0.0759304000, 0.1004479000, 0.1556167000, 0.2933772000, 0.6893486000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0230456000, 0.0283016000, 0.0420733000, 0.0799343000, 0.1919177000, 0.5241070000, 1.4977997000", \ - "0.0229244000, 0.0282720000, 0.0419951000, 0.0797560000, 0.1918221000, 0.5244001000, 1.5009111000", \ - "0.0228399000, 0.0281099000, 0.0420411000, 0.0796597000, 0.1917684000, 0.5245895000, 1.4995485000", \ - "0.0226457000, 0.0278315000, 0.0417370000, 0.0795518000, 0.1915078000, 0.5250195000, 1.4990340000", \ - "0.0243839000, 0.0294797000, 0.0431361000, 0.0799697000, 0.1913115000, 0.5247799000, 1.4991441000", \ - "0.0299871000, 0.0353199000, 0.0487337000, 0.0841824000, 0.1928069000, 0.5239386000, 1.5010262000", \ - "0.0411322000, 0.0475784000, 0.0614224000, 0.0956523000, 0.1968791000, 0.5250937000, 1.4961117000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.4242383000, 0.4339388000, 0.4547424000, 0.4946908000, 0.5689325000, 0.7153607000, 1.0579121000", \ - "0.4274074000, 0.4370234000, 0.4578164000, 0.4979320000, 0.5721549000, 0.7185815000, 1.0611042000", \ - "0.4375577000, 0.4472783000, 0.4680918000, 0.5080293000, 0.5823139000, 0.7288063000, 1.0713753000", \ - "0.4628162000, 0.4725724000, 0.4931894000, 0.5330413000, 0.6072572000, 0.7546729000, 1.0972316000", \ - "0.5186886000, 0.5282279000, 0.5493108000, 0.5892261000, 0.6634991000, 0.8102801000, 1.1532549000", \ - "0.6409733000, 0.6505643000, 0.6710821000, 0.7109028000, 0.7851393000, 0.9328505000, 1.2752260000", \ - "0.8792523000, 0.8898277000, 0.9126365000, 0.9553602000, 1.0342251000, 1.1863209000, 1.5317644000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.1024966000, 0.1086097000, 0.1229357000, 0.1560731000, 0.2401852000, 0.4771833000, 1.1595861000", \ - "0.1073254000, 0.1134309000, 0.1277464000, 0.1608870000, 0.2449947000, 0.4819990000, 1.1643059000", \ - "0.1173882000, 0.1234809000, 0.1378473000, 0.1709630000, 0.2549529000, 0.4918865000, 1.1745891000", \ - "0.1381310000, 0.1442204000, 0.1584595000, 0.1914330000, 0.2755185000, 0.5117137000, 1.1959823000", \ - "0.1774871000, 0.1838691000, 0.1986568000, 0.2321180000, 0.3162333000, 0.5521343000, 1.2383731000", \ - "0.2312027000, 0.2388114000, 0.2557202000, 0.2911365000, 0.3760590000, 0.6120722000, 1.2985876000", \ - "0.2763935000, 0.2864627000, 0.3080810000, 0.3497423000, 0.4376464000, 0.6742385000, 1.3565958000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0508176000, 0.0568400000, 0.0691411000, 0.0923406000, 0.1486436000, 0.2873883000, 0.6882296000", \ - "0.0509703000, 0.0562750000, 0.0679207000, 0.0932048000, 0.1485326000, 0.2873906000, 0.6898414000", \ - "0.0509277000, 0.0568318000, 0.0691509000, 0.0922417000, 0.1486723000, 0.2873206000, 0.6868651000", \ - "0.0511158000, 0.0566512000, 0.0678205000, 0.0919696000, 0.1470211000, 0.2867944000, 0.6876240000", \ - "0.0512882000, 0.0562094000, 0.0681195000, 0.0920530000, 0.1472729000, 0.2864753000, 0.6869805000", \ - "0.0513815000, 0.0565402000, 0.0682081000, 0.0921753000, 0.1487363000, 0.2864563000, 0.6874805000", \ - "0.0597073000, 0.0650217000, 0.0772398000, 0.1034224000, 0.1595404000, 0.2945540000, 0.6919227000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0214513000, 0.0265240000, 0.0399069000, 0.0771644000, 0.1889429000, 0.5234319000, 1.4980112000", \ - "0.0214514000, 0.0265049000, 0.0399242000, 0.0771621000, 0.1889476000, 0.5233956000, 1.4977659000", \ - "0.0214226000, 0.0265453000, 0.0398682000, 0.0771342000, 0.1889658000, 0.5234121000, 1.4989207000", \ - "0.0212837000, 0.0263358000, 0.0397489000, 0.0768281000, 0.1884580000, 0.5232396000, 1.5001412000", \ - "0.0233600000, 0.0285236000, 0.0415299000, 0.0778826000, 0.1890218000, 0.5217817000, 1.4965001000", \ - "0.0293326000, 0.0345713000, 0.0475044000, 0.0826438000, 0.1906701000, 0.5215273000, 1.4985084000", \ - "0.0412050000, 0.0475193000, 0.0610447000, 0.0942464000, 0.1950909000, 0.5245559000, 1.4947789000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.3908978000, 0.4005266000, 0.4215445000, 0.4611454000, 0.5352597000, 0.6830206000, 1.0253999000", \ - "0.3938251000, 0.4034384000, 0.4243652000, 0.4645068000, 0.5385908000, 0.6849522000, 1.0274428000", \ - "0.4032043000, 0.4129420000, 0.4338793000, 0.4737365000, 0.5477493000, 0.6949846000, 1.0373894000", \ - "0.4276141000, 0.4373870000, 0.4583050000, 0.4980589000, 0.5725792000, 0.7196250000, 1.0608812000", \ - "0.4859637000, 0.4957276000, 0.5166181000, 0.5562657000, 0.6303333000, 0.7774977000, 1.1196973000", \ - "0.6238258000, 0.6334271000, 0.6543129000, 0.6940685000, 0.7682437000, 0.9160158000, 1.2582727000", \ - "0.8950259000, 0.9059566000, 0.9293736000, 0.9741816000, 1.0529860000, 1.2059838000, 1.5514373000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0973213000, 0.1031983000, 0.1170362000, 0.1493208000, 0.2323326000, 0.4679241000, 1.1494412000", \ - "0.1022331000, 0.1080593000, 0.1219041000, 0.1541648000, 0.2370651000, 0.4723216000, 1.1572763000", \ - "0.1125409000, 0.1184001000, 0.1321915000, 0.1644313000, 0.2473680000, 0.4827737000, 1.1678506000", \ - "0.1328839000, 0.1387361000, 0.1525662000, 0.1847116000, 0.2676787000, 0.5033765000, 1.1860486000", \ - "0.1698437000, 0.1761447000, 0.1907564000, 0.2236568000, 0.3067828000, 0.5423332000, 1.2275253000", \ - "0.2171292000, 0.2248126000, 0.2415870000, 0.2771039000, 0.3615238000, 0.5970296000, 1.2807254000", \ - "0.2501486000, 0.2603647000, 0.2824309000, 0.3245632000, 0.4126454000, 0.6483868000, 1.3307198000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0513375000, 0.0568591000, 0.0687784000, 0.0926103000, 0.1480289000, 0.2869631000, 0.6872870000", \ - "0.0509960000, 0.0563303000, 0.0677922000, 0.0927108000, 0.1485541000, 0.2873583000, 0.6901920000", \ - "0.0512557000, 0.0561990000, 0.0677790000, 0.0921447000, 0.1489385000, 0.2876255000, 0.6876619000", \ - "0.0512820000, 0.0562062000, 0.0677454000, 0.0937635000, 0.1485188000, 0.2878911000, 0.6860781000", \ - "0.0512854000, 0.0562055000, 0.0677992000, 0.0925488000, 0.1479133000, 0.2866387000, 0.6891637000", \ - "0.0515069000, 0.0569303000, 0.0679117000, 0.0927758000, 0.1489700000, 0.2871691000, 0.6872925000", \ - "0.0621977000, 0.0679318000, 0.0798309000, 0.1055044000, 0.1608760000, 0.2942355000, 0.6900397000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0202912000, 0.0252317000, 0.0385073000, 0.0756222000, 0.1875874000, 0.5232226000, 1.4972356000", \ - "0.0202847000, 0.0253120000, 0.0384405000, 0.0755140000, 0.1874741000, 0.5225420000, 1.4996744000", \ - "0.0202514000, 0.0251972000, 0.0384395000, 0.0753622000, 0.1873208000, 0.5228967000, 1.4982023000", \ - "0.0202812000, 0.0252578000, 0.0384605000, 0.0754551000, 0.1873507000, 0.5220849000, 1.5005105000", \ - "0.0229248000, 0.0278768000, 0.0407680000, 0.0769558000, 0.1877355000, 0.5226285000, 1.5003448000", \ - "0.0296108000, 0.0348209000, 0.0478065000, 0.0820441000, 0.1898298000, 0.5212455000, 1.4979230000", \ - "0.0416700000, 0.0483482000, 0.0620569000, 0.0954933000, 0.1949014000, 0.5238235000, 1.4916386000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.3352405000, 0.3448771000, 0.3657867000, 0.4057107000, 0.4799005000, 0.6272959000, 0.9698311000", \ - "0.3371093000, 0.3467544000, 0.3675860000, 0.4076964000, 0.4817963000, 0.6291433000, 0.9715809000", \ - "0.3444275000, 0.3542149000, 0.3750764000, 0.4150646000, 0.4892844000, 0.6367242000, 0.9792517000", \ - "0.3671801000, 0.3767319000, 0.3978673000, 0.4377901000, 0.5121370000, 0.6596740000, 1.0020624000", \ - "0.4283404000, 0.4379449000, 0.4587739000, 0.4986525000, 0.5726364000, 0.7191648000, 1.0615573000", \ - "0.5762192000, 0.5850317000, 0.6056481000, 0.6455870000, 0.7187736000, 0.8662815000, 1.2086707000", \ - "0.8724720000, 0.8839831000, 0.9086946000, 0.9536699000, 1.0312196000, 1.1804884000, 1.5255396000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0848826000, 0.0904991000, 0.1039026000, 0.1353699000, 0.2176623000, 0.4532807000, 1.1352966000", \ - "0.0897830000, 0.0954059000, 0.1088135000, 0.1403064000, 0.2228096000, 0.4578813000, 1.1392546000", \ - "0.1003030000, 0.1059088000, 0.1193311000, 0.1509098000, 0.2334103000, 0.4684415000, 1.1509111000", \ - "0.1211068000, 0.1266428000, 0.1400004000, 0.1714489000, 0.2539507000, 0.4893709000, 1.1833701000", \ - "0.1557883000, 0.1619271000, 0.1764317000, 0.2090556000, 0.2918044000, 0.5279076000, 1.2213115000", \ - "0.1960053000, 0.2039134000, 0.2209798000, 0.2565883000, 0.3406498000, 0.5758838000, 1.2599072000", \ - "0.2152377000, 0.2259916000, 0.2491777000, 0.2929596000, 0.3813832000, 0.6172222000, 1.2987869000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0509284000, 0.0565619000, 0.0676859000, 0.0938254000, 0.1468159000, 0.2867977000, 0.6875952000", \ - "0.0508016000, 0.0566697000, 0.0677815000, 0.0932364000, 0.1487985000, 0.2869197000, 0.6876339000", \ - "0.0512713000, 0.0561666000, 0.0676610000, 0.0935370000, 0.1487685000, 0.2867829000, 0.6876175000", \ - "0.0513894000, 0.0561830000, 0.0677998000, 0.0937012000, 0.1488700000, 0.2868119000, 0.6876044000", \ - "0.0515427000, 0.0563302000, 0.0682722000, 0.0923543000, 0.1476033000, 0.2877183000, 0.6875649000", \ - "0.0499138000, 0.0569536000, 0.0682145000, 0.0931122000, 0.1484903000, 0.2877854000, 0.6877325000", \ - "0.0679906000, 0.0734789000, 0.0856937000, 0.1082264000, 0.1571620000, 0.2918532000, 0.6912532000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0191009000, 0.0239906000, 0.0369274000, 0.0739494000, 0.1862658000, 0.5222206000, 1.5004682000", \ - "0.0190759000, 0.0239407000, 0.0368702000, 0.0740280000, 0.1862672000, 0.5214398000, 1.5043121000", \ - "0.0191319000, 0.0240390000, 0.0369550000, 0.0739536000, 0.1866035000, 0.5229656000, 1.5025541000", \ - "0.0193535000, 0.0242685000, 0.0371665000, 0.0740089000, 0.1860508000, 0.5213768000, 1.4987049000", \ - "0.0226924000, 0.0277531000, 0.0404229000, 0.0761006000, 0.1869866000, 0.5231635000, 1.5033215000", \ - "0.0306036000, 0.0357691000, 0.0484279000, 0.0822032000, 0.1891021000, 0.5207006000, 1.5007294000", \ - "0.0442801000, 0.0514083000, 0.0655881000, 0.0982716000, 0.1956619000, 0.5230779000, 1.4935555000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0843091000, 0.0888506000, 0.0995313000, 0.1223360000, 0.1736354000, 0.2951914000, 0.6184882000", \ - "0.0898301000, 0.0944189000, 0.1050059000, 0.1278078000, 0.1791294000, 0.3006732000, 0.6243664000", \ - "0.1029912000, 0.1075858000, 0.1180274000, 0.1409239000, 0.1922341000, 0.3137987000, 0.6375007000", \ - "0.1357666000, 0.1403468000, 0.1508117000, 0.1737009000, 0.2252097000, 0.3468650000, 0.6705977000", \ - "0.2055350000, 0.2106698000, 0.2221231000, 0.2460610000, 0.2982539000, 0.4204434000, 0.7440630000", \ - "0.3209331000, 0.3277399000, 0.3427087000, 0.3726440000, 0.4326944000, 0.5604048000, 0.8845791000", \ - "0.5084015000, 0.5171536000, 0.5369551000, 0.5758716000, 0.6516423000, 0.7956750000, 1.1249874000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0949678000, 0.1013553000, 0.1164076000, 0.1510095000, 0.2370441000, 0.4752327000, 1.1605248000", \ - "0.0990552000, 0.1055006000, 0.1205209000, 0.1553173000, 0.2415478000, 0.4798559000, 1.1647968000", \ - "0.1093111000, 0.1157392000, 0.1308184000, 0.1653147000, 0.2514826000, 0.4898549000, 1.1749890000", \ - "0.1351048000, 0.1414806000, 0.1562469000, 0.1903023000, 0.2760097000, 0.5144061000, 1.1994780000", \ - "0.1841332000, 0.1906482000, 0.2056510000, 0.2398013000, 0.3247568000, 0.5627940000, 1.2488037000", \ - "0.2463930000, 0.2540424000, 0.2709027000, 0.3058983000, 0.3912982000, 0.6288582000, 1.3136937000", \ - "0.3060923000, 0.3163431000, 0.3378512000, 0.3781025000, 0.4636916000, 0.7012235000, 1.3855267000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0166728000, 0.0199772000, 0.0280359000, 0.0489644000, 0.1026999000, 0.2417216000, 0.6619638000", \ - "0.0166927000, 0.0199257000, 0.0280345000, 0.0489998000, 0.1029224000, 0.2418542000, 0.6629263000", \ - "0.0165580000, 0.0199164000, 0.0280062000, 0.0488247000, 0.1027904000, 0.2419008000, 0.6629943000", \ - "0.0167579000, 0.0199787000, 0.0281955000, 0.0490216000, 0.1028547000, 0.2415721000, 0.6627995000", \ - "0.0210969000, 0.0241319000, 0.0320644000, 0.0519605000, 0.1042771000, 0.2425787000, 0.6626338000", \ - "0.0307389000, 0.0348153000, 0.0444766000, 0.0659182000, 0.1174496000, 0.2497037000, 0.6664623000", \ - "0.0466407000, 0.0521227000, 0.0637591000, 0.0901452000, 0.1483986000, 0.2753866000, 0.6643783000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014567300, 0.0042441500, 0.0123652000, 0.0360256000, 0.1049590000, 0.3057960000"); - values("0.0228656000, 0.0281685000, 0.0419454000, 0.0797525000, 0.1918322000, 0.5236748000, 1.5002346000", \ - "0.0228462000, 0.0280904000, 0.0419985000, 0.0796950000, 0.1916288000, 0.5246199000, 1.4991265000", \ - "0.0228008000, 0.0280953000, 0.0418369000, 0.0796809000, 0.1914584000, 0.5249089000, 1.4982305000", \ - "0.0223141000, 0.0276112000, 0.0412905000, 0.0791173000, 0.1909933000, 0.5248816000, 1.4989255000", \ - "0.0244099000, 0.0295328000, 0.0427496000, 0.0799557000, 0.1910337000, 0.5246527000, 1.4979676000", \ - "0.0316983000, 0.0363386000, 0.0483818000, 0.0835193000, 0.1923314000, 0.5243153000, 1.5004182000", \ - "0.0437471000, 0.0500274000, 0.0626547000, 0.0937246000, 0.1952704000, 0.5267526000, 1.4981918000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41a_4") { - leakage_power () { - value : 0.0078470000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0048416000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0083431000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0054212000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0068856000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0054212000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0049030000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0054225000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0066887000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0054209000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0048914000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0054218000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0048945000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0054189000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0047815000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0054229000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0060117000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0054212000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0048222000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0054182000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0051636000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0054218000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0077229000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0054226000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0048391000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0054212000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0050057000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0054252000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0446182000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0054272000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0076984000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0054248000; - when : "A1&A2&A3&A4&!B1"; - } - area : 21.270400000; - cell_footprint : "sky130_fd_sc_hd__o41a"; - cell_leakage_power : 0.0069153160; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080646000, 0.0080569000, 0.0080392000, 0.0080422000, 0.0080492000, 0.0080654000, 0.0081028000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008021600, -0.008019300, -0.008013800, -0.008010300, -0.008002100, -0.007983300, -0.007939900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046820000; - } - pin ("A2") { - capacitance : 0.0044620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041540000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080316000, 0.0080303000, 0.0080273000, 0.0080288000, 0.0080320000, 0.0080394000, 0.0080567000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.008003900, -0.008001300, -0.007995200, -0.007993900, -0.007990900, -0.007984000, -0.007968100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0047700000; - } - pin ("A3") { - capacitance : 0.0041920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0038750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079123000, 0.0079071000, 0.0078952000, 0.0078955000, 0.0078960000, 0.0078971000, 0.0079000000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007889800, -0.007884800, -0.007873400, -0.007872500, -0.007870300, -0.007865400, -0.007854000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045090000; - } - pin ("A4") { - capacitance : 0.0042080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0038560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078895000, 0.0078851000, 0.0078750000, 0.0078757000, 0.0078773000, 0.0078810000, 0.0078895000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007856100, -0.007853800, -0.007848600, -0.007844900, -0.007836300, -0.007816400, -0.007770500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045590000; - } - pin ("B1") { - capacitance : 0.0044470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0093262000, 0.0093268000, 0.0093283000, 0.0093259000, 0.0093206000, 0.0093083000, 0.0092799000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000791800, -0.000838700, -0.000946600, -0.000884800, -0.000742200, -0.000413600, 0.0003440000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045900000; - } - pin ("X") { - direction : "output"; - function : "(A1&B1) | (A2&B1) | (A3&B1) | (A4&B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0439783000, 0.0420588000, 0.0363499000, 0.0206423000, -0.032700900, -0.216793700, -0.822394600", \ - "0.0434283000, 0.0414422000, 0.0358783000, 0.0201095000, -0.033098600, -0.216902800, -0.822340600", \ - "0.0430692000, 0.0411515000, 0.0356104000, 0.0198103000, -0.033166600, -0.217192500, -0.823002300", \ - "0.0428186000, 0.0408255000, 0.0352140000, 0.0194362000, -0.033823700, -0.217613300, -0.823036100", \ - "0.0425683000, 0.0406415000, 0.0350768000, 0.0192229000, -0.034028800, -0.218092300, -0.823637700", \ - "0.0423393000, 0.0403639000, 0.0347474000, 0.0188939000, -0.034320300, -0.218315600, -0.823822900", \ - "0.0492557000, 0.0471022000, 0.0407517000, 0.0218911000, -0.035200600, -0.218704500, -0.824031100"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0403625000, 0.0423646000, 0.0487949000, 0.0687762000, 0.1295633000, 0.3183138000, 0.9190766000", \ - "0.0400714000, 0.0421021000, 0.0485029000, 0.0685753000, 0.1294449000, 0.3183636000, 0.9183605000", \ - "0.0398104000, 0.0417908000, 0.0482347000, 0.0682545000, 0.1290435000, 0.3181637000, 0.9185025000", \ - "0.0394890000, 0.0414731000, 0.0479014000, 0.0680668000, 0.1287064000, 0.3173079000, 0.9228043000", \ - "0.0398670000, 0.0418956000, 0.0482104000, 0.0678781000, 0.1281317000, 0.3170033000, 0.9183726000", \ - "0.0419722000, 0.0437768000, 0.0496679000, 0.0682533000, 0.1275311000, 0.3155306000, 0.9172893000", \ - "0.0437613000, 0.0454915000, 0.0512630000, 0.0695798000, 0.1282973000, 0.3173296000, 0.9207710000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0390438000, 0.0370633000, 0.0315110000, 0.0157321000, -0.037645600, -0.221546700, -0.827086800", \ - "0.0385463000, 0.0365789000, 0.0309455000, 0.0156753000, -0.037640600, -0.221778300, -0.827494900", \ - "0.0382374000, 0.0363316000, 0.0306724000, 0.0149397000, -0.038343900, -0.222106100, -0.827604400", \ - "0.0378451000, 0.0359278000, 0.0303863000, 0.0145842000, -0.038396900, -0.222427800, -0.828214400", \ - "0.0375523000, 0.0358627000, 0.0301477000, 0.0144437000, -0.038937600, -0.223019900, -0.828435300", \ - "0.0375658000, 0.0360522000, 0.0301556000, 0.0142912000, -0.039183400, -0.223172000, -0.828700900", \ - "0.0452374000, 0.0431158000, 0.0367460000, 0.0177181000, -0.040324100, -0.223202200, -0.828618300"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0380630000, 0.0400615000, 0.0463119000, 0.0658966000, 0.1257634000, 0.3143191000, 0.9143748000", \ - "0.0380200000, 0.0400728000, 0.0462863000, 0.0658658000, 0.1257283000, 0.3142796000, 0.9144596000", \ - "0.0379782000, 0.0399219000, 0.0462261000, 0.0657185000, 0.1256797000, 0.3138374000, 0.9148175000", \ - "0.0376877000, 0.0396593000, 0.0459457000, 0.0655247000, 0.1253555000, 0.3134844000, 0.9149345000", \ - "0.0374958000, 0.0394235000, 0.0456765000, 0.0647142000, 0.1247714000, 0.3132616000, 0.9182063000", \ - "0.0389490000, 0.0407544000, 0.0466183000, 0.0654256000, 0.1240667000, 0.3119548000, 0.9128569000", \ - "0.0405450000, 0.0423042000, 0.0479534000, 0.0665072000, 0.1247702000, 0.3133675000, 0.9119709000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0343739000, 0.0324025000, 0.0268763000, 0.0110654000, -0.041872400, -0.225945300, -0.831625100", \ - "0.0342880000, 0.0322979000, 0.0266566000, 0.0109307000, -0.042362200, -0.226300700, -0.831842300", \ - "0.0337146000, 0.0318592000, 0.0262641000, 0.0104792000, -0.042734800, -0.226501200, -0.832214100", \ - "0.0334191000, 0.0314438000, 0.0258575000, 0.0100850000, -0.043179200, -0.226927900, -0.832288900", \ - "0.0329216000, 0.0310751000, 0.0255115000, 0.0097958000, -0.043366900, -0.227558300, -0.832903100", \ - "0.0331044000, 0.0311562000, 0.0259851000, 0.0099536000, -0.043370500, -0.227600000, -0.833159100", \ - "0.0423261000, 0.0401158000, 0.0335169000, 0.0141243000, -0.043586700, -0.227409700, -0.832938000"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0358202000, 0.0377941000, 0.0439090000, 0.0632301000, 0.1228587000, 0.3107045000, 0.9105037000", \ - "0.0358626000, 0.0378245000, 0.0440044000, 0.0632952000, 0.1229186000, 0.3107838000, 0.9112044000", \ - "0.0356858000, 0.0376373000, 0.0438611000, 0.0632530000, 0.1228485000, 0.3108195000, 0.9109318000", \ - "0.0354400000, 0.0374106000, 0.0435856000, 0.0629445000, 0.1224129000, 0.3107541000, 0.9151230000", \ - "0.0352527000, 0.0371666000, 0.0432604000, 0.0621232000, 0.1217293000, 0.3097939000, 0.9109627000", \ - "0.0356026000, 0.0374393000, 0.0434128000, 0.0619765000, 0.1208833000, 0.3079884000, 0.9133936000", \ - "0.0370423000, 0.0387471000, 0.0445285000, 0.0626394000, 0.1220228000, 0.3101518000, 0.9072910000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0296892000, 0.0277885000, 0.0221692000, 0.0064379000, -0.046818000, -0.230654100, -0.836031400", \ - "0.0294191000, 0.0274772000, 0.0218150000, 0.0061055000, -0.047102100, -0.231015600, -0.836423000", \ - "0.0290284000, 0.0270384000, 0.0214279000, 0.0057453000, -0.047487200, -0.231538900, -0.836995600", \ - "0.0284552000, 0.0264498000, 0.0208321000, 0.0052342000, -0.047985500, -0.231930400, -0.837501200", \ - "0.0282014000, 0.0262540000, 0.0206234000, 0.0049771000, -0.048299200, -0.232209100, -0.837777300", \ - "0.0287623000, 0.0267884000, 0.0212183000, 0.0054041000, -0.047528200, -0.231720600, -0.837305500", \ - "0.0414128000, 0.0392017000, 0.0325931000, 0.0123139000, -0.045360400, -0.229491200, -0.835169600"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0315990000, 0.0335710000, 0.0396948000, 0.0590487000, 0.1185276000, 0.3058755000, 0.9063555000", \ - "0.0316010000, 0.0335699000, 0.0397859000, 0.0590165000, 0.1185418000, 0.3058158000, 0.9077790000", \ - "0.0314515000, 0.0333929000, 0.0395825000, 0.0590017000, 0.1183955000, 0.3059716000, 0.9023346000", \ - "0.0311171000, 0.0330875000, 0.0392372000, 0.0584656000, 0.1179035000, 0.3044266000, 0.9021256000", \ - "0.0306301000, 0.0325638000, 0.0387374000, 0.0577178000, 0.1169476000, 0.3053911000, 0.9069618000", \ - "0.0311787000, 0.0330438000, 0.0388764000, 0.0576232000, 0.1160474000, 0.3031590000, 0.9059032000", \ - "0.0325830000, 0.0342665000, 0.0401550000, 0.0583728000, 0.1177410000, 0.3053359000, 0.9019621000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0254726000, 0.0241533000, 0.0203355000, 0.0064708000, -0.046689300, -0.234649700, -0.841895400", \ - "0.0251286000, 0.0238630000, 0.0200237000, 0.0061532000, -0.046977400, -0.234932000, -0.842180700", \ - "0.0246352000, 0.0232545000, 0.0193606000, 0.0055166000, -0.047467300, -0.235383100, -0.842616900", \ - "0.0240316000, 0.0229461000, 0.0187083000, 0.0047399000, -0.048228900, -0.235957500, -0.843130200", \ - "0.0236742000, 0.0222067000, 0.0178812000, 0.0035650000, -0.049019500, -0.236335700, -0.843307400", \ - "0.0318221000, 0.0300103000, 0.0243323000, 0.0064947000, -0.049059900, -0.235612500, -0.842428500", \ - "0.0399853000, 0.0380160000, 0.0320851000, 0.0135664000, -0.044686800, -0.233268900, -0.839268800"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016038890, 0.0051449210, 0.0165037700, 0.0529404200, 0.1698211000, 0.5447486000"); - values("0.0331971000, 0.0351517000, 0.0416173000, 0.0617114000, 0.1225435000, 0.3114694000, 0.9164569000", \ - "0.0330519000, 0.0349976000, 0.0414698000, 0.0615522000, 0.1223706000, 0.3113037000, 0.9162728000", \ - "0.0328083000, 0.0348558000, 0.0412755000, 0.0613813000, 0.1221784000, 0.3111827000, 0.9117541000", \ - "0.0326575000, 0.0346367000, 0.0410446000, 0.0610449000, 0.1217241000, 0.3106129000, 0.9121651000", \ - "0.0327938000, 0.0347461000, 0.0409619000, 0.0605559000, 0.1207347000, 0.3095516000, 0.9150723000", \ - "0.0353410000, 0.0371317000, 0.0430159000, 0.0612612000, 0.1207518000, 0.3083159000, 0.9151623000", \ - "0.0379209000, 0.0401051000, 0.0457781000, 0.0642517000, 0.1224170000, 0.3104794000, 0.9103267000"); - } - } - max_capacitance : 0.5447490000; - max_transition : 1.5032640000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.4460322000, 0.4519886000, 0.4675211000, 0.5014674000, 0.5699773000, 0.7134920000, 1.0631832000", \ - "0.4497962000, 0.4558108000, 0.4714082000, 0.5052580000, 0.5740716000, 0.7167658000, 1.0665929000", \ - "0.4610607000, 0.4667726000, 0.4825044000, 0.5164446000, 0.5845542000, 0.7282804000, 1.0777331000", \ - "0.4870039000, 0.4930262000, 0.5084254000, 0.5424898000, 0.6109259000, 0.7538081000, 1.1037488000", \ - "0.5419073000, 0.5479038000, 0.5635211000, 0.5974554000, 0.6659818000, 0.8090536000, 1.1580749000", \ - "0.6532471000, 0.6592472000, 0.6747865000, 0.7087438000, 0.7773094000, 0.9207025000, 1.2704546000", \ - "0.8557954000, 0.8621984000, 0.8788715000, 0.9149967000, 0.9869221000, 1.1352312000, 1.4885694000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.1170069000, 0.1215445000, 0.1338094000, 0.1642170000, 0.2429642000, 0.4725256000, 1.1898970000", \ - "0.1214504000, 0.1259674000, 0.1382323000, 0.1686346000, 0.2472977000, 0.4769404000, 1.1948121000", \ - "0.1312368000, 0.1357535000, 0.1479816000, 0.1783599000, 0.2569832000, 0.4857461000, 1.2054413000", \ - "0.1510106000, 0.1555515000, 0.1676887000, 0.1979555000, 0.2761217000, 0.5059154000, 1.2250447000", \ - "0.1913350000, 0.1959015000, 0.2082371000, 0.2383304000, 0.3162982000, 0.5451249000, 1.2622823000", \ - "0.2514433000, 0.2565593000, 0.2700352000, 0.3016992000, 0.3800912000, 0.6084176000, 1.3284666000", \ - "0.3115759000, 0.3181081000, 0.3348453000, 0.3712956000, 0.4522452000, 0.6804983000, 1.3983329000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0531609000, 0.0565111000, 0.0645686000, 0.0846616000, 0.1341176000, 0.2673334000, 0.6724763000", \ - "0.0527596000, 0.0560011000, 0.0649656000, 0.0848552000, 0.1342564000, 0.2672857000, 0.6733554000", \ - "0.0530293000, 0.0562082000, 0.0646823000, 0.0849191000, 0.1354189000, 0.2671171000, 0.6734683000", \ - "0.0531124000, 0.0560247000, 0.0653036000, 0.0853508000, 0.1356062000, 0.2673917000, 0.6719931000", \ - "0.0528121000, 0.0560890000, 0.0652111000, 0.0848319000, 0.1343800000, 0.2675550000, 0.6735683000", \ - "0.0528112000, 0.0560622000, 0.0646741000, 0.0848628000, 0.1343545000, 0.2674743000, 0.6722591000", \ - "0.0598538000, 0.0628591000, 0.0723148000, 0.0927517000, 0.1448058000, 0.2734464000, 0.6771499000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0261837000, 0.0298409000, 0.0405339000, 0.0710954000, 0.1676810000, 0.4822021000, 1.5007117000", \ - "0.0262293000, 0.0297414000, 0.0404969000, 0.0709349000, 0.1676666000, 0.4827144000, 1.4984134000", \ - "0.0260961000, 0.0297288000, 0.0402856000, 0.0710790000, 0.1673650000, 0.4828702000, 1.5006698000", \ - "0.0257904000, 0.0294179000, 0.0398831000, 0.0707435000, 0.1670675000, 0.4825699000, 1.5026804000", \ - "0.0270473000, 0.0306736000, 0.0410710000, 0.0708341000, 0.1665882000, 0.4814569000, 1.5015600000", \ - "0.0318055000, 0.0354000000, 0.0458847000, 0.0746605000, 0.1680678000, 0.4810743000, 1.5015368000", \ - "0.0429491000, 0.0469663000, 0.0580433000, 0.0849795000, 0.1727201000, 0.4828208000, 1.5003134000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.4258368000, 0.4316786000, 0.4474010000, 0.4814196000, 0.5499479000, 0.6932312000, 1.0418882000", \ - "0.4282430000, 0.4342410000, 0.4497539000, 0.4835377000, 0.5523051000, 0.6958131000, 1.0454223000", \ - "0.4376611000, 0.4436854000, 0.4591184000, 0.4932725000, 0.5616989000, 0.7045083000, 1.0544345000", \ - "0.4609423000, 0.4666608000, 0.4823879000, 0.5163096000, 0.5843776000, 0.7281055000, 1.0775832000", \ - "0.5124691000, 0.5184487000, 0.5339362000, 0.5679238000, 0.6364815000, 0.7798074000, 1.1287934000", \ - "0.6246329000, 0.6307632000, 0.6462929000, 0.6803469000, 0.7489669000, 0.8925095000, 1.2420894000", \ - "0.8357137000, 0.8422531000, 0.8593117000, 0.8965426000, 0.9698656000, 1.1187065000, 1.4733565000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.1074683000, 0.1116083000, 0.1227794000, 0.1510753000, 0.2260052000, 0.4519218000, 1.1669866000", \ - "0.1122534000, 0.1163901000, 0.1276129000, 0.1558746000, 0.2307931000, 0.4567370000, 1.1720462000", \ - "0.1220451000, 0.1261782000, 0.1374434000, 0.1656684000, 0.2406947000, 0.4673350000, 1.1826309000", \ - "0.1415334000, 0.1456577000, 0.1568256000, 0.1849578000, 0.2598884000, 0.4865582000, 1.2021963000", \ - "0.1786485000, 0.1829413000, 0.1944777000, 0.2230273000, 0.2979799000, 0.5240171000, 1.2421553000", \ - "0.2297966000, 0.2347339000, 0.2474873000, 0.2776716000, 0.3536867000, 0.5794319000, 1.2988502000", \ - "0.2712223000, 0.2776510000, 0.2939002000, 0.3298389000, 0.4085896000, 0.6349403000, 1.3504854000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0527665000, 0.0564636000, 0.0653370000, 0.0861735000, 0.1345033000, 0.2673622000, 0.6736801000", \ - "0.0530818000, 0.0564181000, 0.0653109000, 0.0854497000, 0.1345728000, 0.2675729000, 0.6711371000", \ - "0.0530387000, 0.0559449000, 0.0653080000, 0.0854564000, 0.1359679000, 0.2675450000, 0.6729775000", \ - "0.0530263000, 0.0562030000, 0.0646892000, 0.0849079000, 0.1353329000, 0.2671809000, 0.6734902000", \ - "0.0527839000, 0.0564768000, 0.0646741000, 0.0860251000, 0.1341607000, 0.2672208000, 0.6732760000", \ - "0.0532201000, 0.0565904000, 0.0649693000, 0.0851975000, 0.1342992000, 0.2675332000, 0.6732490000", \ - "0.0619342000, 0.0654406000, 0.0750254000, 0.0969188000, 0.1452747000, 0.2770273000, 0.6781026000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0234745000, 0.0268233000, 0.0369903000, 0.0665242000, 0.1623492000, 0.4794063000, 1.4982259000", \ - "0.0234522000, 0.0268500000, 0.0369563000, 0.0665311000, 0.1623008000, 0.4794299000, 1.4988061000", \ - "0.0234559000, 0.0268106000, 0.0368405000, 0.0666464000, 0.1625316000, 0.4785973000, 1.5005908000", \ - "0.0233835000, 0.0267733000, 0.0367347000, 0.0664880000, 0.1624457000, 0.4785913000, 1.5016596000", \ - "0.0249934000, 0.0285249000, 0.0381929000, 0.0674760000, 0.1624895000, 0.4787927000, 1.5020364000", \ - "0.0306412000, 0.0340516000, 0.0439670000, 0.0717374000, 0.1645770000, 0.4783839000, 1.4988633000", \ - "0.0422334000, 0.0461022000, 0.0566501000, 0.0838695000, 0.1696827000, 0.4799056000, 1.4974968000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.3898703000, 0.3958698000, 0.4114748000, 0.4454841000, 0.5137991000, 0.6573499000, 1.0069851000", \ - "0.3921682000, 0.3981758000, 0.4137470000, 0.4477632000, 0.5163208000, 0.6596308000, 1.0081360000", \ - "0.4008693000, 0.4068915000, 0.4223717000, 0.4562785000, 0.5250438000, 0.6681272000, 1.0177367000", \ - "0.4239917000, 0.4300004000, 0.4455681000, 0.4794123000, 0.5481104000, 0.6907360000, 1.0406471000", \ - "0.4787056000, 0.4846768000, 0.5002834000, 0.5341958000, 0.6024069000, 0.7457555000, 1.0951123000", \ - "0.6082217000, 0.6143460000, 0.6296175000, 0.6635854000, 0.7321386000, 0.8756052000, 1.2251206000", \ - "0.8566788000, 0.8634338000, 0.8809641000, 0.9187390000, 0.9924385000, 1.1418256000, 1.4965027000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.1054513000, 0.1094580000, 0.1203034000, 0.1478108000, 0.2214556000, 0.4462439000, 1.1645130000", \ - "0.1102978000, 0.1143137000, 0.1251828000, 0.1527095000, 0.2265219000, 0.4521318000, 1.1657649000", \ - "0.1203056000, 0.1242890000, 0.1351563000, 0.1627457000, 0.2365586000, 0.4622025000, 1.1762500000", \ - "0.1400263000, 0.1440252000, 0.1548673000, 0.1823776000, 0.2561422000, 0.4810755000, 1.1980832000", \ - "0.1762355000, 0.1804856000, 0.1917942000, 0.2199164000, 0.2942126000, 0.5195284000, 1.2350344000", \ - "0.2229555000, 0.2279549000, 0.2409449000, 0.2713624000, 0.3469264000, 0.5720742000, 1.2908840000", \ - "0.2550577000, 0.2616631000, 0.2786782000, 0.3151956000, 0.3952305000, 0.6204004000, 1.3361368000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0530171000, 0.0563731000, 0.0646378000, 0.0848557000, 0.1348824000, 0.2676135000, 0.6715721000", \ - "0.0527211000, 0.0560719000, 0.0645700000, 0.0863208000, 0.1344648000, 0.2673699000, 0.6735265000", \ - "0.0529950000, 0.0562904000, 0.0648267000, 0.0848825000, 0.1340922000, 0.2670450000, 0.6730036000", \ - "0.0527383000, 0.0559932000, 0.0650580000, 0.0848745000, 0.1347147000, 0.2674853000, 0.6719336000", \ - "0.0532752000, 0.0565950000, 0.0646006000, 0.0850097000, 0.1348441000, 0.2668804000, 0.6731314000", \ - "0.0532610000, 0.0565712000, 0.0657878000, 0.0869842000, 0.1347773000, 0.2678076000, 0.6730706000", \ - "0.0658138000, 0.0692338000, 0.0778928000, 0.0987029000, 0.1475351000, 0.2769986000, 0.6778836000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0224415000, 0.0257493000, 0.0355794000, 0.0650219000, 0.1604506000, 0.4775591000, 1.5001380000", \ - "0.0224495000, 0.0257956000, 0.0356328000, 0.0651573000, 0.1605694000, 0.4787197000, 1.4984257000", \ - "0.0224976000, 0.0257958000, 0.0356377000, 0.0651633000, 0.1606354000, 0.4788505000, 1.4995934000", \ - "0.0224270000, 0.0257248000, 0.0357101000, 0.0651478000, 0.1608696000, 0.4785962000, 1.5024605000", \ - "0.0246893000, 0.0280560000, 0.0378781000, 0.0668346000, 0.1610973000, 0.4791171000, 1.5010397000", \ - "0.0309581000, 0.0347503000, 0.0443675000, 0.0718159000, 0.1636560000, 0.4775063000, 1.4984801000", \ - "0.0435880000, 0.0476591000, 0.0584437000, 0.0851800000, 0.1698472000, 0.4798442000, 1.4975327000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.3183442000, 0.3242281000, 0.3400256000, 0.3738921000, 0.4425905000, 0.5856670000, 0.9355270000", \ - "0.3198367000, 0.3258696000, 0.3414250000, 0.3754900000, 0.4440605000, 0.5870420000, 0.9370527000", \ - "0.3263274000, 0.3323077000, 0.3479716000, 0.3820110000, 0.4506076000, 0.5938992000, 0.9429654000", \ - "0.3473613000, 0.3534007000, 0.3687377000, 0.4027371000, 0.4714506000, 0.6148227000, 0.9644536000", \ - "0.4054137000, 0.4113994000, 0.4269095000, 0.4609297000, 0.5294972000, 0.6732119000, 1.0226120000", \ - "0.5480916000, 0.5537593000, 0.5687782000, 0.6020763000, 0.6689054000, 0.8122237000, 1.1620221000", \ - "0.8216861000, 0.8287880000, 0.8471848000, 0.8854573000, 0.9566201000, 1.1002005000, 1.4535849000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0905773000, 0.0944103000, 0.1048869000, 0.1317671000, 0.2046523000, 0.4296258000, 1.1422416000", \ - "0.0954168000, 0.0992766000, 0.1097961000, 0.1366371000, 0.2095107000, 0.4334286000, 1.1516151000", \ - "0.1056008000, 0.1094434000, 0.1199465000, 0.1468976000, 0.2197758000, 0.4439794000, 1.1598087000", \ - "0.1257952000, 0.1296150000, 0.1400757000, 0.1669148000, 0.2396922000, 0.4637771000, 1.1785418000", \ - "0.1590401000, 0.1633071000, 0.1745545000, 0.2025172000, 0.2762048000, 0.5006867000, 1.2147990000", \ - "0.1971469000, 0.2023664000, 0.2157653000, 0.2465809000, 0.3219593000, 0.5467042000, 1.2625015000", \ - "0.2134756000, 0.2204485000, 0.2381255000, 0.2768072000, 0.3581948000, 0.5830144000, 1.2978342000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0531094000, 0.0562611000, 0.0649954000, 0.0848952000, 0.1346227000, 0.2673708000, 0.6730666000", \ - "0.0530745000, 0.0559685000, 0.0654039000, 0.0852200000, 0.1360530000, 0.2674019000, 0.6726900000", \ - "0.0529407000, 0.0562908000, 0.0645191000, 0.0863997000, 0.1336662000, 0.2673499000, 0.6735383000", \ - "0.0528058000, 0.0561378000, 0.0648991000, 0.0853310000, 0.1342562000, 0.2673582000, 0.6715014000", \ - "0.0532231000, 0.0564456000, 0.0653528000, 0.0848352000, 0.1342954000, 0.2673648000, 0.6730859000", \ - "0.0516001000, 0.0549920000, 0.0638440000, 0.0835072000, 0.1353756000, 0.2678434000, 0.6729035000", \ - "0.0717438000, 0.0752958000, 0.0840183000, 0.1026138000, 0.1466097000, 0.2733901000, 0.6766001000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0211031000, 0.0245017000, 0.0341983000, 0.0633566000, 0.1594554000, 0.4779632000, 1.4991096000", \ - "0.0211562000, 0.0244040000, 0.0340964000, 0.0633348000, 0.1594673000, 0.4784551000, 1.5030981000", \ - "0.0212118000, 0.0245297000, 0.0341119000, 0.0635042000, 0.1595106000, 0.4765380000, 1.4994489000", \ - "0.0214916000, 0.0246625000, 0.0343310000, 0.0634567000, 0.1594146000, 0.4763225000, 1.4946753000", \ - "0.0248459000, 0.0280111000, 0.0374507000, 0.0660677000, 0.1603468000, 0.4787347000, 1.5002236000", \ - "0.0325663000, 0.0361027000, 0.0454116000, 0.0726753000, 0.1634968000, 0.4758024000, 1.5030533000", \ - "0.0470376000, 0.0514442000, 0.0627320000, 0.0893341000, 0.1714039000, 0.4792640000, 1.4940441000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0789005000, 0.0817451000, 0.0893510000, 0.1078132000, 0.1527552000, 0.2680574000, 0.5930092000", \ - "0.0840946000, 0.0869825000, 0.0945828000, 0.1130521000, 0.1580298000, 0.2733402000, 0.5980763000", \ - "0.0971666000, 0.0999857000, 0.1075347000, 0.1260263000, 0.1710622000, 0.2864023000, 0.6112640000", \ - "0.1284865000, 0.1312572000, 0.1387862000, 0.1573635000, 0.2021853000, 0.3180416000, 0.6429481000", \ - "0.1924858000, 0.1957441000, 0.2043276000, 0.2242925000, 0.2709049000, 0.3869728000, 0.7120465000", \ - "0.2936751000, 0.2979090000, 0.3090940000, 0.3342609000, 0.3889724000, 0.5119332000, 0.8381048000", \ - "0.4559594000, 0.4614216000, 0.4757217000, 0.5081396000, 0.5780390000, 0.7197353000, 1.0533668000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.1044842000, 0.1089872000, 0.1212026000, 0.1515942000, 0.2301370000, 0.4596608000, 1.1792396000", \ - "0.1084844000, 0.1129889000, 0.1252136000, 0.1555998000, 0.2341599000, 0.4636422000, 1.1832788000", \ - "0.1187219000, 0.1232298000, 0.1353961000, 0.1657889000, 0.2442271000, 0.4739840000, 1.1925391000", \ - "0.1440150000, 0.1484560000, 0.1603983000, 0.1903544000, 0.2683647000, 0.4972214000, 1.2150716000", \ - "0.1947724000, 0.1992239000, 0.2111245000, 0.2408741000, 0.3177965000, 0.5471286000, 1.2666046000", \ - "0.2618431000, 0.2669405000, 0.2797753000, 0.3097809000, 0.3873272000, 0.6159013000, 1.3365954000", \ - "0.3296643000, 0.3360105000, 0.3521311000, 0.3869819000, 0.4646220000, 0.6926928000, 1.4109145000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0160122000, 0.0181230000, 0.0238572000, 0.0406851000, 0.0881987000, 0.2190589000, 0.6411507000", \ - "0.0160580000, 0.0182130000, 0.0238817000, 0.0406819000, 0.0882130000, 0.2189914000, 0.6407411000", \ - "0.0161852000, 0.0181492000, 0.0238485000, 0.0405972000, 0.0881236000, 0.2190732000, 0.6404328000", \ - "0.0161843000, 0.0184080000, 0.0242025000, 0.0407383000, 0.0883777000, 0.2191868000, 0.6410263000", \ - "0.0213697000, 0.0234850000, 0.0293079000, 0.0448739000, 0.0907070000, 0.2198218000, 0.6405876000", \ - "0.0317823000, 0.0342991000, 0.0410509000, 0.0588048000, 0.1051357000, 0.2290610000, 0.6417514000", \ - "0.0477592000, 0.0508605000, 0.0593601000, 0.0818223000, 0.1348322000, 0.2568974000, 0.6472405000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016038900, 0.0051449200, 0.0165038000, 0.0529404000, 0.1698210000, 0.5447490000"); - values("0.0260295000, 0.0296796000, 0.0400730000, 0.0708164000, 0.1673993000, 0.4821205000, 1.5023667000", \ - "0.0260730000, 0.0296871000, 0.0400879000, 0.0708615000, 0.1674098000, 0.4823483000, 1.5017654000", \ - "0.0258600000, 0.0294670000, 0.0399848000, 0.0709076000, 0.1673557000, 0.4829581000, 1.4996497000", \ - "0.0253509000, 0.0289795000, 0.0395783000, 0.0700925000, 0.1665520000, 0.4822430000, 1.5026946000", \ - "0.0266446000, 0.0302270000, 0.0404956000, 0.0704212000, 0.1657986000, 0.4816628000, 1.5029037000", \ - "0.0331629000, 0.0364724000, 0.0453557000, 0.0739150000, 0.1677229000, 0.4811189000, 1.5032637000", \ - "0.0454190000, 0.0490748000, 0.0589211000, 0.0839539000, 0.1707953000, 0.4838620000, 1.4998842000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41ai_1") { - leakage_power () { - value : 0.0023278000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0024189000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0023322000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0023361000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0023146000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0013643000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 7.673241e-06; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0031594000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003399000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0027393000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003400000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0023393000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0027915000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003395000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0023469000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0023493000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0023183000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0035048000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0024200000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0024104000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0003398000; - when : "A1&!A2&A3&!A4&!B1"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__o41ai"; - cell_leakage_power : 0.0013930580; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0023290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040122000, 0.0040157000, 0.0040237000, 0.0040225000, 0.0040196000, 0.0040131000, 0.0039979000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004012700, -0.004011200, -0.004007700, -0.004009000, -0.004011800, -0.004018200, -0.004033200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024330000; - } - pin ("A2") { - capacitance : 0.0024190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040202000, 0.0040192000, 0.0040169000, 0.0040175000, 0.0040190000, 0.0040224000, 0.0040301000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004005100, -0.004006900, -0.004010800, -0.004011300, -0.004012300, -0.004014700, -0.004020200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - } - pin ("A3") { - capacitance : 0.0024070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038893000, 0.0038875000, 0.0038833000, 0.0038836000, 0.0038844000, 0.0038864000, 0.0038908000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003876700, -0.003877100, -0.003877900, -0.003878600, -0.003880300, -0.003884300, -0.003893400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025660000; - } - pin ("A4") { - capacitance : 0.0023800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040970000, 0.0040959000, 0.0040934000, 0.0040910000, 0.0040854000, 0.0040726000, 0.0040429000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004086600, -0.004085300, -0.004082300, -0.004080100, -0.004075100, -0.004063500, -0.004036900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025600000; - } - pin ("B1") { - capacitance : 0.0022880000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0047260000, 0.0047349000, 0.0047554000, 0.0047564000, 0.0047586000, 0.0047638000, 0.0047758000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000293900, -0.000307600, -0.000339200, -0.000313700, -0.000254700, -0.000118800, 0.0001945000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0023490000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3&!A4) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0073974000, 0.0065670000, 0.0049114000, 0.0015706000, -0.005192200, -0.018748600, -0.046249700", \ - "0.0072699000, 0.0064435000, 0.0047861000, 0.0014371000, -0.005310500, -0.018865800, -0.046343500", \ - "0.0071597000, 0.0063239000, 0.0046626000, 0.0013057000, -0.005433300, -0.019004100, -0.046470600", \ - "0.0070286000, 0.0062059000, 0.0045436000, 0.0011916000, -0.005559500, -0.019106100, -0.046588200", \ - "0.0069149000, 0.0061267000, 0.0044683000, 0.0011432000, -0.005549600, -0.019099500, -0.046589100", \ - "0.0070873000, 0.0062534000, 0.0045888000, 0.0012229000, -0.005626700, -0.019198400, -0.046684400", \ - "0.0078223000, 0.0069887000, 0.0052910000, 0.0019229000, -0.004878200, -0.018677900, -0.046570900"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0175046000, 0.0183442000, 0.0200191000, 0.0233861000, 0.0301596000, 0.0438177000, 0.0711848000", \ - "0.0173708000, 0.0182181000, 0.0198738000, 0.0232649000, 0.0301094000, 0.0436823000, 0.0710765000", \ - "0.0171345000, 0.0179922000, 0.0196961000, 0.0231072000, 0.0299397000, 0.0435930000, 0.0710700000", \ - "0.0169822000, 0.0178551000, 0.0195179000, 0.0229163000, 0.0297577000, 0.0434660000, 0.0709012000", \ - "0.0169289000, 0.0177252000, 0.0194169000, 0.0227920000, 0.0296283000, 0.0433395000, 0.0707562000", \ - "0.0168553000, 0.0176541000, 0.0193400000, 0.0227127000, 0.0295221000, 0.0431948000, 0.0706215000", \ - "0.0167742000, 0.0176753000, 0.0193109000, 0.0227656000, 0.0295639000, 0.0431282000, 0.0705728000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0061160000, 0.0052856000, 0.0036340000, 0.0002905000, -0.006421500, -0.020026700, -0.047591200", \ - "0.0060769000, 0.0052506000, 0.0035968000, 0.0002584000, -0.006455000, -0.020068500, -0.047655200", \ - "0.0060003000, 0.0051692000, 0.0035200000, 0.0001886000, -0.006526700, -0.020133800, -0.047702300", \ - "0.0058097000, 0.0050080000, 0.0033750000, 5.270000e-05, -0.006644300, -0.020221000, -0.047780200", \ - "0.0056051000, 0.0048153000, 0.0031936000, -8.88000e-05, -0.006729900, -0.020262300, -0.047821400", \ - "0.0057771000, 0.0049562000, 0.0033042000, -1.35000e-05, -0.006802000, -0.020451300, -0.047966100", \ - "0.0061988000, 0.0053649000, 0.0037648000, 0.0003505000, -0.006395500, -0.020179600, -0.047874200"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0153532000, 0.0162035000, 0.0178954000, 0.0212519000, 0.0280220000, 0.0416413000, 0.0690806000", \ - "0.0151866000, 0.0160343000, 0.0177469000, 0.0211010000, 0.0279108000, 0.0415659000, 0.0689113000", \ - "0.0150240000, 0.0158763000, 0.0175455000, 0.0209558000, 0.0277851000, 0.0414823000, 0.0689120000", \ - "0.0148664000, 0.0156909000, 0.0173708000, 0.0207810000, 0.0276202000, 0.0413522000, 0.0687659000", \ - "0.0147960000, 0.0155839000, 0.0172794000, 0.0206470000, 0.0274777000, 0.0411920000, 0.0686359000", \ - "0.0147104000, 0.0155486000, 0.0172173000, 0.0205667000, 0.0273697000, 0.0410474000, 0.0685326000", \ - "0.0146804000, 0.0155049000, 0.0171730000, 0.0205760000, 0.0274146000, 0.0411245000, 0.0685198000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0047458000, 0.0039262000, 0.0022917000, -0.001054400, -0.007805600, -0.021463600, -0.049108600", \ - "0.0047320000, 0.0039183000, 0.0022804000, -0.001044600, -0.007791200, -0.021439900, -0.049080100", \ - "0.0046653000, 0.0038645000, 0.0022455000, -0.001055000, -0.007771800, -0.021416600, -0.049066300", \ - "0.0044653000, 0.0036763000, 0.0020855000, -0.001165200, -0.007855200, -0.021447900, -0.049062400", \ - "0.0043445000, 0.0035943000, 0.0019210000, -0.001397500, -0.008016400, -0.021544600, -0.049079300", \ - "0.0042534000, 0.0034653000, 0.0018343000, -0.001471300, -0.008161000, -0.021799200, -0.049253900", \ - "0.0047012000, 0.0038214000, 0.0021636000, -0.001195600, -0.008007300, -0.021645100, -0.049288400"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0132225000, 0.0140637000, 0.0157608000, 0.0191071000, 0.0259125000, 0.0395142000, 0.0669249000", \ - "0.0130622000, 0.0139199000, 0.0155879000, 0.0189985000, 0.0258005000, 0.0394394000, 0.0668390000", \ - "0.0128711000, 0.0137263000, 0.0154143000, 0.0188286000, 0.0256717000, 0.0393528000, 0.0667605000", \ - "0.0126985000, 0.0135754000, 0.0152463000, 0.0186557000, 0.0255042000, 0.0392180000, 0.0666784000", \ - "0.0126338000, 0.0134603000, 0.0151202000, 0.0185186000, 0.0253549000, 0.0390462000, 0.0665569000", \ - "0.0125503000, 0.0133773000, 0.0150949000, 0.0184907000, 0.0252641000, 0.0389418000, 0.0664511000", \ - "0.0127354000, 0.0135344000, 0.0151605000, 0.0185551000, 0.0253065000, 0.0390643000, 0.0664791000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0029106000, 0.0020984000, 0.0004427000, -0.002909100, -0.009681400, -0.023381900, -0.051078600", \ - "0.0027780000, 0.0019982000, 0.0003903000, -0.002908700, -0.009643000, -0.023306300, -0.050984500", \ - "0.0025541000, 0.0018084000, 0.0002491000, -0.002974600, -0.009642100, -0.023252900, -0.050896200", \ - "0.0022920000, 0.0015493000, 1.760000e-05, -0.003170700, -0.009743300, -0.023289000, -0.050866000", \ - "0.0021690000, 0.0014251000, -0.000140300, -0.003416700, -0.009979500, -0.023434100, -0.050922600", \ - "0.0021059000, 0.0013081000, -0.000305900, -0.003590700, -0.010181700, -0.023755000, -0.051167200", \ - "0.0027178000, 0.0018489000, 0.0001471000, -0.003283800, -0.010097100, -0.023722300, -0.051219400"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0109843000, 0.0118200000, 0.0135069000, 0.0168960000, 0.0237219000, 0.0373348000, 0.0646901000", \ - "0.0107590000, 0.0115895000, 0.0133088000, 0.0167019000, 0.0235616000, 0.0371989000, 0.0646833000", \ - "0.0104623000, 0.0112729000, 0.0129971000, 0.0164584000, 0.0233350000, 0.0370721000, 0.0645780000", \ - "0.0102710000, 0.0111401000, 0.0128501000, 0.0162259000, 0.0231120000, 0.0368599000, 0.0643623000", \ - "0.0104207000, 0.0112604000, 0.0128726000, 0.0162435000, 0.0230228000, 0.0366937000, 0.0642782000", \ - "0.0109785000, 0.0118006000, 0.0134665000, 0.0164018000, 0.0231410000, 0.0366921000, 0.0641973000", \ - "0.0118497000, 0.0126326000, 0.0142411000, 0.0174555000, 0.0240637000, 0.0374272000, 0.0642515000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0037219000, 0.0029219000, 0.0013168000, -0.001988300, -0.008682900, -0.022208700, -0.049679500", \ - "0.0035662000, 0.0027977000, 0.0011824000, -0.002083300, -0.008746400, -0.022244200, -0.049692800", \ - "0.0034317000, 0.0026441000, 0.0010521000, -0.002221000, -0.008854000, -0.022291400, -0.049712500", \ - "0.0032986000, 0.0024913000, 0.0008714000, -0.002360000, -0.009036900, -0.022460600, -0.049830100", \ - "0.0031759000, 0.0023627000, 0.0007234000, -0.002582500, -0.009216200, -0.022652800, -0.050049600", \ - "0.0036448000, 0.0027807000, 0.0010787000, -0.002374300, -0.009232800, -0.022687700, -0.050178900", \ - "0.0050687000, 0.0041770000, 0.0024673000, -0.001045900, -0.007956600, -0.022068700, -0.049799400"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0010095830, 0.0020385140, 0.0041160960, 0.0083110790, 0.0167814400, 0.0338845000"); - values("0.0101596000, 0.0110879000, 0.0128984000, 0.0164092000, 0.0232753000, 0.0370057000, 0.0644924000", \ - "0.0099089000, 0.0108427000, 0.0126902000, 0.0161590000, 0.0231397000, 0.0369231000, 0.0645099000", \ - "0.0096923000, 0.0105651000, 0.0123670000, 0.0159199000, 0.0229046000, 0.0366697000, 0.0643403000", \ - "0.0096720000, 0.0105156000, 0.0122412000, 0.0156526000, 0.0225374000, 0.0364139000, 0.0641466000", \ - "0.0098091000, 0.0106225000, 0.0122601000, 0.0156019000, 0.0224577000, 0.0363020000, 0.0639688000", \ - "0.0106557000, 0.0115084000, 0.0131121000, 0.0165438000, 0.0231847000, 0.0365023000, 0.0636837000", \ - "0.0126211000, 0.0133282000, 0.0147405000, 0.0176422000, 0.0242557000, 0.0374428000, 0.0646819000"); - } - } - max_capacitance : 0.0338840000; - max_transition : 1.4806290000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0414108000, 0.0452218000, 0.0525645000, 0.0666243000, 0.0931865000, 0.1433687000, 0.2401093000", \ - "0.0462667000, 0.0500261000, 0.0573722000, 0.0713468000, 0.0978333000, 0.1479929000, 0.2446358000", \ - "0.0572241000, 0.0608939000, 0.0680825000, 0.0819660000, 0.1082329000, 0.1583675000, 0.2549441000", \ - "0.0781641000, 0.0823660000, 0.0898706000, 0.1039819000, 0.1298313000, 0.1796232000, 0.2762097000", \ - "0.1102411000, 0.1156809000, 0.1259666000, 0.1437883000, 0.1746446000, 0.2275640000, 0.3244698000", \ - "0.1498700000, 0.1581079000, 0.1725379000, 0.1987977000, 0.2426707000, 0.3132385000, 0.4273777000", \ - "0.1767365000, 0.1888057000, 0.2113143000, 0.2520325000, 0.3198091000, 0.4275435000, 0.5920232000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.2599977000, 0.2746984000, 0.3060187000, 0.3678914000, 0.4915713000, 0.7379454000, 1.2327395000", \ - "0.2630482000, 0.2790475000, 0.3098195000, 0.3726658000, 0.4953537000, 0.7420968000, 1.2378414000", \ - "0.2731010000, 0.2879857000, 0.3210491000, 0.3822960000, 0.5065906000, 0.7543978000, 1.2499559000", \ - "0.2976450000, 0.3134427000, 0.3441279000, 0.4071494000, 0.5314859000, 0.7791859000, 1.2753405000", \ - "0.3478681000, 0.3631274000, 0.3950686000, 0.4571893000, 0.5812366000, 0.8284511000, 1.3260969000", \ - "0.4450330000, 0.4620730000, 0.4951304000, 0.5601485000, 0.6833578000, 0.9309193000, 1.4271825000", \ - "0.6015748000, 0.6221519000, 0.6618709000, 0.7375375000, 0.8794208000, 1.1459885000, 1.6452725000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0326762000, 0.0372295000, 0.0461327000, 0.0631988000, 0.0958911000, 0.1585935000, 0.2834726000", \ - "0.0323626000, 0.0368778000, 0.0457465000, 0.0629568000, 0.0955086000, 0.1583697000, 0.2823282000", \ - "0.0321739000, 0.0366105000, 0.0452571000, 0.0621828000, 0.0950752000, 0.1585049000, 0.2822055000", \ - "0.0388984000, 0.0426114000, 0.0499781000, 0.0649224000, 0.0956471000, 0.1576532000, 0.2822781000", \ - "0.0587983000, 0.0625180000, 0.0699721000, 0.0847946000, 0.1121546000, 0.1658132000, 0.2839711000", \ - "0.0968258000, 0.1015980000, 0.1113686000, 0.1295355000, 0.1612939000, 0.2159355000, 0.3202640000", \ - "0.1648232000, 0.1721795000, 0.1867171000, 0.2122181000, 0.2565686000, 0.3286257000, 0.4445544000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1722483000, 0.1925258000, 0.2331873000, 0.3139929000, 0.4768527000, 0.8043676000, 1.4603138000", \ - "0.1725761000, 0.1929327000, 0.2329800000, 0.3144354000, 0.4769884000, 0.8030606000, 1.4588010000", \ - "0.1723731000, 0.1925869000, 0.2332653000, 0.3143444000, 0.4771541000, 0.8050801000, 1.4609846000", \ - "0.1722747000, 0.1928675000, 0.2330512000, 0.3141357000, 0.4766137000, 0.8043052000, 1.4597706000", \ - "0.1728274000, 0.1930048000, 0.2335183000, 0.3146953000, 0.4779652000, 0.8035995000, 1.4606403000", \ - "0.1931145000, 0.2122339000, 0.2503898000, 0.3265773000, 0.4836480000, 0.8055689000, 1.4605690000", \ - "0.2443695000, 0.2649969000, 0.3057061000, 0.3880542000, 0.5450032000, 0.8474581000, 1.4761998000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0415218000, 0.0450545000, 0.0519208000, 0.0648607000, 0.0893654000, 0.1364697000, 0.2286066000", \ - "0.0463542000, 0.0498923000, 0.0567478000, 0.0696765000, 0.0941734000, 0.1412739000, 0.2334946000", \ - "0.0567747000, 0.0602307000, 0.0669631000, 0.0798767000, 0.1042969000, 0.1513945000, 0.2435702000", \ - "0.0760322000, 0.0799656000, 0.0871799000, 0.1005506000, 0.1249391000, 0.1719190000, 0.2642524000", \ - "0.1031947000, 0.1086255000, 0.1183809000, 0.1360650000, 0.1660299000, 0.2173604000, 0.3105299000", \ - "0.1307836000, 0.1389392000, 0.1536209000, 0.1802136000, 0.2237531000, 0.2947804000, 0.4074596000", \ - "0.1331203000, 0.1461993000, 0.1692828000, 0.2104828000, 0.2801128000, 0.3890019000, 0.5560228000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.2458409000, 0.2607188000, 0.2931859000, 0.3542479000, 0.4778949000, 0.7246584000, 1.2193739000", \ - "0.2486808000, 0.2637679000, 0.2961094000, 0.3576630000, 0.4818988000, 0.7278972000, 1.2236325000", \ - "0.2578560000, 0.2744227000, 0.3052659000, 0.3684630000, 0.4924751000, 0.7393155000, 1.2353393000", \ - "0.2831963000, 0.2990404000, 0.3301548000, 0.3935470000, 0.5176523000, 0.7646077000, 1.2614790000", \ - "0.3395124000, 0.3546027000, 0.3864414000, 0.4485108000, 0.5723017000, 0.8196016000, 1.3164856000", \ - "0.4503392000, 0.4696210000, 0.5041012000, 0.5700160000, 0.6937718000, 0.9407629000, 1.4372242000", \ - "0.6492737000, 0.6719553000, 0.7157107000, 0.7950718000, 0.9445364000, 1.2146016000, 1.7132041000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0295996000, 0.0335515000, 0.0414369000, 0.0570207000, 0.0869692000, 0.1467568000, 0.2671127000", \ - "0.0294563000, 0.0334132000, 0.0413194000, 0.0569078000, 0.0869109000, 0.1471246000, 0.2683136000", \ - "0.0294530000, 0.0332390000, 0.0410581000, 0.0563725000, 0.0866720000, 0.1470940000, 0.2674158000", \ - "0.0353318000, 0.0387453000, 0.0456071000, 0.0592778000, 0.0878965000, 0.1464884000, 0.2680217000", \ - "0.0530986000, 0.0568438000, 0.0646306000, 0.0784036000, 0.1048418000, 0.1564600000, 0.2704666000", \ - "0.0887085000, 0.0938552000, 0.1033406000, 0.1218988000, 0.1522340000, 0.2085885000, 0.3086493000", \ - "0.1556238000, 0.1636753000, 0.1781886000, 0.2036820000, 0.2480680000, 0.3179788000, 0.4376993000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1723570000, 0.1926174000, 0.2334791000, 0.3140114000, 0.4769117000, 0.8030250000, 1.4603382000", \ - "0.1722752000, 0.1925917000, 0.2334817000, 0.3139906000, 0.4768161000, 0.8035784000, 1.4598172000", \ - "0.1725363000, 0.1929068000, 0.2330154000, 0.3143994000, 0.4773960000, 0.8034430000, 1.4591167000", \ - "0.1726614000, 0.1924613000, 0.2330774000, 0.3140562000, 0.4772929000, 0.8035549000, 1.4604873000", \ - "0.1737469000, 0.1934566000, 0.2337762000, 0.3146930000, 0.4778964000, 0.8036073000, 1.4607179000", \ - "0.2020879000, 0.2204150000, 0.2564886000, 0.3313609000, 0.4860691000, 0.8052662000, 1.4617159000", \ - "0.2734127000, 0.2937102000, 0.3338185000, 0.4117921000, 0.5618577000, 0.8536749000, 1.4750844000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0404519000, 0.0436077000, 0.0496494000, 0.0614104000, 0.0843280000, 0.1295825000, 0.2201168000", \ - "0.0453262000, 0.0484947000, 0.0545587000, 0.0663397000, 0.0892626000, 0.1345577000, 0.2251435000", \ - "0.0554677000, 0.0586134000, 0.0647525000, 0.0765919000, 0.0995972000, 0.1449715000, 0.2355129000", \ - "0.0729578000, 0.0765890000, 0.0837047000, 0.0965885000, 0.1200312000, 0.1655956000, 0.2562824000", \ - "0.0952084000, 0.1010945000, 0.1106432000, 0.1282535000, 0.1583566000, 0.2099283000, 0.3023790000", \ - "0.1129349000, 0.1216120000, 0.1373369000, 0.1646925000, 0.2107451000, 0.2828284000, 0.3976438000", \ - "0.0969455000, 0.1105040000, 0.1360613000, 0.1805615000, 0.2545257000, 0.3680065000, 0.5384148000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.2150528000, 0.2295830000, 0.2621307000, 0.3229548000, 0.4465326000, 0.6936384000, 1.1887357000", \ - "0.2179654000, 0.2336676000, 0.2649440000, 0.3260165000, 0.4500947000, 0.6973596000, 1.1924066000", \ - "0.2254693000, 0.2422618000, 0.2738191000, 0.3366752000, 0.4598224000, 0.7073635000, 1.2034446000", \ - "0.2508680000, 0.2674331000, 0.2985613000, 0.3613658000, 0.4854629000, 0.7327818000, 1.2295063000", \ - "0.3104093000, 0.3256628000, 0.3572219000, 0.4191537000, 0.5431662000, 0.7910412000, 1.2874749000", \ - "0.4330579000, 0.4508657000, 0.4879729000, 0.5565229000, 0.6799308000, 0.9275954000, 1.4241182000", \ - "0.6512659000, 0.6771210000, 0.7246810000, 0.8144954000, 0.9687308000, 1.2471717000, 1.7446410000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0240603000, 0.0276478000, 0.0349990000, 0.0495998000, 0.0793908000, 0.1389397000, 0.2590897000", \ - "0.0240466000, 0.0276494000, 0.0349137000, 0.0495721000, 0.0793609000, 0.1388131000, 0.2597030000", \ - "0.0242152000, 0.0277214000, 0.0349852000, 0.0496452000, 0.0793011000, 0.1388920000, 0.2599033000", \ - "0.0301325000, 0.0333989000, 0.0400818000, 0.0530194000, 0.0809406000, 0.1390356000, 0.2600580000", \ - "0.0470848000, 0.0508410000, 0.0586229000, 0.0723670000, 0.0986647000, 0.1503017000, 0.2625397000", \ - "0.0817597000, 0.0871469000, 0.0972470000, 0.1156700000, 0.1477486000, 0.2020767000, 0.3047551000", \ - "0.1469953000, 0.1555214000, 0.1709202000, 0.1984031000, 0.2430373000, 0.3149402000, 0.4323942000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1722873000, 0.1927086000, 0.2335382000, 0.3142829000, 0.4771286000, 0.8036298000, 1.4634228000", \ - "0.1728778000, 0.1928634000, 0.2330071000, 0.3143601000, 0.4770248000, 0.8033431000, 1.4598931000", \ - "0.1724372000, 0.1923834000, 0.2328737000, 0.3136985000, 0.4767847000, 0.8036768000, 1.4597001000", \ - "0.1723558000, 0.1925528000, 0.2328762000, 0.3142115000, 0.4783226000, 0.8035277000, 1.4594137000", \ - "0.1756662000, 0.1946989000, 0.2338864000, 0.3147538000, 0.4772406000, 0.8041682000, 1.4608569000", \ - "0.2120863000, 0.2296901000, 0.2658570000, 0.3382505000, 0.4882833000, 0.8047136000, 1.4606916000", \ - "0.3041254000, 0.3255153000, 0.3655323000, 0.4465135000, 0.5869785000, 0.8686974000, 1.4762374000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0322722000, 0.0350102000, 0.0403872000, 0.0509484000, 0.0720923000, 0.1145047000, 0.1997986000", \ - "0.0368285000, 0.0396660000, 0.0451969000, 0.0558713000, 0.0771472000, 0.1195704000, 0.2048184000", \ - "0.0464405000, 0.0494894000, 0.0552858000, 0.0662662000, 0.0876550000, 0.1304207000, 0.2157119000", \ - "0.0604489000, 0.0645599000, 0.0723252000, 0.0855914000, 0.1087037000, 0.1517817000, 0.2373564000", \ - "0.0745361000, 0.0813133000, 0.0930776000, 0.1130248000, 0.1453781000, 0.1977162000, 0.2859436000", \ - "0.0775649000, 0.0879574000, 0.1079861000, 0.1392210000, 0.1900418000, 0.2668562000, 0.3814274000", \ - "0.0354460000, 0.0531592000, 0.0847880000, 0.1372208000, 0.2202350000, 0.3425327000, 0.5217581000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1552745000, 0.1711156000, 0.2031463000, 0.2651052000, 0.3882625000, 0.6345889000, 1.1302338000", \ - "0.1563640000, 0.1719931000, 0.2043513000, 0.2662807000, 0.3903309000, 0.6378626000, 1.1337249000", \ - "0.1626486000, 0.1780151000, 0.2103220000, 0.2735110000, 0.3985355000, 0.6466568000, 1.1433731000", \ - "0.1860038000, 0.2018927000, 0.2334997000, 0.2957910000, 0.4204999000, 0.6689295000, 1.1666522000", \ - "0.2491713000, 0.2638682000, 0.2931332000, 0.3547244000, 0.4776730000, 0.7249208000, 1.2222594000", \ - "0.3850117000, 0.4033523000, 0.4389378000, 0.5007435000, 0.6222214000, 0.8666031000, 1.3618313000", \ - "0.6035326000, 0.6296894000, 0.6808918000, 0.7710059000, 0.9353350000, 1.2004637000, 1.6845839000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0151898000, 0.0186059000, 0.0253869000, 0.0394419000, 0.0676307000, 0.1245255000, 0.2387199000", \ - "0.0152393000, 0.0185971000, 0.0254755000, 0.0394019000, 0.0675834000, 0.1245523000, 0.2390553000", \ - "0.0164443000, 0.0194912000, 0.0258699000, 0.0394702000, 0.0671053000, 0.1249775000, 0.2392579000", \ - "0.0242497000, 0.0273166000, 0.0335734000, 0.0454486000, 0.0701622000, 0.1243536000, 0.2397892000", \ - "0.0418291000, 0.0456870000, 0.0531532000, 0.0667693000, 0.0918084000, 0.1393481000, 0.2432528000", \ - "0.0760115000, 0.0818349000, 0.0924132000, 0.1110230000, 0.1426623000, 0.1960267000, 0.2908542000", \ - "0.1439358000, 0.1522091000, 0.1676378000, 0.1955428000, 0.2386688000, 0.3096178000, 0.4248180000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.1711496000, 0.1916590000, 0.2323103000, 0.3143106000, 0.4780168000, 0.8032800000, 1.4599845000", \ - "0.1707326000, 0.1912622000, 0.2326042000, 0.3139549000, 0.4770734000, 0.8029592000, 1.4637359000", \ - "0.1696866000, 0.1905672000, 0.2318476000, 0.3137720000, 0.4768674000, 0.8029761000, 1.4618997000", \ - "0.1662066000, 0.1876962000, 0.2302669000, 0.3131523000, 0.4771873000, 0.8032160000, 1.4606089000", \ - "0.1711480000, 0.1900081000, 0.2294597000, 0.3097922000, 0.4755448000, 0.8052310000, 1.4632352000", \ - "0.2182376000, 0.2391959000, 0.2775420000, 0.3448307000, 0.4903449000, 0.8032457000, 1.4606714000", \ - "0.3054978000, 0.3321808000, 0.3842239000, 0.4691720000, 0.6207291000, 0.8891891000, 1.4806293000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0298258000, 0.0337759000, 0.0412579000, 0.0554438000, 0.0819574000, 0.1321105000, 0.2287520000", \ - "0.0340036000, 0.0378914000, 0.0453726000, 0.0596291000, 0.0862419000, 0.1364955000, 0.2331298000", \ - "0.0460065000, 0.0493230000, 0.0562404000, 0.0698693000, 0.0962906000, 0.1467400000, 0.2435356000", \ - "0.0694372000, 0.0739751000, 0.0823971000, 0.0965953000, 0.1214946000, 0.1703224000, 0.2668901000", \ - "0.1010515000, 0.1075315000, 0.1194742000, 0.1402009000, 0.1746790000, 0.2286211000, 0.3232859000", \ - "0.1366117000, 0.1460901000, 0.1636477000, 0.1942703000, 0.2442219000, 0.3254615000, 0.4510921000", \ - "0.1590504000, 0.1727603000, 0.1983059000, 0.2436876000, 0.3200761000, 0.4440125000, 0.6316959000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0255574000, 0.0292877000, 0.0366057000, 0.0506417000, 0.0782213000, 0.1332734000, 0.2432647000", \ - "0.0307436000, 0.0344736000, 0.0417630000, 0.0556367000, 0.0836273000, 0.1386841000, 0.2489198000", \ - "0.0441986000, 0.0477486000, 0.0548809000, 0.0688668000, 0.0966972000, 0.1519044000, 0.2622134000", \ - "0.0669635000, 0.0731650000, 0.0835224000, 0.1002215000, 0.1278791000, 0.1834632000, 0.2945864000", \ - "0.1026569000, 0.1124059000, 0.1293891000, 0.1564922000, 0.1966779000, 0.2560631000, 0.3660066000", \ - "0.1600304000, 0.1749894000, 0.2016965000, 0.2456445000, 0.3110190000, 0.4047215000, 0.5394147000", \ - "0.2604835000, 0.2815884000, 0.3212377000, 0.3867151000, 0.4898348000, 0.6435675000, 0.8585760000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0317384000, 0.0362734000, 0.0450771000, 0.0619675000, 0.0948750000, 0.1580239000, 0.2821745000", \ - "0.0309950000, 0.0357739000, 0.0448369000, 0.0619426000, 0.0947831000, 0.1581667000, 0.2829170000", \ - "0.0322869000, 0.0362259000, 0.0445358000, 0.0611117000, 0.0944097000, 0.1576944000, 0.2822571000", \ - "0.0445376000, 0.0485703000, 0.0552123000, 0.0679550000, 0.0964426000, 0.1570387000, 0.2823777000", \ - "0.0673612000, 0.0726151000, 0.0822475000, 0.0985192000, 0.1250773000, 0.1743136000, 0.2857561000", \ - "0.1075068000, 0.1154832000, 0.1295385000, 0.1532515000, 0.1912543000, 0.2512652000, 0.3475718000", \ - "0.1756649000, 0.1879531000, 0.2092187000, 0.2454143000, 0.3040544000, 0.3894189000, 0.5308416000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0010095800, 0.0020385100, 0.0041161000, 0.0083110800, 0.0167814000, 0.0338845000"); - values("0.0264085000, 0.0316509000, 0.0425894000, 0.0639355000, 0.1057702000, 0.1879676000, 0.3511338000", \ - "0.0264810000, 0.0317954000, 0.0425513000, 0.0639010000, 0.1058267000, 0.1879387000, 0.3510297000", \ - "0.0301599000, 0.0344402000, 0.0436712000, 0.0638931000, 0.1058002000, 0.1878953000, 0.3508979000", \ - "0.0502409000, 0.0530151000, 0.0578394000, 0.0733985000, 0.1087715000, 0.1879651000, 0.3510494000", \ - "0.0897030000, 0.0930605000, 0.1000761000, 0.1138024000, 0.1394038000, 0.2028032000, 0.3521318000", \ - "0.1603387000, 0.1646913000, 0.1741552000, 0.1929515000, 0.2273338000, 0.2848380000, 0.3982399000", \ - "0.2911254000, 0.2953407000, 0.3058473000, 0.3331271000, 0.3846427000, 0.4660742000, 0.5937473000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41ai_2") { - leakage_power () { - value : 0.0022590000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0100640000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0116235000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0005536000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0101656000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0005536000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0081833000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0005535000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0100748000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0005528000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0081834000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0005533000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0081851000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0005543000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0080686000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0005533000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0100432000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0005567000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0081857000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0005538000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0081877000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0005537000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0080692000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0005538000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0081974000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0005530000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0080731000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0005536000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0080822000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0005528000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0080300000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0005539000; - when : "A1&A2&A3&A4&!B1"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__o41ai"; - cell_leakage_power : 0.0047494200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0044270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080244000, 0.0080211000, 0.0080134000, 0.0080160000, 0.0080219000, 0.0080354000, 0.0080667000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007992600, -0.007991000, -0.007987200, -0.007984300, -0.007977700, -0.007962600, -0.007927500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046340000; - } - pin ("A2") { - capacitance : 0.0042970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0040200000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079408000, 0.0079363000, 0.0079260000, 0.0079240000, 0.0079194000, 0.0079087000, 0.0078840000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007924300, -0.007920100, -0.007910500, -0.007907600, -0.007901000, -0.007885700, -0.007850600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045730000; - } - pin ("A3") { - capacitance : 0.0043230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039870000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079653000, 0.0079649000, 0.0079641000, 0.0079656000, 0.0079690000, 0.0079769000, 0.0079951000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007950300, -0.007949100, -0.007946300, -0.007942800, -0.007934700, -0.007916000, -0.007872900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046590000; - } - pin ("A4") { - capacitance : 0.0043310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0039720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079870000, 0.0079848000, 0.0079798000, 0.0079812000, 0.0079844000, 0.0079917000, 0.0080086000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.007972200, -0.007968600, -0.007960500, -0.007959000, -0.007955300, -0.007947000, -0.007927700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046910000; - } - pin ("B1") { - capacitance : 0.0043460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042360000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091635000, 0.0091576000, 0.0091439000, 0.0091470000, 0.0091543000, 0.0091709000, 0.0092094000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000541200, -0.000576500, -0.000658100, -0.000606300, -0.000487100, -0.000212000, 0.0004220000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044550000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3&!A4) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0171582000, 0.0161484000, 0.0139370000, 0.0089744000, -0.002150400, -0.026836000, -0.082041500", \ - "0.0169002000, 0.0159369000, 0.0136902000, 0.0087062000, -0.002373000, -0.027060000, -0.082289300", \ - "0.0166116000, 0.0156171000, 0.0133943000, 0.0084369000, -0.002663400, -0.027343700, -0.082578100", \ - "0.0163263000, 0.0153415000, 0.0131330000, 0.0081484000, -0.002973100, -0.027659300, -0.082853500", \ - "0.0160567000, 0.0150726000, 0.0128565000, 0.0079953000, -0.003037900, -0.027685200, -0.082940800", \ - "0.0158919000, 0.0148732000, 0.0126667000, 0.0076702000, -0.003402400, -0.027960200, -0.083140900", \ - "0.0173746000, 0.0164134000, 0.0141596000, 0.0091022000, -0.002100000, -0.027121300, -0.083093800"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0334217000, 0.0344572000, 0.0367593000, 0.0416991000, 0.0528163000, 0.0776172000, 0.1327662000", \ - "0.0331420000, 0.0340981000, 0.0363669000, 0.0414385000, 0.0526223000, 0.0774283000, 0.1326279000", \ - "0.0326831000, 0.0337102000, 0.0359998000, 0.0410687000, 0.0523185000, 0.0772370000, 0.1324862000", \ - "0.0323372000, 0.0333636000, 0.0356551000, 0.0407233000, 0.0519533000, 0.0769330000, 0.1321895000", \ - "0.0320941000, 0.0331007000, 0.0353377000, 0.0403819000, 0.0515719000, 0.0765192000, 0.1318600000", \ - "0.0319982000, 0.0329747000, 0.0352623000, 0.0402743000, 0.0514440000, 0.0763704000, 0.1317150000", \ - "0.0318590000, 0.0328728000, 0.0351361000, 0.0402267000, 0.0514276000, 0.0761313000, 0.1315112000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0136938000, 0.0126830000, 0.0104596000, 0.0054848000, -0.005556800, -0.030242300, -0.085692200", \ - "0.0136306000, 0.0126286000, 0.0104128000, 0.0054529000, -0.005585400, -0.030310400, -0.085735800", \ - "0.0134710000, 0.0124874000, 0.0102609000, 0.0053175000, -0.005716300, -0.030404400, -0.085851700", \ - "0.0131296000, 0.0121921000, 0.0100146000, 0.0050146000, -0.005967600, -0.030603000, -0.086010300", \ - "0.0126451000, 0.0116847000, 0.0095496000, 0.0046919000, -0.006163100, -0.030722100, -0.086074800", \ - "0.0127807000, 0.0118582000, 0.0096518000, 0.0047421000, -0.006344100, -0.031182500, -0.086377800", \ - "0.0138300000, 0.0127558000, 0.0106039000, 0.0055989000, -0.005617300, -0.030607300, -0.086416500"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0287974000, 0.0298054000, 0.0319696000, 0.0369934000, 0.0481008000, 0.0729124000, 0.1280848000", \ - "0.0283669000, 0.0293729000, 0.0316852000, 0.0367099000, 0.0479060000, 0.0726987000, 0.1278910000", \ - "0.0279933000, 0.0290206000, 0.0313379000, 0.0363588000, 0.0475778000, 0.0724783000, 0.1276414000", \ - "0.0276163000, 0.0286197000, 0.0309038000, 0.0359863000, 0.0472208000, 0.0722265000, 0.1275504000", \ - "0.0273483000, 0.0283305000, 0.0305934000, 0.0356374000, 0.0468801000, 0.0718154000, 0.1271830000", \ - "0.0272874000, 0.0282800000, 0.0305396000, 0.0355557000, 0.0467744000, 0.0716430000, 0.1269738000", \ - "0.0273323000, 0.0283350000, 0.0305589000, 0.0356374000, 0.0468825000, 0.0717201000, 0.1270024000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0108964000, 0.0099120000, 0.0077027000, 0.0027675000, -0.008309400, -0.033100800, -0.088707900", \ - "0.0108325000, 0.0098525000, 0.0076606000, 0.0027558000, -0.008302500, -0.033088300, -0.088672300", \ - "0.0106172000, 0.0096616000, 0.0075094000, 0.0026984000, -0.008312500, -0.033045800, -0.088599600", \ - "0.0101929000, 0.0092547000, 0.0071388000, 0.0023829000, -0.008496600, -0.033129000, -0.088593200", \ - "0.0097560000, 0.0088130000, 0.0066217000, 0.0018812000, -0.008897200, -0.033341300, -0.088679100", \ - "0.0096584000, 0.0086787000, 0.0065284000, 0.0016339000, -0.009203300, -0.033894900, -0.089101900", \ - "0.0106485000, 0.0096604000, 0.0073973000, 0.0023196000, -0.008866200, -0.033659500, -0.089298100"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0242117000, 0.0252186000, 0.0275016000, 0.0324901000, 0.0436367000, 0.0684023000, 0.1235223000", \ - "0.0238832000, 0.0249260000, 0.0272649000, 0.0322188000, 0.0433854000, 0.0682371000, 0.1234340000", \ - "0.0234697000, 0.0245215000, 0.0268354000, 0.0318663000, 0.0430946000, 0.0679979000, 0.1232632000", \ - "0.0232062000, 0.0241387000, 0.0264081000, 0.0314934000, 0.0427771000, 0.0677025000, 0.1230788000", \ - "0.0229015000, 0.0238717000, 0.0261824000, 0.0311916000, 0.0423748000, 0.0673508000, 0.1226906000", \ - "0.0228148000, 0.0238122000, 0.0260467000, 0.0311295000, 0.0424031000, 0.0671712000, 0.1224953000", \ - "0.0232066000, 0.0242410000, 0.0264297000, 0.0313914000, 0.0425233000, 0.0674248000, 0.1227333000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0067723000, 0.0058098000, 0.0036022000, -0.001366600, -0.012485800, -0.037373400, -0.093075800", \ - "0.0064732000, 0.0055416000, 0.0034275000, -0.001415700, -0.012425700, -0.037221500, -0.092877600", \ - "0.0059896000, 0.0051010000, 0.0030625000, -0.001614300, -0.012457100, -0.037119300, -0.092676700", \ - "0.0054409000, 0.0045750000, 0.0025720000, -0.002054000, -0.012708800, -0.037172100, -0.092587000", \ - "0.0052849000, 0.0043512000, 0.0022840000, -0.002484700, -0.013194000, -0.037492000, -0.092701900", \ - "0.0052640000, 0.0042746000, 0.0021275000, -0.002740400, -0.013527600, -0.038073000, -0.093130800", \ - "0.0067604000, 0.0056703000, 0.0033486000, -0.001845400, -0.013023100, -0.037878400, -0.093266500"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0194370000, 0.0204057000, 0.0227494000, 0.0277268000, 0.0388899000, 0.0636635000, 0.1188535000", \ - "0.0189530000, 0.0199709000, 0.0222772000, 0.0273766000, 0.0385846000, 0.0634906000, 0.1186817000", \ - "0.0184004000, 0.0194268000, 0.0217637000, 0.0269118000, 0.0382178000, 0.0632343000, 0.1185121000", \ - "0.0180913000, 0.0190348000, 0.0213417000, 0.0264599000, 0.0377573000, 0.0628260000, 0.1182536000", \ - "0.0180212000, 0.0190018000, 0.0212440000, 0.0262704000, 0.0374829000, 0.0623764000, 0.1178192000", \ - "0.0187764000, 0.0197710000, 0.0219433000, 0.0268591000, 0.0379264000, 0.0625931000, 0.1177619000", \ - "0.0214755000, 0.0224176000, 0.0245703000, 0.0293954000, 0.0400185000, 0.0642097000, 0.1192116000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0092788000, 0.0083471000, 0.0062270000, 0.0014039000, -0.009573000, -0.034180200, -0.089316700", \ - "0.0090764000, 0.0081410000, 0.0059698000, 0.0011845000, -0.009712700, -0.034198800, -0.089347100", \ - "0.0088680000, 0.0079268000, 0.0057640000, 0.0009679000, -0.009914900, -0.034340700, -0.089356600", \ - "0.0085888000, 0.0076375000, 0.0054852000, 0.0006170000, -0.010302500, -0.034720800, -0.089626000", \ - "0.0085011000, 0.0075087000, 0.0053160000, 0.0004146000, -0.010559800, -0.035043300, -0.089974200", \ - "0.0092716000, 0.0082382000, 0.0059275000, 0.0008017000, -0.010240100, -0.035056600, -0.090387200", \ - "0.0123962000, 0.0113348000, 0.0089354000, 0.0037445000, -0.007809400, -0.033392400, -0.089963300"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011173350, 0.0024968740, 0.0055796880, 0.0124687600, 0.0278635600, 0.0622658400"); - values("0.0185976000, 0.0197895000, 0.0223325000, 0.0276553000, 0.0390815000, 0.0640028000, 0.1193450000", \ - "0.0182174000, 0.0193663000, 0.0218474000, 0.0272974000, 0.0388392000, 0.0639219000, 0.1193965000", \ - "0.0179508000, 0.0190597000, 0.0214736000, 0.0268511000, 0.0383292000, 0.0635830000, 0.1193286000", \ - "0.0180251000, 0.0190175000, 0.0212963000, 0.0263174000, 0.0379678000, 0.0629729000, 0.1185354000", \ - "0.0184063000, 0.0193971000, 0.0215580000, 0.0264885000, 0.0376514000, 0.0625283000, 0.1181528000", \ - "0.0202291000, 0.0210889000, 0.0231330000, 0.0279193000, 0.0385752000, 0.0629708000, 0.1177914000", \ - "0.0244713000, 0.0253199000, 0.0272660000, 0.0327683000, 0.0415997000, 0.0658696000, 0.1215492000"); - } - } - max_capacitance : 0.0622660000; - max_transition : 1.4837760000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0435682000, 0.0463437000, 0.0524181000, 0.0651045000, 0.0912253000, 0.1451316000, 0.2576507000", \ - "0.0482859000, 0.0510970000, 0.0570495000, 0.0696664000, 0.0958326000, 0.1495156000, 0.2621142000", \ - "0.0588895000, 0.0616394000, 0.0674564000, 0.0799545000, 0.1057869000, 0.1594179000, 0.2720232000", \ - "0.0788483000, 0.0817881000, 0.0881975000, 0.1007692000, 0.1262338000, 0.1794777000, 0.2919146000", \ - "0.1100769000, 0.1137650000, 0.1218525000, 0.1377983000, 0.1676056000, 0.2240233000, 0.3367694000", \ - "0.1488492000, 0.1543790000, 0.1659896000, 0.1882898000, 0.2296369000, 0.3036101000, 0.4341680000", \ - "0.1728060000, 0.1823630000, 0.1987294000, 0.2329437000, 0.2966524000, 0.4070848000, 0.5912605000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.2670215000, 0.2761138000, 0.3004847000, 0.3490586000, 0.4582314000, 0.6986693000, 1.2315773000", \ - "0.2706353000, 0.2809309000, 0.3032999000, 0.3534887000, 0.4619860000, 0.7027919000, 1.2360022000", \ - "0.2806670000, 0.2905228000, 0.3133372000, 0.3632538000, 0.4734463000, 0.7148649000, 1.2485331000", \ - "0.3058245000, 0.3147163000, 0.3387601000, 0.3891069000, 0.4990109000, 0.7404989000, 1.2750695000", \ - "0.3586493000, 0.3686640000, 0.3908930000, 0.4410375000, 0.5510479000, 0.7923591000, 1.3275153000", \ - "0.4597230000, 0.4708154000, 0.4935078000, 0.5475275000, 0.6568509000, 0.8979494000, 1.4328908000", \ - "0.6234902000, 0.6367819000, 0.6639899000, 0.7269311000, 0.8537733000, 1.1140318000, 1.6533099000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0372507000, 0.0404423000, 0.0475130000, 0.0628382000, 0.0950102000, 0.1624379000, 0.3081947000", \ - "0.0367901000, 0.0400572000, 0.0471585000, 0.0623980000, 0.0946508000, 0.1619007000, 0.3082452000", \ - "0.0364779000, 0.0395791000, 0.0466381000, 0.0617746000, 0.0940368000, 0.1617069000, 0.3079173000", \ - "0.0425926000, 0.0452362000, 0.0510514000, 0.0642526000, 0.0946387000, 0.1613167000, 0.3077286000", \ - "0.0616811000, 0.0643337000, 0.0700814000, 0.0828696000, 0.1103735000, 0.1690030000, 0.3095447000", \ - "0.0994191000, 0.1027620000, 0.1102436000, 0.1255932000, 0.1562363000, 0.2162899000, 0.3426906000", \ - "0.1684117000, 0.1738833000, 0.1851487000, 0.2053329000, 0.2479606000, 0.3222781000, 0.4576859000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.1708300000, 0.1837368000, 0.2136142000, 0.2784755000, 0.4232365000, 0.7444294000, 1.4587457000", \ - "0.1710782000, 0.1837628000, 0.2130756000, 0.2789063000, 0.4235401000, 0.7445505000, 1.4588462000", \ - "0.1708102000, 0.1843895000, 0.2135105000, 0.2788327000, 0.4232251000, 0.7444458000, 1.4586672000", \ - "0.1708135000, 0.1840149000, 0.2135749000, 0.2783518000, 0.4230420000, 0.7440101000, 1.4584550000", \ - "0.1712798000, 0.1843720000, 0.2135717000, 0.2785255000, 0.4231150000, 0.7442328000, 1.4588951000", \ - "0.1891999000, 0.2019084000, 0.2295816000, 0.2903534000, 0.4306114000, 0.7452732000, 1.4587642000", \ - "0.2373961000, 0.2509949000, 0.2803544000, 0.3460442000, 0.4870421000, 0.7878138000, 1.4773424000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0446611000, 0.0473349000, 0.0530266000, 0.0648208000, 0.0893415000, 0.1401413000, 0.2493034000", \ - "0.0495753000, 0.0522095000, 0.0579249000, 0.0697906000, 0.0941281000, 0.1451197000, 0.2542757000", \ - "0.0600410000, 0.0626755000, 0.0682636000, 0.0800600000, 0.1043527000, 0.1552520000, 0.2643517000", \ - "0.0797407000, 0.0825918000, 0.0884423000, 0.1005505000, 0.1248262000, 0.1756774000, 0.2847833000", \ - "0.1087052000, 0.1125462000, 0.1204701000, 0.1358792000, 0.1652540000, 0.2202153000, 0.3305545000", \ - "0.1402395000, 0.1460595000, 0.1572674000, 0.1809185000, 0.2226059000, 0.2971873000, 0.4275930000", \ - "0.1510378000, 0.1593405000, 0.1785221000, 0.2144312000, 0.2799615000, 0.3946140000, 0.5829141000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.2492224000, 0.2597917000, 0.2823301000, 0.3313352000, 0.4401667000, 0.6802499000, 1.2134838000", \ - "0.2513112000, 0.2617613000, 0.2829972000, 0.3345342000, 0.4437450000, 0.6840825000, 1.2172886000", \ - "0.2599914000, 0.2702679000, 0.2932664000, 0.3430850000, 0.4528191000, 0.6941507000, 1.2278050000", \ - "0.2821419000, 0.2928727000, 0.3151357000, 0.3663485000, 0.4764477000, 0.7180856000, 1.2530215000", \ - "0.3350148000, 0.3449879000, 0.3674101000, 0.4171523000, 0.5266311000, 0.7693098000, 1.3040442000", \ - "0.4366142000, 0.4482389000, 0.4728323000, 0.5271739000, 0.6389702000, 0.8797972000, 1.4146729000", \ - "0.6099861000, 0.6238154000, 0.6551100000, 0.7237849000, 0.8566305000, 1.1259179000, 1.6669001000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0341926000, 0.0369217000, 0.0432341000, 0.0570407000, 0.0866404000, 0.1516937000, 0.2966217000", \ - "0.0340501000, 0.0367256000, 0.0431537000, 0.0569009000, 0.0866070000, 0.1517624000, 0.2961898000", \ - "0.0336913000, 0.0365619000, 0.0427801000, 0.0565937000, 0.0863125000, 0.1515539000, 0.2964793000", \ - "0.0388455000, 0.0413266000, 0.0468456000, 0.0590478000, 0.0872257000, 0.1514445000, 0.2965575000", \ - "0.0558130000, 0.0583569000, 0.0641141000, 0.0763835000, 0.1032020000, 0.1602519000, 0.2982068000", \ - "0.0916028000, 0.0947332000, 0.1026776000, 0.1178150000, 0.1489322000, 0.2076927000, 0.3318876000", \ - "0.1580161000, 0.1634492000, 0.1749964000, 0.1979068000, 0.2395184000, 0.3148320000, 0.4532927000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.1707618000, 0.1843440000, 0.2130538000, 0.2789318000, 0.4232771000, 0.7446754000, 1.4586893000", \ - "0.1709177000, 0.1842654000, 0.2129983000, 0.2783268000, 0.4231302000, 0.7444363000, 1.4588816000", \ - "0.1711933000, 0.1843720000, 0.2137266000, 0.2789257000, 0.4232705000, 0.7444504000, 1.4583564000", \ - "0.1709265000, 0.1835887000, 0.2134285000, 0.2782188000, 0.4230081000, 0.7444811000, 1.4589544000", \ - "0.1722923000, 0.1851878000, 0.2147239000, 0.2791199000, 0.4234573000, 0.7458196000, 1.4587931000", \ - "0.2003392000, 0.2127042000, 0.2404478000, 0.2994739000, 0.4359682000, 0.7470813000, 1.4610204000", \ - "0.2681970000, 0.2824629000, 0.3111356000, 0.3754830000, 0.5116112000, 0.8011812000, 1.4763102000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0419938000, 0.0442191000, 0.0488922000, 0.0589338000, 0.0803662000, 0.1265421000, 0.2282707000", \ - "0.0468303000, 0.0491035000, 0.0538092000, 0.0638830000, 0.0853505000, 0.1315580000, 0.2333615000", \ - "0.0569834000, 0.0591902000, 0.0640273000, 0.0741906000, 0.0957025000, 0.1419893000, 0.2439307000", \ - "0.0746121000, 0.0772037000, 0.0825446000, 0.0937729000, 0.1159792000, 0.1625152000, 0.2645925000", \ - "0.0977279000, 0.1016523000, 0.1092752000, 0.1247179000, 0.1531679000, 0.2060919000, 0.3100470000", \ - "0.1193739000, 0.1244569000, 0.1366197000, 0.1595101000, 0.2035302000, 0.2782459000, 0.4044347000", \ - "0.1102192000, 0.1191219000, 0.1383975000, 0.1765333000, 0.2449005000, 0.3634688000, 0.5504077000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.2141922000, 0.2244692000, 0.2456154000, 0.2968934000, 0.4057210000, 0.6456202000, 1.1784339000", \ - "0.2150490000, 0.2251053000, 0.2493391000, 0.2982140000, 0.4078562000, 0.6485497000, 1.1818703000", \ - "0.2232953000, 0.2329558000, 0.2572581000, 0.3067049000, 0.4168193000, 0.6583388000, 1.1921691000", \ - "0.2480666000, 0.2584631000, 0.2801566000, 0.3314588000, 0.4413446000, 0.6829214000, 1.2169752000", \ - "0.3032226000, 0.3130327000, 0.3362313000, 0.3864259000, 0.4958077000, 0.7372738000, 1.2722489000", \ - "0.4166379000, 0.4287206000, 0.4547050000, 0.5112424000, 0.6260391000, 0.8673167000, 1.4021214000", \ - "0.6110388000, 0.6285708000, 0.6652520000, 0.7402409000, 0.8849326000, 1.1658021000, 1.7060506000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0247722000, 0.0272492000, 0.0327629000, 0.0450586000, 0.0726705000, 0.1341424000, 0.2711894000", \ - "0.0247701000, 0.0272369000, 0.0327302000, 0.0450578000, 0.0726584000, 0.1341415000, 0.2716888000", \ - "0.0247754000, 0.0272073000, 0.0327315000, 0.0450793000, 0.0726391000, 0.1340983000, 0.2717790000", \ - "0.0301862000, 0.0324611000, 0.0375668000, 0.0486164000, 0.0743303000, 0.1342739000, 0.2718040000", \ - "0.0460940000, 0.0485569000, 0.0543150000, 0.0663331000, 0.0917473000, 0.1453120000, 0.2745060000", \ - "0.0794655000, 0.0831959000, 0.0909208000, 0.1065515000, 0.1374586000, 0.1955429000, 0.3123410000", \ - "0.1433022000, 0.1491906000, 0.1605566000, 0.1843076000, 0.2276678000, 0.3012941000, 0.4345485000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.1708460000, 0.1842304000, 0.2128885000, 0.2783712000, 0.4230732000, 0.7444921000, 1.4605674000", \ - "0.1708722000, 0.1840154000, 0.2137417000, 0.2784716000, 0.4231052000, 0.7443925000, 1.4612057000", \ - "0.1709095000, 0.1839916000, 0.2135467000, 0.2784738000, 0.4231974000, 0.7443734000, 1.4610978000", \ - "0.1708619000, 0.1837741000, 0.2129679000, 0.2781653000, 0.4243347000, 0.7447500000, 1.4592098000", \ - "0.1748918000, 0.1868300000, 0.2150846000, 0.2790210000, 0.4233585000, 0.7446170000, 1.4589198000", \ - "0.2112882000, 0.2247448000, 0.2506864000, 0.3070713000, 0.4395620000, 0.7498862000, 1.4585465000", \ - "0.3036634000, 0.3181883000, 0.3482069000, 0.4126213000, 0.5448100000, 0.8230111000, 1.4767729000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0323919000, 0.0343621000, 0.0386893000, 0.0478617000, 0.0679366000, 0.1122032000, 0.2107334000", \ - "0.0368802000, 0.0389452000, 0.0433804000, 0.0527463000, 0.0730635000, 0.1175659000, 0.2160976000", \ - "0.0463223000, 0.0485689000, 0.0532392000, 0.0629485000, 0.0834530000, 0.1280448000, 0.2271223000", \ - "0.0599755000, 0.0629929000, 0.0690255000, 0.0809658000, 0.1036563000, 0.1488331000, 0.2482513000", \ - "0.0744461000, 0.0788944000, 0.0883481000, 0.1060430000, 0.1374727000, 0.1923328000, 0.2947305000", \ - "0.0782540000, 0.0848882000, 0.1006128000, 0.1291531000, 0.1786188000, 0.2589726000, 0.3884151000", \ - "0.0409084000, 0.0530932000, 0.0779059000, 0.1245536000, 0.2054975000, 0.3333436000, 0.5287991000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.1434688000, 0.1533861000, 0.1766784000, 0.2256514000, 0.3350441000, 0.5758188000, 1.1088706000", \ - "0.1438429000, 0.1541807000, 0.1770903000, 0.2272946000, 0.3371908000, 0.5778926000, 1.1115596000", \ - "0.1497107000, 0.1602581000, 0.1835286000, 0.2344843000, 0.3450110000, 0.5869307000, 1.1210332000", \ - "0.1729603000, 0.1827219000, 0.2056495000, 0.2551276000, 0.3662949000, 0.6085577000, 1.1445332000", \ - "0.2353842000, 0.2444384000, 0.2655599000, 0.3143948000, 0.4233859000, 0.6647032000, 1.2001636000", \ - "0.3621727000, 0.3746490000, 0.3999583000, 0.4564439000, 0.5644828000, 0.8001102000, 1.3325289000", \ - "0.5659168000, 0.5833746000, 0.6206044000, 0.7000014000, 0.8521641000, 1.1250708000, 1.6504381000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0143388000, 0.0167343000, 0.0221990000, 0.0342552000, 0.0614580000, 0.1226866000, 0.2565164000", \ - "0.0144273000, 0.0167773000, 0.0221791000, 0.0343762000, 0.0613236000, 0.1225101000, 0.2565369000", \ - "0.0156013000, 0.0177145000, 0.0228016000, 0.0344118000, 0.0613532000, 0.1216185000, 0.2577362000", \ - "0.0227581000, 0.0249229000, 0.0297769000, 0.0406175000, 0.0644782000, 0.1223706000, 0.2585189000", \ - "0.0392337000, 0.0420094000, 0.0476226000, 0.0598511000, 0.0843414000, 0.1366505000, 0.2599277000", \ - "0.0722488000, 0.0765264000, 0.0842057000, 0.1007838000, 0.1311250000, 0.1882817000, 0.3030539000", \ - "0.1387271000, 0.1441691000, 0.1557800000, 0.1793846000, 0.2229836000, 0.2962862000, 0.4255201000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.1681662000, 0.1813889000, 0.2115807000, 0.2778613000, 0.4234040000, 0.7443108000, 1.4638086000", \ - "0.1670720000, 0.1812101000, 0.2115842000, 0.2774473000, 0.4230766000, 0.7447241000, 1.4589815000", \ - "0.1655011000, 0.1791930000, 0.2098111000, 0.2773165000, 0.4233984000, 0.7441132000, 1.4601907000", \ - "0.1607823000, 0.1748659000, 0.2062296000, 0.2752094000, 0.4226293000, 0.7443834000, 1.4597586000", \ - "0.1686735000, 0.1808355000, 0.2080538000, 0.2718662000, 0.4179155000, 0.7443803000, 1.4594108000", \ - "0.2106625000, 0.2254803000, 0.2569849000, 0.3171737000, 0.4429604000, 0.7437337000, 1.4591222000", \ - "0.2900059000, 0.3085730000, 0.3494771000, 0.4272372000, 0.5728739000, 0.8447615000, 1.4837760000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0304651000, 0.0333375000, 0.0395232000, 0.0522744000, 0.0783842000, 0.1320141000, 0.2445576000", \ - "0.0345394000, 0.0374201000, 0.0434756000, 0.0562986000, 0.0825138000, 0.1362366000, 0.2488141000", \ - "0.0467764000, 0.0491673000, 0.0547196000, 0.0669925000, 0.0926379000, 0.1464438000, 0.2591965000", \ - "0.0715593000, 0.0748986000, 0.0815037000, 0.0940549000, 0.1179393000, 0.1710515000, 0.2835331000", \ - "0.1065585000, 0.1110837000, 0.1203815000, 0.1386804000, 0.1722329000, 0.2297007000, 0.3404142000", \ - "0.1483230000, 0.1547596000, 0.1681310000, 0.1949067000, 0.2440937000, 0.3298191000, 0.4706961000", \ - "0.1854450000, 0.1945855000, 0.2137841000, 0.2513820000, 0.3246683000, 0.4537426000, 0.6661133000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0217858000, 0.0241133000, 0.0291018000, 0.0395796000, 0.0618274000, 0.1106603000, 0.2188746000", \ - "0.0270020000, 0.0292379000, 0.0341279000, 0.0446821000, 0.0672185000, 0.1162221000, 0.2268534000", \ - "0.0394037000, 0.0421580000, 0.0472779000, 0.0575494000, 0.0800054000, 0.1292726000, 0.2378181000", \ - "0.0584983000, 0.0628023000, 0.0711746000, 0.0863126000, 0.1107755000, 0.1600386000, 0.2673105000", \ - "0.0873192000, 0.0942795000, 0.1078723000, 0.1320256000, 0.1720097000, 0.2324017000, 0.3406694000", \ - "0.1335040000, 0.1439314000, 0.1646368000, 0.2022817000, 0.2663232000, 0.3638640000, 0.5082657000", \ - "0.2139516000, 0.2288519000, 0.2589016000, 0.3142798000, 0.4109871000, 0.5666537000, 0.7982673000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0353865000, 0.0389034000, 0.0457540000, 0.0609745000, 0.0930194000, 0.1607494000, 0.3076238000", \ - "0.0345348000, 0.0379639000, 0.0454695000, 0.0608925000, 0.0931571000, 0.1609912000, 0.3075462000", \ - "0.0353204000, 0.0385322000, 0.0448283000, 0.0597629000, 0.0924647000, 0.1607053000, 0.3075828000", \ - "0.0469064000, 0.0498177000, 0.0558201000, 0.0671517000, 0.0948278000, 0.1600038000, 0.3072393000", \ - "0.0689833000, 0.0732683000, 0.0807411000, 0.0958119000, 0.1233219000, 0.1758369000, 0.3092174000", \ - "0.1091997000, 0.1149265000, 0.1263469000, 0.1475684000, 0.1854061000, 0.2507400000, 0.3654808000", \ - "0.1752892000, 0.1837823000, 0.2014253000, 0.2353336000, 0.2922688000, 0.3862786000, 0.5441435000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011173300, 0.0024968700, 0.0055796900, 0.0124688000, 0.0278636000, 0.0622658000"); - values("0.0211534000, 0.0242293000, 0.0315416000, 0.0470944000, 0.0817850000, 0.1564495000, 0.3187726000", \ - "0.0212907000, 0.0243454000, 0.0315353000, 0.0472970000, 0.0818091000, 0.1564122000, 0.3194576000", \ - "0.0268558000, 0.0290962000, 0.0343151000, 0.0480175000, 0.0818868000, 0.1563561000, 0.3189890000", \ - "0.0473608000, 0.0492428000, 0.0533405000, 0.0618764000, 0.0880740000, 0.1567718000, 0.3189948000", \ - "0.0868585000, 0.0884833000, 0.0926782000, 0.1035726000, 0.1257457000, 0.1770864000, 0.3210621000", \ - "0.1578728000, 0.1598804000, 0.1653128000, 0.1796124000, 0.2102217000, 0.2657995000, 0.3765106000", \ - "0.2921765000, 0.2934500000, 0.2982515000, 0.3152623000, 0.3582425000, 0.4413671000, 0.5781713000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__o41ai_4") { - leakage_power () { - value : 0.0056372000; - when : "!A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0170682000; - when : "!A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0115471000; - when : "!A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015165000; - when : "!A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0100833000; - when : "!A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015152000; - when : "!A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0077004000; - when : "!A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015183000; - when : "!A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0099986000; - when : "!A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015165000; - when : "!A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0077019000; - when : "!A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015208000; - when : "!A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0077149000; - when : "!A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015176000; - when : "!A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0373424000; - when : "!A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015071000; - when : "!A1&A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0098375000; - when : "A1&!A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015168000; - when : "A1&!A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0076912000; - when : "A1&!A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015126000; - when : "A1&!A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0081314000; - when : "A1&!A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015284000; - when : "A1&!A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0078103000; - when : "A1&!A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015149000; - when : "A1&!A2&A3&A4&!B1"; - } - leakage_power () { - value : 0.0083207000; - when : "A1&A2&!A3&!A4&B1"; - } - leakage_power () { - value : 0.0015105000; - when : "A1&A2&!A3&!A4&!B1"; - } - leakage_power () { - value : 0.0376818000; - when : "A1&A2&!A3&A4&B1"; - } - leakage_power () { - value : 0.0015146000; - when : "A1&A2&!A3&A4&!B1"; - } - leakage_power () { - value : 0.0577513000; - when : "A1&A2&A3&!A4&B1"; - } - leakage_power () { - value : 0.0015115000; - when : "A1&A2&A3&!A4&!B1"; - } - leakage_power () { - value : 0.0373388000; - when : "A1&A2&A3&A4&B1"; - } - leakage_power () { - value : 0.0015165000; - when : "A1&A2&A3&A4&!B1"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__o41ai"; - cell_leakage_power : 0.0097529590; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A1") { - capacitance : 0.0086400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0082090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158266000, 0.0158195000, 0.0158030000, 0.0157976000, 0.0157852000, 0.0157569000, 0.0156916000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015751600, -0.015747800, -0.015739100, -0.015740600, -0.015744100, -0.015752300, -0.015770900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090710000; - } - pin ("A2") { - capacitance : 0.0084130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158447000, 0.0158326000, 0.0158048000, 0.0158012000, 0.0157932000, 0.0157747000, 0.0157320000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015802800, -0.015788600, -0.015755900, -0.015751400, -0.015741000, -0.015717000, -0.015661700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089800000; - } - pin ("A3") { - capacitance : 0.0083630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158071000, 0.0157967000, 0.0157727000, 0.0157667000, 0.0157528000, 0.0157210000, 0.0156478000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015781400, -0.015766400, -0.015731700, -0.015723100, -0.015703300, -0.015657800, -0.015552600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0089770000; - } - pin ("A4") { - capacitance : 0.0084050000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0077110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0158524000, 0.0158443000, 0.0158256000, 0.0158204000, 0.0158083000, 0.0157806000, 0.0157167000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.015811800, -0.015801500, -0.015778000, -0.015772300, -0.015759400, -0.015729700, -0.015661000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090990000; - } - pin ("B1") { - capacitance : 0.0086500000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0084760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184853000, 0.0184942000, 0.0185147000, 0.0185125000, 0.0185074000, 0.0184955000, 0.0184682000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002287600, -0.002356700, -0.002515900, -0.002417300, -0.002189900, -0.001665700, -0.000457400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0088240000; - } - pin ("Y") { - direction : "output"; - function : "(!A1&!A2&!A3&!A4) | (!B1)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0335820000, 0.0324435000, 0.0295460000, 0.0224904000, 0.0052049000, -0.037058000, -0.140648200", \ - "0.0330832000, 0.0319430000, 0.0290717000, 0.0220002000, 0.0046753000, -0.037554100, -0.141212400", \ - "0.0325117000, 0.0313173000, 0.0285060000, 0.0214064000, 0.0040939000, -0.038163400, -0.141722400", \ - "0.0319710000, 0.0307878000, 0.0279193000, 0.0208373000, 0.0035437000, -0.038664400, -0.142242900", \ - "0.0314140000, 0.0302145000, 0.0274018000, 0.0205042000, 0.0033479000, -0.038836100, -0.142515800", \ - "0.0309295000, 0.0297733000, 0.0269733000, 0.0200110000, 0.0026365000, -0.039372800, -0.142856700", \ - "0.0334235000, 0.0323313000, 0.0294552000, 0.0222344000, 0.0049136000, -0.037904700, -0.142515000"); - } - related_pin : "A1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0650367000, 0.0661575000, 0.0691201000, 0.0761574000, 0.0934381000, 0.1358574000, 0.2393663000", \ - "0.0644364000, 0.0655722000, 0.0685828000, 0.0756386000, 0.0929762000, 0.1354170000, 0.2388989000", \ - "0.0637364000, 0.0649043000, 0.0679057000, 0.0750446000, 0.0925173000, 0.1350812000, 0.2387580000", \ - "0.0631451000, 0.0642617000, 0.0673229000, 0.0744255000, 0.0919035000, 0.1346335000, 0.2383338000", \ - "0.0626666000, 0.0638319000, 0.0668468000, 0.0738342000, 0.0913011000, 0.1340561000, 0.2378856000", \ - "0.0623043000, 0.0634736000, 0.0664677000, 0.0735471000, 0.0909527000, 0.1335741000, 0.2373883000", \ - "0.0624146000, 0.0635159000, 0.0664394000, 0.0736058000, 0.0910954000, 0.1334086000, 0.2373376000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0271840000, 0.0260238000, 0.0231744000, 0.0160986000, -0.001123100, -0.043286400, -0.147317600", \ - "0.0270906000, 0.0259134000, 0.0230745000, 0.0160083000, -0.001237300, -0.043422900, -0.147418600", \ - "0.0267595000, 0.0256135000, 0.0227492000, 0.0157037000, -0.001503900, -0.043685300, -0.147618000", \ - "0.0261862000, 0.0250665000, 0.0222073000, 0.0152184000, -0.001970000, -0.044074200, -0.148026500", \ - "0.0252255000, 0.0241158000, 0.0212779000, 0.0144184000, -0.002495500, -0.044368000, -0.148312300", \ - "0.0254154000, 0.0242050000, 0.0214534000, 0.0144165000, -0.003078300, -0.045308100, -0.148707400", \ - "0.0270820000, 0.0258100000, 0.0229209000, 0.0159603000, -0.001635000, -0.044271100, -0.148968000"); - } - related_pin : "A2"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0558578000, 0.0570403000, 0.0599761000, 0.0670868000, 0.0844170000, 0.1268955000, 0.2304720000", \ - "0.0553655000, 0.0563907000, 0.0592948000, 0.0665066000, 0.0838841000, 0.1263247000, 0.2298458000", \ - "0.0545584000, 0.0557316000, 0.0585388000, 0.0657728000, 0.0833295000, 0.1259327000, 0.2296187000", \ - "0.0537219000, 0.0549009000, 0.0579246000, 0.0650859000, 0.0825951000, 0.1254036000, 0.2290576000", \ - "0.0531547000, 0.0544072000, 0.0572275000, 0.0645619000, 0.0818380000, 0.1245811000, 0.2285115000", \ - "0.0528763000, 0.0540616000, 0.0569890000, 0.0641297000, 0.0815995000, 0.1241540000, 0.2279855000", \ - "0.0530971000, 0.0541906000, 0.0571569000, 0.0643182000, 0.0818878000, 0.1243254000, 0.2281407000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0215374000, 0.0203738000, 0.0175434000, 0.0105294000, -0.006693300, -0.049160400, -0.153367900", \ - "0.0214295000, 0.0202891000, 0.0174680000, 0.0105139000, -0.006704200, -0.049129000, -0.153472600", \ - "0.0211045000, 0.0199938000, 0.0171904000, 0.0103153000, -0.006761500, -0.049056900, -0.153290800", \ - "0.0202962000, 0.0191982000, 0.0164434000, 0.0097559000, -0.007159400, -0.049150900, -0.153211300", \ - "0.0192500000, 0.0181344000, 0.0153643000, 0.0087022000, -0.008016700, -0.049627200, -0.153434900", \ - "0.0192099000, 0.0180596000, 0.0152112000, 0.0083484000, -0.008616200, -0.050846900, -0.154152800", \ - "0.0205341000, 0.0194331000, 0.0164513000, 0.0093695000, -0.008049600, -0.050408400, -0.154741900"); - } - related_pin : "A3"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0475283000, 0.0487276000, 0.0516955000, 0.0587332000, 0.0761266000, 0.1184928000, 0.2219116000", \ - "0.0468133000, 0.0480872000, 0.0510015000, 0.0580845000, 0.0755721000, 0.1180353000, 0.2216737000", \ - "0.0459089000, 0.0472069000, 0.0501152000, 0.0572717000, 0.0749028000, 0.1175727000, 0.2212160000", \ - "0.0450701000, 0.0462602000, 0.0492323000, 0.0565835000, 0.0740867000, 0.1169028000, 0.2208559000", \ - "0.0445660000, 0.0457841000, 0.0486648000, 0.0557806000, 0.0733014000, 0.1161179000, 0.2201500000", \ - "0.0444623000, 0.0456160000, 0.0485402000, 0.0557393000, 0.0732287000, 0.1156640000, 0.2194421000", \ - "0.0451312000, 0.0463307000, 0.0491173000, 0.0561444000, 0.0734796000, 0.1161463000, 0.2198492000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0142543000, 0.0131060000, 0.0103101000, 0.0032949000, -0.014005400, -0.056534900, -0.160995800", \ - "0.0136497000, 0.0125911000, 0.0098835000, 0.0030893000, -0.013939200, -0.056230400, -0.160619300", \ - "0.0126907000, 0.0116535000, 0.0090657000, 0.0025350000, -0.014123900, -0.056127000, -0.160286200", \ - "0.0116297000, 0.0105943000, 0.0080611000, 0.0016132000, -0.014733800, -0.056299500, -0.160115000", \ - "0.0112440000, 0.0102436000, 0.0074503000, 0.0006120000, -0.015707600, -0.056961400, -0.160370600", \ - "0.0112679000, 0.0101296000, 0.0073202000, 0.0004801000, -0.016225400, -0.058225100, -0.161189000", \ - "0.0136027000, 0.0123589000, 0.0094226000, 0.0020481000, -0.015491300, -0.057858100, -0.161795400"); - } - related_pin : "A4"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0382044000, 0.0393983000, 0.0424063000, 0.0495168000, 0.0668340000, 0.1092937000, 0.2129387000", \ - "0.0371609000, 0.0383179000, 0.0413915000, 0.0485635000, 0.0661583000, 0.1088135000, 0.2125104000", \ - "0.0357904000, 0.0370750000, 0.0400302000, 0.0476132000, 0.0651539000, 0.1081262000, 0.2120318000", \ - "0.0349840000, 0.0361442000, 0.0389856000, 0.0465519000, 0.0642280000, 0.1074463000, 0.2114504000", \ - "0.0347589000, 0.0359183000, 0.0388442000, 0.0459874000, 0.0632012000, 0.1059796000, 0.2105561000", \ - "0.0367211000, 0.0377362000, 0.0405825000, 0.0477389000, 0.0652333000, 0.1065435000, 0.2103172000", \ - "0.0412427000, 0.0425878000, 0.0459413000, 0.0528042000, 0.0691260000, 0.1099306000, 0.2121374000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0194462000, 0.0183427000, 0.0156466000, 0.0089152000, -0.008061700, -0.050084500, -0.153642700", \ - "0.0189340000, 0.0178404000, 0.0151883000, 0.0084428000, -0.008421900, -0.050227500, -0.153604900", \ - "0.0185334000, 0.0174224000, 0.0146848000, 0.0079166000, -0.008874100, -0.050544700, -0.153712300", \ - "0.0178789000, 0.0167820000, 0.0140818000, 0.0072318000, -0.009686200, -0.051367100, -0.154172700", \ - "0.0180242000, 0.0168514000, 0.0139951000, 0.0070528000, -0.009894500, -0.052037000, -0.155008800", \ - "0.0186839000, 0.0174866000, 0.0145726000, 0.0074201000, -0.009932200, -0.051979700, -0.155753000", \ - "0.0240363000, 0.0227711000, 0.0196540000, 0.0122375000, -0.005496300, -0.048353000, -0.155740100"); - } - related_pin : "B1"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012265480, 0.0030088420, 0.0073809800, 0.0181062600, 0.0444164000, 0.1089577000"); - values("0.0367253000, 0.0381901000, 0.0416180000, 0.0495376000, 0.0675671000, 0.1104151000, 0.2144057000", \ - "0.0359024000, 0.0372744000, 0.0406761000, 0.0487778000, 0.0670774000, 0.1100779000, 0.2145769000", \ - "0.0351943000, 0.0365940000, 0.0398264000, 0.0475050000, 0.0659873000, 0.1096563000, 0.2136787000", \ - "0.0350505000, 0.0362855000, 0.0392302000, 0.0468243000, 0.0647865000, 0.1082682000, 0.2130774000", \ - "0.0357339000, 0.0368471000, 0.0396455000, 0.0466875000, 0.0641756000, 0.1072048000, 0.2119991000", \ - "0.0386914000, 0.0398449000, 0.0424580000, 0.0492047000, 0.0659899000, 0.1086017000, 0.2118225000", \ - "0.0460743000, 0.0470550000, 0.0503741000, 0.0560320000, 0.0710716000, 0.1124830000, 0.2167992000"); - } - } - max_capacitance : 0.1089580000; - max_transition : 1.4948920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0490083000, 0.0511526000, 0.0560846000, 0.0676698000, 0.0937063000, 0.1519649000, 0.2835788000", \ - "0.0536368000, 0.0557651000, 0.0606135000, 0.0721033000, 0.0980456000, 0.1561501000, 0.2880506000", \ - "0.0630271000, 0.0649874000, 0.0699070000, 0.0812085000, 0.1069333000, 0.1648506000, 0.2965582000", \ - "0.0800484000, 0.0822212000, 0.0872914000, 0.0985812000, 0.1240464000, 0.1814922000, 0.3130041000", \ - "0.1069422000, 0.1094968000, 0.1153147000, 0.1289086000, 0.1570291000, 0.2169911000, 0.3487538000", \ - "0.1397497000, 0.1431039000, 0.1511453000, 0.1700394000, 0.2073803000, 0.2811576000, 0.4267670000", \ - "0.1533173000, 0.1582672000, 0.1708541000, 0.1974145000, 0.2545746000, 0.3614823000, 0.5563700000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.2869563000, 0.2928388000, 0.3113121000, 0.3515894000, 0.4487748000, 0.6829688000, 1.2534348000", \ - "0.2900632000, 0.2960218000, 0.3146005000, 0.3549624000, 0.4525935000, 0.6868908000, 1.2574926000", \ - "0.3008525000, 0.3065675000, 0.3251295000, 0.3659378000, 0.4632137000, 0.6987697000, 1.2700392000", \ - "0.3260999000, 0.3319910000, 0.3505796000, 0.3911735000, 0.4894476000, 0.7250353000, 1.2970159000", \ - "0.3799177000, 0.3878055000, 0.4044325000, 0.4442618000, 0.5420152000, 0.7780919000, 1.3514118000", \ - "0.4851879000, 0.4921095000, 0.5097973000, 0.5533713000, 0.6510785000, 0.8862163000, 1.4585120000", \ - "0.6606019000, 0.6672498000, 0.6900283000, 0.7381128000, 0.8518970000, 1.1052359000, 1.6832666000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0482631000, 0.0505753000, 0.0562608000, 0.0699239000, 0.1016926000, 0.1745265000, 0.3476280000", \ - "0.0476068000, 0.0499514000, 0.0556194000, 0.0692252000, 0.1010610000, 0.1741124000, 0.3472198000", \ - "0.0469605000, 0.0491572000, 0.0549130000, 0.0684395000, 0.1004222000, 0.1734823000, 0.3469059000", \ - "0.0509562000, 0.0529424000, 0.0581727000, 0.0703212000, 0.1008020000, 0.1729656000, 0.3470362000", \ - "0.0662301000, 0.0680428000, 0.0728795000, 0.0847975000, 0.1129618000, 0.1791733000, 0.3477794000", \ - "0.1026806000, 0.1048377000, 0.1096522000, 0.1222225000, 0.1510881000, 0.2164035000, 0.3718094000", \ - "0.1698206000, 0.1735158000, 0.1816030000, 0.1968595000, 0.2352873000, 0.3116289000, 0.4706067000"); - } - related_pin : "A1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1864820000, 0.1947768000, 0.2170005000, 0.2692028000, 0.3978421000, 0.7109061000, 1.4776961000", \ - "0.1864812000, 0.1947891000, 0.2170494000, 0.2692639000, 0.3976831000, 0.7106363000, 1.4737536000", \ - "0.1864935000, 0.1950739000, 0.2170403000, 0.2692662000, 0.3979665000, 0.7109464000, 1.4744587000", \ - "0.1865171000, 0.1950474000, 0.2171293000, 0.2692656000, 0.3974930000, 0.7106837000, 1.4737628000", \ - "0.1868338000, 0.1959517000, 0.2171957000, 0.2698220000, 0.3981984000, 0.7112498000, 1.4739823000", \ - "0.2030238000, 0.2116545000, 0.2311655000, 0.2807555000, 0.4049114000, 0.7123855000, 1.4741923000", \ - "0.2479497000, 0.2564829000, 0.2787927000, 0.3309706000, 0.4569943000, 0.7518285000, 1.4873726000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0510660000, 0.0529704000, 0.0575844000, 0.0681593000, 0.0921550000, 0.1461061000, 0.2722466000", \ - "0.0557837000, 0.0576590000, 0.0622711000, 0.0728504000, 0.0967531000, 0.1509027000, 0.2771068000", \ - "0.0654992000, 0.0674587000, 0.0719601000, 0.0824859000, 0.1063885000, 0.1605037000, 0.2865176000", \ - "0.0828810000, 0.0849953000, 0.0898961000, 0.1003802000, 0.1241868000, 0.1782309000, 0.3045288000", \ - "0.1096114000, 0.1118590000, 0.1174996000, 0.1307000000, 0.1580190000, 0.2156865000, 0.3429299000", \ - "0.1374388000, 0.1408656000, 0.1493646000, 0.1684950000, 0.2068076000, 0.2808742000, 0.4260592000", \ - "0.1399760000, 0.1446460000, 0.1577857000, 0.1875136000, 0.2461262000, 0.3596246000, 0.5601840000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.2715610000, 0.2786383000, 0.2953486000, 0.3345014000, 0.4320314000, 0.6663136000, 1.2370648000", \ - "0.2730878000, 0.2799412000, 0.2969436000, 0.3361289000, 0.4339776000, 0.6690949000, 1.2399712000", \ - "0.2811841000, 0.2884343000, 0.3054336000, 0.3451345000, 0.4435763000, 0.6794290000, 1.2508009000", \ - "0.3048165000, 0.3100361000, 0.3285525000, 0.3697202000, 0.4679518000, 0.7041988000, 1.2761617000", \ - "0.3579388000, 0.3648969000, 0.3808651000, 0.4221339000, 0.5202991000, 0.7559009000, 1.3289190000", \ - "0.4640342000, 0.4713980000, 0.4904427000, 0.5333780000, 0.6336264000, 0.8691236000, 1.4418947000", \ - "0.6490644000, 0.6581979000, 0.6809544000, 0.7354345000, 0.8538060000, 1.1184510000, 1.6975281000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0424779000, 0.0444354000, 0.0495138000, 0.0615777000, 0.0903970000, 0.1595512000, 0.3297732000", \ - "0.0423466000, 0.0443054000, 0.0493844000, 0.0614210000, 0.0903383000, 0.1597429000, 0.3297302000", \ - "0.0419008000, 0.0439237000, 0.0488615000, 0.0610423000, 0.0900580000, 0.1596109000, 0.3297103000", \ - "0.0457983000, 0.0475899000, 0.0521186000, 0.0630011000, 0.0908105000, 0.1591785000, 0.3296706000", \ - "0.0599945000, 0.0618172000, 0.0664700000, 0.0772544000, 0.1039106000, 0.1669812000, 0.3313562000", \ - "0.0944545000, 0.0967843000, 0.1021694000, 0.1152098000, 0.1442397000, 0.2072179000, 0.3589196000", \ - "0.1613195000, 0.1644657000, 0.1722999000, 0.1913923000, 0.2303499000, 0.3074146000, 0.4645145000"); - } - related_pin : "A2"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1861025000, 0.1949636000, 0.2170582000, 0.2697333000, 0.3978958000, 0.7109691000, 1.4744843000", \ - "0.1864487000, 0.1951398000, 0.2162603000, 0.2695804000, 0.3979826000, 0.7109628000, 1.4744178000", \ - "0.1864236000, 0.1955827000, 0.2166183000, 0.2693269000, 0.3979531000, 0.7108997000, 1.4743297000", \ - "0.1865736000, 0.1950686000, 0.2170846000, 0.2690886000, 0.3978017000, 0.7108143000, 1.4733063000", \ - "0.1877872000, 0.1962209000, 0.2175037000, 0.2696883000, 0.3977748000, 0.7104258000, 1.4739217000", \ - "0.2134752000, 0.2217074000, 0.2418359000, 0.2898713000, 0.4108303000, 0.7137280000, 1.4786659000", \ - "0.2795046000, 0.2882462000, 0.3108082000, 0.3612736000, 0.4833170000, 0.7670845000, 1.4922815000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0483590000, 0.0499543000, 0.0536515000, 0.0625488000, 0.0829409000, 0.1316637000, 0.2485757000", \ - "0.0530040000, 0.0546411000, 0.0583621000, 0.0672699000, 0.0877483000, 0.1364259000, 0.2534928000", \ - "0.0627014000, 0.0643679000, 0.0680854000, 0.0770266000, 0.0977942000, 0.1465093000, 0.2634531000", \ - "0.0797623000, 0.0813707000, 0.0855734000, 0.0953700000, 0.1168744000, 0.1658286000, 0.2831141000", \ - "0.1027560000, 0.1050549000, 0.1103894000, 0.1237321000, 0.1501636000, 0.2054995000, 0.3250085000", \ - "0.1202724000, 0.1246656000, 0.1332449000, 0.1526536000, 0.1933606000, 0.2707146000, 0.4127784000", \ - "0.1041635000, 0.1102584000, 0.1250335000, 0.1563900000, 0.2209331000, 0.3416762000, 0.5485217000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.2343357000, 0.2394189000, 0.2580980000, 0.2984338000, 0.3957415000, 0.6301579000, 1.2005896000", \ - "0.2350792000, 0.2409597000, 0.2594951000, 0.3003714000, 0.3979097000, 0.6326941000, 1.2036107000", \ - "0.2424012000, 0.2479126000, 0.2664497000, 0.3080854000, 0.4063223000, 0.6415273000, 1.2131678000", \ - "0.2656735000, 0.2729589000, 0.2893603000, 0.3305916000, 0.4284312000, 0.6650271000, 1.2379299000", \ - "0.3213474000, 0.3276187000, 0.3452753000, 0.3854378000, 0.4837002000, 0.7201482000, 1.2931590000", \ - "0.4400340000, 0.4480021000, 0.4675478000, 0.5116249000, 0.6147227000, 0.8505037000, 1.4237053000", \ - "0.6473486000, 0.6582161000, 0.6845082000, 0.7436492000, 0.8734888000, 1.1499590000, 1.7296478000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0300066000, 0.0317989000, 0.0361961000, 0.0469716000, 0.0735679000, 0.1390243000, 0.2998936000", \ - "0.0300315000, 0.0317803000, 0.0361930000, 0.0469604000, 0.0736788000, 0.1391957000, 0.3000570000", \ - "0.0299464000, 0.0317551000, 0.0361671000, 0.0470304000, 0.0736854000, 0.1391821000, 0.3001156000", \ - "0.0347141000, 0.0363265000, 0.0404459000, 0.0502485000, 0.0754684000, 0.1392181000, 0.2999880000", \ - "0.0499704000, 0.0518859000, 0.0562984000, 0.0667690000, 0.0914832000, 0.1495834000, 0.3027523000", \ - "0.0845448000, 0.0871555000, 0.0927802000, 0.1061181000, 0.1347457000, 0.1962902000, 0.3360435000", \ - "0.1508965000, 0.1545896000, 0.1631725000, 0.1824881000, 0.2237005000, 0.3012985000, 0.4523912000"); - } - related_pin : "A3"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1860858000, 0.1949031000, 0.2168151000, 0.2692054000, 0.3979022000, 0.7107781000, 1.4773428000", \ - "0.1859932000, 0.1951935000, 0.2169234000, 0.2690108000, 0.3977700000, 0.7108347000, 1.4736845000", \ - "0.1859763000, 0.1951674000, 0.2168084000, 0.2689977000, 0.3977796000, 0.7110261000, 1.4745091000", \ - "0.1863157000, 0.1950309000, 0.2168870000, 0.2699254000, 0.3979467000, 0.7110610000, 1.4743463000", \ - "0.1887261000, 0.1977632000, 0.2179084000, 0.2702566000, 0.3986328000, 0.7106660000, 1.4739298000", \ - "0.2254712000, 0.2334942000, 0.2519560000, 0.2984803000, 0.4152456000, 0.7167393000, 1.4743214000", \ - "0.3127773000, 0.3222217000, 0.3437242000, 0.3979010000, 0.5160199000, 0.7886937000, 1.4907872000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0354414000, 0.0367848000, 0.0401123000, 0.0478034000, 0.0659550000, 0.1097377000, 0.2175224000", \ - "0.0396798000, 0.0410764000, 0.0445390000, 0.0523398000, 0.0708026000, 0.1153219000, 0.2226897000", \ - "0.0489392000, 0.0504667000, 0.0540858000, 0.0622526000, 0.0808556000, 0.1252091000, 0.2327279000", \ - "0.0622015000, 0.0643210000, 0.0689616000, 0.0789974000, 0.1002337000, 0.1455129000, 0.2536423000", \ - "0.0750949000, 0.0783047000, 0.0857154000, 0.1006273000, 0.1302369000, 0.1856950000, 0.2976527000", \ - "0.0758268000, 0.0807743000, 0.0918401000, 0.1161558000, 0.1630993000, 0.2456146000, 0.3912635000", \ - "0.0283805000, 0.0367053000, 0.0552368000, 0.0947133000, 0.1716271000, 0.3026897000, 0.5180431000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1605711000, 0.1678798000, 0.1855995000, 0.2251851000, 0.3234600000, 0.5578819000, 1.1293945000", \ - "0.1609387000, 0.1673463000, 0.1851659000, 0.2254542000, 0.3242768000, 0.5596480000, 1.1311697000", \ - "0.1651043000, 0.1727499000, 0.1893662000, 0.2315074000, 0.3295775000, 0.5678807000, 1.1405776000", \ - "0.1874608000, 0.1942411000, 0.2103170000, 0.2523436000, 0.3515758000, 0.5884208000, 1.1630095000", \ - "0.2499389000, 0.2562588000, 0.2719996000, 0.3114279000, 0.4065110000, 0.6435445000, 1.2174921000", \ - "0.3869520000, 0.3937796000, 0.4126456000, 0.4570042000, 0.5541857000, 0.7845396000, 1.3546475000", \ - "0.6048227000, 0.6139396000, 0.6478315000, 0.7109457000, 0.8459337000, 1.1170691000, 1.6812499000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0166804000, 0.0183641000, 0.0224932000, 0.0325987000, 0.0571481000, 0.1175230000, 0.2659324000", \ - "0.0168083000, 0.0184707000, 0.0225144000, 0.0325155000, 0.0573301000, 0.1183346000, 0.2667095000", \ - "0.0177456000, 0.0192321000, 0.0230706000, 0.0327956000, 0.0573242000, 0.1177650000, 0.2667257000", \ - "0.0249206000, 0.0264810000, 0.0302396000, 0.0392752000, 0.0608538000, 0.1184647000, 0.2662661000", \ - "0.0423043000, 0.0439598000, 0.0480689000, 0.0580795000, 0.0808581000, 0.1337222000, 0.2696960000", \ - "0.0761578000, 0.0787973000, 0.0848798000, 0.0989026000, 0.1273913000, 0.1843474000, 0.3151270000", \ - "0.1446580000, 0.1486109000, 0.1567620000, 0.1760168000, 0.2173615000, 0.2921123000, 0.4351862000"); - } - related_pin : "A4"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.1839696000, 0.1930564000, 0.2147728000, 0.2684286000, 0.3975610000, 0.7110428000, 1.4758724000", \ - "0.1830854000, 0.1923783000, 0.2141102000, 0.2681881000, 0.3976263000, 0.7111610000, 1.4740719000", \ - "0.1813644000, 0.1908562000, 0.2132685000, 0.2674165000, 0.3979352000, 0.7108771000, 1.4792979000", \ - "0.1771883000, 0.1862466000, 0.2098422000, 0.2650708000, 0.3968635000, 0.7112223000, 1.4782975000", \ - "0.1813719000, 0.1893364000, 0.2108003000, 0.2615150000, 0.3921393000, 0.7131450000, 1.4748868000", \ - "0.2241334000, 0.2332119000, 0.2573929000, 0.3054527000, 0.4177911000, 0.7121687000, 1.4731767000", \ - "0.3060802000, 0.3191779000, 0.3446383000, 0.4099493000, 0.5434029000, 0.8115849000, 1.4948923000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0370563000, 0.0391612000, 0.0442085000, 0.0559199000, 0.0819657000, 0.1399856000, 0.2717058000", \ - "0.0408029000, 0.0429254000, 0.0480197000, 0.0596914000, 0.0858164000, 0.1440249000, 0.2757860000", \ - "0.0519573000, 0.0539176000, 0.0586469000, 0.0698448000, 0.0957896000, 0.1540706000, 0.2860546000", \ - "0.0783126000, 0.0805202000, 0.0862174000, 0.0971487000, 0.1208932000, 0.1775680000, 0.3094333000", \ - "0.1158211000, 0.1189690000, 0.1262199000, 0.1420656000, 0.1743723000, 0.2352782000, 0.3648649000", \ - "0.1588487000, 0.1632659000, 0.1736054000, 0.1965714000, 0.2439495000, 0.3344858000, 0.4944769000", \ - "0.1919241000, 0.1982584000, 0.2131381000, 0.2466874000, 0.3161563000, 0.4495850000, 0.6927416000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0235669000, 0.0252406000, 0.0290999000, 0.0380026000, 0.0584247000, 0.1067409000, 0.2244512000", \ - "0.0287838000, 0.0303679000, 0.0341317000, 0.0431399000, 0.0637290000, 0.1122719000, 0.2299789000", \ - "0.0417645000, 0.0436304000, 0.0473721000, 0.0559495000, 0.0764071000, 0.1252459000, 0.2430211000", \ - "0.0625638000, 0.0653669000, 0.0717599000, 0.0845222000, 0.1074660000, 0.1565159000, 0.2741808000", \ - "0.0954236000, 0.0998000000, 0.1097624000, 0.1301592000, 0.1676247000, 0.2297207000, 0.3475898000", \ - "0.1492218000, 0.1554244000, 0.1707457000, 0.2027610000, 0.2620813000, 0.3611996000, 0.5153308000", \ - "0.2442917000, 0.2541989000, 0.2765189000, 0.3234362000, 0.4138644000, 0.5705348000, 0.8202494000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0458958000, 0.0481059000, 0.0537666000, 0.0673466000, 0.0991105000, 0.1726593000, 0.3468568000", \ - "0.0454096000, 0.0478528000, 0.0536571000, 0.0672718000, 0.0991269000, 0.1726387000, 0.3465221000", \ - "0.0448701000, 0.0468657000, 0.0523964000, 0.0657934000, 0.0985888000, 0.1724802000, 0.3464710000", \ - "0.0555826000, 0.0571310000, 0.0615009000, 0.0720981000, 0.0998507000, 0.1711039000, 0.3461871000", \ - "0.0762890000, 0.0791476000, 0.0860029000, 0.0995550000, 0.1301161000, 0.1863562000, 0.3463630000", \ - "0.1183389000, 0.1223062000, 0.1313868000, 0.1514707000, 0.1908715000, 0.2599670000, 0.4004749000", \ - "0.1870598000, 0.1931494000, 0.2069710000, 0.2363024000, 0.2937759000, 0.3989376000, 0.5750747000"); - } - related_pin : "B1"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012265500, 0.0030088400, 0.0073809800, 0.0181063000, 0.0444164000, 0.1089580000"); - values("0.0232291000, 0.0251508000, 0.0302795000, 0.0433679000, 0.0741996000, 0.1475953000, 0.3223308000", \ - "0.0231154000, 0.0251103000, 0.0306438000, 0.0433114000, 0.0741506000, 0.1476254000, 0.3222497000", \ - "0.0275460000, 0.0291921000, 0.0330501000, 0.0439991000, 0.0742823000, 0.1474957000, 0.3221733000", \ - "0.0480720000, 0.0492644000, 0.0519803000, 0.0578096000, 0.0810821000, 0.1479741000, 0.3221148000", \ - "0.0869474000, 0.0879324000, 0.0911140000, 0.0994764000, 0.1192203000, 0.1691198000, 0.3238810000", \ - "0.1583393000, 0.1591714000, 0.1630235000, 0.1737499000, 0.2002360000, 0.2566353000, 0.3774692000", \ - "0.2937083000, 0.2941882000, 0.2968440000, 0.3081085000, 0.3441219000, 0.4265306000, 0.5725317000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2_0") { - leakage_power () { - value : 0.0012363000; - when : "!A&B"; - } - leakage_power () { - value : 0.0026049000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0004383000; - when : "A&B"; - } - leakage_power () { - value : 0.0007459000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__or2"; - cell_leakage_power : 0.0012563580; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017183000, 0.0017174000, 0.0017154000, 0.0017157000, 0.0017164000, 0.0017179000, 0.0017214000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001565400, -0.001593500, -0.001658200, -0.001659900, -0.001663800, -0.001672700, -0.001693400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016150000; - } - pin ("B") { - capacitance : 0.0014860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012619000, 0.0012606000, 0.0012576000, 0.0012608000, 0.0012682000, 0.0012853000, 0.0013247000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000897200, -0.000896500, -0.000894900, -0.000894800, -0.000894500, -0.000893900, -0.000892300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015730000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012105780, 0.0029309990, 0.0070964070, 0.0171815100, 0.0415991200, 0.1007180000"); - values("0.0078125000, 0.0069548000, 0.0046919000, -0.001552800, -0.017699000, -0.057256900, -0.153065200", \ - "0.0076277000, 0.0067734000, 0.0045066000, -0.001742300, -0.017870000, -0.057413400, -0.153230900", \ - "0.0074766000, 0.0066208000, 0.0042927000, -0.001931000, -0.018034200, -0.057572000, -0.153398000", \ - "0.0073300000, 0.0064324000, 0.0041689000, -0.002062300, -0.018170500, -0.057689800, -0.153512300", \ - "0.0072511000, 0.0063322000, 0.0040464000, -0.002176700, -0.018263200, -0.057751900, -0.153521600", \ - "0.0074683000, 0.0063075000, 0.0037720000, -0.002239700, -0.018277000, -0.057747800, -0.153512000", \ - "0.0086523000, 0.0075611000, 0.0047777000, -0.001859200, -0.018222400, -0.057471000, -0.153241500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012105780, 0.0029309990, 0.0070964070, 0.0171815100, 0.0415991200, 0.1007180000"); - values("0.0078077000, 0.0090223000, 0.0118674000, 0.0185794000, 0.0347034000, 0.0741248000, 0.1683972000", \ - "0.0077731000, 0.0089859000, 0.0118275000, 0.0185497000, 0.0347184000, 0.0741046000, 0.1690782000", \ - "0.0077249000, 0.0089321000, 0.0117801000, 0.0185202000, 0.0347185000, 0.0737380000, 0.1691607000", \ - "0.0075323000, 0.0087337000, 0.0115670000, 0.0183349000, 0.0346899000, 0.0736951000, 0.1682162000", \ - "0.0074818000, 0.0086137000, 0.0113845000, 0.0181343000, 0.0345470000, 0.0735848000, 0.1682023000", \ - "0.0076743000, 0.0088416000, 0.0115967000, 0.0182129000, 0.0346547000, 0.0734874000, 0.1681041000", \ - "0.0082146000, 0.0093865000, 0.0121474000, 0.0187712000, 0.0351010000, 0.0745511000, 0.1681411000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012105780, 0.0029309990, 0.0070964070, 0.0171815100, 0.0415991200, 0.1007180000"); - values("0.0071787000, 0.0063267000, 0.0040618000, -0.002158300, -0.018234400, -0.057725200, -0.153510500", \ - "0.0070349000, 0.0061502000, 0.0038910000, -0.002326100, -0.018393000, -0.057874400, -0.153661500", \ - "0.0068838000, 0.0059763000, 0.0036927000, -0.002501700, -0.018556700, -0.058039400, -0.153803600", \ - "0.0067576000, 0.0058812000, 0.0035660000, -0.002623600, -0.018662200, -0.058131600, -0.153896500", \ - "0.0067057000, 0.0057989000, 0.0035060000, -0.002697700, -0.018731300, -0.058165100, -0.153889900", \ - "0.0071255000, 0.0059742000, 0.0035973000, -0.002437700, -0.018437300, -0.057834400, -0.153591100", \ - "0.0087875000, 0.0076226000, 0.0050028000, -0.001758100, -0.018085800, -0.057429800, -0.153139500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012105780, 0.0029309990, 0.0070964070, 0.0171815100, 0.0415991200, 0.1007180000"); - values("0.0065690000, 0.0078359000, 0.0107707000, 0.0175944000, 0.0340117000, 0.0726755000, 0.1671944000", \ - "0.0065336000, 0.0077942000, 0.0107165000, 0.0175260000, 0.0338041000, 0.0733311000, 0.1667709000", \ - "0.0063856000, 0.0076266000, 0.0105335000, 0.0173864000, 0.0338431000, 0.0732966000, 0.1677587000", \ - "0.0061678000, 0.0073825000, 0.0102688000, 0.0170660000, 0.0334470000, 0.0731036000, 0.1674316000", \ - "0.0060645000, 0.0071901000, 0.0100384000, 0.0168099000, 0.0331173000, 0.0724007000, 0.1672775000", \ - "0.0061786000, 0.0073582000, 0.0101861000, 0.0168971000, 0.0331821000, 0.0721017000, 0.1679733000", \ - "0.0068360000, 0.0079906000, 0.0108037000, 0.0174080000, 0.0337567000, 0.0731498000, 0.1677673000"); - } - } - max_capacitance : 0.1007180000; - max_transition : 1.5003870000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.1763624000, 0.1857819000, 0.2040678000, 0.2374749000, 0.3018691000, 0.4385980000, 0.7602293000", \ - "0.1794574000, 0.1888736000, 0.2071431000, 0.2405404000, 0.3049725000, 0.4417936000, 0.7638444000", \ - "0.1900600000, 0.1993968000, 0.2176404000, 0.2510717000, 0.3155275000, 0.4523510000, 0.7739515000", \ - "0.2159359000, 0.2251389000, 0.2434132000, 0.2769908000, 0.3414956000, 0.4783965000, 0.7999852000", \ - "0.2756515000, 0.2849200000, 0.3030534000, 0.3369009000, 0.4014337000, 0.5383634000, 0.8602285000", \ - "0.3875642000, 0.3981324000, 0.4184942000, 0.4555644000, 0.5234015000, 0.6620670000, 0.9839135000", \ - "0.5788878000, 0.5916742000, 0.6160840000, 0.6585785000, 0.7333266000, 0.8768503000, 1.2004733000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0615815000, 0.0696529000, 0.0880524000, 0.1311480000, 0.2339230000, 0.4835950000, 1.0862010000", \ - "0.0663801000, 0.0744264000, 0.0928343000, 0.1357416000, 0.2389741000, 0.4879553000, 1.0939740000", \ - "0.0776157000, 0.0856526000, 0.1040656000, 0.1471207000, 0.2504085000, 0.4995507000, 1.1037973000", \ - "0.0995399000, 0.1077896000, 0.1262558000, 0.1694715000, 0.2733658000, 0.5224394000, 1.1256217000", \ - "0.1292263000, 0.1376430000, 0.1561423000, 0.1994893000, 0.3032599000, 0.5529776000, 1.1563200000", \ - "0.1616967000, 0.1712183000, 0.1906433000, 0.2340459000, 0.3375079000, 0.5870903000, 1.1933926000", \ - "0.1765216000, 0.1890789000, 0.2128160000, 0.2574042000, 0.3595287000, 0.6099489000, 1.2134892000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0346363000, 0.0417261000, 0.0556031000, 0.0859088000, 0.1529244000, 0.3205994000, 0.7472264000", \ - "0.0346614000, 0.0418305000, 0.0558739000, 0.0857550000, 0.1526035000, 0.3204740000, 0.7457841000", \ - "0.0352202000, 0.0419976000, 0.0557336000, 0.0857598000, 0.1525293000, 0.3199694000, 0.7466817000", \ - "0.0350885000, 0.0413321000, 0.0558043000, 0.0856756000, 0.1528151000, 0.3198842000, 0.7442899000", \ - "0.0355498000, 0.0418594000, 0.0557434000, 0.0859137000, 0.1526099000, 0.3201930000, 0.7485137000", \ - "0.0427327000, 0.0496295000, 0.0646527000, 0.0937253000, 0.1583874000, 0.3228762000, 0.7439691000", \ - "0.0567764000, 0.0646563000, 0.0796595000, 0.1109452000, 0.1744735000, 0.3328701000, 0.7443479000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0256554000, 0.0357339000, 0.0606384000, 0.1216762000, 0.2695186000, 0.6282175000, 1.4936208000", \ - "0.0256225000, 0.0357492000, 0.0606193000, 0.1213465000, 0.2696376000, 0.6267064000, 1.4961646000", \ - "0.0255567000, 0.0357461000, 0.0605693000, 0.1214480000, 0.2691340000, 0.6279040000, 1.4961473000", \ - "0.0266223000, 0.0364679000, 0.0607769000, 0.1216072000, 0.2698867000, 0.6280256000, 1.4955546000", \ - "0.0293328000, 0.0384353000, 0.0623286000, 0.1221743000, 0.2695989000, 0.6278782000, 1.4960603000", \ - "0.0367535000, 0.0448171000, 0.0659851000, 0.1233663000, 0.2717556000, 0.6275499000, 1.4919836000", \ - "0.0510133000, 0.0591959000, 0.0784519000, 0.1292410000, 0.2716280000, 0.6305519000, 1.4912306000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.1583602000, 0.1677635000, 0.1860364000, 0.2194197000, 0.2840540000, 0.4210598000, 0.7426325000", \ - "0.1602263000, 0.1696779000, 0.1877152000, 0.2213307000, 0.2859633000, 0.4230050000, 0.7443836000", \ - "0.1696740000, 0.1789970000, 0.1971966000, 0.2309731000, 0.2951766000, 0.4319935000, 0.7543228000", \ - "0.1969222000, 0.2062553000, 0.2244328000, 0.2582043000, 0.3228565000, 0.4598782000, 0.7815092000", \ - "0.2631488000, 0.2724869000, 0.2906398000, 0.3243913000, 0.3889495000, 0.5256700000, 0.8476436000", \ - "0.3847185000, 0.3955099000, 0.4164090000, 0.4528648000, 0.5205964000, 0.6584093000, 0.9781017000", \ - "0.5747414000, 0.5889363000, 0.6145348000, 0.6579023000, 0.7305566000, 0.8718795000, 1.1973899000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0584886000, 0.0668205000, 0.0857139000, 0.1291611000, 0.2336054000, 0.4849012000, 1.0987015000", \ - "0.0634104000, 0.0716941000, 0.0906027000, 0.1341107000, 0.2376334000, 0.4873598000, 1.0908946000", \ - "0.0746966000, 0.0828120000, 0.1015500000, 0.1453097000, 0.2497358000, 0.5017293000, 1.1085413000", \ - "0.0953077000, 0.1035489000, 0.1223722000, 0.1660418000, 0.2698876000, 0.5226027000, 1.1227008000", \ - "0.1229487000, 0.1313810000, 0.1503067000, 0.1940595000, 0.2980931000, 0.5493236000, 1.1516578000", \ - "0.1532548000, 0.1629162000, 0.1828966000, 0.2262473000, 0.3298166000, 0.5798950000, 1.1860914000", \ - "0.1660692000, 0.1795416000, 0.2047842000, 0.2495038000, 0.3518298000, 0.6029490000, 1.2054945000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0346382000, 0.0417364000, 0.0556245000, 0.0859077000, 0.1525298000, 0.3198130000, 0.7458965000", \ - "0.0346914000, 0.0413645000, 0.0557343000, 0.0857075000, 0.1525404000, 0.3208855000, 0.7454358000", \ - "0.0347770000, 0.0412382000, 0.0558618000, 0.0849101000, 0.1524197000, 0.3200956000, 0.7465738000", \ - "0.0347406000, 0.0418232000, 0.0558761000, 0.0850208000, 0.1522955000, 0.3207647000, 0.7444065000", \ - "0.0354685000, 0.0419913000, 0.0558675000, 0.0859584000, 0.1529852000, 0.3194923000, 0.7436866000", \ - "0.0466818000, 0.0531776000, 0.0658282000, 0.0950568000, 0.1591891000, 0.3229934000, 0.7454049000", \ - "0.0649452000, 0.0731818000, 0.0882639000, 0.1141230000, 0.1759659000, 0.3326363000, 0.7460114000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012105800, 0.0029310000, 0.0070964100, 0.0171815000, 0.0415991000, 0.1007180000"); - values("0.0253568000, 0.0354765000, 0.0604046000, 0.1213113000, 0.2713348000, 0.6296791000, 1.4979368000", \ - "0.0253053000, 0.0354249000, 0.0604011000, 0.1213614000, 0.2697006000, 0.6288370000, 1.4925992000", \ - "0.0253961000, 0.0354268000, 0.0602482000, 0.1214230000, 0.2714136000, 0.6342415000, 1.5003868000", \ - "0.0267326000, 0.0363350000, 0.0607404000, 0.1214586000, 0.2698556000, 0.6334566000, 1.4966314000", \ - "0.0298575000, 0.0389949000, 0.0622416000, 0.1222580000, 0.2692617000, 0.6279130000, 1.4984380000", \ - "0.0384091000, 0.0468630000, 0.0670056000, 0.1237365000, 0.2710524000, 0.6261306000, 1.4979931000", \ - "0.0544421000, 0.0625981000, 0.0817651000, 0.1308056000, 0.2715929000, 0.6307330000, 1.4915926000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2_1") { - leakage_power () { - value : 0.0011453000; - when : "!A&B"; - } - leakage_power () { - value : 0.0052491000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0003472000; - when : "A&B"; - } - leakage_power () { - value : 0.0006548000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__or2"; - cell_leakage_power : 0.0018491090; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016991000, 0.0016952000, 0.0016861000, 0.0016868000, 0.0016884000, 0.0016922000, 0.0017008000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001548400, -0.001572900, -0.001629600, -0.001631700, -0.001636800, -0.001648400, -0.001675300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015430000; - } - pin ("B") { - capacitance : 0.0014600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011586000, 0.0011593000, 0.0011609000, 0.0011638000, 0.0011705000, 0.0011861000, 0.0012219000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000794900, -0.000792200, -0.000786100, -0.000786300, -0.000786700, -0.000787600, -0.000789600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015470000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0087511000, 0.0076230000, 0.0047725000, -0.003439600, -0.026861700, -0.089674700, -0.255092900", \ - "0.0085787000, 0.0074807000, 0.0046086000, -0.003591600, -0.027003100, -0.089815100, -0.255225900", \ - "0.0084325000, 0.0073182000, 0.0044629000, -0.003775900, -0.027164300, -0.089944600, -0.255396300", \ - "0.0082961000, 0.0071980000, 0.0043370000, -0.003933900, -0.027315900, -0.090093500, -0.255543200", \ - "0.0082388000, 0.0071105000, 0.0042080000, -0.004058200, -0.027415800, -0.090203200, -0.255548100", \ - "0.0082789000, 0.0069264000, 0.0039122000, -0.004189500, -0.027496700, -0.090211700, -0.255567800", \ - "0.0103488000, 0.0089717000, 0.0054611000, -0.003629400, -0.027458800, -0.090058000, -0.255343200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0097495000, 0.0111331000, 0.0146715000, 0.0237249000, 0.0473518000, 0.1094593000, 0.2742627000", \ - "0.0097120000, 0.0110959000, 0.0146340000, 0.0237185000, 0.0473332000, 0.1094263000, 0.2728284000", \ - "0.0096763000, 0.0110587000, 0.0145988000, 0.0237014000, 0.0474033000, 0.1095175000, 0.2727934000", \ - "0.0094906000, 0.0108586000, 0.0143968000, 0.0235164000, 0.0472962000, 0.1094352000, 0.2727347000", \ - "0.0095747000, 0.0108705000, 0.0142812000, 0.0233855000, 0.0471173000, 0.1099121000, 0.2740403000", \ - "0.0097207000, 0.0110245000, 0.0144245000, 0.0234227000, 0.0472605000, 0.1091033000, 0.2737186000", \ - "0.0104283000, 0.0117204000, 0.0151231000, 0.0240760000, 0.0479287000, 0.1105528000, 0.2737275000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0082543000, 0.0071377000, 0.0042442000, -0.004001300, -0.027349400, -0.090080500, -0.255472300", \ - "0.0080940000, 0.0069730000, 0.0040709000, -0.004177400, -0.027471000, -0.090246600, -0.255596300", \ - "0.0078569000, 0.0067459000, 0.0039290000, -0.004339000, -0.027656200, -0.090348700, -0.255735800", \ - "0.0078059000, 0.0066803000, 0.0037939000, -0.004482100, -0.027810500, -0.090487800, -0.255847000", \ - "0.0077357000, 0.0066013000, 0.0037043000, -0.004546900, -0.027863600, -0.090558100, -0.255879400", \ - "0.0079333000, 0.0065690000, 0.0036507000, -0.004354400, -0.027679300, -0.090323400, -0.255617600", \ - "0.0107688000, 0.0093067000, 0.0057126000, -0.003410300, -0.027077000, -0.089782100, -0.255106500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013141250, 0.0034538490, 0.0090775780, 0.0238581500, 0.0627051700, 0.1648049000"); - values("0.0084894000, 0.0099410000, 0.0136339000, 0.0229110000, 0.0467625000, 0.1090635000, 0.2728356000", \ - "0.0084722000, 0.0099175000, 0.0135897000, 0.0228785000, 0.0466963000, 0.1096809000, 0.2728079000", \ - "0.0083556000, 0.0097748000, 0.0134220000, 0.0226983000, 0.0466430000, 0.1090811000, 0.2709730000", \ - "0.0081589000, 0.0095426000, 0.0131352000, 0.0223344000, 0.0465668000, 0.1087034000, 0.2732563000", \ - "0.0080789000, 0.0093996000, 0.0128878000, 0.0220465000, 0.0458684000, 0.1084540000, 0.2723880000", \ - "0.0083005000, 0.0096276000, 0.0131391000, 0.0220997000, 0.0460528000, 0.1081643000, 0.2734369000", \ - "0.0089787000, 0.0102675000, 0.0136960000, 0.0225976000, 0.0465763000, 0.1090968000, 0.2708041000"); - } - } - max_capacitance : 0.1648050000; - max_transition : 1.5039330000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.1885570000, 0.1967329000, 0.2137609000, 0.2465727000, 0.3096559000, 0.4472908000, 0.7900760000", \ - "0.1921658000, 0.2003849000, 0.2173940000, 0.2502158000, 0.3133291000, 0.4509860000, 0.7937117000", \ - "0.2029708000, 0.2111444000, 0.2281230000, 0.2605031000, 0.3241256000, 0.4616270000, 0.8043309000", \ - "0.2288256000, 0.2369827000, 0.2537751000, 0.2864597000, 0.3498697000, 0.4875034000, 0.8303160000", \ - "0.2891534000, 0.2972978000, 0.3141017000, 0.3466933000, 0.4101576000, 0.5478143000, 0.8909676000", \ - "0.4071170000, 0.4161204000, 0.4348515000, 0.4704004000, 0.5367395000, 0.6759890000, 1.0189599000", \ - "0.6096464000, 0.6206511000, 0.6430316000, 0.6841642000, 0.7580209000, 0.9036409000, 1.2482991000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0606584000, 0.0667303000, 0.0812065000, 0.1170958000, 0.2100643000, 0.4544231000, 1.0969585000", \ - "0.0654413000, 0.0714631000, 0.0859651000, 0.1219462000, 0.2154799000, 0.4592306000, 1.1014806000", \ - "0.0768204000, 0.0828264000, 0.0972657000, 0.1333217000, 0.2266203000, 0.4710119000, 1.1130344000", \ - "0.1000667000, 0.1061938000, 0.1209573000, 0.1571134000, 0.2505297000, 0.4949939000, 1.1370527000", \ - "0.1324917000, 0.1391732000, 0.1542614000, 0.1905411000, 0.2840900000, 0.5291869000, 1.1725140000", \ - "0.1694259000, 0.1774252000, 0.1942096000, 0.2313391000, 0.3249934000, 0.5693116000, 1.2141267000", \ - "0.1898187000, 0.2009422000, 0.2229211000, 0.2639137000, 0.3565406000, 0.6012132000, 1.2422180000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0351217000, 0.0404132000, 0.0529538000, 0.0782329000, 0.1401990000, 0.3012652000, 0.7500821000", \ - "0.0354998000, 0.0404281000, 0.0523141000, 0.0782535000, 0.1402663000, 0.3012846000, 0.7503353000", \ - "0.0354863000, 0.0404110000, 0.0529536000, 0.0795540000, 0.1396810000, 0.3014571000, 0.7518903000", \ - "0.0351675000, 0.0404645000, 0.0531877000, 0.0783740000, 0.1400409000, 0.3012023000, 0.7526389000", \ - "0.0352480000, 0.0407390000, 0.0531678000, 0.0792204000, 0.1394218000, 0.3017965000, 0.7518703000", \ - "0.0419130000, 0.0476728000, 0.0606796000, 0.0858393000, 0.1450942000, 0.3037537000, 0.7481787000", \ - "0.0564095000, 0.0631310000, 0.0767656000, 0.1032268000, 0.1624601000, 0.3150285000, 0.7526586000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0213339000, 0.0282554000, 0.0467501000, 0.0967826000, 0.2293902000, 0.5791351000, 1.4999162000", \ - "0.0212972000, 0.0282223000, 0.0467208000, 0.0966066000, 0.2296813000, 0.5797262000, 1.5007542000", \ - "0.0212675000, 0.0282461000, 0.0466596000, 0.0967731000, 0.2300418000, 0.5799531000, 1.4990396000", \ - "0.0225471000, 0.0291843000, 0.0472445000, 0.0967275000, 0.2301149000, 0.5798923000, 1.4986704000", \ - "0.0262805000, 0.0325062000, 0.0495763000, 0.0978610000, 0.2292355000, 0.5802497000, 1.5010759000", \ - "0.0350784000, 0.0405296000, 0.0560402000, 0.1004522000, 0.2306328000, 0.5786286000, 1.4962728000", \ - "0.0498152000, 0.0562453000, 0.0709956000, 0.1105112000, 0.2325119000, 0.5810062000, 1.4965984000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.1725024000, 0.1807214000, 0.1975789000, 0.2300190000, 0.2936742000, 0.4313658000, 0.7740153000", \ - "0.1747615000, 0.1829425000, 0.1999538000, 0.2327836000, 0.2960770000, 0.4337454000, 0.7767676000", \ - "0.1838135000, 0.1919695000, 0.2089424000, 0.2422760000, 0.3055629000, 0.4432229000, 0.7861940000", \ - "0.2113854000, 0.2195204000, 0.2364669000, 0.2690458000, 0.3325147000, 0.4702345000, 0.8134619000", \ - "0.2781289000, 0.2862367000, 0.3030397000, 0.3354551000, 0.3987513000, 0.5362347000, 0.8795527000", \ - "0.4083667000, 0.4177356000, 0.4367285000, 0.4726634000, 0.5391275000, 0.6767729000, 1.0169230000", \ - "0.6129210000, 0.6246679000, 0.6486406000, 0.6917883000, 0.7654746000, 0.9085681000, 1.2559803000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0579326000, 0.0641358000, 0.0791173000, 0.1158307000, 0.2095437000, 0.4545883000, 1.0981663000", \ - "0.0629153000, 0.0690744000, 0.0840046000, 0.1207190000, 0.2150091000, 0.4594520000, 1.1033883000", \ - "0.0744533000, 0.0805720000, 0.0953855000, 0.1320298000, 0.2266665000, 0.4723351000, 1.1133799000", \ - "0.0968581000, 0.1030780000, 0.1179816000, 0.1543662000, 0.2483415000, 0.4933628000, 1.1421231000", \ - "0.1275228000, 0.1342806000, 0.1497385000, 0.1863415000, 0.2804573000, 0.5262141000, 1.1706767000", \ - "0.1621938000, 0.1709321000, 0.1883525000, 0.2254935000, 0.3196099000, 0.5643052000, 1.2108743000", \ - "0.1816310000, 0.1935191000, 0.2165675000, 0.2582122000, 0.3517417000, 0.5972294000, 1.2386342000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0352641000, 0.0404086000, 0.0530873000, 0.0795520000, 0.1398433000, 0.3010925000, 0.7545841000", \ - "0.0355082000, 0.0406922000, 0.0529699000, 0.0784318000, 0.1397742000, 0.3010736000, 0.7526101000", \ - "0.0355388000, 0.0404538000, 0.0529685000, 0.0784231000, 0.1397830000, 0.3014254000, 0.7513842000", \ - "0.0350959000, 0.0404328000, 0.0522715000, 0.0784445000, 0.1396808000, 0.3008172000, 0.7521206000", \ - "0.0354430000, 0.0408218000, 0.0525358000, 0.0793372000, 0.1400921000, 0.3012807000, 0.7522023000", \ - "0.0457443000, 0.0513731000, 0.0632048000, 0.0873317000, 0.1458170000, 0.3042554000, 0.7512725000", \ - "0.0647621000, 0.0713586000, 0.0848408000, 0.1100384000, 0.1649603000, 0.3164804000, 0.7508084000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013141300, 0.0034538500, 0.0090775800, 0.0238581000, 0.0627052000, 0.1648050000"); - values("0.0210840000, 0.0278960000, 0.0464757000, 0.0964302000, 0.2300640000, 0.5814682000, 1.5017231000", \ - "0.0210332000, 0.0278695000, 0.0464918000, 0.0966799000, 0.2302872000, 0.5823967000, 1.5039329000", \ - "0.0210797000, 0.0279787000, 0.0464735000, 0.0965308000, 0.2311779000, 0.5831457000, 1.4957454000", \ - "0.0226052000, 0.0291019000, 0.0471080000, 0.0966836000, 0.2308331000, 0.5788414000, 1.5038325000", \ - "0.0269438000, 0.0329636000, 0.0497414000, 0.0978488000, 0.2291676000, 0.5811118000, 1.5037793000", \ - "0.0363459000, 0.0422262000, 0.0569303000, 0.1009877000, 0.2307311000, 0.5785094000, 1.5020215000", \ - "0.0525442000, 0.0593926000, 0.0741040000, 0.1126650000, 0.2328960000, 0.5806195000, 1.4941048000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2_2") { - leakage_power () { - value : 0.0015006000; - when : "!A&B"; - } - leakage_power () { - value : 0.0063313000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0007598000; - when : "A&B"; - } - leakage_power () { - value : 0.0010264000; - when : "A&!B"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__or2"; - cell_leakage_power : 0.0024045480; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016826000, 0.0016804000, 0.0016754000, 0.0016757000, 0.0016764000, 0.0016781000, 0.0016821000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001530000, -0.001556600, -0.001618000, -0.001620200, -0.001625200, -0.001636600, -0.001662900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015700000; - } - pin ("B") { - capacitance : 0.0014080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011417000, 0.0011424000, 0.0011438000, 0.0011466000, 0.0011531000, 0.0011680000, 0.0012024000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000797900, -0.000791200, -0.000775900, -0.000775500, -0.000774500, -0.000772300, -0.000767200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014960000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0120788000, 0.0103773000, 0.0062161000, -0.005360400, -0.041075200, -0.149829400, -0.467676200", \ - "0.0118848000, 0.0102591000, 0.0062133000, -0.005342100, -0.041272300, -0.149991700, -0.467727000", \ - "0.0118117000, 0.0101892000, 0.0061587000, -0.005629600, -0.041449500, -0.150149800, -0.467978200", \ - "0.0116374000, 0.0099893000, 0.0059842000, -0.005772700, -0.041628900, -0.150290600, -0.468028100", \ - "0.0114753000, 0.0098043000, 0.0056357000, -0.005953200, -0.041846100, -0.150463900, -0.468174300", \ - "0.0116266000, 0.0099520000, 0.0057741000, -0.005905500, -0.041950700, -0.150563900, -0.468271700", \ - "0.0159047000, 0.0140259000, 0.0091060000, -0.003893500, -0.041768500, -0.150355800, -0.468143000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0145051000, 0.0161690000, 0.0208995000, 0.0340815000, 0.0716001000, 0.1796496000, 0.4941026000", \ - "0.0144760000, 0.0161595000, 0.0208736000, 0.0340529000, 0.0716115000, 0.1796022000, 0.4941779000", \ - "0.0144614000, 0.0161238000, 0.0208301000, 0.0340291000, 0.0715785000, 0.1806068000, 0.4951681000", \ - "0.0144797000, 0.0160918000, 0.0206743000, 0.0338051000, 0.0714524000, 0.1795565000, 0.4941449000", \ - "0.0143820000, 0.0159512000, 0.0205829000, 0.0334171000, 0.0710998000, 0.1798286000, 0.4959128000", \ - "0.0148311000, 0.0163490000, 0.0208399000, 0.0337780000, 0.0710993000, 0.1788636000, 0.4935389000", \ - "0.0157354000, 0.0171985000, 0.0214592000, 0.0343727000, 0.0717702000, 0.1805627000, 0.4943540000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0114575000, 0.0097599000, 0.0057411000, -0.005797700, -0.041753700, -0.150328000, -0.468115900", \ - "0.0113466000, 0.0096656000, 0.0054710000, -0.006062100, -0.041894500, -0.150435300, -0.468207500", \ - "0.0111257000, 0.0094846000, 0.0054586000, -0.006202100, -0.042034800, -0.150579500, -0.468289500", \ - "0.0109904000, 0.0093233000, 0.0051907000, -0.006389900, -0.042256800, -0.150762700, -0.468557600", \ - "0.0109085000, 0.0093373000, 0.0051023000, -0.006504100, -0.042383700, -0.150941800, -0.468622600", \ - "0.0114038000, 0.0096909000, 0.0053268000, -0.006467100, -0.042466000, -0.151021100, -0.468587400", \ - "0.0170604000, 0.0144686000, 0.0093600000, -0.004147400, -0.042170600, -0.150007500, -0.467908100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014516010, 0.0042142900, 0.0122349400, 0.0355204900, 0.1031232000, 0.2993873000"); - values("0.0132471000, 0.0149386000, 0.0197743000, 0.0332091000, 0.0710418000, 0.1798216000, 0.4948538000", \ - "0.0132581000, 0.0149562000, 0.0197662000, 0.0331984000, 0.0710498000, 0.1798788000, 0.4948705000", \ - "0.0131853000, 0.0148773000, 0.0196289000, 0.0330599000, 0.0709137000, 0.1805543000, 0.4944103000", \ - "0.0131051000, 0.0147492000, 0.0194289000, 0.0326314000, 0.0705013000, 0.1796326000, 0.4948835000", \ - "0.0130644000, 0.0146312000, 0.0193311000, 0.0323646000, 0.0699752000, 0.1792295000, 0.4941528000", \ - "0.0135612000, 0.0150794000, 0.0195930000, 0.0324268000, 0.0700201000, 0.1776363000, 0.4956969000", \ - "0.0143901000, 0.0158542000, 0.0201484000, 0.0330783000, 0.0704286000, 0.1789704000, 0.4908659000"); - } - } - max_capacitance : 0.2993870000; - max_transition : 1.5089130000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2581992000, 0.2659441000, 0.2835384000, 0.3184426000, 0.3841776000, 0.5173852000, 0.8457473000", \ - "0.2621977000, 0.2700823000, 0.2877033000, 0.3224540000, 0.3876399000, 0.5215279000, 0.8500431000", \ - "0.2730849000, 0.2808617000, 0.2983238000, 0.3332686000, 0.3983937000, 0.5322251000, 0.8608260000", \ - "0.2984449000, 0.3062414000, 0.3238166000, 0.3586846000, 0.4240831000, 0.5575783000, 0.8860860000", \ - "0.3588159000, 0.3665519000, 0.3840491000, 0.4188813000, 0.4845536000, 0.6184215000, 0.9468692000", \ - "0.4933755000, 0.5013927000, 0.5191418000, 0.5549174000, 0.6211490000, 0.7553806000, 1.0843358000", \ - "0.7347123000, 0.7438896000, 0.7650136000, 0.8065323000, 0.8812446000, 1.0240232000, 1.3567509000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0713188000, 0.0763226000, 0.0885808000, 0.1185377000, 0.1998799000, 0.4325123000, 1.1095543000", \ - "0.0760580000, 0.0810677000, 0.0933266000, 0.1233507000, 0.2044914000, 0.4375657000, 1.1143780000", \ - "0.0874170000, 0.0924229000, 0.1046674000, 0.1346068000, 0.2161377000, 0.4500103000, 1.1243295000", \ - "0.1134161000, 0.1184156000, 0.1305631000, 0.1604561000, 0.2414606000, 0.4747392000, 1.1515161000", \ - "0.1544722000, 0.1603245000, 0.1735274000, 0.2041899000, 0.2855243000, 0.5191144000, 1.1972010000", \ - "0.2032259000, 0.2108271000, 0.2273748000, 0.2606658000, 0.3421095000, 0.5754826000, 1.2548600000", \ - "0.2430948000, 0.2533028000, 0.2752512000, 0.3167021000, 0.4005364000, 0.6339825000, 1.3088391000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0446078000, 0.0490963000, 0.0601314000, 0.0827737000, 0.1358420000, 0.2717052000, 0.6865765000", \ - "0.0443285000, 0.0489429000, 0.0605116000, 0.0837685000, 0.1357620000, 0.2714152000, 0.6862692000", \ - "0.0446053000, 0.0493997000, 0.0606075000, 0.0836438000, 0.1357088000, 0.2715762000, 0.6863433000", \ - "0.0446618000, 0.0491042000, 0.0604816000, 0.0828428000, 0.1346898000, 0.2713684000, 0.6859978000", \ - "0.0445019000, 0.0490085000, 0.0605136000, 0.0829688000, 0.1346150000, 0.2713987000, 0.6863458000", \ - "0.0488782000, 0.0534650000, 0.0641215000, 0.0871296000, 0.1371023000, 0.2725560000, 0.6865020000", \ - "0.0634284000, 0.0684718000, 0.0799390000, 0.1043605000, 0.1576632000, 0.2880998000, 0.6900388000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0188354000, 0.0235194000, 0.0363736000, 0.0742650000, 0.1891619000, 0.5246275000, 1.5021597000", \ - "0.0188950000, 0.0234545000, 0.0363326000, 0.0744267000, 0.1889338000, 0.5250380000, 1.5019634000", \ - "0.0188601000, 0.0234467000, 0.0363189000, 0.0744126000, 0.1890562000, 0.5261092000, 1.4990925000", \ - "0.0194112000, 0.0239216000, 0.0367769000, 0.0744993000, 0.1890201000, 0.5250791000, 1.5021121000", \ - "0.0246295000, 0.0287204000, 0.0406244000, 0.0768390000, 0.1890700000, 0.5251749000, 1.5031717000", \ - "0.0348240000, 0.0393226000, 0.0505096000, 0.0829433000, 0.1914297000, 0.5249869000, 1.5001828000", \ - "0.0493748000, 0.0558342000, 0.0691154000, 0.0997122000, 0.1970465000, 0.5267373000, 1.4966807000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.2403647000, 0.2480923000, 0.2655791000, 0.3003448000, 0.3655690000, 0.4992520000, 0.8280673000", \ - "0.2432186000, 0.2510279000, 0.2685542000, 0.3035476000, 0.3685962000, 0.5023267000, 0.8311296000", \ - "0.2524741000, 0.2603462000, 0.2780121000, 0.3127829000, 0.3781849000, 0.5116830000, 0.8405988000", \ - "0.2789861000, 0.2868830000, 0.3044273000, 0.3392457000, 0.4047797000, 0.5381772000, 0.8672019000", \ - "0.3450072000, 0.3528791000, 0.3703521000, 0.4051864000, 0.4708685000, 0.6046736000, 0.9334157000", \ - "0.4964581000, 0.5042758000, 0.5225630000, 0.5580861000, 0.6244912000, 0.7584692000, 1.0865192000", \ - "0.7503539000, 0.7594830000, 0.7820207000, 0.8262838000, 0.9035263000, 1.0446284000, 1.3757681000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0686885000, 0.0737568000, 0.0862033000, 0.1166465000, 0.1983737000, 0.4324949000, 1.1116973000", \ - "0.0736673000, 0.0787299000, 0.0911726000, 0.1216114000, 0.2032572000, 0.4376247000, 1.1161827000", \ - "0.0852846000, 0.0903478000, 0.1027225000, 0.1330805000, 0.2152232000, 0.4499492000, 1.1240961000", \ - "0.1112313000, 0.1163075000, 0.1286525000, 0.1587762000, 0.2406471000, 0.4756405000, 1.1563170000", \ - "0.1513301000, 0.1571537000, 0.1707281000, 0.2018320000, 0.2833531000, 0.5169410000, 1.1928617000", \ - "0.2000938000, 0.2078907000, 0.2249485000, 0.2584896000, 0.3403794000, 0.5738467000, 1.2544695000", \ - "0.2434090000, 0.2540873000, 0.2768175000, 0.3189637000, 0.4045482000, 0.6371429000, 1.3111180000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0447000000, 0.0489925000, 0.0604030000, 0.0836413000, 0.1361532000, 0.2715854000, 0.6862977000", \ - "0.0445846000, 0.0491364000, 0.0601028000, 0.0837654000, 0.1358941000, 0.2717921000, 0.6862448000", \ - "0.0446348000, 0.0489769000, 0.0598011000, 0.0838772000, 0.1355212000, 0.2720769000, 0.6850505000", \ - "0.0443286000, 0.0491080000, 0.0597124000, 0.0838652000, 0.1354851000, 0.2713446000, 0.6862766000", \ - "0.0443910000, 0.0494451000, 0.0597732000, 0.0838040000, 0.1359325000, 0.2708228000, 0.6864510000", \ - "0.0504558000, 0.0549936000, 0.0654204000, 0.0868267000, 0.1375533000, 0.2725012000, 0.6866572000", \ - "0.0743741000, 0.0795182000, 0.0919842000, 0.1158007000, 0.1620210000, 0.2913545000, 0.6922985000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014516000, 0.0042142900, 0.0122349000, 0.0355205000, 0.1031230000, 0.2993870000"); - values("0.0188664000, 0.0233968000, 0.0362221000, 0.0742630000, 0.1885699000, 0.5266310000, 1.5067183000", \ - "0.0188809000, 0.0234253000, 0.0362303000, 0.0742108000, 0.1886909000, 0.5268023000, 1.5070964000", \ - "0.0186979000, 0.0234071000, 0.0363190000, 0.0742256000, 0.1887504000, 0.5277248000, 1.5049226000", \ - "0.0195899000, 0.0240420000, 0.0367521000, 0.0744673000, 0.1890473000, 0.5269217000, 1.5089129000", \ - "0.0252639000, 0.0294440000, 0.0411745000, 0.0768718000, 0.1891882000, 0.5261664000, 1.5046032000", \ - "0.0355028000, 0.0404628000, 0.0514606000, 0.0837211000, 0.1912700000, 0.5248713000, 1.5059021000", \ - "0.0512317000, 0.0578231000, 0.0714642000, 0.1031087000, 0.1981585000, 0.5264952000, 1.4980674000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2_4") { - leakage_power () { - value : 0.0039006000; - when : "!A&B"; - } - leakage_power () { - value : 0.0051014000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0019054000; - when : "A&B"; - } - leakage_power () { - value : 0.0024409000; - when : "A&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__or2"; - cell_leakage_power : 0.0033370700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024100000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038017000, 0.0037975000, 0.0037879000, 0.0037856000, 0.0037805000, 0.0037685000, 0.0037411000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003393700, -0.003474400, -0.003660400, -0.003663000, -0.003669000, -0.003682800, -0.003714600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025450000; - } - pin ("B") { - capacitance : 0.0023670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025058000, 0.0025020000, 0.0024934000, 0.0025005000, 0.0025169000, 0.0025548000, 0.0026421000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001705600, -0.001714800, -0.001735800, -0.001737300, -0.001740800, -0.001748800, -0.001767400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025440000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015887090, 0.0050479920, 0.0160395800, 0.0509644400, 0.1619353000, 0.5145362000"); - values("0.0232723000, 0.0214184000, 0.0162580000, 0.0003805000, -0.052333100, -0.229904000, -0.800944800", \ - "0.0230936000, 0.0212606000, 0.0157738000, 0.0002076000, -0.052466300, -0.230045500, -0.801080000", \ - "0.0228989000, 0.0210645000, 0.0157223000, 0.0002486000, -0.052504200, -0.230369400, -0.801237100", \ - "0.0226394000, 0.0209322000, 0.0153566000, -0.000267100, -0.052968100, -0.230539700, -0.801379000", \ - "0.0224637000, 0.0206198000, 0.0151345000, -0.000536500, -0.053238000, -0.230811600, -0.801492300", \ - "0.0227526000, 0.0210745000, 0.0154117000, -0.000551000, -0.053486100, -0.231058100, -0.801681200", \ - "0.0303365000, 0.0282261000, 0.0221180000, 0.0037531000, -0.051704500, -0.230395000, -0.801104500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015887090, 0.0050479920, 0.0160395800, 0.0509644400, 0.1619353000, 0.5145362000"); - values("0.0286235000, 0.0305126000, 0.0363910000, 0.0545969000, 0.1112136000, 0.2889002000, 0.8544917000", \ - "0.0285417000, 0.0304530000, 0.0363906000, 0.0546310000, 0.1111845000, 0.2894908000, 0.8539360000", \ - "0.0284986000, 0.0304123000, 0.0363358000, 0.0546450000, 0.1112311000, 0.2894023000, 0.8537122000", \ - "0.0284570000, 0.0302706000, 0.0361273000, 0.0543756000, 0.1109699000, 0.2891574000, 0.8533447000", \ - "0.0284386000, 0.0302695000, 0.0359359000, 0.0538503000, 0.1104723000, 0.2890010000, 0.8528260000", \ - "0.0291942000, 0.0308635000, 0.0364804000, 0.0543278000, 0.1101187000, 0.2878113000, 0.8524655000", \ - "0.0309683000, 0.0326149000, 0.0381295000, 0.0555754000, 0.1117895000, 0.2895769000, 0.8524368000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015887090, 0.0050479920, 0.0160395800, 0.0509644400, 0.1619353000, 0.5145362000"); - values("0.0221650000, 0.0203423000, 0.0148669000, -0.000693100, -0.053153000, -0.230833200, -0.801648600", \ - "0.0220521000, 0.0202065000, 0.0150642000, -0.000604100, -0.053263000, -0.231078000, -0.801725500", \ - "0.0219977000, 0.0201246000, 0.0146369000, -0.001035500, -0.053663400, -0.231161600, -0.802038400", \ - "0.0216519000, 0.0198016000, 0.0143119000, -0.001174700, -0.053884000, -0.231488500, -0.802248100", \ - "0.0216355000, 0.0197584000, 0.0142501000, -0.001457200, -0.053992700, -0.231630500, -0.802121300", \ - "0.0223833000, 0.0204426000, 0.0147362000, -0.001384100, -0.053886300, -0.231392700, -0.801809900", \ - "0.0324177000, 0.0302202000, 0.0241752000, 0.0056002000, -0.052254300, -0.230513900, -0.800898400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015887090, 0.0050479920, 0.0160395800, 0.0509644400, 0.1619353000, 0.5145362000"); - values("0.0255991000, 0.0274595000, 0.0334881000, 0.0522884000, 0.1097284000, 0.2871626000, 0.8500438000", \ - "0.0256228000, 0.0275842000, 0.0335285000, 0.0523005000, 0.1097024000, 0.2887230000, 0.8551200000", \ - "0.0254512000, 0.0274014000, 0.0334704000, 0.0521393000, 0.1095297000, 0.2885820000, 0.8503954000", \ - "0.0252886000, 0.0271336000, 0.0331422000, 0.0515506000, 0.1088528000, 0.2865570000, 0.8506712000", \ - "0.0253141000, 0.0271758000, 0.0330240000, 0.0511925000, 0.1077119000, 0.2862281000, 0.8491875000", \ - "0.0262430000, 0.0280133000, 0.0337712000, 0.0515624000, 0.1072580000, 0.2858998000, 0.8528188000", \ - "0.0278329000, 0.0295232000, 0.0350044000, 0.0524900000, 0.1091695000, 0.2869061000, 0.8501583000"); - } - } - max_capacitance : 0.5145360000; - max_transition : 1.5082430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.2137088000, 0.2183824000, 0.2302343000, 0.2566178000, 0.3098437000, 0.4239624000, 0.7291177000", \ - "0.2187554000, 0.2234216000, 0.2352952000, 0.2616577000, 0.3148669000, 0.4290656000, 0.7342330000", \ - "0.2309985000, 0.2356463000, 0.2474871000, 0.2738701000, 0.3268787000, 0.4414097000, 0.7460039000", \ - "0.2581295000, 0.2627427000, 0.2745648000, 0.3008716000, 0.3541238000, 0.4684144000, 0.7734041000", \ - "0.3211711000, 0.3258127000, 0.3376285000, 0.3638801000, 0.4172704000, 0.5319142000, 0.8371943000", \ - "0.4551697000, 0.4605309000, 0.4731016000, 0.5009789000, 0.5561339000, 0.6720682000, 0.9769994000", \ - "0.6913723000, 0.6969356000, 0.7119864000, 0.7445384000, 0.8077465000, 0.9333941000, 1.2433057000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0807491000, 0.0842950000, 0.0939403000, 0.1194046000, 0.1919323000, 0.4165965000, 1.1299173000", \ - "0.0853266000, 0.0888770000, 0.0985615000, 0.1240040000, 0.1964740000, 0.4213961000, 1.1349703000", \ - "0.0961611000, 0.0997108000, 0.1093915000, 0.1348787000, 0.2074188000, 0.4330450000, 1.1449347000", \ - "0.1220859000, 0.1255382000, 0.1351539000, 0.1604682000, 0.2330520000, 0.4588213000, 1.1705484000", \ - "0.1655284000, 0.1695724000, 0.1797901000, 0.2061790000, 0.2787501000, 0.5037983000, 1.2161099000", \ - "0.2169357000, 0.2217929000, 0.2351352000, 0.2643510000, 0.3377413000, 0.5629877000, 1.2765985000", \ - "0.2575608000, 0.2645745000, 0.2821473000, 0.3190986000, 0.3965888000, 0.6204084000, 1.3318943000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0383121000, 0.0406893000, 0.0481218000, 0.0652495000, 0.1061489000, 0.2230022000, 0.6095994000", \ - "0.0383303000, 0.0407013000, 0.0476939000, 0.0652069000, 0.1060085000, 0.2230218000, 0.6096217000", \ - "0.0383184000, 0.0406621000, 0.0477649000, 0.0645976000, 0.1056722000, 0.2222116000, 0.6105005000", \ - "0.0381354000, 0.0410542000, 0.0481913000, 0.0652971000, 0.1059275000, 0.2224328000, 0.6104021000", \ - "0.0383090000, 0.0406336000, 0.0481101000, 0.0645462000, 0.1059201000, 0.2223047000, 0.6105104000", \ - "0.0441205000, 0.0463884000, 0.0541662000, 0.0701226000, 0.1100020000, 0.2239820000, 0.6115812000", \ - "0.0597725000, 0.0625045000, 0.0702132000, 0.0884335000, 0.1302642000, 0.2414170000, 0.6149622000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0205169000, 0.0236607000, 0.0331820000, 0.0631427000, 0.1625263000, 0.4828211000, 1.5039689000", \ - "0.0204463000, 0.0235243000, 0.0331120000, 0.0631037000, 0.1621676000, 0.4837327000, 1.5046411000", \ - "0.0205054000, 0.0235554000, 0.0331820000, 0.0631510000, 0.1620977000, 0.4840823000, 1.5018004000", \ - "0.0206719000, 0.0238621000, 0.0333611000, 0.0631143000, 0.1625672000, 0.4839442000, 1.5014426000", \ - "0.0255581000, 0.0284943000, 0.0377331000, 0.0658835000, 0.1628919000, 0.4828858000, 1.4991135000", \ - "0.0356656000, 0.0390992000, 0.0472201000, 0.0730005000, 0.1655779000, 0.4825906000, 1.4997319000", \ - "0.0514482000, 0.0554553000, 0.0660413000, 0.0909883000, 0.1732682000, 0.4863337000, 1.4997638000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.1976790000, 0.2022558000, 0.2141532000, 0.2405277000, 0.2936560000, 0.4081665000, 0.7131666000", \ - "0.2011334000, 0.2058005000, 0.2176500000, 0.2440178000, 0.2970023000, 0.4117454000, 0.7164324000", \ - "0.2109617000, 0.2155853000, 0.2274386000, 0.2537543000, 0.3071902000, 0.4214349000, 0.7265234000", \ - "0.2377717000, 0.2424574000, 0.2543642000, 0.2805555000, 0.3333799000, 0.4480584000, 0.7529937000", \ - "0.3040399000, 0.3086079000, 0.3203694000, 0.3466420000, 0.3993192000, 0.5143097000, 0.8194251000", \ - "0.4448855000, 0.4499710000, 0.4630451000, 0.4913479000, 0.5472223000, 0.6634500000, 0.9690264000", \ - "0.6713215000, 0.6775635000, 0.6937186000, 0.7296629000, 0.7964133000, 0.9211518000, 1.2306777000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0766843000, 0.0801989000, 0.0899554000, 0.1158205000, 0.1890230000, 0.4144321000, 1.1272705000", \ - "0.0815329000, 0.0851001000, 0.0947761000, 0.1206416000, 0.1939330000, 0.4198064000, 1.1349165000", \ - "0.0926256000, 0.0961906000, 0.1059665000, 0.1317210000, 0.2047044000, 0.4308927000, 1.1442847000", \ - "0.1185782000, 0.1221283000, 0.1318177000, 0.1573357000, 0.2301930000, 0.4560837000, 1.1812580000", \ - "0.1610377000, 0.1650624000, 0.1757984000, 0.2021894000, 0.2748573000, 0.5002060000, 1.2139014000", \ - "0.2117351000, 0.2171271000, 0.2307981000, 0.2602074000, 0.3340081000, 0.5587384000, 1.2748960000", \ - "0.2556143000, 0.2628765000, 0.2811337000, 0.3187899000, 0.3978068000, 0.6220622000, 1.3330393000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0382047000, 0.0408590000, 0.0479365000, 0.0652887000, 0.1050214000, 0.2226141000, 0.6099038000", \ - "0.0383267000, 0.0406863000, 0.0481449000, 0.0653628000, 0.1058043000, 0.2230118000, 0.6105391000", \ - "0.0382338000, 0.0409847000, 0.0480260000, 0.0644885000, 0.1057845000, 0.2229854000, 0.6095013000", \ - "0.0383132000, 0.0406645000, 0.0477107000, 0.0645892000, 0.1068408000, 0.2227683000, 0.6100032000", \ - "0.0382028000, 0.0410356000, 0.0482171000, 0.0651870000, 0.1066169000, 0.2226540000, 0.6101659000", \ - "0.0477268000, 0.0505309000, 0.0576597000, 0.0734782000, 0.1115982000, 0.2247476000, 0.6100723000", \ - "0.0709782000, 0.0738544000, 0.0819397000, 0.1005786000, 0.1384347000, 0.2446590000, 0.6169061000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015887100, 0.0050479900, 0.0160396000, 0.0509644000, 0.1619350000, 0.5145360000"); - values("0.0202628000, 0.0233756000, 0.0328938000, 0.0627924000, 0.1618441000, 0.4825502000, 1.5002392000", \ - "0.0202157000, 0.0232617000, 0.0328277000, 0.0627250000, 0.1617813000, 0.4840375000, 1.5082426000", \ - "0.0203363000, 0.0233693000, 0.0328515000, 0.0628739000, 0.1621113000, 0.4858338000, 1.5028366000", \ - "0.0208050000, 0.0239239000, 0.0332998000, 0.0630843000, 0.1621112000, 0.4825753000, 1.5028541000", \ - "0.0262351000, 0.0293671000, 0.0378597000, 0.0657330000, 0.1623505000, 0.4834794000, 1.5009581000", \ - "0.0368830000, 0.0401949000, 0.0491770000, 0.0745705000, 0.1656782000, 0.4823836000, 1.5040700000", \ - "0.0538846000, 0.0577029000, 0.0684114000, 0.0939876000, 0.1748017000, 0.4845890000, 1.4987890000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2b_1") { - leakage_power () { - value : 0.0091109000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0015600000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0028829000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0007476000; - when : "A&!B_N"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__or2b"; - cell_leakage_power : 0.0035753310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0017300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030993000, 0.0030804000, 0.0030368000, 0.0030355000, 0.0030325000, 0.0030255000, 0.0030093000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002890800, -0.002920100, -0.002987500, -0.002988500, -0.002990900, -0.002996300, -0.003008700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017970000; - } - pin ("B_N") { - capacitance : 0.0014180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013680000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072271000, 0.0071449000, 0.0069554000, 0.0070284000, 0.0071967000, 0.0075847000, 0.0084790000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0005819000, 0.0005073000, 0.0003351000, 0.0004035000, 0.0005610000, 0.0009241000, 0.0017610000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014690000; - } - pin ("X") { - direction : "output"; - function : "(A) | (!B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0076173000, 0.0065647000, 0.0036784000, -0.004731400, -0.028641300, -0.093126900, -0.263502800", \ - "0.0075463000, 0.0064512000, 0.0035633000, -0.004808000, -0.028767800, -0.093274400, -0.263646200", \ - "0.0074591000, 0.0063183000, 0.0034388000, -0.004928600, -0.028892400, -0.093352700, -0.263848900", \ - "0.0072990000, 0.0061690000, 0.0032717000, -0.005111400, -0.029031600, -0.093477700, -0.263945700", \ - "0.0072305000, 0.0060921000, 0.0031849000, -0.005237200, -0.029133800, -0.093559000, -0.263982200", \ - "0.0075143000, 0.0061452000, 0.0028687000, -0.005322000, -0.029191800, -0.093543400, -0.263977100", \ - "0.0095214000, 0.0081116000, 0.0045308000, -0.004734100, -0.029108700, -0.093313200, -0.263697300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0095011000, 0.0109049000, 0.0144957000, 0.0237271000, 0.0478580000, 0.1115118000, 0.2813633000", \ - "0.0094719000, 0.0108764000, 0.0144646000, 0.0236948000, 0.0478741000, 0.1116309000, 0.2799474000", \ - "0.0094591000, 0.0108472000, 0.0144326000, 0.0236789000, 0.0478987000, 0.1116485000, 0.2799726000", \ - "0.0093258000, 0.0106587000, 0.0142142000, 0.0235157000, 0.0477654000, 0.1115005000, 0.2800318000", \ - "0.0093602000, 0.0106791000, 0.0140606000, 0.0233783000, 0.0475160000, 0.1114571000, 0.2797010000", \ - "0.0096202000, 0.0109860000, 0.0145123000, 0.0235842000, 0.0478358000, 0.1118080000, 0.2799272000", \ - "0.0103175000, 0.0116151000, 0.0150946000, 0.0240907000, 0.0485780000, 0.1126945000, 0.2808742000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0074100000, 0.0062851000, 0.0034080000, -0.004979100, -0.028848600, -0.093227600, -0.263624600", \ - "0.0073542000, 0.0063092000, 0.0033594000, -0.005000900, -0.028891800, -0.093271100, -0.263750600", \ - "0.0073622000, 0.0062436000, 0.0033665000, -0.005024100, -0.028915400, -0.093295200, -0.263724600", \ - "0.0071019000, 0.0059596000, 0.0030939000, -0.005271300, -0.029174200, -0.093563100, -0.264003000", \ - "0.0068946000, 0.0057567000, 0.0028706000, -0.005500400, -0.029390400, -0.093779700, -0.264198300", \ - "0.0086758000, 0.0073711000, 0.0039738000, -0.005152600, -0.029347500, -0.093736200, -0.264170100", \ - "0.0089565000, 0.0076158000, 0.0043328000, -0.004779300, -0.029089500, -0.093564800, -0.264022900"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013201390, 0.0034855360, 0.0092027850, 0.0242979200, 0.0641532700, 0.1693825000"); - values("0.0093569000, 0.0107969000, 0.0144571000, 0.0238664000, 0.0481673000, 0.1120727000, 0.2809644000", \ - "0.0092584000, 0.0107097000, 0.0144100000, 0.0238022000, 0.0481291000, 0.1121345000, 0.2806840000", \ - "0.0093121000, 0.0107614000, 0.0144082000, 0.0238338000, 0.0483838000, 0.1121566000, 0.2809388000", \ - "0.0091643000, 0.0105991000, 0.0142785000, 0.0236607000, 0.0480205000, 0.1118390000, 0.2808076000", \ - "0.0088644000, 0.0103024000, 0.0139781000, 0.0233690000, 0.0477474000, 0.1123784000, 0.2808091000", \ - "0.0086901000, 0.0100470000, 0.0136464000, 0.0231499000, 0.0475369000, 0.1112907000, 0.2788237000", \ - "0.0088639000, 0.0102576000, 0.0138017000, 0.0231718000, 0.0474092000, 0.1119592000, 0.2811987000"); - } - } - max_capacitance : 0.1693830000; - max_transition : 1.5048480000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1827180000, 0.1911837000, 0.2085525000, 0.2416792000, 0.3054608000, 0.4450721000, 0.7958794000", \ - "0.1863619000, 0.1948622000, 0.2122374000, 0.2452735000, 0.3091268000, 0.4486197000, 0.7996051000", \ - "0.1971147000, 0.2055521000, 0.2228758000, 0.2559435000, 0.3198176000, 0.4593194000, 0.8103035000", \ - "0.2228337000, 0.2311076000, 0.2486572000, 0.2816886000, 0.3456461000, 0.4850856000, 0.8362559000", \ - "0.2828154000, 0.2912519000, 0.3084859000, 0.3416016000, 0.4056714000, 0.5452238000, 0.8954093000", \ - "0.3989799000, 0.4084349000, 0.4275697000, 0.4635753000, 0.5308650000, 0.6720228000, 1.0227220000", \ - "0.5992223000, 0.6105452000, 0.6333399000, 0.6753252000, 0.7502739000, 0.8981513000, 1.2515032000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0578322000, 0.0638824000, 0.0782266000, 0.1137338000, 0.2062527000, 0.4506279000, 1.0957903000", \ - "0.0625449000, 0.0685838000, 0.0829328000, 0.1185813000, 0.2112607000, 0.4556327000, 1.1008611000", \ - "0.0739085000, 0.0798619000, 0.0942029000, 0.1299546000, 0.2227462000, 0.4671686000, 1.1123659000", \ - "0.0964969000, 0.1024300000, 0.1170559000, 0.1528954000, 0.2458774000, 0.4898914000, 1.1342005000", \ - "0.1272864000, 0.1338853000, 0.1491282000, 0.1850322000, 0.2781473000, 0.5226386000, 1.1665411000", \ - "0.1595453000, 0.1685155000, 0.1856451000, 0.2223183000, 0.3157272000, 0.5599687000, 1.2054266000", \ - "0.1726957000, 0.1843016000, 0.2073464000, 0.2476005000, 0.3405360000, 0.5854364000, 1.2294677000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0323831000, 0.0380180000, 0.0508060000, 0.0769419000, 0.1394167000, 0.3043685000, 0.7674195000", \ - "0.0324933000, 0.0380854000, 0.0507120000, 0.0764683000, 0.1393522000, 0.3047037000, 0.7674150000", \ - "0.0323253000, 0.0382872000, 0.0507697000, 0.0764206000, 0.1393991000, 0.3047027000, 0.7671672000", \ - "0.0327773000, 0.0380178000, 0.0502601000, 0.0765604000, 0.1391618000, 0.3044445000, 0.7687020000", \ - "0.0325799000, 0.0382403000, 0.0502806000, 0.0768661000, 0.1391020000, 0.3046204000, 0.7669507000", \ - "0.0388542000, 0.0447710000, 0.0575321000, 0.0839779000, 0.1440879000, 0.3072922000, 0.7672583000", \ - "0.0516854000, 0.0584742000, 0.0727948000, 0.1000334000, 0.1614178000, 0.3175371000, 0.7682245000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0189566000, 0.0256971000, 0.0438799000, 0.0934356000, 0.2255410000, 0.5754624000, 1.5005276000", \ - "0.0188985000, 0.0256729000, 0.0439071000, 0.0935668000, 0.2262862000, 0.5765873000, 1.5014345000", \ - "0.0189151000, 0.0256481000, 0.0438207000, 0.0935714000, 0.2262833000, 0.5764975000, 1.5012548000", \ - "0.0201851000, 0.0268048000, 0.0445025000, 0.0935655000, 0.2259774000, 0.5749302000, 1.4973016000", \ - "0.0241695000, 0.0302102000, 0.0467749000, 0.0944315000, 0.2259224000, 0.5747452000, 1.4970253000", \ - "0.0324790000, 0.0384562000, 0.0530741000, 0.0972632000, 0.2270181000, 0.5743646000, 1.5012054000", \ - "0.0464964000, 0.0531090000, 0.0684884000, 0.1070998000, 0.2288082000, 0.5794235000, 1.4968244000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1855684000, 0.1940440000, 0.2114397000, 0.2446723000, 0.3084759000, 0.4482213000, 0.7990660000", \ - "0.1901723000, 0.1986283000, 0.2159871000, 0.2487947000, 0.3129112000, 0.4526513000, 0.8030094000", \ - "0.1999226000, 0.2084380000, 0.2258486000, 0.2590097000, 0.3228521000, 0.4625804000, 0.8134342000", \ - "0.2157343000, 0.2241873000, 0.2416493000, 0.2748331000, 0.3387486000, 0.4782019000, 0.8294297000", \ - "0.2378083000, 0.2461969000, 0.2635534000, 0.2966561000, 0.3605828000, 0.5001629000, 0.8507044000", \ - "0.2611079000, 0.2695612000, 0.2868451000, 0.3199851000, 0.3841903000, 0.5239105000, 0.8751852000", \ - "0.2749168000, 0.2834090000, 0.3007492000, 0.3339575000, 0.3982461000, 0.5380756000, 0.8890910000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.1143943000, 0.1205166000, 0.1351137000, 0.1713985000, 0.2646267000, 0.5120491000, 1.1565110000", \ - "0.1192452000, 0.1254011000, 0.1400530000, 0.1763172000, 0.2696061000, 0.5150238000, 1.1585466000", \ - "0.1317689000, 0.1379350000, 0.1524714000, 0.1886706000, 0.2821711000, 0.5275436000, 1.1748059000", \ - "0.1626621000, 0.1687704000, 0.1834191000, 0.2197683000, 0.3131090000, 0.5599447000, 1.2024202000", \ - "0.2212068000, 0.2273905000, 0.2420493000, 0.2781400000, 0.3714156000, 0.6166481000, 1.2602471000", \ - "0.3122217000, 0.3184338000, 0.3331818000, 0.3692582000, 0.4625626000, 0.7070303000, 1.3536159000", \ - "0.4555848000, 0.4622518000, 0.4772961000, 0.5136137000, 0.6069095000, 0.8520264000, 1.4960136000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0323311000, 0.0378954000, 0.0506921000, 0.0766902000, 0.1392018000, 0.3043338000, 0.7691640000", \ - "0.0323730000, 0.0382520000, 0.0506393000, 0.0770532000, 0.1393479000, 0.3044017000, 0.7671165000", \ - "0.0325081000, 0.0382371000, 0.0502127000, 0.0773172000, 0.1391079000, 0.3046659000, 0.7701763000", \ - "0.0327525000, 0.0384764000, 0.0502070000, 0.0772747000, 0.1388988000, 0.3043404000, 0.7681171000", \ - "0.0322921000, 0.0381696000, 0.0499744000, 0.0767401000, 0.1390372000, 0.3047237000, 0.7727580000", \ - "0.0326636000, 0.0385186000, 0.0509296000, 0.0764201000, 0.1393235000, 0.3038036000, 0.7693133000", \ - "0.0329993000, 0.0385875000, 0.0503366000, 0.0766197000, 0.1394899000, 0.3053660000, 0.7627712000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013201400, 0.0034855400, 0.0092027900, 0.0242979000, 0.0641533000, 0.1693830000"); - values("0.0191000000, 0.0257894000, 0.0437893000, 0.0931935000, 0.2253061000, 0.5777696000, 1.5047847000", \ - "0.0191505000, 0.0258088000, 0.0438537000, 0.0933187000, 0.2253337000, 0.5771875000, 1.4990005000", \ - "0.0191367000, 0.0257919000, 0.0437891000, 0.0931974000, 0.2259175000, 0.5764375000, 1.5009317000", \ - "0.0191586000, 0.0257638000, 0.0438823000, 0.0932930000, 0.2257052000, 0.5777857000, 1.5048477000", \ - "0.0196563000, 0.0262559000, 0.0441606000, 0.0932973000, 0.2256887000, 0.5778039000, 1.5007907000", \ - "0.0207685000, 0.0272501000, 0.0447714000, 0.0934160000, 0.2254543000, 0.5743278000, 1.4994093000", \ - "0.0234397000, 0.0294710000, 0.0461975000, 0.0941074000, 0.2255389000, 0.5748738000, 1.4997853000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2b_2") { - leakage_power () { - value : 0.0083291000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0019370000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0034451000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0012008000; - when : "A&!B_N"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__or2b"; - cell_leakage_power : 0.0037279830; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0017060000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016380000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030821000, 0.0030665000, 0.0030305000, 0.0030299000, 0.0030284000, 0.0030249000, 0.0030170000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002872400, -0.002905800, -0.002982800, -0.002983600, -0.002985200, -0.002989000, -0.002997800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017740000; - } - pin ("B_N") { - capacitance : 0.0014220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072326000, 0.0071512000, 0.0069636000, 0.0070389000, 0.0072124000, 0.0076125000, 0.0085346000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0005521000, 0.0004773000, 0.0003047000, 0.0003767000, 0.0005426000, 0.0009250000, 0.0018065000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014720000; - } - pin ("X") { - direction : "output"; - function : "(A) | (!B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0109790000, 0.0093305000, 0.0051101000, -0.006543600, -0.043737800, -0.156993900, -0.489246500", \ - "0.0109879000, 0.0092966000, 0.0050380000, -0.006809800, -0.043851600, -0.156918000, -0.489618100", \ - "0.0107830000, 0.0093092000, 0.0049807000, -0.006839400, -0.043923600, -0.157049000, -0.489695400", \ - "0.0106560000, 0.0089927000, 0.0048088000, -0.007102000, -0.044209400, -0.157131600, -0.489933000", \ - "0.0105210000, 0.0088354000, 0.0046482000, -0.007257700, -0.044424800, -0.157304500, -0.489993600", \ - "0.0107205000, 0.0089910000, 0.0047004000, -0.007285000, -0.044431600, -0.157414500, -0.489984800", \ - "0.0149851000, 0.0130955000, 0.0081006000, -0.005586300, -0.044578400, -0.156987000, -0.489620700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0144055000, 0.0160239000, 0.0207994000, 0.0343495000, 0.0730083000, 0.1854533000, 0.5165684000", \ - "0.0143676000, 0.0160473000, 0.0208196000, 0.0343133000, 0.0730009000, 0.1863389000, 0.5140555000", \ - "0.0143623000, 0.0160399000, 0.0208143000, 0.0343070000, 0.0730228000, 0.1853511000, 0.5141178000", \ - "0.0142911000, 0.0159291000, 0.0206100000, 0.0340818000, 0.0729225000, 0.1862951000, 0.5159494000", \ - "0.0143263000, 0.0158864000, 0.0205543000, 0.0339303000, 0.0726291000, 0.1854630000, 0.5144678000", \ - "0.0150110000, 0.0165556000, 0.0210788000, 0.0341732000, 0.0727257000, 0.1848374000, 0.5142181000", \ - "0.0157162000, 0.0171912000, 0.0215703000, 0.0347242000, 0.0733691000, 0.1861623000, 0.5149162000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0108339000, 0.0091819000, 0.0049152000, -0.006939900, -0.044087200, -0.156981400, -0.489603200", \ - "0.0106853000, 0.0090469000, 0.0048445000, -0.007037000, -0.044097800, -0.156986600, -0.489715900", \ - "0.0106434000, 0.0090017000, 0.0048151000, -0.006887100, -0.043989600, -0.157069200, -0.489677600", \ - "0.0105229000, 0.0088405000, 0.0046192000, -0.007214200, -0.044372600, -0.157309300, -0.490001400", \ - "0.0102657000, 0.0086518000, 0.0043955000, -0.007430000, -0.044551100, -0.157567200, -0.490178500", \ - "0.0120125000, 0.0102954000, 0.0055677000, -0.007417300, -0.044557300, -0.157546500, -0.490121700", \ - "0.0143073000, 0.0125891000, 0.0078257000, -0.005445800, -0.043915700, -0.157409100, -0.490029900"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0142936000, 0.0159911000, 0.0207852000, 0.0344437000, 0.0734860000, 0.1873066000, 0.5156121000", \ - "0.0142235000, 0.0159249000, 0.0207237000, 0.0343843000, 0.0734058000, 0.1872502000, 0.5163265000", \ - "0.0142519000, 0.0159687000, 0.0207691000, 0.0344270000, 0.0733939000, 0.1863101000, 0.5162471000", \ - "0.0141399000, 0.0158536000, 0.0206538000, 0.0343045000, 0.0732778000, 0.1861899000, 0.5160797000", \ - "0.0139041000, 0.0155914000, 0.0204066000, 0.0339674000, 0.0729937000, 0.1868109000, 0.5136227000", \ - "0.0139095000, 0.0155438000, 0.0201965000, 0.0337251000, 0.0728236000, 0.1852490000, 0.5174066000", \ - "0.0140891000, 0.0157549000, 0.0204197000, 0.0338272000, 0.0728855000, 0.1864695000, 0.5154486000"); - } - } - max_capacitance : 0.3122050000; - max_transition : 1.5049630000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2521650000, 0.2602225000, 0.2781356000, 0.3130472000, 0.3791661000, 0.5142198000, 0.8496892000", \ - "0.2564170000, 0.2643554000, 0.2822066000, 0.3174219000, 0.3836995000, 0.5183597000, 0.8534301000", \ - "0.2672151000, 0.2751158000, 0.2931095000, 0.3283472000, 0.3942176000, 0.5291382000, 0.8643141000", \ - "0.2927391000, 0.3006695000, 0.3184939000, 0.3536094000, 0.4199133000, 0.5544440000, 0.8904374000", \ - "0.3531756000, 0.3611476000, 0.3789347000, 0.4140303000, 0.4801461000, 0.6153295000, 0.9512316000", \ - "0.4869842000, 0.4952174000, 0.5138966000, 0.5501592000, 0.6165671000, 0.7528915000, 1.0884570000", \ - "0.7276686000, 0.7369315000, 0.7585239000, 0.8001378000, 0.8759070000, 1.0191382000, 1.3590858000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0694141000, 0.0743160000, 0.0863297000, 0.1157682000, 0.1962049000, 0.4289551000, 1.1060917000", \ - "0.0741024000, 0.0790184000, 0.0910124000, 0.1204660000, 0.2006005000, 0.4328201000, 1.1102202000", \ - "0.0853600000, 0.0903222000, 0.1023370000, 0.1316772000, 0.2120268000, 0.4441849000, 1.1217701000", \ - "0.1108978000, 0.1158563000, 0.1278053000, 0.1571133000, 0.2375267000, 0.4703804000, 1.1468551000", \ - "0.1505370000, 0.1563122000, 0.1696066000, 0.1998596000, 0.2802517000, 0.5123715000, 1.1908019000", \ - "0.1961781000, 0.2037564000, 0.2202800000, 0.2532052000, 0.3338254000, 0.5661094000, 1.2439304000", \ - "0.2297914000, 0.2402958000, 0.2623183000, 0.3037839000, 0.3872274000, 0.6197051000, 1.2955390000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0418527000, 0.0467120000, 0.0577995000, 0.0816555000, 0.1342684000, 0.2733891000, 0.6975109000", \ - "0.0418383000, 0.0465245000, 0.0578531000, 0.0810220000, 0.1345262000, 0.2720985000, 0.6988603000", \ - "0.0420829000, 0.0469283000, 0.0580678000, 0.0811798000, 0.1342786000, 0.2725462000, 0.6990052000", \ - "0.0422675000, 0.0468188000, 0.0578447000, 0.0809309000, 0.1338048000, 0.2733312000, 0.6983666000", \ - "0.0420007000, 0.0466949000, 0.0577585000, 0.0821572000, 0.1341556000, 0.2725765000, 0.6986102000", \ - "0.0466204000, 0.0510070000, 0.0620331000, 0.0847821000, 0.1364878000, 0.2740216000, 0.6992358000", \ - "0.0604389000, 0.0655183000, 0.0775070000, 0.1022927000, 0.1542991000, 0.2890652000, 0.7042774000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0173418000, 0.0219153000, 0.0344097000, 0.0715777000, 0.1848656000, 0.5202993000, 1.4984340000", \ - "0.0174842000, 0.0219072000, 0.0343929000, 0.0715716000, 0.1850051000, 0.5197467000, 1.4984723000", \ - "0.0173819000, 0.0219058000, 0.0344334000, 0.0714429000, 0.1848683000, 0.5194934000, 1.4985345000", \ - "0.0180437000, 0.0224464000, 0.0349050000, 0.0716879000, 0.1852524000, 0.5207040000, 1.4952329000", \ - "0.0231181000, 0.0273063000, 0.0388149000, 0.0739484000, 0.1853907000, 0.5190761000, 1.4993325000", \ - "0.0326344000, 0.0376273000, 0.0482106000, 0.0801577000, 0.1870992000, 0.5185526000, 1.4969146000", \ - "0.0468447000, 0.0532665000, 0.0668483000, 0.0970909000, 0.1929796000, 0.5216300000, 1.4951145000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.2543825000, 0.2623779000, 0.2802334000, 0.3154456000, 0.3816814000, 0.5164583000, 0.8520423000", \ - "0.2590617000, 0.2670242000, 0.2848635000, 0.3200434000, 0.3863536000, 0.5208846000, 0.8568802000", \ - "0.2689206000, 0.2769542000, 0.2948426000, 0.3300839000, 0.3957363000, 0.5310334000, 0.8663947000", \ - "0.2849441000, 0.2929875000, 0.3108013000, 0.3459678000, 0.4121687000, 0.5467514000, 0.8827074000", \ - "0.3064738000, 0.3144215000, 0.3323002000, 0.3672088000, 0.4333651000, 0.5687705000, 0.9041262000", \ - "0.3289680000, 0.3369297000, 0.3547830000, 0.3898981000, 0.4560336000, 0.5911638000, 0.9265504000", \ - "0.3412204000, 0.3491767000, 0.3669740000, 0.4019945000, 0.4682226000, 0.6037271000, 0.9394260000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.1268182000, 0.1318151000, 0.1437868000, 0.1734501000, 0.2540151000, 0.4869235000, 1.1681931000", \ - "0.1315860000, 0.1365805000, 0.1485602000, 0.1782182000, 0.2588494000, 0.4910330000, 1.1729584000", \ - "0.1443282000, 0.1492898000, 0.1613035000, 0.1909391000, 0.2717105000, 0.5056668000, 1.1857126000", \ - "0.1750844000, 0.1800498000, 0.1920618000, 0.2216788000, 0.3024468000, 0.5367800000, 1.2161410000", \ - "0.2340860000, 0.2390856000, 0.2512120000, 0.2808155000, 0.3615288000, 0.5942740000, 1.2853524000", \ - "0.3258623000, 0.3310188000, 0.3432773000, 0.3729956000, 0.4534152000, 0.6859161000, 1.3655475000", \ - "0.4708423000, 0.4764324000, 0.4893234000, 0.5193723000, 0.6002123000, 0.8326380000, 1.5090337000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0418337000, 0.0466246000, 0.0578852000, 0.0811565000, 0.1338476000, 0.2722985000, 0.6989949000", \ - "0.0418481000, 0.0468270000, 0.0578718000, 0.0809839000, 0.1338481000, 0.2732668000, 0.6985185000", \ - "0.0418563000, 0.0467224000, 0.0577896000, 0.0821532000, 0.1347189000, 0.2729076000, 0.6996130000", \ - "0.0418447000, 0.0466629000, 0.0582242000, 0.0812661000, 0.1343052000, 0.2726076000, 0.6987688000", \ - "0.0420870000, 0.0470553000, 0.0578061000, 0.0814600000, 0.1340720000, 0.2724609000, 0.6984052000", \ - "0.0419647000, 0.0467966000, 0.0579353000, 0.0812251000, 0.1346202000, 0.2726372000, 0.6979964000", \ - "0.0424709000, 0.0470287000, 0.0578898000, 0.0822665000, 0.1337779000, 0.2723566000, 0.6960601000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0175872000, 0.0219054000, 0.0343695000, 0.0713245000, 0.1846059000, 0.5212618000, 1.4997259000", \ - "0.0176129000, 0.0219372000, 0.0343623000, 0.0713329000, 0.1844640000, 0.5220365000, 1.5049627000", \ - "0.0176350000, 0.0219677000, 0.0343347000, 0.0714255000, 0.1843532000, 0.5199448000, 1.5047661000", \ - "0.0176523000, 0.0219484000, 0.0343287000, 0.0714545000, 0.1843073000, 0.5202243000, 1.5042340000", \ - "0.0179678000, 0.0222996000, 0.0346717000, 0.0715990000, 0.1845969000, 0.5213490000, 1.5012475000", \ - "0.0192042000, 0.0234942000, 0.0355952000, 0.0720364000, 0.1842162000, 0.5186012000, 1.5035022000", \ - "0.0216527000, 0.0260697000, 0.0374720000, 0.0729741000, 0.1846712000, 0.5187208000, 1.4969183000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or2b_4") { - leakage_power () { - value : 0.0073823000; - when : "!A&B_N"; - } - leakage_power () { - value : 0.0046341000; - when : "!A&!B_N"; - } - leakage_power () { - value : 0.0047712000; - when : "A&B_N"; - } - leakage_power () { - value : 0.0024191000; - when : "A&!B_N"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__or2b"; - cell_leakage_power : 0.0048016680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023280000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041476000, 0.0041447000, 0.0041380000, 0.0041397000, 0.0041439000, 0.0041534000, 0.0041753000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003915400, -0.003967500, -0.004087600, -0.004089600, -0.004094300, -0.004105100, -0.004129900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026210000; - } - pin ("B_N") { - capacitance : 0.0015690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015060000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092688000, 0.0091603000, 0.0089104000, 0.0089761000, 0.0091276000, 0.0094768000, 0.0102817000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0018585000, 0.0017966000, 0.0016539000, 0.0017138000, 0.0018521000, 0.0021709000, 0.0029055000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016330000; - } - pin ("X") { - direction : "output"; - function : "(A) | (!B_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509840, 0.0160538400, 0.0510248800, 0.1621754000, 0.5154517000"); - values("0.0228747000, 0.0210981000, 0.0155785000, 3.140000e-05, -0.052621700, -0.230552500, -0.802690600", \ - "0.0226893000, 0.0208481000, 0.0153727000, -0.000187700, -0.052715700, -0.230722900, -0.802646300", \ - "0.0225079000, 0.0206850000, 0.0151795000, -0.000112400, -0.052992000, -0.231094200, -0.802949900", \ - "0.0223695000, 0.0205435000, 0.0150551000, -0.000607500, -0.053277400, -0.231196100, -0.803214400", \ - "0.0221180000, 0.0203248000, 0.0146763000, -0.000927700, -0.053639200, -0.231486900, -0.803538400", \ - "0.0223122000, 0.0204073000, 0.0148475000, -0.001147600, -0.053963800, -0.231742100, -0.803413700", \ - "0.0301944000, 0.0293561000, 0.0229933000, 0.0046630000, -0.052236500, -0.231294600, -0.802963200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509840, 0.0160538400, 0.0510248800, 0.1621754000, 0.5154517000"); - values("0.0287900000, 0.0306902000, 0.0365507000, 0.0549527000, 0.1117594000, 0.2901545000, 0.8552855000", \ - "0.0287146000, 0.0306273000, 0.0364847000, 0.0549194000, 0.1117252000, 0.2901577000, 0.8557141000", \ - "0.0285986000, 0.0304867000, 0.0364939000, 0.0548920000, 0.1117174000, 0.2901534000, 0.8552656000", \ - "0.0285519000, 0.0304156000, 0.0362152000, 0.0545213000, 0.1113193000, 0.2901715000, 0.8559383000", \ - "0.0284846000, 0.0303397000, 0.0360593000, 0.0541057000, 0.1107678000, 0.2898271000, 0.8561022000", \ - "0.0292748000, 0.0310511000, 0.0365395000, 0.0544307000, 0.1104727000, 0.2883566000, 0.8552553000", \ - "0.0312118000, 0.0327899000, 0.0382836000, 0.0557388000, 0.1120543000, 0.2901595000, 0.8538671000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509840, 0.0160538400, 0.0510248800, 0.1621754000, 0.5154517000"); - values("0.0218731000, 0.0200243000, 0.0145353000, -0.000989800, -0.053609000, -0.231350300, -0.803143300", \ - "0.0218948000, 0.0200662000, 0.0145826000, -0.000978100, -0.053662700, -0.231351100, -0.803158800", \ - "0.0218658000, 0.0200081000, 0.0145229000, -0.001033900, -0.053649000, -0.231372300, -0.803331000", \ - "0.0215470000, 0.0197000000, 0.0142010000, -0.001370000, -0.053928300, -0.231714600, -0.803651400", \ - "0.0213192000, 0.0194236000, 0.0139883000, -0.001666700, -0.054302100, -0.232098700, -0.803958800", \ - "0.0247643000, 0.0229205000, 0.0171033000, -0.000505700, -0.054345800, -0.232211900, -0.804021900", \ - "0.0280546000, 0.0261759000, 0.0204939000, 0.0030215000, -0.052705800, -0.231790700, -0.803894900"); - } - related_pin : "B_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509840, 0.0160538400, 0.0510248800, 0.1621754000, 0.5154517000"); - values("0.0282957000, 0.0302283000, 0.0362364000, 0.0546232000, 0.1118644000, 0.2909885000, 0.8540568000", \ - "0.0282499000, 0.0301657000, 0.0362005000, 0.0546359000, 0.1117747000, 0.2910407000, 0.8543270000", \ - "0.0282241000, 0.0300668000, 0.0360951000, 0.0546796000, 0.1118545000, 0.2908495000, 0.8580318000", \ - "0.0279654000, 0.0298524000, 0.0358375000, 0.0544171000, 0.1116406000, 0.2906276000, 0.8582808000", \ - "0.0275824000, 0.0294894000, 0.0354963000, 0.0540037000, 0.1111122000, 0.2903316000, 0.8529534000", \ - "0.0275723000, 0.0293597000, 0.0349677000, 0.0535070000, 0.1104098000, 0.2896721000, 0.8568710000", \ - "0.0281971000, 0.0300362000, 0.0358263000, 0.0540450000, 0.1107416000, 0.2902447000, 0.8553993000"); - } - } - max_capacitance : 0.5154520000; - max_transition : 1.5058010000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.2150733000, 0.2196821000, 0.2317055000, 0.2581698000, 0.3115409000, 0.4252341000, 0.7281718000", \ - "0.2199712000, 0.2246453000, 0.2366338000, 0.2631042000, 0.3160020000, 0.4301574000, 0.7329302000", \ - "0.2318925000, 0.2365071000, 0.2484968000, 0.2748177000, 0.3279230000, 0.4421953000, 0.7446763000", \ - "0.2585218000, 0.2631221000, 0.2750400000, 0.3014274000, 0.3546667000, 0.4686453000, 0.7714592000", \ - "0.3211497000, 0.3257472000, 0.3376312000, 0.3640970000, 0.4173512000, 0.5317859000, 0.8348466000", \ - "0.4542935000, 0.4592462000, 0.4723633000, 0.5003544000, 0.5555486000, 0.6710231000, 0.9738824000", \ - "0.6902798000, 0.6964538000, 0.7113207000, 0.7441016000, 0.8071825000, 0.9327169000, 1.2405211000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.0785379000, 0.0820435000, 0.0915951000, 0.1169379000, 0.1894452000, 0.4149282000, 1.1267086000", \ - "0.0830926000, 0.0866114000, 0.0961396000, 0.1214969000, 0.1940172000, 0.4192314000, 1.1318755000", \ - "0.0939026000, 0.0974030000, 0.1070359000, 0.1323318000, 0.2048993000, 0.4305941000, 1.1420221000", \ - "0.1196070000, 0.1230851000, 0.1325453000, 0.1577139000, 0.2302020000, 0.4554164000, 1.1693967000", \ - "0.1617035000, 0.1657528000, 0.1759299000, 0.2020333000, 0.2746657000, 0.4999473000, 1.2134365000", \ - "0.2105157000, 0.2157517000, 0.2286618000, 0.2577399000, 0.3309530000, 0.5560581000, 1.2707634000", \ - "0.2463435000, 0.2533949000, 0.2709707000, 0.3077530000, 0.3849812000, 0.6086430000, 1.3206325000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.0376592000, 0.0404665000, 0.0477727000, 0.0649275000, 0.1054325000, 0.2215231000, 0.6049372000", \ - "0.0375727000, 0.0402866000, 0.0474700000, 0.0649631000, 0.1059268000, 0.2211855000, 0.6053189000", \ - "0.0377109000, 0.0404693000, 0.0473433000, 0.0645086000, 0.1052580000, 0.2213336000, 0.6054700000", \ - "0.0378300000, 0.0405785000, 0.0474671000, 0.0641555000, 0.1055015000, 0.2211431000, 0.6046259000", \ - "0.0377939000, 0.0405516000, 0.0476067000, 0.0652423000, 0.1052442000, 0.2212052000, 0.6043385000", \ - "0.0433939000, 0.0461384000, 0.0535484000, 0.0701814000, 0.1094883000, 0.2229165000, 0.6046935000", \ - "0.0588892000, 0.0615911000, 0.0697652000, 0.0876983000, 0.1296373000, 0.2397656000, 0.6095696000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.0196628000, 0.0228101000, 0.0323524000, 0.0623954000, 0.1615574000, 0.4833097000, 1.5000139000", \ - "0.0196916000, 0.0227849000, 0.0322742000, 0.0622727000, 0.1618145000, 0.4834614000, 1.5013043000", \ - "0.0197684000, 0.0228646000, 0.0323558000, 0.0624055000, 0.1615179000, 0.4828983000, 1.4994080000", \ - "0.0199304000, 0.0230703000, 0.0325410000, 0.0623597000, 0.1614149000, 0.4829949000, 1.5040749000", \ - "0.0249014000, 0.0278312000, 0.0369913000, 0.0648413000, 0.1619827000, 0.4827470000, 1.5027859000", \ - "0.0346343000, 0.0380110000, 0.0464033000, 0.0720410000, 0.1645052000, 0.4816576000, 1.5019337000", \ - "0.0506661000, 0.0540749000, 0.0646137000, 0.0897641000, 0.1720094000, 0.4841078000, 1.4982178000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.2269333000, 0.2316266000, 0.2435590000, 0.2700450000, 0.3232925000, 0.4372786000, 0.7401249000", \ - "0.2317020000, 0.2363064000, 0.2482982000, 0.2748012000, 0.3281433000, 0.4420347000, 0.7446751000", \ - "0.2426999000, 0.2473730000, 0.2592725000, 0.2857651000, 0.3391000000, 0.4530794000, 0.7561148000", \ - "0.2632415000, 0.2679202000, 0.2798348000, 0.3062899000, 0.3597145000, 0.4735374000, 0.7764629000", \ - "0.2926756000, 0.2973007000, 0.3092312000, 0.3356343000, 0.3885641000, 0.5030886000, 0.8056431000", \ - "0.3275635000, 0.3321944000, 0.3441071000, 0.3705606000, 0.4239127000, 0.5383517000, 0.8412176000", \ - "0.3583850000, 0.3630470000, 0.3748853000, 0.4015538000, 0.4548724000, 0.5694821000, 0.8725736000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.1675756000, 0.1712066000, 0.1809381000, 0.2064116000, 0.2793741000, 0.5058194000, 1.2190516000", \ - "0.1722509000, 0.1758567000, 0.1856087000, 0.2111568000, 0.2841741000, 0.5096680000, 1.2229102000", \ - "0.1846537000, 0.1882267000, 0.1980230000, 0.2236495000, 0.2966830000, 0.5228751000, 1.2385704000", \ - "0.2155175000, 0.2191262000, 0.2289049000, 0.2545372000, 0.3275533000, 0.5535188000, 1.2669671000", \ - "0.2834067000, 0.2870025000, 0.2968098000, 0.3223630000, 0.3953528000, 0.6217607000, 1.3335915000", \ - "0.3971913000, 0.4009191000, 0.4108472000, 0.4366654000, 0.5095019000, 0.7351300000, 1.4516747000", \ - "0.5745164000, 0.5787409000, 0.5893261000, 0.6155869000, 0.6881412000, 0.9137262000, 1.6271681000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.0375636000, 0.0402741000, 0.0476177000, 0.0649874000, 0.1050389000, 0.2211483000, 0.6051870000", \ - "0.0376258000, 0.0403381000, 0.0477613000, 0.0649278000, 0.1053136000, 0.2211424000, 0.6054884000", \ - "0.0375721000, 0.0402792000, 0.0477080000, 0.0650454000, 0.1057671000, 0.2211463000, 0.6047862000", \ - "0.0375643000, 0.0402725000, 0.0475658000, 0.0649557000, 0.1052800000, 0.2210838000, 0.6047552000", \ - "0.0375911000, 0.0404161000, 0.0473427000, 0.0647203000, 0.1050254000, 0.2211880000, 0.6048949000", \ - "0.0379236000, 0.0407500000, 0.0479919000, 0.0651529000, 0.1062652000, 0.2206302000, 0.6050531000", \ - "0.0378623000, 0.0405641000, 0.0481377000, 0.0656294000, 0.1055307000, 0.2214860000, 0.6054818000"); - } - related_pin : "B_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015891800, 0.0050509800, 0.0160538000, 0.0510249000, 0.1621750000, 0.5154520000"); - values("0.0207304000, 0.0238224000, 0.0330209000, 0.0626289000, 0.1610802000, 0.4822617000, 1.5019996000", \ - "0.0207376000, 0.0238320000, 0.0329923000, 0.0625281000, 0.1612799000, 0.4821021000, 1.4996838000", \ - "0.0208881000, 0.0238943000, 0.0330923000, 0.0625818000, 0.1612943000, 0.4816480000, 1.5031353000", \ - "0.0208691000, 0.0238349000, 0.0330938000, 0.0626037000, 0.1610201000, 0.4828523000, 1.5058014000", \ - "0.0209780000, 0.0240210000, 0.0332439000, 0.0627148000, 0.1614113000, 0.4819444000, 1.5012188000", \ - "0.0224327000, 0.0254508000, 0.0345126000, 0.0634014000, 0.1611882000, 0.4819132000, 1.5021289000", \ - "0.0255030000, 0.0285312000, 0.0371497000, 0.0649820000, 0.1620118000, 0.4803948000, 1.4994734000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3_1") { - leakage_power () { - value : 0.0010873000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0066082000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0003543000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0006162000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0003505000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0005888000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0003213000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0003500000; - when : "A&B&!C"; - } - area : 6.2560000000; - cell_footprint : "sky130_fd_sc_hd__or3"; - cell_leakage_power : 0.0012845550; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015700000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017211000, 0.0017041000, 0.0016649000, 0.0016653000, 0.0016665000, 0.0016690000, 0.0016749000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001437800, -0.001455400, -0.001496000, -0.001500900, -0.001512300, -0.001538400, -0.001598700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016700000; - } - pin ("B") { - capacitance : 0.0016360000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015480000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022197000, 0.0022466000, 0.0023088000, 0.0023086000, 0.0023081000, 0.0023071000, 0.0023046000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002032900, -0.002100600, -0.002256700, -0.002258500, -0.002262700, -0.002272400, -0.002294600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017230000; - } - pin ("C") { - capacitance : 0.0013960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0010973000, 0.0010956000, 0.0010919000, 0.0010952000, 0.0011027000, 0.0011202000, 0.0011605000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000750200, -0.000743100, -0.000726800, -0.000726800, -0.000726800, -0.000726700, -0.000726600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014920000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0098823000, 0.0088118000, 0.0059675000, -0.002066800, -0.025119800, -0.088714800, -0.257213200", \ - "0.0097065000, 0.0086565000, 0.0059445000, -0.002080400, -0.025306400, -0.088896800, -0.257351900", \ - "0.0095746000, 0.0084958000, 0.0056604000, -0.002391200, -0.025462000, -0.089036600, -0.257499200", \ - "0.0094021000, 0.0083387000, 0.0054968000, -0.002554100, -0.025662400, -0.089192100, -0.257660200", \ - "0.0093000000, 0.0082096000, 0.0053971000, -0.002669500, -0.025821500, -0.089326600, -0.257756700", \ - "0.0092812000, 0.0082295000, 0.0053434000, -0.002745700, -0.025899300, -0.089396700, -0.257787300", \ - "0.0123010000, 0.0108638000, 0.0072404000, -0.002033800, -0.026133700, -0.089320700, -0.257687700"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0096821000, 0.0110858000, 0.0146892000, 0.0238815000, 0.0480350000, 0.1108547000, 0.2773525000", \ - "0.0096391000, 0.0110629000, 0.0146628000, 0.0238594000, 0.0477823000, 0.1109290000, 0.2772865000", \ - "0.0096137000, 0.0110195000, 0.0146174000, 0.0238441000, 0.0480138000, 0.1108578000, 0.2773106000", \ - "0.0095553000, 0.0109380000, 0.0144815000, 0.0237310000, 0.0477661000, 0.1113568000, 0.2786548000", \ - "0.0095912000, 0.0108769000, 0.0144219000, 0.0235202000, 0.0476098000, 0.1107352000, 0.2783520000", \ - "0.0097188000, 0.0110383000, 0.0145251000, 0.0235988000, 0.0477201000, 0.1103768000, 0.2785032000", \ - "0.0104855000, 0.0118110000, 0.0152308000, 0.0243986000, 0.0481056000, 0.1117742000, 0.2765143000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0087838000, 0.0076909000, 0.0049443000, -0.003057500, -0.026244700, -0.089726500, -0.258210900", \ - "0.0087512000, 0.0076319000, 0.0047835000, -0.003287300, -0.026444500, -0.089917500, -0.258298900", \ - "0.0084175000, 0.0073120000, 0.0044890000, -0.003536400, -0.026649300, -0.090088500, -0.258469900", \ - "0.0082687000, 0.0071938000, 0.0043637000, -0.003687600, -0.026787000, -0.090244500, -0.258626700", \ - "0.0081991000, 0.0070975000, 0.0042717000, -0.003786400, -0.026901400, -0.090344600, -0.258728800", \ - "0.0082027000, 0.0070689000, 0.0041922000, -0.003869800, -0.026980800, -0.090411400, -0.258760600", \ - "0.0112942000, 0.0098255000, 0.0061776000, -0.003141000, -0.027039100, -0.089941000, -0.258451300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0092462000, 0.0106878000, 0.0143718000, 0.0237196000, 0.0478796000, 0.1111691000, 0.2774550000", \ - "0.0092972000, 0.0107416000, 0.0144130000, 0.0237803000, 0.0479254000, 0.1110604000, 0.2789665000", \ - "0.0093960000, 0.0108184000, 0.0144784000, 0.0238136000, 0.0479944000, 0.1117737000, 0.2789556000", \ - "0.0092518000, 0.0106311000, 0.0142586000, 0.0235846000, 0.0478619000, 0.1111096000, 0.2775214000", \ - "0.0092749000, 0.0105949000, 0.0140161000, 0.0232549000, 0.0475034000, 0.1109034000, 0.2773535000", \ - "0.0094624000, 0.0107637000, 0.0143099000, 0.0233203000, 0.0475711000, 0.1110468000, 0.2773817000", \ - "0.0099683000, 0.0112714000, 0.0147380000, 0.0239219000, 0.0480169000, 0.1115599000, 0.2782684000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0081876000, 0.0071132000, 0.0042639000, -0.003751900, -0.026858700, -0.090218700, -0.258576600", \ - "0.0080865000, 0.0069694000, 0.0041468000, -0.003879500, -0.026981300, -0.090371300, -0.258708700", \ - "0.0078866000, 0.0068061000, 0.0040438000, -0.004049300, -0.027094900, -0.090512300, -0.258866800", \ - "0.0077838000, 0.0066995000, 0.0038734000, -0.004165600, -0.027265300, -0.090689000, -0.258988600", \ - "0.0077202000, 0.0066160000, 0.0038112000, -0.004230500, -0.027345200, -0.090720600, -0.259064600", \ - "0.0079593000, 0.0071216000, 0.0040796000, -0.003734800, -0.026925800, -0.090447100, -0.258802400", \ - "0.0120065000, 0.0105002000, 0.0066504000, -0.002742800, -0.026844900, -0.090168400, -0.258458600"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0080025000, 0.0094449000, 0.0131000000, 0.0224807000, 0.0465825000, 0.1098523000, 0.2777929000", \ - "0.0079951000, 0.0094326000, 0.0130814000, 0.0224456000, 0.0466143000, 0.1104737000, 0.2765044000", \ - "0.0079275000, 0.0093468000, 0.0130063000, 0.0223521000, 0.0467239000, 0.1104068000, 0.2766972000", \ - "0.0077766000, 0.0091908000, 0.0128023000, 0.0221225000, 0.0463302000, 0.1097991000, 0.2757210000", \ - "0.0077861000, 0.0090931000, 0.0126110000, 0.0217763000, 0.0459304000, 0.1100496000, 0.2760720000", \ - "0.0078619000, 0.0091694000, 0.0126981000, 0.0219365000, 0.0459903000, 0.1089091000, 0.2776209000", \ - "0.0084417000, 0.0097262000, 0.0132153000, 0.0223584000, 0.0462941000, 0.1100566000, 0.2750336000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5030600000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3264345000, 0.3378679000, 0.3611040000, 0.4044878000, 0.4836080000, 0.6388017000, 0.9927376000", \ - "0.3277606000, 0.3393349000, 0.3624945000, 0.4058246000, 0.4853324000, 0.6402563000, 0.9944013000", \ - "0.3362008000, 0.3475863000, 0.3707219000, 0.4141604000, 0.4932061000, 0.6484578000, 1.0025787000", \ - "0.3593536000, 0.3708793000, 0.3940050000, 0.4374138000, 0.5162802000, 0.6717993000, 1.0257839000", \ - "0.4128218000, 0.4238392000, 0.4471677000, 0.4904061000, 0.5698413000, 0.7253060000, 1.0794400000", \ - "0.5260241000, 0.5378809000, 0.5615899000, 0.6055847000, 0.6852149000, 0.8407840000, 1.1946644000", \ - "0.7275415000, 0.7402504000, 0.7668572000, 0.8156309000, 0.9031454000, 1.0660874000, 1.4248105000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0645589000, 0.0708958000, 0.0858378000, 0.1220192000, 0.2152768000, 0.4592835000, 1.1025840000", \ - "0.0693380000, 0.0757511000, 0.0905980000, 0.1267700000, 0.2201557000, 0.4643141000, 1.1072141000", \ - "0.0808100000, 0.0871569000, 0.1019938000, 0.1382694000, 0.2316146000, 0.4754118000, 1.1189566000", \ - "0.1063220000, 0.1126995000, 0.1275296000, 0.1635000000, 0.2567074000, 0.5017362000, 1.1452134000", \ - "0.1434123000, 0.1505179000, 0.1661162000, 0.2022968000, 0.2955211000, 0.5400539000, 1.1855413000", \ - "0.1860173000, 0.1945528000, 0.2125649000, 0.2503935000, 0.3435011000, 0.5876258000, 1.2325991000", \ - "0.2150982000, 0.2271093000, 0.2503874000, 0.2931426000, 0.3854990000, 0.6306858000, 1.2723066000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0485270000, 0.0555297000, 0.0709514000, 0.1033301000, 0.1693874000, 0.3295445000, 0.7699436000", \ - "0.0481960000, 0.0555049000, 0.0711598000, 0.1037978000, 0.1687155000, 0.3291657000, 0.7675253000", \ - "0.0485018000, 0.0554978000, 0.0709810000, 0.1034093000, 0.1706424000, 0.3294845000, 0.7667782000", \ - "0.0481519000, 0.0555251000, 0.0709942000, 0.1031632000, 0.1701496000, 0.3294407000, 0.7700256000", \ - "0.0483831000, 0.0558763000, 0.0713745000, 0.1037986000, 0.1695425000, 0.3286734000, 0.7676850000", \ - "0.0513182000, 0.0589017000, 0.0741300000, 0.1047565000, 0.1711895000, 0.3292936000, 0.7701609000", \ - "0.0600186000, 0.0690232000, 0.0862664000, 0.1183540000, 0.1874641000, 0.3437082000, 0.7745051000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0207061000, 0.0275250000, 0.0456533000, 0.0950432000, 0.2271508000, 0.5751298000, 1.4983773000", \ - "0.0206814000, 0.0275139000, 0.0456249000, 0.0949108000, 0.2268922000, 0.5745153000, 1.4977413000", \ - "0.0205500000, 0.0273680000, 0.0455226000, 0.0947482000, 0.2271763000, 0.5755485000, 1.4986593000", \ - "0.0213385000, 0.0279001000, 0.0456628000, 0.0947784000, 0.2269975000, 0.5766807000, 1.4974904000", \ - "0.0255328000, 0.0316269000, 0.0482077000, 0.0959162000, 0.2269155000, 0.5759058000, 1.4979370000", \ - "0.0337016000, 0.0400930000, 0.0550482000, 0.0988671000, 0.2284589000, 0.5757025000, 1.4978054000", \ - "0.0473629000, 0.0546955000, 0.0700342000, 0.1087512000, 0.2303542000, 0.5786684000, 1.4935966000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3029136000, 0.3142519000, 0.3373279000, 0.3807266000, 0.4602461000, 0.6152955000, 0.9695671000", \ - "0.3046330000, 0.3159071000, 0.3391235000, 0.3826522000, 0.4620017000, 0.6169314000, 0.9712084000", \ - "0.3128514000, 0.3242223000, 0.3474908000, 0.3907625000, 0.4694980000, 0.6251133000, 0.9791837000", \ - "0.3367336000, 0.3480073000, 0.3711053000, 0.4145226000, 0.4934184000, 0.6491540000, 1.0032780000", \ - "0.3944508000, 0.4057264000, 0.4290018000, 0.4721697000, 0.5516904000, 0.7073377000, 1.0615144000", \ - "0.5257325000, 0.5374934000, 0.5612545000, 0.6054703000, 0.6847906000, 0.8408353000, 1.1951482000", \ - "0.7624718000, 0.7757752000, 0.8032618000, 0.8530741000, 0.9411490000, 1.1025996000, 1.4609479000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0630979000, 0.0694892000, 0.0844567000, 0.1210394000, 0.2144733000, 0.4590875000, 1.1028457000", \ - "0.0678784000, 0.0742685000, 0.0892207000, 0.1256228000, 0.2189731000, 0.4636799000, 1.1076255000", \ - "0.0794362000, 0.0857670000, 0.1006344000, 0.1370454000, 0.2307697000, 0.4758299000, 1.1208676000", \ - "0.1036220000, 0.1098437000, 0.1248034000, 0.1612570000, 0.2549118000, 0.4997450000, 1.1434249000", \ - "0.1382692000, 0.1452847000, 0.1607608000, 0.1974052000, 0.2910849000, 0.5361040000, 1.1798220000", \ - "0.1764555000, 0.1854952000, 0.2035815000, 0.2408573000, 0.3343344000, 0.5792518000, 1.2231537000", \ - "0.1973901000, 0.2094967000, 0.2335483000, 0.2767068000, 0.3702468000, 0.6156269000, 1.2584735000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0483594000, 0.0560615000, 0.0714530000, 0.1020572000, 0.1686668000, 0.3290644000, 0.7675796000", \ - "0.0481133000, 0.0555999000, 0.0708781000, 0.1030429000, 0.1701966000, 0.3286165000, 0.7685759000", \ - "0.0483852000, 0.0559254000, 0.0715649000, 0.1022832000, 0.1708955000, 0.3296560000, 0.7688121000", \ - "0.0484919000, 0.0555381000, 0.0709642000, 0.1032451000, 0.1699738000, 0.3293903000, 0.7704059000", \ - "0.0489493000, 0.0563396000, 0.0720077000, 0.1024516000, 0.1684121000, 0.3293885000, 0.7670591000", \ - "0.0519110000, 0.0592709000, 0.0742036000, 0.1047336000, 0.1716616000, 0.3305692000, 0.7679988000", \ - "0.0650545000, 0.0735115000, 0.0899494000, 0.1219888000, 0.1894827000, 0.3439190000, 0.7747007000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0198954000, 0.0266111000, 0.0447289000, 0.0941503000, 0.2268196000, 0.5767533000, 1.4988456000", \ - "0.0198939000, 0.0265840000, 0.0447234000, 0.0940923000, 0.2261928000, 0.5760009000, 1.4984077000", \ - "0.0198779000, 0.0266438000, 0.0447100000, 0.0940832000, 0.2268359000, 0.5770358000, 1.4996634000", \ - "0.0209242000, 0.0274620000, 0.0451961000, 0.0942277000, 0.2269513000, 0.5764600000, 1.4974162000", \ - "0.0249534000, 0.0311924000, 0.0478900000, 0.0952557000, 0.2266476000, 0.5761080000, 1.4973194000", \ - "0.0338853000, 0.0397851000, 0.0549016000, 0.0983562000, 0.2275518000, 0.5751101000, 1.4929470000", \ - "0.0483891000, 0.0552858000, 0.0713600000, 0.1093377000, 0.2298673000, 0.5795051000, 1.4932523000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.2677639000, 0.2791986000, 0.3023546000, 0.3456933000, 0.4253237000, 0.5800098000, 0.9341440000", \ - "0.2686211000, 0.2799173000, 0.3032656000, 0.3466395000, 0.4262939000, 0.5809446000, 0.9350670000", \ - "0.2750779000, 0.2864559000, 0.3097434000, 0.3532890000, 0.4321853000, 0.5880040000, 0.9421557000", \ - "0.2980825000, 0.3093656000, 0.3332835000, 0.3763986000, 0.4559235000, 0.6116412000, 0.9660118000", \ - "0.3597299000, 0.3710538000, 0.3944520000, 0.4380790000, 0.5174268000, 0.6730042000, 1.0271938000", \ - "0.5025418000, 0.5148432000, 0.5386017000, 0.5817887000, 0.6615490000, 0.8174306000, 1.1720241000", \ - "0.7466158000, 0.7609506000, 0.7890505000, 0.8400151000, 0.9271641000, 1.0882005000, 1.4466746000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0597987000, 0.0662203000, 0.0811495000, 0.1175524000, 0.2108832000, 0.4558249000, 1.0997454000", \ - "0.0647744000, 0.0711894000, 0.0860967000, 0.1225489000, 0.2160843000, 0.4605728000, 1.1032207000", \ - "0.0765231000, 0.0828840000, 0.0977344000, 0.1341525000, 0.2279926000, 0.4731906000, 1.1188495000", \ - "0.1001696000, 0.1066107000, 0.1215727000, 0.1579672000, 0.2514357000, 0.4958237000, 1.1522620000", \ - "0.1336882000, 0.1409219000, 0.1567233000, 0.1934322000, 0.2868275000, 0.5316583000, 1.1746020000", \ - "0.1706563000, 0.1799753000, 0.1987144000, 0.2369725000, 0.3299701000, 0.5744027000, 1.2199144000", \ - "0.1929908000, 0.2057536000, 0.2305624000, 0.2750611000, 0.3692402000, 0.6125356000, 1.2555428000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0484085000, 0.0558667000, 0.0713184000, 0.1022434000, 0.1688065000, 0.3296941000, 0.7687290000", \ - "0.0485337000, 0.0559441000, 0.0714942000, 0.1024304000, 0.1696080000, 0.3296302000, 0.7688021000", \ - "0.0483672000, 0.0558064000, 0.0710736000, 0.1034361000, 0.1697171000, 0.3293295000, 0.7702138000", \ - "0.0483242000, 0.0556944000, 0.0709935000, 0.1037753000, 0.1702596000, 0.3289735000, 0.7669152000", \ - "0.0483759000, 0.0559742000, 0.0709411000, 0.1031832000, 0.1695713000, 0.3288881000, 0.7709720000", \ - "0.0525375000, 0.0595582000, 0.0743413000, 0.1065549000, 0.1719364000, 0.3298651000, 0.7689547000", \ - "0.0709523000, 0.0791141000, 0.0966858000, 0.1259396000, 0.1891894000, 0.3420912000, 0.7741407000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0198654000, 0.0265989000, 0.0446102000, 0.0939975000, 0.2264666000, 0.5771986000, 1.5016701000", \ - "0.0198545000, 0.0265440000, 0.0445580000, 0.0939065000, 0.2268102000, 0.5781900000, 1.4961917000", \ - "0.0198850000, 0.0266414000, 0.0445782000, 0.0939930000, 0.2266842000, 0.5787260000, 1.5030600000", \ - "0.0213031000, 0.0277716000, 0.0452906000, 0.0939638000, 0.2274172000, 0.5781913000, 1.4995352000", \ - "0.0260050000, 0.0320234000, 0.0482692000, 0.0954060000, 0.2265870000, 0.5785594000, 1.4974073000", \ - "0.0355012000, 0.0415126000, 0.0565397000, 0.0991997000, 0.2276749000, 0.5754356000, 1.5017211000", \ - "0.0508082000, 0.0584276000, 0.0740824000, 0.1128667000, 0.2308707000, 0.5797618000, 1.4933906000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3_2") { - leakage_power () { - value : 0.0014757000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0059674000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0007819000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0010220000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0007734000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0009721000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0007502000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0007741000; - when : "A&B&!C"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__or3"; - cell_leakage_power : 0.0015646010; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016890000, 0.0016796000, 0.0016580000, 0.0016576000, 0.0016565000, 0.0016542000, 0.0016488000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001403200, -0.001429500, -0.001490000, -0.001494700, -0.001505500, -0.001530600, -0.001588200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016490000; - } - pin ("B") { - capacitance : 0.0016220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022329000, 0.0022567000, 0.0023116000, 0.0023112000, 0.0023101000, 0.0023076000, 0.0023019000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002053500, -0.002115400, -0.002257900, -0.002259400, -0.002262800, -0.002270700, -0.002289000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017050000; - } - pin ("C") { - capacitance : 0.0013790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011140000, 0.0011127000, 0.0011096000, 0.0011125000, 0.0011193000, 0.0011349000, 0.0011710000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000752300, -0.000748800, -0.000740700, -0.000740400, -0.000739600, -0.000737900, -0.000734000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014690000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0141274000, 0.0122794000, 0.0077773000, -0.004046100, -0.040754300, -0.152565300, -0.482971900", \ - "0.0140239000, 0.0121616000, 0.0076607000, -0.004500200, -0.041120000, -0.152677500, -0.483025400", \ - "0.0138247000, 0.0119996000, 0.0074667000, -0.004434000, -0.041010600, -0.152860600, -0.483271100", \ - "0.0136393000, 0.0117978000, 0.0072965000, -0.004845900, -0.041491900, -0.153075600, -0.483390100", \ - "0.0135968000, 0.0117740000, 0.0073067000, -0.004895900, -0.041566400, -0.153251000, -0.483554000", \ - "0.0135222000, 0.0116737000, 0.0072042000, -0.005081200, -0.041773800, -0.153381000, -0.483722600", \ - "0.0162772000, 0.0144411000, 0.0092312000, -0.004620700, -0.041634800, -0.153298200, -0.483564000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0145803000, 0.0162479000, 0.0210255000, 0.0345550000, 0.0730920000, 0.1845800000, 0.5112080000", \ - "0.0145941000, 0.0162744000, 0.0210096000, 0.0345396000, 0.0730562000, 0.1848497000, 0.5110587000", \ - "0.0145581000, 0.0162304000, 0.0210389000, 0.0345085000, 0.0730726000, 0.1847123000, 0.5117796000", \ - "0.0145836000, 0.0162376000, 0.0209009000, 0.0343717000, 0.0729473000, 0.1854129000, 0.5118640000", \ - "0.0145790000, 0.0161659000, 0.0208906000, 0.0339870000, 0.0726259000, 0.1847846000, 0.5135678000", \ - "0.0151314000, 0.0166532000, 0.0211926000, 0.0344794000, 0.0725919000, 0.1841775000, 0.5116183000", \ - "0.0159331000, 0.0174193000, 0.0217740000, 0.0349804000, 0.0730518000, 0.1854647000, 0.5101430000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0129791000, 0.0111188000, 0.0066115000, -0.005179400, -0.041883000, -0.153628900, -0.483836800", \ - "0.0128257000, 0.0109756000, 0.0064629000, -0.005662400, -0.042086300, -0.153791000, -0.484100600", \ - "0.0128723000, 0.0110306000, 0.0064774000, -0.005681400, -0.042330600, -0.154020000, -0.484301700", \ - "0.0125293000, 0.0106825000, 0.0061150000, -0.006031500, -0.042685000, -0.154170200, -0.484494700", \ - "0.0123948000, 0.0106299000, 0.0060846000, -0.006030800, -0.042716000, -0.154329900, -0.484588000", \ - "0.0125137000, 0.0106959000, 0.0061474000, -0.006047100, -0.042782700, -0.154429900, -0.484736100", \ - "0.0150596000, 0.0130558000, 0.0077787000, -0.005922300, -0.042690900, -0.154338800, -0.484572400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0141981000, 0.0158571000, 0.0206714000, 0.0343615000, 0.0731739000, 0.1852347000, 0.5121401000", \ - "0.0142488000, 0.0158948000, 0.0207326000, 0.0344457000, 0.0732386000, 0.1854989000, 0.5124447000", \ - "0.0143184000, 0.0160124000, 0.0208713000, 0.0344407000, 0.0733320000, 0.1862805000, 0.5139192000", \ - "0.0143564000, 0.0160113000, 0.0206842000, 0.0342986000, 0.0731158000, 0.1855191000, 0.5143568000", \ - "0.0142398000, 0.0158254000, 0.0205586000, 0.0337965000, 0.0726644000, 0.1858920000, 0.5112064000", \ - "0.0147837000, 0.0163125000, 0.0208803000, 0.0340973000, 0.0725768000, 0.1841228000, 0.5118732000", \ - "0.0154862000, 0.0169636000, 0.0213726000, 0.0346878000, 0.0730800000, 0.1852886000, 0.5123562000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0124326000, 0.0105889000, 0.0060895000, -0.006052600, -0.042721900, -0.154244300, -0.484454000", \ - "0.0122526000, 0.0104001000, 0.0059056000, -0.006228900, -0.042799700, -0.154332800, -0.484647900", \ - "0.0121246000, 0.0102779000, 0.0057781000, -0.006375100, -0.042970500, -0.154511400, -0.484696700", \ - "0.0119744000, 0.0101414000, 0.0056128000, -0.006345200, -0.043184900, -0.154660100, -0.484947900", \ - "0.0119405000, 0.0100870000, 0.0055561000, -0.006596800, -0.043229200, -0.154765700, -0.484964700", \ - "0.0119897000, 0.0101592000, 0.0055785000, -0.006644800, -0.042729500, -0.154592900, -0.484911200", \ - "0.0156529000, 0.0136152000, 0.0082467000, -0.005659200, -0.042272900, -0.154136400, -0.484479500"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0128951000, 0.0145930000, 0.0194333000, 0.0329845000, 0.0719167000, 0.1850652000, 0.5111977000", \ - "0.0129363000, 0.0146063000, 0.0194619000, 0.0330825000, 0.0718961000, 0.1842670000, 0.5118997000", \ - "0.0128603000, 0.0145758000, 0.0194219000, 0.0330128000, 0.0718576000, 0.1841502000, 0.5114892000", \ - "0.0128122000, 0.0144668000, 0.0192147000, 0.0327251000, 0.0716220000, 0.1842032000, 0.5111292000", \ - "0.0129090000, 0.0145130000, 0.0192121000, 0.0323805000, 0.0711950000, 0.1838613000, 0.5091281000", \ - "0.0133015000, 0.0148221000, 0.0193857000, 0.0327631000, 0.0709154000, 0.1829913000, 0.5109760000", \ - "0.0139791000, 0.0154528000, 0.0197924000, 0.0332008000, 0.0718993000, 0.1839150000, 0.5087442000"); - } - } - max_capacitance : 0.3103740000; - max_transition : 1.5030850000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.4338500000, 0.4440800000, 0.4668097000, 0.5129485000, 0.5971893000, 0.7571855000, 1.1134760000", \ - "0.4362706000, 0.4467247000, 0.4697739000, 0.5155292000, 0.6003231000, 0.7600038000, 1.1160312000", \ - "0.4448948000, 0.4550838000, 0.4777498000, 0.5240904000, 0.6082255000, 0.7680812000, 1.1244663000", \ - "0.4675890000, 0.4776453000, 0.5009065000, 0.5465884000, 0.6313264000, 0.7909713000, 1.1471349000", \ - "0.5206684000, 0.5307585000, 0.5540383000, 0.5997752000, 0.6848679000, 0.8451389000, 1.2002020000", \ - "0.6395820000, 0.6500117000, 0.6728418000, 0.7186529000, 0.8032363000, 0.9640256000, 1.3198895000", \ - "0.8723260000, 0.8832674000, 0.9084193000, 0.9580376000, 1.0474487000, 1.2151629000, 1.5747327000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0763405000, 0.0815661000, 0.0940751000, 0.1242471000, 0.2051349000, 0.4373881000, 1.1173720000", \ - "0.0811601000, 0.0863599000, 0.0987878000, 0.1289155000, 0.2097969000, 0.4428415000, 1.1184886000", \ - "0.0924390000, 0.0976108000, 0.1101324000, 0.1402376000, 0.2211609000, 0.4536450000, 1.1307780000", \ - "0.1192234000, 0.1243327000, 0.1365258000, 0.1664884000, 0.2473967000, 0.4801569000, 1.1573575000", \ - "0.1638177000, 0.1697701000, 0.1832194000, 0.2139872000, 0.2951573000, 0.5274581000, 1.2073251000", \ - "0.2182672000, 0.2260601000, 0.2429404000, 0.2764824000, 0.3580700000, 0.5898040000, 1.2675413000", \ - "0.2656038000, 0.2761460000, 0.2985098000, 0.3398533000, 0.4247917000, 0.6559116000, 1.3322983000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0634663000, 0.0693407000, 0.0830443000, 0.1130323000, 0.1734377000, 0.3172773000, 0.7237825000", \ - "0.0637532000, 0.0696150000, 0.0833257000, 0.1121799000, 0.1722625000, 0.3168882000, 0.7246174000", \ - "0.0634328000, 0.0693424000, 0.0831055000, 0.1118802000, 0.1729352000, 0.3172978000, 0.7241726000", \ - "0.0640098000, 0.0695084000, 0.0831848000, 0.1121738000, 0.1724775000, 0.3171501000, 0.7252620000", \ - "0.0636012000, 0.0696678000, 0.0840516000, 0.1121376000, 0.1732731000, 0.3163904000, 0.7251028000", \ - "0.0636277000, 0.0693823000, 0.0840139000, 0.1138755000, 0.1737460000, 0.3165549000, 0.7239904000", \ - "0.0745949000, 0.0808427000, 0.0948197000, 0.1246323000, 0.1870524000, 0.3250676000, 0.7295662000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0192681000, 0.0237068000, 0.0362664000, 0.0732666000, 0.1859149000, 0.5199137000, 1.4975182000", \ - "0.0191838000, 0.0236620000, 0.0363343000, 0.0732764000, 0.1858123000, 0.5198857000, 1.4970873000", \ - "0.0190741000, 0.0237051000, 0.0362907000, 0.0733656000, 0.1858943000, 0.5191919000, 1.4957059000", \ - "0.0192654000, 0.0237146000, 0.0363350000, 0.0732843000, 0.1859714000, 0.5195288000, 1.4989924000", \ - "0.0242424000, 0.0284343000, 0.0400966000, 0.0755914000, 0.1859551000, 0.5207368000, 1.4993593000", \ - "0.0335223000, 0.0382086000, 0.0495349000, 0.0812925000, 0.1881427000, 0.5200323000, 1.4987745000", \ - "0.0475559000, 0.0541786000, 0.0674049000, 0.0986842000, 0.1944216000, 0.5222660000, 1.4957596000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.4090983000, 0.4193191000, 0.4420065000, 0.4882091000, 0.5725741000, 0.7323522000, 1.0888036000", \ - "0.4115124000, 0.4217091000, 0.4448657000, 0.4907403000, 0.5748377000, 0.7348678000, 1.0912728000", \ - "0.4202559000, 0.4302235000, 0.4534087000, 0.4992692000, 0.5840491000, 0.7432603000, 1.0997312000", \ - "0.4433934000, 0.4535828000, 0.4765933000, 0.5222506000, 0.6069100000, 0.7665779000, 1.1228005000", \ - "0.5008801000, 0.5109448000, 0.5341758000, 0.5799455000, 0.6647854000, 0.8253843000, 1.1804440000", \ - "0.6384618000, 0.6486132000, 0.6716407000, 0.7175860000, 0.8020528000, 0.9626545000, 1.3186505000", \ - "0.9126652000, 0.9237964000, 0.9488778000, 0.9987088000, 1.0891538000, 1.2561588000, 1.6150387000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0745364000, 0.0796014000, 0.0919984000, 0.1221629000, 0.2029134000, 0.4356668000, 1.1137002000", \ - "0.0793118000, 0.0843860000, 0.0967995000, 0.1269858000, 0.2078584000, 0.4408462000, 1.1177123000", \ - "0.0906438000, 0.0957454000, 0.1081482000, 0.1382160000, 0.2194471000, 0.4526409000, 1.1287046000", \ - "0.1167041000, 0.1217933000, 0.1339876000, 0.1639426000, 0.2450779000, 0.4776856000, 1.1574157000", \ - "0.1599827000, 0.1658797000, 0.1794178000, 0.2101599000, 0.2910570000, 0.5244049000, 1.2002407000", \ - "0.2113380000, 0.2190559000, 0.2361739000, 0.2698024000, 0.3515245000, 0.5840146000, 1.2621449000", \ - "0.2538334000, 0.2643794000, 0.2870186000, 0.3293119000, 0.4141368000, 0.6468841000, 1.3224352000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0634491000, 0.0693312000, 0.0830561000, 0.1124136000, 0.1742561000, 0.3173440000, 0.7241544000", \ - "0.0635088000, 0.0693583000, 0.0832117000, 0.1120277000, 0.1732642000, 0.3170862000, 0.7239777000", \ - "0.0635006000, 0.0695322000, 0.0832524000, 0.1120677000, 0.1728412000, 0.3173074000, 0.7251638000", \ - "0.0636898000, 0.0695574000, 0.0838287000, 0.1121722000, 0.1734527000, 0.3170087000, 0.7258436000", \ - "0.0633821000, 0.0696031000, 0.0831506000, 0.1121144000, 0.1736367000, 0.3160402000, 0.7249623000", \ - "0.0638095000, 0.0697314000, 0.0838431000, 0.1134089000, 0.1728177000, 0.3164120000, 0.7238716000", \ - "0.0774862000, 0.0831187000, 0.0982643000, 0.1277973000, 0.1864192000, 0.3256587000, 0.7273022000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0184879000, 0.0230851000, 0.0355800000, 0.0725281000, 0.1856715000, 0.5201696000, 1.4991134000", \ - "0.0185033000, 0.0230866000, 0.0355403000, 0.0724954000, 0.1856815000, 0.5207400000, 1.4971010000", \ - "0.0185373000, 0.0229828000, 0.0354620000, 0.0724861000, 0.1858363000, 0.5212867000, 1.4948439000", \ - "0.0189496000, 0.0233496000, 0.0358454000, 0.0726257000, 0.1853382000, 0.5207113000, 1.5001992000", \ - "0.0239827000, 0.0281632000, 0.0397590000, 0.0749255000, 0.1859729000, 0.5210815000, 1.4964502000", \ - "0.0339356000, 0.0383283000, 0.0498651000, 0.0816595000, 0.1875547000, 0.5184812000, 1.4987792000", \ - "0.0481227000, 0.0546157000, 0.0685532000, 0.1000771000, 0.1945506000, 0.5223504000, 1.4959226000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.3729392000, 0.3831500000, 0.4061339000, 0.4521973000, 0.5365873000, 0.6966708000, 1.0525814000", \ - "0.3747145000, 0.3848792000, 0.4080516000, 0.4539053000, 0.5386348000, 0.6980396000, 1.0544313000", \ - "0.3817555000, 0.3920453000, 0.4151597000, 0.4607846000, 0.5450282000, 0.7051538000, 1.0610888000", \ - "0.4038710000, 0.4140744000, 0.4371007000, 0.4828588000, 0.5673448000, 0.7272446000, 1.0835661000", \ - "0.4646518000, 0.4747898000, 0.4975503000, 0.5435041000, 0.6278532000, 0.7885907000, 1.1444655000", \ - "0.6095776000, 0.6199046000, 0.6428609000, 0.6884937000, 0.7731537000, 0.9336927000, 1.2899519000", \ - "0.9041269000, 0.9157195000, 0.9417834000, 0.9930986000, 1.0834911000, 1.2493798000, 1.6086860000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0716166000, 0.0768270000, 0.0893241000, 0.1195502000, 0.2003550000, 0.4329636000, 1.1101441000", \ - "0.0766601000, 0.0818125000, 0.0943766000, 0.1246535000, 0.2057009000, 0.4384824000, 1.1184886000", \ - "0.0881254000, 0.0932831000, 0.1058096000, 0.1360308000, 0.2171426000, 0.4509147000, 1.1265197000", \ - "0.1147676000, 0.1199003000, 0.1324141000, 0.1624900000, 0.2433578000, 0.4770036000, 1.1528677000", \ - "0.1573822000, 0.1635157000, 0.1772723000, 0.2082769000, 0.2896358000, 0.5231384000, 1.2047224000", \ - "0.2093147000, 0.2174146000, 0.2350002000, 0.2693548000, 0.3511565000, 0.5828877000, 1.2642215000", \ - "0.2555272000, 0.2664670000, 0.2898141000, 0.3334195000, 0.4198200000, 0.6507216000, 1.3267726000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0636120000, 0.0695361000, 0.0836613000, 0.1135145000, 0.1721807000, 0.3165138000, 0.7243420000", \ - "0.0635272000, 0.0694369000, 0.0832174000, 0.1120604000, 0.1731415000, 0.3172750000, 0.7246944000", \ - "0.0640136000, 0.0696721000, 0.0834284000, 0.1121368000, 0.1722224000, 0.3167666000, 0.7251256000", \ - "0.0633549000, 0.0693475000, 0.0837022000, 0.1118474000, 0.1739304000, 0.3169522000, 0.7257739000", \ - "0.0637072000, 0.0691746000, 0.0842223000, 0.1124010000, 0.1733272000, 0.3161029000, 0.7248944000", \ - "0.0636148000, 0.0695293000, 0.0831160000, 0.1135986000, 0.1732485000, 0.3166115000, 0.7237190000", \ - "0.0841603000, 0.0904797000, 0.1049007000, 0.1330133000, 0.1903753000, 0.3269512000, 0.7286899000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0186741000, 0.0232175000, 0.0357851000, 0.0726500000, 0.1856457000, 0.5227388000, 1.4995972000", \ - "0.0186683000, 0.0232807000, 0.0358332000, 0.0727553000, 0.1854096000, 0.5210087000, 1.5030854000", \ - "0.0187535000, 0.0232212000, 0.0357029000, 0.0727490000, 0.1853128000, 0.5226951000, 1.5010100000", \ - "0.0192899000, 0.0238394000, 0.0362426000, 0.0728867000, 0.1856645000, 0.5219097000, 1.4978941000", \ - "0.0246315000, 0.0292392000, 0.0405763000, 0.0754933000, 0.1859595000, 0.5214104000, 1.4991182000", \ - "0.0348934000, 0.0396640000, 0.0515502000, 0.0826274000, 0.1880539000, 0.5187359000, 1.4980710000", \ - "0.0503051000, 0.0568373000, 0.0712409000, 0.1035887000, 0.1955479000, 0.5231901000, 1.4961589000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3_4") { - leakage_power () { - value : 0.0040967000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0046321000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0020287000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0024994000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0020171000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0023608000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0019971000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0020186000; - when : "A&B&!C"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__or3"; - cell_leakage_power : 0.0027063310; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0038554000, 0.0038459000, 0.0038240000, 0.0038266000, 0.0038327000, 0.0038468000, 0.0038794000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003301300, -0.003331300, -0.003400400, -0.003415100, -0.003448900, -0.003526800, -0.003706600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025440000; - } - pin ("B") { - capacitance : 0.0023510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0037651000, 0.0037661000, 0.0037684000, 0.0037708000, 0.0037762000, 0.0037887000, 0.0038176000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003286600, -0.003375600, -0.003580800, -0.003587200, -0.003601900, -0.003635700, -0.003713800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025090000; - } - pin ("C") { - capacitance : 0.0023010000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0021110000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025669000, 0.0025655000, 0.0025623000, 0.0025698000, 0.0025871000, 0.0026271000, 0.0027193000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001724100, -0.001719200, -0.001708100, -0.001710800, -0.001717100, -0.001731500, -0.001764900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024920000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0255141000, 0.0235106000, 0.0176216000, 0.0013860000, -0.052050500, -0.233636200, -0.824800700", \ - "0.0254915000, 0.0234275000, 0.0175912000, 0.0013077000, -0.052137200, -0.233708400, -0.824958600", \ - "0.0251932000, 0.0235843000, 0.0172059000, 0.0008973000, -0.052526200, -0.233978500, -0.825138000", \ - "0.0249575000, 0.0228715000, 0.0170033000, 0.0007651000, -0.052754600, -0.234274100, -0.825371000", \ - "0.0247337000, 0.0226569000, 0.0168143000, 0.0007278000, -0.052906300, -0.234418400, -0.825450900", \ - "0.0247041000, 0.0226766000, 0.0168149000, 0.0006638000, -0.053054200, -0.234611300, -0.825642900", \ - "0.0317538000, 0.0295077000, 0.0230163000, 0.0040802000, -0.053828400, -0.234674400, -0.825591500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0299347000, 0.0319496000, 0.0379576000, 0.0567263000, 0.1149203000, 0.2987714000, 0.8830631000", \ - "0.0299204000, 0.0318373000, 0.0378169000, 0.0566522000, 0.1149092000, 0.2982869000, 0.8873712000", \ - "0.0297922000, 0.0316950000, 0.0377833000, 0.0565876000, 0.1148425000, 0.2982241000, 0.8840089000", \ - "0.0299190000, 0.0318942000, 0.0378799000, 0.0565631000, 0.1147243000, 0.2980506000, 0.8834338000", \ - "0.0298831000, 0.0317320000, 0.0376445000, 0.0561016000, 0.1137406000, 0.2978539000, 0.8871875000", \ - "0.0311214000, 0.0329043000, 0.0385587000, 0.0568393000, 0.1137600000, 0.2970050000, 0.8836660000", \ - "0.0326205000, 0.0342938000, 0.0398850000, 0.0578694000, 0.1148949000, 0.2985944000, 0.8820063000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0232521000, 0.0211033000, 0.0152832000, -0.000531500, -0.054069900, -0.235814800, -0.826810800", \ - "0.0230542000, 0.0209961000, 0.0151498000, -0.000677200, -0.054170000, -0.235945500, -0.826952200", \ - "0.0228477000, 0.0208783000, 0.0149655000, -0.001270800, -0.054693600, -0.236194800, -0.827243900", \ - "0.0226742000, 0.0205921000, 0.0147287000, -0.001587000, -0.054755700, -0.236406200, -0.827317200", \ - "0.0225760000, 0.0205138000, 0.0146485000, -0.001613800, -0.055145900, -0.236637500, -0.827515100", \ - "0.0226005000, 0.0205096000, 0.0146025000, -0.001741400, -0.055311000, -0.236830200, -0.827757500", \ - "0.0294169000, 0.0272438000, 0.0205255000, 0.0014032000, -0.055912000, -0.235835700, -0.827042600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0290379000, 0.0309777000, 0.0369958000, 0.0559287000, 0.1146797000, 0.2986661000, 0.8850506000", \ - "0.0290749000, 0.0310054000, 0.0369980000, 0.0560052000, 0.1147260000, 0.2991859000, 0.8883061000", \ - "0.0291216000, 0.0310460000, 0.0371236000, 0.0561110000, 0.1147119000, 0.2992451000, 0.8884353000", \ - "0.0290397000, 0.0310235000, 0.0370383000, 0.0558330000, 0.1143924000, 0.2989365000, 0.8881638000", \ - "0.0289711000, 0.0308378000, 0.0366287000, 0.0550456000, 0.1134956000, 0.2978762000, 0.8845201000", \ - "0.0297850000, 0.0315699000, 0.0371783000, 0.0554714000, 0.1129293000, 0.2966984000, 0.8827160000", \ - "0.0313511000, 0.0330393000, 0.0385785000, 0.0564306000, 0.1143053000, 0.2982789000, 0.8805977000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0222697000, 0.0202153000, 0.0144059000, -0.001967800, -0.055211900, -0.236593500, -0.827641000", \ - "0.0221959000, 0.0200996000, 0.0142032000, -0.001817500, -0.055258300, -0.236817800, -0.827724000", \ - "0.0220395000, 0.0199494000, 0.0140801000, -0.002204900, -0.055688800, -0.237121100, -0.828055200", \ - "0.0217318000, 0.0197499000, 0.0139547000, -0.002216300, -0.055810800, -0.237287200, -0.828232100", \ - "0.0215261000, 0.0194354000, 0.0135845000, -0.002592700, -0.056190800, -0.237453600, -0.828286500", \ - "0.0220775000, 0.0199806000, 0.0140027000, -0.001444300, -0.055399300, -0.237362400, -0.828300200", \ - "0.0321245000, 0.0298909000, 0.0230514000, 0.0034339000, -0.054364100, -0.235821900, -0.826997700"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015975370, 0.0051042490, 0.0163084500, 0.0521067100, 0.1664848000, 0.5319312000"); - values("0.0257994000, 0.0277347000, 0.0338848000, 0.0527346000, 0.1115687000, 0.2958618000, 0.8824956000", \ - "0.0257490000, 0.0277040000, 0.0338206000, 0.0527317000, 0.1115235000, 0.2945015000, 0.8820683000", \ - "0.0256538000, 0.0276162000, 0.0337165000, 0.0527662000, 0.1114048000, 0.2957524000, 0.8777199000", \ - "0.0256158000, 0.0275224000, 0.0336305000, 0.0524429000, 0.1109451000, 0.2953697000, 0.8823388000", \ - "0.0256737000, 0.0275188000, 0.0334146000, 0.0516441000, 0.1099686000, 0.2945569000, 0.8825168000", \ - "0.0265424000, 0.0284621000, 0.0341784000, 0.0524853000, 0.1094272000, 0.2933500000, 0.8802382000", \ - "0.0279431000, 0.0295961000, 0.0351437000, 0.0531570000, 0.1115391000, 0.2941553000, 0.8817169000"); - } - } - max_capacitance : 0.5319310000; - max_transition : 1.5070720000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.3459759000, 0.3519301000, 0.3672774000, 0.4013956000, 0.4689475000, 0.6050974000, 0.9332050000", \ - "0.3504629000, 0.3564133000, 0.3716655000, 0.4059412000, 0.4735529000, 0.6093772000, 0.9376722000", \ - "0.3619217000, 0.3678751000, 0.3831757000, 0.4172194000, 0.4849762000, 0.6210951000, 0.9491448000", \ - "0.3879018000, 0.3937147000, 0.4091606000, 0.4431471000, 0.5108351000, 0.6470487000, 0.9751912000", \ - "0.4450830000, 0.4508968000, 0.4662083000, 0.5000853000, 0.5674502000, 0.7041038000, 1.0321195000", \ - "0.5702332000, 0.5761056000, 0.5914033000, 0.6252407000, 0.6928736000, 0.8297968000, 1.1573101000", \ - "0.8066398000, 0.8132645000, 0.8303217000, 0.8678373000, 0.9427552000, 1.0862934000, 1.4184540000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0842214000, 0.0878244000, 0.0975802000, 0.1230933000, 0.1953703000, 0.4192494000, 1.1307968000", \ - "0.0887973000, 0.0924025000, 0.1020998000, 0.1276477000, 0.1998561000, 0.4244325000, 1.1389891000", \ - "0.0998479000, 0.1034357000, 0.1132139000, 0.1387216000, 0.2108926000, 0.4350826000, 1.1503253000", \ - "0.1258950000, 0.1294419000, 0.1391071000, 0.1643502000, 0.2362366000, 0.4609243000, 1.1757864000", \ - "0.1727291000, 0.1767696000, 0.1872393000, 0.2132203000, 0.2853855000, 0.5088492000, 1.2232134000", \ - "0.2290893000, 0.2343430000, 0.2472672000, 0.2764051000, 0.3492003000, 0.5730623000, 1.2861322000", \ - "0.2759523000, 0.2829448000, 0.3004853000, 0.3374520000, 0.4146551000, 0.6374002000, 1.3480580000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0554249000, 0.0586787000, 0.0673611000, 0.0880915000, 0.1366495000, 0.2580715000, 0.6385142000", \ - "0.0553418000, 0.0582554000, 0.0673455000, 0.0885551000, 0.1349636000, 0.2581423000, 0.6372824000", \ - "0.0553636000, 0.0583989000, 0.0674031000, 0.0889105000, 0.1355402000, 0.2581226000, 0.6383712000", \ - "0.0553997000, 0.0583414000, 0.0670513000, 0.0877747000, 0.1362831000, 0.2580008000, 0.6382292000", \ - "0.0551651000, 0.0583483000, 0.0673033000, 0.0882174000, 0.1357026000, 0.2577308000, 0.6389781000", \ - "0.0570047000, 0.0598744000, 0.0681769000, 0.0890612000, 0.1358157000, 0.2583084000, 0.6387924000", \ - "0.0686798000, 0.0717879000, 0.0811113000, 0.1023196000, 0.1512418000, 0.2724840000, 0.6445931000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0204332000, 0.0234761000, 0.0327853000, 0.0621686000, 0.1601252000, 0.4796596000, 1.4985264000", \ - "0.0203640000, 0.0234207000, 0.0328129000, 0.0621878000, 0.1602102000, 0.4792802000, 1.5011704000", \ - "0.0204560000, 0.0234420000, 0.0327490000, 0.0621000000, 0.1601910000, 0.4783828000, 1.5010418000", \ - "0.0203585000, 0.0233621000, 0.0326725000, 0.0619858000, 0.1601535000, 0.4793868000, 1.4991167000", \ - "0.0250410000, 0.0278217000, 0.0364804000, 0.0641209000, 0.1605244000, 0.4791870000, 1.5020035000", \ - "0.0346662000, 0.0377596000, 0.0459025000, 0.0715005000, 0.1629469000, 0.4789252000, 1.5017667000", \ - "0.0494961000, 0.0536105000, 0.0643422000, 0.0886908000, 0.1709363000, 0.4820537000, 1.4983637000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.3289307000, 0.3347550000, 0.3501545000, 0.3840742000, 0.4517262000, 0.5878463000, 0.9158468000", \ - "0.3325248000, 0.3383526000, 0.3537816000, 0.3877642000, 0.4554525000, 0.5915065000, 0.9195666000", \ - "0.3429934000, 0.3489844000, 0.3642702000, 0.3983222000, 0.4659464000, 0.6021949000, 0.9303607000", \ - "0.3684825000, 0.3742925000, 0.3896261000, 0.4237173000, 0.4913384000, 0.6280371000, 0.9554376000", \ - "0.4292613000, 0.4351625000, 0.4504693000, 0.4845531000, 0.5517768000, 0.6884379000, 1.0168567000", \ - "0.5692631000, 0.5751594000, 0.5906133000, 0.6247841000, 0.6926189000, 0.8294604000, 1.1569316000", \ - "0.8361279000, 0.8427015000, 0.8600776000, 0.8987137000, 0.9737414000, 1.1182566000, 1.4503452000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0839679000, 0.0875375000, 0.0972925000, 0.1229211000, 0.1954485000, 0.4196942000, 1.1327953000", \ - "0.0885846000, 0.0921888000, 0.1019298000, 0.1276231000, 0.2000398000, 0.4243317000, 1.1372094000", \ - "0.0995256000, 0.1031338000, 0.1129555000, 0.1386163000, 0.2109576000, 0.4352364000, 1.1480996000", \ - "0.1255216000, 0.1290965000, 0.1388406000, 0.1642785000, 0.2364704000, 0.4611993000, 1.1751685000", \ - "0.1708538000, 0.1749512000, 0.1852745000, 0.2118014000, 0.2840981000, 0.5084814000, 1.2220005000", \ - "0.2249340000, 0.2302365000, 0.2434590000, 0.2730581000, 0.3463367000, 0.5706722000, 1.2838133000", \ - "0.2686359000, 0.2757412000, 0.2936942000, 0.3308283000, 0.4091496000, 0.6320571000, 1.3436704000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0553561000, 0.0583394000, 0.0672179000, 0.0881909000, 0.1359003000, 0.2580871000, 0.6390817000", \ - "0.0554173000, 0.0583171000, 0.0671624000, 0.0880688000, 0.1353739000, 0.2580486000, 0.6391747000", \ - "0.0554389000, 0.0587904000, 0.0673590000, 0.0879570000, 0.1366249000, 0.2580341000, 0.6384760000", \ - "0.0553765000, 0.0583407000, 0.0673072000, 0.0888864000, 0.1349998000, 0.2575922000, 0.6386908000", \ - "0.0552410000, 0.0584023000, 0.0673554000, 0.0882764000, 0.1367096000, 0.2576012000, 0.6377047000", \ - "0.0569508000, 0.0601268000, 0.0685765000, 0.0887852000, 0.1357136000, 0.2577085000, 0.6389919000", \ - "0.0736922000, 0.0761565000, 0.0858827000, 0.1067121000, 0.1534132000, 0.2718409000, 0.6459367000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0201870000, 0.0232659000, 0.0325774000, 0.0618147000, 0.1599399000, 0.4795678000, 1.5026096000", \ - "0.0201994000, 0.0232222000, 0.0326083000, 0.0618511000, 0.1597870000, 0.4800760000, 1.5018807000", \ - "0.0202390000, 0.0232845000, 0.0325571000, 0.0617876000, 0.1597658000, 0.4798605000, 1.5014510000", \ - "0.0203197000, 0.0233630000, 0.0325951000, 0.0618945000, 0.1597921000, 0.4800952000, 1.5036409000", \ - "0.0250800000, 0.0280257000, 0.0370800000, 0.0645286000, 0.1600262000, 0.4794346000, 1.5025242000", \ - "0.0349193000, 0.0383346000, 0.0467592000, 0.0722114000, 0.1627270000, 0.4778110000, 1.4979511000", \ - "0.0509912000, 0.0550556000, 0.0656038000, 0.0911762000, 0.1722037000, 0.4813135000, 1.4986000000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.2949677000, 0.3008004000, 0.3159917000, 0.3503244000, 0.4181522000, 0.5539835000, 0.8822564000", \ - "0.2976156000, 0.3034358000, 0.3188829000, 0.3528645000, 0.4205396000, 0.5572641000, 0.8847942000", \ - "0.3055687000, 0.3113421000, 0.3267971000, 0.3609155000, 0.4286358000, 0.5654451000, 0.8929234000", \ - "0.3286381000, 0.3344736000, 0.3499053000, 0.3839359000, 0.4516909000, 0.5884265000, 0.9155640000", \ - "0.3888136000, 0.3946206000, 0.4100035000, 0.4440982000, 0.5116114000, 0.6481958000, 0.9764881000", \ - "0.5324228000, 0.5383110000, 0.5535152000, 0.5876579000, 0.6550555000, 0.7904822000, 1.1186873000", \ - "0.7913129000, 0.7985643000, 0.8166291000, 0.8577409000, 0.9345733000, 1.0786332000, 1.4100765000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0804629000, 0.0841171000, 0.0940829000, 0.1198769000, 0.1924399000, 0.4172655000, 1.1337414000", \ - "0.0853003000, 0.0889518000, 0.0989196000, 0.1247174000, 0.1973201000, 0.4220023000, 1.1376146000", \ - "0.0967231000, 0.1003732000, 0.1103344000, 0.1362267000, 0.2087456000, 0.4339745000, 1.1453045000", \ - "0.1228214000, 0.1264381000, 0.1363085000, 0.1619038000, 0.2343577000, 0.4603581000, 1.1704490000", \ - "0.1675030000, 0.1717195000, 0.1826026000, 0.2092410000, 0.2817608000, 0.5065109000, 1.2238187000", \ - "0.2215470000, 0.2270924000, 0.2411013000, 0.2713802000, 0.3446588000, 0.5681314000, 1.2850137000", \ - "0.2690808000, 0.2764007000, 0.2951617000, 0.3337575000, 0.4140073000, 0.6378605000, 1.3474812000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0554015000, 0.0583384000, 0.0674927000, 0.0889060000, 0.1351814000, 0.2580363000, 0.6375613000", \ - "0.0554124000, 0.0583248000, 0.0671233000, 0.0892245000, 0.1348807000, 0.2575456000, 0.6391707000", \ - "0.0552789000, 0.0582638000, 0.0673539000, 0.0878847000, 0.1350002000, 0.2576948000, 0.6385562000", \ - "0.0552144000, 0.0582066000, 0.0673036000, 0.0890417000, 0.1354705000, 0.2577838000, 0.6391940000", \ - "0.0554137000, 0.0583199000, 0.0671738000, 0.0887097000, 0.1350381000, 0.2572246000, 0.6384019000", \ - "0.0575518000, 0.0605989000, 0.0687883000, 0.0894113000, 0.1375733000, 0.2593991000, 0.6384021000", \ - "0.0826437000, 0.0855698000, 0.0947989000, 0.1174094000, 0.1607158000, 0.2763350000, 0.6467580000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015975400, 0.0051042500, 0.0163085000, 0.0521067000, 0.1664850000, 0.5319310000"); - values("0.0204222000, 0.0234652000, 0.0327905000, 0.0621264000, 0.1596693000, 0.4796953000, 1.5059775000", \ - "0.0204284000, 0.0235562000, 0.0328111000, 0.0620892000, 0.1599868000, 0.4786538000, 1.5015917000", \ - "0.0204285000, 0.0234938000, 0.0328243000, 0.0620479000, 0.1599879000, 0.4806552000, 1.4971254000", \ - "0.0207910000, 0.0237940000, 0.0330911000, 0.0622801000, 0.1599425000, 0.4807758000, 1.5010900000", \ - "0.0261740000, 0.0290487000, 0.0377731000, 0.0652784000, 0.1603542000, 0.4801560000, 1.5070716000", \ - "0.0367054000, 0.0399413000, 0.0493622000, 0.0740055000, 0.1635425000, 0.4788038000, 1.5046610000", \ - "0.0535327000, 0.0581115000, 0.0687030000, 0.0944681000, 0.1736763000, 0.4813303000, 1.4973982000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3b_1") { - leakage_power () { - value : 0.0090986000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0013082000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0029788000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0005740000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0029519000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0005704000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0027120000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0005410000; - when : "A&B&!C_N"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__or3b"; - cell_leakage_power : 0.0025918680; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015730000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0018325000, 0.0018159000, 0.0017778000, 0.0017783000, 0.0017795000, 0.0017823000, 0.0017888000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001554200, -0.001574600, -0.001621700, -0.001626200, -0.001636600, -0.001660500, -0.001715500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016740000; - } - pin ("B") { - capacitance : 0.0017330000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028268000, 0.0028595000, 0.0029349000, 0.0029362000, 0.0029390000, 0.0029456000, 0.0029608000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002765700, -0.002805300, -0.002896800, -0.002898600, -0.002902900, -0.002912800, -0.002935500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018210000; - } - pin ("C_N") { - capacitance : 0.0013530000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0069829000, 0.0069074000, 0.0067331000, 0.0067962000, 0.0069417000, 0.0072770000, 0.0080498000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0005512000, 0.0004871000, 0.0003395000, 0.0003986000, 0.0005348000, 0.0008489000, 0.0015729000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0013940000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0100576000, 0.0089730000, 0.0060912000, -0.001938700, -0.025083000, -0.088632000, -0.257066900", \ - "0.0097416000, 0.0087619000, 0.0059084000, -0.002123000, -0.025261800, -0.088803100, -0.257261300", \ - "0.0095840000, 0.0084881000, 0.0057859000, -0.002244300, -0.025401600, -0.088953800, -0.257409900", \ - "0.0094244000, 0.0083407000, 0.0055362000, -0.002420900, -0.025576300, -0.089124800, -0.257566700", \ - "0.0093390000, 0.0082649000, 0.0054332000, -0.002645100, -0.025743700, -0.089236500, -0.257672800", \ - "0.0092989000, 0.0081762000, 0.0053835000, -0.002698600, -0.025827800, -0.089306000, -0.257706900", \ - "0.0123534000, 0.0109026000, 0.0072770000, -0.001987300, -0.026081500, -0.089227100, -0.257623300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0097660000, 0.0111587000, 0.0147548000, 0.0239410000, 0.0480850000, 0.1109597000, 0.2773402000", \ - "0.0097239000, 0.0111355000, 0.0147263000, 0.0239162000, 0.0478728000, 0.1115393000, 0.2772511000", \ - "0.0096946000, 0.0110988000, 0.0146965000, 0.0238958000, 0.0478593000, 0.1115404000, 0.2772259000", \ - "0.0096392000, 0.0110225000, 0.0145508000, 0.0237886000, 0.0477851000, 0.1114636000, 0.2772873000", \ - "0.0096620000, 0.0109500000, 0.0144088000, 0.0235874000, 0.0476748000, 0.1107385000, 0.2783598000", \ - "0.0097997000, 0.0111005000, 0.0145890000, 0.0236662000, 0.0477898000, 0.1104330000, 0.2785542000", \ - "0.0105596000, 0.0118798000, 0.0153092000, 0.0244704000, 0.0481426000, 0.1118700000, 0.2781656000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0087413000, 0.0076096000, 0.0047475000, -0.003330100, -0.026501400, -0.089902900, -0.258265500", \ - "0.0083791000, 0.0072704000, 0.0046082000, -0.003447900, -0.026603200, -0.090065400, -0.258441100", \ - "0.0081703000, 0.0071058000, 0.0042752000, -0.003756800, -0.026813000, -0.090276200, -0.258679900", \ - "0.0080407000, 0.0069465000, 0.0041442000, -0.003835000, -0.026966800, -0.090453500, -0.258825700", \ - "0.0079539000, 0.0068569000, 0.0040270000, -0.004031300, -0.027078100, -0.090524100, -0.258908000", \ - "0.0079474000, 0.0068124000, 0.0039681000, -0.004072800, -0.027165300, -0.090601500, -0.258944000", \ - "0.0110402000, 0.0095665000, 0.0059193000, -0.003405500, -0.027278200, -0.090197400, -0.258684900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0096553000, 0.0110923000, 0.0147633000, 0.0241036000, 0.0482821000, 0.1115302000, 0.2777328000", \ - "0.0096871000, 0.0111231000, 0.0147933000, 0.0241333000, 0.0483458000, 0.1114968000, 0.2779232000", \ - "0.0097237000, 0.0111418000, 0.0148000000, 0.0241210000, 0.0483105000, 0.1120814000, 0.2793088000", \ - "0.0095864000, 0.0109779000, 0.0145955000, 0.0239212000, 0.0483534000, 0.1118791000, 0.2793151000", \ - "0.0096312000, 0.0109402000, 0.0144522000, 0.0235877000, 0.0478473000, 0.1112604000, 0.2777492000", \ - "0.0097705000, 0.0111386000, 0.0146562000, 0.0236713000, 0.0479104000, 0.1113941000, 0.2774449000", \ - "0.0103249000, 0.0116200000, 0.0150844000, 0.0242670000, 0.0483503000, 0.1118681000, 0.2771981000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0084427000, 0.0073593000, 0.0045302000, -0.003490800, -0.026569800, -0.089900700, -0.258274600", \ - "0.0083806000, 0.0073029000, 0.0044602000, -0.003545300, -0.026614000, -0.089952600, -0.258303300", \ - "0.0083287000, 0.0072617000, 0.0044384000, -0.003521800, -0.026647600, -0.090040600, -0.258404400", \ - "0.0080974000, 0.0070007000, 0.0041790000, -0.003860800, -0.026943700, -0.090357100, -0.258696700", \ - "0.0077844000, 0.0066802000, 0.0038951000, -0.004129100, -0.027208800, -0.090574600, -0.258935000", \ - "0.0086032000, 0.0072147000, 0.0038152000, -0.004242700, -0.027278300, -0.090690600, -0.259018800", \ - "0.0114445000, 0.0100651000, 0.0065620000, -0.002585400, -0.026682000, -0.090504900, -0.258848700"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0095563000, 0.0109888000, 0.0146701000, 0.0240212000, 0.0481639000, 0.1120518000, 0.2783782000", \ - "0.0095232000, 0.0109636000, 0.0145950000, 0.0239230000, 0.0480760000, 0.1119659000, 0.2766899000", \ - "0.0095481000, 0.0109754000, 0.0146247000, 0.0239657000, 0.0481499000, 0.1120147000, 0.2783835000", \ - "0.0094300000, 0.0108711000, 0.0145012000, 0.0238350000, 0.0479768000, 0.1118146000, 0.2781694000", \ - "0.0092445000, 0.0106782000, 0.0142972000, 0.0236090000, 0.0477956000, 0.1112273000, 0.2777822000", \ - "0.0090661000, 0.0104572000, 0.0139975000, 0.0234197000, 0.0476233000, 0.1107460000, 0.2792615000", \ - "0.0092073000, 0.0105763000, 0.0141573000, 0.0233775000, 0.0474458000, 0.1114165000, 0.2780812000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5027860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3305424000, 0.3419813000, 0.3654609000, 0.4093217000, 0.4892520000, 0.6447866000, 1.0000789000", \ - "0.3318817000, 0.3434490000, 0.3669739000, 0.4108993000, 0.4907295000, 0.6462906000, 1.0016041000", \ - "0.3401537000, 0.3515735000, 0.3748814000, 0.4186122000, 0.4987026000, 0.6544583000, 1.0097693000", \ - "0.3634895000, 0.3747739000, 0.3983518000, 0.4419078000, 0.5218656000, 0.6775749000, 1.0329076000", \ - "0.4164326000, 0.4278974000, 0.4513467000, 0.4948538000, 0.5746801000, 0.7310642000, 1.0862773000", \ - "0.5298516000, 0.5416027000, 0.5652294000, 0.6092166000, 0.6897398000, 0.8464147000, 1.2016618000", \ - "0.7312957000, 0.7442102000, 0.7710498000, 0.8200256000, 0.9079016000, 1.0716805000, 1.4318764000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0651026000, 0.0714384000, 0.0863634000, 0.1223128000, 0.2155968000, 0.4593619000, 1.1012183000", \ - "0.0698468000, 0.0762740000, 0.0911232000, 0.1272152000, 0.2204005000, 0.4643833000, 1.1052291000", \ - "0.0813008000, 0.0876599000, 0.1025053000, 0.1386161000, 0.2318758000, 0.4758322000, 1.1165999000", \ - "0.1068812000, 0.1132754000, 0.1280931000, 0.1640376000, 0.2574037000, 0.5014758000, 1.1433181000", \ - "0.1442567000, 0.1513683000, 0.1668888000, 0.2031560000, 0.2962066000, 0.5411394000, 1.1851726000", \ - "0.1872879000, 0.1957812000, 0.2139156000, 0.2517490000, 0.3447105000, 0.5884182000, 1.2324922000", \ - "0.2170282000, 0.2291036000, 0.2524860000, 0.2953550000, 0.3876235000, 0.6324362000, 1.2730095000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0484987000, 0.0561232000, 0.0714613000, 0.1039525000, 0.1713615000, 0.3309080000, 0.7696087000", \ - "0.0489230000, 0.0560278000, 0.0714934000, 0.1038773000, 0.1713692000, 0.3307306000, 0.7699508000", \ - "0.0487553000, 0.0565470000, 0.0718669000, 0.1028186000, 0.1697737000, 0.3310216000, 0.7698535000", \ - "0.0486951000, 0.0566190000, 0.0723495000, 0.1042016000, 0.1698316000, 0.3305712000, 0.7700182000", \ - "0.0486532000, 0.0566718000, 0.0723792000, 0.1032537000, 0.1705221000, 0.3311325000, 0.7702685000", \ - "0.0519377000, 0.0587969000, 0.0743895000, 0.1068512000, 0.1727946000, 0.3319628000, 0.7727883000", \ - "0.0606087000, 0.0695004000, 0.0865040000, 0.1189534000, 0.1880310000, 0.3446312000, 0.7780057000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0207146000, 0.0275521000, 0.0455080000, 0.0947113000, 0.2266335000, 0.5737969000, 1.4954398000", \ - "0.0207136000, 0.0275323000, 0.0455084000, 0.0946994000, 0.2262611000, 0.5746721000, 1.4935203000", \ - "0.0206004000, 0.0273641000, 0.0454594000, 0.0944515000, 0.2263304000, 0.5747925000, 1.4928534000", \ - "0.0213295000, 0.0279258000, 0.0456772000, 0.0945519000, 0.2261682000, 0.5756470000, 1.4923645000", \ - "0.0255262000, 0.0316636000, 0.0483357000, 0.0957027000, 0.2265777000, 0.5751903000, 1.4953503000", \ - "0.0337029000, 0.0403375000, 0.0552204000, 0.0987726000, 0.2279701000, 0.5748091000, 1.4957807000", \ - "0.0474074000, 0.0547745000, 0.0702050000, 0.1088637000, 0.2299608000, 0.5772880000, 1.4927564000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3068071000, 0.3182184000, 0.3416013000, 0.3853776000, 0.4654677000, 0.6211771000, 0.9766152000", \ - "0.3083168000, 0.3197729000, 0.3430881000, 0.3868379000, 0.4670097000, 0.6228800000, 0.9782967000", \ - "0.3165871000, 0.3280796000, 0.3514080000, 0.3952030000, 0.4747533000, 0.6311592000, 0.9863876000", \ - "0.3400761000, 0.3512468000, 0.3748999000, 0.4185970000, 0.4984330000, 0.6545105000, 1.0099293000", \ - "0.3978824000, 0.4093919000, 0.4326948000, 0.4762464000, 0.5562934000, 0.7128355000, 1.0681283000", \ - "0.5293033000, 0.5411216000, 0.5649699000, 0.6094302000, 0.6894256000, 0.8461698000, 1.2016711000", \ - "0.7665830000, 0.7798816000, 0.8076818000, 0.8578067000, 0.9463992000, 1.1096124000, 1.4687648000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0636142000, 0.0699817000, 0.0849876000, 0.1214513000, 0.2147446000, 0.4589128000, 1.1013233000", \ - "0.0684252000, 0.0748159000, 0.0897987000, 0.1262516000, 0.2195256000, 0.4637773000, 1.1064081000", \ - "0.0799588000, 0.0863123000, 0.1011607000, 0.1375546000, 0.2309031000, 0.4757210000, 1.1196318000", \ - "0.1042556000, 0.1106709000, 0.1255607000, 0.1618446000, 0.2556433000, 0.5008243000, 1.1420123000", \ - "0.1391538000, 0.1461767000, 0.1619013000, 0.1984136000, 0.2918418000, 0.5366855000, 1.1795801000", \ - "0.1778103000, 0.1871174000, 0.2049858000, 0.2424975000, 0.3358505000, 0.5803138000, 1.2229012000", \ - "0.1997005000, 0.2118849000, 0.2360707000, 0.2793445000, 0.3728226000, 0.6178595000, 1.2592969000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0486621000, 0.0561085000, 0.0717510000, 0.1042583000, 0.1713085000, 0.3306716000, 0.7697233000", \ - "0.0487708000, 0.0565623000, 0.0721809000, 0.1033679000, 0.1709231000, 0.3310202000, 0.7697737000", \ - "0.0489832000, 0.0560071000, 0.0716109000, 0.1040265000, 0.1710852000, 0.3308492000, 0.7724914000", \ - "0.0488020000, 0.0558911000, 0.0716004000, 0.1041923000, 0.1696000000, 0.3308049000, 0.7694451000", \ - "0.0487644000, 0.0563433000, 0.0717927000, 0.1033486000, 0.1698576000, 0.3309581000, 0.7692619000", \ - "0.0523187000, 0.0594947000, 0.0744455000, 0.1064287000, 0.1731204000, 0.3309446000, 0.7703247000", \ - "0.0651099000, 0.0732203000, 0.0901650000, 0.1225009000, 0.1896306000, 0.3448562000, 0.7769101000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0199971000, 0.0266860000, 0.0447384000, 0.0939822000, 0.2265618000, 0.5754011000, 1.4946797000", \ - "0.0199470000, 0.0266442000, 0.0446611000, 0.0940204000, 0.2265686000, 0.5755825000, 1.4951254000", \ - "0.0199514000, 0.0267113000, 0.0446447000, 0.0939310000, 0.2260086000, 0.5761644000, 1.4976814000", \ - "0.0209435000, 0.0274148000, 0.0451440000, 0.0940163000, 0.2267498000, 0.5746733000, 1.4948255000", \ - "0.0251231000, 0.0312570000, 0.0476500000, 0.0950848000, 0.2261006000, 0.5757991000, 1.4963538000", \ - "0.0337980000, 0.0403387000, 0.0548097000, 0.0984457000, 0.2272836000, 0.5737981000, 1.4918040000", \ - "0.0484728000, 0.0554593000, 0.0716072000, 0.1094143000, 0.2296137000, 0.5785161000, 1.4920566000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.2982002000, 0.3096548000, 0.3330279000, 0.3769172000, 0.4572802000, 0.6123964000, 0.9678289000", \ - "0.3023878000, 0.3138690000, 0.3372565000, 0.3811665000, 0.4614492000, 0.6165450000, 0.9720509000", \ - "0.3108164000, 0.3223385000, 0.3457083000, 0.3892304000, 0.4695271000, 0.6256679000, 0.9810857000", \ - "0.3260670000, 0.3375491000, 0.3609613000, 0.4049575000, 0.4848161000, 0.6405776000, 0.9960509000", \ - "0.3488172000, 0.3602714000, 0.3836957000, 0.4276546000, 0.5079239000, 0.6642689000, 1.0195388000", \ - "0.3767281000, 0.3880523000, 0.4114163000, 0.4552068000, 0.5351365000, 0.6914234000, 1.0461717000", \ - "0.4010101000, 0.4123880000, 0.4357529000, 0.4797002000, 0.5596783000, 0.7162168000, 1.0714314000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.1228046000, 0.1293107000, 0.1444559000, 0.1810644000, 0.2742474000, 0.5180461000, 1.1638608000", \ - "0.1277553000, 0.1342667000, 0.1493261000, 0.1859209000, 0.2790590000, 0.5247818000, 1.1668686000", \ - "0.1405178000, 0.1470131000, 0.1621150000, 0.1986966000, 0.2919436000, 0.5361234000, 1.1818601000", \ - "0.1712156000, 0.1777148000, 0.1927562000, 0.2293137000, 0.3225314000, 0.5689033000, 1.2117394000", \ - "0.2291518000, 0.2356730000, 0.2508366000, 0.2872868000, 0.3808273000, 0.6258450000, 1.2674670000", \ - "0.3187400000, 0.3254500000, 0.3406911000, 0.3771190000, 0.4706293000, 0.7143745000, 1.3584840000", \ - "0.4567011000, 0.4639109000, 0.4796962000, 0.5160563000, 0.6096273000, 0.8547134000, 1.4954723000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0487074000, 0.0561095000, 0.0716134000, 0.1030206000, 0.1702623000, 0.3312943000, 0.7715000000", \ - "0.0486939000, 0.0561429000, 0.0716374000, 0.1028306000, 0.1697015000, 0.3312440000, 0.7716902000", \ - "0.0488978000, 0.0560529000, 0.0716343000, 0.1036146000, 0.1710523000, 0.3311616000, 0.7716864000", \ - "0.0486073000, 0.0558897000, 0.0715541000, 0.1038969000, 0.1712447000, 0.3302759000, 0.7711926000", \ - "0.0487397000, 0.0563735000, 0.0715173000, 0.1034149000, 0.1700228000, 0.3301849000, 0.7730171000", \ - "0.0488186000, 0.0561308000, 0.0717073000, 0.1032198000, 0.1695353000, 0.3309940000, 0.7711933000", \ - "0.0492178000, 0.0563055000, 0.0718326000, 0.1038045000, 0.1712739000, 0.3308177000, 0.7699369000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0208649000, 0.0274273000, 0.0452183000, 0.0938506000, 0.2261101000, 0.5777290000, 1.5006113000", \ - "0.0207778000, 0.0274063000, 0.0451772000, 0.0941082000, 0.2260055000, 0.5772142000, 1.4956998000", \ - "0.0207899000, 0.0274784000, 0.0451514000, 0.0939520000, 0.2261406000, 0.5778263000, 1.5027855000", \ - "0.0207759000, 0.0274003000, 0.0451903000, 0.0938908000, 0.2259585000, 0.5771925000, 1.5005415000", \ - "0.0212409000, 0.0277963000, 0.0455146000, 0.0940247000, 0.2255490000, 0.5765038000, 1.4914070000", \ - "0.0224037000, 0.0288473000, 0.0462044000, 0.0943810000, 0.2256020000, 0.5739504000, 1.5011697000", \ - "0.0252160000, 0.0312942000, 0.0478426000, 0.0953696000, 0.2260104000, 0.5749118000, 1.4933946000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3b_2") { - leakage_power () { - value : 0.0062632000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0019541000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0019497000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0012591000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0019113000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0012528000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0017152000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0012293000; - when : "A&B&!C_N"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__or3b"; - cell_leakage_power : 0.0021918340; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019029000, 0.0019079000, 0.0019195000, 0.0019203000, 0.0019223000, 0.0019268000, 0.0019372000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001719900, -0.001731300, -0.001757500, -0.001763200, -0.001776300, -0.001806600, -0.001876300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015340000; - } - pin ("B") { - capacitance : 0.0015510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027468000, 0.0027432000, 0.0027350000, 0.0027364000, 0.0027397000, 0.0027473000, 0.0027649000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002660500, -0.002675400, -0.002709800, -0.002711500, -0.002715500, -0.002724800, -0.002746100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016150000; - } - pin ("C_N") { - capacitance : 0.0015090000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079107000, 0.0078134000, 0.0075892000, 0.0076372000, 0.0077477000, 0.0080025000, 0.0085899000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0013068000, 0.0012407000, 0.0010884000, 0.0011307000, 0.0012282000, 0.0014531000, 0.0019713000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015720000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0129957000, 0.0112103000, 0.0069188000, -0.004184800, -0.037135100, -0.134812000, -0.417779100", \ - "0.0128855000, 0.0111125000, 0.0068223000, -0.004377600, -0.037260500, -0.134898300, -0.417912500", \ - "0.0126655000, 0.0108878000, 0.0066598000, -0.004476700, -0.037435900, -0.135077000, -0.418065700", \ - "0.0125744000, 0.0107609000, 0.0065363000, -0.004675100, -0.037360300, -0.135269000, -0.418193500", \ - "0.0124346000, 0.0107775000, 0.0065523000, -0.004688700, -0.037612300, -0.135453000, -0.418303700", \ - "0.0124975000, 0.0107366000, 0.0064994000, -0.004801700, -0.037780800, -0.135531400, -0.418371800", \ - "0.0152040000, 0.0133145000, 0.0084165000, -0.004363700, -0.037595400, -0.135373300, -0.418248100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0151084000, 0.0167142000, 0.0212008000, 0.0335895000, 0.0682007000, 0.1662493000, 0.4457676000", \ - "0.0150553000, 0.0166939000, 0.0211962000, 0.0335608000, 0.0682158000, 0.1662083000, 0.4459229000", \ - "0.0150165000, 0.0166287000, 0.0211573000, 0.0335095000, 0.0681561000, 0.1662242000, 0.4461004000", \ - "0.0149791000, 0.0165643000, 0.0210326000, 0.0334135000, 0.0680816000, 0.1661816000, 0.4457237000", \ - "0.0149919000, 0.0165493000, 0.0209262000, 0.0331458000, 0.0677866000, 0.1661437000, 0.4456176000", \ - "0.0156167000, 0.0170825000, 0.0213557000, 0.0332255000, 0.0678382000, 0.1658358000, 0.4457411000", \ - "0.0164527000, 0.0179073000, 0.0220087000, 0.0343955000, 0.0685073000, 0.1665791000, 0.4453040000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0115160000, 0.0097450000, 0.0054707000, -0.005712700, -0.038580200, -0.136288100, -0.419110300", \ - "0.0116805000, 0.0099013000, 0.0053792000, -0.005663100, -0.038492200, -0.136368300, -0.419172000", \ - "0.0112620000, 0.0094888000, 0.0052703000, -0.005941200, -0.038618800, -0.136447400, -0.419265800", \ - "0.0111451000, 0.0093792000, 0.0051190000, -0.006049500, -0.038704900, -0.136625700, -0.419394000", \ - "0.0111020000, 0.0093103000, 0.0050303000, -0.006187800, -0.039035200, -0.136722900, -0.419442100", \ - "0.0112583000, 0.0094846000, 0.0052088000, -0.006069500, -0.039044200, -0.136764900, -0.419556500", \ - "0.0135323000, 0.0116358000, 0.0066800000, -0.006213800, -0.039071700, -0.136765700, -0.419488800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0150360000, 0.0166542000, 0.0212488000, 0.0338238000, 0.0687951000, 0.1672149000, 0.4467358000", \ - "0.0150380000, 0.0166630000, 0.0212163000, 0.0338481000, 0.0688112000, 0.1671745000, 0.4472807000", \ - "0.0150296000, 0.0166736000, 0.0212498000, 0.0338018000, 0.0687879000, 0.1673398000, 0.4469359000", \ - "0.0150787000, 0.0166713000, 0.0210644000, 0.0335422000, 0.0685190000, 0.1668656000, 0.4467900000", \ - "0.0149873000, 0.0165163000, 0.0209755000, 0.0331391000, 0.0681037000, 0.1667317000, 0.4466843000", \ - "0.0154694000, 0.0170451000, 0.0213539000, 0.0335229000, 0.0680359000, 0.1663508000, 0.4464475000", \ - "0.0162063000, 0.0176538000, 0.0217518000, 0.0340478000, 0.0684800000, 0.1669203000, 0.4458680000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0117759000, 0.0100100000, 0.0057442000, -0.005459300, -0.038360500, -0.135978400, -0.418817300", \ - "0.0117913000, 0.0099963000, 0.0057989000, -0.005412500, -0.038362700, -0.136026500, -0.418807900", \ - "0.0116746000, 0.0099091000, 0.0056412000, -0.005557300, -0.038454400, -0.136017500, -0.418898200", \ - "0.0113519000, 0.0095743000, 0.0052922000, -0.005924800, -0.038765400, -0.136380700, -0.419204000", \ - "0.0110596000, 0.0092832000, 0.0050369000, -0.006142900, -0.038994600, -0.136718200, -0.419470400", \ - "0.0109519000, 0.0091936000, 0.0048776000, -0.006108000, -0.039055500, -0.136809800, -0.419648800", \ - "0.0164658000, 0.0147026000, 0.0099522000, -0.002566600, -0.037444200, -0.136688800, -0.419512400"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014260920, 0.0040674750, 0.0116011800, 0.0330887100, 0.0943750500, 0.2691750000"); - values("0.0147176000, 0.0162917000, 0.0208056000, 0.0333190000, 0.0682480000, 0.1667441000, 0.4472277000", \ - "0.0145881000, 0.0162363000, 0.0207706000, 0.0332905000, 0.0681511000, 0.1666114000, 0.4468183000", \ - "0.0146969000, 0.0163063000, 0.0207661000, 0.0333640000, 0.0682267000, 0.1666726000, 0.4468134000", \ - "0.0145726000, 0.0161467000, 0.0206590000, 0.0331710000, 0.0681479000, 0.1665860000, 0.4472523000", \ - "0.0143657000, 0.0159853000, 0.0205228000, 0.0330042000, 0.0679064000, 0.1665138000, 0.4470841000", \ - "0.0143460000, 0.0158868000, 0.0203058000, 0.0328101000, 0.0675925000, 0.1659526000, 0.4465890000", \ - "0.0146738000, 0.0162218000, 0.0205956000, 0.0329812000, 0.0674100000, 0.1664987000, 0.4456512000"); - } - } - max_capacitance : 0.2691750000; - max_transition : 1.5041460000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.4233013000, 0.4333099000, 0.4551437000, 0.4991850000, 0.5783755000, 0.7248681000, 1.0397053000", \ - "0.4264182000, 0.4364918000, 0.4586889000, 0.5022006000, 0.5815515000, 0.7280774000, 1.0430252000", \ - "0.4358371000, 0.4457187000, 0.4679451000, 0.5115672000, 0.5908670000, 0.7373840000, 1.0523041000", \ - "0.4595837000, 0.4693560000, 0.4915909000, 0.5350098000, 0.6139237000, 0.7609258000, 1.0758054000", \ - "0.5129731000, 0.5229235000, 0.5452619000, 0.5887391000, 0.6680922000, 0.8155834000, 1.1297510000", \ - "0.6321961000, 0.6420969000, 0.6642631000, 0.7077200000, 0.7869497000, 0.9344651000, 1.2494352000", \ - "0.8651272000, 0.8758355000, 0.8992188000, 0.9465712000, 1.0315881000, 1.1849404000, 1.5041284000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0760396000, 0.0813894000, 0.0942192000, 0.1251586000, 0.2070926000, 0.4370092000, 1.0919966000", \ - "0.0807637000, 0.0861414000, 0.0989985000, 0.1298192000, 0.2119086000, 0.4416733000, 1.0966347000", \ - "0.0921291000, 0.0974817000, 0.1103475000, 0.1411614000, 0.2232433000, 0.4528271000, 1.1078974000", \ - "0.1186053000, 0.1239247000, 0.1365832000, 0.1672978000, 0.2492830000, 0.4793334000, 1.1345558000", \ - "0.1627769000, 0.1687669000, 0.1822266000, 0.2137191000, 0.2958769000, 0.5258921000, 1.1813300000", \ - "0.2163288000, 0.2240947000, 0.2409195000, 0.2744321000, 0.3563337000, 0.5863420000, 1.2429850000", \ - "0.2613452000, 0.2717191000, 0.2938498000, 0.3356568000, 0.4197714000, 0.6496168000, 1.3029634000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0631837000, 0.0690114000, 0.0822351000, 0.1110561000, 0.1660835000, 0.2954362000, 0.6438052000", \ - "0.0634660000, 0.0692982000, 0.0825785000, 0.1097507000, 0.1664622000, 0.2952816000, 0.6440825000", \ - "0.0633931000, 0.0692480000, 0.0822934000, 0.1110559000, 0.1660124000, 0.2954668000, 0.6440735000", \ - "0.0637969000, 0.0692204000, 0.0823080000, 0.1097497000, 0.1667530000, 0.2953011000, 0.6437546000", \ - "0.0632049000, 0.0692395000, 0.0831833000, 0.1096928000, 0.1655713000, 0.2942663000, 0.6446588000", \ - "0.0635269000, 0.0695548000, 0.0828040000, 0.1100221000, 0.1665087000, 0.2941261000, 0.6437791000", \ - "0.0744582000, 0.0803872000, 0.0937426000, 0.1224766000, 0.1783518000, 0.3031606000, 0.6487577000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0202422000, 0.0251910000, 0.0389038000, 0.0786107000, 0.1959205000, 0.5346699000, 1.5002801000", \ - "0.0201499000, 0.0251766000, 0.0389414000, 0.0787129000, 0.1960137000, 0.5346283000, 1.5008451000", \ - "0.0200814000, 0.0251186000, 0.0388991000, 0.0785934000, 0.1958811000, 0.5343157000, 1.5012469000", \ - "0.0203681000, 0.0253147000, 0.0389887000, 0.0785983000, 0.1956477000, 0.5347249000, 1.4998413000", \ - "0.0249638000, 0.0296299000, 0.0426520000, 0.0806526000, 0.1958036000, 0.5348736000, 1.4983733000", \ - "0.0341095000, 0.0389798000, 0.0514675000, 0.0865344000, 0.1980503000, 0.5347801000, 1.4986477000", \ - "0.0481111000, 0.0551791000, 0.0688902000, 0.1019402000, 0.2033408000, 0.5361140000, 1.4950936000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.4003292000, 0.4103024000, 0.4323696000, 0.4761112000, 0.5552104000, 0.7021106000, 1.0172486000", \ - "0.4032079000, 0.4129076000, 0.4351971000, 0.4788486000, 0.5575875000, 0.7046882000, 1.0196423000", \ - "0.4122502000, 0.4221552000, 0.4443970000, 0.4878281000, 0.5667875000, 0.7138640000, 1.0288435000", \ - "0.4363810000, 0.4461868000, 0.4679190000, 0.5117900000, 0.5907761000, 0.7378027000, 1.0528425000", \ - "0.4946077000, 0.5044559000, 0.5266685000, 0.5700201000, 0.6493380000, 0.7963816000, 1.1119021000", \ - "0.6325266000, 0.6424248000, 0.6645319000, 0.7079972000, 0.7871755000, 0.9346977000, 1.2498220000", \ - "0.9062378000, 0.9171899000, 0.9413514000, 0.9886429000, 1.0736045000, 1.2269522000, 1.5458821000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0743896000, 0.0796954000, 0.0925047000, 0.1234391000, 0.2057727000, 0.4366404000, 1.0906468000", \ - "0.0791422000, 0.0844737000, 0.0972778000, 0.1282865000, 0.2107407000, 0.4411693000, 1.0957889000", \ - "0.0906901000, 0.0960053000, 0.1088107000, 0.1397175000, 0.2220403000, 0.4532823000, 1.1080646000", \ - "0.1168393000, 0.1220912000, 0.1346304000, 0.1653769000, 0.2475703000, 0.4785882000, 1.1342711000", \ - "0.1592984000, 0.1653038000, 0.1790121000, 0.2101668000, 0.2924442000, 0.5234576000, 1.1794483000", \ - "0.2093567000, 0.2169764000, 0.2340032000, 0.2680147000, 0.3505291000, 0.5801946000, 1.2365414000", \ - "0.2508449000, 0.2614360000, 0.2837212000, 0.3261887000, 0.4115697000, 0.6410968000, 1.2947758000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0635623000, 0.0692673000, 0.0828353000, 0.1110741000, 0.1652981000, 0.2949714000, 0.6445709000", \ - "0.0634655000, 0.0694445000, 0.0823549000, 0.1115315000, 0.1667549000, 0.2951389000, 0.6437518000", \ - "0.0633988000, 0.0692433000, 0.0823537000, 0.1097735000, 0.1664650000, 0.2951700000, 0.6437708000", \ - "0.0634459000, 0.0690589000, 0.0821281000, 0.1097765000, 0.1678566000, 0.2940699000, 0.6439811000", \ - "0.0635365000, 0.0689998000, 0.0826392000, 0.1097700000, 0.1673761000, 0.2950072000, 0.6428124000", \ - "0.0635633000, 0.0692091000, 0.0826786000, 0.1114480000, 0.1655859000, 0.2946089000, 0.6433763000", \ - "0.0770880000, 0.0834398000, 0.0974594000, 0.1251926000, 0.1797342000, 0.3035001000, 0.6492211000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0195877000, 0.0245304000, 0.0382000000, 0.0779624000, 0.1955316000, 0.5339006000, 1.5017652000", \ - "0.0195744000, 0.0245195000, 0.0381926000, 0.0777333000, 0.1954298000, 0.5339991000, 1.5013915000", \ - "0.0195428000, 0.0244981000, 0.0381958000, 0.0778851000, 0.1954279000, 0.5346798000, 1.4996916000", \ - "0.0199140000, 0.0248201000, 0.0385640000, 0.0779229000, 0.1954795000, 0.5337494000, 1.4967371000", \ - "0.0247531000, 0.0294182000, 0.0422076000, 0.0800713000, 0.1959226000, 0.5336119000, 1.4991101000", \ - "0.0341886000, 0.0397715000, 0.0519418000, 0.0863609000, 0.1977074000, 0.5330602000, 1.4981667000", \ - "0.0488244000, 0.0554938000, 0.0700494000, 0.1024742000, 0.2032094000, 0.5349721000, 1.4981170000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.3985092000, 0.4087021000, 0.4309520000, 0.4744105000, 0.5537318000, 0.7002655000, 1.0154020000", \ - "0.4027128000, 0.4128106000, 0.4350010000, 0.4787984000, 0.5579454000, 0.7048888000, 1.0200296000", \ - "0.4113749000, 0.4214818000, 0.4437221000, 0.4873533000, 0.5667809000, 0.7133410000, 1.0284291000", \ - "0.4263331000, 0.4364088000, 0.4587127000, 0.5022043000, 0.5817177000, 0.7283517000, 1.0435155000", \ - "0.4479692000, 0.4579474000, 0.4800815000, 0.5236623000, 0.6032299000, 0.7510210000, 1.0658228000", \ - "0.4720880000, 0.4820437000, 0.5041192000, 0.5475454000, 0.6263155000, 0.7739704000, 1.0881774000", \ - "0.4840692000, 0.4939717000, 0.5160624000, 0.5597952000, 0.6389879000, 0.7864687000, 1.1004574000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.1556845000, 0.1611163000, 0.1742217000, 0.2054693000, 0.2878104000, 0.5179178000, 1.1770964000", \ - "0.1600826000, 0.1656300000, 0.1787397000, 0.2099740000, 0.2920276000, 0.5229185000, 1.1794510000", \ - "0.1730054000, 0.1785585000, 0.1915656000, 0.2228657000, 0.3049143000, 0.5357649000, 1.1922090000", \ - "0.2050425000, 0.2104797000, 0.2235904000, 0.2548292000, 0.3372025000, 0.5672371000, 1.2230434000", \ - "0.2730887000, 0.2786290000, 0.2917767000, 0.3229772000, 0.4054462000, 0.6357160000, 1.2958207000", \ - "0.3857036000, 0.3913849000, 0.4047856000, 0.4361661000, 0.5183641000, 0.7482008000, 1.4055619000", \ - "0.5658517000, 0.5720637000, 0.5860881000, 0.6180150000, 0.7004880000, 0.9309666000, 1.5850488000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0635900000, 0.0692998000, 0.0828173000, 0.1097224000, 0.1665287000, 0.2953980000, 0.6440091000", \ - "0.0635333000, 0.0692780000, 0.0826990000, 0.1110613000, 0.1650799000, 0.2942804000, 0.6440053000", \ - "0.0635988000, 0.0693055000, 0.0823620000, 0.1096979000, 0.1660262000, 0.2953802000, 0.6441108000", \ - "0.0635244000, 0.0692828000, 0.0827644000, 0.1098471000, 0.1671276000, 0.2953656000, 0.6440196000", \ - "0.0632365000, 0.0689928000, 0.0831716000, 0.1096659000, 0.1660342000, 0.2935150000, 0.6447364000", \ - "0.0629414000, 0.0688331000, 0.0819915000, 0.1090378000, 0.1644825000, 0.2947634000, 0.6437816000", \ - "0.0633393000, 0.0690627000, 0.0825592000, 0.1106705000, 0.1656066000, 0.2934285000, 0.6417212000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014260900, 0.0040674800, 0.0116012000, 0.0330887000, 0.0943750000, 0.2691750000"); - values("0.0208910000, 0.0258767000, 0.0393966000, 0.0787673000, 0.1955400000, 0.5348011000, 1.5007642000", \ - "0.0208631000, 0.0258299000, 0.0394003000, 0.0785341000, 0.1951568000, 0.5355629000, 1.4999018000", \ - "0.0208249000, 0.0257160000, 0.0393845000, 0.0785430000, 0.1950995000, 0.5353256000, 1.4986760000", \ - "0.0208906000, 0.0258690000, 0.0393950000, 0.0787665000, 0.1956566000, 0.5347473000, 1.5041464000", \ - "0.0210772000, 0.0259981000, 0.0395522000, 0.0788407000, 0.1957770000, 0.5348642000, 1.5008197000", \ - "0.0221920000, 0.0271394000, 0.0404999000, 0.0794316000, 0.1958477000, 0.5325662000, 1.5032084000", \ - "0.0249702000, 0.0298861000, 0.0428399000, 0.0808874000, 0.1957915000, 0.5332608000, 1.4988284000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or3b_4") { - leakage_power () { - value : 0.0053899000; - when : "!A&!B&C_N"; - } - leakage_power () { - value : 0.0046117000; - when : "!A&!B&!C_N"; - } - leakage_power () { - value : 0.0032644000; - when : "!A&B&C_N"; - } - leakage_power () { - value : 0.0024951000; - when : "!A&B&!C_N"; - } - leakage_power () { - value : 0.0031463000; - when : "A&!B&C_N"; - } - leakage_power () { - value : 0.0024858000; - when : "A&!B&!C_N"; - } - leakage_power () { - value : 0.0027968000; - when : "A&B&C_N"; - } - leakage_power () { - value : 0.0024648000; - when : "A&B&!C_N"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__or3b"; - cell_leakage_power : 0.0033318510; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040168000, 0.0040102000, 0.0039950000, 0.0039964000, 0.0039994000, 0.0040064000, 0.0040225000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003482000, -0.003515800, -0.003593800, -0.003604900, -0.003630600, -0.003689700, -0.003826000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025620000; - } - pin ("B") { - capacitance : 0.0023740000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022240000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0043522000, 0.0043488000, 0.0043410000, 0.0043382000, 0.0043319000, 0.0043173000, 0.0042836000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004074000, -0.004135000, -0.004275600, -0.004279300, -0.004287600, -0.004306900, -0.004351400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025240000; - } - pin ("C_N") { - capacitance : 0.0014920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014260000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090681000, 0.0089661000, 0.0087310000, 0.0087725000, 0.0088681000, 0.0090886000, 0.0095967000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031976000, 0.0031437000, 0.0030193000, 0.0030563000, 0.0031416000, 0.0033382000, 0.0037914000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015570000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0246152000, 0.0226482000, 0.0170047000, 0.0019364000, -0.046796400, -0.208967500, -0.726187500", \ - "0.0245057000, 0.0225152000, 0.0173584000, 0.0020890000, -0.046658900, -0.209031300, -0.726351800", \ - "0.0242879000, 0.0223095000, 0.0172356000, 0.0014802000, -0.046771200, -0.209223700, -0.726530200", \ - "0.0240041000, 0.0220507000, 0.0165197000, 0.0013004000, -0.047414800, -0.209525000, -0.726718600", \ - "0.0239445000, 0.0220082000, 0.0163301000, 0.0012111000, -0.047477600, -0.209693400, -0.726904600", \ - "0.0239106000, 0.0218967000, 0.0163961000, 0.0011287000, -0.047714500, -0.209775000, -0.726932700", \ - "0.0304134000, 0.0282844000, 0.0221002000, 0.0046812000, -0.048277300, -0.209683500, -0.726652400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0299791000, 0.0318403000, 0.0374606000, 0.0548826000, 0.1077281000, 0.2714925000, 0.7828965000", \ - "0.0299268000, 0.0317753000, 0.0374116000, 0.0548269000, 0.1077368000, 0.2714519000, 0.7832381000", \ - "0.0297939000, 0.0316427000, 0.0373534000, 0.0547873000, 0.1076368000, 0.2715232000, 0.7833878000", \ - "0.0298683000, 0.0317007000, 0.0373898000, 0.0547269000, 0.1075702000, 0.2712969000, 0.7828822000", \ - "0.0298552000, 0.0316561000, 0.0372419000, 0.0540279000, 0.1070214000, 0.2712628000, 0.7825997000", \ - "0.0309467000, 0.0326395000, 0.0380484000, 0.0549796000, 0.1070637000, 0.2705166000, 0.7825327000", \ - "0.0324280000, 0.0340839000, 0.0393746000, 0.0558521000, 0.1083966000, 0.2718207000, 0.7818669000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0221167000, 0.0201394000, 0.0144889000, -0.000652600, -0.049505800, -0.211596300, -0.728643600", \ - "0.0219180000, 0.0198900000, 0.0141635000, -0.000928600, -0.049636300, -0.211792000, -0.728759500", \ - "0.0214684000, 0.0194576000, 0.0138102000, -0.001241800, -0.049939300, -0.211907600, -0.728860100", \ - "0.0214872000, 0.0195747000, 0.0140561000, -0.001120700, -0.050150200, -0.212020700, -0.729071200", \ - "0.0211080000, 0.0191869000, 0.0135878000, -0.001646500, -0.050287900, -0.212181100, -0.729165600", \ - "0.0213668000, 0.0195421000, 0.0135604000, -0.001705400, -0.050339400, -0.212307300, -0.729218600", \ - "0.0277056000, 0.0255409000, 0.0204962000, 0.0023207000, -0.048797100, -0.211864800, -0.728833000"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0295141000, 0.0312973000, 0.0371072000, 0.0547546000, 0.1082594000, 0.2728366000, 0.7843946000", \ - "0.0295501000, 0.0314250000, 0.0371354000, 0.0548513000, 0.1082854000, 0.2728950000, 0.7846348000", \ - "0.0295459000, 0.0313975000, 0.0372612000, 0.0548896000, 0.1083687000, 0.2728710000, 0.7848073000", \ - "0.0294495000, 0.0313477000, 0.0370827000, 0.0546204000, 0.1079429000, 0.2727076000, 0.7841998000", \ - "0.0294385000, 0.0312367000, 0.0368727000, 0.0538801000, 0.1071304000, 0.2721492000, 0.7840638000", \ - "0.0301777000, 0.0319199000, 0.0372093000, 0.0541989000, 0.1066965000, 0.2706968000, 0.7833191000", \ - "0.0317339000, 0.0333621000, 0.0386026000, 0.0553443000, 0.1079765000, 0.2721887000, 0.7818958000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0216480000, 0.0196613000, 0.0140170000, -0.001108100, -0.049905200, -0.211756600, -0.728756500", \ - "0.0214174000, 0.0194493000, 0.0139654000, -0.001256700, -0.049872300, -0.211718900, -0.728715800", \ - "0.0214686000, 0.0194462000, 0.0138792000, -0.001336300, -0.049952300, -0.211734700, -0.728745500", \ - "0.0210938000, 0.0191176000, 0.0134615000, -0.001373300, -0.050184900, -0.212169500, -0.729155500", \ - "0.0206922000, 0.0187774000, 0.0131412000, -0.002050100, -0.050695900, -0.212537100, -0.729421500", \ - "0.0206775000, 0.0186869000, 0.0130329000, -0.001834400, -0.050644700, -0.212692200, -0.729629800", \ - "0.0302091000, 0.0281970000, 0.0222979000, 0.0051044000, -0.047551800, -0.212587600, -0.729599300"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015647370, 0.0048968030, 0.0153244200, 0.0479573500, 0.1500813000, 0.4696754000"); - values("0.0284090000, 0.0302770000, 0.0359766000, 0.0535586000, 0.1068081000, 0.2710182000, 0.7838679000", \ - "0.0284059000, 0.0302542000, 0.0359957000, 0.0535194000, 0.1068232000, 0.2710564000, 0.7848658000", \ - "0.0284558000, 0.0302888000, 0.0360384000, 0.0535713000, 0.1068438000, 0.2712376000, 0.7842507000", \ - "0.0282252000, 0.0300944000, 0.0358434000, 0.0533750000, 0.1066336000, 0.2707443000, 0.7842648000", \ - "0.0280105000, 0.0298608000, 0.0355992000, 0.0529457000, 0.1063716000, 0.2707313000, 0.7832111000", \ - "0.0277820000, 0.0296097000, 0.0352000000, 0.0526852000, 0.1058137000, 0.2701532000, 0.7802186000", \ - "0.0285567000, 0.0303247000, 0.0358315000, 0.0527961000, 0.1054494000, 0.2704752000, 0.7822757000"); - } - } - max_capacitance : 0.4696750000; - max_transition : 1.5076340000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.3540623000, 0.3599510000, 0.3752742000, 0.4089528000, 0.4750836000, 0.6047603000, 0.9061105000", \ - "0.3584454000, 0.3644727000, 0.3798000000, 0.4134047000, 0.4792793000, 0.6096763000, 0.9107041000", \ - "0.3698933000, 0.3757562000, 0.3911866000, 0.4245824000, 0.4904405000, 0.6210565000, 0.9220935000", \ - "0.3957793000, 0.4016373000, 0.4169279000, 0.4504742000, 0.5168650000, 0.6466119000, 0.9480476000", \ - "0.4526578000, 0.4587217000, 0.4739282000, 0.5073722000, 0.5731879000, 0.7037145000, 1.0052240000", \ - "0.5772892000, 0.5832727000, 0.5984298000, 0.6319303000, 0.6981941000, 0.8287229000, 1.1301647000", \ - "0.8133039000, 0.8197731000, 0.8363008000, 0.8749487000, 0.9467584000, 1.0844181000, 1.3912773000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0870782000, 0.0909273000, 0.1011337000, 0.1276647000, 0.2010622000, 0.4248073000, 1.1240081000", \ - "0.0916340000, 0.0954553000, 0.1056981000, 0.1321928000, 0.2055719000, 0.4299305000, 1.1260006000", \ - "0.1024289000, 0.1062593000, 0.1165346000, 0.1430345000, 0.2164595000, 0.4406798000, 1.1370449000", \ - "0.1287063000, 0.1324852000, 0.1426709000, 0.1689088000, 0.2423726000, 0.4658678000, 1.1653998000", \ - "0.1753846000, 0.1795992000, 0.1904298000, 0.2172682000, 0.2908657000, 0.5146915000, 1.2113366000", \ - "0.2321183000, 0.2374702000, 0.2509198000, 0.2803278000, 0.3547197000, 0.5772017000, 1.2743783000", \ - "0.2794887000, 0.2865617000, 0.3042274000, 0.3412081000, 0.4193370000, 0.6415857000, 1.3369185000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0558550000, 0.0588947000, 0.0679129000, 0.0883809000, 0.1350495000, 0.2525989000, 0.6011208000", \ - "0.0557690000, 0.0588804000, 0.0684245000, 0.0893436000, 0.1351127000, 0.2522063000, 0.6018273000", \ - "0.0558807000, 0.0588958000, 0.0683475000, 0.0884345000, 0.1358314000, 0.2521656000, 0.6017971000", \ - "0.0556668000, 0.0588763000, 0.0681846000, 0.0894147000, 0.1353092000, 0.2525194000, 0.6012226000", \ - "0.0558189000, 0.0588301000, 0.0678168000, 0.0885497000, 0.1356936000, 0.2518933000, 0.6018597000", \ - "0.0572460000, 0.0605441000, 0.0693381000, 0.0895200000, 0.1358165000, 0.2525504000, 0.6015796000", \ - "0.0686804000, 0.0720586000, 0.0810129000, 0.1024778000, 0.1499316000, 0.2663872000, 0.6086189000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0220283000, 0.0253677000, 0.0355234000, 0.0666643000, 0.1676387000, 0.4898717000, 1.5014705000", \ - "0.0220367000, 0.0253845000, 0.0355660000, 0.0666408000, 0.1676583000, 0.4904729000, 1.4990994000", \ - "0.0220404000, 0.0254095000, 0.0355064000, 0.0666425000, 0.1676202000, 0.4900303000, 1.4974357000", \ - "0.0218578000, 0.0252308000, 0.0353015000, 0.0665512000, 0.1678867000, 0.4902256000, 1.5010562000", \ - "0.0260896000, 0.0292245000, 0.0387970000, 0.0686201000, 0.1680500000, 0.4892808000, 1.4995180000", \ - "0.0356863000, 0.0388490000, 0.0482548000, 0.0752537000, 0.1702107000, 0.4899172000, 1.5001475000", \ - "0.0502321000, 0.0544200000, 0.0655840000, 0.0922725000, 0.1781448000, 0.4917696000, 1.4982672000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.3339928000, 0.3399032000, 0.3551026000, 0.3887269000, 0.4548951000, 0.5854432000, 0.8866092000", \ - "0.3376929000, 0.3435798000, 0.3589065000, 0.3924808000, 0.4585287000, 0.5892872000, 0.8902963000", \ - "0.3480632000, 0.3539165000, 0.3691836000, 0.4028290000, 0.4689931000, 0.5988839000, 0.9004401000", \ - "0.3735754000, 0.3794508000, 0.3946740000, 0.4281181000, 0.4942324000, 0.6249818000, 0.9261798000", \ - "0.4340337000, 0.4398907000, 0.4550714000, 0.4886230000, 0.5545225000, 0.6851701000, 0.9873564000", \ - "0.5734022000, 0.5795640000, 0.5949928000, 0.6285298000, 0.6943627000, 0.8256020000, 1.1271870000", \ - "0.8409997000, 0.8475585000, 0.8653011000, 0.9029321000, 0.9761244000, 1.1140757000, 1.4210193000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0836767000, 0.0873944000, 0.0975874000, 0.1240198000, 0.1976676000, 0.4218199000, 1.1196065000", \ - "0.0883799000, 0.0921558000, 0.1022658000, 0.1287265000, 0.2025641000, 0.4264231000, 1.1242318000", \ - "0.0993519000, 0.1031208000, 0.1132911000, 0.1396625000, 0.2132682000, 0.4377765000, 1.1367590000", \ - "0.1252852000, 0.1290164000, 0.1390813000, 0.1653007000, 0.2390277000, 0.4631757000, 1.1598881000", \ - "0.1699099000, 0.1741026000, 0.1849428000, 0.2117680000, 0.2851810000, 0.5095759000, 1.2057478000", \ - "0.2229642000, 0.2283811000, 0.2415789000, 0.2714403000, 0.3457045000, 0.5694853000, 1.2682044000", \ - "0.2647057000, 0.2719754000, 0.2898560000, 0.3271928000, 0.4057689000, 0.6287440000, 1.3248834000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0556090000, 0.0589621000, 0.0679130000, 0.0893673000, 0.1350325000, 0.2517793000, 0.6016577000", \ - "0.0556383000, 0.0590197000, 0.0676789000, 0.0892645000, 0.1352441000, 0.2518444000, 0.6024696000", \ - "0.0558721000, 0.0588912000, 0.0678902000, 0.0883599000, 0.1350573000, 0.2525686000, 0.6012157000", \ - "0.0556263000, 0.0589223000, 0.0683692000, 0.0891402000, 0.1350061000, 0.2517127000, 0.6018711000", \ - "0.0556763000, 0.0589471000, 0.0683245000, 0.0893882000, 0.1347961000, 0.2520070000, 0.6015144000", \ - "0.0571234000, 0.0605009000, 0.0690502000, 0.0893040000, 0.1358046000, 0.2517308000, 0.6016118000", \ - "0.0737973000, 0.0771851000, 0.0857633000, 0.1080955000, 0.1534076000, 0.2670660000, 0.6090907000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0212734000, 0.0246004000, 0.0346237000, 0.0657724000, 0.1668533000, 0.4889945000, 1.5014845000", \ - "0.0212021000, 0.0245339000, 0.0345827000, 0.0657442000, 0.1671080000, 0.4898842000, 1.4996115000", \ - "0.0212103000, 0.0246207000, 0.0345458000, 0.0658547000, 0.1670176000, 0.4897645000, 1.5025906000", \ - "0.0213005000, 0.0246757000, 0.0346967000, 0.0658021000, 0.1672460000, 0.4905151000, 1.4984478000", \ - "0.0258377000, 0.0290504000, 0.0384418000, 0.0681099000, 0.1674747000, 0.4906666000, 1.5008140000", \ - "0.0353571000, 0.0389888000, 0.0479726000, 0.0752106000, 0.1699104000, 0.4890157000, 1.4972487000", \ - "0.0512795000, 0.0549632000, 0.0664836000, 0.0924440000, 0.1787293000, 0.4921999000, 1.4972720000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.3338033000, 0.3396801000, 0.3551963000, 0.3888257000, 0.4549280000, 0.5857149000, 0.8867071000", \ - "0.3381819000, 0.3440677000, 0.3594870000, 0.3932050000, 0.4594171000, 0.5895107000, 0.8912210000", \ - "0.3489289000, 0.3548434000, 0.3700568000, 0.4037734000, 0.4701175000, 0.6000997000, 0.9017767000", \ - "0.3688691000, 0.3748889000, 0.3901258000, 0.4237661000, 0.4899225000, 0.6200733000, 0.9217527000", \ - "0.3971349000, 0.4031235000, 0.4183392000, 0.4518074000, 0.5180873000, 0.6488851000, 0.9507880000", \ - "0.4321297000, 0.4381015000, 0.4532736000, 0.4866880000, 0.5524597000, 0.6830740000, 0.9848865000", \ - "0.4609961000, 0.4669650000, 0.4820726000, 0.5156897000, 0.5816125000, 0.7127063000, 1.0143395000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.1955713000, 0.1995678000, 0.2101520000, 0.2371553000, 0.3109254000, 0.5348747000, 1.2317843000", \ - "0.2006645000, 0.2046869000, 0.2152701000, 0.2421885000, 0.3160885000, 0.5397159000, 1.2413012000", \ - "0.2132724000, 0.2172698000, 0.2278437000, 0.2548513000, 0.3286350000, 0.5529573000, 1.2541084000", \ - "0.2448324000, 0.2488338000, 0.2594122000, 0.2864170000, 0.3602134000, 0.5844991000, 1.2832064000", \ - "0.3179963000, 0.3219985000, 0.3326232000, 0.3594769000, 0.4335165000, 0.6571266000, 1.3547273000", \ - "0.4517121000, 0.4558154000, 0.4665299000, 0.4937498000, 0.5674982000, 0.7920969000, 1.4916821000", \ - "0.6660635000, 0.6705307000, 0.6820485000, 0.7097727000, 0.7835763000, 1.0076877000, 1.7052785000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0556684000, 0.0588476000, 0.0678996000, 0.0885461000, 0.1347848000, 0.2516721000, 0.6021459000", \ - "0.0556234000, 0.0589238000, 0.0682683000, 0.0894164000, 0.1350626000, 0.2522484000, 0.6013962000", \ - "0.0559697000, 0.0593814000, 0.0683517000, 0.0896010000, 0.1349071000, 0.2522909000, 0.6012837000", \ - "0.0558550000, 0.0588859000, 0.0677374000, 0.0892118000, 0.1353513000, 0.2521374000, 0.6017858000", \ - "0.0559004000, 0.0592978000, 0.0680739000, 0.0884746000, 0.1349564000, 0.2518280000, 0.6016521000", \ - "0.0558388000, 0.0588592000, 0.0678063000, 0.0894076000, 0.1352474000, 0.2517876000, 0.6018213000", \ - "0.0557938000, 0.0591386000, 0.0682675000, 0.0889096000, 0.1361124000, 0.2505807000, 0.6011784000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015647400, 0.0048968000, 0.0153244000, 0.0479573000, 0.1500810000, 0.4696750000"); - values("0.0232550000, 0.0265402000, 0.0365821000, 0.0672271000, 0.1673563000, 0.4900380000, 1.5058039000", \ - "0.0232316000, 0.0265052000, 0.0365769000, 0.0672327000, 0.1675931000, 0.4900735000, 1.5071957000", \ - "0.0232069000, 0.0265119000, 0.0365625000, 0.0672723000, 0.1676337000, 0.4899932000, 1.5058778000", \ - "0.0232223000, 0.0265313000, 0.0365790000, 0.0672684000, 0.1674700000, 0.4889963000, 1.5041239000", \ - "0.0233751000, 0.0266215000, 0.0365459000, 0.0671727000, 0.1675546000, 0.4897006000, 1.5076341000", \ - "0.0246066000, 0.0279835000, 0.0377929000, 0.0680833000, 0.1676664000, 0.4898038000, 1.5030110000", \ - "0.0275474000, 0.0309616000, 0.0405131000, 0.0700989000, 0.1684560000, 0.4887248000, 1.4967588000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4_1") { - leakage_power () { - value : 0.0003074000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0003203000; - when : "A&B&C&!D"; - } - leakage_power () { - value : 0.0010416000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0073078000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0003447000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0005666000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0003402000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0005377000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0003162000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0003404000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0003453000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0005602000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0003175000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0003445000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0003166000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0003486000; - when : "A&B&!C&!D"; - } - area : 7.5072000000; - cell_footprint : "sky130_fd_sc_hd__or4"; - cell_leakage_power : 0.0008534742; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016553000, 0.0016540000, 0.0016510000, 0.0016517000, 0.0016533000, 0.0016571000, 0.0016658000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001399300, -0.001416600, -0.001456400, -0.001461600, -0.001473500, -0.001500900, -0.001564000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015260000; - } - pin ("B") { - capacitance : 0.0017270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016300000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025635000, 0.0025374000, 0.0024770000, 0.0024780000, 0.0024801000, 0.0024850000, 0.0024962000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002027700, -0.002106600, -0.002288400, -0.002294500, -0.002308600, -0.002341200, -0.002416200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018250000; - } - pin ("C") { - capacitance : 0.0015200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016168000, 0.0016165000, 0.0016158000, 0.0016161000, 0.0016170000, 0.0016188000, 0.0016232000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001425700, -0.001457400, -0.001530500, -0.001533700, -0.001541100, -0.001558200, -0.001597700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016250000; - } - pin ("D") { - capacitance : 0.0013590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011941000, 0.0011938000, 0.0011930000, 0.0011967000, 0.0012054000, 0.0012254000, 0.0012714000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000765100, -0.000760100, -0.000748800, -0.000748500, -0.000747700, -0.000745900, -0.000741800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014510000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0109121000, 0.0097099000, 0.0067262000, -0.001278000, -0.024013500, -0.087173000, -0.255611500", \ - "0.0107541000, 0.0095472000, 0.0065842000, -0.001334600, -0.024162600, -0.087348400, -0.255760300", \ - "0.0106113000, 0.0093825000, 0.0064042000, -0.001472100, -0.024340900, -0.087508000, -0.255922500", \ - "0.0104335000, 0.0092542000, 0.0063073000, -0.001776900, -0.024525000, -0.087646900, -0.256063500", \ - "0.0103208000, 0.0091210000, 0.0061993000, -0.001805200, -0.024636400, -0.087813900, -0.256167300", \ - "0.0103372000, 0.0090971000, 0.0061569000, -0.001962200, -0.024749300, -0.087870100, -0.256245400", \ - "0.0124956000, 0.0109744000, 0.0072789000, -0.002135500, -0.024789700, -0.087842800, -0.256173500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0099395000, 0.0113885000, 0.0150928000, 0.0244033000, 0.0484065000, 0.1115206000, 0.2779743000", \ - "0.0099176000, 0.0113836000, 0.0150650000, 0.0243900000, 0.0484420000, 0.1114813000, 0.2792889000", \ - "0.0099138000, 0.0113662000, 0.0150595000, 0.0243634000, 0.0484181000, 0.1115233000, 0.2778842000", \ - "0.0098976000, 0.0113274000, 0.0149461000, 0.0242410000, 0.0485605000, 0.1114817000, 0.2792228000", \ - "0.0099319000, 0.0112788000, 0.0148875000, 0.0241156000, 0.0481971000, 0.1120004000, 0.2777790000", \ - "0.0105441000, 0.0118740000, 0.0153305000, 0.0241664000, 0.0483993000, 0.1117121000, 0.2776985000", \ - "0.0111034000, 0.0123899000, 0.0158532000, 0.0250001000, 0.0489617000, 0.1124185000, 0.2776323000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0098588000, 0.0086217000, 0.0057389000, -0.002352100, -0.025110900, -0.088164900, -0.256544500", \ - "0.0098628000, 0.0085825000, 0.0055990000, -0.002460700, -0.025230000, -0.088325000, -0.256646100", \ - "0.0096335000, 0.0084307000, 0.0055274000, -0.002432100, -0.025249900, -0.088427100, -0.256782100", \ - "0.0095058000, 0.0082805000, 0.0053716000, -0.002707300, -0.025421100, -0.088561800, -0.256904200", \ - "0.0093865000, 0.0082849000, 0.0053039000, -0.002793200, -0.025579000, -0.088692500, -0.256999700", \ - "0.0093656000, 0.0081604000, 0.0052091000, -0.002887600, -0.025702100, -0.088763300, -0.257068500", \ - "0.0111882000, 0.0096743000, 0.0059739000, -0.003214700, -0.025687000, -0.088688300, -0.256996400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0095931000, 0.0110569000, 0.0147811000, 0.0241877000, 0.0483574000, 0.1115156000, 0.2782006000", \ - "0.0096688000, 0.0111251000, 0.0148458000, 0.0242313000, 0.0484265000, 0.1116265000, 0.2781977000", \ - "0.0098073000, 0.0112610000, 0.0149641000, 0.0243482000, 0.0485518000, 0.1122670000, 0.2796013000", \ - "0.0097587000, 0.0111771000, 0.0147789000, 0.0241672000, 0.0484318000, 0.1122213000, 0.2795959000", \ - "0.0098198000, 0.0111098000, 0.0146443000, 0.0238836000, 0.0481962000, 0.1120207000, 0.2794095000", \ - "0.0100493000, 0.0113580000, 0.0148604000, 0.0239512000, 0.0481966000, 0.1116972000, 0.2777901000", \ - "0.0104915000, 0.0118435000, 0.0153293000, 0.0244337000, 0.0485818000, 0.1122526000, 0.2773596000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0089864000, 0.0077970000, 0.0048678000, -0.003236800, -0.025994500, -0.088972900, -0.257288900", \ - "0.0089899000, 0.0077367000, 0.0047551000, -0.003269300, -0.026087500, -0.089130600, -0.257420000", \ - "0.0086922000, 0.0074914000, 0.0045088000, -0.003347900, -0.026200900, -0.089299400, -0.257600200", \ - "0.0086415000, 0.0074490000, 0.0044888000, -0.003613400, -0.026395100, -0.089432500, -0.257708700", \ - "0.0084629000, 0.0072549000, 0.0043296000, -0.003746500, -0.026528500, -0.089532700, -0.257811100", \ - "0.0085810000, 0.0073565000, 0.0043955000, -0.003705400, -0.026555500, -0.089615900, -0.257882600", \ - "0.0103210000, 0.0088037000, 0.0050605000, -0.003914200, -0.026125900, -0.089274800, -0.257689300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0093976000, 0.0108371000, 0.0145102000, 0.0238771000, 0.0480721000, 0.1112239000, 0.2776094000", \ - "0.0094176000, 0.0108487000, 0.0145461000, 0.0239152000, 0.0482706000, 0.1113038000, 0.2776614000", \ - "0.0094602000, 0.0108861000, 0.0145580000, 0.0239263000, 0.0481316000, 0.1113254000, 0.2777022000", \ - "0.0094138000, 0.0108035000, 0.0143889000, 0.0237053000, 0.0479913000, 0.1112193000, 0.2776328000", \ - "0.0093349000, 0.0106599000, 0.0141530000, 0.0233612000, 0.0476202000, 0.1110129000, 0.2774472000", \ - "0.0094789000, 0.0107813000, 0.0143743000, 0.0234144000, 0.0475582000, 0.1104745000, 0.2787351000", \ - "0.0099638000, 0.0112485000, 0.0147254000, 0.0238174000, 0.0479692000, 0.1116219000, 0.2779458000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0082634000, 0.0070315000, 0.0040641000, -0.003910900, -0.026684200, -0.089696400, -0.257920100", \ - "0.0081330000, 0.0069239000, 0.0039973000, -0.004054300, -0.026814000, -0.089782000, -0.258014300", \ - "0.0080025000, 0.0067745000, 0.0037906000, -0.004169800, -0.026951400, -0.089935300, -0.258178800", \ - "0.0078799000, 0.0066499000, 0.0036812000, -0.004317800, -0.027085500, -0.090048600, -0.258292100", \ - "0.0078086000, 0.0066058000, 0.0036917000, -0.004368100, -0.027152000, -0.090134100, -0.258344100", \ - "0.0079574000, 0.0067656000, 0.0038346000, -0.004278100, -0.027041400, -0.090068600, -0.258289300", \ - "0.0110289000, 0.0094784000, 0.0056959000, -0.003790000, -0.026563900, -0.089614300, -0.257783100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0079863000, 0.0094211000, 0.0130753000, 0.0224664000, 0.0465616000, 0.1103718000, 0.2779002000", \ - "0.0079831000, 0.0093971000, 0.0130945000, 0.0224406000, 0.0466140000, 0.1099076000, 0.2764399000", \ - "0.0079387000, 0.0093519000, 0.0130136000, 0.0223812000, 0.0465124000, 0.1098043000, 0.2767194000", \ - "0.0078408000, 0.0092294000, 0.0128558000, 0.0221859000, 0.0464391000, 0.1097963000, 0.2765130000", \ - "0.0078338000, 0.0091462000, 0.0127132000, 0.0219700000, 0.0459715000, 0.1095323000, 0.2767062000", \ - "0.0079724000, 0.0092831000, 0.0128207000, 0.0218805000, 0.0461068000, 0.1094574000, 0.2775397000", \ - "0.0086061000, 0.0099093000, 0.0133494000, 0.0225514000, 0.0463540000, 0.1100679000, 0.2750760000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5027270000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4726730000, 0.4860969000, 0.5144944000, 0.5668270000, 0.6603589000, 0.8347756000, 1.2054368000", \ - "0.4731878000, 0.4865178000, 0.5149508000, 0.5670734000, 0.6612325000, 0.8352419000, 1.2059057000", \ - "0.4799254000, 0.4934159000, 0.5217802000, 0.5739773000, 0.6677743000, 0.8421424000, 1.2128379000", \ - "0.5021505000, 0.5160060000, 0.5439473000, 0.5961621000, 0.6890144000, 0.8643232000, 1.2349182000", \ - "0.5536240000, 0.5670847000, 0.5953994000, 0.6475578000, 0.7416793000, 0.9157337000, 1.2859803000", \ - "0.6621217000, 0.6760217000, 0.7040203000, 0.7561669000, 0.8504459000, 1.0250878000, 1.3953025000", \ - "0.8612859000, 0.8753001000, 0.9055435000, 0.9612016000, 1.0602438000, 1.2406074000, 1.6142505000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0658787000, 0.0724224000, 0.0877671000, 0.1245557000, 0.2183952000, 0.4622810000, 1.1061813000", \ - "0.0707742000, 0.0773918000, 0.0926502000, 0.1295238000, 0.2231349000, 0.4677346000, 1.1121329000", \ - "0.0825856000, 0.0891462000, 0.1043677000, 0.1411873000, 0.2350589000, 0.4788260000, 1.1228893000", \ - "0.1089161000, 0.1154404000, 0.1305770000, 0.1671259000, 0.2610614000, 0.5050214000, 1.1495807000", \ - "0.1488495000, 0.1561574000, 0.1720841000, 0.2089287000, 0.3026257000, 0.5475091000, 1.1895709000", \ - "0.1965089000, 0.2058067000, 0.2239498000, 0.2617335000, 0.3548631000, 0.5988772000, 1.2417719000", \ - "0.2323927000, 0.2447400000, 0.2685707000, 0.3119899000, 0.4049207000, 0.6486774000, 1.2903334000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0631159000, 0.0714255000, 0.0898447000, 0.1258577000, 0.1999014000, 0.3648442000, 0.7912239000", \ - "0.0629149000, 0.0712425000, 0.0898786000, 0.1271235000, 0.2010562000, 0.3658112000, 0.7914592000", \ - "0.0628362000, 0.0713554000, 0.0898239000, 0.1278355000, 0.1995943000, 0.3648547000, 0.7911852000", \ - "0.0630256000, 0.0718592000, 0.0899076000, 0.1260170000, 0.2003173000, 0.3650884000, 0.7905551000", \ - "0.0629804000, 0.0712309000, 0.0900649000, 0.1256091000, 0.1996365000, 0.3652282000, 0.7928180000", \ - "0.0629952000, 0.0713979000, 0.0908436000, 0.1263029000, 0.1995622000, 0.3643767000, 0.7914164000", \ - "0.0705707000, 0.0797828000, 0.0991547000, 0.1359732000, 0.2108696000, 0.3723945000, 0.7941947000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0213622000, 0.0283150000, 0.0465264000, 0.0957653000, 0.2277330000, 0.5751616000, 1.4910949000", \ - "0.0213086000, 0.0282551000, 0.0464469000, 0.0957086000, 0.2277345000, 0.5757583000, 1.4964849000", \ - "0.0211944000, 0.0280677000, 0.0463092000, 0.0957962000, 0.2277656000, 0.5753127000, 1.4921252000", \ - "0.0218199000, 0.0284290000, 0.0462968000, 0.0955213000, 0.2276533000, 0.5759886000, 1.4964773000", \ - "0.0259940000, 0.0322215000, 0.0488830000, 0.0962472000, 0.2273246000, 0.5751993000, 1.4962789000", \ - "0.0343285000, 0.0409871000, 0.0559705000, 0.0996494000, 0.2287448000, 0.5758818000, 1.4957000000", \ - "0.0480652000, 0.0554814000, 0.0707120000, 0.1098503000, 0.2304743000, 0.5784789000, 1.4911021000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4567774000, 0.4700480000, 0.4984272000, 0.5507855000, 0.6435268000, 0.8190271000, 1.1896241000", \ - "0.4564226000, 0.4702800000, 0.4983343000, 0.5508825000, 0.6447427000, 0.8188428000, 1.1893909000", \ - "0.4627141000, 0.4760562000, 0.5043495000, 0.5565524000, 0.6505488000, 0.8247769000, 1.1956113000", \ - "0.4842677000, 0.4976758000, 0.5260670000, 0.5783070000, 0.6721179000, 0.8463995000, 1.2172336000", \ - "0.5373787000, 0.5510730000, 0.5789655000, 0.6312051000, 0.7253236000, 0.8997581000, 1.2699582000", \ - "0.6556221000, 0.6693049000, 0.6971472000, 0.7494081000, 0.8434062000, 1.0182943000, 1.3886372000", \ - "0.8835213000, 0.8980600000, 0.9288542000, 0.9852806000, 1.0846278000, 1.2662716000, 1.6404754000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0668237000, 0.0734190000, 0.0888489000, 0.1257756000, 0.2197084000, 0.4635823000, 1.1070513000", \ - "0.0716419000, 0.0782223000, 0.0936284000, 0.1306407000, 0.2245845000, 0.4684024000, 1.1119098000", \ - "0.0833561000, 0.0899043000, 0.1051904000, 0.1420550000, 0.2357237000, 0.4811355000, 1.1249912000", \ - "0.1087821000, 0.1152942000, 0.1303865000, 0.1669548000, 0.2608182000, 0.5062338000, 1.1493553000", \ - "0.1467089000, 0.1539570000, 0.1696748000, 0.2062158000, 0.3000125000, 0.5458202000, 1.1896906000", \ - "0.1896427000, 0.1986852000, 0.2164145000, 0.2547068000, 0.3481518000, 0.5926159000, 1.2383123000", \ - "0.2180841000, 0.2301691000, 0.2542155000, 0.2970366000, 0.3905684000, 0.6357956000, 1.2775593000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0625655000, 0.0715542000, 0.0898115000, 0.1259807000, 0.2001267000, 0.3650329000, 0.7899366000", \ - "0.0629277000, 0.0722305000, 0.0908735000, 0.1267352000, 0.1989230000, 0.3643550000, 0.7922509000", \ - "0.0630755000, 0.0713387000, 0.0899767000, 0.1276211000, 0.2018684000, 0.3654038000, 0.7913293000", \ - "0.0627940000, 0.0712923000, 0.0898754000, 0.1257608000, 0.1994135000, 0.3651323000, 0.7912547000", \ - "0.0628580000, 0.0714754000, 0.0898862000, 0.1280190000, 0.1994860000, 0.3651864000, 0.7925526000", \ - "0.0627387000, 0.0715597000, 0.0898916000, 0.1257030000, 0.1985624000, 0.3643743000, 0.7934214000", \ - "0.0734440000, 0.0821532000, 0.1014195000, 0.1385250000, 0.2150887000, 0.3743993000, 0.7958844000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0207814000, 0.0275704000, 0.0454758000, 0.0947263000, 0.2266214000, 0.5753555000, 1.4970062000", \ - "0.0207483000, 0.0275433000, 0.0454603000, 0.0947326000, 0.2266783000, 0.5754126000, 1.4970509000", \ - "0.0206390000, 0.0274225000, 0.0454471000, 0.0945778000, 0.2265818000, 0.5748760000, 1.4974293000", \ - "0.0212644000, 0.0278817000, 0.0456947000, 0.0944065000, 0.2265361000, 0.5760589000, 1.4959046000", \ - "0.0255547000, 0.0316844000, 0.0484554000, 0.0960309000, 0.2265055000, 0.5753978000, 1.4978601000", \ - "0.0341794000, 0.0401490000, 0.0555853000, 0.0987062000, 0.2274265000, 0.5747408000, 1.4963301000", \ - "0.0476063000, 0.0551006000, 0.0703130000, 0.1099337000, 0.2295217000, 0.5786433000, 1.4935005000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4238629000, 0.4375488000, 0.4657061000, 0.5180901000, 0.6122409000, 0.7862722000, 1.1569754000", \ - "0.4235784000, 0.4375451000, 0.4655476000, 0.5179506000, 0.6118621000, 0.7860427000, 1.1564454000", \ - "0.4290886000, 0.4424305000, 0.4707661000, 0.5230626000, 0.6169329000, 0.7912443000, 1.1622131000", \ - "0.4503129000, 0.4641815000, 0.4920979000, 0.5444207000, 0.6383218000, 0.8125410000, 1.1830278000", \ - "0.5054264000, 0.5190255000, 0.5474279000, 0.5995212000, 0.6928431000, 0.8680400000, 1.2389196000", \ - "0.6386507000, 0.6522430000, 0.6801945000, 0.7322093000, 0.8261096000, 1.0010672000, 1.3715986000", \ - "0.8991583000, 0.9140655000, 0.9453786000, 1.0017737000, 1.1011629000, 1.2824330000, 1.6557832000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0647952000, 0.0712622000, 0.0863619000, 0.1228843000, 0.2163595000, 0.4604274000, 1.1029913000", \ - "0.0698068000, 0.0762816000, 0.0913648000, 0.1278234000, 0.2216531000, 0.4655327000, 1.1085235000", \ - "0.0812950000, 0.0877273000, 0.1027569000, 0.1392841000, 0.2328338000, 0.4771212000, 1.1200422000", \ - "0.1059465000, 0.1123937000, 0.1274355000, 0.1637590000, 0.2573841000, 0.5018231000, 1.1446610000", \ - "0.1417150000, 0.1489318000, 0.1645892000, 0.2013062000, 0.2949930000, 0.5392538000, 1.1816379000", \ - "0.1811483000, 0.1902262000, 0.2086800000, 0.2465822000, 0.3402993000, 0.5848142000, 1.2302234000", \ - "0.2029356000, 0.2153114000, 0.2399983000, 0.2831569000, 0.3771306000, 0.6229523000, 1.2634904000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0631833000, 0.0720334000, 0.0898148000, 0.1262685000, 0.1992465000, 0.3643239000, 0.7921721000", \ - "0.0629338000, 0.0712850000, 0.0895350000, 0.1259679000, 0.1988285000, 0.3656017000, 0.7933391000", \ - "0.0631030000, 0.0714010000, 0.0898261000, 0.1286055000, 0.1995660000, 0.3652628000, 0.7912584000", \ - "0.0628981000, 0.0712808000, 0.0896969000, 0.1282104000, 0.1988848000, 0.3654197000, 0.7936790000", \ - "0.0626790000, 0.0716889000, 0.0901619000, 0.1260839000, 0.2012482000, 0.3646076000, 0.7911129000", \ - "0.0627482000, 0.0716246000, 0.0901642000, 0.1262599000, 0.1987146000, 0.3649272000, 0.7935625000", \ - "0.0758988000, 0.0851562000, 0.1047571000, 0.1409895000, 0.2167464000, 0.3758848000, 0.7942733000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0201634000, 0.0268604000, 0.0448942000, 0.0938907000, 0.2265874000, 0.5751788000, 1.4940099000", \ - "0.0201988000, 0.0269204000, 0.0448303000, 0.0940292000, 0.2267101000, 0.5759435000, 1.4961700000", \ - "0.0201720000, 0.0268597000, 0.0448406000, 0.0939486000, 0.2266075000, 0.5755951000, 1.4955173000", \ - "0.0210744000, 0.0276131000, 0.0452381000, 0.0941564000, 0.2266458000, 0.5755120000, 1.4946913000", \ - "0.0252621000, 0.0315206000, 0.0481956000, 0.0955981000, 0.2263694000, 0.5743502000, 1.4920479000", \ - "0.0341470000, 0.0401648000, 0.0554344000, 0.0989596000, 0.2271946000, 0.5748194000, 1.4970949000", \ - "0.0485616000, 0.0558568000, 0.0723777000, 0.1112689000, 0.2299353000, 0.5780830000, 1.4931965000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3557542000, 0.3692957000, 0.3976655000, 0.4493567000, 0.5436664000, 0.7185493000, 1.0896849000", \ - "0.3558227000, 0.3692745000, 0.3976951000, 0.4499343000, 0.5433270000, 0.7186198000, 1.0897122000", \ - "0.3605304000, 0.3740356000, 0.4024228000, 0.4543305000, 0.5484526000, 0.7235229000, 1.0943405000", \ - "0.3813418000, 0.3948054000, 0.4230688000, 0.4751386000, 0.5691252000, 0.7444074000, 1.1150709000", \ - "0.4394758000, 0.4529444000, 0.4811297000, 0.5334734000, 0.6274549000, 0.8028276000, 1.1735385000", \ - "0.5806550000, 0.5941488000, 0.6218170000, 0.6741616000, 0.7662939000, 0.9408934000, 1.3115511000", \ - "0.8562462000, 0.8721317000, 0.9035543000, 0.9603593000, 1.0583679000, 1.2361536000, 1.6092613000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0612598000, 0.0677348000, 0.0828055000, 0.1193049000, 0.2128774000, 0.4576683000, 1.0988201000", \ - "0.0662437000, 0.0727273000, 0.0877929000, 0.1241584000, 0.2175829000, 0.4616641000, 1.1055460000", \ - "0.0780638000, 0.0845042000, 0.0995020000, 0.1359717000, 0.2298834000, 0.4737702000, 1.1194047000", \ - "0.1022661000, 0.1087617000, 0.1238426000, 0.1602351000, 0.2538013000, 0.4983717000, 1.1406840000", \ - "0.1371470000, 0.1444952000, 0.1605591000, 0.1974787000, 0.2907397000, 0.5351454000, 1.1773650000", \ - "0.1762305000, 0.1857450000, 0.2048215000, 0.2430194000, 0.3359884000, 0.5808841000, 1.2269719000", \ - "0.2001462000, 0.2130026000, 0.2385675000, 0.2842709000, 0.3771138000, 0.6212686000, 1.2641729000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0627098000, 0.0711806000, 0.0898557000, 0.1270831000, 0.2005324000, 0.3654436000, 0.7910205000", \ - "0.0630155000, 0.0717256000, 0.0900693000, 0.1260878000, 0.2010815000, 0.3645366000, 0.7910081000", \ - "0.0628790000, 0.0714326000, 0.0898180000, 0.1266573000, 0.1996792000, 0.3651397000, 0.7913026000", \ - "0.0627754000, 0.0712621000, 0.0898894000, 0.1262786000, 0.1991415000, 0.3648647000, 0.7910773000", \ - "0.0631209000, 0.0718995000, 0.0900253000, 0.1257887000, 0.1988344000, 0.3638974000, 0.7910587000", \ - "0.0619843000, 0.0705084000, 0.0901852000, 0.1263930000, 0.2013271000, 0.3652770000, 0.7937666000", \ - "0.0800619000, 0.0893090000, 0.1077542000, 0.1422176000, 0.2126539000, 0.3722060000, 0.7975808000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0200298000, 0.0266796000, 0.0445581000, 0.0936230000, 0.2264972000, 0.5751192000, 1.5027269000", \ - "0.0200562000, 0.0268008000, 0.0446634000, 0.0936984000, 0.2262583000, 0.5752820000, 1.4995486000", \ - "0.0200667000, 0.0267806000, 0.0446695000, 0.0937580000, 0.2259287000, 0.5762614000, 1.4985303000", \ - "0.0213960000, 0.0278603000, 0.0452695000, 0.0939787000, 0.2264840000, 0.5746850000, 1.5002883000", \ - "0.0261223000, 0.0322562000, 0.0484846000, 0.0952536000, 0.2262415000, 0.5761561000, 1.4995029000", \ - "0.0354230000, 0.0416070000, 0.0568654000, 0.0995057000, 0.2273588000, 0.5746003000, 1.4987397000", \ - "0.0511954000, 0.0590217000, 0.0752102000, 0.1131782000, 0.2305751000, 0.5766709000, 1.4913401000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4_2") { - leakage_power () { - value : 0.0014720000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0066049000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0007992000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0010088000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0007936000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0009749000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0007719000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0007943000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0007936000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0009732000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0007719000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0007942000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0007708000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0007985000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0007631000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0007748000; - when : "A&B&C&!D"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__or4"; - cell_leakage_power : 0.0012287270; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013440000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016668000, 0.0016616000, 0.0016495000, 0.0016502000, 0.0016518000, 0.0016555000, 0.0016641000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001406500, -0.001420700, -0.001453300, -0.001457500, -0.001467300, -0.001489800, -0.001541600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015060000; - } - pin ("B") { - capacitance : 0.0017160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0025479000, 0.0025273000, 0.0024796000, 0.0024798000, 0.0024803000, 0.0024813000, 0.0024838000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002200900, -0.002227700, -0.002289400, -0.002295200, -0.002308600, -0.002339400, -0.002410500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018080000; - } - pin ("C") { - capacitance : 0.0015080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016196000, 0.0016183000, 0.0016153000, 0.0016147000, 0.0016133000, 0.0016100000, 0.0016025000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001423800, -0.001454600, -0.001525600, -0.001528600, -0.001535600, -0.001551700, -0.001588800"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016070000; - } - pin ("D") { - capacitance : 0.0013490000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0012610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0011990000, 0.0011991000, 0.0011994000, 0.0012029000, 0.0012108000, 0.0012290000, 0.0012711000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000741300, -0.000743400, -0.000748400, -0.000747600, -0.000745600, -0.000741100, -0.000730700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014360000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0162834000, 0.0142774000, 0.0092716000, -0.003424500, -0.040264500, -0.151390300, -0.481449200", \ - "0.0161418000, 0.0141217000, 0.0091035000, -0.003558800, -0.040398800, -0.151314600, -0.481519600", \ - "0.0160642000, 0.0140457000, 0.0090277000, -0.003679400, -0.040514200, -0.151639500, -0.481670700", \ - "0.0158609000, 0.0138536000, 0.0088231000, -0.003897000, -0.040681800, -0.151818400, -0.481867800", \ - "0.0156719000, 0.0136589000, 0.0086593000, -0.004020800, -0.040825700, -0.151830500, -0.481993400", \ - "0.0156016000, 0.0136184000, 0.0085704000, -0.004102900, -0.040987800, -0.152028500, -0.482070400", \ - "0.0159005000, 0.0138446000, 0.0087447000, -0.003681500, -0.040794800, -0.152055800, -0.482084000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0149538000, 0.0166110000, 0.0214573000, 0.0350905000, 0.0737483000, 0.1853823000, 0.5114438000", \ - "0.0149304000, 0.0166190000, 0.0214212000, 0.0350332000, 0.0737205000, 0.1853555000, 0.5113994000", \ - "0.0149009000, 0.0165958000, 0.0214247000, 0.0349959000, 0.0736887000, 0.1851364000, 0.5137689000", \ - "0.0149513000, 0.0165757000, 0.0213536000, 0.0349253000, 0.0735552000, 0.1854553000, 0.5118325000", \ - "0.0149244000, 0.0165872000, 0.0213213000, 0.0346123000, 0.0732808000, 0.1852562000, 0.5123218000", \ - "0.0157636000, 0.0172788000, 0.0218383000, 0.0348721000, 0.0733523000, 0.1849570000, 0.5122961000", \ - "0.0166436000, 0.0181186000, 0.0224635000, 0.0357534000, 0.0737414000, 0.1864251000, 0.5114364000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0152376000, 0.0133436000, 0.0082816000, -0.004438700, -0.041211000, -0.152425800, -0.482649900", \ - "0.0152678000, 0.0132804000, 0.0082942000, -0.004415800, -0.041315600, -0.152354300, -0.482348500", \ - "0.0150314000, 0.0130149000, 0.0079920000, -0.004665000, -0.041516200, -0.152411800, -0.482522600", \ - "0.0148449000, 0.0128539000, 0.0078219000, -0.004906500, -0.041241500, -0.152582200, -0.482686000", \ - "0.0147354000, 0.0127298000, 0.0077239000, -0.004759500, -0.041603200, -0.152848800, -0.482800000", \ - "0.0146468000, 0.0126385000, 0.0076620000, -0.005065500, -0.041897300, -0.153012600, -0.482909700", \ - "0.0151319000, 0.0130908000, 0.0079300000, -0.004384500, -0.041552700, -0.152862800, -0.482871100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0147264000, 0.0164198000, 0.0212783000, 0.0349446000, 0.0738148000, 0.1866882000, 0.5132006000", \ - "0.0147308000, 0.0164184000, 0.0212936000, 0.0350055000, 0.0738745000, 0.1867534000, 0.5131483000", \ - "0.0147725000, 0.0164661000, 0.0213261000, 0.0349356000, 0.0738738000, 0.1857905000, 0.5128559000", \ - "0.0148409000, 0.0164979000, 0.0212686000, 0.0348816000, 0.0737036000, 0.1857501000, 0.5122391000", \ - "0.0147878000, 0.0163987000, 0.0210591000, 0.0345061000, 0.0732123000, 0.1858221000, 0.5148790000", \ - "0.0155086000, 0.0170328000, 0.0215739000, 0.0348479000, 0.0731084000, 0.1846225000, 0.5120470000", \ - "0.0162020000, 0.0176779000, 0.0220764000, 0.0351440000, 0.0737161000, 0.1862097000, 0.5130144000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0143000000, 0.0123149000, 0.0073037000, -0.005434700, -0.042217400, -0.153041900, -0.483105800", \ - "0.0142261000, 0.0122255000, 0.0072136000, -0.005487100, -0.041809900, -0.153185700, -0.483192000", \ - "0.0141011000, 0.0120795000, 0.0070553000, -0.005607700, -0.042451500, -0.153310700, -0.483405300", \ - "0.0138758000, 0.0119003000, 0.0068722000, -0.005827100, -0.042199400, -0.153507800, -0.483488200", \ - "0.0138921000, 0.0118571000, 0.0068651000, -0.005876600, -0.042573200, -0.153721100, -0.483717200", \ - "0.0137054000, 0.0117147000, 0.0066938000, -0.005984800, -0.042828700, -0.153894300, -0.483813800", \ - "0.0144385000, 0.0123623000, 0.0071888000, -0.005667800, -0.042600900, -0.153838100, -0.483649600"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0143754000, 0.0160719000, 0.0208416000, 0.0344482000, 0.0733585000, 0.1853477000, 0.5145791000", \ - "0.0143559000, 0.0160395000, 0.0208829000, 0.0345492000, 0.0733687000, 0.1856930000, 0.5145618000", \ - "0.0144167000, 0.0161077000, 0.0209284000, 0.0345431000, 0.0734155000, 0.1857538000, 0.5145214000", \ - "0.0144562000, 0.0161238000, 0.0208762000, 0.0343048000, 0.0732292000, 0.1856026000, 0.5145080000", \ - "0.0144291000, 0.0160306000, 0.0207556000, 0.0339810000, 0.0727973000, 0.1860674000, 0.5117642000", \ - "0.0147844000, 0.0164080000, 0.0209384000, 0.0342199000, 0.0726547000, 0.1843745000, 0.5120438000", \ - "0.0155853000, 0.0170750000, 0.0214068000, 0.0346256000, 0.0730990000, 0.1855052000, 0.5101303000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0135979000, 0.0115770000, 0.0065641000, -0.006187500, -0.042958400, -0.153711800, -0.483776600", \ - "0.0134744000, 0.0114723000, 0.0064711000, -0.006203600, -0.042994800, -0.154009700, -0.483884400", \ - "0.0135196000, 0.0115163000, 0.0065832000, -0.006198200, -0.043036300, -0.154117300, -0.484034500", \ - "0.0132703000, 0.0112470000, 0.0062675000, -0.006431400, -0.043263200, -0.154307000, -0.484216600", \ - "0.0131523000, 0.0111333000, 0.0061025000, -0.006470400, -0.043330600, -0.154352000, -0.484267500", \ - "0.0131962000, 0.0111917000, 0.0061674000, -0.006544900, -0.043372300, -0.154390600, -0.484241000", \ - "0.0148003000, 0.0127214000, 0.0074908000, -0.005437600, -0.042686900, -0.153943700, -0.483768300"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014603460, 0.0042652220, 0.0124574000, 0.0363842400, 0.1062672000, 0.3103737000"); - values("0.0128871000, 0.0145715000, 0.0194134000, 0.0330324000, 0.0719639000, 0.1841811000, 0.5139629000", \ - "0.0129336000, 0.0146347000, 0.0194373000, 0.0330971000, 0.0719398000, 0.1849872000, 0.5113630000", \ - "0.0128948000, 0.0145743000, 0.0194104000, 0.0330993000, 0.0719241000, 0.1839949000, 0.5117389000", \ - "0.0129386000, 0.0145229000, 0.0192954000, 0.0328888000, 0.0717427000, 0.1841817000, 0.5138360000", \ - "0.0130238000, 0.0145995000, 0.0193414000, 0.0324562000, 0.0712201000, 0.1846752000, 0.5114542000", \ - "0.0134274000, 0.0149622000, 0.0194875000, 0.0328302000, 0.0709512000, 0.1824250000, 0.5110884000", \ - "0.0142772000, 0.0157404000, 0.0201522000, 0.0333818000, 0.0716157000, 0.1835997000, 0.5089819000"); - } - } - max_capacitance : 0.3103740000; - max_transition : 1.5064190000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.6186276000, 0.6307866000, 0.6579690000, 0.7127239000, 0.8134548000, 0.9994997000, 1.3816612000", \ - "0.6202702000, 0.6323742000, 0.6592485000, 0.7143839000, 0.8150930000, 0.9994554000, 1.3835183000", \ - "0.6277924000, 0.6398426000, 0.6669832000, 0.7216990000, 0.8225328000, 1.0085327000, 1.3908121000", \ - "0.6492636000, 0.6612692000, 0.6883527000, 0.7430954000, 0.8435809000, 1.0298812000, 1.4121345000", \ - "0.7005506000, 0.7124036000, 0.7397644000, 0.7945740000, 0.8948494000, 1.0795899000, 1.4635257000", \ - "0.8105868000, 0.8228128000, 0.8495023000, 0.9043566000, 1.0048103000, 1.1907594000, 1.5746988000", \ - "1.0341429000, 1.0464608000, 1.0741739000, 1.1314146000, 1.2345710000, 1.4215702000, 1.8070693000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0779247000, 0.0832849000, 0.0961643000, 0.1269952000, 0.2085218000, 0.4422037000, 1.1212551000", \ - "0.0827645000, 0.0881569000, 0.1009652000, 0.1317550000, 0.2133479000, 0.4469931000, 1.1260817000", \ - "0.0943151000, 0.0996328000, 0.1124662000, 0.1432012000, 0.2246954000, 0.4584488000, 1.1378969000", \ - "0.1214924000, 0.1266574000, 0.1393162000, 0.1697768000, 0.2513911000, 0.4850548000, 1.1656459000", \ - "0.1684006000, 0.1744212000, 0.1882914000, 0.2195459000, 0.3008719000, 0.5349534000, 1.2129361000", \ - "0.2269288000, 0.2347754000, 0.2518814000, 0.2858533000, 0.3677383000, 0.6010295000, 1.2807054000", \ - "0.2798168000, 0.2904408000, 0.3129098000, 0.3547621000, 0.4402641000, 0.6720634000, 1.3498820000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0845714000, 0.0911852000, 0.1075676000, 0.1425953000, 0.2096679000, 0.3614143000, 0.7670944000", \ - "0.0846415000, 0.0912068000, 0.1072345000, 0.1408358000, 0.2088565000, 0.3635215000, 0.7656444000", \ - "0.0846330000, 0.0911814000, 0.1075832000, 0.1425501000, 0.2097246000, 0.3612680000, 0.7670550000", \ - "0.0846391000, 0.0911895000, 0.1073763000, 0.1425400000, 0.2094026000, 0.3614534000, 0.7667909000", \ - "0.0845926000, 0.0908022000, 0.1077887000, 0.1417616000, 0.2089922000, 0.3628290000, 0.7659923000", \ - "0.0846065000, 0.0910819000, 0.1077022000, 0.1413241000, 0.2083099000, 0.3629135000, 0.7663026000", \ - "0.0916499000, 0.0983091000, 0.1140036000, 0.1502936000, 0.2162322000, 0.3680322000, 0.7686423000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0199036000, 0.0245855000, 0.0373516000, 0.0746266000, 0.1876706000, 0.5218462000, 1.4995571000", \ - "0.0198383000, 0.0244546000, 0.0373458000, 0.0744549000, 0.1876436000, 0.5218213000, 1.4994437000", \ - "0.0198539000, 0.0244731000, 0.0371163000, 0.0743909000, 0.1874575000, 0.5213878000, 1.4973524000", \ - "0.0198268000, 0.0244728000, 0.0371492000, 0.0742708000, 0.1869811000, 0.5214044000, 1.5000835000", \ - "0.0246072000, 0.0290422000, 0.0409375000, 0.0760515000, 0.1873653000, 0.5222356000, 1.5012606000", \ - "0.0338586000, 0.0383647000, 0.0506630000, 0.0824617000, 0.1893871000, 0.5213059000, 1.4999949000", \ - "0.0479140000, 0.0543439000, 0.0679684000, 0.0998314000, 0.1952615000, 0.5238426000, 1.4973957000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.6023272000, 0.6143631000, 0.6415718000, 0.6963189000, 0.7969320000, 0.9831358000, 1.3654189000", \ - "0.6032181000, 0.6151118000, 0.6426096000, 0.6973035000, 0.7984760000, 0.9838539000, 1.3663779000", \ - "0.6097936000, 0.6218853000, 0.6486433000, 0.7036855000, 0.8043747000, 0.9889025000, 1.3729514000", \ - "0.6308412000, 0.6426461000, 0.6696088000, 0.7244393000, 0.8247610000, 1.0103491000, 1.3935958000", \ - "0.6830973000, 0.6949885000, 0.7217330000, 0.7766663000, 0.8772543000, 1.0627879000, 1.4460996000", \ - "0.8015580000, 0.8135300000, 0.8408452000, 0.8953057000, 0.9957016000, 1.1816367000, 1.5657978000", \ - "1.0577155000, 1.0700384000, 1.0980941000, 1.1552118000, 1.2588310000, 1.4460314000, 1.8319104000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0786446000, 0.0839762000, 0.0967304000, 0.1274317000, 0.2088128000, 0.4430097000, 1.1210847000", \ - "0.0833718000, 0.0887008000, 0.1014557000, 0.1321728000, 0.2136144000, 0.4476662000, 1.1262700000", \ - "0.0949475000, 0.1002323000, 0.1129680000, 0.1435977000, 0.2249367000, 0.4592424000, 1.1374005000", \ - "0.1212455000, 0.1264400000, 0.1390205000, 0.1694019000, 0.2506672000, 0.4851100000, 1.1621747000", \ - "0.1671868000, 0.1731918000, 0.1867803000, 0.2180511000, 0.2994207000, 0.5332232000, 1.2134385000", \ - "0.2226528000, 0.2304230000, 0.2473931000, 0.2813894000, 0.3634277000, 0.5968103000, 1.2788863000", \ - "0.2701259000, 0.2806477000, 0.3032862000, 0.3458204000, 0.4313128000, 0.6635259000, 1.3416619000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0846325000, 0.0911515000, 0.1075567000, 0.1426066000, 0.2095410000, 0.3613906000, 0.7670736000", \ - "0.0844722000, 0.0911750000, 0.1080761000, 0.1428028000, 0.2118736000, 0.3627225000, 0.7669133000", \ - "0.0846965000, 0.0912864000, 0.1071908000, 0.1408524000, 0.2089952000, 0.3630831000, 0.7660724000", \ - "0.0843637000, 0.0907379000, 0.1072677000, 0.1409464000, 0.2099470000, 0.3634115000, 0.7651519000", \ - "0.0844687000, 0.0911244000, 0.1066939000, 0.1413192000, 0.2082465000, 0.3608406000, 0.7665406000", \ - "0.0846289000, 0.0907888000, 0.1079917000, 0.1430469000, 0.2091804000, 0.3604649000, 0.7650127000", \ - "0.0929271000, 0.0994584000, 0.1156677000, 0.1497231000, 0.2170282000, 0.3675806000, 0.7692144000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0194300000, 0.0240337000, 0.0365564000, 0.0736360000, 0.1865543000, 0.5217106000, 1.5015590000", \ - "0.0194970000, 0.0239321000, 0.0364757000, 0.0734456000, 0.1865230000, 0.5213106000, 1.5017994000", \ - "0.0193857000, 0.0239228000, 0.0364137000, 0.0735855000, 0.1865576000, 0.5217816000, 1.5016509000", \ - "0.0195257000, 0.0240052000, 0.0365112000, 0.0734667000, 0.1865063000, 0.5217495000, 1.5003113000", \ - "0.0242521000, 0.0284527000, 0.0406188000, 0.0753162000, 0.1864774000, 0.5218225000, 1.5013470000", \ - "0.0334411000, 0.0381278000, 0.0497443000, 0.0820652000, 0.1882567000, 0.5211814000, 1.5014371000", \ - "0.0479120000, 0.0541711000, 0.0677227000, 0.0987903000, 0.1953338000, 0.5239947000, 1.4959505000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.5688825000, 0.5807188000, 0.6077020000, 0.6627494000, 0.7634907000, 0.9486566000, 1.3318574000", \ - "0.5697300000, 0.5816732000, 0.6084957000, 0.6636301000, 0.7639057000, 0.9498571000, 1.3328678000", \ - "0.5756284000, 0.5876742000, 0.6145029000, 0.6695483000, 0.7700791000, 0.9546858000, 1.3387954000", \ - "0.5961242000, 0.6080211000, 0.6348515000, 0.6898777000, 0.7902178000, 0.9759809000, 1.3590346000", \ - "0.6504206000, 0.6623903000, 0.6895954000, 0.7444286000, 0.8452687000, 1.0308150000, 1.4140461000", \ - "0.7841435000, 0.7961425000, 0.8231895000, 0.8777043000, 0.9786965000, 1.1649134000, 1.5483052000", \ - "1.0761819000, 1.0887005000, 1.1171395000, 1.1743515000, 1.2783902000, 1.4647522000, 1.8492053000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0763993000, 0.0816067000, 0.0941465000, 0.1245801000, 0.2059260000, 0.4397752000, 1.1177052000", \ - "0.0812147000, 0.0864281000, 0.0990825000, 0.1295132000, 0.2109117000, 0.4437293000, 1.1241044000", \ - "0.0925989000, 0.0977866000, 0.1103903000, 0.1407451000, 0.2221616000, 0.4551493000, 1.1362302000", \ - "0.1191722000, 0.1243744000, 0.1368727000, 0.1669577000, 0.2483571000, 0.4813439000, 1.1622329000", \ - "0.1628343000, 0.1689390000, 0.1825181000, 0.2136603000, 0.2950066000, 0.5284553000, 1.2068698000", \ - "0.2158111000, 0.2235327000, 0.2404876000, 0.2749121000, 0.3569465000, 0.5895314000, 1.2690068000", \ - "0.2589391000, 0.2695378000, 0.2926025000, 0.3356868000, 0.4211865000, 0.6533522000, 1.3316053000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0850784000, 0.0913760000, 0.1071729000, 0.1408234000, 0.2082470000, 0.3630679000, 0.7642466000", \ - "0.0844239000, 0.0910566000, 0.1066998000, 0.1409808000, 0.2099857000, 0.3608229000, 0.7656740000", \ - "0.0846302000, 0.0911714000, 0.1072755000, 0.1408134000, 0.2090879000, 0.3632389000, 0.7659230000", \ - "0.0847711000, 0.0914343000, 0.1067066000, 0.1408428000, 0.2094906000, 0.3608192000, 0.7657784000", \ - "0.0846047000, 0.0913287000, 0.1072923000, 0.1423296000, 0.2119815000, 0.3620824000, 0.7652480000", \ - "0.0846522000, 0.0911515000, 0.1079547000, 0.1428762000, 0.2097882000, 0.3613823000, 0.7653500000", \ - "0.0939118000, 0.1006146000, 0.1167009000, 0.1510091000, 0.2161931000, 0.3659997000, 0.7689521000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0190097000, 0.0234812000, 0.0360472000, 0.0729868000, 0.1862020000, 0.5220817000, 1.5001772000", \ - "0.0189427000, 0.0235685000, 0.0361093000, 0.0730879000, 0.1857265000, 0.5211583000, 1.5025796000", \ - "0.0189946000, 0.0235140000, 0.0360773000, 0.0728746000, 0.1857633000, 0.5216966000, 1.5031121000", \ - "0.0192691000, 0.0237525000, 0.0362066000, 0.0731679000, 0.1862148000, 0.5210777000, 1.5031738000", \ - "0.0243307000, 0.0284182000, 0.0403183000, 0.0754802000, 0.1865001000, 0.5214852000, 1.5005117000", \ - "0.0336657000, 0.0390757000, 0.0501936000, 0.0824611000, 0.1886703000, 0.5203006000, 1.5017166000", \ - "0.0481005000, 0.0551891000, 0.0687345000, 0.1001551000, 0.1954795000, 0.5223004000, 1.4988848000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.5001209000, 0.5117475000, 0.5388029000, 0.5938098000, 0.6944599000, 0.8788348000, 1.2631423000", \ - "0.5009386000, 0.5128171000, 0.5399459000, 0.5950898000, 0.6954036000, 0.8814997000, 1.2640278000", \ - "0.5064815000, 0.5182493000, 0.5452714000, 0.6003998000, 0.7013159000, 0.8870554000, 1.2695034000", \ - "0.5262513000, 0.5382198000, 0.5655061000, 0.6204084000, 0.7206608000, 0.9070378000, 1.2899094000", \ - "0.5831129000, 0.5947612000, 0.6216605000, 0.6765813000, 0.7772115000, 0.9630238000, 1.3468070000", \ - "0.7210740000, 0.7332806000, 0.7605163000, 0.8148549000, 0.9161220000, 1.1016876000, 1.4857104000", \ - "1.0345811000, 1.0467511000, 1.0757191000, 1.1324991000, 1.2349565000, 1.4216786000, 1.8040512000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0731398000, 0.0784008000, 0.0911020000, 0.1215096000, 0.2026464000, 0.4359106000, 1.1148878000", \ - "0.0782044000, 0.0834944000, 0.0961257000, 0.1266560000, 0.2079903000, 0.4412471000, 1.1227778000", \ - "0.0896822000, 0.0949675000, 0.1076296000, 0.1380521000, 0.2193099000, 0.4522260000, 1.1339046000", \ - "0.1166247000, 0.1216692000, 0.1343102000, 0.1646138000, 0.2459447000, 0.4788442000, 1.1626023000", \ - "0.1604275000, 0.1665555000, 0.1805731000, 0.2117771000, 0.2927504000, 0.5264977000, 1.2043436000", \ - "0.2139148000, 0.2220839000, 0.2395973000, 0.2746470000, 0.3561632000, 0.5894715000, 1.2726370000", \ - "0.2615347000, 0.2727028000, 0.2962759000, 0.3409857000, 0.4264255000, 0.6595839000, 1.3364284000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0846339000, 0.0912426000, 0.1071771000, 0.1408681000, 0.2081606000, 0.3634627000, 0.7653722000", \ - "0.0846527000, 0.0908239000, 0.1074928000, 0.1416860000, 0.2090974000, 0.3621708000, 0.7657995000", \ - "0.0849214000, 0.0912772000, 0.1067564000, 0.1404894000, 0.2121623000, 0.3620492000, 0.7668154000", \ - "0.0846143000, 0.0910686000, 0.1074356000, 0.1418264000, 0.2092521000, 0.3610991000, 0.7655083000", \ - "0.0843992000, 0.0912815000, 0.1066043000, 0.1415817000, 0.2090089000, 0.3628946000, 0.7648804000", \ - "0.0847410000, 0.0913283000, 0.1069718000, 0.1406786000, 0.2106587000, 0.3619519000, 0.7650645000", \ - "0.0970531000, 0.1035805000, 0.1187924000, 0.1513640000, 0.2165376000, 0.3665896000, 0.7684619000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014603500, 0.0042652200, 0.0124574000, 0.0363842000, 0.1062670000, 0.3103740000"); - values("0.0190465000, 0.0236335000, 0.0360982000, 0.0729718000, 0.1858464000, 0.5217967000, 1.5064192000", \ - "0.0189946000, 0.0235541000, 0.0361350000, 0.0731094000, 0.1860093000, 0.5227526000, 1.5012688000", \ - "0.0191026000, 0.0235734000, 0.0361488000, 0.0729785000, 0.1857656000, 0.5210387000, 1.5049638000", \ - "0.0194390000, 0.0241224000, 0.0365688000, 0.0732499000, 0.1857884000, 0.5217244000, 1.5055095000", \ - "0.0248404000, 0.0291216000, 0.0408753000, 0.0761487000, 0.1862563000, 0.5227545000, 1.5050001000", \ - "0.0349460000, 0.0396576000, 0.0512664000, 0.0829859000, 0.1884607000, 0.5208740000, 1.5049454000", \ - "0.0507602000, 0.0573384000, 0.0715114000, 0.1029222000, 0.1963184000, 0.5221428000, 1.4997051000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4_4") { - leakage_power () { - value : 0.0040669000; - when : "!A&!B&!C&D"; - } - leakage_power () { - value : 0.0059004000; - when : "!A&!B&!C&!D"; - } - leakage_power () { - value : 0.0019956000; - when : "!A&!B&C&D"; - } - leakage_power () { - value : 0.0024239000; - when : "!A&!B&C&!D"; - } - leakage_power () { - value : 0.0019875000; - when : "!A&B&!C&D"; - } - leakage_power () { - value : 0.0023181000; - when : "!A&B&!C&!D"; - } - leakage_power () { - value : 0.0019676000; - when : "!A&B&C&D"; - } - leakage_power () { - value : 0.0019889000; - when : "!A&B&C&!D"; - } - leakage_power () { - value : 0.0019855000; - when : "A&!B&!C&D"; - } - leakage_power () { - value : 0.0022894000; - when : "A&!B&!C&!D"; - } - leakage_power () { - value : 0.0019669000; - when : "A&!B&C&D"; - } - leakage_power () { - value : 0.0019870000; - when : "A&!B&C&!D"; - } - leakage_power () { - value : 0.0019657000; - when : "A&B&!C&D"; - } - leakage_power () { - value : 0.0019915000; - when : "A&B&!C&!D"; - } - leakage_power () { - value : 0.0019594000; - when : "A&B&C&D"; - } - leakage_power () { - value : 0.0019700000; - when : "A&B&C&!D"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__or4"; - cell_leakage_power : 0.0024227670; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022400000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039518000, 0.0039475000, 0.0039376000, 0.0039377000, 0.0039379000, 0.0039382000, 0.0039390000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003309400, -0.003343200, -0.003421000, -0.003436800, -0.003473200, -0.003557100, -0.003750600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024930000; - } - pin ("B") { - capacitance : 0.0024510000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023070000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040186000, 0.0040153000, 0.0040077000, 0.0040091000, 0.0040126000, 0.0040205000, 0.0040387000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003348100, -0.003388100, -0.003480200, -0.003498100, -0.003539300, -0.003634300, -0.003853300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025950000; - } - pin ("C") { - capacitance : 0.0024460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039025000, 0.0039009000, 0.0038971000, 0.0038971000, 0.0038971000, 0.0038970000, 0.0038968000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003453500, -0.003528400, -0.003701000, -0.003710500, -0.003732600, -0.003783600, -0.003900900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026250000; - } - pin ("D") { - capacitance : 0.0023000000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0020960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027252000, 0.0027229000, 0.0027176000, 0.0027245000, 0.0027405000, 0.0027774000, 0.0028624000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001701400, -0.001707500, -0.001721600, -0.001719700, -0.001715100, -0.001704700, -0.001680600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025030000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (D)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0281561000, 0.0258964000, 0.0194889000, 0.0028612000, -0.051366200, -0.233357500, -0.827457000", \ - "0.0279853000, 0.0260372000, 0.0199057000, 0.0028668000, -0.051556900, -0.233500000, -0.827545200", \ - "0.0277519000, 0.0255106000, 0.0191379000, 0.0019609000, -0.052106300, -0.233580300, -0.827619500", \ - "0.0275254000, 0.0253560000, 0.0189731000, 0.0017489000, -0.052336500, -0.233867100, -0.827809400", \ - "0.0273720000, 0.0251337000, 0.0187386000, 0.0016520000, -0.052571800, -0.234077900, -0.827979900", \ - "0.0272004000, 0.0250030000, 0.0185773000, 0.0016318000, -0.052675300, -0.234254000, -0.828176400", \ - "0.0300004000, 0.0276878000, 0.0207812000, 0.0014401000, -0.052550200, -0.234194200, -0.828165600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0301260000, 0.0320327000, 0.0382112000, 0.0570218000, 0.1155306000, 0.2997719000, 0.8919592000", \ - "0.0300449000, 0.0319652000, 0.0381315000, 0.0569621000, 0.1154608000, 0.2995145000, 0.8918918000", \ - "0.0299583000, 0.0319142000, 0.0380548000, 0.0569785000, 0.1154684000, 0.2996341000, 0.8878506000", \ - "0.0300454000, 0.0319525000, 0.0380916000, 0.0569593000, 0.1154251000, 0.2993898000, 0.8907827000", \ - "0.0303407000, 0.0322191000, 0.0381150000, 0.0567990000, 0.1147463000, 0.2991823000, 0.8870623000", \ - "0.0316833000, 0.0334555000, 0.0391418000, 0.0572759000, 0.1149322000, 0.2988419000, 0.8917020000", \ - "0.0339688000, 0.0356818000, 0.0412768000, 0.0590525000, 0.1162392000, 0.3005466000, 0.8868471000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0257908000, 0.0235337000, 0.0171833000, 2.360000e-05, -0.053803800, -0.235620700, -0.829523200", \ - "0.0256845000, 0.0234661000, 0.0170554000, 3.930000e-05, -0.054147800, -0.235634300, -0.829490900", \ - "0.0254924000, 0.0232151000, 0.0168632000, -0.000264000, -0.054450400, -0.235855800, -0.829637500", \ - "0.0254946000, 0.0232718000, 0.0166856000, -0.000532400, -0.054283600, -0.236089800, -0.829846700", \ - "0.0251463000, 0.0229334000, 0.0167290000, -0.000646100, -0.054688600, -0.236263300, -0.830120600", \ - "0.0250672000, 0.0228831000, 0.0165079000, -0.000657800, -0.054976900, -0.236561800, -0.830304500", \ - "0.0272180000, 0.0248852000, 0.0180480000, -0.000665500, -0.055003700, -0.236213800, -0.830103700"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0295149000, 0.0314358000, 0.0375994000, 0.0565027000, 0.1155496000, 0.3006517000, 0.8879528000", \ - "0.0294803000, 0.0314377000, 0.0374899000, 0.0566443000, 0.1156075000, 0.3003705000, 0.8930446000", \ - "0.0294624000, 0.0313724000, 0.0375183000, 0.0565743000, 0.1155166000, 0.3002252000, 0.8898807000", \ - "0.0296273000, 0.0315587000, 0.0376343000, 0.0565269000, 0.1152537000, 0.2998312000, 0.8929266000", \ - "0.0294528000, 0.0313574000, 0.0372796000, 0.0558767000, 0.1143629000, 0.3000185000, 0.8926754000", \ - "0.0309538000, 0.0327268000, 0.0384004000, 0.0567040000, 0.1140024000, 0.2986259000, 0.8881437000", \ - "0.0323164000, 0.0339692000, 0.0395959000, 0.0574653000, 0.1153879000, 0.3001500000, 0.8873850000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0238491000, 0.0216851000, 0.0152488000, -0.001934300, -0.055986100, -0.237295400, -0.831018200", \ - "0.0237788000, 0.0215888000, 0.0151598000, -0.001926300, -0.056094400, -0.237394500, -0.831122900", \ - "0.0236100000, 0.0213929000, 0.0149644000, -0.002120600, -0.056287900, -0.237583100, -0.831299000", \ - "0.0233569000, 0.0210661000, 0.0147333000, -0.002230100, -0.056396900, -0.237870200, -0.831531100", \ - "0.0232301000, 0.0209007000, 0.0145104000, -0.002119600, -0.056449900, -0.238140000, -0.831841900", \ - "0.0233786000, 0.0210886000, 0.0147123000, -0.002468800, -0.056737600, -0.238339100, -0.832064700", \ - "0.0254079000, 0.0230868000, 0.0161443000, -0.002347600, -0.056792900, -0.238374200, -0.831431900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0284754000, 0.0304019000, 0.0365329000, 0.0554128000, 0.1143389000, 0.2993861000, 0.8916833000", \ - "0.0285399000, 0.0304594000, 0.0366037000, 0.0554966000, 0.1143525000, 0.2992063000, 0.8885622000", \ - "0.0285983000, 0.0305269000, 0.0366003000, 0.0556402000, 0.1145254000, 0.2996357000, 0.8920419000", \ - "0.0286762000, 0.0305737000, 0.0366257000, 0.0554808000, 0.1141634000, 0.2992072000, 0.8869599000", \ - "0.0287702000, 0.0306153000, 0.0365412000, 0.0548548000, 0.1134861000, 0.2985847000, 0.8883737000", \ - "0.0298474000, 0.0316160000, 0.0372719000, 0.0555087000, 0.1132057000, 0.2971369000, 0.8911575000", \ - "0.0309319000, 0.0326170000, 0.0381467000, 0.0560190000, 0.1139959000, 0.2981307000, 0.8888828000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0228270000, 0.0205962000, 0.0143258000, -0.002766500, -0.056954800, -0.238389800, -0.832015800", \ - "0.0226854000, 0.0204672000, 0.0140755000, -0.003051700, -0.057203100, -0.238515400, -0.832005900", \ - "0.0223535000, 0.0201483000, 0.0138138000, -0.003379000, -0.057331200, -0.238736000, -0.832406300", \ - "0.0222538000, 0.0200129000, 0.0136475000, -0.003483200, -0.057655200, -0.239001300, -0.832454400", \ - "0.0219723000, 0.0197989000, 0.0133941000, -0.003687400, -0.057869600, -0.239219300, -0.832807900", \ - "0.0223065000, 0.0200925000, 0.0136969000, -0.003145800, -0.057488100, -0.238996700, -0.832662200", \ - "0.0290203000, 0.0265881000, 0.0194381000, -0.000584800, -0.056388500, -0.238071000, -0.831623100"); - } - related_pin : "D"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015989090, 0.0051130190, 0.0163505000, 0.0522859200, 0.1672008000, 0.5346778000"); - values("0.0250182000, 0.0269475000, 0.0329997000, 0.0520989000, 0.1112281000, 0.2963141000, 0.8897799000", \ - "0.0249971000, 0.0269450000, 0.0330643000, 0.0522537000, 0.1111654000, 0.2964007000, 0.8827494000", \ - "0.0249411000, 0.0268849000, 0.0329996000, 0.0521537000, 0.1111267000, 0.2958377000, 0.8866489000", \ - "0.0249543000, 0.0268575000, 0.0329618000, 0.0518477000, 0.1106497000, 0.2957795000, 0.8830836000", \ - "0.0249898000, 0.0268378000, 0.0326264000, 0.0510261000, 0.1096715000, 0.2947796000, 0.8862220000", \ - "0.0257524000, 0.0275208000, 0.0332088000, 0.0518321000, 0.1096442000, 0.2929823000, 0.8850457000", \ - "0.0274773000, 0.0289880000, 0.0345559000, 0.0522320000, 0.1103551000, 0.2947956000, 0.8820250000"); - } - } - max_capacitance : 0.5346780000; - max_transition : 1.5078210000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.4914132000, 0.4982088000, 0.5162480000, 0.5564371000, 0.6363137000, 0.7936776000, 1.1470217000", \ - "0.4954120000, 0.5022173000, 0.5203575000, 0.5605744000, 0.6407498000, 0.7976570000, 1.1511713000", \ - "0.5061124000, 0.5130667000, 0.5305983000, 0.5711051000, 0.6511199000, 0.8078365000, 1.1621484000", \ - "0.5314365000, 0.5384135000, 0.5563630000, 0.5962234000, 0.6761890000, 0.8328743000, 1.1872786000", \ - "0.5873011000, 0.5941201000, 0.6115942000, 0.6520635000, 0.7318983000, 0.8887763000, 1.2432230000", \ - "0.7038614000, 0.7106193000, 0.7283524000, 0.7692376000, 0.8495202000, 1.0071419000, 1.3610394000", \ - "0.9354281000, 0.9425728000, 0.9609944000, 1.0037359000, 1.0865630000, 1.2485422000, 1.6055099000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0876665000, 0.0914850000, 0.1018409000, 0.1282909000, 0.2016966000, 0.4268333000, 1.1413070000", \ - "0.0922595000, 0.0960948000, 0.1064385000, 0.1328672000, 0.2062900000, 0.4314621000, 1.1452620000", \ - "0.1032796000, 0.1071288000, 0.1174100000, 0.1438671000, 0.2173836000, 0.4424535000, 1.1548764000", \ - "0.1300736000, 0.1338521000, 0.1440402000, 0.1701876000, 0.2427525000, 0.4678474000, 1.1817560000", \ - "0.1793437000, 0.1835504000, 0.1943527000, 0.2211278000, 0.2937061000, 0.5187229000, 1.2318099000", \ - "0.2397252000, 0.2451299000, 0.2585070000, 0.2876349000, 0.3612992000, 0.5851170000, 1.3005148000", \ - "0.2947162000, 0.3017531000, 0.3194419000, 0.3567017000, 0.4349419000, 0.6586778000, 1.3688634000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0721265000, 0.0752971000, 0.0854764000, 0.1097659000, 0.1646583000, 0.2931584000, 0.6781201000", \ - "0.0721038000, 0.0756131000, 0.0860699000, 0.1107579000, 0.1636138000, 0.2946543000, 0.6782400000", \ - "0.0722579000, 0.0759717000, 0.0854235000, 0.1094144000, 0.1644540000, 0.2957461000, 0.6784009000", \ - "0.0722971000, 0.0760519000, 0.0858136000, 0.1093954000, 0.1648248000, 0.2958235000, 0.6776397000", \ - "0.0723350000, 0.0760569000, 0.0856061000, 0.1094786000, 0.1631982000, 0.2956620000, 0.6769875000", \ - "0.0720267000, 0.0757059000, 0.0854246000, 0.1106935000, 0.1647953000, 0.2943387000, 0.6768753000", \ - "0.0808025000, 0.0844916000, 0.0944700000, 0.1190932000, 0.1755423000, 0.3006082000, 0.6797883000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0218532000, 0.0249930000, 0.0345172000, 0.0642888000, 0.1619624000, 0.4801233000, 1.5016410000", \ - "0.0217560000, 0.0248926000, 0.0344779000, 0.0642158000, 0.1619003000, 0.4800937000, 1.4986263000", \ - "0.0216805000, 0.0248891000, 0.0343955000, 0.0640968000, 0.1615609000, 0.4791532000, 1.5002369000", \ - "0.0213129000, 0.0245416000, 0.0341004000, 0.0637475000, 0.1613394000, 0.4800055000, 1.4996466000", \ - "0.0258693000, 0.0289207000, 0.0377112000, 0.0654402000, 0.1612808000, 0.4803584000, 1.4972457000", \ - "0.0351003000, 0.0382410000, 0.0469625000, 0.0731255000, 0.1638551000, 0.4787382000, 1.5029858000", \ - "0.0497124000, 0.0535986000, 0.0648038000, 0.0889062000, 0.1716188000, 0.4818649000, 1.4988587000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.4724322000, 0.4792221000, 0.4972090000, 0.5375278000, 0.6171499000, 0.7747223000, 1.1281616000", \ - "0.4756401000, 0.4825544000, 0.5004768000, 0.5409160000, 0.6206838000, 0.7776795000, 1.1319068000", \ - "0.4855485000, 0.4924666000, 0.5100228000, 0.5505307000, 0.6303847000, 0.7872357000, 1.1417696000", \ - "0.5102955000, 0.5170872000, 0.5353725000, 0.5754005000, 0.6554365000, 0.8129576000, 1.1666070000", \ - "0.5669324000, 0.5736043000, 0.5914942000, 0.6315348000, 0.7109291000, 0.8684277000, 1.2226873000", \ - "0.6922470000, 0.6991123000, 0.7170506000, 0.7572592000, 0.8371817000, 0.9949090000, 1.3491634000", \ - "0.9485567000, 0.9557439000, 0.9757921000, 1.0186871000, 1.1026913000, 1.2646244000, 1.6222537000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0867381000, 0.0904582000, 0.1005953000, 0.1266934000, 0.1997952000, 0.4241539000, 1.1369080000", \ - "0.0913392000, 0.0950548000, 0.1051577000, 0.1313640000, 0.2043104000, 0.4293156000, 1.1444630000", \ - "0.1022697000, 0.1059879000, 0.1161163000, 0.1422317000, 0.2152844000, 0.4404405000, 1.1532491000", \ - "0.1282260000, 0.1318990000, 0.1419221000, 0.1678094000, 0.2404795000, 0.4651073000, 1.1803655000", \ - "0.1759205000, 0.1800426000, 0.1905849000, 0.2171874000, 0.2898969000, 0.5145707000, 1.2290472000", \ - "0.2333694000, 0.2387717000, 0.2519710000, 0.2816094000, 0.3550474000, 0.5785067000, 1.2949590000", \ - "0.2806537000, 0.2877081000, 0.3055773000, 0.3429197000, 0.4210527000, 0.6447772000, 1.3562133000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0721369000, 0.0752950000, 0.0855465000, 0.1094088000, 0.1654661000, 0.2934692000, 0.6776344000", \ - "0.0720191000, 0.0757554000, 0.0856911000, 0.1101784000, 0.1629585000, 0.2956226000, 0.6774825000", \ - "0.0721390000, 0.0759190000, 0.0859097000, 0.1095660000, 0.1633346000, 0.2957425000, 0.6770353000", \ - "0.0719774000, 0.0755703000, 0.0857557000, 0.1093914000, 0.1635911000, 0.2951396000, 0.6775303000", \ - "0.0720147000, 0.0757951000, 0.0855107000, 0.1095179000, 0.1637763000, 0.2947341000, 0.6777080000", \ - "0.0719245000, 0.0756796000, 0.0861399000, 0.1105288000, 0.1628068000, 0.2927503000, 0.6773420000", \ - "0.0828268000, 0.0864246000, 0.0963311000, 0.1217217000, 0.1741559000, 0.3042412000, 0.6807104000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0209719000, 0.0239567000, 0.0333849000, 0.0627871000, 0.1601547000, 0.4794958000, 1.4974526000", \ - "0.0208369000, 0.0239364000, 0.0334700000, 0.0627568000, 0.1603059000, 0.4787872000, 1.5026667000", \ - "0.0209663000, 0.0239782000, 0.0334066000, 0.0627015000, 0.1600573000, 0.4795613000, 1.5024837000", \ - "0.0206374000, 0.0237975000, 0.0332682000, 0.0625345000, 0.1600028000, 0.4780420000, 1.5031244000", \ - "0.0250284000, 0.0282485000, 0.0371115000, 0.0647583000, 0.1604680000, 0.4793601000, 1.5011046000", \ - "0.0345356000, 0.0377455000, 0.0462755000, 0.0720021000, 0.1631732000, 0.4781063000, 1.4988718000", \ - "0.0490917000, 0.0533878000, 0.0643977000, 0.0899277000, 0.1714147000, 0.4821970000, 1.4969771000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.4418807000, 0.4488891000, 0.4664235000, 0.5069158000, 0.5868996000, 0.7435859000, 1.0980891000", \ - "0.4445943000, 0.4514996000, 0.4694387000, 0.5099116000, 0.5896360000, 0.7465351000, 1.1009655000", \ - "0.4533574000, 0.4602407000, 0.4781372000, 0.5186041000, 0.5982890000, 0.7552363000, 1.1096412000", \ - "0.4769170000, 0.4838238000, 0.5017543000, 0.5420148000, 0.6219139000, 0.7786352000, 1.1330378000", \ - "0.5346943000, 0.5412298000, 0.5589479000, 0.5998075000, 0.6798167000, 0.8374552000, 1.1908099000", \ - "0.6730183000, 0.6797946000, 0.6978303000, 0.7374207000, 0.8180894000, 0.9756824000, 1.3297131000", \ - "0.9572609000, 0.9644725000, 0.9835041000, 1.0267118000, 1.1113941000, 1.2745849000, 1.6318085000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0844826000, 0.0881436000, 0.0981324000, 0.1239143000, 0.1964714000, 0.4208459000, 1.1357778000", \ - "0.0891848000, 0.0928407000, 0.1028475000, 0.1286490000, 0.2012214000, 0.4251366000, 1.1387719000", \ - "0.1001732000, 0.1038482000, 0.1138331000, 0.1397212000, 0.2121873000, 0.4365779000, 1.1509407000", \ - "0.1262631000, 0.1298458000, 0.1397633000, 0.1654756000, 0.2378105000, 0.4621777000, 1.1744404000", \ - "0.1715578000, 0.1756967000, 0.1864958000, 0.2130282000, 0.2850936000, 0.5091467000, 1.2229444000", \ - "0.2244281000, 0.2297898000, 0.2430995000, 0.2728755000, 0.3467281000, 0.5700772000, 1.2857582000", \ - "0.2664264000, 0.2736608000, 0.2916754000, 0.3294091000, 0.4085970000, 0.6320247000, 1.3437592000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0720153000, 0.0760472000, 0.0854036000, 0.1094325000, 0.1641890000, 0.2958080000, 0.6780149000", \ - "0.0719680000, 0.0757111000, 0.0856800000, 0.1100532000, 0.1627886000, 0.2950385000, 0.6773994000", \ - "0.0721150000, 0.0757134000, 0.0856817000, 0.1101191000, 0.1628393000, 0.2952348000, 0.6773969000", \ - "0.0721861000, 0.0754861000, 0.0857704000, 0.1102934000, 0.1632075000, 0.2957077000, 0.6781329000", \ - "0.0723980000, 0.0759748000, 0.0854999000, 0.1106629000, 0.1634653000, 0.2947326000, 0.6777718000", \ - "0.0719725000, 0.0754802000, 0.0854916000, 0.1094973000, 0.1636278000, 0.2949587000, 0.6775374000", \ - "0.0863607000, 0.0898707000, 0.0993048000, 0.1231514000, 0.1759940000, 0.3034848000, 0.6820781000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0203705000, 0.0234009000, 0.0327803000, 0.0620360000, 0.1596959000, 0.4794524000, 1.5032330000", \ - "0.0203720000, 0.0233747000, 0.0327970000, 0.0620747000, 0.1598071000, 0.4789732000, 1.5027922000", \ - "0.0203728000, 0.0234620000, 0.0328390000, 0.0621247000, 0.1597114000, 0.4793249000, 1.5036045000", \ - "0.0204061000, 0.0234869000, 0.0328737000, 0.0620540000, 0.1594867000, 0.4794112000, 1.4980129000", \ - "0.0251062000, 0.0280091000, 0.0369603000, 0.0648657000, 0.1601632000, 0.4782964000, 1.5024892000", \ - "0.0349741000, 0.0383373000, 0.0469247000, 0.0728376000, 0.1631816000, 0.4781155000, 1.5031505000", \ - "0.0504795000, 0.0547223000, 0.0655039000, 0.0903282000, 0.1719642000, 0.4805662000, 1.4974287000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.3813238000, 0.3881033000, 0.4062667000, 0.4465796000, 0.5267912000, 0.6843936000, 1.0382832000", \ - "0.3833307000, 0.3902084000, 0.4081976000, 0.4485751000, 0.5284352000, 0.6866759000, 1.0398002000", \ - "0.3897890000, 0.3965730000, 0.4148154000, 0.4549935000, 0.5345916000, 0.6926517000, 1.0466294000", \ - "0.4108263000, 0.4178054000, 0.4357883000, 0.4760966000, 0.5558218000, 0.7130652000, 1.0677543000", \ - "0.4670594000, 0.4739400000, 0.4917197000, 0.5320892000, 0.6117828000, 0.7698807000, 1.1239542000", \ - "0.6041318000, 0.6108469000, 0.6288502000, 0.6684924000, 0.7482291000, 0.9060322000, 1.2601723000", \ - "0.8876311000, 0.8950318000, 0.9146594000, 0.9596105000, 1.0445348000, 1.2050720000, 1.5598055000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0799526000, 0.0836222000, 0.0935958000, 0.1196012000, 0.1922097000, 0.4164080000, 1.1306661000", \ - "0.0847993000, 0.0884987000, 0.0985258000, 0.1245399000, 0.1970194000, 0.4220985000, 1.1367322000", \ - "0.0962979000, 0.0999738000, 0.1100090000, 0.1360098000, 0.2085645000, 0.4326670000, 1.1480622000", \ - "0.1224688000, 0.1261138000, 0.1360443000, 0.1617455000, 0.2342534000, 0.4584973000, 1.1803181000", \ - "0.1670537000, 0.1713336000, 0.1820017000, 0.2090197000, 0.2815883000, 0.5066764000, 1.2233594000", \ - "0.2205325000, 0.2260931000, 0.2398993000, 0.2706881000, 0.3446589000, 0.5676691000, 1.2816701000", \ - "0.2666100000, 0.2739894000, 0.2928676000, 0.3316845000, 0.4118550000, 0.6346407000, 1.3460347000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0721094000, 0.0757485000, 0.0853991000, 0.1102182000, 0.1636287000, 0.2949277000, 0.6774472000", \ - "0.0720850000, 0.0756534000, 0.0856010000, 0.1097430000, 0.1629011000, 0.2942364000, 0.6774201000", \ - "0.0720454000, 0.0757922000, 0.0857076000, 0.1095061000, 0.1657032000, 0.2948487000, 0.6779049000", \ - "0.0720805000, 0.0756803000, 0.0855245000, 0.1099386000, 0.1628697000, 0.2951759000, 0.6769116000", \ - "0.0719738000, 0.0756657000, 0.0857907000, 0.1104909000, 0.1646554000, 0.2944696000, 0.6776833000", \ - "0.0710425000, 0.0747836000, 0.0849714000, 0.1097349000, 0.1630538000, 0.2951388000, 0.6774531000", \ - "0.0926359000, 0.0962525000, 0.1067757000, 0.1293265000, 0.1788368000, 0.3021770000, 0.6827988000"); - } - related_pin : "D"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015989100, 0.0051130200, 0.0163505000, 0.0522859000, 0.1672010000, 0.5346780000"); - values("0.0203235000, 0.0233212000, 0.0327923000, 0.0619983000, 0.1594258000, 0.4793169000, 1.5078210000", \ - "0.0202687000, 0.0233601000, 0.0326964000, 0.0619609000, 0.1595193000, 0.4795909000, 1.5009630000", \ - "0.0202888000, 0.0233818000, 0.0327412000, 0.0619775000, 0.1594910000, 0.4779732000, 1.5072819000", \ - "0.0206923000, 0.0237199000, 0.0330189000, 0.0622141000, 0.1595768000, 0.4800960000, 1.5008944000", \ - "0.0258873000, 0.0287249000, 0.0379360000, 0.0652505000, 0.1599714000, 0.4802740000, 1.5057989000", \ - "0.0364676000, 0.0397831000, 0.0485324000, 0.0737051000, 0.1636386000, 0.4781420000, 1.5047640000", \ - "0.0533065000, 0.0569287000, 0.0680990000, 0.0941629000, 0.1736471000, 0.4812970000, 1.4984752000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4b_1") { - leakage_power () { - value : 0.0095460000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0012685000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0029357000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0005703000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0029065000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0005659000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0027082000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0005417000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0029279000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0005707000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0027120000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0005430000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0027162000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0005421000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0026879000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0005328000; - when : "A&B&C&!D_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__or4b"; - cell_leakage_power : 0.0021422130; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014450000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016514000, 0.0016500000, 0.0016469000, 0.0016477000, 0.0016495000, 0.0016536000, 0.0016631000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001411700, -0.001426800, -0.001461600, -0.001466600, -0.001478300, -0.001505200, -0.001567200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015330000; - } - pin ("B") { - capacitance : 0.0018110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028640000, 0.0028318000, 0.0027577000, 0.0027584000, 0.0027601000, 0.0027639000, 0.0027728000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002314700, -0.002399300, -0.002594300, -0.002599800, -0.002612300, -0.002641300, -0.002708000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019090000; - } - pin ("C") { - capacitance : 0.0015030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019312000, 0.0019309000, 0.0019301000, 0.0019307000, 0.0019320000, 0.0019350000, 0.0019418000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001815800, -0.001840000, -0.001895800, -0.001897100, -0.001900200, -0.001907400, -0.001923900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016060000; - } - pin ("D_N") { - capacitance : 0.0014190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0069398000, 0.0068582000, 0.0066702000, 0.0067334000, 0.0068791000, 0.0072148000, 0.0079886000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0006976000, 0.0006293000, 0.0004720000, 0.0005311000, 0.0006672000, 0.0009811000, 0.0017045000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014610000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0097509000, 0.0085782000, 0.0056509000, -0.002444400, -0.025211200, -0.088236000, -0.256671000", \ - "0.0096668000, 0.0084296000, 0.0055455000, -0.002544600, -0.025287200, -0.088355300, -0.256723200", \ - "0.0095457000, 0.0083445000, 0.0055821000, -0.002539300, -0.025364300, -0.088464500, -0.256840300", \ - "0.0094291000, 0.0082008000, 0.0052345000, -0.002781400, -0.025523400, -0.088625200, -0.256971700", \ - "0.0093199000, 0.0082083000, 0.0052308000, -0.002877900, -0.025678500, -0.088735000, -0.257066300", \ - "0.0092909000, 0.0080926000, 0.0051350000, -0.002951100, -0.025771300, -0.088831100, -0.257138600", \ - "0.0111410000, 0.0096255000, 0.0059051000, -0.003300900, -0.025751200, -0.088757000, -0.257064400"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0096854000, 0.0111173000, 0.0148358000, 0.0242698000, 0.0483520000, 0.1121350000, 0.2779576000", \ - "0.0097431000, 0.0111933000, 0.0149064000, 0.0242895000, 0.0485118000, 0.1123244000, 0.2783010000", \ - "0.0098929000, 0.0113473000, 0.0150276000, 0.0244111000, 0.0486181000, 0.1119113000, 0.2795640000", \ - "0.0098378000, 0.0112543000, 0.0148480000, 0.0242324000, 0.0484991000, 0.1122642000, 0.2796025000", \ - "0.0099029000, 0.0111876000, 0.0147467000, 0.0239204000, 0.0482273000, 0.1120451000, 0.2794393000", \ - "0.0101291000, 0.0114370000, 0.0149695000, 0.0240196000, 0.0482246000, 0.1115013000, 0.2780538000", \ - "0.0105590000, 0.0119132000, 0.0154005000, 0.0245893000, 0.0486119000, 0.1123574000, 0.2775801000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0086452000, 0.0074591000, 0.0045419000, -0.003567200, -0.026325800, -0.089307400, -0.257629600", \ - "0.0085179000, 0.0073146000, 0.0045549000, -0.003562200, -0.026376100, -0.089449000, -0.257765000", \ - "0.0083473000, 0.0071473000, 0.0042360000, -0.003843300, -0.026574500, -0.089606800, -0.257900900", \ - "0.0083021000, 0.0071073000, 0.0041435000, -0.003899900, -0.026720500, -0.089756400, -0.258033800", \ - "0.0081142000, 0.0069280000, 0.0040194000, -0.004064300, -0.026810300, -0.089884200, -0.258143100", \ - "0.0081988000, 0.0070157000, 0.0040390000, -0.004034200, -0.026870300, -0.089934600, -0.258205300", \ - "0.0101629000, 0.0086313000, 0.0048729000, -0.004210700, -0.026853700, -0.089879600, -0.258125300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0097399000, 0.0111854000, 0.0148595000, 0.0242183000, 0.0483786000, 0.1115611000, 0.2778957000", \ - "0.0097719000, 0.0112094000, 0.0148784000, 0.0242345000, 0.0484327000, 0.1115717000, 0.2781753000", \ - "0.0097925000, 0.0112150000, 0.0148778000, 0.0242384000, 0.0484056000, 0.1116787000, 0.2781109000", \ - "0.0097516000, 0.0111397000, 0.0147157000, 0.0240335000, 0.0483069000, 0.1115216000, 0.2781889000", \ - "0.0096654000, 0.0109849000, 0.0145540000, 0.0237625000, 0.0479744000, 0.1114080000, 0.2792347000", \ - "0.0098010000, 0.0111063000, 0.0146979000, 0.0237367000, 0.0478796000, 0.1113809000, 0.2790598000", \ - "0.0102731000, 0.0115446000, 0.0150291000, 0.0242089000, 0.0482778000, 0.1118214000, 0.2783198000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0083927000, 0.0072012000, 0.0042708000, -0.003816100, -0.026625000, -0.089633500, -0.257846400", \ - "0.0083328000, 0.0071217000, 0.0041538000, -0.003916600, -0.026675600, -0.089686800, -0.257900900", \ - "0.0082374000, 0.0070647000, 0.0041090000, -0.003923600, -0.026715600, -0.089723300, -0.257930500", \ - "0.0079355000, 0.0067196000, 0.0037596000, -0.004211000, -0.026983700, -0.089967300, -0.258231000", \ - "0.0077185000, 0.0064915000, 0.0035842000, -0.004481300, -0.027242100, -0.090238000, -0.258452400", \ - "0.0076542000, 0.0064535000, 0.0034860000, -0.004571000, -0.027318900, -0.090298000, -0.258554400", \ - "0.0120153000, 0.0105652000, 0.0069330000, -0.002322500, -0.026512100, -0.090077500, -0.258343400"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0094148000, 0.0108495000, 0.0144711000, 0.0238254000, 0.0480012000, 0.1118777000, 0.2763108000", \ - "0.0093529000, 0.0107907000, 0.0144096000, 0.0237599000, 0.0479371000, 0.1118149000, 0.2792661000", \ - "0.0094002000, 0.0108154000, 0.0144589000, 0.0237979000, 0.0479457000, 0.1118596000, 0.2795435000", \ - "0.0093094000, 0.0107474000, 0.0143603000, 0.0236923000, 0.0478579000, 0.1118188000, 0.2792343000", \ - "0.0090967000, 0.0105226000, 0.0141471000, 0.0234634000, 0.0476324000, 0.1116257000, 0.2791760000", \ - "0.0089859000, 0.0103682000, 0.0139692000, 0.0232949000, 0.0474629000, 0.1106351000, 0.2791788000", \ - "0.0091409000, 0.0105199000, 0.0141090000, 0.0233132000, 0.0474080000, 0.1113477000, 0.2784777000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0109131000, 0.0097004000, 0.0067424000, -0.001127400, -0.023953000, -0.087177100, -0.255607600", \ - "0.0107574000, 0.0095546000, 0.0065969000, -0.001338200, -0.024149500, -0.087336500, -0.255748500", \ - "0.0105897000, 0.0093747000, 0.0064172000, -0.001522000, -0.024335700, -0.087518400, -0.255919400", \ - "0.0104418000, 0.0092423000, 0.0063157000, -0.001756700, -0.024524600, -0.087639100, -0.256044500", \ - "0.0104294000, 0.0091945000, 0.0062342000, -0.001848600, -0.024638300, -0.087781100, -0.256156200", \ - "0.0103197000, 0.0091251000, 0.0061726000, -0.001953700, -0.024743000, -0.087859100, -0.256232900", \ - "0.0125220000, 0.0109960000, 0.0073001000, -0.002108400, -0.024799100, -0.087832000, -0.256164400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0099302000, 0.0113880000, 0.0150830000, 0.0243794000, 0.0484199000, 0.1114544000, 0.2791738000", \ - "0.0099020000, 0.0113649000, 0.0150458000, 0.0243664000, 0.0484144000, 0.1114541000, 0.2792227000", \ - "0.0099040000, 0.0113524000, 0.0150364000, 0.0243337000, 0.0483775000, 0.1114888000, 0.2793430000", \ - "0.0098883000, 0.0112883000, 0.0149270000, 0.0242175000, 0.0483255000, 0.1113773000, 0.2792647000", \ - "0.0099118000, 0.0112571000, 0.0148615000, 0.0240838000, 0.0481580000, 0.1119611000, 0.2777584000", \ - "0.0105154000, 0.0118447000, 0.0153024000, 0.0241347000, 0.0483421000, 0.1116625000, 0.2790625000", \ - "0.0110364000, 0.0123417000, 0.0158145000, 0.0249616000, 0.0489172000, 0.1123718000, 0.2771786000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5091190000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4718907000, 0.4854270000, 0.5137856000, 0.5658814000, 0.6597188000, 0.8335803000, 1.2040973000", \ - "0.4725623000, 0.4858527000, 0.5142303000, 0.5662467000, 0.6602721000, 0.8341288000, 1.2046297000", \ - "0.4793601000, 0.4926410000, 0.5209538000, 0.5729156000, 0.6669149000, 0.8408061000, 1.2113123000", \ - "0.5013762000, 0.5147281000, 0.5430028000, 0.5952056000, 0.6878968000, 0.8629869000, 1.2334845000", \ - "0.5528041000, 0.5666662000, 0.5946408000, 0.6468613000, 0.7405088000, 0.9145272000, 1.2847307000", \ - "0.6607575000, 0.6746483000, 0.7025534000, 0.7546628000, 0.8488263000, 1.0232479000, 1.3932924000", \ - "0.8597210000, 0.8736699000, 0.9038549000, 0.9594341000, 1.0583400000, 1.2386002000, 1.6120943000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0660491000, 0.0726418000, 0.0879868000, 0.1248249000, 0.2185244000, 0.4639946000, 1.1099944000", \ - "0.0709536000, 0.0775838000, 0.0928660000, 0.1297665000, 0.2235416000, 0.4687985000, 1.1148682000", \ - "0.0827623000, 0.0893263000, 0.1045623000, 0.1414323000, 0.2355006000, 0.4799212000, 1.1257956000", \ - "0.1090613000, 0.1155857000, 0.1307391000, 0.1673752000, 0.2614068000, 0.5062440000, 1.1517454000", \ - "0.1489874000, 0.1562883000, 0.1722217000, 0.2091258000, 0.3030273000, 0.5485159000, 1.1920653000", \ - "0.1966171000, 0.2058896000, 0.2240161000, 0.2618618000, 0.3557926000, 0.6006441000, 1.2470943000", \ - "0.2325433000, 0.2448210000, 0.2685587000, 0.3119766000, 0.4062184000, 0.6496290000, 1.2934965000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0626496000, 0.0711780000, 0.0897781000, 0.1275130000, 0.2013946000, 0.3654110000, 0.7912316000", \ - "0.0628705000, 0.0712209000, 0.0898077000, 0.1267748000, 0.2007890000, 0.3655532000, 0.7912628000", \ - "0.0631508000, 0.0711666000, 0.0897741000, 0.1268692000, 0.2008265000, 0.3655780000, 0.7912346000", \ - "0.0630277000, 0.0715543000, 0.0897078000, 0.1257974000, 0.2003760000, 0.3649054000, 0.7894982000", \ - "0.0630436000, 0.0713249000, 0.0895060000, 0.1280349000, 0.1985825000, 0.3642558000, 0.7927481000", \ - "0.0624278000, 0.0714264000, 0.0909668000, 0.1262950000, 0.1996888000, 0.3640388000, 0.7912008000", \ - "0.0706245000, 0.0797967000, 0.0991062000, 0.1357953000, 0.2106336000, 0.3724284000, 0.7945095000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0214630000, 0.0284090000, 0.0466784000, 0.0960453000, 0.2281694000, 0.5764239000, 1.4999761000", \ - "0.0214205000, 0.0283676000, 0.0466267000, 0.0958897000, 0.2282846000, 0.5768945000, 1.5003012000", \ - "0.0213119000, 0.0281888000, 0.0464520000, 0.0960170000, 0.2283383000, 0.5770954000, 1.4973425000", \ - "0.0218938000, 0.0286322000, 0.0464939000, 0.0956426000, 0.2280017000, 0.5760941000, 1.4983050000", \ - "0.0260608000, 0.0323165000, 0.0490194000, 0.0964624000, 0.2279119000, 0.5767654000, 1.5001099000", \ - "0.0343853000, 0.0410189000, 0.0560484000, 0.0998601000, 0.2289538000, 0.5773008000, 1.5010394000", \ - "0.0480888000, 0.0555254000, 0.0707603000, 0.1099785000, 0.2309431000, 0.5790542000, 1.4976211000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4562166000, 0.4700023000, 0.4979041000, 0.5501087000, 0.6426813000, 0.8179502000, 1.1884064000", \ - "0.4560060000, 0.4693225000, 0.4975941000, 0.5498532000, 0.6434212000, 0.8176460000, 1.1883102000", \ - "0.4622092000, 0.4754389000, 0.5037106000, 0.5558676000, 0.6499984000, 0.8236791000, 1.1942042000", \ - "0.4836092000, 0.4970618000, 0.5252858000, 0.5775557000, 0.6710348000, 0.8453953000, 1.2160641000", \ - "0.5367045000, 0.5503399000, 0.5781626000, 0.6303443000, 0.7235253000, 0.8984500000, 1.2690873000", \ - "0.6546932000, 0.6684092000, 0.6962175000, 0.7483477000, 0.8421853000, 1.0168720000, 1.3870773000", \ - "0.8820576000, 0.8966661000, 0.9273401000, 0.9836973000, 1.0828940000, 1.2643223000, 1.6383870000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0671890000, 0.0737360000, 0.0891735000, 0.1261269000, 0.2202564000, 0.4658107000, 1.1098684000", \ - "0.0719351000, 0.0785240000, 0.0939414000, 0.1308841000, 0.2251187000, 0.4704322000, 1.1144330000", \ - "0.0836417000, 0.0902095000, 0.1054802000, 0.1423827000, 0.2364914000, 0.4814088000, 1.1284670000", \ - "0.1090651000, 0.1155859000, 0.1307065000, 0.1672981000, 0.2613876000, 0.5074103000, 1.1526360000", \ - "0.1470485000, 0.1542782000, 0.1701108000, 0.2068505000, 0.3009279000, 0.5472689000, 1.1928346000", \ - "0.1900682000, 0.1991075000, 0.2174316000, 0.2554957000, 0.3492484000, 0.5943190000, 1.2396493000", \ - "0.2186965000, 0.2307494000, 0.2542529000, 0.2978314000, 0.3919959000, 0.6371797000, 1.2805424000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0626156000, 0.0718395000, 0.0897335000, 0.1258613000, 0.2001612000, 0.3649159000, 0.7897487000", \ - "0.0629510000, 0.0715331000, 0.0898083000, 0.1256684000, 0.1994207000, 0.3646421000, 0.7909874000", \ - "0.0628605000, 0.0712497000, 0.0901667000, 0.1261443000, 0.2001295000, 0.3655277000, 0.7910545000", \ - "0.0627933000, 0.0712740000, 0.0898534000, 0.1256315000, 0.1994845000, 0.3645158000, 0.7909589000", \ - "0.0630010000, 0.0714498000, 0.0898185000, 0.1259195000, 0.2008707000, 0.3643931000, 0.7909559000", \ - "0.0627325000, 0.0716247000, 0.0898223000, 0.1257603000, 0.1982359000, 0.3641286000, 0.7931456000", \ - "0.0733840000, 0.0824939000, 0.1013252000, 0.1384903000, 0.2147619000, 0.3741103000, 0.7957125000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0208817000, 0.0277215000, 0.0456135000, 0.0949105000, 0.2270251000, 0.5774112000, 1.4972878000", \ - "0.0208875000, 0.0276895000, 0.0455872000, 0.0949092000, 0.2269085000, 0.5769275000, 1.4966783000", \ - "0.0207544000, 0.0275083000, 0.0457160000, 0.0948621000, 0.2267077000, 0.5772983000, 1.4981192000", \ - "0.0213998000, 0.0280226000, 0.0458741000, 0.0947422000, 0.2272878000, 0.5773916000, 1.5006073000", \ - "0.0256279000, 0.0318000000, 0.0483287000, 0.0963121000, 0.2268209000, 0.5761381000, 1.5014695000", \ - "0.0341803000, 0.0402302000, 0.0554078000, 0.0991811000, 0.2286147000, 0.5757777000, 1.5007682000", \ - "0.0477090000, 0.0551811000, 0.0722816000, 0.1099884000, 0.2303977000, 0.5802418000, 1.4948998000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4220565000, 0.4357035000, 0.4640247000, 0.5161043000, 0.6101073000, 0.7839442000, 1.1544968000", \ - "0.4219461000, 0.4352194000, 0.4635864000, 0.5156700000, 0.6098858000, 0.7836090000, 1.1542691000", \ - "0.4273442000, 0.4408222000, 0.4690808000, 0.5213218000, 0.6140532000, 0.7894125000, 1.1600690000", \ - "0.4486881000, 0.4624454000, 0.4904008000, 0.5426243000, 0.6363740000, 0.8104007000, 1.1807920000", \ - "0.5037634000, 0.5172167000, 0.5454985000, 0.5976761000, 0.6910454000, 0.8658084000, 1.2366188000", \ - "0.6368152000, 0.6503991000, 0.6782322000, 0.7301803000, 0.8239161000, 0.9987082000, 1.3690870000", \ - "0.8975917000, 0.9126429000, 0.9432476000, 0.9998145000, 1.0998050000, 1.2813378000, 1.6549332000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0648972000, 0.0713950000, 0.0864617000, 0.1230505000, 0.2167852000, 0.4613503000, 1.1048420000", \ - "0.0697482000, 0.0762256000, 0.0913361000, 0.1279362000, 0.2216348000, 0.4661081000, 1.1096338000", \ - "0.0813152000, 0.0877617000, 0.1028025000, 0.1393977000, 0.2336869000, 0.4781249000, 1.1228890000", \ - "0.1060273000, 0.1124806000, 0.1274193000, 0.1639232000, 0.2578149000, 0.5025310000, 1.1460318000", \ - "0.1417275000, 0.1489284000, 0.1648801000, 0.2015123000, 0.2954291000, 0.5408710000, 1.1853885000", \ - "0.1814114000, 0.1905048000, 0.2089461000, 0.2469339000, 0.3408645000, 0.5859679000, 1.2328545000", \ - "0.2035455000, 0.2158933000, 0.2405703000, 0.2842368000, 0.3782378000, 0.6241808000, 1.2675017000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0631873000, 0.0720103000, 0.0903868000, 0.1261267000, 0.1990104000, 0.3640587000, 0.7920369000", \ - "0.0628682000, 0.0712620000, 0.0902738000, 0.1262746000, 0.2001371000, 0.3655159000, 0.7910568000", \ - "0.0628219000, 0.0714402000, 0.0897506000, 0.1257507000, 0.2002010000, 0.3648485000, 0.7895307000", \ - "0.0628880000, 0.0714260000, 0.0895368000, 0.1258595000, 0.1987453000, 0.3650327000, 0.7934776000", \ - "0.0628789000, 0.0714863000, 0.0898136000, 0.1259012000, 0.1996674000, 0.3651817000, 0.7909972000", \ - "0.0628971000, 0.0716117000, 0.0900370000, 0.1264749000, 0.1984808000, 0.3646803000, 0.7934748000", \ - "0.0755829000, 0.0847483000, 0.1038949000, 0.1406880000, 0.2153943000, 0.3741356000, 0.7947110000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0203288000, 0.0270714000, 0.0450123000, 0.0942344000, 0.2270255000, 0.5758567000, 1.4956602000", \ - "0.0202876000, 0.0269946000, 0.0450576000, 0.0942815000, 0.2272148000, 0.5759549000, 1.4965830000", \ - "0.0203062000, 0.0270280000, 0.0450059000, 0.0941023000, 0.2270138000, 0.5776419000, 1.5009810000", \ - "0.0211922000, 0.0277557000, 0.0453971000, 0.0944078000, 0.2272166000, 0.5760592000, 1.4963720000", \ - "0.0254175000, 0.0316453000, 0.0482109000, 0.0955633000, 0.2270043000, 0.5778032000, 1.5006314000", \ - "0.0342642000, 0.0403224000, 0.0555841000, 0.0992228000, 0.2277899000, 0.5764399000, 1.5005814000", \ - "0.0487500000, 0.0560012000, 0.0724832000, 0.1101230000, 0.2305561000, 0.5797735000, 1.4964414000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3819712000, 0.3956749000, 0.4236608000, 0.4760855000, 0.5698443000, 0.7447167000, 1.1138702000", \ - "0.3856944000, 0.3996360000, 0.4276152000, 0.4799942000, 0.5737618000, 0.7487183000, 1.1179743000", \ - "0.3936008000, 0.4072743000, 0.4353575000, 0.4878887000, 0.5815727000, 0.7561704000, 1.1258301000", \ - "0.4076983000, 0.4211900000, 0.4494891000, 0.5011855000, 0.5952369000, 0.7701028000, 1.1409348000", \ - "0.4291727000, 0.4426398000, 0.4708323000, 0.5231313000, 0.6169803000, 0.7921147000, 1.1623628000", \ - "0.4554121000, 0.4689606000, 0.4972394000, 0.5493258000, 0.6418914000, 0.8179279000, 1.1881919000", \ - "0.4774724000, 0.4911097000, 0.5191461000, 0.5714184000, 0.6650666000, 0.8398383000, 1.2104014000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.1236038000, 0.1301510000, 0.1453087000, 0.1820219000, 0.2756530000, 0.5211596000, 1.1671503000", \ - "0.1284140000, 0.1349760000, 0.1501241000, 0.1868450000, 0.2804915000, 0.5261696000, 1.1753722000", \ - "0.1412305000, 0.1477716000, 0.1629787000, 0.1996785000, 0.2932207000, 0.5385110000, 1.1845529000", \ - "0.1718526000, 0.1784149000, 0.1935440000, 0.2302175000, 0.3237113000, 0.5693785000, 1.2192369000", \ - "0.2297691000, 0.2363650000, 0.2516627000, 0.2883058000, 0.3820279000, 0.6277753000, 1.2759961000", \ - "0.3186844000, 0.3253767000, 0.3407792000, 0.3773656000, 0.4713742000, 0.7160659000, 1.3620552000", \ - "0.4555471000, 0.4627622000, 0.4785665000, 0.5150230000, 0.6089035000, 0.8547092000, 1.4975859000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0631362000, 0.0721148000, 0.0910253000, 0.1258072000, 0.1983666000, 0.3645483000, 0.7920012000", \ - "0.0630295000, 0.0712388000, 0.0895362000, 0.1280464000, 0.1982671000, 0.3645368000, 0.7915235000", \ - "0.0630142000, 0.0717926000, 0.0906353000, 0.1271241000, 0.1987147000, 0.3637713000, 0.7932279000", \ - "0.0626395000, 0.0711545000, 0.0897534000, 0.1265833000, 0.1996280000, 0.3650982000, 0.7910256000", \ - "0.0628582000, 0.0717457000, 0.0900629000, 0.1259057000, 0.1988425000, 0.3634445000, 0.7930397000", \ - "0.0630494000, 0.0712531000, 0.0897065000, 0.1264388000, 0.2006412000, 0.3659988000, 0.7897942000", \ - "0.0627272000, 0.0717699000, 0.0906085000, 0.1264533000, 0.1993625000, 0.3643295000, 0.7908987000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0209412000, 0.0275726000, 0.0453180000, 0.0943379000, 0.2262213000, 0.5779422000, 1.4991389000", \ - "0.0209384000, 0.0275766000, 0.0453207000, 0.0943341000, 0.2263890000, 0.5780805000, 1.5069870000", \ - "0.0209672000, 0.0276957000, 0.0453898000, 0.0943610000, 0.2262932000, 0.5783879000, 1.5091195000", \ - "0.0209693000, 0.0276085000, 0.0453526000, 0.0942870000, 0.2264315000, 0.5780529000, 1.5071112000", \ - "0.0213928000, 0.0279823000, 0.0456621000, 0.0944718000, 0.2262641000, 0.5782348000, 1.5073428000", \ - "0.0225080000, 0.0289255000, 0.0462874000, 0.0946949000, 0.2259118000, 0.5752634000, 1.5052406000", \ - "0.0250035000, 0.0311699000, 0.0478550000, 0.0954865000, 0.2261545000, 0.5762287000, 1.4988429000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4b_2") { - leakage_power () { - value : 0.0062219000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0019329000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0017965000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0012708000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0017610000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0012648000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0015893000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0012443000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0017522000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0012632000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0015879000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0012437000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0015922000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0012426000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0015703000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0012356000; - when : "A&B&C&!D_N"; - } - area : 10.009600000; - cell_footprint : "sky130_fd_sc_hd__or4b"; - cell_leakage_power : 0.0017855800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014520000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0016876000, 0.0016833000, 0.0016732000, 0.0016739000, 0.0016755000, 0.0016793000, 0.0016879000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001453000, -0.001461800, -0.001482100, -0.001486200, -0.001495800, -0.001517800, -0.001568600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015410000; - } - pin ("B") { - capacitance : 0.0014960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0023657000, 0.0023605000, 0.0023485000, 0.0023482000, 0.0023475000, 0.0023458000, 0.0023419000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002118300, -0.002125900, -0.002143400, -0.002150200, -0.002165900, -0.002202100, -0.002285600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015570000; - } - pin ("C") { - capacitance : 0.0014920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019281000, 0.0019264000, 0.0019227000, 0.0019219000, 0.0019201000, 0.0019160000, 0.0019066000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001824300, -0.001842400, -0.001883900, -0.001885500, -0.001889100, -0.001897300, -0.001916300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015910000; - } - pin ("D_N") { - capacitance : 0.0014390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076846000, 0.0075894000, 0.0073702000, 0.0074148000, 0.0075175000, 0.0077544000, 0.0083003000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019235000, 0.0018623000, 0.0017211000, 0.0017599000, 0.0018494000, 0.0020556000, 0.0025309000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015020000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0155530000, 0.0136410000, 0.0089681000, -0.002602700, -0.035279400, -0.131266700, -0.409532200", \ - "0.0153821000, 0.0134904000, 0.0088293000, -0.002705500, -0.035396500, -0.131243900, -0.409626600", \ - "0.0152250000, 0.0134178000, 0.0087600000, -0.002835400, -0.035478200, -0.131483300, -0.409883900", \ - "0.0150557000, 0.0131571000, 0.0084926000, -0.003091600, -0.035767300, -0.131504200, -0.410020800", \ - "0.0148984000, 0.0132481000, 0.0085309000, -0.002987800, -0.035724600, -0.131816100, -0.410200700", \ - "0.0148412000, 0.0129175000, 0.0082645000, -0.003318600, -0.036032600, -0.131959600, -0.410287800", \ - "0.0152561000, 0.0133593000, 0.0086498000, -0.002997700, -0.035928600, -0.131948900, -0.410224600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0151412000, 0.0167946000, 0.0213425000, 0.0337353000, 0.0680645000, 0.1648242000, 0.4400718000", \ - "0.0151057000, 0.0167378000, 0.0212514000, 0.0336855000, 0.0680218000, 0.1650377000, 0.4401394000", \ - "0.0150836000, 0.0167042000, 0.0212274000, 0.0336576000, 0.0680083000, 0.1647372000, 0.4401546000", \ - "0.0151400000, 0.0167416000, 0.0211272000, 0.0335409000, 0.0679189000, 0.1648061000, 0.4401263000", \ - "0.0151089000, 0.0167505000, 0.0212609000, 0.0333465000, 0.0677357000, 0.1647409000, 0.4398848000", \ - "0.0158149000, 0.0172793000, 0.0215582000, 0.0333643000, 0.0677262000, 0.1642975000, 0.4398177000", \ - "0.0166403000, 0.0180794000, 0.0221949000, 0.0343081000, 0.0682354000, 0.1654609000, 0.4398490000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0140043000, 0.0121182000, 0.0074842000, -0.004131900, -0.036841100, -0.132878700, -0.411071000", \ - "0.0137669000, 0.0118480000, 0.0072077000, -0.004324500, -0.037004400, -0.132843400, -0.411111000", \ - "0.0136726000, 0.0117282000, 0.0070622000, -0.004479500, -0.036795400, -0.132896800, -0.411305200", \ - "0.0135343000, 0.0116412000, 0.0069976000, -0.004575800, -0.037259500, -0.132986100, -0.411386400", \ - "0.0134456000, 0.0115692000, 0.0068777000, -0.004661000, -0.037130600, -0.133254900, -0.411519500", \ - "0.0134064000, 0.0115099000, 0.0068207000, -0.004751400, -0.037451600, -0.133352100, -0.411562800", \ - "0.0138330000, 0.0122048000, 0.0072969000, -0.004273800, -0.037183000, -0.133170400, -0.411438800"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0151985000, 0.0168336000, 0.0213636000, 0.0338695000, 0.0685030000, 0.1656665000, 0.4427567000", \ - "0.0151983000, 0.0168350000, 0.0213892000, 0.0338648000, 0.0684953000, 0.1656595000, 0.4428201000", \ - "0.0151590000, 0.0167920000, 0.0213527000, 0.0338498000, 0.0684436000, 0.1656797000, 0.4411050000", \ - "0.0152274000, 0.0168145000, 0.0213096000, 0.0337300000, 0.0682882000, 0.1656388000, 0.4409544000", \ - "0.0151594000, 0.0167288000, 0.0211184000, 0.0333881000, 0.0678756000, 0.1653164000, 0.4411125000", \ - "0.0158963000, 0.0173778000, 0.0216223000, 0.0336700000, 0.0677536000, 0.1647627000, 0.4411819000", \ - "0.0165362000, 0.0179697000, 0.0221187000, 0.0341095000, 0.0680679000, 0.1653816000, 0.4404004000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0132191000, 0.0113286000, 0.0066675000, -0.004883300, -0.037119500, -0.133200200, -0.411557500", \ - "0.0131830000, 0.0112665000, 0.0066047000, -0.004930000, -0.037623400, -0.133385800, -0.411587300", \ - "0.0130207000, 0.0111148000, 0.0064785000, -0.005085200, -0.037757600, -0.133537800, -0.411725800", \ - "0.0128388000, 0.0109433000, 0.0062686000, -0.005262400, -0.037581500, -0.133709600, -0.411980500", \ - "0.0127511000, 0.0108455000, 0.0061665000, -0.005384900, -0.037878700, -0.133927700, -0.412015300", \ - "0.0126290000, 0.0107336000, 0.0061110000, -0.005460100, -0.038167100, -0.134081700, -0.412173900", \ - "0.0135087000, 0.0115120000, 0.0067051000, -0.005082000, -0.037967500, -0.133958700, -0.412134000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0147777000, 0.0164335000, 0.0209642000, 0.0334668000, 0.0680788000, 0.1653878000, 0.4412165000", \ - "0.0147995000, 0.0164217000, 0.0209451000, 0.0334810000, 0.0679984000, 0.1652460000, 0.4409076000", \ - "0.0148524000, 0.0164609000, 0.0209773000, 0.0334415000, 0.0680528000, 0.1652654000, 0.4411417000", \ - "0.0148797000, 0.0164103000, 0.0208758000, 0.0333130000, 0.0678594000, 0.1651545000, 0.4404442000", \ - "0.0147455000, 0.0163251000, 0.0207454000, 0.0329493000, 0.0674915000, 0.1649024000, 0.4405543000", \ - "0.0153566000, 0.0168320000, 0.0210832000, 0.0329307000, 0.0672535000, 0.1641494000, 0.4406027000", \ - "0.0158547000, 0.0172964000, 0.0214186000, 0.0335451000, 0.0676275000, 0.1651512000, 0.4396200000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0131094000, 0.0112153000, 0.0065487000, -0.005007900, -0.037703200, -0.133627400, -0.411683900", \ - "0.0130590000, 0.0111491000, 0.0065738000, -0.005001100, -0.037713200, -0.133641400, -0.411705600", \ - "0.0130028000, 0.0110964000, 0.0064655000, -0.005087900, -0.037774900, -0.133702000, -0.411738000", \ - "0.0126898000, 0.0107752000, 0.0061300000, -0.005491900, -0.038096000, -0.133863300, -0.412108400", \ - "0.0125571000, 0.0105873000, 0.0059332000, -0.005617000, -0.038335300, -0.134258500, -0.412397400", \ - "0.0122422000, 0.0103375000, 0.0056901000, -0.005844400, -0.038458000, -0.134252200, -0.412539000", \ - "0.0171646000, 0.0152103000, 0.0102083000, -0.002648900, -0.037521200, -0.134198600, -0.412370900"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489450, 0.0115220000, 0.0327879100, 0.0933038600, 0.2655128000"); - values("0.0147312000, 0.0163041000, 0.0208149000, 0.0332509000, 0.0678279000, 0.1650310000, 0.4396309000", \ - "0.0146586000, 0.0162650000, 0.0207165000, 0.0331479000, 0.0677371000, 0.1649138000, 0.4415360000", \ - "0.0147252000, 0.0162950000, 0.0208034000, 0.0332416000, 0.0678157000, 0.1649751000, 0.4412622000", \ - "0.0145778000, 0.0161778000, 0.0206588000, 0.0330674000, 0.0676765000, 0.1648005000, 0.4412205000", \ - "0.0144073000, 0.0159833000, 0.0204624000, 0.0329312000, 0.0674535000, 0.1648745000, 0.4410685000", \ - "0.0143537000, 0.0158535000, 0.0203847000, 0.0327857000, 0.0672078000, 0.1643672000, 0.4407937000", \ - "0.0148080000, 0.0163326000, 0.0206849000, 0.0329538000, 0.0670773000, 0.1648548000, 0.4394150000"); - } - } - max_capacitance : 0.2655130000; - max_transition : 1.5020670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.6232652000, 0.6353839000, 0.6617035000, 0.7139674000, 0.8085632000, 0.9789146000, 1.3165902000", \ - "0.6245277000, 0.6365203000, 0.6626938000, 0.7153653000, 0.8099046000, 0.9785210000, 1.3183931000", \ - "0.6316945000, 0.6436173000, 0.6700440000, 0.7222876000, 0.8172276000, 0.9872931000, 1.3251055000", \ - "0.6530319000, 0.6647199000, 0.6908621000, 0.7433692000, 0.8377591000, 1.0073675000, 1.3466087000", \ - "0.7044550000, 0.7162148000, 0.7424102000, 0.7949506000, 0.8893819000, 1.0596810000, 1.3977154000", \ - "0.8151052000, 0.8269302000, 0.8531406000, 0.9054832000, 0.9998872000, 1.1703439000, 1.5095176000", \ - "1.0402225000, 1.0522960000, 1.0799877000, 1.1338789000, 1.2310563000, 1.4019750000, 1.7436397000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0794758000, 0.0850975000, 0.0984017000, 0.1300609000, 0.2127930000, 0.4435312000, 1.0981585000", \ - "0.0842868000, 0.0898711000, 0.1031506000, 0.1348081000, 0.2177890000, 0.4491192000, 1.1050558000", \ - "0.0957886000, 0.1013906000, 0.1146201000, 0.1462356000, 0.2291754000, 0.4600199000, 1.1140160000", \ - "0.1229171000, 0.1283822000, 0.1413616000, 0.1727031000, 0.2553818000, 0.4868861000, 1.1405333000", \ - "0.1696177000, 0.1759225000, 0.1899117000, 0.2218899000, 0.3041769000, 0.5360019000, 1.1889602000", \ - "0.2277230000, 0.2356840000, 0.2528258000, 0.2871193000, 0.3697328000, 0.6006085000, 1.2550455000", \ - "0.2795170000, 0.2901476000, 0.3124704000, 0.3541897000, 0.4398139000, 0.6690900000, 1.3225675000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0845668000, 0.0910595000, 0.1070117000, 0.1402562000, 0.2017732000, 0.3379534000, 0.6788873000", \ - "0.0844836000, 0.0910201000, 0.1066235000, 0.1383098000, 0.2008987000, 0.3398654000, 0.6800603000", \ - "0.0842303000, 0.0913423000, 0.1069873000, 0.1399928000, 0.2043452000, 0.3390448000, 0.6785259000", \ - "0.0849769000, 0.0912398000, 0.1064507000, 0.1384641000, 0.2039733000, 0.3388261000, 0.6810109000", \ - "0.0841456000, 0.0913596000, 0.1060588000, 0.1384603000, 0.2040441000, 0.3360476000, 0.6781006000", \ - "0.0844986000, 0.0911961000, 0.1070267000, 0.1384228000, 0.2043830000, 0.3364164000, 0.6791302000", \ - "0.0918975000, 0.0982512000, 0.1142697000, 0.1476829000, 0.2084853000, 0.3427383000, 0.6813072000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0210490000, 0.0261739000, 0.0401628000, 0.0800178000, 0.1974212000, 0.5343022000, 1.4982182000", \ - "0.0210940000, 0.0261883000, 0.0400700000, 0.0801628000, 0.1976324000, 0.5346741000, 1.4981100000", \ - "0.0209365000, 0.0260258000, 0.0400133000, 0.0799083000, 0.1973774000, 0.5348942000, 1.4941254000", \ - "0.0208561000, 0.0259745000, 0.0400126000, 0.0796570000, 0.1974969000, 0.5353839000, 1.4936909000", \ - "0.0258385000, 0.0303253000, 0.0433982000, 0.0814731000, 0.1972784000, 0.5354443000, 1.4947897000", \ - "0.0341963000, 0.0394555000, 0.0521656000, 0.0871568000, 0.1991752000, 0.5351827000, 1.4958405000", \ - "0.0484327000, 0.0550866000, 0.0693199000, 0.1034169000, 0.2050920000, 0.5377372000, 1.4973559000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.5891930000, 0.6010030000, 0.6276938000, 0.6797823000, 0.7747366000, 0.9447869000, 1.2825705000", \ - "0.5909989000, 0.6028112000, 0.6293733000, 0.6819636000, 0.7762084000, 0.9449013000, 1.2848610000", \ - "0.5992447000, 0.6110291000, 0.6370562000, 0.6896840000, 0.7837662000, 0.9541617000, 1.2929513000", \ - "0.6218376000, 0.6335202000, 0.6596311000, 0.7121169000, 0.8065856000, 0.9765553000, 1.3155029000", \ - "0.6753013000, 0.6869534000, 0.7130785000, 0.7656099000, 0.8598902000, 1.0301631000, 1.3689861000", \ - "0.7942760000, 0.8062804000, 0.8322111000, 0.8846134000, 0.9793037000, 1.1497311000, 1.4890994000", \ - "1.0528354000, 1.0646586000, 1.0923918000, 1.1463688000, 1.2434356000, 1.4150972000, 1.7561995000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0791212000, 0.0846270000, 0.0978327000, 0.1294302000, 0.2123077000, 0.4440761000, 1.0977265000", \ - "0.0837929000, 0.0893441000, 0.1025494000, 0.1341215000, 0.2173021000, 0.4488668000, 1.1023938000", \ - "0.0953454000, 0.1008736000, 0.1141040000, 0.1456776000, 0.2284883000, 0.4600950000, 1.1144758000", \ - "0.1218356000, 0.1272774000, 0.1402982000, 0.1715817000, 0.2542888000, 0.4864608000, 1.1394499000", \ - "0.1672312000, 0.1733599000, 0.1871204000, 0.2192800000, 0.3018794000, 0.5332549000, 1.1892954000", \ - "0.2223687000, 0.2301558000, 0.2471361000, 0.2818067000, 0.3644471000, 0.5952745000, 1.2506912000", \ - "0.2696134000, 0.2803749000, 0.3028403000, 0.3445259000, 0.4304616000, 0.6600746000, 1.3135876000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0843159000, 0.0909244000, 0.1072557000, 0.1400504000, 0.2039822000, 0.3391517000, 0.6789054000", \ - "0.0843810000, 0.0906210000, 0.1070712000, 0.1389492000, 0.2011148000, 0.3401285000, 0.6797845000", \ - "0.0844230000, 0.0911788000, 0.1060131000, 0.1383622000, 0.2026163000, 0.3401078000, 0.6803366000", \ - "0.0845054000, 0.0906154000, 0.1064025000, 0.1384925000, 0.2039160000, 0.3397812000, 0.6797840000", \ - "0.0844038000, 0.0916736000, 0.1061181000, 0.1384888000, 0.2017073000, 0.3378161000, 0.6801341000", \ - "0.0844427000, 0.0910674000, 0.1067886000, 0.1385697000, 0.2046856000, 0.3390402000, 0.6798588000", \ - "0.0922520000, 0.0995135000, 0.1142128000, 0.1461871000, 0.2079535000, 0.3409423000, 0.6823061000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0205819000, 0.0255996000, 0.0393503000, 0.0791792000, 0.1964172000, 0.5334149000, 1.4967726000", \ - "0.0205004000, 0.0255664000, 0.0393589000, 0.0791476000, 0.1966236000, 0.5341685000, 1.4970181000", \ - "0.0204373000, 0.0255429000, 0.0393122000, 0.0790952000, 0.1963985000, 0.5341890000, 1.4946192000", \ - "0.0206520000, 0.0256493000, 0.0394294000, 0.0789174000, 0.1965576000, 0.5346977000, 1.4989762000", \ - "0.0251220000, 0.0298433000, 0.0429834000, 0.0813586000, 0.1968111000, 0.5343878000, 1.4944567000", \ - "0.0342148000, 0.0394252000, 0.0515317000, 0.0865487000, 0.1984756000, 0.5346118000, 1.4986640000", \ - "0.0482502000, 0.0550335000, 0.0690328000, 0.1032583000, 0.2045805000, 0.5369775000, 1.4974005000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.5683657000, 0.5801989000, 0.6062708000, 0.6588687000, 0.7532116000, 0.9233704000, 1.2621783000", \ - "0.5690058000, 0.5810210000, 0.6070863000, 0.6597282000, 0.7542484000, 0.9230228000, 1.2630914000", \ - "0.5748848000, 0.5868355000, 0.6133686000, 0.6657093000, 0.7600446000, 0.9287305000, 1.2688076000", \ - "0.5953681000, 0.6071643000, 0.6331248000, 0.6857042000, 0.7798455000, 0.9505795000, 1.2890464000", \ - "0.6496619000, 0.6613498000, 0.6875046000, 0.7400396000, 0.8343637000, 1.0049769000, 1.3438404000", \ - "0.7831831000, 0.7952326000, 0.8217050000, 0.8737857000, 0.9682610000, 1.1391386000, 1.4785159000", \ - "1.0769381000, 1.0890819000, 1.1161053000, 1.1703116000, 1.2675601000, 1.4401910000, 1.7804394000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0776151000, 0.0830804000, 0.0961287000, 0.1275111000, 0.2103168000, 0.4409557000, 1.0973111000", \ - "0.0825042000, 0.0879637000, 0.1010565000, 0.1324584000, 0.2152085000, 0.4462122000, 1.1005730000", \ - "0.0938911000, 0.0993479000, 0.1123692000, 0.1437571000, 0.2264981000, 0.4572574000, 1.1111739000", \ - "0.1201582000, 0.1254511000, 0.1384102000, 0.1695655000, 0.2519017000, 0.4830795000, 1.1368578000", \ - "0.1644200000, 0.1705623000, 0.1846021000, 0.2165470000, 0.2990855000, 0.5307021000, 1.1847412000", \ - "0.2174107000, 0.2252724000, 0.2423804000, 0.2767659000, 0.3598341000, 0.5904677000, 1.2487916000", \ - "0.2608728000, 0.2717181000, 0.2943862000, 0.3368722000, 0.4228964000, 0.6529393000, 1.3062808000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0845031000, 0.0913242000, 0.1061406000, 0.1383595000, 0.2042975000, 0.3399837000, 0.6800348000", \ - "0.0845738000, 0.0911443000, 0.1065981000, 0.1383334000, 0.2008504000, 0.3396542000, 0.6799519000", \ - "0.0844278000, 0.0908675000, 0.1067893000, 0.1389442000, 0.2010930000, 0.3405178000, 0.6794634000", \ - "0.0843290000, 0.0909456000, 0.1060039000, 0.1384895000, 0.2022193000, 0.3375097000, 0.6802424000", \ - "0.0849457000, 0.0911609000, 0.1063018000, 0.1384332000, 0.2012645000, 0.3368348000, 0.6800729000", \ - "0.0845322000, 0.0910391000, 0.1072692000, 0.1403256000, 0.2017030000, 0.3360809000, 0.6795435000", \ - "0.0936166000, 0.1004312000, 0.1164614000, 0.1481031000, 0.2103756000, 0.3417597000, 0.6821826000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0200983000, 0.0251471000, 0.0388711000, 0.0784567000, 0.1961384000, 0.5352059000, 1.4983144000", \ - "0.0200868000, 0.0251862000, 0.0389444000, 0.0786172000, 0.1961730000, 0.5332048000, 1.4979374000", \ - "0.0201423000, 0.0251113000, 0.0388840000, 0.0785616000, 0.1960774000, 0.5346515000, 1.4989117000", \ - "0.0203440000, 0.0254712000, 0.0391767000, 0.0787057000, 0.1959662000, 0.5347526000, 1.4992343000", \ - "0.0250741000, 0.0299980000, 0.0428202000, 0.0808080000, 0.1962063000, 0.5342448000, 1.4987104000", \ - "0.0343552000, 0.0396688000, 0.0519930000, 0.0869978000, 0.1985628000, 0.5336712000, 1.4991319000", \ - "0.0488290000, 0.0557015000, 0.0702657000, 0.1043217000, 0.2052871000, 0.5367084000, 1.4966690000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.5371650000, 0.5494524000, 0.5759496000, 0.6285991000, 0.7225897000, 0.8934351000, 1.2313316000", \ - "0.5416149000, 0.5535603000, 0.5808666000, 0.6334334000, 0.7277980000, 0.8984242000, 1.2362025000", \ - "0.5497449000, 0.5616452000, 0.5884672000, 0.6411844000, 0.7352771000, 0.9061402000, 1.2439979000", \ - "0.5633715000, 0.5753452000, 0.6015200000, 0.6542716000, 0.7489237000, 0.9185633000, 1.2581243000", \ - "0.5838028000, 0.5957287000, 0.6216566000, 0.6747942000, 0.7691079000, 0.9400153000, 1.2786839000", \ - "0.6068666000, 0.6186933000, 0.6452475000, 0.6976466000, 0.7921727000, 0.9611695000, 1.3008354000", \ - "0.6190062000, 0.6309245000, 0.6574386000, 0.7096739000, 0.8037890000, 0.9742528000, 1.3122969000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.1636881000, 0.1693016000, 0.1826857000, 0.2143513000, 0.2967843000, 0.5276066000, 1.1815308000", \ - "0.1683852000, 0.1740406000, 0.1873505000, 0.2190328000, 0.3018962000, 0.5324473000, 1.1914141000", \ - "0.1810794000, 0.1866869000, 0.2000717000, 0.2317362000, 0.3141600000, 0.5451635000, 1.2018984000", \ - "0.2132398000, 0.2189458000, 0.2322863000, 0.2639013000, 0.3463491000, 0.5775649000, 1.2327076000", \ - "0.2827855000, 0.2884761000, 0.3018880000, 0.3335135000, 0.4162055000, 0.6468424000, 1.3014068000", \ - "0.3998473000, 0.4057248000, 0.4193940000, 0.4511218000, 0.5339308000, 0.7641514000, 1.4220232000", \ - "0.5881018000, 0.5944171000, 0.6087070000, 0.6411211000, 0.7241555000, 0.9547918000, 1.6077254000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0843630000, 0.0907747000, 0.1069903000, 0.1394901000, 0.2014090000, 0.3367163000, 0.6800699000", \ - "0.0842693000, 0.0907422000, 0.1066742000, 0.1399839000, 0.2016836000, 0.3374992000, 0.6794898000", \ - "0.0843962000, 0.0906415000, 0.1070355000, 0.1394099000, 0.2014053000, 0.3365822000, 0.6800994000", \ - "0.0844315000, 0.0911999000, 0.1065574000, 0.1383476000, 0.2010961000, 0.3386000000, 0.6811190000", \ - "0.0845087000, 0.0905895000, 0.1067430000, 0.1392031000, 0.2016344000, 0.3392188000, 0.6791138000", \ - "0.0846142000, 0.0909324000, 0.1066391000, 0.1387126000, 0.2023429000, 0.3396775000, 0.6801126000", \ - "0.0842537000, 0.0904931000, 0.1067426000, 0.1388201000, 0.2010488000, 0.3369035000, 0.6780100000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014228400, 0.0040489400, 0.0115220000, 0.0327879000, 0.0933039000, 0.2655130000"); - values("0.0214529000, 0.0264867000, 0.0400793000, 0.0792340000, 0.1962978000, 0.5347836000, 1.4964695000", \ - "0.0214831000, 0.0264246000, 0.0401054000, 0.0791853000, 0.1963405000, 0.5341462000, 1.4991053000", \ - "0.0214641000, 0.0264877000, 0.0400634000, 0.0792029000, 0.1962275000, 0.5340411000, 1.5020670000", \ - "0.0214070000, 0.0264094000, 0.0400745000, 0.0791930000, 0.1960501000, 0.5333776000, 1.5002216000", \ - "0.0216227000, 0.0266532000, 0.0402077000, 0.0793690000, 0.1961465000, 0.5349908000, 1.5016364000", \ - "0.0227449000, 0.0278432000, 0.0412310000, 0.0800711000, 0.1964046000, 0.5331572000, 1.5017606000", \ - "0.0256172000, 0.0305225000, 0.0435504000, 0.0815523000, 0.1970517000, 0.5333576000, 1.4949229000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4b_4") { - leakage_power () { - value : 0.0083785000; - when : "!A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0042898000; - when : "!A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0047891000; - when : "!A&!B&C&D_N"; - } - leakage_power () { - value : 0.0022170000; - when : "!A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0046833000; - when : "!A&B&!C&D_N"; - } - leakage_power () { - value : 0.0022089000; - when : "!A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0043538000; - when : "!A&B&C&D_N"; - } - leakage_power () { - value : 0.0021889000; - when : "!A&B&C&!D_N"; - } - leakage_power () { - value : 0.0046547000; - when : "A&!B&!C&D_N"; - } - leakage_power () { - value : 0.0022069000; - when : "A&!B&!C&!D_N"; - } - leakage_power () { - value : 0.0043520000; - when : "A&!B&C&D_N"; - } - leakage_power () { - value : 0.0021883000; - when : "A&!B&C&!D_N"; - } - leakage_power () { - value : 0.0043564000; - when : "A&B&!C&D_N"; - } - leakage_power () { - value : 0.0021871000; - when : "A&B&!C&!D_N"; - } - leakage_power () { - value : 0.0043349000; - when : "A&B&C&D_N"; - } - leakage_power () { - value : 0.0021808000; - when : "A&B&C&!D_N"; - } - area : 13.763200000; - cell_footprint : "sky130_fd_sc_hd__or4b"; - cell_leakage_power : 0.0037231330; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039470000, 0.0039437000, 0.0039363000, 0.0039363000, 0.0039362000, 0.0039360000, 0.0039356000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003321700, -0.003356600, -0.003437300, -0.003452600, -0.003487900, -0.003569400, -0.003757300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024920000; - } - pin ("B") { - capacitance : 0.0024460000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023020000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0040111000, 0.0040087000, 0.0040032000, 0.0040028000, 0.0040019000, 0.0039998000, 0.0039951000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003378900, -0.003418500, -0.003509900, -0.003526500, -0.003564700, -0.003652900, -0.003856200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025890000; - } - pin ("C") { - capacitance : 0.0024470000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0041590000, 0.0041571000, 0.0041527000, 0.0041498000, 0.0041432000, 0.0041280000, 0.0040930000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003874800, -0.003935500, -0.004075500, -0.004078800, -0.004086600, -0.004104400, -0.004145400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026260000; - } - pin ("D_N") { - capacitance : 0.0014850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014350000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0084738000, 0.0083827000, 0.0081728000, 0.0082292000, 0.0083593000, 0.0086592000, 0.0093505000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0020737000, 0.0020162000, 0.0018837000, 0.0019371000, 0.0020601000, 0.0023437000, 0.0029973000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015360000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (C) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0285043000, 0.0262302000, 0.0198497000, 0.0027475000, -0.051352300, -0.232755200, -0.825731700", \ - "0.0281746000, 0.0259087000, 0.0195117000, 0.0024192000, -0.051672600, -0.232817300, -0.825782700", \ - "0.0279615000, 0.0256559000, 0.0192768000, 0.0026475000, -0.051544700, -0.233191800, -0.826187200", \ - "0.0276536000, 0.0254213000, 0.0190961000, 0.0019345000, -0.052118700, -0.233351100, -0.826246200", \ - "0.0274673000, 0.0252679000, 0.0189261000, 0.0017777000, -0.052266300, -0.233552400, -0.826441100", \ - "0.0274162000, 0.0251474000, 0.0187735000, 0.0016022000, -0.052490100, -0.233747800, -0.826594100", \ - "0.0301058000, 0.0275227000, 0.0206424000, 0.0017278000, -0.052318200, -0.233676100, -0.826573600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0301012000, 0.0320047000, 0.0380490000, 0.0569411000, 0.1152675000, 0.2990506000, 0.8902896000", \ - "0.0300337000, 0.0319344000, 0.0379855000, 0.0569426000, 0.1152575000, 0.2988949000, 0.8858072000", \ - "0.0299276000, 0.0318296000, 0.0379499000, 0.0568555000, 0.1152108000, 0.2989165000, 0.8891177000", \ - "0.0300377000, 0.0319332000, 0.0380239000, 0.0568357000, 0.1150291000, 0.2989099000, 0.8862320000", \ - "0.0302202000, 0.0320831000, 0.0380295000, 0.0563739000, 0.1145012000, 0.2986500000, 0.8899393000", \ - "0.0317959000, 0.0335413000, 0.0391496000, 0.0575086000, 0.1147015000, 0.2984026000, 0.8857960000", \ - "0.0333963000, 0.0350350000, 0.0405383000, 0.0586540000, 0.1161629000, 0.3002260000, 0.8856623000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0260957000, 0.0238906000, 0.0175093000, 0.0003759000, -0.053727700, -0.235043800, -0.827800700", \ - "0.0257992000, 0.0235157000, 0.0171885000, 3.940000e-05, -0.054103200, -0.235151500, -0.827863700", \ - "0.0256160000, 0.0233516000, 0.0170314000, -0.000131200, -0.053859300, -0.235304300, -0.828186300", \ - "0.0253979000, 0.0231548000, 0.0168392000, -0.000321600, -0.054432500, -0.235460300, -0.828288000", \ - "0.0253656000, 0.0231857000, 0.0167484000, -0.000346100, -0.054503500, -0.235689400, -0.828377700", \ - "0.0251816000, 0.0229642000, 0.0165650000, -0.000568400, -0.054842000, -0.236025200, -0.828640800", \ - "0.0273367000, 0.0249918000, 0.0180697000, -0.000554500, -0.054352900, -0.235810800, -0.828467900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0294705000, 0.0313830000, 0.0373805000, 0.0563960000, 0.1152041000, 0.2996376000, 0.8879919000", \ - "0.0294451000, 0.0312999000, 0.0374167000, 0.0564707000, 0.1152077000, 0.2998490000, 0.8911955000", \ - "0.0294165000, 0.0313123000, 0.0374458000, 0.0564993000, 0.1151945000, 0.2996999000, 0.8912096000", \ - "0.0295785000, 0.0314944000, 0.0375491000, 0.0563793000, 0.1149155000, 0.2994613000, 0.8911404000", \ - "0.0294038000, 0.0313118000, 0.0372094000, 0.0557535000, 0.1141431000, 0.2992505000, 0.8908758000", \ - "0.0308865000, 0.0326578000, 0.0383203000, 0.0566397000, 0.1137555000, 0.2980141000, 0.8862318000", \ - "0.0322382000, 0.0338897000, 0.0395005000, 0.0573526000, 0.1151574000, 0.2995375000, 0.8852669000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0237993000, 0.0215420000, 0.0151716000, -0.002032900, -0.056011600, -0.237012600, -0.829625700", \ - "0.0239310000, 0.0216665000, 0.0152813000, -0.001847100, -0.055960000, -0.237180400, -0.829816100", \ - "0.0234685000, 0.0212270000, 0.0148251000, -0.002258300, -0.056381200, -0.237277700, -0.829913500", \ - "0.0232594000, 0.0210320000, 0.0146289000, -0.002459900, -0.056558500, -0.237492900, -0.830129100", \ - "0.0231196000, 0.0208494000, 0.0143981000, -0.002682000, -0.056598600, -0.237849400, -0.830510500", \ - "0.0231180000, 0.0209000000, 0.0145312000, -0.002555200, -0.056757200, -0.237973000, -0.830551700", \ - "0.0268566000, 0.0245077000, 0.0175618000, -0.000946300, -0.055915100, -0.237361600, -0.830304000"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0287862000, 0.0307048000, 0.0366997000, 0.0556053000, 0.1143905000, 0.2992222000, 0.8902769000", \ - "0.0288354000, 0.0307425000, 0.0368583000, 0.0557046000, 0.1144692000, 0.2992990000, 0.8904024000", \ - "0.0288748000, 0.0307671000, 0.0368764000, 0.0558906000, 0.1145215000, 0.3003936000, 0.8863031000", \ - "0.0288612000, 0.0307661000, 0.0368680000, 0.0556777000, 0.1142374000, 0.2992661000, 0.8905527000", \ - "0.0287393000, 0.0306326000, 0.0365413000, 0.0551075000, 0.1134081000, 0.2982472000, 0.8900434000", \ - "0.0296175000, 0.0314046000, 0.0370861000, 0.0552223000, 0.1128749000, 0.2971996000, 0.8856027000", \ - "0.0310195000, 0.0327173000, 0.0382544000, 0.0561986000, 0.1142935000, 0.2982137000, 0.8828295000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0229693000, 0.0207175000, 0.0143760000, -0.002791700, -0.056698700, -0.237838600, -0.830395200", \ - "0.0229935000, 0.0207202000, 0.0143426000, -0.002777100, -0.056877200, -0.237812600, -0.830210400", \ - "0.0228591000, 0.0206143000, 0.0142467000, -0.002599600, -0.056753900, -0.237923800, -0.830499800", \ - "0.0225357000, 0.0202661000, 0.0138667000, -0.003284400, -0.057165200, -0.238255600, -0.830774900", \ - "0.0222009000, 0.0199440000, 0.0136034000, -0.003540500, -0.057665300, -0.238667700, -0.831039200", \ - "0.0221691000, 0.0199350000, 0.0135175000, -0.003601800, -0.057688500, -0.238787900, -0.831313200", \ - "0.0321190000, 0.0298175000, 0.0231576000, 0.0039517000, -0.054364700, -0.238620800, -0.831175800"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015984520, 0.0051100990, 0.0163365000, 0.0522262200, 0.1669622000, 0.5337623000"); - values("0.0280020000, 0.0298898000, 0.0360184000, 0.0547966000, 0.1136235000, 0.2985900000, 0.8865346000", \ - "0.0279639000, 0.0298722000, 0.0359847000, 0.0547916000, 0.1134096000, 0.2983892000, 0.8865323000", \ - "0.0279890000, 0.0298761000, 0.0359867000, 0.0547763000, 0.1136062000, 0.2983992000, 0.8915754000", \ - "0.0277661000, 0.0296996000, 0.0357363000, 0.0546536000, 0.1134040000, 0.2983195000, 0.8832521000", \ - "0.0274838000, 0.0294063000, 0.0354805000, 0.0543931000, 0.1130925000, 0.2976497000, 0.8873156000", \ - "0.0274799000, 0.0292784000, 0.0351018000, 0.0541097000, 0.1123622000, 0.2974489000, 0.8864930000", \ - "0.0282972000, 0.0301186000, 0.0360173000, 0.0546217000, 0.1130210000, 0.2984952000, 0.8846706000"); - } - } - max_capacitance : 0.5337620000; - max_transition : 1.5084920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.4936968000, 0.5004875000, 0.5186150000, 0.5590405000, 0.6395225000, 0.7976068000, 1.1511498000", \ - "0.4975882000, 0.5046622000, 0.5225768000, 0.5631222000, 0.6431436000, 0.8003518000, 1.1554978000", \ - "0.5083011000, 0.5150833000, 0.5331226000, 0.5734387000, 0.6536884000, 0.8113574000, 1.1655829000", \ - "0.5334658000, 0.5402773000, 0.5580104000, 0.5985937000, 0.6788077000, 0.8359073000, 1.1910254000", \ - "0.5891512000, 0.5961623000, 0.6141586000, 0.6542480000, 0.7343173000, 0.8917491000, 1.2468441000", \ - "0.7060700000, 0.7128476000, 0.7310728000, 0.7712326000, 0.8517798000, 1.0099089000, 1.3646433000", \ - "0.9368344000, 0.9441296000, 0.9629677000, 1.0053063000, 1.0892046000, 1.2510186000, 1.6087450000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0883416000, 0.0921584000, 0.1024384000, 0.1289561000, 0.2022040000, 0.4270160000, 1.1397030000", \ - "0.0929292000, 0.0967642000, 0.1070460000, 0.1335375000, 0.2067705000, 0.4314367000, 1.1430492000", \ - "0.1039301000, 0.1077341000, 0.1180487000, 0.1444713000, 0.2176340000, 0.4422956000, 1.1550205000", \ - "0.1306815000, 0.1344395000, 0.1446277000, 0.1707778000, 0.2433777000, 0.4677562000, 1.1787799000", \ - "0.1799710000, 0.1841628000, 0.1950653000, 0.2218018000, 0.2946030000, 0.5188106000, 1.2318987000", \ - "0.2411795000, 0.2465808000, 0.2599085000, 0.2896139000, 0.3627045000, 0.5862612000, 1.3009055000", \ - "0.2954524000, 0.3025167000, 0.3200002000, 0.3571245000, 0.4352573000, 0.6581417000, 1.3681666000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0720138000, 0.0757991000, 0.0859065000, 0.1107175000, 0.1641400000, 0.2952718000, 0.6800288000", \ - "0.0723698000, 0.0759246000, 0.0859666000, 0.1103197000, 0.1632723000, 0.2960076000, 0.6793754000", \ - "0.0722733000, 0.0758201000, 0.0857188000, 0.1100818000, 0.1648780000, 0.2956595000, 0.6801482000", \ - "0.0722166000, 0.0756134000, 0.0860353000, 0.1098160000, 0.1646085000, 0.2952242000, 0.6804032000", \ - "0.0722642000, 0.0762380000, 0.0860022000, 0.1098009000, 0.1654555000, 0.2948884000, 0.6805493000", \ - "0.0723239000, 0.0759788000, 0.0860093000, 0.1097808000, 0.1647731000, 0.2954393000, 0.6790282000", \ - "0.0808141000, 0.0842771000, 0.0944396000, 0.1186640000, 0.1748512000, 0.3016909000, 0.6818142000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0219390000, 0.0251111000, 0.0346869000, 0.0642632000, 0.1616608000, 0.4795372000, 1.4970430000", \ - "0.0219048000, 0.0250438000, 0.0346052000, 0.0641798000, 0.1614971000, 0.4785493000, 1.4973823000", \ - "0.0217880000, 0.0250395000, 0.0344919000, 0.0640544000, 0.1613486000, 0.4794327000, 1.4971450000", \ - "0.0214789000, 0.0246733000, 0.0341857000, 0.0638010000, 0.1613047000, 0.4792797000, 1.4990413000", \ - "0.0257663000, 0.0286969000, 0.0377078000, 0.0655315000, 0.1610587000, 0.4796712000, 1.4996356000", \ - "0.0356135000, 0.0388818000, 0.0472552000, 0.0729664000, 0.1640587000, 0.4789990000, 1.4977698000", \ - "0.0497180000, 0.0539851000, 0.0644735000, 0.0901158000, 0.1720604000, 0.4823730000, 1.4944207000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.4747116000, 0.4815519000, 0.4996625000, 0.5400534000, 0.6202716000, 0.7787545000, 1.1324334000", \ - "0.4778349000, 0.4848056000, 0.5028771000, 0.5431723000, 0.6233739000, 0.7804280000, 1.1358112000", \ - "0.4877588000, 0.4945445000, 0.5122978000, 0.5529315000, 0.6328148000, 0.7915968000, 1.1452163000", \ - "0.5123806000, 0.5193501000, 0.5373874000, 0.5775770000, 0.6575908000, 0.8148975000, 1.1699810000", \ - "0.5688311000, 0.5757183000, 0.5937101000, 0.6342296000, 0.7141249000, 0.8716143000, 1.2268757000", \ - "0.6938605000, 0.7007258000, 0.7187620000, 0.7591395000, 0.8390839000, 0.9972739000, 1.3524100000", \ - "0.9500249000, 0.9572595000, 0.9758818000, 1.0191058000, 1.1039233000, 1.2667257000, 1.6251379000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0876465000, 0.0913898000, 0.1014720000, 0.1276485000, 0.2005455000, 0.4255520000, 1.1370999000", \ - "0.0922239000, 0.0959301000, 0.1061084000, 0.1323117000, 0.2050891000, 0.4291174000, 1.1418531000", \ - "0.1031534000, 0.1068830000, 0.1170537000, 0.1432222000, 0.2158643000, 0.4403672000, 1.1546705000", \ - "0.1290514000, 0.1327411000, 0.1427974000, 0.1687179000, 0.2412912000, 0.4651882000, 1.1790565000", \ - "0.1769349000, 0.1810663000, 0.1916249000, 0.2182619000, 0.2908494000, 0.5151557000, 1.2285220000", \ - "0.2347345000, 0.2401354000, 0.2533549000, 0.2830442000, 0.3564654000, 0.5795712000, 1.2948298000", \ - "0.2825208000, 0.2895829000, 0.3074811000, 0.3448975000, 0.4230339000, 0.6464124000, 1.3567888000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0723011000, 0.0757926000, 0.0859065000, 0.1106428000, 0.1638098000, 0.2951592000, 0.6798832000", \ - "0.0723584000, 0.0760764000, 0.0860350000, 0.1100403000, 0.1636627000, 0.2966213000, 0.6790610000", \ - "0.0722912000, 0.0755396000, 0.0860714000, 0.1098344000, 0.1641655000, 0.2958761000, 0.6800672000", \ - "0.0724428000, 0.0761753000, 0.0860542000, 0.1100193000, 0.1637201000, 0.2964112000, 0.6798011000", \ - "0.0720873000, 0.0756155000, 0.0857726000, 0.1103933000, 0.1634232000, 0.2958873000, 0.6792607000", \ - "0.0720638000, 0.0757831000, 0.0857276000, 0.1102056000, 0.1637356000, 0.2935489000, 0.6789972000", \ - "0.0829700000, 0.0865637000, 0.0962422000, 0.1211605000, 0.1774321000, 0.3039683000, 0.6831748000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0211255000, 0.0241286000, 0.0336494000, 0.0627833000, 0.1601044000, 0.4790793000, 1.5003006000", \ - "0.0209868000, 0.0242278000, 0.0336638000, 0.0628712000, 0.1601768000, 0.4788352000, 1.4975513000", \ - "0.0211454000, 0.0242061000, 0.0335933000, 0.0628110000, 0.1601262000, 0.4779870000, 1.5004199000", \ - "0.0208794000, 0.0239668000, 0.0334224000, 0.0626602000, 0.1601627000, 0.4784708000, 1.5001206000", \ - "0.0251391000, 0.0283769000, 0.0372378000, 0.0649030000, 0.1601330000, 0.4789947000, 1.4994100000", \ - "0.0346768000, 0.0378822000, 0.0464242000, 0.0721686000, 0.1631770000, 0.4775801000, 1.4981244000", \ - "0.0492238000, 0.0535689000, 0.0645513000, 0.0900946000, 0.1714632000, 0.4817071000, 1.4963455000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.4444743000, 0.4510501000, 0.4688882000, 0.5094964000, 0.5897018000, 0.7467542000, 1.1021758000", \ - "0.4470158000, 0.4537636000, 0.4719344000, 0.5123085000, 0.5928601000, 0.7510421000, 1.1047933000", \ - "0.4555913000, 0.4623691000, 0.4804755000, 0.5209347000, 0.6010897000, 0.7581948000, 1.1135959000", \ - "0.4790197000, 0.4859450000, 0.5038274000, 0.5443528000, 0.6242223000, 0.7812269000, 1.1366799000", \ - "0.5367463000, 0.5432919000, 0.5610748000, 0.6016054000, 0.6809784000, 0.8388786000, 1.1940333000", \ - "0.6743545000, 0.6811603000, 0.6993054000, 0.7391641000, 0.8198929000, 0.9784048000, 1.3332073000", \ - "0.9599498000, 0.9672350000, 0.9866763000, 1.0298407000, 1.1142625000, 1.2776797000, 1.6358261000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0851714000, 0.0888485000, 0.0987734000, 0.1246928000, 0.1970747000, 0.4211876000, 1.1348720000", \ - "0.0898764000, 0.0935432000, 0.1035724000, 0.1293992000, 0.2017567000, 0.4257433000, 1.1389064000", \ - "0.1008689000, 0.1045401000, 0.1145677000, 0.1404978000, 0.2128579000, 0.4374780000, 1.1484609000", \ - "0.1268865000, 0.1305498000, 0.1405203000, 0.1662535000, 0.2383908000, 0.4625081000, 1.1755317000", \ - "0.1723045000, 0.1764325000, 0.1870650000, 0.2138133000, 0.2860973000, 0.5101564000, 1.2245425000", \ - "0.2263461000, 0.2317409000, 0.2451098000, 0.2748958000, 0.3483609000, 0.5721348000, 1.2842536000", \ - "0.2684583000, 0.2757343000, 0.2938366000, 0.3317253000, 0.4108181000, 0.6339563000, 1.3447757000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0725438000, 0.0761249000, 0.0862189000, 0.1097840000, 0.1646690000, 0.2968128000, 0.6790563000", \ - "0.0720406000, 0.0758087000, 0.0860373000, 0.1107725000, 0.1642239000, 0.2951723000, 0.6800603000", \ - "0.0723986000, 0.0759555000, 0.0859993000, 0.1099279000, 0.1633802000, 0.2959837000, 0.6793264000", \ - "0.0722233000, 0.0759997000, 0.0859276000, 0.1106056000, 0.1647588000, 0.2968626000, 0.6790007000", \ - "0.0725759000, 0.0761808000, 0.0857457000, 0.1098351000, 0.1642901000, 0.2956455000, 0.6797150000", \ - "0.0721179000, 0.0757494000, 0.0857337000, 0.1098352000, 0.1647217000, 0.2957449000, 0.6791684000", \ - "0.0858630000, 0.0889171000, 0.0992593000, 0.1248928000, 0.1770296000, 0.3043376000, 0.6834069000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0205002000, 0.0236516000, 0.0330502000, 0.0622989000, 0.1596436000, 0.4792601000, 1.5017864000", \ - "0.0205554000, 0.0235648000, 0.0329949000, 0.0621934000, 0.1597045000, 0.4793804000, 1.5017723000", \ - "0.0206139000, 0.0236856000, 0.0330368000, 0.0622585000, 0.1594327000, 0.4797661000, 1.4978164000", \ - "0.0206688000, 0.0237138000, 0.0330728000, 0.0623296000, 0.1597123000, 0.4795082000, 1.5020183000", \ - "0.0252413000, 0.0284582000, 0.0372124000, 0.0647248000, 0.1601520000, 0.4782104000, 1.5008048000", \ - "0.0350354000, 0.0381281000, 0.0466684000, 0.0726086000, 0.1633454000, 0.4769207000, 1.4988223000", \ - "0.0506068000, 0.0547437000, 0.0655165000, 0.0904701000, 0.1720120000, 0.4808182000, 1.4968710000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.4152474000, 0.4220775000, 0.4398694000, 0.4806187000, 0.5603020000, 0.7182878000, 1.0734441000", \ - "0.4197378000, 0.4267399000, 0.4447191000, 0.4851716000, 0.5653605000, 0.7233376000, 1.0782658000", \ - "0.4301478000, 0.4369481000, 0.4547278000, 0.4954472000, 0.5752184000, 0.7334461000, 1.0881589000", \ - "0.4495315000, 0.4560808000, 0.4738846000, 0.5144784000, 0.5941940000, 0.7522976000, 1.1075789000", \ - "0.4779095000, 0.4846847000, 0.5029289000, 0.5430988000, 0.6232069000, 0.7812304000, 1.1367149000", \ - "0.5159079000, 0.5227834000, 0.5406976000, 0.5808037000, 0.6609283000, 0.8191581000, 1.1730531000", \ - "0.5555250000, 0.5624319000, 0.5804121000, 0.6207848000, 0.7008243000, 0.8583330000, 1.2130902000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.1700449000, 0.1738613000, 0.1841600000, 0.2103680000, 0.2830481000, 0.5067988000, 1.2216164000", \ - "0.1749888000, 0.1788015000, 0.1891014000, 0.2153353000, 0.2878280000, 0.5118811000, 1.2228746000", \ - "0.1874206000, 0.1912176000, 0.2015304000, 0.2277576000, 0.3004729000, 0.5250018000, 1.2392469000", \ - "0.2183196000, 0.2221640000, 0.2323957000, 0.2587101000, 0.3312557000, 0.5550460000, 1.2673882000", \ - "0.2849994000, 0.2888244000, 0.2991291000, 0.3254337000, 0.3979139000, 0.6218931000, 1.3361194000", \ - "0.3941192000, 0.3980840000, 0.4086277000, 0.4352088000, 0.5078543000, 0.7321697000, 1.4432776000", \ - "0.5610354000, 0.5653062000, 0.5763521000, 0.6034162000, 0.6761395000, 0.8998299000, 1.6115641000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0721447000, 0.0757495000, 0.0862541000, 0.1097592000, 0.1642330000, 0.2956331000, 0.6798232000", \ - "0.0722942000, 0.0758877000, 0.0859502000, 0.1099791000, 0.1632278000, 0.2962976000, 0.6792288000", \ - "0.0720700000, 0.0755982000, 0.0861088000, 0.1111803000, 0.1640879000, 0.2957515000, 0.6799263000", \ - "0.0725873000, 0.0761675000, 0.0856988000, 0.1098429000, 0.1642735000, 0.2955282000, 0.6795159000", \ - "0.0723233000, 0.0759995000, 0.0859800000, 0.1098619000, 0.1636170000, 0.2940721000, 0.6802431000", \ - "0.0720992000, 0.0756965000, 0.0858723000, 0.1106025000, 0.1632219000, 0.2956093000, 0.6801796000", \ - "0.0722414000, 0.0760371000, 0.0860457000, 0.1099458000, 0.1634108000, 0.2960299000, 0.6769589000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015984500, 0.0051101000, 0.0163365000, 0.0522262000, 0.1669620000, 0.5337620000"); - values("0.0218215000, 0.0249378000, 0.0340752000, 0.0630559000, 0.1598068000, 0.4787307000, 1.4985793000", \ - "0.0217491000, 0.0249006000, 0.0341320000, 0.0629738000, 0.1594258000, 0.4785863000, 1.5004709000", \ - "0.0218305000, 0.0248995000, 0.0341064000, 0.0631065000, 0.1598600000, 0.4783540000, 1.5084924000", \ - "0.0217427000, 0.0248334000, 0.0341706000, 0.0630379000, 0.1597944000, 0.4792057000, 1.4968037000", \ - "0.0220013000, 0.0250794000, 0.0343001000, 0.0631284000, 0.1595014000, 0.4778561000, 1.5056112000", \ - "0.0233620000, 0.0263389000, 0.0354317000, 0.0638200000, 0.1602354000, 0.4779399000, 1.5032392000", \ - "0.0259265000, 0.0288041000, 0.0378393000, 0.0653288000, 0.1604928000, 0.4777511000, 1.4941208000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4bb_1") { - leakage_power () { - value : 0.0034490000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0010638000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0119259000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0053829000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0028767000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0009774000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0051864000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0030486000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0028731000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0009755000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0051619000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0030445000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0028441000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0009577000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0049196000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0030116000; - when : "A&B&C_N&!D_N"; - } - area : 11.260800000; - cell_footprint : "sky130_fd_sc_hd__or4bb"; - cell_leakage_power : 0.0036061660; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0015030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014080000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017556000, 0.0017456000, 0.0017225000, 0.0017232000, 0.0017248000, 0.0017284000, 0.0017368000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001513200, -0.001531100, -0.001572300, -0.001577100, -0.001588000, -0.001613300, -0.001671600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015980000; - } - pin ("B") { - capacitance : 0.0015440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024116000, 0.0024245000, 0.0024545000, 0.0024548000, 0.0024556000, 0.0024574000, 0.0024615000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002404600, -0.002402100, -0.002396400, -0.002398500, -0.002403100, -0.002413900, -0.002438700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016270000; - } - pin ("C_N") { - capacitance : 0.0015160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072541000, 0.0071588000, 0.0069390000, 0.0070021000, 0.0071477000, 0.0074832000, 0.0082564000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022077000, 0.0021395000, 0.0019822000, 0.0020384000, 0.0021679000, 0.0024665000, 0.0031546000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015680000; - } - pin ("D_N") { - capacitance : 0.0014080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0063042000, 0.0062235000, 0.0060375000, 0.0061054000, 0.0062618000, 0.0066225000, 0.0074539000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019074000, 0.0018420000, 0.0016910000, 0.0017579000, 0.0019121000, 0.0022674000, 0.0030864000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014550000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0106952000, 0.0095117000, 0.0065744000, -0.001320700, -0.024177600, -0.087449400, -0.255896100", \ - "0.0106199000, 0.0094935000, 0.0065726000, -0.001481000, -0.024364500, -0.087592600, -0.256032100", \ - "0.0103757000, 0.0091935000, 0.0062809000, -0.001689800, -0.024561500, -0.087718500, -0.256191300", \ - "0.0103148000, 0.0091373000, 0.0062044000, -0.001945900, -0.024710100, -0.087898800, -0.256333300", \ - "0.0101998000, 0.0090169000, 0.0060846000, -0.001988000, -0.024862200, -0.088044300, -0.256440100", \ - "0.0100766000, 0.0088937000, 0.0059834000, -0.002090100, -0.024936900, -0.088129800, -0.256509200", \ - "0.0123691000, 0.0108832000, 0.0072202000, -0.002134700, -0.025026500, -0.088094000, -0.256440400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0105448000, 0.0119978000, 0.0157061000, 0.0250161000, 0.0490519000, 0.1121156000, 0.2799051000", \ - "0.0105177000, 0.0119851000, 0.0156693000, 0.0249962000, 0.0490682000, 0.1121716000, 0.2797806000", \ - "0.0105113000, 0.0119593000, 0.0156649000, 0.0249743000, 0.0490518000, 0.1126419000, 0.2784085000", \ - "0.0104660000, 0.0119050000, 0.0155512000, 0.0248661000, 0.0489585000, 0.1120186000, 0.2796420000", \ - "0.0105086000, 0.0118662000, 0.0154934000, 0.0247084000, 0.0488653000, 0.1125516000, 0.2782974000", \ - "0.0109719000, 0.0122695000, 0.0157815000, 0.0247418000, 0.0489988000, 0.1123082000, 0.2782181000", \ - "0.0117433000, 0.0130931000, 0.0164229000, 0.0255582000, 0.0494801000, 0.1130607000, 0.2782174000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0092875000, 0.0082453000, 0.0052648000, -0.002716400, -0.025614700, -0.088781500, -0.257165000", \ - "0.0091595000, 0.0079955000, 0.0050819000, -0.003002000, -0.025761400, -0.088901500, -0.257280600", \ - "0.0089946000, 0.0078267000, 0.0049087000, -0.003175700, -0.025943000, -0.089082200, -0.257453600", \ - "0.0089212000, 0.0077679000, 0.0048221000, -0.003248900, -0.026065900, -0.089241300, -0.257579200", \ - "0.0087965000, 0.0075861000, 0.0046727000, -0.003337600, -0.026176100, -0.089290600, -0.257663100", \ - "0.0088284000, 0.0076003000, 0.0046074000, -0.003384900, -0.026277700, -0.089379400, -0.257712600", \ - "0.0109290000, 0.0094431000, 0.0057257000, -0.003655700, -0.026343400, -0.089311000, -0.257591700"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0107988000, 0.0122629000, 0.0159864000, 0.0254246000, 0.0496067000, 0.1133319000, 0.2807509000", \ - "0.0107777000, 0.0122405000, 0.0159664000, 0.0253882000, 0.0495760000, 0.1127938000, 0.2792867000", \ - "0.0107386000, 0.0121780000, 0.0158946000, 0.0252901000, 0.0494926000, 0.1133221000, 0.2793555000", \ - "0.0107014000, 0.0121235000, 0.0157289000, 0.0251159000, 0.0495551000, 0.1132381000, 0.2792710000", \ - "0.0107582000, 0.0120731000, 0.0156503000, 0.0248318000, 0.0491603000, 0.1124133000, 0.2803472000", \ - "0.0109934000, 0.0123011000, 0.0158755000, 0.0248452000, 0.0490863000, 0.1122594000, 0.2787451000", \ - "0.0115552000, 0.0128295000, 0.0163288000, 0.0253391000, 0.0493341000, 0.1131435000, 0.2781586000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0080596000, 0.0068924000, 0.0041243000, -0.003939800, -0.026816300, -0.089954400, -0.258262500", \ - "0.0080484000, 0.0068459000, 0.0039138000, -0.004109200, -0.026818300, -0.089986800, -0.258305000", \ - "0.0079776000, 0.0067891000, 0.0038783000, -0.004080400, -0.026934400, -0.090015400, -0.258362500", \ - "0.0076851000, 0.0064329000, 0.0035882000, -0.004346800, -0.027207600, -0.090341000, -0.258638500", \ - "0.0074797000, 0.0063050000, 0.0033800000, -0.004688700, -0.027474600, -0.090553100, -0.258872500", \ - "0.0073805000, 0.0061781000, 0.0032370000, -0.004780700, -0.027559000, -0.090656500, -0.258955500", \ - "0.0117697000, 0.0103321000, 0.0067683000, -0.002439400, -0.026640400, -0.090260600, -0.258591400"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0113520000, 0.0127889000, 0.0164785000, 0.0258543000, 0.0500149000, 0.1133673000, 0.2796993000", \ - "0.0113085000, 0.0127268000, 0.0164027000, 0.0257815000, 0.0499643000, 0.1132574000, 0.2796492000", \ - "0.0113752000, 0.0128006000, 0.0164740000, 0.0258398000, 0.0502284000, 0.1137835000, 0.2808854000", \ - "0.0112128000, 0.0126609000, 0.0163267000, 0.0257012000, 0.0498572000, 0.1131857000, 0.2796921000", \ - "0.0110339000, 0.0124435000, 0.0160921000, 0.0254746000, 0.0498867000, 0.1134588000, 0.2807560000", \ - "0.0109549000, 0.0123301000, 0.0158907000, 0.0253482000, 0.0494828000, 0.1127609000, 0.2808141000", \ - "0.0112420000, 0.0126133000, 0.0161832000, 0.0253985000, 0.0495689000, 0.1134066000, 0.2803091000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0069989000, 0.0058252000, 0.0029060000, -0.005166600, -0.027927100, -0.090948700, -0.259185600", \ - "0.0069158000, 0.0056693000, 0.0028901000, -0.005160800, -0.027992300, -0.091029500, -0.259244500", \ - "0.0068996000, 0.0057737000, 0.0028344000, -0.005252700, -0.028037600, -0.091063600, -0.259274400", \ - "0.0066480000, 0.0054800000, 0.0025626000, -0.005495000, -0.028287300, -0.091319800, -0.259542000", \ - "0.0063512000, 0.0051569000, 0.0022116000, -0.005808200, -0.028561500, -0.091571700, -0.259813600", \ - "0.0063321000, 0.0051438000, 0.0021882000, -0.005870300, -0.028644600, -0.091650700, -0.259897300", \ - "0.0106709000, 0.0092238000, 0.0056361000, -0.003600700, -0.027757900, -0.091434100, -0.259672200"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0101230000, 0.0115346000, 0.0151751000, 0.0245015000, 0.0486478000, 0.1125533000, 0.2788215000", \ - "0.0100555000, 0.0114666000, 0.0151067000, 0.0244392000, 0.0485791000, 0.1124847000, 0.2787432000", \ - "0.0100851000, 0.0115084000, 0.0151551000, 0.0244930000, 0.0486595000, 0.1125197000, 0.2801147000", \ - "0.0099578000, 0.0113785000, 0.0150446000, 0.0244017000, 0.0485572000, 0.1124253000, 0.2797928000", \ - "0.0097681000, 0.0111956000, 0.0148374000, 0.0241979000, 0.0483741000, 0.1117400000, 0.2786604000", \ - "0.0097059000, 0.0110894000, 0.0146170000, 0.0241051000, 0.0482164000, 0.1120134000, 0.2782679000", \ - "0.0098816000, 0.0112478000, 0.0148489000, 0.0240501000, 0.0479968000, 0.1120886000, 0.2774187000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.5025640000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4517506000, 0.4647662000, 0.4924383000, 0.5435645000, 0.6362035000, 0.8085139000, 1.1776774000", \ - "0.4521638000, 0.4656955000, 0.4929241000, 0.5440980000, 0.6368675000, 0.8091663000, 1.1781244000", \ - "0.4592914000, 0.4722337000, 0.4998257000, 0.5507766000, 0.6434979000, 0.8159373000, 1.1850743000", \ - "0.4810715000, 0.4945503000, 0.5218049000, 0.5727884000, 0.6643457000, 0.8377988000, 1.2070008000", \ - "0.5326428000, 0.5458072000, 0.5730487000, 0.6242810000, 0.7165705000, 0.8893052000, 1.2584036000", \ - "0.6408341000, 0.6543641000, 0.6816460000, 0.7330847000, 0.8253869000, 0.9986243000, 1.3673030000", \ - "0.8381702000, 0.8523094000, 0.8820110000, 0.9371236000, 1.0343083000, 1.2144126000, 1.5872126000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0668820000, 0.0734623000, 0.0888355000, 0.1255970000, 0.2191707000, 0.4636564000, 1.1078052000", \ - "0.0717538000, 0.0783922000, 0.0936931000, 0.1305232000, 0.2240037000, 0.4687297000, 1.1127682000", \ - "0.0835365000, 0.0901180000, 0.1053852000, 0.1422217000, 0.2360282000, 0.4802632000, 1.1225511000", \ - "0.1100707000, 0.1165717000, 0.1317651000, 0.1682902000, 0.2621665000, 0.5063818000, 1.1504933000", \ - "0.1506444000, 0.1579298000, 0.1738935000, 0.2103793000, 0.3038823000, 0.5489447000, 1.1899812000", \ - "0.1994985000, 0.2084361000, 0.2265177000, 0.2644759000, 0.3582591000, 0.6022183000, 1.2448480000", \ - "0.2377070000, 0.2503045000, 0.2739066000, 0.3164126000, 0.4102237000, 0.6549692000, 1.2957949000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0599446000, 0.0681249000, 0.0864196000, 0.1247599000, 0.1965322000, 0.3620513000, 0.7889970000", \ - "0.0594206000, 0.0682513000, 0.0865663000, 0.1224659000, 0.1969722000, 0.3617669000, 0.7911258000", \ - "0.0599684000, 0.0680195000, 0.0864292000, 0.1231977000, 0.1954965000, 0.3622055000, 0.7894708000", \ - "0.0593747000, 0.0682381000, 0.0863650000, 0.1227623000, 0.1961747000, 0.3617046000, 0.7896437000", \ - "0.0595713000, 0.0682578000, 0.0863854000, 0.1240551000, 0.1949790000, 0.3610073000, 0.7903423000", \ - "0.0595507000, 0.0681587000, 0.0873416000, 0.1236175000, 0.1975857000, 0.3613900000, 0.7893094000", \ - "0.0685412000, 0.0776538000, 0.0963219000, 0.1345007000, 0.2088096000, 0.3703010000, 0.7923162000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0215519000, 0.0285202000, 0.0467451000, 0.0959982000, 0.2273333000, 0.5756305000, 1.4959906000", \ - "0.0215291000, 0.0284840000, 0.0466624000, 0.0959289000, 0.2276265000, 0.5746258000, 1.4950403000", \ - "0.0214136000, 0.0282701000, 0.0464821000, 0.0958965000, 0.2275162000, 0.5751002000, 1.4926422000", \ - "0.0219111000, 0.0286251000, 0.0465022000, 0.0954627000, 0.2269868000, 0.5748558000, 1.4941073000", \ - "0.0260429000, 0.0323010000, 0.0490164000, 0.0964479000, 0.2271027000, 0.5760836000, 1.4935095000", \ - "0.0344674000, 0.0403240000, 0.0557918000, 0.0993340000, 0.2283945000, 0.5756281000, 1.4918259000", \ - "0.0479027000, 0.0556089000, 0.0708563000, 0.1094963000, 0.2305398000, 0.5787902000, 1.4912378000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4275895000, 0.4409726000, 0.4680662000, 0.5191536000, 0.6118763000, 0.7843488000, 1.1534336000", \ - "0.4283027000, 0.4416063000, 0.4690748000, 0.5201943000, 0.6116660000, 0.7852495000, 1.1545983000", \ - "0.4356783000, 0.4487848000, 0.4761969000, 0.5272472000, 0.6187488000, 0.7923273000, 1.1616493000", \ - "0.4577133000, 0.4711825000, 0.4984539000, 0.5494216000, 0.6421579000, 0.8147004000, 1.1838653000", \ - "0.5111902000, 0.5242768000, 0.5517723000, 0.6024953000, 0.6950203000, 0.8682514000, 1.2374171000", \ - "0.6303205000, 0.6435416000, 0.6707353000, 0.7220524000, 0.8143974000, 0.9877339000, 1.3567525000", \ - "0.8558170000, 0.8701776000, 0.9004022000, 0.9558183000, 1.0547023000, 1.2341342000, 1.6069264000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0670854000, 0.0737184000, 0.0891209000, 0.1260391000, 0.2196663000, 0.4649225000, 1.1077936000", \ - "0.0718848000, 0.0784932000, 0.0939325000, 0.1308513000, 0.2247580000, 0.4685431000, 1.1116539000", \ - "0.0836156000, 0.0901639000, 0.1054839000, 0.1424360000, 0.2363853000, 0.4811005000, 1.1226736000", \ - "0.1092047000, 0.1157401000, 0.1308581000, 0.1674499000, 0.2615907000, 0.5062105000, 1.1480757000", \ - "0.1477119000, 0.1549003000, 0.1707115000, 0.2072949000, 0.3010119000, 0.5466423000, 1.1905744000", \ - "0.1923254000, 0.2012571000, 0.2195288000, 0.2573836000, 0.3507077000, 0.5950977000, 1.2403365000", \ - "0.2230454000, 0.2353327000, 0.2589984000, 0.3011843000, 0.3947689000, 0.6390781000, 1.2811435000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0597296000, 0.0683959000, 0.0868040000, 0.1224801000, 0.1961176000, 0.3616126000, 0.7912848000", \ - "0.0598278000, 0.0687416000, 0.0870869000, 0.1225678000, 0.1963214000, 0.3616433000, 0.7895841000", \ - "0.0594521000, 0.0686603000, 0.0871483000, 0.1228619000, 0.1962479000, 0.3616775000, 0.7896270000", \ - "0.0593548000, 0.0682420000, 0.0862540000, 0.1243408000, 0.1966003000, 0.3615384000, 0.7921778000", \ - "0.0597381000, 0.0679776000, 0.0865621000, 0.1231406000, 0.1960488000, 0.3618052000, 0.7903625000", \ - "0.0603743000, 0.0685498000, 0.0868612000, 0.1237686000, 0.1960695000, 0.3615417000, 0.7894183000", \ - "0.0707408000, 0.0800491000, 0.0997533000, 0.1361834000, 0.2094301000, 0.3714634000, 0.7945085000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0209955000, 0.0277196000, 0.0457887000, 0.0948693000, 0.2267880000, 0.5757402000, 1.4955829000", \ - "0.0209576000, 0.0277517000, 0.0456404000, 0.0948171000, 0.2266259000, 0.5751233000, 1.4965269000", \ - "0.0208641000, 0.0276026000, 0.0456511000, 0.0947930000, 0.2262654000, 0.5754721000, 1.4906365000", \ - "0.0214325000, 0.0280232000, 0.0458522000, 0.0947492000, 0.2267051000, 0.5752310000, 1.4908401000", \ - "0.0256172000, 0.0317722000, 0.0482829000, 0.0960890000, 0.2266129000, 0.5748205000, 1.4969208000", \ - "0.0339706000, 0.0399070000, 0.0551975000, 0.0989639000, 0.2273466000, 0.5742778000, 1.4959893000", \ - "0.0475316000, 0.0550033000, 0.0701892000, 0.1097434000, 0.2299046000, 0.5773814000, 1.4925636000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.4240375000, 0.4369979000, 0.4645868000, 0.5157807000, 0.6086137000, 0.7810667000, 1.1502864000", \ - "0.4277635000, 0.4409089000, 0.4685030000, 0.5197340000, 0.6121231000, 0.7849270000, 1.1543855000", \ - "0.4362915000, 0.4490963000, 0.4767153000, 0.5276901000, 0.6204010000, 0.7930722000, 1.1624135000", \ - "0.4524693000, 0.4654131000, 0.4929592000, 0.5440392000, 0.6366715000, 0.8093296000, 1.1787642000", \ - "0.4755845000, 0.4889431000, 0.5160442000, 0.5671462000, 0.6597313000, 0.8322162000, 1.2015069000", \ - "0.5028668000, 0.5156795000, 0.5431900000, 0.5941949000, 0.6856417000, 0.8592717000, 1.2285141000", \ - "0.5226560000, 0.5357676000, 0.5633191000, 0.6144162000, 0.7066098000, 0.8798256000, 1.2491742000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.1381805000, 0.1447263000, 0.1599372000, 0.1965488000, 0.2900346000, 0.5344269000, 1.1770470000", \ - "0.1427009000, 0.1492245000, 0.1643840000, 0.2009671000, 0.2943909000, 0.5389157000, 1.1814205000", \ - "0.1553050000, 0.1618076000, 0.1769628000, 0.2134114000, 0.3071960000, 0.5523782000, 1.1964736000", \ - "0.1863758000, 0.1929500000, 0.2081162000, 0.2447784000, 0.3382742000, 0.5823440000, 1.2250028000", \ - "0.2482171000, 0.2547471000, 0.2700137000, 0.3065150000, 0.4002977000, 0.6456738000, 1.2900262000", \ - "0.3452328000, 0.3519214000, 0.3673971000, 0.4038513000, 0.4974790000, 0.7416280000, 1.3850706000", \ - "0.4960086000, 0.5031622000, 0.5188027000, 0.5552493000, 0.6487914000, 0.8937344000, 1.5345811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0597344000, 0.0680855000, 0.0868983000, 0.1227790000, 0.1967662000, 0.3616996000, 0.7906664000", \ - "0.0596541000, 0.0681038000, 0.0864937000, 0.1221378000, 0.1962091000, 0.3617416000, 0.7889626000", \ - "0.0598801000, 0.0680365000, 0.0864378000, 0.1230789000, 0.1970736000, 0.3620057000, 0.7898966000", \ - "0.0600217000, 0.0680246000, 0.0865437000, 0.1238881000, 0.1956478000, 0.3622284000, 0.7889571000", \ - "0.0598578000, 0.0686221000, 0.0865314000, 0.1225746000, 0.1976084000, 0.3613237000, 0.7891599000", \ - "0.0598973000, 0.0681934000, 0.0861729000, 0.1229018000, 0.1967698000, 0.3620634000, 0.7898019000", \ - "0.0596744000, 0.0680563000, 0.0865375000, 0.1245003000, 0.1971123000, 0.3622197000, 0.7895917000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0212264000, 0.0278371000, 0.0454536000, 0.0941840000, 0.2261526000, 0.5760367000, 1.4962466000", \ - "0.0211341000, 0.0278324000, 0.0454664000, 0.0942760000, 0.2263332000, 0.5756273000, 1.4953484000", \ - "0.0211085000, 0.0278066000, 0.0455183000, 0.0942995000, 0.2263812000, 0.5746851000, 1.4929202000", \ - "0.0212391000, 0.0277778000, 0.0455330000, 0.0943751000, 0.2260683000, 0.5748927000, 1.4943301000", \ - "0.0214869000, 0.0282093000, 0.0458124000, 0.0943827000, 0.2263201000, 0.5749732000, 1.4949285000", \ - "0.0225046000, 0.0289369000, 0.0463047000, 0.0946048000, 0.2252279000, 0.5746030000, 1.4964728000", \ - "0.0246198000, 0.0309538000, 0.0476631000, 0.0952225000, 0.2258493000, 0.5753403000, 1.4899428000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3431825000, 0.3566114000, 0.3837249000, 0.4349600000, 0.5273196000, 0.7006290000, 1.0700250000", \ - "0.3468749000, 0.3598181000, 0.3874248000, 0.4384194000, 0.5308795000, 0.7044923000, 1.0738266000", \ - "0.3546609000, 0.3682075000, 0.3954668000, 0.4468913000, 0.5390848000, 0.7121956000, 1.0816961000", \ - "0.3689236000, 0.3821668000, 0.4095068000, 0.4609550000, 0.5531701000, 0.7262706000, 1.0956710000", \ - "0.3887768000, 0.4017336000, 0.4292484000, 0.4805378000, 0.5731400000, 0.7469612000, 1.1161144000", \ - "0.4115109000, 0.4247057000, 0.4520036000, 0.5034850000, 0.5949428000, 0.7685069000, 1.1381214000", \ - "0.4247997000, 0.4375375000, 0.4650184000, 0.5161368000, 0.6086921000, 0.7824845000, 1.1516849000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.1256906000, 0.1322144000, 0.1473637000, 0.1839432000, 0.2772193000, 0.5215378000, 1.1666856000", \ - "0.1304852000, 0.1370085000, 0.1521599000, 0.1887173000, 0.2820053000, 0.5262604000, 1.1716706000", \ - "0.1430530000, 0.1496232000, 0.1647770000, 0.2013511000, 0.2947275000, 0.5397791000, 1.1857195000", \ - "0.1740716000, 0.1805931000, 0.1957914000, 0.2323651000, 0.3256889000, 0.5696159000, 1.2183765000", \ - "0.2332215000, 0.2397734000, 0.2550357000, 0.2914179000, 0.3849369000, 0.6291774000, 1.2702016000", \ - "0.3249812000, 0.3316982000, 0.3469531000, 0.3834510000, 0.4767177000, 0.7209934000, 1.3645010000", \ - "0.4684569000, 0.4755405000, 0.4912627000, 0.5275610000, 0.6218371000, 0.8661686000, 1.5073028000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0598450000, 0.0685957000, 0.0864625000, 0.1223146000, 0.1968092000, 0.3617649000, 0.7894932000", \ - "0.0598603000, 0.0680674000, 0.0875101000, 0.1226448000, 0.1955781000, 0.3612564000, 0.7887958000", \ - "0.0596663000, 0.0688270000, 0.0875677000, 0.1244240000, 0.1952801000, 0.3611755000, 0.7884852000", \ - "0.0596086000, 0.0685009000, 0.0871862000, 0.1232589000, 0.1954939000, 0.3610356000, 0.7890713000", \ - "0.0599171000, 0.0684107000, 0.0864855000, 0.1240252000, 0.1948833000, 0.3612581000, 0.7915828000", \ - "0.0595434000, 0.0684909000, 0.0872457000, 0.1221483000, 0.1973797000, 0.3615881000, 0.7913775000", \ - "0.0596521000, 0.0683500000, 0.0870026000, 0.1221702000, 0.1949872000, 0.3613652000, 0.7869729000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0209105000, 0.0276113000, 0.0452474000, 0.0940569000, 0.2257893000, 0.5772713000, 1.4989171000", \ - "0.0209093000, 0.0276119000, 0.0452464000, 0.0940659000, 0.2257885000, 0.5772339000, 1.4998910000", \ - "0.0209475000, 0.0275998000, 0.0452561000, 0.0939778000, 0.2262247000, 0.5765499000, 1.5025637000", \ - "0.0210101000, 0.0275441000, 0.0452717000, 0.0938521000, 0.2259432000, 0.5764234000, 1.5019611000", \ - "0.0213837000, 0.0279085000, 0.0455602000, 0.0941671000, 0.2260881000, 0.5754115000, 1.5008343000", \ - "0.0223365000, 0.0287823000, 0.0461444000, 0.0942451000, 0.2252516000, 0.5749509000, 1.4932936000", \ - "0.0246117000, 0.0308062000, 0.0475339000, 0.0950702000, 0.2259259000, 0.5758864000, 1.4902669000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4bb_2") { - leakage_power () { - value : 0.0038555000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0014983000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0115768000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0058241000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0033129000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0014156000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0056001000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0034843000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0033048000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0014112000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0055543000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0034753000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0032815000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0013962000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0053523000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0034488000; - when : "A&B&C_N&!D_N"; - } - area : 12.512000000; - cell_footprint : "sky130_fd_sc_hd__or4bb"; - cell_leakage_power : 0.0039869950; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0014890000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014010000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0017290000, 0.0017245000, 0.0017140000, 0.0017139000, 0.0017137000, 0.0017132000, 0.0017121000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.001512400, -0.001527900, -0.001563700, -0.001568400, -0.001579300, -0.001604400, -0.001662200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015770000; - } - pin ("B") { - capacitance : 0.0015340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014570000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024241000, 0.0024331000, 0.0024539000, 0.0024543000, 0.0024553000, 0.0024577000, 0.0024631000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002408100, -0.002404600, -0.002396700, -0.002398500, -0.002402800, -0.002412600, -0.002435100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016110000; - } - pin ("C_N") { - capacitance : 0.0015170000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0072625000, 0.0071669000, 0.0069465000, 0.0070090000, 0.0071531000, 0.0074853000, 0.0082511000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022165000, 0.0021473000, 0.0019878000, 0.0020434000, 0.0021717000, 0.0024675000, 0.0031493000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015680000; - } - pin ("D_N") { - capacitance : 0.0014070000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0063095000, 0.0062287000, 0.0060424000, 0.0061103000, 0.0062668000, 0.0066276000, 0.0074593000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0019092000, 0.0018436000, 0.0016924000, 0.0017597000, 0.0019149000, 0.0022727000, 0.0030974000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014540000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0158585000, 0.0138720000, 0.0089532000, -0.003691100, -0.040613200, -0.152133600, -0.484514400", \ - "0.0157421000, 0.0137443000, 0.0088336000, -0.003477000, -0.040504000, -0.152381300, -0.484652300", \ - "0.0155467000, 0.0135684000, 0.0086594000, -0.003932100, -0.040548900, -0.152584700, -0.484805200", \ - "0.0154137000, 0.0134359000, 0.0085029000, -0.004101900, -0.041032800, -0.152738300, -0.485060000", \ - "0.0152496000, 0.0132670000, 0.0083725000, -0.004254500, -0.041190400, -0.152871400, -0.485205100", \ - "0.0151263000, 0.0131610000, 0.0082626000, -0.004342200, -0.041313300, -0.153081300, -0.485250600", \ - "0.0155550000, 0.0135498000, 0.0085642000, -0.004217700, -0.041212800, -0.153041800, -0.485244500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0155528000, 0.0172489000, 0.0220569000, 0.0357076000, 0.0745672000, 0.1867494000, 0.5172126000", \ - "0.0155289000, 0.0172362000, 0.0220502000, 0.0357053000, 0.0744708000, 0.1868702000, 0.5154831000", \ - "0.0154782000, 0.0171816000, 0.0220194000, 0.0356389000, 0.0744483000, 0.1869165000, 0.5155794000", \ - "0.0155406000, 0.0171980000, 0.0220249000, 0.0356046000, 0.0744117000, 0.1876790000, 0.5177346000", \ - "0.0155200000, 0.0173233000, 0.0221054000, 0.0353145000, 0.0742441000, 0.1867057000, 0.5159319000", \ - "0.0164095000, 0.0179296000, 0.0224401000, 0.0355050000, 0.0742132000, 0.1867491000, 0.5154920000", \ - "0.0172875000, 0.0187662000, 0.0231137000, 0.0364305000, 0.0745795000, 0.1878362000, 0.5150170000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0144088000, 0.0124481000, 0.0075046000, -0.005121000, -0.041996300, -0.153627500, -0.485848400", \ - "0.0143165000, 0.0123250000, 0.0074065000, -0.005283800, -0.042100200, -0.153797900, -0.486052200", \ - "0.0141390000, 0.0121764000, 0.0072492000, -0.005360100, -0.042313700, -0.153912200, -0.486213500", \ - "0.0140057000, 0.0120086000, 0.0073666000, -0.005314200, -0.042126100, -0.154182600, -0.486347400", \ - "0.0138852000, 0.0119016000, 0.0069963000, -0.005595300, -0.042381300, -0.154313200, -0.486403500", \ - "0.0138322000, 0.0118664000, 0.0069128000, -0.005711900, -0.042711100, -0.154419500, -0.486514200", \ - "0.0144925000, 0.0125047000, 0.0074667000, -0.005342200, -0.042343400, -0.154235500, -0.486446300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0157449000, 0.0174255000, 0.0223142000, 0.0360494000, 0.0751031000, 0.1877424000, 0.5166799000", \ - "0.0157613000, 0.0174190000, 0.0222762000, 0.0360565000, 0.0751028000, 0.1885853000, 0.5169143000", \ - "0.0156823000, 0.0174002000, 0.0222691000, 0.0359533000, 0.0750268000, 0.1876537000, 0.5165585000", \ - "0.0157381000, 0.0173990000, 0.0221844000, 0.0358596000, 0.0748670000, 0.1875807000, 0.5157174000", \ - "0.0156984000, 0.0173250000, 0.0220080000, 0.0354619000, 0.0744272000, 0.1876126000, 0.5187795000", \ - "0.0164233000, 0.0179427000, 0.0225841000, 0.0358612000, 0.0742035000, 0.1866166000, 0.5185531000", \ - "0.0172159000, 0.0186564000, 0.0230876000, 0.0363443000, 0.0748624000, 0.1879915000, 0.5156056000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0132144000, 0.0112598000, 0.0063206000, -0.006298100, -0.043177800, -0.154760400, -0.486950400", \ - "0.0131841000, 0.0112021000, 0.0063221000, -0.006314500, -0.043266400, -0.154834300, -0.487073400", \ - "0.0131452000, 0.0111600000, 0.0062333000, -0.006417200, -0.043325500, -0.154820200, -0.487108000", \ - "0.0128689000, 0.0108781000, 0.0059576000, -0.006714000, -0.043595900, -0.155155900, -0.487387000", \ - "0.0126031000, 0.0106353000, 0.0060073000, -0.006612200, -0.043649000, -0.155422100, -0.487619800", \ - "0.0126816000, 0.0107119000, 0.0058218000, -0.006829900, -0.043793900, -0.155526800, -0.487698800", \ - "0.0171914000, 0.0151912000, 0.0098427000, -0.004137800, -0.043435100, -0.155353100, -0.487444900"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0163379000, 0.0180534000, 0.0228341000, 0.0364915000, 0.0755303000, 0.1885202000, 0.5194776000", \ - "0.0162598000, 0.0179215000, 0.0227439000, 0.0364165000, 0.0754741000, 0.1884086000, 0.5193086000", \ - "0.0163202000, 0.0179911000, 0.0228529000, 0.0365060000, 0.0755360000, 0.1884728000, 0.5170281000", \ - "0.0161597000, 0.0178541000, 0.0226778000, 0.0363417000, 0.0753767000, 0.1883416000, 0.5193405000", \ - "0.0160649000, 0.0177579000, 0.0225960000, 0.0362093000, 0.0752016000, 0.1881160000, 0.5173108000", \ - "0.0161723000, 0.0177859000, 0.0223569000, 0.0359442000, 0.0748720000, 0.1873749000, 0.5160770000", \ - "0.0165868000, 0.0181911000, 0.0228387000, 0.0361319000, 0.0752206000, 0.1885486000, 0.5159074000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0120833000, 0.0101073000, 0.0051954000, -0.007438800, -0.044267200, -0.155944600, -0.487948900", \ - "0.0120583000, 0.0100865000, 0.0053297000, -0.007232200, -0.044239300, -0.156029500, -0.488060800", \ - "0.0121698000, 0.0102004000, 0.0052829000, -0.007368300, -0.044332300, -0.156066500, -0.488115200", \ - "0.0117907000, 0.0098058000, 0.0049137000, -0.007712600, -0.044653100, -0.156326000, -0.488344800", \ - "0.0115628000, 0.0095703000, 0.0046731000, -0.007964800, -0.044903200, -0.156574200, -0.488645700", \ - "0.0115430000, 0.0095523000, 0.0046576000, -0.007993200, -0.044927100, -0.156580400, -0.488612900", \ - "0.0166362000, 0.0146292000, 0.0092782000, -0.004622600, -0.043846400, -0.156462800, -0.488534200"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014617790, 0.0042735930, 0.0124940900, 0.0365271900, 0.1067893000, 0.3122047000"); - values("0.0150770000, 0.0167285000, 0.0215470000, 0.0352515000, 0.0742314000, 0.1870417000, 0.5189911000", \ - "0.0150082000, 0.0166607000, 0.0214798000, 0.0351850000, 0.0741637000, 0.1869637000, 0.5192723000", \ - "0.0150731000, 0.0167721000, 0.0215466000, 0.0352188000, 0.0741713000, 0.1871218000, 0.5167291000", \ - "0.0149466000, 0.0166414000, 0.0214301000, 0.0350816000, 0.0741092000, 0.1868170000, 0.5169243000", \ - "0.0148102000, 0.0164814000, 0.0213094000, 0.0348534000, 0.0739017000, 0.1865643000, 0.5187717000", \ - "0.0149586000, 0.0166224000, 0.0213129000, 0.0347628000, 0.0737850000, 0.1864816000, 0.5188238000", \ - "0.0152573000, 0.0168419000, 0.0214693000, 0.0349305000, 0.0739827000, 0.1874795000, 0.5166128000"); - } - } - max_capacitance : 0.3122050000; - max_transition : 1.5056150000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.5873182000, 0.5988535000, 0.6251118000, 0.6787189000, 0.7774612000, 0.9599838000, 1.3439329000", \ - "0.5890237000, 0.6006513000, 0.6267151000, 0.6805438000, 0.7794551000, 0.9626736000, 1.3458223000", \ - "0.5965249000, 0.6080569000, 0.6340442000, 0.6877537000, 0.7862656000, 0.9697773000, 1.3531949000", \ - "0.6178473000, 0.6295852000, 0.6557960000, 0.7092593000, 0.8075886000, 0.9903302000, 1.3742587000", \ - "0.6688953000, 0.6805311000, 0.7069709000, 0.7602148000, 0.8586978000, 1.0414231000, 1.4254985000", \ - "0.7789069000, 0.7904773000, 0.8167395000, 0.8699862000, 0.9686317000, 1.1525376000, 1.5364009000", \ - "1.0021539000, 1.0142066000, 1.0417193000, 1.0973743000, 1.1986064000, 1.3848397000, 1.7707684000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0789428000, 0.0843531000, 0.0971827000, 0.1279556000, 0.2093505000, 0.4426058000, 1.1215266000", \ - "0.0837952000, 0.0891580000, 0.1019776000, 0.1327828000, 0.2143969000, 0.4476080000, 1.1274681000", \ - "0.0952168000, 0.1005753000, 0.1134395000, 0.1441554000, 0.2257515000, 0.4588477000, 1.1385483000", \ - "0.1224605000, 0.1277045000, 0.1404000000, 0.1708364000, 0.2520280000, 0.4856063000, 1.1654868000", \ - "0.1699949000, 0.1760681000, 0.1898738000, 0.2209377000, 0.3019514000, 0.5356183000, 1.2131856000", \ - "0.2296274000, 0.2373813000, 0.2542389000, 0.2881958000, 0.3699563000, 0.6029977000, 1.2839572000", \ - "0.2842673000, 0.2948250000, 0.3172186000, 0.3587636000, 0.4440887000, 0.6753598000, 1.3526862000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0793073000, 0.0858239000, 0.1014647000, 0.1351200000, 0.2026660000, 0.3585110000, 0.7653354000", \ - "0.0793129000, 0.0855022000, 0.1011512000, 0.1351442000, 0.2057065000, 0.3575410000, 0.7672517000", \ - "0.0790694000, 0.0856157000, 0.1011345000, 0.1350810000, 0.2036323000, 0.3586282000, 0.7673038000", \ - "0.0790950000, 0.0855539000, 0.1019909000, 0.1363999000, 0.2034252000, 0.3585584000, 0.7668062000", \ - "0.0791980000, 0.0853663000, 0.1020942000, 0.1356321000, 0.2031706000, 0.3583553000, 0.7667182000", \ - "0.0791231000, 0.0854610000, 0.1022739000, 0.1352450000, 0.2058277000, 0.3570886000, 0.7660618000", \ - "0.0862253000, 0.0934455000, 0.1098680000, 0.1443439000, 0.2130316000, 0.3638354000, 0.7676110000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0200387000, 0.0246196000, 0.0374171000, 0.0743582000, 0.1871648000, 0.5207431000, 1.4964029000", \ - "0.0200635000, 0.0245651000, 0.0373142000, 0.0743520000, 0.1872584000, 0.5210989000, 1.4979322000", \ - "0.0199978000, 0.0245610000, 0.0372439000, 0.0742544000, 0.1871959000, 0.5206448000, 1.4968132000", \ - "0.0199708000, 0.0244784000, 0.0371043000, 0.0740020000, 0.1868886000, 0.5203810000, 1.5005781000", \ - "0.0246296000, 0.0290364000, 0.0407545000, 0.0759432000, 0.1869288000, 0.5212560000, 1.4994204000", \ - "0.0338688000, 0.0385813000, 0.0496776000, 0.0822892000, 0.1888370000, 0.5195021000, 1.4972447000", \ - "0.0475776000, 0.0541025000, 0.0677289000, 0.0994207000, 0.1946406000, 0.5221004000, 1.4954775000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.5622689000, 0.5737390000, 0.5999307000, 0.6535203000, 0.7522373000, 0.9347796000, 1.3188594000", \ - "0.5639567000, 0.5756670000, 0.6017259000, 0.6553583000, 0.7540074000, 0.9366600000, 1.3207184000", \ - "0.5715431000, 0.5829658000, 0.6091046000, 0.6628191000, 0.7615812000, 0.9441259000, 1.3282645000", \ - "0.5932614000, 0.6047622000, 0.6308349000, 0.6844681000, 0.7827772000, 0.9674981000, 1.3496336000", \ - "0.6463042000, 0.6578248000, 0.6837761000, 0.7374406000, 0.8358850000, 1.0194438000, 1.4030334000", \ - "0.7659832000, 0.7777065000, 0.8036460000, 0.8571262000, 0.9556983000, 1.1394093000, 1.5236800000", \ - "1.0203088000, 1.0324932000, 1.0609758000, 1.1163414000, 1.2174494000, 1.4038446000, 1.7903561000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0789268000, 0.0842404000, 0.0970522000, 0.1277291000, 0.2089188000, 0.4427781000, 1.1196727000", \ - "0.0836901000, 0.0889676000, 0.1017609000, 0.1323955000, 0.2136838000, 0.4473971000, 1.1252730000", \ - "0.0949966000, 0.1003364000, 0.1130940000, 0.1436999000, 0.2248648000, 0.4587893000, 1.1359728000", \ - "0.1215572000, 0.1267912000, 0.1394062000, 0.1697706000, 0.2508587000, 0.4849277000, 1.1616841000", \ - "0.1679773000, 0.1739797000, 0.1872601000, 0.2186714000, 0.2998020000, 0.5330524000, 1.2124266000", \ - "0.2244563000, 0.2322732000, 0.2493713000, 0.2832948000, 0.3650526000, 0.5971119000, 1.2769216000", \ - "0.2743338000, 0.2847179000, 0.3072922000, 0.3496334000, 0.4352469000, 0.6666033000, 1.3442337000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0796592000, 0.0858519000, 0.1013533000, 0.1351221000, 0.2057799000, 0.3592064000, 0.7655395000", \ - "0.0792609000, 0.0857387000, 0.1016047000, 0.1350623000, 0.2034509000, 0.3585970000, 0.7667665000", \ - "0.0796781000, 0.0858421000, 0.1012814000, 0.1350445000, 0.2032903000, 0.3584060000, 0.7667794000", \ - "0.0791513000, 0.0855880000, 0.1011424000, 0.1370257000, 0.2038023000, 0.3572269000, 0.7668439000", \ - "0.0791064000, 0.0856737000, 0.1010993000, 0.1350509000, 0.2026261000, 0.3559336000, 0.7671846000", \ - "0.0790802000, 0.0855817000, 0.1019029000, 0.1351550000, 0.2036597000, 0.3573637000, 0.7666023000", \ - "0.0876160000, 0.0947083000, 0.1111046000, 0.1465747000, 0.2139332000, 0.3654706000, 0.7684214000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0196535000, 0.0240730000, 0.0366376000, 0.0733719000, 0.1861382000, 0.5208213000, 1.4998359000", \ - "0.0194739000, 0.0241190000, 0.0366531000, 0.0734296000, 0.1860582000, 0.5205639000, 1.5004287000", \ - "0.0194972000, 0.0240681000, 0.0365860000, 0.0735116000, 0.1861234000, 0.5207700000, 1.5000540000", \ - "0.0196736000, 0.0241385000, 0.0366330000, 0.0733091000, 0.1860762000, 0.5205449000, 1.4980198000", \ - "0.0243362000, 0.0284868000, 0.0404814000, 0.0753695000, 0.1862620000, 0.5206549000, 1.4991031000", \ - "0.0335385000, 0.0381801000, 0.0497497000, 0.0815421000, 0.1879774000, 0.5201218000, 1.4972694000", \ - "0.0477077000, 0.0542305000, 0.0675239000, 0.0987904000, 0.1941834000, 0.5219502000, 1.4942507000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.5590363000, 0.5705144000, 0.5967265000, 0.6503299000, 0.7491070000, 0.9317459000, 1.3158810000", \ - "0.5630654000, 0.5746121000, 0.6013833000, 0.6546025000, 0.7533607000, 0.9359946000, 1.3201377000", \ - "0.5716708000, 0.5831491000, 0.6093554000, 0.6629718000, 0.7617458000, 0.9442201000, 1.3284409000", \ - "0.5880874000, 0.5995469000, 0.6257406000, 0.6793311000, 0.7781064000, 0.9609066000, 1.3450026000", \ - "0.6109074000, 0.6224489000, 0.6485321000, 0.7022101000, 0.8010380000, 0.9834876000, 1.3676571000", \ - "0.6379511000, 0.6496113000, 0.6760460000, 0.7291664000, 0.8278989000, 1.0116440000, 1.3960851000", \ - "0.6572679000, 0.6689089000, 0.6949845000, 0.7484917000, 0.8472673000, 1.0307454000, 1.4138118000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.1509440000, 0.1563203000, 0.1690152000, 0.1995181000, 0.2803626000, 0.5134443000, 1.1928655000", \ - "0.1555238000, 0.1608522000, 0.1736084000, 0.2040905000, 0.2850331000, 0.5180283000, 1.1985284000", \ - "0.1681427000, 0.1734802000, 0.1862311000, 0.2167236000, 0.2977436000, 0.5308218000, 1.2118815000", \ - "0.1993213000, 0.2046738000, 0.2174092000, 0.2479220000, 0.3287703000, 0.5615940000, 1.2412056000", \ - "0.2617835000, 0.2671369000, 0.2799697000, 0.3104051000, 0.3915310000, 0.6245574000, 1.3026425000", \ - "0.3601990000, 0.3656744000, 0.3785602000, 0.4092405000, 0.4904889000, 0.7231797000, 1.4007020000", \ - "0.5135389000, 0.5194158000, 0.5328251000, 0.5637860000, 0.6450752000, 0.8776212000, 1.5554710000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0796773000, 0.0858804000, 0.1014082000, 0.1351810000, 0.2057760000, 0.3605572000, 0.7662607000", \ - "0.0791313000, 0.0853232000, 0.1018597000, 0.1350285000, 0.2030672000, 0.3583158000, 0.7668569000", \ - "0.0793070000, 0.0858283000, 0.1014312000, 0.1350890000, 0.2026459000, 0.3585634000, 0.7662476000", \ - "0.0793281000, 0.0857913000, 0.1014861000, 0.1350715000, 0.2025382000, 0.3582272000, 0.7667473000", \ - "0.0788523000, 0.0854634000, 0.1011599000, 0.1350064000, 0.2055060000, 0.3589219000, 0.7662004000", \ - "0.0792071000, 0.0855558000, 0.1016824000, 0.1354373000, 0.2035546000, 0.3594271000, 0.7666495000", \ - "0.0792623000, 0.0859501000, 0.1019176000, 0.1351328000, 0.2035443000, 0.3578823000, 0.7674959000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0198271000, 0.0243530000, 0.0367531000, 0.0733774000, 0.1857654000, 0.5208004000, 1.5006733000", \ - "0.0198556000, 0.0244809000, 0.0367995000, 0.0733123000, 0.1857035000, 0.5206529000, 1.5016797000", \ - "0.0199387000, 0.0243803000, 0.0367728000, 0.0733335000, 0.1856832000, 0.5209262000, 1.4982372000", \ - "0.0199416000, 0.0243178000, 0.0367383000, 0.0732920000, 0.1857524000, 0.5202227000, 1.5006442000", \ - "0.0201393000, 0.0245146000, 0.0369614000, 0.0732994000, 0.1854270000, 0.5209062000, 1.4994940000", \ - "0.0209504000, 0.0255520000, 0.0378933000, 0.0738524000, 0.1853126000, 0.5195645000, 1.4982311000", \ - "0.0233344000, 0.0275292000, 0.0393841000, 0.0749849000, 0.1856475000, 0.5196497000, 1.4981691000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.4764685000, 0.4878309000, 0.5140063000, 0.5676571000, 0.6663516000, 0.8492707000, 1.2336627000", \ - "0.4806653000, 0.4922338000, 0.5188627000, 0.5721172000, 0.6711355000, 0.8540906000, 1.2376065000", \ - "0.4893334000, 0.5010150000, 0.5274608000, 0.5807388000, 0.6800758000, 0.8631544000, 1.2458317000", \ - "0.5034123000, 0.5150806000, 0.5416105000, 0.5948729000, 0.6934481000, 0.8779532000, 1.2598638000", \ - "0.5236190000, 0.5351725000, 0.5617148000, 0.6148364000, 0.7134907000, 0.8976961000, 1.2805641000", \ - "0.5455116000, 0.5570249000, 0.5831343000, 0.6365317000, 0.7355776000, 0.9188156000, 1.3017705000", \ - "0.5580866000, 0.5694918000, 0.5956055000, 0.6491060000, 0.7476365000, 0.9315299000, 1.3151688000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.1389158000, 0.1442559000, 0.1570578000, 0.1875591000, 0.2685247000, 0.5015951000, 1.1805421000", \ - "0.1437357000, 0.1490756000, 0.1618791000, 0.1923803000, 0.2733469000, 0.5064100000, 1.1856043000", \ - "0.1565083000, 0.1618530000, 0.1745895000, 0.2051715000, 0.2863230000, 0.5198091000, 1.2012967000", \ - "0.1875356000, 0.1928755000, 0.2056307000, 0.2361722000, 0.3169635000, 0.5500374000, 1.2308178000", \ - "0.2472789000, 0.2527018000, 0.2655548000, 0.2960248000, 0.3770750000, 0.6093754000, 1.2918111000", \ - "0.3403498000, 0.3458454000, 0.3588499000, 0.3895807000, 0.4706284000, 0.7028063000, 1.3818420000", \ - "0.4869776000, 0.4927975000, 0.5063027000, 0.5372662000, 0.6181267000, 0.8513071000, 1.5280704000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0792421000, 0.0858677000, 0.1013454000, 0.1350277000, 0.2058389000, 0.3564489000, 0.7668188000", \ - "0.0789180000, 0.0854101000, 0.1013393000, 0.1348887000, 0.2052270000, 0.3574950000, 0.7667044000", \ - "0.0791829000, 0.0859791000, 0.1018055000, 0.1366039000, 0.2053281000, 0.3573409000, 0.7667004000", \ - "0.0792083000, 0.0853647000, 0.1020171000, 0.1355245000, 0.2033145000, 0.3572269000, 0.7667168000", \ - "0.0793166000, 0.0855190000, 0.1016758000, 0.1352062000, 0.2033097000, 0.3570521000, 0.7652591000", \ - "0.0793177000, 0.0854635000, 0.1023730000, 0.1352699000, 0.2050418000, 0.3577448000, 0.7663066000", \ - "0.0797931000, 0.0859052000, 0.1011119000, 0.1355157000, 0.2045207000, 0.3573760000, 0.7666280000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014617800, 0.0042735900, 0.0124941000, 0.0365272000, 0.1067890000, 0.3122050000"); - values("0.0197127000, 0.0243020000, 0.0367533000, 0.0732065000, 0.1855854000, 0.5207570000, 1.5033262000", \ - "0.0197144000, 0.0243024000, 0.0367530000, 0.0732069000, 0.1855852000, 0.5207150000, 1.5020395000", \ - "0.0198088000, 0.0242209000, 0.0367089000, 0.0731476000, 0.1856115000, 0.5206414000, 1.5004387000", \ - "0.0197456000, 0.0242681000, 0.0367723000, 0.0731582000, 0.1856155000, 0.5204754000, 1.5056151000", \ - "0.0200626000, 0.0246072000, 0.0369983000, 0.0732689000, 0.1852583000, 0.5202097000, 1.5031745000", \ - "0.0211388000, 0.0254913000, 0.0377066000, 0.0738592000, 0.1853528000, 0.5188249000, 1.5054071000", \ - "0.0229575000, 0.0276321000, 0.0393531000, 0.0747969000, 0.1855922000, 0.5206382000, 1.4969728000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__or4bb_4") { - leakage_power () { - value : 0.0050278000; - when : "!A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0026199000; - when : "!A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0106797000; - when : "!A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0067646000; - when : "!A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0045839000; - when : "!A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0025913000; - when : "!A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0069627000; - when : "!A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0046576000; - when : "!A&B&C_N&!D_N"; - } - leakage_power () { - value : 0.0045819000; - when : "A&!B&!C_N&D_N"; - } - leakage_power () { - value : 0.0025905000; - when : "A&!B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0069324000; - when : "A&!B&C_N&D_N"; - } - leakage_power () { - value : 0.0046554000; - when : "A&!B&C_N&!D_N"; - } - leakage_power () { - value : 0.0045648000; - when : "A&B&!C_N&D_N"; - } - leakage_power () { - value : 0.0025829000; - when : "A&B&!C_N&!D_N"; - } - leakage_power () { - value : 0.0066326000; - when : "A&B&C_N&D_N"; - } - leakage_power () { - value : 0.0046356000; - when : "A&B&C_N&!D_N"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__or4bb"; - cell_leakage_power : 0.0050664790; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0023650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0039014000, 0.0038949000, 0.0038798000, 0.0038807000, 0.0038828000, 0.0038876000, 0.0038988000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003387500, -0.003424800, -0.003510600, -0.003521300, -0.003545900, -0.003602600, -0.003733300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0024920000; - } - pin ("B") { - capacitance : 0.0024190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045625000, 0.0045536000, 0.0045332000, 0.0045341000, 0.0045361000, 0.0045408000, 0.0045515000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004358700, -0.004386700, -0.004451100, -0.004455100, -0.004464400, -0.004485800, -0.004535200"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025620000; - } - pin ("C_N") { - capacitance : 0.0015030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014490000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0085658000, 0.0084743000, 0.0082636000, 0.0083179000, 0.0084432000, 0.0087321000, 0.0093978000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0045527000, 0.0044966000, 0.0043672000, 0.0044135000, 0.0045203000, 0.0047664000, 0.0053338000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015570000; - } - pin ("D_N") { - capacitance : 0.0013970000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0013470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076561000, 0.0075711000, 0.0073754000, 0.0074398000, 0.0075882000, 0.0079304000, 0.0087190000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0028334000, 0.0027751000, 0.0026408000, 0.0027040000, 0.0028497000, 0.0031856000, 0.0039599000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0014470000; - } - pin ("X") { - direction : "output"; - function : "(A) | (B) | (!C_N) | (!D_N)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0283800000, 0.0261549000, 0.0199139000, 0.0027890000, -0.051213800, -0.232312000, -0.824139900", \ - "0.0282493000, 0.0260210000, 0.0196116000, 0.0025536000, -0.051484700, -0.232356700, -0.824210600", \ - "0.0284189000, 0.0261491000, 0.0199608000, 0.0028015000, -0.051390000, -0.232728900, -0.824568900", \ - "0.0280505000, 0.0258305000, 0.0194547000, 0.0023362000, -0.051748000, -0.232879700, -0.824669700", \ - "0.0275932000, 0.0253189000, 0.0189433000, 0.0018956000, -0.052043700, -0.233115900, -0.824905000", \ - "0.0274960000, 0.0252308000, 0.0188622000, 0.0017073000, -0.052317300, -0.233286400, -0.825017200", \ - "0.0301742000, 0.0278144000, 0.0206961000, 0.0019733000, -0.052142600, -0.233323800, -0.825029800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0299993000, 0.0319153000, 0.0380268000, 0.0568091000, 0.1150784000, 0.2985222000, 0.8887446000", \ - "0.0299414000, 0.0318378000, 0.0378761000, 0.0567555000, 0.1149873000, 0.2984097000, 0.8886331000", \ - "0.0298242000, 0.0317425000, 0.0378535000, 0.0567306000, 0.1150065000, 0.2984504000, 0.8875363000", \ - "0.0299271000, 0.0318359000, 0.0379162000, 0.0567017000, 0.1148905000, 0.2982264000, 0.8842240000", \ - "0.0301039000, 0.0319805000, 0.0379131000, 0.0562027000, 0.1143303000, 0.2981439000, 0.8883255000", \ - "0.0313033000, 0.0333798000, 0.0389879000, 0.0571022000, 0.1144231000, 0.2978776000, 0.8843374000", \ - "0.0331925000, 0.0348446000, 0.0403485000, 0.0584592000, 0.1158661000, 0.2995166000, 0.8838132000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0257555000, 0.0231283000, 0.0168168000, -0.000295300, -0.053959100, -0.235194700, -0.826851300", \ - "0.0253275000, 0.0231132000, 0.0166918000, -0.000362600, -0.054411900, -0.235210500, -0.826875700", \ - "0.0251810000, 0.0229661000, 0.0164912000, -0.000289900, -0.054603400, -0.235409600, -0.827060200", \ - "0.0249184000, 0.0227300000, 0.0163262000, -0.000863200, -0.054802200, -0.235655100, -0.827260500", \ - "0.0248807000, 0.0225994000, 0.0162362000, -0.000880400, -0.055030500, -0.235879300, -0.827410700", \ - "0.0247116000, 0.0224595000, 0.0161246000, -0.000995900, -0.055230600, -0.236160600, -0.827669600", \ - "0.0268265000, 0.0245322000, 0.0176107000, -0.001039900, -0.055214700, -0.235745700, -0.827449600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0302203000, 0.0321341000, 0.0381323000, 0.0571484000, 0.1158982000, 0.2999916000, 0.8903419000", \ - "0.0302113000, 0.0321460000, 0.0381512000, 0.0572057000, 0.1158874000, 0.2997514000, 0.8904661000", \ - "0.0301405000, 0.0320353000, 0.0381651000, 0.0571989000, 0.1158063000, 0.2997265000, 0.8904666000", \ - "0.0302527000, 0.0321506000, 0.0382296000, 0.0570537000, 0.1154988000, 0.2995469000, 0.8864830000", \ - "0.0301126000, 0.0320143000, 0.0379283000, 0.0566123000, 0.1147302000, 0.2996728000, 0.8860337000", \ - "0.0315920000, 0.0333559000, 0.0390235000, 0.0572419000, 0.1143466000, 0.2982743000, 0.8896530000", \ - "0.0327361000, 0.0343877000, 0.0399980000, 0.0578176000, 0.1155479000, 0.2994306000, 0.8844067000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0237871000, 0.0215312000, 0.0151691000, -0.002026500, -0.055929000, -0.236618200, -0.828153500", \ - "0.0239555000, 0.0217273000, 0.0153536000, -0.001735300, -0.055790200, -0.236707700, -0.828212100", \ - "0.0237008000, 0.0214572000, 0.0151019000, -0.001994800, -0.055641100, -0.236812900, -0.828337200", \ - "0.0233686000, 0.0211825000, 0.0147686000, -0.002380800, -0.056319600, -0.236963000, -0.828500000", \ - "0.0233941000, 0.0211648000, 0.0147863000, -0.002340300, -0.056504700, -0.237437800, -0.828934000", \ - "0.0229488000, 0.0207124000, 0.0143596000, -0.002716900, -0.056334800, -0.237449300, -0.829104500", \ - "0.0323832000, 0.0301256000, 0.0233927000, 0.0046462000, -0.053807300, -0.237307300, -0.828881200"); - } - related_pin : "C_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0300152000, 0.0318500000, 0.0379223000, 0.0568296000, 0.1153178000, 0.2998583000, 0.8899763000", \ - "0.0300052000, 0.0319085000, 0.0378849000, 0.0567229000, 0.1152933000, 0.2993275000, 0.8857363000", \ - "0.0299760000, 0.0318823000, 0.0379173000, 0.0568065000, 0.1152279000, 0.2997162000, 0.8867785000", \ - "0.0297679000, 0.0316753000, 0.0377180000, 0.0566049000, 0.1150280000, 0.2995323000, 0.8863754000", \ - "0.0296099000, 0.0315095000, 0.0374825000, 0.0563069000, 0.1148981000, 0.2992133000, 0.8860521000", \ - "0.0292807000, 0.0312277000, 0.0371598000, 0.0560927000, 0.1142932000, 0.2986041000, 0.8863917000", \ - "0.0305535000, 0.0323678000, 0.0382695000, 0.0566743000, 0.1149372000, 0.2997890000, 0.8894969000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0225768000, 0.0203453000, 0.0139329000, -0.003145800, -0.057169400, -0.237990900, -0.829395000", \ - "0.0223224000, 0.0201638000, 0.0138218000, -0.003377800, -0.057319000, -0.238005600, -0.829335500", \ - "0.0224681000, 0.0202398000, 0.0138436000, -0.003175700, -0.057292500, -0.238066100, -0.829473200", \ - "0.0221076000, 0.0198827000, 0.0135961000, -0.003522900, -0.057577400, -0.238386900, -0.829778100", \ - "0.0215889000, 0.0193683000, 0.0129967000, -0.004009300, -0.058027000, -0.238738600, -0.830066700", \ - "0.0215130000, 0.0192727000, 0.0128703000, -0.004244900, -0.058094200, -0.238864600, -0.830346000", \ - "0.0316439000, 0.0293988000, 0.0227500000, 0.0036180000, -0.054576800, -0.238813400, -0.830231900"); - } - related_pin : "D_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0281144000, 0.0300455000, 0.0360301000, 0.0549029000, 0.1134982000, 0.2979013000, 0.8861002000", \ - "0.0280657000, 0.0299483000, 0.0360619000, 0.0548160000, 0.1134917000, 0.2981345000, 0.8810098000", \ - "0.0280434000, 0.0300168000, 0.0360074000, 0.0548798000, 0.1134757000, 0.2993994000, 0.8860673000", \ - "0.0279211000, 0.0297167000, 0.0357886000, 0.0547524000, 0.1132877000, 0.2975374000, 0.8859470000", \ - "0.0276355000, 0.0295472000, 0.0356132000, 0.0544550000, 0.1130768000, 0.2990621000, 0.8855321000", \ - "0.0277136000, 0.0294023000, 0.0351860000, 0.0542119000, 0.1124083000, 0.2970859000, 0.8800827000", \ - "0.0283406000, 0.0301502000, 0.0360765000, 0.0543275000, 0.1129356000, 0.2978892000, 0.8829537000"); - } - } - max_capacitance : 0.5328470000; - max_transition : 1.5029550000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4948267000, 0.5017723000, 0.5198403000, 0.5604309000, 0.6410213000, 0.7995994000, 1.1545590000", \ - "0.4988088000, 0.5057432000, 0.5237514000, 0.5645288000, 0.6448428000, 0.8027807000, 1.1588220000", \ - "0.5096256000, 0.5162861000, 0.5344828000, 0.5747247000, 0.6555936000, 0.8136278000, 1.1689235000", \ - "0.5345844000, 0.5413193000, 0.5594985000, 0.5998885000, 0.6807423000, 0.8391010000, 1.1941187000", \ - "0.5900045000, 0.5966273000, 0.6144250000, 0.6551340000, 0.7349360000, 0.8935263000, 1.2495807000", \ - "0.7062285000, 0.7130128000, 0.7312679000, 0.7715426000, 0.8524508000, 1.0112888000, 1.3669335000", \ - "0.9363860000, 0.9434760000, 0.9622889000, 1.0051232000, 1.0890124000, 1.2517893000, 1.6104590000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0879975000, 0.0918276000, 0.1021887000, 0.1287328000, 0.2019663000, 0.4264983000, 1.1388901000", \ - "0.0926114000, 0.0964376000, 0.1067375000, 0.1333059000, 0.2065560000, 0.4312201000, 1.1435084000", \ - "0.1036220000, 0.1074270000, 0.1177595000, 0.1442437000, 0.2174410000, 0.4419441000, 1.1539761000", \ - "0.1303944000, 0.1341568000, 0.1443611000, 0.1705284000, 0.2432921000, 0.4676259000, 1.1782413000", \ - "0.1796689000, 0.1838664000, 0.1948285000, 0.2215884000, 0.2940191000, 0.5184407000, 1.2308087000", \ - "0.2409929000, 0.2461842000, 0.2595622000, 0.2893393000, 0.3624534000, 0.5858100000, 1.2996898000", \ - "0.2951224000, 0.3021677000, 0.3196842000, 0.3567812000, 0.4349343000, 0.6575867000, 1.3667312000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0721818000, 0.0760134000, 0.0860486000, 0.1109194000, 0.1646437000, 0.2971370000, 0.6819727000", \ - "0.0722045000, 0.0760333000, 0.0861103000, 0.1107316000, 0.1641141000, 0.2973393000, 0.6814210000", \ - "0.0725064000, 0.0759535000, 0.0864825000, 0.1104968000, 0.1650256000, 0.2968897000, 0.6820514000", \ - "0.0721375000, 0.0759345000, 0.0862455000, 0.1111074000, 0.1650235000, 0.2972494000, 0.6818410000", \ - "0.0726478000, 0.0763410000, 0.0859579000, 0.1101225000, 0.1649125000, 0.2956294000, 0.6823750000", \ - "0.0723835000, 0.0761023000, 0.0862042000, 0.1101440000, 0.1653880000, 0.2968176000, 0.6811654000", \ - "0.0809390000, 0.0843577000, 0.0947417000, 0.1204249000, 0.1740983000, 0.3033192000, 0.6837570000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0219760000, 0.0252007000, 0.0347755000, 0.0644203000, 0.1618407000, 0.4795075000, 1.4976064000", \ - "0.0219764000, 0.0251752000, 0.0347725000, 0.0643719000, 0.1617911000, 0.4794793000, 1.4974669000", \ - "0.0218989000, 0.0251316000, 0.0346071000, 0.0642051000, 0.1614890000, 0.4791337000, 1.4961596000", \ - "0.0215006000, 0.0247693000, 0.0343088000, 0.0639053000, 0.1614190000, 0.4785781000, 1.4969977000", \ - "0.0257233000, 0.0288600000, 0.0378109000, 0.0656202000, 0.1612776000, 0.4794182000, 1.4984721000", \ - "0.0351928000, 0.0390709000, 0.0474087000, 0.0730500000, 0.1641968000, 0.4787810000, 1.4953786000", \ - "0.0499226000, 0.0541216000, 0.0645852000, 0.0902703000, 0.1721079000, 0.4817732000, 1.4943839000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4758244000, 0.4826234000, 0.5004320000, 0.5411769000, 0.6213577000, 0.7801000000, 1.1355702000", \ - "0.4789643000, 0.4858919000, 0.5039531000, 0.5446211000, 0.6249234000, 0.7829081000, 1.1390731000", \ - "0.4886239000, 0.4955289000, 0.5134765000, 0.5540711000, 0.6345207000, 0.7923673000, 1.1486398000", \ - "0.5131485000, 0.5199887000, 0.5375623000, 0.5782526000, 0.6588148000, 0.8166997000, 1.1728922000", \ - "0.5688390000, 0.5756268000, 0.5938428000, 0.6342042000, 0.7146213000, 0.8727657000, 1.2291282000", \ - "0.6935936000, 0.7003230000, 0.7185210000, 0.7589622000, 0.8393608000, 0.9981896000, 1.3543242000", \ - "0.9496677000, 0.9571645000, 0.9761300000, 1.0191080000, 1.1038258000, 1.2668570000, 1.6262431000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0872873000, 0.0910522000, 0.1011782000, 0.1274202000, 0.2002542000, 0.4246939000, 1.1380700000", \ - "0.0919103000, 0.0956802000, 0.1058217000, 0.1320545000, 0.2047806000, 0.4290281000, 1.1421770000", \ - "0.1028485000, 0.1065916000, 0.1167954000, 0.1430160000, 0.2156725000, 0.4398849000, 1.1530851000", \ - "0.1288411000, 0.1325376000, 0.1426006000, 0.1685209000, 0.2409834000, 0.4658522000, 1.1794211000", \ - "0.1767251000, 0.1808655000, 0.1914388000, 0.2181095000, 0.2906819000, 0.5147681000, 1.2259516000", \ - "0.2346214000, 0.2399576000, 0.2533968000, 0.2830184000, 0.3563840000, 0.5792780000, 1.2926596000", \ - "0.2823219000, 0.2893978000, 0.3073120000, 0.3447599000, 0.4229005000, 0.6459429000, 1.3557474000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0723477000, 0.0758046000, 0.0862066000, 0.1101891000, 0.1650525000, 0.2961679000, 0.6826540000", \ - "0.0721921000, 0.0759898000, 0.0861461000, 0.1107348000, 0.1640805000, 0.2973078000, 0.6813830000", \ - "0.0722473000, 0.0759325000, 0.0858935000, 0.1112385000, 0.1655736000, 0.2979811000, 0.6816818000", \ - "0.0726098000, 0.0763839000, 0.0864694000, 0.1101277000, 0.1653147000, 0.2964189000, 0.6822315000", \ - "0.0724539000, 0.0760328000, 0.0861431000, 0.1101825000, 0.1644874000, 0.2978086000, 0.6808268000", \ - "0.0722021000, 0.0759947000, 0.0864148000, 0.1110386000, 0.1645083000, 0.2948745000, 0.6812536000", \ - "0.0832020000, 0.0867414000, 0.0969233000, 0.1215535000, 0.1752480000, 0.3064942000, 0.6853863000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0212124000, 0.0242440000, 0.0337873000, 0.0629488000, 0.1602957000, 0.4782437000, 1.4988512000", \ - "0.0211156000, 0.0242569000, 0.0337401000, 0.0629747000, 0.1602273000, 0.4772479000, 1.4998170000", \ - "0.0212447000, 0.0243103000, 0.0337221000, 0.0629523000, 0.1601761000, 0.4773742000, 1.4998318000", \ - "0.0209483000, 0.0241264000, 0.0335486000, 0.0628635000, 0.1601849000, 0.4790999000, 1.4979566000", \ - "0.0255908000, 0.0284669000, 0.0372831000, 0.0650258000, 0.1602263000, 0.4785836000, 1.4977234000", \ - "0.0346748000, 0.0379735000, 0.0468573000, 0.0722360000, 0.1632121000, 0.4779467000, 1.4987923000", \ - "0.0493639000, 0.0537031000, 0.0647179000, 0.0902249000, 0.1715210000, 0.4812257000, 1.4947582000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4814524000, 0.4880512000, 0.5059398000, 0.5467170000, 0.6273247000, 0.7850618000, 1.1414849000", \ - "0.4858808000, 0.4926592000, 0.5108335000, 0.5513621000, 0.6321368000, 0.7912473000, 1.1458303000", \ - "0.4962235000, 0.5030342000, 0.5210695000, 0.5616417000, 0.6419189000, 0.8006844000, 1.1561125000", \ - "0.5170325000, 0.5240232000, 0.5416307000, 0.5823564000, 0.6629320000, 0.8207062000, 1.1771996000", \ - "0.5480766000, 0.5549017000, 0.5730827000, 0.6134828000, 0.6944323000, 0.8527376000, 1.2078681000", \ - "0.5875326000, 0.5942907000, 0.6123804000, 0.6528563000, 0.7330578000, 0.8922023000, 1.2478244000", \ - "0.6265203000, 0.6333198000, 0.6510911000, 0.6918228000, 0.7719056000, 0.9307675000, 1.2863484000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1859920000, 0.1897927000, 0.2000394000, 0.2261569000, 0.2985564000, 0.5224918000, 1.2362693000", \ - "0.1908767000, 0.1946669000, 0.2047788000, 0.2309817000, 0.3035386000, 0.5277499000, 1.2379502000", \ - "0.2033538000, 0.2071181000, 0.2173884000, 0.2435227000, 0.3158154000, 0.5396535000, 1.2506183000", \ - "0.2341668000, 0.2379358000, 0.2481810000, 0.2743086000, 0.3466070000, 0.5704756000, 1.2813031000", \ - "0.3027610000, 0.3065543000, 0.3167191000, 0.3429244000, 0.4153952000, 0.6391624000, 1.3508556000", \ - "0.4193662000, 0.4232671000, 0.4336488000, 0.4600224000, 0.5323806000, 0.7561197000, 1.4680581000", \ - "0.5998941000, 0.6041087000, 0.6149200000, 0.6417163000, 0.7143559000, 0.9382359000, 1.6497397000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0726490000, 0.0762534000, 0.0864120000, 0.1101529000, 0.1653603000, 0.2981440000, 0.6810053000", \ - "0.0721360000, 0.0759507000, 0.0861542000, 0.1110741000, 0.1647326000, 0.2964697000, 0.6820527000", \ - "0.0721923000, 0.0757546000, 0.0860047000, 0.1101167000, 0.1646731000, 0.2960906000, 0.6824164000", \ - "0.0723078000, 0.0763712000, 0.0858980000, 0.1101017000, 0.1659597000, 0.2979474000, 0.6812405000", \ - "0.0722932000, 0.0758911000, 0.0862489000, 0.1111356000, 0.1656000000, 0.2972973000, 0.6816234000", \ - "0.0727507000, 0.0763317000, 0.0861100000, 0.1109075000, 0.1642556000, 0.2972553000, 0.6818789000", \ - "0.0722904000, 0.0758540000, 0.0863673000, 0.1117178000, 0.1649278000, 0.2972239000, 0.6809148000"); - } - related_pin : "C_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0218087000, 0.0250004000, 0.0341824000, 0.0629972000, 0.1598815000, 0.4785127000, 1.4991428000", \ - "0.0217802000, 0.0249161000, 0.0342487000, 0.0631507000, 0.1598189000, 0.4790498000, 1.4963811000", \ - "0.0219267000, 0.0250543000, 0.0341753000, 0.0630822000, 0.1597060000, 0.4783973000, 1.4976236000", \ - "0.0219193000, 0.0250534000, 0.0341565000, 0.0630774000, 0.1597167000, 0.4784175000, 1.4965738000", \ - "0.0218762000, 0.0250224000, 0.0343203000, 0.0631943000, 0.1596866000, 0.4788153000, 1.4982212000", \ - "0.0230201000, 0.0260905000, 0.0354149000, 0.0638265000, 0.1597345000, 0.4779325000, 1.4998026000", \ - "0.0253622000, 0.0282164000, 0.0372846000, 0.0652145000, 0.1606083000, 0.4780438000, 1.4983639000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.4113687000, 0.4182398000, 0.4364133000, 0.4770586000, 0.5577417000, 0.7165714000, 1.0722918000", \ - "0.4160480000, 0.4230944000, 0.4411795000, 0.4814968000, 0.5620606000, 0.7203069000, 1.0766676000", \ - "0.4259706000, 0.4328013000, 0.4508303000, 0.4914631000, 0.5725275000, 0.7310863000, 1.0868790000", \ - "0.4440391000, 0.4509019000, 0.4690742000, 0.5095431000, 0.5905090000, 0.7491668000, 1.1049271000", \ - "0.4705696000, 0.4773755000, 0.4954152000, 0.5357402000, 0.6162443000, 0.7754628000, 1.1312568000", \ - "0.5029040000, 0.5096907000, 0.5274756000, 0.5680610000, 0.6482844000, 0.8070239000, 1.1626887000", \ - "0.5293653000, 0.5361326000, 0.5539668000, 0.5945870000, 0.6752491000, 0.8343517000, 1.1900146000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1698024000, 0.1736492000, 0.1838699000, 0.2101942000, 0.2826311000, 0.5067004000, 1.2186760000", \ - "0.1745785000, 0.1783878000, 0.1886952000, 0.2149130000, 0.2875008000, 0.5112176000, 1.2232115000", \ - "0.1871268000, 0.1909729000, 0.2012173000, 0.2275355000, 0.2999719000, 0.5241123000, 1.2355625000", \ - "0.2180333000, 0.2218225000, 0.2321404000, 0.2584232000, 0.3309350000, 0.5553011000, 1.2663230000", \ - "0.2848574000, 0.2886782000, 0.2989908000, 0.3252992000, 0.3977560000, 0.6218513000, 1.3361262000", \ - "0.3947393000, 0.3985365000, 0.4091761000, 0.4356923000, 0.5083052000, 0.7319019000, 1.4424935000", \ - "0.5656547000, 0.5698811000, 0.5808828000, 0.6077744000, 0.6805674000, 0.9039648000, 1.6146382000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0723854000, 0.0758300000, 0.0858290000, 0.1107917000, 0.1647137000, 0.2970560000, 0.6814306000", \ - "0.0723610000, 0.0763776000, 0.0861466000, 0.1101401000, 0.1658108000, 0.2957355000, 0.6824168000", \ - "0.0722451000, 0.0758705000, 0.0860827000, 0.1111258000, 0.1655060000, 0.2971102000, 0.6814723000", \ - "0.0723541000, 0.0758285000, 0.0861063000, 0.1109310000, 0.1651843000, 0.2970415000, 0.6814411000", \ - "0.0721648000, 0.0756769000, 0.0861227000, 0.1115823000, 0.1644966000, 0.2967940000, 0.6812094000", \ - "0.0723374000, 0.0756896000, 0.0860888000, 0.1102542000, 0.1639874000, 0.2977416000, 0.6811717000", \ - "0.0728397000, 0.0764906000, 0.0863225000, 0.1106766000, 0.1667904000, 0.2972221000, 0.6794208000"); - } - related_pin : "D_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0217570000, 0.0248610000, 0.0342149000, 0.0630831000, 0.1597693000, 0.4794522000, 1.5029549000", \ - "0.0218142000, 0.0249549000, 0.0341084000, 0.0631206000, 0.1597120000, 0.4785745000, 1.4963969000", \ - "0.0217495000, 0.0248525000, 0.0342109000, 0.0630831000, 0.1597633000, 0.4794579000, 1.5022675000", \ - "0.0217714000, 0.0250244000, 0.0342766000, 0.0630864000, 0.1597606000, 0.4790419000, 1.5020313000", \ - "0.0220228000, 0.0251270000, 0.0343131000, 0.0632025000, 0.1594542000, 0.4795755000, 1.5006705000", \ - "0.0231872000, 0.0263526000, 0.0354924000, 0.0638338000, 0.1594683000, 0.4779163000, 1.4982195000", \ - "0.0258885000, 0.0289159000, 0.0376788000, 0.0656430000, 0.1603951000, 0.4780669000, 1.4933494000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__probe_p_8") { - leakage_power () { - value : 0.0076474000; - when : "A"; - } - leakage_power () { - value : 0.0071930000; - when : "!A"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__probe"; - cell_leakage_power : 0.0074202000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0068580000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0064810000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0072350000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017611720, 0.0062034510, 0.0218506800, 0.0769656000, 0.2710993000, 0.9549047000"); - values("0.0622895000, 0.0605814000, 0.0544048000, 0.0324054000, -0.052368100, -0.365511200, -1.473029600", \ - "0.0618556000, 0.0600657000, 0.0538991000, 0.0317923000, -0.052813700, -0.366054700, -1.473527600", \ - "0.0610432000, 0.0592876000, 0.0531525000, 0.0310888000, -0.053696100, -0.366735400, -1.474185800", \ - "0.0606309000, 0.0588453000, 0.0524092000, 0.0300072000, -0.054636200, -0.367296500, -1.474523300", \ - "0.0602371000, 0.0582274000, 0.0516387000, 0.0288377000, -0.055825900, -0.367943600, -1.474959500", \ - "0.0656617000, 0.0634970000, 0.0561417000, 0.0311548000, -0.054832900, -0.366409300, -1.473002300", \ - "0.0734927000, 0.0711778000, 0.0634754000, 0.0375790000, -0.051368800, -0.363269900, -1.468732800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017611720, 0.0062034510, 0.0218506800, 0.0769656000, 0.2710993000, 0.9549047000"); - values("0.0451391000, 0.0474162000, 0.0554099000, 0.0824942000, 0.1724581000, 0.4842208000, 1.5728390000", \ - "0.0447396000, 0.0470680000, 0.0550859000, 0.0821114000, 0.1721294000, 0.4839237000, 1.5726384000", \ - "0.0440728000, 0.0463563000, 0.0542942000, 0.0812141000, 0.1713500000, 0.4836590000, 1.5730391000", \ - "0.0432236000, 0.0453292000, 0.0530304000, 0.0795258000, 0.1697947000, 0.4823883000, 1.5757843000", \ - "0.0432728000, 0.0453501000, 0.0526315000, 0.0788219000, 0.1677390000, 0.4812552000, 1.5803099000", \ - "0.0459963000, 0.0480276000, 0.0552657000, 0.0810059000, 0.1683220000, 0.4803318000, 1.5779272000", \ - "0.0502955000, 0.0523045000, 0.0592626000, 0.0843225000, 0.1740387000, 0.4829633000, 1.5762310000"); - } - } - max_capacitance : 0.9549050000; - max_transition : 1.5044370000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017611700, 0.0062034500, 0.0218507000, 0.0769656000, 0.2710990000, 0.9549050000"); - values("0.0924138000, 0.0942745000, 0.0998980000, 0.1144363000, 0.1489349000, 0.2437060000, 0.5619730000", \ - "0.0976607000, 0.0995028000, 0.1050784000, 0.1196035000, 0.1542219000, 0.2490145000, 0.5680530000", \ - "0.1107395000, 0.1125685000, 0.1181300000, 0.1325987000, 0.1672496000, 0.2620608000, 0.5791334000", \ - "0.1426086000, 0.1444290000, 0.1499999000, 0.1644296000, 0.1991952000, 0.2939871000, 0.6117148000", \ - "0.2123448000, 0.2143543000, 0.2203816000, 0.2356629000, 0.2711181000, 0.3664452000, 0.6837273000", \ - "0.3276238000, 0.3302272000, 0.3380289000, 0.3575314000, 0.3988462000, 0.4979497000, 0.8154331000", \ - "0.5136958000, 0.5170795000, 0.5268898000, 0.5523799000, 0.6050651000, 0.7134495000, 1.0317767000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017611700, 0.0062034500, 0.0218507000, 0.0769656000, 0.2710990000, 0.9549050000"); - values("0.0635825000, 0.0657178000, 0.0724726000, 0.0925350000, 0.1540215000, 0.3624511000, 1.0953717000", \ - "0.0680506000, 0.0701895000, 0.0769417000, 0.0969815000, 0.1585103000, 0.3670883000, 1.0999232000", \ - "0.0790158000, 0.0811445000, 0.0878815000, 0.1077841000, 0.1692221000, 0.3788083000, 1.1117396000", \ - "0.1014748000, 0.1035378000, 0.1103380000, 0.1303697000, 0.1920434000, 0.4021067000, 1.1465204000", \ - "0.1323746000, 0.1347792000, 0.1420951000, 0.1628644000, 0.2248242000, 0.4347874000, 1.1709790000", \ - "0.1642623000, 0.1673212000, 0.1764079000, 0.1997093000, 0.2623169000, 0.4721299000, 1.2075360000", \ - "0.1760921000, 0.1803185000, 0.1924803000, 0.2220296000, 0.2899175000, 0.4991161000, 1.2307121000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017611700, 0.0062034500, 0.0218507000, 0.0769656000, 0.2710990000, 0.9549050000"); - values("0.0189957000, 0.0201414000, 0.0237213000, 0.0344482000, 0.0693112000, 0.1913538000, 0.6407144000", \ - "0.0189328000, 0.0199887000, 0.0237180000, 0.0345681000, 0.0692889000, 0.1914760000, 0.6409532000", \ - "0.0189702000, 0.0201096000, 0.0236086000, 0.0347341000, 0.0691484000, 0.1913769000, 0.6415924000", \ - "0.0188566000, 0.0199720000, 0.0237530000, 0.0347965000, 0.0691623000, 0.1913519000, 0.6414224000", \ - "0.0229019000, 0.0240010000, 0.0276087000, 0.0376960000, 0.0707743000, 0.1915525000, 0.6406566000", \ - "0.0343393000, 0.0357048000, 0.0404984000, 0.0506358000, 0.0817337000, 0.1967624000, 0.6414947000", \ - "0.0529024000, 0.0542052000, 0.0595578000, 0.0735878000, 0.1040412000, 0.2094993000, 0.6441095000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017611700, 0.0062034500, 0.0218507000, 0.0769656000, 0.2710990000, 0.9549050000"); - values("0.0189956000, 0.0209287000, 0.0275318000, 0.0509672000, 0.1354251000, 0.4388659000, 1.5022044000", \ - "0.0189951000, 0.0209063000, 0.0275563000, 0.0509779000, 0.1354216000, 0.4388667000, 1.5028147000", \ - "0.0188858000, 0.0208364000, 0.0274939000, 0.0508846000, 0.1354411000, 0.4377557000, 1.5013618000", \ - "0.0200985000, 0.0220609000, 0.0286084000, 0.0515271000, 0.1354846000, 0.4387426000, 1.5040995000", \ - "0.0242878000, 0.0262493000, 0.0323006000, 0.0541901000, 0.1364057000, 0.4381334000, 1.5030882000", \ - "0.0338962000, 0.0356078000, 0.0414634000, 0.0613044000, 0.1387830000, 0.4370559000, 1.5044372000", \ - "0.0491830000, 0.0517168000, 0.0587880000, 0.0787191000, 0.1469583000, 0.4390466000, 1.4978067000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__probec_p_8") { - leakage_power () { - value : 0.0076474000; - when : "A"; - } - leakage_power () { - value : 0.0071930000; - when : "!A"; - } - area : 15.014400000; - cell_footprint : "sky130_fd_sc_hd__probe"; - cell_leakage_power : 0.0074202010; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0068760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0064970000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0072550000; - } - pin ("X") { - direction : "output"; - function : "(A)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017603260, 0.0061974980, 0.0218192400, 0.0768179500, 0.2704493000, 0.9521582000"); - values("0.0634374000, 0.0617386000, 0.0555443000, 0.0335947000, -0.051078400, -0.363421900, -1.467559700", \ - "0.0629690000, 0.0612538000, 0.0550243000, 0.0329447000, -0.051547500, -0.363975000, -1.468032300", \ - "0.0623317000, 0.0604586000, 0.0542703000, 0.0322609000, -0.052446800, -0.364650700, -1.468692700", \ - "0.0617739000, 0.0598936000, 0.0536563000, 0.0312277000, -0.053371600, -0.365221100, -1.469075100", \ - "0.0611810000, 0.0592690000, 0.0526855000, 0.0299773000, -0.054556700, -0.365879600, -1.469503800", \ - "0.0665203000, 0.0643923000, 0.0570864000, 0.0321664000, -0.053507500, -0.364326800, -1.467515000", \ - "0.0743038000, 0.0721085000, 0.0644661000, 0.0386015000, -0.050121100, -0.361191700, -1.463284600"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0017603260, 0.0061974980, 0.0218192400, 0.0768179500, 0.2704493000, 0.9521582000"); - values("0.0476144000, 0.0499127000, 0.0578641000, 0.0848404000, 0.1746167000, 0.4855519000, 1.5709645000", \ - "0.0472654000, 0.0495588000, 0.0575478000, 0.0844608000, 0.1742746000, 0.4852779000, 1.5715530000", \ - "0.0465471000, 0.0488400000, 0.0567293000, 0.0834580000, 0.1734183000, 0.4849768000, 1.5794954000", \ - "0.0455640000, 0.0477477000, 0.0554152000, 0.0818461000, 0.1719253000, 0.4837568000, 1.5741857000", \ - "0.0456239000, 0.0476954000, 0.0549609000, 0.0811519000, 0.1698602000, 0.4825533000, 1.5781935000", \ - "0.0483403000, 0.0504220000, 0.0576189000, 0.0833383000, 0.1704524000, 0.4817652000, 1.5760331000", \ - "0.0525851000, 0.0546115000, 0.0615615000, 0.0865869000, 0.1761390000, 0.4843847000, 1.5745184000"); - } - } - max_capacitance : 0.9521580000; - max_transition : 1.5040770000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017603300, 0.0061975000, 0.0218192000, 0.0768180000, 0.2704490000, 0.9521580000"); - values("0.0942042000, 0.0960177000, 0.1014240000, 0.1157263000, 0.1500981000, 0.2447823000, 0.5624339000", \ - "0.0994468000, 0.1012048000, 0.1066015000, 0.1209511000, 0.1553909000, 0.2500795000, 0.5684906000", \ - "0.1125246000, 0.1142509000, 0.1196411000, 0.1338919000, 0.1684253000, 0.2631732000, 0.5797342000", \ - "0.1443640000, 0.1461613000, 0.1515220000, 0.1656828000, 0.2003530000, 0.2950457000, 0.6121476000", \ - "0.2143684000, 0.2162786000, 0.2220858000, 0.2370737000, 0.2724138000, 0.3676189000, 0.6842659000", \ - "0.3304008000, 0.3328838000, 0.3403942000, 0.3594773000, 0.4005324000, 0.4995078000, 0.8171905000", \ - "0.5174970000, 0.5207534000, 0.5302278000, 0.5551175000, 0.6074435000, 0.7156757000, 1.0333764000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017603300, 0.0061975000, 0.0218192000, 0.0768180000, 0.2704490000, 0.9521580000"); - values("0.0653439000, 0.0674101000, 0.0740063000, 0.0938897000, 0.1552510000, 0.3632559000, 1.0940907000", \ - "0.0698149000, 0.0718824000, 0.0784769000, 0.0983340000, 0.1597374000, 0.3679069000, 1.0985428000", \ - "0.0807709000, 0.0828353000, 0.0894415000, 0.1091205000, 0.1703654000, 0.3794295000, 1.1135501000", \ - "0.1032375000, 0.1053225000, 0.1120587000, 0.1318377000, 0.1933392000, 0.4020118000, 1.1464060000", \ - "0.1345890000, 0.1368917000, 0.1439765000, 0.1645344000, 0.2263341000, 0.4358948000, 1.1706597000", \ - "0.1671966000, 0.1702742000, 0.1788294000, 0.2017326000, 0.2641400000, 0.4737720000, 1.2053614000", \ - "0.1802034000, 0.1842061000, 0.1958933000, 0.2247511000, 0.2922562000, 0.5010486000, 1.2307643000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017603300, 0.0061975000, 0.0218192000, 0.0768180000, 0.2704490000, 0.9521580000"); - values("0.0198471000, 0.0209313000, 0.0245007000, 0.0351507000, 0.0700021000, 0.1921730000, 0.6411099000", \ - "0.0199004000, 0.0208283000, 0.0244517000, 0.0352580000, 0.0700214000, 0.1923177000, 0.6416255000", \ - "0.0197385000, 0.0208729000, 0.0243874000, 0.0354456000, 0.0699904000, 0.1922434000, 0.6421572000", \ - "0.0197353000, 0.0208278000, 0.0244204000, 0.0352618000, 0.0698508000, 0.1922412000, 0.6424374000", \ - "0.0237299000, 0.0247815000, 0.0281189000, 0.0383310000, 0.0713657000, 0.1924181000, 0.6419282000", \ - "0.0353967000, 0.0367335000, 0.0413891000, 0.0512931000, 0.0824393000, 0.1976763000, 0.6426835000", \ - "0.0543778000, 0.0553964000, 0.0605942000, 0.0743314000, 0.1048237000, 0.2103882000, 0.6454478000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0017603300, 0.0061975000, 0.0218192000, 0.0768180000, 0.2704490000, 0.9521580000"); - values("0.0203276000, 0.0222889000, 0.0288060000, 0.0522811000, 0.1367363000, 0.4397571000, 1.5009517000", \ - "0.0202727000, 0.0222907000, 0.0288357000, 0.0522811000, 0.1367262000, 0.4398756000, 1.4970136000", \ - "0.0202322000, 0.0221403000, 0.0288670000, 0.0522361000, 0.1364673000, 0.4379042000, 1.5018451000", \ - "0.0214578000, 0.0233496000, 0.0298924000, 0.0527878000, 0.1367721000, 0.4400098000, 1.5032039000", \ - "0.0257139000, 0.0274525000, 0.0335479000, 0.0554898000, 0.1377086000, 0.4390920000, 1.5027904000", \ - "0.0351108000, 0.0371674000, 0.0426504000, 0.0624961000, 0.1400769000, 0.4380077000, 1.5040770000", \ - "0.0511390000, 0.0533120000, 0.0601438000, 0.0798873000, 0.1481365000, 0.4401725000, 1.4965561000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfbbn_1") { - leakage_power () { - value : 0.0172358000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146049000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0149422000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0143071000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0215746000; - when : "!SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0123004000; - when : "SET_B&!RESET_B&!CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0167092000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0170489000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0158918000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0177373000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0155880000; - when : "!SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0148924000; - when : "SET_B&!RESET_B&!CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0149835000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146438000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0167733000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0142682000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0220577000; - when : "!SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0122615000; - when : "SET_B&!RESET_B&!CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0165870000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146468000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0229399000; - when : "!SET_B&RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0126401000; - when : "SET_B&!RESET_B&!CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0152003000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146056000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0218549000; - when : "!SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125989000; - when : "SET_B&!RESET_B&!CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0170077000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0172786000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0179273000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0157018000; - when : "SET_B&RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0135525000; - when : "!SET_B&RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0128569000; - when : "SET_B&!RESET_B&!CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0166703000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0172749000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0151245000; - when : "!SET_B&RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0144300000; - when : "SET_B&!RESET_B&!CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0174649000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0170885000; - when : "SET_B&RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0149393000; - when : "!SET_B&RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142436000; - when : "SET_B&!RESET_B&!CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0143587000; - when : "!SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0135134000; - when : "!SET_B&!RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0221050000; - when : "!SET_B&RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0143198000; - when : "!SET_B&RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0146571000; - when : "!SET_B&RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0157466000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0130924000; - when : "!SET_B&!RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0138118000; - when : "!SET_B&!RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0200891000; - when : "!SET_B&RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0226642000; - when : "!SET_B&RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0160450000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0133908000; - when : "!SET_B&!RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0134745000; - when : "!SET_B&!RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0146984000; - when : "!SET_B&RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0157077000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0130535000; - when : "!SET_B&!RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142690000; - when : "!SET_B&!RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0219799000; - when : "!SET_B&RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0140791000; - when : "!SET_B&!RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0147315000; - when : "!SET_B&!RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0145416000; - when : "!SET_B&!RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0126960000; - when : "!SET_B&!RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125061000; - when : "!SET_B&!RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0138531000; - when : "!SET_B&!RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0160863000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0134321000; - when : "!SET_B&!RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0140827000; - when : "!SET_B&!RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0138928000; - when : "!SET_B&!RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0119638000; - when : "SET_B&!RESET_B&CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0136625000; - when : "SET_B&!RESET_B&CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119249000; - when : "SET_B&!RESET_B&CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0122622000; - when : "SET_B&!RESET_B&CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116271000; - when : "SET_B&!RESET_B&CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0132001000; - when : "SET_B&!RESET_B&CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0123035000; - when : "SET_B&!RESET_B&CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0130138000; - when : "SET_B&!RESET_B&CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0163970000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0168594000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0148239000; - when : "SET_B&RESET_B&CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0162106000; - when : "SET_B&RESET_B&CLK_N&D&SCD&SCE&!Q&Q_N"; - } - area : 38.787200000; - cell_footprint : "sky130_fd_sc_hd__sdfbbn"; - cell_leakage_power : 0.0153947700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0017800000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016980000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0352985000, 0.0351707000, 0.0348760000, 0.0349577000, 0.0351461000, 0.0355805000, 0.0365816000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0171088000, 0.0170354000, 0.0168662000, 0.0168729000, 0.0168886000, 0.0169248000, 0.0170082000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018610000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2763402000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2554685000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015380000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0077526000, 0.0076310000, 0.0073507000, 0.0073814000, 0.0074524000, 0.0076161000, 0.0079935000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0024391000, 0.0024142000, 0.0023569000, 0.0023653000, 0.0023851000, 0.0024307000, 0.0025357000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016000000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3645488000, 0.5653464000, 0.9539369000", \ - "0.2321107000, 0.4316875000, 0.8153952000", \ - "0.0803366000, 0.2799134000, 0.6489726000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1265117000, 0.2552878000, 0.3594544000", \ - "-0.088934200, 0.0410625000, 0.1452292000", \ - "-0.332261100, -0.202264300, -0.095656300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.337355500, -0.536932300, -0.920640000", \ - "-0.203696600, -0.405714800, -0.778436200", \ - "-0.051922500, -0.249058000, -0.613234400"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0105449000, -0.121893200, -0.224839200", \ - "0.2076803000, 0.0813457000, -0.021600300", \ - "0.4400208000, 0.3197897000, 0.2241680000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002198500, 0.0037534000, 0.0149741000, 0.0280046000, 0.0262565000, -0.022179900, -0.184126900", \ - "-0.002162100, 0.0037859000, 0.0149829000, 0.0279875000, 0.0262240000, -0.022237900, -0.184193200", \ - "-0.002067700, 0.0038642000, 0.0150567000, 0.0280515000, 0.0262139000, -0.022270500, -0.184250500", \ - "-0.002099800, 0.0038251000, 0.0150034000, 0.0279769000, 0.0261192000, -0.022378500, -0.184336800", \ - "-0.002177900, 0.0037263000, 0.0148614000, 0.0277705000, 0.0258456000, -0.022683000, -0.184708800", \ - "-0.002318700, 0.0035910000, 0.0147253000, 0.0276510000, 0.0257518000, -0.022812300, -0.184831400", \ - "-0.002595200, 0.0033983000, 0.0147082000, 0.0278629000, 0.0258811000, -0.022954000, -0.184924500"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0058975000, 0.0106990000, 0.0195756000, 0.0290990000, 0.0238519000, -0.026856600, -0.189977200", \ - "0.0059261000, 0.0107291000, 0.0195943000, 0.0291190000, 0.0238438000, -0.026824300, -0.189958600", \ - "0.0059964000, 0.0107843000, 0.0196536000, 0.0291607000, 0.0238544000, -0.026829800, -0.189929400", \ - "0.0059691000, 0.0107229000, 0.0195125000, 0.0288971000, 0.0234970000, -0.027329800, -0.190454600", \ - "0.0059451000, 0.0106509000, 0.0193564000, 0.0286146000, 0.0230464000, -0.027891400, -0.191095200", \ - "0.0059325000, 0.0106100000, 0.0192495000, 0.0284130000, 0.0227373000, -0.028427000, -0.191648800", \ - "0.0060279000, 0.0108054000, 0.0196563000, 0.0291209000, 0.0234945000, -0.028478000, -0.191723500"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-2.38500e-05, 0.0037460000, 0.0121705000, 0.0299111000, 0.0626484000, 0.1315236000, 0.3016503000", \ - "-2.81500e-05, 0.0037192000, 0.0121021000, 0.0298094000, 0.0623686000, 0.1317485000, 0.3029338000", \ - "-3.17500e-05, 0.0036949000, 0.0120390000, 0.0296431000, 0.0621678000, 0.1311216000, 0.3018503000", \ - "-4.85500e-05, 0.0036639000, 0.0119808000, 0.0295362000, 0.0620187000, 0.1306450000, 0.3010041000", \ - "-8.30000e-05, 0.0036026000, 0.0118631000, 0.0293451000, 0.0617420000, 0.1303252000, 0.3006715000", \ - "-0.000144200, 0.0035069000, 0.0117038000, 0.0290739000, 0.0613879000, 0.1302169000, 0.3003291000", \ - "-0.000225800, 0.0034349000, 0.0116261000, 0.0292045000, 0.0618841000, 0.1305960000, 0.3021346000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.013849200, -0.008560200, 0.0013205000, 0.0123290000, 0.0082481000, -0.042467900, -0.205210700", \ - "-0.013786400, -0.008506100, 0.0013674000, 0.0123644000, 0.0082888000, -0.042443400, -0.205208600", \ - "-0.013655000, -0.008386100, 0.0014485000, 0.0124050000, 0.0082636000, -0.042495300, -0.205270700", \ - "-0.013706800, -0.008453300, 0.0013475000, 0.0122435000, 0.0080546000, -0.042715300, -0.205504600", \ - "-0.013810500, -0.008574000, 0.0011991000, 0.0120582000, 0.0078425000, -0.042961400, -0.205764600", \ - "-0.014024500, -0.008793100, 0.0009638000, 0.0118285000, 0.0076084000, -0.043221000, -0.206021400", \ - "-0.014474000, -0.009156800, 0.0007641000, 0.0118691000, 0.0079140000, -0.042713400, -0.205426400"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.015326800, -0.011828900, -0.003889800, 0.0124071000, 0.0435541000, 0.1119006000, 0.2833293000", \ - "-0.015271300, -0.011782800, -0.003863300, 0.0124251000, 0.0434770000, 0.1113227000, 0.2830338000", \ - "-0.015135300, -0.011667600, -0.003791200, 0.0124476000, 0.0435020000, 0.1118844000, 0.2810133000", \ - "-0.015186800, -0.011733800, -0.003885500, 0.0123234000, 0.0433342000, 0.1117192000, 0.2826652000", \ - "-0.015295500, -0.011860300, -0.004057500, 0.0120711000, 0.0430492000, 0.1114190000, 0.2810114000", \ - "-0.015510200, -0.012069300, -0.004253400, 0.0118812000, 0.0429003000, 0.1112798000, 0.2808841000", \ - "-0.015915200, -0.012341500, -0.004318300, 0.0117309000, 0.0431955000, 0.1115013000, 0.2813659000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5046930000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.5271879000, 0.5325163000, 0.5436975000, 0.5669758000, 0.6193985000, 0.7530651000, 1.1059061000", \ - "0.5321922000, 0.5375186000, 0.5487018000, 0.5719820000, 0.6243989000, 0.7581668000, 1.1114801000", \ - "0.5447750000, 0.5500922000, 0.5612845000, 0.5845679000, 0.6370309000, 0.7707437000, 1.1234895000", \ - "0.5756007000, 0.5808761000, 0.5920943000, 0.6153251000, 0.6678277000, 0.8015105000, 1.1539816000", \ - "0.6465475000, 0.6518199000, 0.6630405000, 0.6862705000, 0.7387712000, 0.8723186000, 1.2249257000", \ - "0.7761560000, 0.7814284000, 0.7926571000, 0.8159200000, 0.8682440000, 1.0019224000, 1.3543053000", \ - "0.9773080000, 0.9825852000, 0.9938341000, 1.0170612000, 1.0695298000, 1.2031574000, 1.5562360000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4235908000, 0.4303007000, 0.4454420000, 0.4812081000, 0.5742897000, 0.8187677000, 1.4644064000", \ - "0.4286662000, 0.4353461000, 0.4504404000, 0.4864014000, 0.5793037000, 0.8235565000, 1.4722401000", \ - "0.4412278000, 0.4479510000, 0.4630744000, 0.4988842000, 0.5921220000, 0.8368643000, 1.4852174000", \ - "0.4722497000, 0.4788488000, 0.4940149000, 0.5298627000, 0.6232085000, 0.8678444000, 1.5114003000", \ - "0.5428700000, 0.5495233000, 0.5646549000, 0.6004853000, 0.6938104000, 0.9384565000, 1.5834956000", \ - "0.6692115000, 0.6759086000, 0.6910800000, 0.7269587000, 0.8202475000, 1.0649750000, 1.7099312000", \ - "0.8641887000, 0.8708219000, 0.8858400000, 0.9218897000, 1.0149989000, 1.2589693000, 1.9048541000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0178546000, 0.0216661000, 0.0311660000, 0.0544873000, 0.1185079000, 0.2937173000, 0.7617093000", \ - "0.0176061000, 0.0216885000, 0.0311673000, 0.0544927000, 0.1182158000, 0.2937795000, 0.7640682000", \ - "0.0176528000, 0.0217984000, 0.0311894000, 0.0545059000, 0.1181383000, 0.2936824000, 0.7617804000", \ - "0.0176188000, 0.0217079000, 0.0312586000, 0.0546161000, 0.1180002000, 0.2936952000, 0.7659091000", \ - "0.0176137000, 0.0216634000, 0.0312416000, 0.0545019000, 0.1181276000, 0.2939358000, 0.7656695000", \ - "0.0175430000, 0.0217129000, 0.0312011000, 0.0545378000, 0.1182536000, 0.2938302000, 0.7650140000", \ - "0.0176337000, 0.0216594000, 0.0309653000, 0.0544278000, 0.1183953000, 0.2938934000, 0.7685171000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0232978000, 0.0295765000, 0.0465064000, 0.0946410000, 0.2265447000, 0.5754117000, 1.5026856000", \ - "0.0234848000, 0.0296225000, 0.0464747000, 0.0944869000, 0.2264113000, 0.5750624000, 1.5045718000", \ - "0.0233643000, 0.0295607000, 0.0464747000, 0.0945168000, 0.2263061000, 0.5753233000, 1.5028371000", \ - "0.0235687000, 0.0297767000, 0.0466145000, 0.0944561000, 0.2259604000, 0.5746931000, 1.5046934000", \ - "0.0235661000, 0.0295917000, 0.0466156000, 0.0945248000, 0.2261588000, 0.5747037000, 1.5006447000", \ - "0.0236305000, 0.0297841000, 0.0466114000, 0.0943436000, 0.2264104000, 0.5749078000, 1.5007792000", \ - "0.0234834000, 0.0296178000, 0.0466203000, 0.0946091000, 0.2266867000, 0.5748321000, 1.5022009000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2978866000, 0.3032184000, 0.3145875000, 0.3380233000, 0.3905632000, 0.5243886000, 0.8767521000", \ - "0.3029783000, 0.3083079000, 0.3196848000, 0.3431185000, 0.3956774000, 0.5294780000, 0.8818143000", \ - "0.3160603000, 0.3214318000, 0.3327819000, 0.3562264000, 0.4087826000, 0.5424808000, 0.8948634000", \ - "0.3467882000, 0.3521592000, 0.3635149000, 0.3869538000, 0.4395163000, 0.5732105000, 0.9256036000", \ - "0.4169701000, 0.4223417000, 0.4336925000, 0.4571388000, 0.5096978000, 0.6434018000, 0.9957870000", \ - "0.5433883000, 0.5487142000, 0.5601166000, 0.5835254000, 0.6361917000, 0.7699676000, 1.1222163000", \ - "0.7431421000, 0.7485184000, 0.7599286000, 0.7834417000, 0.8360832000, 0.9700245000, 1.3221513000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0180065000, 0.0221851000, 0.0315205000, 0.0549911000, 0.1184127000, 0.2935674000, 0.7632898000", \ - "0.0179834000, 0.0222108000, 0.0315259000, 0.0549930000, 0.1182627000, 0.2936079000, 0.7632289000", \ - "0.0181622000, 0.0219577000, 0.0316984000, 0.0549649000, 0.1184239000, 0.2936101000, 0.7626175000", \ - "0.0181545000, 0.0219614000, 0.0317114000, 0.0549256000, 0.1184201000, 0.2936374000, 0.7618690000", \ - "0.0181680000, 0.0219578000, 0.0316970000, 0.0549741000, 0.1184334000, 0.2936175000, 0.7639508000", \ - "0.0181473000, 0.0219826000, 0.0316739000, 0.0551408000, 0.1182856000, 0.2937706000, 0.7630832000", \ - "0.0182479000, 0.0222445000, 0.0319002000, 0.0551875000, 0.1185495000, 0.2938148000, 0.7620821000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2008971000, 0.2062183000, 0.2175801000, 0.2409528000, 0.2936371000, 0.4273710000, 0.7797606000", \ - "0.2056842000, 0.2110098000, 0.2223933000, 0.2458121000, 0.2983324000, 0.4322345000, 0.7845532000", \ - "0.2156088000, 0.2209357000, 0.2323121000, 0.2556763000, 0.3082510000, 0.4421422000, 0.7946762000", \ - "0.2369373000, 0.2422815000, 0.2535799000, 0.2770516000, 0.3296282000, 0.4635398000, 0.8159630000", \ - "0.2838564000, 0.2892594000, 0.3005884000, 0.3240041000, 0.3766918000, 0.5104800000, 0.8628802000", \ - "0.3620937000, 0.3676259000, 0.3792121000, 0.4029241000, 0.4557809000, 0.5895894000, 0.9420499000", \ - "0.4603350000, 0.4663055000, 0.4783611000, 0.5028545000, 0.5564444000, 0.6901255000, 1.0423862000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3276546000, 0.3350237000, 0.3508033000, 0.3871102000, 0.4802264000, 0.7247404000, 1.3700544000", \ - "0.3327727000, 0.3401441000, 0.3559149000, 0.3922503000, 0.4853675000, 0.7299890000, 1.3756537000", \ - "0.3457020000, 0.3530688000, 0.3688942000, 0.4052462000, 0.4983043000, 0.7427454000, 1.3876793000", \ - "0.3774573000, 0.3848171000, 0.4006462000, 0.4369908000, 0.5300570000, 0.7745041000, 1.4194902000", \ - "0.4535958000, 0.4609656000, 0.4767878000, 0.5131386000, 0.6061973000, 0.8506365000, 1.4955793000", \ - "0.6319373000, 0.6393049000, 0.6550989000, 0.6914371000, 0.7845074000, 1.0290599000, 1.6730474000", \ - "0.9833981000, 0.9915960000, 1.0085460000, 1.0454266000, 1.1383583000, 1.3830861000, 2.0274944000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0179513000, 0.0222611000, 0.0316068000, 0.0549379000, 0.1180480000, 0.2938566000, 0.7631972000", \ - "0.0179637000, 0.0222272000, 0.0315288000, 0.0550420000, 0.1181498000, 0.2936155000, 0.7624963000", \ - "0.0180001000, 0.0222417000, 0.0315453000, 0.0549772000, 0.1181535000, 0.2936585000, 0.7631875000", \ - "0.0180395000, 0.0221524000, 0.0314967000, 0.0550079000, 0.1182615000, 0.2937229000, 0.7636483000", \ - "0.0183453000, 0.0223186000, 0.0317214000, 0.0550778000, 0.1181630000, 0.2937464000, 0.7631251000", \ - "0.0188829000, 0.0228684000, 0.0324639000, 0.0558038000, 0.1189934000, 0.2938345000, 0.7634449000", \ - "0.0212837000, 0.0252278000, 0.0350584000, 0.0573914000, 0.1198547000, 0.2940320000, 0.7596007000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0264957000, 0.0325905000, 0.0486926000, 0.0955319000, 0.2264795000, 0.5744523000, 1.4998791000", \ - "0.0264818000, 0.0325764000, 0.0486082000, 0.0954426000, 0.2265792000, 0.5751422000, 1.5012643000", \ - "0.0265474000, 0.0325487000, 0.0486207000, 0.0955235000, 0.2265272000, 0.5751812000, 1.4988311000", \ - "0.0265216000, 0.0325185000, 0.0486181000, 0.0954852000, 0.2265340000, 0.5751048000, 1.4964784000", \ - "0.0265718000, 0.0325629000, 0.0486251000, 0.0955246000, 0.2265282000, 0.5751745000, 1.4960945000", \ - "0.0265926000, 0.0326350000, 0.0486670000, 0.0954848000, 0.2262206000, 0.5758743000, 1.5004143000", \ - "0.0315405000, 0.0370296000, 0.0520560000, 0.0966625000, 0.2266153000, 0.5747501000, 1.4992759000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.013700500, -0.008366300, 0.0014268000, 0.0123958000, 0.0094852000, -0.035799700, -0.182198200", \ - "-0.013639600, -0.008306800, 0.0014759000, 0.0124207000, 0.0095453000, -0.035756300, -0.182166400", \ - "-0.013501700, -0.008184600, 0.0015672000, 0.0124929000, 0.0095252000, -0.035759000, -0.182167700", \ - "-0.013557600, -0.008263100, 0.0014573000, 0.0123177000, 0.0092990000, -0.036079900, -0.182517300", \ - "-0.013667100, -0.008396200, 0.0012831000, 0.0120785000, 0.0090005000, -0.036415200, -0.182865700", \ - "-0.013885800, -0.008616400, 0.0010529000, 0.0118212000, 0.0087437000, -0.036662300, -0.183125100", \ - "-0.014360700, -0.009057300, 0.0006958000, 0.0116031000, 0.0086405000, -0.036459500, -0.182900100"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.015158400, -0.011522300, -0.003505100, 0.0122976000, 0.0419219000, 0.1050987000, 0.2589431000", \ - "-0.015103000, -0.011478700, -0.003483000, 0.0122815000, 0.0417945000, 0.1049681000, 0.2602484000", \ - "-0.014959600, -0.011339500, -0.003363500, 0.0123957000, 0.0419601000, 0.1050958000, 0.2606984000", \ - "-0.015013200, -0.011413200, -0.003469400, 0.0122411000, 0.0416835000, 0.1047414000, 0.2599440000", \ - "-0.015120600, -0.011537800, -0.003627600, 0.0120282000, 0.0414993000, 0.1043150000, 0.2585738000", \ - "-0.015334400, -0.011747800, -0.003840500, 0.0118158000, 0.0412609000, 0.1043085000, 0.2598836000", \ - "-0.015795400, -0.012151400, -0.004114900, 0.0117427000, 0.0415114000, 0.1045514000, 0.2600109000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.003720000, 0.0002704000, 0.0089500000, 0.0279402000, 0.0607214000, 0.1251723000, 0.2799313000", \ - "-0.003680500, 0.0002933000, 0.0089604000, 0.0279178000, 0.0606435000, 0.1253091000, 0.2796396000", \ - "-0.003586400, 0.0003807000, 0.0090208000, 0.0279331000, 0.0606416000, 0.1250917000, 0.2796304000", \ - "-0.003615500, 0.0003468000, 0.0089920000, 0.0278884000, 0.0605570000, 0.1250149000, 0.2798141000", \ - "-0.003694800, 0.0002473000, 0.0088400000, 0.0276805000, 0.0602793000, 0.1245504000, 0.2801464000", \ - "-0.003846100, 8.940000e-05, 0.0086618000, 0.0274681000, 0.0599808000, 0.1245764000, 0.2789771000", \ - "-0.003874400, 0.0004970000, 0.0099627000, 0.0278195000, 0.0599029000, 0.1242938000, 0.2790424000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0016800000, 0.0073741000, 0.0178923000, 0.0299155000, 0.0283001000, -0.015833900, -0.161657900", \ - "0.0016728000, 0.0073502000, 0.0178359000, 0.0297869000, 0.0281657000, -0.016039100, -0.161854400", \ - "0.0016707000, 0.0073205000, 0.0177576000, 0.0296525000, 0.0279217000, -0.016301000, -0.162146900", \ - "0.0016528000, 0.0072927000, 0.0176982000, 0.0295530000, 0.0277690000, -0.016464900, -0.162306900", \ - "0.0016189000, 0.0072370000, 0.0175884000, 0.0293583000, 0.0274997000, -0.016786300, -0.162624900", \ - "0.0015636000, 0.0071503000, 0.0174443000, 0.0290613000, 0.0270925000, -0.017225000, -0.163066200", \ - "0.0015330000, 0.0071825000, 0.0175424000, 0.0291889000, 0.0274545000, -0.016853000, -0.162624300"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0043342000, 0.0071465000, 0.0134777000, 0.0289925000, 0.0582714000, 0.1203860000, 0.2733447000", \ - "0.0043672000, 0.0071751000, 0.0135009000, 0.0290171000, 0.0582681000, 0.1206330000, 0.2735521000", \ - "0.0044366000, 0.0072355000, 0.0135504000, 0.0290381000, 0.0583151000, 0.1203438000, 0.2735045000", \ - "0.0044145000, 0.0071769000, 0.0134291000, 0.0287988000, 0.0579274000, 0.1199752000, 0.2732547000", \ - "0.0043984000, 0.0071423000, 0.0133129000, 0.0285235000, 0.0574444000, 0.1194048000, 0.2731651000", \ - "0.0044225000, 0.0071782000, 0.0133972000, 0.0283537000, 0.0570046000, 0.1188446000, 0.2719380000", \ - "0.0047241000, 0.0078712000, 0.0149114000, 0.0291142000, 0.0569928000, 0.1188543000, 0.2715301000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.5002650000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.3517387000, 0.3609024000, 0.3797161000, 0.4154216000, 0.4828508000, 0.6175260000, 0.9364789000", \ - "0.3565532000, 0.3656962000, 0.3844292000, 0.4202846000, 0.4877092000, 0.6223922000, 0.9417621000", \ - "0.3693676000, 0.3785480000, 0.3973271000, 0.4330688000, 0.5005016000, 0.6351786000, 0.9544885000", \ - "0.4001593000, 0.4092690000, 0.4281023000, 0.4638173000, 0.5312444000, 0.6659410000, 0.9851043000", \ - "0.4708477000, 0.4799824000, 0.4987982000, 0.5345201000, 0.6019352000, 0.7366459000, 1.0557714000", \ - "0.5974803000, 0.6066481000, 0.6254894000, 0.6612018000, 0.7286421000, 0.8633609000, 1.1826538000", \ - "0.7915169000, 0.8006567000, 0.8194389000, 0.8552360000, 0.9226961000, 1.0574631000, 1.3764446000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.4693792000, 0.4784995000, 0.4982610000, 0.5408797000, 0.6402691000, 0.8873887000, 1.5269979000", \ - "0.4743018000, 0.4834222000, 0.5031843000, 0.5458029000, 0.6451923000, 0.8923198000, 1.5333260000", \ - "0.4871127000, 0.4962133000, 0.5159759000, 0.5585575000, 0.6579548000, 0.9051698000, 1.5442230000", \ - "0.5177545000, 0.5268702000, 0.5466360000, 0.5892150000, 0.6886246000, 0.9358727000, 1.5776457000", \ - "0.5886954000, 0.5978166000, 0.6175793000, 0.6601743000, 0.7595753000, 1.0064085000, 1.6456493000", \ - "0.7184535000, 0.7275222000, 0.7472881000, 0.7898825000, 0.8892672000, 1.1360067000, 1.7760126000", \ - "0.9193072000, 0.9284281000, 0.9481975000, 0.9907966000, 1.0904004000, 1.3368975000, 1.9781357000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0356646000, 0.0419868000, 0.0550999000, 0.0825495000, 0.1418751000, 0.2887193000, 0.7012038000", \ - "0.0356351000, 0.0416602000, 0.0546866000, 0.0824044000, 0.1420271000, 0.2888356000, 0.7004691000", \ - "0.0356294000, 0.0418478000, 0.0550243000, 0.0826034000, 0.1419858000, 0.2887888000, 0.6992079000", \ - "0.0356586000, 0.0422232000, 0.0551570000, 0.0825824000, 0.1420583000, 0.2886995000, 0.7005067000", \ - "0.0356738000, 0.0417599000, 0.0551530000, 0.0825582000, 0.1421377000, 0.2888600000, 0.6994154000", \ - "0.0359571000, 0.0416376000, 0.0551346000, 0.0826079000, 0.1421146000, 0.2892685000, 0.7000548000", \ - "0.0357416000, 0.0418065000, 0.0548335000, 0.0823637000, 0.1421953000, 0.2895557000, 0.7017417000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0332758000, 0.0411358000, 0.0599538000, 0.1095016000, 0.2392312000, 0.5850109000, 1.4937289000", \ - "0.0332810000, 0.0411412000, 0.0599619000, 0.1095036000, 0.2392324000, 0.5852703000, 1.4993435000", \ - "0.0331420000, 0.0409414000, 0.0598470000, 0.1094234000, 0.2399717000, 0.5854568000, 1.5002650000", \ - "0.0332053000, 0.0410020000, 0.0599646000, 0.1094089000, 0.2394846000, 0.5858367000, 1.4996957000", \ - "0.0332822000, 0.0411423000, 0.0599617000, 0.1094757000, 0.2391910000, 0.5857937000, 1.4986681000", \ - "0.0331642000, 0.0409440000, 0.0599625000, 0.1094869000, 0.2391828000, 0.5856249000, 1.4973737000", \ - "0.0332195000, 0.0410054000, 0.0599683000, 0.1094224000, 0.2392251000, 0.5846107000, 1.4979306000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2392752000, 0.2488659000, 0.2696775000, 0.3141142000, 0.4173772000, 0.6671929000, 1.3059303000", \ - "0.2444043000, 0.2540175000, 0.2747587000, 0.3192300000, 0.4225064000, 0.6724101000, 1.3110540000", \ - "0.2568780000, 0.2664900000, 0.2872545000, 0.3317359000, 0.4349948000, 0.6849697000, 1.3223557000", \ - "0.2883984000, 0.2980181000, 0.3187449000, 0.3632168000, 0.4664942000, 0.7163704000, 1.3550177000", \ - "0.3585579000, 0.3681511000, 0.3889206000, 0.4333750000, 0.5366584000, 0.7866482000, 1.4248873000", \ - "0.4856803000, 0.4953989000, 0.5163389000, 0.5610605000, 0.6645313000, 0.9142569000, 1.5523287000", \ - "0.6834838000, 0.6935297000, 0.7149458000, 0.7603801000, 0.8646765000, 1.1145549000, 1.7531450000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0351438000, 0.0435476000, 0.0631308000, 0.1144016000, 0.2475466000, 0.5882901000, 1.4910950000", \ - "0.0352245000, 0.0434274000, 0.0631592000, 0.1142970000, 0.2475100000, 0.5881651000, 1.4907786000", \ - "0.0352035000, 0.0434793000, 0.0631709000, 0.1143181000, 0.2475137000, 0.5882686000, 1.4936642000", \ - "0.0352153000, 0.0433691000, 0.0632042000, 0.1142846000, 0.2475010000, 0.5881358000, 1.4957264000", \ - "0.0351227000, 0.0434935000, 0.0631557000, 0.1143857000, 0.2472583000, 0.5874773000, 1.4953996000", \ - "0.0359138000, 0.0441151000, 0.0637837000, 0.1148966000, 0.2474199000, 0.5877983000, 1.4950114000", \ - "0.0375712000, 0.0459959000, 0.0655707000, 0.1166164000, 0.2487732000, 0.5885437000, 1.4944018000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2442197000, 0.2556008000, 0.2790914000, 0.3239057000, 0.4051383000, 0.5505052000, 0.8737812000", \ - "0.2493081000, 0.2607178000, 0.2841929000, 0.3290410000, 0.4102731000, 0.5555876000, 0.8790830000", \ - "0.2622539000, 0.2735130000, 0.2971370000, 0.3419746000, 0.4231468000, 0.5684770000, 0.8916871000", \ - "0.2940390000, 0.3053038000, 0.3288811000, 0.3737065000, 0.4548248000, 0.6001994000, 0.9236826000", \ - "0.3702806000, 0.3814327000, 0.4050123000, 0.4497561000, 0.5309688000, 0.6763847000, 0.9996447000", \ - "0.5477085000, 0.5591863000, 0.5829654000, 0.6276858000, 0.7087805000, 0.8542407000, 1.1777198000", \ - "0.8763612000, 0.8924368000, 0.9250816000, 0.9814284000, 1.0730963000, 1.2252421000, 1.5504800000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1421273000, 0.1517276000, 0.1724433000, 0.2168691000, 0.3198793000, 0.5695786000, 1.2074121000", \ - "0.1469168000, 0.1565021000, 0.1772446000, 0.2216627000, 0.3246980000, 0.5744019000, 1.2127337000", \ - "0.1568298000, 0.1664145000, 0.1871555000, 0.2315685000, 0.3346338000, 0.5842205000, 1.2215869000", \ - "0.1781894000, 0.1877569000, 0.2085263000, 0.2528776000, 0.3559862000, 0.6057934000, 1.2433201000", \ - "0.2243058000, 0.2341651000, 0.2551580000, 0.2997614000, 0.4030563000, 0.6527970000, 1.2901687000", \ - "0.2972803000, 0.3086364000, 0.3321053000, 0.3795685000, 0.4849912000, 0.7344660000, 1.3720337000", \ - "0.3817668000, 0.3967263000, 0.4266871000, 0.4819364000, 0.5928963000, 0.8428395000, 1.4812693000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0470404000, 0.0542523000, 0.0703042000, 0.1043262000, 0.1654835000, 0.3044873000, 0.7014106000", \ - "0.0470763000, 0.0542748000, 0.0705865000, 0.1042349000, 0.1655835000, 0.3049874000, 0.7065205000", \ - "0.0467073000, 0.0543484000, 0.0706058000, 0.1043587000, 0.1652665000, 0.3041502000, 0.7040680000", \ - "0.0467280000, 0.0543740000, 0.0705657000, 0.1043249000, 0.1651999000, 0.3047486000, 0.7064094000", \ - "0.0466521000, 0.0542987000, 0.0705592000, 0.1043785000, 0.1654726000, 0.3044541000, 0.7040866000", \ - "0.0493647000, 0.0566706000, 0.0721099000, 0.1052075000, 0.1658738000, 0.3047020000, 0.7042166000", \ - "0.0769761000, 0.0864686000, 0.1039296000, 0.1343518000, 0.1862138000, 0.3154933000, 0.7067343000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0350339000, 0.0432310000, 0.0631155000, 0.1141775000, 0.2475390000, 0.5884140000, 1.4959279000", \ - "0.0350213000, 0.0433212000, 0.0630252000, 0.1142405000, 0.2475479000, 0.5877810000, 1.4944616000", \ - "0.0350210000, 0.0433235000, 0.0630288000, 0.1142486000, 0.2475212000, 0.5881811000, 1.4954084000", \ - "0.0349510000, 0.0433762000, 0.0629993000, 0.1142851000, 0.2473151000, 0.5879772000, 1.4951971000", \ - "0.0363145000, 0.0444027000, 0.0641817000, 0.1147165000, 0.2468030000, 0.5880192000, 1.4936923000", \ - "0.0434716000, 0.0518256000, 0.0714235000, 0.1210168000, 0.2495230000, 0.5879566000, 1.4957613000", \ - "0.0596258000, 0.0696018000, 0.0899070000, 0.1372103000, 0.2578286000, 0.5891669000, 1.4944395000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0016200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0129364000, 0.0128464000, 0.0126390000, 0.0126936000, 0.0128198000, 0.0131108000, 0.0137813000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081153000, 0.0080591000, 0.0079297000, 0.0079572000, 0.0080208000, 0.0081674000, 0.0085054000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017060000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0691387000, 0.1942526000, 0.2898743000", \ - "-0.152410800, -0.026076200, 0.0695456000", \ - "-0.409165400, -0.282830700, -0.184767600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0874492000, -0.036444000, -0.123520800", \ - "0.2882467000, 0.1667949000, 0.0784974000", \ - "0.5376771000, 0.4162253000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2071340000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.063315800, -0.076336600", \ - "-0.230535800, -0.168898400, -0.178257200", \ - "-0.334702500, -0.255975300, -0.250685500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.1027161000, 0.1853171000", \ - "0.2699362000, 0.2156230000, 0.2493958000", \ - "0.3997376000, 0.3258932000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0017630000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016900000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029883000, 0.0029843000, 0.0029749000, 0.0029803000, 0.0029931000, 0.0030226000, 0.0030906000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002854400, -0.002850600, -0.002841700, -0.002852200, -0.002876000, -0.002931000, -0.003057600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018370000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2632305000, 0.4396139000, 0.7061341000", \ - "0.1344544000, 0.3083965000, 0.5736960000", \ - "-0.013657600, 0.1590638000, 0.4182598000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1594707000, 0.2943503000, 0.4436829000", \ - "-0.054754600, 0.0789043000, 0.2294577000", \ - "-0.298081400, -0.163201800, -0.012648400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.232375000, -0.406317000, -0.658188800", \ - "-0.106040400, -0.276320300, -0.525750700", \ - "0.0457337000, -0.124546200, -0.367873000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.018752000, -0.154852200, -0.304184900", \ - "0.1759421000, 0.0459453000, -0.102166700", \ - "0.4095033000, 0.2807272000, 0.1411602000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0026290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0025030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0094972000, 0.0094199000, 0.0092417000, 0.0092853000, 0.0093861000, 0.0096184000, 0.0101539000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0012894000, 0.0012520000, 0.0011660000, 0.0011927000, 0.0012547000, 0.0013974000, 0.0017264000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0027550000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3706523000, 0.5494772000, 0.8758119000", \ - "0.2382142000, 0.4170391000, 0.7397116000", \ - "0.0888815000, 0.2640443000, 0.5769512000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2705547000, 0.3517233000, 0.3765443000", \ - "0.1417786000, 0.2229473000, 0.2489889000", \ - "-0.005112600, 0.0760560000, 0.1008770000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.079787100, -0.273260400, -0.511704400", \ - "0.1173483000, -0.076125000, -0.313348300", \ - "0.3521302000, 0.1574362000, -0.077345700"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.000441400, -0.145086600, -0.273667300", \ - "0.1954733000, 0.0593730000, -0.069207700", \ - "0.4302552000, 0.2990378000, 0.1777813000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050741000, 0.0050623000, 0.0050349000, 0.0050485000, 0.0050800000, 0.0051527000, 0.0053202000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004872000, -0.004936100, -0.005084000, -0.005087500, -0.005095700, -0.005114600, -0.005158100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035210000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.066359400, 0.0257956000, 0.1067689000", \ - "-0.254949900, -0.166457000, -0.113559900", \ - "-0.468979800, -0.378045600, -0.344679700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0728008000, -0.016912800, -0.050278600", \ - "0.2626120000, 0.1728984000, 0.1407533000", \ - "0.4742005000, 0.3832663000, 0.3560039000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.2699362000, 0.3997376000", \ - "0.1027161000, 0.2156230000, 0.3258932000", \ - "0.1853171000, 0.2493958000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2543700000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.230535800, -0.334702500", \ - "-0.063315800, -0.168898400, -0.255975300", \ - "-0.076336600, -0.178257200, -0.250685500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK_N") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfbbn_2") { - leakage_power () { - value : 0.0170289000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0142610000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0147241000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0141111000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0137386000; - when : "!SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125244000; - when : "SET_B&!RESET_B&!CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0161519000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0163526000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0153346000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0171807000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0149568000; - when : "!SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0151093000; - when : "SET_B&!RESET_B&!CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146447000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0144440000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0164174000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0139281000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0135556000; - when : "!SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0123415000; - when : "SET_B&!RESET_B&!CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0162409000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0143118000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0139393000; - when : "!SET_B&RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0127251000; - when : "SET_B&!RESET_B&!CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0149934000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0143912000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0140187000; - when : "!SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0128045000; - when : "SET_B&!RESET_B&!CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0164320000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0165821000; - when : "SET_B&RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0173701000; - when : "SET_B&RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0151452000; - when : "SET_B&RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0129213000; - when : "!SET_B&RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0130738000; - when : "SET_B&!RESET_B&!CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0159690000; - when : "SET_B&RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0165692000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0143453000; - when : "!SET_B&RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0144979000; - when : "SET_B&!RESET_B&!CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0167586000; - when : "SET_B&RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0163927000; - when : "SET_B&RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141688000; - when : "!SET_B&RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0143214000; - when : "SET_B&!RESET_B&!CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0137845000; - when : "!SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0133591000; - when : "!SET_B&!RESET_B&!CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0147673000; - when : "!SET_B&RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136015000; - when : "!SET_B&RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0140646000; - when : "!SET_B&RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0151929000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0129410000; - when : "!SET_B&!RESET_B&CLK_N&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136392000; - when : "!SET_B&!RESET_B&!CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0127319000; - when : "!SET_B&RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141559000; - when : "!SET_B&RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0154730000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0132211000; - when : "!SET_B&!RESET_B&CLK_N&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0131761000; - when : "!SET_B&!RESET_B&!CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0139852000; - when : "!SET_B&RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0150099000; - when : "SET_B&RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0127581000; - when : "!SET_B&!RESET_B&CLK_N&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0139658000; - when : "!SET_B&!RESET_B&!CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0139794000; - when : "!SET_B&RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0137763000; - when : "!SET_B&!RESET_B&CLK_N&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0145773000; - when : "!SET_B&!RESET_B&!CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0143878000; - when : "!SET_B&!RESET_B&CLK_N&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125418000; - when : "!SET_B&!RESET_B&!CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0123523000; - when : "!SET_B&!RESET_B&CLK_N&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0135598000; - when : "!SET_B&!RESET_B&!CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0153936000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0131418000; - when : "!SET_B&!RESET_B&CLK_N&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0137893000; - when : "!SET_B&!RESET_B&!CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0135998000; - when : "!SET_B&!RESET_B&CLK_N&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0121915000; - when : "SET_B&!RESET_B&CLK_N&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0138855000; - when : "SET_B&!RESET_B&CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0120086000; - when : "SET_B&!RESET_B&CLK_N&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0124716000; - when : "SET_B&!RESET_B&CLK_N&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0118500000; - when : "SET_B&!RESET_B&CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0132741000; - when : "SET_B&!RESET_B&CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0123922000; - when : "SET_B&!RESET_B&CLK_N&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0130976000; - when : "SET_B&!RESET_B&CLK_N&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0160462000; - when : "SET_B&RESET_B&CLK_N&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0166576000; - when : "SET_B&RESET_B&CLK_N&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146221000; - when : "SET_B&RESET_B&CLK_N&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0158697000; - when : "SET_B&RESET_B&CLK_N&D&SCD&SCE&!Q&Q_N"; - } - area : 41.289600000; - cell_footprint : "sky130_fd_sc_hd__sdfbbn"; - cell_leakage_power : 0.0143258800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0017700000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0353142000, 0.0351881000, 0.0348973000, 0.0349800000, 0.0351711000, 0.0356114000, 0.0366263000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0170516000, 0.0169792000, 0.0168124000, 0.0168195000, 0.0168361000, 0.0168743000, 0.0169625000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018460000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2917193000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2554685000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076487000, 0.0075290000, 0.0072531000, 0.0072850000, 0.0073587000, 0.0075287000, 0.0079204000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022434000, 0.0022150000, 0.0021494000, 0.0021580000, 0.0021780000, 0.0022242000, 0.0023305000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0015940000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3608867000, 0.5616842000, 0.9490540000", \ - "0.2272279000, 0.4280254000, 0.8105124000", \ - "0.0778952000, 0.2762513000, 0.6453106000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1289531000, 0.2577292000, 0.3594544000", \ - "-0.085272100, 0.0435039000, 0.1464499000", \ - "-0.326157600, -0.197381500, -0.093214800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.332472600, -0.533270200, -0.915757100", \ - "-0.198813800, -0.402052700, -0.774774100", \ - "-0.048260400, -0.245395800, -0.609572300"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0117656000, -0.120672500, -0.222397800", \ - "0.2089010000, 0.0825664000, -0.019158900", \ - "0.4400208000, 0.3222311000, 0.2266094000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.014251900, -0.008538000, 0.0034356000, 0.0172322000, 0.0058485000, -0.091254400, -0.417608400", \ - "-0.014196800, -0.008496900, 0.0034452000, 0.0171955000, 0.0057523000, -0.091430000, -0.417807600", \ - "-0.014054100, -0.008358700, 0.0035693000, 0.0172903000, 0.0058313000, -0.091347800, -0.417732400", \ - "-0.014105100, -0.008421900, 0.0034696000, 0.0171128000, 0.0056428000, -0.091609200, -0.418012600", \ - "-0.014209100, -0.008541300, 0.0033264000, 0.0169439000, 0.0054090000, -0.091870400, -0.418264000", \ - "-0.014428800, -0.008763200, 0.0031089000, 0.0167313000, 0.0051585000, -0.092092800, -0.418507100", \ - "-0.014905500, -0.009188900, 0.0028094000, 0.0166328000, 0.0053603000, -0.091744700, -0.418104000"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.015813900, -0.012453800, -0.003629700, 0.0171869000, 0.0636243000, 0.1805625000, 0.5148491000", \ - "-0.015757500, -0.012401000, -0.003584300, 0.0171849000, 0.0638144000, 0.1812120000, 0.5146848000", \ - "-0.015617700, -0.012278400, -0.003498000, 0.0172758000, 0.0636797000, 0.1813713000, 0.5147401000", \ - "-0.015666000, -0.012341000, -0.003573600, 0.0171297000, 0.0633948000, 0.1802349000, 0.5133699000", \ - "-0.015774400, -0.012468600, -0.003746000, 0.0168995000, 0.0630055000, 0.1805875000, 0.5143891000", \ - "-0.015990200, -0.012675400, -0.003963300, 0.0166387000, 0.0628472000, 0.1803915000, 0.5113570000", \ - "-0.016393000, -0.012917400, -0.004005000, 0.0164917000, 0.0632710000, 0.1799320000, 0.5118959000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.002754200, 0.0035026000, 0.0167307000, 0.0325098000, 0.0240116000, -0.070929900, -0.396632000", \ - "-0.002707200, 0.0035519000, 0.0167631000, 0.0325664000, 0.0240474000, -0.070886900, -0.396599300", \ - "-0.002607900, 0.0036358000, 0.0168008000, 0.0325904000, 0.0239470000, -0.070985100, -0.396629000", \ - "-0.002642300, 0.0035888000, 0.0167258000, 0.0324736000, 0.0237741000, -0.071192100, -0.396850400", \ - "-0.002713200, 0.0035093000, 0.0166243000, 0.0322777000, 0.0236023000, -0.071443400, -0.397176200", \ - "-0.002857900, 0.0033519000, 0.0164403000, 0.0320395000, 0.0233250000, -0.071834500, -0.397459100", \ - "-0.003082600, 0.0032781000, 0.0167264000, 0.0329367000, 0.0235805000, -0.071748300, -0.397383400"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("0.0055588000, 0.0107763000, 0.0216227000, 0.0335672000, 0.0212673000, -0.075986500, -0.402576700", \ - "0.0055543000, 0.0107788000, 0.0216184000, 0.0335814000, 0.0212077000, -0.075936500, -0.402601300", \ - "0.0055414000, 0.0107488000, 0.0215923000, 0.0335500000, 0.0212199000, -0.076089700, -0.402766600", \ - "0.0055317000, 0.0107123000, 0.0214758000, 0.0333011000, 0.0207565000, -0.076484400, -0.403093100", \ - "0.0055257000, 0.0106795000, 0.0213650000, 0.0330672000, 0.0204078000, -0.077047900, -0.403790100", \ - "0.0055619000, 0.0107040000, 0.0213891000, 0.0330790000, 0.0202159000, -0.077501100, -0.404283100", \ - "0.0057418000, 0.0110417000, 0.0220649000, 0.0342681000, 0.0210359000, -0.077441000, -0.404244400"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014624920, 0.0042777660, 0.0125124000, 0.0365985700, 0.1070502000, 0.3131202000"); - values("-0.000522200, 0.0031133000, 0.0126137000, 0.0347351000, 0.0827491000, 0.2008601000, 0.5352474000", \ - "-0.000527400, 0.0030968000, 0.0125471000, 0.0346631000, 0.0828282000, 0.2007136000, 0.5320123000", \ - "-0.000530300, 0.0030728000, 0.0124903000, 0.0344764000, 0.0823364000, 0.2006819000, 0.5348923000", \ - "-0.000542800, 0.0030490000, 0.0124330000, 0.0343844000, 0.0822985000, 0.2007184000, 0.5338993000", \ - "-0.000574200, 0.0029990000, 0.0123102000, 0.0341761000, 0.0820122000, 0.2000563000, 0.5312048000", \ - "-0.000628000, 0.0029140000, 0.0121672000, 0.0338856000, 0.0817572000, 0.1994104000, 0.5332778000", \ - "-0.000691000, 0.0028842000, 0.0122267000, 0.0343144000, 0.0823130000, 0.2003489000, 0.5323206000"); - } - } - max_capacitance : 0.3131200000; - max_transition : 1.4986030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.5827393000, 0.5877264000, 0.5987890000, 0.6209790000, 0.6679589000, 0.7849055000, 1.1194871000", \ - "0.5877272000, 0.5927386000, 0.6037296000, 0.6259623000, 0.6728245000, 0.7897016000, 1.1241083000", \ - "0.6004267000, 0.6054292000, 0.6164814000, 0.6387865000, 0.6857418000, 0.8025937000, 1.1374983000", \ - "0.6311741000, 0.6361655000, 0.6472009000, 0.6695305000, 0.7163939000, 0.8333742000, 1.1674585000", \ - "0.7020098000, 0.7070101000, 0.7180775000, 0.7403599000, 0.7872508000, 0.9041723000, 1.2384731000", \ - "0.8314207000, 0.8364118000, 0.8474617000, 0.8697710000, 0.9167354000, 1.0335409000, 1.3682591000", \ - "1.0323006000, 1.0372925000, 1.0483414000, 1.0706510000, 1.1176166000, 1.2343837000, 1.5688719000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.5010088000, 0.5073502000, 0.5215040000, 0.5526603000, 0.6330939000, 0.8643642000, 1.5418905000", \ - "0.5061216000, 0.5125742000, 0.5265593000, 0.5576661000, 0.6380424000, 0.8693802000, 1.5457390000", \ - "0.5187912000, 0.5251083000, 0.5391771000, 0.5703665000, 0.6506912000, 0.8817244000, 1.5589625000", \ - "0.5498267000, 0.5561693000, 0.5703825000, 0.6013697000, 0.6818734000, 0.9131573000, 1.5887087000", \ - "0.6200899000, 0.6264717000, 0.6406949000, 0.6717179000, 0.7517569000, 0.9831628000, 1.6583016000", \ - "0.7467192000, 0.7531364000, 0.7672304000, 0.7981366000, 0.8786281000, 1.1097575000, 1.7855479000", \ - "0.9415417000, 0.9479955000, 0.9619796000, 0.9930528000, 1.0734664000, 1.3043224000, 1.9801623000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0202953000, 0.0235832000, 0.0310356000, 0.0484989000, 0.0966734000, 0.2437864000, 0.6883756000", \ - "0.0204132000, 0.0234475000, 0.0310697000, 0.0488753000, 0.0963078000, 0.2439111000, 0.6878571000", \ - "0.0202104000, 0.0234418000, 0.0307994000, 0.0488700000, 0.0963218000, 0.2436032000, 0.6911929000", \ - "0.0202368000, 0.0234116000, 0.0309655000, 0.0485731000, 0.0963767000, 0.2434199000, 0.6898772000", \ - "0.0204952000, 0.0237205000, 0.0310387000, 0.0485461000, 0.0963858000, 0.2432635000, 0.6927109000", \ - "0.0202262000, 0.0233558000, 0.0307970000, 0.0488617000, 0.0963722000, 0.2433572000, 0.6883815000", \ - "0.0202163000, 0.0233376000, 0.0307967000, 0.0488624000, 0.0963786000, 0.2423120000, 0.6936756000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0252964000, 0.0295069000, 0.0411235000, 0.0753266000, 0.1856185000, 0.5170688000, 1.4959872000", \ - "0.0250654000, 0.0295565000, 0.0411361000, 0.0753523000, 0.1851820000, 0.5178890000, 1.4986035000", \ - "0.0252042000, 0.0294300000, 0.0408257000, 0.0752339000, 0.1852814000, 0.5178719000, 1.4968138000", \ - "0.0249992000, 0.0292850000, 0.0410813000, 0.0752107000, 0.1855662000, 0.5173985000, 1.4940124000", \ - "0.0250879000, 0.0293273000, 0.0411306000, 0.0752465000, 0.1849268000, 0.5170854000, 1.4925912000", \ - "0.0251346000, 0.0298381000, 0.0411144000, 0.0752976000, 0.1855535000, 0.5174254000, 1.4912399000", \ - "0.0250108000, 0.0294862000, 0.0411798000, 0.0751181000, 0.1856026000, 0.5174201000, 1.4960547000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.3582452000, 0.3633529000, 0.3745904000, 0.3972700000, 0.4446186000, 0.5618158000, 0.8953941000", \ - "0.3632134000, 0.3682831000, 0.3795364000, 0.4022372000, 0.4495745000, 0.5667732000, 0.9002329000", \ - "0.3758566000, 0.3809494000, 0.3921743000, 0.4149022000, 0.4622093000, 0.5792987000, 0.9130944000", \ - "0.4068217000, 0.4119243000, 0.4231468000, 0.4459063000, 0.4931847000, 0.6102654000, 0.9440735000", \ - "0.4783872000, 0.4834609000, 0.4947097000, 0.5174109000, 0.5647502000, 0.6819509000, 1.0154293000", \ - "0.6087965000, 0.6139718000, 0.6252038000, 0.6479152000, 0.6952060000, 0.8124371000, 1.1461675000", \ - "0.8167897000, 0.8219465000, 0.8331734000, 0.8558599000, 0.9032650000, 1.0205263000, 1.3539998000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0211653000, 0.0245105000, 0.0318213000, 0.0494767000, 0.0974534000, 0.2430236000, 0.6879892000", \ - "0.0210080000, 0.0241435000, 0.0317284000, 0.0496437000, 0.0973863000, 0.2432308000, 0.6886677000", \ - "0.0210541000, 0.0243975000, 0.0317854000, 0.0497605000, 0.0973216000, 0.2430252000, 0.6885866000", \ - "0.0211228000, 0.0244557000, 0.0317717000, 0.0497438000, 0.0973424000, 0.2429567000, 0.6884473000", \ - "0.0209976000, 0.0245644000, 0.0317231000, 0.0496581000, 0.0974120000, 0.2432541000, 0.6887003000", \ - "0.0213783000, 0.0242816000, 0.0315951000, 0.0495025000, 0.0972460000, 0.2432576000, 0.6888612000", \ - "0.0211213000, 0.0244740000, 0.0318350000, 0.0498435000, 0.0974369000, 0.2429859000, 0.6887617000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.2585272000, 0.2636539000, 0.2748366000, 0.2974997000, 0.3448117000, 0.4620760000, 0.7957483000", \ - "0.2633526000, 0.2684292000, 0.2796529000, 0.3023107000, 0.3496965000, 0.4668951000, 0.8006419000", \ - "0.2732807000, 0.2784037000, 0.2896610000, 0.3123031000, 0.3595779000, 0.4768789000, 0.8104494000", \ - "0.2947699000, 0.2998789000, 0.3110862000, 0.3337992000, 0.3811279000, 0.4983254000, 0.8320937000", \ - "0.3430221000, 0.3480783000, 0.3593296000, 0.3820256000, 0.4293890000, 0.5465972000, 0.8802938000", \ - "0.4326846000, 0.4379080000, 0.4492872000, 0.4722330000, 0.5197739000, 0.6371103000, 0.9709168000", \ - "0.5561998000, 0.5617003000, 0.5736911000, 0.5974235000, 0.6454804000, 0.7631439000, 1.0969484000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.4244340000, 0.4313001000, 0.4464045000, 0.4781794000, 0.5587708000, 0.7899069000, 1.4662310000", \ - "0.4297319000, 0.4366219000, 0.4515652000, 0.4834950000, 0.5640718000, 0.7953618000, 1.4705837000", \ - "0.4427102000, 0.4495521000, 0.4646680000, 0.4964245000, 0.5768814000, 0.8082073000, 1.4856645000", \ - "0.4744656000, 0.4814017000, 0.4963294000, 0.5282242000, 0.6085646000, 0.8396268000, 1.5172926000", \ - "0.5503748000, 0.5574020000, 0.5721759000, 0.6041607000, 0.6844791000, 0.9154070000, 1.5917567000", \ - "0.7286051000, 0.7355191000, 0.7505118000, 0.7822598000, 0.8627531000, 1.0936273000, 1.7702035000", \ - "1.1093444000, 1.1166307000, 1.1324349000, 1.1650173000, 1.2457284000, 1.4772668000, 2.1512627000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0209051000, 0.0241477000, 0.0321004000, 0.0494765000, 0.0972577000, 0.2431837000, 0.6889629000", \ - "0.0209274000, 0.0241127000, 0.0315730000, 0.0497706000, 0.0970399000, 0.2431969000, 0.6876912000", \ - "0.0209140000, 0.0241022000, 0.0318959000, 0.0494714000, 0.0973436000, 0.2429998000, 0.6877575000", \ - "0.0210360000, 0.0242912000, 0.0316747000, 0.0497315000, 0.0971355000, 0.2432101000, 0.6892059000", \ - "0.0209472000, 0.0245830000, 0.0316411000, 0.0496696000, 0.0974807000, 0.2431924000, 0.6885365000", \ - "0.0219272000, 0.0252886000, 0.0326095000, 0.0503348000, 0.0971814000, 0.2434781000, 0.6890234000", \ - "0.0239629000, 0.0272907000, 0.0347272000, 0.0520265000, 0.0990198000, 0.2439207000, 0.6861280000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014624900, 0.0042777700, 0.0125124000, 0.0365986000, 0.1070500000, 0.3131200000"); - values("0.0280778000, 0.0324183000, 0.0439000000, 0.0770869000, 0.1861268000, 0.5177134000, 1.4934187000", \ - "0.0279989000, 0.0325903000, 0.0440709000, 0.0768913000, 0.1854292000, 0.5167999000, 1.4938416000", \ - "0.0278778000, 0.0324070000, 0.0439331000, 0.0769019000, 0.1858661000, 0.5180316000, 1.4937170000", \ - "0.0279020000, 0.0326676000, 0.0439997000, 0.0768744000, 0.1856837000, 0.5175412000, 1.4913789000", \ - "0.0280730000, 0.0324715000, 0.0441089000, 0.0769464000, 0.1858032000, 0.5169324000, 1.4922984000", \ - "0.0279422000, 0.0322040000, 0.0439416000, 0.0768962000, 0.1859437000, 0.5178293000, 1.4950925000", \ - "0.0305107000, 0.0352458000, 0.0463325000, 0.0786758000, 0.1861915000, 0.5175951000, 1.4936625000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014448650, 0.0041752680, 0.0120654000, 0.0348657300, 0.1007525000, 0.2911476000"); - values("-0.014141200, -0.008373300, 0.0035178000, 0.0172103000, 0.0067743000, -0.082284300, -0.382984400", \ - "-0.014079800, -0.008321000, 0.0035751000, 0.0171470000, 0.0068393000, -0.082164400, -0.382841100", \ - "-0.013938200, -0.008197300, 0.0036525000, 0.0173467000, 0.0068133000, -0.082295800, -0.383006100", \ - "-0.013993800, -0.008263300, 0.0035511000, 0.0171070000, 0.0065351000, -0.082518000, -0.383254300", \ - "-0.014101500, -0.008389400, 0.0034045000, 0.0169205000, 0.0063353000, -0.082782400, -0.383541600", \ - "-0.014318400, -0.008612800, 0.0031534000, 0.0166631000, 0.0059987000, -0.083177200, -0.383907900", \ - "-0.014798100, -0.009046900, 0.0028370000, 0.0165351000, 0.0060082000, -0.082851000, -0.383536700"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014448650, 0.0041752680, 0.0120654000, 0.0348657300, 0.1007525000, 0.2911476000"); - values("-0.015645900, -0.012089100, -0.003143800, 0.0171937000, 0.0616998000, 0.1725163000, 0.4795768000", \ - "-0.015585300, -0.012033800, -0.003090700, 0.0172440000, 0.0617937000, 0.1722373000, 0.4797921000", \ - "-0.015450200, -0.011915400, -0.003012800, 0.0172589000, 0.0618777000, 0.1719836000, 0.4794995000", \ - "-0.015497600, -0.011978000, -0.003097600, 0.0171014000, 0.0615374000, 0.1716147000, 0.4813448000", \ - "-0.015601600, -0.012092100, -0.003244100, 0.0169388000, 0.0613881000, 0.1714467000, 0.4813912000", \ - "-0.015820300, -0.012310100, -0.003453000, 0.0167389000, 0.0611712000, 0.1711745000, 0.4810561000", \ - "-0.016297700, -0.012731000, -0.003764300, 0.0166521000, 0.0613671000, 0.1715321000, 0.4791427000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014448650, 0.0041752680, 0.0120654000, 0.0348657300, 0.1007525000, 0.2911476000"); - values("-0.004205400, -0.000215600, 0.0096391000, 0.0324308000, 0.0804535000, 0.1920426000, 0.5002663000", \ - "-0.004165800, -0.000195200, 0.0096694000, 0.0324098000, 0.0804101000, 0.1922794000, 0.4990719000", \ - "-0.004068300, -0.000108400, 0.0097371000, 0.0324483000, 0.0804579000, 0.1918834000, 0.4995748000", \ - "-0.004097000, -0.000134200, 0.0096804000, 0.0323992000, 0.0803201000, 0.1917804000, 0.4993921000", \ - "-0.004165200, -0.000222800, 0.0095687000, 0.0322056000, 0.0800898000, 0.1913447000, 0.4993045000", \ - "-0.004307900, -0.000370800, 0.0094122000, 0.0319559000, 0.0797280000, 0.1915906000, 0.4988648000", \ - "-0.004452100, -0.000218400, 0.0102620000, 0.0328984000, 0.0796737000, 0.1910219000, 0.4980623000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014448650, 0.0041752680, 0.0120654000, 0.0348657300, 0.1007525000, 0.2911476000"); - values("0.0012064000, 0.0073230000, 0.0199745000, 0.0347449000, 0.0256223000, -0.062258100, -0.362303600", \ - "0.0012021000, 0.0073009000, 0.0199054000, 0.0346608000, 0.0255131000, -0.062394600, -0.362551500", \ - "0.0011991000, 0.0072806000, 0.0198607000, 0.0344918000, 0.0252863000, -0.062692800, -0.362835900", \ - "0.0011840000, 0.0072549000, 0.0197928000, 0.0343862000, 0.0251356000, -0.062859000, -0.363057600", \ - "0.0011538000, 0.0071988000, 0.0196770000, 0.0341741000, 0.0248015000, -0.063203300, -0.363360000", \ - "0.0011055000, 0.0071306000, 0.0195467000, 0.0338970000, 0.0243589000, -0.063735600, -0.363846300", \ - "0.0010933000, 0.0072233000, 0.0198154000, 0.0343004000, 0.0247233000, -0.063383900, -0.363450100"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014448650, 0.0041752680, 0.0120654000, 0.0348657300, 0.1007525000, 0.2911476000"); - values("0.0040780000, 0.0070003000, 0.0145147000, 0.0334893000, 0.0777589000, 0.1865875000, 0.4930923000", \ - "0.0040729000, 0.0069986000, 0.0145170000, 0.0334903000, 0.0777436000, 0.1865862000, 0.4931192000", \ - "0.0040656000, 0.0069817000, 0.0144849000, 0.0334641000, 0.0775955000, 0.1867389000, 0.4925067000", \ - "0.0040531000, 0.0069420000, 0.0143791000, 0.0332310000, 0.0772950000, 0.1863832000, 0.4918641000", \ - "0.0040571000, 0.0069243000, 0.0143017000, 0.0329917000, 0.0768225000, 0.1858077000, 0.4937890000", \ - "0.0041090000, 0.0069970000, 0.0144014000, 0.0330201000, 0.0763948000, 0.1854104000, 0.4913911000", \ - "0.0043654000, 0.0075378000, 0.0156057000, 0.0342659000, 0.0766515000, 0.1855961000, 0.4912856000"); - } - } - max_capacitance : 0.2911480000; - max_transition : 1.5025570000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.3798805000, 0.3881176000, 0.4063218000, 0.4420560000, 0.5095694000, 0.6464781000, 0.9788240000", \ - "0.3847670000, 0.3930645000, 0.4112738000, 0.4469231000, 0.5144855000, 0.6513966000, 0.9834442000", \ - "0.3976346000, 0.4059161000, 0.4241110000, 0.4597562000, 0.5273486000, 0.6642273000, 0.9963281000", \ - "0.4284015000, 0.4366636000, 0.4548718000, 0.4905802000, 0.5581104000, 0.6950016000, 1.0273494000", \ - "0.4987513000, 0.5070501000, 0.5251992000, 0.5608924000, 0.6284579000, 0.7653738000, 1.0975779000", \ - "0.6254749000, 0.6337245000, 0.6519996000, 0.6876484000, 0.7552218000, 0.8921234000, 1.2244706000", \ - "0.8201682000, 0.8284837000, 0.8466770000, 0.8824376000, 0.9499822000, 1.0869194000, 1.4189645000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.4843969000, 0.4921946000, 0.5101290000, 0.5487183000, 0.6381283000, 0.8749550000, 1.5511742000", \ - "0.4893629000, 0.4971547000, 0.5150905000, 0.5537048000, 0.6431043000, 0.8799847000, 1.5551515000", \ - "0.5017308000, 0.5095445000, 0.5274701000, 0.5660402000, 0.6554883000, 0.8923057000, 1.5682804000", \ - "0.5325806000, 0.5404078000, 0.5583616000, 0.5969062000, 0.6863376000, 0.9233025000, 1.5980778000", \ - "0.6038047000, 0.6116148000, 0.6295414000, 0.6681125000, 0.7575582000, 0.9946979000, 1.6689556000", \ - "0.7332001000, 0.7410655000, 0.7590056000, 0.7976024000, 0.8870132000, 1.1238124000, 1.7983949000", \ - "0.9339428000, 0.9417566000, 0.9596907000, 0.9982626000, 1.0876909000, 1.3244702000, 1.9993578000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.0362920000, 0.0415120000, 0.0528869000, 0.0773388000, 0.1316545000, 0.2691155000, 0.6882844000", \ - "0.0363040000, 0.0415224000, 0.0529135000, 0.0779500000, 0.1315109000, 0.2690481000, 0.6867207000", \ - "0.0364506000, 0.0414282000, 0.0533212000, 0.0771894000, 0.1316126000, 0.2689650000, 0.6866837000", \ - "0.0363084000, 0.0414152000, 0.0532283000, 0.0770371000, 0.1316529000, 0.2697220000, 0.6851598000", \ - "0.0364348000, 0.0414976000, 0.0529648000, 0.0773385000, 0.1315269000, 0.2688735000, 0.6869025000", \ - "0.0363350000, 0.0414930000, 0.0532762000, 0.0770430000, 0.1316258000, 0.2691408000, 0.6885393000", \ - "0.0365283000, 0.0416371000, 0.0529480000, 0.0771231000, 0.1317434000, 0.2692437000, 0.6866089000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.0297674000, 0.0356612000, 0.0507457000, 0.0889723000, 0.1995015000, 0.5278451000, 1.4984469000", \ - "0.0297528000, 0.0357644000, 0.0506853000, 0.0889644000, 0.1991719000, 0.5285885000, 1.4972049000", \ - "0.0297082000, 0.0357318000, 0.0506912000, 0.0888542000, 0.1995067000, 0.5273472000, 1.4967881000", \ - "0.0299216000, 0.0355556000, 0.0505874000, 0.0888957000, 0.1996931000, 0.5278014000, 1.5011509000", \ - "0.0297174000, 0.0357313000, 0.0506970000, 0.0888511000, 0.1995205000, 0.5269646000, 1.4964882000", \ - "0.0299953000, 0.0358255000, 0.0507002000, 0.0889887000, 0.1993029000, 0.5266570000, 1.5025567000", \ - "0.0297526000, 0.0357208000, 0.0506857000, 0.0888730000, 0.1996490000, 0.5269256000, 1.4978503000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.2560610000, 0.2644816000, 0.2834866000, 0.3238716000, 0.4170123000, 0.6574960000, 1.3320270000", \ - "0.2613305000, 0.2696827000, 0.2886753000, 0.3290767000, 0.4222545000, 0.6629125000, 1.3364142000", \ - "0.2738448000, 0.2821995000, 0.3011844000, 0.3415994000, 0.4347900000, 0.6753786000, 1.3497533000", \ - "0.3054830000, 0.3139338000, 0.3328617000, 0.3732419000, 0.4664698000, 0.7070619000, 1.3809336000", \ - "0.3764577000, 0.3848044000, 0.4038314000, 0.4442291000, 0.5373876000, 0.7778895000, 1.4521049000", \ - "0.5068844000, 0.5153731000, 0.5343728000, 0.5748829000, 0.6683199000, 0.9087542000, 1.5833475000", \ - "0.7130490000, 0.7219740000, 0.7414545000, 0.7822776000, 0.8761743000, 1.1164648000, 1.7899771000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.0317594000, 0.0381757000, 0.0539603000, 0.0933855000, 0.2065637000, 0.5308766000, 1.4920496000", \ - "0.0319426000, 0.0381652000, 0.0538075000, 0.0934847000, 0.2066752000, 0.5309428000, 1.4954019000", \ - "0.0320099000, 0.0381345000, 0.0537617000, 0.0935001000, 0.2068823000, 0.5303996000, 1.4958300000", \ - "0.0317462000, 0.0383137000, 0.0539687000, 0.0934327000, 0.2070081000, 0.5302882000, 1.4917972000", \ - "0.0319513000, 0.0381313000, 0.0539298000, 0.0933935000, 0.2068364000, 0.5307937000, 1.4924794000", \ - "0.0322950000, 0.0388725000, 0.0539444000, 0.0935645000, 0.2069609000, 0.5306255000, 1.4913788000", \ - "0.0341289000, 0.0404781000, 0.0561166000, 0.0952410000, 0.2073914000, 0.5327097000, 1.4946779000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.2843291000, 0.2946700000, 0.3168419000, 0.3587085000, 0.4364139000, 0.5837503000, 0.9219608000", \ - "0.2896441000, 0.2999714000, 0.3221295000, 0.3639888000, 0.4416645000, 0.5889707000, 0.9271319000", \ - "0.3028245000, 0.3131375000, 0.3352026000, 0.3770064000, 0.4546838000, 0.6019961000, 0.9401963000", \ - "0.3348340000, 0.3451450000, 0.3671755000, 0.4089485000, 0.4866251000, 0.6339281000, 0.9718368000", \ - "0.4104572000, 0.4207912000, 0.4428172000, 0.4846063000, 0.5622643000, 0.7096347000, 1.0478032000", \ - "0.5894729000, 0.5996688000, 0.6214305000, 0.6628577000, 0.7402836000, 0.8876342000, 1.2259487000", \ - "0.9507510000, 0.9623449000, 0.9872708000, 1.0352551000, 1.1210742000, 1.2749291000, 1.6147667000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.1565306000, 0.1648702000, 0.1838601000, 0.2242637000, 0.3172635000, 0.5576785000, 1.2313475000", \ - "0.1613077000, 0.1696676000, 0.1886112000, 0.2290480000, 0.3220918000, 0.5624872000, 1.2360124000", \ - "0.1713368000, 0.1796618000, 0.1986541000, 0.2390497000, 0.3320690000, 0.5724466000, 1.2455177000", \ - "0.1927860000, 0.2011525000, 0.2200934000, 0.2604675000, 0.3535621000, 0.5939971000, 1.2670508000", \ - "0.2407836000, 0.2492460000, 0.2683346000, 0.3087257000, 0.4019324000, 0.6423194000, 1.3152600000", \ - "0.3222285000, 0.3319845000, 0.3536248000, 0.3975344000, 0.4931865000, 0.7331512000, 1.4072613000", \ - "0.4249358000, 0.4374525000, 0.4652633000, 0.5178693000, 0.6204331000, 0.8611518000, 1.5342279000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.0514522000, 0.0566663000, 0.0681113000, 0.0936107000, 0.1492802000, 0.2842053000, 0.6926391000", \ - "0.0513944000, 0.0566144000, 0.0679187000, 0.0935125000, 0.1492949000, 0.2839302000, 0.6941762000", \ - "0.0513512000, 0.0565015000, 0.0679842000, 0.0934549000, 0.1491606000, 0.2841026000, 0.6930122000", \ - "0.0513409000, 0.0564713000, 0.0679897000, 0.0934281000, 0.1490692000, 0.2839638000, 0.6921030000", \ - "0.0512350000, 0.0565330000, 0.0680099000, 0.0935379000, 0.1493448000, 0.2840032000, 0.6923243000", \ - "0.0511381000, 0.0562024000, 0.0677531000, 0.0934324000, 0.1491719000, 0.2839900000, 0.6905082000", \ - "0.0695584000, 0.0744573000, 0.0855997000, 0.1125900000, 0.1662030000, 0.2934026000, 0.6945541000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014448600, 0.0041752700, 0.0120654000, 0.0348657000, 0.1007530000, 0.2911480000"); - values("0.0317464000, 0.0380564000, 0.0537845000, 0.0932695000, 0.2068581000, 0.5309150000, 1.4953065000", \ - "0.0317829000, 0.0382779000, 0.0537678000, 0.0934199000, 0.2066765000, 0.5310651000, 1.4940287000", \ - "0.0317341000, 0.0380564000, 0.0537797000, 0.0932629000, 0.2071204000, 0.5314029000, 1.4944382000", \ - "0.0317335000, 0.0381935000, 0.0538891000, 0.0933758000, 0.2069857000, 0.5307507000, 1.4946150000", \ - "0.0325294000, 0.0387980000, 0.0542246000, 0.0936818000, 0.2068113000, 0.5306924000, 1.4934696000", \ - "0.0390722000, 0.0459454000, 0.0615096000, 0.1002998000, 0.2096930000, 0.5299378000, 1.4923844000", \ - "0.0540669000, 0.0627592000, 0.0805973000, 0.1184426000, 0.2194466000, 0.5316072000, 1.4915655000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0016250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0129427000, 0.0128525000, 0.0126446000, 0.0126966000, 0.0128169000, 0.0130940000, 0.0137328000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081090000, 0.0080587000, 0.0079428000, 0.0079717000, 0.0080385000, 0.0081926000, 0.0085477000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017040000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0740215000, 0.1979147000, 0.2898743000", \ - "-0.147528000, -0.022414100, 0.0695456000", \ - "-0.403061800, -0.277947900, -0.184767600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0850078000, -0.036444000, -0.119858700", \ - "0.2870260000, 0.1655742000, 0.0821595000", \ - "0.5352357000, 0.4162253000, 0.3315899000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2400893000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.105421900, -0.060874400, -0.076336600", \ - "-0.229315100, -0.168898400, -0.179477900", \ - "-0.334702500, -0.255975300, -0.253126900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1594707000, 0.1429994000, 0.2451315000", \ - "0.2980124000, 0.2546855000, 0.3092103000", \ - "0.4510072000, 0.3771628000, 0.3999492000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0017590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0029783000, 0.0029774000, 0.0029751000, 0.0029810000, 0.0029949000, 0.0030269000, 0.0031006000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002850600, -0.002847900, -0.002841900, -0.002852300, -0.002876200, -0.002931300, -0.003058300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018350000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2595684000, 0.4359518000, 0.7012513000", \ - "0.1320130000, 0.3059551000, 0.5688132000", \ - "-0.016099000, 0.1566224000, 0.4145977000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1643535000, 0.2980124000, 0.4473450000", \ - "-0.051092400, 0.0825664000, 0.2331198000", \ - "-0.291977900, -0.155877600, -0.006544900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.229933600, -0.402654900, -0.654526700", \ - "-0.103599000, -0.273878900, -0.522088600", \ - "0.0457337000, -0.123325500, -0.366652300"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.018752000, -0.154852200, -0.304184900", \ - "0.1759421000, 0.0459453000, -0.100946000", \ - "0.4107240000, 0.2819479000, 0.1423809000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0026180000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0024880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0095050000, 0.0094293000, 0.0092549000, 0.0092986000, 0.0093995000, 0.0096323000, 0.0101687000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0014667000, 0.0014233000, 0.0013234000, 0.0013460000, 0.0013984000, 0.0015191000, 0.0017974000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0027470000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3694316000, 0.5494772000, 0.8758119000", \ - "0.2357728000, 0.4158184000, 0.7409323000", \ - "0.0876608000, 0.2652650000, 0.5781719000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2681133000, 0.3505026000, 0.3753236000", \ - "0.1405579000, 0.2217266000, 0.2477682000", \ - "-0.006333300, 0.0748353000, 0.0996563000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.082228500, -0.279363900, -0.525132200", \ - "0.1149069000, -0.083449200, -0.326776000", \ - "0.3484681000, 0.1513327000, -0.093214800"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.000441400, -0.145086600, -0.276108700", \ - "0.1954733000, 0.0593730000, -0.071649100", \ - "0.4290345000, 0.2978171000, 0.1741191000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034250000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033390000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050563000, 0.0050478000, 0.0050281000, 0.0050420000, 0.0050744000, 0.0051490000, 0.0053209000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004873800, -0.004868200, -0.004855100, -0.004869400, -0.004902000, -0.004977100, -0.005150300"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035100000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.065138700, 0.0270163000, 0.1397279000", \ - "-0.254949900, -0.164015600, -0.097690800", \ - "-0.466538400, -0.375604200, -0.338576200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0715801000, -0.018133500, -0.051499400", \ - "0.2613913000, 0.1716777000, 0.1383119000", \ - "0.4717591000, 0.3820456000, 0.3535625000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1594707000, 0.2980124000, 0.4510072000", \ - "0.1429994000, 0.2546855000, 0.3771628000", \ - "0.2451315000, 0.3092103000, 0.3999492000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3092955000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.105421900, -0.229315100, -0.334702500", \ - "-0.060874400, -0.168898400, -0.255975300", \ - "-0.076336600, -0.179477900, -0.253126900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "!CLK_N"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK_N") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfbbp_1") { - leakage_power () { - value : 0.0137049000; - when : "!SET_B&!RESET_B&CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0137414000; - when : "!SET_B&!RESET_B&!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0139309000; - when : "!SET_B&!RESET_B&CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136533000; - when : "SET_B&!RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0117800000; - when : "SET_B&!RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0122461000; - when : "SET_B&!RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119597000; - when : "SET_B&!RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116178000; - when : "SET_B&!RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0130419000; - when : "SET_B&!RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0121636000; - when : "SET_B&!RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0128654000; - when : "SET_B&!RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0162376000; - when : "SET_B&RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0168490000; - when : "SET_B&RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0148135000; - when : "SET_B&RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0160611000; - when : "SET_B&RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0172201000; - when : "SET_B&RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0144559000; - when : "SET_B&RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0149221000; - when : "SET_B&RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0143025000; - when : "SET_B&RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0142535000; - when : "!SET_B&RESET_B&CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0122928000; - when : "SET_B&!RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0167011000; - when : "SET_B&RESET_B&CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0169050000; - when : "SET_B&RESET_B&CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0158834000; - when : "SET_B&RESET_B&CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0177296000; - when : "SET_B&RESET_B&!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0154713000; - when : "!SET_B&RESET_B&CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0148773000; - when : "SET_B&!RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0148396000; - when : "SET_B&RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0146357000; - when : "SET_B&RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0166087000; - when : "SET_B&RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0152819000; - when : "!SET_B&RESET_B&!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141193000; - when : "!SET_B&RESET_B&!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0145854000; - when : "!SET_B&RESET_B&!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0157422000; - when : "SET_B&RESET_B&!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0130829000; - when : "!SET_B&!RESET_B&!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142990000; - when : "!SET_B&RESET_B&!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0135010000; - when : "!SET_B&!RESET_B&CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0132464000; - when : "!SET_B&RESET_B&!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0146705000; - when : "!SET_B&RESET_B&!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0160287000; - when : "SET_B&RESET_B&!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0133694000; - when : "!SET_B&!RESET_B&!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0137874000; - when : "!SET_B&!RESET_B&CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0145029000; - when : "!SET_B&RESET_B&!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0155625000; - when : "SET_B&RESET_B&!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0129032000; - when : "!SET_B&!RESET_B&!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0133212000; - when : "!SET_B&!RESET_B&CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0144940000; - when : "!SET_B&RESET_B&!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0139179000; - when : "!SET_B&!RESET_B&!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141074000; - when : "!SET_B&!RESET_B&CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0145293000; - when : "!SET_B&!RESET_B&!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0147188000; - when : "!SET_B&!RESET_B&CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0124938000; - when : "!SET_B&!RESET_B&!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0126832000; - when : "!SET_B&!RESET_B&CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0159461000; - when : "SET_B&RESET_B&!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0132868000; - when : "!SET_B&!RESET_B&!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141228000; - when : "SET_B&RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0140738000; - when : "!SET_B&RESET_B&CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0121131000; - when : "SET_B&!RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0164322000; - when : "SET_B&RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0145065000; - when : "SET_B&RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0144574000; - when : "!SET_B&RESET_B&CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0124967000; - when : "SET_B&!RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0151846000; - when : "SET_B&RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0145890000; - when : "SET_B&RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0145399000; - when : "!SET_B&RESET_B&CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0125793000; - when : "SET_B&!RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0169876000; - when : "SET_B&RESET_B&CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0171310000; - when : "SET_B&RESET_B&CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0179190000; - when : "SET_B&RESET_B&CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0156941000; - when : "SET_B&RESET_B&!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0134358000; - when : "!SET_B&RESET_B&CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0128418000; - when : "SET_B&!RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0165214000; - when : "SET_B&RESET_B&CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0171181000; - when : "SET_B&RESET_B&!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0148599000; - when : "!SET_B&RESET_B&CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142659000; - when : "SET_B&!RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0173075000; - when : "SET_B&RESET_B&CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0169416000; - when : "SET_B&RESET_B&!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0146834000; - when : "!SET_B&RESET_B&CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0140893000; - when : "SET_B&!RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - area : 38.787200000; - cell_footprint : "sky130_fd_sc_hd__sdfbbp"; - cell_leakage_power : 0.0145604700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017630000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0231894000, 0.0230648000, 0.0227777000, 0.0228484000, 0.0230117000, 0.0233880000, 0.0242555000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0295745000, 0.0294864000, 0.0292834000, 0.0293179000, 0.0293979000, 0.0295822000, 0.0300071000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018510000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3817972000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2093310000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0015420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0014610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0076939000, 0.0075739000, 0.0072972000, 0.0073293000, 0.0074037000, 0.0075750000, 0.0079699000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022453000, 0.0022167000, 0.0021506000, 0.0021598000, 0.0021812000, 0.0022306000, 0.0023445000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016240000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3950664000, 0.5958640000, 0.9868958000", \ - "0.2638490000, 0.4646465000, 0.8593405000", \ - "0.1694479000, 0.3714662000, 0.7686016000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1167461000, 0.2479636000, 0.3509095000", \ - "0.0429017000, 0.1643535000, 0.2563132000", \ - "0.0217428000, 0.1407533000, 0.2229473000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.300734400, -0.501531900, -0.892563800", \ - "-0.191489600, -0.393507800, -0.788201800", \ - "-0.104412800, -0.307651700, -0.704787100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.089552700, -0.219549500, -0.313950500", \ - "-0.025474000, -0.146925800, -0.230340500", \ - "-0.001873700, -0.120884100, -0.201857400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.002185900, 0.0037584000, 0.0149671000, 0.0280103000, 0.0262155000, -0.022273400, -0.184252100", \ - "-0.002143500, 0.0038022000, 0.0150028000, 0.0280182000, 0.0261940000, -0.022271200, -0.184281700", \ - "-0.002046900, 0.0038862000, 0.0150584000, 0.0280244000, 0.0262129000, -0.022321300, -0.184307300", \ - "-0.002084600, 0.0038339000, 0.0149766000, 0.0278986000, 0.0260422000, -0.022523100, -0.184523000", \ - "-0.002161400, 0.0037431000, 0.0148595000, 0.0277469000, 0.0257918000, -0.022761200, -0.184796200", \ - "-0.002317000, 0.0035709000, 0.0146562000, 0.0275048000, 0.0254836000, -0.023120700, -0.185171600", \ - "-0.002587000, 0.0034012000, 0.0146891000, 0.0278359000, 0.0258212000, -0.023037700, -0.185040900"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0002105000, 0.0050050000, 0.0138679000, 0.0233749000, 0.0180995000, -0.032659800, -0.195793700", \ - "0.0002282000, 0.0050245000, 0.0138780000, 0.0233823000, 0.0180774000, -0.032636300, -0.195773300", \ - "0.0002727000, 0.0050537000, 0.0138998000, 0.0233834000, 0.0180474000, -0.032727800, -0.195811300", \ - "0.0002500000, 0.0049976000, 0.0137722000, 0.0231402000, 0.0177144000, -0.033153800, -0.196300500", \ - "0.0002347000, 0.0049339000, 0.0136293000, 0.0228685000, 0.0172817000, -0.033707300, -0.196929300", \ - "0.0002395000, 0.0049126000, 0.0135399000, 0.0226968000, 0.0169757000, -0.034223200, -0.197465000", \ - "0.0003712000, 0.0051411000, 0.0139739000, 0.0234207000, 0.0177832000, -0.034219700, -0.197487800"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-2.01000e-05, 0.0037454000, 0.0121662000, 0.0299049000, 0.0625720000, 0.1317912000, 0.3029082000", \ - "-2.90500e-05, 0.0037198000, 0.0121002000, 0.0297661000, 0.0624925000, 0.1311230000, 0.3015769000", \ - "-2.62500e-05, 0.0036980000, 0.0120360000, 0.0296322000, 0.0621806000, 0.1309388000, 0.3026448000", \ - "-4.31500e-05, 0.0036669000, 0.0119748000, 0.0295363000, 0.0619994000, 0.1309146000, 0.3020715000", \ - "-7.83000e-05, 0.0036034000, 0.0118599000, 0.0293149000, 0.0617376000, 0.1302923000, 0.3005069000", \ - "-0.000140100, 0.0035039000, 0.0116966000, 0.0290554000, 0.0613457000, 0.1302109000, 0.3001253000", \ - "-0.000222700, 0.0034260000, 0.0116309000, 0.0291979000, 0.0618894000, 0.1305163000, 0.3006773000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.011363600, -0.006621100, 0.0021676000, 0.0115376000, 0.0058356000, -0.045938600, -0.209233600", \ - "-0.011323300, -0.006583600, 0.0021923000, 0.0115424000, 0.0058241000, -0.045956900, -0.209252800", \ - "-0.011232600, -0.006503100, 0.0022413000, 0.0115621000, 0.0058197000, -0.046037000, -0.209338600", \ - "-0.011275600, -0.006579800, 0.0020946000, 0.0112974000, 0.0054216000, -0.046487600, -0.209786700", \ - "-0.011332300, -0.006659900, 0.0019723000, 0.0111127000, 0.0051687000, -0.046797400, -0.210162000", \ - "-0.011422200, -0.006747000, 0.0018911000, 0.0110122000, 0.0050746000, -0.046856600, -0.210212100", \ - "-0.011575500, -0.006820400, 0.0019784000, 0.0113802000, 0.0056375000, -0.046307600, -0.209598400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.012769100, -0.009706500, -0.002656400, 0.0123924000, 0.0421867000, 0.1097745000, 0.2790940000", \ - "-0.012728800, -0.009671500, -0.002622500, 0.0123438000, 0.0421082000, 0.1093509000, 0.2799585000", \ - "-0.012635900, -0.009595400, -0.002568700, 0.0123733000, 0.0421341000, 0.1095786000, 0.2799924000", \ - "-0.012675300, -0.009660000, -0.002706000, 0.0121430000, 0.0418117000, 0.1092406000, 0.2780106000", \ - "-0.012730000, -0.009742400, -0.002830600, 0.0119457000, 0.0417042000, 0.1090527000, 0.2783847000", \ - "-0.012814900, -0.009814700, -0.002887000, 0.0119201000, 0.0417356000, 0.1084014000, 0.2796341000", \ - "-0.012917400, -0.009754900, -0.002541700, 0.0122429000, 0.0418587000, 0.1086848000, 0.2801479000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5058740000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4057611000, 0.4110451000, 0.4223340000, 0.4455158000, 0.4980242000, 0.6315779000, 0.9844120000", \ - "0.4104582000, 0.4157397000, 0.4269695000, 0.4502101000, 0.5027181000, 0.6362760000, 0.9885864000", \ - "0.4215281000, 0.4268461000, 0.4380520000, 0.4612968000, 0.5138236000, 0.6474514000, 1.0004164000", \ - "0.4473537000, 0.4526923000, 0.4638843000, 0.4871704000, 0.5395910000, 0.6733190000, 1.0261880000", \ - "0.4961527000, 0.5014805000, 0.5126819000, 0.5359727000, 0.5883929000, 0.7220239000, 1.0748822000", \ - "0.5690775000, 0.5743822000, 0.5855996000, 0.6088482000, 0.6612359000, 0.7949837000, 1.1475925000", \ - "0.6632337000, 0.6685207000, 0.6797279000, 0.7030017000, 0.7555078000, 0.8889721000, 1.2413668000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4725688000, 0.4793689000, 0.4944147000, 0.5303303000, 0.6234395000, 0.8678445000, 1.5132776000", \ - "0.4775719000, 0.4842275000, 0.4992754000, 0.5352934000, 0.6279773000, 0.8726809000, 1.5198580000", \ - "0.4885734000, 0.4952183000, 0.5103741000, 0.5462946000, 0.6394743000, 0.8841744000, 1.5275680000", \ - "0.5146099000, 0.5212665000, 0.5363933000, 0.5723228000, 0.6653932000, 0.9098279000, 1.5572293000", \ - "0.5635254000, 0.5702616000, 0.5853001000, 0.6212817000, 0.7140630000, 0.9586371000, 1.6039186000", \ - "0.6330040000, 0.6396558000, 0.6547830000, 0.6907066000, 0.7836719000, 1.0279072000, 1.6764293000", \ - "0.7197742000, 0.7264688000, 0.7415710000, 0.7773034000, 0.8703407000, 1.1147357000, 1.7603142000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0175871000, 0.0216583000, 0.0312186000, 0.0546053000, 0.1180342000, 0.2939858000, 0.7656052000", \ - "0.0175876000, 0.0216630000, 0.0312299000, 0.0546025000, 0.1180273000, 0.2942394000, 0.7646436000", \ - "0.0175763000, 0.0217897000, 0.0311709000, 0.0544993000, 0.1179061000, 0.2947292000, 0.7707338000", \ - "0.0178205000, 0.0216313000, 0.0311500000, 0.0544534000, 0.1181744000, 0.2943240000, 0.7689290000", \ - "0.0176458000, 0.0217434000, 0.0311640000, 0.0544734000, 0.1181909000, 0.2938781000, 0.7615542000", \ - "0.0175957000, 0.0216139000, 0.0310161000, 0.0546123000, 0.1181548000, 0.2942712000, 0.7723858000", \ - "0.0175429000, 0.0215399000, 0.0310409000, 0.0547833000, 0.1181393000, 0.2938730000, 0.7620788000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0235002000, 0.0297287000, 0.0464912000, 0.0945361000, 0.2261325000, 0.5747860000, 1.4978501000", \ - "0.0234027000, 0.0295987000, 0.0463714000, 0.0945178000, 0.2258670000, 0.5754476000, 1.5002817000", \ - "0.0234712000, 0.0296298000, 0.0464827000, 0.0945746000, 0.2262124000, 0.5757703000, 1.5058735000", \ - "0.0234449000, 0.0295542000, 0.0463576000, 0.0945561000, 0.2265509000, 0.5757896000, 1.5031943000", \ - "0.0235206000, 0.0295412000, 0.0465003000, 0.0945017000, 0.2264533000, 0.5743722000, 1.5003868000", \ - "0.0234411000, 0.0295509000, 0.0463672000, 0.0945562000, 0.2263161000, 0.5748684000, 1.5040739000", \ - "0.0234922000, 0.0295914000, 0.0464713000, 0.0944974000, 0.2262714000, 0.5739247000, 1.5034012000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2981591000, 0.3035300000, 0.3149160000, 0.3382795000, 0.3909912000, 0.5246280000, 0.8769932000", \ - "0.3035162000, 0.3088942000, 0.3202744000, 0.3437089000, 0.3963164000, 0.5298990000, 0.8822217000", \ - "0.3162129000, 0.3215528000, 0.3329325000, 0.3563800000, 0.4089404000, 0.5427420000, 0.8950808000", \ - "0.3474394000, 0.3527760000, 0.3641600000, 0.3876073000, 0.4401695000, 0.5739692000, 0.9263000000", \ - "0.4170925000, 0.4224706000, 0.4338516000, 0.4572862000, 0.5098971000, 0.6435170000, 0.9958363000", \ - "0.5443980000, 0.5497023000, 0.5610653000, 0.5845091000, 0.6371058000, 0.7709193000, 1.1233796000", \ - "0.7434935000, 0.7488884000, 0.7603377000, 0.7838391000, 0.8365482000, 0.9701560000, 1.3224792000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0180720000, 0.0222796000, 0.0316100000, 0.0549285000, 0.1183733000, 0.2936159000, 0.7637931000", \ - "0.0180898000, 0.0220043000, 0.0316561000, 0.0550806000, 0.1181654000, 0.2935739000, 0.7629167000", \ - "0.0179524000, 0.0221622000, 0.0314995000, 0.0549569000, 0.1182591000, 0.2935701000, 0.7629345000", \ - "0.0179501000, 0.0221757000, 0.0315025000, 0.0549578000, 0.1183135000, 0.2936178000, 0.7629951000", \ - "0.0180980000, 0.0220033000, 0.0316625000, 0.0550682000, 0.1181613000, 0.2933244000, 0.7629991000", \ - "0.0180168000, 0.0220131000, 0.0316969000, 0.0551137000, 0.1182990000, 0.2934097000, 0.7627739000", \ - "0.0183368000, 0.0222128000, 0.0318616000, 0.0553041000, 0.1186344000, 0.2940414000, 0.7631281000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.2012305000, 0.2065591000, 0.2179315000, 0.2413129000, 0.2940049000, 0.4277394000, 0.7801251000", \ - "0.2060059000, 0.2113376000, 0.2227355000, 0.2461621000, 0.2987605000, 0.4325814000, 0.7849182000", \ - "0.2158958000, 0.2212309000, 0.2326316000, 0.2560533000, 0.3086367000, 0.4425136000, 0.7948180000", \ - "0.2372958000, 0.2426413000, 0.2540031000, 0.2774375000, 0.3300197000, 0.4639189000, 0.8163273000", \ - "0.2843827000, 0.2897910000, 0.3011262000, 0.3245652000, 0.3772419000, 0.5110192000, 0.8634124000", \ - "0.3629777000, 0.3685166000, 0.3801119000, 0.4038490000, 0.4567554000, 0.5905102000, 0.9429616000", \ - "0.4618213000, 0.4677986000, 0.4799049000, 0.5043219000, 0.5579296000, 0.6915916000, 1.0439278000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3267877000, 0.3341569000, 0.3499636000, 0.3862777000, 0.4793586000, 0.7236445000, 1.3681393000", \ - "0.3319673000, 0.3393318000, 0.3550735000, 0.3914375000, 0.4845227000, 0.7287403000, 1.3733545000", \ - "0.3448856000, 0.3522589000, 0.3680545000, 0.4044063000, 0.4974405000, 0.7418506000, 1.3874546000", \ - "0.3766912000, 0.3840649000, 0.3998657000, 0.4361617000, 0.5292620000, 0.7737184000, 1.4187885000", \ - "0.4527959000, 0.4601403000, 0.4759630000, 0.5122957000, 0.6053645000, 0.8496537000, 1.4940676000", \ - "0.6310801000, 0.6384626000, 0.6542896000, 0.6906110000, 0.7836540000, 1.0279236000, 1.6726308000", \ - "0.9819657000, 0.9902480000, 1.0072613000, 1.0441242000, 1.1370773000, 1.3817052000, 2.0258937000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0179202000, 0.0222361000, 0.0315792000, 0.0549187000, 0.1180368000, 0.2940250000, 0.7631481000", \ - "0.0179309000, 0.0221854000, 0.0314941000, 0.0550041000, 0.1182141000, 0.2936530000, 0.7624338000", \ - "0.0179278000, 0.0221751000, 0.0314760000, 0.0549954000, 0.1182708000, 0.2936598000, 0.7622921000", \ - "0.0179949000, 0.0221310000, 0.0314788000, 0.0549757000, 0.1182478000, 0.2936622000, 0.7632134000", \ - "0.0182949000, 0.0223013000, 0.0317002000, 0.0550502000, 0.1180370000, 0.2936747000, 0.7632575000", \ - "0.0188389000, 0.0227688000, 0.0324158000, 0.0557771000, 0.1189526000, 0.2938550000, 0.7641361000", \ - "0.0214103000, 0.0251932000, 0.0349509000, 0.0575713000, 0.1196900000, 0.2942083000, 0.7604974000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0264253000, 0.0326359000, 0.0485605000, 0.0952417000, 0.2266163000, 0.5754300000, 1.4986059000", \ - "0.0263934000, 0.0324789000, 0.0485252000, 0.0954307000, 0.2267257000, 0.5756376000, 1.4948627000", \ - "0.0264400000, 0.0325389000, 0.0486156000, 0.0954566000, 0.2263621000, 0.5740877000, 1.4994909000", \ - "0.0264366000, 0.0325369000, 0.0485607000, 0.0954160000, 0.2262112000, 0.5741592000, 1.4982033000", \ - "0.0265358000, 0.0325423000, 0.0485607000, 0.0952717000, 0.2266458000, 0.5754325000, 1.4963829000", \ - "0.0265710000, 0.0327162000, 0.0486467000, 0.0953691000, 0.2266884000, 0.5747322000, 1.4982976000", \ - "0.0314164000, 0.0371842000, 0.0521451000, 0.0965228000, 0.2264824000, 0.5742984000, 1.4969843000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.011151200, -0.006264400, 0.0026647000, 0.0123320000, 0.0081387000, -0.038052500, -0.184871400", \ - "-0.011120400, -0.006247900, 0.0026484000, 0.0122477000, 0.0080250000, -0.038168100, -0.185009600", \ - "-0.011031600, -0.006171200, 0.0026943000, 0.0122681000, 0.0079821000, -0.038273600, -0.185147100", \ - "-0.011063600, -0.006223600, 0.0025877000, 0.0121004000, 0.0077517000, -0.038520200, -0.185427300", \ - "-0.011119900, -0.006306900, 0.0024682000, 0.0118921000, 0.0074804000, -0.038817000, -0.185733200", \ - "-0.011210500, -0.006395400, 0.0023784000, 0.0118115000, 0.0073774000, -0.038940300, -0.185875100", \ - "-0.011360100, -0.006454100, 0.0024934000, 0.0122160000, 0.0080741000, -0.038450900, -0.185319700"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.012687400, -0.009595800, -0.002666900, 0.0115432000, 0.0395128000, 0.1019562000, 0.2551899000", \ - "-0.012648300, -0.009563100, -0.002642700, 0.0115445000, 0.0395986000, 0.1015567000, 0.2550686000", \ - "-0.012563300, -0.009502700, -0.002629000, 0.0114765000, 0.0393304000, 0.1017103000, 0.2546387000", \ - "-0.012597400, -0.009559800, -0.002733100, 0.0113074000, 0.0391178000, 0.1012936000, 0.2549009000", \ - "-0.012658600, -0.009651600, -0.002884700, 0.0110618000, 0.0388068000, 0.1011211000, 0.2556463000", \ - "-0.012753300, -0.009748900, -0.002991100, 0.0109661000, 0.0386892000, 0.1005361000, 0.2540358000", \ - "-0.012900600, -0.009802200, -0.002843900, 0.0113031000, 0.0390948000, 0.1010364000, 0.2556507000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.003704800, 0.0002781000, 0.0089555000, 0.0279385000, 0.0605810000, 0.1250491000, 0.2798717000", \ - "-0.003661800, 0.0003202000, 0.0089929000, 0.0279233000, 0.0606085000, 0.1250628000, 0.2804078000", \ - "-0.003564400, 0.0004024000, 0.0090493000, 0.0279522000, 0.0606060000, 0.1250718000, 0.2799683000", \ - "-0.003602300, 0.0003479000, 0.0089684000, 0.0278275000, 0.0604370000, 0.1248692000, 0.2802276000", \ - "-0.003678900, 0.0002627000, 0.0088509000, 0.0276435000, 0.0601965000, 0.1247533000, 0.2790861000", \ - "-0.003832800, 9.580000e-05, 0.0086580000, 0.0274229000, 0.0598698000, 0.1241985000, 0.2787426000", \ - "-0.003861300, 0.0005058000, 0.0099748000, 0.0278338000, 0.0598458000, 0.1242756000, 0.2789911000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("0.0016784000, 0.0073635000, 0.0178561000, 0.0298441000, 0.0282120000, -0.015932200, -0.161731200", \ - "0.0016712000, 0.0073375000, 0.0177816000, 0.0297121000, 0.0280414000, -0.016156300, -0.161989300", \ - "0.0016685000, 0.0073117000, 0.0177247000, 0.0295962000, 0.0278302000, -0.016416900, -0.162278700", \ - "0.0016539000, 0.0072886000, 0.0176638000, 0.0294821000, 0.0277037000, -0.016574400, -0.162415400", \ - "0.0016182000, 0.0072253000, 0.0175494000, 0.0292891000, 0.0274041000, -0.016902200, -0.162755100", \ - "0.0015624000, 0.0071386000, 0.0174098000, 0.0290067000, 0.0270020000, -0.017344600, -0.163200100", \ - "0.0015304000, 0.0071674000, 0.0174894000, 0.0291224000, 0.0273138000, -0.016942500, -0.162720400"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012991020, 0.0033753300, 0.0087697930, 0.0227857000, 0.0592018900, 0.1538185000"); - values("-0.001353800, 0.0014512000, 0.0077684000, 0.0232478000, 0.0524869000, 0.1147575000, 0.2675251000", \ - "-0.001331900, 0.0014689000, 0.0077957000, 0.0232620000, 0.0524698000, 0.1148162000, 0.2677387000", \ - "-0.001287100, 0.0015040000, 0.0078056000, 0.0232719000, 0.0524693000, 0.1147856000, 0.2676767000", \ - "-0.001305600, 0.0014495000, 0.0076878000, 0.0230356000, 0.0521184000, 0.1141278000, 0.2674056000", \ - "-0.001313800, 0.0014181000, 0.0075801000, 0.0227707000, 0.0516534000, 0.1134643000, 0.2663911000", \ - "-0.001271800, 0.0014774000, 0.0076831000, 0.0226297000, 0.0512159000, 0.1130365000, 0.2661062000", \ - "-0.000931200, 0.0022067000, 0.0092313000, 0.0234161000, 0.0512291000, 0.1131411000, 0.2657982000"); - } - } - max_capacitance : 0.1538190000; - max_transition : 1.5028750000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.4006315000, 0.4097979000, 0.4286320000, 0.4643859000, 0.5318443000, 0.6666013000, 0.9856519000", \ - "0.4056050000, 0.4147671000, 0.4335270000, 0.4694011000, 0.5368597000, 0.6715475000, 0.9904362000", \ - "0.4165918000, 0.4257544000, 0.4445221000, 0.4803837000, 0.5478488000, 0.6825694000, 1.0017931000", \ - "0.4423612000, 0.4515281000, 0.4703555000, 0.5060976000, 0.5735519000, 0.7083004000, 1.0275852000", \ - "0.4915193000, 0.5006798000, 0.5194247000, 0.5552996000, 0.6227747000, 0.7574654000, 1.0767008000", \ - "0.5611687000, 0.5702963000, 0.5890387000, 0.6249301000, 0.6923817000, 0.8271068000, 1.1463800000", \ - "0.6479053000, 0.6571008000, 0.6758582000, 0.7116948000, 0.7791437000, 0.9138699000, 1.2330132000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.3480837000, 0.3572028000, 0.3770055000, 0.4196214000, 0.5190410000, 0.7660415000, 1.4052803000", \ - "0.3527565000, 0.3618942000, 0.3816859000, 0.4243113000, 0.5237379000, 0.7711534000, 1.4101257000", \ - "0.3638184000, 0.3729461000, 0.3927415000, 0.4353584000, 0.5347899000, 0.7815367000, 1.4188968000", \ - "0.3896910000, 0.3988221000, 0.4186204000, 0.4612383000, 0.5606599000, 0.8077379000, 1.4474503000", \ - "0.4388618000, 0.4479911000, 0.4677886000, 0.5104066000, 0.6098378000, 0.8563922000, 1.4949419000", \ - "0.5113804000, 0.5205217000, 0.5403105000, 0.5829338000, 0.6823769000, 0.9293059000, 1.5692089000", \ - "0.6056466000, 0.6147911000, 0.6345983000, 0.6772419000, 0.7766920000, 1.0236113000, 1.6646720000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0358379000, 0.0421830000, 0.0551374000, 0.0825959000, 0.1421615000, 0.2888361000, 0.6981334000", \ - "0.0358013000, 0.0416315000, 0.0548193000, 0.0824704000, 0.1418475000, 0.2884752000, 0.7002786000", \ - "0.0357964000, 0.0416308000, 0.0549153000, 0.0824776000, 0.1420897000, 0.2893863000, 0.6992660000", \ - "0.0356796000, 0.0419939000, 0.0551397000, 0.0825942000, 0.1422499000, 0.2894359000, 0.7002107000", \ - "0.0357799000, 0.0416074000, 0.0549004000, 0.0824601000, 0.1420390000, 0.2886561000, 0.6992218000", \ - "0.0358971000, 0.0416581000, 0.0549239000, 0.0824953000, 0.1418589000, 0.2888211000, 0.6987059000", \ - "0.0358968000, 0.0419332000, 0.0550085000, 0.0825729000, 0.1421063000, 0.2895545000, 0.6968472000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0333419000, 0.0411325000, 0.0602126000, 0.1095140000, 0.2394602000, 0.5853492000, 1.4992254000", \ - "0.0334061000, 0.0412638000, 0.0600870000, 0.1095935000, 0.2392886000, 0.5852037000, 1.4958143000", \ - "0.0333202000, 0.0411286000, 0.0601004000, 0.1095295000, 0.2389708000, 0.5855385000, 1.4956416000", \ - "0.0333401000, 0.0411335000, 0.0602122000, 0.1095119000, 0.2393440000, 0.5852807000, 1.5028746000", \ - "0.0333292000, 0.0411322000, 0.0601026000, 0.1095474000, 0.2394699000, 0.5860407000, 1.4993992000", \ - "0.0334289000, 0.0412336000, 0.0600606000, 0.1096149000, 0.2393091000, 0.5858514000, 1.4956146000", \ - "0.0333433000, 0.0411036000, 0.0601505000, 0.1095902000, 0.2390359000, 0.5853831000, 1.4949126000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2396027000, 0.2492037000, 0.2699727000, 0.3144510000, 0.4177388000, 0.6676737000, 1.3083092000", \ - "0.2449741000, 0.2545791000, 0.2753351000, 0.3198254000, 0.4231173000, 0.6730410000, 1.3116327000", \ - "0.2575893000, 0.2672154000, 0.2879776000, 0.3324728000, 0.4357698000, 0.6855779000, 1.3241118000", \ - "0.2888066000, 0.2984313000, 0.3192000000, 0.3636871000, 0.4669824000, 0.7167778000, 1.3552968000", \ - "0.3585457000, 0.3681595000, 0.3889193000, 0.4333526000, 0.5366451000, 0.7865626000, 1.4250052000", \ - "0.4859430000, 0.4956379000, 0.5165927000, 0.5613445000, 0.6648481000, 0.9145251000, 1.5519467000", \ - "0.6838170000, 0.6938758000, 0.7152943000, 0.7606817000, 0.8654567000, 1.1152809000, 1.7534342000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0351897000, 0.0435629000, 0.0632180000, 0.1144593000, 0.2466528000, 0.5875197000, 1.4962500000", \ - "0.0351489000, 0.0435373000, 0.0631869000, 0.1144703000, 0.2474793000, 0.5881708000, 1.4906887000", \ - "0.0353380000, 0.0434882000, 0.0632522000, 0.1143749000, 0.2475057000, 0.5879467000, 1.4962694000", \ - "0.0353534000, 0.0435045000, 0.0632592000, 0.1143836000, 0.2475053000, 0.5879480000, 1.4962995000", \ - "0.0351802000, 0.0435624000, 0.0632183000, 0.1144793000, 0.2473239000, 0.5877904000, 1.4946336000", \ - "0.0360190000, 0.0442087000, 0.0638477000, 0.1149593000, 0.2473283000, 0.5879475000, 1.4961550000", \ - "0.0379348000, 0.0461593000, 0.0657266000, 0.1167774000, 0.2477945000, 0.5881308000, 1.4956965000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.2435210000, 0.2547189000, 0.2782951000, 0.3231330000, 0.4044971000, 0.5499269000, 0.8734229000", \ - "0.2486042000, 0.2599133000, 0.2834115000, 0.3282846000, 0.4095990000, 0.5550207000, 0.8786349000", \ - "0.2615281000, 0.2727445000, 0.2963730000, 0.3412197000, 0.4225041000, 0.5679121000, 0.8911646000", \ - "0.2934790000, 0.3048391000, 0.3283040000, 0.3731421000, 0.4544183000, 0.5998420000, 0.9231577000", \ - "0.3695722000, 0.3807027000, 0.4042535000, 0.4490001000, 0.5303136000, 0.6758078000, 0.9990376000", \ - "0.5469448000, 0.5584042000, 0.5821456000, 0.6269011000, 0.7080923000, 0.8536575000, 1.1771641000", \ - "0.8749467000, 0.8909553000, 0.9236221000, 0.9801640000, 1.0720869000, 1.2243860000, 1.5495475000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.1424171000, 0.1520309000, 0.1727711000, 0.2172282000, 0.3202705000, 0.5699197000, 1.2077892000", \ - "0.1471941000, 0.1567955000, 0.1775616000, 0.2220117000, 0.3250785000, 0.5747366000, 1.2132207000", \ - "0.1570862000, 0.1666827000, 0.1874566000, 0.2319134000, 0.3349982000, 0.5846807000, 1.2227053000", \ - "0.1784983000, 0.1880824000, 0.2088776000, 0.2532593000, 0.3563983000, 0.6061553000, 1.2437388000", \ - "0.2248104000, 0.2346885000, 0.2556910000, 0.3003211000, 0.4036331000, 0.6533584000, 1.2910840000", \ - "0.2981366000, 0.3095049000, 0.3329923000, 0.3804817000, 0.4859220000, 0.7353171000, 1.3730181000", \ - "0.3832358000, 0.3981856000, 0.4281977000, 0.4834551000, 0.5944101000, 0.8443717000, 1.4825788000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0470673000, 0.0541740000, 0.0703757000, 0.1044671000, 0.1658177000, 0.3048007000, 0.7056092000", \ - "0.0469262000, 0.0541500000, 0.0704163000, 0.1043357000, 0.1659549000, 0.3046728000, 0.7045852000", \ - "0.0468543000, 0.0542910000, 0.0705451000, 0.1044727000, 0.1655242000, 0.3043977000, 0.7041788000", \ - "0.0471197000, 0.0543769000, 0.0704768000, 0.1044144000, 0.1658164000, 0.3046787000, 0.7043597000", \ - "0.0466048000, 0.0542496000, 0.0705041000, 0.1044576000, 0.1656089000, 0.3045261000, 0.7038999000", \ - "0.0493810000, 0.0566784000, 0.0721379000, 0.1053305000, 0.1661726000, 0.3049385000, 0.7048401000", \ - "0.0768440000, 0.0864175000, 0.1040370000, 0.1348532000, 0.1868016000, 0.3159617000, 0.7063551000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012991000, 0.0033753300, 0.0087697900, 0.0227857000, 0.0592019000, 0.1538190000"); - values("0.0351447000, 0.0433397000, 0.0632023000, 0.1142635000, 0.2474989000, 0.5880697000, 1.4957597000", \ - "0.0351250000, 0.0434212000, 0.0631327000, 0.1143306000, 0.2475200000, 0.5876890000, 1.4934473000", \ - "0.0351291000, 0.0434227000, 0.0631252000, 0.1143579000, 0.2473324000, 0.5879922000, 1.4954458000", \ - "0.0350673000, 0.0434756000, 0.0631006000, 0.1143746000, 0.2472552000, 0.5879687000, 1.4956583000", \ - "0.0364469000, 0.0446097000, 0.0642647000, 0.1148046000, 0.2470327000, 0.5878046000, 1.4957299000", \ - "0.0435905000, 0.0519372000, 0.0715278000, 0.1211163000, 0.2493180000, 0.5879196000, 1.4958491000", \ - "0.0597566000, 0.0697363000, 0.0899106000, 0.1372406000, 0.2580121000, 0.5892659000, 1.4953904000"); - } - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0016390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015590000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0128997000, 0.0128093000, 0.0126009000, 0.0126561000, 0.0127834000, 0.0130768000, 0.0137532000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079937000, 0.0079397000, 0.0078152000, 0.0078445000, 0.0079124000, 0.0080689000, 0.0084296000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017180000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0581523000, 0.1832663000, 0.2752259000", \ - "-0.064520200, 0.0581523000, 0.1464499000", \ - "-0.154038400, -0.031365900, 0.0532695000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.030959000, -0.153631500, -0.240708300", \ - "0.0892721000, -0.032179700, -0.116815100", \ - "0.1800111000, 0.0573385000, -0.027296900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2203161000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.062095000, -0.076336600", \ - "-0.229315100, -0.168898400, -0.178257200", \ - "-0.334702500, -0.255975300, -0.250685500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "SET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.1027161000, 0.1840964000", \ - "0.2711569000, 0.2156230000, 0.2493958000", \ - "0.4021790000, 0.3271139000, 0.3291484000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0017440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017040000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031006000, 0.0030973000, 0.0030897000, 0.0030960000, 0.0031106000, 0.0031442000, 0.0032218000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002971600, -0.002966900, -0.002956000, -0.002966200, -0.002989600, -0.003043600, -0.003168000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2876445000, 0.4628073000, 0.7317689000", \ - "0.1539857000, 0.3303691000, 0.6005514000", \ - "0.0571432000, 0.2335267000, 0.5061504000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1521465000, 0.2870260000, 0.4363587000", \ - "0.0770814000, 0.2082988000, 0.3478659000", \ - "0.0571432000, 0.1871400000, 0.3242656000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.188429700, -0.362371800, -0.620347000", \ - "-0.079184900, -0.254347700, -0.517205700", \ - "0.0054505000, -0.168491500, -0.433791000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.122511700, -0.254949900, -0.398179000", \ - "-0.060874400, -0.188429700, -0.324334600", \ - "-0.039715500, -0.168491500, -0.304396500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0026210000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0024860000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0096099000, 0.0095306000, 0.0093478000, 0.0094067000, 0.0095428000, 0.0098564000, 0.0105794000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0014231000, 0.0013803000, 0.0012817000, 0.0013039000, 0.0013554000, 0.0014740000, 0.0017475000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0027560000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4036113000, 0.5836569000, 0.9148743000", \ - "0.2736146000, 0.4524395000, 0.7860983000", \ - "0.1767721000, 0.3580384000, 0.6953594000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2961895000, 0.3773581000, 0.4021790000", \ - "0.1625306000, 0.2436992000, 0.2709616000", \ - "0.0656882000, 0.1468568000, 0.1728984000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.185988300, -0.383123700, -0.627671200", \ - "-0.121909500, -0.319044900, -0.563592500", \ - "-0.098309200, -0.295444700, -0.541212900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.243963600, -0.366440800", \ - "-0.041343100, -0.172560500, -0.284051400", \ - "-0.020184200, -0.150181000, -0.256789100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0034300000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0050650000, 0.0050511000, 0.0050191000, 0.0050331000, 0.0050658000, 0.0051410000, 0.0053143000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0064941000, 0.0064514000, 0.0063529000, 0.0063426000, 0.0063191000, 0.0062649000, 0.0061400000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035170000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.039503900, 0.0746237000, 0.2422669000", \ - "-0.193914700, -0.077345700, 0.0707663000", \ - "-0.318833300, -0.201043600, -0.061476600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1240703000, 0.0392396000, 0.0083151000", \ - "0.2601706000, 0.1753398000, 0.1444154000", \ - "0.3704408000, 0.2831686000, 0.2522441000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1374980000, 0.2711569000, 0.4021790000", \ - "0.1027161000, 0.2156230000, 0.3271139000", \ - "0.1840964000, 0.2493958000, 0.3291484000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2532714000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "RESET_B"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.229315100, -0.334702500", \ - "-0.062095000, -0.168898400, -0.255975300", \ - "-0.076336600, -0.178257200, -0.250685500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "non_seq_hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clear_preset_var1 : "H"; - clear_preset_var2 : "L"; - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrbp_1") { - leakage_power () { - value : 0.0188441000; - when : "!RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0185804000; - when : "!RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0183437000; - when : "!RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0189362000; - when : "!RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0186853000; - when : "!RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0201140000; - when : "RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0193965000; - when : "RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0193002000; - when : "RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0188558000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0184036000; - when : "!RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0097048000; - when : "RESET_B&CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0101687000; - when : "RESET_B&CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0086776000; - when : "RESET_B&CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0085515000; - when : "RESET_B&!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0193508000; - when : "!RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0196307000; - when : "RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0191668000; - when : "RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0203777000; - when : "RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0190855000; - when : "RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0186332000; - when : "!RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0202189000; - when : "RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0193197000; - when : "RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0188675000; - when : "!RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0198772000; - when : "RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0189892000; - when : "RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0185369000; - when : "!RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0098381000; - when : "RESET_B&CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0090192000; - when : "RESET_B&CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0089143000; - when : "RESET_B&CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0083147000; - when : "RESET_B&!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0191140000; - when : "!RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0099344000; - when : "RESET_B&CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0088151000; - when : "RESET_B&!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0196144000; - when : "!RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0091780000; - when : "RESET_B&CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0086564000; - when : "RESET_B&!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0194557000; - when : "!RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0187211000; - when : "RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0184723000; - when : "!RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0105662000; - when : "RESET_B&!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0104699000; - when : "RESET_B&!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0103365000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0184844000; - when : "RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0189848000; - when : "RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0186056000; - when : "!RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0187019000; - when : "!RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0108004000; - when : "RESET_B&!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0188261000; - when : "RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__sdfrbp"; - cell_leakage_power : 0.0158841600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0024510000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0296423000, 0.0294645000, 0.0290547000, 0.0291850000, 0.0294855000, 0.0301783000, 0.0317751000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184353000, 0.0183165000, 0.0180427000, 0.0181136000, 0.0182771000, 0.0186541000, 0.0195230000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025790000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2653551000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1533070000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079880000, 0.0079024000, 0.0077050000, 0.0077455000, 0.0078392000, 0.0080551000, 0.0085528000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022782000, 0.0022455000, 0.0021701000, 0.0021796000, 0.0022017000, 0.0022527000, 0.0023703000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016760000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2974102000, 0.4957663000, 0.8489564000", \ - "0.2028138000, 0.4023906000, 0.7555808000", \ - "0.1560202000, 0.3568177000, 0.7087871000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1228496000, 0.2613913000, 0.3826478000", \ - "0.0721986000, 0.2021953000, 0.3112448000", \ - "0.0803366000, 0.2054505000, 0.3083965000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.178664100, -0.377020200, -0.677720100", \ - "-0.109702500, -0.309279300, -0.636834700", \ - "-0.073895200, -0.274692700, -0.608351500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.084669900, -0.215887400, -0.309067700", \ - "-0.049888000, -0.176222700, -0.274285800", \ - "-0.062908900, -0.186802100, -0.284865200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013351650, 0.0035653330, 0.0095206180, 0.0254232000, 0.0678883500, 0.1812843000"); - values("-0.006039200, -0.001549100, 0.0068139000, 0.0154940000, 0.0081728000, -0.048287800, -0.225966100", \ - "-0.005984400, -0.001502600, 0.0068208000, 0.0155260000, 0.0081607000, -0.048271300, -0.225989500", \ - "-0.005863200, -0.001398600, 0.0068828000, 0.0154602000, 0.0080559000, -0.048434500, -0.226127800", \ - "-0.005926300, -0.001505000, 0.0066989000, 0.0151535000, 0.0076088000, -0.048921900, -0.226697700", \ - "-0.006016600, -0.001614200, 0.0065460000, 0.0149789000, 0.0073793000, -0.049266900, -0.227036000", \ - "-0.006189300, -0.001756500, 0.0064656000, 0.0149570000, 0.0074180000, -0.049149700, -0.226856500", \ - "-0.006524100, -0.001955200, 0.0065626000, 0.0155048000, 0.0084707000, -0.048106600, -0.225722900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013351650, 0.0035653330, 0.0095206180, 0.0254232000, 0.0678883500, 0.1812843000"); - values("-0.007563800, -0.004971800, 0.0011886000, 0.0147369000, 0.0442359000, 0.1149229000, 0.2994720000", \ - "-0.007512600, -0.004931700, 0.0012013000, 0.0147062000, 0.0442012000, 0.1147338000, 0.2991629000", \ - "-0.007390300, -0.004828000, 0.0012641000, 0.0147270000, 0.0440695000, 0.1153207000, 0.2981773000", \ - "-0.007456100, -0.004940500, 0.0010533000, 0.0143756000, 0.0435792000, 0.1147250000, 0.2975461000", \ - "-0.007551000, -0.005055400, 0.0008988000, 0.0141584000, 0.0432958000, 0.1143984000, 0.2971947000", \ - "-0.007729700, -0.005220300, 0.0007656000, 0.0140596000, 0.0433059000, 0.1143746000, 0.2971635000", \ - "-0.008062100, -0.005402900, 0.0008970000, 0.0146881000, 0.0442232000, 0.1151473000, 0.2972498000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013351650, 0.0035653330, 0.0095206180, 0.0254232000, 0.0678883500, 0.1812843000"); - values("0.0001856000, 0.0038666000, 0.0105670000, 0.0167152000, 0.0068561000, -0.051263700, -0.229763300", \ - "0.0001753000, 0.0038423000, 0.0105129000, 0.0166310000, 0.0067233000, -0.051405100, -0.229891600", \ - "0.0001584000, 0.0038143000, 0.0104558000, 0.0165268000, 0.0065865000, -0.051565200, -0.230060200", \ - "0.0001530000, 0.0038110000, 0.0104441000, 0.0165171000, 0.0065656000, -0.051577900, -0.230079400", \ - "0.0001313000, 0.0037681000, 0.0103733000, 0.0163690000, 0.0063494000, -0.051824000, -0.230319800", \ - "0.0001073000, 0.0037422000, 0.0103169000, 0.0162458000, 0.0061328000, -0.052062000, -0.230538600", \ - "9.250000e-05, 0.0037753000, 0.0104280000, 0.0164036000, 0.0062945000, -0.051784300, -0.230219700"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1812840000; - max_transition : 1.5033780000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.3247635000, 0.3346597000, 0.3553386000, 0.3950618000, 0.4686480000, 0.6274670000, 1.0327250000", \ - "0.3296543000, 0.3395421000, 0.3601436000, 0.3998749000, 0.4735487000, 0.6322570000, 1.0377993000", \ - "0.3405129000, 0.3504010000, 0.3709897000, 0.4107573000, 0.4843568000, 0.6431345000, 1.0487387000", \ - "0.3648889000, 0.3747771000, 0.3953667000, 0.4351229000, 0.5087202000, 0.6675103000, 1.0730112000", \ - "0.4027206000, 0.4126031000, 0.4332833000, 0.4730101000, 0.5466034000, 0.7053931000, 1.1109798000", \ - "0.4522781000, 0.4621833000, 0.4827536000, 0.5225048000, 0.5959901000, 0.7548974000, 1.1602626000", \ - "0.5027690000, 0.5127047000, 0.5332946000, 0.5730754000, 0.6466868000, 0.8054827000, 1.2108012000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.2834343000, 0.2928033000, 0.3128607000, 0.3554859000, 0.4520326000, 0.6948017000, 1.3412207000", \ - "0.2880410000, 0.2973637000, 0.3174691000, 0.3600849000, 0.4566289000, 0.6993550000, 1.3451702000", \ - "0.2987139000, 0.3080604000, 0.3281816000, 0.3707469000, 0.4672910000, 0.7103235000, 1.3561906000", \ - "0.3227867000, 0.3321267000, 0.3522719000, 0.3948472000, 0.4913957000, 0.7344733000, 1.3802458000", \ - "0.3620904000, 0.3714266000, 0.3915640000, 0.4341265000, 0.5306658000, 0.7737498000, 1.4194504000", \ - "0.4144469000, 0.4238044000, 0.4439096000, 0.4865012000, 0.5830665000, 0.8264605000, 1.4730140000", \ - "0.4730137000, 0.4823975000, 0.5025040000, 0.5451640000, 0.6417502000, 0.8842382000, 1.5289032000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0356090000, 0.0419623000, 0.0565913000, 0.0866655000, 0.1540417000, 0.3400220000, 0.8771956000", \ - "0.0353706000, 0.0421867000, 0.0566559000, 0.0867480000, 0.1542202000, 0.3402868000, 0.8743807000", \ - "0.0353408000, 0.0419630000, 0.0566246000, 0.0866442000, 0.1532010000, 0.3400186000, 0.8798076000", \ - "0.0353404000, 0.0419540000, 0.0566759000, 0.0865957000, 0.1536118000, 0.3405697000, 0.8746692000", \ - "0.0354308000, 0.0419351000, 0.0565980000, 0.0867078000, 0.1539699000, 0.3401296000, 0.8794770000", \ - "0.0353143000, 0.0420099000, 0.0564985000, 0.0861886000, 0.1539382000, 0.3406732000, 0.8737516000", \ - "0.0353578000, 0.0424790000, 0.0566190000, 0.0866560000, 0.1541012000, 0.3405857000, 0.8736518000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0320810000, 0.0396026000, 0.0577491000, 0.1039555000, 0.2267948000, 0.5697173000, 1.5031376000", \ - "0.0321952000, 0.0394641000, 0.0574604000, 0.1039908000, 0.2269644000, 0.5697581000, 1.5033781000", \ - "0.0320669000, 0.0395818000, 0.0576375000, 0.1039320000, 0.2266885000, 0.5699550000, 1.5021887000", \ - "0.0320738000, 0.0395198000, 0.0576106000, 0.1039083000, 0.2267039000, 0.5700315000, 1.5021379000", \ - "0.0321412000, 0.0396033000, 0.0576008000, 0.1039060000, 0.2267141000, 0.5700425000, 1.5020881000", \ - "0.0323164000, 0.0395063000, 0.0576697000, 0.1039252000, 0.2267079000, 0.5697432000, 1.4999034000", \ - "0.0321471000, 0.0396824000, 0.0576157000, 0.1040607000, 0.2267508000, 0.5702507000, 1.4965584000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.1992423000, 0.2099929000, 0.2325602000, 0.2769413000, 0.3500325000, 0.5041134000, 0.9098806000", \ - "0.2041813000, 0.2149500000, 0.2375298000, 0.2819667000, 0.3550463000, 0.5091046000, 0.9138524000", \ - "0.2167353000, 0.2275058000, 0.2501377000, 0.2945187000, 0.3676489000, 0.5217615000, 0.9266227000", \ - "0.2481861000, 0.2589453000, 0.2815536000, 0.3259103000, 0.3990704000, 0.5531584000, 0.9578822000", \ - "0.3238136000, 0.3345415000, 0.3570412000, 0.4013490000, 0.4744182000, 0.6285642000, 1.0334114000", \ - "0.4924262000, 0.5041448000, 0.5283617000, 0.5741538000, 0.6471451000, 0.8012403000, 1.2055635000", \ - "0.7785891000, 0.7940782000, 0.8262703000, 0.8855346000, 0.9633027000, 1.1179427000, 1.5230158000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013351700, 0.0035653300, 0.0095206200, 0.0254232000, 0.0678883000, 0.1812840000"); - values("0.0389770000, 0.0465243000, 0.0633553000, 0.0935468000, 0.1503293000, 0.3339339000, 0.8770263000", \ - "0.0391456000, 0.0468416000, 0.0632810000, 0.0935501000, 0.1507283000, 0.3340275000, 0.8713182000", \ - "0.0389479000, 0.0463595000, 0.0633989000, 0.0935889000, 0.1507556000, 0.3337886000, 0.8721172000", \ - "0.0388685000, 0.0463813000, 0.0631595000, 0.0936418000, 0.1507540000, 0.3339836000, 0.8810019000", \ - "0.0393047000, 0.0468083000, 0.0633109000, 0.0936302000, 0.1507656000, 0.3338638000, 0.8764089000", \ - "0.0457433000, 0.0529116000, 0.0693368000, 0.0972076000, 0.1511646000, 0.3341070000, 0.8696741000", \ - "0.0675278000, 0.0775030000, 0.0983968000, 0.1224456000, 0.1608884000, 0.3357057000, 0.8781891000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("-0.005732400, -0.001287800, 0.0065548000, 0.0147053000, 0.0109513000, -0.028338700, -0.149798400", \ - "-0.005683200, -0.001245800, 0.0065543000, 0.0146688000, 0.0108572000, -0.028427300, -0.149901300", \ - "-0.005562200, -0.001143400, 0.0066211000, 0.0146818000, 0.0108194000, -0.028523800, -0.150046100", \ - "-0.005630800, -0.001261500, 0.0063983000, 0.0143289000, 0.0103296000, -0.029105100, -0.150653500", \ - "-0.005728300, -0.001380000, 0.0062402000, 0.0141122000, 0.0100552000, -0.029420300, -0.150987000", \ - "-0.005907900, -0.001550500, 0.0061066000, 0.0140256000, 0.0100419000, -0.029383100, -0.150924800", \ - "-0.006220000, -0.001702100, 0.0062841000, 0.0146498000, 0.0109254000, -0.028423000, -0.149841000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("-0.007105000, -0.004143000, 0.0023762000, 0.0154409000, 0.0403553000, 0.0934007000, 0.2210922000", \ - "-0.007060300, -0.004119400, 0.0023672000, 0.0153423000, 0.0401796000, 0.0934812000, 0.2218000000", \ - "-0.006941700, -0.004024900, 0.0024169000, 0.0153215000, 0.0400454000, 0.0929955000, 0.2215633000", \ - "-0.007000600, -0.004115000, 0.0022549000, 0.0151015000, 0.0397356000, 0.0930065000, 0.2215825000", \ - "-0.007100900, -0.004234700, 0.0020949000, 0.0148959000, 0.0393999000, 0.0928458000, 0.2208835000", \ - "-0.007253600, -0.004347900, 0.0020608000, 0.0149846000, 0.0396573000, 0.0929235000, 0.2202589000", \ - "-0.007535300, -0.004422900, 0.0023110000, 0.0154936000, 0.0403491000, 0.0937060000, 0.2209957000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("-0.000953500, 0.0011794000, 0.0060973000, 0.0167166000, 0.0391598000, 0.0907596000, 0.2174380000", \ - "-0.000966700, 0.0011573000, 0.0060486000, 0.0166096000, 0.0391093000, 0.0906142000, 0.2183125000", \ - "-0.000975300, 0.0011475000, 0.0060345000, 0.0166195000, 0.0389986000, 0.0910791000, 0.2171833000", \ - "-0.000993100, 0.0011142000, 0.0059676000, 0.0165011000, 0.0388450000, 0.0908428000, 0.2181205000", \ - "-0.001018600, 0.0010689000, 0.0058726000, 0.0163613000, 0.0386609000, 0.0902431000, 0.2168188000", \ - "-0.001053400, 0.0010213000, 0.0057925000, 0.0162352000, 0.0384593000, 0.0903801000, 0.2174235000", \ - "-0.001066100, 0.0010684000, 0.0059238000, 0.0163186000, 0.0389487000, 0.0907335000, 0.2176849000"); - } - } - max_capacitance : 0.1300150000; - max_transition : 1.5032920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.3357136000, 0.3411624000, 0.3524427000, 0.3758404000, 0.4284862000, 0.5589084000, 0.8875734000", \ - "0.3402794000, 0.3457671000, 0.3570118000, 0.3803897000, 0.4329640000, 0.5633627000, 0.8933721000", \ - "0.3510029000, 0.3564810000, 0.3677282000, 0.3910602000, 0.4438370000, 0.5741752000, 0.9029254000", \ - "0.3750683000, 0.3805358000, 0.3917891000, 0.4151253000, 0.4679015000, 0.5982180000, 0.9281597000", \ - "0.4143761000, 0.4198440000, 0.4310964000, 0.4544330000, 0.5072062000, 0.6375073000, 0.9674248000", \ - "0.4667771000, 0.4722217000, 0.4835038000, 0.5068402000, 0.5596209000, 0.6900395000, 1.0198612000", \ - "0.5253097000, 0.5307555000, 0.5420465000, 0.5654232000, 0.6180723000, 0.7483825000, 1.0773369000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.3767716000, 0.3838780000, 0.4000796000, 0.4392662000, 0.5363630000, 0.7806772000, 1.4003133000", \ - "0.3815299000, 0.3887075000, 0.4049684000, 0.4438045000, 0.5412382000, 0.7859526000, 1.4051582000", \ - "0.3926584000, 0.3997768000, 0.4160679000, 0.4548903000, 0.5522590000, 0.7970272000, 1.4172097000", \ - "0.4163598000, 0.4234698000, 0.4397902000, 0.4787930000, 0.5763196000, 0.8209657000, 1.4377263000", \ - "0.4546322000, 0.4617545000, 0.4780599000, 0.5170510000, 0.6146189000, 0.8588717000, 1.4797147000", \ - "0.5041570000, 0.5112016000, 0.5273431000, 0.5665402000, 0.6638627000, 0.9084910000, 1.5279910000", \ - "0.5547893000, 0.5619284000, 0.5781061000, 0.6170442000, 0.7143993000, 0.9587374000, 1.5771547000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0169376000, 0.0215055000, 0.0316348000, 0.0568781000, 0.1226368000, 0.2957257000, 0.7377707000", \ - "0.0170292000, 0.0214480000, 0.0317612000, 0.0568627000, 0.1228349000, 0.2951767000, 0.7374035000", \ - "0.0171639000, 0.0214318000, 0.0316541000, 0.0569451000, 0.1228840000, 0.2962631000, 0.7377453000", \ - "0.0171467000, 0.0214445000, 0.0316563000, 0.0569541000, 0.1228552000, 0.2957871000, 0.7401916000", \ - "0.0171582000, 0.0214447000, 0.0316574000, 0.0569665000, 0.1228207000, 0.2957574000, 0.7402158000", \ - "0.0170380000, 0.0214673000, 0.0314502000, 0.0568326000, 0.1227931000, 0.2959806000, 0.7379357000", \ - "0.0169724000, 0.0215192000, 0.0315192000, 0.0569104000, 0.1227524000, 0.2964277000, 0.7309376000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0232177000, 0.0308848000, 0.0516166000, 0.1059431000, 0.2456861000, 0.5989281000, 1.4978651000", \ - "0.0231710000, 0.0308749000, 0.0516179000, 0.1059644000, 0.2457098000, 0.5995721000, 1.4990906000", \ - "0.0232290000, 0.0308938000, 0.0516106000, 0.1059459000, 0.2455049000, 0.5997938000, 1.4968463000", \ - "0.0232896000, 0.0310168000, 0.0514842000, 0.1059035000, 0.2452792000, 0.5992775000, 1.5032923000", \ - "0.0232816000, 0.0310267000, 0.0515154000, 0.1058394000, 0.2454805000, 0.5991403000, 1.4970353000", \ - "0.0231889000, 0.0309199000, 0.0515303000, 0.1059472000, 0.2456894000, 0.5985384000, 1.4969160000", \ - "0.0231826000, 0.0309442000, 0.0516082000, 0.1061753000, 0.2452863000, 0.5980715000, 1.4961814000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.2535619000, 0.2607549000, 0.2771595000, 0.3161478000, 0.4135647000, 0.6592561000, 1.2763054000", \ - "0.2585393000, 0.2658171000, 0.2821395000, 0.3211605000, 0.4186735000, 0.6634487000, 1.2839046000", \ - "0.2710702000, 0.2783357000, 0.2947415000, 0.3340100000, 0.4313965000, 0.6763397000, 1.2941008000", \ - "0.3023334000, 0.3096258000, 0.3260350000, 0.3652685000, 0.4627341000, 0.7077363000, 1.3270588000", \ - "0.3780065000, 0.3852462000, 0.4014474000, 0.4408659000, 0.5383523000, 0.7828642000, 1.4012161000", \ - "0.5487085000, 0.5560692000, 0.5723484000, 0.6118221000, 0.7093036000, 0.9542852000, 1.5731013000", \ - "0.8446698000, 0.8526219000, 0.8697563000, 0.9089173000, 1.0064999000, 1.2509190000, 1.8710113000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0241253000, 0.0316418000, 0.0520958000, 0.1062601000, 0.2461305000, 0.5997061000, 1.4972008000", \ - "0.0240383000, 0.0316472000, 0.0519641000, 0.1062341000, 0.2457393000, 0.5999607000, 1.4984973000", \ - "0.0241805000, 0.0317253000, 0.0520684000, 0.1062105000, 0.2455093000, 0.5989486000, 1.4921570000", \ - "0.0241591000, 0.0317152000, 0.0520887000, 0.1062806000, 0.2453361000, 0.5990214000, 1.4977904000", \ - "0.0240354000, 0.0316034000, 0.0520411000, 0.1063251000, 0.2453279000, 0.5999958000, 1.4972248000", \ - "0.0247447000, 0.0322457000, 0.0524711000, 0.1064221000, 0.2454138000, 0.5985037000, 1.4967257000", \ - "0.0294526000, 0.0366827000, 0.0549218000, 0.1076049000, 0.2460239000, 0.5982217000, 1.4983382000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0035110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048847000, 0.0048906000, 0.0049042000, 0.0049142000, 0.0049371000, 0.0049899000, 0.0051116000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005473700, -0.005522100, -0.005633800, -0.005635100, -0.005638100, -0.005645000, -0.005660900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035410000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.203078100, -0.063315800, 0.2532533000", \ - "-0.326971400, -0.195753900, 0.0964010000", \ - "-0.407944700, -0.284051400, -0.010207000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4164368000, 0.6845847000", \ - "0.3883444000, 0.5244610000, 0.7865052000", \ - "0.4632142000, 0.5956686000, 0.8491679000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2323997000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030995000, 0.0031032000, 0.0031117000, 0.0031194000, 0.0031375000, 0.0031792000, 0.0032752000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003017000, -0.003021100, -0.003030700, -0.003038600, -0.003056500, -0.003097900, -0.003193300"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019630000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3950664000, 0.5690084000, 0.8831361000", \ - "0.3004701000, 0.4744121000, 0.7897604000", \ - "0.2548971000, 0.4300599000, 0.7466289000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2473613000, 0.3590475000, 0.4961732000", \ - "0.1893861000, 0.2998515000, 0.4333151000", \ - "0.2024069000, 0.3128724000, 0.4463359000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.245802700, -0.418524100, -0.694809900", \ - "-0.193931000, -0.367873000, -0.661248700", \ - "-0.167889300, -0.341831400, -0.644972600"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.182326200, -0.289129600, -0.406724000", \ - "-0.157309900, -0.264113300, -0.386590500", \ - "-0.180096400, -0.288120500, -0.414259800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127120000, 0.0125639000, 0.0122225000, 0.0122742000, 0.0123937000, 0.0126690000, 0.0133036000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000299800, -0.000379100, -0.000561800, -0.000543600, -0.000501600, -0.000404600, -0.000181100"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0039730000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3328105000, 0.5030905000, 0.8123353000", \ - "0.2382142000, 0.4072734000, 0.7189597000", \ - "0.1901999000, 0.3604798000, 0.6746074000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3694316000, 0.4737936000, 0.5279115000", \ - "0.2748353000, 0.3791973000, 0.4333151000", \ - "0.2292624000, 0.3336243000, 0.3877422000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.215285200, -0.383123700, -0.660630200", \ - "-0.145102900, -0.315382800, -0.608758400", \ - "-0.109295600, -0.277134100, -0.579054700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.233595700, -0.346502600, -0.407944700", \ - "-0.171958300, -0.281203100, -0.341424500", \ - "-0.138592500, -0.247837200, -0.306837900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrbp_2") { - leakage_power () { - value : 0.0112628000; - when : "!RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0110260000; - when : "!RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116185000; - when : "!RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0113677000; - when : "!RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0127964000; - when : "RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0120789000; - when : "RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119826000; - when : "RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0115382000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0110860000; - when : "!RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0124593000; - when : "RESET_B&CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0129232000; - when : "RESET_B&CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0114321000; - when : "RESET_B&CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0113060000; - when : "RESET_B&!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0120332000; - when : "!RESET_B&CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0123131000; - when : "RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0118492000; - when : "RESET_B&CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0130600000; - when : "RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0117678000; - when : "RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0113156000; - when : "!RESET_B&CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0129013000; - when : "RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0120021000; - when : "RESET_B&!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0115499000; - when : "!RESET_B&CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0125596000; - when : "RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116715000; - when : "RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0112193000; - when : "!RESET_B&CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0125926000; - when : "RESET_B&CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0117738000; - when : "RESET_B&CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0116688000; - when : "RESET_B&CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0110692000; - when : "RESET_B&!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0117964000; - when : "!RESET_B&CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0126889000; - when : "RESET_B&CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0115696000; - when : "RESET_B&!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0122968000; - when : "!RESET_B&CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119325000; - when : "RESET_B&CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0114109000; - when : "RESET_B&!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0121381000; - when : "!RESET_B&CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0114035000; - when : "RESET_B&!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0111546000; - when : "!RESET_B&!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0133207000; - when : "RESET_B&!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0132244000; - when : "RESET_B&!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0130910000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0111668000; - when : "RESET_B&!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116672000; - when : "RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0112880000; - when : "!RESET_B&!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0113843000; - when : "!RESET_B&!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0135549000; - when : "RESET_B&!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0115085000; - when : "RESET_B&!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0115265000; - when : "!RESET_B&!CLK&!D&SCD&SCE&!Q&Q_N"; - } - area : 36.284800000; - cell_footprint : "sky130_fd_sc_hd__sdfrbp"; - cell_leakage_power : 0.0119239200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0024460000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023130000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0296260000, 0.0294477000, 0.0290368000, 0.0291640000, 0.0294572000, 0.0301332000, 0.0316914000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184360000, 0.0183173000, 0.0180437000, 0.0181137000, 0.0182749000, 0.0186468000, 0.0195041000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025790000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2675521000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1653906000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079877000, 0.0079014000, 0.0077025000, 0.0077443000, 0.0078406000, 0.0080627000, 0.0085746000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022781000, 0.0022482000, 0.0021791000, 0.0021876000, 0.0022071000, 0.0022523000, 0.0023565000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2998515000, 0.4982077000, 0.8513978000", \ - "0.2040345000, 0.4036113000, 0.7568014000", \ - "0.1572409000, 0.3580384000, 0.7100078000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1228496000, 0.2613913000, 0.3838685000", \ - "0.0721986000, 0.2021953000, 0.3112448000", \ - "0.0803366000, 0.2066712000, 0.3083965000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.177443400, -0.374578800, -0.674057900", \ - "-0.109702500, -0.308058600, -0.635613900", \ - "-0.073895200, -0.274692700, -0.607130900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.084669900, -0.215887400, -0.306626300", \ - "-0.048667300, -0.175002000, -0.273065100", \ - "-0.062908900, -0.186802100, -0.284865200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("-0.005922900, -0.000754000, 0.0095919000, 0.0208979000, 0.0108989000, -0.067779900, -0.326152900", \ - "-0.005865100, -0.000699300, 0.0096215000, 0.0208851000, 0.0108755000, -0.067831200, -0.326198400", \ - "-0.005740300, -0.000585400, 0.0097040000, 0.0208989000, 0.0107604000, -0.067914000, -0.326313400", \ - "-0.005803700, -0.000697900, 0.0094944000, 0.0205835000, 0.0104019000, -0.068478500, -0.326920700", \ - "-0.005893700, -0.000806100, 0.0093381000, 0.0203834000, 0.0101119000, -0.068753500, -0.327212600", \ - "-0.006063400, -0.000939700, 0.0092762000, 0.0203379000, 0.0101905000, -0.068608300, -0.327007700", \ - "-0.006396700, -0.001121300, 0.0094457000, 0.0211191000, 0.0115537000, -0.067437200, -0.325833600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("-0.007506700, -0.004569400, 0.0027908000, 0.0199497000, 0.0585935000, 0.1548808000, 0.4195573000", \ - "-0.007452700, -0.004525700, 0.0028140000, 0.0199379000, 0.0585375000, 0.1548240000, 0.4192092000", \ - "-0.007328300, -0.004422900, 0.0028757000, 0.0199385000, 0.0584950000, 0.1547083000, 0.4179681000", \ - "-0.007389400, -0.004518900, 0.0026832000, 0.0195989000, 0.0579819000, 0.1545539000, 0.4205179000", \ - "-0.007481800, -0.004646000, 0.0025217000, 0.0193729000, 0.0576860000, 0.1543651000, 0.4203345000", \ - "-0.007659400, -0.004802000, 0.0023879000, 0.0192716000, 0.0576451000, 0.1536792000, 0.4179634000", \ - "-0.007954500, -0.004880700, 0.0027469000, 0.0201023000, 0.0586307000, 0.1554209000, 0.4190775000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014120050, 0.0039875180, 0.0112607900, 0.0318006100, 0.0898052500, 0.2536110000"); - values("0.0004208000, 0.0048468000, 0.0135354000, 0.0221891000, 0.0096569000, -0.070890500, -0.330025400", \ - "0.0004011000, 0.0048164000, 0.0134804000, 0.0221002000, 0.0095387000, -0.071005800, -0.330181500", \ - "0.0003707000, 0.0047780000, 0.0134040000, 0.0219906000, 0.0093761000, -0.071181700, -0.330383200", \ - "0.0003658000, 0.0047691000, 0.0133985000, 0.0219781000, 0.0093681000, -0.071215300, -0.330379200", \ - "0.0003450000, 0.0047316000, 0.0133303000, 0.0218318000, 0.0091405000, -0.071460700, -0.330599100", \ - "0.0003182000, 0.0047021000, 0.0132497000, 0.0216230000, 0.0087761000, -0.071833400, -0.330938200", \ - "0.0003093000, 0.0047595000, 0.0134024000, 0.0218073000, 0.0088126000, -0.071784100, -0.330864900"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.2536110000; - max_transition : 1.5045920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.3400962000, 0.3475719000, 0.3640697000, 0.3960690000, 0.4560360000, 0.5753665000, 0.8542911000", \ - "0.3448621000, 0.3524023000, 0.3688661000, 0.4008716000, 0.4607964000, 0.5801371000, 0.8593448000", \ - "0.3557233000, 0.3632575000, 0.3797169000, 0.4117113000, 0.4716997000, 0.5910194000, 0.8698315000", \ - "0.3800900000, 0.3876302000, 0.4041139000, 0.4360673000, 0.4960281000, 0.6153860000, 0.8945770000", \ - "0.4179967000, 0.4255043000, 0.4420107000, 0.4739594000, 0.5339582000, 0.6532941000, 0.9322645000", \ - "0.4675161000, 0.4750563000, 0.4915280000, 0.5234275000, 0.5834247000, 0.7028012000, 0.9817737000", \ - "0.5180195000, 0.5255793000, 0.5420641000, 0.5740474000, 0.6340567000, 0.7533458000, 1.0322028000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.3076934000, 0.3160095000, 0.3348699000, 0.3755748000, 0.4699391000, 0.7091687000, 1.3717051000", \ - "0.3121735000, 0.3205317000, 0.3393928000, 0.3800857000, 0.4744143000, 0.7136881000, 1.3727074000", \ - "0.3230021000, 0.3313086000, 0.3501279000, 0.3908871000, 0.4852302000, 0.7244981000, 1.3823691000", \ - "0.3470861000, 0.3553613000, 0.3742235000, 0.4149982000, 0.5092545000, 0.7485434000, 1.4054826000", \ - "0.3863576000, 0.3946519000, 0.4135233000, 0.4543171000, 0.5485881000, 0.7878825000, 1.4463747000", \ - "0.4387684000, 0.4470821000, 0.4659326000, 0.5067087000, 0.6010420000, 0.8402055000, 1.4980495000", \ - "0.4974182000, 0.5057323000, 0.5245896000, 0.5653466000, 0.6596786000, 0.8989419000, 1.5580588000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0348595000, 0.0395518000, 0.0499555000, 0.0714031000, 0.1200657000, 0.2375627000, 0.5863237000", \ - "0.0348392000, 0.0395047000, 0.0497267000, 0.0715324000, 0.1201809000, 0.2374637000, 0.5859071000", \ - "0.0348718000, 0.0393678000, 0.0499339000, 0.0714047000, 0.1200593000, 0.2379374000, 0.5858260000", \ - "0.0348274000, 0.0393826000, 0.0498623000, 0.0712843000, 0.1202686000, 0.2379029000, 0.5863389000", \ - "0.0349413000, 0.0394826000, 0.0497692000, 0.0713709000, 0.1198997000, 0.2375426000, 0.5860613000", \ - "0.0348569000, 0.0395254000, 0.0497028000, 0.0712371000, 0.1201700000, 0.2374972000, 0.5844891000", \ - "0.0347754000, 0.0396283000, 0.0499933000, 0.0712375000, 0.1199688000, 0.2381431000, 0.5843192000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0340788000, 0.0405526000, 0.0568873000, 0.0992333000, 0.2158875000, 0.5453982000, 1.5002067000", \ - "0.0341304000, 0.0406651000, 0.0569616000, 0.0992295000, 0.2159466000, 0.5446815000, 1.5013667000", \ - "0.0339483000, 0.0404879000, 0.0568040000, 0.0992010000, 0.2158453000, 0.5456227000, 1.5013831000", \ - "0.0341995000, 0.0405685000, 0.0569420000, 0.0991933000, 0.2161465000, 0.5448100000, 1.5045925000", \ - "0.0339860000, 0.0406103000, 0.0569635000, 0.0991861000, 0.2159351000, 0.5441776000, 1.5019875000", \ - "0.0340304000, 0.0405570000, 0.0568365000, 0.0991926000, 0.2161515000, 0.5456363000, 1.5016363000", \ - "0.0339796000, 0.0406541000, 0.0569386000, 0.0992474000, 0.2163883000, 0.5450967000, 1.5005092000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.2147194000, 0.2227290000, 0.2405308000, 0.2752366000, 0.3399434000, 0.4523134000, 0.7256302000", \ - "0.2198128000, 0.2278578000, 0.2456506000, 0.2803751000, 0.3451008000, 0.4574502000, 0.7308252000", \ - "0.2325432000, 0.2405212000, 0.2584078000, 0.2931751000, 0.3578509000, 0.4702198000, 0.7436344000", \ - "0.2640055000, 0.2719806000, 0.2898546000, 0.3246144000, 0.3892723000, 0.5016788000, 0.7749011000", \ - "0.3392953000, 0.3473273000, 0.3650056000, 0.3997807000, 0.4643685000, 0.5768153000, 0.8502047000", \ - "0.5114055000, 0.5200257000, 0.5385502000, 0.5739509000, 0.6391849000, 0.7516354000, 1.0250502000", \ - "0.8094232000, 0.8207419000, 0.8454814000, 0.8926686000, 0.9725591000, 1.0883295000, 1.3617066000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014120100, 0.0039875200, 0.0112608000, 0.0318006000, 0.0898053000, 0.2536110000"); - values("0.0379298000, 0.0430335000, 0.0550886000, 0.0789501000, 0.1232716000, 0.2262723000, 0.5782439000", \ - "0.0379529000, 0.0434448000, 0.0549545000, 0.0790001000, 0.1232180000, 0.2267765000, 0.5783118000", \ - "0.0382517000, 0.0431077000, 0.0546906000, 0.0792233000, 0.1234140000, 0.2263408000, 0.5782740000", \ - "0.0382590000, 0.0430863000, 0.0547029000, 0.0792108000, 0.1234485000, 0.2268128000, 0.5788010000", \ - "0.0382474000, 0.0430082000, 0.0543348000, 0.0792802000, 0.1233804000, 0.2265109000, 0.5783506000", \ - "0.0434257000, 0.0480474000, 0.0587689000, 0.0819855000, 0.1244293000, 0.2269264000, 0.5770874000", \ - "0.0655099000, 0.0717832000, 0.0855329000, 0.1132374000, 0.1476038000, 0.2329703000, 0.5797786000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.006152400, -0.001152000, 0.0090360000, 0.0199687000, 0.0071583000, -0.083647300, -0.382301600", \ - "-0.006100500, -0.001112500, 0.0090619000, 0.0199696000, 0.0071143000, -0.083717800, -0.382349000", \ - "-0.005975600, -0.001001600, 0.0091253000, 0.0199768000, 0.0070133000, -0.083847700, -0.382494800", \ - "-0.006036700, -0.001106200, 0.0089383000, 0.0196349000, 0.0065364000, -0.084353900, -0.383055000", \ - "-0.006129400, -0.001219200, 0.0087761000, 0.0194071000, 0.0062363000, -0.084727100, -0.383432200", \ - "-0.006303400, -0.001378100, 0.0086333000, 0.0193051000, 0.0061848000, -0.084818400, -0.383574700", \ - "-0.006638500, -0.001548700, 0.0088296000, 0.0200994000, 0.0074848000, -0.083622700, -0.382215600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.007617800, -0.004743300, 0.0028035000, 0.0208457000, 0.0624998000, 0.1696020000, 0.4748360000", \ - "-0.007567600, -0.004709800, 0.0027954000, 0.0207502000, 0.0623426000, 0.1702796000, 0.4725911000", \ - "-0.007443600, -0.004605400, 0.0028525000, 0.0207316000, 0.0622337000, 0.1693248000, 0.4723420000", \ - "-0.007495300, -0.004678700, 0.0027201000, 0.0205758000, 0.0619287000, 0.1698891000, 0.4720914000", \ - "-0.007586700, -0.004791600, 0.0025697000, 0.0203518000, 0.0616906000, 0.1688688000, 0.4740567000", \ - "-0.007748700, -0.004916900, 0.0025348000, 0.0204384000, 0.0619030000, 0.1695265000, 0.4718782000", \ - "-0.008030400, -0.004966700, 0.0028831000, 0.0211440000, 0.0627105000, 0.1701061000, 0.4727615000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "RESET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014425840, 0.0041620980, 0.0120083500, 0.0346461100, 0.0999598700, 0.2884010000"); - values("-0.001234900, 0.0009410000, 0.0069027000, 0.0221979000, 0.0609832000, 0.1671982000, 0.4708897000", \ - "-0.001252000, 0.0009136000, 0.0068504000, 0.0221313000, 0.0609382000, 0.1666785000, 0.4687152000", \ - "-0.001274700, 0.0008898000, 0.0068352000, 0.0221121000, 0.0608780000, 0.1665013000, 0.4687405000", \ - "-0.001286600, 0.0008636000, 0.0067757000, 0.0220018000, 0.0607348000, 0.1664595000, 0.4702777000", \ - "-0.001309200, 0.0008247000, 0.0066892000, 0.0218307000, 0.0604684000, 0.1661166000, 0.4681915000", \ - "-0.001349000, 0.0007640000, 0.0065803000, 0.0216648000, 0.0602610000, 0.1658625000, 0.4699680000", \ - "-0.001369000, 0.0007910000, 0.0065815000, 0.0217721000, 0.0606851000, 0.1661425000, 0.4686769000"); - } - } - max_capacitance : 0.2884010000; - max_transition : 1.4944960000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4229061000, 0.4279972000, 0.4392569000, 0.4617561000, 0.5076295000, 0.6157671000, 0.9156935000", \ - "0.4273402000, 0.4324360000, 0.4436864000, 0.4662504000, 0.5120995000, 0.6202954000, 0.9198933000", \ - "0.4381102000, 0.4432005000, 0.4545439000, 0.4771457000, 0.5230361000, 0.6311043000, 0.9299752000", \ - "0.4621777000, 0.4672719000, 0.4784887000, 0.5011155000, 0.5470319000, 0.6551443000, 0.9542487000", \ - "0.5014957000, 0.5065895000, 0.5178063000, 0.5404330000, 0.5863482000, 0.6944615000, 0.9934495000", \ - "0.5538905000, 0.5589675000, 0.5702832000, 0.5928071000, 0.6386003000, 0.7468050000, 1.0458653000", \ - "0.6125378000, 0.6176170000, 0.6288476000, 0.6513594000, 0.6973193000, 0.8055348000, 1.1055460000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.4727562000, 0.4790496000, 0.4931250000, 0.5247930000, 0.6069998000, 0.8407746000, 1.5176164000", \ - "0.4777650000, 0.4837029000, 0.4977988000, 0.5295807000, 0.6118762000, 0.8451247000, 1.5207204000", \ - "0.4888607000, 0.4948817000, 0.5088607000, 0.5406469000, 0.6229692000, 0.8562873000, 1.5319027000", \ - "0.5127426000, 0.5188588000, 0.5329356000, 0.5648069000, 0.6470824000, 0.8804124000, 1.5560194000", \ - "0.5507856000, 0.5569626000, 0.5709687000, 0.6027160000, 0.6847966000, 0.9182241000, 1.5932653000", \ - "0.6003702000, 0.6065425000, 0.6205457000, 0.6523907000, 0.7345834000, 0.9681950000, 1.6449198000", \ - "0.6510683000, 0.6571293000, 0.6712602000, 0.7030641000, 0.7852937000, 1.0190307000, 1.6974816000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0239057000, 0.0270832000, 0.0343668000, 0.0519790000, 0.0956003000, 0.2247273000, 0.6186809000", \ - "0.0238614000, 0.0269939000, 0.0347662000, 0.0518071000, 0.0957334000, 0.2254249000, 0.6222011000", \ - "0.0239567000, 0.0272206000, 0.0344245000, 0.0517417000, 0.0953560000, 0.2247763000, 0.6196633000", \ - "0.0239830000, 0.0272984000, 0.0345838000, 0.0517495000, 0.0957259000, 0.2248922000, 0.6218331000", \ - "0.0239783000, 0.0272930000, 0.0345668000, 0.0517549000, 0.0957278000, 0.2245089000, 0.6222513000", \ - "0.0239224000, 0.0270287000, 0.0349170000, 0.0517578000, 0.0956666000, 0.2256020000, 0.6226634000", \ - "0.0238377000, 0.0272473000, 0.0345528000, 0.0515098000, 0.0954400000, 0.2249756000, 0.6160502000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0267074000, 0.0311212000, 0.0433658000, 0.0796055000, 0.1918322000, 0.5237049000, 1.4941302000", \ - "0.0266957000, 0.0311926000, 0.0434638000, 0.0794368000, 0.1914147000, 0.5249191000, 1.4934581000", \ - "0.0266566000, 0.0314829000, 0.0434167000, 0.0794338000, 0.1916419000, 0.5248146000, 1.4925052000", \ - "0.0265613000, 0.0313908000, 0.0433217000, 0.0792796000, 0.1915809000, 0.5249190000, 1.4934369000", \ - "0.0266911000, 0.0311229000, 0.0434542000, 0.0793184000, 0.1916583000, 0.5239502000, 1.4941562000", \ - "0.0269340000, 0.0313399000, 0.0432472000, 0.0793012000, 0.1917475000, 0.5238466000, 1.4870287000", \ - "0.0265606000, 0.0313599000, 0.0433732000, 0.0792048000, 0.1918141000, 0.5234167000, 1.4932432000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.3577160000, 0.3639941000, 0.3780027000, 0.4096614000, 0.4916778000, 0.7255223000, 1.4023892000", \ - "0.3629306000, 0.3690135000, 0.3830177000, 0.4147711000, 0.4969503000, 0.7311660000, 1.4051530000", \ - "0.3756342000, 0.3818894000, 0.3958772000, 0.4275015000, 0.5095532000, 0.7431016000, 1.4182424000", \ - "0.4068579000, 0.4131066000, 0.4271199000, 0.4587817000, 0.5409933000, 0.7739970000, 1.4520037000", \ - "0.4820635000, 0.4883325000, 0.5023481000, 0.5339028000, 0.6158971000, 0.8496761000, 1.5244512000", \ - "0.6573434000, 0.6634326000, 0.6774361000, 0.7091225000, 0.7913393000, 1.0244805000, 1.7024068000", \ - "0.9943820000, 1.0010477000, 1.0155825000, 1.0476194000, 1.1299680000, 1.3634202000, 2.0384885000"); - } - related_pin : "RESET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014425800, 0.0041621000, 0.0120084000, 0.0346461000, 0.0999599000, 0.2884010000"); - values("0.0271116000, 0.0314989000, 0.0433659000, 0.0791094000, 0.1911642000, 0.5243217000, 1.4914519000", \ - "0.0273916000, 0.0315692000, 0.0434697000, 0.0792683000, 0.1911447000, 0.5251770000, 1.4935888000", \ - "0.0273003000, 0.0315334000, 0.0434511000, 0.0792046000, 0.1913817000, 0.5245531000, 1.4922683000", \ - "0.0272883000, 0.0315686000, 0.0434262000, 0.0790810000, 0.1911255000, 0.5253301000, 1.4937277000", \ - "0.0271977000, 0.0316530000, 0.0434221000, 0.0790200000, 0.1912865000, 0.5239674000, 1.4942797000", \ - "0.0274154000, 0.0315864000, 0.0434732000, 0.0789889000, 0.1912895000, 0.5253717000, 1.4939419000", \ - "0.0302264000, 0.0345894000, 0.0459600000, 0.0803274000, 0.1913453000, 0.5250091000, 1.4944960000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("RESET_B") { - capacitance : 0.0035140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048338000, 0.0048542000, 0.0049012000, 0.0049111000, 0.0049339000, 0.0049865000, 0.0051079000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005443100, -0.005426300, -0.005387500, -0.005402600, -0.005437600, -0.005517900, -0.005703100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035540000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.201857400, -0.053550100, 0.3106263000", \ - "-0.324529900, -0.184767600, 0.1501120000", \ - "-0.406724000, -0.274285800, 0.0422832000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2790996000, 0.4164368000, 0.6845847000", \ - "0.3883444000, 0.5244610000, 0.7865052000", \ - "0.4632142000, 0.5956686000, 0.8503887000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2686506000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030958000, 0.0031005000, 0.0031115000, 0.0031192000, 0.0031367000, 0.0031773000, 0.0032710000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003018400, -0.003022000, -0.003030400, -0.003040400, -0.003063400, -0.003116300, -0.003238100"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019630000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3975078000, 0.5714499000, 0.8843568000", \ - "0.3016907000, 0.4768535000, 0.7909811000", \ - "0.2573385000, 0.4325013000, 0.7490703000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2485820000, 0.3602682000, 0.4973939000", \ - "0.1906068000, 0.3010723000, 0.4345358000", \ - "0.2036276000, 0.3128724000, 0.4463359000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.243361300, -0.416082700, -0.691147800", \ - "-0.192710300, -0.366652300, -0.660028000", \ - "-0.166668600, -0.340610700, -0.643752000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.181105500, -0.286688200, -0.405503300", \ - "-0.156089200, -0.264113300, -0.385369800", \ - "-0.180096400, -0.288120500, -0.414259800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127074000, 0.0126157000, 0.0124044000, 0.0124479000, 0.0125480000, 0.0127791000, 0.0133117000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000298400, -0.000378500, -0.000563000, -0.000543800, -0.000499800, -0.000398100, -0.000163600"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0039720000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3352520000, 0.5043112000, 0.8147767000", \ - "0.2394349000, 0.4084941000, 0.7214010000", \ - "0.1926413000, 0.3629212000, 0.6758281000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3706523000, 0.4762350000, 0.5303529000", \ - "0.2760560000, 0.3804180000, 0.4345358000", \ - "0.2317038000, 0.3348451000, 0.3889629000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.212843800, -0.381903000, -0.658188800", \ - "-0.143882200, -0.312941400, -0.607537800", \ - "-0.108074900, -0.277134100, -0.579054700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.231154300, -0.344061200, -0.405503300", \ - "-0.170737600, -0.279982400, -0.340203800", \ - "-0.138592500, -0.247837200, -0.306837900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrtn_1") { - leakage_power () { - value : 0.0176056000; - when : "!RESET_B&CLK_N&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0097040000; - when : "RESET_B&CLK_N&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0177297000; - when : "RESET_B&CLK_N&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0177477000; - when : "!RESET_B&CLK_N&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0174841000; - when : "!RESET_B&CLK_N&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0172473000; - when : "!RESET_B&CLK_N&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0178398000; - when : "!RESET_B&CLK_N&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0175890000; - when : "!RESET_B&CLK_N&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0188549000; - when : "RESET_B&!CLK_N&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0181373000; - when : "RESET_B&!CLK_N&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0180410000; - when : "RESET_B&!CLK_N&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0177594000; - when : "RESET_B&CLK_N&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0171444000; - when : "!RESET_B&!CLK_N&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0084456000; - when : "RESET_B&!CLK_N&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0089095000; - when : "RESET_B&!CLK_N&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0074184000; - when : "RESET_B&!CLK_N&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0074556000; - when : "RESET_B&CLK_N&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0180916000; - when : "!RESET_B&!CLK_N&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0183716000; - when : "RESET_B&!CLK_N&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0179077000; - when : "RESET_B&!CLK_N&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0191185000; - when : "RESET_B&!CLK_N&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0179891000; - when : "RESET_B&CLK_N&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0173741000; - when : "!RESET_B&!CLK_N&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0189598000; - when : "RESET_B&!CLK_N&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0182233000; - when : "RESET_B&CLK_N&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0176083000; - when : "!RESET_B&!CLK_N&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0186181000; - when : "RESET_B&!CLK_N&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0178928000; - when : "RESET_B&CLK_N&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0172778000; - when : "!RESET_B&!CLK_N&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0085790000; - when : "RESET_B&!CLK_N&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0077601000; - when : "RESET_B&!CLK_N&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0076552000; - when : "RESET_B&!CLK_N&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0072188000; - when : "RESET_B&CLK_N&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0178549000; - when : "!RESET_B&!CLK_N&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0086753000; - when : "RESET_B&!CLK_N&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0077193000; - when : "RESET_B&CLK_N&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0183553000; - when : "!RESET_B&!CLK_N&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0079188000; - when : "RESET_B&!CLK_N&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0075605000; - when : "RESET_B&CLK_N&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0181965000; - when : "!RESET_B&!CLK_N&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0092401000; - when : "RESET_B&CLK_N&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0176248000; - when : "RESET_B&CLK_N&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0173759000; - when : "!RESET_B&CLK_N&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0094698000; - when : "RESET_B&CLK_N&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0093735000; - when : "RESET_B&CLK_N&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0173880000; - when : "RESET_B&CLK_N&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0178885000; - when : "RESET_B&CLK_N&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0175093000; - when : "!RESET_B&CLK_N&!D&SCD&!SCE&!Q"; - } - area : 31.280000000; - cell_footprint : "sky130_fd_sc_hd__sdfrtn"; - cell_leakage_power : 0.0147064500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "!CLK_N"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK_N") { - capacitance : 0.0024530000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023050000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0270744000, 0.0269030000, 0.0265080000, 0.0266071000, 0.0268357000, 0.0273628000, 0.0285777000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0213368000, 0.0212264000, 0.0209718000, 0.0210349000, 0.0211805000, 0.0215162000, 0.0222899000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0026010000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1434204000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK_N"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2247102000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016130000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079887000, 0.0079026000, 0.0077042000, 0.0077446000, 0.0078379000, 0.0080531000, 0.0085492000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022742000, 0.0022417000, 0.0021669000, 0.0021771000, 0.0022008000, 0.0022556000, 0.0023818000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016610000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3132793000, 0.5116354000, 0.8636048000", \ - "0.1881654000, 0.3865215000, 0.7323874000", \ - "0.0461569000, 0.2445130000, 0.5842754000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0630352000, 0.2064596000, 0.3374818000", \ - "-0.129217500, 0.0105449000, 0.1440085000", \ - "-0.342026700, -0.209588500, -0.082228500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.215285200, -0.412420600, -0.724106800", \ - "-0.084067700, -0.279982400, -0.585565100", \ - "0.0445130000, -0.150181000, -0.452101600"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0044414000, -0.123113900, -0.204087200", \ - "0.1820456000, 0.0569316000, -0.037469400", \ - "0.3814271000, 0.2599753000, 0.1631328000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013362870, 0.0035713250, 0.0095446290, 0.0255087200, 0.0681739400, 0.1821999000"); - values("0.0149419000, 0.0139138000, 0.0111575000, 0.0025391000, -0.022741800, -0.091664300, -0.276306700", \ - "0.0150084000, 0.0139710000, 0.0112227000, 0.0026018000, -0.022685500, -0.091603200, -0.276245300", \ - "0.0151043000, 0.0140518000, 0.0112994000, 0.0026931000, -0.022597000, -0.091502800, -0.276170000", \ - "0.0146914000, 0.0136384000, 0.0108859000, 0.0022808000, -0.023008500, -0.091914200, -0.276579700", \ - "0.0143752000, 0.0133378000, 0.0105796000, 0.0019875000, -0.023309300, -0.092221800, -0.276850300", \ - "0.0139373000, 0.0129213000, 0.0102068000, 0.0016426000, -0.023643400, -0.092545400, -0.277180900", \ - "0.0174897000, 0.0161967000, 0.0127346000, 0.0033387000, -0.022272200, -0.090855000, -0.275486100"); - } - related_pin : "CLK_N"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013362870, 0.0035713250, 0.0095446290, 0.0255087200, 0.0681739400, 0.1821999000"); - values("0.0205014000, 0.0220467000, 0.0260862000, 0.0361033000, 0.0618721000, 0.1309177000, 0.3143873000", \ - "0.0204193000, 0.0219761000, 0.0260058000, 0.0359841000, 0.0617625000, 0.1301425000, 0.3142766000", \ - "0.0204886000, 0.0220550000, 0.0260753000, 0.0360637000, 0.0618609000, 0.1302592000, 0.3143475000", \ - "0.0203017000, 0.0218580000, 0.0258734000, 0.0358540000, 0.0616187000, 0.1299605000, 0.3144085000", \ - "0.0203150000, 0.0218679000, 0.0258979000, 0.0358779000, 0.0616628000, 0.1300205000, 0.3142029000", \ - "0.0205708000, 0.0221334000, 0.0261443000, 0.0361316000, 0.0618901000, 0.1309866000, 0.3146191000", \ - "0.0224712000, 0.0238920000, 0.0275979000, 0.0374011000, 0.0634071000, 0.1315884000, 0.3141508000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013362870, 0.0035713250, 0.0095446290, 0.0255087200, 0.0681739400, 0.1821999000"); - values("0.0156624000, 0.0166275000, 0.0148092000, 0.0066883000, -0.018717900, -0.087622800, -0.272269900", \ - "0.0154835000, 0.0164771000, 0.0146411000, 0.0065155000, -0.018869200, -0.087783800, -0.272408100", \ - "0.0155271000, 0.0165006000, 0.0147090000, 0.0065509000, -0.018831400, -0.087746800, -0.272346000", \ - "0.0155145000, 0.0162641000, 0.0144508000, 0.0062974000, -0.019086200, -0.087982500, -0.272604300", \ - "0.0153858000, 0.0160738000, 0.0141654000, 0.0059745000, -0.019405300, -0.088255000, -0.272834900", \ - "0.0177324000, 0.0165796000, 0.0140475000, 0.0056862000, -0.019730900, -0.088544900, -0.273074100", \ - "0.0207181000, 0.0192321000, 0.0154955000, 0.0057559000, -0.020010600, -0.088500700, -0.272999600"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1822000000; - max_transition : 1.5000970000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.2722941000, 0.2804225000, 0.2970617000, 0.3293681000, 0.3941509000, 0.5455890000, 0.9438457000", \ - "0.2771565000, 0.2852702000, 0.3019290000, 0.3341267000, 0.3990805000, 0.5506612000, 0.9490184000", \ - "0.2896408000, 0.2977717000, 0.3144285000, 0.3466740000, 0.4115389000, 0.5631368000, 0.9602188000", \ - "0.3204443000, 0.3285753000, 0.3452321000, 0.3774783000, 0.4423429000, 0.5939412000, 0.9910065000", \ - "0.3882079000, 0.3963315000, 0.4129823000, 0.4451667000, 0.5100932000, 0.6615538000, 1.0593447000", \ - "0.5020174000, 0.5101480000, 0.5267476000, 0.5589081000, 0.6237760000, 0.7753406000, 1.1739089000", \ - "0.6781545000, 0.6862847000, 0.7030360000, 0.7353379000, 0.8002100000, 0.9518364000, 1.3484275000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.3096794000, 0.3179767000, 0.3359300000, 0.3747000000, 0.4673713000, 0.7097806000, 1.3569544000", \ - "0.3143550000, 0.3226246000, 0.3405933000, 0.3794048000, 0.4718824000, 0.7138146000, 1.3602454000", \ - "0.3267513000, 0.3350347000, 0.3530081000, 0.3918331000, 0.4843201000, 0.7262859000, 1.3728212000", \ - "0.3579155000, 0.3661869000, 0.3841691000, 0.4229478000, 0.5156662000, 0.7572716000, 1.4016620000", \ - "0.4259787000, 0.4342533000, 0.4522209000, 0.4910317000, 0.5834939000, 0.8254565000, 1.4718837000", \ - "0.5439545000, 0.5522174000, 0.5701771000, 0.6089881000, 0.7014566000, 0.9437586000, 1.5919248000", \ - "0.7237435000, 0.7320192000, 0.7499646000, 0.7887328000, 0.8814175000, 1.1238249000, 1.7702609000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.0276261000, 0.0328873000, 0.0445550000, 0.0719041000, 0.1390857000, 0.3288787000, 0.8540513000", \ - "0.0276111000, 0.0330603000, 0.0444388000, 0.0719342000, 0.1393612000, 0.3299350000, 0.8584273000", \ - "0.0276203000, 0.0331516000, 0.0445698000, 0.0719079000, 0.1390371000, 0.3303613000, 0.8555842000", \ - "0.0276199000, 0.0331523000, 0.0445714000, 0.0719090000, 0.1390365000, 0.3303692000, 0.8554691000", \ - "0.0276582000, 0.0330805000, 0.0445717000, 0.0719863000, 0.1390381000, 0.3293483000, 0.8547618000", \ - "0.0277269000, 0.0328675000, 0.0445833000, 0.0715885000, 0.1392404000, 0.3291196000, 0.8592372000", \ - "0.0277448000, 0.0330203000, 0.0448765000, 0.0720440000, 0.1388135000, 0.3286287000, 0.8557429000"); - } - related_pin : "CLK_N"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.0274334000, 0.0343459000, 0.0513539000, 0.0959283000, 0.2215083000, 0.5667921000, 1.4980973000", \ - "0.0274969000, 0.0343816000, 0.0512955000, 0.0960679000, 0.2209529000, 0.5664323000, 1.5000974000", \ - "0.0274692000, 0.0342682000, 0.0512730000, 0.0960641000, 0.2209892000, 0.5664254000, 1.4999618000", \ - "0.0274818000, 0.0342837000, 0.0513436000, 0.0959953000, 0.2215011000, 0.5673911000, 1.4983176000", \ - "0.0274196000, 0.0343766000, 0.0512898000, 0.0960646000, 0.2209774000, 0.5663458000, 1.5000453000", \ - "0.0273468000, 0.0343005000, 0.0512760000, 0.0960595000, 0.2213954000, 0.5660622000, 1.4951422000", \ - "0.0273156000, 0.0342512000, 0.0512580000, 0.0959407000, 0.2211931000, 0.5645462000, 1.4960383000"); - } - timing_sense : "non_unate"; - timing_type : "falling_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.1579051000, 0.1666980000, 0.1849817000, 0.2207944000, 0.2874856000, 0.4372035000, 0.8349988000", \ - "0.1626389000, 0.1714536000, 0.1897421000, 0.2255714000, 0.2923160000, 0.4419243000, 0.8394912000", \ - "0.1751075000, 0.1838964000, 0.2021704000, 0.2380243000, 0.3047910000, 0.4544647000, 0.8518010000", \ - "0.2065190000, 0.2153308000, 0.2335327000, 0.2693426000, 0.3361269000, 0.4858580000, 0.8823552000", \ - "0.2826012000, 0.2913522000, 0.3094733000, 0.3451631000, 0.4119029000, 0.5615962000, 0.9590155000", \ - "0.4375765000, 0.4479897000, 0.4690196000, 0.5082781000, 0.5757975000, 0.7254544000, 1.1217481000", \ - "0.6909881000, 0.7047503000, 0.7325074000, 0.7830788000, 0.8543257000, 1.0041346000, 1.4006375000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013362900, 0.0035713300, 0.0095446300, 0.0255087000, 0.0681739000, 0.1822000000"); - values("0.0301981000, 0.0362817000, 0.0495634000, 0.0778913000, 0.1395499000, 0.3258473000, 0.8576334000", \ - "0.0302141000, 0.0362407000, 0.0495690000, 0.0778356000, 0.1396005000, 0.3264971000, 0.8590907000", \ - "0.0303779000, 0.0362491000, 0.0496871000, 0.0779578000, 0.1396800000, 0.3276348000, 0.8568350000", \ - "0.0304570000, 0.0362300000, 0.0499991000, 0.0780488000, 0.1396531000, 0.3285743000, 0.8565467000", \ - "0.0305651000, 0.0363203000, 0.0497501000, 0.0779781000, 0.1396077000, 0.3266170000, 0.8533396000", \ - "0.0397271000, 0.0460162000, 0.0597181000, 0.0848143000, 0.1415912000, 0.3266010000, 0.8560856000", \ - "0.0588192000, 0.0667804000, 0.0839985000, 0.1064911000, 0.1494130000, 0.3278634000, 0.8571129000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035030000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049774000, 0.0049567000, 0.0049089000, 0.0049186000, 0.0049408000, 0.0049921000, 0.0051103000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.004820600, -0.004820200, -0.004819100, -0.004830800, -0.004857700, -0.004919700, -0.005062600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035140000; - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.264113300, -0.137778600, 0.1226380000", \ - "-0.475897100, -0.355666000, -0.131870400", \ - "-0.716782500, -0.606317100, -0.414259800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3657695000, 0.5043275000, 0.7797995000", \ - "0.5531393000, 0.6904766000, 0.9671693000", \ - "0.7659486000, 0.9032858000, 1.1763164000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3060000000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0018030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030973000, 0.0031026000, 0.0031147000, 0.0031226000, 0.0031408000, 0.0031830000, 0.0032802000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003021100, -0.003024400, -0.003032100, -0.003040200, -0.003058800, -0.003101600, -0.003200400"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019400000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4109356000, 0.5848776000, 0.8990052000", \ - "0.2846009000, 0.4585430000, 0.7726706000", \ - "0.1425925000, 0.3153138000, 0.6282207000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1985332000, 0.3102194000, 0.4510072000", \ - "0.0001771000, 0.1130840000, 0.2563132000", \ - "-0.219956400, -0.109490900, 0.0312969000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.283644500, -0.457586600, -0.739975900", \ - "-0.151206400, -0.323927700, -0.600213600", \ - "-0.023846400, -0.195347000, -0.470412100"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.085890600, -0.191473300, -0.301743500", \ - "0.0868307000, -0.017531200, -0.135125600", \ - "0.2837708000, 0.1769674000, 0.0581523000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0125718000, 0.0124289000, 0.0120994000, 0.0121507000, 0.0122691000, 0.0125420000, 0.0131711000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000196400, -0.000272500, -0.000448100, -0.000428600, -0.000383600, -0.000279700, -4.0269017e-05"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0040530000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3486797000, 0.5189596000, 0.8282044000", \ - "0.2235658000, 0.3926250000, 0.7006491000", \ - "0.0827780000, 0.2506165000, 0.5561992000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3853008000, 0.4896627000, 0.5437806000", \ - "0.2589661000, 0.3645488000, 0.4186667000", \ - "0.1169577000, 0.2213197000, 0.2766582000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.079787100, -0.264715500, -0.476304100", \ - "0.0990378000, -0.087111300, -0.297479200", \ - "0.3008607000, 0.1134909000, -0.096877000"); - } - related_pin : "CLK_N"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.065138700, -0.232977200, -0.393296200", \ - "0.1075827000, -0.057814500, -0.229119800", \ - "0.3057435000, 0.1403463000, -0.034621100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_falling"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "!CLK_N"; - next_state : "D"; - } - pin ("CLK_N") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrtp_1") { - leakage_power () { - value : 0.0177584000; - when : "!RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0175076000; - when : "!RESET_B&!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0189362000; - when : "RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0182187000; - when : "RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0181224000; - when : "RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0176780000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0172258000; - when : "!RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0085270000; - when : "RESET_B&CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0089909000; - when : "RESET_B&CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0074998000; - when : "RESET_B&CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0073737000; - when : "RESET_B&!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0181730000; - when : "!RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0184530000; - when : "RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0179891000; - when : "RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0191999000; - when : "RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0179077000; - when : "RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0174555000; - when : "!RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0190412000; - when : "RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0181419000; - when : "RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0176897000; - when : "!RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0186995000; - when : "RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0178114000; - when : "RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0173592000; - when : "!RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0086604000; - when : "RESET_B&CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0078415000; - when : "RESET_B&CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0077366000; - when : "RESET_B&CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0071369000; - when : "RESET_B&!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0179362000; - when : "!RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0087567000; - when : "RESET_B&CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0076373000; - when : "RESET_B&!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0184367000; - when : "!RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0080002000; - when : "RESET_B&CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0074786000; - when : "RESET_B&!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0182779000; - when : "!RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0175434000; - when : "RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0172945000; - when : "!RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093884000; - when : "RESET_B&!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0092921000; - when : "RESET_B&!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0091587000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0173066000; - when : "RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0178071000; - when : "RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0174279000; - when : "!RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0175242000; - when : "!RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0096227000; - when : "RESET_B&!CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0176483000; - when : "RESET_B&!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0176663000; - when : "!RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0174027000; - when : "!RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0171659000; - when : "!RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - area : 31.280000000; - cell_footprint : "sky130_fd_sc_hd__sdfrtp"; - cell_leakage_power : 0.0147064000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0024400000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0296567000, 0.0294825000, 0.0290808000, 0.0292117000, 0.0295137000, 0.0302097000, 0.0318140000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184375000, 0.0183180000, 0.0180425000, 0.0181136000, 0.0182778000, 0.0186563000, 0.0195287000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025540000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2675521000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1390263000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079870000, 0.0079014000, 0.0077041000, 0.0077446000, 0.0078381000, 0.0080537000, 0.0085508000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022788000, 0.0022461000, 0.0021709000, 0.0021808000, 0.0022038000, 0.0022569000, 0.0023792000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2998515000, 0.4982077000, 0.8501771000", \ - "0.2040345000, 0.4036113000, 0.7568014000", \ - "0.1572409000, 0.3580384000, 0.7100078000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1216289000, 0.2613913000, 0.3826478000", \ - "0.0709779000, 0.2021953000, 0.3112448000", \ - "0.0803366000, 0.2054505000, 0.3083965000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.179884800, -0.377020200, -0.680161400", \ - "-0.110923200, -0.310500000, -0.638055300", \ - "-0.073895200, -0.275913400, -0.609572300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.084669900, -0.215887400, -0.309067700", \ - "-0.048667300, -0.175002000, -0.273065100", \ - "-0.062908900, -0.186802100, -0.284865200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0165237000, 0.0154481000, 0.0126946000, 0.0040038000, -0.021406500, -0.090645100, -0.276296400", \ - "0.0163407000, 0.0152834000, 0.0125081000, 0.0038111000, -0.021593600, -0.090822800, -0.276486600", \ - "0.0162971000, 0.0152353000, 0.0124640000, 0.0037735000, -0.021636200, -0.090864700, -0.276513900", \ - "0.0158343000, 0.0147569000, 0.0120054000, 0.0033142000, -0.022087400, -0.091332000, -0.276981800", \ - "0.0155643000, 0.0145144000, 0.0117312000, 0.0030294000, -0.022374000, -0.091617600, -0.277274900", \ - "0.0162386000, 0.0149137000, 0.0116492000, 0.0029011000, -0.022515200, -0.091747700, -0.277415100", \ - "0.0184665000, 0.0171727000, 0.0137142000, 0.0042961000, -0.021409400, -0.090816200, -0.276476000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0178455000, 0.0194166000, 0.0234297000, 0.0334558000, 0.0594197000, 0.1285854000, 0.3120663000", \ - "0.0178005000, 0.0193684000, 0.0234007000, 0.0334207000, 0.0593238000, 0.1286152000, 0.3129135000", \ - "0.0178166000, 0.0193763000, 0.0234095000, 0.0334288000, 0.0593228000, 0.1286264000, 0.3127237000", \ - "0.0171189000, 0.0186632000, 0.0227227000, 0.0327414000, 0.0588074000, 0.1271457000, 0.3112289000", \ - "0.0166777000, 0.0182283000, 0.0222703000, 0.0322886000, 0.0582334000, 0.1274036000, 0.3112701000", \ - "0.0169578000, 0.0183263000, 0.0221174000, 0.0321852000, 0.0579698000, 0.1265366000, 0.3109205000", \ - "0.0183481000, 0.0197431000, 0.0234689000, 0.0333754000, 0.0590513000, 0.1280903000, 0.3118762000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013374040, 0.0035772970, 0.0095685790, 0.0255941000, 0.0684592900, 0.1831154000"); - values("0.0149976000, 0.0141495000, 0.0124884000, 0.0098245000, -0.005015200, -0.073949300, -0.259581300", \ - "0.0149305000, 0.0140900000, 0.0124871000, 0.0098485000, -0.005066500, -0.073979000, -0.259619500", \ - "0.0146811000, 0.0138483000, 0.0122776000, 0.0098100000, -0.005300600, -0.074261000, -0.259863000", \ - "0.0145422000, 0.0137100000, 0.0122945000, 0.0100884000, -0.005601900, -0.074559800, -0.260194800", \ - "0.0151653000, 0.0144446000, 0.0133776000, 0.0120672000, -0.005703100, -0.074695400, -0.260353700", \ - "0.0174074000, 0.0167294000, 0.0166252000, 0.0164717000, -0.005763100, -0.074843400, -0.260486500", \ - "0.0349893000, 0.0335237000, 0.0297692000, 0.0204466000, -0.005471300, -0.074390200, -0.259979400"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1831150000; - max_transition : 1.5067330000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.2864168000, 0.2945175000, 0.3112487000, 0.3434244000, 0.4084776000, 0.5607380000, 0.9598370000", \ - "0.2910464000, 0.2991517000, 0.3158711000, 0.3480377000, 0.4132388000, 0.5653651000, 0.9650263000", \ - "0.3019043000, 0.3100192000, 0.3267564000, 0.3589135000, 0.4240789000, 0.5762754000, 0.9751762000", \ - "0.3262228000, 0.3343247000, 0.3510525000, 0.3832322000, 0.4482852000, 0.6005517000, 0.9996409000", \ - "0.3639934000, 0.3721200000, 0.3887972000, 0.4209528000, 0.4861169000, 0.6382530000, 1.0389978000", \ - "0.4136017000, 0.4217035000, 0.4384330000, 0.4705875000, 0.5356487000, 0.6879008000, 1.0886176000", \ - "0.4641336000, 0.4722338000, 0.4889272000, 0.5212670000, 0.5863201000, 0.7386082000, 1.1383068000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.2575737000, 0.2658508000, 0.2838263000, 0.3227726000, 0.4155464000, 0.6587624000, 1.3075183000", \ - "0.2621257000, 0.2704030000, 0.2883933000, 0.3273155000, 0.4201718000, 0.6632481000, 1.3147980000", \ - "0.2728632000, 0.2811450000, 0.2991128000, 0.3379697000, 0.4309875000, 0.6745251000, 1.3227388000", \ - "0.2968811000, 0.3051724000, 0.3231357000, 0.3620319000, 0.4551027000, 0.6985277000, 1.3475220000", \ - "0.3362201000, 0.3445085000, 0.3624883000, 0.4013796000, 0.4944355000, 0.7379818000, 1.3872327000", \ - "0.3885322000, 0.3968030000, 0.4148132000, 0.4537204000, 0.5464838000, 0.7903669000, 1.4393551000", \ - "0.4470237000, 0.4553047000, 0.4733078000, 0.5122147000, 0.6049939000, 0.8478743000, 1.4961569000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0277881000, 0.0329047000, 0.0446060000, 0.0715622000, 0.1397049000, 0.3311216000, 0.8705519000", \ - "0.0277887000, 0.0328198000, 0.0446489000, 0.0721933000, 0.1396596000, 0.3305597000, 0.8612713000", \ - "0.0277870000, 0.0329005000, 0.0451453000, 0.0722691000, 0.1396455000, 0.3310327000, 0.8700347000", \ - "0.0277880000, 0.0329007000, 0.0445773000, 0.0715658000, 0.1397048000, 0.3311975000, 0.8702486000", \ - "0.0276909000, 0.0328718000, 0.0446311000, 0.0721988000, 0.1392860000, 0.3307593000, 0.8585371000", \ - "0.0277890000, 0.0329056000, 0.0446097000, 0.0720505000, 0.1389800000, 0.3299241000, 0.8665349000", \ - "0.0275912000, 0.0328152000, 0.0446904000, 0.0719465000, 0.1399282000, 0.3318678000, 0.8577236000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0273928000, 0.0342369000, 0.0512802000, 0.0961506000, 0.2217646000, 0.5685910000, 1.5022555000", \ - "0.0273699000, 0.0341692000, 0.0512582000, 0.0961933000, 0.2216328000, 0.5682250000, 1.5031253000", \ - "0.0273763000, 0.0342878000, 0.0513016000, 0.0960726000, 0.2220110000, 0.5698796000, 1.5067334000", \ - "0.0274443000, 0.0343715000, 0.0514248000, 0.0961086000, 0.2219170000, 0.5679956000, 1.5061018000", \ - "0.0273939000, 0.0343299000, 0.0512651000, 0.0961276000, 0.2215175000, 0.5695203000, 1.5048566000", \ - "0.0273212000, 0.0342928000, 0.0513455000, 0.0962186000, 0.2216349000, 0.5686332000, 1.5053635000", \ - "0.0274658000, 0.0344024000, 0.0513840000, 0.0962429000, 0.2221802000, 0.5687331000, 1.5037505000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.1570489000, 0.1653962000, 0.1825480000, 0.2157203000, 0.2821298000, 0.4416047000, 0.8406065000", \ - "0.1618561000, 0.1702335000, 0.1875122000, 0.2207400000, 0.2871221000, 0.4466112000, 0.8456599000", \ - "0.1744565000, 0.1828276000, 0.1998917000, 0.2330674000, 0.2995322000, 0.4590292000, 0.8578846000", \ - "0.2057991000, 0.2141699000, 0.2313286000, 0.2644388000, 0.3310568000, 0.4906064000, 0.8895192000", \ - "0.2820288000, 0.2903218000, 0.3073956000, 0.3405197000, 0.4073665000, 0.5666734000, 0.9654345000", \ - "0.4363175000, 0.4462214000, 0.4659055000, 0.5022316000, 0.5724052000, 0.7304440000, 1.1290026000", \ - "0.6880869000, 0.7012180000, 0.7274898000, 0.7738736000, 0.8567887000, 1.0121078000, 1.4103722000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013374000, 0.0035773000, 0.0095685800, 0.0255941000, 0.0684593000, 0.1831150000"); - values("0.0291038000, 0.0345047000, 0.0464704000, 0.0738548000, 0.1423594000, 0.3359421000, 0.8584448000", \ - "0.0289082000, 0.0343221000, 0.0466570000, 0.0737482000, 0.1424730000, 0.3356361000, 0.8594668000", \ - "0.0292674000, 0.0344331000, 0.0465791000, 0.0741185000, 0.1424065000, 0.3365145000, 0.8632436000", \ - "0.0289577000, 0.0345533000, 0.0466440000, 0.0737616000, 0.1429820000, 0.3355751000, 0.8584261000", \ - "0.0290300000, 0.0346021000, 0.0472546000, 0.0742835000, 0.1440821000, 0.3352476000, 0.8618475000", \ - "0.0379202000, 0.0439279000, 0.0560582000, 0.0825935000, 0.1507915000, 0.3342929000, 0.8616092000", \ - "0.0560879000, 0.0636705000, 0.0784569000, 0.1080497000, 0.1670839000, 0.3342772000, 0.8602875000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0049712000, 0.0049514000, 0.0049055000, 0.0049153000, 0.0049378000, 0.0049896000, 0.0051091000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005495800, -0.005461300, -0.005381800, -0.005395000, -0.005425300, -0.005495100, -0.005656100"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035280000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.204298800, -0.074302100, 0.2044251000", \ - "-0.326971400, -0.205519500, 0.0463522000", \ - "-0.407944700, -0.292596300, -0.057814500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4152162000, 0.6845847000", \ - "0.3871237000, 0.5232402000, 0.7852845000", \ - "0.4632142000, 0.5944479000, 0.8491679000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1785727000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031000000, 0.0031038000, 0.0031125000, 0.0031202000, 0.0031383000, 0.0031799000, 0.0032758000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003022700, -0.003024800, -0.003029600, -0.003037800, -0.003056400, -0.003099400, -0.003198600"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3962871000, 0.5702292000, 0.8855775000", \ - "0.3016907000, 0.4756328000, 0.7909811000", \ - "0.2561178000, 0.4312806000, 0.7478496000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2461406000, 0.3578268000, 0.4949525000", \ - "0.1893861000, 0.2998515000, 0.4333151000", \ - "0.2024069000, 0.3128724000, 0.4451152000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.245802700, -0.419744800, -0.696030600", \ - "-0.195151700, -0.369093700, -0.662469400", \ - "-0.166668600, -0.341831400, -0.643752000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.181105500, -0.286688200, -0.405503300", \ - "-0.156089200, -0.262892600, -0.385369800", \ - "-0.180096400, -0.288120500, -0.413039100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127239000, 0.0125722000, 0.0122225000, 0.0122744000, 0.0123941000, 0.0126702000, 0.0133064000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000327200, -0.000401400, -0.000572500, -0.000553500, -0.000509400, -0.000407800, -0.000173600"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0039730000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3352520000, 0.5043112000, 0.8135560000", \ - "0.2394349000, 0.4084941000, 0.7214010000", \ - "0.1914206000, 0.3617005000, 0.6758281000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3706523000, 0.4750143000, 0.5291322000", \ - "0.2760560000, 0.3804180000, 0.4345358000", \ - "0.2304831000, 0.3348451000, 0.3889629000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.215285200, -0.384344400, -0.661850900", \ - "-0.146323600, -0.315382800, -0.611199900", \ - "-0.109295600, -0.278354800, -0.580275400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.233595700, -0.346502600, -0.407944700", \ - "-0.173179000, -0.281203100, -0.341424500", \ - "-0.141033800, -0.249058000, -0.308058600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrtp_2") { - leakage_power () { - value : 0.0148932000; - when : "RESET_B&!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0149111000; - when : "!RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0146475000; - when : "!RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0144107000; - when : "!RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0150032000; - when : "!RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0147524000; - when : "!RESET_B&!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0161811000; - when : "RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0154636000; - when : "RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0153673000; - when : "RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0149229000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0144706000; - when : "!RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0088909000; - when : "RESET_B&CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0093548000; - when : "RESET_B&CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0078637000; - when : "RESET_B&CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0077376000; - when : "RESET_B&!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0154178000; - when : "!RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0156978000; - when : "RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0152339000; - when : "RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0164447000; - when : "RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0151525000; - when : "RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0147003000; - when : "!RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0162860000; - when : "RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0153868000; - when : "RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0149345000; - when : "!RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0159443000; - when : "RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0150562000; - when : "RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0146040000; - when : "!RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0090243000; - when : "RESET_B&CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0082054000; - when : "RESET_B&CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0081005000; - when : "RESET_B&CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0075008000; - when : "RESET_B&!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0151811000; - when : "!RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0091206000; - when : "RESET_B&CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0080012000; - when : "RESET_B&!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0156815000; - when : "!RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0083641000; - when : "RESET_B&CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0078425000; - when : "RESET_B&!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0155227000; - when : "!RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0147882000; - when : "RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0145393000; - when : "!RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0097523000; - when : "RESET_B&!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0096560000; - when : "RESET_B&!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0095226000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0145514000; - when : "RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0150519000; - when : "RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0146727000; - when : "!RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0147690000; - when : "!RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0099866000; - when : "RESET_B&!CLK&D&!SCD&SCE&Q"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__sdfrtp"; - cell_leakage_power : 0.0129909200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0024370000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023210000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0296385000, 0.0294603000, 0.0290494000, 0.0291767000, 0.0294704000, 0.0301474000, 0.0317079000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184362000, 0.0183172000, 0.0180429000, 0.0181187000, 0.0182936000, 0.0186968000, 0.0196261000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025540000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2686506000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1555040000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079874000, 0.0079015000, 0.0077036000, 0.0077443000, 0.0078384000, 0.0080554000, 0.0085556000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022775000, 0.0022470000, 0.0021768000, 0.0021860000, 0.0022074000, 0.0022569000, 0.0023709000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4994284000, 0.8526185000", \ - "0.2052552000, 0.4048320000, 0.7580221000", \ - "0.1584616000, 0.3592591000, 0.7112285000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1289531000, 0.2674948000, 0.3911927000", \ - "0.0734193000, 0.2046367000, 0.3149069000", \ - "0.0815573000, 0.2078919000, 0.3108379000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.171339800, -0.367254600, -0.659409500", \ - "-0.103599000, -0.303175800, -0.627069000", \ - "-0.069012400, -0.268589200, -0.601027400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.083449200, -0.214666700, -0.305405600", \ - "-0.048667300, -0.175002000, -0.273065100", \ - "-0.062908900, -0.186802100, -0.283644500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014743640, 0.0043475000, 0.0128196000, 0.0378015200, 0.1114664000, 0.3286842000"); - values("0.0209218000, 0.0194676000, 0.0164444000, 0.0101944000, -0.019368000, -0.137740200, -0.489408300", \ - "0.0209317000, 0.0194395000, 0.0163971000, 0.0101762000, -0.019361500, -0.137728400, -0.489370000", \ - "0.0206679000, 0.0192126000, 0.0162590000, 0.0100428000, -0.019696100, -0.138050300, -0.489733800", \ - "0.0208017000, 0.0194172000, 0.0164422000, 0.0103151000, -0.019987200, -0.138358300, -0.490001000", \ - "0.0221648000, 0.0207088000, 0.0178583000, 0.0123127000, -0.020160600, -0.138631300, -0.490252800", \ - "0.0270583000, 0.0255377000, 0.0225971000, 0.0173374000, -0.020092200, -0.138903400, -0.490438500", \ - "0.0418124000, 0.0399187000, 0.0349035000, 0.0208029000, -0.019794500, -0.138371700, -0.489866400"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014743640, 0.0043475000, 0.0128196000, 0.0378015200, 0.1114664000, 0.3286842000"); - values("0.0199564000, 0.0184239000, 0.0144533000, 0.0026888000, -0.036005100, -0.154680700, -0.506375200", \ - "0.0197922000, 0.0182451000, 0.0142741000, 0.0024967000, -0.036192800, -0.154870800, -0.506549100", \ - "0.0197762000, 0.0182103000, 0.0142497000, 0.0024623000, -0.036237800, -0.154923700, -0.506601600", \ - "0.0192712000, 0.0177287000, 0.0137585000, 0.0019643000, -0.036695900, -0.155374400, -0.507066000", \ - "0.0190384000, 0.0174833000, 0.0135043000, 0.0017450000, -0.036983400, -0.155666100, -0.507332300", \ - "0.0188597000, 0.0173215000, 0.0133354000, 0.0015465000, -0.037151500, -0.155821600, -0.507515100", \ - "0.0239544000, 0.0223612000, 0.0177839000, 0.0044765000, -0.035391600, -0.154491100, -0.506156600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014743640, 0.0043475000, 0.0128196000, 0.0378015200, 0.1114664000, 0.3286842000"); - values("0.0229281000, 0.0245931000, 0.0295821000, 0.0439403000, 0.0845160000, 0.2032140000, 0.5526059000", \ - "0.0228763000, 0.0245317000, 0.0295727000, 0.0439031000, 0.0844536000, 0.2026603000, 0.5509988000", \ - "0.0229052000, 0.0245709000, 0.0295544000, 0.0439452000, 0.0844881000, 0.2023935000, 0.5521871000", \ - "0.0221320000, 0.0238425000, 0.0288744000, 0.0432436000, 0.0837875000, 0.2023641000, 0.5511635000", \ - "0.0217407000, 0.0233914000, 0.0283891000, 0.0427561000, 0.0833106000, 0.2013606000, 0.5520582000", \ - "0.0215911000, 0.0232558000, 0.0282065000, 0.0426795000, 0.0831013000, 0.2013286000, 0.5523059000", \ - "0.0235562000, 0.0251542000, 0.0299023000, 0.0439227000, 0.0843830000, 0.2028898000, 0.5517966000"); - } - } - max_capacitance : 0.3286840000; - max_transition : 1.5082220000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.3173535000, 0.3244202000, 0.3400406000, 0.3710359000, 0.4314851000, 0.5665676000, 0.9324913000", \ - "0.3219905000, 0.3290564000, 0.3446801000, 0.3758370000, 0.4364797000, 0.5711299000, 0.9378363000", \ - "0.3328675000, 0.3398923000, 0.3555267000, 0.3866853000, 0.4474058000, 0.5820117000, 0.9489096000", \ - "0.3571633000, 0.3642292000, 0.3798539000, 0.4108327000, 0.4712967000, 0.6063799000, 0.9723975000", \ - "0.3950522000, 0.4020561000, 0.4177539000, 0.4488486000, 0.5095054000, 0.6441814000, 1.0109232000", \ - "0.4446077000, 0.4516716000, 0.4672928000, 0.4984410000, 0.5586830000, 0.6935164000, 1.0602285000", \ - "0.4952528000, 0.5022614000, 0.5179465000, 0.5490582000, 0.6096577000, 0.7443772000, 1.1109209000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.2811046000, 0.2882758000, 0.3048016000, 0.3405699000, 0.4247428000, 0.6562980000, 1.3373419000", \ - "0.2856214000, 0.2928427000, 0.3093995000, 0.3451636000, 0.4291632000, 0.6615368000, 1.3405005000", \ - "0.2963799000, 0.3035459000, 0.3200845000, 0.3558931000, 0.4399804000, 0.6716923000, 1.3523637000", \ - "0.3203853000, 0.3276102000, 0.3441732000, 0.3799632000, 0.4640439000, 0.6964834000, 1.3782389000", \ - "0.3597367000, 0.3668993000, 0.3834570000, 0.4192250000, 0.5034125000, 0.7356064000, 1.4158643000", \ - "0.4121413000, 0.4193144000, 0.4358513000, 0.4716600000, 0.5555920000, 0.7875560000, 1.4677494000", \ - "0.4706365000, 0.4778623000, 0.4944160000, 0.5302210000, 0.6144033000, 0.8461982000, 1.5249811000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.0308198000, 0.0349495000, 0.0448368000, 0.0661470000, 0.1204888000, 0.2737713000, 0.7618249000", \ - "0.0308664000, 0.0349425000, 0.0449372000, 0.0665173000, 0.1201767000, 0.2730044000, 0.7547906000", \ - "0.0306721000, 0.0350256000, 0.0449992000, 0.0665293000, 0.1201448000, 0.2732029000, 0.7599959000", \ - "0.0308620000, 0.0349637000, 0.0448313000, 0.0661468000, 0.1204870000, 0.2737644000, 0.7617307000", \ - "0.0305803000, 0.0352108000, 0.0449717000, 0.0663003000, 0.1204334000, 0.2734414000, 0.7598797000", \ - "0.0308240000, 0.0349566000, 0.0449627000, 0.0662781000, 0.1197217000, 0.2730590000, 0.7595751000", \ - "0.0308173000, 0.0350806000, 0.0448020000, 0.0664233000, 0.1203348000, 0.2732882000, 0.7519681000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.0278656000, 0.0330783000, 0.0466392000, 0.0821669000, 0.1880854000, 0.5175312000, 1.5006870000", \ - "0.0278885000, 0.0331005000, 0.0466038000, 0.0820784000, 0.1878425000, 0.5169322000, 1.5044379000", \ - "0.0279019000, 0.0331222000, 0.0467134000, 0.0820647000, 0.1880368000, 0.5178939000, 1.5043948000", \ - "0.0278855000, 0.0331161000, 0.0466480000, 0.0821174000, 0.1881386000, 0.5179829000, 1.5082222000", \ - "0.0279739000, 0.0330692000, 0.0467094000, 0.0821576000, 0.1876752000, 0.5172936000, 1.5065886000", \ - "0.0277739000, 0.0331915000, 0.0467016000, 0.0821865000, 0.1878502000, 0.5172381000, 1.4986513000", \ - "0.0278984000, 0.0331987000, 0.0466528000, 0.0821959000, 0.1882193000, 0.5170811000, 1.5018439000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.1902268000, 0.1974955000, 0.2138465000, 0.2459455000, 0.3084193000, 0.4495408000, 0.8145155000", \ - "0.1952992000, 0.2025827000, 0.2188995000, 0.2508948000, 0.3134855000, 0.4546087000, 0.8193559000", \ - "0.2081487000, 0.2154303000, 0.2317473000, 0.2638018000, 0.3263679000, 0.4674285000, 0.8322187000", \ - "0.2394369000, 0.2467374000, 0.2631120000, 0.2952994000, 0.3579478000, 0.4987925000, 0.8636086000", \ - "0.3151180000, 0.3223845000, 0.3387100000, 0.3709807000, 0.4339619000, 0.5738079000, 0.9381529000", \ - "0.4830200000, 0.4911704000, 0.5090541000, 0.5433529000, 0.6090352000, 0.7438374000, 1.1084024000", \ - "0.7700738000, 0.7805064000, 0.8039681000, 0.8506375000, 0.9152106000, 1.0448895000, 1.4093605000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014743600, 0.0043475000, 0.0128196000, 0.0378015000, 0.1114660000, 0.3286840000"); - values("0.0326077000, 0.0372766000, 0.0477941000, 0.0695329000, 0.1238942000, 0.2773629000, 0.7496851000", \ - "0.0329268000, 0.0372494000, 0.0473633000, 0.0705467000, 0.1238582000, 0.2774742000, 0.7525490000", \ - "0.0326794000, 0.0373189000, 0.0479330000, 0.0704788000, 0.1242125000, 0.2772739000, 0.7529803000", \ - "0.0326523000, 0.0374616000, 0.0479134000, 0.0702722000, 0.1243082000, 0.2768076000, 0.7522084000", \ - "0.0327517000, 0.0372854000, 0.0475500000, 0.0706101000, 0.1252267000, 0.2753914000, 0.7524773000", \ - "0.0400050000, 0.0443845000, 0.0550422000, 0.0765967000, 0.1274812000, 0.2700405000, 0.7528096000", \ - "0.0623667000, 0.0684103000, 0.0820111000, 0.0986313000, 0.1263737000, 0.2668371000, 0.7530944000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035330000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048630000, 0.0048763000, 0.0049070000, 0.0049166000, 0.0049391000, 0.0049908000, 0.0051101000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005487400, -0.005456700, -0.005386000, -0.005399200, -0.005429500, -0.005499200, -0.005659900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035300000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.194533200, -0.043784500, 0.3179505000", \ - "-0.318426400, -0.178664100, 0.1501120000", \ - "-0.400620400, -0.266961600, 0.0386211000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4164368000, 0.6845847000", \ - "0.3883444000, 0.5244610000, 0.7852845000", \ - "0.4632142000, 0.5956686000, 0.8491679000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2302027000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030992000, 0.0031032000, 0.0031124000, 0.0031201000, 0.0031381000, 0.0031794000, 0.0032749000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003019100, -0.003022600, -0.003030600, -0.003039700, -0.003060500, -0.003108300, -0.003218500"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3987285000, 0.5726706000, 0.8867982000", \ - "0.3029115000, 0.4768535000, 0.7922018000", \ - "0.2573385000, 0.4325013000, 0.7490703000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2546855000, 0.3675924000, 0.5059388000", \ - "0.1930482000, 0.3035137000, 0.4369772000", \ - "0.2048483000, 0.3153138000, 0.4475566000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.233595700, -0.406317000, -0.676499400", \ - "-0.186606800, -0.362990200, -0.652703800", \ - "-0.160565100, -0.335727900, -0.636427800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.179884800, -0.286688200, -0.404282600", \ - "-0.156089200, -0.262892600, -0.385369800", \ - "-0.180096400, -0.286899700, -0.413039100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127243000, 0.0125724000, 0.0122224000, 0.0122741000, 0.0123936000, 0.0126692000, 0.0133043000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000300900, -0.000380200, -0.000562800, -0.000544700, -0.000502700, -0.000406000, -0.000183000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0039720000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3364726000, 0.5055319000, 0.8159974000", \ - "0.2406556000, 0.4097148000, 0.7214010000", \ - "0.1926413000, 0.3629212000, 0.6770489000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3718730000, 0.4762350000, 0.5303529000", \ - "0.2772767000, 0.3816387000, 0.4357565000", \ - "0.2317038000, 0.3360657000, 0.3901836000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.206740200, -0.374578800, -0.645981800", \ - "-0.138999400, -0.308058600, -0.601434200", \ - "-0.103192100, -0.272251300, -0.571730500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.221388700, -0.335516300, -0.398179000", \ - "-0.165854800, -0.273878900, -0.335321000", \ - "-0.132488900, -0.242954400, -0.301955100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfrtp_4") { - leakage_power () { - value : 0.0158659000; - when : "RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0151484000; - when : "RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0150521000; - when : "RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0146077000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0141555000; - when : "!RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0098495000; - when : "RESET_B&CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0103134000; - when : "RESET_B&CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0088223000; - when : "RESET_B&CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0086962000; - when : "RESET_B&!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0151027000; - when : "!RESET_B&CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0153826000; - when : "RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0149187000; - when : "RESET_B&CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0161296000; - when : "RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0148374000; - when : "RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0143852000; - when : "!RESET_B&CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0159708000; - when : "RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0150716000; - when : "RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0146194000; - when : "!RESET_B&CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0156291000; - when : "RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0147411000; - when : "RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0142889000; - when : "!RESET_B&CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0099828000; - when : "RESET_B&CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0091639000; - when : "RESET_B&CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0090590000; - when : "RESET_B&CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0084594000; - when : "RESET_B&!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0148659000; - when : "!RESET_B&CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0100791000; - when : "RESET_B&CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0089598000; - when : "RESET_B&!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0153663000; - when : "!RESET_B&CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0093227000; - when : "RESET_B&CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0088011000; - when : "RESET_B&!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0152076000; - when : "!RESET_B&CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0144731000; - when : "RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0142242000; - when : "!RESET_B&!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0107109000; - when : "RESET_B&!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0106146000; - when : "RESET_B&!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0104812000; - when : "RESET_B&!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0142363000; - when : "RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0147367000; - when : "RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0143575000; - when : "!RESET_B&!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0144538000; - when : "!RESET_B&!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0109451000; - when : "RESET_B&!CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0145780000; - when : "RESET_B&!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0145960000; - when : "!RESET_B&!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0143323000; - when : "!RESET_B&!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0140956000; - when : "!RESET_B&!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0146881000; - when : "!RESET_B&!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0144373000; - when : "!RESET_B&!CLK&D&SCD&SCE&!Q"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__sdfrtp"; - cell_leakage_power : 0.0131003400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0024390000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0023250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0296101000, 0.0294318000, 0.0290207000, 0.0291561000, 0.0294685000, 0.0301885000, 0.0318482000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184385000, 0.0183201000, 0.0180471000, 0.0181196000, 0.0182868000, 0.0186723000, 0.0195609000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025540000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2675521000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1851638000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0015510000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079872000, 0.0079013000, 0.0077034000, 0.0077444000, 0.0078392000, 0.0080577000, 0.0085612000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0022786000, 0.0022485000, 0.0021792000, 0.0021872000, 0.0022061000, 0.0022494000, 0.0023494000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0016770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2998515000, 0.4982077000, 0.8513978000", \ - "0.2040345000, 0.4036113000, 0.7568014000", \ - "0.1572409000, 0.3580384000, 0.7100078000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1289531000, 0.2687155000, 0.3924134000", \ - "0.0746400000, 0.2058574000, 0.3161276000", \ - "0.0815573000, 0.2078919000, 0.3108379000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.170119100, -0.367254600, -0.656968100", \ - "-0.103599000, -0.303175800, -0.625848300", \ - "-0.069012400, -0.268589200, -0.601027400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.084669900, -0.215887400, -0.307847000", \ - "-0.048667300, -0.175002000, -0.273065100", \ - "-0.062908900, -0.186802100, -0.284865200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016213760, 0.0052577200, 0.0170494800, 0.0552872400, 0.1792828000, 0.5813697000"); - values("0.0288094000, 0.0267757000, 0.0207246000, 0.0036523000, -0.054361700, -0.252813800, -0.903506600", \ - "0.0287390000, 0.0267216000, 0.0207355000, 0.0036153000, -0.054358200, -0.252767100, -0.903504000", \ - "0.0285488000, 0.0264791000, 0.0204674000, 0.0034098000, -0.054556300, -0.253002700, -0.903702300", \ - "0.0280807000, 0.0260624000, 0.0199867000, 0.0029320000, -0.055027300, -0.253447600, -0.904179700", \ - "0.0276735000, 0.0256338000, 0.0196157000, 0.0025439000, -0.055483900, -0.253858500, -0.904590100", \ - "0.0275751000, 0.0256033000, 0.0195568000, 0.0024732000, -0.055489500, -0.253925300, -0.904645700", \ - "0.0354988000, 0.0334393000, 0.0272212000, 0.0081159000, -0.052935300, -0.253007400, -0.903700400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016213760, 0.0052577200, 0.0170494800, 0.0552872400, 0.1792828000, 0.5813697000"); - values("0.0337927000, 0.0355560000, 0.0415159000, 0.0616073000, 0.1241405000, 0.3242578000, 0.9668205000", \ - "0.0336730000, 0.0354876000, 0.0414770000, 0.0614597000, 0.1241048000, 0.3230986000, 0.9682215000", \ - "0.0337148000, 0.0355734000, 0.0415378000, 0.0615056000, 0.1241133000, 0.3230146000, 0.9691025000", \ - "0.0329735000, 0.0347645000, 0.0408115000, 0.0607819000, 0.1234041000, 0.3228711000, 0.9702853000", \ - "0.0325902000, 0.0343809000, 0.0403968000, 0.0603661000, 0.1229700000, 0.3233673000, 0.9730843000", \ - "0.0324500000, 0.0342425000, 0.0402940000, 0.0600996000, 0.1228147000, 0.3216298000, 0.9666003000", \ - "0.0354569000, 0.0372279000, 0.0430718000, 0.0624049000, 0.1245626000, 0.3235582000, 0.9711847000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016213760, 0.0052577200, 0.0170494800, 0.0552872400, 0.1792828000, 0.5813697000"); - values("0.0468098000, 0.0447949000, 0.0387021000, 0.0207640000, -0.036412800, -0.235499000, -0.886291700", \ - "0.0469196000, 0.0448597000, 0.0387699000, 0.0208054000, -0.036427400, -0.235530000, -0.886370800", \ - "0.0466488000, 0.0446193000, 0.0385890000, 0.0205540000, -0.036750000, -0.235836700, -0.886655600", \ - "0.0464855000, 0.0444437000, 0.0382779000, 0.0205177000, -0.036926100, -0.236052600, -0.886877000", \ - "0.0464380000, 0.0444276000, 0.0382981000, 0.0205398000, -0.037352100, -0.236456300, -0.887204500", \ - "0.0468818000, 0.0448260000, 0.0385893000, 0.0209115000, -0.037823700, -0.237085800, -0.887652500", \ - "0.0514826000, 0.0494462000, 0.0430981000, 0.0235031000, -0.038368600, -0.237541700, -0.887943400"); - } - related_pin : "RESET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.5813700000; - max_transition : 1.5056020000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.3901281000, 0.3958398000, 0.4106792000, 0.4436763000, 0.5092843000, 0.6475117000, 1.0136127000", \ - "0.3948863000, 0.4005636000, 0.4154541000, 0.4483063000, 0.5138800000, 0.6522616000, 1.0184116000", \ - "0.4057713000, 0.4114671000, 0.4263985000, 0.4593194000, 0.5252258000, 0.6634578000, 1.0289031000", \ - "0.4300650000, 0.4357409000, 0.4505892000, 0.4834451000, 0.5491983000, 0.6876535000, 1.0532728000", \ - "0.4679246000, 0.4736104000, 0.4885036000, 0.5214986000, 0.5872464000, 0.7252702000, 1.0911558000", \ - "0.5174333000, 0.5231480000, 0.5380046000, 0.5709117000, 0.6366549000, 0.7750351000, 1.1409792000", \ - "0.5680836000, 0.5737468000, 0.5886383000, 0.6213350000, 0.6875383000, 0.8256271000, 1.1916240000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.3323132000, 0.3383121000, 0.3539462000, 0.3897704000, 0.4719656000, 0.6965135000, 1.4089480000", \ - "0.3368570000, 0.3428741000, 0.3585094000, 0.3942995000, 0.4765552000, 0.7012156000, 1.4166517000", \ - "0.3476173000, 0.3536530000, 0.3692699000, 0.4050565000, 0.4872268000, 0.7117915000, 1.4247172000", \ - "0.3716711000, 0.3776409000, 0.3932605000, 0.4291047000, 0.5113134000, 0.7358788000, 1.4494281000", \ - "0.4109862000, 0.4169926000, 0.4326552000, 0.4684181000, 0.5506294000, 0.7752375000, 1.4891033000", \ - "0.4634304000, 0.4694392000, 0.4851221000, 0.5208675000, 0.6030140000, 0.8277407000, 1.5413451000", \ - "0.5221711000, 0.5281573000, 0.5437951000, 0.5795995000, 0.6616000000, 0.8862714000, 1.5987609000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.0446502000, 0.0480295000, 0.0569452000, 0.0774417000, 0.1255327000, 0.2621085000, 0.7244109000", \ - "0.0447934000, 0.0479530000, 0.0573512000, 0.0775154000, 0.1255172000, 0.2622881000, 0.7242724000", \ - "0.0448275000, 0.0480873000, 0.0568971000, 0.0773837000, 0.1267920000, 0.2622649000, 0.7231288000", \ - "0.0448909000, 0.0480854000, 0.0570552000, 0.0780088000, 0.1256855000, 0.2623355000, 0.7234199000", \ - "0.0448135000, 0.0480010000, 0.0569483000, 0.0774845000, 0.1258769000, 0.2627427000, 0.7225704000", \ - "0.0448090000, 0.0481050000, 0.0568418000, 0.0773311000, 0.1266347000, 0.2619218000, 0.7241389000", \ - "0.0447482000, 0.0480083000, 0.0575012000, 0.0776018000, 0.1259599000, 0.2619042000, 0.7206885000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.0366210000, 0.0406195000, 0.0523375000, 0.0822456000, 0.1718130000, 0.4774408000, 1.4990924000", \ - "0.0364434000, 0.0405836000, 0.0519887000, 0.0822648000, 0.1717187000, 0.4768957000, 1.5050636000", \ - "0.0366229000, 0.0408036000, 0.0520833000, 0.0821618000, 0.1717337000, 0.4774451000, 1.5056018000", \ - "0.0365571000, 0.0407445000, 0.0523081000, 0.0821653000, 0.1718162000, 0.4774375000, 1.5032198000", \ - "0.0365108000, 0.0405748000, 0.0521502000, 0.0820149000, 0.1717200000, 0.4774150000, 1.5052259000", \ - "0.0364785000, 0.0408090000, 0.0520225000, 0.0818364000, 0.1716566000, 0.4773623000, 1.5051363000", \ - "0.0363790000, 0.0405327000, 0.0520578000, 0.0822180000, 0.1716336000, 0.4774484000, 1.5035408000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.2685655000, 0.2746004000, 0.2902154000, 0.3251862000, 0.3952750000, 0.5272707000, 0.8853202000", \ - "0.2739322000, 0.2799478000, 0.2956684000, 0.3306764000, 0.4007712000, 0.5324687000, 0.8905094000", \ - "0.2871848000, 0.2931772000, 0.3089975000, 0.3439482000, 0.4141735000, 0.5453731000, 0.9031730000", \ - "0.3189715000, 0.3249867000, 0.3407216000, 0.3756055000, 0.4456161000, 0.5756158000, 0.9336423000", \ - "0.3948775000, 0.4009089000, 0.4166621000, 0.4516926000, 0.5201345000, 0.6471863000, 1.0048598000", \ - "0.5746006000, 0.5807019000, 0.5969934000, 0.6308145000, 0.6874795000, 0.8104518000, 1.1682652000", \ - "0.8920772000, 0.8966852000, 0.9084919000, 0.9347831000, 0.9884309000, 1.1116744000, 1.4704001000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016213800, 0.0052577200, 0.0170495000, 0.0552872000, 0.1792830000, 0.5813700000"); - values("0.0489580000, 0.0528486000, 0.0623579000, 0.0839381000, 0.1297833000, 0.2483798000, 0.7108660000", \ - "0.0490029000, 0.0525618000, 0.0628423000, 0.0840337000, 0.1295397000, 0.2480499000, 0.7128751000", \ - "0.0488054000, 0.0523089000, 0.0623232000, 0.0839618000, 0.1292984000, 0.2477117000, 0.7096141000", \ - "0.0494347000, 0.0530491000, 0.0623286000, 0.0845531000, 0.1279111000, 0.2464930000, 0.7128353000", \ - "0.0496944000, 0.0529791000, 0.0625869000, 0.0851369000, 0.1240485000, 0.2433092000, 0.7145204000", \ - "0.0516074000, 0.0551078000, 0.0634752000, 0.0771422000, 0.1089153000, 0.2389570000, 0.7128094000", \ - "0.0370419000, 0.0393769000, 0.0460518000, 0.0622205000, 0.1049506000, 0.2399752000, 0.7125964000"); - } - related_pin : "RESET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("RESET_B") { - capacitance : 0.0035230000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0035160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0048412000, 0.0048606000, 0.0049052000, 0.0049151000, 0.0049380000, 0.0049907000, 0.0051124000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.005479300, -0.005451200, -0.005386500, -0.005401600, -0.005436200, -0.005515800, -0.005699400"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035310000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.193312500, -0.030356800, 0.4033997000", \ - "-0.317205700, -0.165236300, 0.2355612000", \ - "-0.399399700, -0.253533800, 0.1216289000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4164368000, 0.6845847000", \ - "0.3883444000, 0.5244610000, 0.7865052000", \ - "0.4632142000, 0.5956686000, 0.8491679000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3180836000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "RESET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCD") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0030957000, 0.0031005000, 0.0031118000, 0.0031194000, 0.0031371000, 0.0031780000, 0.0032723000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003017600, -0.003022300, -0.003033300, -0.003043200, -0.003065800, -0.003118000, -0.003238200"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019630000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3975078000, 0.5714499000, 0.8867982000", \ - "0.3016907000, 0.4756328000, 0.7909811000", \ - "0.2573385000, 0.4325013000, 0.7490703000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2559063000, 0.3675924000, 0.5071595000", \ - "0.1930482000, 0.3035137000, 0.4381979000", \ - "0.2048483000, 0.3153138000, 0.4475566000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.232375000, -0.406317000, -0.675278600", \ - "-0.186606800, -0.362990200, -0.652703800", \ - "-0.160565100, -0.334507200, -0.636427800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.181105500, -0.287908800, -0.405503300", \ - "-0.156089200, -0.262892600, -0.385369800", \ - "-0.180096400, -0.288120500, -0.414259800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0036860000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127204000, 0.0125695000, 0.0122218000, 0.0122738000, 0.0123939000, 0.0126707000, 0.0133088000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000300800, -0.000378800, -0.000558600, -0.000540000, -0.000497100, -0.000398100, -0.000170000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0039730000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3352520000, 0.5043112000, 0.8147767000", \ - "0.2394349000, 0.4084941000, 0.7214010000", \ - "0.1926413000, 0.3629212000, 0.6758281000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3706523000, 0.4750143000, 0.5291322000", \ - "0.2760560000, 0.3804180000, 0.4345358000", \ - "0.2317038000, 0.3348451000, 0.3889629000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.204298800, -0.373358100, -0.643540300", \ - "-0.138999400, -0.308058600, -0.600213600", \ - "-0.103192100, -0.271030600, -0.571730500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.220168000, -0.334295600, -0.396958300", \ - "-0.165854800, -0.273878900, -0.335321000", \ - "-0.132488900, -0.241733700, -0.301955100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clear : "!RESET_B"; - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("RESET_B") { - direction : "input"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfsbp_1") { - leakage_power () { - value : 0.0140654000; - when : "CLK&D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0160134000; - when : "CLK&!D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0118528000; - when : "CLK&!D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0115851000; - when : "!CLK&!D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0201707000; - when : "CLK&!D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0205478000; - when : "CLK&!D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0254264000; - when : "CLK&D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0198493000; - when : "CLK&D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0209374000; - when : "!CLK&D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0208134000; - when : "CLK&D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0162812000; - when : "CLK&D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0114027000; - when : "CLK&!D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0181911000; - when : "CLK&!D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0161959000; - when : "!CLK&!D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0247815000; - when : "CLK&!D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0177828000; - when : "CLK&D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0164637000; - when : "!CLK&D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0250493000; - when : "CLK&D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0127243000; - when : "CLK&D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0120353000; - when : "!CLK&!D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0206209000; - when : "CLK&!D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0209980000; - when : "CLK&!D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0249078000; - when : "CLK&D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0211904000; - when : "CLK&D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0195962000; - when : "!CLK&D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0194722000; - when : "CLK&D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0251585000; - when : "CLK&!D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0250630000; - when : "!CLK&!D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0249390000; - when : "CLK&!D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0253161000; - when : "CLK&!D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0246547000; - when : "!CLK&D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0245307000; - when : "CLK&D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0135524000; - when : "!CLK&D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0200012000; - when : "!CLK&!D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0246735000; - when : "!CLK&!D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0205130000; - when : "!CLK&!D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0200628000; - when : "!CLK&!D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0122113000; - when : "!CLK&D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0176781000; - when : "!CLK&!D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0204514000; - when : "!CLK&!D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0246120000; - when : "!CLK&!D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0249414000; - when : "!CLK&D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0172697000; - when : "!CLK&D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0242736000; - when : "!CLK&!D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0201479000; - when : "!CLK&D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0188068000; - when : "!CLK&D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0248798000; - when : "!CLK&D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0238653000; - when : "!CLK&D&SCD&SCE&!SET_B&Q&!Q_N"; - } - area : 36.284800000; - cell_footprint : "sky130_fd_sc_hd__sdfsbp"; - cell_leakage_power : 0.0199282800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0019500000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0018620000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0232574000, 0.0231262000, 0.0228238000, 0.0228734000, 0.0229878000, 0.0232515000, 0.0238593000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184434000, 0.0183813000, 0.0182380000, 0.0182564000, 0.0182988000, 0.0183965000, 0.0186216000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020370000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3202806000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2313012000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018640000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090623000, 0.0089674000, 0.0087486000, 0.0087897000, 0.0088845000, 0.0091028000, 0.0096061000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027206000, 0.0026761000, 0.0025732000, 0.0025952000, 0.0026460000, 0.0027629000, 0.0030325000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019560000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2900859000, 0.4884421000, 0.8330873000", \ - "0.1600892000, 0.3596660000, 0.7030905000", \ - "0.0656882000, 0.2652650000, 0.6062480000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1423809000, 0.2821432000, 0.4204896000", \ - "0.0795228000, 0.2107402000, 0.3319968000", \ - "0.0644674000, 0.1920228000, 0.3022930000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.123732400, -0.317205700, -0.575181000", \ - "-0.025474000, -0.221388700, -0.525750700", \ - "0.0530579000, -0.145298200, -0.461867200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.236639300, -0.344468100", \ - "-0.057212200, -0.184767600, -0.292596300", \ - "-0.050701800, -0.177036500, -0.282423800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("0.0001485000, 0.0043546000, 0.0137457000, 0.0320753000, 0.0651692000, 0.1351231000, 0.3065467000", \ - "0.0001169000, 0.0043086000, 0.0136568000, 0.0319175000, 0.0649605000, 0.1348921000, 0.3054570000", \ - "6.910000e-05, 0.0042539000, 0.0136007000, 0.0318331000, 0.0648421000, 0.1348134000, 0.3053460000", \ - "6.400000e-05, 0.0042469000, 0.0135790000, 0.0317964000, 0.0650354000, 0.1341334000, 0.3047772000", \ - "6.545000e-05, 0.0042515000, 0.0135977000, 0.0318520000, 0.0648778000, 0.1349983000, 0.3068073000", \ - "2.530000e-05, 0.0041685000, 0.0134259000, 0.0315386000, 0.0644517000, 0.1336959000, 0.3060169000", \ - "5.160000e-05, 0.0042709000, 0.0136193000, 0.0317422000, 0.0650552000, 0.1341936000, 0.3053200000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.005864500, -0.001208200, 0.0073918000, 0.0164657000, 0.0105290000, -0.041417500, -0.204781600", \ - "-0.005843700, -0.001203500, 0.0073744000, 0.0163865000, 0.0103928000, -0.041580600, -0.204959800", \ - "-0.005781000, -0.001153400, 0.0074024000, 0.0163751000, 0.0103340000, -0.041658300, -0.205053800", \ - "-0.005802600, -0.001193100, 0.0073260000, 0.0162437000, 0.0101492000, -0.041876800, -0.205305000", \ - "-0.005835100, -0.001242000, 0.0072438000, 0.0161275000, 0.0099783000, -0.042089600, -0.205513300", \ - "-0.005878700, -0.001280900, 0.0072113000, 0.0161135000, 0.0100092000, -0.042065400, -0.205456200", \ - "-0.005924700, -0.001230900, 0.0074557000, 0.0166338000, 0.0106825000, -0.041417500, -0.204734300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.007407900, -0.004638100, 0.0017781000, 0.0160308000, 0.0451221000, 0.1116142000, 0.2826518000", \ - "-0.007376700, -0.004607400, 0.0017912000, 0.0160501000, 0.0451635000, 0.1115322000, 0.2807557000", \ - "-0.007314500, -0.004559800, 0.0018194000, 0.0160317000, 0.0450321000, 0.1120548000, 0.2817799000", \ - "-0.007344200, -0.004619300, 0.0017016000, 0.0158229000, 0.0447821000, 0.1116135000, 0.2805975000", \ - "-0.007382600, -0.004683300, 0.0015819000, 0.0156208000, 0.0444718000, 0.1113037000, 0.2813108000", \ - "-0.007430300, -0.004729400, 0.0015397000, 0.0155960000, 0.0444406000, 0.1113433000, 0.2801045000", \ - "-0.007416900, -0.004533400, 0.0021174000, 0.0161418000, 0.0448848000, 0.1114138000, 0.2803617000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.5041860000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3221056000, 0.3273334000, 0.3384400000, 0.3615858000, 0.4141442000, 0.5482237000, 0.9009296000", \ - "0.3268066000, 0.3319766000, 0.3430802000, 0.3662285000, 0.4188180000, 0.5528713000, 0.9064015000", \ - "0.3377874000, 0.3430415000, 0.3541227000, 0.3772756000, 0.4298216000, 0.5638746000, 0.9170268000", \ - "0.3636872000, 0.3689430000, 0.3800204000, 0.4031730000, 0.4557212000, 0.5897576000, 0.9424236000", \ - "0.4137853000, 0.4189686000, 0.4300563000, 0.4532474000, 0.5058075000, 0.6398153000, 0.9936261000", \ - "0.4856276000, 0.4909019000, 0.5019695000, 0.5251292000, 0.5776712000, 0.7116404000, 1.0651966000", \ - "0.5756677000, 0.5808885000, 0.5919865000, 0.6151615000, 0.6677168000, 0.8017558000, 1.1552854000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3575708000, 0.3645821000, 0.3801614000, 0.4164617000, 0.5099483000, 0.7553813000, 1.4032795000", \ - "0.3622567000, 0.3693262000, 0.3848463000, 0.4211591000, 0.5145758000, 0.7597665000, 1.4065600000", \ - "0.3734030000, 0.3804672000, 0.3960255000, 0.4323287000, 0.5257834000, 0.7710842000, 1.4195991000", \ - "0.3991031000, 0.4061718000, 0.4217280000, 0.4580268000, 0.5514922000, 0.7968209000, 1.4428535000", \ - "0.4493225000, 0.4563216000, 0.4718580000, 0.5081934000, 0.6016100000, 0.8466892000, 1.4961298000", \ - "0.5231266000, 0.5302019000, 0.5456751000, 0.5820447000, 0.6754312000, 0.9205385000, 1.5694583000", \ - "0.6172222000, 0.6242297000, 0.6398452000, 0.6761512000, 0.7695809000, 1.0149797000, 1.6633757000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0175477000, 0.0213462000, 0.0308251000, 0.0543088000, 0.1180498000, 0.2942845000, 0.7655355000", \ - "0.0174797000, 0.0214368000, 0.0308604000, 0.0543407000, 0.1180888000, 0.2937200000, 0.7691432000", \ - "0.0175178000, 0.0213372000, 0.0308465000, 0.0544129000, 0.1180615000, 0.2942640000, 0.7695307000", \ - "0.0175273000, 0.0213474000, 0.0308373000, 0.0543955000, 0.1179828000, 0.2943172000, 0.7588457000", \ - "0.0174420000, 0.0214545000, 0.0308585000, 0.0545802000, 0.1179472000, 0.2933465000, 0.7676458000", \ - "0.0175637000, 0.0213869000, 0.0308530000, 0.0540566000, 0.1180695000, 0.2945031000, 0.7679721000", \ - "0.0174135000, 0.0215066000, 0.0308875000, 0.0544097000, 0.1177775000, 0.2949646000, 0.7596286000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0254391000, 0.0314374000, 0.0479480000, 0.0951357000, 0.2270047000, 0.5751614000, 1.4995383000", \ - "0.0253759000, 0.0314830000, 0.0477773000, 0.0951790000, 0.2262840000, 0.5745424000, 1.5007312000", \ - "0.0255350000, 0.0314266000, 0.0478760000, 0.0951934000, 0.2262589000, 0.5752333000, 1.4987013000", \ - "0.0255300000, 0.0314394000, 0.0479030000, 0.0951787000, 0.2264541000, 0.5749490000, 1.4968877000", \ - "0.0254384000, 0.0313944000, 0.0478837000, 0.0951979000, 0.2266149000, 0.5739441000, 1.4999001000", \ - "0.0254655000, 0.0315121000, 0.0477164000, 0.0950437000, 0.2265568000, 0.5745761000, 1.5016123000", \ - "0.0255357000, 0.0315048000, 0.0479903000, 0.0950640000, 0.2266009000, 0.5750517000, 1.4960729000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.3560826000, 0.3625168000, 0.3773875000, 0.4134062000, 0.5066214000, 0.7520786000, 1.4026509000", \ - "0.3612758000, 0.3677248000, 0.3825765000, 0.4186487000, 0.5118853000, 0.7572352000, 1.4042925000", \ - "0.3744307000, 0.3808590000, 0.3957360000, 0.4317466000, 0.5250947000, 0.7703811000, 1.4174172000", \ - "0.4074661000, 0.4138957000, 0.4287659000, 0.4648156000, 0.5579901000, 0.8031698000, 1.4499554000", \ - "0.4833072000, 0.4897336000, 0.5045985000, 0.5406230000, 0.6338420000, 0.8792987000, 1.5298803000", \ - "0.6381821000, 0.6446370000, 0.6594982000, 0.6955199000, 0.7887419000, 1.0340829000, 1.6833749000", \ - "0.9165092000, 0.9230179000, 0.9379651000, 0.9740603000, 1.0674662000, 1.3120960000, 1.9606472000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0221567000, 0.0284437000, 0.0459288000, 0.0943658000, 0.2259771000, 0.5759664000, 1.5037959000", \ - "0.0220323000, 0.0284319000, 0.0458259000, 0.0943659000, 0.2260810000, 0.5761794000, 1.4997794000", \ - "0.0219784000, 0.0283478000, 0.0458149000, 0.0942234000, 0.2263485000, 0.5758808000, 1.4997021000", \ - "0.0219737000, 0.0283736000, 0.0457850000, 0.0943136000, 0.2262207000, 0.5757372000, 1.5041860000", \ - "0.0221282000, 0.0284200000, 0.0459275000, 0.0943532000, 0.2259539000, 0.5759693000, 1.5037063000", \ - "0.0220341000, 0.0284037000, 0.0457884000, 0.0942843000, 0.2256836000, 0.5749799000, 1.5015041000", \ - "0.0227272000, 0.0289327000, 0.0462452000, 0.0943996000, 0.2261764000, 0.5753354000, 1.4978289000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013340390, 0.0035593210, 0.0094965470, 0.0253375300, 0.0676025200, 0.1803688000"); - values("-0.005973700, -0.001386100, 0.0071393000, 0.0160649000, 0.0091202000, -0.046691300, -0.223159700", \ - "-0.005943400, -0.001363900, 0.0071578000, 0.0160612000, 0.0091215000, -0.046679200, -0.223164300", \ - "-0.005881000, -0.001315800, 0.0071821000, 0.0160495000, 0.0090489000, -0.046757600, -0.223282500", \ - "-0.005910200, -0.001373000, 0.0070644000, 0.0158410000, 0.0087528000, -0.047122500, -0.223665700", \ - "-0.005948100, -0.001434500, 0.0069523000, 0.0156487000, 0.0084991000, -0.047432100, -0.223991400", \ - "-0.005996200, -0.001478600, 0.0069072000, 0.0156114000, 0.0084514000, -0.047460200, -0.223988400", \ - "-0.006041400, -0.001432200, 0.0071408000, 0.0161445000, 0.0091446000, -0.046942500, -0.223442400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013340390, 0.0035593210, 0.0094965470, 0.0253375300, 0.0676025200, 0.1803688000"); - values("-0.007397600, -0.004558700, 0.0020933000, 0.0164721000, 0.0466919000, 0.1174911000, 0.3009176000", \ - "-0.007376500, -0.004549900, 0.0020724000, 0.0163811000, 0.0465587000, 0.1179495000, 0.2984284000", \ - "-0.007313700, -0.004500000, 0.0021019000, 0.0163645000, 0.0465195000, 0.1172567000, 0.3014393000", \ - "-0.007333500, -0.004531200, 0.0020236000, 0.0162333000, 0.0463261000, 0.1177534000, 0.3011530000", \ - "-0.007366600, -0.004597300, 0.0019241000, 0.0160888000, 0.0460861000, 0.1167694000, 0.3005851000", \ - "-0.007409100, -0.004619600, 0.0019135000, 0.0160947000, 0.0461524000, 0.1173525000, 0.2991821000", \ - "-0.007452000, -0.004568400, 0.0021861000, 0.0166535000, 0.0467285000, 0.1179900000, 0.3012490000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013340390, 0.0035593210, 0.0094965470, 0.0253375300, 0.0676025200, 0.1803688000"); - values("0.0015184000, 0.0074927000, 0.0188834000, 0.0320662000, 0.0292961000, -0.023850300, -0.198992200", \ - "0.0014839000, 0.0074254000, 0.0187644000, 0.0318976000, 0.0290313000, -0.024165000, -0.199391900", \ - "0.0014382000, 0.0073714000, 0.0186807000, 0.0317622000, 0.0289259000, -0.024306900, -0.199491800", \ - "0.0014372000, 0.0073900000, 0.0187078000, 0.0318183000, 0.0289228000, -0.024287400, -0.199478500", \ - "0.0014289000, 0.0073660000, 0.0186748000, 0.0317889000, 0.0288846000, -0.024345100, -0.199555500", \ - "0.0013969000, 0.0073039000, 0.0185652000, 0.0315695000, 0.0286040000, -0.024707900, -0.199942900", \ - "0.0013877000, 0.0073043000, 0.0185838000, 0.0316912000, 0.0288308000, -0.024314700, -0.199571900"); - } - related_pin : "SET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.1803690000; - max_transition : 1.5066880000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.2801939000, 0.2913679000, 0.3149178000, 0.3609425000, 0.4430541000, 0.6042685000, 0.9950075000", \ - "0.2850269000, 0.2960587000, 0.3196169000, 0.3656083000, 0.4477326000, 0.6089556000, 1.0001733000", \ - "0.2960709000, 0.3072132000, 0.3307795000, 0.3767820000, 0.4589130000, 0.6201117000, 1.0112823000", \ - "0.3217772000, 0.3329191000, 0.3564801000, 0.4024831000, 0.4846150000, 0.6458243000, 1.0369494000", \ - "0.3720550000, 0.3831412000, 0.4066584000, 0.4526522000, 0.5347903000, 0.6960258000, 1.0869641000", \ - "0.4457553000, 0.4569475000, 0.4805260000, 0.5265827000, 0.6087826000, 0.7700820000, 1.1610845000", \ - "0.5397547000, 0.5506977000, 0.5744831000, 0.6205961000, 0.7028345000, 0.8641552000, 1.2549326000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.2621668000, 0.2705042000, 0.2887195000, 0.3293932000, 0.4269258000, 0.6725829000, 1.3229010000", \ - "0.2669938000, 0.2753321000, 0.2935389000, 0.3342146000, 0.4317502000, 0.6769861000, 1.3312409000", \ - "0.2779885000, 0.2863356000, 0.3045379000, 0.3452123000, 0.4427489000, 0.6879392000, 1.3390505000", \ - "0.3042192000, 0.3124491000, 0.3307187000, 0.3713582000, 0.4688910000, 0.7141418000, 1.3650834000", \ - "0.3544241000, 0.3625481000, 0.3808329000, 0.4214999000, 0.5190356000, 0.7640359000, 1.4136463000", \ - "0.4265178000, 0.4347550000, 0.4530190000, 0.4936721000, 0.5912384000, 0.8364932000, 1.4869393000", \ - "0.5162356000, 0.5244432000, 0.5427063000, 0.5834131000, 0.6810116000, 0.9264775000, 1.5771109000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.0421445000, 0.0499999000, 0.0670100000, 0.1008243000, 0.1663329000, 0.3369760000, 0.8388116000", \ - "0.0426694000, 0.0500898000, 0.0669857000, 0.1010925000, 0.1661103000, 0.3381653000, 0.8405711000", \ - "0.0427111000, 0.0500388000, 0.0669775000, 0.1007115000, 0.1662680000, 0.3375670000, 0.8365355000", \ - "0.0427221000, 0.0500238000, 0.0669933000, 0.1007455000, 0.1662450000, 0.3375202000, 0.8413555000", \ - "0.0424386000, 0.0500185000, 0.0670607000, 0.1011343000, 0.1663555000, 0.3372504000, 0.8424421000", \ - "0.0423474000, 0.0502175000, 0.0672550000, 0.1010150000, 0.1664328000, 0.3375063000, 0.8433959000", \ - "0.0435522000, 0.0505703000, 0.0675121000, 0.1012656000, 0.1664641000, 0.3387712000, 0.8378194000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.0286096000, 0.0356563000, 0.0532276000, 0.1016473000, 0.2280863000, 0.5728754000, 1.5066877000", \ - "0.0286093000, 0.0356565000, 0.0532245000, 0.1016455000, 0.2281485000, 0.5723984000, 1.4995378000", \ - "0.0286165000, 0.0356731000, 0.0533971000, 0.1016505000, 0.2281803000, 0.5725642000, 1.4997060000", \ - "0.0284546000, 0.0356605000, 0.0532773000, 0.1017352000, 0.2278721000, 0.5723976000, 1.5006036000", \ - "0.0284471000, 0.0355717000, 0.0532645000, 0.1017246000, 0.2281778000, 0.5726177000, 1.5052786000", \ - "0.0285003000, 0.0356979000, 0.0533096000, 0.1018004000, 0.2280056000, 0.5725336000, 1.5062677000", \ - "0.0285711000, 0.0357418000, 0.0534065000, 0.1017679000, 0.2282069000, 0.5719134000, 1.5036947000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.2951353000, 0.3030398000, 0.3195708000, 0.3532448000, 0.4203455000, 0.5703255000, 0.9592946000", \ - "0.3002088000, 0.3079456000, 0.3245522000, 0.3581761000, 0.4251658000, 0.5749955000, 0.9633012000", \ - "0.3132475000, 0.3210696000, 0.3376679000, 0.3713086000, 0.4381734000, 0.5879793000, 0.9769053000", \ - "0.3462942000, 0.3541308000, 0.3706729000, 0.4042820000, 0.4711012000, 0.6208702000, 1.0099076000", \ - "0.4221628000, 0.4300042000, 0.4465405000, 0.4801460000, 0.5469264000, 0.6966486000, 1.0855538000", \ - "0.5774249000, 0.5851892000, 0.6017459000, 0.6353336000, 0.7020343000, 0.8516946000, 1.2401883000", \ - "0.8515358000, 0.8602754000, 0.8785801000, 0.9146466000, 0.9835961000, 1.1343705000, 1.5232372000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013340400, 0.0035593200, 0.0094965500, 0.0253375000, 0.0676025000, 0.1803690000"); - values("0.0270731000, 0.0328078000, 0.0459467000, 0.0751492000, 0.1412375000, 0.3215436000, 0.8327689000", \ - "0.0272714000, 0.0327402000, 0.0459856000, 0.0750930000, 0.1406074000, 0.3214468000, 0.8361533000", \ - "0.0275337000, 0.0327806000, 0.0458927000, 0.0749928000, 0.1407491000, 0.3223243000, 0.8332232000", \ - "0.0269539000, 0.0328355000, 0.0459472000, 0.0749257000, 0.1404206000, 0.3223579000, 0.8388603000", \ - "0.0269474000, 0.0328278000, 0.0457437000, 0.0749248000, 0.1405119000, 0.3213798000, 0.8327052000", \ - "0.0267804000, 0.0327456000, 0.0457247000, 0.0745378000, 0.1404555000, 0.3210391000, 0.8363680000", \ - "0.0316989000, 0.0373255000, 0.0508724000, 0.0797710000, 0.1439258000, 0.3220610000, 0.8408956000"); - } - related_pin : "SET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("SCD") { - capacitance : 0.0017350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027510000, 0.0027452000, 0.0027315000, 0.0027377000, 0.0027520000, 0.0027848000, 0.0028604000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002570200, -0.002572000, -0.002576200, -0.002585900, -0.002608200, -0.002659600, -0.002778000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018010000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3535625000, 0.5311667000, 0.8306458000", \ - "0.2247865000, 0.4023906000, 0.7018698000", \ - "0.1303854000, 0.3092103000, 0.6099102000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1692363000, 0.3089987000, 0.4729798000", \ - "0.1075990000, 0.2436992000, 0.3954733000", \ - "0.0962057000, 0.2286439000, 0.3755351000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.156691400, -0.330633500, -0.564194600", \ - "-0.073081400, -0.249464800, -0.517205700", \ - "-0.005535800, -0.181919300, -0.463087900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.123732400, -0.257391300, -0.398179000", \ - "-0.082847000, -0.214064500, -0.354852200", \ - "-0.079998700, -0.211216100, -0.349562500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0035260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033880000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112379000, 0.0111860000, 0.0110664000, 0.0111544000, 0.0113571000, 0.0118245000, 0.0129017000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000149600, -0.000218400, -0.000377200, -0.000311900, -0.000161500, 0.0001853000, 0.0009847000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2949688000, 0.4774557000, 0.7854798000", \ - "0.1649720000, 0.3474590000, 0.6567038000", \ - "0.0705710000, 0.2530580000, 0.5623027000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3535625000, 0.4469381000, 0.5071595000", \ - "0.2247865000, 0.3181621000, 0.3796042000", \ - "0.1291647000, 0.2237611000, 0.2852031000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.127394500, -0.303778000, -0.548325500", \ - "-0.030356800, -0.209181600, -0.489129600", \ - "0.0481751000, -0.134311900, -0.421584000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.168898400, -0.269598300, -0.333481800", \ - "-0.075522800, -0.175002000, -0.238885400", \ - "0.0017884000, -0.097690800, -0.164015600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0033440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033180000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053416000, 0.0053792000, 0.0054658000, 0.0054698000, 0.0054791000, 0.0055004000, 0.0055494000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-7.339774e-05, -0.000178800, -0.000421800, -0.000411400, -0.000387700, -0.000332900, -0.000206600"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033710000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.149367200, -0.098716100, -0.115399100", \ - "-0.292791700, -0.242140600, -0.260044300", \ - "-0.409165400, -0.362176400, -0.377638700"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1692363000, 0.1210267000, 0.1401510000", \ - "0.3089987000, 0.2620098000, 0.2786927000", \ - "0.4229310000, 0.3783835000, 0.3926250000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2214146000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfsbp_2") { - leakage_power () { - value : 0.0202315000; - when : "!CLK&D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0212735000; - when : "CLK&D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0174230000; - when : "CLK&D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0157971000; - when : "!CLK&D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0156835000; - when : "CLK&D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0215369000; - when : "CLK&!D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0214103000; - when : "!CLK&!D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0212967000; - when : "CLK&!D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0216724000; - when : "CLK&!D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0210113000; - when : "!CLK&D&SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0208977000; - when : "CLK&D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0129736000; - when : "!CLK&D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0162449000; - when : "!CLK&!D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0210424000; - when : "!CLK&!D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0167518000; - when : "!CLK&!D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0163006000; - when : "!CLK&!D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0116098000; - when : "!CLK&D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0172230000; - when : "!CLK&!D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0166961000; - when : "!CLK&!D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0209867000; - when : "!CLK&!D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0212982000; - when : "!CLK&D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0168241000; - when : "!CLK&D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0206305000; - when : "!CLK&!D&SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0163811000; - when : "!CLK&D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0150173000; - when : "!CLK&D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0212425000; - when : "!CLK&D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0134806000; - when : "CLK&D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0155723000; - when : "CLK&!D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0112816000; - when : "CLK&!D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0110194000; - when : "!CLK&!D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0164194000; - when : "CLK&!D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0167951000; - when : "CLK&!D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0217927000; - when : "CLK&D&!SCD&SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0160593000; - when : "CLK&D&SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0171609000; - when : "!CLK&D&!SCD&!SCE&SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0170473000; - when : "CLK&D&!SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0158280000; - when : "CLK&D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0108305000; - when : "CLK&!D&!SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0177300000; - when : "CLK&!D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0157612000; - when : "!CLK&!D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0211612000; - when : "CLK&!D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0173311000; - when : "CLK&D&SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0160169000; - when : "!CLK&D&!SCD&SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0214169000; - when : "CLK&D&!SCD&SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0121168000; - when : "CLK&D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0114705000; - when : "!CLK&!D&SCD&!SCE&SET_B&!Q&Q_N"; - } - leakage_power () { - value : 0.0168705000; - when : "CLK&!D&SCD&!SCE&!SET_B&Q&!Q_N"; - } - leakage_power () { - value : 0.0172463000; - when : "CLK&!D&SCD&!SCE&SET_B&Q&!Q_N"; - } - area : 38.787200000; - cell_footprint : "sky130_fd_sc_hd__sdfsbp"; - cell_leakage_power : 0.0172888500; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0019810000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0018940000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0232941000, 0.0231591000, 0.0228478000, 0.0228994000, 0.0230186000, 0.0232933000, 0.0239265000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184940000, 0.0183811000, 0.0181208000, 0.0181370000, 0.0181748000, 0.0182617000, 0.0184622000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020680000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3235761000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2972119000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018570000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091227000, 0.0089921000, 0.0086912000, 0.0087563000, 0.0089065000, 0.0092529000, 0.0100513000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026723000, 0.0026254000, 0.0025175000, 0.0025386000, 0.0025873000, 0.0026998000, 0.0029590000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019490000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2949688000, 0.4933249000, 0.8391908000", \ - "0.1637513000, 0.3633281000, 0.7091940000", \ - "0.0693503000, 0.2689271000, 0.6123515000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1448223000, 0.2858053000, 0.4253724000", \ - "0.0807435000, 0.2119609000, 0.3332174000", \ - "0.0656882000, 0.1932435000, 0.3035137000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.116408200, -0.307440100, -0.555649800", \ - "-0.019370400, -0.215285200, -0.517205700", \ - "0.0579408000, -0.139194700, -0.458205100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.099318400, -0.232977200, -0.339585300", \ - "-0.055991500, -0.182326200, -0.290154900", \ - "-0.050701800, -0.175815800, -0.281203100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("-0.006149000, -0.000985300, 0.0097224000, 0.0214318000, 0.0083352000, -0.088849500, -0.411526300", \ - "-0.006095500, -0.000933400, 0.0097602000, 0.0214433000, 0.0083331000, -0.088854000, -0.411491700", \ - "-0.005968800, -0.000812400, 0.0098648000, 0.0215434000, 0.0083972000, -0.088789800, -0.411443800", \ - "-0.005992100, -0.000864200, 0.0097568000, 0.0213303000, 0.0080833000, -0.089159300, -0.411846100", \ - "-0.006016500, -0.000897200, 0.0097027000, 0.0212400000, 0.0079571000, -0.089306300, -0.412018300", \ - "-0.006056100, -0.000931500, 0.0096860000, 0.0212382000, 0.0079897000, -0.089260400, -0.411952400", \ - "-0.006085200, -0.000839700, 0.0100474000, 0.0220942000, 0.0088481000, -0.088506300, -0.411117200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("-0.007753700, -0.005006200, 0.0024306000, 0.0209792000, 0.0649797000, 0.1796027000, 0.5090404000", \ - "-0.007698600, -0.004950800, 0.0024805000, 0.0210545000, 0.0650551000, 0.1795599000, 0.5087377000", \ - "-0.007576200, -0.004846500, 0.0025591000, 0.0210535000, 0.0649999000, 0.1796219000, 0.5087998000", \ - "-0.007600900, -0.004893000, 0.0024326000, 0.0208530000, 0.0646686000, 0.1790592000, 0.5064816000", \ - "-0.007631000, -0.004945600, 0.0023282000, 0.0206657000, 0.0644801000, 0.1788178000, 0.5077396000", \ - "-0.007676900, -0.004997500, 0.0022842000, 0.0206082000, 0.0643227000, 0.1787847000, 0.5079870000", \ - "-0.007611900, -0.004662800, 0.0030365000, 0.0214655000, 0.0648279000, 0.1792304000, 0.5089901000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014596270, 0.0042610240, 0.0124390100, 0.0363126500, 0.1060059000, 0.3094581000"); - values("-0.000413600, 0.0036477000, 0.0140242000, 0.0370548000, 0.0853329000, 0.2024456000, 0.5317523000", \ - "-0.000433700, 0.0036122000, 0.0139319000, 0.0368823000, 0.0849533000, 0.2024712000, 0.5303035000", \ - "-0.000459500, 0.0035652000, 0.0138600000, 0.0367632000, 0.0847039000, 0.2027017000, 0.5327611000", \ - "-0.000456200, 0.0035797000, 0.0138734000, 0.0368228000, 0.0848559000, 0.2021718000, 0.5302617000", \ - "-0.000453300, 0.0035920000, 0.0139302000, 0.0369097000, 0.0849587000, 0.2025141000, 0.5322592000", \ - "-0.000476900, 0.0035436000, 0.0138146000, 0.0367234000, 0.0846802000, 0.2017079000, 0.5330266000", \ - "-0.000428900, 0.0036890000, 0.0140432000, 0.0369596000, 0.0854061000, 0.2034250000, 0.5314218000"); - } - } - max_capacitance : 0.3094580000; - max_transition : 1.5022430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.3707684000, 0.3756260000, 0.3864742000, 0.4084978000, 0.4548853000, 0.5700559000, 0.8987404000", \ - "0.3756024000, 0.3804449000, 0.3912821000, 0.4133035000, 0.4597237000, 0.5750369000, 0.9048849000", \ - "0.3865785000, 0.3914406000, 0.4022683000, 0.4243154000, 0.4706756000, 0.5858739000, 0.9151486000", \ - "0.4127607000, 0.4176258000, 0.4284839000, 0.4505058000, 0.4968671000, 0.6120546000, 0.9404817000", \ - "0.4626890000, 0.4675492000, 0.4784034000, 0.5004240000, 0.5467929000, 0.6619958000, 0.9903768000", \ - "0.5350819000, 0.5399000000, 0.5506960000, 0.5728127000, 0.6191735000, 0.7344895000, 1.0638065000", \ - "0.6250409000, 0.6298829000, 0.6407156000, 0.6627316000, 0.7091505000, 0.8243808000, 1.1530454000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.4427834000, 0.4494803000, 0.4640714000, 0.4956755000, 0.5763754000, 0.8082816000, 1.4870424000", \ - "0.4474427000, 0.4541535000, 0.4687331000, 0.5003051000, 0.5809753000, 0.8127577000, 1.4894902000", \ - "0.4586203000, 0.4653191000, 0.4799099000, 0.5115416000, 0.5922798000, 0.8242347000, 1.5033089000", \ - "0.4843775000, 0.4909335000, 0.5055416000, 0.5371806000, 0.6181170000, 0.8502170000, 1.5281356000", \ - "0.5345122000, 0.5410459000, 0.5556525000, 0.5873237000, 0.6682406000, 0.9004188000, 1.5781499000", \ - "0.6085155000, 0.6151096000, 0.6297913000, 0.6614722000, 0.7422747000, 0.9743312000, 1.6517395000", \ - "0.7018938000, 0.7086086000, 0.7232049000, 0.7547297000, 0.8356958000, 1.0679192000, 1.7441931000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0208241000, 0.0239367000, 0.0311027000, 0.0487692000, 0.0961903000, 0.2407647000, 0.6833335000", \ - "0.0208411000, 0.0236066000, 0.0307909000, 0.0488795000, 0.0959097000, 0.2414171000, 0.6826898000", \ - "0.0207982000, 0.0238701000, 0.0309366000, 0.0484505000, 0.0957008000, 0.2404534000, 0.6816617000", \ - "0.0208445000, 0.0239229000, 0.0310537000, 0.0484479000, 0.0957912000, 0.2404878000, 0.6853149000", \ - "0.0208288000, 0.0239062000, 0.0310613000, 0.0484823000, 0.0956913000, 0.2404359000, 0.6854896000", \ - "0.0205547000, 0.0236096000, 0.0308917000, 0.0486923000, 0.0959702000, 0.2415297000, 0.6789244000", \ - "0.0207625000, 0.0236095000, 0.0308109000, 0.0488897000, 0.0959500000, 0.2399836000, 0.6768815000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0281233000, 0.0324328000, 0.0437787000, 0.0774126000, 0.1875066000, 0.5201167000, 1.4992310000", \ - "0.0281322000, 0.0323758000, 0.0437915000, 0.0774253000, 0.1873103000, 0.5201916000, 1.4948047000", \ - "0.0280981000, 0.0325062000, 0.0437353000, 0.0773699000, 0.1874405000, 0.5205830000, 1.5003342000", \ - "0.0281276000, 0.0322406000, 0.0438386000, 0.0773650000, 0.1875341000, 0.5197388000, 1.4954021000", \ - "0.0281474000, 0.0322421000, 0.0438794000, 0.0774032000, 0.1875832000, 0.5189284000, 1.4992676000", \ - "0.0280521000, 0.0322366000, 0.0437434000, 0.0772929000, 0.1871051000, 0.5199954000, 1.4980917000", \ - "0.0280509000, 0.0326651000, 0.0435628000, 0.0773808000, 0.1877090000, 0.5202959000, 1.4951194000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.4055168000, 0.4112504000, 0.4243753000, 0.4547199000, 0.5352041000, 0.7669468000, 1.4446639000", \ - "0.4105710000, 0.4161498000, 0.4292684000, 0.4597018000, 0.5400122000, 0.7720039000, 1.4518474000", \ - "0.4237075000, 0.4293997000, 0.4425187000, 0.4729222000, 0.5532748000, 0.7852870000, 1.4639682000", \ - "0.4566297000, 0.4623620000, 0.4753950000, 0.5057672000, 0.5863809000, 0.8176123000, 1.4998965000", \ - "0.5328217000, 0.5385739000, 0.5516274000, 0.5819146000, 0.6625189000, 0.8939374000, 1.5708276000", \ - "0.6889734000, 0.6945684000, 0.7076877000, 0.7380864000, 0.8185898000, 1.0508280000, 1.7257475000", \ - "0.9756181000, 0.9814934000, 0.9946647000, 1.0251904000, 1.1058349000, 1.3373949000, 2.0158184000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014596300, 0.0042610200, 0.0124390000, 0.0363126000, 0.1060060000, 0.3094580000"); - values("0.0231955000, 0.0274766000, 0.0392178000, 0.0746576000, 0.1860730000, 0.5196598000, 1.5017352000", \ - "0.0229242000, 0.0274575000, 0.0391599000, 0.0749370000, 0.1866602000, 0.5214826000, 1.4996132000", \ - "0.0229629000, 0.0271888000, 0.0391150000, 0.0749765000, 0.1864751000, 0.5205982000, 1.5012837000", \ - "0.0230209000, 0.0273721000, 0.0391408000, 0.0746143000, 0.1864928000, 0.5204204000, 1.5020433000", \ - "0.0231428000, 0.0272883000, 0.0391835000, 0.0747688000, 0.1862869000, 0.5202759000, 1.4996998000", \ - "0.0230189000, 0.0274070000, 0.0391175000, 0.0747563000, 0.1869738000, 0.5204996000, 1.5022427000", \ - "0.0239115000, 0.0279241000, 0.0397507000, 0.0752782000, 0.1864759000, 0.5187524000, 1.4970163000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.006165400, -0.001021000, 0.0095723000, 0.0210070000, 0.0067972000, -0.090992100, -0.418741300", \ - "-0.006108000, -0.000978700, 0.0096184000, 0.0210601000, 0.0068573000, -0.090988300, -0.418709700", \ - "-0.005986300, -0.000860600, 0.0096862000, 0.0210762000, 0.0068305000, -0.091018800, -0.418771000", \ - "-0.006012100, -0.000921800, 0.0095764000, 0.0208612000, 0.0065218000, -0.091391800, -0.419156200", \ - "-0.006041000, -0.000963700, 0.0094747000, 0.0206585000, 0.0062259000, -0.091699000, -0.419465100", \ - "-0.006085700, -0.001011400, 0.0094258000, 0.0206168000, 0.0061202000, -0.091757000, -0.419540700", \ - "-0.006118400, -0.000925700, 0.0097941000, 0.0214571000, 0.0075873000, -0.091188700, -0.418890400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.007646300, -0.004718400, 0.0029412000, 0.0215097000, 0.0659992000, 0.1818978000, 0.5177876000", \ - "-0.007600000, -0.004695100, 0.0029456000, 0.0214541000, 0.0658911000, 0.1819079000, 0.5158556000", \ - "-0.007475900, -0.004571400, 0.0030335000, 0.0214827000, 0.0659105000, 0.1827531000, 0.5137213000", \ - "-0.007493900, -0.004617800, 0.0029546000, 0.0213882000, 0.0657095000, 0.1816748000, 0.5149731000", \ - "-0.007521300, -0.004657000, 0.0028625000, 0.0212425000, 0.0654957000, 0.1814372000, 0.5167127000", \ - "-0.007561100, -0.004698300, 0.0028493000, 0.0212433000, 0.0655452000, 0.1823979000, 0.5133638000", \ - "-0.007587400, -0.004585400, 0.0032897000, 0.0220756000, 0.0663610000, 0.1831224000, 0.5139926000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("0.0011188000, 0.0074787000, 0.0209284000, 0.0370644000, 0.0274330000, -0.068377400, -0.395068700", \ - "0.0010961000, 0.0074453000, 0.0208256000, 0.0368837000, 0.0271571000, -0.068687500, -0.395408900", \ - "0.0010702000, 0.0073983000, 0.0207587000, 0.0367613000, 0.0270149000, -0.068871900, -0.395615400", \ - "0.0010728000, 0.0074153000, 0.0207987000, 0.0368257000, 0.0271082000, -0.068745500, -0.395477800", \ - "0.0010761000, 0.0074255000, 0.0208268000, 0.0369165000, 0.0272524000, -0.068568700, -0.395297400", \ - "0.0010505000, 0.0073732000, 0.0207343000, 0.0367261000, 0.0269969000, -0.068936300, -0.395741100", \ - "0.0010547000, 0.0074257000, 0.0208393000, 0.0369671000, 0.0274084000, -0.068231100, -0.395079700"); - } - related_pin : "SET_B"; - rise_power ("scalar") { - values("0.0000000000"); - } - } - max_capacitance : 0.3140360000; - max_transition : 1.5046670000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3088373000, 0.3180753000, 0.3387182000, 0.3806701000, 0.4597788000, 0.6108490000, 0.9743381000", \ - "0.3136552000, 0.3227986000, 0.3434874000, 0.3853742000, 0.4644659000, 0.6155710000, 0.9791241000", \ - "0.3247607000, 0.3339821000, 0.3546248000, 0.3965845000, 0.4756973000, 0.6267620000, 0.9902273000", \ - "0.3505951000, 0.3595950000, 0.3803793000, 0.4222719000, 0.5014017000, 0.6525012000, 1.0156893000", \ - "0.4007363000, 0.4097958000, 0.4305114000, 0.4724177000, 0.5515042000, 0.7026224000, 1.0661518000", \ - "0.4746776000, 0.4838359000, 0.5045206000, 0.5464400000, 0.6255882000, 0.7767451000, 1.1403416000", \ - "0.5682847000, 0.5774355000, 0.5981638000, 0.6400416000, 0.7191435000, 0.8703632000, 1.2336836000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.2745884000, 0.2816684000, 0.2979602000, 0.3346453000, 0.4239001000, 0.6607102000, 1.3469922000", \ - "0.2793369000, 0.2861742000, 0.3026160000, 0.3393900000, 0.4284962000, 0.6653995000, 1.3478970000", \ - "0.2903916000, 0.2974385000, 0.3137880000, 0.3504537000, 0.4396739000, 0.6766091000, 1.3599838000", \ - "0.3166193000, 0.3235322000, 0.3399903000, 0.3766772000, 0.4658882000, 0.7027864000, 1.3900440000", \ - "0.3668937000, 0.3739051000, 0.3902810000, 0.4269257000, 0.5161194000, 0.7530560000, 1.4354327000", \ - "0.4388603000, 0.4457574000, 0.4622372000, 0.4989308000, 0.5881595000, 0.8251427000, 1.5084148000", \ - "0.5285951000, 0.5355787000, 0.5520903000, 0.5887705000, 0.6780107000, 0.9150834000, 1.5968425000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0434041000, 0.0492965000, 0.0626100000, 0.0915570000, 0.1489516000, 0.2902088000, 0.7366654000", \ - "0.0429307000, 0.0490593000, 0.0626955000, 0.0914958000, 0.1488482000, 0.2905568000, 0.7405128000", \ - "0.0434122000, 0.0492692000, 0.0626206000, 0.0915659000, 0.1489243000, 0.2909648000, 0.7382328000", \ - "0.0430064000, 0.0495523000, 0.0627134000, 0.0914539000, 0.1489833000, 0.2903856000, 0.7375163000", \ - "0.0431418000, 0.0494820000, 0.0626688000, 0.0914461000, 0.1489675000, 0.2902557000, 0.7405495000", \ - "0.0430581000, 0.0492388000, 0.0630178000, 0.0917444000, 0.1490492000, 0.2904061000, 0.7396129000", \ - "0.0432187000, 0.0493522000, 0.0629840000, 0.0918547000, 0.1491040000, 0.2907685000, 0.7360971000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0271834000, 0.0328036000, 0.0468913000, 0.0850450000, 0.1958978000, 0.5225115000, 1.5003901000", \ - "0.0271635000, 0.0327551000, 0.0472013000, 0.0850958000, 0.1958354000, 0.5217399000, 1.4991507000", \ - "0.0271887000, 0.0327957000, 0.0468351000, 0.0851999000, 0.1955341000, 0.5211745000, 1.4964614000", \ - "0.0270470000, 0.0329642000, 0.0471696000, 0.0850739000, 0.1955398000, 0.5215131000, 1.5046666000", \ - "0.0268851000, 0.0324994000, 0.0469447000, 0.0850929000, 0.1958365000, 0.5208795000, 1.5021542000", \ - "0.0270710000, 0.0329660000, 0.0471724000, 0.0851220000, 0.1955388000, 0.5214610000, 1.4955229000", \ - "0.0272681000, 0.0328869000, 0.0473372000, 0.0851285000, 0.1957144000, 0.5216805000, 1.4966476000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3055482000, 0.3119931000, 0.3264204000, 0.3559724000, 0.4164454000, 0.5487778000, 0.9044215000", \ - "0.3106902000, 0.3170510000, 0.3313468000, 0.3609756000, 0.4212629000, 0.5535016000, 0.9095147000", \ - "0.3240898000, 0.3304192000, 0.3448386000, 0.3743811000, 0.4345307000, 0.5667019000, 0.9227561000", \ - "0.3569004000, 0.3632162000, 0.3776576000, 0.4072005000, 0.4673117000, 0.5994134000, 0.9552650000", \ - "0.4331004000, 0.4394735000, 0.4538663000, 0.4834432000, 0.5434888000, 0.6755371000, 1.0315070000", \ - "0.5893352000, 0.5956843000, 0.6101220000, 0.6395754000, 0.6996019000, 0.8316058000, 1.1869186000", \ - "0.8684997000, 0.8756029000, 0.8917398000, 0.9239625000, 0.9870057000, 1.1207600000, 1.4766259000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0265215000, 0.0303511000, 0.0409966000, 0.0635187000, 0.1173144000, 0.2640226000, 0.7274553000", \ - "0.0262012000, 0.0306402000, 0.0403632000, 0.0634385000, 0.1170197000, 0.2638285000, 0.7318304000", \ - "0.0261363000, 0.0303724000, 0.0410053000, 0.0635236000, 0.1168793000, 0.2637074000, 0.7296665000", \ - "0.0262224000, 0.0303821000, 0.0409977000, 0.0634887000, 0.1167722000, 0.2642192000, 0.7303945000", \ - "0.0264001000, 0.0306629000, 0.0403439000, 0.0634039000, 0.1166554000, 0.2636164000, 0.7266609000", \ - "0.0262868000, 0.0304109000, 0.0404191000, 0.0631265000, 0.1164411000, 0.2633210000, 0.7287931000", \ - "0.0305014000, 0.0351891000, 0.0459430000, 0.0690512000, 0.1211738000, 0.2654762000, 0.7306951000"); - } - related_pin : "SET_B"; - timing_sense : "positive_unate"; - timing_type : "clear"; - } - } - pin ("SCD") { - capacitance : 0.0017310000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027568000, 0.0027509000, 0.0027373000, 0.0027417000, 0.0027521000, 0.0027760000, 0.0028311000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002554400, -0.002559500, -0.002571100, -0.002581100, -0.002604000, -0.002656800, -0.002778300"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017980000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3572246000, 0.5348288000, 0.8355286000", \ - "0.2272279000, 0.4060527000, 0.7055319000", \ - "0.1340475000, 0.3128724000, 0.6135723000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1716777000, 0.3114401000, 0.4766419000", \ - "0.1088197000, 0.2449199000, 0.3966940000", \ - "0.0962057000, 0.2298646000, 0.3767559000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.146925800, -0.319647100, -0.547104800", \ - "-0.065757200, -0.242140600, -0.504998700", \ - "0.0030091000, -0.174595100, -0.452101600"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.121291000, -0.254949900, -0.394516900", \ - "-0.081626300, -0.212843800, -0.353631500", \ - "-0.079998700, -0.209995400, -0.348341800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0035350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0113879000, 0.0112649000, 0.0109813000, 0.0110834000, 0.0113189000, 0.0118615000, 0.0131122000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000192800, -0.000280500, -0.000482800, -0.000416500, -0.000263300, 8.9748537e-05, 0.0009036000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036670000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3010723000, 0.4823385000, 0.7928040000", \ - "0.1698548000, 0.3523418000, 0.6628073000", \ - "0.0766745000, 0.2591615000, 0.5684063000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3547832000, 0.4481589000, 0.5083802000", \ - "0.2260072000, 0.3193828000, 0.3783835000", \ - "0.1303854000, 0.2249818000, 0.2852031000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.121291000, -0.296453800, -0.534897800", \ - "-0.026694700, -0.204298800, -0.481805300", \ - "0.0518372000, -0.129429000, -0.415480500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.156691400, -0.257391300, -0.320054100", \ - "-0.068198600, -0.166457000, -0.229119800", \ - "0.0091126000, -0.089145800, -0.153029300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0033290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053352000, 0.0053508000, 0.0053865000, 0.0053900000, 0.0053981000, 0.0054167000, 0.0054596000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002533000, 0.0001204000, -0.000186000, -0.000178000, -0.000159600, -0.000117200, -1.9383644e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033920000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.145705100, -0.092612600, -0.105633500", \ - "-0.290350300, -0.237257800, -0.250278600", \ - "-0.406724000, -0.356072900, -0.366652300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1692363000, 0.1210267000, 0.1401510000", \ - "0.3089987000, 0.2607891000, 0.2786927000", \ - "0.4241517000, 0.3783835000, 0.3938457000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2741431000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfstp_1") { - leakage_power () { - value : 0.0138127000; - when : "!CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0096871000; - when : "!CLK&D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0083459000; - when : "!CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0144216000; - when : "!CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0134044000; - when : "!CLK&D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0139271000; - when : "CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0158753000; - when : "CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0117148000; - when : "CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0114491000; - when : "!CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0097105000; - when : "CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0100873000; - when : "CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0149658000; - when : "CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0093890000; - when : "CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0104750000; - when : "!CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0103534000; - when : "CLK&D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0161432000; - when : "CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0112646000; - when : "CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0180528000; - when : "CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0160598000; - when : "!CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0143212000; - when : "CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0176445000; - when : "CLK&D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0163277000; - when : "!CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0145891000; - when : "CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0125860000; - when : "CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0118993000; - when : "!CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0101607000; - when : "CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0105374000; - when : "CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0144475000; - when : "CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0107302000; - when : "CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0091338000; - when : "!CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0090122000; - when : "CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0146980000; - when : "CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0146006000; - when : "!CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0144790000; - when : "CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0148558000; - when : "CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0141923000; - when : "!CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0140707000; - when : "CLK&D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0134196000; - when : "!CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0095431000; - when : "!CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0142119000; - when : "!CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0100514000; - when : "!CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0096012000; - when : "!CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0120785000; - when : "!CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0175453000; - when : "!CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0099932000; - when : "!CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0141538000; - when : "!CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0144798000; - when : "!CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0171370000; - when : "!CLK&D&SCD&SCE&SET_B&!Q"; - } - area : 33.782400000; - cell_footprint : "sky130_fd_sc_hd__sdfstp"; - cell_leakage_power : 0.0129091700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0019500000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0018560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0233924000, 0.0233070000, 0.0231102000, 0.0231644000, 0.0232896000, 0.0235781000, 0.0242433000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184459000, 0.0183851000, 0.0182450000, 0.0182639000, 0.0183076000, 0.0184085000, 0.0186409000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020430000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3147880000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1851638000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091714000, 0.0090421000, 0.0087439000, 0.0088145000, 0.0089775000, 0.0093533000, 0.0102194000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026856000, 0.0025983000, 0.0023971000, 0.0024333000, 0.0025171000, 0.0027100000, 0.0031548000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2839824000, 0.4823385000, 0.8269837000", \ - "0.1552064000, 0.3547832000, 0.6969870000", \ - "0.0608053000, 0.2603821000, 0.6001445000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1399395000, 0.2797018000, 0.4156068000", \ - "0.0783021000, 0.2082988000, 0.3283346000", \ - "0.0632467000, 0.1895814000, 0.2998515000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.128615200, -0.324529900, -0.592270900", \ - "-0.030356800, -0.226271500, -0.535516300", \ - "0.0493958000, -0.150181000, -0.466750000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.102980500, -0.236639300, -0.346909500", \ - "-0.057212200, -0.184767600, -0.292596300", \ - "-0.050701800, -0.177036500, -0.282423800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0239779000, 0.0230646000, 0.0204570000, 0.0120421000, -0.011900900, -0.075697900, -0.244065600", \ - "0.0239452000, 0.0230293000, 0.0204133000, 0.0119970000, -0.011949500, -0.075742600, -0.244115500", \ - "0.0239347000, 0.0230029000, 0.0203920000, 0.0119749000, -0.011970900, -0.075766400, -0.244133100", \ - "0.0235479000, 0.0226220000, 0.0200004000, 0.0115910000, -0.012362900, -0.076157700, -0.244524700", \ - "0.0233095000, 0.0223828000, 0.0197663000, 0.0113511000, -0.012608700, -0.076394600, -0.244763800", \ - "0.0233859000, 0.0224325000, 0.0198192000, 0.0113860000, -0.012571700, -0.076364200, -0.244748200", \ - "0.0258286000, 0.0246158000, 0.0212831000, 0.0122400000, -0.011928300, -0.075909200, -0.244283000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0248860000, 0.0265941000, 0.0307605000, 0.0405312000, 0.0646806000, 0.1284417000, 0.2937075000", \ - "0.0248766000, 0.0265868000, 0.0307532000, 0.0405238000, 0.0646811000, 0.1278958000, 0.2958613000", \ - "0.0246504000, 0.0263817000, 0.0305421000, 0.0403118000, 0.0644298000, 0.1274258000, 0.2945935000", \ - "0.0244073000, 0.0261120000, 0.0302918000, 0.0400440000, 0.0642010000, 0.1278348000, 0.2939049000", \ - "0.0240448000, 0.0257538000, 0.0299304000, 0.0396806000, 0.0638589000, 0.1267919000, 0.2936501000", \ - "0.0239500000, 0.0256187000, 0.0298433000, 0.0395767000, 0.0637156000, 0.1274000000, 0.2949624000", \ - "0.0262851000, 0.0276549000, 0.0312230000, 0.0404654000, 0.0642938000, 0.1275641000, 0.2930201000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529080, 0.0241224900, 0.0635748200, 0.1675515000"); - values("0.0581511000, 0.0597886000, 0.0637351000, 0.0731874000, 0.0974498000, 0.1605258000, 0.3286922000", \ - "0.0578934000, 0.0595173000, 0.0634523000, 0.0729181000, 0.0968966000, 0.1601550000, 0.3284048000", \ - "0.0576498000, 0.0592926000, 0.0632108000, 0.0726078000, 0.0969509000, 0.1605430000, 0.3268889000", \ - "0.0577398000, 0.0593811000, 0.0632899000, 0.0727095000, 0.0968017000, 0.1604515000, 0.3278875000", \ - "0.0577780000, 0.0594068000, 0.0633347000, 0.0728171000, 0.0968035000, 0.1606147000, 0.3280997000", \ - "0.0568425000, 0.0584935000, 0.0623931000, 0.0718582000, 0.0957962000, 0.1596291000, 0.3261326000", \ - "0.0577105000, 0.0590891000, 0.0626615000, 0.0718989000, 0.0964084000, 0.1597170000, 0.3277044000"); - } - } - max_capacitance : 0.1675510000; - max_transition : 1.4980020000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3000310000, 0.3051431000, 0.3161420000, 0.3390783000, 0.3914076000, 0.5247380000, 0.8772921000", \ - "0.3046121000, 0.3097695000, 0.3207092000, 0.3437074000, 0.3960473000, 0.5294558000, 0.8807626000", \ - "0.3159082000, 0.3210704000, 0.3319959000, 0.3549922000, 0.4073305000, 0.5407800000, 0.8933567000", \ - "0.3418898000, 0.3470491000, 0.3579967000, 0.3809328000, 0.4333256000, 0.5666482000, 0.9192849000", \ - "0.3918626000, 0.3970235000, 0.4080498000, 0.4309982000, 0.4833497000, 0.6165730000, 0.9678177000", \ - "0.4641218000, 0.4692677000, 0.4802074000, 0.5031743000, 0.5554496000, 0.6887765000, 1.0402348000", \ - "0.5533069000, 0.5584593000, 0.5694102000, 0.5923537000, 0.6446645000, 0.7781387000, 1.1308199000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3018733000, 0.3086825000, 0.3239931000, 0.3602182000, 0.4534756000, 0.6968104000, 1.3379053000", \ - "0.3065788000, 0.3133840000, 0.3286926000, 0.3649097000, 0.4581978000, 0.7014914000, 1.3438988000", \ - "0.3176374000, 0.3244529000, 0.3397226000, 0.3760527000, 0.4692936000, 0.7123364000, 1.3542584000", \ - "0.3438131000, 0.3506095000, 0.3659482000, 0.4021900000, 0.4952795000, 0.7388116000, 1.3799047000", \ - "0.3942105000, 0.4010226000, 0.4163332000, 0.4525597000, 0.5457568000, 0.7891619000, 1.4311944000", \ - "0.4670878000, 0.4739312000, 0.4891977000, 0.5255727000, 0.6187540000, 0.8621326000, 1.5024036000", \ - "0.5611722000, 0.5680091000, 0.5833314000, 0.6195555000, 0.7128219000, 0.9561443000, 1.5962475000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0170935000, 0.0209903000, 0.0305239000, 0.0542488000, 0.1180424000, 0.2951581000, 0.7701542000", \ - "0.0171064000, 0.0210511000, 0.0304588000, 0.0542391000, 0.1182238000, 0.2951641000, 0.7637370000", \ - "0.0171419000, 0.0210878000, 0.0305819000, 0.0543242000, 0.1182431000, 0.2948989000, 0.7690150000", \ - "0.0171443000, 0.0210596000, 0.0305078000, 0.0543568000, 0.1183366000, 0.2952761000, 0.7652165000", \ - "0.0171355000, 0.0210701000, 0.0306000000, 0.0544201000, 0.1181829000, 0.2950948000, 0.7629545000", \ - "0.0171196000, 0.0210108000, 0.0306581000, 0.0543545000, 0.1181788000, 0.2952377000, 0.7648827000", \ - "0.0171243000, 0.0210002000, 0.0305439000, 0.0542090000, 0.1183710000, 0.2950447000, 0.7588458000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0241617000, 0.0303726000, 0.0472315000, 0.0952354000, 0.2260285000, 0.5739112000, 1.4928319000", \ - "0.0241402000, 0.0303755000, 0.0472505000, 0.0952047000, 0.2259295000, 0.5741420000, 1.4916933000", \ - "0.0241588000, 0.0303307000, 0.0472557000, 0.0952537000, 0.2262679000, 0.5740324000, 1.4964399000", \ - "0.0242007000, 0.0303369000, 0.0472159000, 0.0952499000, 0.2263474000, 0.5727800000, 1.4958202000", \ - "0.0242082000, 0.0303900000, 0.0472312000, 0.0952450000, 0.2261799000, 0.5733997000, 1.4926982000", \ - "0.0241980000, 0.0303321000, 0.0473153000, 0.0948978000, 0.2264264000, 0.5727953000, 1.4972918000", \ - "0.0243314000, 0.0304303000, 0.0473664000, 0.0952548000, 0.2259355000, 0.5729731000, 1.4906115000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.3297399000, 0.3360833000, 0.3509119000, 0.3870598000, 0.4800230000, 0.7226136000, 1.3663757000", \ - "0.3350225000, 0.3413926000, 0.3561948000, 0.3920850000, 0.4850033000, 0.7276579000, 1.3717206000", \ - "0.3482881000, 0.3546567000, 0.3694660000, 0.4055348000, 0.4981362000, 0.7418441000, 1.3832891000", \ - "0.3810945000, 0.3874605000, 0.4022675000, 0.4382560000, 0.5311399000, 0.7748955000, 1.4184846000", \ - "0.4566498000, 0.4630147000, 0.4778183000, 0.5138560000, 0.6066133000, 0.8502705000, 1.4945523000", \ - "0.6102479000, 0.6166357000, 0.6314207000, 0.6675334000, 0.7600634000, 1.0037992000, 1.6449180000", \ - "0.8806673000, 0.8870844000, 0.9019399000, 0.9380940000, 1.0307779000, 1.2735900000, 1.9161586000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013177500, 0.0034729300, 0.0091529100, 0.0241225000, 0.0635748000, 0.1675510000"); - values("0.0215706000, 0.0280698000, 0.0457194000, 0.0949054000, 0.2263874000, 0.5735636000, 1.4939610000", \ - "0.0216156000, 0.0281101000, 0.0458034000, 0.0946274000, 0.2256515000, 0.5743401000, 1.4968886000", \ - "0.0215716000, 0.0280580000, 0.0457176000, 0.0943057000, 0.2254992000, 0.5756683000, 1.4948579000", \ - "0.0215654000, 0.0280495000, 0.0457336000, 0.0946040000, 0.2256750000, 0.5746121000, 1.4944789000", \ - "0.0215839000, 0.0280661000, 0.0457697000, 0.0944538000, 0.2256346000, 0.5764862000, 1.4980024000", \ - "0.0215317000, 0.0279863000, 0.0457935000, 0.0946880000, 0.2257249000, 0.5758513000, 1.4968867000", \ - "0.0219838000, 0.0284717000, 0.0458997000, 0.0944678000, 0.2260288000, 0.5728878000, 1.4970504000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SCD") { - capacitance : 0.0017320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027525000, 0.0027719000, 0.0028166000, 0.0028180000, 0.0028213000, 0.0028291000, 0.0028471000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002567400, -0.002611400, -0.002712700, -0.002715700, -0.002722200, -0.002737400, -0.002772400"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017980000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3474590000, 0.5250631000, 0.8245423000", \ - "0.2199036000, 0.3975078000, 0.6969870000", \ - "0.1255026000, 0.3043275000, 0.6038067000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1667949000, 0.3065573000, 0.4693177000", \ - "0.1063783000, 0.2412578000, 0.3930319000", \ - "0.0937643000, 0.2262025000, 0.3730937000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.165236300, -0.339178400, -0.580063800", \ - "-0.079184900, -0.256789100, -0.526971400", \ - "-0.009197900, -0.186802100, -0.469191400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.124953100, -0.258612000, -0.400620400", \ - "-0.082847000, -0.214064500, -0.356072900", \ - "-0.079998700, -0.209995400, -0.349562500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0035400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112964000, 0.0112478000, 0.0111358000, 0.0112239000, 0.0114274000, 0.0118964000, 0.0129776000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000154400, -0.000313500, -0.000680100, -0.000592100, -0.000389300, 7.8424126e-05, 0.0011564000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036780000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2888652000, 0.4701315000, 0.7781556000", \ - "0.1600892000, 0.3413555000, 0.6506003000", \ - "0.0656882000, 0.2481751000, 0.5561992000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3474590000, 0.4420553000, 0.5022767000", \ - "0.2199036000, 0.3132793000, 0.3747214000", \ - "0.1255026000, 0.2200990000, 0.2815410000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.133498000, -0.311102200, -0.562974000", \ - "-0.035239600, -0.215285200, -0.496453800", \ - "0.0432923000, -0.137974000, -0.427687500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.177443400, -0.278143200, -0.340806000", \ - "-0.082847000, -0.181105500, -0.244988900", \ - "-0.004315100, -0.102573600, -0.168898400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0033190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032650000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053104000, 0.0053154000, 0.0053269000, 0.0053312000, 0.0053410000, 0.0053639000, 0.0054166000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001333000, 3.4673291e-06, -0.000295700, -0.000284700, -0.000259400, -0.000200900, -6.6001846e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033740000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.153029300, -0.106040400, -0.127606100", \ - "-0.296453800, -0.249464800, -0.271030600", \ - "-0.412827500, -0.368279900, -0.388625000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1692363000, 0.1222474000, 0.1425925000", \ - "0.3089987000, 0.2632305000, 0.2811341000", \ - "0.4241517000, 0.3796042000, 0.3962871000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1752772000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfstp_2") { - leakage_power () { - value : 0.0135655000; - when : "CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0155137000; - when : "CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0113531000; - when : "CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0110875000; - when : "!CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0096980000; - when : "CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0100748000; - when : "CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0149533000; - when : "CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0093765000; - when : "CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0104625000; - when : "!CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0103409000; - when : "CLK&D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0157815000; - when : "CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0109029000; - when : "CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0176911000; - when : "CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0156982000; - when : "!CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0143087000; - when : "CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0172828000; - when : "CLK&D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0159660000; - when : "!CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0145765000; - when : "CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0122243000; - when : "CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0115376000; - when : "!CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0101481000; - when : "CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0105249000; - when : "CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0144350000; - when : "CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0107176000; - when : "CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0091213000; - when : "!CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0089997000; - when : "CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0146855000; - when : "CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0145881000; - when : "!CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0144665000; - when : "CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0148433000; - when : "CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0141798000; - when : "!CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0140582000; - when : "CLK&D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0130580000; - when : "!CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0095306000; - when : "!CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0141994000; - when : "!CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0100389000; - when : "!CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0095887000; - when : "!CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0117168000; - when : "!CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0171836000; - when : "!CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0099807000; - when : "!CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0141413000; - when : "!CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0144673000; - when : "!CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0167753000; - when : "!CLK&D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0138002000; - when : "!CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0096746000; - when : "!CLK&D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0083334000; - when : "!CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0144091000; - when : "!CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0133919000; - when : "!CLK&D&SCD&SCE&!SET_B&Q"; - } - area : 35.033600000; - cell_footprint : "sky130_fd_sc_hd__sdfstp"; - cell_leakage_power : 0.0127802800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0019580000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0018730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0233955000, 0.0233109000, 0.0231157000, 0.0231609000, 0.0232648000, 0.0235047000, 0.0240577000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0186016000, 0.0184892000, 0.0182302000, 0.0182462000, 0.0182835000, 0.0183694000, 0.0185675000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020430000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3180836000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1994444000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0091705000, 0.0090415000, 0.0087440000, 0.0087865000, 0.0088848000, 0.0091114000, 0.0096336000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026582000, 0.0025851000, 0.0024166000, 0.0024450000, 0.0025106000, 0.0026617000, 0.0030102000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2876445000, 0.4860007000, 0.8306458000", \ - "0.1576478000, 0.3572246000, 0.6994284000", \ - "0.0632467000, 0.2628236000, 0.6025859000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1436016000, 0.2833639000, 0.4229310000", \ - "0.0795228000, 0.2107402000, 0.3307760000", \ - "0.0632467000, 0.1908021000, 0.3010723000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.115187500, -0.306219400, -0.554429000", \ - "-0.018149700, -0.214064500, -0.512322900", \ - "0.0603822000, -0.139194700, -0.453322300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.100539100, -0.234197900, -0.342026700", \ - "-0.055991500, -0.183546900, -0.290154900", \ - "-0.049481100, -0.175815800, -0.281203100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0278263000, 0.0264233000, 0.0225552000, 0.0106646000, -0.027674400, -0.142402200, -0.479299200", \ - "0.0278593000, 0.0264457000, 0.0225545000, 0.0106601000, -0.027648000, -0.142385600, -0.479294500", \ - "0.0279552000, 0.0265598000, 0.0226778000, 0.0107624000, -0.027555800, -0.142291100, -0.479176500", \ - "0.0275814000, 0.0261572000, 0.0222917000, 0.0103800000, -0.027943300, -0.142688100, -0.479593700", \ - "0.0273377000, 0.0259208000, 0.0220221000, 0.0101349000, -0.028191800, -0.142903900, -0.479802200", \ - "0.0273721000, 0.0259498000, 0.0220896000, 0.0101846000, -0.028132100, -0.142867500, -0.479778500", \ - "0.0302967000, 0.0288338000, 0.0244956000, 0.0115536000, -0.027353300, -0.142347100, -0.479260900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0299830000, 0.0317026000, 0.0368258000, 0.0508868000, 0.0901473000, 0.2037864000, 0.5372745000", \ - "0.0300268000, 0.0317859000, 0.0368636000, 0.0508944000, 0.0901025000, 0.2045856000, 0.5385029000", \ - "0.0299531000, 0.0316909000, 0.0367656000, 0.0508140000, 0.0900394000, 0.2046320000, 0.5374740000", \ - "0.0296610000, 0.0314047000, 0.0364805000, 0.0505487000, 0.0898039000, 0.2032005000, 0.5377666000", \ - "0.0292979000, 0.0310327000, 0.0361622000, 0.0502338000, 0.0895055000, 0.2032781000, 0.5366204000", \ - "0.0291958000, 0.0309345000, 0.0360845000, 0.0500834000, 0.0893325000, 0.2027104000, 0.5398425000", \ - "0.0313371000, 0.0329273000, 0.0375928000, 0.0511511000, 0.0899507000, 0.2043132000, 0.5356581000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0630985000, 0.0648536000, 0.0698552000, 0.0836733000, 0.1227561000, 0.2375647000, 0.5697242000", \ - "0.0628247000, 0.0645522000, 0.0695363000, 0.0834055000, 0.1225639000, 0.2359652000, 0.5718517000", \ - "0.0626053000, 0.0643502000, 0.0693329000, 0.0831334000, 0.1225945000, 0.2373793000, 0.5726176000", \ - "0.0627287000, 0.0644442000, 0.0694238000, 0.0832350000, 0.1223476000, 0.2373562000, 0.5709243000", \ - "0.0627473000, 0.0644635000, 0.0694410000, 0.0832728000, 0.1224739000, 0.2363149000, 0.5723449000", \ - "0.0618310000, 0.0635472000, 0.0685253000, 0.0823914000, 0.1214776000, 0.2354480000, 0.5710484000", \ - "0.0626501000, 0.0642719000, 0.0689978000, 0.0824752000, 0.1221277000, 0.2350750000, 0.5718148000"); - } - } - max_capacitance : 0.3158670000; - max_transition : 1.5009430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.3221851000, 0.3268743000, 0.3373510000, 0.3588961000, 0.4048908000, 0.5212376000, 0.8552819000", \ - "0.3266866000, 0.3313708000, 0.3418778000, 0.3633402000, 0.4093694000, 0.5258259000, 0.8607881000", \ - "0.3379951000, 0.3426828000, 0.3531559000, 0.3746493000, 0.4206786000, 0.5369475000, 0.8732696000", \ - "0.3639787000, 0.3686597000, 0.3791569000, 0.4006240000, 0.4466545000, 0.5630344000, 0.8971263000", \ - "0.4140417000, 0.4187094000, 0.4291894000, 0.4506852000, 0.4967132000, 0.6129815000, 0.9477187000", \ - "0.4862223000, 0.4909229000, 0.5013753000, 0.5228876000, 0.5688697000, 0.6852263000, 1.0197088000", \ - "0.5754308000, 0.5801253000, 0.5905284000, 0.6119799000, 0.6581036000, 0.7745055000, 1.1096277000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.3225691000, 0.3283226000, 0.3416315000, 0.3722389000, 0.4529200000, 0.6856941000, 1.3674499000", \ - "0.3271981000, 0.3330855000, 0.3463337000, 0.3768980000, 0.4575655000, 0.6905667000, 1.3707461000", \ - "0.3382426000, 0.3441870000, 0.3574824000, 0.3879503000, 0.4686371000, 0.7018419000, 1.3841810000", \ - "0.3644848000, 0.3703095000, 0.3835879000, 0.4141941000, 0.4951124000, 0.7280134000, 1.4098109000", \ - "0.4149432000, 0.4206850000, 0.4340148000, 0.4646288000, 0.5453982000, 0.7779370000, 1.4606001000", \ - "0.4878016000, 0.4937612000, 0.5070671000, 0.5375275000, 0.6183014000, 0.8510986000, 1.5320633000", \ - "0.5818918000, 0.5878329000, 0.6011178000, 0.6316967000, 0.7125944000, 0.9456067000, 1.6250316000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0187826000, 0.0216302000, 0.0288232000, 0.0467396000, 0.0940293000, 0.2406048000, 0.6910790000", \ - "0.0188247000, 0.0217268000, 0.0289124000, 0.0465990000, 0.0940400000, 0.2408252000, 0.6899918000", \ - "0.0185750000, 0.0216706000, 0.0291068000, 0.0466381000, 0.0941317000, 0.2397815000, 0.6875492000", \ - "0.0185762000, 0.0216936000, 0.0289034000, 0.0465902000, 0.0939533000, 0.2405010000, 0.6911069000", \ - "0.0187178000, 0.0215769000, 0.0287293000, 0.0466567000, 0.0942147000, 0.2407770000, 0.6836903000", \ - "0.0187839000, 0.0216822000, 0.0288091000, 0.0461852000, 0.0944831000, 0.2407519000, 0.6911791000", \ - "0.0186406000, 0.0217903000, 0.0286535000, 0.0465217000, 0.0944064000, 0.2408548000, 0.6795462000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0231198000, 0.0271620000, 0.0387278000, 0.0736674000, 0.1844122000, 0.5177750000, 1.4908433000", \ - "0.0229540000, 0.0275796000, 0.0387079000, 0.0735902000, 0.1845290000, 0.5169549000, 1.4935876000", \ - "0.0232093000, 0.0271804000, 0.0388772000, 0.0738166000, 0.1844821000, 0.5168411000, 1.4945407000", \ - "0.0231343000, 0.0272139000, 0.0387131000, 0.0736107000, 0.1845726000, 0.5158129000, 1.4967362000", \ - "0.0231580000, 0.0271845000, 0.0388022000, 0.0736309000, 0.1840667000, 0.5158449000, 1.5009429000", \ - "0.0232897000, 0.0272807000, 0.0389445000, 0.0736714000, 0.1843780000, 0.5166249000, 1.4999229000", \ - "0.0232758000, 0.0273074000, 0.0389744000, 0.0738256000, 0.1841029000, 0.5164443000, 1.4901100000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.3461406000, 0.3514749000, 0.3640786000, 0.3940832000, 0.4745880000, 0.7076016000, 1.3921476000", \ - "0.3512839000, 0.3565875000, 0.3691551000, 0.3991507000, 0.4797595000, 0.7124351000, 1.3950409000", \ - "0.3645991000, 0.3699215000, 0.3825268000, 0.4124609000, 0.4931675000, 0.7257571000, 1.4075765000", \ - "0.3973835000, 0.4027544000, 0.4153060000, 0.4452349000, 0.5257748000, 0.7581207000, 1.4387473000", \ - "0.4728231000, 0.4781960000, 0.4907422000, 0.5206702000, 0.6012129000, 0.8336392000, 1.5182444000", \ - "0.6264619000, 0.6318235000, 0.6443367000, 0.6743152000, 0.7549517000, 0.9877744000, 1.6674323000", \ - "0.8978575000, 0.9032461000, 0.9158780000, 0.9459276000, 1.0265371000, 1.2587914000, 1.9426836000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0201819000, 0.0245587000, 0.0364753000, 0.0724021000, 0.1842036000, 0.5184347000, 1.4987506000", \ - "0.0201028000, 0.0244210000, 0.0363993000, 0.0723833000, 0.1840256000, 0.5169220000, 1.4981576000", \ - "0.0202444000, 0.0244316000, 0.0364352000, 0.0724633000, 0.1841860000, 0.5178975000, 1.4940583000", \ - "0.0202023000, 0.0244534000, 0.0364544000, 0.0724705000, 0.1837175000, 0.5164823000, 1.4928773000", \ - "0.0201868000, 0.0244499000, 0.0364467000, 0.0724660000, 0.1842255000, 0.5163596000, 1.4967696000", \ - "0.0201030000, 0.0244436000, 0.0363707000, 0.0722577000, 0.1837137000, 0.5183536000, 1.4980051000", \ - "0.0205473000, 0.0248891000, 0.0367179000, 0.0724214000, 0.1840303000, 0.5144707000, 1.4992164000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SCD") { - capacitance : 0.0017320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027519000, 0.0027687000, 0.0028072000, 0.0028115000, 0.0028217000, 0.0028450000, 0.0028989000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002564500, -0.002609400, -0.002712900, -0.002716200, -0.002723400, -0.002740000, -0.002778300"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017980000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3511211000, 0.5287253000, 0.8282044000", \ - "0.2211243000, 0.3999492000, 0.6994284000", \ - "0.1279440000, 0.3067689000, 0.6062480000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.3089987000, 0.4742005000", \ - "0.1075990000, 0.2424785000, 0.3954733000", \ - "0.0949850000, 0.2274232000, 0.3743145000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.146925800, -0.318426400, -0.545884100", \ - "-0.065757200, -0.242140600, -0.506219400", \ - "0.0017884000, -0.174595100, -0.453322300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.122511700, -0.256170600, -0.396958300", \ - "-0.081626300, -0.212843800, -0.353631500", \ - "-0.078778000, -0.208774700, -0.348341800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0035400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112950000, 0.0112469000, 0.0111361000, 0.0112244000, 0.0114281000, 0.0118977000, 0.0129800000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000154900, -0.000307700, -0.000660100, -0.000582000, -0.000402300, 1.2260024e-05, 0.0009678000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2925274000, 0.4737936000, 0.7818177000", \ - "0.1625306000, 0.3437969000, 0.6530417000", \ - "0.0681296000, 0.2506165000, 0.5586406000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3511211000, 0.4444967000, 0.5059388000", \ - "0.2223450000, 0.3157207000, 0.3783835000", \ - "0.1279440000, 0.2225404000, 0.2852031000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.118849600, -0.294012400, -0.531235700", \ - "-0.024253300, -0.201857400, -0.478143200", \ - "0.0554994000, -0.126987600, -0.411818400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.159132800, -0.261053400, -0.324936800", \ - "-0.069419300, -0.168898400, -0.232781900", \ - "0.0078919000, -0.091587200, -0.157912100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0033190000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032640000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0053175000, 0.0053206000, 0.0053279000, 0.0053320000, 0.0053412000, 0.0053627000, 0.0054123000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001593000, 2.1658136e-05, -0.000295500, -0.000284500, -0.000259000, -0.000200200, -6.4519259e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033740000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.150587900, -0.102378300, -0.123944000", \ - "-0.294012400, -0.247023400, -0.267368500", \ - "-0.411606800, -0.365838500, -0.384962900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.1222474000, 0.1413718000", \ - "0.3089987000, 0.2620098000, 0.2811341000", \ - "0.4241517000, 0.3796042000, 0.3962871000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1829668000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfstp_4") { - leakage_power () { - value : 0.0102213000; - when : "!CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0162970000; - when : "!CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0152798000; - when : "!CLK&D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0133506000; - when : "CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0152988000; - when : "CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0111383000; - when : "CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0108726000; - when : "!CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0115859000; - when : "CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0119627000; - when : "CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0168412000; - when : "CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0112644000; - when : "CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0123504000; - when : "!CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0122288000; - when : "CLK&D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0155667000; - when : "CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0106881000; - when : "CLK&!D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0174763000; - when : "CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0154833000; - when : "!CLK&!D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0161966000; - when : "CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0170680000; - when : "CLK&D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0157512000; - when : "!CLK&D&!SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0164644000; - when : "CLK&D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0120095000; - when : "CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0113228000; - when : "!CLK&!D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0120360000; - when : "CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0124128000; - when : "CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0163229000; - when : "CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0126055000; - when : "CLK&D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0110092000; - when : "!CLK&D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0108876000; - when : "CLK&D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0165734000; - when : "CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0164760000; - when : "!CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0163544000; - when : "CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0167312000; - when : "CLK&!D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0160677000; - when : "!CLK&D&SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0159461000; - when : "CLK&D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0128431000; - when : "!CLK&D&!SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0114185000; - when : "!CLK&!D&!SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0160873000; - when : "!CLK&!D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0119268000; - when : "!CLK&!D&SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0114766000; - when : "!CLK&!D&!SCD&!SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0115020000; - when : "!CLK&D&SCD&!SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0169688000; - when : "!CLK&!D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0118686000; - when : "!CLK&!D&SCD&!SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0160292000; - when : "!CLK&!D&!SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0163552000; - when : "!CLK&D&!SCD&SCE&SET_B&Q"; - } - leakage_power () { - value : 0.0165605000; - when : "!CLK&D&SCD&SCE&SET_B&!Q"; - } - leakage_power () { - value : 0.0156881000; - when : "!CLK&!D&SCD&SCE&!SET_B&Q"; - } - leakage_power () { - value : 0.0115624000; - when : "!CLK&D&!SCD&!SCE&!SET_B&Q"; - } - area : 37.536000000; - cell_footprint : "sky130_fd_sc_hd__sdfstp"; - cell_leakage_power : 0.0139672600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - preset : "!SET_B"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0019500000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0018560000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0235084000, 0.0233907000, 0.0231196000, 0.0231612000, 0.0232576000, 0.0234795000, 0.0239913000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0184533000, 0.0183908000, 0.0182467000, 0.0182651000, 0.0183077000, 0.0184061000, 0.0186328000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020430000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3202806000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2181191000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0018710000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017780000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0090720000, 0.0089753000, 0.0087526000, 0.0087932000, 0.0088872000, 0.0091037000, 0.0096028000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0026002000, 0.0025375000, 0.0023930000, 0.0024201000, 0.0024828000, 0.0026274000, 0.0029606000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019640000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2900859000, 0.4884421000, 0.8318665000", \ - "0.1600892000, 0.3584453000, 0.7018698000", \ - "0.0656882000, 0.2652650000, 0.6050274000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1448223000, 0.2858053000, 0.4265931000", \ - "0.0795228000, 0.2107402000, 0.3319968000", \ - "0.0644674000, 0.1908021000, 0.3010723000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.109084000, -0.297674500, -0.537339200", \ - "-0.012046200, -0.207960900, -0.503778000", \ - "0.0652650000, -0.133091100, -0.445998100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.099318400, -0.232977200, -0.339585300", \ - "-0.054770800, -0.182326200, -0.288934200", \ - "-0.049481100, -0.174595100, -0.279982400"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0391553000, 0.0374079000, 0.0321123000, 0.0157158000, -0.041605800, -0.233162300, -0.852407500", \ - "0.0390948000, 0.0374128000, 0.0320514000, 0.0156405000, -0.041636100, -0.233198800, -0.852417500", \ - "0.0390340000, 0.0374043000, 0.0320242000, 0.0156666000, -0.041650300, -0.233215900, -0.852447500", \ - "0.0386227000, 0.0370320000, 0.0316176000, 0.0152637000, -0.042003400, -0.233585400, -0.852816800", \ - "0.0384681000, 0.0367104000, 0.0314421000, 0.0149930000, -0.042293800, -0.233828800, -0.853075900", \ - "0.0384512000, 0.0368224000, 0.0314891000, 0.0150285000, -0.042232400, -0.233784800, -0.853025200", \ - "0.0428370000, 0.0411296000, 0.0356229000, 0.0178229000, -0.041077500, -0.233258100, -0.852568500"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0431551000, 0.0450236000, 0.0513037000, 0.0708460000, 0.1308216000, 0.3205517000, 0.9338531000", \ - "0.0431401000, 0.0450127000, 0.0513202000, 0.0708229000, 0.1309162000, 0.3214317000, 0.9326981000", \ - "0.0429529000, 0.0448419000, 0.0511070000, 0.0706901000, 0.1306205000, 0.3205231000, 0.9374304000", \ - "0.0426671000, 0.0445648000, 0.0508061000, 0.0703455000, 0.1302873000, 0.3206362000, 0.9330580000", \ - "0.0422936000, 0.0442649000, 0.0504563000, 0.0699294000, 0.1303957000, 0.3198301000, 0.9328955000", \ - "0.0421409000, 0.0440493000, 0.0502953000, 0.0698172000, 0.1297971000, 0.3194745000, 0.9320382000", \ - "0.0445583000, 0.0463909000, 0.0522802000, 0.0712834000, 0.1309013000, 0.3215923000, 0.9309590000"); - } - } - internal_power () { - fall_power ("scalar") { - values("0.0000000000"); - } - related_pin : "SET_B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0759673000, 0.0778501000, 0.0840802000, 0.1034601000, 0.1633224000, 0.3535191000, 0.9698237000", \ - "0.0756070000, 0.0775444000, 0.0837886000, 0.1030921000, 0.1628365000, 0.3530232000, 0.9656826000", \ - "0.0753045000, 0.0772368000, 0.0834804000, 0.1028208000, 0.1627154000, 0.3541308000, 0.9695067000", \ - "0.0754151000, 0.0773860000, 0.0835639000, 0.1029033000, 0.1629504000, 0.3525744000, 0.9648486000", \ - "0.0754464000, 0.0773900000, 0.0836233000, 0.1030146000, 0.1628403000, 0.3531195000, 0.9702346000", \ - "0.0746319000, 0.0765605000, 0.0827648000, 0.1020970000, 0.1619573000, 0.3523370000, 0.9663666000", \ - "0.0757551000, 0.0776199000, 0.0835893000, 0.1024438000, 0.1625347000, 0.3521929000, 0.9650645000"); - } - } - max_capacitance : 0.5548190000; - max_transition : 1.5027430000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3436035000, 0.3469348000, 0.3555734000, 0.3748233000, 0.4161567000, 0.5192415000, 0.8329064000", \ - "0.3482234000, 0.3515548000, 0.3601676000, 0.3793796000, 0.4207618000, 0.5237520000, 0.8378001000", \ - "0.3594110000, 0.3627446000, 0.3713905000, 0.3906348000, 0.4319156000, 0.5350120000, 0.8485946000", \ - "0.3853773000, 0.3887148000, 0.3973425000, 0.4166423000, 0.4578804000, 0.5609608000, 0.8747708000", \ - "0.4354998000, 0.4388246000, 0.4474544000, 0.4666434000, 0.5080482000, 0.6110366000, 0.9243286000", \ - "0.5077380000, 0.5110628000, 0.5196972000, 0.5388669000, 0.5802138000, 0.6832573000, 0.9965947000", \ - "0.5970609000, 0.6004057000, 0.6090404000, 0.6282814000, 0.6695920000, 0.7727450000, 1.0865612000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3459618000, 0.3501045000, 0.3606534000, 0.3866176000, 0.4574641000, 0.6780946000, 1.3876444000", \ - "0.3506852000, 0.3547837000, 0.3653938000, 0.3913178000, 0.4621797000, 0.6825895000, 1.3910163000", \ - "0.3617651000, 0.3658791000, 0.3764288000, 0.4024320000, 0.4731765000, 0.6940457000, 1.4012524000", \ - "0.3879188000, 0.3920022000, 0.4026161000, 0.4285433000, 0.4994041000, 0.7197061000, 1.4282202000", \ - "0.4383620000, 0.4423746000, 0.4530129000, 0.4789560000, 0.5497879000, 0.7700539000, 1.4779930000", \ - "0.5116592000, 0.5157530000, 0.5263772000, 0.5522020000, 0.6230475000, 0.8438056000, 1.5521652000", \ - "0.6060784000, 0.6101708000, 0.6208159000, 0.6467653000, 0.7176289000, 0.9378881000, 1.6478963000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0218030000, 0.0238781000, 0.0291405000, 0.0427740000, 0.0806824000, 0.2037323000, 0.6174800000", \ - "0.0217835000, 0.0236514000, 0.0290390000, 0.0431578000, 0.0812165000, 0.2032594000, 0.6212107000", \ - "0.0217767000, 0.0239144000, 0.0291098000, 0.0427581000, 0.0812181000, 0.2030170000, 0.6165365000", \ - "0.0217974000, 0.0239542000, 0.0290237000, 0.0427456000, 0.0813139000, 0.2032823000, 0.6196421000", \ - "0.0218400000, 0.0239036000, 0.0290555000, 0.0431373000, 0.0812088000, 0.2032328000, 0.6229811000", \ - "0.0218497000, 0.0239015000, 0.0294902000, 0.0428003000, 0.0813658000, 0.2034723000, 0.6223527000", \ - "0.0218810000, 0.0237866000, 0.0291749000, 0.0428679000, 0.0808094000, 0.2039517000, 0.6179989000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0243986000, 0.0271531000, 0.0358471000, 0.0631267000, 0.1577767000, 0.4729863000, 1.5016185000", \ - "0.0243642000, 0.0271375000, 0.0358759000, 0.0630330000, 0.1574358000, 0.4747258000, 1.4985004000", \ - "0.0243759000, 0.0271495000, 0.0357802000, 0.0631573000, 0.1573541000, 0.4736098000, 1.5020046000", \ - "0.0243583000, 0.0271544000, 0.0358704000, 0.0630308000, 0.1573214000, 0.4733879000, 1.4981130000", \ - "0.0243367000, 0.0274902000, 0.0359151000, 0.0630878000, 0.1576381000, 0.4737719000, 1.4970015000", \ - "0.0242625000, 0.0271900000, 0.0358974000, 0.0630956000, 0.1575827000, 0.4738641000, 1.4946460000", \ - "0.0244902000, 0.0272768000, 0.0359879000, 0.0630888000, 0.1573738000, 0.4736962000, 1.4982793000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - timing () { - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3602310000, 0.3639340000, 0.3738760000, 0.3991533000, 0.4698107000, 0.6901793000, 1.3962577000", \ - "0.3652023000, 0.3689438000, 0.3788604000, 0.4039628000, 0.4743809000, 0.6953575000, 1.4022951000", \ - "0.3784353000, 0.3822018000, 0.3920928000, 0.4173714000, 0.4879527000, 0.7083186000, 1.4144693000", \ - "0.4112680000, 0.4150328000, 0.4249280000, 0.4501951000, 0.5207126000, 0.7412700000, 1.4497658000", \ - "0.4867948000, 0.4905586000, 0.5004529000, 0.5257175000, 0.5962351000, 0.8174131000, 1.5267752000", \ - "0.6407774000, 0.6444905000, 0.6544256000, 0.6796324000, 0.7499523000, 0.9706608000, 1.6790330000", \ - "0.9144934000, 0.9182429000, 0.9282754000, 0.9536065000, 1.0239734000, 1.2443918000, 1.9537976000"); - } - related_pin : "SET_B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0212685000, 0.0241923000, 0.0331410000, 0.0614139000, 0.1571299000, 0.4740391000, 1.4983477000", \ - "0.0213859000, 0.0243559000, 0.0331725000, 0.0613645000, 0.1569088000, 0.4744868000, 1.4993112000", \ - "0.0212506000, 0.0242990000, 0.0331119000, 0.0614081000, 0.1571737000, 0.4739097000, 1.4998668000", \ - "0.0212340000, 0.0242908000, 0.0330729000, 0.0612409000, 0.1571889000, 0.4741709000, 1.5027428000", \ - "0.0212231000, 0.0242795000, 0.0330620000, 0.0612462000, 0.1574449000, 0.4748245000, 1.4974093000", \ - "0.0213293000, 0.0242489000, 0.0330698000, 0.0611795000, 0.1569198000, 0.4743627000, 1.4975496000", \ - "0.0218447000, 0.0246393000, 0.0334929000, 0.0615885000, 0.1570509000, 0.4733644000, 1.5005779000"); - } - timing_sense : "negative_unate"; - timing_type : "preset"; - } - } - pin ("SCD") { - capacitance : 0.0017320000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016660000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0027563000, 0.0027495000, 0.0027340000, 0.0027413000, 0.0027586000, 0.0027982000, 0.0028897000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002671300, -0.002684700, -0.002715800, -0.002716300, -0.002717400, -0.002720000, -0.002725900"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017980000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3535625000, 0.5311667000, 0.8306458000", \ - "0.2235658000, 0.4023906000, 0.7006491000", \ - "0.1291647000, 0.3079896000, 0.6074687000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1716777000, 0.3114401000, 0.4766419000", \ - "0.1088197000, 0.2436992000, 0.3954733000", \ - "0.0949850000, 0.2274232000, 0.3743145000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.139601600, -0.309881500, -0.532456400", \ - "-0.059653600, -0.236037100, -0.496453800", \ - "0.0078919000, -0.168491500, -0.443556600"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.121291000, -0.254949900, -0.394516900", \ - "-0.080405600, -0.211623000, -0.352410800", \ - "-0.078778000, -0.208774700, -0.348341800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0035400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0034030000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112950000, 0.0112455000, 0.0111314000, 0.0112278000, 0.0114502000, 0.0119629000, 0.0131447000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.000361200, -0.000451900, -0.000660900, -0.000582100, -0.000400700, 1.780503e-05, 0.0009823000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036770000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2949688000, 0.4762350000, 0.7842591000", \ - "0.1637513000, 0.3462383000, 0.6542624000", \ - "0.0693503000, 0.2518372000, 0.5598613000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3535625000, 0.4469381000, 0.5083802000", \ - "0.2247865000, 0.3181621000, 0.3796042000", \ - "0.1291647000, 0.2237611000, 0.2864238000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.112746100, -0.286688200, -0.516587200", \ - "-0.019370400, -0.196974600, -0.469598300", \ - "0.0603822000, -0.120884100, -0.404494100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.150587900, -0.252508500, -0.317612600", \ - "-0.063315800, -0.162794900, -0.226678400", \ - "0.0127747000, -0.086704400, -0.154250000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SET_B") { - capacitance : 0.0033200000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0032610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0052034000, 0.0052407000, 0.0053267000, 0.0053337000, 0.0053499000, 0.0053873000, 0.0054736000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("7.6237889e-06, -8.6978743e-05, -0.000305000, -0.000293900, -0.000268200, -0.000209000, -7.2394644e-05"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0033790000; - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.149367200, -0.099936800, -0.117840500", \ - "-0.292791700, -0.244582000, -0.262485700", \ - "-0.410386100, -0.363397100, -0.380080100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "recovery_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1704570000, 0.1222474000, 0.1401510000", \ - "0.3102194000, 0.2620098000, 0.2799134000", \ - "0.4241517000, 0.3796042000, 0.3950664000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "removal_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2005429000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "SET_B"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - preset : "!SET_B"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - pin ("SET_B") { - direction : "input"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfxbp_1") { - leakage_power () { - value : 0.0158737000; - when : "CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0156228000; - when : "!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0121428000; - when : "!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0156998000; - when : "!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0154402000; - when : "!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0149568000; - when : "!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0116853000; - when : "!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0132516000; - when : "!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0160713000; - when : "!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0129072000; - when : "!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0124048000; - when : "CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116629000; - when : "CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0114032000; - when : "CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0108260000; - when : "!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0152939000; - when : "CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0164084000; - when : "CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0143074000; - when : "CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0148584000; - when : "!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0120344000; - when : "CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0109198000; - when : "CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0135135000; - when : "CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0115690000; - when : "!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0131692000; - when : "CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119405000; - when : "!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119472000; - when : "CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0113093000; - when : "!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0157773000; - when : "CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0155293000; - when : "CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0147649000; - when : "CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0144009000; - when : "!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0160369000; - when : "CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0159671000; - when : "!CLK&!D&SCD&SCE&Q&!Q_N"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__sdfxbp"; - cell_leakage_power : 0.0137405000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017840000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016990000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0224101000, 0.0222905000, 0.0220146000, 0.0221011000, 0.0223006000, 0.0227605000, 0.0238206000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0178913000, 0.0177689000, 0.0174867000, 0.0175025000, 0.0175393000, 0.0176240000, 0.0178192000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018690000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2389908000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1741787000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016980000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016150000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080837000, 0.0079723000, 0.0077156000, 0.0077633000, 0.0078734000, 0.0081273000, 0.0087125000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0013581000, 0.0013073000, 0.0011904000, 0.0012153000, 0.0012730000, 0.0014059000, 0.0017124000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017810000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1997539000, 0.4005514000, 0.7220033000", \ - "0.0819642000, 0.2827617000, 0.6029928000", \ - "-0.003891900, 0.1956849000, 0.5134746000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1020977000, 0.2320944000, 0.3350404000", \ - "0.0306947000, 0.1497051000, 0.2367819000", \ - "0.0058737000, 0.1212220000, 0.2021953000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.116408200, -0.312322900, -0.591050100", \ - "-0.014487600, -0.212843800, -0.511102200", \ - "0.0603822000, -0.137974000, -0.442335900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.068800800, -0.189031900, -0.262681000", \ - "-0.010825500, -0.126173800, -0.203485000", \ - "0.0078919000, -0.105015000, -0.181105500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("-0.005518100, -0.000854100, 0.0076732000, 0.0166638000, 0.0111603000, -0.037743100, -0.191067600", \ - "-0.005465800, -0.000816100, 0.0076811000, 0.0165834000, 0.0110734000, -0.037852300, -0.191206600", \ - "-0.005337800, -0.000704400, 0.0077478000, 0.0166132000, 0.0110425000, -0.037922400, -0.191306600", \ - "-0.005357900, -0.000746300, 0.0076824000, 0.0164834000, 0.0108674000, -0.038106600, -0.191493600", \ - "-0.005388200, -0.000793600, 0.0076065000, 0.0163415000, 0.0107209000, -0.038291400, -0.191697100", \ - "-0.005422300, -0.000811100, 0.0076087000, 0.0163901000, 0.0107513000, -0.038235200, -0.191648200", \ - "-0.005458300, -0.000763700, 0.0078160000, 0.0168766000, 0.0115211000, -0.037597100, -0.190916000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013067210, 0.0034150410, 0.0089250130, 0.0233250100, 0.0609585600, 0.1593117000"); - values("-0.007107400, -0.004352400, 0.0019538000, 0.0152533000, 0.0425309000, 0.1054743000, 0.2646694000", \ - "-0.007047800, -0.004296300, 0.0020038000, 0.0153047000, 0.0426054000, 0.1060403000, 0.2656920000", \ - "-0.006924300, -0.004197300, 0.0020524000, 0.0152758000, 0.0424988000, 0.1058736000, 0.2657790000", \ - "-0.006950700, -0.004249200, 0.0019507000, 0.0150899000, 0.0422401000, 0.1052778000, 0.2647881000", \ - "-0.006983900, -0.004300400, 0.0018554000, 0.0149418000, 0.0420425000, 0.1046866000, 0.2650112000", \ - "-0.007025700, -0.004343000, 0.0018166000, 0.0149093000, 0.0420030000, 0.1052090000, 0.2649603000", \ - "-0.007059600, -0.004291100, 0.0020589000, 0.0153360000, 0.0424681000, 0.1056165000, 0.2649230000"); - } - } - max_capacitance : 0.1593120000; - max_transition : 1.5087580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.2798396000, 0.2856082000, 0.2977365000, 0.3226481000, 0.3767740000, 0.5066239000, 0.8433231000", \ - "0.2846124000, 0.2903765000, 0.3025050000, 0.3274051000, 0.3815377000, 0.5114051000, 0.8482074000", \ - "0.2956692000, 0.3014443000, 0.3135605000, 0.3384570000, 0.3925897000, 0.5224507000, 0.8592809000", \ - "0.3214107000, 0.3271773000, 0.3392986000, 0.3641941000, 0.4183313000, 0.5481866000, 0.8847360000", \ - "0.3689191000, 0.3746754000, 0.3868022000, 0.4117091000, 0.4658351000, 0.5957057000, 0.9325517000", \ - "0.4354520000, 0.4412171000, 0.4533799000, 0.4782414000, 0.5323998000, 0.6622574000, 0.9990168000", \ - "0.5181741000, 0.5239165000, 0.5360766000, 0.5609656000, 0.6151140000, 0.7449831000, 1.0818216000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.2844727000, 0.2914945000, 0.3072986000, 0.3443825000, 0.4393075000, 0.6845975000, 1.3273193000", \ - "0.2892453000, 0.2961769000, 0.3119477000, 0.3490520000, 0.4439858000, 0.6894634000, 1.3304308000", \ - "0.3002846000, 0.3072578000, 0.3230561000, 0.3601363000, 0.4550585000, 0.7004023000, 1.3417635000", \ - "0.3258682000, 0.3328921000, 0.3486742000, 0.3857638000, 0.4806769000, 0.7256961000, 1.3720018000", \ - "0.3749518000, 0.3819885000, 0.3977810000, 0.4348615000, 0.5297821000, 0.7748185000, 1.4152201000", \ - "0.4452202000, 0.4522374000, 0.4680355000, 0.5051192000, 0.6000453000, 0.8454656000, 1.4877103000", \ - "0.5364196000, 0.5434671000, 0.5592838000, 0.5964017000, 0.6913621000, 0.9366770000, 1.5772638000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0205074000, 0.0247200000, 0.0350510000, 0.0590069000, 0.1203987000, 0.2854998000, 0.7316607000", \ - "0.0204732000, 0.0247127000, 0.0350495000, 0.0591143000, 0.1200062000, 0.2854271000, 0.7360961000", \ - "0.0204822000, 0.0247365000, 0.0350460000, 0.0591795000, 0.1201251000, 0.2861363000, 0.7363665000", \ - "0.0204807000, 0.0247990000, 0.0350108000, 0.0591780000, 0.1202671000, 0.2853008000, 0.7323232000", \ - "0.0204713000, 0.0247448000, 0.0350902000, 0.0591300000, 0.1202476000, 0.2855107000, 0.7336694000", \ - "0.0204666000, 0.0248942000, 0.0348956000, 0.0591922000, 0.1202692000, 0.2855395000, 0.7334080000", \ - "0.0206128000, 0.0249535000, 0.0349399000, 0.0592025000, 0.1204560000, 0.2853285000, 0.7289291000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013067200, 0.0034150400, 0.0089250100, 0.0233250000, 0.0609586000, 0.1593120000"); - values("0.0260470000, 0.0326762000, 0.0502357000, 0.1000388000, 0.2328970000, 0.5832402000, 1.5041335000", \ - "0.0260823000, 0.0326263000, 0.0503165000, 0.1000553000, 0.2332747000, 0.5832358000, 1.5085558000", \ - "0.0260871000, 0.0326748000, 0.0502424000, 0.1000555000, 0.2331678000, 0.5818315000, 1.5072916000", \ - "0.0259911000, 0.0327318000, 0.0502376000, 0.0999893000, 0.2331290000, 0.5835486000, 1.5029793000", \ - "0.0260628000, 0.0326679000, 0.0502734000, 0.1000656000, 0.2338545000, 0.5836361000, 1.5087576000", \ - "0.0260692000, 0.0327036000, 0.0502439000, 0.1000463000, 0.2329459000, 0.5837543000, 1.5065502000", \ - "0.0261431000, 0.0328472000, 0.0502923000, 0.1000207000, 0.2329631000, 0.5819754000, 1.5049556000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("-0.005772300, -0.001346800, 0.0068348000, 0.0152590000, 0.0082718000, -0.045726000, -0.214405800", \ - "-0.005715200, -0.001292100, 0.0068738000, 0.0153037000, 0.0083096000, -0.045696400, -0.214376900", \ - "-0.005589600, -0.001190800, 0.0069313000, 0.0152724000, 0.0081834000, -0.045865300, -0.214600000", \ - "-0.005616100, -0.001242100, 0.0068341000, 0.0150966000, 0.0079175000, -0.046189600, -0.214947800", \ - "-0.005649200, -0.001293600, 0.0067273000, 0.0149376000, 0.0077059000, -0.046438900, -0.215120700", \ - "-0.005690800, -0.001336700, 0.0066966000, 0.0149102000, 0.0076676000, -0.046496300, -0.215259100", \ - "-0.005732800, -0.001293900, 0.0068888000, 0.0153405000, 0.0082686000, -0.045890400, -0.214602900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013248540, 0.0035104760, 0.0093017370, 0.0246468900, 0.0653070500, 0.1730446000"); - values("-0.007079800, -0.004215000, 0.0024679000, 0.0166675000, 0.0461833000, 0.1143556000, 0.2882313000", \ - "-0.007028700, -0.004174200, 0.0024824000, 0.0165826000, 0.0460013000, 0.1143137000, 0.2882711000", \ - "-0.006898200, -0.004059300, 0.0025614000, 0.0166068000, 0.0461252000, 0.1147825000, 0.2882369000", \ - "-0.006919200, -0.004101000, 0.0024805000, 0.0164822000, 0.0457470000, 0.1141358000, 0.2892434000", \ - "-0.006948900, -0.004144700, 0.0024028000, 0.0163423000, 0.0457155000, 0.1140400000, 0.2891617000", \ - "-0.006980400, -0.004164000, 0.0024165000, 0.0163945000, 0.0456804000, 0.1138058000, 0.2879806000", \ - "-0.007016600, -0.004108100, 0.0026274000, 0.0168827000, 0.0462008000, 0.1147843000, 0.2880937000"); - } - } - max_capacitance : 0.1730450000; - max_transition : 1.5041520000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.3338015000, 0.3388659000, 0.3496394000, 0.3721543000, 0.4237110000, 0.5560196000, 0.9073557000", \ - "0.3384881000, 0.3435765000, 0.3543497000, 0.3768587000, 0.4283349000, 0.5607912000, 0.9119621000", \ - "0.3495544000, 0.3546148000, 0.3653942000, 0.3879529000, 0.4394647000, 0.5717727000, 0.9228638000", \ - "0.3752133000, 0.3802859000, 0.3910414000, 0.4136072000, 0.4650889000, 0.5974290000, 0.9482906000", \ - "0.4242096000, 0.4292700000, 0.4400460000, 0.4625584000, 0.5141186000, 0.6464084000, 0.9974271000", \ - "0.4945591000, 0.4996247000, 0.5103901000, 0.5329547000, 0.5844361000, 0.7167572000, 1.0679471000", \ - "0.5858135000, 0.5908800000, 0.6016415000, 0.6242109000, 0.6756997000, 0.8080307000, 1.1589834000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.3324246000, 0.3384885000, 0.3529210000, 0.3885150000, 0.4804931000, 0.7243335000, 1.3699809000", \ - "0.3371726000, 0.3433361000, 0.3577225000, 0.3931835000, 0.4856850000, 0.7292075000, 1.3748778000", \ - "0.3482755000, 0.3544031000, 0.3687751000, 0.4041985000, 0.4965321000, 0.7403959000, 1.3867705000", \ - "0.3739919000, 0.3801370000, 0.3945094000, 0.4299174000, 0.5223744000, 0.7661192000, 1.4115840000", \ - "0.4215388000, 0.4276736000, 0.4420214000, 0.4774117000, 0.5696921000, 0.8141970000, 1.4593348000", \ - "0.4880713000, 0.4941815000, 0.5085641000, 0.5439229000, 0.6363833000, 0.8810975000, 1.5253671000", \ - "0.5707730000, 0.5769082000, 0.5912530000, 0.6266330000, 0.7189544000, 0.9629889000, 1.6101159000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0159214000, 0.0200880000, 0.0293783000, 0.0524392000, 0.1159533000, 0.2904955000, 0.7636352000", \ - "0.0161647000, 0.0198957000, 0.0294138000, 0.0525952000, 0.1153259000, 0.2906346000, 0.7578835000", \ - "0.0159256000, 0.0198950000, 0.0293507000, 0.0524314000, 0.1159885000, 0.2900186000, 0.7624429000", \ - "0.0159380000, 0.0201532000, 0.0294233000, 0.0525036000, 0.1158623000, 0.2900870000, 0.7606095000", \ - "0.0159262000, 0.0200875000, 0.0293694000, 0.0524109000, 0.1159667000, 0.2896240000, 0.7658700000", \ - "0.0159331000, 0.0201170000, 0.0294118000, 0.0523001000, 0.1159107000, 0.2899124000, 0.7630178000", \ - "0.0159122000, 0.0201386000, 0.0294259000, 0.0525004000, 0.1158895000, 0.2899715000, 0.7556511000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013248500, 0.0035104800, 0.0093017400, 0.0246469000, 0.0653071000, 0.1730450000"); - values("0.0195495000, 0.0260645000, 0.0435249000, 0.0920846000, 0.2237518000, 0.5732644000, 1.4988748000", \ - "0.0196185000, 0.0260652000, 0.0435786000, 0.0920895000, 0.2231153000, 0.5741886000, 1.5037630000", \ - "0.0195529000, 0.0260176000, 0.0436069000, 0.0921000000, 0.2237825000, 0.5755790000, 1.5031320000", \ - "0.0195007000, 0.0259392000, 0.0435483000, 0.0920099000, 0.2238051000, 0.5742245000, 1.5041516000", \ - "0.0195674000, 0.0260211000, 0.0435377000, 0.0920582000, 0.2235144000, 0.5726480000, 1.5033252000", \ - "0.0195553000, 0.0260269000, 0.0435532000, 0.0920480000, 0.2237276000, 0.5741190000, 1.5006076000", \ - "0.0195661000, 0.0260220000, 0.0435465000, 0.0920235000, 0.2237117000, 0.5727058000, 1.5003769000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0018150000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033568000, 0.0033502000, 0.0033352000, 0.0033429000, 0.0033609000, 0.0034025000, 0.0034982000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003221900, -0.003221000, -0.003219100, -0.003228000, -0.003248200, -0.003294800, -0.003402200"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019040000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2583477000, 0.4347311000, 0.7220033000", \ - "0.1405579000, 0.3169414000, 0.6042136000", \ - "0.0547018000, 0.2310853000, 0.5195781000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1362773000, 0.2687155000, 0.4082826000", \ - "0.0636536000, 0.1924297000, 0.3222311000", \ - "0.0388327000, 0.1663880000, 0.2925274000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.156691400, -0.329412800, -0.572739600", \ - "-0.065757200, -0.240919900, -0.504998700", \ - "0.0030091000, -0.172153600, -0.444777300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.094435500, -0.218328800, -0.331040400", \ - "-0.040122400, -0.164015600, -0.281610000", \ - "-0.021404900, -0.146518900, -0.265334000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0033610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031670000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0125776000, 0.0124318000, 0.0120958000, 0.0121673000, 0.0123322000, 0.0127125000, 0.0135889000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001810000, 9.6771024e-05, -9.7252345e-05, -6.1919626e-05, 1.954548e-05, 0.0002073000, 0.0006403000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035550000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2217266000, 0.4029929000, 0.6939271000", \ - "0.1027161000, 0.2839824000, 0.5761373000", \ - "0.0144186000, 0.1969056000, 0.4866191000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2595684000, 0.3480612000, 0.3899720000", \ - "0.1417786000, 0.2314922000, 0.2721823000", \ - "0.0571432000, 0.1468568000, 0.1875469000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.137160200, -0.315985000, -0.573960300", \ - "-0.034018900, -0.214064500, -0.489129600", \ - "0.0445130000, -0.135532600, -0.415480500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.082228500, -0.211004600, -0.302964200", \ - "-0.026694700, -0.150587900, -0.243768200", \ - "-0.010418600, -0.133091100, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfxbp_2") { - leakage_power () { - value : 0.0148082000; - when : "CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0140573000; - when : "CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136949000; - when : "!CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0153134000; - when : "CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0152452000; - when : "!CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0151515000; - when : "CLK&!D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0149018000; - when : "!CLK&D&SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0124466000; - when : "!CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0149901000; - when : "!CLK&!D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0147445000; - when : "!CLK&!D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0142575000; - when : "!CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0119906000; - when : "!CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0135409000; - when : "!CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0153643000; - when : "!CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0131975000; - when : "!CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0126948000; - when : "CLK&D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0119646000; - when : "CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0117191000; - when : "CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0111382000; - when : "!CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0145808000; - when : "CLK&!D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0156876000; - when : "CLK&D&!SCD&SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0136013000; - when : "CLK&D&SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0141510000; - when : "!CLK&D&!SCD&!SCE&Q&!Q_N"; - } - leakage_power () { - value : 0.0123389000; - when : "CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0112321000; - when : "CLK&!D&!SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0137891000; - when : "CLK&!D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0118707000; - when : "!CLK&!D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0134457000; - when : "CLK&D&SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0122449000; - when : "!CLK&D&!SCD&SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0122388000; - when : "CLK&D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0116251000; - when : "!CLK&!D&SCD&!SCE&!Q&Q_N"; - } - leakage_power () { - value : 0.0150678000; - when : "CLK&!D&SCD&!SCE&Q&!Q_N"; - } - area : 32.531200000; - cell_footprint : "sky130_fd_sc_hd__sdfxbp"; - cell_leakage_power : 0.0135342200; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017850000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017000000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0225664000, 0.0224470000, 0.0221715000, 0.0222539000, 0.0224441000, 0.0228824000, 0.0238928000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0179689000, 0.0178464000, 0.0175640000, 0.0175808000, 0.0176198000, 0.0177098000, 0.0179173000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018700000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2411878000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1829668000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0079881000, 0.0079143000, 0.0077443000, 0.0077908000, 0.0078984000, 0.0081463000, 0.0087178000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0013745000, 0.0013225000, 0.0012028000, 0.0012281000, 0.0012864000, 0.0014209000, 0.0017310000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017740000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2021953000, 0.4029929000, 0.7244447000", \ - "0.0831849000, 0.2839824000, 0.6054342000", \ - "-0.002671200, 0.1969056000, 0.5146953000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1057598000, 0.2345358000, 0.3387025000", \ - "0.0319154000, 0.1509258000, 0.2392233000", \ - "0.0058737000, 0.1212220000, 0.2021953000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.112746100, -0.308660800, -0.582505200", \ - "-0.012046200, -0.210402300, -0.507440100", \ - "0.0628236000, -0.135532600, -0.438673800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.067580100, -0.187811200, -0.260239600", \ - "-0.009604800, -0.126173800, -0.202264300", \ - "0.0078919000, -0.105015000, -0.181105500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014441070, 0.0041708870, 0.0120464100, 0.0347926000, 0.1004885000, 0.2902321000"); - values("-0.005793100, -0.000561400, 0.0101397000, 0.0219275000, 0.0096593000, -0.081265400, -0.381803100", \ - "-0.005740700, -0.000522500, 0.0101539000, 0.0219225000, 0.0095995000, -0.081384700, -0.381944200", \ - "-0.005605700, -0.000411500, 0.0102485000, 0.0219722000, 0.0094949000, -0.081476500, -0.382047900", \ - "-0.005629200, -0.000445400, 0.0101470000, 0.0217312000, 0.0093077000, -0.081765700, -0.382354400", \ - "-0.005654300, -0.000488000, 0.0100925000, 0.0216933000, 0.0092428000, -0.081856300, -0.382442700", \ - "-0.005699200, -0.000530300, 0.0100502000, 0.0216615000, 0.0091595000, -0.081931900, -0.382472500", \ - "-0.005751300, -0.000494800, 0.0102926000, 0.0221923000, 0.0100934000, -0.081172400, -0.381736100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014441070, 0.0041708870, 0.0120464100, 0.0347926000, 0.1004885000, 0.2902321000"); - values("-0.007403600, -0.004578200, 0.0027419000, 0.0203465000, 0.0617761000, 0.1702305000, 0.4769839000", \ - "-0.007345200, -0.004523200, 0.0027893000, 0.0203864000, 0.0619127000, 0.1692721000, 0.4777358000", \ - "-0.007215900, -0.004412100, 0.0028550000, 0.0203766000, 0.0617393000, 0.1691571000, 0.4765576000", \ - "-0.007238500, -0.004457800, 0.0027599000, 0.0201941000, 0.0614399000, 0.1688623000, 0.4745012000", \ - "-0.007268000, -0.004506600, 0.0026653000, 0.0200215000, 0.0612181000, 0.1688803000, 0.4770203000", \ - "-0.007314800, -0.004552300, 0.0026146000, 0.0199826000, 0.0611371000, 0.1687759000, 0.4745689000", \ - "-0.007357400, -0.004501800, 0.0029135000, 0.0205446000, 0.0617807000, 0.1698186000, 0.4751110000"); - } - } - max_capacitance : 0.2902320000; - max_transition : 1.5059460000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014441100, 0.0041708900, 0.0120464000, 0.0347926000, 0.1004880000, 0.2902320000"); - values("0.2937666000, 0.2987933000, 0.3100447000, 0.3331165000, 0.3818876000, 0.5001363000, 0.8290576000", \ - "0.2984669000, 0.3035411000, 0.3147808000, 0.3378185000, 0.3866311000, 0.5048912000, 0.8340645000", \ - "0.3095042000, 0.3145645000, 0.3258179000, 0.3488722000, 0.3976565000, 0.5159265000, 0.8452668000", \ - "0.3353154000, 0.3403430000, 0.3515869000, 0.3746652000, 0.4234399000, 0.5416960000, 0.8708527000", \ - "0.3828021000, 0.3878580000, 0.3991347000, 0.4221628000, 0.4709809000, 0.5892437000, 0.9182063000", \ - "0.4494770000, 0.4545520000, 0.4657786000, 0.4887983000, 0.5376242000, 0.6558872000, 0.9852997000", \ - "0.5321022000, 0.5371604000, 0.5484264000, 0.5714451000, 0.6202570000, 0.7385347000, 1.0675589000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014441100, 0.0041708900, 0.0120464000, 0.0347926000, 0.1004880000, 0.2902320000"); - values("0.2925860000, 0.2983708000, 0.3119496000, 0.3435714000, 0.4271743000, 0.6622871000, 1.3395116000", \ - "0.2973507000, 0.3031194000, 0.3166411000, 0.3483153000, 0.4318693000, 0.6669311000, 1.3466962000", \ - "0.3083807000, 0.3141738000, 0.3277881000, 0.3594607000, 0.4429958000, 0.6781480000, 1.3560115000", \ - "0.3340553000, 0.3398214000, 0.3534309000, 0.3850948000, 0.4686545000, 0.7038432000, 1.3813103000", \ - "0.3831150000, 0.3889067000, 0.4024485000, 0.4340860000, 0.5176570000, 0.7529559000, 1.4329307000", \ - "0.4535192000, 0.4592378000, 0.4728355000, 0.5045465000, 0.5880926000, 0.8233652000, 1.5028443000", \ - "0.5447159000, 0.5505399000, 0.5640889000, 0.5957662000, 0.6794020000, 0.9147127000, 1.5914622000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014441100, 0.0041708900, 0.0120464000, 0.0347926000, 0.1004880000, 0.2902320000"); - values("0.0201538000, 0.0234348000, 0.0311292000, 0.0501916000, 0.0993816000, 0.2429929000, 0.6770212000", \ - "0.0201109000, 0.0233392000, 0.0312309000, 0.0502592000, 0.0993820000, 0.2431805000, 0.6801256000", \ - "0.0200109000, 0.0232879000, 0.0310782000, 0.0502553000, 0.0993303000, 0.2431662000, 0.6784588000", \ - "0.0201515000, 0.0234330000, 0.0310740000, 0.0501965000, 0.0994445000, 0.2437321000, 0.6762719000", \ - "0.0201033000, 0.0233604000, 0.0310589000, 0.0502626000, 0.0993830000, 0.2429263000, 0.6796922000", \ - "0.0201605000, 0.0233296000, 0.0312790000, 0.0502022000, 0.0995854000, 0.2431704000, 0.6832960000", \ - "0.0201457000, 0.0233112000, 0.0312855000, 0.0500717000, 0.0997027000, 0.2431911000, 0.6763682000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014441100, 0.0041708900, 0.0120464000, 0.0347926000, 0.1004880000, 0.2902320000"); - values("0.0233294000, 0.0279782000, 0.0406879000, 0.0781943000, 0.1926886000, 0.5265478000, 1.5049484000", \ - "0.0233135000, 0.0280315000, 0.0407026000, 0.0781237000, 0.1929459000, 0.5270530000, 1.5011724000", \ - "0.0233317000, 0.0279791000, 0.0407469000, 0.0780183000, 0.1928877000, 0.5266258000, 1.4961317000", \ - "0.0231860000, 0.0277915000, 0.0406847000, 0.0780252000, 0.1927746000, 0.5266189000, 1.4958305000", \ - "0.0232635000, 0.0279623000, 0.0406942000, 0.0781597000, 0.1924202000, 0.5255146000, 1.5024940000", \ - "0.0232010000, 0.0278700000, 0.0406617000, 0.0781164000, 0.1925026000, 0.5251963000, 1.5059460000", \ - "0.0233529000, 0.0280210000, 0.0407638000, 0.0782322000, 0.1925047000, 0.5266034000, 1.5009048000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014653290, 0.0042943790, 0.0125853600, 0.0368833800, 0.1080926000, 0.3167824000"); - values("-0.006021500, -0.001045100, 0.0092818000, 0.0203851000, 0.0059558000, -0.094101800, -0.425464000", \ - "-0.005960500, -0.000988800, 0.0093225000, 0.0204255000, 0.0059966000, -0.094093200, -0.425460600", \ - "-0.005832500, -0.000882500, 0.0093882000, 0.0203995000, 0.0059013000, -0.094197700, -0.425670700", \ - "-0.005854800, -0.000927000, 0.0092879000, 0.0202189000, 0.0056448000, -0.094530800, -0.425950900", \ - "-0.005884400, -0.000971500, 0.0091988000, 0.0200595000, 0.0054271000, -0.094789100, -0.426220800", \ - "-0.005930500, -0.001021300, 0.0091475000, 0.0200120000, 0.0053697000, -0.094860600, -0.426286400", \ - "-0.005983000, -0.000990200, 0.0093796000, 0.0206093000, 0.0059968000, -0.094301000, -0.425670200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014653290, 0.0042943790, 0.0125853600, 0.0368833800, 0.1080926000, 0.3167824000"); - values("-0.007404300, -0.004486400, 0.0032715000, 0.0219068000, 0.0663003000, 0.1839168000, 0.5204127000", \ - "-0.007352000, -0.004451700, 0.0032712000, 0.0219200000, 0.0663952000, 0.1842101000, 0.5214527000", \ - "-0.007217900, -0.004329600, 0.0033541000, 0.0219336000, 0.0661512000, 0.1840091000, 0.5191244000", \ - "-0.007237400, -0.004367000, 0.0032617000, 0.0218332000, 0.0658913000, 0.1830638000, 0.5210547000", \ - "-0.007266300, -0.004415700, 0.0031950000, 0.0216689000, 0.0658982000, 0.1825144000, 0.5184298000", \ - "-0.007306800, -0.004446900, 0.0031813000, 0.0216758000, 0.0658047000, 0.1828134000, 0.5189073000", \ - "-0.007331300, -0.004349300, 0.0034798000, 0.0223068000, 0.0666652000, 0.1840370000, 0.5187327000"); - } - } - max_capacitance : 0.3167820000; - max_transition : 1.5010030000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014653300, 0.0042943800, 0.0125854000, 0.0368834000, 0.1080930000, 0.3167820000"); - values("0.3733139000, 0.3779152000, 0.3885373000, 0.4100947000, 0.4560503000, 0.5720424000, 0.9053093000", \ - "0.3780120000, 0.3826177000, 0.3932363000, 0.4148022000, 0.4607502000, 0.5767442000, 0.9106488000", \ - "0.3891543000, 0.3938577000, 0.4043365000, 0.4258819000, 0.4719251000, 0.5879545000, 0.9215116000", \ - "0.4148038000, 0.4195118000, 0.4299882000, 0.4515330000, 0.4974942000, 0.6136575000, 0.9475229000", \ - "0.4638932000, 0.4686176000, 0.4790831000, 0.5006351000, 0.5465890000, 0.6627359000, 0.9966327000", \ - "0.5342325000, 0.5389508000, 0.5493451000, 0.5708609000, 0.6169091000, 0.7329298000, 1.0664870000", \ - "0.6255110000, 0.6301172000, 0.6407379000, 0.6623020000, 0.7082540000, 0.8242750000, 1.1574112000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014653300, 0.0042943800, 0.0125854000, 0.0368834000, 0.1080930000, 0.3167820000"); - values("0.3767049000, 0.3820466000, 0.3945481000, 0.4240105000, 0.5039939000, 0.7350623000, 1.4146289000", \ - "0.3814158000, 0.3867396000, 0.3992684000, 0.4290257000, 0.5087448000, 0.7399678000, 1.4164092000", \ - "0.3925405000, 0.3978580000, 0.4103974000, 0.4400402000, 0.5200061000, 0.7516060000, 1.4296916000", \ - "0.4182080000, 0.4235495000, 0.4360116000, 0.4657228000, 0.5456991000, 0.7775647000, 1.4548648000", \ - "0.4656477000, 0.4709502000, 0.4834844000, 0.5132382000, 0.5931887000, 0.8245615000, 1.5026715000", \ - "0.5328124000, 0.5380913000, 0.5505479000, 0.5802543000, 0.6602555000, 0.8916413000, 1.5685613000", \ - "0.6151755000, 0.6204561000, 0.6329887000, 0.6627414000, 0.7426976000, 0.9735813000, 1.6526335000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014653300, 0.0042943800, 0.0125854000, 0.0368834000, 0.1080930000, 0.3167820000"); - values("0.0185842000, 0.0215996000, 0.0288200000, 0.0469625000, 0.0948347000, 0.2424507000, 0.6876521000", \ - "0.0185634000, 0.0216065000, 0.0288629000, 0.0469721000, 0.0949004000, 0.2422803000, 0.6929557000", \ - "0.0186411000, 0.0215801000, 0.0287610000, 0.0468844000, 0.0950985000, 0.2424287000, 0.6943889000", \ - "0.0187504000, 0.0216226000, 0.0291917000, 0.0469169000, 0.0951722000, 0.2431127000, 0.6956530000", \ - "0.0187196000, 0.0216356000, 0.0291594000, 0.0468776000, 0.0951364000, 0.2429984000, 0.6896156000", \ - "0.0184851000, 0.0215665000, 0.0288472000, 0.0469464000, 0.0952126000, 0.2426097000, 0.6956474000", \ - "0.0185694000, 0.0216057000, 0.0288463000, 0.0469712000, 0.0948783000, 0.2426231000, 0.6877983000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014653300, 0.0042943800, 0.0125854000, 0.0368834000, 0.1080930000, 0.3167820000"); - values("0.0198830000, 0.0241120000, 0.0361911000, 0.0722031000, 0.1840817000, 0.5185603000, 1.4949435000", \ - "0.0197996000, 0.0242271000, 0.0363043000, 0.0722911000, 0.1838305000, 0.5179769000, 1.5001577000", \ - "0.0198810000, 0.0241551000, 0.0361138000, 0.0722080000, 0.1839670000, 0.5180887000, 1.5004826000", \ - "0.0199453000, 0.0241527000, 0.0362353000, 0.0722741000, 0.1841514000, 0.5178020000, 1.5008843000", \ - "0.0199182000, 0.0242267000, 0.0362666000, 0.0721679000, 0.1837635000, 0.5178433000, 1.4973500000", \ - "0.0197416000, 0.0241101000, 0.0361753000, 0.0722406000, 0.1836160000, 0.5189783000, 1.5010029000", \ - "0.0198766000, 0.0242991000, 0.0363115000, 0.0721539000, 0.1835873000, 0.5164310000, 1.4983625000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0018240000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017340000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033707000, 0.0033655000, 0.0033534000, 0.0033611000, 0.0033791000, 0.0034206000, 0.0035164000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003235500, -0.003234100, -0.003230600, -0.003242100, -0.003268200, -0.003328300, -0.003467000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019140000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2607891000, 0.4371725000, 0.7232240000", \ - "0.1417786000, 0.3193828000, 0.6066549000", \ - "0.0559225000, 0.2323060000, 0.5207988000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1387187000, 0.2711569000, 0.4107240000", \ - "0.0636536000, 0.1936504000, 0.3210104000", \ - "0.0388327000, 0.1663880000, 0.2913066000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.151808600, -0.323309300, -0.565415400", \ - "-0.063315800, -0.237257800, -0.501336600", \ - "0.0042298000, -0.169712200, -0.442335900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.094435500, -0.217108100, -0.328599000", \ - "-0.038901700, -0.162794900, -0.279168600", \ - "-0.021404900, -0.145298200, -0.262892600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0033670000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0126497000, 0.0125550000, 0.0123368000, 0.0124019000, 0.0125523000, 0.0128989000, 0.0136978000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002675000, 0.0001812000, -1.7804701e-05, 1.6899164e-05, 9.6914403e-05, 0.0002814000, 0.0007066000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035610000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2241680000, 0.4054343000, 0.6963685000", \ - "0.1039368000, 0.2864238000, 0.5773581000", \ - "0.0156393000, 0.1981263000, 0.4890606000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2620098000, 0.3505026000, 0.3924134000", \ - "0.1429994000, 0.2327129000, 0.2746237000", \ - "0.0583639000, 0.1480775000, 0.1887676000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.134718700, -0.311102200, -0.569077500", \ - "-0.030356800, -0.210402300, -0.484246800", \ - "0.0481751000, -0.134311900, -0.413039100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.081007800, -0.209783900, -0.301743500", \ - "-0.026694700, -0.149367200, -0.242547500", \ - "-0.010418600, -0.131870400, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfxtp_1") { - leakage_power () { - value : 0.0098196000; - when : "!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0095672000; - when : "!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0090810000; - when : "!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0093194000; - when : "!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0109176000; - when : "!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0101918000; - when : "!CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0105735000; - when : "!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0099323000; - when : "CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0092868000; - when : "CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0090344000; - when : "CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0084540000; - when : "!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093118000; - when : "CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0104226000; - when : "CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0084376000; - when : "CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0089900000; - when : "!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0096590000; - when : "CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0085482000; - when : "CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0110736000; - when : "CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0091927000; - when : "!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0107295000; - when : "CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0095648000; - when : "!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0094754000; - when : "CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0089402000; - when : "!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0097981000; - when : "CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0096917000; - when : "CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0088945000; - when : "CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0085331000; - when : "!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0100505000; - when : "CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0101312000; - when : "!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0100358000; - when : "CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0097871000; - when : "!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0097763000; - when : "!CLK&D&!SCD&!SCE&!Q"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__sdfxtp"; - cell_leakage_power : 0.0096006670; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017760000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0225624000, 0.0224461000, 0.0221780000, 0.0222719000, 0.0224884000, 0.0229872000, 0.0241373000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0179364000, 0.0178135000, 0.0175302000, 0.0175663000, 0.0176494000, 0.0178408000, 0.0182822000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018580000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2400893000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1675876000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016160000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0081497000, 0.0080387000, 0.0077827000, 0.0078300000, 0.0079390000, 0.0081903000, 0.0087697000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0014510000, 0.0014026000, 0.0012909000, 0.0013192000, 0.0013846000, 0.0015350000, 0.0018821000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017760000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2021953000, 0.4029929000, 0.7244447000", \ - "0.0844056000, 0.2852031000, 0.6054342000", \ - "-0.002671200, 0.1981263000, 0.5159160000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0984355000, 0.2259909000, 0.3264954000", \ - "0.0294740000, 0.1484844000, 0.2343405000", \ - "0.0058737000, 0.1200013000, 0.2021953000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.123732400, -0.322088500, -0.606919200", \ - "-0.021811800, -0.218947300, -0.520867900", \ - "0.0554994000, -0.142856800, -0.447218700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.068800800, -0.189031900, -0.261460300", \ - "-0.010825500, -0.126173800, -0.204705700", \ - "0.0078919000, -0.105015000, -0.182326200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0190738000, 0.0180871000, 0.0153116000, 0.0067702000, -0.016794500, -0.079020800, -0.242402300", \ - "0.0191380000, 0.0181544000, 0.0153587000, 0.0068344000, -0.016717400, -0.078970500, -0.242321400", \ - "0.0192046000, 0.0182246000, 0.0154252000, 0.0069018000, -0.016664100, -0.078908300, -0.242255700", \ - "0.0187478000, 0.0177727000, 0.0149535000, 0.0064329000, -0.017131300, -0.079375400, -0.242736500", \ - "0.0184468000, 0.0174846000, 0.0146700000, 0.0061557000, -0.017407300, -0.079656300, -0.243008100", \ - "0.0193274000, 0.0180682000, 0.0146658000, 0.0060427000, -0.017502900, -0.079746600, -0.243107700", \ - "0.0202709000, 0.0190222000, 0.0157113000, 0.0067584000, -0.016952200, -0.079311700, -0.242695700"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621240600, 0.1629738000"); - values("0.0187750000, 0.0204156000, 0.0243722000, 0.0337381000, 0.0571447000, 0.1190410000, 0.2814942000", \ - "0.0188715000, 0.0205039000, 0.0244768000, 0.0338346000, 0.0572700000, 0.1193277000, 0.2811437000", \ - "0.0188314000, 0.0204661000, 0.0244367000, 0.0337980000, 0.0571944000, 0.1191129000, 0.2818411000", \ - "0.0184417000, 0.0200476000, 0.0240311000, 0.0333788000, 0.0568481000, 0.1181305000, 0.2802334000", \ - "0.0180837000, 0.0197254000, 0.0236975000, 0.0330627000, 0.0564983000, 0.1185000000, 0.2808573000", \ - "0.0179647000, 0.0195449000, 0.0234810000, 0.0328816000, 0.0563375000, 0.1182036000, 0.2808859000", \ - "0.0196472000, 0.0209788000, 0.0244942000, 0.0335209000, 0.0567196000, 0.1183452000, 0.2808703000"); - } - } - max_capacitance : 0.1629740000; - max_transition : 1.5068800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2654880000, 0.2706495000, 0.2816042000, 0.3043740000, 0.3553866000, 0.4839117000, 0.8209675000", \ - "0.2702937000, 0.2754509000, 0.2863980000, 0.3091702000, 0.3602326000, 0.4888407000, 0.8266433000", \ - "0.2813525000, 0.2865305000, 0.2974761000, 0.3202481000, 0.3712972000, 0.4998316000, 0.8364033000", \ - "0.3072010000, 0.3123611000, 0.3233195000, 0.3460927000, 0.3971325000, 0.5256475000, 0.8629399000", \ - "0.3547759000, 0.3599327000, 0.3708859000, 0.3936661000, 0.4447162000, 0.5733936000, 0.9104473000", \ - "0.4216545000, 0.4268175000, 0.4377642000, 0.4605318000, 0.5115948000, 0.6400009000, 0.9763570000", \ - "0.5039861000, 0.5091546000, 0.5201151000, 0.5429032000, 0.5939321000, 0.7227359000, 1.0596777000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.2706827000, 0.2773430000, 0.2926541000, 0.3294854000, 0.4238017000, 0.6692137000, 1.3204026000", \ - "0.2753899000, 0.2820979000, 0.2974324000, 0.3342101000, 0.4282626000, 0.6745797000, 1.3197967000", \ - "0.2864773000, 0.2931689000, 0.3085050000, 0.3453018000, 0.4394638000, 0.6855623000, 1.3332269000", \ - "0.3121458000, 0.3187923000, 0.3341376000, 0.3708564000, 0.4652376000, 0.7111807000, 1.3587483000", \ - "0.3612618000, 0.3679389000, 0.3832797000, 0.4200746000, 0.5141771000, 0.7604161000, 1.4064127000", \ - "0.4315302000, 0.4381681000, 0.4535240000, 0.4902584000, 0.5843984000, 0.8306532000, 1.4754751000", \ - "0.5227852000, 0.5294424000, 0.5448208000, 0.5815678000, 0.6758559000, 0.9218912000, 1.5685293000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0174489000, 0.0213835000, 0.0309371000, 0.0537210000, 0.1147749000, 0.2830331000, 0.7305522000", \ - "0.0174224000, 0.0213542000, 0.0309175000, 0.0536873000, 0.1146877000, 0.2824393000, 0.7346806000", \ - "0.0174189000, 0.0213872000, 0.0309025000, 0.0536911000, 0.1149444000, 0.2833565000, 0.7295370000", \ - "0.0175106000, 0.0214948000, 0.0308416000, 0.0538008000, 0.1149338000, 0.2819813000, 0.7344941000", \ - "0.0174000000, 0.0214851000, 0.0308768000, 0.0538274000, 0.1147015000, 0.2846062000, 0.7326844000", \ - "0.0174087000, 0.0214430000, 0.0308895000, 0.0537950000, 0.1143095000, 0.2829899000, 0.7290383000", \ - "0.0174518000, 0.0214874000, 0.0309656000, 0.0538488000, 0.1148811000, 0.2826167000, 0.7243736000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013116800, 0.0034410100, 0.0090270100, 0.0236811000, 0.0621241000, 0.1629740000"); - values("0.0238404000, 0.0303886000, 0.0480351000, 0.0971888000, 0.2296390000, 0.5787751000, 1.5029812000", \ - "0.0238097000, 0.0304055000, 0.0480165000, 0.0969001000, 0.2296613000, 0.5794583000, 1.4975358000", \ - "0.0238581000, 0.0303703000, 0.0480793000, 0.0970362000, 0.2293414000, 0.5800874000, 1.5021661000", \ - "0.0238681000, 0.0303691000, 0.0480509000, 0.0971802000, 0.2291655000, 0.5798465000, 1.5017494000", \ - "0.0238496000, 0.0303473000, 0.0480909000, 0.0969752000, 0.2295930000, 0.5796550000, 1.5067325000", \ - "0.0240086000, 0.0304415000, 0.0480251000, 0.0970018000, 0.2298020000, 0.5791059000, 1.5068801000", \ - "0.0241224000, 0.0305353000, 0.0480716000, 0.0971707000, 0.2291363000, 0.5780567000, 1.5003996000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0018110000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017220000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033492000, 0.0033437000, 0.0033309000, 0.0033388000, 0.0033570000, 0.0033992000, 0.0034965000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003202900, -0.003206100, -0.003213500, -0.003223100, -0.003245100, -0.003295900, -0.003412800"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018990000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2583477000, 0.4347311000, 0.7195618000", \ - "0.1405579000, 0.3169414000, 0.6029928000", \ - "0.0559225000, 0.2310853000, 0.5171367000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1301738000, 0.2626120000, 0.3997376000", \ - "0.0612122000, 0.1899883000, 0.3173483000", \ - "0.0376120000, 0.1651673000, 0.2900859000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.164015600, -0.336737000, -0.584946600", \ - "-0.071860700, -0.244582000, -0.511102200", \ - "-0.001873700, -0.175815800, -0.447218700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.094435500, -0.218328800, -0.329819700", \ - "-0.040122400, -0.162794900, -0.280389300", \ - "-0.021404900, -0.145298200, -0.264113300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0033870000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031920000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0127233000, 0.0125788000, 0.0122458000, 0.0123177000, 0.0124832000, 0.0128651000, 0.0137452000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002743000, 0.0001876000, -1.2309258e-05, 2.318147e-05, 0.0001051000, 0.0002936000, 0.0007284000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2241680000, 0.4054343000, 0.6963685000", \ - "0.1039368000, 0.2864238000, 0.5785788000", \ - "0.0168600000, 0.1981263000, 0.4902812000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2595684000, 0.3505026000, 0.3911927000", \ - "0.1429994000, 0.2327129000, 0.2746237000", \ - "0.0583639000, 0.1492982000, 0.1899883000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.144484400, -0.324529900, -0.588608700", \ - "-0.040122400, -0.220168000, -0.498895200", \ - "0.0384095000, -0.141636100, -0.424025400"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.081007800, -0.209783900, -0.301743500", \ - "-0.026694700, -0.149367200, -0.243768200", \ - "-0.010418600, -0.133091100, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfxtp_2") { - leakage_power () { - value : 0.0091678000; - when : "CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0084172000; - when : "CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0080563000; - when : "!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0095733000; - when : "CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0096059000; - when : "!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0095103000; - when : "CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0092635000; - when : "!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0100718000; - when : "!CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093493000; - when : "!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0091024000; - when : "!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0086156000; - when : "!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0096153000; - when : "!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0111649000; - when : "!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0097230000; - when : "!CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0108224000; - when : "!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0102212000; - when : "CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0095894000; - when : "CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0093426000; - when : "CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0087613000; - when : "!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0088396000; - when : "CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0099470000; - when : "CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0079607000; - when : "CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0085128000; - when : "!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0099631000; - when : "CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0088558000; - when : "CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0113143000; - when : "CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0094950000; - when : "!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0109718000; - when : "CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0098687000; - when : "!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0097646000; - when : "CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0092481000; - when : "!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093264000; - when : "CLK&!D&SCD&!SCE&Q"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__sdfxtp"; - cell_leakage_power : 0.0095012970; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017840000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0017090000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0225773000, 0.0224577000, 0.0221821000, 0.0222681000, 0.0224663000, 0.0229231000, 0.0239764000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0179645000, 0.0178421000, 0.0175600000, 0.0175754000, 0.0176111000, 0.0176932000, 0.0178827000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018580000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2422863000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1774742000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080075000, 0.0079240000, 0.0077316000, 0.0077798000, 0.0078908000, 0.0081465000, 0.0087361000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0014682000, 0.0014198000, 0.0013082000, 0.0013328000, 0.0013894000, 0.0015198000, 0.0018206000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017720000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2046367000, 0.4042135000, 0.7268861000", \ - "0.0856263000, 0.2864238000, 0.6066549000", \ - "-0.001450500, 0.1993470000, 0.5171367000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1082012000, 0.2369772000, 0.3411439000", \ - "0.0331361000, 0.1521465000, 0.2404440000", \ - "0.0058737000, 0.1212220000, 0.2021953000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.111525400, -0.306219400, -0.577622400", \ - "-0.012046200, -0.209181600, -0.506219400", \ - "0.0628236000, -0.135532600, -0.438673800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.067580100, -0.187811200, -0.260239600", \ - "-0.009604800, -0.126173800, -0.203485000", \ - "0.0078919000, -0.105015000, -0.181105500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014589070, 0.0042568180, 0.0124206000, 0.0362409900, 0.1057445000, 0.3085426000"); - values("0.0228088000, 0.0214429000, 0.0177029000, 0.0060328000, -0.031714900, -0.144097400, -0.472582500", \ - "0.0228544000, 0.0214865000, 0.0177740000, 0.0060957000, -0.031642600, -0.144026500, -0.472510200", \ - "0.0229703000, 0.0215877000, 0.0178557000, 0.0061587000, -0.031572100, -0.143948000, -0.472425700", \ - "0.0224854000, 0.0210972000, 0.0173861000, 0.0056840000, -0.032037300, -0.144419600, -0.472796100", \ - "0.0222636000, 0.0208755000, 0.0171784000, 0.0054561000, -0.032250700, -0.144640300, -0.473130600", \ - "0.0229042000, 0.0214112000, 0.0172278000, 0.0054744000, -0.032243900, -0.144625500, -0.473045800", \ - "0.0254810000, 0.0240527000, 0.0197590000, 0.0069478000, -0.031357200, -0.143886100, -0.472433900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014589070, 0.0042568180, 0.0124206000, 0.0362409900, 0.1057445000, 0.3085426000"); - values("0.0240642000, 0.0258115000, 0.0308652000, 0.0446583000, 0.0830222000, 0.1937877000, 0.5215641000", \ - "0.0241551000, 0.0258976000, 0.0309296000, 0.0447080000, 0.0830426000, 0.1950940000, 0.5228374000", \ - "0.0241101000, 0.0258495000, 0.0308638000, 0.0446671000, 0.0830107000, 0.1938007000, 0.5193474000", \ - "0.0237281000, 0.0254690000, 0.0305099000, 0.0442928000, 0.0825951000, 0.1935291000, 0.5190680000", \ - "0.0234143000, 0.0251600000, 0.0302128000, 0.0439789000, 0.0823251000, 0.1933910000, 0.5210401000", \ - "0.0233756000, 0.0251188000, 0.0301032000, 0.0439597000, 0.0822076000, 0.1942551000, 0.5188318000", \ - "0.0253565000, 0.0269626000, 0.0315611000, 0.0449465000, 0.0832440000, 0.1946042000, 0.5199658000"); - } - } - max_capacitance : 0.3085430000; - max_transition : 1.5036360000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014589100, 0.0042568200, 0.0124206000, 0.0362410000, 0.1057440000, 0.3085430000"); - values("0.2797912000, 0.2841885000, 0.2940873000, 0.3146856000, 0.3590693000, 0.4721264000, 0.7966507000", \ - "0.2845682000, 0.2889635000, 0.2988398000, 0.3194011000, 0.3638304000, 0.4767166000, 0.8022511000", \ - "0.2956797000, 0.3000337000, 0.3099467000, 0.3304711000, 0.3748908000, 0.4877954000, 0.8122580000", \ - "0.3214815000, 0.3258690000, 0.3357848000, 0.3563428000, 0.4007586000, 0.5136590000, 0.8375693000", \ - "0.3690616000, 0.3734388000, 0.3833632000, 0.4039410000, 0.4483055000, 0.5612655000, 0.8860103000", \ - "0.4359909000, 0.4403825000, 0.4502680000, 0.4707884000, 0.5152438000, 0.6281857000, 0.9520641000", \ - "0.5184325000, 0.5228091000, 0.5326974000, 0.5533102000, 0.5976664000, 0.7106932000, 1.0351187000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014589100, 0.0042568200, 0.0124206000, 0.0362410000, 0.1057440000, 0.3085430000"); - values("0.2808465000, 0.2861328000, 0.2986853000, 0.3287805000, 0.4101699000, 0.6434921000, 1.3253142000", \ - "0.2856108000, 0.2909049000, 0.3034120000, 0.3334434000, 0.4145166000, 0.6487770000, 1.3321173000", \ - "0.2966674000, 0.3019409000, 0.3144590000, 0.3445360000, 0.4255829000, 0.6598277000, 1.3478456000", \ - "0.3222098000, 0.3274790000, 0.3400828000, 0.3701302000, 0.4512238000, 0.6852877000, 1.3723542000", \ - "0.3713042000, 0.3765914000, 0.3891400000, 0.4191480000, 0.5005568000, 0.7342576000, 1.4183633000", \ - "0.4416482000, 0.4469433000, 0.4595594000, 0.4895907000, 0.5706200000, 0.8047277000, 1.4883461000", \ - "0.5329778000, 0.5382514000, 0.5508865000, 0.5809862000, 0.6622697000, 0.8961278000, 1.5777760000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014589100, 0.0042568200, 0.0124206000, 0.0362410000, 0.1057440000, 0.3085430000"); - values("0.0174135000, 0.0202908000, 0.0274061000, 0.0444768000, 0.0910375000, 0.2332656000, 0.6642534000", \ - "0.0175241000, 0.0202429000, 0.0273268000, 0.0444429000, 0.0912898000, 0.2333829000, 0.6612438000", \ - "0.0174735000, 0.0203364000, 0.0271619000, 0.0446618000, 0.0910866000, 0.2336801000, 0.6625345000", \ - "0.0174134000, 0.0203256000, 0.0271936000, 0.0446454000, 0.0911702000, 0.2336615000, 0.6637684000", \ - "0.0174918000, 0.0203288000, 0.0272472000, 0.0445660000, 0.0908998000, 0.2332935000, 0.6695179000", \ - "0.0174965000, 0.0203534000, 0.0271971000, 0.0444441000, 0.0907657000, 0.2337690000, 0.6634959000", \ - "0.0173561000, 0.0203400000, 0.0271642000, 0.0445760000, 0.0911202000, 0.2339729000, 0.6607804000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014589100, 0.0042568200, 0.0124206000, 0.0362410000, 0.1057440000, 0.3085430000"); - values("0.0212324000, 0.0254432000, 0.0374508000, 0.0735005000, 0.1861458000, 0.5190610000, 1.5036362000", \ - "0.0212003000, 0.0254487000, 0.0374480000, 0.0735657000, 0.1860142000, 0.5184225000, 1.4989662000", \ - "0.0211982000, 0.0254892000, 0.0373662000, 0.0736920000, 0.1859444000, 0.5185766000, 1.5000047000", \ - "0.0213114000, 0.0255451000, 0.0375209000, 0.0735859000, 0.1861149000, 0.5198952000, 1.5026701000", \ - "0.0212156000, 0.0254685000, 0.0373779000, 0.0736625000, 0.1860856000, 0.5196507000, 1.4986891000", \ - "0.0213479000, 0.0255301000, 0.0375252000, 0.0735566000, 0.1860693000, 0.5197509000, 1.4968213000", \ - "0.0213571000, 0.0255082000, 0.0375756000, 0.0736999000, 0.1859666000, 0.5199862000, 1.5001785000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0018140000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017250000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033463000, 0.0033439000, 0.0033385000, 0.0033441000, 0.0033569000, 0.0033864000, 0.0034546000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003217400, -0.003217300, -0.003217100, -0.003227800, -0.003252400, -0.003309300, -0.003440300"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019030000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2620098000, 0.4383932000, 0.7256653000", \ - "0.1429994000, 0.3206035000, 0.6078756000", \ - "0.0583639000, 0.2347474000, 0.5220195000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1399395000, 0.2735983000, 0.4131654000", \ - "0.0648744000, 0.1936504000, 0.3222311000", \ - "0.0388327000, 0.1663880000, 0.2913066000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.149367200, -0.320867800, -0.561753300", \ - "-0.062095000, -0.234816400, -0.498895200", \ - "0.0054505000, -0.168491500, -0.439894500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.094435500, -0.217108100, -0.327378200", \ - "-0.038901700, -0.162794900, -0.279168600", \ - "-0.021404900, -0.145298200, -0.262892600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0033690000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0126389000, 0.0124924000, 0.0121547000, 0.0122301000, 0.0124039000, 0.0128049000, 0.0137290000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002638000, 0.0001803000, -1.221061e-05, 2.2663229e-05, 0.0001031000, 0.0002884000, 0.0007156000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035630000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2253887000, 0.4078756000, 0.6975892000", \ - "0.1063783000, 0.2876445000, 0.5797995000", \ - "0.0180807000, 0.1993470000, 0.4915019000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2632305000, 0.3529440000, 0.3936341000", \ - "0.1454408000, 0.2339336000, 0.2758444000", \ - "0.0608053000, 0.1505189000, 0.1912090000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.131056600, -0.309881500, -0.565415400", \ - "-0.030356800, -0.210402300, -0.484246800", \ - "0.0469544000, -0.133091100, -0.413039100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.081007800, -0.209783900, -0.300522800", \ - "-0.026694700, -0.149367200, -0.242547500", \ - "-0.010418600, -0.131870400, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdfxtp_4") { - leakage_power () { - value : 0.0098373000; - when : "!CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0095917000; - when : "!CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0091048000; - when : "!CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0101631000; - when : "!CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0117133000; - when : "!CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0102115000; - when : "!CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0113700000; - when : "!CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0107685000; - when : "CLK&D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0101375000; - when : "CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0098919000; - when : "CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093105000; - when : "!CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0093288000; - when : "CLK&!D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0104355000; - when : "CLK&D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0084485000; - when : "CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0090001000; - when : "!CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0105117000; - when : "CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0094049000; - when : "CLK&!D&!SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0118627000; - when : "CLK&!D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0100430000; - when : "!CLK&!D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0115193000; - when : "CLK&D&SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0104172000; - when : "!CLK&D&!SCD&SCE&!Q"; - } - leakage_power () { - value : 0.0103124000; - when : "CLK&D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0097974000; - when : "!CLK&!D&SCD&!SCE&!Q"; - } - leakage_power () { - value : 0.0098157000; - when : "CLK&!D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0096554000; - when : "CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0089045000; - when : "CLK&D&!SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0085441000; - when : "!CLK&D&SCD&!SCE&Q"; - } - leakage_power () { - value : 0.0100613000; - when : "CLK&!D&!SCD&SCE&Q"; - } - leakage_power () { - value : 0.0100944000; - when : "!CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0099988000; - when : "CLK&!D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0097510000; - when : "!CLK&D&SCD&SCE&Q"; - } - leakage_power () { - value : 0.0106191000; - when : "!CLK&D&!SCD&!SCE&!Q"; - } - area : 30.028800000; - cell_footprint : "sky130_fd_sc_hd__sdfxtp"; - cell_leakage_power : 0.0100195600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017750000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016930000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0225184000, 0.0224025000, 0.0221353000, 0.0222167000, 0.0224042000, 0.0228363000, 0.0238327000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0179722000, 0.0178492000, 0.0175656000, 0.0175958000, 0.0176654000, 0.0178258000, 0.0181958000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018580000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2422863000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1928533000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0016930000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016120000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0080202000, 0.0079442000, 0.0077691000, 0.0078163000, 0.0079249000, 0.0081756000, 0.0087533000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0014629000, 0.0014147000, 0.0013036000, 0.0013276000, 0.0013828000, 0.0015104000, 0.0018043000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "data"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017740000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2046367000, 0.4042135000, 0.7268861000", \ - "0.0856263000, 0.2864238000, 0.6066549000", \ - "-0.001450500, 0.1993470000, 0.5171367000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1118633000, 0.2406393000, 0.3460267000", \ - "0.0343568000, 0.1545879000, 0.2428854000", \ - "0.0070944000, 0.1224427000, 0.2034160000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.106642600, -0.301336600, -0.566636100", \ - "-0.008384100, -0.206740200, -0.501336600", \ - "0.0652650000, -0.133091100, -0.435011700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.067580100, -0.187811200, -0.260239600", \ - "-0.009604800, -0.126173800, -0.203485000", \ - "0.0078919000, -0.105015000, -0.181105500"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0327682000, 0.0310993000, 0.0258227000, 0.0096312000, -0.046043400, -0.232668500, -0.833238300", \ - "0.0328026000, 0.0311302000, 0.0258502000, 0.0096916000, -0.045973200, -0.232578600, -0.833178700", \ - "0.0329119000, 0.0312682000, 0.0259835000, 0.0098311000, -0.045886300, -0.232527300, -0.833088700", \ - "0.0324406000, 0.0307925000, 0.0254702000, 0.0093702000, -0.046357200, -0.232999000, -0.833568400", \ - "0.0322101000, 0.0305364000, 0.0251846000, 0.0090830000, -0.046638200, -0.233243100, -0.833823000", \ - "0.0321313000, 0.0304242000, 0.0251184000, 0.0090639000, -0.046688700, -0.233303300, -0.833892600", \ - "0.0367132000, 0.0350941000, 0.0296284000, 0.0120656000, -0.045561500, -0.232760500, -0.833392000"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016011820, 0.0051275690, 0.0164203500, 0.0525839300, 0.1683929000, 0.5392554000"); - values("0.0365310000, 0.0384472000, 0.0444620000, 0.0634191000, 0.1219700000, 0.3086621000, 0.9059697000", \ - "0.0365560000, 0.0385025000, 0.0445453000, 0.0635713000, 0.1221052000, 0.3073061000, 0.9026137000", \ - "0.0365723000, 0.0384771000, 0.0445124000, 0.0634644000, 0.1220410000, 0.3069657000, 0.9030124000", \ - "0.0361121000, 0.0380394000, 0.0440962000, 0.0631150000, 0.1217019000, 0.3068182000, 0.9061115000", \ - "0.0358260000, 0.0377430000, 0.0437478000, 0.0627888000, 0.1213875000, 0.3066331000, 0.9058484000", \ - "0.0355507000, 0.0374482000, 0.0435549000, 0.0625649000, 0.1211034000, 0.3061830000, 0.9019090000", \ - "0.0373354000, 0.0391034000, 0.0449718000, 0.0636096000, 0.1223443000, 0.3078448000, 0.9021359000"); - } - } - max_capacitance : 0.5392550000; - max_transition : 1.5037560000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.3163507000, 0.3199453000, 0.3293514000, 0.3502761000, 0.3949070000, 0.5024739000, 0.8230580000", \ - "0.3211832000, 0.3247456000, 0.3341974000, 0.3552010000, 0.3996728000, 0.5072684000, 0.8277904000", \ - "0.3321864000, 0.3358117000, 0.3452356000, 0.3661648000, 0.4106925000, 0.5183628000, 0.8390706000", \ - "0.3578880000, 0.3614659000, 0.3708759000, 0.3918109000, 0.4363267000, 0.5440397000, 0.8647548000", \ - "0.4057168000, 0.4092975000, 0.4187014000, 0.4396750000, 0.4842109000, 0.5918809000, 0.9125747000", \ - "0.4725928000, 0.4762047000, 0.4856108000, 0.5066312000, 0.5511165000, 0.6587422000, 0.9796630000", \ - "0.5551035000, 0.5587213000, 0.5681441000, 0.5890751000, 0.6336927000, 0.7412940000, 1.0620296000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.3092409000, 0.3132705000, 0.3240180000, 0.3507611000, 0.4229362000, 0.6461169000, 1.3612063000", \ - "0.3138809000, 0.3179326000, 0.3287315000, 0.3554766000, 0.4277539000, 0.6505365000, 1.3651553000", \ - "0.3250487000, 0.3290167000, 0.3398152000, 0.3665758000, 0.4387571000, 0.6619108000, 1.3757839000", \ - "0.3505496000, 0.3546360000, 0.3654202000, 0.3921210000, 0.4643492000, 0.6875344000, 1.4027717000", \ - "0.3997288000, 0.4037523000, 0.4145115000, 0.4412579000, 0.5134894000, 0.7363160000, 1.4486770000", \ - "0.4699955000, 0.4740689000, 0.4848545000, 0.5116406000, 0.5836972000, 0.8068779000, 1.5211742000", \ - "0.5612830000, 0.5653789000, 0.5761729000, 0.6028721000, 0.6751761000, 0.8979130000, 1.6094147000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0251534000, 0.0273668000, 0.0334219000, 0.0478518000, 0.0876614000, 0.2130022000, 0.6438026000", \ - "0.0251338000, 0.0274114000, 0.0333146000, 0.0478677000, 0.0875419000, 0.2135674000, 0.6386447000", \ - "0.0253890000, 0.0274107000, 0.0334362000, 0.0479880000, 0.0881498000, 0.2131530000, 0.6426913000", \ - "0.0251928000, 0.0275064000, 0.0334238000, 0.0481445000, 0.0880971000, 0.2135807000, 0.6433800000", \ - "0.0251577000, 0.0274706000, 0.0332488000, 0.0481051000, 0.0882519000, 0.2133136000, 0.6407971000", \ - "0.0253207000, 0.0275168000, 0.0331671000, 0.0479303000, 0.0878095000, 0.2135672000, 0.6405783000", \ - "0.0252805000, 0.0273689000, 0.0331782000, 0.0479635000, 0.0881357000, 0.2136746000, 0.6373455000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016011800, 0.0051275700, 0.0164203000, 0.0525839000, 0.1683930000, 0.5392550000"); - values("0.0256564000, 0.0288226000, 0.0376848000, 0.0655489000, 0.1605730000, 0.4773022000, 1.4978202000", \ - "0.0259531000, 0.0287897000, 0.0377521000, 0.0655574000, 0.1601579000, 0.4771548000, 1.4980632000", \ - "0.0256916000, 0.0286839000, 0.0376175000, 0.0655032000, 0.1605378000, 0.4773489000, 1.4998447000", \ - "0.0257946000, 0.0287297000, 0.0376101000, 0.0655891000, 0.1606670000, 0.4768005000, 1.5022437000", \ - "0.0256285000, 0.0288452000, 0.0376969000, 0.0656338000, 0.1604235000, 0.4768450000, 1.5037555000", \ - "0.0259243000, 0.0287079000, 0.0377565000, 0.0655633000, 0.1606930000, 0.4774050000, 1.4976016000", \ - "0.0259809000, 0.0288516000, 0.0378692000, 0.0656181000, 0.1606850000, 0.4760022000, 1.5003883000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0018160000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017270000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0033588000, 0.0033527000, 0.0033386000, 0.0033463000, 0.0033640000, 0.0034050000, 0.0034994000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003223900, -0.003222200, -0.003218200, -0.003228900, -0.003253800, -0.003311000, -0.003442800"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_in"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019050000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2620098000, 0.4383932000, 0.7256653000", \ - "0.1429994000, 0.3206035000, 0.6078756000", \ - "0.0583639000, 0.2347474000, 0.5232402000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1448223000, 0.2772604000, 0.4180482000", \ - "0.0660950000, 0.1948711000, 0.3246725000", \ - "0.0388327000, 0.1663880000, 0.2925274000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.144484400, -0.314764300, -0.550766900", \ - "-0.059653600, -0.232375000, -0.495233100", \ - "0.0078919000, -0.166050100, -0.437453100"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.094435500, -0.217108100, -0.327378200", \ - "-0.038901700, -0.162794900, -0.279168600", \ - "-0.021404900, -0.145298200, -0.262892600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0033760000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031910000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0126551000, 0.0125607000, 0.0123432000, 0.0124102000, 0.0125647000, 0.0129209000, 0.0137420000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0002628000, 0.0001797000, -1.201075e-05, 2.338813e-05, 0.0001050000, 0.0002931000, 0.0007268000"); - } - } - max_transition : 1.5000000000; - nextstate_type : "scan_enable"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035610000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2266094000, 0.4078756000, 0.6975892000", \ - "0.1063783000, 0.2876445000, 0.5797995000", \ - "0.0180807000, 0.2005677000, 0.4915019000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2632305000, 0.3529440000, 0.3936341000", \ - "0.1454408000, 0.2351543000, 0.2758444000", \ - "0.0608053000, 0.1505189000, 0.1912090000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.128615200, -0.304998700, -0.555649800", \ - "-0.026694700, -0.206740200, -0.478143200", \ - "0.0493958000, -0.130649700, -0.409377000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.081007800, -0.209783900, -0.300522800", \ - "-0.026694700, -0.149367200, -0.242547500", \ - "-0.010418600, -0.131870400, -0.223830100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "D"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sdlclkp_1") { - leakage_power () { - value : 0.0145267000; - when : "CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0086087000; - when : "!CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0087652000; - when : "!CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0064946000; - when : "CLK&!GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0078874000; - when : "!CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0138833000; - when : "!CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0063381000; - when : "CLK&GATE&GCLK&!SCE"; - } - leakage_power () { - value : 0.0056168000; - when : "CLK&GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0152239000; - when : "CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0153805000; - when : "CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0145026000; - when : "CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0070803000; - when : "CLK&!GATE&GCLK&!SCE"; - } - clock_gating_integrated_cell : "latch_posedge_precontrol"; - area : 18.768000000; - cell_footprint : "sky130_fd_sc_hd__sdlclkp"; - cell_leakage_power : 0.0103590100; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0036450000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0034960000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0189737000, 0.0188547000, 0.0185804000, 0.0186450000, 0.0187940000, 0.0191374000, 0.0199291000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0086706000, 0.0085649000, 0.0083213000, 0.0083598000, 0.0084484000, 0.0086530000, 0.0091244000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0037930000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1315825000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0018960000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017500000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0240324000, 0.0238104000, 0.0232988000, 0.0234136000, 0.0236779000, 0.0242874000, 0.0256924000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0148456000, 0.0147999000, 0.0146945000, 0.0147266000, 0.0148005000, 0.0149712000, 0.0153647000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020410000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1741191000, 0.3724753000, 0.6634095000", \ - "0.0807435000, 0.2778789000, 0.5688132000", \ - "0.0278464000, 0.2213197000, 0.5098125000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.0972148000, 0.2174460000, 0.2996400000", \ - "0.0404603000, 0.1521465000, 0.2270163000", \ - "0.0864401000, 0.1993470000, 0.2693340000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.167677700, -0.363592400, -0.641099000", \ - "-0.076743500, -0.273878900, -0.563592500", \ - "-0.023846400, -0.217319700, -0.505812500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.049269500, -0.162176400, -0.228501300", \ - "-0.001059900, -0.107863300, -0.170526000", \ - "0.0054505000, -0.100132200, -0.162794900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0075816000, 0.0067775000, 0.0044194000, -0.003603000, -0.026301200, -0.085624100, -0.239838400", \ - "0.0073402000, 0.0065157000, 0.0041453000, -0.003837100, -0.026518800, -0.085646400, -0.239915400", \ - "0.0074023000, 0.0065768000, 0.0042229000, -0.003753300, -0.026419400, -0.085722500, -0.240011400", \ - "0.0069928000, 0.0062265000, 0.0038397000, -0.004127300, -0.026727200, -0.086055900, -0.240307500", \ - "0.0069671000, 0.0059544000, 0.0035263000, -0.004399900, -0.027051500, -0.086249400, -0.240499400", \ - "0.0086378000, 0.0072882000, 0.0038825000, -0.004847400, -0.026940700, -0.085805800, -0.239885300", \ - "0.0099694000, 0.0086074000, 0.0052125000, -0.003579900, -0.026224300, -0.084176900, -0.239337300"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0099006000, 0.0114540000, 0.0150838000, 0.0238682000, 0.0464720000, 0.1045893000, 0.2573797000", \ - "0.0097973000, 0.0113578000, 0.0149895000, 0.0237789000, 0.0461848000, 0.1048883000, 0.2572827000", \ - "0.0096381000, 0.0112042000, 0.0148661000, 0.0236417000, 0.0461098000, 0.1045027000, 0.2583924000", \ - "0.0087090000, 0.0103215000, 0.0140128000, 0.0228271000, 0.0453460000, 0.1044791000, 0.2576758000", \ - "0.0082155000, 0.0098641000, 0.0136424000, 0.0224164000, 0.0449701000, 0.1042013000, 0.2572919000", \ - "0.0092451000, 0.0105806000, 0.0139659000, 0.0226352000, 0.0452041000, 0.1032692000, 0.2574951000", \ - "0.0102150000, 0.0117467000, 0.0150273000, 0.0238855000, 0.0464229000, 0.1051931000, 0.2561028000"); - } - } - max_capacitance : 0.1547340000; - max_transition : 1.5031300000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0904573000, 0.0958718000, 0.1069883000, 0.1296244000, 0.1792769000, 0.3020517000, 0.6202690000", \ - "0.0953949000, 0.1007864000, 0.1120134000, 0.1346964000, 0.1843420000, 0.3071804000, 0.6264800000", \ - "0.1081883000, 0.1135728000, 0.1247917000, 0.1474603000, 0.1971962000, 0.3202258000, 0.6393647000", \ - "0.1400199000, 0.1452007000, 0.1564977000, 0.1792295000, 0.2291408000, 0.3521054000, 0.6714662000", \ - "0.2076482000, 0.2136295000, 0.2257383000, 0.2495084000, 0.2998355000, 0.4229016000, 0.7419865000", \ - "0.3172621000, 0.3249165000, 0.3398947000, 0.3670125000, 0.4204803000, 0.5451871000, 0.8638505000", \ - "0.4887696000, 0.4989505000, 0.5187649000, 0.5532573000, 0.6132799000, 0.7398130000, 1.0589664000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0876769000, 0.0951814000, 0.1118931000, 0.1500135000, 0.2445892000, 0.4903770000, 1.1339722000", \ - "0.0917952000, 0.0992759000, 0.1160076000, 0.1541390000, 0.2487962000, 0.4946096000, 1.1341724000", \ - "0.1000704000, 0.1075899000, 0.1242924000, 0.1624135000, 0.2570928000, 0.5031069000, 1.1443024000", \ - "0.1184132000, 0.1259366000, 0.1426900000, 0.1809356000, 0.2759943000, 0.5231279000, 1.1647300000", \ - "0.1497300000, 0.1578726000, 0.1755530000, 0.2148565000, 0.3105957000, 0.5577205000, 1.1989899000", \ - "0.1906350000, 0.2004347000, 0.2200213000, 0.2608866000, 0.3571573000, 0.6041495000, 1.2465279000", \ - "0.2230221000, 0.2354625000, 0.2604109000, 0.3060783000, 0.4032671000, 0.6505395000, 1.2899141000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0182656000, 0.0223873000, 0.0316286000, 0.0541644000, 0.1128185000, 0.2745842000, 0.6974499000", \ - "0.0181502000, 0.0224118000, 0.0317490000, 0.0540101000, 0.1128870000, 0.2736568000, 0.6992306000", \ - "0.0182668000, 0.0224230000, 0.0318042000, 0.0539549000, 0.1128988000, 0.2736047000, 0.6993383000", \ - "0.0183615000, 0.0225042000, 0.0316612000, 0.0540726000, 0.1128860000, 0.2737082000, 0.6985477000", \ - "0.0217847000, 0.0256415000, 0.0345802000, 0.0560264000, 0.1134718000, 0.2740607000, 0.7025360000", \ - "0.0312087000, 0.0356566000, 0.0443388000, 0.0643633000, 0.1196907000, 0.2753231000, 0.7007764000", \ - "0.0458103000, 0.0512494000, 0.0619576000, 0.0821835000, 0.1318380000, 0.2798085000, 0.6966104000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0249400000, 0.0323252000, 0.0509220000, 0.1000677000, 0.2338733000, 0.5836971000, 1.5031296000", \ - "0.0249835000, 0.0323374000, 0.0509422000, 0.1000457000, 0.2338718000, 0.5855380000, 1.4965559000", \ - "0.0250394000, 0.0323839000, 0.0510707000, 0.1001307000, 0.2335614000, 0.5862402000, 1.5024878000", \ - "0.0255129000, 0.0327897000, 0.0511718000, 0.1003044000, 0.2333942000, 0.5850431000, 1.4995201000", \ - "0.0286794000, 0.0358542000, 0.0538375000, 0.1027475000, 0.2336763000, 0.5860035000, 1.5001902000", \ - "0.0355252000, 0.0428206000, 0.0597996000, 0.1054300000, 0.2358087000, 0.5850207000, 1.5025636000", \ - "0.0493273000, 0.0579469000, 0.0760430000, 0.1162765000, 0.2383337000, 0.5873906000, 1.4975616000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - pin ("SCE") { - clock_gate_test_pin : "true"; - capacitance : 0.0018290000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017460000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0251342000, 0.0249509000, 0.0245284000, 0.0246196000, 0.0248295000, 0.0253137000, 0.0264298000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0159511000, 0.0158870000, 0.0157393000, 0.0157680000, 0.0158340000, 0.0159865000, 0.0163379000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019130000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1851055000, 0.3578268000, 0.6072572000", \ - "0.0905091000, 0.2644512000, 0.5163229000", \ - "0.0339499000, 0.2066712000, 0.4597637000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1094219000, 0.2394186000, 0.3472474000", \ - "0.0538880000, 0.1765605000, 0.2746237000", \ - "0.1010885000, 0.2237611000, 0.3206035000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.178664100, -0.350164700, -0.589829400", \ - "-0.086509100, -0.260451200, -0.511102200", \ - "-0.029949900, -0.202671200, -0.455763700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.059035200, -0.184149100, -0.278550100", \ - "-0.015708300, -0.132277300, -0.219354200", \ - "-0.014080700, -0.128208300, -0.211623000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - statetable ("CLK GATE SCE","M0") { - table : "L L L : - : L,L L H : - : H,L H L : - : H,L H H : - : H,H - - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__sdlclkp_2") { - leakage_power () { - value : 0.0143531000; - when : "CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0085959000; - when : "!CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0087561000; - when : "!CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0065667000; - when : "CLK&!GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0078800000; - when : "!CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0136527000; - when : "!CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0064065000; - when : "CLK&GATE&GCLK&!SCE"; - } - leakage_power () { - value : 0.0056907000; - when : "CLK&GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0150433000; - when : "CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0152035000; - when : "CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0143275000; - when : "CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0071557000; - when : "CLK&!GATE&GCLK&!SCE"; - } - clock_gating_integrated_cell : "latch_posedge_precontrol"; - area : 20.019200000; - cell_footprint : "sky130_fd_sc_hd__sdlclkp"; - cell_leakage_power : 0.0103026300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0036390000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0034790000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0191972000, 0.0190679000, 0.0187698000, 0.0188166000, 0.0189246000, 0.0191737000, 0.0197477000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0087095000, 0.0086068000, 0.0083703000, 0.0084106000, 0.0085035000, 0.0087179000, 0.0092119000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0038000000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1315825000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0019120000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017610000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0240939000, 0.0238719000, 0.0233601000, 0.0234836000, 0.0237683000, 0.0244244000, 0.0259371000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0150224000, 0.0149707000, 0.0148514000, 0.0148670000, 0.0149028000, 0.0149856000, 0.0151764000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020620000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1753398000, 0.3736960000, 0.6658509000", \ - "0.0807435000, 0.2790996000, 0.5688132000", \ - "0.0266257000, 0.2213197000, 0.5098125000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1191875000, 0.2369772000, 0.3216126000", \ - "0.0477845000, 0.1594707000, 0.2367819000", \ - "0.0925436000, 0.2042298000, 0.2778789000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.155470700, -0.350164700, -0.622788400", \ - "-0.073081400, -0.268996100, -0.555047500", \ - "-0.020184200, -0.213657500, -0.499709000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.049269500, -0.162176400, -0.229722000", \ - "-0.001059900, -0.107863300, -0.170526000", \ - "0.0054505000, -0.100132200, -0.162794900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0118863000, 0.0104883000, 0.0066947000, -0.004868000, -0.042014400, -0.151964200, -0.471996800", \ - "0.0117084000, 0.0102982000, 0.0065019000, -0.005053000, -0.042189000, -0.152154000, -0.472178700", \ - "0.0118254000, 0.0104213000, 0.0066150000, -0.004932400, -0.042034200, -0.152007000, -0.472041700", \ - "0.0113729000, 0.0099817000, 0.0061552000, -0.005429700, -0.042497400, -0.152418300, -0.472426900", \ - "0.0111333000, 0.0096786000, 0.0058175000, -0.005891000, -0.042898200, -0.152671400, -0.472692300", \ - "0.0125222000, 0.0109425000, 0.0064695000, -0.006483500, -0.042922500, -0.152590900, -0.472513500", \ - "0.0154954000, 0.0136858000, 0.0089877000, -0.004219400, -0.042032800, -0.151557700, -0.471376100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0150209000, 0.0166817000, 0.0214403000, 0.0347998000, 0.0724042000, 0.1812477000, 0.4970965000", \ - "0.0149240000, 0.0165995000, 0.0214067000, 0.0347356000, 0.0723446000, 0.1812073000, 0.4975157000", \ - "0.0148421000, 0.0165153000, 0.0212823000, 0.0346333000, 0.0722999000, 0.1810111000, 0.4997115000", \ - "0.0140304000, 0.0157125000, 0.0204913000, 0.0338196000, 0.0714888000, 0.1804422000, 0.4959570000", \ - "0.0136827000, 0.0153081000, 0.0200537000, 0.0333089000, 0.0710425000, 0.1798790000, 0.4985268000", \ - "0.0145183000, 0.0160644000, 0.0205423000, 0.0334892000, 0.0709783000, 0.1793094000, 0.4987799000", \ - "0.0156555000, 0.0171380000, 0.0215613000, 0.0344499000, 0.0723501000, 0.1810150000, 0.4951899000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5010830000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1143057000, 0.1193031000, 0.1303296000, 0.1526770000, 0.1990867000, 0.3121771000, 0.6316708000", \ - "0.1195249000, 0.1245261000, 0.1355377000, 0.1579002000, 0.2043600000, 0.3174750000, 0.6369646000", \ - "0.1326405000, 0.1375296000, 0.1485248000, 0.1710091000, 0.2175023000, 0.3304872000, 0.6501014000", \ - "0.1642643000, 0.1693067000, 0.1802694000, 0.2025534000, 0.2490790000, 0.3623905000, 0.6817444000", \ - "0.2381915000, 0.2431635000, 0.2543171000, 0.2768136000, 0.3235495000, 0.4368608000, 0.7553285000", \ - "0.3681278000, 0.3746874000, 0.3890493000, 0.4161459000, 0.4672869000, 0.5828427000, 0.9019693000", \ - "0.5731703000, 0.5818425000, 0.6010702000, 0.6370442000, 0.6990958000, 0.8209403000, 1.1411497000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1063039000, 0.1127402000, 0.1274404000, 0.1608062000, 0.2435342000, 0.4764074000, 1.1548617000", \ - "0.1105737000, 0.1169227000, 0.1317496000, 0.1650215000, 0.2479289000, 0.4808163000, 1.1565002000", \ - "0.1191067000, 0.1255710000, 0.1402903000, 0.1736272000, 0.2563799000, 0.4905941000, 1.1668070000", \ - "0.1385868000, 0.1449325000, 0.1596962000, 0.1929661000, 0.2759011000, 0.5089925000, 1.1872522000", \ - "0.1761397000, 0.1829601000, 0.1985979000, 0.2329731000, 0.3165222000, 0.5507352000, 1.2262664000", \ - "0.2306991000, 0.2388746000, 0.2566927000, 0.2936389000, 0.3787921000, 0.6127104000, 1.2878504000", \ - "0.2867304000, 0.2974438000, 0.3205152000, 0.3639453000, 0.4530734000, 0.6876711000, 1.3625516000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0210562000, 0.0240594000, 0.0314155000, 0.0491301000, 0.0959888000, 0.2361581000, 0.6675906000", \ - "0.0210573000, 0.0240447000, 0.0313854000, 0.0491357000, 0.0959034000, 0.2362021000, 0.6677077000", \ - "0.0209837000, 0.0240096000, 0.0313781000, 0.0490924000, 0.0962604000, 0.2361336000, 0.6624474000", \ - "0.0210208000, 0.0240896000, 0.0315168000, 0.0491584000, 0.0962727000, 0.2368174000, 0.6591468000", \ - "0.0225720000, 0.0256755000, 0.0325911000, 0.0499347000, 0.0964315000, 0.2367968000, 0.6674044000", \ - "0.0333947000, 0.0368041000, 0.0450949000, 0.0612350000, 0.1045662000, 0.2391772000, 0.6652567000", \ - "0.0510823000, 0.0556184000, 0.0654878000, 0.0845000000, 0.1257720000, 0.2500079000, 0.6616659000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0242997000, 0.0294767000, 0.0428245000, 0.0796293000, 0.1906719000, 0.5254298000, 1.4980586000", \ - "0.0243484000, 0.0295000000, 0.0428352000, 0.0796886000, 0.1901119000, 0.5238791000, 1.4990050000", \ - "0.0243776000, 0.0295093000, 0.0428871000, 0.0796624000, 0.1904091000, 0.5240277000, 1.5010442000", \ - "0.0244072000, 0.0296170000, 0.0429768000, 0.0797825000, 0.1905794000, 0.5252961000, 1.4967726000", \ - "0.0273903000, 0.0324254000, 0.0456744000, 0.0817481000, 0.1911046000, 0.5248171000, 1.5010830000", \ - "0.0345964000, 0.0399413000, 0.0530063000, 0.0872438000, 0.1943964000, 0.5242434000, 1.4974950000", \ - "0.0486425000, 0.0552024000, 0.0695868000, 0.1012115000, 0.2003212000, 0.5258408000, 1.4959326000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - pin ("SCE") { - clock_gate_test_pin : "true"; - capacitance : 0.0018270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017430000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0251651000, 0.0249791000, 0.0245503000, 0.0246278000, 0.0248065000, 0.0252186000, 0.0261685000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0161167000, 0.0160525000, 0.0159046000, 0.0159360000, 0.0160083000, 0.0161753000, 0.0165600000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019100000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1863262000, 0.3602682000, 0.6096986000", \ - "0.0905091000, 0.2644512000, 0.5163229000", \ - "0.0327292000, 0.2054505000, 0.4597637000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1301738000, 0.2601706000, 0.3679993000", \ - "0.0599915000, 0.1838848000, 0.2843893000", \ - "0.1059714000, 0.2274232000, 0.3267070000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.166457000, -0.336737000, -0.572739600", \ - "-0.082847000, -0.255568400, -0.503778000", \ - "-0.025067100, -0.199009100, -0.449660200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.059035200, -0.184149100, -0.278550100", \ - "-0.015708300, -0.133498000, -0.220574900", \ - "-0.014080700, -0.128208300, -0.212843800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - statetable ("CLK GATE SCE","M0") { - table : "L L L : - : L,L L H : - : H,L H L : - : H,L H H : - : H,H - - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__sdlclkp_4") { - leakage_power () { - value : 0.0135191000; - when : "CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0077669000; - when : "!CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0079271000; - when : "!CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0085404000; - when : "CLK&!GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0070510000; - when : "!CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0128507000; - when : "!CLK&!GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0083802000; - when : "CLK&GATE&GCLK&!SCE"; - } - leakage_power () { - value : 0.0076644000; - when : "CLK&GATE&GCLK&SCE"; - } - leakage_power () { - value : 0.0142094000; - when : "CLK&GATE&!GCLK&!SCE"; - } - leakage_power () { - value : 0.0143696000; - when : "CLK&!GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0134935000; - when : "CLK&GATE&!GCLK&SCE"; - } - leakage_power () { - value : 0.0091294000; - when : "CLK&!GATE&GCLK&!SCE"; - } - clock_gating_integrated_cell : "latch_posedge_precontrol"; - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__sdlclkp"; - cell_leakage_power : 0.0104084700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - clock_gate_clock_pin : "true"; - capacitance : 0.0042780000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0040700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0200766000, 0.0199605000, 0.0196930000, 0.0197603000, 0.0199155000, 0.0202732000, 0.0210977000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0078229000, 0.0077458000, 0.0075681000, 0.0075854000, 0.0076253000, 0.0077170000, 0.0079288000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0044860000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1328031000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "GCLK"; - related_pin : "CLK"; - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GATE") { - clock_gate_enable_pin : "true"; - capacitance : 0.0019350000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0254630000, 0.0252385000, 0.0247208000, 0.0248344000, 0.0250961000, 0.0256996000, 0.0270909000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155740000, 0.0155419000, 0.0154679000, 0.0154760000, 0.0154947000, 0.0155381000, 0.0156381000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0020970000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1777813000, 0.3761374000, 0.6682923000", \ - "0.0831849000, 0.2803203000, 0.5712545000", \ - "0.0278464000, 0.2213197000, 0.5122539000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1362773000, 0.2552878000, 0.3399232000", \ - "0.0685365000, 0.1826641000, 0.2611960000", \ - "0.1377096000, 0.2506165000, 0.3279277000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.153029300, -0.347723300, -0.616684900", \ - "-0.073081400, -0.268996100, -0.553826800", \ - "-0.020184200, -0.214878300, -0.500929700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.050490200, -0.164617800, -0.232163400", \ - "-0.002280600, -0.110304700, -0.174188100", \ - "0.0042298000, -0.102573600, -0.165236300"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("GCLK") { - clock_gate_out_pin : "true"; - direction : "output"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0228297000, 0.0211444000, 0.0157963000, -0.000303900, -0.055925600, -0.240742200, -0.833718800", \ - "0.0225894000, 0.0208539000, 0.0155840000, -0.000543700, -0.056143000, -0.240936500, -0.833891100", \ - "0.0226739000, 0.0209749000, 0.0156878000, -0.000454300, -0.056066600, -0.240821500, -0.833780900", \ - "0.0221899000, 0.0204408000, 0.0152008000, -0.001015400, -0.056581600, -0.241300600, -0.834231900", \ - "0.0218615000, 0.0201467000, 0.0146963000, -0.001595700, -0.057220700, -0.241749800, -0.834598300", \ - "0.0218145000, 0.0199020000, 0.0143429000, -0.002007300, -0.057296900, -0.241735400, -0.834437600", \ - "0.0292502000, 0.0270589000, 0.0207209000, 0.0020491000, -0.055994500, -0.240643100, -0.833252100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015979950, 0.0051071750, 0.0163224800, 0.0521664800, 0.1667235000, 0.5328467000"); - values("0.0275072000, 0.0294145000, 0.0354067000, 0.0541528000, 0.1120253000, 0.2953011000, 0.8814294000", \ - "0.0274028000, 0.0293544000, 0.0352886000, 0.0540633000, 0.1119618000, 0.2955966000, 0.8802002000", \ - "0.0272478000, 0.0291903000, 0.0351374000, 0.0539261000, 0.1118780000, 0.2950976000, 0.8848013000", \ - "0.0263797000, 0.0282807000, 0.0342585000, 0.0529610000, 0.1110078000, 0.2945861000, 0.8850531000", \ - "0.0260817000, 0.0279647000, 0.0338580000, 0.0524461000, 0.1103296000, 0.2938008000, 0.8798787000", \ - "0.0276121000, 0.0293549000, 0.0350313000, 0.0530224000, 0.1107236000, 0.2936361000, 0.8817439000", \ - "0.0294814000, 0.0312877000, 0.0366339000, 0.0547468000, 0.1128655000, 0.2959341000, 0.8786598000"); - } - } - max_capacitance : 0.5328470000; - max_transition : 1.5053330000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - state_function : "(CLK*M0)"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1346470000, 0.1383213000, 0.1476195000, 0.1683496000, 0.2121010000, 0.3170668000, 0.6262973000", \ - "0.1399125000, 0.1435221000, 0.1528752000, 0.1736278000, 0.2174373000, 0.3224192000, 0.6316908000", \ - "0.1530609000, 0.1566957000, 0.1660008000, 0.1867505000, 0.2306520000, 0.3355173000, 0.6449091000", \ - "0.1848798000, 0.1884762000, 0.1977523000, 0.2185343000, 0.2624175000, 0.3673086000, 0.6766460000", \ - "0.2599627000, 0.2635462000, 0.2727901000, 0.2935402000, 0.3373976000, 0.4423822000, 0.7518620000", \ - "0.4031952000, 0.4078052000, 0.4194732000, 0.4442793000, 0.4925281000, 0.5999241000, 0.9093753000", \ - "0.6331213000, 0.6392326000, 0.6546452000, 0.6878028000, 0.7484541000, 0.8654703000, 1.1764346000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.1108975000, 0.1152863000, 0.1270147000, 0.1557349000, 0.2301474000, 0.4542507000, 1.1666051000", \ - "0.1151464000, 0.1196096000, 0.1312782000, 0.1599732000, 0.2343195000, 0.4582473000, 1.1747593000", \ - "0.1238560000, 0.1282821000, 0.1398834000, 0.1685869000, 0.2430667000, 0.4680811000, 1.1814774000", \ - "0.1432260000, 0.1476039000, 0.1592851000, 0.1879576000, 0.2623352000, 0.4868332000, 1.2014609000", \ - "0.1810058000, 0.1857603000, 0.1979922000, 0.2276572000, 0.3027839000, 0.5280992000, 1.2395857000", \ - "0.2341616000, 0.2397010000, 0.2537552000, 0.2860504000, 0.3633867000, 0.5883343000, 1.3028064000", \ - "0.2828799000, 0.2900674000, 0.3083257000, 0.3471818000, 0.4295146000, 0.6553885000, 1.3679835000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0254057000, 0.0275594000, 0.0332197000, 0.0478072000, 0.0868157000, 0.2076053000, 0.6192068000", \ - "0.0254649000, 0.0275922000, 0.0332956000, 0.0474922000, 0.0868529000, 0.2075331000, 0.6191179000", \ - "0.0255018000, 0.0277057000, 0.0334747000, 0.0478735000, 0.0868819000, 0.2077429000, 0.6152877000", \ - "0.0255031000, 0.0276948000, 0.0334474000, 0.0478243000, 0.0866654000, 0.2076813000, 0.6153763000", \ - "0.0258502000, 0.0278459000, 0.0335557000, 0.0479305000, 0.0869943000, 0.2077496000, 0.6152582000", \ - "0.0376844000, 0.0400220000, 0.0458992000, 0.0597170000, 0.0951434000, 0.2111869000, 0.6191460000", \ - "0.0580310000, 0.0615543000, 0.0696386000, 0.0853020000, 0.1198749000, 0.2256337000, 0.6174070000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015979900, 0.0051071800, 0.0163225000, 0.0521665000, 0.1667240000, 0.5328470000"); - values("0.0261095000, 0.0293778000, 0.0395817000, 0.0689520000, 0.1640302000, 0.4824502000, 1.4985336000", \ - "0.0258701000, 0.0295285000, 0.0395493000, 0.0690101000, 0.1640908000, 0.4808879000, 1.5043921000", \ - "0.0260347000, 0.0295919000, 0.0395250000, 0.0689584000, 0.1641430000, 0.4822261000, 1.5053334000", \ - "0.0261575000, 0.0296931000, 0.0396567000, 0.0691375000, 0.1642105000, 0.4818361000, 1.5051118000", \ - "0.0289366000, 0.0324294000, 0.0424587000, 0.0710287000, 0.1648295000, 0.4809593000, 1.5008516000", \ - "0.0366961000, 0.0403742000, 0.0501498000, 0.0776576000, 0.1684897000, 0.4803149000, 1.5032359000", \ - "0.0511559000, 0.0565481000, 0.0667324000, 0.0931018000, 0.1767212000, 0.4832287000, 1.4990376000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - pin ("M0") { - direction : "internal"; - internal_node : "M0"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - } - pin ("SCE") { - clock_gate_test_pin : "true"; - capacitance : 0.0018340000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0017450000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0265172000, 0.0263308000, 0.0259013000, 0.0259824000, 0.0261691000, 0.0265997000, 0.0275923000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0167305000, 0.0166781000, 0.0165574000, 0.0165815000, 0.0166370000, 0.0167652000, 0.0170608000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0019230000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1887676000, 0.3614889000, 0.6121400000", \ - "0.0917298000, 0.2656719000, 0.5187643000", \ - "0.0339499000, 0.2066712000, 0.4609844000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1472637000, 0.2772604000, 0.3875306000", \ - "0.0807435000, 0.2058574000, 0.3088034000", \ - "0.1511374000, 0.2738099000, 0.3755351000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.164015600, -0.333074900, -0.567856800", \ - "-0.082847000, -0.255568400, -0.503778000", \ - "-0.026287800, -0.199009100, -0.450880900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.060255900, -0.186590500, -0.280991500", \ - "-0.016929000, -0.134718700, -0.223016300", \ - "-0.015301400, -0.130649700, -0.215285200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - statetable ("CLK GATE SCE","M0") { - table : "L L L : - : L,L L H : - : H,L H L : - : H,L H H : - : H,H - - : - : N"; - } - } - - cell ("sky130_fd_sc_hd__sedfxbp_1") { - leakage_power () { - value : 0.0131199000; - when : "CLK&!D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0120576000; - when : "CLK&D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0175008000; - when : "CLK&D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0141019000; - when : "CLK&D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0141729000; - when : "!CLK&D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0167519000; - when : "CLK&D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0124185000; - when : "CLK&!D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0145370000; - when : "CLK&!D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0136964000; - when : "CLK&!D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0130273000; - when : "!CLK&!D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0138849000; - when : "CLK&D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0158189000; - when : "CLK&!D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0134120000; - when : "!CLK&!D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0136700000; - when : "CLK&!D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0183844000; - when : "CLK&D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0126333000; - when : "CLK&D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0160338000; - when : "CLK&D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0136268000; - when : "!CLK&D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0132854000; - when : "CLK&!D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0166859000; - when : "CLK&!D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0142789000; - when : "!CLK&!D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0174951000; - when : "CLK&D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0181263000; - when : "!CLK&D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0135309000; - when : "CLK&!D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0115669000; - when : "CLK&D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0153358000; - when : "CLK&D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0145926000; - when : "CLK&D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0136822000; - when : "!CLK&D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0128008000; - when : "CLK&D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0152446000; - when : "CLK&!D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0128933000; - when : "CLK&!D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0162922000; - when : "CLK&!D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0137075000; - when : "!CLK&!D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0141272000; - when : "CLK&!D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0149658000; - when : "CLK&D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0123811000; - when : "!CLK&D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0143715000; - when : "CLK&!D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0148249000; - when : "!CLK&!D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0149161000; - when : "!CLK&D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0162612000; - when : "CLK&D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0128294000; - when : "CLK&!D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0134383000; - when : "!CLK&!D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0121604000; - when : "!CLK&!D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0130443000; - when : "CLK&D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0123753000; - when : "!CLK&D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0129643000; - when : "!CLK&!D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0133840000; - when : "CLK&!D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0116379000; - when : "!CLK&D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0125713000; - when : "!CLK&!D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0127862000; - when : "!CLK&D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0124736000; - when : "!CLK&!D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0111472000; - when : "!CLK&D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0127414000; - when : "!CLK&!D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0159136000; - when : "!CLK&!D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0148775000; - when : "!CLK&!D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0131523000; - when : "!CLK&!D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0145872000; - when : "!CLK&D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0139930000; - when : "!CLK&!D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0150924000; - when : "!CLK&D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0157445000; - when : "!CLK&!D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0158105000; - when : "!CLK&D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0153198000; - when : "!CLK&D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0171222000; - when : "!CLK&D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0165538000; - when : "!CLK&D&DE&SCE&SCD&!Q&Q_N"; - } - area : 38.787200000; - cell_footprint : "sky130_fd_sc_hd__sedfxbp"; - cell_leakage_power : 0.0142489800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017580000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0273525000, 0.0272327000, 0.0269566000, 0.0269812000, 0.0270382000, 0.0271694000, 0.0274719000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226297000, 0.0225224000, 0.0222749000, 0.0222694000, 0.0222569000, 0.0222283000, 0.0221623000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018440000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3235761000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3949793000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0017660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156923000, 0.0155279000, 0.0151491000, 0.0152154000, 0.0153684000, 0.0157213000, 0.0165347000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092526000, 0.0092334000, 0.0091890000, 0.0092005000, 0.0092272000, 0.0092888000, 0.0094306000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4060527000, 0.5995260000, 0.9368470000", \ - "0.2772767000, 0.4695293000, 0.8117331000", \ - "0.1755514000, 0.3702454000, 0.7124492000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2070781000, 0.3627096000, 0.5498841000", \ - "0.1442201000, 0.3010723000, 0.4833639000", \ - "0.1206198000, 0.2762513000, 0.4609844000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.322707000, -0.514959600, -0.846177100", \ - "-0.214682900, -0.409377000, -0.743035800", \ - "-0.127606100, -0.322300100, -0.662062500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.339178400, -0.512925200", \ - "-0.125571600, -0.278761700, -0.456170600", \ - "-0.101971400, -0.255161500, -0.437453100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0033020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112413000, 0.0111013000, 0.0107789000, 0.0108460000, 0.0110010000, 0.0113582000, 0.0121817000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001637000, 2.436794e-05, -0.000296800, -0.000241000, -0.000112100, 0.0001850000, 0.0008698000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034290000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3926250000, 0.5787741000, 0.9136536000", \ - "0.2833802000, 0.4683086000, 0.8068502000", \ - "0.1901999000, 0.3775697000, 0.7185528000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4426738000, 0.5336081000, 0.5718568000", \ - "0.3151185000, 0.4048320000, 0.4430807000", \ - "0.2133932000, 0.3031068000, 0.3413555000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.244582000, -0.412420600, -0.594712200", \ - "-0.182944700, -0.349562500, -0.530633400", \ - "-0.155682300, -0.323520800, -0.504591800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.337957700, -0.504380200", \ - "-0.140220100, -0.277541000, -0.445184200", \ - "-0.119061200, -0.256382100, -0.425246100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("-0.007974100, -0.003347200, 0.0051912000, 0.0141234000, 0.0079795000, -0.044240100, -0.209482800", \ - "-0.007923100, -0.003297900, 0.0052093000, 0.0141567000, 0.0080045000, -0.044313600, -0.209560600", \ - "-0.007817200, -0.003217100, 0.0052382000, 0.0141145000, 0.0078287000, -0.044472400, -0.209763200", \ - "-0.007830900, -0.003256900, 0.0051615000, 0.0139492000, 0.0076276000, -0.044735600, -0.210041900", \ - "-0.007850500, -0.003312100, 0.0050300000, 0.0137105000, 0.0072645000, -0.045112600, -0.210461400", \ - "-0.007840900, -0.003310800, 0.0050121000, 0.0136628000, 0.0071602000, -0.045297100, -0.210612600", \ - "-0.007748500, -0.003129900, 0.0053671000, 0.0142698000, 0.0080655000, -0.044516500, -0.209774600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013213260, 0.0034918040, 0.0092276230, 0.0243853900, 0.0644421000, 0.1702980000"); - values("-0.009280700, -0.006185400, 0.0009084000, 0.0156913000, 0.0457979000, 0.1133997000, 0.2866322000", \ - "-0.009228900, -0.006144600, 0.0009366000, 0.0156940000, 0.0458689000, 0.1139237000, 0.2864454000", \ - "-0.009116600, -0.006040800, 0.0010060000, 0.0157382000, 0.0457880000, 0.1138262000, 0.2865146000", \ - "-0.009130900, -0.006088600, 0.0009091000, 0.0155451000, 0.0455135000, 0.1135224000, 0.2841949000", \ - "-0.009141600, -0.006126400, 0.0008198000, 0.0153765000, 0.0452524000, 0.1126382000, 0.2860323000", \ - "-0.009134800, -0.006122100, 0.0008079000, 0.0153402000, 0.0452079000, 0.1132404000, 0.2857521000", \ - "-0.009036100, -0.005927500, 0.0012008000, 0.0159847000, 0.0458102000, 0.1135617000, 0.2847631000"); - } - } - max_capacitance : 0.1702980000; - max_transition : 1.4997530000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.3263357000, 0.3382647000, 0.3627686000, 0.4088158000, 0.4933585000, 0.6518357000, 1.0047720000", \ - "0.3309564000, 0.3429090000, 0.3674259000, 0.4134279000, 0.4980688000, 0.6565219000, 1.0092021000", \ - "0.3419546000, 0.3539218000, 0.3784332000, 0.4244537000, 0.5090789000, 0.6675289000, 1.0204583000", \ - "0.3676434000, 0.3796295000, 0.4041161000, 0.4500503000, 0.5346844000, 0.6931525000, 1.0461237000", \ - "0.4171105000, 0.4290259000, 0.4540659000, 0.4998493000, 0.5844010000, 0.7428312000, 1.0957280000", \ - "0.4935843000, 0.5055084000, 0.5304802000, 0.5760788000, 0.6608684000, 0.8193866000, 1.1720267000", \ - "0.5963551000, 0.6083303000, 0.6328553000, 0.6788275000, 0.7635101000, 0.9220880000, 1.2747566000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.2960087000, 0.3049596000, 0.3242640000, 0.3665741000, 0.4674767000, 0.7166618000, 1.3654654000", \ - "0.3007437000, 0.3094347000, 0.3288461000, 0.3711295000, 0.4720271000, 0.7213820000, 1.3647280000", \ - "0.3117875000, 0.3207245000, 0.3400465000, 0.3823459000, 0.4832537000, 0.7325479000, 1.3786062000", \ - "0.3378511000, 0.3466015000, 0.3659446000, 0.4082301000, 0.5091362000, 0.7583653000, 1.4018871000", \ - "0.3884133000, 0.3971192000, 0.4165227000, 0.4588099000, 0.5597114000, 0.8090725000, 1.4550643000", \ - "0.4630046000, 0.4719631000, 0.4912474000, 0.5335694000, 0.6344700000, 0.8839054000, 1.5278342000", \ - "0.5603361000, 0.5691318000, 0.5886555000, 0.6309532000, 0.7318926000, 0.9813225000, 1.6272899000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0496010000, 0.0574263000, 0.0729397000, 0.1055282000, 0.1735628000, 0.3257916000, 0.7585395000", \ - "0.0497997000, 0.0570903000, 0.0733041000, 0.1057212000, 0.1733772000, 0.3251245000, 0.7589918000", \ - "0.0498079000, 0.0570727000, 0.0733397000, 0.1057127000, 0.1733578000, 0.3257905000, 0.7611460000", \ - "0.0499197000, 0.0578072000, 0.0731734000, 0.1056897000, 0.1736893000, 0.3257783000, 0.7574287000", \ - "0.0493779000, 0.0570757000, 0.0740884000, 0.1058252000, 0.1733631000, 0.3258095000, 0.7581091000", \ - "0.0495517000, 0.0575570000, 0.0732968000, 0.1057242000, 0.1738808000, 0.3250983000, 0.7580466000", \ - "0.0500538000, 0.0584973000, 0.0737006000, 0.1061258000, 0.1737560000, 0.3250383000, 0.7612944000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013213300, 0.0034918000, 0.0092276200, 0.0243854000, 0.0644421000, 0.1702980000"); - values("0.0315906000, 0.0391396000, 0.0578993000, 0.1070591000, 0.2381368000, 0.5775049000, 1.4989943000", \ - "0.0312908000, 0.0390136000, 0.0579541000, 0.1070415000, 0.2381496000, 0.5789111000, 1.4993549000", \ - "0.0316208000, 0.0391224000, 0.0578912000, 0.1070848000, 0.2380538000, 0.5786103000, 1.4973303000", \ - "0.0312100000, 0.0390726000, 0.0579406000, 0.1070439000, 0.2381595000, 0.5784354000, 1.4930186000", \ - "0.0313303000, 0.0389796000, 0.0579588000, 0.1070366000, 0.2381495000, 0.5785695000, 1.4968751000", \ - "0.0317054000, 0.0391918000, 0.0579810000, 0.1070638000, 0.2380931000, 0.5786056000, 1.4997534000", \ - "0.0315469000, 0.0392591000, 0.0580558000, 0.1070853000, 0.2381201000, 0.5777495000, 1.4940029000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.007482000, -0.002151900, 0.0078052000, 0.0189272000, 0.0153712000, -0.035109300, -0.197771500", \ - "-0.007432600, -0.002107800, 0.0078405000, 0.0189470000, 0.0153691000, -0.035121500, -0.197795200", \ - "-0.007317000, -0.002003500, 0.0079244000, 0.0189979000, 0.0153912000, -0.035123800, -0.197780800", \ - "-0.007336100, -0.002054100, 0.0078078000, 0.0187901000, 0.0150897000, -0.035481500, -0.198202700", \ - "-0.007345400, -0.002085600, 0.0077268000, 0.0186351000, 0.0148563000, -0.035769000, -0.198486600", \ - "-0.007336500, -0.002086900, 0.0077076000, 0.0185861000, 0.0148051000, -0.035849500, -0.198557700", \ - "-0.007234500, -0.001883900, 0.0081188000, 0.0193362000, 0.0155003000, -0.035176200, -0.197853600"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013189470, 0.0034792440, 0.0091778810, 0.0242102800, 0.0638641800, 0.1684670000"); - values("-0.009225100, -0.005973900, 0.0018629000, 0.0185990000, 0.0500386000, 0.1179230000, 0.2880749000", \ - "-0.009172900, -0.005916600, 0.0019072000, 0.0186340000, 0.0500539000, 0.1184700000, 0.2892871000", \ - "-0.009069400, -0.005840800, 0.0019404000, 0.0185877000, 0.0499645000, 0.1179962000, 0.2882603000", \ - "-0.009080300, -0.005879800, 0.0018486000, 0.0184372000, 0.0496914000, 0.1174851000, 0.2885426000", \ - "-0.009099000, -0.005935300, 0.0017237000, 0.0181781000, 0.0493558000, 0.1171075000, 0.2876229000", \ - "-0.009091100, -0.005930900, 0.0017167000, 0.0181928000, 0.0493197000, 0.1173179000, 0.2885095000", \ - "-0.008726600, -0.005187300, 0.0027897000, 0.0187809000, 0.0498355000, 0.1176516000, 0.2874678000"); - } - } - max_capacitance : 0.1684670000; - max_transition : 1.4985610000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4216638000, 0.4294348000, 0.4455547000, 0.4769572000, 0.5393633000, 0.6772323000, 1.0280448000", \ - "0.4262643000, 0.4340069000, 0.4501754000, 0.4815457000, 0.5439517000, 0.6818259000, 1.0327601000", \ - "0.4375361000, 0.4452617000, 0.4614311000, 0.4928223000, 0.5552391000, 0.6930462000, 1.0429123000", \ - "0.4632048000, 0.4709365000, 0.4870971000, 0.5185177000, 0.5809132000, 0.7186352000, 1.0697463000", \ - "0.5138434000, 0.5216051000, 0.5377274000, 0.5691310000, 0.6315185000, 0.7693608000, 1.1197748000", \ - "0.5888343000, 0.5966078000, 0.6127162000, 0.6441451000, 0.7065354000, 0.8443053000, 1.1947989000", \ - "0.6856402000, 0.6933794000, 0.7095310000, 0.7409123000, 0.8033291000, 0.9412101000, 1.2906728000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.4897143000, 0.4987981000, 0.5179465000, 0.5584150000, 0.6541371000, 0.9001360000, 1.5446179000", \ - "0.4945270000, 0.5036531000, 0.5227414000, 0.5632000000, 0.6588936000, 0.9050041000, 1.5521459000", \ - "0.5053685000, 0.5145098000, 0.5336598000, 0.5741339000, 0.6697946000, 0.9158487000, 1.5617223000", \ - "0.5310989000, 0.5401771000, 0.5593131000, 0.5997793000, 0.6954475000, 0.9415838000, 1.5875328000", \ - "0.5805524000, 0.5896174000, 0.6087859000, 0.6491561000, 0.7448943000, 0.9909055000, 1.6353172000", \ - "0.6571548000, 0.6662849000, 0.6854380000, 0.7259299000, 0.8216371000, 1.0677788000, 1.7118343000", \ - "0.7599630000, 0.7690231000, 0.7881862000, 0.8286715000, 0.9243835000, 1.1706947000, 1.8164200000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0300085000, 0.0351689000, 0.0462982000, 0.0721270000, 0.1337979000, 0.2989210000, 0.7610545000", \ - "0.0298848000, 0.0348682000, 0.0465313000, 0.0719702000, 0.1335312000, 0.2982687000, 0.7620719000", \ - "0.0299608000, 0.0348307000, 0.0461275000, 0.0719394000, 0.1337806000, 0.2976689000, 0.7644479000", \ - "0.0299749000, 0.0348137000, 0.0462440000, 0.0719949000, 0.1337972000, 0.2991173000, 0.7644286000", \ - "0.0300197000, 0.0350297000, 0.0462492000, 0.0721163000, 0.1338208000, 0.2996142000, 0.7563276000", \ - "0.0300641000, 0.0351371000, 0.0462930000, 0.0721447000, 0.1336456000, 0.2994193000, 0.7579867000", \ - "0.0300106000, 0.0349575000, 0.0462302000, 0.0721297000, 0.1338403000, 0.2985288000, 0.7578014000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013189500, 0.0034792400, 0.0091778800, 0.0242103000, 0.0638642000, 0.1684670000"); - values("0.0363529000, 0.0428787000, 0.0592066000, 0.1038423000, 0.2314721000, 0.5759710000, 1.4928870000", \ - "0.0364081000, 0.0429100000, 0.0592325000, 0.1038167000, 0.2314387000, 0.5764005000, 1.4985613000", \ - "0.0366120000, 0.0430361000, 0.0592297000, 0.1038475000, 0.2315800000, 0.5777845000, 1.4953759000", \ - "0.0363824000, 0.0428972000, 0.0592656000, 0.1038554000, 0.2315113000, 0.5770800000, 1.4957293000", \ - "0.0363907000, 0.0429102000, 0.0593281000, 0.1038522000, 0.2315730000, 0.5765914000, 1.4952167000", \ - "0.0364348000, 0.0428173000, 0.0591719000, 0.1038442000, 0.2313781000, 0.5762352000, 1.4917899000", \ - "0.0365565000, 0.0429025000, 0.0592391000, 0.1038092000, 0.2312502000, 0.5769752000, 1.4980412000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0017260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032054000, 0.0032038000, 0.0032001000, 0.0032015000, 0.0032049000, 0.0032127000, 0.0032307000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003114400, -0.003125300, -0.003150600, -0.003153300, -0.003159300, -0.003173000, -0.003204700"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2925274000, 0.4811179000, 0.7964662000", \ - "0.1600892000, 0.3486797000, 0.6652487000", \ - "0.0534811000, 0.2432923000, 0.5610821000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1130840000, 0.2406393000, 0.3631165000", \ - "0.0453431000, 0.1716777000, 0.2904928000", \ - "0.0144186000, 0.1383119000, 0.2583477000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.217726600, -0.406317000, -0.715561800", \ - "-0.101157600, -0.289748000, -0.603875600", \ - "-0.007977200, -0.196567700, -0.513136700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.226873700, -0.343247400", \ - "-0.031577500, -0.157912100, -0.274285800", \ - "0.0017884000, -0.122104800, -0.240919900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0029600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0105892000, 0.0105172000, 0.0103514000, 0.0104150000, 0.0105618000, 0.0109002000, 0.0116803000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104104000, 0.0102435000, 0.0098590000, 0.0098777000, 0.0099212000, 0.0100214000, 0.0102525000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0029370000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4603659000, 0.7464173000", \ - "0.1478822000, 0.3303691000, 0.6213034000", \ - "0.0473776000, 0.2286439000, 0.5195781000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3047344000, 0.3944479000, 0.4375794000", \ - "0.1722962000, 0.2620098000, 0.3051413000", \ - "0.0669089000, 0.1566224000, 0.1997539000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.187209000, -0.372137400, -0.661850900", \ - "-0.076743500, -0.261671900, -0.552606100", \ - "0.0091126000, -0.172153600, -0.463087900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.085890600, -0.219549500, -0.318833300", \ - "-0.019370400, -0.148146500, -0.249871700", \ - "0.0139954000, -0.114780600, -0.215285200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("DE") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sedfxbp_2") { - leakage_power () { - value : 0.0131099000; - when : "CLK&!D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0120476000; - when : "CLK&D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0174908000; - when : "CLK&D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0140919000; - when : "CLK&D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0141402000; - when : "!CLK&D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0168314000; - when : "CLK&D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0124980000; - when : "CLK&!D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0146165000; - when : "CLK&!D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0137759000; - when : "CLK&!D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0131351000; - when : "!CLK&!D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0139644000; - when : "CLK&D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0158984000; - when : "CLK&!D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0135197000; - when : "!CLK&!D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0137495000; - when : "CLK&!D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0184639000; - when : "CLK&D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0127128000; - when : "CLK&D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0161133000; - when : "CLK&D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0137346000; - when : "!CLK&D&!DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0133649000; - when : "CLK&!D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0167654000; - when : "CLK&!D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0143867000; - when : "!CLK&!D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0175747000; - when : "CLK&D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0182340000; - when : "!CLK&D&DE&SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0135209000; - when : "CLK&!D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0115569000; - when : "CLK&D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0153258000; - when : "CLK&D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0145826000; - when : "CLK&D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0136495000; - when : "!CLK&D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0127908000; - when : "CLK&D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0152346000; - when : "CLK&!D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0128833000; - when : "CLK&!D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0162822000; - when : "CLK&!D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0136748000; - when : "!CLK&!D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0141172000; - when : "CLK&!D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0149558000; - when : "CLK&D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0123484000; - when : "!CLK&D&!DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0143615000; - when : "CLK&!D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0147922000; - when : "!CLK&!D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0148834000; - when : "!CLK&D&DE&SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0163407000; - when : "CLK&D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0129089000; - when : "CLK&!D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0135461000; - when : "!CLK&!D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0122681000; - when : "!CLK&!D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0131238000; - when : "CLK&D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0124830000; - when : "!CLK&D&!DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0129316000; - when : "!CLK&!D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0133740000; - when : "CLK&!D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0116052000; - when : "!CLK&D&!DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0126791000; - when : "!CLK&!D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0128940000; - when : "!CLK&D&!DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0124409000; - when : "!CLK&!D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0111145000; - when : "!CLK&D&!DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0126953000; - when : "!CLK&!D&DE&!SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0158676000; - when : "!CLK&!D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0149927000; - when : "!CLK&!D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0131063000; - when : "!CLK&!D&DE&!SCE&SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0145412000; - when : "!CLK&D&!DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0139469000; - when : "!CLK&!D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0152076000; - when : "!CLK&D&!DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0158597000; - when : "!CLK&!D&DE&SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0159257000; - when : "!CLK&D&DE&!SCE&!SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0154350000; - when : "!CLK&D&DE&!SCE&SCD&!Q&Q_N"; - } - leakage_power () { - value : 0.0170762000; - when : "!CLK&D&DE&SCE&!SCD&Q&!Q_N"; - } - leakage_power () { - value : 0.0166690000; - when : "!CLK&D&DE&SCE&SCD&!Q&Q_N"; - } - area : 41.289600000; - cell_footprint : "sky130_fd_sc_hd__sedfxbp"; - cell_leakage_power : 0.0142845700; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017640000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016850000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0273254000, 0.0272028000, 0.0269202000, 0.0269450000, 0.0270024000, 0.0271348000, 0.0274400000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226670000, 0.0225571000, 0.0223039000, 0.0222968000, 0.0222806000, 0.0222434000, 0.0221577000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018430000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3235761000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4510034000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0017660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0157075000, 0.0155437000, 0.0151661000, 0.0152721000, 0.0155165000, 0.0160800000, 0.0173788000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092538000, 0.0092348000, 0.0091911000, 0.0092021000, 0.0092279000, 0.0092872000, 0.0094239000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4060527000, 0.5995260000, 0.9368470000", \ - "0.2784974000, 0.4695293000, 0.8117331000", \ - "0.1767721000, 0.3714662000, 0.7124492000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2070781000, 0.3639303000, 0.5511048000", \ - "0.1442201000, 0.3010723000, 0.4833639000", \ - "0.1206198000, 0.2774720000, 0.4622051000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.321486300, -0.512518200, -0.843735700", \ - "-0.213462200, -0.406935600, -0.741815100", \ - "-0.126385400, -0.322300100, -0.660841800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.339178400, -0.514145800", \ - "-0.125571600, -0.278761700, -0.457391300", \ - "-0.101971400, -0.255161500, -0.437453100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0033020000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031760000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112442000, 0.0111068000, 0.0107900000, 0.0108582000, 0.0110154000, 0.0113780000, 0.0122136000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001600000, 2.5085856e-05, -0.000285800, -0.000228500, -9.6142454e-05, 0.0002088000, 0.0009117000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034290000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3926250000, 0.5787741000, 0.9136536000", \ - "0.2833802000, 0.4695293000, 0.8080710000", \ - "0.1914206000, 0.3763490000, 0.7185528000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4438945000, 0.5336081000, 0.5718568000", \ - "0.3151185000, 0.4060527000, 0.4430807000", \ - "0.2133932000, 0.3031068000, 0.3425762000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.244582000, -0.412420600, -0.594712200", \ - "-0.182944700, -0.349562500, -0.529412700", \ - "-0.155682300, -0.323520800, -0.505812500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.337957700, -0.504380200", \ - "-0.140220100, -0.277541000, -0.445184200", \ - "-0.119061200, -0.256382100, -0.425246100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.008245500, -0.003113100, 0.0074282000, 0.0186567000, 0.0043237000, -0.093624400, -0.421212100", \ - "-0.008193200, -0.003063900, 0.0074696000, 0.0186764000, 0.0043047000, -0.093686500, -0.421325300", \ - "-0.008078200, -0.002964300, 0.0075043000, 0.0186351000, 0.0041722000, -0.093889600, -0.421510000", \ - "-0.008089700, -0.003002600, 0.0074336000, 0.0185022000, 0.0039509000, -0.094123900, -0.421839400", \ - "-0.008101500, -0.003049700, 0.0073058000, 0.0182510000, 0.0035572000, -0.094602400, -0.422253400", \ - "-0.008084800, -0.003038000, 0.0072948000, 0.0181971000, 0.0034724000, -0.094636000, -0.422289000", \ - "-0.008014900, -0.002915900, 0.0075318000, 0.0186474000, 0.0041329000, -0.093925300, -0.421521800"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014632040, 0.0042819320, 0.0125306800, 0.0366698700, 0.1073110000, 0.3140358000"); - values("-0.009682800, -0.006675400, 0.0011818000, 0.0199323000, 0.0655312000, 0.1826591000, 0.5144091000", \ - "-0.009630600, -0.006630800, 0.0012280000, 0.0199174000, 0.0655183000, 0.1821286000, 0.5148122000", \ - "-0.009509200, -0.006512200, 0.0013142000, 0.0199799000, 0.0655963000, 0.1819542000, 0.5182220000", \ - "-0.009523400, -0.006559900, 0.0012152000, 0.0197819000, 0.0652818000, 0.1820128000, 0.5134236000", \ - "-0.009527200, -0.006579500, 0.0011400000, 0.0196159000, 0.0650512000, 0.1813513000, 0.5134649000", \ - "-0.009511800, -0.006570700, 0.0011236000, 0.0195720000, 0.0649707000, 0.1817964000, 0.5146610000", \ - "-0.009374500, -0.006269900, 0.0017941000, 0.0209912000, 0.0656179000, 0.1821001000, 0.5146466000"); - } - } - max_capacitance : 0.3140360000; - max_transition : 1.4974950000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3944553000, 0.4046026000, 0.4284416000, 0.4747995000, 0.5602561000, 0.7250379000, 1.0826151000", \ - "0.3991119000, 0.4095536000, 0.4330347000, 0.4794256000, 0.5649142000, 0.7297001000, 1.0873482000", \ - "0.4101889000, 0.4206563000, 0.4441152000, 0.4904539000, 0.5759275000, 0.7407151000, 1.0984462000", \ - "0.4357914000, 0.4462320000, 0.4697936000, 0.5160016000, 0.6014543000, 0.7663048000, 1.1238526000", \ - "0.4853473000, 0.4958208000, 0.5192739000, 0.5655685000, 0.6510159000, 0.8158058000, 1.1735177000", \ - "0.5615463000, 0.5719790000, 0.5954388000, 0.6421284000, 0.7273002000, 0.8921963000, 1.2497473000", \ - "0.6639429000, 0.6743537000, 0.6978806000, 0.7443061000, 0.8296291000, 0.9945677000, 1.3520038000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.3161884000, 0.3237851000, 0.3413469000, 0.3795113000, 0.4691585000, 0.7137827000, 1.3968324000", \ - "0.3207934000, 0.3283763000, 0.3460290000, 0.3841109000, 0.4737343000, 0.7182805000, 1.3992142000", \ - "0.3319800000, 0.3395848000, 0.3571344000, 0.3953049000, 0.4849220000, 0.7294586000, 1.4122733000", \ - "0.3579387000, 0.3655032000, 0.3830097000, 0.4212154000, 0.5108405000, 0.7554286000, 1.4363535000", \ - "0.4084768000, 0.4160876000, 0.4336425000, 0.4718105000, 0.5614265000, 0.8059744000, 1.4882988000", \ - "0.4833270000, 0.4909664000, 0.5084396000, 0.5465065000, 0.6362459000, 0.8808175000, 1.5612881000", \ - "0.5809603000, 0.5886077000, 0.6061665000, 0.6442616000, 0.7340124000, 0.9786558000, 1.6625107000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0572274000, 0.0633079000, 0.0777261000, 0.1076392000, 0.1682094000, 0.3102238000, 0.7139321000", \ - "0.0570337000, 0.0635341000, 0.0787750000, 0.1071211000, 0.1679083000, 0.3108008000, 0.7153711000", \ - "0.0570484000, 0.0636679000, 0.0787055000, 0.1067916000, 0.1681341000, 0.3104447000, 0.7126474000", \ - "0.0572825000, 0.0632521000, 0.0785666000, 0.1066628000, 0.1680954000, 0.3105607000, 0.7122261000", \ - "0.0570467000, 0.0637076000, 0.0786904000, 0.1067224000, 0.1681482000, 0.3106660000, 0.7126650000", \ - "0.0572269000, 0.0634991000, 0.0785926000, 0.1080852000, 0.1680310000, 0.3102416000, 0.7137214000", \ - "0.0571790000, 0.0636407000, 0.0781441000, 0.1088602000, 0.1681949000, 0.3105984000, 0.7158592000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014632000, 0.0042819300, 0.0125307000, 0.0366699000, 0.1073110000, 0.3140360000"); - values("0.0300897000, 0.0360228000, 0.0506814000, 0.0883051000, 0.2008878000, 0.5296530000, 1.4972835000", \ - "0.0301235000, 0.0360330000, 0.0506183000, 0.0883077000, 0.2008469000, 0.5289967000, 1.4972011000", \ - "0.0300263000, 0.0359449000, 0.0503532000, 0.0884626000, 0.2008833000, 0.5297060000, 1.4974948000", \ - "0.0301083000, 0.0360362000, 0.0504356000, 0.0883146000, 0.2007980000, 0.5292135000, 1.4947903000", \ - "0.0300647000, 0.0359628000, 0.0503902000, 0.0884535000, 0.2008937000, 0.5309367000, 1.4961195000", \ - "0.0299518000, 0.0356294000, 0.0505180000, 0.0880763000, 0.2008285000, 0.5288951000, 1.4960010000", \ - "0.0300603000, 0.0358402000, 0.0507522000, 0.0884566000, 0.2010851000, 0.5287479000, 1.4950207000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("-0.007955000, -0.002359900, 0.0092603000, 0.0228283000, 0.0131131000, -0.079819200, -0.392341300", \ - "-0.007903100, -0.002310300, 0.0092936000, 0.0228594000, 0.0131184000, -0.079795900, -0.392326800", \ - "-0.007782900, -0.002204400, 0.0093761000, 0.0228903000, 0.0131543000, -0.079839900, -0.392357800", \ - "-0.007795200, -0.002241200, 0.0092802000, 0.0226951000, 0.0128638000, -0.080181200, -0.392729100", \ - "-0.007801000, -0.002271500, 0.0091981000, 0.0225155000, 0.0125908000, -0.080497500, -0.393068500", \ - "-0.007787800, -0.002267600, 0.0091777000, 0.0224701000, 0.0125057000, -0.080581500, -0.393170700", \ - "-0.007578200, -0.001777300, 0.0102889000, 0.0242578000, 0.0135131000, -0.079824700, -0.392350900"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("-0.009578800, -0.006396700, 0.0020246000, 0.0228319000, 0.0685735000, 0.1814948000, 0.5018358000", \ - "-0.009524800, -0.006345100, 0.0020696000, 0.0228457000, 0.0685540000, 0.1819906000, 0.4993848000", \ - "-0.009411500, -0.006254000, 0.0021040000, 0.0228375000, 0.0684652000, 0.1821068000, 0.5016514000", \ - "-0.009421800, -0.006287000, 0.0020246000, 0.0226720000, 0.0682070000, 0.1811626000, 0.4985805000", \ - "-0.009429200, -0.006321800, 0.0019340000, 0.0224729000, 0.0678880000, 0.1808579000, 0.4993493000", \ - "-0.009418600, -0.006320900, 0.0019089000, 0.0223669000, 0.0677698000, 0.1806493000, 0.4982211000", \ - "-0.009174700, -0.005770300, 0.0028897000, 0.0227774000, 0.0684614000, 0.1811754000, 0.4987959000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5003940000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.4777122000, 0.4845296000, 0.4996175000, 0.5297363000, 0.5883359000, 0.7171236000, 1.0587640000", \ - "0.4821925000, 0.4889750000, 0.5040878000, 0.5341313000, 0.5928106000, 0.7215306000, 1.0629232000", \ - "0.4935442000, 0.5003479000, 0.5154618000, 0.5455546000, 0.6041711000, 0.7329188000, 1.0741190000", \ - "0.5191908000, 0.5259928000, 0.5411016000, 0.5711351000, 0.6298073000, 0.7585668000, 1.1000850000", \ - "0.5699106000, 0.5767180000, 0.5918253000, 0.6219039000, 0.6804988000, 0.8092274000, 1.1505952000", \ - "0.6448923000, 0.6517215000, 0.6668096000, 0.6968532000, 0.7555342000, 0.8843014000, 1.2262660000", \ - "0.7423144000, 0.7491081000, 0.7642328000, 0.7943119000, 0.8528909000, 0.9816684000, 1.3225938000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.6254456000, 0.6337854000, 0.6522972000, 0.6898846000, 0.7760392000, 1.0125986000, 1.6938235000", \ - "0.6301752000, 0.6386257000, 0.6570964000, 0.6946849000, 0.7808717000, 1.0173198000, 1.6965880000", \ - "0.6412659000, 0.6496143000, 0.6681236000, 0.7057147000, 0.7918896000, 1.0284401000, 1.7096682000", \ - "0.6666835000, 0.6751220000, 0.6935842000, 0.7311761000, 0.8173923000, 1.0537720000, 1.7343833000", \ - "0.7167185000, 0.7250791000, 0.7435845000, 0.7811874000, 0.8673730000, 1.1038630000, 1.7840867000", \ - "0.7921537000, 0.8006013000, 0.8190752000, 0.8566809000, 0.9428840000, 1.1793641000, 1.8601253000", \ - "0.8950055000, 0.9033329000, 0.9218622000, 0.9594708000, 1.0456604000, 1.2819372000, 1.9622122000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0302683000, 0.0343170000, 0.0436334000, 0.0646568000, 0.1163174000, 0.2597602000, 0.7069583000", \ - "0.0301640000, 0.0342109000, 0.0437869000, 0.0646907000, 0.1159734000, 0.2597148000, 0.7046786000", \ - "0.0299852000, 0.0342714000, 0.0436573000, 0.0647115000, 0.1160945000, 0.2599032000, 0.7022316000", \ - "0.0300829000, 0.0344056000, 0.0441727000, 0.0646131000, 0.1160338000, 0.2592328000, 0.7103695000", \ - "0.0302141000, 0.0344518000, 0.0438024000, 0.0646509000, 0.1161517000, 0.2600153000, 0.7045602000", \ - "0.0301787000, 0.0344516000, 0.0437390000, 0.0646003000, 0.1161952000, 0.2593448000, 0.7076215000", \ - "0.0300664000, 0.0344095000, 0.0438236000, 0.0646676000, 0.1159816000, 0.2595914000, 0.7064045000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0366168000, 0.0418242000, 0.0545179000, 0.0884004000, 0.1954237000, 0.5256313000, 1.4966786000", \ - "0.0365996000, 0.0420692000, 0.0544896000, 0.0883546000, 0.1953713000, 0.5249803000, 1.4966832000", \ - "0.0366020000, 0.0418239000, 0.0545371000, 0.0883872000, 0.1953525000, 0.5255549000, 1.4960378000", \ - "0.0365506000, 0.0420013000, 0.0544664000, 0.0885121000, 0.1952017000, 0.5249162000, 1.4941347000", \ - "0.0365610000, 0.0418284000, 0.0545742000, 0.0884438000, 0.1954414000, 0.5251437000, 1.5003936000", \ - "0.0365621000, 0.0420594000, 0.0544924000, 0.0883616000, 0.1953603000, 0.5255713000, 1.4987463000", \ - "0.0366164000, 0.0419866000, 0.0547652000, 0.0884904000, 0.1953151000, 0.5247701000, 1.4951331000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0017260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032142000, 0.0032107000, 0.0032025000, 0.0032035000, 0.0032061000, 0.0032121000, 0.0032260000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003111900, -0.003122300, -0.003146200, -0.003149100, -0.003155600, -0.003170500, -0.003204900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017820000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2937480000, 0.4811179000, 0.7964662000", \ - "0.1613099000, 0.3499004000, 0.6664694000", \ - "0.0547018000, 0.2432923000, 0.5623027000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1143047000, 0.2406393000, 0.3643372000", \ - "0.0465638000, 0.1716777000, 0.2904928000", \ - "0.0144186000, 0.1383119000, 0.2583477000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.216505900, -0.403875600, -0.714341200", \ - "-0.099936800, -0.288527400, -0.602654900", \ - "-0.006756500, -0.195347000, -0.511916000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.226873700, -0.343247400", \ - "-0.032798200, -0.156691400, -0.275506500", \ - "0.0017884000, -0.122104800, -0.242140600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0029540000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029720000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0105900000, 0.0105176000, 0.0103508000, 0.0104153000, 0.0105642000, 0.0109073000, 0.0116982000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102589000, 0.0101386000, 0.0098612000, 0.0098793000, 0.0099212000, 0.0100180000, 0.0102409000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0029370000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2778789000, 0.4603659000, 0.7464173000", \ - "0.1491029000, 0.3315899000, 0.6225241000", \ - "0.0473776000, 0.2298646000, 0.5207988000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3059551000, 0.3956686000, 0.4375794000", \ - "0.1735169000, 0.2620098000, 0.3063620000", \ - "0.0681296000, 0.1578431000, 0.1997539000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.369696000, -0.658188800", \ - "-0.075522800, -0.259230500, -0.551385400", \ - "0.0103333000, -0.172153600, -0.460646500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.087111300, -0.219549500, -0.318833300", \ - "-0.020591100, -0.148146500, -0.248651000", \ - "0.0127747000, -0.114780600, -0.215285200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("DE") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("Q_N") { - direction : "output"; - function : "IQ_N"; - signal_type : "test_scan_out_inverted"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sedfxtp_1") { - leakage_power () { - value : 0.0075659000; - when : "CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0065036000; - when : "CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0119468000; - when : "CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0085479000; - when : "CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0088524000; - when : "!CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0164637000; - when : "CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0121302000; - when : "CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0142488000; - when : "CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0134082000; - when : "CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0126372000; - when : "!CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0135967000; - when : "CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0155307000; - when : "CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0130218000; - when : "!CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0133818000; - when : "CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0180961000; - when : "CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0123451000; - when : "CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0157456000; - when : "CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0132367000; - when : "!CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0129972000; - when : "CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0163976000; - when : "CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0138888000; - when : "!CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0172069000; - when : "CLK&D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0177361000; - when : "!CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0079769000; - when : "CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0060129000; - when : "CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0097818000; - when : "CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0090386000; - when : "CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0083617000; - when : "!CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0072468000; - when : "CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0096906000; - when : "CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0073393000; - when : "CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0107382000; - when : "CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0083871000; - when : "!CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0085732000; - when : "CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0094118000; - when : "CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0070607000; - when : "!CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0088175000; - when : "CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0095044000; - when : "!CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0095957000; - when : "!CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0159730000; - when : "CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0125412000; - when : "CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0130481000; - when : "!CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0117702000; - when : "!CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0127561000; - when : "CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0119851000; - when : "!CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0076438000; - when : "!CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0078300000; - when : "CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0063174000; - when : "!CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0121812000; - when : "!CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0123961000; - when : "!CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0071531000; - when : "!CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0058267000; - when : "!CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0074489000; - when : "!CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0106211000; - when : "!CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0144733000; - when : "!CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0078598000; - when : "!CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0092947000; - when : "!CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0087005000; - when : "!CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0146882000; - when : "!CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0153403000; - when : "!CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0154063000; - when : "!CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0149156000; - when : "!CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0118297000; - when : "!CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0161496000; - when : "!CLK&D&DE&SCE&SCD&!Q"; - } - area : 36.284800000; - cell_footprint : "sky130_fd_sc_hd__sedfxtp"; - cell_leakage_power : 0.0113620800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017670000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016810000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0273759000, 0.0272568000, 0.0269822000, 0.0270061000, 0.0270610000, 0.0271879000, 0.0274803000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226249000, 0.0225167000, 0.0222673000, 0.0222621000, 0.0222502000, 0.0222228000, 0.0221598000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018530000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3246746000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3828957000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0017660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0156823000, 0.0155161000, 0.0151332000, 0.0152410000, 0.0154893000, 0.0160621000, 0.0173823000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092523000, 0.0092325000, 0.0091870000, 0.0091983000, 0.0092244000, 0.0092848000, 0.0094239000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4060527000, 0.5995260000, 0.9368470000", \ - "0.2784974000, 0.4707500000, 0.8117331000", \ - "0.1767721000, 0.3714662000, 0.7124492000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2070781000, 0.3627096000, 0.5498841000", \ - "0.1442201000, 0.3010723000, 0.4833639000", \ - "0.1218405000, 0.2774720000, 0.4622051000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.322707000, -0.512518200, -0.846177100", \ - "-0.214682900, -0.408156200, -0.744256500", \ - "-0.127606100, -0.323520800, -0.662062500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.337957700, -0.514145800", \ - "-0.125571600, -0.278761700, -0.456170600", \ - "-0.101971400, -0.255161500, -0.438673800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0032910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0112380000, 0.0111035000, 0.0107934000, 0.0108588000, 0.0110094000, 0.0113568000, 0.0121574000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001654000, 2.4954594e-05, -0.000298800, -0.000242900, -0.000114100, 0.0001830000, 0.0008677000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034080000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3926250000, 0.5787741000, 0.9136536000", \ - "0.2833802000, 0.4683086000, 0.8068502000", \ - "0.1901999000, 0.3775697000, 0.7185528000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4438945000, 0.5336081000, 0.5718568000", \ - "0.3163392000, 0.4060527000, 0.4443014000", \ - "0.2146139000, 0.3043275000, 0.3425762000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.244582000, -0.412420600, -0.594712200", \ - "-0.182944700, -0.350783200, -0.529412700", \ - "-0.156903000, -0.323520800, -0.505812500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.337957700, -0.504380200", \ - "-0.140220100, -0.277541000, -0.445184200", \ - "-0.119061200, -0.256382100, -0.425246100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("0.0177487000, 0.0164727000, 0.0132175000, 0.0061286000, -0.016312500, -0.080739800, -0.253037900", \ - "0.0178301000, 0.0165573000, 0.0132993000, 0.0062138000, -0.016232400, -0.080663500, -0.252957300", \ - "0.0177198000, 0.0164488000, 0.0131921000, 0.0061314000, -0.016338000, -0.080776900, -0.253054400", \ - "0.0173995000, 0.0161388000, 0.0128831000, 0.0057963000, -0.016651700, -0.081095000, -0.253373700", \ - "0.0169286000, 0.0156630000, 0.0124109000, 0.0053171000, -0.017132500, -0.081571100, -0.253858700", \ - "0.0168856000, 0.0156173000, 0.0123498000, 0.0052609000, -0.017210600, -0.081625800, -0.253903200", \ - "0.0224879000, 0.0211264000, 0.0176107000, 0.0084085000, -0.016016100, -0.080940100, -0.253211100"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013225070, 0.0034980500, 0.0092523930, 0.0244727100, 0.0647306700, 0.1712136000"); - values("0.0249766000, 0.0264617000, 0.0304846000, 0.0404088000, 0.0651781000, 0.1293204000, 0.3007520000", \ - "0.0250104000, 0.0265043000, 0.0305336000, 0.0404475000, 0.0650669000, 0.1293000000, 0.3019257000", \ - "0.0249414000, 0.0264404000, 0.0304677000, 0.0403897000, 0.0649419000, 0.1301078000, 0.3007076000", \ - "0.0247224000, 0.0261517000, 0.0301741000, 0.0401188000, 0.0646595000, 0.1298316000, 0.3016988000", \ - "0.0243509000, 0.0257809000, 0.0297816000, 0.0397053000, 0.0644837000, 0.1286227000, 0.2997006000", \ - "0.0243255000, 0.0257516000, 0.0297600000, 0.0397297000, 0.0642762000, 0.1294076000, 0.3012666000", \ - "0.0264026000, 0.0278192000, 0.0313900000, 0.0408201000, 0.0650701000, 0.1297988000, 0.3001015000"); - } - } - max_capacitance : 0.1712140000; - max_transition : 1.5031800000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.3141903000, 0.3261226000, 0.3505062000, 0.3968251000, 0.4816206000, 0.6368128000, 0.9889732000", \ - "0.3190684000, 0.3309089000, 0.3554165000, 0.4016640000, 0.4864639000, 0.6417014000, 0.9940412000", \ - "0.3300632000, 0.3419546000, 0.3663580000, 0.4126630000, 0.4974447000, 0.6526775000, 1.0049030000", \ - "0.3555980000, 0.3675253000, 0.3919743000, 0.4382289000, 0.5230093000, 0.6782461000, 1.0305576000", \ - "0.4051813000, 0.4170357000, 0.4414467000, 0.4876863000, 0.5724550000, 0.7276993000, 1.0799938000", \ - "0.4814353000, 0.4935694000, 0.5181207000, 0.5642989000, 0.6491419000, 0.8043900000, 1.1567234000", \ - "0.5841157000, 0.5959861000, 0.6205955000, 0.6668384000, 0.7516993000, 0.9070517000, 1.2590715000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.2922530000, 0.3010718000, 0.3202681000, 0.3626584000, 0.4624516000, 0.7083837000, 1.3557659000", \ - "0.2968710000, 0.3057224000, 0.3249231000, 0.3673006000, 0.4670813000, 0.7129778000, 1.3635171000", \ - "0.3080155000, 0.3168509000, 0.3360718000, 0.3784434000, 0.4782203000, 0.7240571000, 1.3714527000", \ - "0.3343213000, 0.3429178000, 0.3622312000, 0.4045965000, 0.5043003000, 0.7505386000, 1.3999016000", \ - "0.3851199000, 0.3937906000, 0.4130332000, 0.4554077000, 0.5551996000, 0.8011102000, 1.4515895000", \ - "0.4599293000, 0.4685214000, 0.4878507000, 0.5302244000, 0.6299454000, 0.8762018000, 1.5222660000", \ - "0.5562150000, 0.5649396000, 0.5842976000, 0.6267082000, 0.7265213000, 0.9724751000, 1.6214901000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0490752000, 0.0567226000, 0.0738533000, 0.1059570000, 0.1711446000, 0.3223438000, 0.7543087000", \ - "0.0485970000, 0.0564847000, 0.0733431000, 0.1061279000, 0.1713383000, 0.3212203000, 0.7625373000", \ - "0.0484711000, 0.0566660000, 0.0737475000, 0.1060047000, 0.1713662000, 0.3215402000, 0.7619382000", \ - "0.0484530000, 0.0565658000, 0.0734636000, 0.1060992000, 0.1715411000, 0.3212600000, 0.7623776000", \ - "0.0484818000, 0.0566207000, 0.0735515000, 0.1060938000, 0.1716820000, 0.3211538000, 0.7577014000", \ - "0.0486845000, 0.0565592000, 0.0728965000, 0.1064298000, 0.1715218000, 0.3217539000, 0.7625215000", \ - "0.0497800000, 0.0571886000, 0.0740058000, 0.1067105000, 0.1718476000, 0.3217293000, 0.7583801000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013225100, 0.0034980500, 0.0092523900, 0.0244727000, 0.0647307000, 0.1712140000"); - values("0.0309160000, 0.0383929000, 0.0572913000, 0.1062929000, 0.2333330000, 0.5746260000, 1.5002184000", \ - "0.0308630000, 0.0384237000, 0.0573756000, 0.1063651000, 0.2334327000, 0.5747666000, 1.5031797000", \ - "0.0309093000, 0.0384124000, 0.0574032000, 0.1063972000, 0.2333961000, 0.5748398000, 1.4957654000", \ - "0.0305590000, 0.0383401000, 0.0571688000, 0.1063674000, 0.2332430000, 0.5751677000, 1.4986049000", \ - "0.0306844000, 0.0383275000, 0.0572597000, 0.1063440000, 0.2332713000, 0.5747459000, 1.5020182000", \ - "0.0305667000, 0.0384063000, 0.0572033000, 0.1064461000, 0.2333570000, 0.5760177000, 1.5018754000", \ - "0.0308461000, 0.0384354000, 0.0574328000, 0.1068307000, 0.2333704000, 0.5740520000, 1.4992911000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0017270000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016710000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031986000, 0.0031990000, 0.0032001000, 0.0032013000, 0.0032041000, 0.0032108000, 0.0032262000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.003115600, -0.003127300, -0.003154100, -0.003153800, -0.003153300, -0.003152000, -0.003148900"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2937480000, 0.4823385000, 0.7964662000", \ - "0.1613099000, 0.3499004000, 0.6664694000", \ - "0.0547018000, 0.2432923000, 0.5623027000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1130840000, 0.2406393000, 0.3618958000", \ - "0.0465638000, 0.1716777000, 0.2904928000", \ - "0.0144186000, 0.1383119000, 0.2583477000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.216505900, -0.405096400, -0.716782500", \ - "-0.101157600, -0.288527400, -0.603875600", \ - "-0.007977200, -0.195347000, -0.513136700"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.226873700, -0.343247400", \ - "-0.032798200, -0.156691400, -0.274285800", \ - "0.0017884000, -0.122104800, -0.240919900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0029610000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0105908000, 0.0105188000, 0.0103527000, 0.0104176000, 0.0105673000, 0.0109126000, 0.0117086000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0102665000, 0.0101421000, 0.0098554000, 0.0098725000, 0.0099119000, 0.0100029000, 0.0102126000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0029380000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2790996000, 0.4615866000, 0.7476380000", \ - "0.1491029000, 0.3315899000, 0.6225241000", \ - "0.0485983000, 0.2298646000, 0.5207988000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3059551000, 0.3956686000, 0.4375794000", \ - "0.1735169000, 0.2620098000, 0.3063620000", \ - "0.0681296000, 0.1578431000, 0.1997539000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.187209000, -0.372137400, -0.660630200", \ - "-0.076743500, -0.260451200, -0.552606100", \ - "0.0091126000, -0.173374400, -0.463087900"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.087111300, -0.219549500, -0.318833300", \ - "-0.019370400, -0.148146500, -0.249871700", \ - "0.0127747000, -0.114780600, -0.215285200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("DE") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sedfxtp_2") { - leakage_power () { - value : 0.0080069000; - when : "CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0069446000; - when : "CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0123878000; - when : "CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0089889000; - when : "CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0092934000; - when : "!CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0159507000; - when : "CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0116173000; - when : "CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0137358000; - when : "CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0128952000; - when : "CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0121242000; - when : "!CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0130837000; - when : "CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0150177000; - when : "CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0125088000; - when : "!CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0128689000; - when : "CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0175832000; - when : "CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0118322000; - when : "CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0152326000; - when : "CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0127237000; - when : "!CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0124843000; - when : "CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0158847000; - when : "CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0133758000; - when : "!CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0166940000; - when : "CLK&D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0172232000; - when : "!CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0084179000; - when : "CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0064539000; - when : "CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0102228000; - when : "CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0094796000; - when : "CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0088027000; - when : "!CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0076878000; - when : "CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0101316000; - when : "CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0077803000; - when : "CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0111792000; - when : "CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0088281000; - when : "!CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0090142000; - when : "CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0098528000; - when : "CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0075017000; - when : "!CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0092585000; - when : "CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0099454000; - when : "!CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0100367000; - when : "!CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0154600000; - when : "CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0120282000; - when : "CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0125352000; - when : "!CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0112573000; - when : "!CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0122431000; - when : "CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0114722000; - when : "!CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0080848000; - when : "!CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0082710000; - when : "CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0067584000; - when : "!CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0116682000; - when : "!CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0118831000; - when : "!CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0075941000; - when : "!CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0062677000; - when : "!CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0078899000; - when : "!CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0110621000; - when : "!CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0139603000; - when : "!CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0083008000; - when : "!CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0097357000; - when : "!CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0091414000; - when : "!CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0141752000; - when : "!CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0148273000; - when : "!CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0148934000; - when : "!CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0144027000; - when : "!CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0122707000; - when : "!CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0156366000; - when : "!CLK&D&DE&SCE&SCD&!Q"; - } - area : 37.536000000; - cell_footprint : "sky130_fd_sc_hd__sedfxtp"; - cell_leakage_power : 0.0113261000; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017680000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016830000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0272423000, 0.0271187000, 0.0268337000, 0.0268639000, 0.0269332000, 0.0270932000, 0.0274619000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0226624000, 0.0225508000, 0.0222936000, 0.0222868000, 0.0222712000, 0.0222354000, 0.0221529000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018530000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3235761000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4279346000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0017650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016740000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155800000, 0.0154159000, 0.0150375000, 0.0151363000, 0.0153641000, 0.0158893000, 0.0171000000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092483000, 0.0092299000, 0.0091876000, 0.0091994000, 0.0092265000, 0.0092892000, 0.0094338000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018570000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4072734000, 0.5995260000, 0.9368470000", \ - "0.2784974000, 0.4707500000, 0.8117331000", \ - "0.1779928000, 0.3714662000, 0.7136699000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2070781000, 0.3639303000, 0.5511048000", \ - "0.1442201000, 0.3010723000, 0.4845846000", \ - "0.1218405000, 0.2774720000, 0.4622051000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.320265600, -0.511297500, -0.843735700", \ - "-0.213462200, -0.406935600, -0.741815100", \ - "-0.126385400, -0.322300100, -0.660841800"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.339178400, -0.514145800", \ - "-0.125571600, -0.278761700, -0.456170600", \ - "-0.101971400, -0.255161500, -0.437453100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0032920000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031770000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0111004000, 0.0109570000, 0.0106264000, 0.0106996000, 0.0108682000, 0.0112572000, 0.0121537000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001561000, 1.8930252e-05, -0.000297200, -0.000240800, -0.000110900, 0.0001887000, 0.0008795000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034080000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3926250000, 0.5787741000, 0.9136536000", \ - "0.2833802000, 0.4683086000, 0.8068502000", \ - "0.1914206000, 0.3763490000, 0.7185528000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4438945000, 0.5348288000, 0.5718568000", \ - "0.3163392000, 0.4060527000, 0.4443014000", \ - "0.2146139000, 0.3043275000, 0.3425762000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.244582000, -0.412420600, -0.594712200", \ - "-0.182944700, -0.350783200, -0.530633400", \ - "-0.156903000, -0.323520800, -0.505812500"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.337957700, -0.504380200", \ - "-0.140220100, -0.277541000, -0.445184200", \ - "-0.119061200, -0.256382100, -0.425246100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0181159000, 0.0164665000, 0.0122714000, 0.0027590000, -0.032546100, -0.145560700, -0.482052100", \ - "0.0182034000, 0.0165472000, 0.0123448000, 0.0028421000, -0.032435900, -0.145484100, -0.481971000", \ - "0.0181170000, 0.0164566000, 0.0122651000, 0.0027523000, -0.032560900, -0.145578700, -0.482064300", \ - "0.0178052000, 0.0161497000, 0.0119380000, 0.0024637000, -0.032899800, -0.145885100, -0.482391000", \ - "0.0173106000, 0.0156562000, 0.0114426000, 0.0019525000, -0.033397100, -0.146398800, -0.482868000", \ - "0.0172763000, 0.0156913000, 0.0114267000, 0.0019769000, -0.033411900, -0.146377600, -0.482843600", \ - "0.0275254000, 0.0257176000, 0.0207833000, 0.0072351000, -0.031844300, -0.145800300, -0.482257200"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014646220, 0.0042902380, 0.0125671600, 0.0368122800, 0.1078322000, 0.3158668000"); - values("0.0288778000, 0.0306211000, 0.0357419000, 0.0504539000, 0.0902525000, 0.2037723000, 0.5405414000", \ - "0.0288626000, 0.0306614000, 0.0358741000, 0.0505599000, 0.0900258000, 0.2035322000, 0.5377041000", \ - "0.0288421000, 0.0306330000, 0.0358195000, 0.0505044000, 0.0898970000, 0.2038835000, 0.5399244000", \ - "0.0285377000, 0.0302955000, 0.0355775000, 0.0501530000, 0.0896873000, 0.2038538000, 0.5398484000", \ - "0.0281659000, 0.0299295000, 0.0351902000, 0.0498222000, 0.0894932000, 0.2032518000, 0.5396570000", \ - "0.0281955000, 0.0299869000, 0.0351872000, 0.0498327000, 0.0893532000, 0.2033079000, 0.5393284000", \ - "0.0315990000, 0.0332094000, 0.0377841000, 0.0514116000, 0.0902414000, 0.2045700000, 0.5408703000"); - } - } - max_capacitance : 0.3158670000; - max_transition : 1.5034920000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.3787660000, 0.3891041000, 0.4123547000, 0.4586125000, 0.5448387000, 0.7034425000, 1.0536836000", \ - "0.3836376000, 0.3939748000, 0.4172295000, 0.4634831000, 0.5497104000, 0.7083067000, 1.0588024000", \ - "0.3946453000, 0.4049815000, 0.4282316000, 0.4744854000, 0.5607081000, 0.7192820000, 1.0697644000", \ - "0.4201280000, 0.4305974000, 0.4536896000, 0.4999076000, 0.5861464000, 0.7447226000, 1.0950598000", \ - "0.4698539000, 0.4803246000, 0.5034138000, 0.5496187000, 0.6358348000, 0.7944106000, 1.1447070000", \ - "0.5457195000, 0.5559605000, 0.5792063000, 0.6255488000, 0.7117625000, 0.8704253000, 1.2209102000", \ - "0.6480111000, 0.6584173000, 0.6815503000, 0.7279237000, 0.8140124000, 0.9726183000, 1.3230094000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.3120963000, 0.3195597000, 0.3368307000, 0.3747908000, 0.4647817000, 0.7015905000, 1.3867836000", \ - "0.3168632000, 0.3242334000, 0.3415767000, 0.3794602000, 0.4694330000, 0.7064123000, 1.3894927000", \ - "0.3279640000, 0.3354078000, 0.3527116000, 0.3906031000, 0.4806029000, 0.7174071000, 1.3996477000", \ - "0.3540509000, 0.3615214000, 0.3789636000, 0.4167864000, 0.5068270000, 0.7437146000, 1.4269002000", \ - "0.4049377000, 0.4123827000, 0.4297716000, 0.4676114000, 0.5576619000, 0.7944352000, 1.4763945000", \ - "0.4799282000, 0.4873768000, 0.5046923000, 0.5426196000, 0.6326148000, 0.8694857000, 1.5515419000", \ - "0.5760359000, 0.5835735000, 0.6009162000, 0.6388485000, 0.7288961000, 0.9657501000, 1.6472418000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0559727000, 0.0622310000, 0.0776298000, 0.1065274000, 0.1674714000, 0.3013849000, 0.7050549000", \ - "0.0559746000, 0.0622273000, 0.0776351000, 0.1065304000, 0.1674650000, 0.3008325000, 0.7032045000", \ - "0.0559717000, 0.0622245000, 0.0776312000, 0.1065310000, 0.1674687000, 0.3013934000, 0.7048041000", \ - "0.0559574000, 0.0623459000, 0.0776580000, 0.1065181000, 0.1674105000, 0.3016580000, 0.7049870000", \ - "0.0559556000, 0.0623354000, 0.0776524000, 0.1065368000, 0.1674218000, 0.3015454000, 0.7056100000", \ - "0.0564794000, 0.0623151000, 0.0771393000, 0.1067690000, 0.1672279000, 0.3008976000, 0.7050243000", \ - "0.0564205000, 0.0625014000, 0.0769983000, 0.1069328000, 0.1675584000, 0.3006053000, 0.7047967000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014646200, 0.0042902400, 0.0125672000, 0.0368123000, 0.1078320000, 0.3158670000"); - values("0.0295291000, 0.0351828000, 0.0496994000, 0.0875854000, 0.1976114000, 0.5218031000, 1.4996563000", \ - "0.0292808000, 0.0351900000, 0.0496783000, 0.0874524000, 0.1969408000, 0.5218187000, 1.5024137000", \ - "0.0294118000, 0.0352796000, 0.0496557000, 0.0874532000, 0.1970053000, 0.5220933000, 1.5033338000", \ - "0.0294395000, 0.0352703000, 0.0498377000, 0.0875723000, 0.1974086000, 0.5225449000, 1.4991840000", \ - "0.0294184000, 0.0352746000, 0.0498875000, 0.0874872000, 0.1969530000, 0.5227900000, 1.5027775000", \ - "0.0294463000, 0.0353161000, 0.0496866000, 0.0875249000, 0.1969885000, 0.5215187000, 1.5034922000", \ - "0.0293844000, 0.0353769000, 0.0500212000, 0.0877025000, 0.1974612000, 0.5210274000, 1.5034208000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0017260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016700000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0032073000, 0.0032054000, 0.0032009000, 0.0032023000, 0.0032052000, 0.0032123000, 0.0032287000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002989200, -0.002994100, -0.003005400, -0.003014200, -0.003034700, -0.003081500, -0.003189500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2937480000, 0.4823385000, 0.7964662000", \ - "0.1625306000, 0.3511211000, 0.6664694000", \ - "0.0559225000, 0.2445130000, 0.5635234000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1143047000, 0.2406393000, 0.3631165000", \ - "0.0465638000, 0.1716777000, 0.2904928000", \ - "0.0144186000, 0.1383119000, 0.2583477000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.215285200, -0.403875600, -0.714341200", \ - "-0.099936800, -0.288527400, -0.602654900", \ - "-0.006756500, -0.195347000, -0.510695300"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.226873700, -0.343247400", \ - "-0.032798200, -0.156691400, -0.274285800", \ - "0.0017884000, -0.122104800, -0.242140600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0029600000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029820000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0105909000, 0.0105179000, 0.0103497000, 0.0104147000, 0.0105645000, 0.0109099000, 0.0117063000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104253000, 0.0103064000, 0.0100324000, 0.0100448000, 0.0100732000, 0.0101391000, 0.0102909000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0029380000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2790996000, 0.4615866000, 0.7476380000", \ - "0.1491029000, 0.3328105000, 0.6225241000", \ - "0.0485983000, 0.2298646000, 0.5207988000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3059551000, 0.3956686000, 0.4388001000", \ - "0.1747376000, 0.2632305000, 0.3063620000", \ - "0.0681296000, 0.1578431000, 0.2009746000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.184767600, -0.369696000, -0.658188800", \ - "-0.075522800, -0.259230500, -0.551385400", \ - "0.0103333000, -0.172153600, -0.461867200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.085890600, -0.219549500, -0.318833300", \ - "-0.020591100, -0.148146500, -0.249871700", \ - "0.0127747000, -0.114780600, -0.215285200"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("DE") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__sedfxtp_4") { - leakage_power () { - value : 0.0090462000; - when : "CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0079838000; - when : "CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0134271000; - when : "CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0100281000; - when : "CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0103327000; - when : "!CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0162271000; - when : "CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0118936000; - when : "CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0140121000; - when : "CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0131715000; - when : "CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0124006000; - when : "!CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0133601000; - when : "CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0152940000; - when : "CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0127852000; - when : "!CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0131452000; - when : "CLK&!D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0178595000; - when : "CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0121085000; - when : "CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0155089000; - when : "CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0130000000; - when : "!CLK&D&!DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0127606000; - when : "CLK&!D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0161610000; - when : "CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0136521000; - when : "!CLK&!D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0169703000; - when : "CLK&D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0174995000; - when : "!CLK&D&DE&SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0094572000; - when : "CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0074931000; - when : "CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0112621000; - when : "CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0105188000; - when : "CLK&D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0098420000; - when : "!CLK&D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0087271000; - when : "CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0111709000; - when : "CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0088195000; - when : "CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0122185000; - when : "CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0098673000; - when : "!CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0100535000; - when : "CLK&!D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0108921000; - when : "CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0085409000; - when : "!CLK&D&!DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0102978000; - when : "CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0109847000; - when : "!CLK&!D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0110759000; - when : "!CLK&D&DE&SCE&SCD&Q"; - } - leakage_power () { - value : 0.0157363000; - when : "CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0123046000; - when : "CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0128115000; - when : "!CLK&!D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0115336000; - when : "!CLK&!D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0125195000; - when : "CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0117485000; - when : "!CLK&D&!DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0091241000; - when : "!CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0093102000; - when : "CLK&!D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0077977000; - when : "!CLK&D&!DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0119445000; - when : "!CLK&!D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0121594000; - when : "!CLK&D&!DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0086334000; - when : "!CLK&!D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0073070000; - when : "!CLK&D&!DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0089291000; - when : "!CLK&!D&DE&!SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0121014000; - when : "!CLK&!D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0142367000; - when : "!CLK&!D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0093401000; - when : "!CLK&!D&DE&!SCE&SCD&Q"; - } - leakage_power () { - value : 0.0107750000; - when : "!CLK&D&!DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0101807000; - when : "!CLK&!D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0144516000; - when : "!CLK&D&!DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0151036000; - when : "!CLK&!D&DE&SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0151697000; - when : "!CLK&D&DE&!SCE&!SCD&!Q"; - } - leakage_power () { - value : 0.0146790000; - when : "!CLK&D&DE&!SCE&SCD&!Q"; - } - leakage_power () { - value : 0.0133100000; - when : "!CLK&D&DE&SCE&!SCD&Q"; - } - leakage_power () { - value : 0.0159129000; - when : "!CLK&D&DE&SCE&SCD&!Q"; - } - area : 40.038400000; - cell_footprint : "sky130_fd_sc_hd__sedfxtp"; - cell_leakage_power : 0.0119838900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"; - } - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("CLK") { - capacitance : 0.0017740000; - clock : "true"; - direction : "input"; - fall_capacitance : 0.0016950000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0272113000, 0.0271269000, 0.0269323000, 0.0269586000, 0.0270193000, 0.0271593000, 0.0274821000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0227211000, 0.0226172000, 0.0223778000, 0.0223692000, 0.0223493000, 0.0223037000, 0.0221985000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018530000; - timing () { - fall_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3147880000, 0.8333333000, 2.5000000000"); - } - related_output_pin : "Q"; - related_pin : "CLK"; - rise_constraint ("constraint_3_0_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.5575589000, 0.8333333000, 2.5000000000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "min_pulse_width"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("D") { - capacitance : 0.0017660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016750000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0155836000, 0.0154486000, 0.0151372000, 0.0152022000, 0.0153521000, 0.0156976000, 0.0164941000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0092531000, 0.0092331000, 0.0091870000, 0.0091984000, 0.0092245000, 0.0092849000, 0.0094242000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0018580000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3987285000, 0.5922018000, 0.9307435000", \ - "0.2723939000, 0.4658672000, 0.8068502000", \ - "0.1718893000, 0.3665833000, 0.7087871000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2070781000, 0.3639303000, 0.5511048000", \ - "0.1442201000, 0.3010723000, 0.4845846000", \ - "0.1218405000, 0.2774720000, 0.4622051000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.320265600, -0.512518200, -0.843735700", \ - "-0.213462200, -0.406935600, -0.741815100", \ - "-0.126385400, -0.321079400, -0.663283200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.185988300, -0.340399100, -0.515366500", \ - "-0.126792300, -0.279982400, -0.457391300", \ - "-0.103192100, -0.256382100, -0.438673800"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("DE") { - capacitance : 0.0032910000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0031730000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0110942000, 0.0109987000, 0.0107787000, 0.0108463000, 0.0110024000, 0.0113621000, 0.0121912000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0001584000, 1.9889915e-05, -0.000299300, -0.000242900, -0.000112900, 0.0001870000, 0.0008783000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0034080000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.3938457000, 0.5787741000, 0.9136536000", \ - "0.2833802000, 0.4695293000, 0.8068502000", \ - "0.1914206000, 0.3775697000, 0.7197735000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.4365703000, 0.5275046000, 0.5645326000", \ - "0.3102357000, 0.3999492000, 0.4381979000", \ - "0.2097311000, 0.2994447000, 0.3376934000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.245802700, -0.413641300, -0.595932900", \ - "-0.184165400, -0.350783200, -0.530633400", \ - "-0.156903000, -0.324741500, -0.507033200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.199416000, -0.337957700, -0.504380200", \ - "-0.140220100, -0.277541000, -0.445184200", \ - "-0.119061200, -0.256382100, -0.425246100"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("Q") { - direction : "output"; - function : "IQ"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0278681000, 0.0257011000, 0.0191534000, 0.0031103000, -0.051580900, -0.241379100, -0.865710300", \ - "0.0278098000, 0.0256576000, 0.0192685000, 0.0031632000, -0.051496600, -0.241316000, -0.865672800", \ - "0.0277633000, 0.0255259000, 0.0190482000, 0.0030725000, -0.051651700, -0.241419400, -0.865770200", \ - "0.0274458000, 0.0251762000, 0.0188621000, 0.0027476000, -0.051966500, -0.241730700, -0.866088500", \ - "0.0269354000, 0.0247264000, 0.0184002000, 0.0022636000, -0.052519300, -0.242230400, -0.866562800", \ - "0.0269430000, 0.0246926000, 0.0181896000, 0.0021564000, -0.052535900, -0.242349600, -0.866676200", \ - "0.0373653000, 0.0349881000, 0.0279270000, 0.0076094000, -0.051715800, -0.241580300, -0.865899400"); - } - related_pin : "CLK"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016114370, 0.0051934600, 0.0167378700, 0.0539440500, 0.1738549000, 0.5603125000"); - values("0.0398563000, 0.0417550000, 0.0478729000, 0.0676667000, 0.1289319000, 0.3222507000, 0.9412259000", \ - "0.0398748000, 0.0417925000, 0.0479294000, 0.0677125000, 0.1289021000, 0.3210130000, 0.9465956000", \ - "0.0397984000, 0.0417299000, 0.0479052000, 0.0676307000, 0.1286853000, 0.3212313000, 0.9452955000", \ - "0.0394675000, 0.0414122000, 0.0475967000, 0.0673684000, 0.1285557000, 0.3210748000, 0.9451970000", \ - "0.0391727000, 0.0410741000, 0.0471581000, 0.0669751000, 0.1282356000, 0.3203795000, 0.9454113000", \ - "0.0391085000, 0.0410161000, 0.0471104000, 0.0669021000, 0.1279818000, 0.3211519000, 0.9411003000", \ - "0.0430958000, 0.0448836000, 0.0507434000, 0.0695253000, 0.1289767000, 0.3222855000, 0.9404089000"); - } - } - max_capacitance : 0.5603130000; - max_transition : 1.5052910000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.5266594000, 0.5347355000, 0.5555209000, 0.6031744000, 0.6979493000, 0.8761400000, 1.2505328000", \ - "0.5313546000, 0.5391949000, 0.5602399000, 0.6080338000, 0.7027779000, 0.8807992000, 1.2553383000", \ - "0.5424849000, 0.5503188000, 0.5709762000, 0.6190674000, 0.7138932000, 0.8920617000, 1.2663373000", \ - "0.5680032000, 0.5758323000, 0.5968859000, 0.6446227000, 0.7394015000, 0.9175274000, 1.2918056000", \ - "0.6177323000, 0.6255584000, 0.6466251000, 0.6943180000, 0.7890765000, 0.9672146000, 1.3416758000", \ - "0.6937307000, 0.7015714000, 0.7221459000, 0.7701026000, 0.8649475000, 1.0431428000, 1.4173074000", \ - "0.7951123000, 0.8029244000, 0.8241564000, 0.8716916000, 0.9664177000, 1.1447402000, 1.5190657000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.3622970000, 0.3684018000, 0.3844210000, 0.4216083000, 0.5082293000, 0.7394801000, 1.4556700000", \ - "0.3669743000, 0.3732167000, 0.3891247000, 0.4262632000, 0.5128552000, 0.7442282000, 1.4598465000", \ - "0.3781110000, 0.3842260000, 0.4002861000, 0.4374083000, 0.5239895000, 0.7552509000, 1.4723516000", \ - "0.4043555000, 0.4104401000, 0.4263933000, 0.4636534000, 0.5501973000, 0.7814236000, 1.5003997000", \ - "0.4551926000, 0.4613745000, 0.4773303000, 0.5145162000, 0.6011452000, 0.8322384000, 1.5514171000", \ - "0.5300297000, 0.5361634000, 0.5519775000, 0.5892106000, 0.6759319000, 0.9072564000, 1.6242743000", \ - "0.6270872000, 0.6332398000, 0.6492684000, 0.6864981000, 0.7731377000, 1.0044601000, 1.7237738000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0844107000, 0.0887656000, 0.1013312000, 0.1299563000, 0.1907121000, 0.3212665000, 0.7049382000", \ - "0.0844694000, 0.0883673000, 0.1017593000, 0.1307771000, 0.1909614000, 0.3210378000, 0.7069140000", \ - "0.0843524000, 0.0886380000, 0.1014729000, 0.1305649000, 0.1909384000, 0.3195866000, 0.7062083000", \ - "0.0844484000, 0.0884379000, 0.1016042000, 0.1307210000, 0.1909837000, 0.3193787000, 0.7051094000", \ - "0.0842637000, 0.0884852000, 0.1016187000, 0.1306722000, 0.1909034000, 0.3198217000, 0.7027860000", \ - "0.0846635000, 0.0890840000, 0.1011870000, 0.1304558000, 0.1907332000, 0.3206368000, 0.7061219000", \ - "0.0845447000, 0.0889233000, 0.1006112000, 0.1304893000, 0.1908376000, 0.3187750000, 0.7062828000"); - } - related_pin : "CLK"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016114400, 0.0051934600, 0.0167379000, 0.0539441000, 0.1738550000, 0.5603130000"); - values("0.0383753000, 0.0425358000, 0.0553690000, 0.0866519000, 0.1808420000, 0.4827424000, 1.4958392000", \ - "0.0384723000, 0.0431860000, 0.0553778000, 0.0866238000, 0.1808482000, 0.4822591000, 1.5021722000", \ - "0.0384509000, 0.0428837000, 0.0553829000, 0.0866954000, 0.1805751000, 0.4829150000, 1.5019878000", \ - "0.0385369000, 0.0430306000, 0.0553845000, 0.0867069000, 0.1811702000, 0.4827991000, 1.5024002000", \ - "0.0382314000, 0.0427924000, 0.0548286000, 0.0866238000, 0.1808377000, 0.4822362000, 1.5025775000", \ - "0.0386229000, 0.0427151000, 0.0549786000, 0.0866437000, 0.1806599000, 0.4833327000, 1.5052912000", \ - "0.0390046000, 0.0432747000, 0.0553487000, 0.0865986000, 0.1808874000, 0.4825593000, 1.5006837000"); - } - timing_sense : "non_unate"; - timing_type : "rising_edge"; - } - } - pin ("SCD") { - capacitance : 0.0017260000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0016690000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0031209000, 0.0031447000, 0.0031995000, 0.0032005000, 0.0032026000, 0.0032078000, 0.0032196000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("-0.002995400, -0.003044300, -0.003157100, -0.003159300, -0.003164200, -0.003175500, -0.003201500"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0017830000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2852031000, 0.4737936000, 0.7891419000", \ - "0.1552064000, 0.3425762000, 0.6615866000", \ - "0.0498190000, 0.2384095000, 0.5574199000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.1143047000, 0.2406393000, 0.3643372000", \ - "0.0465638000, 0.1716777000, 0.2904928000", \ - "0.0144186000, 0.1395326000, 0.2583477000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.215285200, -0.403875600, -0.714341200", \ - "-0.099936800, -0.288527400, -0.602654900", \ - "-0.006756500, -0.195347000, -0.511916000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.101759800, -0.226873700, -0.344468100", \ - "-0.032798200, -0.157912100, -0.275506500", \ - "0.0017884000, -0.123325500, -0.242140600"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - pin ("SCE") { - capacitance : 0.0029420000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0029470000; - internal_power () { - fall_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0105869000, 0.0105135000, 0.0103444000, 0.0104094000, 0.0105594000, 0.0109052000, 0.0117023000"); - } - rise_power ("power_inputs_1") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - values("0.0104076000, 0.0102392000, 0.0098510000, 0.0098747000, 0.0099293000, 0.0100552000, 0.0103455000"); - } - } - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0029380000; - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2717754000, 0.4542624000, 0.7415345000", \ - "0.1429994000, 0.3254863000, 0.6164206000", \ - "0.0437155000, 0.2249818000, 0.5171367000"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("0.2974102000, 0.3871237000, 0.4302552000", \ - "0.1674134000, 0.2571269000, 0.3002585000", \ - "0.0632467000, 0.1529603000, 0.1960918000"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "setup_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - timing () { - fall_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.183546900, -0.369696000, -0.658188800", \ - "-0.075522800, -0.259230500, -0.551385400", \ - "0.0103333000, -0.172153600, -0.461867200"); - } - related_pin : "CLK"; - rise_constraint ("vio_3_3_1") { - index_1("0.0100000000, 0.5000000000, 1.5000000000"); - index_2("0.0100000000, 0.5000000000, 1.5000000000"); - values("-0.087111300, -0.220770200, -0.321274700", \ - "-0.020591100, -0.148146500, -0.251092400", \ - "0.0127747000, -0.114780600, -0.216505900"); - } - sim_opt : "runlvl=5 accurate=1"; - timing_type : "hold_rising"; - violation_delay_degrade_pct : "10.000000000"; - } - } - test_cell () { - ff ("IQ","IQ_N") { - clocked_on : "CLK"; - next_state : "(D&DE) | (IQ&!DE)"; - } - pin ("CLK") { - direction : "input"; - } - pin ("D") { - direction : "input"; - } - pin ("DE") { - direction : "input"; - } - pin ("Q") { - direction : "output"; - function : "IQ"; - signal_type : "test_scan_out"; - } - pin ("SCD") { - direction : "input"; - signal_type : "test_scan_in"; - } - pin ("SCE") { - direction : "input"; - signal_type : "test_scan_enable"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor2_1") { - leakage_power () { - value : 0.0025566000; - when : "!A&B"; - } - leakage_power () { - value : 0.0004804000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0029874000; - when : "A&B"; - } - leakage_power () { - value : 0.0022371000; - when : "A&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__xnor2"; - cell_leakage_power : 0.0020653530; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0045080000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0043390000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046770000; - } - pin ("B") { - capacitance : 0.0045620000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0044710000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0046530000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B) | (A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0212541000, 0.0203966000, 0.0183263000, 0.0132743000, 0.0013083000, -0.026319100, -0.089446600", \ - "0.0210621000, 0.0202046000, 0.0181343000, 0.0130928000, 0.0011272000, -0.026500500, -0.089627300", \ - "0.0208378000, 0.0199789000, 0.0178990000, 0.0128577000, 0.0008925000, -0.026712500, -0.089825100", \ - "0.0206691000, 0.0197848000, 0.0176785000, 0.0126095000, 0.0006779000, -0.026902700, -0.090000800", \ - "0.0206612000, 0.0197631000, 0.0176218000, 0.0125632000, 0.0006588000, -0.026882000, -0.089950000", \ - "0.0207164000, 0.0197238000, 0.0174623000, 0.0123643000, 0.0010442000, -0.026479400, -0.089512500", \ - "0.0222263000, 0.0212939000, 0.0189236000, 0.0136613000, 0.0015636000, -0.025970100, -0.088417900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0046536000, 0.0057919000, 0.0082625000, 0.0136885000, 0.0257722000, 0.0531978000, 0.1156202000", \ - "0.0044444000, 0.0055590000, 0.0080568000, 0.0134927000, 0.0256073000, 0.0530626000, 0.1156251000", \ - "0.0041199000, 0.0052441000, 0.0077323000, 0.0132036000, 0.0253521000, 0.0528241000, 0.1154207000", \ - "0.0037972000, 0.0048996000, 0.0073834000, 0.0128788000, 0.0251300000, 0.0527196000, 0.1151657000", \ - "0.0037841000, 0.0047206000, 0.0071214000, 0.0126143000, 0.0247897000, 0.0524473000, 0.1151301000", \ - "0.0038968000, 0.0049861000, 0.0074544000, 0.0129104000, 0.0248100000, 0.0525599000, 0.1149145000", \ - "0.0047804000, 0.0057978000, 0.0082136000, 0.0138364000, 0.0259337000, 0.0535550000, 0.1165356000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0210798000, 0.0200224000, 0.0175806000, 0.0120262000, -0.000426900, -0.028411500, -0.091767100", \ - "0.0206999000, 0.0196344000, 0.0172140000, 0.0116620000, -0.000787500, -0.028766300, -0.092073000", \ - "0.0201792000, 0.0191027000, 0.0166971000, 0.0111984000, -0.001197600, -0.029178600, -0.092427500", \ - "0.0195687000, 0.0185355000, 0.0162002000, 0.0107901000, -0.001517700, -0.029436400, -0.092766000", \ - "0.0193002000, 0.0182926000, 0.0159620000, 0.0106365000, -0.001586800, -0.029423800, -0.092736500", \ - "0.0189621000, 0.0179525000, 0.0155698000, 0.0102003000, -0.001380200, -0.029122000, -0.092381400", \ - "0.0204586000, 0.0194496000, 0.0172061000, 0.0119098000, -0.000194000, -0.027955500, -0.090612600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011382370, 0.0025911690, 0.0058987310, 0.0134283100, 0.0305692200, 0.0695900500"); - values("0.0062226000, 0.0073435000, 0.0098230000, 0.0152310000, 0.0272283000, 0.0547078000, 0.1167354000", \ - "0.0059629000, 0.0070876000, 0.0095623000, 0.0149857000, 0.0270056000, 0.0545144000, 0.1172284000", \ - "0.0055694000, 0.0066886000, 0.0091528000, 0.0145690000, 0.0266453000, 0.0543286000, 0.1165925000", \ - "0.0051805000, 0.0062667000, 0.0087231000, 0.0141126000, 0.0263342000, 0.0538733000, 0.1163511000", \ - "0.0053184000, 0.0062469000, 0.0086151000, 0.0139722000, 0.0261111000, 0.0537772000, 0.1164143000", \ - "0.0057322000, 0.0068003000, 0.0092021000, 0.0145291000, 0.0263700000, 0.0540804000, 0.1165046000", \ - "0.0073903000, 0.0084192000, 0.0108560000, 0.0161787000, 0.0282496000, 0.0554913000, 0.1186286000"); - } - } - max_capacitance : 0.0695900000; - max_transition : 1.4892980000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0374137000, 0.0414031000, 0.0501328000, 0.0689368000, 0.1105394000, 0.2037041000, 0.4145033000", \ - "0.0423143000, 0.0463179000, 0.0550444000, 0.0740452000, 0.1156761000, 0.2086769000, 0.4195883000", \ - "0.0517034000, 0.0557622000, 0.0645395000, 0.0836287000, 0.1253351000, 0.2185252000, 0.4295134000", \ - "0.0682622000, 0.0729351000, 0.0832887000, 0.1037547000, 0.1458845000, 0.2393883000, 0.4504921000", \ - "0.0912211000, 0.0983857000, 0.1125359000, 0.1401068000, 0.1900582000, 0.2871116000, 0.4988291000", \ - "0.1128187000, 0.1240902000, 0.1463828000, 0.1885505000, 0.2613697000, 0.3846934000, 0.6101555000", \ - "0.1071319000, 0.1255547000, 0.1627196000, 0.2307021000, 0.3466455000, 0.5321230000, 0.8269580000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0941213000, 0.1040279000, 0.1265192000, 0.1764383000, 0.2886966000, 0.5430323000, 1.1200462000", \ - "0.0988531000, 0.1090306000, 0.1316310000, 0.1818392000, 0.2946032000, 0.5488541000, 1.1260067000", \ - "0.1115258000, 0.1216865000, 0.1442828000, 0.1948122000, 0.3076115000, 0.5624227000, 1.1393637000", \ - "0.1396824000, 0.1496877000, 0.1722470000, 0.2226296000, 0.3356868000, 0.5906368000, 1.1686353000", \ - "0.1982890000, 0.2102514000, 0.2351971000, 0.2857881000, 0.3987954000, 0.6540214000, 1.2323496000", \ - "0.3009308000, 0.3169627000, 0.3501765000, 0.4171192000, 0.5445996000, 0.8002156000, 1.3792549000", \ - "0.4725413000, 0.4976712000, 0.5499183000, 0.6470857000, 0.8225922000, 1.1309064000, 1.7157147000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0255116000, 0.0303044000, 0.0410405000, 0.0652203000, 0.1202617000, 0.2445203000, 0.5287258000", \ - "0.0255630000, 0.0304168000, 0.0411482000, 0.0653830000, 0.1203124000, 0.2443628000, 0.5285509000", \ - "0.0260761000, 0.0307138000, 0.0411967000, 0.0653758000, 0.1203064000, 0.2443603000, 0.5281008000", \ - "0.0324194000, 0.0368225000, 0.0466769000, 0.0683918000, 0.1212277000, 0.2443447000, 0.5282029000", \ - "0.0491879000, 0.0546326000, 0.0654179000, 0.0885335000, 0.1353784000, 0.2496287000, 0.5284382000", \ - "0.0836209000, 0.0910877000, 0.1059869000, 0.1347443000, 0.1872409000, 0.2944901000, 0.5449606000", \ - "0.1484122000, 0.1598077000, 0.1817400000, 0.2236170000, 0.2952565000, 0.4201456000, 0.6569621000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0714559000, 0.0844234000, 0.1139729000, 0.1812960000, 0.3340109000, 0.6815455000, 1.4741902000", \ - "0.0714053000, 0.0845634000, 0.1141746000, 0.1815512000, 0.3345667000, 0.6820500000, 1.4700076000", \ - "0.0713463000, 0.0845266000, 0.1140820000, 0.1812062000, 0.3339938000, 0.6815553000, 1.4713369000", \ - "0.0716971000, 0.0844849000, 0.1140594000, 0.1813920000, 0.3339456000, 0.6818059000, 1.4714270000", \ - "0.0877275000, 0.0990177000, 0.1247999000, 0.1865859000, 0.3343727000, 0.6815178000, 1.4715268000", \ - "0.1286496000, 0.1417827000, 0.1701993000, 0.2293134000, 0.3604324000, 0.6859468000, 1.4738862000", \ - "0.2134171000, 0.2303635000, 0.2671819000, 0.3367471000, 0.4756940000, 0.7623122000, 1.4843476000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0879736000, 0.0928356000, 0.1026908000, 0.1222338000, 0.1626539000, 0.2518160000, 0.4547098000", \ - "0.0932477000, 0.0981090000, 0.1079727000, 0.1275049000, 0.1679441000, 0.2571461000, 0.4599539000", \ - "0.1066165000, 0.1114599000, 0.1212622000, 0.1408419000, 0.1812395000, 0.2706052000, 0.4725861000", \ - "0.1386916000, 0.1434817000, 0.1532383000, 0.1727714000, 0.2132622000, 0.3027510000, 0.5045380000", \ - "0.2050795000, 0.2102447000, 0.2204814000, 0.2405946000, 0.2816081000, 0.3709620000, 0.5738020000", \ - "0.3140539000, 0.3204041000, 0.3325247000, 0.3538867000, 0.3964442000, 0.4865219000, 0.6887515000", \ - "0.4895530000, 0.4979859000, 0.5139256000, 0.5409110000, 0.5875962000, 0.6786547000, 0.8808565000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0751694000, 0.0810697000, 0.0933653000, 0.1191934000, 0.1757629000, 0.3037600000, 0.5957271000", \ - "0.0793663000, 0.0852165000, 0.0975409000, 0.1234232000, 0.1803780000, 0.3085979000, 0.6006250000", \ - "0.0881773000, 0.0940095000, 0.1063585000, 0.1324048000, 0.1891873000, 0.3171431000, 0.6091715000", \ - "0.1063799000, 0.1123094000, 0.1247651000, 0.1508675000, 0.2083215000, 0.3369048000, 0.6313726000", \ - "0.1333069000, 0.1395361000, 0.1525422000, 0.1791110000, 0.2368350000, 0.3662150000, 0.6591384000", \ - "0.1625237000, 0.1696954000, 0.1837260000, 0.2112414000, 0.2691012000, 0.3991435000, 0.6901895000", \ - "0.1712796000, 0.1804689000, 0.1983677000, 0.2293151000, 0.2886584000, 0.4181494000, 0.7121305000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0224865000, 0.0268848000, 0.0367783000, 0.0585781000, 0.1091097000, 0.2281268000, 0.4979848000", \ - "0.0224936000, 0.0269522000, 0.0367106000, 0.0585942000, 0.1092634000, 0.2282550000, 0.4977491000", \ - "0.0225816000, 0.0269946000, 0.0367711000, 0.0587650000, 0.1093991000, 0.2273926000, 0.5020171000", \ - "0.0227575000, 0.0271991000, 0.0368878000, 0.0586740000, 0.1093658000, 0.2282439000, 0.5016808000", \ - "0.0259716000, 0.0303122000, 0.0395581000, 0.0607494000, 0.1102675000, 0.2275468000, 0.4978004000", \ - "0.0347855000, 0.0388052000, 0.0476079000, 0.0681257000, 0.1147722000, 0.2288841000, 0.5004079000", \ - "0.0502125000, 0.0550223000, 0.0641964000, 0.0825912000, 0.1251897000, 0.2335291000, 0.5011518000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0270080000, 0.0334043000, 0.0482756000, 0.0827941000, 0.1628451000, 0.3475847000, 0.7662062000", \ - "0.0270598000, 0.0334770000, 0.0482956000, 0.0828084000, 0.1631730000, 0.3477769000, 0.7697812000", \ - "0.0270525000, 0.0335187000, 0.0484306000, 0.0827948000, 0.1632542000, 0.3475653000, 0.7683433000", \ - "0.0279784000, 0.0343572000, 0.0488672000, 0.0830828000, 0.1634631000, 0.3479544000, 0.7701059000", \ - "0.0309263000, 0.0370766000, 0.0512037000, 0.0847123000, 0.1636328000, 0.3468329000, 0.7665360000", \ - "0.0378687000, 0.0435559000, 0.0565700000, 0.0876585000, 0.1651761000, 0.3479284000, 0.7631074000", \ - "0.0526271000, 0.0583749000, 0.0708549000, 0.0985604000, 0.1694503000, 0.3495317000, 0.7678985000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0296097000, 0.0332590000, 0.0412041000, 0.0589563000, 0.0984756000, 0.1875731000, 0.3892678000", \ - "0.0345021000, 0.0382876000, 0.0464941000, 0.0645287000, 0.1042095000, 0.1932805000, 0.3955867000", \ - "0.0440310000, 0.0480741000, 0.0565564000, 0.0747690000, 0.1147084000, 0.2040165000, 0.4057167000", \ - "0.0579213000, 0.0636453000, 0.0746488000, 0.0955968000, 0.1364075000, 0.2262785000, 0.4288422000", \ - "0.0739048000, 0.0825315000, 0.0993813000, 0.1296888000, 0.1826285000, 0.2767357000, 0.4798069000", \ - "0.0822701000, 0.0962199000, 0.1236074000, 0.1719301000, 0.2512824000, 0.3786568000, 0.5984508000", \ - "0.0546336000, 0.0788279000, 0.1240999000, 0.2033454000, 0.3306776000, 0.5268614000, 0.8257231000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0794984000, 0.0896267000, 0.1120081000, 0.1623149000, 0.2747146000, 0.5290156000, 1.1062609000", \ - "0.0823325000, 0.0926695000, 0.1153646000, 0.1659634000, 0.2788389000, 0.5332907000, 1.1104816000", \ - "0.0925919000, 0.1027798000, 0.1257377000, 0.1764136000, 0.2898095000, 0.5448647000, 1.1226516000", \ - "0.1215620000, 0.1310412000, 0.1535347000, 0.2040695000, 0.3173043000, 0.5727758000, 1.1514181000", \ - "0.1843802000, 0.1968836000, 0.2221036000, 0.2725996000, 0.3843523000, 0.6378045000, 1.2161813000", \ - "0.2857073000, 0.3044930000, 0.3429741000, 0.4160355000, 0.5444155000, 0.7965920000, 1.3715663000", \ - "0.4520108000, 0.4801604000, 0.5391168000, 0.6501808000, 0.8431987000, 1.1646741000, 1.7389461000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0167247000, 0.0214293000, 0.0319246000, 0.0556031000, 0.1079566000, 0.2274689000, 0.5020126000", \ - "0.0169897000, 0.0216114000, 0.0321598000, 0.0554673000, 0.1082767000, 0.2269143000, 0.4988090000", \ - "0.0183508000, 0.0226268000, 0.0325875000, 0.0557693000, 0.1084155000, 0.2283666000, 0.5004188000", \ - "0.0263903000, 0.0307920000, 0.0401839000, 0.0599549000, 0.1092518000, 0.2282024000, 0.5010586000", \ - "0.0443882000, 0.0498130000, 0.0610617000, 0.0830309000, 0.1281234000, 0.2331985000, 0.4989655000", \ - "0.0796239000, 0.0875368000, 0.1031613000, 0.1319726000, 0.1836345000, 0.2839029000, 0.5175134000", \ - "0.1485336000, 0.1597285000, 0.1823033000, 0.2239612000, 0.2935844000, 0.4169944000, 0.6444105000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0712430000, 0.0843621000, 0.1140498000, 0.1812956000, 0.3340228000, 0.6819277000, 1.4750530000", \ - "0.0712513000, 0.0843401000, 0.1140488000, 0.1813947000, 0.3340984000, 0.6818103000, 1.4707817000", \ - "0.0710222000, 0.0841446000, 0.1139301000, 0.1814288000, 0.3339505000, 0.6808313000, 1.4694421000", \ - "0.0732621000, 0.0852946000, 0.1138138000, 0.1811932000, 0.3338476000, 0.6810004000, 1.4765342000", \ - "0.1003642000, 0.1111732000, 0.1331563000, 0.1904222000, 0.3338433000, 0.6824564000, 1.4713941000", \ - "0.1509524000, 0.1669761000, 0.1981301000, 0.2578159000, 0.3733653000, 0.6854615000, 1.4744737000", \ - "0.2372217000, 0.2607529000, 0.3092593000, 0.3940715000, 0.5414956000, 0.8004314000, 1.4892981000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0896917000, 0.0939260000, 0.1029449000, 0.1216708000, 0.1625840000, 0.2547513000, 0.4651192000", \ - "0.0941638000, 0.0984198000, 0.1074572000, 0.1261522000, 0.1671106000, 0.2593133000, 0.4696858000", \ - "0.1061412000, 0.1102558000, 0.1194068000, 0.1383789000, 0.1794195000, 0.2716652000, 0.4820229000", \ - "0.1359716000, 0.1403478000, 0.1495754000, 0.1688446000, 0.2101039000, 0.3025749000, 0.5125907000", \ - "0.1927894000, 0.1978528000, 0.2079361000, 0.2283960000, 0.2706861000, 0.3635023000, 0.5735153000", \ - "0.2815027000, 0.2877836000, 0.3001047000, 0.3226654000, 0.3665753000, 0.4603271000, 0.6711419000", \ - "0.4228669000, 0.4309682000, 0.4472404000, 0.4749996000, 0.5230005000, 0.6171115000, 0.8281621000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0735055000, 0.0793933000, 0.0916209000, 0.1173552000, 0.1734661000, 0.3010142000, 0.5922055000", \ - "0.0772127000, 0.0830754000, 0.0953330000, 0.1211060000, 0.1773349000, 0.3052280000, 0.5965844000", \ - "0.0869150000, 0.0927813000, 0.1049425000, 0.1306719000, 0.1874039000, 0.3150908000, 0.6070271000", \ - "0.1073829000, 0.1133407000, 0.1257020000, 0.1516962000, 0.2087018000, 0.3369135000, 0.6277950000", \ - "0.1347192000, 0.1409291000, 0.1536680000, 0.1801952000, 0.2377425000, 0.3667317000, 0.6601857000", \ - "0.1647985000, 0.1720189000, 0.1856781000, 0.2126279000, 0.2702072000, 0.4006623000, 0.6914623000", \ - "0.1784490000, 0.1881013000, 0.2051033000, 0.2359150000, 0.2938938000, 0.4218359000, 0.7166640000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0294038000, 0.0343572000, 0.0447105000, 0.0677682000, 0.1212734000, 0.2447817000, 0.5285538000", \ - "0.0294680000, 0.0343957000, 0.0447266000, 0.0678491000, 0.1212757000, 0.2447950000, 0.5285165000", \ - "0.0295784000, 0.0344992000, 0.0448423000, 0.0680272000, 0.1212248000, 0.2447509000, 0.5280468000", \ - "0.0301526000, 0.0348658000, 0.0451552000, 0.0682463000, 0.1211151000, 0.2450755000, 0.5283030000", \ - "0.0312519000, 0.0362567000, 0.0467763000, 0.0694554000, 0.1218535000, 0.2452314000, 0.5289987000", \ - "0.0368908000, 0.0419788000, 0.0515685000, 0.0733067000, 0.1235176000, 0.2452375000, 0.5276424000", \ - "0.0496504000, 0.0554734000, 0.0662531000, 0.0872547000, 0.1342103000, 0.2476879000, 0.5286290000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011382400, 0.0025911700, 0.0058987300, 0.0134283000, 0.0305692000, 0.0695901000"); - values("0.0270759000, 0.0335480000, 0.0482992000, 0.0827999000, 0.1632061000, 0.3474849000, 0.7647624000", \ - "0.0271138000, 0.0335014000, 0.0483234000, 0.0827844000, 0.1632423000, 0.3477507000, 0.7670519000", \ - "0.0271249000, 0.0335762000, 0.0484280000, 0.0828755000, 0.1631988000, 0.3486650000, 0.7682027000", \ - "0.0284521000, 0.0347648000, 0.0492729000, 0.0833441000, 0.1633007000, 0.3476028000, 0.7657633000", \ - "0.0312800000, 0.0373027000, 0.0513653000, 0.0851627000, 0.1640390000, 0.3473424000, 0.7697290000", \ - "0.0389901000, 0.0445632000, 0.0570089000, 0.0881072000, 0.1655975000, 0.3486771000, 0.7639235000", \ - "0.0547110000, 0.0602884000, 0.0719234000, 0.0989714000, 0.1696095000, 0.3494537000, 0.7687415000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor2_2") { - leakage_power () { - value : 0.0117114000; - when : "!A&B"; - } - leakage_power () { - value : 0.0012317000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0074405000; - when : "A&B"; - } - leakage_power () { - value : 0.0104538000; - when : "A&!B"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__xnor2"; - cell_leakage_power : 0.0077093300; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0086790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0083180000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0090400000; - } - pin ("B") { - capacitance : 0.0082590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0080770000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0084420000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B) | (A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012494960, 0.0031224790, 0.0078030470, 0.0194997500, 0.0487297000, 0.1217751000"); - values("0.0416832000, 0.0406495000, 0.0380516000, 0.0311227000, 0.0128520000, -0.034048800, -0.152105000", \ - "0.0412475000, 0.0402383000, 0.0376296000, 0.0307194000, 0.0124477000, -0.034456600, -0.152511600", \ - "0.0407567000, 0.0397449000, 0.0371067000, 0.0301795000, 0.0119136000, -0.034979700, -0.152982000", \ - "0.0403867000, 0.0393446000, 0.0366679000, 0.0296975000, 0.0114377000, -0.035329000, -0.153395200", \ - "0.0403057000, 0.0392889000, 0.0364891000, 0.0294013000, 0.0111041000, -0.035682600, -0.153588900", \ - "0.0404687000, 0.0392825000, 0.0363146000, 0.0288944000, 0.0117189000, -0.034948600, -0.152722300", \ - "0.0444973000, 0.0432732000, 0.0401855000, 0.0326484000, 0.0136517000, -0.033161200, -0.149743400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012494960, 0.0031224790, 0.0078030470, 0.0194997500, 0.0487297000, 0.1217751000"); - values("0.0090853000, 0.0104636000, 0.0138142000, 0.0217932000, 0.0407339000, 0.0873622000, 0.2054364000", \ - "0.0086521000, 0.0100236000, 0.0133980000, 0.0213702000, 0.0403238000, 0.0870311000, 0.2040353000", \ - "0.0080112000, 0.0093698000, 0.0127061000, 0.0206739000, 0.0397164000, 0.0864433000, 0.2023921000", \ - "0.0073230000, 0.0086636000, 0.0119609000, 0.0198972000, 0.0390682000, 0.0860189000, 0.2029474000", \ - "0.0076022000, 0.0088215000, 0.0115920000, 0.0195350000, 0.0386951000, 0.0857337000, 0.2030284000", \ - "0.0076621000, 0.0089082000, 0.0120523000, 0.0197778000, 0.0385398000, 0.0860207000, 0.2023294000", \ - "0.0097530000, 0.0109748000, 0.0139895000, 0.0217196000, 0.0409572000, 0.0882869000, 0.2058311000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012494960, 0.0031224790, 0.0078030470, 0.0194997500, 0.0487297000, 0.1217751000"); - values("0.0402115000, 0.0389753000, 0.0358653000, 0.0280557000, 0.0086491000, -0.039225800, -0.157887500", \ - "0.0395922000, 0.0383693000, 0.0352897000, 0.0275296000, 0.0081574000, -0.039737600, -0.158417800", \ - "0.0387752000, 0.0375801000, 0.0344768000, 0.0267440000, 0.0074943000, -0.040328800, -0.158947900", \ - "0.0377868000, 0.0365736000, 0.0335245000, 0.0259456000, 0.0068547000, -0.040773100, -0.159351500", \ - "0.0368027000, 0.0356140000, 0.0328122000, 0.0252819000, 0.0063268000, -0.041010500, -0.159489700", \ - "0.0364446000, 0.0353252000, 0.0323268000, 0.0247228000, 0.0071493000, -0.039954700, -0.158290300", \ - "0.0397997000, 0.0385617000, 0.0354840000, 0.0279245000, 0.0090814000, -0.038125800, -0.154907600"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012494960, 0.0031224790, 0.0078030470, 0.0194997500, 0.0487297000, 0.1217751000"); - values("0.0124024000, 0.0137876000, 0.0171445000, 0.0249994000, 0.0437482000, 0.0903444000, 0.2074321000", \ - "0.0120005000, 0.0133638000, 0.0167045000, 0.0245894000, 0.0434204000, 0.0899373000, 0.2069668000", \ - "0.0113417000, 0.0126858000, 0.0159923000, 0.0238726000, 0.0428177000, 0.0895349000, 0.2067157000", \ - "0.0106360000, 0.0119389000, 0.0151883000, 0.0230403000, 0.0421940000, 0.0891777000, 0.2072445000", \ - "0.0109636000, 0.0121870000, 0.0149678000, 0.0228561000, 0.0418259000, 0.0888924000, 0.2061174000", \ - "0.0117900000, 0.0130255000, 0.0161583000, 0.0239088000, 0.0424090000, 0.0898087000, 0.2057519000", \ - "0.0152250000, 0.0166509000, 0.0197186000, 0.0276944000, 0.0468381000, 0.0935781000, 0.2111785000"); - } - } - max_capacitance : 0.1217750000; - max_transition : 1.4926540000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0389153000, 0.0416781000, 0.0484181000, 0.0640688000, 0.1014081000, 0.1916577000, 0.4145879000", \ - "0.0436013000, 0.0464734000, 0.0531768000, 0.0690479000, 0.1063295000, 0.1967256000, 0.4198585000", \ - "0.0522621000, 0.0551130000, 0.0618762000, 0.0777773000, 0.1152394000, 0.2056864000, 0.4288654000", \ - "0.0670349000, 0.0703548000, 0.0780708000, 0.0953024000, 0.1335069000, 0.2241232000, 0.4475193000", \ - "0.0879396000, 0.0925825000, 0.1029986000, 0.1251173000, 0.1714597000, 0.2665833000, 0.4907667000", \ - "0.1063393000, 0.1133840000, 0.1289909000, 0.1631151000, 0.2294043000, 0.3503033000, 0.5902641000", \ - "0.0967092000, 0.1075718000, 0.1336832000, 0.1878127000, 0.2911848000, 0.4730243000, 0.7816331000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0996199000, 0.1062194000, 0.1226614000, 0.1623016000, 0.2596385000, 0.5011258000, 1.1018688000", \ - "0.1039442000, 0.1109132000, 0.1272080000, 0.1670653000, 0.2648364000, 0.5066764000, 1.1082325000", \ - "0.1164166000, 0.1230109000, 0.1394998000, 0.1795085000, 0.2777631000, 0.5197671000, 1.1215198000", \ - "0.1436621000, 0.1500880000, 0.1664708000, 0.2062709000, 0.3046764000, 0.5467818000, 1.1482083000", \ - "0.1977831000, 0.2057869000, 0.2237741000, 0.2654994000, 0.3634831000, 0.6060123000, 1.2083256000", \ - "0.2898870000, 0.3005363000, 0.3247641000, 0.3794318000, 0.4961800000, 0.7421772000, 1.3452091000", \ - "0.4385464000, 0.4550689000, 0.4928954000, 0.5737256000, 0.7335714000, 1.0393069000, 1.6583461000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0290679000, 0.0322032000, 0.0399536000, 0.0593891000, 0.1077193000, 0.2282403000, 0.5294839000", \ - "0.0291126000, 0.0322351000, 0.0401100000, 0.0593833000, 0.1077234000, 0.2282317000, 0.5295555000", \ - "0.0294849000, 0.0325473000, 0.0402457000, 0.0593883000, 0.1076549000, 0.2283842000, 0.5295468000", \ - "0.0348560000, 0.0378274000, 0.0453850000, 0.0626676000, 0.1088585000, 0.2283656000, 0.5298685000", \ - "0.0504137000, 0.0538960000, 0.0618077000, 0.0802861000, 0.1241344000, 0.2338672000, 0.5299067000", \ - "0.0838336000, 0.0882809000, 0.0990071000, 0.1237831000, 0.1710680000, 0.2766208000, 0.5454933000", \ - "0.1470148000, 0.1541207000, 0.1698879000, 0.2037961000, 0.2684553000, 0.3914556000, 0.6510288000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0739187000, 0.0824290000, 0.1040391000, 0.1581470000, 0.2924337000, 0.6281171000, 1.4643977000", \ - "0.0737774000, 0.0825892000, 0.1040716000, 0.1580253000, 0.2929360000, 0.6282810000, 1.4661363000", \ - "0.0738510000, 0.0826145000, 0.1042126000, 0.1580234000, 0.2929878000, 0.6305311000, 1.4665325000", \ - "0.0740547000, 0.0825886000, 0.1041637000, 0.1581164000, 0.2929090000, 0.6279753000, 1.4648718000", \ - "0.0897189000, 0.0972614000, 0.1159726000, 0.1651760000, 0.2943568000, 0.6277663000, 1.4653831000", \ - "0.1285473000, 0.1377148000, 0.1592289000, 0.2090759000, 0.3249498000, 0.6345833000, 1.4659826000", \ - "0.2115307000, 0.2226188000, 0.2493215000, 0.3093208000, 0.4381593000, 0.7207995000, 1.4806274000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0994968000, 0.1029960000, 0.1111783000, 0.1287770000, 0.1668899000, 0.2563180000, 0.4772815000", \ - "0.1041526000, 0.1077547000, 0.1158704000, 0.1334958000, 0.1716984000, 0.2611580000, 0.4819320000", \ - "0.1164118000, 0.1199800000, 0.1280930000, 0.1456707000, 0.1838596000, 0.2733628000, 0.4944772000", \ - "0.1473835000, 0.1509393000, 0.1589984000, 0.1765161000, 0.2147509000, 0.3041581000, 0.5263817000", \ - "0.2123168000, 0.2160239000, 0.2244337000, 0.2423490000, 0.2809624000, 0.3707218000, 0.5923958000", \ - "0.3179659000, 0.3225678000, 0.3322822000, 0.3521007000, 0.3927085000, 0.4833515000, 0.7048170000", \ - "0.4852115000, 0.4911559000, 0.5038553000, 0.5281577000, 0.5730688000, 0.6655210000, 0.8871534000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0771294000, 0.0807479000, 0.0890324000, 0.1069834000, 0.1473157000, 0.2448966000, 0.4886881000", \ - "0.0813184000, 0.0849588000, 0.0932756000, 0.1112933000, 0.1516141000, 0.2493131000, 0.4940531000", \ - "0.0901598000, 0.0937610000, 0.1020112000, 0.1199299000, 0.1604604000, 0.2580716000, 0.5015888000", \ - "0.1082726000, 0.1119481000, 0.1202589000, 0.1383981000, 0.1792481000, 0.2773871000, 0.5215777000", \ - "0.1356447000, 0.1395785000, 0.1482355000, 0.1671544000, 0.2088348000, 0.3079187000, 0.5536533000", \ - "0.1651854000, 0.1698266000, 0.1798119000, 0.2002406000, 0.2428977000, 0.3423199000, 0.5866992000", \ - "0.1741695000, 0.1804076000, 0.1936986000, 0.2188953000, 0.2656923000, 0.3655516000, 0.6106097000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0238045000, 0.0270765000, 0.0347184000, 0.0532835000, 0.0990851000, 0.2176597000, 0.5175400000", \ - "0.0239314000, 0.0270418000, 0.0347803000, 0.0532061000, 0.0990563000, 0.2172719000, 0.5196626000", \ - "0.0238026000, 0.0271408000, 0.0346604000, 0.0532738000, 0.0991990000, 0.2173433000, 0.5172927000", \ - "0.0239398000, 0.0270787000, 0.0347408000, 0.0533269000, 0.0992115000, 0.2175627000, 0.5159888000", \ - "0.0266639000, 0.0300409000, 0.0374285000, 0.0553708000, 0.1003554000, 0.2173191000, 0.5160503000", \ - "0.0349668000, 0.0380380000, 0.0448605000, 0.0622511000, 0.1050925000, 0.2198354000, 0.5174082000", \ - "0.0492144000, 0.0529659000, 0.0603176000, 0.0767800000, 0.1163224000, 0.2243886000, 0.5201292000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0238377000, 0.0273080000, 0.0358763000, 0.0572386000, 0.1122380000, 0.2524314000, 0.6088633000", \ - "0.0238590000, 0.0272691000, 0.0358496000, 0.0573600000, 0.1121690000, 0.2526767000, 0.6072618000", \ - "0.0238741000, 0.0273305000, 0.0359106000, 0.0572447000, 0.1122150000, 0.2527431000, 0.6064155000", \ - "0.0247985000, 0.0282291000, 0.0366079000, 0.0577908000, 0.1124232000, 0.2531524000, 0.6083372000", \ - "0.0278839000, 0.0311808000, 0.0395159000, 0.0601120000, 0.1138571000, 0.2527358000, 0.6061950000", \ - "0.0351924000, 0.0384153000, 0.0461727000, 0.0656132000, 0.1166146000, 0.2537713000, 0.6050267000", \ - "0.0491720000, 0.0529417000, 0.0611793000, 0.0793922000, 0.1255094000, 0.2561434000, 0.6068355000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0311375000, 0.0337410000, 0.0400550000, 0.0551946000, 0.0915142000, 0.1803408000, 0.4011080000", \ - "0.0356750000, 0.0384222000, 0.0450170000, 0.0604757000, 0.0971135000, 0.1861971000, 0.4063417000", \ - "0.0436930000, 0.0466574000, 0.0535024000, 0.0693934000, 0.1065191000, 0.1956087000, 0.4165076000", \ - "0.0547657000, 0.0585824000, 0.0671149000, 0.0854798000, 0.1241313000, 0.2143309000, 0.4359652000", \ - "0.0665121000, 0.0722600000, 0.0850551000, 0.1107477000, 0.1602252000, 0.2565130000, 0.4787233000", \ - "0.0673164000, 0.0766348000, 0.0978380000, 0.1378843000, 0.2114553000, 0.3393248000, 0.5793214000", \ - "0.0277789000, 0.0435267000, 0.0786210000, 0.1438126000, 0.2604947000, 0.4538432000, 0.7721969000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0769955000, 0.0839916000, 0.1003178000, 0.1402399000, 0.2377903000, 0.4793942000, 1.0805419000", \ - "0.0796032000, 0.0865099000, 0.1031331000, 0.1434240000, 0.2416291000, 0.4835190000, 1.0868707000", \ - "0.0895695000, 0.0964195000, 0.1130708000, 0.1534978000, 0.2516895000, 0.4940342000, 1.0959753000", \ - "0.1172244000, 0.1237609000, 0.1394874000, 0.1796729000, 0.2780838000, 0.5207941000, 1.1234225000", \ - "0.1757734000, 0.1842201000, 0.2038219000, 0.2452175000, 0.3418820000, 0.5836361000, 1.1862709000", \ - "0.2688047000, 0.2814957000, 0.3109390000, 0.3733518000, 0.4938074000, 0.7362853000, 1.3343782000", \ - "0.4217103000, 0.4422508000, 0.4836530000, 0.5751682000, 0.7565203000, 1.0836645000, 1.6833763000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0171807000, 0.0204862000, 0.0286688000, 0.0485452000, 0.0970520000, 0.2170982000, 0.5196427000", \ - "0.0174804000, 0.0208255000, 0.0290212000, 0.0492351000, 0.0978377000, 0.2176238000, 0.5174676000", \ - "0.0186915000, 0.0218000000, 0.0297068000, 0.0493368000, 0.0978439000, 0.2171421000, 0.5188094000", \ - "0.0252327000, 0.0284227000, 0.0359103000, 0.0537233000, 0.0994385000, 0.2175824000, 0.5188571000", \ - "0.0415808000, 0.0453281000, 0.0538095000, 0.0726570000, 0.1167075000, 0.2235199000, 0.5173667000", \ - "0.0749266000, 0.0801736000, 0.0919438000, 0.1162666000, 0.1643903000, 0.2705809000, 0.5326833000", \ - "0.1426702000, 0.1494159000, 0.1655212000, 0.1993965000, 0.2645960000, 0.3877074000, 0.6461646000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0732385000, 0.0821777000, 0.1039581000, 0.1581069000, 0.2925137000, 0.6280106000, 1.4655046000", \ - "0.0731134000, 0.0820461000, 0.1039695000, 0.1580908000, 0.2930701000, 0.6275976000, 1.4666838000", \ - "0.0725926000, 0.0816164000, 0.1037167000, 0.1580816000, 0.2928150000, 0.6282067000, 1.4696839000", \ - "0.0751765000, 0.0831768000, 0.1037633000, 0.1571017000, 0.2925574000, 0.6298857000, 1.4659202000", \ - "0.1011966000, 0.1096232000, 0.1276975000, 0.1718553000, 0.2945869000, 0.6281871000, 1.4657234000", \ - "0.1470798000, 0.1585958000, 0.1847347000, 0.2378951000, 0.3459189000, 0.6370939000, 1.4640965000", \ - "0.2229202000, 0.2404563000, 0.2776141000, 0.3533346000, 0.5004904000, 0.7739285000, 1.4926543000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0977492000, 0.1007585000, 0.1078462000, 0.1238668000, 0.1606663000, 0.2497965000, 0.4719335000", \ - "0.1020113000, 0.1050447000, 0.1122467000, 0.1282944000, 0.1652059000, 0.2543406000, 0.4763643000", \ - "0.1140854000, 0.1171965000, 0.1243577000, 0.1405338000, 0.1775381000, 0.2666319000, 0.4888511000", \ - "0.1431683000, 0.1463624000, 0.1534903000, 0.1699396000, 0.2073062000, 0.2968491000, 0.5195224000", \ - "0.2009748000, 0.2043524000, 0.2117878000, 0.2295518000, 0.2685595000, 0.3587310000, 0.5810323000", \ - "0.2915635000, 0.2957677000, 0.3051008000, 0.3244716000, 0.3650014000, 0.4572317000, 0.6809531000", \ - "0.4390006000, 0.4446236000, 0.4568715000, 0.4812078000, 0.5267127000, 0.6187031000, 0.8425834000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0719531000, 0.0756071000, 0.0838515000, 0.1016625000, 0.1416891000, 0.2392933000, 0.4832348000", \ - "0.0756024000, 0.0792183000, 0.0874639000, 0.1052634000, 0.1453296000, 0.2425122000, 0.4858323000", \ - "0.0849792000, 0.0885413000, 0.0966448000, 0.1144898000, 0.1549013000, 0.2528589000, 0.4970315000", \ - "0.1042340000, 0.1079124000, 0.1162870000, 0.1344735000, 0.1751479000, 0.2734218000, 0.5166799000", \ - "0.1298521000, 0.1336889000, 0.1423158000, 0.1611230000, 0.2028786000, 0.3023765000, 0.5468438000", \ - "0.1555163000, 0.1600778000, 0.1701114000, 0.1898258000, 0.2313457000, 0.3312614000, 0.5765875000", \ - "0.1595263000, 0.1663141000, 0.1791305000, 0.2037979000, 0.2485996000, 0.3470601000, 0.5929255000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0333858000, 0.0365427000, 0.0443344000, 0.0631215000, 0.1096186000, 0.2287753000, 0.5305182000", \ - "0.0336382000, 0.0368275000, 0.0443743000, 0.0630977000, 0.1095681000, 0.2285771000, 0.5304517000", \ - "0.0336299000, 0.0366740000, 0.0444176000, 0.0631284000, 0.1095678000, 0.2283676000, 0.5295477000", \ - "0.0340278000, 0.0371868000, 0.0449569000, 0.0635655000, 0.1097528000, 0.2286897000, 0.5305421000", \ - "0.0339833000, 0.0376346000, 0.0458904000, 0.0646458000, 0.1105284000, 0.2290093000, 0.5298756000", \ - "0.0376372000, 0.0411215000, 0.0496593000, 0.0673896000, 0.1116174000, 0.2288191000, 0.5298235000", \ - "0.0485691000, 0.0527208000, 0.0615338000, 0.0794710000, 0.1209729000, 0.2304614000, 0.5284458000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012495000, 0.0031224800, 0.0078030500, 0.0194997000, 0.0487297000, 0.1217750000"); - values("0.0238687000, 0.0272879000, 0.0358536000, 0.0574155000, 0.1122726000, 0.2531621000, 0.6070502000", \ - "0.0238686000, 0.0273437000, 0.0358914000, 0.0572527000, 0.1121785000, 0.2528689000, 0.6066060000", \ - "0.0238870000, 0.0273969000, 0.0359561000, 0.0573574000, 0.1121832000, 0.2530293000, 0.6073951000", \ - "0.0252241000, 0.0287114000, 0.0372481000, 0.0582569000, 0.1126128000, 0.2533637000, 0.6088262000", \ - "0.0280665000, 0.0313501000, 0.0394525000, 0.0602696000, 0.1143901000, 0.2530018000, 0.6071555000", \ - "0.0357930000, 0.0387603000, 0.0462179000, 0.0650256000, 0.1163694000, 0.2543435000, 0.6062321000", \ - "0.0503144000, 0.0538968000, 0.0621883000, 0.0794795000, 0.1240303000, 0.2561799000, 0.6083346000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor2_4") { - leakage_power () { - value : 0.0124488000; - when : "!A&B"; - } - leakage_power () { - value : 0.0030378000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0095704000; - when : "A&B"; - } - leakage_power () { - value : 0.0114222000; - when : "A&!B"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__xnor2"; - cell_leakage_power : 0.0091197900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0167660000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0160650000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0174670000; - } - pin ("B") { - capacitance : 0.0159280000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0155930000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0162640000; - } - pin ("Y") { - direction : "output"; - function : "(!A&!B) | (A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0861683000, 0.0849669000, 0.0817112000, 0.0723498000, 0.0448304000, -0.033528800, -0.250532500", \ - "0.0854098000, 0.0842507000, 0.0809507000, 0.0715678000, 0.0440876000, -0.034265800, -0.251284500", \ - "0.0844064000, 0.0832269000, 0.0799157000, 0.0705323000, 0.0430365000, -0.035263800, -0.252270800", \ - "0.0834855000, 0.0822490000, 0.0789020000, 0.0694165000, 0.0418942000, -0.036253200, -0.252962400", \ - "0.0828424000, 0.0815461000, 0.0780734000, 0.0683942000, 0.0408448000, -0.037150900, -0.253720000", \ - "0.0829061000, 0.0815432000, 0.0778106000, 0.0672899000, 0.0419586000, -0.035929700, -0.252185000", \ - "0.0899691000, 0.0885668000, 0.0846191000, 0.0742724000, 0.0454649000, -0.032752000, -0.246819900"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0136436000, 0.0152459000, 0.0195099000, 0.0306936000, 0.0595276000, 0.1373701000, 0.3520755000", \ - "0.0128029000, 0.0143906000, 0.0186987000, 0.0299152000, 0.0587407000, 0.1367737000, 0.3520425000", \ - "0.0115224000, 0.0131076000, 0.0173700000, 0.0285636000, 0.0576689000, 0.1357751000, 0.3502504000", \ - "0.0101932000, 0.0117577000, 0.0159615000, 0.0271519000, 0.0565577000, 0.1351076000, 0.3504466000", \ - "0.0103902000, 0.0116827000, 0.0152402000, 0.0265135000, 0.0560448000, 0.1349531000, 0.3485163000", \ - "0.0109148000, 0.0123474000, 0.0162744000, 0.0270687000, 0.0564115000, 0.1352957000, 0.3488588000", \ - "0.0145992000, 0.0159890000, 0.0198998000, 0.0304659000, 0.0599496000, 0.1398034000, 0.3558579000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0790930000, 0.0775545000, 0.0733835000, 0.0621171000, 0.0316626000, -0.049392500, -0.268064900", \ - "0.0780305000, 0.0765009000, 0.0723421000, 0.0611166000, 0.0307753000, -0.050350100, -0.268843700", \ - "0.0765652000, 0.0750929000, 0.0709932000, 0.0597613000, 0.0295752000, -0.051381100, -0.270117500", \ - "0.0750556000, 0.0735685000, 0.0695593000, 0.0585215000, 0.0286677000, -0.052265000, -0.271017000", \ - "0.0742472000, 0.0728281000, 0.0688480000, 0.0580302000, 0.0285942000, -0.051848600, -0.270807100", \ - "0.0734923000, 0.0720580000, 0.0681685000, 0.0574827000, 0.0305907000, -0.049193100, -0.267955300", \ - "0.0803848000, 0.0790098000, 0.0750520000, 0.0646781000, 0.0355196000, -0.043896100, -0.260613900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013699110, 0.0037533110, 0.0102834000, 0.0281746900, 0.0771936200, 0.2114967000"); - values("0.0196642000, 0.0212621000, 0.0255293000, 0.0365849000, 0.0651743000, 0.1427970000, 0.3577892000", \ - "0.0187797000, 0.0203829000, 0.0246557000, 0.0357347000, 0.0644194000, 0.1422832000, 0.3570270000", \ - "0.0175395000, 0.0191196000, 0.0232904000, 0.0343918000, 0.0633834000, 0.1413930000, 0.3564265000", \ - "0.0162728000, 0.0177732000, 0.0219004000, 0.0329743000, 0.0623457000, 0.1409122000, 0.3547493000", \ - "0.0167131000, 0.0180354000, 0.0215443000, 0.0326183000, 0.0618786000, 0.1407320000, 0.3548660000", \ - "0.0187681000, 0.0202427000, 0.0241446000, 0.0350650000, 0.0642625000, 0.1421638000, 0.3566139000", \ - "0.0243999000, 0.0257853000, 0.0296621000, 0.0403712000, 0.0695040000, 0.1487362000, 0.3640341000"); - } - } - max_capacitance : 0.2114970000; - max_transition : 1.5007420000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0433706000, 0.0453367000, 0.0503733000, 0.0633054000, 0.0969206000, 0.1851898000, 0.4236227000", \ - "0.0480967000, 0.0500034000, 0.0551038000, 0.0681853000, 0.1017158000, 0.1900716000, 0.4284222000", \ - "0.0565350000, 0.0584672000, 0.0635131000, 0.0767980000, 0.1105450000, 0.1989932000, 0.4374227000", \ - "0.0702501000, 0.0725969000, 0.0784502000, 0.0929049000, 0.1275176000, 0.2162940000, 0.4550099000", \ - "0.0901600000, 0.0930594000, 0.1009606000, 0.1191904000, 0.1612806000, 0.2559837000, 0.4957786000", \ - "0.1054088000, 0.1098723000, 0.1217440000, 0.1499850000, 0.2108479000, 0.3316891000, 0.5890547000", \ - "0.0863427000, 0.0937807000, 0.1128108000, 0.1575348000, 0.2537223000, 0.4362713000, 0.7689356000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.1114710000, 0.1159225000, 0.1279386000, 0.1601830000, 0.2462169000, 0.4795539000, 1.1168017000", \ - "0.1154140000, 0.1199479000, 0.1317152000, 0.1645107000, 0.2510678000, 0.4850341000, 1.1214271000", \ - "0.1267482000, 0.1312834000, 0.1432508000, 0.1760819000, 0.2633923000, 0.4976572000, 1.1340502000", \ - "0.1531366000, 0.1577899000, 0.1697835000, 0.2024614000, 0.2899263000, 0.5247492000, 1.1615574000", \ - "0.2087516000, 0.2137615000, 0.2271152000, 0.2612723000, 0.3481232000, 0.5830891000, 1.2207824000", \ - "0.3047221000, 0.3117797000, 0.3297603000, 0.3731633000, 0.4778287000, 0.7181901000, 1.3567074000", \ - "0.4655082000, 0.4759718000, 0.5032751000, 0.5683992000, 0.7123726000, 1.0126332000, 1.6691007000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0328246000, 0.0349202000, 0.0406929000, 0.0566569000, 0.1005987000, 0.2213272000, 0.5536658000", \ - "0.0328307000, 0.0349267000, 0.0407527000, 0.0566906000, 0.1006304000, 0.2216905000, 0.5535692000", \ - "0.0330285000, 0.0350741000, 0.0407761000, 0.0566482000, 0.1006038000, 0.2215482000, 0.5539212000", \ - "0.0381891000, 0.0402402000, 0.0457347000, 0.0605680000, 0.1020319000, 0.2213741000, 0.5537846000", \ - "0.0528662000, 0.0551479000, 0.0612054000, 0.0767116000, 0.1171954000, 0.2276661000, 0.5541576000", \ - "0.0862318000, 0.0892385000, 0.0974563000, 0.1168106000, 0.1621629000, 0.2701728000, 0.5679035000", \ - "0.1504814000, 0.1547636000, 0.1666395000, 0.1947200000, 0.2557399000, 0.3821312000, 0.6713600000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0806455000, 0.0866377000, 0.1022302000, 0.1455467000, 0.2639252000, 0.5877244000, 1.4780006000", \ - "0.0807608000, 0.0862568000, 0.1022006000, 0.1454700000, 0.2639924000, 0.5879292000, 1.4735243000", \ - "0.0806518000, 0.0866005000, 0.1022020000, 0.1457652000, 0.2639654000, 0.5875345000, 1.4723487000", \ - "0.0806905000, 0.0864962000, 0.1023047000, 0.1456960000, 0.2641573000, 0.5870808000, 1.4719675000", \ - "0.0948051000, 0.1000885000, 0.1136087000, 0.1530348000, 0.2656347000, 0.5877778000, 1.4730354000", \ - "0.1321308000, 0.1379456000, 0.1535767000, 0.1946746000, 0.2986135000, 0.5955604000, 1.4732890000", \ - "0.2150811000, 0.2229177000, 0.2413604000, 0.2890561000, 0.4027265000, 0.6834220000, 1.4891730000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.1062858000, 0.1087184000, 0.1148508000, 0.1294900000, 0.1631937000, 0.2463063000, 0.4692751000", \ - "0.1109650000, 0.1133853000, 0.1195172000, 0.1341725000, 0.1679648000, 0.2511905000, 0.4735897000", \ - "0.1233158000, 0.1257255000, 0.1318603000, 0.1464399000, 0.1802085000, 0.2634250000, 0.4866414000", \ - "0.1538985000, 0.1563087000, 0.1623731000, 0.1768919000, 0.2106528000, 0.2940814000, 0.5174504000", \ - "0.2209495000, 0.2234359000, 0.2297303000, 0.2446790000, 0.2786351000, 0.3622533000, 0.5868593000", \ - "0.3322874000, 0.3353366000, 0.3428404000, 0.3594038000, 0.3956097000, 0.4807889000, 0.7044242000", \ - "0.5116579000, 0.5157257000, 0.5255807000, 0.5466497000, 0.5880311000, 0.6758343000, 0.8996423000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0828554000, 0.0854638000, 0.0919658000, 0.1074610000, 0.1439198000, 0.2384544000, 0.4981587000", \ - "0.0869906000, 0.0895855000, 0.0961219000, 0.1116350000, 0.1481469000, 0.2430497000, 0.5034999000", \ - "0.0952302000, 0.0978347000, 0.1043053000, 0.1197494000, 0.1565794000, 0.2514040000, 0.5131093000", \ - "0.1121669000, 0.1147845000, 0.1213999000, 0.1371206000, 0.1743873000, 0.2698650000, 0.5306749000", \ - "0.1377052000, 0.1404602000, 0.1473918000, 0.1638586000, 0.2022901000, 0.2991414000, 0.5592872000", \ - "0.1641376000, 0.1674327000, 0.1751902000, 0.1928799000, 0.2325532000, 0.3301521000, 0.5909532000", \ - "0.1655742000, 0.1698450000, 0.1801487000, 0.2022838000, 0.2465093000, 0.3450240000, 0.6062227000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0245147000, 0.0266235000, 0.0323319000, 0.0473995000, 0.0872301000, 0.1980620000, 0.5066865000", \ - "0.0244099000, 0.0265732000, 0.0324562000, 0.0475182000, 0.0873148000, 0.1979621000, 0.5072415000", \ - "0.0246390000, 0.0268236000, 0.0323972000, 0.0475006000, 0.0873023000, 0.1980191000, 0.5064518000", \ - "0.0245954000, 0.0266876000, 0.0324038000, 0.0476320000, 0.0873316000, 0.1980978000, 0.5073702000", \ - "0.0269713000, 0.0291588000, 0.0347540000, 0.0493969000, 0.0884532000, 0.1983438000, 0.5081293000", \ - "0.0356032000, 0.0374691000, 0.0428560000, 0.0567494000, 0.0939170000, 0.2016021000, 0.5080946000", \ - "0.0504165000, 0.0527444000, 0.0582930000, 0.0724478000, 0.1063927000, 0.2066192000, 0.5105575000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0255694000, 0.0278147000, 0.0340677000, 0.0511225000, 0.0984484000, 0.2318277000, 0.6032659000", \ - "0.0255030000, 0.0277907000, 0.0341078000, 0.0510815000, 0.0985051000, 0.2320978000, 0.6027592000", \ - "0.0255634000, 0.0278500000, 0.0341277000, 0.0511075000, 0.0984393000, 0.2320118000, 0.6038733000", \ - "0.0264438000, 0.0288015000, 0.0349743000, 0.0516880000, 0.0986900000, 0.2313666000, 0.6020711000", \ - "0.0293351000, 0.0314647000, 0.0376875000, 0.0541248000, 0.1005765000, 0.2320812000, 0.6002693000", \ - "0.0362512000, 0.0382865000, 0.0445000000, 0.0597736000, 0.1034032000, 0.2336652000, 0.6010125000", \ - "0.0508186000, 0.0528307000, 0.0590053000, 0.0737918000, 0.1132466000, 0.2365962000, 0.6050034000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0352815000, 0.0370315000, 0.0415947000, 0.0533460000, 0.0840623000, 0.1665917000, 0.3890193000", \ - "0.0395347000, 0.0413298000, 0.0460695000, 0.0582550000, 0.0894908000, 0.1715187000, 0.3944696000", \ - "0.0475697000, 0.0495175000, 0.0545225000, 0.0670635000, 0.0989002000, 0.1816361000, 0.4043040000", \ - "0.0586230000, 0.0610559000, 0.0673226000, 0.0820550000, 0.1159612000, 0.1995792000, 0.4234630000", \ - "0.0691877000, 0.0729020000, 0.0821645000, 0.1035775000, 0.1475503000, 0.2401087000, 0.4651209000", \ - "0.0664912000, 0.0725607000, 0.0868812000, 0.1208933000, 0.1890794000, 0.3155613000, 0.5622409000", \ - "0.0155959000, 0.0255836000, 0.0518217000, 0.1062293000, 0.2156762000, 0.4094078000, 0.7434722000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0894431000, 0.0940604000, 0.1063377000, 0.1388589000, 0.2255568000, 0.4589984000, 1.0956753000", \ - "0.0911656000, 0.0960730000, 0.1082078000, 0.1414389000, 0.2284199000, 0.4623537000, 1.0987684000", \ - "0.1003240000, 0.1050921000, 0.1172614000, 0.1504534000, 0.2379830000, 0.4727090000, 1.1098718000", \ - "0.1275764000, 0.1322033000, 0.1443194000, 0.1768991000, 0.2638104000, 0.4990175000, 1.1371351000", \ - "0.1903227000, 0.1958274000, 0.2098645000, 0.2437265000, 0.3290452000, 0.5633177000, 1.2016934000", \ - "0.2923067000, 0.3004558000, 0.3212257000, 0.3719020000, 0.4815066000, 0.7168229000, 1.3526478000", \ - "0.4629533000, 0.4741891000, 0.5028059000, 0.5788611000, 0.7409546000, 1.0652395000, 1.7065545000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0176550000, 0.0198276000, 0.0255669000, 0.0413932000, 0.0838727000, 0.1976204000, 0.5072198000", \ - "0.0179207000, 0.0200812000, 0.0259553000, 0.0418130000, 0.0840755000, 0.1979208000, 0.5064345000", \ - "0.0191497000, 0.0212100000, 0.0267788000, 0.0422002000, 0.0844718000, 0.1975018000, 0.5076811000", \ - "0.0255271000, 0.0275647000, 0.0331186000, 0.0477009000, 0.0864259000, 0.1980653000, 0.5083056000", \ - "0.0419680000, 0.0442507000, 0.0506386000, 0.0661861000, 0.1044096000, 0.2055870000, 0.5078955000", \ - "0.0759757000, 0.0790331000, 0.0876781000, 0.1078272000, 0.1524845000, 0.2544421000, 0.5260616000", \ - "0.1440202000, 0.1483476000, 0.1601621000, 0.1883906000, 0.2486804000, 0.3709742000, 0.6412829000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0803624000, 0.0862636000, 0.1022039000, 0.1455623000, 0.2642236000, 0.5871529000, 1.4710115000", \ - "0.0803251000, 0.0862608000, 0.1020876000, 0.1456593000, 0.2638403000, 0.5873961000, 1.4722475000", \ - "0.0799587000, 0.0859307000, 0.1017819000, 0.1455501000, 0.2638417000, 0.5876576000, 1.4710231000", \ - "0.0810427000, 0.0863967000, 0.1016107000, 0.1447076000, 0.2639333000, 0.5871530000, 1.4732598000", \ - "0.1068121000, 0.1118868000, 0.1242415000, 0.1596634000, 0.2662308000, 0.5874368000, 1.4728216000", \ - "0.1534365000, 0.1598113000, 0.1787846000, 0.2235031000, 0.3208799000, 0.5991684000, 1.4729828000", \ - "0.2295785000, 0.2403665000, 0.2672158000, 0.3342095000, 0.4682147000, 0.7345262000, 1.5007421000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0935093000, 0.0954990000, 0.1006497000, 0.1136166000, 0.1460953000, 0.2324437000, 0.4693996000", \ - "0.0981714000, 0.1001499000, 0.1053114000, 0.1183277000, 0.1510089000, 0.2374563000, 0.4744277000", \ - "0.1104030000, 0.1123714000, 0.1176958000, 0.1307968000, 0.1635261000, 0.2499519000, 0.4866218000", \ - "0.1407252000, 0.1427933000, 0.1482483000, 0.1615412000, 0.1945963000, 0.2812332000, 0.5181434000", \ - "0.2013146000, 0.2035931000, 0.2094098000, 0.2236051000, 0.2579722000, 0.3450789000, 0.5816173000", \ - "0.2978895000, 0.3007057000, 0.3077162000, 0.3240106000, 0.3605816000, 0.4493251000, 0.6868556000", \ - "0.4558866000, 0.4596746000, 0.4690985000, 0.4898670000, 0.5321134000, 0.6235362000, 0.8612472000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0778196000, 0.0804114000, 0.0869172000, 0.1022356000, 0.1384243000, 0.2329697000, 0.4928489000", \ - "0.0812731000, 0.0838694000, 0.0903779000, 0.1057578000, 0.1420294000, 0.2368998000, 0.4956549000", \ - "0.0902659000, 0.0928219000, 0.0993841000, 0.1147507000, 0.1514599000, 0.2461453000, 0.5060897000", \ - "0.1095344000, 0.1121835000, 0.1187825000, 0.1345597000, 0.1717429000, 0.2672413000, 0.5276065000", \ - "0.1345677000, 0.1372654000, 0.1440891000, 0.1602968000, 0.1989527000, 0.2959328000, 0.5555164000", \ - "0.1585782000, 0.1617941000, 0.1694113000, 0.1866177000, 0.2256317000, 0.3222964000, 0.5842075000", \ - "0.1567505000, 0.1609748000, 0.1708803000, 0.1928089000, 0.2346894000, 0.3315348000, 0.5939198000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0368622000, 0.0390765000, 0.0449064000, 0.0605744000, 0.1029867000, 0.2216907000, 0.5540532000", \ - "0.0369148000, 0.0391043000, 0.0449080000, 0.0605773000, 0.1029674000, 0.2219741000, 0.5535201000", \ - "0.0367973000, 0.0390669000, 0.0449984000, 0.0605389000, 0.1029331000, 0.2219649000, 0.5543047000", \ - "0.0370990000, 0.0394040000, 0.0451916000, 0.0608244000, 0.1029317000, 0.2219647000, 0.5543093000", \ - "0.0361728000, 0.0385302000, 0.0446525000, 0.0612725000, 0.1032341000, 0.2220998000, 0.5544427000", \ - "0.0391234000, 0.0415246000, 0.0474518000, 0.0630629000, 0.1040902000, 0.2215390000, 0.5529634000", \ - "0.0494114000, 0.0520519000, 0.0591301000, 0.0756065000, 0.1142857000, 0.2233734000, 0.5509738000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013699100, 0.0037533100, 0.0102834000, 0.0281747000, 0.0771936000, 0.2114970000"); - values("0.0255269000, 0.0278232000, 0.0341731000, 0.0511804000, 0.0986566000, 0.2316991000, 0.6024007000", \ - "0.0255228000, 0.0278273000, 0.0341737000, 0.0512187000, 0.0985469000, 0.2318790000, 0.6050904000", \ - "0.0255345000, 0.0279013000, 0.0341683000, 0.0511861000, 0.0984896000, 0.2319595000, 0.6034798000", \ - "0.0270024000, 0.0293665000, 0.0355487000, 0.0522590000, 0.0989446000, 0.2314975000, 0.6026815000", \ - "0.0293326000, 0.0314843000, 0.0376244000, 0.0542786000, 0.1013152000, 0.2329248000, 0.6020465000", \ - "0.0371289000, 0.0393486000, 0.0445492000, 0.0594313000, 0.1032342000, 0.2348178000, 0.6018213000", \ - "0.0519052000, 0.0542855000, 0.0598419000, 0.0740121000, 0.1125662000, 0.2364119000, 0.6056086000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor3_1") { - leakage_power () { - value : 0.0140429000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0082385000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0200387000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0228060000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0084287000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0111960000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0229939000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0171894000; - when : "A&B&!C"; - } - area : 22.521600000; - cell_footprint : "sky130_fd_sc_hd__xnor3"; - cell_leakage_power : 0.0156167600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024440000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0023000000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025880000; - } - pin ("B") { - capacitance : 0.0052840000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051310000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054360000; - } - pin ("C") { - capacitance : 0.0034800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033610000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035990000; - } - pin ("X") { - direction : "output"; - function : "(!A&!B&!C) | (A&B&!C) | (A&!B&C) | (!A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0459356000, 0.0448634000, 0.0424627000, 0.0355321000, 0.0147288000, -0.043637100, -0.197702100", \ - "0.0457716000, 0.0446992000, 0.0423091000, 0.0353533000, 0.0146124000, -0.043810000, -0.197892500", \ - "0.0455475000, 0.0444947000, 0.0420816000, 0.0351400000, 0.0143406000, -0.044022400, -0.198081300", \ - "0.0454022000, 0.0443526000, 0.0419124000, 0.0349613000, 0.0141833000, -0.044194700, -0.198255200", \ - "0.0451508000, 0.0440850000, 0.0416560000, 0.0346645000, 0.0138598000, -0.044495700, -0.198535400", \ - "0.0456332000, 0.0445324000, 0.0420317000, 0.0349738000, 0.0140379000, -0.044335200, -0.198360800", \ - "0.0508615000, 0.0493335000, 0.0456214000, 0.0364433000, 0.0155465000, -0.042850600, -0.196900000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0385232000, 0.0404631000, 0.0450669000, 0.0548270000, 0.0776663000, 0.1364971000, 0.2896736000", \ - "0.0385145000, 0.0403666000, 0.0450239000, 0.0547455000, 0.0775921000, 0.1362166000, 0.2896269000", \ - "0.0383312000, 0.0401771000, 0.0448533000, 0.0545830000, 0.0773806000, 0.1360411000, 0.2894212000", \ - "0.0379676000, 0.0398611000, 0.0445231000, 0.0542913000, 0.0770855000, 0.1357566000, 0.2891762000", \ - "0.0376813000, 0.0395875000, 0.0442906000, 0.0540884000, 0.0768979000, 0.1357266000, 0.2874794000", \ - "0.0394512000, 0.0407481000, 0.0443340000, 0.0540907000, 0.0767340000, 0.1354691000, 0.2884890000", \ - "0.0416735000, 0.0429754000, 0.0463506000, 0.0551230000, 0.0774953000, 0.1363046000, 0.2888866000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0422326000, 0.0412427000, 0.0387451000, 0.0316316000, 0.0106285000, -0.047852700, -0.201957500", \ - "0.0420649000, 0.0410740000, 0.0385715000, 0.0314594000, 0.0104400000, -0.048028200, -0.202129200", \ - "0.0419008000, 0.0409096000, 0.0384193000, 0.0312907000, 0.0102835000, -0.048194800, -0.202291600", \ - "0.0419317000, 0.0409362000, 0.0384412000, 0.0313140000, 0.0103165000, -0.048154000, -0.202248200", \ - "0.0420987000, 0.0410901000, 0.0385977000, 0.0314607000, 0.0104490000, -0.048037800, -0.202110500", \ - "0.0436520000, 0.0425622000, 0.0400446000, 0.0328491000, 0.0117816000, -0.046667900, -0.200755400", \ - "0.0511074000, 0.0496323000, 0.0459891000, 0.0370217000, 0.0147515000, -0.043125700, -0.197177200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0293238000, 0.0309630000, 0.0351413000, 0.0445200000, 0.0673079000, 0.1260699000, 0.2787790000", \ - "0.0289448000, 0.0305822000, 0.0347231000, 0.0441153000, 0.0668879000, 0.1255299000, 0.2786966000", \ - "0.0284827000, 0.0301323000, 0.0342625000, 0.0436334000, 0.0664374000, 0.1250716000, 0.2768846000", \ - "0.0281383000, 0.0297684000, 0.0338437000, 0.0431836000, 0.0659411000, 0.1246404000, 0.2765367000", \ - "0.0283821000, 0.0299918000, 0.0340200000, 0.0432776000, 0.0660414000, 0.1247585000, 0.2765154000", \ - "0.0311609000, 0.0324511000, 0.0358147000, 0.0444121000, 0.0670367000, 0.1258951000, 0.2779032000", \ - "0.0361366000, 0.0374196000, 0.0407925000, 0.0495535000, 0.0720248000, 0.1306896000, 0.2822853000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0162566000, 0.0153929000, 0.0129177000, 0.0056040000, -0.015837100, -0.074641000, -0.228940500", \ - "0.0158676000, 0.0149642000, 0.0125306000, 0.0052007000, -0.016170900, -0.074995700, -0.229268700", \ - "0.0154597000, 0.0145597000, 0.0121295000, 0.0048024000, -0.016544500, -0.075345200, -0.229613000", \ - "0.0151611000, 0.0142289000, 0.0117766000, 0.0044972000, -0.016859100, -0.075596200, -0.229865400", \ - "0.0152034000, 0.0142741000, 0.0117570000, 0.0044187000, -0.016885800, -0.075588400, -0.229834300", \ - "0.0174018000, 0.0160667000, 0.0126612000, 0.0051251000, -0.016063200, -0.074739000, -0.228966400", \ - "0.0227336000, 0.0213089000, 0.0178215000, 0.0089756000, -0.013846400, -0.072503600, -0.226718800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013003870, 0.0033820130, 0.0087958540, 0.0228760300, 0.0594953800, 0.1547341000"); - values("0.0086759000, 0.0101482000, 0.0138119000, 0.0226716000, 0.0450893000, 0.1035801000, 0.2563845000", \ - "0.0084132000, 0.0098720000, 0.0135584000, 0.0224022000, 0.0448927000, 0.1034934000, 0.2564351000", \ - "0.0080143000, 0.0094943000, 0.0131515000, 0.0220532000, 0.0444989000, 0.1036447000, 0.2557324000", \ - "0.0075967000, 0.0090595000, 0.0127045000, 0.0216402000, 0.0441783000, 0.1033533000, 0.2538316000", \ - "0.0075079000, 0.0089767000, 0.0126159000, 0.0214970000, 0.0440888000, 0.1027241000, 0.2560350000", \ - "0.0086820000, 0.0099803000, 0.0133852000, 0.0219070000, 0.0446046000, 0.1028740000, 0.2561718000", \ - "0.0112441000, 0.0125466000, 0.0158718000, 0.0245908000, 0.0472094000, 0.1058796000, 0.2569713000"); - } - } - max_capacitance : 0.1547340000; - max_transition : 1.5036540000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.3261835000, 0.3379711000, 0.3612459000, 0.4034195000, 0.4796788000, 0.6284753000, 0.9590287000", \ - "0.3307269000, 0.3426612000, 0.3660212000, 0.4079745000, 0.4845269000, 0.6331610000, 0.9634723000", \ - "0.3423403000, 0.3540429000, 0.3772026000, 0.4192545000, 0.4957252000, 0.6444152000, 0.9745602000", \ - "0.3685454000, 0.3802096000, 0.4034034000, 0.4455202000, 0.5219338000, 0.6706289000, 1.0008601000", \ - "0.4152000000, 0.4272249000, 0.4503742000, 0.4924340000, 0.5689020000, 0.7176121000, 1.0477648000", \ - "0.4815172000, 0.4933116000, 0.5164830000, 0.5584857000, 0.6348441000, 0.7837644000, 1.1142207000", \ - "0.5551247000, 0.5669721000, 0.5903118000, 0.6323914000, 0.7087622000, 0.8577275000, 1.1883748000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.3115044000, 0.3218365000, 0.3436880000, 0.3894458000, 0.4902975000, 0.7388155000, 1.3798774000", \ - "0.3165611000, 0.3269043000, 0.3487182000, 0.3944577000, 0.4952838000, 0.7434985000, 1.3855956000", \ - "0.3292220000, 0.3395362000, 0.3614226000, 0.4071878000, 0.5080553000, 0.7566210000, 1.3980772000", \ - "0.3609895000, 0.3713050000, 0.3931878000, 0.4389525000, 0.5398191000, 0.7883841000, 1.4298595000", \ - "0.4352933000, 0.4455956000, 0.4674524000, 0.5131923000, 0.6140100000, 0.8621862000, 1.5083254000", \ - "0.5780242000, 0.5883164000, 0.6104151000, 0.6561517000, 0.7570458000, 1.0051259000, 1.6482028000", \ - "0.8122127000, 0.8226784000, 0.8450377000, 0.8912990000, 0.9926828000, 1.2406075000, 1.8825872000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0542338000, 0.0600230000, 0.0718920000, 0.0999085000, 0.1629811000, 0.3160339000, 0.7173621000", \ - "0.0545346000, 0.0598307000, 0.0718938000, 0.0991476000, 0.1633364000, 0.3154970000, 0.7182481000", \ - "0.0537859000, 0.0600063000, 0.0718494000, 0.0991359000, 0.1632429000, 0.3153069000, 0.7170579000", \ - "0.0537775000, 0.0600484000, 0.0718191000, 0.0991836000, 0.1631729000, 0.3149573000, 0.7165845000", \ - "0.0546942000, 0.0599736000, 0.0718505000, 0.0991672000, 0.1632284000, 0.3152679000, 0.7171179000", \ - "0.0544671000, 0.0602820000, 0.0718572000, 0.0993176000, 0.1637566000, 0.3153303000, 0.7176534000", \ - "0.0544804000, 0.0602923000, 0.0724570000, 0.1006649000, 0.1639641000, 0.3157724000, 0.7153922000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0357205000, 0.0445002000, 0.0648434000, 0.1138316000, 0.2407210000, 0.5862610000, 1.5011440000", \ - "0.0356122000, 0.0444721000, 0.0649082000, 0.1136006000, 0.2406850000, 0.5844960000, 1.5023417000", \ - "0.0357383000, 0.0444380000, 0.0648206000, 0.1138514000, 0.2408312000, 0.5863026000, 1.5006593000", \ - "0.0357343000, 0.0444443000, 0.0648090000, 0.1138453000, 0.2408187000, 0.5862844000, 1.5005942000", \ - "0.0356105000, 0.0444611000, 0.0649165000, 0.1136144000, 0.2407541000, 0.5847506000, 1.5023681000", \ - "0.0359282000, 0.0448268000, 0.0652982000, 0.1141103000, 0.2412589000, 0.5854263000, 1.4959882000", \ - "0.0367898000, 0.0453782000, 0.0661105000, 0.1147859000, 0.2417085000, 0.5835883000, 1.4962831000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.3010308000, 0.3130432000, 0.3362529000, 0.3777922000, 0.4527165000, 0.5996342000, 0.9290140000", \ - "0.3062965000, 0.3183170000, 0.3415490000, 0.3831014000, 0.4580094000, 0.6049174000, 0.9340565000", \ - "0.3189746000, 0.3309386000, 0.3542139000, 0.3957547000, 0.4706811000, 0.6176104000, 0.9470179000", \ - "0.3503779000, 0.3623440000, 0.3856533000, 0.4271129000, 0.5018685000, 0.6490447000, 0.9782559000", \ - "0.4239405000, 0.4359584000, 0.4592329000, 0.5007463000, 0.5757519000, 0.7228007000, 1.0521087000", \ - "0.5819835000, 0.5944183000, 0.6183499000, 0.6605400000, 0.7359050000, 0.8832857000, 1.2129326000", \ - "0.8539089000, 0.8691804000, 0.8974056000, 0.9447686000, 1.0263703000, 1.1792273000, 1.5116024000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.1713912000, 0.1808556000, 0.2014893000, 0.2455991000, 0.3456340000, 0.5935882000, 1.2353952000", \ - "0.1759714000, 0.1854794000, 0.2061168000, 0.2501341000, 0.3502711000, 0.5983293000, 1.2414502000", \ - "0.1870891000, 0.1965313000, 0.2171778000, 0.2611891000, 0.3613320000, 0.6093848000, 1.2529348000", \ - "0.2116741000, 0.2211414000, 0.2418065000, 0.2858294000, 0.3859585000, 0.6340404000, 1.2775401000", \ - "0.2605282000, 0.2700626000, 0.2907682000, 0.3348899000, 0.4347396000, 0.6827849000, 1.3252442000", \ - "0.3358223000, 0.3462838000, 0.3684667000, 0.4146267000, 0.5159297000, 0.7644931000, 1.4075215000", \ - "0.4299489000, 0.4428375000, 0.4693578000, 0.5210288000, 0.6265114000, 0.8755187000, 1.5175750000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0573964000, 0.0622161000, 0.0730388000, 0.0983945000, 0.1612061000, 0.3128546000, 0.7160206000", \ - "0.0574032000, 0.0622212000, 0.0730363000, 0.0986097000, 0.1613770000, 0.3122423000, 0.7154926000", \ - "0.0574619000, 0.0622457000, 0.0731048000, 0.0984579000, 0.1610885000, 0.3132190000, 0.7155824000", \ - "0.0576043000, 0.0621399000, 0.0736712000, 0.0998748000, 0.1604157000, 0.3123721000, 0.7168019000", \ - "0.0579651000, 0.0626917000, 0.0737987000, 0.0998559000, 0.1607792000, 0.3125068000, 0.7172195000", \ - "0.0644800000, 0.0684790000, 0.0775696000, 0.1017133000, 0.1626778000, 0.3132968000, 0.7145278000", \ - "0.0957121000, 0.0955556000, 0.0987417000, 0.1173150000, 0.1737483000, 0.3207603000, 0.7189226000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0323532000, 0.0407385000, 0.0609480000, 0.1104879000, 0.2389486000, 0.5842683000, 1.5009735000", \ - "0.0322799000, 0.0409053000, 0.0610971000, 0.1103479000, 0.2390031000, 0.5843143000, 1.5036355000", \ - "0.0323039000, 0.0408802000, 0.0611055000, 0.1104492000, 0.2390893000, 0.5847696000, 1.4991892000", \ - "0.0323037000, 0.0409078000, 0.0610954000, 0.1104765000, 0.2391286000, 0.5847532000, 1.4987038000", \ - "0.0329224000, 0.0414244000, 0.0615916000, 0.1105523000, 0.2392730000, 0.5845970000, 1.4935486000", \ - "0.0370566000, 0.0456170000, 0.0661741000, 0.1147900000, 0.2412074000, 0.5846771000, 1.4975455000", \ - "0.0472700000, 0.0570990000, 0.0786210000, 0.1260813000, 0.2479074000, 0.5875371000, 1.4940702000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.2466925000, 0.2583875000, 0.2807929000, 0.3220912000, 0.3971645000, 0.5448116000, 0.8744568000", \ - "0.2500810000, 0.2617458000, 0.2841834000, 0.3254583000, 0.4005822000, 0.5481958000, 0.8778716000", \ - "0.2584186000, 0.2700213000, 0.2925382000, 0.3338401000, 0.4088412000, 0.5565191000, 0.8861158000", \ - "0.2786225000, 0.2902189000, 0.3127343000, 0.3539869000, 0.4290262000, 0.5766342000, 0.9062690000", \ - "0.3342392000, 0.3453615000, 0.3679315000, 0.4089668000, 0.4837974000, 0.6314766000, 0.9611415000", \ - "0.4002363000, 0.4115068000, 0.4338399000, 0.4745361000, 0.5491068000, 0.6961999000, 1.0255381000", \ - "0.4569473000, 0.4683519000, 0.4906715000, 0.5315050000, 0.6065866000, 0.7539294000, 1.0824422000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.2218311000, 0.2321033000, 0.2539605000, 0.2996506000, 0.4003775000, 0.6485347000, 1.2937608000", \ - "0.2253162000, 0.2355612000, 0.2574174000, 0.3030898000, 0.4037886000, 0.6516505000, 1.2956780000", \ - "0.2369061000, 0.2472220000, 0.2690485000, 0.3147377000, 0.4154792000, 0.6639695000, 1.3063312000", \ - "0.2666467000, 0.2769835000, 0.2987589000, 0.3444172000, 0.4451391000, 0.6934210000, 1.3352081000", \ - "0.3264981000, 0.3368412000, 0.3586860000, 0.4043995000, 0.5051697000, 0.7536227000, 1.3959903000", \ - "0.4135823000, 0.4237809000, 0.4457534000, 0.4912677000, 0.5916666000, 0.8406221000, 1.4853824000", \ - "0.5417005000, 0.5520858000, 0.5741185000, 0.6200647000, 0.7210880000, 0.9691781000, 1.6091559000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0523177000, 0.0579534000, 0.0699598000, 0.0978952000, 0.1616606000, 0.3128279000, 0.7168944000", \ - "0.0523866000, 0.0579630000, 0.0700416000, 0.0980632000, 0.1617649000, 0.3131484000, 0.7168611000", \ - "0.0522063000, 0.0578483000, 0.0698888000, 0.0974530000, 0.1614629000, 0.3130371000, 0.7168188000", \ - "0.0523353000, 0.0578711000, 0.0698069000, 0.0978986000, 0.1616567000, 0.3127889000, 0.7168908000", \ - "0.0508389000, 0.0564620000, 0.0690935000, 0.0970368000, 0.1612519000, 0.3129540000, 0.7168400000", \ - "0.0507952000, 0.0564594000, 0.0689960000, 0.0975065000, 0.1592496000, 0.3124371000, 0.7155263000", \ - "0.0509003000, 0.0565780000, 0.0691430000, 0.0979884000, 0.1615311000, 0.3124179000, 0.7130409000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0354751000, 0.0444849000, 0.0648845000, 0.1136864000, 0.2405596000, 0.5844428000, 1.5025124000", \ - "0.0355684000, 0.0445132000, 0.0649738000, 0.1135913000, 0.2410732000, 0.5858413000, 1.4961623000", \ - "0.0356302000, 0.0444242000, 0.0647551000, 0.1137232000, 0.2406212000, 0.5860748000, 1.4997684000", \ - "0.0355383000, 0.0444331000, 0.0647490000, 0.1135770000, 0.2405171000, 0.5851979000, 1.5017851000", \ - "0.0355785000, 0.0445036000, 0.0647713000, 0.1137414000, 0.2406915000, 0.5862360000, 1.4996748000", \ - "0.0357510000, 0.0446271000, 0.0649612000, 0.1136361000, 0.2404939000, 0.5862476000, 1.5014779000", \ - "0.0362103000, 0.0448448000, 0.0654061000, 0.1144155000, 0.2412387000, 0.5830027000, 1.4932497000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.2791208000, 0.2908989000, 0.3143019000, 0.3561903000, 0.4327238000, 0.5813334000, 0.9117153000", \ - "0.2826854000, 0.2944339000, 0.3175631000, 0.3596520000, 0.4359818000, 0.5847798000, 0.9151782000", \ - "0.2936304000, 0.3053827000, 0.3285254000, 0.3706050000, 0.4469730000, 0.5957651000, 0.9260953000", \ - "0.3221744000, 0.3338759000, 0.3571000000, 0.3991214000, 0.4755603000, 0.6242976000, 0.9548228000", \ - "0.3862365000, 0.3980231000, 0.4212425000, 0.4632351000, 0.5394674000, 0.6883467000, 1.0189800000", \ - "0.5205699000, 0.5328747000, 0.5571908000, 0.6001279000, 0.6776404000, 0.8270929000, 1.1579261000", \ - "0.7315143000, 0.7487215000, 0.7807275000, 0.8349450000, 0.9242067000, 1.0850700000, 1.4218280000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.1489641000, 0.1583136000, 0.1788415000, 0.2226026000, 0.3218752000, 0.5696646000, 1.2111064000", \ - "0.1520418000, 0.1614059000, 0.1818700000, 0.2256885000, 0.3250365000, 0.5722849000, 1.2149795000", \ - "0.1613141000, 0.1707906000, 0.1912045000, 0.2349524000, 0.3343827000, 0.5819437000, 1.2228245000", \ - "0.1852507000, 0.1946373000, 0.2150218000, 0.2587263000, 0.3579817000, 0.6055020000, 1.2456024000", \ - "0.2333437000, 0.2429486000, 0.2636967000, 0.3076561000, 0.4069530000, 0.6546810000, 1.2966429000", \ - "0.3034201000, 0.3142536000, 0.3370419000, 0.3828566000, 0.4834672000, 0.7318777000, 1.3727914000", \ - "0.3794501000, 0.3937811000, 0.4219521000, 0.4736801000, 0.5771938000, 0.8255475000, 1.4673714000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0541198000, 0.0592030000, 0.0719207000, 0.0989857000, 0.1633032000, 0.3154622000, 0.7187048000", \ - "0.0540638000, 0.0596959000, 0.0719470000, 0.1004474000, 0.1631337000, 0.3155760000, 0.7188779000", \ - "0.0540104000, 0.0595856000, 0.0720386000, 0.1002795000, 0.1633284000, 0.3158991000, 0.7185120000", \ - "0.0541045000, 0.0596189000, 0.0718048000, 0.0991548000, 0.1633778000, 0.3156855000, 0.7187571000", \ - "0.0536191000, 0.0594748000, 0.0717747000, 0.1001215000, 0.1637357000, 0.3156688000, 0.7172059000", \ - "0.0609625000, 0.0667291000, 0.0775889000, 0.1028818000, 0.1664539000, 0.3159577000, 0.7177272000", \ - "0.0939201000, 0.0998489000, 0.1099872000, 0.1323971000, 0.1899664000, 0.3357765000, 0.7255596000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0321309000, 0.0404976000, 0.0605177000, 0.1095395000, 0.2385591000, 0.5850882000, 1.4997632000", \ - "0.0320305000, 0.0405515000, 0.0604004000, 0.1096937000, 0.2383498000, 0.5850510000, 1.4983530000", \ - "0.0319760000, 0.0405301000, 0.0604879000, 0.1094962000, 0.2384663000, 0.5838859000, 1.4936452000", \ - "0.0320184000, 0.0405037000, 0.0603467000, 0.1096893000, 0.2384374000, 0.5845224000, 1.4954223000", \ - "0.0332620000, 0.0417103000, 0.0616627000, 0.1102678000, 0.2386515000, 0.5840608000, 1.4944543000", \ - "0.0395679000, 0.0484634000, 0.0675753000, 0.1147094000, 0.2409792000, 0.5849459000, 1.4993166000", \ - "0.0538995000, 0.0635856000, 0.0836200000, 0.1270253000, 0.2460139000, 0.5872421000, 1.4944960000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.1580573000, 0.1690048000, 0.1912026000, 0.2318951000, 0.3065477000, 0.4537066000, 0.7832456000", \ - "0.1628465000, 0.1740525000, 0.1960769000, 0.2367342000, 0.3116348000, 0.4586410000, 0.7881081000", \ - "0.1725076000, 0.1836503000, 0.2057304000, 0.2464313000, 0.3212943000, 0.4684072000, 0.7976073000", \ - "0.1931762000, 0.2041497000, 0.2258636000, 0.2661998000, 0.3404717000, 0.4878540000, 0.8170350000", \ - "0.2378016000, 0.2471855000, 0.2668872000, 0.3053952000, 0.3784175000, 0.5249239000, 0.8544059000", \ - "0.2810715000, 0.2905546000, 0.3101142000, 0.3477683000, 0.4196016000, 0.5639045000, 0.8923096000", \ - "0.3154076000, 0.3246721000, 0.3441051000, 0.3817892000, 0.4536368000, 0.5990162000, 0.9259281000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.1476253000, 0.1574839000, 0.1789787000, 0.2242681000, 0.3248556000, 0.5736931000, 1.2164523000", \ - "0.1523000000, 0.1622958000, 0.1837019000, 0.2288961000, 0.3295476000, 0.5782297000, 1.2198496000", \ - "0.1652422000, 0.1751617000, 0.1966502000, 0.2418196000, 0.3424356000, 0.5906424000, 1.2335095000", \ - "0.1963681000, 0.2063578000, 0.2278169000, 0.2730369000, 0.3735958000, 0.6222676000, 1.2635608000", \ - "0.2600115000, 0.2698308000, 0.2911875000, 0.3363216000, 0.4368472000, 0.6846273000, 1.3322883000", \ - "0.3595338000, 0.3693363000, 0.3907282000, 0.4357313000, 0.5357497000, 0.7838289000, 1.4283805000", \ - "0.5116381000, 0.5213118000, 0.5425546000, 0.5877699000, 0.6887365000, 0.9367990000, 1.5762605000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0471118000, 0.0535748000, 0.0661793000, 0.0957683000, 0.1601068000, 0.3137060000, 0.7149007000", \ - "0.0470881000, 0.0532657000, 0.0663821000, 0.0944310000, 0.1599784000, 0.3127373000, 0.7181813000", \ - "0.0468180000, 0.0528817000, 0.0662736000, 0.0944373000, 0.1597865000, 0.3123711000, 0.7155872000", \ - "0.0445469000, 0.0509957000, 0.0645190000, 0.0948491000, 0.1592270000, 0.3119834000, 0.7155861000", \ - "0.0369710000, 0.0440198000, 0.0588110000, 0.0896384000, 0.1572554000, 0.3116738000, 0.7153069000", \ - "0.0367903000, 0.0430020000, 0.0580179000, 0.0878001000, 0.1547852000, 0.3069575000, 0.7134404000", \ - "0.0356895000, 0.0424433000, 0.0572074000, 0.0879534000, 0.1547673000, 0.3091618000, 0.7074629000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0338544000, 0.0427004000, 0.0633103000, 0.1127223000, 0.2402924000, 0.5863511000, 1.4954104000", \ - "0.0338301000, 0.0427410000, 0.0632522000, 0.1126487000, 0.2397939000, 0.5865351000, 1.4964531000", \ - "0.0339845000, 0.0426326000, 0.0634160000, 0.1126763000, 0.2402204000, 0.5862935000, 1.4948852000", \ - "0.0338062000, 0.0427807000, 0.0632099000, 0.1125247000, 0.2399345000, 0.5865415000, 1.4958496000", \ - "0.0333752000, 0.0423500000, 0.0633170000, 0.1125657000, 0.2404061000, 0.5862137000, 1.5036542000", \ - "0.0334124000, 0.0423452000, 0.0628806000, 0.1125864000, 0.2395793000, 0.5866728000, 1.5026712000", \ - "0.0343621000, 0.0429598000, 0.0636887000, 0.1133564000, 0.2406231000, 0.5843537000, 1.4950884000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.1368187000, 0.1465362000, 0.1664877000, 0.2046736000, 0.2776180000, 0.4245586000, 0.7545418000", \ - "0.1397194000, 0.1493785000, 0.1692243000, 0.2074637000, 0.2801316000, 0.4273062000, 0.7568836000", \ - "0.1489735000, 0.1584707000, 0.1781087000, 0.2161829000, 0.2886932000, 0.4358057000, 0.7655563000", \ - "0.1748783000, 0.1841732000, 0.2033171000, 0.2408095000, 0.3132973000, 0.4600378000, 0.7897737000", \ - "0.2401062000, 0.2490047000, 0.2673294000, 0.3037296000, 0.3753696000, 0.5215821000, 0.8513057000", \ - "0.3500013000, 0.3608720000, 0.3824462000, 0.4214099000, 0.4939916000, 0.6421731000, 0.9725429000", \ - "0.5157704000, 0.5292586000, 0.5565745000, 0.6043213000, 0.6839028000, 0.8334006000, 1.1682705000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0837924000, 0.0930334000, 0.1130427000, 0.1556035000, 0.2529819000, 0.4997183000, 1.1396515000", \ - "0.0878570000, 0.0970905000, 0.1170913000, 0.1596985000, 0.2572875000, 0.5032753000, 1.1433151000", \ - "0.0980591000, 0.1072524000, 0.1272294000, 0.1698849000, 0.2673803000, 0.5144163000, 1.1546497000", \ - "0.1215980000, 0.1306639000, 0.1504938000, 0.1932389000, 0.2910387000, 0.5385992000, 1.1824144000", \ - "0.1577993000, 0.1670878000, 0.1871415000, 0.2307567000, 0.3299450000, 0.5768260000, 1.2205451000", \ - "0.2010987000, 0.2119829000, 0.2338179000, 0.2779799000, 0.3776359000, 0.6266208000, 1.2706349000", \ - "0.2339178000, 0.2482148000, 0.2761413000, 0.3258350000, 0.4267932000, 0.6753099000, 1.3174777000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0367162000, 0.0442326000, 0.0588435000, 0.0905759000, 0.1578446000, 0.3140854000, 0.7154845000", \ - "0.0367445000, 0.0434211000, 0.0593308000, 0.0904492000, 0.1584110000, 0.3133028000, 0.7168906000", \ - "0.0361458000, 0.0428850000, 0.0586482000, 0.0898330000, 0.1581925000, 0.3130081000, 0.7183272000", \ - "0.0345492000, 0.0414962000, 0.0568680000, 0.0886150000, 0.1567971000, 0.3117062000, 0.7169426000", \ - "0.0347491000, 0.0412001000, 0.0552317000, 0.0866930000, 0.1547510000, 0.3124080000, 0.7182722000", \ - "0.0464445000, 0.0531221000, 0.0662068000, 0.0948081000, 0.1582302000, 0.3148418000, 0.7191073000", \ - "0.0619415000, 0.0704963000, 0.0870198000, 0.1148922000, 0.1728151000, 0.3213176000, 0.7267671000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013003900, 0.0033820100, 0.0087958500, 0.0228760000, 0.0594954000, 0.1547340000"); - values("0.0308152000, 0.0391682000, 0.0593102000, 0.1082348000, 0.2373747000, 0.5860634000, 1.4983426000", \ - "0.0307385000, 0.0392562000, 0.0593786000, 0.1082674000, 0.2373620000, 0.5841683000, 1.4997030000", \ - "0.0306158000, 0.0391495000, 0.0591286000, 0.1081560000, 0.2371082000, 0.5861107000, 1.4955263000", \ - "0.0304765000, 0.0389730000, 0.0591867000, 0.1083528000, 0.2370707000, 0.5856046000, 1.4964220000", \ - "0.0332875000, 0.0410562000, 0.0607879000, 0.1102087000, 0.2382441000, 0.5852317000, 1.4982318000", \ - "0.0424207000, 0.0492486000, 0.0667452000, 0.1128277000, 0.2413090000, 0.5861547000, 1.4967800000", \ - "0.0573550000, 0.0665055000, 0.0847314000, 0.1245380000, 0.2444999000, 0.5894470000, 1.4946278000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor3_2") { - leakage_power () { - value : 0.0133280000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0087148000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0201446000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0224635000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0085349000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0108525000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0222772000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0176658000; - when : "A&B&!C"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__xnor3"; - cell_leakage_power : 0.0154976600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022970000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025830000; - } - pin ("B") { - capacitance : 0.0052800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051240000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054360000; - } - pin ("C") { - capacitance : 0.0034750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033530000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035970000; - } - pin ("X") { - direction : "output"; - function : "(!A&!B&!C) | (A&B&!C) | (A&!B&C) | (!A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0500241000, 0.0482574000, 0.0440443000, 0.0328728000, -0.001874800, -0.109827500, -0.429364500", \ - "0.0498658000, 0.0481125000, 0.0439126000, 0.0327049000, -0.002031800, -0.109997600, -0.429526200", \ - "0.0496624000, 0.0479065000, 0.0436959000, 0.0324869000, -0.002239600, -0.110212000, -0.429738900", \ - "0.0495101000, 0.0477533000, 0.0435401000, 0.0323255000, -0.002416300, -0.110387800, -0.429906700", \ - "0.0493840000, 0.0476108000, 0.0434014000, 0.0321894000, -0.002636700, -0.110569100, -0.430043900", \ - "0.0500081000, 0.0482320000, 0.0439306000, 0.0325327000, -0.002565100, -0.110551200, -0.430017900", \ - "0.0556685000, 0.0536525000, 0.0483282000, 0.0342840000, -0.001273900, -0.109489200, -0.429013300"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0437739000, 0.0455612000, 0.0508650000, 0.0654352000, 0.1037296000, 0.2128807000, 0.5303564000", \ - "0.0437395000, 0.0454555000, 0.0507575000, 0.0653510000, 0.1036240000, 0.2127027000, 0.5298062000", \ - "0.0435181000, 0.0453093000, 0.0506368000, 0.0652142000, 0.1034306000, 0.2124186000, 0.5296143000", \ - "0.0431026000, 0.0450003000, 0.0503710000, 0.0649393000, 0.1031512000, 0.2121023000, 0.5293744000", \ - "0.0430040000, 0.0448506000, 0.0502183000, 0.0648311000, 0.1029597000, 0.2119164000, 0.5287036000", \ - "0.0438039000, 0.0453193000, 0.0501621000, 0.0647440000, 0.1026867000, 0.2116697000, 0.5284871000", \ - "0.0471045000, 0.0486554000, 0.0532176000, 0.0662370000, 0.1038619000, 0.2129996000, 0.5284775000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0462755000, 0.0445349000, 0.0403607000, 0.0290777000, -0.005913900, -0.114025100, -0.433635700", \ - "0.0461058000, 0.0443860000, 0.0402330000, 0.0289195000, -0.006072200, -0.114161200, -0.433772200", \ - "0.0459793000, 0.0442391000, 0.0400891000, 0.0287746000, -0.006216300, -0.114295500, -0.433861000", \ - "0.0460125000, 0.0443002000, 0.0401462000, 0.0288276000, -0.006190700, -0.114253200, -0.433816100", \ - "0.0462042000, 0.0444682000, 0.0402796000, 0.0289750000, -0.006046300, -0.114144400, -0.433675300", \ - "0.0479702000, 0.0462005000, 0.0419418000, 0.0304791000, -0.004791200, -0.112894900, -0.432402900", \ - "0.0567814000, 0.0547597000, 0.0494338000, 0.0355313000, -0.001672600, -0.109322800, -0.428892900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0342599000, 0.0359300000, 0.0410015000, 0.0551969000, 0.0933695000, 0.2025022000, 0.5198246000", \ - "0.0338853000, 0.0355651000, 0.0406197000, 0.0547988000, 0.0929517000, 0.2020098000, 0.5186809000", \ - "0.0333653000, 0.0350750000, 0.0401570000, 0.0543118000, 0.0925282000, 0.2014447000, 0.5184197000", \ - "0.0330593000, 0.0347275000, 0.0397885000, 0.0539208000, 0.0920344000, 0.2012010000, 0.5184260000", \ - "0.0332970000, 0.0349919000, 0.0400289000, 0.0540290000, 0.0921246000, 0.2013054000, 0.5181770000", \ - "0.0359700000, 0.0374712000, 0.0418222000, 0.0552057000, 0.0930420000, 0.2022384000, 0.5187748000", \ - "0.0417342000, 0.0432047000, 0.0476042000, 0.0607723000, 0.0982941000, 0.2071003000, 0.5221648000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0198123000, 0.0182337000, 0.0143847000, 0.0032951000, -0.031955800, -0.140516200, -0.460351500", \ - "0.0194726000, 0.0179041000, 0.0140403000, 0.0029525000, -0.032263800, -0.140813800, -0.460635900", \ - "0.0190548000, 0.0174522000, 0.0136027000, 0.0025572000, -0.032609700, -0.141125700, -0.460960300", \ - "0.0186217000, 0.0170538000, 0.0132094000, 0.0021395000, -0.033023700, -0.141520600, -0.461322400", \ - "0.0184023000, 0.0168209000, 0.0129834000, 0.0018726000, -0.033230900, -0.141648200, -0.461418200", \ - "0.0195733000, 0.0178774000, 0.0138447000, 0.0026617000, -0.032587100, -0.140981500, -0.460709400", \ - "0.0283151000, 0.0264423000, 0.0213454000, 0.0078517000, -0.030174100, -0.138922800, -0.458627900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014530770, 0.0042228650, 0.0122722900, 0.0356651700, 0.1036485000, 0.3012184000"); - values("0.0133104000, 0.0150202000, 0.0199501000, 0.0336619000, 0.0713766000, 0.1800966000, 0.4970275000", \ - "0.0130991000, 0.0148025000, 0.0197420000, 0.0334619000, 0.0712290000, 0.1800455000, 0.4968746000", \ - "0.0127869000, 0.0144597000, 0.0194001000, 0.0331305000, 0.0709875000, 0.1796213000, 0.4989472000", \ - "0.0124623000, 0.0141232000, 0.0190048000, 0.0326977000, 0.0705319000, 0.1794105000, 0.4963228000", \ - "0.0124550000, 0.0140607000, 0.0188179000, 0.0324874000, 0.0703191000, 0.1791654000, 0.4962867000", \ - "0.0140361000, 0.0155303000, 0.0199765000, 0.0327687000, 0.0705842000, 0.1791799000, 0.4969975000", \ - "0.0167541000, 0.0181715000, 0.0224398000, 0.0354138000, 0.0730596000, 0.1820164000, 0.4964432000"); - } - } - max_capacitance : 0.3012180000; - max_transition : 1.5043300000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.3523093000, 0.3623482000, 0.3846114000, 0.4275305000, 0.5052522000, 0.6575858000, 1.0053037000", \ - "0.3567646000, 0.3667829000, 0.3893462000, 0.4323748000, 0.5099038000, 0.6621940000, 1.0100762000", \ - "0.3675919000, 0.3781089000, 0.4005554000, 0.4435919000, 0.5211607000, 0.6734422000, 1.0213332000", \ - "0.3939136000, 0.4044279000, 0.4268106000, 0.4698250000, 0.5474347000, 0.6997554000, 1.0475549000", \ - "0.4409992000, 0.4512705000, 0.4738768000, 0.5166936000, 0.5944830000, 0.7465821000, 1.0942378000", \ - "0.5071718000, 0.5174441000, 0.5396963000, 0.5823846000, 0.6603570000, 0.8126480000, 1.1605190000", \ - "0.5801685000, 0.5907123000, 0.6130095000, 0.6559415000, 0.7336838000, 0.8861014000, 1.2337101000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.3315422000, 0.3401252000, 0.3599382000, 0.4018899000, 0.4951470000, 0.7338961000, 1.4187517000", \ - "0.3367290000, 0.3453411000, 0.3650934000, 0.4070506000, 0.5003085000, 0.7389868000, 1.4240336000", \ - "0.3492915000, 0.3578546000, 0.3776104000, 0.4195735000, 0.5128392000, 0.7514801000, 1.4369095000", \ - "0.3810712000, 0.3896341000, 0.4093890000, 0.4513520000, 0.5446177000, 0.7832574000, 1.4685203000", \ - "0.4552191000, 0.4639245000, 0.4835801000, 0.5257041000, 0.6190278000, 0.8577087000, 1.5420312000", \ - "0.5982420000, 0.6068859000, 0.6266014000, 0.6687669000, 0.7621055000, 1.0009313000, 1.6811642000", \ - "0.8329123000, 0.8416372000, 0.8616289000, 0.9042384000, 0.9980399000, 1.2367211000, 1.9188033000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0614043000, 0.0674014000, 0.0769612000, 0.0997473000, 0.1557016000, 0.2997198000, 0.7085620000", \ - "0.0623194000, 0.0663950000, 0.0768983000, 0.1003048000, 0.1562146000, 0.2994122000, 0.7071504000", \ - "0.0621920000, 0.0668132000, 0.0768779000, 0.1002361000, 0.1567313000, 0.2994288000, 0.7067084000", \ - "0.0622857000, 0.0670050000, 0.0768441000, 0.1001406000, 0.1557975000, 0.2995747000, 0.7084299000", \ - "0.0614504000, 0.0663022000, 0.0769598000, 0.1010100000, 0.1564215000, 0.2996030000, 0.7077001000", \ - "0.0615150000, 0.0659242000, 0.0765445000, 0.0998651000, 0.1561562000, 0.2997368000, 0.7082766000", \ - "0.0625530000, 0.0674789000, 0.0770400000, 0.1001469000, 0.1559890000, 0.2995474000, 0.7057735000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0339009000, 0.0407807000, 0.0568618000, 0.0961659000, 0.2036144000, 0.5271646000, 1.5033230000", \ - "0.0339063000, 0.0404239000, 0.0568278000, 0.0961891000, 0.2036570000, 0.5271287000, 1.5034938000", \ - "0.0338995000, 0.0404429000, 0.0568270000, 0.0962003000, 0.2036771000, 0.5273446000, 1.5034450000", \ - "0.0338962000, 0.0404411000, 0.0568249000, 0.0961996000, 0.2036769000, 0.5273544000, 1.5034051000", \ - "0.0340536000, 0.0406916000, 0.0569412000, 0.0961197000, 0.2035563000, 0.5280255000, 1.5021531000", \ - "0.0341263000, 0.0408033000, 0.0571722000, 0.0962498000, 0.2037809000, 0.5274792000, 1.5016663000", \ - "0.0348655000, 0.0415874000, 0.0577596000, 0.0971366000, 0.2044866000, 0.5275072000, 1.5009066000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.3245511000, 0.3348767000, 0.3571704000, 0.3991133000, 0.4748906000, 0.6240311000, 0.9692218000", \ - "0.3298339000, 0.3401165000, 0.3624006000, 0.4043695000, 0.4801903000, 0.6293374000, 0.9743635000", \ - "0.3425639000, 0.3528371000, 0.3751203000, 0.4170970000, 0.4929387000, 0.6420687000, 0.9870811000", \ - "0.3739400000, 0.3842102000, 0.4064895000, 0.4484573000, 0.5243065000, 0.6734526000, 1.0184692000", \ - "0.4475077000, 0.4578623000, 0.4802290000, 0.5221486000, 0.5979532000, 0.7472136000, 1.0923236000", \ - "0.6059184000, 0.6165225000, 0.6394189000, 0.6819946000, 0.7582301000, 0.9079408000, 1.2533694000", \ - "0.8855559000, 0.8982563000, 0.9252019000, 0.9732608000, 1.0554828000, 1.2106842000, 1.5591026000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1876193000, 0.1954379000, 0.2136831000, 0.2532675000, 0.3440198000, 0.5811666000, 1.2612846000", \ - "0.1923323000, 0.2000591000, 0.2181748000, 0.2578965000, 0.3485835000, 0.5861397000, 1.2710237000", \ - "0.2033209000, 0.2111557000, 0.2292515000, 0.2689582000, 0.3597039000, 0.5972959000, 1.2784581000", \ - "0.2277616000, 0.2356080000, 0.2537607000, 0.2934595000, 0.3842522000, 0.6218490000, 1.3041799000", \ - "0.2764990000, 0.2843384000, 0.3025847000, 0.3422148000, 0.4329663000, 0.6705519000, 1.3568543000", \ - "0.3555395000, 0.3640668000, 0.3834787000, 0.4251495000, 0.5177262000, 0.7558160000, 1.4419735000", \ - "0.4581869000, 0.4685611000, 0.4918688000, 0.5391956000, 0.6372141000, 0.8771623000, 1.5591188000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0630548000, 0.0675661000, 0.0767474000, 0.0981804000, 0.1519117000, 0.2944840000, 0.7047570000", \ - "0.0630590000, 0.0674945000, 0.0773096000, 0.0981304000, 0.1529078000, 0.2947160000, 0.7040775000", \ - "0.0630679000, 0.0674742000, 0.0772351000, 0.0981244000, 0.1526663000, 0.2946824000, 0.7036672000", \ - "0.0631014000, 0.0675105000, 0.0772621000, 0.0981565000, 0.1526511000, 0.2946702000, 0.7037603000", \ - "0.0633826000, 0.0679059000, 0.0769839000, 0.0985199000, 0.1532655000, 0.2947979000, 0.7042275000", \ - "0.0697070000, 0.0727547000, 0.0809908000, 0.1019664000, 0.1537328000, 0.2950682000, 0.7050789000", \ - "0.1010177000, 0.1019763000, 0.1058385000, 0.1196894000, 0.1663319000, 0.3023670000, 0.7081187000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0302789000, 0.0366561000, 0.0522001000, 0.0910354000, 0.1993540000, 0.5260669000, 1.5029881000", \ - "0.0304339000, 0.0367247000, 0.0520792000, 0.0911540000, 0.1990574000, 0.5258064000, 1.5015507000", \ - "0.0304010000, 0.0366390000, 0.0520337000, 0.0910376000, 0.1993959000, 0.5259481000, 1.5014388000", \ - "0.0306221000, 0.0365168000, 0.0521262000, 0.0910433000, 0.1994604000, 0.5254021000, 1.5001572000", \ - "0.0307711000, 0.0368103000, 0.0524004000, 0.0911409000, 0.1995780000, 0.5259320000, 1.5014989000", \ - "0.0340476000, 0.0404717000, 0.0564809000, 0.0952926000, 0.2017489000, 0.5266109000, 1.5016003000", \ - "0.0438897000, 0.0503705000, 0.0684126000, 0.1071528000, 0.2105293000, 0.5284571000, 1.4936704000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2697180000, 0.2796858000, 0.3016753000, 0.3437634000, 0.4207284000, 0.5716370000, 0.9181087000", \ - "0.2731367000, 0.2830901000, 0.3051021000, 0.3472095000, 0.4241395000, 0.5750522000, 0.9215049000", \ - "0.2815367000, 0.2913262000, 0.3134572000, 0.3556068000, 0.4324445000, 0.5833871000, 0.9297366000", \ - "0.3017357000, 0.3117800000, 0.3339793000, 0.3759457000, 0.4526420000, 0.6036391000, 0.9503185000", \ - "0.3578150000, 0.3676879000, 0.3895562000, 0.4314807000, 0.5082440000, 0.6591665000, 1.0056227000", \ - "0.4319282000, 0.4416804000, 0.4632893000, 0.5048639000, 0.5808408000, 0.7315124000, 1.0783178000", \ - "0.4903947000, 0.5002457000, 0.5219944000, 0.5638097000, 0.6403633000, 0.7912364000, 1.1369213000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.2411107000, 0.2496781000, 0.2693440000, 0.3114342000, 0.4047088000, 0.6431581000, 1.3269942000", \ - "0.2446289000, 0.2531321000, 0.2728750000, 0.3148836000, 0.4081387000, 0.6464436000, 1.3295277000", \ - "0.2561759000, 0.2647821000, 0.2844853000, 0.3265013000, 0.4195624000, 0.6584535000, 1.3415570000", \ - "0.2858932000, 0.2944752000, 0.3141283000, 0.3561644000, 0.4492026000, 0.6881880000, 1.3698060000", \ - "0.3460723000, 0.3546669000, 0.3743182000, 0.4163995000, 0.5094767000, 0.7484597000, 1.4299547000", \ - "0.4329519000, 0.4415460000, 0.4613090000, 0.5032669000, 0.5960901000, 0.8350372000, 1.5191587000", \ - "0.5616968000, 0.5702995000, 0.5902646000, 0.6325058000, 0.7258453000, 0.9641585000, 1.6435210000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0591737000, 0.0639337000, 0.0751935000, 0.0984871000, 0.1548333000, 0.2980219000, 0.7058319000", \ - "0.0591864000, 0.0639510000, 0.0751874000, 0.0984617000, 0.1548490000, 0.2979724000, 0.7061208000", \ - "0.0590195000, 0.0647778000, 0.0752036000, 0.0983780000, 0.1537883000, 0.2975533000, 0.7068827000", \ - "0.0591709000, 0.0641443000, 0.0747542000, 0.0988925000, 0.1542504000, 0.2978281000, 0.7065661000", \ - "0.0586296000, 0.0632183000, 0.0740302000, 0.0979302000, 0.1535657000, 0.2978254000, 0.7064330000", \ - "0.0575768000, 0.0630533000, 0.0735882000, 0.0971408000, 0.1530697000, 0.2972334000, 0.7070520000", \ - "0.0579058000, 0.0634074000, 0.0740226000, 0.0976543000, 0.1540978000, 0.2970351000, 0.7021116000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0340145000, 0.0407076000, 0.0566602000, 0.0962034000, 0.2033649000, 0.5283533000, 1.4996699000", \ - "0.0338665000, 0.0402970000, 0.0564954000, 0.0961389000, 0.2036489000, 0.5283611000, 1.5017833000", \ - "0.0338500000, 0.0403991000, 0.0567388000, 0.0960029000, 0.2034298000, 0.5281341000, 1.5020588000", \ - "0.0341031000, 0.0403123000, 0.0566825000, 0.0959029000, 0.2032446000, 0.5283965000, 1.5041652000", \ - "0.0340389000, 0.0404536000, 0.0567784000, 0.0959357000, 0.2033611000, 0.5284064000, 1.5043295000", \ - "0.0338640000, 0.0403923000, 0.0566099000, 0.0956429000, 0.2033756000, 0.5281791000, 1.4992778000", \ - "0.0343022000, 0.0408775000, 0.0573102000, 0.0966960000, 0.2039861000, 0.5261019000, 1.4966322000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.3067609000, 0.3169965000, 0.3392513000, 0.3820658000, 0.4598617000, 0.6121917000, 0.9597790000", \ - "0.3103753000, 0.3208333000, 0.3428340000, 0.3855848000, 0.4633738000, 0.6156669000, 0.9634176000", \ - "0.3215253000, 0.3318021000, 0.3538967000, 0.3967038000, 0.4744255000, 0.6268021000, 0.9745160000", \ - "0.3502114000, 0.3604033000, 0.3825426000, 0.4253589000, 0.5032740000, 0.6554928000, 1.0032123000", \ - "0.4134134000, 0.4236504000, 0.4459306000, 0.4886385000, 0.5664468000, 0.7187911000, 1.0662707000", \ - "0.5453816000, 0.5560019000, 0.5791176000, 0.6226844000, 0.7011077000, 0.8538853000, 1.2018583000", \ - "0.7599897000, 0.7744790000, 0.8047469000, 0.8606423000, 0.9526236000, 1.1182658000, 1.4735909000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1653886000, 0.1731028000, 0.1910557000, 0.2304428000, 0.3204749000, 0.5578793000, 1.2392350000", \ - "0.1684775000, 0.1762060000, 0.1941121000, 0.2335657000, 0.3236716000, 0.5605266000, 1.2463562000", \ - "0.1777775000, 0.1854914000, 0.2035595000, 0.2428763000, 0.3330435000, 0.5701298000, 1.2524735000", \ - "0.2016840000, 0.2093849000, 0.2273121000, 0.2666423000, 0.3565758000, 0.5939895000, 1.2769908000", \ - "0.2519111000, 0.2597822000, 0.2778878000, 0.3173137000, 0.4071787000, 0.6446472000, 1.3294976000", \ - "0.3303113000, 0.3392057000, 0.3591862000, 0.4010088000, 0.4928286000, 0.7308223000, 1.4188467000", \ - "0.4230361000, 0.4341857000, 0.4595391000, 0.5082063000, 0.6050285000, 0.8440203000, 1.5248570000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0608450000, 0.0656050000, 0.0765984000, 0.1001313000, 0.1553806000, 0.2993489000, 0.7086313000", \ - "0.0607389000, 0.0664926000, 0.0767987000, 0.0999215000, 0.1558363000, 0.2998964000, 0.7085674000", \ - "0.0608536000, 0.0656395000, 0.0768232000, 0.0999966000, 0.1553641000, 0.2999619000, 0.7086051000", \ - "0.0608401000, 0.0657013000, 0.0768407000, 0.1000263000, 0.1553883000, 0.2999622000, 0.7086065000", \ - "0.0607436000, 0.0654856000, 0.0762938000, 0.1001617000, 0.1553613000, 0.2989477000, 0.7084768000", \ - "0.0681137000, 0.0720677000, 0.0817039000, 0.1044870000, 0.1576878000, 0.3006175000, 0.7073789000", \ - "0.1067091000, 0.1111309000, 0.1212497000, 0.1390964000, 0.1865364000, 0.3206295000, 0.7177007000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0301991000, 0.0363839000, 0.0515372000, 0.0904327000, 0.1983047000, 0.5262208000, 1.5021117000", \ - "0.0301470000, 0.0362484000, 0.0517215000, 0.0904199000, 0.1987093000, 0.5251429000, 1.5020946000", \ - "0.0299692000, 0.0363403000, 0.0516971000, 0.0903829000, 0.1982613000, 0.5251564000, 1.4960910000", \ - "0.0300996000, 0.0362131000, 0.0515033000, 0.0904033000, 0.1983520000, 0.5261480000, 1.5017370000", \ - "0.0310740000, 0.0371859000, 0.0524703000, 0.0909195000, 0.1983751000, 0.5257522000, 1.5026453000", \ - "0.0366624000, 0.0430247000, 0.0586117000, 0.0959633000, 0.2016878000, 0.5264251000, 1.5027106000", \ - "0.0495738000, 0.0573673000, 0.0739709000, 0.1105737000, 0.2096790000, 0.5298335000, 1.4956204000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1896428000, 0.1995963000, 0.2213252000, 0.2630601000, 0.3395018000, 0.4902135000, 0.8367494000", \ - "0.1942409000, 0.2044516000, 0.2263041000, 0.2679806000, 0.3444894000, 0.4952090000, 0.8417473000", \ - "0.2046491000, 0.2145675000, 0.2363332000, 0.2782927000, 0.3546422000, 0.5054323000, 0.8519752000", \ - "0.2256395000, 0.2357810000, 0.2575414000, 0.2989945000, 0.3753827000, 0.5260753000, 0.8726173000", \ - "0.2712897000, 0.2803406000, 0.3005313000, 0.3404673000, 0.4156786000, 0.5658110000, 0.9120544000", \ - "0.3240972000, 0.3324393000, 0.3513509000, 0.3893791000, 0.4626606000, 0.6110277000, 0.9561493000", \ - "0.3562675000, 0.3646827000, 0.3836806000, 0.4222055000, 0.4959533000, 0.6449337000, 0.9886630000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1643740000, 0.1728194000, 0.1922339000, 0.2338634000, 0.3267265000, 0.5656085000, 1.2500138000", \ - "0.1691507000, 0.1776878000, 0.1969894000, 0.2386750000, 0.3316628000, 0.5698745000, 1.2522809000", \ - "0.1822951000, 0.1908566000, 0.2102129000, 0.2518501000, 0.3447471000, 0.5835065000, 1.2691477000", \ - "0.2138488000, 0.2222766000, 0.2416496000, 0.2833852000, 0.3763636000, 0.6149226000, 1.2993507000", \ - "0.2793158000, 0.2876306000, 0.3070267000, 0.3486696000, 0.4415381000, 0.6802520000, 1.3603155000", \ - "0.3833235000, 0.3915875000, 0.4108150000, 0.4521277000, 0.5444428000, 0.7827762000, 1.4633131000", \ - "0.5434628000, 0.5517202000, 0.5709435000, 0.6124024000, 0.7053697000, 0.9430771000, 1.6223544000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0564718000, 0.0621602000, 0.0726781000, 0.0966996000, 0.1535258000, 0.2970595000, 0.7061407000", \ - "0.0565271000, 0.0614040000, 0.0725249000, 0.0967107000, 0.1534388000, 0.2970829000, 0.7062180000", \ - "0.0561574000, 0.0618065000, 0.0724742000, 0.0970638000, 0.1538511000, 0.2970414000, 0.7056437000", \ - "0.0544145000, 0.0594999000, 0.0718874000, 0.0958565000, 0.1529163000, 0.2971156000, 0.7067864000", \ - "0.0459235000, 0.0514222000, 0.0642108000, 0.0909066000, 0.1502399000, 0.2958054000, 0.7068561000", \ - "0.0439914000, 0.0488248000, 0.0616450000, 0.0876308000, 0.1469665000, 0.2922370000, 0.7057194000", \ - "0.0439447000, 0.0492504000, 0.0614342000, 0.0891299000, 0.1479297000, 0.2931259000, 0.7000536000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0328984000, 0.0396061000, 0.0554909000, 0.0950309000, 0.2029689000, 0.5281066000, 1.5032146000", \ - "0.0327447000, 0.0395380000, 0.0554999000, 0.0951870000, 0.2031175000, 0.5280506000, 1.5026825000", \ - "0.0328704000, 0.0395813000, 0.0554961000, 0.0949844000, 0.2030668000, 0.5276500000, 1.5035185000", \ - "0.0329991000, 0.0393638000, 0.0557482000, 0.0952188000, 0.2028235000, 0.5277649000, 1.5027856000", \ - "0.0325780000, 0.0393588000, 0.0553946000, 0.0949533000, 0.2030249000, 0.5271505000, 1.5003685000", \ - "0.0324732000, 0.0387508000, 0.0550144000, 0.0944353000, 0.2020432000, 0.5277835000, 1.5021584000", \ - "0.0331010000, 0.0393475000, 0.0555106000, 0.0953054000, 0.2033390000, 0.5266299000, 1.4976589000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1755232000, 0.1849844000, 0.2060358000, 0.2468581000, 0.3227004000, 0.4737676000, 0.8208383000", \ - "0.1792743000, 0.1886572000, 0.2096543000, 0.2504416000, 0.3262652000, 0.4773053000, 0.8245781000", \ - "0.1892029000, 0.1985452000, 0.2193328000, 0.2600234000, 0.3358209000, 0.4867703000, 0.8340896000", \ - "0.2151179000, 0.2242246000, 0.2448546000, 0.2851582000, 0.3606099000, 0.5115232000, 0.8587901000", \ - "0.2775159000, 0.2862601000, 0.3058256000, 0.3450002000, 0.4199557000, 0.5703651000, 0.9173524000", \ - "0.3987071000, 0.4087072000, 0.4309563000, 0.4728619000, 0.5481308000, 0.6986189000, 1.0457938000", \ - "0.5782603000, 0.5906454000, 0.6185566000, 0.6716637000, 0.7606142000, 0.9172573000, 1.2702124000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.1016313000, 0.1093972000, 0.1273612000, 0.1663908000, 0.2554486000, 0.4920044000, 1.1727231000", \ - "0.1058855000, 0.1136248000, 0.1316067000, 0.1706622000, 0.2598305000, 0.4963061000, 1.1771383000", \ - "0.1162080000, 0.1239232000, 0.1418935000, 0.1810272000, 0.2702726000, 0.5065171000, 1.1901861000", \ - "0.1405131000, 0.1482457000, 0.1660054000, 0.2049353000, 0.2941745000, 0.5308975000, 1.2120143000", \ - "0.1871093000, 0.1948797000, 0.2128502000, 0.2522917000, 0.3420160000, 0.5790444000, 1.2610659000", \ - "0.2469125000, 0.2563699000, 0.2770893000, 0.3178537000, 0.4089514000, 0.6473905000, 1.3313323000", \ - "0.3051558000, 0.3173592000, 0.3440789000, 0.3940734000, 0.4885790000, 0.7268229000, 1.4082278000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0484066000, 0.0542785000, 0.0663807000, 0.0943504000, 0.1526116000, 0.2977035000, 0.7075177000", \ - "0.0484787000, 0.0541913000, 0.0661719000, 0.0925997000, 0.1527720000, 0.2980563000, 0.7066612000", \ - "0.0476445000, 0.0533620000, 0.0662933000, 0.0927210000, 0.1520767000, 0.2980191000, 0.7081995000", \ - "0.0461550000, 0.0518603000, 0.0646849000, 0.0917674000, 0.1518626000, 0.2977738000, 0.7071193000", \ - "0.0429359000, 0.0487051000, 0.0616519000, 0.0893325000, 0.1508302000, 0.2967129000, 0.7066671000", \ - "0.0557329000, 0.0616050000, 0.0740383000, 0.0973471000, 0.1533078000, 0.2977976000, 0.7079160000", \ - "0.0747091000, 0.0826625000, 0.0982092000, 0.1265504000, 0.1768793000, 0.3108205000, 0.7157204000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014530800, 0.0042228600, 0.0122723000, 0.0356652000, 0.1036480000, 0.3012180000"); - values("0.0294812000, 0.0356998000, 0.0508994000, 0.0894631000, 0.1979377000, 0.5259589000, 1.5018133000", \ - "0.0295580000, 0.0357440000, 0.0508521000, 0.0895802000, 0.1979217000, 0.5261249000, 1.5027819000", \ - "0.0295707000, 0.0357746000, 0.0508444000, 0.0896138000, 0.1974735000, 0.5245927000, 1.5038036000", \ - "0.0291371000, 0.0352867000, 0.0507386000, 0.0893046000, 0.1978962000, 0.5261259000, 1.5015474000", \ - "0.0318486000, 0.0377089000, 0.0524114000, 0.0911428000, 0.1983879000, 0.5259685000, 1.5007136000", \ - "0.0426091000, 0.0478217000, 0.0612549000, 0.0964785000, 0.2027385000, 0.5266283000, 1.5000230000", \ - "0.0590310000, 0.0668420000, 0.0819007000, 0.1148719000, 0.2097303000, 0.5292413000, 1.4960720000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xnor3_4") { - leakage_power () { - value : 0.0144232000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0097427000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0209432000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0237861000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0093332000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0121758000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0233740000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0186936000; - when : "A&B&!C"; - } - area : 26.275200000; - cell_footprint : "sky130_fd_sc_hd__xnor3"; - cell_leakage_power : 0.0165589800; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024370000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022920000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025820000; - } - pin ("B") { - capacitance : 0.0052800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051220000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054380000; - } - pin ("C") { - capacitance : 0.0034750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033520000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035990000; - } - pin ("X") { - direction : "output"; - function : "(!A&!B&!C) | (A&B&!C) | (A&!B&C) | (!A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0606898000, 0.0583569000, 0.0516936000, 0.0337625000, -0.022204300, -0.209957200, -0.827726900", \ - "0.0605359000, 0.0582157000, 0.0515541000, 0.0336508000, -0.022313300, -0.210102600, -0.827881800", \ - "0.0602807000, 0.0580024000, 0.0513572000, 0.0334080000, -0.022534400, -0.210253600, -0.828154800", \ - "0.0602167000, 0.0578696000, 0.0512393000, 0.0332523000, -0.022655900, -0.210420600, -0.828265200", \ - "0.0600193000, 0.0577318000, 0.0510762000, 0.0331052000, -0.022929300, -0.210712800, -0.828540400", \ - "0.0609221000, 0.0585523000, 0.0518218000, 0.0337296000, -0.022727700, -0.210786600, -0.828447500", \ - "0.0647608000, 0.0622708000, 0.0548548000, 0.0362033000, -0.020832400, -0.209606500, -0.827500400"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0551138000, 0.0569371000, 0.0630155000, 0.0830100000, 0.1442240000, 0.3356521000, 0.9453924000", \ - "0.0550560000, 0.0569202000, 0.0629575000, 0.0829637000, 0.1442848000, 0.3353373000, 0.9459559000", \ - "0.0548962000, 0.0567030000, 0.0627892000, 0.0827972000, 0.1441137000, 0.3351814000, 0.9457022000", \ - "0.0546858000, 0.0563909000, 0.0624734000, 0.0826454000, 0.1437313000, 0.3348129000, 0.9486625000", \ - "0.0544128000, 0.0562937000, 0.0624005000, 0.0823921000, 0.1434444000, 0.3348480000, 0.9447339000", \ - "0.0545609000, 0.0564081000, 0.0624628000, 0.0825256000, 0.1433233000, 0.3344785000, 0.9482470000", \ - "0.0595182000, 0.0612186000, 0.0668099000, 0.0854532000, 0.1452458000, 0.3350801000, 0.9481190000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0572391000, 0.0549452000, 0.0482590000, 0.0301911000, -0.025955200, -0.214113100, -0.832103700", \ - "0.0571396000, 0.0548481000, 0.0481056000, 0.0300898000, -0.026145100, -0.214243500, -0.832325100", \ - "0.0570360000, 0.0547662000, 0.0479874000, 0.0298765000, -0.026235900, -0.214343600, -0.832400000", \ - "0.0571257000, 0.0548559000, 0.0480774000, 0.0299800000, -0.026152700, -0.214257200, -0.832308700", \ - "0.0572931000, 0.0550069000, 0.0482877000, 0.0302482000, -0.026032700, -0.214114300, -0.832164600", \ - "0.0592022000, 0.0568632000, 0.0501373000, 0.0319080000, -0.024565100, -0.212842000, -0.830789000", \ - "0.0687854000, 0.0662128000, 0.0585440000, 0.0371296000, -0.020571500, -0.209246800, -0.827449500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0450928000, 0.0467607000, 0.0528563000, 0.0728045000, 0.1338331000, 0.3248671000, 0.9378320000", \ - "0.0447155000, 0.0465207000, 0.0524694000, 0.0724157000, 0.1334299000, 0.3243451000, 0.9386045000", \ - "0.0441847000, 0.0460404000, 0.0520310000, 0.0719159000, 0.1329696000, 0.3238558000, 0.9333643000", \ - "0.0438868000, 0.0456919000, 0.0516040000, 0.0715327000, 0.1327143000, 0.3233877000, 0.9378955000", \ - "0.0441550000, 0.0459559000, 0.0519617000, 0.0718275000, 0.1327938000, 0.3234877000, 0.9371498000", \ - "0.0457945000, 0.0475394000, 0.0534672000, 0.0730640000, 0.1334701000, 0.3244709000, 0.9347790000", \ - "0.0541087000, 0.0557099000, 0.0612296000, 0.0795771000, 0.1392466000, 0.3291194000, 0.9404388000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0309139000, 0.0286628000, 0.0220689000, 0.0042922000, -0.051645100, -0.240242700, -0.858674700", \ - "0.0306769000, 0.0283600000, 0.0217922000, 0.0039717000, -0.051940000, -0.240488700, -0.858949800", \ - "0.0303066000, 0.0279932000, 0.0214318000, 0.0036575000, -0.052252900, -0.240776600, -0.859220500", \ - "0.0298562000, 0.0275718000, 0.0210376000, 0.0033061000, -0.052733300, -0.241093500, -0.859542200", \ - "0.0293132000, 0.0270831000, 0.0205176000, 0.0028588000, -0.053111600, -0.241394600, -0.859769200", \ - "0.0305074000, 0.0281538000, 0.0215910000, 0.0037165000, -0.052522400, -0.241013100, -0.859251500", \ - "0.0412913000, 0.0388204000, 0.0314084000, 0.0104357000, -0.050772200, -0.238996200, -0.857331900"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0016087930, 0.0051764320, 0.0166556200, 0.0535909000, 0.1724334000, 0.5548194000"); - values("0.0237090000, 0.0255349000, 0.0315606000, 0.0513641000, 0.1122819000, 0.3026127000, 0.9164804000", \ - "0.0235422000, 0.0253785000, 0.0313239000, 0.0512081000, 0.1121435000, 0.3023929000, 0.9162454000", \ - "0.0233414000, 0.0250590000, 0.0311096000, 0.0509462000, 0.1119053000, 0.3022170000, 0.9160756000", \ - "0.0229513000, 0.0248106000, 0.0307845000, 0.0506003000, 0.1114796000, 0.3019969000, 0.9147646000", \ - "0.0230440000, 0.0247758000, 0.0306975000, 0.0502507000, 0.1109245000, 0.3017469000, 0.9147330000", \ - "0.0242463000, 0.0258790000, 0.0314277000, 0.0504657000, 0.1102818000, 0.3014320000, 0.9196298000", \ - "0.0297729000, 0.0312707000, 0.0364715000, 0.0545834000, 0.1139558000, 0.3040393000, 0.9144837000"); - } - } - max_capacitance : 0.5548190000; - max_transition : 1.5067580000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.4256591000, 0.4335119000, 0.4539615000, 0.4990438000, 0.5859619000, 0.7552220000, 1.1386380000", \ - "0.4302835000, 0.4376602000, 0.4584051000, 0.5036316000, 0.5907211000, 0.7598787000, 1.1432725000", \ - "0.4415680000, 0.4496593000, 0.4699892000, 0.5151791000, 0.6020349000, 0.7713519000, 1.1546512000", \ - "0.4677969000, 0.4758457000, 0.4961702000, 0.5413570000, 0.6280421000, 0.7974483000, 1.1806079000", \ - "0.5150466000, 0.5227049000, 0.5429197000, 0.5881944000, 0.6748775000, 0.8443915000, 1.2275659000", \ - "0.5801922000, 0.5881159000, 0.6084566000, 0.6537472000, 0.7407489000, 0.9096976000, 1.2933904000", \ - "0.6539770000, 0.6606832000, 0.6813244000, 0.7263922000, 0.8130425000, 0.9819903000, 1.3655072000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3831611000, 0.3900169000, 0.4081532000, 0.4499202000, 0.5424143000, 0.7771561000, 1.4933949000", \ - "0.3884053000, 0.3953243000, 0.4134241000, 0.4550882000, 0.5476434000, 0.7824272000, 1.5019717000", \ - "0.4008553000, 0.4077808000, 0.4258457000, 0.4676460000, 0.5602280000, 0.7952144000, 1.5117252000", \ - "0.4326571000, 0.4395390000, 0.4576381000, 0.4994533000, 0.5920187000, 0.8269890000, 1.5435484000", \ - "0.5069712000, 0.5138905000, 0.5319641000, 0.5736261000, 0.6661960000, 0.9010470000, 1.6204450000", \ - "0.6498266000, 0.6567418000, 0.6748674000, 0.7167207000, 0.8093250000, 1.0443330000, 1.7608920000", \ - "0.8854207000, 0.8923941000, 0.9107120000, 0.9526996000, 1.0456054000, 1.2804270000, 1.9965638000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0812593000, 0.0854319000, 0.0963095000, 0.1192277000, 0.1753532000, 0.3148359000, 0.7361042000", \ - "0.0812743000, 0.0857649000, 0.0965727000, 0.1193398000, 0.1735815000, 0.3149580000, 0.7361461000", \ - "0.0814233000, 0.0852526000, 0.0957852000, 0.1190592000, 0.1753418000, 0.3151222000, 0.7360195000", \ - "0.0813613000, 0.0851991000, 0.0956170000, 0.1191761000, 0.1728021000, 0.3153081000, 0.7377873000", \ - "0.0814382000, 0.0848743000, 0.0957308000, 0.1201818000, 0.1734332000, 0.3151610000, 0.7375089000", \ - "0.0815478000, 0.0847409000, 0.0956018000, 0.1190778000, 0.1726552000, 0.3143408000, 0.7376081000", \ - "0.0815807000, 0.0850149000, 0.0961748000, 0.1212605000, 0.1729922000, 0.3145766000, 0.7380508000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0434249000, 0.0476338000, 0.0614524000, 0.0959372000, 0.1887686000, 0.4887469000, 1.5032563000", \ - "0.0432455000, 0.0482036000, 0.0613867000, 0.0961265000, 0.1884863000, 0.4890863000, 1.5033292000", \ - "0.0427561000, 0.0478662000, 0.0615752000, 0.0958310000, 0.1890478000, 0.4892808000, 1.5008041000", \ - "0.0427303000, 0.0480007000, 0.0612754000, 0.0958786000, 0.1890874000, 0.4892455000, 1.5012483000", \ - "0.0427553000, 0.0477633000, 0.0614369000, 0.0961925000, 0.1885537000, 0.4891677000, 1.5033150000", \ - "0.0428473000, 0.0479274000, 0.0615281000, 0.0960539000, 0.1892254000, 0.4893129000, 1.5008703000", \ - "0.0439511000, 0.0491508000, 0.0620620000, 0.0968503000, 0.1892991000, 0.4882663000, 1.4986914000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3922470000, 0.3998884000, 0.4198631000, 0.4638315000, 0.5482476000, 0.7126379000, 1.0910093000", \ - "0.3975285000, 0.4051761000, 0.4253966000, 0.4693113000, 0.5537954000, 0.7179729000, 1.0963149000", \ - "0.4102600000, 0.4179350000, 0.4379168000, 0.4818974000, 0.5661479000, 0.7305296000, 1.1090173000", \ - "0.4416266000, 0.4494065000, 0.4693403000, 0.5132035000, 0.5975904000, 0.7617241000, 1.1403805000", \ - "0.5146097000, 0.5222681000, 0.5422671000, 0.5862396000, 0.6705100000, 0.8349584000, 1.2135287000", \ - "0.6751355000, 0.6827581000, 0.7030065000, 0.7471894000, 0.8317158000, 0.9964638000, 1.3751752000", \ - "0.9743170000, 0.9828528000, 1.0046970000, 1.0527067000, 1.1417148000, 1.3107759000, 1.6917502000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2310944000, 0.2374369000, 0.2540977000, 0.2925516000, 0.3804305000, 0.6115429000, 1.3276665000", \ - "0.2357127000, 0.2420408000, 0.2587285000, 0.2971125000, 0.3850490000, 0.6159403000, 1.3296911000", \ - "0.2467554000, 0.2530690000, 0.2697432000, 0.3081420000, 0.3960877000, 0.6270156000, 1.3411592000", \ - "0.2710759000, 0.2774532000, 0.2939845000, 0.3324289000, 0.4203198000, 0.6514412000, 1.3677212000", \ - "0.3195935000, 0.3260200000, 0.3425639000, 0.3810753000, 0.4689641000, 0.7000732000, 1.4162188000", \ - "0.4045817000, 0.4113273000, 0.4287417000, 0.4685687000, 0.5577956000, 0.7890816000, 1.5058047000", \ - "0.5235561000, 0.5311476000, 0.5509764000, 0.5955794000, 0.6909673000, 0.9259964000, 1.6422584000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0786706000, 0.0824404000, 0.0924206000, 0.1145951000, 0.1690070000, 0.3074802000, 0.7312095000", \ - "0.0786519000, 0.0824009000, 0.0918999000, 0.1157247000, 0.1682089000, 0.3073728000, 0.7311222000", \ - "0.0784027000, 0.0819288000, 0.0916722000, 0.1150373000, 0.1673230000, 0.3063128000, 0.7305541000", \ - "0.0783449000, 0.0817181000, 0.0929761000, 0.1151401000, 0.1676635000, 0.3073593000, 0.7313118000", \ - "0.0787217000, 0.0822624000, 0.0919114000, 0.1152331000, 0.1675909000, 0.3064322000, 0.7305670000", \ - "0.0809967000, 0.0843107000, 0.0944485000, 0.1174351000, 0.1701875000, 0.3081257000, 0.7314095000", \ - "0.1031459000, 0.1054129000, 0.1125987000, 0.1320894000, 0.1801386000, 0.3138001000, 0.7338369000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0386199000, 0.0431196000, 0.0556835000, 0.0884983000, 0.1804753000, 0.4835878000, 1.4955431000", \ - "0.0384906000, 0.0433062000, 0.0556536000, 0.0883001000, 0.1808556000, 0.4838931000, 1.4985906000", \ - "0.0380667000, 0.0427671000, 0.0555693000, 0.0883315000, 0.1808755000, 0.4838980000, 1.4979317000", \ - "0.0382603000, 0.0429372000, 0.0554625000, 0.0884351000, 0.1807699000, 0.4838808000, 1.5004618000", \ - "0.0381556000, 0.0427564000, 0.0558777000, 0.0884788000, 0.1805796000, 0.4836511000, 1.4951390000", \ - "0.0410463000, 0.0457901000, 0.0588255000, 0.0918245000, 0.1828951000, 0.4843823000, 1.5005642000", \ - "0.0495942000, 0.0547614000, 0.0690299000, 0.1031884000, 0.1929634000, 0.4879255000, 1.4978304000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3380695000, 0.3456577000, 0.3664405000, 0.4112951000, 0.4979152000, 0.6667020000, 1.0493045000", \ - "0.3413627000, 0.3490775000, 0.3698392000, 0.4147356000, 0.5013048000, 0.6701513000, 1.0527231000", \ - "0.3497533000, 0.3575452000, 0.3781208000, 0.4229111000, 0.5094790000, 0.6778610000, 1.0608215000", \ - "0.3697109000, 0.3774013000, 0.3981442000, 0.4430533000, 0.5295233000, 0.6985258000, 1.0809058000", \ - "0.4252301000, 0.4330835000, 0.4533736000, 0.4985384000, 0.5847602000, 0.7530865000, 1.1361017000", \ - "0.5135644000, 0.5214589000, 0.5413146000, 0.5856380000, 0.6719941000, 0.8410179000, 1.2238374000", \ - "0.5767662000, 0.5842871000, 0.6049308000, 0.6496872000, 0.7361663000, 0.9047691000, 1.2861178000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2918713000, 0.2987783000, 0.3168499000, 0.3585272000, 0.4510635000, 0.6862508000, 1.4024096000", \ - "0.2953233000, 0.3022355000, 0.3203297000, 0.3619912000, 0.4545539000, 0.6897270000, 1.4052102000", \ - "0.3067972000, 0.3137120000, 0.3317722000, 0.3735949000, 0.4660897000, 0.7009968000, 1.4177245000", \ - "0.3364154000, 0.3433297000, 0.3613672000, 0.4030035000, 0.4955296000, 0.7303783000, 1.4496933000", \ - "0.3968382000, 0.4037500000, 0.4218345000, 0.4634682000, 0.5559986000, 0.7908031000, 1.5103181000", \ - "0.4839987000, 0.4909092000, 0.5089905000, 0.5504705000, 0.6428724000, 0.8778238000, 1.5940275000", \ - "0.6139315000, 0.6208871000, 0.6391329000, 0.6808898000, 0.7735892000, 1.0081405000, 1.7235952000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0793674000, 0.0834844000, 0.0939240000, 0.1180125000, 0.1745893000, 0.3143966000, 0.7355742000", \ - "0.0798912000, 0.0834925000, 0.0939100000, 0.1180355000, 0.1748514000, 0.3142096000, 0.7356812000", \ - "0.0792043000, 0.0832491000, 0.0939472000, 0.1179053000, 0.1724055000, 0.3138846000, 0.7378174000", \ - "0.0795680000, 0.0834214000, 0.0946257000, 0.1180887000, 0.1721542000, 0.3145347000, 0.7361644000", \ - "0.0789171000, 0.0830759000, 0.0933298000, 0.1188279000, 0.1720583000, 0.3138921000, 0.7377235000", \ - "0.0781453000, 0.0819728000, 0.0931455000, 0.1170476000, 0.1721201000, 0.3154187000, 0.7373486000", \ - "0.0788725000, 0.0832996000, 0.0938940000, 0.1177330000, 0.1743315000, 0.3133883000, 0.7336061000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0426796000, 0.0476555000, 0.0618861000, 0.0960630000, 0.1889497000, 0.4885282000, 1.4985861000", \ - "0.0426747000, 0.0476348000, 0.0618271000, 0.0960091000, 0.1889244000, 0.4881155000, 1.5067583000", \ - "0.0426794000, 0.0479099000, 0.0612003000, 0.0958899000, 0.1890880000, 0.4891058000, 1.5017636000", \ - "0.0426553000, 0.0477172000, 0.0620315000, 0.0961269000, 0.1885745000, 0.4891954000, 1.5032658000", \ - "0.0428707000, 0.0478020000, 0.0613703000, 0.0961384000, 0.1885244000, 0.4891623000, 1.5033617000", \ - "0.0427058000, 0.0476641000, 0.0618370000, 0.0951457000, 0.1886219000, 0.4890802000, 1.5033568000", \ - "0.0430614000, 0.0481058000, 0.0621172000, 0.0965913000, 0.1887761000, 0.4872625000, 1.4979761000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.3815133000, 0.3894630000, 0.4098517000, 0.4550156000, 0.5420926000, 0.7112244000, 1.0945912000", \ - "0.3852635000, 0.3931323000, 0.4137003000, 0.4588212000, 0.5454523000, 0.7142135000, 1.0979365000", \ - "0.3965354000, 0.4044065000, 0.4249592000, 0.4700429000, 0.5567284000, 0.7256349000, 1.1092702000", \ - "0.4253652000, 0.4332343000, 0.4537788000, 0.4988517000, 0.5855462000, 0.7544869000, 1.1381145000", \ - "0.4878257000, 0.4956991000, 0.5162761000, 0.5613653000, 0.6479272000, 0.8167164000, 1.2004774000", \ - "0.6156486000, 0.6235183000, 0.6440776000, 0.6893439000, 0.7766263000, 0.9456205000, 1.3292496000", \ - "0.8496880000, 0.8591659000, 0.8840274000, 0.9384259000, 1.0381420000, 1.2193131000, 1.6085751000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2087517000, 0.2148821000, 0.2315809000, 0.2697502000, 0.3571984000, 0.5872522000, 1.3039102000", \ - "0.2118200000, 0.2181196000, 0.2346309000, 0.2728231000, 0.3602804000, 0.5902194000, 1.3069555000", \ - "0.2210845000, 0.2273889000, 0.2438656000, 0.2821602000, 0.3695386000, 0.5999604000, 1.3155166000", \ - "0.2449426000, 0.2512737000, 0.2676598000, 0.3058772000, 0.3932905000, 0.6233461000, 1.3392139000", \ - "0.2973732000, 0.3036252000, 0.3201751000, 0.3583980000, 0.4454594000, 0.6759345000, 1.3912983000", \ - "0.3887018000, 0.3954971000, 0.4132271000, 0.4531935000, 0.5422995000, 0.7735722000, 1.4877992000", \ - "0.5102112000, 0.5183666000, 0.5398240000, 0.5860113000, 0.6815722000, 0.9156316000, 1.6301358000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0817046000, 0.0852700000, 0.0960393000, 0.1192593000, 0.1736225000, 0.3149540000, 0.7362827000", \ - "0.0811375000, 0.0848399000, 0.0960759000, 0.1212030000, 0.1727925000, 0.3147698000, 0.7372719000", \ - "0.0811486000, 0.0848480000, 0.0960535000, 0.1192181000, 0.1729818000, 0.3144931000, 0.7378205000", \ - "0.0811584000, 0.0848612000, 0.0960680000, 0.1192165000, 0.1730078000, 0.3145784000, 0.7378827000", \ - "0.0810757000, 0.0848355000, 0.0959631000, 0.1210567000, 0.1728066000, 0.3148517000, 0.7373575000", \ - "0.0833216000, 0.0867689000, 0.0966451000, 0.1204691000, 0.1747150000, 0.3160317000, 0.7384244000", \ - "0.1278673000, 0.1306597000, 0.1397731000, 0.1582695000, 0.2033628000, 0.3333131000, 0.7448414000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0376742000, 0.0426961000, 0.0552826000, 0.0875936000, 0.1798076000, 0.4831720000, 1.4966824000", \ - "0.0376514000, 0.0422331000, 0.0552827000, 0.0876539000, 0.1799115000, 0.4824034000, 1.5016258000", \ - "0.0382311000, 0.0429230000, 0.0554968000, 0.0878879000, 0.1796989000, 0.4834770000, 1.4956465000", \ - "0.0376277000, 0.0422584000, 0.0551723000, 0.0876782000, 0.1800520000, 0.4831961000, 1.5038940000", \ - "0.0377686000, 0.0428050000, 0.0552221000, 0.0877348000, 0.1800180000, 0.4833552000, 1.5014507000", \ - "0.0426771000, 0.0476369000, 0.0603644000, 0.0930912000, 0.1825783000, 0.4842775000, 1.4973527000", \ - "0.0560077000, 0.0614854000, 0.0756787000, 0.1081333000, 0.1946794000, 0.4892938000, 1.4982461000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2668316000, 0.2747777000, 0.2953696000, 0.3399719000, 0.4266974000, 0.5946740000, 0.9773117000", \ - "0.2719178000, 0.2797703000, 0.3002219000, 0.3449755000, 0.4314715000, 0.5996545000, 0.9823313000", \ - "0.2830986000, 0.2909487000, 0.3113574000, 0.3561979000, 0.4425984000, 0.6107772000, 0.9935786000", \ - "0.3087698000, 0.3162176000, 0.3369393000, 0.3817182000, 0.4682096000, 0.6367542000, 1.0191987000", \ - "0.3528884000, 0.3607324000, 0.3810973000, 0.4256626000, 0.5120542000, 0.6806971000, 1.0628175000", \ - "0.4314384000, 0.4387985000, 0.4565629000, 0.4975705000, 0.5801820000, 0.7459111000, 1.1281428000", \ - "0.4669448000, 0.4738144000, 0.4921240000, 0.5328386000, 0.6154952000, 0.7818299000, 1.1621341000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2110886000, 0.2180274000, 0.2360083000, 0.2777003000, 0.3699777000, 0.6048961000, 1.3217268000", \ - "0.2160972000, 0.2231367000, 0.2410624000, 0.2827740000, 0.3750156000, 0.6098983000, 1.3267168000", \ - "0.2294617000, 0.2363315000, 0.2543780000, 0.2959314000, 0.3883002000, 0.6230655000, 1.3396333000", \ - "0.2610714000, 0.2678931000, 0.2860658000, 0.3276976000, 0.4200320000, 0.6549645000, 1.3717686000", \ - "0.3277321000, 0.3346129000, 0.3527131000, 0.3941566000, 0.4867081000, 0.7216979000, 1.4360858000", \ - "0.4358554000, 0.4427226000, 0.4605956000, 0.5017564000, 0.5935182000, 0.8286684000, 1.5449939000", \ - "0.6025581000, 0.6093772000, 0.6272552000, 0.6685715000, 0.7607171000, 0.9949950000, 1.7084227000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0786341000, 0.0831284000, 0.0935391000, 0.1172680000, 0.1730000000, 0.3147439000, 0.7366063000", \ - "0.0788941000, 0.0826060000, 0.0934078000, 0.1173662000, 0.1725054000, 0.3143269000, 0.7373648000", \ - "0.0788674000, 0.0825418000, 0.0932651000, 0.1175059000, 0.1721030000, 0.3134950000, 0.7377309000", \ - "0.0790032000, 0.0828767000, 0.0938541000, 0.1174671000, 0.1719085000, 0.3141641000, 0.7370491000", \ - "0.0748925000, 0.0791468000, 0.0905281000, 0.1148528000, 0.1725000000, 0.3138742000, 0.7371484000", \ - "0.0677414000, 0.0715303000, 0.0822624000, 0.1078187000, 0.1659518000, 0.3093211000, 0.7362941000", \ - "0.0685542000, 0.0720238000, 0.0830183000, 0.1095733000, 0.1662565000, 0.3080801000, 0.7303422000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0422579000, 0.0472729000, 0.0608918000, 0.0954178000, 0.1886172000, 0.4887037000, 1.5019247000", \ - "0.0423425000, 0.0473845000, 0.0608039000, 0.0954205000, 0.1884957000, 0.4883162000, 1.5025474000", \ - "0.0428875000, 0.0471880000, 0.0614933000, 0.0954308000, 0.1881872000, 0.4883048000, 1.5031745000", \ - "0.0425533000, 0.0474439000, 0.0610769000, 0.0953521000, 0.1886846000, 0.4890256000, 1.5007798000", \ - "0.0427508000, 0.0477070000, 0.0611648000, 0.0952202000, 0.1883574000, 0.4887195000, 1.5049189000", \ - "0.0422268000, 0.0472303000, 0.0603694000, 0.0942058000, 0.1877725000, 0.4887460000, 1.5024643000", \ - "0.0425988000, 0.0469640000, 0.0611392000, 0.0953452000, 0.1883105000, 0.4869239000, 1.4974421000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.2684432000, 0.2762378000, 0.2969376000, 0.3418139000, 0.4286228000, 0.5970568000, 0.9802695000", \ - "0.2728686000, 0.2806774000, 0.3011202000, 0.3463010000, 0.4326541000, 0.6012622000, 0.9846650000", \ - "0.2833012000, 0.2912248000, 0.3116576000, 0.3567012000, 0.4431346000, 0.6117395000, 0.9951633000", \ - "0.3090587000, 0.3168364000, 0.3372951000, 0.3821430000, 0.4686130000, 0.6373982000, 1.0203772000", \ - "0.3652832000, 0.3731128000, 0.3933244000, 0.4380917000, 0.5242058000, 0.6924967000, 1.0759907000", \ - "0.4858512000, 0.4935758000, 0.5142708000, 0.5581578000, 0.6427895000, 0.8102217000, 1.1934281000", \ - "0.6765015000, 0.6861710000, 0.7121321000, 0.7691789000, 0.8719317000, 1.0508341000, 1.4399015000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.1472658000, 0.1535117000, 0.1700370000, 0.2084977000, 0.2958440000, 0.5254616000, 1.2418081000", \ - "0.1516246000, 0.1580757000, 0.1745165000, 0.2130157000, 0.3003373000, 0.5300616000, 1.2459219000", \ - "0.1622429000, 0.1684909000, 0.1851987000, 0.2235091000, 0.3109961000, 0.5409046000, 1.2555573000", \ - "0.1860980000, 0.1924169000, 0.2090037000, 0.2473376000, 0.3347432000, 0.5648241000, 1.2789168000", \ - "0.2397572000, 0.2460076000, 0.2623148000, 0.3004532000, 0.3879487000, 0.6182155000, 1.3322776000", \ - "0.3228910000, 0.3300710000, 0.3483686000, 0.3885857000, 0.4777370000, 0.7102421000, 1.4272180000", \ - "0.4183961000, 0.4272541000, 0.4502209000, 0.4998480000, 0.5959802000, 0.8293347000, 1.5452716000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0776990000, 0.0816446000, 0.0922818000, 0.1163257000, 0.1726218000, 0.3145150000, 0.7359776000", \ - "0.0778886000, 0.0819903000, 0.0919933000, 0.1166349000, 0.1715024000, 0.3149374000, 0.7377222000", \ - "0.0773770000, 0.0811503000, 0.0919584000, 0.1164766000, 0.1716140000, 0.3150216000, 0.7370692000", \ - "0.0772602000, 0.0812792000, 0.0924866000, 0.1163373000, 0.1719215000, 0.3145036000, 0.7375685000", \ - "0.0752653000, 0.0794602000, 0.0897844000, 0.1149865000, 0.1706384000, 0.3133526000, 0.7379239000", \ - "0.0797074000, 0.0834041000, 0.0929954000, 0.1161944000, 0.1693484000, 0.3131553000, 0.7367035000", \ - "0.1089457000, 0.1143986000, 0.1269597000, 0.1550234000, 0.2059518000, 0.3330370000, 0.7456653000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0016087900, 0.0051764300, 0.0166556000, 0.0535909000, 0.1724330000, 0.5548190000"); - values("0.0376856000, 0.0421718000, 0.0553028000, 0.0878369000, 0.1799879000, 0.4825312000, 1.4995650000", \ - "0.0377619000, 0.0423501000, 0.0549410000, 0.0877906000, 0.1800529000, 0.4828491000, 1.5023525000", \ - "0.0378171000, 0.0424062000, 0.0553020000, 0.0875035000, 0.1801801000, 0.4835686000, 1.5061882000", \ - "0.0380380000, 0.0425340000, 0.0549922000, 0.0874501000, 0.1801930000, 0.4836671000, 1.4968933000", \ - "0.0380586000, 0.0430191000, 0.0554898000, 0.0881198000, 0.1804512000, 0.4837065000, 1.4971314000", \ - "0.0490306000, 0.0536991000, 0.0649561000, 0.0959000000, 0.1853354000, 0.4852910000, 1.5008734000", \ - "0.0696359000, 0.0743740000, 0.0882664000, 0.1187429000, 0.1995943000, 0.4900162000, 1.4986430000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor2_1") { - leakage_power () { - value : 0.0033900000; - when : "!A&B"; - } - leakage_power () { - value : 0.0095263000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0025720000; - when : "A&B"; - } - leakage_power () { - value : 0.0016228000; - when : "A&!B"; - } - area : 8.7584000000; - cell_footprint : "sky130_fd_sc_hd__xor2"; - cell_leakage_power : 0.0042777740; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0043770000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0042100000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045440000; - } - pin ("B") { - capacitance : 0.0043390000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0041700000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0045090000; - } - pin ("X") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("-0.002077100, -0.003130900, -0.005552700, -0.011188900, -0.024286400, -0.054740400, -0.125377500", \ - "-0.002300700, -0.003335600, -0.005768200, -0.011402600, -0.024497400, -0.054969800, -0.125621600", \ - "-0.002515100, -0.003551000, -0.005964600, -0.011575700, -0.024686500, -0.055122900, -0.125811500", \ - "-0.002735300, -0.003757100, -0.006158000, -0.011720300, -0.024796100, -0.055224300, -0.125897100", \ - "-0.002526500, -0.003578000, -0.006160500, -0.011821200, -0.024844200, -0.055209900, -0.125835600", \ - "-0.002456000, -0.003521700, -0.005973600, -0.011680500, -0.024975800, -0.055431400, -0.126008500", \ - "-0.001550400, -0.002634600, -0.005211000, -0.010993400, -0.024367000, -0.055005100, -0.125924000"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0194647000, 0.0205470000, 0.0230392000, 0.0287201000, 0.0417897000, 0.0719793000, 0.1417898000", \ - "0.0193163000, 0.0203989000, 0.0229026000, 0.0286095000, 0.0417172000, 0.0719584000, 0.1417356000", \ - "0.0191295000, 0.0202204000, 0.0227340000, 0.0284762000, 0.0416176000, 0.0718763000, 0.1417052000", \ - "0.0190150000, 0.0200907000, 0.0225783000, 0.0282972000, 0.0414681000, 0.0717562000, 0.1417487000", \ - "0.0188638000, 0.0199437000, 0.0224228000, 0.0281279000, 0.0412337000, 0.0715507000, 0.1414644000", \ - "0.0188883000, 0.0199387000, 0.0224380000, 0.0281357000, 0.0413469000, 0.0715427000, 0.1413474000", \ - "0.0188070000, 0.0198598000, 0.0222689000, 0.0279179000, 0.0414563000, 0.0717843000, 0.1415505000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("-0.000564700, -0.001610500, -0.004038700, -0.009674000, -0.022789900, -0.053271900, -0.123953400", \ - "-0.000728400, -0.001762100, -0.004172900, -0.009779500, -0.022863400, -0.053376900, -0.124039000", \ - "-0.000886100, -0.001917600, -0.004317500, -0.009925900, -0.023008000, -0.053439900, -0.124094500", \ - "-0.001096400, -0.002131500, -0.004488500, -0.010060300, -0.023129100, -0.053511600, -0.124167000", \ - "-0.001075800, -0.002110100, -0.004568500, -0.010164800, -0.023206100, -0.053621900, -0.124216300", \ - "-0.000192600, -0.001225800, -0.003786800, -0.009522000, -0.022949200, -0.053429000, -0.124169200", \ - "0.0014540000, 0.0002934000, -0.002326600, -0.008313600, -0.021657500, -0.052713900, -0.123890900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0011573810, 0.0026790590, 0.0062013820, 0.0143547200, 0.0332277400, 0.0769142700"); - values("0.0158710000, 0.0170026000, 0.0195626000, 0.0253543000, 0.0385783000, 0.0689402000, 0.1391470000", \ - "0.0156279000, 0.0167809000, 0.0193500000, 0.0252126000, 0.0385144000, 0.0689018000, 0.1391206000", \ - "0.0153924000, 0.0165362000, 0.0190886000, 0.0249652000, 0.0383225000, 0.0688351000, 0.1390597000", \ - "0.0152466000, 0.0163447000, 0.0188834000, 0.0246755000, 0.0380209000, 0.0686236000, 0.1388356000", \ - "0.0150737000, 0.0161641000, 0.0186845000, 0.0244037000, 0.0376706000, 0.0682359000, 0.1385220000", \ - "0.0150613000, 0.0161275000, 0.0186268000, 0.0243984000, 0.0376113000, 0.0679970000, 0.1384075000", \ - "0.0155064000, 0.0164788000, 0.0188898000, 0.0243005000, 0.0379059000, 0.0682123000, 0.1381762000"); - } - } - max_capacitance : 0.0769140000; - max_transition : 1.4949300000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.1260781000, 0.1305779000, 0.1394517000, 0.1564011000, 0.1879941000, 0.2505041000, 0.3861979000", \ - "0.1304028000, 0.1349049000, 0.1439232000, 0.1608823000, 0.1924910000, 0.2550079000, 0.3906395000", \ - "0.1427176000, 0.1472222000, 0.1561309000, 0.1731223000, 0.2047547000, 0.2673041000, 0.4028436000", \ - "0.1703706000, 0.1748537000, 0.1838551000, 0.2008618000, 0.2325875000, 0.2951577000, 0.4307854000", \ - "0.2293584000, 0.2340627000, 0.2433476000, 0.2608962000, 0.2932189000, 0.3561483000, 0.4920306000", \ - "0.3315263000, 0.3369141000, 0.3477782000, 0.3678538000, 0.4036732000, 0.4696795000, 0.6057169000", \ - "0.5028164000, 0.5095501000, 0.5230193000, 0.5475777000, 0.5896687000, 0.6618416000, 0.8025696000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0805268000, 0.0901096000, 0.1121622000, 0.1611127000, 0.2722019000, 0.5274848000, 1.1114145000", \ - "0.0852071000, 0.0949025000, 0.1167658000, 0.1657099000, 0.2768830000, 0.5320950000, 1.1159003000", \ - "0.0958198000, 0.1054061000, 0.1269734000, 0.1763352000, 0.2872659000, 0.5419800000, 1.1288998000", \ - "0.1150732000, 0.1243955000, 0.1459258000, 0.1946540000, 0.3060574000, 0.5619045000, 1.1465542000", \ - "0.1399119000, 0.1491484000, 0.1704658000, 0.2192204000, 0.3302435000, 0.5851317000, 1.1746978000", \ - "0.1649774000, 0.1735583000, 0.1944131000, 0.2423617000, 0.3536036000, 0.6071239000, 1.1960524000", \ - "0.1672753000, 0.1772291000, 0.1984824000, 0.2452677000, 0.3557831000, 0.6100516000, 1.1963149000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0264673000, 0.0296661000, 0.0365682000, 0.0517175000, 0.0831413000, 0.1547333000, 0.3304736000", \ - "0.0262472000, 0.0298418000, 0.0366798000, 0.0517706000, 0.0830630000, 0.1547963000, 0.3292057000", \ - "0.0262421000, 0.0297373000, 0.0365519000, 0.0517419000, 0.0829266000, 0.1545751000, 0.3292031000", \ - "0.0264623000, 0.0298077000, 0.0366060000, 0.0516561000, 0.0830452000, 0.1548961000, 0.3291359000", \ - "0.0285969000, 0.0318820000, 0.0389111000, 0.0532984000, 0.0840589000, 0.1554390000, 0.3312235000", \ - "0.0355090000, 0.0394565000, 0.0468160000, 0.0612132000, 0.0922773000, 0.1607217000, 0.3312671000", \ - "0.0492439000, 0.0533773000, 0.0616257000, 0.0776297000, 0.1084086000, 0.1750214000, 0.3376649000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0559991000, 0.0684585000, 0.0971430000, 0.1629645000, 0.3141736000, 0.6633058000, 1.4723042000", \ - "0.0559564000, 0.0684065000, 0.0969287000, 0.1629742000, 0.3141490000, 0.6638274000, 1.4727028000", \ - "0.0558953000, 0.0683034000, 0.0970937000, 0.1630153000, 0.3136869000, 0.6637068000, 1.4762130000", \ - "0.0558532000, 0.0683361000, 0.0969092000, 0.1628033000, 0.3141826000, 0.6636764000, 1.4720821000", \ - "0.0560695000, 0.0685496000, 0.0968821000, 0.1625735000, 0.3139443000, 0.6631236000, 1.4703802000", \ - "0.0591639000, 0.0707668000, 0.0979003000, 0.1624643000, 0.3140978000, 0.6621517000, 1.4735394000", \ - "0.0691211000, 0.0795006000, 0.1035307000, 0.1643065000, 0.3145804000, 0.6652780000, 1.4691667000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0352160000, 0.0388539000, 0.0468747000, 0.0647332000, 0.1045450000, 0.1949742000, 0.4035363000", \ - "0.0394004000, 0.0430108000, 0.0510450000, 0.0689508000, 0.1087421000, 0.1993264000, 0.4071859000", \ - "0.0486784000, 0.0522640000, 0.0603013000, 0.0782435000, 0.1180902000, 0.2087326000, 0.4166521000", \ - "0.0655858000, 0.0701088000, 0.0795541000, 0.0991409000, 0.1396683000, 0.2303657000, 0.4387813000", \ - "0.0875980000, 0.0942939000, 0.1077577000, 0.1349334000, 0.1844770000, 0.2797716000, 0.4885370000", \ - "0.1061057000, 0.1166075000, 0.1380046000, 0.1796099000, 0.2534398000, 0.3776657000, 0.6024938000", \ - "0.0968148000, 0.1132386000, 0.1463574000, 0.2129888000, 0.3280751000, 0.5185704000, 0.8219866000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0948388000, 0.1041693000, 0.1250308000, 0.1729275000, 0.2826903000, 0.5358681000, 1.1224185000", \ - "0.0997006000, 0.1091417000, 0.1302596000, 0.1783790000, 0.2883820000, 0.5414972000, 1.1267793000", \ - "0.1124715000, 0.1218850000, 0.1429507000, 0.1912883000, 0.3017633000, 0.5551545000, 1.1406027000", \ - "0.1411091000, 0.1506083000, 0.1717647000, 0.2199123000, 0.3304829000, 0.5842588000, 1.1700171000", \ - "0.1996200000, 0.2103342000, 0.2339011000, 0.2826987000, 0.3930376000, 0.6473470000, 1.2363838000", \ - "0.2991085000, 0.3144787000, 0.3466624000, 0.4115208000, 0.5373699000, 0.7925411000, 1.3793274000", \ - "0.4601484000, 0.4848043000, 0.5356379000, 0.6339610000, 0.8093701000, 1.1212123000, 1.7153349000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0268070000, 0.0309197000, 0.0406657000, 0.0629952000, 0.1146123000, 0.2338845000, 0.5113115000", \ - "0.0265745000, 0.0308103000, 0.0405700000, 0.0630001000, 0.1147710000, 0.2341315000, 0.5109784000", \ - "0.0273977000, 0.0313809000, 0.0407010000, 0.0627726000, 0.1146965000, 0.2348027000, 0.5108560000", \ - "0.0359329000, 0.0397354000, 0.0481907000, 0.0672894000, 0.1159250000, 0.2347790000, 0.5122973000", \ - "0.0558640000, 0.0605831000, 0.0702350000, 0.0908629000, 0.1336710000, 0.2409196000, 0.5116116000", \ - "0.0930712000, 0.0996754000, 0.1138666000, 0.1407247000, 0.1920497000, 0.2924649000, 0.5313402000", \ - "0.1602269000, 0.1707912000, 0.1922773000, 0.2323080000, 0.3029279000, 0.4271720000, 0.6598243000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0708785000, 0.0832371000, 0.1115828000, 0.1769030000, 0.3274312000, 0.6747152000, 1.4813105000", \ - "0.0708367000, 0.0832027000, 0.1114740000, 0.1769160000, 0.3274796000, 0.6749863000, 1.4829173000", \ - "0.0708796000, 0.0832425000, 0.1114836000, 0.1769081000, 0.3278554000, 0.6753349000, 1.4822017000", \ - "0.0714485000, 0.0835557000, 0.1116746000, 0.1769053000, 0.3280268000, 0.6751179000, 1.4809081000", \ - "0.0863420000, 0.0970610000, 0.1217636000, 0.1817605000, 0.3276440000, 0.6758402000, 1.4813757000", \ - "0.1288221000, 0.1413779000, 0.1682770000, 0.2256277000, 0.3541276000, 0.6802625000, 1.4843736000", \ - "0.2171918000, 0.2341914000, 0.2674705000, 0.3359406000, 0.4748296000, 0.7597126000, 1.4949302000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.1119355000, 0.1164846000, 0.1254458000, 0.1420844000, 0.1734929000, 0.2358023000, 0.3713667000", \ - "0.1145787000, 0.1191019000, 0.1280360000, 0.1446977000, 0.1760782000, 0.2385529000, 0.3739911000", \ - "0.1243800000, 0.1289216000, 0.1378763000, 0.1546987000, 0.1862287000, 0.2486780000, 0.3843430000", \ - "0.1518770000, 0.1563293000, 0.1652448000, 0.1821427000, 0.2139026000, 0.2763089000, 0.4118076000", \ - "0.2119237000, 0.2166565000, 0.2260768000, 0.2439280000, 0.2763449000, 0.3380537000, 0.4736239000", \ - "0.3080707000, 0.3137892000, 0.3248637000, 0.3448279000, 0.3792878000, 0.4447560000, 0.5834592000", \ - "0.4616952000, 0.4684687000, 0.4826081000, 0.5073768000, 0.5480423000, 0.6172247000, 0.7556638000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0949423000, 0.1041636000, 0.1247498000, 0.1711284000, 0.2782069000, 0.5285485000, 1.1116181000", \ - "0.0990569000, 0.1083693000, 0.1289222000, 0.1756000000, 0.2832033000, 0.5337654000, 1.1162513000", \ - "0.1062256000, 0.1155714000, 0.1364855000, 0.1839829000, 0.2925876000, 0.5440694000, 1.1298726000", \ - "0.1200673000, 0.1290008000, 0.1501402000, 0.1983744000, 0.3081556000, 0.5608337000, 1.1440034000", \ - "0.1391193000, 0.1484946000, 0.1698302000, 0.2183489000, 0.3278706000, 0.5812834000, 1.1663579000", \ - "0.1584242000, 0.1675459000, 0.1882291000, 0.2363708000, 0.3475857000, 0.6005512000, 1.1863653000", \ - "0.1589764000, 0.1696126000, 0.1911546000, 0.2387389000, 0.3492497000, 0.6030779000, 1.1890815000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0263048000, 0.0298038000, 0.0366317000, 0.0520319000, 0.0832687000, 0.1550885000, 0.3285631000", \ - "0.0263206000, 0.0297798000, 0.0366277000, 0.0519846000, 0.0833041000, 0.1551073000, 0.3292810000", \ - "0.0264656000, 0.0297929000, 0.0369667000, 0.0518066000, 0.0833601000, 0.1550330000, 0.3288118000", \ - "0.0266960000, 0.0300142000, 0.0370863000, 0.0515049000, 0.0830891000, 0.1550566000, 0.3292530000", \ - "0.0303332000, 0.0332914000, 0.0399530000, 0.0544424000, 0.0853628000, 0.1561607000, 0.3293331000", \ - "0.0400696000, 0.0432706000, 0.0501229000, 0.0631056000, 0.0933984000, 0.1627742000, 0.3325488000", \ - "0.0554817000, 0.0596167000, 0.0678472000, 0.0817858000, 0.1090506000, 0.1725151000, 0.3373886000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0706175000, 0.0830671000, 0.1115782000, 0.1768253000, 0.3285535000, 0.6748362000, 1.4792777000", \ - "0.0706153000, 0.0830585000, 0.1115793000, 0.1768934000, 0.3279727000, 0.6776349000, 1.4782999000", \ - "0.0704250000, 0.0829393000, 0.1115259000, 0.1768404000, 0.3275434000, 0.6753585000, 1.4840916000", \ - "0.0685932000, 0.0813921000, 0.1108935000, 0.1768842000, 0.3277024000, 0.6759032000, 1.4788976000", \ - "0.0627341000, 0.0753004000, 0.1045623000, 0.1718125000, 0.3248507000, 0.6749376000, 1.4836402000", \ - "0.0624435000, 0.0737931000, 0.1015743000, 0.1671756000, 0.3195790000, 0.6695119000, 1.4823713000", \ - "0.0727403000, 0.0832519000, 0.1074363000, 0.1677117000, 0.3175977000, 0.6659331000, 1.4719543000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0309732000, 0.0346482000, 0.0427064000, 0.0605022000, 0.1003507000, 0.1908033000, 0.3989499000", \ - "0.0348663000, 0.0385392000, 0.0466734000, 0.0644633000, 0.1043667000, 0.1948870000, 0.4028073000", \ - "0.0451201000, 0.0486055000, 0.0565986000, 0.0742505000, 0.1141900000, 0.2048513000, 0.4127672000", \ - "0.0626472000, 0.0677324000, 0.0782441000, 0.0982767000, 0.1370429000, 0.2275880000, 0.4356447000", \ - "0.0822582000, 0.0899440000, 0.1058964000, 0.1360306000, 0.1896039000, 0.2836394000, 0.4912887000", \ - "0.0969840000, 0.1082338000, 0.1320925000, 0.1780485000, 0.2586570000, 0.3956471000, 0.6187594000", \ - "0.0838002000, 0.1010691000, 0.1375698000, 0.2067880000, 0.3313068000, 0.5398489000, 0.8693024000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0772738000, 0.0868062000, 0.1083607000, 0.1568500000, 0.2672399000, 0.5202041000, 1.1063365000", \ - "0.0814557000, 0.0910127000, 0.1126222000, 0.1616436000, 0.2722963000, 0.5270045000, 1.1109927000", \ - "0.0933737000, 0.1027599000, 0.1243479000, 0.1730373000, 0.2841319000, 0.5392129000, 1.1267179000", \ - "0.1200550000, 0.1293835000, 0.1505629000, 0.1993662000, 0.3110422000, 0.5656142000, 1.1555157000", \ - "0.1685933000, 0.1807880000, 0.2060294000, 0.2575598000, 0.3689005000, 0.6241932000, 1.2134473000", \ - "0.2449120000, 0.2635063000, 0.3002846000, 0.3706545000, 0.5024765000, 0.7597254000, 1.3463815000", \ - "0.3644032000, 0.3933267000, 0.4511984000, 0.5585382000, 0.7460655000, 1.0660270000, 1.6634460000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0268727000, 0.0309845000, 0.0408186000, 0.0630336000, 0.1148063000, 0.2339956000, 0.5109955000", \ - "0.0264706000, 0.0308194000, 0.0404970000, 0.0629726000, 0.1148316000, 0.2348778000, 0.5105305000", \ - "0.0282614000, 0.0319711000, 0.0409172000, 0.0625355000, 0.1144915000, 0.2348099000, 0.5102969000", \ - "0.0407127000, 0.0446543000, 0.0534106000, 0.0701772000, 0.1167693000, 0.2339469000, 0.5115301000", \ - "0.0639313000, 0.0695681000, 0.0812671000, 0.1041985000, 0.1444321000, 0.2447307000, 0.5109024000", \ - "0.1044679000, 0.1138895000, 0.1310511000, 0.1641385000, 0.2247427000, 0.3205680000, 0.5404304000", \ - "0.1770195000, 0.1902933000, 0.2176950000, 0.2681031000, 0.3527875000, 0.4914411000, 0.7245220000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0011573800, 0.0026790600, 0.0062013800, 0.0143547000, 0.0332277000, 0.0769143000"); - values("0.0564916000, 0.0688590000, 0.0971614000, 0.1629792000, 0.3138555000, 0.6654284000, 1.4739844000", \ - "0.0565454000, 0.0688077000, 0.0972560000, 0.1625976000, 0.3142461000, 0.6637045000, 1.4715126000", \ - "0.0564649000, 0.0688462000, 0.0972332000, 0.1629369000, 0.3140332000, 0.6639587000, 1.4762663000", \ - "0.0586867000, 0.0703250000, 0.0977461000, 0.1625887000, 0.3138589000, 0.6636837000, 1.4722206000", \ - "0.0769930000, 0.0884248000, 0.1124090000, 0.1703816000, 0.3146879000, 0.6640193000, 1.4718338000", \ - "0.1197552000, 0.1328259000, 0.1603563000, 0.2187200000, 0.3451457000, 0.6684276000, 1.4718399000", \ - "0.2058815000, 0.2230695000, 0.2578505000, 0.3296079000, 0.4685026000, 0.7598814000, 1.4874599000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor2_2") { - leakage_power () { - value : 0.0048373000; - when : "!A&B"; - } - leakage_power () { - value : 0.0090099000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0049460000; - when : "A&B"; - } - leakage_power () { - value : 0.0035835000; - when : "A&!B"; - } - area : 16.265600000; - cell_footprint : "sky130_fd_sc_hd__xor2"; - cell_leakage_power : 0.0055941920; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0089800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0085840000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0093760000; - } - pin ("B") { - capacitance : 0.0081650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0078370000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0084930000; - } - pin ("X") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("-0.004662100, -0.005887700, -0.008965500, -0.016735900, -0.036513600, -0.086570300, -0.213492400", \ - "-0.005076400, -0.006296000, -0.009353900, -0.017123000, -0.036854300, -0.086996900, -0.213939600", \ - "-0.005573400, -0.006764800, -0.009812900, -0.017536000, -0.037200600, -0.087318900, -0.214263500", \ - "-0.006086500, -0.007273700, -0.010250900, -0.017895400, -0.037531000, -0.087562600, -0.214505900", \ - "-0.006150200, -0.007354900, -0.010445400, -0.018147800, -0.037660700, -0.087555500, -0.214433800", \ - "-0.005658700, -0.006885400, -0.009986500, -0.017858500, -0.037893600, -0.088025200, -0.214788400", \ - "-0.003892000, -0.005201400, -0.008370400, -0.016481400, -0.036733800, -0.087261400, -0.214735100"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0369292000, 0.0381656000, 0.0413140000, 0.0491942000, 0.0689991000, 0.1187768000, 0.2445055000", \ - "0.0365398000, 0.0377870000, 0.0409828000, 0.0489316000, 0.0688532000, 0.1186584000, 0.2442397000", \ - "0.0361215000, 0.0373753000, 0.0405773000, 0.0486252000, 0.0685953000, 0.1184569000, 0.2443046000", \ - "0.0358413000, 0.0370973000, 0.0402531000, 0.0482564000, 0.0682185000, 0.1182749000, 0.2440825000", \ - "0.0355508000, 0.0368054000, 0.0399221000, 0.0478569000, 0.0678184000, 0.1178351000, 0.2435529000", \ - "0.0355410000, 0.0367405000, 0.0399061000, 0.0479024000, 0.0678099000, 0.1178255000, 0.2432769000", \ - "0.0352335000, 0.0364207000, 0.0394499000, 0.0471029000, 0.0679413000, 0.1179691000, 0.2435949000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("-0.001225600, -0.002450400, -0.005515900, -0.013299800, -0.033041100, -0.083177300, -0.210251600", \ - "-0.001528400, -0.002731500, -0.005788500, -0.013531400, -0.033213200, -0.083368600, -0.210375000", \ - "-0.001939500, -0.003108100, -0.006129500, -0.013804100, -0.033493700, -0.083536300, -0.210567000", \ - "-0.002457400, -0.003670300, -0.006591000, -0.014176900, -0.033770000, -0.083764500, -0.210692000", \ - "-0.002284100, -0.003469200, -0.006565000, -0.014197300, -0.033776900, -0.083796300, -0.210691000", \ - "-0.000898100, -0.002108200, -0.005717400, -0.013688500, -0.033704400, -0.083756400, -0.210784100", \ - "0.0017924000, 0.0004754000, -0.002757900, -0.011136400, -0.031267500, -0.082080500, -0.210166100"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012632050, 0.0031913740, 0.0080627180, 0.0203697300, 0.0514622900, 0.1300148000"); - values("0.0274399000, 0.0288075000, 0.0321880000, 0.0403616000, 0.0604082000, 0.1104334000, 0.2368603000", \ - "0.0269872000, 0.0283851000, 0.0317982000, 0.0400037000, 0.0603026000, 0.1104994000, 0.2368246000", \ - "0.0266097000, 0.0279355000, 0.0312839000, 0.0395135000, 0.0599307000, 0.1103915000, 0.2366890000", \ - "0.0263455000, 0.0276542000, 0.0308905000, 0.0390774000, 0.0593604000, 0.1100257000, 0.2366081000", \ - "0.0260555000, 0.0273572000, 0.0305662000, 0.0385536000, 0.0587118000, 0.1092827000, 0.2361458000", \ - "0.0259435000, 0.0271979000, 0.0303973000, 0.0385457000, 0.0585611000, 0.1089672000, 0.2354595000", \ - "0.0262366000, 0.0273811000, 0.0302657000, 0.0378938000, 0.0586015000, 0.1084169000, 0.2355467000"); - } - } - max_capacitance : 0.1300150000; - max_transition : 1.4987380000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.1384977000, 0.1422068000, 0.1502977000, 0.1661566000, 0.1964545000, 0.2572546000, 0.3935969000", \ - "0.1424172000, 0.1461692000, 0.1541685000, 0.1701493000, 0.2004523000, 0.2613210000, 0.3976153000", \ - "0.1540817000, 0.1577757000, 0.1659206000, 0.1818899000, 0.2121926000, 0.2731040000, 0.4094225000", \ - "0.1809945000, 0.1847089000, 0.1927287000, 0.2088414000, 0.2392330000, 0.3001880000, 0.4362988000", \ - "0.2372084000, 0.2410560000, 0.2493079000, 0.2654707000, 0.2965450000, 0.3578703000, 0.4942545000", \ - "0.3325887000, 0.3369353000, 0.3463400000, 0.3649617000, 0.3994033000, 0.4648464000, 0.6041764000", \ - "0.4898087000, 0.4950906000, 0.5068504000, 0.5295729000, 0.5705907000, 0.6425233000, 0.7862694000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0708429000, 0.0774858000, 0.0939566000, 0.1346119000, 0.2333286000, 0.4791645000, 1.0950048000", \ - "0.0756947000, 0.0822814000, 0.0989232000, 0.1395524000, 0.2378364000, 0.4835485000, 1.1019025000", \ - "0.0867937000, 0.0933608000, 0.1095408000, 0.1499780000, 0.2492272000, 0.4942581000, 1.1093417000", \ - "0.1065740000, 0.1129424000, 0.1289719000, 0.1689532000, 0.2677890000, 0.5134025000, 1.1323527000", \ - "0.1328139000, 0.1389481000, 0.1542258000, 0.1939757000, 0.2923455000, 0.5393939000, 1.1584920000", \ - "0.1600978000, 0.1664035000, 0.1811765000, 0.2204848000, 0.3184447000, 0.5637100000, 1.1815759000", \ - "0.1671551000, 0.1745894000, 0.1913832000, 0.2300386000, 0.3268911000, 0.5726919000, 1.1884465000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0232702000, 0.0257073000, 0.0318215000, 0.0444459000, 0.0731155000, 0.1395496000, 0.3126162000", \ - "0.0232763000, 0.0259348000, 0.0317299000, 0.0444188000, 0.0730869000, 0.1398639000, 0.3121319000", \ - "0.0233470000, 0.0258045000, 0.0317852000, 0.0443448000, 0.0729728000, 0.1397891000, 0.3128331000", \ - "0.0235786000, 0.0261886000, 0.0317882000, 0.0444738000, 0.0730364000, 0.1399871000, 0.3127691000", \ - "0.0253195000, 0.0280221000, 0.0335514000, 0.0459919000, 0.0742742000, 0.1400061000, 0.3126039000", \ - "0.0308286000, 0.0336105000, 0.0402202000, 0.0530794000, 0.0818041000, 0.1468926000, 0.3160481000", \ - "0.0424813000, 0.0461582000, 0.0527709000, 0.0675221000, 0.0978595000, 0.1616311000, 0.3240657000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0433950000, 0.0521716000, 0.0742378000, 0.1284433000, 0.2624563000, 0.6002645000, 1.4511636000", \ - "0.0434337000, 0.0522449000, 0.0740179000, 0.1283847000, 0.2628413000, 0.6011170000, 1.4515309000", \ - "0.0433964000, 0.0521159000, 0.0741651000, 0.1281615000, 0.2628724000, 0.5996897000, 1.4526607000", \ - "0.0434933000, 0.0520284000, 0.0738791000, 0.1281932000, 0.2622725000, 0.5993517000, 1.4537517000", \ - "0.0437520000, 0.0522671000, 0.0737491000, 0.1280984000, 0.2623953000, 0.6008260000, 1.4501028000", \ - "0.0471760000, 0.0549205000, 0.0753277000, 0.1279875000, 0.2627280000, 0.5983435000, 1.4513487000", \ - "0.0568262000, 0.0640667000, 0.0821018000, 0.1304363000, 0.2625872000, 0.6016371000, 1.4457520000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0366878000, 0.0394202000, 0.0460515000, 0.0614511000, 0.0983492000, 0.1882181000, 0.4122795000", \ - "0.0409317000, 0.0437046000, 0.0503680000, 0.0658174000, 0.1026503000, 0.1925650000, 0.4172927000", \ - "0.0503424000, 0.0530575000, 0.0595900000, 0.0751747000, 0.1120444000, 0.2020318000, 0.4265575000", \ - "0.0674054000, 0.0709212000, 0.0787132000, 0.0956543000, 0.1330796000, 0.2234468000, 0.4482092000", \ - "0.0908163000, 0.0956347000, 0.1065715000, 0.1298773000, 0.1765074000, 0.2719941000, 0.4975408000", \ - "0.1118816000, 0.1193171000, 0.1361500000, 0.1723709000, 0.2420603000, 0.3677965000, 0.6106943000", \ - "0.1079090000, 0.1191817000, 0.1464129000, 0.2032867000, 0.3126409000, 0.5044731000, 0.8291883000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.1013748000, 0.1077552000, 0.1240475000, 0.1636831000, 0.2619730000, 0.5085546000, 1.1298122000", \ - "0.1055375000, 0.1120018000, 0.1284449000, 0.1684071000, 0.2670783000, 0.5140612000, 1.1362680000", \ - "0.1173207000, 0.1237444000, 0.1400384000, 0.1803647000, 0.2795946000, 0.5269080000, 1.1487459000", \ - "0.1453186000, 0.1517258000, 0.1677739000, 0.2077863000, 0.3071755000, 0.5548991000, 1.1767954000", \ - "0.1999506000, 0.2077888000, 0.2257879000, 0.2674549000, 0.3665707000, 0.6144783000, 1.2378885000", \ - "0.2910742000, 0.3021466000, 0.3268688000, 0.3820665000, 0.4996659000, 0.7511051000, 1.3740229000", \ - "0.4336232000, 0.4504984000, 0.4898813000, 0.5742122000, 0.7397000000, 1.0549978000, 1.6919731000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0278557000, 0.0307555000, 0.0381278000, 0.0569801000, 0.1046576000, 0.2258045000, 0.5323001000", \ - "0.0275980000, 0.0305700000, 0.0380380000, 0.0568992000, 0.1046078000, 0.2260061000, 0.5331962000", \ - "0.0278874000, 0.0307257000, 0.0379815000, 0.0565398000, 0.1045299000, 0.2257749000, 0.5324279000", \ - "0.0352853000, 0.0378809000, 0.0446928000, 0.0610429000, 0.1058141000, 0.2258656000, 0.5328579000", \ - "0.0533967000, 0.0566260000, 0.0646769000, 0.0824657000, 0.1237218000, 0.2317967000, 0.5327737000", \ - "0.0879987000, 0.0927476000, 0.1038514000, 0.1281722000, 0.1786074000, 0.2820623000, 0.5505975000", \ - "0.1521567000, 0.1596079000, 0.1759489000, 0.2111251000, 0.2808864000, 0.4101538000, 0.6719281000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0658635000, 0.0744751000, 0.0961230000, 0.1501198000, 0.2848755000, 0.6248285000, 1.4843966000", \ - "0.0658935000, 0.0743274000, 0.0961270000, 0.1501292000, 0.2849601000, 0.6239809000, 1.4863532000", \ - "0.0658033000, 0.0744992000, 0.0959603000, 0.1498550000, 0.2852739000, 0.6251155000, 1.4846022000", \ - "0.0666618000, 0.0749003000, 0.0962001000, 0.1501097000, 0.2848835000, 0.6246919000, 1.4820652000", \ - "0.0807572000, 0.0882044000, 0.1072274000, 0.1565418000, 0.2860165000, 0.6249157000, 1.4860295000", \ - "0.1189094000, 0.1277407000, 0.1492433000, 0.1994202000, 0.3158029000, 0.6305258000, 1.4816749000", \ - "0.2013897000, 0.2133187000, 0.2401065000, 0.3014739000, 0.4314330000, 0.7206652000, 1.4987376000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.1135354000, 0.1172345000, 0.1253212000, 0.1411321000, 0.1709996000, 0.2317773000, 0.3679881000", \ - "0.1158619000, 0.1196099000, 0.1277814000, 0.1435497000, 0.1736785000, 0.2345190000, 0.3707583000", \ - "0.1261537000, 0.1298374000, 0.1377989000, 0.1536590000, 0.1836019000, 0.2442664000, 0.3807297000", \ - "0.1536260000, 0.1573158000, 0.1652684000, 0.1810274000, 0.2114569000, 0.2723175000, 0.4085383000", \ - "0.2157204000, 0.2195236000, 0.2277852000, 0.2437790000, 0.2747045000, 0.3364387000, 0.4730395000", \ - "0.3175672000, 0.3221342000, 0.3319043000, 0.3505945000, 0.3832005000, 0.4476124000, 0.5871739000", \ - "0.4813654000, 0.4871496000, 0.4995248000, 0.5224838000, 0.5624081000, 0.6304612000, 0.7708766000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0898785000, 0.0960548000, 0.1114666000, 0.1491248000, 0.2437286000, 0.4865190000, 1.1045026000", \ - "0.0940707000, 0.1003422000, 0.1156960000, 0.1538906000, 0.2489380000, 0.4917062000, 1.1096301000", \ - "0.1013511000, 0.1077969000, 0.1235103000, 0.1623957000, 0.2589187000, 0.5028688000, 1.1212922000", \ - "0.1139012000, 0.1203263000, 0.1361622000, 0.1757829000, 0.2740495000, 0.5188473000, 1.1400489000", \ - "0.1293636000, 0.1358092000, 0.1523199000, 0.1933448000, 0.2917342000, 0.5383232000, 1.1579030000", \ - "0.1431522000, 0.1496354000, 0.1657491000, 0.2056076000, 0.3055157000, 0.5534739000, 1.1742622000", \ - "0.1330891000, 0.1409090000, 0.1587939000, 0.1981393000, 0.2963700000, 0.5450383000, 1.1688642000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0233165000, 0.0258682000, 0.0318581000, 0.0447566000, 0.0734567000, 0.1402240000, 0.3125750000", \ - "0.0235705000, 0.0258730000, 0.0316446000, 0.0448949000, 0.0733738000, 0.1400845000, 0.3128873000", \ - "0.0233875000, 0.0260026000, 0.0317997000, 0.0448137000, 0.0734731000, 0.1399741000, 0.3129170000", \ - "0.0234414000, 0.0259759000, 0.0318132000, 0.0446572000, 0.0731613000, 0.1399281000, 0.3129010000", \ - "0.0260998000, 0.0286890000, 0.0343501000, 0.0473948000, 0.0753344000, 0.1411505000, 0.3131180000", \ - "0.0352046000, 0.0377193000, 0.0433195000, 0.0548519000, 0.0821210000, 0.1472213000, 0.3172045000", \ - "0.0494604000, 0.0520416000, 0.0593126000, 0.0724877000, 0.0970250000, 0.1579033000, 0.3226391000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0649654000, 0.0736882000, 0.0956477000, 0.1498763000, 0.2857273000, 0.6272573000, 1.4811267000", \ - "0.0649800000, 0.0737642000, 0.0955446000, 0.1499280000, 0.2850589000, 0.6269287000, 1.4808509000", \ - "0.0647131000, 0.0735981000, 0.0955189000, 0.1498205000, 0.2854102000, 0.6272066000, 1.4849604000", \ - "0.0619793000, 0.0710637000, 0.0936559000, 0.1495553000, 0.2853681000, 0.6246950000, 1.4852367000", \ - "0.0537970000, 0.0628799000, 0.0855840000, 0.1431683000, 0.2805938000, 0.6247683000, 1.4816494000", \ - "0.0522774000, 0.0603811000, 0.0817334000, 0.1359679000, 0.2739539000, 0.6165972000, 1.4789325000", \ - "0.0611450000, 0.0688738000, 0.0878866000, 0.1363977000, 0.2708009000, 0.6127246000, 1.4715204000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0294322000, 0.0321949000, 0.0388289000, 0.0543131000, 0.0911406000, 0.1809899000, 0.4050461000", \ - "0.0332804000, 0.0360554000, 0.0427348000, 0.0583451000, 0.0951256000, 0.1850991000, 0.4098038000", \ - "0.0437864000, 0.0463586000, 0.0527086000, 0.0681852000, 0.1049871000, 0.1949351000, 0.4192733000", \ - "0.0613941000, 0.0647955000, 0.0732418000, 0.0917326000, 0.1283687000, 0.2182853000, 0.4425062000", \ - "0.0817803000, 0.0872906000, 0.0995910000, 0.1265836000, 0.1785243000, 0.2738434000, 0.4968396000", \ - "0.0972607000, 0.1056981000, 0.1242752000, 0.1656531000, 0.2428085000, 0.3835595000, 0.6258345000", \ - "0.0858433000, 0.0967255000, 0.1271787000, 0.1888504000, 0.3078823000, 0.5211013000, 0.8797424000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0746095000, 0.0815395000, 0.0980231000, 0.1379717000, 0.2351741000, 0.4801485000, 1.0952894000", \ - "0.0785530000, 0.0853667000, 0.1020841000, 0.1422198000, 0.2408163000, 0.4869321000, 1.1021585000", \ - "0.0906585000, 0.0972720000, 0.1136060000, 0.1541478000, 0.2529330000, 0.4992180000, 1.1181956000", \ - "0.1181814000, 0.1249159000, 0.1410777000, 0.1807511000, 0.2794417000, 0.5262002000, 1.1458124000", \ - "0.1659615000, 0.1745215000, 0.1946022000, 0.2395122000, 0.3387854000, 0.5855649000, 1.2051118000", \ - "0.2389627000, 0.2525016000, 0.2826532000, 0.3453134000, 0.4691851000, 0.7211671000, 1.3406238000", \ - "0.3475268000, 0.3697420000, 0.4182347000, 0.5170517000, 0.6978846000, 1.0215699000, 1.6593122000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0281889000, 0.0310405000, 0.0383098000, 0.0571027000, 0.1046458000, 0.2255703000, 0.5326776000", \ - "0.0271840000, 0.0303379000, 0.0379941000, 0.0568930000, 0.1046141000, 0.2258325000, 0.5325913000", \ - "0.0284967000, 0.0312032000, 0.0380897000, 0.0562595000, 0.1044868000, 0.2257337000, 0.5326409000", \ - "0.0391303000, 0.0422909000, 0.0497402000, 0.0647899000, 0.1071060000, 0.2257027000, 0.5332900000", \ - "0.0596949000, 0.0642601000, 0.0741989000, 0.0950827000, 0.1373584000, 0.2368719000, 0.5319141000", \ - "0.0972975000, 0.1037658000, 0.1186631000, 0.1490270000, 0.2072445000, 0.3125950000, 0.5606867000", \ - "0.1617579000, 0.1741475000, 0.1973022000, 0.2454596000, 0.3285548000, 0.4767016000, 0.7385274000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012632100, 0.0031913700, 0.0080627200, 0.0203697000, 0.0514623000, 0.1300150000"); - values("0.0450999000, 0.0534501000, 0.0749979000, 0.1285084000, 0.2628362000, 0.5998981000, 1.4500487000", \ - "0.0453270000, 0.0537701000, 0.0747860000, 0.1283688000, 0.2630452000, 0.5999876000, 1.4533503000", \ - "0.0454338000, 0.0539026000, 0.0750903000, 0.1284993000, 0.2630374000, 0.6012968000, 1.4521058000", \ - "0.0476749000, 0.0555512000, 0.0760392000, 0.1286077000, 0.2625937000, 0.6001993000, 1.4533110000", \ - "0.0644221000, 0.0724955000, 0.0917503000, 0.1382157000, 0.2645450000, 0.6000186000, 1.4541084000", \ - "0.1037109000, 0.1126797000, 0.1346154000, 0.1850346000, 0.3011596000, 0.6073854000, 1.4495093000", \ - "0.1862411000, 0.1978767000, 0.2272521000, 0.2880284000, 0.4203579000, 0.7001883000, 1.4648243000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor2_4") { - leakage_power () { - value : 0.0071544000; - when : "!A&B"; - } - leakage_power () { - value : 0.0107585000; - when : "!A&!B"; - } - leakage_power () { - value : 0.0056040000; - when : "A&B"; - } - leakage_power () { - value : 0.0060047000; - when : "A&!B"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__xor2"; - cell_leakage_power : 0.0073803710; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0173590000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0166090000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0181100000; - } - pin ("B") { - capacitance : 0.0150830000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0144120000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0157550000; - } - pin ("X") { - direction : "output"; - function : "(A&!B) | (!A&B)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("-0.009353200, -0.010762300, -0.014632000, -0.025274800, -0.054785000, -0.136565300, -0.362923600", \ - "-0.010240800, -0.011609600, -0.015454600, -0.026091800, -0.055569400, -0.137404700, -0.363764100", \ - "-0.011272300, -0.012630100, -0.016426900, -0.026952900, -0.056280500, -0.138080900, -0.364624900", \ - "-0.012300700, -0.013629200, -0.017353500, -0.027797400, -0.057036300, -0.138586100, -0.364914600", \ - "-0.012574600, -0.013950200, -0.017842500, -0.028217400, -0.057313200, -0.138687800, -0.364837300", \ - "-0.011353300, -0.012758900, -0.016668300, -0.027355600, -0.057695800, -0.139744700, -0.365479200", \ - "-0.008667900, -0.010139100, -0.014189800, -0.025209600, -0.055645000, -0.138132000, -0.365525200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0738198000, 0.0753531000, 0.0792946000, 0.0901744000, 0.1199423000, 0.2012191000, 0.4251799000", \ - "0.0731748000, 0.0746199000, 0.0786184000, 0.0896336000, 0.1194524000, 0.2010247000, 0.4249036000", \ - "0.0722850000, 0.0738445000, 0.0778100000, 0.0889312000, 0.1190668000, 0.2008785000, 0.4248206000", \ - "0.0718295000, 0.0732238000, 0.0771736000, 0.0881723000, 0.1182779000, 0.2002234000, 0.4244880000", \ - "0.0711848000, 0.0725912000, 0.0765118000, 0.0873854000, 0.1172710000, 0.1993973000, 0.4238938000", \ - "0.0710156000, 0.0724653000, 0.0764309000, 0.0874079000, 0.1173448000, 0.1992413000, 0.4235285000", \ - "0.0701391000, 0.0715192000, 0.0753463000, 0.0858004000, 0.1175061000, 0.1994338000, 0.4239562000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("-0.002064100, -0.003456100, -0.007309900, -0.017992200, -0.047502500, -0.129515200, -0.356010400", \ - "-0.002647800, -0.004026400, -0.007846600, -0.018449000, -0.047976600, -0.129872100, -0.356420700", \ - "-0.003471100, -0.004833300, -0.008601100, -0.019061000, -0.048440200, -0.130265800, -0.356612300", \ - "-0.004352900, -0.005654600, -0.009397200, -0.019845000, -0.049035100, -0.130568200, -0.356970700", \ - "-0.004318000, -0.005718400, -0.009493400, -0.020080200, -0.049320500, -0.130688300, -0.356844400", \ - "-0.002391200, -0.003845500, -0.007817000, -0.018645900, -0.049286200, -0.131171300, -0.357154100", \ - "0.0029354000, 0.0014294000, -0.002768600, -0.014040800, -0.044844200, -0.128155300, -0.356244200"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0013786650, 0.0038014330, 0.0104818100, 0.0289017900, 0.0796917700, 0.2197365000"); - values("0.0519886000, 0.0535976000, 0.0578817000, 0.0690903000, 0.0990387000, 0.1810936000, 0.4072389000", \ - "0.0511053000, 0.0526723000, 0.0570279000, 0.0683969000, 0.0987314000, 0.1806366000, 0.4051989000", \ - "0.0501969000, 0.0517430000, 0.0559635000, 0.0673814000, 0.0980315000, 0.1802728000, 0.4069269000", \ - "0.0496505000, 0.0511488000, 0.0552254000, 0.0664763000, 0.0969992000, 0.1794975000, 0.4065757000", \ - "0.0489505000, 0.0504705000, 0.0544899000, 0.0654526000, 0.0956693000, 0.1789110000, 0.4056357000", \ - "0.0490106000, 0.0504402000, 0.0544267000, 0.0654591000, 0.0957292000, 0.1779419000, 0.4044345000", \ - "0.0493743000, 0.0506929000, 0.0543723000, 0.0649597000, 0.0956659000, 0.1780672000, 0.4040065000"); - } - } - max_capacitance : 0.2197360000; - max_transition : 1.4976190000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.1498213000, 0.1521022000, 0.1579420000, 0.1706484000, 0.1970509000, 0.2525050000, 0.3819992000", \ - "0.1534217000, 0.1557036000, 0.1614396000, 0.1743502000, 0.2006676000, 0.2561700000, 0.3856208000", \ - "0.1647692000, 0.1671180000, 0.1728084000, 0.1857164000, 0.2121356000, 0.2676604000, 0.3971745000", \ - "0.1917592000, 0.1940444000, 0.1996949000, 0.2124735000, 0.2389546000, 0.2946570000, 0.4242198000", \ - "0.2489901000, 0.2513319000, 0.2570763000, 0.2699971000, 0.2970482000, 0.3529857000, 0.4825390000", \ - "0.3493355000, 0.3519830000, 0.3585081000, 0.3732342000, 0.4035063000, 0.4634976000, 0.5967257000", \ - "0.5210429000, 0.5242347000, 0.5321462000, 0.5498254000, 0.5856142000, 0.6531658000, 0.7920983000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0824702000, 0.0871205000, 0.0999131000, 0.1338755000, 0.2240030000, 0.4655699000, 1.1281149000", \ - "0.0874779000, 0.0920609000, 0.1048119000, 0.1390157000, 0.2289731000, 0.4702864000, 1.1320492000", \ - "0.0981387000, 0.1029224000, 0.1155759000, 0.1494399000, 0.2399153000, 0.4819025000, 1.1451019000", \ - "0.1172658000, 0.1218137000, 0.1340927000, 0.1675947000, 0.2578120000, 0.5002633000, 1.1628895000", \ - "0.1412810000, 0.1457323000, 0.1579043000, 0.1911819000, 0.2805902000, 0.5237397000, 1.1871472000", \ - "0.1650427000, 0.1694110000, 0.1813255000, 0.2141437000, 0.3030956000, 0.5453783000, 1.2113351000", \ - "0.1650627000, 0.1701666000, 0.1825782000, 0.2148724000, 0.3027608000, 0.5447091000, 1.2088036000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0258631000, 0.0272958000, 0.0313648000, 0.0411783000, 0.0647598000, 0.1230203000, 0.2829630000", \ - "0.0256963000, 0.0271844000, 0.0315704000, 0.0411118000, 0.0647809000, 0.1230484000, 0.2835780000", \ - "0.0258039000, 0.0273211000, 0.0312231000, 0.0410294000, 0.0645500000, 0.1230651000, 0.2836416000", \ - "0.0260212000, 0.0275553000, 0.0313922000, 0.0413212000, 0.0649676000, 0.1230437000, 0.2837963000", \ - "0.0275022000, 0.0292852000, 0.0327963000, 0.0426531000, 0.0658314000, 0.1234046000, 0.2838002000", \ - "0.0331190000, 0.0349436000, 0.0391283000, 0.0493380000, 0.0727733000, 0.1308584000, 0.2875061000", \ - "0.0455791000, 0.0474508000, 0.0522486000, 0.0630046000, 0.0882908000, 0.1446539000, 0.2969336000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0545477000, 0.0604694000, 0.0769636000, 0.1211413000, 0.2415684000, 0.5726916000, 1.4837939000", \ - "0.0545630000, 0.0605890000, 0.0768845000, 0.1213245000, 0.2417088000, 0.5729234000, 1.4837653000", \ - "0.0545522000, 0.0605333000, 0.0766708000, 0.1213620000, 0.2420048000, 0.5720606000, 1.4826771000", \ - "0.0544345000, 0.0603335000, 0.0767580000, 0.1211477000, 0.2416003000, 0.5729405000, 1.4834963000", \ - "0.0544386000, 0.0602949000, 0.0761584000, 0.1210499000, 0.2410216000, 0.5727535000, 1.4836791000", \ - "0.0571354000, 0.0624336000, 0.0778807000, 0.1210058000, 0.2418170000, 0.5696867000, 1.4809503000", \ - "0.0658208000, 0.0709332000, 0.0845831000, 0.1240170000, 0.2422272000, 0.5753099000, 1.4770219000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0436636000, 0.0453758000, 0.0500607000, 0.0622142000, 0.0935156000, 0.1764752000, 0.4019771000", \ - "0.0474098000, 0.0492156000, 0.0538442000, 0.0660680000, 0.0973631000, 0.1804029000, 0.4067191000", \ - "0.0558684000, 0.0576227000, 0.0623161000, 0.0745588000, 0.1060547000, 0.1891348000, 0.4148759000", \ - "0.0716920000, 0.0738656000, 0.0795040000, 0.0928811000, 0.1253473000, 0.2089834000, 0.4350223000", \ - "0.0934183000, 0.0964121000, 0.1038103000, 0.1220940000, 0.1633954000, 0.2538585000, 0.4806054000", \ - "0.1102166000, 0.1148162000, 0.1264197000, 0.1548898000, 0.2165235000, 0.3371814000, 0.5852526000", \ - "0.0965449000, 0.1035638000, 0.1216761000, 0.1659232000, 0.2629996000, 0.4488046000, 0.7811597000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.1152663000, 0.1197115000, 0.1313149000, 0.1631730000, 0.2484311000, 0.4815269000, 1.1207800000", \ - "0.1186809000, 0.1230035000, 0.1350982000, 0.1670509000, 0.2528935000, 0.4858588000, 1.1268465000", \ - "0.1299064000, 0.1346329000, 0.1461559000, 0.1787279000, 0.2649009000, 0.4987368000, 1.1391225000", \ - "0.1576167000, 0.1618373000, 0.1735779000, 0.2056609000, 0.2920834000, 0.5261697000, 1.1680041000", \ - "0.2135563000, 0.2185918000, 0.2316387000, 0.2650153000, 0.3510895000, 0.5853523000, 1.2264606000", \ - "0.3105179000, 0.3172884000, 0.3343643000, 0.3780825000, 0.4819104000, 0.7215010000, 1.3631631000", \ - "0.4673313000, 0.4784170000, 0.5059216000, 0.5718557000, 0.7176837000, 1.0207096000, 1.6803030000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0306255000, 0.0326024000, 0.0378873000, 0.0527912000, 0.0940997000, 0.2090309000, 0.5265505000", \ - "0.0305594000, 0.0324557000, 0.0378828000, 0.0527709000, 0.0940672000, 0.2090063000, 0.5275455000", \ - "0.0306991000, 0.0326035000, 0.0377471000, 0.0525482000, 0.0939461000, 0.2089878000, 0.5271354000", \ - "0.0372694000, 0.0391281000, 0.0442891000, 0.0573073000, 0.0956952000, 0.2088595000, 0.5270412000", \ - "0.0547171000, 0.0568965000, 0.0624743000, 0.0775606000, 0.1147396000, 0.2168991000, 0.5271663000", \ - "0.0898452000, 0.0929725000, 0.1005826000, 0.1199536000, 0.1638825000, 0.2662955000, 0.5465849000", \ - "0.1543681000, 0.1592050000, 0.1713063000, 0.1991683000, 0.2610707000, 0.3866281000, 0.6630076000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0759070000, 0.0815424000, 0.0969157000, 0.1392374000, 0.2551032000, 0.5748853000, 1.4477172000", \ - "0.0758997000, 0.0814693000, 0.0970385000, 0.1394350000, 0.2552114000, 0.5728129000, 1.4494465000", \ - "0.0759521000, 0.0815833000, 0.0969367000, 0.1392081000, 0.2553012000, 0.5729696000, 1.4523986000", \ - "0.0763891000, 0.0818078000, 0.0972177000, 0.1394148000, 0.2551341000, 0.5731693000, 1.4486934000", \ - "0.0891667000, 0.0940859000, 0.1075588000, 0.1461725000, 0.2565225000, 0.5730347000, 1.4510028000", \ - "0.1258456000, 0.1314789000, 0.1469706000, 0.1871109000, 0.2883875000, 0.5812781000, 1.4505315000", \ - "0.2082668000, 0.2155849000, 0.2345399000, 0.2825965000, 0.3955398000, 0.6695067000, 1.4652712000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.1234675000, 0.1257397000, 0.1314267000, 0.1441660000, 0.1704285000, 0.2255801000, 0.3551103000", \ - "0.1257263000, 0.1280011000, 0.1336729000, 0.1464812000, 0.1726047000, 0.2281072000, 0.3576422000", \ - "0.1357807000, 0.1380280000, 0.1436779000, 0.1561082000, 0.1826469000, 0.2380935000, 0.3677224000", \ - "0.1633535000, 0.1655912000, 0.1712241000, 0.1839759000, 0.2104805000, 0.2661422000, 0.3956312000", \ - "0.2281192000, 0.2304337000, 0.2361473000, 0.2490715000, 0.2760102000, 0.3319250000, 0.4617683000", \ - "0.3382702000, 0.3410712000, 0.3480520000, 0.3630874000, 0.3926597000, 0.4516459000, 0.5842897000", \ - "0.5182355000, 0.5217422000, 0.5303887000, 0.5492988000, 0.5854496000, 0.6497775000, 0.7852521000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.1048461000, 0.1090026000, 0.1202696000, 0.1508533000, 0.2326286000, 0.4605297000, 1.0983631000", \ - "0.1089455000, 0.1132897000, 0.1248770000, 0.1553579000, 0.2377169000, 0.4659305000, 1.1020401000", \ - "0.1158189000, 0.1200469000, 0.1314675000, 0.1626685000, 0.2467387000, 0.4762303000, 1.1137002000", \ - "0.1271718000, 0.1314447000, 0.1432418000, 0.1750644000, 0.2602975000, 0.4919463000, 1.1289183000", \ - "0.1421417000, 0.1466329000, 0.1587245000, 0.1908896000, 0.2762768000, 0.5097093000, 1.1477884000", \ - "0.1528475000, 0.1572159000, 0.1692436000, 0.2012987000, 0.2877989000, 0.5225921000, 1.1631662000", \ - "0.1370997000, 0.1420376000, 0.1546755000, 0.1862847000, 0.2713418000, 0.5062086000, 1.1492168000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0258575000, 0.0273784000, 0.0314467000, 0.0412008000, 0.0649258000, 0.1233208000, 0.2832658000", \ - "0.0258729000, 0.0274055000, 0.0312688000, 0.0410916000, 0.0651922000, 0.1232537000, 0.2836712000", \ - "0.0259981000, 0.0276253000, 0.0314951000, 0.0412600000, 0.0650397000, 0.1233299000, 0.2833123000", \ - "0.0259508000, 0.0274180000, 0.0316281000, 0.0412997000, 0.0649301000, 0.1232317000, 0.2834941000", \ - "0.0284681000, 0.0300106000, 0.0338473000, 0.0433398000, 0.0664746000, 0.1241942000, 0.2833802000", \ - "0.0388366000, 0.0399122000, 0.0435851000, 0.0523870000, 0.0742222000, 0.1301786000, 0.2887548000", \ - "0.0540890000, 0.0561388000, 0.0601321000, 0.0708778000, 0.0922304000, 0.1432362000, 0.2948055000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0752745000, 0.0809621000, 0.0964575000, 0.1392060000, 0.2550944000, 0.5730705000, 1.4496204000", \ - "0.0752050000, 0.0809003000, 0.0964027000, 0.1392268000, 0.2552087000, 0.5730071000, 1.4516470000", \ - "0.0749725000, 0.0807146000, 0.0962014000, 0.1390923000, 0.2551570000, 0.5730953000, 1.4500535000", \ - "0.0730962000, 0.0790643000, 0.0953033000, 0.1388982000, 0.2553379000, 0.5732365000, 1.4477179000", \ - "0.0634505000, 0.0694468000, 0.0857219000, 0.1310455000, 0.2496870000, 0.5735373000, 1.4495534000", \ - "0.0600312000, 0.0657071000, 0.0809499000, 0.1233164000, 0.2413889000, 0.5642955000, 1.4474065000", \ - "0.0678604000, 0.0728150000, 0.0866056000, 0.1252394000, 0.2386312000, 0.5594238000, 1.4371977000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0335696000, 0.0353220000, 0.0400256000, 0.0521365000, 0.0835456000, 0.1666051000, 0.3921810000", \ - "0.0372863000, 0.0390635000, 0.0437525000, 0.0559946000, 0.0874337000, 0.1704923000, 0.3960374000", \ - "0.0471907000, 0.0488378000, 0.0533741000, 0.0655429000, 0.0970316000, 0.1802304000, 0.4057602000", \ - "0.0654116000, 0.0676545000, 0.0737674000, 0.0881423000, 0.1203320000, 0.2030385000, 0.4290612000", \ - "0.0853982000, 0.0889033000, 0.0976499000, 0.1192638000, 0.1662422000, 0.2579159000, 0.4832924000", \ - "0.0984199000, 0.1037521000, 0.1173286000, 0.1492809000, 0.2212170000, 0.3586011000, 0.6101371000", \ - "0.0782870000, 0.0860682000, 0.1062972000, 0.1560700000, 0.2647008000, 0.4752755000, 0.8508662000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0850781000, 0.0899409000, 0.1027952000, 0.1360149000, 0.2242358000, 0.4678875000, 1.1311460000", \ - "0.0886134000, 0.0933029000, 0.1062009000, 0.1398852000, 0.2295681000, 0.4708945000, 1.1332277000", \ - "0.0999498000, 0.1045024000, 0.1171481000, 0.1511322000, 0.2411198000, 0.4838029000, 1.1488448000", \ - "0.1271868000, 0.1316210000, 0.1438976000, 0.1771318000, 0.2671072000, 0.5104442000, 1.1746953000", \ - "0.1760873000, 0.1820284000, 0.1968326000, 0.2342847000, 0.3243756000, 0.5695979000, 1.2362262000", \ - "0.2554318000, 0.2639361000, 0.2866622000, 0.3366414000, 0.4498133000, 0.7008774000, 1.3679664000", \ - "0.3808998000, 0.3945671000, 0.4288706000, 0.5088539000, 0.6710317000, 0.9935092000, 1.6783878000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0309668000, 0.0327628000, 0.0380972000, 0.0529457000, 0.0941547000, 0.2089584000, 0.5270855000", \ - "0.0302730000, 0.0322728000, 0.0377722000, 0.0527265000, 0.0940481000, 0.2088934000, 0.5268767000", \ - "0.0309543000, 0.0327341000, 0.0378132000, 0.0522565000, 0.0938198000, 0.2088570000, 0.5272688000", \ - "0.0413029000, 0.0433314000, 0.0487315000, 0.0615735000, 0.0973744000, 0.2087784000, 0.5270357000", \ - "0.0626560000, 0.0653913000, 0.0731504000, 0.0897430000, 0.1288506000, 0.2224151000, 0.5268013000", \ - "0.1012147000, 0.1055305000, 0.1163309000, 0.1414359000, 0.1938118000, 0.2997774000, 0.5583131000", \ - "0.1664303000, 0.1732680000, 0.1904969000, 0.2303589000, 0.3080212000, 0.4561075000, 0.7360311000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0013786600, 0.0038014300, 0.0104818000, 0.0289018000, 0.0796918000, 0.2197360000"); - values("0.0556082000, 0.0614255000, 0.0774347000, 0.1211863000, 0.2412494000, 0.5733722000, 1.4860994000", \ - "0.0554051000, 0.0614012000, 0.0774506000, 0.1207148000, 0.2412002000, 0.5710328000, 1.4839330000", \ - "0.0557944000, 0.0615850000, 0.0772878000, 0.1212796000, 0.2414769000, 0.5705666000, 1.4904959000", \ - "0.0571563000, 0.0627295000, 0.0781564000, 0.1216595000, 0.2415536000, 0.5706252000, 1.4912858000", \ - "0.0738758000, 0.0792944000, 0.0933395000, 0.1314809000, 0.2439562000, 0.5744571000, 1.4866004000", \ - "0.1113906000, 0.1170693000, 0.1336293000, 0.1749030000, 0.2802974000, 0.5800641000, 1.4839238000", \ - "0.1937913000, 0.2011665000, 0.2219989000, 0.2710132000, 0.3889577000, 0.6707701000, 1.4976191000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor3_1") { - leakage_power () { - value : 0.0095998000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0116656000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0237432000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0185233000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0119131000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0066932000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0187710000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0208368000; - when : "A&B&!C"; - } - area : 23.772800000; - cell_footprint : "sky130_fd_sc_hd__xor3"; - cell_leakage_power : 0.0152182600; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024410000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022990000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025840000; - } - pin ("B") { - capacitance : 0.0052800000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051240000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054350000; - } - pin ("C") { - capacitance : 0.0034850000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033700000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036000000; - } - pin ("X") { - direction : "output"; - function : "(A&!B&!C) | (!A&B&!C) | (!A&!B&C) | (A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0392789000, 0.0382701000, 0.0358285000, 0.0288948000, 0.0084779000, -0.048531500, -0.198555700", \ - "0.0391785000, 0.0381702000, 0.0357130000, 0.0287860000, 0.0083681000, -0.048635200, -0.198656200", \ - "0.0390086000, 0.0379992000, 0.0355476000, 0.0286178000, 0.0081991000, -0.048803000, -0.198825700", \ - "0.0387158000, 0.0376886000, 0.0352324000, 0.0283643000, 0.0078868000, -0.049102600, -0.199123600", \ - "0.0385553000, 0.0375318000, 0.0350733000, 0.0281963000, 0.0077269000, -0.049269000, -0.199292800", \ - "0.0385821000, 0.0375521000, 0.0351043000, 0.0281548000, 0.0077477000, -0.049256300, -0.199275600", \ - "0.0447465000, 0.0433977000, 0.0400026000, 0.0314111000, 0.0091734000, -0.048540100, -0.198537800"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0492808000, 0.0508091000, 0.0546855000, 0.0637889000, 0.0861527000, 0.1436975000, 0.2927508000", \ - "0.0491015000, 0.0506028000, 0.0545072000, 0.0636098000, 0.0859679000, 0.1435268000, 0.2925472000", \ - "0.0488362000, 0.0503500000, 0.0542636000, 0.0633410000, 0.0857320000, 0.1437882000, 0.2922279000", \ - "0.0486415000, 0.0501552000, 0.0540658000, 0.0631481000, 0.0855090000, 0.1430601000, 0.2921352000", \ - "0.0484191000, 0.0499461000, 0.0538105000, 0.0629016000, 0.0853099000, 0.1427562000, 0.2919419000", \ - "0.0487052000, 0.0502654000, 0.0541627000, 0.0632769000, 0.0856398000, 0.1431769000, 0.2921748000", \ - "0.0515830000, 0.0529069000, 0.0563315000, 0.0649841000, 0.0879357000, 0.1450084000, 0.2942690000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0247445000, 0.0237315000, 0.0213186000, 0.0143732000, -0.006055500, -0.063116800, -0.213140300", \ - "0.0243409000, 0.0233481000, 0.0209082000, 0.0139968000, -0.006438000, -0.063507200, -0.213530800", \ - "0.0238637000, 0.0228525000, 0.0204490000, 0.0135003000, -0.006921800, -0.063979900, -0.214009600", \ - "0.0233275000, 0.0223336000, 0.0199392000, 0.0130327000, -0.007417500, -0.064490700, -0.214512200", \ - "0.0235293000, 0.0225567000, 0.0201369000, 0.0131850000, -0.007267700, -0.064322000, -0.214329300", \ - "0.0256859000, 0.0243164000, 0.0215920000, 0.0145444000, -0.006004300, -0.063058100, -0.213055600", \ - "0.0351985000, 0.0338654000, 0.0305137000, 0.0219453000, -0.000242800, -0.058385100, -0.208403300"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0454857000, 0.0470140000, 0.0508919000, 0.0599808000, 0.0823127000, 0.1398432000, 0.2888106000", \ - "0.0450563000, 0.0465844000, 0.0504582000, 0.0595509000, 0.0818885000, 0.1394214000, 0.2884697000", \ - "0.0446270000, 0.0461354000, 0.0500222000, 0.0590947000, 0.0814318000, 0.1389459000, 0.2880930000", \ - "0.0443431000, 0.0458681000, 0.0497411000, 0.0588171000, 0.0811506000, 0.1386885000, 0.2877619000", \ - "0.0444455000, 0.0459623000, 0.0498546000, 0.0589249000, 0.0812844000, 0.1387560000, 0.2881574000", \ - "0.0459193000, 0.0476681000, 0.0518527000, 0.0602266000, 0.0825701000, 0.1400887000, 0.2889572000", \ - "0.0500262000, 0.0513410000, 0.0547798000, 0.0635765000, 0.0862603000, 0.1440582000, 0.2923885000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0100974000, 0.0091266000, 0.0068097000, 3.5712722e-05, -0.020311900, -0.077353800, -0.227406400", \ - "0.0099920000, 0.0090247000, 0.0067031000, -8.827233e-05, -0.020433800, -0.077458800, -0.227484100", \ - "0.0098203000, 0.0088623000, 0.0065357000, -0.000256500, -0.020610200, -0.077614400, -0.227631900", \ - "0.0096854000, 0.0086948000, 0.0064138000, -0.000355100, -0.020762500, -0.077720800, -0.227711800", \ - "0.0099452000, 0.0090418000, 0.0066983000, -0.000168900, -0.020580700, -0.077527300, -0.227464500", \ - "0.0142562000, 0.0129809000, 0.0097091000, 0.0011226000, -0.019724300, -0.076752200, -0.226727200", \ - "0.0190153000, 0.0178816000, 0.0147097000, 0.0061807000, -0.016109800, -0.074115100, -0.224430300"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0012952060, 0.0033551190, 0.0086911440, 0.0225136500, 0.0583196500, 0.1510720000"); - values("0.0254934000, 0.0269316000, 0.0306161000, 0.0395283000, 0.0618932000, 0.1196185000, 0.2674525000", \ - "0.0252534000, 0.0267002000, 0.0303489000, 0.0392732000, 0.0616480000, 0.1192758000, 0.2686896000", \ - "0.0251063000, 0.0265285000, 0.0302108000, 0.0391443000, 0.0614938000, 0.1192046000, 0.2683147000", \ - "0.0251774000, 0.0266105000, 0.0302797000, 0.0392134000, 0.0615949000, 0.1191432000, 0.2683155000", \ - "0.0255795000, 0.0269782000, 0.0306721000, 0.0396025000, 0.0619702000, 0.1196150000, 0.2675263000", \ - "0.0270048000, 0.0282863000, 0.0320316000, 0.0410957000, 0.0632836000, 0.1209844000, 0.2685984000", \ - "0.0293137000, 0.0305838000, 0.0340058000, 0.0427982000, 0.0650712000, 0.1227911000, 0.2713906000"); - } - } - max_capacitance : 0.1510720000; - max_transition : 1.4974980000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.3057679000, 0.3178683000, 0.3413997000, 0.3834241000, 0.4585897000, 0.6046020000, 0.9281851000", \ - "0.3110815000, 0.3231713000, 0.3467546000, 0.3887242000, 0.4638819000, 0.6098630000, 0.9334272000", \ - "0.3237826000, 0.3358175000, 0.3594261000, 0.4013871000, 0.4766071000, 0.6225725000, 0.9462797000", \ - "0.3551027000, 0.3672445000, 0.3907919000, 0.4327401000, 0.5079523000, 0.6539829000, 0.9773898000", \ - "0.4295820000, 0.4415989000, 0.4651082000, 0.5071480000, 0.5823090000, 0.7283273000, 1.0521032000", \ - "0.5873682000, 0.5999541000, 0.6240415000, 0.6666855000, 0.7422647000, 0.8886473000, 1.2125188000", \ - "0.8613682000, 0.8766047000, 0.9050029000, 0.9526648000, 1.0337913000, 1.1856333000, 1.5123156000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1755266000, 0.1851445000, 0.2061075000, 0.2508902000, 0.3516971000, 0.5992453000, 1.2385453000", \ - "0.1801906000, 0.1898390000, 0.2108223000, 0.2555154000, 0.3565366000, 0.6044213000, 1.2427206000", \ - "0.1912442000, 0.2008081000, 0.2218022000, 0.2664833000, 0.3675122000, 0.6154228000, 1.2543623000", \ - "0.2158538000, 0.2254659000, 0.2464770000, 0.2911610000, 0.3921607000, 0.6401014000, 1.2791060000", \ - "0.2646865000, 0.2743606000, 0.2953628000, 0.3401060000, 0.4408032000, 0.6884859000, 1.3276296000", \ - "0.3419942000, 0.3525545000, 0.3750393000, 0.4216314000, 0.5239033000, 0.7720690000, 1.4145132000", \ - "0.4385661000, 0.4515362000, 0.4781792000, 0.5304778000, 0.6368432000, 0.8860390000, 1.5233241000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0627180000, 0.0665185000, 0.0766205000, 0.1011350000, 0.1630815000, 0.3121836000, 0.7047147000", \ - "0.0623170000, 0.0666369000, 0.0768163000, 0.1014161000, 0.1630112000, 0.3104167000, 0.7046075000", \ - "0.0622696000, 0.0667396000, 0.0766708000, 0.1013953000, 0.1626791000, 0.3121440000, 0.7036173000", \ - "0.0624076000, 0.0671466000, 0.0770705000, 0.1025512000, 0.1619944000, 0.3109779000, 0.7039230000", \ - "0.0624291000, 0.0669007000, 0.0769119000, 0.1018671000, 0.1628519000, 0.3121412000, 0.7030468000", \ - "0.0696637000, 0.0729728000, 0.0812913000, 0.1045175000, 0.1642875000, 0.3114101000, 0.7059529000", \ - "0.1022027000, 0.1013144000, 0.1035813000, 0.1206429000, 0.1776169000, 0.3191836000, 0.7087503000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0344760000, 0.0429099000, 0.0633319000, 0.1129249000, 0.2414962000, 0.5854137000, 1.4929676000", \ - "0.0344461000, 0.0430827000, 0.0633891000, 0.1128933000, 0.2410656000, 0.5840727000, 1.4974982000", \ - "0.0344341000, 0.0430335000, 0.0633981000, 0.1129505000, 0.2412919000, 0.5847007000, 1.4942148000", \ - "0.0344106000, 0.0431348000, 0.0633733000, 0.1129459000, 0.2413168000, 0.5846528000, 1.4935894000", \ - "0.0349703000, 0.0434508000, 0.0638307000, 0.1130668000, 0.2416542000, 0.5854089000, 1.4874894000", \ - "0.0389449000, 0.0480105000, 0.0683839000, 0.1175476000, 0.2436889000, 0.5841622000, 1.4928193000", \ - "0.0497092000, 0.0598502000, 0.0810337000, 0.1289757000, 0.2502900000, 0.5867082000, 1.4879659000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.3428200000, 0.3544492000, 0.3777112000, 0.4195088000, 0.4956295000, 0.6430128000, 0.9677735000", \ - "0.3474707000, 0.3591759000, 0.3822762000, 0.4241962000, 0.5001464000, 0.6476826000, 0.9725976000", \ - "0.3587518000, 0.3704412000, 0.3935329000, 0.4354508000, 0.5114076000, 0.6589334000, 0.9838363000", \ - "0.3849006000, 0.3966337000, 0.4197506000, 0.4616838000, 0.5376219000, 0.6851716000, 1.0101281000", \ - "0.4322123000, 0.4439073000, 0.4669980000, 0.5089121000, 0.5848771000, 0.7324262000, 1.0573639000", \ - "0.4991447000, 0.5108344000, 0.5339968000, 0.5756831000, 0.6518595000, 0.7993975000, 1.1240222000", \ - "0.5742435000, 0.5858989000, 0.6092597000, 0.6510391000, 0.7272609000, 0.8748106000, 1.1994867000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.3193405000, 0.3298359000, 0.3519925000, 0.3984070000, 0.5000321000, 0.7483795000, 1.3867172000", \ - "0.3245869000, 0.3350615000, 0.3572194000, 0.4036266000, 0.5052373000, 0.7535405000, 1.3916140000", \ - "0.3369765000, 0.3474592000, 0.3696642000, 0.4160857000, 0.5177229000, 0.7661096000, 1.4044674000", \ - "0.3687007000, 0.3791940000, 0.4013571000, 0.4477726000, 0.5494012000, 0.7977540000, 1.4362609000", \ - "0.4429414000, 0.4533453000, 0.4756991000, 0.5220137000, 0.6237290000, 0.8719802000, 1.5082193000", \ - "0.5867801000, 0.5972132000, 0.6195660000, 0.6661043000, 0.7677738000, 1.0160733000, 1.6541497000", \ - "0.8225522000, 0.8332419000, 0.8559071000, 0.9027914000, 1.0049381000, 1.2525297000, 1.8893072000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0571112000, 0.0620982000, 0.0741339000, 0.1009553000, 0.1645605000, 0.3146445000, 0.7078798000", \ - "0.0570047000, 0.0624773000, 0.0747112000, 0.1010293000, 0.1645879000, 0.3139524000, 0.7085484000", \ - "0.0570537000, 0.0625179000, 0.0744141000, 0.1010165000, 0.1645983000, 0.3139100000, 0.7085570000", \ - "0.0568306000, 0.0623817000, 0.0744675000, 0.1022908000, 0.1643805000, 0.3141588000, 0.7084127000", \ - "0.0570298000, 0.0624861000, 0.0747023000, 0.1022157000, 0.1646021000, 0.3139849000, 0.7084798000", \ - "0.0568410000, 0.0628032000, 0.0743107000, 0.1016304000, 0.1645021000, 0.3145758000, 0.7066892000", \ - "0.0576255000, 0.0625432000, 0.0746147000, 0.1014493000, 0.1647418000, 0.3147577000, 0.7045357000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0379578000, 0.0469316000, 0.0672892000, 0.1163807000, 0.2432284000, 0.5872300000, 1.4913943000", \ - "0.0379966000, 0.0469144000, 0.0673590000, 0.1163590000, 0.2432471000, 0.5872333000, 1.4924113000", \ - "0.0379562000, 0.0469067000, 0.0672577000, 0.1163805000, 0.2431551000, 0.5870532000, 1.4906230000", \ - "0.0379469000, 0.0469295000, 0.0672706000, 0.1163840000, 0.2432202000, 0.5872272000, 1.4907759000", \ - "0.0381652000, 0.0466794000, 0.0672808000, 0.1162416000, 0.2427506000, 0.5870620000, 1.4921991000", \ - "0.0382935000, 0.0471965000, 0.0676916000, 0.1166218000, 0.2433952000, 0.5871246000, 1.4927972000", \ - "0.0391175000, 0.0479077000, 0.0686214000, 0.1175366000, 0.2437483000, 0.5852495000, 1.4911553000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.2961416000, 0.3079659000, 0.3310242000, 0.3729113000, 0.4487566000, 0.5962566000, 0.9212906000", \ - "0.2995722000, 0.3114977000, 0.3344733000, 0.3764365000, 0.4521201000, 0.5997813000, 0.9247909000", \ - "0.3105849000, 0.3224245000, 0.3454733000, 0.3873747000, 0.4632171000, 0.6107352000, 0.9357646000", \ - "0.3391908000, 0.3508716000, 0.3740498000, 0.4158520000, 0.4917325000, 0.6392826000, 0.9643023000", \ - "0.4029503000, 0.4147971000, 0.4378120000, 0.4796748000, 0.5554725000, 0.7030313000, 1.0279408000", \ - "0.5363162000, 0.5482944000, 0.5724985000, 0.6153051000, 0.6921832000, 0.8401738000, 1.1653120000", \ - "0.7476280000, 0.7651714000, 0.7973606000, 0.8507317000, 0.9389544000, 1.0980248000, 1.4291228000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1530055000, 0.1624951000, 0.1833436000, 0.2278063000, 0.3278288000, 0.5747390000, 1.2134177000", \ - "0.1560866000, 0.1655708000, 0.1864196000, 0.2308829000, 0.3309112000, 0.5778332000, 1.2165360000", \ - "0.1654830000, 0.1750477000, 0.1958311000, 0.2401776000, 0.3403085000, 0.5875803000, 1.2255837000", \ - "0.1897840000, 0.1993103000, 0.2200389000, 0.2643283000, 0.3642622000, 0.6115212000, 1.2485524000", \ - "0.2396681000, 0.2493830000, 0.2704130000, 0.3147901000, 0.4147151000, 0.6620943000, 1.2987962000", \ - "0.3131335000, 0.3241277000, 0.3469920000, 0.3933122000, 0.4943880000, 0.7426101000, 1.3790126000", \ - "0.3948357000, 0.4090497000, 0.4373267000, 0.4892813000, 0.5931471000, 0.8419286000, 1.4789723000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0568018000, 0.0623072000, 0.0741014000, 0.1019314000, 0.1648958000, 0.3156216000, 0.7072376000", \ - "0.0567841000, 0.0622965000, 0.0739272000, 0.1014668000, 0.1646692000, 0.3158467000, 0.7071762000", \ - "0.0567963000, 0.0623110000, 0.0740860000, 0.1018645000, 0.1648913000, 0.3156472000, 0.7071234000", \ - "0.0565506000, 0.0622937000, 0.0742477000, 0.1022812000, 0.1648601000, 0.3153915000, 0.7075718000", \ - "0.0568241000, 0.0620672000, 0.0739444000, 0.1010484000, 0.1639650000, 0.3151621000, 0.7072304000", \ - "0.0633300000, 0.0693743000, 0.0797936000, 0.1054903000, 0.1665534000, 0.3143699000, 0.7074497000", \ - "0.1012038000, 0.1045571000, 0.1133657000, 0.1341297000, 0.1927532000, 0.3324829000, 0.7153099000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0342382000, 0.0427790000, 0.0627476000, 0.1120656000, 0.2406189000, 0.5854184000, 1.4948764000", \ - "0.0342331000, 0.0427734000, 0.0627423000, 0.1120668000, 0.2406133000, 0.5854168000, 1.4952828000", \ - "0.0341741000, 0.0427673000, 0.0628353000, 0.1120505000, 0.2401863000, 0.5842081000, 1.4880692000", \ - "0.0341934000, 0.0427586000, 0.0626451000, 0.1118905000, 0.2405330000, 0.5840423000, 1.4869174000", \ - "0.0353349000, 0.0438679000, 0.0638940000, 0.1126250000, 0.2407289000, 0.5844608000, 1.4877876000", \ - "0.0418570000, 0.0501470000, 0.0699513000, 0.1172038000, 0.2438746000, 0.5852488000, 1.4925677000", \ - "0.0566770000, 0.0661731000, 0.0853638000, 0.1292280000, 0.2482440000, 0.5885958000, 1.4881796000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.2488030000, 0.2608279000, 0.2839922000, 0.3259173000, 0.4017805000, 0.5485729000, 0.8723823000", \ - "0.2521842000, 0.2642151000, 0.2873471000, 0.3293552000, 0.4051511000, 0.5519396000, 0.8758180000", \ - "0.2604116000, 0.2724336000, 0.2956333000, 0.3375443000, 0.4134216000, 0.5601939000, 0.8839554000", \ - "0.2801757000, 0.2921325000, 0.3153661000, 0.3573357000, 0.4331333000, 0.5799021000, 0.9036929000", \ - "0.3355563000, 0.3473472000, 0.3704224000, 0.4123227000, 0.4877097000, 0.6346835000, 0.9588493000", \ - "0.4039637000, 0.4155538000, 0.4384914000, 0.4799701000, 0.5549383000, 0.7013429000, 1.0252870000", \ - "0.4605084000, 0.4720044000, 0.4949708000, 0.5367126000, 0.6121790000, 0.7588465000, 1.0820141000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.2282485000, 0.2387457000, 0.2610687000, 0.3072907000, 0.4087360000, 0.6568295000, 1.2947519000", \ - "0.2316804000, 0.2422583000, 0.2644288000, 0.3107891000, 0.4122577000, 0.6604209000, 1.2988038000", \ - "0.2433094000, 0.2537974000, 0.2759412000, 0.3222889000, 0.4237674000, 0.6720318000, 1.3111872000", \ - "0.2728597000, 0.2834233000, 0.3056928000, 0.3518779000, 0.4533182000, 0.7014204000, 1.3399926000", \ - "0.3329261000, 0.3434041000, 0.3655903000, 0.4119711000, 0.5134957000, 0.7617807000, 1.4011369000", \ - "0.4200154000, 0.4303761000, 0.4527191000, 0.4986375000, 0.5997317000, 0.8482842000, 1.4875079000", \ - "0.5475292000, 0.5580947000, 0.5804249000, 0.6270802000, 0.7289909000, 0.9768873000, 1.6130041000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0579294000, 0.0629276000, 0.0743812000, 0.1008192000, 0.1633358000, 0.3125794000, 0.7047277000", \ - "0.0577110000, 0.0629659000, 0.0743411000, 0.1008251000, 0.1632529000, 0.3123113000, 0.7050452000", \ - "0.0579043000, 0.0628976000, 0.0743385000, 0.1007716000, 0.1633941000, 0.3127393000, 0.7044652000", \ - "0.0577930000, 0.0629827000, 0.0741732000, 0.1007549000, 0.1633250000, 0.3126231000, 0.7046330000", \ - "0.0562252000, 0.0615224000, 0.0734908000, 0.1004808000, 0.1636518000, 0.3138524000, 0.7039603000", \ - "0.0554224000, 0.0613489000, 0.0732770000, 0.1007736000, 0.1616167000, 0.3110105000, 0.7049954000", \ - "0.0562302000, 0.0614631000, 0.0737260000, 0.1002300000, 0.1618316000, 0.3111968000, 0.7013390000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0380233000, 0.0469801000, 0.0675005000, 0.1163495000, 0.2431326000, 0.5864063000, 1.4937538000", \ - "0.0379629000, 0.0469344000, 0.0674055000, 0.1163519000, 0.2432149000, 0.5867515000, 1.4926805000", \ - "0.0379315000, 0.0468873000, 0.0672150000, 0.1163203000, 0.2432153000, 0.5871768000, 1.4898327000", \ - "0.0378987000, 0.0468652000, 0.0673534000, 0.1162660000, 0.2431088000, 0.5866104000, 1.4923002000", \ - "0.0379182000, 0.0469415000, 0.0672297000, 0.1163723000, 0.2431791000, 0.5871684000, 1.4890197000", \ - "0.0381397000, 0.0471329000, 0.0675217000, 0.1158863000, 0.2425625000, 0.5863877000, 1.4888408000", \ - "0.0384341000, 0.0474058000, 0.0678115000, 0.1171269000, 0.2437093000, 0.5835356000, 1.4848072000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1404455000, 0.1500344000, 0.1698101000, 0.2076905000, 0.2799137000, 0.4247528000, 0.7481976000", \ - "0.1435074000, 0.1530893000, 0.1727508000, 0.2106806000, 0.2825916000, 0.4277086000, 0.7507462000", \ - "0.1529912000, 0.1624233000, 0.1818863000, 0.2196106000, 0.2914485000, 0.4364800000, 0.7597054000", \ - "0.1792235000, 0.1884131000, 0.2075261000, 0.2447311000, 0.3165095000, 0.4611234000, 0.7844418000", \ - "0.2448485000, 0.2535727000, 0.2719411000, 0.3080611000, 0.3789861000, 0.5232306000, 0.8463719000", \ - "0.3576012000, 0.3683649000, 0.3898203000, 0.4287335000, 0.5005994000, 0.6465501000, 0.9701164000", \ - "0.5285921000, 0.5420871000, 0.5691173000, 0.6171144000, 0.6968107000, 0.8444810000, 1.1731388000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0955482000, 0.1056517000, 0.1273565000, 0.1724812000, 0.2723531000, 0.5188929000, 1.1555003000", \ - "0.0995208000, 0.1096383000, 0.1312892000, 0.1764405000, 0.2762596000, 0.5222456000, 1.1639990000", \ - "0.1092907000, 0.1192920000, 0.1409534000, 0.1862103000, 0.2862102000, 0.5330202000, 1.1682405000", \ - "0.1328636000, 0.1427270000, 0.1641088000, 0.2093004000, 0.3093758000, 0.5561460000, 1.1956890000", \ - "0.1720452000, 0.1817733000, 0.2032646000, 0.2492782000, 0.3504191000, 0.5972887000, 1.2366550000", \ - "0.2199428000, 0.2312247000, 0.2541434000, 0.3001406000, 0.4021521000, 0.6516729000, 1.2906812000", \ - "0.2581925000, 0.2729234000, 0.3018356000, 0.3531901000, 0.4564079000, 0.7051449000, 1.3438739000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0386950000, 0.0454769000, 0.0601141000, 0.0925714000, 0.1591800000, 0.3109836000, 0.7039429000", \ - "0.0382461000, 0.0449562000, 0.0605109000, 0.0911487000, 0.1584196000, 0.3104837000, 0.7047394000", \ - "0.0376771000, 0.0443330000, 0.0598275000, 0.0905264000, 0.1581607000, 0.3101300000, 0.7062069000", \ - "0.0362192000, 0.0431411000, 0.0580856000, 0.0896754000, 0.1578994000, 0.3096003000, 0.7044275000", \ - "0.0362533000, 0.0423673000, 0.0563843000, 0.0877428000, 0.1554530000, 0.3092564000, 0.7055317000", \ - "0.0481338000, 0.0547766000, 0.0676950000, 0.0956431000, 0.1581871000, 0.3120555000, 0.7047942000", \ - "0.0647430000, 0.0737340000, 0.0898304000, 0.1175254000, 0.1742220000, 0.3197874000, 0.7117947000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0360238000, 0.0449634000, 0.0656694000, 0.1153598000, 0.2424637000, 0.5869570000, 1.4897440000", \ - "0.0359055000, 0.0449900000, 0.0655753000, 0.1152947000, 0.2428566000, 0.5861762000, 1.4966747000", \ - "0.0358798000, 0.0447349000, 0.0655112000, 0.1151852000, 0.2426805000, 0.5871278000, 1.4945134000", \ - "0.0353025000, 0.0441768000, 0.0652927000, 0.1147914000, 0.2420989000, 0.5857742000, 1.4899355000", \ - "0.0371268000, 0.0456800000, 0.0664086000, 0.1165666000, 0.2436401000, 0.5868864000, 1.4903225000", \ - "0.0462560000, 0.0536212000, 0.0717609000, 0.1188474000, 0.2466278000, 0.5885135000, 1.4888376000", \ - "0.0627811000, 0.0718502000, 0.0897444000, 0.1310556000, 0.2499147000, 0.5903983000, 1.4858849000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1626431000, 0.1740302000, 0.1966777000, 0.2378877000, 0.3129865000, 0.4601871000, 0.7847718000", \ - "0.1676653000, 0.1790112000, 0.2014999000, 0.2426893000, 0.3177797000, 0.4649648000, 0.7896599000", \ - "0.1777026000, 0.1890251000, 0.2114531000, 0.2527182000, 0.3281203000, 0.4751020000, 0.7996139000", \ - "0.1986734000, 0.2098054000, 0.2318676000, 0.2726981000, 0.3477206000, 0.4947048000, 0.8194128000", \ - "0.2458216000, 0.2553871000, 0.2756486000, 0.3144183000, 0.3878795000, 0.5341839000, 0.8584714000", \ - "0.2913577000, 0.3008705000, 0.3205018000, 0.3584933000, 0.4307566000, 0.5746598000, 0.8982750000", \ - "0.3255471000, 0.3354970000, 0.3551377000, 0.3931023000, 0.4646493000, 0.6098614000, 0.9322856000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.1437035000, 0.1529706000, 0.1732284000, 0.2166893000, 0.3158357000, 0.5638111000, 1.1996923000", \ - "0.1484788000, 0.1576600000, 0.1779127000, 0.2213613000, 0.3205727000, 0.5673573000, 1.2074919000", \ - "0.1613498000, 0.1706237000, 0.1908919000, 0.2343638000, 0.3332624000, 0.5813515000, 1.2203247000", \ - "0.1927569000, 0.2019750000, 0.2222529000, 0.2657219000, 0.3648053000, 0.6119875000, 1.2509906000", \ - "0.2568588000, 0.2660450000, 0.2863104000, 0.3297792000, 0.4287800000, 0.6759632000, 1.3129220000", \ - "0.3570244000, 0.3661846000, 0.3863453000, 0.4298172000, 0.5287043000, 0.7761191000, 1.4118982000", \ - "0.5100135000, 0.5191320000, 0.5393682000, 0.5830855000, 0.6827090000, 0.9299275000, 1.5659746000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0508987000, 0.0568404000, 0.0701938000, 0.0978405000, 0.1622895000, 0.3131679000, 0.7066245000", \ - "0.0507457000, 0.0569767000, 0.0700925000, 0.0978064000, 0.1621675000, 0.3132843000, 0.7068982000", \ - "0.0504468000, 0.0565107000, 0.0698086000, 0.0976918000, 0.1623343000, 0.3133785000, 0.7060413000", \ - "0.0480941000, 0.0543728000, 0.0677506000, 0.0982169000, 0.1620996000, 0.3133279000, 0.7083263000", \ - "0.0401817000, 0.0468486000, 0.0613032000, 0.0923107000, 0.1594305000, 0.3118808000, 0.7056053000", \ - "0.0394093000, 0.0461481000, 0.0598885000, 0.0902370000, 0.1558524000, 0.3076053000, 0.7028313000", \ - "0.0384551000, 0.0448082000, 0.0602161000, 0.0912154000, 0.1574532000, 0.3096958000, 0.6976892000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0012952100, 0.0033551200, 0.0086911400, 0.0225136000, 0.0583196000, 0.1510720000"); - values("0.0328327000, 0.0413857000, 0.0615784000, 0.1108266000, 0.2398551000, 0.5863026000, 1.4893485000", \ - "0.0328214000, 0.0413156000, 0.0616473000, 0.1108220000, 0.2397563000, 0.5843664000, 1.4894537000", \ - "0.0328590000, 0.0412821000, 0.0614914000, 0.1107119000, 0.2394370000, 0.5868545000, 1.4958170000", \ - "0.0328403000, 0.0414362000, 0.0614097000, 0.1107184000, 0.2396892000, 0.5863361000, 1.4932622000", \ - "0.0326563000, 0.0411719000, 0.0615717000, 0.1107202000, 0.2399769000, 0.5871666000, 1.4934917000", \ - "0.0328073000, 0.0413718000, 0.0615897000, 0.1109084000, 0.2391438000, 0.5855765000, 1.4895938000", \ - "0.0337789000, 0.0421639000, 0.0625468000, 0.1120640000, 0.2408642000, 0.5837951000, 1.4866324000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor3_2") { - leakage_power () { - value : 0.0099959000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0126358000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0244313000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0192028000; - when : "!A&B&!C"; - } - leakage_power () { - value : 0.0123724000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0071437000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0189376000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0215765000; - when : "A&B&!C"; - } - area : 25.024000000; - cell_footprint : "sky130_fd_sc_hd__xor3"; - cell_leakage_power : 0.0157869900; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024400000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022960000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025830000; - } - pin ("B") { - capacitance : 0.0052790000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051230000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054350000; - } - pin ("C") { - capacitance : 0.0034820000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033640000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0036010000; - } - pin ("X") { - direction : "output"; - function : "(A&!B&!C) | (!A&B&!C) | (!A&!B&C) | (A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0430605000, 0.0413095000, 0.0371600000, 0.0262396000, -0.007062700, -0.109641500, -0.411222200", \ - "0.0429619000, 0.0412037000, 0.0370434000, 0.0261447000, -0.007167200, -0.109744100, -0.411254400", \ - "0.0427803000, 0.0410337000, 0.0368597000, 0.0259649000, -0.007333100, -0.109915400, -0.411432000", \ - "0.0424927000, 0.0407404000, 0.0365794000, 0.0256872000, -0.007627600, -0.110205600, -0.411707300", \ - "0.0423195000, 0.0405947000, 0.0364486000, 0.0255316000, -0.007846100, -0.110366500, -0.411849500", \ - "0.0423666000, 0.0406187000, 0.0364559000, 0.0255757000, -0.007797900, -0.110365100, -0.411829300", \ - "0.0500745000, 0.0482743000, 0.0434847000, 0.0305821000, -0.005670800, -0.109649800, -0.411094200"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0539116000, 0.0555836000, 0.0602577000, 0.0738692000, 0.1105969000, 0.2145811000, 0.5162274000", \ - "0.0536614000, 0.0553331000, 0.0601198000, 0.0737607000, 0.1104226000, 0.2144183000, 0.5142982000", \ - "0.0534380000, 0.0550456000, 0.0598722000, 0.0734201000, 0.1101145000, 0.2141707000, 0.5136443000", \ - "0.0532740000, 0.0549411000, 0.0596825000, 0.0732152000, 0.1099263000, 0.2140324000, 0.5152176000", \ - "0.0530059000, 0.0546049000, 0.0594546000, 0.0730024000, 0.1097016000, 0.2137404000, 0.5132158000", \ - "0.0533347000, 0.0550125000, 0.0597667000, 0.0734120000, 0.1100632000, 0.2140707000, 0.5157011000", \ - "0.0553914000, 0.0569155000, 0.0614223000, 0.0740478000, 0.1111832000, 0.2145725000, 0.5137616000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0284493000, 0.0267074000, 0.0225788000, 0.0116580000, -0.021670000, -0.124300100, -0.425812700", \ - "0.0280689000, 0.0263266000, 0.0221995000, 0.0112831000, -0.022045500, -0.124672200, -0.426196600", \ - "0.0275647000, 0.0258077000, 0.0216995000, 0.0107804000, -0.022538300, -0.125174100, -0.426710200", \ - "0.0270225000, 0.0252943000, 0.0211620000, 0.0103065000, -0.023021900, -0.125683600, -0.427207500", \ - "0.0271931000, 0.0254720000, 0.0213696000, 0.0104762000, -0.022904300, -0.125549600, -0.427032500", \ - "0.0286311000, 0.0268736000, 0.0227040000, 0.0117420000, -0.021709500, -0.124316200, -0.425761200", \ - "0.0405886000, 0.0387744000, 0.0340653000, 0.0212129000, -0.014968400, -0.119670700, -0.421156500"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0501306000, 0.0516777000, 0.0565359000, 0.0701550000, 0.1068184000, 0.2108066000, 0.5110191000", \ - "0.0496607000, 0.0512571000, 0.0560878000, 0.0696516000, 0.1063195000, 0.2103309000, 0.5099054000", \ - "0.0492249000, 0.0509169000, 0.0555950000, 0.0692000000, 0.1058904000, 0.2098540000, 0.5115011000", \ - "0.0490016000, 0.0506322000, 0.0553106000, 0.0689140000, 0.1056095000, 0.2094784000, 0.5114624000", \ - "0.0490880000, 0.0506914000, 0.0554065000, 0.0690131000, 0.1057150000, 0.2096634000, 0.5114714000", \ - "0.0500671000, 0.0516939000, 0.0565995000, 0.0702509000, 0.1070273000, 0.2109913000, 0.5104495000", \ - "0.0551239000, 0.0566456000, 0.0612239000, 0.0739757000, 0.1102679000, 0.2153533000, 0.5131815000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0134966000, 0.0117973000, 0.0077548000, -0.002948600, -0.036071900, -0.138671800, -0.440188800", \ - "0.0133709000, 0.0117025000, 0.0076259000, -0.003023300, -0.036163000, -0.138724500, -0.440268300", \ - "0.0131671000, 0.0114953000, 0.0074730000, -0.003251400, -0.036344000, -0.138888100, -0.440427300", \ - "0.0130219000, 0.0113172000, 0.0073748000, -0.003288200, -0.036437400, -0.138959200, -0.440448600", \ - "0.0127447000, 0.0111462000, 0.0072708000, -0.003321000, -0.036495400, -0.138966800, -0.440349500", \ - "0.0162361000, 0.0145525000, 0.0099762000, -0.002092900, -0.035486300, -0.138011500, -0.439359400", \ - "0.0239560000, 0.0223041000, 0.0177911000, 0.0052839000, -0.030625300, -0.135271400, -0.436993800"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0014402850, 0.0041488430, 0.0119510300, 0.0344258000, 0.0991659300, 0.2856544000"); - values("0.0298504000, 0.0314865000, 0.0362439000, 0.0496336000, 0.0862433000, 0.1904413000, 0.4898807000", \ - "0.0296118000, 0.0312268000, 0.0359811000, 0.0493869000, 0.0860023000, 0.1902072000, 0.4896148000", \ - "0.0294368000, 0.0310567000, 0.0358158000, 0.0492171000, 0.0858294000, 0.1900251000, 0.4891638000", \ - "0.0294878000, 0.0311252000, 0.0358757000, 0.0492920000, 0.0858826000, 0.1898902000, 0.4874756000", \ - "0.0299681000, 0.0315791000, 0.0363567000, 0.0497539000, 0.0863122000, 0.1904794000, 0.4899396000", \ - "0.0313893000, 0.0324183000, 0.0372945000, 0.0508093000, 0.0872316000, 0.1915017000, 0.4905852000", \ - "0.0342284000, 0.0358059000, 0.0403147000, 0.0531311000, 0.0892371000, 0.1938660000, 0.4917037000"); - } - } - max_capacitance : 0.2856540000; - max_transition : 1.5003590000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3272288000, 0.3375020000, 0.3599021000, 0.4020282000, 0.4772729000, 0.6231376000, 0.9543154000", \ - "0.3324988000, 0.3427990000, 0.3652043000, 0.4073100000, 0.4825389000, 0.6284271000, 0.9596892000", \ - "0.3452069000, 0.3555524000, 0.3780228000, 0.4201266000, 0.4953103000, 0.6411592000, 0.9725271000", \ - "0.3765652000, 0.3868997000, 0.4093565000, 0.4514756000, 0.5266580000, 0.6725249000, 1.0039094000", \ - "0.4501940000, 0.4605400000, 0.4830007000, 0.5252401000, 0.6004860000, 0.7462921000, 1.0773821000", \ - "0.6092644000, 0.6198249000, 0.6426965000, 0.6852801000, 0.7608859000, 0.9071839000, 1.2388902000", \ - "0.8904896000, 0.9030895000, 0.9298342000, 0.9777450000, 1.0592066000, 1.2108863000, 1.5457500000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1902512000, 0.1983125000, 0.2170243000, 0.2575123000, 0.3497236000, 0.5879162000, 1.2643632000", \ - "0.1949212000, 0.2029279000, 0.2215201000, 0.2621403000, 0.3542955000, 0.5929590000, 1.2734527000", \ - "0.2059765000, 0.2140379000, 0.2326852000, 0.2731737000, 0.3653372000, 0.6036892000, 1.2797062000", \ - "0.2304669000, 0.2385497000, 0.2571976000, 0.2977777000, 0.3900289000, 0.6286607000, 1.3071351000", \ - "0.2796099000, 0.2876758000, 0.3063734000, 0.3468613000, 0.4390664000, 0.6776444000, 1.3566314000", \ - "0.3601246000, 0.3688936000, 0.3887530000, 0.4312718000, 0.5251378000, 0.7641838000, 1.4431891000", \ - "0.4655640000, 0.4760091000, 0.4996899000, 0.5477855000, 0.6473189000, 0.8883835000, 1.5656816000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0663383000, 0.0701628000, 0.0793782000, 0.1006309000, 0.1519013000, 0.2890791000, 0.6779158000", \ - "0.0663135000, 0.0701387000, 0.0793398000, 0.1006107000, 0.1513422000, 0.2888065000, 0.6779745000", \ - "0.0662575000, 0.0706839000, 0.0794240000, 0.1004141000, 0.1519225000, 0.2885976000, 0.6761117000", \ - "0.0663091000, 0.0708124000, 0.0792472000, 0.1004841000, 0.1519094000, 0.2886277000, 0.6765533000", \ - "0.0670046000, 0.0705388000, 0.0796492000, 0.1008140000, 0.1529180000, 0.2883258000, 0.6775095000", \ - "0.0725553000, 0.0761510000, 0.0835518000, 0.1031794000, 0.1536193000, 0.2894407000, 0.6774811000", \ - "0.1045253000, 0.1060855000, 0.1087296000, 0.1217620000, 0.1666135000, 0.2967381000, 0.6815493000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0312502000, 0.0380115000, 0.0539093000, 0.0935428000, 0.2028968000, 0.5292193000, 1.4972287000", \ - "0.0314876000, 0.0379975000, 0.0538243000, 0.0936528000, 0.2025980000, 0.5290406000, 1.4956991000", \ - "0.0314366000, 0.0378855000, 0.0538723000, 0.0934273000, 0.2030060000, 0.5291090000, 1.4924151000", \ - "0.0313885000, 0.0378245000, 0.0539129000, 0.0935747000, 0.2029030000, 0.5280324000, 1.4937581000", \ - "0.0316473000, 0.0381514000, 0.0540428000, 0.0936944000, 0.2027417000, 0.5276765000, 1.4923111000", \ - "0.0349907000, 0.0417895000, 0.0582675000, 0.0978113000, 0.2054051000, 0.5289076000, 1.4948794000", \ - "0.0443528000, 0.0517281000, 0.0699674000, 0.1098969000, 0.2143491000, 0.5313211000, 1.4885576000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3667222000, 0.3770551000, 0.3997921000, 0.4424901000, 0.5192656000, 0.6680705000, 1.0024072000", \ - "0.3714998000, 0.3816609000, 0.4043110000, 0.4470248000, 0.5241083000, 0.6725937000, 1.0069993000", \ - "0.3827428000, 0.3929185000, 0.4156185000, 0.4583027000, 0.5353198000, 0.6838503000, 1.0182893000", \ - "0.4090490000, 0.4192182000, 0.4418484000, 0.4845769000, 0.5616961000, 0.7101714000, 1.0445309000", \ - "0.4563256000, 0.4665467000, 0.4890512000, 0.5318058000, 0.6086754000, 0.7575601000, 1.0916451000", \ - "0.5231487000, 0.5333127000, 0.5557946000, 0.5984281000, 0.6756005000, 0.8244608000, 1.1585801000", \ - "0.5976976000, 0.6079757000, 0.6306545000, 0.6733776000, 0.7503645000, 0.8991857000, 1.2333896000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3375973000, 0.3464536000, 0.3667019000, 0.4096672000, 0.5042097000, 0.7437934000, 1.4242679000", \ - "0.3427887000, 0.3516436000, 0.3718200000, 0.4148714000, 0.5095260000, 0.7493367000, 1.4281402000", \ - "0.3552064000, 0.3640776000, 0.3843109000, 0.4272011000, 0.5218826000, 0.7612538000, 1.4393885000", \ - "0.3869274000, 0.3957933000, 0.4160548000, 0.4589106000, 0.5535709000, 0.7928767000, 1.4750355000", \ - "0.4611481000, 0.4699754000, 0.4902550000, 0.5331887000, 0.6278882000, 0.8673990000, 1.5467111000", \ - "0.6048973000, 0.6137889000, 0.6340939000, 0.6772053000, 0.7717857000, 1.0113523000, 1.6923263000", \ - "0.8404172000, 0.8493997000, 0.8699885000, 0.9134559000, 1.0086337000, 1.2480903000, 1.9287800000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0631014000, 0.0682057000, 0.0787558000, 0.1025541000, 0.1564144000, 0.2946800000, 0.6828376000", \ - "0.0629716000, 0.0680938000, 0.0785323000, 0.1018787000, 0.1563575000, 0.2948256000, 0.6822650000", \ - "0.0630056000, 0.0681878000, 0.0786227000, 0.1019062000, 0.1562263000, 0.2948959000, 0.6822550000", \ - "0.0629414000, 0.0680292000, 0.0784933000, 0.1018944000, 0.1564043000, 0.2946956000, 0.6821615000", \ - "0.0636028000, 0.0694306000, 0.0788245000, 0.1016838000, 0.1551216000, 0.2946451000, 0.6820704000", \ - "0.0630724000, 0.0683679000, 0.0784685000, 0.1024692000, 0.1565918000, 0.2943566000, 0.6816521000", \ - "0.0633426000, 0.0684193000, 0.0788102000, 0.1022533000, 0.1564546000, 0.2946945000, 0.6807604000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0353132000, 0.0418051000, 0.0586783000, 0.0987071000, 0.2071389000, 0.5302163000, 1.4976033000", \ - "0.0352788000, 0.0421355000, 0.0586475000, 0.0986708000, 0.2071406000, 0.5306182000, 1.4947319000", \ - "0.0350914000, 0.0418303000, 0.0586045000, 0.0987988000, 0.2072079000, 0.5315162000, 1.4970153000", \ - "0.0349454000, 0.0419443000, 0.0586541000, 0.0987888000, 0.2071968000, 0.5311981000, 1.4977547000", \ - "0.0353928000, 0.0418421000, 0.0585067000, 0.0987193000, 0.2070184000, 0.5315001000, 1.4948540000", \ - "0.0353757000, 0.0420410000, 0.0587035000, 0.0989162000, 0.2072180000, 0.5305694000, 1.4978170000", \ - "0.0357487000, 0.0427772000, 0.0595050000, 0.0997543000, 0.2080979000, 0.5294283000, 1.4959537000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.3224366000, 0.3325719000, 0.3550239000, 0.3978075000, 0.4746260000, 0.6235084000, 0.9575237000", \ - "0.3258460000, 0.3359998000, 0.3586783000, 0.4014932000, 0.4781958000, 0.6270647000, 0.9610670000", \ - "0.3366872000, 0.3471927000, 0.3697067000, 0.4125081000, 0.4893234000, 0.6382011000, 0.9722019000", \ - "0.3658092000, 0.3759592000, 0.3983650000, 0.4411251000, 0.5179690000, 0.6668682000, 1.0008935000", \ - "0.4286222000, 0.4389395000, 0.4616067000, 0.5043081000, 0.5809890000, 0.7298996000, 1.0639600000", \ - "0.5596457000, 0.5704192000, 0.5934763000, 0.6369971000, 0.7146548000, 0.8635949000, 1.1981174000", \ - "0.7754605000, 0.7897851000, 0.8205297000, 0.8756625000, 0.9660767000, 1.1273662000, 1.4688587000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1678397000, 0.1758986000, 0.1943058000, 0.2346266000, 0.3260665000, 0.5637467000, 1.2447491000", \ - "0.1709236000, 0.1789816000, 0.1973890000, 0.2377087000, 0.3291506000, 0.5668542000, 1.2477551000", \ - "0.1803796000, 0.1883446000, 0.2068968000, 0.2470840000, 0.3385742000, 0.5766043000, 1.2545128000", \ - "0.2045095000, 0.2125543000, 0.2309709000, 0.2711637000, 0.3624192000, 0.6005623000, 1.2800031000", \ - "0.2563656000, 0.2644022000, 0.2829745000, 0.3231991000, 0.4143120000, 0.6525112000, 1.3332614000", \ - "0.3374484000, 0.3465686000, 0.3669567000, 0.4094788000, 0.5023679000, 0.7410306000, 1.4166710000", \ - "0.4344329000, 0.4459565000, 0.4711669000, 0.5205343000, 0.6186254000, 0.8581064000, 1.5352254000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0627230000, 0.0686132000, 0.0786966000, 0.1012995000, 0.1553210000, 0.2946342000, 0.6824453000", \ - "0.0639790000, 0.0679673000, 0.0787630000, 0.1017097000, 0.1559247000, 0.2945841000, 0.6827315000", \ - "0.0626540000, 0.0685253000, 0.0787484000, 0.1012793000, 0.1555877000, 0.2946206000, 0.6825259000", \ - "0.0626879000, 0.0687321000, 0.0785547000, 0.1013847000, 0.1551640000, 0.2946334000, 0.6824020000", \ - "0.0629561000, 0.0679011000, 0.0786681000, 0.1016666000, 0.1559648000, 0.2946440000, 0.6826988000", \ - "0.0693863000, 0.0731955000, 0.0836287000, 0.1046140000, 0.1580696000, 0.2953838000, 0.6823593000", \ - "0.1109830000, 0.1149539000, 0.1240377000, 0.1405153000, 0.1855258000, 0.3146172000, 0.6923635000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0311633000, 0.0376158000, 0.0534531000, 0.0929201000, 0.2020921000, 0.5279533000, 1.4963251000", \ - "0.0311636000, 0.0376169000, 0.0534526000, 0.0929222000, 0.2020904000, 0.5278886000, 1.4963029000", \ - "0.0311012000, 0.0373712000, 0.0534007000, 0.0927934000, 0.2017570000, 0.5279270000, 1.4914626000", \ - "0.0311220000, 0.0375486000, 0.0531869000, 0.0928083000, 0.2018509000, 0.5288929000, 1.4962490000", \ - "0.0318520000, 0.0383260000, 0.0539407000, 0.0930294000, 0.2020022000, 0.5285036000, 1.4968440000", \ - "0.0373861000, 0.0440790000, 0.0596484000, 0.0983113000, 0.2050809000, 0.5299358000, 1.4957560000", \ - "0.0506286000, 0.0586964000, 0.0751261000, 0.1123678000, 0.2131692000, 0.5328243000, 1.4900620000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2690631000, 0.2792880000, 0.3018095000, 0.3443331000, 0.4208284000, 0.5686361000, 0.9012863000", \ - "0.2724858000, 0.2827299000, 0.3052701000, 0.3477611000, 0.4242804000, 0.5720558000, 0.9047387000", \ - "0.2807246000, 0.2909675000, 0.3134791000, 0.3560768000, 0.4324822000, 0.5802973000, 0.9128968000", \ - "0.3006264000, 0.3109631000, 0.3336999000, 0.3760343000, 0.4524702000, 0.6000885000, 0.9329234000", \ - "0.3563684000, 0.3668723000, 0.3891055000, 0.4315393000, 0.5078551000, 0.6556187000, 0.9882883000", \ - "0.4328452000, 0.4430565000, 0.4651781000, 0.5072149000, 0.5828445000, 0.7302723000, 1.0634976000", \ - "0.4918209000, 0.5015187000, 0.5239179000, 0.5663281000, 0.6426071000, 0.7900932000, 1.1222941000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.2459075000, 0.2546963000, 0.2749474000, 0.3179168000, 0.4125507000, 0.6521317000, 1.3321958000", \ - "0.2493034000, 0.2581472000, 0.2784200000, 0.3213379000, 0.4159693000, 0.6554262000, 1.3350077000", \ - "0.2609124000, 0.2697541000, 0.2900112000, 0.3329022000, 0.4273567000, 0.6668377000, 1.3477208000", \ - "0.2905125000, 0.2993516000, 0.3195478000, 0.3624770000, 0.4569151000, 0.6965247000, 1.3763558000", \ - "0.3507677000, 0.3595763000, 0.3797347000, 0.4227501000, 0.5172148000, 0.7570268000, 1.4350205000", \ - "0.4376226000, 0.4463860000, 0.4666125000, 0.5096452000, 0.6038553000, 0.8434315000, 1.5212278000", \ - "0.5662085000, 0.5750778000, 0.5955442000, 0.6386826000, 0.7336666000, 0.9728988000, 1.6486970000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0632083000, 0.0679630000, 0.0780860000, 0.1010999000, 0.1541060000, 0.2918776000, 0.6795924000", \ - "0.0631851000, 0.0679970000, 0.0780225000, 0.1011295000, 0.1541875000, 0.2920074000, 0.6793315000", \ - "0.0632306000, 0.0678530000, 0.0782341000, 0.1009798000, 0.1538074000, 0.2925027000, 0.6801403000", \ - "0.0633735000, 0.0681546000, 0.0784053000, 0.1014563000, 0.1550809000, 0.2922237000, 0.6788682000", \ - "0.0624283000, 0.0672057000, 0.0778341000, 0.1005095000, 0.1539854000, 0.2917552000, 0.6796960000", \ - "0.0618976000, 0.0669184000, 0.0773121000, 0.1000571000, 0.1536774000, 0.2920590000, 0.6797961000", \ - "0.0623600000, 0.0676070000, 0.0778250000, 0.1005911000, 0.1542375000, 0.2915379000, 0.6764296000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0352295000, 0.0420451000, 0.0583405000, 0.0987460000, 0.2068895000, 0.5312894000, 1.4945328000", \ - "0.0351371000, 0.0418092000, 0.0584504000, 0.0987054000, 0.2069858000, 0.5314909000, 1.4942644000", \ - "0.0352103000, 0.0418548000, 0.0586574000, 0.0986747000, 0.2071002000, 0.5304634000, 1.4977077000", \ - "0.0351128000, 0.0417347000, 0.0585489000, 0.0985494000, 0.2070287000, 0.5305799000, 1.4971148000", \ - "0.0351615000, 0.0420148000, 0.0587159000, 0.0984878000, 0.2070294000, 0.5314068000, 1.4977233000", \ - "0.0349665000, 0.0422576000, 0.0589155000, 0.0983648000, 0.2066787000, 0.5315844000, 1.4972975000", \ - "0.0355042000, 0.0423097000, 0.0591891000, 0.0995039000, 0.2077733000, 0.5295091000, 1.4909800000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1767168000, 0.1861932000, 0.2070323000, 0.2475588000, 0.3217512000, 0.4683123000, 0.8004659000", \ - "0.1804827000, 0.1900382000, 0.2108305000, 0.2512027000, 0.3254651000, 0.4719370000, 0.8044858000", \ - "0.1906698000, 0.2000152000, 0.2207112000, 0.2608322000, 0.3352369000, 0.4817063000, 0.8138263000", \ - "0.2170444000, 0.2261633000, 0.2466925000, 0.2865354000, 0.3605539000, 0.5071067000, 0.8392864000", \ - "0.2796521000, 0.2883934000, 0.3079389000, 0.3467155000, 0.4202177000, 0.5660027000, 0.8983677000", \ - "0.4016847000, 0.4117124000, 0.4337977000, 0.4754132000, 0.5492330000, 0.6949841000, 1.0273726000", \ - "0.5826112000, 0.5950609000, 0.6229200000, 0.6758134000, 0.7643525000, 0.9168485000, 1.2548508000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1150683000, 0.1238135000, 0.1437437000, 0.1863698000, 0.2800147000, 0.5186945000, 1.1935892000", \ - "0.1192712000, 0.1279660000, 0.1479499000, 0.1905739000, 0.2843134000, 0.5229442000, 1.1980507000", \ - "0.1291498000, 0.1378541000, 0.1578046000, 0.2003630000, 0.2941661000, 0.5322406000, 1.2096056000", \ - "0.1527168000, 0.1613882000, 0.1811908000, 0.2236010000, 0.3174181000, 0.5557756000, 1.2339538000", \ - "0.2013353000, 0.2097713000, 0.2294800000, 0.2719371000, 0.3660010000, 0.6045884000, 1.2812946000", \ - "0.2662000000, 0.2762499000, 0.2977673000, 0.3412660000, 0.4363629000, 0.6773349000, 1.3537070000", \ - "0.3305566000, 0.3431609000, 0.3709973000, 0.4226509000, 0.5213192000, 0.7624812000, 1.4406181000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0490830000, 0.0548558000, 0.0678366000, 0.0938201000, 0.1501504000, 0.2905342000, 0.6792675000", \ - "0.0491437000, 0.0545374000, 0.0669302000, 0.0933736000, 0.1505691000, 0.2907939000, 0.6783185000", \ - "0.0484010000, 0.0541121000, 0.0665346000, 0.0928785000, 0.1500950000, 0.2906169000, 0.6795308000", \ - "0.0470370000, 0.0526494000, 0.0654147000, 0.0919840000, 0.1497638000, 0.2905681000, 0.6799134000", \ - "0.0438268000, 0.0496838000, 0.0633289000, 0.0895934000, 0.1486124000, 0.2899420000, 0.6790360000", \ - "0.0566194000, 0.0624565000, 0.0746354000, 0.0975963000, 0.1517879000, 0.2897636000, 0.6800683000", \ - "0.0759716000, 0.0838439000, 0.0995546000, 0.1294469000, 0.1770704000, 0.3042581000, 0.6884464000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0339886000, 0.0408759000, 0.0575622000, 0.0977098000, 0.2065916000, 0.5306890000, 1.4936837000", \ - "0.0339201000, 0.0408558000, 0.0575574000, 0.0976534000, 0.2065529000, 0.5298492000, 1.4954594000", \ - "0.0340037000, 0.0409204000, 0.0571405000, 0.0976154000, 0.2066439000, 0.5312382000, 1.4971555000", \ - "0.0337742000, 0.0403204000, 0.0569163000, 0.0974347000, 0.2065800000, 0.5314038000, 1.4959024000", \ - "0.0350911000, 0.0417389000, 0.0577122000, 0.0984702000, 0.2069412000, 0.5309022000, 1.4976932000", \ - "0.0451374000, 0.0511808000, 0.0658089000, 0.1032135000, 0.2106533000, 0.5333686000, 1.5003594000", \ - "0.0623978000, 0.0709292000, 0.0870826000, 0.1221549000, 0.2177565000, 0.5370471000, 1.4942589000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1938511000, 0.2039672000, 0.2262275000, 0.2685688000, 0.3451519000, 0.4933309000, 0.8274346000", \ - "0.1984971000, 0.2090049000, 0.2313560000, 0.2739193000, 0.3501719000, 0.4986877000, 0.8327410000", \ - "0.2090095000, 0.2192339000, 0.2414621000, 0.2841386000, 0.3603625000, 0.5089210000, 0.8427509000", \ - "0.2301595000, 0.2402575000, 0.2624282000, 0.3045152000, 0.3808459000, 0.5291819000, 0.8634135000", \ - "0.2776593000, 0.2870334000, 0.3076729000, 0.3480410000, 0.4231043000, 0.5709569000, 0.9046249000", \ - "0.3354911000, 0.3439226000, 0.3630683000, 0.4011928000, 0.4739736000, 0.6194481000, 0.9525736000", \ - "0.3680313000, 0.3766601000, 0.3958859000, 0.4345542000, 0.5079320000, 0.6545357000, 0.9861921000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.1560569000, 0.1639316000, 0.1820770000, 0.2217077000, 0.3122801000, 0.5505593000, 1.2296604000", \ - "0.1609240000, 0.1688158000, 0.1869074000, 0.2265540000, 0.3171349000, 0.5554679000, 1.2325095000", \ - "0.1739225000, 0.1818788000, 0.1999737000, 0.2396279000, 0.3302935000, 0.5684869000, 1.2508196000", \ - "0.2056836000, 0.2135093000, 0.2317785000, 0.2714208000, 0.3620620000, 0.5995962000, 1.2757058000", \ - "0.2715227000, 0.2793308000, 0.2974525000, 0.3370483000, 0.4275971000, 0.6657508000, 1.3439834000", \ - "0.3752873000, 0.3829373000, 0.4010793000, 0.4405792000, 0.5308863000, 0.7687937000, 1.4502289000", \ - "0.5354086000, 0.5431937000, 0.5612316000, 0.6009718000, 0.6918431000, 0.9292985000, 1.6037923000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0599733000, 0.0648485000, 0.0760755000, 0.0995126000, 0.1549808000, 0.2940029000, 0.6814118000", \ - "0.0599282000, 0.0648543000, 0.0761544000, 0.1006235000, 0.1555557000, 0.2940809000, 0.6828084000", \ - "0.0595584000, 0.0650459000, 0.0759702000, 0.0993247000, 0.1545708000, 0.2939195000, 0.6823935000", \ - "0.0576574000, 0.0632066000, 0.0743971000, 0.0988054000, 0.1548365000, 0.2936886000, 0.6815301000", \ - "0.0483413000, 0.0541409000, 0.0669709000, 0.0935053000, 0.1510048000, 0.2922394000, 0.6812143000", \ - "0.0461991000, 0.0513532000, 0.0635775000, 0.0895548000, 0.1468019000, 0.2876255000, 0.6809058000", \ - "0.0459686000, 0.0512993000, 0.0639296000, 0.0901043000, 0.1488132000, 0.2893551000, 0.6744653000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0014402900, 0.0041488400, 0.0119510000, 0.0344258000, 0.0991659000, 0.2856540000"); - values("0.0304294000, 0.0366712000, 0.0523416000, 0.0919079000, 0.2009821000, 0.5284023000, 1.4947107000", \ - "0.0304505000, 0.0367672000, 0.0524117000, 0.0916390000, 0.2013495000, 0.5295965000, 1.4973923000", \ - "0.0302272000, 0.0367682000, 0.0524101000, 0.0917484000, 0.2013548000, 0.5295452000, 1.4979871000", \ - "0.0302000000, 0.0366728000, 0.0523977000, 0.0917525000, 0.2012890000, 0.5291084000, 1.4927926000", \ - "0.0302298000, 0.0365925000, 0.0521962000, 0.0915547000, 0.2013228000, 0.5292746000, 1.4960668000", \ - "0.0301709000, 0.0364070000, 0.0522104000, 0.0916774000, 0.2004614000, 0.5297392000, 1.4982015000", \ - "0.0309827000, 0.0373958000, 0.0527972000, 0.0924830000, 0.2017861000, 0.5289324000, 1.4912634000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - - cell ("sky130_fd_sc_hd__xor3_4") { - leakage_power () { - value : 0.0130746000; - when : "A&!B&C"; - } - leakage_power () { - value : 0.0081032000; - when : "A&!B&!C"; - } - leakage_power () { - value : 0.0197583000; - when : "A&B&C"; - } - leakage_power () { - value : 0.0224497000; - when : "A&B&!C"; - } - leakage_power () { - value : 0.0108918000; - when : "!A&!B&C"; - } - leakage_power () { - value : 0.0135832000; - when : "!A&!B&!C"; - } - leakage_power () { - value : 0.0252379000; - when : "!A&B&C"; - } - leakage_power () { - value : 0.0202666000; - when : "!A&B&!C"; - } - area : 27.526400000; - cell_footprint : "sky130_fd_sc_hd__xor3"; - cell_leakage_power : 0.0166706400; - driver_waveform_fall : "ramp"; - driver_waveform_rise : "ramp"; - pg_pin ("VGND") { - pg_type : "primary_ground"; - related_bias_pin : "VPB"; - voltage_name : "VGND"; - } - pg_pin ("VNB") { - pg_type : "nwell"; - physical_connection : "device_layer"; - voltage_name : "VNB"; - } - pg_pin ("VPB") { - pg_type : "pwell"; - physical_connection : "device_layer"; - voltage_name : "VPB"; - } - pg_pin ("VPWR") { - pg_type : "primary_power"; - related_bias_pin : "VNB"; - voltage_name : "VPWR"; - } - pin ("A") { - capacitance : 0.0024220000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0022790000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0025650000; - } - pin ("B") { - capacitance : 0.0052750000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0051170000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0054320000; - } - pin ("C") { - capacitance : 0.0034650000; - clock : "false"; - direction : "input"; - fall_capacitance : 0.0033430000; - max_transition : 1.5000000000; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - rise_capacitance : 0.0035860000; - } - pin ("X") { - direction : "output"; - function : "(A&!B&!C) | (!A&B&!C) | (!A&!B&C) | (A&B&C)"; - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0533230000, 0.0510815000, 0.0445521000, 0.0273206000, -0.025053400, -0.197288300, -0.756775900", \ - "0.0532224000, 0.0509566000, 0.0444268000, 0.0271868000, -0.025044500, -0.197385500, -0.756837500", \ - "0.0530352000, 0.0507960000, 0.0442891000, 0.0270494000, -0.025266400, -0.197543800, -0.757025100", \ - "0.0527708000, 0.0504860000, 0.0440163000, 0.0268442000, -0.025539900, -0.197876500, -0.757342900", \ - "0.0525988000, 0.0503405000, 0.0439074000, 0.0266593000, -0.025747600, -0.197965600, -0.757464500", \ - "0.0527444000, 0.0504064000, 0.0439546000, 0.0267355000, -0.025655100, -0.197932500, -0.757403500", \ - "0.0615465000, 0.0592010000, 0.0524347000, 0.0332821000, -0.023267800, -0.197298200, -0.756714500"); - } - related_pin : "A"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0639735000, 0.0656933000, 0.0712885000, 0.0900739000, 0.1472822000, 0.3234468000, 0.8792868000", \ - "0.0638228000, 0.0654942000, 0.0710944000, 0.0898885000, 0.1471310000, 0.3232647000, 0.8787634000", \ - "0.0636136000, 0.0653006000, 0.0709417000, 0.0895493000, 0.1469329000, 0.3227728000, 0.8799339000", \ - "0.0633340000, 0.0650603000, 0.0706618000, 0.0894448000, 0.1466363000, 0.3228167000, 0.8786688000", \ - "0.0631345000, 0.0648852000, 0.0706657000, 0.0891768000, 0.1464868000, 0.3223231000, 0.8785130000", \ - "0.0635527000, 0.0652917000, 0.0709017000, 0.0896107000, 0.1468483000, 0.3229401000, 0.8782255000", \ - "0.0653183000, 0.0670276000, 0.0725198000, 0.0901862000, 0.1480350000, 0.3236232000, 0.8793034000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0386194000, 0.0362739000, 0.0298496000, 0.0127639000, -0.039537500, -0.211734800, -0.771292900", \ - "0.0381704000, 0.0358925000, 0.0294595000, 0.0123663000, -0.039943600, -0.212101900, -0.771679300", \ - "0.0376633000, 0.0354285000, 0.0289762000, 0.0118240000, -0.040277000, -0.212612500, -0.772168500", \ - "0.0371045000, 0.0348230000, 0.0284491000, 0.0112498000, -0.040899700, -0.213150400, -0.772695000", \ - "0.0372523000, 0.0349959000, 0.0285743000, 0.0114350000, -0.040678000, -0.213094800, -0.772543300", \ - "0.0384590000, 0.0362696000, 0.0298833000, 0.0127458000, -0.039544600, -0.212012500, -0.771438100", \ - "0.0526765000, 0.0504471000, 0.0437040000, 0.0246688000, -0.031666600, -0.207431400, -0.766891900"); - } - related_pin : "B"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0602672000, 0.0620038000, 0.0676764000, 0.0862401000, 0.1435662000, 0.3195028000, 0.8721109000", \ - "0.0598632000, 0.0615793000, 0.0672174000, 0.0858074000, 0.1431357000, 0.3191402000, 0.8719826000", \ - "0.0593536000, 0.0609458000, 0.0666412000, 0.0854596000, 0.1426928000, 0.3184670000, 0.8746418000", \ - "0.0590030000, 0.0607282000, 0.0663359000, 0.0850605000, 0.1423264000, 0.3181262000, 0.8743158000", \ - "0.0590801000, 0.0607648000, 0.0664008000, 0.0851276000, 0.1423963000, 0.3181908000, 0.8742888000", \ - "0.0603151000, 0.0620308000, 0.0676508000, 0.0862013000, 0.1434594000, 0.3196891000, 0.8753033000", \ - "0.0661173000, 0.0679292000, 0.0733861000, 0.0911168000, 0.1469228000, 0.3232805000, 0.8792818000"); - } - } - internal_power () { - fall_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0238020000, 0.0214843000, 0.0150690000, -0.002090600, -0.054183900, -0.226320500, -0.785856100", \ - "0.0236761000, 0.0213960000, 0.0149510000, -0.002240900, -0.054148900, -0.226420000, -0.785912500", \ - "0.0235649000, 0.0212882000, 0.0148026000, -0.002336200, -0.054434400, -0.226531700, -0.786040400", \ - "0.0234329000, 0.0211734000, 0.0147216000, -0.002358700, -0.054454800, -0.226617200, -0.786044600", \ - "0.0227856000, 0.0205646000, 0.0142233000, -0.002744700, -0.054612800, -0.226679000, -0.786004000", \ - "0.0234396000, 0.0212848000, 0.0150710000, -0.001702000, -0.053753800, -0.225733300, -0.784935100", \ - "0.0359865000, 0.0337800000, 0.0272132000, 0.0086652000, -0.047579500, -0.223788200, -0.782992200"); - } - related_pin : "C"; - rise_power ("power_outputs_1") { - index_1("0.0100000000, 0.0230505800, 0.0531329300, 0.1224745000, 0.2823108000, 0.6507428000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209010, 0.0159106300, 0.0504188900, 0.1597714000, 0.5062964000"); - values("0.0393273000, 0.0410132000, 0.0468933000, 0.0655563000, 0.1224612000, 0.2985942000, 0.8559662000", \ - "0.0390756000, 0.0407860000, 0.0466620000, 0.0653171000, 0.1222522000, 0.2984116000, 0.8558435000", \ - "0.0389403000, 0.0406388000, 0.0464706000, 0.0651521000, 0.1221266000, 0.2983087000, 0.8556166000", \ - "0.0389589000, 0.0407143000, 0.0464879000, 0.0651318000, 0.1222350000, 0.2981787000, 0.8514149000", \ - "0.0393827000, 0.0410981000, 0.0469030000, 0.0656062000, 0.1225515000, 0.2986296000, 0.8563376000", \ - "0.0404907000, 0.0423217000, 0.0480076000, 0.0667205000, 0.1236392000, 0.2996857000, 0.8561867000", \ - "0.0450861000, 0.0467341000, 0.0523295000, 0.0701318000, 0.1255798000, 0.3025074000, 0.8560837000"); - } - } - max_capacitance : 0.5062960000; - max_transition : 1.5035790000; - power_down_function : "(!VPWR + VGND)"; - related_ground_pin : "VGND"; - related_power_pin : "VPWR"; - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.3890381000, 0.3967643000, 0.4162581000, 0.4587203000, 0.5391453000, 0.6931830000, 1.0355804000", \ - "0.3942998000, 0.4019165000, 0.4215517000, 0.4640062000, 0.5443498000, 0.6977644000, 1.0407417000", \ - "0.4071301000, 0.4146828000, 0.4343964000, 0.4769920000, 0.5572115000, 0.7108721000, 1.0536738000", \ - "0.4384725000, 0.4460564000, 0.4658592000, 0.5081486000, 0.5887223000, 0.7421815000, 1.0850963000", \ - "0.5116124000, 0.5192263000, 0.5388524000, 0.5812633000, 0.6616443000, 0.8155474000, 1.1581769000", \ - "0.6729369000, 0.6805779000, 0.7003624000, 0.7428888000, 0.8234932000, 0.9777322000, 1.3205380000", \ - "0.9735034000, 0.9818917000, 1.0034900000, 1.0496543000, 1.1351891000, 1.2934844000, 1.6391323000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.2336253000, 0.2402151000, 0.2572435000, 0.2965076000, 0.3858674000, 0.6196526000, 1.3351558000", \ - "0.2382117000, 0.2447798000, 0.2618212000, 0.3010214000, 0.3905283000, 0.6240723000, 1.3370745000", \ - "0.2492309000, 0.2557961000, 0.2728426000, 0.3120528000, 0.4015653000, 0.6351381000, 1.3483391000", \ - "0.2735782000, 0.2801853000, 0.2971486000, 0.3364010000, 0.4258526000, 0.6594572000, 1.3740740000", \ - "0.3223894000, 0.3289639000, 0.3460011000, 0.3852787000, 0.4747568000, 0.7079321000, 1.4230174000", \ - "0.4086358000, 0.4155336000, 0.4332806000, 0.4739062000, 0.5645863000, 0.7987254000, 1.5155973000", \ - "0.5296386000, 0.5375298000, 0.5576748000, 0.6029756000, 0.6997847000, 0.9370104000, 1.6514641000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0778601000, 0.0813272000, 0.0917460000, 0.1126379000, 0.1607698000, 0.2877981000, 0.6603575000", \ - "0.0781249000, 0.0815033000, 0.0908104000, 0.1127008000, 0.1609152000, 0.2869602000, 0.6606091000", \ - "0.0780439000, 0.0819752000, 0.0912729000, 0.1138170000, 0.1607207000, 0.2873898000, 0.6599295000", \ - "0.0781306000, 0.0819839000, 0.0909492000, 0.1131985000, 0.1625064000, 0.2877892000, 0.6598975000", \ - "0.0782955000, 0.0816912000, 0.0921660000, 0.1128417000, 0.1608041000, 0.2876203000, 0.6605044000", \ - "0.0808852000, 0.0840165000, 0.0930809000, 0.1143661000, 0.1619181000, 0.2883519000, 0.6606873000", \ - "0.1028420000, 0.1058856000, 0.1124880000, 0.1304662000, 0.1745756000, 0.2950824000, 0.6634738000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0387810000, 0.0433799000, 0.0567188000, 0.0906636000, 0.1845718000, 0.4888372000, 1.4994325000", \ - "0.0385580000, 0.0433789000, 0.0565166000, 0.0906444000, 0.1850297000, 0.4898671000, 1.4920255000", \ - "0.0385682000, 0.0433945000, 0.0566041000, 0.0906545000, 0.1850086000, 0.4898290000, 1.4924922000", \ - "0.0385697000, 0.0435341000, 0.0565646000, 0.0906084000, 0.1849288000, 0.4899713000, 1.4942979000", \ - "0.0391030000, 0.0437178000, 0.0569344000, 0.0904853000, 0.1846965000, 0.4889974000, 1.4968490000", \ - "0.0412464000, 0.0464317000, 0.0601792000, 0.0941001000, 0.1870247000, 0.4899187000, 1.4990575000", \ - "0.0497795000, 0.0554137000, 0.0698267000, 0.1052507000, 0.1970383000, 0.4952550000, 1.4949890000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.4356104000, 0.4438338000, 0.4645603000, 0.5089155000, 0.5930497000, 0.7528294000, 1.1020389000", \ - "0.4403772000, 0.4483400000, 0.4687442000, 0.5134412000, 0.5979482000, 0.7571539000, 1.1066926000", \ - "0.4515907000, 0.4596319000, 0.4801126000, 0.5247019000, 0.6091257000, 0.7685698000, 1.1179014000", \ - "0.4781229000, 0.4859175000, 0.5066483000, 0.5512897000, 0.6352828000, 0.7949058000, 1.1444033000", \ - "0.5252282000, 0.5328168000, 0.5536038000, 0.5980803000, 0.6823456000, 0.8421540000, 1.1913592000", \ - "0.5914483000, 0.5991997000, 0.6199376000, 0.6646249000, 0.7490129000, 0.9085187000, 1.2579093000", \ - "0.6649833000, 0.6727560000, 0.6934938000, 0.7381417000, 0.8221810000, 0.9819319000, 1.3311914000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.3889672000, 0.3961170000, 0.4145808000, 0.4570298000, 0.5508589000, 0.7878833000, 1.5020267000", \ - "0.3941961000, 0.4013176000, 0.4198137000, 0.4622245000, 0.5560704000, 0.7932205000, 1.5104431000", \ - "0.4066559000, 0.4138271000, 0.4322463000, 0.4745874000, 0.5686072000, 0.8060163000, 1.5183427000", \ - "0.4383296000, 0.4454715000, 0.4639478000, 0.5064125000, 0.6002365000, 0.8372348000, 1.5514608000", \ - "0.5127284000, 0.5198703000, 0.5383948000, 0.5806327000, 0.6745497000, 0.9117901000, 1.6287934000", \ - "0.6569102000, 0.6640387000, 0.6826222000, 0.7250156000, 0.8188979000, 1.0560262000, 1.7735267000", \ - "0.8944489000, 0.9016606000, 0.9203651000, 0.9629273000, 1.0572340000, 1.2943587000, 2.0085980000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0816757000, 0.0854231000, 0.0955138000, 0.1187466000, 0.1691167000, 0.2986923000, 0.6704443000", \ - "0.0814670000, 0.0858444000, 0.0960661000, 0.1186997000, 0.1705037000, 0.2989502000, 0.6704185000", \ - "0.0815696000, 0.0857964000, 0.0961940000, 0.1189394000, 0.1710097000, 0.2985542000, 0.6699535000", \ - "0.0809449000, 0.0854160000, 0.0956794000, 0.1196195000, 0.1693497000, 0.2983694000, 0.6703567000", \ - "0.0810510000, 0.0856412000, 0.0964823000, 0.1188724000, 0.1691462000, 0.2987652000, 0.6704459000", \ - "0.0810508000, 0.0859694000, 0.0964725000, 0.1192589000, 0.1714974000, 0.2984195000, 0.6698022000", \ - "0.0811712000, 0.0856045000, 0.0957021000, 0.1196869000, 0.1695176000, 0.2983840000, 0.6708109000"); - } - related_pin : "A"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0435559000, 0.0484412000, 0.0623995000, 0.0979197000, 0.1924557000, 0.4947381000, 1.4999092000", \ - "0.0428765000, 0.0480560000, 0.0624111000, 0.0979595000, 0.1923759000, 0.4949254000, 1.5001240000", \ - "0.0428850000, 0.0482006000, 0.0628594000, 0.0979987000, 0.1926125000, 0.4945694000, 1.4994187000", \ - "0.0435481000, 0.0484688000, 0.0623773000, 0.0978893000, 0.1925541000, 0.4946163000, 1.4998014000", \ - "0.0429029000, 0.0481817000, 0.0626275000, 0.0981663000, 0.1925150000, 0.4949773000, 1.5004478000", \ - "0.0431609000, 0.0483290000, 0.0624881000, 0.0981046000, 0.1925009000, 0.4949043000, 1.5000302000", \ - "0.0435325000, 0.0488947000, 0.0633808000, 0.0990167000, 0.1930707000, 0.4939781000, 1.4962055000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.3923758000, 0.4002203000, 0.4210617000, 0.4654821000, 0.5495210000, 0.7089084000, 1.0586477000", \ - "0.3959417000, 0.4039525000, 0.4245469000, 0.4692912000, 0.5530651000, 0.7123940000, 1.0622113000", \ - "0.4073216000, 0.4151196000, 0.4358910000, 0.4805323000, 0.5643844000, 0.7237684000, 1.0735529000", \ - "0.4360469000, 0.4439112000, 0.4647832000, 0.5091229000, 0.5932517000, 0.7526583000, 1.1023743000", \ - "0.4983297000, 0.5063830000, 0.5266655000, 0.5712268000, 0.6553519000, 0.8150464000, 1.1643910000", \ - "0.6246162000, 0.6326373000, 0.6533560000, 0.6979478000, 0.7821867000, 0.9420736000, 1.2917496000", \ - "0.8561690000, 0.8659928000, 0.8913408000, 0.9450550000, 1.0417258000, 1.2132165000, 1.5687129000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.2111112000, 0.2176218000, 0.2344747000, 0.2733946000, 0.3623608000, 0.5948536000, 1.3094134000", \ - "0.2142071000, 0.2206863000, 0.2375652000, 0.2764809000, 0.3654451000, 0.5979600000, 1.3124900000", \ - "0.2234833000, 0.2300034000, 0.2468672000, 0.2858752000, 0.3747931000, 0.6076464000, 1.3207474000", \ - "0.2475480000, 0.2540842000, 0.2708834000, 0.3097803000, 0.3986576000, 0.6312986000, 1.3455682000", \ - "0.3010216000, 0.3075517000, 0.3243149000, 0.3632703000, 0.4519089000, 0.6844405000, 1.3962849000", \ - "0.3944582000, 0.4014593000, 0.4194802000, 0.4600396000, 0.5504048000, 0.7840504000, 1.4984308000", \ - "0.5191944000, 0.5275381000, 0.5492431000, 0.5959304000, 0.6926461000, 0.9287534000, 1.6431122000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0813161000, 0.0856184000, 0.0960661000, 0.1189170000, 0.1700967000, 0.2973065000, 0.6712622000", \ - "0.0808674000, 0.0850140000, 0.0958680000, 0.1200844000, 0.1694906000, 0.2987707000, 0.6707734000", \ - "0.0808901000, 0.0855550000, 0.0959758000, 0.1205437000, 0.1698748000, 0.2972034000, 0.6711951000", \ - "0.0813261000, 0.0856467000, 0.0961105000, 0.1188961000, 0.1701453000, 0.2973130000, 0.6711746000", \ - "0.0812792000, 0.0852376000, 0.0954084000, 0.1192894000, 0.1694865000, 0.2985403000, 0.6716577000", \ - "0.0833902000, 0.0871377000, 0.0973502000, 0.1195931000, 0.1702787000, 0.2989316000, 0.6704322000", \ - "0.1289438000, 0.1319010000, 0.1408912000, 0.1573676000, 0.1999018000, 0.3172077000, 0.6787068000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0379938000, 0.0427981000, 0.0563628000, 0.0898369000, 0.1838630000, 0.4885756000, 1.4975342000", \ - "0.0380110000, 0.0427944000, 0.0563697000, 0.0898319000, 0.1838309000, 0.4886328000, 1.4972699000", \ - "0.0385826000, 0.0435062000, 0.0560913000, 0.0899793000, 0.1840248000, 0.4895752000, 1.4933510000", \ - "0.0379394000, 0.0428530000, 0.0563218000, 0.0897923000, 0.1836658000, 0.4891736000, 1.4926874000", \ - "0.0380194000, 0.0428405000, 0.0565211000, 0.0898895000, 0.1841523000, 0.4893476000, 1.4939855000", \ - "0.0426679000, 0.0478656000, 0.0608898000, 0.0948437000, 0.1863998000, 0.4896900000, 1.4932771000", \ - "0.0555771000, 0.0612286000, 0.0760918000, 0.1094835000, 0.1981380000, 0.4949793000, 1.4945495000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.3304060000, 0.3381073000, 0.3584887000, 0.4019846000, 0.4846125000, 0.6424525000, 0.9889227000", \ - "0.3338148000, 0.3415109000, 0.3619573000, 0.4054170000, 0.4880708000, 0.6458044000, 0.9923881000", \ - "0.3420544000, 0.3498934000, 0.3700006000, 0.4135530000, 0.4963163000, 0.6539678000, 1.0004575000", \ - "0.3616680000, 0.3693550000, 0.3897848000, 0.4333457000, 0.5160298000, 0.6735961000, 1.0200784000", \ - "0.4167640000, 0.4246039000, 0.4448156000, 0.4882375000, 0.5708167000, 0.7282088000, 1.0751523000", \ - "0.5092298000, 0.5169315000, 0.5367243000, 0.5796184000, 0.6620680000, 0.8198415000, 1.1670327000", \ - "0.5753296000, 0.5830741000, 0.6025915000, 0.6464571000, 0.7287397000, 0.8858921000, 1.2320102000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.2956955000, 0.3028503000, 0.3213707000, 0.3635744000, 0.4574788000, 0.6948737000, 1.4098583000", \ - "0.2991267000, 0.3062647000, 0.3247521000, 0.3670149000, 0.4609137000, 0.6983548000, 1.4127469000", \ - "0.3105012000, 0.3176068000, 0.3360996000, 0.3785461000, 0.4724202000, 0.7095628000, 1.4240278000", \ - "0.3400231000, 0.3471397000, 0.3655800000, 0.4079009000, 0.5017492000, 0.7389367000, 1.4559838000", \ - "0.4004166000, 0.4075405000, 0.4259885000, 0.4683176000, 0.5621854000, 0.7993630000, 1.5164877000", \ - "0.4875458000, 0.4946844000, 0.5131626000, 0.5552984000, 0.6491797000, 0.8864324000, 1.6036451000", \ - "0.6163299000, 0.6235191000, 0.6421753000, 0.6846593000, 0.7788321000, 1.0157951000, 1.7292532000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0797246000, 0.0835722000, 0.0932900000, 0.1160424000, 0.1655571000, 0.2946646000, 0.6660594000", \ - "0.0797659000, 0.0835682000, 0.0932917000, 0.1160549000, 0.1657782000, 0.2945669000, 0.6662536000", \ - "0.0797172000, 0.0833994000, 0.0938137000, 0.1158883000, 0.1664083000, 0.2946383000, 0.6660740000", \ - "0.0799080000, 0.0836199000, 0.0945086000, 0.1160327000, 0.1672804000, 0.2946825000, 0.6658906000", \ - "0.0795309000, 0.0838047000, 0.0937562000, 0.1155422000, 0.1663230000, 0.2944614000, 0.6666230000", \ - "0.0785307000, 0.0823415000, 0.0929344000, 0.1153422000, 0.1657479000, 0.2955177000, 0.6666457000", \ - "0.0790988000, 0.0825956000, 0.0942297000, 0.1154906000, 0.1662363000, 0.2940989000, 0.6632661000"); - } - related_pin : "B"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0428669000, 0.0481807000, 0.0625082000, 0.0981321000, 0.1926589000, 0.4948079000, 1.4947196000", \ - "0.0428368000, 0.0481196000, 0.0625528000, 0.0980993000, 0.1926903000, 0.4945114000, 1.4942898000", \ - "0.0429179000, 0.0485545000, 0.0624536000, 0.0977714000, 0.1929342000, 0.4948104000, 1.4974290000", \ - "0.0435326000, 0.0487793000, 0.0623014000, 0.0980300000, 0.1924313000, 0.4949904000, 1.5003524000", \ - "0.0433949000, 0.0486259000, 0.0623427000, 0.0980838000, 0.1924500000, 0.4949832000, 1.5003297000", \ - "0.0433178000, 0.0484909000, 0.0621953000, 0.0973008000, 0.1925028000, 0.4946693000, 1.5001579000", \ - "0.0433761000, 0.0486705000, 0.0631600000, 0.0987339000, 0.1928583000, 0.4931774000, 1.4962606000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.2617128000, 0.2694725000, 0.2896366000, 0.3329362000, 0.4153732000, 0.5723828000, 0.9186618000", \ - "0.2662231000, 0.2739302000, 0.2939645000, 0.3374939000, 0.4195975000, 0.5763880000, 0.9233737000", \ - "0.2768493000, 0.2845631000, 0.3044802000, 0.3479926000, 0.4301057000, 0.5868066000, 0.9338701000", \ - "0.3027148000, 0.3105920000, 0.3304433000, 0.3738282000, 0.4557963000, 0.6126213000, 0.9595790000", \ - "0.3592504000, 0.3670950000, 0.3867373000, 0.4297406000, 0.5114247000, 0.6682675000, 1.0150669000", \ - "0.4795433000, 0.4870761000, 0.5072310000, 0.5497747000, 0.6299724000, 0.7857749000, 1.1324801000", \ - "0.6678400000, 0.6773667000, 0.7027664000, 0.7576489000, 0.8566788000, 1.0240662000, 1.3769188000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.1672699000, 0.1743687000, 0.1927873000, 0.2351156000, 0.3287814000, 0.5654304000, 1.2767095000", \ - "0.1716881000, 0.1787273000, 0.1973642000, 0.2394727000, 0.3331345000, 0.5698184000, 1.2845095000", \ - "0.1819844000, 0.1890490000, 0.2074845000, 0.2497587000, 0.3435148000, 0.5802622000, 1.2917980000", \ - "0.2050161000, 0.2120738000, 0.2305227000, 0.2727383000, 0.3665335000, 0.6030428000, 1.3167664000", \ - "0.2573202000, 0.2643711000, 0.2824405000, 0.3243269000, 0.4178594000, 0.6546883000, 1.3694164000", \ - "0.3459023000, 0.3535257000, 0.3729917000, 0.4159372000, 0.5107686000, 0.7494980000, 1.4620638000", \ - "0.4497893000, 0.4589458000, 0.4828555000, 0.5341774000, 0.6348909000, 0.8740570000, 1.5892375000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0752103000, 0.0792753000, 0.0896981000, 0.1127038000, 0.1657491000, 0.2942166000, 0.6657414000", \ - "0.0753458000, 0.0795047000, 0.0902751000, 0.1133809000, 0.1641975000, 0.2924044000, 0.6662745000", \ - "0.0750728000, 0.0793082000, 0.0891743000, 0.1132580000, 0.1640771000, 0.2936256000, 0.6656263000", \ - "0.0744241000, 0.0781821000, 0.0886484000, 0.1143526000, 0.1637151000, 0.2922472000, 0.6663198000", \ - "0.0719145000, 0.0765771000, 0.0870461000, 0.1110551000, 0.1629274000, 0.2935225000, 0.6664184000", \ - "0.0775179000, 0.0804357000, 0.0903687000, 0.1116820000, 0.1619093000, 0.2932101000, 0.6655125000", \ - "0.1040248000, 0.1089356000, 0.1222252000, 0.1498818000, 0.1974572000, 0.3140170000, 0.6770123000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0430184000, 0.0476833000, 0.0619612000, 0.0973470000, 0.1922703000, 0.4943219000, 1.5014645000", \ - "0.0428555000, 0.0480097000, 0.0621808000, 0.0973937000, 0.1922918000, 0.4947988000, 1.5005543000", \ - "0.0429909000, 0.0479599000, 0.0624328000, 0.0974189000, 0.1922818000, 0.4940919000, 1.5004191000", \ - "0.0429328000, 0.0484058000, 0.0621073000, 0.0973829000, 0.1924609000, 0.4947015000, 1.4971341000", \ - "0.0419470000, 0.0469733000, 0.0617108000, 0.0972544000, 0.1923861000, 0.4943252000, 1.5006200000", \ - "0.0513592000, 0.0563817000, 0.0694290000, 0.1033464000, 0.1965807000, 0.4960563000, 1.5035794000", \ - "0.0713813000, 0.0772680000, 0.0930001000, 0.1240501000, 0.2096869000, 0.5024105000, 1.4980949000"); - } - timing_sense : "positive_unate"; - timing_type : "combinational"; - } - timing () { - cell_fall ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.2702284000, 0.2780798000, 0.2988752000, 0.3433368000, 0.4271595000, 0.5867558000, 0.9357763000", \ - "0.2753913000, 0.2834272000, 0.3039085000, 0.3482792000, 0.4324426000, 0.5914410000, 0.9409362000", \ - "0.2861505000, 0.2941537000, 0.3148203000, 0.3591118000, 0.4431729000, 0.6025603000, 0.9517890000", \ - "0.3098450000, 0.3177466000, 0.3384889000, 0.3829988000, 0.4669171000, 0.6263888000, 0.9756635000", \ - "0.3541352000, 0.3620250000, 0.3825175000, 0.4264947000, 0.5102894000, 0.6694479000, 1.0185058000", \ - "0.4423516000, 0.4491715000, 0.4671696000, 0.5072536000, 0.5859872000, 0.7429967000, 1.0920650000", \ - "0.4818076000, 0.4886616000, 0.5068093000, 0.5469793000, 0.6259918000, 0.7827688000, 1.1298008000"); - } - cell_rise ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.1932084000, 0.1996519000, 0.2164941000, 0.2552749000, 0.3438883000, 0.5765253000, 1.2912347000", \ - "0.1982211000, 0.2047014000, 0.2215532000, 0.2602948000, 0.3489170000, 0.5816450000, 1.2967565000", \ - "0.2115757000, 0.2179944000, 0.2348895000, 0.2735657000, 0.3622000000, 0.5950190000, 1.3100904000", \ - "0.2435475000, 0.2499723000, 0.2667747000, 0.3056006000, 0.3942633000, 0.6271560000, 1.3401703000", \ - "0.3105100000, 0.3169758000, 0.3338047000, 0.3725772000, 0.4612031000, 0.6938234000, 1.4086374000", \ - "0.4192081000, 0.4257404000, 0.4423321000, 0.4810147000, 0.5690016000, 0.8021610000, 1.5151341000", \ - "0.5862942000, 0.5927550000, 0.6092866000, 0.6480869000, 0.7366237000, 0.9688568000, 1.6820718000"); - } - fall_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0812541000, 0.0851702000, 0.0958330000, 0.1182894000, 0.1687955000, 0.2985516000, 0.6711479000", \ - "0.0806482000, 0.0845520000, 0.0950796000, 0.1183363000, 0.1698090000, 0.2985583000, 0.6706864000", \ - "0.0803335000, 0.0848628000, 0.0952509000, 0.1181709000, 0.1686246000, 0.2981487000, 0.6697789000", \ - "0.0804499000, 0.0843566000, 0.0949782000, 0.1179081000, 0.1686894000, 0.2978058000, 0.6714420000", \ - "0.0758599000, 0.0798206000, 0.0907151000, 0.1146699000, 0.1693041000, 0.2976116000, 0.6711181000", \ - "0.0677050000, 0.0716229000, 0.0825907000, 0.1064535000, 0.1609131000, 0.2948327000, 0.6701933000", \ - "0.0687189000, 0.0725467000, 0.0830315000, 0.1088921000, 0.1616501000, 0.2919935000, 0.6629990000"); - } - related_pin : "C"; - rise_transition ("del_1_7_7") { - index_1("0.0100000000, 0.0230506000, 0.0531329000, 0.1224740000, 0.2823110000, 0.6507430000, 1.5000000000"); - index_2("0.0005000000, 0.0015844400, 0.0050209000, 0.0159106000, 0.0504189000, 0.1597710000, 0.5062960000"); - values("0.0381354000, 0.0431550000, 0.0557474000, 0.0894886000, 0.1835407000, 0.4887629000, 1.4983069000", \ - "0.0382841000, 0.0431008000, 0.0558681000, 0.0895289000, 0.1836433000, 0.4889424000, 1.4994218000", \ - "0.0378636000, 0.0430683000, 0.0560167000, 0.0894731000, 0.1837949000, 0.4892784000, 1.4981292000", \ - "0.0377661000, 0.0424752000, 0.0560652000, 0.0895167000, 0.1840525000, 0.4899186000, 1.4928372000", \ - "0.0382293000, 0.0430367000, 0.0557163000, 0.0892529000, 0.1834981000, 0.4890026000, 1.5021226000", \ - "0.0373885000, 0.0425606000, 0.0558010000, 0.0891452000, 0.1833518000, 0.4889457000, 1.4991330000", \ - "0.0381850000, 0.0428619000, 0.0561597000, 0.0898340000, 0.1837796000, 0.4882866000, 1.4945289000"); - } - timing_sense : "negative_unate"; - timing_type : "combinational"; - } - } - } - default_operating_conditions : "tt_025C_1v80"; - -} diff --git a/flow/platforms/sky130hd_fakestack/pdn.tcl b/flow/platforms/sky130hd_fakestack/pdn.tcl deleted file mode 100644 index 1901913015..0000000000 --- a/flow/platforms/sky130hd_fakestack/pdn.tcl +++ /dev/null @@ -1,39 +0,0 @@ -#################################### -# global connections -#################################### -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR} -add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPB} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND} -add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VNB} -global_connect -#################################### -# voltage domains -#################################### -set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} -#################################### -# standard cell grid -#################################### -define_pdn_grid -name {grid} -voltage_domains {CORE} -add_pdn_stripe -grid {grid} -layer {met1} -width {0.48} -pitch {5.44} -offset {0} -followpins -add_pdn_stripe -grid {grid} -layer {met4} -width {1.600} -pitch {27.140} -offset {13.570} -add_pdn_stripe -grid {grid} -layer {met5} -width {1.600} -pitch {27.200} -offset {13.600} -add_pdn_connect -grid {grid} -layers {met1 met4} -add_pdn_connect -grid {grid} -layers {met4 met5} -#################################### -# macro grids -#################################### -#################################### -# grid for: CORE_macro_grid_1 -#################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary -add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} -#################################### -# grid for: CORE_macro_grid_2 -#################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary -add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/platforms/sky130hd_fakestack/rcx_patterns.rules b/flow/platforms/sky130hd_fakestack/rcx_patterns.rules deleted file mode 120000 index 7f7fe1ca66..0000000000 --- a/flow/platforms/sky130hd_fakestack/rcx_patterns.rules +++ /dev/null @@ -1 +0,0 @@ -../sky130hs/rcx_patterns.rules \ No newline at end of file diff --git a/flow/platforms/sky130hd_fakestack/setRC.tcl b/flow/platforms/sky130hd_fakestack/setRC.tcl deleted file mode 100644 index 547add7dc3..0000000000 --- a/flow/platforms/sky130hd_fakestack/setRC.tcl +++ /dev/null @@ -1,28 +0,0 @@ -# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier -# cap units pf/um -set_layer_rc -layer li1 -capacitance 1.499e-04 -resistance 7.176e-02 -set_layer_rc -layer met1 -capacitance 1.72375E-04 -resistance 8.929e-04 -set_layer_rc -layer met2 -capacitance 1.36233E-04 -resistance 8.929e-04 -set_layer_rc -layer met3 -capacitance 2.14962E-04 -resistance 1.567e-04 -set_layer_rc -layer met4 -capacitance 1.48128E-04 -resistance 1.567e-04 -set_layer_rc -layer met5 -capacitance 1.54087E-04 -resistance 1.781e-05 -# RV temp values -- need correlation -set_layer_rc -layer met6 -capacitance 1.54087E-04 -resistance 1.781e-05 -set_layer_rc -layer met7 -capacitance 1.54087E-04 -resistance 1.781e-05 -set_layer_rc -layer met8 -capacitance 1.54087E-04 -resistance 1.781e-05 -set_layer_rc -layer met9 -capacitance 1.54087E-04 -resistance 1.781e-05 -# end correlate - -set_layer_rc -via mcon -resistance 9.249146E-3 -set_layer_rc -via via -resistance 4.5E-3 -set_layer_rc -via via2 -resistance 3.368786E-3 -set_layer_rc -via via3 -resistance 0.376635E-3 -set_layer_rc -via via4 -resistance 0.00580E-3 -# RV temp values -- need correlation -set_layer_rc -via via5 -resistance 0.00580E-3 -set_layer_rc -via via6 -resistance 0.00580E-3 -set_layer_rc -via via7 -resistance 0.00580E-3 -set_layer_rc -via via8 -resistance 0.00580E-3 - -set_wire_rc -signal -layer met2 -set_wire_rc -clock -layer met5 diff --git a/flow/platforms/sky130hd_fakestack/sky130hd.lyp b/flow/platforms/sky130hd_fakestack/sky130hd.lyp deleted file mode 100644 index 738ec7059e..0000000000 --- a/flow/platforms/sky130hd_fakestack/sky130hd.lyp +++ /dev/null @@ -1,8496 +0,0 @@ - - - - #ccccd9 - #ccccd9 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - prBoundary.boundary - 235/4 - 235/4@1 - - - #00ffff - #00ffff - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - pwell.drawing - 64/44 - 64/44@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C38 - C0 - true - true - false - 1 - false - false - 0 - pwell.pin - 122/16 - 122/16@1 - - - #9900e6 - #9900e6 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - pwell.label - 64/59 - 64/59@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - pwell.res - 64/13 - 64/13@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - pwell.cut - 64/14 - 64/14@1 - - - #ffffff - #96c8ff - 0 - 0 - C38 - C0 - true - true - false - 1 - false - false - 0 - pwelliso.pin - 44/16 - 44/16@1 - - - #9900e6 - #9900e6 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - pwelliso.label - 44/5 - 44/5@1 - - - #00cc66 - #00cc66 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - nwell.drawing - 64/20 - 64/20@1 - - - #ff00ff - #ff00ff - 0 - 0 - C2 - C0 - true - true - false - 1 - false - false - 0 - nwell.net - 84/23 - 84/23@1 - - - #268c6b - #268c6b - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - nwell.pin - 64/16 - 64/16@1 - - - #333399 - #333399 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - nwell.label - 64/5 - 64/5@1 - - - #c8ffc8 - #c8ffc8 - 0 - 0 - C47 - C0 - true - true - false - 1 - false - false - 0 - dnwell.drawing - 64/18 - 64/18@1 - - - #00ffff - #00ffff - 0 - 0 - C6 - C0 - true - true - false - 1 - false - false - 0 - vhvi.drawing - 74/21 - 74/21@1 - - - #00ff00 - #00ff00 - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - diff.drawing - 65/20 - 65/20@1 - - - #00ff00 - #00ff00 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - diff.res - 65/13 - 65/13@1 - - - #00ff00 - #00ff00 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - diff.cut - 65/14 - 65/14@1 - - - #268c6b - #268c6b - 0 - 0 - C36 - C0 - false - true - false - 1 - false - false - 0 - diff.pin - 65/16 - 65/16@1 - - - #c8ffc8 - #c8ffc8 - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - diff.label - 65/6 - 65/6@1 - - - #00ff00 - #00ff00 - 0 - 0 - C5 - C0 - false - true - false - 1 - false - false - 0 - diff.net - 65/23 - 65/23@1 - - - #00ff00 - #00ff00 - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - diff.boundary - 65/4 - 65/4@1 - - - #9900e6 - #9900e6 - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - diff.hv - 65/8 - 65/8@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - tap.drawing - 65/44 - 65/44@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - tap.pin - 65/48 - 65/48@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C5 - C0 - false - true - false - 1 - false - false - 0 - tap.net - 65/41 - 65/41@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - tap.boundary - 65/60 - 65/60@1 - - - #fff464 - #fff464 - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - tap.label - 65/5 - 65/5@1 - - - #9900e6 - #9900e6 - 0 - 0 - C22 - C0 - true - true - false - 1 - false - false - 0 - psdm.drawing - 94/20 - 94/20@1 - - - #e61f0d - #e61f0d - 0 - 0 - C21 - C0 - true - true - false - 1 - false - false - 0 - nsdm.drawing - 93/44 - 93/44@1 - - - #ff0000 - #ff0000 - 0 - 0 - C41 - C0 - true - true - false - 1 - false - false - 0 - poly.drawing - 66/20 - 66/20@1 - - - #ff8000 - #ff8000 - 0 - 0 - C38 - C0 - true - true - false - 1 - false - false - 0 - poly.pin - 66/16 - 66/16@1 - - - #ff0000 - #ff0000 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - poly.res - 66/13 - 66/13@1 - - - #ff0000 - #ff0000 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - poly.cut - 66/14 - 66/14@1 - - - #ff0000 - #ff0000 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - poly.gate - 66/9 - 66/9@1 - - - #ffafaf - #ffafaf - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - poly.label - 66/5 - 66/5@1 - - - #ff0000 - #ff0000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - poly.boundary - 66/4 - 66/4@1 - - - #ff0000 - #ff0000 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - poly.probe - 66/25 - 66/25@1 - - - #ff0000 - #ff0000 - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - poly.short - 66/15 - 66/15@1 - - - #ff0000 - #ff0000 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - poly.net - 66/23 - 66/23@1 - - - #ff0000 - #ff0000 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - poly.model - 66/83 - 66/83@1 - - - #00cc66 - #00cc66 - 0 - 0 - C50 - C0 - true - true - false - 1 - false - false - 0 - ldntm.drawing - 11/44 - 11/44@1 - - - #96c8ff - #ffffff - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - lvtn.drawing - 125/44 - 125/44@1 - - - #ff8000 - #ffffff - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - hvtp.drawing - 78/44 - 78/44@1 - - - #ff0000 - #e61f0d - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - hvtr.drawing - 18/20 - 18/20@1 - - - #9900e6 - #9900e6 - 0 - 0 - C41 - C0 - true - true - false - 1 - false - false - 0 - tunm.drawing - 80/20 - 80/20@1 - - - #ffffcc - #ffffcc - 0 - 0 - C23 - C0 - true - true - false - 1 - false - false - 0 - licon1.drawing - 66/44 - 66/44@1 - - - #ffffcc - #ffffcc - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - licon1.boundary - 66/60 - 66/60@1 - - - #ffe6bf - #c8ffff - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - licon1.pin - 66/58 - 66/58@1 - - - #ffffcc - #ffffcc - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - licon1.net - 66/41 - 66/41@1 - - - #bf4026 - #bf4026 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - npc.drawing - 95/20 - 95/20@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - li1.drawing - 67/20 - 67/20@1 - - - #bf4026 - #bf4026 - 0 - 0 - C46 - C0 - true - true - false - 1 - false - false - 0 - li1.pin - 67/16 - 67/16@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - li1.res - 67/13 - 67/13@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - li1.cut - 67/14 - 67/14@1 - - - #bf4026 - #bf4026 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - li1.label - 67/5 - 67/5@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - li1.net - 67/23 - 67/23@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - li1.boundary - 67/4 - 67/4@1 - - - #bf4026 - #bf4026 - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - li1.blockage - 67/10 - 67/10@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - li1.short - 67/15 - 67/15@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - li1.probe - 67/25 - 67/25@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - mcon.drawing - 67/44 - 67/44@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - mcon.boundary - 67/60 - 67/60@1 - - - #ffffcc - #d9e6ff - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - mcon.pin - 67/48 - 67/48@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - mcon.net - 67/41 - 67/41@1 - - - #0000ff - #0000ff - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.drawing - 68/20 - 68/20@1 - - - #0000ff - #0000ff - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met1.res - 68/13 - 68/13@1 - - - #0000ff - #0000ff - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - met1.cut - 68/14 - 68/14@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C6 - C0 - true - true - false - 1 - false - false - 0 - met1.pin - 68/16 - 68/16@1 - - - #96c8ff - #96c8ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met1.label - 68/5 - 68/5@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - met1.net - 68/23 - 68/23@1 - - - #0000ff - #0000ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - met1.boundary - 68/4 - 68/4@1 - - - #0000ff - #0000ff - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - met1.blockage - 68/10 - 68/10@1 - - - #0000ff - #0000ff - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - met1.short - 68/15 - 68/15@1 - - - #0000ff - #0000ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met1.probe - 68/25 - 68/25@1 - - - #0000ff - #0000ff - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - met1.option1 - 68/32 - 68/32@1 - - - #0000ff - #0000ff - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - met1.option2 - 68/33 - 68/33@1 - - - #0000ff - #0000ff - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - met1.option3 - 68/34 - 68/34@1 - - - #0000ff - #0000ff - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - met1.option4 - 68/35 - 68/35@1 - - - #0000ff - #0000ff - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - met1.option5 - 68/36 - 68/36@1 - - - #0000ff - #0000ff - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - met1.option6 - 68/37 - 68/37@1 - - - #0000ff - #0000ff - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - met1.option7 - 68/38 - 68/38@1 - - - #0000ff - #0000ff - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - met1.option8 - 68/39 - 68/39@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - via.drawing - 68/44 - 68/44@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - via.boundary - 68/60 - 68/60@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - via.net - 68/41 - 68/41@1 - - - #ae7dff - #ae7dff - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - via.pin - 68/58 - 68/58@1 - - - #ff00ff - #ff00ff - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.drawing - 69/20 - 69/20@1 - - - #ff00ff - #ff00ff - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met2.res - 69/13 - 69/13@1 - - - #ff00ff - #ff00ff - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - met2.cut - 69/14 - 69/14@1 - - - #ff00ff - #ff00ff - 0 - 0 - C45 - C0 - true - true - false - 1 - false - false - 0 - met2.pin - 69/16 - 69/16@1 - - - #ffc8ff - #ffc8ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met2.label - 69/5 - 69/5@1 - - - #ff00ff - #ff00ff - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - met2.net - 69/23 - 69/23@1 - - - #ff00ff - #ff00ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - met2.boundary - 69/4 - 69/4@1 - - - #ff00ff - #ff00ff - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - met2.blockage - 69/10 - 69/10@1 - - - #ff00ff - #ff00ff - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - met2.short - 69/15 - 69/15@1 - - - #ff00ff - #ff00ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met2.probe - 69/25 - 69/25@1 - - - #ff00ff - #ff00ff - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - met2.option1 - 69/32 - 69/32@1 - - - #ff00ff - #ff00ff - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - met2.option2 - 69/33 - 69/33@1 - - - #ff00ff - #ff00ff - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - met2.option3 - 69/34 - 69/34@1 - - - #ff00ff - #ff00ff - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - met2.option4 - 69/35 - 69/35@1 - - - #ff00ff - #ff00ff - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - met2.option5 - 69/36 - 69/36@1 - - - #ff00ff - #ff00ff - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - met2.option6 - 69/37 - 69/37@1 - - - #ff00ff - #ff00ff - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - met2.option7 - 69/38 - 69/38@1 - - - #ff00ff - #ff00ff - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - met2.option8 - 69/39 - 69/39@1 - - - #ff8000 - #ff8000 - 0 - 0 - I1 - C0 - true - true - false - 3 - false - false - 0 - via2.drawing - 69/44 - 69/44@1 - - - #ff8000 - #ff8000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - via2.boundary - 69/60 - 69/60@1 - - - #ff8000 - #ff8000 - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - via2.pin - 69/58 - 69/58@1 - - - #ff8000 - #ff8000 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - via2.net - 69/41 - 69/41@1 - - - #00ffff - #00ffff - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.drawing - 70/20 - 70/20@1 - - - #00ffff - #00ffff - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met3.res - 70/13 - 70/13@1 - - - #00ffff - #00ffff - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - met3.cut - 70/14 - 70/14@1 - - - #00ffff - #00ffff - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - met3.pin - 70/16 - 70/16@1 - - - #c8ffff - #c8ffff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met3.label - 70/5 - 70/5@1 - - - #00ffff - #00ffff - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - met3.net - 70/23 - 70/23@1 - - - #00ffff - #00ffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - met3.boundary - 70/4 - 70/4@1 - - - #00ffff - #00ffff - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - met3.blockage - 70/10 - 70/10@1 - - - #00ffff - #00ffff - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - met3.short - 70/15 - 70/15@1 - - - #00ffff - #00ffff - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met3.fuse - 70/17 - 70/17@1 - - - #00ffff - #00ffff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met3.probe - 70/25 - 70/25@1 - - - #00ffff - #00ffff - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - met3.option1 - 70/32 - 70/32@1 - - - #00ffff - #00ffff - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - met3.option2 - 70/33 - 70/33@1 - - - #00ffff - #00ffff - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - met3.option3 - 70/34 - 70/34@1 - - - #00ffff - #00ffff - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - met3.option4 - 70/35 - 70/35@1 - - - #00ffff - #00ffff - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - met3.option5 - 70/36 - 70/36@1 - - - #00ffff - #00ffff - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - met3.option6 - 70/37 - 70/37@1 - - - #00ffff - #00ffff - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - met3.option7 - 70/38 - 70/38@1 - - - #00ffff - #00ffff - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - met3.option8 - 70/39 - 70/39@1 - - - #268c6b - #268c6b - 0 - 0 - I1 - C0 - true - true - false - 3 - false - false - 0 - via3.drawing - 70/44 - 70/44@1 - - - #268c6b - #268c6b - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - via3.boundary - 70/60 - 70/60@1 - - - #268c6b - #268c6b - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - via3.pin - 70/48 - 70/48@1 - - - #268c6b - #268c6b - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - via3.net - 70/41 - 70/41@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.drawing - 71/20 - 71/20@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met4.res - 71/13 - 71/13@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - met4.cut - 71/14 - 71/14@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - met4.pin - 71/16 - 71/16@1 - - - #ae7dff - #ae7dff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met4.label - 71/5 - 71/5@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - met4.net - 71/23 - 71/23@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - met4.boundary - 71/4 - 71/4@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - met4.blockage - 71/10 - 71/10@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - met4.short - 71/15 - 71/15@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met4.fuse - 71/17 - 71/17@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met4.probe - 71/25 - 71/25@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - met4.option1 - 71/32 - 71/32@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - met4.option2 - 71/33 - 71/33@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - met4.option3 - 71/34 - 71/34@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - met4.option4 - 71/35 - 71/35@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - met4.option5 - 71/36 - 71/36@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - met4.option6 - 71/37 - 71/37@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - met4.option7 - 71/38 - 71/38@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - met4.option8 - 71/39 - 71/39@1 - - - #ffff00 - #ffff00 - 0 - 0 - I1 - C0 - true - true - false - 3 - false - false - 0 - via4.drawing - 71/44 - 71/44@1 - - - #ffff00 - #ffff00 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - via4.boundary - 71/60 - 71/60@1 - - - #ffff00 - #ffff00 - 0 - 0 - C6 - C0 - false - true - false - 1 - false - false - 0 - via4.pin - 71/48 - 71/48@1 - - - #ffff00 - #ffff00 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - via4.net - 71/41 - 71/41@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.drawing - 72/20 - 72/20@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met5.res - 72/13 - 72/13@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C1 - C0 - false - true - false - 1 - false - false - 0 - met5.cut - 72/14 - 72/14@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - met5.pin - 72/16 - 72/16@1 - - - #fff464 - #fff464 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met5.label - 72/5 - 72/5@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C5 - C0 - true - true - false - 1 - false - false - 0 - met5.net - 72/23 - 72/23@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - met5.boundary - 72/4 - 72/4@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C53 - C0 - true - true - false - 1 - false - false - 0 - met5.blockage - 72/10 - 72/10@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C36 - C0 - true - true - false - 1 - false - false - 0 - met5.short - 72/15 - 72/15@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - I1 - C0 - false - true - false - 1 - false - false - 0 - met5.fuse - 72/17 - 72/17@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - met5.probe - 72/25 - 72/25@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - met5.option1 - 72/32 - 72/32@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - met5.option2 - 72/33 - 72/33@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - met5.option3 - 72/34 - 72/34@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - met5.option4 - 72/35 - 72/35@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - met5.option5 - 72/36 - 72/36@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - met5.option6 - 72/37 - 72/37@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - met5.option7 - 72/38 - 72/38@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - met5.option8 - 72/39 - 72/39@1 - - - #00cc66 - #00cc66 - 0 - 0 - C50 - C0 - true - true - false - 1 - false - false - 0 - nsm.drawing - 61/20 - 61/20@1 - - - #ffffcc - #ffffcc - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - pad.drawing - 76/20 - 76/20@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - pad.label - 76/5 - 76/5@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - pad.pin - 76/16 - 76/16@1 - - - #ff00ff - #ff00ff - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - pnp.drawing - 82/44 - 82/44@1 - - - #ffc8ff - #ffc8ff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - pnp.label - 82/59 - 82/59@1 - - - #00ffff - #00ffff - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - npn.drawing - 82/20 - 82/20@1 - - - #c8ffff - #c8ffff - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - npn.label - 82/5 - 82/5@1 - - - #ffffff - #96c8ff - 0 - 0 - C38 - C0 - true - true - false - 1 - false - false - 0 - rpm.drawing - 86/20 - 86/20@1 - - - #9900e6 - #9900e6 - 0 - 0 - C4 - C0 - true - true - false - 1 - false - false - 0 - hvi.drawing - 75/20 - 75/20@1 - - - #ffb232 - #ffb232 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - capacitor.drawing - 82/64 - 82/64@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - ncm.drawing - 92/44 - 92/44@1 - - - #ff8000 - #ff8000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - cncm.drawing - 96/44 - 96/44@1 - - - #ff0000 - #ff0000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - cncm.mask - 17/0 - 17/0@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C20 - C1 - true - true - false - 1 - false - false - 0 - pmm.drawing - 85/44 - 85/44@1 - - - #bf4026 - #bf4026 - 0 - 0 - C40 - C0 - true - true - false - 1 - false - false - 0 - pmm2.drawing - 77/20 - 77/20@1 - - - #e61f0d - #e61f0d - 0 - 0 - C47 - C0 - true - true - false - 1 - false - false - 0 - rdl.drawing - 74/20 - 74/20@1 - - - #e61f0d - #e61f0d - 0 - 0 - C34 - C0 - true - true - false - 1 - false - false - 0 - rdl.pin - 74/16 - 74/16@1 - - - #ff6464 - #ff6464 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - rdl.label - 74/5 - 74/5@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - rdl.res - 74/13 - 74/13@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - rdl.cut - 74/14 - 74/14@1 - - - #e61f0d - #e61f0d - 0 - 0 - C36 - C0 - false - true - false - 1 - false - false - 0 - rdl.short - 74/15 - 74/15@1 - - - #e61f0d - #e61f0d - 0 - 0 - C25 - C0 - false - true - false - 1 - false - false - 0 - rdl.option1 - 89/32 - 89/32@1 - - - #e61f0d - #e61f0d - 0 - 0 - C26 - C0 - false - true - false - 1 - false - false - 0 - rdl.option2 - 89/33 - 89/33@1 - - - #e61f0d - #e61f0d - 0 - 0 - C27 - C0 - false - true - false - 1 - false - false - 0 - rdl.option3 - 89/34 - 89/34@1 - - - #e61f0d - #e61f0d - 0 - 0 - C28 - C0 - false - true - false - 1 - false - false - 0 - rdl.option4 - 89/35 - 89/35@1 - - - #e61f0d - #e61f0d - 0 - 0 - C29 - C0 - false - true - false - 1 - false - false - 0 - rdl.option5 - 89/36 - 89/36@1 - - - #e61f0d - #e61f0d - 0 - 0 - C30 - C0 - false - true - false - 1 - false - false - 0 - rdl.option6 - 89/37 - 89/37@1 - - - #e61f0d - #e61f0d - 0 - 0 - C31 - C0 - false - true - false - 1 - false - false - 0 - rdl.option7 - 89/38 - 89/38@1 - - - #e61f0d - #e61f0d - 0 - 0 - C32 - C0 - false - true - false - 1 - false - false - 0 - rdl.option8 - 89/39 - 89/39@1 - - - #ccccd9 - #333399 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - ubm.drawing - 127/21 - 127/21@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - bump.drawing - 127/22 - 127/22@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - inductor.drawing - 82/24 - 82/24@1 - - - #fff464 - #fff464 - 0 - 0 - C1 - C0 - true - true - false - 1 - false - false - 0 - inductor.label - 82/25 - 82/25@1 - - - #333399 - #ffffff - 0 - 0 - C25 - C0 - true - true - false - 1 - false - false - 0 - inductor.term1 - 82/26 - 82/26@1 - - - #333399 - #ffffff - 0 - 0 - C26 - C0 - true - true - false - 1 - false - false - 0 - inductor.term2 - 82/27 - 82/27@1 - - - #333399 - #ffffff - 0 - 0 - C27 - C0 - true - true - false - 1 - false - false - 0 - inductor.term3 - 82/28 - 82/28@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - cfom.drawing - 22/20 - 22/20@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cfom.mask - 23/0 - 23/0@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cfom.maskAdd - 22/21 - 22/21@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cfom.maskDrop - 22/22 - 22/22@1 - - - #268c6b - #268c6b - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cfom.waffleDrop - 22/24 - 22/24@1 - - - #ccccd9 - #ccccd9 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - fom.dummy - 22/23 - 22/23@1 - - - #268c6b - #268c6b - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cnwm.drawing - 109/44 - 109/44@1 - - - #268c6b - #268c6b - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cnwm.mask - 21/0 - 21/0@1 - - - #268c6b - #268c6b - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cnwm.maskAdd - 109/43 - 109/43@1 - - - #268c6b - #268c6b - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cnwm.maskDrop - 109/42 - 109/42@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - cdnm.drawing - 110/20 - 110/20@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cdnm.mask - 48/0 - 48/0@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cdnm.maskAdd - 110/21 - 110/21@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - cdnm.maskDrop - 110/22 - 110/22@1 - - - #96c8ff - #ffffcc - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - clvtnm.drawing - 25/44 - 25/44@1 - - - #96c8ff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - clvtnm.mask - 25/0 - 25/0@1 - - - #96c8ff - #ffffff - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - clvtnm.maskAdd - 25/43 - 25/43@1 - - - #96c8ff - #0000ff - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - clvtnm.maskDrop - 25/42 - 25/42@1 - - - #ff8000 - #ffffcc - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - chvtpm.drawing - 88/44 - 88/44@1 - - - #ff8000 - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - chvtpm.mask - 97/0 - 97/0@1 - - - #ff8000 - #ffffff - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - chvtpm.maskAdd - 97/43 - 97/43@1 - - - #ff8000 - #0000ff - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - chvtpm.maskDrop - 97/42 - 97/42@1 - - - #ff0000 - #d9e6ff - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - chvtrm.drawing - 98/44 - 98/44@1 - - - #ff0000 - #e61f0d - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - chvtrm.mask - 98/0 - 98/0@1 - - - #ff0000 - #e61f0d - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - chvtrm.maskAdd - 98/43 - 98/43@1 - - - #ff0000 - #d9e6ff - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - chvtrm.maskDrop - 98/42 - 98/42@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - ctunm.drawing - 96/20 - 96/20@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - ctunm.mask - 20/0 - 20/0@1 - - - #ffffff - #ffffff - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - ctunm.maskAdd - 96/21 - 96/21@1 - - - #ffffff - #ffffff - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - ctunm.maskDrop - 96/22 - 96/22@1 - - - #ff0000 - #ff0000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - conom.drawing - 87/44 - 87/44@1 - - - #ff0000 - #ff0000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - conom.mask - 88/0 - 88/0@1 - - - #ff0000 - #ff0000 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - conom.maskAdd - 87/43 - 87/43@1 - - - #ff0000 - #ff0000 - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - conom.maskDrop - 87/42 - 87/42@1 - - - #00cc66 - #00cc66 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - cnsdm.drawing - 29/20 - 29/20@1 - - - #00cc66 - #00cc66 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cnsdm.mask - 30/0 - 30/0@1 - - - #00cc66 - #00cc66 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cnsdm.maskAdd - 29/21 - 29/21@1 - - - #00cc66 - #00cc66 - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cnsdm.maskDrop - 29/22 - 29/22@1 - - - #ffff00 - #ffff00 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - cpsdm.drawing - 31/20 - 31/20@1 - - - #ffff00 - #ffff00 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cpsdm.mask - 32/0 - 32/0@1 - - - #ffff00 - #ffff00 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cpsdm.maskAdd - 31/21 - 31/21@1 - - - #ffff00 - #ffff00 - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cpsdm.maskDrop - 31/22 - 31/22@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - cntm.drawing - 26/20 - 26/20@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cntm.mask - 27/0 - 27/0@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cntm.maskAdd - 26/21 - 26/21@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cntm.maskDrop - 26/22 - 26/22@1 - - - #ffff00 - #ffff00 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - hvntm.drawing - 125/20 - 125/20@1 - - - #fff5e6 - #fff5e6 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - chvntm.drawing - 38/20 - 38/20@1 - - - #fff5e6 - #fff5e6 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - chvntm.mask - 39/0 - 39/0@1 - - - #fff5e6 - #fff5e6 - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - chvntm.maskAdd - 38/21 - 38/21@1 - - - #fff5e6 - #fff5e6 - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - chvntm.maskDrop - 38/22 - 38/22@1 - - - #00cc66 - #00cc66 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cldntm.drawing - 11/20 - 11/20@1 - - - #00cc66 - #00cc66 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cldntm.mask - 11/0 - 11/0@1 - - - #ff8000 - #ff8000 - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - clvom.drawing - 45/20 - 45/20@1 - - - #268c6b - #268c6b - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - clvom.mask - 46/0 - 46/0@1 - - - #268c6b - #268c6b - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - clvom.maskAdd - 45/21 - 45/21@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - clvom.maskDrop - 45/22 - 45/22@1 - - - #ff8000 - #ff8000 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cp1m.drawing - 33/44 - 33/44@1 - - - #ff8000 - #ff8000 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cp1m.mask - 28/0 - 28/0@1 - - - #ff8000 - #ff8000 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cp1m.maskAdd - 33/43 - 33/43@1 - - - #9900e6 - #9900e6 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cp1m.waffleDrop - 33/24 - 33/24@1 - - - #ff8000 - #ff8000 - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cp1m.maskDrop - 33/42 - 33/42@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cli1m.drawing - 115/44 - 115/44@1 - - - #00ffff - #00ffff - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cli1m.mask - 56/0 - 56/0@1 - - - #00ffff - #00ffff - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cli1m.maskAdd - 115/43 - 115/43@1 - - - #00ffff - #00ffff - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - cli1m.maskDrop - 115/42 - 115/42@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - clicm1.drawing - 106/44 - 106/44@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - clicm1.mask - 43/0 - 43/0@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - clicm1.maskAdd - 106/43 - 106/43@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - clicm1.maskDrop - 106/42 - 106/42@1 - - - #0000ff - #0000ff - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cmm1.drawing - 62/20 - 62/20@1 - - - #0000ff - #0000ff - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cmm1.mask - 36/0 - 36/0@1 - - - #0000ff - #0000ff - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cmm1.maskAdd - 62/21 - 62/21@1 - - - #0000ff - #0000ff - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cmm1.maskDrop - 62/22 - 62/22@1 - - - #0000ff - #0000ff - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cmm1.waffleDrop - 62/24 - 62/24@1 - - - #ffffcc - #ffffcc - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cviam.drawing - 105/20 - 105/20@1 - - - #ffffcc - #ffffcc - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cviam.mask - 40/0 - 40/0@1 - - - #ffffcc - #ffffcc - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cviam.maskAdd - 105/21 - 105/21@1 - - - #ffffcc - #ffffcc - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cviam.maskDrop - 105/22 - 105/22@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cmm2.drawing - 105/44 - 105/44@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cmm2.mask - 41/0 - 41/0@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cmm2.maskAdd - 105/43 - 105/43@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cmm2.maskDrop - 105/42 - 105/42@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cmm2.waffleDrop - 105/52 - 105/52@1 - - - #333399 - #333399 - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cviam2.drawing - 108/20 - 108/20@1 - - - #333399 - #333399 - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cviam2.mask - 44/0 - 44/0@1 - - - #333399 - #333399 - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cviam2.maskAdd - 108/21 - 108/21@1 - - - #333399 - #333399 - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cviam2.maskDrop - 108/22 - 108/22@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cmm3.drawing - 107/20 - 107/20@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cmm3.mask - 34/0 - 34/0@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cmm3.maskAdd - 107/21 - 107/21@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cmm3.maskDrop - 107/22 - 107/22@1 - - - #5e00e6 - #5e00e6 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cmm3.waffleDrop - 107/24 - 107/24@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - cnpc.drawing - 44/20 - 44/20@1 - - - #e61f0d - #e61f0d - 0 - 0 - C39 - C0 - true - true - false - 1 - false - false - 0 - cnpc.mask - 49/0 - 49/0@1 - - - #e61f0d - #e61f0d - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cnpc.maskAdd - 44/43 - 44/43@1 - - - #e61f0d - #e61f0d - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cnpc.maskDrop - 44/42 - 44/42@1 - - - #268c6b - #268c6b - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cviam3.drawing - 112/20 - 112/20@1 - - - #268c6b - #268c6b - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cviam3.mask - 50/0 - 50/0@1 - - - #268c6b - #268c6b - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cviam3.maskAdd - 112/21 - 112/21@1 - - - #268c6b - #268c6b - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cviam3.maskDrop - 112/22 - 112/22@1 - - - #00cc66 - #00cc66 - 0 - 0 - C20 - C0 - true - true - false - 1 - false - false - 0 - cnsm.mask - 22/0 - 22/0@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cpdm.drawing - 104/44 - 104/44@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cpdm.mask - 37/0 - 37/0@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cpdm.maskAdd - 104/43 - 104/43@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C11 - C0 - false - true - false - 1 - false - false - 0 - cpdm.maskDrop - 104/42 - 104/42@1 - - - #8c8ca6 - #0000ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - cpmm.drawing - 91/44 - 91/44@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cpbo.mask - 99/0 - 99/0@1 - - - #00cc66 - #00cc66 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cmm4.mask - 51/0 - 51/0@1 - - - #00cc66 - #00cc66 - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - cmm4.maskAdd - 112/43 - 112/43@1 - - - #00cc66 - #00cc66 - 0 - 0 - C11 - C0 - true - true - false - 1 - false - false - 0 - cmm4.maskDrop - 112/42 - 112/42@1 - - - #00cc66 - #00cc66 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cmm4.waffleDrop - 112/4 - 112/4@1 - - - #00ffff - #00ffff - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cviam4.drawing - 117/20 - 117/20@1 - - - #00ffff - #00ffff - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cviam4.mask - 58/0 - 58/0@1 - - - #00ffff - #00ffff - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cviam4.maskAdd - 117/21 - 117/21@1 - - - #00ffff - #00ffff - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cviam4.maskDrop - 117/22 - 117/22@1 - - - #ff8000 - #ff8000 - 0 - 0 - C13 - C0 - true - true - false - 1 - false - false - 0 - cmm5.mask - 59/0 - 59/0@1 - - - #ff8000 - #ff8000 - 0 - 0 - I1 - C0 - true - true - false - 1 - false - false - 0 - cmm5.waffleDrop - 117/4 - 117/4@1 - - - #0000ff - #0000ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - target.drawing - 76/44 - 76/44@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - false - true - false - 1 - false - false - 0 - cctm1.drawing - 101/44 - 101/44@1 - - - #ffffff - #ffffff - 0 - 0 - C17 - C0 - true - true - false - 1 - false - false - 0 - cctm1.mask - 35/0 - 35/0@1 - - - #ffffff - #ffffff - 0 - 0 - C14 - C0 - false - true - false - 1 - false - false - 0 - cctm1.maskAdd - 101/43 - 101/43@1 - - - #ffffff - #ffffff - 0 - 0 - C3 - C0 - false - true - false - 1 - false - false - 0 - cctm1.maskDrop - 101/42 - 101/42@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - crpm.drawing - 53/44 - 53/44@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - crpm.mask - 96/0 - 96/0@1 - - - #ffffff - #ffffff - 0 - 0 - C14 - C0 - true - true - false - 1 - false - false - 0 - crpm.maskAdd - 53/43 - 53/43@1 - - - #ffffff - #ffffff - 0 - 0 - C3 - C0 - true - true - false - 1 - false - false - 0 - crpm.maskDrop - 53/42 - 53/42@1 - - - #e61f0d - #e61f0d - 0 - 0 - C47 - C0 - false - true - false - 1 - false - false - 0 - ccu1m.mask - 93/0 - 93/0@1 - - - #bf4026 - #bf4026 - 0 - 0 - C40 - C0 - false - true - false - 1 - false - false - 0 - cpmm2.mask - 94/0 - 94/0@1 - - - #ccccd9 - #333399 - 0 - 0 - C7 - C0 - false - true - false - 1 - false - false - 0 - cubm.mask - 100/0 - 100/0@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C20 - C0 - false - true - false - 1 - false - false - 0 - cbump.mask - 101/0 - 101/0@1 - - - #00bfff - #00bfff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - overlap.drawing - 90/20 - 90/20@1 - - - #ff7f50 - #ff7f50 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - overlap.boundary - 90/4 - 90/4@1 - - - #ff8000 - #ff8000 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.lowTapDensity - 81/14 - 81/14@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.notCritSide - 81/15 - 81/15@1 - - - #adff2f - #adff2f - 0 - 0 - C2 - C0 - true - true - false - 3 - false - false - 0 - areaid.injection - 81/17 - 81/17@1 - - - #bebed8 - #bebed8 - 0 - 0 - C2 - C0 - true - true - false - 3 - false - false - 0 - areaid.rfdiode - 81/125 - 81/125@1 - - - #ffffff - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.seal - 81/1 - 81/1@1 - - - #d9e6ff - #d9e6ff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.core - 81/2 - 81/2@1 - - - #ffffcc - #ffffcc - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.frame - 81/3 - 81/3@1 - - - #d9cc00 - #d9cc00 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.esd - 81/19 - 81/19@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.dieCut - 81/11 - 81/11@1 - - - #00ff00 - #00ff00 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.moduleCut - 81/10 - 81/10@1 - - - #00ffff - #00ffff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.frameRect - 81/12 - 81/12@1 - - - #333399 - #ccccd9 - 0 - 0 - C22 - C0 - true - true - false - 1 - false - false - 0 - areaid.substrateCut - 81/53 - 81/53@1 - - - #ffff00 - #ffff00 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.diode - 81/23 - 81/23@1 - - - #ff00ff - #ff00ff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.standardc - 81/4 - 81/4@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C0 - C5 - true - true - false - 1 - false - false - 0 - areaid.deadZon - 81/50 - 81/50@1 - - - #ff8000 - #ff8000 - 0 - 0 - C0 - C5 - true - true - false - 1 - false - false - 0 - areaid.critCorner - 81/51 - 81/51@1 - - - #ffffcc - #ffffcc - 0 - 0 - C0 - C5 - true - true - false - 1 - false - false - 0 - areaid.critSid - 81/52 - 81/52@1 - - - #8c8ca6 - #c8ffc8 - 0 - 0 - C20 - C0 - true - true - false - 3 - false - false - 0 - areaid.opcDrop - 81/54 - 81/54@1 - - - #00bfff - #00ffe7 - 0 - 0 - C1 - C0 - true - true - false - 3 - false - false - 0 - areaid.waffleWindow - 81/13 - 81/13@1 - - - #daa520 - #daa520 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.extendedDrain - 81/57 - 81/57@1 - - - #ffbff2 - #ffbff2 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.lvNative - 81/60 - 81/60@1 - - - #9900e6 - #9900e6 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.photo - 81/81 - 81/81@1 - - - #ff00ff - #00ff00 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.etest - 81/101 - 81/101@1 - - - #ff0000 - #ff0000 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.hvnwell - 81/63 - 81/63@1 - - - #9900e6 - #9900e6 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.rdlprobepad - 81/27 - 81/27@1 - - - #00bfff - #00bfff - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.sigPadDiff - 81/6 - 81/6@1 - - - #c8ffc8 - #c8ffc8 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.sigPadWell - 81/7 - 81/7@1 - - - #ff7f50 - #ff7f50 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.sigPadMetNtr - 81/8 - 81/8@1 - - - #ff6464 - #ff6464 - 0 - 0 - C0 - C0 - true - true - false - 3 - false - false - 0 - areaid.analog - 81/79 - 81/79@1 - - - #ffff00 - #ffffff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - prune.drawing - 84/44 - 84/44@1 - - - #0000ff - #0000ff - 0 - 0 - C0 - C0 - true - true - false - 1 - false - false - 0 - padCenter.drawing - 81/20 - 81/20@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa1 - 68/88 - 68/88@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa1 - 69/88 - 69/88@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa1 - 70/88 - 70/88@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa1 - 71/88 - 71/88@1 - - - #8c8ca6 - #8c8ca6 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa1 - 72/88 - 72/88@1 - - - #00ffe7 - #00ffe7 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa2 - 68/89 - 68/89@1 - - - #00ffe7 - #00ffe7 - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa2 - 69/89 - 69/89@1 - - - #00ffe7 - #00ffe7 - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa2 - 70/89 - 70/89@1 - - - #00ffe7 - #00ffe7 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa2 - 71/89 - 71/89@1 - - - #00ffe7 - #00ffe7 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa2 - 72/89 - 72/89@1 - - - #ffffcc - #ffffcc - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa3 - 68/90 - 68/90@1 - - - #ffffcc - #ffffcc - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa3 - 69/90 - 69/90@1 - - - #ffffcc - #ffffcc - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa3 - 70/90 - 70/90@1 - - - #ffffcc - #ffffcc - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa3 - 71/90 - 71/90@1 - - - #ffffcc - #ffffcc - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa3 - 72/90 - 72/90@1 - - - #802626 - #802626 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa4 - 68/91 - 68/91@1 - - - #802626 - #802626 - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa4 - 69/91 - 69/91@1 - - - #802626 - #802626 - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa4 - 70/91 - 70/91@1 - - - #802626 - #802626 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa4 - 71/91 - 71/91@1 - - - #802626 - #802626 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa4 - 72/91 - 72/91@1 - - - #333399 - #333399 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa5 - 68/92 - 68/92@1 - - - #333399 - #333399 - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa5 - 69/92 - 69/92@1 - - - #333399 - #333399 - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa5 - 70/92 - 70/92@1 - - - #333399 - #333399 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa5 - 71/92 - 71/92@1 - - - #333399 - #333399 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa5 - 72/92 - 72/92@1 - - - #fa8072 - #fa8072 - 0 - 0 - C7 - C0 - true - true - false - 1 - false - false - 0 - met1.psa6 - 68/93 - 68/93@1 - - - #fa8072 - #fa8072 - 0 - 0 - C37 - C0 - true - true - false - 1 - false - false - 0 - met2.psa6 - 69/93 - 69/93@1 - - - #fa8072 - #fa8072 - 0 - 0 - C49 - C0 - true - true - false - 1 - false - false - 0 - met3.psa6 - 70/93 - 70/93@1 - - - #fa8072 - #fa8072 - 0 - 0 - C15 - C0 - true - true - false - 1 - false - false - 0 - met4.psa6 - 71/93 - 71/93@1 - - - #fa8072 - #fa8072 - 0 - 0 - C42 - C0 - true - true - false - 1 - false - false - 0 - met5.psa6 - 72/93 - 72/93@1 - - - #ff0000 - #ff0000 - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa1 - 74/88 - 74/88@1 - - - #0000ff - #0000ff - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa2 - 74/89 - 74/89@1 - - - #00cc66 - #00cc66 - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa3 - 74/90 - 74/90@1 - - - #ffffff - #ffffff - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa4 - 74/91 - 74/91@1 - - - #ffff00 - #ffff00 - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa5 - 74/92 - 74/92@1 - - - #bf4026 - #bf4026 - 0 - 0 - C10 - C0 - true - true - false - 1 - false - false - 0 - rdl.psa6 - 74/93 - 74/93@1 - - - #ffe6bf - #ffe6bf - 0 - 0 - C20 - C1 - false - true - false - 1 - false - false - 0 - blanking.drawing - 124/40 - 124/40@1 - - - #80a8ff - #80a8ff - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - via.label 5/1@1 - - - #80a8ff - #80a8ff - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - via.blockage 5/3@1 - - - #ff0080 - #ff0080 - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - via2.blockage 7/3@1 - - - #8000ff - #8000ff - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - via3.label 9/1@1 - - - #8000ff - #8000ff - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - via3.blockage 9/3@1 - - - #0080ff - #0080ff - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - via4.label 11/1@1 - - - #0080ff - #0080ff - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - via4.blockage 11/3@1 - - - #800057 - #800057 - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - rdlcon.drawing 13/0@1 - - - #0080ff - #0080ff - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - marker.error 83/6@1 - - - #0080ff - #0080ff - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - marker.warning 83/7@1 - - - #0080ff - #0080ff - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - text.drawing 83/44@1 - - - #008080 - #008080 - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - crrpm.mask 102/0@1 - - - #008080 - #008080 - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - rrpm.drawing 102/20@1 - - - #80ff8d - #80ff8d - 0 - 0 - I9 - - true - true - false - - false - false - 0 - - prBoundary.drawing 235/0@1 - - - #ffae00 - #ffae00 - 0 - 0 - I5 - - true - true - false - - false - false - 0 - - OUTLINE@1 - - GDS - - - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - - 1 - blank - - - - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - **************** - - 2 - solid - - - - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - - 3 - dots - - - - ................ - ................ - ................ - **************** - ................ - ................ - ................ - **************** - ................ - ................ - ................ - **************** - ................ - ................ - ................ - **************** - - 4 - hLine - - - - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - ..*...*...*...*. - - 5 - vLine - - - - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - - 6 - cross - - - - ...*...*...*...* - ...*...*...*...* - ...*...*...*...* - **************** - ...*...*...*...* - ...*...*...*...* - ...*...*...*...* - **************** - ...*...*...*...* - ...*...*...*...* - ...*...*...*...* - **************** - ...*...*...*...* - ...*...*...*...* - ...*...*...*...* - **************** - - 7 - grid - - - - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - - 8 - slash - - - - *...*...*...*... - .*...*...*...*.. - ..*...*...*...*. - ...*...*...*...* - *...*...*...*... - .*...*...*...*.. - ..*...*...*...*. - ...*...*...*...* - *...*...*...*... - .*...*...*...*.. - ..*...*...*...*. - ...*...*...*...* - *...*...*...*... - .*...*...*...*.. - ..*...*...*...*. - ...*...*...*...* - - 9 - backSlash - - - - **......**...... - ..*.......*..... - ...**......**... - .....*.......*.. - ......**......** - *.......*....... - .**......**..... - ...*.......*.... - ....**......**.. - ......*.......*. - *......**......* - .*.......*...... - ..**......**.... - ....*.......*... - .....**......**. - .......*.......* - - 10 - hZigZag - - - - *....*....*..... - *.....*....*.... - .*....*.....*... - ..*....*....*... - ..*.....*....*.. - ...*....*.....*. - ....*....*....*. - ....*.....*....* - *....*....*..... - *.....*....*.... - .*....*.....*... - ..*....*....*... - ..*.....*....*.. - ...*....*.....*. - ....*....*....*. - ....*.....*....* - - 11 - vZigZag - - - - ................ - ................ - ...*****...***** - ...*...*...*...* - ...*...*...*...* - ****...*****...* - ................ - ................ - ................ - ................ - ...*****...***** - ...*...*...*...* - ...*...*...*...* - ****...*****...* - ................ - ................ - - 12 - hCurb - - - - .....*.......*.. - .....*.......*.. - .....*.......*.. - ..****....****.. - ..*.......*..... - ..*.......*..... - ..*.......*..... - ..****....****.. - .....*.......*.. - .....*.......*.. - .....*.......*.. - ..****....****.. - ..*.......*..... - ..*.......*..... - ..*.......*..... - ..****....****.. - - 13 - vCurb - - - - **************** - ..*.......*..... - ..*.......*..... - ..*.......*..... - **************** - ......*.......*. - ......*.......*. - ......*.......*. - **************** - ..*.......*..... - ..*.......*..... - ..*.......*..... - **************** - ......*.......*. - ......*.......*. - ......*.......*. - - 14 - brick - - - - ................ - ..*.......*..... - ..*.......*..... - ..*.......*..... - *****...*****... - ..*.......*..... - ..*.......*..... - ..*.......*..... - ................ - .....*.......*.. - .....*.......*.. - .....*.......*.. - ...*****...***** - .....*.......*.. - .....*.......*.. - .....*.......*.. - - 15 - dagger - - - - ................ - ..*............. - ..*............. - ..*............. - *****........... - ..*............. - ..*............. - ..*............. - ................ - .............*.. - .............*.. - .............*.. - ...........***** - .............*.. - .............*.. - .............*.. - - 16 - sparseDagger - - - - ................ - ..........*..... - ..........*..... - ..........*..... - ........*****... - ..........*..... - ..........*..... - ..........*..... - ................ - .....*.......... - .....*.......... - .....*.......... - ...*****........ - .....*.......... - .....*.......... - .....*.......... - - 17 - sparseDagger2 - - - - ................ - ....*........... - ...*.*.......... - ..*...*......... - .*.....*........ - *********....... - ................ - ................ - ................ - ...........*.... - ..........*.*... - .........*...*.. - ........*.....*. - .......********* - ................ - ................ - - 18 - triangle - - - - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - *...*...*...*... - .*.*.*.*.*.*.*.* - ..*...*...*...*. - .*.*.*.*.*.*.*.* - - 19 - x - - - - ................ - .*.....*.....*.. - ..*...**....*... - ...*.*.*...*.... - ....*..*..*..... - .....*.*.*...... - ......***....... - .......*........ - ......***....... - .....*.*.*...... - ....*..*..*..... - ...*...*...*.... - ..*....*....*... - .*..*******..*.. - ................ - ................ - - 20 - Xone - - - - ................ - .*....**.....*.. - ..*..*..*...*... - ...**....*.*.... - ....*....**..... - .....*...*...... - ......*.*....... - .......*........ - ......*.*....... - .....*...*...... - ....*.....*..... - ...**......*.... - ..*.*.......*... - .*..******...*.. - ................ - ................ - - 21 - Xtwo - - - - ................ - ................ - ......*.......*. - ................ - ................ - ................ - ..*.......*..... - ................ - ................ - ................ - ......*.......*. - ................ - ................ - ................ - ..*.......*..... - ................ - - 22 - spareDots - - - - ................ - ................ - ................ - ................ - ................ - ......*.......*. - ................ - ................ - ................ - ................ - ................ - ................ - ..*.......*..... - ................ - ................ - ................ - - 23 - spareDots21 - - - - ................ - ................ - ......*.......*. - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ..*.......*..... - ................ - ................ - ................ - ................ - ................ - - 24 - spareDots22 - - - - ****....****.... - ****....****.... - ****....****.... - ****....****.... - ....****....**** - ....****....**** - ....****....**** - ....****....**** - ****....****.... - ****....****.... - ****....****.... - ****....****.... - ....****....**** - ....****....**** - ....****....**** - ....****....**** - - 25 - checker - - - - ....****....**** - ....****....**** - ....****....**** - ....****....**** - ****....****.... - ****....****.... - ****....****.... - ****....****.... - ....****....**** - ....****....**** - ....****....**** - ....****....**** - ****....****.... - ****....****.... - ****....****.... - ****....****.... - - 26 - checker2 - - - - ................ - ................ - ................ - ................ - .......*........ - ......**........ - .......*........ - .......*........ - .......*........ - .......*........ - ......***....... - ................ - ................ - ................ - ................ - ................ - - 27 - one - - - - ................ - ................ - ................ - ................ - ................ - .......**....... - ......*..*...... - .........*...... - ........*....... - .......*........ - ......*......... - ......****...... - ................ - ................ - ................ - ................ - - 28 - two - - - - ................ - ................ - ................ - ................ - ................ - ......***....... - .....*...*...... - .........*...... - .......**....... - .........*...... - .....*...*...... - ......***....... - ................ - ................ - ................ - ................ - - 29 - three - - - - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - .............*.. - ............**.. - ...........*.*.. - ..........*..*.. - .........******. - .............*.. - .............*.. - ................ - - 30 - four - - - - ................ - ................ - ................ - ......***....... - .....*.......... - .....*.......... - .....***........ - ........*....... - ........*....... - .....***........ - ................ - ................ - ................ - ................ - ................ - ................ - - 31 - five - - - - ................ - ................ - ................ - ................ - .......***...... - ......*......... - ......*......... - ......****...... - ......*...*..... - ......*...*..... - .......***...... - ................ - ................ - ................ - ................ - ................ - - 32 - six - - - - ................ - ................ - ................ - .....******..... - ..........*..... - .........*...... - .........*...... - ........*....... - ........*....... - .......*........ - ......*......... - .....*.......... - ................ - ................ - ................ - ................ - - 33 - seven - - - - ................ - ................ - ................ - ................ - ......***....... - .....*...*...... - .....*...*...... - ......***....... - .....*...*...... - .....*...*...... - ......***....... - ................ - ................ - ................ - ................ - ................ - - 34 - eight - - - - *..............* - .*............*. - ..*..........*.. - ...*........*... - ....*......*.... - .....*....*..... - ......*..*...... - .......**....... - .......**....... - ......*..*...... - .....*....*..... - ....*......*.... - ...*........*... - ..*..........*.. - .*............*. - *..............* - - 35 - box45 - - - - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - .*.*.*.*.*.*.*.* - *.*.*.*.*.*.*.*. - - 36 - gray50 - - - - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - *...*...*...*... - ................ - ..*...*...*...*. - ................ - - 37 - gray25 - - - - .*.*.*...*.*.*.. - ................ - ...*...*...*...* - ................ - .*...*.*.*...*.* - ................ - ...*...*...*...* - ................ - .*.*.*...*.*.*.. - ................ - ...*...*...*...* - ................ - .*...*.*.*...*.* - ................ - ...*...*...*...* - ................ - - 38 - snow - - - - ..*.......*..... - ...*.......*.... - ....*.......*... - .....*.......*.. - ......*.......*. - .......*.......* - *.......*....... - .*.......*...... - ..*.......*..... - ...*.......*.... - ....*.......*... - .....*.......*.. - ......*.......*. - .......*.......* - *.......*....... - .*.......*...... - - 39 - backSlash2 - - - - *.....*.*.....*. - .*...*...*...*.. - ..*.*.....*.*... - ...*...*...*...* - ..*.*.....*.*... - .*...*...*...*.. - *.....*.*.....*. - ...*...*...*...* - *.....*.*.....*. - .*...*...*...*.. - ..*.*.....*.*... - ...*...*...*...* - ..*.*.....*.*... - .*...*...*...*.. - *.....*.*.....*. - ...*...*...*...* - - 40 - lattice - - - - **..**..**..**.. - **..**..**..**.. - ..**..**..**..** - ..**..**..**..** - **..**..**..**.. - **..**..**..**.. - ..**..**..**..** - ..**..**..**..** - **..**..**..**.. - **..**..**..**.. - ..**..**..**..** - ..**..**..**..** - **..**..**..**.. - **..**..**..**.. - ..**..**..**..** - ..**..**..**..** - - 41 - smallChecker - - - - ....*........... - ...*.*.......... - ..*...*......... - .*.....*........ - *.......*....... - .*.......*...... - ..*.......*..... - ...*.......*.... - ....*.......*... - .....*.......*.. - ......*.......*. - .......*.......* - ........*.....*. - .........*...*.. - ..........*.*... - ...........*.... - - 42 - slantBox - - - - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - .*...*...*...*.. - *...*...*...*... - ...*...*...*...* - ..*...*...*...*. - - 43 - slash2 - - - - ...*.......*.... - ..*.......*..... - .*.......*...... - *.......*....... - .......*.......* - ......*.......*. - .....*.......*.. - ....*.......*... - ...*.......*.... - ..*.......*..... - .*.......*...... - *.......*....... - .......*.......* - ......*.......*. - .....*.......*.. - ....*.......*... - - 44 - bigSlash - - - - ****....****.... - *..*....*..*.... - *..*....*..*.... - ****....****.... - ................ - ................ - ................ - ................ - ****....****.... - *..*....*..*.... - *..*....*..*.... - ****....****.... - ................ - ................ - ................ - ................ - - 45 - boxes - - - - ..**......**.... - .*..*....*..*... - *....*..*....*.. - *....*..*....*.. - .*..*....*..*... - ..**......**.... - ................ - ................ - ..**......**.... - .*..*....*..*... - *....*..*....*.. - *....*..*....*.. - .*..*....*..*... - ..**......**.... - ................ - ................ - - 46 - circles - - - - .**..**..**..**. - ...*...*...*...* - *...*...*...*... - .**..**..**..**. - .**..**..**..**. - *...*...*...*... - ...*...*...*...* - .**..**..**..**. - .**..**..**..**. - ...*...*...*...* - *...*...*...*... - .**..**..**..**. - .**..**..**..**. - *...*...*...*... - ...*...*...*...* - .**..**..**..**. - - 47 - zigzag - - - - ................ - *.*.*.*.*.*.*.*. - ................ - ...*....*....*.. - ................ - *.*.*.*.*.*.*.*. - ................ - ...*....*....*.. - ................ - *.*.*.*.*.*.*.*. - ................ - ...*....*....*.. - ................ - *.*.*.*.*.*.*.*. - ................ - ...*....*....*.. - - 48 - lightMesh - - - - ...............* - ..............*. - .............*.. - ............*... - ...........*.... - ..........*..... - .........*...... - ........*....... - .......*........ - ......*......... - .....*.......... - ....*........... - ...*............ - ..*............. - .*.............. - *............... - - 49 - hugeSlash - - - - *............... - .*.............. - ..*............. - ...*............ - ....*........... - .....*.......... - ......*......... - .......*........ - ........*....... - .........*...... - ..........*..... - ...........*.... - ............*... - .............*.. - ..............*. - ...............* - - 50 - hugeSlash2 - - - - *.........*..... - .....*.......... - ..*.........*... - .......*........ - ....*.........*. - .*.......*...... - ......*......... - ...*.......*.... - ........*....... - .....*.......*.. - *.........*..... - .......*........ - ..*.........*... - .........*...... - ....*.........*. - ...........*.... - - 51 - curve - - - - ....*....*....*. - ..*............. - *.......*....... - .............*.. - .......*........ - ............*... - .....*.......... - ...*.......*.... - *............... - ................ - .........*...... - ................ - ......*........* - ...*............ - *............*.. - ..........*..... - - 52 - curve2 - - - - ...........*.... - ..........*.*... - .........*...*.. - ........*.....*. - .........*...*.. - ..........*.*... - ...........*.... - ................ - ................ - ...*............ - ..*.*........... - .*...*.......... - *.....*......... - .*...*.......... - ..*.*........... - ...*............ - - 53 - diams - - - - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ................ - ...*............ - ..*.*........... - .*...*.......... - *.....*......... - .*...*.......... - ..*.*........... - ...*............ - - 54 - sparsediam - - - - .......*.......* - ......*......... - .....*.......... - ................ - ................ - ................ - .*.............. - *............... - .......*.......* - ..............*. - .............*.. - ................ - ................ - ................ - .........*...... - ........*....... - - 55 - rain - - - *** - 1 - solid - - - ****.. - 2 - dashed - - - *.. - 3 - dots - - - ***..*.. - 4 - dashDot - - - **.. - 5 - shortDash - - - ****..**.. - 6 - doubleDash - - - *... - 7 - hidden - - - *** - 8 - thickLine - - diff --git a/flow/platforms/sky130hd_fakestack/sky130hd.lyt b/flow/platforms/sky130hd_fakestack/sky130hd.lyt deleted file mode 100644 index 4614e85b98..0000000000 --- a/flow/platforms/sky130hd_fakestack/sky130hd.lyt +++ /dev/null @@ -1,158 +0,0 @@ - - - sky130A - SkyWater 130nm technology - - 0.001 - ./platforms/sky130hd/ - .klayout/tech/sky130 - sky130hd.lyp - true - - - 1 - true - true - - - true - layer_map() - true - true - - - true - layer_map('areaid.analog : 81/79';'areaid.core : 81/2';'areaid.critCorner : 81/51';'areaid.critSid : 81/52';'areaid.deadZon : 81/50';'areaid.dieCut : 81/11';'areaid.diode : 81/23';'areaid.esd : 81/19';'areaid.etest : 81/101';'areaid.extendedDrain : 81/57';'areaid.frame : 81/3';'areaid.frameRect : 81/12';'areaid.hvnwell : 81/63';'areaid.injection : 81/17';'areaid.lowTapDensity : 81/14';'areaid.lvNative : 81/60';'areaid.moduleCut : 81/10';'areaid.notCritSide : 81/15';'areaid.opcDrop : 81/54';'areaid.photo : 81/81';'areaid.rdlprobepad : 81/27';'areaid.rfdiode : 81/125';'areaid.seal : 81/1';'areaid.sigPadDiff : 81/6';'areaid.sigPadMetNtr : 81/8';'areaid.sigPadWell : 81/7';'areaid.standardc : 81/4';'areaid.substrateCut : 81/53';'areaid.waffleWindow : 81/13';'blanking.drawing : 124/40';'bump.drawing : 127/22';'capacitor.drawing : 82/64';'cbump.mask : 101/0';'cctm1.drawing : 101/44';'cctm1.mask : 35/0';'cctm1.maskAdd : 101/43';'cctm1.maskDrop : 101/42';'ccu1m.mask : 93/0';'cdnm.drawing : 110/20';'cdnm.mask : 48/0';'cdnm.maskAdd : 110/21';'cdnm.maskDrop : 110/22';'cfom.drawing : 22/20';'cfom.mask : 23/0';'cfom.maskAdd : 22/21';'cfom.maskDrop : 22/22';'cfom.waffleDrop : 22/24';'chvntm.drawing : 38/20';'chvntm.mask : 39/0';'chvntm.maskAdd : 38/21';'chvntm.maskDrop : 38/22';'chvtpm.drawing : 88/44';'chvtpm.mask : 97/0';'chvtpm.maskAdd : 97/43';'chvtpm.maskDrop : 97/42';'chvtrm.drawing : 98/44';'chvtrm.mask : 98/0';'chvtrm.maskAdd : 98/43';'chvtrm.maskDrop : 98/42';'cldntm.drawing : 11/20';'cldntm.mask : 11/0';'cli1m.drawing : 115/44';'cli1m.mask : 56/0';'cli1m.maskAdd : 115/43';'cli1m.maskDrop : 115/42';'clicm1.drawing : 106/44';'clicm1.mask : 43/0';'clicm1.maskAdd : 106/43';'clicm1.maskDrop : 106/42';'clvom.drawing : 45/20';'clvom.mask : 46/0';'clvom.maskAdd : 45/21';'clvom.maskDrop : 45/22';'clvtnm.drawing : 25/44';'clvtnm.mask : 25/0';'clvtnm.maskAdd : 25/43';'clvtnm.maskDrop : 25/42';'cmm1.drawing : 62/20';'cmm1.mask : 36/0';'cmm1.maskAdd : 62/21';'cmm1.maskDrop : 62/22';'cmm1.waffleDrop : 62/24';'cmm2.drawing : 105/44';'cmm2.mask : 41/0';'cmm2.maskAdd : 105/43';'cmm2.maskDrop : 105/42';'cmm2.waffleDrop : 105/52';'cmm3.drawing : 107/20';'cmm3.mask : 34/0';'cmm3.maskAdd : 107/21';'cmm3.maskDrop : 107/22';'cmm3.waffleDrop : 107/24';'cmm4.mask : 51/0';'cmm4.maskAdd : 112/43';'cmm4.maskDrop : 112/42';'cmm4.waffleDrop : 112/4';'cmm5.mask : 59/0';'cmm5.waffleDrop : 117/4';'cncm.drawing : 96/44';'cncm.mask : 17/0';'cnpc.drawing : 44/20';'cnpc.mask : 49/0';'cnpc.maskAdd : 44/43';'cnpc.maskDrop : 44/42';'cnsdm.drawing : 29/20';'cnsdm.mask : 30/0';'cnsdm.maskAdd : 29/21';'cnsdm.maskDrop : 29/22';'cnsm.mask : 22/0';'cntm.drawing : 26/20';'cntm.mask : 27/0';'cntm.maskAdd : 26/21';'cntm.maskDrop : 26/22';'cnwm.drawing : 109/44';'cnwm.mask : 21/0';'cnwm.maskAdd : 109/43';'cnwm.maskDrop : 109/42';'conom.drawing : 87/44';'conom.mask : 88/0';'conom.maskAdd : 87/43';'conom.maskDrop : 87/42';'cp1m.drawing : 33/44';'cp1m.mask : 28/0';'cp1m.maskAdd : 33/43';'cp1m.maskDrop : 33/42';'cp1m.waffleDrop : 33/24';'cpbo.mask : 99/0';'cpdm.drawing : 104/44';'cpdm.mask : 37/0';'cpdm.maskAdd : 104/43';'cpdm.maskDrop : 104/42';'cpmm2.mask : 94/0';'cpmm.drawing : 91/44';'cpsdm.drawing : 31/20';'cpsdm.mask : 32/0';'cpsdm.maskAdd : 31/21';'cpsdm.maskDrop : 31/22';'crpm.drawing : 53/44';'crpm.mask : 96/0';'crpm.maskAdd : 53/43';'crpm.maskDrop : 53/42';'crrpm.mask : 102/0';'ctunm.drawing : 96/20';'ctunm.mask : 20/0';'ctunm.maskAdd : 96/21';'ctunm.maskDrop : 96/22';'cubm.mask : 100/0';'cviam2.drawing : 108/20';'cviam2.mask : 44/0';'cviam2.maskAdd : 108/21';'cviam2.maskDrop : 108/22';'cviam3.drawing : 112/20';'cviam3.mask : 50/0';'cviam3.maskAdd : 112/21';'cviam3.maskDrop : 112/22';'cviam4.drawing : 117/20';'cviam4.mask : 58/0';'cviam4.maskAdd : 117/21';'cviam4.maskDrop : 117/22';'cviam.drawing : 105/20';'cviam.mask : 40/0';'cviam.maskAdd : 105/21';'cviam.maskDrop : 105/22';'diff.boundary : 65/4';'diff.cut : 65/14';'diff.drawing : 65/20';'diff.hv : 65/8';'diff.label : 65/6';'diff.net : 65/23';'diff.pin : 65/16';'diff.res : 65/13';'dnwell.drawing : 64/18';'fom.dummy : 22/23';'hvi.drawing : 75/20';'hvntm.drawing : 125/20';'hvtp.drawing : 78/44';'hvtr.drawing : 18/20';'inductor.drawing : 82/24';'inductor.label : 82/25';'inductor.term1 : 82/26';'inductor.term2 : 82/27';'inductor.term3 : 82/28';'ldntm.drawing : 11/44';'li1.blockage : 67/10';'li1.boundary : 67/4';'li1.cut : 67/14';'li1.drawing : 67/20';'li1.label : 67/5';'li1.net : 67/23';'li1.pin : 67/16';'li1.probe : 67/25';'li1.res : 67/13';'li1.short : 67/15';'licon1.boundary : 66/60';'licon1.drawing : 66/44';'licon1.net : 66/41';'licon1.pin : 66/58';'lvtn.drawing : 125/44';'marker.error : 83/6';'marker.warning : 83/7';'mcon.boundary : 67/60';'mcon.drawing : 67/44';'mcon.blockage : 67/44';'mcon.net : 67/41';'mcon.pin : 67/48';'met1.blockage : 68/10';'met1.boundary : 68/4';'met1.cut : 68/14';'met1.drawing : 68/20';'met1.label : 68/5';'met1.net : 68/23';'met1.option1 : 68/32';'met1.option2 : 68/33';'met1.option3 : 68/34';'met1.option4 : 68/35';'met1.option5 : 68/36';'met1.option6 : 68/37';'met1.option7 : 68/38';'met1.option8 : 68/39';'met1.pin : 68/16';'met1.probe : 68/25';'met1.psa1 : 68/88';'met1.psa2 : 68/89';'met1.psa3 : 68/90';'met1.psa4 : 68/91';'met1.psa5 : 68/92';'met1.psa6 : 68/93';'met1.res : 68/13';'met1.short : 68/15';'met2.blockage : 69/10';'met2.boundary : 69/4';'met2.cut : 69/14';'met2.drawing : 69/20';'met2.label : 69/5';'met2.net : 69/23';'met2.option1 : 69/32';'met2.option2 : 69/33';'met2.option3 : 69/34';'met2.option4 : 69/35';'met2.option5 : 69/36';'met2.option6 : 69/37';'met2.option7 : 69/38';'met2.option8 : 69/39';'met2.pin : 69/16';'met2.probe : 69/25';'met2.psa1 : 69/88';'met2.psa2 : 69/89';'met2.psa3 : 69/90';'met2.psa4 : 69/91';'met2.psa5 : 69/92';'met2.psa6 : 69/93';'met2.res : 69/13';'met2.short : 69/15';'met3.blockage : 70/10';'met3.boundary : 70/4';'met3.cut : 70/14';'met3.drawing : 70/20';'met3.fuse : 70/17';'met3.label : 70/5';'met3.net : 70/23';'met3.option1 : 70/32';'met3.option2 : 70/33';'met3.option3 : 70/34';'met3.option4 : 70/35';'met3.option5 : 70/36';'met3.option6 : 70/37';'met3.option7 : 70/38';'met3.option8 : 70/39';'met3.pin : 70/16';'met3.probe : 70/25';'met3.psa1 : 70/88';'met3.psa2 : 70/89';'met3.psa3 : 70/90';'met3.psa4 : 70/91';'met3.psa5 : 70/92';'met3.psa6 : 70/93';'met3.res : 70/13';'met3.short : 70/15';'met4.blockage : 71/10';'met4.boundary : 71/4';'met4.cut : 71/14';'met4.drawing : 71/20';'met4.fuse : 71/17';'met4.label : 71/5';'met4.net : 71/23';'met4.option1 : 71/32';'met4.option2 : 71/33';'met4.option3 : 71/34';'met4.option4 : 71/35';'met4.option5 : 71/36';'met4.option6 : 71/37';'met4.option7 : 71/38';'met4.option8 : 71/39';'met4.pin : 71/16';'met4.probe : 71/25';'met4.psa1 : 71/88';'met4.psa2 : 71/89';'met4.psa3 : 71/90';'met4.psa4 : 71/91';'met4.psa5 : 71/92';'met4.psa6 : 71/93';'met4.res : 71/13';'met4.short : 71/15';'met5.blockage : 72/10';'met5.boundary : 72/4';'met5.cut : 72/14';'met5.drawing : 72/20';'met5.fuse : 72/17';'met5.label : 72/5';'met5.net : 72/23';'met5.option1 : 72/32';'met5.option2 : 72/33';'met5.option3 : 72/34';'met5.option4 : 72/35';'met5.option5 : 72/36';'met5.option6 : 72/37';'met5.option7 : 72/38';'met5.option8 : 72/39';'met5.pin : 72/16';'met5.probe : 72/25';'met5.psa1 : 72/88';'met5.psa2 : 72/89';'met5.psa3 : 72/90';'met5.psa4 : 72/91';'met5.psa5 : 72/92';'met5.psa6 : 72/93';'met5.res : 72/13';'met5.short : 72/15';'ncm.drawing : 92/44';'npc.drawing : 95/20';'npn.drawing : 82/20';'npn.label : 82/5';'nsdm.drawing : 93/44';'nsm.drawing : 61/20';'nwell.drawing : 64/20';'nwell.label : 64/5';'nwell.net : 84/23';'nwell.pin : 64/16';'overlap.boundary : 90/4';'overlap.drawing : 90/20';'pad.drawing : 76/20';'pad.label : 76/5';'pad.pin : 76/16';'padCenter.drawing : 81/20';'pmm2.drawing : 77/20';'pmm.drawing : 85/44';'pnp.drawing : 82/44';'pnp.label : 82/59';'poly.boundary : 66/4';'poly.cut : 66/14';'poly.drawing : 66/20';'poly.gate : 66/9';'poly.label : 66/5';'poly.model : 66/83';'poly.net : 66/23';'poly.pin : 66/16';'poly.probe : 66/25';'poly.res : 66/13';'poly.short : 66/15';'prBoundary.boundary : 235/4';'prBoundary.drawing : 235/0';'prune.drawing : 84/44';'psdm.drawing : 94/20';'pwell.cut : 64/14';'pwell.drawing : 64/44';'pwell.label : 64/59';'pwell.pin : 122/16';'pwell.res : 64/13';'pwelliso.label : 44/5';'pwelliso.pin : 44/16';'rdl.cut : 74/14';'rdl.drawing : 74/20';'rdl.label : 74/5';'rdl.option1 : 89/32';'rdl.option2 : 89/33';'rdl.option3 : 89/34';'rdl.option4 : 89/35';'rdl.option5 : 89/36';'rdl.option6 : 89/37';'rdl.option7 : 89/38';'rdl.option8 : 89/39';'rdl.pin : 74/16';'rdl.psa1 : 74/88';'rdl.psa2 : 74/89';'rdl.psa3 : 74/90';'rdl.psa4 : 74/91';'rdl.psa5 : 74/92';'rdl.psa6 : 74/93';'rdl.res : 74/13';'rdl.short : 74/15';'rpm.drawing : 86/20';'rrpm.drawing : 102/20';'tap.boundary : 65/60';'tap.drawing : 65/44';'tap.label : 65/5';'tap.net : 65/41';'tap.pin : 65/48';'target.drawing : 76/44';'text.drawing : 83/44';'tunm.drawing : 80/20';'ubm.drawing : 127/21';'vhvi.drawing : 74/21';'via2.boundary : 69/60';'via2.drawing : 69/44';'via2.net : 69/41';'via2.pin : 69/58';'via3.boundary : 70/60';'via3.drawing : 70/44';'via3.net : 70/41';'via3.pin : 70/48';'via4.boundary : 71/60';'via4.drawing : 71/44';'via4.net : 71/41';'via4.pin : 71/48';'via.boundary : 68/60';'via.drawing : 68/44';'via.net : 68/41';'via.pin : 68/58') - 0.001 - true - #1 - true - #1 - false - #1 - true - prBoundary.boundary - true - PLACEMENT_BLK - true - REGIONS - true - .drawing - 44 - true - .pin - 16 - true - .pin - 16 - false - .FILL - 5 - false - .blockage - 10 - true - .blockage - 10 - true - .label - 5 - true - .label - 5 - true - .drawing - 20 - true - .drawing - 20 - VIA_ - true - default - false - - merged.lef - - - 0.001 - 1 - 100 - 100 - 0 - 0 - 0 - false - false - false - true - layer_map() - - - 0 - 0.001 - layer_map() - true - false - - - 1 - 0.001 - layer_map() - true - false - true - - - - - - - true - false - false - false - false - false - 8000 - 32000 - LIB - - - 2 - false - false - 1 - * - false - - - 0 - - - false - false - - - 0 - - true - - - - li1,mcon,met1 - met1,via,met2 - met2,via2,met3 - met3,via3,met4 - met4,via4,met5 - li1='67/20+67/16' - met1='68/20+68/16' - met2='69/20+69/16' - met3='70/20+70/16' - met4='71/20+71/16' - met5='72/20-72/15+72/16' - via='68/44' - via2='69/44' - via3='70/44' - via4='71/44' - - diff --git a/flow/platforms/sky130hd_fakestack/tapcell.tcl b/flow/platforms/sky130hd_fakestack/tapcell.tcl deleted file mode 100644 index 67311b3d80..0000000000 --- a/flow/platforms/sky130hd_fakestack/tapcell.tcl +++ /dev/null @@ -1,4 +0,0 @@ -tapcell \ - -distance 14 \ - -tapcell_master "$::env(TAP_CELL_NAME)" - diff --git a/flow/platforms/sky130hs/config.mk b/flow/platforms/sky130hs/config.mk index 69fbd842d6..bb76601b78 100644 --- a/flow/platforms/sky130hs/config.mk +++ b/flow/platforms/sky130hs/config.mk @@ -39,6 +39,13 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hs.v # Define ABC driver and load export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1 export ABC_LOAD_IN_FF = 5 + +# ----------------------------------------------------- +# Sizing +# ----------------------------------------------------- + +export MATCH_CELL_FOOTPRINT = 1 + #-------------------------------------------------------- # Floorplan # ------------------------------------------------------- @@ -48,8 +55,8 @@ export ABC_LOAD_IN_FF = 5 export PLACE_SITE = unit # IO Placer pin layers -export IO_PLACER_H = met3 -export IO_PLACER_V = met2 +export IO_PLACER_H ?= met3 +export IO_PLACER_V ?= met2 # Define default PDN config export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl @@ -59,7 +66,6 @@ export TAP_CELL_NAME = sky130_fd_sc_hs__tapvpwrvgnd_1 export TAPCELL_TCL ?= $(PLATFORM_DIR)/tapcell.tcl export MACRO_PLACE_HALO ?= 40 40 -export MACRO_PLACE_CHANNEL ?= 80 80 #--------------------------------------------------------- # Place @@ -71,8 +77,13 @@ export PLACE_DENSITY ?= 0.50 # --------------------------------------------------------- # FastRoute options export MIN_ROUTING_LAYER = met1 +export MIN_CLK_ROUTING_LAYER = met3 export MAX_ROUTING_LAYER = met5 # +# Max iterations of repair antennas +export MAX_REPAIR_ANTENNAS_ITER_GRT ?= 5 +export MAX_REPAIR_ANTENNAS_ITER_DRT ?= 5 +# # Define fastRoute tcl export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl @@ -94,6 +105,6 @@ export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules # IR drop estimation supply net name to be analyzed and supply voltage variable # For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2" -export PWR_NETS_VOLTAGES ?= "VDD 1.8" -export GND_NETS_VOLTAGES ?= "VSS 0.0" +export PWR_NETS_VOLTAGES ?= VDD 1.8 +export GND_NETS_VOLTAGES ?= VSS 0.0 export IR_DROP_LAYER ?= met1 diff --git a/flow/platforms/sky130hs/fastroute.tcl b/flow/platforms/sky130hs/fastroute.tcl index 06c2749720..76f9321967 100644 --- a/flow/platforms/sky130hs/fastroute.tcl +++ b/flow/platforms/sky130hs/fastroute.tcl @@ -1,3 +1,4 @@ set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.2 +set_routing_layers -clock $::env(MIN_CLK_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/flow/platforms/sky130hs/pdn.tcl b/flow/platforms/sky130hs/pdn.tcl index 546a9a084f..8597d2a4bb 100644 --- a/flow/platforms/sky130hs/pdn.tcl +++ b/flow/platforms/sky130hs/pdn.tcl @@ -30,10 +30,12 @@ add_pdn_connect -grid {grid} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_1 #################################### -define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_1} -voltage_domains {CORE} -macro \ + -orient {R0 R180 MX MY} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_1} -layers {met4 met5} #################################### # grid for: CORE_macro_grid_2 #################################### -define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary +define_pdn_grid -name {CORE_macro_grid_2} -voltage_domains {CORE} -macro \ + -orient {R90 R270 MXR90 MYR90} -halo {2.0 2.0 2.0 2.0} -default -grid_over_boundary add_pdn_connect -grid {CORE_macro_grid_2} -layers {met4 met5} diff --git a/flow/platforms/sky130hs/work_around_yosys/formal_pdk.v b/flow/platforms/sky130hs/work_around_yosys/formal_pdk.v deleted file mode 100644 index 8c1b1a8996..0000000000 --- a/flow/platforms/sky130hs/work_around_yosys/formal_pdk.v +++ /dev/null @@ -1,13535 +0,0 @@ -//13474: - -(* noblackbox *) module sky130_ef_sc_hd__decap_12 (); - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); -endmodule // sky130_ef_sc_hd__decap_12 - -(* noblackbox *) module sky130_ef_sc_hd__fakediode_2 (DIODE); - input DIODE; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__diode base ( - .DIODE(DIODE) - ); -endmodule // sky130_ef_sc_hd__fakediode_2 - -(* noblackbox *) module sky130_ef_sc_hd__fill_8 (); - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; -endmodule // sky130_ef_sc_hd__fill_8 - -(* noblackbox *) module sky130_ef_sc_hd__fill_12 (); - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fill base (); -endmodule // sky130_ef_sc_hd__fill_12 - -(* noblackbox *) module sky130_fd_sc_hs__udp_dff$NSR (Q,SET,RESET,CLK_N,D); - output Q; - input SET; - input RESET; - input CLK_N; - input D; - reg Q; - wire AD = SET; - wire AL = SET | RESET; - always @(negedge CLK_N or posedge AL) - if (AL) Q <= AD; - else Q <= D; -endmodule // sky130_fd_sc_hs__udp_dff - -(* noblackbox *) module sky130_fd_sc_hs__udp_dff$P (Q,D,CLK); - output Q; - input D; - input CLK; - reg Q; - always @(posedge CLK) Q <= D; -endmodule // sky130_fd_sc_hs__udp_dff - -(* noblackbox *) module sky130_fd_sc_hs__udp_dff$PR (Q,D,CLK,RESET); - output Q; - input D; - input CLK; - input RESET; - reg Q; - always @(posedge CLK or posedge RESET) - if (RESET) Q <= 1'b0; - else Q <= D; -endmodule // sky130_fd_sc_hs__udp_dff - -(* noblackbox *) module sky130_fd_sc_hs__udp_dff$PS (Q,D,CLK,SET); - output Q; - input D; - input CLK; - input SET; - reg Q; - always @(posedge CLK or posedge SET) - if (SET) Q <= 1'b1; - else Q <= D; -endmodule // sky130_fd_sc_hs__udp_dff - -(* noblackbox *) module sky130_fd_sc_hs__udp_dlatch$lP (Q,D,GATE); - output Q; - input D; - input GATE; - reg Q; - always @(GATE or D) - if (GATE) Q <= D; -endmodule // sky130_fd_sc_hs__udp_dlatch - -(* noblackbox *) module sky130_fd_sc_hs__udp_dlatch$P (Q,D,GATE); - output Q; - input D; - input GATE; - reg Q; - always @(GATE or D) - if (GATE) Q <= D; -endmodule // sky130_fd_sc_hs__udp_dlatch - -(* noblackbox *) module sky130_fd_sc_hs__udp_dlatch$PR (Q,D,GATE,RESET); - output Q; -input D; -input GATE; -input RESET; -reg Q; -wire AG = GATE | RESET; -wire AD = (~RESET) & D; -always @(AG or AD) - if (AG) Q <= AD; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_mux_2to1 (X,A0,A1,S); -output X; -reg X; -input A0; -input A1; -input S; -always @* casez ({A0,A1,S}) - 3'b00?: {X} = 1'b0; - 3'b11?: {X} = 1'b1; - 3'b0?0: {X} = 1'b0; - 3'b1?0: {X} = 1'b1; - 3'b?01: {X} = 1'b0; - 3'b?11: {X} = 1'b1; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_mux_2to1_N (Y,A0,A1,S); -output Y; -reg Y; -input A0; -input A1; -input S; -always @* casez ({A0,A1,S}) - 3'b0?0: {Y} = 1'b1; - 3'b1?0: {Y} = 1'b0; - 3'b?01: {Y} = 1'b1; - 3'b?11: {Y} = 1'b0; - 3'b00?: {Y} = 1'b1; - 3'b11?: {Y} = 1'b0; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_mux_4to2 (X,A0,A1,A2,A3,S0,S1); -output X; -reg X; -input A0; -input A1; -input A2; -input A3; -input S0; -input S1; -always @* casez ({A0,A1,A2,A3,S0,S1}) - 6'b0???00: {X} = 1'b0; - 6'b1???00: {X} = 1'b1; - 6'b?0??10: {X} = 1'b0; - 6'b?1??10: {X} = 1'b1; - 6'b??0?01: {X} = 1'b0; - 6'b??1?01: {X} = 1'b1; - 6'b???011: {X} = 1'b0; - 6'b???111: {X} = 1'b1; - 6'b0000??: {X} = 1'b0; - 6'b1111??: {X} = 1'b1; - 6'b00???0: {X} = 1'b0; - 6'b11???0: {X} = 1'b1; - 6'b??00?1: {X} = 1'b0; - 6'b??11?1: {X} = 1'b1; - 6'b0?0?0?: {X} = 1'b0; - 6'b1?1?0?: {X} = 1'b1; - 6'b?0?01?: {X} = 1'b0; - 6'b?1?11?: {X} = 1'b1; -endcase; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_pwrgood$l_pp$G (UDP_OUT,UDP_IN,VGND); -output UDP_OUT; -input UDP_IN; -input VGND; -assign UDP_OUT = UDP_IN; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_pwrgood_pp$G (UDP_OUT,UDP_IN,VGND); -output UDP_OUT; -input UDP_IN; -input VGND; -assign UDP_OUT = UDP_IN; -endmodule -(* noblackbox *) module sky130_fd_sc_hs__udp_pwrgood_pp$P (UDP_OUT,UDP_IN,VPWR); -output UDP_OUT; -input UDP_IN; -input VPWR; -assign UDP_OUT = UDP_IN; -endmodule // sky130_fd_sc_hs__udp_pwrgood_pp - -(* noblackbox *) module sky130_fd_sc_hs__a2bb2o (X,A1_N,A2_N,B1,B2); - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - wire and0_out ; - wire nor0_out ; - wire or0_out_X; - - and and0 (and0_out , B1, B2 ); - nor nor0 (nor0_out , A1_N, A2_N ); - or or0 (or0_out_X, nor0_out, and0_out); - buf buf0 (X , or0_out_X ); -endmodule // sky130_fd_sc_hs__a2bb2o - -(* noblackbox *) module sky130_fd_sc_hs__a2bb2o_1 (X,A1_N,A2_N,B1,B2); - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); -endmodule // sky130_fd_sc_hs__a2bb2o_1 - -(* noblackbox *) module sky130_fd_sc_hs__a2bb2o_2 (X,A1_N,A2_N,B1,B2); - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); -endmodule // sky130_fd_sc_hs__a2bb2o_2 - -(* noblackbox *) module sky130_fd_sc_hs__a2bb2o_4 (X,A1_N,A2_N,B1,B2); - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2o base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); -endmodule // sky130_fd_sc_hs__a2bb2o_4 - -(* noblackbox *) module sky130_fd_sc_hs__a2bb2oi (Y,A1_N,A2_N,B1,B2); - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - wire and0_out ; - wire nor0_out ; - wire nor1_out_Y; - - and and0 (and0_out , B1, B2 ); - nor nor0 (nor0_out , A1_N, A2_N ); - nor nor1 (nor1_out_Y, nor0_out, and0_out); - buf buf0 (Y , nor1_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2bb2oi_1 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2bb2oi_2 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2bb2oi_4 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2bb2oi base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21bo (X,A1,A2,B1_N); - - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - wire nand0_out ; - wire nand1_out_X; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out_X, B1_N, nand0_out); - buf buf0 (X , nand1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21bo_1 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21bo_2 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21bo_4 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21bo base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21boi (Y,A1,A2,B1_N); - - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - wire b ; - wire and0_out ; - wire nor0_out_Y; - - - not not0 (b , B1_N ); - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, b, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21boi_0 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21boi_1 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21boi_2 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21boi_4 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21boi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21o (X,A1,A2,B1); - - - - output X ; - input A1; - input A2; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21o_1 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21o_2 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21o_4 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21oi (Y,A1,A2,B1); - - - - output Y ; - input A1; - input A2; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21oi_1 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21oi_2 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a21oi_4 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a21oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22o (X,A1,A2,B1,B2); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - or or0 (or0_out_X, and1_out, and0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22o_1 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22o_2 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22o_4 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22oi (Y,A1,A2,B1,B2); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - wire nand0_out ; - wire nand1_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out , B2, B1 ); - and and0 (and0_out_Y, nand0_out, nand1_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22oi_1 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22oi_2 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a22oi_4 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a22oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31o (X,A1,A2,A3,B1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A3, A1, A2 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31o_1 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31o_2 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31o_4 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31oi (Y,A1,A2,A3,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A3, A1, A2 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31oi_1 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31oi_2 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a31oi_4 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a31oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32o (X,A1,A2,A3,B1,B2); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , A3, A1, A2 ); - and and1 (and1_out , B1, B2 ); - or or0 (or0_out_X, and1_out, and0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32o_1 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32o_2 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32o_4 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32oi (Y,A1,A2,A3,B1,B2); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire nand0_out ; - wire nand1_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1, A3 ); - nand nand1 (nand1_out , B2, B1 ); - and and0 (and0_out_Y, nand0_out, nand1_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32oi_1 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32oi_2 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a32oi_4 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a32oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41o (X,A1,A2,A3,A4,B1); - - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2, A3, A4 ); - or or0 (or0_out_X, and0_out, B1 ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41o_1 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41o_2 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41o_4 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41oi (Y,A1,A2,A3,A4,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2, A3, A4 ); - nor nor0 (nor0_out_Y, B1, and0_out ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41oi_1 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41oi_2 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a41oi_4 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a41oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211o (X,A1,A2,B1,C1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, and0_out, C1, B1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211o_1 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211o_2 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211o_4 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211oi (Y,A1,A2,B1,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, B1, C1); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211oi_1 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211oi_2 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a211oi_4 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a211oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221o (X,A1,A2,B1,B2,C1); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire and0_out ; - wire and1_out ; - wire or0_out_X; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - or or0 (or0_out_X, and1_out, and0_out, C1); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221o_1 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221o_2 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221o_4 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221oi (Y,A1,A2,B1,B2,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire and0_out ; - wire and1_out ; - wire nor0_out_Y; - - - and and0 (and0_out , B1, B2 ); - and and1 (and1_out , A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, C1, and1_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221oi_1 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221oi_2 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a221oi_4 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a221oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule - -(* noblackbox *) module sky130_fd_sc_hs__a222oi (Y,A1,A2,B1,B2,C1,C2); - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - wire nand0_out ; - wire nand1_out ; - wire nand2_out ; - wire and0_out_Y; - - - nand nand0 (nand0_out , A2, A1 ); - nand nand1 (nand1_out , B2, B1 ); - nand nand2 (nand2_out , C2, C1 ); - and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out); - buf buf0 (Y , and0_out_Y ); - - -endmodule // sky130_fd_sc_hs__a222oi - -(* noblackbox *) module sky130_fd_sc_hs__a222oi_1 (Y,A1,A2,B1,B2,C1,C2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a222oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1), - .C2(C2) - ); -endmodule // sky130_fd_sc_hs__a222oi_1 - -(* noblackbox *) module sky130_fd_sc_hs__a222oi_2 (Y,A1,A2,B1,B2,C1,C2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a222oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1), - .C2(C2) - ); -endmodule // sky130_fd_sc_hs__a222oi_2 - -(* noblackbox *) module sky130_fd_sc_hs__a222oi_4 (Y,A1,A2,B1,B2,C1,C2); - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a222oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1), - .C2(C2) - ); -endmodule // sky130_fd_sc_hs__a222oi_4 - - -(* noblackbox *) module sky130_fd_sc_hs__a222o (X,A1,A2,B1,B2,C1, C2); - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - wire and0_out ; - wire and1_out ; - wire and2_out ; - wire or0_out_X; - - and and0 (and0_out , A1, A2); - and and0 (and1_out , B1, B2); - and and0 (and2_out , C1, C2); - or or0 (or0_out_X, and0_out, and1_out, and2_out); - buf buf0 (X , or0_out_X ); -endmodule // sky130_fd_sc_hs__a222o - - -(* noblackbox *) module sky130_fd_sc_hs__a222o_1 (X,A1,A2,B1,B2,C1, C2); - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - sky130_fd_sc_hs__a222oi base (.Y(Y), .A1(A1), .A2(A2), .B1(B1), - .B2(B2), .C1(C1), .C2(C2)); -endmodule // sky130_fd_sc_hs__a222o_1 - -(* noblackbox *) module sky130_fd_sc_hs__a222o_2 (X,A1,A2,B1,B2,C1, C2); - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - input C2; - - sky130_fd_sc_hs__a222oi base (.Y(Y), .A1(A1), .A2(A2), .B1(B1), - .B2(B2), .C1(C1), .C2(C2)); -endmodule // sky130_fd_sc_hs__a222o_2 - -(* noblackbox *) module sky130_fd_sc_hs__a311o (X,A1,A2,A3,B1,C1); - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - wire and0_out ; - wire or0_out_X; - - and and0 (and0_out , A3, A1, A2 ); - or or0 (or0_out_X, and0_out, C1, B1); - buf buf0 (X , or0_out_X ); -endmodule // sky130_fd_sc_hs__a311o - -(* noblackbox *) module sky130_fd_sc_hs__a311o_1 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); -endmodule // sky130_fd_sc_hs__a311o_1 - -(* noblackbox *) module sky130_fd_sc_hs__a311o_2 (X,A1,A2,A3,B1,C1); - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); -endmodule - -(* noblackbox *) module sky130_fd_sc_hs__a311o_4 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311o base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a311oi (Y,A1,A2,A3,B1,C1); - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A3, A1, A2 ); - nor nor0 (nor0_out_Y, and0_out, B1, C1); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a311oi_1 (Y,A1,A2,A3,B1,C1); - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); -endmodule // sky130_fd_sc_hs__a311oi_1 - -(* noblackbox *) module sky130_fd_sc_hs__a311oi_2 (Y,A1,A2,A3,B1,C1); - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); -endmodule // sky130_fd_sc_hs__a311oi_2 - -(* noblackbox *) module sky130_fd_sc_hs__a311oi_4 (Y,A1,A2,A3,B1,C1); - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a311oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); -endmodule // sky130_fd_sc_hs__a311oi_4 - -(* noblackbox *) module sky130_fd_sc_hs__a2111o (X,A1,A2,B1,C1,D1); - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - wire and0_out ; - wire or0_out_X; - - - and and0 (and0_out , A1, A2 ); - or or0 (or0_out_X, C1, B1, and0_out, D1); - buf buf0 (X , or0_out_X ); -endmodule // sky130_fd_sc_hs__a2111o - -(* noblackbox *) module sky130_fd_sc_hs__a2111o_1 (X,A1,A2,B1,C1,D1); - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); -endmodule // sky130_fd_sc_hs__a2111o_1 - -(* noblackbox *) module sky130_fd_sc_hs__a2111o_2 (X,A1,A2,B1,C1,D1); - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); -endmodule // sky130_fd_sc_hs__a2111o_2 - -(* noblackbox *) module sky130_fd_sc_hs__a2111o_4 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111o base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2111oi (Y,A1,A2,B1,C1,D1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire and0_out ; - wire nor0_out_Y; - - - and and0 (and0_out , A1, A2 ); - nor nor0 (nor0_out_Y, B1, C1, D1, and0_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2111oi_0 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2111oi_1 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2111oi_2 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__a2111oi_4 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__a2111oi base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2 (X,A,B); - - - - output X; - input A; - input B; - - - wire and0_out_X; - - - and and0 (and0_out_X, A, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2_0 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2b (X,A_N,B); - - - - output X ; - input A_N; - input B ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, not0_out, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2b_1 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2b_2 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and2b_4 (X,A_N,B); - - - output X ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and2b base ( - .X(X), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire and0_out_X; - - - and and0 (and0_out_X, C, A, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3b (X,A_N,B,C); - - - - output X ; - input A_N; - input B ; - input C ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, C, not0_out, B ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3b_1 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3b_2 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and3b_4 (X,A_N,B,C); - - - output X ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and3b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4 (X,A,B,C,D); - - - - output X; - input A; - input B; - input C; - input D; - - - wire and0_out_X; - - - and and0 (and0_out_X, A, B, C, D ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4_1 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4_2 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4_4 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4b (X,A_N,B,C,D); - - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , A_N ); - and and0 (and0_out_X, not0_out, B, C, D); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4b_1 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4b_2 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4b_4 (X,A_N,B,C,D); - - - output X ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4b base ( - .X(X), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4bb (X,A_N,B_N,C,D); - - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - wire nor0_out ; - wire and0_out_X; - - - nor nor0 (nor0_out , A_N, B_N ); - and and0 (and0_out_X, nor0_out, C, D ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4bb_1 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4bb_2 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__and4bb_4 (X,A_N,B_N,C,D); - - - output X ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__and4bb base ( - .X(X), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_4 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_6 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_12 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__buf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__buf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufbuf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufbuf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__bufbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufbuf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__bufbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufinv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufinv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__bufinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__bufinv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__bufinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf_4 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf_8 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkbuf_16 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkbuf base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s15 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s15_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s15 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s15_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s15 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s18 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s18_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s18 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s18_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s18 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s25 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s25_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s25 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s25_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s25 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s50 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s50_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s50 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlybuf4s50_2 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkdlybuf4s50 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv_1 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinvlp (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinvlp_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinvlp base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkinvlp_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__clkinvlp base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__conb (HI,LO); - - - - output HI; - output LO; - - - mod_pullup pullup0 (HI ); - mod_pulldown pulldown0 (LO ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__conb_1 (HI,LO); - - - output HI; - output LO; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__conb base ( - .HI(HI), - .LO(LO) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap_3 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap_4 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap_6 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap_8 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__decap_12 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__decap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfbbn (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - wire RESET; - wire SET ; - wire CLK ; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - not not2 (CLK , CLK_N ); - sky130_fd_sc_hs__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, D); - buf buf0 (Q , buf_Q ); - not not3 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfbbn_1 (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfbbn_2 (Q,Q_N,D,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfbbp (Q,Q_N,D,CLK,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input CLK ; - input SET_B ; - input RESET_B; - - - wire RESET; - wire SET ; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - sky130_fd_sc_hs__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, D); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfbbp_1 (Q,Q_N,D,CLK,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input CLK ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfbbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .CLK(CLK), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrbp (Q,Q_N,CLK,D,RESET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - wire buf_Q; - wire RESET; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , D, CLK, RESET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrbp_1 (Q,Q_N,CLK,D,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrbp_2 (Q,Q_N,CLK,D,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtn (Q,CLK_N,D,RESET_B); - - - - output Q ; - input CLK_N ; - input D ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire intclk; - - - not not0 (RESET , RESET_B ); - not not1 (intclk, CLK_N ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , D, intclk, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtn_1 (Q,CLK_N,D,RESET_B); - - - output Q ; - input CLK_N ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrtn base ( - .Q(Q), - .CLK_N(CLK_N), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtp (Q,CLK,D,RESET_B); - - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - wire buf_Q; - wire RESET; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , D, CLK, RESET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtp_1 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtp_2 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfrtp_4 (Q,CLK,D,RESET_B); - - - output Q ; - input CLK ; - input D ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfsbp (Q,Q_N,CLK,D,SET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - wire buf_Q; - wire SET ; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hs__udp_dff$PS dff0 (buf_Q , D, CLK, SET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfsbp_1 (Q,Q_N,CLK,D,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfsbp_2 (Q,Q_N,CLK,D,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfstp (Q,CLK,D,SET_B); - - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - wire buf_Q; - wire SET ; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hs__udp_dff$PS dff0 (buf_Q , D, CLK, SET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfstp_1 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfstp_2 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfstp_4 (Q,CLK,D,SET_B); - - - output Q ; - input CLK ; - input D ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxbp (Q,Q_N,CLK,D); - - - - output Q ; - output Q_N; - input CLK; - input D ; - - - wire buf_Q; - - - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , D, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxbp_1 (Q,Q_N,CLK,D); - - - output Q ; - output Q_N; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxbp_2 (Q,Q_N,CLK,D); - - - output Q ; - output Q_N; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxtp (Q,CLK,D); - - - - output Q ; - input CLK; - input D ; - - - wire buf_Q; - - - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , D, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxtp_1 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxtp_2 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dfxtp_4 (Q,CLK,D); - - - output Q ; - input CLK; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__diode (DIODE); - - - - input DIODE; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__diode_2 (DIODE); - - - input DIODE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__diode base ( - .DIODE(DIODE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlclkp (GCLK,GATE,CLK); - - - - output GCLK; - input GATE; - input CLK ; - - - wire m0 ; - wire clkn; - - - not not0 (clkn , CLK ); - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (m0 , GATE, clkn ); - and and0 (GCLK , m0, CLK ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlclkp_1 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlclkp_2 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlclkp_4 (GCLK,GATE,CLK); - - - output GCLK; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlclkp base ( - .GCLK(GCLK), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbn (Q,Q_N,RESET_B,D,GATE_N); - - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - wire RESET ; - wire intgate; - wire buf_Q ; - - - not not0 (RESET , RESET_B ); - not not1 (intgate, GATE_N ); - sky130_fd_sc_hs__udp_dlatch$PR dlatch0 (buf_Q , D, intgate, RESET); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbn_1 (Q,Q_N,RESET_B,D,GATE_N); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrbn base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbn_2 (Q,Q_N,RESET_B,D,GATE_N); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrbn base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbp (Q,Q_N,RESET_B,D,GATE); - - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - wire RESET; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_dlatch$PR dlatch0 (buf_Q , D, GATE, RESET ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbp_1 (Q,Q_N,RESET_B,D,GATE); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrbp base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrbp_2 (Q,Q_N,RESET_B,D,GATE); - - - output Q ; - output Q_N ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrbp base ( - .Q(Q), - .Q_N(Q_N), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtn (Q,RESET_B,D,GATE_N); - - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - wire RESET ; - wire intgate; - wire buf_Q ; - - - not not0 (RESET , RESET_B ); - not not1 (intgate, GATE_N ); - sky130_fd_sc_hs__udp_dlatch$PR dlatch0 (buf_Q , D, intgate, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtn_1 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtn_2 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtn_4 (Q,RESET_B,D,GATE_N); - - - output Q ; - input RESET_B; - input D ; - input GATE_N ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtn base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtp (Q,RESET_B,D,GATE); - - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - wire RESET; - wire buf_Q; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_dlatch$PR dlatch0 (buf_Q , D, GATE, RESET ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtp_1 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtp_2 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlrtp_4 (Q,RESET_B,D,GATE); - - - output Q ; - input RESET_B; - input D ; - input GATE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlrtp base ( - .Q(Q), - .RESET_B(RESET_B), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxbn (Q,Q_N,D,GATE_N); - - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - wire GATE ; - wire buf_Q; - - - not not0 (GATE , GATE_N ); - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxbn_1 (Q,Q_N,D,GATE_N); - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxbn_2 (Q,Q_N,D,GATE_N); - - - output Q ; - output Q_N ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxbp (Q,Q_N,D,GATE); - - - - output Q ; - output Q_N ; - input D ; - input GATE; - - - wire buf_Q; - - - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxbp_1 (Q,Q_N,D,GATE); - - - output Q ; - output Q_N ; - input D ; - input GATE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtn (Q,D,GATE_N); - - - - output Q ; - input D ; - input GATE_N; - - - wire GATE ; - wire buf_Q; - - - not not0 (GATE , GATE_N ); - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtn_1 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtn_2 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtn_4 (Q,D,GATE_N); - - - output Q ; - input D ; - input GATE_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxtn base ( - .Q(Q), - .D(D), - .GATE_N(GATE_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtp (Q,D,GATE); - - - - output Q ; - input D ; - input GATE; - - - wire buf_Q; - - - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (buf_Q , D, GATE ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlxtp_1 (Q,D,GATE); - - - output Q ; - input D ; - input GATE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlxtp base ( - .Q(Q), - .D(D), - .GATE(GATE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd1 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd1_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlygate4sd1 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd2 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd2_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlygate4sd2 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd3 (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlygate4sd3_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlygate4sd3 base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv3sd1_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv3sd2_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv3sd3_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv5sd1_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv5sd2_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__clkdlyinv5sd3_1 (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - not not0 (not0_out_Y , A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s2s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s2s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlymetal6s2s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s4s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s4s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlymetal6s4s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s6s (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__dlymetal6s6s_1 (X,A); - - - output X; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__dlymetal6s6s base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ebufn (Z,A,TE_B); - - - - output Z ; - input A ; - input TE_B; - - - bufif0 bufif00 (Z , A, TE_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ebufn_1 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ebufn_2 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ebufn_4 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ebufn_8 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ebufn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__edfxbp (Q,Q_N,CLK,D,DE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__edfxbp_1 (Q,Q_N,CLK,D,DE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__edfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__edfxtp (Q,CLK,D,DE); - - - - output Q ; - input CLK; - input D ; - input DE ; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__edfxtp_1 (Q,CLK,D,DE); - - - output Q ; - input CLK; - input D ; - input DE ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__edfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn (Z,A,TE_B); - - - - output Z ; - input A ; - input TE_B; - - - notif0 notif00 (Z , A, TE_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn_0 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn_1 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn_2 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn_4 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvn_8 (Z,A,TE_B); - - - output Z ; - input A ; - input TE_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvn base ( - .Z(Z), - .A(A), - .TE_B(TE_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvp (Z,A,TE); - - - - output Z ; - input A ; - input TE; - - - notif1 notif10 (Z , A, TE ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvp_1 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvp_2 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvp_4 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__einvp_8 (Z,A,TE); - - - output Z ; - input A ; - input TE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__einvp base ( - .Z(Z), - .A(A), - .TE(TE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fa (COUT,SUM,A,B,CIN); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - wire or0_out ; - wire and0_out ; - wire and1_out ; - wire and2_out ; - wire nor0_out ; - wire nor1_out ; - wire or1_out_COUT; - wire or2_out_SUM ; - - - or or0 (or0_out , CIN, B ); - and and0 (and0_out , or0_out, A ); - and and1 (and1_out , B, CIN ); - or or1 (or1_out_COUT, and1_out, and0_out); - buf buf0 (COUT , or1_out_COUT ); - and and2 (and2_out , CIN, A, B ); - nor nor0 (nor0_out , A, or0_out ); - nor nor1 (nor1_out , nor0_out, COUT ); - or or2 (or2_out_SUM , nor1_out, and2_out); - buf buf1 (SUM , or2_out_SUM ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fa_1 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fa_2 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fa_4 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fa base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fah (COUT,SUM,A,B,CI); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CI ; - - - wire xor0_out_SUM; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_COUT; - - - xor xor0 (xor0_out_SUM, A, B, CI ); - buf buf0 (SUM , xor0_out_SUM ); - and and0 (a_b , A, B ); - and and1 (a_ci , A, CI ); - and and2 (b_ci , B, CI ); - or or0 (or0_out_COUT, a_b, a_ci, b_ci); - buf buf1 (COUT , or0_out_COUT ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fah_1 (COUT,SUM,A,B,CI); - - - output COUT; - output SUM ; - input A ; - input B ; - input CI ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fah base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CI(CI) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fahcin (COUT,SUM,A,B,CIN); - - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - wire ci ; - wire xor0_out_SUM; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_COUT; - - - not not0 (ci , CIN ); - xor xor0 (xor0_out_SUM, A, B, ci ); - buf buf0 (SUM , xor0_out_SUM ); - and and0 (a_b , A, B ); - and and1 (a_ci , A, ci ); - and and2 (b_ci , B, ci ); - or or0 (or0_out_COUT, a_b, a_ci, b_ci); - buf buf1 (COUT , or0_out_COUT ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fahcin_1 (COUT,SUM,A,B,CIN); - - - output COUT; - output SUM ; - input A ; - input B ; - input CIN ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fahcin base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B), - .CIN(CIN) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fahcon (COUT_N,SUM,A,B,CI); - - - - output COUT_N; - output SUM ; - input A ; - input B ; - input CI ; - - - wire xor0_out_SUM ; - wire a_b ; - wire a_ci ; - wire b_ci ; - wire or0_out_coutn; - - - xor xor0 (xor0_out_SUM , A, B, CI ); - buf buf0 (SUM , xor0_out_SUM ); - nor nor0 (a_b , A, B ); - nor nor1 (a_ci , A, CI ); - nor nor2 (b_ci , B, CI ); - or or0 (or0_out_coutn, a_b, a_ci, b_ci); - buf buf1 (COUT_N , or0_out_coutn ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fahcon_1 (COUT_N,SUM,A,B,CI); - - - output COUT_N; - output SUM ; - input A ; - input B ; - input CI ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fahcon base ( - .COUT_N(COUT_N), - .SUM(SUM), - .A(A), - .B(B), - .CI(CI) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fill (); - - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fill_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fill_2 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fill_4 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__fill_8 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__fill base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ha (COUT,SUM,A,B); - - - - output COUT; - output SUM ; - input A ; - input B ; - - - wire and0_out_COUT; - wire xor0_out_SUM ; - - - and and0 (and0_out_COUT, A, B ); - buf buf0 (COUT , and0_out_COUT ); - xor xor0 (xor0_out_SUM , B, A ); - buf buf1 (SUM , xor0_out_SUM ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ha_1 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ha_2 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__ha_4 (COUT,SUM,A,B); - - - output COUT; - output SUM ; - input A ; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__ha base ( - .COUT(COUT), - .SUM(SUM), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_1 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_2 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_4 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_6 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_8 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_12 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__inv_16 (Y,A); - - - output Y; - input A; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__inv base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_bleeder (SHORT); - - - input SHORT; - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_bleeder_1 (SHORT); - - - input SHORT; - - - wire VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_bleeder base ( - .SHORT(SHORT) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr_1 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr_2 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr_4 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr_8 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkbufkapwr_16 (X,A); - - - output X; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkbufkapwr base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr (Y,A); - - - - output Y; - input A; - - - wire not0_out_Y; - - - not not0 (not0_out_Y, A ); - buf buf0 (Y , not0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr_1 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr_2 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr_4 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr_8 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_clkinvkapwr_16 (Y,A); - - - output Y; - input A; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_clkinvkapwr base ( - .Y(Y), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr_3 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr_4 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr_6 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr_8 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_decapkapwr_12 (); - - - supply1 VPWR ; - supply1 KAPWR; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_decapkapwr base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso0n (X,A,SLEEP_B); - - - - output X ; - input A ; - input SLEEP_B; - - - and and0 (X , A, SLEEP_B ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso0n_1 (X,A,SLEEP_B); - - - output X ; - input A ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_inputiso0n base ( - .X(X), - .A(A), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso0p (X,A,SLEEP); - - - - output X ; - input A ; - input SLEEP; - - - wire sleepn; - - - not not0 (sleepn, SLEEP ); - and and0 (X , A, sleepn ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso0p_1 (X,A,SLEEP); - - - output X ; - input A ; - input SLEEP; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_inputiso0p base ( - .X(X), - .A(A), - .SLEEP(SLEEP) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso1n (X,A,SLEEP_B); - - - - output X ; - input A ; - input SLEEP_B; - - - wire SLEEP; - - - not not0 (SLEEP , SLEEP_B ); - or or0 (X , A, SLEEP ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso1n_1 (X,A,SLEEP_B); - - - output X ; - input A ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_inputiso1n base ( - .X(X), - .A(A), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso1p (X,A,SLEEP); - - - - output X ; - input A ; - input SLEEP; - - - or or0 (X , A, SLEEP ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputiso1p_1 (X,A,SLEEP); - - - output X ; - input A ; - input SLEEP; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_inputiso1p base ( - .X(X), - .A(A), - .SLEEP(SLEEP) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputisolatch (Q,D,SLEEP_B); - - - - output Q ; - input D ; - input SLEEP_B; - - - wire buf_Q; - - - sky130_fd_sc_hs__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_inputisolatch_1 (Q,D,SLEEP_B); - - - output Q ; - input D ; - input SLEEP_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_inputisolatch base ( - .Q(Q), - .D(D), - .SLEEP_B(SLEEP_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc (X,SLEEP,A); - - - - output X ; - input SLEEP; - input A ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , SLEEP ); - and and0 (and0_out_X, not0_out, A ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc_1 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc_2 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc_4 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc_8 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrc_16 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrc base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrckapwr (X,SLEEP,A); - - - - output X ; - input SLEEP; - input A ; - - - wire not0_out ; - wire and0_out_X; - - - not not0 (not0_out , SLEEP ); - and and0 (and0_out_X, not0_out, A ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_isobufsrckapwr_16 (X,SLEEP,A); - - - output X ; - input SLEEP; - input A ; - - - supply1 KAPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_isobufsrckapwr base ( - .X(X), - .SLEEP(SLEEP), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap_1 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap_2 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap_4 (X,A); - - - output X; - input A; - - - wire VPWRIN; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_hl_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_4 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap (X,A); - - - - output X; - input A; - - - buf buf0 (X , A ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap_1 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap_2 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap_4 (X,A); - - - output X; - input A; - - - wire LOWLVPWR; - supply1 VPWR ; - supply0 VGND ; - supply1 VPB ; - - sky130_fd_sc_hs__lpflow_lsbuf_lh_isowell_tap base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__macro_sparecell (LO); - - - - output LO; - - - wire nor2left ; - wire invleft ; - wire nor2right; - wire invright ; - wire nd2left ; - wire nd2right ; - wire tielo ; - wire net7 ; - - - sky130_fd_sc_hs__inv_2 inv0 (.A(nor2left) , .Y(invleft) ); - sky130_fd_sc_hs__inv_2 inv1 (.A(nor2right), .Y(invright) ); - sky130_fd_sc_hs__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) ); - sky130_fd_sc_hs__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right)); - sky130_fd_sc_hs__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) ); - sky130_fd_sc_hs__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) ); - sky130_fd_sc_hs__conb_1 conb0 (.LO(tielo) , .HI(net7) ); - buf buf0 (LO , tielo ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__maj3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire or0_out ; - wire and0_out ; - wire and1_out ; - wire or1_out_X; - - - or or0 (or0_out , B, A ); - and and0 (and0_out , or0_out, C ); - and and1 (and1_out , A, B ); - or or1 (or1_out_X, and1_out, and0_out); - buf buf0 (X , or1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__maj3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__maj3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__maj3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__maj3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2 (X,A0,A1,S); - - - - output X ; - input A0; - input A1; - input S ; - - - wire mux_2to10_out_X; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S ); - buf buf0 (X , mux_2to10_out_X); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2_1 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2_2 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2_4 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2_8 (X,A0,A1,S); - - - output X ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2 base ( - .X(X), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2i (Y,A0,A1,S); - - - - output Y ; - input A0; - input A1; - input S ; - - - wire mux_2to1_n0_out_Y; - - - sky130_fd_sc_hs__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S ); - buf buf0 (Y , mux_2to1_n0_out_Y); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2i_1 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2i_2 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux2i_4 (Y,A0,A1,S); - - - output Y ; - input A0; - input A1; - input S ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux2i base ( - .Y(Y), - .A0(A0), - .A1(A1), - .S(S) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux4 (X,A0,A1,A2,A3,S0,S1); - - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - wire mux_4to20_out_X; - - - sky130_fd_sc_hs__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1); - buf buf0 (X , mux_4to20_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux4_1 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux4_2 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__mux4_4 (X,A0,A1,A2,A3,S0,S1); - - - output X ; - input A0; - input A1; - input A2; - input A3; - input S0; - input S1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__mux4 base ( - .X(X), - .A0(A0), - .A1(A1), - .A2(A2), - .A3(A3), - .S0(S0), - .S1(S1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, B, A ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2_8 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2b (Y,A_N,B); - - - - output Y ; - input A_N; - input B ; - - - wire not0_out ; - wire or0_out_Y; - - - not not0 (not0_out , B ); - or or0 (or0_out_Y, not0_out, A_N ); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2b_1 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2b_2 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand2b_4 (Y,A_N,B); - - - output Y ; - input A_N; - input B ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand2b base ( - .Y(Y), - .A_N(A_N), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3 (Y,A,B,C); - - - - output Y; - input A; - input B; - input C; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, B, A, C ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3_1 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3_2 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3_4 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3b (Y,A_N,B,C); - - - - output Y ; - input A_N; - input B ; - input C ; - - - wire not0_out ; - wire nand0_out_Y; - - - not not0 (not0_out , A_N ); - nand nand0 (nand0_out_Y, B, not0_out, C ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3b_1 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3b_2 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand3b_4 (Y,A_N,B,C); - - - output Y ; - input A_N; - input B ; - input C ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand3b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4 (Y,A,B,C,D); - - - - output Y; - input A; - input B; - input C; - input D; - - - wire nand0_out_Y; - - - nand nand0 (nand0_out_Y, D, C, B, A ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4_1 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4_2 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4_4 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4b (Y,A_N,B,C,D); - - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - wire not0_out ; - wire nand0_out_Y; - - - not not0 (not0_out , A_N ); - nand nand0 (nand0_out_Y, D, C, B, not0_out); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4b_1 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4b_2 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4b_4 (Y,A_N,B,C,D); - - - output Y ; - input A_N; - input B ; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4b base ( - .Y(Y), - .A_N(A_N), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4bb (Y,A_N,B_N,C,D); - - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - wire nand0_out; - wire or0_out_Y; - - - nand nand0 (nand0_out, D, C ); - or or0 (or0_out_Y, B_N, A_N, nand0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4bb_1 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4bb_2 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nand4bb_4 (Y,A_N,B_N,C,D); - - - output Y ; - input A_N; - input B_N; - input C ; - input D ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nand4bb base ( - .Y(Y), - .A_N(A_N), - .B_N(B_N), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, A, B ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2_8 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2b (Y,A,B_N); - - - - output Y ; - input A ; - input B_N; - - - wire not0_out ; - wire and0_out_Y; - - - not not0 (not0_out , A ); - and and0 (and0_out_Y, not0_out, B_N ); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2b_1 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2b_2 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor2b_4 (Y,A,B_N); - - - output Y ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor2b base ( - .Y(Y), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3 (Y,A,B,C); - - - - output Y; - input A; - input B; - input C; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, C, A, B ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3_1 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3_2 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3_4 (Y,A,B,C); - - - output Y; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3 base ( - .Y(Y), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3b (Y,A,B,C_N); - - - - output Y ; - input A ; - input B ; - input C_N; - - - wire nor0_out ; - wire and0_out_Y; - - - nor nor0 (nor0_out , A, B ); - and and0 (and0_out_Y, C_N, nor0_out ); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3b_1 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3b_2 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor3b_4 (Y,A,B,C_N); - - - output Y ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor3b base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4 (Y,A,B,C,D); - - - - output Y; - input A; - input B; - input C; - input D; - - - wire nor0_out_Y; - - - nor nor0 (nor0_out_Y, A, B, C, D ); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4_1 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4_2 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4_4 (Y,A,B,C,D); - - - output Y; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4 base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4b (Y,A,B,C,D_N); - - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - wire not0_out ; - wire nor0_out_Y; - - - not not0 (not0_out , D_N ); - nor nor0 (nor0_out_Y, A, B, C, not0_out); - buf buf0 (Y , nor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4b_1 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4b_2 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4b_4 (Y,A,B,C,D_N); - - - output Y ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4b base ( - .Y(Y), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4bb (Y,A,B,C_N,D_N); - - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - wire nor0_out ; - wire and0_out_Y; - - - nor nor0 (nor0_out , A, B ); - and and0 (and0_out_Y, nor0_out, C_N, D_N); - buf buf0 (Y , and0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4bb_1 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4bb_2 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__nor4bb_4 (Y,A,B,C_N,D_N); - - - output Y ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__nor4bb base ( - .Y(Y), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2a (X,A1_N,A2_N,B1,B2); - - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire nand0_out ; - wire or0_out ; - wire and0_out_X; - - - nand nand0 (nand0_out , A2_N, A1_N ); - or or0 (or0_out , B2, B1 ); - and and0 (and0_out_X, nand0_out, or0_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2a_1 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2a_2 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2a_4 (X,A1_N,A2_N,B1,B2); - - - output X ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2a base ( - .X(X), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2ai (Y,A1_N,A2_N,B1,B2); - - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - wire nand0_out ; - wire or0_out ; - wire nand1_out_Y; - - - nand nand0 (nand0_out , A2_N, A1_N ); - or or0 (or0_out , B2, B1 ); - nand nand1 (nand1_out_Y, nand0_out, or0_out); - buf buf0 (Y , nand1_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2ai_1 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2ai_2 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2bb2ai_4 (Y,A1_N,A2_N,B1,B2); - - - output Y ; - input A1_N; - input A2_N; - input B1 ; - input B2 ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2bb2ai base ( - .Y(Y), - .A1_N(A1_N), - .A2_N(A2_N), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21a (X,A1,A2,B1); - - - - output X ; - input A1; - input A2; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21a_1 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21a_2 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21a_4 (X,A1,A2,B1); - - - output X ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ai (Y,A1,A2,B1); - - - - output Y ; - input A1; - input A2; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ai_0 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ai_1 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ai_2 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ai_4 (Y,A1,A2,B1); - - - output Y ; - input A1; - input A2; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ba (X,A1,A2,B1_N); - - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - wire nor0_out ; - wire nor1_out_X; - - - nor nor0 (nor0_out , A1, A2 ); - nor nor1 (nor1_out_X, B1_N, nor0_out ); - buf buf0 (X , nor1_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ba_1 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ba_2 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21ba_4 (X,A1,A2,B1_N); - - - output X ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21ba base ( - .X(X), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21bai (Y,A1,A2,B1_N); - - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - wire b ; - wire or0_out ; - wire nand0_out_Y; - - - not not0 (b , B1_N ); - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, b, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21bai_1 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21bai_2 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o21bai_4 (Y,A1,A2,B1_N); - - - output Y ; - input A1 ; - input A2 ; - input B1_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o21bai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1_N(B1_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22a (X,A1,A2,B1,B2); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - or or1 (or1_out , B2, B1 ); - and and0 (and0_out_X, or0_out, or1_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22a_1 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22a_2 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22a_4 (X,A1,A2,B1,B2); - - - output X ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22ai (Y,A1,A2,B1,B2); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - wire nor0_out ; - wire nor1_out ; - wire or0_out_Y; - - - nor nor0 (nor0_out , B1, B2 ); - nor nor1 (nor1_out , A1, A2 ); - or or0 (or0_out_Y, nor1_out, nor0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22ai_1 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22ai_2 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o22ai_4 (Y,A1,A2,B1,B2); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o22ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31a (X,A1,A2,A3,B1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31a_1 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31a_2 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31a_4 (X,A1,A2,A3,B1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31ai (Y,A1,A2,A3,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1, A3 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31ai_1 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31ai_2 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o31ai_4 (Y,A1,A2,A3,B1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o31ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32a (X,A1,A2,A3,B1,B2); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - or or1 (or1_out , B2, B1 ); - and and0 (and0_out_X, or0_out, or1_out); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32a_1 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32a_2 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32a_4 (X,A1,A2,A3,B1,B2); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32ai (Y,A1,A2,A3,B1,B2); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - wire nor0_out ; - wire nor1_out ; - wire or0_out_Y; - - - nor nor0 (nor0_out , A3, A1, A2 ); - nor nor1 (nor1_out , B1, B2 ); - or or0 (or0_out_Y, nor1_out, nor0_out); - buf buf0 (Y , or0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32ai_1 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32ai_2 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o32ai_4 (Y,A1,A2,A3,B1,B2); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input B2; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o32ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .B2(B2) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41a (X,A1,A2,A3,A4,B1); - - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A4, A3, A2, A1 ); - and and0 (and0_out_X, or0_out, B1 ); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41a_1 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41a_2 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41a_4 (X,A1,A2,A3,A4,B1); - - - output X ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41ai (Y,A1,A2,A3,A4,B1); - - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A4, A3, A2, A1 ); - nand nand0 (nand0_out_Y, B1, or0_out ); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41ai_1 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41ai_2 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o41ai_4 (Y,A1,A2,A3,A4,B1); - - - output Y ; - input A1; - input A2; - input A3; - input A4; - input B1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o41ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .A4(A4), - .B1(B1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211a (X,A1,A2,B1,C1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, or0_out, B1, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211a_1 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211a_2 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211a_4 (X,A1,A2,B1,C1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211ai (Y,A1,A2,B1,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, C1, or0_out, B1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211ai_1 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211ai_2 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o211ai_4 (Y,A1,A2,B1,C1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o211ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221a (X,A1,A2,B1,B2,C1); - - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire or0_out ; - wire or1_out ; - wire and0_out_X; - - - or or0 (or0_out , B2, B1 ); - or or1 (or1_out , A2, A1 ); - and and0 (and0_out_X, or0_out, or1_out, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221a_1 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221a_2 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221a_4 (X,A1,A2,B1,B2,C1); - - - output X ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221ai (Y,A1,A2,B1,B2,C1); - - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - wire or0_out ; - wire or1_out ; - wire nand0_out_Y; - - - or or0 (or0_out , B2, B1 ); - or or1 (or1_out , A2, A1 ); - nand nand0 (nand0_out_Y, or1_out, or0_out, C1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221ai_1 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221ai_2 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o221ai_4 (Y,A1,A2,B1,B2,C1); - - - output Y ; - input A1; - input A2; - input B1; - input B2; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o221ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .B2(B2), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311a (X,A1,A2,A3,B1,C1); - - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1, A3 ); - and and0 (and0_out_X, or0_out, B1, C1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311a_1 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311a_2 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311a_4 (X,A1,A2,A3,B1,C1); - - - output X ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311a base ( - .X(X), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311ai (Y,A1,A2,A3,B1,C1); - - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1, A3 ); - nand nand0 (nand0_out_Y, C1, or0_out, B1); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311ai_0 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311ai_1 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311ai_2 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o311ai_4 (Y,A1,A2,A3,B1,C1); - - - output Y ; - input A1; - input A2; - input A3; - input B1; - input C1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o311ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .A3(A3), - .B1(B1), - .C1(C1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111a (X,A1,A2,B1,C1,D1); - - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire or0_out ; - wire and0_out_X; - - - or or0 (or0_out , A2, A1 ); - and and0 (and0_out_X, B1, C1, or0_out, D1); - buf buf0 (X , and0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111a_1 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111a_2 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111a_4 (X,A1,A2,B1,C1,D1); - - - output X ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111a base ( - .X(X), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111ai (Y,A1,A2,B1,C1,D1); - - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - wire or0_out ; - wire nand0_out_Y; - - - or or0 (or0_out , A2, A1 ); - nand nand0 (nand0_out_Y, C1, B1, D1, or0_out); - buf buf0 (Y , nand0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111ai_1 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111ai_2 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__o2111ai_4 (Y,A1,A2,B1,C1,D1); - - - output Y ; - input A1; - input A2; - input B1; - input C1; - input D1; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__o2111ai base ( - .Y(Y), - .A1(A1), - .A2(A2), - .B1(B1), - .C1(C1), - .D1(D1) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2 (X,A,B); - - - - output X; - input A; - input B; - - - wire or0_out_X; - - - or or0 (or0_out_X, B, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2_0 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2b (X,A,B_N); - - - - output X ; - input A ; - input B_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , B_N ); - or or0 (or0_out_X, not0_out, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2b_1 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2b_2 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or2b_4 (X,A,B_N); - - - output X ; - input A ; - input B_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or2b base ( - .X(X), - .A(A), - .B_N(B_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire or0_out_X; - - - or or0 (or0_out_X, B, A, C ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3b (X,A,B,C_N); - - - - output X ; - input A ; - input B ; - input C_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , C_N ); - or or0 (or0_out_X, B, A, not0_out ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3b_1 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3b_2 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or3b_4 (X,A,B,C_N); - - - output X ; - input A ; - input B ; - input C_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or3b base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4 (X,A,B,C,D); - - - - output X; - input A; - input B; - input C; - input D; - - - wire or0_out_X; - - - or or0 (or0_out_X, D, C, B, A ); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4_1 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4_2 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4_4 (X,A,B,C,D); - - - output X; - input A; - input B; - input C; - input D; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4 base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D(D) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4b (X,A,B,C,D_N); - - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - wire not0_out ; - wire or0_out_X; - - - not not0 (not0_out , D_N ); - or or0 (or0_out_X, not0_out, C, B, A); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4b_1 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4b_2 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4b_4 (X,A,B,C,D_N); - - - output X ; - input A ; - input B ; - input C ; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4b base ( - .X(X), - .A(A), - .B(B), - .C(C), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4bb (X,A,B,C_N,D_N); - - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - wire nand0_out; - wire or0_out_X; - - - nand nand0 (nand0_out, D_N, C_N ); - or or0 (or0_out_X, B, A, nand0_out); - buf buf0 (X , or0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4bb_1 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4bb_2 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__or4bb_4 (X,A,B,C_N,D_N); - - - output X ; - input A ; - input B ; - input C_N; - input D_N; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__or4bb base ( - .X(X), - .A(A), - .B(B), - .C_N(C_N), - .D_N(D_N) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__probe_p (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__probe_p_8 (X,A); - - - output X; - input A; - - - supply0 VGND; - supply0 VNB ; - supply1 VPB ; - supply1 VPWR; - - sky130_fd_sc_hs__probe_p base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__probec_p (X,A); - - - - output X; - input A; - - - wire buf0_out_X; - - - buf buf0 (buf0_out_X, A ); - buf buf1 (X , buf0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__probec_p_8 (X,A); - - - output X; - input A; - - - supply0 VGND; - supply0 VNB ; - supply1 VPB ; - supply1 VPWR; - - sky130_fd_sc_hs__probec_p base ( - .X(X), - .A(A) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfbbn (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - wire RESET ; - wire SET ; - wire CLK ; - wire buf_Q ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - not not2 (CLK , CLK_N ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, mux_out); - buf buf0 (Q , buf_Q ); - not not3 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfbbn_1 (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfbbn_2 (Q,Q_N,D,SCD,SCE,CLK_N,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK_N ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfbbn base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK_N(CLK_N), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfbbp (Q,Q_N,D,SCD,SCE,CLK,SET_B,RESET_B); - - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK ; - input SET_B ; - input RESET_B; - - - wire RESET ; - wire SET ; - wire buf_Q ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (SET , SET_B ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$NSR dff0 (buf_Q , SET, RESET, CLK, mux_out); - buf buf0 (Q , buf_Q ); - not not2 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfbbp_1 (Q,Q_N,D,SCD,SCE,CLK,SET_B,RESET_B); - - - output Q ; - output Q_N ; - input D ; - input SCD ; - input SCE ; - input CLK ; - input SET_B ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfbbp base ( - .Q(Q), - .Q_N(Q_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .CLK(CLK), - .SET_B(SET_B), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrbp (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , mux_out, CLK, RESET); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrbp_1 (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrbp_2 (Q,Q_N,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtn (Q,CLK_N,D,SCD,SCE,RESET_B); - - - - output Q ; - input CLK_N ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire intclk ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - not not1 (intclk , CLK_N ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , mux_out, intclk, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtn_1 (Q,CLK_N,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK_N ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrtn base ( - .Q(Q), - .CLK_N(CLK_N), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtp (Q,CLK,D,SCD,SCE,RESET_B); - - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - wire buf_Q ; - wire RESET ; - wire mux_out; - - - not not0 (RESET , RESET_B ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$PR dff0 (buf_Q , mux_out, CLK, RESET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtp_1 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtp_2 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfrtp_4 (Q,CLK,D,SCD,SCE,RESET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input RESET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfrtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .RESET_B(RESET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfsbp (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - wire buf_Q ; - wire SET ; - wire mux_out; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$PS dff0 (buf_Q , mux_out, CLK, SET); - buf buf0 (Q , buf_Q ); - not not1 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfsbp_1 (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfsbp_2 (Q,Q_N,CLK,D,SCD,SCE,SET_B); - - - output Q ; - output Q_N ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfsbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfstp (Q,CLK,D,SCD,SCE,SET_B); - - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - wire buf_Q ; - wire SET ; - wire mux_out; - - - not not0 (SET , SET_B ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$PS dff0 (buf_Q , mux_out, CLK, SET); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfstp_1 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfstp_2 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfstp_4 (Q,CLK,D,SCD,SCE,SET_B); - - - output Q ; - input CLK ; - input D ; - input SCD ; - input SCE ; - input SET_B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfstp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE), - .SET_B(SET_B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxbp (Q,Q_N,CLK,D,SCD,SCE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxbp_1 (Q,Q_N,CLK,D,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxbp_2 (Q,Q_N,CLK,D,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxtp (Q,CLK,D,SCD,SCE); - - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxtp_1 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxtp_2 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdfxtp_4 (Q,CLK,D,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdlclkp (GCLK,SCE,GATE,CLK); - - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - wire m0 ; - wire m0n ; - wire clkn ; - wire SCE_GATE; - - - not not0 (m0n , m0 ); - not not1 (clkn , CLK ); - nor nor0 (SCE_GATE, GATE, SCE ); - sky130_fd_sc_hs__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn ); - and and0 (GCLK , m0n, CLK ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdlclkp_1 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdlclkp_2 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sdlclkp_4 (GCLK,SCE,GATE,CLK); - - - output GCLK; - input SCE ; - input GATE; - input CLK ; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sdlclkp base ( - .GCLK(GCLK), - .SCE(SCE), - .GATE(GATE), - .CLK(CLK) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxbp (Q,Q_N,CLK,D,DE,SCD,SCE); - - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - wire de_d ; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - not not0 (Q_N , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxbp_1 (Q,Q_N,CLK,D,DE,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sedfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxbp_2 (Q,Q_N,CLK,D,DE,SCD,SCE); - - - output Q ; - output Q_N; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sedfxbp base ( - .Q(Q), - .Q_N(Q_N), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxtp (Q,CLK,D,DE,SCD,SCE); - - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - wire buf_Q ; - wire mux_out; - wire de_d ; - - - sky130_fd_sc_hs__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE ); - sky130_fd_sc_hs__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE ); - sky130_fd_sc_hs__udp_dff$P dff0 (buf_Q , mux_out, CLK ); - buf buf0 (Q , buf_Q ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxtp_1 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxtp_2 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__sedfxtp_4 (Q,CLK,D,DE,SCD,SCE); - - - output Q ; - input CLK; - input D ; - input DE ; - input SCD; - input SCE; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__sedfxtp base ( - .Q(Q), - .CLK(CLK), - .D(D), - .DE(DE), - .SCD(SCD), - .SCE(SCE) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tap (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tap_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__tap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tap_2 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__tap base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvgnd2 (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvgnd2_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__tapvgnd2 base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvgnd (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvgnd_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__tapvgnd base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvpwrvgnd (); - - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__tapvpwrvgnd_1 (); - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__tapvpwrvgnd base (); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor2 (Y,A,B); - - - - output Y; - input A; - input B; - - - wire xnor0_out_Y; - - - xnor xnor0 (xnor0_out_Y, A, B ); - buf buf0 (Y , xnor0_out_Y ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor2_1 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor2_2 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor2_4 (Y,A,B); - - - output Y; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor2 base ( - .Y(Y), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire xnor0_out_X; - - - xnor xnor0 (xnor0_out_X, A, B, C ); - buf buf0 (X , xnor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xnor3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xnor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor2 (X,A,B); - - - - output X; - input A; - input B; - - - wire xor0_out_X; - - - xor xor0 (xor0_out_X, B, A ); - buf buf0 (X , xor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor2_1 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor2_2 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor2_4 (X,A,B); - - - output X; - input A; - input B; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor2 base ( - .X(X), - .A(A), - .B(B) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor3 (X,A,B,C); - - - - output X; - input A; - input B; - input C; - - - wire xor0_out_X; - - - xor xor0 (xor0_out_X, A, B, C ); - buf buf0 (X , xor0_out_X ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor3_1 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor3_2 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module sky130_fd_sc_hs__xor3_4 (X,A,B,C); - - - output X; - input A; - input B; - input C; - - - supply1 VPWR; - supply0 VGND; - supply1 VPB ; - supply0 VNB ; - - sky130_fd_sc_hs__xor3 base ( - .X(X), - .A(A), - .B(B), - .C(C) - ); - - -endmodule -(* noblackbox *) module mod_pullup (Y); -output Y; -assign Y = 1'b1; -endmodule -(* noblackbox *) module mod_pulldown (Y); -output Y; -assign Y = 1'b0; -endmodule diff --git a/flow/platforms/sky130ram/Makefile b/flow/platforms/sky130ram/Makefile index 2b94bbe31d..ab4ca6f876 100644 --- a/flow/platforms/sky130ram/Makefile +++ b/flow/platforms/sky130ram/Makefile @@ -66,7 +66,7 @@ endif # Verbosity OPTS += -v -SHELL ?= /bin/bash +SHELL ?= /usr/bin/env bash export SHELL export SHELLOPTS := pipefail diff --git a/flow/scripts/README.md b/flow/scripts/README.md new file mode 100644 index 0000000000..be55534412 --- /dev/null +++ b/flow/scripts/README.md @@ -0,0 +1,96 @@ +# Scripts + +Various scripts to support flow as well as utilities. + +## variables.mk + +ORFS defines tcl scripts and variables that can be used to implement a flow. Variables in EDA flows is an idiomatic domain feature: placement density, list of .lib, .lef files, etc. + +The variables are implemented using the `make` language, which ORFS makes no effort to hide. See examples below for usage. Beyond `make`, ORFS uses Python and bash to implement the variables. + +The choice of `make` to implement the ORFS variables is historical and technical. Technically, the `make` language implements features such as default values, forward references, conditional evaluation of variables, environment variables support and specifying variables on the command line. `make` itself is an uncomplicated dependency, even if depending on and sharing makefiles can be trickier. There is no simple and obviously better choice than `make` to support these features and the use-cases. + +ORFS avoids the [inversion of control](https://en.wikipedia.org/wiki/Inversion_of_control) trap where the user wants to be in control of the flow and also ORFS wants to be in the flow. To ORFS all build systems are first class citizens and the user can choose if it wants to let ORFS run the flow or if the user wants to be in control of the flow. The job of ORFS is to define and support an interface such that the user can pick a flow implementation that balances simplicity and required features for their project. + +`make`'s simplicity reduces the cognitive load when getting started with simple OpenROAD examples, but its simplicity eventually causes more problems than it solves when the flow gets complicated enough. MegaBoom illustrates a how a more complicated flow is better implemented in bazel-orfs. + +Some use-cases for `variables.mk`: + +- ORFS has a Makefile that implements a flow on top of the variables implemented in `variables.mk` and the ORFS scripts. This is used for CI and local regression testing. +- The has his own Makefile where ORFS is part of the user's flow where they can include and use only `variables.mk` or the ORFS `makefile`, while remaining in charge. +- bazel-orfs currently uses the ORFS `makefile` do- targets where no dependency checking is done to implement an ORFS flow. bazel-orfs may switch to using `variables.mk` to evaluate the variables and invoking OpenROAD directly. + +### Variables hello world + +It can be useful to run simple experiments to see what variables evaluate to: + + $ make --file=scripts/variables.mk PLATFORM=asap7 DESIGN_NAME=gcd print-OBJECTS_DIR + OBJECTS_DIR = ./objects/asap7/gcd/base + +### Creating and using a bash sourceable script to set up variables + +As an example of evaluating ORFS variables and invoking OpenROAD directly, first run synthesis on an existing design, set up variables, source the environment variables, then invoke floorplan directly: + + $ cd .../OpenROAD-flow-scripts/flow + $ make DESIGN_CONFIG=designs/asap7/gcd/config.mk synth + $ make DESIGN_CONFIG=designs/asap7/gcd/config.mk vars + $ . objects/asap7/gcd/base/vars.sh + $ openroad -exit scripts/floorplan.tcl + [deleted] + ========================================================================== + floorplan final report_design_area + -------------------------------------------------------------------------- + Design area 38 u^2 19% utilization. + $ + +### Creating a bash sourcable script to set up variables using `variables.mk` directly + +It is also possible to evaluate the variables without using the ORFS `Makefile`, but using `variables.mk` directly. In this example we copy the variables set in `designs/asap7/gcd/config.mk` onto the command line: + + $ make PLATFORM=asap7 DESIGN_NAME=gcd VERILOG_FILES=$(ls designs/src/gcd/*.v) SDC_FILE=designs/asap7/gcd/constraint.sdc "DIE_AREA=0 0 16.2 16.2" "CORE_AREA=1.08 1.08 15.12 15.12" PLACE_DENSITY=0.35 SKIP_LAST_GASP=1 --file=scripts/variables.mk vars + $ . objects/asap7/gcd/base/vars.sh + $ openroad -exit scripts/floorplan.tcl + [deleted] + ========================================================================== + floorplan final report_design_area + -------------------------------------------------------------------------- + Design area 38 u^2 19% utilization. + $ + +### flow.sh and synth.sh + +Utility scripts that can be used in combination with `variables.mk` to invoke synthesis and flow steps without going through the ORFS `Makefile`. + +## make run-yosys + +Sets up all the ORFS environment variables and launches Yosys. + +Useful to run a Yosys script or interactive mode on the synthesis result to extract information or debug synthesis results using Yosys commands. + +Used with the `YOSYS_RUN_ARGS` variable to pass arguments to Yosys. The default arguments is a "Hello world" script that lists all modules with the keep_hierarchy attribute set and writes a report of those modules. + + $ make DESIGN_CONFIG=designs/asap7/aes-block/config.mk synth run-yosys + $ cat reports/asap7/aes-block/base/keep.txt + + 2 modules: + aes_cipher_top aes_key_expand_128 + +## yosys_load.tcl + +Loads in 1_synth.v synthesis result from Yosys. This is useful in automation, such as generating reports from synthesis, but can also be used in interactive inspection. + +Example usage to examine results interactively: + + make DESIGN_CONFIG=designs/asap7/aes-block/config.mk synth run-yosys RUN_YOSYS_ARGS=-C + +Load synthesis result and list modules that were kept in hierarchical synthesis: + + [banner deleted] + % source $::env(SCRIPTS_DIR)/yosys_load.tcl + [yosys verbose output deleted] + % ls A:keep_hierarchy=1 + + 2 modules: + aes_cipher_top + aes_key_expand_128 + % diff --git a/flow/scripts/abc_retime.script b/flow/scripts/abc_retime.script new file mode 100644 index 0000000000..deb1c4758f --- /dev/null +++ b/flow/scripts/abc_retime.script @@ -0,0 +1,3 @@ +st +retime -v -o +map diff --git a/flow/scripts/abc_speed_gia_only.script b/flow/scripts/abc_speed_gia_only.script new file mode 100644 index 0000000000..e2d22a4f4b --- /dev/null +++ b/flow/scripts/abc_speed_gia_only.script @@ -0,0 +1,28 @@ +&st +&dch +&nf +&st +&syn2 +&if -g -K 6 +&synch2 +&nf +&st +&syn2 +&if -g -K 6 +&synch2 +&nf +&st +&syn2 +&if -g -K 6 +&synch2 +&nf +&st +&syn2 +&if -g -K 6 +&synch2 +&nf +&st +&syn2 +&if -g -K 6 +&synch2 +&nf diff --git a/flow/scripts/add_routing_blk.tcl b/flow/scripts/add_routing_blk.tcl index 7fc079f446..f4aadedbe7 100644 --- a/flow/scripts/add_routing_blk.tcl +++ b/flow/scripts/add_routing_blk.tcl @@ -22,19 +22,19 @@ foreach inst $allInsts { set loc_llx [lindex [$inst getLocation] 0] set loc_lly [lindex [$inst getLocation] 1] - if {[string match "*gf12*" $name]||[string match "IN12LP*" $name]} { + if { [string match "*gf12*" $name] || [string match "IN12LP*" $name] } { set w [$master getWidth] set h [$master getHeight] - set llx_Mx [expr $loc_llx - (128*$numTrack)] - set lly_Mx [expr $loc_lly - (128*$numTrack)] - set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] - set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] + set llx_Mx [expr $loc_llx - (128*$numTrack)] + set lly_Mx [expr $loc_lly - (128*$numTrack)] + set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] + set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] - set llx_Cx $loc_llx - set lly_Cx [expr $loc_lly - (160*$numTrack)] - set urx_Cx [expr $loc_llx + $w] - set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] + set llx_Cx $loc_llx + set lly_Cx [expr $loc_lly - (160*$numTrack)] + set urx_Cx [expr $loc_llx + $w] + set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] set obs_M2 [odb::dbObstruction_create $block $layer_M2 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] set obs_M3 [odb::dbObstruction_create $block $layer_M3 $llx_Mx $lly_Mx $urx_Mx $ury_Mx] @@ -44,6 +44,6 @@ foreach inst $allInsts { } } -if {$cnt != 0} { +if { $cnt != 0 } { puts "Created $cnt routing blockages over macros" } diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index 55f4a06207..0fe80f63ad 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -7,7 +7,7 @@ load_design 3_place.odb 3_place.sdc # so cts does not try to buffer the inverted clocks. repair_clock_inverters -proc save_progress {stage} { +proc save_progress { stage } { puts "Run 'make gui_$stage.odb' to load progress snapshot" write_db $::env(RESULTS_DIR)/$stage.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/$stage.sdc @@ -15,68 +15,56 @@ proc save_progress {stage} { # Run CTS set cts_args [list \ - -sink_clustering_enable \ - -balance_levels] + -sink_clustering_enable \ + -balance_levels \ + -repair_clock_nets] -append_env_var cts_args -distance_between_buffers CTS_BUF_DISTANCE 1 -append_env_var cts_args -sink_clustering_size CTS_CLUSTER_SIZE 1 -append_env_var cts_args -sink_clustering_max_diameter CTS_CLUSTER_DIAMETER 1 +append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1 +append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1 +append_env_var cts_args CTS_CLUSTER_DIAMETER -sink_clustering_max_diameter 1 +append_env_var cts_args CTS_BUF_LIST -buf_list 1 +append_env_var cts_args CTS_LIB_NAME -library 1 -if {[env_var_exists_and_non_empty CTS_ARGS]} { - set cts_args $::env(CTS_ARGS) -} - -log_cmd clock_tree_synthesis {*}$cts_args -if {[env_var_equals CTS_SNAPSHOTS 1]} { - save_progress 4_1_pre_repair_clock_nets +if { [env_var_exists_and_non_empty CTS_ARGS] } { + set cts_args $::env(CTS_ARGS) } -set_propagated_clock [all_clocks] - set_dont_use $::env(DONT_USE_CELLS) -utl::push_metrics_stage "cts__{}__pre_repair" - -estimate_parasitics -placement -if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts pre-repair" -} -utl::pop_metrics_stage - -repair_clock_nets +log_cmd clock_tree_synthesis {*}$cts_args -utl::push_metrics_stage "cts__{}__post_repair" +utl::push_metrics_stage "cts__{}__pre_repair_timing" estimate_parasitics -placement if { $::env(DETAILED_METRICS) } { - report_metrics 4 "cts post-repair" + report_metrics 4 "cts pre-repair-timing" } utl::pop_metrics_stage set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement estimate_parasitics -placement -if {[env_var_equals CTS_SNAPSHOTS 1]} { +if { [env_var_equals CTS_SNAPSHOTS 1] } { save_progress 4_1_pre_repair_hold_setup } -if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} { - if {$::env(EQUIVALENCE_CHECK)} { - write_eqy_verilog 4_before_rsz.v +if { ![env_var_equals SKIP_CTS_REPAIR_TIMING 1] } { + if { $::env(EQUIVALENCE_CHECK) } { + write_eqy_verilog 4_before_rsz.v } repair_timing_helper - if {$::env(EQUIVALENCE_CHECK)} { - run_equivalence_test + if { $::env(EQUIVALENCE_CHECK) } { + run_equivalence_test } - set result [catch {detailed_placement} msg] - if {$result != 0} { + set result [catch { detailed_placement } msg] + if { $result != 0 } { save_progress 4_1_error puts "Detailed placement failed in CTS: $msg" exit $result @@ -87,9 +75,7 @@ if {![env_var_equals SKIP_CTS_REPAIR_TIMING 1]} { report_metrics 4 "cts final" -if { [env_var_exists_and_non_empty POST_CTS_TCL] } { - source $::env(POST_CTS_TCL) -} +source_env_var_if_exists POST_CTS_TCL write_db $::env(RESULTS_DIR)/4_1_cts.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/4_cts.sdc diff --git a/flow/scripts/deleteNonClkNets.tcl b/flow/scripts/deleteNonClkNets.tcl index 0a6e80bb3c..bad10a4772 100644 --- a/flow/scripts/deleteNonClkNets.tcl +++ b/flow/scripts/deleteNonClkNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -13,24 +13,26 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl read_def $::env(RESULTS_DIR)/6_final.def set block [[[ord::get_db] getChip] getBlock] -set nets [$block getNets] +set nets [$block getNets] set insts [$block getInsts] # Delete all non-clock nets foreach net $nets { set sigType [$net getSigType] set wire [$net getWire] - if {"$sigType" eq "SIGNAL" && "$wire" ne "NULL"} { + if { "$sigType" eq "SIGNAL" && "$wire" ne "NULL" } { odb::dbWire_destroy $wire - } elseif {"$sigType" eq "POWER" || - "$sigType" eq "GROUND"} { + } elseif { + "$sigType" eq "POWER" || + "$sigType" eq "GROUND" + } { $net destroySWires } } # Delete fill cells to clean up screenshot foreach inst $insts { - if {"[[$inst getMaster] getType]" eq "CORE_SPACER"} { + if { "[[$inst getMaster] getType]" eq "CORE_SPACER" } { odb::dbInst_destroy $inst } } diff --git a/flow/scripts/deletePowerNets.tcl b/flow/scripts/deletePowerNets.tcl index 74120d50b3..e1e6def4e1 100644 --- a/flow/scripts/deletePowerNets.tcl +++ b/flow/scripts/deletePowerNets.tcl @@ -1,6 +1,6 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -12,7 +12,7 @@ source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read def and sdc read_def $::env(RESULTS_DIR)/6_final.def -proc deleteNetByName {name} { +proc deleteNetByName { name } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/deleteRoutingObstructions.tcl b/flow/scripts/deleteRoutingObstructions.tcl index 5f78de4e06..2743009338 100644 --- a/flow/scripts/deleteRoutingObstructions.tcl +++ b/flow/scripts/deleteRoutingObstructions.tcl @@ -1,4 +1,4 @@ -proc deleteRoutingObstructions {} { +proc deleteRoutingObstructions { } { set db [ord::get_db] set chip [$db getChip] set block [$chip getBlock] diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl index 3709a447d3..0c4e10585e 100644 --- a/flow/scripts/density_fill.tcl +++ b/flow/scripts/density_fill.tcl @@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables final load_design 5_route.odb 5_route.sdc -if {[env_var_equals USE_FILL 1]} { +if { [env_var_equals USE_FILL 1] } { set_propagated_clock [all_clocks] density_fill -rules $::env(FILL_CONFIG) # The .v file is just for debugging purposes, not a result of diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl index a92a5ae800..c093b162fe 100644 --- a/flow/scripts/detail_place.tcl +++ b/flow/scripts/detail_place.tcl @@ -5,19 +5,19 @@ load_design 3_4_place_resized.odb 2_floorplan.sdc source $::env(PLATFORM_DIR)/setRC.tcl -proc do_dpl {} { +proc do_dpl { } { # Only for use with hybrid rows - if {[env_var_equals BALANCE_ROWS 1]} { + if { [env_var_equals BALANCE_ROWS 1] } { balance_row_usage } - + set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) detailed_placement - - if {[env_var_equals ENABLE_DPO 1]} { - if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} { + + if { [env_var_equals ENABLE_DPO 1] } { + if { [env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT] } { improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT) } else { improve_placement @@ -26,12 +26,12 @@ proc do_dpl {} { optimize_mirroring utl::info FLW 12 "Placement violations [check_placement -verbose]." - + estimate_parasitics -placement } -set result [catch {do_dpl} errMsg] -if {$result != 0} { +set result [catch { do_dpl } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_5_place_dp-failed.odb error $errMsg } diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl index 7aeafcdb31..ba0258a7ce 100644 --- a/flow/scripts/detail_route.tcl +++ b/flow/scripts/detail_route.tcl @@ -1,10 +1,16 @@ utl::set_metrics_stage "detailedroute__{}" source $::env(SCRIPTS_DIR)/load.tcl load_design 5_1_grt.odb 5_1_grt.sdc -if {![grt::have_routes]} { +if { ![grt::have_routes] } { error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \ in DRC viewer to view congestion" } + +if { [env_var_equals SKIP_DETAILED_ROUTE 1] } { + write_db $::env(RESULTS_DIR)/5_2_route.odb + exit +} + erase_non_stage_variables route set_propagated_clock [all_clocks] @@ -12,8 +18,6 @@ set additional_args "" append_env_var additional_args dbProcessNode -db_process_node 1 append_env_var additional_args OR_SEED -or_seed 1 append_env_var additional_args OR_K -or_k 1 -append_env_var additional_args MIN_ROUTING_LAYER -bottom_routing_layer 1 -append_env_var additional_args MAX_ROUTING_LAYER -top_routing_layer 1 append_env_var additional_args VIA_IN_PIN_MIN_LAYER -via_in_pin_bottom_layer 1 append_env_var additional_args VIA_IN_PIN_MAX_LAYER -via_in_pin_top_layer 1 append_env_var additional_args DISABLE_VIA_GEN -disable_via_gen 0 @@ -36,8 +40,10 @@ append additional_args " -verbose 1" # having to go spelunking in Tcl or modify configuration scripts, while # not having to wait too long or generating large useless reports. -set arguments [expr {[env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : \ - [concat $additional_args {-drc_report_iter_step 5}]}] +set arguments [expr { + [env_var_exists_and_non_empty DETAILED_ROUTE_ARGS] ? $::env(DETAILED_ROUTE_ARGS) : + [concat $additional_args {-drc_report_iter_step 5}] +}] set all_args [concat [list \ -output_drc $::env(REPORTS_DIR)/5_route_drc.rpt \ @@ -46,27 +52,25 @@ set all_args [concat [list \ log_cmd detailed_route {*}$all_args -fast_route - -if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} { +if { ![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1] && $::env(MAX_REPAIR_ANTENNAS_ITER_DRT) } { set repair_antennas_iters 1 - if {[repair_antennas]} { + if { [repair_antennas] } { detailed_route {*}$all_args } - while {[check_antennas] && $repair_antennas_iters < 5} { + while { [check_antennas] && $repair_antennas_iters < $::env(MAX_REPAIR_ANTENNAS_ITER_DRT) } { repair_antennas detailed_route {*}$all_args incr repair_antennas_iters } +} else { + utl::metric_int "antenna_diodes_count" -1 } -if { [env_var_exists_and_non_empty POST_DETAIL_ROUTE_TCL] } { - source $::env(POST_DETAIL_ROUTE_TCL) -} +source_env_var_if_exists POST_DETAIL_ROUTE_TCL check_antennas -report_file $env(REPORTS_DIR)/drt_antennas.log -if {![design_is_routed]} { +if { ![design_is_routed] } { error "Design has unrouted nets." } diff --git a/flow/scripts/escape.sh b/flow/scripts/escape.sh index eeb1c803b9..7b9e4260de 100755 --- a/flow/scripts/escape.sh +++ b/flow/scripts/escape.sh @@ -1,2 +1,2 @@ -#!/bin/bash +#!/usr/bin/env bash sed -e 's/ /\\ /g' -e 's/(/\\(/g' -e 's/|/\\|/g' -e 's/)/\\)/g' diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl index 293f69ac83..ea23e5b24f 100644 --- a/flow/scripts/fillcell.tcl +++ b/flow/scripts/fillcell.tcl @@ -1,6 +1,6 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables route -if {[env_var_exists_and_non_empty FILL_CELLS]} { +if { [env_var_exists_and_non_empty FILL_CELLS] } { load_design 5_2_route.odb 5_1_grt.sdc set_propagated_clock [all_clocks] diff --git a/flow/scripts/final_report.tcl b/flow/scripts/final_report.tcl index 6900d915dd..5b0b33e381 100644 --- a/flow/scripts/final_report.tcl +++ b/flow/scripts/final_report.tcl @@ -18,14 +18,10 @@ write_def $::env(RESULTS_DIR)/6_final.def write_verilog $::env(RESULTS_DIR)/6_final.v # Run extraction and STA -if {[env_var_exists_and_non_empty RCX_RULES]} { - - # Set RC corner for RCX - # Set in config.mk - if {[env_var_exists_and_non_empty RCX_RC_CORNER]} { - set rc_corner $::env(RCX_RC_CORNER) - } - +if { + [env_var_exists_and_non_empty RCX_RULES] + && [env_var_equals SKIP_DETAILED_ROUTE 0] +} { # RCX section define_process_corner -ext_model_index 0 X extract_parasitics -ext_model_file $::env(RCX_RULES) @@ -38,25 +34,24 @@ if {[env_var_exists_and_non_empty RCX_RULES]} { read_spef $::env(RESULTS_DIR)/6_final.spef # Static IR drop analysis - if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { - dict for {pwrNetName pwrNetVoltage} {*}$::env(PWR_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} - analyze_power_grid -net ${pwrNetName} \ - -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt + if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { + dict for {pwrNetName pwrNetVoltage} $::env(PWR_NETS_VOLTAGES) { + set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage} + analyze_power_grid -net ${pwrNetName} \ + -error_file $::env(REPORTS_DIR)/${pwrNetName}.rpt } } else { puts "IR drop analysis for power nets is skipped because PWR_NETS_VOLTAGES is undefined" } - if {[env_var_exists_and_non_empty GND_NETS_VOLTAGES]} { - dict for {gndNetName gndNetVoltage} {*}$::env(GND_NETS_VOLTAGES) { - set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} - analyze_power_grid -net ${gndNetName} \ - -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt + if { [env_var_exists_and_non_empty GND_NETS_VOLTAGES] } { + dict for {gndNetName gndNetVoltage} $::env(GND_NETS_VOLTAGES) { + set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage} + analyze_power_grid -net ${gndNetName} \ + -error_file $::env(REPORTS_DIR)/${gndNetName}.rpt } } else { puts "IR drop analysis for ground nets is skipped because GND_NETS_VOLTAGES is undefined" } - } else { puts "OpenRCX is not enabled for this platform." } @@ -66,6 +61,6 @@ report_cell_usage report_metrics 6 "finish" # Save a final image if openroad is compiled with the gui -if {[expr [llength [info procs save_image]] > 0]} { - gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false +if { [ord::openroad_gui_compiled] } { + gui::show "source $::env(SCRIPTS_DIR)/save_images.tcl" false } diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl index d2b26dbefe..925df920aa 100644 --- a/flow/scripts/floorplan.tcl +++ b/flow/scripts/floorplan.tcl @@ -3,14 +3,14 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan load_design 1_synth.v 1_synth.sdc -proc report_unused_masters {} { +proc report_unused_masters { } { set db [ord::get_db] set libs [$db getLibs] set masters "" foreach lib $libs { foreach master [$lib getMasters] { # filter out non-block masters, or you can remove this conditional to detect any unused master - if {[$master getType] == "BLOCK"} { + if { [$master getType] == "BLOCK" } { lappend masters $master } } @@ -45,153 +45,94 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1 set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF] set use_footprint [env_var_exists_and_non_empty FOOTPRINT] -set use_die_and_core_area [expr {[env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA]}] +set use_die_and_core_area \ + [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }] set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION] -set methods_defined [expr {$use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization}] -if {$methods_defined > 1} { - puts "ERROR: Floorplan initialization methods are mutually exclusive, pick one." - exit 1 +set methods_defined \ + [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }] +if { $methods_defined > 1 } { + puts "Error: Floorplan initialization methods are mutually exclusive, pick one." + exit 1 } -if {$use_floorplan_def} { - # Initialize floorplan by reading in floorplan DEF - puts "Read in Floorplan DEF to initialize floorplan: $env(FLOORPLAN_DEF)" - read_def -floorplan_initialize $env(FLOORPLAN_DEF) -} elseif {$use_footprint} { - # Initialize floorplan using ICeWall FOOTPRINT - ICeWall load_footprint $env(FOOTPRINT) - - initialize_floorplan \ - -die_area [ICeWall get_die_area] \ - -core_area [ICeWall get_core_area] \ - -site $::env(PLACE_SITE) - - ICeWall init_footprint $env(SIG_MAP_FILE) -} elseif {$use_die_and_core_area} { - initialize_floorplan -die_area $::env(DIE_AREA) \ - -core_area $::env(CORE_AREA) \ - -site $::env(PLACE_SITE) \ - {*}$additional_args -} elseif {$use_core_utilization} { - set aspect_ratio 1.0 - if {[env_var_exists_and_non_empty "CORE_ASPECT_RATIO"]} { - set aspect_ratio $::env(CORE_ASPECT_RATIO) - } - set core_margin 1.0 - if {[env_var_exists_and_non_empty "CORE_MARGIN"]} { - set core_margin $::env(CORE_MARGIN) - } - initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ - -aspect_ratio $aspect_ratio \ - -core_space $core_margin \ - -site $::env(PLACE_SITE) \ - {*}$additional_args +if { $use_floorplan_def } { + # Initialize floorplan by reading in floorplan DEF + log_cmd read_def -floorplan_initialize $env(FLOORPLAN_DEF) +} elseif { $use_footprint } { + # Initialize floorplan using ICeWall FOOTPRINT + ICeWall load_footprint $env(FOOTPRINT) + + initialize_floorplan \ + -die_area [ICeWall get_die_area] \ + -core_area [ICeWall get_core_area] \ + -site $::env(PLACE_SITE) + + ICeWall init_footprint $env(SIG_MAP_FILE) +} elseif { $use_die_and_core_area } { + initialize_floorplan -die_area $::env(DIE_AREA) \ + -core_area $::env(CORE_AREA) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args +} elseif { $use_core_utilization } { + initialize_floorplan -utilization $::env(CORE_UTILIZATION) \ + -aspect_ratio $::env(CORE_ASPECT_RATIO) \ + -core_space $::env(CORE_MARGIN) \ + -site $::env(PLACE_SITE) \ + {*}$additional_args } else { - puts "ERROR: No floorplan initialization method specified" - exit 1 + puts "Error: No floorplan initialization method specified" + exit 1 } if { [env_var_exists_and_non_empty MAKE_TRACKS] } { - source $::env(MAKE_TRACKS) -} elseif {[file exists $::env(PLATFORM_DIR)/make_tracks.tcl]} { - source $::env(PLATFORM_DIR)/make_tracks.tcl + log_cmd source $::env(MAKE_TRACKS) +} elseif { [file exists $::env(PLATFORM_DIR)/make_tracks.tcl] } { + log_cmd source $::env(PLATFORM_DIR)/make_tracks.tcl } else { make_tracks } -if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} { - source $::env(FOOTPRINT_TCL) +source_env_var_if_exists FOOTPRINT_TCL + +# This needs to come before any call to remove_buffers. You could have one +# tie driving multiple buffers that drive multiple outputs. +# Repair tie lo fanout +puts "Repair tie lo fanout..." +set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0] +set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] +set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1] +repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin + +# Repair tie hi fanout +puts "Repair tie hi fanout..." +set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0] +set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] +set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1] +repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin + +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + estimate_parasitics -placement + replace_arith_modules } if { [env_var_equals REMOVE_ABC_BUFFERS 1] } { # remove buffers inserted by yosys/abc remove_buffers } else { - repair_timing_helper 0 -} - -##### Restructure for timing ######### -if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } { - repair_design_helper - repair_timing_helper - # pre restructure area/timing report (ideal clocks) - puts "Post synth-opt area" - report_design_area - report_worst_slack -min -digits 3 - puts "Post synth-opt wns" - report_worst_slack -max -digits 3 - puts "Post synth-opt tns" - report_tns -digits 3 - - write_verilog $::env(RESULTS_DIR)/2_pre_abc_timing.v - - restructure -target timing -liberty_file $::env(DONT_USE_SC_LIB) \ - -work_dir $::env(RESULTS_DIR) - - write_verilog $::env(RESULTS_DIR)/2_post_abc_timing.v - - # post restructure area/timing report (ideal clocks) - remove_buffers - repair_design_helper - repair_timing_helper - - puts "Post restructure-opt wns" - report_worst_slack -max -digits 3 - puts "Post restructure-opt tns" - report_tns -digits 3 - - # remove buffers inserted by optimization - remove_buffers + # Skip clone & split + set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer" + set ::env(SKIP_LAST_GASP) 1 + repair_timing_helper -setup } - puts "Default units for flow" report_units report_units_metric report_metrics 2 "floorplan final" false false -if { [env_var_equals RESYNTH_AREA_RECOVER 1] } { - - utl::push_metrics_stage "floorplan__{}__pre_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances before restructure is $num_instances" - puts "Design Area before restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage - - write_verilog $::env(RESULTS_DIR)/2_pre_abc.v - - set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] - set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] - set tielo_port $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] - - set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] - set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] - set tiehi_port $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] - - restructure -liberty_file $::env(DONT_USE_SC_LIB) -target "area" \ - -tiehi_port $tiehi_port \ - -tielo_port $tielo_port \ - -work_dir $::env(RESULTS_DIR) - - # remove buffers inserted by abc - remove_buffers - - write_verilog $::env(RESULTS_DIR)/2_post_abc.v - utl::push_metrics_stage "floorplan__{}__post_restruct" - set num_instances [llength [get_cells -hier *]] - puts "number instances after restructure is $num_instances" - puts "Design Area after restructure" - report_design_area - report_design_area_metrics - utl::pop_metrics_stage -} - -if { [env_var_exists_and_non_empty POST_FLOORPLAN_TCL] } { - source $::env(POST_FLOORPLAN_TCL) -} +source_env_var_if_exists POST_FLOORPLAN_TCL +source_env_var_if_exists IO_CONSTRAINTS write_db $::env(RESULTS_DIR)/2_1_floorplan.odb write_sdc -no_timestamp $::env(RESULTS_DIR)/2_1_floorplan.sdc diff --git a/flow/scripts/flow.sh b/flow/scripts/flow.sh new file mode 100755 index 0000000000..96ef5615e0 --- /dev/null +++ b/flow/scripts/flow.sh @@ -0,0 +1,11 @@ +#!/usr/bin/env bash +set -u -eo pipefail +mkdir -p $RESULTS_DIR $LOG_DIR $REPORTS_DIR $OBJECTS_DIR +echo Running $2.tcl, stage $1 +(trap 'mv $LOG_DIR/$1.tmp.log $LOG_DIR/$1.log' EXIT; \ + $OPENROAD_EXE $OPENROAD_ARGS -exit $SCRIPTS_DIR/noop.tcl 2>&1 >$LOG_DIR/$1.tmp.log; \ + eval "$TIME_CMD $OPENROAD_CMD -no_splash $SCRIPTS_DIR/$2.tcl -metrics $LOG_DIR/$1.json" 2>&1 | \ + tee -a $(realpath $LOG_DIR/$1.tmp.log)) +# Log the hash for this step. The summary "make elapsed" in "make finish", +# will not have all the .odb files for the bazel-orfs use-case. +$PYTHON_EXE $UTILS_DIR/genElapsedTime.py --match $1 -d $LOG_DIR | tee -a $(realpath $LOG_DIR/$1.log) diff --git a/flow/scripts/generate-variables-docs.py b/flow/scripts/generate-variables-docs.py index 3c10c1be24..75a38d6f4f 100755 --- a/flow/scripts/generate-variables-docs.py +++ b/flow/scripts/generate-variables-docs.py @@ -17,17 +17,17 @@ preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"] stages = {stage for value in data.values() for stage in value.get("stages", [])} # convert set of stages to stages in a list in the preferred order, but -# list all stages -stages = [stage for stage in preferred_order if stage in stages] + [ - stage for stage in stages if stage not in preferred_order -] +# list all stages and sort the rest for a stable order +stages = [stage for stage in preferred_order if stage in stages] + sorted( + [stage for stage in stages if stage not in preferred_order] +) markdown_table = "" markdown_table += "## Variables in alphabetic order\n\n" table_header = """ -| Variable | Description | Default | Deprecated | -| --- | --- | --- | --- | +| Variable | Description | Default | +| --- | --- | --- | """ table_rows = "" for key in sorted(data): @@ -35,9 +35,9 @@ description = value.get("description", "").replace("\n", " ").strip() table_rows += ( f'| {key}' + + f'{" (deprecated)" if value.get("deprecated", 0) == 1 else ""}' + f"| {description}" + f'| {value.get("default", "")}' - + f'| {"yes" if value.get("deprecated", 0) == 1 else ""}' + "|\n" ) diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl index 7593816383..87599290db 100644 --- a/flow/scripts/generate_abstract.tcl +++ b/flow/scripts/generate_abstract.tcl @@ -1,31 +1,40 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables generate_abstract -set stem [expr {[env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final"}] +set stem [expr { + [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? + $::env(ABSTRACT_SOURCE) : + "6_final" +}] set result [find_sdc_file $stem.odb] set design_stage [lindex $result 0] set sdc_file [lindex $result 1] -load_design $stem.odb [file tail $sdc_file] +log_cmd load_design $stem.odb [file tail $sdc_file] -if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} { - read_spef $::env(RESULTS_DIR)/$stem.spef -} elseif {$design_stage >= 3} { - puts "Estimating parasitics" - estimate_parasitics -placement +if { $design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef] } { + log_cmd read_spef $::env(RESULTS_DIR)/$stem.spef +} elseif { $design_stage >= 3 } { + log_cmd estimate_parasitics -placement } -if {$design_stage >= 4} { +if { $design_stage >= 4 } { set_propagated_clock [all_clocks] } # write_timing_model includes the source latency in the model set_clock_latency -source 0 [all_clocks] puts "Generating abstract views" -write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib -write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef +if { [env_var_exists_and_non_empty CORNERS] } { + foreach corner $::env(CORNERS) { + log_cmd write_timing_model -corner $corner $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_$corner.lib + } +} else { + log_cmd write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME)_typ.lib +} +log_cmd write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef -if {[env_var_exists_and_non_empty CDL_FILES]} { +if { [env_var_exists_and_non_empty CDL_FILES] } { cdl read_masters $::env(CDL_FILES) cdl out $::env(RESULTS_DIR)/$stem.cdl } diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl index 34ca29e50b..d283e5a2a5 100644 --- a/flow/scripts/global_place.tcl +++ b/flow/scripts/global_place.tcl @@ -5,44 +5,65 @@ load_design 3_2_place_iop.odb 2_floorplan.sdc set_dont_use $::env(DONT_USE_CELLS) -fast_route +remove_buffers + +# Do not buffer chip-level designs +# by default, IO ports will be buffered +# to not buffer IO ports, set environment variable +# DONT_BUFFER_PORT = 1 +if { ![env_var_exists_and_non_empty FOOTPRINT] } { + if { ![env_var_equals DONT_BUFFER_PORTS 1] } { + puts "Perform port buffering..." + buffer_ports + } +} + +if { [env_var_exists_and_non_empty FASTROUTE_TCL] } { + log_cmd source $::env(FASTROUTE_TCL) +} else { + log_cmd \ + set_global_routing_layer_adjustment \ + $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) + log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) +} set global_placement_args {} # Parameters for routability mode in global placement -if {$::env(GPL_ROUTABILITY_DRIVEN)} { - lappend global_placement_args {-routability_driven} -} +append_env_var global_placement_args GPL_ROUTABILITY_DRIVEN -routability_driven 0 # Parameters for timing driven mode in global placement -if {$::env(GPL_TIMING_DRIVEN)} { +if { $::env(GPL_TIMING_DRIVEN) } { lappend global_placement_args {-timing_driven} + if { [info exists ::env(GPL_KEEP_OVERFLOW)] } { + lappend global_placement_args -keep_resize_below_overflow $::env(GPL_KEEP_OVERFLOW) + } } -proc do_placement {global_placement_args} { +proc do_placement { global_placement_args } { set all_args [concat [list -density [place_density_with_lb_addon] \ -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \ $global_placement_args] - lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS) + lappend all_args {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] log_cmd global_placement {*}$all_args } -set result [catch {do_placement $global_placement_args} errMsg] -if {$result != 0} { +set result [catch { do_placement $global_placement_args } errMsg] +if { $result != 0 } { write_db $::env(RESULTS_DIR)/3_3_place_gp-failed.odb error $errMsg } estimate_parasitics -placement -if {[env_var_equals CLUSTER_FLOPS 1]} { +if { [env_var_equals CLUSTER_FLOPS 1] } { cluster_flops estimate_parasitics -placement } -report_metrics 5 "global place" false false +report_metrics 3 "global place" false false write_db $::env(RESULTS_DIR)/3_3_place_gp.odb diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl index fa9a53d537..ff05f363f6 100644 --- a/flow/scripts/global_place_skip_io.tcl +++ b/flow/scripts/global_place_skip_io.tcl @@ -6,9 +6,9 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } { puts "FLOORPLAN_DEF is set. Skipping global placement without IOs" } else { log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - {*}$::env(GLOBAL_PLACEMENT_ARGS) + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS] } write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 16639a3c93..165a90361b 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -5,14 +5,10 @@ load_design 4_cts.odb 4_cts.sdc # This proc is here to allow us to use 'return' to return early from this # file which is sourced -proc global_route_helper {} { - if {[env_var_exists_and_non_empty PRE_GLOBAL_ROUTE]} { - source $::env(PRE_GLOBAL_ROUTE) - } - - fast_route +proc global_route_helper { } { + source_env_var_if_exists PRE_GLOBAL_ROUTE_TCL - proc do_global_route {} { + proc do_global_route { } { set all_args [concat [list \ -congestion_report_file $::global_route_congestion_report] \ $::env(GLOBAL_ROUTE_ARGS)] @@ -20,12 +16,12 @@ proc global_route_helper {} { log_cmd global_route {*}$all_args } - set result [catch {do_global_route} errMsg] + pin_access - if {$result != 0} { - if {[expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \ - ![file exists $::global_route_congestion_report] || \ - [file size $::global_route_congestion_report] == 0]} { + set result [catch { do_global_route } errMsg] + + if { $result != 0 } { + if { !$::env(GENERATE_ARTIFACTS_ON_FAILURE) } { write_db $::env(RESULTS_DIR)/5_1_grt-failed.odb error $errMsg } @@ -35,13 +31,13 @@ proc global_route_helper {} { } set_placement_padding -global \ - -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ - -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) + -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ + -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) set_propagated_clock [all_clocks] estimate_parasitics -global_routing - if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { + if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { set_dont_use $::env(DONT_USE_CELLS) } @@ -58,10 +54,11 @@ proc global_route_helper {} { # Running DPL to fix overlapped instances # Run to get modified net by DPL - global_route -start_incremental - detailed_placement + log_cmd global_route -start_incremental + log_cmd detailed_placement # Route only the modified net by DPL - global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt # Repair timing using global route parasitics puts "Repair setup and hold violations..." @@ -75,20 +72,23 @@ proc global_route_helper {} { # Running DPL to fix overlapped instances # Run to get modified net by DPL - global_route -start_incremental - detailed_placement + log_cmd global_route -start_incremental + log_cmd detailed_placement # Route only the modified net by DPL - global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt } - global_route -start_incremental - recover_power + + log_cmd global_route -start_incremental + recover_power_helper # Route the modified nets by rsz journal restore - global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt + log_cmd global_route -end_incremental \ + -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt - if {![env_var_equals SKIP_ANTENNA_REPAIR 1]} { + if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] && $::env(MAX_REPAIR_ANTENNAS_ITER_GRT) } { puts "Repair antennas..." - repair_antennas -iterations 5 + repair_antennas -iterations $::env(MAX_REPAIR_ANTENNAS_ITER_GRT) check_placement -verbose check_antennas -report_file $::env(REPORTS_DIR)/grt_antennas.log } diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl index 05b2ac261a..e4f61e0983 100644 --- a/flow/scripts/io_placement.tcl +++ b/flow/scripts/io_placement.tcl @@ -1,10 +1,18 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables place -if {![env_var_equals IS_CHIP 1]} { +if { + ![env_var_exists_and_non_empty FLOORPLAN_DEF] && + ![env_var_exists_and_non_empty FOOTPRINT] && + ![env_var_exists_and_non_empty FOOTPRINT_TCL] +} { load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc - source $::env(SCRIPTS_DIR)/io_placement_util.tcl + log_cmd place_pins \ + -hor_layers $::env(IO_PLACER_H) \ + -ver_layers $::env(IO_PLACER_V) \ + {*}[env_var_or_empty PLACE_PINS_ARGS] write_db $::env(RESULTS_DIR)/3_2_place_iop.odb + write_pin_placement $::env(RESULTS_DIR)/3_2_place_iop.tcl } else { log_cmd exec cp $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb $::env(RESULTS_DIR)/3_2_place_iop.odb } diff --git a/flow/scripts/io_placement_random.tcl b/flow/scripts/io_placement_random.tcl deleted file mode 100644 index 7535485af1..0000000000 --- a/flow/scripts/io_placement_random.tcl +++ /dev/null @@ -1,11 +0,0 @@ -source $::env(SCRIPTS_DIR)/load.tcl -erase_non_stage_variables floorplan - -if {![env_var_equals IS_CHIP 1]} { - load_design 2_1_floorplan.odb 2_1_floorplan.sdc - lappend ::env(PLACE_PINS_ARGS) -random - source $::env(SCRIPTS_DIR)/io_placement_util.tcl - write_db $::env(RESULTS_DIR)/2_2_floorplan_io.odb -} else { - log_cmd exec cp $::env(RESULTS_DIR)/2_1_floorplan.odb $::env(RESULTS_DIR)/2_2_floorplan_io.odb -} diff --git a/flow/scripts/io_placement_util.tcl b/flow/scripts/io_placement_util.tcl deleted file mode 100644 index 60be7bd484..0000000000 --- a/flow/scripts/io_placement_util.tcl +++ /dev/null @@ -1,11 +0,0 @@ -if {[env_var_exists_and_non_empty FLOORPLAN_DEF]} { - puts "Skipping IO placement as DEF file was used to initialize floorplan." -} else { - if {[env_var_exists_and_non_empty IO_CONSTRAINTS]} { - source $::env(IO_CONSTRAINTS) - } - set args [list -hor_layers $::env(IO_PLACER_H) \ - -ver_layers $::env(IO_PLACER_V) \ - {*}$::env(PLACE_PINS_ARGS)] - log_cmd place_pins {*}$args -} diff --git a/flow/scripts/klayout.tcl b/flow/scripts/klayout.tcl index 56cc08ad6b..811902d6c7 100644 --- a/flow/scripts/klayout.tcl +++ b/flow/scripts/klayout.tcl @@ -1,20 +1,20 @@ -if {[env_var_exists_and_non_empty FILL_CONFIG]} { - set fill_config $::env(FILL_CONFIG) +if { [env_var_exists_and_non_empty FILL_CONFIG] } { + set fill_config $::env(FILL_CONFIG) } else { - set fill_config "" + set fill_config "" } -if {[env_var_exists_and_non_empty SEAL_GDS]} { - set seal_gds $::env(SEAL_GDS) +if { [env_var_exists_and_non_empty SEAL_GDS] } { + set seal_gds $::env(SEAL_GDS) } else { - set seal_gds "" + set seal_gds "" } exec klayout -zz -rd design_name=$::env(DESIGN_NAME) \ - -rd in_def=$::env(RESULTS_DIR)/6_final.def \ - -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ - -rd config_file=$fill_config \ - -rd seal_file=$seal_gds \ - -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ - -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ - -rm $::env(UTILS_DIR)/def2stream.py + -rd in_def=$::env(RESULTS_DIR)/6_final.def \ + -rd in_files="$::env(GDSOAS_FILES) $::env(WRAPPED_GDSOAS)" \ + -rd config_file=$fill_config \ + -rd seal_file=$seal_gds \ + -rd out_file=$::env(RESULTS_DIR)/6_final.$::env(STREAM_SYSTEM_EXT) \ + -rd tech_file=$::env(OBJECTS_DIR)/klayout.lyt \ + -rm $::env(UTILS_DIR)/def2stream.py diff --git a/flow/scripts/klayout/README.md b/flow/scripts/klayout/README.md new file mode 100644 index 0000000000..cb01de3a0b --- /dev/null +++ b/flow/scripts/klayout/README.md @@ -0,0 +1,60 @@ +# Collection of Ruby scripts to generate KLayout files required by ORFS + +This directory contains a set of Ruby scripts that will generate the following KLayout files: + +- Technology File +- Layer Properties File + +using the following files as input: + +- Cadence Virtuoso SKILL tech file +- Cadence Virtuoso layer mapping file +- Technology LEF file + +## Setup +Copy the following files into ~/.klayout/ruby + +- GenericLayerNameMapper.rb +- KLayoutLayerMapGenerator.rb +- KLayoutLayerPropertiesFileGenerator.rb +- LEFViaData.rb +- LEFNamedObject.rb +- LEFVia.rb +- LEFLayer.rb + +Also make sure that you have the import_tf.rb file from [tf_import](https://github.com/klayoutmatthias/tf_import) copied there as well. If you follow the instructions at [Guide to Integrate a New Platform into the OpenROAD Flow](https://openroad-flow-scripts.readthedocs.io/en/latest/contrib/PlatformBringUp.html#klayout-properties-file), it will be installed in ~/.klayout/salt/tf_import. Just copy it over to ~/.klayout/ruby, so that the scripts can find it. + +## Usage +Then gen_klayout_files.sh is the main driver to generate the files. Its usage is: + +``` +Usage: gen_klayout_files.sh -v -l + -t -n + -d -p + -o [-m layer_name_mapper_ruby] [-h] +``` + +where + +- virtuoso_tech_file: Cadence Virtuoso SKILL tech file +- virtuoso_layer_map: Cadence Virtuoso layer mapping file (maps Cadence + layer/purpose pairs to GDS II layer/datatype) +- tech_lef: Cadence technology LEF with layer and via definitions +- tech_name: Name to put in KLayout technology file +- tech_description: Description to put in KLayout technology file +- klayout_lyp: KLayout layer properties file (typically ending in .lyp) - + generated from Virtuoso tech file +- klayout_lyt: Klayout technology file (typically ending in .lyt) +- layer_name_mapper_ruby: Name of Ruby file containing custom layer name mapper + Uses GenericLayerNameMapper.rb by default + +For example: + +``` +gen_klayout_files.sh -v process.tf -l process.layermap -d adv_process.lef \ + -n adv_process -d "Really advanced process" -p output.lyp \ + -o output.lyt -m AdvProcessLayerNameMapper.rb +``` + + + diff --git a/flow/scripts/klayout/src/GenericLayerNameMapper.rb b/flow/scripts/klayout/src/GenericLayerNameMapper.rb new file mode 100755 index 0000000000..3d0e762b85 --- /dev/null +++ b/flow/scripts/klayout/src/GenericLayerNameMapper.rb @@ -0,0 +1,61 @@ +#!/usr/bin/env ruby +# +# Generic LayerNameMapper +# + +require 'optparse' + +# +# Class to map layer names (default) +# +class LayerNameMapper + # + # Initializer + # + def initialize() + end + + # + # Maps layers to the desired name in the layer map + # + def map_layer_name(design_manual_layer_name, cds_layer_name, cds_purpose_name) + if design_manual_layer_name && design_manual_layer_name.length > 0 + return design_manual_layer_name + end + return cds_layer_name + end + + # + # Standalone main driver + # + def LayerNameMapper.main() + options = {} + OptionParser.new do |opts| + opts.banner = "Usage: LayerNameMapper.rb -d design_manual_layer_name -l cds_layer_name -p cds_purpose_name" + opts.on("-dDESIGN_MANUAL_LAYER_NAME", "--design_manual_layer_name=DESIGN_MANUAL_LAYER_NAME") do |design_manual_layer_name| + options[:design_manual_layer_name] = design_manual_layer_name + end + opts.on("-lCDS_LAYER_NAME", "--layer_name=CDS_LAYER_NAME") do |cds_layer_name| + options[:cds_layer_name] = cds_layer_name + end + opts.on("-pCDS_PURPOSE_NAME", "--purpose_name=CDS_PURPOSE_NAME") do |cds_purpose_name| + options[:cds_purpose_name] = cds_purpose_name + end + end.parse! + if options[:design_manual_layer_name] && options[:cds_layer_name] && + options[:cds_purpose_name] + rep = LayerNameMapper.new() + puts rep.map_layer_name(options[:design_manual_layer_name], + options[:cds_layer_name], + options[:cds_purpose_name]) + end + end +end + + +# +# Only call the main driver if we're calling this as a script +# +if __FILE__ == $0 + LayerNameMapper.main() +end diff --git a/flow/scripts/klayout/src/KLayoutLayerMapGenerator.rb b/flow/scripts/klayout/src/KLayoutLayerMapGenerator.rb new file mode 100755 index 0000000000..225db9b57b --- /dev/null +++ b/flow/scripts/klayout/src/KLayoutLayerMapGenerator.rb @@ -0,0 +1,171 @@ +#!/usr/bin/env ruby +# +# Generates the KLayout layer map file from the Virtuoso Stream Layer Map File +# It's really here to map from the Virtuoso purpose name to KLayout's LEF +# purpose name +# +# Virtuoso Stream Layer Map File Format: +# layer_name purpose_name gds_layer gds_datatype +# +# KLayout Layer Map File Format: +# layer_name lef_purpose_name gds_layer gds_datatype +# +# Usage: KLayoutLayerMapGenerator.rb -i -o +# [-m ] +# +# layer_name_mapper is the path to a file that implements LayerNameMapper for +# custom layer name mapping +# +# File needs to be located in ~/.klayout/ruby +# + +require 'optparse' + +# +# Class to generate the layer map from the Virtuoso Stream Layer Map file +# +class KLayoutLayerMapGenerator + # + # Structs used to store data + # + VirtuosoLayerInfo = Struct.new(:cds_lpp, :gds) + VirtuosoLayerPurposePair = Struct.new(:layer_name, :purpose_name) + GDSLayerDataType = Struct.new(:layer, :datatype) + + # + # Initializer + # + # layer_map: Stores mapping from layer name to VirtuosoLayerInfo object + # + def initialize(layer_name_mapper_file) + @layer_map = {} + # load in layer_name_mapper dynamically + load layer_name_mapper_file + @layer_name_mapper = LayerNameMapper.new() + end + + # + # Reads the Virtuoso Layer Map file + # + def read_virtuoso_layer_map_file(file_name) + fh = File.open(file_name, chomp: true) + if fh + read(fh) + fh.close + else + puts "Error: can't open " + file_name + end + end + + # + # Reads the content from a stream + # + # For each layer in the layer mapping file, add an entry into layer_map. + # The key is the mapped layer name and the value is a list of + # VirtuosoLayerInfo objects. The value is a list since there can be multiple + # entries for the same mapped layer name in the Virtuoso map + # + def read(fh) + layer_re = /(\S+)\s+(\S+)\s+(\d+)\s+(\d+)([^#]*)\#\s*(\S+)?/ + fh.each_line do | line | + if not line.match(/^#/) + result = line.match(layer_re) + if result + layer_name = result[1] + purpose_name = result[2] + gds_layer = result[3].to_i + gds_datatype = result[4].to_i + design_manual_layer_name = result[6] + key = map_layer_name(design_manual_layer_name, layer_name, + purpose_name) + cds_lpp = VirtuosoLayerPurposePair.new(layer_name, purpose_name) + gds = GDSLayerDataType.new(gds_layer, gds_datatype) + layer_info = VirtuosoLayerInfo.new(cds_lpp, gds) + if @layer_map[key] + @layer_map[key] << layer_info + else + @layer_map[key] = [layer_info] + end + else + if line != "\n" + puts "Skipping: " + line + end + end + end + end + end + + # + # Maps layers to the desired name in the layer map + # + def map_layer_name(design_manual_layer_name, cds_layer_name, cds_purpose_name) + return @layer_name_mapper.map_layer_name(design_manual_layer_name, cds_layer_name, cds_purpose_name) + end + + # + # Writes the layer map to a file + # + def write_layer_map_file(file_name) + out_fh = File.open(file_name, "w") do |out_fh| + write_layer_map(out_fh) + end + end + + # + # Writes the layer map to a file handle + # + def write_layer_map(outfh) + layer_map = get_map() + layer_map.each { | layer_name, layer_list | + layer_list.each { | layer_info | + gds_info = layer_info.gds + outfh.printf("%s %d %d\n", layer_name, gds_info.layer, + gds_info.datatype) + } + } + end + + # + # Accessor to return a hash sorted by the gds layer + # + def get_map + sorted_hash = @layer_map.sort_by {|key, value| value[0].gds.layer } + sorted_hash = Hash[sorted_hash] + return sorted_hash + end + + # + # Standalone main driver + # + def KLayoutLayerMapGenerator.main + options = {"layer_name_mapper": "GenericLayerNameMapper.rb"} + OptionParser.new do |opts| + opts.banner = "Usage: KLayoutLayerMapGenerator.rb -i input_file -o output_file" + opts.on("-iINPUT_FILE", "--input_file=INPUT_FILE") do |input_file| + options[:input_file] = input_file + end + opts.on("-oOUTPUT_FILE", "--output_file=OUTPUT_FILE") do |output_file| + options[:output_file] = output_file + end + opts.on("-mLAYER_NAME_MAPPER", "--layer_name_mapper=LAYER_NAME_MAPPER") do |layer_name_mapper_ruby_file| + options[:layer_name_mapper_ruby_file] = layer_name_mapper_ruby_file + end + end.parse! + + if options[:input_file] && options[:output_file] + rep = KLayoutLayerMapGenerator.new(options[:layer_name_mapper_ruby_file]) + rep.read_virtuoso_layer_map_file(options[:input_file]) + rep.write_layer_map_file(options[:output_file]) + else + puts "Usage: KLayoutLayerMapGenerator.rb -i input_file -o output_file [-m layer_name_mapper]" + exit 1 + end + end +end + +# +# Only call the main driver if we're calling this as a script +# +if __FILE__ == $0 + KLayoutLayerMapGenerator.main() +end diff --git a/flow/scripts/klayout/src/KLayoutLayerPropertiesFileGenerator.rb b/flow/scripts/klayout/src/KLayoutLayerPropertiesFileGenerator.rb new file mode 100755 index 0000000000..72e2e69dc9 --- /dev/null +++ b/flow/scripts/klayout/src/KLayoutLayerPropertiesFileGenerator.rb @@ -0,0 +1,70 @@ +#!/usr/bin/env -S klayout -b -r +# +# Generates a KLayout layer properties (.lyp) file from the Virtuoso SKILL Tech +# File +# +# import_tf needs to be in ~/.klayout/ruby, not ~/.klayout/salt +# +# KLayout doesn't support script-specific command line options, so work around +# it with env vars +# +# Usage: KLayoutLayerPropertiesFileGenerator.rb +# + +include RBA +require 'import_tf' + +# +# Class to generate KLayout layer properties file from Virtuoso tech file +# +class KLayoutLayerPropertiesFileGenerator + # + # Initializer + # + # layout_view: layout view to import tech file into + # + def initialize() + @layout_view = LayoutView.new + end + + # + # Reads the Virtuoso tech file + # + def read_virtuoso_tech_file(file_name) + TechfileToKLayout.import_techfile(@layout_view, file_name) + end + + # + # Writes the layer properties file + # + def write_layer_properties_file(file_name) + @layout_view.save_layer_props(file_name) + end + + # + # Standalone main driver + # + # Uses env vars to get arguments since KLayout doesn't support + # script-specific arguments (e.g. it thinks that all arguments are for it) + # + def KLayoutLayerPropertiesFileGenerator.main + input_file = ENV["VIRTUOSO_TECH_FILE"] + output_file = ENV["KLAYOUT_LAYER_PROPERTIES_FILE"] + + if input_file && output_file + rep = KLayoutLayerPropertiesFileGenerator.new() + rep.read_virtuoso_tech_file(input_file) + rep.write_layer_properties_file(output_file) + else + puts "Usage: KLayoutLayerPropertiesFileGenerator.rb" + exit 1 + end + end +end + +# +# Only call the main driver if we're calling this as a script +# +if __FILE__ == $0 + KLayoutLayerPropertiesFileGenerator.main() +end diff --git a/flow/scripts/klayout/src/KLayoutTechFileGenerator.rb b/flow/scripts/klayout/src/KLayoutTechFileGenerator.rb new file mode 100755 index 0000000000..68687cb299 --- /dev/null +++ b/flow/scripts/klayout/src/KLayoutTechFileGenerator.rb @@ -0,0 +1,169 @@ +#!/usr/bin/env -S klayout -b -r +# +# Generates a KLayout technology file (.lyt) from the Virtuoso and Tech LEF +# files +# +# The Ruby files LEFViaData.rb and KLayoutLayerMapGenerator need to be in +# ~/.klayout/ruby +# +# KLayout doesn't support script-specific command line options, so work around +# it with env vars +# +# Usage: KLayoutTechFileGenerator.rb +# + +include RBA +require 'LEFViaData' +require 'KLayoutLayerMapGenerator' + +# +# Class to generate the KLayout tech file +# +class KLayoutTechFileGenerator + # + # Initializer + # + # tech: KLayout technology object + # + def initialize(name, description, layer_properties_file) + @tech = Technology.new() + @tech.name = name + @tech.description = description + @tech.layer_properties_file = layer_properties_file + end + + # + # Iterates through the Virtuoso layer map and creates the layer map that + # gets written to the tech file. + # + # layer map maps layer_name to a string "layer_name:gds_layer/gds_datatype" + # + # Caveats + # 1) KLayout only writes out one mapping per layer, so we only add the + # first occurrence of the layer into the map. This is usually datatype + # == 0 + # + def get_layer_map(sorted_layer_map) + layer_map = LayerMap.new() + sorted_layer_map.each do |layer_name, layer_list| + is_first = true + layer_list.each do |layer_info| + gds_info = layer_info.gds + if layer_name.match?(/\A\d/) + # single quote escaping required for layers that start + # with a digit + layer_name = "'" + layer_name + "'" + end + map_str = sprintf("%s:%d/%d", layer_name, gds_info.layer, + gds_info.datatype) + if is_first + layer_map.map(map_str) + is_first = false + end + end + end + return layer_map + end + + # + # Adds the via layer stack to the connectivity object + # + def add_via_connectivity(lef_file, sorted_layer_map) + via_data = LEFViaData.new() + via_data.read_file(lef_file) + connectivity = @tech.component("connectivity") + via_data.get_map().each do | via_name, via | + layer_list = via.get_layer_list() + lower_layer = layer_list[0] + via_layer = layer_list[1] + upper_layer = layer_list[2] + connection = NetTracerConnectivity.new + connection.name = via_name + connection.connection(lower_layer.get_layer().get_name(), + via_layer.get_layer().get_name(), + upper_layer.get_layer().get_name()) + connectivity.add(connection) + end + # add symbolic mappings based on layers having multiple mappings + sorted_layer_map.each do | layer_name, layer_list | + if layer_list.length > 1 + formatted_layer_list = [] + layer_list.each do | layer_info | + gds_info = layer_info.gds + gds_data = sprintf("%d/%d", gds_info.layer, + gds_info.datatype) + formatted_layer_list << gds_data + end + expr = formatted_layer_list.join("+") + connection = NetTracerConnectivity.new + connection.symbol(layer_name, expr) + connectivity.add(connection) + end + end + end + + # + # Returns the Virtuoso layer map + # + def get_virtuoso_layer_map(file_name, layer_name_mapper) + layer_map_gen = KLayoutLayerMapGenerator.new(layer_name_mapper) + layer_map_gen.read_virtuoso_layer_map_file(file_name) + sorted_layer_map = layer_map_gen.get_map() + return sorted_layer_map + end + + # + # Adds the layer map to the technology object + # + def add_layer_map(layer_map) + # Gets a copy of the reader options + reader_opts = @tech.load_layout_options + lefdef_config = reader_opts.lefdef_config + lefdef_config.layer_map = layer_map + # Add a placeholder LEF, so that the technology file has a lef-files + # element. ORFS keys off this later and replaces the element with the + # real list of LEF files during during 6_final + lefdef_config.lef_files = [ "placeholder.lef" ] + # Store the updated reader options back on the tech object + @tech.load_layout_options = reader_opts + end + + # + # Writes the tech file + # + def save_tech(file_name) + @tech.save(file_name) + end + + # + # Standalone main driver + # + # Uses env vars to get arguments since KLayout doesn't support + # script-specific arguments (e.g. it thinks that all arguments are for it) + # + def KLayoutTechFileGenerator.main() + name = ENV["TECH_NAME"] + desc = ENV["TECH_DESC"] + layer_map_file = ENV["VIRTUOSO_LAYER_MAP_FILE"] + lef_file = ENV["TECH_LEF"] + lyp_file = ENV["KLAYOUT_LAYER_PROPERTIES_FILE"] + lyt_file = ENV["KLAYOUT_TECH_FILE"] + layer_name_mapper = ENV["LAYER_NAME_MAPPER"] + rep = KLayoutTechFileGenerator.new(name, desc, lyp_file) + sorted_layer_map = rep.get_virtuoso_layer_map(layer_map_file, + layer_name_mapper) + layer_map = rep.get_layer_map(sorted_layer_map) + rep.add_layer_map(layer_map) + rep.add_via_connectivity(lef_file, sorted_layer_map) + rep.save_tech(lyt_file) + end +end + +# +# Only call the main driver if we're calling this as a script +# +if __FILE__ == $0 + KLayoutTechFileGenerator.main() +end + + diff --git a/flow/scripts/klayout/src/LEFLayer.rb b/flow/scripts/klayout/src/LEFLayer.rb new file mode 100755 index 0000000000..73d2fa5686 --- /dev/null +++ b/flow/scripts/klayout/src/LEFLayer.rb @@ -0,0 +1,64 @@ +#!/usr/bin/env ruby + +require 'digest' +require_relative 'LEFNamedObject' + +# +# Class to store LEF layer data +# +class LEFLayer < LEFNamedObject + # + # Initializer + # + def initialize(name, num, type=nil) + super(name) + @num = num + @type = type + end + + # + # Sets the layer type + # + def set_type(layer_type) + @type = layer_type + end + + # + # Sets the layer number (order of layer in the tech LEF, which implies + # layer stacking order + # + def get_number() + return @num + end + + # + # Returns the layer type + # + def get_type() + return @type + end + + # + # Writes the LEF statement snippet for the layer + # + def write_lef(out) + layer_name = get_name() + out.puts sprintf("LAYER %s", layer_name) + out.puts sprintf(" TYPE %s ;", get_type()) + out.puts sprintf("END %s", layer_name) + out.puts + end + + # + # Returns the SHA256 for the layer + # + # Layer number is skipped since the layer number could be different between + # tech LEF versions and we'd like to use this to compare across versions + # + def sha256() + if get_type.nil? + return Digest::SHA256.hexdigest(get_name()) + end + return Digest::SHA256.hexdigest(get_name() + get_type()) + end +end diff --git a/flow/scripts/klayout/src/LEFNamedObject.rb b/flow/scripts/klayout/src/LEFNamedObject.rb new file mode 100755 index 0000000000..aebecfde15 --- /dev/null +++ b/flow/scripts/klayout/src/LEFNamedObject.rb @@ -0,0 +1,20 @@ +#!/usr/bin/env ruby + +# +# Class for a basic LEF named object +# +class LEFNamedObject + # + # Initializer + # + def initialize(name) + @name = name + end + + # + # Returns the name + # + def get_name() + return @name + end +end diff --git a/flow/scripts/klayout/src/LEFVia.rb b/flow/scripts/klayout/src/LEFVia.rb new file mode 100755 index 0000000000..e23b2a3df2 --- /dev/null +++ b/flow/scripts/klayout/src/LEFVia.rb @@ -0,0 +1,136 @@ +#!/usr/bin/env ruby + +require 'digest' +require 'json' +require_relative 'LEFNamedObject' + +# +# Class to store LEF via information +# +class LEFVia < LEFNamedObject + # + # Container class that store information about the and shapes that are part + # of the via that exist on the specified layer. Only RECTs are supported. + # + class LEFViaLayer + # + # Initializer + # + # layer is a ref to a LEFLayer + # shape_list is the list of shapes for the via on the specified layer + # + def initialize(layer) + # make sure this is a LEFLayer + if !layer.is_a?(LEFLayer) + raise ArgumentError, sprintf("LEFViaLayer initialize expects LEFLayer, got %s", layer.class.name) + end + @layer = layer + @shape_list = [] + end + + # + # Adds a shape to the shape list + # + def add_shape(shape) + @shape_list << shape + end + + # + # Returns the LEF layer for the shapes + # + def get_layer() + return @layer + end + + # + # Returns the shape list + # + def get_shape_list() + return @shape_list + end + + # + # Computes and returns the sha256 for the container + # + def sha256() + layer_sha = get_layer().sha256() + serialized_shapes = JSON.generate(get_shape_list) + shape_list_sha = Digest::SHA256.hexdigest(serialized_shapes) + return Digest::SHA256.hexdigest(layer_sha + shape_list_sha) + end + + # + # Writes the LEF snippet for the container + # + def write_lef(outfh) + outfh.puts sprintf(" LAYER %s ;", get_layer().get_name()) + get_shape_list.each do | rect | + outfh.puts sprintf(" RECT %5.3f %5.3f %5.3f %5.3f ;", rect[0], + rect[1], rect[2], rect[3]) + end + end + end + + # + # Initializer + # + # layer_list is a list of LEFViaLayers, which is unsorted. That way whoever + # is creating the via can just add LEFViaLayers without regard for the + # layer stacking order. + # + def initialize(name, is_default=false) + super(name) + @is_default = is_default + + # List of LEFViaLayers - unsorted + @layer_list = [] + end + + # + # Computes and returns the sha256 for the via + # + def sha256() + layer_stack = get_layer_list() + hashes = get_layer_list.map { |layer| layer.sha256 } + concat_hashes = hashes.join + return Digest::SHA256.hexdigest(concat_hashes) + end + + # + # Returns the LEFViaLayer list for the via + # + # default is to sort the layers, by the layer number. That way it's returned + # bottom layer to top layer + # + def get_layer_list(sorted=true) + if sorted + return @layer_list.sort_by { |layer| layer.get_layer().get_number } + end + return @layer_list + end + + # + # Adds a layer to the layer list + # + def add_layer(layer) + @layer_list << layer + end + + # + # Writes the LEF snippet + # + def write_lef(outfh) + via_name = get_name() + if @is_default + default_str = " DEFAULT" + else + default_str = "" + end + outfh.puts sprintf("VIA %s%s", via_name, default_str) + get_layer_list().each do | layer | + layer.write_lef(outfh) + end + outfh.puts sprintf("END %s", via_name) + outfh.puts + end +end diff --git a/flow/scripts/klayout/src/LEFViaData.rb b/flow/scripts/klayout/src/LEFViaData.rb new file mode 100755 index 0000000000..ecef4beca8 --- /dev/null +++ b/flow/scripts/klayout/src/LEFViaData.rb @@ -0,0 +1,231 @@ +#!/usr/bin/env ruby +# +# Extracts via layer stack information from the technology LEF file +# +# Usage: LEFViaData.rb -i tech_lef_file [-s sha_file] [-l layer_lef_file ] +# [-v via_lef_file ] +# +# This file needs to be located in ~/.klayout/ruby +# + +require 'optparse' +require_relative 'LEFVia' +require_relative 'LEFLayer' + +# +# Class to extract via layer stack information from technology LEF +# +class LEFViaData + # + # Initialization method + # + # via_map: stores the mapping from a key to the list of layers in the stack + # layer_ct: current layer count - used to set layer numbers establishing + # layer stack order + # start_via_re: regexp to find the start of the LEF VIA statement + # via_layer_re: regexp to extract the layer name in the via layer stack + # start_layer_re: regexp to find the start of the LEF LAYER statement + # rect_re: regexp to extract rect coords + # layer_type_re: regexp to extract LAYER TYPE + # end_re: regexp to find the end of a section + # + def initialize() + @layer_map = {} + @layer_ct = 0 + @via_map = {} + @start_via_re = /^\s*VIA\s+(\S+)(?i)(\s+DEFAULT)?/ + @via_layer_re = /^\s*LAYER\s+(\S+)\s*\;/ + @start_layer_re = /^\s*LAYER\s+(\S+)\s*$/ + @rect_re = /^\s*RECT\s+(\S+)\s+(\S+)\s+(\S+)\s+(\S+)/ + @layer_type_re = /^\s*TYPE\s+(\S+)/ + @end_re = /^\s*END\s+\S+/ + end + + # + # Reads the tech LEF and creates the VIA map + # + def read_file(file_name) + fh = File.open(file_name, chomp: true) + if fh + read(fh) + fh.close + else + puts "Error: can't open " + file_name + end + end + + # + # Reads the content from a stream and looks for the LEF LAYER and VIA + # statements. The layers are added to the layer_map and the vias are added + # to the via_map + # + def read(fh) + while (line = fh.gets) + result = line.match(@start_via_re) + if result + via_name = result[1] + is_default = result[2] + via = LEFVia.new(via_name, is_default) + read_via(fh, via) + @via_map[via.get_name()] = via + else + result = line.match(@start_layer_re) + if result + layer_name = result[1] + layer = LEFLayer.new(layer_name, @layer_ct) + read_layer(fh, layer) + @layer_map[layer_name] = layer + @layer_ct += 1 + end + end + end + end + + # + # Reads the LEF LAYER definition and adds it to the layer object + # + def read_layer(fh, layer) + while (line = fh.gets) + if line.match(@end_re) + return + end + result = line.match(@layer_type_re) + if result + layer.set_type(result[1]) + end + end + end + + # + # Reads the LEF VIA definition and adds it to the via object + # + def read_via(fh, via) + current_layer = nil + while (line = fh.gets) + if line.match(@end_re) + via.add_layer(current_layer) + return + end + result = line.match(@via_layer_re) + if result + if current_layer + via.add_layer(current_layer) + end + current_layer = LEFVia::LEFViaLayer.new(@layer_map[result[1]]) + else + result = line.match(@rect_re) + if result + rect = [result[1].to_f, result[2].to_f, result[3].to_f, result[4].to_f] + current_layer.add_shape(rect) + end + end + end + end + + # + # Accessor to get the via map + # + def get_map() + return @via_map + end + + # + # Utility method to write out LEF VIA snippet to output stream + # + def write_via_lef(outfh) + @via_map.each do | via_name, via | + via.write_lef(outfh) + end + end + + # + # Utility method to write out LEF VIA snippet to file + # + def write_via_lef_file(file_name) + outfh = File.open(file_name, "w") + write_via_lef(outfh) + outfh.close + end + + # + # Utility method to write out SHA list to output stream + # + def write_sha(outfh) + @via_map.each do | via_name, via | + sha256 = via.sha256() + outfh.puts sprintf("%s %s", sha256, via_name) + end + end + + # + # Utility method to write out SHA list to output file + # + def write_sha_file(file_name) + outfh = File.open(file_name, "w") + write_sha(outfh) + outfh.close + end + + # + # Utility method to write out LEF LAYER snippet to output stream + # + def write_layer_lef(outfh) + sorted_layer_map = @layer_map.sort_by { |layer_name, layer| layer.get_number }.to_h + sorted_layer_map.each do | layer_name, layer | + layer.write_lef(outfh) + end + end + + # + # Utility method to write out LEF LAYER snippet to output file + # + def write_layer_lef_file(file_name) + outfh = File.open(file_name, "w") + write_layer_lef(outfh) + outfh.close + end + + # + # Standalone main driver + # + def LEFViaData.main() + options = {} + OptionParser.new do |opts| + opts.banner = "Usage: LEFViaData.rb -i tech_lef_file [-s ] [-l ] [-v -l +# -t -n +# -d -p +# -o [-m layer_name_mapper_ruby] [-h] +# +# where +# virtuoso_tech_file: Cadence Virtuoso SKILL tech file +# virtuoso_layer_map: Cadence Virtuoso layer mapping file (maps Cadence +# layer/purpose pairs to GDS II layer/datatype) +# tech_lef: Cadence technology LEF with layer and via definitions +# tech_name: Name to put in KLayout technology file +# tech_description: Description to put in KLayout technology file +# klayout_lyp: KLayout layer properties file (typically ending in .lyp) - +# generated from Virtuoso tech file +# klayout_lyt: Klayout technology file (typically ending in .lyt) +# layer_name_mapper_ruby: Name of Ruby file containing custom layer name mapper +# Uses GenericLayerNameMapper.rb by default +# +# KLayout doesn't support passing script-specific command line arguments, so we +# translate this script's command line arguments into environment variables to +# pass to the KLayout Ruby scripts we call +# + +# +# Prints the help usage +# +PrintHelp() +{ + echo "Usage: gen_klayout_files.sh -v -l " + echo " -t -n -d " + echo " -p -o " + echo " [-m " +} + +# +# Clear the env variables, in case they are set. +# +# Could cache previous values and set them back to their previous values in the +# future +# +ClearEnvVars() +{ + unset VIRTUOSO_TECH_FILE + unset VIRTUOSO_LAYER_MAP_FILE + unset TECH_LEF + unset KLAYOUT_LAYER_PROPERTIES_FILE + unset KLAYOUT_TECH_FILE + unset TECH_NAME + unset TECH_DESC + unset LAYER_NAME_MAPPER +} + +# +# Parse args and set environment variables +# +GetOptionsAndSetEnvVars() +{ + export LAYER_NAME_MAPPER=GenericLayerNameMapper.rb + local OPTIND + while getopts "hv:l:t:n:d:p:o:m:" option; do + case $option in + h) + PrintHelp + exit 1;; + v) + export VIRTUOSO_TECH_FILE=$OPTARG + ;; + l) + export VIRTUOSO_LAYER_MAP_FILE=$OPTARG + ;; + t) + export TECH_LEF=$OPTARG + ;; + n) + export TECH_NAME=$OPTARG + ;; + d) + export TECH_DESC=$OPTARG + ;; + p) + export KLAYOUT_LAYER_PROPERTIES_FILE=$OPTARG + ;; + o) + export KLAYOUT_TECH_FILE=$OPTARG + ;; + m) + export LAYER_NAME_MAPPER=$OPTARG + ;; + \?) + echo "Error: Invalid option" + exit 1;; + esac + done + shift $((OPTIND-1)) +} + +# +# Check that all required env vars are set +# +CheckRequiredEnvVars() +{ + if [ -z "${VIRTUOSO_TECH_FILE}" ] || [ -z "${VIRTUOSO_LAYER_MAP_FILE}" ] || + [ -z "${TECH_LEF}" ] || [ -z "${KLAYOUT_LAYER_PROPERTIES_FILE}" ] || + [ -z "${KLAYOUT_TECH_FILE}" ] || [ -z "${TECH_NAME}" ] || + [ -z "${TECH_DESC}" ]; then + echo "Error: Missing a required option" + PrintHelp + exit 1 + fi +} + +# +# Echoes env vars and values +# +EchoEnvVars() +{ + echo "VIRTUOSO_TECH_FILE=${VIRTUOSO_TECH_FILE}" + echo "VIRTUOSO_LAYER_MAP_FILE=${VIRTUOSO_LAYER_MAP_FILE}" + echo "TECH_LEF=${TECH_LEF}" + echo "KLAYOUT_LAYER_PROPERTIES_FILE=${KLAYOUT_LAYER_PROPERTIES_FILE}" + echo "KLAYOUT_TECH_FILE=${KLAYOUT_TECH_FILE}" + echo "TECH_NAME=${TECH_NAME}" + echo "TECH_DESC=${TECH_DESC}" + echo "LAYER_NAME_MAPPER=${LAYER_NAME_MAPPER}" +} + +# +# Check that Ruby scripts that we depend on are in place +# +CheckRequiredKLayoutScripts() +{ + is_error=0 + klayout_file_path=~/.klayout/ruby + script_list=("LEFNamedObject.rb" "LEFLayer.rb" "LEFVia.rb" "LEFViaData.rb" + "KLayoutLayerMapGenerator.rb" "import_tf.rb" + "KLayoutLayerPropertiesFileGenerator.rb") + script_list+=("${LAYER_NAME_MAPPER}") + for script_name in "${script_list[@]}"; do + file_path=${klayout_file_path}/${script_name} + if [ ! -e $file_path ]; then + echo "Error: Missing KLayout script: $file_path" + is_error=1 + fi + done + if [ $is_error -eq 1 ]; then + echo "Info: Please install missing scripts using ORFS instructions at https://openroad-flow-scripts.readthedocs.io/en/latest/contrib/PlatformBringUp.html#klayout-properties-file" + exit 1; + fi +} + +# +# Calls the KLayout scripts to generate the layer properties and tech files +# +CallKLayoutScripts() +{ + pwd=$(dirname "$0") + + $pwd/KLayoutLayerPropertiesFileGenerator.rb + $pwd/KLayoutTechFileGenerator.rb +} + +# +# Steps to execute +# +ClearEnvVars +GetOptionsAndSetEnvVars "$@" +CheckRequiredEnvVars +CheckRequiredKLayoutScripts +CallKLayoutScripts +ClearEnvVars + +exit 0 diff --git a/flow/scripts/klayout/test/GenericLayerNameMapperTest.rb b/flow/scripts/klayout/test/GenericLayerNameMapperTest.rb new file mode 100755 index 0000000000..46471491d9 --- /dev/null +++ b/flow/scripts/klayout/test/GenericLayerNameMapperTest.rb @@ -0,0 +1,36 @@ +#!/usr/bin/env ruby + +require 'test/unit' +require_relative '../src/GenericLayerNameMapper' + +# +# Unit test for GenericLayerNameMapper +# +class GenericLayerNameMapperTest < Test::Unit::TestCase + # + # Sets up GenericLayerNameMapper object + # + def setup + @rep = LayerNameMapper.new() + end + + # + # Tests basic operation + # + def test_basic + test_data = [ + [ "M1", "M1", "drawing", "M1" ], + [ "", "E1", "drawing", "E1" ], + ] + test_data.each do | test_case | + design_layer_name = test_case[0] + cds_layer_name = test_case[1] + cds_purpose_name = test_case[2] + exp_layer_name = test_case[3] + mapped_name = @rep.map_layer_name(design_layer_name, cds_layer_name, + cds_purpose_name) + assert(mapped_name == exp_layer_name, + sprintf("got %s expecting %s", mapped_name, exp_layer_name)) + end + end +end diff --git a/flow/scripts/klayout/test/KLayoutLayerMapGeneratorTest.rb b/flow/scripts/klayout/test/KLayoutLayerMapGeneratorTest.rb new file mode 100755 index 0000000000..99c7cf8f61 --- /dev/null +++ b/flow/scripts/klayout/test/KLayoutLayerMapGeneratorTest.rb @@ -0,0 +1,66 @@ +#!/usr/bin/env ruby + +require 'stringio' +require 'test/unit' +require_relative '../src/KLayoutLayerMapGenerator' + +# +# Unit test for KLayoutLayerMapGenerator +# +class KLayoutLayerMapGeneratorTest < Test::Unit::TestCase + # + # Sets up KLayoutLayerMapGenerator object + # + def setup + current_dir = File.dirname(__FILE__) + layer_name_map_file = File.join(current_dir, "..", "src", + "GenericLayerNameMapper.rb") + @rep = KLayoutLayerMapGenerator.new(layer_name_map_file) + end + + # + # Tests basic operation + # + def test_basic + data_str = <<~LM_TEXT +# Bogus sample layer map +M1 drawing 99 0 # M1 +M1 net 99 23 # M1_NET +M1 net2 99 23 # M1_NET +1Layer drawing 123 99 # 1Layer +LM_TEXT + + data_stream = StringIO.new(data_str) + @rep.read(data_stream) + layer_map = @rep.get_map() + assert(layer_map) + assert(layer_map.length == 3) + # Test M1 entry + layer_list = layer_map["M1"] + assert(layer_list.length == 1) + entry = layer_list[0] + assert(entry) + assert(entry.cds_lpp.layer_name == "M1") + assert(entry.cds_lpp.purpose_name == "drawing") + assert(entry.gds.layer == 99) + assert(entry.gds.datatype == 0) + # Test M1 NET entry + layer_list = layer_map["M1_NET"] + assert(layer_list.length == 2) + layer_list.each do | entry | + assert(entry) + assert(entry.cds_lpp.layer_name == "M1") + assert(entry.cds_lpp.purpose_name.start_with?("net")) + assert(entry.gds.layer == 99) + assert(entry.gds.datatype == 23) + end + # Test 1Layer entry + layer_list = layer_map["1Layer"] + assert(layer_list.length == 1) + entry = layer_list[0] + assert(entry.cds_lpp.layer_name == "1Layer") + assert(entry.cds_lpp.purpose_name == "drawing") + assert(entry.gds.layer == 123) + assert(entry.gds.datatype == 99) + end +end diff --git a/flow/scripts/klayout/test/LEFLayerTest.rb b/flow/scripts/klayout/test/LEFLayerTest.rb new file mode 100755 index 0000000000..b7c49de1c6 --- /dev/null +++ b/flow/scripts/klayout/test/LEFLayerTest.rb @@ -0,0 +1,49 @@ +#!/usr/bin/env ruby + +require 'test/unit' +require_relative '../src/LEFLayer' + +# +# Unit test for LEFLayer +# +class LEFLayerTest < Test::Unit::TestCase + # + # Sets up LEFLayer object + # + def setup + end + + # + # Tests basic operation + # + def test_basic + name = "M1" + num = 100 + type = "ROUTING" + + # make a M1 and verify contents + orig_m1 = LEFLayer.new(name, num) + assert(orig_m1) + assert(orig_m1.get_type().nil?) + assert(orig_m1.get_name() == name) + assert(orig_m1.get_number() == num) + sha_wo_type = orig_m1.sha256() + orig_m1.set_type(type) + assert(orig_m1.get_type() == type) + orig_m1_sha = orig_m1.sha256() + assert(orig_m1_sha != sha_wo_type) + + # make a new M1 with a different layer number + new_m1 = LEFLayer.new(name, num + 1) + assert(new_m1) + assert(new_m1.get_type().nil?) + assert(new_m1.get_name() == name) + assert(new_m1.get_number() == num + 1) + new_m1.set_type(type) + assert(new_m1.get_type() == type) + new_m1_sha = new_m1.sha256() + + # The sha's should be the same since we are excluding the layer number + assert(orig_m1_sha == new_m1_sha) + end +end diff --git a/flow/scripts/klayout/test/LEFNamedObjectTest.rb b/flow/scripts/klayout/test/LEFNamedObjectTest.rb new file mode 100755 index 0000000000..cca8e350a4 --- /dev/null +++ b/flow/scripts/klayout/test/LEFNamedObjectTest.rb @@ -0,0 +1,26 @@ +#!/usr/bin/env ruby + +require 'test/unit' +require_relative '../src/LEFNamedObject' + +# +# Unit test for LEFNamedObject +# +class LEFNamedObjectTest < Test::Unit::TestCase + # + # Sets up LEFNamedObject object + # + def setup + end + + # + # Tests basic operation + # + def test_basic + name = "M1" + + obj = LEFNamedObject.new(name) + assert(obj) + assert(obj.get_name() == name) + end +end diff --git a/flow/scripts/klayout/test/LEFViaDataTest.rb b/flow/scripts/klayout/test/LEFViaDataTest.rb new file mode 100755 index 0000000000..a8b9685dca --- /dev/null +++ b/flow/scripts/klayout/test/LEFViaDataTest.rb @@ -0,0 +1,77 @@ +#!/usr/bin/env ruby + +require 'stringio' +require 'test/unit' +require_relative '../src/LEFViaData' + +# +# Unit test for LEFViaData +# +class LEFViaDataTest < Test::Unit::TestCase + # + # Sets up LEFViaData object + # + def setup + @rep = LEFViaData.new() + end + + # + # Tests basic operation + # + def test_basic + data_str = <<~LEF_TEXT +LAYER M8 + TYPE ROUTING ; +END M8 +LAYER V8 + TYPE CUT ; +END V8 +LAYER M9 + TYPE ROUTING ; +END M9 +LAYER V9 + TYPE CUT ; +END V9 +LAYER Pad + TYPE ROUTING ; +END Pad + VIA VIA9Pad Default + LAYER M9 ; + RECT -0.05 -0.05 0.05 0.05 ; + LAYER Pad ; + RECT -0.05 -0.05 0.05 0.05 ; + LAYER V9 ; + RECT -0.05 -0.05 0.05 0.05 ; +END VIA9Pad + +VIA VIA89 Default + LAYER M8 ; + RECT -0.02 -0.02 0.02 0.02 ; + LAYER M9 ; + RECT -0.02 -0.02 0.02 0.02 ; + LAYER V8 ; + RECT -0.02 -0.02 0.02 0.02 ; +END VIA89 +LEF_TEXT + + exp_layers = { + "VIA9Pad" => [ "M9", "V9", "Pad" ], + "VIA89" => [ "M8", "V8", "M9" ], + } + + data_stream = StringIO.new(data_str) + @rep.read(data_stream) + via_map = @rep.get_map() + assert(via_map) + assert(via_map.length == 2, + sprintf("via map length is not 2: %d", via_map.length)) + via_map.each do | via_name, via | + layer_list = via.get_layer_list() + assert(layer_list.length == exp_layers[via_name].length) + layer_name_list = layer_list.sort_by {|obj| obj.get_layer.get_number}.map { |obj| obj.get_layer.get_name } + assert(exp_layers[via_name] == layer_name_list, + sprintf("expected %s. got %s", exp_layers[via_name], + layer_name_list)) + end + end +end diff --git a/flow/scripts/klayout/test/LEFViaTest.rb b/flow/scripts/klayout/test/LEFViaTest.rb new file mode 100755 index 0000000000..3e8d853e42 --- /dev/null +++ b/flow/scripts/klayout/test/LEFViaTest.rb @@ -0,0 +1,157 @@ +#!/usr/bin/env ruby + +require 'test/unit' +require 'stringio' +require_relative '../src/LEFLayer' +require_relative '../src/LEFVia' + +# +# Unit test for LEFVia +# +class LEFViaTest < Test::Unit::TestCase + # + # Sets up LEFVia object + # + def setup + @m1_layer = LEFLayer.new("M1", 100, "ROUTING") + @cut_layer = LEFLayer.new("CUT", 150, "CUT") + @m2_layer = LEFLayer.new("M2", 200, "ROUTING") + @diff_m1_layer = LEFLayer.new(@m1_layer.get_name(), + @m1_layer.get_number() + 1000, + @m1_layer.get_type()) + @rect = [0, 0, 100, 100] + @bottom_via_layer = LEFVia::LEFViaLayer::new(@m1_layer) + @bottom_via_layer.add_shape(@rect) + @bottom_via_layer_lef = get_exp_via_layer_str(@m1_layer.get_name(), + @rect) + @cut_via_layer = LEFVia::LEFViaLayer::new(@cut_layer) + @cut_via_layer.add_shape(@rect) + @cut_via_layer_lef = get_exp_via_layer_str(@cut_layer.get_name(), @rect) + @top_via_layer = LEFVia::LEFViaLayer::new(@m2_layer) + @top_via_layer.add_shape(@rect) + @top_via_layer_lef = get_exp_via_layer_str(@m2_layer.get_name(), @rect) + end + + def get_exp_via_layer_str(layer_name, rect) + return sprintf(" LAYER %s ;\n RECT %5.3f %5.3f %5.3f %5.3f ;\n", + layer_name, rect[0], rect[1], rect[2], rect[3]) + end + + # + # Tests the LEFViaLayer object + # + def test_via_layer_basic + lef_output = StringIO.new() + + obj = LEFVia::LEFViaLayer.new(@m1_layer) + assert(obj) + assert(obj.get_layer() == @m1_layer) + assert(obj.get_shape_list().empty?) + obj.write_lef(lef_output) + exp_lef = " LAYER M1 ;\n" + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + obj.add_shape(@rect) + assert(obj.get_shape_list().length == 1) + assert(obj.get_shape_list()[0] == @rect) + exp_lef = " LAYER M1 ;\n RECT 0.000 0.000 100.000 100.000 ;\n" + lef_output.rewind + obj.write_lef(lef_output) + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + orig_sha = obj.sha256 + + # Make another object with the same values, but a different layer + new_obj = LEFVia::LEFViaLayer.new(@diff_m1_layer) + new_obj.add_shape(@rect) + new_sha = new_obj.sha256 + assert(orig_sha == new_sha) + end + + # + # Tests basic operation for a default via + # + def test_basic_default + name = "VIA12" + lef_output = StringIO.new() + + obj = LEFVia.new(name, true) + assert(obj) + assert(obj.get_name() == name) + assert(obj.get_layer_list().empty?) + exp_lef = sprintf("VIA %s DEFAULT\nEND %s\n\n", name, name) + empty_sha = obj.sha256() + obj.write_lef(lef_output) + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + + # add layers and check + obj.add_layer(@bottom_via_layer) + obj.add_layer(@cut_via_layer) + obj.add_layer(@top_via_layer) + + # check unsorted layer_list + assert(obj.get_layer_list(false).length == 3) + + # check sorted layer_list + layer_list = obj.get_layer_list() + assert(layer_list.length == 3) + assert(layer_list[0] == @bottom_via_layer) + assert(layer_list[1] == @cut_via_layer) + assert(layer_list[2] == @top_via_layer) + + # check LEF output + lef_output.rewind + obj.write_lef(lef_output) + exp_lef = sprintf("VIA %s DEFAULT\n%s%s%sEND %s\n\n", name, + @bottom_via_layer_lef, @cut_via_layer_lef, + @top_via_layer_lef, name) + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + + # Check sha's with and without layers - should be different + assert(obj.sha256() != empty_sha) + end + + # + # Tests basic operation + # + def test_basic + name = "VIA12" + lef_output = StringIO.new() + + obj = LEFVia.new(name, false) + assert(obj) + assert(obj.get_name() == name) + exp_lef = sprintf("VIA %s\nEND %s\n\n", name, name) + obj.write_lef(lef_output) + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + + # add layers and check + # for this test, we'll create the layers in top to bottom order and + # then verify that they come back in bottom to top order + obj.add_layer(@top_via_layer) + obj.add_layer(@cut_via_layer) + obj.add_layer(@bottom_via_layer) + + # check unsorted layer_list + assert(obj.get_layer_list(false).length == 3) + + # check sorted layer_list + layer_list = obj.get_layer_list() + assert(layer_list.length == 3) + assert(layer_list[0] == @bottom_via_layer) + assert(layer_list[1] == @cut_via_layer) + assert(layer_list[2] == @top_via_layer) + + # check LEF output + lef_output.rewind + obj.write_lef(lef_output) + exp_lef = sprintf("VIA %s\n%s%s%sEND %s\n\n", name, + @bottom_via_layer_lef, @cut_via_layer_lef, + @top_via_layer_lef, name) + assert(lef_output.string == exp_lef, + sprintf("got '%s' expected '%s'", lef_output.string, exp_lef)) + end +end diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl index 90eca7ef51..104ae12993 100644 --- a/flow/scripts/load.tcl +++ b/flow/scripts/load.tcl @@ -2,27 +2,39 @@ source $::env(SCRIPTS_DIR)/util.tcl source $::env(SCRIPTS_DIR)/report_metrics.tcl -# Temporarily disable sta's threading due to random failures -sta::set_thread_count 1 +proc load_design { design_file sdc_file } { + source_env_var_if_exists PLATFORM_TCL -proc load_design {design_file sdc_file} { - # Read liberty files source $::env(SCRIPTS_DIR)/read_liberty.tcl # Read design files set ext [file extension $design_file] - if {$ext == ".v"} { + if { $ext == ".v" } { read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } } read_verilog $::env(RESULTS_DIR)/$design_file - link_design $::env(DESIGN_NAME) - } elseif {$ext == ".odb"} { - read_db $::env(RESULTS_DIR)/$design_file + if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] + } { + link_design -hier $::env(DESIGN_NAME) + } else { + link_design $::env(DESIGN_NAME) + } + } elseif { $ext == ".odb" } { + if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] + } { + read_db -hier $::env(RESULTS_DIR)/$design_file + } else { + read_db $::env(RESULTS_DIR)/$design_file + } } else { error "Unrecognized input file $design_file" } @@ -30,8 +42,8 @@ proc load_design {design_file sdc_file} { # Read SDC file read_sdc $::env(RESULTS_DIR)/$sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { - source $::env(PLATFORM_DIR)/derate.tcl + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { + log_cmd source $::env(PLATFORM_DIR)/derate.tcl } source $::env(PLATFORM_DIR)/setRC.tcl @@ -43,86 +55,68 @@ proc load_design {design_file sdc_file} { } #=========================================================================================== -# Routines to run equivalence tests when they are enabled. - -proc get_verilog_cells_for_design { } { - set dir "$::env(PLATFORM_DIR)/work_around_yosys/" - set cell_files [glob $dir/*.v ] -} +# Routines to run equivalence tests when they are enabled. -proc write_eqy_verilog {filename} { +proc write_eqy_verilog { filename } { # Filter out cells with no verilog/not needed for equivalence such # as fillers and tap cells - if {[env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY]} { + if { [env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY] } { write_verilog -remove_cells $::env(REMOVE_CELLS_FOR_EQY) $::env(RESULTS_DIR)/$filename } else { - write_verilog $::env(RESULTS_DIR)/$filename + write_verilog $::env(RESULTS_DIR)/$filename } } -proc write_eqy_script_for_sky130hd {} { - error "this routine is not yet implemented" - #[gold] - #read_verilog -sv ./before.v ./formal_pdk.v - - #[gate] - #read_verilog -sv ./after.v ./formal_pdk.v - - #[script] - #prep -top aes_cipher_top -flatten - - ## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all - #rename -hide */_*_.* - - ## This removes unused signals before partitioning so no partitions are created for them - #opt_clean -purge - #memory_map - - #[collect *] - ## This groups signals like `some_signal[0]`, `some_signal[1]`, ... that only differ in the index - #group *[] \1[] - - #[strategy basic] - #use sat - #depth 2 -} - - proc write_eqy_script { } { - set top_cell [current_design] - set cell_files [get_verilog_cells_for_design] - set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] - # Gold netlist - puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - # Modified netlist - puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n" - puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" - - # Recommendation from eqy team on how to speed up a design - puts $outfile "\[match *]\ngate-nomatch _*_.*\n\n" - - # Equivalence check recipe 1 - puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" - # Equivalence check recipe 2 - puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" - - close $outfile + set top_cell [current_design] + set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w] + # Gold netlist + puts $outfile "\[gold]\nread_liberty -ignore_miss_func $::env(LIB_FILES)\n" + puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + # Modified netlist + puts $outfile "\[gate]\nread_liberty -ignore_miss_func $::env(LIB_FILES)\n" + puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v\n" + puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n" + + # Recommendation from eqy team on how to speed up a design + puts $outfile "\[match *]\ngate-nomatch _*_.*" + + # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets" + puts $outfile "gate-nomatch net*" + + # Forbid matching on buffer instances or cloned instances to make it less + # likely EQY will fail to prove equivalence because of its assuming structural + # similarity between gold and gate netlists. This doesn't remove coverage. + puts $outfile "gate-nomatch clone*" + puts $outfile "gate-nomatch place*" + puts $outfile "gate-nomatch rebuffer*" + puts $outfile "gate-nomatch wire*" + puts $outfile "gate-nomatch place*\n\n" + + # Equivalence check recipe 1 + puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n" + # Equivalence check recipe 2 + puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n" + + close $outfile } -proc run_equivalence_test {} { - write_eqy_verilog 4_after_rsz.v - write_eqy_script - - eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ - --force \ - --jobs $::env(NUM_CORES) \ - $::env(OBJECTS_DIR)/4_eqy_test.eqy \ - > $::env(LOG_DIR)/4_equivalence_check.log - set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] - if { $count == 0 } { - error "Repair timing output failed equivalence test" - } else { - puts "Repair timing output passed equivalence test" - } +proc run_equivalence_test { } { + write_eqy_verilog 4_after_rsz.v + write_eqy_script + + # tclint-disable-next-line command-args + eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \ + --force \ + --jobs $::env(NUM_CORES) \ + $::env(OBJECTS_DIR)/4_eqy_test.eqy \ + > $::env(LOG_DIR)/4_equivalence_check.log + set count \ + [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log] + if { $count == 0 } { + error "Repair timing output failed equivalence test" + } else { + puts "Repair timing output passed equivalence test" + } } diff --git a/flow/scripts/macro_place.tcl b/flow/scripts/macro_place.tcl index 12d59b1008..cc0f7706c6 100644 --- a/flow/scripts/macro_place.tcl +++ b/flow/scripts/macro_place.tcl @@ -1,7 +1,8 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_2_floorplan_io.odb 2_1_floorplan.sdc +load_design 2_1_floorplan.odb 2_1_floorplan.sdc source $::env(SCRIPTS_DIR)/macro_place_util.tcl -write_db $::env(RESULTS_DIR)/2_3_floorplan_macro.odb +write_db $::env(RESULTS_DIR)/2_2_floorplan_macro.odb +write_macro_placement $::env(RESULTS_DIR)/2_2_floorplan_macro.tcl diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl index 54bbff6ade..8aa9963ad0 100644 --- a/flow/scripts/macro_place_util.tcl +++ b/flow/scripts/macro_place_util.tcl @@ -1,7 +1,16 @@ -if {[find_macros] != ""} { -# If wrappers defined replace macros with their wrapped version -# # ---------------------------------------------------------------------------- - if {[env_var_exists_and_non_empty MACRO_WRAPPERS]} { +if { [find_macros] != "" } { + if { ![env_var_exists_and_non_empty RTLMP_RPT_DIR] } { + set ::env(RTLMP_RPT_DIR) "$::env(OBJECTS_DIR)/rtlmp" + } + if { ![env_var_exists_and_non_empty RTLMP_RPT_FILE] } { + set ::env(RTLMP_RPT_FILE) "partition.txt" + } + if { ![env_var_exists_and_non_empty RTLMP_BLOCKAGE_FILE] } { + set ::env(RTLMP_BLOCKAGE_FILE) "$::env(OBJECTS_DIR)/rtlmp/partition.txt.blockage" + } + + # If wrappers defined replace macros with their wrapped version + if { [env_var_exists_and_non_empty MACRO_WRAPPERS] } { source $::env(MACRO_WRAPPERS) set wrapped_macros [dict keys [dict get $wrapper around]] @@ -9,7 +18,7 @@ if {[find_macros] != ""} { set block [ord::get_db_block] foreach inst [$block getInsts] { - if {[lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1} { + if { [lsearch -exact $wrapped_macros [[$inst getMaster] getName]] > -1 } { set new_master [dict get $wrapper around [[$inst getMaster] getName]] puts "Replacing [[$inst getMaster] getName] with $new_master for [$inst getName]" $inst swapMaster [$db findMaster $new_master] @@ -18,19 +27,16 @@ if {[find_macros] != ""} { } lassign $::env(MACRO_PLACE_HALO) halo_x halo_y - lassign $::env(MACRO_PLACE_CHANNEL) channel_x channel_y set halo_max [expr max($halo_x, $halo_y)] - set channel_max [expr max($channel_x, $channel_y)] - set blockage_width [expr max($halo_max, $channel_max/2)] + set blockage_width $halo_max - - if {[env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO]} { + if { [env_var_exists_and_non_empty MACRO_BLOCKAGE_HALO] } { set blockage_width $::env(MACRO_BLOCKAGE_HALO) } - if {[env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]} { + if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } { log_cmd source $::env(MACRO_PLACEMENT_TCL) - } elseif {[env_var_exists_and_non_empty MACRO_PLACEMENT]} { + } elseif { [env_var_exists_and_non_empty MACRO_PLACEMENT] } { source $::env(SCRIPTS_DIR)/read_macro_placement.tcl log_cmd read_macro_placement $::env(MACRO_PLACEMENT) } else { @@ -68,7 +74,7 @@ if {[find_macros] != ""} { } source $::env(SCRIPTS_DIR)/placement_blockages.tcl - block_channels $blockage_width + block_channels $blockage_width } else { puts "No macros found: Skipping macro_placement" } diff --git a/flow/scripts/mem_dump.py b/flow/scripts/mem_dump.py index 0104ae19c9..36956bece8 100644 --- a/flow/scripts/mem_dump.py +++ b/flow/scripts/mem_dump.py @@ -123,6 +123,5 @@ def format_ram_table_from_json(data, max_bits=None): print(formatted_table) if not max_ok: sys.exit( - "ERROR: Synthesized memory size exceeds maximum allowed bits " - + str(args.max_bits) + f"Error: Synthesized memory size {args.max_bits} exceeds SYNTH_MEMORY_MAX_BITS" ) diff --git a/flow/scripts/noop.tcl b/flow/scripts/noop.tcl index e69de29bb2..8b13789179 100644 --- a/flow/scripts/noop.tcl +++ b/flow/scripts/noop.tcl @@ -0,0 +1 @@ + diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl index 64b7617da4..8a1dcc0da4 100644 --- a/flow/scripts/open.tcl +++ b/flow/scripts/open.tcl @@ -1,71 +1,71 @@ source $::env(SCRIPTS_DIR)/util.tcl -# Read liberty files + +source_env_var_if_exists PLATFORM_TCL + source $::env(SCRIPTS_DIR)/read_liberty.tcl -# Read def -if {[env_var_exists_and_non_empty DEF_FILE]} { - # Read lef - read_lef $::env(TECH_LEF) - read_lef $::env(SC_LEF) - if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} { - foreach lef $::env(ADDITIONAL_LEFS) { - read_lef $lef - } +if { [env_var_exists_and_non_empty DEF_FILE] } { + log_cmd read_lef $::env(TECH_LEF) + log_cmd read_lef $::env(SC_LEF) + if { [env_var_exists_and_non_empty ADDITIONAL_LEFS] } { + foreach lef $::env(ADDITIONAL_LEFS) { + log_cmd read_lef $lef } - set input_file $::env(DEF_FILE) - read_def $input_file + } + set input_file $::env(DEF_FILE) + log_cmd read_def $input_file } else { - set input_file $::env(ODB_FILE) - read_db $input_file + set input_file $::env(ODB_FILE) + log_cmd read_db $input_file } -proc read_timing {input_file} { +proc read_timing { input_file } { set result [find_sdc_file $input_file] set design_stage [lindex $result 0] set sdc_file [lindex $result 1] - if {$sdc_file == ""} { + if { $sdc_file == "" } { set sdc_file $::env(SDC_FILE) } - read_sdc $sdc_file - if [file exists $::env(PLATFORM_DIR)/derate.tcl] { + log_cmd read_sdc $sdc_file + if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } { source $::env(PLATFORM_DIR)/derate.tcl } - + source $::env(PLATFORM_DIR)/setRC.tcl - if {$design_stage >= 4} { + if { $design_stage >= 4 } { # CTS has run, so propagate clocks set_propagated_clock [all_clocks] } - - if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} { + + if { $design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef] } { log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef - } elseif {$design_stage >= 5} { - if { [grt::have_routes] } { + } elseif { $design_stage >= 5 } { + if { [log_cmd grt::have_routes] } { log_cmd estimate_parasitics -global_routing } else { puts "No global routing results available, skipping estimate_parasitics" puts "Load $::global_route_congestion_report for details" } - } elseif {$design_stage >= 3} { + } elseif { $design_stage >= 3 } { log_cmd estimate_parasitics -placement } - puts -nonewline "Populating timing paths..." # Warm up OpenSTA, so clicking on timing related buttons reacts faster - set _tmp [find_timing_paths] - puts "OK" + set _tmp [log_cmd find_timing_paths] } -if {[env_var_equals GUI_TIMING 1]} { - puts "GUI_TIMING=1 reading timing, takes a little while for large designs..." - read_timing $input_file +if { [ord::openroad_gui_compiled] } { + set db_basename [file rootname [file tail $input_file]] + gui::set_title \ + "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}" } -fast_route - -if {[env_var_equals GUI_SHOW 1]} { - # Show the GUI when it is ready; it is unresponsive(with modal requesters - # saying it is unresponsive) until everything is loaded - gui::unminimize +if { [env_var_equals GUI_TIMING 1] } { + puts "GUI_TIMING=1 reading timing, takes a little while for large designs..." + read_timing $input_file + if { [gui::enabled] } { + log_cmd gui::select_chart "Endpoint Slack" + log_cmd gui::update_timing_report + } } diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index a43f95ef19..72d2c55c14 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -1,23 +1,21 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_4_floorplan_tapcell.odb 2_1_floorplan.sdc +load_design 2_3_floorplan_tapcell.odb 2_1_floorplan.sdc source $::env(PDN_TCL) pdngen -if { [env_var_exists_and_non_empty POST_PDN_TCL] } { - source $::env(POST_PDN_TCL) -} +source_env_var_if_exists POST_PDN_TCL # Check all supply nets set block [ord::get_db_block] foreach net [$block getNets] { - set type [$net getSigType] - if {$type == "POWER" || $type == "GROUND"} { -# Temporarily disable due to CI issues -# puts "Check supply: [$net getName]" -# check_power_grid -net [$net getName] - } + set type [$net getSigType] + if { $type == "POWER" || $type == "GROUND" } { + # Temporarily disable due to CI issues + # puts "Check supply: [$net getName]" + # check_power_grid -net [$net getName] + } } -write_db $::env(RESULTS_DIR)/2_5_floorplan_pdn.odb +write_db $::env(RESULTS_DIR)/2_4_floorplan_pdn.odb diff --git a/flow/scripts/placement_blockages.tcl b/flow/scripts/placement_blockages.tcl index 876a01f903..82c306474b 100644 --- a/flow/scripts/placement_blockages.tcl +++ b/flow/scripts/placement_blockages.tcl @@ -1,4 +1,4 @@ -proc block_channels {channel_width_in_microns} { +proc block_channels { channel_width_in_microns } { set tech [ord::get_db_tech] set units [$tech getDbUnitsPerMicron] set block [ord::get_db_block] @@ -8,7 +8,7 @@ proc block_channels {channel_width_in_microns} { # set shapes {} foreach inst [$block getInsts] { - if {[[$inst getMaster] getType] == "BLOCK"} { + if { [[$inst getMaster] getType] == "BLOCK" } { set box [$inst getBBox] lappend shapes [odb::newSetFromRect [$box xMin] [$box yMin] [$box xMax] [$box yMax]] } @@ -37,9 +37,8 @@ proc block_channels {channel_width_in_microns} { # set rects [odb::getRectangles $shapeSet] foreach rect $rects { - set b [odb::dbBlockage_create $block \ - [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] - $b setSoft + set b [odb::dbBlockage_create $block \ + [$rect xMin] [$rect yMin] [$rect xMax] [$rect yMax]] + $b setSoft } } - diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl index 68f36e84a5..14f8f06e7a 100644 --- a/flow/scripts/read_liberty.tcl +++ b/flow/scripts/read_liberty.tcl @@ -1,18 +1,11 @@ -# To remove [WARNING STA-1212] from the logs for ASAP7. -# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz line 13178, timing group from output port. -# Added following suppress_message -if {[env_var_equals PLATFORM asap7]} { - suppress_message STA 1212 -} - #Read Liberty -if {[env_var_exists_and_non_empty CORNERS]} { +if { [env_var_exists_and_non_empty CORNERS] } { # corners define_corners {*}$::env(CORNERS) foreach corner $::env(CORNERS) { set LIBKEY "[string toupper $corner]_LIB_FILES" foreach libFile $::env($LIBKEY) { - read_liberty -corner $corner $libFile + log_cmd read_liberty -corner $corner $libFile } unset LIBKEY } @@ -20,10 +13,6 @@ if {[env_var_exists_and_non_empty CORNERS]} { } else { ## no corner foreach libFile $::env(LIB_FILES) { - read_liberty $libFile + log_cmd read_liberty $libFile } } - -if {[env_var_equals PLATFORM asap7]} { - unsuppress_message STA 1212 -} diff --git a/flow/scripts/read_macro_placement.tcl b/flow/scripts/read_macro_placement.tcl index 68c08231a4..bc643c7734 100644 --- a/flow/scripts/read_macro_placement.tcl +++ b/flow/scripts/read_macro_placement.tcl @@ -1,19 +1,19 @@ -proc read_macro_placement {macro_placement_file} { +proc read_macro_placement { macro_placement_file } { set block [ord::get_db_block] set units [$block getDefUnits] set ch [open $macro_placement_file] - while {![eof $ch]} { + while { ![eof $ch] } { set line [gets $ch] - if {[llength $line] == 0} {continue} + if { [llength $line] == 0 } { continue } set inst_name [lindex $line 0] set orientation [lindex $line 1] set x [expr round([lindex $line 2] * $units)] set y [expr round([lindex $line 3] * $units)] - if {[set inst [$block findInst $inst_name]] == "NULL"} { + if { [set inst [$block findInst $inst_name]] == "NULL" } { error "Cannot find instance $inst_name" } diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl index d0af3e97af..645cdbcb67 100644 --- a/flow/scripts/report_metrics.tcl +++ b/flow/scripts/report_metrics.tcl @@ -1,13 +1,13 @@ proc report_puts { out } { - upvar 1 when when - upvar 1 filename filename - set fileId [open $filename a] - puts $fileId $out - close $fileId + upvar 1 when when + upvar 1 filename filename + set fileId [open $filename a] + puts $fileId $out + close $fileId } -proc report_metrics { stage when {include_erc true} {include_clock_skew true} } { - if {[env_var_equals SKIP_REPORT_METRICS 1]} { +proc report_metrics { stage when { include_erc true } { include_clock_skew true } } { + if { [env_var_equals SKIP_REPORT_METRICS 1] } { return } puts "Report metrics stage $stage, $when..." @@ -18,7 +18,8 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "$when report_tns" report_puts "--------------------------------------------------------------------------" report_tns >> $filename - report_tns_metric >> $filename + report_tns_metric + report_tns_metric -hold report_puts "\n==========================================================================" report_puts "$when report_wns" @@ -29,33 +30,43 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "$when report_worst_slack" report_puts "--------------------------------------------------------------------------" report_worst_slack >> $filename - report_worst_slack_metric >> $filename + report_worst_slack_metric + report_worst_slack_metric -hold + + report_puts "\n==========================================================================" + report_puts "$when report_clock_min_period" + report_puts "--------------------------------------------------------------------------" + report_clock_min_period -include_port_paths >> $filename + report_fmax_metric - if {$include_clock_skew && $::env(REPORT_CLOCK_SKEW)} { + if { $include_clock_skew && $::env(REPORT_CLOCK_SKEW) } { report_puts "\n==========================================================================" report_puts "$when report_clock_skew" report_puts "--------------------------------------------------------------------------" report_clock_skew >> $filename - report_clock_skew_metric >> $filename - report_clock_skew_metric -hold >> $filename + report_clock_skew_metric + report_clock_skew_metric -hold } report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay min" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded >> $filename + report_checks -path_delay min -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -path_delay max" report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded >> $filename + report_checks -path_delay max -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename report_puts "\n==========================================================================" report_puts "$when report_checks -unconstrained" report_puts "--------------------------------------------------------------------------" - report_checks -unconstrained -fields {slew cap input nets fanout} -format full_clock_expanded >> $filename + report_checks -unconstrained -fields {slew cap input net fanout} \ + -format full_clock_expanded >> $filename - if {$include_erc} { + if { $include_erc } { report_puts "\n==========================================================================" report_puts "$when report_check_types -max_slew -max_cap -max_fanout -violators" report_puts "--------------------------------------------------------------------------" @@ -73,7 +84,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_slew_check_limit]" - if {[sta::max_slew_check_limit] < 1e30} { + if { [sta::max_slew_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_slew_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -90,7 +101,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_fanout_check_limit]" - if {[sta::max_fanout_check_limit] < 1e30} { + if { [sta::max_fanout_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_fanout_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -107,7 +118,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "--------------------------------------------------------------------------" report_puts "[sta::max_capacitance_check_limit]" - if {[sta::max_capacitance_check_limit] < 1e30} { + if { [sta::max_capacitance_check_limit] < 1e30 } { report_puts "\n==========================================================================" report_puts "$when max_capacitance_check_slack_limit" report_puts "--------------------------------------------------------------------------" @@ -140,7 +151,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "hold violation count [sta::endpoint_violation_count min]" set critical_path [lindex [find_timing_paths -sort_by_slack] 0] - if {$critical_path != ""} { + if { $critical_path != "" } { set path_delay [sta::format_time [[$critical_path path] arrival] 4] set path_slack [sta::format_time [[$critical_path path] slack] 4] } else { @@ -148,52 +159,58 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } set path_slack 0 } - if { [llength [all_registers]] != 0} { - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay max reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - report_puts "\n==========================================================================" - report_puts "$when report_checks -path_delay min reg to reg" - report_puts "--------------------------------------------------------------------------" - report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename - - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - } else { - set target_clock_latency_max 0 - } - + if { [llength [all_registers]] != 0 } { + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay max reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay max -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename + report_puts "\n==========================================================================" + report_puts "$when report_checks -path_delay min reg to reg" + report_puts "--------------------------------------------------------------------------" + report_checks -path_delay min -from [all_registers] -to [all_registers] \ + -format full_clock_expanded >> $filename + + set inp_to_reg_critical_path \ + [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_max \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + } else { + set target_clock_latency_max 0 + } + + + set inp_to_reg_critical_path [lindex \ + [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] + if { $inp_to_reg_critical_path != "" } { + set target_clock_latency_min \ + [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] + set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] + } else { + set target_clock_latency_min 0 + set source_clock_latency 0 + } - set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0] - if {$inp_to_reg_critical_path != ""} { - set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4] - set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4] - } else { - set target_clock_latency_min 0 - set source_clock_latency 0 - } - - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency max path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_max" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency max path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_max" - report_puts "\n==========================================================================" - report_puts "$when critical path target clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$target_clock_latency_min" + report_puts "\n==========================================================================" + report_puts "$when critical path target clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$target_clock_latency_min" - report_puts "\n==========================================================================" - report_puts "$when critical path source clock latency min path" - report_puts "--------------------------------------------------------------------------" - report_puts "$source_clock_latency" + report_puts "\n==========================================================================" + report_puts "$when critical path source clock latency min path" + report_puts "--------------------------------------------------------------------------" + report_puts "$source_clock_latency" } else { - puts "No registers in design" + puts "No registers in design" } # end if all_registers - + report_puts "\n==========================================================================" report_puts "$when critical path delay" report_puts "--------------------------------------------------------------------------" @@ -213,16 +230,16 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} } report_puts "\n==========================================================================" report_puts "$when report_power" report_puts "--------------------------------------------------------------------------" - if {[env_var_exists_and_non_empty CORNERS]} { + if { [env_var_exists_and_non_empty CORNERS] } { foreach corner $::env(CORNERS) { report_puts "Corner: $corner" report_power -corner $corner >> $filename - report_power_metric -corner $corner >> $filename + report_power_metric -corner $corner } unset corner } else { report_power >> $filename - report_power_metric >> $filename + report_power_metric } # TODO these only work to stdout, whereas we want to append to the $filename diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl index cb38355043..50276a85ec 100644 --- a/flow/scripts/resize.tcl +++ b/flow/scripts/resize.tcl @@ -10,38 +10,15 @@ set pin_count_before [sta::network_leaf_pin_count] set_dont_use $::env(DONT_USE_CELLS) -# Do not buffer chip-level designs -# by default, IO ports will be buffered -# to not buffer IO ports, set environment variable -# DONT_BUFFER_PORT = 1 -if { ![env_var_exists_and_non_empty FOOTPRINT] } { - if { ![env_var_equals DONT_BUFFER_PORTS 1] } { - puts "Perform port buffering..." - buffer_ports - } +if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } { + log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO) } -repair_design_helper - -if { [env_var_exists_and_non_empty TIE_SEPARATION] } { - set tie_separation $env(TIE_SEPARATION) -} else { - set tie_separation 0 +if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } { + replace_arith_modules } -# Repair tie lo fanout -puts "Repair tie lo fanout..." -set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0] -set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]] -set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tielo_pin - -# Repair tie hi fanout -puts "Repair tie hi fanout..." -set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0] -set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]] -set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1] -repair_tie_fanout -separation $tie_separation $tiehi_pin +repair_design_helper # hold violations are not repaired until after CTS diff --git a/flow/scripts/save_images.tcl b/flow/scripts/save_images.tcl index a3a460599f..5dec935009 100644 --- a/flow/scripts/save_images.tcl +++ b/flow/scripts/save_images.tcl @@ -7,37 +7,41 @@ set height [ord::dbu_to_microns $height] set resolution [expr $height / 1000] set markerdb [[ord::get_db_block] findMarkerCategory DRC] -if {$markerdb != "NULL" && [$markerdb getMarkerCount] > 0} { +if { $markerdb != "NULL" && [$markerdb getMarkerCount] > 0 } { gui::select_marker_category $markerdb } - + +gui::clear_highlights -1 gui::clear_selections +gui::fit + # Setup initial visibility to avoid any previous settings gui::set_display_controls "*" visible false gui::set_display_controls "Layers/*" visible true gui::set_display_controls "Nets/*" visible true -gui::set_display_controls "Instances/*" visible false -gui::set_display_controls "Instances/StdCells/*" visible true -gui::set_display_controls "Instances/Macro" visible true -gui::set_display_controls "Instances/Pads/*" visible true -gui::set_display_controls "Instances/Physical/*" visible true -gui::set_display_controls "Shape Types/Pins" visible true -gui::set_display_controls "Shape Types/*/*" visible true -gui::set_display_controls "Misc/Instances/names" visible true +gui::set_display_controls "Instances/*" visible true +gui::set_display_controls "Shape Types/*" visible true +gui::set_display_controls "Misc/Instances/*" visible false +gui::set_display_controls "Misc/Instances/Pins" visible true +gui::set_display_controls "Misc/Instances/Blockages" visible true gui::set_display_controls "Misc/Scale bar" visible true gui::set_display_controls "Misc/Highlight selected" visible true gui::set_display_controls "Misc/Detailed view" visible true # The routing view +save_image -resolution $resolution $::env(REPORTS_DIR)/final_all.webp +gui::set_display_controls "Nets/Power" visible false +gui::set_display_controls "Nets/Ground" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_routing.webp # The placement view without routing -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/Physical/*" visible false +gui::set_display_controls "Misc/Instances/*" visible false save_image -resolution $resolution $::env(REPORTS_DIR)/final_placement.webp -if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { +if { [env_var_exists_and_non_empty PWR_NETS_VOLTAGES] } { gui::set_display_controls "Heat Maps/IR Drop" visible true gui::set_heatmap IRDrop Layer $::env(IR_DROP_LAYER) gui::set_heatmap IRDrop ShowLegend 1 @@ -46,43 +50,60 @@ if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} { } # The clock view: all clock nets and buffers -gui::set_display_controls "Layers/*" visible true +gui::set_display_controls "Shape Types/Routing/*" visible true gui::set_display_controls "Nets/*" visible false gui::set_display_controls "Nets/Clock" visible true gui::set_display_controls "Instances/*" visible false gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true +gui::set_display_controls "Instances/StdCells/Sequential" visible true +gui::set_display_controls "Instances/Macro" visible true select -name "clk*" -type Inst save_image -resolution $resolution $::env(REPORTS_DIR)/final_clocks.webp gui::clear_selections +gui::show_widget "Clock Tree Viewer" +foreach clock [get_clocks *] { + if { [llength [get_property $clock sources]] > 0 } { + set clock_name [get_name $clock] + save_clocktree_image -clock $clock_name \ + -width 1024 -height 1024 \ + $::env(REPORTS_DIR)/cts_$clock_name.webp + gui::select_clockviewer_clock $clock_name + save_image -resolution $resolution $::env(REPORTS_DIR)/cts_${clock_name}_layout.webp + } +} +gui::hide_widget "Clock Tree Viewer" + # The resizer view: all instances created by the resizer grouped -gui::set_display_controls "Layers/*" visible false +gui::set_display_controls "Nets/*" visible true +gui::set_display_controls "Nets/Power" visible false +gui::set_display_controls "Nets/Ground" visible false +gui::set_display_controls "Shape Types/Routing/*" visible false gui::set_display_controls "Instances/*" visible true gui::set_display_controls "Instances/Physical/*" visible false -select -name "hold*" -type Inst -highlight 0 ;# green -select -name "input*" -type Inst -highlight 1 ;# yellow +select -name "hold*" -type Inst -highlight 0 ;# green +select -name "input*" -type Inst -highlight 1 ;# yellow select -name "output*" -type Inst -highlight 1 -select -name "repeater*" -type Inst -highlight 3 ;# magenta +select -name "repeater*" -type Inst -highlight 3 ;# magenta select -name "fanout*" -type Inst -highlight 3 select -name "load_slew*" -type Inst -highlight 3 select -name "max_cap*" -type Inst -highlight 3 select -name "max_length*" -type Inst -highlight 3 select -name "wire*" -type Inst -highlight 3 -select -name "rebuffer*" -type Inst -highlight 4 ;# red -select -name "split*" -type Inst -highlight 5 ;# dark green +select -name "rebuffer*" -type Inst -highlight 4 ;# red +select -name "split*" -type Inst -highlight 5 ;# dark green save_image -resolution $resolution $::env(REPORTS_DIR)/final_resizer.webp -for {set i 0} {$i <= 5} {incr i} { - gui::clear_highlights $i -} + +gui::clear_highlights -1 gui::clear_selections -foreach clock [get_clocks *] { - if { [llength [get_property $clock sources]] > 0 } { - set clock_name [get_name $clock] - save_clocktree_image -clock $clock_name \ - $::env(REPORTS_DIR)/cts_$clock_name.webp - } -} +# The routing congestion view +gui::set_display_controls "Instances/*" visible true +gui::set_display_controls "Instances/Physical/*" visible false +gui::set_display_controls "Nets/*" visible false +gui::set_display_controls "Heat Maps/Routing Congestion" visible true + +save_image -resolution $resolution $::env(REPORTS_DIR)/final_congestion.webp gui::restore_display_controls diff --git a/flow/scripts/sta-synth.tcl b/flow/scripts/sta-synth.tcl deleted file mode 100644 index a51ba8ea91..0000000000 --- a/flow/scripts/sta-synth.tcl +++ /dev/null @@ -1,2 +0,0 @@ -source $::env(SCRIPTS_DIR)/load.tcl -load_design 1_synth.v 1_synth.sdc diff --git a/flow/scripts/synth.sh b/flow/scripts/synth.sh new file mode 100755 index 0000000000..71f8ed5fc3 --- /dev/null +++ b/flow/scripts/synth.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -u -eo pipefail +mkdir -p $RESULTS_DIR $LOG_DIR $REPORTS_DIR $OBJECTS_DIR +eval "$TIME_CMD $YOSYS_EXE $YOSYS_FLAGS -c $1" 2>&1 | tee $(realpath $2) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index 99eede38fb..5bc80e2195 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -1,37 +1,83 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl +read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil hierarchy -check -top $::env(DESIGN_NAME) -set ungroup_threshold 0 -if { $::env(MAX_UNGROUP_SIZE) > 0 } { - set ungroup_threshold $::env(MAX_UNGROUP_SIZE) - puts "Ungroup modules of size greater than $ungroup_threshold" -} - -set fp [open $::env(SYNTH_STATS) r] -while {[gets $fp line] != -1} { - set fields [split $line " "] - set area [lindex $fields 0] - set module_name [lindex $fields 1] - - if {[expr $area > $ungroup_threshold]} { - puts "Keeping module $module_name (area: $area)" - select -module $module_name - setattr -mod -set keep_hierarchy 1 - select -clear - } else { - puts "Flattening module $module_name (area: $area)" - } -} -close $fp - if { [env_var_equals SYNTH_GUT 1] } { # /deletes all cells at the top level, which will quickly optimize away # everything else, including macros. delete $::env(DESIGN_NAME)/c:* } -synthesize_check mem $::env(SYNTH_FULL_ARGS) +if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } { + foreach module $::env(SYNTH_KEEP_MODULES) { + select -module $module + setattr -mod -set keep_hierarchy 1 + select -clear + } +} + +if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } { + scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR) +} + +set synth_full_args [env_var_or_empty SYNTH_ARGS] +if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } { + set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)] +} else { + set synth_full_args [concat $synth_full_args \ + "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"] +} + +if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { + # Perform standard coarse-level synthesis script, flatten right away + synth -flatten -run :fine {*}$synth_full_args +} else { + # Perform standard coarse-level synthesis script, + # defer flattening until we have decided what hierarchy to keep + synth -run :fine + + if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } { + set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE) + puts "Keep modules above estimated size of $ungroup_threshold gate equivalents" + + convert_liberty_areas + keep_hierarchy -min_cost $ungroup_threshold + } else { + keep_hierarchy + } + + # Re-run coarse-level script, this time do pass -flatten + synth -flatten -run coarse:fine {*}$synth_full_args +} + +json -o $::env(RESULTS_DIR)/mem.json +# Run report and check here so as to fail early if this synthesis run is doomed +exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \ + --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json + +if { [env_var_exists_and_non_empty SYNTH_RETIME_MODULES] } { + select $::env(SYNTH_RETIME_MODULES) + opt -fast -full + memory_map + opt -full + techmap + abc -dff -script scripts/abc_retime.script + select -clear +} + +if { + [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] || + [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] +} { + source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl +} else { + synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args +} + +# Get rid of indigestibles +chformal -remove +delete t:\$print # rename registers to have the verilog register name in its name # of the form \regName$_DFF_P_. We should fix yosys to make it the reg name. @@ -42,7 +88,7 @@ renames -wire opt -purge # Technology mapping of adders -if {[env_var_exists_and_non_empty ADDER_MAP_FILE] && [file isfile $::env(ADDER_MAP_FILE)]} { +if { [env_var_exists_and_non_empty ADDER_MAP_FILE] } { # extract the full adders extract_fa # map full adders @@ -53,7 +99,7 @@ if {[env_var_exists_and_non_empty ADDER_MAP_FILE] && [file isfile $::env(ADDER_M } # Technology mapping of latches -if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} { +if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } { techmap -map $::env(LATCH_MAP_FILE) } @@ -64,19 +110,26 @@ foreach cell $::env(DONT_USE_CELLS) { # Technology mapping of flip-flops # dfflibmap only supports one liberty file -if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { +if { [env_var_exists_and_non_empty DFF_LIB_FILE] } { dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args } else { dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args } opt -puts "abc [join $abc_args " "]" -abc {*}$abc_args - # Replace undef values with defined constants setundef -zero +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { + log_cmd abc {*}$abc_args +} else { + scratchpad -set abc9.script scripts/abc_speed_gia_only.script + # crop out -script from arguments + set abc_args [lrange $abc_args 2 end] + log_cmd abc_new {*}$abc_args + delete {t:$specify*} +} + # Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..}) splitnets @@ -85,8 +138,8 @@ opt_clean -purge # Technology mapping of constant hi- and/or lo-drivers hilomap -singleton \ - -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ - -locell {*}$::env(TIELO_CELL_AND_PORT) + -hicell {*}$::env(TIEHI_CELL_AND_PORT) \ + -locell {*}$::env(TIELO_CELL_AND_PORT) # Insert buffer cells for pass through wires insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS) @@ -96,8 +149,18 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs +# check the design is composed exclusively of target cells, and check for other problems +if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } { + check -assert -mapped +} else { + # Wrapped operator synthesis leaves around $buf cells which `check -mapped` + # gets confused by, once Yosys#4931 is merged we can remove this branch and + # always run `check -assert -mapped` + check -assert +} + # Write synthesized design -write_verilog -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v +write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_2_yosys.v # One day a more sophisticated synthesis will write out a modified # .sdc file after synthesis. For now, just copy the input .sdc file, # making synthesis more consistent with other stages. diff --git a/flow/scripts/synth_canonicalize.tcl b/flow/scripts/synth_canonicalize.tcl index f41017c67f..f7d4c44657 100644 --- a/flow/scripts/synth_canonicalize.tcl +++ b/flow/scripts/synth_canonicalize.tcl @@ -1,6 +1,16 @@ source $::env(SCRIPTS_DIR)/synth_preamble.tcl +read_design_sources + +dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] { + # Apply toplevel parameters + chparam -set $key $value $::env(DESIGN_NAME) +} + hierarchy -check -top $::env(DESIGN_NAME) + +source_env_var_if_exists SYNTH_CANONICALIZE_TCL + # Get rid of unused modules opt_clean -purge # The hash of this file will not change if files not part of synthesis do not change -write_rtlil $::env(RESULTS_DIR)/1_synth.rtlil +write_rtlil $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil diff --git a/flow/scripts/synth_metrics.tcl b/flow/scripts/synth_metrics.tcl index f24a05e80e..d2fe0ab500 100644 --- a/flow/scripts/synth_metrics.tcl +++ b/flow/scripts/synth_metrics.tcl @@ -1,5 +1,5 @@ utl::set_metrics_stage "synth__{}" source $::env(SCRIPTS_DIR)/load.tcl -load_design 1_1_yosys.v 1_synth.sdc +load_design 1_2_yosys.v 1_synth.sdc report_metrics 1 "Post synthesis" false false diff --git a/flow/scripts/synth_odb.tcl b/flow/scripts/synth_odb.tcl new file mode 100644 index 0000000000..8b7af86e0f --- /dev/null +++ b/flow/scripts/synth_odb.tcl @@ -0,0 +1,16 @@ +utl::set_metrics_stage "floorplan__{}" +source $::env(SCRIPTS_DIR)/load.tcl +erase_non_stage_variables synth +load_design 1_synth.v 1_synth.sdc + +write_db $::env(RESULTS_DIR)/1_3_synth.odb +# Canonicalize 1_synth.sdc. The original SDC_FILE provided by +# the user could have dependencies, such as sourcing util.tcl, +# which are read in here and a canonicalized version is written +# out by OpenSTA that has no dependencies. +write_sdc -no_timestamp $::env(RESULTS_DIR)/1_3_synth.sdc + +# Final output of the synthesis stage, the other files are written out for +# consistency and logging of .odb hashes +exec cp $::env(RESULTS_DIR)/1_3_synth.sdc $::env(RESULTS_DIR)/1_synth.sdc +exec cp $::env(RESULTS_DIR)/1_3_synth.odb $::env(RESULTS_DIR)/1_synth.odb diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 89a11db660..9e044df07d 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -3,67 +3,90 @@ yosys -import source $::env(SCRIPTS_DIR)/util.tcl erase_non_stage_variables synth -if {[env_var_exists_and_non_empty CACHED_NETLIST]} { - log_cmd exec cp $::env(CACHED_NETLIST) $::env(RESULTS_DIR)/1_1_yosys.v - log_cmd exec cp $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc - if {[env_var_exists_and_non_empty CACHED_REPORTS]} { - log_cmd exec cp {*}$::env(CACHED_REPORTS) $::env(REPORTS_DIR)/. +# If using a cached, gate level netlist, then copy over to the results dir with +# preserve timestamps flag set. If you don't, subsequent runs will cause the +# floorplan step to be re-executed. +if { [env_var_exists_and_non_empty SYNTH_NETLIST_FILES] } { + if { [llength $::env(SYNTH_NETLIST_FILES)] == 1 } { + log_cmd exec cp -p $::env(SYNTH_NETLIST_FILES) $::env(RESULTS_DIR)/1_2_yosys.v + } else { + # The date should be the most recent date of the files, but to + # keep things simple we just use the creation date + log_cmd exec cat {*}$::env(SYNTH_NETLIST_FILES) > $::env(RESULTS_DIR)/1_2_yosys.v } - exit -} - -# Setup verilog include directories -set vIdirsArgs "" -if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} { - foreach dir $::env(VERILOG_INCLUDE_DIRS) { - lappend vIdirsArgs "-I$dir" + log_cmd exec cp -p $::env(SDC_FILE) $::env(RESULTS_DIR)/1_synth.sdc + if { [env_var_exists_and_non_empty CACHED_REPORTS] } { + log_cmd exec cp -p {*}$::env(CACHED_REPORTS) $::env(REPORTS_DIR)/. } - set vIdirsArgs [join $vIdirsArgs] + exit } - -# Read verilog files -foreach file $::env(VERILOG_FILES) { - if {[file extension $file] == ".rtlil"} { - read_rtlil $file - } elseif {[file extension $file] == ".json"} { +proc read_checkpoint { file } { + # We are reading a Yosys checkpoint + if { [file extension $file] == ".json" } { read_json $file } else { - read_verilog -defer -sv {*}$vIdirsArgs $file + read_rtlil $file } } +proc read_design_sources { } { + # We are reading Verilog sources + source $::env(SCRIPTS_DIR)/synth_stdcells.tcl + + # Setup verilog include directories + set vIdirsArgs "" + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + foreach dir $::env(VERILOG_INCLUDE_DIRS) { + lappend vIdirsArgs "-I$dir" + } + set vIdirsArgs [join $vIdirsArgs] + } - - -# Read standard cells and macros as blackbox inputs -# These libs have their dont_use properties set accordingly -read_liberty -lib {*}$::env(DONT_USE_LIBS) - -# Apply toplevel parameters (if exist) -if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} { - dict for {key value} $::env(VERILOG_TOP_PARAMS) { - chparam -set $key $value $::env(DESIGN_NAME) + if { [env_var_equals SYNTH_HDL_FRONTEND slang] } { + # slang requires all files at once + plugin -i slang + yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \ + --ignore-assertions --no-implicit-memories --top $::env(DESIGN_NAME) \ + {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES] + # Workaround for yosys-slang#119 + setattr -unset init + } elseif { [env_var_equals SYNTH_HDL_FRONTEND verific] } { + if { [env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS] } { + verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS) + } + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { + verific -vlog-define {*}$::env(VERILOG_DEFINES) + } + verific -sv2012 {*}$::env(VERILOG_FILES) + verific -import -no-split-complex-ports $::env(DESIGN_NAME) + } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { + verilog_defaults -push + if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { + verilog_defaults -add {*}$::env(VERILOG_DEFINES) + } + foreach file $::env(VERILOG_FILES) { + read_verilog -defer -sv {*}$vIdirsArgs $file + } + verilog_defaults -pop + } else { + error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" } -} -# Read platform specific mapfile for OPENROAD_CLKGATE cells -if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} { - read_verilog -defer $::env(CLKGATE_MAP_FILE) -} + # Read platform specific mapfile for OPENROAD_CLKGATE cells + if { [env_var_exists_and_non_empty CLKGATE_MAP_FILE] } { + read_verilog -defer $::env(CLKGATE_MAP_FILE) + } -# Mark modules to keep from getting removed in flattening -if {[env_var_exists_and_non_empty PRESERVE_CELLS]} { - # Expand hierarchy since verilog was read in with -defer - hierarchy -check -top $::env(DESIGN_NAME) - foreach cell $::env(PRESERVE_CELLS) { - select -module $cell - setattr -mod -set keep_hierarchy 1 - select -clear + if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { + hierarchy -check -top $::env(DESIGN_NAME) + foreach m $::env(SYNTH_BLACKBOXES) { + blackbox $m + } } } -if {$::env(ABC_AREA)} { +if { $::env(ABC_AREA) } { puts "Using ABC area script." set abc_script $::env(SCRIPTS_DIR)/abc_area.script } else { @@ -74,22 +97,22 @@ if {$::env(ABC_AREA)} { # Technology mapping for cells # ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't set abc_args [list -script $abc_script \ - -liberty $::env(DONT_USE_SC_LIB) \ - -constr $::env(OBJECTS_DIR)/abc.constr] + -liberty $::env(DONT_USE_SC_LIB) \ + -constr $::env(OBJECTS_DIR)/abc.constr] # Exclude dont_use cells. This includes macros that are specified via # LIB_FILES and ADDITIONAL_LIBS that are included in LIB_FILES. -if {[env_var_exists_and_non_empty DONT_USE_CELLS]} { +if { [env_var_exists_and_non_empty DONT_USE_CELLS] } { foreach cell $::env(DONT_USE_CELLS) { lappend abc_args -dont_use $cell } } -if {[env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] && [file isfile $::env(SDC_FILE_CLOCK_PERIOD)]} { +if { [env_var_exists_and_non_empty SDC_FILE_CLOCK_PERIOD] } { puts "Extracting clock period from SDC file: $::env(SDC_FILE_CLOCK_PERIOD)" set fp [open $::env(SDC_FILE_CLOCK_PERIOD) r] set clock_period [string trim [read $fp]] - if {$clock_period != ""} { + if { $clock_period != "" } { puts "Setting clock period to $clock_period" lappend abc_args -D $clock_period } @@ -107,13 +130,31 @@ puts $constr "set_driving_cell $::env(ABC_DRIVER_CELL)" puts $constr "set_load $::env(ABC_LOAD_IN_FF)" close $constr -proc synthesize_check {report synth_args} { - # Generic synthesis - log_cmd synth -top $::env(DESIGN_NAME) -run :fine {*}$synth_args - json -o $::env(RESULTS_DIR)/$report.json - # Run report and check here so as to fail early if this synthesis run is doomed - exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/$report.json - synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_args - # Get rid of indigestibles - chformal -remove +proc convert_liberty_areas { } { + cellmatch -derive_luts =A:liberty_cell + # find a reference nand2 gate + set found_cell "" + set found_cell_area "" + # iterate over all cells with a nand2 signature + foreach cell [tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m] { + if { ![rtlil::has_attr -mod $cell area] } { + puts "Cell $cell missing area information" + continue + } + set area [rtlil::get_attr -string -mod $cell area] + if { $found_cell == "" || $area < $found_cell_area } { + set found_cell $cell + set found_cell_area $area + } + } + if { $found_cell == "" } { + error "reference nand2 cell not found" + } + + # convert the area on all Liberty cells to a gate number equivalent + foreach box [tee -q -s result.string select -list-mod =A:area =A:liberty_cell %i] { + set area [rtlil::get_attr -mod -string $box area] + set gate_eq [expr int($area / $found_cell_area)] + rtlil::set_attr -mod -uint $box gate_cost_equivalent $gate_eq + } } diff --git a/flow/scripts/synth_stats.tcl b/flow/scripts/synth_stats.tcl deleted file mode 100644 index 1cd73b49a5..0000000000 --- a/flow/scripts/synth_stats.tcl +++ /dev/null @@ -1,80 +0,0 @@ -# Gather statistics, if needed. Gathering the statistics is -# time consuming, because it requires a full synthesis run. -# -# The statistics is needed for SYNTH_HIERARCHICAL=1 flattening/keep -# module policy, and write to $::env(SYNTH_STATS) -source $::env(SCRIPTS_DIR)/util.tcl - -proc write_keep_hierarchy {} { - if { ![env_var_equals SYNTH_HIERARCHICAL 1] } { - set out_script_ptr [open $::env(SYNTH_STATS) w] - close $out_script_ptr - return - } - - source $::env(SCRIPTS_DIR)/synth_preamble.tcl - - synthesize_check mem_hierarchical {} - - if { [env_var_exists_and_non_empty ADDER_MAP_FILE] && [file isfile $::env(ADDER_MAP_FILE)] } { - techmap -map $::env(ADDER_MAP_FILE) - } - techmap - if {[env_var_exists_and_non_empty DFF_LIB_FILE]} { - dfflibmap -liberty $::env(DFF_LIB_FILE) - } else { - dfflibmap -liberty $::env(DONT_USE_SC_LIB) - } - puts "abc [join $abc_args " "]" - abc {*}$abc_args - - tee -o $::env(REPORTS_DIR)/synth_hier_stat.txt stat {*}$stat_libs - - hierarchy -check -top $::env(DESIGN_NAME) - set fptr [open $::env(REPORTS_DIR)/synth_hier_stat.txt r] - set contents [read -nonewline $fptr] - close $fptr - set split_cont [split $contents "\n"] - set hierarchy_section 0 - set module_list {} - foreach line $split_cont { - if {[regexp {=== design hierarchy ===} $line]} { - set hierarchy_section 1 - continue - } - if {[regexp { Number of wires.*} $line ]} { - set hierarchy_section 0 - continue - } - if { $hierarchy_section == 1 } { - if {[regexp { +(\S+) +.*} $line -> module_name]} { - lappend module_list $module_name - puts "Found module $module_name" - } - } - } - - set areas {} - foreach module $module_list { - tee -o $::env(OBJECTS_DIR)/synth_stat_temp_module.txt stat -top "$module" {*}$stat_libs - set fptr1 [open $::env(OBJECTS_DIR)/synth_stat_temp_module.txt r] - set contents1 [read -nonewline $fptr1] - close $fptr1 - set split_cont1 [split $contents1 "\n"] - foreach line $split_cont1 { - if {[regexp { +Chip area for top module '(\S+)': (.*)} $line -> module_name area]} { - lappend areas "$area $module_name" - } - } - file delete -force $::env(OBJECTS_DIR)/synth_stat_temp_module.txt - } - set areas [lsort -index 0 -real $areas] - - set out_script_ptr [open $::env(SYNTH_STATS) w] - foreach {line} $areas { - puts $out_script_ptr $line - } - close $out_script_ptr -} - -write_keep_hierarchy diff --git a/flow/scripts/synth_stdcells.tcl b/flow/scripts/synth_stdcells.tcl new file mode 100644 index 0000000000..a18ee84417 --- /dev/null +++ b/flow/scripts/synth_stdcells.tcl @@ -0,0 +1,5 @@ +# Read standard cells and macros as blackbox inputs +# These libs have their dont_use properties set accordingly +read_liberty -overwrite -setattr liberty_cell -lib {*}$::env(DONT_USE_LIBS) +read_liberty -overwrite -setattr liberty_cell \ + -unit_delay -wb -ignore_miss_func -ignore_buses {*}$::env(DONT_USE_LIBS) diff --git a/flow/scripts/synth_wrap_operators-booth.v b/flow/scripts/synth_wrap_operators-booth.v new file mode 100644 index 0000000000..c715f6b67d --- /dev/null +++ b/flow/scripts/synth_wrap_operators-booth.v @@ -0,0 +1,4 @@ +(* techmap_wrap = "booth" *) +(* techmap_celltype = "$macc" *) +module _70_macc; +endmodule diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl new file mode 100644 index 0000000000..a47dc60452 --- /dev/null +++ b/flow/scripts/synth_wrap_operators.tcl @@ -0,0 +1,76 @@ +set deferred_cells { + { + \$alu + ALU_{A_WIDTH}_{A_SIGNED}_{B_WIDTH}_{B_SIGNED}_{Y_WIDTH}{%unused} + {HAN_CARLSON -map +/choices/han-carlson.v} + {KOGGE_STONE -map +/choices/kogge-stone.v} + {SKLANSKY -map +/choices/sklansky.v} + {BRENT_KUNG} + } + { + \$macc + MACC_{CONFIG}_{Y_WIDTH}{%unused} + {BOOTH -max_iter 1 -map ../flow/scripts/synth_wrap_operators-booth.v} + {BASE -map +/choices/han-carlson.v} + } +} + +techmap {*}[join [lmap cell $deferred_cells { string cat "-dont_map [lindex $cell 0]" }] " "] + +foreach info $deferred_cells { + set type [lindex $info 0] + set naming_template [lindex $info 1] + # default architecture and its suffix + set default [lindex $info 2] + set default_suffix [lindex $default 0] + + log -header "Generating architectural options for $type" + log -push + + wrapcell \ + -setattr arithmetic_operator \ + -setattr copy_pending \ + -formatattr implements_operator $naming_template \ + -formatattr architecture $default_suffix \ + -formatattr source_cell $type \ + -name ${naming_template}_${default_suffix} \ + t:$type r:A_WIDTH>=10 r:Y_WIDTH>=14 %i %i + + # make per-architecture copies of the unmapped module + foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] { # tclint-disable-line line-length + setattr -mod -unset copy_pending $modname + + # iterate over non-default architectures + foreach arch [lrange $info 3 end] { + set suffix [lindex $arch 0] + set base [rtlil::get_attr -string -mod $modname implements_operator] + set newname ${base}_${suffix} + yosys copy $modname $newname + yosys setattr -mod -set architecture \"$suffix\" $newname + } + } + + # iterate over all architectures, both the default and non-default + foreach arch [lrange $info 2 end] { + set suffix [lindex $arch 0] + set extra_map_args [lrange $arch 1 end] + + # map all operator copies which were selected to have this architecture + techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i + + # booth isn't able to map all $macc configurations: catch if this is one + # of those and delete the option + delete A:source_cell=$type A:architecture=$suffix %i t:\$macc %m %i + } + + log -pop +} + +opt -fast -full +memory_map +opt -full +# Get rid of indigestibles +chformal -remove +setattr -mod -set abc9_script {"+&dch;&nf -R 5;"} A:arithmetic_operator +setattr -mod -set abc9_box 1 A:arithmetic_operator +techmap -map +/techmap.v -map +/choices/han-carlson.v diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl index 842a858ea1..eb00d11e23 100644 --- a/flow/scripts/tapcell.tcl +++ b/flow/scripts/tapcell.tcl @@ -1,12 +1,12 @@ source $::env(SCRIPTS_DIR)/load.tcl erase_non_stage_variables floorplan -load_design 2_3_floorplan_macro.odb 2_1_floorplan.sdc +load_design 2_2_floorplan_macro.odb 2_1_floorplan.sdc -if {[env_var_exists_and_non_empty TAPCELL_TCL]} { - source $::env(TAPCELL_TCL) +if { [env_var_exists_and_non_empty TAPCELL_TCL] } { + source $::env(TAPCELL_TCL) } else { - cut_rows + cut_rows } -write_db $::env(RESULTS_DIR)/2_4_floorplan_tapcell.odb +write_db $::env(RESULTS_DIR)/2_3_floorplan_tapcell.odb diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index 418353e920..b241cfbdce 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -1,49 +1,45 @@ -proc log_cmd {cmd args} { - puts "$cmd [join $args " "]" - $cmd {*}$args -} - -proc fast_route {} { - if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { - source $::env(FASTROUTE_TCL) - } else { - set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT) - set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) - if {[env_var_exists_and_non_empty MACRO_EXTENSION]} { - set_macro_extension $::env(MACRO_EXTENSION) - } +proc log_cmd { cmd args } { + # log the command, escape arguments with spaces + set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length + puts $log_cmd + set start [clock seconds] + set result [uplevel 1 [list $cmd {*}$args]] + set time [expr { [clock seconds] - $start }] + if { $time >= 5 } { + # Ideally we'd use a single line, but the command can output text + # and we don't want to mix it with the log, so output the time it took afterwards. + puts "Took $time seconds: $log_cmd" } + return $result } -proc repair_timing_helper { {hold_margin 1} } { - set additional_args "-verbose" +proc repair_timing_helper { args } { + set additional_args "$args -verbose" append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1 - if {$hold_margin || $::env(HOLD_SLACK_MARGIN) < 0} { + if { $::env(HOLD_SLACK_MARGIN) < 0 } { append_env_var additional_args HOLD_SLACK_MARGIN -hold_margin 1 } + append_env_var additional_args SETUP_MOVE_SEQUENCE -sequence 1 append_env_var additional_args TNS_END_PERCENT -repair_tns 1 append_env_var additional_args SKIP_PIN_SWAP -skip_pin_swap 0 append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0 append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0 append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0 append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 - puts "repair_timing [join $additional_args " "]" - repair_timing {*}$additional_args + log_cmd repair_timing {*}$additional_args } -proc repair_design_helper {} { +proc repair_design_helper { } { puts "Perform buffer insertion and gate resizing..." - set additional_args "" + set additional_args "-verbose" append_env_var additional_args CAP_MARGIN -cap_margin 1 append_env_var additional_args SLEW_MARGIN -slew_margin 1 append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 - puts "repair_design [join $additional_args " "]" - - repair_design {*}$additional_args + log_cmd repair_design {*}$additional_args } -proc recover_power {} { +proc recover_power_helper { } { if { $::env(RECOVER_POWER) == 0 } { return } @@ -52,29 +48,29 @@ proc recover_power {} { report_tns report_wns report_power - set additional_args "" + set additional_args "-verbose" append_env_var additional_args RECOVER_POWER -recover_power 1 append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0 - repair_timing {*}$additional_args + log_cmd repair_timing {*}$additional_args report_tns report_wns report_power } -proc extract_stage {input_file} { - if {![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2]} { - puts "ERROR: Could not determine design stage from $input_file" +proc extract_stage { input_file } { + if { ![regexp {/([0-9])_(([0-9])_)?} $input_file match num1 _ num2] } { + puts "Error: Could not determine design stage from $input_file" exit 1 } lappend number_groups $num1 - if {$num2!=""} { - lappend number_groups $num2 + if { $num2 != "" } { + lappend number_groups $num2 } else { lappend number_groups "0" } } -proc find_sdc_file {input_file} { +proc find_sdc_file { input_file } { # canonicalize input file, sometimes it is called with an input # file relative to $::env(RESULTS_DIR), other times with # an absolute path @@ -88,11 +84,12 @@ proc find_sdc_file {input_file} { set sdc_file "" set exact_sdc [string map {.odb .sdc} $input_file] - set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] + set sdc_files \ + [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"] set sdc_files [lsort -decreasing -dictionary $sdc_files] - set sdc_files [lmap file $sdc_files {file normalize $file}] + set sdc_files [lmap file $sdc_files { file normalize $file }] foreach name $sdc_files { - if {[lindex [lsort -decreasing -dictionary [list $name $exact_sdc] ] 0] == $exact_sdc} { + if { [lindex [lsort -decreasing -dictionary [list $name $exact_sdc]] 0] == $exact_sdc } { set sdc_file $name break } @@ -100,26 +97,36 @@ proc find_sdc_file {input_file} { return [list $design_stage $sdc_file] } -proc env_var_equals {env_var value} { - return [expr {[info exists ::env($env_var)] && $::env($env_var) == $value}] +proc env_var_equals { env_var value } { + return [expr { [info exists ::env($env_var)] && $::env($env_var) == $value }] } -proc env_var_exists_and_non_empty {env_var} { - return [expr {[info exists ::env($env_var)] && ![string equal $::env($env_var) ""]}] +proc env_var_exists_and_non_empty { env_var } { + return [expr { [info exists ::env($env_var)] && ![string equal $::env($env_var) ""] }] } -proc append_env_var {list_name var_name prefix has_arg} { +proc append_env_var { list_name var_name prefix has_arg } { upvar $list_name list - if {(!$has_arg && [env_var_equals $var_name 1]) || - ($has_arg && [env_var_exists_and_non_empty $var_name])} { + if { + (!$has_arg && [env_var_equals $var_name 1]) || + ($has_arg && [env_var_exists_and_non_empty $var_name]) + } { lappend list $prefix - if {$has_arg} { + if { $has_arg } { lappend list $::env($var_name) } } } -proc find_macros {} { +# Non-empty defaults should go into variables.yaml, generally +proc env_var_or_empty { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { + return $::env($env_var) + } + return "" +} + +proc find_macros { } { set macros "" set db [ord::get_db] @@ -135,16 +142,16 @@ proc find_macros {} { return $macros } -proc erase_non_stage_variables {stage_name} { +proc erase_non_stage_variables { stage_name } { # "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of # variables to erase. - # + # # Tcl yaml package can't be imported in the sta/openroad environment: - # + # # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875 set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name] foreach var $variables { - if {[info exists ::env($var)]} { + if { [info exists ::env($var)] } { unset ::env($var) } } @@ -152,19 +159,30 @@ proc erase_non_stage_variables {stage_name} { set global_route_congestion_report $::env(REPORTS_DIR)/congestion.rpt -proc place_density_with_lb_addon {} { - if {[env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON]} { +proc place_density_with_lb_addon { } { + if { [env_var_exists_and_non_empty PLACE_DENSITY_LB_ADDON] } { # check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON set place_density_lb [gpl::get_global_placement_uniform_density \ - -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ - -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] - set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] - if {$place_density > 1.0} { - utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99." + -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \ + -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] + set place_density \ + [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01] + if { $place_density > 1.0 } { + utl::error FLW 24 \ + "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = \ + $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of \ + PLACE_DENSITY_LB_ADDON is between 0 and 0.99." } - puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" + puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON \ + $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb" } else { set place_density $::env(PLACE_DENSITY) } return $place_density } + +proc source_env_var_if_exists { env_var } { + if { [env_var_exists_and_non_empty $env_var] } { + log_cmd source $::env($env_var) + } +} diff --git a/flow/scripts/variables.mk b/flow/scripts/variables.mk new file mode 100644 index 0000000000..6cfd19517d --- /dev/null +++ b/flow/scripts/variables.mk @@ -0,0 +1,229 @@ +# Sets up ORFS variables using make variable support, relying +# on makefile features such as defaults, forward references, +# lazy evaluation, conditional code, include statements, +# etc. + +export DESIGN_NICKNAME?=$(DESIGN_NAME) + +#------------------------------------------------------------------------------- +# Setup variables to point to other location for the following sub directory +# - designs - default is under current directory +# - platforms - default is under current directory +# - utils, scripts, test - default is under current directory +export DESIGN_HOME ?= $(FLOW_HOME)/designs +export PLATFORM_HOME ?= $(FLOW_HOME)/platforms + +export UTILS_DIR ?= $(FLOW_HOME)/util +export SCRIPTS_DIR ?= $(FLOW_HOME)/scripts +export TEST_DIR ?= $(FLOW_HOME)/test + +PUBLIC=nangate45 sky130hd sky130hs asap7 ihp-sg13g2 gf180 + +ifeq ($(origin PLATFORM), undefined) + $(error PLATFORM variable not set.) +endif +ifeq ($(origin DESIGN_NAME), undefined) + $(error DESIGN_NAME variable not set.) +endif + +ifneq ($(PLATFORM_DIR),) +else ifneq ($(wildcard $(PLATFORM_HOME)/$(PLATFORM)),) + export PLATFORM_DIR = $(PLATFORM_HOME)/$(PLATFORM) +else ifneq ($(findstring $(PLATFORM),$(PUBLIC)),) + export PLATFORM_DIR = ./platforms/$(PLATFORM) +else ifneq ($(wildcard ../../$(PLATFORM)),) + export PLATFORM_DIR = ../../$(PLATFORM) +else + $(error [ERROR][FLOW] Platform '$(PLATFORM)' not found.) +endif + +include $(PLATFORM_DIR)/config.mk + +# __SPACE__ is a workaround for whitespace hell in "foreach"; there +# is no way to escape space in defaults.py and get "foreach" to work. +$(foreach line,$(shell $(PYTHON_EXE) $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line)))) + +export LOG_DIR = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) +export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) +export REPORTS_DIR = $(WORK_HOME)/reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) +export RESULTS_DIR = $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT) + +#------------------------------------------------------------------------------- +ifeq (,$(strip $(NUM_CORES))) + # Linux (utility program) + NUM_CORES := $(shell nproc 2>/dev/null) + + ifeq (,$(strip $(NUM_CORES))) + # Linux (generic) + NUM_CORES := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null) + endif + ifeq (,$(strip $(NUM_CORES))) + # BSD (at least FreeBSD and Mac OSX) + NUM_CORES := $(shell sysctl -n hw.ncpu 2>/dev/null) + endif + ifeq (,$(strip $(NUM_CORES))) + # Fallback + NUM_CORES := 1 + endif +endif +export NUM_CORES + +#------------------------------------------------------------------------------- +# setup all commands used within this flow +export PYTHON_EXE ?= $(shell command -v python3) + +export TIME_BIN ?= env time +TIME_CMD = $(TIME_BIN) -f 'Elapsed time: %E[h:]min:sec. CPU time: user %U sys %S (%P). Peak memory: %MKB.' +TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null) +ifeq (,$(strip $(TIME_TEST))) + TIME_CMD = $(TIME_BIN) +endif +export TIME_CMD + +# The following determine the executable location for each tool used by this flow. +# Priority is given to +# 1 user explicit set with variable in Makefile or command line, for instance setting OPENROAD_EXE +# 2 either +# 2.1 if in Nix shell: openroad, yosys from the environment +# 2.2 ORFS compiled tools: openroad, yosys +ifneq (${IN_NIX_SHELL},) + export OPENROAD_EXE ?= $(shell command -v openroad) +else + export OPENROAD_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/openroad) +endif +ifneq (${IN_NIX_SHELL},) + export OPENSTA_EXE ?= $(shell command -v sta) +else + export OPENSTA_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/OpenROAD/bin/sta) +endif + +export OPENROAD_ARGS = -no_init -threads $(NUM_CORES) $(OR_ARGS) +export OPENROAD_CMD = $(OPENROAD_EXE) -exit $(OPENROAD_ARGS) +export OPENROAD_NO_EXIT_CMD = $(OPENROAD_EXE) $(OPENROAD_ARGS) +export OPENROAD_GUI_CMD = $(OPENROAD_EXE) -gui $(OR_ARGS) + +ifneq (${IN_NIX_SHELL},) + YOSYS_EXE ?= $(shell command -v yosys) +else + YOSYS_EXE ?= $(abspath $(FLOW_HOME)/../tools/install/yosys/bin/yosys) +endif +export YOSYS_EXE + +# Use locally installed and built klayout if it exists, otherwise use klayout in path +KLAYOUT_DIR = $(abspath $(FLOW_HOME)/../tools/install/klayout/) +KLAYOUT_BIN_FROM_DIR = $(KLAYOUT_DIR)/klayout + +ifeq ($(wildcard $(KLAYOUT_BIN_FROM_DIR)), $(KLAYOUT_BIN_FROM_DIR)) +KLAYOUT_CMD ?= sh -c 'LD_LIBRARY_PATH=$(dir $(KLAYOUT_BIN_FROM_DIR)) $$0 "$$@"' $(KLAYOUT_BIN_FROM_DIR) +else +ifeq ($(KLAYOUT_CMD),) +KLAYOUT_CMD := $(shell command -v klayout) +endif +endif +KLAYOUT_FOUND = $(if $(KLAYOUT_CMD),,$(error KLayout not found in PATH)) + +ifneq ($(shell command -v stdbuf),) + STDBUF_CMD ?= stdbuf -o L +endif + +#------------------------------------------------------------------------------- +WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.lef=_mod.lef)) +WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib)) +export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS) +export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS) + +export DONT_USE_LIBS = $(patsubst %.lib.gz, %.lib, $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES)))) +export DONT_USE_SC_LIB ?= $(firstword $(DONT_USE_LIBS)) + +# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS +STREAM_SYSTEM ?= GDS +ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),) + export STREAM_SYSTEM_EXT := gds + GDSOAS_FILES = $(GDS_FILES) + ADDITIONAL_GDSOAS = $(ADDITIONAL_GDS) + SEAL_GDSOAS = $(SEAL_GDS) +else + export STREAM_SYSTEM_EXT := oas + GDSOAS_FILES = $(OAS_FILES) + ADDITIONAL_GDSOAS = $(ADDITIONAL_OAS) + SEAL_GDSOAS = $(SEAL_OAS) +endif +export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT))) + +# If we are running headless use offscreen rendering for save_image +ifeq ($(DISPLAY),) +export QT_QPA_PLATFORM ?= offscreen +endif + +# Create Macro wrappers (if necessary) +export WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg + +export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH) + +export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl +export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt + +export YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD) + +# Ubuntu 22.04 ships with older than 0.28.11, so support older versions +# for a while still. +export KLAYOUT_ENV_VAR_IN_PATH_VERSION = 0.28.11 +export KLAYOUT_VERSION := $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -v 2>/dev/null | grep 'KLayout' | cut -d ' ' -f2),) + +export KLAYOUT_ENV_VAR_IN_PATH = $(shell \ + if [ -z "$(KLAYOUT_VERSION)" ]; then \ + echo "not_found"; \ + elif [ "$$(echo -e "$(KLAYOUT_VERSION)\n$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" | sort -V | head -n1)" = "$(KLAYOUT_VERSION)" ] && [ "$(KLAYOUT_VERSION)" != "$(KLAYOUT_ENV_VAR_IN_PATH_VERSION)" ]; then \ + echo "invalid"; \ + else \ + echo "valid"; \ + fi) + +export GDS_FINAL_FILE = $(RESULTS_DIR)/6_final.$(STREAM_SYSTEM_EXT) +export RESULTS_ODB = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.odb))) +export RESULTS_DEF = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.def))) +export RESULTS_GDS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.gds))) +export RESULTS_OAS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.oas))) +export GDS_MERGED_FILE = $(RESULTS_DIR)/6_1_merged.$(STREAM_SYSTEM_EXT) + +define get_variables +$(foreach V, $(.VARIABLES),$(if $(filter-out $(1), $(origin $V)), $(if $(filter-out .% %QT_QPA_PLATFORM% %TIME_CMD% KLAYOUT% GENERATE_ABSTRACT_RULE% do-step% do-copy% OPEN_GUI% OPEN_GUI_SHORTCUT% SUB_MAKE% UNSET_VARS% export%, $(V)), $V$ ))) +endef + +export UNSET_VARIABLES_NAMES := $(call get_variables,command% line environment% default automatic) +export ISSUE_VARIABLES_NAMES := $(sort $(filter-out \n get_variables, $(call get_variables,environment% default automatic))) +# This is Makefile's way to define a macro that expands to a single newline. +define newline + + +endef +export ISSUE_VARIABLES := $(foreach V, $(ISSUE_VARIABLES_NAMES), $(if $($V),$V=$($V),$V='')$(newline)) +export COMMAND_LINE_ARGS := $(foreach V,$(.VARIABLES),$(if $(filter command% line, $(origin $V)),$(V))) + +# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file +ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) + ifneq ($(wildcard $(SDC_FILE)),) + export ABC_CLOCK_PERIOD_IN_PS := $(shell sed -nE "s/^set\s+clk_period\s+(\S+).*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1}') + endif +endif + +.PHONY: vars +vars: + mkdir -p $(OBJECTS_DIR) + $(UTILS_DIR)/generate-vars.sh $(OBJECTS_DIR)/vars + +.PHONY: print-% +# Print any variable, for instance: make print-DIE_AREA +print-%: + # HERE BE DRAGONS! + # + # We have to use /tmp. $(OBJECTS_DIR) may not exist + # at $(file) expansion time, which is before commands are run + # here, so we can't mkdir -p $(OBJECTS_DIR) either + # + # We have to use $(file ...) because we want to be able + # to print variables that contain newlines. + $(file >/tmp/print_tmp$$,$($*)) + @echo -n "$* = " + @cat /tmp/print_tmp$$ + @rm /tmp/print_tmp$$ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 0039bdbd42..ebcc0d2075 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -2,39 +2,32 @@ GENERATE_ARTIFACTS_ON_FAILURE: description: > For instance Bazel needs artifacts (.odb and .rpt files) on a failure to - allow the user to save hours on re-running the failed step locally, but - when working with a Makefile flow, it is more natural to fail the step - and leave the user to manually inspect the logs and artifacts directly via - the file system. - - Set to 1 to change the behavior to generate artifacts upon failure to - e.g. do a global route. The exit code will still be non-zero on all other + allow the user to save hours on re-running the failed step locally, but when + working with a Makefile flow, it is more natural to fail the step and leave + the user to manually inspect the logs and artifacts directly via the file + system. + Set to 1 to change the behavior to generate artifacts upon failure to e.g. + do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. - Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. - Detailed route will not proceed, if there is global routing congestion - - This allows build systems, such as bazel, to create artifacts for global - and detailed route, even if the operation had problems, without having - know about the semantics between global and detailed route. - - Considering that global and detailed route can run for a long time and - use a lot of memory, this allows inspecting results on a laptop for - a build that ran on a server. + This allows build systems, such as bazel, to create artifacts for global and + detailed route, even if the operation had problems, without having know + about the semantics between global and detailed route. + Considering that global and detailed route can run for a long time and use a + lot of memory, this allows inspecting results on a laptop for a build that + ran on a server. default: 0 - TNS_END_PERCENT: description: > - Default TNS_END_PERCENT value for post CTS timing repair. - Try fixing all violating endpoints by default (reduce to 5% for runtime). - - Specifies how many percent of violating paths to fix [0-100]. - Worst path will always be fixed. + Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all + violating endpoints by default (reduce to 5% for runtime). + Specifies how many percent of violating paths to fix [0-100]. Worst path + will always be fixed. default: 100 stages: - cts @@ -42,7 +35,29 @@ TNS_END_PERCENT: - grt ROUTING_LAYER_ADJUSTMENT: default: 0.5 - description: Default routing layer adjustment + description: > + Adjusts routing layer capacities to manage congestion and + improve detailed routing. High values ease detailed routing + but risk excessive detours and long global routing times, + while low values reduce global routing failure but can + complicate detailed routing. + The global routing running time normally reduces + dramatically (entirely design specific, but going from hours to + minutes has been observed) when the value is + low (such as 0.10). + Sometimes, global routing will succeed with lower values and + fail with higher values. Exploring results with different + values can help shed light on the problem. Start with + a too low value, such as 0.10, and bisect + to value that works by doing multiple global routing runs. + As a last resort, `make global_route_issue` and using + the tools/OpenROAD/etc/deltaDebug.py can be useful to debug + global routing errors. If there is something specific that is + impossible to route, such as a clock line over a macro, global + routing will terminate with DRC errors routes that could + have been routed were it not for the specific impossible routes. + deltaDebug.py should weed out the possible routes and leave + a minimal failing case that pinpoints the problem. stages: - place - grt @@ -75,10 +90,12 @@ EQUIVALENCE_CHECK: stages: - cts CORE_UTILIZATION: - description: > + description: | The core utilization percentage (0-100). stages: - floorplan + tunable: 1 + type: float CORE_AREA: description: > The core area specified as a list of lower-left and upper-right corners in @@ -86,11 +103,11 @@ CORE_AREA: (X1 Y1 X2 Y2). stages: - floorplan + tunable: 1 REPORT_CLOCK_SKEW: - description: - Report clock skew as part of reporting metrics, starting at CTS, - before which there is no clock skew. - + description: > + Report clock skew as part of reporting metrics, starting at CTS, before which + there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable. stages: - cts @@ -110,7 +127,7 @@ SKIP_REPORT_METRICS: - route - final PROCESS: - description: > + description: | Technology node or process in use. CORNER: description: > @@ -120,45 +137,89 @@ TECH_LEF: A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements. SC_LEF: - description: > + description: | Path to technology standard cell LEF file. GDS_FILES: - description: > + description: | Path to platform GDS files. LIB_FILES: description: > A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell. +PLATFORM_TCL: + description: | + Specifies a Tcl script with commands to run before loading design. DONT_USE_CELLS: - description: > + description: | Dont use cells eases pin access in detailed routing. SYNTH_GUT: description: > - Load design and remove all internal logic before doing synthesis. This - is useful when creating a mock .lef abstract that has a smaller area - than the amount of logic would allow. bazel-orfs uses this to mock - SRAMs, for instance. + Load design and remove all internal logic before doing synthesis. This is + useful when creating a mock .lef abstract that has a smaller area than the + amount of logic would allow. bazel-orfs uses this to mock SRAMs, for + instance. stages: - synth SYNTH_HIERARCHICAL: - description: > + description: | Enable to Synthesis hierarchically, otherwise considered flat synthesis. stages: - synth default: 0 -LATCH_MAP_FILE: +SYNTH_MEMORY_MAX_BITS: + description: > + Maximum number of bits for memory synthesis. + default: 4096 + stages: + - synth +SYNTH_HDL_FRONTEND: description: > + Select an alternative language frontend to ingest the design. Available option + is "slang". If the variable is empty, design is read with the Yosys read_verilog + command. + stages: + - synth +SYNTH_BLACKBOXES: + description: > + List of cells treated as a black box by Yosys. With Bazel, this can be used + to run synthesis in parallel for the large modules of the design. + stages: + - synth +SYNTH_NETLIST_FILES: + description: > + Skips synthesis and uses the supplied netlist files. If the netlist files + contains duplicate modules, which can happen when using hierarchical + synthesis on indvidual netlist files and combining here, + subsequent modules are silently ignored and only the first module is used. + stages: + - synth +SYNTH_CANONICALIZE_TCL: + description: > + Specifies a Tcl script with commands to run as part of the synth + canonicalize step. + stages: + - synth +SYNTH_RETIME_MODULES: + description: > + List of modules to apply retiming to. These modules must not get + dissolved and as such they should either be the top module or be included + in SYNTH_KEEP_MODULES. This is an experimental option and may cause adverse + effects. + stages: + - synth +LATCH_MAP_FILE: + description: | List of latches treated as a black box by Yosys. stages: - synth CLKGATE_MAP_FILE: - description: > + description: | List of cells for gating clock treated as a black box by Yosys. stages: - synth ADDER_MAP_FILE: - description: > + description: | List of adders treated as a black box by Yosys. stages: - synth @@ -168,15 +229,26 @@ TIEHI_CELL_AND_PORT: Netlist. stages: - synth - - place + - floorplan TIELO_CELL_AND_PORT: - description: > + description: | Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist. stages: - synth + - floorplan +TIE_SEPARATION: + description: | + Distance separating tie high/low instances from the load. + stages: + - floorplan + default: 0 +EARLY_SIZING_CAP_RATIO: + description: | + Ratio between the input pin capacitance and the output pin load during initial gate sizing. + stages: - place MIN_BUF_CELL_AND_PORTS: - description: > + description: | Used to insert a buffer cell to pass through wires. Used in synthesis. stages: - synth @@ -187,23 +259,40 @@ ABC_CLOCK_PERIOD_IN_PS: stages: - synth ABC_DRIVER_CELL: - description: > + description: | Default driver cell used during ABC synthesis. stages: - synth ABC_LOAD_IN_FF: - description: > + description: | During synthesis set_load value used. stages: - synth -MAX_UNGROUP_SIZE: +SYNTH_MINIMUM_KEEP_SIZE: description: > - For hierarchical synthesis, we ungroup modules of larger area than given by - this variable. The default value is > 0 platform specific. + For hierarchical synthesis, we keep modules of larger area than given by + this variable and flatten smaller modules. + The area unit used is the size of a basic nand2 gate from the + platform's standard cell library. The default value is platform specific. stages: - synth -FLOORPLAN_DEF: + default: 0 +SYNTH_WRAPPED_OPERATORS: description: > + Synthesize multiple architectural options for each arithmetic operator in the + design. These options are available for switching among in later stages of + the flow. + stages: + - synth +SWAP_ARITH_OPERATORS: + description: > + Improve timing QoR by swapping ALU and MULT arithmetic operators. + stages: + - synth + - floorplan + - place +FLOORPLAN_DEF: + description: | Use the DEF file to initialize floorplan. stages: - floorplan @@ -211,18 +300,18 @@ FLOORPLAN_DEF: REMOVE_ABC_BUFFERS: description: > Remove abc buffers from the netlist. If timing repair in floorplanning is - taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early - instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1. + taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early + instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1. stages: - floorplan deprecated: 1 PLACE_SITE: - description: > + description: | Placement site for core cells defined in the technology LEF file. stages: - floorplan TAPCELL_TCL: - description: > + description: | Path to Endcap and Welltie cells file. stages: - floorplan @@ -233,7 +322,7 @@ MACRO_PLACEMENT: stages: - floorplan MACRO_PLACEMENT_TCL: - description: > + description: | Specifies the path of a TCL file on how to place certain macros manually. stages: - floorplan @@ -243,16 +332,13 @@ MACRO_PLACE_HALO: placement. stages: - floorplan -MACRO_PLACE_CHANNEL: - description: > - Horizontal/vertical channel width between macros (microns). Used by - automatic macro placement. Imagine channel=10 and halo=5. Then macros must - be 10 apart but standard cells must be 5 away from a macro. - stages: - - floorplan MACRO_BLOCKAGE_HALO: description: > - Blockage width overridden from default calculation. + Distance beyond the edges of a macro that will also be covered by the + blockage generated for that macro. + Note that the default macro blockage halo comes from the largest of the + specified MACRO_PLACE_HALO x or y values. This variable overrides that + calculation. stages: - floorplan PDN_TCL: @@ -263,34 +349,32 @@ PDN_TCL: stages: - floorplan MAKE_TRACKS: - description: > + description: | Tcl file that defines add routing tracks to a floorplan. stages: - floorplan IO_CONSTRAINTS: - description: > + description: | File path to the IO constraints .tcl file. stages: - floorplan - place IO_PLACER_H: description: > - The metal layer on which to place the I/O pins horizontally (top and bottom + A list of metal layers on which the I/O pins are placed horizontally (top and bottom of the die). stages: - - floorplan - place IO_PLACER_V: description: > - The metal layer on which to place the I/O pins vertically (sides of the + A list of metal layers on which the I/O pins are placed vertically (sides of the die). stages: - - floorplan - place GUI_TIMING: description: > - Load timing information when opening GUI. For large designs, this can - be quite time consuming. Useful to disable when investigating non-timing + Load timing information when opening GUI. For large designs, this can be + quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc. default: 1 FILL_CELLS: @@ -300,7 +384,7 @@ FILL_CELLS: stages: - route TAP_CELL_NAME: - description: > + description: | Name of the cell to use in tap cell insertion. CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: description: > @@ -310,6 +394,8 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: - place - floorplan default: 0 + type: int + tunable: 1 CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability in detail @@ -319,17 +405,24 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT: - cts - grt default: 0 + type: int + tunable: 1 PLACE_PINS_ARGS: - description: > + description: | Arguments to place_pins stages: - place - - floorplan - default: "" PLACE_DENSITY: description: > - The desired placement density of cells. It reflects how spread the cells - would be on the core area. 1.0 = closely dense. 0.0 = widely spread. + The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. + + The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. + + If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. + + A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. + + The default is platform specific. stages: - floorplan - place @@ -337,30 +430,34 @@ PLACE_DENSITY_LB_ADDON: description: > Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists. + stages: + - floorplan + - place + tunable: 1 + type: float REPAIR_PDN_VIA_LAYER: - description: > + description: | Remove power grid vias which generate DRC violations after detailed routing. GLOBAL_PLACEMENT_ARGS: description: > Use additional tuning parameters during global placement other than default args defined in global_place.tcl. - default: "" ENABLE_DPO: - description: > + description: | Enable detail placement with improve_placement feature. default: 1 DPO_MAX_DISPLACEMENT: - description: > + description: | Specifies how far an instance can be moved when optimizing. default: 5 1 GPL_TIMING_DRIVEN: - description: > + description: | Specifies whether the placer should use timing driven placement. stages: - place default: 1 GPL_ROUTABILITY_DRIVEN: - description: > + description: | Specifies whether the placer should use routability driven placement. stages: - place @@ -374,41 +471,72 @@ SLEW_MARGIN: Specifies a slew margin when fixing max slew violations. This option allows you to overfix. CTS_ARGS: - description: > + description: | Override `clock_tree_synthesis` arguments. stages: - cts HOLD_SLACK_MARGIN: description: > Specifies a time margin for the slack when fixing hold violations. - This option allows you to overfix or underfix(negative value, terminate + This option allows you to overfix or underfix (negative value, terminate retiming before 0 or positive slack). - - Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan. - + floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0 (default hold slack margin). This avoids overrepair in floorplan for hold by default, but allows skipping hold repair using a negative HOLD_SLACK_MARGIN. - Exiting timing repair early is useful in exploration where - - the .sdc has a fixed clock period at designs target clock period and where - HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running + the .sdc has a fixed clock period at the design's target clock period and where + HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair (extremely long running times) when exploring different parameter settings. + When an ideal clock is used, that is before CTS, + a clock insertion delay of 0 is used in timing paths. This creates + a mismatch between macros that have a .lib file from after CTS, when + the clock is propagated. To mitigate this, OpenSTA will use subtract + the clock insertion delay of macros when calculating timing with ideal + clock. Provided that min_clock_tree_path + and max_clock_tree_path are in the .lib file, which is the case for + macros built with OpenROAD. This is less accurate than if OpenROAD had + created a placeholder clock tree for timing estimation purposes + prior to CTS. + There will inevitably be inaccuracies in the timing calculation prior + to CTS. Use a slack margin that is low enough, even negative, to + avoid overrepair. Inaccuracies in the timing prior to CTS can also + lead to underrepair, but there no obvious and simple way to avoid + underrapir in these cases. + Overrepair can lead to excessive runtimes in repair or too much buffering + being added, which can present itself as congestion of hold cells or + buffer cells. + Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration + when trying to find the minimum clock period for a design. + The SDC_FILE for a design can be quite complicated and instead of + modifying the clock period in the SDC_FILE, which can be non-trivial, + the clock period can be fixed at the target frequency and the + SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible + current minimum clock period. stages: - cts - floorplan - grt default: 0 SETUP_SLACK_MARGIN: - description: > + description: | Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). + See HOLD_SLACK_MARGIN for more details. stages: - cts - floorplan - grt default: 0 +SETUP_REPAIR_SEQUENCE: + description: | + Specifies the sequence of moves to do in repair_timing -setup. This should be a string + of move keywords separated by commas such as the default when not used: + "unbuffer,sizedown,sizeup,swap,buffer,clone,split". + stages: + - cts + - floorplan + - grt SKIP_GATE_CLONING: description: > Do not use gate cloning transform to fix timing violations (default: use @@ -446,7 +574,7 @@ SKIP_CTS_REPAIR_TIMING: stages: - cts MIN_ROUTING_LAYER: - description: > + description: | The lowest metal layer name to be used in routing. stages: - place @@ -454,7 +582,7 @@ MIN_ROUTING_LAYER: - route - final MAX_ROUTING_LAYER: - description: > + description: | The highest metal layer name to be used in routing. stages: - place @@ -462,12 +590,12 @@ MAX_ROUTING_LAYER: - route - final DETAILED_ROUTE_ARGS: - description: > + description: | Add additional arguments for debugging purposes during detail route. stages: - route MACRO_EXTENSION: - description: > + description: | Sets the number of GCells added to the blockages boundaries from macros. DETAILED_ROUTE_END_ITERATION: description: > @@ -476,51 +604,57 @@ DETAILED_ROUTE_END_ITERATION: stages: - route RCX_RULES: - description: > + description: | RC Extraction rules file path. SET_RC_TCL: - description: > + description: | Metal & Via RC definition file path. FILL_CONFIG: - description: > + description: | JSON rule file for metal fill during chip finishing. KLAYOUT_TECH_FILE: - description: > + description: | A mapping from LEF/DEF to GDS using the KLayout tool. IR_DROP_LAYER: - description: > + description: | Default metal layer to report IR drop. PLATFORM: required: true - description: > + description: | Specifies process design kit or technology node to be used. DESIGN_NAME: required: true - description: > + description: | The name of the top-level module of the design. VERILOG_FILES: required: true description: > - The path to the design Verilog files or JSON files providing a description - of modules (check `yosys -h write_json` for more details). + The path to the design Verilog/SystemVerilog files providing a description + of modules. + stages: + - synth +VERILOG_DEFINES: + description: > + Preprocessor defines passed to the language frontend. + Example: `-D HPDCACHE_ASSERT_OFF` stages: - synth SDC_FILE: required: true - description: > + description: | The path to design constraint (SDC) file. stages: - synth SDC_GUT: description: > - Load design and remove all internal logic before doing synthesis. This - is useful when creating a mock .lef abstract that has a smaller area - than the amount of logic would allow. bazel-orfs uses this to mock - SRAMs, for instance. + Load design and remove all internal logic before doing synthesis. This is + useful when creating a mock .lef abstract that has a smaller area than the + amount of logic would allow. bazel-orfs uses this to mock SRAMs, for + instance. stages: - synth ADDITIONAL_FILES: - description: > + description: | Additional files to be added to `make issue` archive. ADDITIONAL_LEFS: description: > @@ -531,12 +665,12 @@ ADDITIONAL_LIBS: Hardened macro library files listed here. The library information is immutable and used throughout all stages. Not stored in the .odb file. ADDITIONAL_GDS: - description: > + description: | Hardened macro GDS files listed here. stages: - final VERILOG_INCLUDE_DIRS: - description: > + description: | Specifies the include directories for the Verilog input files. stages: - synth @@ -546,18 +680,18 @@ DESIGN_NICKNAME: DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a different design. ABC_AREA: - description: > + description: | Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. stages: - synth default: 0 PWR_NETS_VOLTAGES: - description: > + description: | Used for IR Drop calculation. stages: - final GND_NETS_VOLTAGES: - description: > + description: | Used for IR Drop calculation. stages: - final @@ -566,23 +700,28 @@ BLOCKS: Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile. CDL_FILES: - description: > + description: | Insert additional Circuit Description Language (`.cdl`) netlist files. DFF_LIB_FILES: - description: > + description: | Technology mapping liberty files for flip-flops. DONT_USE_LIBS: - description: > + description: | Set liberty files as `dont_use`. -PRESERVE_CELLS: - description: > +SYNTH_KEEP_MODULES: + description: | Mark modules to keep from getting removed in flattening. + stages: + - synth SYNTH_ARGS: - description: > + description: | Optional synthesis variables for yosys. - default: -flatten +SYNTH_HIER_SEPARATOR: + description: | + Separator used for the synthesis flatten stage. + default: . VERILOG_TOP_PARAMS: - description: > + description: | Apply toplevel params (if exist). stages: - synth @@ -592,6 +731,9 @@ CORE_ASPECT_RATIO: `CORE_UTILIZATION` is undefined. stages: - floorplan + default: 1.0 + tunable: 1 + type: float CORE_MARGIN: description: > The margin between the core area and die area, specified in microns. @@ -601,6 +743,9 @@ CORE_MARGIN: is undefined. stages: - floorplan + default: 1.0 + tunable: 1 + type: float DIE_AREA: description: > The die area specified as a list of lower-left and upper-right corners in @@ -608,75 +753,89 @@ DIE_AREA: (X1 Y1 X2 Y2). stages: - floorplan -RESYNTH_AREA_RECOVER: - description: > - Enable re-synthesis for area reclaim. - stages: - - synth - default: 0 -RESYNTH_TIMING_RECOVER: - description: > - Enable re-synthesis for timing optimization. - stages: - - synth - default: 0 -MACRO_HALO_X: + tunable: 1 +MACRO_ROWS_HALO_X: description: > - Set macro halo for x-direction. Only available for ASAP7 PDK. + Horizontal distance between the edge of the macro and the beginning of the + rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks + design. stages: - floorplan -MACRO_HALO_Y: +MACRO_ROWS_HALO_Y: description: > - Set macro halo for y-direction. Only available for ASAP7 PDK. + Vertical distance between the edge of the macro and the beginning of the + rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks + design. stages: - floorplan MACRO_WRAPPERS: - description: > + description: | The wrapper file that replaces existing macros with their wrapped version. stages: - floorplan CTS_BUF_DISTANCE: - description: > + description: | Distance (in microns) between buffers. stages: - cts + tunable: 1 + type: float +CTS_BUF_LIST: + description: | + List of cells used to construct the clock tree. Overrides buffer inference. + stages: + - cts CTS_CLUSTER_DIAMETER: description: > Maximum diameter (in microns) of sink cluster. default: 20 stages: - cts + tunable: 1 + type: float CTS_CLUSTER_SIZE: description: > Maximum number of sinks per cluster. default: 50 stages: - cts + tunable: 1 + type: int +CTS_LIB_NAME: + description: | + Name of the Liberty library to use in selecting the clock buffers. + stages: + - cts CTS_SNAPSHOT: - description: > + description: | Creates ODB/SDC files prior to clock net and setup/hold repair. stages: - cts POST_CTS_TCL: - description: > + description: | Specifies a Tcl script with commands to run after CTS is completed. stages: - cts FASTROUTE_TCL: - description: > + description: | Specifies a Tcl script with commands to run before FastRoute. USE_FILL: description: > Whether to perform metal density filling. default: 0 SEAL_GDS: - description: > + description: | Seal macro to place around the design. ABSTRACT_SOURCE: - description: > + description: | Which .odb file to use to create abstract stages: - generate_abstract +PRE_GLOBAL_ROUTE_TCL: + description: | + Specifies a Tcl script with commands to run before global route. + stages: + - grt GLOBAL_ROUTE_ARGS: description: > Replaces default arguments for global route. @@ -814,3 +973,43 @@ RTLMP_ARGS: Overrides all other RTL macro placer arguments. stages: - floorplan +GDS_ALLOW_EMPTY: + description: > + Regular expression of module names of macros that have no .gds file + stages: + - final +RUN_SCRIPT: + description: > + Path to script to run from `make run`, python or tcl script detected by + .py or .tcl extension. +RUN_LOG_NAME_STEM: + description: > + Stem of the log file name, the log file will be named + `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`. + default: run +YOSYS_FLAGS: + description: > + Flags to pass to yosys. + stages: + - synth + default: -v 3 +FLOW_VARIANT: + description: > + Flow variant to use, used in the flow variant directory name. + default: base +RULES_JSON: + description: > + json files with the metrics baseline regression rules. + In the ORFS Makefile, this defaults to $DESIGN_DIR/rules-base.json, + but ORFS does not mandate the users source directory layout and + this can be placed elsewhere when the user sets up an ORFS + config.mk or from bazel-orfs. + stages: + - test +SKIP_DETAILED_ROUTE: + default: 0 + description: > + Skips detailed route. + stages: + - route + - final diff --git a/flow/scripts/view_cells.tcl b/flow/scripts/view_cells.tcl index d6bf433d9a..c7a4ca087c 100644 --- a/flow/scripts/view_cells.tcl +++ b/flow/scripts/view_cells.tcl @@ -2,7 +2,7 @@ read_lef $::env(TECH_LEF) read_lef $::env(SC_LEF) -if {[info exist ::env(ADDITIONAL_LEFS)]} { +if { [info exist ::env(ADDITIONAL_LEFS)] } { foreach lef $::env(ADDITIONAL_LEFS) { read_lef $lef } @@ -16,9 +16,9 @@ set block [odb::dbBlock_create $chip all_cells] # Get all the masters set masters {} foreach lib [$db getLibs] { - foreach master [$lib getMasters] { - lappend masters $master - } + foreach master [$lib getMasters] { + lappend masters $master + } } # Find the number of masters & the max width and height of any master @@ -26,9 +26,9 @@ set max_width 0 set max_height 0 set num_masters 0 foreach master $masters { - set max_width [expr max($max_width, [$master getWidth])] - set max_height [expr max($max_height, [$master getHeight])] - incr num_masters + set max_width [expr max($max_width, [$master getWidth])] + set max_height [expr max($max_height, [$master getHeight])] + incr num_masters } # The steps for laying out the cells @@ -42,15 +42,15 @@ set x_width [expr ceil(sqrt($num_masters * $y_step / $x_step))] set x 0 set y 0 foreach master $masters { - set inst [odb::dbInst_create $block $master [$master getName]] - $inst setPlacementStatus PLACED - $inst setLocation [expr $x * $x_step] [expr $y * $y_step] - - incr x - if {$x == $x_width} { - set x 0 - incr y - } + set inst [odb::dbInst_create $block $master [$master getName]] + $inst setPlacementStatus PLACED + $inst setLocation [expr $x * $x_step] [expr $y * $y_step] + + incr x + if { $x == $x_width } { + set x 0 + incr y + } } gui::design_created gui::fit diff --git a/flow/scripts/write_ref_sdc.tcl b/flow/scripts/write_ref_sdc.tcl index d28c20d9b4..60c6bb7658 100644 --- a/flow/scripts/write_ref_sdc.tcl +++ b/flow/scripts/write_ref_sdc.tcl @@ -19,13 +19,13 @@ if { [llength $clks] == 0 } { set ref_period [expr ($period - $slack) * (1.0 - $margin/100.0)] utl::info "FLW" 8 "Clock $clk_name period [format %.3f $ref_period]" utl::info "FLW" 9 "Clock $clk_name slack [format %.3f $slack]" - + set sources [$clk sources] # Redefine clock with updated period. create_clock -name $clk_name -period $ref_period $sources # Undo the set_propagated_clock so SDC at beginning of flow uses ideal clocks. unset_propagated_clock [all_clocks] - write_sdc -no_timestamp [file join $env(RESULTS_DIR) "updated_clks.sdc"] + write_sdc -no_timestamp [file join $::env(RESULTS_DIR) "updated_clks.sdc"] # Reset create_clock -name $clk_name -period $period $sources set_propagated_clock [all_clocks] @@ -37,4 +37,4 @@ if { [llength $clks] == 0 } { } } -utl::info "FLW" 11 "Path endpoint count [sta::endpoint_count]" +utl::info "FLW" 11 "Path endpoint path count [sta::endpoint_path_count]" diff --git a/flow/scripts/yosys_keep.tcl b/flow/scripts/yosys_keep.tcl new file mode 100644 index 0000000000..f28a730ed5 --- /dev/null +++ b/flow/scripts/yosys_keep.tcl @@ -0,0 +1,5 @@ +# Example script, tee list of modules with keep attribute to a +# report file +source $::env(SCRIPTS_DIR)/yosys_load.tcl + +tee -o $::env(REPORTS_DIR)/keep.txt ls A:keep_hierarchy=1 diff --git a/flow/scripts/yosys_load.tcl b/flow/scripts/yosys_load.tcl new file mode 100644 index 0000000000..2d6fe387f7 --- /dev/null +++ b/flow/scripts/yosys_load.tcl @@ -0,0 +1,6 @@ +# Load synthesis result +yosys -import + +source $::env(SCRIPTS_DIR)/synth_stdcells.tcl + +read_verilog $::env(RESULTS_DIR)/1_synth.v diff --git a/flow/test/core_tests.sh b/flow/test/core_tests.sh deleted file mode 100644 index 02a07b7396..0000000000 --- a/flow/test/core_tests.sh +++ /dev/null @@ -1,33 +0,0 @@ -test/test_helper.sh gcd nangate45 -test/test_helper.sh gcd tsmc65lp -test/test_helper.sh gcd gf14 -test/test_helper.sh dynamic_node nangate45 -test/test_helper.sh dynamic_node tsmc65lp -test/test_helper.sh aes nangate45 -test/test_helper.sh aes tsmc65lp -test/test_helper.sh aes gf14 -test/test_helper.sh vb tsmc65lp -test/test_helper.sh tinyRocket nangate45 -test/test_helper.sh tinyRocket tsmc65lp -test/test_helper.sh ibex tsmc65lp -test/test_helper.sh ibex nangate45 -test/test_helper.sh ibex gf14 -test/test_helper.sh jpeg nangate45 -test/test_helper.sh jpeg tsmc65lp -test/test_helper.sh jpeg gf14 -test/test_helper.sh bp_fe_top nangate45 -test/test_helper.sh bp_fe_top tsmc65lp -test/test_helper.sh swerv nangate45 -test/test_helper.sh swerv tsmc65lp -test/test_helper.sh swerv gf14 -test/test_helper.sh ariane tsmc65lp -test/test_helper.sh bp_be_top tsmc65lp -test/test_helper.sh bp_be_top nangate45 -test/test_helper.sh black_parrot nangate45 -test/test_helper.sh black_parrot tsmc65lp -test/test_helper.sh bp_multi_top tsmc65lp -test/test_helper.sh bp_multi_top nangate45 -test/test_helper.sh swerv_wrapper nangate45 -test/test_helper.sh swerv_wrapper tsmc65lp -test/test_helper.sh coyote tsmc65lp -test/test_helper.sh dynamic_node gf14 diff --git a/flow/test/nodes.txt b/flow/test/nodes.txt deleted file mode 100644 index bb33d62586..0000000000 --- a/flow/test/nodes.txt +++ /dev/null @@ -1 +0,0 @@ -1/localhost diff --git a/flow/test/openroad.sh b/flow/test/openroad.sh new file mode 100755 index 0000000000..d47e20263b --- /dev/null +++ b/flow/test/openroad.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash +set -e +# HACK while we're waiting for OpenROAD to be switched to MODULE.bazel +# OpenROAD has its own TCL library +unset TCL_LIBRARY +./external/_main~_repo_rules~openroad/openroad "$@" diff --git a/flow/test/smoke.sh b/flow/test/smoke.sh deleted file mode 100644 index 0cc3e1c4bc..0000000000 --- a/flow/test/smoke.sh +++ /dev/null @@ -1,3 +0,0 @@ -test/test_helper.sh gcd nangate45 -test/test_helper.sh gcd tsmc65lp -test/test_helper.sh gcd gf14 diff --git a/flow/test/test_autotuner.sh b/flow/test/test_autotuner.sh new file mode 100755 index 0000000000..03e9ddd005 --- /dev/null +++ b/flow/test/test_autotuner.sh @@ -0,0 +1,48 @@ +#!/usr/bin/env bash + +set -eoux pipefail + +DESIGN_NAME=${1:-gcd} +PLATFORM=${2:-nangate45} +# unittest does not allow dashes on test names +PLATFORM_WITHOUT_DASHES="${PLATFORM//-/}" + +# run the commands in ORFS root dir +echo "[INFO FLW-0029] Installing dependencies in virtual environment." +cd ../ +./tools/AutoTuner/installer.sh +. ./tools/AutoTuner/setup.sh + +echo "Running Autotuner smoke tune test" +python3 -m unittest tools.AutoTuner.test.smoke_test_tune.${PLATFORM_WITHOUT_DASHES}TuneSmokeTest.test_tune + +echo "Running Autotuner smoke sweep test" +python3 -m unittest tools.AutoTuner.test.smoke_test_sweep.${PLATFORM_WITHOUT_DASHES}SweepSmokeTest.test_sweep + +echo "Running Autotuner smoke tests for --sample and --iteration." +python3 -m unittest tools.AutoTuner.test.smoke_test_sample_iteration.${PLATFORM_WITHOUT_DASHES}SampleIterationSmokeTest.test_sample_iteration + +echo "Running Autotuner smoke algorithm eval test" +python3 -m unittest tools.AutoTuner.test.smoke_test_algo_eval.${PLATFORM_WITHOUT_DASHES}AlgoEvalSmokeTest.test_algo_eval + +if [ "$PLATFORM_WITHOUT_DASHES" == "asap7" ] && [ "$DESIGN_NAME" == "gcd" ]; then + echo "Running Autotuner ref file test (only once)" + python3 -m unittest tools.AutoTuner.test.ref_file_check.RefFileCheck + + echo "Running AutoTuner resume test (only once)" + # Temporarily disable resume check test due to flakiness + #python3 -m unittest tools.AutoTuner.test.resume_check.ResumeCheck.test_tune_resume + + echo "Running AutoTuner binary check (only once)" + openroad_autotuner -h +fi + +echo "Running Autotuner plotting smoke test" +all_experiments=$(ls -d ./flow/logs/${PLATFORM}/${DESIGN_NAME}/smoke-test-tune*) +all_experiments=$(basename -a $all_experiments) +for expt in $all_experiments; do + python3 tools/AutoTuner/scripts/plot.py \ + --platform ${PLATFORM} \ + --design ${DESIGN_NAME} \ + --experiment $expt +done diff --git a/flow/test/test_delta_debug.sh b/flow/test/test_delta_debug.sh index a856c1ce5c..59180cf8b8 100755 --- a/flow/test/test_delta_debug.sh +++ b/flow/test/test_delta_debug.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # # deltaDebug.py integration smoke-test, run from ORFS/flow folder. # @@ -11,7 +11,7 @@ cd "$(dirname "$0")/.." echo "Test deltaDebug.py with a make invocation" make DESIGN_CONFIG=designs/asap7/gcd/config.mk clean_all floorplan -openroad -exit -python ../tools/OpenROAD/etc/deltaDebug.py --persistence 2 --use_stdout --error_string "100 overflow" --base_db_path results/asap7/gcd/base/2_floorplan.odb --step "make DESIGN_CONFIG=designs/asap7/gcd/config.mk do-3_1_place_gp_skip_io" +openroad -exit -python ../tools/OpenROAD/etc/deltaDebug.py --persistence 2 --use_stdout --error_string " 100 | " --base_db_path results/asap7/gcd/base/2_floorplan.odb --step "make DESIGN_CONFIG=designs/asap7/gcd/config.mk do-3_1_place_gp_skip_io" echo "Test deltaDebug.py with a make issue" testname=uart @@ -24,4 +24,4 @@ mkdir -p results/delta-debug/ cd results/delta-debug/ tar --strip-components=1 -xzf ../../$latest_file sed -i 's/openroad -no_init/openroad -exit -no_init/g' run-me-$testname-asap7-base.sh -openroad -exit -python ../../../tools/OpenROAD/etc/deltaDebug.py --persistence 3 --use_stdout --error_string "100 overflow" --base_db_path results/asap7/$testname/base/3_2_place_iop.odb --step ./run-me-$testname-asap7-base.sh --multiplier 2 +openroad -exit -python ../../../tools/OpenROAD/etc/deltaDebug.py --persistence 3 --use_stdout --error_string " 100 | " --base_db_path results/asap7/$testname/base/3_2_place_iop.odb --step ./run-me-$testname-asap7-base.sh --multiplier 2 diff --git a/flow/test/test_genElapsedTime.py b/flow/test/test_genElapsedTime.py index e6108cb093..36da00209e 100755 --- a/flow/test/test_genElapsedTime.py +++ b/flow/test/test_genElapsedTime.py @@ -30,7 +30,7 @@ def test_elapsed_time(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 5400 9440\nTotal 5400 9440\n" + self.tmp_dir.name + "\n1_test 5400 9440 N/A\nTotal 5400 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -44,7 +44,7 @@ def test_zero_time(self, mock_stdout): # call the script with the test log file genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) expected_output = ( - self.tmp_dir.name + "\n1_test 74 9440\nTotal 74 9440\n" + self.tmp_dir.name + "\n1_test 74 9440 N/A\nTotal 74 9440\n" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) @@ -61,7 +61,7 @@ def test_elapsed_time_longer_duration(self, mock_stdout): genElapsedTime.scan_logs(["--logDir", str(self.tmp_dir.name), "--noHeader"]) # check if output is correct expected_output = ( - self.tmp_dir.name + "\n1_test 744 9440 Total 744 9440" + self.tmp_dir.name + "\n1_test 744 9440 N/A Total 744 9440" ).split() actual_output = mock_stdout.getvalue().split() self.assertEqual(actual_output, expected_output) diff --git a/flow/test/test_helper.sh b/flow/test/test_helper.sh index 9b2409d114..0b6af7e2d7 100755 --- a/flow/test/test_helper.sh +++ b/flow/test/test_helper.sh @@ -8,9 +8,10 @@ cd "$(dirname "$(readlink -f "$0")")/../" DESIGN_NAME=${1:-gcd} PLATFORM=${2:-nangate45} CONFIG_MK=${3:-config.mk} -if [ $# -eq 4 ]; then +if [ $# -ge 4 ]; then FLOW_VARIANT=$4 fi +TARGET=${5:-'finish metadata'} DESIGN_CONFIG=./designs/$PLATFORM/$DESIGN_NAME/$CONFIG_MK LOG_FILE=./logs/$PLATFORM/$DESIGN_NAME.log mkdir -p "./logs/$PLATFORM" @@ -26,12 +27,16 @@ $__make clean_all clean_metadata 2>&1 | tee "$LOG_FILE" # turn off abort on error so we can always capture the result set +e -$__make finish metadata 2>&1 | tee -a "$LOG_FILE" +eval $__make "${TARGET}" 2>&1 | tee -a "$LOG_FILE" # Save the return code to return as the overall status after we package # the results ret=$? +if [ "${TARGET}" != "finish metadata" ]; then + exit $ret +fi + if [ -z "${PRIVATE_DIR+x}" ]; then PRIVATE_DIR="../../private_tool_scripts" fi @@ -76,51 +81,40 @@ if [ $ret -eq 0 ] && grep -q 'power:' <(echo $TARGETS); then $__make power 2>&1 | tee -a "$LOG_FILE" ret=$(( ret + $? )) fi +set -x -if [[ -n "${RUN_AUTOTUNER+x}" ]] && [[ ${RUN_AUTOTUNER} -eq 1 ]]; then - # run the commands in ORFS root dir - echo "[INFO FLW-0029] Installing dependencies in virtual environment." - cd ../ - ./tools/AutoTuner/installer.sh - . ./tools/AutoTuner/setup.sh - - # remove dashes and capitalize platform name - PLATFORM=${PLATFORM//-/} - # convert to uppercase - PLATFORM=${PLATFORM^^} - - echo "Running Autotuner smoke tune test" - python3 -m unittest tools.AutoTuner.test.smoke_test_tune.${PLATFORM}TuneSmokeTest.test_tune - - echo "Running Autotuner smoke sweep test" - python3 -m unittest tools.AutoTuner.test.smoke_test_sweep.${PLATFORM}SweepSmokeTest.test_sweep - - echo "Running Autotuner smoke tests for --sample and --iteration." - python3 -m unittest tools.AutoTuner.test.smoke_test_sample_iteration.${PLATFORM}SampleIterationSmokeTest.test_sample_iteration +# Run Autotuner CI specifically for gcd on selected platforms. +if [ -z "${RUN_AUTOTUNER+x}" ]; then + echo "RUN_AUTOTUNER not set, disable AT test." + RUN_AUTOTUNER="false" +fi - if [ "$PLATFORM" == "asap7" ] && [ "$DESIGN" == "gcd" ]; then - echo "Running Autotuner ref file test (only once)" - python3 -m unittest tools.AutoTuner.test.ref_file_check.RefFileCheck.test_files - fi +if [ "${RUN_AUTOTUNER}" == "true" ]; then + case $DESIGN_NAME in + "gcd") + # Keep RUN_AUTOTUNER enabled only for these designs + ;; + *) + echo "Disable AT test for design ${DESIGN_NAME}." + RUN_AUTOTUNER="false" + ;; + esac + case $PLATFORM in + "asap7" | "sky130hd" | "ihp-sg13g2" ) + # Keep RUN_AUTOTUNER enabled only for these platforms + ;; + *) + echo "Disable AT test for platform ${PLATFORM}." + RUN_AUTOTUNER="false" + ;; + esac +fi - echo "Running Autotuner smoke algorithm & evaluation test" - python3 -m unittest tools.AutoTuner.test.smoke_test_algo_eval.${PLATFORM}AlgoEvalSmokeTest.test_algo_eval - - # run this test last (because it modifies current path) - echo "Running Autotuner remote test" - if [ "$PLATFORM" == "asap7" ] && [ "$DESIGN" == "gcd" ]; then - # Get the directory of the current script - script_dir="$(dirname "${BASH_SOURCE[0]}")" - cd "$script_dir"/../../ - latest_image=$(./etc/DockerTag.sh -dev) - echo "ORFS_VERSION=$latest_image" > ./tools/AutoTuner/.env - cd ./tools/AutoTuner - docker compose up --wait - docker compose exec ray-worker bash -c "cd /OpenROAD-flow-scripts/tools/AutoTuner/src/autotuner && \ - python3 distributed.py --design gcd --platform asap7 --server 127.0.0.1 --port 10001 \ - --config ../../../../flow/designs/asap7/gcd/autotuner.json tune --samples 1" - docker compose down -v --remove-orphans - fi +if [ "${RUN_AUTOTUNER}" == "true" ]; then + set +x + echo "Start AutoTuner test." + ./test/test_autotuner.sh $DESIGN_NAME $PLATFORM + set -x fi exit $ret diff --git a/flow/test/test_make_issue.sh b/flow/test/test_make_issue.sh index bc055ddbf6..6fd7be46d3 100755 --- a/flow/test/test_make_issue.sh +++ b/flow/test/test_make_issue.sh @@ -1,11 +1,14 @@ -#!/bin/bash +#!/usr/bin/env bash # make issue smoketest set -ue -o pipefail -testname=Element +# Pick a design that builds quickly and has +# has some interesting "make issue" features to test, +# such as ADDITIONAL_FILES -make DESIGN_CONFIG=designs/asap7/mock-array/$testname/config.mk floorplan -make ISSUE_TAG=tag DESIGN_CONFIG=designs/asap7/mock-array/$testname/config.mk io_placement_random_issue +make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk floorplan +make ISSUE_TAG=tag DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk io_placement_random_issue +# io placement needs ADDITIONAL_FILES to work, so not a random test test_archive=io_placement_random_tag.tar.gz ls -l $test_archive echo "Testing $test_archive" @@ -14,6 +17,8 @@ rm -rf results/make-issue/ mkdir -p results/make-issue/ cd results/make-issue/ tar --strip-components=1 -xzf ../../$test_archive -runme=run-me-mock-array_$testname-asap7-base.sh +runme=run-me-mock-array_Element-asap7-base.sh sed -i 's/openroad -no_init/openroad -exit -no_init/g' $runme ./$runme +# check for basic syntax errors +openroad -exit -no_init vars-mock-array_Element-asap7-base.tcl diff --git a/flow/test/test_outoftree.sh b/flow/test/test_outoftree.sh new file mode 100755 index 0000000000..5474b3012b --- /dev/null +++ b/flow/test/test_outoftree.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +# +# deltaDebug.py integration smoke-test, run from ORFS/flow folder. +# +# Exit with error if anything is amiss, including evaluation of +# variable names such as $(false), unused variables, etc. +set -x -ue -o pipefail + +cd "$(dirname "$0")/.." +rm -rf results/outoftree/ +mkdir -p results/outoftree/ +cd results/outoftree/ +cp ../../designs/src/aes/* . +make --file=../../Makefile DESIGN_CONFIG=../../designs/asap7/minimal/config.mk DESIGN_NAME=aes_cipher_top VERILOG_FILES="$(ls *.v | xargs)" grt diff --git a/flow/tutorials/scripts/drt/drc_fix.tcl b/flow/tutorials/scripts/drt/drc_fix.tcl index 16e8030c85..4126fc64e9 100644 --- a/flow/tutorials/scripts/drt/drc_fix.tcl +++ b/flow/tutorials/scripts/drt/drc_fix.tcl @@ -8,10 +8,9 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -23,10 +22,8 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/drc_issue.tcl b/flow/tutorials/scripts/drt/drc_issue.tcl index 54a6427d45..af54690e7e 100644 --- a/flow/tutorials/scripts/drt/drc_issue.tcl +++ b/flow/tutorials/scripts/drt/drc_issue.tcl @@ -8,10 +8,9 @@ read_sdc ./gcd/gcd.sdc # global_route set_global_routing_layer_adjustment met1-met5 0.5 set_routing_layers -signal met1-met5 -set_macro_extension 2 global_route -guide_file [make_result_file route.guide] \ - -congestion_iterations 100 \ - -verbose + -congestion_iterations 100 \ + -verbose source ../../../platforms/sky130hd/setRC.tcl set_propagated_clock [all_clocks] @@ -23,10 +22,8 @@ set_thread_count 2 set drc_rpt [make_result_file 5_route_drc.rpt] set maze_log [make_result_file maze.log] detailed_route -output_drc $drc_rpt \ - -output_maze $maze_log \ - -bottom_routing_layer met1 \ - -top_routing_layer met5 \ - -verbose 1 + -output_maze $maze_log \ + -verbose 1 set route_def [make_result_file 5_route.def] write_def $route_def puts "Number of DRC Violations = [detailed_route_num_drvs]" diff --git a/flow/tutorials/scripts/drt/helpers.tcl b/flow/tutorials/scripts/drt/helpers.tcl index be1af8e7c2..bfb1fe8386 100644 --- a/flow/tutorials/scripts/drt/helpers.tcl +++ b/flow/tutorials/scripts/drt/helpers.tcl @@ -14,7 +14,7 @@ proc make_result_file { filename } { # puts [exec cat $file] without forking. proc report_file { file } { set stream [open $file r] - + while { [gets $stream line] >= 0 } { puts $line } @@ -24,9 +24,9 @@ proc report_file { file } { proc diff_files { file1 file2 } { set stream1 [open $file1 r] set stream2 [open $file2 r] - + set line 1 - set diff_line 0; + set diff_line 0 while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } { if { $line1 != $line2 } { set diff_line $line diff --git a/flow/tutorials/scripts/gui/load_lef.tcl b/flow/tutorials/scripts/gui/load_lef.tcl index 259bdb4c03..34d5760cb8 100644 --- a/flow/tutorials/scripts/gui/load_lef.tcl +++ b/flow/tutorials/scripts/gui/load_lef.tcl @@ -1,6 +1,6 @@ -proc load_lef_sky130 {} { - set FLOW_PATH [exec pwd] - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef - read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef +proc load_lef_sky130 { } { + set FLOW_PATH [exec pwd] + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef + read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef } create_toolbar_button -name "Load_LEF" -text "Load_LEF" -script {load_lef_sky130} -echo diff --git a/flow/util/BUILD.bazel b/flow/util/BUILD.bazel new file mode 100644 index 0000000000..b8892cbab6 --- /dev/null +++ b/flow/util/BUILD.bazel @@ -0,0 +1,42 @@ +load("@orfs-pip//:requirements.bzl", "requirement") +load("@rules_python//python:pip.bzl", "compile_pip_requirements") + +exports_files(["open_plots.sh"]) + +py_binary( + name = "plot_congestion", + srcs = ["plot_congestion.py"], + main = "plot_congestion.py", + visibility = ["//visibility:public"], + deps = [requirement("matplotlib")], +) + +compile_pip_requirements( + name = "requirements", + src = "requirements.in", + requirements_txt = "requirements_lock.txt", +) + +MAKEFILE_SHARED = [ + "*.mk", +] + +# for scripts/flow.sh steps +filegroup( + name = "makefile", + srcs = glob(MAKEFILE_SHARED + [ + "*.py", + "*.sh", + ]), + visibility = ["//visibility:public"], +) + +# for scripts/synth.sh steps +filegroup( + name = "makefile_yosys", + srcs = glob(MAKEFILE_SHARED) + [ + "merge_lib.py", + "preprocessLib.py", + ], + visibility = ["//visibility:public"], +) diff --git a/flow/util/addDummyToLef.py b/flow/util/addDummyToLef.py index c6a39471c8..3c0c828eec 100755 --- a/flow/util/addDummyToLef.py +++ b/flow/util/addDummyToLef.py @@ -30,5 +30,5 @@ f.write(result) f.close() else: - print("ERROR: Pattern not found") + print("Error: Pattern not found") sys.exit(1) diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl index 2507dd5fb9..901fd13706 100644 --- a/flow/util/cell-veneer/lefdef.tcl +++ b/flow/util/cell-veneer/lefdef.tcl @@ -1,20 +1,19 @@ -proc absolute_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] + [lindex $offset 0]] \ - [expr [lindex $rect 1] + [lindex $offset 1]] \ - [expr [lindex $rect 2] + [lindex $offset 0]] \ - [expr [lindex $rect 3] + [lindex $offset 1]] \ - ] -} -proc relative_rectangle {rect offset} { - return [list \ - [expr [lindex $rect 0] - [lindex $offset 0]] \ - [expr [lindex $rect 1] - [lindex $offset 1]] \ - [expr [lindex $rect 2] - [lindex $offset 0]] \ - [expr [lindex $rect 3] - [lindex $offset 1]] \ - ] +proc absolute_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] + [lindex $offset 0]] \ + [expr [lindex $rect 1] + [lindex $offset 1]] \ + [expr [lindex $rect 2] + [lindex $offset 0]] \ + [expr [lindex $rect 3] + [lindex $offset 1]]] +} +proc relative_rectangle { rect offset } { + return [list \ + [expr [lindex $rect 0] - [lindex $offset 0]] \ + [expr [lindex $rect 1] - [lindex $offset 1]] \ + [expr [lindex $rect 2] - [lindex $offset 0]] \ + [expr [lindex $rect 3] - [lindex $offset 1]]] } +# tclint-disable-next-line command-args if [package vcompare 8.6 $tcl_version] { proc lmap {_var list body} { upvar 1 $_var var @@ -25,919 +24,955 @@ if [package vcompare 8.6 $tcl_version] { } namespace eval lef { - variable lefOut stdout - variable def_units 2000 - - proc open {file_name} { - variable lefOut - set lefOut [::open $file_name w] - } - - proc close {} { - variable lefOut - if {$lefOut != "stdout"} { - ::close $lefOut - } - set lefOut stdout - } - - proc out {args} { - variable lefOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $lefOut [lindex $args 1] - } else { - puts $lefOut [lindex $args 0] - } - } +variable lefOut stdout +variable def_units 2000 - variable cells - - proc get_cells {} { - variable cells - return $cells - } - - proc get_cell {cell_name} { - variable cells - return [dict get $cells $cell_name] - } - - proc get_width {cell} { - return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] - } - - proc get_height {cell} { - return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] - } - - proc read_macros {file_name} { - variable cells - variable def_units - - set ch [::open $file_name] - - set cells {} +# tclint-disable-next-line redefined-builtin +proc open { file_name } { + variable lefOut + set lefOut [::open $file_name w] +} - while {![eof $ch]} { - set line [gets $ch] +# tclint-disable-next-line redefined-builtin +proc close { } { + variable lefOut + if { $lefOut != "stdout" } { + ::close $lefOut + } + set lefOut stdout +} - if {[regexp {MACRO\s*([^\s]*)} $line - cell_name]} { - dict set cells $cell_name units $def_units - dict set cells $cell_name name $cell_name - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {CLASS\s+([^\s]*)} $line - cell_class]} { - dict set cells $cell_name cell_class $cell_class - } elseif {[regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y]} { - dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] {expr round($x * $def_units)}] - } elseif {[regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y]} { - dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] {expr round($x * $def_units)}]] - } elseif {[regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height]} { - dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] - } elseif {[regexp {SYMMETRY\s+(.*)\s;} $line - symmetry]} { - dict set cells $cell_name symmetry $symmetry - } elseif {[regexp {SITE\s+([^\s]*)} $line - site]} { - dict set cells $cell_name site $site - } elseif {[regexp {PIN\s*([^\s]*)} $line - pin_name]} { - set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] - if {[info vars antennamodel] != ""} { - unset antennamodel - } - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {DIRECTION\s+([^\s]*)} $line - direction]} { - dict set cells $cell_name pins $pin_name direction $direction - } elseif {[regexp {USE\s+([^\s]*)} $line - use]} { - dict set cells $cell_name pins $pin_name use $use - } elseif {[regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel]} { - continue - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area layer $layer] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area]} { - if {[info vars antennamodel] == ""} { - set antennamodel "default" - } - if {[dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel]} { - set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] - } else { - set model {} - } - lappend model [list gate_area $gate_area] - dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea - } elseif {[regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea]} { - dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea - } elseif {[regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape]} { - dict set cells $cell_name pins $pin_name shape $shape - } elseif {[regexp {PORT} $line]} { - set port {} - dict set port orientation N - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)} $line - layer]} { - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - mask $mask \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $port layers $layer shapes]} { - set layer_shapes [dict get $port layers $layer shapes] - } else { - set layer_shapes {} - } - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } else { - set offset [lmap x [list $x1 $y1] {expr round($x * $def_units)}] - dict set port fixed $offset - } - set new_shape [list \ - rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] $offset] \ - ] - lappend layer_shapes $new_shape - dict set port layers $layer shapes $layer_shapes - } elseif {[regexp {END} $line]} { - if {[dict exists $cells $cell_name pins $pin_name ports]} { - set ports [dict get $cells $cell_name pins $pin_name ports] - } else { - set ports {} - } - lappend ports $port - dict set cells $cell_name pins $pin_name ports $ports - break - } else { - error "Parsing failure PORT:\n$line" - } - } - } elseif {[regexp "END\\s$pin_pattern" $line]} { - break - } else { - error "Parsing failure PIN:\n$line" - } - } - } elseif {[regexp {OBS} $line]} { - while {![eof $ch]} { - set line [gets $ch] - if {[regexp {^\s*$} $line]} { - continue - } elseif {[regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw]} { - if {$drw != ""} { - dict set cells $cell_name layers $layer drw $drw - } - continue - } elseif {[regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}] mask $mask] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2]} { - if {[dict exists $cells $cell_name obstructions $layer]} { - set obstructions [dict get $cells $cell_name obstructions $layer] - } else { - set obstructions {} - } - lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] {expr round($x * $def_units)}]] - dict set cells $cell_name obstructions $layer $obstructions - } elseif {[regexp {END} $line]} { - break - } else { - error "Parsing failure OBS:\n$line" - } - } - } elseif {[regexp "END\\s*$cell_name" $line]} { - break - } else { - error "Parsing failure MACRO\n$line" - } - } - } - } +proc out { args } { + variable lefOut - ::close $ch - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $lefOut [lindex $args 1] + } else { + puts $lefOut [lindex $args 0] + } +} - proc get_blockage_layers {design} { - if {[dict exists $design blockage_layers]} { - return [dict get $design blockage_layers] - } +variable cells - set blocked_layers {} +proc get_cells { } { + variable cells + return $cells +} - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name - } - return $blocked_layers - } +proc get_cell { cell_name } { + variable cells + return [dict get $cells $cell_name] +} - proc write_header {} { - } - proc write_footer {} { - } - # Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries - # - cell_class - # - origin - # - foreign - # - ref - # - origin - # - die_area - # - symmetry - # - site - # - pins: dict with the name of the pin as the key - # - antenna_model - # - gate_area - # - layer - # - antennadiffarea - # - layer - # - area - # - direction - # - use - # - shape - # - ports: a list of lists of shapes that make up a physical connection - # - layer - # - rect - # - mask? - # - obstructions - # - layer: a dictionaries with layer_name as the key - # - rect - # - mask? - # - proc write {design} { - set def_units [dict get $design units] - - out "MACRO [dict get $design name]" - out " CLASS [dict get $design cell_class] ;" - if {[dict exists $design origin]} { - out " ORIGIN [dict get $design origin] ;" - } else { - out " ORIGIN 0.0 0.0 ;" - } - out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" - out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" - out " SYMMETRY [dict get $design symmetry] ;" - if {[dict exists $design site]} { - out " SITE [dict get $design site] ;" - } +proc get_width { cell } { + return [expr [lindex [dict get $cell die_area] 2] - [lindex [dict get $cell die_area] 0]] +} - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - out " PIN $pin_name" - out " DIRECTION [dict get $pin direction] ;" - if {[dict exists $pin use]} { - out " USE [dict get $pin use] ;" - } - foreach port [dict get $pin ports] { - out " PORT " - foreach layer_name [dict keys [dict get $port layers]] { - set shapes [dict get $port layers $layer_name shapes] - - out " LAYER $layer_name ;" - foreach shape $shapes { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - set rect [absolute_rectangle [dict get $shape rect] $offset] - - if {[dict exists $shape mask]} { - out " RECT MASK [dict get $shape mask] [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x $rect {expr 1.0 * $x / $def_units}] ;" - } - } - } - out " END " - } - out " END $pin_name" - } - } +proc get_height { cell } { + return [expr [lindex [dict get $cell die_area] 3] - [lindex [dict get $cell die_area] 1]] +} - if {[dict exists $design obstructions]} { - out " OBS" - if {[dict get $design use_sheet_obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - lappend blocked_layers $layer_name +# tclint-disable line-length +proc read_macros { file_name } { + variable cells + variable def_units + + set ch [::open $file_name] + + set cells {} + + while { ![eof $ch] } { + set line [gets $ch] + + if { [regexp {MACRO\s*([^\s]*)} $line - cell_name] } { + dict set cells $cell_name units $def_units + dict set cells $cell_name name $cell_name + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {CLASS\s+([^\s]*)} $line - cell_class] } { + dict set cells $cell_name cell_class $cell_class + } elseif { [regexp {ORIGIN\s+([^\s]*)\s+([^\s]*)} $line - origin_x origin_y] } { + dict set cells $cell_name origin [lmap x [list $origin_x $origin_y] { expr round($x * $def_units) }] + } elseif { [regexp {FOREIGN\s+([^\s]*)\s+([^\s]*)\s+([^\s]*)} $line - foreign x y] } { + dict set cells $cell_name foreign [list ref $foreign origin [lmap x [list $x $y] { expr round($x * $def_units) }]] + } elseif { [regexp {SIZE\s+([^\s]*)\s+BY\s+([^\s]*)} $line - width height] } { + dict set cells $cell_name die_area [list 0 0 [expr round($width * $def_units)] [expr round($height * $def_units)]] + } elseif { [regexp {SYMMETRY\s+(.*)\s;} $line - symmetry] } { + dict set cells $cell_name symmetry $symmetry + } elseif { [regexp {SITE\s+([^\s]*)} $line - site] } { + dict set cells $cell_name site $site + } elseif { [regexp {PIN\s*([^\s]*)} $line - pin_name] } { + set pin_pattern [regsub -all {([\[\]])} $pin_name {\\\1}] + if { [info vars antennamodel] != "" } { + unset antennamodel + } + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {DIRECTION\s+([^\s]*)} $line - direction] } { + dict set cells $cell_name pins $pin_name direction $direction + } elseif { [regexp {USE\s+([^\s]*)} $line - use] } { + dict set cells $cell_name pins $pin_name use $use + } elseif { [regexp {ANTENNAMODEL\s+([^\s]*)} $line - antennamodel] } { + continue + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - gate_area layer] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" + } + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area layer $layer] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNAGATEAREA\s+([^\s]*)} $line - gate_area] } { + if { [info vars antennamodel] == "" } { + set antennamodel "default" } - set sheet "0 0 [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]" - foreach layer_name [get_blockage_layers $design] { - if {[dict exists $design layers $layer_name drw]} { - set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " + if { [dict exists $cells $cell_name pins $pin_name antenna_model $antennamodel] } { + set model [dict get $cells $cell_name pins $pin_name antenna_model $antennamodel] + } else { + set model {} + } + lappend model [list gate_area $gate_area] + dict set cells $cell_name pins $pin_name antenna_model $antennamodel $model + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s+LAYER\s+([^\s]*)} $line - antennadiffarea layer] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + dict set cells $cell_name pins $pin_name antennadiffarea layer $antennadiffarea + } elseif { [regexp {ANTENNADIFFAREA\s+([^\s]*)\s} $line - antennadiffarea] } { + dict set cells $cell_name pins $pin_name antennadiffarea area $antennadiffarea + } elseif { [regexp {SHAPE\s+([^\s]*)\s+([^\s]*)} $line - shape] } { + dict set cells $cell_name pins $pin_name shape $shape + } elseif { [regexp {PORT} $line] } { + set port {} + dict set port orientation N + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)} $line - layer] } { + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset] \ + mask $mask] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $port layers $layer shapes] } { + set layer_shapes [dict get $port layers $layer shapes] + } else { + set layer_shapes {} + } + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } else { + set offset [lmap x [list $x1 $y1] { expr round($x * $def_units) }] + dict set port fixed $offset + } + set new_shape [list \ + rect [relative_rectangle [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] $offset]] + lappend layer_shapes $new_shape + dict set port layers $layer shapes $layer_shapes + } elseif { [regexp {END} $line] } { + if { [dict exists $cells $cell_name pins $pin_name ports] } { + set ports [dict get $cells $cell_name pins $pin_name ports] + } else { + set ports {} + } + lappend ports $port + dict set cells $cell_name pins $pin_name ports $ports + break } else { - set drw "" + error "Parsing failure PORT:\n$line" } - out " LAYER $layer_name $drw;" - out " RECT $sheet ;" } + } elseif { [regexp "END\\s$pin_pattern" $line] } { + break } else { - dict for {layer_name obstructions} [dict get $design obstructions] { - out " LAYER $layer_name ;" - foreach obs $obstructions { - if {[dict exists $obs mask]} { - out " RECT MASK [dict get $obs mask] [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } else { - out " RECT [lmap x [dict get $obs rect] {expr 1.0 * $x / $def_units}] ;" - } - } + error "Parsing failure PIN:\n$line" + } + } + } elseif { [regexp {OBS} $line] } { + while { ![eof $ch] } { + set line [gets $ch] + if { [regexp {^\s*$} $line] } { + continue + } elseif { [regexp {LAYER\s+([^\s]*)(\s+DESIGNRULEWIDTH\s+([0-9.]+))?} $line - layer - drw] } { + if { $drw != "" } { + dict set cells $cell_name layers $layer drw $drw + } + continue + } elseif { [regexp {RECT\s+MASK\s+([^\s]*)\s+([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - mask x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} + } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }] mask $mask] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {RECT\s([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)\s\s*([0-9\-\.]*)} $line - x1 y1 x2 y2] } { + if { [dict exists $cells $cell_name obstructions $layer] } { + set obstructions [dict get $cells $cell_name obstructions $layer] + } else { + set obstructions {} } + lappend obstructions [list rect [lmap x [list $x1 $y1 $x2 $y2] { expr round($x * $def_units) }]] + dict set cells $cell_name obstructions $layer $obstructions + } elseif { [regexp {END} $line] } { + break + } else { + error "Parsing failure OBS:\n$line" } - out " END" + } + } elseif { [regexp "END\\s*$cell_name" $line] } { + break + } else { + error "Parsing failure MACRO\n$line" } - out "END [dict get $design name]" - out "" + } } - - proc write_cells {file_name cells} { - lef open $file_name - - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" - out "SITE sc10p5mcpp84_14lpp" - out " CLASS CORE ;" - out " SIZE 0.084 BY 0.672 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp" - out "" - out "SITE sc10p5mcpp84_14lpp_pg" - out " CLASS CORE ;" - out " SIZE 0.084 BY 1.344 ;" - out " SYMMETRY Y ;" - out "END sc10p5mcpp84_14lpp_pg" - out "" + } - dict for {cell_name cell} $cells { - lef write $cell - } + ::close $ch +} +# tclint-enable line-length - out "END LIBRARY" - out "" - lef close - } +proc get_blockage_layers { design } { + if { [dict exists $design blockage_layers] } { + return [dict get $design blockage_layers] + } - proc write_macros {file_name cells} { - lef open $file_name + set blocked_layers {} - out "###############################################################" - out "# Created by cell-veneer" - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - out "" - out "VERSION 5.8 ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DIVIDERCHAR \"/\" ;" - out "" + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + return $blocked_layers +} - dict for {cell_name cell} $cells { - lef write $cell - } +proc write_header { } { - out "END LIBRARY" - out "" - lef close - } +} +proc write_footer { } { - namespace export read_macros get_width get_height - namespace export get_cell get_cells write write_cells write_macros - namespace export open close out - namespace ensemble create } +# tclint-disable-next-line line-length +# Read a LEF from a file into a dictionary with the name of the cell as the key and the following entries +# - cell_class +# - origin +# - foreign +# - ref +# - origin +# - die_area +# - symmetry +# - site +# - pins: dict with the name of the pin as the key +# - antenna_model +# - gate_area +# - layer +# - antennadiffarea +# - layer +# - area +# - direction +# - use +# - shape +# - ports: a list of lists of shapes that make up a physical connection +# - layer +# - rect +# - mask? +# - obstructions +# - layer: a dictionaries with layer_name as the key +# - rect +# - mask? +# +proc write { design } { + set def_units [dict get $design units] + + out "MACRO [dict get $design name]" + out " CLASS [dict get $design cell_class] ;" + if { [dict exists $design origin] } { + out " ORIGIN [dict get $design origin] ;" + } else { + out " ORIGIN 0.0 0.0 ;" + } + out " FOREIGN [dict get $design foreign ref] [dict get $design foreign origin] ;" + out " SIZE [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units]\ + BY [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units] ;" + out " SYMMETRY [dict get $design symmetry] ;" + if { [dict exists $design site] } { + out " SITE [dict get $design site] ;" + } + + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + out " PIN $pin_name" + out " DIRECTION [dict get $pin direction] ;" + if { [dict exists $pin use] } { + out " USE [dict get $pin use] ;" + } + foreach port [dict get $pin ports] { + out " PORT " + foreach layer_name [dict keys [dict get $port layers]] { + set shapes [dict get $port layers $layer_name shapes] + + out " LAYER $layer_name ;" + foreach shape $shapes { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] + } + set rect [absolute_rectangle [dict get $shape rect] $offset] -namespace eval def { - variable def_units - variable defOut stdout - variable designs {} - - proc open {file_name} { - variable defOut - set defOut [::open $file_name w] - } - - proc close {} { - variable defOut - if {$defOut != "stdout"} { - ::close $defOut + if { [dict exists $shape mask] } { + out \ + " RECT MASK [dict get $shape mask]\ + [lmap x $rect { expr { 1.0 * $x / $def_units } }] \ + ;" + } else { + out " RECT [lmap x $rect { expr 1.0 * $x / $def_units }] ;" + } + } } - set defOut stdout + out " END " + } + out " END $pin_name" } - - proc out {args} { - variable defOut - - if {[llength $args] == 2} { - puts [lindex $args 0] $defOut [lindex $args 1] + } + + if { [dict exists $design obstructions] } { + out " OBS" + if { [dict get $design use_sheet_obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + lappend blocked_layers $layer_name + } + set sheet [concat \ + 0 0 \ + [expr 1.0 * [lindex [dict get $design die_area] 2] / $def_units] \ + [expr 1.0 * [lindex [dict get $design die_area] 3] / $def_units]] + foreach layer_name [get_blockage_layers $design] { + if { [dict exists $design layers $layer_name drw] } { + set drw "DESIGNRULEWIDTH [dict get $design layers $layer_name drw] " } else { - puts $defOut [lindex $args 0] + set drw "" } + out " LAYER $layer_name $drw;" + out " RECT $sheet ;" + } + } else { + dict for {layer_name obstructions} [dict get $design obstructions] { + out " LAYER $layer_name ;" + foreach obs $obstructions { + if { [dict exists $obs mask] } { + out " RECT MASK [dict get $obs mask]\ + [lmap x [dict get $obs rect] { expr { 1.0 * $x / $def_units } }] + ;" + } else { + out " RECT [lmap x [dict get $obs rect] { expr 1.0 * $x / $def_units }] ;" + } + } + } } + out " END" + } + out "END [dict get $design name]" + out "" +} - # Write out DEF from a design structure which is a dictionary with the following keys - # - name - # - tool - # - units - # - die_area - # - core_area - # - rows: dict with the index of the row as the key - # - site - # - start - # - height - # - orientation - # - num_sites - # - site_width - # - pins: dict with the name of the pin as the key - # - net_name - # - direction - # - use - # - special - # - ports : a list of dictionaries, one per port - # - orientation - # - (placed|fixed) - # - layers - # - spacing - # - designrulewidth - # - shapes : list of rectangles (or polygons) - # - (rect|polygon) - # - physical_viarules: dict with the name of the viarule as the key - # - rule - # - cutsize - # - layers - # - cutspacing - # - enclosure - # - rowcol - # - components: dict with the instance name of the component as the key - # - inst_name - # - cell_name - # - (fixed|placed)? - # - orientation - # - nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictionaries - # - layer - # - points: list of points, where a point can be an XY location or the name of a VIA - # - special_nets: dict with the name of the net as the key - # - use: SIGNAL | POWER | GROUND - # - connections: list of instance pin pairs - # - routes: list of dictioaries - # - layer - # - width - # - shape - # - points: list of points, where a point can be an XY location or the name of a VIA - # - - proc shift_point {point x y} { - return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] - } - - proc shift_rect {rect x y} { - return [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y] [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]] - } +proc write_cells { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + out "SITE sc10p5mcpp84_14lpp" + out " CLASS CORE ;" + out " SIZE 0.084 BY 0.672 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp" + out "" + out "SITE sc10p5mcpp84_14lpp_pg" + out " CLASS CORE ;" + out " SIZE 0.084 BY 1.344 ;" + out " SYMMETRY Y ;" + out "END sc10p5mcpp84_14lpp_pg" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - proc shift_origin {design x y} { - if {[dict exists $design die_area]} { - dict set design die_area [shift_rect [dict get $design die_area] $x $y] - } - if {[dict exists $design core_area]} { - dict set design core_area [shift_rect [dict get $design core_area] $x $y] - } - if {[dict exists $design rows]} { - } - if {[dict exists $design pins]} { - dict for {pin_name pin} [dict get $design pins] { - set ports {} - foreach port [dict get $pin ports] { - if {[dict exists $port fixed]} { - dict set port fixed [shift_point [dict get $port fixed] $x $y] - } elseif {[dict exists $port placed]} { - dict set port placed [shift_point [dict get $port placed] $x $y] - } - lappend ports $port - } - dict set design pins $pin_name ports $ports - } - } - if {[dict exists $design components]} { - dict for {inst_name inst} [dict get $design components] { - if {[dict exists $inst fixed]} { - dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] - } elseif {[dict exists $inst placed]} { - dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] - } - } - } - if {[dict exists $design nets]} { - dict for {net_name net} [dict get $design nets] { - if {[dict exists $net routes]} { - set routes {} - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design nets $net_name routes $routes - } - } - } - if {[dict exists $design special_nets]} { - dict for {net_name net} [dict get $design special_nets] { - set routes {} - if {[dict exists $net routes]} { - foreach route [dict get $net routes] { - set points {} - foreach point $points { - if {[llength $point] == 2} { - lappend points [shift_point $point $x $y] - } else { - lappend points $point - } - } - lappend routes $route - } - dict set design special_nets $net_name routes $routes - } - } - } - if {[dict exists $design obstructions]} { - dict for {layer_name obstructions} [dict get $design obstructions] { - set new_obs {} - foreach obs $obstructions { - dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] - lappend new_obs $obs - } - dict set design obstructions $layer_name $new_obs - } - } +proc write_macros { file_name cells } { + lef open $file_name + + out "###############################################################" + out "# Created by cell-veneer" + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + out "" + out "VERSION 5.8 ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DIVIDERCHAR \"/\" ;" + out "" + + dict for {cell_name cell} $cells { + lef write $cell + } + + out "END LIBRARY" + out "" + lef close +} - return $design - } +namespace export read_macros get_width get_height +namespace export get_cell get_cells write write_cells write_macros +namespace export open close out +namespace ensemble create +} - variable layer_info {} - proc set_layer_info {layer_name key value} { - variable layer_info +namespace eval def { +variable def_units +variable defOut stdout +variable designs {} + +# tclint-disable-next-line redefined-builtin +proc open { file_name } { + variable defOut + set defOut [::open $file_name w] +} - dict set layer_info layers $layer_name $key $value - } +# tclint-disable-next-line redefined-builtin +proc close { } { + variable defOut + if { $defOut != "stdout" } { + ::close $defOut + } + set defOut stdout +} - proc get_layer_width {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name width] - } +proc out { args } { + variable defOut - proc get_layer_non_preferred_width {layer_name} { - variable layer_info - if {[dict exists $layer_info layers $layer_name non_preferred_width]} { - return [dict get $layer_info layers $layer_name non_preferred_width] - } - return [dict get $layer_info layers $layer_name width] - } + if { [llength $args] == 2 } { + puts [lindex $args 0] $defOut [lindex $args 1] + } else { + puts $defOut [lindex $args 0] + } +} - proc get_layer_direction {layer_name} { - variable layer_info - return [dict get $layer_info layers $layer_name direction] - } +# Write out DEF from a design structure which is a dictionary with the following keys +# - name +# - tool +# - units +# - die_area +# - core_area +# - rows: dict with the index of the row as the key +# - site +# - start +# - height +# - orientation +# - num_sites +# - site_width +# - pins: dict with the name of the pin as the key +# - net_name +# - direction +# - use +# - special +# - ports : a list of dictionaries, one per port +# - orientation +# - (placed|fixed) +# - layers +# - spacing +# - designrulewidth +# - shapes : list of rectangles (or polygons) +# - (rect|polygon) +# - physical_viarules: dict with the name of the viarule as the key +# - rule +# - cutsize +# - layers +# - cutspacing +# - enclosure +# - rowcol +# - components: dict with the instance name of the component as the key +# - inst_name +# - cell_name +# - (fixed|placed)? +# - orientation +# - nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictionaries +# - layer +# - points: list of points, where a point can be an XY location or the name of a VIA +# - special_nets: dict with the name of the net as the key +# - use: SIGNAL | POWER | GROUND +# - connections: list of instance pin pairs +# - routes: list of dictioaries +# - layer +# - width +# - shape +# - points: list of points, where a point can be an XY location or the name of a VIA +# + +proc shift_point { point x y } { + return [list [expr [lindex $point 0] + $x] [expr [lindex $point 1] + $y]] +} - proc get_line_direction {points} { - if {[lindex $points 0 0] == [lindex $points 1 0]} { - set direction "VERTICAL" - } elseif {[lindex $points 0 1] == [lindex $points 1 1]} { - set direction "HORIZONTAL" - } else { - error "Non orthogonal line $points" +proc shift_rect { rect x y } { + return [concat \ + [list [expr [lindex $rect 0] + $x] [expr [lindex $rect 1] + $y]] \ + [list [expr [lindex $rect 2] + $x] [expr [lindex $rect 3] + $y]]] +} + +proc shift_origin { design x y } { + if { [dict exists $design die_area] } { + dict set design die_area [shift_rect [dict get $design die_area] $x $y] + } + if { [dict exists $design core_area] } { + dict set design core_area [shift_rect [dict get $design core_area] $x $y] + } + if { [dict exists $design rows] } { + + } + if { [dict exists $design pins] } { + dict for {pin_name pin} [dict get $design pins] { + set ports {} + foreach port [dict get $pin ports] { + if { [dict exists $port fixed] } { + dict set port fixed [shift_point [dict get $port fixed] $x $y] + } elseif { [dict exists $port placed] } { + dict set port placed [shift_point [dict get $port placed] $x $y] + } + lappend ports $port + } + dict set design pins $pin_name ports $ports + } + } + if { [dict exists $design components] } { + dict for {inst_name inst} [dict get $design components] { + if { [dict exists $inst fixed] } { + dict set design components $inst_name fixed [shift_point [dict get $inst fixed] $x $y] + } elseif { [dict exists $inst placed] } { + dict set design components $inst_name placed [shift_point [dict get $inst placed] $x $y] + } + } + } + if { [dict exists $design nets] } { + dict for {net_name net} [dict get $design nets] { + if { [dict exists $net routes] } { + set routes {} + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } - return $direction + dict set design nets $net_name routes $routes + } } - proc get_line_width {layer_name points} { - set direction [get_line_direction $points] - - if {[get_layer_direction $layer_name] == $direction} { - return [get_layer_width $layer_name] - } else { - return [get_layer_non_preferred_width $layer_name] + } + if { [dict exists $design special_nets] } { + dict for {net_name net} [dict get $design special_nets] { + set routes {} + if { [dict exists $net routes] } { + foreach route [dict get $net routes] { + set points {} + foreach point $points { + if { [llength $point] == 2 } { + lappend points [shift_point $point $x $y] + } else { + lappend points $point + } + } + lappend routes $route } + dict set design special_nets $net_name routes $routes + } + } + } + if { [dict exists $design obstructions] } { + dict for {layer_name obstructions} [dict get $design obstructions] { + set new_obs {} + foreach obs $obstructions { + dict set obs rect [def::shift_rect [dict get $obs rect] $x $y] + lappend new_obs $obs + } + dict set design obstructions $layer_name $new_obs } + } - proc get_extended_line {layer_name points} { - if {[llength [lindex $points 1]] == 1} { - return "( [lindex $points 0] ) [lindex $points 1]" - } + return $design +} - set direction [get_line_direction $points] +variable layer_info {} +proc set_layer_info { layer_name key value } { + variable layer_info - if {$direction == [get_layer_direction $layer_name]} { - set extension [expr [get_layer_non_preferred_width $layer_name] / 2] - } else { - set extension [expr [get_layer_width $layer_name] / 2] - } + dict set layer_info layers $layer_name $key $value +} - if {$direction == "VERTICAL"} { - set x_min [lindex $points 0 0] - set x_max [lindex $points 0 0] - set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] - set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] - } else { - set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] - set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] - set y_min [lindex $points 0 1] - set y_max [lindex $points 0 1] - } +proc get_layer_width { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name width] +} - return "( $x_min $y_min ) ( $x_max $y_max )" - } +proc get_layer_non_preferred_width { layer_name } { + variable layer_info + if { [dict exists $layer_info layers $layer_name non_preferred_width] } { + return [dict get $layer_info layers $layer_name non_preferred_width] + } + return [dict get $layer_info layers $layer_name width] +} - proc write {design} { - out "###############################################################" - if {[dict exists $design tool]} { - out "# Created by [dict get $design tool]" - } - out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" - out "###############################################################" - - out "VERSION 5.8 ;" - out "DIVIDERCHAR \"/\" ;" - out "BUSBITCHARS \"\[\]\" ;" - out "DESIGN [dict get $design name] ;" - out "UNITS DISTANCE MICRONS [dict get $design units] ;" - out "" +proc get_layer_direction { layer_name } { + variable layer_info + return [dict get $layer_info layers $layer_name direction] +} - if {[dict exists $design properties]} { - out "PROPERTYDEFINITIONS " - if {[dict exists $design properties core_area]} { - out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" - out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" - out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" - out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" - } - out "END PROPERTYDEFINITIONS" - } +proc get_line_direction { points } { + if { [lindex $points 0 0] == [lindex $points 1 0] } { + set direction "VERTICAL" + } elseif { [lindex $points 0 1] == [lindex $points 1 1] } { + set direction "HORIZONTAL" + } else { + error "Non orthogonal line $points" + } + return $direction +} +proc get_line_width { layer_name points } { + set direction [get_line_direction $points] + + if { [get_layer_direction $layer_name] == $direction } { + return [get_layer_width $layer_name] + } else { + return [get_layer_non_preferred_width $layer_name] + } +} - out "" - out "DIEAREA ( [lrange [dict get $design die_area] 0 1] ) ( [lrange [dict get $design die_area] 2 3] ) ;" +proc get_extended_line { layer_name points } { + if { [llength [lindex $points 1]] == 1 } { + return "( [lindex $points 0] ) [lindex $points 1]" + } + + set direction [get_line_direction $points] + + if { $direction == [get_layer_direction $layer_name] } { + set extension [expr [get_layer_non_preferred_width $layer_name] / 2] + } else { + set extension [expr [get_layer_width $layer_name] / 2] + } + + if { $direction == "VERTICAL" } { + set x_min [lindex $points 0 0] + set x_max [lindex $points 0 0] + set y_min [expr min([lindex $points 0 1], [lindex $points 1 1]) - $extension] + set y_max [expr max([lindex $points 0 1], [lindex $points 1 1]) + $extension] + } else { + set x_min [expr min([lindex $points 0 0], [lindex $points 1 0])] + set x_max [expr max([lindex $points 0 0], [lindex $points 1 0])] + set y_min [lindex $points 0 1] + set y_max [lindex $points 0 1] + } + + return "( $x_min $y_min ) ( $x_max $y_max )" +} - if {[dict exists $design tracks]} { - } - - if {[dict exists $design rows]} { - foreach idx [lsort -integer [dict keys $design rows]] { - out -nonewline "ROW ROW_$idx [dict keys $design rows $idx site] [dict keys $design rows $idx start] [dict keys $design rows $idx height] [dict keys $design rows $idx orientation]" - out " DO [dict keys $design rows $idx num_sites] BY 1 STEP [dict keys $design rows $idx site_width] 0 ;" +proc write { design } { + out "###############################################################" + if { [dict exists $design tool] } { + out "# Created by [dict get $design tool]" + } + out "# Created on: [clock format [clock seconds] -format {%A, %d %B %Y}]" + out "###############################################################" + + out "VERSION 5.8 ;" + out "DIVIDERCHAR \"/\" ;" + out "BUSBITCHARS \"\[\]\" ;" + out "DESIGN [dict get $design name] ;" + out "UNITS DISTANCE MICRONS [dict get $design units] ;" + out "" + + if { [dict exists $design properties] } { + out "PROPERTYDEFINITIONS " + if { [dict exists $design properties core_area] } { + out "DESIGN FE_CORE_BOX_LL_X REAL [lindex [dict get $design properties core_area] 0] ;" + out "DESIGN FE_CORE_BOX_UR_X REAL [lindex [dict get $design properties core_area] 1] ;" + out "DESIGN FE_CORE_BOX_LL_Y REAL [lindex [dict get $design properties core_area] 2] ;" + out "DESIGN FE_CORE_BOX_UR_Y REAL [lindex [dict get $design properties core_area] 3] ;" + } + out "END PROPERTYDEFINITIONS" + } + + out "" + out "DIEAREA ( [lrange [dict get $design die_area] 0 1] )\ + ( [lrange [dict get $design die_area] 2 3] ) ;" + + if { [dict exists $design tracks] } { + + } + + if { [dict exists $design rows] } { + foreach idx [lsort -integer [dict keys $design rows]] { + out -nonewline [concat \ + "ROW ROW_$idx" \ + [dict get $design rows $idx site] \ + [dict get $design rows $idx start] \ + [dict get $design rows $idx height] \ + [dict get $design rows $idx orientation]] + out " DO [dict get $design rows $idx num_sites] BY 1 STEP\ + [dict get $design rows $idx site_width] 0 ;" + } + } + + if { [dict exists $design pins] } { + out "" + out "PINS [dict size [dict get $design pins]] ;" + dict for {pin_name pin} [dict get $design pins] { + out -nonewline \ + "- $pin_name + NET [dict get $pin net_name]\ + + DIRECTION [dict get $pin direction]" + if { [dict exists $pin use] } { + out -nonewline " + USE [dict get $pin use]" + } + if { [dict exists $pin special] } { + out -nonewline " + SPECIAL" + } + out "" + if { [dict exists $pin ports] } { + foreach port [dict get $pin ports] { + if { [llength [dict get $design pins $pin_name ports]] > 1 } { + out " + PORT " + } + dict for {layer_name layer_info} [dict get $port layers] { + foreach shape [dict get $port layers $layer_name shapes] { + out -nonewline " + LAYER $layer_name " + if { [dict exists $port layers $layer_name spacing] } { + out "SPACING [dict get $port layers $layer_name spacing] " + } elseif { [dict exists $port layers $layer_name designrulewidth] } { + out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " + } + out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " } - } - - if {[dict exists $design pins]} { - out "" - out "PINS [dict size [dict get $design pins]] ;" - dict for {pin_name pin} [dict get $design pins] { - out -nonewline "- $pin_name + NET [dict get $pin net_name] + DIRECTION [dict get $pin direction] " - if {[dict exists $pin use]} { - out -nonewline "+ USE [dict get $pin use] " - } - if {[dict exists $pin special]} { - out -nonewline "+ SPECIAL " - } - out "" - if {[dict exists $pin ports]} { - foreach port [dict get $pin ports] { - if {[llength [dict get $design pins $pin_name ports]] > 1} { - out " + PORT " - } - dict for {layer_name layer_info} [dict get $port layers] { - foreach shape [dict get $port layers $layer_name shapes] { - out -nonewline " + LAYER $layer_name " - if {[dict exists $port layers $layer_name spacing]} { - out "SPACING [dict get $port layers $layer_name spacing] " - } elseif {[dict exists $port layers $layer_name designrulewidth]} { - out "DESIGNRULEWIDTH [dict get $port layers $layer_name designrulewidth] " - } - out "( [lrange [dict get $shape rect] 0 1] ) ( [lrange [dict get $shape rect] 2 3] ) " - } - } - if {[dict exists $port fixed]} { - out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " - } elseif {[dict exists $shape placed]} { - out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " - } - } - out " ;" - } + } + if { [dict exists $port fixed] } { + out " + FIXED ( [dict get $port fixed] ) [dict get $port orientation] " + } elseif { [dict exists $shape placed] } { + out " + PLACED ( [dict get $port placed] ) [dict get $port orientation] " + } + } + out " ;" + } + } + out "END PINS" + } + + ##### Generating via rules + + if { [dict exists $design physical_viarules] } { + out "" + out "VIAS [dict size [dict get $design physical_viarules]] ;" + dict for {name rule} [dict get $design physical_viarules] { + out "- $name" + out " + VIARULE [dict get $rule rule]" + out " + CUTSIZE [dict get $rule cutsize]" + out " + LAYERS [dict get $rule layers]" + out " + CUTSPACING [dict get $rule cutspacing]" + out " + ENCLOSURE [dict get $rule enclosure]" + out " + ROWCOL [dict get $rule rowcol]" + out " ;" + } + out "END VIAS" + } + + if { [dict exists $design components] } { + out "" + out "COMPONENTS [dict size [dict get $design components]] ;" + dict for {inst_name inst} [dict get $design components] { + out -nonewline "- $inst_name [dict get $inst cell_name] " + if { [dict exists $inst fixed] } { + out -nonewline "+ FIXED ( [dict get $inst fixed] ) " + } elseif { [dict exists $inst placed] } { + out -nonewline "+ PLACED ( [dict get $inst placed] ) " + } + if { [dict exists $inst orientation] } { + out -nonewline "[dict get $inst orientation] " + } + out ";" + } + out "END COMPONENTS" + } + + if { [dict exists $design nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design nets]] ;" + dict for {net_name net} [dict get $design nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set type "ROUTED" + foreach route [dict get $net routes] { + set first_point [lindex [dict get $route points] 0] + + foreach point [lrange [dict get $route points] 1 end] { + set points [get_extended_line [dict get $route layer] [list $first_point $point]] + if { [dict exists $route shape] } { + set shape " + SHAPE [dict get $route shape] " + } else { + set shape "" } - out "END PINS" - } - - ##### Generating via rules - - if {[dict exists $design physical_viarules]} { - out "" - out "VIAS [dict size [dict get $design physical_viarules]] ;" - dict for {name rule} [dict get $design physical_viarules] { - out "- $name" - out " + VIARULE [dict get $rule rule]" - out " + CUTSIZE [dict get $rule cutsize]" - out " + LAYERS [dict get $rule layers]" - out " + CUTSPACING [dict get $rule cutspacing]" - out " + ENCLOSURE [dict get $rule enclosure]" - out " + ROWCOL [dict get $rule rowcol]" - out " ;" + if { [dict exists $route mask] } { + set mask "MASK [dict get $route mask] " + } else { + set mask "" } - out "END VIAS" - } - - if {[dict exists $design components]} { - out "" - out "COMPONENTS [dict size [dict get $design components]] ;" - dict for {inst_name inst} [dict get $design components] { - out -nonewline "- $inst_name [dict get $inst cell_name] " - if {[dict exists $inst fixed]} { - out -nonewline "+ FIXED ( [dict get $inst fixed] ) " - } elseif {[dict exists $inst placed]} { - out -nonewline "+ PLACED ( [dict get $inst placed] ) " - } - if {[dict exists $inst orientation]} { - out -nonewline "[dict get $inst orientation] " - } - out ";" + if { [llength $point] == 2 } { + out -nonewline \ + " + $type [dict get $route layer]\ + [get_line_width [dict get $route layer] [list $first_point $point]] " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask + } else { + out -nonewline " + $type [dict get $route layer] 0 " + out -nonewline $shape + out -nonewline $points + out -nonewline $mask } - out "END COMPONENTS" - } - - if {[dict exists $design nets]} { out "" - out "SPECIALNETS [dict size [dict get $design nets]] ;" - dict for {net_name net} [dict get $design nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set type "ROUTED" - foreach route [dict get $net routes] { - set first_point [lindex [dict get $route points] 0] - - foreach point [lrange [dict get $route points] 1 end] { - set points [get_extended_line [dict get $route layer] [list $first_point $point]] - if {[dict exists $route shape]} { - set shape " + SHAPE [dict get $route shape] " - } else { - set shape "" - } - if {[dict exists $route mask]} { - set mask "MASK [dict get $route mask] " - } else { - set mask "" - } - if {[llength $point] == 2} { - out -nonewline " + $type [dict get $route layer] [get_line_width [dict get $route layer] [list $first_point $point]] " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } else { - out -nonewline " + $type [dict get $route layer] 0 " - out -nonewline $shape - out -nonewline $points - out -nonewline $mask - } - out "" - set first_point $point - set type "ROUTED" - } - } - } - out " + USE [dict get $net use]\n ;" - } - out "END SPECIALNETS" + set first_point $point + set type "ROUTED" + } } - - if {[dict exists $design special_nets]} { - out "" - out "SPECIALNETS [dict size [dict get $design special_nets]] ;" - dict for {net_name net} [dict get $design special_nets] { - out -nonewline "- $net_name " - foreach connection [dict get $net connections] { - out " ( $connection )" - } - if {[dict exists $net routes]} { - set route [lindex [dict get $net routes] 0] - out -nonewline " + ROUTED [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - - foreach route [lrange [dict get $net routes] 1 end] { - out " NEW [dict get $route layer] [expr round([dict get $route width])] + SHAPE [dict get $route shape] " - foreach point [dict get $route points] { - out -nonewline " $point" - } - out "" - } - } - out " + USE [dict get $net use]\n ;" - } - out "\nEND SPECIALNETS" + } + out " + USE [dict get $net use]\n ;" + } + out "END SPECIALNETS" + } + + if { [dict exists $design special_nets] } { + out "" + out "SPECIALNETS [dict size [dict get $design special_nets]] ;" + dict for {net_name net} [dict get $design special_nets] { + out -nonewline "- $net_name " + foreach connection [dict get $net connections] { + out " ( $connection )" + } + if { [dict exists $net routes] } { + set route [lindex [dict get $net routes] 0] + out -nonewline \ + " + ROUTED [dict get $route layer]\ + [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" } - out "" - out "END DESIGN" + + foreach route [lrange [dict get $net routes] 1 end] { + out \ + " NEW [dict get $route layer] [expr round([dict get $route width])]\ + + SHAPE [dict get $route shape] " + foreach point [dict get $route points] { + out -nonewline " $point" + } + out "" + } + } + out " + USE [dict get $net use]\n ;" } + out "\nEND SPECIALNETS" + } - proc new_design {design_name units {die_area {0 0 0 0}}} { - variable designs - variable current_design - set current_design $design_name + out "" + out "END DESIGN" +} - dict set designs $current_design [list name $design_name units $units die_area $die_area] - } +proc new_design { design_name units { die_area {0 0 0 0} } } { + variable designs + variable current_design + set current_design $design_name - proc add_component {inst_name cell_name x y orientation status} { - variable designs - variable current_design + dict set designs $current_design [list name $design_name units $units die_area $die_area] +} - dict set designs $current_design components $inst_name inst_name $inst_name - dict set designs $current_design components $inst_name cell_name $cell_name - dict set designs $current_design components $inst_name $status [list $x $y] - dict set designs $current_design components $inst_name orientation $orientation - } - - proc get_current_design {} { - variable designs - variable current_design +proc add_component { inst_name cell_name x y orientation status } { + variable designs + variable current_design - return [dict get $designs $current_design] - } - - proc write_cells {cells} { - dict for {cell_name cell} $cells { - def open ${cell_name}.def - def write $cell - def close - } - } - - proc set_def_units {units} { - variable def_units - - set def_units $units - } - - proc get_def_units {} { - variable def_units - - return $def_units - } - - namespace export new_design add_component get_current_design - namespace export set_def_units get_def_units shift_origin shift_rect - namespace export open close out write write_cells - namespace export set_layer_info - namespace ensemble create + dict set designs $current_design components $inst_name inst_name $inst_name + dict set designs $current_design components $inst_name cell_name $cell_name + dict set designs $current_design components $inst_name $status [list $x $y] + dict set designs $current_design components $inst_name orientation $orientation +} + +proc get_current_design { } { + variable designs + variable current_design + + return [dict get $designs $current_design] +} + +proc write_cells { cells } { + dict for {cell_name cell} $cells { + def open ${cell_name}.def + def write $cell + def close + } +} + +proc set_def_units { units } { + variable def_units + + set def_units $units +} + +proc get_def_units { } { + variable def_units + + return $def_units +} + +namespace export new_design add_component get_current_design +namespace export set_def_units get_def_units shift_origin shift_rect +namespace export open close out write write_cells +namespace export set_layer_info +namespace ensemble create } package provide lefdef 1.0.0 diff --git a/flow/util/cell-veneer/pkgIndex.tcl b/flow/util/cell-veneer/pkgIndex.tcl index 806a34f75f..45719f8484 100644 --- a/flow/util/cell-veneer/pkgIndex.tcl +++ b/flow/util/cell-veneer/pkgIndex.tcl @@ -1,3 +1,3 @@ -package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] +# tclint-disable command-args +package ifneeded lefdef 1.0.0 [list source [file join $dir lefdef.tcl]] package ifneeded wrapper 1.0.0 [list source [file join $dir wrap_stdcells.tcl]] - diff --git a/flow/util/cell-veneer/wrap.tcl b/flow/util/cell-veneer/wrap.tcl index 3ca893b8fd..8fa52113ab 100755 --- a/flow/util/cell-veneer/wrap.tcl +++ b/flow/util/cell-veneer/wrap.tcl @@ -5,7 +5,7 @@ exec tclsh "$0" ${1+"$@"} package require wrapper package require lefdef -if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { +if { [set idx [lsearch -exact $argv {-cfg}]] > -1 } { set cfg_file [lindex $argv [expr $idx + 1]] set argv [lreplace $argv $idx [expr $idx + 1]] @@ -15,7 +15,7 @@ if {[set idx [lsearch -exact $argv {-cfg}]] > -1} { wrapper critical 2 "no configuration data loaded" } -if {[lindex $argv 0] == "-macro"} { +if { [lindex $argv 0] == "-macro" } { set lef_files [lrange $argv 1 end] set cells {} foreach file_name $lef_files { diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl index f6abb4a674..f6ad587cc6 100644 --- a/flow/util/cell-veneer/wrap_stdcells.tcl +++ b/flow/util/cell-veneer/wrap_stdcells.tcl @@ -1,701 +1,732 @@ namespace eval wrapper { - variable wrapper_cfg - - proc set_message {level message} { - return "\[$level\] $message" - } +variable wrapper_cfg - proc debug {message} { - set state [info frame -1] - set str "" - if {[dict exists $state file]} { - set str "$str[dict get $state file]:" - } - if {[dict exists $state proc]} { - set str "$str[dict get $state proc]:" - } - if {[dict exists $state line]} { - set str "$str[dict get $state line]" - } - puts [set_message DEBUG "$str: $message"] - } +proc set_message { level message } { + return "\[$level\] $message" +} - proc information {id message} { - puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +proc debug { message } { + set state [info frame -1] + set str "" + if { [dict exists $state file] } { + set str "$str[dict get $state file]:" } - - proc warning {id message} { - puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state proc] } { + set str "$str[dict get $state proc]:" } - - proc err {id message} { - puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] + if { [dict exists $state line] } { + set str "$str[dict get $state line]" } + puts [set_message DEBUG "$str: $message"] +} - proc critical {id message} { - error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] - } +proc information { id message } { + puts [set_message INFO [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc warning { id message } { + puts [set_message WARN [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc err { id message } { + puts [set_message ERROR [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc critical { id message } { + error [set_message CRIT [format "\[WRAP-%04d\] %s" $id $message]] +} + +proc find_cells_with_m2_pins { } { + set cells [lef get_cells] + set data {} + + dict for {cell_name cell} $cells { + dict for {pin_name pin} [dict get $cell pins] { + foreach port [dict get $pin ports] { + set offset [wrapper::get_port_offset $port] + set layer_name "M2" + if { [dict exists $port layers $layer_name] } { + foreach shape [dict get $port layers $layer_name shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] - proc find_cells_with_m2_pins {} { - set cells [lef get_cells] - set data {} - - dict for {cell_name cell} $cells { - dict for {pin_name pin} [dict get $cell pins] { - foreach port [dict get $pin ports] { - set offset [wrapper::get_port_offset $port] - set layer_name "M2" - if {[dict exists $port layers $layer_name]} { - foreach shape [dict get $port layers $layer_name shapes] { - - set rect [absolute_rectangle [dict get $shape rect] $offset] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {[dict exists $data $cell_name pins $pin_name]} { - set pins [dict get $data $cell_name pins $pin_name] - } else { - set pins {} - } - if {round($y2 - $y1) > 64} { - error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" - } - lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name pins $pin_name $pins + if { [dict exists $data $cell_name pins $pin_name] } { + set pins [dict get $data $cell_name pins $pin_name] + } else { + set pins {} + } + if { round($y2 - $y1) > 64 } { + error "cell $cell_name, pin: $pin_name, [expr $y2 - $y1] -> vertical M2 pin: $y2, $y1" } + lappend pins [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name pins $pin_name $pins } } } + } - if {[dict exists $data $cell_name]} { - dict for {layer_name obstructions} [dict get $cell obstructions] { - if {$layer_name == "M2"} { - foreach obs $obstructions { - set rect [dict get $obs rect] - set x1 [lindex $rect 0] - set y1 [lindex $rect 1] - set x2 [lindex $rect 2] - set y2 [lindex $rect 3] - - if {round(($y2 - $y1)) > 64} { - error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" - } - if {[dict exists $data $cell_name blockages]} { - set blockages [dict get $data $cell_name blockages] - } else { - set blockages {} - } - - lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] - dict set data $cell_name blockages $blockages + if { [dict exists $data $cell_name] } { + dict for {layer_name obstructions} [dict get $cell obstructions] { + if { $layer_name == "M2" } { + foreach obs $obstructions { + set rect [dict get $obs rect] + set x1 [lindex $rect 0] + set y1 [lindex $rect 1] + set x2 [lindex $rect 2] + set y2 [lindex $rect 3] + + if { round(($y2 - $y1)) > 64 } { + error "cell $cell_name, blockage, [expr $y2 - $y1] -> vertical blockage: $y2, $y1" + } + if { [dict exists $data $cell_name blockages] } { + set blockages [dict get $data $cell_name blockages] + } else { + set blockages {} } + + lappend blockages [list track [expr round(($y2 + $y1) / 2 / 128)] from $x1 to $x2] + dict set data $cell_name blockages $blockages } } } } - - return $data } - proc clear_left {physical_pin blockages} { - set track [dict get $physical_pin track] + return $data +} - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage to] < [dict get $physical_pin from]} { - return 0 - } +proc clear_left { physical_pin blockages } { + set track [dict get $physical_pin track] + + foreach blockage $blockages { + if { + [dict get $blockage track] == $track && + [dict get $blockage to] < [dict get $physical_pin from] + } { + return 0 } - return 1 } + return 1 +} - proc clear_right {physical_pin blockages} { - set track [dict get $physical_pin track] +proc clear_right { physical_pin blockages } { + set track [dict get $physical_pin track] - foreach blockage $blockages { - if {[dict get $blockage track] == $track && [dict get $blockage from] > [dict get $physical_pin to]} { - return 0 - } + foreach blockage $blockages { + if { + [dict get $blockage track] == $track && + [dict get $blockage from] > [dict get $physical_pin to] + } { + return 0 } - return 1 } + return 1 +} - proc create_def_wrapper {cell_name new_cell_name} { - variable tech - set orig_cell [lef get_cell $cell_name] - - set design $orig_cell - - dict set design name $new_cell_name - dict set design tool "cell-veneer" - dict set design units 2000 - dict set design use_sheet_obstructions 0 - if {[dict exists $tech use_sheet_obstructions]} { - dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] - } - if {[dict exists $tech blockage_layers]} { - dict set design blockage_layers [dict get $tech blockage_layers] - } - dict set design die_area [dict get $orig_cell die_area] - - dict set design components u0 cell_name $cell_name - dict set design components u0 placed "0 0" - dict set design components u0 orientation "N" - - dict for {pin_name pin} [dict get $orig_cell pins] { - - dict set design pins $pin_name net_name $pin_name - if {[dict exists $pin use]} { - if {[dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND"} { - dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] - dict set design special_nets $pin_name use [dict get $pin use] - } else { - dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] - dict set design nets $pin_name use [dict get $pin use] - } +proc create_def_wrapper { cell_name new_cell_name } { + variable tech + set orig_cell [lef get_cell $cell_name] + + set design $orig_cell + + dict set design name $new_cell_name + dict set design tool "cell-veneer" + dict set design units 2000 + dict set design use_sheet_obstructions 0 + if { [dict exists $tech use_sheet_obstructions] } { + dict set design use_sheet_obstructions [dict get $tech use_sheet_obstructions] + } + if { [dict exists $tech blockage_layers] } { + dict set design blockage_layers [dict get $tech blockage_layers] + } + dict set design die_area [dict get $orig_cell die_area] + + dict set design components u0 cell_name $cell_name + dict set design components u0 placed "0 0" + dict set design components u0 orientation "N" + + dict for {pin_name pin} [dict get $orig_cell pins] { + dict set design pins $pin_name net_name $pin_name + if { [dict exists $pin use] } { + if { [dict get $pin use] == "POWER" || [dict get $pin use] == "GROUND" } { + dict set design special_nets $pin_name connections [list "PIN $pin_name" "* $pin_name"] + dict set design special_nets $pin_name use [dict get $pin use] } else { dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] + dict set design nets $pin_name use [dict get $pin use] } + } else { + dict set design nets $pin_name connections [list "PIN $pin_name" "u0 $pin_name"] } - - return $design } - - proc get_port_offset {port} { - if {[dict exists $port fixed]} { - return [dict get $port fixed] - } elseif {[dict exists $port placed]} { - return [dict get $port fixed] - } - return [list 0 0] + return $design +} + +proc get_port_offset { port } { + if { [dict exists $port fixed] } { + return [dict get $port fixed] + } elseif { [dict exists $port placed] } { + return [dict get $port fixed] } - proc move_m2_pins_to_edge {cell_name cell_data} { - variable wrapper_cfg - - set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] - set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] - set def_units [dict get $wrapper_cfg def_units] - set layer_name [dict get $wrapper_cfg remove_pins layer] - set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] - set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] - set new_pin_layer_width [expr round([dict get $wrapper_cfg layer $new_pin_layer_name width] * $def_units)] - set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] - set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - set lower_y [expr 2 * 128] - set upper_y [expr 8 * 128] - set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] - - set right_padding 0 - set left_padding 0 - - # Determine which sides to route the M2 pins to and create a wire - dict for {pin_name pin} [dict get $cell_data pins] { - set wires {} - foreach physical_pin $pin { - if {[dict get $physical_pin to] >= [expr $cell_width / 2.0]} { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } elseif {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } else { - set direction blocked - } - } else { + return [list 0 0] +} + +proc move_m2_pins_to_edge { cell_name cell_data } { + variable wrapper_cfg + + set wrapper_cell [lef get_cell [dict get $wrapper_cfg padding_cell]] + set padding_cell_width [lindex [dict get $wrapper_cell die_area] 2] + set def_units [dict get $wrapper_cfg def_units] + set layer_name [dict get $wrapper_cfg remove_pins layer] + set layer_width [expr round([dict get $wrapper_cfg layer $layer_name width] * $def_units)] + set new_pin_layer_name [dict get $wrapper_cfg new_pins layer] + set new_pin_layer_width [expr round( \ + [dict get $wrapper_cfg layer $new_pin_layer_name width] * \ + $def_units \ + )] + set cell_width [lindex [dict get [lef get_cell $cell_name] die_area] 2] + set design [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + set lower_y [expr 2 * 128] + set upper_y [expr 8 * 128] + set via_overlap [expr round([dict get $wrapper_cfg via_overlap] * $def_units)] + + set right_padding 0 + set left_padding 0 + + # Determine which sides to route the M2 pins to and create a wire + dict for {pin_name pin} [dict get $cell_data pins] { + set wires {} + foreach physical_pin $pin { + if { [dict get $physical_pin to] >= ($cell_width / 2.0) } { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { set direction right + } elseif { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { + set direction left + } else { + set direction blocked } } else { - if {[dict exists $cell_data blockages]} { - if {[wrapper::clear_left $physical_pin [dict get $cell_data blockages]]} { - set direction left - } elseif {[wrapper::clear_right $physical_pin [dict get $cell_data blockages]]} { - set direction right - } else { - set direction blocked - } - } else { + set direction right + } + } else { + if { [dict exists $cell_data blockages] } { + if { [wrapper::clear_left $physical_pin [dict get $cell_data blockages]] } { set direction left + } elseif { [wrapper::clear_right $physical_pin [dict get $cell_data blockages]] } { + set direction right + } else { + set direction blocked } - } - - if {$direction == "blocked"} { - break - } - - set y [expr [dict get $physical_pin track] * 128] - if {$direction == "right"} { - set x1 [dict get $physical_pin to] - set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] - set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] - incr right_padding - } elseif {$direction == "left"} { - set x1 [dict get $physical_pin from] - set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] - set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] - incr left_padding - } - - # Route M2 out to the side of the block - lappend wires [list \ - layer $layer_name \ - points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]] - ] - set new_wire [list \ - layer "M1" \ - points [list [list $x2 $lower_y] [list $x2 $upper_y]] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_wire mask [dict get $wrapper_cfg new_pins mask] - } - lappend wires $new_wire - # Add the new M2 wire as an obstruction when writing the LEF of the cell - if {[dict exists $design obstructions $layer_name]} { - set obstructions [dict get $design obstructions $layer_name] } else { - set obstructions {} + set direction left } - lappend obstructions [list \ - rect [list \ - [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ - [expr max($x1, $x3)] [expr $y + round($layer_width / 2)] \ - ] - ] - dict set design obstructions $layer_name $obstructions + } + if { $direction == "blocked" } { break } - if {$direction == "blocked"} { - break + set y [expr [dict get $physical_pin track] * 128] + if { $direction == "right" } { + set x1 [dict get $physical_pin to] + set x2 [expr $cell_width + ($padding_cell_width * ($right_padding + 1))] + set x3 [expr $cell_width + ($padding_cell_width * ($right_padding + 1)) + $via_overlap] + incr right_padding + } elseif { $direction == "left" } { + set x1 [dict get $physical_pin from] + set x2 [expr 0 - ($padding_cell_width * ($left_padding + 1))] + set x3 [expr 0 - ($padding_cell_width * ($left_padding + 1)) - $via_overlap] + incr left_padding } - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers "M2"]} { - set offset [get_port_offset $port] - # Copy all M2 pins on instance to M2 obstructions - foreach shape [dict get $port layers "M2" shapes] { - set pin_rect [absolute_rectangle [dict get $shape rect] $offset] - - set m2_obstructions [dict get $design obstructions M2] - lappend m2_obstructions [list \ - rect $pin_rect \ - ] - dict set design obstructions M2 $m2_obstructions - } - # Replace the M2 port with an M1 port which is now at the side of the cells - set new_pin_rect [list [expr round($x2 - ($new_pin_layer_width / 2))] $lower_y [expr round($x2 + ($new_pin_layer_width / 2))] $upper_y] - if {[dict exists $port layers "M1" shapes]} { - set shapes [dict get $port layers "M1" shapes] - } else { - set shapes {} - } - set new_shape [list \ - rect [relative_rectangle $new_pin_rect $offset] \ - ] - if {[dict exists $wrapper_cfg new_pins mask]} { - dict set new_shape mask [dict get $wrapper_cfg new_pins mask] - } - lappend shapes $new_shape - dict set port layers M1 shapes $shapes - } - dict set port layers [dict remove [dict get $port layers] "M2"] - lappend ports $port + # Route M2 out to the side of the block + lappend wires [list \ + layer $layer_name \ + points [list [list $x1 $y] [list $x3 $y] [dict get $wrapper_cfg via]]] + set new_wire [list \ + layer "M1" \ + points [list [list $x2 $lower_y] [list $x2 $upper_y]]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_wire mask [dict get $wrapper_cfg new_pins mask] } - dict set design pins $pin_name ports $ports - dict set design nets $pin_name routes $wires + lappend wires $new_wire + # Add the new M2 wire as an obstruction when writing the LEF of the cell + if { [dict exists $design obstructions $layer_name] } { + set obstructions [dict get $design obstructions $layer_name] + } else { + set obstructions {} + } + lappend obstructions [list \ + rect [list \ + [expr min($x1, $x3)] [expr $y - round($layer_width / 2)] \ + [expr max($x1, $x3)] [expr $y + round($layer_width / 2)]]] + dict set design obstructions $layer_name $obstructions + + break } - # Adjust the placement of the component if we have padding on the left - if {$left_padding > 0} { - dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + if { $direction == "blocked" } { + break } - # Add in the cell padding - set pad_idx 0 - if {$left_padding > 0} { - for {set i 0} {$i <= $left_padding} {incr i} { - set x [expr $padding_cell_width * ($i + 1) * -1] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers "M2"] } { + set offset [get_port_offset $port] + # Copy all M2 pins on instance to M2 obstructions + foreach shape [dict get $port layers "M2" shapes] { + set pin_rect [absolute_rectangle [dict get $shape rect] $offset] + + set m2_obstructions [dict get $design obstructions M2] + lappend m2_obstructions [list \ + rect $pin_rect] + dict set design obstructions M2 $m2_obstructions + } + # Replace the M2 port with an M1 port which is now at the side of the cells + set new_pin_rect [concat \ + [list \ + [expr round($x2 - ($new_pin_layer_width / 2))] \ + $lower_y \ + [expr round($x2 + ($new_pin_layer_width / 2))] \ + $upper_y]] + if { [dict exists $port layers "M1" shapes] } { + set shapes [dict get $port layers "M1" shapes] + } else { + set shapes {} + } + set new_shape [list \ + rect [relative_rectangle $new_pin_rect $offset]] + if { [dict exists $wrapper_cfg new_pins mask] } { + dict set new_shape mask [dict get $wrapper_cfg new_pins mask] } - incr pad_idx + lappend shapes $new_shape + dict set port layers M1 shapes $shapes } - } else { - set left_padding -1 + dict set port layers [dict remove [dict get $port layers] "M2"] + lappend ports $port } - if {$right_padding > 0} { - for {set i 0} {$i <= $right_padding} {incr i} { - set x [expr $padding_cell_width * $i + $cell_width] - set y 0 - dict set design components p$pad_idx inst_name p$pad_idx - dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] - dict set design components p$pad_idx placed [list $x $y] - dict set design components p$pad_idx orientation N - - # Add all obstructions of padding cell to obstructions of wrapper - dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { - if {[dict exists $design obstructions $layer_name]} { - set current_obstructions [dict get $design obstructions $layer_name] - } else { - set current_obstructions {} - } - foreach obs $obstructions { - dict set obs rect [def shift_rect [dict get $obs rect] $x $y] - lappend current_obstructions $obs - } - dict set design obstructions $layer_name $current_obstructions + dict set design pins $pin_name ports $ports + dict set design nets $pin_name routes $wires + } + + # Adjust the placement of the component if we have padding on the left + if { $left_padding > 0 } { + dict set design components u0 placed [list [expr $padding_cell_width * ($left_padding + 1)] 0] + } + + # Add in the cell padding + set pad_idx 0 + if { $left_padding > 0 } { + for { set i 0 } { $i <= $left_padding } { incr i } { + set x [expr $padding_cell_width * ($i + 1) * -1] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs } - incr pad_idx + dict set design obstructions $layer_name $current_obstructions } + incr pad_idx } + } else { + set left_padding -1 + } + if { $right_padding > 0 } { + for { set i 0 } { $i <= $right_padding } { incr i } { + set x [expr $padding_cell_width * $i + $cell_width] + set y 0 + dict set design components p$pad_idx inst_name p$pad_idx + dict set design components p$pad_idx cell_name [dict get $wrapper_cfg padding_cell] + dict set design components p$pad_idx placed [list $x $y] + dict set design components p$pad_idx orientation N + + # Add all obstructions of padding cell to obstructions of wrapper + dict for {layer_name obstructions} [dict get $wrapper_cell obstructions] { + if { [dict exists $design obstructions $layer_name] } { + set current_obstructions [dict get $design obstructions $layer_name] + } else { + set current_obstructions {} + } + foreach obs $obstructions { + dict set obs rect [def shift_rect [dict get $obs rect] $x $y] + lappend current_obstructions $obs + } + dict set design obstructions $layer_name $current_obstructions + } + incr pad_idx + } + } - # Adjust origin so that 0,0 is the lowr left corner of the cell - set adjustment [expr $padding_cell_width * ($left_padding + 1)] - set design [def shift_origin $design $adjustment 0] - - dict set design die_area [list \ - 0 \ - 0 \ - [expr [lindex [dict get $design die_area] 2] + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)] \ - [lindex [dict get $design die_area] 3] \ - ] - - # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper - # VDD overlaps by 0.009 on each side - # VSS overlaps by 0.009 on each side - # VNW overlaps the edges of the cell by 0.1 on both sides - set extend_ports { + # Adjust origin so that 0,0 is the lowr left corner of the cell + set adjustment [expr $padding_cell_width * ($left_padding + 1)] + set design [def shift_origin $design $adjustment 0] + + dict set design die_area [list \ + 0 \ + 0 \ + [concat \ + [expr [lindex [dict get $design die_area] 2] + \ + (($pad_idx - ($left_padding + 1)) * $padding_cell_width)]] \ + [lindex [dict get $design die_area] 3]] + + # Extend VDD, VSS, VPW, VNW pins to be the width of the wrapper + # VDD overlaps by 0.009 on each side + # VSS overlaps by 0.009 on each side + # VNW overlaps the edges of the cell by 0.1 on both sides + set extend_ports { VDD {layer M1 overlap 0.009} VSS {layer M1 overlap 0.009} VNW {layer NW overlap 0.1} VPW {layer SXCUT overlap 0} } - dict for {pin_name info} $extend_ports { - set layer [dict get $info layer] - set overlap [dict get $info overlap] - - set ports {} - foreach port [dict get $design pins $pin_name ports] { - if {[dict exists $port layers $layer]} { - set shapes {} - set offset [get_port_offset $port] - - foreach shape [dict get $port layers $layer shapes] { - set rect [absolute_rectangle [dict get $shape rect] $offset] - dict set shape rect [relative_rectangle \ - [list \ - [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ - [lindex $rect 1] \ - [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ - [lindex $rect 3] \ - ] \ - $offset \ - ] - lappend shapes $shape - } - dict set port layers $layer shapes $shapes + dict for {pin_name info} $extend_ports { + set layer [dict get $info layer] + set overlap [dict get $info overlap] + + set ports {} + foreach port [dict get $design pins $pin_name ports] { + if { [dict exists $port layers $layer] } { + set shapes {} + set offset [get_port_offset $port] + + foreach shape [dict get $port layers $layer shapes] { + set rect [absolute_rectangle [dict get $shape rect] $offset] + dict set shape rect [relative_rectangle \ + [list \ + [expr [lindex [dict get $design die_area] 0] - [expr round($overlap * $def_units)]] \ + [lindex $rect 1] \ + [expr [lindex [dict get $design die_area] 2] + [expr round($overlap * $def_units)]] \ + [lindex $rect 3]] \ + $offset] + lappend shapes $shape } - lappend ports $port + dict set port layers $layer shapes $shapes } - dict set design pins $pin_name ports $ports + lappend ports $port } - - return $design + dict set design pins $pin_name ports $ports } - proc build_wrappers {data} { - variable wrapper_cfg - - set designs {} + return $design +} - dict for {cell_name cell_data} $data { - set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] - dict set designs [dict get $data name] $data - } +proc build_wrappers { data } { + variable wrapper_cfg + + set designs {} - return $designs + dict for {cell_name cell_data} $data { + set data [move_m2_pins_to_edge $cell_name $cell_data $wrapper_cfg] + dict set designs [dict get $data name] $data } - proc get_pin_rect {port layer} { - if {[dict exists $port fixed]} { - set offset [dict get $port fixed] - } elseif {[dict exists $port placed]} { - set offset [dict get $port placed] - } else { - set offset [list 0 0] - } - - return [absolute_rectangle [dict get [lindex [dict get $port layers $layer shapes] 0] rect] $offset] + return $designs +} + +proc get_pin_rect { port layer } { + if { [dict exists $port fixed] } { + set offset [dict get $port fixed] + } elseif { [dict exists $port placed] } { + set offset [dict get $port placed] + } else { + set offset [list 0 0] } - - proc wrap_macro {cell_name} { - variable tech - set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] - debug "$tech" - debug "[dict get $wrapper use_sheet_obstructions]" - - set cell [lef get_cell $cell_name] - # debug "$cell_name" - - # Order the signal pins based on the y location of the pin - set pin_info {} - set net_info {} - set grid_pins {} - dict for {pin_name pin} [dict get $cell pins] { - if {[dict get $pin use] != "SIGNAL"} {continue} - - # CHEAT: Assume that there is only one port for each pin and one rectangle per layer - set port [lindex [dict get $pin ports] 0] - if {[dict exists $port layers C4]} { - set pin_rect [get_pin_rect $port C4] - dict set net_info $pin_name pin_layer "C4" - } elseif {[dict exists $port layers M3]} { - set pin_rect [get_pin_rect $port M3] - dict set net_info $pin_name pin_layer "M3" - } + return [absolute_rectangle \ + [dict get \ + [lindex \ + [dict get $port layers $layer shapes] 0] rect] $offset] +} - set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] - set grid_y [expr round((floor(([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / [dict get $tech pitch horizontal_track]) - 1))] +proc wrap_macro { cell_name } { + variable tech + set wrapper [wrapper::create_def_wrapper $cell_name ${cell_name}_mod] + debug "$tech" + debug "[dict get $wrapper use_sheet_obstructions]" + + set cell [lef get_cell $cell_name] + # debug "$cell_name" + + # Order the signal pins based on the y location of the pin + set pin_info {} + set net_info {} + set grid_pins {} + + dict for {pin_name pin} [dict get $cell pins] { + if { [dict get $pin use] != "SIGNAL" } { continue } + + # CHEAT: Assume that there is only one port for each pin and one rectangle per layer + set port [lindex [dict get $pin ports] 0] + if { [dict exists $port layers C4] } { + set pin_rect [get_pin_rect $port C4] + dict set net_info $pin_name pin_layer "C4" + } elseif { [dict exists $port layers M3] } { + set pin_rect [get_pin_rect $port M3] + dict set net_info $pin_name pin_layer "M3" + } - # Need to check that the grid point we're trying to use is going to be accessible. - # If it is not, then try the point 2 grid points higher - if {[dict exists $grid_pins $grid_y]} { - if {[dict exists [expr $grid_y + 2]]} { - puts "Cell $cell_name" - puts "Problem assigning pin grid - requested and upper grid points for $pin_name at $grid_y already allocated to [dict get $grid_pins $grid_y] and [dict get $grid_pins [expr $grid_y + 2]]" - exit -1 - } - set grid_y [expr $grid_y + 2] + set macro_pin_y [expr ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2] + set grid_y [expr round((floor( \ + ([lindex $pin_rect 1] + [lindex $pin_rect 3]) / 2 / \ + [dict get $tech pitch horizontal_track]) - 1))] + + # Need to check that the grid point we're trying to use is going to be accessible. + # If it is not, then try the point 2 grid points higher + if { [dict exists $grid_pins $grid_y] } { + if { [dict exists $grid_pins [expr $grid_y + 2]] } { + puts "Cell $cell_name" + puts [concat "Problem assigning pin grid - requested and upper grid points " \ + "for $pin_name at " \ + "$grid_y already allocated to [dict get $grid_pins $grid_y] and " \ + "[dict get $grid_pins [expr $grid_y + 2]]"] + exit -1 } - dict set grid_pins $grid_y $pin_name - - dict set net_info $pin_name grid_y $grid_y - dict set net_info $pin_name macro_pin_y $macro_pin_y + set grid_y [expr $grid_y + 2] } + dict set grid_pins $grid_y $pin_name - set order [lsort -integer [dict keys $grid_pins]] - set prev_pos [lindex $order 0] + dict set net_info $pin_name grid_y $grid_y + dict set net_info $pin_name macro_pin_y $macro_pin_y + } - # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro - # If there is another pin close by, the we will need to have the jog 3 grids further in - dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 - foreach pin_pos [lrange $order 1 end] { - if {$pin_pos - $prev_pos > 3} { - dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 - } else { - dict set net_info [dict get $grid_pins $pin_pos] h_offset [expr [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] + 3] - } - set prev_pos $pin_pos + set order [lsort -integer [dict keys $grid_pins]] + set prev_pos [lindex $order 0] + + # tclint-disable-next-line line-length + # We will have a jog in the track, which needs to be on a vertical grid 3 units from the edge of the macro + # If there is another pin close by, the we will need to have the jog 3 grids further in + dict set net_info [dict get $grid_pins $prev_pos] h_offset 3 + foreach pin_pos [lrange $order 1 end] { + if { $pin_pos - $prev_pos > 3 } { + dict set net_info [dict get $grid_pins $pin_pos] h_offset 3 + } else { + dict set net_info [dict get $grid_pins $pin_pos] h_offset \ + [expr \ + [dict get $net_info [dict get $grid_pins $prev_pos] h_offset] \ + + 3] } + set prev_pos $pin_pos + } - # Work out where to place the instance based on the size of amount of jogging space needed - set wrapper_depth 0 - dict for {net_name net} [dict get $net_info] { - if {$wrapper_depth < [dict get $net h_offset]} { - set wrapper_depth [dict get $net h_offset] - } + # Work out where to place the instance based on the size of amount of jogging space needed + set wrapper_depth 0 + dict for {net_name net} [dict get $net_info] { + if { $wrapper_depth < [dict get $net h_offset] } { + set wrapper_depth [dict get $net h_offset] } - set wrapper_depth [expr $wrapper_depth + 3] - set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] - set width [expr round((floor([lef get_width $cell] / [dict get $tech pitch vertical_track]) + 1) * [dict get $tech pitch vertical_track] )] - set height [expr round((floor([lef get_height $cell] / [dict get $tech pitch horizontal_track]) + 1) * [dict get $tech pitch horizontal_track])] - - # Now we know where the macro is placed, we know the size of the wrapper - dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] - # debug "Set die area [dict get $wrapper die_area]" - # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM - - # Shift the wrapper so the lower left corner is at (0, 0) - set wrapper [def shift_origin $wrapper $macro_x 0] - # debug "Shifted die area [dict get $wrapper die_area]" - - # Add obstructions - foreach obs_layer {M3 J3 C4} { - set obstructions {} - if {[dict exists $wrapper obstructions $obs_layer]} { - set obstructions [dict get $wrapper obstructions $obs_layer] - } - # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" - lappend obstructions [list rect [list 0 0 $macro_x $height]] - # debug "[lindex $obstructions 0]" - dict set wrapper obstructions $obs_layer $obstructions - # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + } + set wrapper_depth [expr $wrapper_depth + 3] + set macro_x [expr $wrapper_depth * [dict get $tech pitch vertical_track]] + set width [expr round((floor([lef get_width $cell] / \ + [dict get $tech pitch vertical_track]) + 1) * \ + [dict get $tech pitch vertical_track])] + set height [expr round((floor([lef get_height $cell] / \ + [dict get $tech pitch horizontal_track]) + 1) * \ + [dict get $tech pitch horizontal_track])] + + # Now we know where the macro is placed, we know the size of the wrapper + dict set wrapper die_area [list [expr round(-1 * $macro_x)] 0 [expr $width] $height] + # debug "Set die area [dict get $wrapper die_area]" + + # tclint-disable-next-line line-length + # Now we know the maximum extent of the space needed for the job we can add in the pins the appropriate number of grids to the left of the RAM + + # Shift the wrapper so the lower left corner is at (0, 0) + set wrapper [def shift_origin $wrapper $macro_x 0] + # debug "Shifted die area [dict get $wrapper die_area]" + + # Add obstructions + foreach obs_layer {M3 J3 C4} { + set obstructions {} + if { [dict exists $wrapper obstructions $obs_layer] } { + set obstructions [dict get $wrapper obstructions $obs_layer] } - - - # Add wrapper pins and nets - dict for {net_name net} [dict get $net_info] { - set grid_y [dict get $net grid_y] - set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] - - set new_port [lindex [dict get $wrapper pins $net_name ports] 0] - dict set new_port layers {} - dict set new_port fixed [list 0 $y_position] - dict set new_port layers "C4" shapes [list \ - [list rect [list 0 [expr 0 - [dict get $tech layer C4 width] / 2] [dict get $tech layer C4 depth] [expr 0 + [dict get $tech layer C4 width] / 2]]] \ - ] - # debug "Replacing pin $net_name with $new_port" - dict set wrapper pins $net_name ports [list $new_port] - - set segments {} - - # First segment from RAM to jog location, to the y grid of the pin - set target_grid_point [expr ($wrapper_depth - [dict get $net h_offset]) * [dict get $tech pitch vertical_track]] - set width [dict get $tech layer [dict get $net pin_layer] width] + # debug "[lindex [dict get $wrapper obstructions $obs_layer] 0]" + lappend obstructions [list rect [list 0 0 $macro_x $height]] + # debug "[lindex $obstructions 0]" + dict set wrapper obstructions $obs_layer $obstructions + # debug "Added wrapper obstruction [list 0 0 [expr $width + $macro_x] $height]" + } + + + # Add wrapper pins and nets + dict for {net_name net} [dict get $net_info] { + set grid_y [dict get $net grid_y] + set y_position [expr $grid_y * [dict get $tech pitch horizontal_track]] + + set new_port [lindex [dict get $wrapper pins $net_name ports] 0] + dict set new_port layers {} + dict set new_port fixed [list 0 $y_position] + dict set new_port layers "C4" shapes [list \ + [list rect [concat \ + [list 0 \ + [expr 0 - [dict get $tech layer C4 width] / 2] \ + [dict get $tech layer C4 depth] \ + [expr 0 + [dict get $tech layer C4 width] / 2]]]]] + # debug "Replacing pin $net_name with $new_port" + dict set wrapper pins $net_name ports [list $new_port] + + set segments {} + + # First segment from RAM to jog location, to the y grid of the pin + set target_grid_point [expr \ + ($wrapper_depth - [dict get $net h_offset]) * \ + [dict get $tech pitch vertical_track]] + set width [dict get $tech layer [dict get $net pin_layer] width] + lappend segments [list \ + layer [dict get $net pin_layer] \ + points [list \ + "$macro_x [dict get $net macro_pin_y]" \ + "$target_grid_point [dict get $net macro_pin_y]" \ + "$target_grid_point $y_position"]] + if { [dict get $net pin_layer] != "C4" } { lappend segments [list \ layer [dict get $net pin_layer] \ - points [list \ - "$macro_x [dict get $net macro_pin_y]" \ - "$target_grid_point [dict get $net macro_pin_y]" \ - "$target_grid_point $y_position" \ - ] - ] - if {[dict get $net pin_layer] != "C4"} { - lappend segments [list \ - layer [dict get $net pin_layer] \ - points [list \ - "$target_grid_point $y_position" \ - [dict get $tech via] \ - ] \ - ] - } - lappend segments [list \ - layer C4 \ points [list \ "$target_grid_point $y_position" \ - "0 $y_position" \ - ] \ - ] - - dict set wrapper nets $net_name routes $segments + [dict get $tech via]]] } + lappend segments [list \ + layer C4 \ + points [list \ + "$target_grid_point $y_position" \ + "0 $y_position"]] - return $wrapper + dict set wrapper nets $net_name routes $segments } - proc test_harness {wrappers} { - variable wrapper_cfg - - set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] - set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] - set idx 0 - set num_cells [dict size $wrappers] - set num_grids [expr round(sqrt($num_cells)) + 1] - set max_cell_width 0 - dict for {cell_name cell} $wrappers { - set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] - } - set grid_x_size [expr $max_cell_width + (2 * $site_width)] - set grid_y_size [expr 4 * $site_height] + return $wrapper +} - def new_design "test_harness" [dict get $wrapper_cfg def_units] [list 0 0 [expr round($grid_x_size * $num_grids)] [expr round($grid_y_size * $num_grids)]] +proc test_harness { wrappers } { + variable wrapper_cfg - foreach cell [dict keys $wrappers] { - set x [expr round(($idx % $num_grids) * $grid_x_size)] - set y [expr round(round($idx / $num_grids) * $grid_y_size)] + set site_height [expr [dict get $wrapper_cfg site height] * [dict get $wrapper_cfg def_units]] + set site_width [expr [dict get $wrapper_cfg site width] * [dict get $wrapper_cfg def_units]] + set idx 0 + set num_cells [dict size $wrappers] + set num_grids [expr round(sqrt($num_cells)) + 1] + set max_cell_width 0 + dict for {cell_name cell} $wrappers { + set max_cell_width [expr max($max_cell_width,[lindex [dict get $cell die_area] 2])] + } + set grid_x_size [expr $max_cell_width + (2 * $site_width)] + set grid_y_size [expr 4 * $site_height] - set orig_cell [regsub {_mod} $cell {}] - def add_component "w_$idx" $cell $x $y N placed - def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed + def new_design "test_harness" [dict get $wrapper_cfg def_units] \ + [concat [list 0 0] \ + [list [expr round($grid_x_size * $num_grids)] \ + [expr round($grid_y_size * $num_grids)]]] - incr idx - } + foreach cell [dict keys $wrappers] { + set x [expr round(($idx % $num_grids) * $grid_x_size)] + set y [expr round(round($idx / $num_grids) * $grid_y_size)] - def open test_harness.def - def write [set design [def get_current_design]] - def close + set orig_cell [regsub {_mod} $cell {}] + def add_component "w_$idx" $cell $x $y N placed + def add_component "o_$idx" $orig_cell $x [expr round($y + (2 * $site_height))] N placed - return $design + incr idx } - proc set_stdcell_config {config} { - variable wrapper_cfg - set wrapper_cfg $config - } + def open test_harness.def + def write [set design [def get_current_design]] + def close - proc run {} { - set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef + return $design +} - lef read_macros $file_name - set data [wrapper find_cells_with_m2_pins] +proc set_stdcell_config { config } { + variable wrapper_cfg + set wrapper_cfg $config +} - set wrappers [wrapper build_wrappers $data] +proc run { } { + # tclint-disable-next-line line-length + set file_name /projects/ssg/pj10000064_diphda/users/colhol01/openroad/library/arm/cp/14lpp/sc10p5mcpp84_base_lvt_c14/r2p1/lef/sc10p5mcpp84_14lpp_base_lvt_c14.lef - lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers - def write_cells $wrappers - } + lef read_macros $file_name + set data [wrapper find_cells_with_m2_pins] - proc convert_tech_to_def_units {tech} { - set def_units [dict get $tech units] - dict for {layer_name layer} [dict get $tech layer] { - foreach property {depth width non_preferred_width} { - if {[dict exists $layer $property]} { - dict set tech layer $layer_name $property [expr round([dict get $layer $property] * $def_units)] - } + set wrappers [wrapper build_wrappers $data] + + lef write_cells sc10p5mcpp84_14lpp_base_lvt_c14.mod.lef $wrappers + def write_cells $wrappers +} + +proc convert_tech_to_def_units { tech } { + set def_units [dict get $tech units] + dict for {layer_name layer} [dict get $tech layer] { + foreach property {depth width non_preferred_width} { + if { [dict exists $layer $property] } { + dict set tech layer $layer_name $property \ + [expr round( \ + [dict get $layer $property] * $def_units \ + )] } } - - foreach layer_name [dict keys [dict get $tech layer]] { - foreach property {direction width non_preferred_width} { - if {[dict exists $tech layer $layer_name $property]} { - def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] - } + } + + foreach layer_name [dict keys [dict get $tech layer]] { + foreach property {direction width non_preferred_width} { + if { [dict exists $tech layer $layer_name $property] } { + def set_layer_info $layer_name $property [dict get $tech layer $layer_name $property] } } + } - dict set tech pitch vertical_track [expr round([dict get $tech pitch vertical_track] * $def_units)] - dict set tech pitch horizontal_track [expr round([dict get $tech pitch horizontal_track] * $def_units)] + dict set tech pitch vertical_track [expr round( \ + [dict get $tech pitch vertical_track] * $def_units)] + dict set tech pitch horizontal_track [expr round( \ + [dict get $tech pitch horizontal_track] * $def_units)] - return $tech - } + return $tech +} - proc set_macro_config {lef_tech} { - variable tech - - set tech [convert_tech_to_def_units $lef_tech] - } - - proc macro {lef_file} { - lef read_macros $lef_file - set cells {} - - foreach cell_name [dict keys [lef get_cells]] { +proc set_macro_config { lef_tech } { + variable tech + + set tech [convert_tech_to_def_units $lef_tech] +} + +proc macro { lef_file } { + lef read_macros $lef_file + set cells {} + + foreach cell_name [dict keys [lef get_cells]] { # debug "$cell_name" - set designs [list ${cell_name}_mod [wrap_macro $cell_name]] - lef write_macros ${cell_name}_mod.lef $designs - def write_cells $designs - lappend cells $cell_name - } - - return $cells + set designs [list ${cell_name}_mod [wrap_macro $cell_name]] + lef write_macros ${cell_name}_mod.lef $designs + def write_cells $designs + lappend cells $cell_name } - namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config - namespace export information warning err critical - namespace export build_wrappers - namespace export test_harness - namespace ensemble create + return $cells +} + +namespace export find_cells_with_m2_pins macro set_stdcell_config set_macro_config +namespace export information warning err critical +namespace export build_wrappers +namespace export test_harness +namespace ensemble create } package provide wrapper 1.0.0 diff --git a/flow/util/correlateRC.py b/flow/util/correlateRC.py index bc046e94d2..410f8e3144 100755 --- a/flow/util/correlateRC.py +++ b/flow/util/correlateRC.py @@ -5,9 +5,10 @@ # Use ORFS 'make write_net_rc' to write cap files. import os -from sys import exit +from sys import exit, stderr from collections import defaultdict +import traceback import collections import argparse import re @@ -15,6 +16,8 @@ from sklearn.linear_model import LinearRegression import matplotlib.pyplot as plt +LAYER_HEADER_RE = re.compile("^([^\\(]+)\\(([^\\)]+)\\)$") + # Parse and validate arguments # ============================================================================= @@ -81,6 +84,12 @@ def makeDict(): data = makeDict() +stack = [] +stack_line = None + +# indices of relevant layers (routable layers or via layers) +active_layers = set() + # Parse the cap CSV file generated by compare_rc_script.tcl for rc_file in args.rc_file: design = rc_file @@ -88,32 +97,64 @@ def makeDict(): with open(rc_file) as f: nonGrtNets = 0 for line in f: + if line.startswith("# stack: "): + if stack_line is not None and stack_line != line: + print(f"layer stack inconsistent", file=stderr) + exit(1) + elif stack_line is None: + for layer in line.removeprefix("# stack: ").strip().split(" "): + name = layer + is_routing = False + via_resist = 0.0 + if layer.endswith(")"): + # layer name has extra data + match = LAYER_HEADER_RE.match(layer) + assert match + name = match.group(1) + if match.group(2) == "routing": + is_routing = True + else: + via_resist = float(match.group(2)) + stack.append((name, is_routing, via_resist)) + stack_line = line + continue + tokens = line.strip().split(",") netName = tokens[0] - gpl_res = float(tokens[1]) - gpl_cap = float(tokens[2]) - grt_res = float(tokens[3]) - grt_cap = float(tokens[4]) - rcx_res = float(tokens[5]) - rcx_cap = float(tokens[6]) - - data[design][netName]["gpl_res"] = gpl_res - data[design][netName]["gpl_cap"] = gpl_cap - data[design][netName]["grt_res"] = grt_res - data[design][netName]["grt_cap"] = grt_cap - data[design][netName]["rcx_res"] = rcx_res - data[design][netName]["rcx_cap"] = rcx_cap - - layer_lengths = [] - layer_names = [] - wire_length = 0.0 - for i in range(7, len(tokens), 2): - layer_names.append(tokens[i]) - layer_length = float(tokens[i + 1]) - layer_lengths.append(layer_length) - wire_length += layer_length + + data[design][netName] = { + "type": tokens[1], + "gpl_res": float(tokens[2]), + "gpl_cap": float(tokens[3]), + "grt_res": float(tokens[4]), + "grt_cap": float(tokens[5]), + "rcx_res": float(tokens[6]), + "rcx_cap": float(tokens[7]), + } + + layer_lengths = [float(tok) for tok in tokens[8:]] + for i, length in enumerate(layer_lengths): + if length > 0: + active_layers.add(i) + data[design][netName]["layer_lengths"] = layer_lengths - data[design][netName]["wire_length"] = wire_length + data[design][netName]["routable_layer_lengths"] = [ + length + for i, length in enumerate(layer_lengths) + # ignore non-routable layers + if stack[i][1] + ] + data[design][netName]["wire_length"] = sum( + length + for i, length in enumerate(layer_lengths) + # ignore non-routable layers + if stack[i][1] + ) + data[design][netName]["grt_via_res"] = sum( + (length * stack[i][2]) + for i, length in enumerate(layer_lengths) + if not stack[i][1] + ) ################################################################ @@ -210,16 +251,15 @@ def makeDict(): for net in data[design]: rcx_res = data[design][net]["rcx_res"] if rcx_res > 0: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) - y.append(rcx_res) + x.append(data[design][net]["routable_layer_lengths"]) + y.append(rcx_res - data[design][net]["grt_via_res"]) x = np.array(x) y = np.array(y) res_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = res_model.score(x, y) -print("Resistance coefficient of determination: {:.4f}".format(r_sq)) +print("# Resistance coefficient of determination: {:.4f}".format(r_sq)) ################################################################ @@ -229,8 +269,7 @@ def makeDict(): y = [] for design in data: for net in data[design]: - layer_lengths = data[design][net]["layer_lengths"] - x.append(layer_lengths) + x.append(data[design][net]["routable_layer_lengths"]) y.append(data[design][net]["rcx_cap"]) x = np.array(x) @@ -238,51 +277,62 @@ def makeDict(): cap_model = LinearRegression(fit_intercept=False).fit(x, y) r_sq = cap_model.score(x, y) -print("Capacitance coefficient of determination: {:.4f}".format(r_sq)) - -print("Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) -for layer, res_coeff, cap_coeff in zip(layer_names, res_model.coef_, cap_model.coef_): - if res_coeff > 0.0 or cap_coeff > 0.0: +print("# Capacitance coefficient of determination: {:.4f}".format(r_sq)) +print("# Updated layer resistance {}/um capacitance {}/um".format(res_unit, cap_unit)) + +routable_layers = [layer for layer in stack if layer[1]] +for i, layer in enumerate(routable_layers): + res_coeff = res_model.coef_[i] + cap_coeff = cap_model.coef_[i] + if res_coeff != 0.0 or cap_coeff != 0.0: print( "set_layer_rc -layer {} -resistance {:.5E} -capacitance {:.5E}".format( - layer, res_coeff / res_scale, cap_coeff / cap_scale + layer[0], res_coeff / res_scale, cap_coeff / cap_scale ) ) ################################################################ -x = [] -y = [] -for design in data: - for net in data[design]: - wire_res = data[design][net]["rcx_res"] - wire_length = data[design][net]["wire_length"] - if wire_res != 0.0: - x.append([wire_length]) - y.append(wire_res) - -x = np.array(x) -y = np.array(y) - -wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_res = wire_res_model.coef_[0] -x = [] -y = [] -for design in data: - for net in data[design]: - wire_length = data[design][net]["wire_length"] - x.append([wire_length]) - y.append(data[design][net]["rcx_cap"]) +def generic_rc_fit(type_sieve): + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + wire_res = data[design][net]["rcx_res"] + wire_length = data[design][net]["wire_length"] + if net_type in type_sieve and wire_res != 0.0: + x.append([wire_length]) + y.append(wire_res) + x = np.array(x) + y = np.array(y) + wire_res_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_res = wire_res_model.coef_[0] + + x = [] + y = [] + for design in data: + for net in data[design]: + net_type = data[design][net]["type"] + if net_type in type_sieve: + wire_length = data[design][net]["wire_length"] + wire_cap = data[design][net]["rcx_cap"] + x.append([wire_length]) + y.append(wire_cap) + x = np.array(x) + y = np.array(y) + wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) + wire_cap = wire_cap_model.coef_[0] + + return "-resistance {:.5E} -capacitance {:.5E}".format( + wire_res / res_scale, wire_cap / cap_scale + ) -x = np.array(x) -y = np.array(y) -wire_cap_model = LinearRegression(fit_intercept=False).fit(x, y) -wire_cap = wire_cap_model.coef_[0] +print("# Combined fit:") +print("set_wire_rc " + generic_rc_fit(["signal", "clock"])) -print( - "set_wire_rc -resistance {:.5E} -capacitance {:.5E}".format( - wire_res / res_scale, wire_cap / cap_scale - ) -) +print("# Split signal/clock fit:") +print("set_wire_rc -signal " + generic_rc_fit(["signal"])) +print("set_wire_rc -clock " + generic_rc_fit(["clock"])) diff --git a/flow/util/cred_helper.py b/flow/util/cred_helper.py new file mode 100755 index 0000000000..e87c80b0df --- /dev/null +++ b/flow/util/cred_helper.py @@ -0,0 +1,93 @@ +#!/usr/bin/env python3 +# +# Returns information about user's GCP entitlements +# +# Usage: cred_helper.py [get|test] +# +# get prints the GCP auth token +# test prints the user's GCP entitlements +# +# Calling script without arguments prints out usage information and then exits with a non-zero code (per spec) +# + +import subprocess +import requests +import json +import re +import sys + + +def get_gcloud_auth_token(test): + """ + Returns the gcloud auth token based on the user.bazelrc + """ + + with open("user.bazelrc") as f: + all = f.read() + match = re.search(r"# user: (.*)", all) + if match is None: + sys.exit('Did not find username in user.bazelrc file as "# user: "') + USER = match.group(1) + + cmd = ["gcloud", "auth", "print-access-token", USER] + if test: + print("Running: " + subprocess.list2cmdline(cmd)) + result = subprocess.run(cmd, capture_output=True, text=True, check=True) + token = result.stdout.strip() + return token + + +def generate_credentials(test): + """ + Generate the credentials in a form that Bazel wants, which is the + Authorization key points to a list + """ + + bearer_token = get_gcloud_auth_token(test) + + # Create the JSON object with the required format + credentials = {"headers": {"Authorization": [f"Bearer {bearer_token}"]}} + return credentials + + +def test_permissions(credentials, bucket_name): + """ + Tests the user's entitlements for this bucket + + Note that the call to check the permissions needs the Authorization key to + point to a string and not a list. So, take the first element in the list + and make it the only value + """ + + credentials["headers"]["Authorization"] = credentials["headers"]["Authorization"][0] + url = ( + f"https://storage.googleapis.com/storage/v1/b/{bucket_name}/iam/testPermissions" + ) + permissions = {"permissions": ["storage.buckets.get", "storage.objects.create"]} + + response = requests.get(url, params=permissions, headers=credentials["headers"]) + response.raise_for_status() + return response.json() + + +def main(): + if ( + len(sys.argv) <= 1 + or (len(sys.argv) == 2 and sys.argv[1] not in ["get", "test"]) + or len(sys.argv) >= 3 + ): + sys.exit("Usage: python cred_helper.py [get|test]") + test = sys.argv[1] == "test" + + credentials = generate_credentials(test) + if not test: + print(json.dumps(credentials, indent=2)) + return + + permissions = test_permissions(credentials, "megaboom-bazel-artifacts") + + print(json.dumps(permissions, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/flow/util/def2stream.py b/flow/util/def2stream.py index a29be31c9e..5062474f9e 100644 --- a/flow/util/def2stream.py +++ b/flow/util/def2stream.py @@ -20,7 +20,6 @@ for i in main_layout.each_cell(): print("[INFO] '{0}'".format(i.name)) -print("[INFO] Reading DEF ...") main_layout.read(in_def, layoutOptions) # Clear cells @@ -28,35 +27,33 @@ # remove orphan cell BUT preserve cell with VIA_ # - KLayout is prepending VIA_ when reading DEF that instantiates LEF's via -print("[INFO] Clearing cells...") for i in main_layout.each_cell(): if i.cell_index() != top_cell_index: - if not i.name.startswith("VIA_"): + if not i.name.startswith("VIA_") and not i.name.endswith("_DEF_FILL"): i.clear() # Load in the gds to merge -print("[INFO] Merging GDS/OAS files...") for fil in in_files.split(): print("\t{0}".format(fil)) main_layout.read(fil) # Copy the top level only to a new layout -print("[INFO] Copying toplevel cell '{0}'".format(design_name)) top_only_layout = pya.Layout() top_only_layout.dbu = main_layout.dbu top = top_only_layout.create_cell(design_name) top.copy_tree(main_layout.cell(design_name)) -print("[INFO] Checking for missing cell from GDS/OAS...") missing_cell = False -regex = None -if "GDS_ALLOW_EMPTY" in os.environ: - print("[INFO] Found GDS_ALLOW_EMPTY variable.") - regex = os.getenv("GDS_ALLOW_EMPTY") +allow_empty = os.environ.get("GDS_ALLOW_EMPTY", "") +regex = re.compile(allow_empty) if allow_empty else None + +if allow_empty: + print(f"[INFO] GDS_ALLOW_EMPTY={allow_empty}") + for i in top_only_layout.each_cell(): if i.is_empty(): missing_cell = True - if regex is not None and re.match(regex, i.name): + if regex is not None and regex.match(i.name): print( "[WARNING] LEF Cell '{0}' ignored. Matches GDS_ALLOW_EMPTY.".format( i.name @@ -72,7 +69,6 @@ if not missing_cell: print("[INFO] All LEF cells have matching GDS/OAS cells") -print("[INFO] Checking for orphan cell in the final layout...") orphan_cell = False for i in top_only_layout.each_cell(): if i.name != design_name and i.parent_cells() == 0: @@ -81,14 +77,12 @@ errors += 1 if not orphan_cell: - print("[INFO] No orphan cells") + print("[INFO] No orphan cells in the final layout") if seal_file: top_cell = top_only_layout.top_cell() - print("[INFO] Reading seal GDS/OAS file...") - print("\t{0}".format(seal_file)) top_only_layout.read(seal_file) for cell in top_only_layout.top_cells(): @@ -101,7 +95,6 @@ top.insert(pya.CellInstArray(cell.cell_index(), pya.Trans())) # Write out the GDS -print("[INFO] Writing out GDS/OAS '{0}'".format(out_file)) top_only_layout.write(out_file) sys.exit(errors) diff --git a/flow/util/docker_shell b/flow/util/docker_shell index 2073edad5e..9c598db280 100755 --- a/flow/util/docker_shell +++ b/flow/util/docker_shell @@ -1,8 +1,29 @@ #!/usr/bin/env bash set -ex + +# +# Method to use docker CLI to determine if we're using docker or podman +# +# Sets container_engine global variable with either "docker" or "podman" +# +get_container_engine () { + local DOCKER_VERSION_STRING=$(docker --version 2> /dev/null) + + if [[ "$DOCKER_VERSION_STRING" == *"Docker"* ]]; then + container_engine="docker" + elif [[ "$DOCKER_VERSION_STRING" == *"podman"* ]]; then + container_engine="podman" + else + echo "Unable to determine container engine using docker CLI" + exit 1 + fi +} + DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" +get_container_engine + WORKSPACE=$(pwd) YOSYS_EXE=${YOSYS_EXE:-/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys} OPENROAD_EXE=${OPENROAD_EXE:-/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad} @@ -17,9 +38,15 @@ if test -t 0; then DOCKER_INTERACTIVE=-ti fi +if [[ $container_engine == "podman" ]]; then + user_args="--privileged --userns=keep-id" +else + user_args="-u $(id -u ${USER}):$(id -g ${USER})" +fi + # Most of these options below has to do with allowing to # run the OpenROAD GUI from within Docker. -docker run -u $(id -u ${USER}):$(id -g ${USER}) \ +docker run $user_args \ -e LIBGL_ALWAYS_SOFTWARE=1 \ -e "QT_X11_NO_MITSHM=1" \ -e XDG_RUNTIME_DIR=/tmp/xdg-run \ @@ -29,16 +56,16 @@ docker run -u $(id -u ${USER}):$(id -g ${USER}) \ -v $XAUTH:$XAUTH \ -e XAUTHORITY=$XAUTH \ -e FLOW_HOME=/OpenROAD-flow-scripts/flow/ \ - -e MAKEFILES=/OpenROAD-flow-scripts/flow/Makefile \ -e YOSYS_EXE=$YOSYS_EXE \ -e OPENROAD_EXE=$OPENROAD_EXE \ -e KLAYOUT_CMD=$KLAYOUT_CMD \ - -v $WORKSPACE:/OpenROAD-flow-scripts/flow \ + -v $WORKSPACE:/OpenROAD-flow-scripts/flow:Z \ --network host \ $DOCKER_INTERACTIVE \ ${OR_IMAGE:-openroad/flow-ubuntu22.04-builder:latest} \ bash -c "set -ex mkdir /tmp/xdg-run cd /OpenROAD-flow-scripts/flow + . ../env.sh $ARGUMENTS " diff --git a/flow/util/executeParallel.sh b/flow/util/executeParallel.sh deleted file mode 100755 index 78c90e21e2..0000000000 --- a/flow/util/executeParallel.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/usr/bin/env bash - -/home/tool/gnu/parallel/parallel-20160822/bin/parallel --joblog out.log --bar --env GRB_LICENSE_FILE --env LD_LIBRARY_PATH --env PATH --env LM_LICENSE_FILE --sshloginfile node --workdir $PWD < run.sh diff --git a/flow/util/genElapsedTime.py b/flow/util/genElapsedTime.py index 4a1159d105..3d78e66455 100755 --- a/flow/util/genElapsedTime.py +++ b/flow/util/genElapsedTime.py @@ -4,26 +4,51 @@ # in the flow and prints it in a table # --------------------------------------------------------------------------- +import argparse +import hashlib import pathlib import os -import argparse # argument parsing import sys # Parse and validate arguments # ============================================================================== +def get_hash(f): + # content hash for the result file alongside .log file is useful to + # debug divergent results under what should be identical + # builds(such as local and CI builds) + for ext in [".odb", ".rtlil", ".v"]: + result_file = pathlib.Path( + str(f).replace("logs/", "results/").replace(".log", ext) + ) + if result_file.exists(): + hasher = hashlib.sha1() + with open(result_file, "rb") as odb_f: + while True: + chunk = odb_f.read(16 * 1024 * 1024) + if not chunk: + break + hasher.update(chunk) + return hasher.hexdigest() + return "N/A" + + def print_log_dir_times(logdir, args): first = True totalElapsed = 0 total_max_memory = 0 - print(logdir) + if not args.match: + print(logdir) # Loop on all log files in the directory for f in sorted(pathlib.Path(logdir).glob("**/*.log")): if "eqy_output" in str(f): continue # Extract Elapsed Time line from log file + stem = os.path.splitext(os.path.basename(str(f)))[0] + if args.match and args.match != stem: + continue with open(str(f)) as logfile: found = False for line in logfile: @@ -60,36 +85,49 @@ def print_log_dir_times(logdir, args): peak_memory = int( int(line.split("Peak memory: ")[1].split("KB")[0]) / 1024 ) + break + + odb_hash = get_hash(f) if not found: print("No elapsed time found in", str(f), file=sys.stderr) continue # Print the name of the step and the corresponding elapsed time - format_str = "%-25s %20s %14s" + format_str = "%-25s %10s %14s %20s" if elapsedTime is not None and peak_memory is not None: if first and not args.noHeader: - print(format_str % ("Log", "Elapsed seconds", "Peak Memory/MB")) + print( + format_str + % ("Log", "Elapsed/s", "Peak Memory/MB", "sha1sum .odb [0:20)") + ) first = False print( format_str % ( - os.path.splitext(os.path.basename(str(f)))[0], + stem, elapsedTime, peak_memory, + odb_hash[0:20], ) ) - totalElapsed += elapsedTime - total_max_memory = max(total_max_memory, int(peak_memory)) + if elapsedTime is not None: + totalElapsed += elapsedTime + if peak_memory is not None: + total_max_memory = max(total_max_memory, int(peak_memory)) - if totalElapsed != 0: - print(format_str % ("Total", totalElapsed, total_max_memory)) + if totalElapsed != 0 and not args.match: + print(format_str % ("Total", totalElapsed, total_max_memory, "")) def scan_logs(args): parser = argparse.ArgumentParser( description="Print elapsed time for every step in the flow" ) + parser.add_argument( + "--match", + help="Match this string in the log file names", + ) parser.add_argument( "--logDir", "-d", required=True, nargs="+", help="Log files directories" ) diff --git a/flow/util/genMassive.py b/flow/util/genMassive.py index 332a4caaec..c05da0926e 100644 --- a/flow/util/genMassive.py +++ b/flow/util/genMassive.py @@ -332,7 +332,7 @@ def writeConfigs(CurAttrs, CurChunkNum): fo = open("%s/%s" % (CurChunkDir, fileName), "w") - fo.write("include $(realpath $(dir $(DESIGN_CONFIG))../../)/config.mk\n") + fo.write("include $(realpath $(DESIGN_DIR)../../)/config.mk\n") fo.write("\n") fo.write("FLOW_VARIANT = %s\n" % (variantName)) fo.write("\n") @@ -363,8 +363,7 @@ def writeConfigs(CurAttrs, CurChunkNum): fOutSdc.write(filedata) fOutSdc.close() fo.write( - "export SDC_FILE = $(dir $(DESIGN_CONFIG))/constraint-DoE-%s.sdc\n" - % variantName + "export SDC_FILE = $(DESIGN_DIR)/constraint-DoE-%s.sdc\n" % variantName ) if CurAbcClkPeriod != "empty": @@ -411,8 +410,7 @@ def writeConfigs(CurAttrs, CurChunkNum): or CurGrSeed != "empty" ): fo.write( - "export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute-DoE-%s.tcl" - % variantName + "export FASTROUTE_TCL = $(DESIGN_DIR)/fastroute-DoE-%s.tcl" % variantName ) if CurPlatform in PUBLIC: diff --git a/flow/util/genMetrics.py b/flow/util/genMetrics.py index 9c4ecba2ce..33261a7f8c 100755 --- a/flow/util/genMetrics.py +++ b/flow/util/genMetrics.py @@ -6,7 +6,6 @@ # ----------------------------------------------------------------------------- import os -from sys import exit from datetime import datetime, timedelta from collections import defaultdict from uuid import uuid4 as uuid @@ -14,33 +13,18 @@ import argparse import json -import pandas as pd import re from glob import glob -# make sure the working dir is flow/ -os.chdir(os.path.join(os.path.dirname(os.path.abspath(__file__)), "..")) - -# Parse and validate arguments -# ============================================================================= - def parse_args(): parser = argparse.ArgumentParser( description="Generates metadata from OpenROAD flow" ) - parser.add_argument( - "--flowPath", - "-f", - required=False, - default="./", - help="Path to the flow directory", - ) parser.add_argument( "--design", "-d", - required=False, - default="all_designs", + required=True, help="Design Name for metrics", ) parser.add_argument( @@ -64,13 +48,11 @@ def parse_args(): "--output", "-o", required=False, default="metadata.json", help="Output file" ) parser.add_argument("--hier", "-x", action="store_true", help="Hierarchical JSON") + parser.add_argument("--logs", help="Path to logs") + parser.add_argument("--reports", help="Path to reports") + parser.add_argument("--results", help="Path to results") args = parser.parse_args() - if not os.path.isdir(args.flowPath): - print("[ERROR] flowPath does not exist") - print("Path: " + args.flowPath) - exit(1) - return args @@ -100,10 +82,8 @@ def extractTagFromFile( if jsonTag in jsonFile: print("[WARN] Overwriting Tag", jsonTag) - # Open file try: - searchFilePath = os.path.join(args.flowPath, file) - with open(searchFilePath) as f: + with open(file) as f: content = f.read() parsedMetrics = re.findall(pattern, content, re.M) @@ -128,12 +108,12 @@ def extractTagFromFile( else: # Only print a warning if the defaultNotFound is not set print( - "[WARN] Tag {} not found in {}.".format(jsonTag, searchFilePath), + "[WARN] Tag {} not found in {}.".format(jsonTag, file), "Will use {}.".format(defaultNotFound), ) jsonFile[jsonTag] = defaultNotFound except IOError: - print("[ERROR] Failed to open file:", searchFilePath) + print("[ERROR] Failed to open file:", file) jsonFile[jsonTag] = "ERR" @@ -210,13 +190,11 @@ def merge_jsons(root_path, output, files): file.close() -def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): +def extract_metrics( + cwd, platform, design, flow_variant, output, hier_json, logPath, rptPath, resultPath +): baseRegEx = "^{}\n^-*\n^{}" - logPath = os.path.join(cwd, "logs", platform, design, flow_variant) - rptPath = os.path.join(cwd, "reports", platform, design, flow_variant) - resultPath = os.path.join(cwd, "results", platform, design, flow_variant) - metrics_dict = defaultdict(dict) metrics_dict["run__flow__generate_date"] = now.strftime("%Y-%m-%d %H:%M") metrics_dict["run__flow__metrics_version"] = "Metrics_2.1.2" @@ -310,7 +288,7 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): # Accumulate time # ========================================================================= - extractGnuTime("synth", metrics_dict, logPath + "/1_1_yosys.log") + extractGnuTime("synth", metrics_dict, logPath + "/1_2_yosys.log") extractGnuTime("floorplan", metrics_dict, logPath + "/2_1_floorplan.log") extractGnuTime("floorplan_io", metrics_dict, logPath + "/2_2_floorplan_io.log") extractGnuTime( @@ -367,10 +345,6 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): else: metrics_dict["total_time"] = str(total) - metrics_df = pd.DataFrame(list(metrics_dict.items())) - col_index = metrics_df.iloc[0][1] + "__" + metrics_df.iloc[1][1] - metrics_df.columns = ["Metrics", col_index] - if hier_json: # Convert the Metrics dictionary to hierarchical format by stripping # the stage as a 'key' @@ -384,64 +358,18 @@ def extract_metrics(cwd, platform, design, flow_variant, output, hier_json): with open(output, "w") as resultSpecfile: json.dump(metrics_dict, resultSpecfile, indent=2, sort_keys=True) - return metrics_dict, metrics_df - args = parse_args() now = datetime.now() -flow_variants = args.flowVariant.split() -all_designs = True if args.design == "all_designs" else False -designs = args.design.split() -platforms = args.platform.split() - -if all_designs or len(designs) > 1 or len(flow_variants) > 1: - rootdir = "./logs" - all_df = pd.DataFrame() - all_d = [] - - cwd = os.getcwd() - for platform_it in os.scandir(rootdir): - if not platform_it.is_dir(): - continue - plt = platform_it.name - if not plt in platforms: - continue - for design_it in os.scandir(platform_it.path): - if not design_it.is_dir(): - continue - des = design_it.name - if not (all_designs or des in designs): - continue - for variant in flow_variants: - log_dir = os.path.join(cwd, "logs", plt, des, variant) - if not os.path.isdir(log_dir): - continue - if not os.path.isfile(os.path.join(log_dir, "6_report.json")): - print( - f"Skip extracting metrics for {plt}, {des}, {variant} as run did not complete" - ) - continue - print(f"Extract Metrics for {plt}, {des}, {variant}") - file = "/".join(["reports", plt, des, variant, "metrics.json"]) - metrics, df = extract_metrics(cwd, plt, des, variant, file, args.hier) - all_d.append(metrics) - if all_df.shape[0] == 0: - all_df = df - else: - all_df = all_df.merge(df, on="Metrics", how="inner") - - with open("metrics.json", "w") as outFile: - json.dump(all_d, outFile, indent=2) - - with open("metrics.html", "w") as f: - f.write(all_df.to_html()) -else: - metrics_dict, metrics_df = extract_metrics( - args.flowPath, - args.platform, - args.design, - args.flowVariant, - args.output, - args.hier, - ) +extract_metrics( + os.path.join(os.path.dirname(os.path.realpath(__file__)), "../"), + args.platform, + args.design, + args.flowVariant, + args.output, + args.hier, + args.logs, + args.reports, + args.results, +) diff --git a/flow/util/genReport.py b/flow/util/genReport.py index c6bf63b1ba..402c0efde4 100755 --- a/flow/util/genReport.py +++ b/flow/util/genReport.py @@ -15,10 +15,11 @@ SUMMARY_FILENAME = f"{REPORTS_FOLDER}/report-summary.log" DRC_FILENAME = "5_route_drc.rpt" LAST_EXPECTED_LOG = ["6_report.log", "generate_abstract.log"] -METRICS_LOG_FMT = "gen-metrics-{}-check.log" -METRICS_CHECK_FMT = "{}/metadata-{}-check.log" +METRICS_LOG_FMT = "metadata-generate.log" +METRICS_CHECK_FMT = "{}/metadata-check.log" REGEX_ERROR = re.compile(r"^\[error ?(\w+-\d+)?\]", re.IGNORECASE) REGEX_WARNING = re.compile(r"^\[warning ?(\w+-\d+)?\]", re.IGNORECASE) +SKIPPED_FLOW_VARIANT_KEYWORDS = ["test", "tune"] STATUS_GREEN = "Passing" STATUS_RED = "Failing" @@ -248,7 +249,9 @@ def write_summary(): dir_list = log_dir.split(os.sep) # Handles autotuner folders, which do not have `report.log` natively. # TODO: Can we log something for autotuner? - if len(dir_list) != 4 or "test-" in dir_list[-1]: + if len(dir_list) != 4 or any( + word in dir_list[-1] for word in SKIPPED_FLOW_VARIANT_KEYWORDS + ): continue report_dir = log_dir.replace(LOGS_FOLDER, REPORTS_FOLDER) @@ -270,13 +273,13 @@ def write_summary(): # check if metrics generation had issues d["metrics_logs_errors"], d["metrics_logs_warnings"] = parse_messages( - os.path.join(report_dir, METRICS_LOG_FMT.format(variant)), + os.path.join(report_dir, METRICS_LOG_FMT), print_missing=d["finished"], ) # check if metrics passed d["metrics_errors"], d["metrics_warnings"] = parse_messages( - METRICS_CHECK_FMT.format(report_dir, variant), print_missing=d["finished"] + METRICS_CHECK_FMT.format(report_dir), print_missing=d["finished"] ) # check if calibre was run and if drc check passed diff --git a/flow/util/genReportTable.py b/flow/util/genReportTable.py index a9046a39ad..9ec16e1475 100755 --- a/flow/util/genReportTable.py +++ b/flow/util/genReportTable.py @@ -51,7 +51,7 @@ args = parser.parse_args() goldFilename = f"metadata-{args.variant}-ok.json" -runFilename = f"metadata-{args.variant}.json" +runFilename = f"metadata.json" def readMetrics(fname, justLoad=False): diff --git a/flow/util/genRuleFile.py b/flow/util/genRuleFile.py index 66430b4e83..1cd52b831b 100755 --- a/flow/util/genRuleFile.py +++ b/flow/util/genRuleFile.py @@ -2,100 +2,37 @@ from math import ceil, isinf from os import chdir, getcwd -from os.path import isfile, abspath +from os.path import isfile from re import sub import argparse import json import operator +import os import sys -import requests -def get_golden(platform, design, api_base_url): - try: - response = requests.get( - api_base_url + f"/golden?platform={platform}&design={design}&variant=base" - ) - - # Check if the request was successful (status code 200) - if response.status_code == 200 and "error" not in response.json(): - # Parse the JSON response - data = response.json() - - return data, None - else: - print("API request failed") - return None, "API request failed" - except Exception as e: - print(f"An error occurred: {str(e)}") - return None, f"An error occurred: {str(e)}" - - -def get_metrics(commitSHA, platform, design, api_base_url): - try: - response = requests.get( - api_base_url - + f"/commit?commitSHA={commitSHA}&platform={platform}&design={design}&variant=base" - ) - - # Check if the request was successful (status code 200) - if response.status_code == 200 and "error" not in response.json(): - # Parse the JSON response - data = response.json() - - return data, None - else: - print("API request failed") - return None, "API request failed" - except Exception as e: - print(f"An error occurred: {str(e)}") - return None, f"An error occurred: {str(e)}" - - -def update_rules(designDir, variant, golden_metrics, overwrite): - if overwrite: - gen_rule_file( - designDir, # design directory - True, # update - False, # tighten - False, # failing - variant, # variant - golden_metrics, # metrics needed for update, default is {} in case of file - ) - else: - gen_rule_file( - designDir, # design directory - False, # update - True, # tighten - False, # failing - variant, # variant - golden_metrics, # metrics needed for update, default is {} in case of file - ) - - -def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics={}): - original_directory = getcwd() - chdir(design_dir) +def gen_rule_file( + rules_file, + new_rules_file, + update, + tighten, + failing, + variant, + metrics_file=None, + metrics_to_consider=[], +): + with open(metrics_file, "r") as f: + metrics = json.load(f) + if not isinstance(metrics, dict): + print(f"[ERROR] Invalid format for reference metrics {metrics_file}") + sys.exit(1) - metrics_file = f"metadata-{variant}-ok.json" - rules_file = f"rules-{variant}.json" rules = dict() - - if golden_metrics == {}: - if isfile(metrics_file): - with open(metrics_file, "r") as f: - metrics = json.load(f) - else: - print(f"[ERROR] File not found {abspath(metrics_file)}") - sys.exit(1) - else: - metrics = golden_metrics - if isfile(rules_file): with open(rules_file, "r") as f: OLD_RULES = json.load(f) else: - print(f"[WARNING] File not found {abspath(rules_file)}") + print(f"[WARNING] No old rules file found {rules_file}") OLD_RULES = None # dict format @@ -156,7 +93,7 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= # route "globalroute__antenna_diodes_count": { "mode": "padding", - "padding": 15, + "padding": 50, "round_value": True, "compare": "<=", }, @@ -179,7 +116,7 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= }, "detailedroute__antenna_diodes_count": { "mode": "padding", - "padding": 15, + "padding": 50, "min_max": max, "min_max_direct": 5, "round_value": True, @@ -244,11 +181,8 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= change_str = "" for field, option in rules_dict.items(): if field not in metrics.keys(): - print( - f"[ERROR] Metric {field} not found in " - f"metrics file: {metrics_file} or golden metrics." - ) - sys.exit(1) + print(f"[WARNING] Metric {field} not found") + continue if isinstance(metrics[field], str): print(f"[WARNING] Skipping string field {field} = {metrics[field]}") @@ -307,7 +241,17 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= else: rule_value = ceil(rule_value * 100) / 100.0 - if OLD_RULES is not None and field in OLD_RULES.keys(): + preserve_old_rule = ( + True + if len(metrics_to_consider) > 0 and field not in metrics_to_consider + else False + ) + has_old_rule = OLD_RULES is not None and field in OLD_RULES.keys() + + if has_old_rule and preserve_old_rule: + rule_value = OLD_RULES[field]["value"] + + if has_old_rule and not preserve_old_rule: old_rule = OLD_RULES[field] if old_rule["compare"] != option["compare"]: print("[WARNING] Compare operator changed since last update.") @@ -321,51 +265,54 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= else: rule_value = ceil(rule_value * 100) / 100.0 - UPDATE = False + need_to_update = False if ( tighten and rule_value != old_rule["value"] and compare(rule_value, old_rule["value"]) ): - UPDATE = True + need_to_update = True change_str += format_str.format( field, old_rule["value"], rule_value, "Tighten" ) if failing and not compare(metrics[field], old_rule["value"]): - UPDATE = True + need_to_update = True change_str += format_str.format( field, old_rule["value"], rule_value, "Failing" ) if update and old_rule["value"] != rule_value: - UPDATE = True + need_to_update = True change_str += format_str.format( field, old_rule["value"], rule_value, "Updating" ) - if not UPDATE: + if not need_to_update: rule_value = old_rule["value"] rules[field] = dict(value=rule_value, compare=option["compare"]) if len(change_str) > 0: + print(f"{os.path.normpath(rules_file)} updates:") print(format_str.format("Metric", "Old", "New", "Type"), end="") print(format_str.format("------", "---", "---", "----"), end="") print(change_str) - with open(rules_file, "w") as f: - print("[INFO] writing", abspath(rules_file)) + with open(new_rules_file, "w") as f: json.dump(rules, f, indent=4) - chdir(original_directory) + +def comma_separated_list(value): + if value is None or value == "all": + return [] + return [item.strip() for item in value.split(",")] if __name__ == "__main__": parser = argparse.ArgumentParser( description="Generates or updates rules file for CI." ) - parser.add_argument("dir", help="Path to the design directory.") parser.add_argument( "-v", "--variant", default="base", help='Flow variant [default="base"].' ) @@ -390,6 +337,32 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= default=False, help="Update failing rules.", ) + parser.add_argument( + "-r", + "--reference", + type=str, + default=None, + help="Reference metadata file.", + ) + parser.add_argument( + "--rules", + type=str, + default=None, + help="Rules input file.", + ) + parser.add_argument( + "--new-rules", + type=str, + default=None, + help="Rules output file.", + ) + parser.add_argument( + "-m", + "--metrics", + type=comma_separated_list, + default="all", + help="Only consider the following metrics to change. [default=all]", + ) args = parser.parse_args() if not args.update and not args.tighten and not args.failing: @@ -400,4 +373,13 @@ def gen_rule_file(design_dir, update, tighten, failing, variant, golden_metrics= parser.print_help() sys.exit(1) - gen_rule_file(args.dir, args.update, args.tighten, args.failing, args.variant) + gen_rule_file( + args.rules, + args.new_rules, + args.update, + args.tighten, + args.failing, + args.variant, + args.reference, + args.metrics, + ) diff --git a/flow/util/generate-vars.sh b/flow/util/generate-vars.sh index a45a0556e0..a80c0d1312 100755 --- a/flow/util/generate-vars.sh +++ b/flow/util/generate-vars.sh @@ -22,7 +22,7 @@ while read -r VAR; do # they are invalid in shell continue fi - name="${VAR%=*}" + name="${VAR%%=*}" value="${VAR#*=}" if [[ "${name}" =~ ^[[:digit:]] ]] ; then # skip if the name starts with a number @@ -46,13 +46,6 @@ while read -r VAR; do # skip variables that match the exclude patterns continue fi - # handle special case where the variable needs to be splitted in Tcl code - if [[ "${name}" == "GND_NETS_VOLTAGES" || "${name}" == "PWR_NETS_VOLTAGES" ]]; then - echo "export ${name}='${value}'" >> $1.sh - echo "set env(${name}) ${value}" >> $1.tcl - echo "set env ${name} ${value}" >> $1.gdb - continue - fi # convert absolute paths if possible to use FLOW_HOME variable if [[ "${name}" == *"SCRIPTS_DIR"* ]]; then @@ -63,8 +56,8 @@ while read -r VAR; do echo "export ${name}=\"${value}\"" >> $1.sh if [[ "${value}" == *'$'* ]]; then - echo "set env ${name} $(sed -e 's,${FLOW_HOME},getenv("FLOW_HOME"),' <<< ${value})" >> $1.gdb - echo "set env(${name}) \"$(sed -e 's,${FLOW_HOME},$::env(FLOW_HOME),' <<< ${value})\"" >> $1.tcl + echo "set env ${name} $(sed -e 's,${FLOW_HOME},getenv("FLOW_HOME"),g' <<< ${value})" >> $1.gdb + echo "set env(${name}) \"$(sed -e 's,${FLOW_HOME},$::env(FLOW_HOME),g' <<< ${value})\"" >> $1.tcl else echo "set env(${name}) \"${value}\"" >> $1.tcl echo "set env ${name} ${value}" >> $1.gdb diff --git a/flow/util/makeIssue.sh b/flow/util/makeIssue.sh index bc7fe2462e..9152294daa 100755 --- a/flow/util/makeIssue.sh +++ b/flow/util/makeIssue.sh @@ -7,12 +7,13 @@ currentDate=$(date +"%Y-%m-%d_%H-%M") ISSUE_TAG=${ISSUE_TAG:-"${DESIGN_NICKNAME}_${PLATFORM}_${FLOW_VARIANT}_${currentDate}"} ISSUE_CP_DESIGN_FILE_VARS="SDC_FILE \ VERILOG_FILES \ - CACHED_NETLIST \ + SYNTH_NETLIST_FILES \ FOOTPRINT_TCL \ FOOTPRINT \ SIG_MAP_FILE \ IO_CONSTRAINTS \ MACRO_PLACEMENT \ + MACRO_WRAPPERS \ RTLMP_CONFIG_FILE \ DFF_LIB_FILE " ISSUE_CP_PLATFORM_FILE_VARS="LIB_FILES \ @@ -31,7 +32,7 @@ ISSUE_CP_PLATFORM_FILE_VARS="LIB_FILES \ PDN_TCL \ POST_PDN_TCL \ POST_CTS_TCL \ - PRE_GLOBAL_ROUTE \ + PRE_GLOBAL_ROUTE_TCL \ FASTROUTE_TCL \ POST_DETAIL_ROUTE_TCL \ RCX_RULES \ diff --git a/flow/util/mergeLib.pl b/flow/util/mergeLib.pl deleted file mode 100755 index 146a75febf..0000000000 --- a/flow/util/mergeLib.pl +++ /dev/null @@ -1,61 +0,0 @@ -#!/usr/bin/env perl - -# This script is sourced from Brown (with slight modifications). It merges -# several timing libraries into one. -# ------------------------------------------------------------------------------ - -use strict; -use warnings; - -my $sclname = $ARGV[0]; -shift @ARGV; -my $cnt = @ARGV; - -if($cnt>0){ - process_header($ARGV[0]); - my $file; - foreach my $file (@ARGV) { - process_cells($file) - } - print "\n}\n"; -} else { - print "use: mergeLib.pl new_library_name lib1 lib2 lib3 ...."; -} - - -sub process_header { - my $filename = shift; - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - while (<$fh>) { - if(/library\s*\(/) { - print "library ($sclname) {\n"; - next; - } - last if(/^[\t\s]*cell\s*\(/); - print $_; - } - close($fh) -} - -sub process_cells { - my $filename = shift; - - open(my $fh, '<', $filename) or die "Could not open file $filename $!"; - - my $flag = 0; - # cut the cells - while (<$fh>) { - #chomp $_; - if(/^[\t\s]*cell\s*\(/) {#&& $flag==0){ - die "Error! new cell before finishing the previous one!\n" if($flag!=0); - print "\n$_"; - $flag=1; - } elsif($flag > 0){ - $flag++ if(/\{/); - $flag-- if(/\}/); - #print "...}\n" if($flag==0); - print "$_"; - } - } - close($fh) -} diff --git a/flow/util/merge_lib.py b/flow/util/merge_lib.py new file mode 100755 index 0000000000..961b5e2330 --- /dev/null +++ b/flow/util/merge_lib.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python3 + +import re +import sys + + +def process_header(filename, sclname): + with open(filename, "r") as fh: + for line in fh: + if re.search(r"library\s*\(", line): + print(f"library ({sclname}) {{") + continue + if re.match(r"^[\t ]*cell\s*\(", line): + break + print(line, end="") + + +def process_cells(filename): + with open(filename, "r") as fh: + flag = 0 # brace depth + for line in fh: + # Match 'cell ( ... )' with optional whitespace + if re.match(r"^[\t ]*cell\s*\(", line): + if flag != 0: + raise RuntimeError( + "Error! new cell before finishing the previous one!" + ) + print() # print blank line like Perl + print(line, end="") + flag = 1 # entering a cell block + elif flag > 0: + # Increase/decrease brace depth + flag += line.count("{") + flag -= line.count("}") + print(line, end="") + + # Optionally: reset flag to 0 here if it's finished + # But not necessary unless you're adding post-processing + + +def main(): + if len(sys.argv) < 3: + print("use: mergeLib.py new_library_name lib1 lib2 lib3 ....") + sys.exit(1) + + sclname = sys.argv[1] + files = sys.argv[2:] + + process_header(files[0], sclname) + for file in files: + process_cells(file) + print("\n}") + + +if __name__ == "__main__": + main() diff --git a/flow/util/open_plots.sh b/flow/util/open_plots.sh new file mode 100755 index 0000000000..8ff044b165 --- /dev/null +++ b/flow/util/open_plots.sh @@ -0,0 +1,2 @@ +#!/usr/bin/env bash +xdg-open $1 diff --git a/flow/util/plot_congestion.bzl b/flow/util/plot_congestion.bzl new file mode 100644 index 0000000000..507bec80ec --- /dev/null +++ b/flow/util/plot_congestion.bzl @@ -0,0 +1,23 @@ +"""Plots congestion against some parameter such as PLACE_DENSITY""" + +def plot_congestion(name, srcs, argument, values): + native.filegroup( + name = "{name}_congestion".format(name = name), + srcs = srcs, + output_group = "5_global_route.rpt", + ) + + native.genrule( + name = "{}_pdf".format(name), + srcs = ["{name}_congestion".format(name = name)], + outs = ["{}.pdf".format(name)], + cmd = "$(execpath //flow/util:plot_congestion) {argument} $@ $(locations :{name}_congestion) {values}".format(values = " ".join(values), argument = argument, name = name), + tools = ["//flow/util:plot_congestion"], + ) + + native.sh_binary( + name = name, + srcs = ["//flow/util:open_plots.sh"], + args = ["$(location :{}.pdf)".format(name)], + data = ["{}.pdf".format(name)], + ) diff --git a/flow/util/plot_congestion.py b/flow/util/plot_congestion.py new file mode 100644 index 0000000000..da6ce3056b --- /dev/null +++ b/flow/util/plot_congestion.py @@ -0,0 +1,31 @@ +import matplotlib.pyplot as plt +import numpy as np +import sys +import re +import os + + +sweep = sys.argv[1] +output = sys.argv[2] +remainder = sys.argv[3:] +files = remainder[: len(remainder) // 2] +values = remainder[len(remainder) // 2 :] + +# count lines in each file and divide by 3 and create a list of those +# numbers +congestion = [] +for file in files: + with open(file, "r") as f: + lines = f.readlines() + congestion.append(len(lines) // 4) + +# xy plot of density vs DRC errors +x = list(map(float, values)) +y = congestion +plt.plot(x, y, "o-") +plt.xlabel(sweep) +plt.ylabel("DRC Errors") +plt.title(sweep + " vs DRC Errors") +plt.grid() +plt.yscale("log") +plt.savefig(output) diff --git a/flow/util/preprocessLib.py b/flow/util/preprocessLib.py index 7f14ea536e..4e4cb025bc 100755 --- a/flow/util/preprocessLib.py +++ b/flow/util/preprocessLib.py @@ -36,6 +36,12 @@ content, count = re.subn(pattern, replace, content) print("Replaced malformed functions", count) +# Yosys-abc raises an assertion if the capacitive_load_unit is not ff +pattern = r"capacitive_load_unit\s*\(\s*0.001,pf\s*\);" +replace = r"capacitive_load_unit (1,ff);" +content, count = re.subn(pattern, replace, content) +print("Replaced capacitive_load_unit", count) + # Write output file print("Writing replaced file:", args.outputFile) f = open(args.outputFile, "w") diff --git a/flow/util/requirements.in b/flow/util/requirements.in new file mode 100644 index 0000000000..df6af3963f --- /dev/null +++ b/flow/util/requirements.in @@ -0,0 +1,2 @@ +matplotlib==3.10.0 +PyYAML==6.0.2 diff --git a/flow/util/requirements_lock.txt b/flow/util/requirements_lock.txt new file mode 100644 index 0000000000..e6aa58ad02 --- /dev/null +++ b/flow/util/requirements_lock.txt @@ -0,0 +1,439 @@ +# +# This file is autogenerated by pip-compile with Python 3.13 +# by the following command: +# +# bazel run //flow/util:requirements.update +# +contourpy==1.3.1 \ + --hash=sha256:041b640d4ec01922083645a94bb3b2e777e6b626788f4095cf21abbe266413c1 \ + --hash=sha256:05e806338bfeaa006acbdeba0ad681a10be63b26e1b17317bfac3c5d98f36cda \ + --hash=sha256:08d9d449a61cf53033612cb368f3a1b26cd7835d9b8cd326647efe43bca7568d \ + --hash=sha256:0ffa84be8e0bd33410b17189f7164c3589c229ce5db85798076a3fa136d0e509 \ + --hash=sha256:113231fe3825ebf6f15eaa8bc1f5b0ddc19d42b733345eae0934cb291beb88b6 \ + --hash=sha256:14c102b0eab282427b662cb590f2e9340a9d91a1c297f48729431f2dcd16e14f \ + --hash=sha256:174e758c66bbc1c8576992cec9599ce8b6672b741b5d336b5c74e35ac382b18e \ + --hash=sha256:19c1555a6801c2f084c7ddc1c6e11f02eb6a6016ca1318dd5452ba3f613a1751 \ + --hash=sha256:19d40d37c1c3a4961b4619dd9d77b12124a453cc3d02bb31a07d58ef684d3d86 \ + --hash=sha256:1bf98051f1045b15c87868dbaea84f92408337d4f81d0e449ee41920ea121d3b \ + --hash=sha256:20914c8c973f41456337652a6eeca26d2148aa96dd7ac323b74516988bea89fc \ + --hash=sha256:287ccc248c9e0d0566934e7d606201abd74761b5703d804ff3df8935f523d546 \ + --hash=sha256:2ba94a401342fc0f8b948e57d977557fbf4d515f03c67682dd5c6191cb2d16ec \ + --hash=sha256:31c1b55c1f34f80557d3830d3dd93ba722ce7e33a0b472cba0ec3b6535684d8f \ + --hash=sha256:36987a15e8ace5f58d4d5da9dca82d498c2bbb28dff6e5d04fbfcc35a9cb3a82 \ + --hash=sha256:3a04ecd68acbd77fa2d39723ceca4c3197cb2969633836ced1bea14e219d077c \ + --hash=sha256:3e8b974d8db2c5610fb4e76307e265de0edb655ae8169e8b21f41807ccbeec4b \ + --hash=sha256:3ea9924d28fc5586bf0b42d15f590b10c224117e74409dd7a0be3b62b74a501c \ + --hash=sha256:4318af1c925fb9a4fb190559ef3eec206845f63e80fb603d47f2d6d67683901c \ + --hash=sha256:44a29502ca9c7b5ba389e620d44f2fbe792b1fb5734e8b931ad307071ec58c53 \ + --hash=sha256:47734d7073fb4590b4a40122b35917cd77be5722d80683b249dac1de266aac80 \ + --hash=sha256:4d76d5993a34ef3df5181ba3c92fabb93f1eaa5729504fb03423fcd9f3177242 \ + --hash=sha256:4dbbc03a40f916a8420e420d63e96a1258d3d1b58cbdfd8d1f07b49fcbd38e85 \ + --hash=sha256:500360b77259914f7805af7462e41f9cb7ca92ad38e9f94d6c8641b089338124 \ + --hash=sha256:523a8ee12edfa36f6d2a49407f705a6ef4c5098de4f498619787e272de93f2d5 \ + --hash=sha256:573abb30e0e05bf31ed067d2f82500ecfdaec15627a59d63ea2d95714790f5c2 \ + --hash=sha256:5b75aa69cb4d6f137b36f7eb2ace9280cfb60c55dc5f61c731fdf6f037f958a3 \ + --hash=sha256:61332c87493b00091423e747ea78200659dc09bdf7fd69edd5e98cef5d3e9a8d \ + --hash=sha256:805617228ba7e2cbbfb6c503858e626ab528ac2a32a04a2fe88ffaf6b02c32bc \ + --hash=sha256:841ad858cff65c2c04bf93875e384ccb82b654574a6d7f30453a04f04af71342 \ + --hash=sha256:89785bb2a1980c1bd87f0cb1517a71cde374776a5f150936b82580ae6ead44a1 \ + --hash=sha256:8eb96e79b9f3dcadbad2a3891672f81cdcab7f95b27f28f1c67d75f045b6b4f1 \ + --hash=sha256:974d8145f8ca354498005b5b981165b74a195abfae9a8129df3e56771961d595 \ + --hash=sha256:9ddeb796389dadcd884c7eb07bd14ef12408aaae358f0e2ae24114d797eede30 \ + --hash=sha256:a045f341a77b77e1c5de31e74e966537bba9f3c4099b35bf4c2e3939dd54cdab \ + --hash=sha256:a0cffcbede75c059f535725c1680dfb17b6ba8753f0c74b14e6a9c68c29d7ea3 \ + --hash=sha256:a761d9ccfc5e2ecd1bf05534eda382aa14c3e4f9205ba5b1684ecfe400716ef2 \ + --hash=sha256:a7895f46d47671fa7ceec40f31fae721da51ad34bdca0bee83e38870b1f47ffd \ + --hash=sha256:a9fa36448e6a3a1a9a2ba23c02012c43ed88905ec80163f2ffe2421c7192a5d7 \ + --hash=sha256:ab29962927945d89d9b293eabd0d59aea28d887d4f3be6c22deaefbb938a7277 \ + --hash=sha256:abbb49fb7dac584e5abc6636b7b2a7227111c4f771005853e7d25176daaf8453 \ + --hash=sha256:ac4578ac281983f63b400f7fe6c101bedc10651650eef012be1ccffcbacf3697 \ + --hash=sha256:adce39d67c0edf383647a3a007de0a45fd1b08dedaa5318404f1a73059c2512b \ + --hash=sha256:ade08d343436a94e633db932e7e8407fe7de8083967962b46bdfc1b0ced39454 \ + --hash=sha256:b2bdca22a27e35f16794cf585832e542123296b4687f9fd96822db6bae17bfc9 \ + --hash=sha256:b2f926efda994cdf3c8d3fdb40b9962f86edbc4457e739277b961eced3d0b4c1 \ + --hash=sha256:b457d6430833cee8e4b8e9b6f07aa1c161e5e0d52e118dc102c8f9bd7dd060d6 \ + --hash=sha256:c414fc1ed8ee1dbd5da626cf3710c6013d3d27456651d156711fa24f24bd1291 \ + --hash=sha256:cb76c1a154b83991a3cbbf0dfeb26ec2833ad56f95540b442c73950af2013750 \ + --hash=sha256:dfd97abd83335045a913e3bcc4a09c0ceadbe66580cf573fe961f4a825efa699 \ + --hash=sha256:e914a8cb05ce5c809dd0fe350cfbb4e881bde5e2a38dc04e3afe1b3e58bd158e \ + --hash=sha256:ece6df05e2c41bd46776fbc712e0996f7c94e0d0543af1656956d150c4ca7c81 \ + --hash=sha256:efa874e87e4a647fd2e4f514d5e91c7d493697127beb95e77d2f7561f6905bd9 \ + --hash=sha256:f611e628ef06670df83fce17805c344710ca5cde01edfdc72751311da8585375 + # via matplotlib +cycler==0.12.1 \ + --hash=sha256:85cef7cff222d8644161529808465972e51340599459b8ac3ccbac5a854e0d30 \ + --hash=sha256:88bb128f02ba341da8ef447245a9e138fae777f6a23943da4540077d3601eb1c + # via matplotlib +fonttools==4.55.7 \ + --hash=sha256:05568a66b090ed9d79aefdce2ceb180bb64fc856961deaedc29f5ad51355ce2c \ + --hash=sha256:087ace2d06894ccdb03e6975d05da6bb9cec0c689b2a9983c059880e33a1464a \ + --hash=sha256:09740feed51f9ed816aebf5d82071b7fecf693ac3a7e0fc8ea433f5dc3bd92f5 \ + --hash=sha256:0ed25d7b5fa4ae6a805c2a9cc0e5307d45cbb3b8e155584fe932d0f3b6a997bf \ + --hash=sha256:1101976c703ff4008a928fc3fef42caf06d035bfc4614230d7e797cbe356feb0 \ + --hash=sha256:12e81d44f762156d28b5c93a6b65d98ed73678be45b22546de8ed29736c3cb96 \ + --hash=sha256:1d4be8354c245c00aecfc90f5d3da8606226f0ac22e1cb0837b39139e4c2df85 \ + --hash=sha256:23df0f1003abaf8a435543f59583fc247e7ae1b047ee2263510e0654a5f207e0 \ + --hash=sha256:2dbc08e227fbeb716776905a7bd3c4fc62c8e37c8ef7d481acd10cb5fde12222 \ + --hash=sha256:2e6dffe9cbcd163ef617fab1f81682e4d1629b7a5b9c5e598274dc2d03e88bcd \ + --hash=sha256:3098355e7a7b5ac48d5dc29684a65271187b865b85675033958b57c40364ee34 \ + --hash=sha256:30c3501328363b73a90acc8a722dd199c993f2c4369ea16886128d94e91897ec \ + --hash=sha256:3304dfcf9ca204dd0ef691a287bd851ddd8e8250108658c0677c3fdfec853a20 \ + --hash=sha256:371197de1283cc99f5f10eb91496520eb0e2d079312d014fd6cef9e802174c6a \ + --hash=sha256:3976db357484bf4cb533dfd0d1a444b38ad06062458715ebf21e38c71aff325d \ + --hash=sha256:418ece624fbc04e199f58398ffef3eaad645baba65434871b09eb7350a3a346b \ + --hash=sha256:5ff0daf8b2e0612e5761fed2e4a2f54eff9d9ec0aeb4091c9f3666f9a118325e \ + --hash=sha256:6899e3d97225a8218f525e9754da0376e1c62953a0d57a76c5abaada51e0d140 \ + --hash=sha256:69ed0660750993150f7c4d966c0c1ffaa0385f23ccef85c2ff108062d80dd7ea \ + --hash=sha256:6eb93cbba484a463b5ee83f7dd3211905f27a3871d20d90fb72de84c6c5056e3 \ + --hash=sha256:775ed0700ee6f781436641f18a0c61b1846a8c1aecae6da6b395c4417e2cb567 \ + --hash=sha256:77e5115a425d53be6e31cd0fe9210f62a488bccf81eb113ab5dd7f4fa88e4d81 \ + --hash=sha256:7858dc6823296a053d85b831fa8428781c6c6f06fca44582bf7b6b2ff32a9089 \ + --hash=sha256:7ff8e606f905048dc91a55a06d994b68065bf35752ae199df54a9bf30013dcaa \ + --hash=sha256:82163d58b43eff6e2025a25c32905fdb9042a163cc1ff82dab393e7ffc77a7d5 \ + --hash=sha256:833927d089e6585019f2c85e3f8f7d87733e3fe81cd704ebaca7afa27e2e7113 \ + --hash=sha256:8ef5ee98fc320c158e4e459a5ee40d1ac3728d4ce11c3c8dfd854aa0aa5c042f \ + --hash=sha256:9074a2848ea5b607377e16998dfcf90cf5eb614d0c388541b9782d5cc038e149 \ + --hash=sha256:916e1d926823b4b3b3815c59fc79f4ed670696fdd5fd9a5e690a0503eef38f79 \ + --hash=sha256:9ec71d0cc0242899f87e4c230ed0b22c7b8681f288fb80e3d81c2c54c5bd2c79 \ + --hash=sha256:a3d19ea483b3cd8833e9e2ee8115f3d2044d55d3743d84f9c23b48b52d7516d8 \ + --hash=sha256:a7831d16c95b60866772a15fdcc03772625c4bb6d858e0ad8ef3d6e48709b2ef \ + --hash=sha256:b89da448e0073408d7b2c44935f9fdae4fdc93644899f99f6102ef883ecf083c \ + --hash=sha256:bee4920ebeb540849bc3555d871e2a8487e39ce8263c281f74d5b6d44d2bf1df \ + --hash=sha256:c135c91d47351b84893fb6fcbb8f178eba14f7cb195850264c0675c85e4238b6 \ + --hash=sha256:c26445a7be689f8b70df7d5d2e2c85ec4407bdb769902a23dd45ac44f767575d \ + --hash=sha256:c2680a3e6e2e2d104a7ea81fb89323e1a9122c23b03d6569d0768887d0d76e69 \ + --hash=sha256:c665df9c9d99937a5bf807bace1c0c95bd13f55de8c82aaf9856b868dcbfe5d9 \ + --hash=sha256:d4b1c5939c0521525f45522823508e6fad21175bca978583688ea3b3736e6625 \ + --hash=sha256:d4bd27f0fa5120aaa39f76de5768959bc97300e0f59a3160d466b51436a38aea \ + --hash=sha256:e10c7fb80cdfdc32244514cbea0906e9f53e3cc80d64d3389da09502fd999b55 \ + --hash=sha256:e2cbafedb9462be7cf68c66b6ca1d8309842fe36b729f1b1969595f5d660e5c2 \ + --hash=sha256:e4bde87985012adbd7559bc363d802fb335e92a07ff86a76cf02bebb0b8566d1 \ + --hash=sha256:e696d6e2baf4cc57ded34bb87e5d3a9e4da9732f3d9e8e2c6db0746e57a6dc0b \ + --hash=sha256:ee7aa8bb716318e3d835ef473978e22b7a39c0f1b3b08cc0b0ee1bba6f73bc1e \ + --hash=sha256:f0899cd23967950e7b902ea75af06cfe5f59ac71eb38e98a774c9e596790e6aa \ + --hash=sha256:f0c45eae32d090763820756b18322a70571dada3f1cbe003debc37a9c35bc260 \ + --hash=sha256:f3b63648600dd0081bdd6856a86d014a7f1d2d11c3c974542f866478d832e103 \ + --hash=sha256:f669910b64d27750398f6c56c651367d4954b05c86ff067af1c9949e109cf1e2 \ + --hash=sha256:fd4ebc475d43f3de2b26e0cf551eff92c24e22d1aee03dc1b33adb52fc2e6cb2 + # via matplotlib +kiwisolver==1.4.8 \ + --hash=sha256:01c3d31902c7db5fb6182832713d3b4122ad9317c2c5877d0539227d96bb2e50 \ + --hash=sha256:034d2c891f76bd3edbdb3ea11140d8510dca675443da7304205a2eaa45d8334c \ + --hash=sha256:085940635c62697391baafaaeabdf3dd7a6c3643577dde337f4d66eba021b2b8 \ + --hash=sha256:08e77738ed7538f036cd1170cbed942ef749137b1311fa2bbe2a7fda2f6bf3cc \ + --hash=sha256:111793b232842991be367ed828076b03d96202c19221b5ebab421ce8bcad016f \ + --hash=sha256:11e1022b524bd48ae56c9b4f9296bce77e15a2e42a502cceba602f804b32bb79 \ + --hash=sha256:151dffc4865e5fe6dafce5480fab84f950d14566c480c08a53c663a0020504b6 \ + --hash=sha256:16523b40aab60426ffdebe33ac374457cf62863e330a90a0383639ce14bf44b2 \ + --hash=sha256:1732e065704b47c9afca7ffa272f845300a4eb959276bf6970dc07265e73b605 \ + --hash=sha256:1c8ceb754339793c24aee1c9fb2485b5b1f5bb1c2c214ff13368431e51fc9a09 \ + --hash=sha256:23454ff084b07ac54ca8be535f4174170c1094a4cff78fbae4f73a4bcc0d4dab \ + --hash=sha256:23d5f023bdc8c7e54eb65f03ca5d5bb25b601eac4d7f1a042888a1f45237987e \ + --hash=sha256:257af1622860e51b1a9d0ce387bf5c2c4f36a90594cb9514f55b074bcc787cfc \ + --hash=sha256:286b18e86682fd2217a48fc6be6b0f20c1d0ed10958d8dc53453ad58d7be0bf8 \ + --hash=sha256:291331973c64bb9cce50bbe871fb2e675c4331dab4f31abe89f175ad7679a4d7 \ + --hash=sha256:2f0121b07b356a22fb0414cec4666bbe36fd6d0d759db3d37228f496ed67c880 \ + --hash=sha256:3452046c37c7692bd52b0e752b87954ef86ee2224e624ef7ce6cb21e8c41cc1b \ + --hash=sha256:34d142fba9c464bc3bbfeff15c96eab0e7310343d6aefb62a79d51421fcc5f1b \ + --hash=sha256:369b75d40abedc1da2c1f4de13f3482cb99e3237b38726710f4a793432b1c5ff \ + --hash=sha256:36dbbfd34838500a31f52c9786990d00150860e46cd5041386f217101350f0d3 \ + --hash=sha256:370fd2df41660ed4e26b8c9d6bbcad668fbe2560462cba151a721d49e5b6628c \ + --hash=sha256:3a96c0e790ee875d65e340ab383700e2b4891677b7fcd30a699146f9384a2bb0 \ + --hash=sha256:3b9b4d2892fefc886f30301cdd80debd8bb01ecdf165a449eb6e78f79f0fabd6 \ + --hash=sha256:3cd3bc628b25f74aedc6d374d5babf0166a92ff1317f46267f12d2ed54bc1d30 \ + --hash=sha256:3ddc373e0eef45b59197de815b1b28ef89ae3955e7722cc9710fb91cd77b7f47 \ + --hash=sha256:4191ee8dfd0be1c3666ccbac178c5a05d5f8d689bbe3fc92f3c4abec817f8fe0 \ + --hash=sha256:54a62808ac74b5e55a04a408cda6156f986cefbcf0ada13572696b507cc92fa1 \ + --hash=sha256:577facaa411c10421314598b50413aa1ebcf5126f704f1e5d72d7e4e9f020d90 \ + --hash=sha256:641f2ddf9358c80faa22e22eb4c9f54bd3f0e442e038728f500e3b978d00aa7d \ + --hash=sha256:65ea09a5a3faadd59c2ce96dc7bf0f364986a315949dc6374f04396b0d60e09b \ + --hash=sha256:68269e60ee4929893aad82666821aaacbd455284124817af45c11e50a4b42e3c \ + --hash=sha256:69b5637c3f316cab1ec1c9a12b8c5f4750a4c4b71af9157645bf32830e39c03a \ + --hash=sha256:7506488470f41169b86d8c9aeff587293f530a23a23a49d6bc64dab66bedc71e \ + --hash=sha256:768cade2c2df13db52475bd28d3a3fac8c9eff04b0e9e2fda0f3760f20b3f7fc \ + --hash=sha256:77e6f57a20b9bd4e1e2cedda4d0b986ebd0216236f0106e55c28aea3d3d69b16 \ + --hash=sha256:782bb86f245ec18009890e7cb8d13a5ef54dcf2ebe18ed65f795e635a96a1c6a \ + --hash=sha256:7a3ad337add5148cf51ce0b55642dc551c0b9d6248458a757f98796ca7348712 \ + --hash=sha256:7cd2785b9391f2873ad46088ed7599a6a71e762e1ea33e87514b1a441ed1da1c \ + --hash=sha256:7e9a60b50fe8b2ec6f448fe8d81b07e40141bfced7f896309df271a0b92f80f3 \ + --hash=sha256:84a2f830d42707de1d191b9490ac186bf7997a9495d4e9072210a1296345f7dc \ + --hash=sha256:856b269c4d28a5c0d5e6c1955ec36ebfd1651ac00e1ce0afa3e28da95293b561 \ + --hash=sha256:858416b7fb777a53f0c59ca08190ce24e9abbd3cffa18886a5781b8e3e26f65d \ + --hash=sha256:87b287251ad6488e95b4f0b4a79a6d04d3ea35fde6340eb38fbd1ca9cd35bbbc \ + --hash=sha256:88c6f252f6816a73b1f8c904f7bbe02fd67c09a69f7cb8a0eecdbf5ce78e63db \ + --hash=sha256:893f5525bb92d3d735878ec00f781b2de998333659507d29ea4466208df37bed \ + --hash=sha256:89c107041f7b27844179ea9c85d6da275aa55ecf28413e87624d033cf1f6b751 \ + --hash=sha256:918139571133f366e8362fa4a297aeba86c7816b7ecf0bc79168080e2bd79957 \ + --hash=sha256:99cea8b9dd34ff80c521aef46a1dddb0dcc0283cf18bde6d756f1e6f31772165 \ + --hash=sha256:a17b7c4f5b2c51bb68ed379defd608a03954a1845dfed7cc0117f1cc8a9b7fd2 \ + --hash=sha256:a3c44cb68861de93f0c4a8175fbaa691f0aa22550c331fefef02b618a9dcb476 \ + --hash=sha256:a4d3601908c560bdf880f07d94f31d734afd1bb71e96585cace0e38ef44c6d84 \ + --hash=sha256:a5ce1e481a74b44dd5e92ff03ea0cb371ae7a0268318e202be06c8f04f4f1246 \ + --hash=sha256:a66f60f8d0c87ab7f59b6fb80e642ebb29fec354a4dfad687ca4092ae69d04f4 \ + --hash=sha256:b21dbe165081142b1232a240fc6383fd32cdd877ca6cc89eab93e5f5883e1c25 \ + --hash=sha256:b47a465040146981dc9db8647981b8cb96366fbc8d452b031e4f8fdffec3f26d \ + --hash=sha256:b5773efa2be9eb9fcf5415ea3ab70fc785d598729fd6057bea38d539ead28271 \ + --hash=sha256:b83dc6769ddbc57613280118fb4ce3cd08899cc3369f7d0e0fab518a7cf37fdb \ + --hash=sha256:bade438f86e21d91e0cf5dd7c0ed00cda0f77c8c1616bd83f9fc157fa6760d31 \ + --hash=sha256:bcb1ebc3547619c3b58a39e2448af089ea2ef44b37988caf432447374941574e \ + --hash=sha256:be4816dc51c8a471749d664161b434912eee82f2ea66bd7628bd14583a833e85 \ + --hash=sha256:c07b29089b7ba090b6f1a669f1411f27221c3662b3a1b7010e67b59bb5a6f10b \ + --hash=sha256:c2b9a96e0f326205af81a15718a9073328df1173a2619a68553decb7097fd5d7 \ + --hash=sha256:c5020c83e8553f770cb3b5fc13faac40f17e0b205bd237aebd21d53d733adb03 \ + --hash=sha256:c72941acb7b67138f35b879bbe85be0f6c6a70cab78fe3ef6db9c024d9223e5b \ + --hash=sha256:c8bf637892dc6e6aad2bc6d4d69d08764166e5e3f69d469e55427b6ac001b19d \ + --hash=sha256:cc978a80a0db3a66d25767b03688f1147a69e6237175c0f4ffffaaedf744055a \ + --hash=sha256:ce2cf1e5688edcb727fdf7cd1bbd0b6416758996826a8be1d958f91880d0809d \ + --hash=sha256:d47b28d1dfe0793d5e96bce90835e17edf9a499b53969b03c6c47ea5985844c3 \ + --hash=sha256:d47cfb2650f0e103d4bf68b0b5804c68da97272c84bb12850d877a95c056bd67 \ + --hash=sha256:d5536185fce131780ebd809f8e623bf4030ce1b161353166c49a3c74c287897f \ + --hash=sha256:d561d2d8883e0819445cfe58d7ddd673e4015c3c57261d7bdcd3710d0d14005c \ + --hash=sha256:d6af5e8815fd02997cb6ad9bbed0ee1e60014438ee1a5c2444c96f87b8843502 \ + --hash=sha256:d6d6bd87df62c27d4185de7c511c6248040afae67028a8a22012b010bc7ad062 \ + --hash=sha256:dace81d28c787956bfbfbbfd72fdcef014f37d9b48830829e488fdb32b49d954 \ + --hash=sha256:e063ef9f89885a1d68dd8b2e18f5ead48653176d10a0e324e3b0030e3a69adeb \ + --hash=sha256:e7a019419b7b510f0f7c9dceff8c5eae2392037eae483a7f9162625233802b0a \ + --hash=sha256:eaa973f1e05131de5ff3569bbba7f5fd07ea0595d3870ed4a526d486fe57fa1b \ + --hash=sha256:eb158fe28ca0c29f2260cca8c43005329ad58452c36f0edf298204de32a9a3ed \ + --hash=sha256:ed33ca2002a779a2e20eeb06aea7721b6e47f2d4b8a8ece979d8ba9e2a167e34 \ + --hash=sha256:fc2ace710ba7c1dfd1a3b42530b62b9ceed115f19a1656adefce7b1782a37794 + # via matplotlib +matplotlib==3.10.0 \ + --hash=sha256:01d2b19f13aeec2e759414d3bfe19ddfb16b13a1250add08d46d5ff6f9be83c6 \ + --hash=sha256:12eaf48463b472c3c0f8dbacdbf906e573013df81a0ab82f0616ea4b11281908 \ + --hash=sha256:2c5829a5a1dd5a71f0e31e6e8bb449bc0ee9dbfb05ad28fc0c6b55101b3a4be6 \ + --hash=sha256:2fbbabc82fde51391c4da5006f965e36d86d95f6ee83fb594b279564a4c5d0d2 \ + --hash=sha256:3547d153d70233a8496859097ef0312212e2689cdf8d7ed764441c77604095ae \ + --hash=sha256:359f87baedb1f836ce307f0e850d12bb5f1936f70d035561f90d41d305fdacea \ + --hash=sha256:3b427392354d10975c1d0f4ee18aa5844640b512d5311ef32efd4dd7db106ede \ + --hash=sha256:4659665bc7c9b58f8c00317c3c2a299f7f258eeae5a5d56b4c64226fca2f7c59 \ + --hash=sha256:4673ff67a36152c48ddeaf1135e74ce0d4bce1bbf836ae40ed39c29edf7e2765 \ + --hash=sha256:503feb23bd8c8acc75541548a1d709c059b7184cde26314896e10a9f14df5f12 \ + --hash=sha256:5439f4c5a3e2e8eab18e2f8c3ef929772fd5641876db71f08127eed95ab64683 \ + --hash=sha256:5cdbaf909887373c3e094b0318d7ff230b2ad9dcb64da7ade654182872ab2593 \ + --hash=sha256:5e6c6461e1fc63df30bf6f80f0b93f5b6784299f721bc28530477acd51bfc3d1 \ + --hash=sha256:5fd41b0ec7ee45cd960a8e71aea7c946a28a0b8a4dcee47d2856b2af051f334c \ + --hash=sha256:607b16c8a73943df110f99ee2e940b8a1cbf9714b65307c040d422558397dac5 \ + --hash=sha256:7e8632baebb058555ac0cde75db885c61f1212e47723d63921879806b40bec6a \ + --hash=sha256:81713dd0d103b379de4516b861d964b1d789a144103277769238c732229d7f03 \ + --hash=sha256:845d96568ec873be63f25fa80e9e7fae4be854a66a7e2f0c8ccc99e94a8bd4ef \ + --hash=sha256:95b710fea129c76d30be72c3b38f330269363fbc6e570a5dd43580487380b5ff \ + --hash=sha256:96f2886f5c1e466f21cc41b70c5a0cd47bfa0015eb2d5793c88ebce658600e25 \ + --hash=sha256:994c07b9d9fe8d25951e3202a68c17900679274dadfc1248738dcfa1bd40d7f3 \ + --hash=sha256:9ade1003376731a971e398cc4ef38bb83ee8caf0aee46ac6daa4b0506db1fd06 \ + --hash=sha256:9b0558bae37f154fffda54d779a592bc97ca8b4701f1c710055b609a3bac44c8 \ + --hash=sha256:a2a43cbefe22d653ab34bb55d42384ed30f611bcbdea1f8d7f431011a2e1c62e \ + --hash=sha256:a994f29e968ca002b50982b27168addfd65f0105610b6be7fa515ca4b5307c95 \ + --hash=sha256:ad2e15300530c1a94c63cfa546e3b7864bd18ea2901317bae8bbf06a5ade6dcf \ + --hash=sha256:ae80dc3a4add4665cf2faa90138384a7ffe2a4e37c58d83e115b54287c4f06ef \ + --hash=sha256:b886d02a581b96704c9d1ffe55709e49b4d2d52709ccebc4be42db856e511278 \ + --hash=sha256:c40ba2eb08b3f5de88152c2333c58cee7edcead0a2a0d60fcafa116b17117adc \ + --hash=sha256:c55b20591ced744aa04e8c3e4b7543ea4d650b6c3c4b208c08a05b4010e8b442 \ + --hash=sha256:c58a9622d5dbeb668f407f35f4e6bfac34bb9ecdcc81680c04d0258169747997 \ + --hash=sha256:d44cb942af1693cced2604c33a9abcef6205601c445f6d0dc531d813af8a2f5a \ + --hash=sha256:d907fddb39f923d011875452ff1eca29a9e7f21722b873e90db32e5d8ddff12e \ + --hash=sha256:fd44fc75522f58612ec4a33958a7e5552562b7705b42ef1b4f8c0818e304a363 + # via -r flow/util/requirements.in +numpy==2.2.2 \ + --hash=sha256:02935e2c3c0c6cbe9c7955a8efa8908dd4221d7755644c59d1bba28b94fd334f \ + --hash=sha256:0349b025e15ea9d05c3d63f9657707a4e1d471128a3b1d876c095f328f8ff7f0 \ + --hash=sha256:09d6a2032faf25e8d0cadde7fd6145118ac55d2740132c1d845f98721b5ebcfd \ + --hash=sha256:0bc61b307655d1a7f9f4b043628b9f2b721e80839914ede634e3d485913e1fb2 \ + --hash=sha256:0eec19f8af947a61e968d5429f0bd92fec46d92b0008d0a6685b40d6adf8a4f4 \ + --hash=sha256:106397dbbb1896f99e044efc90360d098b3335060375c26aa89c0d8a97c5f648 \ + --hash=sha256:128c41c085cab8a85dc29e66ed88c05613dccf6bc28b3866cd16050a2f5448be \ + --hash=sha256:149d1113ac15005652e8d0d3f6fd599360e1a708a4f98e43c9c77834a28238cb \ + --hash=sha256:159ff6ee4c4a36a23fe01b7c3d07bd8c14cc433d9720f977fcd52c13c0098160 \ + --hash=sha256:22ea3bb552ade325530e72a0c557cdf2dea8914d3a5e1fecf58fa5dbcc6f43cd \ + --hash=sha256:23ae9f0c2d889b7b2d88a3791f6c09e2ef827c2446f1c4a3e3e76328ee4afd9a \ + --hash=sha256:250c16b277e3b809ac20d1f590716597481061b514223c7badb7a0f9993c7f84 \ + --hash=sha256:2ec6c689c61df613b783aeb21f945c4cbe6c51c28cb70aae8430577ab39f163e \ + --hash=sha256:2ffbb1acd69fdf8e89dd60ef6182ca90a743620957afb7066385a7bbe88dc748 \ + --hash=sha256:3074634ea4d6df66be04f6728ee1d173cfded75d002c75fac79503a880bf3825 \ + --hash=sha256:356ca982c188acbfa6af0d694284d8cf20e95b1c3d0aefa8929376fea9146f60 \ + --hash=sha256:3fbe72d347fbc59f94124125e73fc4976a06927ebc503ec5afbfb35f193cd957 \ + --hash=sha256:40c7ff5da22cd391944a28c6a9c638a5eef77fcf71d6e3a79e1d9d9e82752715 \ + --hash=sha256:41184c416143defa34cc8eb9d070b0a5ba4f13a0fa96a709e20584638254b317 \ + --hash=sha256:451e854cfae0febe723077bd0cf0a4302a5d84ff25f0bfece8f29206c7bed02e \ + --hash=sha256:4525b88c11906d5ab1b0ec1f290996c0020dd318af8b49acaa46f198b1ffc283 \ + --hash=sha256:463247edcee4a5537841d5350bc87fe8e92d7dd0e8c71c995d2c6eecb8208278 \ + --hash=sha256:4dbd80e453bd34bd003b16bd802fac70ad76bd463f81f0c518d1245b1c55e3d9 \ + --hash=sha256:57b4012e04cc12b78590a334907e01b3a85efb2107df2b8733ff1ed05fce71de \ + --hash=sha256:5a8c863ceacae696aff37d1fd636121f1a512117652e5dfb86031c8d84836369 \ + --hash=sha256:5acea83b801e98541619af398cc0109ff48016955cc0818f478ee9ef1c5c3dcb \ + --hash=sha256:642199e98af1bd2b6aeb8ecf726972d238c9877b0f6e8221ee5ab945ec8a2189 \ + --hash=sha256:64bd6e1762cd7f0986a740fee4dff927b9ec2c5e4d9a28d056eb17d332158014 \ + --hash=sha256:6d9fc9d812c81e6168b6d405bf00b8d6739a7f72ef22a9214c4241e0dc70b323 \ + --hash=sha256:7079129b64cb78bdc8d611d1fd7e8002c0a2565da6a47c4df8062349fee90e3e \ + --hash=sha256:7dca87ca328f5ea7dafc907c5ec100d187911f94825f8700caac0b3f4c384b49 \ + --hash=sha256:860fd59990c37c3ef913c3ae390b3929d005243acca1a86facb0773e2d8d9e50 \ + --hash=sha256:8e6da5cffbbe571f93588f562ed130ea63ee206d12851b60819512dd3e1ba50d \ + --hash=sha256:8ec0636d3f7d68520afc6ac2dc4b8341ddb725039de042faf0e311599f54eb37 \ + --hash=sha256:9491100aba630910489c1d0158034e1c9a6546f0b1340f716d522dc103788e39 \ + --hash=sha256:97b974d3ba0fb4612b77ed35d7627490e8e3dff56ab41454d9e8b23448940576 \ + --hash=sha256:995f9e8181723852ca458e22de5d9b7d3ba4da3f11cc1cb113f093b271d7965a \ + --hash=sha256:9dd47ff0cb2a656ad69c38da850df3454da88ee9a6fde0ba79acceee0e79daba \ + --hash=sha256:9fad446ad0bc886855ddf5909cbf8cb5d0faa637aaa6277fb4b19ade134ab3c7 \ + --hash=sha256:a972cec723e0563aa0823ee2ab1df0cb196ed0778f173b381c871a03719d4826 \ + --hash=sha256:ac9bea18d6d58a995fac1b2cb4488e17eceeac413af014b1dd26170b766d8467 \ + --hash=sha256:b0531f0b0e07643eb089df4c509d30d72c9ef40defa53e41363eca8a8cc61495 \ + --hash=sha256:b208cfd4f5fe34e1535c08983a1a6803fdbc7a1e86cf13dd0c61de0b51a0aadc \ + --hash=sha256:b3482cb7b3325faa5f6bc179649406058253d91ceda359c104dac0ad320e1391 \ + --hash=sha256:b6fb9c32a91ec32a689ec6410def76443e3c750e7cfc3fb2206b985ffb2b85f0 \ + --hash=sha256:b78ea78450fd96a498f50ee096f69c75379af5138f7881a51355ab0e11286c97 \ + --hash=sha256:bd249bc894af67cbd8bad2c22e7cbcd46cf87ddfca1f1289d1e7e54868cc785c \ + --hash=sha256:c7d1fd447e33ee20c1f33f2c8e6634211124a9aabde3c617687d8b739aa69eac \ + --hash=sha256:d0bbe7dd86dca64854f4b6ce2ea5c60b51e36dfd597300057cf473d3615f2369 \ + --hash=sha256:d6d6a0910c3b4368d89dde073e630882cdb266755565155bc33520283b2d9df8 \ + --hash=sha256:da1eeb460ecce8d5b8608826595c777728cdf28ce7b5a5a8c8ac8d949beadcf2 \ + --hash=sha256:e0c8854b09bc4de7b041148d8550d3bd712b5c21ff6a8ed308085f190235d7ff \ + --hash=sha256:e0d4142eb40ca6f94539e4db929410f2a46052a0fe7a2c1c59f6179c39938d2a \ + --hash=sha256:e9e82dcb3f2ebbc8cb5ce1102d5f1c5ed236bf8a11730fb45ba82e2841ec21df \ + --hash=sha256:ed6906f61834d687738d25988ae117683705636936cc605be0bb208b23df4d8f + # via + # contourpy + # matplotlib +packaging==24.2 \ + --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 \ + --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f + # via matplotlib +pillow==11.1.0 \ + --hash=sha256:015c6e863faa4779251436db398ae75051469f7c903b043a48f078e437656f83 \ + --hash=sha256:0a2f91f8a8b367e7a57c6e91cd25af510168091fb89ec5146003e424e1558a96 \ + --hash=sha256:11633d58b6ee5733bde153a8dafd25e505ea3d32e261accd388827ee987baf65 \ + --hash=sha256:2062ffb1d36544d42fcaa277b069c88b01bb7298f4efa06731a7fd6cc290b81a \ + --hash=sha256:31eba6bbdd27dde97b0174ddf0297d7a9c3a507a8a1480e1e60ef914fe23d352 \ + --hash=sha256:3362c6ca227e65c54bf71a5f88b3d4565ff1bcbc63ae72c34b07bbb1cc59a43f \ + --hash=sha256:368da70808b36d73b4b390a8ffac11069f8a5c85f29eff1f1b01bcf3ef5b2a20 \ + --hash=sha256:36ba10b9cb413e7c7dfa3e189aba252deee0602c86c309799da5a74009ac7a1c \ + --hash=sha256:3764d53e09cdedd91bee65c2527815d315c6b90d7b8b79759cc48d7bf5d4f114 \ + --hash=sha256:3a5fe20a7b66e8135d7fd617b13272626a28278d0e578c98720d9ba4b2439d49 \ + --hash=sha256:3cdcdb0b896e981678eee140d882b70092dac83ac1cdf6b3a60e2216a73f2b91 \ + --hash=sha256:4637b88343166249fe8aa94e7c4a62a180c4b3898283bb5d3d2fd5fe10d8e4e0 \ + --hash=sha256:4db853948ce4e718f2fc775b75c37ba2efb6aaea41a1a5fc57f0af59eee774b2 \ + --hash=sha256:4dd43a78897793f60766563969442020e90eb7847463eca901e41ba186a7d4a5 \ + --hash=sha256:54251ef02a2309b5eec99d151ebf5c9904b77976c8abdcbce7891ed22df53884 \ + --hash=sha256:54ce1c9a16a9561b6d6d8cb30089ab1e5eb66918cb47d457bd996ef34182922e \ + --hash=sha256:593c5fd6be85da83656b93ffcccc2312d2d149d251e98588b14fbc288fd8909c \ + --hash=sha256:5bb94705aea800051a743aa4874bb1397d4695fb0583ba5e425ee0328757f196 \ + --hash=sha256:67cd427c68926108778a9005f2a04adbd5e67c442ed21d95389fe1d595458756 \ + --hash=sha256:70ca5ef3b3b1c4a0812b5c63c57c23b63e53bc38e758b37a951e5bc466449861 \ + --hash=sha256:73ddde795ee9b06257dac5ad42fcb07f3b9b813f8c1f7f870f402f4dc54b5269 \ + --hash=sha256:758e9d4ef15d3560214cddbc97b8ef3ef86ce04d62ddac17ad39ba87e89bd3b1 \ + --hash=sha256:7d33d2fae0e8b170b6a6c57400e077412240f6f5bb2a342cf1ee512a787942bb \ + --hash=sha256:7fdadc077553621911f27ce206ffcbec7d3f8d7b50e0da39f10997e8e2bb7f6a \ + --hash=sha256:8000376f139d4d38d6851eb149b321a52bb8893a88dae8ee7d95840431977081 \ + --hash=sha256:837060a8599b8f5d402e97197d4924f05a2e0d68756998345c829c33186217b1 \ + --hash=sha256:89dbdb3e6e9594d512780a5a1c42801879628b38e3efc7038094430844e271d8 \ + --hash=sha256:8c730dc3a83e5ac137fbc92dfcfe1511ce3b2b5d7578315b63dbbb76f7f51d90 \ + --hash=sha256:8e275ee4cb11c262bd108ab2081f750db2a1c0b8c12c1897f27b160c8bd57bbc \ + --hash=sha256:9044b5e4f7083f209c4e35aa5dd54b1dd5b112b108648f5c902ad586d4f945c5 \ + --hash=sha256:93a18841d09bcdd774dcdc308e4537e1f867b3dec059c131fde0327899734aa1 \ + --hash=sha256:9409c080586d1f683df3f184f20e36fb647f2e0bc3988094d4fd8c9f4eb1b3b3 \ + --hash=sha256:96f82000e12f23e4f29346e42702b6ed9a2f2fea34a740dd5ffffcc8c539eb35 \ + --hash=sha256:9aa9aeddeed452b2f616ff5507459e7bab436916ccb10961c4a382cd3e03f47f \ + --hash=sha256:9ee85f0696a17dd28fbcfceb59f9510aa71934b483d1f5601d1030c3c8304f3c \ + --hash=sha256:a07dba04c5e22824816b2615ad7a7484432d7f540e6fa86af60d2de57b0fcee2 \ + --hash=sha256:a3cd561ded2cf2bbae44d4605837221b987c216cff94f49dfeed63488bb228d2 \ + --hash=sha256:a697cd8ba0383bba3d2d3ada02b34ed268cb548b369943cd349007730c92bddf \ + --hash=sha256:a76da0a31da6fcae4210aa94fd779c65c75786bc9af06289cd1c184451ef7a65 \ + --hash=sha256:a85b653980faad27e88b141348707ceeef8a1186f75ecc600c395dcac19f385b \ + --hash=sha256:a8d65b38173085f24bc07f8b6c505cbb7418009fa1a1fcb111b1f4961814a442 \ + --hash=sha256:aa8dd43daa836b9a8128dbe7d923423e5ad86f50a7a14dc688194b7be5c0dea2 \ + --hash=sha256:ab8a209b8485d3db694fa97a896d96dd6533d63c22829043fd9de627060beade \ + --hash=sha256:abc56501c3fd148d60659aae0af6ddc149660469082859fa7b066a298bde9482 \ + --hash=sha256:ad5db5781c774ab9a9b2c4302bbf0c1014960a0a7be63278d13ae6fdf88126fe \ + --hash=sha256:ae98e14432d458fc3de11a77ccb3ae65ddce70f730e7c76140653048c71bfcbc \ + --hash=sha256:b20be51b37a75cc54c2c55def3fa2c65bb94ba859dde241cd0a4fd302de5ae0a \ + --hash=sha256:b523466b1a31d0dcef7c5be1f20b942919b62fd6e9a9be199d035509cbefc0ec \ + --hash=sha256:b5d658fbd9f0d6eea113aea286b21d3cd4d3fd978157cbf2447a6035916506d3 \ + --hash=sha256:b6123aa4a59d75f06e9dd3dac5bf8bc9aa383121bb3dd9a7a612e05eabc9961a \ + --hash=sha256:bd165131fd51697e22421d0e467997ad31621b74bfc0b75956608cb2906dda07 \ + --hash=sha256:bf902d7413c82a1bfa08b06a070876132a5ae6b2388e2712aab3a7cbc02205c6 \ + --hash=sha256:c12fc111ef090845de2bb15009372175d76ac99969bdf31e2ce9b42e4b8cd88f \ + --hash=sha256:c1eec9d950b6fe688edee07138993e54ee4ae634c51443cfb7c1e7613322718e \ + --hash=sha256:c640e5a06869c75994624551f45e5506e4256562ead981cce820d5ab39ae2192 \ + --hash=sha256:cc1331b6d5a6e144aeb5e626f4375f5b7ae9934ba620c0ac6b3e43d5e683a0f0 \ + --hash=sha256:cfd5cd998c2e36a862d0e27b2df63237e67273f2fc78f47445b14e73a810e7e6 \ + --hash=sha256:d3d8da4a631471dfaf94c10c85f5277b1f8e42ac42bade1ac67da4b4a7359b73 \ + --hash=sha256:d44ff19eea13ae4acdaaab0179fa68c0c6f2f45d66a4d8ec1eda7d6cecbcc15f \ + --hash=sha256:dd0052e9db3474df30433f83a71b9b23bd9e4ef1de13d92df21a52c0303b8ab6 \ + --hash=sha256:dd0e081319328928531df7a0e63621caf67652c8464303fd102141b785ef9547 \ + --hash=sha256:dda60aa465b861324e65a78c9f5cf0f4bc713e4309f83bc387be158b077963d9 \ + --hash=sha256:e06695e0326d05b06833b40b7ef477e475d0b1ba3a6d27da1bb48c23209bf457 \ + --hash=sha256:e1abe69aca89514737465752b4bcaf8016de61b3be1397a8fc260ba33321b3a8 \ + --hash=sha256:e267b0ed063341f3e60acd25c05200df4193e15a4a5807075cd71225a2386e26 \ + --hash=sha256:e5449ca63da169a2e6068dd0e2fcc8d91f9558aba89ff6d02121ca8ab11e79e5 \ + --hash=sha256:e63e4e5081de46517099dc30abe418122f54531a6ae2ebc8680bcd7096860eab \ + --hash=sha256:f189805c8be5ca5add39e6f899e6ce2ed824e65fb45f3c28cb2841911da19070 \ + --hash=sha256:f7955ecf5609dee9442cbface754f2c6e541d9e6eda87fad7f7a989b0bdb9d71 \ + --hash=sha256:f86d3a7a9af5d826744fabf4afd15b9dfef44fe69a98541f666f66fbb8d3fef9 \ + --hash=sha256:fbd43429d0d7ed6533b25fc993861b8fd512c42d04514a0dd6337fb3ccf22761 + # via matplotlib +pyparsing==3.2.1 \ + --hash=sha256:506ff4f4386c4cec0590ec19e6302d3aedb992fdc02c761e90416f158dacf8e1 \ + --hash=sha256:61980854fd66de3a90028d679a954d5f2623e83144b5afe5ee86f43d762e5f0a + # via matplotlib +python-dateutil==2.9.0.post0 \ + --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 \ + --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427 + # via matplotlib +pyyaml==6.0.2 \ + --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff \ + --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 \ + --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 \ + --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e \ + --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 \ + --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 \ + --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 \ + --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee \ + --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 \ + --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 \ + --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a \ + --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf \ + --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 \ + --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 \ + --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 \ + --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 \ + --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc \ + --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a \ + --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 \ + --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 \ + --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c \ + --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 \ + --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d \ + --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 \ + --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 \ + --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e \ + --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b \ + --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 \ + --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 \ + --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 \ + --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 \ + --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 \ + --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b \ + --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 \ + --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 \ + --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 \ + --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e \ + --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f \ + --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 \ + --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 \ + --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab \ + --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 \ + --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 \ + --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e \ + --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 \ + --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d \ + --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 \ + --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 \ + --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed \ + --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 \ + --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba \ + --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 \ + --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4 + # via -r flow/util/requirements.in +six==1.17.0 \ + --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 \ + --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81 + # via python-dateutil diff --git a/flow/util/run.sh b/flow/util/run.sh deleted file mode 100644 index 50bf15d61d..0000000000 --- a/flow/util/run.sh +++ /dev/null @@ -1,9 +0,0 @@ -DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk make -DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk make -DESIGN_CONFIG=./designs/sky130hd/aes/config.mk make -DESIGN_CONFIG=./designs/sky130hd/jpeg/config.mk make -# -DESIGN_CONFIG=./designs/gf12/gcd/config.mk make -DESIGN_CONFIG=./designs/gf12/ibex/config.mk make -DESIGN_CONFIG=./designs/gf12/aes/config.mk make -DESIGN_CONFIG=./designs/gf12/jpeg/config.mk make diff --git a/flow/util/updateRules.py b/flow/util/updateRules.py deleted file mode 100644 index cc4e2d747a..0000000000 --- a/flow/util/updateRules.py +++ /dev/null @@ -1,80 +0,0 @@ -import firebase_admin -from firebase_admin import credentials -from firebase_admin import firestore -from datetime import datetime -import json -import argparse -import re -import os -import requests -from genRuleFile import get_golden -from genRuleFile import update_rules -from genRuleFile import get_metrics - -# make sure the working dir is flow/ -os.chdir(os.path.join(os.path.dirname(os.path.abspath(__file__)), "..")) - -# Create the argument parser -parser = argparse.ArgumentParser(description="Process some integers.") - -parser.add_argument("--keyFile", type=str, help="Service account credentials key file") -parser.add_argument( - "--overwrite", - action="store_true", - default=False, - help="Overwrite the golden metrics", -) -parser.add_argument( - "--apiURL", - type=str, - default="http://localhost:80", - help="Set API Base URL to get golden metrics", -) -parser.add_argument( - "--commitSHA", - type=str, - default="", - help="commit for the metrics used to update the rules", -) - -# Parse the arguments -args = parser.parse_args() - -# Initialize Firebase Admin SDK with service account credentials -cred = credentials.Certificate(json.loads(args.keyFile)) - -firebase_admin.initialize_app(cred) -# Initialize Firestore client -db = firestore.client() - -api_base_url = args.apiURL - -runFilename = f"rules-base.json" - -for designsDir, dirs, files in sorted(os.walk("designs", topdown=False)): - dirList = designsDir.split(os.sep) - if len(dirList) != 3: - continue - - platform = dirList[1] - design = dirList[2] - test = "{} {}".format(platform, design) - dataFile = os.path.join(designsDir, runFilename) - if os.path.exists(dataFile) and ( - platform != "sky130hd_fakestack" or platform != "src" - ): - metrics, error_metrics = get_metrics( - args.commitSHA, # commit - platform, # platform - design, # design - api_base_url, # backend url - ) - if error_metrics: - print("failed to update rule for", platform, design) - continue - update_rules( - designsDir, # design directory - "base", # variant - metrics, # metrics needed for update, default is {} in case of file - args.overwrite, # overwrite flag, default is false - ) diff --git a/flow/util/uploadMetadata.py b/flow/util/uploadMetadata.py index 6073d35775..b940941e7a 100755 --- a/flow/util/uploadMetadata.py +++ b/flow/util/uploadMetadata.py @@ -31,7 +31,7 @@ args = parser.parse_args() -def upload_data(db, datafile, platform, design, variant, args, rules): +def upload_data(db, dataFile, platform, design, variant, args, rules): # Set the document data key = args.commitSHA + "-" + platform + "-" + design + "-" + variant doc_ref = db.collection("build_metrics").document(key) @@ -166,9 +166,7 @@ def upload_data(db, datafile, platform, design, variant, args, rules): raise Exception(f"Failed to upload data for {platform} {design} {variant}.") -def get_rules(platform, design, variant): - runFilename = f"rules-{variant}.json" - dataFile = os.path.join("designs", platform, design, runFilename) +def get_rules(dataFile): data = {} if os.path.exists(dataFile): with open(dataFile) as f: @@ -182,7 +180,7 @@ def get_rules(platform, design, variant): # Initialize Firestore client db = firestore.client() -runFilename = f"metadata-{args.variant}.json" +RUN_FILENAME = "metadata.json" for reportDir, dirs, files in sorted(os.walk("reports", topdown=False)): dirList = reportDir.split(os.sep) @@ -193,7 +191,7 @@ def get_rules(platform, design, variant): platform = dirList[1] design = dirList[2] variant = dirList[3] - dataFile = os.path.join(reportDir, runFilename) + dataFile = os.path.join(reportDir, RUN_FILENAME) if not os.path.exists(dataFile): print(f"[WARN] No data file for {platform} {design} {variant}.") continue @@ -201,6 +199,6 @@ def get_rules(platform, design, variant): print(f"[WARN] Skiping upload {platform} {design} {variant}.") continue print(f"[INFO] Get rules for {platform} {design} {variant}.") - rules = get_rules(platform, design, variant) + rules = get_rules(os.path.join("designs", platform, design, RUN_FILENAME)) print(f"[INFO] Upload data for {platform} {design} {variant}.") upload_data(db, dataFile, platform, design, variant, args, rules) diff --git a/flow/util/utils.mk b/flow/util/utils.mk index c1f368bbd9..84f10aa11a 100644 --- a/flow/util/utils.mk +++ b/flow/util/utils.mk @@ -1,45 +1,86 @@ # Utilities #=============================================================================== .PHONY: metadata -metadata: finish - @echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt - @$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ - -p $(PLATFORM) \ - -v $(FLOW_VARIANT) \ - -o $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json 2>&1 \ - | tee $(REPORTS_DIR)/gen-metrics-$(FLOW_VARIANT)-check.log - @$(UTILS_DIR)/checkMetadata.py \ - -m $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json \ - -r $(dir $(DESIGN_CONFIG))rules-$(FLOW_VARIANT).json 2>&1 \ - | tee $(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log +metadata: finish metadata-generate metadata-check + +.PHONY: metadata-generate +metadata-generate: + mkdir -p $(REPORTS_DIR) + echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + -p $(PLATFORM) \ + -v $(FLOW_VARIANT) \ + --logs $(LOG_DIR) \ + --reports $(REPORTS_DIR) \ + --results $(RESULTS_DIR) \ + -o $(REPORTS_DIR)/metadata.json 2>&1 \ + | tee $(abspath $(REPORTS_DIR)/metadata-generate.log) + +export RULES_JSON ?= $(DESIGN_DIR)/rules-$(FLOW_VARIANT).json + +.PHONY: metadata-check +metadata-check: + $(PYTHON_EXE) $(UTILS_DIR)/checkMetadata.py \ + -m $(REPORTS_DIR)/metadata.json \ + -r $(RULES_JSON) 2>&1 \ + | tee $(abspath $(REPORTS_DIR)/metadata-check.log) .PHONY: clean_metadata clean_metadata: - rm -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log - rm -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json + rm -f $(REPORTS_DIR)/design-dir.txt + rm -f $(REPORTS_DIR)/metadata*.* .PHONY: update_ok -update_ok: update_metadata update_rules +update_ok: update_rules .PHONY: update_metadata update_metadata: - cp -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json \ + cp -f $(REPORTS_DIR)/metadata.json \ $(DESIGN_DIR)/metadata-$(FLOW_VARIANT)-ok.json +.PHONY: do-update_rules +do-update_rules: + mkdir -p $(REPORTS_DIR) + $(PYTHON_EXE) $(UTILS_DIR)/genRuleFile.py \ + --rules $(RULES_JSON) \ + --new-rules $(REPORTS_DIR)/rules.json \ + --reference $(REPORTS_DIR)/metadata.json \ + --variant $(FLOW_VARIANT) \ + --failing \ + --tighten + +.PHONY: do-copy_update_rules +do-copy_update_rules: + cp -f $(REPORTS_DIR)/rules.json \ + $(RULES_JSON) + .PHONY: update_rules -update_rules: - $(UTILS_DIR)/genRuleFile.py $(DESIGN_DIR) --variant $(FLOW_VARIANT) --failing --tighten +update_rules: do-update_rules do-copy_update_rules + +.PHONY: do-update_rules_force +do-update_rules_force: + mkdir -p $(REPORTS_DIR) + $(UTILS_DIR)/genRuleFile.py \ + --rules $(RULES_JSON) \ + --new-rules $(REPORTS_DIR)/rules.json \ + --reference $(REPORTS_DIR)/metadata.json \ + --variant $(FLOW_VARIANT) \ + --update .PHONY: update_rules_force -update_rules_force: - $(UTILS_DIR)/genRuleFile.py $(DESIGN_DIR) --variant $(FLOW_VARIANT) --update +update_rules_force: do-update_rules_force + cp -f $(REPORTS_DIR)/rules.json \ + $(RULES_JSON) .PHONY: update_metadata_autotuner update_metadata_autotuner: - @$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ - -p $(PLATFORM) \ - -v $(FLOW_VARIANT) \ - -o $(DESIGN_DIR)/metadata-$(FLOW_VARIANT)-at.json -x + $(PYTHON_EXE) $(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \ + -p $(PLATFORM) \ + -v $(FLOW_VARIANT) \ + --logs $(LOG_DIR) \ + --reports $(REPORTS_DIR) \ + --results $(RESULTS_DIR) \ + -o $(DESIGN_DIR)/metadata-$(FLOW_VARIANT)-at.json -x #------------------------------------------------------------------------------- @@ -52,7 +93,7 @@ $(RESULTS_DIR)/6_net_rc.csv: .PHONY: correlate_rc correlate_rc: $(RESULTS_DIR)/6_net_rc.csv - $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $(RESULTS_DIR)/6_net_rc.csv # TODO Make always wants to redo designs with this rule, regardless of which variations are tried. # $(MAKE) DESIGN_CONFIG=$$config write_net_rc; \ @@ -63,7 +104,7 @@ correlate_platform_rc: design=$$(basename $$(dirname $$config)); \ make DESIGN_CONFIG=./$$config results/$(PLATFORM)/$$design/base/6_net_rc.csv; \ done - $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) + $(PYTHON_EXE) $(UTILS_DIR)/correlateRC.py $$(find results/$(PLATFORM)/*/base -name 6_net_rc.csv) # Run test using gnu parallel #------------------------------------------------------------------------------- @@ -92,15 +133,6 @@ define \n endef -define get_variables -$(foreach V, $(.VARIABLES),$(if $(filter-out $(1), $(origin $V)), $(if $(filter-out .% %QT_QPA_PLATFORM% %TIME_CMD% KLAYOUT% GENERATE_ABSTRACT_RULE% do-step% do-copy% OPEN_GUI% OPEN_GUI_SHORTCUT% SUB_MAKE% UNSET_VARS%, $(V)), $V$ ))) -endef - -export UNSET_VARIABLES_NAMES := $(call get_variables,command% line environment% default automatic) -export ISSUE_VARIABLES_NAMES := $(sort $(filter-out \n get_variables, $(call get_variables,environment% default automatic))) -export ISSUE_VARIABLES := $(foreach V, $(ISSUE_VARIABLES_NAMES), $(if $($V),$V=$($V),$V='')${\n}) -export COMMAND_LINE_ARGS := $(foreach V,$(.VARIABLES),$(if $(filter command% line, $(origin $V)),$(V))) - $(foreach script,$(ISSUE_SCRIPTS),$(script)_issue): %_issue : versions.txt $(UTILS_DIR)/makeIssue.sh $* @@ -160,10 +192,3 @@ endif .PHONY: update_sdc_clocks update_sdc_clocks: $(RESULTS_DIR)/route.guide cp $(RESULTS_DIR)/updated_clks.sdc $(SDC_FILE) - -# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file -ifeq ($(origin ABC_CLOCK_PERIOD_IN_PS), undefined) - ifneq ($(wildcard $(SDC_FILE)),) - export ABC_CLOCK_PERIOD_IN_PS := $(shell sed -nE "s/^set\s+clk_period\s+(\S+).*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1}') - endif -endif diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl index 5b028f9417..9f6b5d2b49 100644 --- a/flow/util/write_net_rc.tcl +++ b/flow/util/write_net_rc.tcl @@ -37,25 +37,65 @@ proc write_rc_csv { filename } { upvar 1 grt rc_var2 upvar 1 rcx rc_var3 - set max_layer_name $::env(MAX_ROUTING_LAYER) - set max_layer [[[ord::get_db_tech] findLayer $max_layer_name] getRoutingLevel] - set min_layer_name $::env(MIN_ROUTING_LAYER) - set min_layer [[[ord::get_db_tech] findLayer $min_layer_name] getRoutingLevel] + set tech [ord::get_db_tech] set stream [open $filename "w"] + + puts -nonewline $stream "# stack:" + foreach layer [[ord::get_db_tech] getLayers] { + set routing [expr [$layer getRoutingLevel] != 0] + set is_routing([$layer getNumber]) $routing + set is_routing([$layer getNumber]) $routing + puts -nonewline $stream " [$layer getName]" + if { $routing } { + puts -nonewline $stream "(routing)" + } else { + # insert via resistance information + set via_resist [$layer getResistance] + if { $via_resist != 0.0 } { + puts -nonewline $stream "([format %.4e $via_resist])" + } + } + } + puts $stream "" + + set use_drt_data [env_var_exists_and_non_empty CORRELATE_DRT_WIRELENGTH] + foreach net [get_nets *] { - set net_name [get_full_name $net] - lassign $rc_var1($net_name) wire_res1 wire_cap1 - lassign $rc_var2($net_name) wire_res2 wire_cap2 - lassign $rc_var3($net_name) wire_res3 wire_cap3 - puts -nonewline $stream "[get_full_name $net],[format %.3e $wire_res1],[format %.3e $wire_cap1],[format %.3e $wire_res2],[format %.3e $wire_cap2],[format %.3e $wire_res3],[format %.3e $wire_cap3]" set db_net [sta::sta_to_db_net $net] - set layer_lengths [grt::route_layer_lengths $db_net] - for {set layer $min_layer} {$layer <= $max_layer} {incr layer} { - set layer_name [[[ord::get_db_tech] findRoutingLayer $layer] getName] - set length [lindex $layer_lengths $layer] - puts -nonewline $stream ",$layer_name,[ord::dbu_to_microns $length]" + set type [$db_net getSigType] + if { + ([string equal $type "CLOCK"] || [string equal $type "SIGNAL"]) && + (!$use_drt_data || [$db_net getWire] ne "NULL") + } { + set net_name [get_full_name $net] + lassign $rc_var1($net_name) wire_res1 wire_cap1 + lassign $rc_var2($net_name) wire_res2 wire_cap2 + lassign $rc_var3($net_name) wire_res3 wire_cap3 + set net_type [expr { [string equal $type "CLOCK"] ? "clock" : "signal" }] + puts -nonewline $stream "[get_full_name $net],$net_type," + puts -nonewline $stream [concat \ + [format "%.3e" $wire_res1] "," [format "%.3e" $wire_cap1] "," \ + [format "%.3e" $wire_res2] "," [format "%.3e" $wire_cap2] "," \ + [format "%.3e" $wire_res3] "," [format "%.3e" $wire_cap3]] + set db_net [sta::sta_to_db_net $net] + + if { $use_drt_data } { + set layer_lengths [drt::route_layer_lengths [$db_net getWire]] + } else { + set layer_lengths [grt::route_layer_lengths $db_net] + } + + for { set layer 0 } { $layer < [$tech getLayerCount] } { incr layer } { + set length [lindex $layer_lengths $layer] + if { $is_routing($layer) } { + puts -nonewline $stream ",[ord::dbu_to_microns $length]" + } else { + puts -nonewline $stream ",$length" + } + } + + puts $stream "" } - puts $stream "" } close $stream } @@ -73,19 +113,7 @@ proc record_wire_rc { var_name } { # Only works or makes sense for 2 pin nets. proc net_wire_res { net } { - set pins [get_pins -of_object $net] - if { [llength $pins] == 2 } { - lassign $pins pin1 pin2 - if { [$pin1 is_driver] } { - set drvr $pin1 - } else { - set drvr $pin2 - } - lassign [sta::find_pi_elmore $drvr rise max] c2 rpi c1 - return $rpi - } else { - return 0.0 - } + return [rsz::sum_parasitic_network_resist $net] } proc net_wire_cap { net } { @@ -118,7 +146,8 @@ proc compare_wire_rc { count var_name ref_var_name } { # implicit arg to net_var_cap_less set var_cap_less_name $ref_var_name set nets [lsort -command net_var_cap_less [get_nets *]] - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total [format %5s $var_name] [format %5s $ref_var_name]" + puts "net fanout [format %4s $var_name] [format %5s $ref_var_name] \ + wire total [format %5s $var_name] [format %5s $ref_var_name]" puts " cap cap delta delta res res delta" set res_sum 0.0 set res_count 0 @@ -139,8 +168,11 @@ proc compare_wire_rc { count var_name ref_var_name } { set res_avg [expr $res_sum / $count] set cap_avg [expr $cap_sum / $count] set total_cap_avg [expr $total_cap_sum / $count] - puts " ----- ----- -----" - puts " [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]% [format %+4.0f $res_avg]%" + puts " \ + ----- ----- -----" + puts " \ + [format %+4.0f $cap_avg]% [format %+4.0f $total_cap_avg]%\ + [format %+4.0f $res_avg]%" } proc compare_net_wire_rc { net_name var_name ref_var_name } { @@ -148,7 +180,8 @@ proc compare_net_wire_rc { net_name var_name ref_var_name } { upvar 1 $ref_var_name ref_var global var_cap_less_name - puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] wire total" + puts "net fanout [format %5s $var_name] [format %5s $ref_var_name] \ + wire total" puts " cap cap delta delta" compare_wire_rc1 [get_net $net_name] $var_name $ref_var_name } @@ -175,7 +208,7 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set cap_delta 0.0 } - + set total_cap [expr $pin_cap + $wire_cap] set total_cap_ref [expr $pin_cap + $wire_cap_ref] if { $total_cap_ref != 0.0 } { @@ -183,12 +216,21 @@ proc compare_wire_rc1 { net var_name ref_var_name } { } else { set total_delta 0.0 } - + set fanout [llength [get_pins -of $net -filter "direction == input"]] - puts -nonewline "[format %-20s $net_name] [format %5d $fanout] [format %8s [sta::format_capacitance $wire_cap 3]] [format %8s [sta::format_capacitance $wire_cap_ref 3]] [format %4.0f $cap_delta]% [format %4.0f $total_delta]%" + puts -nonewline [concat \ + [format "%-20s" $net_name] " " \ + [format "%5d" $fanout] " " \ + [format "%8s" [sta::format_capacitance $wire_cap 3]] " " \ + [format "%8s" [sta::format_capacitance $wire_cap_ref 3]] " " \ + [format "%4.0f" $cap_delta]% " " \ + [format "%4.0f" $total_delta]%] if { $res > 0.0 } { - puts "[format %8s [sta::format_resistance $res 3]] [format %8s [sta::format_resistance $res_ref 3]] [format %4.0f $res_delta]%" + puts [concat \ + [format "%8s" [sta::format_resistance $res 3]] " " \ + [format "%8s" [sta::format_resistance $res_ref 3]] " " \ + [format "%4.0f" $res_delta]%] } else { puts "" } @@ -207,8 +249,12 @@ proc write_layer_rc_cmds { adjustment } { set cap_edge [$layer getEdgeCapacitance] set cap_area [$layer getCapacitance] # Convert pF/um to F/um. - set cap [expr ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] - puts "set_layer_rc -layer [$layer getConstName] -resistance [format %.4e [sta::resistance_sta_ui $res]] -capacitance [format %.4e [sta::capacitance_sta_ui $cap]]" + set cap [expr \ + ($cap_edge * 2.0 + $wire_width * $cap_area) * 1e-12 / (1.0 + $adjustment / 100.0)] + puts [concat \ + "set_layer_rc -layer [$layer getConstName] " \ + "-resistance [format %.4e [sta::resistance_sta_ui $res]] " \ + "-capacitance [format %.4e [sta::capacitance_sta_ui $cap]]"] } } } diff --git a/flow/util/write_net_rc_script.tcl b/flow/util/write_net_rc_script.tcl index afda93c270..a2815ce5a6 100644 --- a/flow/util/write_net_rc_script.tcl +++ b/flow/util/write_net_rc_script.tcl @@ -1,26 +1,15 @@ source $::env(SCRIPTS_DIR)/load.tcl -# Note 6_final.def has wires that prevent global routing. -load_design 4_1_cts.odb 4_cts.sdc +load_design 6_final.odb 6_final.sdc source $::env(UTILS_DIR)/write_net_rc.tcl estimate_parasitics -placement record_wire_rc gpl -if {[env_var_exists_and_non_empty FASTROUTE_TCL]} { - source $env(FASTROUTE_TCL) -} else { - set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) 0.5 - set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER) - set_macro_extension 2 -} - -global_route -congestion_iterations 100 - estimate_parasitics -global_routing record_wire_rc grt -read_spef -quiet -reduce_to pi_elmore $::env(RESULTS_DIR)/6_final.spef +read_spef $::env(RESULTS_DIR)/6_final.spef record_wire_rc rcx #compare_wire_rc 50 grt rcx diff --git a/jenkins/public_nightly.Jenkinsfile b/jenkins/public_nightly.Jenkinsfile index 1c8d6b7c5f..75fbdcfbeb 100644 --- a/jenkins/public_nightly.Jenkinsfile +++ b/jenkins/public_nightly.Jenkinsfile @@ -1,4 +1,4 @@ -@Library('utils@orfs-v2.2.2') _ +@Library('utils@orfs-v2.3.5') _ node { @@ -64,6 +64,8 @@ node { } stage ('Cleanup and Reporting') { + env.CHANGE_BRANCH = 'nightly' + env.BRANCH_NAME = 'nightly' finalReport(DOCKER_IMAGE); } diff --git a/jenkins/public_tests_all.Jenkinsfile b/jenkins/public_tests_all.Jenkinsfile index 87a00ac565..1239a279e3 100644 --- a/jenkins/public_tests_all.Jenkinsfile +++ b/jenkins/public_tests_all.Jenkinsfile @@ -1,8 +1,22 @@ -@Library('utils@orfs-v2.2.2') _ +@Library('utils@orfs-v2.3.5') _ node { + + def isDefaultBranch = (env.BRANCH_NAME == 'master') + def daysToKeep = '20'; + def numToKeep = (isDefaultBranch ? '-1' : '10'); - properties([copyArtifactPermission('${JOB_NAME},'+env.BRANCH_NAME)]); + properties([ + copyArtifactPermission('${JOB_NAME},'+env.BRANCH_NAME), + + buildDiscarder(logRotator( + daysToKeepStr: daysToKeep, + artifactDaysToKeepStr: daysToKeep, + + numToKeepStr: numToKeep, + artifactNumToKeepStr: numToKeep + )) + ]); stage('Checkout') { if (env.BRANCH_NAME && env.BRANCH_NAME == 'master') { diff --git a/setup.sh b/setup.sh index 3063856d07..22a84cfea8 100755 --- a/setup.sh +++ b/setup.sh @@ -27,7 +27,4 @@ elif grep -q "^+" "$tmpfile"; then fi "$DIR/etc/DependencyInstaller.sh" -base -"$DIR/tools/OpenROAD/etc/DependencyInstaller.sh" -base - sudo -u $SUDO_USER "$DIR/etc/DependencyInstaller.sh" -common -prefix="$DIR/dependencies" -sudo -u $SUDO_USER "$DIR/tools/OpenROAD/etc/DependencyInstaller.sh" -common -prefix="$DIR/dependencies" diff --git a/tclint.toml b/tclint.toml new file mode 100644 index 0000000000..4a98b01c7c --- /dev/null +++ b/tclint.toml @@ -0,0 +1,21 @@ +# hardcoded list of paths to exclude while we incrementally lint codebase +# See issue #3268 for tracking +exclude = [ + "flow/results", + "flow/logs", + "flow/designs/asap7/cva6/constraint.sdc", + "tools/OpenROAD", + "tools/yosys", + "tools/yosys-slang", +] + +ignore = [ + "unbraced-expr", +] + +[style] +indent = 2 +line-length = 100 +allow-aligned-sets = true +indent-namespace-eval = false +spaces-in-braces = true \ No newline at end of file diff --git a/tools/AutoTuner/RAY_README.md b/tools/AutoTuner/RAY_README.md deleted file mode 100644 index 8c9fd33ad0..0000000000 --- a/tools/AutoTuner/RAY_README.md +++ /dev/null @@ -1,246 +0,0 @@ -# AutoTuner with Ray cluster at GCP - -This documentation shows how to create a Ray cluster on Google Cloud -Kubernetes Engine (i.e., GKE) and the required support infrastructure to -enable AutoTuner to work properly. The documentation is intended to users -with some familiarity with Google Cloud or other cloud services. For -more details on how to use AutoTuner see the main documentation page -[here](https://openroad-flow-scripts.readthedocs.io/en/latest/user/InstructionsForAutoTuner.html). - -## How to use this document - -If you want to create a new cluster, follow the document from begin to end. - -If you want to run experiments on an existing cluster, make sure you have -all the [Prerequisites](#prerequisites) and then you can jump to [Running -Ray programs with Ray Client](#running-ray-programs-with-ray-client). - -## Prerequisites - -- Google Cloud CLI installed, see instructions [here](https://cloud.google.com/sdk/docs/install). -- Access to an existing Google Cloud project with "Editor" permissions to - create the cluster. To use an existing cluster contact the person who - created the cluster. -- `kubectl` installed and available on your PATH. See instructions bellow. - - -Configure `gcloud` to use the Kubernetes credentials of the newly created -cluster. The credentials allow the use of `kubectl` locally. - -```bash -gcloud components install kubectl -``` - -## Enable GKE - -Follow the Google quickstart guide up to the section "Create a GKE cluster" -[here](https://cloud.google.com/kubernetes-engine/docs/quickstart). The -quickstart guide instructs how to enable GKE (Google's Kubernetes Engine) -start a CLI interface and get the settings for your project. - -## Create a Kubernetes cluster - -Create a GKE cluster using the following `gcloud` command as a guide. Note -that each argument defines a characteristic of the cluster. Furthermore, -the cluster and node pool allocate resources that cost money. Hence, be -mindful when choosing the configuration. For additional information see: - -```bash -gcloud beta container clusters create --help -gcloud beta container node-pools create --help -``` - -```bash -gcloud beta container clusters create "autotuner" \ - --machine-type "e2-standard-8" \ - --image-type "UBUNTU_CONTAINERD" \ - --disk-type "pd-standard" \ - --disk-size "100" \ - --num-nodes "1" \ - --enable-autoscaling \ - --min-nodes "1" \ - --max-nodes "10" -``` - -Configure `gcloud` to use the Kubernetes credentials of the newly created -cluster. The credentials allow the use of `kubectl` locally. - -```bash -gcloud container clusters get-credentials autotuner -``` - -Create a new node pool. This step is optional, however, recommended. The -new pool uses preemptive nodes which are not only cheaper, but also have -a more powerful CPU and have more disk space. - -```bash -gcloud beta container node-pools create "worker-pool" \ - --cluster "autotuner" \ - --machine-type "c2-standard-60" \ - --image-type "UBUNTU_CONTAINERD" \ - --disk-type "pd-standard" \ - --disk-size "2000" \ - --preemptible \ - --num-nodes "3" \ - --enable-autoscaling \ - --min-nodes "1" \ - --max-nodes "625" -``` - -## Create NFS and setup mount options - -NOTE: This tutorial requires a working NFS server. - -To access the NFS mount point in the Ray cluster, we use a NFS helm -chart. You need to modify the helm chart with the information about your -server IP and mount point path. - -### Install NFS Kubernetes provisioner - -```bash -helm repo add nfs-subdir-external-provisioner https://kubernetes-sigs.github.io/nfs-subdir-external-provisioner -helm repo update -``` - -Before installing the helm chart, double check the fields marked with -`TODO` on the file `./nfs/nfs-helm-values.yaml`. The `server` and `path` -need to match the NFS server IP and the path to the exposed folder. -The `nodeSelector` must match the non-preemptive Kubernetes pool. - -```bash -helm install nfs nfs-subdir-external-provisioner/nfs-subdir-external-provisioner -f nfs/nfs-helm-values.yaml -``` - -### Create a PVC - -Create the PVC: - -```bash -kubectl create -f nfs/nfs-pvc.yaml -``` - -## Ray cluster - -The two main files for the helm chart are: - -```bash -helm-chart/templates/raycluster.yaml -helm-chart/values.yaml -``` - -You can restrict the node pool your AutoTuner jobs will use. To create -this policy, replace POOL_NAME with the name of the pool you created on -the previous step. For this tutorial we use `worker-pool`. - -```yaml -nodeSelector: - cloud.google.com/gke-nodepool: POOL_NAME -``` - -### Deploy Ray cluster inside Kubernetes - -Use Helm to deploy a Ray cluster. - -```bash -helm install autotuner ./helm-chart -``` - -### Upgrade deployment - -After the initial deployment, if you change the values inside `./helm-chart` -you need to upgrade the configuration stored at the Kubernetes cluster. - -```bash -helm upgrade autotuner ./helm-chart -``` - -### Useful ways to observe - -Ray dashboard: - -```bash -kubectl port-forward service/autotuner-ray-head 8265 -``` - -Overall cluster status: - -```bash -kubectl get nodes,rayclusters,pods,services,replicaset,pvc,pv -``` - -Ray auto-scaler logs: - -```bash -kubectl logs \ - $(kubectl get pod -l cluster.ray.io/component=operator -o custom-columns=:metadata.name) \ - --tail=100 -f -``` - -### Remove - -First, delete the `RayCluster` custom resource. - -```bash -kubectl delete raycluster autotuner -``` - -Delete the Ray release. - -```bash -helm uninstall autotuner -``` - -## Running Ray programs with Ray Client - -Currently there are three different ways to launch a job on the GKE cluster. -All three methods depend on having `kubectl` installed and correctly setup. - -To configure `gcloud` to use the Kubernetes credentials of a existing cluster. - -```bash -gcloud components install kubectl -gcloud container clusters get-credentials autotuner -``` - -### Using port forwarding - -NOTE: Ray requires that the version of Python on the server and locally -match. The current `openroad/ray` image has Python 3.7.7, make sure your -local machine has at least Python 3.7.x before continuing. - -```bash -pip3 install -U --user 'ray[default,tune]==1.11.0' ax-platform hyperopt nevergrad optuna pandas -pip3 install -U --user colorama==0.4.4 bayesian-optimization==1.4.0 -``` - -Start the port forwarding: - -```bash -kubectl port-forward service/autotuner-ray-head 10001 -``` - -Run the test script locally: - -```bash -python3 kubernetes/run.py -``` - -### Connecting to head node - -Instead of depending on your local environment, you can connect to the head -node of the Ray cluster and run the scripts from there. - -```bash -kubectl exec -it $(kubectl get pod -l cluster.ray.io/component=autotuner-ray-head -o custom-columns=:metadata.name) -- bash -wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/master/tools/AutoTuner/kubernetes/run.py -python run.py -``` - -### Using Kubernetes job submit - -Finally, if you do not wish to keep a terminal session open, you can submit -a Kubernetes job. - -```bash -kubectl create -f kubernetes/submit.yaml -``` diff --git a/tools/AutoTuner/helm-chart/.helmignore b/tools/AutoTuner/helm-chart/.helmignore deleted file mode 100644 index 0e8a0eb36f..0000000000 --- a/tools/AutoTuner/helm-chart/.helmignore +++ /dev/null @@ -1,23 +0,0 @@ -# Patterns to ignore when building packages. -# This supports shell glob matching, relative path matching, and -# negation (prefixed with !). Only one pattern per line. -.DS_Store -# Common VCS dirs -.git/ -.gitignore -.bzr/ -.bzrignore -.hg/ -.hgignore -.svn/ -# Common backup files -*.swp -*.bak -*.tmp -*.orig -*~ -# Various IDEs -.project -.idea/ -*.tmproj -.vscode/ diff --git a/tools/AutoTuner/helm-chart/Chart.yaml b/tools/AutoTuner/helm-chart/Chart.yaml deleted file mode 100644 index b2148b1ace..0000000000 --- a/tools/AutoTuner/helm-chart/Chart.yaml +++ /dev/null @@ -1,10 +0,0 @@ -apiVersion: v2 -name: ray -description: A Helm chart for deployments of Ray on Kubernetes. -type: application - -# Chart version. -version: 0.1.0 - -# Ray version. -appVersion: "latest" diff --git a/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml b/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml deleted file mode 100644 index 6db9d73a97..0000000000 --- a/tools/AutoTuner/helm-chart/crds/cluster_crd.yaml +++ /dev/null @@ -1,4321 +0,0 @@ -apiVersion: apiextensions.k8s.io/v1 -kind: CustomResourceDefinition -metadata: - name: rayclusters.cluster.ray.io -spec: - group: cluster.ray.io - scope: Namespaced - names: - plural: rayclusters - singular: raycluster - kind: RayCluster - versions: - - name: v1 - served: true - storage: true - subresources: - status: {} - additionalPrinterColumns: - - name: status - type: string - description: Updating, Running, Error, or AutoscalingExceptionRecovery - jsonPath: .status.phase - - name: restarts - type: integer - description: Number of Ray cluster restarts triggered by autoscaler failure. - jsonPath: .status.autoscalerRetries - - name: age - type: date - jsonPath: .metadata.creationTimestamp - schema: - openAPIV3Schema: - description: Ray cluster configuration - type: object - required: - - spec - properties: - status: - type: object - x-kubernetes-preserve-unknown-fields: true - properties: - phase: - description: Updating, Running, Error, or AutoscalingExceptionRecovery - type: string - autoscalerRetries: - description: Number of Ray cluster restarts triggered by autoscaler failure. - type: integer - spec: - type: object - required: - - podTypes - - headPodType - properties: - maxWorkers: - description: The maximum number of workers nodes to launch in addition to the - head node. - type: integer - minimum: 0 - upscalingSpeed: - description: The autoscaler will scale up the cluster faster with higher upscaling - speed. E.g., if the task requires adding more nodes then autoscaler will gradually - scale up the cluster in chunks of upscalingSpeed*currentlyRunningNodes. This - number should be > 0. - type: number - minimum: 0 - idleTimeoutMinutes: - description: If a node is idle for this many minutes, it will be removed. - type: integer - minimum: 0 - headServicePorts: - description: Optional list of ports to use for the Ray head service. - type: array - items: - type: object - required: - - name - - port - - targetPort - properties: - name: - type: string - port: - type: integer - targetPort: - x-kubernetes-int-or-string: true - podTypes: - description: A list of Pod types on which to run Ray nodes, for multi-node-type autoscaling. - type: array - items: - type: object - required: - - name - - podConfig - properties: - name: - type: string - description: Name of the Pod type. - minWorkers: - type: integer - description: Minimum number of Ray workers of this Pod type. - maxWorkers: - type: integer - description: Maximum number of Ray workers of this Pod type. - rayResources: - type: object - description: User-specified custom resources for use by Ray. Keys strings, values integers. - # TODO (dmitri): Validate that values are integers [patternProperties not supported by OpenAPI v3.0] - x-kubernetes-preserve-unknown-fields: true - setupCommands: - description: Alias for workerSetupCommands - type: array - items: - type: string - description: shell command - workerSetupCommands: - description: Commands to run before starting the Ray runtime for workers of this podType. - type: array - items: - type: string - description: shell command - podConfig: - type: object - description: Pod configuration. - x-kubernetes-embedded-resource: true - properties: - spec: - description: PodSpec is a description of a pod. - properties: - activeDeadlineSeconds: - description: Optional duration in seconds the pod may be active - on the node relative to StartTime before the system will actively - try to mark it failed and kill associated containers. Value - must be a positive integer. - format: int64 - type: integer - affinity: - description: If specified, the pod's scheduling constraints - properties: - nodeAffinity: - description: Describes node affinity scheduling rules for - the pod. - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the affinity expressions specified - by this field, but it may choose a node that violates - one or more of the expressions. The node that is most - preferred is the one with the greatest sum of weights, - i.e. for each node that meets all of the scheduling - requirements (resource request, requiredDuringScheduling - affinity expressions, etc.), compute a sum by iterating - through the elements of this field and adding "weight" - to the sum if the node matches the corresponding matchExpressions; - the node(s) with the highest sum are the most preferred. - items: - description: An empty preferred scheduling term matches - all objects with implicit weight 0 (i.e. it's a - no-op). A null preferred scheduling term matches - no objects (i.e. is also a no-op). - properties: - preference: - description: A node selector term, associated - with the corresponding weight. - properties: - matchExpressions: - description: A list of node selector requirements - by node's labels. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchFields: - description: A list of node selector requirements - by node's fields. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - type: object - weight: - description: Weight associated with matching the - corresponding nodeSelectorTerm, in the range - 1-100. - format: int32 - type: integer - required: - - preference - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to an - update), the system may or may not try to eventually - evict the pod from its node. - properties: - nodeSelectorTerms: - description: Required. A list of node selector terms. - The terms are ORed. - items: - description: A null or empty node selector term - matches no objects. The requirements of them - are ANDed. The TopologySelectorTerm type implements - a subset of the NodeSelectorTerm. - properties: - matchExpressions: - description: A list of node selector requirements - by node's labels. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchFields: - description: A list of node selector requirements - by node's fields. - items: - description: A node selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: The label key that the - selector applies to. - type: string - operator: - description: Represents a key's relationship - to a set of values. Valid operators - are In, NotIn, Exists, DoesNotExist. - Gt, and Lt. - type: string - values: - description: An array of string values. - If the operator is In or NotIn, the - values array must be non-empty. If - the operator is Exists or DoesNotExist, - the values array must be empty. If - the operator is Gt or Lt, the values - array must have a single element, - which will be interpreted as an integer. - This array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - type: object - type: array - required: - - nodeSelectorTerms - type: object - type: object - podAffinity: - description: Describes pod affinity scheduling rules (e.g. - co-locate this pod in the same node, zone, etc. as some - other pod(s)). - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the affinity expressions specified - by this field, but it may choose a node that violates - one or more of the expressions. The node that is most - preferred is the one with the greatest sum of weights, - i.e. for each node that meets all of the scheduling - requirements (resource request, requiredDuringScheduling - affinity expressions, etc.), compute a sum by iterating - through the elements of this field and adding "weight" - to the sum if the node has pods which matches the - corresponding podAffinityTerm; the node(s) with the - highest sum are the most preferred. - items: - description: The weights of all of the matched WeightedPodAffinityTerm - fields are added per-node to find the most preferred - node(s) - properties: - podAffinityTerm: - description: Required. A pod affinity term, associated - with the corresponding weight. - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list - of label selector requirements. The - requirements are ANDed. - items: - description: A label selector requirement - is a selector that contains values, - a key, and an operator that relates - the key and values. - properties: - key: - description: key is the label key - that the selector applies to. - type: string - operator: - description: operator represents - a key's relationship to a set - of values. Valid operators are - In, NotIn, Exists and DoesNotExist. - type: string - values: - description: values is an array - of string values. If the operator - is In or NotIn, the values array - must be non-empty. If the operator - is Exists or DoesNotExist, the - values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator - is "In", and the values array contains - only "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located - (affinity) or not co-located (anti-affinity) - with the pods matching the labelSelector - in the specified namespaces, where co-located - is defined as running on a node whose value - of the label with key topologyKey matches - that of any node on which any of the selected - pods is running. Empty topologyKey is not - allowed. - type: string - required: - - topologyKey - type: object - weight: - description: weight associated with matching the - corresponding podAffinityTerm, in the range - 1-100. - format: int32 - type: integer - required: - - podAffinityTerm - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to a - pod label update), the system may or may not try to - eventually evict the pod from its node. When there - are multiple elements, the lists of nodes corresponding - to each podAffinityTerm are intersected, i.e. all - terms must be satisfied. - items: - description: Defines a set of pods (namely those matching - the labelSelector relative to the given namespace(s)) - that this pod should be co-located (affinity) or - not co-located (anti-affinity) with, where co-located - is defined as running on a node whose value of the - label with key matches that of any - node on which a pod of the set of pods is running - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list of - label selector requirements. The requirements - are ANDed. - items: - description: A label selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: key is the label key that - the selector applies to. - type: string - operator: - description: operator represents a key's - relationship to a set of values. Valid - operators are In, NotIn, Exists and - DoesNotExist. - type: string - values: - description: values is an array of string - values. If the operator is In or NotIn, - the values array must be non-empty. - If the operator is Exists or DoesNotExist, - the values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator is - "In", and the values array contains only - "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located (affinity) - or not co-located (anti-affinity) with the pods - matching the labelSelector in the specified - namespaces, where co-located is defined as running - on a node whose value of the label with key - topologyKey matches that of any node on which - any of the selected pods is running. Empty topologyKey - is not allowed. - type: string - required: - - topologyKey - type: object - type: array - type: object - podAntiAffinity: - description: Describes pod anti-affinity scheduling rules - (e.g. avoid putting this pod in the same node, zone, etc. - as some other pod(s)). - properties: - preferredDuringSchedulingIgnoredDuringExecution: - description: The scheduler will prefer to schedule pods - to nodes that satisfy the anti-affinity expressions - specified by this field, but it may choose a node - that violates one or more of the expressions. The - node that is most preferred is the one with the greatest - sum of weights, i.e. for each node that meets all - of the scheduling requirements (resource request, - requiredDuringScheduling anti-affinity expressions, - etc.), compute a sum by iterating through the elements - of this field and adding "weight" to the sum if the - node has pods which matches the corresponding podAffinityTerm; - the node(s) with the highest sum are the most preferred. - items: - description: The weights of all of the matched WeightedPodAffinityTerm - fields are added per-node to find the most preferred - node(s) - properties: - podAffinityTerm: - description: Required. A pod affinity term, associated - with the corresponding weight. - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list - of label selector requirements. The - requirements are ANDed. - items: - description: A label selector requirement - is a selector that contains values, - a key, and an operator that relates - the key and values. - properties: - key: - description: key is the label key - that the selector applies to. - type: string - operator: - description: operator represents - a key's relationship to a set - of values. Valid operators are - In, NotIn, Exists and DoesNotExist. - type: string - values: - description: values is an array - of string values. If the operator - is In or NotIn, the values array - must be non-empty. If the operator - is Exists or DoesNotExist, the - values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator - is "In", and the values array contains - only "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located - (affinity) or not co-located (anti-affinity) - with the pods matching the labelSelector - in the specified namespaces, where co-located - is defined as running on a node whose value - of the label with key topologyKey matches - that of any node on which any of the selected - pods is running. Empty topologyKey is not - allowed. - type: string - required: - - topologyKey - type: object - weight: - description: weight associated with matching the - corresponding podAffinityTerm, in the range - 1-100. - format: int32 - type: integer - required: - - podAffinityTerm - - weight - type: object - type: array - requiredDuringSchedulingIgnoredDuringExecution: - description: If the anti-affinity requirements specified - by this field are not met at scheduling time, the - pod will not be scheduled onto the node. If the anti-affinity - requirements specified by this field cease to be met - at some point during pod execution (e.g. due to a - pod label update), the system may or may not try to - eventually evict the pod from its node. When there - are multiple elements, the lists of nodes corresponding - to each podAffinityTerm are intersected, i.e. all - terms must be satisfied. - items: - description: Defines a set of pods (namely those matching - the labelSelector relative to the given namespace(s)) - that this pod should be co-located (affinity) or - not co-located (anti-affinity) with, where co-located - is defined as running on a node whose value of the - label with key matches that of any - node on which a pod of the set of pods is running - properties: - labelSelector: - description: A label query over a set of resources, - in this case pods. - properties: - matchExpressions: - description: matchExpressions is a list of - label selector requirements. The requirements - are ANDed. - items: - description: A label selector requirement - is a selector that contains values, a - key, and an operator that relates the - key and values. - properties: - key: - description: key is the label key that - the selector applies to. - type: string - operator: - description: operator represents a key's - relationship to a set of values. Valid - operators are In, NotIn, Exists and - DoesNotExist. - type: string - values: - description: values is an array of string - values. If the operator is In or NotIn, - the values array must be non-empty. - If the operator is Exists or DoesNotExist, - the values array must be empty. This - array is replaced during a strategic - merge patch. - items: - type: string - type: array - required: - - key - - operator - type: object - type: array - matchLabels: - additionalProperties: - type: string - description: matchLabels is a map of {key,value} - pairs. A single {key,value} in the matchLabels - map is equivalent to an element of matchExpressions, - whose key field is "key", the operator is - "In", and the values array contains only - "value". The requirements are ANDed. - type: object - type: object - namespaces: - description: namespaces specifies which namespaces - the labelSelector applies to (matches against); - null or empty list means "this pod's namespace" - items: - type: string - type: array - topologyKey: - description: This pod should be co-located (affinity) - or not co-located (anti-affinity) with the pods - matching the labelSelector in the specified - namespaces, where co-located is defined as running - on a node whose value of the label with key - topologyKey matches that of any node on which - any of the selected pods is running. Empty topologyKey - is not allowed. - type: string - required: - - topologyKey - type: object - type: array - type: object - type: object - automountServiceAccountToken: - description: AutomountServiceAccountToken indicates whether - a service account token should be automatically mounted. - type: boolean - containers: - description: List of containers belonging to the pod. Containers - cannot currently be added or removed. There must be at least - one container in a Pod. Cannot be updated. - items: - description: A single application container that you want - to run within a pod. - properties: - args: - description: 'Arguments to the entrypoint. The docker - image''s CMD is used if this is not provided. Variable - references $(VAR_NAME) are expanded using the container''s - environment. If a variable cannot be resolved, the reference - in the input string will be unchanged. The $(VAR_NAME) - syntax can be escaped with a double $$, ie: $$(VAR_NAME). - Escaped references will never be expanded, regardless - of whether the variable exists or not. Cannot be updated. - More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - command: - description: 'Entrypoint array. Not executed within a - shell. The docker image''s ENTRYPOINT is used if this - is not provided. Variable references $(VAR_NAME) are - expanded using the container''s environment. If a variable - cannot be resolved, the reference in the input string - will be unchanged. The $(VAR_NAME) syntax can be escaped - with a double $$, ie: $$(VAR_NAME). Escaped references - will never be expanded, regardless of whether the variable - exists or not. Cannot be updated. More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - env: - description: List of environment variables to set in the - container. Cannot be updated. - items: - description: EnvVar represents an environment variable - present in a Container. - properties: - name: - description: Name of the environment variable. Must - be a C_IDENTIFIER. - type: string - value: - description: 'Variable references $(VAR_NAME) are - expanded using the previous defined environment - variables in the container and any service environment - variables. If a variable cannot be resolved, the - reference in the input string will be unchanged. - The $(VAR_NAME) syntax can be escaped with a double - $$, ie: $$(VAR_NAME). Escaped references will - never be expanded, regardless of whether the variable - exists or not. Defaults to "".' - type: string - valueFrom: - description: Source for the environment variable's - value. Cannot be used if value is not empty. - properties: - configMapKeyRef: - description: Selects a key of a ConfigMap. - properties: - key: - description: The key to select. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's key must be defined - type: boolean - required: - - key - type: object - fieldRef: - description: 'Selects a field of the pod: supports - metadata.name, metadata.namespace, metadata.labels, - metadata.annotations, spec.nodeName, spec.serviceAccountName, - status.hostIP, status.podIP.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, limits.ephemeral-storage, requests.cpu, - requests.memory and requests.ephemeral-storage) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - secretKeyRef: - description: Selects a key of a secret in the - pod's namespace - properties: - key: - description: The key of the secret to select - from. Must be a valid secret key. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or it's key must be defined - type: boolean - required: - - key - type: object - type: object - required: - - name - type: object - type: array - envFrom: - description: List of sources to populate environment variables - in the container. The keys defined within a source must - be a C_IDENTIFIER. All invalid keys will be reported - as an event when the container is starting. When a key - exists in multiple sources, the value associated with - the last source will take precedence. Values defined - by an Env with a duplicate key will take precedence. - Cannot be updated. - items: - description: EnvFromSource represents the source of - a set of ConfigMaps - properties: - configMapRef: - description: The ConfigMap to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap must - be defined - type: boolean - type: object - prefix: - description: An optional identifier to prepend to - each key in the ConfigMap. Must be a C_IDENTIFIER. - type: string - secretRef: - description: The Secret to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret must - be defined - type: boolean - type: object - type: object - type: array - image: - description: 'Docker image name. More info: https://kubernetes.io/docs/concepts/containers/images - This field is optional to allow higher level config - management to default or override container images in - workload controllers like Deployments and StatefulSets.' - type: string - imagePullPolicy: - description: 'Image pull policy. One of Always, Never, - IfNotPresent. Defaults to Always if :latest tag is specified, - or IfNotPresent otherwise. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/containers/images#updating-images' - type: string - lifecycle: - description: Actions that the management system should - take in response to container lifecycle events. Cannot - be updated. - properties: - postStart: - description: 'PostStart is called immediately after - a container is created. If the handler fails, the - container is terminated and restarted according - to its restart policy. Other management of the container - blocks until the hook completes. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - preStop: - description: 'PreStop is called immediately before - a container is terminated due to an API request - or management event such as liveness probe failure, - preemption, resource contention, etc. The handler - is not called if the container crashes or exits. - The reason for termination is passed to the handler. - The Pod''s termination grace period countdown begins - before the PreStop hooked is executed. Regardless - of the outcome of the handler, the container will - eventually terminate within the Pod''s termination - grace period. Other management of the container - blocks until the hook completes or until the termination - grace period is reached. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - type: object - livenessProbe: - description: 'Periodic probe of container liveness. Container - will be restarted if the probe fails. Cannot be updated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - name: - description: Name of the container specified as a DNS_LABEL. - Each container in a pod must have a unique name (DNS_LABEL). - Cannot be updated. - type: string - ports: - description: List of ports to expose from the container. - Exposing a port here gives the system additional information - about the network connections a container uses, but - is primarily informational. Not specifying a port here - DOES NOT prevent that port from being exposed. Any port - which is listening on the default "0.0.0.0" address - inside a container will be accessible from the network. - Cannot be updated. - items: - description: ContainerPort represents a network port - in a single container. - properties: - containerPort: - description: Number of port to expose on the pod's - IP address. This must be a valid port number, - 0 < x < 65536. - format: int32 - type: integer - hostIP: - description: What host IP to bind the external port - to. - type: string - hostPort: - description: Number of port to expose on the host. - If specified, this must be a valid port number, - 0 < x < 65536. If HostNetwork is specified, this - must match ContainerPort. Most containers do not - need this. - format: int32 - type: integer - name: - description: If specified, this must be an IANA_SVC_NAME - and unique within the pod. Each named port in - a pod must have a unique name. Name for the port - that can be referred to by services. - type: string - protocol: - description: Protocol for port. Must be UDP, TCP, - or SCTP. Defaults to "TCP". - type: string - default: TCP - required: - - containerPort - type: object - type: array - x-kubernetes-list-map-keys: - - containerPort - - protocol - x-kubernetes-list-type: map - readinessProbe: - description: 'Periodic probe of container service readiness. - Container will be removed from service endpoints if - the probe fails. Cannot be updated. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - resources: - description: 'Compute Resources required by this container. - Cannot be updated. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - properties: - limits: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Limits describes the maximum amount - of compute resources allowed. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - requests: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Requests describes the minimum amount - of compute resources required. If Requests is omitted - for a container, it defaults to Limits if that is - explicitly specified, otherwise to an implementation-defined - value. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - type: object - securityContext: - description: 'Security options the pod should run with. - More info: https://kubernetes.io/docs/concepts/policy/security-context/ - More info: https://kubernetes.io/docs/tasks/configure-pod-container/security-context/' - properties: - allowPrivilegeEscalation: - description: 'AllowPrivilegeEscalation controls whether - a process can gain more privileges than its parent - process. This bool directly controls if the no_new_privs - flag will be set on the container process. AllowPrivilegeEscalation - is true always when the container is: 1) run as - Privileged 2) has CAP_SYS_ADMIN' - type: boolean - capabilities: - description: The capabilities to add/drop when running - containers. Defaults to the default set of capabilities - granted by the container runtime. - properties: - add: - description: Added capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - drop: - description: Removed capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - type: object - privileged: - description: Run container in privileged mode. Processes - in privileged containers are essentially equivalent - to root on the host. Defaults to false. - type: boolean - procMount: - description: procMount denotes the type of proc mount - to use for the containers. The default is DefaultProcMount - which uses the container runtime defaults for readonly - paths and masked paths. This requires the ProcMountType - feature flag to be enabled. - type: string - readOnlyRootFilesystem: - description: Whether this container has a read-only - root filesystem. Default is false. - type: boolean - runAsGroup: - description: The GID to run the entrypoint of the - container process. Uses runtime default if unset. - May also be set in PodSecurityContext. If set in - both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run - as a non-root user. If true, the Kubelet will validate - the image at runtime to ensure that it does not - run as UID 0 (root) and fail to start the container - if it does. If unset or false, no such validation - will be performed. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the - container process. Defaults to user specified in - image metadata if unspecified. May also be set in - PodSecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to - the container. If unspecified, the container runtime - will allocate a random SELinux context for each - container. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - properties: - level: - description: Level is SELinux level label that - applies to the container. - type: string - role: - description: Role is a SELinux role label that - applies to the container. - type: string - type: - description: Type is a SELinux type label that - applies to the container. - type: string - user: - description: User is a SELinux user label that - applies to the container. - type: string - type: object - type: object - stdin: - description: Whether this container should allocate a - buffer for stdin in the container runtime. If this is - not set, reads from stdin in the container will always - result in EOF. Default is false. - type: boolean - stdinOnce: - description: Whether the container runtime should close - the stdin channel after it has been opened by a single - attach. When stdin is true the stdin stream will remain - open across multiple attach sessions. If stdinOnce is - set to true, stdin is opened on container start, is - empty until the first client attaches to stdin, and - then remains open and accepts data until the client - disconnects, at which time stdin is closed and remains - closed until the container is restarted. If this flag - is false, a container processes that reads from stdin - will never receive an EOF. Default is false - type: boolean - terminationMessagePath: - description: 'Optional: Path at which the file to which - the container''s termination message will be written - is mounted into the container''s filesystem. Message - written is intended to be brief final status, such as - an assertion failure message. Will be truncated by the - node if greater than 4096 bytes. The total message length - across all containers will be limited to 12kb. Defaults - to /dev/termination-log. Cannot be updated.' - type: string - terminationMessagePolicy: - description: Indicate how the termination message should - be populated. File will use the contents of terminationMessagePath - to populate the container status message on both success - and failure. FallbackToLogsOnError will use the last - chunk of container log output if the termination message - file is empty and the container exited with an error. - The log output is limited to 2048 bytes or 80 lines, - whichever is smaller. Defaults to File. Cannot be updated. - type: string - tty: - description: Whether this container should allocate a - TTY for itself, also requires 'stdin' to be true. Default - is false. - type: boolean - volumeDevices: - description: volumeDevices is the list of block devices - to be used by the container. This is a beta feature. - items: - description: volumeDevice describes a mapping of a raw - block device within a container. - properties: - devicePath: - description: devicePath is the path inside of the - container that the device will be mapped to. - type: string - name: - description: name must match the name of a persistentVolumeClaim - in the pod - type: string - required: - - devicePath - - name - type: object - type: array - volumeMounts: - description: Pod volumes to mount into the container's - filesystem. Cannot be updated. - items: - description: VolumeMount describes a mounting of a Volume - within a container. - properties: - mountPath: - description: Path within the container at which - the volume should be mounted. Must not contain - ':'. - type: string - mountPropagation: - description: mountPropagation determines how mounts - are propagated from the host to container and - the other way around. When not set, MountPropagationNone - is used. This field is beta in 1.10. - type: string - name: - description: This must match the Name of a Volume. - type: string - readOnly: - description: Mounted read-only if true, read-write - otherwise (false or unspecified). Defaults to - false. - type: boolean - subPath: - description: Path within the volume from which the - container's volume should be mounted. Defaults - to "" (volume's root). - type: string - subPathExpr: - description: Expanded path within the volume from - which the container's volume should be mounted. - Behaves similarly to SubPath but environment variable - references $(VAR_NAME) are expanded using the - container's environment. Defaults to "" (volume's - root). SubPathExpr and SubPath are mutually exclusive. - This field is alpha in 1.14. - type: string - required: - - mountPath - - name - type: object - type: array - workingDir: - description: Container's working directory. If not specified, - the container runtime's default will be used, which - might be configured in the container image. Cannot be - updated. - type: string - required: - - name - type: object - type: array - dnsConfig: - description: Specifies the DNS parameters of a pod. Parameters - specified here will be merged to the generated DNS configuration - based on DNSPolicy. - properties: - nameservers: - description: A list of DNS name server IP addresses. This - will be appended to the base nameservers generated from - DNSPolicy. Duplicated nameservers will be removed. - items: - type: string - type: array - options: - description: A list of DNS resolver options. This will be - merged with the base options generated from DNSPolicy. - Duplicated entries will be removed. Resolution options - given in Options will override those that appear in the - base DNSPolicy. - items: - description: PodDNSConfigOption defines DNS resolver options - of a pod. - properties: - name: - description: Required. - type: string - value: - type: string - type: object - type: array - searches: - description: A list of DNS search domains for host-name - lookup. This will be appended to the base search paths - generated from DNSPolicy. Duplicated search paths will - be removed. - items: - type: string - type: array - type: object - dnsPolicy: - description: Set DNS policy for the pod. Defaults to "ClusterFirst". - Valid values are 'ClusterFirstWithHostNet', 'ClusterFirst', - 'Default' or 'None'. DNS parameters given in DNSConfig will - be merged with the policy selected with DNSPolicy. To have - DNS options set along with hostNetwork, you have to specify - DNS policy explicitly to 'ClusterFirstWithHostNet'. - type: string - enableServiceLinks: - description: 'EnableServiceLinks indicates whether information - about services should be injected into pod''s environment - variables, matching the syntax of Docker links. Optional: - Defaults to true.' - type: boolean - hostAliases: - description: HostAliases is an optional list of hosts and IPs - that will be injected into the pod's hosts file if specified. - This is only valid for non-hostNetwork pods. - items: - description: HostAlias holds the mapping between IP and hostnames - that will be injected as an entry in the pod's hosts file. - properties: - hostnames: - description: Hostnames for the above IP address. - items: - type: string - type: array - ip: - description: IP address of the host file entry. - type: string - type: object - type: array - hostIPC: - description: 'Use the host''s ipc namespace. Optional: Default - to false.' - type: boolean - hostNetwork: - description: Host networking requested for this pod. Use the - host's network namespace. If this option is set, the ports - that will be used must be specified. Default to false. - type: boolean - hostPID: - description: 'Use the host''s pid namespace. Optional: Default - to false.' - type: boolean - hostname: - description: Specifies the hostname of the Pod If not specified, - the pod's hostname will be set to a system-defined value. - type: string - imagePullSecrets: - description: 'ImagePullSecrets is an optional list of references - to secrets in the same namespace to use for pulling any of - the images used by this PodSpec. If specified, these secrets - will be passed to individual puller implementations for them - to use. For example, in the case of docker, only DockerConfig - type secrets are honored. More info: https://kubernetes.io/docs/concepts/containers/images#specifying-imagepullsecrets-on-a-pod' - items: - description: LocalObjectReference contains enough information - to let you locate the referenced object inside the same - namespace. - properties: - name: - description: 'Name of the referent. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, uid?' - type: string - type: object - type: array - initContainers: - description: 'List of initialization containers belonging to - the pod. Init containers are executed in order prior to containers - being started. If any init container fails, the pod is considered - to have failed and is handled according to its restartPolicy. - The name for an init container or normal container must be - unique among all containers. Init containers may not have - Lifecycle actions, Readiness probes, or Liveness probes. The - resourceRequirements of an init container are taken into account - during scheduling by finding the highest request/limit for - each resource type, and then using the max of of that value - or the sum of the normal containers. Limits are applied to - init containers in a similar fashion. Init containers cannot - currently be added or removed. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/workloads/pods/init-containers/' - items: - description: A single application container that you want - to run within a pod. - properties: - args: - description: 'Arguments to the entrypoint. The docker - image''s CMD is used if this is not provided. Variable - references $(VAR_NAME) are expanded using the container''s - environment. If a variable cannot be resolved, the reference - in the input string will be unchanged. The $(VAR_NAME) - syntax can be escaped with a double $$, ie: $$(VAR_NAME). - Escaped references will never be expanded, regardless - of whether the variable exists or not. Cannot be updated. - More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - command: - description: 'Entrypoint array. Not executed within a - shell. The docker image''s ENTRYPOINT is used if this - is not provided. Variable references $(VAR_NAME) are - expanded using the container''s environment. If a variable - cannot be resolved, the reference in the input string - will be unchanged. The $(VAR_NAME) syntax can be escaped - with a double $$, ie: $$(VAR_NAME). Escaped references - will never be expanded, regardless of whether the variable - exists or not. Cannot be updated. More info: https://kubernetes.io/docs/tasks/inject-data-application/define-command-argument-container/#running-a-command-in-a-shell' - items: - type: string - type: array - env: - description: List of environment variables to set in the - container. Cannot be updated. - items: - description: EnvVar represents an environment variable - present in a Container. - properties: - name: - description: Name of the environment variable. Must - be a C_IDENTIFIER. - type: string - value: - description: 'Variable references $(VAR_NAME) are - expanded using the previous defined environment - variables in the container and any service environment - variables. If a variable cannot be resolved, the - reference in the input string will be unchanged. - The $(VAR_NAME) syntax can be escaped with a double - $$, ie: $$(VAR_NAME). Escaped references will - never be expanded, regardless of whether the variable - exists or not. Defaults to "".' - type: string - valueFrom: - description: Source for the environment variable's - value. Cannot be used if value is not empty. - properties: - configMapKeyRef: - description: Selects a key of a ConfigMap. - properties: - key: - description: The key to select. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's key must be defined - type: boolean - required: - - key - type: object - fieldRef: - description: 'Selects a field of the pod: supports - metadata.name, metadata.namespace, metadata.labels, - metadata.annotations, spec.nodeName, spec.serviceAccountName, - status.hostIP, status.podIP.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, limits.ephemeral-storage, requests.cpu, - requests.memory and requests.ephemeral-storage) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - secretKeyRef: - description: Selects a key of a secret in the - pod's namespace - properties: - key: - description: The key of the secret to select - from. Must be a valid secret key. - type: string - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or it's key must be defined - type: boolean - required: - - key - type: object - type: object - required: - - name - type: object - type: array - envFrom: - description: List of sources to populate environment variables - in the container. The keys defined within a source must - be a C_IDENTIFIER. All invalid keys will be reported - as an event when the container is starting. When a key - exists in multiple sources, the value associated with - the last source will take precedence. Values defined - by an Env with a duplicate key will take precedence. - Cannot be updated. - items: - description: EnvFromSource represents the source of - a set of ConfigMaps - properties: - configMapRef: - description: The ConfigMap to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap must - be defined - type: boolean - type: object - prefix: - description: An optional identifier to prepend to - each key in the ConfigMap. Must be a C_IDENTIFIER. - type: string - secretRef: - description: The Secret to select from - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret must - be defined - type: boolean - type: object - type: object - type: array - image: - description: 'Docker image name. More info: https://kubernetes.io/docs/concepts/containers/images - This field is optional to allow higher level config - management to default or override container images in - workload controllers like Deployments and StatefulSets.' - type: string - imagePullPolicy: - description: 'Image pull policy. One of Always, Never, - IfNotPresent. Defaults to Always if :latest tag is specified, - or IfNotPresent otherwise. Cannot be updated. More info: - https://kubernetes.io/docs/concepts/containers/images#updating-images' - type: string - lifecycle: - description: Actions that the management system should - take in response to container lifecycle events. Cannot - be updated. - properties: - postStart: - description: 'PostStart is called immediately after - a container is created. If the handler fails, the - container is terminated and restarted according - to its restart policy. Other management of the container - blocks until the hook completes. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - preStop: - description: 'PreStop is called immediately before - a container is terminated due to an API request - or management event such as liveness probe failure, - preemption, resource contention, etc. The handler - is not called if the container crashes or exits. - The reason for termination is passed to the handler. - The Pod''s termination grace period countdown begins - before the PreStop hooked is executed. Regardless - of the outcome of the handler, the container will - eventually terminate within the Pod''s termination - grace period. Other management of the container - blocks until the hook completes or until the termination - grace period is reached. More info: https://kubernetes.io/docs/concepts/containers/container-lifecycle-hooks/#container-hooks' - properties: - exec: - description: One and only one of the following - should be specified. Exec specifies the action - to take. - properties: - command: - description: Command is the command line to - execute inside the container, the working - directory for the command is root ('/') - in the container's filesystem. The command - is simply exec'd, it is not run inside a - shell, so traditional shell instructions - ('|', etc) won't work. To use a shell, you - need to explicitly call out to that shell. - Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - httpGet: - description: HTTPGet specifies the http request - to perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set - "Host" in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the - request. HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom - header to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting - to the host. Defaults to HTTP. - type: string - required: - - port - type: object - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: - implement a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect - to, defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to - access on the container. Number must be - in the range 1 to 65535. Name must be an - IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - type: object - type: object - livenessProbe: - description: 'Periodic probe of container liveness. Container - will be restarted if the probe fails. Cannot be updated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - name: - description: Name of the container specified as a DNS_LABEL. - Each container in a pod must have a unique name (DNS_LABEL). - Cannot be updated. - type: string - ports: - description: List of ports to expose from the container. - Exposing a port here gives the system additional information - about the network connections a container uses, but - is primarily informational. Not specifying a port here - DOES NOT prevent that port from being exposed. Any port - which is listening on the default "0.0.0.0" address - inside a container will be accessible from the network. - Cannot be updated. - items: - description: ContainerPort represents a network port - in a single container. - properties: - containerPort: - description: Number of port to expose on the pod's - IP address. This must be a valid port number, - 0 < x < 65536. - format: int32 - type: integer - hostIP: - description: What host IP to bind the external port - to. - type: string - hostPort: - description: Number of port to expose on the host. - If specified, this must be a valid port number, - 0 < x < 65536. If HostNetwork is specified, this - must match ContainerPort. Most containers do not - need this. - format: int32 - type: integer - name: - description: If specified, this must be an IANA_SVC_NAME - and unique within the pod. Each named port in - a pod must have a unique name. Name for the port - that can be referred to by services. - type: string - protocol: - description: Protocol for port. Must be UDP, TCP, - or SCTP. Defaults to "TCP". - type: string - default: TCP - required: - - containerPort - type: object - type: array - x-kubernetes-list-map-keys: - - containerPort - - protocol - x-kubernetes-list-type: map - readinessProbe: - description: 'Periodic probe of container service readiness. - Container will be removed from service endpoints if - the probe fails. Cannot be updated. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - properties: - exec: - description: One and only one of the following should - be specified. Exec specifies the action to take. - properties: - command: - description: Command is the command line to execute - inside the container, the working directory - for the command is root ('/') in the container's - filesystem. The command is simply exec'd, it - is not run inside a shell, so traditional shell - instructions ('|', etc) won't work. To use a - shell, you need to explicitly call out to that - shell. Exit status of 0 is treated as live/healthy - and non-zero is unhealthy. - items: - type: string - type: array - type: object - failureThreshold: - description: Minimum consecutive failures for the - probe to be considered failed after having succeeded. - Defaults to 3. Minimum value is 1. - format: int32 - type: integer - httpGet: - description: HTTPGet specifies the http request to - perform. - properties: - host: - description: Host name to connect to, defaults - to the pod IP. You probably want to set "Host" - in httpHeaders instead. - type: string - httpHeaders: - description: Custom headers to set in the request. - HTTP allows repeated headers. - items: - description: HTTPHeader describes a custom header - to be used in HTTP probes - properties: - name: - description: The header field name - type: string - value: - description: The header field value - type: string - required: - - name - - value - type: object - type: array - path: - description: Path to access on the HTTP server. - type: string - port: - anyOf: - - type: integer - - type: string - description: Name or number of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - scheme: - description: Scheme to use for connecting to the - host. Defaults to HTTP. - type: string - required: - - port - type: object - initialDelaySeconds: - description: 'Number of seconds after the container - has started before liveness probes are initiated. - More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - periodSeconds: - description: How often (in seconds) to perform the - probe. Default to 10 seconds. Minimum value is 1. - format: int32 - type: integer - successThreshold: - description: Minimum consecutive successes for the - probe to be considered successful after having failed. - Defaults to 1. Must be 1 for liveness. Minimum value - is 1. - format: int32 - type: integer - tcpSocket: - description: 'TCPSocket specifies an action involving - a TCP port. TCP hooks not yet supported TODO: implement - a realistic TCP lifecycle hook' - properties: - host: - description: 'Optional: Host name to connect to, - defaults to the pod IP.' - type: string - port: - anyOf: - - type: integer - - type: string - description: Number or name of the port to access - on the container. Number must be in the range - 1 to 65535. Name must be an IANA_SVC_NAME. - x-kubernetes-int-or-string: true - required: - - port - type: object - timeoutSeconds: - description: 'Number of seconds after which the probe - times out. Defaults to 1 second. Minimum value is - 1. More info: https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle#container-probes' - format: int32 - type: integer - type: object - resources: - description: 'Compute Resources required by this container. - Cannot be updated. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - properties: - limits: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Limits describes the maximum amount - of compute resources allowed. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - requests: - additionalProperties: - anyOf: - - type: integer - - type: string - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - description: 'Requests describes the minimum amount - of compute resources required. If Requests is omitted - for a container, it defaults to Limits if that is - explicitly specified, otherwise to an implementation-defined - value. More info: https://kubernetes.io/docs/concepts/configuration/manage-compute-resources-container/' - type: object - type: object - securityContext: - description: 'Security options the pod should run with. - More info: https://kubernetes.io/docs/concepts/policy/security-context/ - More info: https://kubernetes.io/docs/tasks/configure-pod-container/security-context/' - properties: - allowPrivilegeEscalation: - description: 'AllowPrivilegeEscalation controls whether - a process can gain more privileges than its parent - process. This bool directly controls if the no_new_privs - flag will be set on the container process. AllowPrivilegeEscalation - is true always when the container is: 1) run as - Privileged 2) has CAP_SYS_ADMIN' - type: boolean - capabilities: - description: The capabilities to add/drop when running - containers. Defaults to the default set of capabilities - granted by the container runtime. - properties: - add: - description: Added capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - drop: - description: Removed capabilities - items: - description: Capability represent POSIX capabilities - type - type: string - type: array - type: object - privileged: - description: Run container in privileged mode. Processes - in privileged containers are essentially equivalent - to root on the host. Defaults to false. - type: boolean - procMount: - description: procMount denotes the type of proc mount - to use for the containers. The default is DefaultProcMount - which uses the container runtime defaults for readonly - paths and masked paths. This requires the ProcMountType - feature flag to be enabled. - type: string - readOnlyRootFilesystem: - description: Whether this container has a read-only - root filesystem. Default is false. - type: boolean - runAsGroup: - description: The GID to run the entrypoint of the - container process. Uses runtime default if unset. - May also be set in PodSecurityContext. If set in - both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run - as a non-root user. If true, the Kubelet will validate - the image at runtime to ensure that it does not - run as UID 0 (root) and fail to start the container - if it does. If unset or false, no such validation - will be performed. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the - container process. Defaults to user specified in - image metadata if unspecified. May also be set in - PodSecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to - the container. If unspecified, the container runtime - will allocate a random SELinux context for each - container. May also be set in PodSecurityContext. If - set in both SecurityContext and PodSecurityContext, - the value specified in SecurityContext takes precedence. - properties: - level: - description: Level is SELinux level label that - applies to the container. - type: string - role: - description: Role is a SELinux role label that - applies to the container. - type: string - type: - description: Type is a SELinux type label that - applies to the container. - type: string - user: - description: User is a SELinux user label that - applies to the container. - type: string - type: object - type: object - stdin: - description: Whether this container should allocate a - buffer for stdin in the container runtime. If this is - not set, reads from stdin in the container will always - result in EOF. Default is false. - type: boolean - stdinOnce: - description: Whether the container runtime should close - the stdin channel after it has been opened by a single - attach. When stdin is true the stdin stream will remain - open across multiple attach sessions. If stdinOnce is - set to true, stdin is opened on container start, is - empty until the first client attaches to stdin, and - then remains open and accepts data until the client - disconnects, at which time stdin is closed and remains - closed until the container is restarted. If this flag - is false, a container processes that reads from stdin - will never receive an EOF. Default is false - type: boolean - terminationMessagePath: - description: 'Optional: Path at which the file to which - the container''s termination message will be written - is mounted into the container''s filesystem. Message - written is intended to be brief final status, such as - an assertion failure message. Will be truncated by the - node if greater than 4096 bytes. The total message length - across all containers will be limited to 12kb. Defaults - to /dev/termination-log. Cannot be updated.' - type: string - terminationMessagePolicy: - description: Indicate how the termination message should - be populated. File will use the contents of terminationMessagePath - to populate the container status message on both success - and failure. FallbackToLogsOnError will use the last - chunk of container log output if the termination message - file is empty and the container exited with an error. - The log output is limited to 2048 bytes or 80 lines, - whichever is smaller. Defaults to File. Cannot be updated. - type: string - tty: - description: Whether this container should allocate a - TTY for itself, also requires 'stdin' to be true. Default - is false. - type: boolean - volumeDevices: - description: volumeDevices is the list of block devices - to be used by the container. This is a beta feature. - items: - description: volumeDevice describes a mapping of a raw - block device within a container. - properties: - devicePath: - description: devicePath is the path inside of the - container that the device will be mapped to. - type: string - name: - description: name must match the name of a persistentVolumeClaim - in the pod - type: string - required: - - devicePath - - name - type: object - type: array - volumeMounts: - description: Pod volumes to mount into the container's - filesystem. Cannot be updated. - items: - description: VolumeMount describes a mounting of a Volume - within a container. - properties: - mountPath: - description: Path within the container at which - the volume should be mounted. Must not contain - ':'. - type: string - mountPropagation: - description: mountPropagation determines how mounts - are propagated from the host to container and - the other way around. When not set, MountPropagationNone - is used. This field is beta in 1.10. - type: string - name: - description: This must match the Name of a Volume. - type: string - readOnly: - description: Mounted read-only if true, read-write - otherwise (false or unspecified). Defaults to - false. - type: boolean - subPath: - description: Path within the volume from which the - container's volume should be mounted. Defaults - to "" (volume's root). - type: string - subPathExpr: - description: Expanded path within the volume from - which the container's volume should be mounted. - Behaves similarly to SubPath but environment variable - references $(VAR_NAME) are expanded using the - container's environment. Defaults to "" (volume's - root). SubPathExpr and SubPath are mutually exclusive. - This field is alpha in 1.14. - type: string - required: - - mountPath - - name - type: object - type: array - workingDir: - description: Container's working directory. If not specified, - the container runtime's default will be used, which - might be configured in the container image. Cannot be - updated. - type: string - required: - - name - type: object - type: array - nodeName: - description: NodeName is a request to schedule this pod onto - a specific node. If it is non-empty, the scheduler simply - schedules this pod onto that node, assuming that it fits resource - requirements. - type: string - nodeSelector: - additionalProperties: - type: string - description: 'NodeSelector is a selector which must be true - for the pod to fit on a node. Selector which must match a - node''s labels for the pod to be scheduled on that node. More - info: https://kubernetes.io/docs/concepts/configuration/assign-pod-node/' - type: object - priority: - description: The priority value. Various system components use - this field to find the priority of the pod. When Priority - Admission Controller is enabled, it prevents users from setting - this field. The admission controller populates this field - from PriorityClassName. The higher the value, the higher the - priority. - format: int32 - type: integer - priorityClassName: - description: If specified, indicates the pod's priority. "system-node-critical" - and "system-cluster-critical" are two special keywords which - indicate the highest priorities with the former being the - highest priority. Any other name must be defined by creating - a PriorityClass object with that name. If not specified, the - pod priority will be default or zero if there is no default. - type: string - readinessGates: - description: 'If specified, all readiness gates will be evaluated - for pod readiness. A pod is ready when all its containers - are ready AND all conditions specified in the readiness gates - have status equal to "True" More info: https://git.k8s.io/enhancements/keps/sig-network/0007-pod-ready%2B%2B.md' - items: - description: PodReadinessGate contains the reference to a - pod condition - properties: - conditionType: - description: ConditionType refers to a condition in the - pod's condition list with matching type. - type: string - required: - - conditionType - type: object - type: array - restartPolicy: - description: 'Restart policy for all containers within the pod. - One of Always, OnFailure, Never. Default to Always. More info: - https://kubernetes.io/docs/concepts/workloads/pods/pod-lifecycle/#restart-policy' - type: string - runtimeClassName: - description: 'RuntimeClassName refers to a RuntimeClass object - in the node.k8s.io group, which should be used to run this - pod. If no RuntimeClass resource matches the named class, - the pod will not be run. If unset or empty, the "legacy" RuntimeClass - will be used, which is an implicit class with an empty definition - that uses the default runtime handler. More info: https://git.k8s.io/enhancements/keps/sig-node/runtime-class.md - This is an alpha feature and may change in the future.' - type: string - schedulerName: - description: If specified, the pod will be dispatched by specified - scheduler. If not specified, the pod will be dispatched by - default scheduler. - type: string - securityContext: - description: 'SecurityContext holds pod-level security attributes - and common container settings. Optional: Defaults to empty. See - type description for default values of each field.' - properties: - fsGroup: - description: "A special supplemental group that applies - to all containers in a pod. Some volume types allow the - Kubelet to change the ownership of that volume to be owned - by the pod: \n 1. The owning GID will be the FSGroup 2. - The setgid bit is set (new files created in the volume - will be owned by FSGroup) 3. The permission bits are OR'd - with rw-rw---- \n If unset, the Kubelet will not modify - the ownership and permissions of any volume." - format: int64 - type: integer - runAsGroup: - description: The GID to run the entrypoint of the container - process. Uses runtime default if unset. May also be set - in SecurityContext. If set in both SecurityContext and - PodSecurityContext, the value specified in SecurityContext - takes precedence for that container. - format: int64 - type: integer - runAsNonRoot: - description: Indicates that the container must run as a - non-root user. If true, the Kubelet will validate the - image at runtime to ensure that it does not run as UID - 0 (root) and fail to start the container if it does. If - unset or false, no such validation will be performed. - May also be set in SecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence. - type: boolean - runAsUser: - description: The UID to run the entrypoint of the container - process. Defaults to user specified in image metadata - if unspecified. May also be set in SecurityContext. If - set in both SecurityContext and PodSecurityContext, the - value specified in SecurityContext takes precedence for - that container. - format: int64 - type: integer - seLinuxOptions: - description: The SELinux context to be applied to all containers. - If unspecified, the container runtime will allocate a - random SELinux context for each container. May also be - set in SecurityContext. If set in both SecurityContext - and PodSecurityContext, the value specified in SecurityContext - takes precedence for that container. - properties: - level: - description: Level is SELinux level label that applies - to the container. - type: string - role: - description: Role is a SELinux role label that applies - to the container. - type: string - type: - description: Type is a SELinux type label that applies - to the container. - type: string - user: - description: User is a SELinux user label that applies - to the container. - type: string - type: object - supplementalGroups: - description: A list of groups applied to the first process - run in each container, in addition to the container's - primary GID. If unspecified, no groups will be added - to any container. - items: - format: int64 - type: integer - type: array - sysctls: - description: Sysctls hold a list of namespaced sysctls used - for the pod. Pods with unsupported sysctls (by the container - runtime) might fail to launch. - items: - description: Sysctl defines a kernel parameter to be set - properties: - name: - description: Name of a property to set - type: string - value: - description: Value of a property to set - type: string - required: - - name - - value - type: object - type: array - type: object - serviceAccount: - description: 'DeprecatedServiceAccount is a depreciated alias - for ServiceAccountName. Deprecated: Use serviceAccountName - instead.' - type: string - serviceAccountName: - description: 'ServiceAccountName is the name of the ServiceAccount - to use to run this pod. More info: https://kubernetes.io/docs/tasks/configure-pod-container/configure-service-account/' - type: string - shareProcessNamespace: - description: 'Share a single process namespace between all of - the containers in a pod. When this is set containers will - be able to view and signal processes from other containers - in the same pod, and the first process in each container will - not be assigned PID 1. HostPID and ShareProcessNamespace cannot - both be set. Optional: Default to false. This field is beta-level - and may be disabled with the PodShareProcessNamespace feature.' - type: boolean - subdomain: - description: If specified, the fully qualified Pod hostname - will be "...svc.". If not specified, the pod will not have a domainname - at all. - type: string - terminationGracePeriodSeconds: - description: Optional duration in seconds the pod needs to terminate - gracefully. May be decreased in delete request. Value must - be non-negative integer. The value zero indicates delete immediately. - If this value is nil, the default grace period will be used - instead. The grace period is the duration in seconds after - the processes running in the pod are sent a termination signal - and the time when the processes are forcibly halted with a - kill signal. Set this value longer than the expected cleanup - time for your process. Defaults to 30 seconds. - format: int64 - type: integer - tolerations: - description: If specified, the pod's tolerations. - items: - description: The pod this Toleration is attached to tolerates - any taint that matches the triple using - the matching operator . - properties: - effect: - description: Effect indicates the taint effect to match. - Empty means match all taint effects. When specified, - allowed values are NoSchedule, PreferNoSchedule and - NoExecute. - type: string - key: - description: Key is the taint key that the toleration - applies to. Empty means match all taint keys. If the - key is empty, operator must be Exists; this combination - means to match all values and all keys. - type: string - operator: - description: Operator represents a key's relationship - to the value. Valid operators are Exists and Equal. - Defaults to Equal. Exists is equivalent to wildcard - for value, so that a pod can tolerate all taints of - a particular category. - type: string - tolerationSeconds: - description: TolerationSeconds represents the period of - time the toleration (which must be of effect NoExecute, - otherwise this field is ignored) tolerates the taint. - By default, it is not set, which means tolerate the - taint forever (do not evict). Zero and negative values - will be treated as 0 (evict immediately) by the system. - format: int64 - type: integer - value: - description: Value is the taint value the toleration matches - to. If the operator is Exists, the value should be empty, - otherwise just a regular string. - type: string - type: object - type: array - volumes: - description: 'List of volumes that can be mounted by containers - belonging to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes' - items: - description: Volume represents a named volume in a pod that - may be accessed by any container in the pod. - properties: - awsElasticBlockStore: - description: 'AWSElasticBlockStore represents an AWS Disk - resource that is attached to a kubelet''s host machine - and then exposed to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - partition: - description: 'The partition in the volume that you - want to mount. If omitted, the default is to mount - by volume name. Examples: For volume /dev/sda1, - you specify the partition as "1". Similarly, the - volume partition for /dev/sda is "0" (or you can - leave the property empty).' - format: int32 - type: integer - readOnly: - description: 'Specify "true" to force and set the - ReadOnly property in VolumeMounts to "true". If - omitted, the default is "false". More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - type: boolean - volumeID: - description: 'Unique ID of the persistent disk resource - in AWS (Amazon EBS volume). More info: https://kubernetes.io/docs/concepts/storage/volumes#awselasticblockstore' - type: string - required: - - volumeID - type: object - azureDisk: - description: AzureDisk represents an Azure Data Disk mount - on the host and bind mount to the pod. - properties: - cachingMode: - description: 'Host Caching mode: None, Read Only, - Read Write.' - type: string - diskName: - description: The Name of the data disk in the blob - storage - type: string - diskURI: - description: The URI the data disk in the blob storage - type: string - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - kind: - description: 'Expected values Shared: multiple blob - disks per storage account Dedicated: single blob - disk per storage account Managed: azure managed - data disk (only in managed availability set). defaults - to shared' - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - required: - - diskName - - diskURI - type: object - azureFile: - description: AzureFile represents an Azure File Service - mount on the host and bind mount to the pod. - properties: - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretName: - description: the name of secret that contains Azure - Storage Account Name and Key - type: string - shareName: - description: Share Name - type: string - required: - - secretName - - shareName - type: object - cephfs: - description: CephFS represents a Ceph FS mount on the - host that shares a pod's lifetime - properties: - monitors: - description: 'Required: Monitors is a collection of - Ceph monitors More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - items: - type: string - type: array - path: - description: 'Optional: Used as the mounted root, - rather than the full Ceph tree, default is /' - type: string - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts. More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: boolean - secretFile: - description: 'Optional: SecretFile is the path to - key ring for User, default is /etc/ceph/user.secret - More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: string - secretRef: - description: 'Optional: SecretRef is reference to - the authentication secret for User, default is empty. - More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - user: - description: 'Optional: User is the rados user name, - default is admin More info: https://releases.k8s.io/HEAD/examples/volumes/cephfs/README.md#how-to-use-it' - type: string - required: - - monitors - type: object - cinder: - description: 'Cinder represents a cinder volume attached - and mounted on kubelets host machine More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - properties: - fsType: - description: 'Filesystem type to mount. Must be a - filesystem type supported by the host operating - system. Examples: "ext4", "xfs", "ntfs". Implicitly - inferred to be "ext4" if unspecified. More info: - https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: string - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts. More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: boolean - secretRef: - description: 'Optional: points to a secret object - containing parameters used to connect to OpenStack.' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - volumeID: - description: 'volume id used to identify the volume - in cinder More info: https://releases.k8s.io/HEAD/examples/mysql-cinder-pd/README.md' - type: string - required: - - volumeID - type: object - configMap: - description: ConfigMap represents a configMap that should - populate this volume - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: If unspecified, each key-value pair in - the Data field of the referenced ConfigMap will - be projected into the volume as a file whose name - is the key and content is the value. If specified, - the listed keys will be projected into the specified - paths, and unlisted keys will not be present. If - a key is specified which is not present in the ConfigMap, - the volume setup will error unless it is marked - optional. Paths must be relative and may not contain - the '..' path or start with '..'. - items: - description: Maps a string key to a path within - a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of the file to - map the key to. May not be an absolute path. - May not contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - optional: - description: Specify whether the ConfigMap or it's - keys must be defined - type: boolean - type: object - csi: - description: CSI (Container Storage Interface) represents - storage that is handled by an external CSI driver (Alpha - feature). - properties: - driver: - description: Driver is the name of the CSI driver - that handles this volume. Consult with your admin - for the correct name as registered in the cluster. - type: string - fsType: - description: Filesystem type to mount. Ex. "ext4", - "xfs", "ntfs". If not provided, the empty value - is passed to the associated CSI driver which will - determine the default filesystem to apply. - type: string - nodePublishSecretRef: - description: NodePublishSecretRef is a reference to - the secret object containing sensitive information - to pass to the CSI driver to complete the CSI NodePublishVolume - and NodeUnpublishVolume calls. This field is optional, - and may be empty if no secret is required. If the - secret object contains more than one secret, all - secret references are passed. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - readOnly: - description: Specifies a read-only configuration for - the volume. Defaults to false (read/write). - type: boolean - volumeAttributes: - additionalProperties: - type: string - description: VolumeAttributes stores driver-specific - properties that are passed to the CSI driver. Consult - your driver's documentation for supported values. - type: object - required: - - driver - type: object - downwardAPI: - description: DownwardAPI represents downward API about - the pod that should populate this volume - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: Items is a list of downward API volume - file - items: - description: DownwardAPIVolumeFile represents information - to create the file containing the pod field - properties: - fieldRef: - description: 'Required: Selects a field of the - pod: only annotations, labels, name and namespace - are supported.' - properties: - apiVersion: - description: Version of the schema the FieldPath - is written in terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field to select - in the specified API version. - type: string - required: - - fieldPath - type: object - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: 'Required: Path is the relative - path name of the file to be created. Must - not be absolute or contain the ''..'' path. - Must be utf-8 encoded. The first item of the - relative path must not start with ''..''' - type: string - resourceFieldRef: - description: 'Selects a resource of the container: - only resources limits and requests (limits.cpu, - limits.memory, requests.cpu and requests.memory) - are currently supported.' - properties: - containerName: - description: 'Container name: required for - volumes, optional for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output format - of the exposed resources, defaults to - "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource to select' - type: string - required: - - resource - type: object - required: - - path - type: object - type: array - type: object - emptyDir: - description: 'EmptyDir represents a temporary directory - that shares a pod''s lifetime. More info: https://kubernetes.io/docs/concepts/storage/volumes#emptydir' - properties: - medium: - description: 'What type of storage medium should back - this directory. The default is "" which means to - use the node''s default medium. Must be an empty - string (default) or Memory. More info: https://kubernetes.io/docs/concepts/storage/volumes#emptydir' - type: string - sizeLimit: - anyOf: - - type: integer - - type: string - description: 'Total amount of local storage required - for this EmptyDir volume. The size limit is also - applicable for memory medium. The maximum usage - on memory medium EmptyDir would be the minimum value - between the SizeLimit specified here and the sum - of memory limits of all containers in a pod. The - default is nil which means that the limit is undefined. - More info: http://kubernetes.io/docs/user-guide/volumes#emptydir' - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - type: object - fc: - description: FC represents a Fibre Channel resource that - is attached to a kubelet's host machine and then exposed - to the pod. - properties: - fsType: - description: 'Filesystem type to mount. Must be a - filesystem type supported by the host operating - system. Ex. "ext4", "xfs", "ntfs". Implicitly inferred - to be "ext4" if unspecified. TODO: how do we prevent - errors in the filesystem from compromising the machine' - type: string - lun: - description: 'Optional: FC target lun number' - format: int32 - type: integer - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts.' - type: boolean - targetWWNs: - description: 'Optional: FC target worldwide names - (WWNs)' - items: - type: string - type: array - wwids: - description: 'Optional: FC volume world wide identifiers - (wwids) Either wwids or combination of targetWWNs - and lun must be set, but not both simultaneously.' - items: - type: string - type: array - type: object - flexVolume: - description: FlexVolume represents a generic volume resource - that is provisioned/attached using an exec based plugin. - properties: - driver: - description: Driver is the name of the driver to use - for this volume. - type: string - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". The default filesystem depends - on FlexVolume script. - type: string - options: - additionalProperties: - type: string - description: 'Optional: Extra command options if any.' - type: object - readOnly: - description: 'Optional: Defaults to false (read/write). - ReadOnly here will force the ReadOnly setting in - VolumeMounts.' - type: boolean - secretRef: - description: 'Optional: SecretRef is reference to - the secret object containing sensitive information - to pass to the plugin scripts. This may be empty - if no secret object is specified. If the secret - object contains more than one secret, all secrets - are passed to the plugin scripts.' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - required: - - driver - type: object - flocker: - description: Flocker represents a Flocker volume attached - to a kubelet's host machine. This depends on the Flocker - control service being running - properties: - datasetName: - description: Name of the dataset stored as metadata - -> name on the dataset for Flocker should be considered - as deprecated - type: string - datasetUUID: - description: UUID of the dataset. This is unique identifier - of a Flocker dataset - type: string - type: object - gcePersistentDisk: - description: 'GCEPersistentDisk represents a GCE Disk - resource that is attached to a kubelet''s host machine - and then exposed to the pod. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - partition: - description: 'The partition in the volume that you - want to mount. If omitted, the default is to mount - by volume name. Examples: For volume /dev/sda1, - you specify the partition as "1". Similarly, the - volume partition for /dev/sda is "0" (or you can - leave the property empty). More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - format: int32 - type: integer - pdName: - description: 'Unique name of the PD resource in GCE. - Used to identify the disk in GCE. More info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - type: string - readOnly: - description: 'ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. More - info: https://kubernetes.io/docs/concepts/storage/volumes#gcepersistentdisk' - type: boolean - required: - - pdName - type: object - gitRepo: - description: 'GitRepo represents a git repository at a - particular revision. DEPRECATED: GitRepo is deprecated. - To provision a container with a git repo, mount an EmptyDir - into an InitContainer that clones the repo using git, - then mount the EmptyDir into the Pod''s container.' - properties: - directory: - description: Target directory name. Must not contain - or start with '..'. If '.' is supplied, the volume - directory will be the git repository. Otherwise, - if specified, the volume will contain the git repository - in the subdirectory with the given name. - type: string - repository: - description: Repository URL - type: string - revision: - description: Commit hash for the specified revision. - type: string - required: - - repository - type: object - glusterfs: - description: 'Glusterfs represents a Glusterfs mount on - the host that shares a pod''s lifetime. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md' - properties: - endpoints: - description: 'EndpointsName is the endpoint name that - details Glusterfs topology. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: string - path: - description: 'Path is the Glusterfs volume path. More - info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: string - readOnly: - description: 'ReadOnly here will force the Glusterfs - volume to be mounted with read-only permissions. - Defaults to false. More info: https://releases.k8s.io/HEAD/examples/volumes/glusterfs/README.md#create-a-pod' - type: boolean - required: - - endpoints - - path - type: object - hostPath: - description: 'HostPath represents a pre-existing file - or directory on the host machine that is directly exposed - to the container. This is generally used for system - agents or other privileged things that are allowed to - see the host machine. Most containers will NOT need - this. More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath - --- TODO(jonesdl) We need to restrict who can use host - directory mounts and who can/can not mount host directories - as read/write.' - properties: - path: - description: 'Path of the directory on the host. If - the path is a symlink, it will follow the link to - the real path. More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath' - type: string - type: - description: 'Type for HostPath Volume Defaults to - "" More info: https://kubernetes.io/docs/concepts/storage/volumes#hostpath' - type: string - required: - - path - type: object - iscsi: - description: 'ISCSI represents an ISCSI Disk resource - that is attached to a kubelet''s host machine and then - exposed to the pod. More info: https://releases.k8s.io/HEAD/examples/volumes/iscsi/README.md' - properties: - chapAuthDiscovery: - description: whether support iSCSI Discovery CHAP - authentication - type: boolean - chapAuthSession: - description: whether support iSCSI Session CHAP authentication - type: boolean - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#iscsi - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - initiatorName: - description: Custom iSCSI Initiator Name. If initiatorName - is specified with iscsiInterface simultaneously, - new iSCSI interface : - will be created for the connection. - type: string - iqn: - description: Target iSCSI Qualified Name. - type: string - iscsiInterface: - description: iSCSI Interface Name that uses an iSCSI - transport. Defaults to 'default' (tcp). - type: string - lun: - description: iSCSI Target Lun number. - format: int32 - type: integer - portals: - description: iSCSI Target Portal List. The portal - is either an IP or ip_addr:port if the port is other - than default (typically TCP ports 860 and 3260). - items: - type: string - type: array - readOnly: - description: ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. - type: boolean - secretRef: - description: CHAP Secret for iSCSI target and initiator - authentication - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - targetPortal: - description: iSCSI Target Portal. The Portal is either - an IP or ip_addr:port if the port is other than - default (typically TCP ports 860 and 3260). - type: string - required: - - iqn - - lun - - targetPortal - type: object - name: - description: 'Volume''s name. Must be a DNS_LABEL and - unique within the pod. More info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names' - type: string - nfs: - description: 'NFS represents an NFS mount on the host - that shares a pod''s lifetime More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - properties: - path: - description: 'Path that is exported by the NFS server. - More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: string - readOnly: - description: 'ReadOnly here will force the NFS export - to be mounted with read-only permissions. Defaults - to false. More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: boolean - server: - description: 'Server is the hostname or IP address - of the NFS server. More info: https://kubernetes.io/docs/concepts/storage/volumes#nfs' - type: string - required: - - path - - server - type: object - persistentVolumeClaim: - description: 'PersistentVolumeClaimVolumeSource represents - a reference to a PersistentVolumeClaim in the same namespace. - More info: https://kubernetes.io/docs/concepts/storage/persistent-volumes#persistentvolumeclaims' - properties: - claimName: - description: 'ClaimName is the name of a PersistentVolumeClaim - in the same namespace as the pod using this volume. - More info: https://kubernetes.io/docs/concepts/storage/persistent-volumes#persistentvolumeclaims' - type: string - readOnly: - description: Will force the ReadOnly setting in VolumeMounts. - Default false. - type: boolean - required: - - claimName - type: object - photonPersistentDisk: - description: PhotonPersistentDisk represents a PhotonController - persistent disk attached and mounted on kubelets host - machine - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - pdID: - description: ID that identifies Photon Controller - persistent disk - type: string - required: - - pdID - type: object - portworxVolume: - description: PortworxVolume represents a portworx volume - attached and mounted on kubelets host machine - properties: - fsType: - description: FSType represents the filesystem type - to mount Must be a filesystem type supported by - the host operating system. Ex. "ext4", "xfs". Implicitly - inferred to be "ext4" if unspecified. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - volumeID: - description: VolumeID uniquely identifies a Portworx - volume - type: string - required: - - volumeID - type: object - projected: - description: Items for all in one resources secrets, configmaps, - and downward API - properties: - defaultMode: - description: Mode bits to use on created files by - default. Must be a value between 0 and 0777. Directories - within the path are not affected by this setting. - This might be in conflict with other options that - affect the file mode, like fsGroup, and the result - can be other mode bits set. - format: int32 - type: integer - sources: - description: list of volume projections - items: - description: Projection that may be projected along - with other supported volume types - properties: - configMap: - description: information about the configMap - data to project - properties: - items: - description: If unspecified, each key-value - pair in the Data field of the referenced - ConfigMap will be projected into the volume - as a file whose name is the key and content - is the value. If specified, the listed - keys will be projected into the specified - paths, and unlisted keys will not be present. - If a key is specified which is not present - in the ConfigMap, the volume setup will - error unless it is marked optional. Paths - must be relative and may not contain the - '..' path or start with '..'. - items: - description: Maps a string key to a path - within a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of - the file to map the key to. May - not be an absolute path. May not - contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the ConfigMap - or it's keys must be defined - type: boolean - type: object - downwardAPI: - description: information about the downwardAPI - data to project - properties: - items: - description: Items is a list of DownwardAPIVolume - file - items: - description: DownwardAPIVolumeFile represents - information to create the file containing - the pod field - properties: - fieldRef: - description: 'Required: Selects a - field of the pod: only annotations, - labels, name and namespace are supported.' - properties: - apiVersion: - description: Version of the schema - the FieldPath is written in - terms of, defaults to "v1". - type: string - fieldPath: - description: Path of the field - to select in the specified API - version. - type: string - required: - - fieldPath - type: object - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: 'Required: Path is the - relative path name of the file to - be created. Must not be absolute - or contain the ''..'' path. Must - be utf-8 encoded. The first item - of the relative path must not start - with ''..''' - type: string - resourceFieldRef: - description: 'Selects a resource of - the container: only resources limits - and requests (limits.cpu, limits.memory, - requests.cpu and requests.memory) - are currently supported.' - properties: - containerName: - description: 'Container name: - required for volumes, optional - for env vars' - type: string - divisor: - anyOf: - - type: integer - - type: string - description: Specifies the output - format of the exposed resources, - defaults to "1" - pattern: ^(\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))(([KMGTPE]i)|[numkMGTPE]|([eE](\+|-)?(([0-9]+(\.[0-9]*)?)|(\.[0-9]+))))?$ - x-kubernetes-int-or-string: true - resource: - description: 'Required: resource - to select' - type: string - required: - - resource - type: object - required: - - path - type: object - type: array - type: object - secret: - description: information about the secret data - to project - properties: - items: - description: If unspecified, each key-value - pair in the Data field of the referenced - Secret will be projected into the volume - as a file whose name is the key and content - is the value. If specified, the listed - keys will be projected into the specified - paths, and unlisted keys will not be present. - If a key is specified which is not present - in the Secret, the volume setup will error - unless it is marked optional. Paths must - be relative and may not contain the '..' - path or start with '..'. - items: - description: Maps a string key to a path - within a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits - to use on this file, must be a value - between 0 and 0777. If not specified, - the volume defaultMode will be used. - This might be in conflict with other - options that affect the file mode, - like fsGroup, and the result can - be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of - the file to map the key to. May - not be an absolute path. May not - contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - name: - description: 'Name of the referent. More - info: https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, - kind, uid?' - type: string - optional: - description: Specify whether the Secret - or its key must be defined - type: boolean - type: object - serviceAccountToken: - description: information about the serviceAccountToken - data to project - properties: - audience: - description: Audience is the intended audience - of the token. A recipient of a token must - identify itself with an identifier specified - in the audience of the token, and otherwise - should reject the token. The audience - defaults to the identifier of the apiserver. - type: string - expirationSeconds: - description: ExpirationSeconds is the requested - duration of validity of the service account - token. As the token approaches expiration, - the kubelet volume plugin will proactively - rotate the service account token. The - kubelet will start trying to rotate the - token if the token is older than 80 percent - of its time to live or if the token is - older than 24 hours.Defaults to 1 hour - and must be at least 10 minutes. - format: int64 - type: integer - path: - description: Path is the path relative to - the mount point of the file to project - the token into. - type: string - required: - - path - type: object - type: object - type: array - required: - - sources - type: object - quobyte: - description: Quobyte represents a Quobyte mount on the - host that shares a pod's lifetime - properties: - group: - description: Group to map volume access to Default - is no group - type: string - readOnly: - description: ReadOnly here will force the Quobyte - volume to be mounted with read-only permissions. - Defaults to false. - type: boolean - registry: - description: Registry represents a single or multiple - Quobyte Registry services specified as a string - as host:port pair (multiple entries are separated - with commas) which acts as the central registry - for volumes - type: string - tenant: - description: Tenant owning the given Quobyte volume - in the Backend Used with dynamically provisioned - Quobyte volumes, value is set by the plugin - type: string - user: - description: User to map volume access to Defaults - to serivceaccount user - type: string - volume: - description: Volume is a string that references an - already created Quobyte volume by name. - type: string - required: - - registry - - volume - type: object - rbd: - description: 'RBD represents a Rados Block Device mount - on the host that shares a pod''s lifetime. More info: - https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md' - properties: - fsType: - description: 'Filesystem type of the volume that you - want to mount. Tip: Ensure that the filesystem type - is supported by the host operating system. Examples: - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. More info: https://kubernetes.io/docs/concepts/storage/volumes#rbd - TODO: how do we prevent errors in the filesystem - from compromising the machine' - type: string - image: - description: 'The rados image name. More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - keyring: - description: 'Keyring is the path to key ring for - RBDUser. Default is /etc/ceph/keyring. More info: - https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - monitors: - description: 'A collection of Ceph monitors. More - info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - items: - type: string - type: array - pool: - description: 'The rados pool name. Default is rbd. - More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - readOnly: - description: 'ReadOnly here will force the ReadOnly - setting in VolumeMounts. Defaults to false. More - info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: boolean - secretRef: - description: 'SecretRef is name of the authentication - secret for RBDUser. If provided overrides keyring. - Default is nil. More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - user: - description: 'The rados user name. Default is admin. - More info: https://releases.k8s.io/HEAD/examples/volumes/rbd/README.md#how-to-use-it' - type: string - required: - - image - - monitors - type: object - scaleIO: - description: ScaleIO represents a ScaleIO persistent volume - attached and mounted on Kubernetes nodes. - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Default is "xfs". - type: string - gateway: - description: The host address of the ScaleIO API Gateway. - type: string - protectionDomain: - description: The name of the ScaleIO Protection Domain - for the configured storage. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretRef: - description: SecretRef references to the secret for - ScaleIO user and other sensitive information. If - this is not provided, Login operation will fail. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - sslEnabled: - description: Flag to enable/disable SSL communication - with Gateway, default false - type: boolean - storageMode: - description: Indicates whether the storage for a volume - should be ThickProvisioned or ThinProvisioned. Default - is ThinProvisioned. - type: string - storagePool: - description: The ScaleIO Storage Pool associated with - the protection domain. - type: string - system: - description: The name of the storage system as configured - in ScaleIO. - type: string - volumeName: - description: The name of a volume already created - in the ScaleIO system that is associated with this - volume source. - type: string - required: - - gateway - - secretRef - - system - type: object - secret: - description: 'Secret represents a secret that should populate - this volume. More info: https://kubernetes.io/docs/concepts/storage/volumes#secret' - properties: - defaultMode: - description: 'Optional: mode bits to use on created - files by default. Must be a value between 0 and - 0777. Defaults to 0644. Directories within the path - are not affected by this setting. This might be - in conflict with other options that affect the file - mode, like fsGroup, and the result can be other - mode bits set.' - format: int32 - type: integer - items: - description: If unspecified, each key-value pair in - the Data field of the referenced Secret will be - projected into the volume as a file whose name is - the key and content is the value. If specified, - the listed keys will be projected into the specified - paths, and unlisted keys will not be present. If - a key is specified which is not present in the Secret, - the volume setup will error unless it is marked - optional. Paths must be relative and may not contain - the '..' path or start with '..'. - items: - description: Maps a string key to a path within - a volume. - properties: - key: - description: The key to project. - type: string - mode: - description: 'Optional: mode bits to use on - this file, must be a value between 0 and 0777. - If not specified, the volume defaultMode will - be used. This might be in conflict with other - options that affect the file mode, like fsGroup, - and the result can be other mode bits set.' - format: int32 - type: integer - path: - description: The relative path of the file to - map the key to. May not be an absolute path. - May not contain the path element '..'. May - not start with the string '..'. - type: string - required: - - key - - path - type: object - type: array - optional: - description: Specify whether the Secret or it's keys - must be defined - type: boolean - secretName: - description: 'Name of the secret in the pod''s namespace - to use. More info: https://kubernetes.io/docs/concepts/storage/volumes#secret' - type: string - type: object - storageos: - description: StorageOS represents a StorageOS volume attached - and mounted on Kubernetes nodes. - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - readOnly: - description: Defaults to false (read/write). ReadOnly - here will force the ReadOnly setting in VolumeMounts. - type: boolean - secretRef: - description: SecretRef specifies the secret to use - for obtaining the StorageOS API credentials. If - not specified, default values will be attempted. - properties: - name: - description: 'Name of the referent. More info: - https://kubernetes.io/docs/concepts/overview/working-with-objects/names/#names - TODO: Add other useful fields. apiVersion, kind, - uid?' - type: string - type: object - volumeName: - description: VolumeName is the human-readable name - of the StorageOS volume. Volume names are only - unique within a namespace. - type: string - volumeNamespace: - description: VolumeNamespace specifies the scope of - the volume within StorageOS. If no namespace is - specified then the Pod's namespace will be used. This - allows the Kubernetes name scoping to be mirrored - within StorageOS for tighter integration. Set VolumeName - to any name to override the default behaviour. Set - to "default" if you are not using namespaces within - StorageOS. Namespaces that do not pre-exist within - StorageOS will be created. - type: string - type: object - vsphereVolume: - description: VsphereVolume represents a vSphere volume - attached and mounted on kubelets host machine - properties: - fsType: - description: Filesystem type to mount. Must be a filesystem - type supported by the host operating system. Ex. - "ext4", "xfs", "ntfs". Implicitly inferred to be - "ext4" if unspecified. - type: string - storagePolicyID: - description: Storage Policy Based Management (SPBM) - profile ID associated with the StoragePolicyName. - type: string - storagePolicyName: - description: Storage Policy Based Management (SPBM) - profile name. - type: string - volumePath: - description: Path that identifies vSphere volume vmdk - type: string - required: - - volumePath - type: object - required: - - name - type: object - type: array - required: - - containers - type: object - headPodType: - description: Specifies the head node type. - type: string - headStartRayCommands: - description: Commands to start Ray on the head node. - type: array - items: - type: string - description: shell command - workerStartRayCommands: - description: Commands to start Ray on worker nodes. - type: array - items: - type: string - description: shell command diff --git a/tools/AutoTuner/helm-chart/templates/_helpers.tpl b/tools/AutoTuner/helm-chart/templates/_helpers.tpl deleted file mode 100644 index 615d4e36d3..0000000000 --- a/tools/AutoTuner/helm-chart/templates/_helpers.tpl +++ /dev/null @@ -1,10 +0,0 @@ -{{/* -Compute clusterMaxWorkers as the sum of per-pod-type max workers. -*/}} -{{- define "ray.clusterMaxWorkers" -}} -{{- $total := 0 }} -{{- range .Values.podTypes }} -{{- $total = add $total .maxWorkers }} -{{- end }} -{{- $total }} -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml b/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml deleted file mode 100644 index 5e0221a444..0000000000 --- a/tools/AutoTuner/helm-chart/templates/operator_cluster_scoped.yaml +++ /dev/null @@ -1,66 +0,0 @@ -{{- if and (not .Values.namespacedOperator) (not .Values.clusterOnly) }} ---- -apiVersion: v1 -kind: ServiceAccount -metadata: - name: ray-operator-serviceaccount - namespace: {{ .Values.operatorNamespace }} ---- -kind: ClusterRole -apiVersion: rbac.authorization.k8s.io/v1 -metadata: - name: ray-operator-clusterrole -rules: -- apiGroups: ["", "cluster.ray.io"] - resources: ["rayclusters", "rayclusters/finalizers", "rayclusters/status", "pods", "pods/exec", "services"] - verbs: ["get", "watch", "list", "create", "delete", "patch", "update"] -- apiGroups: [""] - resources: [events] - verbs: [create] ---- -apiVersion: rbac.authorization.k8s.io/v1 -kind: ClusterRoleBinding -metadata: - name: ray-operator-clusterrolebinding -subjects: -- kind: ServiceAccount - name: ray-operator-serviceaccount - namespace: {{ .Values.operatorNamespace }} -roleRef: - kind: ClusterRole - name: ray-operator-clusterrole - apiGroup: rbac.authorization.k8s.io ---- -apiVersion: apps/v1 -kind: Deployment -metadata: - name: ray-operator - namespace: {{ .Values.operatorNamespace }} -spec: - replicas: 1 - selector: - matchLabels: - cluster.ray.io/component: operator - template: - metadata: - labels: - cluster.ray.io/component: operator - spec: - serviceAccountName: ray-operator-serviceaccount - containers: - - name: ray - imagePullPolicy: Always - image: {{ .Values.operatorImage }} - command: ["ray-operator"] - env: - - name: AUTOSCALER_MAX_NUM_FAILURES - value: "inf" - resources: - requests: - cpu: 1 - memory: 1Gi - ephemeral-storage: 1Gi - limits: - memory: 2Gi - cpu: 1 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml b/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml deleted file mode 100644 index 4458b63059..0000000000 --- a/tools/AutoTuner/helm-chart/templates/operator_namespaced.yaml +++ /dev/null @@ -1,67 +0,0 @@ -{{- if and (.Values.namespacedOperator) (not .Values.clusterOnly) }} ---- -apiVersion: v1 -kind: ServiceAccount -metadata: - name: ray-operator-serviceaccount ---- -kind: Role -apiVersion: rbac.authorization.k8s.io/v1 -metadata: - name: ray-operator-role -rules: -- apiGroups: ["", "cluster.ray.io"] - resources: ["rayclusters", "rayclusters/finalizers", "rayclusters/status", "pods", "pods/exec", "services"] - verbs: ["get", "watch", "list", "create", "delete", "patch", "update"] -- apiGroups: [""] - resources: [events] - verbs: [create] ---- -apiVersion: rbac.authorization.k8s.io/v1 -kind: RoleBinding -metadata: - name: ray-operator-rolebinding -subjects: -- kind: ServiceAccount - name: ray-operator-serviceaccount -roleRef: - kind: Role - name: ray-operator-role - apiGroup: rbac.authorization.k8s.io ---- -apiVersion: apps/v1 -kind: Deployment -metadata: - name: ray-operator -spec: - replicas: 1 - selector: - matchLabels: - cluster.ray.io/component: operator - template: - metadata: - labels: - cluster.ray.io/component: operator - spec: - serviceAccountName: ray-operator-serviceaccount - containers: - - name: ray - imagePullPolicy: Always - image: {{ .Values.operatorImage }} - command: ["ray-operator"] - env: - - name: RAY_OPERATOR_POD_NAMESPACE - valueFrom: - fieldRef: - fieldPath: metadata.namespace - - name: AUTOSCALER_MAX_NUM_FAILURES - value: "inf" - resources: - requests: - cpu: 1 - memory: 1Gi - ephemeral-storage: 1Gi - limits: - memory: 2Gi - cpu: 1 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/templates/raycluster.yaml b/tools/AutoTuner/helm-chart/templates/raycluster.yaml deleted file mode 100644 index 51c703fadf..0000000000 --- a/tools/AutoTuner/helm-chart/templates/raycluster.yaml +++ /dev/null @@ -1,107 +0,0 @@ -{{- if not .Values.operatorOnly }} -apiVersion: cluster.ray.io/v1 -kind: RayCluster -metadata: - name: {{ .Release.Name }} -spec: - # The maximum number of workers nodes to launch in addition to the head node. - maxWorkers: {{ include "ray.clusterMaxWorkers" . }} - # The autoscaler will scale up the cluster faster with higher upscaling speed. - # E.g., if the task requires adding more nodes then autoscaler will gradually - # scale up the cluster in chunks of upscaling_speed*currently_running_nodes. - # This number should be > 0. - upscalingSpeed: 1.0 - # If a node is idle for this many minutes, it will be removed. - idleTimeoutMinutes: 5 - # Specify the pod type for the ray head node (as configured below). - headPodType: {{ .Values.headPodType }} - # Specify the allowed pod types for this ray cluster and the resources they provide. - podTypes: - {{- range $key, $val := .Values.podTypes }} - - name: {{ $key }} - minWorkers: {{ $val.minWorkers | default 0}} - maxWorkers: {{ $val.maxWorkers | default 0}} - {{- if $val.rayResources }} - rayResources: - {{- toYaml $val.rayResources | nindent 8 }} - {{- end }} - podConfig: - apiVersion: v1 - kind: Pod - metadata: - generateName: {{ kebabcase $key }}- - spec: - restartPolicy: Never - # This volume allocates shared memory for Ray to use for its plasma - # object store. If you do not provide this, Ray will fall back to - # /tmp which cause slowdowns if is not a shared memory volume. - volumes: - - name: dshm - emptyDir: - medium: Memory - - name: nfs-share - persistentVolumeClaim: - claimName: nfs-dynamic-pvc - readOnly: false - - containers: - - name: ray-node - imagePullPolicy: Always - image: {{ $.Values.image }} - # Do not change this command - it keeps the pod alive until it is - # explicitly killed. - command: ["/bin/bash", "-c", "--"] - args: ['trap : TERM INT; sleep infinity & wait;'] - env: - - name: RAY_gcs_server_rpc_server_thread_num - value: "1" - ports: - - containerPort: 6379 # Redis port for Ray <= 1.10.0. GCS server port for Ray >= 1.11.0. - - containerPort: 10001 # Used by Ray Client - - containerPort: 8265 # Used by Ray Dashboard - - containerPort: 8000 # Used by Ray Serve - - # This volume allocates shared memory for Ray to use for its plasma - # object store. If you do not provide this, Ray will fall back to - # /tmp which cause slowdowns if is not a shared memory volume. - volumeMounts: - - mountPath: /dev/shm - name: dshm - - mountPath: /shared-data - name: nfs-share - resources: - requests: - cpu: {{ .CPU }} - memory: {{ .memory }} - limits: - cpu: {{ .CPU }} - # The maximum memory that this pod is allowed to use. The - # limit will be detected by ray and split to use 10% for - # redis, 30% for the shared memory object store, and the - # rest for application memory. If this limit is not set and - # the object store size is not set manually, ray will - # allocate a very large object store in each pod that may - # cause problems for other pods. - memory: {{ .memory }} - {{- if .GPU }} - nvidia.com/gpu: {{ .GPU }} - {{- end }} - {{- if .nodeSelector }} - nodeSelector: - {{- toYaml $val.nodeSelector | nindent 12 }} - {{- end }} - {{- if $val.tolerations }} - tolerations: - {{- toYaml $val.tolerations | nindent 10 }} - {{- end }} - {{- end }} - # Commands to start Ray on the head node. You don't need to change this. - # Note dashboard-host is set to 0.0.0.0 so that Kubernetes can port forward. - headStartRayCommands: - - ray stop - - ulimit -n 65536; ray start --head --port=6379 --no-monitor --dashboard-host 0.0.0.0 - # Commands to start Ray on worker nodes. You don't need to change this. - workerStartRayCommands: - - ray stop - - ulimit -n 65536; ray start --address=$RAY_HEAD_IP:6379 -{{- end }} diff --git a/tools/AutoTuner/helm-chart/values.yaml b/tools/AutoTuner/helm-chart/values.yaml deleted file mode 100644 index c420c5ffd0..0000000000 --- a/tools/AutoTuner/helm-chart/values.yaml +++ /dev/null @@ -1,107 +0,0 @@ -# Default values for Ray. - -# RayCluster settings: - -# image is Ray image to use for the head and workers of this Ray cluster. -# It's recommended to build custom dependencies for your workload into this image, -# taking one of the offical `rayproject/ray` images as base. -image: openroad/ray:latest -# headPodType is the podType used for the Ray head node (as configured below). -headPodType: rayHeadType -# podTypes is the list of pod configurations available for use as Ray nodes. -podTypes: - # The key for each podType is a user-defined string. - # Since we set headPodType: rayHeadType, the Ray head pod will use the configuration - # defined in this entry of podTypes: - rayHeadType: - # CPU is the number of CPUs used by this pod type. - # (Used for both requests and limits. Must be an integer, as Ray does not support fractional CPUs.) - CPU: 7 - # memory is the memory used by this Pod type. - # (Used for both requests and limits.) - memory: 24Gi - # GPU is the number of NVIDIA GPUs used by this pod type. - # (Optional, requires GPU nodes with appropriate setup. See https://docs.ray.io/en/master/cluster/kubernetes-gpu.html) - GPU: 0 - # rayResources is an optional string-int mapping signalling additional resources to Ray. - # "CPU", "GPU", and "memory" are filled automatically based on the above settings, but can be overriden; - # For example, rayResources: {"CPU": 0} can be used in the head podType to prevent Ray from scheduling tasks on the head. - # See https://docs.ray.io/en/master/advanced.html#dynamic-remote-parameters for an example of usage of custom resources in a Ray task. - rayResources: {"CPU": 0} - # Optionally, set a node selector for this podType: https://kubernetes.io/docs/concepts/scheduling-eviction/assign-pod-node/#nodeselector - nodeSelector: - cloud.google.com/gke-nodepool: default-pool - - # tolerations for Ray pods of this podType (the head's podType in this case) - # ref: https://kubernetes.io/docs/concepts/configuration/taint-and-toleration/ - # Note that it is often not necessary to manually specify tolerations for GPU - # usage on managed platforms such as AKS, EKS, and GKE. - # ref: https://docs.ray.io/en/master/cluster/kubernetes-gpu.html - tolerations: [] - # - key: "nvidia.com/gpu" - # operator: Exists - # effect: NoSchedule - - # The key for each podType is a user-defined string. - rayWorkerType: - # minWorkers is the minimum number of Ray workers of this pod type to keep running. - minWorkers: 2 - # maxWorkers is the maximum number of Ray workers of this pod type to which Ray will scale. - maxWorkers: 30 - # memory is the memory used by this Pod type. - # (Used for both requests and limits.) - memory: 100Gi - # CPU is the number of CPUs used by this pod type. - # (Used for both requests and limits. Must be an integer, as Ray does not support fractional CPUs.) - CPU: 28 - # GPU is the number of NVIDIA GPUs used by this pod type. - # (Optional, requires GPU nodes with appropriate setup. See https://docs.ray.io/en/master/cluster/kubernetes-gpu.html) - GPU: 0 - # rayResources is an optional string-int mapping signalling additional resources to Ray. - # "CPU", "GPU", and "memory" are filled automatically based on the above settings, but can be overriden; - # For example, rayResources: {"CPU": 0} can be used in the head podType to prevent Ray from scheduling tasks on the head. - # See https://docs.ray.io/en/master/advanced.html#dynamic-remote-parameters for an example of usage of custom resources in a Ray task. - rayResources: {} - # Optionally, set a node selector for this Pod type. See https://kubernetes.io/docs/concepts/scheduling-eviction/assign-pod-node/#nodeselector - nodeSelector: - cloud.google.com/gke-nodepool: worker-pool - - # tolerations for Ray pods of this podType - # ref: https://kubernetes.io/docs/concepts/configuration/taint-and-toleration/ - # Note that it is often not necessary to manually specify tolerations for GPU - # usage on managed platforms such as AKS, EKS, and GKE. - # ref: https://docs.ray.io/en/master/cluster/kubernetes-gpu.html - tolerations: [] - # - key: nvidia.com/gpu - # operator: Exists - # effect: NoSchedule - - # Optionally, define more worker podTypes - # rayWorkerType2: - # minWorkers: 0 - # maxWorkers: 10 - # memory: ... - - -# Operator settings: - -# operatorOnly - If true, will only set up the Operator with this release, -# without launching a Ray cluster. -operatorOnly: false -# clusterOnly - If true, will only create a RayCluster resource with this release, -# without setting up the Operator. -# (Useful when launching multiple Ray clusters.) -clusterOnly: false -# namespacedOperator - If true, the operator is scoped to the Release namespace -# and only manages RayClusters in that namespace. -# By default, the operator is cluster-scoped and runs in the default namespace. -namespacedOperator: false -# operatorNamepsace - If using a cluster-scoped operator (namespacedOperator: false), set the namespace -# in which to launch the operator. -operatorNamespace: default -# operatorImage - The image used in the operator deployment. -# It is recommended to use one of the official `rayproject/ray` images for the operator. -# It is recommended to use the same Ray version in the operator as in the Ray clusters managed -# by the operator. In other words, the images specified under the fields `operatorImage` and `image` -# should carry matching Ray versions. -operatorImage: rayproject/ray:latest diff --git a/tools/AutoTuner/installer.sh b/tools/AutoTuner/installer.sh index c694715511..c6b784ee63 100755 --- a/tools/AutoTuner/installer.sh +++ b/tools/AutoTuner/installer.sh @@ -7,5 +7,27 @@ script_dir="$(dirname "${BASH_SOURCE[0]}")" venv_name="autotuner_env" python3 -m venv "$script_dir/$venv_name" source "$script_dir/$venv_name/bin/activate" -pip3 install -U -r $script_dir/requirements.txt + +retry_count=0 +max_retries=5 +success=false + +while [[ $retry_count -lt $max_retries ]]; do + if pip3 cache purge && pip3 install --no-cache-dir -U -r "$script_dir/requirements.txt"; then + success=true + break + else + retry_count=$((retry_count + 1)) + echo "Attempt $retry_count failed. Retrying in 1 minute..." + sleep 60 + fi +done + +if [ "$success" = false ]; then + echo "Failed to install requirements after $max_retries attempts." + deactivate + exit 1 +fi + +pip3 install --no-cache-dir -e "$script_dir" deactivate diff --git a/tools/AutoTuner/kubernetes/Dockerfile b/tools/AutoTuner/kubernetes/Dockerfile deleted file mode 100644 index d07ca06f5f..0000000000 --- a/tools/AutoTuner/kubernetes/Dockerfile +++ /dev/null @@ -1,13 +0,0 @@ -FROM rayproject/ray:1.11.0 - -RUN pip install -U ax-platform hyperopt nevergrad optuna pandas - -RUN sudo apt-get update -y \ - && sudo apt-get install -y vim htop gcc time libffi-dev \ - && wget https://www.klayout.org/downloads/Ubuntu-20/klayout_0.27.1-1_amd64.deb \ - && sudo apt-get install -y --fix-broken ./klayout_0.27.1-1_amd64.deb \ - && rm ./klayout_0.27.1-1_amd64.deb - -RUN wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD/master/etc/DependencyInstaller.sh \ - && sudo bash ./DependencyInstaller.sh -dev \ - && rm DependencyInstaller.sh diff --git a/tools/AutoTuner/kubernetes/distributed-job-example.yaml b/tools/AutoTuner/kubernetes/distributed-job-example.yaml deleted file mode 100644 index 728e35c235..0000000000 --- a/tools/AutoTuner/kubernetes/distributed-job-example.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Job to submit a Ray program from a pod outside a running Ray cluster. -apiVersion: batch/v1 -kind: Job -metadata: - name: ray-test-job -spec: - template: - spec: - restartPolicy: Never - containers: - - name: ray - image: gcr.io/foss-fpga-tools-ext-openroad/ray - imagePullPolicy: Always - command: [ "/bin/bash", "-c", "--" ] - args: - - "echo " - resources: - requests: - cpu: 100m - memory: 512Mi diff --git a/tools/AutoTuner/kubernetes/run.py b/tools/AutoTuner/kubernetes/run.py deleted file mode 100644 index b9e944d748..0000000000 --- a/tools/AutoTuner/kubernetes/run.py +++ /dev/null @@ -1,33 +0,0 @@ -""" This script is meant to be run from a pod in the same Kubernetes namespace -as your Ray cluster. -""" - -from collections import Counter -import sys -import time -import ray - - -@ray.remote -def gethostname(x): - import platform - - time.sleep(2) - return x + (platform.node(),) - - -def main(): - """ - Check that objects can be transferred from each node to each other node. - """ - results = [gethostname.remote(gethostname.remote(())) for _ in range(10)] - print(Counter(ray.get(results))) - sys.stdout.flush() - - print("Success!") - sys.stdout.flush() - - -if __name__ == "__main__": - ray.init("ray://127.0.0.1:10001") - main() diff --git a/tools/AutoTuner/kubernetes/submit.yaml b/tools/AutoTuner/kubernetes/submit.yaml deleted file mode 100644 index 10cb632e4b..0000000000 --- a/tools/AutoTuner/kubernetes/submit.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Job to submit a Ray program from a pod outside a running Ray cluster. -apiVersion: batch/v1 -kind: Job -metadata: - name: ray-test-job -spec: - template: - spec: - restartPolicy: Never - containers: - - name: ray - image: openroad/ray - imagePullPolicy: Always - command: [ "/bin/bash", "-c", "--" ] - args: - - "wget https://raw.githubusercontent.com/The-OpenROAD-Project/OpenROAD-flow-scripts/master/tools/AutoTuner/kubernetes/run.py && python run.py" - resources: - requests: - cpu: 100m - memory: 512Mi diff --git a/tools/AutoTuner/nfs/nfs-helm-values.yaml b/tools/AutoTuner/nfs/nfs-helm-values.yaml deleted file mode 100644 index 04b2fb41f1..0000000000 --- a/tools/AutoTuner/nfs/nfs-helm-values.yaml +++ /dev/null @@ -1,108 +0,0 @@ -replicaCount: 1 -strategyType: Recreate - -image: - # from https://github.com/kubernetes-sigs/nfs-subdir-external-provisioner - repository: k8s.gcr.io/sig-storage/nfs-subdir-external-provisioner - tag: v4.0.2 - pullPolicy: IfNotPresent -imagePullSecrets: [] - -nfs: - # TODO: check before deploying the chart - server: - # TODO: check before deploying the chart - path: - mountOptions: - volumeName: nfs-provisioner - # Reclaim policy for the main nfs volume - reclaimPolicy: Retain - -# For creating the StorageClass automatically: -storageClass: - create: true - - # Set a provisioner name. If unset, a name will be generated. - # provisionerName: - - # Set StorageClass as the default StorageClass - # Ignored if storageClass.create is false - defaultClass: false - - # Set a StorageClass name - # Ignored if storageClass.create is false - name: nfs-client - - # Allow volume to be expanded dynamically - allowVolumeExpansion: true - - # Method used to reclaim an obsoleted volume - reclaimPolicy: Delete - - # When set to false your PVs will not be archived by the provisioner upon deletion of the PVC. - archiveOnDelete: false - - # If it exists and has 'delete' value, delete the directory. If it exists and has 'retain' value, save the directory. - # Overrides archiveOnDelete. - # Ignored if value not set. - onDelete: - - # Specifies a template for creating a directory path via PVC metadata's such as labels, annotations, name or namespace. - # Ignored if value not set. - pathPattern: - - # Set access mode - ReadWriteOnce, ReadOnlyMany or ReadWriteMany - accessModes: ReadWriteOnce - - # Storage class annotations - annotations: {} - -leaderElection: - # When set to false leader election will be disabled - enabled: true - -## For RBAC support: -rbac: - # Specifies whether RBAC resources should be created - create: true - -# If true, create & use Pod Security Policy resources -# https://kubernetes.io/docs/concepts/policy/pod-security-policy/ -podSecurityPolicy: - enabled: false - -# Deployment pod annotations -podAnnotations: {} - -## Set pod priorityClassName -# priorityClassName: "" - -serviceAccount: - # Specifies whether a ServiceAccount should be created - create: true - - # Annotations to add to the service account - annotations: {} - - # The name of the ServiceAccount to use. - # If not set and create is true, a name is generated using the fullname template - name: - -resources: {} - # limits: - # cpu: 100m - # memory: 128Mi - # requests: - # cpu: 100m - # memory: 128Mi - -# TODO: check before deploying the chart -nodeSelector: - cloud.google.com/gke-nodepool: default-pool - -tolerations: [] - -affinity: {} - -# Additional labels for any resource created -labels: {} diff --git a/tools/AutoTuner/nfs/nfs-pvc.yaml b/tools/AutoTuner/nfs/nfs-pvc.yaml deleted file mode 100644 index eac3a60343..0000000000 --- a/tools/AutoTuner/nfs/nfs-pvc.yaml +++ /dev/null @@ -1,11 +0,0 @@ -apiVersion: v1 -kind: PersistentVolumeClaim -metadata: - name: nfs-dynamic-pvc -spec: - storageClassName: nfs-client - accessModes: - - ReadWriteMany - resources: - requests: - storage: 1000Gi diff --git a/tools/AutoTuner/pyproject.toml b/tools/AutoTuner/pyproject.toml new file mode 100644 index 0000000000..f90a73257d --- /dev/null +++ b/tools/AutoTuner/pyproject.toml @@ -0,0 +1,31 @@ +[project] +name = "autotuner" +version = "0.0.1" +description = "This project provides a set of tools for tuning OpenROAD-flow-scripts parameter without user interference." +classifiers = [ + "Programming Language :: Python :: 3", + "License :: OSI Approved :: BSD 3-Clause", +] +readme = "README.md" +requires-python = ">= 3.8" +dynamic = ["dependencies", "optional-dependencies"] + +[project.scripts] +openroad_autotuner = "autotuner.distributed:main" + +[tool.setuptools.dynamic] +dependencies = { file = ["requirements.txt"] } +optional-dependencies.dev = { file = ["requirements-dev.txt"] } + +[build-system] +requires = ["setuptools", "setuptools_scm"] +build-backend = "setuptools.build_meta" + +[tool.setuptools.packages.find] +where = ["src/"] +include = [ + "autotuner*", +] + +[tool.setuptools] +include-package-data = true diff --git a/tools/AutoTuner/requirements-dev.txt b/tools/AutoTuner/requirements-dev.txt new file mode 100644 index 0000000000..7e66a17d49 --- /dev/null +++ b/tools/AutoTuner/requirements-dev.txt @@ -0,0 +1 @@ +black diff --git a/tools/AutoTuner/requirements.txt b/tools/AutoTuner/requirements.txt index 5bf65305cc..d4a4dbe5ff 100644 --- a/tools/AutoTuner/requirements.txt +++ b/tools/AutoTuner/requirements.txt @@ -1,11 +1,13 @@ -ray[default,tune]==2.9.3 +ray[default,tune]==2.43.0 ax-platform>=0.3.3,<=0.3.7 hyperopt==0.2.7 optuna==3.6.0 pandas>=2.0,<=2.2.1 bayesian-optimization==1.4.0 colorama==0.4.6 -tensorboard>=2.14.0,<=2.16.2 -protobuf==3.20.3 +tensorboard>=2.17.0 +protobuf>=5.26.1 SQLAlchemy==1.4.17 -urllib3<=1.26.15 +urllib3>=1.26.17 +matplotlib==3.10.0 +pyyaml==6.0.1 diff --git a/tools/AutoTuner/scripts/plot.py b/tools/AutoTuner/scripts/plot.py new file mode 100644 index 0000000000..aaddd29c6d --- /dev/null +++ b/tools/AutoTuner/scripts/plot.py @@ -0,0 +1,234 @@ +############################################################################# +## +## BSD 3-Clause License +## +## Copyright (c) 2019, The Regents of the University of California +## All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################### + +import glob +import json +import numpy as np +import pandas as pd +import matplotlib.pyplot as plt +import re +import os +import argparse +import sys + +# Only does plotting for AutoTunerBase variants +AT_REGEX = r"variant-AutoTunerBase-([\w-]+)-\w+" + +# TODO: Make sure the distributed.py METRIC variable is consistent with this, single source of truth. +METRIC = "metric" + +cur_dir = os.path.dirname(os.path.abspath(__file__)) +root_dir = os.path.join(cur_dir, "../../../") +os.chdir(root_dir) + + +def load_dir(dir: str) -> pd.DataFrame: + """ + Load and merge progress, parameters, and metrics data from a specified directory. + This function searches for `progress.csv`, `params.json`, and `metrics.json` files within the given directory, + concatenates the data, and merges them into a single pandas DataFrame. + Args: + dir (str): The directory path containing the subdirectories with `progress.csv`, `params.json`, and `metrics.json` files. + Returns: + pd.DataFrame: A DataFrame containing the merged data from the progress, parameters, and metrics files. + """ + + # Concatenate progress DFs + progress_csvs = glob.glob(f"{dir}/*/progress.csv") + if len(progress_csvs) == 0: + print("No progress.csv files found.") + sys.exit(1) + progress_df = pd.concat([pd.read_csv(f) for f in progress_csvs]) + + # Concatenate params.json & metrics.json file + params = [] + failed = [] + for params_fname in glob.glob(f"{dir}/*/params.json"): + metrics_fname = params_fname.replace("params.json", "metrics.json").replace( + "ray", "or-0" + ) + try: + with open(params_fname, "r") as f: + _dict = json.load(f) + _dict["trial_id"] = re.search(AT_REGEX, params_fname).group(1) + with open(metrics_fname, "r") as f: + metrics = json.load(f) + ws = metrics["finish"]["timing__setup__ws"] + metrics["worst_slack"] = ws + _dict.update(metrics) + params.append(_dict) + except Exception as e: + failed.append(metrics_fname) + print("Failed to load", metrics_fname) + print(e) + continue + + # Merge all dataframe + params_df = pd.DataFrame(params) + try: + progress_df = progress_df.merge(params_df, on="trial_id") + except KeyError: + print( + "Unable to merge DFs due to missing trial_id in params.json (possibly due to failed trials.)" + ) + sys.exit(1) + + # Print failed, if any + if failed: + failed_files = "\n".join(failed) + print(f"Failed to load {len(failed)} files:\n{failed_files}") + return progress_df + + +def preprocess(df: pd.DataFrame) -> pd.DataFrame: + """ + Preprocess the input DataFrame by renaming columns, removing unnecessary columns, + filtering out invalid rows, and normalizing the timestamp. + Args: + df (pd.DataFrame): The input DataFrame to preprocess. + Returns: + pd.DataFrame: The preprocessed DataFrame with renamed columns, removed columns, + filtered rows, and normalized timestamp. + """ + + cols_to_remove = [ + "done", + "training_iteration", + "date", + "pid", + "hostname", + "node_ip", + "time_since_restore", + "time_total_s", + "iterations_since_restore", + ] + rename_dict = { + "time_this_iter_s": "runtime", + "_SDC_CLK_PERIOD": "clk_period", # param + } + try: + df = df.rename(columns=rename_dict) + df = df.drop(columns=cols_to_remove) + df = df[df[METRIC] != 9e99] + df["timestamp"] -= df["timestamp"].min() + return df + except KeyError as e: + print( + f"KeyError: {e} in the DataFrame. Dataframe does not contain necessary columns." + ) + sys.exit(1) + + +def plot(df: pd.DataFrame, key: str, dir: str): + """ + Plots a scatter plot with a linear fit and a box plot for a specified key from a DataFrame. + Args: + df (pd.DataFrame): The DataFrame containing the data to plot. + key (str): The column name in the DataFrame to plot. + dir (str): The directory where the plots will be saved. The directory must exist. + Returns: + None + """ + + assert os.path.exists(dir), f"Directory {dir} does not exist." + # Plot box plot and time series plot for key + fig, ax = plt.subplots(1, figsize=(15, 10)) + ax.scatter(df["timestamp"], df[key]) + ax.set_xlabel("Time (s)") + ax.set_ylabel(key) + ax.set_title(f"{key} vs Time") + + try: + coeff = np.polyfit(df["timestamp"], df[key], 1) + poly_func = np.poly1d(coeff) + ax.plot( + df["timestamp"], + poly_func(df["timestamp"]), + "r--", + label=f"y={coeff[0]:.2f}x+{coeff[1]:.2f}", + ) + ax.legend() + except np.linalg.LinAlgError: + print("Cannot fit a line to the data, plotting only scatter plot.") + + fig.savefig(f"{dir}/{key}.png") + + plt.figure(figsize=(15, 10)) + plt.boxplot(df[key]) + plt.ylabel(key) + plt.title(f"{key} Boxplot") + plt.savefig(f"{dir}/{key}-boxplot.png") + + +def main(platform: str, design: str, experiment: str): + """ + Main function to process results from a specified directory and plot the results. + Args: + platform (str): The platform name. + design (str): The design name. + experiment (str): The experiment name. + Returns: + None + """ + + results_dir = os.path.join( + root_dir, f"./flow/logs/{platform}/{design}/{experiment}" + ) + img_dir = os.path.join( + root_dir, f"./flow/reports/images/{platform}/{design}/{experiment}" + ) + print("Processing results from", results_dir) + os.makedirs(img_dir, exist_ok=True) + df = load_dir(results_dir) + df = preprocess(df) + keys = [METRIC] + ["runtime", "clk_period", "worst_slack"] + + # Plot only if more than one entry + if len(df) < 2: + print("Less than 2 entries, skipping plotting.") + sys.exit(0) + for key in keys: + plot(df, key, img_dir) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Plot AutoTuner results.") + parser.add_argument("--platform", type=str, help="Platform name.", required=True) + parser.add_argument("--design", type=str, help="Design name.", required=True) + parser.add_argument( + "--experiment", type=str, help="Experiment name.", required=True + ) + args = parser.parse_args() + main(platform=args.platform, design=args.design, experiment=args.experiment) diff --git a/tools/AutoTuner/src/autotuner/__init__.py b/tools/AutoTuner/src/autotuner/__init__.py new file mode 100644 index 0000000000..2703c2c57d --- /dev/null +++ b/tools/AutoTuner/src/autotuner/__init__.py @@ -0,0 +1,4 @@ +""" +AutoTuner module integrating Ray Tune and Vizier framework +for ORFS parameters optimization. +""" diff --git a/tools/AutoTuner/src/autotuner/distributed.py b/tools/AutoTuner/src/autotuner/distributed.py index fc84c9a05a..2d87b710ac 100644 --- a/tools/AutoTuner/src/autotuner/distributed.py +++ b/tools/AutoTuner/src/autotuner/distributed.py @@ -1,43 +1,73 @@ +############################################################################# +## +## BSD 3-Clause License +## +## Copyright (c) 2019, The Regents of the University of California +## All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################### + """ This scripts handles sweeping and tuning of OpenROAD-flow-scripts parameters. Dependencies are documented in pip format at distributed-requirements.txt For both sweep and tune modes: - python3 distributed.py -h + openroad_autotuner -h Note: the order of the parameters matter. Arguments --design, --platform and --config are always required and should precede the . AutoTuner: - python3 distributed.py tune -h - python3 distributed.py --design gcd --platform sky130hd \ + openroad_autotuner tune -h + openroad_autotuner --design gcd --platform sky130hd \ --config ../designs/sky130hd/gcd/autotuner.json \ tune Example: Parameter sweeping: - python3 distributed.py sweep -h + openroad_autotuner sweep -h Example: - python3 distributed.py --design gcd --platform sky130hd \ - --config distributed-sweep-example.json \ - sweep + openroad_autotuner --design gcd --platform sky130hd \ + --config distributed-sweep-example.json \ + sweep """ import argparse import json import os -import re import sys -import glob -import subprocess import random -from datetime import datetime -from multiprocessing import cpu_count -from subprocess import run from itertools import product -from collections import namedtuple from uuid import uuid4 as uuid +from collections import namedtuple +from multiprocessing import cpu_count import numpy as np import torch @@ -55,15 +85,27 @@ from ax.service.ax_client import AxClient -DATE = datetime.now().strftime("%Y-%m-%d-%H-%M-%S") -ORFS_URL = "https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts" -FASTROUTE_TCL = "fastroute.tcl" -CONSTRAINTS_SDC = "constraint.sdc" -METRIC = "minimum" +from autotuner.utils import ( + openroad, + consumer, + parse_config, + read_config, + read_metrics, + prepare_ray_server, + CONSTRAINTS_SDC, + FASTROUTE_TCL, +) + +# Name of the final metric +METRIC = "metric" +# The worst of optimized metric ERROR_METRIC = 9e99 +# Path to the FLOW_HOME directory ORFS_FLOW_DIR = os.path.abspath( os.path.join(os.path.dirname(__file__), "../../../../flow") ) +# Global variable for args +args = None class AutoTunerBase(tune.Trainable): @@ -76,24 +118,53 @@ def setup(self, config): Setup current experiment step. """ # We create the following directory structure: - # 1/ 2/ 3/ 4/ 5/ 6/ - # ////-DATE// - repo_dir = os.getcwd() + "/../" * 6 - self.repo_dir = os.path.abspath(repo_dir) - self.parameters = parse_config(config, path=os.getcwd()) + # 1/ 2/ 3/ 4/ 5/ + # //// + self.repo_dir = os.path.abspath(LOCAL_DIR + "/../" * 4) + self.parameters = parse_config( + config=config, + base_dir=self.repo_dir, + platform=args.platform, + sdc_original=SDC_ORIGINAL, + constraints_sdc=CONSTRAINTS_SDC, + fr_original=FR_ORIGINAL, + fastroute_tcl=FASTROUTE_TCL, + path=os.getcwd(), + ) self.step_ = 0 self.variant = f"variant-{self.__class__.__name__}-{self.trial_id}-or" + # Do a valid config check here, since we still have the config in a + # dict vs. having to scan through the parameter string later + self.is_valid_config = self._is_valid_config(config) def step(self): """ Run step experiment and compute its score. """ - metrics_file = openroad(self.repo_dir, self.parameters, self.variant) + + # if not a valid config, then don't run and pass back an error + if not self.is_valid_config: + return {METRIC: ERROR_METRIC, "effective_clk_period": "-", "num_drc": "-"} + self._variant = f"{self.variant}-{self.step_}" + metrics_file = openroad( + args=args, + base_dir=self.repo_dir, + parameters=self.parameters, + flow_variant=self._variant, + install_path=INSTALL_PATH, + ) self.step_ += 1 - score = self.evaluate(self.read_metrics(metrics_file)) + (score, effective_clk_period, num_drc, die_area) = self.evaluate( + read_metrics(metrics_file, args.stop_stage) + ) # Feed the score back to Tune. # return must match 'metric' used in tune.run() - return {METRIC: score} + return { + METRIC: score, + "effective_clk_period": effective_clk_period, + "num_drc": num_drc, + "die_area": die_area, + } def evaluate(self, metrics): """ @@ -104,51 +175,39 @@ def evaluate(self, metrics): error = "ERR" in metrics.values() not_found = "N/A" in metrics.values() if error or not_found: - return ERROR_METRIC - gamma = (metrics["clk_period"] - metrics["worst_slack"]) / 10 - score = metrics["clk_period"] - metrics["worst_slack"] - score = score * (self.step_ / 100) ** (-1) + gamma * metrics["num_drc"] - return score - - @classmethod - def read_metrics(cls, file_name): + return (ERROR_METRIC, "-", "-", "-") + effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] + num_drc = metrics["num_drc"] + gamma = effective_clk_period / 10 + score = effective_clk_period + score = score * (100 / self.step_) + gamma * num_drc + return (score, effective_clk_period, num_drc, metrics["die_area"]) + + def _is_valid_config(self, config): """ - Collects metrics to evaluate the user-defined objective function. + Checks dependent parameters and returns False if we violate + a dependency. That way, we don't end up running an incompatible run """ - with open(file_name) as file: - data = json.load(file) - clk_period = 9999999 - worst_slack = "ERR" - wirelength = "ERR" - num_drc = "ERR" - total_power = "ERR" - core_util = "ERR" - final_util = "ERR" - for stage, value in data.items(): - if stage == "constraints" and len(value["clocks__details"]) > 0: - clk_period = float(value["clocks__details"][0].split()[1]) - if stage == "floorplan" and "design__instance__utilization" in value: - core_util = value["design__instance__utilization"] - if stage == "detailedroute" and "route__drc_errors" in value: - num_drc = value["route__drc_errors"] - if stage == "detailedroute" and "route__wirelength" in value: - wirelength = value["route__wirelength"] - if stage == "finish" and "timing__setup__ws" in value: - worst_slack = value["timing__setup__ws"] - if stage == "finish" and "power__total" in value: - total_power = value["power__total"] - if stage == "finish" and "design__instance__utilization" in value: - final_util = value["design__instance__utilization"] - ret = { - "clk_period": clk_period, - "worst_slack": worst_slack, - "wirelength": wirelength, - "num_drc": num_drc, - "total_power": total_power, - "core_util": core_util, - "final_util": final_util, - } - return ret + + ret_val = True + ret_val &= self._is_valid_padding(config) + return ret_val + + def _is_valid_padding(self, config): + """Returns True if global padding >= detail padding""" + + if ( + "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT" in config + and "CELL_PAD_IN_SITES_DETAIL_PLACEMENT" in config + ): + global_padding = config["CELL_PAD_IN_SITES_GLOBAL_PLACEMENT"] + detail_padding = config["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"] + if global_padding < detail_padding: + print( + f"[WARN TUN-0032] CELL_PAD_IN_SITES_DETAIL_PLACEMENT ({detail_padding}) cannot be greater than CELL_PAD_IN_SITES_GLOBAL_PLACEMENT ({global_padding})" + ) + return False + return True class PPAImprov(AutoTunerBase): @@ -188,462 +247,14 @@ def percent(x_1, x_2): def evaluate(self, metrics): error = "ERR" in metrics.values() or "ERR" in reference.values() not_found = "N/A" in metrics.values() or "N/A" in reference.values() - print("Metrics", metrics.values()) - print("Reference", reference.values()) - print(error, not_found) if error or not_found: - return ERROR_METRIC + return (ERROR_METRIC, "-", "-", "-") ppa = self.get_ppa(metrics) gamma = ppa / 10 score = ppa * (self.step_ / 100) ** (-1) + (gamma * metrics["num_drc"]) - return score - - -def read_config(file_name): - """ - Please consider inclusive, exclusive - Most type uses [min, max) - But, Quantization makes the upper bound inclusive. - e.g., qrandint and qlograndint uses [min, max] - step value is used for quantized type (e.g., quniform). Otherwise, write 0. - When min==max, it means the constant value - """ - - def read(path): - # if file path does not exist, return empty string - print(os.path.abspath(path)) - if not os.path.isfile(os.path.abspath(path)): - return "" - with open(os.path.abspath(path), "r") as file: - ret = file.read() - return ret - - def read_sweep(this): - return [*this["minmax"], this["step"]] - - def apply_condition(config, data): - # TODO: tune.sample_from only supports random search algorithm. - # To make conditional parameter for the other algorithms, different - # algorithms should take different methods (will be added) - if args.algorithm != "random": - return config - dp_pad_min = data["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"]["minmax"][0] - dp_pad_step = data["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"]["step"] - if dp_pad_step == 1: - config["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"] = tune.sample_from( - lambda spec: np.random.randint( - dp_pad_min, spec.config.CELL_PAD_IN_SITES_GLOBAL_PLACEMENT + 1 - ) - ) - if dp_pad_step > 1: - config["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"] = tune.sample_from( - lambda spec: random.randrange( - dp_pad_min, - spec.config.CELL_PAD_IN_SITES_GLOBAL_PLACEMENT + 1, - dp_pad_step, - ) - ) - return config - - def read_tune(this): - min_, max_ = this["minmax"] - if min_ == max_: - # Returning a choice of a single element allow pbt algorithm to - # work. pbt does not accept single values as tunable. - return tune.choice([min_, max_]) - if this["type"] == "int": - if this["step"] == 1: - return tune.randint(min_, max_) - return tune.choice(np.ndarray.tolist(np.arange(min_, max_, this["step"]))) - if this["type"] == "float": - if this["step"] == 0: - return tune.uniform(min_, max_) - return tune.choice(np.ndarray.tolist(np.arange(min_, max_, this["step"]))) - return None - - def read_tune_ax(name, this): - """ - Ax format: https://ax.dev/versions/0.3.7/api/service.html - """ - dict_ = dict(name=name) - if "minmax" not in this: - return None - min_, max_ = this["minmax"] - if min_ == max_: - dict_["type"] = "fixed" - dict_["value"] = min_ - elif this["type"] == "int": - if this["step"] == 1: - dict_["type"] = "range" - dict_["bounds"] = [min_, max_] - dict_["value_type"] = "int" - else: - dict_["type"] = "choice" - dict_["values"] = tune.randint(min_, max_, this["step"]) - dict_["value_type"] = "int" - elif this["type"] == "float": - if this["step"] == 1: - dict_["type"] = "choice" - dict_["values"] = tune.choice( - np.ndarray.tolist(np.arange(min_, max_, this["step"])) - ) - dict_["value_type"] = "float" - else: - dict_["type"] = "range" - dict_["bounds"] = [min_, max_] - dict_["value_type"] = "float" - return dict_ - - def read_tune_pbt(name, this): - """ - PBT format: https://docs.ray.io/en/releases-2.9.3/tune/examples/pbt_guide.html - Note that PBT does not support step values. - """ - if "minmax" not in this: - return None - min_, max_ = this["minmax"] - if min_ == max_: - return ray.tune.choice([min_, max_]) - if this["type"] == "int": - return ray.tune.randint(min_, max_) - if this["type"] == "float": - return ray.tune.uniform(min_, max_) - - # Check file exists and whether it is a valid JSON file. - assert os.path.isfile(file_name), f"File {file_name} not found." - try: - with open(file_name) as file: - data = json.load(file) - except json.JSONDecodeError: - raise ValueError(f"Invalid JSON file: {file_name}") - sdc_file = "" - fr_file = "" - if args.mode == "tune" and args.algorithm == "ax": - config = list() - else: - config = dict() - for key, value in data.items(): - if key == "best_result": - continue - if key == "_SDC_FILE_PATH" and value != "": - if sdc_file != "": - print("[WARNING TUN-0004] Overwriting SDC base file.") - sdc_file = read(f"{os.path.dirname(file_name)}/{value}") - continue - if key == "_FR_FILE_PATH" and value != "": - if fr_file != "": - print("[WARNING TUN-0005] Overwriting FastRoute base file.") - fr_file = read(f"{os.path.dirname(file_name)}/{value}") - continue - if not isinstance(value, dict): - # To take care of empty values like _FR_FILE_PATH - if args.mode == "tune" and args.algorithm == "ax": - param_dict = read_tune_ax(key, value) - if param_dict: - config.append(param_dict) - elif args.mode == "tune" and args.algorithm == "pbt": - param_dict = read_tune_pbt(key, value) - if param_dict: - config[key] = param_dict - else: - config[key] = value - elif args.mode == "sweep": - config[key] = read_sweep(value) - elif args.mode == "tune" and args.algorithm == "ax": - config.append(read_tune_ax(key, value)) - elif args.mode == "tune" and args.algorithm == "pbt": - config[key] = read_tune_pbt(key, value) - elif args.mode == "tune": - config[key] = read_tune(value) - if args.mode == "tune": - config = apply_condition(config, data) - return config, sdc_file, fr_file - - -def parse_flow_variables(): - """ - Parse the flow variables from source - - Code: Makefile `vars` target output - - TODO: Tests. - - Output: - - flow_variables: set of flow variables - """ - cur_path = os.path.dirname(os.path.realpath(__file__)) - - # first, generate vars.tcl - makefile_path = os.path.join(cur_path, "../../../../flow/") - initial_path = os.path.abspath(os.getcwd()) - os.chdir(makefile_path) - result = subprocess.run(["make", "vars", f"PLATFORM={args.platform}"]) - if result.returncode != 0: - print(f"[ERROR TUN-0018] Makefile failed with error code {result.returncode}.") - sys.exit(1) - if not os.path.exists("vars.tcl"): - print(f"[ERROR TUN-0019] Makefile did not generate vars.tcl.") - sys.exit(1) - os.chdir(initial_path) - - # for code parsing, you need to parse from both scripts and vars.tcl file. - pattern = r"(?:::)?env\((.*?)\)" - files = glob.glob(os.path.join(cur_path, "../../../../flow/scripts/*.tcl")) - files.append(os.path.join(cur_path, "../../../../flow/vars.tcl")) - variables = set() - for file in files: - with open(file) as fp: - matches = re.findall(pattern, fp.read()) - for match in matches: - for variable in match.split("\n"): - variables.add(variable.strip().upper()) - return variables - - -def parse_config(config, path=os.getcwd()): - """ - Parse configuration received from tune into make variables. - """ - options = "" - sdc = {} - fast_route = {} - flow_variables = parse_flow_variables() - for key, value in config.items(): - # Keys that begin with underscore need special handling. - if key.startswith("_"): - # Variables to be injected into fastroute.tcl - if key.startswith("_FR_"): - fast_route[key.replace("_FR_", "", 1)] = value - # Variables to be injected into constraints.sdc - elif key.startswith("_SDC_"): - sdc[key.replace("_SDC_", "", 1)] = value - # Special substitution cases - elif key == "_PINS_DISTANCE": - options += f' PLACE_PINS_ARGS="-min_distance {value}"' - elif key == "_SYNTH_FLATTEN": - print( - "[WARNING TUN-0013] Non-flatten the designs are not " - "fully supported, ignoring _SYNTH_FLATTEN parameter." - ) - # Default case is VAR=VALUE - else: - # FIXME there is no robust way to get this metainformation from - # ORFS about the variables, so disable this code for now. - - # Sanity check: ignore all flow variables that are not tunable - # if key not in flow_variables: - # print(f"[ERROR TUN-0017] Variable {key} is not tunable.") - # sys.exit(1) - options += f" {key}={value}" - if bool(sdc): - write_sdc(sdc, path) - options += f" SDC_FILE={path}/{CONSTRAINTS_SDC}" - if bool(fast_route): - write_fast_route(fast_route, path) - options += f" FASTROUTE_TCL={path}/{FASTROUTE_TCL}" - return options - - -def write_sdc(variables, path): - """ - Create a SDC file with parameters for current tuning iteration. - """ - # Handle case where the reference file does not exist - if SDC_ORIGINAL == "": - print("[ERROR TUN-0020] No SDC reference file provided.") - sys.exit(1) - new_file = SDC_ORIGINAL - for key, value in variables.items(): - if key == "CLK_PERIOD": - if new_file.find("set clk_period") != -1: - new_file = re.sub( - r"set clk_period .*\n(.*)", f"set clk_period {value}\n\\1", new_file - ) - else: - new_file = re.sub( - r"-period [0-9\.]+ (.*)", f"-period {value} \\1", new_file - ) - new_file = re.sub(r"-waveform [{}\s0-9\.]+[\s|\n]", "", new_file) - elif key == "UNCERTAINTY": - if new_file.find("set uncertainty") != -1: - new_file = re.sub( - r"set uncertainty .*\n(.*)", - f"set uncertainty {value}\n\\1", - new_file, - ) - else: - new_file += f"\nset uncertainty {value}\n" - elif key == "IO_DELAY": - if new_file.find("set io_delay") != -1: - new_file = re.sub( - r"set io_delay .*\n(.*)", f"set io_delay {value}\n\\1", new_file - ) - else: - new_file += f"\nset io_delay {value}\n" - file_name = path + f"/{CONSTRAINTS_SDC}" - with open(file_name, "w") as file: - file.write(new_file) - return file_name - - -def write_fast_route(variables, path): - """ - Create a FastRoute Tcl file with parameters for current tuning iteration. - """ - # Handle case where the reference file does not exist (asap7 doesn't have reference) - if FR_ORIGINAL == "" and args.platform != "asap7": - print("[ERROR TUN-0021] No FastRoute Tcl reference file provided.") - sys.exit(1) - layer_cmd = "set_global_routing_layer_adjustment" - new_file = FR_ORIGINAL - for key, value in variables.items(): - if key.startswith("LAYER_ADJUST"): - layer = key.lstrip("LAYER_ADJUST") - # If there is no suffix (i.e., layer name) apply adjust to all - # layers. - if layer == "": - new_file += "\nset_global_routing_layer_adjustment" - new_file += " $::env(MIN_ROUTING_LAYER)" - new_file += "-$::env(MAX_ROUTING_LAYER)" - new_file += f" {value}" - elif re.search(f"{layer_cmd}.*{layer}", new_file): - new_file = re.sub( - f"({layer_cmd}.*{layer}).*\n(.*)", f"\\1 {value}\n\\2", new_file - ) - else: - new_file += f"\n{layer_cmd} {layer} {value}\n" - elif key == "GR_SEED": - new_file += f"\nset_global_routing_random -seed {value}\n" - file_name = path + f"/{FASTROUTE_TCL}" - with open(file_name, "w") as file: - file.write(new_file) - return file_name - - -def run_command(cmd, timeout=None, stderr_file=None, stdout_file=None, fail_fast=False): - """ - Wrapper for subprocess.run - Allows to run shell command, control print and exceptions. - """ - process = run( - cmd, timeout=timeout, capture_output=True, text=True, check=False, shell=True - ) - if stderr_file is not None and process.stderr != "": - with open(stderr_file, "a") as file: - file.write(f"\n\n{cmd}\n{process.stderr}") - if stdout_file is not None and process.stdout != "": - with open(stdout_file, "a") as file: - file.write(f"\n\n{cmd}\n{process.stdout}") - if args.verbose >= 1: - print(process.stderr) - if args.verbose >= 2: - print(process.stdout) - - if fail_fast and process.returncode != 0: - raise RuntimeError - - -@ray.remote -def openroad_distributed(repo_dir, config, path): - """Simple wrapper to run openroad distributed with Ray.""" - config = parse_config(config) - openroad(repo_dir, config, str(uuid()), path=path) - - -def openroad(base_dir, parameters, flow_variant, path=""): - """ - Run OpenROAD-flow-scripts with a given set of parameters. - """ - # Make sure path ends in a slash, i.e., is a folder - flow_variant = f"{args.experiment}/{flow_variant}" - if path != "": - log_path = f"{path}/{flow_variant}/" - report_path = log_path.replace("logs", "reports") - run_command(f"mkdir -p {log_path}") - run_command(f"mkdir -p {report_path}") - else: - log_path = report_path = os.getcwd() + "/" - - export_command = f"export PATH={INSTALL_PATH}/OpenROAD/bin" - export_command += f":{INSTALL_PATH}/yosys/bin:$PATH" - export_command += " && " - - make_command = export_command - make_command += f"make -C {base_dir}/flow DESIGN_CONFIG=designs/" - make_command += f"{args.platform}/{args.design}/config.mk" - make_command += f" PLATFORM={args.platform}" - make_command += f" FLOW_VARIANT={flow_variant} {parameters}" - make_command += f" EQUIVALENCE_CHECK=0" - make_command += f" NPROC={args.openroad_threads} SHELL=bash" - run_command( - make_command, - timeout=args.timeout, - stderr_file=f"{log_path}error-make-finish.log", - stdout_file=f"{log_path}make-finish-stdout.log", - ) - - metrics_file = os.path.join(report_path, "metrics.json") - metrics_command = export_command - metrics_command += f"{base_dir}/flow/util/genMetrics.py -x" - metrics_command += f" -v {flow_variant}" - metrics_command += f" -d {args.design}" - metrics_command += f" -p {args.platform}" - metrics_command += f" -o {metrics_file}" - run_command( - metrics_command, - stderr_file=f"{log_path}error-metrics.log", - stdout_file=f"{log_path}metrics-stdout.log", - ) - - return metrics_file - - -def clone(path): - """ - Clone base repo in the remote machine. Only used for Kubernetes at GCP. - """ - if args.git_clone: - run_command(f"rm -rf {path}") - if not os.path.isdir(f"{path}/.git"): - git_command = "git clone --depth 1 --recursive --single-branch" - git_command += f" {args.git_clone_args}" - git_command += f" --branch {args.git_orfs_branch}" - git_command += f" {args.git_url} {path}" - run_command(git_command) - - -def build(base, install): - """ - Build OpenROAD, Yosys and other dependencies. - """ - build_command = f'cd "{base}"' - if args.git_clean: - build_command += " && git clean -xdf tools" - build_command += " && git submodule foreach --recursive git clean -xdf" - if ( - args.git_clean - or not os.path.isfile(f"{install}/OpenROAD/bin/openroad") - or not os.path.isfile(f"{install}/yosys/bin/yosys") - ): - build_command += ' && bash -ic "./build_openroad.sh' - # Some GCP machines have 200+ cores. Let's be reasonable... - build_command += f" --local --nice --threads {min(32, cpu_count())}" - if args.git_latest: - build_command += " --latest" - build_command += f' {args.build_args}"' - run_command(build_command) - - -@ray.remote -def setup_repo(base): - """ - Clone ORFS repository and compile binaries. - """ - print(f"[INFO TUN-0000] Remote folder: {base}") - install = f"{base}/tools/install" - if args.server is not None: - clone(base) - build(base, install) - return install + effective_clk_period = metrics["clk_period"] - metrics["worst_slack"] + num_drc = metrics["num_drc"] + return (score, effective_clk_period, num_drc, metrics["die_area"]) def parse_arguments(): @@ -697,62 +308,19 @@ def parse_arguments(): default=None, help="Time limit (in hours) for each trial run. Default is no limit.", ) - tune_parser.add_argument( - "--resume", action="store_true", help="Resume previous run." - ) - - # Setup - parser.add_argument( - "--git_clean", - action="store_true", - help="Clean binaries and build files." - " WARNING: may lose previous data." - " Use carefully.", - ) - parser.add_argument( - "--git_clone", - action="store_true", - help="Force new git clone." - " WARNING: may lose previous data." - " Use carefully.", - ) - parser.add_argument( - "--git_clone_args", - type=str, - metavar="", - default="", - help="Additional git clone arguments.", - ) - parser.add_argument( - "--git_latest", action="store_true", help="Use latest version of OpenROAD app." - ) parser.add_argument( - "--git_or_branch", + "--stop_stage", type=str, metavar="", - default="", - help="OpenROAD app branch to use.", + choices=["floorplan", "place", "cts", "globalroute", "route", "finish"], + default="finish", + help="Name of the stage to stop after. Default is finish.", ) - parser.add_argument( - "--git_orfs_branch", - type=str, - metavar="", - default="master", - help="OpenROAD-flow-scripts branch to use.", - ) - parser.add_argument( - "--git_url", - type=str, - metavar="", - default=ORFS_URL, - help="OpenROAD-flow-scripts repo URL to use.", - ) - parser.add_argument( - "--build_args", - type=str, - metavar="", - default="", - help="Additional arguments given to ./build_openroad.sh.", + tune_parser.add_argument( + "--resume", + action="store_true", + help="Resume previous run. Note that you must also set a unique experiment\ + name identifier via `--experiment NAME` to be able to resume.", ) # ML @@ -786,8 +354,8 @@ def parse_arguments(): ) tune_parser.add_argument( "--resources_per_trial", - type=int, - metavar="", + type=float, + metavar="", default=1, help="Number of CPUs to request for each tuning job.", ) @@ -852,51 +420,66 @@ def parse_arguments(): " training stderr\n\t2: also print training stdout.", ) - arguments = parser.parse_args() - if arguments.mode == "tune": - arguments.algorithm = arguments.algorithm.lower() + args = parser.parse_args() + if args.mode == "tune": + args.algorithm = args.algorithm.lower() # Validation of arguments - if arguments.eval == "ppa-improv" and arguments.reference is None: + if args.eval == "ppa-improv" and args.reference is None: print( '[ERROR TUN-0006] The argument "--eval ppa-improv"' ' requires that "--reference " is also given.' ) sys.exit(7) - arguments.experiment += f"-{arguments.mode}-{DATE}" + # Check for experiment name and resume flag. + if args.resume and args.experiment == "test": + print( + '[ERROR TUN-0031] The flag "--resume"' + ' requires that "--experiment NAME" is also given.' + ) + sys.exit(1) - if arguments.timeout is not None: - arguments.timeout = round(arguments.timeout * 3600) + # If the experiment name is the default, add a UUID to the end. + if args.experiment == "test": + id = str(uuid())[:8] + args.experiment = f"{args.mode}-{id}" + else: + args.experiment += f"-{args.mode}" - return arguments + if args.timeout is not None: + args.timeout = round(args.timeout * 3600) + return args -def set_algorithm(experiment_name, config): + +def set_algorithm( + algorithm_name, experiment_name, best_params, seed, perturbation, jobs, config +): """ Configure search algorithm. """ # Pre-set seed if user sets seed to 0 - if args.seed == 0: + if seed == 0: print( "Warning: you have chosen not to set a seed. Do you wish to continue? (y/n)" ) if input().lower() != "y": sys.exit(0) - args.seed = None + seed = None else: - torch.manual_seed(args.seed) - np.random.seed(args.seed) - random.seed(args.seed) + torch.manual_seed(seed) + np.random.seed(seed) + random.seed(seed) - if args.algorithm == "hyperopt": + if algorithm_name == "hyperopt": algorithm = HyperOptSearch( points_to_evaluate=best_params, - random_state_seed=args.seed, + random_state_seed=seed, ) - elif args.algorithm == "ax": + elif algorithm_name == "ax": ax_client = AxClient( enforce_sequential_optimization=False, - random_seed=args.seed, + random_seed=seed, ) AxClientMetric = namedtuple("AxClientMetric", "minimize") ax_client.create_experiment( @@ -905,25 +488,25 @@ def set_algorithm(experiment_name, config): objectives={METRIC: AxClientMetric(minimize=True)}, ) algorithm = AxSearch(ax_client=ax_client, points_to_evaluate=best_params) - elif args.algorithm == "optuna": - algorithm = OptunaSearch(points_to_evaluate=best_params, seed=args.seed) - elif args.algorithm == "pbt": - print("Warning: PBT does not support seed values. args.seed will be ignored.") + elif algorithm_name == "optuna": + algorithm = OptunaSearch(points_to_evaluate=best_params, seed=seed) + elif algorithm_name == "pbt": + print("Warning: PBT does not support seed values. seed will be ignored.") algorithm = PopulationBasedTraining( time_attr="training_iteration", - perturbation_interval=args.perturbation, + perturbation_interval=perturbation, hyperparam_mutations=config, synch=True, ) - elif args.algorithm == "random": + elif algorithm_name == "random": algorithm = BasicVariantGenerator( - max_concurrent=args.jobs, - random_state=args.seed, + max_concurrent=jobs, + random_state=seed, ) # A wrapper algorithm for limiting the number of concurrent trials. - if args.algorithm not in ["random", "pbt"]: - algorithm = ConcurrencyLimiter(algorithm, max_concurrent=args.jobs) + if algorithm_name not in ["random", "pbt"]: + algorithm = ConcurrencyLimiter(algorithm, max_concurrent=jobs) return algorithm @@ -966,17 +549,6 @@ def save_best(results): print(f"[INFO TUN-0003] Best parameters written to {new_best_path}") -@ray.remote -def consumer(queue): - """consumer""" - while not queue.empty(): - next_item = queue.get() - name = next_item[1] - print(f"[INFO TUN-0007] Scheduling run for parameter {name}.") - ray.get(openroad_distributed.remote(*next_item)) - print(f"[INFO TUN-0008] Finished run for parameter {name}.") - - def sweep(): """Run sweep of parameters""" if args.server is not None: @@ -985,7 +557,7 @@ def sweep(): # //// repo_dir = os.path.abspath(LOCAL_DIR + "/../" * 4) else: - repo_dir = os.path.abspath("../") + repo_dir = os.path.abspath(os.path.join(ORFS_FLOW_DIR, "..")) print(f"[INFO TUN-0012] Log folder {LOCAL_DIR}.") queue = Queue() parameter_list = list() @@ -1002,58 +574,40 @@ def sweep(): temp = dict() for value in parameter: temp.update(value) - print(temp) - queue.put([repo_dir, temp, LOCAL_DIR]) + queue.put([args, repo_dir, temp, SDC_ORIGINAL, FR_ORIGINAL, INSTALL_PATH]) workers = [consumer.remote(queue) for _ in range(args.jobs)] print("[INFO TUN-0009] Waiting for results.") ray.get(workers) print("[INFO TUN-0010] Sweep complete.") -if __name__ == "__main__": +def main(): + global args, SDC_ORIGINAL, FR_ORIGINAL, LOCAL_DIR, INSTALL_PATH, ORFS_FLOW_DIR, config_dict, reference, best_params args = parse_arguments() # Read config and original files before handling where to run in case we # need to upload the files. - config_dict, SDC_ORIGINAL, FR_ORIGINAL = read_config(os.path.abspath(args.config)) + config_dict, SDC_ORIGINAL, FR_ORIGINAL = read_config( + os.path.abspath(args.config), args.mode, getattr(args, "algorithm", None) + ) - # Connect to remote Ray server if any, otherwise will run locally - if args.server is not None: - # At GCP we have a NFS folder that is present for all worker nodes. - # This allows to build required binaries once. We clone, build and - # store intermediate files at LOCAL_DIR. - with open(args.config) as config_file: - LOCAL_DIR = "/shared-data/autotuner" - LOCAL_DIR += f"-orfs-{args.git_orfs_branch}" - if args.git_or_branch != "": - LOCAL_DIR += f"-or-{args.git_or_branch}" - if args.git_latest: - LOCAL_DIR += "-or-latest" - # Connect to ray server before first remote execution. - ray.init(f"ray://{args.server}:{args.port}") - # Remote functions return a task id and are non-blocking. Since we - # need the setup repo before continuing, we call ray.get() to wait - # for its completion. - INSTALL_PATH = ray.get(setup_repo.remote(LOCAL_DIR)) - LOCAL_DIR += f"/flow/logs/{args.platform}/{args.design}" - print("[INFO TUN-0001] NFS setup completed.") - else: - # For local runs, use the same folder as other ORFS utilities. - ORFS_FLOW_DIR = os.path.abspath( - os.path.join(os.path.dirname(__file__), "../../../../flow") - ) - os.chdir(ORFS_FLOW_DIR) - LOCAL_DIR = f"logs/{args.platform}/{args.design}" - LOCAL_DIR = os.path.abspath(LOCAL_DIR) - INSTALL_PATH = os.path.abspath("../tools/install") + LOCAL_DIR, ORFS_FLOW_DIR, INSTALL_PATH = prepare_ray_server(args) if args.mode == "tune": best_params = set_best_params(args.platform, args.design) - search_algo = set_algorithm(args.experiment, config_dict) + search_algo = set_algorithm( + args.algorithm, + args.experiment, + best_params, + args.seed, + args.perturbation, + args.jobs, + config_dict, + ) TrainClass = set_training_class(args.eval) # PPAImprov requires a reference file to compute training scores. if args.eval == "ppa-improv": - reference = PPAImprov.read_metrics(args.reference) + reference = read_metrics(args.reference, args.stop_stage) tune_args = dict( name=args.experiment, @@ -1061,10 +615,10 @@ def sweep(): mode="min", num_samples=args.samples, fail_fast=False, - local_dir=LOCAL_DIR, + storage_path=LOCAL_DIR, resume=args.resume, stop={"training_iteration": args.iterations}, - resources_per_trial={"cpu": args.resources_per_trial}, + resources_per_trial={"cpu": os.cpu_count() / args.jobs}, log_to_file=["trail-out.log", "trail-err.log"], trial_name_creator=lambda x: f"variant-{x.trainable_name}-{x.trial_id}-ray", trial_dirname_creator=lambda x: f"variant-{x.trainable_name}-{x.trial_id}-ray", @@ -1084,8 +638,12 @@ def sweep(): print(f"[INFO TUN-0002] Best parameters found: {analysis.best_config}") # if all runs have failed - if analysis.best_result["minimum"] == ERROR_METRIC: + if analysis.best_result[METRIC] == ERROR_METRIC: print("[ERROR TUN-0016] No successful runs found.") - sys.exit(1) + sys.exit(16) elif args.mode == "sweep": sweep() + + +if __name__ == "__main__": + main() diff --git a/tools/AutoTuner/src/autotuner/utils.py b/tools/AutoTuner/src/autotuner/utils.py new file mode 100644 index 0000000000..61aebb3390 --- /dev/null +++ b/tools/AutoTuner/src/autotuner/utils.py @@ -0,0 +1,656 @@ +############################################################################# +## +## BSD 3-Clause License +## +## Copyright (c) 2019, The Regents of the University of California +## All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################### + +import glob +import json +import os +import re +import yaml +import subprocess +import sys +import uuid +import time +from multiprocessing import cpu_count +from datetime import datetime + +import numpy as np +import ray + +# Default scheme of a SDC constraints file +SDC_TEMPLATE = """ +set clk_name core_clock +set clk_port_name clk +set clk_period 2000 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +""" +# Name of the SDC file with constraints +CONSTRAINTS_SDC = "constraint.sdc" +# Name of the TCL script run before routing +FASTROUTE_TCL = "fastroute.tcl" +DATE = datetime.now().strftime("%Y-%m-%d-%H-%M-%S") + + +def write_sdc(variables, path, sdc_original, constraints_sdc): + """ + Create a SDC file with parameters for current tuning iteration. + """ + # Handle case where the reference file does not exist + if sdc_original == "": + print("[ERROR TUN-0020] No SDC reference file provided.") + sys.exit(1) + new_file = sdc_original + for key, value in variables.items(): + if key == "CLK_PERIOD": + if new_file.find("set clk_period") != -1: + new_file = re.sub( + r"set clk_period .*\n(.*)", f"set clk_period {value}\n\\1", new_file + ) + else: + new_file = re.sub( + r"-period [0-9\.]+ (.*)", f"-period {value} \\1", new_file + ) + new_file = re.sub(r"-waveform [{}\s0-9\.]+[\s|\n]", "", new_file) + elif key == "UNCERTAINTY": + if new_file.find("set uncertainty") != -1: + new_file = re.sub( + r"set uncertainty .*\n(.*)", + f"set uncertainty {value}\n\\1", + new_file, + ) + else: + new_file += f"\nset uncertainty {value}\n" + elif key == "IO_DELAY": + if new_file.find("set io_delay") != -1: + new_file = re.sub( + r"set io_delay .*\n(.*)", f"set io_delay {value}\n\\1", new_file + ) + else: + new_file += f"\nset io_delay {value}\n" + else: + print( + f"[WARN TUN-0025] {key} variable not supported in context of SDC files" + ) + continue + file_name = path + f"/{constraints_sdc}" + with open(file_name, "w") as file: + file.write(new_file) + return file_name + + +def write_fast_route(variables, path, platform, fr_original, fastroute_tcl): + """ + Create a FastRoute Tcl file with parameters for current tuning iteration. + """ + # Handle case where the reference file does not exist (asap7 doesn't have reference) + if fr_original == "" and platform != "asap7": + print("[ERROR TUN-0021] No FastRoute Tcl reference file provided.") + sys.exit(1) + layer_cmd = "set_global_routing_layer_adjustment" + new_file = fr_original + # This is part of the defaults when no FASTROUTE_TCL is provided + if len(new_file) == 0: + new_file = "set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)" + for key, value in variables.items(): + if key.startswith("LAYER_ADJUST"): + layer = key.lstrip("LAYER_ADJUST") + # If there is no suffix (i.e., layer name) apply adjust to all + # layers. + if layer == "": + new_file += "\nset_global_routing_layer_adjustment" + new_file += " $::env(MIN_ROUTING_LAYER)" + new_file += "-$::env(MAX_ROUTING_LAYER)" + new_file += f" {value}" + elif re.search(f"{layer_cmd}.*{layer}", new_file): + new_file = re.sub( + f"({layer_cmd}.*{layer}).*\n(.*)", f"\\1 {value}\n\\2", new_file + ) + else: + new_file += f"\n{layer_cmd} {layer} {value}\n" + elif key == "GR_SEED": + new_file += f"\nset_global_routing_random -seed {value}\n" + else: + print( + f"[WARN TUN-0028] {key} variable not supported in context of FastRoute TCL files" + ) + continue + file_name = path + f"/{fastroute_tcl}" + with open(file_name, "w") as file: + file.write(new_file) + return file_name + + +def parse_flow_variables(base_dir, platform): + """ + Parse the flow variables from source + - Code: Makefile `vars` target output + + TODO: Tests. + + Output: + - flow_variables: set of flow variables + """ + # first, generate vars.tcl + makefile_path = os.path.join(base_dir, "flow") + result = subprocess.run( + ["make", "-C", makefile_path, "vars", f"PLATFORM={platform}"], + capture_output=True, + ) + if result.returncode != 0: + print(f"[ERROR TUN-0018] Makefile failed with error code {result.returncode}.") + sys.exit(1) + if not os.path.exists(os.path.join(makefile_path, "vars.tcl")): + print("[ERROR TUN-0019] Makefile did not generate vars.tcl.") + sys.exit(1) + + # for code parsing, you need to parse from both scripts and vars.tcl file. + pattern = r"(?:::)?env\((.*?)\)" + files = glob.glob(os.path.join(makefile_path, "scripts/*.tcl")) + files.append(os.path.join(makefile_path, "vars.tcl")) + variables = set() + for file in files: + with open(file) as fp: + matches = re.findall(pattern, fp.read()) + for match in matches: + for variable in match.split("\n"): + variables.add(variable.strip().upper()) + return variables + + +def parse_tunable_variables(): + """ + Parse the tunable variables from variables.yaml + TODO: Tests. + """ + cur_path = os.path.dirname(os.path.realpath(__file__)) + vars_path = os.path.join(cur_path, "../../../../flow/scripts/variables.yaml") + + # Read from variables.yaml and get variables with tunable = 1 + with open(vars_path) as file: + result = yaml.safe_load(file) + variables = {key for key, value in result.items() if value.get("tunable", 0) == 1} + return variables + + +def parse_config( + config, + base_dir, + platform, + sdc_original, + constraints_sdc, + fr_original, + fastroute_tcl, + path=os.getcwd(), +): + """ + Parse configuration received from tune into make variables. + """ + options = "" + sdc = {} + fast_route = {} + flow_variables = parse_tunable_variables() + for key, value in config.items(): + # Keys that begin with underscore need special handling. + if key.startswith("_"): + # Variables to be injected into fastroute.tcl + if key.startswith("_FR_"): + fast_route[key[4:]] = value + # Variables to be injected into constraints.sdc + elif key.startswith("_SDC_"): + sdc[key[5:]] = value + # Special substitution cases + elif key == "_PINS_DISTANCE": + options += f' PLACE_PINS_ARGS="-min_distance {value}"' + elif key == "_SYNTH_FLATTEN": + print( + "[WARNING TUN-0013] Non-flatten the designs are not " + "fully supported, ignoring _SYNTH_FLATTEN parameter." + ) + # Default case is VAR=VALUE + else: + # Sanity check: ignore all flow variables that are not tunable + if key not in flow_variables: + print(f"[ERROR TUN-0017] Variable {key} is not tunable.") + sys.exit(1) + options += f" {key}={value}" + if sdc: + write_sdc(sdc, path, sdc_original, constraints_sdc) + options += f" SDC_FILE={path}/{constraints_sdc}" + if fast_route: + write_fast_route(fast_route, path, platform, fr_original, fastroute_tcl) + options += f" FASTROUTE_TCL={path}/{fastroute_tcl}" + return options + + +def run_command( + args, cmd, timeout=None, stderr_file=None, stdout_file=None, fail_fast=False +): + """ + Wrapper for subprocess.run + Allows to run shell command, control print and exceptions. + """ + process = subprocess.run( + cmd, timeout=timeout, capture_output=True, text=True, check=False, shell=True + ) + if stderr_file is not None and process.stderr != "": + with open(stderr_file, "a") as file: + file.write(f"\n\n{cmd}\n{process.stderr}") + if stdout_file is not None and process.stdout != "": + with open(stdout_file, "a") as file: + file.write(f"\n\n{cmd}\n{process.stdout}") + if args.verbose >= 1: + print(process.stderr) + if args.verbose >= 2: + print(process.stdout) + + if fail_fast and process.returncode != 0: + raise RuntimeError + + +def openroad( + args, + base_dir, + parameters, + flow_variant, + install_path=None, +): + """ + Run OpenROAD-flow-scripts with a given set of parameters. + """ + # Make sure path ends in a slash, i.e., is a folder + flow_variant = f"{args.experiment}/{flow_variant}" + log_path = os.path.abspath( + os.path.join(base_dir, f"flow/logs/{args.platform}/{args.design}", flow_variant) + ) + report_path = os.path.abspath( + os.path.join( + base_dir, f"flow/reports/{args.platform}/{args.design}", flow_variant + ) + ) + results_path = os.path.abspath( + os.path.join( + base_dir, f"flow/results/{args.platform}/{args.design}", flow_variant + ) + ) + os.makedirs(log_path, exist_ok=True) + os.makedirs(report_path, exist_ok=True) + os.makedirs(results_path, exist_ok=True) + + if install_path is None: + install_path = os.path.join(base_dir, "tools/install") + + export_command = f"export PATH={install_path}/OpenROAD/bin" + export_command += f":{install_path}/yosys/bin:$PATH" + export_command += " && " + + make_command = export_command + make_command += f"make -C {base_dir}/flow DESIGN_CONFIG=designs/" + make_command += f"{args.platform}/{args.design}/config.mk" + make_command += f" PLATFORM={args.platform}" + make_command += f" FLOW_VARIANT={flow_variant} {parameters}" + make_command += " EQUIVALENCE_CHECK=0" + make_command += f" NUM_CORES={args.openroad_threads} SHELL=bash" + if args.stop_stage != "finish": + make_command += f" {args.stop_stage}" + run_command( + args, + make_command, + timeout=args.timeout, + stderr_file=os.path.join(log_path, "error-make-finish.log"), + stdout_file=os.path.join(log_path, "make-finish-stdout.log"), + ) + + metrics_file = os.path.abspath(os.path.join(log_path, "metrics.json")) + metrics_command = export_command + metrics_command += f"{base_dir}/flow/util/genMetrics.py -x" + metrics_command += f" -v {flow_variant}" + metrics_command += f" -d {args.design}" + metrics_command += f" -p {args.platform}" + metrics_command += f" --logs {log_path}" + metrics_command += f" --reports {report_path}" + metrics_command += f" --results {results_path}" + metrics_command += f" -o {metrics_file}" + run_command( + args, + metrics_command, + stderr_file=os.path.join(log_path, "error-metrics.log"), + stdout_file=os.path.join(log_path, "metrics-stdout.log"), + ) + + return metrics_file + + +def read_metrics(file_name, stop_stage): + """ + Collects metrics to evaluate the user-defined objective function. + + stop_stage indicates the last stage executed, so get most of the metrics + from that stage. The default stop stage is "finish". But if the run stops + before "finish", then no need to extract the metrics from the route stage, + so set them to 0 + """ + with open(file_name) as file: + data = json.load(file) + clk_period = 9999999 + worst_slack = "ERR" + total_power = "ERR" + core_util = "ERR" + final_util = "ERR" + design_area = "ERR" + die_area = "ERR" + core_area = "ERR" + if stop_stage != "finish": + num_drc = wirelength = 0 + else: + num_drc = wirelength = "ERR" + for stage_name, value in data.items(): + if stage_name == "constraints" and len(value["clocks__details"]) > 0: + clk_period = float(value["clocks__details"][0].split()[1]) + if stage_name == "floorplan" and "design__instance__utilization" in value: + core_util = value["design__instance__utilization"] + if stage_name == "detailedroute" and "route__drc_errors" in value: + num_drc = value["route__drc_errors"] + if stage_name == "detailedroute" and "route__wirelength" in value: + wirelength = value["route__wirelength"] + if stage_name == stop_stage and "timing__setup__ws" in value: + worst_slack = value["timing__setup__ws"] + if stage_name == stop_stage and "power__total" in value: + total_power = value["power__total"] + if stage_name == stop_stage and "design__instance__utilization" in value: + final_util = value["design__instance__utilization"] + if stage_name == stop_stage and "design__instance__area" in value: + design_area = value["design__instance__area"] + if stage_name == stop_stage and "design__core__area" in value: + core_area = value["design__core__area"] + if stage_name == stop_stage and "design__die__area" in value: + die_area = value["design__die__area"] + ret = { + "clk_period": clk_period, + "worst_slack": worst_slack, + "total_power": total_power, + "core_util": core_util, + "final_util": final_util, + "design_area": design_area, + "core_area": core_area, + "die_area": die_area, + "wirelength": wirelength, + "num_drc": num_drc, + } + return ret + + +def read_config(file_name, mode, algorithm): + """ + Please consider inclusive, exclusive + Most type uses [min, max) + But, Quantization makes the upper bound inclusive. + e.g., qrandint and qlograndint uses [min, max] + step value is used for quantized type (e.g., quniform). Otherwise, write 0. + When min==max, it means the constant value + """ + + def read(path): + # if file path does not exist, return empty string + print(os.path.abspath(path)) + if not os.path.isfile(os.path.abspath(path)): + return "" + with open(os.path.abspath(path), "r") as file: + ret = file.read() + return ret + + def read_sweep(this): + return [*this["minmax"], this["step"]] + + def apply_condition(config, data): + from ray import tune + import random + + # TODO: tune.sample_from only supports random search algorithm. + # To make conditional parameter for the other algorithms, different + # algorithms should take different methods (will be added) + if algorithm != "random": + return config + dp_pad_min = data["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"]["minmax"][0] + dp_pad_step = data["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"]["step"] + if dp_pad_step == 1: + config["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"] = tune.sample_from( + lambda spec: np.random.randint( + dp_pad_min, spec.config.CELL_PAD_IN_SITES_GLOBAL_PLACEMENT + 1 + ) + ) + if dp_pad_step > 1: + config["CELL_PAD_IN_SITES_DETAIL_PLACEMENT"] = tune.sample_from( + lambda spec: random.randrange( + dp_pad_min, + spec.config.CELL_PAD_IN_SITES_GLOBAL_PLACEMENT + 1, + dp_pad_step, + ) + ) + return config + + def read_tune(this): + from ray import tune + + min_, max_ = this["minmax"] + if min_ == max_: + # Returning a choice of a single element allow pbt algorithm to + # work. pbt does not accept single values as tunable. + return tune.choice([min_, max_]) + if this["type"] == "int": + if this["step"] == 1: + return tune.randint(min_, max_) + return tune.choice(np.ndarray.tolist(np.arange(min_, max_, this["step"]))) + if this["type"] == "float": + if this["step"] == 0: + return tune.uniform(min_, max_) + return tune.choice(np.ndarray.tolist(np.arange(min_, max_, this["step"]))) + return None + + def read_tune_ax(name, this): + """ + Ax format: https://ax.dev/versions/0.3.7/api/service.html + """ + from ray import tune + + dict_ = dict(name=name) + if "minmax" not in this: + return None + min_, max_ = this["minmax"] + if min_ == max_: + dict_["type"] = "fixed" + dict_["value"] = min_ + elif this["type"] == "int": + if this["step"] == 1: + dict_["type"] = "range" + dict_["bounds"] = [min_, max_] + dict_["value_type"] = "int" + else: + dict_["type"] = "choice" + dict_["values"] = tune.randint(min_, max_, this["step"]) + dict_["value_type"] = "int" + elif this["type"] == "float": + if this["step"] == 1: + dict_["type"] = "choice" + dict_["values"] = tune.choice( + np.ndarray.tolist(np.arange(min_, max_, this["step"])) + ) + dict_["value_type"] = "float" + else: + dict_["type"] = "range" + dict_["bounds"] = [min_, max_] + dict_["value_type"] = "float" + return dict_ + + def read_tune_pbt(name, this): + """ + PBT format: https://docs.ray.io/en/releases-2.9.3/tune/examples/pbt_guide.html + Note that PBT does not support step values. + """ + from ray import tune + + if "minmax" not in this: + return None + min_, max_ = this["minmax"] + if min_ == max_: + return tune.choice([min_, max_]) + if this["type"] == "int": + return tune.randint(min_, max_) + if this["type"] == "float": + return tune.uniform(min_, max_) + + # Check file exists and whether it is a valid JSON file. + assert os.path.isfile(file_name), f"File {file_name} not found." + try: + with open(file_name) as file: + data = json.load(file) + except json.JSONDecodeError: + raise ValueError(f"Invalid JSON file: {file_name}") + sdc_file = "" + fr_file = "" + if mode == "tune" and algorithm == "ax": + config = list() + else: + config = dict() + for key, value in data.items(): + if key == "best_result": + continue + if key == "_SDC_FILE_PATH" and value != "": + if sdc_file != "": + print("[WARNING TUN-0004] Overwriting SDC base file.") + sdc_file = read(f"{os.path.dirname(file_name)}/{value}") + continue + if key == "_FR_FILE_PATH" and value != "": + if fr_file != "": + print("[WARNING TUN-0005] Overwriting FastRoute base file.") + fr_file = read(f"{os.path.dirname(file_name)}/{value}") + continue + if not isinstance(value, dict): + # To take care of empty values like _FR_FILE_PATH + if mode == "tune" and algorithm == "ax": + param_dict = read_tune_ax(key, value) + if param_dict: + config.append(param_dict) + elif mode == "tune" and algorithm == "pbt": + param_dict = read_tune_pbt(key, value) + if param_dict: + config[key] = param_dict + else: + config[key] = value + elif mode == "sweep": + config[key] = read_sweep(value) + elif mode == "tune" and algorithm == "ax": + config.append(read_tune_ax(key, value)) + elif mode == "tune" and algorithm == "pbt": + config[key] = read_tune_pbt(key, value) + elif mode == "tune": + config[key] = read_tune(value) + if mode == "tune": + config = apply_condition(config, data) + return config, sdc_file, fr_file + + +def prepare_ray_server(args): + """ + Prepares Ray server and returns basic directories. + """ + # Connect to remote Ray server if any, otherwise will run locally + if args.server is not None: + # Connect to ray server before first remote execution. + ray.init(f"ray://{args.server}:{args.port}") + print("[INFO TUN-0001] Connected to Ray server.") + # Common variables used for local and remote runs. + orfs_dir = getattr(args, "orfs", None) + orfs_flow_dir = os.path.abspath( + os.path.join(orfs_dir, "flow") + if orfs_dir + else os.path.join(os.path.dirname(__file__), "../../../../flow") + ) + local_dir = f"logs/{args.platform}/{args.design}" + local_dir = os.path.join(orfs_flow_dir, local_dir) + install_path = os.path.abspath(os.path.join(orfs_flow_dir, "../tools/install")) + return local_dir, orfs_flow_dir, install_path + + +@ray.remote +def openroad_distributed( + args, + repo_dir, + config, + sdc_original, + fr_original, + install_path, + variant=None, +): + """Simple wrapper to run openroad distributed with Ray.""" + config = parse_config( + config=config, + base_dir=repo_dir, + platform=args.platform, + sdc_original=sdc_original, + constraints_sdc=CONSTRAINTS_SDC, + fr_original=fr_original, + fastroute_tcl=FASTROUTE_TCL, + ) + if variant is None: + variant = config.replace(" ", "_").replace("=", "_") + t = time.time() + metric_file = openroad( + args=args, + base_dir=repo_dir, + parameters=config, + flow_variant=f"{uuid.uuid4()}-{variant}" if variant else f"{uuid.uuid4()}", + install_path=install_path, + ) + duration = time.time() - t + return metric_file, duration + + +@ray.remote +def consumer(queue): + """consumer""" + while not queue.empty(): + next_item = queue.get() + name = next_item[1] + print(f"[INFO TUN-0007] Scheduling run for parameter {name}.") + ray.get(openroad_distributed.remote(*next_item)) + print(f"[INFO TUN-0008] Finished run for parameter {name}.") diff --git a/tools/AutoTuner/test/autotuner_test_utils.py b/tools/AutoTuner/test/autotuner_test_utils.py new file mode 100644 index 0000000000..3058bb6c4a --- /dev/null +++ b/tools/AutoTuner/test/autotuner_test_utils.py @@ -0,0 +1,61 @@ +#!/usr/bin/env python3 +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + +import os + +# Accepted RC: success and failed with no valid results. +accepted_rc = [0, 16] + + +class AutoTunerTestUtils: + @staticmethod + def get_exec_cmd(): + """ + Returns the execution command based on whether this is a coverage run or + not. + + Note that you need to run coverage combine after the runs complete to + get the coverage of the parent plus the child invocations + """ + + if "COVERAGE_RUN" in os.environ: + exec = "coverage run --parallel-mode --omit=*/site-packages/*,*/dist-packages/*" + else: # pragma: no cover + exec = "python3" + return exec + " -m autotuner.distributed" + + +if __name__ == "__main__": # pragma: no cover + print(AutoTunerTestUtils.get_exec_cmd()) diff --git a/tools/AutoTuner/test/ref_file_check.py b/tools/AutoTuner/test/ref_file_check.py index e0401693c4..bb02a868cd 100644 --- a/tools/AutoTuner/test/ref_file_check.py +++ b/tools/AutoTuner/test/ref_file_check.py @@ -1,38 +1,109 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + import unittest import subprocess import os +from .autotuner_test_utils import AutoTunerTestUtils cur_dir = os.path.dirname(os.path.abspath(__file__)) -src_dir = os.path.join(cur_dir, "../src/autotuner") +src_dir = os.path.join(cur_dir, "../src") orfs_dir = os.path.join(cur_dir, "../../../flow") os.chdir(src_dir) class RefFileCheck(unittest.TestCase): - # only test 1 platform/design. - platform = "asap7" - design = "gcd" + """ + Tests situations where a referenced file (SDC or FastRoute) is not + defined in the AutoTuner config + """ def setUp(self): - configs = [ - "../../test/files/no_sdc_ref.json", - "../../test/files/no_fr_ref.json", - ] - self.commands = [ - f"python3 distributed.py" - f" --design {self.design}" - f" --platform {self.platform}" - f" --config {c}" - f" tune --samples 1" - for c in configs - ] - - # Make this a test case - def test_files(self): - for c in self.commands: - out = subprocess.run(c, shell=True) - failed = out.returncode != 0 - self.assertTrue(failed) + self._cur_dir = os.path.dirname(os.path.abspath(__file__)) + src_dir = os.path.join(self._cur_dir, "../src") + os.chdir(src_dir) + + self._exec = AutoTunerTestUtils.get_exec_cmd() + + def _execute_autotuner(self, platform, design, config_file, error_code=None): + full_path = os.path.abspath(os.path.join(self._cur_dir, config_file)) + + cmd = f"{self._exec} --design {design} --platform {platform} --config {full_path} tune --samples 1" + + out = subprocess.run(cmd, shell=True, text=True, capture_output=True) + failed = out.returncode != 0 + self.assertTrue(failed, f"AT run with {config_file} passed") + if error_code: + self.assertTrue( + error_code in out.stdout, + f"Didn't find error code {error_code} in output '{out.stdout}'", + ) + + def test_asap_gcd_no_sdc(self): + """ + Tests when SDC file is not defined, which is an error for all + platforms and designs + """ + + platform = "asap7" + design = "gcd" + config_file = "files/no_sdc_ref.json" + error_code = "[ERROR TUN-0020] No SDC reference" + self._execute_autotuner(platform, design, config_file, error_code) + + def test_asap_gcd_no_fr(self): + """ + Tests when FastRoute file is not defined, which is not an error for + asap platform. This test fails anyway + """ + + platform = "asap7" + design = "gcd" + config_file = "files/no_fr_ref.json" + self._execute_autotuner(platform, design, config_file) + + def test_ihp_gcd_no_fr(self): + """ + Tests when FastRoute file is not defined, which is not an error for + any non-asap7 platform. + """ + + platform = "ihp-sg13g2" + design = "gcd" + config_file = "files/no_fr_ref.json" + error_code = "[ERROR TUN-0021] No FastRoute Tcl" + self._execute_autotuner(platform, design, config_file, error_code) if __name__ == "__main__": diff --git a/tools/AutoTuner/test/resume_check.py b/tools/AutoTuner/test/resume_check.py new file mode 100644 index 0000000000..69eaec1f24 --- /dev/null +++ b/tools/AutoTuner/test/resume_check.py @@ -0,0 +1,125 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + +import unittest +import subprocess +import os +import time +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc + +from contextlib import contextmanager + +cur_dir = os.path.dirname(os.path.abspath(__file__)) +src_dir = os.path.join(cur_dir, "../src") +orfs_dir = os.path.join(cur_dir, "../../../flow") +os.chdir(src_dir) + + +@contextmanager +def managed_process(*args, **kwargs): + """ + Runs process and ensures it is killed when the context is exited. + """ + proc = subprocess.Popen(*args, **kwargs) + try: + yield proc + finally: + if proc.poll() is None: # If the process is still running + proc.kill() # Forcefully kill it + + +class ResumeCheck(unittest.TestCase): + # only test 1 platform/design. + platform = "asap7" + design = "gcd" + samples = 5 + iterations = 2 + + def setUp(self): + self.config = os.path.join( + orfs_dir, "designs", self.platform, self.design, "autotuner.json" + ) + self.jobs = self.samples + self.num_cpus = os.cpu_count() + + # How it works: Say we have 5 samples and 5 iterations. + # If we want to limit to only 5 trials (and avoid any parallelism magic by Ray) + # We can set resources_per_trial = NUM_CORES/5 = 3.2 (fractional resources_per_trial are allowed!) + + # Cast to 1 decimal place + res_per_trial = float("{:.1f}".format(self.num_cpus / self.samples)) + options = ["", "--resume"] + self.exec = AutoTunerTestUtils.get_exec_cmd() + self.commands = [ + f"{self.exec}" + f" --design {self.design}" + f" --platform {self.platform}" + f" --config {self.config}" + f" --jobs {self.jobs}" + f" --experiment test-resume" + f" tune --iterations {self.iterations} --samples {self.samples}" + f" --resources_per_trial {res_per_trial}" + f" {c}" + for c in options + ] + + def test_tune_resume(self): + # Goal is to first run the first config (without resume) and then run the second config (with resume) + # and check if the run is able to complete. + + # Run the first config asynchronously. + print("Running the first config") + with managed_process(self.commands[0], shell=True) as proc: + time.sleep(120) + + # Keep trying to stop the ray cluster until it is stopped + while 1: + proc = subprocess.run("ray status", shell=True) + no_nodes = proc.returncode != 0 + proc = subprocess.run("ray stop", shell=True) + successful = proc.returncode in accepted_rc + + if no_nodes and successful: + break + time.sleep(10) + + # Run the second config to completion + print("Running the second config") + proc = subprocess.run(self.commands[1], shell=True) + successful = proc.returncode in accepted_rc + self.assertTrue(successful) + + +if __name__ == "__main__": + unittest.main() diff --git a/tools/AutoTuner/test/smoke_test_algo_eval.py b/tools/AutoTuner/test/smoke_test_algo_eval.py index a695489b48..01fdc95403 100644 --- a/tools/AutoTuner/test/smoke_test_algo_eval.py +++ b/tools/AutoTuner/test/smoke_test_algo_eval.py @@ -1,11 +1,44 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + import unittest import subprocess import os +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) -src_dir = os.path.join(cur_dir, "../src/autotuner") orfs_dir = os.path.join(cur_dir, "../../../flow") -os.chdir(src_dir) class BaseAlgoEvalSmokeTest(unittest.TestCase): @@ -21,8 +54,9 @@ def setUp(self): _algo = ["hyperopt", "ax", "optuna", "pbt", "random"] _eval = ["default", "ppa-improv"] self.matrix = [(a, e) for a in _algo for e in _eval] + self.exec = AutoTunerTestUtils.get_exec_cmd() self.commands = [ - f"python3 distributed.py" + f"{self.exec}" f" --design {self.design}" f" --platform {self.platform}" f" --experiment {self.experiment}" @@ -34,59 +68,41 @@ def setUp(self): ] def make_base(self): - os.chdir(orfs_dir) commands = [ - f"make DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk clean_all", - f"make DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk EQUIVALENCE_CHECK=0", - f"make DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk update_metadata_autotuner", + f"make -C {orfs_dir} DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk clean_all", + f"make -C {orfs_dir} DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk EQUIVALENCE_CHECK=0", + f"make -C {orfs_dir} DESIGN_CONFIG=./designs/{self.platform}/{self.design}/config.mk update_metadata_autotuner", ] for command in commands: - out = subprocess.run(command, shell=True, check=True) - self.assertTrue(out.returncode == 0) - os.chdir(src_dir) - - -class ASAP7AlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): - platform = "asap7" - design = "gcd" + out = subprocess.run(command, shell=True) + self.assertTrue(out.returncode in accepted_rc) def test_algo_eval(self): + if not (self.platform and self.design): + raise unittest.SkipTest("Platform and design have to be defined") # Run `make` to get baseline metrics (metadata-base-ok.json) self.make_base() for command in self.commands: print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) -class IHPSG13G2AlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): - platform = "ihp-sg13g2" +class asap7AlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): + platform = "asap7" design = "gcd" - def test_algo_eval(self): - # Run `make` to get baseline metrics (metadata-base-ok.json) - self.make_base() - for command in self.commands: - print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) + +class ihpsg13g2AlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): + platform = "ihp-sg13g2" + design = "gcd" -class SKY130HDAlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): +class sky130hdAlgoEvalSmokeTest(BaseAlgoEvalSmokeTest): platform = "sky130hd" design = "gcd" - def test_algo_eval(self): - # Run `make` to get baseline metrics (metadata-base-ok.json) - self.make_base() - for command in self.commands: - print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - if __name__ == "__main__": unittest.main() diff --git a/tools/AutoTuner/test/smoke_test_sample_iteration.py b/tools/AutoTuner/test/smoke_test_sample_iteration.py index f49c22a088..8e3a6843d1 100644 --- a/tools/AutoTuner/test/smoke_test_sample_iteration.py +++ b/tools/AutoTuner/test/smoke_test_sample_iteration.py @@ -1,10 +1,43 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + import unittest import subprocess import os +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) -src_dir = os.path.join(cur_dir, "../src/autotuner") -os.chdir(src_dir) class BaseSampleIterationSmokeTest(unittest.TestCase): @@ -18,8 +51,9 @@ def setUp(self): ) self.experiment = f"smoke-test-sample-iteration-{self.platform}" self.matrix = [(5, 1), (1, 5), (2, 2), (1, 1)] + self.exec = AutoTunerTestUtils.get_exec_cmd() self.commands = [ - f"python3 distributed.py" + f"{self.exec}" f" --design {self.design}" f" --platform {self.platform}" f" --experiment {self.experiment}" @@ -28,42 +62,30 @@ def setUp(self): for s, i in self.matrix ] - -class ASAP7SampleIterationSmokeTest(BaseSampleIterationSmokeTest): - platform = "asap7" - design = "gcd" - def test_sample_iteration(self): + if not (self.platform and self.design): + raise unittest.SkipTest("Platform and design have to be defined") for command in self.commands: print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 + out = subprocess.run(command, shell=True) + successful = out.returncode in accepted_rc self.assertTrue(successful) -class SKY130HDSampleIterationSmokeTest(BaseSampleIterationSmokeTest): - platform = "sky130hd" +class asap7SampleIterationSmokeTest(BaseSampleIterationSmokeTest): + platform = "asap7" design = "gcd" - def test_sample_iteration(self): - for command in self.commands: - print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) +class sky130hdSampleIterationSmokeTest(BaseSampleIterationSmokeTest): + platform = "sky130hd" + design = "gcd" -class IHPSG13G2SampleIterationSmokeTest(BaseSampleIterationSmokeTest): + +class ihpsg13g2SampleIterationSmokeTest(BaseSampleIterationSmokeTest): platform = "ihp-sg13g2" design = "gcd" - def test_sample_iteration(self): - for command in self.commands: - print(command) - out = subprocess.run(command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - if __name__ == "__main__": unittest.main() diff --git a/tools/AutoTuner/test/smoke_test_sweep.py b/tools/AutoTuner/test/smoke_test_sweep.py index 7a1b013911..eb790441ff 100644 --- a/tools/AutoTuner/test/smoke_test_sweep.py +++ b/tools/AutoTuner/test/smoke_test_sweep.py @@ -1,11 +1,44 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + import unittest import subprocess import os import json +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) -src_dir = os.path.join(cur_dir, "../src/autotuner") -os.chdir(src_dir) class BaseSweepSmokeTest(unittest.TestCase): @@ -13,7 +46,9 @@ class BaseSweepSmokeTest(unittest.TestCase): design = "" def setUp(self): - self.config = "distributed-sweep-example.json" + self.config = os.path.abspath( + os.path.join(cur_dir, "../src/autotuner/distributed-sweep-example.json") + ) # make sure this json only has 1 key called "CTS_CLUSTER_SIZE" and 4 possible values with open(self.config) as f: contents = json.load(f) @@ -30,8 +65,9 @@ def setUp(self): core = os.cpu_count() self.jobs = 4 if core >= 4 else core self.experiment = f"smoke-test-sweep-{self.platform}" + self.exec = AutoTunerTestUtils.get_exec_cmd() self.command = ( - "python3 distributed.py" + f"{self.exec}" f" --design {self.design}" f" --platform {self.platform}" f" --experiment {self.experiment}" @@ -41,40 +77,27 @@ def setUp(self): ) def test_sweep(self): - raise NotImplementedError( - "This method needs to be implemented in the derivative classes." - ) + if not (self.platform and self.design): + raise unittest.SkipTest("Platform and design have to be defined") + out = subprocess.run(self.command, shell=True) + successful = out.returncode in accepted_rc + self.assertTrue(successful) -class ASAP7SweepSmokeTest(BaseSweepSmokeTest): +class asap7SweepSmokeTest(BaseSweepSmokeTest): platform = "asap7" design = "gcd" - def test_sweep(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - -class SKY130HDSweepSmokeTest(BaseSweepSmokeTest): +class sky130hdSweepSmokeTest(BaseSweepSmokeTest): platform = "sky130hd" design = "gcd" - def test_sweep(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - -class IHPSG13G2SweepSmokeTest(BaseSweepSmokeTest): +class ihpsg13g2SweepSmokeTest(BaseSweepSmokeTest): platform = "ihp-sg13g2" design = "gcd" - def test_sweep(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - if __name__ == "__main__": unittest.main() diff --git a/tools/AutoTuner/test/smoke_test_tune.py b/tools/AutoTuner/test/smoke_test_tune.py index 9710416745..89cc83bf8b 100644 --- a/tools/AutoTuner/test/smoke_test_tune.py +++ b/tools/AutoTuner/test/smoke_test_tune.py @@ -1,10 +1,43 @@ +############################################################################# +## +## Copyright (c) 2024, Precision Innovations Inc. +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +############################################################################### + import unittest import subprocess import os +from .autotuner_test_utils import AutoTunerTestUtils, accepted_rc cur_dir = os.path.dirname(os.path.abspath(__file__)) -src_dir = os.path.join(cur_dir, "../src/autotuner") -os.chdir(src_dir) class BaseTuneSmokeTest(unittest.TestCase): @@ -17,8 +50,9 @@ def setUp(self): f"../../../flow/designs/{self.platform}/{self.design}/autotuner.json", ) self.experiment = f"smoke-test-tune-{self.platform}" + self.exec = AutoTunerTestUtils.get_exec_cmd() self.command = ( - "python3 distributed.py" + f"{self.exec}" f" --design {self.design}" f" --platform {self.platform}" f" --experiment {self.experiment}" @@ -27,40 +61,27 @@ def setUp(self): ) def test_tune(self): - raise NotImplementedError( - "This method needs to be implemented in the derivative classes." - ) + if not (self.platform and self.design): + raise unittest.SkipTest("Platform and design have to be defined") + out = subprocess.run(self.command, shell=True) + successful = out.returncode in accepted_rc + self.assertTrue(successful) -class ASAP7TuneSmokeTest(BaseTuneSmokeTest): +class asap7TuneSmokeTest(BaseTuneSmokeTest): platform = "asap7" design = "gcd" - def test_tune(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - -class SKY130HDTuneSmokeTest(BaseTuneSmokeTest): +class sky130hdTuneSmokeTest(BaseTuneSmokeTest): platform = "sky130hd" design = "gcd" - def test_tune(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - -class IHPSG13G2TuneSmokeTest(BaseTuneSmokeTest): +class ihpsg13g2TuneSmokeTest(BaseTuneSmokeTest): platform = "ihp-sg13g2" design = "gcd" - def test_tune(self): - out = subprocess.run(self.command, shell=True, check=True) - successful = out.returncode == 0 - self.assertTrue(successful) - if __name__ == "__main__": unittest.main() diff --git a/tools/OpenROAD b/tools/OpenROAD index 0b348c1932..06d4a26e7a 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit 0b348c1932f42f2b238ec67caad461e16618ad18 +Subproject commit 06d4a26e7a5fd3dc14fb5517f846d2dcb5cbd14b diff --git a/tools/yosys b/tools/yosys index 647d61dd92..9ed031ddd5 160000 --- a/tools/yosys +++ b/tools/yosys @@ -1 +1 @@ -Subproject commit 647d61dd9212365a3cd44db219660b8f90b95cbd +Subproject commit 9ed031ddd588442f22be13ce608547a5809b62f0 diff --git a/tools/yosys-slang b/tools/yosys-slang new file mode 160000 index 0000000000..f9aad2dae5 --- /dev/null +++ b/tools/yosys-slang @@ -0,0 +1 @@ +Subproject commit f9aad2dae584fa5eb224d55f1eba483f86480516 diff --git a/yamlfix.toml b/yamlfix.toml new file mode 100644 index 0000000000..2374071179 --- /dev/null +++ b/yamlfix.toml @@ -0,0 +1,11 @@ +explicit_start = true +line_length = 80 +preserve_quotes = true +quote_representation = "'" +section_whitelines = 0 +sequence_style = "block_style" +comments_min_spaces_from_content = 2 +allow_duplicate_keys = false +indent_mapping = 2 +indent_offset = 2 +indent_sequence = 4